commit aeaa4039d03d729eca1ab12b5cbd195d6e97e68c
author Ash Charles <ashcharles@gmail.com> Wed Jul 24 12:22:35 2013 -0700
committer Tom Rini <trini@ti.com> Thu Aug 15 08:51:11 2013 -0400
tree b6e694c626290296b3676c53c988c2386c440ef3
parent 9f32a9e8f3f997daa2cc9f714718f0215cea7989

omap: overo: Use 200MHz SDRC timings for revision 1, 2 & 3 boards

Gumstix uses 200Mhz RAM on revision 1, 2 & 3 COMs, so use 200MHz
timings rather than 165MHz.  Based on 6cf8bf44b1f8550e12f7f2a16e01890e5de8443d

Signed-off-by: Ash Charles <ashcharles@gmail.com>

board/overo/overo.c

diff --git a/board/overo/overo.c b/board/overo/overo.c
index 92d3de4..aace42a 100644
--- a/board/overo/overo.c
+++ b/board/overo/overo.c
@@ -142,16 +142,16 @@
 		timings->rfr_ctrl = SDP_3430_SDRC_RFR_CTRL_165MHz;
 		break;
 	case REVISION_1: /* Micron 256MB/512MB, 1/2 banks of 256MB */
-		timings->mcfg = MICRON_V_MCFG_165(256 << 20);
-		timings->ctrla = MICRON_V_ACTIMA_165;
-		timings->ctrlb = MICRON_V_ACTIMB_165;
-		timings->rfr_ctrl = SDP_3430_SDRC_RFR_CTRL_165MHz;
+		timings->mcfg = MICRON_V_MCFG_200(256 << 20);
+		timings->ctrla = MICRON_V_ACTIMA_200;
+		timings->ctrlb = MICRON_V_ACTIMB_200;
+		timings->rfr_ctrl = SDP_3430_SDRC_RFR_CTRL_200MHz;
 		break;
 	case REVISION_2: /* Hynix 256MB/512MB, 1/2 banks of 256MB */
-		timings->mcfg = HYNIX_V_MCFG_165(256 << 20);
-		timings->ctrla = HYNIX_V_ACTIMA_165;
-		timings->ctrlb = HYNIX_V_ACTIMB_165;
-		timings->rfr_ctrl = SDP_3430_SDRC_RFR_CTRL_165MHz;
+		timings->mcfg = HYNIX_V_MCFG_200(256 << 20);
+		timings->ctrla = HYNIX_V_ACTIMA_200;
+		timings->ctrlb = HYNIX_V_ACTIMB_200;
+		timings->rfr_ctrl = SDP_3430_SDRC_RFR_CTRL_200MHz;
 		break;
 	case REVISION_3: /* Micron 512MB/1024MB, 1/2 banks of 512MB */
 		timings->mcfg = MCFG(512 << 20, 15);