ddr: marvell: only assert M_ODT[0] on write for a single CS
When using only a single DDR chip select only assert M_ODT[0] on write.
Do not assert it on read and do not assert M_ODT[1] at all. Also set
tODT_OFF_WR to 0x9 which contradicts the recommendation from the
functional spec but is what Marvell's binary training blob does and
seems to give better results when ODT is active during writes.
Signed-off-by: Chris Packham <judge.packham@gmail.com>
Signed-off-by: Stefan Roese <sr@denx.de>
diff --git a/drivers/ddr/marvell/a38x/ddr3_init.h b/drivers/ddr/marvell/a38x/ddr3_init.h
index 8cb0886..a4c75a9 100644
--- a/drivers/ddr/marvell/a38x/ddr3_init.h
+++ b/drivers/ddr/marvell/a38x/ddr3_init.h
@@ -183,7 +183,8 @@
extern u32 g_zpodt_ctrl;
extern u32 g_znodt_ctrl;
extern u32 g_dic;
-extern u32 g_odt_config;
+extern u32 g_odt_config_2cs;
+extern u32 g_odt_config_1cs;
extern u32 g_rtt_nom;
extern u8 debug_training_access;
diff --git a/drivers/ddr/marvell/a38x/ddr3_training.c b/drivers/ddr/marvell/a38x/ddr3_training.c
index e70ca4b..043143a 100644
--- a/drivers/ddr/marvell/a38x/ddr3_training.c
+++ b/drivers/ddr/marvell/a38x/ddr3_training.c
@@ -315,6 +315,7 @@
enum hws_access_type access_type = ACCESS_TYPE_UNICAST;
u32 data_read[MAX_INTERFACE_NUM];
struct hws_topology_map *tm = ddr3_get_topology_map();
+ u32 odt_config = g_odt_config_2cs;
DEBUG_TRAINING_IP(DEBUG_LEVEL_TRACE,
("Init_controller, do_mrs_phy=%d, is_ctrl64_bit=%d\n",
@@ -570,6 +571,9 @@
DUNIT_CONTROL_HIGH_REG,
(init_cntr_prm->msys_init << 7), (1 << 7)));
+ /* calculate number of CS (per interface) */
+ CHECK_STATUS(calc_cs_num
+ (dev_num, if_id, &cs_num));
timing = tm->interface_params[if_id].timing;
if (mode2_t != 0xff) {
@@ -578,9 +582,6 @@
/* Board topology map is forcing timing */
t2t = (timing == HWS_TIM_2T) ? 1 : 0;
} else {
- /* calculate number of CS (per interface) */
- CHECK_STATUS(calc_cs_num
- (dev_num, if_id, &cs_num));
t2t = (cs_num == 1) ? 0 : 1;
}
@@ -623,9 +624,11 @@
(1 << 11)));
/* Set Active control for ODT write transactions */
+ if (cs_num == 1)
+ odt_config = g_odt_config_1cs;
CHECK_STATUS(ddr3_tip_if_write
(dev_num, ACCESS_TYPE_MULTICAST,
- PARAM_NOT_CARE, 0x1494, g_odt_config,
+ PARAM_NOT_CARE, 0x1494, odt_config,
MASK_ALL_BITS));
}
} else {
@@ -1539,7 +1542,7 @@
CHECK_STATUS(ddr3_tip_if_write(dev_num, access_type,
if_id, ODT_TIMING_LOW,
val, 0xffff0));
- val = 0x71 | ((cwl_value - 1) << 8) | ((cwl_value + 5) << 12);
+ val = 0x91 | ((cwl_value - 1) << 8) | ((cwl_value + 5) << 12);
CHECK_STATUS(ddr3_tip_if_write(dev_num, access_type,
if_id, ODT_TIMING_HI_REG,
val, 0xffff));
@@ -1591,7 +1594,7 @@
CHECK_STATUS(ddr3_tip_if_write(dev_num, access_type, if_id,
ODT_TIMING_LOW, val, 0xffff0));
- val = 0x71 | ((cwl_value - 1) << 8) | ((cwl_value + 5) << 12);
+ val = 0x91 | ((cwl_value - 1) << 8) | ((cwl_value + 5) << 12);
CHECK_STATUS(ddr3_tip_if_write(dev_num, access_type, if_id,
ODT_TIMING_HI_REG, val, 0xffff));
if (odt_additional == 1) {
diff --git a/drivers/ddr/marvell/a38x/ddr3_training_static.c b/drivers/ddr/marvell/a38x/ddr3_training_static.c
index 5101f3f..b73bbf4 100644
--- a/drivers/ddr/marvell/a38x/ddr3_training_static.c
+++ b/drivers/ddr/marvell/a38x/ddr3_training_static.c
@@ -21,7 +21,8 @@
u32 g_znodt_data = 45; /* controller data - N ODT */
u32 g_zpodt_ctrl = 45; /* controller data - P ODT */
u32 g_znodt_ctrl = 45; /* controller data - N ODT */
-u32 g_odt_config = 0x120012;
+u32 g_odt_config_2cs = 0x120012;
+u32 g_odt_config_1cs = 0x10000;
u32 g_rtt_nom = 0x44;
u32 g_dic = 0x2;