OMAP4+: Handle sdram init after warm reset
EMIF and DDR device state are preserved in warmreset. Redoing the full
initialisation would cause unexpected behaviour. Do only partial
initialisation to account for frequency change.
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
Signed-off-by: R Sricharan <r.sricharan@ti.com>
Signed-off-by: Senthilvadivu Guruswamy <svadivu@ti.com>
diff --git a/arch/arm/cpu/armv7/omap-common/emif-common.c b/arch/arm/cpu/armv7/omap-common/emif-common.c
index 23cf619..edc63fa 100644
--- a/arch/arm/cpu/armv7/omap-common/emif-common.c
+++ b/arch/arm/cpu/armv7/omap-common/emif-common.c
@@ -990,7 +990,7 @@
return NULL;
/* Do the minimum init for mode register accesses */
- if (!running_from_sdram()) {
+ if (!(running_from_sdram() || warm_reset())) {
phy = get_ddr_phy_ctrl_1(get_sys_clk_freq() / 2, RL_BOOT);
writel(phy, &emif->emif_ddr_phy_ctrl_1);
}
@@ -1070,7 +1070,7 @@
* Changing the timing registers in EMIF can happen(going from one
* OPP to another)
*/
- if (!in_sdram) {
+ if (!(in_sdram || warm_reset())) {
if (omap_revision() != OMAP5432_ES1_0)
lpddr2_init(base, regs);
else
@@ -1242,7 +1242,7 @@
in_sdram = running_from_sdram();
debug("in_sdram = %d\n", in_sdram);
- if (!in_sdram) {
+ if (!(in_sdram || warm_reset())) {
if (omap_rev != OMAP5432_ES1_0)
bypass_dpll(&prcm->cm_clkmode_dpll_core);
else
@@ -1252,8 +1252,10 @@
do_sdram_init(EMIF1_BASE);
do_sdram_init(EMIF2_BASE);
- if (!in_sdram) {
+ if (!in_sdram)
dmm_init(DMM_BASE);
+
+ if (!(in_sdram || warm_reset())) {
emif_post_init_config(EMIF1_BASE);
emif_post_init_config(EMIF2_BASE);
}