| commit | ae5ed18156e0fb44a91c721d7ae8c33911a102b1 | [log] [tgz] |
|---|---|---|
| author | Wenyou Yang <wenyou.yang@microchip.com> | Fri Feb 09 11:34:51 2018 +0800 |
| committer | Tom Rini <trini@konsulko.com> | Fri Mar 16 07:30:04 2018 -0400 |
| tree | efe417a3aa1f19076069eb4138e31ffa8731a66b | |
| parent | 22cb237f35b4dabba90bc8fa6136f472ddcd69b5 [diff] |
clk: at91: add PLLADIV driver As said in the SAMA5D2 datasheet, the PLLA clock must be divided by 2 by writing the PLLADIV2 bit in PMC_MCKR, if the ratio between PCK and MCK is 3 (MDIV = 3). This is the purpose of the driver. Signed-off-by: Wenyou Yang <wenyou.yang@microchip.com>