tree 049a59419c5b3071168505cb745ce228290e655b
parent a9b87fd32805405219def910e9ad4a53e51ce398
author Kever Yang <kever.yang@rock-chips.com> 1512031879 +0800
committer Philipp Tomsich <philipp.tomsich@theobroma-systems.com> 1512078927 +0100

rockchip: rk3036: fix pll config for correct frequency

There is a fixed div-2 between PLL and clk_ddr/clk_ddrphy,
so we need to double to pll output and then ddr can work
in correct frequency.

Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
Acked-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>