Merge tag 'ti-v2021.04-rc1' of https://gitlab.denx.de/u-boot/custodians/u-boot-ti

- DM support for OMAP PWM backlight
- USB host mode support for AM654
- Minor SPI fixes
- Add support k2g ice board with 1GHz silicon
- Fix GTC programming for K3 devices
diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
index 6b5235e..95557d6 100644
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@ -1046,6 +1046,7 @@
 	select SPL_USE_TINY_PRINTF
 	select USE_PREBOOT
 	select SYS_RELOC_GD_ENV_ADDR
+	imply BOARD_LATE_INIT
 	imply CMD_DM
 	imply CMD_GPT
 	imply CMD_UBI if MTD_RAW_NAND
diff --git a/arch/arm/cpu/armv8/Makefile b/arch/arm/cpu/armv8/Makefile
index 93d26f9..f7b4a5e 100644
--- a/arch/arm/cpu/armv8/Makefile
+++ b/arch/arm/cpu/armv8/Makefile
@@ -27,6 +27,8 @@
 
 ifndef CONFIG_SPL_BUILD
 obj-$(CONFIG_ARMV8_SPIN_TABLE) += spin_table.o spin_table_v8.o
+else
+obj-$(CONFIG_ARCH_SUNXI) += fel_utils.o
 endif
 obj-$(CONFIG_$(SPL_)ARMV8_SEC_FIRMWARE_SUPPORT) += sec_firmware.o sec_firmware_asm.o
 
diff --git a/arch/arm/cpu/armv8/fel_utils.S b/arch/arm/cpu/armv8/fel_utils.S
new file mode 100644
index 0000000..9510dcd
--- /dev/null
+++ b/arch/arm/cpu/armv8/fel_utils.S
@@ -0,0 +1,78 @@
+/*
+ * Utility functions for FEL mode, when running SPL in AArch64.
+ *
+ * Copyright (c) 2017 Arm Ltd.
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <asm-offsets.h>
+#include <config.h>
+#include <asm/system.h>
+#include <linux/linkage.h>
+
+/*
+ * We don't overwrite save_boot_params() here, to save the FEL state upon
+ * entry, since this would run *after* the RMR reset, which clobbers that
+ * state.
+ * Instead we store the state _very_ early in the boot0 hook, *before*
+ * resetting to AArch64.
+ */
+
+/*
+ * The FEL routines in BROM run in AArch32.
+ * Reset back into 32-bit mode here and restore the saved FEL state
+ * afterwards.
+ * Resetting back into AArch32/EL3 using the RMR always enters the BROM,
+ * but we can use the CPU hotplug mechanism to branch back to our code
+ * immediately.
+ */
+ENTRY(return_to_fel)
+	/*
+	 * the RMR reset will clear all registers, so save the arguments
+	 * (LR and SP) in the fel_stash structure, which we read anyways later
+	 */
+	adr	x2, fel_stash
+	str	w0, [x2]
+	str	w1, [x2, #4]
+
+	adr	x1, fel_stash_addr	// to find the fel_stash address in AA32
+	str	w2, [x1]
+
+	ldr	x0, =0xfa50392f		// CPU hotplug magic
+#ifdef CONFIG_MACH_SUN50I_H6
+	ldr	x2, =(SUNXI_RTC_BASE + 0x1b8)	// BOOT_CPU_HP_FLAG_REG
+	str	w0, [x2], #0x4
+#else
+	ldr	x2, =(SUNXI_CPUCFG_BASE + 0x1a4) // offset for CPU hotplug base
+	str	w0, [x2, #0x8]
+#endif
+	adr	x0, back_in_32
+	str	w0, [x2]
+
+	dsb	sy
+	isb	sy
+	mov	x0, #2			// RMR reset into AArch32
+	dsb	sy
+	msr	RMR_EL3, x0
+	isb	sy
+1:	wfi
+	b	1b
+
+/* AArch32 code to restore the state from fel_stash and return back to FEL. */
+back_in_32:
+	.word	0xe59f0028 	// ldr	r0, [pc, #40]	; load fel_stash address
+	.word	0xe5901008 	// ldr	r1, [r0, #8]
+	.word	0xe129f001 	// msr	CPSR_fc, r1
+	.word	0xf57ff06f	// isb
+	.word	0xe590d000 	// ldr	sp, [r0]
+	.word	0xe590e004 	// ldr	lr, [r0, #4]
+	.word	0xe5901010 	// ldr	r1, [r0, #16]
+	.word	0xee0c1f10 	// mcr	15, 0, r1, cr12, cr0, {0} ; VBAR
+	.word	0xe590100c 	// ldr	r1, [r0, #12]
+	.word	0xee011f10 	// mcr	15, 0, r1, cr1, cr0, {0}  ; SCTLR
+	.word	0xf57ff06f	// isb
+	.word	0xe12fff1e 	// bx	lr		; return to FEL
+fel_stash_addr:
+	.word   0x00000000	// receives fel_stash addr, by AA64 code above
+ENDPROC(return_to_fel)
diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile
index fd47e40..0f738c2 100644
--- a/arch/arm/dts/Makefile
+++ b/arch/arm/dts/Makefile
@@ -590,6 +590,7 @@
 	sun8i-r40-bananapi-m2-ultra.dtb \
 	sun8i-v40-bananapi-m2-berry.dtb
 dtb-$(CONFIG_MACH_SUN8I_V3S) += \
+	sun8i-s3-pinecube.dtb \
 	sun8i-v3s-licheepi-zero.dtb
 dtb-$(CONFIG_MACH_SUN50I_H5) += \
 	sun50i-h5-bananapi-m2-plus.dtb \
@@ -889,6 +890,9 @@
 dtb-$(CONFIG_TARGET_OMAP5_UEVM) += \
 	omap5-uevm.dtb
 
+dtb-$(CONFIG_TARGET_SAMA7G5EK) += \
+	sama7g5ek.dtb
+
 dtb-$(CONFIG_TARGET_SAMA5D2_PTC_EK) += \
 	at91-sama5d2_ptc_ek.dtb
 
diff --git a/arch/arm/dts/sama7g5.dtsi b/arch/arm/dts/sama7g5.dtsi
new file mode 100644
index 0000000..0cb6eaf
--- /dev/null
+++ b/arch/arm/dts/sama7g5.dtsi
@@ -0,0 +1,170 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * sama7g5.dtsi - Device Tree Include file for SAMA7G5 SoC.
+ *
+ * Copyright (C) 2020 Microchip Technology Inc. and its subsidiaries
+ *
+ * Author: Eugen Hristev <eugen.hristev@microchip.com>
+ * Author: Claudiu Beznea <claudiu.beznea@microchip.com>
+ *
+ */
+
+#include "skeleton.dtsi"
+#include <dt-bindings/clk/at91.h>
+
+/ {
+	model = "Microchip SAMA7G5 family SoC";
+	compatible = "microchip,sama7g5";
+
+	clocks {
+		slow_rc_osc: slow_rc_osc {
+			compatible = "fixed-clock";
+			#clock-cells = <0>;
+			clock-frequency = <32000>;
+		};
+
+		main_rc: main_rc {
+			compatible = "fixed-clock";
+			#clock-cells = <0>;
+			clock-frequency = <12000000>;
+		};
+
+		slow_xtal: slow_xtal {
+			compatible = "fixed-clock";
+			#clock-cells = <0>;
+		};
+
+		main_xtal: main_xtal {
+			compatible = "fixed-clock";
+			#clock-cells = <0>;
+		};
+	};
+
+	cpus {
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		A7_0: cpu@0 {
+			device_type = "cpu";
+			compatible = "arm,cortex-a7";
+			clocks = <&pmc PMC_TYPE_CORE 8>, <&pmc PMC_TYPE_CORE 22>, <&main_xtal>;
+			clock-names = "cpu", "master", "xtal";
+		};
+	};
+
+	ahb {
+		compatible = "simple-bus";
+		#address-cells = <1>;
+		#size-cells = <1>;
+
+		apb {
+			compatible = "simple-bus";
+			#address-cells = <1>;
+			#size-cells = <1>;
+
+			pioA: pinctrl@e0014000 {
+				compatible = "atmel,sama5d2-gpio";
+				reg = <0xe0014000 0x800>;
+				gpio-controller;
+				#gpio-cells = <2>;
+				clocks = <&pmc PMC_TYPE_PERIPHERAL 11>;
+				status = "okay";
+
+				pinctrl: pinctrl_default {
+					compatible = "microchip,sama7g5-pinctrl";
+				};
+			};
+
+			pmc: pmc@e0018000 {
+				compatible = "microchip,sama7g5-pmc";
+				reg = <0xe0018000 0x200>;
+				#clock-cells = <2>;
+				clocks = <&clk32 1>, <&clk32 0>, <&main_xtal>, <&main_rc>;
+				clock-names = "td_slck", "md_slck", "main_xtal", "main_rc";
+				status = "okay";
+			};
+
+			clk32: sckc@e001d050 {
+				compatible = "microchip,sam9x60-sckc";
+				reg = <0xe001d050 0x4>;
+				clocks = <&slow_rc_osc>, <&slow_xtal>;
+				#clock-cells = <1>;
+			};
+
+			sdmmc0: sdio-host@e1204000 {
+				compatible = "microchip,sama7g5-sdhci";
+				reg = <0xe1204000 0x300>;
+				clocks = <&pmc PMC_TYPE_PERIPHERAL 80>, <&pmc PMC_TYPE_GCK 80>;
+				clock-names = "hclock", "multclk";
+				assigned-clocks = <&pmc PMC_TYPE_GCK 80>;
+				assigned-clock-rates = <200000000>;
+				assigned-clock-parents = <&pmc PMC_TYPE_CORE 10>; /* sys pll div. */
+				status = "disabled";
+			};
+
+			sdmmc1: sdio-host@e1208000 {
+				compatible = "microchip,sama7g5-sdhci";
+				reg = <0xe1208000 0x300>;
+				clocks = <&pmc PMC_TYPE_PERIPHERAL 81>, <&pmc PMC_TYPE_GCK 81>;
+				clock-names = "hclock", "multclk";
+				assigned-clocks = <&pmc PMC_TYPE_GCK 81>;
+				assigned-clock-rates = <200000000>;
+				assigned-clock-parents = <&pmc PMC_TYPE_CORE 10>; /* sys pll div. */
+				status = "disabled";
+			};
+
+			pit64b0: timer@e1800000 {
+				compatible = "microchip,sama7g5-pit64b";
+				reg = <0xe1800000 0x4000>;
+				clocks = <&pmc PMC_TYPE_PERIPHERAL 70>, <&pmc PMC_TYPE_GCK 70>;
+				clock-names = "pclk", "gclk";
+				status = "okay";
+			};
+
+			flx1: flexcom@e181c000 {
+				compatible = "atmel,sama5d2-flexcom";
+				reg = <0xe181c000 0x200>;
+				clocks = <&pmc PMC_TYPE_PERIPHERAL 39>;
+				#address-cells = <1>;
+				#size-cells = <1>;
+				ranges = <0x0 0xe181c000 0x800>;
+				status = "disabled";
+
+				i2c1: i2c@600 {
+					compatible = "atmel,sama5d2-i2c";
+					reg = <0x600 0x200>;
+					#address-cells = <1>;
+					#size-cells = <0>;
+					clocks = <&pmc PMC_TYPE_PERIPHERAL 39>;
+				};
+			};
+
+			uart0: serial@e1824200 {
+				compatible = "atmel,at91sam9260-usart";
+				reg = <0xe1824200 0x200>;
+				clocks = <&pmc PMC_TYPE_PERIPHERAL 41>;
+				clock-names = "usart";
+				status = "disabled";
+			};
+
+			gmac0: ethernet@e2800000 {
+				compatible = "cdns,sama7g5-gem";
+				reg = <0xe2800000 0x4000>;
+				clocks = <&pmc PMC_TYPE_PERIPHERAL 51>, <&pmc PMC_TYPE_PERIPHERAL 51>, <&pmc PMC_TYPE_GCK 51>;
+				clock-names = "hclk", "pclk", "tx_clk";
+				assigned-clocks = <&pmc PMC_TYPE_GCK 51>;
+				assigned-clock-parents = <&pmc PMC_TYPE_CORE 21>; /* eth pll div. */
+				assigned-clock-rates = <125000000>;
+				status = "disabled";
+			};
+
+			gmac1: ethernet@e2804000 {
+				compatible = "cdns,sama7g5-emac";
+				reg = <0xe2804000 0x1000>;
+				clocks = <&pmc PMC_TYPE_PERIPHERAL 52>, <&pmc PMC_TYPE_PERIPHERAL 52>;
+				clock-names = "pclk", "hclk";
+				status = "disabled";
+			};
+		};
+	};
+};
diff --git a/arch/arm/dts/sama7g5ek-u-boot.dtsi b/arch/arm/dts/sama7g5ek-u-boot.dtsi
new file mode 100644
index 0000000..5e1a0d5
--- /dev/null
+++ b/arch/arm/dts/sama7g5ek-u-boot.dtsi
@@ -0,0 +1,65 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * sama7g5ek-u-boot.dts - Device Tree file for SAMA7G5 SoC u-boot properties.
+ *
+ * Copyright (C) 2020 Microchip Technology Inc. and its subsidiaries
+ *
+ * Author: Eugen Hristev <eugen.hristev@microchip.com>
+ * Author: Claudiu Beznea <claudiu.beznea@microchip.com>
+ *
+ */
+
+/ {
+	chosen {
+		u-boot,dm-pre-reloc;
+	};
+
+	ahb {
+		u-boot,dm-pre-reloc;
+
+		apb {
+			u-boot,dm-pre-reloc;
+		};
+	};
+};
+
+&main_rc {
+	u-boot,dm-pre-reloc;
+};
+
+&main_xtal {
+	u-boot,dm-pre-reloc;
+};
+
+&pioA {
+	u-boot,dm-pre-reloc;
+
+	pinctrl {
+		u-boot,dm-pre-reloc;
+	};
+};
+
+&pinctrl_flx3_default {
+	u-boot,dm-pre-reloc;
+};
+
+&pit64b0 {
+	u-boot,dm-pre-reloc;
+};
+
+&pmc {
+	u-boot,dm-pre-reloc;
+};
+
+&slow_rc_osc {
+	u-boot,dm-pre-reloc;
+};
+
+&slow_xtal {
+	u-boot,dm-pre-reloc;
+};
+
+&uart0 {
+	u-boot,dm-pre-reloc;
+};
+
diff --git a/arch/arm/dts/sama7g5ek.dts b/arch/arm/dts/sama7g5ek.dts
new file mode 100644
index 0000000..ff9c9eb
--- /dev/null
+++ b/arch/arm/dts/sama7g5ek.dts
@@ -0,0 +1,202 @@
+// SPDX-License-Identifier: GPL-2.0+ OR MIT
+/*
+ * sama7g5ek.dts - Device Tree file for SAMA7G5 EK
+ *		   SAMA7G5 Evaluation Kit
+ *
+ *  Copyright (c) 2020, Microchip Technology Inc.
+ *                2020, Eugen Hristev <eugen.hristev@microchip.com>
+ *		  2020, Claudiu Beznea <claudiu.beznea@microchip.com>
+ */
+/dts-v1/;
+#include "sama7g5.dtsi"
+#include "sama7g5-pinfunc.h"
+
+/ {
+	model = "Microchip SAMA7G5 Evaluation Kit";
+	compatible = "microchip,sama7g5ek", "microchip,sama7g54", "microchip,sama7g5", "microchip,sama7";
+
+	aliases {
+		serial0 = &uart0;
+		i2c0 = &i2c1;
+	};
+
+	chosen {
+		stdout-path = "serial0:115200n8";
+	};
+
+	clocks {
+		slow_xtal: slow_xtal {
+			clock-frequency = <32768>;
+		};
+
+		main_xtal: main_xtal {
+			clock-frequency = <24000000>;
+		};
+	};
+
+	ahb {
+
+		apb {
+			sdmmc0: sdio-host@e1204000 {
+				bus-width = <8>;
+				non-removable;
+				pinctrl-names = "default";
+				pinctrl-0 = <&pinctrl_sdmmc0_cmd_data_default
+					     &pinctrl_sdmmc0_ck_rstn_ds_cd_default>;
+				status = "okay";
+			};
+
+			sdmmc1: sdio-host@e1208000 {
+				bus-width = <4>;
+				pinctrl-names = "default";
+				pinctrl-0 = <&pinctrl_sdmmc1_cmd_data_default
+					     &pinctrl_sdmmc1_ck_cd_rstn_vddsel_default>;
+				status = "okay";
+			};
+
+			uart0: serial@e1824200 {
+				pinctrl-names = "default";
+				pinctrl-0 = <&pinctrl_flx3_default>;
+				status = "okay";
+			};
+		};
+	};
+};
+
+&flx1 {
+	atmel,flexcom-mode = <3>;
+	status = "okay";
+};
+
+&i2c1 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_flx1_default>;
+	status = "okay";
+
+	eeprom@52 {
+		compatible = "microchip,24aa02e48";
+		reg = <0x52>;
+		pagesize = <16>;
+	};
+
+	eeprom@53 {
+		compatible = "microchip,24aa02e48";
+		reg = <0x53>;
+		pagesize = <16>;
+	};
+};
+
+&gmac0 {
+	#address-cells = <1>;
+	#size-cells = <0>;
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_gmac0_default &pinctrl_gmac0_txc_default>;
+	phy-mode = "rgmii-id";
+	status = "okay";
+
+	ethernet-phy@7 {
+		reg = <0x7>;
+	};
+};
+
+&gmac1 {
+	#address-cells = <1>;
+	#size-cells = <0>;
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_gmac1_default>;
+	phy-mode = "rmii";
+	status = "okay";
+
+	ethernet-phy@0 {
+		reg = <0x0>;
+	};
+};
+
+&pinctrl {
+	pinctrl_flx1_default: flx1_default {
+		pinmux = <PIN_PC9__FLEXCOM1_IO0>,
+			 <PIN_PC10__FLEXCOM1_IO1>;
+		bias-disable;
+	};
+
+	pinctrl_flx3_default: flx3_default {
+		pinmux = <PIN_PD16__FLEXCOM3_IO0>,
+			 <PIN_PD17__FLEXCOM3_IO1>;
+		bias-disable;
+	};
+
+	pinctrl_sdmmc0_cmd_data_default: sdmmc0_cmd_data_default {
+		pinmux = <PIN_PA1__SDMMC0_CMD>,
+			 <PIN_PA3__SDMMC0_DAT0>,
+			 <PIN_PA4__SDMMC0_DAT1>,
+			 <PIN_PA5__SDMMC0_DAT2>,
+			 <PIN_PA6__SDMMC0_DAT3>,
+			 <PIN_PA7__SDMMC0_DAT4>,
+			 <PIN_PA8__SDMMC0_DAT5>,
+			 <PIN_PA9__SDMMC0_DAT6>,
+			 <PIN_PA10__SDMMC0_DAT7>;
+		bias-pull-up;
+	};
+
+	pinctrl_sdmmc0_ck_rstn_ds_cd_default: sdmmc0_ck_rstn_ds_cd_default {
+		pinmux = <PIN_PA0__SDMMC0_CK>,
+			 <PIN_PA2__SDMMC0_RSTN>,
+			 <PIN_PA11__SDMMC0_DS>,
+			 <PIN_PA14__SDMMC0_CD>;
+		bias-pull-up;
+	};
+
+	pinctrl_sdmmc1_cmd_data_default: sdmmc1_cmd_data_default {
+		pinmux = <PIN_PB29__SDMMC1_CMD>,
+			 <PIN_PB31__SDMMC1_DAT0>,
+			 <PIN_PC0__SDMMC1_DAT1>,
+			 <PIN_PC1__SDMMC1_DAT2>,
+			 <PIN_PC2__SDMMC1_DAT3>;
+		bias-pull-up;
+	};
+
+	pinctrl_sdmmc1_ck_cd_rstn_vddsel_default: sdmmc1_ck_cd_rstn_vddsel_default {
+		pinmux = <PIN_PB30__SDMMC1_CK>,
+			 <PIN_PB28__SDMMC1_RSTN>,
+			 <PIN_PC5__SDMMC1_1V8SEL>,
+			 <PIN_PC4__SDMMC1_CD>;
+		bias-pull-up;
+	};
+
+	pinctrl_gmac0_default: gmac0_default {
+		pinmux = <PIN_PA16__G0_TX0>,
+			 <PIN_PA17__G0_TX1>,
+			 <PIN_PA26__G0_TX2>,
+			 <PIN_PA27__G0_TX3>,
+			 <PIN_PA19__G0_RX0>,
+			 <PIN_PA20__G0_RX1>,
+			 <PIN_PA28__G0_RX2>,
+			 <PIN_PA29__G0_RX3>,
+			 <PIN_PA15__G0_TXEN>,
+			 <PIN_PA30__G0_RXCK>,
+			 <PIN_PA18__G0_RXDV>,
+			 <PIN_PA22__G0_MDC>,
+			 <PIN_PA23__G0_MDIO>,
+			 <PIN_PA25__G0_125CK>;
+		bias-disable;
+	};
+
+	pinctrl_gmac0_txc_default: gmac0_txc_default {
+		pinmux = <PIN_PA24__G0_TXCK>;
+		bias-pull-up;
+	};
+
+	pinctrl_gmac1_default: gmac1_default {
+		pinmux = <PIN_PD30__G1_TXCK>,
+			 <PIN_PD22__G1_TX0>,
+			 <PIN_PD23__G1_TX1>,
+			 <PIN_PD21__G1_TXEN>,
+			 <PIN_PD25__G1_RX0>,
+			 <PIN_PD26__G1_RX1>,
+			 <PIN_PD27__G1_RXER>,
+			 <PIN_PD24__G1_RXDV>,
+			 <PIN_PD28__G1_MDC>,
+			 <PIN_PD29__G1_MDIO>;
+		bias-disable;
+	};
+};
diff --git a/arch/arm/include/asm/arch-sunxi/boot0.h b/arch/arm/include/asm/arch-sunxi/boot0.h
index 54c144a..46d0f06 100644
--- a/arch/arm/include/asm/arch-sunxi/boot0.h
+++ b/arch/arm/include/asm/arch-sunxi/boot0.h
@@ -15,6 +15,19 @@
 	tst     x0, x0                  // this is "b #0x84" in ARM
 	b       reset
 	.space  0x7c
+
+	.word	0xe28f0058	// add     r0, pc, #88
+	.word	0xe59f1054	// ldr     r1, [pc, #84]
+	.word	0xe0800001	// add     r0, r0, r1
+	.word	0xe580d000	// str     sp, [r0]
+	.word	0xe580e004	// str     lr, [r0, #4]
+	.word	0xe10fe000	// mrs     lr, CPSR
+	.word	0xe580e008	// str     lr, [r0, #8]
+	.word	0xee11ef10	// mrc     15, 0, lr, cr1, cr0, {0}
+	.word	0xe580e00c	// str     lr, [r0, #12]
+	.word	0xee1cef10	// mrc     15, 0, lr, cr12, cr0, {0}
+	.word	0xe580e010	// str     lr, [r0, #16]
+
 	.word	0xe59f1024	// ldr     r1, [pc, #36] ; 0x170000a0
 	.word	0xe59f0024	// ldr     r0, [pc, #36] ; CONFIG_*_TEXT_BASE
 	.word	0xe5810000	// str     r0, [r1]
@@ -36,6 +49,7 @@
 #else
 	.word   CONFIG_SYS_TEXT_BASE
 #endif
+	.word	fel_stash - .
 #else
 /* normal execution */
 	b	reset
diff --git a/arch/arm/include/asm/arch-sunxi/spl.h b/arch/arm/include/asm/arch-sunxi/spl.h
index 8c916e8..58cdf80 100644
--- a/arch/arm/include/asm/arch-sunxi/spl.h
+++ b/arch/arm/include/asm/arch-sunxi/spl.h
@@ -7,19 +7,7 @@
 #ifndef	_ASM_ARCH_SPL_H_
 #define	_ASM_ARCH_SPL_H_
 
-#define BOOT0_MAGIC		"eGON.BT0"
-#define SPL_SIGNATURE		"SPL" /* marks "sunxi" SPL header */
-#define SPL_MAJOR_BITS		3
-#define SPL_MINOR_BITS		5
-#define SPL_VERSION(maj, min)						\
-	((((maj) & ((1U << SPL_MAJOR_BITS) - 1)) << SPL_MINOR_BITS) | \
-	((min) & ((1U << SPL_MINOR_BITS) - 1)))
-
-#define SPL_HEADER_VERSION	SPL_VERSION(0, 2)
-
-#define SPL_ENV_HEADER_VERSION	SPL_VERSION(0, 1)
-#define SPL_DT_HEADER_VERSION	SPL_VERSION(0, 2)
-#define SPL_DRAM_HEADER_VERSION	SPL_VERSION(0, 3)
+#include <sunxi_image.h>
 
 #define SPL_ADDR		CONFIG_SUNXI_SRAM_ADDRESS
 
@@ -31,59 +19,7 @@
 #define SUNXI_BOOTED_FROM_MMC0_HIGH	0x10
 #define SUNXI_BOOTED_FROM_MMC2_HIGH	0x12
 
-/* boot head definition from sun4i boot code */
-struct boot_file_head {
-	uint32_t b_instruction;	/* one intruction jumping to real code */
-	uint8_t magic[8];	/* ="eGON.BT0" or "eGON.BT1", not C-style str */
-	uint32_t check_sum;	/* generated by PC */
-	uint32_t length;	/* generated by PC */
-	/*
-	 * We use a simplified header, only filling in what is needed
-	 * by the boot ROM. To be compatible with Allwinner tools we
-	 * would need to implement the proper fields here instead of
-	 * padding.
-	 *
-	 * Actually we want the ability to recognize our "sunxi" variant
-	 * of the SPL. To do so, let's place a special signature into the
-	 * "pub_head_size" field. We can reasonably expect Allwinner's
-	 * boot0 to always have the upper 16 bits of this set to 0 (after
-	 * all the value shouldn't be larger than the limit imposed by
-	 * SRAM size).
-	 * If the signature is present (at 0x14), then we know it's safe
-	 * to use the remaining 8 bytes (at 0x18) for our own purposes.
-	 * (E.g. sunxi-tools "fel" utility can pass information there.)
-	 */
-	union {
-		uint32_t pub_head_size;
-		uint8_t spl_signature[4];
-	};
-	uint32_t fel_script_address;	/* since v0.1, set by sunxi-fel */
-	/*
-	 * If the fel_uEnv_length member below is set to a non-zero value,
-	 * it specifies the size (byte count) of data at fel_script_address.
-	 * At the same time this indicates that the data is in uEnv.txt
-	 * compatible format, ready to be imported via "env import -t".
-	 */
-	uint32_t fel_uEnv_length;	/* since v0.1, set by sunxi-fel */
-	/*
-	 * Offset of an ASCIIZ string (relative to the SPL header), which
-	 * contains the default device tree name (CONFIG_DEFAULT_DEVICE_TREE).
-	 * This is optional and may be set to NULL. Is intended to be used
-	 * by flash programming tools for providing nice informative messages
-	 * to the users.
-	 */
-	uint32_t dt_name_offset;	/* since v0.2, set by mksunxiboot */
-	uint32_t dram_size;		/* in MiB, since v0.3, set by SPL */
-	uint32_t boot_media;		/* written here by the boot ROM */
-	/* A padding area (may be used for storing text strings) */
-	uint32_t string_pool[13];	/* since v0.2, filled by mksunxiboot */
-	/* The header must be a multiple of 32 bytes (for VBAR alignment) */
-};
-
-/* Compile time check to assure proper alignment of structure */
-typedef char boot_file_head_not_multiple_of_32[1 - 2*(sizeof(struct boot_file_head) % 32)];
-
-#define is_boot0_magic(addr)	(memcmp((void *)addr, BOOT0_MAGIC, 8) == 0)
+#define is_boot0_magic(addr)	(memcmp((void *)(addr), BOOT0_MAGIC, 8) == 0)
 
 uint32_t sunxi_get_boot_device(void);
 
diff --git a/arch/arm/mach-at91/Kconfig b/arch/arm/mach-at91/Kconfig
index be1415f..c78a308 100644
--- a/arch/arm/mach-at91/Kconfig
+++ b/arch/arm/mach-at91/Kconfig
@@ -265,6 +265,13 @@
 	select SUPPORT_SPL
 	imply CMD_DM
 
+config TARGET_SAMA7G5EK
+       bool "SAMA7G5 EK board"
+       select SAMA7G5
+       select BOARD_EARLY_INIT_F
+       select BOARD_LATE_INIT
+
+
 config TARGET_TAURUS
 	bool "Support taurus"
 	select AT91SAM9G20
@@ -327,6 +334,7 @@
 source "board/atmel/at91sam9rlek/Kconfig"
 source "board/atmel/at91sam9x5ek/Kconfig"
 source "board/atmel/sam9x60ek/Kconfig"
+source "board/atmel/sama7g5ek/Kconfig"
 source "board/atmel/sama5d2_ptc_ek/Kconfig"
 source "board/atmel/sama5d2_xplained/Kconfig"
 source "board/atmel/sama5d27_som1_ek/Kconfig"
diff --git a/arch/arm/mach-sunxi/Kconfig b/arch/arm/mach-sunxi/Kconfig
index 49ef217..11e6445 100644
--- a/arch/arm/mach-sunxi/Kconfig
+++ b/arch/arm/mach-sunxi/Kconfig
@@ -1016,4 +1016,15 @@
 	  Enable this option to automatically select the device tree for the
 	  correct PinePhone hardware revision during boot.
 
+config BLUETOOTH_DT_DEVICE_FIXUP
+	string "Fixup the Bluetooth controller address"
+	default ""
+	help
+	  This option specifies the DT compatible name of the Bluetooth
+	  controller for which to set the "local-bd-address" property.
+	  Set this option if your device ships with the Bluetooth controller
+	  default address.
+	  The used address is "bdaddr" if set, and "ethaddr" with the LSB
+	  flipped elsewise.
+
 endif
diff --git a/arch/arm/mach-sunxi/dram_sun50i_h6.c b/arch/arm/mach-sunxi/dram_sun50i_h6.c
index 9e34da4..32ec0bc 100644
--- a/arch/arm/mach-sunxi/dram_sun50i_h6.c
+++ b/arch/arm/mach-sunxi/dram_sun50i_h6.c
@@ -37,9 +37,9 @@
 
 static void mctl_sys_init(struct dram_para *para);
 static void mctl_com_init(struct dram_para *para);
-static void mctl_channel_init(struct dram_para *para);
+static bool mctl_channel_init(struct dram_para *para);
 
-static void mctl_core_init(struct dram_para *para)
+static bool mctl_core_init(struct dram_para *para)
 {
 	mctl_sys_init(para);
 	mctl_com_init(para);
@@ -51,7 +51,7 @@
 	default:
 		panic("Unsupported DRAM type!");
 	};
-	mctl_channel_init(para);
+	return mctl_channel_init(para);
 }
 
 /* PHY initialisation */
@@ -411,7 +411,7 @@
 	}
 }
 
-static void mctl_channel_init(struct dram_para *para)
+static bool mctl_channel_init(struct dram_para *para)
 {
 	struct sunxi_mctl_com_reg * const mctl_com =
 			(struct sunxi_mctl_com_reg *)SUNXI_DRAM_COM_BASE;
@@ -528,46 +528,15 @@
 		clrbits_le32(&mctl_phy->dx[i].gcr[3], ~0x3ffff);
 	udelay(10);
 
-	if (readl(&mctl_phy->pgsr[0]) & 0x400000)
-	{
-		/* Check for single rank and optionally half DQ. */
-		if ((readl(&mctl_phy->dx[0].rsr[0]) & 0x3) == 2 &&
-		    (readl(&mctl_phy->dx[1].rsr[0]) & 0x3) == 2) {
-			para->ranks = 1;
-
-			if ((readl(&mctl_phy->dx[2].rsr[0]) & 0x3) != 2 ||
-			    (readl(&mctl_phy->dx[3].rsr[0]) & 0x3) != 2)
-				para->bus_full_width = 0;
-
-			/* Restart DRAM initialization from scratch. */
-			mctl_core_init(para);
-			return;
-		}
-
-		/*
-		 * Check for dual rank and half DQ. NOTE: This combination
-		 * is highly unlikely and was not tested. Condition is the
-		 * same as in libdram, though.
-		 */
-		if ((readl(&mctl_phy->dx[0].rsr[0]) & 0x3) == 0 &&
-		    (readl(&mctl_phy->dx[1].rsr[0]) & 0x3) == 0) {
-			para->bus_full_width = 0;
-
-			/* Restart DRAM initialization from scratch. */
-			mctl_core_init(para);
-			return;
-		}
-
-		panic("This DRAM setup is currently not supported.\n");
-	}
-
 	if (readl(&mctl_phy->pgsr[0]) & 0xff00000) {
 		/* Oops! There's something wrong! */
 		debug("PLL = %x\n", readl(0x3001010));
 		debug("DRAM PHY PGSR0 = %x\n", readl(&mctl_phy->pgsr[0]));
 		for (i = 0; i < 4; i++)
 			debug("DRAM PHY DX%dRSR0 = %x\n", i, readl(&mctl_phy->dx[i].rsr[0]));
-		panic("Error while initializing DRAM PHY!\n");
+		debug("Error while initializing DRAM PHY!\n");
+
+		return false;
 	}
 
 	if (sunxi_dram_is_lpddr(para->type))
@@ -582,13 +551,59 @@
 	writel(0xffffffff, &mctl_com->maer0);
 	writel(0x7ff, &mctl_com->maer1);
 	writel(0xffff, &mctl_com->maer2);
+
+	return true;
+}
+
+static void mctl_auto_detect_rank_width(struct dram_para *para)
+{
+	/* this is minimum size that it's supported */
+	para->cols = 8;
+	para->rows = 13;
+
+	/*
+	 * Previous versions of this driver tried to auto detect the rank
+	 * and width by looking at controller registers. However this proved
+	 * to be not reliable, so this approach here is the more robust
+	 * solution. Check the git history for details.
+	 *
+	 * Strategy here is to test most demanding combination first and least
+	 * demanding last, otherwise HW might not be fully utilized. For
+	 * example, half bus width and rank = 1 combination would also work
+	 * on HW with full bus width and rank = 2, but only 1/4 RAM would be
+	 * visible.
+	 */
+
+	debug("testing 32-bit width, rank = 2\n");
+	para->bus_full_width = 1;
+	para->ranks = 2;
+	if (mctl_core_init(para))
+		return;
+
+	debug("testing 32-bit width, rank = 1\n");
+	para->bus_full_width = 1;
+	para->ranks = 1;
+	if (mctl_core_init(para))
+		return;
+
+	debug("testing 16-bit width, rank = 2\n");
+	para->bus_full_width = 0;
+	para->ranks = 2;
+	if (mctl_core_init(para))
+		return;
+
+	debug("testing 16-bit width, rank = 1\n");
+	para->bus_full_width = 0;
+	para->ranks = 1;
+	if (mctl_core_init(para))
+		return;
+
+	panic("This DRAM setup is currently not supported.\n");
 }
 
 static void mctl_auto_detect_dram_size(struct dram_para *para)
 {
 	/* TODO: non-(LP)DDR3 */
-	/* Detect rank number and half DQ by the code in mctl_channel_init. */
-	mctl_core_init(para);
 
 	/* detect row address bits */
 	para->cols = 8;
@@ -652,10 +667,6 @@
 			(struct sunxi_mctl_com_reg *)SUNXI_DRAM_COM_BASE;
 	struct dram_para para = {
 		.clk = CONFIG_DRAM_CLK,
-		.ranks = 2,
-		.cols = 11,
-		.rows = 14,
-		.bus_full_width = 1,
 #ifdef CONFIG_SUNXI_DRAM_H6_LPDDR3
 		.type = SUNXI_DRAM_TYPE_LPDDR3,
 		.dx_read_delays  = SUN50I_H6_LPDDR3_DX_READ_DELAYS,
@@ -673,6 +684,7 @@
 	setbits_le32(0x7010310, BIT(8));
 	clrbits_le32(0x7010318, 0x3f);
 
+	mctl_auto_detect_rank_width(&para);
 	mctl_auto_detect_dram_size(&para);
 
 	mctl_core_init(&para);
diff --git a/board/atmel/sama7g5ek/Kconfig b/board/atmel/sama7g5ek/Kconfig
new file mode 100644
index 0000000..a89db8d
--- /dev/null
+++ b/board/atmel/sama7g5ek/Kconfig
@@ -0,0 +1,15 @@
+if TARGET_SAMA7G5EK
+
+config SYS_BOARD
+	default "sama7g5ek"
+
+config SYS_VENDOR
+	default "atmel"
+
+config SYS_SOC
+	default "at91"
+
+config SYS_CONFIG_NAME
+	default "sama7g5ek"
+
+endif
diff --git a/board/atmel/sama7g5ek/MAINTAINERS b/board/atmel/sama7g5ek/MAINTAINERS
new file mode 100644
index 0000000..eac9729
--- /dev/null
+++ b/board/atmel/sama7g5ek/MAINTAINERS
@@ -0,0 +1,8 @@
+SAMA7G5 EK BOARD
+M:     Eugen Hristev <eugen.hristev@microchip.com>
+S:     Maintained
+F:     board/atmel/sama7g5ek.c
+F:     include/configs/sama7g5ek.h
+F:     configs/sama7g5ek_mmc1_defconfig
+F:     configs/sama7g5ek_mmc_defconfig
+
diff --git a/board/atmel/sama7g5ek/Makefile b/board/atmel/sama7g5ek/Makefile
new file mode 100644
index 0000000..a6eedd1
--- /dev/null
+++ b/board/atmel/sama7g5ek/Makefile
@@ -0,0 +1,7 @@
+# SPDX-License-Identifier:     GPL-2.0+
+#
+# Copyright (C) 2020 Microchip Technology Inc.
+#                   Eugen Hristev <eugen.hristev@microchip.com>
+#
+
+obj-y += sama7g5ek.o
diff --git a/board/atmel/sama7g5ek/sama7g5ek.c b/board/atmel/sama7g5ek/sama7g5ek.c
new file mode 100644
index 0000000..b5cece0
--- /dev/null
+++ b/board/atmel/sama7g5ek/sama7g5ek.c
@@ -0,0 +1,76 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2020 Microchip Technology, Inc.
+ *		      Eugen Hristev <eugen.hristev@microchip.com>
+ */
+
+#include <common.h>
+#include <debug_uart.h>
+#include <init.h>
+#include <asm/io.h>
+#include <asm/arch/at91_common.h>
+#include <asm/arch/atmel_pio4.h>
+#include <asm/arch/clk.h>
+#include <asm/arch/gpio.h>
+#include <asm/arch/sama7g5.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+int board_late_init(void)
+{
+	return 0;
+}
+
+#if (IS_ENABLED(CONFIG_DEBUG_UART_BOARD_INIT))
+static void board_uart0_hw_init(void)
+{
+	/* FLEXCOM3 IO0 */
+	atmel_pio4_set_f_periph(AT91_PIO_PORTD, 17, ATMEL_PIO_PUEN_MASK);
+	/* FLEXCOM3 IO1 */
+	atmel_pio4_set_f_periph(AT91_PIO_PORTD, 16, 0);
+
+	at91_periph_clk_enable(ATMEL_ID_FLEXCOM3);
+}
+
+void board_debug_uart_init(void)
+{
+	board_uart0_hw_init();
+}
+#endif
+
+int board_early_init_f(void)
+{
+#if (IS_ENABLED(CONFIG_DEBUG_UART))
+	debug_uart_init();
+#endif
+	return 0;
+}
+
+#define MAC24AA_MAC_OFFSET     0xfa
+
+#if (IS_ENABLED(CONFIG_MISC_INIT_R))
+int misc_init_r(void)
+{
+#if (IS_ENABLED(CONFIG_I2C_EEPROM))
+	at91_set_ethaddr(MAC24AA_MAC_OFFSET);
+	at91_set_eth1addr(MAC24AA_MAC_OFFSET);
+#endif
+	return 0;
+}
+#endif
+
+int board_init(void)
+{
+	/* address of boot parameters */
+	gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
+
+	return 0;
+}
+
+int dram_init(void)
+{
+	gd->ram_size = get_ram_size((void *)CONFIG_SYS_SDRAM_BASE,
+				    CONFIG_SYS_SDRAM_SIZE);
+	return 0;
+}
+
diff --git a/board/sunxi/MAINTAINERS b/board/sunxi/MAINTAINERS
index d3755ae..735801a 100644
--- a/board/sunxi/MAINTAINERS
+++ b/board/sunxi/MAINTAINERS
@@ -440,6 +440,11 @@
 S:	Maintained
 F:	configs/pinebook_defconfig
 
+PINECUBE BOARD:
+M:	Icenowy Zheng <icenowy@aosc.io>
+S:	Maintained
+F:	configs/pinecube_defconfig
+
 PINE64 BOARDS
 M:	Andre Przywara <andre.przywara@arm.com>
 S:	Maintained
diff --git a/board/sunxi/board.c b/board/sunxi/board.c
index 708a27e..4f05895 100644
--- a/board/sunxi/board.c
+++ b/board/sunxi/board.c
@@ -39,6 +39,7 @@
 #include <u-boot/crc.h>
 #include <env_internal.h>
 #include <linux/libfdt.h>
+#include <fdt_support.h>
 #include <nand.h>
 #include <net.h>
 #include <spl.h>
@@ -789,6 +790,38 @@
 	env_set_hex("fel_scriptaddr", spl->fel_script_address);
 }
 
+static bool get_unique_sid(unsigned int *sid)
+{
+	if (sunxi_get_sid(sid) != 0)
+		return false;
+
+	if (!sid[0])
+		return false;
+
+	/*
+	 * The single words 1 - 3 of the SID have quite a few bits
+	 * which are the same on many models, so we take a crc32
+	 * of all 3 words, to get a more unique value.
+	 *
+	 * Note we only do this on newer SoCs as we cannot change
+	 * the algorithm on older SoCs since those have been using
+	 * fixed mac-addresses based on only using word 3 for a
+	 * long time and changing a fixed mac-address with an
+	 * u-boot update is not good.
+	 */
+#if !defined(CONFIG_MACH_SUN4I) && !defined(CONFIG_MACH_SUN5I) && \
+    !defined(CONFIG_MACH_SUN6I) && !defined(CONFIG_MACH_SUN7I) && \
+    !defined(CONFIG_MACH_SUN8I_A23) && !defined(CONFIG_MACH_SUN8I_A33)
+	sid[3] = crc32(0, (unsigned char *)&sid[1], 12);
+#endif
+
+	/* Ensure the NIC specific bytes of the mac are not all 0 */
+	if ((sid[3] & 0xffffff) == 0)
+		sid[3] |= 0x800000;
+
+	return true;
+}
+
 /*
  * Note this function gets called multiple times.
  * It must not make any changes to env variables which already exist.
@@ -799,61 +832,40 @@
 	unsigned int sid[4];
 	uint8_t mac_addr[6];
 	char ethaddr[16];
-	int i, ret;
-
-	ret = sunxi_get_sid(sid);
-	if (ret == 0 && sid[0] != 0) {
-		/*
-		 * The single words 1 - 3 of the SID have quite a few bits
-		 * which are the same on many models, so we take a crc32
-		 * of all 3 words, to get a more unique value.
-		 *
-		 * Note we only do this on newer SoCs as we cannot change
-		 * the algorithm on older SoCs since those have been using
-		 * fixed mac-addresses based on only using word 3 for a
-		 * long time and changing a fixed mac-address with an
-		 * u-boot update is not good.
-		 */
-#if !defined(CONFIG_MACH_SUN4I) && !defined(CONFIG_MACH_SUN5I) && \
-    !defined(CONFIG_MACH_SUN6I) && !defined(CONFIG_MACH_SUN7I) && \
-    !defined(CONFIG_MACH_SUN8I_A23) && !defined(CONFIG_MACH_SUN8I_A33)
-		sid[3] = crc32(0, (unsigned char *)&sid[1], 12);
-#endif
+	int i;
 
-		/* Ensure the NIC specific bytes of the mac are not all 0 */
-		if ((sid[3] & 0xffffff) == 0)
-			sid[3] |= 0x800000;
+	if (!get_unique_sid(sid))
+		return;
 
-		for (i = 0; i < 4; i++) {
-			sprintf(ethaddr, "ethernet%d", i);
-			if (!fdt_get_alias(fdt, ethaddr))
-				continue;
+	for (i = 0; i < 4; i++) {
+		sprintf(ethaddr, "ethernet%d", i);
+		if (!fdt_get_alias(fdt, ethaddr))
+			continue;
 
-			if (i == 0)
-				strcpy(ethaddr, "ethaddr");
-			else
-				sprintf(ethaddr, "eth%daddr", i);
+		if (i == 0)
+			strcpy(ethaddr, "ethaddr");
+		else
+			sprintf(ethaddr, "eth%daddr", i);
 
-			if (env_get(ethaddr))
-				continue;
+		if (env_get(ethaddr))
+			continue;
 
-			/* Non OUI / registered MAC address */
-			mac_addr[0] = (i << 4) | 0x02;
-			mac_addr[1] = (sid[0] >>  0) & 0xff;
-			mac_addr[2] = (sid[3] >> 24) & 0xff;
-			mac_addr[3] = (sid[3] >> 16) & 0xff;
-			mac_addr[4] = (sid[3] >>  8) & 0xff;
-			mac_addr[5] = (sid[3] >>  0) & 0xff;
+		/* Non OUI / registered MAC address */
+		mac_addr[0] = (i << 4) | 0x02;
+		mac_addr[1] = (sid[0] >>  0) & 0xff;
+		mac_addr[2] = (sid[3] >> 24) & 0xff;
+		mac_addr[3] = (sid[3] >> 16) & 0xff;
+		mac_addr[4] = (sid[3] >>  8) & 0xff;
+		mac_addr[5] = (sid[3] >>  0) & 0xff;
 
-			eth_env_set_enetaddr(ethaddr, mac_addr);
-		}
+		eth_env_set_enetaddr(ethaddr, mac_addr);
+	}
 
-		if (!env_get("serial#")) {
-			snprintf(serial_string, sizeof(serial_string),
-				"%08x%08x", sid[0], sid[3]);
+	if (!env_get("serial#")) {
+		snprintf(serial_string, sizeof(serial_string),
+			"%08x%08x", sid[0], sid[3]);
 
-			env_set("serial#", serial_string);
-		}
+		env_set("serial#", serial_string);
 	}
 }
 
@@ -890,6 +902,11 @@
 
 	setup_environment(gd->fdt_blob);
 
+	return 0;
+}
+
+int board_late_init(void)
+{
 #ifdef CONFIG_USB_ETHER
 	usb_ether_init();
 #endif
@@ -897,6 +914,38 @@
 	return 0;
 }
 
+static void bluetooth_dt_fixup(void *blob)
+{
+	/* Some devices ship with a Bluetooth controller default address.
+	 * Set a valid address through the device tree.
+	 */
+	uchar tmp[ETH_ALEN], bdaddr[ETH_ALEN];
+	unsigned int sid[4];
+	int i;
+
+	if (!CONFIG_BLUETOOTH_DT_DEVICE_FIXUP[0])
+		return;
+
+	if (eth_env_get_enetaddr("bdaddr", tmp)) {
+		/* Convert between the binary formats of the corresponding stacks */
+		for (i = 0; i < ETH_ALEN; ++i)
+			bdaddr[i] = tmp[ETH_ALEN - i - 1];
+	} else {
+		if (!get_unique_sid(sid))
+			return;
+
+		bdaddr[0] = ((sid[3] >>  0) & 0xff) ^ 1;
+		bdaddr[1] = (sid[3] >>  8) & 0xff;
+		bdaddr[2] = (sid[3] >> 16) & 0xff;
+		bdaddr[3] = (sid[3] >> 24) & 0xff;
+		bdaddr[4] = (sid[0] >>  0) & 0xff;
+		bdaddr[5] = 0x02;
+	}
+
+	do_fixup_by_compat(blob, CONFIG_BLUETOOTH_DT_DEVICE_FIXUP,
+			   "local-bd-address", bdaddr, ETH_ALEN, 1);
+}
+
 int ft_board_setup(void *blob, struct bd_info *bd)
 {
 	int __maybe_unused r;
@@ -907,6 +956,8 @@
 	 */
 	setup_environment(blob);
 
+	bluetooth_dt_fixup(blob);
+
 #ifdef CONFIG_VIDEO_DT_SIMPLEFB
 	r = sunxi_simplefb_setup(blob);
 	if (r)
diff --git a/common/image.c b/common/image.c
index 451fc68..6923dac 100644
--- a/common/image.c
+++ b/common/image.c
@@ -189,6 +189,7 @@
 	{	IH_TYPE_STM32IMAGE, "stm32image", "STMicroelectronics STM32 Image" },
 	{	IH_TYPE_MTKIMAGE,   "mtk_image",   "MediaTek BootROM loadable Image" },
 	{	IH_TYPE_COPRO, "copro", "Coprocessor Image"},
+	{	IH_TYPE_SUNXI_EGON, "sunxi_egon",  "Allwinner eGON Boot Image" },
 	{	-1,		    "",		  "",			},
 };
 
diff --git a/configs/at91sam9260ek_dataflash_cs0_defconfig b/configs/at91sam9260ek_dataflash_cs0_defconfig
index 0d9b691..89f5f2c 100644
--- a/configs/at91sam9260ek_dataflash_cs0_defconfig
+++ b/configs/at91sam9260ek_dataflash_cs0_defconfig
@@ -43,7 +43,6 @@
 # CONFIG_MMC is not set
 CONFIG_MTD=y
 CONFIG_MTD_RAW_NAND=y
-# CONFIG_SYS_NAND_USE_FLASH_BBT is not set
 CONFIG_NAND_ATMEL=y
 CONFIG_DM_SPI_FLASH=y
 CONFIG_SPI_FLASH_ATMEL=y
diff --git a/configs/at91sam9260ek_dataflash_cs1_defconfig b/configs/at91sam9260ek_dataflash_cs1_defconfig
index d0542ec..a7d0d28 100644
--- a/configs/at91sam9260ek_dataflash_cs1_defconfig
+++ b/configs/at91sam9260ek_dataflash_cs1_defconfig
@@ -43,7 +43,6 @@
 # CONFIG_MMC is not set
 CONFIG_MTD=y
 CONFIG_MTD_RAW_NAND=y
-# CONFIG_SYS_NAND_USE_FLASH_BBT is not set
 CONFIG_NAND_ATMEL=y
 CONFIG_DM_SPI_FLASH=y
 CONFIG_SPI_FLASH_ATMEL=y
diff --git a/configs/at91sam9260ek_nandflash_defconfig b/configs/at91sam9260ek_nandflash_defconfig
index e68f0bd..a5eaba5 100644
--- a/configs/at91sam9260ek_nandflash_defconfig
+++ b/configs/at91sam9260ek_nandflash_defconfig
@@ -40,7 +40,6 @@
 # CONFIG_MMC is not set
 CONFIG_MTD=y
 CONFIG_MTD_RAW_NAND=y
-# CONFIG_SYS_NAND_USE_FLASH_BBT is not set
 CONFIG_NAND_ATMEL=y
 CONFIG_DM_SPI_FLASH=y
 CONFIG_SPI_FLASH_ATMEL=y
diff --git a/configs/at91sam9261ek_dataflash_cs0_defconfig b/configs/at91sam9261ek_dataflash_cs0_defconfig
index e19b97b..2172c79 100644
--- a/configs/at91sam9261ek_dataflash_cs0_defconfig
+++ b/configs/at91sam9261ek_dataflash_cs0_defconfig
@@ -42,7 +42,6 @@
 # CONFIG_MMC is not set
 CONFIG_MTD=y
 CONFIG_MTD_RAW_NAND=y
-# CONFIG_SYS_NAND_USE_FLASH_BBT is not set
 CONFIG_NAND_ATMEL=y
 CONFIG_DM_SPI_FLASH=y
 CONFIG_SPI_FLASH_ATMEL=y
diff --git a/configs/at91sam9261ek_dataflash_cs3_defconfig b/configs/at91sam9261ek_dataflash_cs3_defconfig
index 0ea3d0d..c1f79bc 100644
--- a/configs/at91sam9261ek_dataflash_cs3_defconfig
+++ b/configs/at91sam9261ek_dataflash_cs3_defconfig
@@ -42,7 +42,6 @@
 # CONFIG_MMC is not set
 CONFIG_MTD=y
 CONFIG_MTD_RAW_NAND=y
-# CONFIG_SYS_NAND_USE_FLASH_BBT is not set
 CONFIG_NAND_ATMEL=y
 CONFIG_DM_SPI_FLASH=y
 CONFIG_SPI_FLASH_ATMEL=y
diff --git a/configs/at91sam9261ek_nandflash_defconfig b/configs/at91sam9261ek_nandflash_defconfig
index 48a8f35..4aaae50 100644
--- a/configs/at91sam9261ek_nandflash_defconfig
+++ b/configs/at91sam9261ek_nandflash_defconfig
@@ -39,7 +39,6 @@
 # CONFIG_MMC is not set
 CONFIG_MTD=y
 CONFIG_MTD_RAW_NAND=y
-# CONFIG_SYS_NAND_USE_FLASH_BBT is not set
 CONFIG_NAND_ATMEL=y
 CONFIG_DM_SPI_FLASH=y
 CONFIG_SPI_FLASH_ATMEL=y
diff --git a/configs/at91sam9263ek_dataflash_cs0_defconfig b/configs/at91sam9263ek_dataflash_cs0_defconfig
index 2e0e808..cee2b72 100644
--- a/configs/at91sam9263ek_dataflash_cs0_defconfig
+++ b/configs/at91sam9263ek_dataflash_cs0_defconfig
@@ -47,7 +47,6 @@
 CONFIG_GENERIC_ATMEL_MCI=y
 CONFIG_MTD=y
 CONFIG_MTD_RAW_NAND=y
-# CONFIG_SYS_NAND_USE_FLASH_BBT is not set
 CONFIG_NAND_ATMEL=y
 CONFIG_DM_SPI_FLASH=y
 CONFIG_SPI_FLASH_ATMEL=y
diff --git a/configs/at91sam9263ek_dataflash_defconfig b/configs/at91sam9263ek_dataflash_defconfig
index 2e0e808..cee2b72 100644
--- a/configs/at91sam9263ek_dataflash_defconfig
+++ b/configs/at91sam9263ek_dataflash_defconfig
@@ -47,7 +47,6 @@
 CONFIG_GENERIC_ATMEL_MCI=y
 CONFIG_MTD=y
 CONFIG_MTD_RAW_NAND=y
-# CONFIG_SYS_NAND_USE_FLASH_BBT is not set
 CONFIG_NAND_ATMEL=y
 CONFIG_DM_SPI_FLASH=y
 CONFIG_SPI_FLASH_ATMEL=y
diff --git a/configs/at91sam9263ek_nandflash_defconfig b/configs/at91sam9263ek_nandflash_defconfig
index aad5e13..4f5a9d4 100644
--- a/configs/at91sam9263ek_nandflash_defconfig
+++ b/configs/at91sam9263ek_nandflash_defconfig
@@ -44,7 +44,6 @@
 CONFIG_GENERIC_ATMEL_MCI=y
 CONFIG_MTD=y
 CONFIG_MTD_RAW_NAND=y
-# CONFIG_SYS_NAND_USE_FLASH_BBT is not set
 CONFIG_NAND_ATMEL=y
 CONFIG_DM_SPI_FLASH=y
 CONFIG_SPI_FLASH_ATMEL=y
diff --git a/configs/at91sam9263ek_norflash_boot_defconfig b/configs/at91sam9263ek_norflash_boot_defconfig
index f1d3575..7ee13e3 100644
--- a/configs/at91sam9263ek_norflash_boot_defconfig
+++ b/configs/at91sam9263ek_norflash_boot_defconfig
@@ -47,7 +47,6 @@
 CONFIG_FLASH_CFI_DRIVER=y
 CONFIG_SYS_FLASH_CFI=y
 CONFIG_MTD_RAW_NAND=y
-# CONFIG_SYS_NAND_USE_FLASH_BBT is not set
 CONFIG_NAND_ATMEL=y
 CONFIG_DM_SPI_FLASH=y
 CONFIG_SPI_FLASH_ATMEL=y
diff --git a/configs/at91sam9263ek_norflash_defconfig b/configs/at91sam9263ek_norflash_defconfig
index 04302f8..4eba692 100644
--- a/configs/at91sam9263ek_norflash_defconfig
+++ b/configs/at91sam9263ek_norflash_defconfig
@@ -47,7 +47,6 @@
 CONFIG_FLASH_CFI_DRIVER=y
 CONFIG_SYS_FLASH_CFI=y
 CONFIG_MTD_RAW_NAND=y
-# CONFIG_SYS_NAND_USE_FLASH_BBT is not set
 CONFIG_NAND_ATMEL=y
 CONFIG_DM_SPI_FLASH=y
 CONFIG_SPI_FLASH_ATMEL=y
diff --git a/configs/at91sam9g10ek_dataflash_cs0_defconfig b/configs/at91sam9g10ek_dataflash_cs0_defconfig
index 2b3469b..65e8fab 100644
--- a/configs/at91sam9g10ek_dataflash_cs0_defconfig
+++ b/configs/at91sam9g10ek_dataflash_cs0_defconfig
@@ -42,7 +42,6 @@
 # CONFIG_MMC is not set
 CONFIG_MTD=y
 CONFIG_MTD_RAW_NAND=y
-# CONFIG_SYS_NAND_USE_FLASH_BBT is not set
 CONFIG_NAND_ATMEL=y
 CONFIG_DM_SPI_FLASH=y
 CONFIG_SPI_FLASH_ATMEL=y
diff --git a/configs/at91sam9g10ek_dataflash_cs3_defconfig b/configs/at91sam9g10ek_dataflash_cs3_defconfig
index 8f5fdd2..2c292d2 100644
--- a/configs/at91sam9g10ek_dataflash_cs3_defconfig
+++ b/configs/at91sam9g10ek_dataflash_cs3_defconfig
@@ -42,7 +42,6 @@
 # CONFIG_MMC is not set
 CONFIG_MTD=y
 CONFIG_MTD_RAW_NAND=y
-# CONFIG_SYS_NAND_USE_FLASH_BBT is not set
 CONFIG_NAND_ATMEL=y
 CONFIG_DM_SPI_FLASH=y
 CONFIG_SPI_FLASH_ATMEL=y
diff --git a/configs/at91sam9g10ek_nandflash_defconfig b/configs/at91sam9g10ek_nandflash_defconfig
index 5bc3cb3..2a5acd5 100644
--- a/configs/at91sam9g10ek_nandflash_defconfig
+++ b/configs/at91sam9g10ek_nandflash_defconfig
@@ -39,7 +39,6 @@
 # CONFIG_MMC is not set
 CONFIG_MTD=y
 CONFIG_MTD_RAW_NAND=y
-# CONFIG_SYS_NAND_USE_FLASH_BBT is not set
 CONFIG_NAND_ATMEL=y
 CONFIG_DM_SPI_FLASH=y
 CONFIG_SPI_FLASH_ATMEL=y
diff --git a/configs/at91sam9g20ek_2mmc_defconfig b/configs/at91sam9g20ek_2mmc_defconfig
index 546ae19..67dbca0 100644
--- a/configs/at91sam9g20ek_2mmc_defconfig
+++ b/configs/at91sam9g20ek_2mmc_defconfig
@@ -42,7 +42,6 @@
 CONFIG_GENERIC_ATMEL_MCI=y
 CONFIG_MTD=y
 CONFIG_MTD_RAW_NAND=y
-# CONFIG_SYS_NAND_USE_FLASH_BBT is not set
 CONFIG_NAND_ATMEL=y
 CONFIG_DM_SPI_FLASH=y
 CONFIG_SPI_FLASH_ATMEL=y
diff --git a/configs/at91sam9g20ek_2mmc_nandflash_defconfig b/configs/at91sam9g20ek_2mmc_nandflash_defconfig
index bb9ff3e..6bba1ab 100644
--- a/configs/at91sam9g20ek_2mmc_nandflash_defconfig
+++ b/configs/at91sam9g20ek_2mmc_nandflash_defconfig
@@ -42,7 +42,6 @@
 CONFIG_GENERIC_ATMEL_MCI=y
 CONFIG_MTD=y
 CONFIG_MTD_RAW_NAND=y
-# CONFIG_SYS_NAND_USE_FLASH_BBT is not set
 CONFIG_NAND_ATMEL=y
 CONFIG_DM_SPI_FLASH=y
 CONFIG_SPI_FLASH_ATMEL=y
diff --git a/configs/at91sam9g20ek_dataflash_cs0_defconfig b/configs/at91sam9g20ek_dataflash_cs0_defconfig
index 2576f93..2523205 100644
--- a/configs/at91sam9g20ek_dataflash_cs0_defconfig
+++ b/configs/at91sam9g20ek_dataflash_cs0_defconfig
@@ -43,7 +43,6 @@
 # CONFIG_MMC is not set
 CONFIG_MTD=y
 CONFIG_MTD_RAW_NAND=y
-# CONFIG_SYS_NAND_USE_FLASH_BBT is not set
 CONFIG_NAND_ATMEL=y
 CONFIG_DM_SPI_FLASH=y
 CONFIG_SPI_FLASH_ATMEL=y
diff --git a/configs/at91sam9g20ek_dataflash_cs1_defconfig b/configs/at91sam9g20ek_dataflash_cs1_defconfig
index 46d611c..ecfbacd 100644
--- a/configs/at91sam9g20ek_dataflash_cs1_defconfig
+++ b/configs/at91sam9g20ek_dataflash_cs1_defconfig
@@ -43,7 +43,6 @@
 # CONFIG_MMC is not set
 CONFIG_MTD=y
 CONFIG_MTD_RAW_NAND=y
-# CONFIG_SYS_NAND_USE_FLASH_BBT is not set
 CONFIG_NAND_ATMEL=y
 CONFIG_DM_SPI_FLASH=y
 CONFIG_SPI_FLASH_ATMEL=y
diff --git a/configs/at91sam9g20ek_nandflash_defconfig b/configs/at91sam9g20ek_nandflash_defconfig
index 843e17f..8e0db87 100644
--- a/configs/at91sam9g20ek_nandflash_defconfig
+++ b/configs/at91sam9g20ek_nandflash_defconfig
@@ -40,7 +40,6 @@
 # CONFIG_MMC is not set
 CONFIG_MTD=y
 CONFIG_MTD_RAW_NAND=y
-# CONFIG_SYS_NAND_USE_FLASH_BBT is not set
 CONFIG_NAND_ATMEL=y
 CONFIG_DM_SPI_FLASH=y
 CONFIG_SPI_FLASH_ATMEL=y
diff --git a/configs/at91sam9m10g45ek_mmc_defconfig b/configs/at91sam9m10g45ek_mmc_defconfig
index dd77c8d..2c4bbd0 100644
--- a/configs/at91sam9m10g45ek_mmc_defconfig
+++ b/configs/at91sam9m10g45ek_mmc_defconfig
@@ -42,7 +42,6 @@
 CONFIG_GENERIC_ATMEL_MCI=y
 CONFIG_MTD=y
 CONFIG_MTD_RAW_NAND=y
-# CONFIG_SYS_NAND_USE_FLASH_BBT is not set
 CONFIG_NAND_ATMEL=y
 CONFIG_DM_ETH=y
 CONFIG_MACB=y
diff --git a/configs/at91sam9m10g45ek_nandflash_defconfig b/configs/at91sam9m10g45ek_nandflash_defconfig
index e13851d..4494f8d 100644
--- a/configs/at91sam9m10g45ek_nandflash_defconfig
+++ b/configs/at91sam9m10g45ek_nandflash_defconfig
@@ -42,7 +42,6 @@
 CONFIG_DM_MMC=y
 CONFIG_GENERIC_ATMEL_MCI=y
 CONFIG_MTD=y
-# CONFIG_SYS_NAND_USE_FLASH_BBT is not set
 CONFIG_NAND_ATMEL=y
 CONFIG_DM_ETH=y
 CONFIG_MACB=y
diff --git a/configs/at91sam9n12ek_mmc_defconfig b/configs/at91sam9n12ek_mmc_defconfig
index fa802c3..74a28a3 100644
--- a/configs/at91sam9n12ek_mmc_defconfig
+++ b/configs/at91sam9n12ek_mmc_defconfig
@@ -41,7 +41,6 @@
 CONFIG_GENERIC_ATMEL_MCI=y
 CONFIG_MTD=y
 CONFIG_MTD_RAW_NAND=y
-# CONFIG_SYS_NAND_USE_FLASH_BBT is not set
 CONFIG_NAND_ATMEL=y
 CONFIG_DM_SPI_FLASH=y
 CONFIG_SF_DEFAULT_SPEED=30000000
diff --git a/configs/at91sam9n12ek_nandflash_defconfig b/configs/at91sam9n12ek_nandflash_defconfig
index 429b140..42d86fd 100644
--- a/configs/at91sam9n12ek_nandflash_defconfig
+++ b/configs/at91sam9n12ek_nandflash_defconfig
@@ -41,7 +41,6 @@
 CONFIG_DM_MMC=y
 CONFIG_GENERIC_ATMEL_MCI=y
 CONFIG_MTD=y
-# CONFIG_SYS_NAND_USE_FLASH_BBT is not set
 CONFIG_NAND_ATMEL=y
 CONFIG_SPL_GENERATE_ATMEL_PMECC_HEADER=y
 CONFIG_DM_SPI_FLASH=y
diff --git a/configs/at91sam9n12ek_spiflash_defconfig b/configs/at91sam9n12ek_spiflash_defconfig
index 9975947..6a340f5 100644
--- a/configs/at91sam9n12ek_spiflash_defconfig
+++ b/configs/at91sam9n12ek_spiflash_defconfig
@@ -43,7 +43,6 @@
 CONFIG_GENERIC_ATMEL_MCI=y
 CONFIG_MTD=y
 CONFIG_MTD_RAW_NAND=y
-# CONFIG_SYS_NAND_USE_FLASH_BBT is not set
 CONFIG_NAND_ATMEL=y
 CONFIG_DM_SPI_FLASH=y
 CONFIG_SF_DEFAULT_SPEED=30000000
diff --git a/configs/at91sam9rlek_dataflash_defconfig b/configs/at91sam9rlek_dataflash_defconfig
index ea14df9..7e2b635 100644
--- a/configs/at91sam9rlek_dataflash_defconfig
+++ b/configs/at91sam9rlek_dataflash_defconfig
@@ -45,7 +45,6 @@
 CONFIG_GENERIC_ATMEL_MCI=y
 CONFIG_MTD=y
 CONFIG_MTD_RAW_NAND=y
-# CONFIG_SYS_NAND_USE_FLASH_BBT is not set
 CONFIG_NAND_ATMEL=y
 CONFIG_DM_SPI_FLASH=y
 CONFIG_SPI_FLASH_ATMEL=y
diff --git a/configs/at91sam9rlek_mmc_defconfig b/configs/at91sam9rlek_mmc_defconfig
index 5e62ff3..f8fe961 100644
--- a/configs/at91sam9rlek_mmc_defconfig
+++ b/configs/at91sam9rlek_mmc_defconfig
@@ -41,7 +41,6 @@
 CONFIG_GENERIC_ATMEL_MCI=y
 CONFIG_MTD=y
 CONFIG_MTD_RAW_NAND=y
-# CONFIG_SYS_NAND_USE_FLASH_BBT is not set
 CONFIG_NAND_ATMEL=y
 CONFIG_DM_SPI_FLASH=y
 CONFIG_SPI_FLASH_ATMEL=y
diff --git a/configs/at91sam9rlek_nandflash_defconfig b/configs/at91sam9rlek_nandflash_defconfig
index ff32bf5..60715a0 100644
--- a/configs/at91sam9rlek_nandflash_defconfig
+++ b/configs/at91sam9rlek_nandflash_defconfig
@@ -42,7 +42,6 @@
 CONFIG_GENERIC_ATMEL_MCI=y
 CONFIG_MTD=y
 CONFIG_MTD_RAW_NAND=y
-# CONFIG_SYS_NAND_USE_FLASH_BBT is not set
 CONFIG_NAND_ATMEL=y
 CONFIG_DM_SPI_FLASH=y
 CONFIG_SPI_FLASH_ATMEL=y
diff --git a/configs/at91sam9x5ek_dataflash_defconfig b/configs/at91sam9x5ek_dataflash_defconfig
index e9159d8..b6d6a30 100644
--- a/configs/at91sam9x5ek_dataflash_defconfig
+++ b/configs/at91sam9x5ek_dataflash_defconfig
@@ -46,7 +46,6 @@
 CONFIG_GENERIC_ATMEL_MCI=y
 CONFIG_MTD=y
 CONFIG_MTD_RAW_NAND=y
-# CONFIG_SYS_NAND_USE_FLASH_BBT is not set
 CONFIG_NAND_ATMEL=y
 CONFIG_SPL_GENERATE_ATMEL_PMECC_HEADER=y
 CONFIG_DM_SPI_FLASH=y
diff --git a/configs/at91sam9x5ek_mmc_defconfig b/configs/at91sam9x5ek_mmc_defconfig
index 7f8fa22..d48d2d7 100644
--- a/configs/at91sam9x5ek_mmc_defconfig
+++ b/configs/at91sam9x5ek_mmc_defconfig
@@ -44,7 +44,6 @@
 CONFIG_GENERIC_ATMEL_MCI=y
 CONFIG_MTD=y
 CONFIG_MTD_RAW_NAND=y
-# CONFIG_SYS_NAND_USE_FLASH_BBT is not set
 CONFIG_NAND_ATMEL=y
 CONFIG_DM_SPI_FLASH=y
 CONFIG_SF_DEFAULT_SPEED=30000000
diff --git a/configs/at91sam9x5ek_nandflash_defconfig b/configs/at91sam9x5ek_nandflash_defconfig
index 2f39c82..2b1256d 100644
--- a/configs/at91sam9x5ek_nandflash_defconfig
+++ b/configs/at91sam9x5ek_nandflash_defconfig
@@ -44,7 +44,6 @@
 CONFIG_DM_MMC=y
 CONFIG_GENERIC_ATMEL_MCI=y
 CONFIG_MTD=y
-# CONFIG_SYS_NAND_USE_FLASH_BBT is not set
 CONFIG_NAND_ATMEL=y
 CONFIG_SPL_GENERATE_ATMEL_PMECC_HEADER=y
 CONFIG_DM_SPI_FLASH=y
diff --git a/configs/at91sam9x5ek_spiflash_defconfig b/configs/at91sam9x5ek_spiflash_defconfig
index 8575a33..eb935d6 100644
--- a/configs/at91sam9x5ek_spiflash_defconfig
+++ b/configs/at91sam9x5ek_spiflash_defconfig
@@ -46,7 +46,6 @@
 CONFIG_GENERIC_ATMEL_MCI=y
 CONFIG_MTD=y
 CONFIG_MTD_RAW_NAND=y
-# CONFIG_SYS_NAND_USE_FLASH_BBT is not set
 CONFIG_NAND_ATMEL=y
 CONFIG_DM_SPI_FLASH=y
 CONFIG_SF_DEFAULT_SPEED=30000000
diff --git a/configs/at91sam9xeek_dataflash_cs0_defconfig b/configs/at91sam9xeek_dataflash_cs0_defconfig
index c92d08f..d963305 100644
--- a/configs/at91sam9xeek_dataflash_cs0_defconfig
+++ b/configs/at91sam9xeek_dataflash_cs0_defconfig
@@ -43,7 +43,6 @@
 # CONFIG_MMC is not set
 CONFIG_MTD=y
 CONFIG_MTD_RAW_NAND=y
-# CONFIG_SYS_NAND_USE_FLASH_BBT is not set
 CONFIG_NAND_ATMEL=y
 CONFIG_DM_SPI_FLASH=y
 CONFIG_SPI_FLASH_ATMEL=y
diff --git a/configs/at91sam9xeek_dataflash_cs1_defconfig b/configs/at91sam9xeek_dataflash_cs1_defconfig
index 5959c62..fd07ebc 100644
--- a/configs/at91sam9xeek_dataflash_cs1_defconfig
+++ b/configs/at91sam9xeek_dataflash_cs1_defconfig
@@ -43,7 +43,6 @@
 # CONFIG_MMC is not set
 CONFIG_MTD=y
 CONFIG_MTD_RAW_NAND=y
-# CONFIG_SYS_NAND_USE_FLASH_BBT is not set
 CONFIG_NAND_ATMEL=y
 CONFIG_DM_SPI_FLASH=y
 CONFIG_SPI_FLASH_ATMEL=y
diff --git a/configs/at91sam9xeek_nandflash_defconfig b/configs/at91sam9xeek_nandflash_defconfig
index 1f32b82..a772227 100644
--- a/configs/at91sam9xeek_nandflash_defconfig
+++ b/configs/at91sam9xeek_nandflash_defconfig
@@ -40,7 +40,6 @@
 # CONFIG_MMC is not set
 CONFIG_MTD=y
 CONFIG_MTD_RAW_NAND=y
-# CONFIG_SYS_NAND_USE_FLASH_BBT is not set
 CONFIG_NAND_ATMEL=y
 CONFIG_DM_SPI_FLASH=y
 CONFIG_SPI_FLASH_ATMEL=y
diff --git a/configs/pinecube_defconfig b/configs/pinecube_defconfig
new file mode 100644
index 0000000..a8c404f
--- /dev/null
+++ b/configs/pinecube_defconfig
@@ -0,0 +1,15 @@
+CONFIG_ARM=y
+CONFIG_ARCH_SUNXI=y
+CONFIG_SPL=y
+CONFIG_MACH_SUN8I_V3S=y
+CONFIG_SUNXI_DRAM_DDR3_1333=y
+CONFIG_DRAM_CLK=504
+CONFIG_DRAM_ODT_EN=y
+CONFIG_I2C0_ENABLE=y
+CONFIG_DEFAULT_DEVICE_TREE="sun8i-s3-pinecube"
+CONFIG_SPL_I2C_SUPPORT=y
+# CONFIG_NETDEVICES is not set
+CONFIG_AXP209_POWER=y
+CONFIG_AXP_DCDC2_VOLT=1250
+CONFIG_AXP_DCDC3_VOLT=3300
+CONFIG_CONS_INDEX=3
diff --git a/configs/sama5d2_ptc_ek_mmc_defconfig b/configs/sama5d2_ptc_ek_mmc_defconfig
index e566f54..0c0dcbb 100644
--- a/configs/sama5d2_ptc_ek_mmc_defconfig
+++ b/configs/sama5d2_ptc_ek_mmc_defconfig
@@ -52,7 +52,6 @@
 CONFIG_MMC_SDHCI_ATMEL=y
 CONFIG_MTD=y
 CONFIG_MTD_RAW_NAND=y
-# CONFIG_SYS_NAND_USE_FLASH_BBT is not set
 CONFIG_NAND_ATMEL=y
 CONFIG_ATMEL_NAND_HW_PMECC=y
 CONFIG_PMECC_CAP=4
diff --git a/configs/sama5d2_ptc_ek_nandflash_defconfig b/configs/sama5d2_ptc_ek_nandflash_defconfig
index a331609..224afea 100644
--- a/configs/sama5d2_ptc_ek_nandflash_defconfig
+++ b/configs/sama5d2_ptc_ek_nandflash_defconfig
@@ -52,7 +52,6 @@
 CONFIG_MMC_SDHCI=y
 CONFIG_MMC_SDHCI_ATMEL=y
 CONFIG_MTD=y
-# CONFIG_SYS_NAND_USE_FLASH_BBT is not set
 CONFIG_NAND_ATMEL=y
 CONFIG_ATMEL_NAND_HW_PMECC=y
 CONFIG_PMECC_CAP=4
diff --git a/configs/sama5d36ek_cmp_mmc_defconfig b/configs/sama5d36ek_cmp_mmc_defconfig
index 846f96b..22c1134 100644
--- a/configs/sama5d36ek_cmp_mmc_defconfig
+++ b/configs/sama5d36ek_cmp_mmc_defconfig
@@ -45,7 +45,6 @@
 CONFIG_GENERIC_ATMEL_MCI=y
 CONFIG_MTD=y
 CONFIG_MTD_RAW_NAND=y
-# CONFIG_SYS_NAND_USE_FLASH_BBT is not set
 CONFIG_NAND_ATMEL=y
 CONFIG_DM_SPI_FLASH=y
 CONFIG_SF_DEFAULT_SPEED=30000000
diff --git a/configs/sama5d36ek_cmp_nandflash_defconfig b/configs/sama5d36ek_cmp_nandflash_defconfig
index d38a0be..ed78f4e 100644
--- a/configs/sama5d36ek_cmp_nandflash_defconfig
+++ b/configs/sama5d36ek_cmp_nandflash_defconfig
@@ -45,7 +45,6 @@
 CONFIG_DM_MMC=y
 CONFIG_GENERIC_ATMEL_MCI=y
 CONFIG_MTD=y
-# CONFIG_SYS_NAND_USE_FLASH_BBT is not set
 CONFIG_NAND_ATMEL=y
 CONFIG_SPL_GENERATE_ATMEL_PMECC_HEADER=y
 CONFIG_DM_SPI_FLASH=y
diff --git a/configs/sama5d36ek_cmp_spiflash_defconfig b/configs/sama5d36ek_cmp_spiflash_defconfig
index 6a63a74..8fc183f 100644
--- a/configs/sama5d36ek_cmp_spiflash_defconfig
+++ b/configs/sama5d36ek_cmp_spiflash_defconfig
@@ -47,7 +47,6 @@
 CONFIG_GENERIC_ATMEL_MCI=y
 CONFIG_MTD=y
 CONFIG_MTD_RAW_NAND=y
-# CONFIG_SYS_NAND_USE_FLASH_BBT is not set
 CONFIG_NAND_ATMEL=y
 CONFIG_DM_SPI_FLASH=y
 CONFIG_SF_DEFAULT_SPEED=30000000
diff --git a/configs/sama5d3_xplained_mmc_defconfig b/configs/sama5d3_xplained_mmc_defconfig
index ec117ee..c839b4f 100644
--- a/configs/sama5d3_xplained_mmc_defconfig
+++ b/configs/sama5d3_xplained_mmc_defconfig
@@ -64,7 +64,6 @@
 CONFIG_GENERIC_ATMEL_MCI=y
 CONFIG_MTD=y
 CONFIG_MTD_RAW_NAND=y
-# CONFIG_SYS_NAND_USE_FLASH_BBT is not set
 CONFIG_NAND_ATMEL=y
 CONFIG_DM_ETH=y
 CONFIG_MACB=y
diff --git a/configs/sama5d3_xplained_nandflash_defconfig b/configs/sama5d3_xplained_nandflash_defconfig
index 7f9c73b..4d8a63f 100644
--- a/configs/sama5d3_xplained_nandflash_defconfig
+++ b/configs/sama5d3_xplained_nandflash_defconfig
@@ -63,7 +63,6 @@
 CONFIG_DM_MMC=y
 CONFIG_GENERIC_ATMEL_MCI=y
 CONFIG_MTD=y
-# CONFIG_SYS_NAND_USE_FLASH_BBT is not set
 CONFIG_NAND_ATMEL=y
 CONFIG_PMECC_CAP=4
 CONFIG_SPL_GENERATE_ATMEL_PMECC_HEADER=y
diff --git a/configs/sama5d3xek_mmc_defconfig b/configs/sama5d3xek_mmc_defconfig
index 50f97e6..70c6e30 100644
--- a/configs/sama5d3xek_mmc_defconfig
+++ b/configs/sama5d3xek_mmc_defconfig
@@ -69,7 +69,6 @@
 CONFIG_SYS_FLASH_PROTECTION=y
 CONFIG_SYS_FLASH_CFI=y
 CONFIG_MTD_RAW_NAND=y
-# CONFIG_SYS_NAND_USE_FLASH_BBT is not set
 CONFIG_NAND_ATMEL=y
 CONFIG_DM_SPI_FLASH=y
 CONFIG_SF_DEFAULT_SPEED=30000000
diff --git a/configs/sama5d3xek_nandflash_defconfig b/configs/sama5d3xek_nandflash_defconfig
index 3521a44..fe615c3 100644
--- a/configs/sama5d3xek_nandflash_defconfig
+++ b/configs/sama5d3xek_nandflash_defconfig
@@ -67,7 +67,6 @@
 CONFIG_FLASH_CFI_DRIVER=y
 CONFIG_SYS_FLASH_PROTECTION=y
 CONFIG_SYS_FLASH_CFI=y
-# CONFIG_SYS_NAND_USE_FLASH_BBT is not set
 CONFIG_NAND_ATMEL=y
 CONFIG_PMECC_CAP=4
 CONFIG_SPL_GENERATE_ATMEL_PMECC_HEADER=y
diff --git a/configs/sama5d3xek_spiflash_defconfig b/configs/sama5d3xek_spiflash_defconfig
index b8c4d32..5a06518 100644
--- a/configs/sama5d3xek_spiflash_defconfig
+++ b/configs/sama5d3xek_spiflash_defconfig
@@ -70,7 +70,6 @@
 CONFIG_SYS_FLASH_PROTECTION=y
 CONFIG_SYS_FLASH_CFI=y
 CONFIG_MTD_RAW_NAND=y
-# CONFIG_SYS_NAND_USE_FLASH_BBT is not set
 CONFIG_NAND_ATMEL=y
 CONFIG_DM_SPI_FLASH=y
 CONFIG_SF_DEFAULT_SPEED=30000000
diff --git a/configs/sama5d4_xplained_mmc_defconfig b/configs/sama5d4_xplained_mmc_defconfig
index 33a1ea7..d1cbf32 100644
--- a/configs/sama5d4_xplained_mmc_defconfig
+++ b/configs/sama5d4_xplained_mmc_defconfig
@@ -60,7 +60,6 @@
 CONFIG_GENERIC_ATMEL_MCI=y
 CONFIG_MTD=y
 CONFIG_MTD_RAW_NAND=y
-# CONFIG_SYS_NAND_USE_FLASH_BBT is not set
 CONFIG_NAND_ATMEL=y
 CONFIG_ATMEL_NAND_HW_PMECC=y
 CONFIG_PMECC_CAP=8
diff --git a/configs/sama5d4_xplained_nandflash_defconfig b/configs/sama5d4_xplained_nandflash_defconfig
index a47199f..f805cf1 100644
--- a/configs/sama5d4_xplained_nandflash_defconfig
+++ b/configs/sama5d4_xplained_nandflash_defconfig
@@ -60,7 +60,6 @@
 CONFIG_DM_MMC=y
 CONFIG_GENERIC_ATMEL_MCI=y
 CONFIG_MTD=y
-# CONFIG_SYS_NAND_USE_FLASH_BBT is not set
 CONFIG_NAND_ATMEL=y
 CONFIG_PMECC_CAP=8
 CONFIG_SPL_GENERATE_ATMEL_PMECC_HEADER=y
diff --git a/configs/sama5d4_xplained_spiflash_defconfig b/configs/sama5d4_xplained_spiflash_defconfig
index de5f92d..d9ad9cc 100644
--- a/configs/sama5d4_xplained_spiflash_defconfig
+++ b/configs/sama5d4_xplained_spiflash_defconfig
@@ -66,7 +66,6 @@
 CONFIG_GENERIC_ATMEL_MCI=y
 CONFIG_MTD=y
 CONFIG_MTD_RAW_NAND=y
-# CONFIG_SYS_NAND_USE_FLASH_BBT is not set
 CONFIG_NAND_ATMEL=y
 CONFIG_DM_SPI_FLASH=y
 CONFIG_SF_DEFAULT_SPEED=30000000
diff --git a/configs/sama5d4ek_mmc_defconfig b/configs/sama5d4ek_mmc_defconfig
index 25d875e..d91a6f6 100644
--- a/configs/sama5d4ek_mmc_defconfig
+++ b/configs/sama5d4ek_mmc_defconfig
@@ -60,7 +60,6 @@
 CONFIG_GENERIC_ATMEL_MCI=y
 CONFIG_MTD=y
 CONFIG_MTD_RAW_NAND=y
-# CONFIG_SYS_NAND_USE_FLASH_BBT is not set
 CONFIG_NAND_ATMEL=y
 CONFIG_DM_SPI_FLASH=y
 CONFIG_SF_DEFAULT_SPEED=30000000
diff --git a/configs/sama5d4ek_nandflash_defconfig b/configs/sama5d4ek_nandflash_defconfig
index 3ef8ed6..00216f0 100644
--- a/configs/sama5d4ek_nandflash_defconfig
+++ b/configs/sama5d4ek_nandflash_defconfig
@@ -60,7 +60,6 @@
 CONFIG_DM_MMC=y
 CONFIG_GENERIC_ATMEL_MCI=y
 CONFIG_MTD=y
-# CONFIG_SYS_NAND_USE_FLASH_BBT is not set
 CONFIG_NAND_ATMEL=y
 CONFIG_PMECC_CAP=8
 CONFIG_SPL_GENERATE_ATMEL_PMECC_HEADER=y
diff --git a/configs/sama5d4ek_spiflash_defconfig b/configs/sama5d4ek_spiflash_defconfig
index cb8ed99..5ebd1cc 100644
--- a/configs/sama5d4ek_spiflash_defconfig
+++ b/configs/sama5d4ek_spiflash_defconfig
@@ -63,7 +63,6 @@
 CONFIG_GENERIC_ATMEL_MCI=y
 CONFIG_MTD=y
 CONFIG_MTD_RAW_NAND=y
-# CONFIG_SYS_NAND_USE_FLASH_BBT is not set
 CONFIG_NAND_ATMEL=y
 CONFIG_DM_SPI_FLASH=y
 CONFIG_SF_DEFAULT_SPEED=30000000
diff --git a/configs/sama7g5ek_mmc1_defconfig b/configs/sama7g5ek_mmc1_defconfig
new file mode 100644
index 0000000..af36202
--- /dev/null
+++ b/configs/sama7g5ek_mmc1_defconfig
@@ -0,0 +1,70 @@
+CONFIG_ARM=y
+CONFIG_ARCH_AT91=y
+CONFIG_SYS_TEXT_BASE=0x66f00000
+CONFIG_TARGET_SAMA7G5EK=y
+CONFIG_SYS_MALLOC_F_LEN=0x11000
+CONFIG_NR_DRAM_BANKS=1
+CONFIG_ENV_SIZE=0x4000
+CONFIG_DM_GPIO=y
+CONFIG_DEBUG_UART_BOARD_INIT=y
+CONFIG_DEBUG_UART_BASE=0xe1824200
+CONFIG_DEBUG_UART_CLOCK=200000000
+CONFIG_DEFAULT_DEVICE_TREE="sama7g5ek"
+CONFIG_DEBUG_UART=y
+CONFIG_ENV_VARS_UBOOT_CONFIG=y
+CONFIG_FIT=y
+CONFIG_SD_BOOT=y
+CONFIG_USE_BOOTARGS=y
+CONFIG_BOOTARGS="console=ttyS0,115200 root=/dev/mmcblk1p2 rw rootwait"
+CONFIG_MISC_INIT_R=y
+CONFIG_HUSH_PARSER=y
+CONFIG_CMD_BOOTZ=y
+# CONFIG_CMD_IMI is not set
+CONFIG_CMD_MD5SUM=y
+CONFIG_CMD_MEMTEST=y
+CONFIG_SYS_MEMTEST_START=0x60000000
+CONFIG_SYS_MEMTEST_END=0x70000000
+CONFIG_CMD_STRINGS=y
+CONFIG_CMD_DM=y
+CONFIG_CMD_GPIO=y
+CONFIG_CMD_I2C=y
+# CONFIG_CMD_LOADS is not set
+CONFIG_CMD_MMC=y
+CONFIG_CMD_DHCP=y
+CONFIG_CMD_MII=y
+CONFIG_CMD_PING=y
+CONFIG_CMD_EXT4=y
+CONFIG_CMD_FAT=y
+CONFIG_OF_CONTROL=y
+CONFIG_ENV_IS_IN_FAT=y
+CONFIG_ENV_FAT_DEVICE_AND_PART="1:1"
+CONFIG_SYS_RELOC_GD_ENV_ADDR=y
+CONFIG_DM=y
+CONFIG_CLK=y
+CONFIG_CLK_CCF=y
+CONFIG_CLK_AT91=y
+CONFIG_AT91_UTMI=y
+CONFIG_AT91_GENERIC_CLK=y
+CONFIG_AT91_SAM9X60_PLL=y
+CONFIG_CPU=y
+CONFIG_ATMEL_PIO4=y
+CONFIG_DM_I2C=y
+CONFIG_SYS_I2C_AT91=y
+CONFIG_I2C_EEPROM=y
+CONFIG_MICROCHIP_FLEXCOM=y
+CONFIG_DM_MMC=y
+CONFIG_MMC_SDHCI=y
+CONFIG_MMC_SDHCI_ATMEL=y
+CONFIG_PHY_MICREL=y
+CONFIG_PHY_MICREL_KSZ90X1=y
+CONFIG_DM_ETH=y
+CONFIG_MACB=y
+CONFIG_PINCTRL=y
+CONFIG_PINCTRL_AT91PIO4=y
+CONFIG_DM_SERIAL=y
+CONFIG_DEBUG_UART_ANNOUNCE=y
+CONFIG_ATMEL_USART=y
+CONFIG_TIMER=y
+CONFIG_MCHP_PIT64B_TIMER=y
+CONFIG_OF_LIBFDT_OVERLAY=y
+# CONFIG_EFI_LOADER_HII is not set
diff --git a/configs/sama7g5ek_mmc_defconfig b/configs/sama7g5ek_mmc_defconfig
new file mode 100644
index 0000000..bbd1a0c
--- /dev/null
+++ b/configs/sama7g5ek_mmc_defconfig
@@ -0,0 +1,70 @@
+CONFIG_ARM=y
+CONFIG_ARCH_AT91=y
+CONFIG_SYS_TEXT_BASE=0x66f00000
+CONFIG_TARGET_SAMA7G5EK=y
+CONFIG_SYS_MALLOC_F_LEN=0x11000
+CONFIG_NR_DRAM_BANKS=1
+CONFIG_ENV_SIZE=0x4000
+CONFIG_DM_GPIO=y
+CONFIG_DEBUG_UART_BOARD_INIT=y
+CONFIG_DEBUG_UART_BASE=0xe1824200
+CONFIG_DEBUG_UART_CLOCK=200000000
+CONFIG_DEFAULT_DEVICE_TREE="sama7g5ek"
+CONFIG_DEBUG_UART=y
+CONFIG_ENV_VARS_UBOOT_CONFIG=y
+CONFIG_FIT=y
+CONFIG_SD_BOOT=y
+CONFIG_USE_BOOTARGS=y
+CONFIG_BOOTARGS="console=ttyS0,115200 root=/dev/mmcblk0p2 rw rootwait"
+CONFIG_MISC_INIT_R=y
+CONFIG_HUSH_PARSER=y
+CONFIG_CMD_BOOTZ=y
+# CONFIG_CMD_IMI is not set
+CONFIG_CMD_MD5SUM=y
+CONFIG_CMD_MEMTEST=y
+CONFIG_SYS_MEMTEST_START=0x60000000
+CONFIG_SYS_MEMTEST_END=0x70000000
+CONFIG_CMD_STRINGS=y
+CONFIG_CMD_DM=y
+CONFIG_CMD_GPIO=y
+CONFIG_CMD_I2C=y
+# CONFIG_CMD_LOADS is not set
+CONFIG_CMD_MMC=y
+CONFIG_CMD_DHCP=y
+CONFIG_CMD_MII=y
+CONFIG_CMD_PING=y
+CONFIG_CMD_EXT4=y
+CONFIG_CMD_FAT=y
+CONFIG_OF_CONTROL=y
+CONFIG_ENV_IS_IN_FAT=y
+CONFIG_ENV_FAT_DEVICE_AND_PART="0:1"
+CONFIG_SYS_RELOC_GD_ENV_ADDR=y
+CONFIG_DM=y
+CONFIG_CLK=y
+CONFIG_CLK_CCF=y
+CONFIG_CLK_AT91=y
+CONFIG_AT91_UTMI=y
+CONFIG_AT91_GENERIC_CLK=y
+CONFIG_AT91_SAM9X60_PLL=y
+CONFIG_CPU=y
+CONFIG_ATMEL_PIO4=y
+CONFIG_DM_I2C=y
+CONFIG_SYS_I2C_AT91=y
+CONFIG_I2C_EEPROM=y
+CONFIG_MICROCHIP_FLEXCOM=y
+CONFIG_DM_MMC=y
+CONFIG_MMC_SDHCI=y
+CONFIG_MMC_SDHCI_ATMEL=y
+CONFIG_PHY_MICREL=y
+CONFIG_PHY_MICREL_KSZ90X1=y
+CONFIG_DM_ETH=y
+CONFIG_MACB=y
+CONFIG_PINCTRL=y
+CONFIG_PINCTRL_AT91PIO4=y
+CONFIG_DM_SERIAL=y
+CONFIG_DEBUG_UART_ANNOUNCE=y
+CONFIG_ATMEL_USART=y
+CONFIG_TIMER=y
+CONFIG_MCHP_PIT64B_TIMER=y
+CONFIG_OF_LIBFDT_OVERLAY=y
+# CONFIG_EFI_LOADER_HII is not set
diff --git a/include/configs/sama7g5ek.h b/include/configs/sama7g5ek.h
new file mode 100644
index 0000000..ef3bfa3
--- /dev/null
+++ b/include/configs/sama7g5ek.h
@@ -0,0 +1,45 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Configuration file for the SAMA7G5EK Board.
+ *
+ * Copyright (C) 2020 Microchip Corporation
+ *		      Eugen Hristev <eugen.hristev@microchip.com>
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+#define CONFIG_SYS_AT91_SLOW_CLOCK      32768
+#define CONFIG_SYS_AT91_MAIN_CLOCK      24000000 /* from 24 MHz crystal */
+
+/* SDRAM */
+#define CONFIG_SYS_SDRAM_BASE		0x60000000
+#define CONFIG_SYS_SDRAM_SIZE		0x20000000
+
+#ifdef CONFIG_SPL_BUILD
+#define CONFIG_SYS_INIT_SP_ADDR		0x218000
+#else
+#define CONFIG_SYS_INIT_SP_ADDR \
+	(CONFIG_SYS_SDRAM_BASE + 16 * 1024 + CONFIG_SYS_MALLOC_F_LEN - \
+	 GENERATED_GBL_DATA_SIZE)
+#endif
+
+#define CONFIG_SYS_LOAD_ADDR		0x62000000 /* load address */
+
+#undef CONFIG_BOOTCOMMAND
+#ifdef CONFIG_SD_BOOT
+/* u-boot env in sd/mmc card */
+
+/* bootstrap + u-boot + env in sd card */
+#define CONFIG_BOOTCOMMAND	"fatload mmc " CONFIG_ENV_FAT_DEVICE_AND_PART " 0x61000000 at91-sama7g5ek.dtb; " \
+				"fatload mmc " CONFIG_ENV_FAT_DEVICE_AND_PART " 0x62000000 zImage; " \
+				"bootz 0x62000000 - 0x61000000"
+#endif
+
+/* Size of malloc() pool */
+#define CONFIG_SYS_MALLOC_LEN		(4 * 1024 * 1024)
+
+#define CONFIG_ARP_TIMEOUT		200
+#define CONFIG_NET_RETRY_COUNT		50
+
+#endif
diff --git a/include/configs/sunxi-common.h b/include/configs/sunxi-common.h
index a6a4879..203cb10 100644
--- a/include/configs/sunxi-common.h
+++ b/include/configs/sunxi-common.h
@@ -163,9 +163,7 @@
 
 #define CONFIG_SYS_MONITOR_LEN		(768 << 10)	/* 768 KiB */
 
-#ifndef CONFIG_ARM64		/* AArch64 FEL support is not ready yet */
 #define CONFIG_SPL_BOARD_LOAD_IMAGE
-#endif
 
 /*
  * We cannot use expressions here, because expressions won't be evaluated in
diff --git a/include/image.h b/include/image.h
index 41473db..856bc3e 100644
--- a/include/image.h
+++ b/include/image.h
@@ -308,6 +308,7 @@
 	IH_TYPE_IMX8MIMAGE,		/* Freescale IMX8MBoot Image	*/
 	IH_TYPE_IMX8IMAGE,		/* Freescale IMX8Boot Image	*/
 	IH_TYPE_COPRO,			/* Coprocessor Image for remoteproc*/
+	IH_TYPE_SUNXI_EGON,		/* Allwinner eGON Boot Image */
 
 	IH_TYPE_COUNT,			/* Number of image types */
 };
diff --git a/include/sunxi_image.h b/include/sunxi_image.h
new file mode 100644
index 0000000..5b2055c
--- /dev/null
+++ b/include/sunxi_image.h
@@ -0,0 +1,82 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * (C) Copyright 2007-2011
+ * Allwinner Technology Co., Ltd. <www.allwinnertech.com>
+ * Tom Cubie <tangliang@allwinnertech.com>
+ *
+ * Constants and data structures used in Allwinner "eGON" images, as
+ * parsed by the Boot-ROM.
+ *
+ * Shared between mkimage and the SPL.
+ */
+#ifndef	SUNXI_IMAGE_H
+#define	SUNXI_IMAGE_H
+
+#define BOOT0_MAGIC		"eGON.BT0"
+#define BROM_STAMP_VALUE	0x5f0a6c39
+#define SPL_SIGNATURE		"SPL" /* marks "sunxi" SPL header */
+#define SPL_MAJOR_BITS		3
+#define SPL_MINOR_BITS		5
+#define SPL_VERSION(maj, min)						\
+	((((maj) & ((1U << SPL_MAJOR_BITS) - 1)) << SPL_MINOR_BITS) | \
+	((min) & ((1U << SPL_MINOR_BITS) - 1)))
+
+#define SPL_HEADER_VERSION	SPL_VERSION(0, 2)
+
+#define SPL_ENV_HEADER_VERSION	SPL_VERSION(0, 1)
+#define SPL_DT_HEADER_VERSION	SPL_VERSION(0, 2)
+#define SPL_DRAM_HEADER_VERSION	SPL_VERSION(0, 3)
+
+/* boot head definition from sun4i boot code */
+struct boot_file_head {
+	uint32_t b_instruction;	/* one intruction jumping to real code */
+	uint8_t magic[8];	/* ="eGON.BT0" or "eGON.BT1", not C-style str */
+	uint32_t check_sum;	/* generated by PC */
+	uint32_t length;	/* generated by PC */
+	/*
+	 * We use a simplified header, only filling in what is needed
+	 * by the boot ROM. To be compatible with Allwinner tools we
+	 * would need to implement the proper fields here instead of
+	 * padding.
+	 *
+	 * Actually we want the ability to recognize our "sunxi" variant
+	 * of the SPL. To do so, let's place a special signature into the
+	 * "pub_head_size" field. We can reasonably expect Allwinner's
+	 * boot0 to always have the upper 16 bits of this set to 0 (after
+	 * all the value shouldn't be larger than the limit imposed by
+	 * SRAM size).
+	 * If the signature is present (at 0x14), then we know it's safe
+	 * to use the remaining 8 bytes (at 0x18) for our own purposes.
+	 * (E.g. sunxi-tools "fel" utility can pass information there.)
+	 */
+	union {
+		uint32_t pub_head_size;
+		uint8_t spl_signature[4];
+	};
+	uint32_t fel_script_address;	/* since v0.1, set by sunxi-fel */
+	/*
+	 * If the fel_uEnv_length member below is set to a non-zero value,
+	 * it specifies the size (byte count) of data at fel_script_address.
+	 * At the same time this indicates that the data is in uEnv.txt
+	 * compatible format, ready to be imported via "env import -t".
+	 */
+	uint32_t fel_uEnv_length;	/* since v0.1, set by sunxi-fel */
+	/*
+	 * Offset of an ASCIIZ string (relative to the SPL header), which
+	 * contains the default device tree name (CONFIG_DEFAULT_DEVICE_TREE).
+	 * This is optional and may be set to NULL. Is intended to be used
+	 * by flash programming tools for providing nice informative messages
+	 * to the users.
+	 */
+	uint32_t dt_name_offset;	/* since v0.2, set by mksunxiboot */
+	uint32_t dram_size;		/* in MiB, since v0.3, set by SPL */
+	uint32_t boot_media;		/* written here by the boot ROM */
+	/* A padding area (may be used for storing text strings) */
+	uint32_t string_pool[13];	/* since v0.2, filled by mksunxiboot */
+	/* The header must be a multiple of 32 bytes (for VBAR alignment) */
+};
+
+/* Compile time check to assure proper alignment of structure */
+typedef char boot_file_head_not_multiple_of_32[1 - 2*(sizeof(struct boot_file_head) % 32)];
+
+#endif
diff --git a/scripts/Makefile.spl b/scripts/Makefile.spl
index 87021e2..ea4e045 100644
--- a/scripts/Makefile.spl
+++ b/scripts/Makefile.spl
@@ -386,11 +386,11 @@
 $(obj)/$(SPL_BIN).sfp: $(obj)/$(SPL_BIN).bin FORCE
 	$(call if_changed,mkimage)
 
-quiet_cmd_mksunxiboot = MKSUNXI $@
-cmd_mksunxiboot = $(objtree)/tools/mksunxiboot \
-			--default-dt $(CONFIG_DEFAULT_DEVICE_TREE) $< $@
+MKIMAGEFLAGS_sunxi-spl.bin = -T sunxi_egon \
+	-n $(CONFIG_DEFAULT_DEVICE_TREE)
+
 $(obj)/sunxi-spl.bin: $(obj)/$(SPL_BIN).bin FORCE
-	$(call if_changed,mksunxiboot)
+	$(call if_changed,mkimage)
 
 quiet_cmd_sunxi_spl_image_builder = SUNXI_SPL_IMAGE_BUILDER $@
 cmd_sunxi_spl_image_builder = $(objtree)/tools/sunxi-spl-image-builder \
diff --git a/tools/Makefile b/tools/Makefile
index 14fb0ed..9b1aa51 100644
--- a/tools/Makefile
+++ b/tools/Makefile
@@ -104,6 +104,7 @@
 			stm32image.o \
 			$(ROCKCHIP_OBS) \
 			socfpgaimage.o \
+			sunxi_egon.o \
 			lib/crc16.o \
 			lib/sha1.o \
 			lib/sha256.o \
diff --git a/tools/sunxi_egon.c b/tools/sunxi_egon.c
new file mode 100644
index 0000000..a5299eb
--- /dev/null
+++ b/tools/sunxi_egon.c
@@ -0,0 +1,136 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * (C) Copyright 2018 Arm Ltd.
+ */
+
+#include "imagetool.h"
+#include <image.h>
+
+#include <sunxi_image.h>
+
+/*
+ * NAND requires 8K padding. SD/eMMC gets away with 512 bytes,
+ * but let's use the larger padding to cover both.
+ */
+#define PAD_SIZE			8192
+
+static int egon_check_params(struct image_tool_params *params)
+{
+	/* We just need a binary image file. */
+	return !params->dflag;
+}
+
+static int egon_verify_header(unsigned char *ptr, int image_size,
+			      struct image_tool_params *params)
+{
+	const struct boot_file_head *header = (void *)ptr;
+	uint32_t length;
+
+	/* First 4 bytes must be an ARM branch instruction. */
+	if ((le32_to_cpu(header->b_instruction) & 0xff000000) != 0xea000000)
+		return EXIT_FAILURE;
+
+	if (memcmp(header->magic, BOOT0_MAGIC, sizeof(header->magic)))
+		return EXIT_FAILURE;
+
+	length = le32_to_cpu(header->length);
+	/* Must be at least 512 byte aligned. */
+	if (length & 511)
+		return EXIT_FAILURE;
+
+	/*
+	 * Image could also contain U-Boot proper, so could be bigger.
+	 * But it must not be shorter.
+	 */
+	if (image_size < length)
+		return EXIT_FAILURE;
+
+	return EXIT_SUCCESS;
+}
+
+static void egon_print_header(const void *buf)
+{
+	const struct boot_file_head *header = buf;
+
+	printf("Allwinner eGON image, size: %d bytes\n",
+	       le32_to_cpu(header->length));
+
+	if (memcmp(header->spl_signature, SPL_SIGNATURE, 3))
+		return;
+
+	printf("\tSPL header version %d.%d\n",
+	       header->spl_signature[3] >> SPL_MINOR_BITS,
+	       header->spl_signature[3] & ((1U << SPL_MINOR_BITS) - 1));
+	if (header->spl_signature[3] >= SPL_DT_HEADER_VERSION) {
+		uint32_t dt_name_offs = le32_to_cpu(header->dt_name_offset);
+
+		if (dt_name_offs > 0)
+			printf("\tDT name: %s\n", (char *)buf + dt_name_offs);
+	}
+}
+
+static void egon_set_header(void *buf, struct stat *sbuf, int infd,
+			    struct image_tool_params *params)
+{
+	struct boot_file_head *header = buf;
+	uint32_t *buf32 = buf;
+	uint32_t checksum = 0, value;
+	int i;
+
+	/* Generate an ARM branch instruction to jump over the header. */
+	value = 0xea000000 | (sizeof(struct boot_file_head) / 4 - 2);
+	header->b_instruction = cpu_to_le32(value);
+
+	memcpy(header->magic, BOOT0_MAGIC, sizeof(header->magic));
+	header->check_sum = cpu_to_le32(BROM_STAMP_VALUE);
+	header->length = cpu_to_le32(params->file_size);
+
+	memcpy(header->spl_signature, SPL_SIGNATURE, 3);
+	header->spl_signature[3] = SPL_ENV_HEADER_VERSION;
+
+	/* If an image name has been provided, use it as the DT name. */
+	if (params->imagename && params->imagename[0]) {
+		if (strlen(params->imagename) > sizeof(header->string_pool) - 1)
+			printf("WARNING: DT name too long for SPL header!\n");
+		else {
+			strcpy((char *)header->string_pool, params->imagename);
+			value = offsetof(struct boot_file_head, string_pool);
+			header->dt_name_offset = cpu_to_le32(value);
+			header->spl_signature[3] = SPL_DT_HEADER_VERSION;
+		}
+	}
+
+	/* Calculate the checksum. Yes, it's that simple. */
+	for (i = 0; i < sbuf->st_size / 4; i++)
+		checksum += le32_to_cpu(buf32[i]);
+	header->check_sum = cpu_to_le32(checksum);
+}
+
+static int egon_check_image_type(uint8_t type)
+{
+	return type == IH_TYPE_SUNXI_EGON ? 0 : 1;
+}
+
+static int egon_vrec_header(struct image_tool_params *params,
+			    struct image_type_params *tparams)
+{
+	tparams->hdr = calloc(sizeof(struct boot_file_head), 1);
+
+	/* Return padding to 8K blocks. */
+	return ALIGN(params->file_size, PAD_SIZE) - params->file_size;
+}
+
+U_BOOT_IMAGE_TYPE(
+	sunxi_egon,
+	"Allwinner eGON Boot Image support",
+	sizeof(struct boot_file_head),
+	NULL,
+	egon_check_params,
+	egon_verify_header,
+	egon_print_header,
+	egon_set_header,
+	NULL,
+	egon_check_image_type,
+	NULL,
+	egon_vrec_header
+);