Merge patch series "bootstd: Try again to resolve infinite-loop bug"
Simon Glass <sjg@chromium.org> says:
This little series tries to resolve a problem found with an earlier
fix.
diff --git a/Kconfig b/Kconfig
index 82df59f..8b7b213 100644
--- a/Kconfig
+++ b/Kconfig
@@ -209,6 +209,7 @@
config NR_DRAM_BANKS
int "Number of DRAM banks"
default 1 if ARCH_SUNXI || ARCH_OWL
+ default 2 if OMAP34XX
default 4
help
This defines the number of DRAM banks.
@@ -236,6 +237,7 @@
config HAS_CUSTOM_SYS_INIT_SP_ADDR
bool "Use a custom location for the initial stack pointer address"
depends on ARC || (ARM && !INIT_SP_RELATIVE) || MIPS || PPC || RISCV
+ default y if OMAP34XX || AM33XX || AM43XX || DRA7XX
default y if TFABOOT
help
Typically, we use an initial stack pointer address that is calculated
@@ -249,6 +251,10 @@
config CUSTOM_SYS_INIT_SP_ADDR
hex "Static location for the initial stack pointer"
depends on HAS_CUSTOM_SYS_INIT_SP_ADDR
+ default 0x4020ff00 if OMAP34XX
+ default 0x4030ff00 if AM33XX
+ default 0x4033ff00 if AM43XX
+ default 0x4037ff00 if DRA7XX
default TEXT_BASE if TFABOOT
config SYS_MALLOC_F
@@ -615,6 +621,7 @@
config SYS_MONITOR_LEN
int "Maximum size in bytes reserved for U-Boot in memory"
default 1048576 if X86
+ default 262144 if OMAP34XX
default 786432 if ARCH_SUNXI
default 0
help
diff --git a/MAINTAINERS b/MAINTAINERS
index f1fe19e..daaf034 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -1649,6 +1649,7 @@
F: arch/arm/mach-omap2/config_secure.mk
F: arch/arm/mach-k3/security.c
F: configs/am335x_hs_evm_defconfig
+F: configs/am335x_hs_evm_spi_defconfig
F: configs/am335x_hs_evm_uart_defconfig
F: configs/am43xx_hs_evm_defconfig
F: configs/am43xx_hs_evm_qspi_defconfig
@@ -1710,6 +1711,19 @@
S: Maintained
F: drivers/ufs/
+UPL
+M: Simon Glass <sjg@chromium.org>
+S: Maintained
+T: git https://source.denx.de/u-boot/custodians/u-boot-dm.git
+F: boot/upl*
+F: cmd/upl.c
+F: common/spl/spl_upl.c
+F: doc/usage/upl.rst
+F: doc/usage/cmd/upl.rst
+F: include/upl.h
+F: test/boot/upl.c
+F: test/py/tests/test_upl.py
+
USB
M: Marek Vasut <marex@denx.de>
S: Maintained
diff --git a/Makefile b/Makefile
index 21aa068..9a52cc8 100644
--- a/Makefile
+++ b/Makefile
@@ -3,7 +3,7 @@
VERSION = 2024
PATCHLEVEL = 10
SUBLEVEL =
-EXTRAVERSION = -rc2
+EXTRAVERSION = -rc3
NAME =
# *DOCUMENTATION*
@@ -1473,8 +1473,10 @@
u-boot-lzma.img: u-boot.bin.lzma FORCE
$(call if_changed,mkimage)
+fit_image := $(if $(CONFIG_SANDBOX_VPL),u-boot,u-boot-nodtb.bin)
+
u-boot-dtb.img u-boot.img u-boot.kwb u-boot.pbl u-boot-ivt.img: \
- $(if $(CONFIG_SPL_LOAD_FIT),u-boot-nodtb.bin \
+ $(if $(CONFIG_SPL_LOAD_FIT),$(fit_image) \
$(if $(CONFIG_OF_SEPARATE)$(CONFIG_OF_EMBED)$(CONFIG_SANDBOX),dts/dt.dtb) \
,$(UBOOT_BIN)) FORCE
$(call if_changed,mkimage)
diff --git a/README b/README
index b76449b..4be1e8c 100644
--- a/README
+++ b/README
@@ -771,21 +771,8 @@
CFG_SYS_NUM_I2C_BUSES
Hold the number of i2c buses you want to use.
- CFG_SYS_I2C_DIRECT_BUS
- define this, if you don't use i2c muxes on your hardware.
- if CFG_SYS_I2C_MAX_HOPS is not defined or == 0 you can
- omit this define.
-
- CFG_SYS_I2C_MAX_HOPS
- define how many muxes are maximal consecutively connected
- on one i2c bus. If you not use i2c muxes, omit this
- define.
-
CFG_SYS_I2C_BUSES
- hold a list of buses you want to use, only used if
- CFG_SYS_I2C_DIRECT_BUS is not defined, for example
- a board with CFG_SYS_I2C_MAX_HOPS = 1 and
- CFG_SYS_NUM_I2C_BUSES = 9:
+ hold a list of buses you want to use
CFG_SYS_I2C_BUSES {{0, {I2C_NULL_HOP}}, \
{0, {{I2C_MUX_PCA9547, 0x70, 1}}}, \
@@ -883,13 +870,6 @@
You should define these to the GPIO value as given directly to
the generic GPIO functions.
- CFG_I2C_MULTI_BUS
-
- This option allows the use of multiple I2C buses, each of which
- must have a controller. At any point in time, only one bus is
- active. To switch to a different bus, use the 'i2c dev' command.
- Note that bus numbering is zero-based.
-
CFG_SYS_I2C_NOPROBES
This option specifies a list of I2C devices that will be skipped
@@ -900,11 +880,6 @@
will skip addresses 0x50 and 0x68 on a board with one I2C bus
- CFG_SYS_RTC_BUS_NUM
-
- If defined, then this indicates the I2C bus number for the RTC.
- If not defined, then U-Boot assumes that RTC is on I2C bus 0.
-
CONFIG_SOFT_I2C_READ_REPEATED_START
defining this will force the i2c_read() function in
diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
index ba0359f..656f588 100644
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@ -802,7 +802,7 @@
bool "TI OMAP2+"
select CPU_V7A
select GPIO_EXTRA_HEADER
- select SPL_BOARD_INIT if SPL
+ select SPL_SOC_INIT if SPL
select SPL_STACK_R if SPL
select SUPPORT_SPL
imply TI_SYSC if DM && OF_CONTROL
diff --git a/arch/arm/cpu/arm926ejs/mxs/spl_boot.c b/arch/arm/cpu/arm926ejs/mxs/spl_boot.c
index 76a69d7..dd74832 100644
--- a/arch/arm/cpu/arm926ejs/mxs/spl_boot.c
+++ b/arch/arm/cpu/arm926ejs/mxs/spl_boot.c
@@ -117,7 +117,7 @@
gd->bd = &bdata;
gd->baudrate = CONFIG_BAUDRATE;
serial_init();
- gd->have_console = 1;
+ gd->flags |= GD_FLG_HAVE_CONSOLE;
#endif
}
diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile
index 2d931c2..4d59e98 100644
--- a/arch/arm/dts/Makefile
+++ b/arch/arm/dts/Makefile
@@ -950,13 +950,6 @@
dtb-$(CONFIG_RZA1) += \
r7s72100-gr-peach.dtb
-dtb-$(CONFIG_ARCH_KEYSTONE) += keystone-k2hk-evm.dtb \
- keystone-k2l-evm.dtb \
- keystone-k2e-evm.dtb \
- keystone-k2g-evm.dtb \
- keystone-k2g-generic.dtb \
- keystone-k2g-ice.dtb
-
dtb-$(CONFIG_TARGET_AT91SAM9261EK) += at91sam9261ek.dtb
dtb-$(CONFIG_TARGET_PM9261) += at91sam9261ek.dtb
diff --git a/arch/arm/dts/exynos4210-origen.dts b/arch/arm/dts/exynos4210-origen.dts
index 65a5fcd..40289c8 100644
--- a/arch/arm/dts/exynos4210-origen.dts
+++ b/arch/arm/dts/exynos4210-origen.dts
@@ -25,8 +25,7 @@
};
&sdhci2 {
- samsung,bus-width = <4>;
- samsung,timing = <1 2 3>;
+ bus-width = <4>;
cd-gpios = <&gpk2 2 0>;
status = "okay";
};
diff --git a/arch/arm/dts/exynos4210-trats.dts b/arch/arm/dts/exynos4210-trats.dts
index 05989ee..88e9c0e 100644
--- a/arch/arm/dts/exynos4210-trats.dts
+++ b/arch/arm/dts/exynos4210-trats.dts
@@ -240,15 +240,13 @@
};
&sdhci0 {
- samsung,bus-width = <8>;
- samsung,timing = <1 3 3>;
+ bus-width = <8>;
pwr-gpios = <&gpk0 2 0>;
status = "okay";
};
&sdhci2 {
- samsung,bus-width = <4>;
- samsung,timing = <1 2 3>;
+ bus-width = <4>;
cd-gpios = <&gpx3 4 0>;
status = "okay";
};
diff --git a/arch/arm/dts/exynos4210-universal_c210.dts b/arch/arm/dts/exynos4210-universal_c210.dts
index 610a8ad..c87b92b 100644
--- a/arch/arm/dts/exynos4210-universal_c210.dts
+++ b/arch/arm/dts/exynos4210-universal_c210.dts
@@ -235,15 +235,13 @@
};
&sdhci0 {
- samsung,bus-width = <8>;
- samsung,timing = <1 3 3>;
+ bus-width = <8>;
pwr-gpios = <&gpk0 2 0>;
status = "okay";
};
&sdhci2 {
- samsung,bus-width = <4>;
- samsung,timing = <1 2 3>;
+ bus-width = <4>;
cd-gpios = <&gpx3 4 0>;
status = "okay";
};
diff --git a/arch/arm/dts/exynos4412-odroid.dts b/arch/arm/dts/exynos4412-odroid.dts
index ce08e8d..346e0f5 100644
--- a/arch/arm/dts/exynos4412-odroid.dts
+++ b/arch/arm/dts/exynos4412-odroid.dts
@@ -234,20 +234,19 @@
};
&sdhci2 {
- samsung,bus-width = <4>;
- samsung,timing = <1 2 3>;
+ bus-width = <4>;
cd-inverted;
cd-gpios = <&gpk2 2 0>;
status = "okay";
};
&mshc_0 {
- samsung,bus-width = <8>;
- samsung,timing = <2 1 0>;
- samsung,removable = <0>;
- fifoth_val = <0x203f0040>;
- bus_hz = <400000000>;
- div = <0x3>;
+ bus-width = <8>;
+ samsung,dw-mshc-ciu-div = <0>;
+ samsung,dw-mshc-sdr-timing = <2 1>;
+ non-removable;
+ fifo-depth = <0x80>;
+ clock-frequency = <400000000>;
index = <4>;
status = "okay";
};
diff --git a/arch/arm/dts/exynos4412-trats2.dts b/arch/arm/dts/exynos4412-trats2.dts
index c4db137..2b71d32 100644
--- a/arch/arm/dts/exynos4412-trats2.dts
+++ b/arch/arm/dts/exynos4412-trats2.dts
@@ -108,8 +108,7 @@
};
sdhci@12510000 {
- samsung,bus-width = <8>;
- samsung,timing = <1 3 3>;
+ bus-width = <8>;
pwr-gpios = <&gpk0 4 0>;
status = "disabled";
};
@@ -431,26 +430,23 @@
};
&sdhci0 {
- samsung,bus-width = <8>;
- samsung,timing = <1 3 3>;
+ bus-width = <8>;
pwr-gpios = <&gpk0 4 0>;
status = "disabled";
};
&sdhci2 {
- samsung,bus-width = <4>;
- samsung,timing = <1 2 3>;
+ bus-width = <4>;
cd-gpios = <&gpk2 2 0>;
status = "okay";
};
&mshc_0 {
- samsung,bus-width = <8>;
- samsung,timing = <2 1 0>;
- samsung,removable = <0>;
- fifoth_val = <0x203f0040>;
- bus_hz = <400000000>;
- div = <0x3>;
+ bus-width = <8>;
+ samsung,dw-mshc-ciu-div = <0>;
+ samsung,dw-mshc-sdr-timing = <2 1>;
+ non-removable;
+ clock-frequency = <400000000>;
index = <4>;
fifo-depth = <0x80>;
status = "okay";
diff --git a/arch/arm/dts/exynos5250-arndale.dts b/arch/arm/dts/exynos5250-arndale.dts
index 60309c6..4c894f1 100644
--- a/arch/arm/dts/exynos5250-arndale.dts
+++ b/arch/arm/dts/exynos5250-arndale.dts
@@ -27,8 +27,9 @@
};
mmc@12200000 {
- samsung,bus-width = <8>;
- samsung,timing = <1 3 3>;
+ bus-width = <8>;
+ samsung,dw-mshc-ciu-div = <3>;
+ samsung,dw-mshc-sdr-timing = <1 3>;
};
mmc@12210000 {
@@ -36,8 +37,9 @@
};
mmc@12220000 {
- samsung,bus-width = <4>;
- samsung,timing = <1 2 3>;
+ bus-width = <4>;
+ samsung,dw-mshc-ciu-div = <3>;
+ samsung,dw-mshc-sdr-timing = <1 2>;
};
mmc@12230000 {
diff --git a/arch/arm/dts/exynos5250-smdk5250.dts b/arch/arm/dts/exynos5250-smdk5250.dts
index afe0cca..f9f54cb 100644
--- a/arch/arm/dts/exynos5250-smdk5250.dts
+++ b/arch/arm/dts/exynos5250-smdk5250.dts
@@ -145,9 +145,10 @@
};
mmc@12200000 {
- samsung,bus-width = <8>;
- samsung,timing = <1 3 3>;
- samsung,removable = <0>;
+ bus-width = <8>;
+ samsung,dw-mshc-ciu-div = <3>;
+ samsung,dw-mshc-sdr-timing = <1 3>;
+ non-removable;
};
mmc@12210000 {
@@ -155,9 +156,9 @@
};
mmc@12220000 {
- samsung,bus-width = <4>;
- samsung,timing = <1 2 3>;
- samsung,removable = <1>;
+ bus-width = <4>;
+ samsung,dw-mshc-ciu-div = <3>;
+ samsung,dw-mshc-sdr-timing = <1 2>;
};
mmc@12230000 {
diff --git a/arch/arm/dts/exynos5250-snow.dts b/arch/arm/dts/exynos5250-snow.dts
index e41f2d3..ab7b521 100644
--- a/arch/arm/dts/exynos5250-snow.dts
+++ b/arch/arm/dts/exynos5250-snow.dts
@@ -301,9 +301,10 @@
};
mmc@12200000 {
- samsung,bus-width = <8>;
- samsung,timing = <1 3 3>;
- samsung,removable = <0>;
+ bus-width = <8>;
+ samsung,dw-mshc-ciu-div = <3>;
+ samsung,dw-mshc-sdr-timing = <1 3>;
+ non-removable;
};
mmc@12210000 {
@@ -311,9 +312,9 @@
};
mmc@12220000 {
- samsung,bus-width = <4>;
- samsung,timing = <1 2 3>;
- samsung,removable = <1>;
+ bus-width = <4>;
+ samsung,dw-mshc-ciu-div = <3>;
+ samsung,dw-mshc-sdr-timing = <1 2>;
};
mmc@12230000 {
diff --git a/arch/arm/dts/exynos5250-spring.dts b/arch/arm/dts/exynos5250-spring.dts
index 77e7a6b..9c47883 100644
--- a/arch/arm/dts/exynos5250-spring.dts
+++ b/arch/arm/dts/exynos5250-spring.dts
@@ -103,9 +103,10 @@
};
mmc@12200000 {
- samsung,bus-width = <8>;
- samsung,timing = <1 3 3>;
- samsung,removable = <0>;
+ bus-width = <8>;
+ samsung,dw-mshc-ciu-div = <3>;
+ samsung,dw-mshc-sdr-timing = <1 3>;
+ non-removable;
};
mmc@12210000 {
diff --git a/arch/arm/dts/exynos5420-smdk5420.dts b/arch/arm/dts/exynos5420-smdk5420.dts
index 7a5da67..6ba1306 100644
--- a/arch/arm/dts/exynos5420-smdk5420.dts
+++ b/arch/arm/dts/exynos5420-smdk5420.dts
@@ -106,9 +106,10 @@
};
mmc@12200000 {
- samsung,bus-width = <8>;
- samsung,timing = <1 3 3>;
- samsung,removable = <0>;
+ bus-width = <8>;
+ samsung,dw-mshc-ciu-div = <3>;
+ samsung,dw-mshc-sdr-timing = <1 3>;
+ non-removable;
samsung,pre-init;
};
@@ -117,9 +118,9 @@
};
mmc@12220000 {
- samsung,bus-width = <4>;
- samsung,timing = <1 2 3>;
- samsung,removable = <1>;
+ bus-width = <4>;
+ samsung,dw-mshc-ciu-div = <3>;
+ samsung,dw-mshc-sdr-timing = <1 2>;
};
mmc@12230000 {
diff --git a/arch/arm/dts/exynos5422-odroidxu3.dts b/arch/arm/dts/exynos5422-odroidxu3.dts
index 9d055d0..ef25cf7 100644
--- a/arch/arm/dts/exynos5422-odroidxu3.dts
+++ b/arch/arm/dts/exynos5422-odroidxu3.dts
@@ -280,11 +280,11 @@
};
mmc@12200000 {
- fifoth_val = <0x201f0020>;
+ fifo-depth = <0x40>;
};
mmc@12220000 {
- fifoth_val = <0x201f0020>;
+ fifo-depth = <0x40>;
};
emmc-reset {
diff --git a/arch/arm/dts/exynos54xx.dtsi b/arch/arm/dts/exynos54xx.dtsi
index 221da8b..5915ed6 100644
--- a/arch/arm/dts/exynos54xx.dtsi
+++ b/arch/arm/dts/exynos54xx.dtsi
@@ -119,9 +119,10 @@
};
mmc@12200000 {
- samsung,bus-width = <8>;
- samsung,timing = <1 3 3>;
- samsung,removable = <0>;
+ bus-width = <8>;
+ samsung,dw-mshc-ciu-div = <3>;
+ samsung,dw-mshc-sdr-timing = <1 3>;
+ non-removable;
samsung,pre-init;
};
@@ -130,9 +131,9 @@
};
mmc@12220000 {
- samsung,bus-width = <4>;
- samsung,timing = <1 2 3>;
- samsung,removable = <1>;
+ bus-width = <4>;
+ samsung,dw-mshc-ciu-div = <3>;
+ samsung,dw-mshc-sdr-timing = <1 2>;
};
mmc@12230000 {
diff --git a/arch/arm/dts/imx6qdl-mba6-u-boot.dtsi b/arch/arm/dts/imx6qdl-mba6-u-boot.dtsi
index 78457ef..c8c0fc1 100644
--- a/arch/arm/dts/imx6qdl-mba6-u-boot.dtsi
+++ b/arch/arm/dts/imx6qdl-mba6-u-boot.dtsi
@@ -10,6 +10,22 @@
};
};
+&aips2 {
+ bootph-all;
+};
+
+&pinctrl_uart2 {
+ bootph-all;
+};
+
+&soc {
+ bootph-all;
+};
+
+&uart2 {
+ bootph-all;
+};
+
&wdog1 {
bootph-pre-ram;
};
diff --git a/arch/arm/dts/k3-am69-r5-sk.dts b/arch/arm/dts/k3-am69-r5-sk.dts
index f177f56..4d6aab5 100644
--- a/arch/arm/dts/k3-am69-r5-sk.dts
+++ b/arch/arm/dts/k3-am69-r5-sk.dts
@@ -97,6 +97,12 @@
<0x0 0x58000000 0x0 0x8000000>;
};
+&fss {
+ /* enable ranges missing from the FSS node */
+ ranges = <0x0 0x47000000 0x0 0x47000000 0x0 0x00068400>,
+ <0x0 0x50000000 0x0 0x50000000 0x0 0x08000000>;
+};
+
&mcu_ringacc {
ti,sci = <&dm_tifs>;
};
diff --git a/arch/arm/dts/k3-j7200-r5-common-proc-board.dts b/arch/arm/dts/k3-j7200-r5-common-proc-board.dts
index fb7e2e5..94760c7 100644
--- a/arch/arm/dts/k3-j7200-r5-common-proc-board.dts
+++ b/arch/arm/dts/k3-j7200-r5-common-proc-board.dts
@@ -89,6 +89,12 @@
<0x0 0x50000000 0x0 0x8000000>;
};
+&fss {
+ /* enable ranges missing from the FSS node */
+ ranges = <0x0 0x47000000 0x0 0x47000000 0x0 0x00068400>,
+ <0x0 0x50000000 0x0 0x50000000 0x0 0x08000000>;
+};
+
&mcu_ringacc {
ti,sci = <&dm_tifs>;
};
diff --git a/arch/arm/dts/k3-j721e-r5-common-proc-board.dts b/arch/arm/dts/k3-j721e-r5-common-proc-board.dts
index c7e3443..ce55ea6 100644
--- a/arch/arm/dts/k3-j721e-r5-common-proc-board.dts
+++ b/arch/arm/dts/k3-j721e-r5-common-proc-board.dts
@@ -62,3 +62,9 @@
reg = <0x0 0x47050000 0x0 0x100>,
<0x0 0x58000000 0x0 0x8000000>;
};
+
+&fss {
+ /* enable ranges missing from the FSS node */
+ ranges = <0x0 0x47000000 0x0 0x47000000 0x0 0x00068400>,
+ <0x0 0x50000000 0x0 0x50000000 0x0 0x08000000>;
+};
diff --git a/arch/arm/dts/k3-j721e-r5-sk.dts b/arch/arm/dts/k3-j721e-r5-sk.dts
index 96a13b2..5470490 100644
--- a/arch/arm/dts/k3-j721e-r5-sk.dts
+++ b/arch/arm/dts/k3-j721e-r5-sk.dts
@@ -57,3 +57,9 @@
reg = <0x0 0x47040000 0x0 0x100>,
<0x0 0x50000000 0x0 0x8000000>;
};
+
+&fss {
+ /* enable ranges missing from the FSS node */
+ ranges = <0x0 0x47000000 0x0 0x47000000 0x0 0x00068400>,
+ <0x0 0x50000000 0x0 0x50000000 0x0 0x08000000>;
+};
diff --git a/arch/arm/dts/k3-j784s4-r5-evm.dts b/arch/arm/dts/k3-j784s4-r5-evm.dts
index bef4573..d2c7522 100644
--- a/arch/arm/dts/k3-j784s4-r5-evm.dts
+++ b/arch/arm/dts/k3-j784s4-r5-evm.dts
@@ -97,6 +97,12 @@
<0x0 0x58000000 0x0 0x8000000>;
};
+&fss {
+ /* enable ranges missing from the FSS node */
+ ranges = <0x0 0x47000000 0x0 0x47000000 0x0 0x00068400>,
+ <0x0 0x50000000 0x0 0x50000000 0x0 0x08000000>;
+};
+
&mcu_ringacc {
ti,sci = <&dm_tifs>;
};
diff --git a/arch/arm/dts/keystone-clocks.dtsi b/arch/arm/dts/keystone-clocks.dtsi
deleted file mode 100644
index 33742d8..0000000
--- a/arch/arm/dts/keystone-clocks.dtsi
+++ /dev/null
@@ -1,411 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0
-/*
- * Device Tree Source for Keystone 2 clock tree
- *
- * Copyright (C) 2013-2017 Texas Instruments Incorporated - https://www.ti.com/
- */
-
-clocks {
- #address-cells = <1>;
- #size-cells = <1>;
- ranges;
-
- mainmuxclk: mainmuxclk@2310108 {
- #clock-cells = <0>;
- compatible = "ti,keystone,pll-mux-clock";
- clocks = <&mainpllclk>, <&refclksys>;
- reg = <0x02310108 4>;
- bit-shift = <23>;
- bit-mask = <1>;
- clock-output-names = "mainmuxclk";
- };
-
- chipclk1: chipclk1 {
- #clock-cells = <0>;
- compatible = "fixed-factor-clock";
- clocks = <&mainmuxclk>;
- clock-div = <1>;
- clock-mult = <1>;
- clock-output-names = "chipclk1";
- };
-
- chipclk1rstiso: chipclk1rstiso {
- #clock-cells = <0>;
- compatible = "fixed-factor-clock";
- clocks = <&mainmuxclk>;
- clock-div = <1>;
- clock-mult = <1>;
- clock-output-names = "chipclk1rstiso";
- };
-
- gemtraceclk: gemtraceclk@2310120 {
- #clock-cells = <0>;
- compatible = "ti,keystone,pll-divider-clock";
- clocks = <&mainmuxclk>;
- reg = <0x02310120 4>;
- bit-shift = <0>;
- bit-mask = <8>;
- clock-output-names = "gemtraceclk";
- };
-
- chipstmxptclk: chipstmxptclk@2310164 {
- #clock-cells = <0>;
- compatible = "ti,keystone,pll-divider-clock";
- clocks = <&mainmuxclk>;
- reg = <0x02310164 4>;
- bit-shift = <0>;
- bit-mask = <8>;
- clock-output-names = "chipstmxptclk";
- };
-
- chipclk12: chipclk12 {
- #clock-cells = <0>;
- compatible = "fixed-factor-clock";
- clocks = <&chipclk1>;
- clock-div = <2>;
- clock-mult = <1>;
- clock-output-names = "chipclk12";
- };
-
- chipclk13: chipclk13 {
- #clock-cells = <0>;
- compatible = "fixed-factor-clock";
- clocks = <&chipclk1>;
- clock-div = <3>;
- clock-mult = <1>;
- clock-output-names = "chipclk13";
- };
-
- paclk13: paclk13 {
- #clock-cells = <0>;
- compatible = "fixed-factor-clock";
- clocks = <&papllclk>;
- clock-div = <3>;
- clock-mult = <1>;
- clock-output-names = "paclk13";
- };
-
- chipclk14: chipclk14 {
- #clock-cells = <0>;
- compatible = "fixed-factor-clock";
- clocks = <&chipclk1>;
- clock-div = <4>;
- clock-mult = <1>;
- clock-output-names = "chipclk14";
- };
-
- chipclk16: chipclk16 {
- #clock-cells = <0>;
- compatible = "fixed-factor-clock";
- clocks = <&chipclk1>;
- clock-div = <6>;
- clock-mult = <1>;
- clock-output-names = "chipclk16";
- };
-
- chipclk112: chipclk112 {
- #clock-cells = <0>;
- compatible = "fixed-factor-clock";
- clocks = <&chipclk1>;
- clock-div = <12>;
- clock-mult = <1>;
- clock-output-names = "chipclk112";
- };
-
- chipclk124: chipclk124 {
- #clock-cells = <0>;
- compatible = "fixed-factor-clock";
- clocks = <&chipclk1>;
- clock-div = <24>;
- clock-mult = <1>;
- clock-output-names = "chipclk114";
- };
-
- chipclk1rstiso13: chipclk1rstiso13 {
- #clock-cells = <0>;
- compatible = "fixed-factor-clock";
- clocks = <&chipclk1rstiso>;
- clock-div = <3>;
- clock-mult = <1>;
- clock-output-names = "chipclk1rstiso13";
- };
-
- chipclk1rstiso14: chipclk1rstiso14 {
- #clock-cells = <0>;
- compatible = "fixed-factor-clock";
- clocks = <&chipclk1rstiso>;
- clock-div = <4>;
- clock-mult = <1>;
- clock-output-names = "chipclk1rstiso14";
- };
-
- chipclk1rstiso16: chipclk1rstiso16 {
- #clock-cells = <0>;
- compatible = "fixed-factor-clock";
- clocks = <&chipclk1rstiso>;
- clock-div = <6>;
- clock-mult = <1>;
- clock-output-names = "chipclk1rstiso16";
- };
-
- chipclk1rstiso112: chipclk1rstiso112 {
- #clock-cells = <0>;
- compatible = "fixed-factor-clock";
- clocks = <&chipclk1rstiso>;
- clock-div = <12>;
- clock-mult = <1>;
- clock-output-names = "chipclk1rstiso112";
- };
-
- clkmodrst0: clkmodrst0@2350000 {
- #clock-cells = <0>;
- compatible = "ti,keystone,psc-clock";
- clocks = <&chipclk16>;
- clock-output-names = "modrst0";
- reg = <0x02350000 0xb00>, <0x02350000 0x400>;
- reg-names = "control", "domain";
- domain-id = <0>;
- };
-
-
- clkusb: clkusb@2350008 {
- #clock-cells = <0>;
- compatible = "ti,keystone,psc-clock";
- clocks = <&chipclk16>;
- clock-output-names = "usb";
- reg = <0x02350008 0xb00>, <0x02350000 0x400>;
- reg-names = "control", "domain";
- domain-id = <0>;
- };
-
- clkaemifspi: clkaemifspi@235000c {
- #clock-cells = <0>;
- compatible = "ti,keystone,psc-clock";
- clocks = <&chipclk16>;
- clock-output-names = "aemif-spi";
- reg = <0x0235000c 0xb00>, <0x02350000 0x400>;
- reg-names = "control", "domain";
- domain-id = <0>;
- };
-
-
- clkdebugsstrc: clkdebugsstrc@2350014 {
- #clock-cells = <0>;
- compatible = "ti,keystone,psc-clock";
- clocks = <&chipclk13>;
- clock-output-names = "debugss-trc";
- reg = <0x02350014 0xb00>, <0x02350000 0x400>;
- reg-names = "control", "domain";
- domain-id = <1>;
- };
-
- clktetbtrc: clktetbtrc@2350018 {
- #clock-cells = <0>;
- compatible = "ti,keystone,psc-clock";
- clocks = <&chipclk13>;
- clock-output-names = "tetb-trc";
- reg = <0x02350018 0xb00>, <0x02350004 0x400>;
- reg-names = "control", "domain";
- domain-id = <1>;
- };
-
- clkpa: clkpa@235001c {
- #clock-cells = <0>;
- compatible = "ti,keystone,psc-clock";
- clocks = <&paclk13>;
- clock-output-names = "pa";
- reg = <0x0235001c 0xb00>, <0x02350008 0x400>;
- reg-names = "control", "domain";
- domain-id = <2>;
- };
-
- clkcpgmac: clkcpgmac@2350020 {
- #clock-cells = <0>;
- compatible = "ti,keystone,psc-clock";
- clocks = <&clkpa>;
- clock-output-names = "cpgmac";
- reg = <0x02350020 0xb00>, <0x02350008 0x400>;
- reg-names = "control", "domain";
- domain-id = <2>;
- };
-
- clksa: clksa@2350024 {
- #clock-cells = <0>;
- compatible = "ti,keystone,psc-clock";
- clocks = <&clkpa>;
- clock-output-names = "sa";
- reg = <0x02350024 0xb00>, <0x02350008 0x400>;
- reg-names = "control", "domain";
- domain-id = <2>;
- };
-
- clkpcie: clkpcie@2350028 {
- #clock-cells = <0>;
- compatible = "ti,keystone,psc-clock";
- clocks = <&chipclk12>;
- clock-output-names = "pcie";
- reg = <0x02350028 0xb00>, <0x0235000c 0x400>;
- reg-names = "control", "domain";
- domain-id = <3>;
- };
-
- clksr: clksr@2350034 {
- #clock-cells = <0>;
- compatible = "ti,keystone,psc-clock";
- clocks = <&chipclk1rstiso112>;
- clock-output-names = "sr";
- reg = <0x02350034 0xb00>, <0x02350018 0x400>;
- reg-names = "control", "domain";
- domain-id = <6>;
- };
-
- clkgem0: clkgem0@235003c {
- #clock-cells = <0>;
- compatible = "ti,keystone,psc-clock";
- clocks = <&chipclk1>;
- clock-output-names = "gem0";
- reg = <0x0235003c 0xb00>, <0x02350020 0x400>;
- reg-names = "control", "domain";
- domain-id = <8>;
- };
-
- clkddr30: clkddr30@235005c {
- #clock-cells = <0>;
- compatible = "ti,keystone,psc-clock";
- clocks = <&chipclk12>;
- clock-output-names = "ddr3-0";
- reg = <0x0235005c 0xb00>, <0x02350040 0x400>;
- reg-names = "control", "domain";
- domain-id = <16>;
- };
-
- clkwdtimer0: clkwdtimer0@2350000 {
- #clock-cells = <0>;
- compatible = "ti,keystone,psc-clock";
- clocks = <&clkmodrst0>;
- clock-output-names = "timer0";
- reg = <0x02350000 0xb00>, <0x02350000 0x400>;
- reg-names = "control", "domain";
- domain-id = <0>;
- };
-
- clkwdtimer1: clkwdtimer1@2350000 {
- #clock-cells = <0>;
- compatible = "ti,keystone,psc-clock";
- clocks = <&clkmodrst0>;
- clock-output-names = "timer1";
- reg = <0x02350000 0xb00>, <0x02350000 0x400>;
- reg-names = "control", "domain";
- domain-id = <0>;
- };
-
- clkwdtimer2: clkwdtimer2@2350000 {
- #clock-cells = <0>;
- compatible = "ti,keystone,psc-clock";
- clocks = <&clkmodrst0>;
- clock-output-names = "timer2";
- reg = <0x02350000 0xb00>, <0x02350000 0x400>;
- reg-names = "control", "domain";
- domain-id = <0>;
- };
-
- clkwdtimer3: clkwdtimer3@2350000 {
- #clock-cells = <0>;
- compatible = "ti,keystone,psc-clock";
- clocks = <&clkmodrst0>;
- clock-output-names = "timer3";
- reg = <0x02350000 0xb00>, <0x02350000 0x400>;
- reg-names = "control", "domain";
- domain-id = <0>;
- };
-
- clktimer15: clktimer15@2350000 {
- #clock-cells = <0>;
- compatible = "ti,keystone,psc-clock";
- clocks = <&clkmodrst0>;
- clock-output-names = "timer15";
- reg = <0x02350000 0xb00>, <0x02350000 0x400>;
- reg-names = "control", "domain";
- domain-id = <0>;
- };
-
- clkuart0: clkuart0@2350000 {
- #clock-cells = <0>;
- compatible = "ti,keystone,psc-clock";
- clocks = <&clkmodrst0>;
- clock-output-names = "uart0";
- reg = <0x02350000 0xb00>, <0x02350000 0x400>;
- reg-names = "control", "domain";
- domain-id = <0>;
- };
-
- clkuart1: clkuart1@2350000 {
- #clock-cells = <0>;
- compatible = "ti,keystone,psc-clock";
- clocks = <&clkmodrst0>;
- clock-output-names = "uart1";
- reg = <0x02350000 0xb00>, <0x02350000 0x400>;
- reg-names = "control", "domain";
- domain-id = <0>;
- };
-
- clkaemif: clkaemif@2350000 {
- #clock-cells = <0>;
- compatible = "ti,keystone,psc-clock";
- clocks = <&clkaemifspi>;
- clock-output-names = "aemif";
- reg = <0x02350000 0xb00>, <0x02350000 0x400>;
- reg-names = "control", "domain";
- domain-id = <0>;
- };
-
- clkusim: clkusim@2350000 {
- #clock-cells = <0>;
- compatible = "ti,keystone,psc-clock";
- clocks = <&clkmodrst0>;
- clock-output-names = "usim";
- reg = <0x02350000 0xb00>, <0x02350000 0x400>;
- reg-names = "control", "domain";
- domain-id = <0>;
- };
-
- clki2c: clki2c@2350000 {
- #clock-cells = <0>;
- compatible = "ti,keystone,psc-clock";
- clocks = <&clkmodrst0>;
- clock-output-names = "i2c";
- reg = <0x02350000 0xb00>, <0x02350000 0x400>;
- reg-names = "control", "domain";
- domain-id = <0>;
- };
-
- clkspi: clkspi@2350000 {
- #clock-cells = <0>;
- compatible = "ti,keystone,psc-clock";
- clocks = <&clkaemifspi>;
- clock-output-names = "spi";
- reg = <0x02350000 0xb00>, <0x02350000 0x400>;
- reg-names = "control", "domain";
- domain-id = <0>;
- };
-
- clkgpio: clkgpio@2350000 {
- #clock-cells = <0>;
- compatible = "ti,keystone,psc-clock";
- clocks = <&clkmodrst0>;
- clock-output-names = "gpio";
- reg = <0x02350000 0xb00>, <0x02350000 0x400>;
- reg-names = "control", "domain";
- domain-id = <0>;
- };
-
- clkkeymgr: clkkeymgr@2350000 {
- #clock-cells = <0>;
- compatible = "ti,keystone,psc-clock";
- clocks = <&clkmodrst0>;
- clock-output-names = "keymgr";
- reg = <0x02350000 0xb00>, <0x02350000 0x400>;
- reg-names = "control", "domain";
- domain-id = <0>;
- };
-};
diff --git a/arch/arm/dts/keystone-k2e-clocks.dtsi b/arch/arm/dts/keystone-k2e-clocks.dtsi
deleted file mode 100644
index 46f8ab3..0000000
--- a/arch/arm/dts/keystone-k2e-clocks.dtsi
+++ /dev/null
@@ -1,74 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0
-/*
- * Keystone 2 Edison SoC specific device tree
- *
- * Copyright (C) 2014-2017 Texas Instruments Incorporated - https://www.ti.com/
- */
-
-clocks {
- mainpllclk: mainpllclk@2310110 {
- #clock-cells = <0>;
- compatible = "ti,keystone,main-pll-clock";
- clocks = <&refclksys>;
- reg = <0x02620350 4>, <0x02310110 4>, <0x02310108 4>;
- reg-names = "control", "multiplier", "post-divider";
- };
-
- papllclk: papllclk@2620358 {
- #clock-cells = <0>;
- compatible = "ti,keystone,pll-clock";
- clocks = <&refclkpass>;
- clock-output-names = "papllclk";
- reg = <0x02620358 4>;
- reg-names = "control";
- };
-
- ddr3apllclk: ddr3apllclk@2620360 {
- #clock-cells = <0>;
- compatible = "ti,keystone,pll-clock";
- clocks = <&refclkddr3a>;
- clock-output-names = "ddr-3a-pll-clk";
- reg = <0x02620360 4>;
- reg-names = "control";
- };
-
- clkusb1: clkusb1@2350004 {
- #clock-cells = <0>;
- compatible = "ti,keystone,psc-clock";
- clocks = <&chipclk16>;
- clock-output-names = "usb1";
- reg = <0x02350004 0xb00>, <0x02350000 0x400>;
- reg-names = "control", "domain";
- domain-id = <0>;
- };
-
- clkhyperlink0: clkhyperlink0@2350030 {
- #clock-cells = <0>;
- compatible = "ti,keystone,psc-clock";
- clocks = <&chipclk12>;
- clock-output-names = "hyperlink-0";
- reg = <0x02350030 0xb00>, <0x02350014 0x400>;
- reg-names = "control", "domain";
- domain-id = <5>;
- };
-
- clkpcie1: clkpcie1@235006c {
- #clock-cells = <0>;
- compatible = "ti,keystone,psc-clock";
- clocks = <&chipclk12>;
- clock-output-names = "pcie1";
- reg = <0x0235006c 0xb00>, <0x02350048 0x400>;
- reg-names = "control", "domain";
- domain-id = <18>;
- };
-
- clkxge: clkxge@23500c8 {
- #clock-cells = <0>;
- compatible = "ti,keystone,psc-clock";
- clocks = <&chipclk13>;
- clock-output-names = "xge";
- reg = <0x023500c8 0xb00>, <0x02350074 0x400>;
- reg-names = "control", "domain";
- domain-id = <29>;
- };
-};
diff --git a/arch/arm/dts/keystone-k2e-evm-u-boot.dtsi b/arch/arm/dts/keystone-k2e-evm-u-boot.dtsi
index 953c750..e77c53d 100644
--- a/arch/arm/dts/keystone-k2e-evm-u-boot.dtsi
+++ b/arch/arm/dts/keystone-k2e-evm-u-boot.dtsi
@@ -4,15 +4,23 @@
*/
/{
- soc {
- bootph-all;
- };
aliases {
usb0 = &usb;
usb1 = &usb1;
+ i2c0 = &i2c0;
+ i2c1 = &i2c1;
+ i2c2 = &i2c2;
+ };
+
+ chosen {
+ stdout-path = &uart0;
};
};
+&soc0 {
+ bootph-all;
+};
+
&i2c1 {
bootph-all;
};
diff --git a/arch/arm/dts/keystone-k2e-evm.dts b/arch/arm/dts/keystone-k2e-evm.dts
deleted file mode 100644
index bf88444..0000000
--- a/arch/arm/dts/keystone-k2e-evm.dts
+++ /dev/null
@@ -1,152 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0
-/*
- * Keystone 2 Edison EVM device tree
- *
- * Copyright (C) 2013-2017 Texas Instruments Incorporated - https://www.ti.com/
- */
-/dts-v1/;
-
-#include "keystone.dtsi"
-#include "keystone-k2e.dtsi"
-
-/ {
- compatible = "ti,k2e-evm", "ti,k2e", "ti,keystone";
- model = "Texas Instruments Keystone 2 Edison EVM";
-
- soc {
-
- clocks {
- refclksys: refclksys {
- #clock-cells = <0>;
- compatible = "fixed-clock";
- clock-frequency = <100000000>;
- clock-output-names = "refclk-sys";
- };
-
- refclkpass: refclkpass {
- #clock-cells = <0>;
- compatible = "fixed-clock";
- clock-frequency = <100000000>;
- clock-output-names = "refclk-pass";
- };
-
- refclkddr3a: refclkddr3a {
- #clock-cells = <0>;
- compatible = "fixed-clock";
- clock-frequency = <100000000>;
- clock-output-names = "refclk-ddr3a";
- };
- };
- };
-};
-
-&usb_phy {
- status = "okay";
-};
-
-&usb {
- status = "okay";
-};
-
-&usb1_phy {
- status = "okay";
-};
-
-&usb1 {
- status = "okay";
-};
-
-&i2c0 {
- dtt@50 {
- compatible = "at,24c1024";
- reg = <0x50>;
- };
-};
-
-&aemif {
- cs0 {
- #address-cells = <2>;
- #size-cells = <1>;
- clock-ranges;
- ranges;
-
- ti,cs-chipselect = <0>;
- /* all timings in nanoseconds */
- ti,cs-min-turnaround-ns = <12>;
- ti,cs-read-hold-ns = <6>;
- ti,cs-read-strobe-ns = <23>;
- ti,cs-read-setup-ns = <9>;
- ti,cs-write-hold-ns = <8>;
- ti,cs-write-strobe-ns = <23>;
- ti,cs-write-setup-ns = <8>;
-
- nand@0,0 {
- compatible = "ti,keystone-nand","ti,davinci-nand";
- #address-cells = <1>;
- #size-cells = <1>;
- reg = <0 0 0x4000000
- 1 0 0x0000100>;
-
- ti,davinci-chipselect = <0>;
- ti,davinci-mask-ale = <0x2000>;
- ti,davinci-mask-cle = <0x4000>;
- ti,davinci-mask-chipsel = <0>;
- nand-ecc-mode = "hw";
- ti,davinci-ecc-bits = <4>;
- nand-on-flash-bbt;
-
- partition@0 {
- label = "u-boot";
- reg = <0x0 0x100000>;
- read-only;
- };
-
- partition@100000 {
- label = "params";
- reg = <0x100000 0x80000>;
- read-only;
- };
-
- partition@180000 {
- label = "ubifs";
- reg = <0x180000 0x1FE80000>;
- };
- };
- };
-};
-
-&spi0 {
- status = "okay";
- nor_flash: flash@0 {
- #address-cells = <1>;
- #size-cells = <1>;
- compatible = "Micron,n25q128a11", "jedec,spi-nor";
- spi-max-frequency = <54000000>;
- m25p,fast-read;
- reg = <0>;
-
- partition@0 {
- label = "u-boot-spl";
- reg = <0x0 0x80000>;
- read-only;
- };
-
- partition@1 {
- label = "misc";
- reg = <0x80000 0xf80000>;
- };
- };
-};
-
-&mdio {
- status = "okay";
- ethphy0: ethernet-phy@0 {
- compatible = "marvell,88E1514", "marvell,88E1510", "ethernet-phy-ieee802.3-c22";
- reg = <0>;
- };
-
- ethphy1: ethernet-phy@1 {
- compatible = "marvell,88E1514", "marvell,88E1510", "ethernet-phy-ieee802.3-c22";
- reg = <1>;
- };
-};
diff --git a/arch/arm/dts/keystone-k2e-netcp.dtsi b/arch/arm/dts/keystone-k2e-netcp.dtsi
deleted file mode 100644
index dd61503..0000000
--- a/arch/arm/dts/keystone-k2e-netcp.dtsi
+++ /dev/null
@@ -1,203 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0
-/*
- * Device Tree Source for Keystone 2 Edison Netcp driver
- *
- * Copyright (C) 2015-2017 Texas Instruments Incorporated - https://www.ti.com/
- */
-
-qmss: qmss@2a40000 {
- compatible = "ti,keystone-navigator-qmss";
- dma-coherent;
- #address-cells = <1>;
- #size-cells = <1>;
- clocks = <&chipclk13>;
- ranges;
- queue-range = <0 0x2000>;
- linkram0 = <0x100000 0x4000>;
- linkram1 = <0 0x10000>;
-
- qmgrs {
- #address-cells = <1>;
- #size-cells = <1>;
- ranges;
- qmgr0 {
- managed-queues = <0 0x2000>;
- reg = <0x2a40000 0x20000>,
- <0x2a06000 0x400>,
- <0x2a02000 0x1000>,
- <0x2a03000 0x1000>,
- <0x23a80000 0x20000>,
- <0x2a80000 0x20000>;
- reg-names = "peek", "status", "config",
- "region", "push", "pop";
- };
- };
- queue-pools {
- qpend {
- qpend-0 {
- qrange = <658 8>;
- interrupts =<0 40 0xf04 0 41 0xf04 0 42 0xf04
- 0 43 0xf04 0 44 0xf04 0 45 0xf04
- 0 46 0xf04 0 47 0xf04>;
- };
- qpend-1 {
- qrange = <528 16>;
- interrupts = <0 48 0xf04 0 49 0xf04 0 50 0xf04
- 0 51 0xf04 0 52 0xf04 0 53 0xf04
- 0 54 0xf04 0 55 0xf04 0 56 0xf04
- 0 57 0xf04 0 58 0xf04 0 59 0xf04
- 0 60 0xf04 0 61 0xf04 0 62 0xf04
- 0 63 0xf04>;
- qalloc-by-id;
- };
- qpend-2 {
- qrange = <544 16>;
- interrupts = <0 64 0xf04 0 65 0xf04 0 66 0xf04
- 0 59 0xf04 0 68 0xf04 0 69 0xf04
- 0 70 0xf04 0 71 0xf04 0 72 0xf04
- 0 73 0xf04 0 74 0xf04 0 75 0xf04
- 0 76 0xf04 0 77 0xf04 0 78 0xf04
- 0 79 0xf04>;
- };
- };
- general-purpose {
- gp-0 {
- qrange = <4000 64>;
- };
- netcp-tx {
- qrange = <896 128>;
- qalloc-by-id;
- };
- };
- };
- descriptor-regions {
- #address-cells = <1>;
- #size-cells = <1>;
- ranges;
- region-12 {
- id = <12>;
- region-spec = <8192 128>; /* num_desc desc_size */
- link-index = <0x4000>;
- };
- };
-}; /* qmss */
-
-knav_dmas: knav_dmas@0 {
- compatible = "ti,keystone-navigator-dma";
- clocks = <&papllclk>;
- #address-cells = <1>;
- #size-cells = <1>;
- ranges;
- ti,navigator-cloud-address = <0x23a80000 0x23a90000
- 0x23a80000 0x23a90000>;
-
- dma_gbe: dma_gbe@0 {
- reg = <0x24186000 0x100>,
- <0x24187000 0x2a0>,
- <0x24188000 0xb60>,
- <0x24186100 0x80>,
- <0x24189000 0x1000>;
- reg-names = "global", "txchan", "rxchan",
- "txsched", "rxflow";
- };
-};
-
-netcp: netcp@24000000 {
- reg = <0x2620110 0x8>;
- reg-names = "efuse";
- compatible = "ti,netcp-1.0";
- #address-cells = <1>;
- #size-cells = <1>;
-
- /* NetCP address range */
- ranges = <0 0x24000000 0x1000000>;
-
- clocks = <&papllclk>, <&clkcpgmac>, <&chipclk12>;
- dma-coherent;
-
- ti,navigator-dmas = <&dma_gbe 0>,
- <&dma_gbe 8>,
- <&dma_gbe 0>;
- ti,navigator-dma-names = "netrx0", "netrx1", "nettx";
-
- netcp-devices {
- #address-cells = <1>;
- #size-cells = <1>;
- ranges;
- gbe@200000 { /* ETHSS */
- label = "netcp-gbe";
- compatible = "ti,netcp-gbe-9";
- reg = <0x200000 0x900>, <0x220000 0x20000>;
- /* enable-ale; */
- tx-queue = <896>;
- tx-channel = "nettx";
-
- interfaces {
- gbe0: interface-0 {
- slave-port = <0>;
- link-interface = <1>;
- phy-handle = <ðphy0>;
- };
- gbe1: interface-1 {
- slave-port = <1>;
- link-interface = <1>;
- phy-handle = <ðphy1>;
- };
- };
-
- secondary-slave-ports {
- port-2 {
- slave-port = <2>;
- link-interface = <2>;
- };
- port-3 {
- slave-port = <3>;
- link-interface = <2>;
- };
- port-4 {
- slave-port = <4>;
- link-interface = <2>;
- };
- port-5 {
- slave-port = <5>;
- link-interface = <2>;
- };
- port-6 {
- slave-port = <6>;
- link-interface = <2>;
- };
- port-7 {
- slave-port = <7>;
- link-interface = <2>;
- };
- };
- };
- };
-
- netcp-interfaces {
- interface-0 {
- rx-channel = "netrx0";
- rx-pool = <1024 12>;
- tx-pool = <1024 12>;
- rx-queue-depth = <128 128 0 0>;
- rx-buffer-size = <1518 4096 0 0>;
- rx-queue = <528>;
- tx-completion-queue = <530>;
- efuse-mac = <1>;
- netcp-gbe = <&gbe0>;
-
- };
- interface-1 {
- rx-channel = "netrx1";
- rx-pool = <1024 12>;
- tx-pool = <1024 12>;
- rx-queue-depth = <128 128 0 0>;
- rx-buffer-size = <1518 4096 0 0>;
- rx-queue = <529>;
- tx-completion-queue = <531>;
- efuse-mac = <0>;
- local-mac-address = [02 18 31 7e 3e 00];
- netcp-gbe = <&gbe1>;
- };
- };
-};
diff --git a/arch/arm/dts/keystone-k2e.dtsi b/arch/arm/dts/keystone-k2e.dtsi
deleted file mode 100644
index 449cddc..0000000
--- a/arch/arm/dts/keystone-k2e.dtsi
+++ /dev/null
@@ -1,144 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0
-/*
- * Keystone 2 Edison soc device tree
- *
- * Copyright (C) 2013-2017 Texas Instruments Incorporated - https://www.ti.com/
- */
-
-/ {
- cpus {
- #address-cells = <1>;
- #size-cells = <0>;
-
- interrupt-parent = <&gic>;
-
- cpu@0 {
- compatible = "arm,cortex-a15";
- device_type = "cpu";
- reg = <0>;
- };
-
- cpu@1 {
- compatible = "arm,cortex-a15";
- device_type = "cpu";
- reg = <1>;
- };
-
- cpu@2 {
- compatible = "arm,cortex-a15";
- device_type = "cpu";
- reg = <2>;
- };
-
- cpu@3 {
- compatible = "arm,cortex-a15";
- device_type = "cpu";
- reg = <3>;
- };
- };
-
- soc {
- /include/ "keystone-k2e-clocks.dtsi"
-
- usb: usb@2680000 {
- interrupts = <GIC_SPI 152 IRQ_TYPE_EDGE_RISING>;
- usb@2690000 {
- interrupts = <GIC_SPI 152 IRQ_TYPE_EDGE_RISING>;
- };
- };
-
- usb1_phy: usb_phy@2620750 {
- compatible = "ti,keystone-usbphy";
- #address-cells = <1>;
- #size-cells = <1>;
- reg = <0x2620750 24>;
- status = "disabled";
- };
-
- usb1: usb@25000000 {
- compatible = "ti,keystone-dwc3";
- #address-cells = <1>;
- #size-cells = <1>;
- reg = <0x25000000 0x10000>;
- clocks = <&clkusb1>;
- clock-names = "usb";
- interrupts = <GIC_SPI 414 IRQ_TYPE_EDGE_RISING>;
- ranges;
- dma-coherent;
- dma-ranges;
- status = "disabled";
-
- usb@25010000 {
- compatible = "synopsys,dwc3";
- reg = <0x25010000 0x70000>;
- interrupts = <GIC_SPI 414 IRQ_TYPE_EDGE_RISING>;
- usb-phy = <&usb1_phy>, <&usb1_phy>;
- };
- };
-
- dspgpio0: keystone_dsp_gpio@02620240 {
- compatible = "ti,keystone-dsp-gpio";
- gpio-controller;
- #gpio-cells = <2>;
- gpio,syscon-dev = <&devctrl 0x240>;
- };
-
- pcie1: pcie@21020000 {
- compatible = "ti,keystone-pcie","snps,dw-pcie";
- clocks = <&clkpcie1>;
- clock-names = "pcie";
- #address-cells = <3>;
- #size-cells = <2>;
- reg = <0x21021000 0x2000>, <0x21020000 0x1000>, <0x02620128 4>;
- ranges = <0x81000000 0 0 0x23260000 0x4000 0x4000
- 0x82000000 0 0x60000000 0x60000000 0 0x10000000>;
-
- status = "disabled";
- device_type = "pci";
- num-lanes = <2>;
-
- #interrupt-cells = <1>;
- interrupt-map-mask = <0 0 0 7>;
- interrupt-map = <0 0 0 1 &pcie_intc1 0>, /* INT A */
- <0 0 0 2 &pcie_intc1 1>, /* INT B */
- <0 0 0 3 &pcie_intc1 2>, /* INT C */
- <0 0 0 4 &pcie_intc1 3>; /* INT D */
-
- pcie_msi_intc1: msi-interrupt-controller {
- interrupt-controller;
- #interrupt-cells = <1>;
- interrupt-parent = <&gic>;
- interrupts = <GIC_SPI 377 IRQ_TYPE_EDGE_RISING>,
- <GIC_SPI 378 IRQ_TYPE_EDGE_RISING>,
- <GIC_SPI 379 IRQ_TYPE_EDGE_RISING>,
- <GIC_SPI 380 IRQ_TYPE_EDGE_RISING>,
- <GIC_SPI 381 IRQ_TYPE_EDGE_RISING>,
- <GIC_SPI 382 IRQ_TYPE_EDGE_RISING>,
- <GIC_SPI 383 IRQ_TYPE_EDGE_RISING>,
- <GIC_SPI 384 IRQ_TYPE_EDGE_RISING>;
- };
-
- pcie_intc1: legacy-interrupt-controller {
- interrupt-controller;
- #interrupt-cells = <1>;
- interrupt-parent = <&gic>;
- interrupts = <GIC_SPI 373 IRQ_TYPE_EDGE_RISING>,
- <GIC_SPI 374 IRQ_TYPE_EDGE_RISING>,
- <GIC_SPI 375 IRQ_TYPE_EDGE_RISING>,
- <GIC_SPI 376 IRQ_TYPE_EDGE_RISING>;
- };
- };
-
- mdio: mdio@24200f00 {
- compatible = "ti,keystone_mdio", "ti,davinci_mdio";
- #address-cells = <1>;
- #size-cells = <0>;
- reg = <0x24200f00 0x100>;
- status = "disabled";
- clocks = <&clkcpgmac>;
- clock-names = "fck";
- bus_freq = <2500000>;
- };
- /include/ "keystone-k2e-netcp.dtsi"
- };
-};
diff --git a/arch/arm/dts/keystone-k2g-evm-u-boot.dtsi b/arch/arm/dts/keystone-k2g-evm-u-boot.dtsi
index 72b67b2..19c78c9 100644
--- a/arch/arm/dts/keystone-k2g-evm-u-boot.dtsi
+++ b/arch/arm/dts/keystone-k2g-evm-u-boot.dtsi
@@ -4,20 +4,34 @@
*/
/{
- soc {
- bootph-all;
- };
aliases {
usb0 = &usb0;
usb1 = &usb1;
};
+
+ chosen {
+ stdout-path = &uart0;
+ };
+};
+
+&soc0 {
+ bootph-all;
+
+ pmmc@2900000 {
+ bootph-all;
+ compatible = "ti,power-processor";
+ reg = <0x02900000 0x40000>;
+ ti,lpsc_module = <1>;
+ };
};
&i2c0 {
+ status = "okay";
bootph-all;
};
&i2c1 {
+ status = "okay";
bootph-all;
};
diff --git a/arch/arm/dts/keystone-k2g-evm.dts b/arch/arm/dts/keystone-k2g-evm.dts
deleted file mode 100644
index 491fdc4..0000000
--- a/arch/arm/dts/keystone-k2g-evm.dts
+++ /dev/null
@@ -1,148 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0
-/*
- * Device Tree Source for K2G EVM
- *
- * Copyright (C) 2016-2017 Texas Instruments Incorporated - https://www.ti.com/
- */
-/dts-v1/;
-
-#include "keystone-k2g.dtsi"
-
-/ {
- compatible = "ti,k2g-evm","ti,keystone";
- model = "Texas Instruments K2G General Purpose EVM";
-
- chosen {
- stdout-path = &uart0;
- };
-
- memory@80000000 {
- device_type = "memory";
- reg = <0x80000000 0x80000000>;
- };
-};
-
-&mdio {
- status = "okay";
- ethphy0: ethernet-phy@0 {
- reg = <0>;
- };
-};
-
-&keystone_usb0 {
- status = "okay";
-};
-
-&usb0_phy {
- status = "okay";
-};
-
-&usb0 {
- dr_mode = "host";
- status = "okay";
-};
-
-&keystone_usb1 {
- status = "okay";
-};
-
-&usb1_phy {
- status = "okay";
-};
-
-&usb1 {
- dr_mode = "peripheral";
- status = "okay";
-};
-
-&gbe0 {
- phy-handle = <ðphy0>;
-};
-
-&netcp {
- status = "okay";
-};
-
-&spi1 {
- status = "okay";
-
- spi_nor: flash@0 {
- #address-cells = <1>;
- #size-cells = <1>;
- compatible = "jedec,spi-nor";
- spi-max-frequency = <50000000>;
- m25p,fast-read;
- reg = <0>;
-
- partition@0 {
- label = "u-boot-spl";
- reg = <0x0 0x80000>;
- read-only;
- };
-
- partition@1 {
- label = "misc";
- reg = <0x80000 0xf80000>;
- };
- };
-};
-
-&qspi {
- status = "okay";
-
- flash0: flash@0 {
- compatible = "s25fl512s", "jedec,spi-nor";
- reg = <0>;
- spi-tx-bus-width = <1>;
- spi-rx-bus-width = <4>;
- spi-max-frequency = <96000000>;
- #address-cells = <1>;
- #size-cells = <1>;
- cdns,tshsl-ns = <392>;
- cdns,tsd2d-ns = <392>;
- cdns,tchsh-ns = <100>;
- cdns,tslch-ns = <100>;
- block-size = <18>;
-
- partition@0 {
- label = "QSPI.u-boot-spl-os";
- reg = <0x00000000 0x00100000>;
- };
- partition@1 {
- label = "QSPI.u-boot-env";
- reg = <0x00100000 0x00040000>;
- };
- partition@2 {
- label = "QSPI.skern";
- reg = <0x00140000 0x0040000>;
- };
- partition@3 {
- label = "QSPI.pmmc-firmware";
- reg = <0x00180000 0x0040000>;
- };
- partition@4 {
- label = "QSPI.kernel";
- reg = <0x001C0000 0x0800000>;
- };
- partition@5 {
- label = "QSPI.file-system";
- reg = <0x009C0000 0x3640000>;
- };
- };
-};
-
-&mmc0 {
- status = "okay";
-};
-
-&mmc1 {
- status = "okay";
-};
-
-&i2c0 {
- status = "okay";
-};
-
-&i2c1 {
- status = "okay";
-};
diff --git a/arch/arm/dts/keystone-k2g-generic-u-boot.dtsi b/arch/arm/dts/keystone-k2g-generic-u-boot.dtsi
deleted file mode 100644
index 3634ed7..0000000
--- a/arch/arm/dts/keystone-k2g-generic-u-boot.dtsi
+++ /dev/null
@@ -1,18 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * Copyright (C) 2017 Texas Instruments Incorporated - https://www.ti.com/
- */
-
-/{
- soc {
- bootph-all;
- };
-};
-
-&i2c0 {
- bootph-all;
-};
-
-&i2c1 {
- bootph-all;
-};
diff --git a/arch/arm/dts/keystone-k2g-generic.dts b/arch/arm/dts/keystone-k2g-generic.dts
deleted file mode 100644
index dc6c31a..0000000
--- a/arch/arm/dts/keystone-k2g-generic.dts
+++ /dev/null
@@ -1,27 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * Device Tree Source for Generic 66AK2G0X EVM
- *
- * Copyright (C) 2017 Texas Instruments Incorporated - https://www.ti.com/
- */
-
-/dts-v1/;
-
-#include "keystone-k2g.dtsi"
-
-/ {
- compatible = "ti,k2g-generic", "ti,k2g", "ti,keystone";
- model = "Texas Instruments 66AK2G02 Generic";
-
- chosen {
- stdout-path = &uart0;
- };
-};
-
-&i2c0 {
- status = "okay";
-};
-
-&i2c1 {
- status = "okay";
-};
diff --git a/arch/arm/dts/keystone-k2g-ice-u-boot.dtsi b/arch/arm/dts/keystone-k2g-ice-u-boot.dtsi
index 3634ed7..1527446 100644
--- a/arch/arm/dts/keystone-k2g-ice-u-boot.dtsi
+++ b/arch/arm/dts/keystone-k2g-ice-u-boot.dtsi
@@ -4,15 +4,28 @@
*/
/{
- soc {
+ chosen {
+ stdout-path = &uart0;
+ };
+};
+
+&soc0 {
+ bootph-all;
+
+ pmmc@2900000 {
bootph-all;
+ compatible = "ti,power-processor";
+ reg = <0x02900000 0x40000>;
+ ti,lpsc_module = <1>;
};
};
&i2c0 {
+ status = "okay";
bootph-all;
};
&i2c1 {
+ status = "okay";
bootph-all;
};
diff --git a/arch/arm/dts/keystone-k2g-ice.dts b/arch/arm/dts/keystone-k2g-ice.dts
deleted file mode 100644
index b898ae6..0000000
--- a/arch/arm/dts/keystone-k2g-ice.dts
+++ /dev/null
@@ -1,118 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0
-/*
- * Device Tree Source for K2G Industrial Communication Engine EVM
- *
- * Copyright (C) 2017 Texas Instruments Incorporated - https://www.ti.com/
- */
-/dts-v1/;
-
-#include "keystone-k2g.dtsi"
-#include <dt-bindings/net/ti-dp83867.h>
-
-/ {
- compatible = "ti,k2g-ice", "ti,k2g", "ti,keystone";
- model = "Texas Instruments K2G Industrial Communication EVM";
-
- chosen {
- stdout-path = &uart0;
- };
-
- memory@80000000 {
- device_type = "memory";
- reg = <0x80000000 0x20000000>;
- };
-};
-
-&mmc1 {
- status = "okay";
-};
-
-&i2c0 {
- status = "okay";
-};
-
-&i2c1 {
- status = "okay";
-};
-
-&qspi {
- status = "okay";
-
- flash0: flash@0 {
- compatible = "s25fl256s1", "jedec,spi-nor";
- reg = <0>;
- spi-tx-bus-width = <1>;
- spi-rx-bus-width = <4>;
- spi-max-frequency = <96000000>;
- #address-cells = <1>;
- #size-cells = <1>;
- cdns,read-delay = <5>;
- cdns,tshsl-ns = <500>;
- cdns,tsd2d-ns = <500>;
- cdns,tchsh-ns = <119>;
- cdns,tslch-ns = <119>;
-
- partition@0 {
- label = "QSPI.u-boot";
- reg = <0x00000000 0x00100000>;
- };
- partition@1 {
- label = "QSPI.u-boot-env";
- reg = <0x00100000 0x00040000>;
- };
- partition@2 {
- label = "QSPI.skern";
- reg = <0x00140000 0x0040000>;
- };
- partition@3 {
- label = "QSPI.pmmc-firmware";
- reg = <0x00180000 0x0040000>;
- };
- partition@4 {
- label = "QSPI.kernel";
- reg = <0x001c0000 0x0800000>;
- };
- partition@5 {
- label = "QSPI.u-boot-spl-os";
- reg = <0x009c0000 0x0040000>;
- };
- partition@6 {
- label = "QSPI.file-system";
- reg = <0x00a00000 0x1600000>;
- };
- };
-};
-
-&qmss {
- status = "okay";
-};
-
-&knav_dmas {
- status = "okay";
-};
-
-&netcp {
- pinctrl-names = "default";
- //pinctrl-0 = <&emac_pins>;
- status = "okay";
-};
-
-&mdio {
- pinctrl-names = "default";
- //pinctrl-0 = <&mdio_pins>;
- status = "okay";
- ethphy0: ethernet-phy@0 {
- reg = <0>;
- ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_25_NS>;
- ti,tx-internal-delay = <DP83867_RGMIIDCTL_250_PS>;
- ti,fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_8_B_NIB>;
- ti,min-output-impedance;
- ti,dp83867-rxctrl-strap-quirk;
- };
-};
-
-&gbe0 {
- phy-handle = <ðphy0>;
- phy-mode = "rgmii-id";
- status = "okay";
-};
diff --git a/arch/arm/dts/keystone-k2g-netcp.dtsi b/arch/arm/dts/keystone-k2g-netcp.dtsi
deleted file mode 100644
index 2afb488..0000000
--- a/arch/arm/dts/keystone-k2g-netcp.dtsi
+++ /dev/null
@@ -1,149 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0
-/*
- * Device Tree Source for K2G Netcp driver
- *
- * Copyright (C) 2018 Texas Instruments Incorporated - https://www.ti.com/
- */
-
-qmss: qmss@4020000 {
- compatible = "ti,keystone-navigator-qmss-l";
- dma-coherent;
- #address-cells = <1>;
- #size-cells = <1>;
- /* power-domains = <&k2g_pds K2G_DEV_NSS0>; */
- /* clocks = <&k2g_clks K2G_DEV_NSS0 K2G_DEV_NSS_VCLK>; */
- clock-names = "nss_vclk";
- ranges;
- queue-range = <0 0x80>;
- linkram0 = <0x4020000 0x7ff>;
-
- qmgrs {
- #address-cells = <1>;
- #size-cells = <1>;
- ranges;
- qmgr0 {
- managed-queues = <0 0x80>;
- reg = <0x4100000 0x800>,
- <0x4040000 0x100>,
- <0x4080000 0x800>,
- <0x40c0000 0x800>;
- reg-names = "peek", "config",
- "region", "push";
- };
-
- };
- queue-pools {
- qpend {
- qpend-0 {
- qrange = <77 8>;
- interrupts =<0 308 0xf04 0 309 0xf04 0 310 0xf04
- 0 311 0xf04 0 312 0xf04 0 313 0xf04
- 0 314 0xf04 0 315 0xf04>;
- qalloc-by-id;
- };
- };
- general-purpose {
- gp-0 {
- qrange = <112 8>;
- };
- netcp-tx {
- qrange = <5 8>;
- qalloc-by-id;
- };
- };
- };
-
- descriptor-regions {
- #address-cells = <1>;
- #size-cells = <1>;
- ranges;
- region-12 {
- id = <12>;
- region-spec = <1023 128>; /* num_desc desc_size */
- link-index = <0x400>;
- };
- };
-}; /* qmss */
-
-knav_dmas: knav_dmas@0 {
- compatible = "ti,keystone-navigator-dma";
- #address-cells = <1>;
- #size-cells = <1>;
- /* power-domains = <&k2g_pds K2G_DEV_NSS0>; */
- /* clocks = <&k2g_clks K2G_DEV_NSS0 K2G_DEV_NSS_VCLK>; */
- clock-names = "nss_vclk";
- ranges;
- ti,navigator-cloud-address = <0x40c0000 0x40c0000 0x40c0000 0x40c0000>;
-
- dma_gbe: dma_gbe@0 {
- reg = <0x4010000 0x100>,
- <0x4011000 0x2a0>, /* 21 Tx channels */
- <0x4012000 0x400>, /* 32 Rx channels */
- <0x4010100 0x80>,
- <0x4013000 0x400>; /* 32 Rx flows */
- reg-names = "global", "txchan", "rxchan",
- "txsched", "rxflow";
- };
-
-};
-
-gbe_subsys: subsys@4200000 {
- compatible = "syscon";
- reg = <0x4200000 0x100>;
-};
-
-netcp: netcp@4000000 {
- reg = <0x2620110 0x8>;
- reg-names = "efuse";
- compatible = "ti,netcp-1.0";
- #address-cells = <1>;
- #size-cells = <1>;
- status = "disabled";
- /* power-domains = <&k2g_pds K2G_DEV_NSS0>; */
- /* clocks = <&k2g_clks K2G_DEV_NSS0 K2G_DEV_NSS_ESW_CLK>; */
- clock-names = "ethss_clk";
-
- /* NetCP address range */
- ranges = <0 0x4000000 0x1000000>;
-
- dma-coherent;
-
- ti,navigator-dmas = <&dma_gbe 0>, <&dma_gbe 5>;
- ti,navigator-dma-names = "netrx0", "nettx";
-
- netcp-devices {
- #address-cells = <1>;
- #size-cells = <1>;
- ranges;
- gbe@200000 {
- label = "netcp-gbe";
- compatible = "ti,netcp-gbe-2";
- syscon-subsys = <&gbe_subsys>;
- reg = <0x200100 0xe00>, <0x220000 0x20000>;
- /* enable-ale; */
- tx-queue = <5>;
- tx-channel = "nettx";
-
- interfaces {
- gbe0: interface-0 {
- slave-port = <0>;
- link-interface = <5>;
- };
- };
- };
- };
-
- netcp-interfaces {
- interface-0 {
- rx-channel = "netrx0";
- rx-pool = <512 12>;
- tx-pool = <511 12>;
- rx-queue-depth = <128 128 0 0>;
- rx-buffer-size = <1518 4096 0 0>;
- rx-queue = <77>;
- tx-completion-queue = <78>;
- efuse-mac = <1>;
- netcp-gbe = <&gbe0>;
- };
- };
-};
diff --git a/arch/arm/dts/keystone-k2g.dtsi b/arch/arm/dts/keystone-k2g.dtsi
deleted file mode 100644
index 5c3ff12..0000000
--- a/arch/arm/dts/keystone-k2g.dtsi
+++ /dev/null
@@ -1,258 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0
-/*
- * Device Tree Source for K2G SOC
- *
- * Copyright (C) 2016-2017 Texas Instruments Incorporated - https://www.ti.com/
- */
-
-#include <dt-bindings/interrupt-controller/arm-gic.h>
-
-/ {
- model = "Texas Instruments K2G SoC";
- #address-cells = <1>;
- #size-cells = <1>;
- interrupt-parent = <&gic>;
-
- chosen { };
-
- aliases {
- serial0 = &uart0;
- spi0 = &spi0;
- spi1 = &spi1;
- spi2 = &spi2;
- spi3 = &spi3;
- spi4 = &qspi;
- i2c0 = &i2c0;
- i2c1 = &i2c1;
- i2c2 = &i2c2;
- };
-
- cpus {
- #address-cells = <1>;
- #size-cells = <0>;
-
- interrupt-parent = <&gic>;
-
- cpu@0 {
- compatible = "arm,cortex-a15";
- device_type = "cpu";
- reg = <0>;
- };
- };
-
- gic: interrupt-controller@2561000 {
- compatible = "arm,cortex-a15-gic";
- #interrupt-cells = <3>;
- interrupt-controller;
- reg = <0x0 0x02561000 0x0 0x1000>,
- <0x0 0x02562000 0x0 0x2000>,
- <0x0 0x02564000 0x0 0x1000>,
- <0x0 0x02566000 0x0 0x2000>;
- interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) |
- IRQ_TYPE_LEVEL_HIGH)>;
- };
-
- soc {
- #address-cells = <1>;
- #size-cells = <1>;
- compatible = "ti,keystone","simple-bus";
- interrupt-parent = <&gic>;
- ranges;
-
- uart0: serial@02530c00 {
- compatible = "ns16550a";
- current-speed = <115200>;
- reg-shift = <2>;
- reg-io-width = <4>;
- reg = <0x02530c00 0x100>;
- clock-names = "uart";
- interrupts = <GIC_SPI 164 IRQ_TYPE_EDGE_RISING>;
- };
-
- mdio: mdio@4200f00 {
- compatible = "ti,keystone_mdio", "ti,davinci_mdio";
- #address-cells = <1>;
- #size-cells = <0>;
- /* power-domains = <&k2g_pds K2G_DEV_NSS0>; */
- /* clocks = <&k2g_clks K2G_DEV_NSS0 K2G_DEV_NSS_ESW_CLK>; */
- clock-names = "fck";
- reg = <0x04200f00 0x100>;
- status = "disabled";
- bus_freq = <2500000>;
- };
-
- qspi: qspi@2940000 {
- compatible = "cdns,qspi-nor";
- #address-cells = <1>;
- #size-cells = <0>;
- reg = <0x02940000 0x1000>,
- <0x24000000 0x4000000>;
- interrupts = <GIC_SPI 198 IRQ_TYPE_EDGE_RISING>;
- num-cs = <4>;
- cdns,fifo-depth = <256>;
- cdns,fifo-width = <4>;
- cdns,trigger-address = <0x24000000>;
- status = "disabled";
- };
-
- #include "keystone-k2g-netcp.dtsi"
-
- pmmc: pmmc@2900000 {
- compatible = "ti,power-processor";
- reg = <0x02900000 0x40000>;
- ti,lpsc_module = <1>;
- };
-
- spi0: spi@21805400 {
- compatible = "ti,keystone-spi", "ti,dm6441-spi";
- reg = <0x21805400 0x200>;
- num-cs = <4>;
- ti,davinci-spi-intr-line = <0>;
- interrupts = <GIC_SPI 64 IRQ_TYPE_EDGE_RISING>;
- #address-cells = <1>;
- #size-cells = <0>;
- status = "disabled";
- };
-
- spi1: spi@21805800 {
- compatible = "ti,keystone-spi", "ti,dm6441-spi";
- reg = <0x21805800 0x200>;
- num-cs = <4>;
- ti,davinci-spi-intr-line = <0>;
- interrupts = <GIC_SPI 66 IRQ_TYPE_EDGE_RISING>;
- #address-cells = <1>;
- #size-cells = <0>;
- status = "disabled";
- };
-
- spi2: spi@21805c00 {
- compatible = "ti,keystone-spi", "ti,dm6441-spi";
- reg = <0x21805C00 0x200>;
- num-cs = <4>;
- ti,davinci-spi-intr-line = <0>;
- interrupts = <GIC_SPI 68 IRQ_TYPE_EDGE_RISING>;
- #address-cells = <1>;
- #size-cells = <0>;
- status = "disabled";
- };
-
- spi3: spi@21806000 {
- compatible = "ti,keystone-spi", "ti,dm6441-spi";
- reg = <0x21806000 0x200>;
- num-cs = <4>;
- ti,davinci-spi-intr-line = <0>;
- interrupts = <GIC_SPI 70 IRQ_TYPE_EDGE_RISING>;
- #address-cells = <1>;
- #size-cells = <0>;
- status = "disabled";
- };
- i2c0: i2c@2530000 {
- compatible = "ti,keystone-i2c";
- reg = <0x02530000 0x400>;
- clock-frequency = <100000>;
- interrupts = <GIC_SPI 88 IRQ_TYPE_EDGE_RISING>;
- #address-cells = <1>;
- #size-cells = <0>;
- status = "disabled";
- };
-
- i2c1: i2c@2530400 {
- compatible = "ti,keystone-i2c";
- reg = <0x02530400 0x400>;
- clock-frequency = <100000>;
- interrupts = <GIC_SPI 89 IRQ_TYPE_EDGE_RISING>;
- #address-cells = <1>;
- #size-cells = <0>;
- status = "disabled";
- };
-
- i2c2: i2c@2530800 {
- compatible = "ti,keystone-i2c";
- reg = <0x02530800 0x400>;
- clock-frequency = <100000>;
- interrupts = <GIC_SPI 90 IRQ_TYPE_EDGE_RISING>;
- #address-cells = <1>;
- #size-cells = <0>;
- status = "disabled";
- };
-
- mmc0: mmc@23000000 {
- compatible = "ti,omap4-hsmmc";
- reg = <0x23000000 0x400>;
- interrupts = <GIC_SPI 96 IRQ_TYPE_EDGE_RISING>;
- bus-width = <4>;
- ti,needs-special-reset;
- no-1-8-v;
- max-frequency = <96000000>;
- status = "disabled";
- };
-
- mmc1: mmc@23100000 {
- compatible = "ti,omap4-hsmmc";
- reg = <0x23100000 0x400>;
- interrupts = <GIC_SPI 97 IRQ_TYPE_EDGE_RISING>;
- bus-width = <8>;
- ti,needs-special-reset;
- ti,non-removable;
- max-frequency = <96000000>;
- status = "disabled";
- clock-names = "fck";
- };
-
- usb0_phy: usb-phy@0 {
- compatible = "usb-nop-xceiv";
- status = "disabled";
- };
-
- keystone_usb0: keystone-dwc3@2680000 {
- compatible = "ti,keystone-dwc3";
- #address-cells = <1>;
- #size-cells = <1>;
- reg = <0x2680000 0x10000>;
- interrupts = <GIC_SPI 128 IRQ_TYPE_EDGE_RISING>;
- ranges;
- dma-coherent;
- dma-ranges;
- status = "disabled";
- /*power-domains = <&k2g_pds 0x0016>;*/
-
- usb0: usb@2690000 {
- compatible = "snps,dwc3";
- reg = <0x2690000 0x10000>;
- interrupts = <GIC_SPI 128 IRQ_TYPE_EDGE_RISING>;
- maximum-speed = "high-speed";
- dr_mode = "otg";
- /*usb-phy = <&usb0_phy>;*/
- status = "disabled";
- };
- };
-
- usb1_phy: usb-phy@1 {
- compatible = "usb-nop-xceiv";
- status = "disabled";
- };
-
- keystone_usb1: keystone-dwc3@2580000 {
- compatible = "ti,keystone-dwc3";
- #address-cells = <1>;
- #size-cells = <1>;
- reg = <0x2580000 0x10000>;
- interrupts = <GIC_SPI 144 IRQ_TYPE_EDGE_RISING>;
- ranges;
- dma-coherent;
- dma-ranges;
- status = "disabled";
- /*power-domains = <&k2g_pds 0x0017>;*/
-
- usb1: usb@2590000 {
- compatible = "snps,dwc3";
- reg = <0x2590000 0x10000>;
- interrupts = <GIC_SPI 144 IRQ_TYPE_EDGE_RISING>;
- maximum-speed = "high-speed";
- dr_mode = "otg";
- /*usb-phy = <&usb1_phy>;*/
- status = "disabled";
- };
- };
- };
-};
diff --git a/arch/arm/dts/keystone-k2hk-clocks.dtsi b/arch/arm/dts/keystone-k2hk-clocks.dtsi
deleted file mode 100644
index 3ca4722..0000000
--- a/arch/arm/dts/keystone-k2hk-clocks.dtsi
+++ /dev/null
@@ -1,422 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0
-/*
- * Keystone 2 Kepler/Hawking SoC clock nodes
- *
- * Copyright (C) 2013-2017 Texas Instruments Incorporated - https://www.ti.com/
- */
-
-clocks {
- armpllclk: armpllclk@2620370 {
- #clock-cells = <0>;
- compatible = "ti,keystone,pll-clock";
- clocks = <&refclkarm>;
- clock-output-names = "arm-pll-clk";
- reg = <0x02620370 4>;
- reg-names = "control";
- };
-
- mainpllclk: mainpllclk@2310110 {
- #clock-cells = <0>;
- compatible = "ti,keystone,main-pll-clock";
- clocks = <&refclksys>;
- reg = <0x02620350 4>, <0x02310110 4>, <0x02310108 4>;
- reg-names = "control", "multiplier", "post-divider";
- };
-
- papllclk: papllclk@2620358 {
- #clock-cells = <0>;
- compatible = "ti,keystone,pll-clock";
- clocks = <&refclkpass>;
- clock-output-names = "papllclk";
- reg = <0x02620358 4>;
- reg-names = "control";
- };
-
- ddr3apllclk: ddr3apllclk@2620360 {
- #clock-cells = <0>;
- compatible = "ti,keystone,pll-clock";
- clocks = <&refclkddr3a>;
- clock-output-names = "ddr-3a-pll-clk";
- reg = <0x02620360 4>;
- reg-names = "control";
- };
-
- ddr3bpllclk: ddr3bpllclk@2620368 {
- #clock-cells = <0>;
- compatible = "ti,keystone,pll-clock";
- clocks = <&refclkddr3b>;
- clock-output-names = "ddr-3b-pll-clk";
- reg = <0x02620368 4>;
- reg-names = "control";
- };
-
- clktsip: clktsip@2350000 {
- #clock-cells = <0>;
- compatible = "ti,keystone,psc-clock";
- clocks = <&chipclk16>;
- clock-output-names = "tsip";
- reg = <0x02350000 0xb00>, <0x02350000 0x400>;
- reg-names = "control", "domain";
- domain-id = <0>;
- };
-
- clksrio: clksrio@235002c {
- #clock-cells = <0>;
- compatible = "ti,keystone,psc-clock";
- clocks = <&chipclk1rstiso13>;
- clock-output-names = "srio";
- reg = <0x0235002c 0xb00>, <0x02350010 0x400>;
- reg-names = "control", "domain";
- domain-id = <4>;
- };
-
- clkhyperlink0: clkhyperlink0@2350030 {
- #clock-cells = <0>;
- compatible = "ti,keystone,psc-clock";
- clocks = <&chipclk12>;
- clock-output-names = "hyperlink-0";
- reg = <0x02350030 0xb00>, <0x02350014 0x400>;
- reg-names = "control", "domain";
- domain-id = <5>;
- };
-
- clkgem1: clkgem1@2350040 {
- #clock-cells = <0>;
- compatible = "ti,keystone,psc-clock";
- clocks = <&chipclk1>;
- clock-output-names = "gem1";
- reg = <0x02350040 0xb00>, <0x02350024 0x400>;
- reg-names = "control", "domain";
- domain-id = <9>;
- };
-
- clkgem2: clkgem2@2350044 {
- #clock-cells = <0>;
- compatible = "ti,keystone,psc-clock";
- clocks = <&chipclk1>;
- clock-output-names = "gem2";
- reg = <0x02350044 0xb00>, <0x02350028 0x400>;
- reg-names = "control", "domain";
- domain-id = <10>;
- };
-
- clkgem3: clkgem3@2350048 {
- #clock-cells = <0>;
- compatible = "ti,keystone,psc-clock";
- clocks = <&chipclk1>;
- clock-output-names = "gem3";
- reg = <0x02350048 0xb00>, <0x0235002c 0x400>;
- reg-names = "control", "domain";
- domain-id = <11>;
- };
-
- clkgem4: clkgem4@235004c {
- #clock-cells = <0>;
- compatible = "ti,keystone,psc-clock";
- clocks = <&chipclk1>;
- clock-output-names = "gem4";
- reg = <0x0235004c 0xb00>, <0x02350030 0x400>;
- reg-names = "control", "domain";
- domain-id = <12>;
- };
-
- clkgem5: clkgem5@2350050 {
- #clock-cells = <0>;
- compatible = "ti,keystone,psc-clock";
- clocks = <&chipclk1>;
- clock-output-names = "gem5";
- reg = <0x02350050 0xb00>, <0x02350034 0x400>;
- reg-names = "control", "domain";
- domain-id = <13>;
- };
-
- clkgem6: clkgem6@2350054 {
- #clock-cells = <0>;
- compatible = "ti,keystone,psc-clock";
- clocks = <&chipclk1>;
- clock-output-names = "gem6";
- reg = <0x02350054 0xb00>, <0x02350038 0x400>;
- reg-names = "control", "domain";
- domain-id = <14>;
- };
-
- clkgem7: clkgem7@2350058 {
- #clock-cells = <0>;
- compatible = "ti,keystone,psc-clock";
- clocks = <&chipclk1>;
- clock-output-names = "gem7";
- reg = <0x02350058 0xb00>, <0x0235003c 0x400>;
- reg-names = "control", "domain";
- domain-id = <15>;
- };
-
- clkddr31: clkddr31@2350060 {
- #clock-cells = <0>;
- compatible = "ti,keystone,psc-clock";
- clocks = <&chipclk13>;
- clock-output-names = "ddr3-1";
- reg = <0x02350060 0xb00>, <0x02350040 0x400>;
- reg-names = "control", "domain";
- domain-id = <16>;
- };
-
- clktac: clktac@2350064 {
- #clock-cells = <0>;
- compatible = "ti,keystone,psc-clock";
- clocks = <&chipclk13>;
- clock-output-names = "tac";
- reg = <0x02350064 0xb00>, <0x02350044 0x400>;
- reg-names = "control", "domain";
- domain-id = <17>;
- };
-
- clkrac01: clkrac01@2350068 {
- #clock-cells = <0>;
- compatible = "ti,keystone,psc-clock";
- clocks = <&chipclk13>;
- clock-output-names = "rac-01";
- reg = <0x02350068 0xb00>, <0x02350044 0x400>;
- reg-names = "control", "domain";
- domain-id = <17>;
- };
-
- clkrac23: clkrac23@235006c {
- #clock-cells = <0>;
- compatible = "ti,keystone,psc-clock";
- clocks = <&chipclk13>;
- clock-output-names = "rac-23";
- reg = <0x0235006c 0xb00>, <0x02350048 0x400>;
- reg-names = "control", "domain";
- domain-id = <18>;
- };
-
- clkfftc0: clkfftc0@2350070 {
- #clock-cells = <0>;
- compatible = "ti,keystone,psc-clock";
- clocks = <&chipclk13>;
- clock-output-names = "fftc-0";
- reg = <0x02350070 0xb00>, <0x0235004c 0x400>;
- reg-names = "control", "domain";
- domain-id = <19>;
- };
-
- clkfftc1: clkfftc1@2350074 {
- #clock-cells = <0>;
- compatible = "ti,keystone,psc-clock";
- clocks = <&chipclk13>;
- clock-output-names = "fftc-1";
- reg = <0x02350074 0xb00>, <0x0235004c 0x400>;
- reg-names = "control", "domain";
- domain-id = <19>;
- };
-
- clkfftc2: clkfftc2@2350078 {
- #clock-cells = <0>;
- compatible = "ti,keystone,psc-clock";
- clocks = <&chipclk13>;
- clock-output-names = "fftc-2";
- reg = <0x02350078 0xb00>, <0x02350050 0x400>;
- reg-names = "control", "domain";
- domain-id = <20>;
- };
-
- clkfftc3: clkfftc3@235007c {
- #clock-cells = <0>;
- compatible = "ti,keystone,psc-clock";
- clocks = <&chipclk13>;
- clock-output-names = "fftc-3";
- reg = <0x0235007c 0xb00>, <0x02350050 0x400>;
- reg-names = "control", "domain";
- domain-id = <20>;
- };
-
- clkfftc4: clkfftc4@2350080 {
- #clock-cells = <0>;
- compatible = "ti,keystone,psc-clock";
- clocks = <&chipclk13>;
- clock-output-names = "fftc-4";
- reg = <0x02350080 0xb00>, <0x02350050 0x400>;
- reg-names = "control", "domain";
- domain-id = <20>;
- };
-
- clkfftc5: clkfftc5@2350084 {
- #clock-cells = <0>;
- compatible = "ti,keystone,psc-clock";
- clocks = <&chipclk13>;
- clock-output-names = "fftc-5";
- reg = <0x02350084 0xb00>, <0x02350050 0x400>;
- reg-names = "control", "domain";
- domain-id = <20>;
- };
-
- clkaif: clkaif@2350088 {
- #clock-cells = <0>;
- compatible = "ti,keystone,psc-clock";
- clocks = <&chipclk13>;
- clock-output-names = "aif";
- reg = <0x02350088 0xb00>, <0x02350054 0x400>;
- reg-names = "control", "domain";
- domain-id = <21>;
- };
-
- clktcp3d0: clktcp3d0@235008c {
- #clock-cells = <0>;
- compatible = "ti,keystone,psc-clock";
- clocks = <&chipclk13>;
- clock-output-names = "tcp3d-0";
- reg = <0x0235008c 0xb00>, <0x02350058 0x400>;
- reg-names = "control", "domain";
- domain-id = <22>;
- };
-
- clktcp3d1: clktcp3d1@2350090 {
- #clock-cells = <0>;
- compatible = "ti,keystone,psc-clock";
- clocks = <&chipclk13>;
- clock-output-names = "tcp3d-1";
- reg = <0x02350090 0xb00>, <0x02350058 0x400>;
- reg-names = "control", "domain";
- domain-id = <22>;
- };
-
- clktcp3d2: clktcp3d2@2350094 {
- #clock-cells = <0>;
- compatible = "ti,keystone,psc-clock";
- clocks = <&chipclk13>;
- clock-output-names = "tcp3d-2";
- reg = <0x02350094 0xb00>, <0x0235005c 0x400>;
- reg-names = "control", "domain";
- domain-id = <23>;
- };
-
- clktcp3d3: clktcp3d3@2350098 {
- #clock-cells = <0>;
- compatible = "ti,keystone,psc-clock";
- clocks = <&chipclk13>;
- clock-output-names = "tcp3d-3";
- reg = <0x02350098 0xb00>, <0x0235005c 0x400>;
- reg-names = "control", "domain";
- domain-id = <23>;
- };
-
- clkvcp0: clkvcp0@235009c {
- #clock-cells = <0>;
- compatible = "ti,keystone,psc-clock";
- clocks = <&chipclk13>;
- clock-output-names = "vcp-0";
- reg = <0x0235009c 0xb00>, <0x02350060 0x400>;
- reg-names = "control", "domain";
- domain-id = <24>;
- };
-
- clkvcp1: clkvcp1@23500a0 {
- #clock-cells = <0>;
- compatible = "ti,keystone,psc-clock";
- clocks = <&chipclk13>;
- clock-output-names = "vcp-1";
- reg = <0x023500a0 0xb00>, <0x02350060 0x400>;
- reg-names = "control", "domain";
- domain-id = <24>;
- };
-
- clkvcp2: clkvcp2@23500a4 {
- #clock-cells = <0>;
- compatible = "ti,keystone,psc-clock";
- clocks = <&chipclk13>;
- clock-output-names = "vcp-2";
- reg = <0x023500a4 0xb00>, <0x02350060 0x400>;
- reg-names = "control", "domain";
- domain-id = <24>;
- };
-
- clkvcp3: clkvcp3@23500a8 {
- #clock-cells = <0>;
- compatible = "ti,keystone,psc-clock";
- clocks = <&chipclk13>;
- clock-output-names = "vcp-3";
- reg = <0x023500a8 0xb00>, <0x02350060 0x400>;
- reg-names = "control", "domain";
- domain-id = <24>;
- };
-
- clkvcp4: clkvcp4@23500ac {
- #clock-cells = <0>;
- compatible = "ti,keystone,psc-clock";
- clocks = <&chipclk13>;
- clock-output-names = "vcp-4";
- reg = <0x023500ac 0xb00>, <0x02350064 0x400>;
- reg-names = "control", "domain";
- domain-id = <25>;
- };
-
- clkvcp5: clkvcp5@23500b0 {
- #clock-cells = <0>;
- compatible = "ti,keystone,psc-clock";
- clocks = <&chipclk13>;
- clock-output-names = "vcp-5";
- reg = <0x023500b0 0xb00>, <0x02350064 0x400>;
- reg-names = "control", "domain";
- domain-id = <25>;
- };
-
- clkvcp6: clkvcp6@23500b4 {
- #clock-cells = <0>;
- compatible = "ti,keystone,psc-clock";
- clocks = <&chipclk13>;
- clock-output-names = "vcp-6";
- reg = <0x023500b4 0xb00>, <0x02350064 0x400>;
- reg-names = "control", "domain";
- domain-id = <25>;
- };
-
- clkvcp7: clkvcp7@23500b8 {
- #clock-cells = <0>;
- compatible = "ti,keystone,psc-clock";
- clocks = <&chipclk13>;
- clock-output-names = "vcp-7";
- reg = <0x023500b8 0xb00>, <0x02350064 0x400>;
- reg-names = "control", "domain";
- domain-id = <25>;
- };
-
- clkbcp: clkbcp@23500bc {
- #clock-cells = <0>;
- compatible = "ti,keystone,psc-clock";
- clocks = <&chipclk13>;
- clock-output-names = "bcp";
- reg = <0x023500bc 0xb00>, <0x02350068 0x400>;
- reg-names = "control", "domain";
- domain-id = <26>;
- };
-
- clkdxb: clkdxb@23500c0 {
- #clock-cells = <0>;
- compatible = "ti,keystone,psc-clock";
- clocks = <&chipclk13>;
- clock-output-names = "dxb";
- reg = <0x023500c0 0xb00>, <0x0235006c 0x400>;
- reg-names = "control", "domain";
- domain-id = <27>;
- };
-
- clkhyperlink1: clkhyperlink1@23500c4 {
- #clock-cells = <0>;
- compatible = "ti,keystone,psc-clock";
- clocks = <&chipclk12>;
- clock-output-names = "hyperlink-1";
- reg = <0x023500c4 0xb00>, <0x02350070 0x400>;
- reg-names = "control", "domain";
- domain-id = <28>;
- };
-
- clkxge: clkxge@23500c8 {
- #clock-cells = <0>;
- compatible = "ti,keystone,psc-clock";
- clocks = <&chipclk13>;
- clock-output-names = "xge";
- reg = <0x023500c8 0xb00>, <0x02350074 0x400>;
- reg-names = "control", "domain";
- domain-id = <29>;
- };
-};
diff --git a/arch/arm/dts/keystone-k2hk-evm-u-boot.dtsi b/arch/arm/dts/keystone-k2hk-evm-u-boot.dtsi
index 3e38f22..3b3d327 100644
--- a/arch/arm/dts/keystone-k2hk-evm-u-boot.dtsi
+++ b/arch/arm/dts/keystone-k2hk-evm-u-boot.dtsi
@@ -4,9 +4,19 @@
*/
/{
- soc {
- bootph-all;
+ aliases {
+ i2c0 = &i2c0;
+ i2c1 = &i2c1;
+ i2c2 = &i2c2;
};
+
+ chosen {
+ stdout-path = &uart0;
+ };
+};
+
+&soc0 {
+ bootph-all;
};
&i2c1 {
@@ -18,11 +28,9 @@
psc-domain = <2>;
};
-&usb {
- dwc3@2690000 {
- phys = <&usb_phy>;
- dr_mode = "host";
- snps,u2ss_inp3_quirk;
- status = "okay";
- };
+&usb0 {
+ phys = <&usb_phy>;
+ dr_mode = "host";
+ snps,u2ss_inp3_quirk;
+ status = "okay";
};
diff --git a/arch/arm/dts/keystone-k2hk-evm.dts b/arch/arm/dts/keystone-k2hk-evm.dts
deleted file mode 100644
index 6222876..0000000
--- a/arch/arm/dts/keystone-k2hk-evm.dts
+++ /dev/null
@@ -1,180 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0
-/*
- * Keystone 2 Kepler/Hawking EVM device tree
- *
- * Copyright (C) 2013-2017 Texas Instruments Incorporated - https://www.ti.com/
- */
-/dts-v1/;
-
-#include "keystone.dtsi"
-#include "keystone-k2hk.dtsi"
-
-/ {
- compatible = "ti,k2hk-evm","ti,keystone";
- model = "Texas Instruments Keystone 2 Kepler/Hawking EVM";
-
- soc {
- clocks {
- refclksys: refclksys {
- #clock-cells = <0>;
- compatible = "fixed-clock";
- clock-frequency = <122880000>;
- clock-output-names = "refclk-sys";
- };
-
- refclkpass: refclkpass {
- #clock-cells = <0>;
- compatible = "fixed-clock";
- clock-frequency = <122880000>;
- clock-output-names = "refclk-pass";
- };
-
- refclkarm: refclkarm {
- #clock-cells = <0>;
- compatible = "fixed-clock";
- clock-frequency = <125000000>;
- clock-output-names = "refclk-arm";
- };
-
- refclkddr3a: refclkddr3a {
- #clock-cells = <0>;
- compatible = "fixed-clock";
- clock-frequency = <100000000>;
- clock-output-names = "refclk-ddr3a";
- };
-
- refclkddr3b: refclkddr3b {
- #clock-cells = <0>;
- compatible = "fixed-clock";
- clock-frequency = <100000000>;
- clock-output-names = "refclk-ddr3b";
- };
- };
- };
-
- leds {
- compatible = "gpio-leds";
- led-debug-1-1 {
- label = "keystone:green:debug1";
- gpios = <&gpio0 12 GPIO_ACTIVE_HIGH>; /* 12 */
- };
-
- led-debug-1-2 {
- label = "keystone:red:debug1";
- gpios = <&gpio0 13 GPIO_ACTIVE_HIGH>; /* 13 */
- };
-
- led-debug-2 {
- label = "keystone:blue:debug2";
- gpios = <&gpio0 14 GPIO_ACTIVE_HIGH>; /* 14 */
- };
-
- led-debug-3 {
- label = "keystone:blue:debug3";
- gpios = <&gpio0 15 GPIO_ACTIVE_HIGH>; /* 15 */
- };
- };
-};
-
-&usb_phy {
- status = "okay";
-};
-
-&usb {
- status = "okay";
-};
-
-&aemif {
- cs0 {
- #address-cells = <2>;
- #size-cells = <1>;
- clock-ranges;
- ranges;
-
- ti,cs-chipselect = <0>;
- /* all timings in nanoseconds */
- ti,cs-min-turnaround-ns = <12>;
- ti,cs-read-hold-ns = <6>;
- ti,cs-read-strobe-ns = <23>;
- ti,cs-read-setup-ns = <9>;
- ti,cs-write-hold-ns = <8>;
- ti,cs-write-strobe-ns = <23>;
- ti,cs-write-setup-ns = <8>;
-
- nand@0,0 {
- compatible = "ti,keystone-nand","ti,davinci-nand";
- #address-cells = <1>;
- #size-cells = <1>;
- reg = <0 0 0x4000000
- 1 0 0x0000100>;
-
- ti,davinci-chipselect = <0>;
- ti,davinci-mask-ale = <0x2000>;
- ti,davinci-mask-cle = <0x4000>;
- ti,davinci-mask-chipsel = <0>;
- nand-ecc-mode = "hw";
- ti,davinci-ecc-bits = <4>;
- nand-on-flash-bbt;
-
- partition@0 {
- label = "u-boot";
- reg = <0x0 0x100000>;
- read-only;
- };
-
- partition@100000 {
- label = "params";
- reg = <0x100000 0x80000>;
- read-only;
- };
-
- partition@180000 {
- label = "ubifs";
- reg = <0x180000 0x1fe80000>;
- };
- };
- };
-};
-
-&i2c0 {
- dtt@50 {
- compatible = "at,24c1024";
- reg = <0x50>;
- };
-};
-
-&spi0 {
- status = "okay";
- nor_flash: flash@0 {
- #address-cells = <1>;
- #size-cells = <1>;
- compatible = "Micron,n25q128a11", "jedec,spi-nor";
- spi-max-frequency = <54000000>;
- m25p,fast-read;
- reg = <0>;
-
- partition@0 {
- label = "u-boot-spl";
- reg = <0x0 0x80000>;
- read-only;
- };
-
- partition@1 {
- label = "misc";
- reg = <0x80000 0xf80000>;
- };
- };
-};
-
-&mdio {
- status = "okay";
- ethphy0: ethernet-phy@0 {
- compatible = "marvell,88E1111", "ethernet-phy-ieee802.3-c22";
- reg = <0>;
- };
-
- ethphy1: ethernet-phy@1 {
- compatible = "marvell,88E1111", "ethernet-phy-ieee802.3-c22";
- reg = <1>;
- };
-};
diff --git a/arch/arm/dts/keystone-k2hk-netcp.dtsi b/arch/arm/dts/keystone-k2hk-netcp.dtsi
deleted file mode 100644
index 3f8c4c2..0000000
--- a/arch/arm/dts/keystone-k2hk-netcp.dtsi
+++ /dev/null
@@ -1,207 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0
-/*
- * Device Tree Source for Keystone 2 Hawking Netcp driver
- *
- * Copyright (C) 2015-2017 Texas Instruments Incorporated - https://www.ti.com/
- */
-
-qmss: qmss@2a40000 {
- compatible = "ti,keystone-navigator-qmss";
- dma-coherent;
- #address-cells = <1>;
- #size-cells = <1>;
- clocks = <&chipclk13>;
- ranges;
- queue-range = <0 0x4000>;
- linkram0 = <0x100000 0x8000>;
- linkram1 = <0x0 0x10000>;
-
- qmgrs {
- #address-cells = <1>;
- #size-cells = <1>;
- ranges;
- qmgr0 {
- managed-queues = <0 0x2000>;
- reg = <0x2a40000 0x20000>,
- <0x2a06000 0x400>,
- <0x2a02000 0x1000>,
- <0x2a03000 0x1000>,
- <0x23a80000 0x20000>,
- <0x2a80000 0x20000>;
- reg-names = "peek", "status", "config",
- "region", "push", "pop";
- };
-
- qmgr1 {
- managed-queues = <0x2000 0x2000>;
- reg = <0x2a60000 0x20000>,
- <0x2a06400 0x400>,
- <0x2a04000 0x1000>,
- <0x2a05000 0x1000>,
- <0x23aa0000 0x20000>,
- <0x2aa0000 0x20000>;
- reg-names = "peek", "status", "config",
- "region", "push", "pop";
- };
- };
-
- queue-pools {
- qpend {
- qpend-0 {
- qrange = <658 8>;
- interrupts =<0 40 0xf04 0 41 0xf04 0 42 0xf04
- 0 43 0xf04 0 44 0xf04 0 45 0xf04
- 0 46 0xf04 0 47 0xf04>;
- };
- qpend-1 {
- qrange = <8704 16>;
- interrupts = <0 48 0xf04 0 49 0xf04 0 50 0xf04
- 0 51 0xf04 0 52 0xf04 0 53 0xf04
- 0 54 0xf04 0 55 0xf04 0 56 0xf04
- 0 57 0xf04 0 58 0xf04 0 59 0xf04
- 0 60 0xf04 0 61 0xf04 0 62 0xf04
- 0 63 0xf04>;
- qalloc-by-id;
- };
- qpend-2 {
- qrange = <8720 16>;
- interrupts = <0 64 0xf04 0 65 0xf04 0 66 0xf04
- 0 59 0xf04 0 68 0xf04 0 69 0xf04
- 0 70 0xf04 0 71 0xf04 0 72 0xf04
- 0 73 0xf04 0 74 0xf04 0 75 0xf04
- 0 76 0xf04 0 77 0xf04 0 78 0xf04
- 0 79 0xf04>;
- };
- };
- general-purpose {
- gp-0 {
- qrange = <4000 64>;
- };
- netcp-tx {
- qrange = <640 9>;
- qalloc-by-id;
- };
- netcpx-tx {
- qrange = <8752 8>;
- qalloc-by-id;
- };
- };
- };
-
- descriptor-regions {
- #address-cells = <1>;
- #size-cells = <1>;
- ranges;
- region-12 {
- id = <12>;
- region-spec = <8192 128>; /* num_desc desc_size */
- link-index = <0x4000>;
- };
- };
-}; /* qmss */
-
-knav_dmas: knav_dmas@0 {
- compatible = "ti,keystone-navigator-dma";
- clocks = <&papllclk>;
- #address-cells = <1>;
- #size-cells = <1>;
- ranges;
- ti,navigator-cloud-address = <0x23a80000 0x23a90000
- 0x23aa0000 0x23ab0000>;
-
- dma_gbe: dma_gbe@0 {
- reg = <0x2004000 0x100>,
- <0x2004400 0x120>,
- <0x2004800 0x300>,
- <0x2004c00 0x120>,
- <0x2005000 0x400>;
- reg-names = "global", "txchan", "rxchan",
- "txsched", "rxflow";
- };
-};
-
-netcp: netcp@2000000 {
- reg = <0x2620110 0x8>;
- reg-names = "efuse";
- compatible = "ti,netcp-1.0";
- #address-cells = <1>;
- #size-cells = <1>;
-
- /* NetCP address range */
- ranges = <0 0x2000000 0x100000>;
-
- clocks = <&papllclk>, <&clkcpgmac>, <&chipclk12>;
- dma-coherent;
-
- ti,navigator-dmas = <&dma_gbe 22>,
- <&dma_gbe 23>,
- <&dma_gbe 8>;
- ti,navigator-dma-names = "netrx0", "netrx1", "nettx";
-
- netcp-devices {
- ranges;
- #address-cells = <1>;
- #size-cells = <1>;
- gbe@90000 { /* ETHSS */
- #address-cells = <1>;
- #size-cells = <1>;
- label = "netcp-gbe";
- compatible = "ti,netcp-gbe";
- reg = <0x90000 0x300>, <0x90400 0x400>, <0x90800 0x700>;
- /* enable-ale; */
- tx-queue = <648>;
- tx-channel = "nettx";
-
- interfaces {
- gbe0: interface-0 {
- slave-port = <0>;
- link-interface = <1>;
- phy-handle = <ðphy0>;
- };
- gbe1: interface-1 {
- slave-port = <1>;
- link-interface = <1>;
- phy-handle = <ðphy1>;
- };
- };
-
- secondary-slave-ports {
- port-2 {
- slave-port = <2>;
- link-interface = <2>;
- };
- port-3 {
- slave-port = <3>;
- link-interface = <2>;
- };
- };
- };
- };
-
- netcp-interfaces {
- interface-0 {
- rx-channel = "netrx0";
- rx-pool = <1024 12>;
- tx-pool = <1024 12>;
- rx-queue-depth = <128 128 0 0>;
- rx-buffer-size = <1518 4096 0 0>;
- rx-queue = <8704>;
- tx-completion-queue = <8706>;
- efuse-mac = <1>;
- netcp-gbe = <&gbe0>;
-
- };
- interface-1 {
- rx-channel = "netrx1";
- rx-pool = <1024 12>;
- tx-pool = <1024 12>;
- rx-queue-depth = <128 128 0 0>;
- rx-buffer-size = <1518 4096 0 0>;
- rx-queue = <8705>;
- tx-completion-queue = <8707>;
- efuse-mac = <0>;
- local-mac-address = [02 18 31 7e 3e 6f];
- netcp-gbe = <&gbe1>;
- };
- };
-};
diff --git a/arch/arm/dts/keystone-k2hk.dtsi b/arch/arm/dts/keystone-k2hk.dtsi
deleted file mode 100644
index e5ab1fb..0000000
--- a/arch/arm/dts/keystone-k2hk.dtsi
+++ /dev/null
@@ -1,111 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0
-/*
- * Keystone 2 Kepler/Hawking soc specific device tree
- *
- * Copyright (C) 2013-2017 Texas Instruments Incorporated - https://www.ti.com/
- */
-
-/ {
- cpus {
- #address-cells = <1>;
- #size-cells = <0>;
-
- interrupt-parent = <&gic>;
-
- cpu@0 {
- compatible = "arm,cortex-a15";
- device_type = "cpu";
- reg = <0>;
- };
-
- cpu@1 {
- compatible = "arm,cortex-a15";
- device_type = "cpu";
- reg = <1>;
- };
-
- cpu@2 {
- compatible = "arm,cortex-a15";
- device_type = "cpu";
- reg = <2>;
- };
-
- cpu@3 {
- compatible = "arm,cortex-a15";
- device_type = "cpu";
- reg = <3>;
- };
- };
-
- soc {
- /include/ "keystone-k2hk-clocks.dtsi"
-
- dspgpio0: keystone_dsp_gpio@02620240 {
- compatible = "ti,keystone-dsp-gpio";
- gpio-controller;
- #gpio-cells = <2>;
- gpio,syscon-dev = <&devctrl 0x240>;
- };
-
- dspgpio1: keystone_dsp_gpio@2620244 {
- compatible = "ti,keystone-dsp-gpio";
- gpio-controller;
- #gpio-cells = <2>;
- gpio,syscon-dev = <&devctrl 0x244>;
- };
-
- dspgpio2: keystone_dsp_gpio@2620248 {
- compatible = "ti,keystone-dsp-gpio";
- gpio-controller;
- #gpio-cells = <2>;
- gpio,syscon-dev = <&devctrl 0x248>;
- };
-
- dspgpio3: keystone_dsp_gpio@262024c {
- compatible = "ti,keystone-dsp-gpio";
- gpio-controller;
- #gpio-cells = <2>;
- gpio,syscon-dev = <&devctrl 0x24c>;
- };
-
- dspgpio4: keystone_dsp_gpio@2620250 {
- compatible = "ti,keystone-dsp-gpio";
- gpio-controller;
- #gpio-cells = <2>;
- gpio,syscon-dev = <&devctrl 0x250>;
- };
-
- dspgpio5: keystone_dsp_gpio@2620254 {
- compatible = "ti,keystone-dsp-gpio";
- gpio-controller;
- #gpio-cells = <2>;
- gpio,syscon-dev = <&devctrl 0x254>;
- };
-
- dspgpio6: keystone_dsp_gpio@2620258 {
- compatible = "ti,keystone-dsp-gpio";
- gpio-controller;
- #gpio-cells = <2>;
- gpio,syscon-dev = <&devctrl 0x258>;
- };
-
- dspgpio7: keystone_dsp_gpio@262025c {
- compatible = "ti,keystone-dsp-gpio";
- gpio-controller;
- #gpio-cells = <2>;
- gpio,syscon-dev = <&devctrl 0x25c>;
- };
-
- mdio: mdio@02090300 {
- compatible = "ti,keystone_mdio", "ti,davinci_mdio";
- #address-cells = <1>;
- #size-cells = <0>;
- reg = <0x02090300 0x100>;
- status = "disabled";
- clocks = <&clkcpgmac>;
- clock-names = "fck";
- bus_freq = <2500000>;
- };
- /include/ "keystone-k2hk-netcp.dtsi"
- };
-};
diff --git a/arch/arm/dts/keystone-k2l-clocks.dtsi b/arch/arm/dts/keystone-k2l-clocks.dtsi
deleted file mode 100644
index fcfc2fb..0000000
--- a/arch/arm/dts/keystone-k2l-clocks.dtsi
+++ /dev/null
@@ -1,263 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0
-/*
- * Keystone 2 lamarr SoC clock nodes
- *
- * Copyright (C) 2013-2017 Texas Instruments Incorporated - https://www.ti.com/
- */
-
-clocks {
- armpllclk: armpllclk@2620370 {
- #clock-cells = <0>;
- compatible = "ti,keystone,pll-clock";
- clocks = <&refclksys>;
- clock-output-names = "arm-pll-clk";
- reg = <0x02620370 4>;
- reg-names = "control";
- };
-
- mainpllclk: mainpllclk@2310110 {
- #clock-cells = <0>;
- compatible = "ti,keystone,main-pll-clock";
- clocks = <&refclksys>;
- reg = <0x02620350 4>, <0x02310110 4>, <0x02310108 4>;
- reg-names = "control", "multiplier", "post-divider";
- };
-
- papllclk: papllclk@2620358 {
- #clock-cells = <0>;
- compatible = "ti,keystone,pll-clock";
- clocks = <&refclksys>;
- clock-output-names = "papllclk";
- reg = <0x02620358 4>;
- reg-names = "control";
- };
-
- ddr3apllclk: ddr3apllclk@2620360 {
- #clock-cells = <0>;
- compatible = "ti,keystone,pll-clock";
- clocks = <&refclksys>;
- clock-output-names = "ddr-3a-pll-clk";
- reg = <0x02620360 4>;
- reg-names = "control";
- };
-
- clkdfeiqnsys: clkdfeiqnsys@2350004 {
- #clock-cells = <0>;
- compatible = "ti,keystone,psc-clock";
- clocks = <&chipclk12>;
- clock-output-names = "dfe";
- reg-names = "control", "domain";
- reg = <0x02350004 0xb00>, <0x02350000 0x400>;
- domain-id = <0>;
- };
-
- clkpcie1: clkpcie1@235002c {
- #clock-cells = <0>;
- compatible = "ti,keystone,psc-clock";
- clocks = <&chipclk12>;
- clock-output-names = "pcie";
- reg = <0x0235002c 0xb00>, <0x02350000 0x400>;
- reg-names = "control", "domain";
- domain-id = <4>;
- };
-
- clkgem1: clkgem1@2350040 {
- #clock-cells = <0>;
- compatible = "ti,keystone,psc-clock";
- clocks = <&chipclk1>;
- clock-output-names = "gem1";
- reg = <0x02350040 0xb00>, <0x02350024 0x400>;
- reg-names = "control", "domain";
- domain-id = <9>;
- };
-
- clkgem2: clkgem2@2350044 {
- #clock-cells = <0>;
- compatible = "ti,keystone,psc-clock";
- clocks = <&chipclk1>;
- clock-output-names = "gem2";
- reg = <0x02350044 0xb00>, <0x02350028 0x400>;
- reg-names = "control", "domain";
- domain-id = <10>;
- };
-
- clkgem3: clkgem3@2350048 {
- #clock-cells = <0>;
- compatible = "ti,keystone,psc-clock";
- clocks = <&chipclk1>;
- clock-output-names = "gem3";
- reg = <0x02350048 0xb00>, <0x0235002c 0x400>;
- reg-names = "control", "domain";
- domain-id = <11>;
- };
-
- clktac: clktac@2350064 {
- #clock-cells = <0>;
- compatible = "ti,keystone,psc-clock";
- clocks = <&chipclk13>;
- clock-output-names = "tac";
- reg = <0x02350064 0xb00>, <0x02350044 0x400>;
- reg-names = "control", "domain";
- domain-id = <17>;
- };
-
- clkrac: clkrac@2350068 {
- #clock-cells = <0>;
- compatible = "ti,keystone,psc-clock";
- clocks = <&chipclk13>;
- clock-output-names = "rac";
- reg = <0x02350068 0xb00>, <0x02350044 0x400>;
- reg-names = "control", "domain";
- domain-id = <17>;
- };
-
- clkdfepd0: clkdfepd0@235006c {
- #clock-cells = <0>;
- compatible = "ti,keystone,psc-clock";
- clocks = <&chipclk13>;
- clock-output-names = "dfe-pd0";
- reg = <0x0235006c 0xb00>, <0x02350044 0x400>;
- reg-names = "control", "domain";
- domain-id = <18>;
- };
-
- clkfftc0: clkfftc0@2350070 {
- #clock-cells = <0>;
- compatible = "ti,keystone,psc-clock";
- clocks = <&chipclk13>;
- clock-output-names = "fftc-0";
- reg = <0x02350070 0xb00>, <0x0235004c 0x400>;
- reg-names = "control", "domain";
- domain-id = <19>;
- };
-
- clkosr: clkosr@2350088 {
- #clock-cells = <0>;
- compatible = "ti,keystone,psc-clock";
- clocks = <&chipclk13>;
- clock-output-names = "osr";
- reg = <0x02350088 0xb00>, <0x0235004c 0x400>;
- reg-names = "control", "domain";
- domain-id = <21>;
- };
-
- clktcp3d0: clktcp3d0@235008c {
- #clock-cells = <0>;
- compatible = "ti,keystone,psc-clock";
- clocks = <&chipclk13>;
- clock-output-names = "tcp3d-0";
- reg = <0x0235008c 0xb00>, <0x02350058 0x400>;
- reg-names = "control", "domain";
- domain-id = <22>;
- };
-
- clktcp3d1: clktcp3d1@2350094 {
- #clock-cells = <0>;
- compatible = "ti,keystone,psc-clock";
- clocks = <&chipclk13>;
- clock-output-names = "tcp3d-1";
- reg = <0x02350094 0xb00>, <0x02350058 0x400>;
- reg-names = "control", "domain";
- domain-id = <23>;
- };
-
- clkvcp0: clkvcp0@235009c {
- #clock-cells = <0>;
- compatible = "ti,keystone,psc-clock";
- clocks = <&chipclk13>;
- clock-output-names = "vcp-0";
- reg = <0x0235009c 0xb00>, <0x02350060 0x400>;
- reg-names = "control", "domain";
- domain-id = <24>;
- };
-
- clkvcp1: clkvcp1@23500a0 {
- #clock-cells = <0>;
- compatible = "ti,keystone,psc-clock";
- clocks = <&chipclk13>;
- clock-output-names = "vcp-1";
- reg = <0x023500a0 0xb00>, <0x02350060 0x400>;
- reg-names = "control", "domain";
- domain-id = <24>;
- };
-
- clkvcp2: clkvcp2@23500a4 {
- #clock-cells = <0>;
- compatible = "ti,keystone,psc-clock";
- clocks = <&chipclk13>;
- clock-output-names = "vcp-2";
- reg = <0x023500a4 0xb00>, <0x02350060 0x400>;
- reg-names = "control", "domain";
- domain-id = <24>;
- };
-
- clkvcp3: clkvcp3@23500a8 {
- #clock-cells = <0>;
- compatible = "ti,keystone,psc-clock";
- clocks = <&chipclk13>;
- clock-output-names = "vcp-3";
- reg = <0x023500a8 0xb00>, <0x02350060 0x400>;
- reg-names = "control", "domain";
- domain-id = <24>;
- };
-
- clkbcp: clkbcp@23500bc {
- #clock-cells = <0>;
- compatible = "ti,keystone,psc-clock";
- clocks = <&chipclk13>;
- clock-output-names = "bcp";
- reg = <0x023500bc 0xb00>, <0x02350068 0x400>;
- reg-names = "control", "domain";
- domain-id = <26>;
- };
-
- clkdfepd1: clkdfepd1@23500c0 {
- #clock-cells = <0>;
- compatible = "ti,keystone,psc-clock";
- clocks = <&chipclk13>;
- clock-output-names = "dfe-pd1";
- reg = <0x023500c0 0xb00>, <0x02350044 0x400>;
- reg-names = "control", "domain";
- domain-id = <27>;
- };
-
- clkfftc1: clkfftc1@23500c4 {
- #clock-cells = <0>;
- compatible = "ti,keystone,psc-clock";
- clocks = <&chipclk13>;
- clock-output-names = "fftc-1";
- reg = <0x023500c4 0xb00>, <0x023504c0 0x400>;
- reg-names = "control", "domain";
- domain-id = <28>;
- };
-
- clkiqnail: clkiqnail@23500c8 {
- #clock-cells = <0>;
- compatible = "ti,keystone,psc-clock";
- clocks = <&chipclk13>;
- clock-output-names = "iqn-ail";
- reg = <0x023500c8 0xb00>, <0x0235004c 0x400>;
- reg-names = "control", "domain";
- domain-id = <29>;
- };
-
- clkuart2: clkuart2@2350000 {
- #clock-cells = <0>;
- compatible = "ti,keystone,psc-clock";
- clocks = <&clkmodrst0>;
- clock-output-names = "uart2";
- reg = <0x02350000 0xb00>, <0x02350000 0x400>;
- reg-names = "control", "domain";
- domain-id = <0>;
- };
-
- clkuart3: clkuart3@2350000 {
- #clock-cells = <0>;
- compatible = "ti,keystone,psc-clock";
- clocks = <&clkmodrst0>;
- clock-output-names = "uart3";
- reg = <0x02350000 0xb00>, <0x02350000 0x400>;
- reg-names = "control", "domain";
- domain-id = <0>;
- };
-};
diff --git a/arch/arm/dts/keystone-k2l-evm-u-boot.dtsi b/arch/arm/dts/keystone-k2l-evm-u-boot.dtsi
index f1aed14..d9dee80 100644
--- a/arch/arm/dts/keystone-k2l-evm-u-boot.dtsi
+++ b/arch/arm/dts/keystone-k2l-evm-u-boot.dtsi
@@ -3,16 +3,30 @@
* Copyright (C) 2019 Texas Instruments Incorporated - https://www.ti.com/
*/
+/{
+ aliases {
+ i2c0 = &i2c0;
+ i2c1 = &i2c1;
+ i2c2 = &i2c2;
+ };
+
+ chosen {
+ stdout-path = &uart0;
+ };
+};
+
+&soc0 {
+ bootph-all;
+};
+
&usb_phy {
#phy-cells = <0>;
psc-domain = <2>;
};
-&usb {
- dwc3@2690000 {
- phys = <&usb_phy>;
- dr_mode = "host";
- snps,u2ss_inp3_quirk;
- status = "okay";
- };
+&usb0 {
+ phys = <&usb_phy>;
+ dr_mode = "host";
+ snps,u2ss_inp3_quirk;
+ status = "okay";
};
diff --git a/arch/arm/dts/keystone-k2l-evm.dts b/arch/arm/dts/keystone-k2l-evm.dts
deleted file mode 100644
index 9d2b454..0000000
--- a/arch/arm/dts/keystone-k2l-evm.dts
+++ /dev/null
@@ -1,129 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0
-/*
- * Keystone 2 Lamarr EVM device tree
- *
- * Copyright (C) 2014-2017 Texas Instruments Incorporated - https://www.ti.com/
- */
-/dts-v1/;
-
-#include "keystone.dtsi"
-#include "keystone-k2l.dtsi"
-
-/ {
- compatible = "ti,k2l-evm","ti,keystone";
- model = "Texas Instruments Keystone 2 Lamarr EVM";
-
- soc {
- clocks {
- refclksys: refclksys {
- #clock-cells = <0>;
- compatible = "fixed-clock";
- clock-frequency = <122880000>;
- clock-output-names = "refclk-sys";
- };
- };
- };
-};
-
-&usb_phy {
- status = "okay";
-};
-
-&usb {
- status = "okay";
-};
-
-&i2c0 {
- dtt@50 {
- compatible = "at,24c1024";
- reg = <0x50>;
- };
-};
-
-&aemif {
- cs0 {
- #address-cells = <2>;
- #size-cells = <1>;
- clock-ranges;
- ranges;
-
- ti,cs-chipselect = <0>;
- /* all timings in nanoseconds */
- ti,cs-min-turnaround-ns = <12>;
- ti,cs-read-hold-ns = <6>;
- ti,cs-read-strobe-ns = <23>;
- ti,cs-read-setup-ns = <9>;
- ti,cs-write-hold-ns = <8>;
- ti,cs-write-strobe-ns = <23>;
- ti,cs-write-setup-ns = <8>;
-
- nand@0,0 {
- compatible = "ti,keystone-nand","ti,davinci-nand";
- #address-cells = <1>;
- #size-cells = <1>;
- reg = <0 0 0x4000000
- 1 0 0x0000100>;
-
- ti,davinci-chipselect = <0>;
- ti,davinci-mask-ale = <0x2000>;
- ti,davinci-mask-cle = <0x4000>;
- ti,davinci-mask-chipsel = <0>;
- nand-ecc-mode = "hw";
- ti,davinci-ecc-bits = <4>;
- nand-on-flash-bbt;
-
- partition@0 {
- label = "u-boot";
- reg = <0x0 0x100000>;
- read-only;
- };
-
- partition@100000 {
- label = "params";
- reg = <0x100000 0x80000>;
- read-only;
- };
-
- partition@180000 {
- label = "ubifs";
- reg = <0x180000 0x7FE80000>;
- };
- };
- };
-};
-
-&spi0 {
- status ="okay";
- nor_flash: flash@0 {
- #address-cells = <1>;
- #size-cells = <1>;
- compatible = "Micron,n25q128a11", "jedec,spi-nor";
- spi-max-frequency = <54000000>;
- m25p,fast-read;
- reg = <0>;
-
- partition@0 {
- label = "u-boot-spl";
- reg = <0x0 0x80000>;
- read-only;
- };
-
- partition@1 {
- label = "misc";
- reg = <0x80000 0xf80000>;
- };
- };
-};
-
-&mdio {
- status = "okay";
- ethphy0: ethernet-phy@0 {
- compatible = "marvell,88E1514", "marvell,88E1510", "ethernet-phy-ieee802.3-c22";
- reg = <0>;
- };
-
- ethphy1: ethernet-phy@1 {
- compatible = "marvell,88E1514", "marvell,88E1510", "ethernet-phy-ieee802.3-c22";
- reg = <1>;
- };
-};
diff --git a/arch/arm/dts/keystone-k2l-netcp.dtsi b/arch/arm/dts/keystone-k2l-netcp.dtsi
deleted file mode 100644
index 2caa058..0000000
--- a/arch/arm/dts/keystone-k2l-netcp.dtsi
+++ /dev/null
@@ -1,187 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0
-/*
- * Device Tree Source for Keystone 2 Lamarr Netcp driver
- *
- * Copyright (C) 2015-2017 Texas Instruments Incorporated - https://www.ti.com/
- */
-
-qmss: qmss@2a40000 {
- compatible = "ti,keystone-navigator-qmss";
- dma-coherent;
- #address-cells = <1>;
- #size-cells = <1>;
- clocks = <&chipclk13>;
- ranges;
- queue-range = <0 0x2000>;
- linkram0 = <0x100000 0x4000>;
- linkram1 = <0x70000000 0x10000>; /* 1MB OSR mem */
-
- qmgrs {
- #address-cells = <1>;
- #size-cells = <1>;
- ranges;
- qmgr0 {
- managed-queues = <0 0x2000>;
- reg = <0x2a40000 0x20000>,
- <0x2a06000 0x400>,
- <0x2a02000 0x1000>,
- <0x2a03000 0x1000>,
- <0x23a80000 0x20000>,
- <0x2a80000 0x20000>;
- reg-names = "peek", "status", "config",
- "region", "push", "pop";
- };
- };
- queue-pools {
- qpend {
- qpend-0 {
- qrange = <658 8>;
- interrupts =<0 40 0xf04 0 41 0xf04 0 42 0xf04
- 0 43 0xf04 0 44 0xf04 0 45 0xf04
- 0 46 0xf04 0 47 0xf04>;
- };
- qpend-1 {
- qrange = <528 16>;
- interrupts = <0 48 0xf04 0 49 0xf04 0 50 0xf04
- 0 51 0xf04 0 52 0xf04 0 53 0xf04
- 0 54 0xf04 0 55 0xf04 0 56 0xf04
- 0 57 0xf04 0 58 0xf04 0 59 0xf04
- 0 60 0xf04 0 61 0xf04 0 62 0xf04
- 0 63 0xf04>;
- qalloc-by-id;
- };
- qpend-2 {
- qrange = <544 16>;
- interrupts = <0 64 0xf04 0 65 0xf04 0 66 0xf04
- 0 59 0xf04 0 68 0xf04 0 69 0xf04
- 0 70 0xf04 0 71 0xf04 0 72 0xf04
- 0 73 0xf04 0 74 0xf04 0 75 0xf04
- 0 76 0xf04 0 77 0xf04 0 78 0xf04
- 0 79 0xf04>;
- };
- };
- general-purpose {
- gp-0 {
- qrange = <4000 64>;
- };
- netcp-tx {
- qrange = <896 128>;
- qalloc-by-id;
- };
- };
- };
-
- descriptor-regions {
- #address-cells = <1>;
- #size-cells = <1>;
- ranges;
- region-12 {
- id = <12>;
- region-spec = <8192 128>; /* num_desc desc_size */
- link-index = <0x4000>;
- };
- };
-}; /* qmss */
-
-knav_dmas: knav_dmas@0 {
- compatible = "ti,keystone-navigator-dma";
- clocks = <&papllclk>;
- #address-cells = <1>;
- #size-cells = <1>;
- ranges;
- ti,navigator-cloud-address = <0x23a80000 0x23a90000>;
-
- dma_gbe: dma_gbe@0 {
- reg = <0x26186000 0x100>,
- <0x26187000 0x2a0>,
- <0x26188000 0xb60>,
- <0x26186100 0x80>,
- <0x26189000 0x1000>;
- reg-names = "global", "txchan", "rxchan",
- "txsched", "rxflow";
- };
-};
-
-netcp: netcp@26000000 {
- reg = <0x2620110 0x8>;
- reg-names = "efuse";
- compatible = "ti,netcp-1.0";
- #address-cells = <1>;
- #size-cells = <1>;
-
- /* NetCP address range */
- ranges = <0 0x26000000 0x1000000>;
-
- clocks = <&papllclk>, <&clkcpgmac>, <&chipclk12>;
- dma-coherent;
-
- ti,navigator-dmas = <&dma_gbe 0>,
- <&dma_gbe 8>,
- <&dma_gbe 0>;
- ti,navigator-dma-names = "netrx0", "netrx1", "nettx";
-
- netcp-devices {
- #address-cells = <1>;
- #size-cells = <1>;
- ranges;
- gbe@200000 { /* ETHSS */
- label = "netcp-gbe";
- compatible = "ti,netcp-gbe-5";
- reg = <0x200000 0x900>, <0x220000 0x20000>;
- /* enable-ale; */
- tx-queue = <896>;
- tx-channel = "nettx";
-
- interfaces {
- gbe0: interface-0 {
- slave-port = <0>;
- link-interface = <1>;
- phy-handle = <ðphy0>;
- };
- gbe1: interface-1 {
- slave-port = <1>;
- link-interface = <1>;
- phy-handle = <ðphy1>;
- };
- };
-
- secondary-slave-ports {
- port-2 {
- slave-port = <2>;
- link-interface = <2>;
- };
- port-3 {
- slave-port = <3>;
- link-interface = <2>;
- };
- };
- };
- };
-
- netcp-interfaces {
- interface-0 {
- rx-channel = "netrx0";
- rx-pool = <1024 12>;
- tx-pool = <1024 12>;
- rx-queue-depth = <128 128 0 0>;
- rx-buffer-size = <1518 4096 0 0>;
- rx-queue = <528>;
- tx-completion-queue = <530>;
- efuse-mac = <1>;
- netcp-gbe = <&gbe0>;
-
- };
- interface-1 {
- rx-channel = "netrx1";
- rx-pool = <1024 12>;
- tx-pool = <1024 12>;
- rx-queue-depth = <128 128 0 0>;
- rx-buffer-size = <1518 4096 0 0>;
- rx-queue = <529>;
- tx-completion-queue = <531>;
- efuse-mac = <0>;
- local-mac-address = [02 18 31 7e 3e 7f];
- netcp-gbe = <&gbe1>;
- };
- };
-};
diff --git a/arch/arm/dts/keystone-k2l.dtsi b/arch/arm/dts/keystone-k2l.dtsi
deleted file mode 100644
index c8893e2..0000000
--- a/arch/arm/dts/keystone-k2l.dtsi
+++ /dev/null
@@ -1,105 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0
-/*
- * Keystone 2 Lamarr SoC specific device tree
- *
- * Copyright (C) 2014-2017 Texas Instruments Incorporated - https://www.ti.com/
- */
-
-/ {
- cpus {
- #address-cells = <1>;
- #size-cells = <0>;
-
- interrupt-parent = <&gic>;
-
- cpu@0 {
- compatible = "arm,cortex-a15";
- device_type = "cpu";
- reg = <0>;
- };
-
- cpu@1 {
- compatible = "arm,cortex-a15";
- device_type = "cpu";
- reg = <1>;
- };
- };
-
- soc {
- /include/ "keystone-k2l-clocks.dtsi"
-
- uart2: serial@2348400 {
- compatible = "ns16550a";
- current-speed = <115200>;
- reg-shift = <2>;
- reg-io-width = <4>;
- reg = <0x02348400 0x100>;
- clocks = <&clkuart2>;
- interrupts = <GIC_SPI 432 IRQ_TYPE_EDGE_RISING>;
- };
-
- uart3: serial@2348800 {
- compatible = "ns16550a";
- current-speed = <115200>;
- reg-shift = <2>;
- reg-io-width = <4>;
- reg = <0x02348800 0x100>;
- clocks = <&clkuart3>;
- interrupts = <GIC_SPI 435 IRQ_TYPE_EDGE_RISING>;
- };
-
- dspgpio0: keystone_dsp_gpio@02620240 {
- compatible = "ti,keystone-dsp-gpio";
- gpio-controller;
- #gpio-cells = <2>;
- gpio,syscon-dev = <&devctrl 0x240>;
- };
-
- dspgpio1: keystone_dsp_gpio@2620244 {
- compatible = "ti,keystone-dsp-gpio";
- gpio-controller;
- #gpio-cells = <2>;
- gpio,syscon-dev = <&devctrl 0x244>;
- };
-
- dspgpio2: keystone_dsp_gpio@2620248 {
- compatible = "ti,keystone-dsp-gpio";
- gpio-controller;
- #gpio-cells = <2>;
- gpio,syscon-dev = <&devctrl 0x248>;
- };
-
- dspgpio3: keystone_dsp_gpio@262024c {
- compatible = "ti,keystone-dsp-gpio";
- gpio-controller;
- #gpio-cells = <2>;
- gpio,syscon-dev = <&devctrl 0x24c>;
- };
-
- mdio: mdio@26200f00 {
- compatible = "ti,keystone_mdio", "ti,davinci_mdio";
- #address-cells = <1>;
- #size-cells = <0>;
- reg = <0x26200f00 0x100>;
- status = "disabled";
- clocks = <&clkcpgmac>;
- clock-names = "fck";
- bus_freq = <2500000>;
- };
- /include/ "keystone-k2l-netcp.dtsi"
- };
-};
-
-&spi0 {
- ti,davinci-spi-num-cs = <5>;
-};
-
-&spi1 {
- ti,davinci-spi-num-cs = <3>;
-};
-
-&spi2 {
- ti,davinci-spi-num-cs = <5>;
- /* Pin muxed. Enabled and configured by Bootloader */
- status = "disabled";
-};
diff --git a/arch/arm/dts/keystone.dtsi b/arch/arm/dts/keystone.dtsi
deleted file mode 100644
index 1538cce..0000000
--- a/arch/arm/dts/keystone.dtsi
+++ /dev/null
@@ -1,330 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0
-/*
- * Copyright (C) 2013-2017 Texas Instruments Incorporated - https://www.ti.com/
- */
-
-#include <dt-bindings/interrupt-controller/arm-gic.h>
-#include <dt-bindings/gpio/gpio.h>
-
-#include "skeleton.dtsi"
-
-/ {
- model = "Texas Instruments Keystone 2 SoC";
- #address-cells = <1>;
- #size-cells = <1>;
- interrupt-parent = <&gic>;
-
- aliases {
- serial0 = &uart0;
- spi0 = &spi0;
- spi1 = &spi1;
- spi2 = &spi2;
- i2c0 = &i2c0;
- i2c1 = &i2c1;
- i2c2 = &i2c2;
- };
-
- chosen {
- stdout-path = &uart0;
- };
-
- memory {
- reg = <0x80000000 0x40000000>;
- };
-
- gic: interrupt-controller {
- compatible = "arm,cortex-a15-gic";
- #interrupt-cells = <3>;
- interrupt-controller;
- reg = <0x02561000 0x1000>,
- <0x02562000 0x2000>,
- <0x02564000 0x1000>,
- <0x02566000 0x2000>;
- interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) |
- IRQ_TYPE_LEVEL_HIGH)>;
- };
-
- timer {
- compatible = "arm,armv7-timer";
- interrupts =
- <GIC_PPI 13
- (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
- <GIC_PPI 14
- (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
- <GIC_PPI 11
- (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
- <GIC_PPI 10
- (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
- };
-
- pmu {
- compatible = "arm,cortex-a15-pmu";
- interrupts = <GIC_SPI 20 IRQ_TYPE_EDGE_RISING>,
- <GIC_SPI 21 IRQ_TYPE_EDGE_RISING>,
- <GIC_SPI 22 IRQ_TYPE_EDGE_RISING>,
- <GIC_SPI 23 IRQ_TYPE_EDGE_RISING>;
- };
-
- soc {
- #address-cells = <1>;
- #size-cells = <1>;
- compatible = "ti,keystone","simple-bus";
- interrupt-parent = <&gic>;
- ranges;
-
- pllctrl: pll-controller@02310000 {
- compatible = "ti,keystone-pllctrl", "syscon";
- reg = <0x02310000 0x200>;
- };
-
- devctrl: device-state-control@02620000 {
- compatible = "ti,keystone-devctrl", "syscon";
- reg = <0x02620000 0x1000>;
- };
-
- rstctrl: reset-controller {
- compatible = "ti,keystone-reset";
- ti,syscon-pll = <&pllctrl 0xe4>;
- ti,syscon-dev = <&devctrl 0x328>;
- ti,wdt-list = <0>;
- };
-
- /include/ "keystone-clocks.dtsi"
-
- uart0: serial@2530c00 {
- compatible = "ns16550a";
- current-speed = <115200>;
- reg-shift = <2>;
- reg-io-width = <4>;
- reg = <0x02530c00 0x100>;
- clocks = <&clkuart0>;
- interrupts = <GIC_SPI 277 IRQ_TYPE_EDGE_RISING>;
- };
-
- uart1: serial@2531000 {
- compatible = "ns16550a";
- current-speed = <115200>;
- reg-shift = <2>;
- reg-io-width = <4>;
- reg = <0x02531000 0x100>;
- clocks = <&clkuart1>;
- interrupts = <GIC_SPI 280 IRQ_TYPE_EDGE_RISING>;
- };
-
- i2c0: i2c@2530000 {
- compatible = "ti,davinci-i2c";
- reg = <0x02530000 0x400>;
- clock-frequency = <100000>;
- clocks = <&clki2c>;
- interrupts = <GIC_SPI 283 IRQ_TYPE_EDGE_RISING>;
- #address-cells = <1>;
- #size-cells = <0>;
- };
-
- i2c1: i2c@2530400 {
- compatible = "ti,davinci-i2c";
- reg = <0x02530400 0x400>;
- clock-frequency = <100000>;
- clocks = <&clki2c>;
- interrupts = <GIC_SPI 286 IRQ_TYPE_EDGE_RISING>;
- #address-cells = <1>;
- #size-cells = <0>;
- };
-
- i2c2: i2c@2530800 {
- compatible = "ti,davinci-i2c";
- reg = <0x02530800 0x400>;
- clock-frequency = <100000>;
- clocks = <&clki2c>;
- interrupts = <GIC_SPI 289 IRQ_TYPE_EDGE_RISING>;
- #address-cells = <1>;
- #size-cells = <0>;
- };
-
- spi0: spi@21000400 {
- compatible = "ti,dm6441-spi";
- reg = <0x21000400 0x200>;
- num-cs = <4>;
- ti,davinci-spi-intr-line = <0>;
- interrupts = <GIC_SPI 292 IRQ_TYPE_EDGE_RISING>;
- clocks = <&clkspi>;
- #address-cells = <1>;
- #size-cells = <0>;
- };
-
- spi1: spi@21000600 {
- compatible = "ti,dm6441-spi";
- reg = <0x21000600 0x200>;
- num-cs = <4>;
- ti,davinci-spi-intr-line = <0>;
- interrupts = <GIC_SPI 296 IRQ_TYPE_EDGE_RISING>;
- clocks = <&clkspi>;
- #address-cells = <1>;
- #size-cells = <0>;
- };
-
- spi2: spi@21000800 {
- compatible = "ti,dm6441-spi";
- reg = <0x21000800 0x200>;
- num-cs = <4>;
- ti,davinci-spi-intr-line = <0>;
- interrupts = <GIC_SPI 300 IRQ_TYPE_EDGE_RISING>;
- clocks = <&clkspi>;
- #address-cells = <1>;
- #size-cells = <0>;
- };
-
- usb_phy: usb_phy@2620738 {
- compatible = "ti,keystone-usbphy";
- #address-cells = <1>;
- #size-cells = <1>;
- reg = <0x2620738 24>;
- status = "disabled";
- };
-
- usb: usb@2680000 {
- compatible = "ti,keystone-dwc3";
- #address-cells = <1>;
- #size-cells = <1>;
- reg = <0x2680000 0x10000>;
- clocks = <&clkusb>;
- clock-names = "usb";
- interrupts = <GIC_SPI 393 IRQ_TYPE_EDGE_RISING>;
- ranges;
- dma-coherent;
- dma-ranges;
- status = "disabled";
-
- usb@2690000 {
- compatible = "synopsys,dwc3";
- reg = <0x2690000 0x70000>;
- interrupts = <GIC_SPI 393 IRQ_TYPE_EDGE_RISING>;
- usb-phy = <&usb_phy>, <&usb_phy>;
- };
- };
-
- wdt: wdt@22f0080 {
- compatible = "ti,keystone-wdt","ti,davinci-wdt";
- reg = <0x022f0080 0x80>;
- clocks = <&clkwdtimer0>;
- };
-
- clock_event: timer@22f0000 {
- compatible = "ti,keystone-timer";
- reg = <0x022f0000 0x80>;
- interrupts = <GIC_SPI 110 IRQ_TYPE_EDGE_RISING>;
- clocks = <&clktimer15>;
- };
-
- gpio0: gpio@260bf00 {
- compatible = "ti,keystone-gpio";
- reg = <0x0260bf00 0x100>;
- gpio-controller;
- #gpio-cells = <2>;
- /* HW Interrupts mapped to GPIO pins */
- interrupts = <GIC_SPI 120 IRQ_TYPE_EDGE_RISING>,
- <GIC_SPI 121 IRQ_TYPE_EDGE_RISING>,
- <GIC_SPI 122 IRQ_TYPE_EDGE_RISING>,
- <GIC_SPI 123 IRQ_TYPE_EDGE_RISING>,
- <GIC_SPI 124 IRQ_TYPE_EDGE_RISING>,
- <GIC_SPI 125 IRQ_TYPE_EDGE_RISING>,
- <GIC_SPI 126 IRQ_TYPE_EDGE_RISING>,
- <GIC_SPI 127 IRQ_TYPE_EDGE_RISING>,
- <GIC_SPI 128 IRQ_TYPE_EDGE_RISING>,
- <GIC_SPI 129 IRQ_TYPE_EDGE_RISING>,
- <GIC_SPI 130 IRQ_TYPE_EDGE_RISING>,
- <GIC_SPI 131 IRQ_TYPE_EDGE_RISING>,
- <GIC_SPI 132 IRQ_TYPE_EDGE_RISING>,
- <GIC_SPI 133 IRQ_TYPE_EDGE_RISING>,
- <GIC_SPI 134 IRQ_TYPE_EDGE_RISING>,
- <GIC_SPI 135 IRQ_TYPE_EDGE_RISING>,
- <GIC_SPI 136 IRQ_TYPE_EDGE_RISING>,
- <GIC_SPI 137 IRQ_TYPE_EDGE_RISING>,
- <GIC_SPI 138 IRQ_TYPE_EDGE_RISING>,
- <GIC_SPI 139 IRQ_TYPE_EDGE_RISING>,
- <GIC_SPI 140 IRQ_TYPE_EDGE_RISING>,
- <GIC_SPI 141 IRQ_TYPE_EDGE_RISING>,
- <GIC_SPI 142 IRQ_TYPE_EDGE_RISING>,
- <GIC_SPI 143 IRQ_TYPE_EDGE_RISING>,
- <GIC_SPI 144 IRQ_TYPE_EDGE_RISING>,
- <GIC_SPI 145 IRQ_TYPE_EDGE_RISING>,
- <GIC_SPI 146 IRQ_TYPE_EDGE_RISING>,
- <GIC_SPI 147 IRQ_TYPE_EDGE_RISING>,
- <GIC_SPI 148 IRQ_TYPE_EDGE_RISING>,
- <GIC_SPI 149 IRQ_TYPE_EDGE_RISING>,
- <GIC_SPI 150 IRQ_TYPE_EDGE_RISING>,
- <GIC_SPI 151 IRQ_TYPE_EDGE_RISING>;
- clocks = <&clkgpio>;
- clock-names = "gpio";
- ti,ngpio = <32>;
- ti,davinci-gpio-unbanked = <32>;
- };
-
- aemif: aemif@21000A00 {
- compatible = "ti,keystone-aemif", "ti,davinci-aemif";
- #address-cells = <2>;
- #size-cells = <1>;
- clocks = <&clkaemif>;
- clock-names = "aemif";
- clock-ranges;
-
- reg = <0x21000A00 0x00000100>;
- ranges = <0 0 0x30000000 0x10000000
- 1 0 0x21000A00 0x00000100>;
- };
-
- kirq0: keystone_irq@26202a0 {
- compatible = "ti,keystone-irq";
- interrupts = <GIC_SPI 4 IRQ_TYPE_EDGE_RISING>;
- interrupt-controller;
- #interrupt-cells = <1>;
- ti,syscon-dev = <&devctrl 0x2a0>;
- };
-
- pcie0: pcie@21800000 {
- compatible = "ti,keystone-pcie", "snps,dw-pcie";
- clocks = <&clkpcie>;
- clock-names = "pcie";
- #address-cells = <3>;
- #size-cells = <2>;
- reg = <0x21801000 0x2000>, <0x21800000 0x1000>, <0x02620128 4>;
- ranges = <0x81000000 0 0 0x23250000 0 0x4000
- 0x82000000 0 0x50000000 0x50000000 0 0x10000000>;
-
- status = "disabled";
- device_type = "pci";
- num-lanes = <2>;
-
- #interrupt-cells = <1>;
- interrupt-map-mask = <0 0 0 7>;
- interrupt-map = <0 0 0 1 &pcie_intc0 0>, /* INT A */
- <0 0 0 2 &pcie_intc0 1>, /* INT B */
- <0 0 0 3 &pcie_intc0 2>, /* INT C */
- <0 0 0 4 &pcie_intc0 3>; /* INT D */
-
- pcie_msi_intc0: msi-interrupt-controller {
- interrupt-controller;
- #interrupt-cells = <1>;
- interrupt-parent = <&gic>;
- interrupts = <GIC_SPI 30 IRQ_TYPE_EDGE_RISING>,
- <GIC_SPI 31 IRQ_TYPE_EDGE_RISING>,
- <GIC_SPI 32 IRQ_TYPE_EDGE_RISING>,
- <GIC_SPI 33 IRQ_TYPE_EDGE_RISING>,
- <GIC_SPI 34 IRQ_TYPE_EDGE_RISING>,
- <GIC_SPI 35 IRQ_TYPE_EDGE_RISING>,
- <GIC_SPI 36 IRQ_TYPE_EDGE_RISING>,
- <GIC_SPI 37 IRQ_TYPE_EDGE_RISING>;
- };
-
- pcie_intc0: legacy-interrupt-controller {
- interrupt-controller;
- #interrupt-cells = <1>;
- interrupt-parent = <&gic>;
- interrupts = <GIC_SPI 26 IRQ_TYPE_EDGE_RISING>,
- <GIC_SPI 27 IRQ_TYPE_EDGE_RISING>,
- <GIC_SPI 28 IRQ_TYPE_EDGE_RISING>,
- <GIC_SPI 29 IRQ_TYPE_EDGE_RISING>;
- };
- };
- };
-};
diff --git a/arch/arm/dts/mt7981.dtsi b/arch/arm/dts/mt7981.dtsi
index 7aaa777..a9991a1 100644
--- a/arch/arm/dts/mt7981.dtsi
+++ b/arch/arm/dts/mt7981.dtsi
@@ -98,14 +98,6 @@
bootph-all;
};
- infracfg_ao: infracfg_ao@10001000 {
- compatible = "mediatek,mt7981-infracfg_ao";
- reg = <0x10001000 0x80>;
- clock-parent = <&infracfg>;
- #clock-cells = <1>;
- bootph-all;
- };
-
infracfg: infracfg@10001000 {
compatible = "mediatek,mt7981-infracfg";
reg = <0x10001000 0x30>;
@@ -140,14 +132,13 @@
#clock-cells = <1>;
#pwm-cells = <2>;
interrupts = <GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&infracfg CK_INFRA_PWM>,
- <&infracfg_ao CK_INFRA_PWM_BSEL>,
- <&infracfg_ao CK_INFRA_PWM1_CK>,
- <&infracfg_ao CK_INFRA_PWM2_CK>,
- /* FIXME */
- <&infracfg_ao CK_INFRA_PWM2_CK>;
- assigned-clocks = <&topckgen CK_TOP_PWM_SEL>;
- assigned-clock-parents = <&topckgen CK_TOP_CB_CKSQ_40M>;
+ clocks = <&topckgen CLK_TOP_PWM_SEL>,
+ <&infracfg CLK_INFRA_PWM_BSEL>,
+ <&infracfg CLK_INFRA_PWM1_CK>,
+ <&infracfg CLK_INFRA_PWM2_CK>,
+ <&infracfg CLK_INFRA_PWM3_CK>;
+ assigned-clocks = <&topckgen CLK_TOP_PWM_SEL>;
+ assigned-clock-parents = <&topckgen CLK_TOP_CB_CKSQ_40M>;
clock-names = "top", "main", "pwm1", "pwm2", "pwm3";
status = "disabled";
};
@@ -158,8 +149,8 @@
<0x10217080 0x80>;
interrupts = <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>;
clock-div = <1>;
- clocks = <&infracfg_ao CK_INFRA_I2CO_CK>,
- <&infracfg_ao CK_INFRA_AP_DMA_CK>;
+ clocks = <&infracfg CLK_INFRA_I2C0_CK>,
+ <&infracfg CLK_INFRA_AP_DMA_CK>;
clock-names = "main", "dma";
#address-cells = <1>;
#size-cells = <0>;
@@ -170,11 +161,11 @@
compatible = "mediatek,hsuart";
reg = <0x11002000 0x400>;
interrupts = <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&infracfg_ao CK_INFRA_UART0_CK>;
- assigned-clocks = <&topckgen CK_TOP_UART_SEL>,
- <&infracfg_ao CK_INFRA_UART0_SEL>;
- assigned-clock-parents = <&topckgen CK_TOP_CB_CKSQ_40M>,
- <&infracfg CK_INFRA_UART>;
+ clocks = <&infracfg CLK_INFRA_UART0_CK>;
+ assigned-clocks = <&topckgen CLK_TOP_UART_SEL>,
+ <&infracfg CLK_INFRA_UART0_SEL>;
+ assigned-clock-parents = <&topckgen CLK_TOP_CB_CKSQ_40M>,
+ <&topckgen CLK_TOP_UART_SEL>;
mediatek,force-highspeed;
status = "disabled";
bootph-all;
@@ -184,11 +175,11 @@
compatible = "mediatek,hsuart";
reg = <0x11003000 0x400>;
interrupts = <GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&infracfg_ao CK_INFRA_UART1_CK>;
- assigned-clocks = <&topckgen CK_TOP_UART_SEL>,
- <&infracfg_ao CK_INFRA_UART1_SEL>;
- assigned-clock-parents = <&topckgen CK_TOP_CB_CKSQ_40M>,
- <&infracfg CK_INFRA_UART>;
+ clocks = <&infracfg CLK_INFRA_UART1_CK>;
+ assigned-clocks = <&topckgen CLK_TOP_UART_SEL>,
+ <&infracfg CLK_INFRA_UART1_SEL>;
+ assigned-clock-parents = <&topckgen CLK_TOP_CB_CKSQ_40M>,
+ <&topckgen CLK_TOP_UART_SEL>;
mediatek,force-highspeed;
status = "disabled";
};
@@ -197,11 +188,11 @@
compatible = "mediatek,hsuart";
reg = <0x11004000 0x400>;
interrupts = <GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&infracfg_ao CK_INFRA_UART2_CK>;
- assigned-clocks = <&topckgen CK_TOP_UART_SEL>,
- <&infracfg_ao CK_INFRA_UART2_SEL>;
- assigned-clock-parents = <&topckgen CK_TOP_CB_CKSQ_40M>,
- <&infracfg CK_INFRA_UART>;
+ clocks = <&infracfg CLK_INFRA_UART2_CK>;
+ assigned-clocks = <&topckgen CLK_TOP_UART_SEL>,
+ <&infracfg CLK_INFRA_UART2_SEL>;
+ assigned-clock-parents = <&topckgen CLK_TOP_CB_CKSQ_40M>,
+ <&topckgen CLK_TOP_UART_SEL>;
mediatek,force-highspeed;
status = "disabled";
};
@@ -211,14 +202,14 @@
reg = <0x11005000 0x1000>,
<0x11006000 0x1000>;
reg-names = "nfi", "ecc";
- clocks = <&infracfg_ao CK_INFRA_SPINFI1_CK>,
- <&infracfg_ao CK_INFRA_NFI1_CK>,
- <&infracfg_ao CK_INFRA_NFI_HCK_CK>;
+ clocks = <&infracfg CLK_INFRA_SPINFI1_CK>,
+ <&infracfg CLK_INFRA_NFI1_CK>,
+ <&infracfg CLK_INFRA_NFI_HCK_CK>;
clock-names = "pad_clk", "nfi_clk", "nfi_hclk";
- assigned-clocks = <&topckgen CK_TOP_SPINFI_SEL>,
- <&topckgen CK_TOP_NFI1X_SEL>;
- assigned-clock-parents = <&topckgen CK_TOP_CB_M_D8>,
- <&topckgen CK_TOP_CB_M_D8>;
+ assigned-clocks = <&topckgen CLK_TOP_SPINFI_SEL>,
+ <&topckgen CLK_TOP_NFI1X_SEL>;
+ assigned-clock-parents = <&topckgen CLK_TOP_CB_M_D8>,
+ <&topckgen CLK_TOP_CB_M_D8>;
status = "disabled";
};
@@ -244,14 +235,14 @@
};
sgmiisys0: syscon@10060000 {
- compatible = "mediatek,mt7986-sgmiisys", "syscon";
+ compatible = "mediatek,mt7981-sgmiisys_0", "syscon";
reg = <0x10060000 0x1000>;
pn_swap;
#clock-cells = <1>;
};
sgmiisys1: syscon@10070000 {
- compatible = "mediatek,mt7986-sgmiisys", "syscon";
+ compatible = "mediatek,mt7981-sgmiisys_1", "syscon";
reg = <0x10070000 0x1000>;
#clock-cells = <1>;
};
@@ -265,13 +256,13 @@
spi0: spi@1100a000 {
compatible = "mediatek,ipm-spi";
reg = <0x1100a000 0x100>;
- clocks = <&infracfg_ao CK_INFRA_SPI0_CK>,
- <&topckgen CK_TOP_SPI_SEL>;
- assigned-clocks = <&topckgen CK_TOP_SPI_SEL>,
- <&infracfg CK_INFRA_SPI0_SEL>;
- assigned-clock-parents = <&topckgen CK_TOP_CB_M_D2>,
- <&topckgen CK_INFRA_ISPI0>;
- clock-names = "sel-clk", "spi-clk";
+ clocks = <&infracfg CLK_INFRA_SPI0_CK>,
+ <&topckgen CLK_TOP_SPI_SEL>;
+ assigned-clocks = <&topckgen CLK_TOP_SPI_SEL>,
+ <&infracfg CLK_INFRA_SPI0_SEL>;
+ assigned-clock-parents = <&topckgen CLK_TOP_CB_M_D2>,
+ <&topckgen CLK_TOP_SPI_SEL>;
+ clock-names = "spi-clk", "sel-clk";
interrupts = <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>;
status = "disabled";
};
@@ -280,19 +271,26 @@
compatible = "mediatek,ipm-spi";
reg = <0x1100b000 0x100>;
interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&infracfg CLK_INFRA_SPI1_CK>,
+ <&topckgen CLK_TOP_SPIM_MST_SEL>;
+ assigned-clocks = <&topckgen CLK_TOP_SPIM_MST_SEL>,
+ <&infracfg CLK_INFRA_SPI1_SEL>;
+ assigned-clock-parents = <&topckgen CLK_TOP_CB_M_D2>,
+ <&topckgen CLK_TOP_SPIM_MST_SEL>;
+ clock-names = "spi-clk", "sel-clk";
status = "disabled";
};
spi2: spi@11009000 {
compatible = "mediatek,ipm-spi";
reg = <0x11009000 0x100>;
- clocks = <&infracfg_ao CK_INFRA_SPI0_CK>,
- <&topckgen CK_TOP_SPI_SEL>;
- assigned-clocks = <&topckgen CK_TOP_SPI_SEL>,
- <&infracfg CK_INFRA_SPI0_SEL>;
- assigned-clock-parents = <&topckgen CK_TOP_CB_M_D2>,
- <&topckgen CK_INFRA_ISPI0>;
- clock-names = "sel-clk", "spi-clk";
+ clocks = <&infracfg CLK_INFRA_SPI2_CK>,
+ <&topckgen CLK_TOP_SPI_SEL>;
+ assigned-clocks = <&topckgen CLK_TOP_SPI_SEL>,
+ <&infracfg CLK_INFRA_SPI2_SEL>;
+ assigned-clock-parents = <&topckgen CLK_TOP_CB_M_D2>,
+ <&topckgen CLK_TOP_SPI_SEL>;
+ clock-names = "spi-clk", "sel-clk";
interrupts = <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>;
status = "disabled";
};
@@ -302,13 +300,13 @@
reg = <0x11230000 0x1000>,
<0x11C20000 0x1000>;
interrupts = <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&topckgen CK_TOP_EMMC_400M>,
- <&topckgen CK_TOP_EMMC_208M>,
- <&infracfg_ao CK_INFRA_MSDC_CK>;
- assigned-clocks = <&topckgen CK_TOP_EMMC_400M_SEL>,
- <&topckgen CK_TOP_EMMC_208M_SEL>;
- assigned-clock-parents = <&topckgen CK_TOP_CB_NET2_D2>,
- <&topckgen CK_TOP_CB_M_D2>;
+ clocks = <&topckgen CLK_TOP_EMMC_400M>,
+ <&topckgen CLK_TOP_EMMC_208M>,
+ <&infracfg CLK_INFRA_MSDC_CK>;
+ assigned-clocks = <&topckgen CLK_TOP_EMMC_400M_SEL>,
+ <&topckgen CLK_TOP_EMMC_208M_SEL>;
+ assigned-clock-parents = <&topckgen CLK_TOP_CB_NET2_D2>,
+ <&topckgen CLK_TOP_CB_M_D2>;
clock-names = "source", "hclk", "source_cg";
status = "disabled";
};
diff --git a/arch/arm/dts/mt7986.dtsi b/arch/arm/dts/mt7986.dtsi
index 30b5a89..f871f23 100644
--- a/arch/arm/dts/mt7986.dtsi
+++ b/arch/arm/dts/mt7986.dtsi
@@ -78,7 +78,7 @@
compatible = "mediatek,mt7986-timer";
reg = <0x10008000 0x1000>;
interrupts = <GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&infracfg CK_INFRA_CK_F26M>;
+ clocks = <&topckgen CLK_TOP_F26M_SEL>;
clock-names = "gpt-clk";
bootph-all;
};
@@ -115,13 +115,6 @@
#clock-cells = <1>;
};
- infracfg_ao: infracfg_ao@10001000 {
- compatible = "mediatek,mt7986-infracfg_ao";
- reg = <0x10001000 0x68>;
- clock-parent = <&infracfg>;
- #clock-cells = <1>;
- };
-
infracfg: infracfg@10001040 {
compatible = "mediatek,mt7986-infracfg";
reg = <0x10001000 0x1000>;
@@ -154,18 +147,18 @@
#clock-cells = <1>;
#pwm-cells = <2>;
interrupts = <GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&infracfg CK_INFRA_PWM>,
- <&infracfg_ao CK_INFRA_PWM_BSEL>,
- <&infracfg_ao CK_INFRA_PWM1_CK>,
- <&infracfg_ao CK_INFRA_PWM2_CK>;
- assigned-clocks = <&topckgen CK_TOP_PWM_SEL>,
- <&infracfg CK_INFRA_PWM_BSEL>,
- <&infracfg CK_INFRA_PWM1_SEL>,
- <&infracfg CK_INFRA_PWM2_SEL>;
- assigned-clock-parents = <&topckgen CK_TOP_CB_M_D4>,
- <&infracfg CK_INFRA_PWM>,
- <&infracfg CK_INFRA_PWM>,
- <&infracfg CK_INFRA_PWM>;
+ clocks = <&topckgen CLK_TOP_PWM_SEL>,
+ <&infracfg CLK_INFRA_PWM_BSEL>,
+ <&infracfg CLK_INFRA_PWM1_CK>,
+ <&infracfg CLK_INFRA_PWM2_CK>;
+ assigned-clocks = <&topckgen CLK_TOP_PWM_SEL>,
+ <&infracfg CLK_INFRA_PWM_BSEL>,
+ <&infracfg CLK_INFRA_PWM1_SEL>,
+ <&infracfg CLK_INFRA_PWM2_SEL>;
+ assigned-clock-parents = <&topckgen CLK_TOP_MPLL_D4>,
+ <&topckgen CLK_TOP_PWM_SEL>,
+ <&topckgen CLK_TOP_PWM_SEL>,
+ <&topckgen CLK_TOP_PWM_SEL>;
clock-names = "top", "main", "pwm1", "pwm2";
status = "disabled";
bootph-all;
@@ -175,11 +168,11 @@
compatible = "mediatek,hsuart";
reg = <0x11002000 0x400>;
interrupts = <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&infracfg_ao CK_INFRA_UART0_CK>;
- assigned-clocks = <&topckgen CK_TOP_UART_SEL>,
- <&infracfg_ao CK_INFRA_UART0_SEL>;
- assigned-clock-parents = <&topckgen CK_TOP_CB_CKSQ_40M>,
- <&infracfg CK_INFRA_UART>;
+ clocks = <&infracfg CLK_INFRA_UART0_CK>;
+ assigned-clocks = <&topckgen CLK_TOP_UART_SEL>,
+ <&infracfg CLK_INFRA_UART0_SEL>;
+ assigned-clock-parents = <&topckgen CLK_TOP_XTAL>,
+ <&topckgen CLK_TOP_UART_SEL>;
mediatek,force-highspeed;
status = "disabled";
bootph-all;
@@ -189,9 +182,9 @@
compatible = "mediatek,hsuart";
reg = <0x11003000 0x400>;
interrupts = <GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&infracfg_ao CK_INFRA_UART1_CK>;
- assigned-clocks = <&infracfg CK_INFRA_UART1_SEL>;
- assigned-clock-parents = <&infracfg CK_INFRA_CK_F26M>;
+ clocks = <&infracfg CLK_INFRA_UART1_CK>;
+ assigned-clocks = <&infracfg CLK_INFRA_UART1_SEL>;
+ assigned-clock-parents = <&topckgen CLK_TOP_F26M_SEL>;
mediatek,force-highspeed;
status = "disabled";
};
@@ -200,9 +193,9 @@
compatible = "mediatek,hsuart";
reg = <0x11004000 0x400>;
interrupts = <GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&infracfg_ao CK_INFRA_UART2_CK>;
- assigned-clocks = <&infracfg CK_INFRA_UART2_SEL>;
- assigned-clock-parents = <&infracfg CK_INFRA_CK_F26M>;
+ clocks = <&infracfg CLK_INFRA_UART2_CK>;
+ assigned-clocks = <&infracfg CLK_INFRA_UART2_SEL>;
+ assigned-clock-parents = <&topckgen CLK_TOP_F26M_SEL>;
mediatek,force-highspeed;
status = "disabled";
};
@@ -212,14 +205,14 @@
reg = <0x11005000 0x1000>,
<0x11006000 0x1000>;
reg-names = "nfi", "ecc";
- clocks = <&infracfg_ao CK_INFRA_SPINFI1_CK>,
- <&infracfg_ao CK_INFRA_NFI1_CK>,
- <&infracfg_ao CK_INFRA_NFI_HCK_CK>;
+ clocks = <&infracfg CLK_INFRA_SPINFI1_CK>,
+ <&infracfg CLK_INFRA_NFI1_CK>,
+ <&infracfg CLK_INFRA_NFI_HCK_CK>;
clock-names = "pad_clk", "nfi_clk", "nfi_hclk";
- assigned-clocks = <&topckgen CK_TOP_SPINFI_SEL>,
- <&topckgen CK_TOP_NFI1X_SEL>;
- assigned-clock-parents = <&topckgen CK_TOP_CB_M_D8>,
- <&topckgen CK_TOP_CB_M_D8>;
+ assigned-clocks = <&topckgen CLK_TOP_SPINFI_SEL>,
+ <&topckgen CLK_TOP_NFI1X_SEL>;
+ assigned-clock-parents = <&topckgen CLK_TOP_MPLL_D8>,
+ <&topckgen CLK_TOP_MPLL_D8>;
status = "disabled";
};
@@ -258,12 +251,12 @@
spi0: spi@1100a000 {
compatible = "mediatek,ipm-spi";
reg = <0x1100a000 0x100>;
- clocks = <&infracfg_ao CK_INFRA_SPI0_CK>,
- <&topckgen CK_TOP_SPI_SEL>;
- assigned-clocks = <&topckgen CK_TOP_SPI_SEL>,
- <&infracfg CK_INFRA_SPI0_SEL>;
- assigned-clock-parents = <&topckgen CK_TOP_CB_M_D2>,
- <&topckgen CK_INFRA_ISPI0>;
+ clocks = <&infracfg CLK_INFRA_SPI0_CK>,
+ <&topckgen CLK_TOP_SPI_SEL>;
+ assigned-clocks = <&topckgen CLK_TOP_SPI_SEL>,
+ <&infracfg CLK_INFRA_SPI0_SEL>;
+ assigned-clock-parents = <&topckgen CLK_TOP_MPLL_D2>,
+ <&topckgen CLK_TOP_SPI_SEL>;
clock-names = "sel-clk", "spi-clk";
interrupts = <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>;
status = "disabled";
@@ -281,13 +274,13 @@
reg = <0x11230000 0x1000>,
<0x11C20000 0x1000>;
interrupts = <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&topckgen CK_TOP_EMMC_416M>,
- <&topckgen CK_TOP_EMMC_250M>,
- <&infracfg_ao CK_INFRA_MSDC_CK>;
- assigned-clocks = <&topckgen CK_TOP_EMMC_416M_SEL>,
- <&topckgen CK_TOP_EMMC_250M_SEL>;
- assigned-clock-parents = <&topckgen CK_TOP_CB_M_416M>,
- <&topckgen CK_TOP_NET1_D5_D2>;
+ clocks = <&topckgen CLK_TOP_EMMC_416M_SEL>,
+ <&topckgen CLK_TOP_EMMC_250M_SEL>,
+ <&infracfg CLK_INFRA_MSDC_CK>;
+ assigned-clocks = <&topckgen CLK_TOP_EMMC_416M_SEL>,
+ <&topckgen CLK_TOP_EMMC_250M_SEL>;
+ assigned-clock-parents = <&fixed_plls CLK_APMIXED_MPLL>,
+ <&topckgen CLK_TOP_NET1PLL_D5_D2>;
clock-names = "source", "hclk", "source_cg";
status = "disabled";
};
diff --git a/arch/arm/dts/mt7988.dtsi b/arch/arm/dts/mt7988.dtsi
index 5c0c5bc..e120e50 100644
--- a/arch/arm/dts/mt7988.dtsi
+++ b/arch/arm/dts/mt7988.dtsi
@@ -97,13 +97,6 @@
interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
};
- infracfg_ao_cgs: infracfg_ao_cgs@10001000 {
- compatible = "mediatek,mt7988-infracfg_ao_cgs", "syscon";
- reg = <0 0x10001000 0 0x1000>;
- clock-parent = <&infracfg_ao>;
- #clock-cells = <1>;
- };
-
apmixedsys: apmixedsys@1001e000 {
compatible = "mediatek,mt7988-fixed-plls", "syscon";
reg = <0 0x1001e000 0 0x1000>;
@@ -251,7 +244,7 @@
#clock-cells = <1>;
};
- infracfg_ao: infracfg@10001000 {
+ infracfg: infracfg@10001000 {
compatible = "mediatek,mt7988-infracfg", "syscon";
reg = <0 0x10001000 0 0x1000>;
clock-parent = <&topckgen>;
@@ -262,11 +255,11 @@
compatible = "mediatek,hsuart";
reg = <0 0x11000000 0 0x100>;
interrupts = <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&infracfg_ao_cgs CK_INFRA_52M_UART0_CK>;
- assigned-clocks = <&topckgen CK_TOP_UART_SEL>,
- <&infracfg_ao CK_INFRA_MUX_UART0_SEL>;
- assigned-clock-parents = <&topckgen CK_TOP_CB_CKSQ_40M>,
- <&infracfg_ao CK_INFRA_UART_O0>;
+ clocks = <&infracfg CLK_INFRA_52M_UART0_CK>;
+ assigned-clocks = <&topckgen CLK_TOP_UART_SEL>,
+ <&infracfg CLK_INFRA_MUX_UART0_SEL>;
+ assigned-clock-parents = <&topckgen CLK_TOP_XTAL>,
+ <&topckgen CLK_TOP_UART_SEL>;
status = "disabled";
};
@@ -274,11 +267,11 @@
compatible = "mediatek,hsuart";
reg = <0 0x11000100 0 0x100>;
interrupts = <GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&infracfg_ao_cgs CK_INFRA_52M_UART1_CK>;
- assigned-clocks = <&topckgen CK_TOP_UART_SEL>,
- <&infracfg_ao CK_INFRA_MUX_UART1_SEL>;
- assigned-clock-parents = <&topckgen CK_TOP_CB_CKSQ_40M>,
- <&infracfg_ao CK_INFRA_UART_O1>;
+ clocks = <&infracfg CLK_INFRA_52M_UART1_CK>;
+ assigned-clocks = <&topckgen CLK_TOP_UART_SEL>,
+ <&infracfg CLK_INFRA_MUX_UART1_SEL>;
+ assigned-clock-parents = <&topckgen CLK_TOP_XTAL>,
+ <&topckgen CLK_TOP_UART_SEL>;
status = "disabled";
};
@@ -286,11 +279,11 @@
compatible = "mediatek,hsuart";
reg = <0 0x11000200 0 0x100>;
interrupts = <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&infracfg_ao_cgs CK_INFRA_52M_UART2_CK>;
- assigned-clocks = <&topckgen CK_TOP_UART_SEL>,
- <&infracfg_ao CK_INFRA_MUX_UART2_SEL>;
- assigned-clock-parents = <&topckgen CK_TOP_CB_CKSQ_40M>,
- <&infracfg_ao CK_INFRA_UART_O2>;
+ clocks = <&infracfg CLK_INFRA_52M_UART2_CK>;
+ assigned-clocks = <&topckgen CLK_TOP_UART_SEL>,
+ <&infracfg CLK_INFRA_MUX_UART2_SEL>;
+ assigned-clock-parents = <&topckgen CLK_TOP_XTAL>,
+ <&topckgen CLK_TOP_UART_SEL>;
status = "disabled";
};
@@ -301,8 +294,8 @@
<0 0x10217080 0 0x80>;
interrupts = <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>;
clock-div = <1>;
- clocks = <&infracfg_ao CK_INFRA_I2C_BCK>,
- <&infracfg_ao CK_INFRA_66M_AP_DMA_BCK>;
+ clocks = <&infracfg CLK_INFRA_I2C_BCK>,
+ <&infracfg CLK_INFRA_66M_AP_DMA_BCK>;
clock-names = "main", "dma";
#address-cells = <1>;
#size-cells = <0>;
@@ -316,8 +309,8 @@
<0 0x10217100 0 0x80>;
interrupts = <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>;
clock-div = <1>;
- clocks = <&infracfg_ao CK_INFRA_I2C_BCK>,
- <&infracfg_ao CK_INFRA_66M_AP_DMA_BCK>;
+ clocks = <&infracfg CLK_INFRA_I2C_BCK>,
+ <&infracfg CLK_INFRA_66M_AP_DMA_BCK>;
clock-names = "main", "dma";
#address-cells = <1>;
#size-cells = <0>;
@@ -331,8 +324,8 @@
<0 0x10217180 0 0x80>;
interrupts = <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>;
clock-div = <1>;
- clocks = <&infracfg_ao CK_INFRA_I2C_BCK>,
- <&infracfg_ao CK_INFRA_66M_AP_DMA_BCK>;
+ clocks = <&infracfg CLK_INFRA_I2C_BCK>,
+ <&infracfg CLK_INFRA_66M_AP_DMA_BCK>;
clock-names = "main", "dma";
#address-cells = <1>;
#size-cells = <0>;
@@ -343,16 +336,16 @@
compatible = "mediatek,mt7988-pwm";
reg = <0 0x10048000 0 0x1000>;
#pwm-cells = <2>;
- clocks = <&infracfg_ao CK_INFRA_66M_PWM_BCK>,
- <&infracfg_ao CK_INFRA_66M_PWM_HCK>,
- <&infracfg_ao CK_INFRA_66M_PWM_CK1>,
- <&infracfg_ao CK_INFRA_66M_PWM_CK2>,
- <&infracfg_ao CK_INFRA_66M_PWM_CK3>,
- <&infracfg_ao CK_INFRA_66M_PWM_CK4>,
- <&infracfg_ao CK_INFRA_66M_PWM_CK5>,
- <&infracfg_ao CK_INFRA_66M_PWM_CK6>,
- <&infracfg_ao CK_INFRA_66M_PWM_CK7>,
- <&infracfg_ao CK_INFRA_66M_PWM_CK8>;
+ clocks = <&infracfg CLK_INFRA_66M_PWM_BCK>,
+ <&infracfg CLK_INFRA_66M_PWM_HCK>,
+ <&infracfg CLK_INFRA_66M_PWM_CK1>,
+ <&infracfg CLK_INFRA_66M_PWM_CK2>,
+ <&infracfg CLK_INFRA_66M_PWM_CK3>,
+ <&infracfg CLK_INFRA_66M_PWM_CK4>,
+ <&infracfg CLK_INFRA_66M_PWM_CK5>,
+ <&infracfg CLK_INFRA_66M_PWM_CK6>,
+ <&infracfg CLK_INFRA_66M_PWM_CK7>,
+ <&infracfg CLK_INFRA_66M_PWM_CK8>;
clock-names = "top", "main", "pwm1", "pwm2", "pwm3",
"pwm4","pwm5","pwm6","pwm7","pwm8";
status = "disabled";
@@ -365,14 +358,14 @@
<0 0x11002000 0 0x1000>;
reg-names = "nfi", "ecc";
interrupts = <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&infracfg_ao CK_INFRA_SPINFI>,
- <&infracfg_ao CK_INFRA_NFI>,
- <&infracfg_ao CK_INFRA_66M_NFI_HCK>;
+ clocks = <&infracfg CLK_INFRA_SPINFI>,
+ <&infracfg CLK_INFRA_NFI>,
+ <&infracfg CLK_INFRA_66M_NFI_HCK>;
clock-names = "pad_clk", "nfi_clk", "nfi_hclk";
- assigned-clocks = <&topckgen CK_TOP_SPINFI_SEL>,
- <&topckgen CK_TOP_NFI1X_SEL>;
- assigned-clock-parents = <&topckgen CK_TOP_CB_M_D8>,
- <&topckgen CK_TOP_CB_M_D8>;
+ assigned-clocks = <&topckgen CLK_TOP_SPINFI_SEL>,
+ <&topckgen CLK_TOP_NFI1X_SEL>;
+ assigned-clock-parents = <&topckgen CLK_TOP_MPLL_D8>,
+ <&topckgen CLK_TOP_MPLL_D8>;
status = "disabled";
};
@@ -408,10 +401,10 @@
"mediatek,mt7986-mmc";
reg = <0 0x11230000 0 0x1000>;
interrupts = <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&infracfg_ao_cgs CK_INFRA_MSDC400>,
- <&infracfg_ao_cgs CK_INFRA_MSDC2_HCK>,
- <&infracfg_ao_cgs CK_INFRA_133M_MSDC_0_HCK>,
- <&infracfg_ao_cgs CK_INFRA_66M_MSDC_0_HCK>;
+ clocks = <&infracfg CLK_INFRA_MSDC400>,
+ <&infracfg CLK_INFRA_MSDC2_HCK>,
+ <&infracfg CLK_INFRA_133M_MSDC_0_HCK>,
+ <&infracfg CLK_INFRA_66M_MSDC_0_HCK>;
clock-names = "source", "hclk", "source_cg", "axi_cg";
status = "disabled";
};
diff --git a/arch/arm/dts/omap3-sniper-u-boot.dtsi b/arch/arm/dts/omap3-sniper-u-boot.dtsi
new file mode 100644
index 0000000..d467f53
--- /dev/null
+++ b/arch/arm/dts/omap3-sniper-u-boot.dtsi
@@ -0,0 +1,16 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2024 Paul Kocialkowski <contact@paulk.fr>
+ */
+
+#include "omap3-u-boot.dtsi"
+
+/ {
+ chosen {
+ stdout-path = &uart3;
+ };
+};
+
+&i2c1 {
+ clock-frequency = <400000>;
+};
diff --git a/arch/arm/include/asm/arch-am33xx/sys_proto.h b/arch/arm/include/asm/arch-am33xx/sys_proto.h
index 513cdac..7abcd1c 100644
--- a/arch/arm/include/asm/arch-am33xx/sys_proto.h
+++ b/arch/arm/include/asm/arch-am33xx/sys_proto.h
@@ -37,7 +37,6 @@
#ifdef CONFIG_NOR_BOOT
void enable_norboot_pin_mux(void);
#endif
-void am33xx_spl_board_init(void);
int am335x_get_efuse_mpu_max_freq(struct ctrl_dev *cdev);
int am335x_get_mpu_vdd(int sil_rev, int frequency);
int am335x_get_tps65910_mpu_vdd(int sil_rev, int frequency);
diff --git a/arch/arm/include/asm/arch-rockchip/timer.h b/arch/arm/include/asm/arch-rockchip/timer.h
index 77b5422..b5fc738 100644
--- a/arch/arm/include/asm/arch-rockchip/timer.h
+++ b/arch/arm/include/asm/arch-rockchip/timer.h
@@ -15,4 +15,7 @@
u32 timer_int_status;
};
+/** rockchip_stimer_init() - Set up the timer ready for use */
+void rockchip_stimer_init(void);
+
#endif
diff --git a/arch/arm/lib/bdinfo.c b/arch/arm/lib/bdinfo.c
index 7c49462..c7fff01 100644
--- a/arch/arm/lib/bdinfo.c
+++ b/arch/arm/lib/bdinfo.c
@@ -58,7 +58,7 @@
printf("Board Type = %ld\n", gd->board_type);
#endif
#if CONFIG_IS_ENABLED(SYS_MALLOC_F)
- printf("Early malloc usage: %lx / %x\n", gd->malloc_ptr,
+ printf("Early malloc usage: %x / %x\n", gd->malloc_ptr,
CONFIG_VAL(SYS_MALLOC_F_LEN));
#endif
}
diff --git a/arch/arm/mach-exynos/include/mach/dwmmc.h b/arch/arm/mach-exynos/include/mach/dwmmc.h
index 59c28ed..75d8498 100644
--- a/arch/arm/mach-exynos/include/mach/dwmmc.h
+++ b/arch/arm/mach-exynos/include/mach/dwmmc.h
@@ -4,24 +4,34 @@
* Jaehoon Chung <jh80.chung@samsung.com>
*/
-#define DWMCI_CLKSEL 0x09C
-#define DWMCI_SET_SAMPLE_CLK(x) (x)
-#define DWMCI_SET_DRV_CLK(x) ((x) << 16)
-#define DWMCI_SET_DIV_RATIO(x) ((x) << 24)
+#ifndef __ASM_ARM_ARCH_DWMMC_H
+#define __ASM_ARM_ARCH_DWMMC_H
-#define EMMCP_MPSBEGIN0 0x1200
-#define EMMCP_SEND0 0x1204
-#define EMMCP_CTRL0 0x120C
+#include <linux/bitops.h>
-#define MPSCTRL_SECURE_READ_BIT (0x1<<7)
-#define MPSCTRL_SECURE_WRITE_BIT (0x1<<6)
-#define MPSCTRL_NON_SECURE_READ_BIT (0x1<<5)
-#define MPSCTRL_NON_SECURE_WRITE_BIT (0x1<<4)
-#define MPSCTRL_USE_FUSE_KEY (0x1<<3)
-#define MPSCTRL_ECB_MODE (0x1<<2)
-#define MPSCTRL_ENCRYPTION (0x1<<1)
-#define MPSCTRL_VALID (0x1<<0)
+#define DWMCI_CLKSEL 0x09c
+#define DWMCI_CLKSEL64 0x0a8
+#define DWMCI_SET_SAMPLE_CLK(x) (x)
+#define DWMCI_SET_DRV_CLK(x) ((x) << 16)
+#define DWMCI_SET_DIV_RATIO(x) ((x) << 24)
+
+/* Protector Register */
+#define DWMCI_EMMCP_BASE 0x1000
+#define EMMCP_MPSBEGIN0 (DWMCI_EMMCP_BASE + 0x0200)
+#define EMMCP_SEND0 (DWMCI_EMMCP_BASE + 0x0204)
+#define EMMCP_CTRL0 (DWMCI_EMMCP_BASE + 0x020c)
+
+#define MPSCTRL_SECURE_READ_BIT BIT(7)
+#define MPSCTRL_SECURE_WRITE_BIT BIT(6)
+#define MPSCTRL_NON_SECURE_READ_BIT BIT(5)
+#define MPSCTRL_NON_SECURE_WRITE_BIT BIT(4)
+#define MPSCTRL_USE_FUSE_KEY BIT(3)
+#define MPSCTRL_ECB_MODE BIT(2)
+#define MPSCTRL_ENCRYPTION BIT(1)
+#define MPSCTRL_VALID BIT(0)
/* CLKSEL Register */
#define DWMCI_DIVRATIO_BIT 24
#define DWMCI_DIVRATIO_MASK 0x7
+
+#endif /* __ASM_ARM_ARCH_DWMMC_H */
diff --git a/arch/arm/mach-exynos/spl_boot.c b/arch/arm/mach-exynos/spl_boot.c
index bd5a064..219d7fb 100644
--- a/arch/arm/mach-exynos/spl_boot.c
+++ b/arch/arm/mach-exynos/spl_boot.c
@@ -312,7 +312,7 @@
memzero((void *)gd, sizeof(gd_t));
gd->flags |= GD_FLG_RELOC;
gd->baudrate = CONFIG_BAUDRATE;
- gd->have_console = 1;
+ gd->flags |= GD_FLG_HAVE_CONSOLE;
}
void board_init_f(unsigned long bootflag)
diff --git a/arch/arm/mach-imx/imx8m/soc.c b/arch/arm/mach-imx/imx8m/soc.c
index be38ca5..f30178a 100644
--- a/arch/arm/mach-imx/imx8m/soc.c
+++ b/arch/arm/mach-imx/imx8m/soc.c
@@ -735,6 +735,7 @@
#endif
#if defined(CONFIG_IMX8MN) || defined(CONFIG_IMX8MP)
+#ifdef SYS_MMCSD_RAW_MODE_U_BOOT_USE_PARTITION
#define IMG_CNTN_SET1_OFFSET GENMASK(22, 19)
unsigned long arch_spl_mmc_get_uboot_raw_sector(struct mmc *mmc,
unsigned long raw_sect)
@@ -769,6 +770,7 @@
return raw_sect;
}
+#endif /* SYS_MMCSD_RAW_MODE_U_BOOT_USE_PARTITION */
#endif
bool is_usb_boot(void)
diff --git a/arch/arm/mach-imx/imx9/soc.c b/arch/arm/mach-imx/imx9/soc.c
index 3220822..f88e7a2 100644
--- a/arch/arm/mach-imx/imx9/soc.c
+++ b/arch/arm/mach-imx/imx9/soc.c
@@ -536,7 +536,7 @@
temp = 0;
if (!strcmp(type, "critical"))
- temp = 1000 * (maxc - 5);
+ temp = 1000 * maxc;
else if (!strcmp(type, "passive"))
temp = 1000 * (maxc - 10);
if (temp) {
diff --git a/arch/arm/mach-imx/mx6/soc.c b/arch/arm/mach-imx/mx6/soc.c
index 3a3e01f..2c0c77e 100644
--- a/arch/arm/mach-imx/mx6/soc.c
+++ b/arch/arm/mach-imx/mx6/soc.c
@@ -585,6 +585,10 @@
{"ecspi1:1", MAKE_CFGVAL(0x30, 0x00, 0x00, 0x18)},
{"ecspi1:2", MAKE_CFGVAL(0x30, 0x00, 0x00, 0x28)},
{"ecspi1:3", MAKE_CFGVAL(0x30, 0x00, 0x00, 0x38)},
+ {"ecspi3:0", MAKE_CFGVAL(0x30, 0x00, 0x00, 0x0a)},
+ {"ecspi3:1", MAKE_CFGVAL(0x30, 0x00, 0x00, 0x1a)},
+ {"ecspi3:2", MAKE_CFGVAL(0x30, 0x00, 0x00, 0x2a)},
+ {"ecspi3:3", MAKE_CFGVAL(0x30, 0x00, 0x00, 0x3a)},
/* 4 bit bus width */
{"esdhc1", MAKE_CFGVAL(0x40, 0x20, 0x00, 0x00)},
{"esdhc2", MAKE_CFGVAL(0x40, 0x28, 0x00, 0x00)},
diff --git a/arch/arm/mach-imx/spl_imx_romapi.c b/arch/arm/mach-imx/spl_imx_romapi.c
index 9a86f5c..3982f4c 100644
--- a/arch/arm/mach-imx/spl_imx_romapi.c
+++ b/arch/arm/mach-imx/spl_imx_romapi.c
@@ -33,8 +33,17 @@
ulong __weak spl_romapi_get_uboot_base(u32 image_offset, u32 rom_bt_dev)
{
- return image_offset +
- (CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR * 512 - 0x8000);
+ u32 sector = 0;
+
+ /*
+ * Some boards use this value even though MMC is not enabled in SPL, for
+ * example imx8mn_bsh_smm_s2
+ */
+#ifdef CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR
+ sector = CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR;
+#endif
+
+ return image_offset + sector * 512 - 0x8000;
}
static int is_boot_from_stream_device(u32 boot)
@@ -99,18 +108,13 @@
if (IS_ENABLED(CONFIG_SPL_LOAD_FIT) && image_get_magic(header) == FDT_MAGIC) {
struct spl_load_info load;
- memset(&load, 0, sizeof(load));
- spl_set_bl_len(&load, pagesize);
- load.read = spl_romapi_read_seekable;
+ spl_load_init(&load, spl_romapi_read_seekable, NULL, pagesize);
return spl_load_simple_fit(spl_image, &load, offset, header);
} else if (IS_ENABLED(CONFIG_SPL_LOAD_IMX_CONTAINER) &&
valid_container_hdr((void *)header)) {
struct spl_load_info load;
- memset(&load, 0, sizeof(load));
- spl_set_bl_len(&load, pagesize);
- load.read = spl_romapi_read_seekable;
-
+ spl_load_init(&load, spl_romapi_read_seekable, NULL, pagesize);
ret = spl_load_imx_container(spl_image, &load, offset);
} else {
/* TODO */
@@ -332,10 +336,7 @@
ss.end = p;
ss.pagesize = pagesize;
- memset(&load, 0, sizeof(load));
- spl_set_bl_len(&load, 1);
- load.read = spl_romapi_read_stream;
- load.priv = &ss;
+ spl_load_init(&load, spl_romapi_read_stream, &ss, 1);
return spl_load_simple_fit(spl_image, &load, (ulong)phdr, phdr);
}
diff --git a/arch/arm/mach-k3/common.c b/arch/arm/mach-k3/common.c
index eaa7d36..df48ec8 100644
--- a/arch/arm/mach-k3/common.c
+++ b/arch/arm/mach-k3/common.c
@@ -104,7 +104,7 @@
gd->cur_serial_dev = dev;
gd->flags |= GD_FLG_SERIAL_READY;
- gd->have_console = 1;
+ gd->flags |= GD_FLG_HAVE_CONSOLE;
return 0;
}
diff --git a/arch/arm/mach-k3/r5/sysfw-loader.c b/arch/arm/mach-k3/r5/sysfw-loader.c
index 94d051b..188731e 100644
--- a/arch/arm/mach-k3/r5/sysfw-loader.c
+++ b/arch/arm/mach-k3/r5/sysfw-loader.c
@@ -451,7 +451,7 @@
* the case when continuing to boot serially from the same
* UART that the ROM loaded the initial bootloader from.
*/
- if (!gd->have_console)
+ if (!(gd->flags & GD_FLG_HAVE_CONSOLE))
early_console_init();
#endif
ret = spl_ymodem_load_image(&spl_image, &bootdev);
diff --git a/arch/arm/mach-omap2/am33xx/board.c b/arch/arm/mach-omap2/am33xx/board.c
index 84a60de..abdc1e4 100644
--- a/arch/arm/mach-omap2/am33xx/board.c
+++ b/arch/arm/mach-omap2/am33xx/board.c
@@ -337,14 +337,6 @@
return 0;
}
-/*
- * This function is the place to do per-board things such as ramp up the
- * MPU clock frequency.
- */
-__weak void am33xx_spl_board_init(void)
-{
-}
-
#if defined(CONFIG_SPL_AM33XX_ENABLE_RTC32K_OSC)
static void rtc32k_enable(void)
{
diff --git a/arch/arm/mach-omap2/boot-common.c b/arch/arm/mach-omap2/boot-common.c
index e1ea351..649bc07 100644
--- a/arch/arm/mach-omap2/boot-common.c
+++ b/arch/arm/mach-omap2/boot-common.c
@@ -269,7 +269,7 @@
debug("%s: IPU2 failed to start (%d)\n", __func__, ret);
}
-void spl_board_init(void)
+void spl_soc_init(void)
{
/* Prepare console output */
preloader_console_init();
@@ -286,9 +286,6 @@
#if defined(CONFIG_HW_WATCHDOG) || defined(CONFIG_WATCHDOG)
hw_watchdog_init();
#endif
-#ifdef CONFIG_AM33XX
- am33xx_spl_board_init();
-#endif
if (IS_ENABLED(CONFIG_SPL_BUILD) &&
IS_ENABLED(CONFIG_REMOTEPROC_TI_IPU))
spl_boot_ipu();
diff --git a/arch/arm/mach-rockchip/Makefile b/arch/arm/mach-rockchip/Makefile
index c07bdae..3b13891 100644
--- a/arch/arm/mach-rockchip/Makefile
+++ b/arch/arm/mach-rockchip/Makefile
@@ -8,9 +8,9 @@
# inaccessible/protected memory (and the bootrom-helper assumes that
# the stack-pointer is valid before switching to the U-Boot stack).
obj-spl-$(CONFIG_ROCKCHIP_BROM_HELPER) += bootrom.o
-obj-spl-$(CONFIG_SPL_ROCKCHIP_COMMON_BOARD) += spl.o spl-boot-order.o
+obj-spl-$(CONFIG_SPL_ROCKCHIP_COMMON_BOARD) += spl.o spl-boot-order.o spl_common.o
obj-tpl-$(CONFIG_ROCKCHIP_BROM_HELPER) += bootrom.o
-obj-tpl-$(CONFIG_TPL_ROCKCHIP_COMMON_BOARD) += tpl.o
+obj-tpl-$(CONFIG_TPL_ROCKCHIP_COMMON_BOARD) += tpl.o spl_common.o
obj-tpl-$(CONFIG_ROCKCHIP_PX30) += px30-board-tpl.o
obj-spl-$(CONFIG_ROCKCHIP_RK3036) += rk3036-board-spl.o
diff --git a/arch/arm/mach-rockchip/spl.c b/arch/arm/mach-rockchip/spl.c
index 3ce7e79..f4d29bb 100644
--- a/arch/arm/mach-rockchip/spl.c
+++ b/arch/arm/mach-rockchip/spl.c
@@ -13,6 +13,7 @@
#include <ram.h>
#include <spl.h>
#include <asm/arch-rockchip/bootrom.h>
+#include <asm/arch-rockchip/timer.h>
#include <asm/global_data.h>
#include <asm/io.h>
#include <linux/bitops.h>
@@ -79,33 +80,6 @@
return MMCSD_MODE_RAW;
}
-#define TIMER_LOAD_COUNT_L 0x00
-#define TIMER_LOAD_COUNT_H 0x04
-#define TIMER_CONTROL_REG 0x10
-#define TIMER_EN 0x1
-#define TIMER_FMODE BIT(0)
-#define TIMER_RMODE BIT(1)
-
-__weak void rockchip_stimer_init(void)
-{
-#if defined(CONFIG_ROCKCHIP_STIMER_BASE)
- /* If Timer already enabled, don't re-init it */
- u32 reg = readl(CONFIG_ROCKCHIP_STIMER_BASE + TIMER_CONTROL_REG);
-
- if (reg & TIMER_EN)
- return;
-#ifndef CONFIG_ARM64
- asm volatile("mcr p15, 0, %0, c14, c0, 0"
- : : "r"(CONFIG_COUNTER_FREQUENCY));
-#endif
- writel(0, CONFIG_ROCKCHIP_STIMER_BASE + TIMER_CONTROL_REG);
- writel(0xffffffff, CONFIG_ROCKCHIP_STIMER_BASE);
- writel(0xffffffff, CONFIG_ROCKCHIP_STIMER_BASE + 4);
- writel(TIMER_EN | TIMER_FMODE, CONFIG_ROCKCHIP_STIMER_BASE +
- TIMER_CONTROL_REG);
-#endif
-}
-
__weak int board_early_init_f(void)
{
return 0;
diff --git a/arch/arm/mach-rockchip/spl_common.c b/arch/arm/mach-rockchip/spl_common.c
new file mode 100644
index 0000000..b29f334
--- /dev/null
+++ b/arch/arm/mach-rockchip/spl_common.c
@@ -0,0 +1,36 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * (C) Copyright 2019 Rockchip Electronics Co., Ltd
+ */
+
+#include <asm/io.h>
+#include <linux/bitops.h>
+
+#define TIMER_LOAD_COUNT_L 0x00
+#define TIMER_LOAD_COUNT_H 0x04
+#define TIMER_CONTROL_REG 0x10
+#define TIMER_EN 0x1
+#define TIMER_FMODE BIT(0)
+#define TIMER_RMODE BIT(1)
+
+__weak void rockchip_stimer_init(void)
+{
+#if defined(CONFIG_ROCKCHIP_STIMER_BASE)
+ /* If Timer already enabled, don't re-init it */
+ u32 reg = readl(CONFIG_ROCKCHIP_STIMER_BASE + TIMER_CONTROL_REG);
+
+ if (reg & TIMER_EN)
+ return;
+
+#ifndef CONFIG_ARM64
+ asm volatile("mcr p15, 0, %0, c14, c0, 0"
+ : : "r"(CONFIG_COUNTER_FREQUENCY));
+#endif
+
+ writel(0, CONFIG_ROCKCHIP_STIMER_BASE + TIMER_CONTROL_REG);
+ writel(0xffffffff, CONFIG_ROCKCHIP_STIMER_BASE);
+ writel(0xffffffff, CONFIG_ROCKCHIP_STIMER_BASE + 4);
+ writel(TIMER_EN | TIMER_FMODE, CONFIG_ROCKCHIP_STIMER_BASE +
+ TIMER_CONTROL_REG);
+#endif
+}
diff --git a/arch/arm/mach-rockchip/tpl.c b/arch/arm/mach-rockchip/tpl.c
index 597a5ca..bbb9329 100644
--- a/arch/arm/mach-rockchip/tpl.c
+++ b/arch/arm/mach-rockchip/tpl.c
@@ -14,41 +14,13 @@
#include <version.h>
#include <asm/io.h>
#include <asm/arch-rockchip/bootrom.h>
+#include <asm/arch-rockchip/timer.h>
#include <linux/bitops.h>
#if CONFIG_IS_ENABLED(BANNER_PRINT)
#include <timestamp.h>
#endif
-#define TIMER_LOAD_COUNT_L 0x00
-#define TIMER_LOAD_COUNT_H 0x04
-#define TIMER_CONTROL_REG 0x10
-#define TIMER_EN 0x1
-#define TIMER_FMODE BIT(0)
-#define TIMER_RMODE BIT(1)
-
-__weak void rockchip_stimer_init(void)
-{
-#if defined(CONFIG_ROCKCHIP_STIMER_BASE)
- /* If Timer already enabled, don't re-init it */
- u32 reg = readl(CONFIG_ROCKCHIP_STIMER_BASE + TIMER_CONTROL_REG);
-
- if (reg & TIMER_EN)
- return;
-
-#ifndef CONFIG_ARM64
- asm volatile("mcr p15, 0, %0, c14, c0, 0"
- : : "r"(CONFIG_COUNTER_FREQUENCY));
-#endif
-
- writel(0, CONFIG_ROCKCHIP_STIMER_BASE + TIMER_CONTROL_REG);
- writel(0xffffffff, CONFIG_ROCKCHIP_STIMER_BASE);
- writel(0xffffffff, CONFIG_ROCKCHIP_STIMER_BASE + 4);
- writel(TIMER_EN | TIMER_FMODE, CONFIG_ROCKCHIP_STIMER_BASE +
- TIMER_CONTROL_REG);
-#endif
-}
-
void board_init_f(ulong dummy)
{
struct udevice *dev;
diff --git a/arch/arm/mach-sunxi/spl_spi_sunxi.c b/arch/arm/mach-sunxi/spl_spi_sunxi.c
index d7abdc2..5f72e80 100644
--- a/arch/arm/mach-sunxi/spl_spi_sunxi.c
+++ b/arch/arm/mach-sunxi/spl_spi_sunxi.c
@@ -390,8 +390,7 @@
struct spl_load_info load;
debug("Found FIT image\n");
- spl_set_bl_len(&load, 1);
- load.read = spi_load_read;
+ spl_load_init(&load, spi_load_read, NULL, 1);
ret = spl_load_simple_fit(spl_image, &load,
load_offset, header);
} else {
diff --git a/arch/arm/mach-tegra/board2.c b/arch/arm/mach-tegra/board2.c
index 479137e..7971e3b 100644
--- a/arch/arm/mach-tegra/board2.c
+++ b/arch/arm/mach-tegra/board2.c
@@ -423,10 +423,6 @@
gd->bd->bi_dram[0].start = CFG_SYS_SDRAM_BASE;
gd->bd->bi_dram[0].size = usable_ram_size_below_4g();
-#ifdef CONFIG_PCI
- gd->pci_ram_top = gd->bd->bi_dram[0].start + gd->bd->bi_dram[0].size;
-#endif
-
#ifdef CONFIG_PHYS_64BIT
if (gd->ram_size > SZ_2G) {
gd->bd->bi_dram[1].start = 0x100000000;
diff --git a/arch/arm/mach-tegra/cboot.c b/arch/arm/mach-tegra/cboot.c
index c12543d..e2342b2 100644
--- a/arch/arm/mach-tegra/cboot.c
+++ b/arch/arm/mach-tegra/cboot.c
@@ -189,10 +189,6 @@
gd->bd->bi_dram[i].size = tegra_mem_map[1 + i].size;
}
-#ifdef CONFIG_PCI
- gd->pci_ram_top = ram_top;
-#endif
-
return 0;
}
diff --git a/arch/m68k/cpu/mcf5445x/cpu.c b/arch/m68k/cpu/mcf5445x/cpu.c
index b811ac3..3fbd6a5 100644
--- a/arch/m68k/cpu/mcf5445x/cpu.c
+++ b/arch/m68k/cpu/mcf5445x/cpu.c
@@ -92,7 +92,7 @@
strmhz(buf3, gd->arch.flb_clk));
#ifdef CONFIG_PCI
printf(" PCI CLK %s MHz INP CLK %s MHz VCO CLK %s MHz\n",
- strmhz(buf1, gd->pci_clk),
+ strmhz(buf1, gd->arch.pci_clk),
strmhz(buf2, gd->arch.inp_clk),
strmhz(buf3, gd->arch.vco_clk));
#else
diff --git a/arch/m68k/include/asm/global_data.h b/arch/m68k/include/asm/global_data.h
index 93efc72..4ac8869 100644
--- a/arch/m68k/include/asm/global_data.h
+++ b/arch/m68k/include/asm/global_data.h
@@ -26,6 +26,8 @@
#if defined(CONFIG_FSL_ESDHC)
unsigned long sdhc_per_clk;
#endif
+ /** @pci_clk: PCI clock rate in Hz */
+ unsigned long pci_clk;
};
#include <asm-generic/global_data.h>
diff --git a/arch/m68k/lib/bdinfo.c b/arch/m68k/lib/bdinfo.c
index cf6ae5a..891e94b 100644
--- a/arch/m68k/lib/bdinfo.c
+++ b/arch/m68k/lib/bdinfo.c
@@ -22,7 +22,7 @@
bd->bi_busfreq = gd->bus_clk; /* Bus Freq, in Hz */
if (IS_ENABLED(CONFIG_PCI))
- bd->bi_pcifreq = gd->pci_clk;
+ bd->bi_pcifreq = gd->arch.pci_clk;
#if defined(CONFIG_EXTRA_CLOCK)
bd->bi_inpfreq = gd->arch.inp_clk; /* input Freq in Hz */
diff --git a/arch/mips/mach-ath79/ar934x/clk.c b/arch/mips/mach-ath79/ar934x/clk.c
index bdaa683..231a21c 100644
--- a/arch/mips/mach-ath79/ar934x/clk.c
+++ b/arch/mips/mach-ath79/ar934x/clk.c
@@ -327,8 +327,8 @@
{
ar934x_update_clock();
printf("CPU: %8ld MHz\n", gd->cpu_clk / 1000000);
- printf("Memory: %8ld MHz\n", gd->mem_clk / 1000000);
- printf("AHB: %8ld MHz\n", gd->bus_clk / 1000000);
+ printf("Memory: %8d MHz\n", gd->mem_clk / 1000000);
+ printf("AHB: %8d MHz\n", gd->bus_clk / 1000000);
return 0;
}
diff --git a/arch/mips/mach-octeon/cpu.c b/arch/mips/mach-octeon/cpu.c
index c7744e8..c771da6 100644
--- a/arch/mips/mach-octeon/cpu.c
+++ b/arch/mips/mach-octeon/cpu.c
@@ -67,7 +67,7 @@
gd->cpu_clk = ref_clock * FIELD_GET(RST_BOOT_C_MUL, val);
gd->bus_clk = ref_clock * FIELD_GET(RST_BOOT_PNR_MUL, val);
- debug("%s: cpu: %lu, bus: %lu\n", __func__, gd->cpu_clk, gd->bus_clk);
+ debug("%s: cpu: %lu, bus: %u\n", __func__, gd->cpu_clk, gd->bus_clk);
return 0;
}
diff --git a/arch/mips/mach-octeon/octeon_fdt.c b/arch/mips/mach-octeon/octeon_fdt.c
index c74fe9d..15ce292 100644
--- a/arch/mips/mach-octeon/octeon_fdt.c
+++ b/arch/mips/mach-octeon/octeon_fdt.c
@@ -687,13 +687,6 @@
while (node_offset > 0 &&
!(found = !fdt_node_check_compatible(fdt, node_offset, compat))) {
node_offset = fdt_parent_offset(fdt, node_offset);
-#ifdef CONFIG_OCTEON_I2C_FDT
- bus = i2c_get_bus_num_fdt(node_offset);
- if (bus >= 0) {
- debug("%s: Found bus 0x%x\n", __func__, bus);
- return bus;
- }
-#endif
}
if (!found) {
printf("Error: node %d in device tree is not a child of the I2C bus\n",
diff --git a/arch/powerpc/cpu/mpc83xx/pci.c b/arch/powerpc/cpu/mpc83xx/pci.c
index 6f378c4..aef1123 100644
--- a/arch/powerpc/cpu/mpc83xx/pci.c
+++ b/arch/powerpc/cpu/mpc83xx/pci.c
@@ -45,7 +45,7 @@
do_fixup_by_path(blob, path, "bus-range",
&tmp, sizeof(tmp), 1);
- tmp[0] = cpu_to_be32(gd->pci_clk);
+ tmp[0] = cpu_to_be32(gd->arch.pci_clk);
do_fixup_by_path(blob, path, "clock-frequency",
&tmp, sizeof(tmp[0]), 1);
}
@@ -60,7 +60,7 @@
do_fixup_by_path(blob, path, "bus-range",
&tmp, sizeof(tmp), 1);
- tmp[0] = cpu_to_be32(gd->pci_clk);
+ tmp[0] = cpu_to_be32(gd->arch.pci_clk);
do_fixup_by_path(blob, path, "clock-frequency",
&tmp, sizeof(tmp[0]), 1);
}
diff --git a/arch/powerpc/cpu/mpc83xx/speed.c b/arch/powerpc/cpu/mpc83xx/speed.c
index 7246496..0185ab5 100644
--- a/arch/powerpc/cpu/mpc83xx/speed.c
+++ b/arch/powerpc/cpu/mpc83xx/speed.c
@@ -456,7 +456,7 @@
#if defined(CONFIG_ARCH_MPC837X)
gd->arch.sata_clk = sata_clk;
#endif
- gd->pci_clk = pci_sync_in;
+ gd->arch.pci_clk = pci_sync_in;
gd->cpu_clk = gd->arch.core_clk;
gd->bus_clk = gd->arch.csb_clk;
return 0;
diff --git a/arch/powerpc/include/asm/global_data.h b/arch/powerpc/include/asm/global_data.h
index a9efbbd..cc2ce61 100644
--- a/arch/powerpc/include/asm/global_data.h
+++ b/arch/powerpc/include/asm/global_data.h
@@ -87,6 +87,8 @@
#if defined(CONFIG_LWMON5)
unsigned long kbd_status;
#endif
+ /** @pci_clk: PCI clock rate in Hz */
+ unsigned long pci_clk;
};
#include <asm-generic/global_data.h>
diff --git a/arch/sandbox/cpu/cpu.c b/arch/sandbox/cpu/cpu.c
index 0ed85b3..4f15a56 100644
--- a/arch/sandbox/cpu/cpu.c
+++ b/arch/sandbox/cpu/cpu.c
@@ -340,6 +340,8 @@
int err;
int fd;
+ if (gd->fdt_blob)
+ return (void *)gd->fdt_blob;
blob = map_sysmem(CONFIG_SYS_FDT_LOAD_ADDR, 0);
*ret = 0;
if (!state->fdt_fname) {
diff --git a/arch/sandbox/cpu/os.c b/arch/sandbox/cpu/os.c
index 46ff305..f5c9a8a 100644
--- a/arch/sandbox/cpu/os.c
+++ b/arch/sandbox/cpu/os.c
@@ -47,12 +47,24 @@
ssize_t os_read(int fd, void *buf, size_t count)
{
- return read(fd, buf, count);
+ ssize_t ret;
+
+ ret = read(fd, buf, count);
+ if (ret == -1)
+ return -errno;
+
+ return ret;
}
ssize_t os_write(int fd, const void *buf, size_t count)
{
- return write(fd, buf, count);
+ ssize_t ret;
+
+ ret = write(fd, buf, count);
+ if (ret == -1)
+ return -errno;
+
+ return ret;
}
int os_printf(const char *fmt, ...)
@@ -69,6 +81,8 @@
off_t os_lseek(int fd, off_t offset, int whence)
{
+ off_t ret;
+
if (whence == OS_SEEK_SET)
whence = SEEK_SET;
else if (whence == OS_SEEK_CUR)
@@ -77,7 +91,11 @@
whence = SEEK_END;
else
os_exit(1);
- return lseek(fd, offset, whence);
+ ret = lseek(fd, offset, whence);
+ if (ret == -1)
+ return -errno;
+
+ return ret;
}
int os_open(const char *pathname, int os_flags)
@@ -808,7 +826,7 @@
* @count: Number of arguments in @add_args
* Return: 0 if OK, -ENOMEM if out of memory
*/
-static int add_args(char ***argvp, char *add_args[], int count)
+static int add_args(char ***argvp, const char *add_args[], int count)
{
char **argv, **ap;
int argc;
@@ -859,7 +877,7 @@
struct sandbox_state *state = state_get_current();
char mem_fname[30];
int fd, err;
- char *extra_args[5];
+ const char *extra_args[5];
char **argv = state->argv;
int argc;
#ifdef DEBUG
@@ -964,7 +982,7 @@
p = strstr(fname, subdir);
if (p) {
if (*next_prefix)
- /* e.g. ".../tpl/u-boot-spl" to "../spl/u-boot-spl" */
+ /* e.g. ".../tpl/u-boot-spl" to ".../spl/u-boot-spl" */
memcpy(p + 1, next_prefix, strlen(next_prefix));
else
/* e.g. ".../spl/u-boot" to ".../u-boot" */
diff --git a/arch/sandbox/cpu/spl.c b/arch/sandbox/cpu/spl.c
index 9ad9da6..cc46965 100644
--- a/arch/sandbox/cpu/spl.c
+++ b/arch/sandbox/cpu/spl.c
@@ -3,13 +3,18 @@
* Copyright (c) 2016 Google, Inc
*/
+#define LOG_CATEGORY LOGC_BOOT
+
#include <dm.h>
#include <hang.h>
#include <handoff.h>
+#include <image.h>
#include <init.h>
#include <log.h>
+#include <mapmem.h>
#include <os.h>
#include <spl.h>
+#include <upl.h>
#include <asm/global_data.h>
#include <asm/spl.h>
#include <asm/state.h>
@@ -51,7 +56,8 @@
void board_boot_order(u32 *spl_boot_list)
{
spl_boot_list[0] = BOOT_DEVICE_VBE;
- spl_boot_list[1] = BOOT_DEVICE_BOARD;
+ spl_boot_list[1] = BOOT_DEVICE_UPL;
+ spl_boot_list[2] = BOOT_DEVICE_BOARD;
}
static int spl_board_load_file(struct spl_image_info *spl_image,
@@ -179,3 +185,114 @@
return 0;
}
+
+/* Context used to hold file descriptor */
+struct load_ctx {
+ int fd;
+};
+
+static ulong read_fit_image(struct spl_load_info *load, ulong offset,
+ ulong size, void *buf)
+{
+ struct load_ctx *load_ctx = load->priv;
+ off_t ret;
+ ssize_t res;
+
+ ret = os_lseek(load_ctx->fd, offset, OS_SEEK_SET);
+ if (ret < 0) {
+ printf("Failed to seek to %zx, got %zx\n", offset, ret);
+ return log_msg_ret("lse", ret);
+ }
+
+ res = os_read(load_ctx->fd, buf, size);
+ if (res < 0) {
+ printf("Failed to read %lx bytes, got %ld\n", size, res);
+ return log_msg_ret("osr", res);
+ }
+
+ return size;
+}
+
+int sandbox_spl_load_fit(char *fname, int maxlen, struct spl_image_info *image)
+{
+ struct legacy_img_hdr *header;
+ struct load_ctx load_ctx;
+ struct spl_load_info load;
+ int ret;
+ int fd;
+
+ spl_load_init(&load, read_fit_image, &load_ctx,
+ IS_ENABLED(CONFIG_SPL_LOAD_BLOCK) ? 512 : 1);
+
+ ret = sandbox_find_next_phase(fname, maxlen, true);
+ if (ret) {
+ printf("%s not found, error %d\n", fname, ret);
+ return log_msg_ret("nph", ret);
+ }
+
+ header = spl_get_load_buffer(-sizeof(*header), sizeof(*header));
+
+ log_debug("reading from %s\n", fname);
+ fd = os_open(fname, OS_O_RDONLY);
+ if (fd < 0) {
+ printf("Failed to open '%s'\n", fname);
+ return log_msg_ret("ope", -errno);
+ }
+ ret = os_read(fd, header, sizeof(*header));
+ if (ret != sizeof(*header)) {
+ printf("Failed to read %lx bytes, got %d\n", sizeof(*header),
+ ret);
+ return log_msg_ret("rea", ret);
+ }
+ load_ctx.fd = fd;
+
+ load.priv = &load_ctx;
+
+ ret = spl_load_simple_fit(image, &load, 0, header);
+ if (ret)
+ return log_msg_ret("slf", ret);
+
+ return 0;
+}
+
+static int upl_load_from_image(struct spl_image_info *spl_image,
+ struct spl_boot_device *bootdev)
+{
+ long long size;
+ char *fname;
+ int ret, fd;
+ ulong addr;
+
+ if (!CONFIG_IS_ENABLED(UPL_OUT))
+ return -ENOTSUPP;
+
+ spl_upl_init();
+ fname = os_malloc(256);
+
+ ret = sandbox_spl_load_fit(fname, 256, spl_image);
+ if (ret)
+ return log_msg_ret("fit", ret);
+ spl_image->flags = SPL_SANDBOXF_ARG_IS_BUF;
+ spl_image->arg = map_sysmem(spl_image->load_addr, 0);
+ /* size is set by load_simple_fit(), offset is left as 0 */
+
+ /* now read the whole FIT into memory */
+ fd = os_open(fname, OS_O_RDONLY);
+ if (fd < 0)
+ return log_msg_ret("op2", -ENOENT);
+ if (os_get_filesize(fname, &size))
+ return log_msg_ret("fis", -ENOENT);
+
+ /* place it after the loaded image, allowing plenty of space */
+ addr = ALIGN(spl_image->load_addr + size, 0x1000);
+ log_debug("Loading whole FIT to %lx\n", addr);
+ if (os_read(fd, map_sysmem(addr, 0), size) != size)
+ return log_msg_ret("rea", -EIO);
+ os_close(fd);
+
+ /* tell UPL where it is */
+ upl_set_fit_addr(addr);
+
+ return 0;
+}
+SPL_LOAD_IMAGE_METHOD("upl", 4, BOOT_DEVICE_UPL, upl_load_from_image);
diff --git a/arch/sandbox/cpu/start.c b/arch/sandbox/cpu/start.c
index dce8041..9ad5d46 100644
--- a/arch/sandbox/cpu/start.c
+++ b/arch/sandbox/cpu/start.c
@@ -431,6 +431,14 @@
}
SANDBOX_CMDLINE_OPT(autoboot_keyed, 0, "Allow keyed autoboot");
+static int sandbox_cmdline_cb_upl(struct sandbox_state *state, const char *arg)
+{
+ state->upl = true;
+
+ return 0;
+}
+SANDBOX_CMDLINE_OPT(upl, 0, "Enable Universal Payload (UPL)");
+
static void setup_ram_buf(struct sandbox_state *state)
{
/* Zero the RAM buffer if we didn't read it, to keep valgrind happy */
@@ -483,6 +491,9 @@
text_base = os_find_text_base();
+ memset(&data, '\0', sizeof(data));
+ gd = &data;
+
/*
* This must be the first invocation of os_malloc() to have
* state->ram_buf in the low 4 GiB.
@@ -501,8 +512,6 @@
os_exit(1);
memcpy(os_argv, argv, size);
- memset(&data, '\0', sizeof(data));
- gd = &data;
gd->arch.text_base = text_base;
state = state_get_current();
@@ -539,6 +548,9 @@
goto err;
}
+ if (state->upl)
+ gd->flags |= GD_FLG_UPL;
+
#if CONFIG_IS_ENABLED(SYS_MALLOC_F)
gd->malloc_base = CFG_MALLOC_F_ADDR;
#endif
@@ -557,7 +569,7 @@
log_debug("debug: %s\n", __func__);
/* Do pre- and post-relocation init */
- board_init_f(0);
+ board_init_f(gd->flags);
board_init_r(gd->new_gd, 0);
diff --git a/arch/sandbox/include/asm/spl.h b/arch/sandbox/include/asm/spl.h
index 4fab24c..d824b21 100644
--- a/arch/sandbox/include/asm/spl.h
+++ b/arch/sandbox/include/asm/spl.h
@@ -6,6 +6,8 @@
#ifndef __asm_spl_h
#define __asm_spl_h
+struct spl_image_info;
+
enum {
BOOT_DEVICE_MMC1,
BOOT_DEVICE_MMC2,
@@ -16,6 +18,7 @@
BOOT_DEVICE_NOR,
BOOT_DEVICE_SPI,
BOOT_DEVICE_NAND,
+ BOOT_DEVICE_UPL,
};
/**
@@ -31,4 +34,16 @@
*/
int sandbox_find_next_phase(char *fname, int maxlen, bool use_img);
+/**
+ * sandbox_spl_load_fit() - Load the next phase from a FIT
+ *
+ * Loads a FIT containing the next phase and sets it up for booting
+ *
+ * @fname: Returns filename loaded
+ * @maxlen: Maximum length for @fname including \0
+ * @image: Place to put SPL-image information
+ * Return: 0 if OK, -ve on error
+ */
+int sandbox_spl_load_fit(char *fname, int maxlen, struct spl_image_info *image);
+
#endif
diff --git a/arch/sandbox/include/asm/state.h b/arch/sandbox/include/asm/state.h
index c84a1f7..6b50473 100644
--- a/arch/sandbox/include/asm/state.h
+++ b/arch/sandbox/include/asm/state.h
@@ -97,6 +97,7 @@
bool autoboot_keyed; /* Use keyed-autoboot feature */
bool disable_eth; /* Disable Ethernet devices */
bool disable_sf_bootdevs; /* Don't bind SPI flash bootdevs */
+ bool upl; /* Enable Universal Payload (UPL) */
/* Pointer to information for each SPI bus/cs */
struct sandbox_spi_info spi[CONFIG_SANDBOX_SPI_MAX_BUS]
diff --git a/arch/x86/cpu/i386/cpu.c b/arch/x86/cpu/i386/cpu.c
index db2727d..934e98a 100644
--- a/arch/x86/cpu/i386/cpu.c
+++ b/arch/x86/cpu/i386/cpu.c
@@ -412,12 +412,6 @@
return 32;
}
-/* Don't allow PCI region 3 to use memory in the 2-4GB memory hole */
-static void setup_pci_ram_top(void)
-{
- gd_set_pci_ram_top(0x80000000U);
-}
-
static void setup_mtrr(void)
{
u64 mtrr_cap;
@@ -469,7 +463,6 @@
setup_cpu_features();
setup_identity();
setup_mtrr();
- setup_pci_ram_top();
/* Set up the i8254 timer if required */
if (IS_ENABLED(CONFIG_I8254_TIMER))
@@ -483,7 +476,6 @@
long addr;
setup_identity();
- setup_pci_ram_top();
addr = locate_coreboot_table();
if (addr >= 0) {
gd->arch.coreboot_table = addr;
diff --git a/arch/x86/cpu/intel_common/cpu_from_spl.c b/arch/x86/cpu/intel_common/cpu_from_spl.c
index 48b2ef2..5aad2ae 100644
--- a/arch/x86/cpu/intel_common/cpu_from_spl.c
+++ b/arch/x86/cpu/intel_common/cpu_from_spl.c
@@ -24,9 +24,7 @@
int ret;
#if CONFIG_IS_ENABLED(HANDOFF) && IS_ENABLED(CONFIG_USE_HOB)
- struct spl_handoff *ho = gd->spl_handoff;
-
- gd->arch.hob_list = ho->arch.hob_list;
+ gd->arch.hob_list = handoff_get();
#endif
ret = x86_cpu_reinit_f();
diff --git a/arch/x86/cpu/ivybridge/cpu.c b/arch/x86/cpu/ivybridge/cpu.c
index d71ab0a..05691a3 100644
--- a/arch/x86/cpu/ivybridge/cpu.c
+++ b/arch/x86/cpu/ivybridge/cpu.c
@@ -55,7 +55,6 @@
static int ivybridge_cpu_init(void)
{
- struct pci_controller *hose;
struct udevice *bus, *dev;
int ret;
@@ -65,10 +64,6 @@
if (ret)
return ret;
post_code(0x72);
- hose = dev_get_uclass_priv(bus);
-
- /* TODO(sjg@chromium.org): Get rid of gd->hose */
- gd->hose = hose;
ret = uclass_first_device_err(UCLASS_LPC, &dev);
if (ret)
diff --git a/arch/x86/include/asm/posix_types.h b/arch/x86/include/asm/posix_types.h
index dbcea7f..e1ed9bc 100644
--- a/arch/x86/include/asm/posix_types.h
+++ b/arch/x86/include/asm/posix_types.h
@@ -20,11 +20,12 @@
#if defined(__x86_64__)
typedef unsigned long __kernel_size_t;
typedef long __kernel_ssize_t;
+typedef long __kernel_ptrdiff_t;
#else
typedef unsigned int __kernel_size_t;
typedef int __kernel_ssize_t;
-#endif
typedef int __kernel_ptrdiff_t;
+#endif
typedef long __kernel_time_t;
typedef long __kernel_suseconds_t;
typedef long __kernel_clock_t;
diff --git a/arch/x86/lib/fsp/fsp_graphics.c b/arch/x86/lib/fsp/fsp_graphics.c
index 5f77012..ad25020 100644
--- a/arch/x86/lib/fsp/fsp_graphics.c
+++ b/arch/x86/lib/fsp/fsp_graphics.c
@@ -103,7 +103,6 @@
* For IGD, it seems to be always on BAR2.
*/
vesa->phys_base_ptr = dm_pci_read_bar32(dev, 2);
- gd->fb_base = vesa->phys_base_ptr;
ret = vesa_setup_video_priv(vesa, vesa->phys_base_ptr, uc_priv, plat);
if (ret)
diff --git a/arch/x86/lib/fsp2/fsp_dram.c b/arch/x86/lib/fsp2/fsp_dram.c
index 83c6d7b..a50dc98 100644
--- a/arch/x86/lib/fsp2/fsp_dram.c
+++ b/arch/x86/lib/fsp2/fsp_dram.c
@@ -59,7 +59,7 @@
#endif
} else {
#if CONFIG_IS_ENABLED(HANDOFF)
- struct spl_handoff *ho = gd->spl_handoff;
+ struct spl_handoff *ho = handoff_get();
if (!ho) {
log_debug("No SPL handoff found\n");
@@ -82,7 +82,7 @@
return gd->ram_size;
#if CONFIG_IS_ENABLED(HANDOFF)
- struct spl_handoff *ho = gd->spl_handoff;
+ struct spl_handoff *ho = handoff_get();
log_debug("usable_ram_top = %lx\n", ho->arch.usable_ram_top);
diff --git a/board/BuR/brppt1/board.c b/board/BuR/brppt1/board.c
index 192a2fa..80e0ca8 100644
--- a/board/BuR/brppt1/board.c
+++ b/board/BuR/brppt1/board.c
@@ -79,7 +79,7 @@
#define OSC (V_OSCK/1000000)
static const struct dpll_params dpll_ddr3 = { 400, OSC-1, 1, -1, -1, -1, -1};
-void am33xx_spl_board_init(void)
+void spl_board_init(void)
{
int rc;
diff --git a/board/BuR/brsmarc1/board.c b/board/BuR/brsmarc1/board.c
index 2d3f593..bfb6adf 100644
--- a/board/BuR/brsmarc1/board.c
+++ b/board/BuR/brsmarc1/board.c
@@ -72,7 +72,7 @@
#define OSC (V_OSCK / 1000000)
const struct dpll_params dpll_ddr3 = { 400, OSC - 1, 1, -1, -1, -1, -1};
-void am33xx_spl_board_init(void)
+void spl_board_init(void)
{
struct cm_perpll *const cmper = (struct cm_perpll *)CM_PER;
struct cm_wkuppll *const cmwkup = (struct cm_wkuppll *)CM_WKUP;
diff --git a/board/BuR/brxre1/board.c b/board/BuR/brxre1/board.c
index b9b595c..510d2af 100644
--- a/board/BuR/brxre1/board.c
+++ b/board/BuR/brxre1/board.c
@@ -79,7 +79,7 @@
#define OSC (V_OSCK / 1000000)
const struct dpll_params dpll_ddr3 = { 400, OSC - 1, 1, -1, -1, -1, -1};
-void am33xx_spl_board_init(void)
+void spl_board_init(void)
{
int rc;
diff --git a/board/advantech/imx8mp_rsb3720a1/imx8mp_rsb3720a1.c b/board/advantech/imx8mp_rsb3720a1/imx8mp_rsb3720a1.c
index cc3a662..b9f4700 100644
--- a/board/advantech/imx8mp_rsb3720a1/imx8mp_rsb3720a1.c
+++ b/board/advantech/imx8mp_rsb3720a1/imx8mp_rsb3720a1.c
@@ -189,7 +189,7 @@
return 0;
}
-#ifdef CONFIG_SPL_MMC
+#ifdef CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR
#define UBOOT_RAW_SECTOR_OFFSET 0x40
unsigned long board_spl_mmc_get_uboot_raw_sector(struct mmc *mmc,
unsigned long raw_sector)
@@ -203,4 +203,4 @@
return CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR;
}
}
-#endif /* CONFIG_SPL_MMC */
+#endif /* CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR */
diff --git a/board/armltd/corstone1000/MAINTAINERS b/board/armltd/corstone1000/MAINTAINERS
index 1cc9aaa..ede4b00 100644
--- a/board/armltd/corstone1000/MAINTAINERS
+++ b/board/armltd/corstone1000/MAINTAINERS
@@ -1,6 +1,6 @@
CORSTONE1000 BOARD
M: Abdellatif El Khlifi <abdellatif.elkhlifi@arm.com>
-M: Xueliang Zhong <xueliang.zhong@arm.com>
+M: Hugues Kamba Mpiana <hugues.kambampiana@arm.com>
S: Maintained
F: board/armltd/corstone1000/
F: include/configs/corstone1000.h
diff --git a/board/bosch/guardian/board.c b/board/bosch/guardian/board.c
index 41d7567..33ba7a7 100644
--- a/board/bosch/guardian/board.c
+++ b/board/bosch/guardian/board.c
@@ -75,7 +75,7 @@
const struct dpll_params dpll_ddr = {
400, OSC - 1, 1, -1, -1, -1, -1};
-void am33xx_spl_board_init(void)
+void spl_board_init(void)
{
int mpu_vdd;
int usb_cur_lim;
diff --git a/board/bosch/shc/board.c b/board/bosch/shc/board.c
index ab68874..1f9dc2d 100644
--- a/board/bosch/shc/board.c
+++ b/board/bosch/shc/board.c
@@ -34,6 +34,7 @@
#include <asm/emif.h>
#include <asm/gpio.h>
#include <i2c.h>
+#include <i2c_eeprom.h>
#include <miiphy.h>
#include <cpsw.h>
#include <linux/delay.h>
@@ -51,21 +52,21 @@
/*
* Read header information from EEPROM into global structure.
*/
-#define EEPROM_ADDR 0x50
static int read_eeprom(void)
{
+ struct udevice *dev;
+ int ret;
+
/* Check if baseboard eeprom is available */
- if (i2c_probe(EEPROM_ADDR)) {
- puts("Could not probe the EEPROM; something fundamentally wrong on the I2C bus.\n");
- return -ENODEV;
+ ret = uclass_first_device_err(UCLASS_I2C_EEPROM, &dev);
+ if (ret) {
+ puts("Could not find EEPROM.\n");
+ return ret;
}
- /* read the eeprom using i2c */
- if (i2c_read(EEPROM_ADDR, 0, 2, (uchar *)&header,
- sizeof(header))) {
- puts("Could not read the EEPROM; something fundamentally wrong on the I2C bus.\n");
- return -EIO;
- }
+ ret = i2c_eeprom_read(dev, 0, (uint8_t *)&header, sizeof(header));
+ if (ret)
+ return ret;
if (header.magic != HDR_MAGIC) {
printf("Incorrect magic number (0x%x) in EEPROM\n",
@@ -310,7 +311,7 @@
const struct dpll_params dpll_mpu_shc_opp100 = {
99, MPUPLL_N, 1, -1, -1, -1, -1};
-void am33xx_spl_board_init(void)
+void spl_board_init(void)
{
int sil_rev;
int mpu_vdd;
@@ -445,7 +446,6 @@
#if defined(CONFIG_HW_WATCHDOG)
hw_watchdog_init();
#endif
- i2c_init(CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE);
if (read_eeprom() < 0)
puts("EEPROM Content Invalid.\n");
diff --git a/board/compulab/cm_fx6/cm_fx6.c b/board/compulab/cm_fx6/cm_fx6.c
index c6d33c3..40047cf 100644
--- a/board/compulab/cm_fx6/cm_fx6.c
+++ b/board/compulab/cm_fx6/cm_fx6.c
@@ -14,6 +14,7 @@
#include <env.h>
#include <fsl_esdhc_imx.h>
#include <init.h>
+#include <i2c.h>
#include <miiphy.h>
#include <mtd_node.h>
#include <net.h>
@@ -256,7 +257,7 @@
{
int ret;
- ret = setup_i2c(busnum, CONFIG_SYS_I2C_SPEED, 0x7f, pads);
+ ret = setup_i2c(busnum, I2C_SPEED_STANDARD_RATE, 0x7f, pads);
if (ret)
printf("Warning: I2C%d setup failed: %d\n", busnum, ret);
diff --git a/board/compulab/cm_t43/cm_t43.c b/board/compulab/cm_t43/cm_t43.c
index 1815819..983991e 100644
--- a/board/compulab/cm_t43/cm_t43.c
+++ b/board/compulab/cm_t43/cm_t43.c
@@ -48,8 +48,6 @@
gd->bd->bi_boot_params = CFG_SYS_SDRAM_BASE + 0x100;
gpmc_init();
set_i2c_pin_mux();
- i2c_init(CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE);
- i2c_probe(TPS65218_CHIP_PM);
return 0;
}
diff --git a/board/compulab/common/Makefile b/board/compulab/common/Makefile
index 7c8226e..c7b2237 100644
--- a/board/compulab/common/Makefile
+++ b/board/compulab/common/Makefile
@@ -4,6 +4,12 @@
#
# Author: Igor Grinberg <grinberg@compulab.co.il>
+CL_EEPROM=y
+
+ifdef CONFIG_TARGET_TRIMSLICE
+CL_EEPROM=
+endif
+
obj-y += common.o
-obj-$(CONFIG_$(SPL_)SYS_I2C_LEGACY) += eeprom.o
+obj-$(CL_EEPROM) += eeprom.o
obj-$(CONFIG_SMC911X) += omap3_smc911x.o
diff --git a/board/compulab/common/eeprom.c b/board/compulab/common/eeprom.c
index efdaf34..1b12d09 100644
--- a/board/compulab/common/eeprom.c
+++ b/board/compulab/common/eeprom.c
@@ -34,19 +34,15 @@
static int cl_eeprom_read(uint offset, uchar *buf, int len)
{
+ struct udevice *eeprom;
int res;
- unsigned int current_i2c_bus = i2c_get_bus_num();
- res = i2c_set_bus_num(cl_eeprom_bus);
- if (res < 0)
+ res = i2c_get_chip_for_busnum(cl_eeprom_bus, CONFIG_SYS_I2C_EEPROM_ADDR,
+ CONFIG_SYS_I2C_EEPROM_ADDR_LEN, &eeprom);
+ if (res)
return res;
- res = i2c_read(CONFIG_SYS_I2C_EEPROM_ADDR, offset,
- CONFIG_SYS_I2C_EEPROM_ADDR_LEN, buf, len);
-
- i2c_set_bus_num(current_i2c_bus);
-
- return res;
+ return dm_i2c_read(eeprom, offset, (uint8_t *)buf, len);
}
static int cl_eeprom_setup(uint eeprom_bus)
diff --git a/board/compulab/common/eeprom.h b/board/compulab/common/eeprom.h
index 9bd7604..0a44926 100644
--- a/board/compulab/common/eeprom.h
+++ b/board/compulab/common/eeprom.h
@@ -10,7 +10,7 @@
#define _EEPROM_
#include <errno.h>
-#if CONFIG_IS_ENABLED(SYS_I2C_LEGACY)
+#if !CONFIG_IS_ENABLED(TARGET_TRIMSLICE)
int cl_eeprom_read_mac_addr(uchar *buf, uint eeprom_bus);
u32 cl_eeprom_get_board_rev(uint eeprom_bus);
int cl_eeprom_get_product_name(uchar *buf, uint eeprom_bus);
diff --git a/board/data_modul/imx8mp_edm_sbc/spl.c b/board/data_modul/imx8mp_edm_sbc/spl.c
index c193589..f81b727 100644
--- a/board/data_modul/imx8mp_edm_sbc/spl.c
+++ b/board/data_modul/imx8mp_edm_sbc/spl.c
@@ -100,7 +100,10 @@
if (boot_dev_spl == MMC3_BOOT) /* eMMC */
return BOOT_DEVICE_MMC2;
- return BOOT_DEVICE_MMC1; /* SD */
+ if (boot_dev_spl == SD2_BOOT) /* SD */
+ return BOOT_DEVICE_MMC1;
+
+ return BOOT_DEVICE_BOOTROM; /* USB SDPS */
}
void board_boot_order(u32 *spl_boot_list)
diff --git a/board/eets/pdu001/board.c b/board/eets/pdu001/board.c
index 2ad256f..00f9a5e 100644
--- a/board/eets/pdu001/board.c
+++ b/board/eets/pdu001/board.c
@@ -56,10 +56,10 @@
* boot device save register
* -------------------------
* The boot device can be quired by 'spl_boot_device()' in
- * 'am33xx_spl_board_init'. However it can't be saved in the u-boot
+ * 'spl_board_init'. However it can't be saved in the u-boot
* environment here. In turn 'spl_boot_device' can't be called in
* 'board_late_init' which allows writing to u-boot environment.
- * To get the boot device from 'am33xx_spl_board_init' to
+ * To get the boot device from 'spl_board_init' to
* 'board_late_init' we therefore use a scratch register from the RTC.
*/
#define CFG_SYS_RTC_SCRATCH0 0x60
@@ -192,7 +192,7 @@
const struct dpll_params dpll_ddr_bone_black = {
400, OSC - 1, 1, -1, -1, -1, -1};
-void am33xx_spl_board_init(void)
+void spl_board_init(void)
{
struct ctrl_dev *cdev = (struct ctrl_dev *)CTRL_DEVICE_BASE;
diff --git a/board/freescale/ls2080ardb/eth_ls2080rdb.c b/board/freescale/ls2080ardb/eth_ls2080rdb.c
index 44d9782..7fc4fec 100644
--- a/board/freescale/ls2080ardb/eth_ls2080rdb.c
+++ b/board/freescale/ls2080ardb/eth_ls2080rdb.c
@@ -12,7 +12,7 @@
int board_eth_init(struct bd_info *bis)
{
-#ifdef CONFIG_PHY_AQUANTIA
+#if defined(CONFIG_PHY_AQUANTIA) && !defined(CONFIG_SPL_BUILD)
/*
* Export functions to be used by AQ firmware
* upload application
diff --git a/board/friendlyarm/nanopi2/board.c b/board/friendlyarm/nanopi2/board.c
index c8cbc5a..b32dfc6 100644
--- a/board/friendlyarm/nanopi2/board.c
+++ b/board/friendlyarm/nanopi2/board.c
@@ -11,6 +11,7 @@
#ifdef CONFIG_PWM_NX
#include <pwm.h>
#endif
+#include <video.h>
#include <asm/global_data.h>
#include <asm/io.h>
@@ -492,12 +493,8 @@
ARRAY_SIZE(splash_locations));
}
- if (!err) {
- char addr[64];
-
- sprintf(addr, "0x%lx", gd->fb_base);
- env_set("fb_addr", addr);
- }
+ if (!err)
+ env_set_hex("fb_addr", video_get_fb());
return err;
}
diff --git a/board/grinn/chiliboard/board.c b/board/grinn/chiliboard/board.c
index 8313b37..e0eb8aa 100644
--- a/board/grinn/chiliboard/board.c
+++ b/board/grinn/chiliboard/board.c
@@ -80,7 +80,7 @@
enable_board_pin_mux();
}
-void am33xx_spl_board_init(void)
+void spl_board_init(void)
{
chilisom_spl_board_init();
}
diff --git a/board/kosagi/novena/novena.c b/board/kosagi/novena/novena.c
index 3220727..f65551e 100644
--- a/board/kosagi/novena/novena.c
+++ b/board/kosagi/novena/novena.c
@@ -137,23 +137,23 @@
int misc_init_r(void)
{
struct novena_eeprom_data data;
- uchar *datap = (uchar *)&data;
+ uint8_t *datap = (uint8_t *)&data;
const char *signature = "Novena";
+ struct udevice *eeprom;
int ret;
/* If 'ethaddr' is already set, do nothing. */
if (env_get("ethaddr"))
return 0;
- /* EEPROM is at bus 2. */
- ret = i2c_set_bus_num(2);
+ /* EEPROM is at bus 2, address 0x56 */
+ ret = i2c_get_chip_for_busnum(2, 0x56, 1, &eeprom);
if (ret) {
puts("Cannot select EEPROM I2C bus.\n");
return 0;
}
- /* EEPROM is at address 0x56. */
- ret = eeprom_read(0x56, 0, datap, sizeof(data));
+ ret = dm_i2c_read(eeprom, 0, datap, sizeof(data));
if (ret) {
puts("Cannot read I2C EEPROM.\n");
return 0;
diff --git a/board/kosagi/novena/video.c b/board/kosagi/novena/video.c
index be5a737..67f9843 100644
--- a/board/kosagi/novena/video.c
+++ b/board/kosagi/novena/video.c
@@ -58,28 +58,29 @@
#define IT6521_RETRY_MAX 20
+static struct udevice *it6251_chip;
+static struct udevice *it6251_lvds;
+
static int it6251_is_stable(void)
{
- const unsigned int caddr = NOVENA_IT6251_CHIPADDR;
- const unsigned int laddr = NOVENA_IT6251_LVDSADDR;
int status;
int clkcnt;
int rpclkcnt;
int refstate;
- rpclkcnt = (i2c_reg_read(caddr, 0x13) & 0xff) |
- ((i2c_reg_read(caddr, 0x14) << 8) & 0x0f00);
+ rpclkcnt = (dm_i2c_reg_read(it6251_chip, 0x13) & 0xff) |
+ ((dm_i2c_reg_read(it6251_chip, 0x14) << 8) & 0x0f00);
debug("RPCLKCnt: %d\n", rpclkcnt);
- status = i2c_reg_read(caddr, IT6251_SYSTEM_STATUS);
+ status = dm_i2c_reg_read(it6251_chip, IT6251_SYSTEM_STATUS);
debug("System status: 0x%02x\n", status);
- clkcnt = (i2c_reg_read(laddr, IT6251_REG_PCLK_CNT_LOW) & 0xff) |
- ((i2c_reg_read(laddr, IT6251_REG_PCLK_CNT_HIGH) << 8) &
+ clkcnt = (dm_i2c_reg_read(it6251_lvds, IT6251_REG_PCLK_CNT_LOW) & 0xff) |
+ ((dm_i2c_reg_read(it6251_lvds, IT6251_REG_PCLK_CNT_HIGH) << 8) &
0x0f00);
debug("Clock: 0x%02x\n", clkcnt);
- refstate = i2c_reg_read(laddr, IT6251_REF_STATE);
+ refstate = dm_i2c_reg_read(it6251_lvds, IT6251_REF_STATE);
debug("Ref Link State: 0x%02x\n", refstate);
if ((refstate & 0x1f) != 0)
@@ -97,16 +98,14 @@
static int it6251_ready(void)
{
- const unsigned int caddr = NOVENA_IT6251_CHIPADDR;
-
/* Test if the IT6251 came out of reset by reading ID regs. */
- if (i2c_reg_read(caddr, IT6251_VENDOR_ID_LOW) != 0x15)
+ if (dm_i2c_reg_read(it6251_chip, IT6251_VENDOR_ID_LOW) != 0x15)
return 0;
- if (i2c_reg_read(caddr, IT6251_VENDOR_ID_HIGH) != 0xca)
+ if (dm_i2c_reg_read(it6251_chip, IT6251_VENDOR_ID_HIGH) != 0xca)
return 0;
- if (i2c_reg_read(caddr, IT6251_DEVICE_ID_LOW) != 0x51)
+ if (dm_i2c_reg_read(it6251_chip, IT6251_DEVICE_ID_LOW) != 0x51)
return 0;
- if (i2c_reg_read(caddr, IT6251_DEVICE_ID_HIGH) != 0x62)
+ if (dm_i2c_reg_read(it6251_chip, IT6251_DEVICE_ID_HIGH) != 0x62)
return 0;
return 1;
@@ -114,116 +113,112 @@
static void it6251_program_regs(void)
{
- const unsigned int caddr = NOVENA_IT6251_CHIPADDR;
- const unsigned int laddr = NOVENA_IT6251_LVDSADDR;
-
- i2c_reg_write(caddr, 0x05, 0x00);
+ dm_i2c_reg_write(it6251_chip, 0x05, 0x00);
mdelay(1);
/* set LVDSRX address, and enable */
- i2c_reg_write(caddr, 0xfd, 0xbc);
- i2c_reg_write(caddr, 0xfe, 0x01);
+ dm_i2c_reg_write(it6251_chip, 0xfd, 0xbc);
+ dm_i2c_reg_write(it6251_chip, 0xfe, 0x01);
/*
* LVDSRX
*/
/* This write always fails, because the chip goes into reset */
/* reset LVDSRX */
- i2c_reg_write(laddr, 0x05, 0xff);
- i2c_reg_write(laddr, 0x05, 0x00);
+ dm_i2c_reg_write(it6251_lvds, 0x05, 0xff);
+ dm_i2c_reg_write(it6251_lvds, 0x05, 0x00);
/* reset LVDSRX PLL */
- i2c_reg_write(laddr, 0x3b, 0x42);
- i2c_reg_write(laddr, 0x3b, 0x43);
+ dm_i2c_reg_write(it6251_lvds, 0x3b, 0x42);
+ dm_i2c_reg_write(it6251_lvds, 0x3b, 0x43);
/* something with SSC PLL */
- i2c_reg_write(laddr, 0x3c, 0x08);
+ dm_i2c_reg_write(it6251_lvds, 0x3c, 0x08);
/* don't swap links, but writing reserved registers */
- i2c_reg_write(laddr, 0x0b, 0x88);
+ dm_i2c_reg_write(it6251_lvds, 0x0b, 0x88);
/* JEIDA, 8-bit depth 0x11, orig 0x42 */
- i2c_reg_write(laddr, 0x2c, 0x01);
+ dm_i2c_reg_write(it6251_lvds, 0x2c, 0x01);
/* "reserved" */
- i2c_reg_write(laddr, 0x32, 0x04);
+ dm_i2c_reg_write(it6251_lvds, 0x32, 0x04);
/* "reserved" */
- i2c_reg_write(laddr, 0x35, 0xe0);
+ dm_i2c_reg_write(it6251_lvds, 0x35, 0xe0);
/* "reserved" + clock delay */
- i2c_reg_write(laddr, 0x2b, 0x24);
+ dm_i2c_reg_write(it6251_lvds, 0x2b, 0x24);
/* reset LVDSRX pix clock */
- i2c_reg_write(laddr, 0x05, 0x02);
- i2c_reg_write(laddr, 0x05, 0x00);
+ dm_i2c_reg_write(it6251_lvds, 0x05, 0x02);
+ dm_i2c_reg_write(it6251_lvds, 0x05, 0x00);
/*
* DPTX
*/
/* set for two lane mode, normal op, no swapping, no downspread */
- i2c_reg_write(caddr, 0x16, 0x02);
+ dm_i2c_reg_write(it6251_chip, 0x16, 0x02);
/* some AUX channel EDID magic */
- i2c_reg_write(caddr, 0x23, 0x40);
+ dm_i2c_reg_write(it6251_chip, 0x23, 0x40);
/* power down lanes 3-0 */
- i2c_reg_write(caddr, 0x5c, 0xf3);
+ dm_i2c_reg_write(it6251_chip, 0x5c, 0xf3);
/* enable DP scrambling, change EQ CR phase */
- i2c_reg_write(caddr, 0x5f, 0x06);
+ dm_i2c_reg_write(it6251_chip, 0x5f, 0x06);
/* color mode RGB, pclk/2 */
- i2c_reg_write(caddr, 0x60, 0x02);
+ dm_i2c_reg_write(it6251_chip, 0x60, 0x02);
/* dual pixel input mode, no EO swap, no RGB swap */
- i2c_reg_write(caddr, 0x61, 0x04);
+ dm_i2c_reg_write(it6251_chip, 0x61, 0x04);
/* M444B24 video format */
- i2c_reg_write(caddr, 0x62, 0x01);
+ dm_i2c_reg_write(it6251_chip, 0x62, 0x01);
/* vesa range / not interlace / vsync high / hsync high */
- i2c_reg_write(caddr, 0xa0, 0x0F);
+ dm_i2c_reg_write(it6251_chip, 0xa0, 0x0F);
/* hpd event timer set to 1.6-ish ms */
- i2c_reg_write(caddr, 0xc9, 0xf5);
+ dm_i2c_reg_write(it6251_chip, 0xc9, 0xf5);
/* more reserved magic */
- i2c_reg_write(caddr, 0xca, 0x4d);
- i2c_reg_write(caddr, 0xcb, 0x37);
+ dm_i2c_reg_write(it6251_chip, 0xca, 0x4d);
+ dm_i2c_reg_write(it6251_chip, 0xcb, 0x37);
/* enhanced framing mode, auto video fifo reset, video mute disable */
- i2c_reg_write(caddr, 0xd3, 0x03);
+ dm_i2c_reg_write(it6251_chip, 0xd3, 0x03);
/* "vidstmp" and some reserved stuff */
- i2c_reg_write(caddr, 0xd4, 0x45);
+ dm_i2c_reg_write(it6251_chip, 0xd4, 0x45);
/* queue number -- reserved */
- i2c_reg_write(caddr, 0xe7, 0xa0);
+ dm_i2c_reg_write(it6251_chip, 0xe7, 0xa0);
/* info frame packets and reserved */
- i2c_reg_write(caddr, 0xe8, 0x33);
+ dm_i2c_reg_write(it6251_chip, 0xe8, 0x33);
/* more AVI stuff */
- i2c_reg_write(caddr, 0xec, 0x00);
+ dm_i2c_reg_write(it6251_chip, 0xec, 0x00);
/* select PC master reg for aux channel? */
- i2c_reg_write(caddr, 0x23, 0x42);
+ dm_i2c_reg_write(it6251_chip, 0x23, 0x42);
/* send PC request commands */
- i2c_reg_write(caddr, 0x24, 0x00);
- i2c_reg_write(caddr, 0x25, 0x00);
- i2c_reg_write(caddr, 0x26, 0x00);
+ dm_i2c_reg_write(it6251_chip, 0x24, 0x00);
+ dm_i2c_reg_write(it6251_chip, 0x25, 0x00);
+ dm_i2c_reg_write(it6251_chip, 0x26, 0x00);
/* native aux read */
- i2c_reg_write(caddr, 0x2b, 0x00);
+ dm_i2c_reg_write(it6251_chip, 0x2b, 0x00);
/* back to internal */
- i2c_reg_write(caddr, 0x23, 0x40);
+ dm_i2c_reg_write(it6251_chip, 0x23, 0x40);
/* voltage swing level 3 */
- i2c_reg_write(caddr, 0x19, 0xff);
+ dm_i2c_reg_write(it6251_chip, 0x19, 0xff);
/* pre-emphasis level 3 */
- i2c_reg_write(caddr, 0x1a, 0xff);
+ dm_i2c_reg_write(it6251_chip, 0x1a, 0xff);
/* start link training */
- i2c_reg_write(caddr, 0x17, 0x01);
+ dm_i2c_reg_write(it6251_chip, 0x17, 0x01);
}
static int it6251_init(void)
{
- const unsigned int caddr = NOVENA_IT6251_CHIPADDR;
int reg;
int tries, retries = 0;
@@ -233,7 +228,7 @@
/* Wait for video stable. */
for (tries = 0; tries < 100; tries++) {
- reg = i2c_reg_read(caddr, 0x17);
+ reg = dm_i2c_reg_read(it6251_chip, 0x17);
/* Test Link CFG, STS, LCS read done. */
if ((reg & 0xe0) != 0xe0) {
/* Not yet, wait a bit more. */
@@ -285,10 +280,14 @@
enable_lvds(dev);
- ret = i2c_set_bus_num(NOVENA_IT6251_I2C_BUS);
- if (ret) {
- puts("Cannot select IT6251 I2C bus.\n");
- return 0;
+ if (!it6251_chip) {
+ ret = i2c_get_chip_for_busnum(NOVENA_IT6251_I2C_BUS,
+ NOVENA_IT6251_CHIPADDR,
+ 1, &it6251_chip);
+ if (ret) {
+ puts("Cannot select IT6251 I2C bus.\n");
+ return 0;
+ }
}
/* Wait up-to ~250 mS for the LVDS to come up. */
@@ -435,9 +434,20 @@
{
int ret;
+ if (!it6251_chip) {
+ ret = i2c_get_chip_for_busnum(NOVENA_IT6251_I2C_BUS,
+ NOVENA_IT6251_CHIPADDR,
+ 1, &it6251_chip);
+ if (ret) {
+ puts("Cannot select LVDS-to-eDP I2C bus.\n");
+ return;
+ }
+ }
+
- ret = i2c_set_bus_num(NOVENA_IT6251_I2C_BUS);
+ ret = i2c_get_chip_for_busnum(NOVENA_IT6251_I2C_BUS,
+ NOVENA_IT6251_LVDSADDR, 1, &it6251_lvds);
if (ret) {
- puts("Cannot select LVDS-to-eDP I2C bus.\n");
+ puts("Cannot find IT6251 LVDS bus.\n");
return;
}
diff --git a/board/lg/sniper/sniper.c b/board/lg/sniper/sniper.c
index 88d5d08..9d0959f 100644
--- a/board/lg/sniper/sniper.c
+++ b/board/lg/sniper/sniper.c
@@ -14,11 +14,9 @@
#include <linux/ctype.h>
#include <linux/usb/musb.h>
#include <asm/omap_musb.h>
-#include <asm/arch/mmc_host_def.h>
#include <asm/arch/sys_proto.h>
#include <asm/arch/mem.h>
#include <asm/io.h>
-#include <ns16550.h>
#include <twl4030.h>
#include "sniper.h"
@@ -30,18 +28,6 @@
.nand_string = "MMC"
};
-static const struct ns16550_plat serial_omap_plat = {
- .base = OMAP34XX_UART3,
- .reg_shift = 2,
- .clock = V_NS16550_CLK,
- .fcr = UART_FCR_DEFVAL,
-};
-
-U_BOOT_DRVINFO(sniper_serial) = {
- .name = "ns16550_serial",
- .plat = &serial_omap_plat
-};
-
#if defined(CONFIG_USB_MUSB_HOST) || defined(CONFIG_USB_MUSB_GADGET)
static struct musb_hdrc_config musb_config = {
.multipoint = 1,
@@ -77,6 +63,11 @@
timings->rfr_ctrl = SDP_3430_SDRC_RFR_CTRL_200MHz;
timings->mr = MICRON_V_MR_165;
}
+
+void spl_board_init(void)
+{
+ twl4030_power_mmc_init(1);
+}
#endif
int board_init(void)
@@ -188,13 +179,3 @@
return omap_reboot_mode_store("b");
}
-
-int board_mmc_init(struct bd_info *bis)
-{
- return omap_mmc_init(1, 0, 0, -1, -1);
-}
-
-void board_mmc_power_init(void)
-{
- twl4030_power_mmc_init(1);
-}
diff --git a/board/phytec/phycore_imx8mp/phycore_imx8mp.env b/board/phytec/phycore_imx8mp/phycore_imx8mp.env
index f8f878e..889464e 100644
--- a/board/phytec/phycore_imx8mp/phycore_imx8mp.env
+++ b/board/phytec/phycore_imx8mp/phycore_imx8mp.env
@@ -30,7 +30,7 @@
loadfdt=fatload mmc ${mmcdev}:${mmcpart} ${fdt_addr_r} ${fdtfile}
loadimage=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${image}
mmcargs=
- setenv bootargs console=${console}
+ setenv bootargs ${mcore_clk} console=${console}
root=/dev/mmcblk${mmcdev}p${mmcroot} ${raucargs} rootwait rw
mmcautodetect=yes
mmcboot=
@@ -51,7 +51,7 @@
mmcpart=1
mmcroot=2
netargs=
- setenv bootargs console=${console} root=/dev/nfs ip=dhcp
+ setenv bootargs ${mcore_clk} console=${console} root=/dev/nfs ip=dhcp
nfsroot=${serverip}:${nfsroot},v3,tcp
netboot=
echo Booting from net ...;
@@ -74,4 +74,5 @@
echo WARN: Cannot load the DT;
fi;
nfsroot=/srv/nfs
+prepare_mcore=setenv mcore_clk clk-imx8mp.mcore_booted
sd_dev=1
diff --git a/board/ronetix/pm9263/pm9263.c b/board/ronetix/pm9263/pm9263.c
index 1de1bd6..8125f06 100644
--- a/board/ronetix/pm9263/pm9263.c
+++ b/board/ronetix/pm9263/pm9263.c
@@ -9,6 +9,7 @@
#include <config.h>
#include <init.h>
+#include <video.h>
#include <asm/global_data.h>
#include <linux/sizes.h>
#include <asm/io.h>
@@ -110,11 +111,12 @@
#ifdef CONFIG_DISPLAY_BOARDINFO
int checkboard (void)
{
+ ulong fb_base = video_get_fb();
char *ss;
printf ("Board : Ronetix PM9263\n");
- switch (gd->fb_base) {
+ switch (fb_base) {
case PHYS_PSRAM:
ss = "(PSRAM)";
break;
@@ -127,7 +129,7 @@
ss = "";
break;
}
- printf("Video memory : 0x%08lX %s\n", gd->fb_base, ss );
+ printf("Video memory : 0x%08lX %s\n", fb_base, ss);
printf ("\n");
return 0;
diff --git a/board/siemens/common/board_am335x.c b/board/siemens/common/board_am335x.c
index 2a72760..e6537b0 100644
--- a/board/siemens/common/board_am335x.c
+++ b/board/siemens/common/board_am335x.c
@@ -36,7 +36,7 @@
/* enable early the console */
gd->baudrate = CONFIG_BAUDRATE;
serial_init();
- gd->have_console = 1;
+ gd->flags |= GD_FLG_HAVE_CONSOLE;
siemens_ee_setup();
if (draco_read_eeprom() < 0)
diff --git a/board/softing/vining_2000/vining_2000.c b/board/softing/vining_2000/vining_2000.c
index a0dbf97..bd430cf 100644
--- a/board/softing/vining_2000/vining_2000.c
+++ b/board/softing/vining_2000/vining_2000.c
@@ -18,7 +18,6 @@
#include <asm/gpio.h>
#include <asm/mach-imx/iomux-v3.h>
#include <asm/io.h>
-#include <asm/mach-imx/mxc_i2c.h>
#include <asm/sections.h>
#include <env.h>
#include <linux/bitops.h>
@@ -27,7 +26,6 @@
#include <config.h>
#include <fsl_esdhc_imx.h>
#include <mmc.h>
-#include <i2c.h>
#include <miiphy.h>
#include <netdev.h>
#include <power/pmic.h>
@@ -53,10 +51,6 @@
PAD_CTL_PUS_100K_DOWN | PAD_CTL_SPEED_HIGH | \
PAD_CTL_SRE_FAST)
-#define I2C_PAD_CTRL (PAD_CTL_HYS | PAD_CTL_PUS_100K_UP | \
- PAD_CTL_PKE | PAD_CTL_ODE | PAD_CTL_SPEED_MED | \
- PAD_CTL_DSE_40ohm)
-
#define USDHC_CLK_PAD_CTRL (PAD_CTL_HYS | PAD_CTL_SPEED_MED | \
PAD_CTL_DSE_80ohm | PAD_CTL_SRE_FAST)
@@ -120,21 +114,6 @@
return ret;
}
-#define PC MUX_PAD_CTRL(I2C_PAD_CTRL)
-/* I2C1 for PMIC */
-static struct i2c_pads_info i2c_pad_info1 = {
- .scl = {
- .i2c_mode = MX6_PAD_GPIO1_IO00__I2C1_SCL | PC,
- .gpio_mode = MX6_PAD_GPIO1_IO00__GPIO1_IO_0 | PC,
- .gp = IMX_GPIO_NR(1, 0),
- },
- .sda = {
- .i2c_mode = MX6_PAD_GPIO1_IO01__I2C1_SDA | PC,
- .gpio_mode = MX6_PAD_GPIO1_IO01__GPIO1_IO_1 | PC,
- .gp = IMX_GPIO_NR(1, 1),
- },
-};
-
static struct pmic *pfuze_init(unsigned char i2cbus)
{
struct pmic *p;
@@ -400,10 +379,6 @@
/* Address of boot parameters */
gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
-#ifdef CONFIG_SYS_I2C_MXC
- setup_i2c(0, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info1);
-#endif
-
return board_net_init();
}
diff --git a/board/tcl/sl50/board.c b/board/tcl/sl50/board.c
index 484b4e2..6c60c70 100644
--- a/board/tcl/sl50/board.c
+++ b/board/tcl/sl50/board.c
@@ -92,7 +92,7 @@
const struct dpll_params dpll_ddr_sl50 = {
400, OSC-1, 1, -1, -1, -1, -1};
-void am33xx_spl_board_init(void)
+void spl_board_init(void)
{
int mpu_vdd;
diff --git a/board/toradex/apalis-imx8/apalis-imx8.c b/board/toradex/apalis-imx8/apalis-imx8.c
index 72d67d9..570bf2a 100644
--- a/board/toradex/apalis-imx8/apalis-imx8.c
+++ b/board/toradex/apalis-imx8/apalis-imx8.c
@@ -290,6 +290,14 @@
return 0;
}
+void reset_cpu(void)
+{
+ sc_pm_reboot(-1, SC_PM_RESET_TYPE_COLD);
+
+ do {
+ } while (1);
+}
+
#if defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP)
int ft_board_setup(void *blob, struct bd_info *bd)
{
diff --git a/board/tq/tqma6/tqma6.c b/board/tq/tqma6/tqma6.c
index 445ce98..40369f0 100644
--- a/board/tq/tqma6/tqma6.c
+++ b/board/tq/tqma6/tqma6.c
@@ -19,33 +19,15 @@
#include <linux/errno.h>
#include <asm/gpio.h>
#include <asm/io.h>
-#include <asm/mach-imx/spi.h>
-#include <fsl_esdhc_imx.h>
#include <linux/libfdt.h>
#include <mmc.h>
#include <power/pfuze100_pmic.h>
#include <power/pmic.h>
-#include <spi_flash.h>
#include "tqma6_bb.h"
DECLARE_GLOBAL_DATA_PTR;
-#define USDHC_CLK_PAD_CTRL (PAD_CTL_PUS_47K_UP | PAD_CTL_SPEED_LOW | \
- PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST | PAD_CTL_HYS)
-
-#define USDHC_PAD_CTRL (PAD_CTL_PUS_47K_UP | PAD_CTL_SPEED_LOW | \
- PAD_CTL_DSE_80ohm | PAD_CTL_SRE_FAST | PAD_CTL_HYS)
-
-#define GPIO_OUT_PAD_CTRL (PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_LOW | \
- PAD_CTL_DSE_40ohm | PAD_CTL_HYS)
-
-#define GPIO_IN_PAD_CTRL (PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_LOW | \
- PAD_CTL_DSE_40ohm | PAD_CTL_HYS)
-
-#define SPI_PAD_CTRL (PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \
- PAD_CTL_DSE_80ohm | PAD_CTL_SRE_FAST | PAD_CTL_HYS)
-
int dram_init(void)
{
gd->ram_size = imx_ddr_size();
@@ -55,114 +37,6 @@
static const uint16_t tqma6_emmc_dsr = 0x0100;
-#ifndef CONFIG_DM_MMC
-/* eMMC on USDHCI3 always present */
-static iomux_v3_cfg_t const tqma6_usdhc3_pads[] = {
- NEW_PAD_CTRL(MX6_PAD_SD3_CLK__SD3_CLK, USDHC_PAD_CTRL),
- NEW_PAD_CTRL(MX6_PAD_SD3_CMD__SD3_CMD, USDHC_PAD_CTRL),
- NEW_PAD_CTRL(MX6_PAD_SD3_DAT0__SD3_DATA0, USDHC_PAD_CTRL),
- NEW_PAD_CTRL(MX6_PAD_SD3_DAT1__SD3_DATA1, USDHC_PAD_CTRL),
- NEW_PAD_CTRL(MX6_PAD_SD3_DAT2__SD3_DATA2, USDHC_PAD_CTRL),
- NEW_PAD_CTRL(MX6_PAD_SD3_DAT3__SD3_DATA3, USDHC_PAD_CTRL),
- NEW_PAD_CTRL(MX6_PAD_SD3_DAT4__SD3_DATA4, USDHC_PAD_CTRL),
- NEW_PAD_CTRL(MX6_PAD_SD3_DAT5__SD3_DATA5, USDHC_PAD_CTRL),
- NEW_PAD_CTRL(MX6_PAD_SD3_DAT6__SD3_DATA6, USDHC_PAD_CTRL),
- NEW_PAD_CTRL(MX6_PAD_SD3_DAT7__SD3_DATA7, USDHC_PAD_CTRL),
- /* eMMC reset */
- NEW_PAD_CTRL(MX6_PAD_SD3_RST__SD3_RESET, GPIO_OUT_PAD_CTRL),
-};
-
-/*
- * According to board_mmc_init() the following map is done:
- * (U-Boot device node) (Physical Port)
- * mmc0 eMMC (SD3) on TQMa6
- * mmc1 .. n optional slots used on baseboard
- */
-struct fsl_esdhc_cfg tqma6_usdhc_cfg = {
- .esdhc_base = USDHC3_BASE_ADDR,
- .max_bus_width = 8,
-};
-
-int board_mmc_getcd(struct mmc *mmc)
-{
- struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv;
- int ret = 0;
-
- if (cfg->esdhc_base == USDHC3_BASE_ADDR)
- /* eMMC/uSDHC3 is always present */
- ret = 1;
- else
- ret = tqma6_bb_board_mmc_getcd(mmc);
-
- return ret;
-}
-
-int board_mmc_getwp(struct mmc *mmc)
-{
- struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv;
- int ret = 0;
-
- if (cfg->esdhc_base == USDHC3_BASE_ADDR)
- /* eMMC/uSDHC3 is always present */
- ret = 0;
- else
- ret = tqma6_bb_board_mmc_getwp(mmc);
-
- return ret;
-}
-
-int board_mmc_init(struct bd_info *bis)
-{
- imx_iomux_v3_setup_multiple_pads(tqma6_usdhc3_pads,
- ARRAY_SIZE(tqma6_usdhc3_pads));
- tqma6_usdhc_cfg.sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK);
- if (fsl_esdhc_initialize(bis, &tqma6_usdhc_cfg)) {
- puts("Warning: failed to initialize eMMC dev\n");
- } else {
- struct mmc *mmc = find_mmc_device(0);
- if (mmc)
- mmc_set_dsr(mmc, tqma6_emmc_dsr);
- }
-
- tqma6_bb_board_mmc_init(bis);
-
- return 0;
-}
-#endif
-
-#ifndef CONFIG_DM_SPI
-static iomux_v3_cfg_t const tqma6_ecspi1_pads[] = {
- /* SS1 */
- NEW_PAD_CTRL(MX6_PAD_EIM_D19__GPIO3_IO19, SPI_PAD_CTRL),
- NEW_PAD_CTRL(MX6_PAD_EIM_D16__ECSPI1_SCLK, SPI_PAD_CTRL),
- NEW_PAD_CTRL(MX6_PAD_EIM_D17__ECSPI1_MISO, SPI_PAD_CTRL),
- NEW_PAD_CTRL(MX6_PAD_EIM_D18__ECSPI1_MOSI, SPI_PAD_CTRL),
-};
-
-#define TQMA6_SF_CS_GPIO IMX_GPIO_NR(3, 19)
-
-static unsigned const tqma6_ecspi1_cs[] = {
- TQMA6_SF_CS_GPIO,
-};
-
-__weak void tqma6_iomuxc_spi(void)
-{
- unsigned i;
-
- for (i = 0; i < ARRAY_SIZE(tqma6_ecspi1_cs); ++i)
- gpio_direction_output(tqma6_ecspi1_cs[i], 1);
- imx_iomux_v3_setup_multiple_pads(tqma6_ecspi1_pads,
- ARRAY_SIZE(tqma6_ecspi1_pads));
-}
-
-#if defined(CONFIG_SF_DEFAULT_BUS) && defined(CONFIG_SF_DEFAULT_CS)
-int board_spi_cs_gpio(unsigned bus, unsigned cs)
-{
- return ((bus == CONFIG_SF_DEFAULT_BUS) &&
- (cs == CONFIG_SF_DEFAULT_CS)) ? TQMA6_SF_CS_GPIO : -1;
-}
-#endif
-#endif
int board_early_init_f(void)
{
diff --git a/board/tq/tqma6/tqma6_mba6.c b/board/tq/tqma6/tqma6_mba6.c
index 877539e..b8f7659 100644
--- a/board/tq/tqma6/tqma6_mba6.c
+++ b/board/tq/tqma6/tqma6_mba6.c
@@ -31,28 +31,6 @@
#include "tqma6_bb.h"
-#define UART_PAD_CTRL (PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \
- PAD_CTL_DSE_80ohm | PAD_CTL_SRE_FAST | PAD_CTL_HYS)
-
-#define USDHC_CLK_PAD_CTRL (PAD_CTL_PUS_47K_UP | PAD_CTL_SPEED_LOW | \
- PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST | PAD_CTL_HYS)
-
-#define USDHC_PAD_CTRL (PAD_CTL_PUS_47K_UP | PAD_CTL_SPEED_LOW | \
- PAD_CTL_DSE_80ohm | PAD_CTL_SRE_FAST | PAD_CTL_HYS)
-
-#define GPIO_OUT_PAD_CTRL (PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_LOW | \
- PAD_CTL_DSE_40ohm | PAD_CTL_HYS)
-
-#define GPIO_IN_PAD_CTRL (PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_LOW | \
- PAD_CTL_DSE_40ohm | PAD_CTL_HYS)
-
-#define SPI_PAD_CTRL (PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \
- PAD_CTL_DSE_80ohm | PAD_CTL_SRE_FAST | PAD_CTL_HYS)
-
-#define I2C_PAD_CTRL (PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \
- PAD_CTL_DSE_80ohm | PAD_CTL_HYS | \
- PAD_CTL_ODE | PAD_CTL_SRE_FAST)
-
#if defined(CONFIG_TQMA6Q)
#define IOMUX_SW_PAD_CTRL_GRP_DDR_TYPE_RGMII 0x02e0790
@@ -89,17 +67,6 @@
(void *)IOMUX_SW_PAD_CTRL_GRP_DDR_TYPE_RGMII);
}
-static iomux_v3_cfg_t const mba6_uart2_pads[] = {
- NEW_PAD_CTRL(MX6_PAD_SD4_DAT4__UART2_RX_DATA, UART_PAD_CTRL),
- NEW_PAD_CTRL(MX6_PAD_SD4_DAT7__UART2_TX_DATA, UART_PAD_CTRL),
-};
-
-static void mba6_setup_iomuxc_uart(void)
-{
- imx_iomux_v3_setup_multiple_pads(mba6_uart2_pads,
- ARRAY_SIZE(mba6_uart2_pads));
-}
-
int board_mmc_get_env_dev(int devno)
{
/*
@@ -159,8 +126,6 @@
int tqma6_bb_board_early_init_f(void)
{
- mba6_setup_iomuxc_uart();
-
return 0;
}
diff --git a/board/vscom/baltos/board.c b/board/vscom/baltos/board.c
index cea25f8..f54f183 100644
--- a/board/vscom/baltos/board.c
+++ b/board/vscom/baltos/board.c
@@ -177,7 +177,7 @@
const struct dpll_params dpll_ddr_baltos = {
400, OSC-1, 1, -1, -1, -1, -1};
-void am33xx_spl_board_init(void)
+void spl_board_init(void)
{
int sil_rev, mpu_vdd;
int freq;
diff --git a/boot/Kconfig b/boot/Kconfig
index 940389d..7ac3457 100644
--- a/boot/Kconfig
+++ b/boot/Kconfig
@@ -745,6 +745,76 @@
This provides a way to try out standard boot on an existing boot flow.
It is not enabled by default to save space.
+config UPL
+ bool "upl - Universal Payload Specification"
+ imply CMD_UPL
+ imply UPL_READ
+ imply UPL_WRITE
+ imply SPL_UPL if SPL
+ help
+ Provides support for UPL payloads and handoff information. U-Boot
+ supports generating and accepting handoff information. The mkimage
+ tool will eventually support creating payloads.
+
+if UPL
+
+config UPL_READ
+ bool "upl - Support reading a Universal Payload handoff"
+ help
+ Provides support for decoding a UPL-format payload into a C structure
+ which can be used elsewhere in U-Boot. This is just the reading
+ implementation, useful for trying it out. See UPL_IN for how
+ to tell U-Boot to actually read it on startup and use it for memory
+ and device information, etc.
+
+config UPL_WRITE
+ bool "upl - Support writing a Universal Payload handoff"
+ help
+ Provides support for encoding a UPL-format payload from a C structure
+ so it can be passed to another program. This is just the writing
+ implementation, useful for trying it out. See SPL_UPL_OUT
+ for how to tell U-Boot SPL to actually write it before jumping to
+ the next phase.
+
+config UPL_IN
+ bool "upl - Read the UPL handoff on startup"
+ select UPL_READ
+ help
+ Read an SPL handoff when U-Boot starts and use it to provide
+ devices, memory layout, etc. required by U-Boot. This allows U-Boot
+ to function as a payload in the meaning of the specification.
+
+if SPL
+
+config SPL_UPL
+ bool "Write a UPL handoff in SPL"
+ imply SPL_UPL_OUT
+ help
+ This tells SPL to write a UPL handoff and pass it to the next phase
+ (e.g. to U-Boot or another program which SPL loads and runs). THis
+ provides information to help that program run correctly and
+ efficiently on the machine.
+
+config SPL_UPL_WRITE
+ bool # upl - Support writing a Universal Payload handoff in SPL
+ select SPL_BLOBLIST
+ help
+ Provides support for encoding a UPL-format payload from a C structure
+ so it can be passed to another program. This is just the writing
+ implementation, useful for trying it out.
+
+config SPL_UPL_OUT
+ bool "upl - Support writing a Universal Payload handoff in SPL"
+ select SPL_UPL_WRITE
+ help
+ Provides support for encoding a UPL-format payload and passing it to
+ the next firmware phase. This allows U-Boot SPL to function as
+ Platform Init in the meaning of the specification.
+
+endif # SPL
+
+endif # UPL
+
endif # BOOTSTD
config LEGACY_IMAGE_FORMAT
diff --git a/boot/Makefile b/boot/Makefile
index dff6f99..f4675d6 100644
--- a/boot/Makefile
+++ b/boot/Makefile
@@ -43,6 +43,10 @@
obj-$(CONFIG_$(SPL_TPL_)OF_LIBFDT) += fdt_support.o
obj-$(CONFIG_$(SPL_TPL_)FDT_SIMPLEFB) += fdt_simplefb.o
+obj-$(CONFIG_$(SPL_TPL_)UPL) += upl_common.o
+obj-$(CONFIG_$(SPL_TPL_)UPL_READ) += upl_read.o
+obj-$(CONFIG_$(SPL_TPL_)UPL_WRITE) += upl_write.o
+
obj-$(CONFIG_$(SPL_TPL_)OF_LIBFDT) += image-fdt.o
obj-$(CONFIG_$(SPL_TPL_)FIT_SIGNATURE) += fdt_region.o
obj-$(CONFIG_$(SPL_TPL_)FIT) += image-fit.o
diff --git a/boot/image-fit.c b/boot/image-fit.c
index 9253f81..7d56f0b 100644
--- a/boot/image-fit.c
+++ b/boot/image-fit.c
@@ -36,6 +36,7 @@
#include <bootm.h>
#include <image.h>
#include <bootstage.h>
+#include <upl.h>
#include <u-boot/crc.h>
/*****************************************************************************/
@@ -2294,6 +2295,8 @@
bootstage_mark(bootstage_id + BOOTSTAGE_SUB_LOAD);
+ upl_add_image(fit, noffset, load, len);
+
*datap = load;
*lenp = len;
if (fit_unamep)
diff --git a/boot/upl_common.c b/boot/upl_common.c
new file mode 100644
index 0000000..3924423
--- /dev/null
+++ b/boot/upl_common.c
@@ -0,0 +1,60 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * UPL handoff command functions
+ *
+ * Copyright 2024 Google LLC
+ * Written by Simon Glass <sjg@chromium.org>
+ */
+
+#define LOG_CATEGORY UCLASS_BOOTSTD
+
+#include <string.h>
+#include <upl.h>
+
+/* Names of bootmodes */
+const char *const bootmode_names[UPLBM_COUNT] = {
+ [UPLBM_FULL] = "full",
+ [UPLBM_MINIMAL] = "minimal",
+ [UPLBM_FAST] = "fast",
+ [UPLBM_DIAG] = "diag",
+ [UPLBM_DEFAULT] = "default",
+ [UPLBM_S2] = "s2",
+ [UPLBM_S3] = "s3",
+ [UPLBM_S4] = "s4",
+ [UPLBM_S5] = "s5",
+ [UPLBM_FACTORY] = "factory",
+ [UPLBM_FLASH] = "flash",
+ [UPLBM_RECOVERY] = "recovery",
+};
+
+/* Names of memory usages */
+const char *const usage_names[UPLUS_COUNT] = {
+ [UPLUS_ACPI_RECLAIM] = "acpi-reclaim",
+ [UPLUS_ACPI_NVS] = "acpi-nvs",
+ [UPLUS_BOOT_CODE] = "boot-code",
+ [UPLUS_BOOT_DATA] = "boot-data",
+ [UPLUS_RUNTIME_CODE] = "runtime-code",
+ [UPLUS_RUNTIME_DATA] = "runtime-data",
+};
+
+/* Names of access types */
+const char *const access_types[UPLUS_COUNT] = {
+ [UPLAT_MMIO] = "mmio",
+ [UPLAT_IO] = "io",
+};
+
+/* Names of graphics formats */
+const char *const graphics_formats[UPLUS_COUNT] = {
+ [UPLGF_ARGB32] = "a8r8g8b8",
+ [UPLGF_ABGR32] = "a8b8g8r8",
+ [UPLGF_ABGR64] = "a16b16g16r16",
+};
+
+void upl_init(struct upl *upl)
+{
+ memset(upl, '\0', sizeof(struct upl));
+ alist_init_struct(&upl->image, struct upl_image);
+ alist_init_struct(&upl->mem, struct upl_mem);
+ alist_init_struct(&upl->memmap, struct upl_memmap);
+ alist_init_struct(&upl->memres, struct upl_memres);
+}
diff --git a/boot/upl_common.h b/boot/upl_common.h
new file mode 100644
index 0000000..cc517dc
--- /dev/null
+++ b/boot/upl_common.h
@@ -0,0 +1,24 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * UPL handoff command functions
+ *
+ * Copyright 2024 Google LLC
+ * Written by Simon Glass <sjg@chromium.org>
+ */
+
+#ifndef __UPL_COMMON_H
+#define __UPL_COMMON_H
+
+/* Names of bootmodes */
+extern const char *const bootmode_names[UPLBM_COUNT];
+
+/* Names of memory usages */
+extern const char *const usage_names[UPLUS_COUNT];
+
+/* Names of access types */
+extern const char *const access_types[UPLUS_COUNT];
+
+/* Names of graphics formats */
+extern const char *const graphics_formats[UPLUS_COUNT];
+
+#endif /* __UPL_COMMON_H */
diff --git a/boot/upl_read.c b/boot/upl_read.c
new file mode 100644
index 0000000..5063897
--- /dev/null
+++ b/boot/upl_read.c
@@ -0,0 +1,588 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * UPL handoff parsing
+ *
+ * Copyright 2024 Google LLC
+ * Written by Simon Glass <sjg@chromium.org>
+ */
+
+#define LOG_CATEGORY UCLASS_BOOTSTD
+
+#include <log.h>
+#include <upl.h>
+#include <dm/ofnode.h>
+#include "upl_common.h"
+
+/**
+ * read_addr() - Read an address
+ *
+ * Reads an address in the correct format, either 32- or 64-bit
+ *
+ * @upl: UPL state
+ * @node: Node to read from
+ * @prop: Property name to read
+ * @addr: Place to put the address
+ * Return: 0 if OK, -ve on error
+ */
+static int read_addr(const struct upl *upl, ofnode node, const char *prop,
+ ulong *addrp)
+{
+ int ret;
+
+ if (upl->addr_cells == 1) {
+ u32 val;
+
+ ret = ofnode_read_u32(node, prop, &val);
+ if (!ret)
+ *addrp = val;
+ } else {
+ u64 val;
+
+ ret = ofnode_read_u64(node, prop, &val);
+ if (!ret)
+ *addrp = val;
+ }
+
+ return ret;
+}
+
+/**
+ * read_size() - Read a size
+ *
+ * Reads a size in the correct format, either 32- or 64-bit
+ *
+ * @upl: UPL state
+ * @node: Node to read from
+ * @prop: Property name to read
+ * @addr: Place to put the size
+ * Return: 0 if OK, -ve on error
+ */
+static int read_size(const struct upl *upl, ofnode node, const char *prop,
+ ulong *sizep)
+{
+ int ret;
+
+ if (upl->size_cells == 1) {
+ u32 val;
+
+ ret = ofnode_read_u32(node, prop, &val);
+ if (!ret)
+ *sizep = val;
+ } else {
+ u64 val;
+
+ ret = ofnode_read_u64(node, prop, &val);
+ if (!ret)
+ *sizep = val;
+ }
+
+ return ret;
+}
+
+/**
+ * ofnode_read_bitmask() - Read a bit mask from a string list
+ *
+ * @node: Node to read from
+ * @prop: Property name to read
+ * @names: Array of names for each bit
+ * @count: Number of array entries
+ * @value: Returns resulting bit-mask value on success
+ * Return: 0 if OK, -EINVAL if a bit number is not defined, -ENOSPC if the
+ * string is too long for the (internal) buffer, -EINVAL if no such property
+ */
+static int ofnode_read_bitmask(ofnode node, const char *prop,
+ const char *const names[], uint count,
+ uint *valuep)
+{
+ const char **list;
+ const char **strp;
+ uint val;
+ uint bit;
+ int ret;
+
+ ret = ofnode_read_string_list(node, prop, &list);
+ if (ret < 0)
+ return log_msg_ret("rea", ret);
+
+ val = 0;
+ for (strp = list; *strp; strp++) {
+ const char *str = *strp;
+ bool found = false;
+
+ for (bit = 0; bit < count; bit++) {
+ if (!strcmp(str, names[bit])) {
+ found = true;
+ break;
+ }
+ }
+ if (found)
+ val |= BIT(bit);
+ else
+ log_warning("%s/%s: Invalid value '%s'\n",
+ ofnode_get_name(node), prop, str);
+ }
+ *valuep = val;
+
+ return 0;
+}
+
+/**
+ * ofnode_read_value() - Read a string value as an int using a lookup
+ *
+ * @node: Node to read from
+ * @prop: Property name to read
+ * @names: Array of names for each int value
+ * @count: Number of array entries
+ * @valuep: Returns int value read
+ * Return: 0 if OK, -EINVAL if a bit number is not defined, -ENOENT if the
+ * property does not exist
+ */
+static int ofnode_read_value(ofnode node, const char *prop,
+ const char *const names[], uint count,
+ uint *valuep)
+{
+ const char *str;
+ int i;
+
+ str = ofnode_read_string(node, prop);
+ if (!str)
+ return log_msg_ret("rd", -ENOENT);
+
+ for (i = 0; i < count; i++) {
+ if (!strcmp(names[i], str)) {
+ *valuep = i;
+ return 0;
+ }
+ }
+
+ log_debug("Unnamed value '%s'\n", str);
+ return log_msg_ret("val", -EINVAL);
+}
+
+static int read_uint(ofnode node, const char *prop, uint *valp)
+{
+ u32 val;
+ int ret;
+
+ ret = ofnode_read_u32(node, prop, &val);
+ if (ret)
+ return ret;
+ *valp = val;
+
+ return 0;
+}
+
+/**
+ * decode_root_props() - Decode root properties from the tree
+ *
+ * @upl: UPL state
+ * @node: Node to decode
+ * Return 0 if OK, -ve on error
+ */
+static int decode_root_props(struct upl *upl, ofnode node)
+{
+ int ret;
+
+ ret = read_uint(node, UPLP_ADDRESS_CELLS, &upl->addr_cells);
+ if (!ret)
+ ret = read_uint(node, UPLP_SIZE_CELLS, &upl->size_cells);
+ if (ret)
+ return log_msg_ret("cel", ret);
+
+ return 0;
+}
+
+/**
+ * decode_root_props() - Decode UPL parameters from the tree
+ *
+ * @upl: UPL state
+ * @node: Node to decode
+ * Return 0 if OK, -ve on error
+ */
+static int decode_upl_params(struct upl *upl, ofnode options)
+{
+ ofnode node;
+ int ret;
+
+ node = ofnode_find_subnode(options, UPLN_UPL_PARAMS);
+ if (!ofnode_valid(node))
+ return log_msg_ret("par", -EINVAL);
+ log_debug("decoding '%s'\n", ofnode_get_name(node));
+
+ ret = read_addr(upl, node, UPLP_SMBIOS, &upl->smbios);
+ if (ret)
+ return log_msg_ret("smb", ret);
+ ret = read_addr(upl, node, UPLP_ACPI, &upl->acpi);
+ if (ret)
+ return log_msg_ret("acp", ret);
+ ret = ofnode_read_bitmask(node, UPLP_BOOTMODE, bootmode_names,
+ UPLBM_COUNT, &upl->bootmode);
+ if (ret)
+ return log_msg_ret("boo", ret);
+ ret = read_uint(node, UPLP_ADDR_WIDTH, &upl->addr_width);
+ if (ret)
+ return log_msg_ret("add", ret);
+ ret = read_uint(node, UPLP_ACPI_NVS_SIZE, &upl->acpi_nvs_size);
+ if (ret)
+ return log_msg_ret("nvs", ret);
+
+ return 0;
+}
+
+/**
+ * decode_upl_images() - Decode /options/upl-image nodes
+ *
+ * @node: /options node in which to look for the node
+ * Return 0 if OK, -ve on error
+ */
+static int decode_upl_images(struct upl *upl, ofnode options)
+{
+ ofnode node, images;
+ int ret;
+
+ images = ofnode_find_subnode(options, UPLN_UPL_IMAGE);
+ if (!ofnode_valid(images))
+ return log_msg_ret("img", -EINVAL);
+ log_debug("decoding '%s'\n", ofnode_get_name(images));
+
+ ret = read_addr(upl, images, UPLP_FIT, &upl->fit);
+ if (!ret)
+ ret = read_uint(images, UPLP_CONF_OFFSET, &upl->conf_offset);
+ if (ret)
+ return log_msg_ret("cnf", ret);
+
+ ofnode_for_each_subnode(node, images) {
+ struct upl_image img;
+
+ ret = read_addr(upl, node, UPLP_LOAD, &img.load);
+ if (!ret)
+ ret = read_size(upl, node, UPLP_SIZE, &img.size);
+ if (!ret)
+ ret = read_uint(node, UPLP_OFFSET, &img.offset);
+ img.description = ofnode_read_string(node, UPLP_DESCRIPTION);
+ if (!img.description)
+ return log_msg_ret("sim", ret);
+ if (!alist_add(&upl->image, img))
+ return log_msg_ret("img", -ENOMEM);
+ }
+
+ return 0;
+}
+
+/**
+ * decode_addr_size() - Decide a set of addr/size pairs
+ *
+ * Each base/size value from the devicetree is written to the region list
+ *
+ * @upl: UPL state
+ * @buf: Bytes to decode
+ * @size: Number of bytes to decode
+ * @regions: List of regions to process (struct memregion)
+ * Returns: number of regions found, if OK, else -ve on error
+ */
+static int decode_addr_size(const struct upl *upl, const char *buf, int size,
+ struct alist *regions)
+{
+ const char *ptr, *end = buf + size;
+ int i;
+
+ alist_init_struct(regions, struct memregion);
+ ptr = buf;
+ for (i = 0; ptr < end; i++) {
+ struct memregion reg;
+
+ if (upl->addr_cells == 1)
+ reg.base = fdt32_to_cpu(*(u32 *)ptr);
+ else
+ reg.base = fdt64_to_cpu(*(u64 *)ptr);
+ ptr += upl->addr_cells * sizeof(u32);
+
+ if (upl->size_cells == 1)
+ reg.size = fdt32_to_cpu(*(u32 *)ptr);
+ else
+ reg.size = fdt64_to_cpu(*(u64 *)ptr);
+ ptr += upl->size_cells * sizeof(u32);
+ if (ptr > end)
+ return -ENOSPC;
+
+ if (!alist_add(regions, reg))
+ return log_msg_ret("reg", -ENOMEM);
+ }
+
+ return i;
+}
+
+/**
+ * node_matches_at() - Check if a node name matches "base@..."
+ *
+ * Return: true if the node name matches the base string followed by an @ sign;
+ * false otherwise
+ */
+static bool node_matches_at(ofnode node, const char *base)
+{
+ const char *name = ofnode_get_name(node);
+ int len = strlen(base);
+
+ return !strncmp(base, name, len) && name[len] == '@';
+}
+
+/**
+ * decode_upl_memory_node() - Decode a /memory node from the tree
+ *
+ * @upl: UPL state
+ * @node: Node to decode
+ * Return 0 if OK, -ve on error
+ */
+static int decode_upl_memory_node(struct upl *upl, ofnode node)
+{
+ struct upl_mem mem;
+ const char *buf;
+ int size, len;
+
+ buf = ofnode_read_prop(node, UPLP_REG, &size);
+ if (!buf) {
+ log_warning("Node '%s': Missing '%s' property\n",
+ ofnode_get_name(node), UPLP_REG);
+ return log_msg_ret("reg", -EINVAL);
+ }
+ len = decode_addr_size(upl, buf, size, &mem.region);
+ if (len < 0)
+ return log_msg_ret("buf", len);
+ mem.hotpluggable = ofnode_read_bool(node, UPLP_HOTPLUGGABLE);
+ if (!alist_add(&upl->mem, mem))
+ return log_msg_ret("mem", -ENOMEM);
+
+ return 0;
+}
+
+/**
+ * decode_upl_memmap() - Decode memory-map nodes from the tree
+ *
+ * @upl: UPL state
+ * @root: Parent node containing the /memory-map nodes
+ * Return 0 if OK, -ve on error
+ */
+static int decode_upl_memmap(struct upl *upl, ofnode root)
+{
+ ofnode node;
+
+ ofnode_for_each_subnode(node, root) {
+ struct upl_memmap memmap;
+ int size, len, ret;
+ const char *buf;
+
+ memmap.name = ofnode_get_name(node);
+ memmap.usage = 0;
+
+ buf = ofnode_read_prop(node, UPLP_REG, &size);
+ if (!buf) {
+ log_warning("Node '%s': Missing '%s' property\n",
+ ofnode_get_name(node), UPLP_REG);
+ continue;
+ }
+
+ len = decode_addr_size(upl, buf, size, &memmap.region);
+ if (len < 0)
+ return log_msg_ret("buf", len);
+ ret = ofnode_read_bitmask(node, UPLP_USAGE, usage_names,
+ UPLUS_COUNT, &memmap.usage);
+ if (ret && ret != -EINVAL) /* optional property */
+ return log_msg_ret("bit", ret);
+
+ if (!alist_add(&upl->memmap, memmap))
+ return log_msg_ret("mmp", -ENOMEM);
+ }
+
+ return 0;
+}
+
+/**
+ * decode_upl_memres() - Decode reserved-memory nodes from the tree
+ *
+ * @upl: UPL state
+ * @root: Parent node containing the reserved-memory nodes
+ * Return 0 if OK, -ve on error
+ */
+static int decode_upl_memres(struct upl *upl, ofnode root)
+{
+ ofnode node;
+
+ ofnode_for_each_subnode(node, root) {
+ struct upl_memres memres;
+ const char *buf;
+ int size, len;
+
+ log_debug("decoding '%s'\n", ofnode_get_name(node));
+ memres.name = ofnode_get_name(node);
+
+ buf = ofnode_read_prop(node, UPLP_REG, &size);
+ if (!buf) {
+ log_warning("Node '%s': Missing 'reg' property\n",
+ ofnode_get_name(node));
+ continue;
+ }
+
+ len = decode_addr_size(upl, buf, size, &memres.region);
+ if (len < 0)
+ return log_msg_ret("buf", len);
+ memres.no_map = ofnode_read_bool(node, UPLP_NO_MAP);
+
+ if (!alist_add(&upl->memres, memres))
+ return log_msg_ret("mre", -ENOMEM);
+ }
+
+ return 0;
+}
+
+/**
+ * decode_upl_serial() - Decode the serial node
+ *
+ * @upl: UPL state
+ * @root: Parent node contain node
+ * Return 0 if OK, -ve on error
+ */
+static int decode_upl_serial(struct upl *upl, ofnode node)
+{
+ struct upl_serial *ser = &upl->serial;
+ const char *buf;
+ int len, size;
+ int ret;
+
+ ser->compatible = ofnode_read_string(node, UPLP_COMPATIBLE);
+ if (!ser->compatible) {
+ log_warning("Node '%s': Missing compatible string\n",
+ ofnode_get_name(node));
+ return log_msg_ret("com", -EINVAL);
+ }
+ ret = read_uint(node, UPLP_CLOCK_FREQUENCY, &ser->clock_frequency);
+ if (!ret)
+ ret = read_uint(node, UPLP_CURRENT_SPEED, &ser->current_speed);
+ if (ret)
+ return log_msg_ret("spe", ret);
+
+ buf = ofnode_read_prop(node, UPLP_REG, &size);
+ if (!buf) {
+ log_warning("Node '%s': Missing 'reg' property\n",
+ ofnode_get_name(node));
+ return log_msg_ret("reg", -EINVAL);
+ }
+
+ len = decode_addr_size(upl, buf, sizeof(buf), &ser->reg);
+ if (len < 0)
+ return log_msg_ret("buf", len);
+
+ /* set defaults */
+ ser->reg_io_shift = UPLD_REG_IO_SHIFT;
+ ser->reg_offset = UPLD_REG_OFFSET;
+ ser->reg_io_width = UPLD_REG_IO_WIDTH;
+ read_uint(node, UPLP_REG_IO_SHIFT, &ser->reg_io_shift);
+ read_uint(node, UPLP_REG_OFFSET, &ser->reg_offset);
+ read_uint(node, UPLP_REG_IO_WIDTH, &ser->reg_io_width);
+ read_addr(upl, node, UPLP_VIRTUAL_REG, &ser->virtual_reg);
+ ret = ofnode_read_value(node, UPLP_ACCESS_TYPE, access_types,
+ ARRAY_SIZE(access_types), &ser->access_type);
+ if (ret && ret != -ENOENT)
+ return log_msg_ret("ser", ret);
+
+ return 0;
+}
+
+/**
+ * decode_upl_graphics() - Decode graphics node
+ *
+ * @upl: UPL state
+ * @root: Node to decode
+ * Return 0 if OK, -ve on error
+ */
+static int decode_upl_graphics(struct upl *upl, ofnode node)
+{
+ struct upl_graphics *gra = &upl->graphics;
+ const char *buf, *compat;
+ int len, size;
+ int ret;
+
+ compat = ofnode_read_string(node, UPLP_COMPATIBLE);
+ if (!compat) {
+ log_warning("Node '%s': Missing compatible string\n",
+ ofnode_get_name(node));
+ return log_msg_ret("com", -EINVAL);
+ }
+ if (strcmp(UPLC_GRAPHICS, compat)) {
+ log_warning("Node '%s': Ignoring compatible '%s'\n",
+ ofnode_get_name(node), compat);
+ return 0;
+ }
+
+ buf = ofnode_read_prop(node, UPLP_REG, &size);
+ if (!buf) {
+ log_warning("Node '%s': Missing 'reg' property\n",
+ ofnode_get_name(node));
+ return log_msg_ret("reg", -EINVAL);
+ }
+
+ len = decode_addr_size(upl, buf, sizeof(buf), &gra->reg);
+ if (len < 0)
+ return log_msg_ret("buf", len);
+
+ ret = read_uint(node, UPLP_WIDTH, &gra->width);
+ if (!ret)
+ ret = read_uint(node, UPLP_HEIGHT, &gra->height);
+ if (!ret)
+ ret = read_uint(node, UPLP_STRIDE, &gra->stride);
+ if (!ret) {
+ ret = ofnode_read_value(node, UPLP_GRAPHICS_FORMAT,
+ graphics_formats,
+ ARRAY_SIZE(graphics_formats),
+ &gra->format);
+ }
+ if (ret)
+ return log_msg_ret("pro", ret);
+
+ return 0;
+}
+
+int upl_read_handoff(struct upl *upl, oftree tree)
+{
+ ofnode root, node;
+ int ret;
+
+ if (!oftree_valid(tree))
+ return log_msg_ret("tre", -EINVAL);
+
+ root = oftree_root(tree);
+
+ upl_init(upl);
+ ret = decode_root_props(upl, root);
+ if (ret)
+ return log_msg_ret("roo", ret);
+
+ ofnode_for_each_subnode(node, root) {
+ const char *name = ofnode_get_name(node);
+
+ log_debug("decoding '%s'\n", name);
+ if (!strcmp(UPLN_OPTIONS, name)) {
+ ret = decode_upl_params(upl, node);
+ if (ret)
+ return log_msg_ret("opt", ret);
+
+ ret = decode_upl_images(upl, node);
+ } else if (node_matches_at(node, UPLN_MEMORY)) {
+ ret = decode_upl_memory_node(upl, node);
+ } else if (!strcmp(UPLN_MEMORY_MAP, name)) {
+ ret = decode_upl_memmap(upl, node);
+ } else if (!strcmp(UPLN_MEMORY_RESERVED, name)) {
+ ret = decode_upl_memres(upl, node);
+ } else if (node_matches_at(node, UPLN_SERIAL)) {
+ ret = decode_upl_serial(upl, node);
+ } else if (node_matches_at(node, UPLN_GRAPHICS)) {
+ ret = decode_upl_graphics(upl, node);
+ } else {
+ log_debug("Unknown node '%s'\n", name);
+ ret = 0;
+ }
+ if (ret)
+ return log_msg_ret("err", ret);
+ }
+
+ return 0;
+}
diff --git a/boot/upl_write.c b/boot/upl_write.c
new file mode 100644
index 0000000..7d637c15
--- /dev/null
+++ b/boot/upl_write.c
@@ -0,0 +1,622 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * UPL handoff generation
+ *
+ * Copyright 2024 Google LLC
+ * Written by Simon Glass <sjg@chromium.org>
+ */
+
+#define LOG_CATEGORY UCLASS_BOOTSTD
+
+#include <log.h>
+#include <upl.h>
+#include <dm/ofnode.h>
+#include "upl_common.h"
+
+/**
+ * write_addr() - Write an address
+ *
+ * Writes an address in the correct format, either 32- or 64-bit
+ *
+ * @upl: UPL state
+ * @node: Node to write to
+ * @prop: Property name to write
+ * @addr: Address to write
+ * Return: 0 if OK, -ve on error
+ */
+static int write_addr(const struct upl *upl, ofnode node, const char *prop,
+ ulong addr)
+{
+ int ret;
+
+ if (upl->addr_cells == 1)
+ ret = ofnode_write_u32(node, prop, addr);
+ else
+ ret = ofnode_write_u64(node, prop, addr);
+
+ return ret;
+}
+
+/**
+ * write_size() - Write a size
+ *
+ * Writes a size in the correct format, either 32- or 64-bit
+ *
+ * @upl: UPL state
+ * @node: Node to write to
+ * @prop: Property name to write
+ * @size: Size to write
+ * Return: 0 if OK, -ve on error
+ */
+static int write_size(const struct upl *upl, ofnode node, const char *prop,
+ ulong size)
+{
+ int ret;
+
+ if (upl->size_cells == 1)
+ ret = ofnode_write_u32(node, prop, size);
+ else
+ ret = ofnode_write_u64(node, prop, size);
+
+ return ret;
+}
+
+/**
+ * ofnode_write_bitmask() - Write a bit mask as a string list
+ *
+ * @node: Node to write to
+ * @prop: Property name to write
+ * @names: Array of names for each bit
+ * @count: Number of array entries
+ * @value: Bit-mask value to write
+ * Return: 0 if OK, -EINVAL if a bit number is not defined, -ENOSPC if the
+ * string is too long for the (internal) buffer
+ */
+static int ofnode_write_bitmask(ofnode node, const char *prop,
+ const char *const names[], uint count,
+ uint value)
+{
+ char buf[128];
+ char *ptr, *end = buf + sizeof(buf);
+ uint bit;
+ int ret;
+
+ ptr = buf;
+ for (bit = 0; bit < count; bit++) {
+ if (value & BIT(bit)) {
+ const char *str = names[bit];
+ uint len;
+
+ if (!str) {
+ log_debug("Unnamed bit number %d\n", bit);
+ return log_msg_ret("bit", -EINVAL);
+ }
+ len = strlen(str) + 1;
+ if (ptr + len > end) {
+ log_debug("String array too long\n");
+ return log_msg_ret("bit", -ENOSPC);
+ }
+
+ memcpy(ptr, str, len);
+ ptr += len;
+ }
+ }
+
+ ret = ofnode_write_prop(node, prop, buf, ptr - buf, true);
+ if (ret)
+ return log_msg_ret("wri", ret);
+
+ return 0;
+}
+
+/**
+ * ofnode_write_value() - Write an int as a string value using a lookup
+ *
+ * @node: Node to write to
+ * @prop: Property name to write
+ * @names: Array of names for each int value
+ * @count: Number of array entries
+ * @value: Int value to write
+ * Return: 0 if OK, -EINVAL if a bit number is not defined, -ENOSPC if the
+ * string is too long for the (internal) buffer
+ */
+static int ofnode_write_value(ofnode node, const char *prop,
+ const char *const names[], uint count,
+ uint value)
+{
+ const char *str;
+ int ret;
+
+ if (value >= count) {
+ log_debug("Value of range %d\n", value);
+ return log_msg_ret("val", -ERANGE);
+ }
+ str = names[value];
+ if (!str) {
+ log_debug("Unnamed value %d\n", value);
+ return log_msg_ret("val", -EINVAL);
+ }
+ ret = ofnode_write_string(node, prop, str);
+ if (ret)
+ return log_msg_ret("wri", ret);
+
+ return 0;
+}
+
+/**
+ * add_root_props() - Add root properties to the tree
+ *
+ * @node: Node to add to
+ * Return 0 if OK, -ve on error
+ */
+static int add_root_props(const struct upl *upl, ofnode node)
+{
+ int ret;
+
+ ret = ofnode_write_u32(node, UPLP_ADDRESS_CELLS, upl->addr_cells);
+ if (!ret)
+ ret = ofnode_write_u32(node, UPLP_SIZE_CELLS, upl->size_cells);
+ if (ret)
+ return log_msg_ret("cel", ret);
+
+ return 0;
+}
+
+/**
+ * add_upl_params() - Add UPL parameters node
+ *
+ * @upl: UPL state
+ * @options: /options node to add to
+ * Return 0 if OK, -ve on error
+ */
+static int add_upl_params(const struct upl *upl, ofnode options)
+{
+ ofnode node;
+ int ret;
+
+ ret = ofnode_add_subnode(options, UPLN_UPL_PARAMS, &node);
+ if (ret)
+ return log_msg_ret("img", ret);
+
+ ret = write_addr(upl, node, UPLP_SMBIOS, upl->smbios);
+ if (!ret)
+ ret = write_addr(upl, node, UPLP_ACPI, upl->acpi);
+ if (!ret && upl->bootmode)
+ ret = ofnode_write_bitmask(node, UPLP_BOOTMODE, bootmode_names,
+ UPLBM_COUNT, upl->bootmode);
+ if (!ret)
+ ret = ofnode_write_u32(node, UPLP_ADDR_WIDTH, upl->addr_width);
+ if (!ret)
+ ret = ofnode_write_u32(node, UPLP_ACPI_NVS_SIZE,
+ upl->acpi_nvs_size);
+ if (ret)
+ return log_msg_ret("cnf", ret);
+
+ return 0;
+}
+
+/**
+ * add_upl_image() - Add /options/upl-image nodes and properties to the tree
+ *
+ * @upl: UPL state
+ * @node: /options node to add to
+ * Return 0 if OK, -ve on error
+ */
+static int add_upl_image(const struct upl *upl, ofnode options)
+{
+ ofnode node;
+ int ret, i;
+
+ ret = ofnode_add_subnode(options, UPLN_UPL_IMAGE, &node);
+ if (ret)
+ return log_msg_ret("img", ret);
+
+ if (upl->fit)
+ ret = ofnode_write_u32(node, UPLP_FIT, upl->fit);
+ if (!ret && upl->conf_offset)
+ ret = ofnode_write_u32(node, UPLP_CONF_OFFSET,
+ upl->conf_offset);
+ if (ret)
+ return log_msg_ret("cnf", ret);
+
+ for (i = 0; i < upl->image.count; i++) {
+ const struct upl_image *img = alist_get(&upl->image, i,
+ struct upl_image);
+ ofnode subnode;
+ char name[10];
+
+ snprintf(name, sizeof(name), UPLN_IMAGE "-%d", i + 1);
+ ret = ofnode_add_subnode(node, name, &subnode);
+ if (ret)
+ return log_msg_ret("sub", ret);
+
+ ret = write_addr(upl, subnode, UPLP_LOAD, img->load);
+ if (!ret)
+ ret = write_size(upl, subnode, UPLP_SIZE, img->size);
+ if (!ret && img->offset)
+ ret = ofnode_write_u32(subnode, UPLP_OFFSET,
+ img->offset);
+ ret = ofnode_write_string(subnode, UPLP_DESCRIPTION,
+ img->description);
+ if (ret)
+ return log_msg_ret("sim", ret);
+ }
+
+ return 0;
+}
+
+/**
+ * buffer_addr_size() - Generate a set of addr/size pairs
+ *
+ * Each base/size value from each region is written to the buffer in a suitable
+ * format to be written to the devicetree
+ *
+ * @upl: UPL state
+ * @buf: Buffer to write to
+ * @size: Buffer size
+ * @num_regions: Number of regions to process
+ * @region: List of regions to process (struct memregion)
+ * Returns: Number of bytes written, or -ENOSPC if the buffer is too small
+ */
+static int buffer_addr_size(const struct upl *upl, char *buf, int size,
+ uint num_regions, const struct alist *region)
+{
+ char *ptr, *end = buf + size;
+ int i;
+
+ ptr = buf;
+ for (i = 0; i < num_regions; i++) {
+ const struct memregion *reg = alist_get(region, i,
+ struct memregion);
+
+ if (upl->addr_cells == 1)
+ *(u32 *)ptr = cpu_to_fdt32(reg->base);
+ else
+ *(u64 *)ptr = cpu_to_fdt64(reg->base);
+ ptr += upl->addr_cells * sizeof(u32);
+
+ if (upl->size_cells == 1)
+ *(u32 *)ptr = cpu_to_fdt32(reg->size);
+ else
+ *(u64 *)ptr = cpu_to_fdt64(reg->size);
+ ptr += upl->size_cells * sizeof(u32);
+ if (ptr > end)
+ return -ENOSPC;
+ }
+
+ return ptr - buf;
+}
+
+/**
+ * add_upl_memory() - Add /memory nodes to the tree
+ *
+ * @upl: UPL state
+ * @root: Parent node to contain the new /memory nodes
+ * Return 0 if OK, -ve on error
+ */
+static int add_upl_memory(const struct upl *upl, ofnode root)
+{
+ int i;
+
+ for (i = 0; i < upl->mem.count; i++) {
+ const struct upl_mem *mem = alist_get(&upl->mem, i,
+ struct upl_mem);
+ char buf[mem->region.count * sizeof(64) * 2];
+ const struct memregion *first;
+ char name[26];
+ int ret, len;
+ ofnode node;
+
+ if (!mem->region.count) {
+ log_debug("Memory %d has no regions\n", i);
+ return log_msg_ret("reg", -EINVAL);
+ }
+ first = alist_get(&mem->region, 0, struct memregion);
+ sprintf(name, UPLN_MEMORY "@0x%lx", first->base);
+ ret = ofnode_add_subnode(root, name, &node);
+ if (ret)
+ return log_msg_ret("mem", ret);
+
+ len = buffer_addr_size(upl, buf, sizeof(buf), mem->region.count,
+ &mem->region);
+ if (len < 0)
+ return log_msg_ret("buf", len);
+
+ ret = ofnode_write_prop(node, UPLP_REG, buf, len, true);
+ if (!ret && mem->hotpluggable)
+ ret = ofnode_write_bool(node, UPLP_HOTPLUGGABLE,
+ mem->hotpluggable);
+ if (ret)
+ return log_msg_ret("lst", ret);
+ }
+
+ return 0;
+}
+
+/**
+ * add_upl_memmap() - Add memory-map nodes to the tree
+ *
+ * @upl: UPL state
+ * @root: Parent node to contain the new /memory-map node and its subnodes
+ * Return 0 if OK, -ve on error
+ */
+static int add_upl_memmap(const struct upl *upl, ofnode root)
+{
+ ofnode mem_node;
+ int i, ret;
+
+ if (!upl->memmap.count)
+ return 0;
+ ret = ofnode_add_subnode(root, UPLN_MEMORY_MAP, &mem_node);
+ if (ret)
+ return log_msg_ret("img", ret);
+
+ for (i = 0; i < upl->memmap.count; i++) {
+ const struct upl_memmap *memmap = alist_get(&upl->memmap, i,
+ struct upl_memmap);
+ char buf[memmap->region.count * sizeof(64) * 2];
+ const struct memregion *first;
+ char name[26];
+ int ret, len;
+ ofnode node;
+
+ if (!memmap->region.count) {
+ log_debug("Memory %d has no regions\n", i);
+ return log_msg_ret("reg", -EINVAL);
+ }
+ first = alist_get(&memmap->region, 0, struct memregion);
+ sprintf(name, "%s@0x%lx", memmap->name, first->base);
+ ret = ofnode_add_subnode(mem_node, name, &node);
+ if (ret)
+ return log_msg_ret("memmap", ret);
+
+ len = buffer_addr_size(upl, buf, sizeof(buf),
+ memmap->region.count, &memmap->region);
+ if (len < 0)
+ return log_msg_ret("buf", len);
+ ret = ofnode_write_prop(node, UPLP_REG, buf, len, true);
+ if (!ret && memmap->usage)
+ ret = ofnode_write_bitmask(node, UPLP_USAGE,
+ usage_names,
+ UPLUS_COUNT, memmap->usage);
+ if (ret)
+ return log_msg_ret("lst", ret);
+ }
+
+ return 0;
+}
+
+/**
+ * add_upl_memres() - Add /memory-reserved nodes to the tree
+ *
+ * @upl: UPL state
+ * @root: Parent node to contain the new node
+ * Return 0 if OK, -ve on error
+ */
+static int add_upl_memres(const struct upl *upl, ofnode root,
+ bool skip_existing)
+{
+ ofnode mem_node;
+ int i, ret;
+
+ if (!upl->memmap.count)
+ return 0;
+ ret = ofnode_add_subnode(root, UPLN_MEMORY_RESERVED, &mem_node);
+ if (ret) {
+ if (skip_existing && ret == -EEXIST)
+ return 0;
+ return log_msg_ret("img", ret);
+ }
+
+ for (i = 0; i < upl->memres.count; i++) {
+ const struct upl_memres *memres = alist_get(&upl->memres, i,
+ struct upl_memres);
+ char buf[memres->region.count * sizeof(64) * 2];
+ const struct memregion *first;
+ char name[26];
+ int ret, len;
+ ofnode node;
+
+ if (!memres->region.count) {
+ log_debug("Memory %d has no regions\n", i);
+ return log_msg_ret("reg", -EINVAL);
+ }
+ first = alist_get(&memres->region, 0, struct memregion);
+ sprintf(name, "%s@0x%lx", memres->name, first->base);
+ ret = ofnode_add_subnode(mem_node, name, &node);
+ if (ret)
+ return log_msg_ret("memres", ret);
+
+ len = buffer_addr_size(upl, buf, sizeof(buf),
+ memres->region.count, &memres->region);
+ ret = ofnode_write_prop(node, UPLP_REG, buf, len, true);
+ if (!ret && memres->no_map)
+ ret = ofnode_write_bool(node, UPLP_NO_MAP,
+ memres->no_map);
+ if (ret)
+ return log_msg_ret("lst", ret);
+ }
+
+ return 0;
+}
+
+/**
+ * add_upl_serial() - Add serial node
+ *
+ * @upl: UPL state
+ * @root: Parent node to contain the new node
+ * Return 0 if OK, -ve on error
+ */
+static int add_upl_serial(const struct upl *upl, ofnode root,
+ bool skip_existing)
+{
+ const struct upl_serial *ser = &upl->serial;
+ const struct memregion *first;
+ char name[26];
+ ofnode node;
+ int ret;
+
+ if (!ser->compatible || skip_existing)
+ return 0;
+ if (!ser->reg.count)
+ return log_msg_ret("ser", -EINVAL);
+ first = alist_get(&ser->reg, 0, struct memregion);
+ sprintf(name, UPLN_SERIAL "@0x%lx", first->base);
+ ret = ofnode_add_subnode(root, name, &node);
+ if (ret)
+ return log_msg_ret("img", ret);
+ ret = ofnode_write_string(node, UPLP_COMPATIBLE, ser->compatible);
+ if (!ret)
+ ret = ofnode_write_u32(node, UPLP_CLOCK_FREQUENCY,
+ ser->clock_frequency);
+ if (!ret)
+ ret = ofnode_write_u32(node, UPLP_CURRENT_SPEED,
+ ser->current_speed);
+ if (!ret) {
+ char buf[16];
+ int len;
+
+ len = buffer_addr_size(upl, buf, sizeof(buf), 1, &ser->reg);
+ if (len < 0)
+ return log_msg_ret("buf", len);
+
+ ret = ofnode_write_prop(node, UPLP_REG, buf, len, true);
+ }
+ if (!ret && ser->reg_io_shift != UPLD_REG_IO_SHIFT)
+ ret = ofnode_write_u32(node, UPLP_REG_IO_SHIFT,
+ ser->reg_io_shift);
+ if (!ret && ser->reg_offset != UPLD_REG_OFFSET)
+ ret = ofnode_write_u32(node, UPLP_REG_OFFSET, ser->reg_offset);
+ if (!ret && ser->reg_io_width != UPLD_REG_IO_WIDTH)
+ ret = ofnode_write_u32(node, UPLP_REG_IO_WIDTH,
+ ser->reg_io_width);
+ if (!ret && ser->virtual_reg)
+ ret = write_addr(upl, node, UPLP_VIRTUAL_REG, ser->virtual_reg);
+ if (!ret) {
+ ret = ofnode_write_value(node, UPLP_ACCESS_TYPE, access_types,
+ ARRAY_SIZE(access_types),
+ ser->access_type);
+ }
+ if (ret)
+ return log_msg_ret("ser", ret);
+
+ return 0;
+}
+
+/**
+ * add_upl_graphics() - Add graphics node
+ *
+ * @upl: UPL state
+ * @root: Parent node to contain the new node
+ * Return 0 if OK, -ve on error
+ */
+static int add_upl_graphics(const struct upl *upl, ofnode root)
+{
+ const struct upl_graphics *gra = &upl->graphics;
+ const struct memregion *first;
+ char name[36];
+ ofnode node;
+ int ret;
+
+ if (!gra->reg.count)
+ return log_msg_ret("gra", -ENOENT);
+ first = alist_get(&gra->reg, 0, struct memregion);
+ sprintf(name, UPLN_GRAPHICS "@0x%lx", first->base);
+ ret = ofnode_add_subnode(root, name, &node);
+ if (ret)
+ return log_msg_ret("gra", ret);
+
+ ret = ofnode_write_string(node, UPLP_COMPATIBLE, UPLC_GRAPHICS);
+ if (!ret) {
+ char buf[16];
+ int len;
+
+ len = buffer_addr_size(upl, buf, sizeof(buf), 1, &gra->reg);
+ if (len < 0)
+ return log_msg_ret("buf", len);
+
+ ret = ofnode_write_prop(node, UPLP_REG, buf, len, true);
+ }
+ if (!ret)
+ ret = ofnode_write_u32(node, UPLP_WIDTH, gra->width);
+ if (!ret)
+ ret = ofnode_write_u32(node, UPLP_HEIGHT, gra->height);
+ if (!ret)
+ ret = ofnode_write_u32(node, UPLP_STRIDE, gra->stride);
+ if (!ret) {
+ ret = ofnode_write_value(node, UPLP_GRAPHICS_FORMAT,
+ graphics_formats,
+ ARRAY_SIZE(graphics_formats),
+ gra->format);
+ }
+ if (ret)
+ return log_msg_ret("pro", ret);
+
+ return 0;
+}
+
+int upl_write_handoff(const struct upl *upl, ofnode root, bool skip_existing)
+{
+ ofnode options;
+ int ret;
+
+ ret = add_root_props(upl, root);
+ if (ret)
+ return log_msg_ret("ad1", ret);
+ ret = ofnode_add_subnode(root, UPLN_OPTIONS, &options);
+ if (ret && ret != -EEXIST)
+ return log_msg_ret("opt", -EINVAL);
+
+ ret = add_upl_params(upl, options);
+ if (ret)
+ return log_msg_ret("ad1", ret);
+
+ ret = add_upl_image(upl, options);
+ if (ret)
+ return log_msg_ret("ad2", ret);
+
+ ret = add_upl_memory(upl, root);
+ if (ret)
+ return log_msg_ret("ad3", ret);
+
+ ret = add_upl_memmap(upl, root);
+ if (ret)
+ return log_msg_ret("ad4", ret);
+
+ ret = add_upl_memres(upl, root, skip_existing);
+ if (ret)
+ return log_msg_ret("ad5", ret);
+
+ ret = add_upl_serial(upl, root, skip_existing);
+ if (ret)
+ return log_msg_ret("ad6", ret);
+
+ ret = add_upl_graphics(upl, root);
+ if (ret && ret != -ENOENT)
+ return log_msg_ret("ad6", ret);
+
+ return 0;
+}
+
+int upl_create_handoff_tree(const struct upl *upl, oftree *treep)
+{
+ ofnode root;
+ oftree tree;
+ int ret;
+
+ ret = oftree_new(&tree);
+ if (ret)
+ return log_msg_ret("new", ret);
+
+ root = oftree_root(tree);
+ if (!ofnode_valid(root))
+ return log_msg_ret("roo", -EINVAL);
+
+ ret = upl_write_handoff(upl, root, false);
+ if (ret)
+ return log_msg_ret("wr", ret);
+
+ *treep = tree;
+
+ return 0;
+}
diff --git a/cmd/Kconfig b/cmd/Kconfig
index 978f44e..43f78a5 100644
--- a/cmd/Kconfig
+++ b/cmd/Kconfig
@@ -388,6 +388,13 @@
help
Support reading NAND Seattle Image (SEAMA) images.
+config CMD_UPL
+ bool "upl - Universal Payload Specification"
+ help
+ Provides commands to deal with UPL payloads and handoff information.
+ U-Boot supports generating and accepting handoff information. The
+ mkimage tool will eventually support creating payloads.
+
config CMD_VBE
bool "vbe - Verified Boot for Embedded"
depends on BOOTMETH_VBE
@@ -2003,6 +2010,7 @@
config CMD_WGET
bool "wget"
select PROT_TCP
+ default y if SANDBOX
help
wget is a simple command to download kernel, or other files,
from a http server over TCP.
diff --git a/cmd/Makefile b/cmd/Makefile
index 87133cc..91227f1 100644
--- a/cmd/Makefile
+++ b/cmd/Makefile
@@ -189,6 +189,7 @@
obj-$(CONFIG_CMD_UNIVERSE) += universe.o
obj-$(CONFIG_CMD_UNLZ4) += unlz4.o
obj-$(CONFIG_CMD_UNZIP) += unzip.o
+obj-$(CONFIG_CMD_UPL) += upl.o
obj-$(CONFIG_CMD_VIRTIO) += virtio.o
obj-$(CONFIG_CMD_WDT) += wdt.o
obj-$(CONFIG_CMD_LZMADEC) += lzmadec.o
diff --git a/cmd/bdinfo.c b/cmd/bdinfo.c
index 437ac4e..59fbaea 100644
--- a/cmd/bdinfo.c
+++ b/cmd/bdinfo.c
@@ -154,8 +154,6 @@
if (IS_ENABLED(CONFIG_CMD_NET))
print_eth();
bdinfo_print_num_l("fdt_blob", (ulong)map_to_sysmem(gd->fdt_blob));
- bdinfo_print_num_l("new_fdt", (ulong)map_to_sysmem(gd->new_fdt));
- bdinfo_print_num_l("fdt_size", (ulong)gd->fdt_size);
if (IS_ENABLED(CONFIG_VIDEO))
show_video_info();
#if CONFIG_IS_ENABLED(MULTI_DTB_FIT)
diff --git a/cmd/date.c b/cmd/date.c
index 755adec..8614f02 100644
--- a/cmd/date.c
+++ b/cmd/date.c
@@ -31,7 +31,6 @@
int old_bus __maybe_unused;
/* switch to correct I2C bus */
-#ifdef CONFIG_DM_RTC
struct udevice *dev;
rcode = uclass_get_device_by_seq(UCLASS_RTC, 0, &dev);
@@ -42,35 +41,19 @@
return CMD_RET_FAILURE;
}
}
-#elif CONFIG_IS_ENABLED(SYS_I2C_LEGACY)
- old_bus = i2c_get_bus_num();
- i2c_set_bus_num(CFG_SYS_RTC_BUS_NUM);
-#else
- old_bus = I2C_GET_BUS();
- I2C_SET_BUS(CFG_SYS_RTC_BUS_NUM);
-#endif
switch (argc) {
case 2: /* set date & time */
if (strcmp(argv[1],"reset") == 0) {
puts ("Reset RTC...\n");
-#ifdef CONFIG_DM_RTC
rcode = dm_rtc_reset(dev);
if (!rcode)
rcode = dm_rtc_set(dev, &default_tm);
-#else
- rtc_reset();
- rcode = rtc_set(&default_tm);
-#endif
if (rcode)
puts("## Failed to set date after RTC reset\n");
} else {
/* initialize tm with current time */
-#ifdef CONFIG_DM_RTC
rcode = dm_rtc_get(dev, &tm);
-#else
- rcode = rtc_get(&tm);
-#endif
if (!rcode) {
/* insert new date & time */
if (mk_date(argv[1], &tm) != 0) {
@@ -78,11 +61,7 @@
break;
}
/* and write to RTC */
-#ifdef CONFIG_DM_RTC
rcode = dm_rtc_set(dev, &tm);
-#else
- rcode = rtc_set(&tm);
-#endif
if (rcode) {
printf("## Set date failed: err=%d\n",
rcode);
@@ -93,11 +72,7 @@
}
fallthrough;
case 1: /* get date & time */
-#ifdef CONFIG_DM_RTC
rcode = dm_rtc_get(dev, &tm);
-#else
- rcode = rtc_get(&tm);
-#endif
if (rcode) {
puts("## Get date failed\n");
break;
@@ -114,13 +89,6 @@
rcode = CMD_RET_USAGE;
}
- /* switch back to original I2C bus */
-#if CONFIG_IS_ENABLED(SYS_I2C_LEGACY)
- i2c_set_bus_num(old_bus);
-#elif !defined(CONFIG_DM_RTC)
- I2C_SET_BUS(old_bus);
-#endif
-
return rcode ? CMD_RET_FAILURE : 0;
}
diff --git a/cmd/i2c.c b/cmd/i2c.c
index 7dac0a9..7246c4f 100644
--- a/cmd/i2c.c
+++ b/cmd/i2c.c
@@ -1698,18 +1698,6 @@
for (i = 0; i < CFG_SYS_NUM_I2C_BUSES; i++) {
printf("Bus %d:\t%s", i, I2C_ADAP_NR(i)->name);
-#ifndef CFG_SYS_I2C_DIRECT_BUS
- int j;
-
- for (j = 0; j < CFG_SYS_I2C_MAX_HOPS; j++) {
- if (i2c_bus[i].next_hop[j].chip == 0)
- break;
- printf("->%s@0x%2x:%d",
- i2c_bus[i].next_hop[j].mux.name,
- i2c_bus[i].next_hop[j].chip,
- i2c_bus[i].next_hop[j].channel);
- }
-#endif
printf("\n");
}
#endif
@@ -1734,17 +1722,6 @@
return -1;
}
printf("Bus %d:\t%s", i, I2C_ADAP_NR(i)->name);
-#ifndef CFG_SYS_I2C_DIRECT_BUS
- int j;
- for (j = 0; j < CFG_SYS_I2C_MAX_HOPS; j++) {
- if (i2c_bus[i].next_hop[j].chip == 0)
- break;
- printf("->%s@0x%2x:%d",
- i2c_bus[i].next_hop[j].mux.name,
- i2c_bus[i].next_hop[j].chip,
- i2c_bus[i].next_hop[j].channel);
- }
-#endif
printf("\n");
#endif
}
diff --git a/cmd/led.c b/cmd/led.c
index 2f786f3..91fb856 100644
--- a/cmd/led.c
+++ b/cmd/led.c
@@ -118,7 +118,7 @@
return 0;
}
-#ifdef CONFIG_LED_BLINK
+#if defined(CONFIG_LED_BLINK) || defined(CONFIG_LED_SW_BLINK)
#define BLINK "|blink [blink-freq in ms]"
#else
#define BLINK ""
diff --git a/cmd/mmc.c b/cmd/mmc.c
index 7244a90..ff7b8e5 100644
--- a/cmd/mmc.c
+++ b/cmd/mmc.c
@@ -238,7 +238,7 @@
if (argc == 5)
key_addr = (void *)hextoul(argv[4], NULL);
- printf("\nMMC RPMB read: dev # %d, block # %d, count %d ... ",
+ printf("MMC RPMB read: dev # %d, block # %d, count %d ... ",
curr_device, blk, cnt);
n = mmc_rpmb_read(mmc, addr, blk, cnt, key_addr);
@@ -265,7 +265,7 @@
cnt = hextoul(argv[3], NULL);
key_addr = (void *)hextoul(argv[4], NULL);
- printf("\nMMC RPMB write: dev # %d, block # %d, count %d ... ",
+ printf("MMC RPMB write: dev # %d, block # %d, count %d ... ",
curr_device, blk, cnt);
n = mmc_rpmb_write(mmc, addr, blk, cnt, key_addr);
@@ -362,7 +362,7 @@
if (!mmc)
return CMD_RET_FAILURE;
- printf("\nMMC read: dev # %d, block # %d, count %d ... ",
+ printf("MMC read: dev # %d, block # %d, count %d ... ",
curr_device, blk, cnt);
n = blk_dread(mmc_get_blk_desc(mmc), blk, cnt, addr);
@@ -411,7 +411,7 @@
if (!mmc)
return CMD_RET_FAILURE;
- printf("\nMMC Sparse write: dev # %d, block # %d ... ",
+ printf("MMC Sparse write: dev # %d, block # %d ... ",
curr_device, blk);
if (mmc_getwp(mmc) == 1) {
@@ -455,7 +455,7 @@
if (!mmc)
return CMD_RET_FAILURE;
- printf("\nMMC write: dev # %d, block # %d, count %d ... ",
+ printf("MMC write: dev # %d, block # %d, count %d ... ",
curr_device, blk, cnt);
if (mmc_getwp(mmc) == 1) {
@@ -484,7 +484,7 @@
if (!mmc)
return CMD_RET_FAILURE;
- printf("\nMMC erase: dev # %d, block # %d, count %d ... ",
+ printf("MMC erase: dev # %d, block # %d, count %d ... ",
curr_device, blk, cnt);
if (mmc_getwp(mmc) == 1) {
diff --git a/cmd/sb.c b/cmd/sb.c
index 1aa5921..db485fd 100644
--- a/cmd/sb.c
+++ b/cmd/sb.c
@@ -14,8 +14,10 @@
char *const argv[])
{
#if CONFIG_IS_ENABLED(HANDOFF)
- if (gd->spl_handoff)
- printf("SPL handoff magic %lx\n", gd->spl_handoff->arch.magic);
+ struct spl_handoff *handoff = handoff_get();
+
+ if (handoff)
+ printf("SPL handoff magic %lx\n", handoff->arch.magic);
else
printf("SPL handoff info not received\n");
diff --git a/cmd/upl.c b/cmd/upl.c
new file mode 100644
index 0000000..c974588
--- /dev/null
+++ b/cmd/upl.c
@@ -0,0 +1,118 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Commands for UPL handoff generation
+ *
+ * Copyright 2024 Google LLC
+ * Written by Simon Glass <sjg@chromium.org>
+ */
+
+#define LOG_CATEGORY UCLASS_BOOTSTD
+
+#include <abuf.h>
+#include <alist.h>
+#include <command.h>
+#include <display_options.h>
+#include <mapmem.h>
+#include <string.h>
+#include <upl.h>
+#include <dm/ofnode.h>
+#include <test/ut.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+static int do_upl_info(struct cmd_tbl *cmdtp, int flag, int argc,
+ char *const argv[])
+{
+ const struct upl *upl = gd_upl();
+
+ printf("UPL state: %sactive\n", upl ? "" : "in");
+ if (!upl)
+ return 0;
+ if (argc > 1 && !strcmp("-v", argv[1])) {
+ int i;
+
+ printf("fit %lx\n", upl->fit);
+ printf("conf_offset %x\n", upl->conf_offset);
+ for (i = 0; i < upl->image.count; i++) {
+ const struct upl_image *img =
+ alist_get(&upl->image, i, struct upl_image);
+
+ printf("image %d: load %lx size %lx offset %x: %s\n", i,
+ img->load, img->size, img->offset,
+ img->description);
+ }
+ }
+
+ return 0;
+}
+
+static int do_upl_write(struct cmd_tbl *cmdtp, int flag, int argc,
+ char *const argv[])
+{
+ struct upl s_upl, *upl = &s_upl;
+ struct unit_test_state uts;
+ struct abuf buf;
+ oftree tree;
+ ulong addr;
+ int ret;
+
+ upl_get_test_data(&uts, upl);
+
+ log_debug("Writing UPL\n");
+ ret = upl_create_handoff_tree(upl, &tree);
+ if (ret) {
+ log_err("Failed to write (err=%dE)\n", ret);
+ return CMD_RET_FAILURE;
+ }
+
+ log_debug("Flattening\n");
+ ret = oftree_to_fdt(tree, &buf);
+ if (ret) {
+ log_err("Failed to write (err=%dE)\n", ret);
+ return CMD_RET_FAILURE;
+ }
+ addr = map_to_sysmem(abuf_data(&buf));
+ printf("UPL handoff written to %lx size %lx\n", addr, abuf_size(&buf));
+ if (env_set_hex("upladdr", addr) ||
+ env_set_hex("uplsize", abuf_size(&buf))) {
+ printf("Cannot set env var\n");
+ return CMD_RET_FAILURE;
+ }
+
+ log_debug("done\n");
+
+ return 0;
+}
+
+static int do_upl_read(struct cmd_tbl *cmdtp, int flag, int argc,
+ char *const argv[])
+{
+ struct upl s_upl, *upl = &s_upl;
+ oftree tree;
+ ulong addr;
+ int ret;
+
+ if (argc < 1)
+ return CMD_RET_USAGE;
+ addr = hextoul(argv[1], NULL);
+
+ printf("Reading UPL at %lx\n", addr);
+ tree = oftree_from_fdt(map_sysmem(addr, 0));
+ ret = upl_read_handoff(upl, tree);
+ if (ret) {
+ log_err("Failed to read (err=%dE)\n", ret);
+ return CMD_RET_FAILURE;
+ }
+
+ return 0;
+}
+
+U_BOOT_LONGHELP(upl,
+ "info [-v] - Check UPL status\n"
+ "upl read <addr> - Read handoff information\n"
+ "upl write - Write handoff information");
+
+U_BOOT_CMD_WITH_SUBCMDS(upl, "Universal Payload support", upl_help_text,
+ U_BOOT_SUBCMD_MKENT(info, 2, 1, do_upl_info),
+ U_BOOT_SUBCMD_MKENT(read, 2, 1, do_upl_read),
+ U_BOOT_SUBCMD_MKENT(write, 1, 1, do_upl_write));
diff --git a/common/board_f.c b/common/board_f.c
index 29e1851..d9fe6f9 100644
--- a/common/board_f.c
+++ b/common/board_f.c
@@ -40,6 +40,7 @@
#include <sysreset.h>
#include <timer.h>
#include <trace.h>
+#include <upl.h>
#include <video.h>
#include <watchdog.h>
#include <asm/cache.h>
@@ -304,17 +305,6 @@
return 0;
}
-static int setup_spl_handoff(void)
-{
-#if CONFIG_IS_ENABLED(HANDOFF)
- gd->spl_handoff = bloblist_find(BLOBLISTT_U_BOOT_SPL_HANDOFF,
- sizeof(struct spl_handoff));
- debug("Found SPL hand-off info %p\n", gd->spl_handoff);
-#endif
-
- return 0;
-}
-
__weak int arch_cpu_init(void)
{
return 0;
@@ -350,7 +340,7 @@
static int setup_dest_addr(void)
{
- debug("Monitor len: %08lX\n", gd->mon_len);
+ debug("Monitor len: %08x\n", gd->mon_len);
/*
* Ram is setup, size stored in gd !!
*/
@@ -487,7 +477,7 @@
gd->relocaddr &= ~(65536 - 1);
#endif
- debug("Reserving %ldk for U-Boot at: %08lx\n",
+ debug("Reserving %dk for U-Boot at: %08lx\n",
gd->mon_len >> 10, gd->relocaddr);
}
@@ -574,12 +564,15 @@
* section, then it will be relocated with other data.
*/
if (gd->fdt_blob) {
- gd->fdt_size = ALIGN(fdt_totalsize(gd->fdt_blob), 32);
+ gd->boardf->fdt_size =
+ ALIGN(fdt_totalsize(gd->fdt_blob), 32);
- gd->start_addr_sp = reserve_stack_aligned(gd->fdt_size);
- gd->new_fdt = map_sysmem(gd->start_addr_sp, gd->fdt_size);
+ gd->start_addr_sp = reserve_stack_aligned(
+ gd->boardf->fdt_size);
+ gd->boardf->new_fdt = map_sysmem(gd->start_addr_sp,
+ gd->boardf->fdt_size);
debug("Reserving %lu Bytes for FDT at: %08lx\n",
- gd->fdt_size, gd->start_addr_sp);
+ gd->boardf->fdt_size, gd->start_addr_sp);
}
}
@@ -592,7 +585,7 @@
int size = bootstage_get_size();
gd->start_addr_sp = reserve_stack_aligned(size);
- gd->new_bootstage = map_sysmem(gd->start_addr_sp, size);
+ gd->boardf->new_bootstage = map_sysmem(gd->start_addr_sp, size);
debug("Reserving %#x Bytes for bootstage at: %08lx\n", size,
gd->start_addr_sp);
#endif
@@ -623,8 +616,8 @@
/* Align to a 4KB boundary for easier reading of addresses */
gd->start_addr_sp = ALIGN_DOWN(gd->start_addr_sp -
CONFIG_BLOBLIST_SIZE_RELOC, 0x1000);
- gd->new_bloblist = map_sysmem(gd->start_addr_sp,
- CONFIG_BLOBLIST_SIZE_RELOC);
+ gd->boardf->new_bloblist = map_sysmem(gd->start_addr_sp,
+ CONFIG_BLOBLIST_SIZE_RELOC);
#endif
return 0;
@@ -667,10 +660,10 @@
static int reloc_fdt(void)
{
if (!IS_ENABLED(CONFIG_OF_EMBED)) {
- if (gd->new_fdt) {
- memcpy(gd->new_fdt, gd->fdt_blob,
+ if (gd->boardf->new_fdt) {
+ memcpy(gd->boardf->new_fdt, gd->fdt_blob,
fdt_totalsize(gd->fdt_blob));
- gd->fdt_blob = gd->new_fdt;
+ gd->fdt_blob = gd->boardf->new_fdt;
}
}
@@ -682,15 +675,8 @@
#ifdef CONFIG_BOOTSTAGE
if (gd->flags & GD_FLG_SKIP_RELOC)
return 0;
- if (gd->new_bootstage) {
- int size = bootstage_get_size();
-
- debug("Copying bootstage from %p to %p, size %x\n",
- gd->bootstage, gd->new_bootstage, size);
- memcpy(gd->new_bootstage, gd->bootstage, size);
- gd->bootstage = gd->new_bootstage;
- bootstage_relocate();
- }
+ if (gd->boardf->new_bootstage)
+ bootstage_relocate(gd->boardf->new_bootstage);
#endif
return 0;
@@ -707,10 +693,11 @@
debug("Not relocating bloblist\n");
return 0;
}
- if (gd->new_bloblist) {
+ if (gd->boardf->new_bloblist) {
debug("Copying bloblist from %p to %p, size %x\n",
- gd->bloblist, gd->new_bloblist, gd->bloblist->total_size);
- return bloblist_reloc(gd->new_bloblist,
+ gd->bloblist, gd->boardf->new_bloblist,
+ gd->bloblist->total_size);
+ return bloblist_reloc(gd->boardf->new_bloblist,
CONFIG_BLOBLIST_SIZE_RELOC);
}
#endif
@@ -856,6 +843,26 @@
__weak int clear_bss(void)
{
+ return 0;
+}
+
+static int initf_upl(void)
+{
+ struct upl *upl;
+ int ret;
+
+ if (!IS_ENABLED(CONFIG_UPL_IN) || !(gd->flags & GD_FLG_UPL))
+ return 0;
+
+ upl = malloc(sizeof(struct upl));
+ if (upl)
+ ret = upl_read_handoff(upl, oftree_default());
+ if (ret) {
+ printf("UPL handoff: read failure (err=%dE)\n", ret);
+ return ret;
+ }
+ gd_set_upl(upl);
+
return 0;
}
@@ -868,11 +875,11 @@
trace_early_init,
#endif
initf_malloc,
+ initf_upl,
log_init,
initf_bootstage, /* uses its own timer, so does not need DM */
event_init,
bloblist_maybe_init,
- setup_spl_handoff,
#if defined(CONFIG_CONSOLE_RECORD_INIT_F)
console_record_init,
#endif
@@ -1005,8 +1012,11 @@
void board_init_f(ulong boot_flags)
{
+ struct board_f boardf;
+
gd->flags = boot_flags;
- gd->have_console = 0;
+ gd->flags &= ~GD_FLG_HAVE_CONSOLE;
+ gd->boardf = &boardf;
if (initcall_run_list(init_sequence_f))
hang();
diff --git a/common/board_r.c b/common/board_r.c
index d4ba245..e88b7ea 100644
--- a/common/board_r.c
+++ b/common/board_r.c
@@ -192,7 +192,7 @@
ulong start;
#if CONFIG_IS_ENABLED(SYS_MALLOC_F)
- debug("Pre-reloc malloc() used %#lx bytes (%ld KB)\n", gd->malloc_ptr,
+ debug("Pre-reloc malloc() used %#x bytes (%d KB)\n", gd->malloc_ptr,
gd->malloc_ptr / 1024);
#endif
/* The malloc area is immediately below the monitor copy in DRAM */
@@ -521,6 +521,8 @@
uclass_count);
if (CONFIG_IS_ENABLED(OF_REAL))
printf(", devicetree: %s", fdtdec_get_srcname());
+ if (CONFIG_IS_ENABLED(UPL))
+ printf(", universal payload active");
printf("\n");
if (IS_ENABLED(CONFIG_OF_HAS_PRIOR_STAGE) &&
(gd->fdt_src == FDTSRC_SEPARATE ||
diff --git a/common/bootstage.c b/common/bootstage.c
index b6c268d..49acc90 100644
--- a/common/bootstage.c
+++ b/common/bootstage.c
@@ -54,12 +54,16 @@
u32 next_id; /* Next ID to use for bootstage */
};
-int bootstage_relocate(void)
+int bootstage_relocate(void *to)
{
- struct bootstage_data *data = gd->bootstage;
+ struct bootstage_data *data;
int i;
char *ptr;
+ debug("Copying bootstage from %p to %p\n", gd->bootstage, to);
+ memcpy(to, gd->bootstage, sizeof(struct bootstage_data));
+ data = gd->bootstage = to;
+
/* Figure out where to relocate the strings to */
ptr = (char *)(data + 1);
diff --git a/common/console.c b/common/console.c
index 63f7800..52d6df8 100644
--- a/common/console.c
+++ b/common/console.c
@@ -189,6 +189,7 @@
/* Assign the new device (leaving the existing one started) */
stdio_devices[file] = dev;
+#ifndef CONFIG_SPL_BUILD
/*
* Update monitor functions
* (to use the console stuff by other applications)
@@ -206,7 +207,7 @@
break;
}
break;
-
+#endif
default: /* Invalid file ID */
error = -1;
}
@@ -586,7 +587,7 @@
if (IS_ENABLED(CONFIG_DISABLE_CONSOLE) && (gd->flags & GD_FLG_DISABLE_CONSOLE))
return 0;
- if (!gd->have_console)
+ if (!(gd->flags & GD_FLG_HAVE_CONSOLE))
return 0;
ch = console_record_getc();
@@ -607,7 +608,7 @@
if (IS_ENABLED(CONFIG_DISABLE_CONSOLE) && (gd->flags & GD_FLG_DISABLE_CONSOLE))
return 0;
- if (!gd->have_console)
+ if (!(gd->flags & GD_FLG_HAVE_CONSOLE))
return 0;
if (console_record_tstc())
@@ -715,7 +716,7 @@
if (IS_ENABLED(CONFIG_DISABLE_CONSOLE) && (gd->flags & GD_FLG_DISABLE_CONSOLE))
return;
- if (!gd->have_console)
+ if (!(gd->flags & GD_FLG_HAVE_CONSOLE))
return pre_console_putc(c);
if (gd->flags & GD_FLG_DEVINIT) {
@@ -759,7 +760,7 @@
if (IS_ENABLED(CONFIG_DISABLE_CONSOLE) && (gd->flags & GD_FLG_DISABLE_CONSOLE))
return;
- if (!gd->have_console)
+ if (!(gd->flags & GD_FLG_HAVE_CONSOLE))
return pre_console_puts(s);
if (gd->flags & GD_FLG_DEVINIT) {
@@ -793,7 +794,7 @@
if (IS_ENABLED(CONFIG_DISABLE_CONSOLE) && (gd->flags & GD_FLG_DISABLE_CONSOLE))
return;
- if (!gd->have_console)
+ if (!(gd->flags & GD_FLG_HAVE_CONSOLE))
return;
if (gd->flags & GD_FLG_DEVINIT) {
@@ -845,6 +846,8 @@
{
if (gd->flags & GD_FLG_RECORD_OVF)
return -ENOSPC;
+ if (console_record_isempty())
+ return -ENOENT;
return membuff_readline((struct membuff *)&gd->console_out, str,
maxlen, '\0', false);
@@ -872,7 +875,7 @@
static int ctrlc_was_pressed = 0;
int ctrlc(void)
{
- if (!ctrlc_disabled && gd->have_console) {
+ if (!ctrlc_disabled && (gd->flags & GD_FLG_HAVE_CONSOLE)) {
if (tstc()) {
switch (getchar()) {
case 0x03: /* ^C - Control C */
@@ -1011,7 +1014,7 @@
/* Called before relocation - use serial functions */
int console_init_f(void)
{
- gd->have_console = 1;
+ gd->flags |= GD_FLG_HAVE_CONSOLE;
console_update_silent();
diff --git a/common/dlmalloc.c b/common/dlmalloc.c
index 62e8557..1ac7ce3 100644
--- a/common/dlmalloc.c
+++ b/common/dlmalloc.c
@@ -386,8 +386,8 @@
/* pad request bytes into a usable size */
#define request2size(req) \
- (((long)((req) + (SIZE_SZ + MALLOC_ALIGN_MASK)) < \
- (long)(MINSIZE + MALLOC_ALIGN_MASK)) ? MINSIZE : \
+ ((((req) + (SIZE_SZ + MALLOC_ALIGN_MASK)) < \
+ (MINSIZE + MALLOC_ALIGN_MASK)) ? MINSIZE : \
(((req) + (SIZE_SZ + MALLOC_ALIGN_MASK)) & ~(MALLOC_ALIGN_MASK)))
/* Check if m has acceptable alignment */
@@ -581,6 +581,9 @@
ulong old = mem_malloc_brk;
ulong new = old + increment;
+ if ((new < mem_malloc_start) || (new > mem_malloc_end))
+ return (void *)MORECORE_FAILURE;
+
/*
* if we are giving memory back make sure we clear it out since
* we set MORECORE_CLEARS to 1
@@ -588,9 +591,6 @@
if (increment < 0)
memset((void *)new, 0, -increment);
- if ((new < mem_malloc_start) || (new > mem_malloc_end))
- return (void *)MORECORE_FAILURE;
-
mem_malloc_brk = new;
return (void *)old;
@@ -1274,7 +1274,8 @@
return NULL;
}
- if ((long)bytes < 0) return NULL;
+ if (bytes > CONFIG_SYS_MALLOC_LEN || (long)bytes < 0)
+ return NULL;
nb = request2size(bytes); /* padded request size; */
@@ -1687,7 +1688,8 @@
}
#endif
- if ((long)bytes < 0) return NULL;
+ if (bytes > CONFIG_SYS_MALLOC_LEN || (long)bytes < 0)
+ return NULL;
/* realloc of null is supposed to be same as malloc */
if (oldmem == NULL) return mALLOc_impl(bytes);
@@ -1698,6 +1700,10 @@
panic("pre-reloc realloc() is not supported");
}
#endif
+ if (CONFIG_IS_ENABLED(UNIT_TEST) && malloc_testing) {
+ if (--malloc_max_allocs < 0)
+ return NULL;
+ }
newp = oldp = mem2chunk(oldmem);
newsize = oldsize = chunksize(oldp);
@@ -1907,7 +1913,8 @@
mchunkptr remainder; /* spare room at end to split off */
long remainder_size; /* its size */
- if ((long)bytes < 0) return NULL;
+ if (bytes > CONFIG_SYS_MALLOC_LEN || (long)bytes < 0)
+ return NULL;
#if CONFIG_IS_ENABLED(SYS_MALLOC_F)
if (!(gd->flags & GD_FLG_FULL_MALLOC_INIT)) {
diff --git a/common/hwconfig.c b/common/hwconfig.c
index afaa6cb..25a8cd5 100644
--- a/common/hwconfig.c
+++ b/common/hwconfig.c
@@ -77,7 +77,13 @@
/* if we are passed a buffer use it, otherwise try the environment */
if (!env_hwconfig) {
- if (!(gd->flags & GD_FLG_ENV_READY) && gd->env_valid != ENV_VALID) {
+#if CONFIG_IS_ENABLED(ENV_SUPPORT)
+ if (!(gd->flags & GD_FLG_ENV_READY) &&
+ gd->env_valid != ENV_VALID)
+#else
+ if (true)
+#endif
+ {
printf("WARNING: Calling __hwconfig without a buffer "
"and before environment is ready\n");
return NULL;
diff --git a/common/init/handoff.c b/common/init/handoff.c
index a7cd065..86c020e 100644
--- a/common/init/handoff.c
+++ b/common/init/handoff.c
@@ -5,6 +5,7 @@
* Copyright 2018 Google, Inc
*/
+#include <bloblist.h>
#include <handoff.h>
#include <asm/global_data.h>
@@ -38,3 +39,14 @@
bd->bi_dram[i].size = ho->ram_bank[i].size;
}
}
+
+struct spl_handoff *handoff_get(void)
+{
+ struct spl_handoff *handoff;
+
+ handoff = bloblist_find(BLOBLISTT_U_BOOT_SPL_HANDOFF,
+ sizeof(struct spl_handoff));
+ debug("Found SPL hand-off info %p\n", handoff);
+
+ return handoff;
+}
diff --git a/common/log_console.c b/common/log_console.c
index c27101b..9376baa 100644
--- a/common/log_console.c
+++ b/common/log_console.c
@@ -38,10 +38,10 @@
printf("%d-", rec->line);
if (fmt & BIT(LOGF_FUNC)) {
if (CONFIG_IS_ENABLED(USE_TINY_PRINTF)) {
- printf("%s()", rec->func);
+ printf("%s()", rec->func ?: "?");
} else {
printf("%*s()", CONFIG_LOGF_FUNC_PAD,
- rec->func);
+ rec->func ?: "?");
}
}
}
diff --git a/common/log_syslog.c b/common/log_syslog.c
index d01bb74..0dcb5f7 100644
--- a/common/log_syslog.c
+++ b/common/log_syslog.c
@@ -88,7 +88,7 @@
if (fmt & BIT(LOGF_LINE))
append(&ptr, msg_end, "%d-", rec->line);
if (fmt & BIT(LOGF_FUNC))
- append(&ptr, msg_end, "%s()", rec->func);
+ append(&ptr, msg_end, "%s()", rec->func ?: "?");
if (fmt & BIT(LOGF_MSG))
append(&ptr, msg_end, "%s%s",
fmt != BIT(LOGF_MSG) ? " " : "", rec->msg);
diff --git a/common/malloc_simple.c b/common/malloc_simple.c
index 4e6d795..5a8ec53 100644
--- a/common/malloc_simple.c
+++ b/common/malloc_simple.c
@@ -23,7 +23,7 @@
addr = ALIGN(gd->malloc_base + gd->malloc_ptr, align);
new_ptr = addr + bytes - gd->malloc_base;
- log_debug("size=%lx, ptr=%lx, limit=%lx: ", (ulong)bytes, new_ptr,
+ log_debug("size=%lx, ptr=%lx, limit=%x: ", (ulong)bytes, new_ptr,
gd->malloc_limit);
if (new_ptr > gd->malloc_limit) {
log_err("alloc space exhausted\n");
@@ -87,6 +87,6 @@
void malloc_simple_info(void)
{
- log_info("malloc_simple: %lx bytes used, %lx remain\n", gd->malloc_ptr,
+ log_info("malloc_simple: %x bytes used, %x remain\n", gd->malloc_ptr,
CONFIG_VAL(SYS_MALLOC_F_LEN) - gd->malloc_ptr);
}
diff --git a/common/spl/Kconfig b/common/spl/Kconfig
index c08ff06..3c44e32 100644
--- a/common/spl/Kconfig
+++ b/common/spl/Kconfig
@@ -78,6 +78,7 @@
hex "Maximum size of the SPL image, excluding BSS"
default 0x30000 if ARCH_MX6 && MX6_OCRAM_256KB
default 0x1b000 if AM33XX && !TI_SECURE_DEVICE
+ default 0xec00 if OMAP34XX
default 0x10000 if ARCH_MX6 && !MX6_OCRAM_256KB
default 0x7fa0 if SUNXI_SRAM_ADDRESS = 0x10000
default 0x7fa0 if SUNXI_SRAM_ADDRESS = 0x20000 && !MACH_SUN50I_H616
@@ -261,6 +262,7 @@
config SPL_TEXT_BASE
hex "SPL Text Base"
+ default 0x40200000 if OMAP34XX
default 0x402F4000 if AM43XX
default 0x402F0400 if AM33XX
default 0x40301350 if OMAP54XX
@@ -490,24 +492,45 @@
the board.
config SPL_SYS_MMCSD_RAW_MODE
- bool
- help
- Support booting from an MMC without a filesystem.
-
-config SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR
- bool "MMC raw mode: by sector"
+ bool "Use raw reads to locate the next boot phase"
+ depends on SPL_DM_MMC || SPL_MMC
default y if ARCH_SUNXI || ARCH_DAVINCI || ARCH_UNIPHIER || \
ARCH_MX6 || ARCH_MX7 || \
ARCH_ROCKCHIP || ARCH_MVEBU || ARCH_SOCFPGA || \
ARCH_AT91 || ARCH_ZYNQ || ARCH_KEYSTONE || OMAP34XX || \
OMAP54XX || AM33XX || AM43XX || \
TARGET_SIFIVE_UNLEASHED || TARGET_SIFIVE_UNMATCHED
- select SPL_LOAD_BLOCK if SPL_MMC
- select SPL_SYS_MMCSD_RAW_MODE if SPL_MMC
+ help
+ Support booting from an MMC without a filesystem.
+
+if SPL_SYS_MMCSD_RAW_MODE
+
+choice
+ prompt "Method for locating next phase of boot (e.g. U-Boot)"
+
+config SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR
+ bool "MMC raw mode: by sector"
+ select SPL_LOAD_BLOCK
help
Use sector number for specifying U-Boot location on MMC/SD in
raw mode.
+config SYS_MMCSD_RAW_MODE_U_BOOT_USE_PARTITION
+ bool "MMC raw mode: by partition"
+ select SPL_LOAD_BLOCK
+ help
+ Use a partition for loading U-Boot when using MMC/SD in raw mode.
+
+config SYS_MMCSD_RAW_MODE_U_BOOT_USE_PARTITION_TYPE
+ bool "MMC raw mode: by partition type"
+ depends on DOS_PARTITION
+ help
+ Use partition type for specifying U-Boot partition on MMC/SD in
+ raw mode. U-Boot will be loaded from the first partition of this
+ type to be found.
+
+endchoice
+
config SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR
hex "Address on the MMC to load U-Boot from"
depends on SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR
@@ -538,13 +561,6 @@
If unsure, leave the default.
-config SYS_MMCSD_RAW_MODE_U_BOOT_USE_PARTITION
- bool "MMC Raw mode: by partition"
- select SPL_LOAD_BLOCK if SPL_MMC
- select SPL_SYS_MMCSD_RAW_MODE if SPL_MMC
- help
- Use a partition for loading U-Boot when using MMC/SD in raw mode.
-
config SYS_MMCSD_RAW_MODE_U_BOOT_PARTITION
hex "Partition to use to load U-Boot from"
depends on SYS_MMCSD_RAW_MODE_U_BOOT_USE_PARTITION
@@ -553,14 +569,6 @@
Partition on the MMC to load U-Boot from when the MMC is being
used in raw mode
-config SYS_MMCSD_RAW_MODE_U_BOOT_USE_PARTITION_TYPE
- bool "MMC raw mode: by partition type"
- depends on DOS_PARTITION && SYS_MMCSD_RAW_MODE_U_BOOT_USE_PARTITION
- help
- Use partition type for specifying U-Boot partition on MMC/SD in
- raw mode. U-Boot will be loaded from the first partition of this
- type to be found.
-
config SYS_MMCSD_RAW_MODE_U_BOOT_PARTITION_TYPE
hex "Partition Type on the MMC to load U-Boot from"
depends on SYS_MMCSD_RAW_MODE_U_BOOT_USE_PARTITION_TYPE
@@ -568,6 +576,8 @@
Partition Type on the MMC to load U-Boot from, when the MMC is being
used in raw mode.
+endif # SPL_SYS_MMCSD_RAW_MODE
+
config SUPPORT_EMMC_BOOT_OVERRIDE_PART_CONFIG
bool "Override eMMC EXT_CSC_PART_CONFIG by user defined partition"
depends on SUPPORT_EMMC_BOOT
diff --git a/common/spl/Makefile b/common/spl/Makefile
index 4809f9c..137b184 100644
--- a/common/spl/Makefile
+++ b/common/spl/Makefile
@@ -37,3 +37,5 @@
obj-$(CONFIG_$(SPL_TPL_)RAM_SUPPORT) += spl_ram.o
obj-$(CONFIG_$(SPL_TPL_)USB_SDP_SUPPORT) += spl_sdp.o
endif
+
+obj-$(CONFIG_$(SPL_TPL_)UPL) += spl_upl.o
diff --git a/common/spl/spl.c b/common/spl/spl.c
index 7794ddc..da110ee 100644
--- a/common/spl/spl.c
+++ b/common/spl/spl.c
@@ -245,7 +245,6 @@
return map_sysmem(CONFIG_TEXT_BASE + offset, 0);
}
-#ifdef CONFIG_SPL_RAW_IMAGE_SUPPORT
void spl_set_header_raw_uboot(struct spl_image_info *spl_image)
{
ulong u_boot_pos = spl_get_image_pos();
@@ -273,7 +272,6 @@
spl_image->os = IH_OS_U_BOOT;
spl_image->name = "U-Boot";
}
-#endif
__weak int spl_parse_board_header(struct spl_image_info *spl_image,
const struct spl_boot_device *bootdev,
@@ -308,8 +306,10 @@
ret = spl_parse_legacy_header(spl_image, header);
if (ret)
return ret;
- } else {
-#ifdef CONFIG_SPL_PANIC_ON_RAW_IMAGE
+ return 0;
+ }
+
+ if (IS_ENABLED(CONFIG_SPL_PANIC_ON_RAW_IMAGE)) {
/*
* CONFIG_SPL_PANIC_ON_RAW_IMAGE is defined when the
* code which loads images in SPL cannot guarantee that
@@ -319,10 +319,9 @@
* is bad, and thus should be skipped silently.
*/
panic("** no mkimage signature but raw image not supported");
-#endif
+ }
-#if CONFIG_IS_ENABLED(OS_BOOT)
-#if defined(CMD_BOOTI)
+ if (CONFIG_IS_ENABLED(OS_BOOT) && IS_ENABLED(CONFIG_CMD_BOOTI)) {
ulong start, size;
if (!booti_setup((ulong)header, &start, &size, 0)) {
@@ -336,7 +335,7 @@
spl_image->load_addr, spl_image->size);
return 0;
}
-#elif defined(CMD_BOOTZ)
+ } else if (CONFIG_IS_ENABLED(OS_BOOT) && IS_ENABLED(CONFIG_CMD_BOOTZ)) {
ulong start, end;
if (!bootz_setup((ulong)header, &start, &end)) {
@@ -350,22 +349,21 @@
spl_image->load_addr, spl_image->size);
return 0;
}
-#endif
-#endif
+ }
- if (!spl_parse_board_header(spl_image, bootdev, (const void *)header, sizeof(*header)))
- return 0;
+ if (!spl_parse_board_header(spl_image, bootdev, (const void *)header,
+ sizeof(*header)))
+ return 0;
-#ifdef CONFIG_SPL_RAW_IMAGE_SUPPORT
+ if (IS_ENABLED(CONFIG_SPL_RAW_IMAGE_SUPPORT)) {
/* Signature not found - assume u-boot.bin */
debug("mkimage signature not found - ih_magic = %x\n",
- header->ih_magic);
+ header->ih_magic);
spl_set_header_raw_uboot(spl_image);
-#else
+ } else {
/* RAW image not supported, proceed to other boot methods. */
debug("Raw boot image support not enabled, proceeding to other boot methods\n");
return -EINVAL;
-#endif
}
return 0;
@@ -784,7 +782,7 @@
}
if (CONFIG_IS_ENABLED(SYS_MALLOC_F) &&
!IS_ENABLED(CONFIG_SPL_SYS_MALLOC_SIZE))
- debug("SPL malloc() used 0x%lx bytes (%ld KB)\n",
+ debug("SPL malloc() used 0x%x bytes (%d KB)\n",
gd_malloc_ptr(), gd_malloc_ptr() / 1024);
bootstage_mark_name(get_bootstage_id(false), "end phase");
@@ -810,6 +808,14 @@
printf(SPL_TPL_PROMPT
"SPL hand-off write failed (err=%d)\n", ret);
}
+ if (CONFIG_IS_ENABLED(UPL_OUT) && (gd->flags & GD_FLG_UPL)) {
+ ret = spl_write_upl_handoff(&spl_image);
+ if (ret) {
+ printf(SPL_TPL_PROMPT
+ "UPL hand-off write failed (err=%d)\n", ret);
+ hang();
+ }
+ }
if (CONFIG_IS_ENABLED(BLOBLIST)) {
ret = bloblist_finish();
if (ret)
@@ -832,7 +838,7 @@
serial_init(); /* serial communications setup */
- gd->have_console = 1;
+ gd->flags |= GD_FLG_HAVE_CONSOLE;
#if CONFIG_IS_ENABLED(BANNER_PRINT)
puts("\nU-Boot " SPL_TPL_NAME " " PLAIN_VERSION " (" U_BOOT_DATE " - "
@@ -895,7 +901,7 @@
#if defined(CONFIG_SPL_SYS_MALLOC_SIMPLE) && CONFIG_IS_ENABLED(SYS_MALLOC_F)
if (CONFIG_SPL_STACK_R_MALLOC_SIMPLE_LEN) {
- debug("SPL malloc() before relocation used 0x%lx bytes (%ld KB)\n",
+ debug("SPL malloc() before relocation used 0x%x bytes (%d KB)\n",
gd->malloc_ptr, gd->malloc_ptr / 1024);
ptr -= CONFIG_SPL_STACK_R_MALLOC_SIMPLE_LEN;
gd->malloc_base = ptr;
diff --git a/common/spl/spl_blk_fs.c b/common/spl/spl_blk_fs.c
index bc551c5..bbf90a9 100644
--- a/common/spl/spl_blk_fs.c
+++ b/common/spl/spl_blk_fs.c
@@ -80,11 +80,8 @@
return ret;
}
- load.read = spl_fit_read;
- if (IS_ENABLED(CONFIG_SPL_FS_FAT_DMA_ALIGN))
- spl_set_bl_len(&load, ARCH_DMA_MINALIGN);
- else
- spl_set_bl_len(&load, 1);
- load.priv = &dev;
+ spl_load_init(&load, spl_fit_read, &dev,
+ IS_ENABLED(CONFIG_SPL_FS_FAT_DMA_ALIGN) ?
+ ARCH_DMA_MINALIGN : 1);
return spl_load(spl_image, bootdev, &load, filesize, 0);
}
diff --git a/common/spl/spl_ext.c b/common/spl/spl_ext.c
index 76f49a5..c547882 100644
--- a/common/spl/spl_ext.c
+++ b/common/spl/spl_ext.c
@@ -51,8 +51,7 @@
goto end;
}
- spl_set_bl_len(&load, 1);
- load.read = spl_fit_read;
+ spl_load_init(&load, spl_fit_read, NULL, 1);
err = spl_load(spl_image, bootdev, &load, filelen, 0);
end:
diff --git a/common/spl/spl_fat.c b/common/spl/spl_fat.c
index bd8aab2..fce451b 100644
--- a/common/spl/spl_fat.c
+++ b/common/spl/spl_fat.c
@@ -83,12 +83,10 @@
size = 0;
}
- load.read = spl_fit_read;
- if (IS_ENABLED(CONFIG_SPL_FS_FAT_DMA_ALIGN))
- spl_set_bl_len(&load, ARCH_DMA_MINALIGN);
- else
- spl_set_bl_len(&load, 1);
- load.priv = (void *)filename;
+ spl_load_init(&load, spl_fit_read, (void *)filename,
+ IS_ENABLED(CONFIG_SPL_FS_FAT_DMA_ALIGN) ?
+ ARCH_DMA_MINALIGN : 1);
+
err = spl_load(spl_image, bootdev, &load, size, 0);
end:
diff --git a/common/spl/spl_fit.c b/common/spl/spl_fit.c
index 2a097f4..1ad5a69 100644
--- a/common/spl/spl_fit.c
+++ b/common/spl/spl_fit.c
@@ -12,6 +12,7 @@
#include <memalign.h>
#include <mapmem.h>
#include <spl.h>
+#include <upl.h>
#include <sysinfo.h>
#include <asm/global_data.h>
#include <asm/io.h>
@@ -336,6 +337,8 @@
image_info->entry_point = FDT_ERROR;
}
+ upl_add_image(fit, node, load_addr, length);
+
return 0;
}
@@ -847,6 +850,8 @@
spl_image->entry_point = spl_image->load_addr;
spl_image->flags |= SPL_FIT_FOUND;
+ upl_set_fit_info(map_to_sysmem(ctx.fit), ctx.conf_node,
+ spl_image->entry_point);
return 0;
}
@@ -941,6 +946,10 @@
if (ret < 0)
return ret;
}
+ spl_image->flags |= SPL_FIT_FOUND;
+
+ upl_set_fit_info(map_to_sysmem(header), conf_noffset,
+ spl_image->entry_point);
return 0;
}
diff --git a/common/spl/spl_mmc.c b/common/spl/spl_mmc.c
index ccab0be..3fd8160 100644
--- a/common/spl/spl_mmc.c
+++ b/common/spl/spl_mmc.c
@@ -46,21 +46,17 @@
struct blk_desc *bd = mmc_get_blk_desc(mmc);
struct spl_load_info load;
- load.priv = bd;
- spl_set_bl_len(&load, bd->blksz);
- load.read = h_spl_load_read;
+ spl_load_init(&load, h_spl_load_read, bd, bd->blksz);
ret = spl_load(spl_image, bootdev, &load, 0, sector << bd->log2blksz);
if (ret) {
-#ifdef CONFIG_SPL_LIBCOMMON_SUPPORT
puts("mmc_load_image_raw_sector: mmc block read error\n");
-#endif
- return -1;
+ return ret;
}
return 0;
}
-static int spl_mmc_get_device_index(u32 boot_device)
+static int spl_mmc_get_device_index(uint boot_device)
{
switch (boot_device) {
case BOOT_DEVICE_MMC1:
@@ -70,40 +66,30 @@
return 1;
}
-#ifdef CONFIG_SPL_LIBCOMMON_SUPPORT
printf("spl: unsupported mmc boot device.\n");
-#endif
return -ENODEV;
}
-static int spl_mmc_find_device(struct mmc **mmcp, u32 boot_device)
+static int spl_mmc_find_device(struct mmc **mmcp, int mmc_dev)
{
- int err, mmc_dev;
-
- mmc_dev = spl_mmc_get_device_index(boot_device);
- if (mmc_dev < 0)
- return mmc_dev;
+ int ret;
#if CONFIG_IS_ENABLED(DM_MMC)
- err = mmc_init_device(mmc_dev);
+ ret = mmc_init_device(mmc_dev);
#else
- err = mmc_initialize(NULL);
+ ret = mmc_initialize(NULL);
#endif /* DM_MMC */
- if (err) {
-#ifdef CONFIG_SPL_LIBCOMMON_SUPPORT
- printf("spl: could not initialize mmc. error: %d\n", err);
-#endif
- return err;
+ if (ret) {
+ printf("spl: could not initialize mmc. error: %d\n", ret);
+ return ret;
}
*mmcp = find_mmc_device(mmc_dev);
- err = *mmcp ? 0 : -ENODEV;
- if (err) {
-#ifdef CONFIG_SPL_LIBCOMMON_SUPPORT
+ ret = *mmcp ? 0 : -ENODEV;
+ if (ret) {
printf("spl: could not find mmc device %d. error: %d\n",
- mmc_dev, err);
-#endif
- return err;
+ mmc_dev, ret);
+ return ret;
}
return 0;
@@ -116,14 +102,14 @@
unsigned long sector)
{
struct disk_partition info;
- int err;
+ int ret;
#ifdef CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_PARTITION_TYPE
int type_part;
/* Only support MBR so DOS_ENTRY_NUMBERS */
for (type_part = 1; type_part <= DOS_ENTRY_NUMBERS; type_part++) {
- err = part_get_info(mmc_get_blk_desc(mmc), type_part, &info);
- if (err)
+ ret = part_get_info(mmc_get_blk_desc(mmc), type_part, &info);
+ if (ret)
continue;
if (info.sys_ind ==
CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_PARTITION_TYPE) {
@@ -133,12 +119,10 @@
}
#endif
- err = part_get_info(mmc_get_blk_desc(mmc), partition, &info);
- if (err) {
-#ifdef CONFIG_SPL_LIBCOMMON_SUPPORT
+ ret = part_get_info(mmc_get_blk_desc(mmc), partition, &info);
+ if (ret) {
puts("spl: partition error\n");
-#endif
- return -1;
+ return ret;
}
#ifdef CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR
@@ -164,10 +148,8 @@
CONFIG_SYS_MMCSD_RAW_MODE_ARGS_SECTORS,
(void *)CONFIG_SPL_PAYLOAD_ARGS_ADDR);
if (count != CONFIG_SYS_MMCSD_RAW_MODE_ARGS_SECTORS) {
-#ifdef CONFIG_SPL_LIBCOMMON_SUPPORT
puts("mmc_load_image_raw_os: mmc block read error\n");
-#endif
- return -1;
+ return -EIO;
}
#endif /* CONFIG_SYS_MMCSD_RAW_MODE_ARGS_SECTOR */
@@ -205,7 +187,7 @@
struct mmc *mmc,
const char *filename)
{
- int err = -ENOSYS;
+ int ret = -ENOSYS;
__maybe_unused int partition = CONFIG_SYS_MMCSD_FS_BOOT_PARTITION;
@@ -214,8 +196,8 @@
struct disk_partition info;
debug("Checking for the first MBR bootable partition\n");
for (int type_part = 1; type_part <= DOS_ENTRY_NUMBERS; type_part++) {
- err = part_get_info(mmc_get_blk_desc(mmc), type_part, &info);
- if (err)
+ ret = part_get_info(mmc_get_blk_desc(mmc), type_part, &info);
+ if (ret)
continue;
debug("Partition %d is of type %d and bootable=%d\n", type_part, info.sys_ind, info.bootable);
if (info.bootable != 0) {
@@ -233,40 +215,40 @@
#ifdef CONFIG_SPL_FS_FAT
if (!spl_start_uboot()) {
- err = spl_load_image_fat_os(spl_image, bootdev, mmc_get_blk_desc(mmc),
- partition);
- if (!err)
- return err;
+ ret = spl_load_image_fat_os(spl_image, bootdev, mmc_get_blk_desc(mmc),
+ partition);
+ if (!ret)
+ return 0;
}
#ifdef CONFIG_SPL_FS_LOAD_PAYLOAD_NAME
- err = spl_load_image_fat(spl_image, bootdev, mmc_get_blk_desc(mmc),
+ ret = spl_load_image_fat(spl_image, bootdev, mmc_get_blk_desc(mmc),
partition,
filename);
- if (!err)
- return err;
+ if (!ret)
+ return ret;
#endif
#endif
#ifdef CONFIG_SPL_FS_EXT4
if (!spl_start_uboot()) {
- err = spl_load_image_ext_os(spl_image, bootdev, mmc_get_blk_desc(mmc),
- partition);
- if (!err)
- return err;
+ ret = spl_load_image_ext_os(spl_image, bootdev, mmc_get_blk_desc(mmc),
+ partition);
+ if (!ret)
+ return 0;
}
#ifdef CONFIG_SPL_FS_LOAD_PAYLOAD_NAME
- err = spl_load_image_ext(spl_image, bootdev, mmc_get_blk_desc(mmc),
+ ret = spl_load_image_ext(spl_image, bootdev, mmc_get_blk_desc(mmc),
partition,
filename);
- if (!err)
- return err;
+ if (!ret)
+ return 0;
#endif
#endif
#if defined(CONFIG_SPL_FS_FAT) || defined(CONFIG_SPL_FS_EXT4)
- err = -ENOENT;
+ ret = -ENOENT;
#endif
- return err;
+ return ret;
}
#endif
@@ -354,87 +336,82 @@
unsigned long raw_sect)
{
u32 boot_mode;
- int err = 0;
+ int ret = 0;
__maybe_unused int part = 0;
int mmc_dev;
/* Perform peripheral init only once for an mmc device */
mmc_dev = spl_mmc_get_device_index(bootdev->boot_device);
if (!mmc || spl_mmc_get_mmc_devnum(mmc) != mmc_dev) {
- err = spl_mmc_find_device(&mmc, bootdev->boot_device);
- if (err)
- return err;
+ ret = spl_mmc_find_device(&mmc, mmc_dev);
+ if (ret)
+ return ret;
- err = mmc_init(mmc);
- if (err) {
+ ret = mmc_init(mmc);
+ if (ret) {
mmc = NULL;
-#ifdef CONFIG_SPL_LIBCOMMON_SUPPORT
- printf("spl: mmc init failed with error: %d\n", err);
-#endif
- return err;
+ printf("spl: mmc init failed with error: %d\n", ret);
+ return ret;
}
}
boot_mode = spl_mmc_boot_mode(mmc, bootdev->boot_device);
- err = -EINVAL;
+ ret = -EINVAL;
switch (boot_mode) {
case MMCSD_MODE_EMMCBOOT:
part = spl_mmc_emmc_boot_partition(mmc);
if (CONFIG_IS_ENABLED(MMC_TINY))
- err = mmc_switch_part(mmc, part);
+ ret = mmc_switch_part(mmc, part);
else
- err = blk_dselect_hwpart(mmc_get_blk_desc(mmc), part);
+ ret = blk_dselect_hwpart(mmc_get_blk_desc(mmc), part);
- if (err) {
-#ifdef CONFIG_SPL_LIBCOMMON_SUPPORT
+ if (ret) {
puts("spl: mmc partition switch failed\n");
-#endif
- return err;
+ return ret;
}
/* Fall through */
case MMCSD_MODE_RAW:
debug("spl: mmc boot mode: raw\n");
if (!spl_start_uboot()) {
- err = mmc_load_image_raw_os(spl_image, bootdev, mmc);
- if (!err)
- return err;
+ ret = mmc_load_image_raw_os(spl_image, bootdev, mmc);
+ if (!ret)
+ return 0;
}
raw_sect = spl_mmc_get_uboot_raw_sector(mmc, raw_sect);
#ifdef CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_PARTITION
- err = mmc_load_image_raw_partition(spl_image, bootdev,
+ ret = mmc_load_image_raw_partition(spl_image, bootdev,
mmc, raw_part,
raw_sect);
- if (!err)
- return err;
+ if (!ret)
+ return 0;
#endif
#ifdef CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR
- err = mmc_load_image_raw_sector(spl_image, bootdev, mmc,
- raw_sect + spl_mmc_raw_uboot_offset(part));
- if (!err)
- return err;
+ ret = mmc_load_image_raw_sector(spl_image, bootdev, mmc,
+ raw_sect +
+ spl_mmc_raw_uboot_offset(part));
+ if (!ret)
+ return 0;
#endif
/* If RAW mode fails, try FS mode. */
#ifdef CONFIG_SYS_MMCSD_FS_BOOT
case MMCSD_MODE_FS:
debug("spl: mmc boot mode: fs\n");
- err = spl_mmc_do_fs_boot(spl_image, bootdev, mmc, filename);
- if (!err)
- return err;
+ ret = spl_mmc_do_fs_boot(spl_image, bootdev, mmc, filename);
+ if (!ret)
+ return 0;
break;
#endif
-#ifdef CONFIG_SPL_LIBCOMMON_SUPPORT
default:
puts("spl: mmc: wrong boot mode\n");
-#endif
}
- return err;
+ return ret;
}
int spl_mmc_load_image(struct spl_image_info *spl_image,
diff --git a/common/spl/spl_nand.c b/common/spl/spl_nand.c
index 5631fa6..22883f4 100644
--- a/common/spl/spl_nand.c
+++ b/common/spl/spl_nand.c
@@ -71,9 +71,7 @@
{
struct spl_load_info load;
- load.priv = &offset;
- spl_set_bl_len(&load, 1);
- load.read = spl_nand_read;
+ spl_load_init(&load, spl_nand_read, &offset, 1);
return spl_load(spl_image, bootdev, &load, 0, offset);
}
diff --git a/common/spl/spl_net.c b/common/spl/spl_net.c
index be7278b..2be7b73 100644
--- a/common/spl/spl_net.c
+++ b/common/spl/spl_net.c
@@ -47,8 +47,7 @@
return rv;
}
- spl_set_bl_len(&load, 1);
- load.read = spl_net_load_read;
+ spl_load_init(&load, spl_net_load_read, NULL, 1);
return spl_load(spl_image, bootdev, &load, 0, 0);
}
#endif
diff --git a/common/spl/spl_nor.c b/common/spl/spl_nor.c
index ed76b5e..1021d93 100644
--- a/common/spl/spl_nor.c
+++ b/common/spl/spl_nor.c
@@ -49,8 +49,7 @@
int ret;
debug("Found FIT\n");
- spl_set_bl_len(&load, 1);
- load.read = spl_nor_load_read;
+ spl_load_init(&load, spl_nor_load_read, NULL, 1);
ret = spl_load_simple_fit(spl_image, &load,
CONFIG_SYS_OS_BASE,
@@ -93,8 +92,7 @@
* Load real U-Boot from its location in NOR flash to its
* defined location in SDRAM
*/
- spl_set_bl_len(&load, 1);
- load.read = spl_nor_load_read;
+ spl_load_init(&load, spl_nor_load_read, NULL, 1);
return spl_load(spl_image, bootdev, &load, 0, spl_nor_get_uboot_base());
}
SPL_LOAD_IMAGE_METHOD("NOR", 0, BOOT_DEVICE_NOR, spl_nor_load_image);
diff --git a/common/spl/spl_ram.c b/common/spl/spl_ram.c
index 5a23841..71b7a83 100644
--- a/common/spl/spl_ram.c
+++ b/common/spl/spl_ram.c
@@ -69,8 +69,7 @@
struct spl_load_info load;
debug("Found FIT\n");
- spl_set_bl_len(&load, 1);
- load.read = spl_ram_load_read;
+ spl_load_init(&load, spl_ram_load_read, NULL, 1);
ret = spl_load_simple_fit(spl_image, &load, 0, header);
} else {
ulong u_boot_pos = spl_get_image_pos();
diff --git a/common/spl/spl_semihosting.c b/common/spl/spl_semihosting.c
index 2047248..f36863f 100644
--- a/common/spl/spl_semihosting.c
+++ b/common/spl/spl_semihosting.c
@@ -43,9 +43,7 @@
}
len = ret;
- load.read = smh_fit_read;
- spl_set_bl_len(&load, 1);
- load.priv = &fd;
+ spl_load_init(&load, smh_fit_read, &fd, 1);
ret = spl_load(spl_image, bootdev, &load, len, 0);
if (ret)
log_debug("could not read %s: %d\n", filename, ret);
diff --git a/common/spl/spl_spi.c b/common/spl/spl_spi.c
index 8ab4803..691a431 100644
--- a/common/spl/spl_spi.c
+++ b/common/spl/spl_spi.c
@@ -77,9 +77,7 @@
return -ENODEV;
}
- load.priv = flash;
- spl_set_bl_len(&load, 1);
- load.read = spl_spi_fit_read;
+ spl_load_init(&load, spl_spi_fit_read, flash, 1);
#if CONFIG_IS_ENABLED(OS_BOOT)
if (spl_start_uboot()) {
diff --git a/common/spl/spl_upl.c b/common/spl/spl_upl.c
new file mode 100644
index 0000000..067d437
--- /dev/null
+++ b/common/spl/spl_upl.c
@@ -0,0 +1,172 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * UPL handoff parsing
+ *
+ * Copyright 2024 Google LLC
+ * Written by Simon Glass <sjg@chromium.org>
+ */
+
+#define LOG_CATEGORY UCLASS_BOOTSTD
+
+#include <alist.h>
+#include <bloblist.h>
+#include <dm.h>
+#include <image.h>
+#include <mapmem.h>
+#include <serial.h>
+#include <spl.h>
+#include <upl.h>
+#include <video.h>
+#include <asm/global_data.h>
+#include <dm/read.h>
+#include <dm/uclass-internal.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+struct upl s_upl;
+
+void upl_set_fit_addr(ulong fit)
+{
+ struct upl *upl = &s_upl;
+
+ upl->fit = fit;
+}
+
+void upl_set_fit_info(ulong fit, int conf_offset, ulong entry_addr)
+{
+ struct upl *upl = &s_upl;
+
+ upl->fit = fit;
+ upl->conf_offset = conf_offset;
+ log_debug("upl: add fit %lx conf %x\n", fit, conf_offset);
+}
+
+int _upl_add_image(int node, ulong load_addr, ulong size, const char *desc)
+{
+ struct upl *upl = &s_upl;
+ struct upl_image img;
+
+ img.load = load_addr;
+ img.size = size;
+ img.offset = node;
+ img.description = desc;
+ if (!alist_add(&upl->image, img))
+ return -ENOMEM;
+ log_debug("upl: add image %s at %lx size %lx\n", desc, load_addr, size);
+
+ return 0;
+}
+
+static int write_serial(struct upl_serial *ser)
+{
+ struct udevice *dev = gd->cur_serial_dev;
+ struct serial_device_info info;
+ struct memregion region;
+ int ret;
+
+ if (!dev)
+ return log_msg_ret("ser", -ENOENT);
+ ret = serial_getinfo(dev, &info);
+ if (ret)
+ return log_msg_ret("inf", ret);
+
+ ser->compatible = ofnode_read_string(dev_ofnode(dev), "compatible");
+ ser->clock_frequency = info.clock;
+ ser->current_speed = gd->baudrate;
+ region.base = info.addr;
+ region.size = info.size;
+ alist_init_struct(&ser->reg, struct memregion);
+ if (!alist_add(&ser->reg, region))
+ return -ENOMEM;
+ ser->reg_io_shift = info.reg_shift;
+ ser->reg_offset = info.reg_offset;
+ ser->reg_io_width = info.reg_width;
+ ser->virtual_reg = 0;
+ ser->access_type = info.addr_space;
+
+ return 0;
+}
+
+static int write_graphics(struct upl_graphics *gra)
+{
+ struct video_uc_plat *plat;
+ struct video_priv *priv;
+ struct memregion region;
+ struct udevice *dev;
+
+ alist_init_struct(&gra->reg, struct memregion);
+ uclass_find_first_device(UCLASS_VIDEO, &dev);
+ if (!dev || !device_active(dev))
+ return log_msg_ret("vid", -ENOENT);
+
+ plat = dev_get_uclass_plat(dev);
+ region.base = plat->base;
+ region.size = plat->size;
+ if (!alist_add(&gra->reg, region))
+ return log_msg_ret("reg", -ENOMEM);
+
+ priv = dev_get_uclass_priv(dev);
+ gra->width = priv->xsize;
+ gra->height = priv->ysize;
+ gra->stride = priv->line_length; /* private field */
+ switch (priv->format) {
+ case VIDEO_RGBA8888:
+ case VIDEO_X8R8G8B8:
+ gra->format = UPLGF_ARGB32;
+ break;
+ case VIDEO_X8B8G8R8:
+ gra->format = UPLGF_ABGR32;
+ break;
+ case VIDEO_X2R10G10B10:
+ log_debug("device '%s': VIDEO_X2R10G10B10 not supported\n",
+ dev->name);
+ return log_msg_ret("for", -EPROTO);
+ case VIDEO_UNKNOWN:
+ log_debug("device '%s': Unknown video format\n", dev->name);
+ return log_msg_ret("for", -EPROTO);
+ }
+
+ return 0;
+}
+
+int spl_write_upl_handoff(struct spl_image_info *spl_image)
+{
+ struct upl *upl = &s_upl;
+ struct abuf buf;
+ ofnode root;
+ void *ptr;
+ int ret;
+
+ log_debug("UPL: Writing handoff - image_count=%d\n", upl->image.count);
+ upl->addr_cells = IS_ENABLED(CONFIG_PHYS_64BIT) ? 2 : 1;
+ upl->size_cells = IS_ENABLED(CONFIG_PHYS_64BIT) ? 2 : 1;
+ upl->bootmode = UPLBM_DEFAULT;
+ ret = write_serial(&upl->serial);
+ if (ret)
+ return log_msg_ret("ser", ret);
+ ret = write_graphics(&upl->graphics);
+ if (ret && ret != -ENOENT)
+ return log_msg_ret("gra", ret);
+
+ root = ofnode_root();
+ ret = upl_write_handoff(upl, root, true);
+ if (ret)
+ return log_msg_ret("wr", ret);
+
+ ret = oftree_to_fdt(oftree_default(), &buf);
+ if (ret)
+ return log_msg_ret("fdt", ret);
+ log_debug("FDT size %zx\n", abuf_size(&buf));
+
+ ptr = bloblist_add(BLOBLISTT_CONTROL_FDT, abuf_size(&buf), 0);
+ if (!ptr)
+ return log_msg_ret("blo", -ENOENT);
+ memcpy(ptr, abuf_data(&buf), abuf_size(&buf));
+
+ return 0;
+}
+
+void spl_upl_init(void)
+{
+ upl_init(&s_upl);
+}
diff --git a/common/spl/spl_ymodem.c b/common/spl/spl_ymodem.c
index 4c7222a..2be9571 100644
--- a/common/spl/spl_ymodem.c
+++ b/common/spl/spl_ymodem.c
@@ -132,11 +132,9 @@
struct ymodem_fit_info info;
debug("Found FIT\n");
- load.priv = (void *)&info;
- spl_set_bl_len(&load, 1);
+ spl_load_init(&load, ymodem_read_fit, (void *)&info, 1);
info.buf = buf;
info.image_read = BUF_SIZE;
- load.read = ymodem_read_fit;
ret = spl_load_simple_fit(spl_image, &load, 0, (void *)buf);
size = info.image_read;
diff --git a/configs/MPC837XERDB_defconfig b/configs/MPC837XERDB_defconfig
index 9eac43a..dd30e8d 100644
--- a/configs/MPC837XERDB_defconfig
+++ b/configs/MPC837XERDB_defconfig
@@ -139,7 +139,6 @@
CONFIG_BOOTP_BOOTFILESIZE=y
CONFIG_CMD_MII=y
CONFIG_CMD_PING=y
-CONFIG_CMD_DATE=y
CONFIG_CMD_EXT2=y
CONFIG_CMD_FAT=y
CONFIG_OF_CONTROL=y
diff --git a/configs/am335x_baltos_defconfig b/configs/am335x_baltos_defconfig
index f8dfd1d..3fcebc6 100644
--- a/configs/am335x_baltos_defconfig
+++ b/configs/am335x_baltos_defconfig
@@ -3,8 +3,6 @@
CONFIG_ARCH_OMAP2PLUS=y
CONFIG_SPL_LIBCOMMON_SUPPORT=y
CONFIG_SPL_LIBGENERIC_SUPPORT=y
-CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y
-CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x4030ff00
CONFIG_DEFAULT_DEVICE_TREE="am335x-baltos"
CONFIG_AM33XX=y
CONFIG_TARGET_AM335X_BALTOS=y
@@ -19,6 +17,7 @@
CONFIG_OF_BOARD_SETUP=y
CONFIG_BOOTCOMMAND="run findfdt; run usbboot;run mmcboot;setenv mmcdev 1; setenv bootpart 1:2; run mmcboot;run nandboot;"
CONFIG_SYS_CONSOLE_INFO_QUIET=y
+CONFIG_SPL_BOARD_INIT=y
CONFIG_SPL_SYS_MALLOC=y
CONFIG_SPL_SYS_MALLOC_SIZE=0x800000
CONFIG_SPL_FS_EXT4=y
diff --git a/configs/am335x_evm_defconfig b/configs/am335x_evm_defconfig
index cabc181..5dd0b32 100644
--- a/configs/am335x_evm_defconfig
+++ b/configs/am335x_evm_defconfig
@@ -2,8 +2,6 @@
CONFIG_ARCH_CPU_INIT=y
CONFIG_ARCH_OMAP2PLUS=y
CONFIG_TI_COMMON_CMD_OPTIONS=y
-CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y
-CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x4030ff00
CONFIG_SF_DEFAULT_SPEED=24000000
CONFIG_DEFAULT_DEVICE_TREE="am335x-evm"
CONFIG_AM33XX=y
diff --git a/configs/am335x_evm_spiboot_defconfig b/configs/am335x_evm_spiboot_defconfig
index 8239f5f..a55aace 100644
--- a/configs/am335x_evm_spiboot_defconfig
+++ b/configs/am335x_evm_spiboot_defconfig
@@ -2,8 +2,6 @@
CONFIG_ARCH_CPU_INIT=y
CONFIG_ARCH_OMAP2PLUS=y
CONFIG_TI_COMMON_CMD_OPTIONS=y
-CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y
-CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x4030ff00
CONFIG_SF_DEFAULT_SPEED=24000000
CONFIG_ENV_OFFSET=0x100000
CONFIG_SPL_DM_SPI=y
diff --git a/configs/am335x_guardian_defconfig b/configs/am335x_guardian_defconfig
index 7513854..6b36f6e 100644
--- a/configs/am335x_guardian_defconfig
+++ b/configs/am335x_guardian_defconfig
@@ -3,8 +3,6 @@
CONFIG_ARCH_OMAP2PLUS=y
CONFIG_SPL_LIBCOMMON_SUPPORT=y
CONFIG_SPL_LIBGENERIC_SUPPORT=y
-CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y
-CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x4030fef0
CONFIG_ENV_SIZE=0x40000
CONFIG_ENV_OFFSET=0x500000
CONFIG_DEFAULT_DEVICE_TREE="am335x-guardian"
@@ -31,10 +29,11 @@
CONFIG_AUTOBOOT_STOP_STR=" "
CONFIG_SYS_CONSOLE_INFO_QUIET=y
CONFIG_ARCH_MISC_INIT=y
+CONFIG_SPL_BOARD_INIT=y
# CONFIG_SPL_RAW_IMAGE_SUPPORT is not set
CONFIG_SPL_SYS_MALLOC=y
CONFIG_SPL_SYS_MALLOC_SIZE=0x800000
-# CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR is not set
+# CONFIG_SPL_SYS_MMCSD_RAW_MODE is not set
CONFIG_SPL_ENV_SUPPORT=y
CONFIG_SPL_ETH=y
CONFIG_SPL_I2C=y
diff --git a/configs/am335x_hs_evm_defconfig b/configs/am335x_hs_evm_defconfig
index 3694cc3..d780239 100644
--- a/configs/am335x_hs_evm_defconfig
+++ b/configs/am335x_hs_evm_defconfig
@@ -3,8 +3,6 @@
CONFIG_ARCH_OMAP2PLUS=y
CONFIG_TI_SECURE_DEVICE=y
CONFIG_TI_COMMON_CMD_OPTIONS=y
-CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y
-CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x4030ff00
CONFIG_SF_DEFAULT_SPEED=24000000
CONFIG_DEFAULT_DEVICE_TREE="am335x-evm"
CONFIG_SPL_TEXT_BASE=0x40300350
diff --git a/configs/am335x_hs_evm_spi_defconfig b/configs/am335x_hs_evm_spi_defconfig
new file mode 100644
index 0000000..df00984
--- /dev/null
+++ b/configs/am335x_hs_evm_spi_defconfig
@@ -0,0 +1,26 @@
+#include <configs/am335x_hs_evm_defconfig>
+
+CONFIG_ARM=y
+CONFIG_ARCH_OMAP2PLUS=y
+
+CONFIG_SPL_SPI_FLASH_SUPPORT=y
+CONFIG_SPL_SPI_SUPPORT=y
+
+CONFIG_SPI_BOOT=y
+
+CONFIG_SPL_MTD_SUPPORT=y
+
+CONFIG_CMD_MMC=y
+CONFIG_CMD_SF=y
+CONFIG_CMD_SPI=y
+CONFIG_CMD_I2C=y
+CONFIG_CMD_USB=y
+CONFIG_CMD_DFU=y
+CONFIG_CMD_GPIO=y
+# CONFIG_CMD_SETEXPR is not set
+CONFIG_CMD_EXT4_WRITE=y
+
+CONFIG_BLK=n
+
+CONFIG_USE_TINY_PRINTF=y
+CONFIG_SPL_OF_LIBFDT=y
diff --git a/configs/am335x_hs_evm_uart_defconfig b/configs/am335x_hs_evm_uart_defconfig
index a99b7b4..bd97994 100644
--- a/configs/am335x_hs_evm_uart_defconfig
+++ b/configs/am335x_hs_evm_uart_defconfig
@@ -3,8 +3,6 @@
CONFIG_ARCH_OMAP2PLUS=y
CONFIG_TI_SECURE_DEVICE=y
CONFIG_TI_COMMON_CMD_OPTIONS=y
-CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y
-CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x4030ff00
CONFIG_SF_DEFAULT_SPEED=24000000
CONFIG_DEFAULT_DEVICE_TREE="am335x-evm"
CONFIG_SPL_TEXT_BASE=0x40301950
diff --git a/configs/am335x_igep003x_defconfig b/configs/am335x_igep003x_defconfig
index ddffd4f..1994388 100644
--- a/configs/am335x_igep003x_defconfig
+++ b/configs/am335x_igep003x_defconfig
@@ -4,8 +4,6 @@
CONFIG_SPL_GPIO=y
CONFIG_SPL_LIBCOMMON_SUPPORT=y
CONFIG_SPL_LIBGENERIC_SUPPORT=y
-CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y
-CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x4030ff00
CONFIG_ENV_SIZE=0x18000
CONFIG_DEFAULT_DEVICE_TREE="am335x-base0033"
CONFIG_AM33XX=y
@@ -76,7 +74,7 @@
CONFIG_VERSION_VARIABLE=y
CONFIG_NET_RETRY_COUNT=10
CONFIG_BOOTP_SEND_HOSTNAME=y
-CONFIG_SYS_I2C_LEGACY=y
+CONFIG_DM_I2C=y
CONFIG_SPL_SYS_I2C_LEGACY=y
CONFIG_MMC_OMAP_HS=y
CONFIG_MTD=y
diff --git a/configs/am335x_pdu001_defconfig b/configs/am335x_pdu001_defconfig
index febe5eb..d9acc81 100644
--- a/configs/am335x_pdu001_defconfig
+++ b/configs/am335x_pdu001_defconfig
@@ -4,8 +4,6 @@
CONFIG_SYS_MALLOC_F_LEN=0x1200
CONFIG_SPL_LIBCOMMON_SUPPORT=y
CONFIG_SPL_LIBGENERIC_SUPPORT=y
-CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y
-CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x4030ff00
CONFIG_ENV_SIZE=0x4000
CONFIG_DM_GPIO=y
CONFIG_DEFAULT_DEVICE_TREE="am335x-pdu001"
@@ -24,9 +22,10 @@
CONFIG_AUTOBOOT_STOP_STR=" "
CONFIG_BOOTCOMMAND="run eval_boot_device;part uuid mmc ${mmc_boot}:${root_fs_partition} root_fs_partuuid;setenv bootargs console=${console} vt.global_cursor_default=0 root=PARTUUID=${root_fs_partuuid} rootfstype=ext4 rootwait rootdelay=1;fatload mmc ${mmc_boot} ${fdtaddr} ${fdtfile};fatload mmc ${mmc_boot} ${loadaddr} ${bootfile};bootz ${loadaddr} - ${fdtaddr}"
CONFIG_BOARD_LATE_INIT=y
+CONFIG_SPL_BOARD_INIT=y
CONFIG_SPL_SYS_MALLOC=y
CONFIG_SPL_SYS_MALLOC_SIZE=0x800000
-# CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR is not set
+# CONFIG_SPL_SYS_MMCSD_RAW_MODE is not set
CONFIG_SPL_I2C=y
# CONFIG_SPL_NAND_SUPPORT is not set
CONFIG_SPL_POWER=y
diff --git a/configs/am335x_shc_defconfig b/configs/am335x_shc_defconfig
index 47c08e5..72933ba 100644
--- a/configs/am335x_shc_defconfig
+++ b/configs/am335x_shc_defconfig
@@ -4,8 +4,6 @@
CONFIG_SPL_GPIO=y
CONFIG_SPL_LIBCOMMON_SUPPORT=y
CONFIG_SPL_LIBGENERIC_SUPPORT=y
-CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y
-CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x4030ff00
CONFIG_ENV_SIZE=0x1000
CONFIG_ENV_OFFSET=0x7000
CONFIG_DEFAULT_DEVICE_TREE="am335x-shc"
@@ -33,6 +31,7 @@
CONFIG_DEFAULT_FDT_FILE="am335x-shc"
CONFIG_SYS_PBSIZE=1049
CONFIG_SYS_CONSOLE_INFO_QUIET=y
+CONFIG_SPL_BOARD_INIT=y
CONFIG_SPL_SYS_MALLOC_SIMPLE=y
CONFIG_SPL_SYS_MALLOC=y
CONFIG_SPL_SYS_MALLOC_SIZE=0x800000
@@ -66,10 +65,12 @@
CONFIG_VERSION_VARIABLE=y
CONFIG_NET_RETRY_COUNT=10
CONFIG_BOOTP_SEND_HOSTNAME=y
-CONFIG_SYS_I2C_LEGACY=y
+CONFIG_DM_I2C=y
CONFIG_SPL_SYS_I2C_LEGACY=y
CONFIG_SYS_I2C_SLAVE=0x1
CONFIG_SYS_I2C_SPEED=400000
+CONFIG_MISC=y
+CONFIG_I2C_EEPROM=y
CONFIG_MMC_OMAP_HS=y
CONFIG_HSMMC2_8BIT=y
CONFIG_PHY_ADDR_ENABLE=y
diff --git a/configs/am335x_shc_ict_defconfig b/configs/am335x_shc_ict_defconfig
index c7618c5..b8a3227 100644
--- a/configs/am335x_shc_ict_defconfig
+++ b/configs/am335x_shc_ict_defconfig
@@ -4,8 +4,6 @@
CONFIG_SPL_GPIO=y
CONFIG_SPL_LIBCOMMON_SUPPORT=y
CONFIG_SPL_LIBGENERIC_SUPPORT=y
-CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y
-CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x4030ff00
CONFIG_ENV_SIZE=0x1000
CONFIG_ENV_OFFSET=0x7000
CONFIG_DEFAULT_DEVICE_TREE="am335x-shc"
@@ -31,6 +29,7 @@
CONFIG_DEFAULT_FDT_FILE="am335x-shc"
CONFIG_SYS_PBSIZE=1049
CONFIG_SYS_CONSOLE_INFO_QUIET=y
+CONFIG_SPL_BOARD_INIT=y
CONFIG_SPL_SYS_MALLOC_SIMPLE=y
CONFIG_SPL_SYS_MALLOC=y
CONFIG_SPL_SYS_MALLOC_SIZE=0x800000
@@ -64,10 +63,12 @@
CONFIG_VERSION_VARIABLE=y
CONFIG_NET_RETRY_COUNT=10
CONFIG_BOOTP_SEND_HOSTNAME=y
-CONFIG_SYS_I2C_LEGACY=y
+CONFIG_DM_I2C=y
CONFIG_SPL_SYS_I2C_LEGACY=y
CONFIG_SYS_I2C_SLAVE=0x1
CONFIG_SYS_I2C_SPEED=400000
+CONFIG_MISC=y
+CONFIG_I2C_EEPROM=y
CONFIG_MMC_OMAP_HS=y
CONFIG_HSMMC2_8BIT=y
CONFIG_PHY_ADDR_ENABLE=y
diff --git a/configs/am335x_shc_netboot_defconfig b/configs/am335x_shc_netboot_defconfig
index 9342658..b25a4de 100644
--- a/configs/am335x_shc_netboot_defconfig
+++ b/configs/am335x_shc_netboot_defconfig
@@ -4,8 +4,6 @@
CONFIG_SPL_GPIO=y
CONFIG_SPL_LIBCOMMON_SUPPORT=y
CONFIG_SPL_LIBGENERIC_SUPPORT=y
-CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y
-CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x4030ff00
CONFIG_ENV_SIZE=0x1000
CONFIG_ENV_OFFSET=0x7000
CONFIG_DEFAULT_DEVICE_TREE="am335x-shc"
@@ -34,6 +32,7 @@
CONFIG_DEFAULT_FDT_FILE="am335x-shc"
CONFIG_SYS_PBSIZE=1049
CONFIG_SYS_CONSOLE_INFO_QUIET=y
+CONFIG_SPL_BOARD_INIT=y
CONFIG_SPL_SYS_MALLOC_SIMPLE=y
CONFIG_SPL_SYS_MALLOC=y
CONFIG_SPL_SYS_MALLOC_SIZE=0x800000
@@ -67,10 +66,12 @@
CONFIG_VERSION_VARIABLE=y
CONFIG_NET_RETRY_COUNT=10
CONFIG_BOOTP_SEND_HOSTNAME=y
-CONFIG_SYS_I2C_LEGACY=y
+CONFIG_DM_I2C=y
CONFIG_SPL_SYS_I2C_LEGACY=y
CONFIG_SYS_I2C_SLAVE=0x1
CONFIG_SYS_I2C_SPEED=400000
+CONFIG_MISC=y
+CONFIG_I2C_EEPROM=y
CONFIG_MMC_OMAP_HS=y
CONFIG_HSMMC2_8BIT=y
CONFIG_PHY_ADDR_ENABLE=y
diff --git a/configs/am335x_shc_sdboot_defconfig b/configs/am335x_shc_sdboot_defconfig
index 439f9b8..8486ccb 100644
--- a/configs/am335x_shc_sdboot_defconfig
+++ b/configs/am335x_shc_sdboot_defconfig
@@ -4,8 +4,6 @@
CONFIG_SPL_GPIO=y
CONFIG_SPL_LIBCOMMON_SUPPORT=y
CONFIG_SPL_LIBGENERIC_SUPPORT=y
-CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y
-CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x4030ff00
CONFIG_ENV_SIZE=0x1000
CONFIG_ENV_OFFSET=0x7000
CONFIG_DEFAULT_DEVICE_TREE="am335x-shc"
@@ -34,6 +32,7 @@
CONFIG_DEFAULT_FDT_FILE="am335x-shc"
CONFIG_SYS_PBSIZE=1049
CONFIG_SYS_CONSOLE_INFO_QUIET=y
+CONFIG_SPL_BOARD_INIT=y
CONFIG_SPL_SYS_MALLOC_SIMPLE=y
CONFIG_SPL_SYS_MALLOC=y
CONFIG_SPL_SYS_MALLOC_SIZE=0x800000
@@ -66,10 +65,12 @@
CONFIG_VERSION_VARIABLE=y
CONFIG_NET_RETRY_COUNT=10
CONFIG_BOOTP_SEND_HOSTNAME=y
-CONFIG_SYS_I2C_LEGACY=y
+CONFIG_DM_I2C=y
CONFIG_SPL_SYS_I2C_LEGACY=y
CONFIG_SYS_I2C_SLAVE=0x1
CONFIG_SYS_I2C_SPEED=400000
+CONFIG_MISC=y
+CONFIG_I2C_EEPROM=y
CONFIG_MMC_OMAP_HS=y
CONFIG_HSMMC2_8BIT=y
CONFIG_PHY_ADDR_ENABLE=y
diff --git a/configs/am335x_sl50_defconfig b/configs/am335x_sl50_defconfig
index 88122bd..7444e55 100644
--- a/configs/am335x_sl50_defconfig
+++ b/configs/am335x_sl50_defconfig
@@ -4,8 +4,6 @@
CONFIG_SPL_GPIO=y
CONFIG_SPL_LIBCOMMON_SUPPORT=y
CONFIG_SPL_LIBGENERIC_SUPPORT=y
-CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y
-CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x4030ff00
CONFIG_ENV_OFFSET=0x0
CONFIG_DEFAULT_DEVICE_TREE="am335x-sl50"
CONFIG_AM33XX=y
@@ -24,6 +22,7 @@
CONFIG_AUTOBOOT_DELAY_STR="d"
CONFIG_AUTOBOOT_STOP_STR=" "
CONFIG_SYS_CONSOLE_INFO_QUIET=y
+CONFIG_SPL_BOARD_INIT=y
CONFIG_SPL_SYS_MALLOC=y
CONFIG_SPL_SYS_MALLOC_SIZE=0x800000
CONFIG_SPL_ENV_SUPPORT=y
@@ -66,7 +65,7 @@
CONFIG_BOOTP_SEND_HOSTNAME=y
CONFIG_BOOTCOUNT_LIMIT=y
CONFIG_SYS_BOOTCOUNT_BE=y
-CONFIG_SYS_I2C_LEGACY=y
+CONFIG_DM_I2C=y
CONFIG_SPL_SYS_I2C_LEGACY=y
CONFIG_SYS_I2C_EEPROM_ADDR=0x50
CONFIG_MMC_OMAP_HS=y
diff --git a/configs/am3517_evm_defconfig b/configs/am3517_evm_defconfig
index 3236f1d..4c1f664 100644
--- a/configs/am3517_evm_defconfig
+++ b/configs/am3517_evm_defconfig
@@ -5,15 +5,10 @@
CONFIG_TEXT_BASE=0x80100000
CONFIG_SYS_MALLOC_F_LEN=0x4000
CONFIG_TI_COMMON_CMD_OPTIONS=y
-CONFIG_NR_DRAM_BANKS=2
CONFIG_ENV_SOURCE_FILE="am3517evm"
-CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y
-CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x4020ff00
CONFIG_DEFAULT_DEVICE_TREE="ti/omap/am3517-evm"
-CONFIG_SPL_TEXT_BASE=0x40200000
CONFIG_TARGET_AM3517_EVM=y
CONFIG_EMIF4=y
-CONFIG_SYS_MONITOR_LEN=262144
CONFIG_SPL_SYS_MALLOC_F_LEN=0x2500
CONFIG_SPL=y
CONFIG_LTO=y
@@ -21,11 +16,10 @@
CONFIG_BOOTDELAY=10
CONFIG_BOOTCOMMAND="mmc dev ${mmcdev}; if mmc rescan; then echo SD/MMC found on device $mmcdev; if run loadbootenv; then run importbootenv; fi; echo Checking if uenvcmd is set ...; if test -n $uenvcmd; then echo Running uenvcmd ...; run uenvcmd; fi; echo Running default loadimage ...; setenv bootfile zImage; if run loadimage; then run loadfdt; run mmcboot; fi; else run nandboot; fi"
CONFIG_SYS_PBSIZE=1054
-CONFIG_SPL_MAX_SIZE=0xec00
CONFIG_SPL_SYS_MALLOC_SIMPLE=y
CONFIG_SPL_SYS_MALLOC=y
CONFIG_SPL_SYS_MALLOC_SIZE=0x800000
-# CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR is not set
+# CONFIG_SPL_SYS_MMCSD_RAW_MODE is not set
# CONFIG_SPL_FS_EXT4 is not set
# CONFIG_SPL_I2C is not set
CONFIG_SPL_MTD=y
diff --git a/configs/am43xx_evm_defconfig b/configs/am43xx_evm_defconfig
index d73b1cb..0fc4c0f 100644
--- a/configs/am43xx_evm_defconfig
+++ b/configs/am43xx_evm_defconfig
@@ -3,8 +3,6 @@
CONFIG_ARCH_CPU_INIT=y
CONFIG_ARCH_OMAP2PLUS=y
CONFIG_TI_COMMON_CMD_OPTIONS=y
-CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y
-CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x4033ff00
CONFIG_SF_DEFAULT_SPEED=48000000
CONFIG_ENV_SIZE=0x10000
CONFIG_DM_GPIO=y
diff --git a/configs/am43xx_evm_qspiboot_defconfig b/configs/am43xx_evm_qspiboot_defconfig
index 89e2125..c538c1a 100644
--- a/configs/am43xx_evm_qspiboot_defconfig
+++ b/configs/am43xx_evm_qspiboot_defconfig
@@ -4,8 +4,6 @@
CONFIG_ARCH_OMAP2PLUS=y
CONFIG_TEXT_BASE=0x30000000
CONFIG_SYS_MALLOC_F_LEN=0x400
-CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y
-CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x4033ff00
CONFIG_SF_DEFAULT_SPEED=48000000
CONFIG_ENV_SIZE=0x10000
CONFIG_ENV_OFFSET=0x110000
diff --git a/configs/am43xx_evm_rtconly_defconfig b/configs/am43xx_evm_rtconly_defconfig
index 2ff0119..0fe5479 100644
--- a/configs/am43xx_evm_rtconly_defconfig
+++ b/configs/am43xx_evm_rtconly_defconfig
@@ -3,8 +3,6 @@
CONFIG_ARCH_CPU_INIT=y
CONFIG_ARCH_OMAP2PLUS=y
CONFIG_TI_COMMON_CMD_OPTIONS=y
-CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y
-CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x4033ff00
CONFIG_SF_DEFAULT_SPEED=48000000
CONFIG_ENV_SIZE=0x10000
CONFIG_DM_GPIO=y
diff --git a/configs/am43xx_evm_usbhost_boot_defconfig b/configs/am43xx_evm_usbhost_boot_defconfig
index 845b686..c4693bc 100644
--- a/configs/am43xx_evm_usbhost_boot_defconfig
+++ b/configs/am43xx_evm_usbhost_boot_defconfig
@@ -2,8 +2,6 @@
CONFIG_SKIP_LOWLEVEL_INIT=y
CONFIG_ARCH_CPU_INIT=y
CONFIG_ARCH_OMAP2PLUS=y
-CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y
-CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x4033ff00
CONFIG_SF_DEFAULT_SPEED=48000000
CONFIG_ENV_SIZE=0x10000
CONFIG_DM_GPIO=y
diff --git a/configs/am43xx_hs_evm_defconfig b/configs/am43xx_hs_evm_defconfig
index ff5073c..980ef13 100644
--- a/configs/am43xx_hs_evm_defconfig
+++ b/configs/am43xx_hs_evm_defconfig
@@ -4,8 +4,6 @@
CONFIG_ARCH_OMAP2PLUS=y
CONFIG_TI_SECURE_DEVICE=y
CONFIG_TI_COMMON_CMD_OPTIONS=y
-CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y
-CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x4033ff00
CONFIG_SF_DEFAULT_SPEED=48000000
CONFIG_ENV_SIZE=0x10000
CONFIG_DM_GPIO=y
diff --git a/configs/am43xx_hs_evm_qspi_defconfig b/configs/am43xx_hs_evm_qspi_defconfig
index 5ef59d8..75725e1 100644
--- a/configs/am43xx_hs_evm_qspi_defconfig
+++ b/configs/am43xx_hs_evm_qspi_defconfig
@@ -3,8 +3,6 @@
# CONFIG_SYS_THUMB_BUILD is not set
CONFIG_ARCH_OMAP2PLUS=y
CONFIG_TI_SECURE_DEVICE=y
-CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y
-CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x4033ff00
CONFIG_SF_DEFAULT_SPEED=48000000
CONFIG_ENV_SIZE=0x10000
CONFIG_ENV_OFFSET=0x110000
diff --git a/configs/am57xx_evm_defconfig b/configs/am57xx_evm_defconfig
index 7c3ceeb..587af53 100644
--- a/configs/am57xx_evm_defconfig
+++ b/configs/am57xx_evm_defconfig
@@ -1,9 +1,6 @@
CONFIG_ARM=y
CONFIG_ARCH_OMAP2PLUS=y
CONFIG_TI_COMMON_CMD_OPTIONS=y
-CONFIG_NR_DRAM_BANKS=2
-CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y
-CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x4037ff00
CONFIG_SF_DEFAULT_SPEED=76800000
CONFIG_DM_GPIO=y
CONFIG_SPL_DM_SPI=y
diff --git a/configs/am57xx_hs_evm_defconfig b/configs/am57xx_hs_evm_defconfig
index 1f7eca4..b790897 100644
--- a/configs/am57xx_hs_evm_defconfig
+++ b/configs/am57xx_hs_evm_defconfig
@@ -2,9 +2,6 @@
CONFIG_ARCH_OMAP2PLUS=y
CONFIG_TI_SECURE_DEVICE=y
CONFIG_TI_COMMON_CMD_OPTIONS=y
-CONFIG_NR_DRAM_BANKS=2
-CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y
-CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x4037ff00
CONFIG_SF_DEFAULT_SPEED=76800000
CONFIG_DM_GPIO=y
CONFIG_SPL_DM_SPI=y
diff --git a/configs/am57xx_hs_evm_usb_defconfig b/configs/am57xx_hs_evm_usb_defconfig
index 807e1d6..450751b 100644
--- a/configs/am57xx_hs_evm_usb_defconfig
+++ b/configs/am57xx_hs_evm_usb_defconfig
@@ -2,9 +2,6 @@
CONFIG_ARCH_OMAP2PLUS=y
CONFIG_TI_SECURE_DEVICE=y
CONFIG_TI_COMMON_CMD_OPTIONS=y
-CONFIG_NR_DRAM_BANKS=2
-CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y
-CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x4037ff00
CONFIG_SF_DEFAULT_SPEED=76800000
CONFIG_DM_GPIO=y
CONFIG_SPL_DM_SPI=y
diff --git a/configs/am62ax_evm_a53_defconfig b/configs/am62ax_evm_a53_defconfig
index 4a351cd..b905ff7 100644
--- a/configs/am62ax_evm_a53_defconfig
+++ b/configs/am62ax_evm_a53_defconfig
@@ -30,6 +30,7 @@
CONFIG_SPL_MAX_SIZE=0x58000
CONFIG_SPL_PAD_TO=0x0
CONFIG_SPL_SYS_MALLOC_SIMPLE=y
+CONFIG_SPL_SYS_MMCSD_RAW_MODE=y
CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR=y
CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x1400
CONFIG_SPL_FS_LOAD_PAYLOAD_NAME="u-boot.img"
diff --git a/configs/am62ax_evm_r5_defconfig b/configs/am62ax_evm_r5_defconfig
index 44ccb6b..092d083 100644
--- a/configs/am62ax_evm_r5_defconfig
+++ b/configs/am62ax_evm_r5_defconfig
@@ -39,6 +39,7 @@
CONFIG_SPL_HAS_CUSTOM_MALLOC_START=y
CONFIG_SPL_CUSTOM_SYS_MALLOC_ADDR=0x84000000
CONFIG_SPL_EARLY_BSS=y
+CONFIG_SPL_SYS_MMCSD_RAW_MODE=y
CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR=y
CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x400
CONFIG_SPL_DMA=y
diff --git a/configs/am62px_evm_a53_defconfig b/configs/am62px_evm_a53_defconfig
index 87005d0..9635beb 100644
--- a/configs/am62px_evm_a53_defconfig
+++ b/configs/am62px_evm_a53_defconfig
@@ -37,6 +37,7 @@
CONFIG_SPL_MAX_SIZE=0x58000
CONFIG_SPL_PAD_TO=0x0
CONFIG_SPL_SYS_MALLOC_SIMPLE=y
+CONFIG_SPL_SYS_MMCSD_RAW_MODE=y
CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR=y
CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x1400
CONFIG_SPL_DMA=y
diff --git a/configs/am62px_evm_r5_defconfig b/configs/am62px_evm_r5_defconfig
index ace5569..4f7be44 100644
--- a/configs/am62px_evm_r5_defconfig
+++ b/configs/am62px_evm_r5_defconfig
@@ -40,6 +40,7 @@
CONFIG_SPL_SYS_MALLOC_SIMPLE=y
CONFIG_SPL_SEPARATE_BSS=y
CONFIG_SPL_EARLY_BSS=y
+CONFIG_SPL_SYS_MMCSD_RAW_MODE=y
CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR=y
CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x400
CONFIG_SPL_DMA=y
diff --git a/configs/am62x_beagleplay_a53_defconfig b/configs/am62x_beagleplay_a53_defconfig
index 79c82d1..af54f96 100644
--- a/configs/am62x_beagleplay_a53_defconfig
+++ b/configs/am62x_beagleplay_a53_defconfig
@@ -40,6 +40,7 @@
CONFIG_SPL_MAX_SIZE=0x58000
CONFIG_SPL_SYS_REPORT_STACK_F_USAGE=y
CONFIG_SPL_SYS_MALLOC_SIMPLE=y
+CONFIG_SPL_SYS_MMCSD_RAW_MODE=y
CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR=y
CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x1400
CONFIG_SPL_FS_LOAD_PAYLOAD_NAME="u-boot.img"
diff --git a/configs/am62x_beagleplay_r5_defconfig b/configs/am62x_beagleplay_r5_defconfig
index d0cc4f5..ee4c43f 100644
--- a/configs/am62x_beagleplay_r5_defconfig
+++ b/configs/am62x_beagleplay_r5_defconfig
@@ -45,6 +45,7 @@
CONFIG_SPL_CUSTOM_SYS_MALLOC_ADDR=0x84000000
CONFIG_SPL_SYS_MALLOC_SIZE=0x1000000
CONFIG_SPL_EARLY_BSS=y
+CONFIG_SPL_SYS_MMCSD_RAW_MODE=y
CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR=y
CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x400
CONFIG_SPL_DM_MAILBOX=y
diff --git a/configs/am62x_evm_a53_defconfig b/configs/am62x_evm_a53_defconfig
index ca993b4..0b7ee94 100644
--- a/configs/am62x_evm_a53_defconfig
+++ b/configs/am62x_evm_a53_defconfig
@@ -38,6 +38,7 @@
CONFIG_SPL_MAX_SIZE=0x58000
CONFIG_SPL_SYS_REPORT_STACK_F_USAGE=y
CONFIG_SPL_SYS_MALLOC_SIMPLE=y
+CONFIG_SPL_SYS_MMCSD_RAW_MODE=y
CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR=y
CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x1400
CONFIG_SPL_FS_LOAD_PAYLOAD_NAME="u-boot.img"
diff --git a/configs/am62x_evm_r5_defconfig b/configs/am62x_evm_r5_defconfig
index 4b2e57b..78ed3f6 100644
--- a/configs/am62x_evm_r5_defconfig
+++ b/configs/am62x_evm_r5_defconfig
@@ -47,6 +47,7 @@
CONFIG_SPL_CUSTOM_SYS_MALLOC_ADDR=0x84000000
CONFIG_SPL_SYS_MALLOC_SIZE=0x1000000
CONFIG_SPL_EARLY_BSS=y
+CONFIG_SPL_SYS_MMCSD_RAW_MODE=y
CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR=y
CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x400
CONFIG_SPL_DM_MAILBOX=y
diff --git a/configs/am64x_evm_a53_defconfig b/configs/am64x_evm_a53_defconfig
index 5b01002..e6e3e01 100644
--- a/configs/am64x_evm_a53_defconfig
+++ b/configs/am64x_evm_a53_defconfig
@@ -43,6 +43,7 @@
CONFIG_SPL_SYS_MALLOC_SIMPLE=y
CONFIG_SPL_SYS_MALLOC=y
CONFIG_SPL_SYS_MALLOC_SIZE=0x800000
+CONFIG_SPL_SYS_MMCSD_RAW_MODE=y
CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR=y
CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x1800
CONFIG_SPL_DMA=y
diff --git a/configs/am64x_evm_r5_defconfig b/configs/am64x_evm_r5_defconfig
index 96475d4..1e83b7f 100644
--- a/configs/am64x_evm_r5_defconfig
+++ b/configs/am64x_evm_r5_defconfig
@@ -50,6 +50,7 @@
CONFIG_SPL_CUSTOM_SYS_MALLOC_ADDR=0x84000000
CONFIG_SPL_SYS_MALLOC_SIZE=0x1000000
CONFIG_SPL_EARLY_BSS=y
+CONFIG_SPL_SYS_MMCSD_RAW_MODE=y
CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR=y
CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x800
CONFIG_SPL_DMA=y
diff --git a/configs/am65x_evm_a53_defconfig b/configs/am65x_evm_a53_defconfig
index 925a88e..f22b9af 100644
--- a/configs/am65x_evm_a53_defconfig
+++ b/configs/am65x_evm_a53_defconfig
@@ -44,6 +44,7 @@
CONFIG_SPL_SYS_MALLOC_SIMPLE=y
CONFIG_SPL_SYS_MALLOC=y
CONFIG_SPL_SYS_MALLOC_SIZE=0x800000
+CONFIG_SPL_SYS_MMCSD_RAW_MODE=y
CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR=y
CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x1400
CONFIG_SPL_DMA=y
diff --git a/configs/am65x_evm_r5_defconfig b/configs/am65x_evm_r5_defconfig
index 4fc9c39..1660bf9 100644
--- a/configs/am65x_evm_r5_defconfig
+++ b/configs/am65x_evm_r5_defconfig
@@ -46,6 +46,7 @@
CONFIG_SPL_CUSTOM_SYS_MALLOC_ADDR=0x84000000
CONFIG_SPL_SYS_MALLOC_SIZE=0x1000000
CONFIG_SPL_EARLY_BSS=y
+CONFIG_SPL_SYS_MMCSD_RAW_MODE=y
CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR=y
CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x400
CONFIG_SPL_DMA=y
diff --git a/configs/apalis-imx8_defconfig b/configs/apalis-imx8_defconfig
index e9fb4c7..466147f 100644
--- a/configs/apalis-imx8_defconfig
+++ b/configs/apalis-imx8_defconfig
@@ -13,6 +13,7 @@
CONFIG_BOOTAUX_RESERVED_MEM_BASE=0x88000000
CONFIG_BOOTAUX_RESERVED_MEM_SIZE=0x08000000
CONFIG_TARGET_APALIS_IMX8=y
+CONFIG_IMX_BOOTAUX=y
CONFIG_OF_LIBFDT_OVERLAY=y
CONFIG_SYS_LOAD_ADDR=0x95400000
CONFIG_SYS_MEMTEST_START=0x88000000
diff --git a/configs/brppt1_mmc_defconfig b/configs/brppt1_mmc_defconfig
index 0b2ee74..8947b76 100644
--- a/configs/brppt1_mmc_defconfig
+++ b/configs/brppt1_mmc_defconfig
@@ -6,8 +6,6 @@
CONFIG_SPL_LIBCOMMON_SUPPORT=y
CONFIG_SPL_LIBGENERIC_SUPPORT=y
CONFIG_NR_DRAM_BANKS=1
-CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y
-CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x4030ff00
CONFIG_ENV_SIZE=0x10000
CONFIG_ENV_OFFSET=0x40000
CONFIG_DM_GPIO=y
@@ -39,6 +37,7 @@
# CONFIG_DISPLAY_CPUINFO is not set
# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_ARCH_MISC_INIT=y
+CONFIG_SPL_BOARD_INIT=y
CONFIG_SPL_SYS_MALLOC_SIMPLE=y
CONFIG_SPL_SYS_MALLOC=y
CONFIG_SPL_SYS_MALLOC_SIZE=0x500000
diff --git a/configs/brppt2_defconfig b/configs/brppt2_defconfig
index 47b37bb..2f29cb3 100644
--- a/configs/brppt2_defconfig
+++ b/configs/brppt2_defconfig
@@ -34,7 +34,7 @@
CONFIG_BOARD_EARLY_INIT_F=y
CONFIG_SPL_BOARD_INIT=y
CONFIG_SPL_SYS_MALLOC=y
-# CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR is not set
+# CONFIG_SPL_SYS_MMCSD_RAW_MODE is not set
CONFIG_SPL_I2C=y
CONFIG_SPL_DM_SPI_FLASH=y
CONFIG_SPL_SPI_LOAD=y
diff --git a/configs/brsmarc1_defconfig b/configs/brsmarc1_defconfig
index f584b8d..a17afde 100644
--- a/configs/brsmarc1_defconfig
+++ b/configs/brsmarc1_defconfig
@@ -4,8 +4,6 @@
CONFIG_SPL_GPIO=y
CONFIG_SPL_LIBCOMMON_SUPPORT=y
CONFIG_SPL_LIBGENERIC_SUPPORT=y
-CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y
-CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x4030ff00
CONFIG_SF_DEFAULT_SPEED=24000000
CONFIG_ENV_SIZE=0x10000
CONFIG_ENV_OFFSET=0x20000
@@ -39,11 +37,12 @@
# CONFIG_DISPLAY_CPUINFO is not set
# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_ARCH_MISC_INIT=y
+CONFIG_SPL_BOARD_INIT=y
# CONFIG_SPL_RAW_IMAGE_SUPPORT is not set
CONFIG_SPL_SYS_MALLOC_SIMPLE=y
CONFIG_SPL_SYS_MALLOC=y
CONFIG_SPL_SYS_MALLOC_SIZE=0x500000
-# CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR is not set
+# CONFIG_SPL_SYS_MMCSD_RAW_MODE is not set
CONFIG_SPL_I2C=y
# CONFIG_SPL_NAND_SUPPORT is not set
CONFIG_SPL_DM_SPI_FLASH=y
diff --git a/configs/brxre1_defconfig b/configs/brxre1_defconfig
index 6c27f07..fc801f2 100644
--- a/configs/brxre1_defconfig
+++ b/configs/brxre1_defconfig
@@ -4,8 +4,6 @@
CONFIG_SPL_GPIO=y
CONFIG_SPL_LIBCOMMON_SUPPORT=y
CONFIG_SPL_LIBGENERIC_SUPPORT=y
-CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y
-CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x4030ff00
CONFIG_ENV_SIZE=0x10000
CONFIG_ENV_OFFSET=0x40000
CONFIG_DM_GPIO=y
@@ -35,6 +33,7 @@
# CONFIG_DISPLAY_CPUINFO is not set
# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_ARCH_MISC_INIT=y
+CONFIG_SPL_BOARD_INIT=y
CONFIG_SPL_SYS_MALLOC_SIMPLE=y
CONFIG_SPL_SYS_MALLOC=y
CONFIG_SPL_SYS_MALLOC_SIZE=0x500000
diff --git a/configs/cgtqmx8_defconfig b/configs/cgtqmx8_defconfig
index 24dfdae..a9283ad 100644
--- a/configs/cgtqmx8_defconfig
+++ b/configs/cgtqmx8_defconfig
@@ -43,6 +43,7 @@
CONFIG_SPL_HAS_CUSTOM_MALLOC_START=y
CONFIG_SPL_CUSTOM_SYS_MALLOC_ADDR=0x120000
CONFIG_SPL_SYS_MALLOC_SIZE=0x3000
+CONFIG_SPL_SYS_MMCSD_RAW_MODE=y
CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR=y
CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x800
CONFIG_SYS_MMCSD_FS_BOOT_PARTITION=0
diff --git a/configs/chiliboard_defconfig b/configs/chiliboard_defconfig
index c574d93..8cb6b34 100644
--- a/configs/chiliboard_defconfig
+++ b/configs/chiliboard_defconfig
@@ -3,8 +3,6 @@
CONFIG_ARCH_OMAP2PLUS=y
CONFIG_SPL_LIBCOMMON_SUPPORT=y
CONFIG_SPL_LIBGENERIC_SUPPORT=y
-CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y
-CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x4030fef0
CONFIG_ENV_SIZE=0x2000
CONFIG_ENV_OFFSET=0x20000
CONFIG_DM_GPIO=y
@@ -24,6 +22,7 @@
CONFIG_DEFAULT_FDT_FILE="am335x-chiliboard.dtb"
CONFIG_SYS_CONSOLE_INFO_QUIET=y
CONFIG_ARCH_MISC_INIT=y
+CONFIG_SPL_BOARD_INIT=y
CONFIG_SPL_SYS_MALLOC=y
CONFIG_SPL_SYS_MALLOC_SIZE=0x800000
CONFIG_SPL_I2C=y
@@ -53,7 +52,7 @@
CONFIG_BOOTP_SEND_HOSTNAME=y
CONFIG_BOOTCOUNT_LIMIT=y
CONFIG_SYS_BOOTCOUNT_BE=y
-CONFIG_SYS_I2C_LEGACY=y
+CONFIG_DM_I2C=y
CONFIG_SPL_SYS_I2C_LEGACY=y
CONFIG_MISC=y
CONFIG_MMC_OMAP_HS=y
diff --git a/configs/chromebit_mickey_defconfig b/configs/chromebit_mickey_defconfig
index e5d805d..93bf4f5 100644
--- a/configs/chromebit_mickey_defconfig
+++ b/configs/chromebit_mickey_defconfig
@@ -38,7 +38,7 @@
CONFIG_SPL_NO_BSS_LIMIT=y
# CONFIG_SPL_RAW_IMAGE_SUPPORT is not set
# CONFIG_SPL_SHARES_INIT_SP_ADDR is not set
-# CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR is not set
+# CONFIG_SPL_SYS_MMCSD_RAW_MODE is not set
CONFIG_SPL_SPI_LOAD=y
CONFIG_SYS_SPI_U_BOOT_OFFS=0x20000
CONFIG_CMD_GPIO=y
diff --git a/configs/chromebook_jerry_defconfig b/configs/chromebook_jerry_defconfig
index 9bc5953..a1df1f8 100644
--- a/configs/chromebook_jerry_defconfig
+++ b/configs/chromebook_jerry_defconfig
@@ -37,7 +37,7 @@
CONFIG_SPL_NO_BSS_LIMIT=y
# CONFIG_SPL_RAW_IMAGE_SUPPORT is not set
# CONFIG_SPL_SHARES_INIT_SP_ADDR is not set
-# CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR is not set
+# CONFIG_SPL_SYS_MMCSD_RAW_MODE is not set
CONFIG_SPL_SPI_LOAD=y
CONFIG_SYS_SPI_U_BOOT_OFFS=0x20000
CONFIG_CMD_GPIO=y
diff --git a/configs/chromebook_minnie_defconfig b/configs/chromebook_minnie_defconfig
index 26fa05e..03520b6 100644
--- a/configs/chromebook_minnie_defconfig
+++ b/configs/chromebook_minnie_defconfig
@@ -38,7 +38,7 @@
CONFIG_SPL_NO_BSS_LIMIT=y
# CONFIG_SPL_RAW_IMAGE_SUPPORT is not set
# CONFIG_SPL_SHARES_INIT_SP_ADDR is not set
-# CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR is not set
+# CONFIG_SPL_SYS_MMCSD_RAW_MODE is not set
CONFIG_SPL_SPI_LOAD=y
CONFIG_SYS_SPI_U_BOOT_OFFS=0x20000
CONFIG_CMD_GPIO=y
diff --git a/configs/chromebook_speedy_defconfig b/configs/chromebook_speedy_defconfig
index 5deb09b..607fd28 100644
--- a/configs/chromebook_speedy_defconfig
+++ b/configs/chromebook_speedy_defconfig
@@ -38,7 +38,7 @@
CONFIG_SPL_NO_BSS_LIMIT=y
# CONFIG_SPL_RAW_IMAGE_SUPPORT is not set
# CONFIG_SPL_SHARES_INIT_SP_ADDR is not set
-# CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR is not set
+# CONFIG_SPL_SYS_MMCSD_RAW_MODE is not set
CONFIG_SPL_SPI_LOAD=y
CONFIG_SYS_SPI_U_BOOT_OFFS=0x20000
CONFIG_CMD_GPIO=y
diff --git a/configs/ci20_mmc_defconfig b/configs/ci20_mmc_defconfig
index 39f3384..90574d2 100644
--- a/configs/ci20_mmc_defconfig
+++ b/configs/ci20_mmc_defconfig
@@ -32,6 +32,7 @@
CONFIG_SPL_MAX_SIZE=0x2e00
# CONFIG_SPL_SHARES_INIT_SP_ADDR is not set
# CONFIG_SPL_BANNER_PRINT is not set
+CONFIG_SPL_SYS_MMCSD_RAW_MODE=y
CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR=y
CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x1c
CONFIG_SPL_MMC_TINY=y
diff --git a/configs/cm_fx6_defconfig b/configs/cm_fx6_defconfig
index 386616c..81a39f7 100644
--- a/configs/cm_fx6_defconfig
+++ b/configs/cm_fx6_defconfig
@@ -80,7 +80,7 @@
CONFIG_DWC_AHSATA=y
# CONFIG_DWC_AHSATA_AHCI is not set
CONFIG_LBA48=y
-CONFIG_SYS_I2C_LEGACY=y
+CONFIG_DM_I2C=y
CONFIG_SPL_SYS_I2C_LEGACY=y
CONFIG_SYS_I2C_MXC=y
CONFIG_SYS_MXC_I2C3_SPEED=400000
diff --git a/configs/cm_t43_defconfig b/configs/cm_t43_defconfig
index 32f126a..eabeee8 100644
--- a/configs/cm_t43_defconfig
+++ b/configs/cm_t43_defconfig
@@ -5,8 +5,6 @@
CONFIG_SYS_MALLOC_F_LEN=0x400
CONFIG_SPL_LIBCOMMON_SUPPORT=y
CONFIG_SPL_LIBGENERIC_SUPPORT=y
-CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y
-CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x4033ff00
CONFIG_SF_DEFAULT_SPEED=48000000
CONFIG_ENV_SIZE=0x4000
CONFIG_ENV_OFFSET=0xC0000
@@ -38,6 +36,7 @@
CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x480
CONFIG_SPL_FS_EXT4=y
CONFIG_SPL_I2C=y
+# CONFIG_SPL_DM_I2C is not set
CONFIG_SPL_MTD=y
# CONFIG_SPL_NAND_SUPPORT is not set
CONFIG_SPL_NAND_DRIVERS=y
@@ -72,7 +71,7 @@
CONFIG_VERSION_VARIABLE=y
CONFIG_BOOTP_SEND_HOSTNAME=y
CONFIG_SYS_RX_ETH_BUFFER=64
-CONFIG_SYS_I2C_LEGACY=y
+CONFIG_DM_I2C=y
CONFIG_SPL_SYS_I2C_LEGACY=y
CONFIG_MMC_OMAP_HS=y
CONFIG_HSMMC2_8BIT=y
diff --git a/configs/colibri-imx8x_defconfig b/configs/colibri-imx8x_defconfig
index e76373e..d7b1b76 100644
--- a/configs/colibri-imx8x_defconfig
+++ b/configs/colibri-imx8x_defconfig
@@ -13,6 +13,8 @@
CONFIG_BOOTAUX_RESERVED_MEM_BASE=0x88000000
CONFIG_BOOTAUX_RESERVED_MEM_SIZE=0x08000000
CONFIG_TARGET_COLIBRI_IMX8X=y
+CONFIG_IMX_SNVS_SEC_SC=y
+CONFIG_IMX_BOOTAUX=y
CONFIG_OF_LIBFDT_OVERLAY=y
CONFIG_SYS_LOAD_ADDR=0x95c00000
CONFIG_SYS_MEMTEST_START=0x88000000
diff --git a/configs/da850evm_defconfig b/configs/da850evm_defconfig
index 30d1a93..d10faa5 100644
--- a/configs/da850evm_defconfig
+++ b/configs/da850evm_defconfig
@@ -50,7 +50,7 @@
CONFIG_SPL_HAS_CUSTOM_MALLOC_START=y
CONFIG_SPL_CUSTOM_SYS_MALLOC_ADDR=0xc0f70000
CONFIG_SPL_SYS_MALLOC_SIZE=0x110000
-# CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR is not set
+# CONFIG_SPL_SYS_MMCSD_RAW_MODE is not set
CONFIG_SPL_DM_SPI_FLASH=y
CONFIG_SPL_SPI_LOAD=y
CONFIG_SYS_SPI_U_BOOT_OFFS=0x8000
diff --git a/configs/da850evm_nand_defconfig b/configs/da850evm_nand_defconfig
index 62cbd02..7e59b6f 100644
--- a/configs/da850evm_nand_defconfig
+++ b/configs/da850evm_nand_defconfig
@@ -46,7 +46,7 @@
CONFIG_SPL_HAS_CUSTOM_MALLOC_START=y
CONFIG_SPL_CUSTOM_SYS_MALLOC_ADDR=0xc0f70000
CONFIG_SPL_SYS_MALLOC_SIZE=0x110000
-# CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR is not set
+# CONFIG_SPL_SYS_MMCSD_RAW_MODE is not set
CONFIG_SPL_NAND_SUPPORT=y
CONFIG_SPL_NAND_DRIVERS=y
CONFIG_SPL_NAND_ECC=y
diff --git a/configs/deneb_defconfig b/configs/deneb_defconfig
index 4b9b073..4731e84 100644
--- a/configs/deneb_defconfig
+++ b/configs/deneb_defconfig
@@ -55,6 +55,7 @@
CONFIG_SPL_HAS_CUSTOM_MALLOC_START=y
CONFIG_SPL_CUSTOM_SYS_MALLOC_ADDR=0x120000
CONFIG_SPL_SYS_MALLOC_SIZE=0x3000
+CONFIG_SPL_SYS_MMCSD_RAW_MODE=y
CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR=y
CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x800
CONFIG_SPL_POWER_DOMAIN=y
diff --git a/configs/devkit8000_defconfig b/configs/devkit8000_defconfig
index 7653fbb..33201ce 100644
--- a/configs/devkit8000_defconfig
+++ b/configs/devkit8000_defconfig
@@ -3,13 +3,8 @@
CONFIG_TEXT_BASE=0x80100000
CONFIG_SYS_MALLOC_LEN=0x40000
CONFIG_SYS_MALLOC_F_LEN=0x4000
-CONFIG_NR_DRAM_BANKS=2
-CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y
-CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x4020ff00
CONFIG_DEFAULT_DEVICE_TREE="omap3-devkit8000"
-CONFIG_SPL_TEXT_BASE=0x40200000
CONFIG_TARGET_DEVKIT8000=y
-CONFIG_SYS_MONITOR_LEN=262144
CONFIG_SPL_SYS_MALLOC_F_LEN=0x400
CONFIG_SPL_BSS_START_ADDR=0x80000500
CONFIG_SPL=y
@@ -17,7 +12,6 @@
CONFIG_BOOTCOMMAND="run autoboot"
CONFIG_USE_PREBOOT=y
CONFIG_SYS_CONSOLE_INFO_QUIET=y
-CONFIG_SPL_MAX_SIZE=0xec00
CONFIG_SPL_SYS_MALLOC_SIMPLE=y
CONFIG_SPL_SYS_MALLOC=y
CONFIG_SPL_HAS_CUSTOM_MALLOC_START=y
diff --git a/configs/display5_defconfig b/configs/display5_defconfig
index 1d3336b..7463f4f 100644
--- a/configs/display5_defconfig
+++ b/configs/display5_defconfig
@@ -42,7 +42,7 @@
CONFIG_MISC_INIT_R=y
CONFIG_SPL_BOOTCOUNT_LIMIT=y
CONFIG_SPL_SYS_MALLOC=y
-# CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR is not set
+# CONFIG_SPL_SYS_MMCSD_RAW_MODE is not set
CONFIG_SPL_DMA=y
CONFIG_SPL_ENV_SUPPORT=y
CONFIG_SPL_SAVEENV=y
diff --git a/configs/display5_factory_defconfig b/configs/display5_factory_defconfig
index 7c681f0..59d0c5d 100644
--- a/configs/display5_factory_defconfig
+++ b/configs/display5_factory_defconfig
@@ -39,7 +39,7 @@
CONFIG_SYS_PBSIZE=2084
CONFIG_MISC_INIT_R=y
CONFIG_SPL_SYS_MALLOC=y
-# CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR is not set
+# CONFIG_SPL_SYS_MMCSD_RAW_MODE is not set
CONFIG_SPL_DMA=y
CONFIG_SPL_I2C=y
CONFIG_SPL_OS_BOOT=y
diff --git a/configs/dra7xx_evm_defconfig b/configs/dra7xx_evm_defconfig
index 0cea550..6264d9f 100644
--- a/configs/dra7xx_evm_defconfig
+++ b/configs/dra7xx_evm_defconfig
@@ -2,9 +2,6 @@
CONFIG_ARCH_OMAP2PLUS=y
CONFIG_SYS_MALLOC_F_LEN=0x18000
CONFIG_TI_COMMON_CMD_OPTIONS=y
-CONFIG_NR_DRAM_BANKS=2
-CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y
-CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x4037fef0
CONFIG_SF_DEFAULT_SPEED=76800000
CONFIG_DM_GPIO=y
CONFIG_SPL_DM_SPI=y
diff --git a/configs/dra7xx_hs_evm_defconfig b/configs/dra7xx_hs_evm_defconfig
index 5f56b18..4e79297 100644
--- a/configs/dra7xx_hs_evm_defconfig
+++ b/configs/dra7xx_hs_evm_defconfig
@@ -3,9 +3,6 @@
CONFIG_TI_SECURE_DEVICE=y
CONFIG_SYS_MALLOC_F_LEN=0x18000
CONFIG_TI_COMMON_CMD_OPTIONS=y
-CONFIG_NR_DRAM_BANKS=2
-CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y
-CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x4037fef0
CONFIG_SF_DEFAULT_SPEED=76800000
CONFIG_DM_GPIO=y
CONFIG_SPL_DM_SPI=y
diff --git a/configs/dra7xx_hs_evm_usb_defconfig b/configs/dra7xx_hs_evm_usb_defconfig
index 5b67a0e..68d342b 100644
--- a/configs/dra7xx_hs_evm_usb_defconfig
+++ b/configs/dra7xx_hs_evm_usb_defconfig
@@ -3,9 +3,6 @@
CONFIG_TI_SECURE_DEVICE=y
CONFIG_SYS_MALLOC_F_LEN=0x18000
CONFIG_TI_COMMON_CMD_OPTIONS=y
-CONFIG_NR_DRAM_BANKS=2
-CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y
-CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x4037fef0
CONFIG_SF_DEFAULT_SPEED=76800000
CONFIG_DM_GPIO=y
CONFIG_SPL_DM_SPI=y
diff --git a/configs/draco-etamin_defconfig b/configs/draco-etamin_defconfig
index ba3f381..78ee5c1 100644
--- a/configs/draco-etamin_defconfig
+++ b/configs/draco-etamin_defconfig
@@ -5,8 +5,6 @@
CONFIG_SPL_LIBCOMMON_SUPPORT=y
CONFIG_SPL_LIBGENERIC_SUPPORT=y
CONFIG_NR_DRAM_BANKS=1
-CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y
-CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x4030ff00
CONFIG_ENV_SIZE=0x2000
CONFIG_ENV_OFFSET=0x980000
CONFIG_DEFAULT_DEVICE_TREE="am335x-draco"
diff --git a/configs/draco-rastaban_defconfig b/configs/draco-rastaban_defconfig
index 43d29f5..ea6518e 100644
--- a/configs/draco-rastaban_defconfig
+++ b/configs/draco-rastaban_defconfig
@@ -5,8 +5,6 @@
CONFIG_SPL_LIBCOMMON_SUPPORT=y
CONFIG_SPL_LIBGENERIC_SUPPORT=y
CONFIG_NR_DRAM_BANKS=1
-CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y
-CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x4030ff00
CONFIG_ENV_SIZE=0x2000
CONFIG_DEFAULT_DEVICE_TREE="am335x-draco"
CONFIG_AM33XX=y
@@ -35,7 +33,7 @@
CONFIG_SPL_SYS_MALLOC=y
CONFIG_SPL_HAS_CUSTOM_MALLOC_START=y
CONFIG_SPL_CUSTOM_SYS_MALLOC_ADDR=0x80208000
-# CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR is not set
+# CONFIG_SPL_SYS_MMCSD_RAW_MODE is not set
CONFIG_SPL_I2C=y
CONFIG_SPL_NAND_DRIVERS=y
CONFIG_SPL_NAND_ECC=y
diff --git a/configs/draco-thuban_defconfig b/configs/draco-thuban_defconfig
index b457b22..4672d4b 100644
--- a/configs/draco-thuban_defconfig
+++ b/configs/draco-thuban_defconfig
@@ -5,8 +5,6 @@
CONFIG_SPL_LIBCOMMON_SUPPORT=y
CONFIG_SPL_LIBGENERIC_SUPPORT=y
CONFIG_NR_DRAM_BANKS=1
-CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y
-CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x4030ff00
CONFIG_ENV_SIZE=0x2000
CONFIG_DEFAULT_DEVICE_TREE="am335x-draco"
CONFIG_AM33XX=y
@@ -35,7 +33,7 @@
CONFIG_SPL_SYS_MALLOC=y
CONFIG_SPL_HAS_CUSTOM_MALLOC_START=y
CONFIG_SPL_CUSTOM_SYS_MALLOC_ADDR=0x80208000
-# CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR is not set
+# CONFIG_SPL_SYS_MMCSD_RAW_MODE is not set
CONFIG_SPL_I2C=y
CONFIG_SPL_NAND_DRIVERS=y
CONFIG_SPL_NAND_ECC=y
diff --git a/configs/e850-96_defconfig b/configs/e850-96_defconfig
index 2949da2..e5d9099 100644
--- a/configs/e850-96_defconfig
+++ b/configs/e850-96_defconfig
@@ -9,12 +9,20 @@
CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0xf8c00000
CONFIG_DEFAULT_DEVICE_TREE="exynos/exynos850-e850-96"
CONFIG_SYS_LOAD_ADDR=0x80000000
+CONFIG_ANDROID_BOOT_IMAGE=y
# CONFIG_AUTOBOOT is not set
# CONFIG_DISPLAY_CPUINFO is not set
+CONFIG_HUSH_PARSER=y
+CONFIG_CMD_ABOOTIMG=y
+CONFIG_CMD_CLK=y
+CONFIG_CMD_GPT=y
+CONFIG_CMD_MMC=y
+CONFIG_CMD_PART=y
+CONFIG_CMD_TIME=y
CONFIG_CMD_RNG=y
# CONFIG_NET is not set
CONFIG_CLK_EXYNOS850=y
-# CONFIG_MMC is not set
+CONFIG_MMC_DW=y
CONFIG_SOC_SAMSUNG=y
CONFIG_EXYNOS_PMU=y
CONFIG_EXYNOS_USI=y
diff --git a/configs/ethernut5_defconfig b/configs/ethernut5_defconfig
index cc2f567..004f186 100644
--- a/configs/ethernut5_defconfig
+++ b/configs/ethernut5_defconfig
@@ -46,7 +46,6 @@
CONFIG_CMD_DNS=y
CONFIG_CMD_BSP=y
CONFIG_CMD_CACHE=y
-CONFIG_CMD_DATE=y
CONFIG_CMD_EXT2=y
CONFIG_CMD_FAT=y
CONFIG_CMD_JFFS2=y
diff --git a/configs/gardena-smart-gateway-at91sam_defconfig b/configs/gardena-smart-gateway-at91sam_defconfig
index 3b9466c..42f116f 100644
--- a/configs/gardena-smart-gateway-at91sam_defconfig
+++ b/configs/gardena-smart-gateway-at91sam_defconfig
@@ -46,7 +46,7 @@
# CONFIG_SPL_SHARES_INIT_SP_ADDR is not set
CONFIG_SPL_SYS_MALLOC=y
CONFIG_SPL_SYS_MALLOC_SIZE=0x80000
-# CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR is not set
+# CONFIG_SPL_SYS_MMCSD_RAW_MODE is not set
CONFIG_SPL_NAND_SUPPORT=y
CONFIG_SPL_NAND_RAW_ONLY=y
CONFIG_SPL_NAND_DRIVERS=y
diff --git a/configs/giedi_defconfig b/configs/giedi_defconfig
index c7390d1..774ab64 100644
--- a/configs/giedi_defconfig
+++ b/configs/giedi_defconfig
@@ -55,6 +55,7 @@
CONFIG_SPL_HAS_CUSTOM_MALLOC_START=y
CONFIG_SPL_CUSTOM_SYS_MALLOC_ADDR=0x120000
CONFIG_SPL_SYS_MALLOC_SIZE=0x3000
+CONFIG_SPL_SYS_MMCSD_RAW_MODE=y
CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR=y
CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x800
CONFIG_SPL_POWER_DOMAIN=y
diff --git a/configs/igep00x0_defconfig b/configs/igep00x0_defconfig
index 4738916..f1d9bb3 100644
--- a/configs/igep00x0_defconfig
+++ b/configs/igep00x0_defconfig
@@ -4,14 +4,9 @@
CONFIG_ARCH_OMAP2PLUS=y
CONFIG_SYS_MALLOC_F_LEN=0x4000
CONFIG_TI_COMMON_CMD_OPTIONS=y
-CONFIG_NR_DRAM_BANKS=2
-CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y
-CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x4020ff00
CONFIG_ENV_SIZE=0x8000
CONFIG_DEFAULT_DEVICE_TREE="ti/omap/omap3-igep0020"
-CONFIG_SPL_TEXT_BASE=0x40200000
CONFIG_TARGET_OMAP3_IGEP00X0=y
-CONFIG_SYS_MONITOR_LEN=262144
CONFIG_SPL_SYS_MALLOC_F_LEN=0x400
CONFIG_SPL=y
CONFIG_DISTRO_DEFAULTS=y
@@ -22,7 +17,6 @@
CONFIG_SYS_CONSOLE_IS_IN_ENV=y
CONFIG_SYS_CONSOLE_INFO_QUIET=y
# CONFIG_DISPLAY_BOARDINFO is not set
-CONFIG_SPL_MAX_SIZE=0xec00
CONFIG_SPL_SYS_MALLOC_SIMPLE=y
CONFIG_SPL_SYS_MALLOC=y
CONFIG_SPL_SYS_MALLOC_SIZE=0x800000
diff --git a/configs/imx28_xea_defconfig b/configs/imx28_xea_defconfig
index 822a329..d147001 100644
--- a/configs/imx28_xea_defconfig
+++ b/configs/imx28_xea_defconfig
@@ -48,6 +48,7 @@
# CONFIG_SPL_RAW_IMAGE_SUPPORT is not set
CONFIG_SPL_SYS_MALLOC_SIMPLE=y
# CONFIG_SPL_SHARES_INIT_SP_ADDR is not set
+CONFIG_SPL_SYS_MMCSD_RAW_MODE=y
CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR=y
CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x0
CONFIG_SUPPORT_EMMC_BOOT_OVERRIDE_PART_CONFIG=y
diff --git a/configs/imx28_xea_sb_defconfig b/configs/imx28_xea_sb_defconfig
index 8d48d8c..aa1116a 100644
--- a/configs/imx28_xea_sb_defconfig
+++ b/configs/imx28_xea_sb_defconfig
@@ -29,6 +29,7 @@
CONFIG_SPL_BOARD_INIT=y
# CONFIG_SPL_RAW_IMAGE_SUPPORT is not set
CONFIG_SPL_SYS_MALLOC_SIMPLE=y
+CONFIG_SPL_SYS_MMCSD_RAW_MODE=y
CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR=y
CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0
CONFIG_SUPPORT_EMMC_BOOT_OVERRIDE_PART_CONFIG=y
diff --git a/configs/imx6q_logic_defconfig b/configs/imx6q_logic_defconfig
index 7203583..b893da6 100644
--- a/configs/imx6q_logic_defconfig
+++ b/configs/imx6q_logic_defconfig
@@ -30,7 +30,7 @@
CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE=y
CONFIG_SPL_RAW_IMAGE_SUPPORT=y
CONFIG_SPL_SYS_MALLOC=y
-# CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR is not set
+# CONFIG_SPL_SYS_MMCSD_RAW_MODE is not set
CONFIG_SPL_DMA=y
CONFIG_SPL_FS_LOAD_PAYLOAD_NAME="u-boot-dtb.img"
CONFIG_SPL_I2C=y
diff --git a/configs/imx8mm-cl-iot-gate-optee_defconfig b/configs/imx8mm-cl-iot-gate-optee_defconfig
index f5bb50c..0b7dd63 100644
--- a/configs/imx8mm-cl-iot-gate-optee_defconfig
+++ b/configs/imx8mm-cl-iot-gate-optee_defconfig
@@ -37,6 +37,7 @@
CONFIG_SPL_HAS_CUSTOM_MALLOC_START=y
CONFIG_SPL_CUSTOM_SYS_MALLOC_ADDR=0x42200000
CONFIG_SPL_SYS_MALLOC_SIZE=0x80000
+CONFIG_SPL_SYS_MMCSD_RAW_MODE=y
CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR=y
CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x300
CONFIG_SPL_I2C=y
diff --git a/configs/imx8mm-cl-iot-gate_defconfig b/configs/imx8mm-cl-iot-gate_defconfig
index b36ad7c..9312e9f 100644
--- a/configs/imx8mm-cl-iot-gate_defconfig
+++ b/configs/imx8mm-cl-iot-gate_defconfig
@@ -39,6 +39,7 @@
CONFIG_SPL_HAS_CUSTOM_MALLOC_START=y
CONFIG_SPL_CUSTOM_SYS_MALLOC_ADDR=0x42200000
CONFIG_SPL_SYS_MALLOC_SIZE=0x80000
+CONFIG_SPL_SYS_MMCSD_RAW_MODE=y
CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR=y
CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x300
CONFIG_SPL_I2C=y
diff --git a/configs/imx8mm-icore-mx8mm-ctouch2_defconfig b/configs/imx8mm-icore-mx8mm-ctouch2_defconfig
index d4e9d9f..f37297c 100644
--- a/configs/imx8mm-icore-mx8mm-ctouch2_defconfig
+++ b/configs/imx8mm-icore-mx8mm-ctouch2_defconfig
@@ -36,6 +36,7 @@
CONFIG_SPL_HAS_CUSTOM_MALLOC_START=y
CONFIG_SPL_CUSTOM_SYS_MALLOC_ADDR=0x42200000
CONFIG_SPL_SYS_MALLOC_SIZE=0x80000
+CONFIG_SPL_SYS_MMCSD_RAW_MODE=y
CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR=y
CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x300
CONFIG_SPL_POWER=y
diff --git a/configs/imx8mm-icore-mx8mm-edimm2.2_defconfig b/configs/imx8mm-icore-mx8mm-edimm2.2_defconfig
index c85a141..950246e 100644
--- a/configs/imx8mm-icore-mx8mm-edimm2.2_defconfig
+++ b/configs/imx8mm-icore-mx8mm-edimm2.2_defconfig
@@ -36,6 +36,7 @@
CONFIG_SPL_HAS_CUSTOM_MALLOC_START=y
CONFIG_SPL_CUSTOM_SYS_MALLOC_ADDR=0x42200000
CONFIG_SPL_SYS_MALLOC_SIZE=0x80000
+CONFIG_SPL_SYS_MMCSD_RAW_MODE=y
CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR=y
CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x300
CONFIG_SPL_POWER=y
diff --git a/configs/imx8mm-mx8menlo_defconfig b/configs/imx8mm-mx8menlo_defconfig
index 5e6bbb3..8644177 100644
--- a/configs/imx8mm-mx8menlo_defconfig
+++ b/configs/imx8mm-mx8menlo_defconfig
@@ -52,6 +52,7 @@
CONFIG_SPL_HAS_CUSTOM_MALLOC_START=y
CONFIG_SPL_CUSTOM_SYS_MALLOC_ADDR=0x42200000
CONFIG_SPL_SYS_MALLOC_SIZE=0x80000
+CONFIG_SPL_SYS_MMCSD_RAW_MODE=y
CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR=y
CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x300
CONFIG_SPL_I2C=y
diff --git a/configs/imx8mm-phygate-tauri-l_defconfig b/configs/imx8mm-phygate-tauri-l_defconfig
index 16ba7d4..6570c9f 100644
--- a/configs/imx8mm-phygate-tauri-l_defconfig
+++ b/configs/imx8mm-phygate-tauri-l_defconfig
@@ -37,6 +37,7 @@
CONFIG_SPL_HAS_CUSTOM_MALLOC_START=y
CONFIG_SPL_CUSTOM_SYS_MALLOC_ADDR=0x42200000
CONFIG_SPL_SYS_MALLOC_SIZE=0x80000
+CONFIG_SPL_SYS_MMCSD_RAW_MODE=y
CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR=y
CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x300
CONFIG_SPL_I2C=y
diff --git a/configs/imx8mm_beacon_defconfig b/configs/imx8mm_beacon_defconfig
index e3dcbfe..7f0cb9a 100644
--- a/configs/imx8mm_beacon_defconfig
+++ b/configs/imx8mm_beacon_defconfig
@@ -38,6 +38,7 @@
CONFIG_SPL_HAS_CUSTOM_MALLOC_START=y
CONFIG_SPL_CUSTOM_SYS_MALLOC_ADDR=0x42200000
CONFIG_SPL_SYS_MALLOC_SIZE=0x80000
+CONFIG_SPL_SYS_MMCSD_RAW_MODE=y
CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR=y
CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x300
CONFIG_SPL_I2C=y
diff --git a/configs/imx8mm_beacon_fspi_defconfig b/configs/imx8mm_beacon_fspi_defconfig
index 0aca853..354a671 100644
--- a/configs/imx8mm_beacon_fspi_defconfig
+++ b/configs/imx8mm_beacon_fspi_defconfig
@@ -41,6 +41,7 @@
CONFIG_SPL_HAS_CUSTOM_MALLOC_START=y
CONFIG_SPL_CUSTOM_SYS_MALLOC_ADDR=0x42200000
CONFIG_SPL_SYS_MALLOC_SIZE=0x80000
+CONFIG_SPL_SYS_MMCSD_RAW_MODE=y
CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR=y
CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x300
CONFIG_SPL_I2C=y
diff --git a/configs/imx8mm_data_modul_edm_sbc_defconfig b/configs/imx8mm_data_modul_edm_sbc_defconfig
index f26a879..34566d4 100644
--- a/configs/imx8mm_data_modul_edm_sbc_defconfig
+++ b/configs/imx8mm_data_modul_edm_sbc_defconfig
@@ -59,6 +59,7 @@
CONFIG_SPL_HAS_CUSTOM_MALLOC_START=y
CONFIG_SPL_CUSTOM_SYS_MALLOC_ADDR=0x42200000
CONFIG_SPL_SYS_MALLOC_SIZE=0x1000000
+CONFIG_SPL_SYS_MMCSD_RAW_MODE=y
CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR=y
CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x300
CONFIG_SPL_I2C=y
@@ -105,6 +106,8 @@
CONFIG_CMD_USB=y
CONFIG_CMD_USB_SDP=y
CONFIG_CMD_USB_MASS_STORAGE=y
+CONFIG_CMD_CAT=y
+CONFIG_CMD_XXD=y
CONFIG_CMD_DHCP=y
CONFIG_CMD_DHCP6=y
CONFIG_CMD_TFTPPUT=y
diff --git a/configs/imx8mm_evk_defconfig b/configs/imx8mm_evk_defconfig
index 788770b..3fd2d9f 100644
--- a/configs/imx8mm_evk_defconfig
+++ b/configs/imx8mm_evk_defconfig
@@ -35,6 +35,7 @@
CONFIG_SPL_HAS_CUSTOM_MALLOC_START=y
CONFIG_SPL_CUSTOM_SYS_MALLOC_ADDR=0x42200000
CONFIG_SPL_SYS_MALLOC_SIZE=0x80000
+CONFIG_SPL_SYS_MMCSD_RAW_MODE=y
CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR=y
CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x300
CONFIG_SPL_I2C=y
diff --git a/configs/imx8mm_evk_fspi_defconfig b/configs/imx8mm_evk_fspi_defconfig
index a57dc47..96c0a46 100644
--- a/configs/imx8mm_evk_fspi_defconfig
+++ b/configs/imx8mm_evk_fspi_defconfig
@@ -39,6 +39,7 @@
CONFIG_SPL_HAS_CUSTOM_MALLOC_START=y
CONFIG_SPL_CUSTOM_SYS_MALLOC_ADDR=0x42200000
CONFIG_SPL_SYS_MALLOC_SIZE=0x80000
+CONFIG_SPL_SYS_MMCSD_RAW_MODE=y
CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR=y
CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x300
CONFIG_SPL_I2C=y
diff --git a/configs/imx8mm_phg_defconfig b/configs/imx8mm_phg_defconfig
index e14dcdf..2fd319b 100644
--- a/configs/imx8mm_phg_defconfig
+++ b/configs/imx8mm_phg_defconfig
@@ -36,6 +36,7 @@
CONFIG_SPL_HAS_CUSTOM_MALLOC_START=y
CONFIG_SPL_CUSTOM_SYS_MALLOC_ADDR=0x42200000
CONFIG_SPL_SYS_MALLOC_SIZE=0x80000
+CONFIG_SPL_SYS_MMCSD_RAW_MODE=y
CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR=y
CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x300
CONFIG_SPL_I2C=y
diff --git a/configs/imx8mm_venice_defconfig b/configs/imx8mm_venice_defconfig
index f4d999b..fc3e3ec 100644
--- a/configs/imx8mm_venice_defconfig
+++ b/configs/imx8mm_venice_defconfig
@@ -44,6 +44,7 @@
CONFIG_SPL_SYS_MALLOC=y
CONFIG_SPL_HAS_CUSTOM_MALLOC_START=y
CONFIG_SPL_CUSTOM_SYS_MALLOC_ADDR=0x42200000
+CONFIG_SPL_SYS_MMCSD_RAW_MODE=y
CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR=y
CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x300
CONFIG_SPL_I2C=y
diff --git a/configs/imx8mn_beacon_2g_defconfig b/configs/imx8mn_beacon_2g_defconfig
index 1129d80..7a19315 100644
--- a/configs/imx8mn_beacon_2g_defconfig
+++ b/configs/imx8mn_beacon_2g_defconfig
@@ -48,6 +48,7 @@
CONFIG_SPL_HAS_CUSTOM_MALLOC_START=y
CONFIG_SPL_CUSTOM_SYS_MALLOC_ADDR=0x42200000
CONFIG_SPL_SYS_MALLOC_SIZE=0x80000
+CONFIG_SPL_SYS_MMCSD_RAW_MODE=y
CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR=y
CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x300
CONFIG_SPL_I2C=y
diff --git a/configs/imx8mn_beacon_defconfig b/configs/imx8mn_beacon_defconfig
index f4af998..eebfb0d 100644
--- a/configs/imx8mn_beacon_defconfig
+++ b/configs/imx8mn_beacon_defconfig
@@ -47,6 +47,7 @@
CONFIG_SPL_HAS_CUSTOM_MALLOC_START=y
CONFIG_SPL_CUSTOM_SYS_MALLOC_ADDR=0x42200000
CONFIG_SPL_SYS_MALLOC_SIZE=0x80000
+CONFIG_SPL_SYS_MMCSD_RAW_MODE=y
CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR=y
CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x300
CONFIG_SPL_I2C=y
diff --git a/configs/imx8mn_beacon_fspi_defconfig b/configs/imx8mn_beacon_fspi_defconfig
index cecde44..6acbb8a 100644
--- a/configs/imx8mn_beacon_fspi_defconfig
+++ b/configs/imx8mn_beacon_fspi_defconfig
@@ -47,6 +47,7 @@
CONFIG_SPL_HAS_CUSTOM_MALLOC_START=y
CONFIG_SPL_CUSTOM_SYS_MALLOC_ADDR=0x42200000
CONFIG_SPL_SYS_MALLOC_SIZE=0x80000
+CONFIG_SPL_SYS_MMCSD_RAW_MODE=y
CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR=y
CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x300
CONFIG_SPL_I2C=y
diff --git a/configs/imx8mn_bsh_smm_s2_defconfig b/configs/imx8mn_bsh_smm_s2_defconfig
index b4351a3..29d7cda 100644
--- a/configs/imx8mn_bsh_smm_s2_defconfig
+++ b/configs/imx8mn_bsh_smm_s2_defconfig
@@ -42,6 +42,7 @@
CONFIG_SPL_HAS_CUSTOM_MALLOC_START=y
CONFIG_SPL_CUSTOM_SYS_MALLOC_ADDR=0x42200000
CONFIG_SPL_SYS_MALLOC_SIZE=0x80000
+CONFIG_SPL_SYS_MMCSD_RAW_MODE=y
CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR=y
CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x300
CONFIG_SPL_DMA=y
diff --git a/configs/imx8mn_bsh_smm_s2pro_defconfig b/configs/imx8mn_bsh_smm_s2pro_defconfig
index 0faa337..151a9a5 100644
--- a/configs/imx8mn_bsh_smm_s2pro_defconfig
+++ b/configs/imx8mn_bsh_smm_s2pro_defconfig
@@ -43,6 +43,7 @@
CONFIG_SPL_HAS_CUSTOM_MALLOC_START=y
CONFIG_SPL_CUSTOM_SYS_MALLOC_ADDR=0x42200000
CONFIG_SPL_SYS_MALLOC_SIZE=0x80000
+CONFIG_SPL_SYS_MMCSD_RAW_MODE=y
CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR=y
CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x300
CONFIG_SPL_I2C=y
diff --git a/configs/imx8mn_ddr4_evk_defconfig b/configs/imx8mn_ddr4_evk_defconfig
index 82e3ce1..93380a0 100644
--- a/configs/imx8mn_ddr4_evk_defconfig
+++ b/configs/imx8mn_ddr4_evk_defconfig
@@ -41,6 +41,7 @@
CONFIG_SPL_HAS_CUSTOM_MALLOC_START=y
CONFIG_SPL_CUSTOM_SYS_MALLOC_ADDR=0x42200000
CONFIG_SPL_SYS_MALLOC_SIZE=0x80000
+CONFIG_SPL_SYS_MMCSD_RAW_MODE=y
CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR=y
CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x300
CONFIG_SPL_I2C=y
diff --git a/configs/imx8mn_evk_defconfig b/configs/imx8mn_evk_defconfig
index 679ca71..5405f8f 100644
--- a/configs/imx8mn_evk_defconfig
+++ b/configs/imx8mn_evk_defconfig
@@ -44,6 +44,7 @@
CONFIG_SPL_HAS_CUSTOM_MALLOC_START=y
CONFIG_SPL_CUSTOM_SYS_MALLOC_ADDR=0x42200000
CONFIG_SPL_SYS_MALLOC_SIZE=0x80000
+CONFIG_SPL_SYS_MMCSD_RAW_MODE=y
CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR=y
CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x300
CONFIG_SPL_I2C=y
diff --git a/configs/imx8mn_var_som_defconfig b/configs/imx8mn_var_som_defconfig
index 218415f..0155cb2 100644
--- a/configs/imx8mn_var_som_defconfig
+++ b/configs/imx8mn_var_som_defconfig
@@ -46,6 +46,7 @@
CONFIG_SPL_HAS_CUSTOM_MALLOC_START=y
CONFIG_SPL_CUSTOM_SYS_MALLOC_ADDR=0x42200000
CONFIG_SPL_SYS_MALLOC_SIZE=0x80000
+CONFIG_SPL_SYS_MMCSD_RAW_MODE=y
CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR=y
CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x300
CONFIG_SPL_I2C=y
diff --git a/configs/imx8mn_venice_defconfig b/configs/imx8mn_venice_defconfig
index b65fef0..93e6a28 100644
--- a/configs/imx8mn_venice_defconfig
+++ b/configs/imx8mn_venice_defconfig
@@ -46,6 +46,7 @@
CONFIG_SPL_HAS_CUSTOM_MALLOC_START=y
CONFIG_SPL_CUSTOM_SYS_MALLOC_ADDR=0x42200000
CONFIG_SPL_SYS_MALLOC_SIZE=0x80000
+CONFIG_SPL_SYS_MMCSD_RAW_MODE=y
CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR=y
CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x300
CONFIG_SPL_I2C=y
diff --git a/configs/imx8mp-icore-mx8mp-edimm2.2_defconfig b/configs/imx8mp-icore-mx8mp-edimm2.2_defconfig
index 05f68c7..497a908 100644
--- a/configs/imx8mp-icore-mx8mp-edimm2.2_defconfig
+++ b/configs/imx8mp-icore-mx8mp-edimm2.2_defconfig
@@ -44,6 +44,7 @@
CONFIG_SPL_HAS_CUSTOM_MALLOC_START=y
CONFIG_SPL_CUSTOM_SYS_MALLOC_ADDR=0x42200000
CONFIG_SPL_SYS_MALLOC_SIZE=0x80000
+CONFIG_SPL_SYS_MMCSD_RAW_MODE=y
CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR=y
CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x300
CONFIG_SPL_I2C=y
diff --git a/configs/imx8mp_beacon_defconfig b/configs/imx8mp_beacon_defconfig
index 3c337d4..ba676c9 100644
--- a/configs/imx8mp_beacon_defconfig
+++ b/configs/imx8mp_beacon_defconfig
@@ -53,6 +53,7 @@
CONFIG_SPL_HAS_CUSTOM_MALLOC_START=y
CONFIG_SPL_CUSTOM_SYS_MALLOC_ADDR=0x42200000
CONFIG_SPL_SYS_MALLOC_SIZE=0x80000
+CONFIG_SPL_SYS_MMCSD_RAW_MODE=y
CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR=y
CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x300
CONFIG_SPL_I2C=y
diff --git a/configs/imx8mp_data_modul_edm_sbc_defconfig b/configs/imx8mp_data_modul_edm_sbc_defconfig
index fe3e757..0e910e2 100644
--- a/configs/imx8mp_data_modul_edm_sbc_defconfig
+++ b/configs/imx8mp_data_modul_edm_sbc_defconfig
@@ -66,6 +66,7 @@
CONFIG_SPL_HAS_CUSTOM_MALLOC_START=y
CONFIG_SPL_CUSTOM_SYS_MALLOC_ADDR=0x4c000000
CONFIG_SPL_SYS_MALLOC_SIZE=0x80000
+CONFIG_SPL_SYS_MMCSD_RAW_MODE=y
CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR=y
CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x300
CONFIG_SPL_I2C=y
@@ -112,6 +113,8 @@
CONFIG_CMD_USB=y
CONFIG_CMD_USB_SDP=y
CONFIG_CMD_USB_MASS_STORAGE=y
+CONFIG_CMD_CAT=y
+CONFIG_CMD_XXD=y
CONFIG_CMD_DHCP=y
CONFIG_CMD_DHCP6=y
CONFIG_CMD_TFTPPUT=y
diff --git a/configs/imx8mp_debix_model_a_defconfig b/configs/imx8mp_debix_model_a_defconfig
index aa1de6d..c76ab23 100644
--- a/configs/imx8mp_debix_model_a_defconfig
+++ b/configs/imx8mp_debix_model_a_defconfig
@@ -37,6 +37,7 @@
CONFIG_SPL_BOOTROM_SUPPORT=y
CONFIG_SPL_SYS_MALLOC_SIMPLE=y
# CONFIG_SPL_SHARES_INIT_SP_ADDR is not set
+CONFIG_SPL_SYS_MMCSD_RAW_MODE=y
CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR=y
CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x300
CONFIG_SPL_I2C=y
diff --git a/configs/imx8mp_dhcom_pdk2_defconfig b/configs/imx8mp_dhcom_pdk2_defconfig
index 79b3e96..f807b0c 100644
--- a/configs/imx8mp_dhcom_pdk2_defconfig
+++ b/configs/imx8mp_dhcom_pdk2_defconfig
@@ -64,6 +64,7 @@
CONFIG_SPL_HAS_CUSTOM_MALLOC_START=y
CONFIG_SPL_CUSTOM_SYS_MALLOC_ADDR=0x4c000000
CONFIG_SPL_SYS_MALLOC_SIZE=0x80000
+CONFIG_SPL_SYS_MMCSD_RAW_MODE=y
CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR=y
CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x300
# CONFIG_SPL_FIT_IMAGE_TINY is not set
diff --git a/configs/imx8mp_dhcom_pdk3_defconfig b/configs/imx8mp_dhcom_pdk3_defconfig
index 8ef8bf4..05895d6 100644
--- a/configs/imx8mp_dhcom_pdk3_defconfig
+++ b/configs/imx8mp_dhcom_pdk3_defconfig
@@ -66,6 +66,7 @@
CONFIG_SPL_HAS_CUSTOM_MALLOC_START=y
CONFIG_SPL_CUSTOM_SYS_MALLOC_ADDR=0x4c000000
CONFIG_SPL_SYS_MALLOC_SIZE=0x80000
+CONFIG_SPL_SYS_MMCSD_RAW_MODE=y
CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR=y
CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x300
# CONFIG_SPL_FIT_IMAGE_TINY is not set
diff --git a/configs/imx8mp_evk_defconfig b/configs/imx8mp_evk_defconfig
index a2c0796..4b9ac30 100644
--- a/configs/imx8mp_evk_defconfig
+++ b/configs/imx8mp_evk_defconfig
@@ -41,6 +41,7 @@
CONFIG_SPL_HAS_CUSTOM_MALLOC_START=y
CONFIG_SPL_CUSTOM_SYS_MALLOC_ADDR=0x42200000
CONFIG_SPL_SYS_MALLOC_SIZE=0x80000
+CONFIG_SPL_SYS_MMCSD_RAW_MODE=y
CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR=y
CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x300
CONFIG_SPL_I2C=y
diff --git a/configs/imx8mp_rsb3720a1_4G_defconfig b/configs/imx8mp_rsb3720a1_4G_defconfig
index 5478936..7a7f390 100644
--- a/configs/imx8mp_rsb3720a1_4G_defconfig
+++ b/configs/imx8mp_rsb3720a1_4G_defconfig
@@ -53,6 +53,8 @@
CONFIG_SPL_HAS_CUSTOM_MALLOC_START=y
CONFIG_SPL_CUSTOM_SYS_MALLOC_ADDR=0x42200000
CONFIG_SPL_SYS_MALLOC_SIZE=0x80000
+CONFIG_SPL_SYS_MMCSD_RAW_MODE=y
+CONFIG_SPL_SYS_MMCSD_RAW_MODE=y
CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR=y
CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x300
CONFIG_SPL_I2C=y
diff --git a/configs/imx8mp_rsb3720a1_6G_defconfig b/configs/imx8mp_rsb3720a1_6G_defconfig
index 4b0b71d..75d110f 100644
--- a/configs/imx8mp_rsb3720a1_6G_defconfig
+++ b/configs/imx8mp_rsb3720a1_6G_defconfig
@@ -53,6 +53,7 @@
CONFIG_SPL_HAS_CUSTOM_MALLOC_START=y
CONFIG_SPL_CUSTOM_SYS_MALLOC_ADDR=0x42200000
CONFIG_SPL_SYS_MALLOC_SIZE=0x80000
+CONFIG_SPL_SYS_MMCSD_RAW_MODE=y
CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR=y
CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x300
CONFIG_SPL_I2C=y
diff --git a/configs/imx8mp_venice_defconfig b/configs/imx8mp_venice_defconfig
index df93774..b08e4ae 100644
--- a/configs/imx8mp_venice_defconfig
+++ b/configs/imx8mp_venice_defconfig
@@ -48,6 +48,7 @@
CONFIG_SPL_HAS_CUSTOM_MALLOC_START=y
CONFIG_SPL_CUSTOM_SYS_MALLOC_ADDR=0x42200000
CONFIG_SPL_SYS_MALLOC_SIZE=0x80000
+CONFIG_SPL_SYS_MMCSD_RAW_MODE=y
CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR=y
CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x300
CONFIG_SPL_I2C=y
diff --git a/configs/imx8mq_cm_defconfig b/configs/imx8mq_cm_defconfig
index 5eb96d3..ac45c3d 100644
--- a/configs/imx8mq_cm_defconfig
+++ b/configs/imx8mq_cm_defconfig
@@ -40,6 +40,7 @@
CONFIG_SPL_HAS_CUSTOM_MALLOC_START=y
CONFIG_SPL_CUSTOM_SYS_MALLOC_ADDR=0x42200000
CONFIG_SPL_SYS_MALLOC_SIZE=0x80000
+CONFIG_SPL_SYS_MMCSD_RAW_MODE=y
CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR=y
CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x300
CONFIG_SPL_I2C=y
diff --git a/configs/imx8mq_evk_defconfig b/configs/imx8mq_evk_defconfig
index 3c1701a..2a51681 100644
--- a/configs/imx8mq_evk_defconfig
+++ b/configs/imx8mq_evk_defconfig
@@ -42,6 +42,7 @@
CONFIG_SPL_HAS_CUSTOM_MALLOC_START=y
CONFIG_SPL_CUSTOM_SYS_MALLOC_ADDR=0x42200000
CONFIG_SPL_SYS_MALLOC_SIZE=0x80000
+CONFIG_SPL_SYS_MMCSD_RAW_MODE=y
CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR=y
CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x300
CONFIG_SPL_I2C=y
diff --git a/configs/imx8mq_phanbell_defconfig b/configs/imx8mq_phanbell_defconfig
index 3a3fb75..4c36827 100644
--- a/configs/imx8mq_phanbell_defconfig
+++ b/configs/imx8mq_phanbell_defconfig
@@ -43,6 +43,7 @@
CONFIG_SPL_HAS_CUSTOM_MALLOC_START=y
CONFIG_SPL_CUSTOM_SYS_MALLOC_ADDR=0x42200000
CONFIG_SPL_SYS_MALLOC_SIZE=0x80000
+CONFIG_SPL_SYS_MMCSD_RAW_MODE=y
CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR=y
CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x300
CONFIG_SPL_I2C=y
diff --git a/configs/imx8mq_reform2_defconfig b/configs/imx8mq_reform2_defconfig
index 1844e3c..2a951f1 100644
--- a/configs/imx8mq_reform2_defconfig
+++ b/configs/imx8mq_reform2_defconfig
@@ -45,6 +45,7 @@
CONFIG_SPL_HAS_CUSTOM_MALLOC_START=y
CONFIG_SPL_CUSTOM_SYS_MALLOC_ADDR=0x42200000
CONFIG_SPL_SYS_MALLOC_SIZE=0x80000
+CONFIG_SPL_SYS_MMCSD_RAW_MODE=y
CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR=y
CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x300
CONFIG_SPL_I2C=y
diff --git a/configs/imx8qm_mek_defconfig b/configs/imx8qm_mek_defconfig
index bf02d3e..a96fb31 100644
--- a/configs/imx8qm_mek_defconfig
+++ b/configs/imx8qm_mek_defconfig
@@ -48,6 +48,7 @@
CONFIG_SPL_HAS_CUSTOM_MALLOC_START=y
CONFIG_SPL_CUSTOM_SYS_MALLOC_ADDR=0x120000
CONFIG_SPL_SYS_MALLOC_SIZE=0x3000
+CONFIG_SPL_SYS_MMCSD_RAW_MODE=y
CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR=y
CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x800
CONFIG_SPL_POWER_DOMAIN=y
diff --git a/configs/imx8qxp_mek_defconfig b/configs/imx8qxp_mek_defconfig
index d6b79f5..56cc834 100644
--- a/configs/imx8qxp_mek_defconfig
+++ b/configs/imx8qxp_mek_defconfig
@@ -49,6 +49,7 @@
CONFIG_SPL_HAS_CUSTOM_MALLOC_START=y
CONFIG_SPL_CUSTOM_SYS_MALLOC_ADDR=0x120000
CONFIG_SPL_SYS_MALLOC_SIZE=0x3000
+CONFIG_SPL_SYS_MMCSD_RAW_MODE=y
CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR=y
CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x800
CONFIG_SPL_POWER_DOMAIN=y
diff --git a/configs/imx8ulp_evk_defconfig b/configs/imx8ulp_evk_defconfig
index 0f0748b..c20b904 100644
--- a/configs/imx8ulp_evk_defconfig
+++ b/configs/imx8ulp_evk_defconfig
@@ -44,6 +44,7 @@
CONFIG_SPL_HAS_CUSTOM_MALLOC_START=y
CONFIG_SPL_CUSTOM_SYS_MALLOC_ADDR=0x22040000
CONFIG_SPL_SYS_MALLOC_SIZE=0x8000
+CONFIG_SPL_SYS_MMCSD_RAW_MODE=y
CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR=y
CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x300
CONFIG_SPL_WATCHDOG=y
diff --git a/configs/imx93-phyboard-segin_defconfig b/configs/imx93-phyboard-segin_defconfig
index e3eb002..6e9e9c5 100644
--- a/configs/imx93-phyboard-segin_defconfig
+++ b/configs/imx93-phyboard-segin_defconfig
@@ -44,6 +44,7 @@
CONFIG_SPL_LOAD_IMX_CONTAINER=y
CONFIG_IMX_CONTAINER_CFG="arch/arm/mach-imx/imx9/container.cfg"
# CONFIG_SPL_SHARES_INIT_SP_ADDR is not set
+CONFIG_SPL_SYS_MMCSD_RAW_MODE=y
CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR=y
CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x1040
CONFIG_SPL_I2C=y
diff --git a/configs/imx93_11x11_evk_defconfig b/configs/imx93_11x11_evk_defconfig
index 6f083e0..198d43e 100644
--- a/configs/imx93_11x11_evk_defconfig
+++ b/configs/imx93_11x11_evk_defconfig
@@ -42,6 +42,7 @@
CONFIG_SPL_HAS_CUSTOM_MALLOC_START=y
CONFIG_SPL_CUSTOM_SYS_MALLOC_ADDR=0x83200000
CONFIG_SPL_SYS_MALLOC_SIZE=0x80000
+CONFIG_SPL_SYS_MMCSD_RAW_MODE=y
CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR=y
CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x1040
CONFIG_SPL_I2C=y
diff --git a/configs/imx93_11x11_evk_ld_defconfig b/configs/imx93_11x11_evk_ld_defconfig
index deed068..fd33fd5 100644
--- a/configs/imx93_11x11_evk_ld_defconfig
+++ b/configs/imx93_11x11_evk_ld_defconfig
@@ -43,6 +43,7 @@
CONFIG_SPL_HAS_CUSTOM_MALLOC_START=y
CONFIG_SPL_CUSTOM_SYS_MALLOC_ADDR=0x83200000
CONFIG_SPL_SYS_MALLOC_SIZE=0x80000
+CONFIG_SPL_SYS_MMCSD_RAW_MODE=y
CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR=y
CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x1040
CONFIG_SPL_I2C=y
diff --git a/configs/imx93_var_som_defconfig b/configs/imx93_var_som_defconfig
index 94ce213..14f220e 100644
--- a/configs/imx93_var_som_defconfig
+++ b/configs/imx93_var_som_defconfig
@@ -45,6 +45,7 @@
CONFIG_SPL_LOAD_IMX_CONTAINER=y
CONFIG_IMX_CONTAINER_CFG="arch/arm/mach-imx/imx9/container.cfg"
# CONFIG_SPL_SHARES_INIT_SP_ADDR is not set
+CONFIG_SPL_SYS_MMCSD_RAW_MODE=y
CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR=y
CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x1040
CONFIG_SPL_I2C=y
diff --git a/configs/imxrt1020-evk_defconfig b/configs/imxrt1020-evk_defconfig
index 80c8769..72bbd72 100644
--- a/configs/imxrt1020-evk_defconfig
+++ b/configs/imxrt1020-evk_defconfig
@@ -31,6 +31,7 @@
CONFIG_SPL_BOARD_INIT=y
# CONFIG_SPL_RAW_IMAGE_SUPPORT is not set
CONFIG_SPL_SYS_MALLOC_SIMPLE=y
+CONFIG_SPL_SYS_MMCSD_RAW_MODE=y
CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR=y
CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x100
# CONFIG_BOOTM_NETBSD is not set
diff --git a/configs/imxrt1050-evk_defconfig b/configs/imxrt1050-evk_defconfig
index 086fc47..fdbce8e 100644
--- a/configs/imxrt1050-evk_defconfig
+++ b/configs/imxrt1050-evk_defconfig
@@ -35,6 +35,7 @@
CONFIG_SPL_BOARD_INIT=y
# CONFIG_SPL_RAW_IMAGE_SUPPORT is not set
CONFIG_SPL_SYS_MALLOC_SIMPLE=y
+CONFIG_SPL_SYS_MMCSD_RAW_MODE=y
CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR=y
CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x100
CONFIG_SPL_NOR_SUPPORT=y
diff --git a/configs/imxrt1050-evk_fspi_defconfig b/configs/imxrt1050-evk_fspi_defconfig
index 4b252cf..03543ed 100644
--- a/configs/imxrt1050-evk_fspi_defconfig
+++ b/configs/imxrt1050-evk_fspi_defconfig
@@ -36,6 +36,7 @@
CONFIG_SPL_BOARD_INIT=y
# CONFIG_SPL_RAW_IMAGE_SUPPORT is not set
CONFIG_SPL_SYS_MALLOC_SIMPLE=y
+CONFIG_SPL_SYS_MMCSD_RAW_MODE=y
CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR=y
CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x100
CONFIG_SPL_NOR_SUPPORT=y
diff --git a/configs/imxrt1170-evk_defconfig b/configs/imxrt1170-evk_defconfig
index 83825da..fe0058a 100644
--- a/configs/imxrt1170-evk_defconfig
+++ b/configs/imxrt1170-evk_defconfig
@@ -31,6 +31,7 @@
CONFIG_SPL_BOARD_INIT=y
# CONFIG_SPL_RAW_IMAGE_SUPPORT is not set
CONFIG_SPL_SYS_MALLOC_SIMPLE=y
+CONFIG_SPL_SYS_MMCSD_RAW_MODE=y
CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR=y
CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x100
# CONFIG_BOOTM_NETBSD is not set
diff --git a/configs/iot2050_defconfig b/configs/iot2050_defconfig
index 8654bf2..2a7a958 100644
--- a/configs/iot2050_defconfig
+++ b/configs/iot2050_defconfig
@@ -53,6 +53,7 @@
CONFIG_SPL_SYS_MALLOC_SIMPLE=y
CONFIG_SPL_SYS_MALLOC=y
CONFIG_SPL_SYS_MALLOC_SIZE=0x800000
+CONFIG_SPL_SYS_MMCSD_RAW_MODE=y
CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR=y
CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x1400
CONFIG_SPL_DM_MAILBOX=y
diff --git a/configs/j7200_evm_a72_defconfig b/configs/j7200_evm_a72_defconfig
index fcfa926..137ca3f 100644
--- a/configs/j7200_evm_a72_defconfig
+++ b/configs/j7200_evm_a72_defconfig
@@ -45,6 +45,7 @@
CONFIG_SPL_SYS_MALLOC_SIMPLE=y
CONFIG_SPL_SYS_MALLOC=y
CONFIG_SPL_SYS_MALLOC_SIZE=0x800000
+CONFIG_SPL_SYS_MMCSD_RAW_MODE=y
CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR=y
CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x1800
CONFIG_SPL_DMA=y
diff --git a/configs/j7200_evm_r5_defconfig b/configs/j7200_evm_r5_defconfig
index e023af2..774a9ef 100644
--- a/configs/j7200_evm_r5_defconfig
+++ b/configs/j7200_evm_r5_defconfig
@@ -44,6 +44,7 @@
CONFIG_SPL_CUSTOM_SYS_MALLOC_ADDR=0x84000000
CONFIG_SPL_SYS_MALLOC_SIZE=0x1000000
CONFIG_SPL_EARLY_BSS=y
+CONFIG_SPL_SYS_MMCSD_RAW_MODE=y
CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR=y
CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x800
CONFIG_SPL_DMA=y
diff --git a/configs/j721e_beagleboneai64_a72_defconfig b/configs/j721e_beagleboneai64_a72_defconfig
index 86c565a..ed75f7e 100644
--- a/configs/j721e_beagleboneai64_a72_defconfig
+++ b/configs/j721e_beagleboneai64_a72_defconfig
@@ -44,6 +44,7 @@
CONFIG_SPL_SYS_MALLOC_SIMPLE=y
CONFIG_SPL_SYS_MALLOC=y
CONFIG_SPL_SYS_MALLOC_SIZE=0x800000
+CONFIG_SPL_SYS_MMCSD_RAW_MODE=y
CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR=y
CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x1400
CONFIG_SPL_DMA=y
diff --git a/configs/j721e_beagleboneai64_r5_defconfig b/configs/j721e_beagleboneai64_r5_defconfig
index 314161b..ce96e49 100644
--- a/configs/j721e_beagleboneai64_r5_defconfig
+++ b/configs/j721e_beagleboneai64_r5_defconfig
@@ -42,6 +42,7 @@
CONFIG_SPL_CUSTOM_SYS_MALLOC_ADDR=0x84000000
CONFIG_SPL_SYS_MALLOC_SIZE=0x1000000
CONFIG_SPL_EARLY_BSS=y
+CONFIG_SPL_SYS_MMCSD_RAW_MODE=y
CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR=y
CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x400
CONFIG_SPL_DMA=y
diff --git a/configs/j721e_evm_a72_defconfig b/configs/j721e_evm_a72_defconfig
index f993157..640c1be 100644
--- a/configs/j721e_evm_a72_defconfig
+++ b/configs/j721e_evm_a72_defconfig
@@ -44,6 +44,7 @@
CONFIG_SPL_SYS_MALLOC_SIMPLE=y
CONFIG_SPL_SYS_MALLOC=y
CONFIG_SPL_SYS_MALLOC_SIZE=0x800000
+CONFIG_SPL_SYS_MMCSD_RAW_MODE=y
CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR=y
CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x1400
CONFIG_SPL_DMA=y
diff --git a/configs/j721e_evm_r5_defconfig b/configs/j721e_evm_r5_defconfig
index f1c9bbd..3b4a7c3 100644
--- a/configs/j721e_evm_r5_defconfig
+++ b/configs/j721e_evm_r5_defconfig
@@ -49,6 +49,7 @@
CONFIG_SPL_CUSTOM_SYS_MALLOC_ADDR=0x84000000
CONFIG_SPL_SYS_MALLOC_SIZE=0x1000000
CONFIG_SPL_EARLY_BSS=y
+CONFIG_SPL_SYS_MMCSD_RAW_MODE=y
CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR=y
CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x400
CONFIG_SPL_DMA=y
diff --git a/configs/j721s2_evm_a72_defconfig b/configs/j721s2_evm_a72_defconfig
index 5800e4b..d78ebb5 100644
--- a/configs/j721s2_evm_a72_defconfig
+++ b/configs/j721s2_evm_a72_defconfig
@@ -43,6 +43,7 @@
CONFIG_SPL_SYS_MALLOC_SIMPLE=y
CONFIG_SPL_SYS_MALLOC=y
CONFIG_SPL_SYS_MALLOC_SIZE=0x800000
+CONFIG_SPL_SYS_MMCSD_RAW_MODE=y
CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR=y
CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x1400
CONFIG_SPL_DMA=y
diff --git a/configs/j721s2_evm_r5_defconfig b/configs/j721s2_evm_r5_defconfig
index d0af664..b6adb6a 100644
--- a/configs/j721s2_evm_r5_defconfig
+++ b/configs/j721s2_evm_r5_defconfig
@@ -50,6 +50,7 @@
CONFIG_SPL_CUSTOM_SYS_MALLOC_ADDR=0x84000000
CONFIG_SPL_SYS_MALLOC_SIZE=0x1000000
CONFIG_SPL_EARLY_BSS=y
+CONFIG_SPL_SYS_MMCSD_RAW_MODE=y
CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR=y
CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x400
CONFIG_SPL_DMA=y
diff --git a/configs/j722s_evm_a53_defconfig b/configs/j722s_evm_a53_defconfig
index 1675ced..9862022 100644
--- a/configs/j722s_evm_a53_defconfig
+++ b/configs/j722s_evm_a53_defconfig
@@ -37,6 +37,7 @@
CONFIG_SPL_MAX_SIZE=0x58000
CONFIG_SPL_PAD_TO=0x0
CONFIG_SPL_SYS_MALLOC_SIMPLE=y
+CONFIG_SPL_SYS_MMCSD_RAW_MODE=y
CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR=y
CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x1400
CONFIG_SPL_DMA=y
diff --git a/configs/j722s_evm_r5_defconfig b/configs/j722s_evm_r5_defconfig
index 8ba3916..e574be9 100644
--- a/configs/j722s_evm_r5_defconfig
+++ b/configs/j722s_evm_r5_defconfig
@@ -40,6 +40,7 @@
CONFIG_SPL_SYS_MALLOC_SIMPLE=y
CONFIG_SPL_SEPARATE_BSS=y
CONFIG_SPL_EARLY_BSS=y
+CONFIG_SPL_SYS_MMCSD_RAW_MODE=y
CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR=y
CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x400
CONFIG_SPL_DMA=y
diff --git a/configs/j784s4_evm_a72_defconfig b/configs/j784s4_evm_a72_defconfig
index 520a53b..f022017 100644
--- a/configs/j784s4_evm_a72_defconfig
+++ b/configs/j784s4_evm_a72_defconfig
@@ -38,6 +38,7 @@
CONFIG_SPL_MAX_SIZE=0xc0000
CONFIG_SPL_BOARD_INIT=y
CONFIG_SPL_SYS_MALLOC_SIMPLE=y
+CONFIG_SPL_SYS_MMCSD_RAW_MODE=y
CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR=y
CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x1400
CONFIG_SPL_DMA=y
diff --git a/configs/j784s4_evm_r5_defconfig b/configs/j784s4_evm_r5_defconfig
index 543b0a5..a116881 100644
--- a/configs/j784s4_evm_r5_defconfig
+++ b/configs/j784s4_evm_r5_defconfig
@@ -44,6 +44,7 @@
CONFIG_SPL_SYS_MALLOC_SIMPLE=y
CONFIG_SPL_SEPARATE_BSS=y
CONFIG_SPL_EARLY_BSS=y
+CONFIG_SPL_SYS_MMCSD_RAW_MODE=y
CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR=y
CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x400
CONFIG_SPL_DMA=y
diff --git a/configs/k2e_evm_defconfig b/configs/k2e_evm_defconfig
index 8d6cb24..f201a175 100644
--- a/configs/k2e_evm_defconfig
+++ b/configs/k2e_evm_defconfig
@@ -18,7 +18,7 @@
CONFIG_ENV_SIZE=0x40000
CONFIG_ENV_OFFSET=0x100000
CONFIG_SPL_DM_SPI=y
-CONFIG_DEFAULT_DEVICE_TREE="keystone-k2e-evm"
+CONFIG_DEFAULT_DEVICE_TREE="ti/keystone/keystone-k2e-evm"
CONFIG_SPL_TEXT_BASE=0xC100000
CONFIG_SPL_SERIAL=y
CONFIG_SPL_STACK=0xc1223f4
@@ -99,3 +99,4 @@
CONFIG_USB_XHCI_DWC3=y
CONFIG_USB_DWC3=y
CONFIG_USB_DWC3_GENERIC=y
+CONFIG_OF_UPSTREAM=y
diff --git a/configs/k2e_hs_evm_defconfig b/configs/k2e_hs_evm_defconfig
index e3c0ae1..46501d5 100644
--- a/configs/k2e_hs_evm_defconfig
+++ b/configs/k2e_hs_evm_defconfig
@@ -15,7 +15,7 @@
CONFIG_SF_DEFAULT_SPEED=30000000
CONFIG_ENV_SIZE=0x40000
CONFIG_ENV_OFFSET=0x100000
-CONFIG_DEFAULT_DEVICE_TREE="keystone-k2e-evm"
+CONFIG_DEFAULT_DEVICE_TREE="ti/keystone/keystone-k2e-evm"
CONFIG_TIMESTAMP=y
CONFIG_DISTRO_DEFAULTS=y
CONFIG_OF_BOARD_SETUP=y
@@ -73,3 +73,4 @@
CONFIG_USB_XHCI_DWC3=y
CONFIG_USB_DWC3=y
CONFIG_USB_DWC3_GENERIC=y
+CONFIG_OF_UPSTREAM=y
diff --git a/configs/k2g_evm_defconfig b/configs/k2g_evm_defconfig
index 5d54d75..57a3d36 100644
--- a/configs/k2g_evm_defconfig
+++ b/configs/k2g_evm_defconfig
@@ -17,7 +17,7 @@
CONFIG_SF_DEFAULT_SPEED=30000000
CONFIG_ENV_SIZE=0x40000
CONFIG_SPL_DM_SPI=y
-CONFIG_DEFAULT_DEVICE_TREE="keystone-k2g-evm"
+CONFIG_DEFAULT_DEVICE_TREE="ti/keystone/keystone-k2g-evm"
CONFIG_SPL_TEXT_BASE=0xC0A0000
CONFIG_SPL_SERIAL=y
CONFIG_SPL_STACK=0xc0c23f4
@@ -57,7 +57,7 @@
CONFIG_CMD_UBI=y
CONFIG_OF_CONTROL=y
CONFIG_SPL_OF_CONTROL=y
-CONFIG_OF_LIST="keystone-k2g-generic keystone-k2g-evm keystone-k2g-ice"
+CONFIG_OF_LIST="ti/keystone/keystone-k2g-evm ti/keystone/keystone-k2g-ice"
CONFIG_DTB_RESELECT=y
CONFIG_MULTI_DTB_FIT=y
CONFIG_ENV_OVERWRITE=y
@@ -109,3 +109,4 @@
CONFIG_USB_GADGET=y
CONFIG_USB_GADGET_DOWNLOAD=y
CONFIG_USB_FUNCTION_SDP=y
+CONFIG_OF_UPSTREAM=y
diff --git a/configs/k2g_hs_evm_defconfig b/configs/k2g_hs_evm_defconfig
index 9adab3a..392ec5b 100644
--- a/configs/k2g_hs_evm_defconfig
+++ b/configs/k2g_hs_evm_defconfig
@@ -14,7 +14,7 @@
CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0xc09ff10
CONFIG_SF_DEFAULT_SPEED=30000000
CONFIG_ENV_SIZE=0x40000
-CONFIG_DEFAULT_DEVICE_TREE="keystone-k2g-evm"
+CONFIG_DEFAULT_DEVICE_TREE="ti/keystone/keystone-k2g-evm"
CONFIG_TIMESTAMP=y
CONFIG_DISTRO_DEFAULTS=y
CONFIG_OF_BOARD_SETUP=y
@@ -33,7 +33,7 @@
CONFIG_MTDIDS_DEFAULT="nand0=davinci_nand.0"
CONFIG_CMD_UBI=y
CONFIG_OF_CONTROL=y
-CONFIG_OF_LIST="keystone-k2g-generic keystone-k2g-evm keystone-k2g-ice"
+CONFIG_OF_LIST="ti/keystone/keystone-k2g-evm ti/keystone/keystone-k2g-ice"
CONFIG_DTB_RESELECT=y
CONFIG_MULTI_DTB_FIT=y
CONFIG_ENV_OVERWRITE=y
@@ -84,3 +84,4 @@
CONFIG_USB_GADGET=y
CONFIG_USB_GADGET_DOWNLOAD=y
CONFIG_USB_FUNCTION_SDP=y
+CONFIG_OF_UPSTREAM=y
diff --git a/configs/k2hk_evm_defconfig b/configs/k2hk_evm_defconfig
index 4da75d1..2e29b2f 100644
--- a/configs/k2hk_evm_defconfig
+++ b/configs/k2hk_evm_defconfig
@@ -18,7 +18,7 @@
CONFIG_ENV_SIZE=0x40000
CONFIG_ENV_OFFSET=0x100000
CONFIG_SPL_DM_SPI=y
-CONFIG_DEFAULT_DEVICE_TREE="keystone-k2hk-evm"
+CONFIG_DEFAULT_DEVICE_TREE="ti/keystone/keystone-k2hk-evm"
CONFIG_SPL_TEXT_BASE=0xC200000
CONFIG_SPL_SERIAL=y
CONFIG_SPL_STACK=0xc2223f4
@@ -100,3 +100,4 @@
CONFIG_USB_XHCI_DWC3=y
CONFIG_USB_DWC3=y
CONFIG_USB_DWC3_GENERIC=y
+CONFIG_OF_UPSTREAM=y
diff --git a/configs/k2hk_hs_evm_defconfig b/configs/k2hk_hs_evm_defconfig
index 1a24d71..cf299f2 100644
--- a/configs/k2hk_hs_evm_defconfig
+++ b/configs/k2hk_hs_evm_defconfig
@@ -15,7 +15,7 @@
CONFIG_SF_DEFAULT_SPEED=30000000
CONFIG_ENV_SIZE=0x40000
CONFIG_ENV_OFFSET=0x100000
-CONFIG_DEFAULT_DEVICE_TREE="keystone-k2hk-evm"
+CONFIG_DEFAULT_DEVICE_TREE="ti/keystone/keystone-k2hk-evm"
CONFIG_TIMESTAMP=y
CONFIG_DISTRO_DEFAULTS=y
CONFIG_OF_BOARD_SETUP=y
@@ -74,3 +74,4 @@
CONFIG_USB_XHCI_DWC3=y
CONFIG_USB_DWC3=y
CONFIG_USB_DWC3_GENERIC=y
+CONFIG_OF_UPSTREAM=y
diff --git a/configs/k2l_evm_defconfig b/configs/k2l_evm_defconfig
index c4534f0..0cadece 100644
--- a/configs/k2l_evm_defconfig
+++ b/configs/k2l_evm_defconfig
@@ -18,7 +18,7 @@
CONFIG_ENV_SIZE=0x40000
CONFIG_ENV_OFFSET=0x100000
CONFIG_SPL_DM_SPI=y
-CONFIG_DEFAULT_DEVICE_TREE="keystone-k2l-evm"
+CONFIG_DEFAULT_DEVICE_TREE="ti/keystone/keystone-k2l-evm"
CONFIG_SPL_TEXT_BASE=0xC100000
CONFIG_SPL_SERIAL=y
CONFIG_SPL_STACK=0xc1223f4
@@ -100,3 +100,4 @@
CONFIG_USB_XHCI_DWC3=y
CONFIG_USB_DWC3=y
CONFIG_USB_DWC3_GENERIC=y
+CONFIG_OF_UPSTREAM=y
diff --git a/configs/k2l_hs_evm_defconfig b/configs/k2l_hs_evm_defconfig
index c874349..5496049 100644
--- a/configs/k2l_hs_evm_defconfig
+++ b/configs/k2l_hs_evm_defconfig
@@ -15,7 +15,7 @@
CONFIG_SF_DEFAULT_SPEED=30000000
CONFIG_ENV_SIZE=0x40000
CONFIG_ENV_OFFSET=0x100000
-CONFIG_DEFAULT_DEVICE_TREE="keystone-k2l-evm"
+CONFIG_DEFAULT_DEVICE_TREE="ti/keystone/keystone-k2l-evm"
CONFIG_TIMESTAMP=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_USE_BOOTCOMMAND=y
@@ -78,3 +78,4 @@
CONFIG_USB_DWC3=y
CONFIG_USB_DWC3_GENERIC=y
CONFIG_USB_STORAGE=y
+CONFIG_OF_UPSTREAM=y
diff --git a/configs/kontron-sl-mx8mm_defconfig b/configs/kontron-sl-mx8mm_defconfig
index 1b7d22b..d85a433 100644
--- a/configs/kontron-sl-mx8mm_defconfig
+++ b/configs/kontron-sl-mx8mm_defconfig
@@ -44,6 +44,7 @@
CONFIG_SPL_HAS_CUSTOM_MALLOC_START=y
CONFIG_SPL_CUSTOM_SYS_MALLOC_ADDR=0x42200000
CONFIG_SPL_SYS_MALLOC_SIZE=0x80000
+CONFIG_SPL_SYS_MMCSD_RAW_MODE=y
CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR=y
CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x300
CONFIG_SPL_I2C=y
diff --git a/configs/kontron_pitx_imx8m_defconfig b/configs/kontron_pitx_imx8m_defconfig
index c213347..5223883 100644
--- a/configs/kontron_pitx_imx8m_defconfig
+++ b/configs/kontron_pitx_imx8m_defconfig
@@ -44,6 +44,7 @@
CONFIG_SPL_HAS_CUSTOM_MALLOC_START=y
CONFIG_SPL_CUSTOM_SYS_MALLOC_ADDR=0x42200000
CONFIG_SPL_SYS_MALLOC_SIZE=0x80000
+CONFIG_SPL_SYS_MMCSD_RAW_MODE=y
CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR=y
CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x300
CONFIG_SPL_I2C=y
diff --git a/configs/kontron_sl28_defconfig b/configs/kontron_sl28_defconfig
index a1d5f89..c4493e5 100644
--- a/configs/kontron_sl28_defconfig
+++ b/configs/kontron_sl28_defconfig
@@ -51,6 +51,7 @@
CONFIG_SPL_BOARD_INIT=y
# CONFIG_SPL_SHARES_INIT_SP_ADDR is not set
CONFIG_SPL_SYS_MALLOC=y
+CONFIG_SPL_SYS_MMCSD_RAW_MODE=y
CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR=y
CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x900
CONFIG_SPL_MPC8XXX_INIT_DDR=y
diff --git a/configs/librem5_defconfig b/configs/librem5_defconfig
index 6999a68..248fc1f 100644
--- a/configs/librem5_defconfig
+++ b/configs/librem5_defconfig
@@ -46,6 +46,7 @@
CONFIG_SPL_HAS_CUSTOM_MALLOC_START=y
CONFIG_SPL_CUSTOM_SYS_MALLOC_ADDR=0x42200000
CONFIG_SPL_SYS_MALLOC_SIZE=0x80000
+CONFIG_SPL_SYS_MMCSD_RAW_MODE=y
CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR=y
CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x300
CONFIG_SPL_I2C=y
diff --git a/configs/ls1021aiot_sdcard_defconfig b/configs/ls1021aiot_sdcard_defconfig
index 2354f41..981093a 100644
--- a/configs/ls1021aiot_sdcard_defconfig
+++ b/configs/ls1021aiot_sdcard_defconfig
@@ -49,6 +49,7 @@
CONFIG_SPL_SYS_MALLOC=y
CONFIG_SPL_HAS_CUSTOM_MALLOC_START=y
CONFIG_SPL_CUSTOM_SYS_MALLOC_ADDR=0x82080000
+CONFIG_SPL_SYS_MMCSD_RAW_MODE=y
CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR=y
CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0xe8
CONFIG_SPL_ENV_SUPPORT=y
diff --git a/configs/ls1021aqds_nand_defconfig b/configs/ls1021aqds_nand_defconfig
index 136ca9a..4fc0e66 100644
--- a/configs/ls1021aqds_nand_defconfig
+++ b/configs/ls1021aqds_nand_defconfig
@@ -60,6 +60,7 @@
CONFIG_SPL_SYS_MALLOC=y
CONFIG_SPL_HAS_CUSTOM_MALLOC_START=y
CONFIG_SPL_CUSTOM_SYS_MALLOC_ADDR=0x80200000
+CONFIG_SPL_SYS_MMCSD_RAW_MODE=y
CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR=y
CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0xe8
CONFIG_SPL_ENV_SUPPORT=y
diff --git a/configs/ls1021aqds_sdcard_ifc_defconfig b/configs/ls1021aqds_sdcard_ifc_defconfig
index befb4ae..72632b8 100644
--- a/configs/ls1021aqds_sdcard_ifc_defconfig
+++ b/configs/ls1021aqds_sdcard_ifc_defconfig
@@ -59,6 +59,7 @@
CONFIG_SPL_SYS_MALLOC=y
CONFIG_SPL_HAS_CUSTOM_MALLOC_START=y
CONFIG_SPL_CUSTOM_SYS_MALLOC_ADDR=0x820c0000
+CONFIG_SPL_SYS_MMCSD_RAW_MODE=y
CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR=y
CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0xe8
CONFIG_SPL_ENV_SUPPORT=y
diff --git a/configs/ls1021aqds_sdcard_qspi_defconfig b/configs/ls1021aqds_sdcard_qspi_defconfig
index db06a03..78dce4d 100644
--- a/configs/ls1021aqds_sdcard_qspi_defconfig
+++ b/configs/ls1021aqds_sdcard_qspi_defconfig
@@ -58,6 +58,7 @@
CONFIG_SPL_SYS_MALLOC=y
CONFIG_SPL_HAS_CUSTOM_MALLOC_START=y
CONFIG_SPL_CUSTOM_SYS_MALLOC_ADDR=0x820c0000
+CONFIG_SPL_SYS_MMCSD_RAW_MODE=y
CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR=y
CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0xe8
CONFIG_SPL_ENV_SUPPORT=y
diff --git a/configs/ls1021atsn_sdcard_defconfig b/configs/ls1021atsn_sdcard_defconfig
index e5d8eeb..0853bfb 100644
--- a/configs/ls1021atsn_sdcard_defconfig
+++ b/configs/ls1021atsn_sdcard_defconfig
@@ -52,6 +52,7 @@
CONFIG_SPL_SYS_MALLOC=y
CONFIG_SPL_HAS_CUSTOM_MALLOC_START=y
CONFIG_SPL_CUSTOM_SYS_MALLOC_ADDR=0x82100000
+CONFIG_SPL_SYS_MMCSD_RAW_MODE=y
CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR=y
CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0xe8
CONFIG_SPL_ENV_SUPPORT=y
diff --git a/configs/ls1021atwr_sdcard_ifc_SECURE_BOOT_defconfig b/configs/ls1021atwr_sdcard_ifc_SECURE_BOOT_defconfig
index dc0e507..28434d8 100644
--- a/configs/ls1021atwr_sdcard_ifc_SECURE_BOOT_defconfig
+++ b/configs/ls1021atwr_sdcard_ifc_SECURE_BOOT_defconfig
@@ -60,6 +60,7 @@
CONFIG_SPL_SYS_MALLOC=y
CONFIG_SPL_HAS_CUSTOM_MALLOC_START=y
CONFIG_SPL_CUSTOM_SYS_MALLOC_ADDR=0x82104000
+CONFIG_SPL_SYS_MMCSD_RAW_MODE=y
CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR=y
CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0xe8
CONFIG_SPL_ENV_SUPPORT=y
diff --git a/configs/ls1021atwr_sdcard_ifc_defconfig b/configs/ls1021atwr_sdcard_ifc_defconfig
index 9980d61..b4348f1 100644
--- a/configs/ls1021atwr_sdcard_ifc_defconfig
+++ b/configs/ls1021atwr_sdcard_ifc_defconfig
@@ -61,6 +61,7 @@
CONFIG_SPL_SYS_MALLOC=y
CONFIG_SPL_HAS_CUSTOM_MALLOC_START=y
CONFIG_SPL_CUSTOM_SYS_MALLOC_ADDR=0x82100000
+CONFIG_SPL_SYS_MMCSD_RAW_MODE=y
CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR=y
CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0xe8
CONFIG_SPL_ENV_SUPPORT=y
diff --git a/configs/ls1021atwr_sdcard_qspi_defconfig b/configs/ls1021atwr_sdcard_qspi_defconfig
index ed92e34..8d2c391 100644
--- a/configs/ls1021atwr_sdcard_qspi_defconfig
+++ b/configs/ls1021atwr_sdcard_qspi_defconfig
@@ -62,6 +62,7 @@
CONFIG_SPL_SYS_MALLOC=y
CONFIG_SPL_HAS_CUSTOM_MALLOC_START=y
CONFIG_SPL_CUSTOM_SYS_MALLOC_ADDR=0x82100000
+CONFIG_SPL_SYS_MMCSD_RAW_MODE=y
CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR=y
CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0xe8
CONFIG_SPL_ENV_SUPPORT=y
diff --git a/configs/ls2080aqds_nand_defconfig b/configs/ls2080aqds_nand_defconfig
index 06e4154..0066414 100644
--- a/configs/ls2080aqds_nand_defconfig
+++ b/configs/ls2080aqds_nand_defconfig
@@ -61,7 +61,6 @@
CONFIG_CMD_USB=y
# CONFIG_CMD_SETEXPR is not set
CONFIG_CMD_CACHE=y
-CONFIG_CMD_DATE=y
# CONFIG_ISO_PARTITION is not set
# CONFIG_SPL_EFI_PARTITION is not set
CONFIG_OF_CONTROL=y
diff --git a/configs/ls2080aqds_qspi_defconfig b/configs/ls2080aqds_qspi_defconfig
index 0b54bc9..44a1459 100644
--- a/configs/ls2080aqds_qspi_defconfig
+++ b/configs/ls2080aqds_qspi_defconfig
@@ -43,7 +43,6 @@
CONFIG_CMD_USB=y
# CONFIG_CMD_SETEXPR is not set
CONFIG_CMD_CACHE=y
-CONFIG_CMD_DATE=y
# CONFIG_ISO_PARTITION is not set
CONFIG_OF_CONTROL=y
CONFIG_OF_EMBED=y
diff --git a/configs/ls2080ardb_nand_defconfig b/configs/ls2080ardb_nand_defconfig
index f1009e1..cbc8d6a 100644
--- a/configs/ls2080ardb_nand_defconfig
+++ b/configs/ls2080ardb_nand_defconfig
@@ -68,7 +68,6 @@
CONFIG_CMD_USB=y
# CONFIG_CMD_SETEXPR is not set
CONFIG_CMD_CACHE=y
-CONFIG_CMD_DATE=y
CONFIG_OF_CONTROL=y
CONFIG_ENV_OVERWRITE=y
CONFIG_ENV_IS_IN_NAND=y
diff --git a/configs/malta64_defconfig b/configs/malta64_defconfig
index ff371da..8ac29b9 100644
--- a/configs/malta64_defconfig
+++ b/configs/malta64_defconfig
@@ -27,7 +27,6 @@
# CONFIG_CMD_SETEXPR is not set
CONFIG_CMD_DHCP=y
CONFIG_CMD_PING=y
-CONFIG_CMD_DATE=y
# CONFIG_ISO_PARTITION is not set
CONFIG_ENV_IS_IN_FLASH=y
CONFIG_SYS_IDE_MAXBUS=1
diff --git a/configs/malta64el_defconfig b/configs/malta64el_defconfig
index 5b130bc..0a71013 100644
--- a/configs/malta64el_defconfig
+++ b/configs/malta64el_defconfig
@@ -29,7 +29,6 @@
# CONFIG_CMD_SETEXPR is not set
CONFIG_CMD_DHCP=y
CONFIG_CMD_PING=y
-CONFIG_CMD_DATE=y
# CONFIG_ISO_PARTITION is not set
CONFIG_ENV_IS_IN_FLASH=y
CONFIG_SYS_IDE_MAXBUS=1
diff --git a/configs/malta_defconfig b/configs/malta_defconfig
index ce917a6..355292e 100644
--- a/configs/malta_defconfig
+++ b/configs/malta_defconfig
@@ -26,7 +26,6 @@
# CONFIG_CMD_SETEXPR is not set
CONFIG_CMD_DHCP=y
CONFIG_CMD_PING=y
-CONFIG_CMD_DATE=y
# CONFIG_ISO_PARTITION is not set
CONFIG_ENV_IS_IN_FLASH=y
CONFIG_SYS_IDE_MAXBUS=1
diff --git a/configs/maltael_defconfig b/configs/maltael_defconfig
index de29a7a..ffd2771 100644
--- a/configs/maltael_defconfig
+++ b/configs/maltael_defconfig
@@ -28,7 +28,6 @@
# CONFIG_CMD_SETEXPR is not set
CONFIG_CMD_DHCP=y
CONFIG_CMD_PING=y
-CONFIG_CMD_DATE=y
# CONFIG_ISO_PARTITION is not set
CONFIG_ENV_IS_IN_FLASH=y
CONFIG_SYS_IDE_MAXBUS=1
diff --git a/configs/msc_sm2s_imx8mp_defconfig b/configs/msc_sm2s_imx8mp_defconfig
index 2e1d112..47ed5cf 100644
--- a/configs/msc_sm2s_imx8mp_defconfig
+++ b/configs/msc_sm2s_imx8mp_defconfig
@@ -43,6 +43,7 @@
CONFIG_SPL_HAS_CUSTOM_MALLOC_START=y
CONFIG_SPL_CUSTOM_SYS_MALLOC_ADDR=0x42200000
CONFIG_SPL_SYS_MALLOC_SIZE=0x80000
+CONFIG_SPL_SYS_MMCSD_RAW_MODE=y
CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR=y
CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x300
CONFIG_SPL_I2C=y
diff --git a/configs/mx28evk_defconfig b/configs/mx28evk_defconfig
index 1fe68ef..dddb57e 100644
--- a/configs/mx28evk_defconfig
+++ b/configs/mx28evk_defconfig
@@ -32,7 +32,6 @@
CONFIG_CMD_NAND_TRIMFFS=y
CONFIG_CMD_USB_MASS_STORAGE=y
CONFIG_CMD_CACHE=y
-CONFIG_CMD_DATE=y
CONFIG_CMD_EXT4=y
CONFIG_CMD_EXT4_WRITE=y
CONFIG_CMD_FAT=y
diff --git a/configs/mx51evk_defconfig b/configs/mx51evk_defconfig
index e5178fb..5932a15 100644
--- a/configs/mx51evk_defconfig
+++ b/configs/mx51evk_defconfig
@@ -31,7 +31,6 @@
CONFIG_CMD_DHCP=y
CONFIG_CMD_MII=y
CONFIG_CMD_PING=y
-CONFIG_CMD_DATE=y
CONFIG_CMD_FAT=y
CONFIG_OF_CONTROL=y
CONFIG_ENV_OVERWRITE=y
diff --git a/configs/novena_defconfig b/configs/novena_defconfig
index 322689e..dd3541b 100644
--- a/configs/novena_defconfig
+++ b/configs/novena_defconfig
@@ -67,7 +67,7 @@
CONFIG_BOUNCE_BUFFER=y
CONFIG_DWC_AHSATA=y
CONFIG_LBA48=y
-CONFIG_SYS_I2C_LEGACY=y
+CONFIG_DM_I2C=y
CONFIG_SPL_SYS_I2C_LEGACY=y
CONFIG_SYS_I2C_MXC=y
CONFIG_FSL_USDHC=y
diff --git a/configs/omap35_logic_defconfig b/configs/omap35_logic_defconfig
index 23b2e50..29aa01f 100644
--- a/configs/omap35_logic_defconfig
+++ b/configs/omap35_logic_defconfig
@@ -6,14 +6,9 @@
CONFIG_SYS_MALLOC_F_LEN=0x3000
CONFIG_TI_COMMON_CMD_OPTIONS=y
# CONFIG_SPL_GPIO is not set
-CONFIG_NR_DRAM_BANKS=2
-CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y
-CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x4020ff00
CONFIG_DEFAULT_DEVICE_TREE="ti/omap/logicpd-torpedo-35xx-devkit"
-CONFIG_SPL_TEXT_BASE=0x40200000
CONFIG_TARGET_OMAP3_LOGIC=y
# CONFIG_SPL_OMAP3_ID_NAND is not set
-CONFIG_SYS_MONITOR_LEN=262144
CONFIG_SPL=y
CONFIG_LTO=y
CONFIG_ANDROID_BOOT_IMAGE=y
@@ -24,11 +19,10 @@
CONFIG_DEFAULT_FDT_FILE="logicpd-torpedo-35xx-devkit.dtb"
CONFIG_SYS_PBSIZE=1054
CONFIG_SYS_CONSOLE_INFO_QUIET=y
-CONFIG_SPL_MAX_SIZE=0xec00
CONFIG_SPL_SYS_MALLOC_SIMPLE=y
CONFIG_SPL_SYS_MALLOC=y
CONFIG_SPL_SYS_MALLOC_SIZE=0x800000
-# CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR is not set
+# CONFIG_SPL_SYS_MMCSD_RAW_MODE is not set
# CONFIG_SPL_FS_EXT4 is not set
# CONFIG_SPL_I2C is not set
CONFIG_SPL_MTD=y
diff --git a/configs/omap35_logic_somlv_defconfig b/configs/omap35_logic_somlv_defconfig
index a5f242f..4c60514 100644
--- a/configs/omap35_logic_somlv_defconfig
+++ b/configs/omap35_logic_somlv_defconfig
@@ -6,14 +6,9 @@
CONFIG_SYS_MALLOC_F_LEN=0x3000
CONFIG_TI_COMMON_CMD_OPTIONS=y
# CONFIG_SPL_GPIO is not set
-CONFIG_NR_DRAM_BANKS=2
-CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y
-CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x4020ff00
CONFIG_DEFAULT_DEVICE_TREE="ti/omap/logicpd-som-lv-35xx-devkit"
-CONFIG_SPL_TEXT_BASE=0x40200000
CONFIG_TARGET_OMAP3_LOGIC=y
# CONFIG_SPL_OMAP3_ID_NAND is not set
-CONFIG_SYS_MONITOR_LEN=262144
CONFIG_SPL=y
CONFIG_LTO=y
CONFIG_SYS_MONITOR_BASE=0x10000000
@@ -25,11 +20,10 @@
CONFIG_DEFAULT_FDT_FILE="logicpd-som-lv-35xx-devkit.dtb"
CONFIG_SYS_PBSIZE=1054
CONFIG_SYS_CONSOLE_INFO_QUIET=y
-CONFIG_SPL_MAX_SIZE=0xec00
CONFIG_SPL_SYS_MALLOC_SIMPLE=y
CONFIG_SPL_SYS_MALLOC=y
CONFIG_SPL_SYS_MALLOC_SIZE=0x800000
-# CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR is not set
+# CONFIG_SPL_SYS_MMCSD_RAW_MODE is not set
# CONFIG_SPL_FS_EXT4 is not set
# CONFIG_SPL_I2C is not set
CONFIG_SPL_MTD=y
diff --git a/configs/omap3_evm_defconfig b/configs/omap3_evm_defconfig
index 3c8d974..cc0b61a 100644
--- a/configs/omap3_evm_defconfig
+++ b/configs/omap3_evm_defconfig
@@ -3,13 +3,8 @@
# CONFIG_SPL_USE_ARCH_MEMSET is not set
CONFIG_ARCH_OMAP2PLUS=y
CONFIG_SYS_MALLOC_F_LEN=0x4000
-CONFIG_NR_DRAM_BANKS=2
-CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y
-CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x4020ff00
CONFIG_DEFAULT_DEVICE_TREE="omap3-evm"
-CONFIG_SPL_TEXT_BASE=0x40200000
CONFIG_TARGET_OMAP3_EVM=y
-CONFIG_SYS_MONITOR_LEN=262144
CONFIG_SPL_SYS_MALLOC_F_LEN=0x400
CONFIG_SPL=y
CONFIG_DISTRO_DEFAULTS=y
@@ -18,7 +13,6 @@
CONFIG_DEFAULT_FDT_FILE="omap3-evm.dtb"
CONFIG_SYS_PBSIZE=1053
CONFIG_SYS_CONSOLE_INFO_QUIET=y
-CONFIG_SPL_MAX_SIZE=0xec00
CONFIG_SPL_SYS_MALLOC_SIMPLE=y
CONFIG_SPL_SYS_MALLOC=y
CONFIG_SPL_SYS_MALLOC_SIZE=0x800000
diff --git a/configs/omap3_logic_defconfig b/configs/omap3_logic_defconfig
index d081d4e..e3791da 100644
--- a/configs/omap3_logic_defconfig
+++ b/configs/omap3_logic_defconfig
@@ -6,14 +6,9 @@
CONFIG_SYS_MALLOC_F_LEN=0x3000
CONFIG_TI_COMMON_CMD_OPTIONS=y
# CONFIG_SPL_GPIO is not set
-CONFIG_NR_DRAM_BANKS=2
-CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y
-CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x4020ff00
CONFIG_DEFAULT_DEVICE_TREE="ti/omap/logicpd-torpedo-37xx-devkit"
-CONFIG_SPL_TEXT_BASE=0x40200000
CONFIG_TARGET_OMAP3_LOGIC=y
# CONFIG_SPL_OMAP3_ID_NAND is not set
-CONFIG_SYS_MONITOR_LEN=262144
CONFIG_SPL=y
CONFIG_LTO=y
CONFIG_ANDROID_BOOT_IMAGE=y
@@ -23,11 +18,10 @@
CONFIG_PREBOOT="setenv preboot;saveenv;"
CONFIG_SYS_PBSIZE=1054
CONFIG_SYS_CONSOLE_INFO_QUIET=y
-CONFIG_SPL_MAX_SIZE=0xec00
CONFIG_SPL_SYS_MALLOC_SIMPLE=y
CONFIG_SPL_SYS_MALLOC=y
CONFIG_SPL_SYS_MALLOC_SIZE=0x800000
-# CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR is not set
+# CONFIG_SPL_SYS_MMCSD_RAW_MODE is not set
# CONFIG_SPL_FS_EXT4 is not set
# CONFIG_SPL_I2C is not set
CONFIG_SPL_MTD=y
diff --git a/configs/omap3_logic_somlv_defconfig b/configs/omap3_logic_somlv_defconfig
index 68e89d2..e9291d5 100644
--- a/configs/omap3_logic_somlv_defconfig
+++ b/configs/omap3_logic_somlv_defconfig
@@ -6,14 +6,9 @@
CONFIG_SYS_MALLOC_F_LEN=0x3000
CONFIG_TI_COMMON_CMD_OPTIONS=y
# CONFIG_SPL_GPIO is not set
-CONFIG_NR_DRAM_BANKS=2
-CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y
-CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x4020ff00
CONFIG_DEFAULT_DEVICE_TREE="ti/omap/logicpd-som-lv-37xx-devkit"
-CONFIG_SPL_TEXT_BASE=0x40200000
CONFIG_TARGET_OMAP3_LOGIC=y
# CONFIG_SPL_OMAP3_ID_NAND is not set
-CONFIG_SYS_MONITOR_LEN=262144
CONFIG_SPL=y
CONFIG_LTO=y
CONFIG_SYS_MONITOR_BASE=0x10000000
@@ -25,11 +20,10 @@
CONFIG_DEFAULT_FDT_FILE="logicpd-som-lv-37xx-devkit.dtb"
CONFIG_SYS_PBSIZE=1054
CONFIG_SYS_CONSOLE_INFO_QUIET=y
-CONFIG_SPL_MAX_SIZE=0xec00
CONFIG_SPL_SYS_MALLOC_SIMPLE=y
CONFIG_SPL_SYS_MALLOC=y
CONFIG_SPL_SYS_MALLOC_SIZE=0x800000
-# CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR is not set
+# CONFIG_SPL_SYS_MMCSD_RAW_MODE is not set
# CONFIG_SPL_FS_EXT4 is not set
# CONFIG_SPL_I2C is not set
CONFIG_SPL_MTD=y
diff --git a/configs/pcm051_rev3_defconfig b/configs/pcm051_rev3_defconfig
index 7846981..a4e467f 100644
--- a/configs/pcm051_rev3_defconfig
+++ b/configs/pcm051_rev3_defconfig
@@ -3,8 +3,6 @@
CONFIG_ARCH_OMAP2PLUS=y
CONFIG_SPL_LIBCOMMON_SUPPORT=y
CONFIG_SPL_LIBGENERIC_SUPPORT=y
-CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y
-CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x4030ff00
CONFIG_SF_DEFAULT_SPEED=24000000
CONFIG_DEFAULT_DEVICE_TREE="am335x-wega-rdk"
CONFIG_AM33XX=y
diff --git a/configs/phycore-am335x-r2-regor_defconfig b/configs/phycore-am335x-r2-regor_defconfig
index ac638c4..d5056cc 100644
--- a/configs/phycore-am335x-r2-regor_defconfig
+++ b/configs/phycore-am335x-r2-regor_defconfig
@@ -4,8 +4,6 @@
CONFIG_SPL_GPIO=y
CONFIG_SPL_LIBCOMMON_SUPPORT=y
CONFIG_SPL_LIBGENERIC_SUPPORT=y
-CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y
-CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x4030ff00
CONFIG_ENV_OFFSET=0xA0000
CONFIG_DEFAULT_DEVICE_TREE="am335x-regor-rdk"
CONFIG_AM33XX=y
diff --git a/configs/phycore-am335x-r2-wega_defconfig b/configs/phycore-am335x-r2-wega_defconfig
index 98c6217..5813d10 100644
--- a/configs/phycore-am335x-r2-wega_defconfig
+++ b/configs/phycore-am335x-r2-wega_defconfig
@@ -4,8 +4,6 @@
CONFIG_SPL_GPIO=y
CONFIG_SPL_LIBCOMMON_SUPPORT=y
CONFIG_SPL_LIBGENERIC_SUPPORT=y
-CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y
-CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x4030ff00
CONFIG_ENV_OFFSET=0xA0000
CONFIG_DEFAULT_DEVICE_TREE="am335x-wega-rdk"
CONFIG_AM33XX=y
diff --git a/configs/phycore-imx8mm_defconfig b/configs/phycore-imx8mm_defconfig
index 6748e6f..61a3ead 100644
--- a/configs/phycore-imx8mm_defconfig
+++ b/configs/phycore-imx8mm_defconfig
@@ -40,6 +40,7 @@
CONFIG_SPL_HAS_CUSTOM_MALLOC_START=y
CONFIG_SPL_CUSTOM_SYS_MALLOC_ADDR=0x42200000
CONFIG_SPL_SYS_MALLOC_SIZE=0x80000
+CONFIG_SPL_SYS_MMCSD_RAW_MODE=y
CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR=y
CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x300
CONFIG_SPL_I2C=y
diff --git a/configs/phycore-imx8mp_defconfig b/configs/phycore-imx8mp_defconfig
index 63f8a80..802d956 100644
--- a/configs/phycore-imx8mp_defconfig
+++ b/configs/phycore-imx8mp_defconfig
@@ -24,6 +24,7 @@
CONFIG_SPL_BSS_MAX_SIZE=0x400
CONFIG_SPL=y
CONFIG_ENV_OFFSET_REDUND=0x3e0000
+CONFIG_IMX_BOOTAUX=y
CONFIG_SPL_IMX_ROMAPI_LOADADDR=0x48000000
CONFIG_SYS_LOAD_ADDR=0x40480000
CONFIG_FIT=y
@@ -44,6 +45,7 @@
CONFIG_SPL_HAS_CUSTOM_MALLOC_START=y
CONFIG_SPL_CUSTOM_SYS_MALLOC_ADDR=0x42200000
CONFIG_SPL_SYS_MALLOC_SIZE=0x80000
+CONFIG_SPL_SYS_MMCSD_RAW_MODE=y
CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR=y
CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x300
# CONFIG_SPL_CRYPTO is not set
diff --git a/configs/phycore_am62x_a53_defconfig b/configs/phycore_am62x_a53_defconfig
index 39161b7..d8b129f 100644
--- a/configs/phycore_am62x_a53_defconfig
+++ b/configs/phycore_am62x_a53_defconfig
@@ -47,6 +47,7 @@
CONFIG_SPL_SYS_REPORT_STACK_F_USAGE=y
CONFIG_SPL_BOARD_INIT=y
CONFIG_SPL_SYS_MALLOC_SIMPLE=y
+CONFIG_SPL_SYS_MMCSD_RAW_MODE=y
CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR=y
CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x1400
CONFIG_SPL_ENV_SUPPORT=y
diff --git a/configs/phycore_am62x_r5_defconfig b/configs/phycore_am62x_r5_defconfig
index b7d0273..7fc3abf 100644
--- a/configs/phycore_am62x_r5_defconfig
+++ b/configs/phycore_am62x_r5_defconfig
@@ -48,6 +48,7 @@
CONFIG_SPL_CUSTOM_SYS_MALLOC_ADDR=0x84000000
CONFIG_SPL_SYS_MALLOC_SIZE=0x1000000
CONFIG_SPL_EARLY_BSS=y
+CONFIG_SPL_SYS_MMCSD_RAW_MODE=y
CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR=y
CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x400
CONFIG_SPL_I2C=y
diff --git a/configs/phycore_am64x_a53_defconfig b/configs/phycore_am64x_a53_defconfig
index 1af72e8..5cf24b9 100644
--- a/configs/phycore_am64x_a53_defconfig
+++ b/configs/phycore_am64x_a53_defconfig
@@ -45,6 +45,7 @@
CONFIG_SPL_SYS_MALLOC_SIMPLE=y
CONFIG_SPL_SYS_MALLOC=y
CONFIG_SPL_SYS_MALLOC_SIZE=0x800000
+CONFIG_SPL_SYS_MMCSD_RAW_MODE=y
CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR=y
CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x1400
CONFIG_SPL_DMA=y
diff --git a/configs/phycore_am64x_r5_defconfig b/configs/phycore_am64x_r5_defconfig
index a0d7824..72d10f7 100644
--- a/configs/phycore_am64x_r5_defconfig
+++ b/configs/phycore_am64x_r5_defconfig
@@ -49,6 +49,7 @@
CONFIG_SPL_CUSTOM_SYS_MALLOC_ADDR=0x84000000
CONFIG_SPL_SYS_MALLOC_SIZE=0x1000000
CONFIG_SPL_EARLY_BSS=y
+CONFIG_SPL_SYS_MMCSD_RAW_MODE=y
CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR=y
CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x400
CONFIG_SPL_DMA=y
diff --git a/configs/pico-imx8mq_defconfig b/configs/pico-imx8mq_defconfig
index cf91eb5..ef876ab 100644
--- a/configs/pico-imx8mq_defconfig
+++ b/configs/pico-imx8mq_defconfig
@@ -43,6 +43,7 @@
CONFIG_SPL_HAS_CUSTOM_MALLOC_START=y
CONFIG_SPL_CUSTOM_SYS_MALLOC_ADDR=0x42200000
CONFIG_SPL_SYS_MALLOC_SIZE=0x80000
+CONFIG_SPL_SYS_MMCSD_RAW_MODE=y
CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR=y
CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x300
CONFIG_SPL_I2C=y
diff --git a/configs/pxm2_defconfig b/configs/pxm2_defconfig
index c2f8693..30946b8 100644
--- a/configs/pxm2_defconfig
+++ b/configs/pxm2_defconfig
@@ -6,8 +6,6 @@
CONFIG_SPL_LIBCOMMON_SUPPORT=y
CONFIG_SPL_LIBGENERIC_SUPPORT=y
CONFIG_NR_DRAM_BANKS=1
-CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y
-CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x4030ff00
CONFIG_ENV_SIZE=0x2000
CONFIG_SPL_DM_SPI=y
CONFIG_DEFAULT_DEVICE_TREE="am335x-pxm50"
diff --git a/configs/rut_defconfig b/configs/rut_defconfig
index 7e78f1d..2bcbdd6 100644
--- a/configs/rut_defconfig
+++ b/configs/rut_defconfig
@@ -6,8 +6,6 @@
CONFIG_SPL_LIBCOMMON_SUPPORT=y
CONFIG_SPL_LIBGENERIC_SUPPORT=y
CONFIG_NR_DRAM_BANKS=1
-CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y
-CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x4030ff00
CONFIG_ENV_SIZE=0x2000
CONFIG_SPL_DM_SPI=y
CONFIG_DEFAULT_DEVICE_TREE="am335x-rut"
@@ -90,7 +88,7 @@
CONFIG_BOOTCOUNT_ENV=y
CONFIG_DFU_NAND=y
CONFIG_SYS_DFU_DATA_BUF_SIZE=0x100000
-CONFIG_SYS_I2C_LEGACY=y
+CONFIG_DM_I2C=y
CONFIG_SPL_SYS_I2C_LEGACY=y
# CONFIG_SPL_DM_MMC is not set
CONFIG_MMC_OMAP_HS=y
diff --git a/configs/sama5d27_wlsom1_ek_mmc_defconfig b/configs/sama5d27_wlsom1_ek_mmc_defconfig
index 89a5bcd..25213af 100644
--- a/configs/sama5d27_wlsom1_ek_mmc_defconfig
+++ b/configs/sama5d27_wlsom1_ek_mmc_defconfig
@@ -48,7 +48,7 @@
CONFIG_SPL_SYS_MALLOC=y
CONFIG_SPL_SYS_MALLOC_SIZE=0x80000
CONFIG_SPL_DISPLAY_PRINT=y
-# CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR is not set
+# CONFIG_SPL_SYS_MMCSD_RAW_MODE is not set
CONFIG_SPL_AT91_MCK_BYPASS=y
CONFIG_HUSH_PARSER=y
CONFIG_CMD_BOOTZ=y
diff --git a/configs/sama5d27_wlsom1_ek_qspiflash_defconfig b/configs/sama5d27_wlsom1_ek_qspiflash_defconfig
index a070445..5502858 100644
--- a/configs/sama5d27_wlsom1_ek_qspiflash_defconfig
+++ b/configs/sama5d27_wlsom1_ek_qspiflash_defconfig
@@ -48,7 +48,7 @@
CONFIG_SPL_SYS_MALLOC=y
CONFIG_SPL_SYS_MALLOC_SIZE=0x80000
CONFIG_SPL_DISPLAY_PRINT=y
-# CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR is not set
+# CONFIG_SPL_SYS_MMCSD_RAW_MODE is not set
CONFIG_SPL_DM_SPI_FLASH=y
CONFIG_SPL_SPI_LOAD=y
CONFIG_SYS_SPI_U_BOOT_OFFS=0x40000
diff --git a/configs/sama5d2_icp_mmc_defconfig b/configs/sama5d2_icp_mmc_defconfig
index 6b9fa27..98b931c 100644
--- a/configs/sama5d2_icp_mmc_defconfig
+++ b/configs/sama5d2_icp_mmc_defconfig
@@ -49,7 +49,7 @@
CONFIG_SPL_SYS_MALLOC=y
CONFIG_SPL_SYS_MALLOC_SIZE=0x80000
CONFIG_SPL_DISPLAY_PRINT=y
-# CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR is not set
+# CONFIG_SPL_SYS_MMCSD_RAW_MODE is not set
CONFIG_SPL_RAM_SUPPORT=y
CONFIG_SPL_RAM_DEVICE=y
CONFIG_SPL_AT91_MCK_BYPASS=y
diff --git a/configs/sandbox_defconfig b/configs/sandbox_defconfig
index dc5fcdb..a50fbce 100644
--- a/configs/sandbox_defconfig
+++ b/configs/sandbox_defconfig
@@ -16,6 +16,7 @@
CONFIG_FIT_CIPHER=y
CONFIG_FIT_VERBOSE=y
CONFIG_BOOTMETH_ANDROID=y
+CONFIG_UPL=y
CONFIG_LEGACY_IMAGE_FORMAT=y
CONFIG_MEASURED_BOOT=y
CONFIG_BOOTSTAGE=y
@@ -39,6 +40,7 @@
CONFIG_LOG=y
CONFIG_LOG_MAX_LEVEL=9
CONFIG_LOG_DEFAULT_LEVEL=6
+CONFIG_LOGF_FUNC=y
CONFIG_DISPLAY_BOARDINFO_LATE=y
CONFIG_STACKPROTECTOR=y
CONFIG_CMD_CPU=y
diff --git a/configs/sandbox_noinst_defconfig b/configs/sandbox_noinst_defconfig
index f372301..bfd95e2 100644
--- a/configs/sandbox_noinst_defconfig
+++ b/configs/sandbox_noinst_defconfig
@@ -43,6 +43,7 @@
CONFIG_SPL_HAS_CUSTOM_MALLOC_START=y
CONFIG_SPL_CUSTOM_SYS_MALLOC_ADDR=0xa000000
CONFIG_SPL_SYS_MALLOC_SIZE=0x4000000
+CONFIG_SPL_SYS_MMCSD_RAW_MODE=y
CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR=y
CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x0
CONFIG_SPL_ENV_SUPPORT=y
diff --git a/configs/sandbox_vpl_defconfig b/configs/sandbox_vpl_defconfig
index 72483d8..96e9211 100644
--- a/configs/sandbox_vpl_defconfig
+++ b/configs/sandbox_vpl_defconfig
@@ -27,6 +27,9 @@
CONFIG_FIT_VERBOSE=y
CONFIG_FIT_BEST_MATCH=y
CONFIG_SPL_LOAD_FIT=y
+CONFIG_UPL=y
+CONFIG_UPL_IN=y
+CONFIG_SPL_UPL_OUT=y
CONFIG_BOOTSTAGE=y
CONFIG_BOOTSTAGE_REPORT=y
CONFIG_BOOTSTAGE_FDT=y
@@ -35,6 +38,7 @@
CONFIG_CONSOLE_RECORD=y
CONFIG_CONSOLE_RECORD_OUT_SIZE=0x1000
CONFIG_DISPLAY_BOARDINFO_LATE=y
+CONFIG_BLOBLIST_SIZE=0x5000
CONFIG_SPL_NO_BSS_LIMIT=y
CONFIG_HANDOFF=y
CONFIG_SPL_BOARD_INIT=y
diff --git a/configs/sniper_defconfig b/configs/sniper_defconfig
index 0243b15..bc4ff09 100644
--- a/configs/sniper_defconfig
+++ b/configs/sniper_defconfig
@@ -1,43 +1,33 @@
CONFIG_ARM=y
-# CONFIG_SYS_THUMB_BUILD is not set
CONFIG_ARCH_OMAP2PLUS=y
-CONFIG_TEXT_BASE=0x80100000
-CONFIG_SYS_MALLOC_LEN=0x120000
-CONFIG_SYS_MALLOC_F_LEN=0x400
-CONFIG_NR_DRAM_BANKS=2
-CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y
-CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x4020ff00
-CONFIG_SPL_TEXT_BASE=0x40200000
+CONFIG_SYS_MALLOC_F_LEN=0x4000
+CONFIG_DEFAULT_DEVICE_TREE="ti/omap/omap3-sniper"
CONFIG_TARGET_SNIPER=y
-CONFIG_SPL_STACK=0x4020fffc
-CONFIG_SPL_BSS_START_ADDR=0x80000000
+CONFIG_SPL_SYS_MALLOC_F_LEN=0x400
CONFIG_SPL=y
CONFIG_DISTRO_DEFAULTS=y
CONFIG_BOOTCOMMAND="setenv boot_mmc_part ${kernel_mmc_part}; if test reboot-${reboot-mode} = reboot-r; then echo recovery; setenv boot_mmc_part ${recovery_mmc_part}; fi; if test reboot-${reboot-mode} = reboot-b; then echo fastboot; fastboot 0; fi; part start mmc ${boot_mmc_dev} ${boot_mmc_part} boot_mmc_start; part size mmc ${boot_mmc_dev} ${boot_mmc_part} boot_mmc_size; mmc dev ${boot_mmc_dev}; mmc read ${kernel_addr_r} ${boot_mmc_start} ${boot_mmc_size} && bootm ${kernel_addr_r};"
-CONFIG_SYS_CBSIZE=512
-CONFIG_SYS_PBSIZE=538
CONFIG_SYS_CONSOLE_IS_IN_ENV=y
-CONFIG_SPL_MAX_SIZE=0xec00
-# CONFIG_SPL_SHARES_INIT_SP_ADDR is not set
+CONFIG_SPL_BOARD_INIT=y
+CONFIG_SPL_SYS_MALLOC_SIMPLE=y
CONFIG_SPL_SYS_MALLOC=y
-CONFIG_SPL_HAS_CUSTOM_MALLOC_START=y
-CONFIG_SPL_CUSTOM_SYS_MALLOC_ADDR=0x80208000
-# CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR is not set
+CONFIG_SPL_SYS_MALLOC_SIZE=0x800000
+# CONFIG_SPL_SYS_MMCSD_RAW_MODE is not set
CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_PARTITION=y
CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_PARTITION=2
# CONFIG_SPL_FS_EXT4 is not set
# CONFIG_SPL_NAND_SUPPORT is not set
-CONFIG_SYS_PROMPT="sniper # "
CONFIG_CMD_GPIO=y
CONFIG_CMD_I2C=y
CONFIG_CMD_MMC=y
# CONFIG_CMD_SETEXPR is not set
+CONFIG_OF_CONTROL=y
+CONFIG_SPL_OF_CONTROL=y
+CONFIG_OF_UPSTREAM=y
CONFIG_ENV_OVERWRITE=y
CONFIG_SYS_RELOC_GD_ENV_ADDR=y
-CONFIG_SYS_I2C_LEGACY=y
-CONFIG_SPL_SYS_I2C_LEGACY=y
-CONFIG_SYS_I2C_SPEED=400000
+CONFIG_SPL_DM=y
+CONFIG_DM_I2C=y
+CONFIG_I2C_SET_DEFAULT_BUS_NUM=y
CONFIG_TWL4030_INPUT=y
CONFIG_MMC_OMAP_HS=y
-CONFIG_CONS_INDEX=3
-CONFIG_OF_LIBFDT=y
diff --git a/configs/socfpga_secu1_defconfig b/configs/socfpga_secu1_defconfig
index b8d9c84..a023e45 100644
--- a/configs/socfpga_secu1_defconfig
+++ b/configs/socfpga_secu1_defconfig
@@ -42,7 +42,7 @@
CONFIG_SPL_NO_BSS_LIMIT=y
CONFIG_SPL_LEGACY_IMAGE_CRC_CHECK=y
# CONFIG_SPL_SHARES_INIT_SP_ADDR is not set
-# CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR is not set
+# CONFIG_SPL_SYS_MMCSD_RAW_MODE is not set
CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_PARTITION=0x1
# CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_PARTITION_TYPE is not set
CONFIG_SPL_MTD=y
diff --git a/configs/verdin-am62_a53_defconfig b/configs/verdin-am62_a53_defconfig
index 25f5f5e..c5652e9 100644
--- a/configs/verdin-am62_a53_defconfig
+++ b/configs/verdin-am62_a53_defconfig
@@ -51,6 +51,7 @@
CONFIG_SPL_SYS_REPORT_STACK_F_USAGE=y
CONFIG_SPL_BOARD_INIT=y
CONFIG_SPL_SYS_MALLOC_SIMPLE=y
+CONFIG_SPL_SYS_MMCSD_RAW_MODE=y
CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR=y
CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x1400
CONFIG_SPL_DMA=y
diff --git a/configs/verdin-am62_r5_defconfig b/configs/verdin-am62_r5_defconfig
index e39ee2a..bd9ecd9 100644
--- a/configs/verdin-am62_r5_defconfig
+++ b/configs/verdin-am62_r5_defconfig
@@ -41,6 +41,7 @@
CONFIG_SPL_CUSTOM_SYS_MALLOC_ADDR=0x84000000
CONFIG_SPL_SYS_MALLOC_SIZE=0x1000000
CONFIG_SPL_EARLY_BSS=y
+CONFIG_SPL_SYS_MMCSD_RAW_MODE=y
CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR=y
CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x400
CONFIG_SPL_ENV_SUPPORT=y
diff --git a/configs/verdin-imx8mm_defconfig b/configs/verdin-imx8mm_defconfig
index ef7f3b1..9ca2055 100644
--- a/configs/verdin-imx8mm_defconfig
+++ b/configs/verdin-imx8mm_defconfig
@@ -47,6 +47,7 @@
CONFIG_SPL_HAS_CUSTOM_MALLOC_START=y
CONFIG_SPL_CUSTOM_SYS_MALLOC_ADDR=0x42200000
CONFIG_SPL_SYS_MALLOC_SIZE=0x80000
+CONFIG_SPL_SYS_MMCSD_RAW_MODE=y
CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR=y
CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x300
CONFIG_SPL_I2C=y
diff --git a/configs/verdin-imx8mp_defconfig b/configs/verdin-imx8mp_defconfig
index fca91f7..c74398f 100644
--- a/configs/verdin-imx8mp_defconfig
+++ b/configs/verdin-imx8mp_defconfig
@@ -60,6 +60,7 @@
CONFIG_SPL_HAS_CUSTOM_MALLOC_START=y
CONFIG_SPL_CUSTOM_SYS_MALLOC_ADDR=0x42200000
CONFIG_SPL_SYS_MALLOC_SIZE=0x80000
+CONFIG_SPL_SYS_MMCSD_RAW_MODE=y
CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR=y
CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x300
CONFIG_SPL_I2C=y
diff --git a/configs/vf610twr_defconfig b/configs/vf610twr_defconfig
index af889ec..7713454 100644
--- a/configs/vf610twr_defconfig
+++ b/configs/vf610twr_defconfig
@@ -47,7 +47,7 @@
CONFIG_ENV_IS_IN_MMC=y
CONFIG_SYS_RELOC_GD_ENV_ADDR=y
CONFIG_VYBRID_GPIO=y
-CONFIG_SYS_I2C_LEGACY=y
+CONFIG_DM_I2C=y
CONFIG_SYS_I2C_MXC=y
CONFIG_FSL_ESDHC_IMX=y
CONFIG_MTD=y
diff --git a/configs/vf610twr_nand_defconfig b/configs/vf610twr_nand_defconfig
index c50afc4..2cef898 100644
--- a/configs/vf610twr_nand_defconfig
+++ b/configs/vf610twr_nand_defconfig
@@ -48,7 +48,7 @@
CONFIG_ENV_RANGE=0x80000
CONFIG_SYS_RELOC_GD_ENV_ADDR=y
CONFIG_VYBRID_GPIO=y
-CONFIG_SYS_I2C_LEGACY=y
+CONFIG_DM_I2C=y
CONFIG_SYS_I2C_MXC=y
CONFIG_FSL_ESDHC_IMX=y
CONFIG_MTD=y
diff --git a/configs/vining_2000_defconfig b/configs/vining_2000_defconfig
index c39597c..e5c9c28 100644
--- a/configs/vining_2000_defconfig
+++ b/configs/vining_2000_defconfig
@@ -70,7 +70,7 @@
CONFIG_USE_ETHPRIME=y
CONFIG_ETHPRIME="FEC"
CONFIG_BOUNCE_BUFFER=y
-CONFIG_SYS_I2C_LEGACY=y
+CONFIG_DM_I2C=y
CONFIG_SPL_SYS_I2C_LEGACY=y
CONFIG_SYS_I2C_MXC=y
CONFIG_SUPPORT_EMMC_RPMB=y
diff --git a/configs/work_92105_defconfig b/configs/work_92105_defconfig
index 4b73e15..e7da0de 100644
--- a/configs/work_92105_defconfig
+++ b/configs/work_92105_defconfig
@@ -47,7 +47,6 @@
CONFIG_CMD_DHCP=y
CONFIG_CMD_MII=y
CONFIG_CMD_PING=y
-CONFIG_CMD_DATE=y
CONFIG_DOS_PARTITION=y
CONFIG_ENV_IS_IN_NAND=y
CONFIG_SYS_REDUNDAND_ENVIRONMENT=y
diff --git a/doc/I2C_Edge_Conditions b/doc/I2C_Edge_Conditions
index f4a9968..9ccb21c 100644
--- a/doc/I2C_Edge_Conditions
+++ b/doc/I2C_Edge_Conditions
@@ -31,12 +31,10 @@
!!!THIS IS AN UNDOCUMENTED I2C BUS BUG, NOT A AMCC 4xx BUG!!!
This reset edge condition could possibly be present in every I2C
-controller and device available. For boards where a I2C bus reset
-function can be implemented a i2c_init_board() function should be
-provided and enabled by #define'ing CONFIG_SYS_I2C_INIT_BOARD in your
-board's config file. Note that this is NOT necessary when using the
-bit-banging I2C driver (common/soft_i2c.c) as this already includes
-the I2C bus reset sequence.
+controller and device available.
+
+Note that this problem does not happen when using the bit-banging I2C driver
+(common/soft_i2c.c) as this already includes the I2C bus reset sequence.
Many thanks to Bill Hunter for finding this serious BUG.
diff --git a/doc/board/samsung/e850-96.rst b/doc/board/samsung/e850-96.rst
index 0cb9547..0a7b6fc 100644
--- a/doc/board/samsung/e850-96.rst
+++ b/doc/board/samsung/e850-96.rst
@@ -47,12 +47,13 @@
---------------
.. warning::
- At the moment both eMMC and USB features are not enabled in U-Boot. Flashing
+ At the moment USB is not enabled in U-Boot for this board. Although eMMC is
+ enabled, you won't be able to flash images over USB (fastboot). So flashing
U-Boot binary **WILL** effectively brick your board. The ``dltool`` [8]_ can
be used then to perform USB boot and flash LittleKernel bootloader binary [7]_
to unbrick and revive the board. Flashing U-Boot binary might be helpful for
developers or anybody who want to check current state of U-Boot enablement on
- E850-96 (which is mostly serial console and related blocks).
+ E850-96 (which is mostly serial console, eMMC and related blocks).
Build U-Boot binary from source code (using AArch64 baremetal GCC toolchain):
diff --git a/doc/develop/commands.rst b/doc/develop/commands.rst
index 5ad4e59..77a7a4d 100644
--- a/doc/develop/commands.rst
+++ b/doc/develop/commands.rst
@@ -197,7 +197,6 @@
ctx.current = buf;
ut_assertok(acpi_fill_ssdt(&ctx));
- console_record_reset();
run_command("acpi items", 0);
ut_assert_nextline("dev 'acpi-test', type 1, size 2");
ut_assert_nextline("dev 'acpi-test2', type 1, size 2");
@@ -205,13 +204,11 @@
ctx.current = buf;
ut_assertok(acpi_inject_dsdt(&ctx));
- console_record_reset();
run_command("acpi items", 0);
ut_assert_nextline("dev 'acpi-test', type 2, size 2");
ut_assert_nextline("dev 'acpi-test2', type 2, size 2");
ut_assert_console_end();
- console_record_reset();
run_command("acpi items -d", 0);
ut_assert_nextline("dev 'acpi-test', type 2, size 2");
ut_assert_nextlines_are_dump(2);
@@ -223,4 +220,8 @@
return 0;
}
- DM_TEST(dm_test_acpi_cmd_items, UT_TESTF_SCAN_PDATA | UT_TESTF_SCAN_FDT);
+ DM_TEST(dm_test_acpi_cmd_items, UTF_SCAN_PDATA | UTF_SCAN_FDT | UTF_CONSOLE);
+
+Note that it is not necessary to call console_record_reset() unless you are
+trying to drop some unchecked output. Consider using ut_check_skip_to_line()
+instead.
diff --git a/doc/develop/global_data.rst b/doc/develop/global_data.rst
index d143f27..2863154 100644
--- a/doc/develop/global_data.rst
+++ b/doc/develop/global_data.rst
@@ -51,6 +51,31 @@
whenever U-Boot is reentered. This is also relevant for the implementation of
function tracing. For setting the value of gd function set_gd() can be used.
+Guidelines
+----------
+
+The global_data structure is placed in some memory which is available very early
+after boot to allow for a minimum set of global variables during system
+initialisation (until the memory controller is set up and RAM can be used). It
+is the primary data structure passed from pre-relocation U-Boot to
+post-relocation, i.e. ``from board_init_f()`` ``to board_init_r()``.
+
+The global_data struct exists for the lifetime of U-Boot. Since the struct is
+used by all architectures, fields added should be useful for most architectures.
+Fields which are only needed on one or two architectures can be placed in the
+architecture-specific ``struct arch_global_data``.
+
+In any case the struct should be kept small, since it uses precious SRAM on
+many boards.
+
+SPL also uses global data, as well as U-Boot proper, so take care to avoid
+adding fields to SPL which are not actually used by SPL. You can create
+access functions or macros in the header file to avoid filling the C code with
+#ifdefs.
+
+A flags word is available, which provides a convenient means to track the state
+of various initialisation phases within U-Boot.
+
Global data structure
---------------------
diff --git a/doc/README.generic-board b/doc/develop/historical/generic_board.rst
similarity index 95%
rename from doc/README.generic-board
rename to doc/develop/historical/generic_board.rst
index bc35179..12550a1 100644
--- a/doc/README.generic-board
+++ b/doc/develop/historical/generic_board.rst
@@ -1,10 +1,9 @@
-# SPDX-License-Identifier: GPL-2.0+
-#
-# (C) Copyright 2014 Google, Inc
-# Simon Glass <sjg@chromium.org>
+.. SPDX-License-Identifier: GPL-2.0+
+.. (C) Copyright 2014 Google, Inc
+.. sectionauthor:: Simon Glass <sjg@chromium.org>
-Background
-----------
+Generic board
+-------------
U-Boot traditionally had a board.c file for each architecture. This introduced
quite a lot of duplication, with each architecture tending to do
@@ -16,7 +15,7 @@
What has changed?
------------------
+~~~~~~~~~~~~~~~~~
The main change is that the arch/<arch>/lib/board.c file is removed in
favour of common/board_f.c (for pre-relocation init) and common/board_r.c
@@ -28,7 +27,7 @@
Further Background
-------------------
+~~~~~~~~~~~~~~~~~~
The full text of the original generic board series is reproduced below.
@@ -132,4 +131,6 @@
Simon Glass, sjg@chromium.org
March 2014
+
Updated after final removal, May 2016
+
diff --git a/doc/develop/historical/index.rst b/doc/develop/historical/index.rst
new file mode 100644
index 0000000..e4462f5
--- /dev/null
+++ b/doc/develop/historical/index.rst
@@ -0,0 +1,12 @@
+.. SPDX-License-Identifier: GPL-2.0+
+
+Historical Documents
+====================
+
+This section provides documentation about major changes in U-Boot over the
+years.
+
+.. toctree::
+ :maxdepth: 1
+
+ generic_board
diff --git a/doc/develop/index.rst b/doc/develop/index.rst
index c0107a7..0d0e60a 100644
--- a/doc/develop/index.rst
+++ b/doc/develop/index.rst
@@ -99,3 +99,11 @@
:maxdepth: 1
python_cq
+
+Historical documentation
+------------------------
+
+.. toctree::
+ :maxdepth: 2
+
+ historical/index
diff --git a/doc/develop/release_cycle.rst b/doc/develop/release_cycle.rst
index 776af60..7286375 100644
--- a/doc/develop/release_cycle.rst
+++ b/doc/develop/release_cycle.rst
@@ -71,7 +71,7 @@
* U-Boot v2024.10-rc2 was released on Mon 05 August 2024.
-.. * U-Boot v2024.10-rc3 was released on Mon 19 August 2024.
+* U-Boot v2024.10-rc3 was released on Mon 19 August 2024.
.. * U-Boot v2024.10-rc4 was released on Mon 02 September 2024.
diff --git a/doc/develop/tests_writing.rst b/doc/develop/tests_writing.rst
index 44b544f..a328ebf 100644
--- a/doc/develop/tests_writing.rst
+++ b/doc/develop/tests_writing.rst
@@ -81,7 +81,7 @@
perform some operations, with a 'checker' C unit test doing the checks
afterwards. This can be achieved with these steps:
-- Add the `UT_TESTF_MANUAL` flag to the checker test so that the `ut` command
+- Add the `UTF_MANUAL` flag to the checker test so that the `ut` command
does not run it by default
- Add a `_norun` suffix to the name so that pytest knows to skip it too
@@ -95,7 +95,7 @@
# Run the checker to make sure that everything worked
ut -f bootstd vbe_test_fixup_norun
-Note that apart from the `UT_TESTF_MANUAL` flag, the code in a 'manual' C test
+Note that apart from the `UTF_MANUAL` flag, the code in a 'manual' C test
is just like any other C test. It still uses ut_assert...() and other such
constructs, in this case to check that the expected things happened in the
Python test.
@@ -151,7 +151,6 @@
buf[0x31] = 0x12;
buf[0xff] = 0x12;
buf[0x100] = 0x12;
- ut_assertok(console_record_reset_enable());
run_command("ms.b 1 ff 12", 0);
ut_assert_nextline("00000030: 00 12 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ................");
ut_assert_nextline("--");
@@ -167,7 +166,7 @@
return 0;
}
- MEM_TEST(mem_test_ms_b, UT_TESTF_CONSOLE_REC);
+ MEM_TEST(mem_test_ms_b, UTF_CONSOLE);
This runs the command directly in U-Boot, then checks the console output, also
directly in U-Boot. If run by itself this takes 100ms. For 1000 runs it takes
@@ -226,14 +225,17 @@
return 0;
}
- DM_TEST(dm_test_uclassname_what, UT_TESTF_SCAN_FDT);
+ DM_TEST(dm_test_uclassname_what, UTF_SCAN_FDT);
+
+Note that the convention is to NOT add a blank line before the macro, so that
+the function it relates to is more obvious.
Replace 'uclassname' with the name of your uclass, if applicable. Replace 'what'
with what you are testing.
The flags for DM_TEST() are defined in test/test.h and you typically want
-UT_TESTF_SCAN_FDT so that the devicetree is scanned and all devices are bound
-and ready for use. The DM_TEST macro adds UT_TESTF_DM automatically so that
+UTF_SCAN_FDT so that the devicetree is scanned and all devices are bound
+and ready for use. The DM_TEST macro adds UTF_DM automatically so that
the test runner knows it is a driver model test.
Driver model tests are special in that the entire driver model state is
@@ -263,7 +265,7 @@
return 0;
}
- MEM_TEST(mem_test_ms_new_thing, UT_TESTF_CONSOLE_REC);
+ MEM_TEST(mem_test_ms_new_thing, UTF_CONSOLE);
Note that the MEM_TEST() macros is defined at the top of the file.
diff --git a/doc/device-tree-bindings/exynos/dwmmc.txt b/doc/device-tree-bindings/exynos/dwmmc.txt
index 694d195..d90792b 100644
--- a/doc/device-tree-bindings/exynos/dwmmc.txt
+++ b/doc/device-tree-bindings/exynos/dwmmc.txt
@@ -12,7 +12,9 @@
Required SoC Specific Properties:
- compatible: should be
- - samsung,exynos-dwmmc: for exynos platforms
+ - samsung,exynos4412-dw-mshc: for Exynos4 platforms
+ - samsung,exynos-dwmmc: for Exynos5 platforms
+ - samsung,exynos7-dw-mshc-smu: for Exynos7 platforms (with SMU block)
- reg: physical base address of the controller and length of memory mapped
region.
@@ -23,32 +25,38 @@
- #address-cells: should be 1.
- #size-cells: should be 0.
-- samsung,bus-width: The width of the bus used to interface the devices
+- bus-width: The width of the bus used to interface the devices
supported by DWC_mobile_storage (SD-MMC/EMMC/SDIO).
. Typically the bus width is 4 or 8.
-- samsung,timing: The timing values to be written into the
- Drv/sample clock selection register of corresponding channel.
- . It is comprised of 3 values corresponding to the 3 fileds
- 'SelClk_sample', 'SelClk_drv' and 'DIVRATIO' of CLKSEL register.
- . SelClk_sample: Select sample clock among 8 shifted clocks.
- . SelClk_drv: Select drv clock among 8 shifted clocks.
- . DIVRATIO: Clock Divide ratio select.
- . The above 3 values are used by the clock phase shifter.
+- samsung,dw-mshc-ciu-div: The divider value for the card interface unit (ciu)
+ clock (0..7).
+- samsung,dw-mshc-sdr-timing: The timing values for single data rate (SDR) mode
+ operation.
+ . First value is CIU clock phase shift value for TX mode (0..7).
+ . Second value is CIU clock phase shift value for RX mode (0..7).
+- samsung,dw-mshc-ddr-timing: The timing values for double data rate (DDR) mode
+ operation. If missing, values from samsung,dw-mshc-sdr-timing are used.
+ . First value is CIU clock phase shift value for TX mode (0..7).
+ . Second value is CIU clock phase shift value for RX mode (0..7).
Example:
mmc@12200000 {
- samsung,bus-width = <8>;
- samsung,timing = <1 3 3>;
- samsung,removable = <1>;
-}
+ bus-width = <8>;
+ non-removable;
+ samsung,dw-mshc-ciu-div = <3>;
+ samsung,dw-mshc-sdr-timing = <1 3>;
+ samsung,dw-mshc-ddr-timing = <0 2>;
+};
+
In the above example,
. The bus width is 8
- . Timing is comprised of 3 values as explained below
+ . Divider value for CLKSEL register is 3. The CIU clock rate will be
+ calculated as SDCLKIN / (3 + 1).
+ . SDR and DDR timings are comprised of 2 values as explained below
1 - SelClk_sample
3 - SelClk_drv
- 3 - DIVRATIO
- . The 'removable' flag indicates whether the the particilar device
+ . The 'non-removable' flag indicates whether the particular device
cannot be removed (always present) or it is a removable device.
- 1 - Indicates that the device is removable.
- 0 - Indicates that the device cannot be removed.
+ Flag is present - Indicates that the device cannot be removed.
+ Flag is not present - Indicates that the device is removable.
diff --git a/doc/device-tree-bindings/spi/soft-spi.txt b/doc/device-tree-bindings/spi/soft-spi.txt
index bdf7e86..77b01b2 100644
--- a/doc/device-tree-bindings/spi/soft-spi.txt
+++ b/doc/device-tree-bindings/spi/soft-spi.txt
@@ -8,14 +8,15 @@
Mandatory properties:
compatible: "spi-gpio"
-cs-gpios: GPIOs to use for SPI chip select (output)
+cs-gpios: GPIOs to use for SPI chip select (output), not required if num-chipselects = <0>
sck-gpios: GPIO to use for SPI clock (output)
And at least one of:
mosi-gpios: GPIO to use for SPI MOSI line (output)
miso-gpios: GPIO to use for SPI MISO line (input)
-Optional propertie:
+Optional properties:
spi-delay-us: Number of microseconds of delay between each CS transition
+num-chipselects: Number of chipselect lines
The GPIOs should be specified as required by the GPIO controller referenced.
The first cell holds the phandle of the controller and the second cell
diff --git a/doc/usage/cmd/env.rst b/doc/usage/cmd/env.rst
index 9629f97..b65d85b 100644
--- a/doc/usage/cmd/env.rst
+++ b/doc/usage/cmd/env.rst
@@ -79,7 +79,8 @@
environment to their default values.
var
- list of variable name.
+ list of variable names. If variable is not part of default
+ environment, it is deleted with a warning message on console.
\-a
all U-Boot environment.
\-f
@@ -309,6 +310,7 @@
Reset environment variable to default value, in memory::
=> env default bootcmd
+ => env default ipaddr serverip
=> env default -a
Save current environment in persistent storage::
diff --git a/doc/usage/cmd/upl.rst b/doc/usage/cmd/upl.rst
new file mode 100644
index 0000000..8d6ea5d
--- /dev/null
+++ b/doc/usage/cmd/upl.rst
@@ -0,0 +1,186 @@
+.. SPDX-License-Identifier: GPL-2.0+:
+
+upl command
+===========
+
+Synopsis
+--------
+
+::
+
+ upl write
+ upl read <addr>
+ upl info [-v]
+
+Description
+-----------
+
+The *upl* command is used to test U-Boot's support for the Universal Payload
+Specification (UPL) firmware standard (see :doc:`../upl`). It allows creation of
+a fake handoff for use in testing.
+
+
+upl write
+~~~~~~~~~
+
+Write a fake UPL handoff structure. The `upladdr` environment variable is set to
+the address of this structure and `uplsize` is set to the size.
+
+
+upl read
+~~~~~~~~
+
+Read a UPL handoff structure into internal state. This allows testing that the
+handoff can be obtained.
+
+upl info
+~~~~~~~~
+
+Show basic information about usage of UPL:
+
+ UPL state
+ active or inactive (indicates whether U-Boot booted from UPL or not)
+
+ fit
+ Address of the FIT which was loaded
+
+ conf_offset 2a4
+ FIT offset of the chosen configuration
+
+For each image the following information is shown:
+
+ Image number
+ Images are numbered from 0
+
+ load
+ Address to which the image was loaded
+
+ size
+ Size of the loaded image
+
+ offset
+ FIT offset of the image
+
+ description
+ Description of the image
+
+
+Example
+-------
+
+This shows checking whether a UPL handoff was read at start-up::
+
+ => upl info
+ UPL state: active
+
+This shows how to use the command to write and display the handoff::
+
+ => upl write
+ UPL handoff written to bc8a5e0 size 662
+ => print upladdr
+ upladdr=bc8a5e0
+ => print uplsize
+ uplsize=662
+
+ > fdt addr ${upladdr}
+ Working FDT set to bc8a5e0
+ => fdt print
+ / {
+ #address-cells = <0x00000001>;
+ #size-cells = <0x00000001>;
+ options {
+ upl-params {
+ smbios = <0x00000123>;
+ acpi = <0x00000456>;
+ bootmode = "default", "s3";
+ addr-width = <0x0000002e>;
+ acpi-nvs-size = <0x00000100>;
+ };
+ upl-image {
+ fit = <0x00000789>;
+ conf-offset = <0x00000234>;
+ image-1 {
+ load = <0x00000001>;
+ size = <0x00000002>;
+ offset = <0x00000003>;
+ description = "U-Boot";
+ };
+ image-2 {
+ load = <0x00000004>;
+ size = <0x00000005>;
+ offset = <0x00000006>;
+ description = "ATF";
+ };
+ };
+ };
+ memory@0x10 {
+ reg = <0x00000010 0x00000020 0x00000030 0x00000040 0x00000050 0x00000060>;
+ };
+ memory@0x70 {
+ reg = <0x00000070 0x00000080>;
+ hotpluggable;
+ };
+ memory-map {
+ acpi@0x11 {
+ reg = <0x00000011 0x00000012 0x00000013 0x00000014 0x00000015 0x00000016 0x00000017 0x00000018 0x00000019 0x0000001a>;
+ usage = "acpi-reclaim";
+ };
+ u-boot@0x21 {
+ reg = <0x00000021 0x00000022>;
+ usage = "boot-data";
+ };
+ efi@0x23 {
+ reg = <0x00000023 0x00000024>;
+ usage = "runtime-code";
+ };
+ empty@0x25 {
+ reg = <0x00000025 0x00000026 0x00000027 0x00000028>;
+ };
+ acpi-things@0x2a {
+ reg = <0x0000002a 0x00000000>;
+ usage = "acpi-nvs", "runtime-code";
+ };
+ };
+ reserved-memory {
+ mmio@0x2b {
+ reg = <0x0000002b 0x0000002c>;
+ };
+ memory@0x2d {
+ reg = <0x0000002d 0x0000002e 0x0000002f 0x00000030>;
+ no-map;
+ };
+ };
+ serial@0xf1de0000 {
+ compatible = "ns16550a";
+ clock-frequency = <0x001c2000>;
+ current-speed = <0x0001c200>;
+ reg = <0xf1de0000 0x00000100>;
+ reg-io-shift = <0x00000002>;
+ reg-offset = <0x00000040>;
+ virtual-reg = <0x20000000>;
+ access-type = "mmio";
+ };
+ framebuffer@0xd0000000 {
+ compatible = "simple-framebuffer";
+ reg = <0xd0000000 0x10000000>;
+ width = <0x00000500>;
+ height = <0x00000500>;
+ stride = <0x00001400>;
+ format = "a8r8g8b8";
+ };
+ };
+ =>
+
+This showing reading the handoff into internal state::
+
+ => upl read bc8a5e0
+ Reading UPL at bc8a5e0
+ =>
+
+This shows getting basic information about UPL:
+
+ => upl info -v
+ UPL state: active
+ fit 1264000
+ conf_offset 2a4
+ image 0: load 200000 size 105f5c8 offset a4: U-Boot 2024.07-00770-g739ee12e8358 for sandbox board
diff --git a/doc/usage/cmd/ut.rst b/doc/usage/cmd/ut.rst
index 45bc9ff..afeafa8 100644
--- a/doc/usage/cmd/ut.rst
+++ b/doc/usage/cmd/ut.rst
@@ -32,7 +32,7 @@
For a list of available test suites, type `ut` by itself.
-Each test is normally run once, although those marked with `UT_TESTF_DM` are
+Each test is normally run once, although those marked with `UTF_DM` are
run with livetree and flattree where possible. To run a test more than once,
use the `-r` flag.
diff --git a/doc/usage/index.rst b/doc/usage/index.rst
index 1f6518b..b058c22 100644
--- a/doc/usage/index.rst
+++ b/doc/usage/index.rst
@@ -15,6 +15,7 @@
cmdline
semihosting
measured_boot
+ upl
Shell commands
--------------
@@ -114,6 +115,7 @@
cmd/tftpput
cmd/trace
cmd/true
+ cmd/upl
cmd/ums
cmd/unbind
cmd/ut
diff --git a/doc/usage/upl.rst b/doc/usage/upl.rst
new file mode 100644
index 0000000..3c4a10c
--- /dev/null
+++ b/doc/usage/upl.rst
@@ -0,0 +1,46 @@
+.. SPDX-License-Identifier: GPL-2.0-or-later
+
+Universal Payload
+-----------------
+
+`Universal Payload (UPL) <https://universalpayload.github.io/spec/index.html>`_
+is an Industry Standard for firmware components. UPL
+is designed to improve interoperability within the firmware industry, allowing
+mixing and matching of projects with less friction and fewer project-specific
+implementations. UPL is cross-platform, supporting ARM, x86 and RISC-V
+initially.
+
+UPL is defined in termns of two firmware components:
+
+`Platform Init`
+ Perhaps initial setup of the hardware and jumps to the payload.
+
+`Payload`
+ Selects the OS to boot
+
+In practice UPL can be used to handle any number of handoffs through the
+firmware startup process, with one program acting as platform init and another
+acting as the payload.
+
+UPL provides a standard for three main pieces:
+
+- file format for the payload, which may comprise multiple images to load
+- handoff format for the information the payload needs, such as serial port,
+ memory layout, etc.
+- machine state and register settings at the point of handoff
+
+See also the :doc:`cmd/upl`.
+
+UPL in U-Boot
+~~~~~~~~~~~~~
+
+U-Boot supports:
+
+- writing a UPL handoff (devicetree) in SPL
+- reading a UPL handoff in U-Boot proper
+- creating a FIT
+
+There are some new FIT features in UPL which are not yet supported in U-Boot.
+
+.. sectionauthor:: Simon Glass <sjg@chromium.org>
+.. July 2024
diff --git a/drivers/block/sandbox.c b/drivers/block/sandbox.c
index ec34f1a..6c74d66 100644
--- a/drivers/block/sandbox.c
+++ b/drivers/block/sandbox.c
@@ -25,7 +25,7 @@
struct udevice *host_dev = dev_get_parent(dev);
struct host_sb_plat *plat = dev_get_plat(host_dev);
- if (os_lseek(plat->fd, start * desc->blksz, OS_SEEK_SET) == -1) {
+ if (os_lseek(plat->fd, start * desc->blksz, OS_SEEK_SET) < 0) {
printf("ERROR: Invalid block %lx\n", start);
return -1;
}
@@ -44,7 +44,7 @@
struct udevice *host_dev = dev_get_parent(dev);
struct host_sb_plat *plat = dev_get_plat(host_dev);
- if (os_lseek(plat->fd, start * desc->blksz, OS_SEEK_SET) == -1) {
+ if (os_lseek(plat->fd, start * desc->blksz, OS_SEEK_SET) < 0) {
printf("ERROR: Invalid block %lx\n", start);
return -1;
}
diff --git a/drivers/clk/mediatek/clk-mt7622.c b/drivers/clk/mediatek/clk-mt7622.c
index 2beb630..23b9787 100644
--- a/drivers/clk/mediatek/clk-mt7622.c
+++ b/drivers/clk/mediatek/clk-mt7622.c
@@ -66,6 +66,24 @@
21, 0x358, 1, 0x35c, 0),
};
+static const struct mtk_gate_regs apmixed_cg_regs = {
+ .set_ofs = 0x8,
+ .clr_ofs = 0x8,
+ .sta_ofs = 0x8,
+};
+
+#define GATE_APMIXED(_id, _parent, _shift) { \
+ .id = _id, \
+ .parent = _parent, \
+ .regs = &apmixed_cg_regs, \
+ .shift = _shift, \
+ .flags = CLK_GATE_NO_SETCLR_INV, \
+ }
+
+static const struct mtk_gate apmixed_cgs[] = {
+ GATE_APMIXED(CLK_APMIXED_MAIN_CORE_EN, CLK_APMIXED_MAINPLL, 5),
+};
+
/* topckgen */
#define FACTOR0(_id, _parent, _mult, _div) \
FACTOR(_id, _parent, _mult, _div, CLK_PARENT_APMIXED)
@@ -366,6 +384,20 @@
};
/* infracfg */
+#define APMIXED_PARENT(_id) PARENT(_id, CLK_PARENT_APMIXED)
+#define XTAL_PARENT(_id) PARENT(_id, CLK_PARENT_XTAL)
+
+static const struct mtk_parent infra_mux1_parents[] = {
+ XTAL_PARENT(CLK_XTAL),
+ APMIXED_PARENT(CLK_APMIXED_MAINPLL),
+ APMIXED_PARENT(CLK_APMIXED_MAIN_CORE_EN),
+ APMIXED_PARENT(CLK_APMIXED_MAINPLL),
+};
+
+static const struct mtk_composite infra_muxes[] = {
+ MUX_MIXED(CLK_INFRA_MUX1_SEL, infra_mux1_parents, 0x000, 2, 2),
+};
+
static const struct mtk_gate_regs infra_cg_regs = {
.set_ofs = 0x40,
.clr_ofs = 0x44,
@@ -382,14 +414,26 @@
static const struct mtk_gate infra_cgs[] = {
GATE_INFRA(CLK_INFRA_DBGCLK_PD, CLK_TOP_AXI_SEL, 0),
- GATE_INFRA(CLK_INFRA_TRNG, CLK_TOP_AXI_SEL, 2),
GATE_INFRA(CLK_INFRA_AUDIO_PD, CLK_TOP_AUD_INTBUS_SEL, 5),
GATE_INFRA(CLK_INFRA_IRRX_PD, CLK_TOP_IRRX_SEL, 16),
GATE_INFRA(CLK_INFRA_APXGPT_PD, CLK_TOP_F10M_REF_SEL, 18),
GATE_INFRA(CLK_INFRA_PMIC_PD, CLK_TOP_PMICSPI_SEL, 22),
+ GATE_INFRA(CLK_INFRA_TRNG, CLK_TOP_AXI_SEL, 2),
};
/* pericfg */
+static const int peribus_ck_parents[] = {
+ CLK_TOP_SYSPLL1_D8,
+ CLK_TOP_SYSPLL1_D4,
+};
+
+#define PERI_MUX(_id, _parents, _reg, _shift, _width) \
+ MUX_FLAGS(_id, _parents, _reg, _shift, _width, CLK_PARENT_TOPCKGEN)
+
+static const struct mtk_composite peri_muxes[] = {
+ PERI_MUX(CLK_PERIBUS_SEL, peribus_ck_parents, 0x05c, 0, 1),
+};
+
static const struct mtk_gate_regs peri0_cg_regs = {
.set_ofs = 0x8,
.clr_ofs = 0x10,
@@ -402,13 +446,17 @@
.sta_ofs = 0x1C,
};
-#define GATE_PERI0(_id, _parent, _shift) { \
+#define GATE_PERI0_FLAGS(_id, _parent, _shift, _flags) { \
.id = _id, \
.parent = _parent, \
.regs = &peri0_cg_regs, \
.shift = _shift, \
- .flags = CLK_GATE_SETCLR | CLK_PARENT_TOPCKGEN, \
+ .flags = _flags, \
}
+#define GATE_PERI0(_id, _parent, _shift) \
+ GATE_PERI0_FLAGS(_id, _parent, _shift, CLK_GATE_SETCLR | CLK_PARENT_TOPCKGEN)
+#define GATE_PERI0_XTAL(_id, _parent, _shift) \
+ GATE_PERI0_FLAGS(_id, _parent, _shift, CLK_GATE_SETCLR | CLK_PARENT_XTAL)
#define GATE_PERI1(_id, _parent, _shift) { \
.id = _id, \
@@ -421,14 +469,14 @@
static const struct mtk_gate peri_cgs[] = {
/* PERI0 */
GATE_PERI0(CLK_PERI_THERM_PD, CLK_TOP_AXI_SEL, 1),
- GATE_PERI0(CLK_PERI_PWM1_PD, CLK_XTAL, 2),
- GATE_PERI0(CLK_PERI_PWM2_PD, CLK_XTAL, 3),
- GATE_PERI0(CLK_PERI_PWM3_PD, CLK_XTAL, 4),
- GATE_PERI0(CLK_PERI_PWM4_PD, CLK_XTAL, 5),
- GATE_PERI0(CLK_PERI_PWM5_PD, CLK_XTAL, 6),
- GATE_PERI0(CLK_PERI_PWM6_PD, CLK_XTAL, 7),
- GATE_PERI0(CLK_PERI_PWM7_PD, CLK_XTAL, 8),
- GATE_PERI0(CLK_PERI_PWM_PD, CLK_XTAL, 9),
+ GATE_PERI0_XTAL(CLK_PERI_PWM1_PD, CLK_XTAL, 2),
+ GATE_PERI0_XTAL(CLK_PERI_PWM2_PD, CLK_XTAL, 3),
+ GATE_PERI0_XTAL(CLK_PERI_PWM3_PD, CLK_XTAL, 4),
+ GATE_PERI0_XTAL(CLK_PERI_PWM4_PD, CLK_XTAL, 5),
+ GATE_PERI0_XTAL(CLK_PERI_PWM5_PD, CLK_XTAL, 6),
+ GATE_PERI0_XTAL(CLK_PERI_PWM6_PD, CLK_XTAL, 7),
+ GATE_PERI0_XTAL(CLK_PERI_PWM7_PD, CLK_XTAL, 8),
+ GATE_PERI0_XTAL(CLK_PERI_PWM_PD, CLK_XTAL, 9),
GATE_PERI0(CLK_PERI_AP_DMA_PD, CLK_TOP_AXI_SEL, 12),
GATE_PERI0(CLK_PERI_MSDC30_0_PD, CLK_TOP_MSDC30_0_SEL, 13),
GATE_PERI0(CLK_PERI_MSDC30_1_PD, CLK_TOP_MSDC30_1_SEL, 14),
@@ -436,12 +484,13 @@
GATE_PERI0(CLK_PERI_UART1_PD, CLK_TOP_AXI_SEL, 18),
GATE_PERI0(CLK_PERI_UART2_PD, CLK_TOP_AXI_SEL, 19),
GATE_PERI0(CLK_PERI_UART3_PD, CLK_TOP_AXI_SEL, 20),
+ GATE_PERI0(CLK_PERI_UART4_PD, CLK_TOP_AXI_SEL, 21),
GATE_PERI0(CLK_PERI_BTIF_PD, CLK_TOP_AXI_SEL, 22),
GATE_PERI0(CLK_PERI_I2C0_PD, CLK_TOP_AXI_SEL, 23),
GATE_PERI0(CLK_PERI_I2C1_PD, CLK_TOP_AXI_SEL, 24),
GATE_PERI0(CLK_PERI_I2C2_PD, CLK_TOP_AXI_SEL, 25),
GATE_PERI0(CLK_PERI_SPI1_PD, CLK_TOP_SPI1_SEL, 26),
- GATE_PERI0(CLK_PERI_AUXADC_PD, CLK_XTAL, 27),
+ GATE_PERI0_XTAL(CLK_PERI_AUXADC_PD, CLK_XTAL, 27),
GATE_PERI0(CLK_PERI_SPI0_PD, CLK_TOP_SPI0_SEL, 28),
GATE_PERI0(CLK_PERI_SNFI_PD, CLK_TOP_NFI_INFRA_SEL, 29),
GATE_PERI0(CLK_PERI_NFI_PD, CLK_TOP_AXI_SEL, 30),
@@ -550,12 +599,33 @@
GATE_SSUSB(CLK_SSUSB_DMA_EN, CLK_TOP_HIF_SEL, 8),
};
+static const struct mtk_clk_tree mt7622_apmixed_clk_tree = {
+ .xtal2_rate = 25 * MHZ,
+ .plls = apmixed_plls,
+ .gates_offs = CLK_APMIXED_MAIN_CORE_EN,
+ .gates = apmixed_cgs,
+};
+
+static const struct mtk_clk_tree mt7622_infra_clk_tree = {
+ .xtal_rate = 25 * MHZ,
+ .muxes_offs = CLK_INFRA_MUX1_SEL,
+ .gates_offs = CLK_INFRA_DBGCLK_PD,
+ .muxes = infra_muxes,
+ .gates = infra_cgs,
+};
+
+static const struct mtk_clk_tree mt7622_peri_clk_tree = {
+ .xtal_rate = 25 * MHZ,
+ .muxes_offs = CLK_PERIBUS_SEL,
+ .gates_offs = CLK_PERI_THERM_PD,
+ .muxes = peri_muxes,
+ .gates = peri_cgs,
+};
+
static const struct mtk_clk_tree mt7622_clk_tree = {
.xtal_rate = 25 * MHZ,
- .xtal2_rate = 25 * MHZ,
.fdivs_offs = CLK_TOP_TO_USB3_SYS,
.muxes_offs = CLK_TOP_AXI_SEL,
- .plls = apmixed_plls,
.fclks = top_fixed_clks,
.fdivs = top_fixed_divs,
.muxes = top_muxes,
@@ -582,7 +652,7 @@
struct mtk_clk_priv *priv = dev_get_priv(dev);
int ret;
- ret = mtk_common_clk_init(dev, &mt7622_clk_tree);
+ ret = mtk_common_clk_init(dev, &mt7622_apmixed_clk_tree);
if (ret)
return ret;
@@ -603,12 +673,12 @@
static int mt7622_infracfg_probe(struct udevice *dev)
{
- return mtk_common_clk_gate_init(dev, &mt7622_clk_tree, infra_cgs);
+ return mtk_common_clk_infrasys_init(dev, &mt7622_infra_clk_tree);
}
static int mt7622_pericfg_probe(struct udevice *dev)
{
- return mtk_common_clk_gate_init(dev, &mt7622_clk_tree, peri_cgs);
+ return mtk_common_clk_infrasys_init(dev, &mt7622_peri_clk_tree);
}
static int mt7622_pciesys_probe(struct udevice *dev)
diff --git a/drivers/clk/mediatek/clk-mt7623.c b/drivers/clk/mediatek/clk-mt7623.c
index 5072c99..d0b80f4 100644
--- a/drivers/clk/mediatek/clk-mt7623.c
+++ b/drivers/clk/mediatek/clk-mt7623.c
@@ -25,6 +25,22 @@
#define AXI_DIV_SEL(x) (x)
/* apmixedsys */
+static const int pll_id_offs_map[] = {
+ [CLK_APMIXED_ARMPLL] = 0,
+ [CLK_APMIXED_MAINPLL] = 1,
+ [CLK_APMIXED_UNIVPLL] = 2,
+ [CLK_APMIXED_MMPLL] = 3,
+ [CLK_APMIXED_MSDCPLL] = 4,
+ [CLK_APMIXED_TVDPLL] = 5,
+ [CLK_APMIXED_AUD1PLL] = 6,
+ [CLK_APMIXED_TRGPLL] = 7,
+ [CLK_APMIXED_ETHPLL] = 8,
+ [CLK_APMIXED_VDECPLL] = 9,
+ [CLK_APMIXED_HADDS2PLL] = 10,
+ [CLK_APMIXED_AUD2PLL] = 11,
+ [CLK_APMIXED_TVD2PLL] = 12,
+};
+
#define PLL(_id, _reg, _pwr_reg, _en_mask, _flags, _pcwbits, _pd_reg, \
_pd_shift, _pcw_reg, _pcw_shift) { \
.id = _id, \
@@ -71,6 +87,176 @@
};
/* topckgen */
+
+/* Fixed CLK exposed upstream by the hdmi PHY driver */
+#define CLK_TOP_HDMITX_CLKDIG_CTS CLK_TOP_NR
+
+static const int top_id_offs_map[CLK_TOP_NR + 1] = {
+ /* Fixed CLK */
+ [CLK_TOP_DPI] = 0,
+ [CLK_TOP_DMPLL] = 1,
+ [CLK_TOP_VENCPLL] = 2,
+ [CLK_TOP_HDMI_0_PIX340M] = 3,
+ [CLK_TOP_HDMI_0_DEEP340M] = 4,
+ [CLK_TOP_HDMI_0_PLL340M] = 5,
+ [CLK_TOP_HADDS2_FB] = 6,
+ [CLK_TOP_WBG_DIG_416M] = 7,
+ [CLK_TOP_DSI0_LNTC_DSI] = 8,
+ [CLK_TOP_HDMI_SCL_RX] = 9,
+ [CLK_TOP_32K_EXTERNAL] = 10,
+ [CLK_TOP_HDMITX_CLKDIG_CTS] = 11,
+ [CLK_TOP_AUD_EXT1] = 12,
+ [CLK_TOP_AUD_EXT2] = 13,
+ [CLK_TOP_NFI1X_PAD] = 14,
+ /* Factor CLK */
+ [CLK_TOP_SYSPLL] = 15,
+ [CLK_TOP_SYSPLL_D2] = 16,
+ [CLK_TOP_SYSPLL_D3] = 17,
+ [CLK_TOP_SYSPLL_D5] = 18,
+ [CLK_TOP_SYSPLL_D7] = 19,
+ [CLK_TOP_SYSPLL1_D2] = 20,
+ [CLK_TOP_SYSPLL1_D4] = 21,
+ [CLK_TOP_SYSPLL1_D8] = 22,
+ [CLK_TOP_SYSPLL1_D16] = 23,
+ [CLK_TOP_SYSPLL2_D2] = 24,
+ [CLK_TOP_SYSPLL2_D4] = 25,
+ [CLK_TOP_SYSPLL2_D8] = 26,
+ [CLK_TOP_SYSPLL3_D2] = 27,
+ [CLK_TOP_SYSPLL3_D4] = 28,
+ [CLK_TOP_SYSPLL4_D2] = 29,
+ [CLK_TOP_SYSPLL4_D4] = 30,
+ [CLK_TOP_UNIVPLL] = 31,
+ [CLK_TOP_UNIVPLL_D2] = 32,
+ [CLK_TOP_UNIVPLL_D3] = 33,
+ [CLK_TOP_UNIVPLL_D5] = 34,
+ [CLK_TOP_UNIVPLL_D7] = 35,
+ [CLK_TOP_UNIVPLL_D26] = 36,
+ [CLK_TOP_UNIVPLL_D52] = 37,
+ [CLK_TOP_UNIVPLL_D108] = 38,
+ [CLK_TOP_USB_PHY48M] = 39,
+ [CLK_TOP_UNIVPLL1_D2] = 40,
+ [CLK_TOP_UNIVPLL1_D4] = 41,
+ [CLK_TOP_UNIVPLL1_D8] = 42,
+ [CLK_TOP_UNIVPLL2_D2] = 43,
+ [CLK_TOP_UNIVPLL2_D4] = 44,
+ [CLK_TOP_UNIVPLL2_D8] = 45,
+ [CLK_TOP_UNIVPLL2_D16] = 46,
+ [CLK_TOP_UNIVPLL2_D32] = 47,
+ [CLK_TOP_UNIVPLL3_D2] = 48,
+ [CLK_TOP_UNIVPLL3_D4] = 49,
+ [CLK_TOP_UNIVPLL3_D8] = 50,
+ [CLK_TOP_MSDCPLL] = 51,
+ [CLK_TOP_MSDCPLL_D2] = 52,
+ [CLK_TOP_MSDCPLL_D4] = 53,
+ [CLK_TOP_MSDCPLL_D8] = 54,
+ [CLK_TOP_MMPLL] = 55,
+ [CLK_TOP_MMPLL_D2] = 56,
+ [CLK_TOP_DMPLL_D2] = 57,
+ [CLK_TOP_DMPLL_D4] = 58,
+ [CLK_TOP_DMPLL_X2] = 59,
+ [CLK_TOP_TVDPLL] = 60,
+ [CLK_TOP_TVDPLL_D2] = 61,
+ [CLK_TOP_TVDPLL_D4] = 62,
+ [CLK_TOP_VDECPLL] = 63,
+ [CLK_TOP_TVD2PLL] = 64,
+ [CLK_TOP_TVD2PLL_D2] = 65,
+ [CLK_TOP_MIPIPLL] = 66,
+ [CLK_TOP_MIPIPLL_D2] = 67,
+ [CLK_TOP_MIPIPLL_D4] = 68,
+ [CLK_TOP_HDMIPLL] = 69,
+ [CLK_TOP_HDMIPLL_D2] = 70,
+ [CLK_TOP_HDMIPLL_D3] = 71,
+ [CLK_TOP_ARMPLL_1P3G] = 72,
+ [CLK_TOP_AUDPLL] = 73,
+ [CLK_TOP_AUDPLL_D4] = 74,
+ [CLK_TOP_AUDPLL_D8] = 75,
+ [CLK_TOP_AUDPLL_D16] = 76,
+ [CLK_TOP_AUDPLL_D24] = 77,
+ [CLK_TOP_AUD1PLL_98M] = 78,
+ [CLK_TOP_AUD2PLL_90M] = 79,
+ [CLK_TOP_HADDS2PLL_98M] = 80,
+ [CLK_TOP_HADDS2PLL_294M] = 81,
+ [CLK_TOP_ETHPLL_500M] = 82,
+ [CLK_TOP_CLK26M_D8] = 83,
+ [CLK_TOP_32K_INTERNAL] = 84,
+ [CLK_TOP_AXISEL_D4] = 85,
+ [CLK_TOP_8BDAC] = 86,
+ /* MUX CLK */
+ [CLK_TOP_AXI_SEL] = 87,
+ [CLK_TOP_MEM_SEL] = 88,
+ [CLK_TOP_DDRPHYCFG_SEL] = 89,
+ [CLK_TOP_MM_SEL] = 90,
+ [CLK_TOP_PWM_SEL] = 91,
+ [CLK_TOP_VDEC_SEL] = 92,
+ [CLK_TOP_MFG_SEL] = 93,
+ [CLK_TOP_CAMTG_SEL] = 94,
+ [CLK_TOP_UART_SEL] = 95,
+ [CLK_TOP_SPI0_SEL] = 96,
+ [CLK_TOP_USB20_SEL] = 97,
+ [CLK_TOP_MSDC30_0_SEL] = 98,
+ [CLK_TOP_MSDC30_1_SEL] = 99,
+ [CLK_TOP_MSDC30_2_SEL] = 100,
+ [CLK_TOP_AUDIO_SEL] = 101,
+ [CLK_TOP_AUDINTBUS_SEL] = 102,
+ [CLK_TOP_PMICSPI_SEL] = 103,
+ [CLK_TOP_SCP_SEL] = 104,
+ [CLK_TOP_DPI0_SEL] = 105,
+ [CLK_TOP_DPI1_SEL] = 106,
+ [CLK_TOP_TVE_SEL] = 107,
+ [CLK_TOP_HDMI_SEL] = 108,
+ [CLK_TOP_APLL_SEL] = 109,
+ [CLK_TOP_RTC_SEL] = 110,
+ [CLK_TOP_NFI2X_SEL] = 111,
+ [CLK_TOP_EMMC_HCLK_SEL] = 112,
+ [CLK_TOP_FLASH_SEL] = 113,
+ [CLK_TOP_DI_SEL] = 114,
+ [CLK_TOP_NR_SEL] = 115,
+ [CLK_TOP_OSD_SEL] = 116,
+ [CLK_TOP_HDMIRX_BIST_SEL] = 117,
+ [CLK_TOP_INTDIR_SEL] = 118,
+ [CLK_TOP_ASM_I_SEL] = 119,
+ [CLK_TOP_ASM_M_SEL] = 120,
+ [CLK_TOP_ASM_H_SEL] = 121,
+ [CLK_TOP_MS_CARD_SEL] = 122,
+ [CLK_TOP_ETHIF_SEL] = 123,
+ [CLK_TOP_HDMIRX26_24_SEL] = 124,
+ [CLK_TOP_MSDC30_3_SEL] = 125,
+ [CLK_TOP_CMSYS_SEL] = 126,
+ [CLK_TOP_SPI1_SEL] = 127,
+ [CLK_TOP_SPI2_SEL] = 128,
+ [CLK_TOP_8BDAC_SEL] = 129,
+ [CLK_TOP_AUD2DVD_SEL] = 130,
+ [CLK_TOP_PADMCLK_SEL] = 131,
+ [CLK_TOP_AUD_MUX1_SEL] = 132,
+ [CLK_TOP_AUD_MUX2_SEL] = 133,
+ [CLK_TOP_AUDPLL_MUX_SEL] = 134,
+ [CLK_TOP_AUD_K1_SRC_SEL] = 135,
+ [CLK_TOP_AUD_K2_SRC_SEL] = 136,
+ [CLK_TOP_AUD_K3_SRC_SEL] = 137,
+ [CLK_TOP_AUD_K4_SRC_SEL] = 138,
+ [CLK_TOP_AUD_K5_SRC_SEL] = 139,
+ [CLK_TOP_AUD_K6_SRC_SEL] = 140,
+ /* Misc CLK only used as parents */
+ [CLK_TOP_AUD_EXTCK1_DIV] = 141,
+ [CLK_TOP_AUD_EXTCK2_DIV] = 142,
+ [CLK_TOP_AUD_MUX1_DIV] = 143,
+ [CLK_TOP_AUD_MUX2_DIV] = 144,
+ [CLK_TOP_AUD_K1_SRC_DIV] = 145,
+ [CLK_TOP_AUD_K2_SRC_DIV] = 146,
+ [CLK_TOP_AUD_K3_SRC_DIV] = 147,
+ [CLK_TOP_AUD_K4_SRC_DIV] = 148,
+ [CLK_TOP_AUD_K5_SRC_DIV] = 149,
+ [CLK_TOP_AUD_K6_SRC_DIV] = 150,
+ [CLK_TOP_AUD_48K_TIMING] = 151,
+ [CLK_TOP_AUD_44K_TIMING] = 152,
+ [CLK_TOP_AUD_I2S1_MCLK] = 153,
+ [CLK_TOP_AUD_I2S2_MCLK] = 154,
+ [CLK_TOP_AUD_I2S3_MCLK] = 155,
+ [CLK_TOP_AUD_I2S4_MCLK] = 156,
+ [CLK_TOP_AUD_I2S5_MCLK] = 157,
+ [CLK_TOP_AUD_I2S6_MCLK] = 158,
+};
+
#define FACTOR0(_id, _parent, _mult, _div) \
FACTOR(_id, _parent, _mult, _div, CLK_PARENT_APMIXED)
@@ -586,21 +772,26 @@
.sta_ofs = 0x48,
};
-#define GATE_INFRA(_id, _parent, _shift) { \
+#define GATE_INFRA_FLAGS(_id, _parent, _shift, _flags) { \
.id = _id, \
.parent = _parent, \
.regs = &infra_cg_regs, \
.shift = _shift, \
- .flags = CLK_GATE_SETCLR | CLK_PARENT_TOPCKGEN, \
+ .flags = _flags, \
}
+#define GATE_INFRA(_id, _parent, _shift) \
+ GATE_INFRA_FLAGS(_id, _parent, _shift, CLK_GATE_SETCLR | CLK_PARENT_TOPCKGEN)
+#define GATE_INFRA_XTAL(_id, _parent, _shift) \
+ GATE_INFRA_FLAGS(_id, _parent, _shift, CLK_GATE_SETCLR | CLK_PARENT_XTAL)
+
static const struct mtk_gate infra_cgs[] = {
GATE_INFRA(CLK_INFRA_DBG, CLK_TOP_AXI_SEL, 0),
GATE_INFRA(CLK_INFRA_SMI, CLK_TOP_MM_SEL, 1),
GATE_INFRA(CLK_INFRA_QAXI_CM4, CLK_TOP_AXI_SEL, 2),
GATE_INFRA(CLK_INFRA_AUD_SPLIN_B, CLK_TOP_HADDS2PLL_294M, 4),
- GATE_INFRA(CLK_INFRA_AUDIO, CLK_XTAL, 5),
- GATE_INFRA(CLK_INFRA_EFUSE, CLK_XTAL, 6),
+ GATE_INFRA_XTAL(CLK_INFRA_AUDIO, CLK_XTAL, 5),
+ GATE_INFRA_XTAL(CLK_INFRA_EFUSE, CLK_XTAL, 6),
GATE_INFRA(CLK_INFRA_L2C_SRAM, CLK_TOP_MM_SEL, 7),
GATE_INFRA(CLK_INFRA_M4U, CLK_TOP_MEM_SEL, 8),
GATE_INFRA(CLK_INFRA_CONNMCU, CLK_TOP_WBG_DIG_416M, 12),
@@ -616,6 +807,74 @@
};
/* pericfg */
+static const int peri_id_offs_map[] = {
+ /* MUX CLK */
+ [CLK_PERI_UART0_SEL] = 1,
+ [CLK_PERI_UART1_SEL] = 2,
+ [CLK_PERI_UART2_SEL] = 3,
+ [CLK_PERI_UART3_SEL] = 4,
+ /* GATE CLK */
+ [CLK_PERI_NFI] = 5,
+ [CLK_PERI_THERM] = 6,
+ [CLK_PERI_PWM1] = 7,
+ [CLK_PERI_PWM2] = 8,
+ [CLK_PERI_PWM3] = 9,
+ [CLK_PERI_PWM4] = 10,
+ [CLK_PERI_PWM5] = 11,
+ [CLK_PERI_PWM6] = 12,
+ [CLK_PERI_PWM7] = 13,
+ [CLK_PERI_PWM] = 14,
+ [CLK_PERI_USB0] = 15,
+ [CLK_PERI_USB1] = 16,
+ [CLK_PERI_AP_DMA] = 17,
+ [CLK_PERI_MSDC30_0] = 18,
+ [CLK_PERI_MSDC30_1] = 19,
+ [CLK_PERI_MSDC30_2] = 20,
+ [CLK_PERI_MSDC30_3] = 21,
+ [CLK_PERI_MSDC50_3] = 22,
+ [CLK_PERI_NLI] = 23,
+ [CLK_PERI_UART0] = 24,
+ [CLK_PERI_UART1] = 25,
+ [CLK_PERI_UART2] = 26,
+ [CLK_PERI_UART3] = 27,
+ [CLK_PERI_BTIF] = 28,
+ [CLK_PERI_I2C0] = 29,
+ [CLK_PERI_I2C1] = 30,
+ [CLK_PERI_I2C2] = 31,
+ [CLK_PERI_I2C3] = 32,
+ [CLK_PERI_AUXADC] = 33,
+ [CLK_PERI_SPI0] = 34,
+ [CLK_PERI_ETH] = 35,
+ [CLK_PERI_USB0_MCU] = 36,
+ [CLK_PERI_USB1_MCU] = 37,
+ [CLK_PERI_USB_SLV] = 38,
+ [CLK_PERI_GCPU] = 39,
+ [CLK_PERI_NFI_ECC] = 40,
+ [CLK_PERI_NFI_PAD] = 41,
+ [CLK_PERI_FLASH] = 42,
+ [CLK_PERI_HOST89_INT] = 43,
+ [CLK_PERI_HOST89_SPI] = 44,
+ [CLK_PERI_HOST89_DVD] = 45,
+ [CLK_PERI_SPI1] = 46,
+ [CLK_PERI_SPI2] = 47,
+ [CLK_PERI_FCI] = 48,
+};
+
+#define TOP_PARENT(_id) PARENT(_id, CLK_PARENT_TOPCKGEN)
+#define XTAL_PARENT(_id) PARENT(_id, CLK_PARENT_XTAL)
+
+static const struct mtk_parent uart_ck_sel_parents[] = {
+ XTAL_PARENT(CLK_XTAL),
+ TOP_PARENT(CLK_TOP_UART_SEL),
+};
+
+static const struct mtk_composite peri_muxes[] = {
+ MUX_MIXED(CLK_PERI_UART0_SEL, uart_ck_sel_parents, 0x40C, 0, 1),
+ MUX_MIXED(CLK_PERI_UART1_SEL, uart_ck_sel_parents, 0x40C, 1, 1),
+ MUX_MIXED(CLK_PERI_UART2_SEL, uart_ck_sel_parents, 0x40C, 2, 1),
+ MUX_MIXED(CLK_PERI_UART3_SEL, uart_ck_sel_parents, 0x40C, 3, 1),
+};
+
static const struct mtk_gate_regs peri0_cg_regs = {
.set_ofs = 0x8,
.clr_ofs = 0x10,
@@ -628,13 +887,17 @@
.sta_ofs = 0x1C,
};
-#define GATE_PERI0(_id, _parent, _shift) { \
+#define GATE_PERI0_FLAGS(_id, _parent, _shift, _flags) { \
.id = _id, \
.parent = _parent, \
.regs = &peri0_cg_regs, \
.shift = _shift, \
- .flags = CLK_GATE_SETCLR | CLK_PARENT_TOPCKGEN, \
+ .flags = _flags, \
}
+#define GATE_PERI0(_id, _parent, _shift) \
+ GATE_PERI0_FLAGS(_id, _parent, _shift, CLK_GATE_SETCLR | CLK_PARENT_TOPCKGEN)
+#define GATE_PERI0_XTAL(_id, _parent, _shift) \
+ GATE_PERI0_FLAGS(_id, _parent, _shift, CLK_GATE_SETCLR | CLK_PARENT_XTAL)
#define GATE_PERI1(_id, _parent, _shift) { \
.id = _id, \
@@ -672,10 +935,10 @@
GATE_PERI0(CLK_PERI_I2C0, CLK_TOP_AXI_SEL, 24),
GATE_PERI0(CLK_PERI_I2C1, CLK_TOP_AXI_SEL, 25),
GATE_PERI0(CLK_PERI_I2C2, CLK_TOP_AXI_SEL, 26),
- GATE_PERI0(CLK_PERI_I2C3, CLK_XTAL, 27),
- GATE_PERI0(CLK_PERI_AUXADC, CLK_XTAL, 28),
+ GATE_PERI0_XTAL(CLK_PERI_I2C3, CLK_XTAL, 27),
+ GATE_PERI0_XTAL(CLK_PERI_AUXADC, CLK_XTAL, 28),
GATE_PERI0(CLK_PERI_SPI0, CLK_TOP_SPI0_SEL, 29),
- GATE_PERI0(CLK_PERI_ETH, CLK_XTAL, 30),
+ GATE_PERI0_XTAL(CLK_PERI_ETH, CLK_XTAL, 30),
GATE_PERI0(CLK_PERI_USB0_MCU, CLK_TOP_AXI_SEL, 31),
GATE_PERI1(CLK_PERI_USB1_MCU, CLK_TOP_AXI_SEL, 0),
@@ -730,12 +993,17 @@
GATE_ETH_HIF1(CLK_HIFSYS_PCIE2, CLK_TOP_ETHPLL_500M, 26),
};
-static const struct mtk_clk_tree mt7623_clk_tree = {
- .xtal_rate = 26 * MHZ,
+static const struct mtk_clk_tree mt7623_apmixedsys_clk_tree = {
.xtal2_rate = 26 * MHZ,
- .fdivs_offs = CLK_TOP_SYSPLL,
- .muxes_offs = CLK_TOP_AXI_SEL,
+ .id_offs_map = pll_id_offs_map,
.plls = apmixed_plls,
+};
+
+static const struct mtk_clk_tree mt7623_topckgen_clk_tree = {
+ .xtal_rate = 26 * MHZ,
+ .id_offs_map = top_id_offs_map,
+ .fdivs_offs = top_id_offs_map[CLK_TOP_SYSPLL],
+ .muxes_offs = top_id_offs_map[CLK_TOP_AXI_SEL],
.fclks = top_fixed_clks,
.fdivs = top_fixed_divs,
.muxes = top_muxes,
@@ -760,7 +1028,7 @@
struct mtk_clk_priv *priv = dev_get_priv(dev);
int ret;
- ret = mtk_common_clk_init(dev, &mt7623_clk_tree);
+ ret = mtk_common_clk_init(dev, &mt7623_apmixedsys_clk_tree);
if (ret)
return ret;
@@ -774,27 +1042,45 @@
static int mt7623_topckgen_probe(struct udevice *dev)
{
- return mtk_common_clk_init(dev, &mt7623_clk_tree);
+ return mtk_common_clk_init(dev, &mt7623_topckgen_clk_tree);
}
+static const struct mtk_clk_tree mt7623_clk_gate_tree = {
+ /* Each CLK ID for gates clock starts at index 1 */
+ .gates_offs = 1,
+ .xtal_rate = 26 * MHZ,
+};
+
static int mt7623_infracfg_probe(struct udevice *dev)
{
- return mtk_common_clk_gate_init(dev, &mt7623_clk_tree, infra_cgs);
+ return mtk_common_clk_gate_init(dev, &mt7623_clk_gate_tree,
+ infra_cgs);
}
+static const struct mtk_clk_tree mt7623_clk_peri_tree = {
+ .id_offs_map = peri_id_offs_map,
+ .muxes_offs = peri_id_offs_map[CLK_PERI_UART0_SEL],
+ .gates_offs = peri_id_offs_map[CLK_PERI_NFI],
+ .muxes = peri_muxes,
+ .gates = peri_cgs,
+ .xtal_rate = 26 * MHZ,
+};
+
static int mt7623_pericfg_probe(struct udevice *dev)
{
- return mtk_common_clk_gate_init(dev, &mt7623_clk_tree, peri_cgs);
+ return mtk_common_clk_infrasys_init(dev, &mt7623_clk_peri_tree);
}
static int mt7623_hifsys_probe(struct udevice *dev)
{
- return mtk_common_clk_gate_init(dev, &mt7623_clk_tree, hif_cgs);
+ return mtk_common_clk_gate_init(dev, &mt7623_clk_gate_tree,
+ hif_cgs);
}
static int mt7623_ethsys_probe(struct udevice *dev)
{
- return mtk_common_clk_gate_init(dev, &mt7623_clk_tree, eth_cgs);
+ return mtk_common_clk_gate_init(dev, &mt7623_clk_gate_tree,
+ eth_cgs);
}
static int mt7623_ethsys_hifsys_bind(struct udevice *dev)
@@ -889,7 +1175,7 @@
.of_match = mt7623_pericfg_compat,
.probe = mt7623_pericfg_probe,
.priv_auto = sizeof(struct mtk_cg_priv),
- .ops = &mtk_clk_gate_ops,
+ .ops = &mtk_clk_infrasys_ops,
.flags = DM_FLAG_PRE_RELOC,
};
diff --git a/drivers/clk/mediatek/clk-mt7981.c b/drivers/clk/mediatek/clk-mt7981.c
index 13dc3df..9707391 100644
--- a/drivers/clk/mediatek/clk-mt7981.c
+++ b/drivers/clk/mediatek/clk-mt7981.c
@@ -29,204 +29,204 @@
/* FIXED PLLS */
static const struct mtk_fixed_clk fixed_pll_clks[] = {
- FIXED_CLK(CK_APMIXED_ARMPLL, CLK_XTAL, 1300000000),
- FIXED_CLK(CK_APMIXED_NET2PLL, CLK_XTAL, 800000000),
- FIXED_CLK(CK_APMIXED_MMPLL, CLK_XTAL, 720000000),
- FIXED_CLK(CK_APMIXED_SGMPLL, CLK_XTAL, 325000000),
- FIXED_CLK(CK_APMIXED_WEDMCUPLL, CLK_XTAL, 208000000),
- FIXED_CLK(CK_APMIXED_NET1PLL, CLK_XTAL, 2500000000),
- FIXED_CLK(CK_APMIXED_MPLL, CLK_XTAL, 416000000),
- FIXED_CLK(CK_APMIXED_APLL2, CLK_XTAL, 196608000),
+ FIXED_CLK(CLK_APMIXED_ARMPLL, CLK_XTAL, 1300000000),
+ FIXED_CLK(CLK_APMIXED_NET2PLL, CLK_XTAL, 800000000),
+ FIXED_CLK(CLK_APMIXED_MMPLL, CLK_XTAL, 720000000),
+ FIXED_CLK(CLK_APMIXED_SGMPLL, CLK_XTAL, 325000000),
+ FIXED_CLK(CLK_APMIXED_WEDMCUPLL, CLK_XTAL, 208000000),
+ FIXED_CLK(CLK_APMIXED_NET1PLL, CLK_XTAL, 2500000000),
+ FIXED_CLK(CLK_APMIXED_MPLL, CLK_XTAL, 416000000),
+ FIXED_CLK(CLK_APMIXED_APLL2, CLK_XTAL, 196608000),
};
/* TOPCKGEN FIXED CLK */
static const struct mtk_fixed_clk top_fixed_clks[] = {
- FIXED_CLK(CK_TOP_CB_CKSQ_40M, CLK_XTAL, 40000000),
+ FIXED_CLK(CLK_TOP_CB_CKSQ_40M, CLK_XTAL, 40000000),
};
/* TOPCKGEN FIXED DIV */
static const struct mtk_fixed_factor top_fixed_divs[] = {
- PLL_FACTOR(CK_TOP_CB_M_416M, "cb_m_416m", CK_APMIXED_MPLL, 1, 1),
- PLL_FACTOR(CK_TOP_CB_M_D2, "cb_m_d2", CK_APMIXED_MPLL, 1, 2),
- PLL_FACTOR(CK_TOP_CB_M_D3, "cb_m_d3", CK_APMIXED_MPLL, 1, 3),
- PLL_FACTOR(CK_TOP_M_D3_D2, "m_d3_d2", CK_APMIXED_MPLL, 1, 2),
- PLL_FACTOR(CK_TOP_CB_M_D4, "cb_m_d4", CK_APMIXED_MPLL, 1, 4),
- PLL_FACTOR(CK_TOP_CB_M_D8, "cb_m_d8", CK_APMIXED_MPLL, 1, 8),
- PLL_FACTOR(CK_TOP_M_D8_D2, "m_d8_d2", CK_APMIXED_MPLL, 1, 16),
- PLL_FACTOR(CK_TOP_CB_MM_720M, "cb_mm_720m", CK_APMIXED_MMPLL, 1, 1),
- PLL_FACTOR(CK_TOP_CB_MM_D2, "cb_mm_d2", CK_APMIXED_MMPLL, 1, 2),
- PLL_FACTOR(CK_TOP_CB_MM_D3, "cb_mm_d3", CK_APMIXED_MMPLL, 1, 3),
- PLL_FACTOR(CK_TOP_CB_MM_D3_D5, "cb_mm_d3_d5", CK_APMIXED_MMPLL, 1, 15),
- PLL_FACTOR(CK_TOP_CB_MM_D4, "cb_mm_d4", CK_APMIXED_MMPLL, 1, 4),
- PLL_FACTOR(CK_TOP_CB_MM_D6, "cb_mm_d6", CK_APMIXED_MMPLL, 1, 6),
- PLL_FACTOR(CK_TOP_MM_D6_D2, "mm_d6_d2", CK_APMIXED_MMPLL, 1, 12),
- PLL_FACTOR(CK_TOP_CB_MM_D8, "cb_mm_d8", CK_APMIXED_MMPLL, 1, 8),
- PLL_FACTOR(CK_TOP_CB_APLL2_196M, "cb_apll2_196m", CK_APMIXED_APLL2, 1,
+ PLL_FACTOR(CLK_TOP_CB_M_416M, "cb_m_416m", CLK_APMIXED_MPLL, 1, 1),
+ PLL_FACTOR(CLK_TOP_CB_M_D2, "cb_m_d2", CLK_APMIXED_MPLL, 1, 2),
+ PLL_FACTOR(CLK_TOP_CB_M_D3, "cb_m_d3", CLK_APMIXED_MPLL, 1, 3),
+ PLL_FACTOR(CLK_TOP_M_D3_D2, "m_d3_d2", CLK_APMIXED_MPLL, 1, 2),
+ PLL_FACTOR(CLK_TOP_CB_M_D4, "cb_m_d4", CLK_APMIXED_MPLL, 1, 4),
+ PLL_FACTOR(CLK_TOP_CB_M_D8, "cb_m_d8", CLK_APMIXED_MPLL, 1, 8),
+ PLL_FACTOR(CLK_TOP_M_D8_D2, "m_d8_d2", CLK_APMIXED_MPLL, 1, 16),
+ PLL_FACTOR(CLK_TOP_CB_MM_720M, "cb_mm_720m", CLK_APMIXED_MMPLL, 1, 1),
+ PLL_FACTOR(CLK_TOP_CB_MM_D2, "cb_mm_d2", CLK_APMIXED_MMPLL, 1, 2),
+ PLL_FACTOR(CLK_TOP_CB_MM_D3, "cb_mm_d3", CLK_APMIXED_MMPLL, 1, 3),
+ PLL_FACTOR(CLK_TOP_CB_MM_D3_D5, "cb_mm_d3_d5", CLK_APMIXED_MMPLL, 1, 15),
+ PLL_FACTOR(CLK_TOP_CB_MM_D4, "cb_mm_d4", CLK_APMIXED_MMPLL, 1, 4),
+ PLL_FACTOR(CLK_TOP_CB_MM_D6, "cb_mm_d6", CLK_APMIXED_MMPLL, 1, 6),
+ PLL_FACTOR(CLK_TOP_MM_D6_D2, "mm_d6_d2", CLK_APMIXED_MMPLL, 1, 12),
+ PLL_FACTOR(CLK_TOP_CB_MM_D8, "cb_mm_d8", CLK_APMIXED_MMPLL, 1, 8),
+ PLL_FACTOR(CLK_TOP_CB_APLL2_196M, "cb_apll2_196m", CLK_APMIXED_APLL2, 1,
1),
- PLL_FACTOR(CK_TOP_APLL2_D2, "apll2_d2", CK_APMIXED_APLL2, 1, 2),
- PLL_FACTOR(CK_TOP_APLL2_D4, "apll2_d4", CK_APMIXED_APLL2, 1, 4),
- PLL_FACTOR(CK_TOP_NET1_2500M, "net1_2500m", CK_APMIXED_NET1PLL, 1, 1),
- PLL_FACTOR(CK_TOP_CB_NET1_D4, "cb_net1_d4", CK_APMIXED_NET1PLL, 1, 4),
- PLL_FACTOR(CK_TOP_CB_NET1_D5, "cb_net1_d5", CK_APMIXED_NET1PLL, 1, 5),
- PLL_FACTOR(CK_TOP_NET1_D5_D2, "net1_d5_d2", CK_APMIXED_NET1PLL, 1, 10),
- PLL_FACTOR(CK_TOP_NET1_D5_D4, "net1_d5_d4", CK_APMIXED_NET1PLL, 1, 20),
- PLL_FACTOR(CK_TOP_CB_NET1_D8, "cb_net1_d8", CK_APMIXED_NET1PLL, 1, 8),
- PLL_FACTOR(CK_TOP_NET1_D8_D2, "net1_d8_d2", CK_APMIXED_NET1PLL, 1, 16),
- PLL_FACTOR(CK_TOP_NET1_D8_D4, "net1_d8_d4", CK_APMIXED_NET1PLL, 1, 32),
- PLL_FACTOR(CK_TOP_CB_NET2_800M, "cb_net2_800m", CK_APMIXED_NET2PLL, 1,
+ PLL_FACTOR(CLK_TOP_APLL2_D2, "apll2_d2", CLK_APMIXED_APLL2, 1, 2),
+ PLL_FACTOR(CLK_TOP_APLL2_D4, "apll2_d4", CLK_APMIXED_APLL2, 1, 4),
+ PLL_FACTOR(CLK_TOP_NET1_2500M, "net1_2500m", CLK_APMIXED_NET1PLL, 1, 1),
+ PLL_FACTOR(CLK_TOP_CB_NET1_D4, "cb_net1_d4", CLK_APMIXED_NET1PLL, 1, 4),
+ PLL_FACTOR(CLK_TOP_CB_NET1_D5, "cb_net1_d5", CLK_APMIXED_NET1PLL, 1, 5),
+ PLL_FACTOR(CLK_TOP_NET1_D5_D2, "net1_d5_d2", CLK_APMIXED_NET1PLL, 1, 10),
+ PLL_FACTOR(CLK_TOP_NET1_D5_D4, "net1_d5_d4", CLK_APMIXED_NET1PLL, 1, 20),
+ PLL_FACTOR(CLK_TOP_CB_NET1_D8, "cb_net1_d8", CLK_APMIXED_NET1PLL, 1, 8),
+ PLL_FACTOR(CLK_TOP_NET1_D8_D2, "net1_d8_d2", CLK_APMIXED_NET1PLL, 1, 16),
+ PLL_FACTOR(CLK_TOP_NET1_D8_D4, "net1_d8_d4", CLK_APMIXED_NET1PLL, 1, 32),
+ PLL_FACTOR(CLK_TOP_CB_NET2_800M, "cb_net2_800m", CLK_APMIXED_NET2PLL, 1,
1),
- PLL_FACTOR(CK_TOP_CB_NET2_D2, "cb_net2_d2", CK_APMIXED_NET2PLL, 1, 2),
- PLL_FACTOR(CK_TOP_CB_NET2_D4, "cb_net2_d4", CK_APMIXED_NET2PLL, 1, 4),
- PLL_FACTOR(CK_TOP_NET2_D4_D2, "net2_d4_d2", CK_APMIXED_NET2PLL, 1, 8),
- PLL_FACTOR(CK_TOP_NET2_D4_D4, "net2_d4_d4", CK_APMIXED_NET2PLL, 1, 16),
- PLL_FACTOR(CK_TOP_CB_NET2_D6, "cb_net2_d6", CK_APMIXED_NET2PLL, 1, 6),
- PLL_FACTOR(CK_TOP_CB_WEDMCU_208M, "cb_wedmcu_208m",
- CK_APMIXED_WEDMCUPLL, 1, 1),
- PLL_FACTOR(CK_TOP_CB_SGM_325M, "cb_sgm_325m", CK_APMIXED_SGMPLL, 1, 1),
- TOP_FACTOR(CK_TOP_CKSQ_40M_D2, "cksq_40m_d2", CK_TOP_CB_CKSQ_40M, 1, 2),
- TOP_FACTOR(CK_TOP_CB_RTC_32K, "cb_rtc_32k", CK_TOP_CB_CKSQ_40M, 1,
+ PLL_FACTOR(CLK_TOP_CB_NET2_D2, "cb_net2_d2", CLK_APMIXED_NET2PLL, 1, 2),
+ PLL_FACTOR(CLK_TOP_CB_NET2_D4, "cb_net2_d4", CLK_APMIXED_NET2PLL, 1, 4),
+ PLL_FACTOR(CLK_TOP_NET2_D4_D2, "net2_d4_d2", CLK_APMIXED_NET2PLL, 1, 8),
+ PLL_FACTOR(CLK_TOP_NET2_D4_D4, "net2_d4_d4", CLK_APMIXED_NET2PLL, 1, 16),
+ PLL_FACTOR(CLK_TOP_CB_NET2_D6, "cb_net2_d6", CLK_APMIXED_NET2PLL, 1, 6),
+ PLL_FACTOR(CLK_TOP_CB_WEDMCU_208M, "cb_wedmcu_208m",
+ CLK_APMIXED_WEDMCUPLL, 1, 1),
+ PLL_FACTOR(CLK_TOP_CB_SGM_325M, "cb_sgm_325m", CLK_APMIXED_SGMPLL, 1, 1),
+ TOP_FACTOR(CLK_TOP_CKSQ_40M_D2, "cksq_40m_d2", CLK_TOP_CB_CKSQ_40M, 1, 2),
+ TOP_FACTOR(CLK_TOP_CB_RTC_32K, "cb_rtc_32k", CLK_TOP_CB_CKSQ_40M, 1,
1250),
- TOP_FACTOR(CK_TOP_CB_RTC_32P7K, "cb_rtc_32p7k", CK_TOP_CB_CKSQ_40M, 1,
+ TOP_FACTOR(CLK_TOP_CB_RTC_32P7K, "cb_rtc_32p7k", CLK_TOP_CB_CKSQ_40M, 1,
1220),
- TOP_FACTOR(CK_TOP_USB_TX250M, "usb_tx250m", CK_TOP_CB_CKSQ_40M, 1, 1),
- TOP_FACTOR(CK_TOP_FAUD, "faud", CK_TOP_CB_CKSQ_40M, 1, 1),
- TOP_FACTOR(CK_TOP_NFI1X, "nfi1x", CK_TOP_NFI1X_SEL, 1, 1),
- TOP_FACTOR(CK_TOP_USB_EQ_RX250M, "usb_eq_rx250m", CK_TOP_CB_CKSQ_40M, 1,
+ TOP_FACTOR(CLK_TOP_USB_TX250M, "usb_tx250m", CLK_TOP_CB_CKSQ_40M, 1, 1),
+ TOP_FACTOR(CLK_TOP_FAUD, "faud", CLK_TOP_AUD_SEL, 1, 1),
+ TOP_FACTOR(CLK_TOP_NFI1X, "nfi1x", CLK_TOP_NFI1X_SEL, 1, 1),
+ TOP_FACTOR(CLK_TOP_USB_EQ_RX250M, "usb_eq_rx250m", CLK_TOP_CB_CKSQ_40M, 1,
1),
- TOP_FACTOR(CK_TOP_USB_CDR_CK, "usb_cdr", CK_TOP_CB_CKSQ_40M, 1, 1),
- TOP_FACTOR(CK_TOP_USB_LN0_CK, "usb_ln0", CK_TOP_CB_CKSQ_40M, 1, 1),
- TOP_FACTOR(CK_TOP_SPINFI_BCK, "spinfi_bck", CK_TOP_SPINFI_SEL, 1, 1),
- TOP_FACTOR(CK_TOP_SPI, "spi", CK_TOP_SPI_SEL, 1, 1),
- TOP_FACTOR(CK_TOP_SPIM_MST, "spim_mst", CK_TOP_SPIM_MST_SEL, 1, 1),
- TOP_FACTOR(CK_TOP_UART_BCK, "uart_bck", CK_TOP_UART_SEL, 1, 1),
- TOP_FACTOR(CK_TOP_PWM_BCK, "pwm_bck", CK_TOP_PWM_SEL, 1, 1),
- TOP_FACTOR(CK_TOP_I2C_BCK, "i2c_bck", CK_TOP_I2C_SEL, 1, 1),
- TOP_FACTOR(CK_TOP_PEXTP_TL, "pextp_tl", CK_TOP_PEXTP_TL_SEL, 1, 1),
- TOP_FACTOR(CK_TOP_EMMC_208M, "emmc_208m", CK_TOP_EMMC_208M_SEL, 1, 1),
- TOP_FACTOR(CK_TOP_EMMC_400M, "emmc_400m", CK_TOP_EMMC_400M_SEL, 1, 1),
- TOP_FACTOR(CK_TOP_DRAMC_REF, "dramc_ref", CK_TOP_DRAMC_SEL, 1, 1),
- TOP_FACTOR(CK_TOP_DRAMC_MD32, "dramc_md32", CK_TOP_DRAMC_MD32_SEL, 1,
+ TOP_FACTOR(CLK_TOP_USB_CDR_CK, "usb_cdr", CLK_TOP_CB_CKSQ_40M, 1, 1),
+ TOP_FACTOR(CLK_TOP_USB_LN0_CK, "usb_ln0", CLK_TOP_CB_CKSQ_40M, 1, 1),
+ TOP_FACTOR(CLK_TOP_SPINFI_BCK, "spinfi_bck", CLK_TOP_SPINFI_SEL, 1, 1),
+ TOP_FACTOR(CLK_TOP_SPI, "spi", CLK_TOP_SPI_SEL, 1, 1),
+ TOP_FACTOR(CLK_TOP_SPIM_MST, "spim_mst", CLK_TOP_SPIM_MST_SEL, 1, 1),
+ TOP_FACTOR(CLK_TOP_UART_BCK, "uart_bck", CLK_TOP_UART_SEL, 1, 1),
+ TOP_FACTOR(CLK_TOP_PWM_BCK, "pwm_bck", CLK_TOP_PWM_SEL, 1, 1),
+ TOP_FACTOR(CLK_TOP_I2C_BCK, "i2c_bck", CLK_TOP_I2C_SEL, 1, 1),
+ TOP_FACTOR(CLK_TOP_PEXTP_TL, "pextp_tl", CLK_TOP_PEXTP_TL_SEL, 1, 1),
+ TOP_FACTOR(CLK_TOP_EMMC_208M, "emmc_208m", CLK_TOP_EMMC_208M_SEL, 1, 1),
+ TOP_FACTOR(CLK_TOP_EMMC_400M, "emmc_400m", CLK_TOP_EMMC_400M_SEL, 1, 1),
+ TOP_FACTOR(CLK_TOP_DRAMC_REF, "dramc_ref", CLK_TOP_DRAMC_SEL, 1, 1),
+ TOP_FACTOR(CLK_TOP_DRAMC_MD32, "dramc_md32", CLK_TOP_DRAMC_MD32_SEL, 1,
1),
- TOP_FACTOR(CK_TOP_SYSAXI, "sysaxi", CK_TOP_SYSAXI_SEL, 1, 1),
- TOP_FACTOR(CK_TOP_SYSAPB, "sysapb", CK_TOP_SYSAPB_SEL, 1, 1),
- TOP_FACTOR(CK_TOP_ARM_DB_MAIN, "arm_db_main", CK_TOP_ARM_DB_MAIN_SEL, 1,
+ TOP_FACTOR(CLK_TOP_SYSAXI, "sysaxi", CLK_TOP_SYSAXI_SEL, 1, 1),
+ TOP_FACTOR(CLK_TOP_SYSAPB, "sysapb", CLK_TOP_SYSAPB_SEL, 1, 1),
+ TOP_FACTOR(CLK_TOP_ARM_DB_MAIN, "arm_db_main", CLK_TOP_ARM_DB_MAIN_SEL, 1,
1),
- TOP_FACTOR(CK_TOP_AP2CNN_HOST, "ap2cnn_host", CK_TOP_AP2CNN_HOST_SEL, 1,
+ TOP_FACTOR(CLK_TOP_AP2CNN_HOST, "ap2cnn_host", CLK_TOP_AP2CNN_HOST_SEL, 1,
1),
- TOP_FACTOR(CK_TOP_NETSYS, "netsys", CK_TOP_NETSYS_SEL, 1, 1),
- TOP_FACTOR(CK_TOP_NETSYS_500M, "netsys_500m", CK_TOP_NETSYS_500M_SEL, 1,
+ TOP_FACTOR(CLK_TOP_NETSYS, "netsys", CLK_TOP_NETSYS_SEL, 1, 1),
+ TOP_FACTOR(CLK_TOP_NETSYS_500M, "netsys_500m", CLK_TOP_NETSYS_500M_SEL, 1,
1),
- TOP_FACTOR(CK_TOP_NETSYS_WED_MCU, "netsys_wed_mcu",
- CK_TOP_NETSYS_MCU_SEL, 1, 1),
- TOP_FACTOR(CK_TOP_NETSYS_2X, "netsys_2x", CK_TOP_NETSYS_2X_SEL, 1, 1),
- TOP_FACTOR(CK_TOP_SGM_325M, "sgm_325m", CK_TOP_SGM_325M_SEL, 1, 1),
- TOP_FACTOR(CK_TOP_SGM_REG, "sgm_reg", CK_TOP_SGM_REG_SEL, 1, 1),
- TOP_FACTOR(CK_TOP_F26M, "csw_f26m", CK_TOP_F26M_SEL, 1, 1),
- TOP_FACTOR(CK_TOP_EIP97B, "eip97b", CK_TOP_EIP97B_SEL, 1, 1),
- TOP_FACTOR(CK_TOP_USB3_PHY, "usb3_phy", CK_TOP_USB3_PHY_SEL, 1, 1),
- TOP_FACTOR(CK_TOP_AUD, "aud", CK_TOP_FAUD, 1, 1),
- TOP_FACTOR(CK_TOP_A1SYS, "a1sys", CK_TOP_A1SYS_SEL, 1, 1),
- TOP_FACTOR(CK_TOP_AUD_L, "aud_l", CK_TOP_AUD_L_SEL, 1, 1),
- TOP_FACTOR(CK_TOP_A_TUNER, "a_tuner", CK_TOP_A_TUNER_SEL, 1, 1),
- TOP_FACTOR(CK_TOP_U2U3_REF, "u2u3_ref", CK_TOP_U2U3_SEL, 1, 1),
- TOP_FACTOR(CK_TOP_U2U3_SYS, "u2u3_sys", CK_TOP_U2U3_SYS_SEL, 1, 1),
- TOP_FACTOR(CK_TOP_U2U3_XHCI, "u2u3_xhci", CK_TOP_U2U3_XHCI_SEL, 1, 1),
- TOP_FACTOR(CK_TOP_USB_FRMCNT, "usb_frmcnt", CK_TOP_USB_FRMCNT_SEL, 1,
+ TOP_FACTOR(CLK_TOP_NETSYS_WED_MCU, "netsys_wed_mcu",
+ CLK_TOP_NETSYS_MCU_SEL, 1, 1),
+ TOP_FACTOR(CLK_TOP_NETSYS_2X, "netsys_2x", CLK_TOP_NETSYS_2X_SEL, 1, 1),
+ TOP_FACTOR(CLK_TOP_SGM_325M, "sgm_325m", CLK_TOP_SGM_325M_SEL, 1, 1),
+ TOP_FACTOR(CLK_TOP_SGM_REG, "sgm_reg", CLK_TOP_SGM_REG_SEL, 1, 1),
+ TOP_FACTOR(CLK_TOP_F26M, "csw_f26m", CLK_TOP_F26M_SEL, 1, 1),
+ TOP_FACTOR(CLK_TOP_EIP97B, "eip97b", CLK_TOP_EIP97B_SEL, 1, 1),
+ TOP_FACTOR(CLK_TOP_USB3_PHY, "usb3_phy", CLK_TOP_USB3_PHY_SEL, 1, 1),
+ TOP_FACTOR(CLK_TOP_AUD, "aud", CLK_TOP_FAUD, 1, 1),
+ TOP_FACTOR(CLK_TOP_A1SYS, "a1sys", CLK_TOP_A1SYS_SEL, 1, 1),
+ TOP_FACTOR(CLK_TOP_AUD_L, "aud_l", CLK_TOP_AUD_L_SEL, 1, 1),
+ TOP_FACTOR(CLK_TOP_A_TUNER, "a_tuner", CLK_TOP_A_TUNER_SEL, 1, 1),
+ TOP_FACTOR(CLK_TOP_U2U3_REF, "u2u3_ref", CLK_TOP_U2U3_SEL, 1, 1),
+ TOP_FACTOR(CLK_TOP_U2U3_SYS, "u2u3_sys", CLK_TOP_U2U3_SYS_SEL, 1, 1),
+ TOP_FACTOR(CLK_TOP_U2U3_XHCI, "u2u3_xhci", CLK_TOP_U2U3_XHCI_SEL, 1, 1),
+ TOP_FACTOR(CLK_TOP_USB_FRMCNT, "usb_frmcnt", CLK_TOP_USB_FRMCNT_SEL, 1,
1),
};
/* TOPCKGEN MUX PARENTS */
-static const int nfi1x_parents[] = { CK_TOP_CB_CKSQ_40M, CK_TOP_CB_MM_D4,
- CK_TOP_NET1_D8_D2, CK_TOP_CB_NET2_D6,
- CK_TOP_CB_M_D4, CK_TOP_CB_MM_D8,
- CK_TOP_NET1_D8_D4, CK_TOP_CB_M_D8 };
+static const int nfi1x_parents[] = { CLK_TOP_CB_CKSQ_40M, CLK_TOP_CB_MM_D4,
+ CLK_TOP_NET1_D8_D2, CLK_TOP_CB_NET2_D6,
+ CLK_TOP_CB_M_D4, CLK_TOP_CB_MM_D8,
+ CLK_TOP_NET1_D8_D4, CLK_TOP_CB_M_D8 };
-static const int spinfi_parents[] = { CK_TOP_CKSQ_40M_D2, CK_TOP_CB_CKSQ_40M,
- CK_TOP_NET1_D5_D4, CK_TOP_CB_M_D4,
- CK_TOP_CB_MM_D8, CK_TOP_NET1_D8_D4,
- CK_TOP_MM_D6_D2, CK_TOP_CB_M_D8 };
+static const int spinfi_parents[] = { CLK_TOP_CKSQ_40M_D2, CLK_TOP_CB_CKSQ_40M,
+ CLK_TOP_NET1_D5_D4, CLK_TOP_CB_M_D4,
+ CLK_TOP_CB_MM_D8, CLK_TOP_NET1_D8_D4,
+ CLK_TOP_MM_D6_D2, CLK_TOP_CB_M_D8 };
-static const int spi_parents[] = { CK_TOP_CB_CKSQ_40M, CK_TOP_CB_M_D2,
- CK_TOP_CB_MM_D4, CK_TOP_NET1_D8_D2,
- CK_TOP_CB_NET2_D6, CK_TOP_NET1_D5_D4,
- CK_TOP_CB_M_D4, CK_TOP_NET1_D8_D4 };
+static const int spi_parents[] = { CLK_TOP_CB_CKSQ_40M, CLK_TOP_CB_M_D2,
+ CLK_TOP_CB_MM_D4, CLK_TOP_NET1_D8_D2,
+ CLK_TOP_CB_NET2_D6, CLK_TOP_NET1_D5_D4,
+ CLK_TOP_CB_M_D4, CLK_TOP_NET1_D8_D4 };
-static const int uart_parents[] = { CK_TOP_CB_CKSQ_40M, CK_TOP_CB_M_D8,
- CK_TOP_M_D8_D2 };
+static const int uart_parents[] = { CLK_TOP_CB_CKSQ_40M, CLK_TOP_CB_M_D8,
+ CLK_TOP_M_D8_D2 };
-static const int pwm_parents[] = { CK_TOP_CB_CKSQ_40M, CK_TOP_NET1_D8_D2,
- CK_TOP_NET1_D5_D4, CK_TOP_CB_M_D4,
- CK_TOP_M_D8_D2, CK_TOP_CB_RTC_32K };
+static const int pwm_parents[] = { CLK_TOP_CB_CKSQ_40M, CLK_TOP_NET1_D8_D2,
+ CLK_TOP_NET1_D5_D4, CLK_TOP_CB_M_D4,
+ CLK_TOP_M_D8_D2, CLK_TOP_CB_RTC_32K };
-static const int i2c_parents[] = { CK_TOP_CB_CKSQ_40M, CK_TOP_NET1_D5_D4,
- CK_TOP_CB_M_D4, CK_TOP_NET1_D8_D4 };
+static const int i2c_parents[] = { CLK_TOP_CB_CKSQ_40M, CLK_TOP_NET1_D5_D4,
+ CLK_TOP_CB_M_D4, CLK_TOP_NET1_D8_D4 };
-static const int pextp_tl_ck_parents[] = { CK_TOP_CB_CKSQ_40M,
- CK_TOP_NET1_D5_D4, CK_TOP_CB_M_D4,
- CK_TOP_CB_RTC_32K };
+static const int pextp_tl_ck_parents[] = { CLK_TOP_CB_CKSQ_40M,
+ CLK_TOP_NET1_D5_D4, CLK_TOP_CB_M_D4,
+ CLK_TOP_CB_RTC_32K };
static const int emmc_208m_parents[] = {
- CK_TOP_CB_CKSQ_40M, CK_TOP_CB_M_D2, CK_TOP_CB_NET2_D4,
- CK_TOP_CB_APLL2_196M, CK_TOP_CB_MM_D4, CK_TOP_NET1_D8_D2,
- CK_TOP_CB_MM_D6
+ CLK_TOP_CB_CKSQ_40M, CLK_TOP_CB_M_D2, CLK_TOP_CB_NET2_D4,
+ CLK_TOP_CB_APLL2_196M, CLK_TOP_CB_MM_D4, CLK_TOP_NET1_D8_D2,
+ CLK_TOP_CB_MM_D6
};
-static const int emmc_400m_parents[] = { CK_TOP_CB_CKSQ_40M, CK_TOP_CB_NET2_D2,
- CK_TOP_CB_MM_D2, CK_TOP_CB_NET2_D2 };
+static const int emmc_400m_parents[] = { CLK_TOP_CB_CKSQ_40M, CLK_TOP_CB_NET2_D2,
+ CLK_TOP_CB_MM_D2, CLK_TOP_CB_NET2_D2 };
-static const int csw_f26m_parents[] = { CK_TOP_CKSQ_40M_D2, CK_TOP_M_D8_D2 };
+static const int csw_f26m_parents[] = { CLK_TOP_CKSQ_40M_D2, CLK_TOP_M_D8_D2 };
-static const int dramc_md32_parents[] = { CK_TOP_CB_CKSQ_40M, CK_TOP_CB_M_D2,
- CK_TOP_CB_WEDMCU_208M };
+static const int dramc_md32_parents[] = { CLK_TOP_CB_CKSQ_40M, CLK_TOP_CB_M_D2,
+ CLK_TOP_CB_WEDMCU_208M };
-static const int sysaxi_parents[] = { CK_TOP_CB_CKSQ_40M, CK_TOP_NET1_D8_D2 };
+static const int sysaxi_parents[] = { CLK_TOP_CB_CKSQ_40M, CLK_TOP_NET1_D8_D2 };
-static const int sysapb_parents[] = { CK_TOP_CB_CKSQ_40M, CK_TOP_M_D3_D2 };
+static const int sysapb_parents[] = { CLK_TOP_CB_CKSQ_40M, CLK_TOP_M_D3_D2 };
-static const int arm_db_main_parents[] = { CK_TOP_CB_CKSQ_40M,
- CK_TOP_CB_NET2_D6 };
+static const int arm_db_main_parents[] = { CLK_TOP_CB_CKSQ_40M,
+ CLK_TOP_CB_NET2_D6 };
-static const int ap2cnn_host_parents[] = { CK_TOP_CB_CKSQ_40M,
- CK_TOP_NET1_D8_D4 };
+static const int ap2cnn_host_parents[] = { CLK_TOP_CB_CKSQ_40M,
+ CLK_TOP_NET1_D8_D4 };
-static const int netsys_parents[] = { CK_TOP_CB_CKSQ_40M, CK_TOP_CB_MM_D2 };
+static const int netsys_parents[] = { CLK_TOP_CB_CKSQ_40M, CLK_TOP_CB_MM_D2 };
-static const int netsys_500m_parents[] = { CK_TOP_CB_CKSQ_40M,
- CK_TOP_CB_NET1_D5 };
+static const int netsys_500m_parents[] = { CLK_TOP_CB_CKSQ_40M,
+ CLK_TOP_CB_NET1_D5 };
-static const int netsys_mcu_parents[] = { CK_TOP_CB_CKSQ_40M, CK_TOP_CB_MM_720M,
- CK_TOP_CB_NET1_D4, CK_TOP_CB_NET1_D5,
- CK_TOP_CB_M_416M };
+static const int netsys_mcu_parents[] = { CLK_TOP_CB_CKSQ_40M, CLK_TOP_CB_MM_720M,
+ CLK_TOP_CB_NET1_D4, CLK_TOP_CB_NET1_D5,
+ CLK_TOP_CB_M_416M };
-static const int netsys_2x_parents[] = { CK_TOP_CB_CKSQ_40M,
- CK_TOP_CB_NET2_800M,
- CK_TOP_CB_MM_720M };
+static const int netsys_2x_parents[] = { CLK_TOP_CB_CKSQ_40M,
+ CLK_TOP_CB_NET2_800M,
+ CLK_TOP_CB_MM_720M };
-static const int sgm_325m_parents[] = { CK_TOP_CB_CKSQ_40M,
- CK_TOP_CB_SGM_325M };
+static const int sgm_325m_parents[] = { CLK_TOP_CB_CKSQ_40M,
+ CLK_TOP_CB_SGM_325M };
-static const int sgm_reg_parents[] = { CK_TOP_CB_CKSQ_40M, CK_TOP_CB_NET2_D4 };
+static const int sgm_reg_parents[] = { CLK_TOP_CB_CKSQ_40M, CLK_TOP_CB_NET2_D4 };
-static const int eip97b_parents[] = { CK_TOP_CB_CKSQ_40M, CK_TOP_CB_NET1_D5,
- CK_TOP_CB_M_416M, CK_TOP_CB_MM_D2,
- CK_TOP_NET1_D5_D2 };
+static const int eip97b_parents[] = { CLK_TOP_CB_CKSQ_40M, CLK_TOP_CB_NET1_D5,
+ CLK_TOP_CB_M_416M, CLK_TOP_CB_MM_D2,
+ CLK_TOP_NET1_D5_D2 };
-static const int aud_parents[] = { CK_TOP_CB_CKSQ_40M, CK_TOP_CB_APLL2_196M };
+static const int aud_parents[] = { CLK_TOP_CB_CKSQ_40M, CLK_TOP_CB_APLL2_196M };
-static const int a1sys_parents[] = { CK_TOP_CB_CKSQ_40M, CK_TOP_APLL2_D4 };
+static const int a1sys_parents[] = { CLK_TOP_CB_CKSQ_40M, CLK_TOP_APLL2_D4 };
-static const int aud_l_parents[] = { CK_TOP_CB_CKSQ_40M, CK_TOP_CB_APLL2_196M,
- CK_TOP_M_D8_D2 };
+static const int aud_l_parents[] = { CLK_TOP_CB_CKSQ_40M, CLK_TOP_CB_APLL2_196M,
+ CLK_TOP_M_D8_D2 };
-static const int a_tuner_parents[] = { CK_TOP_CB_CKSQ_40M, CK_TOP_APLL2_D4,
- CK_TOP_M_D8_D2 };
+static const int a_tuner_parents[] = { CLK_TOP_CB_CKSQ_40M, CLK_TOP_APLL2_D4,
+ CLK_TOP_M_D8_D2 };
-static const int u2u3_parents[] = { CK_TOP_CB_CKSQ_40M, CK_TOP_M_D8_D2 };
+static const int u2u3_parents[] = { CLK_TOP_CB_CKSQ_40M, CLK_TOP_M_D8_D2 };
-static const int u2u3_sys_parents[] = { CK_TOP_CB_CKSQ_40M, CK_TOP_NET1_D5_D4 };
+static const int u2u3_sys_parents[] = { CLK_TOP_CB_CKSQ_40M, CLK_TOP_NET1_D5_D4 };
-static const int usb_frmcnt_parents[] = { CK_TOP_CB_CKSQ_40M,
- CK_TOP_CB_MM_D3_D5 };
+static const int usb_frmcnt_parents[] = { CLK_TOP_CB_CKSQ_40M,
+ CLK_TOP_CB_MM_D3_D5 };
#define TOP_MUX(_id, _name, _parents, _mux_ofs, _mux_set_ofs, _mux_clr_ofs, \
_shift, _width, _gate, _upd_ofs, _upd) \
@@ -242,174 +242,150 @@
/* TOPCKGEN MUX_GATE */
static const struct mtk_composite top_muxes[] = {
- TOP_MUX(CK_TOP_NFI1X_SEL, "nfi1x_sel", nfi1x_parents, 0x0, 0x4, 0x8, 0,
+ TOP_MUX(CLK_TOP_NFI1X_SEL, "nfi1x_sel", nfi1x_parents, 0x0, 0x4, 0x8, 0,
3, 7, 0x1c0, 0),
- TOP_MUX(CK_TOP_SPINFI_SEL, "spinfi_sel", spinfi_parents, 0x0, 0x4, 0x8,
+ TOP_MUX(CLK_TOP_SPINFI_SEL, "spinfi_sel", spinfi_parents, 0x0, 0x4, 0x8,
8, 3, 15, 0x1c0, 1),
- TOP_MUX(CK_TOP_SPI_SEL, "spi_sel", spi_parents, 0x0, 0x4, 0x8, 16, 3,
+ TOP_MUX(CLK_TOP_SPI_SEL, "spi_sel", spi_parents, 0x0, 0x4, 0x8, 16, 3,
23, 0x1c0, 2),
- TOP_MUX(CK_TOP_SPIM_MST_SEL, "spim_mst_sel", spi_parents, 0x0, 0x4, 0x8,
+ TOP_MUX(CLK_TOP_SPIM_MST_SEL, "spim_mst_sel", spi_parents, 0x0, 0x4, 0x8,
24, 3, 31, 0x1c0, 3),
- TOP_MUX(CK_TOP_UART_SEL, "uart_sel", uart_parents, 0x10, 0x14, 0x18, 0,
+ TOP_MUX(CLK_TOP_UART_SEL, "uart_sel", uart_parents, 0x10, 0x14, 0x18, 0,
2, 7, 0x1c0, 4),
- TOP_MUX(CK_TOP_PWM_SEL, "pwm_sel", pwm_parents, 0x10, 0x14, 0x18, 8, 3,
+ TOP_MUX(CLK_TOP_PWM_SEL, "pwm_sel", pwm_parents, 0x10, 0x14, 0x18, 8, 3,
15, 0x1c0, 5),
- TOP_MUX(CK_TOP_I2C_SEL, "i2c_sel", i2c_parents, 0x10, 0x14, 0x18, 16, 2,
+ TOP_MUX(CLK_TOP_I2C_SEL, "i2c_sel", i2c_parents, 0x10, 0x14, 0x18, 16, 2,
23, 0x1c0, 6),
- TOP_MUX(CK_TOP_PEXTP_TL_SEL, "pextp_tl_ck_sel", pextp_tl_ck_parents,
+ TOP_MUX(CLK_TOP_PEXTP_TL_SEL, "pextp_tl_ck_sel", pextp_tl_ck_parents,
0x10, 0x14, 0x18, 24, 2, 31, 0x1c0, 7),
- TOP_MUX(CK_TOP_EMMC_208M_SEL, "emmc_208m_sel", emmc_208m_parents, 0x20,
+ TOP_MUX(CLK_TOP_EMMC_208M_SEL, "emmc_208m_sel", emmc_208m_parents, 0x20,
0x24, 0x28, 0, 3, 7, 0x1c0, 8),
- TOP_MUX(CK_TOP_EMMC_400M_SEL, "emmc_400m_sel", emmc_400m_parents, 0x20,
+ TOP_MUX(CLK_TOP_EMMC_400M_SEL, "emmc_400m_sel", emmc_400m_parents, 0x20,
0x24, 0x28, 8, 2, 15, 0x1c0, 9),
- TOP_MUX(CK_TOP_F26M_SEL, "csw_f26m_sel", csw_f26m_parents, 0x20, 0x24,
+ TOP_MUX(CLK_TOP_F26M_SEL, "csw_f26m_sel", csw_f26m_parents, 0x20, 0x24,
0x28, 16, 1, 23, 0x1c0, 10),
- TOP_MUX(CK_TOP_DRAMC_SEL, "dramc_sel", csw_f26m_parents, 0x20, 0x24,
+ TOP_MUX(CLK_TOP_DRAMC_SEL, "dramc_sel", csw_f26m_parents, 0x20, 0x24,
0x28, 24, 1, 31, 0x1c0, 11),
- TOP_MUX(CK_TOP_DRAMC_MD32_SEL, "dramc_md32_sel", dramc_md32_parents,
+ TOP_MUX(CLK_TOP_DRAMC_MD32_SEL, "dramc_md32_sel", dramc_md32_parents,
0x30, 0x34, 0x38, 0, 2, 7, 0x1c0, 12),
- TOP_MUX(CK_TOP_SYSAXI_SEL, "sysaxi_sel", sysaxi_parents, 0x30, 0x34,
+ TOP_MUX(CLK_TOP_SYSAXI_SEL, "sysaxi_sel", sysaxi_parents, 0x30, 0x34,
0x38, 8, 1, 15, 0x1c0, 13),
- TOP_MUX(CK_TOP_SYSAPB_SEL, "sysapb_sel", sysapb_parents, 0x30, 0x34,
+ TOP_MUX(CLK_TOP_SYSAPB_SEL, "sysapb_sel", sysapb_parents, 0x30, 0x34,
0x38, 16, 1, 23, 0x1c0, 14),
- TOP_MUX(CK_TOP_ARM_DB_MAIN_SEL, "arm_db_main_sel", arm_db_main_parents,
+ TOP_MUX(CLK_TOP_ARM_DB_MAIN_SEL, "arm_db_main_sel", arm_db_main_parents,
0x30, 0x34, 0x38, 24, 1, 31, 0x1c0, 15),
- TOP_MUX(CK_TOP_AP2CNN_HOST_SEL, "ap2cnn_host_sel", ap2cnn_host_parents,
+ TOP_MUX(CLK_TOP_AP2CNN_HOST_SEL, "ap2cnn_host_sel", ap2cnn_host_parents,
0x40, 0x44, 0x48, 0, 1, 7, 0x1c0, 16),
- TOP_MUX(CK_TOP_NETSYS_SEL, "netsys_sel", netsys_parents, 0x40, 0x44,
+ TOP_MUX(CLK_TOP_NETSYS_SEL, "netsys_sel", netsys_parents, 0x40, 0x44,
0x48, 8, 1, 15, 0x1c0, 17),
- TOP_MUX(CK_TOP_NETSYS_500M_SEL, "netsys_500m_sel", netsys_500m_parents,
+ TOP_MUX(CLK_TOP_NETSYS_500M_SEL, "netsys_500m_sel", netsys_500m_parents,
0x40, 0x44, 0x48, 16, 1, 23, 0x1c0, 18),
- TOP_MUX(CK_TOP_NETSYS_MCU_SEL, "netsys_mcu_sel", netsys_mcu_parents,
+ TOP_MUX(CLK_TOP_NETSYS_MCU_SEL, "netsys_mcu_sel", netsys_mcu_parents,
0x40, 0x44, 0x48, 24, 3, 31, 0x1c0, 19),
- TOP_MUX(CK_TOP_NETSYS_2X_SEL, "netsys_2x_sel", netsys_2x_parents, 0x50,
+ TOP_MUX(CLK_TOP_NETSYS_2X_SEL, "netsys_2x_sel", netsys_2x_parents, 0x50,
0x54, 0x58, 0, 2, 7, 0x1c0, 20),
- TOP_MUX(CK_TOP_SGM_325M_SEL, "sgm_325m_sel", sgm_325m_parents, 0x50,
+ TOP_MUX(CLK_TOP_SGM_325M_SEL, "sgm_325m_sel", sgm_325m_parents, 0x50,
0x54, 0x58, 8, 1, 15, 0x1c0, 21),
- TOP_MUX(CK_TOP_SGM_REG_SEL, "sgm_reg_sel", sgm_reg_parents, 0x50, 0x54,
+ TOP_MUX(CLK_TOP_SGM_REG_SEL, "sgm_reg_sel", sgm_reg_parents, 0x50, 0x54,
0x58, 16, 1, 23, 0x1c0, 22),
- TOP_MUX(CK_TOP_EIP97B_SEL, "eip97b_sel", eip97b_parents, 0x50, 0x54,
+ TOP_MUX(CLK_TOP_EIP97B_SEL, "eip97b_sel", eip97b_parents, 0x50, 0x54,
0x58, 24, 3, 31, 0x1c0, 23),
- TOP_MUX(CK_TOP_USB3_PHY_SEL, "usb3_phy_sel", csw_f26m_parents, 0x60,
+ TOP_MUX(CLK_TOP_USB3_PHY_SEL, "usb3_phy_sel", csw_f26m_parents, 0x60,
0x64, 0x68, 0, 1, 7, 0x1c0, 24),
- TOP_MUX(CK_TOP_AUD_SEL, "aud_sel", aud_parents, 0x60, 0x64, 0x68, 8, 1,
+ TOP_MUX(CLK_TOP_AUD_SEL, "aud_sel", aud_parents, 0x60, 0x64, 0x68, 8, 1,
15, 0x1c0, 25),
- TOP_MUX(CK_TOP_A1SYS_SEL, "a1sys_sel", a1sys_parents, 0x60, 0x64, 0x68,
+ TOP_MUX(CLK_TOP_A1SYS_SEL, "a1sys_sel", a1sys_parents, 0x60, 0x64, 0x68,
16, 1, 23, 0x1c0, 26),
- TOP_MUX(CK_TOP_AUD_L_SEL, "aud_l_sel", aud_l_parents, 0x60, 0x64, 0x68,
+ TOP_MUX(CLK_TOP_AUD_L_SEL, "aud_l_sel", aud_l_parents, 0x60, 0x64, 0x68,
24, 2, 31, 0x1c0, 27),
- TOP_MUX(CK_TOP_A_TUNER_SEL, "a_tuner_sel", a_tuner_parents, 0x70, 0x74,
+ TOP_MUX(CLK_TOP_A_TUNER_SEL, "a_tuner_sel", a_tuner_parents, 0x70, 0x74,
0x78, 0, 2, 7, 0x1c0, 28),
- TOP_MUX(CK_TOP_U2U3_SEL, "u2u3_sel", u2u3_parents, 0x70, 0x74, 0x78, 8,
+ TOP_MUX(CLK_TOP_U2U3_SEL, "u2u3_sel", u2u3_parents, 0x70, 0x74, 0x78, 8,
1, 15, 0x1c0, 29),
- TOP_MUX(CK_TOP_U2U3_SYS_SEL, "u2u3_sys_sel", u2u3_sys_parents, 0x70,
+ TOP_MUX(CLK_TOP_U2U3_SYS_SEL, "u2u3_sys_sel", u2u3_sys_parents, 0x70,
0x74, 0x78, 16, 1, 23, 0x1c0, 30),
- TOP_MUX(CK_TOP_U2U3_XHCI_SEL, "u2u3_xhci_sel", u2u3_sys_parents, 0x70,
+ TOP_MUX(CLK_TOP_U2U3_XHCI_SEL, "u2u3_xhci_sel", u2u3_sys_parents, 0x70,
0x74, 0x78, 24, 1, 31, 0x1c4, 0),
- TOP_MUX(CK_TOP_USB_FRMCNT_SEL, "usb_frmcnt_sel", usb_frmcnt_parents,
+ TOP_MUX(CLK_TOP_USB_FRMCNT_SEL, "usb_frmcnt_sel", usb_frmcnt_parents,
0x80, 0x84, 0x88, 0, 1, 7, 0x1c4, 1),
};
/* INFRA FIXED DIV */
static const struct mtk_fixed_factor infra_fixed_divs[] = {
- TOP_FACTOR(CK_INFRA_CK_F26M, "infra_ck_f26m", CK_TOP_F26M_SEL, 1, 1),
- TOP_FACTOR(CK_INFRA_UART, "infra_uart", CK_TOP_UART_SEL, 1, 1),
- TOP_FACTOR(CK_INFRA_ISPI0, "infra_ispi0", CK_TOP_SPI_SEL, 1, 1),
- TOP_FACTOR(CK_INFRA_I2C, "infra_i2c", CK_TOP_I2C_SEL, 1, 1),
- TOP_FACTOR(CK_INFRA_ISPI1, "infra_ispi1", CK_TOP_SPIM_MST_SEL, 1, 1),
- TOP_FACTOR(CK_INFRA_PWM, "infra_pwm", CK_TOP_PWM_SEL, 1, 1),
- TOP_FACTOR(CK_INFRA_66M_MCK, "infra_66m_mck", CK_TOP_SYSAXI_SEL, 1, 2),
- TOP_FACTOR(CK_INFRA_CK_F32K, "infra_ck_f32k", CK_TOP_CB_RTC_32P7K, 1,
- 1),
- TOP_FACTOR(CK_INFRA_PCIE_CK, "infra_pcie", CK_TOP_PEXTP_TL_SEL, 1, 1),
- INFRA_FACTOR(CK_INFRA_PWM_BCK, "infra_pwm_bck", CK_INFRA_PWM_BSEL, 1,
- 1),
- INFRA_FACTOR(CK_INFRA_PWM_CK1, "infra_pwm_ck1", CK_INFRA_PWM1_SEL, 1,
- 1),
- INFRA_FACTOR(CK_INFRA_PWM_CK2, "infra_pwm_ck2", CK_INFRA_PWM2_SEL, 1,
- 1),
- TOP_FACTOR(CK_INFRA_133M_HCK, "infra_133m_hck", CK_TOP_SYSAXI, 1, 1),
- INFRA_FACTOR(CK_INFRA_66M_PHCK, "infra_66m_phck", CK_INFRA_133M_HCK, 1,
- 1),
- TOP_FACTOR(CK_INFRA_FAUD_L_CK, "infra_faud_l", CK_TOP_AUD_L, 1, 1),
- TOP_FACTOR(CK_INFRA_FAUD_AUD_CK, "infra_faud_aud", CK_TOP_A1SYS, 1, 1),
- TOP_FACTOR(CK_INFRA_FAUD_EG2_CK, "infra_faud_eg2", CK_TOP_A_TUNER, 1,
- 1),
- TOP_FACTOR(CK_INFRA_I2CS_CK, "infra_i2cs", CK_TOP_I2C_BCK, 1, 1),
- INFRA_FACTOR(CK_INFRA_MUX_UART0, "infra_mux_uart0", CK_INFRA_UART0_SEL,
- 1, 1),
- INFRA_FACTOR(CK_INFRA_MUX_UART1, "infra_mux_uart1", CK_INFRA_UART1_SEL,
- 1, 1),
- INFRA_FACTOR(CK_INFRA_MUX_UART2, "infra_mux_uart2", CK_INFRA_UART2_SEL,
- 1, 1),
- TOP_FACTOR(CK_INFRA_NFI_CK, "infra_nfi", CK_TOP_NFI1X, 1, 1),
- TOP_FACTOR(CK_INFRA_SPINFI_CK, "infra_spinfi", CK_TOP_SPINFI_BCK, 1, 1),
- INFRA_FACTOR(CK_INFRA_MUX_SPI0, "infra_mux_spi0", CK_INFRA_SPI0_SEL, 1,
- 1),
- INFRA_FACTOR(CK_INFRA_MUX_SPI1, "infra_mux_spi1", CK_INFRA_SPI1_SEL, 1,
- 1),
- INFRA_FACTOR(CK_INFRA_MUX_SPI2, "infra_mux_spi2", CK_INFRA_SPI2_SEL, 1,
- 1),
- TOP_FACTOR(CK_INFRA_RTC_32K, "infra_rtc_32k", CK_TOP_CB_RTC_32K, 1, 1),
- TOP_FACTOR(CK_INFRA_FMSDC_CK, "infra_fmsdc", CK_TOP_EMMC_400M, 1, 1),
- TOP_FACTOR(CK_INFRA_FMSDC_HCK_CK, "infra_fmsdc_hck", CK_TOP_EMMC_208M,
- 1, 1),
- TOP_FACTOR(CK_INFRA_PERI_133M, "infra_peri_133m", CK_TOP_SYSAXI, 1, 1),
- TOP_FACTOR(CK_INFRA_133M_PHCK, "infra_133m_phck", CK_TOP_SYSAXI, 1, 1),
- TOP_FACTOR(CK_INFRA_USB_SYS_CK, "infra_usb_sys", CK_TOP_U2U3_SYS, 1, 1),
- TOP_FACTOR(CK_INFRA_USB_CK, "infra_usb", CK_TOP_U2U3_REF, 1, 1),
- TOP_FACTOR(CK_INFRA_USB_XHCI_CK, "infra_usb_xhci", CK_TOP_U2U3_XHCI, 1,
- 1),
- TOP_FACTOR(CK_INFRA_PCIE_GFMUX_TL_O_PRE, "infra_pcie_mux",
- CK_TOP_PEXTP_TL, 1, 1),
- TOP_FACTOR(CK_INFRA_F26M_CK0, "infra_f26m_ck0", CK_TOP_F26M, 1, 1),
- TOP_FACTOR(CK_INFRA_133M_MCK, "infra_133m_mck", CK_TOP_SYSAXI, 1, 1),
+ TOP_FACTOR(CLK_INFRA_66M_MCK, "infra_66m_mck", CLK_TOP_SYSAXI_SEL, 1, 2),
};
/* INFRASYS MUX PARENTS */
-static const int infra_uart0_parents[] = { CK_INFRA_CK_F26M, CK_INFRA_UART };
+#define INFRA_PARENT(_id) PARENT(_id, CLK_PARENT_INFRASYS)
+#define TOP_PARENT(_id) PARENT(_id, CLK_PARENT_TOPCKGEN)
+#define VOID_PARENT PARENT(-1, 0)
-static const int infra_spi0_parents[] = { CK_INFRA_I2C, CK_INFRA_ISPI0 };
+static const struct mtk_parent infra_uart0_parents[] = {
+ TOP_PARENT(CLK_TOP_F26M_SEL),
+ TOP_PARENT(CLK_TOP_UART_SEL)
+};
+
+static const struct mtk_parent infra_spi0_parents[] = {
+ TOP_PARENT(CLK_TOP_I2C_SEL),
+ TOP_PARENT(CLK_TOP_SPI_SEL)
+};
-static const int infra_spi1_parents[] = { CK_INFRA_I2C, CK_INFRA_ISPI1 };
+static const struct mtk_parent infra_spi1_parents[] = {
+ TOP_PARENT(CLK_TOP_I2C_SEL),
+ TOP_PARENT(CLK_TOP_SPIM_MST_SEL)
+};
-static const int infra_pwm1_parents[] = { -1, -1, -1, CK_INFRA_PWM };
+static const struct mtk_parent infra_pwm1_parents[] = {
+ VOID_PARENT,
+ TOP_PARENT(CLK_TOP_PWM_SEL)
+};
-static const int infra_pwm_bsel_parents[] = { -1, -1, -1, CK_INFRA_PWM };
+static const struct mtk_parent infra_pwm_bsel_parents[] = {
+ TOP_PARENT(CLK_TOP_CB_RTC_32P7K),
+ TOP_PARENT(CLK_TOP_F26M_SEL),
+ INFRA_PARENT(CLK_INFRA_66M_MCK),
+ TOP_PARENT(CLK_TOP_PWM_SEL)
+};
-static const int infra_pcie_parents[] = { CK_INFRA_CK_F32K, CK_INFRA_CK_F26M,
- CK_TOP_CB_CKSQ_40M, CK_INFRA_PCIE_CK};
+static const struct mtk_parent infra_pcie_parents[] = {
+ TOP_PARENT(CLK_TOP_CB_RTC_32P7K),
+ TOP_PARENT(CLK_TOP_F26M_SEL),
+ TOP_PARENT(CLK_TOP_CB_CKSQ_40M),
+ TOP_PARENT(CLK_TOP_PEXTP_TL_SEL)
+};
#define INFRA_MUX(_id, _name, _parents, _reg, _shift, _width) \
{ \
.id = _id, .mux_reg = (_reg) + 0x8, \
.mux_set_reg = (_reg) + 0x0, .mux_clr_reg = (_reg) + 0x4, \
.mux_shift = _shift, .mux_mask = BIT(_width) - 1, \
- .parent = _parents, .num_parents = ARRAY_SIZE(_parents), \
- .flags = CLK_MUX_SETCLR_UPD | CLK_PARENT_INFRASYS, \
+ .parent_flags = _parents, .num_parents = ARRAY_SIZE(_parents), \
+ .flags = CLK_MUX_SETCLR_UPD | CLK_PARENT_MIXED, \
}
/* INFRA MUX */
static const struct mtk_composite infra_muxes[] = {
- INFRA_MUX(CK_INFRA_UART0_SEL, "infra_uart0_sel", infra_uart0_parents,
+ INFRA_MUX(CLK_INFRA_UART0_SEL, "infra_uart0_sel", infra_uart0_parents,
0x10, 0, 1),
- INFRA_MUX(CK_INFRA_UART1_SEL, "infra_uart1_sel", infra_uart0_parents,
+ INFRA_MUX(CLK_INFRA_UART1_SEL, "infra_uart1_sel", infra_uart0_parents,
0x10, 1, 1),
- INFRA_MUX(CK_INFRA_UART2_SEL, "infra_uart2_sel", infra_uart0_parents,
+ INFRA_MUX(CLK_INFRA_UART2_SEL, "infra_uart2_sel", infra_uart0_parents,
0x10, 2, 1),
- INFRA_MUX(CK_INFRA_SPI0_SEL, "infra_spi0_sel", infra_spi0_parents, 0x10,
+ INFRA_MUX(CLK_INFRA_SPI0_SEL, "infra_spi0_sel", infra_spi0_parents, 0x10,
4, 1),
- INFRA_MUX(CK_INFRA_SPI1_SEL, "infra_spi1_sel", infra_spi1_parents, 0x10,
+ INFRA_MUX(CLK_INFRA_SPI1_SEL, "infra_spi1_sel", infra_spi1_parents, 0x10,
5, 1),
- INFRA_MUX(CK_INFRA_SPI2_SEL, "infra_spi2_sel", infra_spi0_parents, 0x10,
+ INFRA_MUX(CLK_INFRA_SPI2_SEL, "infra_spi2_sel", infra_spi0_parents, 0x10,
6, 1),
- INFRA_MUX(CK_INFRA_PWM1_SEL, "infra_pwm1_sel", infra_pwm1_parents, 0x10,
- 9, 2),
- INFRA_MUX(CK_INFRA_PWM2_SEL, "infra_pwm2_sel", infra_pwm1_parents, 0x10,
- 11, 2),
- INFRA_MUX(CK_INFRA_PWM_BSEL, "infra_pwm_bsel", infra_pwm_bsel_parents,
+ INFRA_MUX(CLK_INFRA_PWM1_SEL, "infra_pwm1_sel", infra_pwm1_parents, 0x10,
+ 9, 1),
+ INFRA_MUX(CLK_INFRA_PWM2_SEL, "infra_pwm2_sel", infra_pwm1_parents, 0x10,
+ 11, 1),
+ INFRA_MUX(CLK_INFRA_PWM3_SEL, "infra_pwm3_sel", infra_pwm1_parents, 0x10,
+ 15, 1),
+ INFRA_MUX(CLK_INFRA_PWM_BSEL, "infra_pwm_bsel", infra_pwm_bsel_parents,
0x10, 13, 2),
- INFRA_MUX(CK_INFRA_PCIE_SEL, "infra_pcie_sel", infra_pcie_parents, 0x20,
+ INFRA_MUX(CLK_INFRA_PCIE_SEL, "infra_pcie_sel", infra_pcie_parents, 0x20,
0, 2),
};
@@ -431,92 +407,105 @@
.sta_ofs = 0x68,
};
-#define GATE_INFRA0(_id, _name, _parent, _shift) \
+#define GATE_INFRA0(_id, _name, _parent, _shift, _flags) \
{ \
.id = _id, .parent = _parent, .regs = &infra_0_cg_regs, \
.shift = _shift, \
- .flags = CLK_GATE_SETCLR | CLK_PARENT_INFRASYS, \
+ .flags = _flags, \
}
+#define GATE_INFRA0_INFRA(_id, _name, _parent, _shift) \
+ GATE_INFRA0(_id, _name, _parent, _shift, CLK_GATE_SETCLR | CLK_PARENT_INFRASYS)
+#define GATE_INFRA0_TOP(_id, _name, _parent, _shift) \
+ GATE_INFRA0(_id, _name, _parent, _shift, CLK_GATE_SETCLR | CLK_PARENT_TOPCKGEN)
-#define GATE_INFRA1(_id, _name, _parent, _shift) \
+#define GATE_INFRA1(_id, _name, _parent, _shift, _flags) \
{ \
.id = _id, .parent = _parent, .regs = &infra_1_cg_regs, \
.shift = _shift, \
- .flags = CLK_GATE_SETCLR | CLK_PARENT_INFRASYS, \
+ .flags = _flags, \
}
+#define GATE_INFRA1_INFRA(_id, _name, _parent, _shift) \
+ GATE_INFRA1(_id, _name, _parent, _shift, CLK_GATE_SETCLR | CLK_PARENT_INFRASYS)
+#define GATE_INFRA1_TOP(_id, _name, _parent, _shift) \
+ GATE_INFRA1(_id, _name, _parent, _shift, CLK_GATE_SETCLR | CLK_PARENT_TOPCKGEN)
-#define GATE_INFRA2(_id, _name, _parent, _shift) \
+#define GATE_INFRA2(_id, _name, _parent, _shift, _flags) \
{ \
.id = _id, .parent = _parent, .regs = &infra_2_cg_regs, \
.shift = _shift, \
- .flags = CLK_GATE_SETCLR | CLK_PARENT_INFRASYS, \
+ .flags = _flags, \
}
+#define GATE_INFRA2_INFRA(_id, _name, _parent, _shift) \
+ GATE_INFRA2(_id, _name, _parent, _shift, CLK_GATE_SETCLR | CLK_PARENT_INFRASYS)
+#define GATE_INFRA2_TOP(_id, _name, _parent, _shift) \
+ GATE_INFRA2(_id, _name, _parent, _shift, CLK_GATE_SETCLR | CLK_PARENT_TOPCKGEN)
/* INFRA GATE */
-static const struct mtk_gate infracfg_ao_gates[] = {
- GATE_INFRA0(CK_INFRA_GPT_STA, "infra_gpt_sta", CK_INFRA_66M_MCK, 0),
- GATE_INFRA0(CK_INFRA_PWM_HCK, "infra_pwm_hck", CK_INFRA_66M_MCK, 1),
- GATE_INFRA0(CK_INFRA_PWM_STA, "infra_pwm_sta", CK_INFRA_PWM_BCK, 2),
- GATE_INFRA0(CK_INFRA_PWM1_CK, "infra_pwm1", CK_INFRA_PWM_CK1, 3),
- GATE_INFRA0(CK_INFRA_PWM2_CK, "infra_pwm2", CK_INFRA_PWM_CK2, 4),
- GATE_INFRA0(CK_INFRA_CQ_DMA_CK, "infra_cq_dma", CK_INFRA_133M_HCK, 6),
- GATE_INFRA0(CK_INFRA_AUD_BUS_CK, "infra_aud_bus", CK_INFRA_66M_PHCK, 8),
- GATE_INFRA0(CK_INFRA_AUD_26M_CK, "infra_aud_26m", CK_INFRA_CK_F26M, 9),
- GATE_INFRA0(CK_INFRA_AUD_L_CK, "infra_aud_l", CK_INFRA_FAUD_L_CK, 10),
- GATE_INFRA0(CK_INFRA_AUD_AUD_CK, "infra_aud_aud", CK_INFRA_FAUD_AUD_CK,
- 11),
- GATE_INFRA0(CK_INFRA_AUD_EG2_CK, "infra_aud_eg2", CK_INFRA_FAUD_EG2_CK,
- 13),
- GATE_INFRA0(CK_INFRA_DRAMC_26M_CK, "infra_dramc_26m", CK_INFRA_CK_F26M,
- 14),
- GATE_INFRA0(CK_INFRA_DBG_CK, "infra_dbg", CK_INFRA_66M_MCK, 15),
- GATE_INFRA0(CK_INFRA_AP_DMA_CK, "infra_ap_dma", CK_INFRA_66M_MCK, 16),
- GATE_INFRA0(CK_INFRA_SEJ_CK, "infra_sej", CK_INFRA_66M_MCK, 24),
- GATE_INFRA0(CK_INFRA_SEJ_13M_CK, "infra_sej_13m", CK_INFRA_CK_F26M, 25),
- GATE_INFRA1(CK_INFRA_THERM_CK, "infra_therm", CK_INFRA_CK_F26M, 0),
- GATE_INFRA1(CK_INFRA_I2CO_CK, "infra_i2co", CK_INFRA_I2CS_CK, 1),
- GATE_INFRA1(CK_INFRA_UART0_CK, "infra_uart0", CK_INFRA_MUX_UART0, 2),
- GATE_INFRA1(CK_INFRA_UART1_CK, "infra_uart1", CK_INFRA_MUX_UART1, 3),
- GATE_INFRA1(CK_INFRA_UART2_CK, "infra_uart2", CK_INFRA_MUX_UART2, 4),
- GATE_INFRA1(CK_INFRA_SPI2_CK, "infra_spi2", CK_INFRA_MUX_SPI2, 6),
- GATE_INFRA1(CK_INFRA_SPI2_HCK_CK, "infra_spi2_hck", CK_INFRA_66M_MCK,
- 7),
- GATE_INFRA1(CK_INFRA_NFI1_CK, "infra_nfi1", CK_INFRA_NFI_CK, 8),
- GATE_INFRA1(CK_INFRA_SPINFI1_CK, "infra_spinfi1", CK_INFRA_SPINFI_CK,
+static const struct mtk_gate infracfg_gates[] = {
+ GATE_INFRA0_INFRA(CLK_INFRA_GPT_STA, "infra_gpt_sta", CLK_INFRA_66M_MCK, 0),
+ GATE_INFRA0_INFRA(CLK_INFRA_PWM_HCK, "infra_pwm_hck", CLK_INFRA_66M_MCK, 1),
+ GATE_INFRA0_INFRA(CLK_INFRA_PWM_STA, "infra_pwm_sta", CLK_INFRA_PWM_BSEL, 2),
+ GATE_INFRA0_INFRA(CLK_INFRA_PWM1_CK, "infra_pwm1", CLK_INFRA_PWM1_SEL, 3),
+ GATE_INFRA0_INFRA(CLK_INFRA_PWM2_CK, "infra_pwm2", CLK_INFRA_PWM2_SEL, 4),
+ GATE_INFRA0_INFRA(CLK_INFRA_PWM3_CK, "infra_pwm3", CLK_INFRA_PWM3_SEL, 27),
+ GATE_INFRA0_TOP(CLK_INFRA_CQ_DMA_CK, "infra_cq_dma", CLK_TOP_SYSAXI, 6),
+ GATE_INFRA0_TOP(CLK_INFRA_AUD_BUS_CK, "infra_aud_bus", CLK_TOP_SYSAXI, 8),
+ GATE_INFRA0_TOP(CLK_INFRA_AUD_26M_CK, "infra_aud_26m", CLK_TOP_F26M_SEL, 9),
+ GATE_INFRA0_TOP(CLK_INFRA_AUD_L_CK, "infra_aud_l", CLK_TOP_AUD_L, 10),
+ GATE_INFRA0_TOP(CLK_INFRA_AUD_AUD_CK, "infra_aud_aud", CLK_TOP_A1SYS,
+ 11),
+ GATE_INFRA0_TOP(CLK_INFRA_AUD_EG2_CK, "infra_aud_eg2", CLK_TOP_A_TUNER,
+ 13),
+ GATE_INFRA0_TOP(CLK_INFRA_DRAMC_26M_CK, "infra_dramc_26m", CLK_TOP_F26M_SEL,
+ 14),
+ GATE_INFRA0_INFRA(CLK_INFRA_DBG_CK, "infra_dbg", CLK_INFRA_66M_MCK, 15),
+ GATE_INFRA0_INFRA(CLK_INFRA_AP_DMA_CK, "infra_ap_dma", CLK_INFRA_66M_MCK, 16),
+ GATE_INFRA0_INFRA(CLK_INFRA_SEJ_CK, "infra_sej", CLK_INFRA_66M_MCK, 24),
+ GATE_INFRA0_TOP(CLK_INFRA_SEJ_13M_CK, "infra_sej_13m", CLK_TOP_F26M_SEL, 25),
+ GATE_INFRA1_TOP(CLK_INFRA_THERM_CK, "infra_therm", CLK_TOP_F26M_SEL, 0),
+ GATE_INFRA1_TOP(CLK_INFRA_I2C0_CK, "infra_i2c0", CLK_TOP_I2C_BCK, 1),
+ GATE_INFRA1_INFRA(CLK_INFRA_UART0_CK, "infra_uart0", CLK_INFRA_UART0_SEL, 2),
+ GATE_INFRA1_INFRA(CLK_INFRA_UART1_CK, "infra_uart1", CLK_INFRA_UART1_SEL, 3),
+ GATE_INFRA1_INFRA(CLK_INFRA_UART2_CK, "infra_uart2", CLK_INFRA_UART2_SEL, 4),
+ GATE_INFRA1_INFRA(CLK_INFRA_SPI2_CK, "infra_spi2", CLK_INFRA_SPI2_SEL, 6),
+ GATE_INFRA1_INFRA(CLK_INFRA_SPI2_HCK_CK, "infra_spi2_hck", CLK_INFRA_66M_MCK,
+ 7),
+ GATE_INFRA1_TOP(CLK_INFRA_NFI1_CK, "infra_nfi1", CLK_TOP_NFI1X, 8),
+ GATE_INFRA1_TOP(CLK_INFRA_SPINFI1_CK, "infra_spinfi1", CLK_TOP_SPINFI_BCK,
9),
- GATE_INFRA1(CK_INFRA_NFI_HCK_CK, "infra_nfi_hck", CK_INFRA_66M_MCK, 10),
- GATE_INFRA1(CK_INFRA_SPI0_CK, "infra_spi0", CK_INFRA_MUX_SPI0, 11),
- GATE_INFRA1(CK_INFRA_SPI1_CK, "infra_spi1", CK_INFRA_MUX_SPI1, 12),
- GATE_INFRA1(CK_INFRA_SPI0_HCK_CK, "infra_spi0_hck", CK_INFRA_66M_MCK,
- 13),
- GATE_INFRA1(CK_INFRA_SPI1_HCK_CK, "infra_spi1_hck", CK_INFRA_66M_MCK,
- 14),
- GATE_INFRA1(CK_INFRA_FRTC_CK, "infra_frtc", CK_INFRA_RTC_32K, 15),
- GATE_INFRA1(CK_INFRA_MSDC_CK, "infra_msdc", CK_INFRA_FMSDC_CK, 16),
- GATE_INFRA1(CK_INFRA_MSDC_HCK_CK, "infra_msdc_hck",
- CK_INFRA_FMSDC_HCK_CK, 17),
- GATE_INFRA1(CK_INFRA_MSDC_133M_CK, "infra_msdc_133m",
- CK_INFRA_PERI_133M, 18),
- GATE_INFRA1(CK_INFRA_MSDC_66M_CK, "infra_msdc_66m", CK_INFRA_66M_PHCK,
- 19),
- GATE_INFRA1(CK_INFRA_ADC_26M_CK, "infra_adc_26m", CK_TOP_F26M, 20),
- GATE_INFRA1(CK_INFRA_ADC_FRC_CK, "infra_adc_frc", CK_TOP_F26M, 21),
- GATE_INFRA1(CK_INFRA_FBIST2FPC_CK, "infra_fbist2fpc", CK_INFRA_NFI_CK,
- 23),
- GATE_INFRA1(CK_INFRA_I2C_MCK_CK, "infra_i2c_mck", CK_INFRA_133M_MCK,
- 25),
- GATE_INFRA1(CK_INFRA_I2C_PCK_CK, "infra_i2c_pck", CK_INFRA_66M_MCK, 26),
- GATE_INFRA2(CK_INFRA_IUSB_133_CK, "infra_iusb_133", CK_INFRA_133M_PHCK,
- 0),
- GATE_INFRA2(CK_INFRA_IUSB_66M_CK, "infra_iusb_66m", CK_INFRA_66M_PHCK,
- 1),
- GATE_INFRA2(CK_INFRA_IUSB_SYS_CK, "infra_iusb_sys", CK_INFRA_USB_SYS_CK,
- 2),
- GATE_INFRA2(CK_INFRA_IUSB_CK, "infra_iusb", CK_INFRA_USB_CK, 3),
- GATE_INFRA2(CK_INFRA_IPCIE_CK, "infra_ipcie",
- CK_INFRA_PCIE_GFMUX_TL_O_PRE, 12),
- GATE_INFRA2(CK_INFRA_IPCIER_CK, "infra_ipcier", CK_INFRA_F26M_CK0, 14),
- GATE_INFRA2(CK_INFRA_IPCIEB_CK, "infra_ipcieb", CK_INFRA_133M_PHCK, 15),
+ GATE_INFRA1_INFRA(CLK_INFRA_NFI_HCK_CK, "infra_nfi_hck", CLK_INFRA_66M_MCK, 10),
+ GATE_INFRA1_INFRA(CLK_INFRA_SPI0_CK, "infra_spi0", CLK_INFRA_SPI0_SEL, 11),
+ GATE_INFRA1_INFRA(CLK_INFRA_SPI1_CK, "infra_spi1", CLK_INFRA_SPI1_SEL, 12),
+ GATE_INFRA1_INFRA(CLK_INFRA_SPI0_HCK_CK, "infra_spi0_hck", CLK_INFRA_66M_MCK,
+ 13),
+ GATE_INFRA1_INFRA(CLK_INFRA_SPI1_HCK_CK, "infra_spi1_hck", CLK_INFRA_66M_MCK,
+ 14),
+ GATE_INFRA1_TOP(CLK_INFRA_FRTC_CK, "infra_frtc", CLK_TOP_CB_RTC_32K, 15),
+ GATE_INFRA1_TOP(CLK_INFRA_MSDC_CK, "infra_msdc", CLK_TOP_EMMC_400M, 16),
+ GATE_INFRA1_TOP(CLK_INFRA_MSDC_HCK_CK, "infra_msdc_hck",
+ CLK_TOP_EMMC_208M, 17),
+ GATE_INFRA1_TOP(CLK_INFRA_MSDC_133M_CK, "infra_msdc_133m",
+ CLK_TOP_SYSAXI, 18),
+ GATE_INFRA1_TOP(CLK_INFRA_MSDC_66M_CK, "infra_msdc_66m", CLK_TOP_SYSAXI,
+ 19),
+ GATE_INFRA1_INFRA(CLK_INFRA_ADC_26M_CK, "infra_adc_26m", CLK_INFRA_ADC_FRC_CK, 20),
+ GATE_INFRA1_TOP(CLK_INFRA_ADC_FRC_CK, "infra_adc_frc", CLK_TOP_F26M, 21),
+ GATE_INFRA1_TOP(CLK_INFRA_FBIST2FPC_CK, "infra_fbist2fpc", CLK_TOP_NFI1X,
+ 23),
+ GATE_INFRA1_TOP(CLK_INFRA_I2C_MCK_CK, "infra_i2c_mck", CLK_TOP_SYSAXI,
+ 25),
+ GATE_INFRA1_INFRA(CLK_INFRA_I2C_PCK_CK, "infra_i2c_pck", CLK_INFRA_66M_MCK, 26),
+ GATE_INFRA2_TOP(CLK_INFRA_IUSB_133_CK, "infra_iusb_133", CLK_TOP_SYSAXI,
+ 0),
+ GATE_INFRA2_TOP(CLK_INFRA_IUSB_66M_CK, "infra_iusb_66m", CLK_TOP_SYSAXI,
+ 1),
+ GATE_INFRA2_TOP(CLK_INFRA_IUSB_SYS_CK, "infra_iusb_sys", CLK_TOP_U2U3_SYS,
+ 2),
+ GATE_INFRA2_TOP(CLK_INFRA_IUSB_CK, "infra_iusb", CLK_TOP_U2U3_REF, 3),
+ GATE_INFRA2_TOP(CLK_INFRA_IPCIE_CK, "infra_ipcie", CLK_TOP_PEXTP_TL, 12),
+ GATE_INFRA2_TOP(CLK_INFRA_IPCIE_PIPE_CK, "infra_ipcie_pipe", CLK_TOP_CB_CKSQ_40M, 13),
+ GATE_INFRA2_TOP(CLK_INFRA_IPCIER_CK, "infra_ipcier", CLK_TOP_F26M, 14),
+ GATE_INFRA2_TOP(CLK_INFRA_IPCIEB_CK, "infra_ipcieb", CLK_TOP_SYSAXI, 15),
};
static const struct mtk_clk_tree mt7981_fixed_pll_clk_tree = {
@@ -526,19 +515,22 @@
};
static const struct mtk_clk_tree mt7981_topckgen_clk_tree = {
- .fdivs_offs = CK_TOP_CB_M_416M,
- .muxes_offs = CK_TOP_NFI1X_SEL,
+ .fdivs_offs = CLK_TOP_CB_M_416M,
+ .muxes_offs = CLK_TOP_NFI1X_SEL,
.fclks = top_fixed_clks,
.fdivs = top_fixed_divs,
.muxes = top_muxes,
- .flags = CLK_BYPASS_XTAL,
+ .flags = CLK_BYPASS_XTAL | CLK_TOPCKGEN,
};
static const struct mtk_clk_tree mt7981_infracfg_clk_tree = {
- .fdivs_offs = CK_INFRA_CK_F26M,
- .muxes_offs = CK_INFRA_UART0_SEL,
+ .fdivs_offs = CLK_INFRA_66M_MCK,
+ .muxes_offs = CLK_INFRA_UART0_SEL,
+ .gates_offs = CLK_INFRA_GPT_STA,
.fdivs = infra_fixed_divs,
.muxes = infra_muxes,
+ .gates = infracfg_gates,
+ .flags = CLK_INFRASYS,
};
static const struct udevice_id mt7981_fixed_pll_compat[] = {
@@ -592,20 +584,9 @@
{}
};
-static const struct udevice_id mt7981_infracfg_ao_compat[] = {
- { .compatible = "mediatek,mt7981-infracfg_ao" },
- {}
-};
-
static int mt7981_infracfg_probe(struct udevice *dev)
{
- return mtk_common_clk_init(dev, &mt7981_infracfg_clk_tree);
-}
-
-static int mt7981_infracfg_ao_probe(struct udevice *dev)
-{
- return mtk_common_clk_gate_init(dev, &mt7981_infracfg_clk_tree,
- infracfg_ao_gates);
+ return mtk_common_clk_infrasys_init(dev, &mt7981_infracfg_clk_tree);
}
U_BOOT_DRIVER(mtk_clk_infracfg) = {
@@ -618,16 +599,74 @@
.flags = DM_FLAG_PRE_RELOC,
};
+/* sgmiisys */
+static const struct mtk_gate_regs sgmii_cg_regs = {
+ .set_ofs = 0xe4,
+ .clr_ofs = 0xe4,
+ .sta_ofs = 0xe4,
+};
+
-U_BOOT_DRIVER(mtk_clk_infracfg_ao) = {
- .name = "mt7981-clock-infracfg-ao",
+#define GATE_SGMII(_id, _name, _parent, _shift) \
+ { \
+ .id = _id, .parent = _parent, .regs = &sgmii_cg_regs, \
+ .shift = _shift, \
+ .flags = CLK_GATE_NO_SETCLR_INV | CLK_PARENT_TOPCKGEN, \
+ }
+
+static const struct mtk_gate sgmii0_cgs[] = {
+ GATE_SGMII(CLK_SGM0_TX_EN, "sgm0_tx_en", CLK_TOP_USB_TX250M, 2),
+ GATE_SGMII(CLK_SGM0_RX_EN, "sgm0_rx_en", CLK_TOP_USB_EQ_RX250M, 3),
+ GATE_SGMII(CLK_SGM0_CK0_EN, "sgm0_ck0_en", CLK_TOP_USB_LN0_CK, 4),
+ GATE_SGMII(CLK_SGM0_CDR_CK0_EN, "sgm0_cdr_ck0_en", CLK_TOP_USB_CDR_CK, 5),
+};
+
+static int mt7981_sgmii0sys_probe(struct udevice *dev)
+{
+ return mtk_common_clk_gate_init(dev, &mt7981_topckgen_clk_tree,
+ sgmii0_cgs);
+}
+
+static const struct udevice_id mt7981_sgmii0sys_compat[] = {
+ { .compatible = "mediatek,mt7981-sgmiisys_0", },
+ {}
+};
+
+U_BOOT_DRIVER(mtk_clk_sgmii0sys) = {
+ .name = "mt7981-clock-sgmii0sys",
.id = UCLASS_CLK,
- .of_match = mt7981_infracfg_ao_compat,
- .probe = mt7981_infracfg_ao_probe,
+ .of_match = mt7981_sgmii0sys_compat,
+ .probe = mt7981_sgmii0sys_probe,
.priv_auto = sizeof(struct mtk_cg_priv),
.ops = &mtk_clk_gate_ops,
- .flags = DM_FLAG_PRE_RELOC,
+};
+
+static const struct mtk_gate sgmii1_cgs[] = {
+ GATE_SGMII(CLK_SGM1_TX_EN, "sgm1_tx_en", CLK_TOP_USB_TX250M, 2),
+ GATE_SGMII(CLK_SGM1_RX_EN, "sgm1_rx_en", CLK_TOP_USB_EQ_RX250M, 3),
+ GATE_SGMII(CLK_SGM1_CK1_EN, "sgm1_ck1_en", CLK_TOP_USB_LN0_CK, 4),
+ GATE_SGMII(CLK_SGM1_CDR_CK1_EN, "sgm1_cdr_ck1_en", CLK_TOP_USB_CDR_CK, 5),
};
+static int mt7981_sgmii1sys_probe(struct udevice *dev)
+{
+ return mtk_common_clk_gate_init(dev, &mt7981_topckgen_clk_tree,
+ sgmii1_cgs);
+}
+
+static const struct udevice_id mt7981_sgmii1sys_compat[] = {
+ { .compatible = "mediatek,mt7981-sgmiisys_1", },
+ {}
+};
+
+U_BOOT_DRIVER(mtk_clk_sgmii1sys) = {
+ .name = "mt7981-clock-sgmii1sys",
+ .id = UCLASS_CLK,
+ .of_match = mt7981_sgmii1sys_compat,
+ .probe = mt7981_sgmii1sys_probe,
+ .priv_auto = sizeof(struct mtk_cg_priv),
+ .ops = &mtk_clk_gate_ops,
+};
+
/* ethsys */
static const struct mtk_gate_regs eth_cg_regs = {
.set_ofs = 0x30,
@@ -643,10 +682,10 @@
}
static const struct mtk_gate eth_cgs[] = {
- GATE_ETH(CK_ETH_FE_EN, "eth_fe_en", CK_TOP_NETSYS_2X, 6),
- GATE_ETH(CK_ETH_GP2_EN, "eth_gp2_en", CK_TOP_SGM_325M, 7),
- GATE_ETH(CK_ETH_GP1_EN, "eth_gp1_en", CK_TOP_SGM_325M, 8),
- GATE_ETH(CK_ETH_WOCPU0_EN, "eth_wocpu0_en", CK_TOP_NETSYS_WED_MCU, 15),
+ GATE_ETH(CLK_ETH_FE_EN, "eth_fe_en", CLK_TOP_NETSYS_2X, 6),
+ GATE_ETH(CLK_ETH_GP2_EN, "eth_gp2_en", CLK_TOP_SGM_325M, 7),
+ GATE_ETH(CLK_ETH_GP1_EN, "eth_gp1_en", CLK_TOP_SGM_325M, 8),
+ GATE_ETH(CLK_ETH_WOCPU0_EN, "eth_wocpu0_en", CLK_TOP_NETSYS_WED_MCU, 15),
};
static int mt7981_ethsys_probe(struct udevice *dev)
diff --git a/drivers/clk/mediatek/clk-mt7986.c b/drivers/clk/mediatek/clk-mt7986.c
index efc3d41..c5cc772 100644
--- a/drivers/clk/mediatek/clk-mt7986.c
+++ b/drivers/clk/mediatek/clk-mt7986.c
@@ -18,6 +18,11 @@
#define MT7986_CLK_PDN 0x250
#define MT7986_CLK_PDN_EN_WRITE BIT(31)
+#define APMIXED_PARENT(_id) PARENT(_id, CLK_PARENT_APMIXED)
+#define INFRA_PARENT(_id) PARENT(_id, CLK_PARENT_INFRASYS)
+#define TOP_PARENT(_id) PARENT(_id, CLK_PARENT_TOPCKGEN)
+#define VOID_PARENT PARENT(-1, 0)
+
#define PLL_FACTOR(_id, _name, _parent, _mult, _div) \
FACTOR(_id, _parent, _mult, _div, CLK_PARENT_APMIXED)
@@ -29,177 +34,195 @@
/* FIXED PLLS */
static const struct mtk_fixed_clk fixed_pll_clks[] = {
- FIXED_CLK(CK_APMIXED_ARMPLL, CLK_XTAL, 2000000000),
- FIXED_CLK(CK_APMIXED_NET2PLL, CLK_XTAL, 800000000),
- FIXED_CLK(CK_APMIXED_MMPLL, CLK_XTAL, 1440000000),
- FIXED_CLK(CK_APMIXED_SGMPLL, CLK_XTAL, 325000000),
- FIXED_CLK(CK_APMIXED_WEDMCUPLL, CLK_XTAL, 760000000),
- FIXED_CLK(CK_APMIXED_NET1PLL, CLK_XTAL, 2500000000),
- FIXED_CLK(CK_APMIXED_MPLL, CLK_XTAL, 416000000),
- FIXED_CLK(CK_APMIXED_APLL2, CLK_XTAL, 196608000),
+ FIXED_CLK(CLK_APMIXED_ARMPLL, CLK_XTAL, 2000000000),
+ FIXED_CLK(CLK_APMIXED_NET2PLL, CLK_XTAL, 800000000),
+ FIXED_CLK(CLK_APMIXED_MMPLL, CLK_XTAL, 1440000000),
+ FIXED_CLK(CLK_APMIXED_SGMPLL, CLK_XTAL, 325000000),
+ FIXED_CLK(CLK_APMIXED_WEDMCUPLL, CLK_XTAL, 760000000),
+ FIXED_CLK(CLK_APMIXED_NET1PLL, CLK_XTAL, 2500000000),
+ FIXED_CLK(CLK_APMIXED_MPLL, CLK_XTAL, 416000000),
+ FIXED_CLK(CLK_APMIXED_APLL2, CLK_XTAL, 196608000),
};
/* TOPCKGEN FIXED CLK */
static const struct mtk_fixed_clk top_fixed_clks[] = {
- FIXED_CLK(CK_TOP_CB_CKSQ_40M, CLK_XTAL, 40000000),
+ FIXED_CLK(CLK_TOP_XTAL, CLK_XTAL, 40000000),
};
/* TOPCKGEN FIXED DIV */
static const struct mtk_fixed_factor top_fixed_divs[] = {
- PLL_FACTOR(CK_TOP_CB_M_416M, "cb_m_416m", CK_APMIXED_MPLL, 1, 1),
- PLL_FACTOR(CK_TOP_CB_M_D2, "cb_m_d2", CK_APMIXED_MPLL, 1, 2),
- PLL_FACTOR(CK_TOP_CB_M_D4, "cb_m_d4", CK_APMIXED_MPLL, 1, 4),
- PLL_FACTOR(CK_TOP_CB_M_D8, "cb_m_d8", CK_APMIXED_MPLL, 1, 8),
- PLL_FACTOR(CK_TOP_M_D8_D2, "m_d8_d2", CK_APMIXED_MPLL, 1, 16),
- PLL_FACTOR(CK_TOP_M_D3_D2, "m_d3_d2", CK_APMIXED_MPLL, 1, 2),
- PLL_FACTOR(CK_TOP_CB_MM_D2, "cb_mm_d2", CK_APMIXED_MMPLL, 1, 2),
- PLL_FACTOR(CK_TOP_CB_MM_D4, "cb_mm_d4", CK_APMIXED_MMPLL, 1, 4),
- PLL_FACTOR(CK_TOP_CB_MM_D8, "cb_mm_d8", CK_APMIXED_MMPLL, 1, 8),
- PLL_FACTOR(CK_TOP_MM_D8_D2, "mm_d8_d2", CK_APMIXED_MMPLL, 1, 16),
- PLL_FACTOR(CK_TOP_MM_D3_D8, "mm_d3_d8", CK_APMIXED_MMPLL, 1, 8),
- PLL_FACTOR(CK_TOP_CB_U2_PHYD_CK, "cb_u2_phyd", CK_APMIXED_MMPLL, 1, 30),
- PLL_FACTOR(CK_TOP_CB_APLL2_196M, "cb_apll2_196m", CK_APMIXED_APLL2, 1,
- 1),
- PLL_FACTOR(CK_TOP_APLL2_D4, "apll2_d4", CK_APMIXED_APLL2, 1, 4),
- PLL_FACTOR(CK_TOP_CB_NET1_D4, "cb_net1_d4", CK_APMIXED_NET1PLL, 1, 4),
- PLL_FACTOR(CK_TOP_CB_NET1_D5, "cb_net1_d5", CK_APMIXED_NET1PLL, 1, 5),
- PLL_FACTOR(CK_TOP_NET1_D5_D2, "net1_d5_d2", CK_APMIXED_NET1PLL, 1, 10),
- PLL_FACTOR(CK_TOP_NET1_D5_D4, "net1_d5_d4", CK_APMIXED_NET1PLL, 1, 20),
- PLL_FACTOR(CK_TOP_NET1_D8_D2, "net1_d8_d2", CK_APMIXED_NET1PLL, 1, 16),
- PLL_FACTOR(CK_TOP_NET1_D8_D4, "net1_d8_d4", CK_APMIXED_NET1PLL, 1, 32),
- PLL_FACTOR(CK_TOP_CB_NET2_800M, "cb_net2_800m", CK_APMIXED_NET2PLL, 1,
- 1),
- PLL_FACTOR(CK_TOP_CB_NET2_D4, "cb_net2_d4", CK_APMIXED_NET2PLL, 1, 4),
- PLL_FACTOR(CK_TOP_NET2_D4_D2, "net2_d4_d2", CK_APMIXED_NET2PLL, 1, 8),
- PLL_FACTOR(CK_TOP_NET2_D3_D2, "net2_d3_d2", CK_APMIXED_NET2PLL, 1, 2),
- PLL_FACTOR(CK_TOP_CB_WEDMCU_760M, "cb_wedmcu_760m",
- CK_APMIXED_WEDMCUPLL, 1, 1),
- PLL_FACTOR(CK_TOP_WEDMCU_D5_D2, "wedmcu_d5_d2", CK_APMIXED_WEDMCUPLL, 1,
- 10),
- PLL_FACTOR(CK_TOP_CB_SGM_325M, "cb_sgm_325m", CK_APMIXED_SGMPLL, 1, 1),
- TOP_FACTOR(CK_TOP_CB_CKSQ_40M_D2, "cb_cksq_40m_d2", CK_TOP_CB_CKSQ_40M,
+ /* TOP Factors */
+ TOP_FACTOR(CLK_TOP_XTAL_D2, "xtal_d2", CLK_TOP_XTAL,
1, 2),
- TOP_FACTOR(CK_TOP_CB_RTC_32K, "cb_rtc_32k", CK_TOP_CB_CKSQ_40M, 1,
+ TOP_FACTOR(CLK_TOP_RTC_32K, "rtc_32k", CLK_TOP_XTAL, 1,
1250),
- TOP_FACTOR(CK_TOP_CB_RTC_32P7K, "cb_rtc_32p7k", CK_TOP_CB_CKSQ_40M, 1,
+ TOP_FACTOR(CLK_TOP_RTC_32P7K, "rtc_32p7k", CLK_TOP_XTAL, 1,
1220),
- TOP_FACTOR(CK_TOP_NFI1X, "nfi1x", CK_TOP_NFI1X_SEL, 1, 1),
- TOP_FACTOR(CK_TOP_USB_EQ_RX250M, "usb_eq_rx250m", CK_TOP_CB_CKSQ_40M, 1,
- 1),
- TOP_FACTOR(CK_TOP_USB_TX250M, "usb_tx250m", CK_TOP_CB_CKSQ_40M, 1, 1),
- TOP_FACTOR(CK_TOP_USB_LN0_CK, "usb_ln0", CK_TOP_CB_CKSQ_40M, 1, 1),
- TOP_FACTOR(CK_TOP_USB_CDR_CK, "usb_cdr", CK_TOP_CB_CKSQ_40M, 1, 1),
- TOP_FACTOR(CK_TOP_SPINFI_BCK, "spinfi_bck", CK_TOP_SPINFI_SEL, 1, 1),
- TOP_FACTOR(CK_TOP_I2C_BCK, "i2c_bck", CK_TOP_I2C_SEL, 1, 1),
- TOP_FACTOR(CK_TOP_PEXTP_TL, "pextp_tl", CK_TOP_PEXTP_TL_SEL, 1, 1),
- TOP_FACTOR(CK_TOP_EMMC_250M, "emmc_250m", CK_TOP_EMMC_250M_SEL, 1, 1),
- TOP_FACTOR(CK_TOP_EMMC_416M, "emmc_416m", CK_TOP_EMMC_416M_SEL, 1, 1),
- TOP_FACTOR(CK_TOP_F_26M_ADC_CK, "f_26m_adc", CK_TOP_F_26M_ADC_SEL, 1,
- 1),
- TOP_FACTOR(CK_TOP_SYSAXI, "sysaxi", CK_TOP_SYSAXI_SEL, 1, 1),
- TOP_FACTOR(CK_TOP_NETSYS_WED_MCU, "netsys_wed_mcu",
- CK_TOP_NETSYS_MCU_SEL, 1, 1),
- TOP_FACTOR(CK_TOP_NETSYS_2X, "netsys_2x", CK_TOP_NETSYS_2X_SEL, 1, 1),
- TOP_FACTOR(CK_TOP_SGM_325M, "sgm_325m", CK_TOP_SGM_325M_SEL, 1, 1),
- TOP_FACTOR(CK_TOP_A1SYS, "a1sys", CK_TOP_A1SYS_SEL, 1, 1),
- TOP_FACTOR(CK_TOP_EIP_B, "eip_b", CK_TOP_EIP_B_SEL, 1, 1),
- TOP_FACTOR(CK_TOP_F26M, "csw_f26m", CK_TOP_F26M_SEL, 1, 1),
- TOP_FACTOR(CK_TOP_AUD_L, "aud_l", CK_TOP_AUD_L_SEL, 1, 1),
- TOP_FACTOR(CK_TOP_A_TUNER, "a_tuner", CK_TOP_A_TUNER_SEL, 2, 1),
- TOP_FACTOR(CK_TOP_U2U3_REF, "u2u3_ref", CK_TOP_U2U3_SEL, 1, 1),
- TOP_FACTOR(CK_TOP_U2U3_SYS, "u2u3_sys", CK_TOP_U2U3_SYS_SEL, 1, 1),
- TOP_FACTOR(CK_TOP_U2U3_XHCI, "u2u3_xhci", CK_TOP_U2U3_XHCI_SEL, 1, 1),
- TOP_FACTOR(CK_TOP_AP2CNN_HOST, "ap2cnn_host", CK_TOP_AP2CNN_HOST_SEL, 1,
- 1),
+ /* Not defined upstream and not used */
+ /* TOP_FACTOR(CLK_TOP_A_TUNER, "a_tuner", CLK_TOP_A_TUNER_SEL, 2, 1), */
+ /* MPLL */
+ PLL_FACTOR(CLK_TOP_MPLL_D2, "mpll_d2", CLK_APMIXED_MPLL, 1, 2),
+ PLL_FACTOR(CLK_TOP_MPLL_D4, "mpll_d4", CLK_APMIXED_MPLL, 1, 4),
+ PLL_FACTOR(CLK_TOP_MPLL_D8, "mpll_d8", CLK_APMIXED_MPLL, 1, 8),
+ PLL_FACTOR(CLK_TOP_MPLL_D8_D2, "mpll_d8_d2", CLK_APMIXED_MPLL, 1, 16),
+ PLL_FACTOR(CLK_TOP_MPLL_D3_D2, "mpll_d3_d2", CLK_APMIXED_MPLL, 1, 2),
+ /* MMPLL */
+ PLL_FACTOR(CLK_TOP_MMPLL_D2, "mmpll_d2", CLK_APMIXED_MMPLL, 1, 2),
+ PLL_FACTOR(CLK_TOP_MMPLL_D4, "mmpll_d4", CLK_APMIXED_MMPLL, 1, 4),
+ PLL_FACTOR(CLK_TOP_MMPLL_D8, "mmpll_d8", CLK_APMIXED_MMPLL, 1, 8),
+ PLL_FACTOR(CLK_TOP_MMPLL_D8_D2, "mmpll_d8_d2", CLK_APMIXED_MMPLL, 1, 16),
+ PLL_FACTOR(CLK_TOP_MMPLL_D3_D8, "mmpll_d3_d8", CLK_APMIXED_MMPLL, 1, 8),
+ PLL_FACTOR(CLK_TOP_MMPLL_U2PHYD, "mmpll_u2phy", CLK_APMIXED_MMPLL, 1, 30),
+ /* APLL2 */
+ PLL_FACTOR(CLK_TOP_APLL2_D4, "apll2_d4", CLK_APMIXED_APLL2, 1, 4),
+ /* NET1PLL */
+ PLL_FACTOR(CLK_TOP_NET1PLL_D4, "net1pll_d4", CLK_APMIXED_NET1PLL, 1, 4),
+ PLL_FACTOR(CLK_TOP_NET1PLL_D5, "net1pll_d5", CLK_APMIXED_NET1PLL, 1, 5),
+ PLL_FACTOR(CLK_TOP_NET1PLL_D5_D2, "net1pll_d5_d2", CLK_APMIXED_NET1PLL, 1, 10),
+ PLL_FACTOR(CLK_TOP_NET1PLL_D5_D4, "net1pll_d5_d4", CLK_APMIXED_NET1PLL, 1, 20),
+ PLL_FACTOR(CLK_TOP_NET1PLL_D8_D2, "net1pll_d8_d2", CLK_APMIXED_NET1PLL, 1, 16),
+ PLL_FACTOR(CLK_TOP_NET1PLL_D8_D4, "net1pll_d8_d4", CLK_APMIXED_NET1PLL, 1, 32),
+ /* NET2PLL */
+ PLL_FACTOR(CLK_TOP_NET2PLL_D4, "net2pll_d4", CLK_APMIXED_NET2PLL, 1, 4),
+ PLL_FACTOR(CLK_TOP_NET2PLL_D4_D2, "net2pll_d4_d2", CLK_APMIXED_NET2PLL, 1, 8),
+ PLL_FACTOR(CLK_TOP_NET2PLL_D3_D2, "net2pll_d3_d2", CLK_APMIXED_NET2PLL, 1, 2),
+ /* WEDMCUPLL */
+ PLL_FACTOR(CLK_TOP_WEDMCUPLL_D5_D2, "wedmcupll_d5_d2", CLK_APMIXED_WEDMCUPLL, 1,
+ 10),
};
/* TOPCKGEN MUX PARENTS */
-static const int nfi1x_parents[] = { CK_TOP_CB_CKSQ_40M, CK_TOP_CB_MM_D8,
- CK_TOP_NET1_D8_D2, CK_TOP_NET2_D3_D2,
- CK_TOP_CB_M_D4, CK_TOP_MM_D8_D2,
- CK_TOP_WEDMCU_D5_D2, CK_TOP_CB_M_D8 };
+static const struct mtk_parent nfi1x_parents[] = {
+ TOP_PARENT(CLK_TOP_XTAL), TOP_PARENT(CLK_TOP_MMPLL_D8),
+ TOP_PARENT(CLK_TOP_NET1PLL_D8_D2), TOP_PARENT(CLK_TOP_NET2PLL_D3_D2),
+ TOP_PARENT(CLK_TOP_MPLL_D4), TOP_PARENT(CLK_TOP_MMPLL_D8_D2),
+ TOP_PARENT(CLK_TOP_WEDMCUPLL_D5_D2), TOP_PARENT(CLK_TOP_MPLL_D8),
+};
-static const int spinfi_parents[] = {
- CK_TOP_CB_CKSQ_40M_D2, CK_TOP_CB_CKSQ_40M, CK_TOP_NET1_D5_D4,
- CK_TOP_CB_M_D4, CK_TOP_MM_D8_D2, CK_TOP_WEDMCU_D5_D2,
- CK_TOP_MM_D3_D8, CK_TOP_CB_M_D8
+static const struct mtk_parent spinfi_parents[] = {
+ TOP_PARENT(CLK_TOP_XTAL_D2), TOP_PARENT(CLK_TOP_XTAL),
+ TOP_PARENT(CLK_TOP_NET1PLL_D5_D4), TOP_PARENT(CLK_TOP_MPLL_D4),
+ TOP_PARENT(CLK_TOP_MMPLL_D8_D2), TOP_PARENT(CLK_TOP_WEDMCUPLL_D5_D2),
+ TOP_PARENT(CLK_TOP_MMPLL_D3_D8), TOP_PARENT(CLK_TOP_MPLL_D8),
};
-static const int spi_parents[] = { CK_TOP_CB_CKSQ_40M, CK_TOP_CB_M_D2,
- CK_TOP_CB_MM_D8, CK_TOP_NET1_D8_D2,
- CK_TOP_NET2_D3_D2, CK_TOP_NET1_D5_D4,
- CK_TOP_CB_M_D4, CK_TOP_WEDMCU_D5_D2 };
+static const struct mtk_parent spi_parents[] = {
+ TOP_PARENT(CLK_TOP_XTAL), TOP_PARENT(CLK_TOP_MPLL_D2),
+ TOP_PARENT(CLK_TOP_MMPLL_D8), TOP_PARENT(CLK_TOP_NET1PLL_D8_D2),
+ TOP_PARENT(CLK_TOP_NET2PLL_D3_D2), TOP_PARENT(CLK_TOP_NET1PLL_D5_D4),
+ TOP_PARENT(CLK_TOP_MPLL_D4), TOP_PARENT(CLK_TOP_WEDMCUPLL_D5_D2),
+};
-static const int uart_parents[] = { CK_TOP_CB_CKSQ_40M, CK_TOP_CB_M_D8,
- CK_TOP_M_D8_D2 };
+static const struct mtk_parent uart_parents[] = {
+ TOP_PARENT(CLK_TOP_XTAL), TOP_PARENT(CLK_TOP_MPLL_D8),
+ TOP_PARENT(CLK_TOP_MPLL_D8_D2),
+};
-static const int pwm_parents[] = { CK_TOP_CB_CKSQ_40M, CK_TOP_NET1_D8_D2,
- CK_TOP_NET1_D5_D4, CK_TOP_CB_M_D4 };
+static const struct mtk_parent pwm_parents[] = {
+ TOP_PARENT(CLK_TOP_XTAL), TOP_PARENT(CLK_TOP_NET1PLL_D8_D2),
+ TOP_PARENT(CLK_TOP_NET1PLL_D5_D4), TOP_PARENT(CLK_TOP_MPLL_D4),
+};
-static const int i2c_parents[] = { CK_TOP_CB_CKSQ_40M, CK_TOP_NET1_D5_D4,
- CK_TOP_CB_M_D4, CK_TOP_NET1_D8_D4 };
+static const struct mtk_parent i2c_parents[] = {
+ TOP_PARENT(CLK_TOP_XTAL), TOP_PARENT(CLK_TOP_NET1PLL_D5_D4),
+ TOP_PARENT(CLK_TOP_MPLL_D4), TOP_PARENT(CLK_TOP_NET1PLL_D8_D4),
+};
-static const int pextp_tl_ck_parents[] = { CK_TOP_CB_CKSQ_40M,
- CK_TOP_NET1_D5_D4, CK_TOP_NET2_D4_D2,
- CK_TOP_CB_RTC_32K };
+static const struct mtk_parent pextp_tl_ck_parents[] = {
+ TOP_PARENT(CLK_TOP_XTAL), TOP_PARENT(CLK_TOP_NET1PLL_D5_D4),
+ TOP_PARENT(CLK_TOP_NET2PLL_D4_D2), TOP_PARENT(CLK_TOP_RTC_32K),
+};
-static const int emmc_250m_parents[] = { CK_TOP_CB_CKSQ_40M,
- CK_TOP_NET1_D5_D2 };
+static const struct mtk_parent emmc_250m_parents[] = {
+ TOP_PARENT(CLK_TOP_XTAL), TOP_PARENT(CLK_TOP_NET1PLL_D5_D2),
+};
-static const int emmc_416m_parents[] = { CK_TOP_CB_CKSQ_40M, CK_TOP_CB_M_416M };
+static const struct mtk_parent emmc_416m_parents[] = {
+ TOP_PARENT(CLK_TOP_XTAL), APMIXED_PARENT(CLK_APMIXED_MPLL),
+};
-static const int f_26m_adc_parents[] = { CK_TOP_CB_CKSQ_40M, CK_TOP_M_D8_D2 };
+static const struct mtk_parent f_26m_adc_parents[] = {
+ TOP_PARENT(CLK_TOP_XTAL), TOP_PARENT(CLK_TOP_MPLL_D8_D2),
+};
-static const int dramc_md32_parents[] = { CK_TOP_CB_CKSQ_40M, CK_TOP_CB_M_D2 };
+static const struct mtk_parent dramc_md32_parents[] = {
+ TOP_PARENT(CLK_TOP_XTAL), TOP_PARENT(CLK_TOP_MPLL_D2),
+};
-static const int sysaxi_parents[] = { CK_TOP_CB_CKSQ_40M, CK_TOP_NET1_D8_D2,
- CK_TOP_CB_NET2_D4 };
+static const struct mtk_parent sysaxi_parents[] = {
+ TOP_PARENT(CLK_TOP_XTAL), TOP_PARENT(CLK_TOP_NET1PLL_D8_D2),
+ TOP_PARENT(CLK_TOP_NET2PLL_D4),
+};
-static const int sysapb_parents[] = { CK_TOP_CB_CKSQ_40M, CK_TOP_M_D3_D2,
- CK_TOP_NET2_D4_D2 };
+static const struct mtk_parent sysapb_parents[] = {
+ TOP_PARENT(CLK_TOP_XTAL), TOP_PARENT(CLK_TOP_MPLL_D3_D2),
+ TOP_PARENT(CLK_TOP_NET2PLL_D4_D2),
+};
-static const int arm_db_main_parents[] = { CK_TOP_CB_CKSQ_40M,
- CK_TOP_NET2_D3_D2 };
+static const struct mtk_parent arm_db_main_parents[] = {
+ TOP_PARENT(CLK_TOP_XTAL), TOP_PARENT(CLK_TOP_NET2PLL_D3_D2),
+};
-static const int arm_db_jtsel_parents[] = { -1, CK_TOP_CB_CKSQ_40M };
+static const struct mtk_parent arm_db_jtsel_parents[] = {
+ VOID_PARENT, TOP_PARENT(CLK_TOP_XTAL),
+};
-static const int netsys_parents[] = { CK_TOP_CB_CKSQ_40M, CK_TOP_CB_MM_D4 };
+static const struct mtk_parent netsys_parents[] = {
+ TOP_PARENT(CLK_TOP_XTAL), TOP_PARENT(CLK_TOP_MMPLL_D4),
+};
-static const int netsys_500m_parents[] = { CK_TOP_CB_CKSQ_40M,
- CK_TOP_CB_NET1_D5 };
+static const struct mtk_parent netsys_500m_parents[] = {
+ TOP_PARENT(CLK_TOP_XTAL), TOP_PARENT(CLK_TOP_NET1PLL_D5),
+};
-static const int netsys_mcu_parents[] = { CK_TOP_CB_CKSQ_40M,
- CK_TOP_CB_WEDMCU_760M,
- CK_TOP_CB_MM_D2, CK_TOP_CB_NET1_D4,
- CK_TOP_CB_NET1_D5 };
+static const struct mtk_parent netsys_mcu_parents[] = {
+ TOP_PARENT(CLK_TOP_XTAL), APMIXED_PARENT(CLK_APMIXED_WEDMCUPLL),
+ TOP_PARENT(CLK_TOP_MMPLL_D2), TOP_PARENT(CLK_TOP_NET1PLL_D4),
+ TOP_PARENT(CLK_TOP_NET1PLL_D5),
+};
-static const int netsys_2x_parents[] = { CK_TOP_CB_CKSQ_40M,
- CK_TOP_CB_NET2_800M,
- CK_TOP_CB_WEDMCU_760M,
- CK_TOP_CB_MM_D2 };
+static const struct mtk_parent netsys_2x_parents[] = {
+ TOP_PARENT(CLK_TOP_XTAL), TOP_PARENT(CLK_APMIXED_NET2PLL),
+ APMIXED_PARENT(CLK_APMIXED_WEDMCUPLL), TOP_PARENT(CLK_TOP_MMPLL_D2),
+};
-static const int sgm_325m_parents[] = { CK_TOP_CB_CKSQ_40M,
- CK_TOP_CB_SGM_325M };
+static const struct mtk_parent sgm_325m_parents[] = {
+ TOP_PARENT(CLK_TOP_XTAL), APMIXED_PARENT(CLK_APMIXED_SGMPLL),
+};
-static const int sgm_reg_parents[] = { CK_TOP_CB_CKSQ_40M, CK_TOP_NET1_D8_D4 };
+static const struct mtk_parent sgm_reg_parents[] = {
+ TOP_PARENT(CLK_TOP_XTAL), TOP_PARENT(CLK_TOP_NET1PLL_D8_D4),
+};
-static const int a1sys_parents[] = { CK_TOP_CB_CKSQ_40M, CK_TOP_APLL2_D4 };
+static const struct mtk_parent a1sys_parents[] = {
+ TOP_PARENT(CLK_TOP_XTAL), TOP_PARENT(CLK_TOP_APLL2_D4),
+};
-static const int conn_mcusys_parents[] = { CK_TOP_CB_CKSQ_40M,
- CK_TOP_CB_MM_D2 };
+static const struct mtk_parent conn_mcusys_parents[] = {
+ TOP_PARENT(CLK_TOP_XTAL), TOP_PARENT(CLK_TOP_MMPLL_D2),
+};
-static const int eip_b_parents[] = { CK_TOP_CB_CKSQ_40M, CK_TOP_CB_NET2_800M };
+static const struct mtk_parent eip_b_parents[] = {
+ TOP_PARENT(CLK_TOP_XTAL), APMIXED_PARENT(CLK_APMIXED_NET2PLL),
+};
-static const int aud_l_parents[] = { CK_TOP_CB_CKSQ_40M, CK_TOP_CB_APLL2_196M,
- CK_TOP_M_D8_D2 };
+static const struct mtk_parent aud_l_parents[] = {
+ TOP_PARENT(CLK_TOP_XTAL), APMIXED_PARENT(CLK_APMIXED_APLL2),
+ TOP_PARENT(CLK_TOP_MPLL_D8_D2),
+};
-static const int a_tuner_parents[] = { CK_TOP_CB_CKSQ_40M, CK_TOP_APLL2_D4,
- CK_TOP_M_D8_D2 };
+static const struct mtk_parent a_tuner_parents[] = {
+ TOP_PARENT(CLK_TOP_XTAL), TOP_PARENT(CLK_TOP_APLL2_D4),
+ TOP_PARENT(CLK_TOP_MPLL_D8_D2),
+};
-static const int u2u3_sys_parents[] = { CK_TOP_CB_CKSQ_40M, CK_TOP_NET1_D5_D4 };
+static const struct mtk_parent u2u3_sys_parents[] = {
+ TOP_PARENT(CLK_TOP_XTAL), TOP_PARENT(CLK_TOP_NET1PLL_D5_D4),
+};
-static const int da_u2_refsel_parents[] = { CK_TOP_CB_CKSQ_40M,
- CK_TOP_CB_U2_PHYD_CK };
+static const struct mtk_parent da_u2_refsel_parents[] = {
+ TOP_PARENT(CLK_TOP_XTAL), TOP_PARENT(CLK_TOP_MMPLL_U2PHYD),
+};
#define TOP_MUX(_id, _name, _parents, _mux_ofs, _mux_set_ofs, _mux_clr_ofs, \
_shift, _width, _gate, _upd_ofs, _upd) \
@@ -208,199 +231,167 @@
.mux_clr_reg = _mux_clr_ofs, .upd_reg = _upd_ofs, \
.upd_shift = _upd, .mux_shift = _shift, \
.mux_mask = BIT(_width) - 1, .gate_reg = _mux_ofs, \
- .gate_shift = _gate, .parent = _parents, \
+ .gate_shift = _gate, .parent_flags = _parents, \
.num_parents = ARRAY_SIZE(_parents), \
- .flags = CLK_MUX_SETCLR_UPD, \
+ .flags = CLK_MUX_SETCLR_UPD | CLK_PARENT_MIXED, \
}
/* TOPCKGEN MUX_GATE */
static const struct mtk_composite top_muxes[] = {
/* CLK_CFG_0 */
- TOP_MUX(CK_TOP_NFI1X_SEL, "nfi1x_sel", nfi1x_parents, 0x000, 0x004,
+ TOP_MUX(CLK_TOP_NFI1X_SEL, "nfi1x_sel", nfi1x_parents, 0x000, 0x004,
0x008, 0, 3, 7, 0x1C0, 0),
- TOP_MUX(CK_TOP_SPINFI_SEL, "spinfi_sel", spinfi_parents, 0x000, 0x004,
+ TOP_MUX(CLK_TOP_SPINFI_SEL, "spinfi_sel", spinfi_parents, 0x000, 0x004,
0x008, 8, 3, 15, 0x1C0, 1),
- TOP_MUX(CK_TOP_SPI_SEL, "spi_sel", spi_parents, 0x000, 0x004, 0x008, 16,
+ TOP_MUX(CLK_TOP_SPI_SEL, "spi_sel", spi_parents, 0x000, 0x004, 0x008, 16,
3, 23, 0x1C0, 2),
- TOP_MUX(CK_TOP_SPIM_MST_SEL, "spim_mst_sel", spi_parents, 0x000, 0x004,
+ TOP_MUX(CLK_TOP_SPIM_MST_SEL, "spim_mst_sel", spi_parents, 0x000, 0x004,
0x008, 24, 3, 31, 0x1C0, 3),
/* CLK_CFG_1 */
- TOP_MUX(CK_TOP_UART_SEL, "uart_sel", uart_parents, 0x010, 0x014, 0x018,
+ TOP_MUX(CLK_TOP_UART_SEL, "uart_sel", uart_parents, 0x010, 0x014, 0x018,
0, 2, 7, 0x1C0, 4),
- TOP_MUX(CK_TOP_PWM_SEL, "pwm_sel", pwm_parents, 0x010, 0x014, 0x018, 8,
+ TOP_MUX(CLK_TOP_PWM_SEL, "pwm_sel", pwm_parents, 0x010, 0x014, 0x018, 8,
2, 15, 0x1C0, 5),
- TOP_MUX(CK_TOP_I2C_SEL, "i2c_sel", i2c_parents, 0x010, 0x014, 0x018, 16,
+ TOP_MUX(CLK_TOP_I2C_SEL, "i2c_sel", i2c_parents, 0x010, 0x014, 0x018, 16,
2, 23, 0x1C0, 6),
- TOP_MUX(CK_TOP_PEXTP_TL_SEL, "pextp_tl_ck_sel", pextp_tl_ck_parents,
+ TOP_MUX(CLK_TOP_PEXTP_TL_SEL, "pextp_tl_ck_sel", pextp_tl_ck_parents,
0x010, 0x014, 0x018, 24, 2, 31, 0x1C0, 7),
/* CLK_CFG_2 */
- TOP_MUX(CK_TOP_EMMC_250M_SEL, "emmc_250m_sel", emmc_250m_parents, 0x020,
+ TOP_MUX(CLK_TOP_EMMC_250M_SEL, "emmc_250m_sel", emmc_250m_parents, 0x020,
0x024, 0x028, 0, 1, 7, 0x1C0, 8),
- TOP_MUX(CK_TOP_EMMC_416M_SEL, "emmc_416m_sel", emmc_416m_parents, 0x020,
+ TOP_MUX(CLK_TOP_EMMC_416M_SEL, "emmc_416m_sel", emmc_416m_parents, 0x020,
0x024, 0x028, 8, 1, 15, 0x1C0, 9),
- TOP_MUX(CK_TOP_F_26M_ADC_SEL, "f_26m_adc_sel", f_26m_adc_parents, 0x020,
+ TOP_MUX(CLK_TOP_F_26M_ADC_SEL, "f_26m_adc_sel", f_26m_adc_parents, 0x020,
0x024, 0x028, 16, 1, 23, 0x1C0, 10),
- TOP_MUX(CK_TOP_DRAMC_SEL, "dramc_sel", f_26m_adc_parents, 0x020, 0x024,
+ TOP_MUX(CLK_TOP_DRAMC_SEL, "dramc_sel", f_26m_adc_parents, 0x020, 0x024,
0x028, 24, 1, 31, 0x1C0, 11),
/* CLK_CFG_3 */
- TOP_MUX(CK_TOP_DRAMC_MD32_SEL, "dramc_md32_sel", dramc_md32_parents,
+ TOP_MUX(CLK_TOP_DRAMC_MD32_SEL, "dramc_md32_sel", dramc_md32_parents,
0x030, 0x034, 0x038, 0, 1, 7, 0x1C0, 12),
- TOP_MUX(CK_TOP_SYSAXI_SEL, "sysaxi_sel", sysaxi_parents, 0x030, 0x034,
+ TOP_MUX(CLK_TOP_SYSAXI_SEL, "sysaxi_sel", sysaxi_parents, 0x030, 0x034,
0x038, 8, 2, 15, 0x1C0, 13),
- TOP_MUX(CK_TOP_SYSAPB_SEL, "sysapb_sel", sysapb_parents, 0x030, 0x034,
+ TOP_MUX(CLK_TOP_SYSAPB_SEL, "sysapb_sel", sysapb_parents, 0x030, 0x034,
0x038, 16, 2, 23, 0x1C0, 14),
- TOP_MUX(CK_TOP_ARM_DB_MAIN_SEL, "arm_db_main_sel", arm_db_main_parents,
+ TOP_MUX(CLK_TOP_ARM_DB_MAIN_SEL, "arm_db_main_sel", arm_db_main_parents,
0x030, 0x034, 0x038, 24, 1, 31, 0x1C0, 15),
/* CLK_CFG_4 */
- TOP_MUX(CK_TOP_ARM_DB_JTSEL, "arm_db_jtsel", arm_db_jtsel_parents,
+ TOP_MUX(CLK_TOP_ARM_DB_JTSEL, "arm_db_jtsel", arm_db_jtsel_parents,
0x040, 0x044, 0x048, 0, 1, 7, 0x1C0, 16),
- TOP_MUX(CK_TOP_NETSYS_SEL, "netsys_sel", netsys_parents, 0x040, 0x044,
+ TOP_MUX(CLK_TOP_NETSYS_SEL, "netsys_sel", netsys_parents, 0x040, 0x044,
0x048, 8, 1, 15, 0x1C0, 17),
- TOP_MUX(CK_TOP_NETSYS_500M_SEL, "netsys_500m_sel", netsys_500m_parents,
+ TOP_MUX(CLK_TOP_NETSYS_500M_SEL, "netsys_500m_sel", netsys_500m_parents,
0x040, 0x044, 0x048, 16, 1, 23, 0x1C0, 18),
- TOP_MUX(CK_TOP_NETSYS_MCU_SEL, "netsys_mcu_sel", netsys_mcu_parents,
+ TOP_MUX(CLK_TOP_NETSYS_MCU_SEL, "netsys_mcu_sel", netsys_mcu_parents,
0x040, 0x044, 0x048, 24, 3, 31, 0x1C0, 19),
/* CLK_CFG_5 */
- TOP_MUX(CK_TOP_NETSYS_2X_SEL, "netsys_2x_sel", netsys_2x_parents, 0x050,
+ TOP_MUX(CLK_TOP_NETSYS_2X_SEL, "netsys_2x_sel", netsys_2x_parents, 0x050,
0x054, 0x058, 0, 2, 7, 0x1C0, 20),
- TOP_MUX(CK_TOP_SGM_325M_SEL, "sgm_325m_sel", sgm_325m_parents, 0x050,
+ TOP_MUX(CLK_TOP_SGM_325M_SEL, "sgm_325m_sel", sgm_325m_parents, 0x050,
0x054, 0x058, 8, 1, 15, 0x1C0, 21),
- TOP_MUX(CK_TOP_SGM_REG_SEL, "sgm_reg_sel", sgm_reg_parents, 0x050,
+ TOP_MUX(CLK_TOP_SGM_REG_SEL, "sgm_reg_sel", sgm_reg_parents, 0x050,
0x054, 0x058, 16, 1, 23, 0x1C0, 22),
- TOP_MUX(CK_TOP_A1SYS_SEL, "a1sys_sel", a1sys_parents, 0x050, 0x054,
+ TOP_MUX(CLK_TOP_A1SYS_SEL, "a1sys_sel", a1sys_parents, 0x050, 0x054,
0x058, 24, 1, 31, 0x1C0, 23),
/* CLK_CFG_6 */
- TOP_MUX(CK_TOP_CONN_MCUSYS_SEL, "conn_mcusys_sel", conn_mcusys_parents,
+ TOP_MUX(CLK_TOP_CONN_MCUSYS_SEL, "conn_mcusys_sel", conn_mcusys_parents,
0x060, 0x064, 0x068, 0, 1, 7, 0x1C0, 24),
- TOP_MUX(CK_TOP_EIP_B_SEL, "eip_b_sel", eip_b_parents, 0x060, 0x064,
+ TOP_MUX(CLK_TOP_EIP_B_SEL, "eip_b_sel", eip_b_parents, 0x060, 0x064,
0x068, 8, 1, 15, 0x1C0, 25),
- TOP_MUX(CK_TOP_PCIE_PHY_SEL, "pcie_phy_sel", f_26m_adc_parents, 0x060,
+ TOP_MUX(CLK_TOP_PCIE_PHY_SEL, "pcie_phy_sel", f_26m_adc_parents, 0x060,
0x064, 0x068, 16, 1, 23, 0x1C0, 26),
- TOP_MUX(CK_TOP_USB3_PHY_SEL, "usb3_phy_sel", f_26m_adc_parents, 0x060,
+ TOP_MUX(CLK_TOP_USB3_PHY_SEL, "usb3_phy_sel", f_26m_adc_parents, 0x060,
0x064, 0x068, 24, 1, 31, 0x1C0, 27),
/* CLK_CFG_7 */
- TOP_MUX(CK_TOP_F26M_SEL, "csw_f26m_sel", f_26m_adc_parents, 0x070,
+ TOP_MUX(CLK_TOP_F26M_SEL, "csw_f26m_sel", f_26m_adc_parents, 0x070,
0x074, 0x078, 0, 1, 7, 0x1C0, 28),
- TOP_MUX(CK_TOP_AUD_L_SEL, "aud_l_sel", aud_l_parents, 0x070, 0x074,
+ TOP_MUX(CLK_TOP_AUD_L_SEL, "aud_l_sel", aud_l_parents, 0x070, 0x074,
0x078, 8, 2, 15, 0x1C0, 29),
- TOP_MUX(CK_TOP_A_TUNER_SEL, "a_tuner_sel", a_tuner_parents, 0x070,
+ TOP_MUX(CLK_TOP_A_TUNER_SEL, "a_tuner_sel", a_tuner_parents, 0x070,
0x074, 0x078, 16, 2, 23, 0x1C0, 30),
- TOP_MUX(CK_TOP_U2U3_SEL, "u2u3_sel", f_26m_adc_parents, 0x070, 0x074,
+ TOP_MUX(CLK_TOP_U2U3_SEL, "u2u3_sel", f_26m_adc_parents, 0x070, 0x074,
0x078, 24, 1, 31, 0x1C4, 0),
/* CLK_CFG_8 */
- TOP_MUX(CK_TOP_U2U3_SYS_SEL, "u2u3_sys_sel", u2u3_sys_parents, 0x080,
+ TOP_MUX(CLK_TOP_U2U3_SYS_SEL, "u2u3_sys_sel", u2u3_sys_parents, 0x080,
0x084, 0x088, 0, 1, 7, 0x1C4, 1),
- TOP_MUX(CK_TOP_U2U3_XHCI_SEL, "u2u3_xhci_sel", u2u3_sys_parents, 0x080,
+ TOP_MUX(CLK_TOP_U2U3_XHCI_SEL, "u2u3_xhci_sel", u2u3_sys_parents, 0x080,
0x084, 0x088, 8, 1, 15, 0x1C4, 2),
- TOP_MUX(CK_TOP_DA_U2_REFSEL, "da_u2_refsel", da_u2_refsel_parents,
+ TOP_MUX(CLK_TOP_DA_U2_REFSEL, "da_u2_refsel", da_u2_refsel_parents,
0x080, 0x084, 0x088, 16, 1, 23, 0x1C4, 3),
- TOP_MUX(CK_TOP_DA_U2_CK_1P_SEL, "da_u2_ck_1p_sel", da_u2_refsel_parents,
+ TOP_MUX(CLK_TOP_DA_U2_CK_1P_SEL, "da_u2_ck_1p_sel", da_u2_refsel_parents,
0x080, 0x084, 0x088, 24, 1, 31, 0x1C4, 4),
/* CLK_CFG_9 */
- TOP_MUX(CK_TOP_AP2CNN_HOST_SEL, "ap2cnn_host_sel", sgm_reg_parents,
+ TOP_MUX(CLK_TOP_AP2CNN_HOST_SEL, "ap2cnn_host_sel", sgm_reg_parents,
0x090, 0x094, 0x098, 0, 1, 7, 0x1C4, 5),
};
/* INFRA FIXED DIV */
static const struct mtk_fixed_factor infra_fixed_divs[] = {
- TOP_FACTOR(CK_INFRA_CK_F26M, "infra_ck_f26m", CK_TOP_F26M_SEL, 1, 1),
- TOP_FACTOR(CK_INFRA_UART, "infra_uart", CK_TOP_UART_SEL, 1, 1),
- TOP_FACTOR(CK_INFRA_ISPI0, "infra_ispi0", CK_TOP_SPI_SEL, 1, 1),
- TOP_FACTOR(CK_INFRA_I2C, "infra_i2c", CK_TOP_I2C_SEL, 1, 1),
- TOP_FACTOR(CK_INFRA_ISPI1, "infra_ispi1", CK_TOP_SPINFI_SEL, 1, 1),
- TOP_FACTOR(CK_INFRA_PWM, "infra_pwm", CK_TOP_PWM_SEL, 1, 1),
- TOP_FACTOR(CK_INFRA_66M_MCK, "infra_66m_mck", CK_TOP_SYSAXI_SEL, 1, 2),
- TOP_FACTOR(CK_INFRA_CK_F32K, "infra_ck_f32k", CK_TOP_CB_RTC_32P7K, 1,
- 1),
- TOP_FACTOR(CK_INFRA_PCIE_CK, "infra_pcie", CK_TOP_PEXTP_TL_SEL, 1, 1),
- INFRA_FACTOR(CK_INFRA_PWM_BCK, "infra_pwm_bck", CK_INFRA_PWM_BSEL, 1,
- 1),
- INFRA_FACTOR(CK_INFRA_PWM_CK1, "infra_pwm_ck1", CK_INFRA_PWM1_SEL, 1,
- 1),
- INFRA_FACTOR(CK_INFRA_PWM_CK2, "infra_pwm_ck2", CK_INFRA_PWM2_SEL, 1,
- 1),
- TOP_FACTOR(CK_INFRA_133M_HCK, "infra_133m_hck", CK_TOP_SYSAXI, 1, 1),
- TOP_FACTOR(CK_INFRA_EIP_CK, "infra_eip", CK_TOP_EIP_B, 1, 1),
- INFRA_FACTOR(CK_INFRA_66M_PHCK, "infra_66m_phck", CK_INFRA_133M_HCK, 1,
- 1),
- TOP_FACTOR(CK_INFRA_FAUD_L_CK, "infra_faud_l", CK_TOP_AUD_L, 1, 1),
- TOP_FACTOR(CK_INFRA_FAUD_AUD_CK, "infra_faud_aud", CK_TOP_A1SYS, 1, 1),
- TOP_FACTOR(CK_INFRA_FAUD_EG2_CK, "infra_faud_eg2", CK_TOP_A_TUNER, 1,
- 1),
- TOP_FACTOR(CK_INFRA_I2CS_CK, "infra_i2cs", CK_TOP_I2C_BCK, 1, 1),
- INFRA_FACTOR(CK_INFRA_MUX_UART0, "infra_mux_uart0", CK_INFRA_UART0_SEL,
- 1, 1),
- INFRA_FACTOR(CK_INFRA_MUX_UART1, "infra_mux_uart1", CK_INFRA_UART1_SEL,
- 1, 1),
- INFRA_FACTOR(CK_INFRA_MUX_UART2, "infra_mux_uart2", CK_INFRA_UART2_SEL,
- 1, 1),
- TOP_FACTOR(CK_INFRA_NFI_CK, "infra_nfi", CK_TOP_NFI1X, 1, 1),
- TOP_FACTOR(CK_INFRA_SPINFI_CK, "infra_spinfi", CK_TOP_SPINFI_BCK, 1, 1),
- INFRA_FACTOR(CK_INFRA_MUX_SPI0, "infra_mux_spi0", CK_INFRA_SPI0_SEL, 1,
- 1),
- INFRA_FACTOR(CK_INFRA_MUX_SPI1, "infra_mux_spi1", CK_INFRA_SPI1_SEL, 1,
- 1),
- TOP_FACTOR(CK_INFRA_RTC_32K, "infra_rtc_32k", CK_TOP_CB_RTC_32K, 1, 1),
- TOP_FACTOR(CK_INFRA_FMSDC_CK, "infra_fmsdc", CK_TOP_EMMC_416M, 1, 1),
- TOP_FACTOR(CK_INFRA_FMSDC_HCK_CK, "infra_fmsdc_hck", CK_TOP_EMMC_250M,
- 1, 1),
- TOP_FACTOR(CK_INFRA_PERI_133M, "infra_peri_133m", CK_TOP_SYSAXI, 1, 1),
- TOP_FACTOR(CK_INFRA_133M_PHCK, "infra_133m_phck", CK_TOP_SYSAXI, 1, 1),
- TOP_FACTOR(CK_INFRA_USB_SYS_CK, "infra_usb_sys", CK_TOP_U2U3_SYS, 1, 1),
- TOP_FACTOR(CK_INFRA_USB_CK, "infra_usb", CK_TOP_U2U3_REF, 1, 1),
- TOP_FACTOR(CK_INFRA_USB_XHCI_CK, "infra_usb_xhci", CK_TOP_U2U3_XHCI, 1,
- 1),
- TOP_FACTOR(CK_INFRA_PCIE_GFMUX_TL_O_PRE, "infra_pcie_mux",
- CK_TOP_PEXTP_TL, 1, 1),
- TOP_FACTOR(CK_INFRA_F26M_CK0, "infra_f26m_ck0", CK_TOP_F26M, 1, 1),
- TOP_FACTOR(CK_INFRA_HD_133M, "infra_hd_133m", CK_TOP_SYSAXI, 1, 1),
+ TOP_FACTOR(CLK_INFRA_SYSAXI_D2, "infra_sysaxi_d2", CLK_TOP_SYSAXI_SEL, 1, 2),
};
/* INFRASYS MUX PARENTS */
-static const int infra_uart0_parents[] = { CK_INFRA_CK_F26M, CK_INFRA_UART };
-static const int infra_spi0_parents[] = { CK_INFRA_I2C, CK_INFRA_ISPI0 };
-static const int infra_spi1_parents[] = { CK_INFRA_I2C, CK_INFRA_ISPI1 };
+static const struct mtk_parent infra_uart0_parents[] = {
+ TOP_PARENT(CLK_TOP_F26M_SEL),
+ TOP_PARENT(CLK_TOP_UART_SEL)
+};
+
+static const struct mtk_parent infra_spi0_parents[] = {
+ TOP_PARENT(CLK_TOP_I2C_SEL),
+ TOP_PARENT(CLK_TOP_SPI_SEL)
+};
-static const int infra_pwm_bsel_parents[] = { CK_INFRA_CK_F32K,
- CK_INFRA_CK_F26M,
- CK_INFRA_66M_MCK, CK_INFRA_PWM };
+static const struct mtk_parent infra_spi1_parents[] = {
+ TOP_PARENT(CLK_TOP_I2C_SEL),
+ TOP_PARENT(CLK_TOP_SPINFI_SEL)
+};
-static const int infra_pcie_parents[] = { CK_INFRA_CK_F32K, CK_INFRA_CK_F26M,
- -1, CK_INFRA_PCIE_CK };
+static const struct mtk_parent infra_pwm_bsel_parents[] = {
+ TOP_PARENT(CLK_TOP_RTC_32P7K),
+ TOP_PARENT(CLK_TOP_F26M_SEL),
+ INFRA_PARENT(CLK_INFRA_SYSAXI_D2),
+ TOP_PARENT(CLK_TOP_PWM_SEL)
+};
+
+static const struct mtk_parent infra_pcie_parents[] = {
+ TOP_PARENT(CLK_TOP_RTC_32P7K),
+ TOP_PARENT(CLK_TOP_F26M_SEL),
+ TOP_PARENT(CLK_TOP_XTAL),
+ TOP_PARENT(CLK_TOP_PEXTP_TL_SEL)
+};
#define INFRA_MUX(_id, _name, _parents, _reg, _shift, _width) \
{ \
.id = _id, .mux_reg = (_reg) + 0x8, \
.mux_set_reg = (_reg) + 0x0, .mux_clr_reg = (_reg) + 0x4, \
.mux_shift = _shift, .mux_mask = BIT(_width) - 1, \
- .parent = _parents, .num_parents = ARRAY_SIZE(_parents), \
- .flags = CLK_MUX_SETCLR_UPD | CLK_PARENT_INFRASYS, \
+ .parent_flags = _parents, .num_parents = ARRAY_SIZE(_parents), \
+ .flags = CLK_MUX_SETCLR_UPD | CLK_PARENT_MIXED, \
}
/* INFRA MUX */
static const struct mtk_composite infra_muxes[] = {
/* MODULE_CLK_SEL_0 */
- INFRA_MUX(CK_INFRA_UART0_SEL, "infra_uart0_sel", infra_uart0_parents,
+ INFRA_MUX(CLK_INFRA_UART0_SEL, "infra_uart0_sel", infra_uart0_parents,
0x10, 0, 1),
- INFRA_MUX(CK_INFRA_UART1_SEL, "infra_uart1_sel", infra_uart0_parents,
+ INFRA_MUX(CLK_INFRA_UART1_SEL, "infra_uart1_sel", infra_uart0_parents,
0x10, 1, 1),
- INFRA_MUX(CK_INFRA_UART2_SEL, "infra_uart2_sel", infra_uart0_parents,
+ INFRA_MUX(CLK_INFRA_UART2_SEL, "infra_uart2_sel", infra_uart0_parents,
0x10, 2, 1),
- INFRA_MUX(CK_INFRA_SPI0_SEL, "infra_spi0_sel", infra_spi0_parents, 0x10,
+ INFRA_MUX(CLK_INFRA_SPI0_SEL, "infra_spi0_sel", infra_spi0_parents, 0x10,
4, 1),
- INFRA_MUX(CK_INFRA_SPI1_SEL, "infra_spi1_sel", infra_spi1_parents, 0x10,
+ INFRA_MUX(CLK_INFRA_SPI1_SEL, "infra_spi1_sel", infra_spi1_parents, 0x10,
5, 1),
- INFRA_MUX(CK_INFRA_PWM1_SEL, "infra_pwm1_sel", infra_pwm_bsel_parents,
+ INFRA_MUX(CLK_INFRA_PWM1_SEL, "infra_pwm1_sel", infra_pwm_bsel_parents,
0x10, 9, 2),
- INFRA_MUX(CK_INFRA_PWM2_SEL, "infra_pwm2_sel", infra_pwm_bsel_parents,
+ INFRA_MUX(CLK_INFRA_PWM2_SEL, "infra_pwm2_sel", infra_pwm_bsel_parents,
0x10, 11, 2),
- INFRA_MUX(CK_INFRA_PWM_BSEL, "infra_pwm_bsel", infra_pwm_bsel_parents,
+ INFRA_MUX(CLK_INFRA_PWM_BSEL, "infra_pwm_bsel", infra_pwm_bsel_parents,
0x10, 13, 2),
/* MODULE_CLK_SEL_1 */
- INFRA_MUX(CK_INFRA_PCIE_SEL, "infra_pcie_sel", infra_pcie_parents, 0x20,
+ INFRA_MUX(CLK_INFRA_PCIE_SEL, "infra_pcie_sel", infra_pcie_parents, 0x20,
0, 2),
};
@@ -422,113 +413,131 @@
.sta_ofs = 0x68,
};
-#define GATE_INFRA0(_id, _name, _parent, _shift) \
+#define GATE_INFRA0(_id, _name, _parent, _shift, _flags) \
{ \
.id = _id, .parent = _parent, .regs = &infra_0_cg_regs, \
.shift = _shift, \
- .flags = CLK_GATE_SETCLR | CLK_PARENT_INFRASYS, \
+ .flags = _flags, \
}
+#define GATE_INFRA0_INFRA(_id, _name, _parent, _shift) \
+ GATE_INFRA0(_id, _name, _parent, _shift, CLK_GATE_SETCLR | CLK_PARENT_INFRASYS)
+#define GATE_INFRA0_TOP(_id, _name, _parent, _shift) \
+ GATE_INFRA0(_id, _name, _parent, _shift, CLK_GATE_SETCLR | CLK_PARENT_TOPCKGEN)
-#define GATE_INFRA1(_id, _name, _parent, _shift) \
+#define GATE_INFRA1(_id, _name, _parent, _shift, _flags) \
{ \
.id = _id, .parent = _parent, .regs = &infra_1_cg_regs, \
.shift = _shift, \
- .flags = CLK_GATE_SETCLR | CLK_PARENT_INFRASYS, \
+ .flags = _flags, \
}
+#define GATE_INFRA1_INFRA(_id, _name, _parent, _shift) \
+ GATE_INFRA1(_id, _name, _parent, _shift, CLK_GATE_SETCLR | CLK_PARENT_INFRASYS)
+#define GATE_INFRA1_TOP(_id, _name, _parent, _shift) \
+ GATE_INFRA1(_id, _name, _parent, _shift, CLK_GATE_SETCLR | CLK_PARENT_TOPCKGEN)
-#define GATE_INFRA2(_id, _name, _parent, _shift) \
+#define GATE_INFRA2(_id, _name, _parent, _shift, _flags) \
{ \
.id = _id, .parent = _parent, .regs = &infra_2_cg_regs, \
.shift = _shift, \
- .flags = CLK_GATE_SETCLR | CLK_PARENT_INFRASYS, \
+ .flags = _flags, \
}
+#define GATE_INFRA2_INFRA(_id, _name, _parent, _shift) \
+ GATE_INFRA2(_id, _name, _parent, _shift, CLK_GATE_SETCLR | CLK_PARENT_INFRASYS)
+#define GATE_INFRA2_TOP(_id, _name, _parent, _shift) \
+ GATE_INFRA2(_id, _name, _parent, _shift, CLK_GATE_SETCLR | CLK_PARENT_TOPCKGEN)
/* INFRA GATE */
-static const struct mtk_gate infracfg_ao_gates[] = {
+static const struct mtk_gate infracfg_gates[] = {
/* INFRA0 */
- GATE_INFRA0(CK_INFRA_GPT_STA, "infra_gpt_sta", CK_INFRA_66M_MCK, 0),
- GATE_INFRA0(CK_INFRA_PWM_HCK, "infra_pwm_hck", CK_INFRA_66M_MCK, 1),
- GATE_INFRA0(CK_INFRA_PWM_STA, "infra_pwm_sta", CK_INFRA_PWM_BCK, 2),
- GATE_INFRA0(CK_INFRA_PWM1_CK, "infra_pwm1", CK_INFRA_PWM_CK1, 3),
- GATE_INFRA0(CK_INFRA_PWM2_CK, "infra_pwm2", CK_INFRA_PWM_CK2, 4),
- GATE_INFRA0(CK_INFRA_CQ_DMA_CK, "infra_cq_dma", CK_INFRA_133M_HCK, 6),
- GATE_INFRA0(CK_INFRA_EIP97_CK, "infra_eip97", CK_INFRA_EIP_CK, 7),
- GATE_INFRA0(CK_INFRA_AUD_BUS_CK, "infra_aud_bus", CK_INFRA_66M_PHCK, 8),
- GATE_INFRA0(CK_INFRA_AUD_26M_CK, "infra_aud_26m", CK_INFRA_CK_F26M, 9),
- GATE_INFRA0(CK_INFRA_AUD_L_CK, "infra_aud_l", CK_INFRA_FAUD_L_CK, 10),
- GATE_INFRA0(CK_INFRA_AUD_AUD_CK, "infra_aud_aud", CK_INFRA_FAUD_AUD_CK,
- 11),
- GATE_INFRA0(CK_INFRA_AUD_EG2_CK, "infra_aud_eg2", CK_INFRA_FAUD_EG2_CK,
- 13),
- GATE_INFRA0(CK_INFRA_DRAMC_26M_CK, "infra_dramc_26m", CK_INFRA_CK_F26M,
- 14),
- GATE_INFRA0(CK_INFRA_DBG_CK, "infra_dbg", CK_INFRA_66M_MCK, 15),
- GATE_INFRA0(CK_INFRA_AP_DMA_CK, "infra_ap_dma", CK_INFRA_66M_MCK, 16),
- GATE_INFRA0(CK_INFRA_SEJ_CK, "infra_sej", CK_INFRA_66M_MCK, 24),
- GATE_INFRA0(CK_INFRA_SEJ_13M_CK, "infra_sej_13m", CK_INFRA_CK_F26M, 25),
- GATE_INFRA0(CK_INFRA_TRNG_CK, "infra_trng", CK_INFRA_HD_133M, 26),
+ GATE_INFRA0_INFRA(CLK_INFRA_GPT_STA, "infra_gpt_sta", CLK_INFRA_SYSAXI_D2, 0),
+ GATE_INFRA0_INFRA(CLK_INFRA_PWM_HCK, "infra_pwm_hck", CLK_INFRA_SYSAXI_D2, 1),
+ GATE_INFRA0_INFRA(CLK_INFRA_PWM_STA, "infra_pwm_sta", CLK_INFRA_PWM_BSEL, 2),
+ GATE_INFRA0_INFRA(CLK_INFRA_PWM1_CK, "infra_pwm1", CLK_INFRA_PWM1_SEL, 3),
+ GATE_INFRA0_INFRA(CLK_INFRA_PWM2_CK, "infra_pwm2", CLK_INFRA_PWM2_SEL, 4),
+ GATE_INFRA0_TOP(CLK_INFRA_CQ_DMA_CK, "infra_cq_dma", CLK_TOP_SYSAXI_SEL, 6),
+ GATE_INFRA0_TOP(CLK_INFRA_EIP97_CK, "infra_eip97", CLK_TOP_EIP_B_SEL, 7),
+ GATE_INFRA0_TOP(CLK_INFRA_AUD_BUS_CK, "infra_aud_bus", CLK_TOP_SYSAXI_SEL, 8),
+ GATE_INFRA0_TOP(CLK_INFRA_AUD_26M_CK, "infra_aud_26m", CLK_TOP_F26M_SEL, 9),
+ GATE_INFRA0_TOP(CLK_INFRA_AUD_L_CK, "infra_aud_l", CLK_TOP_AUD_L_SEL, 10),
+ GATE_INFRA0_TOP(CLK_INFRA_AUD_AUD_CK, "infra_aud_aud", CLK_TOP_A1SYS_SEL,
+ 11),
+ GATE_INFRA0_TOP(CLK_INFRA_AUD_EG2_CK, "infra_aud_eg2", CLK_TOP_A_TUNER_SEL,
+ 13),
+ GATE_INFRA0_TOP(CLK_INFRA_DRAMC_26M_CK, "infra_dramc_26m", CLK_TOP_F26M_SEL,
+ 14),
+ GATE_INFRA0_INFRA(CLK_INFRA_DBG_CK, "infra_dbg", CLK_INFRA_SYSAXI_D2, 15),
+ GATE_INFRA0_INFRA(CLK_INFRA_AP_DMA_CK, "infra_ap_dma", CLK_INFRA_SYSAXI_D2, 16),
+ GATE_INFRA0_INFRA(CLK_INFRA_SEJ_CK, "infra_sej", CLK_INFRA_SYSAXI_D2, 24),
+ GATE_INFRA0_TOP(CLK_INFRA_SEJ_13M_CK, "infra_sej_13m", CLK_TOP_F26M_SEL, 25),
/* INFRA1 */
- GATE_INFRA1(CK_INFRA_THERM_CK, "infra_therm", CK_INFRA_CK_F26M, 0),
- GATE_INFRA1(CK_INFRA_I2CO_CK, "infra_i2co", CK_INFRA_I2CS_CK, 1),
- GATE_INFRA1(CK_INFRA_UART0_CK, "infra_uart0", CK_INFRA_MUX_UART0, 2),
- GATE_INFRA1(CK_INFRA_UART1_CK, "infra_uart1", CK_INFRA_MUX_UART1, 3),
- GATE_INFRA1(CK_INFRA_UART2_CK, "infra_uart2", CK_INFRA_MUX_UART2, 4),
- GATE_INFRA1(CK_INFRA_NFI1_CK, "infra_nfi1", CK_INFRA_NFI_CK, 8),
- GATE_INFRA1(CK_INFRA_SPINFI1_CK, "infra_spinfi1", CK_INFRA_SPINFI_CK,
- 9),
- GATE_INFRA1(CK_INFRA_NFI_HCK_CK, "infra_nfi_hck", CK_INFRA_66M_MCK, 10),
- GATE_INFRA1(CK_INFRA_SPI0_CK, "infra_spi0", CK_INFRA_MUX_SPI0, 11),
- GATE_INFRA1(CK_INFRA_SPI1_CK, "infra_spi1", CK_INFRA_MUX_SPI1, 12),
- GATE_INFRA1(CK_INFRA_SPI0_HCK_CK, "infra_spi0_hck", CK_INFRA_66M_MCK,
- 13),
- GATE_INFRA1(CK_INFRA_SPI1_HCK_CK, "infra_spi1_hck", CK_INFRA_66M_MCK,
- 14),
- GATE_INFRA1(CK_INFRA_FRTC_CK, "infra_frtc", CK_INFRA_RTC_32K, 15),
- GATE_INFRA1(CK_INFRA_MSDC_CK, "infra_msdc", CK_INFRA_FMSDC_CK, 16),
- GATE_INFRA1(CK_INFRA_MSDC_HCK_CK, "infra_msdc_hck",
- CK_INFRA_FMSDC_HCK_CK, 17),
- GATE_INFRA1(CK_INFRA_MSDC_133M_CK, "infra_msdc_133m",
- CK_INFRA_PERI_133M, 18),
- GATE_INFRA1(CK_INFRA_MSDC_66M_CK, "infra_msdc_66m", CK_INFRA_66M_PHCK,
- 19),
- GATE_INFRA1(CK_INFRA_ADC_26M_CK, "infra_adc_26m", CK_INFRA_CK_F26M, 20),
- GATE_INFRA1(CK_INFRA_ADC_FRC_CK, "infra_adc_frc", CK_INFRA_CK_F26M, 21),
- GATE_INFRA1(CK_INFRA_FBIST2FPC_CK, "infra_fbist2fpc", CK_INFRA_NFI_CK,
- 23),
+ GATE_INFRA1_TOP(CLK_INFRA_THERM_CK, "infra_therm", CLK_TOP_F26M_SEL, 0),
+ GATE_INFRA1_TOP(CLK_INFRA_I2C0_CK, "infra_i2co", CLK_TOP_I2C_SEL, 1),
+ GATE_INFRA1_INFRA(CLK_INFRA_UART0_CK, "infra_uart0", CLK_INFRA_UART0_SEL, 2),
+ GATE_INFRA1_INFRA(CLK_INFRA_UART1_CK, "infra_uart1", CLK_INFRA_UART1_SEL, 3),
+ GATE_INFRA1_INFRA(CLK_INFRA_UART2_CK, "infra_uart2", CLK_INFRA_UART2_SEL, 4),
+ GATE_INFRA1_TOP(CLK_INFRA_NFI1_CK, "infra_nfi1", CLK_TOP_NFI1X_SEL, 8),
+ GATE_INFRA1_TOP(CLK_INFRA_SPINFI1_CK, "infra_spinfi1", CLK_TOP_SPINFI_SEL,
+ 9),
+ GATE_INFRA1_INFRA(CLK_INFRA_NFI_HCK_CK, "infra_nfi_hck", CLK_INFRA_SYSAXI_D2, 10),
+ GATE_INFRA1_INFRA(CLK_INFRA_SPI0_CK, "infra_spi0", CLK_INFRA_SPI0_SEL, 11),
+ GATE_INFRA1_INFRA(CLK_INFRA_SPI1_CK, "infra_spi1", CLK_INFRA_SPI1_SEL, 12),
+ GATE_INFRA1_INFRA(CLK_INFRA_SPI0_HCK_CK, "infra_spi0_hck", CLK_INFRA_SYSAXI_D2,
+ 13),
+ GATE_INFRA1_INFRA(CLK_INFRA_SPI1_HCK_CK, "infra_spi1_hck", CLK_INFRA_SYSAXI_D2,
+ 14),
+ GATE_INFRA1_TOP(CLK_INFRA_FRTC_CK, "infra_frtc", CLK_TOP_RTC_32K, 15),
+ GATE_INFRA1_TOP(CLK_INFRA_MSDC_CK, "infra_msdc", CLK_TOP_EMMC_416M_SEL, 16),
+ GATE_INFRA1_TOP(CLK_INFRA_MSDC_HCK_CK, "infra_msdc_hck",
+ CLK_TOP_EMMC_250M_SEL, 17),
+ GATE_INFRA1_TOP(CLK_INFRA_MSDC_133M_CK, "infra_msdc_133m",
+ CLK_TOP_SYSAXI_SEL, 18),
+ GATE_INFRA1_INFRA(CLK_INFRA_MSDC_66M_CK, "infra_msdc_66m", CLK_INFRA_SYSAXI_D2,
+ 19),
+ GATE_INFRA1_INFRA(CLK_INFRA_ADC_26M_CK, "infra_adc_26m", CLK_INFRA_ADC_FRC_CK, 20),
+ GATE_INFRA1_TOP(CLK_INFRA_ADC_FRC_CK, "infra_adc_frc", CLK_TOP_F26M_SEL, 21),
+ GATE_INFRA1_TOP(CLK_INFRA_FBIST2FPC_CK, "infra_fbist2fpc", CLK_TOP_NFI1X_SEL,
+ 23),
/* INFRA2 */
- GATE_INFRA2(CK_INFRA_IUSB_133_CK, "infra_iusb_133", CK_INFRA_133M_PHCK,
- 0),
- GATE_INFRA2(CK_INFRA_IUSB_66M_CK, "infra_iusb_66m", CK_INFRA_66M_PHCK,
- 1),
- GATE_INFRA2(CK_INFRA_IUSB_SYS_CK, "infra_iusb_sys", CK_INFRA_USB_SYS_CK,
- 2),
- GATE_INFRA2(CK_INFRA_IUSB_CK, "infra_iusb", CK_INFRA_USB_CK, 3),
- GATE_INFRA2(CK_INFRA_IPCIE_CK, "infra_ipcie", CK_INFRA_PCIE_CK, 13),
- GATE_INFRA2(CK_INFRA_IPCIER_CK, "infra_ipcier", CK_INFRA_F26M_CK0, 15),
- GATE_INFRA2(CK_INFRA_IPCIEB_CK, "infra_ipcieb", CK_INFRA_133M_PHCK, 15),
+ GATE_INFRA2_TOP(CLK_INFRA_IUSB_133_CK, "infra_iusb_133", CLK_TOP_SYSAXI_SEL,
+ 0),
+ GATE_INFRA2_INFRA(CLK_INFRA_IUSB_66M_CK, "infra_iusb_66m", CLK_INFRA_SYSAXI_D2,
+ 1),
+ GATE_INFRA2_TOP(CLK_INFRA_IUSB_SYS_CK, "infra_iusb_sys", CLK_TOP_U2U3_SYS_SEL,
+ 2),
+ GATE_INFRA2_TOP(CLK_INFRA_IUSB_CK, "infra_iusb", CLK_TOP_U2U3_SEL, 3),
+ GATE_INFRA2_TOP(CLK_INFRA_IPCIE_CK, "infra_ipcie", CLK_TOP_PEXTP_TL_SEL, 12),
+ GATE_INFRA2_TOP(CLK_INFRA_IPCIE_PIPE_CK, "infra_ipcie_pipe", CLK_TOP_XTAL, 13),
+ GATE_INFRA2_TOP(CLK_INFRA_IPCIER_CK, "infra_ipcier", CLK_TOP_F26M_SEL, 14),
+ GATE_INFRA2_TOP(CLK_INFRA_IPCIEB_CK, "infra_ipcieb", CLK_TOP_SYSAXI_SEL, 15),
+ /* upstream linux unordered */
+ GATE_INFRA0_TOP(CLK_INFRA_TRNG_CK, "infra_trng", CLK_TOP_SYSAXI_SEL, 26),
};
static const struct mtk_clk_tree mt7986_fixed_pll_clk_tree = {
.fdivs_offs = CLK_APMIXED_NR_CLK,
.xtal_rate = 40 * MHZ,
.fclks = fixed_pll_clks,
+ .flags = CLK_APMIXED,
};
static const struct mtk_clk_tree mt7986_topckgen_clk_tree = {
- .fdivs_offs = CK_TOP_CB_M_416M,
- .muxes_offs = CK_TOP_NFI1X_SEL,
+ .fdivs_offs = CLK_TOP_XTAL_D2,
+ .muxes_offs = CLK_TOP_NFI1X_SEL,
.fclks = top_fixed_clks,
.fdivs = top_fixed_divs,
.muxes = top_muxes,
- .flags = CLK_BYPASS_XTAL,
+ .flags = CLK_BYPASS_XTAL | CLK_TOPCKGEN,
};
static const struct mtk_clk_tree mt7986_infracfg_clk_tree = {
- .fdivs_offs = CK_INFRA_CK_F26M,
- .muxes_offs = CK_INFRA_UART0_SEL,
+ .fdivs_offs = CLK_INFRA_SYSAXI_D2,
+ .muxes_offs = CLK_INFRA_UART0_SEL,
+ .gates_offs = CLK_INFRA_GPT_STA,
.fdivs = infra_fixed_divs,
.muxes = infra_muxes,
+ .gates = infracfg_gates,
+ .flags = CLK_INFRASYS,
};
static const struct udevice_id mt7986_fixed_pll_compat[] = {
@@ -582,22 +591,11 @@
{}
};
-static const struct udevice_id mt7986_infracfg_ao_compat[] = {
- { .compatible = "mediatek,mt7986-infracfg_ao" },
- {}
-};
-
static int mt7986_infracfg_probe(struct udevice *dev)
{
- return mtk_common_clk_init(dev, &mt7986_infracfg_clk_tree);
+ return mtk_common_clk_infrasys_init(dev, &mt7986_infracfg_clk_tree);
}
-static int mt7986_infracfg_ao_probe(struct udevice *dev)
-{
- return mtk_common_clk_gate_init(dev, &mt7986_infracfg_clk_tree,
- infracfg_ao_gates);
-}
-
U_BOOT_DRIVER(mtk_clk_infracfg) = {
.name = "mt7986-clock-infracfg",
.id = UCLASS_CLK,
@@ -608,16 +606,6 @@
.flags = DM_FLAG_PRE_RELOC,
};
-U_BOOT_DRIVER(mtk_clk_infracfg_ao) = {
- .name = "mt7986-clock-infracfg-ao",
- .id = UCLASS_CLK,
- .of_match = mt7986_infracfg_ao_compat,
- .probe = mt7986_infracfg_ao_probe,
- .priv_auto = sizeof(struct mtk_cg_priv),
- .ops = &mtk_clk_gate_ops,
- .flags = DM_FLAG_PRE_RELOC,
-};
-
/* ethsys */
static const struct mtk_gate_regs eth_cg_regs = {
.sta_ofs = 0x30,
@@ -631,11 +619,11 @@
}
static const struct mtk_gate eth_cgs[] = {
- GATE_ETH(CK_ETH_FE_EN, "eth_fe_en", CK_TOP_NETSYS_2X, 7),
- GATE_ETH(CK_ETH_GP2_EN, "eth_gp2_en", CK_TOP_SGM_325M, 8),
- GATE_ETH(CK_ETH_GP1_EN, "eth_gp1_en", CK_TOP_SGM_325M, 8),
- GATE_ETH(CK_ETH_WOCPU1_EN, "eth_wocpu1_en", CK_TOP_NETSYS_WED_MCU, 14),
- GATE_ETH(CK_ETH_WOCPU0_EN, "eth_wocpu0_en", CK_TOP_NETSYS_WED_MCU, 15),
+ GATE_ETH(CLK_ETH_FE_EN, "eth_fe_en", CLK_TOP_NETSYS_2X_SEL, 7),
+ GATE_ETH(CLK_ETH_GP2_EN, "eth_gp2_en", CLK_TOP_SGM_325M_SEL, 8),
+ GATE_ETH(CLK_ETH_GP1_EN, "eth_gp1_en", CLK_TOP_SGM_325M_SEL, 8),
+ GATE_ETH(CLK_ETH_WOCPU1_EN, "eth_wocpu1_en", CLK_TOP_NETSYS_MCU_SEL, 14),
+ GATE_ETH(CLK_ETH_WOCPU0_EN, "eth_wocpu0_en", CLK_TOP_NETSYS_MCU_SEL, 15),
};
static int mt7986_ethsys_probe(struct udevice *dev)
diff --git a/drivers/clk/mediatek/clk-mt7988.c b/drivers/clk/mediatek/clk-mt7988.c
index 32b0451..8f4e8f4 100644
--- a/drivers/clk/mediatek/clk-mt7988.c
+++ b/drivers/clk/mediatek/clk-mt7988.c
@@ -35,225 +35,243 @@
/* FIXED PLLS */
static const struct mtk_fixed_clk apmixedsys_mtk_plls[] = {
- FIXED_CLK(CK_APMIXED_NETSYSPLL, CLK_XTAL, 850000000),
- FIXED_CLK(CK_APMIXED_MPLL, CLK_XTAL, 416000000),
- FIXED_CLK(CK_APMIXED_MMPLL, CLK_XTAL, 720000000),
- FIXED_CLK(CK_APMIXED_APLL2, CLK_XTAL, 196608000),
- FIXED_CLK(CK_APMIXED_NET1PLL, CLK_XTAL, 2500000000),
- FIXED_CLK(CK_APMIXED_NET2PLL, CLK_XTAL, 800000000),
- FIXED_CLK(CK_APMIXED_WEDMCUPLL, CLK_XTAL, 208000000),
- FIXED_CLK(CK_APMIXED_SGMPLL, CLK_XTAL, 325000000),
- FIXED_CLK(CK_APMIXED_ARM_B, CLK_XTAL, 1500000000),
- FIXED_CLK(CK_APMIXED_CCIPLL2_B, CLK_XTAL, 960000000),
- FIXED_CLK(CK_APMIXED_USXGMIIPLL, CLK_XTAL, 644533000),
- FIXED_CLK(CK_APMIXED_MSDCPLL, CLK_XTAL, 400000000),
+ FIXED_CLK(CLK_APMIXED_NETSYSPLL, CLK_XTAL, 850000000),
+ FIXED_CLK(CLK_APMIXED_MPLL, CLK_XTAL, 416000000),
+ FIXED_CLK(CLK_APMIXED_MMPLL, CLK_XTAL, 720000000),
+ FIXED_CLK(CLK_APMIXED_APLL2, CLK_XTAL, 196608000),
+ FIXED_CLK(CLK_APMIXED_NET1PLL, CLK_XTAL, 2500000000),
+ FIXED_CLK(CLK_APMIXED_NET2PLL, CLK_XTAL, 800000000),
+ FIXED_CLK(CLK_APMIXED_WEDMCUPLL, CLK_XTAL, 208000000),
+ FIXED_CLK(CLK_APMIXED_SGMPLL, CLK_XTAL, 325000000),
+ FIXED_CLK(CLK_APMIXED_ARM_B, CLK_XTAL, 1500000000),
+ FIXED_CLK(CLK_APMIXED_CCIPLL2_B, CLK_XTAL, 960000000),
+ FIXED_CLK(CLK_APMIXED_USXGMIIPLL, CLK_XTAL, 644533000),
+ FIXED_CLK(CLK_APMIXED_MSDCPLL, CLK_XTAL, 400000000),
};
+/* TOPCKGEN FIXED CLK */
+static const struct mtk_fixed_clk topckgen_mtk_fixed_clks[] = {
+ FIXED_CLK(CLK_TOP_XTAL, CLK_XTAL, 40000000),
+};
+
/* TOPCKGEN FIXED DIV */
static const struct mtk_fixed_factor topckgen_mtk_fixed_factors[] = {
- XTAL_FACTOR(CK_TOP_CB_CKSQ_40M, "cb_cksq_40m", CLK_XTAL, 1, 1),
- PLL_FACTOR(CK_TOP_CB_M_416M, "cb_m_416m", CK_APMIXED_MPLL, 1, 1),
- PLL_FACTOR(CK_TOP_CB_M_D2, "cb_m_d2", CK_APMIXED_MPLL, 1, 2),
- PLL_FACTOR(CK_TOP_M_D3_D2, "m_d3_d2", CK_APMIXED_MPLL, 1, 2),
- PLL_FACTOR(CK_TOP_CB_M_D4, "cb_m_d4", CK_APMIXED_MPLL, 1, 4),
- PLL_FACTOR(CK_TOP_CB_M_D8, "cb_m_d8", CK_APMIXED_MPLL, 1, 8),
- PLL_FACTOR(CK_TOP_M_D8_D2, "m_d8_d2", CK_APMIXED_MPLL, 1, 16),
- PLL_FACTOR(CK_TOP_CB_MM_720M, "cb_mm_720m", CK_APMIXED_MMPLL, 1, 1),
- PLL_FACTOR(CK_TOP_CB_MM_D2, "cb_mm_d2", CK_APMIXED_MMPLL, 1, 2),
- PLL_FACTOR(CK_TOP_CB_MM_D3_D5, "cb_mm_d3_d5", CK_APMIXED_MMPLL, 1, 15),
- PLL_FACTOR(CK_TOP_CB_MM_D4, "cb_mm_d4", CK_APMIXED_MMPLL, 1, 4),
- PLL_FACTOR(CK_TOP_MM_D6_D2, "mm_d6_d2", CK_APMIXED_MMPLL, 1, 12),
- PLL_FACTOR(CK_TOP_CB_MM_D8, "cb_mm_d8", CK_APMIXED_MMPLL, 1, 8),
- PLL_FACTOR(CK_TOP_CB_APLL2_196M, "cb_apll2_196m", CK_APMIXED_APLL2, 1,
- 1),
- PLL_FACTOR(CK_TOP_CB_APLL2_D4, "cb_apll2_d4", CK_APMIXED_APLL2, 1, 4),
- PLL_FACTOR(CK_TOP_CB_NET1_D4, "cb_net1_d4", CK_APMIXED_NET1PLL, 1, 4),
- PLL_FACTOR(CK_TOP_CB_NET1_D5, "cb_net1_d5", CK_APMIXED_NET1PLL, 1, 5),
- PLL_FACTOR(CK_TOP_NET1_D5_D2, "net1_d5_d2", CK_APMIXED_NET1PLL, 1, 10),
- PLL_FACTOR(CK_TOP_NET1_D5_D4, "net1_d5_d4", CK_APMIXED_NET1PLL, 1, 20),
- PLL_FACTOR(CK_TOP_CB_NET1_D8, "cb_net1_d8", CK_APMIXED_NET1PLL, 1, 8),
- PLL_FACTOR(CK_TOP_NET1_D8_D2, "net1_d8_d2", CK_APMIXED_NET1PLL, 1, 16),
- PLL_FACTOR(CK_TOP_NET1_D8_D4, "net1_d8_d4", CK_APMIXED_NET1PLL, 1, 32),
- PLL_FACTOR(CK_TOP_NET1_D8_D8, "net1_d8_d8", CK_APMIXED_NET1PLL, 1, 64),
- PLL_FACTOR(CK_TOP_NET1_D8_D16, "net1_d8_d16", CK_APMIXED_NET1PLL, 1,
- 128),
- PLL_FACTOR(CK_TOP_CB_NET2_800M, "cb_net2_800m", CK_APMIXED_NET2PLL, 1,
- 1),
- PLL_FACTOR(CK_TOP_CB_NET2_D2, "cb_net2_d2", CK_APMIXED_NET2PLL, 1, 2),
- PLL_FACTOR(CK_TOP_CB_NET2_D4, "cb_net2_d4", CK_APMIXED_NET2PLL, 1, 4),
- PLL_FACTOR(CK_TOP_NET2_D4_D4, "net2_d4_d4", CK_APMIXED_NET2PLL, 1, 16),
- PLL_FACTOR(CK_TOP_NET2_D4_D8, "net2_d4_d8", CK_APMIXED_NET2PLL, 1, 32),
- PLL_FACTOR(CK_TOP_CB_NET2_D6, "cb_net2_d6", CK_APMIXED_NET2PLL, 1, 6),
- PLL_FACTOR(CK_TOP_CB_NET2_D8, "cb_net2_d8", CK_APMIXED_NET2PLL, 1, 8),
- PLL_FACTOR(CK_TOP_CB_WEDMCU_208M, "cb_wedmcu_208m",
- CK_APMIXED_WEDMCUPLL, 1, 1),
- PLL_FACTOR(CK_TOP_CB_SGM_325M, "cb_sgm_325m", CK_APMIXED_SGMPLL, 1, 1),
- PLL_FACTOR(CK_TOP_CB_NETSYS_850M, "cb_netsys_850m",
- CK_APMIXED_NETSYSPLL, 1, 1),
- PLL_FACTOR(CK_TOP_CB_MSDC_400M, "cb_msdc_400m", CK_APMIXED_MSDCPLL, 1,
- 1),
- TOP_FACTOR(CK_TOP_CKSQ_40M_D2, "cksq_40m_d2", CK_TOP_CB_CKSQ_40M, 1, 2),
- TOP_FACTOR(CK_TOP_CB_RTC_32K, "cb_rtc_32k", CK_TOP_CB_CKSQ_40M, 1,
+ TOP_FACTOR(CLK_TOP_XTAL_D2, "xtal_d2", CLK_TOP_XTAL, 1, 2),
+ TOP_FACTOR(CLK_TOP_RTC_32K, "rtc_32k", CLK_TOP_XTAL, 1,
1250),
- TOP_FACTOR(CK_TOP_CB_RTC_32P7K, "cb_rtc_32p7k", CK_TOP_CB_CKSQ_40M, 1,
+ TOP_FACTOR(CLK_TOP_RTC_32P7K, "rtc_32p7k", CLK_TOP_XTAL, 1,
1220),
- TOP_FACTOR(CK_TOP_INFRA_F32K, "csw_infra_f32k", CK_TOP_CB_RTC_32P7K, 1,
- 1),
- XTAL_FACTOR(CK_TOP_CKSQ_SRC, "cksq_src", CLK_XTAL, 1, 1),
- TOP_FACTOR(CK_TOP_NETSYS_2X, "netsys_2x", CK_TOP_NETSYS_2X_SEL, 1, 1),
- TOP_FACTOR(CK_TOP_NETSYS_GSW, "netsys_gsw", CK_TOP_NETSYS_GSW_SEL, 1,
- 1),
- TOP_FACTOR(CK_TOP_NETSYS_WED_MCU, "netsys_wed_mcu",
- CK_TOP_NETSYS_MCU_SEL, 1, 1),
- TOP_FACTOR(CK_TOP_EIP197, "eip197", CK_TOP_EIP197_SEL, 1, 1),
- TOP_FACTOR(CK_TOP_EMMC_250M, "emmc_250m", CK_TOP_EMMC_250M_SEL, 1, 1),
- TOP_FACTOR(CK_TOP_EMMC_400M, "emmc_400m", CK_TOP_EMMC_400M_SEL, 1, 1),
- TOP_FACTOR(CK_TOP_SPI, "spi", CK_TOP_SPI_SEL, 1, 1),
- TOP_FACTOR(CK_TOP_SPIM_MST, "spim_mst", CK_TOP_SPIM_MST_SEL, 1, 1),
- TOP_FACTOR(CK_TOP_NFI1X, "nfi1x", CK_TOP_NFI1X_SEL, 1, 1),
- TOP_FACTOR(CK_TOP_SPINFI_BCK, "spinfi_bck", CK_TOP_SPINFI_SEL, 1, 1),
- TOP_FACTOR(CK_TOP_I2C_BCK, "i2c_bck", CK_TOP_I2C_SEL, 1, 1),
- TOP_FACTOR(CK_TOP_USB_SYS, "usb_sys", CK_TOP_USB_SYS_SEL, 1, 1),
- TOP_FACTOR(CK_TOP_USB_SYS_P1, "usb_sys_p1", CK_TOP_USB_SYS_P1_SEL, 1,
- 1),
- TOP_FACTOR(CK_TOP_USB_XHCI, "usb_xhci", CK_TOP_USB_XHCI_SEL, 1, 1),
- TOP_FACTOR(CK_TOP_USB_XHCI_P1, "usb_xhci_p1", CK_TOP_USB_XHCI_P1_SEL, 1,
- 1),
- TOP_FACTOR(CK_TOP_USB_FRMCNT, "usb_frmcnt", CK_TOP_USB_FRMCNT_SEL, 1,
- 1),
- TOP_FACTOR(CK_TOP_USB_FRMCNT_P1, "usb_frmcnt_p1",
- CK_TOP_USB_FRMCNT_P1_SEL, 1, 1),
- TOP_FACTOR(CK_TOP_AUD, "aud", CK_TOP_AUD_SEL, 1, 1),
- TOP_FACTOR(CK_TOP_A1SYS, "a1sys", CK_TOP_A1SYS_SEL, 1, 1),
- TOP_FACTOR(CK_TOP_AUD_L, "aud_l", CK_TOP_AUD_L_SEL, 1, 1),
- TOP_FACTOR(CK_TOP_A_TUNER, "a_tuner", CK_TOP_A_TUNER_SEL, 1, 1),
- TOP_FACTOR(CK_TOP_SYSAXI, "sysaxi", CK_TOP_SYSAXI_SEL, 1, 1),
- TOP_FACTOR(CK_TOP_INFRA_F26M, "csw_infra_f26m", CK_TOP_INFRA_F26M_SEL,
- 1, 1),
- TOP_FACTOR(CK_TOP_USB_REF, "usb_ref", CK_TOP_CKSQ_SRC, 1, 1),
- TOP_FACTOR(CK_TOP_USB_CK_P1, "usb_ck_p1", CK_TOP_CKSQ_SRC, 1, 1),
+ PLL_FACTOR(CLK_TOP_MPLL_D2, "mpll_d2", CLK_APMIXED_MPLL, 1, 2),
+ PLL_FACTOR(CLK_TOP_MPLL_D3_D2, "mpll_d3_d2", CLK_APMIXED_MPLL, 1, 2),
+ PLL_FACTOR(CLK_TOP_MPLL_D4, "mpll_d4", CLK_APMIXED_MPLL, 1, 4),
+ PLL_FACTOR(CLK_TOP_MPLL_D8, "mpll_d8", CLK_APMIXED_MPLL, 1, 8),
+ PLL_FACTOR(CLK_TOP_MPLL_D8_D2, "mpll_d8_d2", CLK_APMIXED_MPLL, 1, 16),
+ PLL_FACTOR(CLK_TOP_MMPLL_D2, "mmpll_d2", CLK_APMIXED_MMPLL, 1, 2),
+ PLL_FACTOR(CLK_TOP_MMPLL_D3_D5, "mmpll_d3_d5", CLK_APMIXED_MMPLL, 1, 15),
+ PLL_FACTOR(CLK_TOP_MMPLL_D4, "mmpll_d4", CLK_APMIXED_MMPLL, 1, 4),
+ PLL_FACTOR(CLK_TOP_MMPLL_D6_D2, "mmpll_d6_d2", CLK_APMIXED_MMPLL, 1, 12),
+ PLL_FACTOR(CLK_TOP_MMPLL_D8, "mmpll_d8", CLK_APMIXED_MMPLL, 1, 8),
+ PLL_FACTOR(CLK_TOP_APLL2_D4, "apll2_d4", CLK_APMIXED_APLL2, 1, 4),
+ PLL_FACTOR(CLK_TOP_NET1PLL_D4, "net1pll_d4", CLK_APMIXED_NET1PLL, 1, 4),
+ PLL_FACTOR(CLK_TOP_NET1PLL_D5, "net1pll_d5", CLK_APMIXED_NET1PLL, 1, 5),
+ PLL_FACTOR(CLK_TOP_NET1PLL_D5_D2, "net1pll_d5_d2", CLK_APMIXED_NET1PLL, 1, 10),
+ PLL_FACTOR(CLK_TOP_NET1PLL_D5_D4, "net1pll_d5_d4", CLK_APMIXED_NET1PLL, 1, 20),
+ PLL_FACTOR(CLK_TOP_NET1PLL_D8, "net1pll_d8", CLK_APMIXED_NET1PLL, 1, 8),
+ PLL_FACTOR(CLK_TOP_NET1PLL_D8_D2, "net1pll_d8_d2", CLK_APMIXED_NET1PLL, 1, 16),
+ PLL_FACTOR(CLK_TOP_NET1PLL_D8_D4, "net1pll_d8_d4", CLK_APMIXED_NET1PLL, 1, 32),
+ PLL_FACTOR(CLK_TOP_NET1PLL_D8_D8, "net1pll_d8_d8", CLK_APMIXED_NET1PLL, 1, 64),
+ PLL_FACTOR(CLK_TOP_NET1PLL_D8_D16, "net1pll_d8_d16", CLK_APMIXED_NET1PLL, 1,
+ 128),
+ PLL_FACTOR(CLK_TOP_NET2PLL_D2, "net2pll_d2", CLK_APMIXED_NET2PLL, 1, 2),
+ PLL_FACTOR(CLK_TOP_NET2PLL_D4, "net2pll_d4", CLK_APMIXED_NET2PLL, 1, 4),
+ PLL_FACTOR(CLK_TOP_NET2PLL_D4_D4, "net2pll_d4_d4", CLK_APMIXED_NET2PLL, 1, 16),
+ PLL_FACTOR(CLK_TOP_NET2PLL_D4_D8, "net2pll_d4_d8", CLK_APMIXED_NET2PLL, 1, 32),
+ PLL_FACTOR(CLK_TOP_NET2PLL_D6, "net2pll_d6", CLK_APMIXED_NET2PLL, 1, 6),
+ PLL_FACTOR(CLK_TOP_NET2PLL_D8, "net2pll_d8", CLK_APMIXED_NET2PLL, 1, 8),
};
/* TOPCKGEN MUX PARENTS */
-static const int netsys_parents[] = { CK_TOP_CB_CKSQ_40M, CK_TOP_CB_NET2_D2,
- CK_TOP_CB_MM_D2 };
+#define APMIXED_PARENT(_id) PARENT(_id, CLK_PARENT_APMIXED)
+#define TOP_PARENT(_id) PARENT(_id, CLK_PARENT_TOPCKGEN)
-static const int netsys_500m_parents[] = { CK_TOP_CB_CKSQ_40M,
- CK_TOP_CB_NET1_D5,
- CK_TOP_NET1_D5_D2 };
+static const struct mtk_parent netsys_parents[] = {
+ TOP_PARENT(CLK_TOP_XTAL), TOP_PARENT(CLK_TOP_NET2PLL_D2),
+ TOP_PARENT(CLK_TOP_MMPLL_D2),
+};
-static const int netsys_2x_parents[] = { CK_TOP_CB_CKSQ_40M,
- CK_TOP_CB_NET2_800M,
- CK_TOP_CB_MM_720M };
+static const struct mtk_parent netsys_500m_parents[] = {
+ TOP_PARENT(CLK_TOP_XTAL), TOP_PARENT(CLK_TOP_NET1PLL_D5),
+ TOP_PARENT(CLK_TOP_NET1PLL_D5_D2),
+};
-static const int netsys_gsw_parents[] = { CK_TOP_CB_CKSQ_40M, CK_TOP_CB_NET1_D4,
- CK_TOP_CB_NET1_D5 };
+static const struct mtk_parent netsys_2x_parents[] = {
+ TOP_PARENT(CLK_TOP_XTAL), APMIXED_PARENT(CLK_APMIXED_NET2PLL),
+ APMIXED_PARENT(CLK_APMIXED_MMPLL),
+};
-static const int eth_gmii_parents[] = { CK_TOP_CB_CKSQ_40M, CK_TOP_NET1_D5_D4 };
+static const struct mtk_parent netsys_gsw_parents[] = {
+ TOP_PARENT(CLK_TOP_XTAL), TOP_PARENT(CLK_TOP_NET1PLL_D4),
+ TOP_PARENT(CLK_TOP_NET1PLL_D5),
+};
-static const int netsys_mcu_parents[] = {
- CK_TOP_CB_CKSQ_40M, CK_TOP_CB_NET2_800M, CK_TOP_CB_MM_720M,
- CK_TOP_CB_NET1_D4, CK_TOP_CB_NET1_D5, CK_TOP_CB_M_416M
+static const struct mtk_parent eth_gmii_parents[] = {
+ TOP_PARENT(CLK_TOP_XTAL), TOP_PARENT(CLK_TOP_NET1PLL_D5_D4),
};
-static const int eip197_parents[] = {
- CK_TOP_CB_CKSQ_40M, CK_TOP_CB_NETSYS_850M, CK_TOP_CB_NET2_800M,
- CK_TOP_CB_MM_720M, CK_TOP_CB_NET1_D4, CK_TOP_CB_NET1_D5
+static const struct mtk_parent netsys_mcu_parents[] = {
+ TOP_PARENT(CLK_TOP_XTAL), APMIXED_PARENT(CLK_APMIXED_NET2PLL),
+ APMIXED_PARENT(CLK_APMIXED_MMPLL), TOP_PARENT(CLK_TOP_NET1PLL_D4),
+ TOP_PARENT(CLK_TOP_NET1PLL_D5), APMIXED_PARENT(CLK_APMIXED_MPLL),
};
-static const int axi_infra_parents[] = { CK_TOP_CB_CKSQ_40M,
- CK_TOP_NET1_D8_D2 };
+static const struct mtk_parent eip197_parents[] = {
+ TOP_PARENT(CLK_TOP_XTAL), APMIXED_PARENT(CLK_APMIXED_NETSYSPLL),
+ APMIXED_PARENT(CLK_APMIXED_NET2PLL), APMIXED_PARENT(CLK_APMIXED_MMPLL),
+ TOP_PARENT(CLK_TOP_NET1PLL_D4), TOP_PARENT(CLK_TOP_NET1PLL_D5),
+};
-static const int uart_parents[] = { CK_TOP_CB_CKSQ_40M, CK_TOP_CB_M_D8,
- CK_TOP_M_D8_D2 };
+static const struct mtk_parent axi_infra_parents[] = {
+ TOP_PARENT(CLK_TOP_XTAL), TOP_PARENT(CLK_TOP_NET1PLL_D8_D2),
+};
-static const int emmc_250m_parents[] = { CK_TOP_CB_CKSQ_40M, CK_TOP_NET1_D5_D2,
- CK_TOP_CB_MM_D4 };
+static const struct mtk_parent uart_parents[] = {
+ TOP_PARENT(CLK_TOP_XTAL), TOP_PARENT(CLK_TOP_MPLL_D8),
+ TOP_PARENT(CLK_TOP_MPLL_D8_D2),
+};
-static const int emmc_400m_parents[] = {
- CK_TOP_CB_CKSQ_40M, CK_TOP_CB_MSDC_400M, CK_TOP_CB_MM_D2,
- CK_TOP_CB_M_D2, CK_TOP_CB_MM_D4, CK_TOP_NET1_D8_D2
+static const struct mtk_parent emmc_250m_parents[] = {
+ TOP_PARENT(CLK_TOP_XTAL), TOP_PARENT(CLK_TOP_NET1PLL_D5_D2),
+ TOP_PARENT(CLK_TOP_MMPLL_D4),
};
-static const int spi_parents[] = { CK_TOP_CB_CKSQ_40M, CK_TOP_CB_M_D2,
- CK_TOP_CB_MM_D4, CK_TOP_NET1_D8_D2,
- CK_TOP_CB_NET2_D6, CK_TOP_NET1_D5_D4,
- CK_TOP_CB_M_D4, CK_TOP_NET1_D8_D4 };
+static const struct mtk_parent emmc_400m_parents[] = {
+ TOP_PARENT(CLK_TOP_XTAL), APMIXED_PARENT(CLK_APMIXED_MSDCPLL),
+ TOP_PARENT(CLK_TOP_MMPLL_D2), TOP_PARENT(CLK_TOP_MPLL_D2),
+ TOP_PARENT(CLK_TOP_MMPLL_D4), TOP_PARENT(CLK_TOP_NET1PLL_D8_D2),
+};
-static const int nfi1x_parents[] = { CK_TOP_CB_CKSQ_40M, CK_TOP_CB_MM_D4,
- CK_TOP_NET1_D8_D2, CK_TOP_CB_NET2_D6,
- CK_TOP_CB_M_D4, CK_TOP_CB_MM_D8,
- CK_TOP_NET1_D8_D4, CK_TOP_CB_M_D8 };
+static const struct mtk_parent spi_parents[] = {
+ TOP_PARENT(CLK_TOP_XTAL), TOP_PARENT(CLK_TOP_MPLL_D2),
+ TOP_PARENT(CLK_TOP_MMPLL_D4), TOP_PARENT(CLK_TOP_NET1PLL_D8_D2),
+ TOP_PARENT(CLK_TOP_NET2PLL_D6), TOP_PARENT(CLK_TOP_NET1PLL_D5_D4),
+ TOP_PARENT(CLK_TOP_MPLL_D4), TOP_PARENT(CLK_TOP_NET1PLL_D8_D4),
+};
-static const int spinfi_parents[] = { CK_TOP_CKSQ_40M_D2, CK_TOP_CB_CKSQ_40M,
- CK_TOP_NET1_D5_D4, CK_TOP_CB_M_D4,
- CK_TOP_CB_MM_D8, CK_TOP_NET1_D8_D4,
- CK_TOP_MM_D6_D2, CK_TOP_CB_M_D8 };
+static const struct mtk_parent nfi1x_parents[] = {
+ TOP_PARENT(CLK_TOP_XTAL), TOP_PARENT(CLK_TOP_MMPLL_D4),
+ TOP_PARENT(CLK_TOP_NET1PLL_D8_D2), TOP_PARENT(CLK_TOP_NET2PLL_D6),
+ TOP_PARENT(CLK_TOP_MPLL_D4), TOP_PARENT(CLK_TOP_MMPLL_D8),
+ TOP_PARENT(CLK_TOP_NET1PLL_D8_D4), TOP_PARENT(CLK_TOP_MPLL_D8),
+};
-static const int pwm_parents[] = { CK_TOP_CB_CKSQ_40M, CK_TOP_NET1_D8_D2,
- CK_TOP_NET1_D5_D4, CK_TOP_CB_M_D4,
- CK_TOP_M_D8_D2, CK_TOP_CB_RTC_32K };
+static const struct mtk_parent spinfi_parents[] = {
+ TOP_PARENT(CLK_TOP_XTAL_D2), TOP_PARENT(CLK_TOP_XTAL),
+ TOP_PARENT(CLK_TOP_NET1PLL_D5_D4), TOP_PARENT(CLK_TOP_MPLL_D4),
+ TOP_PARENT(CLK_TOP_MMPLL_D8), TOP_PARENT(CLK_TOP_NET1PLL_D8_D4),
+ TOP_PARENT(CLK_TOP_MMPLL_D6_D2), TOP_PARENT(CLK_TOP_MPLL_D8),
+};
-static const int i2c_parents[] = { CK_TOP_CB_CKSQ_40M, CK_TOP_NET1_D5_D4,
- CK_TOP_CB_M_D4, CK_TOP_NET1_D8_D4 };
+static const struct mtk_parent pwm_parents[] = {
+ TOP_PARENT(CLK_TOP_XTAL), TOP_PARENT(CLK_TOP_NET1PLL_D8_D2),
+ TOP_PARENT(CLK_TOP_NET1PLL_D5_D4), TOP_PARENT(CLK_TOP_MPLL_D4),
+ TOP_PARENT(CLK_TOP_MPLL_D8_D2), TOP_PARENT(CLK_TOP_RTC_32K),
+};
-static const int pcie_mbist_250m_parents[] = { CK_TOP_CB_CKSQ_40M,
- CK_TOP_NET1_D5_D2 };
+static const struct mtk_parent i2c_parents[] = {
+ TOP_PARENT(CLK_TOP_XTAL), TOP_PARENT(CLK_TOP_NET1PLL_D5_D4),
+ TOP_PARENT(CLK_TOP_MPLL_D4), TOP_PARENT(CLK_TOP_NET1PLL_D8_D4),
+};
-static const int pextp_tl_ck_parents[] = { CK_TOP_CB_CKSQ_40M,
- CK_TOP_CB_NET2_D6, CK_TOP_CB_MM_D8,
- CK_TOP_M_D8_D2, CK_TOP_CB_RTC_32K };
+static const struct mtk_parent pcie_mbist_250m_parents[] = {
+ TOP_PARENT(CLK_TOP_XTAL), TOP_PARENT(CLK_TOP_NET1PLL_D5_D2),
+};
-static const int usb_frmcnt_parents[] = { CK_TOP_CB_CKSQ_40M,
- CK_TOP_CB_MM_D3_D5 };
+static const struct mtk_parent pextp_tl_ck_parents[] = {
+ TOP_PARENT(CLK_TOP_XTAL), TOP_PARENT(CLK_TOP_NET2PLL_D6),
+ TOP_PARENT(CLK_TOP_MMPLL_D8), TOP_PARENT(CLK_TOP_MPLL_D8_D2),
+ TOP_PARENT(CLK_TOP_RTC_32K),
+};
-static const int aud_parents[] = { CK_TOP_CB_CKSQ_40M, CK_TOP_CB_APLL2_196M };
+static const struct mtk_parent usb_frmcnt_parents[] = {
+ TOP_PARENT(CLK_TOP_XTAL), TOP_PARENT(CLK_TOP_MMPLL_D3_D5),
+};
-static const int a1sys_parents[] = { CK_TOP_CB_CKSQ_40M, CK_TOP_CB_APLL2_D4 };
+static const struct mtk_parent aud_parents[] = {
+ TOP_PARENT(CLK_TOP_XTAL), APMIXED_PARENT(CLK_APMIXED_APLL2),
+};
-static const int aud_l_parents[] = { CK_TOP_CB_CKSQ_40M, CK_TOP_CB_APLL2_196M,
- CK_TOP_M_D8_D2 };
+static const struct mtk_parent a1sys_parents[] = {
+ TOP_PARENT(CLK_TOP_XTAL), TOP_PARENT(CLK_TOP_APLL2_D4),
+};
+
+static const struct mtk_parent aud_l_parents[] = {
+ TOP_PARENT(CLK_TOP_XTAL), APMIXED_PARENT(CLK_APMIXED_APLL2),
+ TOP_PARENT(CLK_TOP_MPLL_D8_D2),
+};
-static const int sspxtp_parents[] = { CK_TOP_CKSQ_40M_D2, CK_TOP_M_D8_D2 };
+static const struct mtk_parent sspxtp_parents[] = {
+ TOP_PARENT(CLK_TOP_XTAL_D2), TOP_PARENT(CLK_TOP_MPLL_D8_D2),
+};
-static const int usxgmii_sbus_0_parents[] = { CK_TOP_CB_CKSQ_40M,
- CK_TOP_NET1_D8_D4 };
+static const struct mtk_parent usxgmii_sbus_0_parents[] = {
+ TOP_PARENT(CLK_TOP_XTAL), TOP_PARENT(CLK_TOP_NET1PLL_D8_D4),
+};
-static const int sgm_0_parents[] = { CK_TOP_CB_CKSQ_40M, CK_TOP_CB_SGM_325M };
+static const struct mtk_parent sgm_0_parents[] = {
+ TOP_PARENT(CLK_TOP_XTAL), APMIXED_PARENT(CLK_APMIXED_SGMPLL),
+};
-static const int sysapb_parents[] = { CK_TOP_CB_CKSQ_40M, CK_TOP_M_D3_D2 };
+static const struct mtk_parent sysapb_parents[] = {
+ TOP_PARENT(CLK_TOP_XTAL), TOP_PARENT(CLK_TOP_MPLL_D3_D2),
+};
-static const int eth_refck_50m_parents[] = { CK_TOP_CB_CKSQ_40M,
- CK_TOP_NET2_D4_D4 };
+static const struct mtk_parent eth_refck_50m_parents[] = {
+ TOP_PARENT(CLK_TOP_XTAL), TOP_PARENT(CLK_TOP_NET2PLL_D4_D4),
+};
-static const int eth_sys_200m_parents[] = { CK_TOP_CB_CKSQ_40M,
- CK_TOP_CB_NET2_D4 };
+static const struct mtk_parent eth_sys_200m_parents[] = {
+ TOP_PARENT(CLK_TOP_XTAL), TOP_PARENT(CLK_TOP_NET2PLL_D4),
+};
-static const int eth_xgmii_parents[] = { CK_TOP_CKSQ_40M_D2, CK_TOP_NET1_D8_D8,
- CK_TOP_NET1_D8_D16 };
+static const struct mtk_parent eth_xgmii_parents[] = {
+ TOP_PARENT(CLK_TOP_XTAL_D2), TOP_PARENT(CLK_TOP_NET1PLL_D8_D8),
+ TOP_PARENT(CLK_TOP_NET1PLL_D8_D16),
+};
-static const int bus_tops_parents[] = { CK_TOP_CB_CKSQ_40M, CK_TOP_CB_NET1_D5,
- CK_TOP_CB_NET2_D2 };
+static const struct mtk_parent bus_tops_parents[] = {
+ TOP_PARENT(CLK_TOP_XTAL), TOP_PARENT(CLK_TOP_NET1PLL_D5),
+ TOP_PARENT(CLK_TOP_NET2PLL_D2),
+};
-static const int npu_tops_parents[] = { CK_TOP_CB_CKSQ_40M,
- CK_TOP_CB_NET2_800M };
+static const struct mtk_parent npu_tops_parents[] = {
+ TOP_PARENT(CLK_TOP_XTAL), APMIXED_PARENT(CLK_APMIXED_NET2PLL),
+};
-static const int dramc_md32_parents[] = { CK_TOP_CB_CKSQ_40M, CK_TOP_CB_M_D2,
- CK_TOP_CB_WEDMCU_208M };
+static const struct mtk_parent dramc_md32_parents[] = {
+ TOP_PARENT(CLK_TOP_XTAL), TOP_PARENT(CLK_TOP_MPLL_D2),
+ APMIXED_PARENT(CLK_APMIXED_WEDMCUPLL),
+};
-static const int da_xtp_glb_p0_parents[] = { CK_TOP_CB_CKSQ_40M,
- CK_TOP_CB_NET2_D8 };
+static const struct mtk_parent da_xtp_glb_p0_parents[] = {
+ TOP_PARENT(CLK_TOP_XTAL), TOP_PARENT(CLK_TOP_NET2PLL_D8),
+};
-static const int mcusys_backup_625m_parents[] = { CK_TOP_CB_CKSQ_40M,
- CK_TOP_CB_NET1_D4 };
+static const struct mtk_parent mcusys_backup_625m_parents[] = {
+ TOP_PARENT(CLK_TOP_XTAL), TOP_PARENT(CLK_TOP_NET1PLL_D4),
+};
-static const int macsec_parents[] = { CK_TOP_CB_CKSQ_40M, CK_TOP_CB_SGM_325M,
- CK_TOP_CB_NET1_D8 };
+static const struct mtk_parent macsec_parents[] = {
+ TOP_PARENT(CLK_TOP_XTAL), APMIXED_PARENT(CLK_APMIXED_SGMPLL),
+ TOP_PARENT(CLK_TOP_NET1PLL_D8),
+};
-static const int netsys_tops_400m_parents[] = { CK_TOP_CB_CKSQ_40M,
- CK_TOP_CB_NET2_D2 };
+static const struct mtk_parent netsys_tops_400m_parents[] = {
+ TOP_PARENT(CLK_TOP_XTAL), TOP_PARENT(CLK_TOP_NET2PLL_D2),
+};
-static const int eth_mii_parents[] = { CK_TOP_CKSQ_40M_D2, CK_TOP_NET2_D4_D8 };
+static const struct mtk_parent eth_mii_parents[] = {
+ TOP_PARENT(CLK_TOP_XTAL_D2), TOP_PARENT(CLK_TOP_NET2PLL_D4_D8),
+};
#define TOP_MUX(_id, _name, _parents, _mux_ofs, _mux_set_ofs, _mux_clr_ofs, \
_shift, _width, _gate, _upd_ofs, _upd) \
@@ -262,278 +280,204 @@
.mux_clr_reg = _mux_clr_ofs, .upd_reg = _upd_ofs, \
.upd_shift = _upd, .mux_shift = _shift, \
.mux_mask = BIT(_width) - 1, .gate_reg = _mux_ofs, \
- .gate_shift = _gate, .parent = _parents, \
+ .gate_shift = _gate, .parent_flags = _parents, \
.num_parents = ARRAY_SIZE(_parents), \
- .flags = CLK_MUX_SETCLR_UPD, \
+ .flags = CLK_MUX_SETCLR_UPD | CLK_PARENT_MIXED, \
}
/* TOPCKGEN MUX_GATE */
static const struct mtk_composite topckgen_mtk_muxes[] = {
- TOP_MUX(CK_TOP_NETSYS_SEL, "netsys_sel", netsys_parents, 0x0, 0x4, 0x8,
+ TOP_MUX(CLK_TOP_NETSYS_SEL, "netsys_sel", netsys_parents, 0x0, 0x4, 0x8,
0, 2, 7, 0x1c0, 0),
- TOP_MUX(CK_TOP_NETSYS_500M_SEL, "netsys_500m_sel", netsys_500m_parents,
+ TOP_MUX(CLK_TOP_NETSYS_500M_SEL, "netsys_500m_sel", netsys_500m_parents,
0x0, 0x4, 0x8, 8, 2, 15, 0x1c0, 1),
- TOP_MUX(CK_TOP_NETSYS_2X_SEL, "netsys_2x_sel", netsys_2x_parents, 0x0,
+ TOP_MUX(CLK_TOP_NETSYS_2X_SEL, "netsys_2x_sel", netsys_2x_parents, 0x0,
0x4, 0x8, 16, 2, 23, 0x1c0, 2),
- TOP_MUX(CK_TOP_NETSYS_GSW_SEL, "netsys_gsw_sel", netsys_gsw_parents,
+ TOP_MUX(CLK_TOP_NETSYS_GSW_SEL, "netsys_gsw_sel", netsys_gsw_parents,
0x0, 0x4, 0x8, 24, 2, 31, 0x1c0, 3),
- TOP_MUX(CK_TOP_ETH_GMII_SEL, "eth_gmii_sel", eth_gmii_parents, 0x10,
+ TOP_MUX(CLK_TOP_ETH_GMII_SEL, "eth_gmii_sel", eth_gmii_parents, 0x10,
0x14, 0x18, 0, 1, 7, 0x1c0, 4),
- TOP_MUX(CK_TOP_NETSYS_MCU_SEL, "netsys_mcu_sel", netsys_mcu_parents,
+ TOP_MUX(CLK_TOP_NETSYS_MCU_SEL, "netsys_mcu_sel", netsys_mcu_parents,
0x10, 0x14, 0x18, 8, 3, 15, 0x1c0, 5),
- TOP_MUX(CK_TOP_NETSYS_PAO_2X_SEL, "netsys_pao_2x_sel",
+ TOP_MUX(CLK_TOP_NETSYS_PAO_2X_SEL, "netsys_pao_2x_sel",
netsys_mcu_parents, 0x10, 0x14, 0x18, 16, 3, 23, 0x1c0, 6),
- TOP_MUX(CK_TOP_EIP197_SEL, "eip197_sel", eip197_parents, 0x10, 0x14,
+ TOP_MUX(CLK_TOP_EIP197_SEL, "eip197_sel", eip197_parents, 0x10, 0x14,
0x18, 24, 3, 31, 0x1c0, 7),
- TOP_MUX(CK_TOP_AXI_INFRA_SEL, "axi_infra_sel", axi_infra_parents, 0x20,
+ TOP_MUX(CLK_TOP_AXI_INFRA_SEL, "axi_infra_sel", axi_infra_parents, 0x20,
0x24, 0x28, 0, 1, 7, 0x1c0, 8),
- TOP_MUX(CK_TOP_UART_SEL, "uart_sel", uart_parents, 0x20, 0x24, 0x28, 8,
+ TOP_MUX(CLK_TOP_UART_SEL, "uart_sel", uart_parents, 0x20, 0x24, 0x28, 8,
2, 15, 0x1c0, 9),
- TOP_MUX(CK_TOP_EMMC_250M_SEL, "emmc_250m_sel", emmc_250m_parents, 0x20,
+ TOP_MUX(CLK_TOP_EMMC_250M_SEL, "emmc_250m_sel", emmc_250m_parents, 0x20,
0x24, 0x28, 16, 2, 23, 0x1c0, 10),
- TOP_MUX(CK_TOP_EMMC_400M_SEL, "emmc_400m_sel", emmc_400m_parents, 0x20,
+ TOP_MUX(CLK_TOP_EMMC_400M_SEL, "emmc_400m_sel", emmc_400m_parents, 0x20,
0x24, 0x28, 24, 3, 31, 0x1c0, 11),
- TOP_MUX(CK_TOP_SPI_SEL, "spi_sel", spi_parents, 0x30, 0x34, 0x38, 0, 3,
+ TOP_MUX(CLK_TOP_SPI_SEL, "spi_sel", spi_parents, 0x30, 0x34, 0x38, 0, 3,
7, 0x1c0, 12),
- TOP_MUX(CK_TOP_SPIM_MST_SEL, "spim_mst_sel", spi_parents, 0x30, 0x34,
+ TOP_MUX(CLK_TOP_SPIM_MST_SEL, "spim_mst_sel", spi_parents, 0x30, 0x34,
0x38, 8, 3, 15, 0x1c0, 13),
- TOP_MUX(CK_TOP_NFI1X_SEL, "nfi1x_sel", nfi1x_parents, 0x30, 0x34, 0x38,
+ TOP_MUX(CLK_TOP_NFI1X_SEL, "nfi1x_sel", nfi1x_parents, 0x30, 0x34, 0x38,
16, 3, 23, 0x1c0, 14),
- TOP_MUX(CK_TOP_SPINFI_SEL, "spinfi_sel", spinfi_parents, 0x30, 0x34,
+ TOP_MUX(CLK_TOP_SPINFI_SEL, "spinfi_sel", spinfi_parents, 0x30, 0x34,
0x38, 24, 3, 31, 0x1c0, 15),
- TOP_MUX(CK_TOP_PWM_SEL, "pwm_sel", pwm_parents, 0x40, 0x44, 0x48, 0, 3,
+ TOP_MUX(CLK_TOP_PWM_SEL, "pwm_sel", pwm_parents, 0x40, 0x44, 0x48, 0, 3,
7, 0x1c0, 16),
- TOP_MUX(CK_TOP_I2C_SEL, "i2c_sel", i2c_parents, 0x40, 0x44, 0x48, 8, 2,
+ TOP_MUX(CLK_TOP_I2C_SEL, "i2c_sel", i2c_parents, 0x40, 0x44, 0x48, 8, 2,
15, 0x1c0, 17),
- TOP_MUX(CK_TOP_PCIE_MBIST_250M_SEL, "pcie_mbist_250m_sel",
+ TOP_MUX(CLK_TOP_PCIE_MBIST_250M_SEL, "pcie_mbist_250m_sel",
pcie_mbist_250m_parents, 0x40, 0x44, 0x48, 16, 1, 23, 0x1c0,
18),
- TOP_MUX(CK_TOP_PEXTP_TL_SEL, "pextp_tl_ck_sel", pextp_tl_ck_parents,
+ TOP_MUX(CLK_TOP_PEXTP_TL_SEL, "pextp_tl_ck_sel", pextp_tl_ck_parents,
0x40, 0x44, 0x48, 24, 3, 31, 0x1c0, 19),
- TOP_MUX(CK_TOP_PEXTP_TL_P1_SEL, "pextp_tl_ck_p1_sel",
+ TOP_MUX(CLK_TOP_PEXTP_TL_P1_SEL, "pextp_tl_ck_p1_sel",
pextp_tl_ck_parents, 0x50, 0x54, 0x58, 0, 3, 7, 0x1c0, 20),
- TOP_MUX(CK_TOP_PEXTP_TL_P2_SEL, "pextp_tl_ck_p2_sel",
+ TOP_MUX(CLK_TOP_PEXTP_TL_P2_SEL, "pextp_tl_ck_p2_sel",
pextp_tl_ck_parents, 0x50, 0x54, 0x58, 8, 3, 15, 0x1c0, 21),
- TOP_MUX(CK_TOP_PEXTP_TL_P3_SEL, "pextp_tl_ck_p3_sel",
+ TOP_MUX(CLK_TOP_PEXTP_TL_P3_SEL, "pextp_tl_ck_p3_sel",
pextp_tl_ck_parents, 0x50, 0x54, 0x58, 16, 3, 23, 0x1c0, 22),
- TOP_MUX(CK_TOP_USB_SYS_SEL, "usb_sys_sel", eth_gmii_parents, 0x50, 0x54,
+ TOP_MUX(CLK_TOP_USB_SYS_SEL, "usb_sys_sel", eth_gmii_parents, 0x50, 0x54,
0x58, 24, 1, 31, 0x1c0, 23),
- TOP_MUX(CK_TOP_USB_SYS_P1_SEL, "usb_sys_p1_sel", eth_gmii_parents, 0x60,
+ TOP_MUX(CLK_TOP_USB_SYS_P1_SEL, "usb_sys_p1_sel", eth_gmii_parents, 0x60,
0x64, 0x68, 0, 1, 7, 0x1c0, 24),
- TOP_MUX(CK_TOP_USB_XHCI_SEL, "usb_xhci_sel", eth_gmii_parents, 0x60,
+ TOP_MUX(CLK_TOP_USB_XHCI_SEL, "usb_xhci_sel", eth_gmii_parents, 0x60,
0x64, 0x68, 8, 1, 15, 0x1c0, 25),
- TOP_MUX(CK_TOP_USB_XHCI_P1_SEL, "usb_xhci_p1_sel", eth_gmii_parents,
+ TOP_MUX(CLK_TOP_USB_XHCI_P1_SEL, "usb_xhci_p1_sel", eth_gmii_parents,
0x60, 0x64, 0x68, 16, 1, 23, 0x1c0, 26),
- TOP_MUX(CK_TOP_USB_FRMCNT_SEL, "usb_frmcnt_sel", usb_frmcnt_parents,
+ TOP_MUX(CLK_TOP_USB_FRMCNT_SEL, "usb_frmcnt_sel", usb_frmcnt_parents,
0x60, 0x64, 0x68, 24, 1, 31, 0x1c0, 27),
- TOP_MUX(CK_TOP_USB_FRMCNT_P1_SEL, "usb_frmcnt_p1_sel",
+ TOP_MUX(CLK_TOP_USB_FRMCNT_P1_SEL, "usb_frmcnt_p1_sel",
usb_frmcnt_parents, 0x70, 0x74, 0x78, 0, 1, 7, 0x1c0, 28),
- TOP_MUX(CK_TOP_AUD_SEL, "aud_sel", aud_parents, 0x70, 0x74, 0x78, 8, 1,
+ TOP_MUX(CLK_TOP_AUD_SEL, "aud_sel", aud_parents, 0x70, 0x74, 0x78, 8, 1,
15, 0x1c0, 29),
- TOP_MUX(CK_TOP_A1SYS_SEL, "a1sys_sel", a1sys_parents, 0x70, 0x74, 0x78,
+ TOP_MUX(CLK_TOP_A1SYS_SEL, "a1sys_sel", a1sys_parents, 0x70, 0x74, 0x78,
16, 1, 23, 0x1c0, 30),
- TOP_MUX(CK_TOP_AUD_L_SEL, "aud_l_sel", aud_l_parents, 0x70, 0x74, 0x78,
+ TOP_MUX(CLK_TOP_AUD_L_SEL, "aud_l_sel", aud_l_parents, 0x70, 0x74, 0x78,
24, 2, 31, 0x1c4, 0),
- TOP_MUX(CK_TOP_A_TUNER_SEL, "a_tuner_sel", a1sys_parents, 0x80, 0x84,
+ TOP_MUX(CLK_TOP_A_TUNER_SEL, "a_tuner_sel", a1sys_parents, 0x80, 0x84,
0x88, 0, 1, 7, 0x1c4, 1),
- TOP_MUX(CK_TOP_SSPXTP_SEL, "sspxtp_sel", sspxtp_parents, 0x80, 0x84,
+ TOP_MUX(CLK_TOP_SSPXTP_SEL, "sspxtp_sel", sspxtp_parents, 0x80, 0x84,
0x88, 8, 1, 15, 0x1c4, 2),
- TOP_MUX(CK_TOP_USB_PHY_SEL, "usb_phy_sel", sspxtp_parents, 0x80, 0x84,
+ TOP_MUX(CLK_TOP_USB_PHY_SEL, "usb_phy_sel", sspxtp_parents, 0x80, 0x84,
0x88, 16, 1, 23, 0x1c4, 3),
- TOP_MUX(CK_TOP_USXGMII_SBUS_0_SEL, "usxgmii_sbus_0_sel",
+ TOP_MUX(CLK_TOP_USXGMII_SBUS_0_SEL, "usxgmii_sbus_0_sel",
usxgmii_sbus_0_parents, 0x80, 0x84, 0x88, 24, 1, 31, 0x1c4, 4),
- TOP_MUX(CK_TOP_USXGMII_SBUS_1_SEL, "usxgmii_sbus_1_sel",
+ TOP_MUX(CLK_TOP_USXGMII_SBUS_1_SEL, "usxgmii_sbus_1_sel",
usxgmii_sbus_0_parents, 0x90, 0x94, 0x98, 0, 1, 7, 0x1c4, 5),
- TOP_MUX(CK_TOP_SGM_0_SEL, "sgm_0_sel", sgm_0_parents, 0x90, 0x94, 0x98,
+ TOP_MUX(CLK_TOP_SGM_0_SEL, "sgm_0_sel", sgm_0_parents, 0x90, 0x94, 0x98,
8, 1, 15, 0x1c4, 6),
- TOP_MUX(CK_TOP_SGM_SBUS_0_SEL, "sgm_sbus_0_sel", usxgmii_sbus_0_parents,
+ TOP_MUX(CLK_TOP_SGM_SBUS_0_SEL, "sgm_sbus_0_sel", usxgmii_sbus_0_parents,
0x90, 0x94, 0x98, 16, 1, 23, 0x1c4, 7),
- TOP_MUX(CK_TOP_SGM_1_SEL, "sgm_1_sel", sgm_0_parents, 0x90, 0x94, 0x98,
+ TOP_MUX(CLK_TOP_SGM_1_SEL, "sgm_1_sel", sgm_0_parents, 0x90, 0x94, 0x98,
24, 1, 31, 0x1c4, 8),
- TOP_MUX(CK_TOP_SGM_SBUS_1_SEL, "sgm_sbus_1_sel", usxgmii_sbus_0_parents,
+ TOP_MUX(CLK_TOP_SGM_SBUS_1_SEL, "sgm_sbus_1_sel", usxgmii_sbus_0_parents,
0xa0, 0xa4, 0xa8, 0, 1, 7, 0x1c4, 9),
- TOP_MUX(CK_TOP_XFI_PHY_0_XTAL_SEL, "xfi_phy_0_xtal_sel", sspxtp_parents,
+ TOP_MUX(CLK_TOP_XFI_PHY_0_XTAL_SEL, "xfi_phy_0_xtal_sel", sspxtp_parents,
0xa0, 0xa4, 0xa8, 8, 1, 15, 0x1c4, 10),
- TOP_MUX(CK_TOP_XFI_PHY_1_XTAL_SEL, "xfi_phy_1_xtal_sel", sspxtp_parents,
+ TOP_MUX(CLK_TOP_XFI_PHY_1_XTAL_SEL, "xfi_phy_1_xtal_sel", sspxtp_parents,
0xa0, 0xa4, 0xa8, 16, 1, 23, 0x1c4, 11),
- TOP_MUX(CK_TOP_SYSAXI_SEL, "sysaxi_sel", axi_infra_parents, 0xa0, 0xa4,
+ TOP_MUX(CLK_TOP_SYSAXI_SEL, "sysaxi_sel", axi_infra_parents, 0xa0, 0xa4,
0xa8, 24, 1, 31, 0x1c4, 12),
- TOP_MUX(CK_TOP_SYSAPB_SEL, "sysapb_sel", sysapb_parents, 0xb0, 0xb4,
+ TOP_MUX(CLK_TOP_SYSAPB_SEL, "sysapb_sel", sysapb_parents, 0xb0, 0xb4,
0xb8, 0, 1, 7, 0x1c4, 13),
- TOP_MUX(CK_TOP_ETH_REFCK_50M_SEL, "eth_refck_50m_sel",
+ TOP_MUX(CLK_TOP_ETH_REFCK_50M_SEL, "eth_refck_50m_sel",
eth_refck_50m_parents, 0xb0, 0xb4, 0xb8, 8, 1, 15, 0x1c4, 14),
- TOP_MUX(CK_TOP_ETH_SYS_200M_SEL, "eth_sys_200m_sel",
+ TOP_MUX(CLK_TOP_ETH_SYS_200M_SEL, "eth_sys_200m_sel",
eth_sys_200m_parents, 0xb0, 0xb4, 0xb8, 16, 1, 23, 0x1c4, 15),
- TOP_MUX(CK_TOP_ETH_SYS_SEL, "eth_sys_sel", pcie_mbist_250m_parents,
+ TOP_MUX(CLK_TOP_ETH_SYS_SEL, "eth_sys_sel", pcie_mbist_250m_parents,
0xb0, 0xb4, 0xb8, 24, 1, 31, 0x1c4, 16),
- TOP_MUX(CK_TOP_ETH_XGMII_SEL, "eth_xgmii_sel", eth_xgmii_parents, 0xc0,
+ TOP_MUX(CLK_TOP_ETH_XGMII_SEL, "eth_xgmii_sel", eth_xgmii_parents, 0xc0,
0xc4, 0xc8, 0, 2, 7, 0x1c4, 17),
- TOP_MUX(CK_TOP_BUS_TOPS_SEL, "bus_tops_sel", bus_tops_parents, 0xc0,
+ TOP_MUX(CLK_TOP_BUS_TOPS_SEL, "bus_tops_sel", bus_tops_parents, 0xc0,
0xc4, 0xc8, 8, 2, 15, 0x1c4, 18),
- TOP_MUX(CK_TOP_NPU_TOPS_SEL, "npu_tops_sel", npu_tops_parents, 0xc0,
+ TOP_MUX(CLK_TOP_NPU_TOPS_SEL, "npu_tops_sel", npu_tops_parents, 0xc0,
0xc4, 0xc8, 16, 1, 23, 0x1c4, 19),
- TOP_MUX(CK_TOP_DRAMC_SEL, "dramc_sel", sspxtp_parents, 0xc0, 0xc4, 0xc8,
+ TOP_MUX(CLK_TOP_DRAMC_SEL, "dramc_sel", sspxtp_parents, 0xc0, 0xc4, 0xc8,
24, 1, 31, 0x1c4, 20),
- TOP_MUX(CK_TOP_DRAMC_MD32_SEL, "dramc_md32_sel", dramc_md32_parents,
+ TOP_MUX(CLK_TOP_DRAMC_MD32_SEL, "dramc_md32_sel", dramc_md32_parents,
0xd0, 0xd4, 0xd8, 0, 2, 7, 0x1c4, 21),
- TOP_MUX(CK_TOP_INFRA_F26M_SEL, "csw_infra_f26m_sel", sspxtp_parents,
+ TOP_MUX(CLK_TOP_INFRA_F26M_SEL, "csw_infra_f26m_sel", sspxtp_parents,
0xd0, 0xd4, 0xd8, 8, 1, 15, 0x1c4, 22),
- TOP_MUX(CK_TOP_PEXTP_P0_SEL, "pextp_p0_sel", sspxtp_parents, 0xd0, 0xd4,
+ TOP_MUX(CLK_TOP_PEXTP_P0_SEL, "pextp_p0_sel", sspxtp_parents, 0xd0, 0xd4,
0xd8, 16, 1, 23, 0x1c4, 23),
- TOP_MUX(CK_TOP_PEXTP_P1_SEL, "pextp_p1_sel", sspxtp_parents, 0xd0, 0xd4,
+ TOP_MUX(CLK_TOP_PEXTP_P1_SEL, "pextp_p1_sel", sspxtp_parents, 0xd0, 0xd4,
0xd8, 24, 1, 31, 0x1c4, 24),
- TOP_MUX(CK_TOP_PEXTP_P2_SEL, "pextp_p2_sel", sspxtp_parents, 0xe0, 0xe4,
+ TOP_MUX(CLK_TOP_PEXTP_P2_SEL, "pextp_p2_sel", sspxtp_parents, 0xe0, 0xe4,
0xe8, 0, 1, 7, 0x1c4, 25),
- TOP_MUX(CK_TOP_PEXTP_P3_SEL, "pextp_p3_sel", sspxtp_parents, 0xe0, 0xe4,
+ TOP_MUX(CLK_TOP_PEXTP_P3_SEL, "pextp_p3_sel", sspxtp_parents, 0xe0, 0xe4,
0xe8, 8, 1, 15, 0x1c4, 26),
- TOP_MUX(CK_TOP_DA_XTP_GLB_P0_SEL, "da_xtp_glb_p0_sel",
+ TOP_MUX(CLK_TOP_DA_XTP_GLB_P0_SEL, "da_xtp_glb_p0_sel",
da_xtp_glb_p0_parents, 0xe0, 0xe4, 0xe8, 16, 1, 23, 0x1c4, 27),
- TOP_MUX(CK_TOP_DA_XTP_GLB_P1_SEL, "da_xtp_glb_p1_sel",
+ TOP_MUX(CLK_TOP_DA_XTP_GLB_P1_SEL, "da_xtp_glb_p1_sel",
da_xtp_glb_p0_parents, 0xe0, 0xe4, 0xe8, 24, 1, 31, 0x1c4, 28),
- TOP_MUX(CK_TOP_DA_XTP_GLB_P2_SEL, "da_xtp_glb_p2_sel",
+ TOP_MUX(CLK_TOP_DA_XTP_GLB_P2_SEL, "da_xtp_glb_p2_sel",
da_xtp_glb_p0_parents, 0xf0, 0xf4, 0xf8, 0, 1, 7, 0x1c4, 29),
- TOP_MUX(CK_TOP_DA_XTP_GLB_P3_SEL, "da_xtp_glb_p3_sel",
+ TOP_MUX(CLK_TOP_DA_XTP_GLB_P3_SEL, "da_xtp_glb_p3_sel",
da_xtp_glb_p0_parents, 0xf0, 0xf4, 0xf8, 8, 1, 15, 0x1c4, 30),
- TOP_MUX(CK_TOP_CKM_SEL, "ckm_sel", sspxtp_parents, 0xf0, 0xf4, 0xf8, 16,
+ TOP_MUX(CLK_TOP_CKM_SEL, "ckm_sel", sspxtp_parents, 0xf0, 0xf4, 0xf8, 16,
1, 23, 0x1c8, 0),
- TOP_MUX(CK_TOP_DA_SELM_XTAL_SEL, "da_selm_xtal_sel", sspxtp_parents,
+ TOP_MUX(CLK_TOP_DA_SEL, "da_sel", sspxtp_parents,
0xf0, 0xf4, 0xf8, 24, 1, 31, 0x1c8, 1),
- TOP_MUX(CK_TOP_PEXTP_SEL, "pextp_sel", sspxtp_parents, 0x100, 0x104,
+ TOP_MUX(CLK_TOP_PEXTP_SEL, "pextp_sel", sspxtp_parents, 0x100, 0x104,
0x108, 0, 1, 7, 0x1c8, 2),
- TOP_MUX(CK_TOP_TOPS_P2_26M_SEL, "tops_p2_26m_sel", sspxtp_parents,
+ TOP_MUX(CLK_TOP_TOPS_P2_26M_SEL, "tops_p2_26m_sel", sspxtp_parents,
0x100, 0x104, 0x108, 8, 1, 15, 0x1c8, 3),
- TOP_MUX(CK_TOP_MCUSYS_BACKUP_625M_SEL, "mcusys_backup_625m_sel",
+ TOP_MUX(CLK_TOP_MCUSYS_BACKUP_625M_SEL, "mcusys_backup_625m_sel",
mcusys_backup_625m_parents, 0x100, 0x104, 0x108, 16, 1, 23,
0x1c8, 4),
- TOP_MUX(CK_TOP_NETSYS_SYNC_250M_SEL, "netsys_sync_250m_sel",
+ TOP_MUX(CLK_TOP_NETSYS_SYNC_250M_SEL, "netsys_sync_250m_sel",
pcie_mbist_250m_parents, 0x100, 0x104, 0x108, 24, 1, 31, 0x1c8,
5),
- TOP_MUX(CK_TOP_MACSEC_SEL, "macsec_sel", macsec_parents, 0x110, 0x114,
+ TOP_MUX(CLK_TOP_MACSEC_SEL, "macsec_sel", macsec_parents, 0x110, 0x114,
0x118, 0, 2, 7, 0x1c8, 6),
- TOP_MUX(CK_TOP_NETSYS_TOPS_400M_SEL, "netsys_tops_400m_sel",
+ TOP_MUX(CLK_TOP_NETSYS_TOPS_400M_SEL, "netsys_tops_400m_sel",
netsys_tops_400m_parents, 0x110, 0x114, 0x118, 8, 1, 15, 0x1c8,
7),
- TOP_MUX(CK_TOP_NETSYS_PPEFB_250M_SEL, "netsys_ppefb_250m_sel",
+ TOP_MUX(CLK_TOP_NETSYS_PPEFB_250M_SEL, "netsys_ppefb_250m_sel",
pcie_mbist_250m_parents, 0x110, 0x114, 0x118, 16, 1, 23, 0x1c8,
8),
- TOP_MUX(CK_TOP_NETSYS_WARP_SEL, "netsys_warp_sel", netsys_parents,
+ TOP_MUX(CLK_TOP_NETSYS_WARP_SEL, "netsys_warp_sel", netsys_parents,
0x110, 0x114, 0x118, 24, 2, 31, 0x1c8, 9),
- TOP_MUX(CK_TOP_ETH_MII_SEL, "eth_mii_sel", eth_mii_parents, 0x120,
+ TOP_MUX(CLK_TOP_ETH_MII_SEL, "eth_mii_sel", eth_mii_parents, 0x120,
0x124, 0x128, 0, 1, 7, 0x1c8, 10),
- TOP_MUX(CK_TOP_CK_NPU_SEL_CM_TOPS_SEL, "ck_npu_sel_cm_tops_sel",
+ TOP_MUX(CLK_TOP_NPU_SEL, "ck_npu_sel",
netsys_2x_parents, 0x120, 0x124, 0x128, 8, 2, 15, 0x1c8, 11),
};
-/* INFRA FIXED DIV */
-static const struct mtk_fixed_factor infracfg_mtk_fixed_factor[] = {
- TOP_FACTOR(CK_INFRA_CK_F26M, "infra_ck_f26m", CK_TOP_INFRA_F26M_SEL, 1,
- 1),
- TOP_FACTOR(CK_INFRA_PWM_O, "infra_pwm_o", CK_TOP_PWM_SEL, 1, 1),
- TOP_FACTOR(CK_INFRA_PCIE_OCC_P0, "infra_pcie_ck_occ_p0",
- CK_TOP_PEXTP_TL_SEL, 1, 1),
- TOP_FACTOR(CK_INFRA_PCIE_OCC_P1, "infra_pcie_ck_occ_p1",
- CK_TOP_PEXTP_TL_P1_SEL, 1, 1),
- TOP_FACTOR(CK_INFRA_PCIE_OCC_P2, "infra_pcie_ck_occ_p2",
- CK_TOP_PEXTP_TL_P2_SEL, 1, 1),
- TOP_FACTOR(CK_INFRA_PCIE_OCC_P3, "infra_pcie_ck_occ_p3",
- CK_TOP_PEXTP_TL_P3_SEL, 1, 1),
- TOP_FACTOR(CK_INFRA_133M_HCK, "infra_133m_hck", CK_TOP_SYSAXI, 1, 1),
- INFRA_FACTOR(CK_INFRA_133M_PHCK, "infra_133m_phck", CK_INFRA_133M_HCK,
- 1, 1),
- INFRA_FACTOR(CK_INFRA_66M_PHCK, "infra_66m_phck", CK_INFRA_133M_HCK, 1,
- 1),
- TOP_FACTOR(CK_INFRA_FAUD_L_O, "infra_faud_l_o", CK_TOP_AUD_L, 1, 1),
- TOP_FACTOR(CK_INFRA_FAUD_AUD_O, "infra_faud_aud_o", CK_TOP_A1SYS, 1, 1),
- TOP_FACTOR(CK_INFRA_FAUD_EG2_O, "infra_faud_eg2_o", CK_TOP_A_TUNER, 1,
- 1),
- TOP_FACTOR(CK_INFRA_I2C_O, "infra_i2c_o", CK_TOP_I2C_BCK, 1, 1),
- TOP_FACTOR(CK_INFRA_UART_O0, "infra_uart_o0", CK_TOP_UART_SEL, 1, 1),
- TOP_FACTOR(CK_INFRA_UART_O1, "infra_uart_o1", CK_TOP_UART_SEL, 1, 1),
- TOP_FACTOR(CK_INFRA_UART_O2, "infra_uart_o2", CK_TOP_UART_SEL, 1, 1),
- TOP_FACTOR(CK_INFRA_NFI_O, "infra_nfi_o", CK_TOP_NFI1X, 1, 1),
- TOP_FACTOR(CK_INFRA_SPINFI_O, "infra_spinfi_o", CK_TOP_SPINFI_BCK, 1,
- 1),
- TOP_FACTOR(CK_INFRA_SPI0_O, "infra_spi0_o", CK_TOP_SPI, 1, 1),
- TOP_FACTOR(CK_INFRA_SPI1_O, "infra_spi1_o", CK_TOP_SPIM_MST, 1, 1),
- INFRA_FACTOR(CK_INFRA_LB_MUX_FRTC, "infra_lb_mux_frtc", CK_INFRA_FRTC,
- 1, 1),
- TOP_FACTOR(CK_INFRA_FRTC, "infra_frtc", CK_TOP_CB_RTC_32K, 1, 1),
- TOP_FACTOR(CK_INFRA_FMSDC400_O, "infra_fmsdc400_o", CK_TOP_EMMC_400M, 1,
- 1),
- TOP_FACTOR(CK_INFRA_FMSDC2_HCK_OCC, "infra_fmsdc2_hck_occ",
- CK_TOP_EMMC_250M, 1, 1),
- TOP_FACTOR(CK_INFRA_PERI_133M, "infra_peri_133m", CK_TOP_SYSAXI, 1, 1),
- TOP_FACTOR(CK_INFRA_USB_O, "infra_usb_o", CK_TOP_USB_REF, 1, 1),
- TOP_FACTOR(CK_INFRA_USB_O_P1, "infra_usb_o_p1", CK_TOP_USB_CK_P1, 1, 1),
- TOP_FACTOR(CK_INFRA_USB_FRMCNT_O, "infra_usb_frmcnt_o",
- CK_TOP_USB_FRMCNT, 1, 1),
- TOP_FACTOR(CK_INFRA_USB_FRMCNT_O_P1, "infra_usb_frmcnt_o_p1",
- CK_TOP_USB_FRMCNT_P1, 1, 1),
- TOP_FACTOR(CK_INFRA_USB_XHCI_O, "infra_usb_xhci_o", CK_TOP_USB_XHCI, 1,
- 1),
- TOP_FACTOR(CK_INFRA_USB_XHCI_O_P1, "infra_usb_xhci_o_p1",
- CK_TOP_USB_XHCI_P1, 1, 1),
- XTAL_FACTOR(CK_INFRA_USB_PIPE_O, "infra_usb_pipe_o", CLK_XTAL, 1, 1),
- XTAL_FACTOR(CK_INFRA_USB_PIPE_O_P1, "infra_usb_pipe_o_p1", CLK_XTAL, 1,
- 1),
- XTAL_FACTOR(CK_INFRA_USB_UTMI_O, "infra_usb_utmi_o", CLK_XTAL, 1, 1),
- XTAL_FACTOR(CK_INFRA_USB_UTMI_O_P1, "infra_usb_utmi_o_p1", CLK_XTAL, 1,
- 1),
- XTAL_FACTOR(CK_INFRA_PCIE_PIPE_OCC_P0, "infra_pcie_pipe_ck_occ_p0",
- CLK_XTAL, 1, 1),
- XTAL_FACTOR(CK_INFRA_PCIE_PIPE_OCC_P1, "infra_pcie_pipe_ck_occ_p1",
- CLK_XTAL, 1, 1),
- XTAL_FACTOR(CK_INFRA_PCIE_PIPE_OCC_P2, "infra_pcie_pipe_ck_occ_p2",
- CLK_XTAL, 1, 1),
- XTAL_FACTOR(CK_INFRA_PCIE_PIPE_OCC_P3, "infra_pcie_pipe_ck_occ_p3",
- CLK_XTAL, 1, 1),
- TOP_FACTOR(CK_INFRA_F26M_O0, "infra_f26m_o0", CK_TOP_INFRA_F26M, 1, 1),
- TOP_FACTOR(CK_INFRA_F26M_O1, "infra_f26m_o1", CK_TOP_INFRA_F26M, 1, 1),
- TOP_FACTOR(CK_INFRA_133M_MCK, "infra_133m_mck", CK_TOP_SYSAXI, 1, 1),
- TOP_FACTOR(CK_INFRA_66M_MCK, "infra_66m_mck", CK_TOP_SYSAXI, 1, 1),
- TOP_FACTOR(CK_INFRA_PERI_66M_O, "infra_peri_66m_o", CK_TOP_SYSAXI, 1,
- 1),
- TOP_FACTOR(CK_INFRA_USB_SYS_O, "infra_usb_sys_o", CK_TOP_USB_SYS, 1, 1),
- TOP_FACTOR(CK_INFRA_USB_SYS_O_P1, "infra_usb_sys_o_p1",
- CK_TOP_USB_SYS_P1, 1, 1),
-};
-
/* INFRASYS MUX PARENTS */
-static const int infra_mux_uart0_parents[] = { CK_INFRA_CK_F26M,
- CK_INFRA_UART_O0 };
+static const int infra_mux_uart0_parents[] = { CLK_TOP_INFRA_F26M_SEL,
+ CLK_TOP_UART_SEL };
-static const int infra_mux_uart1_parents[] = { CK_INFRA_CK_F26M,
- CK_INFRA_UART_O1 };
+static const int infra_mux_uart1_parents[] = { CLK_TOP_INFRA_F26M_SEL,
+ CLK_TOP_UART_SEL };
-static const int infra_mux_uart2_parents[] = { CK_INFRA_CK_F26M,
- CK_INFRA_UART_O2 };
+static const int infra_mux_uart2_parents[] = { CLK_TOP_INFRA_F26M_SEL,
+ CLK_TOP_UART_SEL };
-static const int infra_mux_spi0_parents[] = { CK_INFRA_I2C_O, CK_INFRA_SPI0_O };
+static const int infra_mux_spi0_parents[] = { CLK_TOP_I2C_SEL, CLK_TOP_SPI_SEL };
-static const int infra_mux_spi1_parents[] = { CK_INFRA_I2C_O, CK_INFRA_SPI1_O };
+static const int infra_mux_spi1_parents[] = { CLK_TOP_I2C_SEL, CLK_TOP_SPIM_MST_SEL };
-static const int infra_pwm_bck_parents[] = { CK_TOP_INFRA_F32K,
- CK_INFRA_CK_F26M, CK_INFRA_66M_MCK,
- CK_INFRA_PWM_O };
+static const int infra_pwm_bck_parents[] = { CLK_TOP_RTC_32P7K,
+ CLK_TOP_INFRA_F26M_SEL, CLK_TOP_SYSAXI_SEL,
+ CLK_TOP_PWM_SEL };
static const int infra_pcie_gfmux_tl_ck_o_p0_parents[] = {
- CK_TOP_INFRA_F32K, CK_INFRA_CK_F26M, CK_INFRA_CK_F26M,
- CK_INFRA_PCIE_OCC_P0
+ CLK_TOP_RTC_32P7K, CLK_TOP_INFRA_F26M_SEL, CLK_TOP_INFRA_F26M_SEL,
+ CLK_TOP_PEXTP_TL_SEL
};
static const int infra_pcie_gfmux_tl_ck_o_p1_parents[] = {
- CK_TOP_INFRA_F32K, CK_INFRA_CK_F26M, CK_INFRA_CK_F26M,
- CK_INFRA_PCIE_OCC_P1
+ CLK_TOP_RTC_32P7K, CLK_TOP_INFRA_F26M_SEL, CLK_TOP_INFRA_F26M_SEL,
+ CLK_TOP_PEXTP_TL_P1_SEL
};
static const int infra_pcie_gfmux_tl_ck_o_p2_parents[] = {
- CK_TOP_INFRA_F32K, CK_INFRA_CK_F26M, CK_INFRA_CK_F26M,
- CK_INFRA_PCIE_OCC_P2
+ CLK_TOP_RTC_32P7K, CLK_TOP_INFRA_F26M_SEL, CLK_TOP_INFRA_F26M_SEL,
+ CLK_TOP_PEXTP_TL_P2_SEL
};
static const int infra_pcie_gfmux_tl_ck_o_p3_parents[] = {
- CK_TOP_INFRA_F32K, CK_INFRA_CK_F26M, CK_INFRA_CK_F26M,
- CK_INFRA_PCIE_OCC_P3
+ CLK_TOP_RTC_32P7K, CLK_TOP_INFRA_F26M_SEL, CLK_TOP_INFRA_F26M_SEL,
+ CLK_TOP_PEXTP_TL_P3_SEL
};
#define INFRA_MUX(_id, _name, _parents, _reg, _shift, _width) \
@@ -542,51 +486,51 @@
.mux_clr_reg = _reg + 0x4, .mux_shift = _shift, \
.mux_mask = BIT(_width) - 1, .parent = _parents, \
.num_parents = ARRAY_SIZE(_parents), \
- .flags = CLK_MUX_SETCLR_UPD | CLK_PARENT_INFRASYS, \
+ .flags = CLK_MUX_SETCLR_UPD | CLK_PARENT_TOPCKGEN, \
}
/* INFRA MUX */
static const struct mtk_composite infracfg_mtk_mux[] = {
- INFRA_MUX(CK_INFRA_MUX_UART0_SEL, "infra_mux_uart0_sel",
+ INFRA_MUX(CLK_INFRA_MUX_UART0_SEL, "infra_mux_uart0_sel",
infra_mux_uart0_parents, 0x10, 0, 1),
- INFRA_MUX(CK_INFRA_MUX_UART1_SEL, "infra_mux_uart1_sel",
+ INFRA_MUX(CLK_INFRA_MUX_UART1_SEL, "infra_mux_uart1_sel",
infra_mux_uart1_parents, 0x10, 1, 1),
- INFRA_MUX(CK_INFRA_MUX_UART2_SEL, "infra_mux_uart2_sel",
+ INFRA_MUX(CLK_INFRA_MUX_UART2_SEL, "infra_mux_uart2_sel",
infra_mux_uart2_parents, 0x10, 2, 1),
- INFRA_MUX(CK_INFRA_MUX_SPI0_SEL, "infra_mux_spi0_sel",
+ INFRA_MUX(CLK_INFRA_MUX_SPI0_SEL, "infra_mux_spi0_sel",
infra_mux_spi0_parents, 0x10, 4, 1),
- INFRA_MUX(CK_INFRA_MUX_SPI1_SEL, "infra_mux_spi1_sel",
+ INFRA_MUX(CLK_INFRA_MUX_SPI1_SEL, "infra_mux_spi1_sel",
infra_mux_spi1_parents, 0x10, 5, 1),
- INFRA_MUX(CK_INFRA_MUX_SPI2_SEL, "infra_mux_spi2_sel",
+ INFRA_MUX(CLK_INFRA_MUX_SPI2_SEL, "infra_mux_spi2_sel",
infra_mux_spi0_parents, 0x10, 6, 1),
- INFRA_MUX(CK_INFRA_PWM_SEL, "infra_pwm_sel", infra_pwm_bck_parents,
+ INFRA_MUX(CLK_INFRA_PWM_SEL, "infra_pwm_sel", infra_pwm_bck_parents,
0x10, 14, 2),
- INFRA_MUX(CK_INFRA_PWM_CK1_SEL, "infra_pwm_ck1_sel",
+ INFRA_MUX(CLK_INFRA_PWM_CK1_SEL, "infra_pwm_ck1_sel",
infra_pwm_bck_parents, 0x10, 16, 2),
- INFRA_MUX(CK_INFRA_PWM_CK2_SEL, "infra_pwm_ck2_sel",
+ INFRA_MUX(CLK_INFRA_PWM_CK2_SEL, "infra_pwm_ck2_sel",
infra_pwm_bck_parents, 0x10, 18, 2),
- INFRA_MUX(CK_INFRA_PWM_CK3_SEL, "infra_pwm_ck3_sel",
+ INFRA_MUX(CLK_INFRA_PWM_CK3_SEL, "infra_pwm_ck3_sel",
infra_pwm_bck_parents, 0x10, 20, 2),
- INFRA_MUX(CK_INFRA_PWM_CK4_SEL, "infra_pwm_ck4_sel",
+ INFRA_MUX(CLK_INFRA_PWM_CK4_SEL, "infra_pwm_ck4_sel",
infra_pwm_bck_parents, 0x10, 22, 2),
- INFRA_MUX(CK_INFRA_PWM_CK5_SEL, "infra_pwm_ck5_sel",
+ INFRA_MUX(CLK_INFRA_PWM_CK5_SEL, "infra_pwm_ck5_sel",
infra_pwm_bck_parents, 0x10, 24, 2),
- INFRA_MUX(CK_INFRA_PWM_CK6_SEL, "infra_pwm_ck6_sel",
+ INFRA_MUX(CLK_INFRA_PWM_CK6_SEL, "infra_pwm_ck6_sel",
infra_pwm_bck_parents, 0x10, 26, 2),
- INFRA_MUX(CK_INFRA_PWM_CK7_SEL, "infra_pwm_ck7_sel",
+ INFRA_MUX(CLK_INFRA_PWM_CK7_SEL, "infra_pwm_ck7_sel",
infra_pwm_bck_parents, 0x10, 28, 2),
- INFRA_MUX(CK_INFRA_PWM_CK8_SEL, "infra_pwm_ck8_sel",
+ INFRA_MUX(CLK_INFRA_PWM_CK8_SEL, "infra_pwm_ck8_sel",
infra_pwm_bck_parents, 0x10, 30, 2),
- INFRA_MUX(CK_INFRA_PCIE_GFMUX_TL_O_P0_SEL,
+ INFRA_MUX(CLK_INFRA_PCIE_GFMUX_TL_O_P0_SEL,
"infra_pcie_gfmux_tl_o_p0_sel",
infra_pcie_gfmux_tl_ck_o_p0_parents, 0x20, 0, 2),
- INFRA_MUX(CK_INFRA_PCIE_GFMUX_TL_O_P1_SEL,
+ INFRA_MUX(CLK_INFRA_PCIE_GFMUX_TL_O_P1_SEL,
"infra_pcie_gfmux_tl_o_p1_sel",
infra_pcie_gfmux_tl_ck_o_p1_parents, 0x20, 2, 2),
- INFRA_MUX(CK_INFRA_PCIE_GFMUX_TL_O_P2_SEL,
+ INFRA_MUX(CLK_INFRA_PCIE_GFMUX_TL_O_P2_SEL,
"infra_pcie_gfmux_tl_o_p2_sel",
infra_pcie_gfmux_tl_ck_o_p2_parents, 0x20, 4, 2),
- INFRA_MUX(CK_INFRA_PCIE_GFMUX_TL_O_P3_SEL,
+ INFRA_MUX(CLK_INFRA_PCIE_GFMUX_TL_O_P3_SEL,
"infra_pcie_gfmux_tl_o_p3_sel",
infra_pcie_gfmux_tl_ck_o_p3_parents, 0x20, 6, 2),
};
@@ -615,218 +559,238 @@
.sta_ofs = 0x68,
};
-#define GATE_INFRA0(_id, _name, _parent, _shift) \
+#define GATE_INFRA0(_id, _name, _parent, _shift, _flags) \
{ \
.id = _id, .parent = _parent, .regs = &infra_0_cg_regs, \
.shift = _shift, \
- .flags = CLK_GATE_SETCLR | CLK_PARENT_INFRASYS, \
+ .flags = _flags, \
}
+#define GATE_INFRA0_INFRA(_id, _name, _parent, _shift) \
+ GATE_INFRA0(_id, _name, _parent, _shift, CLK_GATE_SETCLR | CLK_PARENT_INFRASYS)
+#define GATE_INFRA0_TOP(_id, _name, _parent, _shift) \
+ GATE_INFRA0(_id, _name, _parent, _shift, CLK_GATE_SETCLR | CLK_PARENT_TOPCKGEN)
-#define GATE_INFRA1(_id, _name, _parent, _shift) \
+#define GATE_INFRA1(_id, _name, _parent, _shift, _flags) \
{ \
.id = _id, .parent = _parent, .regs = &infra_1_cg_regs, \
.shift = _shift, \
- .flags = CLK_GATE_SETCLR | CLK_PARENT_INFRASYS, \
+ .flags = _flags, \
}
+#define GATE_INFRA1_INFRA(_id, _name, _parent, _shift) \
+ GATE_INFRA1(_id, _name, _parent, _shift, CLK_GATE_SETCLR | CLK_PARENT_INFRASYS)
+#define GATE_INFRA1_TOP(_id, _name, _parent, _shift) \
+ GATE_INFRA1(_id, _name, _parent, _shift, CLK_GATE_SETCLR | CLK_PARENT_TOPCKGEN)
-#define GATE_INFRA2(_id, _name, _parent, _shift) \
+#define GATE_INFRA2(_id, _name, _parent, _shift, _flags) \
{ \
.id = _id, .parent = _parent, .regs = &infra_2_cg_regs, \
.shift = _shift, \
- .flags = CLK_GATE_SETCLR | CLK_PARENT_INFRASYS, \
+ .flags = _flags, \
}
+#define GATE_INFRA2_INFRA(_id, _name, _parent, _shift) \
+ GATE_INFRA2(_id, _name, _parent, _shift, CLK_GATE_SETCLR | CLK_PARENT_INFRASYS)
+#define GATE_INFRA2_TOP(_id, _name, _parent, _shift) \
+ GATE_INFRA2(_id, _name, _parent, _shift, CLK_GATE_SETCLR | CLK_PARENT_TOPCKGEN)
-#define GATE_INFRA3(_id, _name, _parent, _shift) \
+#define GATE_INFRA3(_id, _name, _parent, _shift, _flags) \
{ \
.id = _id, .parent = _parent, .regs = &infra_3_cg_regs, \
.shift = _shift, \
- .flags = CLK_GATE_SETCLR | CLK_PARENT_INFRASYS, \
+ .flags = _flags, \
}
+#define GATE_INFRA3_INFRA(_id, _name, _parent, _shift) \
+ GATE_INFRA3(_id, _name, _parent, _shift, CLK_GATE_SETCLR | CLK_PARENT_INFRASYS)
+#define GATE_INFRA3_TOP(_id, _name, _parent, _shift) \
+ GATE_INFRA3(_id, _name, _parent, _shift, CLK_GATE_SETCLR | CLK_PARENT_TOPCKGEN)
+#define GATE_INFRA3_XTAL(_id, _name, _parent, _shift) \
+ GATE_INFRA3(_id, _name, _parent, _shift, CLK_GATE_SETCLR | CLK_PARENT_XTAL)
/* INFRA GATE */
static const struct mtk_gate infracfg_mtk_gates[] = {
- GATE_INFRA1(CK_INFRA_66M_GPT_BCK, "infra_hf_66m_gpt_bck",
- CK_INFRA_66M_MCK, 0),
- GATE_INFRA1(CK_INFRA_66M_PWM_HCK, "infra_hf_66m_pwm_hck",
- CK_INFRA_66M_MCK, 1),
- GATE_INFRA1(CK_INFRA_66M_PWM_BCK, "infra_hf_66m_pwm_bck",
- CK_INFRA_PWM_SEL, 2),
- GATE_INFRA1(CK_INFRA_66M_PWM_CK1, "infra_hf_66m_pwm_ck1",
- CK_INFRA_PWM_CK1_SEL, 3),
- GATE_INFRA1(CK_INFRA_66M_PWM_CK2, "infra_hf_66m_pwm_ck2",
- CK_INFRA_PWM_CK2_SEL, 4),
- GATE_INFRA1(CK_INFRA_66M_PWM_CK3, "infra_hf_66m_pwm_ck3",
- CK_INFRA_PWM_CK3_SEL, 5),
- GATE_INFRA1(CK_INFRA_66M_PWM_CK4, "infra_hf_66m_pwm_ck4",
- CK_INFRA_PWM_CK4_SEL, 6),
- GATE_INFRA1(CK_INFRA_66M_PWM_CK5, "infra_hf_66m_pwm_ck5",
- CK_INFRA_PWM_CK5_SEL, 7),
- GATE_INFRA1(CK_INFRA_66M_PWM_CK6, "infra_hf_66m_pwm_ck6",
- CK_INFRA_PWM_CK6_SEL, 8),
- GATE_INFRA1(CK_INFRA_66M_PWM_CK7, "infra_hf_66m_pwm_ck7",
- CK_INFRA_PWM_CK7_SEL, 9),
- GATE_INFRA1(CK_INFRA_66M_PWM_CK8, "infra_hf_66m_pwm_ck8",
- CK_INFRA_PWM_CK8_SEL, 10),
- GATE_INFRA1(CK_INFRA_133M_CQDMA_BCK, "infra_hf_133m_cqdma_bck",
- CK_INFRA_133M_MCK, 12),
- GATE_INFRA1(CK_INFRA_66M_AUD_SLV_BCK, "infra_66m_aud_slv_bck",
- CK_INFRA_66M_PHCK, 13),
- GATE_INFRA1(CK_INFRA_AUD_26M, "infra_f_faud_26m", CK_INFRA_CK_F26M, 14),
- GATE_INFRA1(CK_INFRA_AUD_L, "infra_f_faud_l", CK_INFRA_FAUD_L_O, 15),
- GATE_INFRA1(CK_INFRA_AUD_AUD, "infra_f_aud_aud", CK_INFRA_FAUD_AUD_O,
- 16),
- GATE_INFRA1(CK_INFRA_AUD_EG2, "infra_f_faud_eg2", CK_INFRA_FAUD_EG2_O,
- 18),
- GATE_INFRA1(CK_INFRA_DRAMC_F26M, "infra_dramc_f26m", CK_INFRA_CK_F26M,
- 19),
- GATE_INFRA1(CK_INFRA_133M_DBG_ACKM, "infra_hf_133m_dbg_ackm",
- CK_INFRA_133M_MCK, 20),
- GATE_INFRA1(CK_INFRA_66M_AP_DMA_BCK, "infra_66m_ap_dma_bck",
- CK_INFRA_66M_MCK, 21),
- GATE_INFRA1(CK_INFRA_66M_SEJ_BCK, "infra_hf_66m_sej_bck",
- CK_INFRA_66M_MCK, 29),
- GATE_INFRA1(CK_INFRA_PRE_CK_SEJ_F13M, "infra_pre_ck_sej_f13m",
- CK_INFRA_CK_F26M, 30),
- GATE_INFRA1(CK_INFRA_66M_TRNG, "infra_hf_66m_trng", CK_INFRA_PERI_66M_O,
- 31),
- GATE_INFRA2(CK_INFRA_26M_THERM_SYSTEM, "infra_hf_26m_therm_system",
- CK_INFRA_CK_F26M, 0),
- GATE_INFRA2(CK_INFRA_I2C_BCK, "infra_i2c_bck", CK_INFRA_I2C_O, 1),
- GATE_INFRA2(CK_INFRA_66M_UART0_PCK, "infra_hf_66m_uart0_pck",
- CK_INFRA_66M_MCK, 3),
- GATE_INFRA2(CK_INFRA_66M_UART1_PCK, "infra_hf_66m_uart1_pck",
- CK_INFRA_66M_MCK, 4),
- GATE_INFRA2(CK_INFRA_66M_UART2_PCK, "infra_hf_66m_uart2_pck",
- CK_INFRA_66M_MCK, 5),
- GATE_INFRA2(CK_INFRA_52M_UART0_CK, "infra_f_52m_uart0",
- CK_INFRA_MUX_UART0_SEL, 3),
- GATE_INFRA2(CK_INFRA_52M_UART1_CK, "infra_f_52m_uart1",
- CK_INFRA_MUX_UART1_SEL, 4),
- GATE_INFRA2(CK_INFRA_52M_UART2_CK, "infra_f_52m_uart2",
- CK_INFRA_MUX_UART2_SEL, 5),
- GATE_INFRA2(CK_INFRA_NFI, "infra_f_fnfi", CK_INFRA_NFI_O, 9),
- GATE_INFRA2(CK_INFRA_SPINFI, "infra_f_fspinfi", CK_INFRA_SPINFI_O, 10),
- GATE_INFRA2(CK_INFRA_66M_NFI_HCK, "infra_hf_66m_nfi_hck",
- CK_INFRA_66M_MCK, 11),
- GATE_INFRA2(CK_INFRA_104M_SPI0, "infra_hf_104m_spi0",
- CK_INFRA_MUX_SPI0_SEL, 12),
- GATE_INFRA2(CK_INFRA_104M_SPI1, "infra_hf_104m_spi1",
- CK_INFRA_MUX_SPI1_SEL, 13),
- GATE_INFRA2(CK_INFRA_104M_SPI2_BCK, "infra_hf_104m_spi2_bck",
- CK_INFRA_MUX_SPI2_SEL, 14),
- GATE_INFRA2(CK_INFRA_66M_SPI0_HCK, "infra_hf_66m_spi0_hck",
- CK_INFRA_66M_MCK, 15),
- GATE_INFRA2(CK_INFRA_66M_SPI1_HCK, "infra_hf_66m_spi1_hck",
- CK_INFRA_66M_MCK, 16),
- GATE_INFRA2(CK_INFRA_66M_SPI2_HCK, "infra_hf_66m_spi2_hck",
- CK_INFRA_66M_MCK, 17),
- GATE_INFRA2(CK_INFRA_66M_FLASHIF_AXI, "infra_hf_66m_flashif_axi",
- CK_INFRA_66M_MCK, 18),
- GATE_INFRA2(CK_INFRA_RTC, "infra_f_frtc", CK_INFRA_LB_MUX_FRTC, 19),
- GATE_INFRA2(CK_INFRA_26M_ADC_BCK, "infra_f_26m_adc_bck",
- CK_INFRA_F26M_O1, 20),
- GATE_INFRA2(CK_INFRA_RC_ADC, "infra_f_frc_adc", CK_INFRA_26M_ADC_BCK,
- 21),
- GATE_INFRA2(CK_INFRA_MSDC400, "infra_f_fmsdc400", CK_INFRA_FMSDC400_O,
- 22),
- GATE_INFRA2(CK_INFRA_MSDC2_HCK, "infra_f_fmsdc2_hck",
- CK_INFRA_FMSDC2_HCK_OCC, 23),
- GATE_INFRA2(CK_INFRA_133M_MSDC_0_HCK, "infra_hf_133m_msdc_0_hck",
- CK_INFRA_PERI_133M, 24),
- GATE_INFRA2(CK_INFRA_66M_MSDC_0_HCK, "infra_66m_msdc_0_hck",
- CK_INFRA_66M_PHCK, 25),
- GATE_INFRA2(CK_INFRA_133M_CPUM_BCK, "infra_hf_133m_cpum_bck",
- CK_INFRA_133M_MCK, 26),
- GATE_INFRA2(CK_INFRA_BIST2FPC, "infra_hf_fbist2fpc", CK_INFRA_NFI_O,
- 27),
- GATE_INFRA2(CK_INFRA_I2C_X16W_MCK_CK_P1, "infra_hf_i2c_x16w_mck_ck_p1",
- CK_INFRA_133M_MCK, 29),
- GATE_INFRA2(CK_INFRA_I2C_X16W_PCK_CK_P1, "infra_hf_i2c_x16w_pck_ck_p1",
- CK_INFRA_66M_PHCK, 31),
- GATE_INFRA3(CK_INFRA_133M_USB_HCK, "infra_133m_usb_hck",
- CK_INFRA_133M_PHCK, 0),
- GATE_INFRA3(CK_INFRA_133M_USB_HCK_CK_P1, "infra_133m_usb_hck_ck_p1",
- CK_INFRA_133M_PHCK, 1),
- GATE_INFRA3(CK_INFRA_66M_USB_HCK, "infra_66m_usb_hck",
- CK_INFRA_66M_PHCK, 2),
- GATE_INFRA3(CK_INFRA_66M_USB_HCK_CK_P1, "infra_66m_usb_hck_ck_p1",
- CK_INFRA_66M_PHCK, 3),
- GATE_INFRA3(CK_INFRA_USB_SYS, "infra_usb_sys", CK_INFRA_USB_SYS_O, 4),
- GATE_INFRA3(CK_INFRA_USB_SYS_CK_P1, "infra_usb_sys_ck_p1",
- CK_INFRA_USB_SYS_O_P1, 5),
- GATE_INFRA3(CK_INFRA_USB_REF, "infra_usb_ref", CK_INFRA_USB_O, 6),
- GATE_INFRA3(CK_INFRA_USB_CK_P1, "infra_usb_ck_p1", CK_INFRA_USB_O_P1,
- 7),
- GATE_INFRA3(CK_INFRA_USB_FRMCNT, "infra_usb_frmcnt",
- CK_INFRA_USB_FRMCNT_O, 8),
- GATE_INFRA3(CK_INFRA_USB_FRMCNT_CK_P1, "infra_usb_frmcnt_ck_p1",
- CK_INFRA_USB_FRMCNT_O_P1, 9),
- GATE_INFRA3(CK_INFRA_USB_PIPE, "infra_usb_pipe", CK_INFRA_USB_PIPE_O,
- 10),
- GATE_INFRA3(CK_INFRA_USB_PIPE_CK_P1, "infra_usb_pipe_ck_p1",
- CK_INFRA_USB_PIPE_O_P1, 11),
- GATE_INFRA3(CK_INFRA_USB_UTMI, "infra_usb_utmi", CK_INFRA_USB_UTMI_O,
- 12),
- GATE_INFRA3(CK_INFRA_USB_UTMI_CK_P1, "infra_usb_utmi_ck_p1",
- CK_INFRA_USB_UTMI_O_P1, 13),
- GATE_INFRA3(CK_INFRA_USB_XHCI, "infra_usb_xhci", CK_INFRA_USB_XHCI_O,
- 14),
- GATE_INFRA3(CK_INFRA_USB_XHCI_CK_P1, "infra_usb_xhci_ck_p1",
- CK_INFRA_USB_XHCI_O_P1, 15),
- GATE_INFRA3(CK_INFRA_PCIE_GFMUX_TL_P0, "infra_pcie_gfmux_tl_ck_p0",
- CK_INFRA_PCIE_GFMUX_TL_O_P0_SEL, 20),
- GATE_INFRA3(CK_INFRA_PCIE_GFMUX_TL_P1, "infra_pcie_gfmux_tl_ck_p1",
- CK_INFRA_PCIE_GFMUX_TL_O_P1_SEL, 21),
- GATE_INFRA3(CK_INFRA_PCIE_GFMUX_TL_P2, "infra_pcie_gfmux_tl_ck_p2",
- CK_INFRA_PCIE_GFMUX_TL_O_P2_SEL, 22),
- GATE_INFRA3(CK_INFRA_PCIE_GFMUX_TL_P3, "infra_pcie_gfmux_tl_ck_p3",
- CK_INFRA_PCIE_GFMUX_TL_O_P3_SEL, 23),
- GATE_INFRA3(CK_INFRA_PCIE_PIPE_P0, "infra_pcie_pipe_ck_p0",
- CK_INFRA_PCIE_PIPE_OCC_P0, 24),
- GATE_INFRA3(CK_INFRA_PCIE_PIPE_P1, "infra_pcie_pipe_ck_p1",
- CK_INFRA_PCIE_PIPE_OCC_P1, 25),
- GATE_INFRA3(CK_INFRA_PCIE_PIPE_P2, "infra_pcie_pipe_ck_p2",
- CK_INFRA_PCIE_PIPE_OCC_P2, 26),
- GATE_INFRA3(CK_INFRA_PCIE_PIPE_P3, "infra_pcie_pipe_ck_p3",
- CK_INFRA_PCIE_PIPE_OCC_P3, 27),
- GATE_INFRA3(CK_INFRA_133M_PCIE_CK_P0, "infra_133m_pcie_ck_p0",
- CK_INFRA_133M_PHCK, 28),
- GATE_INFRA3(CK_INFRA_133M_PCIE_CK_P1, "infra_133m_pcie_ck_p1",
- CK_INFRA_133M_PHCK, 29),
- GATE_INFRA3(CK_INFRA_133M_PCIE_CK_P2, "infra_133m_pcie_ck_p2",
- CK_INFRA_133M_PHCK, 30),
- GATE_INFRA3(CK_INFRA_133M_PCIE_CK_P3, "infra_133m_pcie_ck_p3",
- CK_INFRA_133M_PHCK, 31),
- GATE_INFRA0(CK_INFRA_PCIE_PERI_26M_CK_P0,
- "infra_pcie_peri_ck_26m_ck_p0", CK_INFRA_F26M_O0, 7),
- GATE_INFRA0(CK_INFRA_PCIE_PERI_26M_CK_P1,
- "infra_pcie_peri_ck_26m_ck_p1", CK_INFRA_F26M_O0, 8),
- GATE_INFRA0(CK_INFRA_PCIE_PERI_26M_CK_P2,
- "infra_pcie_peri_ck_26m_ck_p2", CK_INFRA_F26M_O0, 9),
- GATE_INFRA0(CK_INFRA_PCIE_PERI_26M_CK_P3,
- "infra_pcie_peri_ck_26m_ck_p3", CK_INFRA_F26M_O0, 10),
+ GATE_INFRA0_TOP(CLK_INFRA_PCIE_PERI_26M_CK_P0,
+ "infra_pcie_peri_ck_26m_ck_p0", CLK_TOP_INFRA_F26M_SEL, 7),
+ GATE_INFRA0_TOP(CLK_INFRA_PCIE_PERI_26M_CK_P1,
+ "infra_pcie_peri_ck_26m_ck_p1", CLK_TOP_INFRA_F26M_SEL, 8),
+ GATE_INFRA0_INFRA(CLK_INFRA_PCIE_PERI_26M_CK_P2,
+ "infra_pcie_peri_ck_26m_ck_p2", CLK_INFRA_PCIE_PERI_26M_CK_P3, 9),
+ GATE_INFRA0_TOP(CLK_INFRA_PCIE_PERI_26M_CK_P3,
+ "infra_pcie_peri_ck_26m_ck_p3", CLK_TOP_INFRA_F26M_SEL, 10),
+ GATE_INFRA1_TOP(CLK_INFRA_66M_GPT_BCK, "infra_hf_66m_gpt_bck",
+ CLK_TOP_SYSAXI_SEL, 0),
+ GATE_INFRA1_TOP(CLK_INFRA_66M_PWM_HCK, "infra_hf_66m_pwm_hck",
+ CLK_TOP_SYSAXI_SEL, 1),
+ GATE_INFRA1_INFRA(CLK_INFRA_66M_PWM_BCK, "infra_hf_66m_pwm_bck",
+ CLK_INFRA_PWM_SEL, 2),
+ GATE_INFRA1_INFRA(CLK_INFRA_66M_PWM_CK1, "infra_hf_66m_pwm_ck1",
+ CLK_INFRA_PWM_CK1_SEL, 3),
+ GATE_INFRA1_INFRA(CLK_INFRA_66M_PWM_CK2, "infra_hf_66m_pwm_ck2",
+ CLK_INFRA_PWM_CK2_SEL, 4),
+ GATE_INFRA1_INFRA(CLK_INFRA_66M_PWM_CK3, "infra_hf_66m_pwm_ck3",
+ CLK_INFRA_PWM_CK3_SEL, 5),
+ GATE_INFRA1_INFRA(CLK_INFRA_66M_PWM_CK4, "infra_hf_66m_pwm_ck4",
+ CLK_INFRA_PWM_CK4_SEL, 6),
+ GATE_INFRA1_INFRA(CLK_INFRA_66M_PWM_CK5, "infra_hf_66m_pwm_ck5",
+ CLK_INFRA_PWM_CK5_SEL, 7),
+ GATE_INFRA1_INFRA(CLK_INFRA_66M_PWM_CK6, "infra_hf_66m_pwm_ck6",
+ CLK_INFRA_PWM_CK6_SEL, 8),
+ GATE_INFRA1_INFRA(CLK_INFRA_66M_PWM_CK7, "infra_hf_66m_pwm_ck7",
+ CLK_INFRA_PWM_CK7_SEL, 9),
+ GATE_INFRA1_INFRA(CLK_INFRA_66M_PWM_CK8, "infra_hf_66m_pwm_ck8",
+ CLK_INFRA_PWM_CK8_SEL, 10),
+ GATE_INFRA1_TOP(CLK_INFRA_133M_CQDMA_BCK, "infra_hf_133m_cqdma_bck",
+ CLK_TOP_SYSAXI_SEL, 12),
+ GATE_INFRA1_TOP(CLK_INFRA_66M_AUD_SLV_BCK, "infra_66m_aud_slv_bck",
+ CLK_TOP_SYSAXI_SEL, 13),
+ GATE_INFRA1_TOP(CLK_INFRA_AUD_26M, "infra_f_faud_26m", CLK_TOP_INFRA_F26M_SEL, 14),
+ GATE_INFRA1_TOP(CLK_INFRA_AUD_L, "infra_f_faud_l", CLK_TOP_AUD_L_SEL, 15),
+ GATE_INFRA1_TOP(CLK_INFRA_AUD_AUD, "infra_f_aud_aud", CLK_TOP_A1SYS_SEL,
+ 16),
+ GATE_INFRA1_TOP(CLK_INFRA_AUD_EG2, "infra_f_faud_eg2", CLK_TOP_A_TUNER_SEL,
+ 18),
+ GATE_INFRA1_TOP(CLK_INFRA_DRAMC_F26M, "infra_dramc_f26m", CLK_TOP_INFRA_F26M_SEL,
+ 19),
+ GATE_INFRA1_TOP(CLK_INFRA_133M_DBG_ACKM, "infra_hf_133m_dbg_ackm",
+ CLK_TOP_SYSAXI_SEL, 20),
+ GATE_INFRA1_TOP(CLK_INFRA_66M_AP_DMA_BCK, "infra_66m_ap_dma_bck",
+ CLK_TOP_SYSAXI_SEL, 21),
+ GATE_INFRA1_TOP(CLK_INFRA_66M_SEJ_BCK, "infra_hf_66m_sej_bck",
+ CLK_TOP_SYSAXI_SEL, 29),
+ GATE_INFRA1_TOP(CLK_INFRA_PRE_CK_SEJ_F13M, "infra_pre_ck_sej_f13m",
+ CLK_TOP_INFRA_F26M_SEL, 30),
+ /* GATE_INFRA1_TOP(CLK_INFRA_66M_TRNG, "infra_hf_66m_trng", CLK_TOP_SYSAXI_SEL,
+ 31), */
+ GATE_INFRA2_TOP(CLK_INFRA_26M_THERM_SYSTEM, "infra_hf_26m_therm_system",
+ CLK_TOP_INFRA_F26M_SEL, 0),
+ GATE_INFRA2_TOP(CLK_INFRA_I2C_BCK, "infra_i2c_bck", CLK_TOP_I2C_SEL, 1),
+ /* GATE_INFRA2_TOP(CLK_INFRA_66M_UART0_PCK, "infra_hf_66m_uart0_pck",
+ CLK_TOP_SYSAXI_SEL, 3), */
+ /* GATE_INFRA2_TOP(CLK_INFRA_66M_UART1_PCK, "infra_hf_66m_uart1_pck",
+ CLK_TOP_SYSAXI_SEL, 4), */
+ /* GATE_INFRA2_TOP(CLK_INFRA_66M_UART2_PCK, "infra_hf_66m_uart2_pck",
+ CLK_TOP_SYSAXI_SEL, 5), */
+ GATE_INFRA2_INFRA(CLK_INFRA_52M_UART0_CK, "infra_f_52m_uart0",
+ CLK_INFRA_MUX_UART0_SEL, 3),
+ GATE_INFRA2_INFRA(CLK_INFRA_52M_UART1_CK, "infra_f_52m_uart1",
+ CLK_INFRA_MUX_UART1_SEL, 4),
+ GATE_INFRA2_INFRA(CLK_INFRA_52M_UART2_CK, "infra_f_52m_uart2",
+ CLK_INFRA_MUX_UART2_SEL, 5),
+ GATE_INFRA2_TOP(CLK_INFRA_NFI, "infra_f_fnfi", CLK_TOP_NFI1X_SEL, 9),
+ GATE_INFRA2_TOP(CLK_INFRA_SPINFI, "infra_f_fspinfi", CLK_TOP_SPINFI_SEL, 10),
+ GATE_INFRA2_TOP(CLK_INFRA_66M_NFI_HCK, "infra_hf_66m_nfi_hck",
+ CLK_TOP_SYSAXI_SEL, 11),
+ GATE_INFRA2_INFRA(CLK_INFRA_104M_SPI0, "infra_hf_104m_spi0",
+ CLK_INFRA_MUX_SPI0_SEL, 12),
+ GATE_INFRA2_INFRA(CLK_INFRA_104M_SPI1, "infra_hf_104m_spi1",
+ CLK_INFRA_MUX_SPI1_SEL, 13),
+ GATE_INFRA2_INFRA(CLK_INFRA_104M_SPI2_BCK, "infra_hf_104m_spi2_bck",
+ CLK_INFRA_MUX_SPI2_SEL, 14),
+ GATE_INFRA2_TOP(CLK_INFRA_66M_SPI0_HCK, "infra_hf_66m_spi0_hck",
+ CLK_TOP_SYSAXI_SEL, 15),
+ GATE_INFRA2_TOP(CLK_INFRA_66M_SPI1_HCK, "infra_hf_66m_spi1_hck",
+ CLK_TOP_SYSAXI_SEL, 16),
+ GATE_INFRA2_TOP(CLK_INFRA_66M_SPI2_HCK, "infra_hf_66m_spi2_hck",
+ CLK_TOP_SYSAXI_SEL, 17),
+ GATE_INFRA2_TOP(CLK_INFRA_66M_FLASHIF_AXI, "infra_hf_66m_flashif_axi",
+ CLK_TOP_SYSAXI_SEL, 18),
+ GATE_INFRA2_TOP(CLK_INFRA_RTC, "infra_f_frtc", CLK_TOP_RTC_32K, 19),
+ GATE_INFRA2_TOP(CLK_INFRA_26M_ADC_BCK, "infra_f_26m_adc_bck",
+ CLK_TOP_INFRA_F26M_SEL, 20),
+ GATE_INFRA2_INFRA(CLK_INFRA_RC_ADC, "infra_f_frc_adc", CLK_INFRA_26M_ADC_BCK,
+ 21),
+ GATE_INFRA2_TOP(CLK_INFRA_MSDC400, "infra_f_fmsdc400", CLK_TOP_EMMC_400M_SEL,
+ 22),
+ GATE_INFRA2_TOP(CLK_INFRA_MSDC2_HCK, "infra_f_fmsdc2_hck",
+ CLK_TOP_EMMC_250M_SEL, 23),
+ GATE_INFRA2_TOP(CLK_INFRA_133M_MSDC_0_HCK, "infra_hf_133m_msdc_0_hck",
+ CLK_TOP_SYSAXI_SEL, 24),
+ GATE_INFRA2_TOP(CLK_INFRA_66M_MSDC_0_HCK, "infra_66m_msdc_0_hck",
+ CLK_TOP_SYSAXI_SEL, 25),
+ GATE_INFRA2_TOP(CLK_INFRA_133M_CPUM_BCK, "infra_hf_133m_cpum_bck",
+ CLK_TOP_SYSAXI_SEL, 26),
+ GATE_INFRA2_TOP(CLK_INFRA_BIST2FPC, "infra_hf_fbist2fpc", CLK_TOP_NFI1X_SEL,
+ 27),
+ GATE_INFRA2_TOP(CLK_INFRA_I2C_X16W_MCK_CK_P1, "infra_hf_i2c_x16w_mck_ck_p1",
+ CLK_TOP_SYSAXI_SEL, 29),
+ GATE_INFRA2_TOP(CLK_INFRA_I2C_X16W_PCK_CK_P1, "infra_hf_i2c_x16w_pck_ck_p1",
+ CLK_TOP_SYSAXI_SEL, 31),
+ GATE_INFRA3_TOP(CLK_INFRA_133M_USB_HCK, "infra_133m_usb_hck",
+ CLK_TOP_SYSAXI_SEL, 0),
+ GATE_INFRA3_TOP(CLK_INFRA_133M_USB_HCK_CK_P1, "infra_133m_usb_hck_ck_p1",
+ CLK_TOP_SYSAXI_SEL, 1),
+ GATE_INFRA3_TOP(CLK_INFRA_66M_USB_HCK, "infra_66m_usb_hck",
+ CLK_TOP_SYSAXI_SEL, 2),
+ GATE_INFRA3_TOP(CLK_INFRA_66M_USB_HCK_CK_P1, "infra_66m_usb_hck_ck_p1",
+ CLK_TOP_SYSAXI_SEL, 3),
+ GATE_INFRA3_TOP(CLK_INFRA_USB_SYS, "infra_usb_sys", CLK_TOP_USB_SYS_SEL, 4),
+ GATE_INFRA3_TOP(CLK_INFRA_USB_SYS_CK_P1, "infra_usb_sys_ck_p1",
+ CLK_TOP_USB_SYS_P1_SEL, 5),
+ GATE_INFRA3_XTAL(CLK_INFRA_USB_REF, "infra_usb_ref", CLK_XTAL, 6),
+ GATE_INFRA3_XTAL(CLK_INFRA_USB_CK_P1, "infra_usb_ck_p1", CLK_XTAL,
+ 7),
+ GATE_INFRA3_TOP(CLK_INFRA_USB_FRMCNT, "infra_usb_frmcnt",
+ CLK_TOP_USB_FRMCNT_SEL, 8),
+ GATE_INFRA3_TOP(CLK_INFRA_USB_FRMCNT_CK_P1, "infra_usb_frmcnt_ck_p1",
+ CLK_TOP_USB_FRMCNT_P1_SEL, 9),
+ GATE_INFRA3_XTAL(CLK_INFRA_USB_PIPE, "infra_usb_pipe", CLK_XTAL,
+ 10),
+ GATE_INFRA3_XTAL(CLK_INFRA_USB_PIPE_CK_P1, "infra_usb_pipe_ck_p1",
+ CLK_XTAL, 11),
+ GATE_INFRA3_XTAL(CLK_INFRA_USB_UTMI, "infra_usb_utmi", CLK_XTAL,
+ 12),
+ GATE_INFRA3_XTAL(CLK_INFRA_USB_UTMI_CK_P1, "infra_usb_utmi_ck_p1",
+ CLK_XTAL, 13),
+ GATE_INFRA3_TOP(CLK_INFRA_USB_XHCI, "infra_usb_xhci", CLK_TOP_USB_XHCI_SEL,
+ 14),
+ GATE_INFRA3_TOP(CLK_INFRA_USB_XHCI_CK_P1, "infra_usb_xhci_ck_p1",
+ CLK_TOP_USB_XHCI_P1_SEL, 15),
+ GATE_INFRA3_INFRA(CLK_INFRA_PCIE_GFMUX_TL_P0, "infra_pcie_gfmux_tl_ck_p0",
+ CLK_INFRA_PCIE_GFMUX_TL_O_P0_SEL, 20),
+ GATE_INFRA3_INFRA(CLK_INFRA_PCIE_GFMUX_TL_P1, "infra_pcie_gfmux_tl_ck_p1",
+ CLK_INFRA_PCIE_GFMUX_TL_O_P1_SEL, 21),
+ GATE_INFRA3_INFRA(CLK_INFRA_PCIE_GFMUX_TL_P2, "infra_pcie_gfmux_tl_ck_p2",
+ CLK_INFRA_PCIE_GFMUX_TL_O_P2_SEL, 22),
+ GATE_INFRA3_INFRA(CLK_INFRA_PCIE_GFMUX_TL_P3, "infra_pcie_gfmux_tl_ck_p3",
+ CLK_INFRA_PCIE_GFMUX_TL_O_P3_SEL, 23),
+ GATE_INFRA3_XTAL(CLK_INFRA_PCIE_PIPE_P0, "infra_pcie_pipe_ck_p0",
+ CLK_XTAL, 24),
+ GATE_INFRA3_XTAL(CLK_INFRA_PCIE_PIPE_P1, "infra_pcie_pipe_ck_p1",
+ CLK_XTAL, 25),
+ GATE_INFRA3_XTAL(CLK_INFRA_PCIE_PIPE_P2, "infra_pcie_pipe_ck_p2",
+ CLK_XTAL, 26),
+ GATE_INFRA3_XTAL(CLK_INFRA_PCIE_PIPE_P3, "infra_pcie_pipe_ck_p3",
+ CLK_XTAL, 27),
+ GATE_INFRA3_TOP(CLK_INFRA_133M_PCIE_CK_P0, "infra_133m_pcie_ck_p0",
+ CLK_TOP_SYSAXI_SEL, 28),
+ GATE_INFRA3_TOP(CLK_INFRA_133M_PCIE_CK_P1, "infra_133m_pcie_ck_p1",
+ CLK_TOP_SYSAXI_SEL, 29),
+ GATE_INFRA3_TOP(CLK_INFRA_133M_PCIE_CK_P2, "infra_133m_pcie_ck_p2",
+ CLK_TOP_SYSAXI_SEL, 30),
+ GATE_INFRA3_TOP(CLK_INFRA_133M_PCIE_CK_P3, "infra_133m_pcie_ck_p3",
+ CLK_TOP_SYSAXI_SEL, 31),
};
static const struct mtk_clk_tree mt7988_fixed_pll_clk_tree = {
.fdivs_offs = ARRAY_SIZE(apmixedsys_mtk_plls),
.fclks = apmixedsys_mtk_plls,
+ .flags = CLK_APMIXED,
.xtal_rate = 40 * MHZ,
};
static const struct mtk_clk_tree mt7988_topckgen_clk_tree = {
- .fdivs_offs = CK_TOP_CB_CKSQ_40M,
- .muxes_offs = CK_TOP_NETSYS_SEL,
+ .fdivs_offs = CLK_TOP_XTAL_D2,
+ .muxes_offs = CLK_TOP_NETSYS_SEL,
+ .fclks = topckgen_mtk_fixed_clks,
.fdivs = topckgen_mtk_fixed_factors,
.muxes = topckgen_mtk_muxes,
- .flags = CLK_BYPASS_XTAL,
+ .flags = CLK_BYPASS_XTAL | CLK_TOPCKGEN,
.xtal_rate = 40 * MHZ,
};
static const struct mtk_clk_tree mt7988_infracfg_clk_tree = {
- .fdivs_offs = CK_INFRA_CK_F26M,
- .muxes_offs = CK_INFRA_MUX_UART0_SEL,
- .fdivs = infracfg_mtk_fixed_factor,
+ .muxes_offs = CLK_INFRA_MUX_UART0_SEL,
+ .gates_offs = CLK_INFRA_PCIE_PERI_26M_CK_P0,
.muxes = infracfg_mtk_mux,
+ .gates = infracfg_mtk_gates,
.flags = CLK_BYPASS_XTAL,
.xtal_rate = 40 * MHZ,
};
@@ -884,22 +848,11 @@
{}
};
-static const struct udevice_id mt7988_infracfg_ao_cgs_compat[] = {
- { .compatible = "mediatek,mt7988-infracfg_ao_cgs" },
- {}
-};
-
static int mt7988_infracfg_probe(struct udevice *dev)
{
- return mtk_common_clk_init(dev, &mt7988_infracfg_clk_tree);
+ return mtk_common_clk_infrasys_init(dev, &mt7988_infracfg_clk_tree);
}
-static int mt7988_infracfg_ao_cgs_probe(struct udevice *dev)
-{
- return mtk_common_clk_gate_init(dev, &mt7988_infracfg_clk_tree,
- infracfg_mtk_gates);
-}
-
U_BOOT_DRIVER(mtk_clk_infracfg) = {
.name = "mt7988-clock-infracfg",
.id = UCLASS_CLK,
@@ -910,16 +863,6 @@
.flags = DM_FLAG_PRE_RELOC,
};
-U_BOOT_DRIVER(mtk_clk_infracfg_ao_cgs) = {
- .name = "mt7988-clock-infracfg_ao_cgs",
- .id = UCLASS_CLK,
- .of_match = mt7988_infracfg_ao_cgs_compat,
- .probe = mt7988_infracfg_ao_cgs_probe,
- .priv_auto = sizeof(struct mtk_cg_priv),
- .ops = &mtk_clk_gate_ops,
- .flags = DM_FLAG_PRE_RELOC,
-};
-
/* ETHDMA */
static const struct mtk_gate_regs ethdma_cg_regs = {
@@ -936,7 +879,7 @@
}
static const struct mtk_gate ethdma_mtk_gate[] = {
- GATE_ETHDMA(CK_ETHDMA_FE_EN, "ethdma_fe_en", CK_TOP_NETSYS_2X, 6),
+ GATE_ETHDMA(CLK_ETHDMA_FE_EN, "ethdma_fe_en", CLK_TOP_NETSYS_2X_SEL, 6),
};
static int mt7988_ethdma_probe(struct udevice *dev)
@@ -991,10 +934,10 @@
}
static const struct mtk_gate sgmiisys_0_mtk_gate[] = {
- /* connect to fake clock, so use CK_TOP_CB_CKSQ_40M as the clock parent */
- GATE_SGMII0(CK_SGM0_TX_EN, "sgm0_tx_en", CK_TOP_CB_CKSQ_40M, 2),
- /* connect to fake clock, so use CK_TOP_CB_CKSQ_40M as the clock parent */
- GATE_SGMII0(CK_SGM0_RX_EN, "sgm0_rx_en", CK_TOP_CB_CKSQ_40M, 3),
+ /* connect to fake clock, so use CLK_TOP_XTAL as the clock parent */
+ GATE_SGMII0(CLK_SGM0_TX_EN, "sgm0_tx_en", CLK_TOP_XTAL, 2),
+ /* connect to fake clock, so use CLK_TOP_XTAL as the clock parent */
+ GATE_SGMII0(CLK_SGM0_RX_EN, "sgm0_rx_en", CLK_TOP_XTAL, 3),
};
static int mt7988_sgmiisys_0_probe(struct udevice *dev)
@@ -1035,10 +978,10 @@
}
static const struct mtk_gate sgmiisys_1_mtk_gate[] = {
- /* connect to fake clock, so use CK_TOP_CB_CKSQ_40M as the clock parent */
- GATE_SGMII1(CK_SGM1_TX_EN, "sgm1_tx_en", CK_TOP_CB_CKSQ_40M, 2),
- /* connect to fake clock, so use CK_TOP_CB_CKSQ_40M as the clock parent */
- GATE_SGMII1(CK_SGM1_RX_EN, "sgm1_rx_en", CK_TOP_CB_CKSQ_40M, 3),
+ /* connect to fake clock, so use CLK_TOP_XTAL as the clock parent */
+ GATE_SGMII1(CLK_SGM1_TX_EN, "sgm1_tx_en", CLK_TOP_XTAL, 2),
+ /* connect to fake clock, so use CLK_TOP_XTAL as the clock parent */
+ GATE_SGMII1(CLK_SGM1_RX_EN, "sgm1_rx_en", CLK_TOP_XTAL, 3),
};
static int mt7988_sgmiisys_1_probe(struct udevice *dev)
@@ -1079,12 +1022,12 @@
}
static const struct mtk_gate ethwarp_mtk_gate[] = {
- GATE_ETHWARP(CK_ETHWARP_WOCPU2_EN, "ethwarp_wocpu2_en",
- CK_TOP_NETSYS_WED_MCU, 13),
- GATE_ETHWARP(CK_ETHWARP_WOCPU1_EN, "ethwarp_wocpu1_en",
- CK_TOP_NETSYS_WED_MCU, 14),
- GATE_ETHWARP(CK_ETHWARP_WOCPU0_EN, "ethwarp_wocpu0_en",
- CK_TOP_NETSYS_WED_MCU, 15),
+ GATE_ETHWARP(CLK_ETHWARP_WOCPU2_EN, "ethwarp_wocpu2_en",
+ CLK_TOP_NETSYS_MCU_SEL, 13),
+ GATE_ETHWARP(CLK_ETHWARP_WOCPU1_EN, "ethwarp_wocpu1_en",
+ CLK_TOP_NETSYS_MCU_SEL, 14),
+ GATE_ETHWARP(CLK_ETHWARP_WOCPU0_EN, "ethwarp_wocpu0_en",
+ CLK_TOP_NETSYS_MCU_SEL, 15),
};
static int mt7988_ethwarp_probe(struct udevice *dev)
diff --git a/drivers/clk/mpc83xx_clk.c b/drivers/clk/mpc83xx_clk.c
index a29ad0d..a43fff2 100644
--- a/drivers/clk/mpc83xx_clk.c
+++ b/drivers/clk/mpc83xx_clk.c
@@ -358,7 +358,7 @@
gd->mem_clk = priv->speed[MPC83XX_CLK_MEM];
if (mpc83xx_has_pci(type))
- gd->pci_clk = priv->speed[MPC83XX_CLK_PCI];
+ gd->arch.pci_clk = priv->speed[MPC83XX_CLK_PCI];
gd->cpu_clk = priv->speed[MPC83XX_CLK_CORE];
gd->bus_clk = priv->speed[MPC83XX_CLK_CSB];
diff --git a/drivers/clk/rockchip/clk_rk3399.c b/drivers/clk/rockchip/clk_rk3399.c
index 24cefeb..8992404 100644
--- a/drivers/clk/rockchip/clk_rk3399.c
+++ b/drivers/clk/rockchip/clk_rk3399.c
@@ -8,6 +8,7 @@
#include <dm.h>
#include <dt-structs.h>
#include <errno.h>
+#include <handoff.h>
#include <log.h>
#include <malloc.h>
#include <mapmem.h>
@@ -1467,7 +1468,7 @@
init_clocks = true;
#elif CONFIG_IS_ENABLED(HANDOFF)
if (!(gd->flags & GD_FLG_RELOC)) {
- if (!(gd->spl_handoff))
+ if (!handoff_get())
init_clocks = true;
}
#endif
diff --git a/drivers/ddr/fsl/main.c b/drivers/ddr/fsl/main.c
index 31091bb..888dfb7 100644
--- a/drivers/ddr/fsl/main.c
+++ b/drivers/ddr/fsl/main.c
@@ -111,7 +111,7 @@
#if CONFIG_IS_ENABLED(DM_I2C)
ret = dm_i2c_read(dev, 0, buf, len);
#else
- ret = i2c_read(dev->chip, addr, alen, buf, len);
+ ret = 0;
#endif
return ret;
@@ -162,7 +162,6 @@
};
dev = &ldev;
- i2c_set_bus_num(CONFIG_SYS_SPD_BUS_NUM);
#endif
#ifdef CONFIG_SYS_FSL_DDR4
diff --git a/drivers/i2c/i2c_core.c b/drivers/i2c/i2c_core.c
index 7c43a55..cccd450 100644
--- a/drivers/i2c/i2c_core.c
+++ b/drivers/i2c/i2c_core.c
@@ -33,137 +33,8 @@
return i2c_adap_p;
}
-#if !defined(CFG_SYS_I2C_DIRECT_BUS)
-struct i2c_bus_hose i2c_bus[CFG_SYS_NUM_I2C_BUSES] =
- CFG_SYS_I2C_BUSES;
-#endif
-
DECLARE_GLOBAL_DATA_PTR;
-#ifndef CFG_SYS_I2C_DIRECT_BUS
-/*
- * i2c_mux_set()
- * -------------
- *
- * This turns on the given channel on I2C multiplexer chip connected to
- * a given I2C adapter directly or via other multiplexers. In the latter
- * case the entire multiplexer chain must be initialized first starting
- * with the one connected directly to the adapter. When disabling a chain
- * muxes must be programmed in reverse order, starting with the one
- * farthest from the adapter.
- *
- * mux_id is the multiplexer chip type from defined in i2c.h. So far only
- * NXP (Philips) PCA954x multiplexers are supported. Switches are NOT
- * supported (anybody uses them?)
- */
-
-static int i2c_mux_set(struct i2c_adapter *adap, int mux_id, int chip,
- int channel)
-{
- uint8_t buf;
- int ret;
-
- /* channel < 0 - turn off the mux */
- if (channel < 0) {
- buf = 0;
- ret = adap->write(adap, chip, 0, 0, &buf, 1);
- if (ret)
- printf("%s: Could not turn off the mux.\n", __func__);
- return ret;
- }
-
- switch (mux_id) {
- case I2C_MUX_PCA9540_ID:
- case I2C_MUX_PCA9542_ID:
- if (channel > 1)
- return -1;
- buf = (uint8_t)((channel & 0x01) | (1 << 2));
- break;
- case I2C_MUX_PCA9544_ID:
- if (channel > 3)
- return -1;
- buf = (uint8_t)((channel & 0x03) | (1 << 2));
- break;
- case I2C_MUX_PCA9547_ID:
- if (channel > 7)
- return -1;
- buf = (uint8_t)((channel & 0x07) | (1 << 3));
- break;
- case I2C_MUX_PCA9548_ID:
- if (channel > 7)
- return -1;
- buf = (uint8_t)(0x01 << channel);
- break;
- default:
- printf("%s: wrong mux id: %d\n", __func__, mux_id);
- return -1;
- }
-
- ret = adap->write(adap, chip, 0, 0, &buf, 1);
- if (ret)
- printf("%s: could not set mux: id: %d chip: %x channel: %d\n",
- __func__, mux_id, chip, channel);
- return ret;
-}
-
-static int i2c_mux_set_all(void)
-{
- struct i2c_bus_hose *i2c_bus_tmp = &i2c_bus[I2C_BUS];
- int i;
-
- /* Connect requested bus if behind muxes */
- if (i2c_bus_tmp->next_hop[0].chip != 0) {
- /* Set all muxes along the path to that bus */
- for (i = 0; i < CFG_SYS_I2C_MAX_HOPS; i++) {
- int ret;
-
- if (i2c_bus_tmp->next_hop[i].chip == 0)
- break;
-
- ret = i2c_mux_set(I2C_ADAP,
- i2c_bus_tmp->next_hop[i].mux.id,
- i2c_bus_tmp->next_hop[i].chip,
- i2c_bus_tmp->next_hop[i].channel);
- if (ret != 0)
- return ret;
- }
- }
- return 0;
-}
-
-static int i2c_mux_disconnect_all(void)
-{
- struct i2c_bus_hose *i2c_bus_tmp = &i2c_bus[I2C_BUS];
- int i;
- uint8_t buf = 0;
-
- if (I2C_ADAP->init_done == 0)
- return 0;
-
- /* Disconnect current bus (turn off muxes if any) */
- if ((i2c_bus_tmp->next_hop[0].chip != 0) &&
- (I2C_ADAP->init_done != 0)) {
- i = CFG_SYS_I2C_MAX_HOPS;
- do {
- uint8_t chip;
- int ret;
-
- chip = i2c_bus_tmp->next_hop[--i].chip;
- if (chip == 0)
- continue;
-
- ret = I2C_ADAP->write(I2C_ADAP, chip, 0, 0, &buf, 1);
- if (ret != 0) {
- printf("i2c: mux disconnect error\n");
- return ret;
- }
- } while (i > 0);
- }
-
- return 0;
-}
-#endif
-
/*
* i2c_init_bus():
* ---------------
@@ -237,11 +108,6 @@
if ((bus == I2C_BUS) && (I2C_ADAP->init_done > 0))
return 0;
-#ifndef CFG_SYS_I2C_DIRECT_BUS
- if (bus >= CFG_SYS_NUM_I2C_BUSES)
- return -1;
-#endif
-
max = ll_entry_count(struct i2c_adapter, i2c);
if (I2C_ADAPTER(bus) >= max) {
printf("Error, wrong i2c adapter %d max %d possible\n",
@@ -249,17 +115,10 @@
return -2;
}
-#ifndef CFG_SYS_I2C_DIRECT_BUS
- i2c_mux_disconnect_all();
-#endif
-
gd->cur_i2c_bus = bus;
if (I2C_ADAP->init_done == 0)
i2c_init_bus(bus, I2C_ADAP->speed, I2C_ADAP->slaveaddr);
-#ifndef CFG_SYS_I2C_DIRECT_BUS
- i2c_mux_set_all();
-#endif
return 0;
}
diff --git a/drivers/i2c/mxc_i2c.c b/drivers/i2c/mxc_i2c.c
index 84c0050..2f3cb59 100644
--- a/drivers/i2c/mxc_i2c.c
+++ b/drivers/i2c/mxc_i2c.c
@@ -620,6 +620,7 @@
__attribute__((weak, alias("__enable_i2c_clk")));
#if !CONFIG_IS_ENABLED(DM_I2C)
+
/*
* Read data from I2C device
*
diff --git a/drivers/i2c/soft_i2c.c b/drivers/i2c/soft_i2c.c
index 89ddf82..79f7a32 100644
--- a/drivers/i2c/soft_i2c.c
+++ b/drivers/i2c/soft_i2c.c
@@ -107,16 +107,13 @@
/*-----------------------------------------------------------------------
* Local functions
*/
-#if !defined(CONFIG_SYS_I2C_INIT_BOARD)
static void send_reset (void);
-#endif
static void send_start (void);
static void send_stop (void);
static void send_ack (int);
static int write_byte (uchar byte);
static uchar read_byte (int);
-#if !defined(CONFIG_SYS_I2C_INIT_BOARD)
/*-----------------------------------------------------------------------
* Send a reset sequence consisting of 9 clocks with the data signal high
* to clock any confused device back into an idle state. Also send a
@@ -144,7 +141,6 @@
send_stop();
I2C_TRISTATE;
}
-#endif
/*-----------------------------------------------------------------------
* START: High -> Low on SDA while SCL is High
@@ -277,12 +273,6 @@
*/
static void soft_i2c_init(struct i2c_adapter *adap, int speed, int slaveaddr)
{
-#if defined(CONFIG_SYS_I2C_INIT_BOARD)
- /* call board specific i2c bus reset routine before accessing the */
- /* environment, which might be in a chip on that bus. For details */
- /* about this problem see doc/I2C_Edge_Conditions. */
- i2c_init_board();
-#else
/*
* WARNING: Do NOT save speed in a static variable: if the
* I2C routines are called before RAM is initialized (to read
@@ -290,7 +280,6 @@
* system will crash.
*/
send_reset ();
-#endif
}
/*-----------------------------------------------------------------------
diff --git a/drivers/mmc/ca_dw_mmc.c b/drivers/mmc/ca_dw_mmc.c
index 54a2ba4..1af5ec0 100644
--- a/drivers/mmc/ca_dw_mmc.c
+++ b/drivers/mmc/ca_dw_mmc.c
@@ -86,7 +86,7 @@
clk_div = 1;
}
- return SD_SCLK_MAX / clk_div / (host->div + 1);
+ return SD_SCLK_MAX / clk_div;
}
static int ca_dwmmc_of_to_plat(struct udevice *dev)
diff --git a/drivers/mmc/dw_mmc.c b/drivers/mmc/dw_mmc.c
index f4ecd74..8551eac 100644
--- a/drivers/mmc/dw_mmc.c
+++ b/drivers/mmc/dw_mmc.c
@@ -20,6 +20,47 @@
#define PAGE_SIZE 4096
+/* Internal DMA Controller (IDMAC) descriptor for 32-bit addressing mode */
+struct dwmci_idmac32 {
+ u32 des0; /* Control descriptor */
+ u32 des1; /* Buffer size */
+ u32 des2; /* Buffer physical address */
+ u32 des3; /* Next descriptor physical address */
+} __aligned(ARCH_DMA_MINALIGN);
+
+/* Internal DMA Controller (IDMAC) descriptor for 64-bit addressing mode */
+struct dwmci_idmac64 {
+ u32 des0; /* Control descriptor */
+ u32 des1; /* Reserved */
+ u32 des2; /* Buffer sizes */
+ u32 des3; /* Reserved */
+ u32 des4; /* Lower 32-bits of Buffer Address Pointer 1 */
+ u32 des5; /* Upper 32-bits of Buffer Address Pointer 1 */
+ u32 des6; /* Lower 32-bits of Next Descriptor Address */
+ u32 des7; /* Upper 32-bits of Next Descriptor Address */
+} __aligned(ARCH_DMA_MINALIGN);
+
+/* Register offsets for DW MMC blocks with 32-bit IDMAC */
+static const struct dwmci_idmac_regs dwmci_idmac_regs32 = {
+ .dbaddrl = DWMCI_DBADDR,
+ .idsts = DWMCI_IDSTS,
+ .idinten = DWMCI_IDINTEN,
+ .dscaddrl = DWMCI_DSCADDR,
+ .bufaddrl = DWMCI_BUFADDR,
+};
+
+/* Register offsets for DW MMC blocks with 64-bit IDMAC */
+static const struct dwmci_idmac_regs dwmci_idmac_regs64 = {
+ .dbaddrl = DWMCI_DBADDRL,
+ .dbaddru = DWMCI_DBADDRU,
+ .idsts = DWMCI_IDSTS64,
+ .idinten = DWMCI_IDINTEN64,
+ .dscaddrl = DWMCI_DSCADDRL,
+ .dscaddru = DWMCI_DSCADDRU,
+ .bufaddrl = DWMCI_BUFADDRL,
+ .bufaddru = DWMCI_BUFADDRU,
+};
+
static int dwmci_wait_reset(struct dwmci_host *host, u32 value)
{
unsigned long timeout = 1000;
@@ -35,57 +76,98 @@
return 0;
}
-static void dwmci_set_idma_desc(struct dwmci_idmac *idmac,
- u32 desc0, u32 desc1, u32 desc2)
+static void dwmci_set_idma_desc32(struct dwmci_idmac32 *desc, u32 control,
+ u32 buf_size, u32 buf_addr)
{
- struct dwmci_idmac *desc = idmac;
+ phys_addr_t desc_phys = virt_to_phys(desc);
+ u32 next_desc_phys = desc_phys + sizeof(struct dwmci_idmac32);
- desc->flags = desc0;
- desc->cnt = desc1;
- desc->addr = desc2;
- desc->next_addr = (ulong)desc + sizeof(struct dwmci_idmac);
+ desc->des0 = control;
+ desc->des1 = buf_size;
+ desc->des2 = buf_addr;
+ desc->des3 = next_desc_phys;
}
-static void dwmci_prepare_data(struct dwmci_host *host,
- struct mmc_data *data,
- struct dwmci_idmac *cur_idmac,
- void *bounce_buffer)
+static void dwmci_set_idma_desc64(struct dwmci_idmac64 *desc, u32 control,
+ u32 buf_size, u64 buf_addr)
{
- unsigned long ctrl;
- unsigned int i = 0, flags, cnt, blk_cnt;
- ulong data_start, data_end;
-
- blk_cnt = data->blocks;
+ phys_addr_t desc_phys = virt_to_phys(desc);
+ u64 next_desc_phys = desc_phys + sizeof(struct dwmci_idmac64);
- dwmci_wait_reset(host, DWMCI_CTRL_FIFO_RESET);
+ desc->des0 = control;
+ desc->des1 = 0;
+ desc->des2 = buf_size;
+ desc->des3 = 0;
+ desc->des4 = buf_addr & 0xffffffff;
+ desc->des5 = buf_addr >> 32;
+ desc->des6 = next_desc_phys & 0xffffffff;
+ desc->des7 = next_desc_phys >> 32;
+}
- /* Clear IDMAC interrupt */
- dwmci_writel(host, DWMCI_IDSTS, 0xFFFFFFFF);
+static void dwmci_prepare_desc(struct dwmci_host *host, struct mmc_data *data,
+ void *cur_idmac, void *bounce_buffer)
+{
+ struct dwmci_idmac32 *desc32 = cur_idmac;
+ struct dwmci_idmac64 *desc64 = cur_idmac;
+ ulong data_start, data_end;
+ unsigned int blk_cnt, i;
data_start = (ulong)cur_idmac;
- dwmci_writel(host, DWMCI_DBADDR, (ulong)cur_idmac);
+ blk_cnt = data->blocks;
- do {
- flags = DWMCI_IDMAC_OWN | DWMCI_IDMAC_CH ;
- flags |= (i == 0) ? DWMCI_IDMAC_FS : 0;
+ for (i = 0;; i++) {
+ phys_addr_t buf_phys = virt_to_phys(bounce_buffer);
+ unsigned int flags, cnt;
+
+ flags = DWMCI_IDMAC_OWN | DWMCI_IDMAC_CH;
+ if (i == 0)
+ flags |= DWMCI_IDMAC_FS;
if (blk_cnt <= 8) {
flags |= DWMCI_IDMAC_LD;
cnt = data->blocksize * blk_cnt;
- } else
+ } else {
cnt = data->blocksize * 8;
+ }
- dwmci_set_idma_desc(cur_idmac, flags, cnt,
- (ulong)bounce_buffer + (i * PAGE_SIZE));
+ if (host->dma_64bit_address) {
+ dwmci_set_idma_desc64(desc64, flags, cnt,
+ buf_phys + i * PAGE_SIZE);
+ desc64++;
+ } else {
+ dwmci_set_idma_desc32(desc32, flags, cnt,
+ buf_phys + i * PAGE_SIZE);
+ desc32++;
+ }
- cur_idmac++;
if (blk_cnt <= 8)
break;
blk_cnt -= 8;
- i++;
- } while(1);
+ }
- data_end = (ulong)cur_idmac;
+ if (host->dma_64bit_address)
+ data_end = (ulong)desc64;
+ else
+ data_end = (ulong)desc32;
flush_dcache_range(data_start, roundup(data_end, ARCH_DMA_MINALIGN));
+}
+
+static void dwmci_prepare_data(struct dwmci_host *host, struct mmc_data *data,
+ void *cur_idmac, void *bounce_buffer)
+{
+ const u32 idmacl = virt_to_phys(cur_idmac) & 0xffffffff;
+ const u32 idmacu = (u64)virt_to_phys(cur_idmac) >> 32;
+ unsigned long ctrl;
+
+ dwmci_wait_reset(host, DWMCI_CTRL_FIFO_RESET);
+
+ /* Clear IDMAC interrupt */
+ dwmci_writel(host, host->regs->idsts, 0xffffffff);
+
+ dwmci_writel(host, host->regs->dbaddrl, idmacl);
+ if (host->dma_64bit_address)
+ dwmci_writel(host, host->regs->dbaddru, idmacu);
+
+ dwmci_prepare_desc(host, data, cur_idmac, bounce_buffer);
ctrl = dwmci_readl(host, DWMCI_CTRL);
ctrl |= DWMCI_IDMAC_EN | DWMCI_DMA_EN;
@@ -132,90 +214,86 @@
return timeout;
}
-static int dwmci_data_transfer(struct dwmci_host *host, struct mmc_data *data)
+static int dwmci_data_transfer_fifo(struct dwmci_host *host,
+ struct mmc_data *data, u32 mask)
{
- struct mmc *mmc = host->mmc;
+ const u32 int_rx = mask & (DWMCI_INTMSK_RXDR | DWMCI_INTMSK_DTO);
+ const u32 int_tx = mask & DWMCI_INTMSK_TXDR;
int ret = 0;
- u32 timeout, mask, size, i, len = 0;
- u32 *buf = NULL;
- ulong start = get_timer(0);
- u32 fifo_depth = (((host->fifoth_val & RX_WMARK_MASK) >>
- RX_WMARK_SHIFT) + 1) * 2;
+ u32 len = 0, size, i;
+ u32 *buf;
- size = data->blocksize * data->blocks;
+ size = (data->blocksize * data->blocks) / 4;
+ if (!host->fifo_mode || !size)
+ return 0;
+
if (data->flags == MMC_DATA_READ)
buf = (unsigned int *)data->dest;
else
buf = (unsigned int *)data->src;
- timeout = dwmci_get_timeout(mmc, size);
+ if (data->flags == MMC_DATA_READ && int_rx) {
+ dwmci_writel(host, DWMCI_RINTSTS, int_rx);
+ while (size) {
+ ret = dwmci_fifo_ready(host, DWMCI_FIFO_EMPTY, &len);
+ if (ret < 0)
+ break;
+
+ len = (len >> DWMCI_FIFO_SHIFT) & DWMCI_FIFO_MASK;
+ len = min(size, len);
+ for (i = 0; i < len; i++)
+ *buf++ = dwmci_readl(host, DWMCI_DATA);
+ size = size > len ? (size - len) : 0;
+ }
+ } else if (data->flags == MMC_DATA_WRITE && int_tx) {
+ while (size) {
+ ret = dwmci_fifo_ready(host, DWMCI_FIFO_FULL, &len);
+ if (ret < 0)
+ break;
+
+ len = host->fifo_depth - ((len >> DWMCI_FIFO_SHIFT) &
+ DWMCI_FIFO_MASK);
+ len = min(size, len);
+ for (i = 0; i < len; i++)
+ dwmci_writel(host, DWMCI_DATA, *buf++);
+ size = size > len ? (size - len) : 0;
+ }
+ dwmci_writel(host, DWMCI_RINTSTS, DWMCI_INTMSK_TXDR);
+ }
- size /= 4;
+ return ret;
+}
+
+static int dwmci_data_transfer(struct dwmci_host *host, struct mmc_data *data)
+{
+ struct mmc *mmc = host->mmc;
+ int ret = 0;
+ u32 timeout, mask, size;
+ ulong start = get_timer(0);
+
+ size = data->blocksize * data->blocks;
+ timeout = dwmci_get_timeout(mmc, size);
for (;;) {
mask = dwmci_readl(host, DWMCI_RINTSTS);
- /* Error during data transfer. */
+ /* Error during data transfer */
if (mask & (DWMCI_DATA_ERR | DWMCI_DATA_TOUT)) {
debug("%s: DATA ERROR!\n", __func__);
ret = -EINVAL;
break;
}
- if (host->fifo_mode && size) {
- len = 0;
- if (data->flags == MMC_DATA_READ &&
- (mask & (DWMCI_INTMSK_RXDR | DWMCI_INTMSK_DTO))) {
- dwmci_writel(host, DWMCI_RINTSTS,
- mask & (DWMCI_INTMSK_RXDR |
- DWMCI_INTMSK_DTO));
- while (size) {
- ret = dwmci_fifo_ready(host,
- DWMCI_FIFO_EMPTY,
- &len);
- if (ret < 0)
- break;
+ ret = dwmci_data_transfer_fifo(host, data, mask);
- len = (len >> DWMCI_FIFO_SHIFT) &
- DWMCI_FIFO_MASK;
- len = min(size, len);
- for (i = 0; i < len; i++)
- *buf++ =
- dwmci_readl(host, DWMCI_DATA);
- size = size > len ? (size - len) : 0;
- }
- } else if (data->flags == MMC_DATA_WRITE &&
- (mask & DWMCI_INTMSK_TXDR)) {
- while (size) {
- ret = dwmci_fifo_ready(host,
- DWMCI_FIFO_FULL,
- &len);
- if (ret < 0)
- break;
-
- len = fifo_depth - ((len >>
- DWMCI_FIFO_SHIFT) &
- DWMCI_FIFO_MASK);
- len = min(size, len);
- for (i = 0; i < len; i++)
- dwmci_writel(host, DWMCI_DATA,
- *buf++);
- size = size > len ? (size - len) : 0;
- }
- dwmci_writel(host, DWMCI_RINTSTS,
- DWMCI_INTMSK_TXDR);
- }
- }
-
- /* Data arrived correctly. */
+ /* Data arrived correctly */
if (mask & DWMCI_INTMSK_DTO) {
ret = 0;
break;
}
- /* Check for timeout. */
+ /* Check for timeout */
if (get_timer(start) > timeout) {
- debug("%s: Timeout waiting for data!\n",
- __func__);
+ debug("%s: Timeout waiting for data!\n", __func__);
ret = -ETIMEDOUT;
break;
}
@@ -223,11 +301,38 @@
dwmci_writel(host, DWMCI_RINTSTS, mask);
+ return ret;
+}
+
+static int dwmci_dma_transfer(struct dwmci_host *host, uint flags,
+ struct bounce_buffer *bbstate)
+{
+ int ret;
+ u32 mask, ctrl;
+
+ if (flags == MMC_DATA_READ)
+ mask = DWMCI_IDINTEN_RI;
+ else
+ mask = DWMCI_IDINTEN_TI;
+
+ ret = wait_for_bit_le32(host->ioaddr + host->regs->idsts, mask, true,
+ 1000, false);
+ if (ret)
+ debug("%s: DWMCI_IDINTEN mask 0x%x timeout\n", __func__, mask);
+
+ /* Clear interrupts */
+ dwmci_writel(host, host->regs->idsts, DWMCI_IDINTEN_MASK);
+
+ ctrl = dwmci_readl(host, DWMCI_CTRL);
+ ctrl &= ~DWMCI_DMA_EN;
+ dwmci_writel(host, DWMCI_CTRL, ctrl);
+
+ bounce_buffer_stop(bbstate);
return ret;
}
static int dwmci_set_transfer_mode(struct dwmci_host *host,
- struct mmc_data *data)
+ struct mmc_data *data)
{
unsigned long mode;
@@ -238,33 +343,30 @@
return mode;
}
-#ifdef CONFIG_DM_MMC
-static int dwmci_send_cmd(struct udevice *dev, struct mmc_cmd *cmd,
- struct mmc_data *data)
-{
- struct mmc *mmc = mmc_get_mmc_dev(dev);
-#else
-static int dwmci_send_cmd(struct mmc *mmc, struct mmc_cmd *cmd,
- struct mmc_data *data)
+static void dwmci_wait_while_busy(struct dwmci_host *host, struct mmc_cmd *cmd)
{
-#endif
- struct dwmci_host *host = mmc->priv;
- ALLOC_CACHE_ALIGN_BUFFER(struct dwmci_idmac, cur_idmac,
- data ? DIV_ROUND_UP(data->blocks, 8) : 0);
- int ret = 0, flags = 0, i;
- unsigned int timeout = 500;
- u32 retry = 100000;
- u32 mask, ctrl;
- ulong start = get_timer(0);
- struct bounce_buffer bbstate;
+ unsigned int timeout = 500; /* msec */
+ ulong start;
+ start = get_timer(0);
while (dwmci_readl(host, DWMCI_STATUS) & DWMCI_BUSY) {
if (get_timer(start) > timeout) {
- debug("%s: Timeout on data busy, continue anyway\n", __func__);
+ debug("%s: Timeout on data busy, continue anyway\n",
+ __func__);
break;
}
}
+}
+
+static int dwmci_send_cmd_common(struct dwmci_host *host, struct mmc_cmd *cmd,
+ struct mmc_data *data, void *cur_idmac)
+{
+ int ret, flags = 0, i;
+ u32 retry = 100000;
+ u32 mask;
+ struct bounce_buffer bbstate;
+ dwmci_wait_while_busy(host, cmd);
dwmci_writel(host, DWMCI_RINTSTS, DWMCI_INTMSK_ALL);
if (data) {
@@ -276,12 +378,12 @@
} else {
if (data->flags == MMC_DATA_READ) {
ret = bounce_buffer_start(&bbstate,
- (void*)data->dest,
+ (void *)data->dest,
data->blocksize *
data->blocks, GEN_BB_WRITE);
} else {
ret = bounce_buffer_start(&bbstate,
- (void*)data->src,
+ (void *)data->src,
data->blocksize *
data->blocks, GEN_BB_READ);
}
@@ -316,9 +418,9 @@
if (cmd->resp_type & MMC_RSP_CRC)
flags |= DWMCI_CMD_CHECK_CRC;
- flags |= (cmd->cmdidx | DWMCI_CMD_START | DWMCI_CMD_USE_HOLD_REG);
+ flags |= cmd->cmdidx | DWMCI_CMD_START | DWMCI_CMD_USE_HOLD_REG;
- debug("Sending CMD%d\n",cmd->cmdidx);
+ debug("Sending CMD%d\n", cmd->cmdidx);
dwmci_writel(host, DWMCI_CMD, flags);
@@ -332,7 +434,7 @@
}
if (i == retry) {
- debug("%s: Timeout.\n", __func__);
+ debug("%s: Timeout\n", __func__);
return -ETIMEDOUT;
}
@@ -345,14 +447,14 @@
* below shall be debug(). eMMC cards also do not favor
* CMD8, please keep that in mind.
*/
- debug("%s: Response Timeout.\n", __func__);
+ debug("%s: Response Timeout\n", __func__);
return -ETIMEDOUT;
} else if (mask & DWMCI_INTMSK_RE) {
- debug("%s: Response Error.\n", __func__);
+ debug("%s: Response Error\n", __func__);
return -EIO;
} else if ((cmd->resp_type & MMC_RSP_CRC) &&
(mask & DWMCI_INTMSK_RCRC)) {
- debug("%s: Response CRC Error.\n", __func__);
+ debug("%s: Response CRC Error\n", __func__);
return -EIO;
}
@@ -369,26 +471,8 @@
if (data) {
ret = dwmci_data_transfer(host, data);
-
- /* only dma mode need it */
- if (!host->fifo_mode) {
- if (data->flags == MMC_DATA_READ)
- mask = DWMCI_IDINTEN_RI;
- else
- mask = DWMCI_IDINTEN_TI;
- ret = wait_for_bit_le32(host->ioaddr + DWMCI_IDSTS,
- mask, true, 1000, false);
- if (ret)
- debug("%s: DWMCI_IDINTEN mask 0x%x timeout.\n",
- __func__, mask);
- /* clear interrupts */
- dwmci_writel(host, DWMCI_IDSTS, DWMCI_IDINTEN_MASK);
-
- ctrl = dwmci_readl(host, DWMCI_CTRL);
- ctrl &= ~(DWMCI_DMA_EN);
- dwmci_writel(host, DWMCI_CTRL, ctrl);
- bounce_buffer_stop(&bbstate);
- }
+ if (!host->fifo_mode)
+ ret = dwmci_dma_transfer(host, data->flags, &bbstate);
}
udelay(100);
@@ -396,40 +480,39 @@
return ret;
}
-static int dwmci_setup_bus(struct dwmci_host *host, u32 freq)
+#ifdef CONFIG_DM_MMC
+static int dwmci_send_cmd(struct udevice *dev, struct mmc_cmd *cmd,
+ struct mmc_data *data)
{
- u32 div, status;
- int timeout = 10000;
- unsigned long sclk;
+ struct mmc *mmc = mmc_get_mmc_dev(dev);
+#else
+static int dwmci_send_cmd(struct mmc *mmc, struct mmc_cmd *cmd,
+ struct mmc_data *data)
+{
+#endif
+ struct dwmci_host *host = mmc->priv;
+ const size_t buf_size = data ? DIV_ROUND_UP(data->blocks, 8) : 0;
- if ((freq == host->clock) || (freq == 0))
- return 0;
- /*
- * If host->get_mmc_clk isn't defined,
- * then assume that host->bus_hz is source clock value.
- * host->bus_hz should be set by user.
- */
- if (host->get_mmc_clk)
- sclk = host->get_mmc_clk(host, freq);
- else if (host->bus_hz)
- sclk = host->bus_hz;
- else {
- debug("%s: Didn't get source clock value.\n", __func__);
- return -EINVAL;
+ if (host->dma_64bit_address) {
+ ALLOC_CACHE_ALIGN_BUFFER(struct dwmci_idmac64, idmac, buf_size);
+ return dwmci_send_cmd_common(host, cmd, data, idmac);
+ } else {
+ ALLOC_CACHE_ALIGN_BUFFER(struct dwmci_idmac32, idmac, buf_size);
+ return dwmci_send_cmd_common(host, cmd, data, idmac);
}
-
- if (sclk == freq)
- div = 0; /* bypass mode */
- else
- div = DIV_ROUND_UP(sclk, 2 * freq);
+}
- dwmci_writel(host, DWMCI_CLKENA, 0);
- dwmci_writel(host, DWMCI_CLKSRC, 0);
+static int dwmci_control_clken(struct dwmci_host *host, bool on)
+{
+ const u32 val = on ? DWMCI_CLKEN_ENABLE | DWMCI_CLKEN_LOW_PWR : 0;
+ const u32 cmd_only_clk = DWMCI_CMD_PRV_DAT_WAIT | DWMCI_CMD_UPD_CLK;
+ int timeout = 10000;
+ u32 status;
- dwmci_writel(host, DWMCI_CLKDIV, div);
- dwmci_writel(host, DWMCI_CMD, DWMCI_CMD_PRV_DAT_WAIT |
- DWMCI_CMD_UPD_CLK | DWMCI_CMD_START);
+ dwmci_writel(host, DWMCI_CLKENA, val);
+ /* Inform CIU */
+ dwmci_writel(host, DWMCI_CMD, DWMCI_CMD_START | cmd_only_clk);
do {
status = dwmci_readl(host, DWMCI_CMD);
if (timeout-- < 0) {
@@ -438,20 +521,62 @@
}
} while (status & DWMCI_CMD_START);
- dwmci_writel(host, DWMCI_CLKENA, DWMCI_CLKEN_ENABLE |
- DWMCI_CLKEN_LOW_PWR);
+ return 0;
+}
- dwmci_writel(host, DWMCI_CMD, DWMCI_CMD_PRV_DAT_WAIT |
- DWMCI_CMD_UPD_CLK | DWMCI_CMD_START);
+/*
+ * Update the clock divider.
+ *
+ * To prevent a clock glitch keep the clock stopped during the update of
+ * clock divider and clock source.
+ */
+static int dwmci_update_div(struct dwmci_host *host, u32 div)
+{
+ int ret;
- timeout = 10000;
- do {
- status = dwmci_readl(host, DWMCI_CMD);
- if (timeout-- < 0) {
- debug("%s: Timeout!\n", __func__);
- return -ETIMEDOUT;
- }
- } while (status & DWMCI_CMD_START);
+ /* Disable clock */
+ ret = dwmci_control_clken(host, false);
+ if (ret)
+ return ret;
+
+ /* Set clock to desired speed */
+ dwmci_writel(host, DWMCI_CLKDIV, div);
+ dwmci_writel(host, DWMCI_CLKSRC, 0);
+
+ /* Enable clock */
+ return dwmci_control_clken(host, true);
+}
+
+static int dwmci_setup_bus(struct dwmci_host *host, u32 freq)
+{
+ u32 div;
+ unsigned long sclk;
+ int ret;
+
+ if (freq == host->clock || freq == 0)
+ return 0;
+
+ /*
+ * If host->get_mmc_clk isn't defined, then assume that host->bus_hz is
+ * source clock value. host->bus_hz should be set by user.
+ */
+ if (host->get_mmc_clk) {
+ sclk = host->get_mmc_clk(host, freq);
+ } else if (host->bus_hz) {
+ sclk = host->bus_hz;
+ } else {
+ debug("%s: Didn't get source clock value\n", __func__);
+ return -EINVAL;
+ }
+
+ if (sclk == freq)
+ div = 0; /* bypass mode */
+ else
+ div = DIV_ROUND_UP(sclk, 2 * freq);
+
+ ret = dwmci_update_div(host, div);
+ if (ret)
+ return ret;
host->clock = freq;
@@ -469,7 +594,7 @@
struct dwmci_host *host = (struct dwmci_host *)mmc->priv;
u32 ctype, regs;
- debug("Buswidth = %d, clock: %d\n", mmc->bus_width, mmc->clock);
+ debug("Bus width = %d, clock: %d\n", mmc->bus_width, mmc->clock);
dwmci_setup_bus(host, mmc->clock);
switch (mmc->bus_width) {
@@ -524,6 +649,48 @@
return 0;
}
+static void dwmci_init_fifo(struct dwmci_host *host)
+{
+ u32 fifo_thr, fifoth_val;
+
+ if (!host->fifo_depth) {
+ u32 fifo_size;
+
+ /*
+ * Automatically detect FIFO depth from FIFOTH register.
+ * Power-on value of RX_WMark is FIFO_DEPTH-1.
+ */
+ fifo_size = dwmci_readl(host, DWMCI_FIFOTH);
+ fifo_size = ((fifo_size & RX_WMARK_MASK) >> RX_WMARK_SHIFT) + 1;
+ host->fifo_depth = fifo_size;
+ }
+
+ fifo_thr = host->fifo_depth / 2;
+ fifoth_val = MSIZE(0x2) | RX_WMARK(fifo_thr - 1) | TX_WMARK(fifo_thr);
+ dwmci_writel(host, DWMCI_FIFOTH, fifoth_val);
+}
+
+static void dwmci_init_dma(struct dwmci_host *host)
+{
+ int addr_config;
+
+ if (host->fifo_mode)
+ return;
+
+ addr_config = (dwmci_readl(host, DWMCI_HCON) >> 27) & 0x1;
+ if (addr_config == 1) {
+ host->dma_64bit_address = true;
+ host->regs = &dwmci_idmac_regs64;
+ debug("%s: IDMAC supports 64-bit address mode\n", __func__);
+ } else {
+ host->dma_64bit_address = false;
+ host->regs = &dwmci_idmac_regs32;
+ debug("%s: IDMAC supports 32-bit address mode\n", __func__);
+ }
+
+ dwmci_writel(host, host->regs->idinten, DWMCI_IDINTEN_MASK);
+}
+
static int dwmci_init(struct mmc *mmc)
{
struct dwmci_host *host = mmc->priv;
@@ -541,30 +708,18 @@
/* Enumerate at 400KHz */
dwmci_setup_bus(host, mmc->cfg->f_min);
- dwmci_writel(host, DWMCI_RINTSTS, 0xFFFFFFFF);
+ dwmci_writel(host, DWMCI_RINTSTS, 0xffffffff);
dwmci_writel(host, DWMCI_INTMASK, 0);
- dwmci_writel(host, DWMCI_TMOUT, 0xFFFFFFFF);
+ dwmci_writel(host, DWMCI_TMOUT, 0xffffffff);
- dwmci_writel(host, DWMCI_IDINTEN, 0);
dwmci_writel(host, DWMCI_BMOD, 1);
-
- if (!host->fifoth_val) {
- uint32_t fifo_size;
-
- fifo_size = dwmci_readl(host, DWMCI_FIFOTH);
- fifo_size = ((fifo_size & RX_WMARK_MASK) >> RX_WMARK_SHIFT) + 1;
- host->fifoth_val = MSIZE(0x2) | RX_WMARK(fifo_size / 2 - 1) |
- TX_WMARK(fifo_size / 2);
- }
- dwmci_writel(host, DWMCI_FIFOTH, host->fifoth_val);
+ dwmci_init_fifo(host);
+ dwmci_init_dma(host);
dwmci_writel(host, DWMCI_CLKENA, 0);
dwmci_writel(host, DWMCI_CLKSRC, 0);
- if (!host->fifo_mode)
- dwmci_writel(host, DWMCI_IDINTEN, DWMCI_IDINTEN_MASK);
-
return 0;
}
@@ -590,7 +745,7 @@
#endif
void dwmci_setup_cfg(struct mmc_config *cfg, struct dwmci_host *host,
- u32 max_clk, u32 min_clk)
+ u32 max_clk, u32 min_clk)
{
cfg->name = host->name;
#ifndef CONFIG_DM_MMC
@@ -626,7 +781,7 @@
dwmci_setup_cfg(&host->cfg, host, max_clk, min_clk);
host->mmc = mmc_create(&host->cfg, host);
- if (host->mmc == NULL)
+ if (!host->mmc)
return -1;
return 0;
diff --git a/drivers/mmc/exynos_dw_mmc.c b/drivers/mmc/exynos_dw_mmc.c
index a51f762..c8bf89d 100644
--- a/drivers/mmc/exynos_dw_mmc.c
+++ b/drivers/mmc/exynos_dw_mmc.c
@@ -4,10 +4,9 @@
* Jaehoon Chung <jh80.chung@samsung.com>
*/
+#include <clk.h>
#include <dwmmc.h>
-#include <fdtdec.h>
#include <asm/global_data.h>
-#include <linux/libfdt.h>
#include <malloc.h>
#include <errno.h>
#include <asm/arch/dwmmc.h>
@@ -15,6 +14,7 @@
#include <asm/arch/pinmux.h>
#include <asm/arch/power.h>
#include <asm/gpio.h>
+#include <linux/err.h>
#include <linux/printk.h>
#define DWMMC_MAX_CH_NUM 4
@@ -23,6 +23,11 @@
#define DWMMC_MMC0_SDR_TIMING_VAL 0x03030001
#define DWMMC_MMC2_SDR_TIMING_VAL 0x03020001
+#define EXYNOS4412_FIXED_CIU_CLK_DIV 4
+
+/* Quirks */
+#define DWMCI_QUIRK_DISABLE_SMU BIT(0)
+
#ifdef CONFIG_DM_MMC
#include <dm.h>
DECLARE_GLOBAL_DATA_PTR;
@@ -33,35 +38,117 @@
};
#endif
-/* Exynos implmentation specific drver private data */
+/* Chip specific data */
+struct exynos_dwmmc_variant {
+ u32 clksel; /* CLKSEL register offset */
+ u8 div; /* (optional) fixed clock divider value: 0..7 */
+ u32 quirks; /* quirk flags - see DWMCI_QUIRK_... */
+};
+
+/* Exynos implementation specific driver private data */
struct dwmci_exynos_priv_data {
#ifdef CONFIG_DM_MMC
struct dwmci_host host;
#endif
+ struct clk clk;
u32 sdr_timing;
+ u32 ddr_timing;
+ const struct exynos_dwmmc_variant *chip;
};
-/*
- * Function used as callback function to initialise the
- * CLKSEL register for every mmc channel.
- */
-static int exynos_dwmci_clksel(struct dwmci_host *host)
+static struct dwmci_exynos_priv_data *exynos_dwmmc_get_priv(
+ struct dwmci_host *host)
{
#ifdef CONFIG_DM_MMC
- struct dwmci_exynos_priv_data *priv =
- container_of(host, struct dwmci_exynos_priv_data, host);
+ return container_of(host, struct dwmci_exynos_priv_data, host);
#else
- struct dwmci_exynos_priv_data *priv = host->priv;
+ return host->priv;
#endif
- dwmci_writel(host, DWMCI_CLKSEL, priv->sdr_timing);
+}
+
+/**
+ * exynos_dwmmc_get_sclk - Get source clock (SDCLKIN) rate
+ * @host: MMC controller object
+ * @rate: Will contain clock rate, Hz
+ *
+ * Return: 0 on success or negative value on error
+ */
+static int exynos_dwmmc_get_sclk(struct dwmci_host *host, unsigned long *rate)
+{
+#ifdef CONFIG_CPU_V7A
+ *rate = get_mmc_clk(host->dev_index);
+#else
+ struct dwmci_exynos_priv_data *priv = exynos_dwmmc_get_priv(host);
+
+ *rate = clk_get_rate(&priv->clk);
+#endif
+
+ if (IS_ERR_VALUE(*rate))
+ return *rate;
return 0;
}
-unsigned int exynos_dwmci_get_clk(struct dwmci_host *host, uint freq)
+/**
+ * exynos_dwmmc_set_sclk - Set source clock (SDCLKIN) rate
+ * @host: MMC controller object
+ * @rate: Desired clock rate, Hz
+ *
+ * Return: 0 on success or negative value on error
+ */
+static int exynos_dwmmc_set_sclk(struct dwmci_host *host, unsigned long rate)
{
+ int err;
+
+#ifdef CONFIG_CPU_V7A
unsigned long sclk;
- int8_t clk_div;
+ unsigned int div;
+
+ err = exynos_dwmmc_get_sclk(host, &sclk);
+ if (err)
+ return err;
+
+ div = DIV_ROUND_UP(sclk, rate);
+ set_mmc_clk(host->dev_index, div);
+#else
+ struct dwmci_exynos_priv_data *priv = exynos_dwmmc_get_priv(host);
+
+ err = clk_set_rate(&priv->clk, rate);
+ if (err < 0)
+ return err;
+#endif
+
+ return 0;
+}
+
+/* Configure CLKSEL register with chosen timing values */
+static int exynos_dwmci_clksel(struct dwmci_host *host)
+{
+ struct dwmci_exynos_priv_data *priv = exynos_dwmmc_get_priv(host);
+ u32 timing;
+
+ if (host->mmc->selected_mode == MMC_DDR_52)
+ timing = priv->ddr_timing;
+ else
+ timing = priv->sdr_timing;
+
+ dwmci_writel(host, priv->chip->clksel, timing);
+
+ return 0;
+}
+
+/**
+ * exynos_dwmmc_get_ciu_div - Get internal clock divider value
+ * @host: MMC controller object
+ *
+ * Returns: Divider value, in range of 1..8
+ */
+static u8 exynos_dwmmc_get_ciu_div(struct dwmci_host *host)
+{
+ struct dwmci_exynos_priv_data *priv = exynos_dwmmc_get_priv(host);
+
+ if (priv->chip->div)
+ return priv->chip->div + 1;
/*
* Since SDCLKIN is divided inside controller by the DIVRATIO
@@ -69,22 +156,42 @@
* clock value to calculate the CLKDIV value.
* as per user manual:cclk_in = SDCLKIN / (DIVRATIO + 1)
*/
- clk_div = ((dwmci_readl(host, DWMCI_CLKSEL) >> DWMCI_DIVRATIO_BIT)
- & DWMCI_DIVRATIO_MASK) + 1;
- sclk = get_mmc_clk(host->dev_index);
+ return ((dwmci_readl(host, priv->chip->clksel) >> DWMCI_DIVRATIO_BIT)
+ & DWMCI_DIVRATIO_MASK) + 1;
+}
- /*
- * Assume to know divider value.
- * When clock unit is broken, need to set "host->div"
- */
- return sclk / clk_div / (host->div + 1);
+static unsigned int exynos_dwmci_get_clk(struct dwmci_host *host, uint freq)
+{
+ unsigned long sclk;
+ u8 clk_div;
+ int err;
+
+ /* Should be double rate for DDR mode */
+ if (host->mmc->selected_mode == MMC_DDR_52 && host->mmc->bus_width == 8)
+ freq *= 2;
+
+ clk_div = exynos_dwmmc_get_ciu_div(host);
+ err = exynos_dwmmc_set_sclk(host, freq * clk_div);
+ if (err) {
+ printf("DWMMC%d: failed to set clock rate (%d); "
+ "continue anyway\n", host->dev_index, err);
+ }
+
+ err = exynos_dwmmc_get_sclk(host, &sclk);
+ if (err) {
+ printf("DWMMC%d: failed to get clock rate (%d)\n",
+ host->dev_index, err);
+ return 0;
+ }
+
+ return sclk / clk_div;
}
static void exynos_dwmci_board_init(struct dwmci_host *host)
{
- struct dwmci_exynos_priv_data *priv = host->priv;
+ struct dwmci_exynos_priv_data *priv = exynos_dwmmc_get_priv(host);
- if (host->quirks & DWMCI_QUIRK_DISABLE_SMU) {
+ if (priv->chip->quirks & DWMCI_QUIRK_DISABLE_SMU) {
dwmci_writel(host, EMMCP_MPSBEGIN0, 0);
dwmci_writel(host, EMMCP_SEND0, 0);
dwmci_writel(host, EMMCP_CTRL0,
@@ -94,73 +201,27 @@
MPSCTRL_NON_SECURE_WRITE_BIT | MPSCTRL_VALID);
}
- /* Set to timing value at initial time */
if (priv->sdr_timing)
exynos_dwmci_clksel(host);
}
-static int exynos_dwmci_core_init(struct dwmci_host *host)
-{
- unsigned int div;
- unsigned long freq, sclk;
-
- if (host->bus_hz)
- freq = host->bus_hz;
- else
- freq = DWMMC_MAX_FREQ;
-
- /* request mmc clock vlaue of 52MHz. */
- sclk = get_mmc_clk(host->dev_index);
- div = DIV_ROUND_UP(sclk, freq);
- /* set the clock divisor for mmc */
- set_mmc_clk(host->dev_index, div);
-
- host->name = "EXYNOS DWMMC";
-#ifdef CONFIG_EXYNOS5420
- host->quirks = DWMCI_QUIRK_DISABLE_SMU;
-#endif
- host->board_init = exynos_dwmci_board_init;
-
- host->caps = MMC_MODE_DDR_52MHz;
- host->clksel = exynos_dwmci_clksel;
- host->get_mmc_clk = exynos_dwmci_get_clk;
-
-#ifndef CONFIG_DM_MMC
- /* Add the mmc channel to be registered with mmc core */
- if (add_dwmci(host, DWMMC_MAX_FREQ, DWMMC_MIN_FREQ)) {
- printf("DWMMC%d registration failed\n", host->dev_index);
- return -1;
- }
-#endif
-
- return 0;
-}
-
-static int do_dwmci_init(struct dwmci_host *host)
+#ifdef CONFIG_DM_MMC
+static int exynos_dwmmc_of_to_plat(struct udevice *dev)
{
- int flag, err;
+ struct dwmci_exynos_priv_data *priv = dev_get_priv(dev);
+ struct dwmci_host *host = &priv->host;
+ u32 div, timing[2];
+ int err;
- flag = host->buswidth == 8 ? PINMUX_FLAG_8BIT_MODE : PINMUX_FLAG_NONE;
- err = exynos_pinmux_config(host->dev_id, flag);
- if (err) {
- printf("DWMMC%d not configure\n", host->dev_index);
- return err;
- }
+ priv->chip = (struct exynos_dwmmc_variant *)dev_get_driver_data(dev);
- return exynos_dwmci_core_init(host);
-}
+#ifdef CONFIG_CPU_V7A
+ const void *blob = gd->fdt_blob;
+ int node = dev_of_offset(dev);
-static int exynos_dwmci_get_config(const void *blob, int node,
- struct dwmci_host *host,
- struct dwmci_exynos_priv_data *priv)
-{
- int err = 0;
- u32 base, timing[3];
-
- /* Extract device id for each mmc channel */
+ /* Obtain device ID for current MMC channel */
host->dev_id = pinmux_decode_periph_id(blob, node);
-
- host->dev_index = fdtdec_get_int(blob, node, "index", host->dev_id);
+ host->dev_index = dev_read_u32_default(dev, "index", host->dev_id);
if (host->dev_index == host->dev_id)
host->dev_index = host->dev_id - PERIPH_ID_SDMMC0;
@@ -168,31 +229,34 @@
printf("DWMMC%d: Can't get the dev index\n", host->dev_index);
return -EINVAL;
}
-
- /* Get the bus width from the device node (Default is 4bit buswidth) */
- host->buswidth = fdtdec_get_int(blob, node, "samsung,bus-width", 4);
+#else
+ if (dev_read_bool(dev, "non-removable"))
+ host->dev_index = 0; /* eMMC */
+ else
+ host->dev_index = 2; /* SD card */
+#endif
- /* Set the base address from the device node */
- base = fdtdec_get_addr(blob, node, "reg");
- if (!base) {
+ host->ioaddr = dev_read_addr_ptr(dev);
+ if (!host->ioaddr) {
printf("DWMMC%d: Can't get base address\n", host->dev_index);
return -EINVAL;
}
- host->ioaddr = (void *)base;
+
+ if (priv->chip->div)
+ div = priv->chip->div;
+ else
+ div = dev_read_u32_default(dev, "samsung,dw-mshc-ciu-div", 0);
- /* Extract the timing info from the node */
- err = fdtdec_get_int_array(blob, node, "samsung,timing", timing, 3);
+ err = dev_read_u32_array(dev, "samsung,dw-mshc-sdr-timing", timing, 2);
if (err) {
- printf("DWMMC%d: Can't get sdr-timings for devider\n",
- host->dev_index);
+ printf("DWMMC%d: Can't get sdr-timings\n", host->dev_index);
return -EINVAL;
}
-
- priv->sdr_timing = (DWMCI_SET_SAMPLE_CLK(timing[0]) |
- DWMCI_SET_DRV_CLK(timing[1]) |
- DWMCI_SET_DIV_RATIO(timing[2]));
+ priv->sdr_timing = DWMCI_SET_SAMPLE_CLK(timing[0]) |
+ DWMCI_SET_DRV_CLK(timing[1]) |
+ DWMCI_SET_DIV_RATIO(div);
- /* sdr_timing didn't assigned anything, use the default value */
+ /* sdr_timing wasn't set, use the default value */
if (!priv->sdr_timing) {
if (host->dev_index == 0)
priv->sdr_timing = DWMMC_MMC0_SDR_TIMING_VAL;
@@ -200,35 +264,82 @@
priv->sdr_timing = DWMMC_MMC2_SDR_TIMING_VAL;
}
- host->fifoth_val = fdtdec_get_int(blob, node, "fifoth_val", 0);
- host->bus_hz = fdtdec_get_int(blob, node, "bus_hz", 0);
- host->div = fdtdec_get_int(blob, node, "div", 0);
+ err = dev_read_u32_array(dev, "samsung,dw-mshc-ddr-timing", timing, 2);
+ if (err) {
+ debug("DWMMC%d: Can't get ddr-timings, using sdr-timings\n",
+ host->dev_index);
+ priv->ddr_timing = priv->sdr_timing;
+ } else {
+ priv->ddr_timing = DWMCI_SET_SAMPLE_CLK(timing[0]) |
+ DWMCI_SET_DRV_CLK(timing[1]) |
+ DWMCI_SET_DIV_RATIO(div);
+ }
+
+ host->buswidth = dev_read_u32_default(dev, "bus-width", 4);
+ host->fifo_depth = dev_read_u32_default(dev, "fifo-depth", 0);
+ host->bus_hz = dev_read_u32_default(dev, "clock-frequency", 0);
return 0;
}
-#ifdef CONFIG_DM_MMC
static int exynos_dwmmc_probe(struct udevice *dev)
{
struct exynos_mmc_plat *plat = dev_get_plat(dev);
struct mmc_uclass_priv *upriv = dev_get_uclass_priv(dev);
struct dwmci_exynos_priv_data *priv = dev_get_priv(dev);
struct dwmci_host *host = &priv->host;
+ unsigned long freq;
int err;
- err = exynos_dwmci_get_config(gd->fdt_blob, dev_of_offset(dev), host,
- priv);
+#ifndef CONFIG_CPU_V7A
+ err = clk_get_by_index(dev, 1, &priv->clk); /* ciu */
if (err)
return err;
- err = do_dwmci_init(host);
- if (err)
+#endif
+
+#ifdef CONFIG_CPU_V7A
+ int flag;
+
+ flag = host->buswidth == 8 ? PINMUX_FLAG_8BIT_MODE : PINMUX_FLAG_NONE;
+ err = exynos_pinmux_config(host->dev_id, flag);
+ if (err) {
+ printf("DWMMC%d not configure\n", host->dev_index);
return err;
+ }
+#endif
+ if (host->bus_hz)
+ freq = host->bus_hz;
+ else
+ freq = DWMMC_MAX_FREQ;
+
+ err = exynos_dwmmc_set_sclk(host, freq);
+ if (err) {
+ printf("DWMMC%d: failed to set clock rate on probe (%d); "
+ "continue anyway\n", host->dev_index, err);
+ }
+
+ host->name = dev->name;
+ host->board_init = exynos_dwmci_board_init;
+ host->caps = MMC_MODE_DDR_52MHz;
+ host->clksel = exynos_dwmci_clksel;
+ host->get_mmc_clk = exynos_dwmci_get_clk;
+
+#ifdef CONFIG_BLK
dwmci_setup_cfg(&plat->cfg, host, DWMMC_MAX_FREQ, DWMMC_MIN_FREQ);
host->mmc = &plat->mmc;
+#else
+ err = add_dwmci(host, DWMMC_MAX_FREQ, DWMMC_MIN_FREQ);
+ if (err) {
+ printf("DWMMC%d registration failed\n", host->dev_index);
+ return err;
+ }
+#endif
+
host->mmc->priv = &priv->host;
- host->priv = dev;
upriv->mmc = host->mmc;
+ host->mmc->dev = dev;
+ host->priv = dev;
return dwmci_probe(dev);
}
@@ -240,9 +351,34 @@
return dwmci_bind(dev, &plat->mmc, &plat->cfg);
}
+static const struct exynos_dwmmc_variant exynos4_drv_data = {
+ .clksel = DWMCI_CLKSEL,
+ .div = EXYNOS4412_FIXED_CIU_CLK_DIV - 1,
+};
+
+static const struct exynos_dwmmc_variant exynos5_drv_data = {
+ .clksel = DWMCI_CLKSEL,
+#ifdef CONFIG_EXYNOS5420
+ .quirks = DWMCI_QUIRK_DISABLE_SMU,
+#endif
+};
+
+static const struct exynos_dwmmc_variant exynos7_smu_drv_data = {
+ .clksel = DWMCI_CLKSEL64,
+ .quirks = DWMCI_QUIRK_DISABLE_SMU,
+};
+
static const struct udevice_id exynos_dwmmc_ids[] = {
- { .compatible = "samsung,exynos4412-dw-mshc" },
- { .compatible = "samsung,exynos-dwmmc" },
+ {
+ .compatible = "samsung,exynos4412-dw-mshc",
+ .data = (ulong)&exynos4_drv_data,
+ }, {
+ .compatible = "samsung,exynos-dwmmc",
+ .data = (ulong)&exynos5_drv_data,
+ }, {
+ .compatible = "samsung,exynos7-dw-mshc-smu",
+ .data = (ulong)&exynos7_smu_drv_data,
+ },
{ }
};
@@ -250,9 +386,10 @@
.name = "exynos_dwmmc",
.id = UCLASS_MMC,
.of_match = exynos_dwmmc_ids,
+ .of_to_plat = exynos_dwmmc_of_to_plat,
.bind = exynos_dwmmc_bind,
- .ops = &dm_dwmci_ops,
.probe = exynos_dwmmc_probe,
+ .ops = &dm_dwmci_ops,
.priv_auto = sizeof(struct dwmci_exynos_priv_data),
.plat_auto = sizeof(struct exynos_mmc_plat),
};
diff --git a/drivers/mmc/ftsdc010_mci.h b/drivers/mmc/ftsdc010_mci.h
index 782d92b..36187cf 100644
--- a/drivers/mmc/ftsdc010_mci.h
+++ b/drivers/mmc/ftsdc010_mci.h
@@ -28,7 +28,6 @@
int dev_index;
int dev_id;
int buswidth;
- u32 fifoth_val;
struct mmc *mmc;
void *priv;
bool fifo_mode;
diff --git a/drivers/mmc/hi6220_dw_mmc.c b/drivers/mmc/hi6220_dw_mmc.c
index c68a915..0302f5c 100644
--- a/drivers/mmc/hi6220_dw_mmc.c
+++ b/drivers/mmc/hi6220_dw_mmc.c
@@ -36,7 +36,7 @@
struct hisi_mmc_data {
unsigned int clock;
bool use_fifo;
- u32 fifoth_val;
+ u32 fifo_depth;
};
static int hi6220_dwmmc_of_to_plat(struct udevice *dev)
@@ -125,7 +125,7 @@
host->mmc = &plat->mmc;
host->fifo_mode = mmc_data->use_fifo;
- host->fifoth_val = mmc_data->fifoth_val;
+ host->fifo_depth = mmc_data->fifo_depth;
host->mmc->priv = &priv->host;
upriv->mmc = host->mmc;
host->mmc->dev = dev;
@@ -158,8 +158,7 @@
static const struct hisi_mmc_data hi3798mv2x_mmc_data = {
.clock = 50000000,
.use_fifo = false,
- // FIFO depth is 256
- .fifoth_val = MSIZE(4) | RX_WMARK(0x7f) | TX_WMARK(0x80),
+ .fifo_depth = 256,
};
static const struct udevice_id hi6220_dwmmc_ids[] = {
diff --git a/drivers/mmc/mmc.c b/drivers/mmc/mmc.c
index cf8277c..9644aa7 100644
--- a/drivers/mmc/mmc.c
+++ b/drivers/mmc/mmc.c
@@ -294,7 +294,7 @@
if (status & MMC_STATUS_MASK) {
#if !defined(CONFIG_SPL_BUILD) || defined(CONFIG_SPL_LIBCOMMON_SUPPORT)
- pr_err("Status Error: 0x%08x\n", status);
+ log_err("Status Error: %#08x\n", status);
#endif
return -ECOMM;
}
@@ -307,7 +307,7 @@
if (timeout_ms <= 0) {
#if !defined(CONFIG_SPL_BUILD) || defined(CONFIG_SPL_LIBCOMMON_SUPPORT)
- pr_err("Timeout waiting card ready\n");
+ log_err("Timeout waiting card ready\n");
#endif
return -ETIMEDOUT;
}
@@ -449,7 +449,7 @@
if (blkcnt > 1) {
if (mmc_send_stop_transmission(mmc, false)) {
#if !defined(CONFIG_SPL_BUILD) || defined(CONFIG_SPL_LIBCOMMON_SUPPORT)
- pr_err("mmc fail to send stop cmd\n");
+ log_err("mmc fail to send stop cmd\n");
#endif
return 0;
}
@@ -500,8 +500,8 @@
if ((start + blkcnt) > block_dev->lba) {
#if !defined(CONFIG_SPL_BUILD) || defined(CONFIG_SPL_LIBCOMMON_SUPPORT)
- pr_err("MMC: block number 0x" LBAF " exceeds max(0x" LBAF ")\n",
- start + blkcnt, block_dev->lba);
+ log_err("MMC: block number 0x" LBAF " exceeds max(0x" LBAF ")\n",
+ start + blkcnt, block_dev->lba);
#endif
return 0;
}
@@ -996,7 +996,7 @@
return 0;
if (!ext_csd) {
- pr_err("No ext_csd found!\n"); /* this should enver happen */
+ log_err("No ext_csd found!\n"); /* this should never happen */
return -ENOTSUPP;
}
@@ -1108,17 +1108,17 @@
return -EINVAL;
if (IS_SD(mmc) || (mmc->version < MMC_VERSION_4_41)) {
- pr_err("eMMC >= 4.4 required for enhanced user data area\n");
+ log_err("eMMC >= 4.4 required for enhanced user data area\n");
return -EMEDIUMTYPE;
}
if (!(mmc->part_support & PART_SUPPORT)) {
- pr_err("Card does not support partitioning\n");
+ log_err("Card does not support partitioning\n");
return -EMEDIUMTYPE;
}
if (!mmc->hc_wp_grp_size) {
- pr_err("Card does not define HC WP group size\n");
+ log_err("Card does not define HC WP group size\n");
return -EMEDIUMTYPE;
}
@@ -1126,8 +1126,7 @@
if (conf->user.enh_size) {
if (conf->user.enh_size % mmc->hc_wp_grp_size ||
conf->user.enh_start % mmc->hc_wp_grp_size) {
- pr_err("User data enhanced area not HC WP group "
- "size aligned\n");
+ log_err("User data enhanced area not HC WP group size aligned\n");
return -EINVAL;
}
part_attrs |= EXT_CSD_ENH_USR;
@@ -1145,8 +1144,8 @@
for (pidx = 0; pidx < 4; pidx++) {
if (conf->gp_part[pidx].size % mmc->hc_wp_grp_size) {
- pr_err("GP%i partition not HC WP group size "
- "aligned\n", pidx+1);
+ log_err("GP%i partition not HC WP group-size aligned\n",
+ pidx + 1);
return -EINVAL;
}
gp_size_mult[pidx] = conf->gp_part[pidx].size / mmc->hc_wp_grp_size;
@@ -1157,7 +1156,7 @@
}
if (part_attrs && ! (mmc->part_support & ENHNCD_SUPPORT)) {
- pr_err("Card does not support enhanced attribute\n");
+ log_err("Card does not support enhanced attribute\n");
return -EMEDIUMTYPE;
}
@@ -1170,8 +1169,8 @@
(ext_csd[EXT_CSD_MAX_ENH_SIZE_MULT+1] << 8) +
ext_csd[EXT_CSD_MAX_ENH_SIZE_MULT];
if (tot_enh_size_mult > max_enh_size_mult) {
- pr_err("Total enhanced size exceeds maximum (%u > %u)\n",
- tot_enh_size_mult, max_enh_size_mult);
+ log_err("Total enhanced size exceeds maximum (%#x > %#x)\n",
+ tot_enh_size_mult, max_enh_size_mult);
return -EMEDIUMTYPE;
}
@@ -1204,7 +1203,7 @@
if (ext_csd[EXT_CSD_PARTITION_SETTING] &
EXT_CSD_PARTITION_SETTING_COMPLETED) {
- pr_err("Card already partitioned\n");
+ log_err("Card already partitioned\n");
return -EPERM;
}
@@ -1875,7 +1874,7 @@
}
}
- pr_err("unable to select a mode\n");
+ log_err("unable to select a mode\n");
return -ENOTSUPP;
}
@@ -2253,7 +2252,7 @@
}
}
- pr_err("unable to select a mode : %d\n", err);
+ log_err("unable to select a mode: %d\n", err);
return -ENOTSUPP;
}
@@ -2921,7 +2920,8 @@
if (err) {
#if !defined(CONFIG_SPL_BUILD) || defined(CONFIG_SPL_LIBCOMMON_SUPPORT)
if (!quiet)
- pr_err("Card did not respond to voltage select! : %d\n", err);
+ log_err("Card did not respond to voltage select! : %d\n",
+ err);
#endif
return -EOPNOTSUPP;
}
@@ -2954,7 +2954,7 @@
| MMC_CAP(MMC_LEGACY) |
MMC_MODE_1BIT);
} else {
- pr_err("bus_mode requested is not supported\n");
+ log_err("bus_mode requested is not supported\n");
return -EINVAL;
}
}
@@ -2974,7 +2974,7 @@
if (no_card) {
mmc->has_init = 0;
#if !defined(CONFIG_SPL_BUILD) || defined(CONFIG_SPL_LIBCOMMON_SUPPORT)
- pr_err("MMC: no card present\n");
+ log_err("MMC: no card present\n");
#endif
return -ENOMEDIUM;
}
@@ -3103,7 +3103,7 @@
uclass_foreach_dev(dev, uc) {
ret = device_probe(dev);
if (ret)
- pr_err("%s - probe failed: %d\n", dev->name, ret);
+ log_err("%s - probe failed: %d\n", dev->name, ret);
}
return 0;
diff --git a/drivers/mmc/nexell_dw_mmc.c b/drivers/mmc/nexell_dw_mmc.c
index 2e1ce54..80df617 100644
--- a/drivers/mmc/nexell_dw_mmc.c
+++ b/drivers/mmc/nexell_dw_mmc.c
@@ -186,10 +186,7 @@
struct dwmci_host *host = &priv->host;
struct udevice *pwr_dev __maybe_unused;
- host->fifoth_val = MSIZE(0x2) |
- RX_WMARK(priv->fifo_size / 2 - 1) |
- TX_WMARK(priv->fifo_size / 2);
-
+ host->fifo_depth = priv->fifo_size;
host->fifo_mode = priv->fifo_mode;
dwmci_setup_cfg(&plat->cfg, host, priv->max_freq, priv->min_freq);
diff --git a/drivers/mmc/rockchip_dw_mmc.c b/drivers/mmc/rockchip_dw_mmc.c
index 549fb80..fb77b04 100644
--- a/drivers/mmc/rockchip_dw_mmc.c
+++ b/drivers/mmc/rockchip_dw_mmc.c
@@ -138,10 +138,7 @@
if (ret < 0)
return ret;
#endif
- host->fifoth_val = MSIZE(0x2) |
- RX_WMARK(priv->fifo_depth / 2 - 1) |
- TX_WMARK(priv->fifo_depth / 2);
-
+ host->fifo_depth = priv->fifo_depth;
host->fifo_mode = priv->fifo_mode;
#if CONFIG_IS_ENABLED(MMC_PWRSEQ)
diff --git a/drivers/mmc/s5p_sdhci.c b/drivers/mmc/s5p_sdhci.c
index 80dbb38..278019f 100644
--- a/drivers/mmc/s5p_sdhci.c
+++ b/drivers/mmc/s5p_sdhci.c
@@ -166,7 +166,7 @@
host->index = dev_id - PERIPH_ID_SDMMC0;
/* Get bus width */
- bus_width = fdtdec_get_int(blob, node, "samsung,bus-width", 0);
+ bus_width = fdtdec_get_int(blob, node, "bus-width", 0);
if (bus_width <= 0) {
debug("MMC: Can't get bus-width\n");
return -EINVAL;
diff --git a/drivers/mmc/sdhci.c b/drivers/mmc/sdhci.c
index 560b7e8..4833b51 100644
--- a/drivers/mmc/sdhci.c
+++ b/drivers/mmc/sdhci.c
@@ -32,8 +32,7 @@
sdhci_writeb(host, mask, SDHCI_SOFTWARE_RESET);
while (sdhci_readb(host, SDHCI_SOFTWARE_RESET) & mask) {
if (timeout == 0) {
- printf("%s: Reset 0x%x never completed.\n",
- __func__, (int)mask);
+ log_warning("Reset %#x never completed\n", mask);
return;
}
timeout--;
@@ -139,8 +138,7 @@
do {
stat = sdhci_readl(host, SDHCI_INT_STATUS);
if (stat & SDHCI_INT_ERROR) {
- pr_debug("%s: Error detected in status(0x%X)!\n",
- __func__, stat);
+ log_debug("Error detected in status(%#x)!\n", stat);
return -EIO;
}
if (!transfer_done && (stat & rdy)) {
@@ -173,7 +171,7 @@
if (timeout-- > 0)
udelay(10);
else {
- printf("%s: Transfer data timeout\n", __func__);
+ log_err("Transfer data timeout\n");
return -ETIMEDOUT;
}
} while (!(stat & SDHCI_INT_DATA_END));
@@ -232,13 +230,13 @@
while (sdhci_readl(host, SDHCI_PRESENT_STATE) & mask) {
if (time >= cmd_timeout) {
- printf("%s: MMC: %d busy ", __func__, mmc_dev);
+ log_warning("mmc%d busy ", mmc_dev);
if (2 * cmd_timeout <= SDHCI_CMD_MAX_TIMEOUT) {
cmd_timeout += cmd_timeout;
- printf("timeout increasing to: %u ms.\n",
- cmd_timeout);
+ log_warning("timeout increasing to: %u ms\n",
+ cmd_timeout);
} else {
- puts("timeout.\n");
+ log_warning("timeout\n");
return -ECOMM;
}
}
@@ -316,8 +314,8 @@
}
if (get_timer(start) >= SDHCI_READ_STATUS_TIMEOUT) {
- printf("%s: Timeout for status update: %08x %08x\n",
- __func__, stat, mask);
+ log_warning("Timeout for status update: %08x %08x\n",
+ stat, mask);
return -ETIMEDOUT;
}
} while ((stat & mask) != mask);
@@ -358,7 +356,7 @@
struct mmc *mmc = mmc_get_mmc_dev(dev);
struct sdhci_host *host = mmc->priv;
- debug("%s\n", __func__);
+ log_debug("sdhci tuning\n");
if (host->ops && host->ops->platform_execute_tuning) {
err = host->ops->platform_execute_tuning(mmc, opcode);
@@ -380,8 +378,7 @@
while (sdhci_readl(host, SDHCI_PRESENT_STATE) &
(SDHCI_CMD_INHIBIT | SDHCI_DATA_INHIBIT)) {
if (timeout == 0) {
- printf("%s: Timeout to wait cmd & data inhibit\n",
- __func__);
+ log_err("Timeout waiting for cmd & data inhibit\n");
return -EBUSY;
}
@@ -397,7 +394,7 @@
if (host->ops && host->ops->set_delay) {
ret = host->ops->set_delay(host);
if (ret) {
- printf("%s: Error while setting tap delay\n", __func__);
+ log_err("Error while setting tap delay\n");
return ret;
}
}
@@ -405,7 +402,7 @@
if (host->ops && host->ops->config_dll) {
ret = host->ops->config_dll(host, clock, false);
if (ret) {
- printf("%s: Error while configuring dll\n", __func__);
+ log_err("Error configuring dll\n");
return ret;
}
}
@@ -456,7 +453,7 @@
if (host->ops && host->ops->config_dll) {
ret = host->ops->config_dll(host, clock, true);
if (ret) {
- printf("%s: Error while configuring dll\n", __func__);
+ log_err("Error while configuring dll\n");
return ret;
}
}
@@ -472,8 +469,7 @@
while (!((clk = sdhci_readw(host, SDHCI_CLOCK_CONTROL))
& SDHCI_CLOCK_INT_STABLE)) {
if (timeout == 0) {
- printf("%s: Internal clock never stabilised.\n",
- __func__);
+ log_err("Internal clock never stabilised.\n");
return -EBUSY;
}
timeout--;
@@ -738,8 +734,7 @@
if (host->quirks & SDHCI_QUIRK_32BIT_DMA_ADDR) {
host->align_buffer = memalign(8, 512 * 1024);
if (!host->align_buffer) {
- printf("%s: Aligned buffer alloc failed!!!\n",
- __func__);
+ log_err("Aligned buffer alloc failed\n");
return -ENOMEM;
}
}
@@ -881,20 +876,18 @@
#else
caps = sdhci_readl(host, SDHCI_CAPABILITIES);
#endif
- debug("%s, caps: 0x%x\n", __func__, caps);
+ log_debug("caps: %#x\n", caps);
#if CONFIG_IS_ENABLED(MMC_SDHCI_SDMA)
if ((caps & SDHCI_CAN_DO_SDMA)) {
host->flags |= USE_SDMA;
} else {
- debug("%s: Your controller doesn't support SDMA!!\n",
- __func__);
+ log_debug("Controller doesn't support SDMA\n");
}
#endif
#if CONFIG_IS_ENABLED(MMC_SDHCI_ADMA)
if (!(caps & SDHCI_CAN_DO_ADMA2)) {
- printf("%s: Your controller doesn't support ADMA!!\n",
- __func__);
+ log_err("Controller doesn't support ADMA\n");
return -EINVAL;
}
if (!host->adma_desc_table) {
@@ -927,7 +920,7 @@
#else
caps_1 = sdhci_readl(host, SDHCI_CAPABILITIES_1);
#endif
- debug("%s, caps_1: 0x%x\n", __func__, caps_1);
+ log_debug("caps_1: %#x\n", caps_1);
host->clk_mul = (caps_1 & SDHCI_CLOCK_MUL_MASK) >>
SDHCI_CLOCK_MUL_SHIFT;
@@ -953,8 +946,7 @@
host->max_clk *= host->clk_mul;
}
if (host->max_clk == 0) {
- printf("%s: Hardware doesn't specify base clock frequency\n",
- __func__);
+ log_err("Hardware doesn't specify base clock frequency\n");
return -EINVAL;
}
if (f_max && (f_max < host->max_clk))
@@ -1047,7 +1039,7 @@
host->mmc = mmc_create(&host->cfg, host);
if (host->mmc == NULL) {
- printf("%s: mmc create fail!\n", __func__);
+ log_err("mmc create fail\n");
return -ENOMEM;
}
diff --git a/drivers/mmc/snps_dw_mmc.c b/drivers/mmc/snps_dw_mmc.c
index 9bdbe50..f30331e 100644
--- a/drivers/mmc/snps_dw_mmc.c
+++ b/drivers/mmc/snps_dw_mmc.c
@@ -81,7 +81,7 @@
host->ioaddr = dev_read_addr_ptr(dev);
/*
- * If fifo-depth is unset don't set fifoth_val - we will try to
+ * If fifo-depth is unset don't set fifo_depth - we will try to
* auto detect it.
*/
ret = dev_read_u32(dev, "fifo-depth", &fifo_depth);
@@ -89,9 +89,7 @@
if (fifo_depth < FIFO_MIN || fifo_depth > FIFO_MAX)
return -EINVAL;
- host->fifoth_val = MSIZE(0x2) |
- RX_WMARK(fifo_depth / 2 - 1) |
- TX_WMARK(fifo_depth / 2);
+ host->fifo_depth = fifo_depth;
}
host->buswidth = dev_read_u32_default(dev, "bus-width", 4);
diff --git a/drivers/mmc/socfpga_dw_mmc.c b/drivers/mmc/socfpga_dw_mmc.c
index f738019..3147d30 100644
--- a/drivers/mmc/socfpga_dw_mmc.c
+++ b/drivers/mmc/socfpga_dw_mmc.c
@@ -134,8 +134,8 @@
* We only have one dwmmc block on gen5 SoCFPGA.
*/
host->dev_index = 0;
- host->fifoth_val = MSIZE(0x2) |
- RX_WMARK(fifo_depth / 2 - 1) | TX_WMARK(fifo_depth / 2);
+
+ host->fifo_depth = fifo_depth;
priv->drvsel = fdtdec_get_uint(gd->fdt_blob, dev_of_offset(dev),
"drvsel", 3);
priv->smplsel = fdtdec_get_uint(gd->fdt_blob, dev_of_offset(dev),
diff --git a/drivers/pinctrl/pinctrl-generic.c b/drivers/pinctrl/pinctrl-generic.c
index 2464acf..81a9327 100644
--- a/drivers/pinctrl/pinctrl-generic.c
+++ b/drivers/pinctrl/pinctrl-generic.c
@@ -22,7 +22,7 @@
if (!ops->get_pins_count || !ops->get_pin_name) {
dev_dbg(dev, "get_pins_count or get_pin_name missing\n");
- return -ENOSYS;
+ return -ENOENT;
}
npins = ops->get_pins_count(dev);
@@ -35,7 +35,7 @@
return selector;
}
- return -ENOSYS;
+ return -ENOENT;
}
/**
@@ -53,7 +53,7 @@
if (!ops->get_groups_count || !ops->get_group_name) {
dev_dbg(dev, "get_groups_count or get_group_name missing\n");
- return -ENOSYS;
+ return -ENOENT;
}
ngroups = ops->get_groups_count(dev);
@@ -66,7 +66,7 @@
return selector;
}
- return -ENOSYS;
+ return -ENOENT;
}
#if CONFIG_IS_ENABLED(PINMUX)
@@ -86,7 +86,7 @@
if (!ops->get_functions_count || !ops->get_function_name) {
dev_dbg(dev,
"get_functions_count or get_function_name missing\n");
- return -ENOSYS;
+ return -ENOENT;
}
nfuncs = ops->get_functions_count(dev);
@@ -99,7 +99,7 @@
return selector;
}
- return -ENOSYS;
+ return -ENOENT;
}
/**
@@ -119,14 +119,14 @@
if (is_group) {
if (!ops->pinmux_group_set) {
dev_dbg(dev, "pinmux_group_set op missing\n");
- return -ENOSYS;
+ return -ENOENT;
}
return ops->pinmux_group_set(dev, selector, func_selector);
} else {
if (!ops->pinmux_set) {
dev_dbg(dev, "pinmux_set op missing\n");
- return -ENOSYS;
+ return -ENOENT;
}
return ops->pinmux_set(dev, selector, func_selector);
}
@@ -162,7 +162,7 @@
if (!ops->pinconf_num_params || !ops->pinconf_params) {
dev_dbg(dev, "pinconf_num_params or pinconf_params missing\n");
- return -ENOSYS;
+ return -ENOENT;
}
p = ops->pinconf_params;
@@ -176,7 +176,7 @@
}
}
- return -ENOSYS;
+ return -ENOENT;
}
/**
@@ -198,7 +198,7 @@
if (is_group) {
if (!ops->pinconf_group_set) {
dev_dbg(dev, "pinconf_group_set op missing\n");
- return -ENOSYS;
+ return -ENOENT;
}
return ops->pinconf_group_set(dev, selector, param,
@@ -206,7 +206,7 @@
} else {
if (!ops->pinconf_set) {
dev_dbg(dev, "pinconf_set op missing\n");
- return -ENOSYS;
+ return -ENOENT;
}
return ops->pinconf_set(dev, selector, param, argument);
}
@@ -215,7 +215,7 @@
static int pinconf_prop_name_to_param(struct udevice *dev,
const char *property, u32 *default_value)
{
- return -ENOSYS;
+ return -ENOENT;
}
static int pinconf_enable_setting(struct udevice *dev, bool is_group,
diff --git a/drivers/power/power_i2c.c b/drivers/power/power_i2c.c
index a871fc4..c2fc1c6 100644
--- a/drivers/power/power_i2c.c
+++ b/drivers/power/power_i2c.c
@@ -33,8 +33,6 @@
p->bus);
return -ENXIO;
}
-#else /* Non DM I2C support - will be removed */
- I2C_SET_BUS(p->bus);
#endif
switch (pmic_i2c_tx_num) {
@@ -93,9 +91,6 @@
return -ENXIO;
}
ret = dm_i2c_read(dev, reg, buf, pmic_i2c_tx_num);
-#else /* Non DM I2C support - will be removed */
- I2C_SET_BUS(p->bus);
- ret = i2c_read(pmic_i2c_addr, reg, 1, buf, pmic_i2c_tx_num);
#endif
if (ret)
return ret;
diff --git a/drivers/spi/soft_spi.c b/drivers/spi/soft_spi.c
index 9bdb4a5..a8ec2f4 100644
--- a/drivers/spi/soft_spi.c
+++ b/drivers/spi/soft_spi.c
@@ -237,6 +237,18 @@
return 0;
}
+static int retrieve_num_chipselects(struct udevice *dev)
+{
+ int chipselects;
+ int ret;
+
+ ret = ofnode_read_u32(dev_ofnode(dev), "num-chipselects", &chipselects);
+ if (ret)
+ return ret;
+
+ return chipselects;
+}
+
static int soft_spi_probe(struct udevice *dev)
{
struct spi_slave *slave = dev_get_parent_priv(dev);
@@ -249,7 +261,15 @@
ret = gpio_request_by_name(dev, "cs-gpios", 0, &plat->cs,
GPIOD_IS_OUT | cs_flags);
- if (ret)
+ /*
+ * If num-chipselects is zero we're ignoring absence of cs-gpios. This
+ * code relies on the fact that `gpio_request_by_name` call above
+ * initiailizes plat->cs to correct value with invalid GPIO even when
+ * there is no cs-gpios node in dts. All other functions which work
+ * with plat->cs verify it via `dm_gpio_is_valid` before using it, so
+ * such value doesn't cause any problems.
+ */
+ if (ret && retrieve_num_chipselects(dev) != 0)
return -EINVAL;
ret = gpio_request_by_name(dev, "gpio-sck", 0, &plat->sclk,
@@ -271,7 +291,7 @@
ret = gpio_request_by_name(dev, "gpio-miso", 0, &plat->miso,
GPIOD_IS_IN);
if (ret)
- ret = gpio_request_by_name(dev, "gpio-miso", 0, &plat->miso,
+ ret = gpio_request_by_name(dev, "miso-gpios", 0, &plat->miso,
GPIOD_IS_IN);
if (ret)
plat->flags |= SPI_MASTER_NO_RX;
diff --git a/drivers/usb/emul/sandbox_flash.c b/drivers/usb/emul/sandbox_flash.c
index 24420e3..b5176bb 100644
--- a/drivers/usb/emul/sandbox_flash.c
+++ b/drivers/usb/emul/sandbox_flash.c
@@ -196,7 +196,7 @@
priv->fd != -1) {
offset = os_lseek(priv->fd, info->seek_block * info->block_size,
OS_SEEK_SET);
- if (offset == (off_t)-1)
+ if (offset < 0)
setup_fail_response(priv);
else
setup_response(priv);
diff --git a/drivers/usb/gadget/atmel_usba_udc.c b/drivers/usb/gadget/atmel_usba_udc.c
index f99553d..a77037a 100644
--- a/drivers/usb/gadget/atmel_usba_udc.c
+++ b/drivers/usb/gadget/atmel_usba_udc.c
@@ -7,16 +7,28 @@
* Bo Shen <voice.shen@atmel.com>
*/
-#include <linux/bitops.h>
-#include <linux/errno.h>
+#include <clk.h>
+#include <dm.h>
+#include <log.h>
+#include <malloc.h>
#include <asm/gpio.h>
#include <asm/hardware.h>
+#include <dm/device_compat.h>
+#include <dm/devres.h>
+#include <linux/bitops.h>
+#include <linux/errno.h>
#include <linux/list.h>
-#include <linux/printk.h>
#include <linux/usb/ch9.h>
#include <linux/usb/gadget.h>
#include <linux/usb/atmel_usba_udc.h>
-#include <malloc.h>
+
+#if CONFIG_IS_ENABLED(DM_USB_GADGET)
+#include <mach/atmel_usba_udc.h>
+
+static int usba_udc_start(struct usb_gadget *gadget,
+ struct usb_gadget_driver *driver);
+static int usba_udc_stop(struct usb_gadget *gadget);
+#endif /* CONFIG_IS_ENABLED(DM_USB_GADGET) */
#include "atmel_usba_udc.h"
@@ -506,10 +518,32 @@
return 0;
}
+static int usba_udc_pullup(struct usb_gadget *gadget, int is_on)
+{
+ struct usba_udc *udc = to_usba_udc(gadget);
+ u32 ctrl;
+
+ ctrl = usba_readl(udc, CTRL);
+
+ if (is_on)
+ ctrl &= ~USBA_DETACH;
+ else
+ ctrl |= USBA_DETACH;
+
+ usba_writel(udc, CTRL, ctrl);
+
+ return 0;
+}
+
static const struct usb_gadget_ops usba_udc_ops = {
.get_frame = usba_udc_get_frame,
.wakeup = usba_udc_wakeup,
.set_selfpowered = usba_udc_set_selfpowered,
+ .pullup = usba_udc_pullup,
+#if CONFIG_IS_ENABLED(DM_USB_GADGET)
+ .udc_start = usba_udc_start,
+ .udc_stop = usba_udc_stop,
+#endif
};
static struct usb_endpoint_descriptor usba_ep0_desc = {
@@ -1153,7 +1187,7 @@
return 0;
}
-static int atmel_usba_start(struct usba_udc *udc)
+static int usba_udc_enable(struct usba_udc *udc)
{
udc->devstatus = 1 << USB_DEVICE_SELF_POWERED;
@@ -1168,7 +1202,7 @@
return 0;
}
-static int atmel_usba_stop(struct usba_udc *udc)
+static int usba_udc_disable(struct usba_udc *udc)
{
udc->gadget.speed = USB_SPEED_UNKNOWN;
reset_all_endpoints(udc);
@@ -1179,6 +1213,47 @@
return 0;
}
+static struct usba_ep *usba_udc_pdata(struct usba_platform_data *pdata,
+ struct usba_udc *udc)
+{
+ struct usba_ep *eps;
+ int i;
+
+ eps = malloc(sizeof(struct usba_ep) * pdata->num_ep);
+ if (!eps) {
+ log_err("failed to alloc eps\n");
+ return NULL;
+ }
+
+ udc->gadget.ep0 = &eps[0].ep;
+
+ INIT_LIST_HEAD(&udc->gadget.ep_list);
+ INIT_LIST_HEAD(&eps[0].ep.ep_list);
+
+ for (i = 0; i < pdata->num_ep; i++) {
+ struct usba_ep *ep = &eps[i];
+
+ ep->ep_regs = udc->regs + USBA_EPT_BASE(i);
+ ep->dma_regs = udc->regs + USBA_DMA_BASE(i);
+ ep->fifo = udc->fifo + USBA_FIFO_BASE(i);
+ ep->ep.ops = &usba_ep_ops;
+ ep->ep.name = pdata->ep[i].name;
+ ep->ep.maxpacket = pdata->ep[i].fifo_size;
+ ep->fifo_size = ep->ep.maxpacket;
+ ep->udc = udc;
+ INIT_LIST_HEAD(&ep->queue);
+ ep->nr_banks = pdata->ep[i].nr_banks;
+ ep->index = pdata->ep[i].index;
+ ep->can_dma = pdata->ep[i].can_dma;
+ ep->can_isoc = pdata->ep[i].can_isoc;
+ if (i)
+ list_add_tail(&ep->ep.ep_list, &udc->gadget.ep_list);
+ };
+
+ return eps;
+}
+
+#if !CONFIG_IS_ENABLED(DM_USB_GADGET)
static struct usba_udc controller = {
.regs = (unsigned *)ATMEL_BASE_UDPHS,
.fifo = (unsigned *)ATMEL_BASE_UDPHS_FIFO,
@@ -1204,22 +1279,22 @@
int ret;
if (!driver || !driver->bind || !driver->setup) {
- printf("bad paramter\n");
+ log_err("bad parameter\n");
return -EINVAL;
}
if (udc->driver) {
- printf("UDC already has a gadget driver\n");
+ log_err("UDC already has a gadget driver\n");
return -EBUSY;
}
- atmel_usba_start(udc);
+ usba_udc_enable(udc);
udc->driver = driver;
ret = driver->bind(&udc->gadget);
if (ret) {
- pr_err("driver->bind() returned %d\n", ret);
+ log_err("driver->bind() returned %d\n", ret);
udc->driver = NULL;
}
@@ -1231,7 +1306,7 @@
struct usba_udc *udc = &controller;
if (!driver || !driver->unbind || !driver->disconnect) {
- pr_err("bad paramter\n");
+ log_err("bad parameter\n");
return -EINVAL;
}
@@ -1239,58 +1314,145 @@
driver->unbind(&udc->gadget);
udc->driver = NULL;
- atmel_usba_stop(udc);
+ usba_udc_disable(udc);
return 0;
}
-static struct usba_ep *usba_udc_pdata(struct usba_platform_data *pdata,
- struct usba_udc *udc)
+int usba_udc_probe(struct usba_platform_data *pdata)
{
- struct usba_ep *eps;
- int i;
+ struct usba_udc *udc;
- eps = malloc(sizeof(struct usba_ep) * pdata->num_ep);
- if (!eps) {
- pr_err("failed to alloc eps\n");
- return NULL;
- }
+ udc = &controller;
- udc->gadget.ep0 = &eps[0].ep;
+ udc->usba_ep = usba_udc_pdata(pdata, udc);
- INIT_LIST_HEAD(&udc->gadget.ep_list);
- INIT_LIST_HEAD(&eps[0].ep.ep_list);
+ return 0;
+}
- for (i = 0; i < pdata->num_ep; i++) {
- struct usba_ep *ep = &eps[i];
+#else /* !CONFIG_IS_ENABLED(DM_USB_GADGET) */
+struct usba_priv_data {
+ struct clk_bulk clks;
+ struct usba_udc udc;
+};
- ep->ep_regs = udc->regs + USBA_EPT_BASE(i);
- ep->dma_regs = udc->regs + USBA_DMA_BASE(i);
- ep->fifo = udc->fifo + USBA_FIFO_BASE(i);
- ep->ep.ops = &usba_ep_ops;
- ep->ep.name = pdata->ep[i].name;
- ep->ep.maxpacket = pdata->ep[i].fifo_size;
- ep->fifo_size = ep->ep.maxpacket;
- ep->udc = udc;
- INIT_LIST_HEAD(&ep->queue);
- ep->nr_banks = pdata->ep[i].nr_banks;
- ep->index = pdata->ep[i].index;
- ep->can_dma = pdata->ep[i].can_dma;
- ep->can_isoc = pdata->ep[i].can_isoc;
- if (i)
- list_add_tail(&ep->ep.ep_list, &udc->gadget.ep_list);
- };
+static int usba_udc_start(struct usb_gadget *gadget,
+ struct usb_gadget_driver *driver)
+{
+ struct usba_udc *udc = to_usba_udc(gadget);
- return eps;
+ usba_udc_enable(udc);
+
+ udc->driver = driver;
+ return 0;
}
-int usba_udc_probe(struct usba_platform_data *pdata)
+static int usba_udc_stop(struct usb_gadget *gadget)
{
- struct usba_udc *udc;
+ struct usba_udc *udc = to_usba_udc(gadget);
- udc = &controller;
+ udc->driver = NULL;
- udc->usba_ep = usba_udc_pdata(pdata, udc);
+ usba_udc_disable(udc);
+ return 0;
+}
+
+static int usba_udc_clk_init(struct udevice *dev, struct clk_bulk *clks)
+{
+ int ret;
+
+ ret = clk_get_bulk(dev, clks);
+ if (ret == -ENOSYS)
+ return 0;
+
+ if (ret)
+ return ret;
+
+ ret = clk_enable_bulk(clks);
+ if (ret) {
+ clk_release_bulk(clks);
+ return ret;
+ }
return 0;
}
+
+static int usba_udc_probe(struct udevice *dev)
+{
+ struct usba_priv_data *priv = dev_get_priv(dev);
+ struct usba_udc *udc = &priv->udc;
+ int ret;
+
+ udc->fifo = (void __iomem *)dev_remap_addr_index(dev, FIFO_IOMEM_ID);
+ if (!udc->fifo)
+ return -EINVAL;
+
+ udc->regs = (void __iomem *)dev_remap_addr_index(dev, CTRL_IOMEM_ID);
+ if (!udc->regs)
+ return -EINVAL;
+
+ ret = usba_udc_clk_init(dev, &priv->clks);
+ if (ret)
+ return ret;
+
+ udc->usba_ep = usba_udc_pdata(&pdata, udc);
+
+ udc->gadget.ops = &usba_udc_ops;
+ udc->gadget.speed = USB_SPEED_HIGH,
+ udc->gadget.is_dualspeed = 1,
+ udc->gadget.name = "atmel_usba_udc",
+
+ ret = usb_add_gadget_udc((struct device *)dev, &udc->gadget);
+ if (ret)
+ goto err;
+
+ return 0;
+err:
+ free(udc->usba_ep);
+
+ clk_release_bulk(&priv->clks);
+
+ return ret;
+}
+
+static int usba_udc_remove(struct udevice *dev)
+{
+ struct usba_priv_data *priv = dev_get_priv(dev);
+
+ usb_del_gadget_udc(&priv->udc.gadget);
+
+ free(priv->udc.usba_ep);
+
+ clk_release_bulk(&priv->clks);
+
+ return dm_scan_fdt_dev(dev);
+}
+
+static int usba_udc_handle_interrupts(struct udevice *dev)
+{
+ struct usba_priv_data *priv = dev_get_priv(dev);
+
+ return usba_udc_irq(&priv->udc);
+}
+
+static const struct usb_gadget_generic_ops usba_udc_gadget_ops = {
+ .handle_interrupts = usba_udc_handle_interrupts,
+};
+
+static const struct udevice_id usba_udc_ids[] = {
+ { .compatible = "atmel,at91sam9rl-udc" },
+ { .compatible = "atmel,at91sam9g45-udc" },
+ { .compatible = "atmel,sama5d3-udc" },
+ {}
+};
+
+U_BOOT_DRIVER(atmel_usba_udc) = {
+ .name = "atmel_usba_udc",
+ .id = UCLASS_USB_GADGET_GENERIC,
+ .of_match = usba_udc_ids,
+ .ops = &usba_udc_gadget_ops,
+ .probe = usba_udc_probe,
+ .remove = usba_udc_remove,
+ .priv_auto = sizeof(struct usba_priv_data),
+};
+#endif /* !CONFIG_IS_ENABLED(DM_USB_GADGET) */
diff --git a/drivers/usb/gadget/atmel_usba_udc.h b/drivers/usb/gadget/atmel_usba_udc.h
index f6cb48c..7f5e98f 100644
--- a/drivers/usb/gadget/atmel_usba_udc.h
+++ b/drivers/usb/gadget/atmel_usba_udc.h
@@ -211,6 +211,9 @@
#define EP0_EPT_SIZE USBA_EPT_SIZE_64
#define EP0_NR_BANKS 1
+#define FIFO_IOMEM_ID 0
+#define CTRL_IOMEM_ID 1
+
#define DBG_ERR 0x0001 /* report all error returns */
#define DBG_HW 0x0002 /* debug hardware initialization */
#define DBG_GADGET 0x0004 /* calls to/from gadget driver */
diff --git a/drivers/usb/gadget/f_sdp.c b/drivers/usb/gadget/f_sdp.c
index 514c097..5d62eb4 100644
--- a/drivers/usb/gadget/f_sdp.c
+++ b/drivers/usb/gadget/f_sdp.c
@@ -842,9 +842,7 @@
struct spl_load_info load;
debug("Found FIT\n");
- load.priv = header;
- spl_set_bl_len(&load, 1);
- load.read = sdp_load_read;
+ spl_load_init(&load, sdp_load_read, header, 1);
spl_load_simple_fit(spl_image, &load, 0,
header);
@@ -855,9 +853,7 @@
valid_container_hdr((void *)header)) {
struct spl_load_info load;
- load.priv = header;
- spl_set_bl_len(&load, 1);
- load.read = sdp_load_read;
+ spl_load_init(&load, sdp_load_read, header, 1);
spl_load_imx_container(spl_image, &load, 0);
return SDP_EXIT;
}
diff --git a/drivers/usb/gadget/udc/udc-uclass.c b/drivers/usb/gadget/udc/udc-uclass.c
index fbe62bb..723d1cd 100644
--- a/drivers/usb/gadget/udc/udc-uclass.c
+++ b/drivers/usb/gadget/udc/udc-uclass.c
@@ -83,7 +83,7 @@
#if CONFIG_IS_ENABLED(DM)
UCLASS_DRIVER(usb_gadget_generic) = {
.id = UCLASS_USB_GADGET_GENERIC,
- .name = "usb",
+ .name = "usb_gadget",
.flags = DM_UC_FLAG_SEQ_ALIAS,
};
#endif
diff --git a/drivers/usb/host/ohci-lpc32xx.c b/drivers/usb/host/ohci-lpc32xx.c
index ed04cae..bf89bf8 100644
--- a/drivers/usb/host/ohci-lpc32xx.c
+++ b/drivers/usb/host/ohci-lpc32xx.c
@@ -94,10 +94,6 @@
static void isp1301_configure(struct udevice *dev)
{
-#if !CONFIG_IS_ENABLED(DM_I2C)
- i2c_set_bus_num(I2C_2);
-#endif
-
/*
* LPC32XX only supports DAT_SE0 USB mode
* This sequence is important
diff --git a/drivers/video/imx/mxc_ipuv3_fb.c b/drivers/video/imx/mxc_ipuv3_fb.c
index 039b220..fdeb3ca 100644
--- a/drivers/video/imx/mxc_ipuv3_fb.c
+++ b/drivers/video/imx/mxc_ipuv3_fb.c
@@ -403,7 +403,6 @@
(uint32_t) fbi->fix.smem_start, fbi->fix.smem_len);
fbi->screen_size = fbi->fix.smem_len;
- gd->fb_base = fbi->fix.smem_start;
/* Clear the screen */
memset((char *)fbi->screen_base, 0, fbi->fix.smem_len);
@@ -633,7 +632,6 @@
mmu_set_region_dcache_behaviour(fb_start, fb_end - fb_start,
DCACHE_WRITEBACK);
video_set_flush_dcache(dev, true);
- gd->fb_base = fb_start;
return 0;
}
diff --git a/drivers/video/mxsfb.c b/drivers/video/mxsfb.c
index 792d631..e72839c 100644
--- a/drivers/video/mxsfb.c
+++ b/drivers/video/mxsfb.c
@@ -335,7 +335,6 @@
mmu_set_region_dcache_behaviour(fb_start, fb_end - fb_start,
DCACHE_WRITEBACK);
video_set_flush_dcache(dev, true);
- gd->fb_base = plat->base;
return ret;
}
diff --git a/drivers/video/video-uclass.c b/drivers/video/video-uclass.c
index a5aa8dd..41bb764 100644
--- a/drivers/video/video-uclass.c
+++ b/drivers/video/video-uclass.c
@@ -145,13 +145,26 @@
*addrp -= CONFIG_VAL(VIDEO_PCI_DEFAULT_FB_SIZE);
gd->video_bottom = *addrp;
- gd->fb_base = *addrp;
debug("Video frame buffers from %lx to %lx\n", gd->video_bottom,
gd->video_top);
return 0;
}
+ulong video_get_fb(void)
+{
+ struct udevice *dev;
+
+ uclass_find_first_device(UCLASS_VIDEO, &dev);
+ if (dev) {
+ const struct video_uc_plat *uc_plat = dev_get_uclass_plat(dev);
+
+ return uc_plat->base;
+ }
+
+ return 0;
+}
+
int video_fill_part(struct udevice *dev, int xstart, int ystart, int xend,
int yend, u32 colour)
{
@@ -210,7 +223,6 @@
return -ENOENT;
gd->video_bottom = ho->fb;
- gd->fb_base = ho->fb;
gd->video_top = ho->fb + ho->size;
debug("%s: Reserving %lx bytes at %08x as per bloblist received\n",
__func__, (unsigned long)ho->size, (u32)ho->fb);
diff --git a/drivers/video/zynqmp/zynqmp_dpsub.c b/drivers/video/zynqmp/zynqmp_dpsub.c
index 1405b29..76abfea 100644
--- a/drivers/video/zynqmp/zynqmp_dpsub.c
+++ b/drivers/video/zynqmp/zynqmp_dpsub.c
@@ -49,7 +49,7 @@
DPDMA_DESCRIPTOR_ADDR_EXT_SRC_ADDR_EXT_SHIFT) |
(upper_32_bits((u64)&cur_desc)));
cur_desc.next_desr = lower_32_bits((u64)&cur_desc);
- cur_desc.src_addr = lower_32_bits((u64)gd->fb_base);
+ cur_desc.src_addr = lower_32_bits((u64)video_get_fb());
}
static void dma_set_descriptor_address(struct udevice *dev)
@@ -2134,7 +2134,6 @@
dev_dbg(dev, "BPP in bits %d, bpix %d\n",
priv->non_live_graphics->bpp, uc_priv->bpix);
- uc_priv->fb = (void *)gd->fb_base;
uc_priv->xsize = vidc_video_timing_modes[priv->video_mode].video_timing.h_active;
uc_priv->ysize = vidc_video_timing_modes[priv->video_mode].video_timing.v_active;
/* Calculated by core but need it for my own setup */
diff --git a/env/common.c b/env/common.c
index 8d47d72..6cba7f1 100644
--- a/env/common.c
+++ b/env/common.c
@@ -401,7 +401,15 @@
* Special use-case: import from default environment
* (and use \0 as a separator)
*/
- flags |= H_NOCLEAR | H_DEFAULT;
+
+ /*
+ * When vars are passed remove variables that are not in
+ * the default environment.
+ */
+ if (!nvars)
+ flags |= H_NOCLEAR;
+
+ flags |= H_DEFAULT;
return himport_r(&env_htab, default_environment,
sizeof(default_environment), '\0',
flags, 0, nvars, vars);
diff --git a/fs/ext4/ext4_common.c b/fs/ext4/ext4_common.c
index 52152a2..76f7102 100644
--- a/fs/ext4/ext4_common.c
+++ b/fs/ext4/ext4_common.c
@@ -2181,13 +2181,18 @@
struct ext2fs_node *diro = node;
int status;
loff_t actread;
+ size_t alloc_size;
if (!diro->inode_read) {
status = ext4fs_read_inode(diro->data, diro->ino, &diro->inode);
if (status == 0)
return NULL;
}
- symlink = zalloc(le32_to_cpu(diro->inode.size) + 1);
+
+ if (__builtin_add_overflow(le32_to_cpu(diro->inode.size), 1, &alloc_size))
+ return NULL;
+
+ symlink = zalloc(alloc_size);
if (!symlink)
return NULL;
@@ -2383,6 +2388,20 @@
fs->inodesz = 128;
fs->gdsize = 32;
} else {
+ int missing = __le32_to_cpu(data->sblock.feature_incompat) &
+ ~(EXT4_FEATURE_INCOMPAT_SUPP |
+ EXT4_FEATURE_INCOMPAT_SUPP_LAZY_RO);
+
+ if (missing) {
+ /*
+ * This code used to be relaxed about feature flags.
+ * We don't stop the mount to avoid breaking existing setups.
+ * But, incompatible features can cause serious read errors.
+ */
+ log_err("fs uses incompatible features: %08x, ignoring\n",
+ missing);
+ }
+
debug("EXT4 features COMPAT: %08x INCOMPAT: %08x RO_COMPAT: %08x\n",
__le32_to_cpu(data->sblock.feature_compatibility),
__le32_to_cpu(data->sblock.feature_incompat),
diff --git a/fs/ext4/ext4_common.h b/fs/ext4/ext4_common.h
index 84500e9..3467520 100644
--- a/fs/ext4/ext4_common.h
+++ b/fs/ext4/ext4_common.h
@@ -24,6 +24,7 @@
#include <ext4fs.h>
#include <malloc.h>
#include <asm/cache.h>
+#include <linux/compat.h>
#include <linux/errno.h>
#if defined(CONFIG_EXT4_WRITE)
#include "ext4_journal.h"
@@ -43,9 +44,7 @@
static inline void *zalloc(size_t size)
{
- void *p = memalign(ARCH_DMA_MINALIGN, size);
- memset(p, 0, size);
- return p;
+ return kzalloc(size, 0);
}
int ext4fs_read_inode(struct ext2_data *data, int ino,
diff --git a/fs/ext4/ext4_write.c b/fs/ext4/ext4_write.c
index a2dfff8..d109ed6 100644
--- a/fs/ext4/ext4_write.c
+++ b/fs/ext4/ext4_write.c
@@ -866,6 +866,7 @@
ALLOC_CACHE_ALIGN_BUFFER(char, filename, 256);
bool store_link_in_inode = false;
memset(filename, 0x00, 256);
+ int missing_feat;
if (type != FILETYPE_REG && type != FILETYPE_SYMLINK)
return -1;
@@ -879,8 +880,15 @@
return -1;
}
- if (le32_to_cpu(fs->sb->feature_ro_compat) & EXT4_FEATURE_RO_COMPAT_METADATA_CSUM) {
- printf("Unsupported feature metadata_csum found, not writing.\n");
+ missing_feat = le32_to_cpu(fs->sb->feature_incompat) & ~EXT4_FEATURE_INCOMPAT_SUPP;
+ if (missing_feat) {
+ log_err("Unsupported features found %08x, not writing.\n", missing_feat);
+ return -1;
+ }
+
+ missing_feat = le32_to_cpu(fs->sb->feature_ro_compat) & ~EXT4_FEATURE_RO_COMPAT_SUPP;
+ if (missing_feat) {
+ log_err("Unsupported RO compat features found %08x, not writing.\n", missing_feat);
return -1;
}
diff --git a/fs/sandbox/sandboxfs.c b/fs/sandbox/sandboxfs.c
index 773b583..76f1a71 100644
--- a/fs/sandbox/sandboxfs.c
+++ b/fs/sandbox/sandboxfs.c
@@ -28,7 +28,7 @@
if (fd < 0)
return fd;
ret = os_lseek(fd, pos, OS_SEEK_SET);
- if (ret == -1) {
+ if (ret < 0) {
os_close(fd);
return ret;
}
@@ -65,14 +65,14 @@
if (fd < 0)
return fd;
ret = os_lseek(fd, pos, OS_SEEK_SET);
- if (ret == -1) {
+ if (ret < 0) {
os_close(fd);
return ret;
}
size = os_write(fd, buffer, towrite);
os_close(fd);
- if (size == -1) {
+ if (size < 0) {
ret = -1;
} else {
ret = 0;
diff --git a/fs/squashfs/sqfs.c b/fs/squashfs/sqfs.c
index 1430e67..b931401 100644
--- a/fs/squashfs/sqfs.c
+++ b/fs/squashfs/sqfs.c
@@ -24,7 +24,12 @@
#include "sqfs_filesystem.h"
#include "sqfs_utils.h"
+#define MAX_SYMLINK_NEST 8
+
static struct squashfs_ctxt ctxt;
+static int symlinknest;
+
+static int sqfs_readdir_nest(struct fs_dir_stream *fs_dirs, struct fs_dirent **dentp);
static int sqfs_disk_read(__u32 block, __u32 nr_blocks, void *buf)
{
@@ -422,8 +427,10 @@
char *resolved, *target;
u32 sz;
+ if (__builtin_add_overflow(get_unaligned_le32(&sym->symlink_size), 1, &sz))
+ return NULL;
+
- sz = get_unaligned_le32(&sym->symlink_size);
- target = malloc(sz + 1);
+ target = malloc(sz);
if (!target)
return NULL;
@@ -431,9 +438,9 @@
* There is no trailling null byte in the symlink's target path, so a
* copy is made and a '\0' is added at its end.
*/
- target[sz] = '\0';
+ target[sz - 1] = '\0';
/* Get target name (relative path) */
- strncpy(target, sym->symlink, sz);
+ strncpy(target, sym->symlink, sz - 1);
/* Relative -> absolute path conversion */
resolved = sqfs_get_abs_path(base_path, target);
@@ -472,6 +479,8 @@
/* Start by root inode */
table = sqfs_find_inode(dirs->inode_table, le32_to_cpu(sblk->inodes),
sblk->inodes, sblk->block_size);
+ if (!table)
+ return -EINVAL;
dir = (struct squashfs_dir_inode *)table;
ldir = (struct squashfs_ldir_inode *)table;
@@ -506,7 +515,7 @@
goto out;
}
- while (!sqfs_readdir(dirsp, &dent)) {
+ while (!sqfs_readdir_nest(dirsp, &dent)) {
ret = strcmp(dent->name, token_list[j]);
if (!ret)
break;
@@ -527,10 +536,17 @@
/* Get reference to inode in the inode table */
table = sqfs_find_inode(dirs->inode_table, new_inode_number,
sblk->inodes, sblk->block_size);
+ if (!table)
+ return -EINVAL;
dir = (struct squashfs_dir_inode *)table;
/* Check for symbolic link and inode type sanity */
if (get_unaligned_le16(&dir->inode_type) == SQFS_SYMLINK_TYPE) {
+ if (++symlinknest == MAX_SYMLINK_NEST) {
+ ret = -ELOOP;
+ goto out;
+ }
+
sym = (struct squashfs_symlink_inode *)table;
/* Get first j + 1 tokens */
path = sqfs_concat_tokens(token_list, j + 1);
@@ -551,8 +567,11 @@
ret = -ENOMEM;
goto out;
}
- /* Concatenate remaining tokens and symlink's target */
- res = malloc(strlen(rem) + strlen(target) + 1);
+ /*
+ * Concatenate remaining tokens and symlink's target.
+ * Allocate enough space for rem, target, '/' and '\0'.
+ */
+ res = malloc(strlen(rem) + strlen(target) + 2);
if (!res) {
ret = -ENOMEM;
goto out;
@@ -878,7 +897,7 @@
return metablks_count;
}
-int sqfs_opendir(const char *filename, struct fs_dir_stream **dirsp)
+static int sqfs_opendir_nest(const char *filename, struct fs_dir_stream **dirsp)
{
unsigned char *inode_table = NULL, *dir_table = NULL;
int j, token_count = 0, ret = 0, metablks_count;
@@ -973,8 +992,20 @@
return ret;
}
+int sqfs_opendir(const char *filename, struct fs_dir_stream **dirsp)
+{
+ symlinknest = 0;
+ return sqfs_opendir_nest(filename, dirsp);
+}
+
int sqfs_readdir(struct fs_dir_stream *fs_dirs, struct fs_dirent **dentp)
{
+ symlinknest = 0;
+ return sqfs_readdir_nest(fs_dirs, dentp);
+}
+
+static int sqfs_readdir_nest(struct fs_dir_stream *fs_dirs, struct fs_dirent **dentp)
+{
struct squashfs_super_block *sblk = ctxt.sblk;
struct squashfs_dir_stream *dirs;
struct squashfs_lreg_inode *lreg;
@@ -1023,6 +1054,8 @@
i_number = dirs->dir_header->inode_number + dirs->entry->inode_offset;
ipos = sqfs_find_inode(dirs->inode_table, i_number, sblk->inodes,
sblk->block_size);
+ if (!ipos)
+ return -SQFS_STOP_READDIR;
base = (struct squashfs_base_inode *)ipos;
@@ -1317,8 +1350,8 @@
return datablk_count;
}
-int sqfs_read(const char *filename, void *buf, loff_t offset, loff_t len,
- loff_t *actread)
+static int sqfs_read_nest(const char *filename, void *buf, loff_t offset,
+ loff_t len, loff_t *actread)
{
char *dir = NULL, *fragment_block, *datablock = NULL;
char *fragment = NULL, *file = NULL, *resolved, *data;
@@ -1348,11 +1381,11 @@
}
/*
- * sqfs_opendir will uncompress inode and directory tables, and will
+ * sqfs_opendir_nest will uncompress inode and directory tables, and will
* return a pointer to the directory that contains the requested file.
*/
sqfs_split_path(&file, &dir, filename);
- ret = sqfs_opendir(dir, &dirsp);
+ ret = sqfs_opendir_nest(dir, &dirsp);
if (ret) {
goto out;
}
@@ -1360,7 +1393,7 @@
dirs = (struct squashfs_dir_stream *)dirsp;
/* For now, only regular files are able to be loaded */
- while (!sqfs_readdir(dirsp, &dent)) {
+ while (!sqfs_readdir_nest(dirsp, &dent)) {
ret = strcmp(dent->name, file);
if (!ret)
break;
@@ -1379,6 +1412,10 @@
i_number = dirs->dir_header->inode_number + dirs->entry->inode_offset;
ipos = sqfs_find_inode(dirs->inode_table, i_number, sblk->inodes,
sblk->block_size);
+ if (!ipos) {
+ ret = -EINVAL;
+ goto out;
+ }
base = (struct squashfs_base_inode *)ipos;
switch (get_unaligned_le16(&base->inode_type)) {
@@ -1409,9 +1446,14 @@
break;
case SQFS_SYMLINK_TYPE:
case SQFS_LSYMLINK_TYPE:
+ if (++symlinknest == MAX_SYMLINK_NEST) {
+ ret = -ELOOP;
+ goto out;
+ }
+
symlink = (struct squashfs_symlink_inode *)ipos;
resolved = sqfs_resolve_symlink(symlink, filename);
- ret = sqfs_read(resolved, buf, offset, len, actread);
+ ret = sqfs_read_nest(resolved, buf, offset, len, actread);
free(resolved);
goto out;
case SQFS_BLKDEV_TYPE:
@@ -1582,7 +1624,14 @@
return ret;
}
-int sqfs_size(const char *filename, loff_t *size)
+int sqfs_read(const char *filename, void *buf, loff_t offset, loff_t len,
+ loff_t *actread)
+{
+ symlinknest = 0;
+ return sqfs_read_nest(filename, buf, offset, len, actread);
+}
+
+static int sqfs_size_nest(const char *filename, loff_t *size)
{
struct squashfs_super_block *sblk = ctxt.sblk;
struct squashfs_symlink_inode *symlink;
@@ -1598,10 +1647,10 @@
sqfs_split_path(&file, &dir, filename);
/*
- * sqfs_opendir will uncompress inode and directory tables, and will
+ * sqfs_opendir_nest will uncompress inode and directory tables, and will
* return a pointer to the directory that contains the requested file.
*/
- ret = sqfs_opendir(dir, &dirsp);
+ ret = sqfs_opendir_nest(dir, &dirsp);
if (ret) {
ret = -EINVAL;
goto free_strings;
@@ -1609,7 +1658,7 @@
dirs = (struct squashfs_dir_stream *)dirsp;
- while (!sqfs_readdir(dirsp, &dent)) {
+ while (!sqfs_readdir_nest(dirsp, &dent)) {
ret = strcmp(dent->name, file);
if (!ret)
break;
@@ -1627,6 +1676,13 @@
i_number = dirs->dir_header->inode_number + dirs->entry->inode_offset;
ipos = sqfs_find_inode(dirs->inode_table, i_number, sblk->inodes,
sblk->block_size);
+
+ if (!ipos) {
+ *size = 0;
+ ret = -EINVAL;
+ goto free_strings;
+ }
+
free(dirs->entry);
dirs->entry = NULL;
@@ -1642,6 +1698,11 @@
break;
case SQFS_SYMLINK_TYPE:
case SQFS_LSYMLINK_TYPE:
+ if (++symlinknest == MAX_SYMLINK_NEST) {
+ *size = 0;
+ return -ELOOP;
+ }
+
symlink = (struct squashfs_symlink_inode *)ipos;
resolved = sqfs_resolve_symlink(symlink, filename);
ret = sqfs_size(resolved, size);
@@ -1681,10 +1742,11 @@
sqfs_split_path(&file, &dir, filename);
/*
- * sqfs_opendir will uncompress inode and directory tables, and will
+ * sqfs_opendir_nest will uncompress inode and directory tables, and will
* return a pointer to the directory that contains the requested file.
*/
- ret = sqfs_opendir(dir, &dirsp);
+ symlinknest = 0;
+ ret = sqfs_opendir_nest(dir, &dirsp);
if (ret) {
ret = -EINVAL;
goto free_strings;
@@ -1692,7 +1754,7 @@
dirs = (struct squashfs_dir_stream *)dirsp;
- while (!sqfs_readdir(dirsp, &dent)) {
+ while (!sqfs_readdir_nest(dirsp, &dent)) {
ret = strcmp(dent->name, file);
if (!ret)
break;
@@ -1709,6 +1771,12 @@
return ret == 0;
}
+int sqfs_size(const char *filename, loff_t *size)
+{
+ symlinknest = 0;
+ return sqfs_size_nest(filename, size);
+}
+
void sqfs_close(void)
{
sqfs_decompressor_cleanup(&ctxt);
diff --git a/fs/squashfs/sqfs_inode.c b/fs/squashfs/sqfs_inode.c
index d25cfb5..bb3ccd3 100644
--- a/fs/squashfs/sqfs_inode.c
+++ b/fs/squashfs/sqfs_inode.c
@@ -78,11 +78,16 @@
case SQFS_SYMLINK_TYPE:
case SQFS_LSYMLINK_TYPE: {
+ int size;
+
struct squashfs_symlink_inode *symlink =
(struct squashfs_symlink_inode *)inode;
- return sizeof(*symlink) +
- get_unaligned_le32(&symlink->symlink_size);
+ if (__builtin_add_overflow(sizeof(*symlink),
+ get_unaligned_le32(&symlink->symlink_size), &size))
+ return -EINVAL;
+
+ return size;
}
case SQFS_BLKDEV_TYPE:
diff --git a/include/alist.h b/include/alist.h
new file mode 100644
index 0000000..586a1ef
--- /dev/null
+++ b/include/alist.h
@@ -0,0 +1,228 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Handles a contiguous list of pointers which be allocated and freed
+ *
+ * Copyright 2023 Google LLC
+ * Written by Simon Glass <sjg@chromium.org>
+ */
+
+#ifndef __ALIST_H
+#define __ALIST_H
+
+#include <stdbool.h>
+#include <linux/bitops.h>
+#include <linux/types.h>
+
+/**
+ * struct alist - object list that can be allocated and freed
+ *
+ * Holds a list of objects, each of the same size. The object is typically a
+ * C struct. The array is alloced in memory can change in size.
+ *
+ * The list rememebers the size of the list, but has a separate count of how
+ * much space is allocated, This allows it increase in size in steps as more
+ * elements are added, which is more efficient that reallocating the list every
+ * time a single item is added
+ *
+ * Two types of access are provided:
+ *
+ * alist_get...(index)
+ * gets an existing element, if its index is less that size
+ *
+ * alist_ensure(index)
+ * address an existing element, or creates a new one if not present
+ *
+ * @data: object data of size `@obj_size * @alloc`. The list can grow as
+ * needed but never shrinks
+ * @obj_size: Size of each object in bytes
+ * @count: number of objects in array
+ * @alloc: allocated length of array, to which @count can grow
+ * @flags: flags for the alist (ALISTF_...)
+ */
+struct alist {
+ void *data;
+ u16 obj_size;
+ u16 count;
+ u16 alloc;
+ u16 flags;
+};
+
+/**
+ * enum alist_flags - Flags for the alist
+ *
+ * @ALIST_FAIL: true if any allocation has failed. Once this has happened, the
+ * alist is dead and cannot grow further
+ */
+enum alist_flags {
+ ALISTF_FAIL = BIT(0),
+};
+
+/**
+ * alist_has() - Check if an index is within the list range
+ *
+ * Checks if index is within the current alist count
+ *
+ * @lst: alist to check
+ * @index: Index to check
+ * Returns: true if value, else false
+ */
+static inline bool alist_has(struct alist *lst, uint index)
+{
+ return index < lst->count;
+}
+
+/**
+ * alist_err() - Check if the alist is still valid
+ *
+ * @lst: List to check
+ * Return: false if OK, true if any previous allocation failed
+ */
+static inline bool alist_err(struct alist *lst)
+{
+ return lst->flags & ALISTF_FAIL;
+}
+
+/**
+ * alist_get_ptr() - Get the value of a pointer
+ *
+ * @lst: alist to check
+ * @index: Index to read from
+ * Returns: pointer, if present, else NULL
+ */
+const void *alist_get_ptr(const struct alist *lst, uint index);
+
+/**
+ * alist_getd() - Get the value of a pointer directly, with no checking
+ *
+ * This must only be called on indexes for which alist_has() returns true
+ *
+ * @lst: alist to check
+ * @index: Index to read from
+ * Returns: pointer value (may be NULL)
+ */
+static inline const void *alist_getd(struct alist *lst, uint index)
+{
+ return lst->data + index * lst->obj_size;
+}
+
+/** get an entry as a constant */
+#define alist_get(_lst, _index, _struct) \
+ ((const _struct *)alist_get_ptr(_lst, _index))
+
+/** get an entry which can be written to */
+#define alist_getw(_lst, _index, _struct) \
+ ((_struct *)alist_get_ptr(_lst, _index))
+
+/**
+ * alist_ensure_ptr() - Ensure an object exists at a given index
+ *
+ * This provides read/write access to an array element. If it does not exist,
+ * it is allocated, reading for the caller to store the object into
+ *
+ * Allocates a object at the given index if needed
+ *
+ * @lst: alist to check
+ * @index: Index to address
+ * Returns: pointer where struct can be read/written, or NULL if out of memory
+ */
+void *alist_ensure_ptr(struct alist *lst, uint index);
+
+/**
+ * alist_ensure() - Address a struct, the correct object type
+ *
+ * Use as:
+ * struct my_struct *ptr = alist_ensure(&lst, 4, struct my_struct);
+ */
+#define alist_ensure(_lst, _index, _struct) \
+ ((_struct *)alist_ensure_ptr(_lst, _index))
+
+/**
+ * alist_add_placeholder() - Add a new item to the end of the list
+ *
+ * @lst: alist to add to
+ * Return: Pointer to the newly added position. Note that this is not inited so
+ * the caller must copy the requested struct to the returned pointer
+ */
+void *alist_add_placeholder(struct alist *lst);
+
+/**
+ * alist_add_ptr() - Ad a new object to the list
+ *
+ * @lst: alist to add to
+ * @obj: Pointer to object to copy in
+ * Returns: pointer to where the object was copied, or NULL if out of memory
+ */
+void *alist_add_ptr(struct alist *lst, void *obj);
+
+/**
+ * alist_expand_by() - Expand a list by the given amount
+ *
+ * @lst: alist to expand
+ * @inc_by: Amount to expand by
+ * Return: true if OK, false if out of memory
+ */
+bool alist_expand_by(struct alist *lst, uint inc_by);
+
+/**
+ * alist_add() - Used to add an object type with the correct type
+ *
+ * Use as:
+ * struct my_struct obj;
+ * struct my_struct *ptr = alist_add(&lst, &obj);
+ */
+#define alist_add(_lst, _obj) \
+ ((typeof(_obj) *)alist_add_ptr(_lst, &(_obj)))
+
+/**
+ * alist_init() - Set up a new object list
+ *
+ * Sets up a list of objects, initially empty
+ *
+ * @lst: alist to set up
+ * @obj_size: Size of each element in bytes
+ * @alloc_size: Number of items to allowed to start, before reallocation is
+ * needed (0 to start with no space)
+ * Return: true if OK, false if out of memory
+ */
+bool alist_init(struct alist *lst, uint obj_size, uint alloc_size);
+
+#define alist_init_struct(_lst, _struct) \
+ alist_init(_lst, sizeof(_struct), 0)
+
+/**
+ * alist_uninit_move_ptr() - Return the allocated contents and uninit the alist
+ *
+ * This returns the alist data to the caller, so that the caller receives data
+ * that it can be sure will hang around. The caller is responsible for freeing
+ * the data.
+ *
+ * If the alist size is 0, this returns NULL
+ *
+ * The alist is uninited as part of this.
+ *
+ * The alist must be inited before this can be called.
+ *
+ * @alist: alist to uninit
+ * @countp: if non-NULL, returns the number of objects in the returned data
+ * (which is @alist->size)
+ * Return: data contents, allocated with malloc(), or NULL if the data could not
+ * be allocated, or the data size is 0
+ */
+void *alist_uninit_move_ptr(struct alist *alist, size_t *countp);
+
+/**
+ * alist_uninit_move() - Typed version of alist_uninit_move_ptr()
+ */
+#define alist_uninit_move(_lst, _countp, _struct) \
+ (_struct *)alist_uninit_move_ptr(_lst, _countp)
+
+/**
+ * alist_uninit() - Free any memory used by an alist
+ *
+ * The alist must be inited before this can be called.
+ *
+ * @alist: alist to uninit
+ */
+void alist_uninit(struct alist *alist);
+
+#endif /* __ALIST_H */
diff --git a/include/asm-generic/global_data.h b/include/asm-generic/global_data.h
index 27aa75e..d6c15e2 100644
--- a/include/asm-generic/global_data.h
+++ b/include/asm-generic/global_data.h
@@ -20,6 +20,7 @@
*/
#ifndef __ASSEMBLY__
+#include <board_f.h>
#include <cyclic.h>
#include <event_internal.h>
#include <fdtdec.h>
@@ -30,6 +31,7 @@
struct acpi_ctx;
struct driver_rt;
+struct upl;
typedef struct global_data gd_t;
@@ -42,38 +44,140 @@
*/
struct bd_info *bd;
/**
+ * @new_gd: pointer to relocated global data
+ */
+ struct global_data *new_gd;
+ /**
+ * @fdt_blob: U-Boot's own device tree, NULL if none
+ */
+ const void *fdt_blob;
+ /**
+ * @cur_serial_dev: current serial device
+ */
+ struct udevice *cur_serial_dev;
+#ifndef CONFIG_SPL_BUILD
+ /**
+ * @jt: jump table
+ *
+ * The jump table contains pointers to exported functions. A pointer to
+ * the jump table is passed to standalone applications.
+ */
+ struct jt_funcs *jt;
+ /**
+ * @boardf: information only used before relocation
+ */
+ struct board_f *boardf;
+#endif
+ /**
+ * @ram_size: RAM size in bytes
+ */
+ phys_size_t ram_size;
+ /**
+ * @ram_top: top address of RAM used by U-Boot
+ */
+ phys_addr_t ram_top;
+ /**
* @flags: global data flags
*
* See &enum gd_flags
*/
unsigned long flags;
/**
+ * @cpu_clk: CPU clock rate in Hz
+ */
+ unsigned long cpu_clk;
+#if CONFIG_IS_ENABLED(ENV_SUPPORT)
+ /**
+ * @env_addr: address of environment structure
+ *
+ * @env_addr contains the address of the structure holding the
+ * environment variables.
+ */
+ unsigned long env_addr;
+#endif /* ENV_SUPPORT */
+ /**
+ * @ram_base: base address of RAM used by U-Boot
+ */
+ unsigned long ram_base;
+ /**
+ * @relocaddr: start address of U-Boot in RAM
+ *
+ * After relocation this field indicates the address to which U-Boot
+ * has been relocated. It can be displayed using the bdinfo command.
+ * Its value is needed to display the source code when debugging with
+ * GDB using the 'add-symbol-file u-boot <relocaddr>' command.
+ */
+ unsigned long relocaddr;
+ /**
+ * @irq_sp: IRQ stack pointer
+ */
+ unsigned long irq_sp;
+ /**
+ * @start_addr_sp: initial stack pointer address
+ */
+ unsigned long start_addr_sp;
+ /**
+ * @reloc_off: relocation offset
+ */
+ unsigned long reloc_off;
+ /**
+ * @bus_clk: platform clock rate in Hz
+ */
+ unsigned int bus_clk;
+ /**
+ * @mem_clk: memory clock rate in Hz
+ */
+ unsigned int mem_clk;
+ /**
+ * @mon_len: monitor length in bytes
+ */
+ unsigned int mon_len;
+ /**
* @baudrate: baud rate of the serial interface
*/
unsigned int baudrate;
+#if CONFIG_IS_ENABLED(ENV_SUPPORT)
/**
- * @cpu_clk: CPU clock rate in Hz
+ * @env_has_init: bit mask indicating environment locations
+ *
+ * &enum env_location defines which bit relates to which location
*/
- unsigned long cpu_clk;
+ unsigned short env_has_init;
/**
- * @bus_clk: platform clock rate in Hz
+ * @env_valid: environment is valid
+ *
+ * See &enum env_valid
*/
- unsigned long bus_clk;
+ unsigned char env_valid;
/**
- * @pci_clk: PCI clock rate in Hz
+ * @env_load_prio: priority of the loaded environment
*/
- /* We cannot bracket this with CONFIG_PCI due to mpc5xxx */
- unsigned long pci_clk;
+ char env_load_prio;
/**
- * @mem_clk: memory clock rate in Hz
+ * @env_buf: buffer for env_get() before reloc
*/
- unsigned long mem_clk;
-#if CONFIG_IS_ENABLED(VIDEO)
+ char env_buf[32];
+#endif /* ENV_SUPPORT */
/**
- * @fb_base: base address of frame buffer memory
+ * @fdt_src: Source of FDT
*/
- unsigned long fb_base;
-#endif
+ enum fdt_source_t fdt_src;
+ /**
+ * @arch: architecture-specific data
+ */
+ struct arch_global_data arch;
+ /**
+ * @dmtag_list: List of DM tags
+ */
+ struct list_head dmtag_list;
+ /**
+ * @timebase_h: high 32 bits of timer
+ */
+ unsigned int timebase_h;
+ /**
+ * @timebase_l: low 32 bits of timer
+ */
+ unsigned int timebase_l;
#if defined(CONFIG_POST)
/**
* @post_log_word: active POST tests
@@ -103,15 +207,6 @@
*/
unsigned long board_type;
#endif
- /**
- * @have_console: console is available
- *
- * A value of 1 indicates that serial_init() was called and a console
- * is available.
- * A value of 0 indicates that console input and output drivers shall
- * not be called.
- */
- unsigned long have_console;
#if CONFIG_IS_ENABLED(PRE_CONSOLE_BUFFER)
/**
* @precon_buf_idx: pre-console buffer index
@@ -125,71 +220,6 @@
*/
long precon_buf_idx;
#endif
- /**
- * @env_addr: address of environment structure
- *
- * @env_addr contains the address of the structure holding the
- * environment variables.
- */
- unsigned long env_addr;
- /**
- * @env_valid: environment is valid
- *
- * See &enum env_valid
- */
- unsigned long env_valid;
- /**
- * @env_has_init: bit mask indicating environment locations
- *
- * &enum env_location defines which bit relates to which location
- */
- unsigned long env_has_init;
- /**
- * @env_load_prio: priority of the loaded environment
- */
- int env_load_prio;
- /**
- * @ram_base: base address of RAM used by U-Boot
- */
- unsigned long ram_base;
- /**
- * @ram_top: top address of RAM used by U-Boot
- */
- phys_addr_t ram_top;
- /**
- * @relocaddr: start address of U-Boot in RAM
- *
- * After relocation this field indicates the address to which U-Boot
- * has been relocated. It can be displayed using the bdinfo command.
- * Its value is needed to display the source code when debugging with
- * GDB using the 'add-symbol-file u-boot <relocaddr>' command.
- */
- unsigned long relocaddr;
- /**
- * @ram_size: RAM size in bytes
- */
- phys_size_t ram_size;
- /**
- * @mon_len: monitor length in bytes
- */
- unsigned long mon_len;
- /**
- * @irq_sp: IRQ stack pointer
- */
- unsigned long irq_sp;
- /**
- * @start_addr_sp: initial stack pointer address
- */
- unsigned long start_addr_sp;
- /**
- * @reloc_off: relocation offset
- */
- unsigned long reloc_off;
- /**
- * @new_gd: pointer to relocated global data
- */
- struct global_data *new_gd;
-
#ifdef CONFIG_DM
/**
* @dm_root: root instance for Driver Model
@@ -234,46 +264,18 @@
*/
struct udevice *timer;
#endif
- /**
- * @fdt_blob: U-Boot's own device tree, NULL if none
- */
- const void *fdt_blob;
- /**
- * @new_fdt: relocated device tree
- */
- void *new_fdt;
- /**
- * @fdt_size: space reserved for relocated device space
- */
- unsigned long fdt_size;
- /**
- * @fdt_src: Source of FDT
- */
- enum fdt_source_t fdt_src;
#if CONFIG_IS_ENABLED(OF_LIVE)
/**
* @of_root: root node of the live tree
*/
struct device_node *of_root;
#endif
-
#if CONFIG_IS_ENABLED(MULTI_DTB_FIT)
/**
* @multi_dtb_fit: pointer to uncompressed multi-dtb FIT image
*/
const void *multi_dtb_fit;
#endif
- /**
- * @jt: jump table
- *
- * The jump table contains pointers to exported functions. A pointer to
- * the jump table is passed to standalone applications.
- */
- struct jt_funcs *jt;
- /**
- * @env_buf: buffer for env_get() before reloc
- */
- char env_buf[32];
#ifdef CONFIG_TRACE
/**
* @trace_buff: trace buffer
@@ -289,18 +291,10 @@
*/
int cur_i2c_bus;
#endif
- /**
- * @timebase_h: high 32 bits of timer
- */
- unsigned int timebase_h;
- /**
- * @timebase_l: low 32 bits of timer
- */
- unsigned int timebase_l;
+#if CONFIG_IS_ENABLED(CMD_BDINFO_EXTRA)
/**
* @malloc_start: start of malloc() region
*/
-#if CONFIG_IS_ENABLED(CMD_BDINFO_EXTRA)
unsigned long malloc_start;
#endif
#if CONFIG_IS_ENABLED(SYS_MALLOC_F)
@@ -309,43 +303,14 @@
*/
unsigned long malloc_base;
/**
- * @malloc_limit: limit address of early malloc()
+ * @malloc_limit: maximum size of early malloc()
*/
- unsigned long malloc_limit;
+ unsigned int malloc_limit;
/**
- * @malloc_ptr: current address of early malloc()
+ * @malloc_ptr: currently used bytes of early malloc()
*/
- unsigned long malloc_ptr;
+ unsigned int malloc_ptr;
#endif
-#ifdef CONFIG_PCI
- /**
- * @hose: PCI hose for early use
- */
- struct pci_controller *hose;
- /**
- * @pci_ram_top: top of region accessible to PCI
- */
- phys_addr_t pci_ram_top;
-#endif
-#ifdef CONFIG_PCI_BOOTDELAY
- /**
- * @pcidelay_done: delay time before scanning of PIC hose expired
- *
- * If CONFIG_PCI_BOOTDELAY=y, pci_hose_scan() waits for the number of
- * milliseconds defined by environment variable pcidelay before
- * scanning. Once this delay has expired the flag @pcidelay_done
- * is set to 1.
- */
- int pcidelay_done;
-#endif
- /**
- * @cur_serial_dev: current serial device
- */
- struct udevice *cur_serial_dev;
- /**
- * @arch: architecture-specific data
- */
- struct arch_global_data arch;
#ifdef CONFIG_CONSOLE_RECORD
/**
* @console_out: output buffer for console recording
@@ -376,13 +341,19 @@
* @bootstage: boot stage information
*/
struct bootstage_data *bootstage;
- /**
- * @new_bootstage: relocated boot stage information
- */
- struct bootstage_data *new_bootstage;
#endif
#ifdef CONFIG_LOG
/**
+ * @log_head: list of logging devices
+ */
+ struct list_head log_head;
+ /**
+ * @log_fmt: bit mask for logging format
+ *
+ * The @log_fmt bit mask selects the fields to be shown in log messages.
+ * &enum log_fmt defines the bits of the bit mask.
+ */
+ /**
* @log_drop_count: number of dropped log messages
*
* This counter is incremented for each log message which can not
@@ -396,60 +367,39 @@
* For logging devices without filters @default_log_level defines the
* logging level, cf. &enum log_level_t.
*/
- int default_log_level;
- /**
- * @log_head: list of logging devices
- */
- struct list_head log_head;
- /**
- * @log_fmt: bit mask for logging format
- *
- * The @log_fmt bit mask selects the fields to be shown in log messages.
- * &enum log_fmt defines the bits of the bit mask.
- */
- int log_fmt;
-
- /**
- * @processing_msg: a log message is being processed
- *
- * This flag is used to suppress the creation of additional messages
- * while another message is being processed.
- */
- bool processing_msg;
+ char default_log_level;
+ char log_fmt;
/**
* @logc_prev: logging category of previous message
*
* This value is used as logging category for continuation messages.
*/
- int logc_prev;
+ unsigned char logc_prev;
/**
* @logl_prev: logging level of the previous message
*
* This value is used as logging level for continuation messages.
*/
- int logl_prev;
+ unsigned char logl_prev;
/**
* @log_cont: Previous log line did not finished wtih \n
*
* This allows for chained log messages on the same line
*/
bool log_cont;
+ /**
+ * @processing_msg: a log message is being processed
+ *
+ * This flag is used to suppress the creation of additional messages
+ * while another message is being processed.
+ */
+ bool processing_msg;
#endif
#if CONFIG_IS_ENABLED(BLOBLIST)
/**
* @bloblist: blob list information
*/
struct bloblist_hdr *bloblist;
- /**
- * @new_bloblist: relocated blob list information
- */
- struct bloblist_hdr *new_bloblist;
-#endif
-#if CONFIG_IS_ENABLED(HANDOFF)
- /**
- * @spl_handoff: SPL hand-off information
- */
- struct spl_handoff *spl_handoff;
#endif
#if defined(CONFIG_TRANSLATION_OFFSET)
/**
@@ -487,10 +437,12 @@
*/
struct hlist_head cyclic_list;
#endif
+#if CONFIG_IS_ENABLED(UPL)
/**
- * @dmtag_list: List of DM tags
+ * @upl: Universal Payload-handoff information
*/
- struct list_head dmtag_list;
+ struct upl *upl;
+#endif
};
#ifndef DO_DEPS_ONLY
static_assert(sizeof(struct global_data) == GD_SIZE);
@@ -578,18 +530,20 @@
#define gd_set_malloc_start(val)
#endif
-#if CONFIG_IS_ENABLED(PCI)
-#define gd_set_pci_ram_top(val) gd->pci_ram_top = val
-#else
-#define gd_set_pci_ram_top(val)
-#endif
-
#if CONFIG_VAL(SYS_MALLOC_F_LEN)
#define gd_malloc_ptr() gd->malloc_ptr
#else
#define gd_malloc_ptr() 0L
#endif
+#if CONFIG_IS_ENABLED(UPL)
+#define gd_upl() gd->upl
+#define gd_set_upl(_val) gd->upl = (_val)
+#else
+#define gd_upl() NULL
+#define gd_set_upl(val)
+#endif
+
/**
* enum gd_flags - global data flags
*
@@ -701,6 +655,16 @@
* @GD_FLG_HUSH_MODERN_PARSER: Use hush 2021 parser.
*/
GD_FLG_HUSH_MODERN_PARSER = 0x2000000,
+ /**
+ * @GD_FLG_UPL: Read/write a Universal Payload (UPL) handoff
+ */
+ GD_FLG_UPL = 0x4000000,
+ /**
+ * @GD_FLG_HAVE_CONSOLE: serial_init() was called and a console
+ * is available. When not set, indicates that console input and output
+ * drivers shall not be called.
+ */
+ GD_FLG_HAVE_CONSOLE = 0x8000000,
};
#endif /* __ASSEMBLY__ */
diff --git a/include/blk.h b/include/blk.h
index 7c7cf7f..1fc9a5b 100644
--- a/include/blk.h
+++ b/include/blk.h
@@ -650,7 +650,7 @@
struct blk_desc *blk_get_devnum_by_uclass_id(enum uclass_id uclass_id, int devnum);
/**
- * blk_get_devnum_by_uclass_id() - Get a block device by type name, and number
+ * blk_get_devnum_by_uclass_idname() - Get block device by type name and number
*
* This looks up the block device type based on @uclass_idname, then calls
* blk_get_devnum_by_uclass_id().
@@ -660,7 +660,7 @@
* Return: point to block device descriptor, or NULL if not found
*/
struct blk_desc *blk_get_devnum_by_uclass_idname(const char *uclass_idname,
- int devnum);
+ int devnum);
/**
* blk_dselect_hwpart() - select a hardware partition
diff --git a/include/board_f.h b/include/board_f.h
new file mode 100644
index 0000000..05aa515
--- /dev/null
+++ b/include/board_f.h
@@ -0,0 +1,35 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright 2024 Google LLC
+ * Written by: Simon Glass <sjg@chromeium.org>
+ */
+
+#ifndef __BOARD_F
+#define __BOARD_F
+
+/**
+ * struct board_f: Information used only before relocation
+ *
+ * This struct is set up in board_init_f() and used to deal with relocation. It
+ * is not available after relocation.
+ */
+struct board_f {
+ /**
+ * @new_fdt: relocated device tree
+ */
+ void *new_fdt;
+ /**
+ * @fdt_size: space reserved for relocated device space
+ */
+ unsigned long fdt_size;
+ /**
+ * @new_bootstage: relocated boot stage information
+ */
+ struct bootstage_data *new_bootstage;
+ /**
+ * @new_bloblist: relocated blob list information
+ */
+ struct bloblist_hdr *new_bloblist;
+};
+
+#endif
diff --git a/include/bootstage.h b/include/bootstage.h
index f4e77b0..5779264 100644
--- a/include/bootstage.h
+++ b/include/bootstage.h
@@ -258,7 +258,7 @@
* relocation, since memory can be overwritten later.
* Return: Always returns 0, to indicate success
*/
-int bootstage_relocate(void);
+int bootstage_relocate(void *to);
/**
* Add a new bootstage record
@@ -395,7 +395,7 @@
* and won't even do that unless CONFIG_SHOW_BOOT_PROGRESS is defined
*/
-static inline int bootstage_relocate(void)
+static inline int bootstage_relocate(void *to)
{
return 0;
}
diff --git a/include/configs/ethernut5.h b/include/configs/ethernut5.h
index 807c696..c327bbb 100644
--- a/include/configs/ethernut5.h
+++ b/include/configs/ethernut5.h
@@ -59,9 +59,6 @@
#define CFG_SYS_I2C_RTC_ADDR 0x51
#endif
-/* I2C */
-#define CFG_SYS_MAX_I2C_BUS 1
-
#define I2C_SOFT_DECLARATIONS
#define GPIO_I2C_SCL AT91_PIO_PORTA, 24
diff --git a/include/configs/gw_ventana.h b/include/configs/gw_ventana.h
index ebc5d03..3e720a6 100644
--- a/include/configs/gw_ventana.h
+++ b/include/configs/gw_ventana.h
@@ -6,55 +6,26 @@
#ifndef __CONFIG_H
#define __CONFIG_H
-/* SPL */
-/* Location in NAND to read U-Boot from */
-
-/* Falcon Mode */
-
-/* Falcon Mode - MMC support: args@1MB kernel@2MB */
-
#include "mx6_common.h"
/* Serial */
#define CFG_MXC_UART_BASE UART2_BASE
-/* NAND */
-
/* MMC Configs */
#define CFG_SYS_FSL_ESDHC_ADDR 0
-/*
- * PCI express
- */
-
-/*
- * PMIC
- */
+/* PMIC */
#define CFG_POWER_PFUZE100_I2C_ADDR 0x08
#define CFG_POWER_LTC3676_I2C_ADDR 0x3c
-/* Various command support */
-
/* USB Configs */
#define CFG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW)
#define CFG_MXC_USB_FLAGS 0
-/* Miscellaneous configurable options */
-
-/* Memory configuration */
-
/* Physical Memory Map */
#define PHYS_SDRAM MMDC0_ARB_BASE_ADDR
#define CFG_SYS_SDRAM_BASE PHYS_SDRAM
#define CFG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR
#define CFG_SYS_INIT_RAM_SIZE IRAM_SIZE
-/*
- * MTD Command for mtdparts
- */
-
-/* Persistent Environment Config */
-
-/* Environment */
-
#endif /* __CONFIG_H */
diff --git a/include/configs/ls1028aqds.h b/include/configs/ls1028aqds.h
index 769ece9..ed93b51 100644
--- a/include/configs/ls1028aqds.h
+++ b/include/configs/ls1028aqds.h
@@ -47,7 +47,6 @@
#endif
/* RTC */
-#define CFG_SYS_RTC_BUS_NUM 1
#define I2C_MUX_CH_RTC 0xB
/* Store environment at top of flash */
diff --git a/include/configs/ls1028ardb.h b/include/configs/ls1028ardb.h
index 0f591e3..d44ce45 100644
--- a/include/configs/ls1028ardb.h
+++ b/include/configs/ls1028ardb.h
@@ -10,8 +10,6 @@
#define COUNTER_FREQUENCY_REAL (get_board_sys_clk() / 4)
-#define CFG_SYS_RTC_BUS_NUM 0
-
/* Store environment at top of flash */
/*
diff --git a/include/configs/ls1046afrwy.h b/include/configs/ls1046afrwy.h
index 5e03a96..21804fc 100644
--- a/include/configs/ls1046afrwy.h
+++ b/include/configs/ls1046afrwy.h
@@ -66,7 +66,6 @@
/* RTC */
#define CFG_SYS_I2C_RTC_ADDR 0x51 /* Channel 0 I2C bus 0*/
-#define CFG_SYS_RTC_BUS_NUM 0
/*
* Environment
diff --git a/include/configs/lx2160aqds.h b/include/configs/lx2160aqds.h
index 3a316e7..5b397e2 100644
--- a/include/configs/lx2160aqds.h
+++ b/include/configs/lx2160aqds.h
@@ -8,9 +8,6 @@
#include "lx2160a_common.h"
-/* RTC */
-#define CFG_SYS_RTC_BUS_NUM 0
-
/* MAC/PHY configuration */
/* Initial environment variables */
diff --git a/include/configs/lx2160ardb.h b/include/configs/lx2160ardb.h
index 6404b35..e700a7b 100644
--- a/include/configs/lx2160ardb.h
+++ b/include/configs/lx2160ardb.h
@@ -8,9 +8,6 @@
#include "lx2160a_common.h"
-/* RTC */
-#define CFG_SYS_RTC_BUS_NUM 4
-
#if defined(CONFIG_FSL_MC_ENET)
#define AQR113C_PHY_ADDR1 0x0
#define AQR113C_PHY_ADDR2 0x08
diff --git a/include/configs/lx2162aqds.h b/include/configs/lx2162aqds.h
index 54d7cea..2d0db47 100644
--- a/include/configs/lx2162aqds.h
+++ b/include/configs/lx2162aqds.h
@@ -10,9 +10,6 @@
/* USB */
-/* RTC */
-#define CFG_SYS_RTC_BUS_NUM 0
-
/* Initial environment variables */
#define CFG_EXTRA_ENV_SETTINGS \
EXTRA_ENV_SETTINGS \
diff --git a/include/configs/m53menlo.h b/include/configs/m53menlo.h
index 9cf46b2..c245cbe 100644
--- a/include/configs/m53menlo.h
+++ b/include/configs/m53menlo.h
@@ -57,8 +57,6 @@
#define CFG_FEC_MXC_PHYADDR 0x0
#endif
-#define CFG_SYS_RTC_BUS_NUM 1 /* I2C2 */
-
/*
* RTC
*/
diff --git a/include/configs/phycore_imx8mm.h b/include/configs/phycore_imx8mm.h
index dd7cfdb..0910ae2 100644
--- a/include/configs/phycore_imx8mm.h
+++ b/include/configs/phycore_imx8mm.h
@@ -29,6 +29,14 @@
"mmcdev=" __stringify(CONFIG_SYS_MMC_ENV_DEV) "\0" \
"mmcpart=1\0" \
"mmcroot=2\0" \
+ "update_offset=0x42\0" \
+ "update_filename=flash.bin\0" \
+ "update_bootimg=" \
+ "mmc dev ${mmcdev} ; " \
+ "if dhcp ${loadaddr} ${update_filepath}/${update_filename} ; then " \
+ "setexpr fw_sz ${filesize} / 0x200 ; " /* SD block size */ \
+ "mmc write ${loadaddr} ${update_offset} ${fw_sz} ; " \
+ "fi\0" \
"mmcautodetect=yes\0" \
"mmcargs=setenv bootargs console=${console} " \
"root=/dev/mmcblk${mmcdev}p${mmcroot} rootwait rw\0" \
diff --git a/include/configs/sniper.h b/include/configs/sniper.h
index 45a3102..d0ae5e1 100644
--- a/include/configs/sniper.h
+++ b/include/configs/sniper.h
@@ -35,20 +35,6 @@
#define CFG_SYS_SDRAM_BASE 0x80000000
/*
- * I2C
- */
-
-#define CFG_I2C_MULTI_BUS
-
-/*
- * Input
- */
-
-/*
- * SPL
- */
-
-/*
* Serial
*/
diff --git a/include/configs/tqma6.h b/include/configs/tqma6.h
index b4a06a7..ceeed17 100644
--- a/include/configs/tqma6.h
+++ b/include/configs/tqma6.h
@@ -26,6 +26,11 @@
#define TQMA6_SPI_FLASH_SECTOR_SIZE SZ_64K
+#if !defined(CONFIG_DM_PMIC)
+#define CFG_POWER_PFUZE100_I2C_ADDR 0x08
+#define TQMA6_PFUZE100_I2C_BUS 2
+#endif
+
/* MMC Configs */
#define CFG_SYS_FSL_ESDHC_ADDR 0
diff --git a/include/configs/tqma6_wru4.h b/include/configs/tqma6_wru4.h
index e06fc7f..5e21463 100644
--- a/include/configs/tqma6_wru4.h
+++ b/include/configs/tqma6_wru4.h
@@ -16,7 +16,6 @@
/* Watchdog */
/* Config on-board RTC */
-#define CFG_SYS_RTC_BUS_NUM 2
#define CFG_SYS_I2C_RTC_ADDR 0x68
/* Turn off RTC square-wave output to save battery */
diff --git a/include/console.h b/include/console.h
index 2617e16..6b6d0f9 100644
--- a/include/console.h
+++ b/include/console.h
@@ -73,7 +73,7 @@
* @str: Place to put string
* @maxlen: Maximum length of @str including nul terminator
* Return: length of string returned, or -ENOSPC if the console buffer was
- * overflowed by the output
+ * overflowed by the output, or -ENOENT if there was nothing to read
*/
int console_record_readline(char *str, int maxlen);
diff --git a/include/dm/test.h b/include/dm/test.h
index 0273741..3cbf2c7 100644
--- a/include/dm/test.h
+++ b/include/dm/test.h
@@ -143,7 +143,7 @@
/* Declare a new driver model test */
#define DM_TEST(_name, _flags) \
- UNIT_TEST(_name, UT_TESTF_DM | UT_TESTF_CONSOLE_REC | (_flags), dm_test)
+ UNIT_TEST(_name, UTF_DM | UTF_CONSOLE | (_flags), dm_test)
/*
* struct sandbox_sdl_plat - Platform data for the SDL video driver
diff --git a/include/dt-bindings/clock/mt7622-clk.h b/include/dt-bindings/clock/mt7622-clk.h
index 76fcaff..cdbcaef 100644
--- a/include/dt-bindings/clock/mt7622-clk.h
+++ b/include/dt-bindings/clock/mt7622-clk.h
@@ -117,46 +117,51 @@
#define CLK_TOP_I2S1_MCK_DIV_PD 104
#define CLK_TOP_I2S2_MCK_DIV_PD 105
#define CLK_TOP_I2S3_MCK_DIV_PD 106
+#define CLK_TOP_A1SYS_HP_DIV_PD 107
+#define CLK_TOP_A2SYS_HP_DIV_PD 108
/* INFRACFG */
-#define CLK_INFRA_DBGCLK_PD 0
-#define CLK_INFRA_TRNG 1
+#define CLK_INFRA_MUX1_SEL 0
+#define CLK_INFRA_DBGCLK_PD 1
#define CLK_INFRA_AUDIO_PD 2
#define CLK_INFRA_IRRX_PD 3
#define CLK_INFRA_APXGPT_PD 4
#define CLK_INFRA_PMIC_PD 5
+#define CLK_INFRA_TRNG 6
/* PERICFG */
-#define CLK_PERI_THERM_PD 0
-#define CLK_PERI_PWM1_PD 1
-#define CLK_PERI_PWM2_PD 2
-#define CLK_PERI_PWM3_PD 3
-#define CLK_PERI_PWM4_PD 4
-#define CLK_PERI_PWM5_PD 5
-#define CLK_PERI_PWM6_PD 6
-#define CLK_PERI_PWM7_PD 7
-#define CLK_PERI_PWM_PD 8
-#define CLK_PERI_AP_DMA_PD 9
-#define CLK_PERI_MSDC30_0_PD 10
-#define CLK_PERI_MSDC30_1_PD 11
-#define CLK_PERI_UART0_PD 12
-#define CLK_PERI_UART1_PD 13
-#define CLK_PERI_UART2_PD 14
-#define CLK_PERI_UART3_PD 15
-#define CLK_PERI_BTIF_PD 16
-#define CLK_PERI_I2C0_PD 17
-#define CLK_PERI_I2C1_PD 18
-#define CLK_PERI_I2C2_PD 19
-#define CLK_PERI_SPI1_PD 20
-#define CLK_PERI_AUXADC_PD 21
-#define CLK_PERI_SPI0_PD 22
-#define CLK_PERI_SNFI_PD 23
-#define CLK_PERI_NFI_PD 24
-#define CLK_PERI_NFIECC_PD 25
-#define CLK_PERI_FLASH_PD 26
-#define CLK_PERI_IRTX_PD 27
+#define CLK_PERIBUS_SEL 0
+#define CLK_PERI_THERM_PD 1
+#define CLK_PERI_PWM1_PD 2
+#define CLK_PERI_PWM2_PD 3
+#define CLK_PERI_PWM3_PD 4
+#define CLK_PERI_PWM4_PD 5
+#define CLK_PERI_PWM5_PD 6
+#define CLK_PERI_PWM6_PD 7
+#define CLK_PERI_PWM7_PD 8
+#define CLK_PERI_PWM_PD 9
+#define CLK_PERI_AP_DMA_PD 10
+#define CLK_PERI_MSDC30_0_PD 11
+#define CLK_PERI_MSDC30_1_PD 12
+#define CLK_PERI_UART0_PD 13
+#define CLK_PERI_UART1_PD 14
+#define CLK_PERI_UART2_PD 15
+#define CLK_PERI_UART3_PD 16
+#define CLK_PERI_UART4_PD 17
+#define CLK_PERI_BTIF_PD 18
+#define CLK_PERI_I2C0_PD 19
+#define CLK_PERI_I2C1_PD 20
+#define CLK_PERI_I2C2_PD 21
+#define CLK_PERI_SPI1_PD 22
+#define CLK_PERI_AUXADC_PD 23
+#define CLK_PERI_SPI0_PD 24
+#define CLK_PERI_SNFI_PD 25
+#define CLK_PERI_NFI_PD 26
+#define CLK_PERI_NFIECC_PD 27
+#define CLK_PERI_FLASH_PD 28
+#define CLK_PERI_IRTX_PD 29
/* APMIXEDSYS */
@@ -169,6 +174,7 @@
#define CLK_APMIXED_AUD2PLL 6
#define CLK_APMIXED_TRGPLL 7
#define CLK_APMIXED_SGMIPLL 8
+#define CLK_APMIXED_MAIN_CORE_EN 9
/* AUDIOSYS */
@@ -206,7 +212,7 @@
#define CLK_AUDIO_DLMCH 31
#define CLK_AUDIO_ARB1 32
#define CLK_AUDIO_AWB 33
-#define CLK_AUDIO_AWB3 34
+#define CLK_AUDIO_AWB2 34
#define CLK_AUDIO_DAI 35
#define CLK_AUDIO_MOD 36
#define CLK_AUDIO_ASRCI3 37
diff --git a/include/dt-bindings/clock/mt7623-clk.h b/include/dt-bindings/clock/mt7623-clk.h
index 71ced15..0caeb65 100644
--- a/include/dt-bindings/clock/mt7623-clk.h
+++ b/include/dt-bindings/clock/mt7623-clk.h
@@ -7,407 +7,477 @@
#define _DT_BINDINGS_CLK_MT2701_H
/* TOPCKGEN */
-#define CLK_TOP_FCLKS_OFF 0
+#define CLK_TOP_SYSPLL 1
+#define CLK_TOP_SYSPLL_D2 2
+#define CLK_TOP_SYSPLL_D3 3
+#define CLK_TOP_SYSPLL_D5 4
+#define CLK_TOP_SYSPLL_D7 5
+#define CLK_TOP_SYSPLL1_D2 6
+#define CLK_TOP_SYSPLL1_D4 7
+#define CLK_TOP_SYSPLL1_D8 8
+#define CLK_TOP_SYSPLL1_D16 9
+#define CLK_TOP_SYSPLL2_D2 10
+#define CLK_TOP_SYSPLL2_D4 11
+#define CLK_TOP_SYSPLL2_D8 12
+#define CLK_TOP_SYSPLL3_D2 13
+#define CLK_TOP_SYSPLL3_D4 14
+#define CLK_TOP_SYSPLL4_D2 15
+#define CLK_TOP_SYSPLL4_D4 16
+#define CLK_TOP_UNIVPLL 17
+#define CLK_TOP_UNIVPLL_D2 18
+#define CLK_TOP_UNIVPLL_D3 19
+#define CLK_TOP_UNIVPLL_D5 20
+#define CLK_TOP_UNIVPLL_D7 21
+#define CLK_TOP_UNIVPLL_D26 22
+#define CLK_TOP_UNIVPLL_D52 23
+#define CLK_TOP_UNIVPLL_D108 24
+#define CLK_TOP_USB_PHY48M 25
+#define CLK_TOP_UNIVPLL1_D2 26
+#define CLK_TOP_UNIVPLL1_D4 27
+#define CLK_TOP_UNIVPLL1_D8 28
+#define CLK_TOP_UNIVPLL2_D2 29
+#define CLK_TOP_UNIVPLL2_D4 30
+#define CLK_TOP_UNIVPLL2_D8 31
+#define CLK_TOP_UNIVPLL2_D16 32
+#define CLK_TOP_UNIVPLL2_D32 33
+#define CLK_TOP_UNIVPLL3_D2 34
+#define CLK_TOP_UNIVPLL3_D4 35
+#define CLK_TOP_UNIVPLL3_D8 36
+#define CLK_TOP_MSDCPLL 37
+#define CLK_TOP_MSDCPLL_D2 38
+#define CLK_TOP_MSDCPLL_D4 39
+#define CLK_TOP_MSDCPLL_D8 40
+#define CLK_TOP_MMPLL 41
+#define CLK_TOP_MMPLL_D2 42
+#define CLK_TOP_DMPLL 43
+#define CLK_TOP_DMPLL_D2 44
+#define CLK_TOP_DMPLL_D4 45
+#define CLK_TOP_DMPLL_X2 46
+#define CLK_TOP_TVDPLL 47
+#define CLK_TOP_TVDPLL_D2 48
+#define CLK_TOP_TVDPLL_D4 49
+#define CLK_TOP_TVD2PLL 50
+#define CLK_TOP_TVD2PLL_D2 51
+#define CLK_TOP_HADDS2PLL_98M 52
+#define CLK_TOP_HADDS2PLL_294M 53
+#define CLK_TOP_HADDS2_FB 54
+#define CLK_TOP_MIPIPLL_D2 55
+#define CLK_TOP_MIPIPLL_D4 56
+#define CLK_TOP_HDMIPLL 57
+#define CLK_TOP_HDMIPLL_D2 58
+#define CLK_TOP_HDMIPLL_D3 59
+#define CLK_TOP_HDMI_SCL_RX 60
+#define CLK_TOP_HDMI_0_PIX340M 61
+#define CLK_TOP_HDMI_0_DEEP340M 62
+#define CLK_TOP_HDMI_0_PLL340M 63
+#define CLK_TOP_AUD1PLL_98M 64
+#define CLK_TOP_AUD2PLL_90M 65
+#define CLK_TOP_AUDPLL 66
+#define CLK_TOP_AUDPLL_D4 67
+#define CLK_TOP_AUDPLL_D8 68
+#define CLK_TOP_AUDPLL_D16 69
+#define CLK_TOP_AUDPLL_D24 70
+#define CLK_TOP_ETHPLL_500M 71
+#define CLK_TOP_VDECPLL 72
+#define CLK_TOP_VENCPLL 73
+#define CLK_TOP_MIPIPLL 74
+#define CLK_TOP_ARMPLL_1P3G 75
-#define CLK_TOP_DPI 0
-#define CLK_TOP_DMPLL 1
-#define CLK_TOP_VENCPLL 2
-#define CLK_TOP_HDMI_0_PIX340M 3
-#define CLK_TOP_HDMI_0_DEEP340M 4
-#define CLK_TOP_HDMI_0_PLL340M 5
-#define CLK_TOP_HADDS2_FB 6
-#define CLK_TOP_WBG_DIG_416M 7
-#define CLK_TOP_DSI0_LNTC_DSI 8
-#define CLK_TOP_HDMI_SCL_RX 9
-#define CLK_TOP_32K_EXTERNAL 10
-#define CLK_TOP_HDMITX_CLKDIG_CTS 11
-#define CLK_TOP_AUD_EXT1 12
-#define CLK_TOP_AUD_EXT2 13
-#define CLK_TOP_NFI1X_PAD 14
+#define CLK_TOP_MM_SEL 76
+#define CLK_TOP_DDRPHYCFG_SEL 77
+#define CLK_TOP_MEM_SEL 78
+#define CLK_TOP_AXI_SEL 79
+#define CLK_TOP_CAMTG_SEL 80
+#define CLK_TOP_MFG_SEL 81
+#define CLK_TOP_VDEC_SEL 82
+#define CLK_TOP_PWM_SEL 83
+#define CLK_TOP_MSDC30_0_SEL 84
+#define CLK_TOP_USB20_SEL 85
+#define CLK_TOP_SPI0_SEL 86
+#define CLK_TOP_UART_SEL 87
+#define CLK_TOP_AUDINTBUS_SEL 88
+#define CLK_TOP_AUDIO_SEL 89
+#define CLK_TOP_MSDC30_2_SEL 90
+#define CLK_TOP_MSDC30_1_SEL 91
+#define CLK_TOP_DPI1_SEL 92
+#define CLK_TOP_DPI0_SEL 93
+#define CLK_TOP_SCP_SEL 94
+#define CLK_TOP_PMICSPI_SEL 95
+#define CLK_TOP_APLL_SEL 96
+#define CLK_TOP_HDMI_SEL 97
+#define CLK_TOP_TVE_SEL 98
+#define CLK_TOP_EMMC_HCLK_SEL 99
+#define CLK_TOP_NFI2X_SEL 100
+#define CLK_TOP_RTC_SEL 101
+#define CLK_TOP_OSD_SEL 102
+#define CLK_TOP_NR_SEL 103
+#define CLK_TOP_DI_SEL 104
+#define CLK_TOP_FLASH_SEL 105
+#define CLK_TOP_ASM_M_SEL 106
+#define CLK_TOP_ASM_I_SEL 107
+#define CLK_TOP_INTDIR_SEL 108
+#define CLK_TOP_HDMIRX_BIST_SEL 109
+#define CLK_TOP_ETHIF_SEL 110
+#define CLK_TOP_MS_CARD_SEL 111
+#define CLK_TOP_ASM_H_SEL 112
+#define CLK_TOP_SPI1_SEL 113
+#define CLK_TOP_CMSYS_SEL 114
+#define CLK_TOP_MSDC30_3_SEL 115
+#define CLK_TOP_HDMIRX26_24_SEL 116
+#define CLK_TOP_AUD2DVD_SEL 117
+#define CLK_TOP_8BDAC_SEL 118
+#define CLK_TOP_SPI2_SEL 119
+#define CLK_TOP_AUD_MUX1_SEL 120
+#define CLK_TOP_AUD_MUX2_SEL 121
+#define CLK_TOP_AUDPLL_MUX_SEL 122
+#define CLK_TOP_AUD_K1_SRC_SEL 123
+#define CLK_TOP_AUD_K2_SRC_SEL 124
+#define CLK_TOP_AUD_K3_SRC_SEL 125
+#define CLK_TOP_AUD_K4_SRC_SEL 126
+#define CLK_TOP_AUD_K5_SRC_SEL 127
+#define CLK_TOP_AUD_K6_SRC_SEL 128
+#define CLK_TOP_PADMCLK_SEL 129
+#define CLK_TOP_AUD_EXTCK1_DIV 130
+#define CLK_TOP_AUD_EXTCK2_DIV 131
+#define CLK_TOP_AUD_MUX1_DIV 132
+#define CLK_TOP_AUD_MUX2_DIV 133
+#define CLK_TOP_AUD_K1_SRC_DIV 134
+#define CLK_TOP_AUD_K2_SRC_DIV 135
+#define CLK_TOP_AUD_K3_SRC_DIV 136
+#define CLK_TOP_AUD_K4_SRC_DIV 137
+#define CLK_TOP_AUD_K5_SRC_DIV 138
+#define CLK_TOP_AUD_K6_SRC_DIV 139
+#define CLK_TOP_AUD_I2S1_MCLK 140
+#define CLK_TOP_AUD_I2S2_MCLK 141
+#define CLK_TOP_AUD_I2S3_MCLK 142
+#define CLK_TOP_AUD_I2S4_MCLK 143
+#define CLK_TOP_AUD_I2S5_MCLK 144
+#define CLK_TOP_AUD_I2S6_MCLK 145
+#define CLK_TOP_AUD_48K_TIMING 146
+#define CLK_TOP_AUD_44K_TIMING 147
-#define CLK_TOP_SYSPLL 15
-#define CLK_TOP_SYSPLL_D2 16
-#define CLK_TOP_SYSPLL_D3 17
-#define CLK_TOP_SYSPLL_D5 18
-#define CLK_TOP_SYSPLL_D7 19
-#define CLK_TOP_SYSPLL1_D2 20
-#define CLK_TOP_SYSPLL1_D4 21
-#define CLK_TOP_SYSPLL1_D8 22
-#define CLK_TOP_SYSPLL1_D16 23
-#define CLK_TOP_SYSPLL2_D2 24
-#define CLK_TOP_SYSPLL2_D4 25
-#define CLK_TOP_SYSPLL2_D8 26
-#define CLK_TOP_SYSPLL3_D2 27
-#define CLK_TOP_SYSPLL3_D4 28
-#define CLK_TOP_SYSPLL4_D2 29
-#define CLK_TOP_SYSPLL4_D4 30
-#define CLK_TOP_UNIVPLL 31
-#define CLK_TOP_UNIVPLL_D2 32
-#define CLK_TOP_UNIVPLL_D3 33
-#define CLK_TOP_UNIVPLL_D5 34
-#define CLK_TOP_UNIVPLL_D7 35
-#define CLK_TOP_UNIVPLL_D26 36
-#define CLK_TOP_UNIVPLL_D52 37
-#define CLK_TOP_UNIVPLL_D108 38
-#define CLK_TOP_USB_PHY48M 39
-#define CLK_TOP_UNIVPLL1_D2 40
-#define CLK_TOP_UNIVPLL1_D4 41
-#define CLK_TOP_UNIVPLL1_D8 42
-#define CLK_TOP_UNIVPLL2_D2 43
-#define CLK_TOP_UNIVPLL2_D4 44
-#define CLK_TOP_UNIVPLL2_D8 45
-#define CLK_TOP_UNIVPLL2_D16 46
-#define CLK_TOP_UNIVPLL2_D32 47
-#define CLK_TOP_UNIVPLL3_D2 48
-#define CLK_TOP_UNIVPLL3_D4 49
-#define CLK_TOP_UNIVPLL3_D8 50
-#define CLK_TOP_MSDCPLL 51
-#define CLK_TOP_MSDCPLL_D2 52
-#define CLK_TOP_MSDCPLL_D4 53
-#define CLK_TOP_MSDCPLL_D8 54
-#define CLK_TOP_MMPLL 55
-#define CLK_TOP_MMPLL_D2 56
-#define CLK_TOP_DMPLL_D2 57
-#define CLK_TOP_DMPLL_D4 58
-#define CLK_TOP_DMPLL_X2 59
-#define CLK_TOP_TVDPLL 60
-#define CLK_TOP_TVDPLL_D2 61
-#define CLK_TOP_TVDPLL_D4 62
-#define CLK_TOP_VDECPLL 63
-#define CLK_TOP_TVD2PLL 64
-#define CLK_TOP_TVD2PLL_D2 65
-#define CLK_TOP_MIPIPLL 66
-#define CLK_TOP_MIPIPLL_D2 67
-#define CLK_TOP_MIPIPLL_D4 68
-#define CLK_TOP_HDMIPLL 69
-#define CLK_TOP_HDMIPLL_D2 70
-#define CLK_TOP_HDMIPLL_D3 71
-#define CLK_TOP_ARMPLL_1P3G 72
-#define CLK_TOP_AUDPLL 73
-#define CLK_TOP_AUDPLL_D4 74
-#define CLK_TOP_AUDPLL_D8 75
-#define CLK_TOP_AUDPLL_D16 76
-#define CLK_TOP_AUDPLL_D24 77
-#define CLK_TOP_AUD1PLL_98M 78
-#define CLK_TOP_AUD2PLL_90M 79
-#define CLK_TOP_HADDS2PLL_98M 80
-#define CLK_TOP_HADDS2PLL_294M 81
-#define CLK_TOP_ETHPLL_500M 82
-#define CLK_TOP_CLK26M_D8 83
-#define CLK_TOP_32K_INTERNAL 84
-#define CLK_TOP_AXISEL_D4 85
-#define CLK_TOP_8BDAC 86
-
-#define CLK_TOP_AXI_SEL 87
-#define CLK_TOP_MEM_SEL 88
-#define CLK_TOP_DDRPHYCFG_SEL 89
-#define CLK_TOP_MM_SEL 90
-#define CLK_TOP_PWM_SEL 91
-#define CLK_TOP_VDEC_SEL 92
-#define CLK_TOP_MFG_SEL 93
-#define CLK_TOP_CAMTG_SEL 94
-#define CLK_TOP_UART_SEL 95
-#define CLK_TOP_SPI0_SEL 96
-#define CLK_TOP_USB20_SEL 97
-#define CLK_TOP_MSDC30_0_SEL 98
-#define CLK_TOP_MSDC30_1_SEL 99
-#define CLK_TOP_MSDC30_2_SEL 100
-#define CLK_TOP_AUDIO_SEL 101
-#define CLK_TOP_AUDINTBUS_SEL 102
-#define CLK_TOP_PMICSPI_SEL 103
-#define CLK_TOP_SCP_SEL 104
-#define CLK_TOP_DPI0_SEL 105
-#define CLK_TOP_DPI1_SEL 106
-#define CLK_TOP_TVE_SEL 107
-#define CLK_TOP_HDMI_SEL 108
-#define CLK_TOP_APLL_SEL 109
-#define CLK_TOP_RTC_SEL 110
-#define CLK_TOP_NFI2X_SEL 111
-#define CLK_TOP_EMMC_HCLK_SEL 112
-#define CLK_TOP_FLASH_SEL 113
-#define CLK_TOP_DI_SEL 114
-#define CLK_TOP_NR_SEL 115
-#define CLK_TOP_OSD_SEL 116
-#define CLK_TOP_HDMIRX_BIST_SEL 117
-#define CLK_TOP_INTDIR_SEL 118
-#define CLK_TOP_ASM_I_SEL 119
-#define CLK_TOP_ASM_M_SEL 120
-#define CLK_TOP_ASM_H_SEL 121
-#define CLK_TOP_MS_CARD_SEL 122
-#define CLK_TOP_ETHIF_SEL 123
-#define CLK_TOP_HDMIRX26_24_SEL 124
-#define CLK_TOP_MSDC30_3_SEL 125
-#define CLK_TOP_CMSYS_SEL 126
-#define CLK_TOP_SPI1_SEL 127
-#define CLK_TOP_SPI2_SEL 128
-#define CLK_TOP_8BDAC_SEL 129
-#define CLK_TOP_AUD2DVD_SEL 130
-#define CLK_TOP_PADMCLK_SEL 131
-#define CLK_TOP_AUD_MUX1_SEL 132
-#define CLK_TOP_AUD_MUX2_SEL 133
-#define CLK_TOP_AUDPLL_MUX_SEL 134
-#define CLK_TOP_AUD_K1_SRC_SEL 135
-#define CLK_TOP_AUD_K2_SRC_SEL 136
-#define CLK_TOP_AUD_K3_SRC_SEL 137
-#define CLK_TOP_AUD_K4_SRC_SEL 138
-#define CLK_TOP_AUD_K5_SRC_SEL 139
-#define CLK_TOP_AUD_K6_SRC_SEL 140
-
-#define CLK_TOP_AUD_EXTCK1_DIV 141
-#define CLK_TOP_AUD_EXTCK2_DIV 142
-#define CLK_TOP_AUD_MUX1_DIV 143
-#define CLK_TOP_AUD_MUX2_DIV 144
-#define CLK_TOP_AUD_K1_SRC_DIV 145
-#define CLK_TOP_AUD_K2_SRC_DIV 146
-#define CLK_TOP_AUD_K3_SRC_DIV 147
-#define CLK_TOP_AUD_K4_SRC_DIV 148
-#define CLK_TOP_AUD_K5_SRC_DIV 149
-#define CLK_TOP_AUD_K6_SRC_DIV 150
-#define CLK_TOP_AUD_48K_TIMING 151
-#define CLK_TOP_AUD_44K_TIMING 152
-#define CLK_TOP_AUD_I2S1_MCLK 153
-#define CLK_TOP_AUD_I2S2_MCLK 154
-#define CLK_TOP_AUD_I2S3_MCLK 155
-#define CLK_TOP_AUD_I2S4_MCLK 156
-#define CLK_TOP_AUD_I2S5_MCLK 157
-#define CLK_TOP_AUD_I2S6_MCLK 158
+#define CLK_TOP_32K_INTERNAL 148
+#define CLK_TOP_32K_EXTERNAL 149
+#define CLK_TOP_CLK26M_D8 150
+#define CLK_TOP_8BDAC 151
+#define CLK_TOP_WBG_DIG_416M 152
+#define CLK_TOP_DPI 153
+#define CLK_TOP_DSI0_LNTC_DSI 154
+#define CLK_TOP_AUD_EXT1 155
+#define CLK_TOP_AUD_EXT2 156
+#define CLK_TOP_NFI1X_PAD 157
+#define CLK_TOP_AXISEL_D4 158
#define CLK_TOP_NR 159
/* APMIXEDSYS */
-#define CLK_APMIXED_ARMPLL 0
-#define CLK_APMIXED_MAINPLL 1
-#define CLK_APMIXED_UNIVPLL 2
-#define CLK_APMIXED_MMPLL 3
-#define CLK_APMIXED_MSDCPLL 4
-#define CLK_APMIXED_TVDPLL 5
-#define CLK_APMIXED_AUD1PLL 6
-#define CLK_APMIXED_TRGPLL 7
-#define CLK_APMIXED_ETHPLL 8
-#define CLK_APMIXED_VDECPLL 9
-#define CLK_APMIXED_HADDS2PLL 10
-#define CLK_APMIXED_AUD2PLL 11
-#define CLK_APMIXED_TVD2PLL 12
-#define CLK_APMIXED_NR 13
+
+#define CLK_APMIXED_ARMPLL 1
+#define CLK_APMIXED_MAINPLL 2
+#define CLK_APMIXED_UNIVPLL 3
+#define CLK_APMIXED_MMPLL 4
+#define CLK_APMIXED_MSDCPLL 5
+#define CLK_APMIXED_TVDPLL 6
+#define CLK_APMIXED_AUD1PLL 7
+#define CLK_APMIXED_TRGPLL 8
+#define CLK_APMIXED_ETHPLL 9
+#define CLK_APMIXED_VDECPLL 10
+#define CLK_APMIXED_HADDS2PLL 11
+#define CLK_APMIXED_AUD2PLL 12
+#define CLK_APMIXED_TVD2PLL 13
+#define CLK_APMIXED_HDMI_REF 14
+#define CLK_APMIXED_NR 15
+
+/* DDRPHY */
+
+#define CLK_DDRPHY_VENCPLL 1
+#define CLK_DDRPHY_NR 2
/* INFRACFG */
-#define CLK_INFRA_DBG 0
-#define CLK_INFRA_SMI 1
-#define CLK_INFRA_QAXI_CM4 2
-#define CLK_INFRA_AUD_SPLIN_B 3
-#define CLK_INFRA_AUDIO 4
-#define CLK_INFRA_EFUSE 5
-#define CLK_INFRA_L2C_SRAM 6
-#define CLK_INFRA_M4U 7
-#define CLK_INFRA_CONNMCU 8
-#define CLK_INFRA_TRNG 9
-#define CLK_INFRA_RAMBUFIF 10
-#define CLK_INFRA_CPUM 11
-#define CLK_INFRA_KP 12
-#define CLK_INFRA_CEC 13
-#define CLK_INFRA_IRRX 14
-#define CLK_INFRA_PMICSPI 15
-#define CLK_INFRA_PMICWRAP 16
-#define CLK_INFRA_DDCCI 17
-#define CLK_INFRA_CPUSEL 18
-#define CLK_INFRA_NR 19
+
+#define CLK_INFRA_DBG 1
+#define CLK_INFRA_SMI 2
+#define CLK_INFRA_QAXI_CM4 3
+#define CLK_INFRA_AUD_SPLIN_B 4
+#define CLK_INFRA_AUDIO 5
+#define CLK_INFRA_EFUSE 6
+#define CLK_INFRA_L2C_SRAM 7
+#define CLK_INFRA_M4U 8
+#define CLK_INFRA_CONNMCU 9
+#define CLK_INFRA_TRNG 10
+#define CLK_INFRA_RAMBUFIF 11
+#define CLK_INFRA_CPUM 12
+#define CLK_INFRA_KP 13
+#define CLK_INFRA_CEC 14
+#define CLK_INFRA_IRRX 15
+#define CLK_INFRA_PMICSPI 16
+#define CLK_INFRA_PMICWRAP 17
+#define CLK_INFRA_DDCCI 18
+#define CLK_INFRA_CLK_13M 19
+#define CLK_INFRA_CPUSEL 20
+#define CLK_INFRA_NR 21
/* PERICFG */
-#define CLK_PERI_NFI 0
-#define CLK_PERI_THERM 1
-#define CLK_PERI_PWM1 2
-#define CLK_PERI_PWM2 3
-#define CLK_PERI_PWM3 4
-#define CLK_PERI_PWM4 5
-#define CLK_PERI_PWM5 6
-#define CLK_PERI_PWM6 7
-#define CLK_PERI_PWM7 8
-#define CLK_PERI_PWM 9
-#define CLK_PERI_USB0 10
-#define CLK_PERI_USB1 11
-#define CLK_PERI_AP_DMA 12
-#define CLK_PERI_MSDC30_0 13
-#define CLK_PERI_MSDC30_1 14
-#define CLK_PERI_MSDC30_2 15
-#define CLK_PERI_MSDC30_3 16
-#define CLK_PERI_MSDC50_3 17
-#define CLK_PERI_NLI 18
-#define CLK_PERI_UART0 19
-#define CLK_PERI_UART1 20
-#define CLK_PERI_UART2 21
-#define CLK_PERI_UART3 22
-#define CLK_PERI_BTIF 23
-#define CLK_PERI_I2C0 24
-#define CLK_PERI_I2C1 25
-#define CLK_PERI_I2C2 26
-#define CLK_PERI_I2C3 27
-#define CLK_PERI_AUXADC 28
-#define CLK_PERI_SPI0 39
-#define CLK_PERI_ETH 30
-#define CLK_PERI_USB0_MCU 31
+
+#define CLK_PERI_NFI 1
+#define CLK_PERI_THERM 2
+#define CLK_PERI_PWM1 3
+#define CLK_PERI_PWM2 4
+#define CLK_PERI_PWM3 5
+#define CLK_PERI_PWM4 6
+#define CLK_PERI_PWM5 7
+#define CLK_PERI_PWM6 8
+#define CLK_PERI_PWM7 9
+#define CLK_PERI_PWM 10
+#define CLK_PERI_USB0 11
+#define CLK_PERI_USB1 12
+#define CLK_PERI_AP_DMA 13
+#define CLK_PERI_MSDC30_0 14
+#define CLK_PERI_MSDC30_1 15
+#define CLK_PERI_MSDC30_2 16
+#define CLK_PERI_MSDC30_3 17
+#define CLK_PERI_MSDC50_3 18
+#define CLK_PERI_NLI 19
+#define CLK_PERI_UART0 20
+#define CLK_PERI_UART1 21
+#define CLK_PERI_UART2 22
+#define CLK_PERI_UART3 23
+#define CLK_PERI_BTIF 24
+#define CLK_PERI_I2C0 25
+#define CLK_PERI_I2C1 26
+#define CLK_PERI_I2C2 27
+#define CLK_PERI_I2C3 28
+#define CLK_PERI_AUXADC 29
+#define CLK_PERI_SPI0 30
+#define CLK_PERI_ETH 31
+#define CLK_PERI_USB0_MCU 32
+
+#define CLK_PERI_USB1_MCU 33
+#define CLK_PERI_USB_SLV 34
+#define CLK_PERI_GCPU 35
+#define CLK_PERI_NFI_ECC 36
+#define CLK_PERI_NFI_PAD 37
+#define CLK_PERI_FLASH 38
+#define CLK_PERI_HOST89_INT 39
+#define CLK_PERI_HOST89_SPI 40
+#define CLK_PERI_HOST89_DVD 41
+#define CLK_PERI_SPI1 42
+#define CLK_PERI_SPI2 43
+#define CLK_PERI_FCI 44
-#define CLK_PERI_USB1_MCU 32
-#define CLK_PERI_USB_SLV 33
-#define CLK_PERI_GCPU 34
-#define CLK_PERI_NFI_ECC 35
-#define CLK_PERI_NFI_PAD 36
-#define CLK_PERI_FLASH 37
-#define CLK_PERI_HOST89_INT 38
-#define CLK_PERI_HOST89_SPI 39
-#define CLK_PERI_HOST89_DVD 40
-#define CLK_PERI_SPI1 41
-#define CLK_PERI_SPI2 42
-#define CLK_PERI_FCI 43
-#define CLK_PERI_NR 44
+#define CLK_PERI_UART0_SEL 45
+#define CLK_PERI_UART1_SEL 46
+#define CLK_PERI_UART2_SEL 47
+#define CLK_PERI_UART3_SEL 48
+#define CLK_PERI_NR 49
/* AUDIO */
-#define CLK_AUD_AFE 0
-#define CLK_AUD_LRCK_DETECT 1
-#define CLK_AUD_I2S 2
-#define CLK_AUD_APLL_TUNER 3
-#define CLK_AUD_HDMI 4
-#define CLK_AUD_SPDF 5
-#define CLK_AUD_SPDF2 6
-#define CLK_AUD_APLL 7
-#define CLK_AUD_TML 8
-#define CLK_AUD_AHB_IDLE_EXT 9
-#define CLK_AUD_AHB_IDLE_INT 10
-#define CLK_AUD_I2SIN1 11
-#define CLK_AUD_I2SIN2 12
-#define CLK_AUD_I2SIN3 13
-#define CLK_AUD_I2SIN4 14
-#define CLK_AUD_I2SIN5 15
-#define CLK_AUD_I2SIN6 16
-#define CLK_AUD_I2SO1 17
-#define CLK_AUD_I2SO2 18
-#define CLK_AUD_I2SO3 19
-#define CLK_AUD_I2SO4 20
-#define CLK_AUD_I2SO5 21
-#define CLK_AUD_I2SO6 22
-#define CLK_AUD_ASRCI1 23
-#define CLK_AUD_ASRCI2 24
-#define CLK_AUD_ASRCO1 25
-#define CLK_AUD_ASRCO2 26
-#define CLK_AUD_ASRC11 27
-#define CLK_AUD_ASRC12 28
-#define CLK_AUD_HDMIRX 29
-#define CLK_AUD_INTDIR 30
-#define CLK_AUD_A1SYS 31
-#define CLK_AUD_A2SYS 32
-#define CLK_AUD_AFE_CONN 33
-#define CLK_AUD_AFE_PCMIF 34
-#define CLK_AUD_AFE_MRGIF 35
+#define CLK_AUD_AFE 1
+#define CLK_AUD_LRCK_DETECT 2
+#define CLK_AUD_I2S 3
+#define CLK_AUD_APLL_TUNER 4
+#define CLK_AUD_HDMI 5
+#define CLK_AUD_SPDF 6
+#define CLK_AUD_SPDF2 7
+#define CLK_AUD_APLL 8
+#define CLK_AUD_TML 9
+#define CLK_AUD_AHB_IDLE_EXT 10
+#define CLK_AUD_AHB_IDLE_INT 11
-#define CLK_AUD_MMIF_UL1 36
-#define CLK_AUD_MMIF_UL2 37
-#define CLK_AUD_MMIF_UL3 38
-#define CLK_AUD_MMIF_UL4 39
-#define CLK_AUD_MMIF_UL5 40
-#define CLK_AUD_MMIF_UL6 41
-#define CLK_AUD_MMIF_DL1 42
-#define CLK_AUD_MMIF_DL2 43
-#define CLK_AUD_MMIF_DL3 44
-#define CLK_AUD_MMIF_DL4 45
-#define CLK_AUD_MMIF_DL5 46
-#define CLK_AUD_MMIF_DL6 47
-#define CLK_AUD_MMIF_DLMCH 48
-#define CLK_AUD_MMIF_ARB1 49
-#define CLK_AUD_MMIF_AWB1 50
-#define CLK_AUD_MMIF_AWB2 51
-#define CLK_AUD_MMIF_DAI 52
+#define CLK_AUD_I2SIN1 12
+#define CLK_AUD_I2SIN2 13
+#define CLK_AUD_I2SIN3 14
+#define CLK_AUD_I2SIN4 15
+#define CLK_AUD_I2SIN5 16
+#define CLK_AUD_I2SIN6 17
+#define CLK_AUD_I2SO1 18
+#define CLK_AUD_I2SO2 19
+#define CLK_AUD_I2SO3 20
+#define CLK_AUD_I2SO4 21
+#define CLK_AUD_I2SO5 22
+#define CLK_AUD_I2SO6 23
+#define CLK_AUD_ASRCI1 24
+#define CLK_AUD_ASRCI2 25
+#define CLK_AUD_ASRCO1 26
+#define CLK_AUD_ASRCO2 27
+#define CLK_AUD_ASRC11 28
+#define CLK_AUD_ASRC12 29
+#define CLK_AUD_HDMIRX 30
+#define CLK_AUD_INTDIR 31
+#define CLK_AUD_A1SYS 32
+#define CLK_AUD_A2SYS 33
+#define CLK_AUD_AFE_CONN 34
+#define CLK_AUD_AFE_PCMIF 35
+#define CLK_AUD_AFE_MRGIF 36
-#define CLK_AUD_DMIC1 53
-#define CLK_AUD_DMIC2 54
-#define CLK_AUD_ASRCI3 55
-#define CLK_AUD_ASRCI4 56
-#define CLK_AUD_ASRCI5 57
-#define CLK_AUD_ASRCI6 58
-#define CLK_AUD_ASRCO3 59
-#define CLK_AUD_ASRCO4 60
-#define CLK_AUD_ASRCO5 61
-#define CLK_AUD_ASRCO6 62
-#define CLK_AUD_MEM_ASRC1 63
-#define CLK_AUD_MEM_ASRC2 64
-#define CLK_AUD_MEM_ASRC3 65
-#define CLK_AUD_MEM_ASRC4 66
-#define CLK_AUD_MEM_ASRC5 67
-#define CLK_AUD_DSD_ENC 68
-#define CLK_AUD_ASRC_BRG 60
-#define CLK_AUD_NR 70
+#define CLK_AUD_MMIF_UL1 37
+#define CLK_AUD_MMIF_UL2 38
+#define CLK_AUD_MMIF_UL3 39
+#define CLK_AUD_MMIF_UL4 40
+#define CLK_AUD_MMIF_UL5 41
+#define CLK_AUD_MMIF_UL6 42
+#define CLK_AUD_MMIF_DL1 43
+#define CLK_AUD_MMIF_DL2 44
+#define CLK_AUD_MMIF_DL3 45
+#define CLK_AUD_MMIF_DL4 46
+#define CLK_AUD_MMIF_DL5 47
+#define CLK_AUD_MMIF_DL6 48
+#define CLK_AUD_MMIF_DLMCH 49
+#define CLK_AUD_MMIF_ARB1 50
+#define CLK_AUD_MMIF_AWB1 51
+#define CLK_AUD_MMIF_AWB2 52
+#define CLK_AUD_MMIF_DAI 53
+
+#define CLK_AUD_DMIC1 54
+#define CLK_AUD_DMIC2 55
+#define CLK_AUD_ASRCI3 56
+#define CLK_AUD_ASRCI4 57
+#define CLK_AUD_ASRCI5 58
+#define CLK_AUD_ASRCI6 59
+#define CLK_AUD_ASRCO3 60
+#define CLK_AUD_ASRCO4 61
+#define CLK_AUD_ASRCO5 62
+#define CLK_AUD_ASRCO6 63
+#define CLK_AUD_MEM_ASRC1 64
+#define CLK_AUD_MEM_ASRC2 65
+#define CLK_AUD_MEM_ASRC3 66
+#define CLK_AUD_MEM_ASRC4 67
+#define CLK_AUD_MEM_ASRC5 68
+#define CLK_AUD_DSD_ENC 69
+#define CLK_AUD_ASRC_BRG 70
+#define CLK_AUD_NR 71
/* MMSYS */
-#define CLK_MM_SMI_COMMON 0
-#define CLK_MM_SMI_LARB0 1
-#define CLK_MM_CMDQ 2
-#define CLK_MM_MUTEX 3
-#define CLK_MM_DISP_COLOR 4
-#define CLK_MM_DISP_BLS 5
-#define CLK_MM_DISP_WDMA 6
-#define CLK_MM_DISP_RDMA 7
-#define CLK_MM_DISP_OVL 8
-#define CLK_MM_MDP_TDSHP 9
-#define CLK_MM_MDP_WROT 10
-#define CLK_MM_MDP_WDMA 11
-#define CLK_MM_MDP_RSZ1 12
-#define CLK_MM_MDP_RSZ0 13
-#define CLK_MM_MDP_RDMA 14
-#define CLK_MM_MDP_BLS_26M 15
-#define CLK_MM_CAM_MDP 16
-#define CLK_MM_FAKE_ENG 17
-#define CLK_MM_MUTEX_32K 18
-#define CLK_MM_DISP_RDMA1 19
-#define CLK_MM_DISP_UFOE 20
+
+#define CLK_MM_SMI_COMMON 1
+#define CLK_MM_SMI_LARB0 2
+#define CLK_MM_CMDQ 3
+#define CLK_MM_MUTEX 4
+#define CLK_MM_DISP_COLOR 5
+#define CLK_MM_DISP_BLS 6
+#define CLK_MM_DISP_WDMA 7
+#define CLK_MM_DISP_RDMA 8
+#define CLK_MM_DISP_OVL 9
+#define CLK_MM_MDP_TDSHP 10
+#define CLK_MM_MDP_WROT 11
+#define CLK_MM_MDP_WDMA 12
+#define CLK_MM_MDP_RSZ1 13
+#define CLK_MM_MDP_RSZ0 14
+#define CLK_MM_MDP_RDMA 15
+#define CLK_MM_MDP_BLS_26M 16
+#define CLK_MM_CAM_MDP 17
+#define CLK_MM_FAKE_ENG 18
+#define CLK_MM_MUTEX_32K 19
+#define CLK_MM_DISP_RDMA1 20
+#define CLK_MM_DISP_UFOE 21
-#define CLK_MM_DSI_ENGINE 21
-#define CLK_MM_DSI_DIG 22
-#define CLK_MM_DPI_DIGL 23
-#define CLK_MM_DPI_ENGINE 24
-#define CLK_MM_DPI1_DIGL 25
-#define CLK_MM_DPI1_ENGINE 26
-#define CLK_MM_TVE_OUTPUT 27
-#define CLK_MM_TVE_INPUT 28
-#define CLK_MM_HDMI_PIXEL 29
-#define CLK_MM_HDMI_PLL 30
-#define CLK_MM_HDMI_AUDIO 31
-#define CLK_MM_HDMI_SPDIF 32
-#define CLK_MM_TVE_FMM 33
-#define CLK_MM_NR 34
+#define CLK_MM_DSI_ENGINE 22
+#define CLK_MM_DSI_DIG 23
+#define CLK_MM_DPI_DIGL 24
+#define CLK_MM_DPI_ENGINE 25
+#define CLK_MM_DPI1_DIGL 26
+#define CLK_MM_DPI1_ENGINE 27
+#define CLK_MM_TVE_OUTPUT 28
+#define CLK_MM_TVE_INPUT 29
+#define CLK_MM_HDMI_PIXEL 30
+#define CLK_MM_HDMI_PLL 31
+#define CLK_MM_HDMI_AUDIO 32
+#define CLK_MM_HDMI_SPDIF 33
+#define CLK_MM_TVE_FMM 34
+#define CLK_MM_NR 35
/* IMGSYS */
-#define CLK_IMG_SMI_COMM 0
-#define CLK_IMG_RESZ 1
-#define CLK_IMG_JPGDEC_SMI 2
-#define CLK_IMG_JPGDEC 3
-#define CLK_IMG_VENC_LT 4
-#define CLK_IMG_VENC 5
-#define CLK_IMG_NR 6
+
+#define CLK_IMG_SMI_COMM 1
+#define CLK_IMG_RESZ 2
+#define CLK_IMG_JPGDEC_SMI 3
+#define CLK_IMG_JPGDEC 4
+#define CLK_IMG_VENC_LT 5
+#define CLK_IMG_VENC 6
+#define CLK_IMG_NR 7
/* VDEC */
-#define CLK_VDEC_CKGEN 0
-#define CLK_VDEC_LARB 1
-#define CLK_VDEC_NR 2
+
+#define CLK_VDEC_CKGEN 1
+#define CLK_VDEC_LARB 2
+#define CLK_VDEC_NR 3
/* HIFSYS */
-#define CLK_HIFSYS_USB0PHY 0
-#define CLK_HIFSYS_USB1PHY 1
-#define CLK_HIFSYS_PCIE0 2
-#define CLK_HIFSYS_PCIE1 3
-#define CLK_HIFSYS_PCIE2 4
-#define CLK_HIFSYS_NR 5
+
+#define CLK_HIFSYS_USB0PHY 1
+#define CLK_HIFSYS_USB1PHY 2
+#define CLK_HIFSYS_PCIE0 3
+#define CLK_HIFSYS_PCIE1 4
+#define CLK_HIFSYS_PCIE2 5
+#define CLK_HIFSYS_NR 6
/* ETHSYS */
-#define CLK_ETHSYS_HSDMA 0
-#define CLK_ETHSYS_ESW 1
-#define CLK_ETHSYS_GP2 2
-#define CLK_ETHSYS_GP1 3
-#define CLK_ETHSYS_PCM 4
-#define CLK_ETHSYS_GDMA 5
-#define CLK_ETHSYS_I2S 6
-#define CLK_ETHSYS_CRYPTO 7
-#define CLK_ETHSYS_NR 8
+#define CLK_ETHSYS_HSDMA 1
+#define CLK_ETHSYS_ESW 2
+#define CLK_ETHSYS_GP2 3
+#define CLK_ETHSYS_GP1 4
+#define CLK_ETHSYS_PCM 5
+#define CLK_ETHSYS_GDMA 6
+#define CLK_ETHSYS_I2S 7
+#define CLK_ETHSYS_CRYPTO 8
+#define CLK_ETHSYS_NR 9
/* G3DSYS */
-#define CLK_G3DSYS_CORE 0
-#define CLK_G3DSYS_NR 1
+#define CLK_G3DSYS_CORE 1
+#define CLK_G3DSYS_NR 2
+
+/* BDP */
+
+#define CLK_BDP_BRG_BA 1
+#define CLK_BDP_BRG_DRAM 2
+#define CLK_BDP_LARB_DRAM 3
+#define CLK_BDP_WR_VDI_PXL 4
+#define CLK_BDP_WR_VDI_DRAM 5
+#define CLK_BDP_WR_B 6
+#define CLK_BDP_DGI_IN 7
+#define CLK_BDP_DGI_OUT 8
+#define CLK_BDP_FMT_MAST_27 9
+#define CLK_BDP_FMT_B 10
+#define CLK_BDP_OSD_B 11
+#define CLK_BDP_OSD_DRAM 12
+#define CLK_BDP_OSD_AGENT 13
+#define CLK_BDP_OSD_PXL 14
+#define CLK_BDP_RLE_B 15
+#define CLK_BDP_RLE_AGENT 16
+#define CLK_BDP_RLE_DRAM 17
+#define CLK_BDP_F27M 18
+#define CLK_BDP_F27M_VDOUT 19
+#define CLK_BDP_F27_74_74 20
+#define CLK_BDP_F2FS 21
+#define CLK_BDP_F2FS74_148 22
+#define CLK_BDP_FB 23
+#define CLK_BDP_VDO_DRAM 24
+#define CLK_BDP_VDO_2FS 25
+#define CLK_BDP_VDO_B 26
+#define CLK_BDP_WR_DI_PXL 27
+#define CLK_BDP_WR_DI_DRAM 28
+#define CLK_BDP_WR_DI_B 29
+#define CLK_BDP_NR_PXL 30
+#define CLK_BDP_NR_DRAM 31
+#define CLK_BDP_NR_B 32
+
+#define CLK_BDP_RX_F 33
+#define CLK_BDP_RX_X 34
+#define CLK_BDP_RXPDT 35
+#define CLK_BDP_RX_CSCL_N 36
+#define CLK_BDP_RX_CSCL 37
+#define CLK_BDP_RX_DDCSCL_N 38
+#define CLK_BDP_RX_DDCSCL 39
+#define CLK_BDP_RX_VCO 40
+#define CLK_BDP_RX_DP 41
+#define CLK_BDP_RX_P 42
+#define CLK_BDP_RX_M 43
+#define CLK_BDP_RX_PLL 44
+#define CLK_BDP_BRG_RT_B 45
+#define CLK_BDP_BRG_RT_DRAM 46
+#define CLK_BDP_LARBRT_DRAM 47
+#define CLK_BDP_TMDS_SYN 48
+#define CLK_BDP_HDMI_MON 49
+#define CLK_BDP_NR 50
#endif /* _DT_BINDINGS_CLK_MT2701_H */
diff --git a/include/dt-bindings/clock/mt7981-clk.h b/include/dt-bindings/clock/mt7981-clk.h
index e24c759..5232591 100644
--- a/include/dt-bindings/clock/mt7981-clk.h
+++ b/include/dt-bindings/clock/mt7981-clk.h
@@ -8,260 +8,219 @@
#ifndef _DT_BINDINGS_CLK_MT7981_H
#define _DT_BINDINGS_CLK_MT7981_H
-/* INFRACFG */
-
-#define CK_INFRA_CK_F26M 0
-#define CK_INFRA_UART 1
-#define CK_INFRA_ISPI0 2
-#define CK_INFRA_I2C 3
-#define CK_INFRA_ISPI1 4
-#define CK_INFRA_PWM 5
-#define CK_INFRA_66M_MCK 6
-#define CK_INFRA_CK_F32K 7
-#define CK_INFRA_PCIE_CK 8
-#define CK_INFRA_PWM_BCK 9
-#define CK_INFRA_PWM_CK1 10
-#define CK_INFRA_PWM_CK2 11
-#define CK_INFRA_133M_HCK 12
-#define CK_INFRA_66M_PHCK 13
-#define CK_INFRA_FAUD_L_CK 14
-#define CK_INFRA_FAUD_AUD_CK 15
-#define CK_INFRA_FAUD_EG2_CK 16
-#define CK_INFRA_I2CS_CK 17
-#define CK_INFRA_MUX_UART0 18
-#define CK_INFRA_MUX_UART1 19
-#define CK_INFRA_MUX_UART2 20
-#define CK_INFRA_NFI_CK 21
-#define CK_INFRA_SPINFI_CK 22
-#define CK_INFRA_MUX_SPI0 23
-#define CK_INFRA_MUX_SPI1 24
-#define CK_INFRA_MUX_SPI2 25
-#define CK_INFRA_RTC_32K 26
-#define CK_INFRA_FMSDC_CK 27
-#define CK_INFRA_FMSDC_HCK_CK 28
-#define CK_INFRA_PERI_133M 29
-#define CK_INFRA_133M_PHCK 30
-#define CK_INFRA_USB_SYS_CK 31
-#define CK_INFRA_USB_CK 32
-#define CK_INFRA_USB_XHCI_CK 33
-#define CK_INFRA_PCIE_GFMUX_TL_O_PRE 34
-#define CK_INFRA_F26M_CK0 35
-#define CK_INFRA_133M_MCK 36
-#define CLK_INFRA_NR_CLK 37
-
/* TOPCKGEN */
-#define CK_TOP_CB_CKSQ_40M 0
-#define CK_TOP_CB_M_416M 1
-#define CK_TOP_CB_M_D2 2
-#define CK_TOP_CB_M_D3 3
-#define CK_TOP_M_D3_D2 4
-#define CK_TOP_CB_M_D4 5
-#define CK_TOP_CB_M_D8 6
-#define CK_TOP_M_D8_D2 7
-#define CK_TOP_CB_MM_720M 8
-#define CK_TOP_CB_MM_D2 9
-#define CK_TOP_CB_MM_D3 10
-#define CK_TOP_CB_MM_D3_D5 11
-#define CK_TOP_CB_MM_D4 12
-#define CK_TOP_CB_MM_D6 13
-#define CK_TOP_MM_D6_D2 14
-#define CK_TOP_CB_MM_D8 15
-#define CK_TOP_CB_APLL2_196M 16
-#define CK_TOP_APLL2_D2 17
-#define CK_TOP_APLL2_D4 18
-#define CK_TOP_NET1_2500M 19
-#define CK_TOP_CB_NET1_D4 20
-#define CK_TOP_CB_NET1_D5 21
-#define CK_TOP_NET1_D5_D2 22
-#define CK_TOP_NET1_D5_D4 23
-#define CK_TOP_CB_NET1_D8 24
-#define CK_TOP_NET1_D8_D2 25
-#define CK_TOP_NET1_D8_D4 26
-#define CK_TOP_CB_NET2_800M 27
-#define CK_TOP_CB_NET2_D2 28
-#define CK_TOP_CB_NET2_D4 29
-#define CK_TOP_NET2_D4_D2 30
-#define CK_TOP_NET2_D4_D4 31
-#define CK_TOP_CB_NET2_D6 32
-#define CK_TOP_CB_WEDMCU_208M 33
-#define CK_TOP_CB_SGM_325M 34
-#define CK_TOP_CKSQ_40M_D2 35
-#define CK_TOP_CB_RTC_32K 36
-#define CK_TOP_CB_RTC_32P7K 37
-#define CK_TOP_USB_TX250M 38
-#define CK_TOP_FAUD 39
-#define CK_TOP_NFI1X 40
-#define CK_TOP_USB_EQ_RX250M 41
-#define CK_TOP_USB_CDR_CK 42
-#define CK_TOP_USB_LN0_CK 43
-#define CK_TOP_SPINFI_BCK 44
-#define CK_TOP_SPI 45
-#define CK_TOP_SPIM_MST 46
-#define CK_TOP_UART_BCK 47
-#define CK_TOP_PWM_BCK 48
-#define CK_TOP_I2C_BCK 49
-#define CK_TOP_PEXTP_TL 50
-#define CK_TOP_EMMC_208M 51
-#define CK_TOP_EMMC_400M 52
-#define CK_TOP_DRAMC_REF 53
-#define CK_TOP_DRAMC_MD32 54
-#define CK_TOP_SYSAXI 55
-#define CK_TOP_SYSAPB 56
-#define CK_TOP_ARM_DB_MAIN 57
-#define CK_TOP_AP2CNN_HOST 58
-#define CK_TOP_NETSYS 59
-#define CK_TOP_NETSYS_500M 60
-#define CK_TOP_NETSYS_WED_MCU 61
-#define CK_TOP_NETSYS_2X 62
-#define CK_TOP_SGM_325M 63
-#define CK_TOP_SGM_REG 64
-#define CK_TOP_F26M 65
-#define CK_TOP_EIP97B 66
-#define CK_TOP_USB3_PHY 67
-#define CK_TOP_AUD 68
-#define CK_TOP_A1SYS 69
-#define CK_TOP_AUD_L 70
-#define CK_TOP_A_TUNER 71
-#define CK_TOP_U2U3_REF 72
-#define CK_TOP_U2U3_SYS 73
-#define CK_TOP_U2U3_XHCI 74
-#define CK_TOP_USB_FRMCNT 75
-#define CK_TOP_NFI1X_SEL 76
-#define CK_TOP_SPINFI_SEL 77
-#define CK_TOP_SPI_SEL 78
-#define CK_TOP_SPIM_MST_SEL 79
-#define CK_TOP_UART_SEL 80
-#define CK_TOP_PWM_SEL 81
-#define CK_TOP_I2C_SEL 82
-#define CK_TOP_PEXTP_TL_SEL 83
-#define CK_TOP_EMMC_208M_SEL 84
-#define CK_TOP_EMMC_400M_SEL 85
-#define CK_TOP_F26M_SEL 86
-#define CK_TOP_DRAMC_SEL 87
-#define CK_TOP_DRAMC_MD32_SEL 88
-#define CK_TOP_SYSAXI_SEL 89
-#define CK_TOP_SYSAPB_SEL 90
-#define CK_TOP_ARM_DB_MAIN_SEL 91
-#define CK_TOP_AP2CNN_HOST_SEL 92
-#define CK_TOP_NETSYS_SEL 93
-#define CK_TOP_NETSYS_500M_SEL 94
-#define CK_TOP_NETSYS_MCU_SEL 95
-#define CK_TOP_NETSYS_2X_SEL 96
-#define CK_TOP_SGM_325M_SEL 97
-#define CK_TOP_SGM_REG_SEL 98
-#define CK_TOP_EIP97B_SEL 99
-#define CK_TOP_USB3_PHY_SEL 100
-#define CK_TOP_AUD_SEL 101
-#define CK_TOP_A1SYS_SEL 102
-#define CK_TOP_AUD_L_SEL 103
-#define CK_TOP_A_TUNER_SEL 104
-#define CK_TOP_U2U3_SEL 105
-#define CK_TOP_U2U3_SYS_SEL 106
-#define CK_TOP_U2U3_XHCI_SEL 107
-#define CK_TOP_USB_FRMCNT_SEL 108
-#define CLK_TOP_NR_CLK 109
+#define CLK_TOP_CB_CKSQ_40M 0
+#define CLK_TOP_CB_M_416M 1
+#define CLK_TOP_CB_M_D2 2
+#define CLK_TOP_CB_M_D3 3
+#define CLK_TOP_M_D3_D2 4
+#define CLK_TOP_CB_M_D4 5
+#define CLK_TOP_CB_M_D8 6
+#define CLK_TOP_M_D8_D2 7
+#define CLK_TOP_CB_MM_720M 8
+#define CLK_TOP_CB_MM_D2 9
+#define CLK_TOP_CB_MM_D3 10
+#define CLK_TOP_CB_MM_D3_D5 11
+#define CLK_TOP_CB_MM_D4 12
+#define CLK_TOP_CB_MM_D6 13
+#define CLK_TOP_MM_D6_D2 14
+#define CLK_TOP_CB_MM_D8 15
+#define CLK_TOP_CB_APLL2_196M 16
+#define CLK_TOP_APLL2_D2 17
+#define CLK_TOP_APLL2_D4 18
+#define CLK_TOP_NET1_2500M 19
+#define CLK_TOP_CB_NET1_D4 20
+#define CLK_TOP_CB_NET1_D5 21
+#define CLK_TOP_NET1_D5_D2 22
+#define CLK_TOP_NET1_D5_D4 23
+#define CLK_TOP_CB_NET1_D8 24
+#define CLK_TOP_NET1_D8_D2 25
+#define CLK_TOP_NET1_D8_D4 26
+#define CLK_TOP_CB_NET2_800M 27
+#define CLK_TOP_CB_NET2_D2 28
+#define CLK_TOP_CB_NET2_D4 29
+#define CLK_TOP_NET2_D4_D2 30
+#define CLK_TOP_NET2_D4_D4 31
+#define CLK_TOP_CB_NET2_D6 32
+#define CLK_TOP_CB_WEDMCU_208M 33
+#define CLK_TOP_CB_SGM_325M 34
+#define CLK_TOP_CKSQ_40M_D2 35
+#define CLK_TOP_CB_RTC_32K 36
+#define CLK_TOP_CB_RTC_32P7K 37
+#define CLK_TOP_USB_TX250M 38
+#define CLK_TOP_FAUD 39
+#define CLK_TOP_NFI1X 40
+#define CLK_TOP_USB_EQ_RX250M 41
+#define CLK_TOP_USB_CDR_CK 42
+#define CLK_TOP_USB_LN0_CK 43
+#define CLK_TOP_SPINFI_BCK 44
+#define CLK_TOP_SPI 45
+#define CLK_TOP_SPIM_MST 46
+#define CLK_TOP_UART_BCK 47
+#define CLK_TOP_PWM_BCK 48
+#define CLK_TOP_I2C_BCK 49
+#define CLK_TOP_PEXTP_TL 50
+#define CLK_TOP_EMMC_208M 51
+#define CLK_TOP_EMMC_400M 52
+#define CLK_TOP_DRAMC_REF 53
+#define CLK_TOP_DRAMC_MD32 54
+#define CLK_TOP_SYSAXI 55
+#define CLK_TOP_SYSAPB 56
+#define CLK_TOP_ARM_DB_MAIN 57
+#define CLK_TOP_AP2CNN_HOST 58
+#define CLK_TOP_NETSYS 59
+#define CLK_TOP_NETSYS_500M 60
+#define CLK_TOP_NETSYS_WED_MCU 61
+#define CLK_TOP_NETSYS_2X 62
+#define CLK_TOP_SGM_325M 63
+#define CLK_TOP_SGM_REG 64
+#define CLK_TOP_F26M 65
+#define CLK_TOP_EIP97B 66
+#define CLK_TOP_USB3_PHY 67
+#define CLK_TOP_AUD 68
+#define CLK_TOP_A1SYS 69
+#define CLK_TOP_AUD_L 70
+#define CLK_TOP_A_TUNER 71
+#define CLK_TOP_U2U3_REF 72
+#define CLK_TOP_U2U3_SYS 73
+#define CLK_TOP_U2U3_XHCI 74
+#define CLK_TOP_USB_FRMCNT 75
+#define CLK_TOP_NFI1X_SEL 76
+#define CLK_TOP_SPINFI_SEL 77
+#define CLK_TOP_SPI_SEL 78
+#define CLK_TOP_SPIM_MST_SEL 79
+#define CLK_TOP_UART_SEL 80
+#define CLK_TOP_PWM_SEL 81
+#define CLK_TOP_I2C_SEL 82
+#define CLK_TOP_PEXTP_TL_SEL 83
+#define CLK_TOP_EMMC_208M_SEL 84
+#define CLK_TOP_EMMC_400M_SEL 85
+#define CLK_TOP_F26M_SEL 86
+#define CLK_TOP_DRAMC_SEL 87
+#define CLK_TOP_DRAMC_MD32_SEL 88
+#define CLK_TOP_SYSAXI_SEL 89
+#define CLK_TOP_SYSAPB_SEL 90
+#define CLK_TOP_ARM_DB_MAIN_SEL 91
+#define CLK_TOP_AP2CNN_HOST_SEL 92
+#define CLK_TOP_NETSYS_SEL 93
+#define CLK_TOP_NETSYS_500M_SEL 94
+#define CLK_TOP_NETSYS_MCU_SEL 95
+#define CLK_TOP_NETSYS_2X_SEL 96
+#define CLK_TOP_SGM_325M_SEL 97
+#define CLK_TOP_SGM_REG_SEL 98
+#define CLK_TOP_EIP97B_SEL 99
+#define CLK_TOP_USB3_PHY_SEL 100
+#define CLK_TOP_AUD_SEL 101
+#define CLK_TOP_A1SYS_SEL 102
+#define CLK_TOP_AUD_L_SEL 103
+#define CLK_TOP_A_TUNER_SEL 104
+#define CLK_TOP_U2U3_SEL 105
+#define CLK_TOP_U2U3_SYS_SEL 106
+#define CLK_TOP_U2U3_XHCI_SEL 107
+#define CLK_TOP_USB_FRMCNT_SEL 108
+#define CLK_TOP_AUD_I2S_M 109
+#define CLK_TOP_NR_CLK 110
-/*
- * INFRACFG_AO
- * clock muxes need to be append to infracfg domain, and clock gates
- * need to be keep in infracgh_ao domain
- */
-#define INFRACFG_AO_OFFSET 10
+/* INFRACFG */
-#define CK_INFRA_UART0_SEL (0 + CLK_INFRA_NR_CLK)
-#define CK_INFRA_UART1_SEL (1 + CLK_INFRA_NR_CLK)
-#define CK_INFRA_UART2_SEL (2 + CLK_INFRA_NR_CLK)
-#define CK_INFRA_SPI0_SEL (3 + CLK_INFRA_NR_CLK)
-#define CK_INFRA_SPI1_SEL (4 + CLK_INFRA_NR_CLK)
-#define CK_INFRA_SPI2_SEL (5 + CLK_INFRA_NR_CLK)
-#define CK_INFRA_PWM1_SEL (6 + CLK_INFRA_NR_CLK)
-#define CK_INFRA_PWM2_SEL (7 + CLK_INFRA_NR_CLK)
-#define CK_INFRA_PWM_BSEL (8 + CLK_INFRA_NR_CLK)
-#define CK_INFRA_PCIE_SEL (9 + CLK_INFRA_NR_CLK)
-#define CK_INFRA_GPT_STA (10 - INFRACFG_AO_OFFSET)
-#define CK_INFRA_PWM_HCK (11 - INFRACFG_AO_OFFSET)
-#define CK_INFRA_PWM_STA (12 - INFRACFG_AO_OFFSET)
-#define CK_INFRA_PWM1_CK (13 - INFRACFG_AO_OFFSET)
-#define CK_INFRA_PWM2_CK (14 - INFRACFG_AO_OFFSET)
-#define CK_INFRA_CQ_DMA_CK (15 - INFRACFG_AO_OFFSET)
-#define CK_INFRA_AUD_BUS_CK (16 - INFRACFG_AO_OFFSET)
-#define CK_INFRA_AUD_26M_CK (17 - INFRACFG_AO_OFFSET)
-#define CK_INFRA_AUD_L_CK (18 - INFRACFG_AO_OFFSET)
-#define CK_INFRA_AUD_AUD_CK (19 - INFRACFG_AO_OFFSET)
-#define CK_INFRA_AUD_EG2_CK (20 - INFRACFG_AO_OFFSET)
-#define CK_INFRA_DRAMC_26M_CK (21 - INFRACFG_AO_OFFSET)
-#define CK_INFRA_DBG_CK (22 - INFRACFG_AO_OFFSET)
-#define CK_INFRA_AP_DMA_CK (23 - INFRACFG_AO_OFFSET)
-#define CK_INFRA_SEJ_CK (24 - INFRACFG_AO_OFFSET)
-#define CK_INFRA_SEJ_13M_CK (25 - INFRACFG_AO_OFFSET)
-#define CK_INFRA_THERM_CK (26 - INFRACFG_AO_OFFSET)
-#define CK_INFRA_I2CO_CK (27 - INFRACFG_AO_OFFSET)
-#define CK_INFRA_UART0_CK (28 - INFRACFG_AO_OFFSET)
-#define CK_INFRA_UART1_CK (29 - INFRACFG_AO_OFFSET)
-#define CK_INFRA_UART2_CK (30 - INFRACFG_AO_OFFSET)
-#define CK_INFRA_SPI2_CK (31 - INFRACFG_AO_OFFSET)
-#define CK_INFRA_SPI2_HCK_CK (32 - INFRACFG_AO_OFFSET)
-#define CK_INFRA_NFI1_CK (33 - INFRACFG_AO_OFFSET)
-#define CK_INFRA_SPINFI1_CK (34 - INFRACFG_AO_OFFSET)
-#define CK_INFRA_NFI_HCK_CK (35 - INFRACFG_AO_OFFSET)
-#define CK_INFRA_SPI0_CK (36 - INFRACFG_AO_OFFSET)
-#define CK_INFRA_SPI1_CK (37 - INFRACFG_AO_OFFSET)
-#define CK_INFRA_SPI0_HCK_CK (38 - INFRACFG_AO_OFFSET)
-#define CK_INFRA_SPI1_HCK_CK (39 - INFRACFG_AO_OFFSET)
-#define CK_INFRA_FRTC_CK (40 - INFRACFG_AO_OFFSET)
-#define CK_INFRA_MSDC_CK (41 - INFRACFG_AO_OFFSET)
-#define CK_INFRA_MSDC_HCK_CK (42 - INFRACFG_AO_OFFSET)
-#define CK_INFRA_MSDC_133M_CK (43 - INFRACFG_AO_OFFSET)
-#define CK_INFRA_MSDC_66M_CK (44 - INFRACFG_AO_OFFSET)
-#define CK_INFRA_ADC_26M_CK (45 - INFRACFG_AO_OFFSET)
-#define CK_INFRA_ADC_FRC_CK (46 - INFRACFG_AO_OFFSET)
-#define CK_INFRA_FBIST2FPC_CK (47 - INFRACFG_AO_OFFSET)
-#define CK_INFRA_I2C_MCK_CK (48 - INFRACFG_AO_OFFSET)
-#define CK_INFRA_I2C_PCK_CK (49 - INFRACFG_AO_OFFSET)
-#define CK_INFRA_IUSB_133_CK (50 - INFRACFG_AO_OFFSET)
-#define CK_INFRA_IUSB_66M_CK (51 - INFRACFG_AO_OFFSET)
-#define CK_INFRA_IUSB_SYS_CK (52 - INFRACFG_AO_OFFSET)
-#define CK_INFRA_IUSB_CK (53 - INFRACFG_AO_OFFSET)
-#define CK_INFRA_IPCIE_CK (54 - INFRACFG_AO_OFFSET)
-#define CK_INFRA_IPCIER_CK (55 - INFRACFG_AO_OFFSET)
-#define CK_INFRA_IPCIEB_CK (56 - INFRACFG_AO_OFFSET)
-#define CLK_INFRA_AO_NR_CLK (57 - INFRACFG_AO_OFFSET)
+#define CLK_INFRA_66M_MCK 0
+#define CLK_INFRA_UART0_SEL 1
+#define CLK_INFRA_UART1_SEL 2
+#define CLK_INFRA_UART2_SEL 3
+#define CLK_INFRA_SPI0_SEL 4
+#define CLK_INFRA_SPI1_SEL 5
+#define CLK_INFRA_SPI2_SEL 6
+#define CLK_INFRA_PWM1_SEL 7
+#define CLK_INFRA_PWM2_SEL 8
+#define CLK_INFRA_PWM3_SEL 9
+#define CLK_INFRA_PWM_BSEL 10
+#define CLK_INFRA_PCIE_SEL 11
+#define CLK_INFRA_GPT_STA 12
+#define CLK_INFRA_PWM_HCK 13
+#define CLK_INFRA_PWM_STA 14
+#define CLK_INFRA_PWM1_CK 15
+#define CLK_INFRA_PWM2_CK 16
+#define CLK_INFRA_PWM3_CK 17
+#define CLK_INFRA_CQ_DMA_CK 18
+#define CLK_INFRA_AUD_BUS_CK 19
+#define CLK_INFRA_AUD_26M_CK 20
+#define CLK_INFRA_AUD_L_CK 21
+#define CLK_INFRA_AUD_AUD_CK 22
+#define CLK_INFRA_AUD_EG2_CK 23
+#define CLK_INFRA_DRAMC_26M_CK 24
+#define CLK_INFRA_DBG_CK 25
+#define CLK_INFRA_AP_DMA_CK 26
+#define CLK_INFRA_SEJ_CK 27
+#define CLK_INFRA_SEJ_13M_CK 28
+#define CLK_INFRA_THERM_CK 29
+#define CLK_INFRA_I2C0_CK 30
+#define CLK_INFRA_UART0_CK 31
+#define CLK_INFRA_UART1_CK 32
+#define CLK_INFRA_UART2_CK 33
+#define CLK_INFRA_SPI2_CK 34
+#define CLK_INFRA_SPI2_HCK_CK 35
+#define CLK_INFRA_NFI1_CK 36
+#define CLK_INFRA_SPINFI1_CK 37
+#define CLK_INFRA_NFI_HCK_CK 38
+#define CLK_INFRA_SPI0_CK 39
+#define CLK_INFRA_SPI1_CK 40
+#define CLK_INFRA_SPI0_HCK_CK 41
+#define CLK_INFRA_SPI1_HCK_CK 42
+#define CLK_INFRA_FRTC_CK 43
+#define CLK_INFRA_MSDC_CK 44
+#define CLK_INFRA_MSDC_HCK_CK 45
+#define CLK_INFRA_MSDC_133M_CK 46
+#define CLK_INFRA_MSDC_66M_CK 47
+#define CLK_INFRA_ADC_26M_CK 48
+#define CLK_INFRA_ADC_FRC_CK 49
+#define CLK_INFRA_FBIST2FPC_CK 50
+#define CLK_INFRA_I2C_MCK_CK 51
+#define CLK_INFRA_I2C_PCK_CK 52
+#define CLK_INFRA_IUSB_133_CK 53
+#define CLK_INFRA_IUSB_66M_CK 54
+#define CLK_INFRA_IUSB_SYS_CK 55
+#define CLK_INFRA_IUSB_CK 56
+#define CLK_INFRA_IPCIE_CK 57
+#define CLK_INFRA_IPCIE_PIPE_CK 58
+#define CLK_INFRA_IPCIER_CK 59
+#define CLK_INFRA_IPCIEB_CK 60
+#define CLK_INFRA_NR_CLK 61
/* APMIXEDSYS */
-#define CK_APMIXED_ARMPLL 0
-#define CK_APMIXED_NET2PLL 1
-#define CK_APMIXED_MMPLL 2
-#define CK_APMIXED_SGMPLL 3
-#define CK_APMIXED_WEDMCUPLL 4
-#define CK_APMIXED_NET1PLL 5
-#define CK_APMIXED_MPLL 6
-#define CK_APMIXED_APLL2 7
+#define CLK_APMIXED_ARMPLL 0
+#define CLK_APMIXED_NET2PLL 1
+#define CLK_APMIXED_MMPLL 2
+#define CLK_APMIXED_SGMPLL 3
+#define CLK_APMIXED_WEDMCUPLL 4
+#define CLK_APMIXED_NET1PLL 5
+#define CLK_APMIXED_MPLL 6
+#define CLK_APMIXED_APLL2 7
#define CLK_APMIXED_NR_CLK 8
/* SGMIISYS_0 */
-#define CK_SGM0_TX_EN 0
-#define CK_SGM0_RX_EN 1
-#define CK_SGM0_CK0_EN 2
-#define CK_SGM0_CDR_CK0_EN 3
+#define CLK_SGM0_TX_EN 0
+#define CLK_SGM0_RX_EN 1
+#define CLK_SGM0_CK0_EN 2
+#define CLK_SGM0_CDR_CK0_EN 3
#define CLK_SGMII0_NR_CLK 4
/* SGMIISYS_1 */
-#define CK_SGM1_TX_EN 0
-#define CK_SGM1_RX_EN 1
-#define CK_SGM1_CK1_EN 2
-#define CK_SGM1_CDR_CK1_EN 3
+#define CLK_SGM1_TX_EN 0
+#define CLK_SGM1_RX_EN 1
+#define CLK_SGM1_CK1_EN 2
+#define CLK_SGM1_CDR_CK1_EN 3
#define CLK_SGMII1_NR_CLK 4
/* ETHSYS */
-#define CK_ETH_FE_EN 0
-#define CK_ETH_GP2_EN 1
-#define CK_ETH_GP1_EN 2
-#define CK_ETH_WOCPU0_EN 3
+#define CLK_ETH_FE_EN 0
+#define CLK_ETH_GP2_EN 1
+#define CLK_ETH_GP1_EN 2
+#define CLK_ETH_WOCPU0_EN 3
#define CLK_ETH_NR_CLK 4
#endif /* _DT_BINDINGS_CLK_MT7981_H */
diff --git a/include/dt-bindings/clock/mt7986-clk.h b/include/dt-bindings/clock/mt7986-clk.h
index 820f863..5da2603 100644
--- a/include/dt-bindings/clock/mt7986-clk.h
+++ b/include/dt-bindings/clock/mt7986-clk.h
@@ -8,240 +8,169 @@
#ifndef _DT_BINDINGS_CLK_MT7986_H
#define _DT_BINDINGS_CLK_MT7986_H
-/* INFRACFG */
-
-#define CK_INFRA_CK_F26M 0
-#define CK_INFRA_UART 1
-#define CK_INFRA_ISPI0 2
-#define CK_INFRA_I2C 3
-#define CK_INFRA_ISPI1 4
-#define CK_INFRA_PWM 5
-#define CK_INFRA_66M_MCK 6
-#define CK_INFRA_CK_F32K 7
-#define CK_INFRA_PCIE_CK 8
-#define CK_INFRA_PWM_BCK 9
-#define CK_INFRA_PWM_CK1 10
-#define CK_INFRA_PWM_CK2 11
-#define CK_INFRA_133M_HCK 12
-#define CK_INFRA_EIP_CK 13
-#define CK_INFRA_66M_PHCK 14
-#define CK_INFRA_FAUD_L_CK 15
-#define CK_INFRA_FAUD_AUD_CK 17
-#define CK_INFRA_FAUD_EG2_CK 17
-#define CK_INFRA_I2CS_CK 18
-#define CK_INFRA_MUX_UART0 19
-#define CK_INFRA_MUX_UART1 20
-#define CK_INFRA_MUX_UART2 21
-#define CK_INFRA_NFI_CK 22
-#define CK_INFRA_SPINFI_CK 23
-#define CK_INFRA_MUX_SPI0 24
-#define CK_INFRA_MUX_SPI1 25
-#define CK_INFRA_RTC_32K 26
-#define CK_INFRA_FMSDC_CK 27
-#define CK_INFRA_FMSDC_HCK_CK 28
-#define CK_INFRA_PERI_133M 29
-#define CK_INFRA_133M_PHCK 30
-#define CK_INFRA_USB_SYS_CK 31
-#define CK_INFRA_USB_CK 32
-#define CK_INFRA_USB_XHCI_CK 33
-#define CK_INFRA_PCIE_GFMUX_TL_O_PRE 34
-#define CK_INFRA_F26M_CK0 35
-#define CK_INFRA_HD_133M 36
-#define CLK_INFRA_NR_CLK 37
-
/* TOPCKGEN */
-#define CK_TOP_CB_CKSQ_40M 0
-#define CK_TOP_CB_M_416M 1
-#define CK_TOP_CB_M_D2 2
-#define CK_TOP_CB_M_D4 3
-#define CK_TOP_CB_M_D8 4
-#define CK_TOP_M_D8_D2 5
-#define CK_TOP_M_D3_D2 6
-#define CK_TOP_CB_MM_D2 7
-#define CK_TOP_CB_MM_D4 8
-#define CK_TOP_CB_MM_D8 9
-#define CK_TOP_MM_D8_D2 10
-#define CK_TOP_MM_D3_D8 11
-#define CK_TOP_CB_U2_PHYD_CK 12
-#define CK_TOP_CB_APLL2_196M 13
-#define CK_TOP_APLL2_D4 14
-#define CK_TOP_CB_NET1_D4 15
-#define CK_TOP_CB_NET1_D5 16
-#define CK_TOP_NET1_D5_D2 17
-#define CK_TOP_NET1_D5_D4 18
-#define CK_TOP_NET1_D8_D2 19
-#define CK_TOP_NET1_D8_D4 20
-#define CK_TOP_CB_NET2_800M 21
-#define CK_TOP_CB_NET2_D4 22
-#define CK_TOP_NET2_D4_D2 23
-#define CK_TOP_NET2_D3_D2 24
-#define CK_TOP_CB_WEDMCU_760M 25
-#define CK_TOP_WEDMCU_D5_D2 26
-#define CK_TOP_CB_SGM_325M 27
-#define CK_TOP_CB_CKSQ_40M_D2 28
-#define CK_TOP_CB_RTC_32K 29
-#define CK_TOP_CB_RTC_32P7K 30
-#define CK_TOP_NFI1X 31
-#define CK_TOP_USB_EQ_RX250M 32
-#define CK_TOP_USB_TX250M 33
-#define CK_TOP_USB_LN0_CK 34
-#define CK_TOP_USB_CDR_CK 35
-#define CK_TOP_SPINFI_BCK 36
-#define CK_TOP_I2C_BCK 37
-#define CK_TOP_PEXTP_TL 38
-#define CK_TOP_EMMC_250M 39
-#define CK_TOP_EMMC_416M 40
-#define CK_TOP_F_26M_ADC_CK 41
-#define CK_TOP_SYSAXI 42
-#define CK_TOP_NETSYS_WED_MCU 43
-#define CK_TOP_NETSYS_2X 44
-#define CK_TOP_SGM_325M 45
-#define CK_TOP_A1SYS 46
-#define CK_TOP_EIP_B 47
-#define CK_TOP_F26M 48
-#define CK_TOP_AUD_L 49
-#define CK_TOP_A_TUNER 50
-#define CK_TOP_U2U3_REF 51
-#define CK_TOP_U2U3_SYS 52
-#define CK_TOP_U2U3_XHCI 53
-#define CK_TOP_AP2CNN_HOST 54
-#define CK_TOP_NFI1X_SEL 55
-#define CK_TOP_SPINFI_SEL 56
-#define CK_TOP_SPI_SEL 57
-#define CK_TOP_SPIM_MST_SEL 58
-#define CK_TOP_UART_SEL 59
-#define CK_TOP_PWM_SEL 60
-#define CK_TOP_I2C_SEL 61
-#define CK_TOP_PEXTP_TL_SEL 62
-#define CK_TOP_EMMC_250M_SEL 63
-#define CK_TOP_EMMC_416M_SEL 64
-#define CK_TOP_F_26M_ADC_SEL 65
-#define CK_TOP_DRAMC_SEL 66
-#define CK_TOP_DRAMC_MD32_SEL 67
-#define CK_TOP_SYSAXI_SEL 68
-#define CK_TOP_SYSAPB_SEL 69
-#define CK_TOP_ARM_DB_MAIN_SEL 70
-#define CK_TOP_ARM_DB_JTSEL 71
-#define CK_TOP_NETSYS_SEL 72
-#define CK_TOP_NETSYS_500M_SEL 73
-#define CK_TOP_NETSYS_MCU_SEL 74
-#define CK_TOP_NETSYS_2X_SEL 75
-#define CK_TOP_SGM_325M_SEL 76
-#define CK_TOP_SGM_REG_SEL 77
-#define CK_TOP_A1SYS_SEL 78
-#define CK_TOP_CONN_MCUSYS_SEL 79
-#define CK_TOP_EIP_B_SEL 80
-#define CK_TOP_PCIE_PHY_SEL 81
-#define CK_TOP_USB3_PHY_SEL 82
-#define CK_TOP_F26M_SEL 83
-#define CK_TOP_AUD_L_SEL 84
-#define CK_TOP_A_TUNER_SEL 85
-#define CK_TOP_U2U3_SEL 86
-#define CK_TOP_U2U3_SYS_SEL 87
-#define CK_TOP_U2U3_XHCI_SEL 88
-#define CK_TOP_DA_U2_REFSEL 89
-#define CK_TOP_DA_U2_CK_1P_SEL 90
-#define CK_TOP_AP2CNN_HOST_SEL 91
-#define CLK_TOP_NR_CLK 92
+#define CLK_TOP_XTAL 0
+#define CLK_TOP_XTAL_D2 1
+#define CLK_TOP_RTC_32K 2
+#define CLK_TOP_RTC_32P7K 3
+/* #define CLK_TOP_A_TUNER 4 */
+#define CLK_TOP_MPLL_D2 4
+#define CLK_TOP_MPLL_D4 5
+#define CLK_TOP_MPLL_D8 6
+#define CLK_TOP_MPLL_D8_D2 7
+#define CLK_TOP_MPLL_D3_D2 8
+#define CLK_TOP_MMPLL_D2 9
+#define CLK_TOP_MMPLL_D4 10
+#define CLK_TOP_MMPLL_D8 11
+#define CLK_TOP_MMPLL_D8_D2 12
+#define CLK_TOP_MMPLL_D3_D8 13
+#define CLK_TOP_MMPLL_U2PHYD 14
+#define CLK_TOP_APLL2_D4 15
+#define CLK_TOP_NET1PLL_D4 16
+#define CLK_TOP_NET1PLL_D5 17
+#define CLK_TOP_NET1PLL_D5_D2 18
+#define CLK_TOP_NET1PLL_D5_D4 19
+#define CLK_TOP_NET1PLL_D8_D2 20
+#define CLK_TOP_NET1PLL_D8_D4 21
+#define CLK_TOP_NET2PLL_D4 22
+#define CLK_TOP_NET2PLL_D4_D2 23
+#define CLK_TOP_NET2PLL_D3_D2 24
+#define CLK_TOP_WEDMCUPLL_D5_D2 25
+#define CLK_TOP_NFI1X_SEL 26
+#define CLK_TOP_SPINFI_SEL 27
+#define CLK_TOP_SPI_SEL 28
+#define CLK_TOP_SPIM_MST_SEL 29
+#define CLK_TOP_UART_SEL 30
+#define CLK_TOP_PWM_SEL 31
+#define CLK_TOP_I2C_SEL 32
+#define CLK_TOP_PEXTP_TL_SEL 33
+#define CLK_TOP_EMMC_250M_SEL 34
+#define CLK_TOP_EMMC_416M_SEL 35
+#define CLK_TOP_F_26M_ADC_SEL 36
+#define CLK_TOP_DRAMC_SEL 37
+#define CLK_TOP_DRAMC_MD32_SEL 38
+#define CLK_TOP_SYSAXI_SEL 39
+#define CLK_TOP_SYSAPB_SEL 40
+#define CLK_TOP_ARM_DB_MAIN_SEL 41
+#define CLK_TOP_ARM_DB_JTSEL 42
+#define CLK_TOP_NETSYS_SEL 43
+#define CLK_TOP_NETSYS_500M_SEL 44
+#define CLK_TOP_NETSYS_MCU_SEL 45
+#define CLK_TOP_NETSYS_2X_SEL 46
+#define CLK_TOP_SGM_325M_SEL 47
+#define CLK_TOP_SGM_REG_SEL 48
+#define CLK_TOP_A1SYS_SEL 49
+#define CLK_TOP_CONN_MCUSYS_SEL 50
+#define CLK_TOP_EIP_B_SEL 51
+#define CLK_TOP_PCIE_PHY_SEL 52
+#define CLK_TOP_USB3_PHY_SEL 53
+#define CLK_TOP_F26M_SEL 54
+#define CLK_TOP_AUD_L_SEL 55
+#define CLK_TOP_A_TUNER_SEL 56
+#define CLK_TOP_U2U3_SEL 57
+#define CLK_TOP_U2U3_SYS_SEL 58
+#define CLK_TOP_U2U3_XHCI_SEL 59
+#define CLK_TOP_DA_U2_REFSEL 60
+#define CLK_TOP_DA_U2_CK_1P_SEL 61
+#define CLK_TOP_AP2CNN_HOST_SEL 62
+#define CLK_TOP_NR_CLK 63
-/*
- * INFRACFG_AO
- * clock muxes need to be append to infracfg domain, and clock gates
- * need to be keep in infracgh_ao domain
- */
+/* INFRACFG */
-#define CK_INFRA_UART0_SEL (0 + CLK_INFRA_NR_CLK)
-#define CK_INFRA_UART1_SEL (1 + CLK_INFRA_NR_CLK)
-#define CK_INFRA_UART2_SEL (2 + CLK_INFRA_NR_CLK)
-#define CK_INFRA_SPI0_SEL (3 + CLK_INFRA_NR_CLK)
-#define CK_INFRA_SPI1_SEL (4 + CLK_INFRA_NR_CLK)
-#define CK_INFRA_PWM1_SEL (5 + CLK_INFRA_NR_CLK)
-#define CK_INFRA_PWM2_SEL (6 + CLK_INFRA_NR_CLK)
-#define CK_INFRA_PWM_BSEL (7 + CLK_INFRA_NR_CLK)
-#define CK_INFRA_PCIE_SEL (8 + CLK_INFRA_NR_CLK)
-#define CK_INFRA_GPT_STA 0
-#define CK_INFRA_PWM_HCK 1
-#define CK_INFRA_PWM_STA 2
-#define CK_INFRA_PWM1_CK 3
-#define CK_INFRA_PWM2_CK 4
-#define CK_INFRA_CQ_DMA_CK 5
-#define CK_INFRA_EIP97_CK 6
-#define CK_INFRA_AUD_BUS_CK 7
-#define CK_INFRA_AUD_26M_CK 8
-#define CK_INFRA_AUD_L_CK 9
-#define CK_INFRA_AUD_AUD_CK 10
-#define CK_INFRA_AUD_EG2_CK 11
-#define CK_INFRA_DRAMC_26M_CK 12
-#define CK_INFRA_DBG_CK 13
-#define CK_INFRA_AP_DMA_CK 14
-#define CK_INFRA_SEJ_CK 15
-#define CK_INFRA_SEJ_13M_CK 16
-#define CK_INFRA_THERM_CK 17
-#define CK_INFRA_I2CO_CK 18
-#define CK_INFRA_TRNG_CK 19
-#define CK_INFRA_UART0_CK 20
-#define CK_INFRA_UART1_CK 21
-#define CK_INFRA_UART2_CK 22
-#define CK_INFRA_NFI1_CK 23
-#define CK_INFRA_SPINFI1_CK 24
-#define CK_INFRA_NFI_HCK_CK 25
-#define CK_INFRA_SPI0_CK 26
-#define CK_INFRA_SPI1_CK 27
-#define CK_INFRA_SPI0_HCK_CK 28
-#define CK_INFRA_SPI1_HCK_CK 29
-#define CK_INFRA_FRTC_CK 30
-#define CK_INFRA_MSDC_CK 31
-#define CK_INFRA_MSDC_HCK_CK 32
-#define CK_INFRA_MSDC_133M_CK 33
-#define CK_INFRA_MSDC_66M_CK 34
-#define CK_INFRA_ADC_26M_CK 35
-#define CK_INFRA_ADC_FRC_CK 36
-#define CK_INFRA_FBIST2FPC_CK 37
-#define CK_INFRA_IUSB_133_CK 38
-#define CK_INFRA_IUSB_66M_CK 39
-#define CK_INFRA_IUSB_SYS_CK 40
-#define CK_INFRA_IUSB_CK 41
-#define CK_INFRA_IPCIE_CK 42
-#define CK_INFRA_IPCIER_CK 43
-#define CK_INFRA_IPCIEB_CK 44
-#define CLK_INFRA_AO_NR_CLK 45
+#define CLK_INFRA_SYSAXI_D2 0
+#define CLK_INFRA_UART0_SEL 1
+#define CLK_INFRA_UART1_SEL 2
+#define CLK_INFRA_UART2_SEL 3
+#define CLK_INFRA_SPI0_SEL 4
+#define CLK_INFRA_SPI1_SEL 5
+#define CLK_INFRA_PWM1_SEL 6
+#define CLK_INFRA_PWM2_SEL 7
+#define CLK_INFRA_PWM_BSEL 8
+#define CLK_INFRA_PCIE_SEL 9
+#define CLK_INFRA_GPT_STA 10
+#define CLK_INFRA_PWM_HCK 11
+#define CLK_INFRA_PWM_STA 12
+#define CLK_INFRA_PWM1_CK 13
+#define CLK_INFRA_PWM2_CK 14
+#define CLK_INFRA_CQ_DMA_CK 15
+#define CLK_INFRA_EIP97_CK 16
+#define CLK_INFRA_AUD_BUS_CK 17
+#define CLK_INFRA_AUD_26M_CK 18
+#define CLK_INFRA_AUD_L_CK 19
+#define CLK_INFRA_AUD_AUD_CK 20
+#define CLK_INFRA_AUD_EG2_CK 21
+#define CLK_INFRA_DRAMC_26M_CK 22
+#define CLK_INFRA_DBG_CK 23
+#define CLK_INFRA_AP_DMA_CK 24
+#define CLK_INFRA_SEJ_CK 25
+#define CLK_INFRA_SEJ_13M_CK 26
+#define CLK_INFRA_THERM_CK 27
+#define CLK_INFRA_I2C0_CK 28
+#define CLK_INFRA_UART0_CK 29
+#define CLK_INFRA_UART1_CK 30
+#define CLK_INFRA_UART2_CK 31
+#define CLK_INFRA_NFI1_CK 32
+#define CLK_INFRA_SPINFI1_CK 33
+#define CLK_INFRA_NFI_HCK_CK 34
+#define CLK_INFRA_SPI0_CK 35
+#define CLK_INFRA_SPI1_CK 36
+#define CLK_INFRA_SPI0_HCK_CK 37
+#define CLK_INFRA_SPI1_HCK_CK 38
+#define CLK_INFRA_FRTC_CK 39
+#define CLK_INFRA_MSDC_CK 40
+#define CLK_INFRA_MSDC_HCK_CK 41
+#define CLK_INFRA_MSDC_133M_CK 42
+#define CLK_INFRA_MSDC_66M_CK 43
+#define CLK_INFRA_ADC_26M_CK 44
+#define CLK_INFRA_ADC_FRC_CK 45
+#define CLK_INFRA_FBIST2FPC_CK 46
+#define CLK_INFRA_IUSB_133_CK 47
+#define CLK_INFRA_IUSB_66M_CK 48
+#define CLK_INFRA_IUSB_SYS_CK 49
+#define CLK_INFRA_IUSB_CK 50
+#define CLK_INFRA_IPCIE_CK 51
+#define CLK_INFRA_IPCIE_PIPE_CK 52
+#define CLK_INFRA_IPCIER_CK 53
+#define CLK_INFRA_IPCIEB_CK 54
+#define CLK_INFRA_TRNG_CK 55
+#define CLK_INFRA_AO_NR_CLK 46
/* APMIXEDSYS */
-#define CK_APMIXED_ARMPLL 0
-#define CK_APMIXED_NET2PLL 1
-#define CK_APMIXED_MMPLL 2
-#define CK_APMIXED_SGMPLL 3
-#define CK_APMIXED_WEDMCUPLL 4
-#define CK_APMIXED_NET1PLL 5
-#define CK_APMIXED_MPLL 6
-#define CK_APMIXED_APLL2 7
+#define CLK_APMIXED_ARMPLL 0
+#define CLK_APMIXED_NET2PLL 1
+#define CLK_APMIXED_MMPLL 2
+#define CLK_APMIXED_SGMPLL 3
+#define CLK_APMIXED_WEDMCUPLL 4
+#define CLK_APMIXED_NET1PLL 5
+#define CLK_APMIXED_MPLL 6
+#define CLK_APMIXED_APLL2 7
#define CLK_APMIXED_NR_CLK 8
/* SGMIISYS_0 */
-#define CK_SGM0_TX_EN 0
-#define CK_SGM0_RX_EN 1
-#define CK_SGM0_CK0_EN 2
-#define CK_SGM0_CDR_CK0_EN 3
+#define CLK_SGM0_TX_EN 0
+#define CLK_SGM0_RX_EN 1
+#define CLK_SGM0_CK0_EN 2
+#define CLK_SGM0_CDR_CK0_EN 3
#define CLK_SGMII0_NR_CLK 4
/* SGMIISYS_1 */
-#define CK_SGM1_TX_EN 0
-#define CK_SGM1_RX_EN 1
-#define CK_SGM1_CK1_EN 2
-#define CK_SGM1_CDR_CK1_EN 3
+#define CLK_SGM1_TX_EN 0
+#define CLK_SGM1_RX_EN 1
+#define CLK_SGM1_CK1_EN 2
+#define CLK_SGM1_CDR_CK1_EN 3
#define CLK_SGMII1_NR_CLK 4
/* ETHSYS */
-#define CK_ETH_FE_EN 0
-#define CK_ETH_GP2_EN 1
-#define CK_ETH_GP1_EN 2
-#define CK_ETH_WOCPU1_EN 3
-#define CK_ETH_WOCPU0_EN 4
+#define CLK_ETH_FE_EN 0
+#define CLK_ETH_GP2_EN 1
+#define CLK_ETH_GP1_EN 2
+#define CLK_ETH_WOCPU1_EN 3
+#define CLK_ETH_WOCPU0_EN 4
#define CLK_ETH_NR_CLK 5
#endif
diff --git a/include/dt-bindings/clock/mt7988-clk.h b/include/dt-bindings/clock/mt7988-clk.h
index 5c21bf6..e6e6978 100644
--- a/include/dt-bindings/clock/mt7988-clk.h
+++ b/include/dt-bindings/clock/mt7988-clk.h
@@ -8,342 +8,257 @@
#ifndef _DT_BINDINGS_CLK_MT7988_H
#define _DT_BINDINGS_CLK_MT7988_H
-/* INFRACFG */
-/* mtk_fixed_factor */
-#define CK_INFRA_CK_F26M 0
-#define CK_INFRA_PWM_O 1
-#define CK_INFRA_PCIE_OCC_P0 2
-#define CK_INFRA_PCIE_OCC_P1 3
-#define CK_INFRA_PCIE_OCC_P2 4
-#define CK_INFRA_PCIE_OCC_P3 5
-#define CK_INFRA_133M_HCK 6
-#define CK_INFRA_133M_PHCK 7
-#define CK_INFRA_66M_PHCK 8
-#define CK_INFRA_FAUD_L_O 9
-#define CK_INFRA_FAUD_AUD_O 10
-#define CK_INFRA_FAUD_EG2_O 11
-#define CK_INFRA_I2C_O 12
-#define CK_INFRA_UART_O0 13
-#define CK_INFRA_UART_O1 14
-#define CK_INFRA_UART_O2 15
-#define CK_INFRA_NFI_O 16
-#define CK_INFRA_SPINFI_O 17
-#define CK_INFRA_SPI0_O 18
-#define CK_INFRA_SPI1_O 19
-#define CK_INFRA_LB_MUX_FRTC 20
-#define CK_INFRA_FRTC 21
-#define CK_INFRA_FMSDC400_O 22
-#define CK_INFRA_FMSDC2_HCK_OCC 23
-#define CK_INFRA_PERI_133M 24
-#define CK_INFRA_USB_O 25
-#define CK_INFRA_USB_O_P1 26
-#define CK_INFRA_USB_FRMCNT_O 27
-#define CK_INFRA_USB_FRMCNT_O_P1 28
-#define CK_INFRA_USB_XHCI_O 29
-#define CK_INFRA_USB_XHCI_O_P1 30
-#define CK_INFRA_USB_PIPE_O 31
-#define CK_INFRA_USB_PIPE_O_P1 32
-#define CK_INFRA_USB_UTMI_O 33
-#define CK_INFRA_USB_UTMI_O_P1 34
-#define CK_INFRA_PCIE_PIPE_OCC_P0 35
-#define CK_INFRA_PCIE_PIPE_OCC_P1 36
-#define CK_INFRA_PCIE_PIPE_OCC_P2 37
-#define CK_INFRA_PCIE_PIPE_OCC_P3 38
-#define CK_INFRA_F26M_O0 39
-#define CK_INFRA_F26M_O1 40
-#define CK_INFRA_133M_MCK 41
-#define CK_INFRA_66M_MCK 42
-#define CK_INFRA_PERI_66M_O 43
-#define CK_INFRA_USB_SYS_O 44
-#define CK_INFRA_USB_SYS_O_P1 45
-
/* INFRACFG_AO */
-#define GATE_OFFSET 65
/* mtk_mux */
-#define CK_INFRA_MUX_UART0_SEL 46 /* Linux CLK ID (0) */
-#define CK_INFRA_MUX_UART1_SEL 47 /* Linux CLK ID (1) */
-#define CK_INFRA_MUX_UART2_SEL 48 /* Linux CLK ID (2) */
-#define CK_INFRA_MUX_SPI0_SEL 49 /* Linux CLK ID (3) */
-#define CK_INFRA_MUX_SPI1_SEL 50 /* Linux CLK ID (4) */
-#define CK_INFRA_MUX_SPI2_SEL 51 /* Linux CLK ID (5) */
-#define CK_INFRA_PWM_SEL 52 /* Linux CLK ID (6) */
-#define CK_INFRA_PWM_CK1_SEL 53 /* Linux CLK ID (7) */
-#define CK_INFRA_PWM_CK2_SEL 54 /* Linux CLK ID (8) */
-#define CK_INFRA_PWM_CK3_SEL 55 /* Linux CLK ID (9) */
-#define CK_INFRA_PWM_CK4_SEL 56 /* Linux CLK ID (10) */
-#define CK_INFRA_PWM_CK5_SEL 57 /* Linux CLK ID (11) */
-#define CK_INFRA_PWM_CK6_SEL 58 /* Linux CLK ID (12) */
-#define CK_INFRA_PWM_CK7_SEL 59 /* Linux CLK ID (13) */
-#define CK_INFRA_PWM_CK8_SEL 60 /* Linux CLK ID (14) */
-#define CK_INFRA_PCIE_GFMUX_TL_O_P0_SEL 61 /* Linux CLK ID (15) */
-#define CK_INFRA_PCIE_GFMUX_TL_O_P1_SEL 62 /* Linux CLK ID (16) */
-#define CK_INFRA_PCIE_GFMUX_TL_O_P2_SEL 63 /* Linux CLK ID (17) */
-#define CK_INFRA_PCIE_GFMUX_TL_O_P3_SEL 64 /* Linux CLK ID (18) */
+#define CLK_INFRA_MUX_UART0_SEL 0
+#define CLK_INFRA_MUX_UART1_SEL 1
+#define CLK_INFRA_MUX_UART2_SEL 2
+#define CLK_INFRA_MUX_SPI0_SEL 3
+#define CLK_INFRA_MUX_SPI1_SEL 4
+#define CLK_INFRA_MUX_SPI2_SEL 5
+#define CLK_INFRA_PWM_SEL 6
+#define CLK_INFRA_PWM_CK1_SEL 7
+#define CLK_INFRA_PWM_CK2_SEL 8
+#define CLK_INFRA_PWM_CK3_SEL 9
+#define CLK_INFRA_PWM_CK4_SEL 10
+#define CLK_INFRA_PWM_CK5_SEL 11
+#define CLK_INFRA_PWM_CK6_SEL 12
+#define CLK_INFRA_PWM_CK7_SEL 13
+#define CLK_INFRA_PWM_CK8_SEL 14
+#define CLK_INFRA_PCIE_GFMUX_TL_O_P0_SEL 15
+#define CLK_INFRA_PCIE_GFMUX_TL_O_P1_SEL 16
+#define CLK_INFRA_PCIE_GFMUX_TL_O_P2_SEL 17
+#define CLK_INFRA_PCIE_GFMUX_TL_O_P3_SEL 18
+
+/* INFRACFG */
/* mtk_gate */
-#define CK_INFRA_66M_GPT_BCK (65 - GATE_OFFSET) /* Linux CLK ID (19) */
-#define CK_INFRA_66M_PWM_HCK (66 - GATE_OFFSET) /* Linux CLK ID (20) */
-#define CK_INFRA_66M_PWM_BCK (67 - GATE_OFFSET) /* Linux CLK ID (21) */
-#define CK_INFRA_66M_PWM_CK1 (68 - GATE_OFFSET) /* Linux CLK ID (22) */
-#define CK_INFRA_66M_PWM_CK2 (69 - GATE_OFFSET) /* Linux CLK ID (23) */
-#define CK_INFRA_66M_PWM_CK3 (70 - GATE_OFFSET) /* Linux CLK ID (24) */
-#define CK_INFRA_66M_PWM_CK4 (71 - GATE_OFFSET) /* Linux CLK ID (25) */
-#define CK_INFRA_66M_PWM_CK5 (72 - GATE_OFFSET) /* Linux CLK ID (26) */
-#define CK_INFRA_66M_PWM_CK6 (73 - GATE_OFFSET) /* Linux CLK ID (27) */
-#define CK_INFRA_66M_PWM_CK7 (74 - GATE_OFFSET) /* Linux CLK ID (28) */
-#define CK_INFRA_66M_PWM_CK8 (75 - GATE_OFFSET) /* Linux CLK ID (29) */
-#define CK_INFRA_133M_CQDMA_BCK (76 - GATE_OFFSET) /* Linux CLK ID (30) */
-#define CK_INFRA_66M_AUD_SLV_BCK (77 - GATE_OFFSET) /* Linux CLK ID (31) */
-#define CK_INFRA_AUD_26M (78 - GATE_OFFSET) /* Linux CLK ID (32) */
-#define CK_INFRA_AUD_L (79 - GATE_OFFSET) /* Linux CLK ID (33) */
-#define CK_INFRA_AUD_AUD (80 - GATE_OFFSET) /* Linux CLK ID (34) */
-#define CK_INFRA_AUD_EG2 (81 - GATE_OFFSET) /* Linux CLK ID (35) */
-#define CK_INFRA_DRAMC_F26M (82 - GATE_OFFSET) /* Linux CLK ID (36) */
-#define CK_INFRA_133M_DBG_ACKM (83 - GATE_OFFSET) /* Linux CLK ID (37) */
-#define CK_INFRA_66M_AP_DMA_BCK (84 - GATE_OFFSET) /* Linux CLK ID (38) */
-#define CK_INFRA_66M_SEJ_BCK (85 - GATE_OFFSET) /* Linux CLK ID (39) */
-#define CK_INFRA_PRE_CK_SEJ_F13M (86 - GATE_OFFSET) /* Linux CLK ID (40) */
-#define CK_INFRA_66M_TRNG (87 - GATE_OFFSET) /* Linux CLK ID (41) */
-#define CK_INFRA_26M_THERM_SYSTEM (88 - GATE_OFFSET) /* Linux CLK ID (42) */
-#define CK_INFRA_I2C_BCK (89 - GATE_OFFSET) /* Linux CLK ID (43) */
-#define CK_INFRA_66M_UART0_PCK (90 - GATE_OFFSET) /* Linux CLK ID (44) */
-#define CK_INFRA_66M_UART1_PCK (91 - GATE_OFFSET) /* Linux CLK ID (45) */
-#define CK_INFRA_66M_UART2_PCK (92 - GATE_OFFSET) /* Linux CLK ID (46) */
-#define CK_INFRA_52M_UART0_CK (93 - GATE_OFFSET) /* Linux CLK ID (47) */
-#define CK_INFRA_52M_UART1_CK (94 - GATE_OFFSET) /* Linux CLK ID (48) */
-#define CK_INFRA_52M_UART2_CK (95 - GATE_OFFSET) /* Linux CLK ID (49) */
-#define CK_INFRA_NFI (96 - GATE_OFFSET) /* Linux CLK ID (50) */
-#define CK_INFRA_SPINFI (97 - GATE_OFFSET) /* Linux CLK ID (51) */
-#define CK_INFRA_66M_NFI_HCK (98 - GATE_OFFSET) /* Linux CLK ID (52) */
-#define CK_INFRA_104M_SPI0 (99 - GATE_OFFSET) /* Linux CLK ID (53) */
-#define CK_INFRA_104M_SPI1 (100 - GATE_OFFSET) /* Linux CLK ID (54) */
-#define CK_INFRA_104M_SPI2_BCK (101 - GATE_OFFSET) /* Linux CLK ID (55) */
-#define CK_INFRA_66M_SPI0_HCK (102 - GATE_OFFSET) /* Linux CLK ID (56) */
-#define CK_INFRA_66M_SPI1_HCK (103 - GATE_OFFSET) /* Linux CLK ID (57) */
-#define CK_INFRA_66M_SPI2_HCK (104 - GATE_OFFSET) /* Linux CLK ID (58) */
-#define CK_INFRA_66M_FLASHIF_AXI (105 - GATE_OFFSET) /* Linux CLK ID (59) */
-#define CK_INFRA_RTC (106 - GATE_OFFSET) /* Linux CLK ID (60) */
-#define CK_INFRA_26M_ADC_BCK (107 - GATE_OFFSET) /* Linux CLK ID (61) */
-#define CK_INFRA_RC_ADC (108 - GATE_OFFSET) /* Linux CLK ID (62) */
-#define CK_INFRA_MSDC400 (109 - GATE_OFFSET) /* Linux CLK ID (63) */
-#define CK_INFRA_MSDC2_HCK (110 - GATE_OFFSET) /* Linux CLK ID (64) */
-#define CK_INFRA_133M_MSDC_0_HCK (111 - GATE_OFFSET) /* Linux CLK ID (65) */
-#define CK_INFRA_66M_MSDC_0_HCK (112 - GATE_OFFSET) /* Linux CLK ID (66) */
-#define CK_INFRA_133M_CPUM_BCK (113 - GATE_OFFSET) /* Linux CLK ID (67) */
-#define CK_INFRA_BIST2FPC (114 - GATE_OFFSET) /* Linux CLK ID (68) */
-#define CK_INFRA_I2C_X16W_MCK_CK_P1 (115 - GATE_OFFSET) /* Linux CLK ID (69) */
-#define CK_INFRA_I2C_X16W_PCK_CK_P1 (116 - GATE_OFFSET) /* Linux CLK ID (70) */
-#define CK_INFRA_133M_USB_HCK (117 - GATE_OFFSET) /* Linux CLK ID (71) */
-#define CK_INFRA_133M_USB_HCK_CK_P1 (118 - GATE_OFFSET) /* Linux CLK ID (72) */
-#define CK_INFRA_66M_USB_HCK (119 - GATE_OFFSET) /* Linux CLK ID (73) */
-#define CK_INFRA_66M_USB_HCK_CK_P1 (120 - GATE_OFFSET) /* Linux CLK ID (74) */
-#define CK_INFRA_USB_SYS (121 - GATE_OFFSET) /* Linux CLK ID (75) */
-#define CK_INFRA_USB_SYS_CK_P1 (122 - GATE_OFFSET) /* Linux CLK ID (76) */
-#define CK_INFRA_USB_REF (123 - GATE_OFFSET) /* Linux CLK ID (77) */
-#define CK_INFRA_USB_CK_P1 (124 - GATE_OFFSET) /* Linux CLK ID (78) */
-#define CK_INFRA_USB_FRMCNT (125 - GATE_OFFSET) /* Linux CLK ID (79) */
-#define CK_INFRA_USB_FRMCNT_CK_P1 (126 - GATE_OFFSET) /* Linux CLK ID (80) */
-#define CK_INFRA_USB_PIPE (127 - GATE_OFFSET) /* Linux CLK ID (81) */
-#define CK_INFRA_USB_PIPE_CK_P1 (128 - GATE_OFFSET) /* Linux CLK ID (82) */
-#define CK_INFRA_USB_UTMI (129 - GATE_OFFSET) /* Linux CLK ID (83) */
-#define CK_INFRA_USB_UTMI_CK_P1 (130 - GATE_OFFSET) /* Linux CLK ID (84) */
-#define CK_INFRA_USB_XHCI (131 - GATE_OFFSET) /* Linux CLK ID (85) */
-#define CK_INFRA_USB_XHCI_CK_P1 (132 - GATE_OFFSET) /* Linux CLK ID (86) */
-#define CK_INFRA_PCIE_GFMUX_TL_P0 (133 - GATE_OFFSET) /* Linux CLK ID (87) */
-#define CK_INFRA_PCIE_GFMUX_TL_P1 (134 - GATE_OFFSET) /* Linux CLK ID (88) */
-#define CK_INFRA_PCIE_GFMUX_TL_P2 (135 - GATE_OFFSET) /* Linux CLK ID (89) */
-#define CK_INFRA_PCIE_GFMUX_TL_P3 (136 - GATE_OFFSET) /* Linux CLK ID (90) */
-#define CK_INFRA_PCIE_PIPE_P0 (137 - GATE_OFFSET) /* Linux CLK ID (91) */
-#define CK_INFRA_PCIE_PIPE_P1 (138 - GATE_OFFSET) /* Linux CLK ID (92) */
-#define CK_INFRA_PCIE_PIPE_P2 (139 - GATE_OFFSET) /* Linux CLK ID (93) */
-#define CK_INFRA_PCIE_PIPE_P3 (140 - GATE_OFFSET) /* Linux CLK ID (94) */
-#define CK_INFRA_133M_PCIE_CK_P0 (141 - GATE_OFFSET) /* Linux CLK ID (95) */
-#define CK_INFRA_133M_PCIE_CK_P1 (142 - GATE_OFFSET) /* Linux CLK ID (96) */
-#define CK_INFRA_133M_PCIE_CK_P2 (143 - GATE_OFFSET) /* Linux CLK ID (97) */
-#define CK_INFRA_133M_PCIE_CK_P3 (144 - GATE_OFFSET) /* Linux CLK ID (98) */
-#define CK_INFRA_PCIE_PERI_26M_CK_P0 (145 - GATE_OFFSET) /* Linux CLK ID (99) */
-#define CK_INFRA_PCIE_PERI_26M_CK_P1 \
- (146 - GATE_OFFSET) /* Linux CLK ID (100) */
-#define CK_INFRA_PCIE_PERI_26M_CK_P2 \
- (147 - GATE_OFFSET) /* Linux CLK ID (101) */
-#define CK_INFRA_PCIE_PERI_26M_CK_P3 \
- (148 - GATE_OFFSET) /* Linux CLK ID (102) */
+#define CLK_INFRA_PCIE_PERI_26M_CK_P0 19
+#define CLK_INFRA_PCIE_PERI_26M_CK_P1 20
+#define CLK_INFRA_PCIE_PERI_26M_CK_P2 21
+#define CLK_INFRA_PCIE_PERI_26M_CK_P3 22
+#define CLK_INFRA_66M_GPT_BCK 23
+#define CLK_INFRA_66M_PWM_HCK 24
+#define CLK_INFRA_66M_PWM_BCK 25
+#define CLK_INFRA_66M_PWM_CK1 26
+#define CLK_INFRA_66M_PWM_CK2 27
+#define CLK_INFRA_66M_PWM_CK3 28
+#define CLK_INFRA_66M_PWM_CK4 29
+#define CLK_INFRA_66M_PWM_CK5 30
+#define CLK_INFRA_66M_PWM_CK6 31
+#define CLK_INFRA_66M_PWM_CK7 32
+#define CLK_INFRA_66M_PWM_CK8 33
+#define CLK_INFRA_133M_CQDMA_BCK 34
+#define CLK_INFRA_66M_AUD_SLV_BCK 35
+#define CLK_INFRA_AUD_26M 36
+#define CLK_INFRA_AUD_L 37
+#define CLK_INFRA_AUD_AUD 38
+#define CLK_INFRA_AUD_EG2 39
+#define CLK_INFRA_DRAMC_F26M 40
+#define CLK_INFRA_133M_DBG_ACKM 41
+#define CLK_INFRA_66M_AP_DMA_BCK 42
+#define CLK_INFRA_66M_SEJ_BCK 43
+#define CLK_INFRA_PRE_CK_SEJ_F13M 44
+/* #define CLK_INFRA_66M_TRNG 44 */
+#define CLK_INFRA_26M_THERM_SYSTEM 45
+#define CLK_INFRA_I2C_BCK 46
+/* #define CLK_INFRA_66M_UART0_PCK 46 */
+/* #define CLK_INFRA_66M_UART1_PCK 47 */
+/* #define CLK_INFRA_66M_UART2_PCK 48 */
+#define CLK_INFRA_52M_UART0_CK 47
+#define CLK_INFRA_52M_UART1_CK 48
+#define CLK_INFRA_52M_UART2_CK 49
+#define CLK_INFRA_NFI 50
+#define CLK_INFRA_SPINFI 51
+#define CLK_INFRA_66M_NFI_HCK 52
+#define CLK_INFRA_104M_SPI0 53
+#define CLK_INFRA_104M_SPI1 54
+#define CLK_INFRA_104M_SPI2_BCK 55
+#define CLK_INFRA_66M_SPI0_HCK 56
+#define CLK_INFRA_66M_SPI1_HCK 57
+#define CLK_INFRA_66M_SPI2_HCK 58
+#define CLK_INFRA_66M_FLASHIF_AXI 59
+#define CLK_INFRA_RTC 60
+#define CLK_INFRA_26M_ADC_BCK 61
+#define CLK_INFRA_RC_ADC 62
+#define CLK_INFRA_MSDC400 63
+#define CLK_INFRA_MSDC2_HCK 64
+#define CLK_INFRA_133M_MSDC_0_HCK 65
+#define CLK_INFRA_66M_MSDC_0_HCK 66
+#define CLK_INFRA_133M_CPUM_BCK 67
+#define CLK_INFRA_BIST2FPC 68
+#define CLK_INFRA_I2C_X16W_MCK_CK_P1 69
+#define CLK_INFRA_I2C_X16W_PCK_CK_P1 70
+#define CLK_INFRA_133M_USB_HCK 71
+#define CLK_INFRA_133M_USB_HCK_CK_P1 72
+#define CLK_INFRA_66M_USB_HCK 73
+#define CLK_INFRA_66M_USB_HCK_CK_P1 74
+#define CLK_INFRA_USB_SYS 75
+#define CLK_INFRA_USB_SYS_CK_P1 76
+#define CLK_INFRA_USB_REF 77
+#define CLK_INFRA_USB_CK_P1 78
+#define CLK_INFRA_USB_FRMCNT 79
+#define CLK_INFRA_USB_FRMCNT_CK_P1 80
+#define CLK_INFRA_USB_PIPE 81
+#define CLK_INFRA_USB_PIPE_CK_P1 82
+#define CLK_INFRA_USB_UTMI 83
+#define CLK_INFRA_USB_UTMI_CK_P1 84
+#define CLK_INFRA_USB_XHCI 85
+#define CLK_INFRA_USB_XHCI_CK_P1 86
+#define CLK_INFRA_PCIE_GFMUX_TL_P0 87
+#define CLK_INFRA_PCIE_GFMUX_TL_P1 88
+#define CLK_INFRA_PCIE_GFMUX_TL_P2 89
+#define CLK_INFRA_PCIE_GFMUX_TL_P3 90
+#define CLK_INFRA_PCIE_PIPE_P0 91
+#define CLK_INFRA_PCIE_PIPE_P1 92
+#define CLK_INFRA_PCIE_PIPE_P2 93
+#define CLK_INFRA_PCIE_PIPE_P3 94
+#define CLK_INFRA_133M_PCIE_CK_P0 95
+#define CLK_INFRA_133M_PCIE_CK_P1 96
+#define CLK_INFRA_133M_PCIE_CK_P2 97
+#define CLK_INFRA_133M_PCIE_CK_P3 98
/* TOPCKGEN */
+/* mtk_fixed_clk */
+#define CLK_TOP_XTAL 0
/* mtk_fixed_factor */
-#define CK_TOP_CB_CKSQ_40M 0 /* Linux CLK ID (74) */
-#define CK_TOP_CB_M_416M 1 /* Linux CLK ID (75) */
-#define CK_TOP_CB_M_D2 2 /* Linux CLK ID (76) */
-#define CK_TOP_M_D3_D2 3 /* Linux CLK ID (77) */
-#define CK_TOP_CB_M_D4 4 /* Linux CLK ID (78) */
-#define CK_TOP_CB_M_D8 5 /* Linux CLK ID (79) */
-#define CK_TOP_M_D8_D2 6 /* Linux CLK ID (80) */
-#define CK_TOP_CB_MM_720M 7 /* Linux CLK ID (81) */
-#define CK_TOP_CB_MM_D2 8 /* Linux CLK ID (82) */
-#define CK_TOP_CB_MM_D3_D5 9 /* Linux CLK ID (83) */
-#define CK_TOP_CB_MM_D4 10 /* Linux CLK ID (84) */
-#define CK_TOP_MM_D6_D2 11 /* Linux CLK ID (85) */
-#define CK_TOP_CB_MM_D8 12 /* Linux CLK ID (86) */
-#define CK_TOP_CB_APLL2_196M 13 /* Linux CLK ID (87) */
-#define CK_TOP_CB_APLL2_D4 14 /* Linux CLK ID (88) */
-#define CK_TOP_CB_NET1_D4 15 /* Linux CLK ID (89) */
-#define CK_TOP_CB_NET1_D5 16 /* Linux CLK ID (90) */
-#define CK_TOP_NET1_D5_D2 17 /* Linux CLK ID (91) */
-#define CK_TOP_NET1_D5_D4 18 /* Linux CLK ID (92) */
-#define CK_TOP_CB_NET1_D8 19 /* Linux CLK ID (93) */
-#define CK_TOP_NET1_D8_D2 20 /* Linux CLK ID (94) */
-#define CK_TOP_NET1_D8_D4 21 /* Linux CLK ID (95) */
-#define CK_TOP_NET1_D8_D8 22 /* Linux CLK ID (96) */
-#define CK_TOP_NET1_D8_D16 23 /* Linux CLK ID (97) */
-#define CK_TOP_CB_NET2_800M 24 /* Linux CLK ID (98) */
-#define CK_TOP_CB_NET2_D2 25 /* Linux CLK ID (99) */
-#define CK_TOP_CB_NET2_D4 26 /* Linux CLK ID (100) */
-#define CK_TOP_NET2_D4_D4 27 /* Linux CLK ID (101) */
-#define CK_TOP_NET2_D4_D8 28 /* Linux CLK ID (102) */
-#define CK_TOP_CB_NET2_D6 29 /* Linux CLK ID (103) */
-#define CK_TOP_CB_NET2_D8 30 /* Linux CLK ID (104) */
-#define CK_TOP_CB_WEDMCU_208M 31 /* Linux CLK ID (105) */
-#define CK_TOP_CB_SGM_325M 32 /* Linux CLK ID (106) */
-#define CK_TOP_CB_NETSYS_850M 33 /* Linux CLK ID (107) */
-#define CK_TOP_CB_MSDC_400M 34 /* Linux CLK ID (108) */
-#define CK_TOP_CKSQ_40M_D2 35 /* Linux CLK ID (109) */
-#define CK_TOP_CB_RTC_32K 36 /* Linux CLK ID (110) */
-#define CK_TOP_CB_RTC_32P7K 37 /* Linux CLK ID (111) */
-#define CK_TOP_INFRA_F32K 38 /* Linux CLK ID (112) */
-#define CK_TOP_CKSQ_SRC 39 /* Linux CLK ID (113) */
-#define CK_TOP_NETSYS_2X 40 /* Linux CLK ID (114) */
-#define CK_TOP_NETSYS_GSW 41 /* Linux CLK ID (115) */
-#define CK_TOP_NETSYS_WED_MCU 42 /* Linux CLK ID (116) */
-#define CK_TOP_EIP197 43 /* Linux CLK ID (117) */
-#define CK_TOP_EMMC_250M 44 /* Linux CLK ID (118) */
-#define CK_TOP_EMMC_400M 45 /* Linux CLK ID (119) */
-#define CK_TOP_SPI 46 /* Linux CLK ID (120) */
-#define CK_TOP_SPIM_MST 47 /* Linux CLK ID (121) */
-#define CK_TOP_NFI1X 48 /* Linux CLK ID (122) */
-#define CK_TOP_SPINFI_BCK 49 /* Linux CLK ID (123) */
-#define CK_TOP_I2C_BCK 50 /* Linux CLK ID (124) */
-#define CK_TOP_USB_SYS 51 /* Linux CLK ID (125) */
-#define CK_TOP_USB_SYS_P1 52 /* Linux CLK ID (126) */
-#define CK_TOP_USB_XHCI 53 /* Linux CLK ID (127) */
-#define CK_TOP_USB_XHCI_P1 54 /* Linux CLK ID (128) */
-#define CK_TOP_USB_FRMCNT 55 /* Linux CLK ID (129) */
-#define CK_TOP_USB_FRMCNT_P1 56 /* Linux CLK ID (130) */
-#define CK_TOP_AUD 57 /* Linux CLK ID (131) */
-#define CK_TOP_A1SYS 58 /* Linux CLK ID (132) */
-#define CK_TOP_AUD_L 59 /* Linux CLK ID (133) */
-#define CK_TOP_A_TUNER 60 /* Linux CLK ID (134) */
-#define CK_TOP_SYSAXI 61 /* Linux CLK ID (135) */
-#define CK_TOP_INFRA_F26M 62 /* Linux CLK ID (136) */
-#define CK_TOP_USB_REF 63 /* Linux CLK ID (137) */
-#define CK_TOP_USB_CK_P1 64 /* Linux CLK ID (138) */
+#define CLK_TOP_XTAL_D2 1
+#define CLK_TOP_RTC_32K 2
+#define CLK_TOP_RTC_32P7K 3
+#define CLK_TOP_MPLL_D2 4
+#define CLK_TOP_MPLL_D3_D2 5
+#define CLK_TOP_MPLL_D4 6
+#define CLK_TOP_MPLL_D8 7
+#define CLK_TOP_MPLL_D8_D2 8
+#define CLK_TOP_MMPLL_D2 9
+#define CLK_TOP_MMPLL_D3_D5 10
+#define CLK_TOP_MMPLL_D4 11
+#define CLK_TOP_MMPLL_D6_D2 12
+#define CLK_TOP_MMPLL_D8 13
+#define CLK_TOP_APLL2_D4 14
+#define CLK_TOP_NET1PLL_D4 15
+#define CLK_TOP_NET1PLL_D5 16
+#define CLK_TOP_NET1PLL_D5_D2 17
+#define CLK_TOP_NET1PLL_D5_D4 18
+#define CLK_TOP_NET1PLL_D8 19
+#define CLK_TOP_NET1PLL_D8_D2 20
+#define CLK_TOP_NET1PLL_D8_D4 21
+#define CLK_TOP_NET1PLL_D8_D8 22
+#define CLK_TOP_NET1PLL_D8_D16 23
+#define CLK_TOP_NET2PLL_D2 24
+#define CLK_TOP_NET2PLL_D4 25
+#define CLK_TOP_NET2PLL_D4_D4 26
+#define CLK_TOP_NET2PLL_D4_D8 27
+#define CLK_TOP_NET2PLL_D6 28
+#define CLK_TOP_NET2PLL_D8 29
/* mtk_mux */
-#define CK_TOP_NETSYS_SEL 65 /* Linux CLK ID (0) */
-#define CK_TOP_NETSYS_500M_SEL 66 /* Linux CLK ID (1) */
-#define CK_TOP_NETSYS_2X_SEL 67 /* Linux CLK ID (2) */
-#define CK_TOP_NETSYS_GSW_SEL 68 /* Linux CLK ID (3) */
-#define CK_TOP_ETH_GMII_SEL 69 /* Linux CLK ID (4) */
-#define CK_TOP_NETSYS_MCU_SEL 70 /* Linux CLK ID (5) */
-#define CK_TOP_NETSYS_PAO_2X_SEL 71 /* Linux CLK ID (6) */
-#define CK_TOP_EIP197_SEL 72 /* Linux CLK ID (7) */
-#define CK_TOP_AXI_INFRA_SEL 73 /* Linux CLK ID (8) */
-#define CK_TOP_UART_SEL 74 /* Linux CLK ID (9) */
-#define CK_TOP_EMMC_250M_SEL 75 /* Linux CLK ID (10) */
-#define CK_TOP_EMMC_400M_SEL 76 /* Linux CLK ID (11) */
-#define CK_TOP_SPI_SEL 77 /* Linux CLK ID (12) */
-#define CK_TOP_SPIM_MST_SEL 78 /* Linux CLK ID (13) */
-#define CK_TOP_NFI1X_SEL 79 /* Linux CLK ID (14) */
-#define CK_TOP_SPINFI_SEL 80 /* Linux CLK ID (15) */
-#define CK_TOP_PWM_SEL 81 /* Linux CLK ID (16) */
-#define CK_TOP_I2C_SEL 82 /* Linux CLK ID (17) */
-#define CK_TOP_PCIE_MBIST_250M_SEL 83 /* Linux CLK ID (18) */
-#define CK_TOP_PEXTP_TL_SEL 84 /* Linux CLK ID (19) */
-#define CK_TOP_PEXTP_TL_P1_SEL 85 /* Linux CLK ID (20) */
-#define CK_TOP_PEXTP_TL_P2_SEL 86 /* Linux CLK ID (21) */
-#define CK_TOP_PEXTP_TL_P3_SEL 87 /* Linux CLK ID (22) */
-#define CK_TOP_USB_SYS_SEL 88 /* Linux CLK ID (23) */
-#define CK_TOP_USB_SYS_P1_SEL 89 /* Linux CLK ID (24) */
-#define CK_TOP_USB_XHCI_SEL 90 /* Linux CLK ID (25) */
-#define CK_TOP_USB_XHCI_P1_SEL 91 /* Linux CLK ID (26) */
-#define CK_TOP_USB_FRMCNT_SEL 92 /* Linux CLK ID (27) */
-#define CK_TOP_USB_FRMCNT_P1_SEL 93 /* Linux CLK ID (28) */
-#define CK_TOP_AUD_SEL 94 /* Linux CLK ID (29) */
-#define CK_TOP_A1SYS_SEL 95 /* Linux CLK ID (30) */
-#define CK_TOP_AUD_L_SEL 96 /* Linux CLK ID (31) */
-#define CK_TOP_A_TUNER_SEL 97 /* Linux CLK ID (32) */
-#define CK_TOP_SSPXTP_SEL 98 /* Linux CLK ID (33) */
-#define CK_TOP_USB_PHY_SEL 99 /* Linux CLK ID (34) */
-#define CK_TOP_USXGMII_SBUS_0_SEL 100 /* Linux CLK ID (35) */
-#define CK_TOP_USXGMII_SBUS_1_SEL 101 /* Linux CLK ID (36) */
-#define CK_TOP_SGM_0_SEL 102 /* Linux CLK ID (37) */
-#define CK_TOP_SGM_SBUS_0_SEL 103 /* Linux CLK ID (38) */
-#define CK_TOP_SGM_1_SEL 104 /* Linux CLK ID (39) */
-#define CK_TOP_SGM_SBUS_1_SEL 105 /* Linux CLK ID (40) */
-#define CK_TOP_XFI_PHY_0_XTAL_SEL 106 /* Linux CLK ID (41) */
-#define CK_TOP_XFI_PHY_1_XTAL_SEL 107 /* Linux CLK ID (42) */
-#define CK_TOP_SYSAXI_SEL 108 /* Linux CLK ID (43) */
-#define CK_TOP_SYSAPB_SEL 109 /* Linux CLK ID (44) */
-#define CK_TOP_ETH_REFCK_50M_SEL 110 /* Linux CLK ID (45) */
-#define CK_TOP_ETH_SYS_200M_SEL 111 /* Linux CLK ID (46) */
-#define CK_TOP_ETH_SYS_SEL 112 /* Linux CLK ID (47) */
-#define CK_TOP_ETH_XGMII_SEL 113 /* Linux CLK ID (48) */
-#define CK_TOP_BUS_TOPS_SEL 114 /* Linux CLK ID (49) */
-#define CK_TOP_NPU_TOPS_SEL 115 /* Linux CLK ID (50) */
-#define CK_TOP_DRAMC_SEL 116 /* Linux CLK ID (51) */
-#define CK_TOP_DRAMC_MD32_SEL 117 /* Linux CLK ID (52) */
-#define CK_TOP_INFRA_F26M_SEL 118 /* Linux CLK ID (53) */
-#define CK_TOP_PEXTP_P0_SEL 119 /* Linux CLK ID (54) */
-#define CK_TOP_PEXTP_P1_SEL 120 /* Linux CLK ID (55) */
-#define CK_TOP_PEXTP_P2_SEL 121 /* Linux CLK ID (56) */
-#define CK_TOP_PEXTP_P3_SEL 122 /* Linux CLK ID (57) */
-#define CK_TOP_DA_XTP_GLB_P0_SEL 123 /* Linux CLK ID (58) */
-#define CK_TOP_DA_XTP_GLB_P1_SEL 124 /* Linux CLK ID (59) */
-#define CK_TOP_DA_XTP_GLB_P2_SEL 125 /* Linux CLK ID (60) */
-#define CK_TOP_DA_XTP_GLB_P3_SEL 126 /* Linux CLK ID (61) */
-#define CK_TOP_CKM_SEL 127 /* Linux CLK ID (62) */
-#define CK_TOP_DA_SELM_XTAL_SEL 128 /* Linux CLK ID (63) */
-#define CK_TOP_PEXTP_SEL 129 /* Linux CLK ID (64) */
-#define CK_TOP_TOPS_P2_26M_SEL 130 /* Linux CLK ID (65) */
-#define CK_TOP_MCUSYS_BACKUP_625M_SEL 131 /* Linux CLK ID (66) */
-#define CK_TOP_NETSYS_SYNC_250M_SEL 132 /* Linux CLK ID (67) */
-#define CK_TOP_MACSEC_SEL 133 /* Linux CLK ID (68) */
-#define CK_TOP_NETSYS_TOPS_400M_SEL 134 /* Linux CLK ID (69) */
-#define CK_TOP_NETSYS_PPEFB_250M_SEL 135 /* Linux CLK ID (70) */
-#define CK_TOP_NETSYS_WARP_SEL 136 /* Linux CLK ID (71) */
-#define CK_TOP_ETH_MII_SEL 137 /* Linux CLK ID (72) */
-#define CK_TOP_CK_NPU_SEL_CM_TOPS_SEL 138 /* Linux CLK ID (73) */
+#define CLK_TOP_NETSYS_SEL 30
+#define CLK_TOP_NETSYS_500M_SEL 31
+#define CLK_TOP_NETSYS_2X_SEL 32
+#define CLK_TOP_NETSYS_GSW_SEL 33
+#define CLK_TOP_ETH_GMII_SEL 34
+#define CLK_TOP_NETSYS_MCU_SEL 35
+#define CLK_TOP_NETSYS_PAO_2X_SEL 36
+#define CLK_TOP_EIP197_SEL 37
+#define CLK_TOP_AXI_INFRA_SEL 38
+#define CLK_TOP_UART_SEL 39
+#define CLK_TOP_EMMC_250M_SEL 40
+#define CLK_TOP_EMMC_400M_SEL 41
+#define CLK_TOP_SPI_SEL 42
+#define CLK_TOP_SPIM_MST_SEL 43
+#define CLK_TOP_NFI1X_SEL 44
+#define CLK_TOP_SPINFI_SEL 45
+#define CLK_TOP_PWM_SEL 46
+#define CLK_TOP_I2C_SEL 47
+#define CLK_TOP_PCIE_MBIST_250M_SEL 48
+#define CLK_TOP_PEXTP_TL_SEL 49
+#define CLK_TOP_PEXTP_TL_P1_SEL 50
+#define CLK_TOP_PEXTP_TL_P2_SEL 51
+#define CLK_TOP_PEXTP_TL_P3_SEL 52
+#define CLK_TOP_USB_SYS_SEL 53
+#define CLK_TOP_USB_SYS_P1_SEL 54
+#define CLK_TOP_USB_XHCI_SEL 55
+#define CLK_TOP_USB_XHCI_P1_SEL 56
+#define CLK_TOP_USB_FRMCNT_SEL 57
+#define CLK_TOP_USB_FRMCNT_P1_SEL 58
+#define CLK_TOP_AUD_SEL 59
+#define CLK_TOP_A1SYS_SEL 60
+#define CLK_TOP_AUD_L_SEL 61
+#define CLK_TOP_A_TUNER_SEL 62
+#define CLK_TOP_SSPXTP_SEL 63
+#define CLK_TOP_USB_PHY_SEL 64
+#define CLK_TOP_USXGMII_SBUS_0_SEL 65
+#define CLK_TOP_USXGMII_SBUS_1_SEL 66
+#define CLK_TOP_SGM_0_SEL 67
+#define CLK_TOP_SGM_SBUS_0_SEL 68
+#define CLK_TOP_SGM_1_SEL 69
+#define CLK_TOP_SGM_SBUS_1_SEL 70
+#define CLK_TOP_XFI_PHY_0_XTAL_SEL 71
+#define CLK_TOP_XFI_PHY_1_XTAL_SEL 72
+#define CLK_TOP_SYSAXI_SEL 73
+#define CLK_TOP_SYSAPB_SEL 74
+#define CLK_TOP_ETH_REFCK_50M_SEL 75
+#define CLK_TOP_ETH_SYS_200M_SEL 76
+#define CLK_TOP_ETH_SYS_SEL 77
+#define CLK_TOP_ETH_XGMII_SEL 78
+#define CLK_TOP_BUS_TOPS_SEL 79
+#define CLK_TOP_NPU_TOPS_SEL 80
+#define CLK_TOP_DRAMC_SEL 81
+#define CLK_TOP_DRAMC_MD32_SEL 82
+#define CLK_TOP_INFRA_F26M_SEL 83
+#define CLK_TOP_PEXTP_P0_SEL 84
+#define CLK_TOP_PEXTP_P1_SEL 85
+#define CLK_TOP_PEXTP_P2_SEL 86
+#define CLK_TOP_PEXTP_P3_SEL 87
+#define CLK_TOP_DA_XTP_GLB_P0_SEL 88
+#define CLK_TOP_DA_XTP_GLB_P1_SEL 89
+#define CLK_TOP_DA_XTP_GLB_P2_SEL 90
+#define CLK_TOP_DA_XTP_GLB_P3_SEL 91
+#define CLK_TOP_CKM_SEL 92
+#define CLK_TOP_DA_SEL 93
+#define CLK_TOP_PEXTP_SEL 94
+#define CLK_TOP_TOPS_P2_26M_SEL 95
+#define CLK_TOP_MCUSYS_BACKUP_625M_SEL 96
+#define CLK_TOP_NETSYS_SYNC_250M_SEL 97
+#define CLK_TOP_MACSEC_SEL 98
+#define CLK_TOP_NETSYS_TOPS_400M_SEL 99
+#define CLK_TOP_NETSYS_PPEFB_250M_SEL 100
+#define CLK_TOP_NETSYS_WARP_SEL 101
+#define CLK_TOP_ETH_MII_SEL 102
+#define CLK_TOP_NPU_SEL 103
/* APMIXEDSYS */
/* mtk_pll_data */
-#define CK_APMIXED_NETSYSPLL 0
-#define CK_APMIXED_MPLL 1
-#define CK_APMIXED_MMPLL 2
-#define CK_APMIXED_APLL2 3
-#define CK_APMIXED_NET1PLL 4
-#define CK_APMIXED_NET2PLL 5
-#define CK_APMIXED_WEDMCUPLL 6
-#define CK_APMIXED_SGMPLL 7
-#define CK_APMIXED_ARM_B 8
-#define CK_APMIXED_CCIPLL2_B 9
-#define CK_APMIXED_USXGMIIPLL 10
-#define CK_APMIXED_MSDCPLL 11
+#define CLK_APMIXED_NETSYSPLL 0
+#define CLK_APMIXED_MPLL 1
+#define CLK_APMIXED_MMPLL 2
+#define CLK_APMIXED_APLL2 3
+#define CLK_APMIXED_NET1PLL 4
+#define CLK_APMIXED_NET2PLL 5
+#define CLK_APMIXED_WEDMCUPLL 6
+#define CLK_APMIXED_SGMPLL 7
+#define CLK_APMIXED_ARM_B 8
+#define CLK_APMIXED_CCIPLL2_B 9
+#define CLK_APMIXED_USXGMIIPLL 10
+#define CLK_APMIXED_MSDCPLL 11
/* ETHSYS ETH DMA */
/* mtk_gate */
-#define CK_ETHDMA_FE_EN 0
+#define CLK_ETHDMA_FE_EN 0
/* SGMIISYS_0 */
/* mtk_gate */
-#define CK_SGM0_TX_EN 0
-#define CK_SGM0_RX_EN 1
+#define CLK_SGM0_TX_EN 0
+#define CLK_SGM0_RX_EN 1
/* SGMIISYS_1 */
/* mtk_gate */
-#define CK_SGM1_TX_EN 0
-#define CK_SGM1_RX_EN 1
+#define CLK_SGM1_TX_EN 0
+#define CLK_SGM1_RX_EN 1
/* ETHWARP */
/* mtk_gate */
-#define CK_ETHWARP_WOCPU2_EN 0
-#define CK_ETHWARP_WOCPU1_EN 1
-#define CK_ETHWARP_WOCPU0_EN 2
+#define CLK_ETHWARP_WOCPU2_EN 0
+#define CLK_ETHWARP_WOCPU1_EN 1
+#define CLK_ETHWARP_WOCPU0_EN 2
#endif /* _DT_BINDINGS_CLK_MT7988_H */
diff --git a/include/dwmmc.h b/include/dwmmc.h
index 136a95b..6edb9e1 100644
--- a/include/dwmmc.h
+++ b/include/dwmmc.h
@@ -15,170 +15,205 @@
#define DWMCI_CTRL 0x000
#define DWMCI_PWREN 0x004
#define DWMCI_CLKDIV 0x008
-#define DWMCI_CLKSRC 0x00C
+#define DWMCI_CLKSRC 0x00c
#define DWMCI_CLKENA 0x010
#define DWMCI_TMOUT 0x014
#define DWMCI_CTYPE 0x018
-#define DWMCI_BLKSIZ 0x01C
+#define DWMCI_BLKSIZ 0x01c
#define DWMCI_BYTCNT 0x020
#define DWMCI_INTMASK 0x024
#define DWMCI_CMDARG 0x028
-#define DWMCI_CMD 0x02C
+#define DWMCI_CMD 0x02c
#define DWMCI_RESP0 0x030
#define DWMCI_RESP1 0x034
#define DWMCI_RESP2 0x038
-#define DWMCI_RESP3 0x03C
+#define DWMCI_RESP3 0x03c
#define DWMCI_MINTSTS 0x040
#define DWMCI_RINTSTS 0x044
#define DWMCI_STATUS 0x048
-#define DWMCI_FIFOTH 0x04C
+#define DWMCI_FIFOTH 0x04c
#define DWMCI_CDETECT 0x050
#define DWMCI_WRTPRT 0x054
#define DWMCI_GPIO 0x058
-#define DWMCI_TCMCNT 0x05C
+#define DWMCI_TCMCNT 0x05c
#define DWMCI_TBBCNT 0x060
#define DWMCI_DEBNCE 0x064
#define DWMCI_USRID 0x068
-#define DWMCI_VERID 0x06C
+#define DWMCI_VERID 0x06c
#define DWMCI_HCON 0x070
#define DWMCI_UHS_REG 0x074
#define DWMCI_BMOD 0x080
#define DWMCI_PLDMND 0x084
+#define DWMCI_DATA 0x200
+/* Registers to support IDMAC 32-bit address mode */
#define DWMCI_DBADDR 0x088
-#define DWMCI_IDSTS 0x08C
+#define DWMCI_IDSTS 0x08c
#define DWMCI_IDINTEN 0x090
#define DWMCI_DSCADDR 0x094
#define DWMCI_BUFADDR 0x098
-#define DWMCI_DATA 0x200
+/* Registers to support IDMAC 64-bit address mode */
+#define DWMCI_DBADDRL 0x088
+#define DWMCI_DBADDRU 0x08c
+#define DWMCI_IDSTS64 0x090
+#define DWMCI_IDINTEN64 0x094
+#define DWMCI_DSCADDRL 0x098
+#define DWMCI_DSCADDRU 0x09c
+#define DWMCI_BUFADDRL 0x0a0
+#define DWMCI_BUFADDRU 0x0a4
/* Interrupt Mask register */
#define DWMCI_INTMSK_ALL 0xffffffff
-#define DWMCI_INTMSK_RE (1 << 1)
-#define DWMCI_INTMSK_CDONE (1 << 2)
-#define DWMCI_INTMSK_DTO (1 << 3)
-#define DWMCI_INTMSK_TXDR (1 << 4)
-#define DWMCI_INTMSK_RXDR (1 << 5)
-#define DWMCI_INTMSK_RCRC (1 << 6)
-#define DWMCI_INTMSK_DCRC (1 << 7)
-#define DWMCI_INTMSK_RTO (1 << 8)
-#define DWMCI_INTMSK_DRTO (1 << 9)
-#define DWMCI_INTMSK_HTO (1 << 10)
-#define DWMCI_INTMSK_FRUN (1 << 11)
-#define DWMCI_INTMSK_HLE (1 << 12)
-#define DWMCI_INTMSK_SBE (1 << 13)
-#define DWMCI_INTMSK_ACD (1 << 14)
-#define DWMCI_INTMSK_EBE (1 << 15)
+#define DWMCI_INTMSK_RE BIT(1)
+#define DWMCI_INTMSK_CDONE BIT(2)
+#define DWMCI_INTMSK_DTO BIT(3)
+#define DWMCI_INTMSK_TXDR BIT(4)
+#define DWMCI_INTMSK_RXDR BIT(5)
+#define DWMCI_INTMSK_RCRC BIT(6)
+#define DWMCI_INTMSK_DCRC BIT(7)
+#define DWMCI_INTMSK_RTO BIT(8)
+#define DWMCI_INTMSK_DRTO BIT(9)
+#define DWMCI_INTMSK_HTO BIT(10)
+#define DWMCI_INTMSK_FRUN BIT(11)
+#define DWMCI_INTMSK_HLE BIT(12)
+#define DWMCI_INTMSK_SBE BIT(13)
+#define DWMCI_INTMSK_ACD BIT(14)
+#define DWMCI_INTMSK_EBE BIT(15)
-/* Raw interrupt Regsiter */
-#define DWMCI_DATA_ERR (DWMCI_INTMSK_EBE | DWMCI_INTMSK_SBE | DWMCI_INTMSK_HLE |\
- DWMCI_INTMSK_FRUN | DWMCI_INTMSK_EBE | DWMCI_INTMSK_DCRC)
-#define DWMCI_DATA_TOUT (DWMCI_INTMSK_HTO | DWMCI_INTMSK_DRTO)
+/* Raw interrupt register */
+#define DWMCI_DATA_ERR (DWMCI_INTMSK_EBE | DWMCI_INTMSK_SBE | \
+ DWMCI_INTMSK_HLE | DWMCI_INTMSK_FRUN | \
+ DWMCI_INTMSK_EBE | DWMCI_INTMSK_DCRC)
+#define DWMCI_DATA_TOUT (DWMCI_INTMSK_HTO | DWMCI_INTMSK_DRTO)
+
/* CTRL register */
-#define DWMCI_CTRL_RESET (1 << 0)
-#define DWMCI_CTRL_FIFO_RESET (1 << 1)
-#define DWMCI_CTRL_DMA_RESET (1 << 2)
-#define DWMCI_DMA_EN (1 << 5)
-#define DWMCI_CTRL_SEND_AS_CCSD (1 << 10)
-#define DWMCI_IDMAC_EN (1 << 25)
+#define DWMCI_CTRL_RESET BIT(0)
+#define DWMCI_CTRL_FIFO_RESET BIT(1)
+#define DWMCI_CTRL_DMA_RESET BIT(2)
+#define DWMCI_DMA_EN BIT(5)
+#define DWMCI_CTRL_SEND_AS_CCSD BIT(10)
+#define DWMCI_IDMAC_EN BIT(25)
#define DWMCI_RESET_ALL (DWMCI_CTRL_RESET | DWMCI_CTRL_FIFO_RESET |\
DWMCI_CTRL_DMA_RESET)
/* CMD register */
-#define DWMCI_CMD_RESP_EXP (1 << 6)
-#define DWMCI_CMD_RESP_LENGTH (1 << 7)
-#define DWMCI_CMD_CHECK_CRC (1 << 8)
-#define DWMCI_CMD_DATA_EXP (1 << 9)
-#define DWMCI_CMD_RW (1 << 10)
-#define DWMCI_CMD_SEND_STOP (1 << 12)
-#define DWMCI_CMD_ABORT_STOP (1 << 14)
-#define DWMCI_CMD_PRV_DAT_WAIT (1 << 13)
-#define DWMCI_CMD_UPD_CLK (1 << 21)
-#define DWMCI_CMD_USE_HOLD_REG (1 << 29)
-#define DWMCI_CMD_START (1 << 31)
+#define DWMCI_CMD_RESP_EXP BIT(6)
+#define DWMCI_CMD_RESP_LENGTH BIT(7)
+#define DWMCI_CMD_CHECK_CRC BIT(8)
+#define DWMCI_CMD_DATA_EXP BIT(9)
+#define DWMCI_CMD_RW BIT(10)
+#define DWMCI_CMD_SEND_STOP BIT(12)
+#define DWMCI_CMD_ABORT_STOP BIT(14)
+#define DWMCI_CMD_PRV_DAT_WAIT BIT(13)
+#define DWMCI_CMD_UPD_CLK BIT(21)
+#define DWMCI_CMD_USE_HOLD_REG BIT(29)
+#define DWMCI_CMD_START BIT(31)
/* CLKENA register */
-#define DWMCI_CLKEN_ENABLE (1 << 0)
-#define DWMCI_CLKEN_LOW_PWR (1 << 16)
+#define DWMCI_CLKEN_ENABLE BIT(0)
+#define DWMCI_CLKEN_LOW_PWR BIT(16)
-/* Card-type registe */
+/* Card type register */
#define DWMCI_CTYPE_1BIT 0
-#define DWMCI_CTYPE_4BIT (1 << 0)
-#define DWMCI_CTYPE_8BIT (1 << 16)
+#define DWMCI_CTYPE_4BIT BIT(0)
+#define DWMCI_CTYPE_8BIT BIT(16)
-/* Status Register */
-#define DWMCI_FIFO_EMPTY (1 << 2)
-#define DWMCI_FIFO_FULL (1 << 3)
-#define DWMCI_BUSY (1 << 9)
+/* Status register */
+#define DWMCI_FIFO_EMPTY BIT(2)
+#define DWMCI_FIFO_FULL BIT(3)
+#define DWMCI_BUSY BIT(9)
#define DWMCI_FIFO_MASK 0x1fff
#define DWMCI_FIFO_SHIFT 17
-/* FIFOTH Register */
+/* FIFOTH register */
#define MSIZE(x) ((x) << 28)
#define RX_WMARK(x) ((x) << 16)
#define TX_WMARK(x) (x)
#define RX_WMARK_SHIFT 16
#define RX_WMARK_MASK (0xfff << RX_WMARK_SHIFT)
-#define DWMCI_IDMAC_OWN (1 << 31)
-#define DWMCI_IDMAC_CH (1 << 4)
-#define DWMCI_IDMAC_FS (1 << 3)
-#define DWMCI_IDMAC_LD (1 << 2)
+#define DWMCI_IDMAC_OWN BIT(31)
+#define DWMCI_IDMAC_CH BIT(4)
+#define DWMCI_IDMAC_FS BIT(3)
+#define DWMCI_IDMAC_LD BIT(2)
-/* Bus Mode Register */
-#define DWMCI_BMOD_IDMAC_RESET (1 << 0)
-#define DWMCI_BMOD_IDMAC_FB (1 << 1)
-#define DWMCI_BMOD_IDMAC_EN (1 << 7)
+/* Bus Mode register */
+#define DWMCI_BMOD_IDMAC_RESET BIT(0)
+#define DWMCI_BMOD_IDMAC_FB BIT(1)
+#define DWMCI_BMOD_IDMAC_EN BIT(7)
/* UHS register */
-#define DWMCI_DDR_MODE (1 << 16)
+#define DWMCI_DDR_MODE BIT(16)
/* Internal IDMAC interrupt defines */
-#define DWMCI_IDINTEN_RI BIT(1)
-#define DWMCI_IDINTEN_TI BIT(0)
+#define DWMCI_IDINTEN_RI BIT(1)
+#define DWMCI_IDINTEN_TI BIT(0)
+#define DWMCI_IDINTEN_MASK (DWMCI_IDINTEN_TI | DWMCI_IDINTEN_RI)
-#define DWMCI_IDINTEN_MASK (DWMCI_IDINTEN_TI | \
- DWMCI_IDINTEN_RI)
-
-/* quirks */
-#define DWMCI_QUIRK_DISABLE_SMU (1 << 0)
+/**
+ * struct dwmci_idmac_regs - Offsets of IDMAC registers
+ *
+ * @dbaddrl: Descriptor base address, lower 32 bits
+ * @dbaddru: Descriptor base address, upper 32 bits
+ * @idsts: Internal DMA status
+ * @idinten: Internal DMA interrupt enable
+ * @dscaddrl: IDMAC descriptor address, lower 32 bits
+ * @dscaddru: IDMAC descriptor address, upper 32 bits
+ * @bufaddrl: Current data buffer address, lower 32 bits
+ * @bufaddru: Current data buffer address, upper 32 bits
+ */
+struct dwmci_idmac_regs {
+ u32 dbaddrl;
+ u32 dbaddru;
+ u32 idsts;
+ u32 idinten;
+ u32 dscaddrl;
+ u32 dscaddru;
+ u32 bufaddrl;
+ u32 bufaddru;
+};
/**
* struct dwmci_host - Information about a designware MMC host
*
* @name: Device name
* @ioaddr: Base I/O address of controller
- * @quirks: Quick flags - see DWMCI_QUIRK_...
* @caps: Capabilities - see MMC_MODE_...
+ * @clock: Current clock frequency (after internal divider), Hz
* @bus_hz: Bus speed in Hz, if @get_mmc_clk() is NULL
- * @div: Arbitrary clock divider value for use by controller
* @dev_index: Arbitrary device index for use by controller
* @dev_id: Arbitrary device ID for use by controller
* @buswidth: Bus width in bits (8 or 4)
- * @fifoth_val: Value for FIFOTH register (or 0 to leave unset)
+ * @fifo_depth: Depth of FIFO, bytes (or 0 for automatic detection)
* @mmc: Pointer to generic MMC structure for this device
* @priv: Private pointer for use by controller
+ * @clksel: (Optional) Platform function to run when speed/width is changed
+ * @board_init: (Optional) Platform function to run on init
+ * @cfg: Internal MMC configuration, for !CONFIG_BLK cases
+ * @fifo_mode: Use FIFO mode (not DMA) to read and write data
+ * @dma_64bit_address: Whether DMA supports 64-bit address mode or not
+ * @regs: Registers that can vary for different DW MMC block versions
*/
struct dwmci_host {
const char *name;
void *ioaddr;
- unsigned int quirks;
unsigned int caps;
- unsigned int version;
unsigned int clock;
unsigned int bus_hz;
- unsigned int div;
int dev_index;
int dev_id;
int buswidth;
- u32 fifoth_val;
+ u32 fifo_depth;
struct mmc *mmc;
void *priv;
int (*clksel)(struct dwmci_host *host);
void (*board_init)(struct dwmci_host *host);
-
/**
- * Get / set a particular MMC clock frequency
+ * @get_mmc_clk: (Optional) Platform function to get/set a particular
+ * MMC clock frequency
+ *
+ * @host: DWMMC host
+ * @freq: Frequency the host is trying to achieve
*
* This is used to request the current clock frequency of the clock
* that drives the DWMMC peripheral. The caller will then use this
@@ -186,26 +221,18 @@
* required MMC bus clock frequency. If you want to handle the
* clock external to DWMMC, use @freq to select the frequency and
* return that value too. Then DWMMC will put itself in bypass mode.
- *
- * @host: DWMMC host
- * @freq: Frequency the host is trying to achieve
*/
unsigned int (*get_mmc_clk)(struct dwmci_host *host, uint freq);
+
#ifndef CONFIG_BLK
struct mmc_config cfg;
#endif
- /* use fifo mode to read and write data */
bool fifo_mode;
+ bool dma_64bit_address;
+ const struct dwmci_idmac_regs *regs;
};
-struct dwmci_idmac {
- u32 flags;
- u32 cnt;
- u32 addr;
- u32 next_addr;
-} __aligned(ARCH_DMA_MINALIGN);
-
static inline void dwmci_writel(struct dwmci_host *host, int reg, u32 val)
{
writel(val, host->ioaddr + reg);
@@ -220,6 +247,7 @@
{
writeb(val, host->ioaddr + reg);
}
+
static inline u32 dwmci_readl(struct dwmci_host *host, int reg)
{
return readl(host->ioaddr + reg);
@@ -236,8 +264,13 @@
}
#ifdef CONFIG_BLK
+
/**
* dwmci_setup_cfg() - Set up the configuration for DWMMC
+ * @cfg: Configuration structure to fill in (generally &plat->mmc)
+ * @host: DWMMC host
+ * @max_clk: Maximum supported clock speed in Hz (e.g. 150000000)
+ * @min_clk: Minimum supported clock speed in Hz (e.g. 400000)
*
* This is used to set up a DWMMC device when you are using CONFIG_BLK.
*
@@ -262,44 +295,41 @@
* struct rockchip_mmc_plat *plat = dev_get_plat(dev);
*
* See rockchip_dw_mmc.c for an example.
- *
- * @cfg: Configuration structure to fill in (generally &plat->mmc)
- * @host: DWMMC host
- * @max_clk: Maximum supported clock speed in HZ (e.g. 150000000)
- * @min_clk: Minimum supported clock speed in HZ (e.g. 400000)
*/
void dwmci_setup_cfg(struct mmc_config *cfg, struct dwmci_host *host,
- u32 max_clk, u32 min_clk);
+ u32 max_clk, u32 min_clk);
/**
* dwmci_bind() - Set up a new MMC block device
+ * @dev: Device to set up
+ * @mmc: Pointer to mmc structure (normally &plat->mmc)
+ * @cfg: Empty configuration structure (generally &plat->cfg). This is
+ * normally all zeroes at this point. The only purpose of passing
+ * this in is to set mmc->cfg to it.
*
* This is used to set up a DWMMC block device when you are using CONFIG_BLK.
* It should be called from your driver's bind() method.
*
* See rockchip_dw_mmc.c for an example.
*
- * @dev: Device to set up
- * @mmc: Pointer to mmc structure (normally &plat->mmc)
- * @cfg: Empty configuration structure (generally &plat->cfg). This is
- * normally all zeroes at this point. The only purpose of passing
- * this in is to set mmc->cfg to it.
* Return: 0 if OK, -ve if the block device could not be created
*/
int dwmci_bind(struct udevice *dev, struct mmc *mmc, struct mmc_config *cfg);
#else
+
/**
* add_dwmci() - Add a new DWMMC interface
+ * @host: DWMMC host structure
+ * @max_clk: Maximum supported clock speed in Hz (e.g. 150000000)
+ * @min_clk: Minimum supported clock speed in Hz (e.g. 400000)
*
* This is used when you are not using CONFIG_BLK. Convert your driver over!
*
- * @host: DWMMC host structure
- * @max_clk: Maximum supported clock speed in HZ (e.g. 150000000)
- * @min_clk: Minimum supported clock speed in HZ (e.g. 400000)
* Return: 0 if OK, -ve on error
*/
int add_dwmci(struct dwmci_host *host, u32 max_clk, u32 min_clk);
+
#endif /* !CONFIG_BLK */
#ifdef CONFIG_DM_MMC
diff --git a/include/env_default.h b/include/env_default.h
index 076ffdd..aa3dd40 100644
--- a/include/env_default.h
+++ b/include/env_default.h
@@ -82,9 +82,6 @@
#ifdef CONFIG_SYS_LOAD_ADDR
"loadaddr=" __stringify(CONFIG_SYS_LOAD_ADDR)"\0"
#endif
-#if defined(CONFIG_PCI_BOOTDELAY) && (CONFIG_PCI_BOOTDELAY > 0)
- "pcidelay=" __stringify(CONFIG_PCI_BOOTDELAY)"\0"
-#endif
#ifdef CONFIG_ENV_VARS_UBOOT_CONFIG
"arch=" CONFIG_SYS_ARCH "\0"
#ifdef CONFIG_SYS_CPU
diff --git a/include/env_internal.h b/include/env_internal.h
index 0a267e3..c1c0727 100644
--- a/include/env_internal.h
+++ b/include/env_internal.h
@@ -100,6 +100,7 @@
#include <env_flags.h>
#include <search.h>
+/* this is stored as bits in gd->env_has_init so is limited to 16 entries */
enum env_location {
ENVL_UNKNOWN,
ENVL_EEPROM,
diff --git a/include/ext4fs.h b/include/ext4fs.h
index d96edfd..41f9eb8 100644
--- a/include/ext4fs.h
+++ b/include/ext4fs.h
@@ -34,12 +34,63 @@
#define EXT4_TOPDIR_FL 0x00020000 /* Top of directory hierarchies*/
#define EXT4_EXTENTS_FL 0x00080000 /* Inode uses extents */
#define EXT4_EXT_MAGIC 0xf30a
-#define EXT4_FEATURE_RO_COMPAT_GDT_CSUM 0x0010
+
+#define EXT4_FEATURE_RO_COMPAT_SPARSE_SUPER 0x0001
+#define EXT4_FEATURE_RO_COMPAT_LARGE_FILE 0x0002
+#define EXT4_FEATURE_RO_COMPAT_BTREE_DIR 0x0004
+#define EXT4_FEATURE_RO_COMPAT_HUGE_FILE 0x0008
+#define EXT4_FEATURE_RO_COMPAT_GDT_CSUM 0x0010
+#define EXT4_FEATURE_RO_COMPAT_DIR_NLINK 0x0020
+#define EXT4_FEATURE_RO_COMPAT_EXTRA_ISIZE 0x0040
+#define EXT4_FEATURE_RO_COMPAT_QUOTA 0x0100
+#define EXT4_FEATURE_RO_COMPAT_BIGALLOC 0x0200
#define EXT4_FEATURE_RO_COMPAT_METADATA_CSUM 0x0400
+
+#define EXT4_FEATURE_INCOMPAT_FILETYPE 0x0002
+#define EXT4_FEATURE_INCOMPAT_RECOVER 0x0004
#define EXT4_FEATURE_INCOMPAT_EXTENTS 0x0040
#define EXT4_FEATURE_INCOMPAT_64BIT 0x0080
+#define EXT4_FEATURE_INCOMPAT_MMP 0x0100
+#define EXT4_FEATURE_INCOMPAT_FLEX_BG 0x0200
+#define EXT4_FEATURE_INCOMPAT_CSUM_SEED 0x2000
+#define EXT4_FEATURE_INCOMPAT_ENCRYPT 0x10000
+
#define EXT4_INDIRECT_BLOCKS 12
+/*
+ * Incompat features supported by this implementation.
+ */
+#define EXT4_FEATURE_INCOMPAT_SUPP (EXT4_FEATURE_INCOMPAT_FILETYPE | \
+ EXT4_FEATURE_INCOMPAT_RECOVER | \
+ EXT4_FEATURE_INCOMPAT_EXTENTS | \
+ EXT4_FEATURE_INCOMPAT_64BIT | \
+ EXT4_FEATURE_INCOMPAT_FLEX_BG)
+
+/*
+ * Incompat features supported by this implementation only in a lazy
+ * way, good enough for reading files.
+ *
+ * - Multi mount protection (mmp) is not supported, but for read-only
+ * we get away with it.
+ * - Same for metadata_csum_seed and metadata_csum.
+ * - The implementation has also no clue about fscrypt, but it can read
+ * unencrypted files. Reading encrypted files will read garbage.
+ */
+#define EXT4_FEATURE_INCOMPAT_SUPP_LAZY_RO (EXT4_FEATURE_INCOMPAT_MMP | \
+ EXT4_FEATURE_INCOMPAT_CSUM_SEED | \
+ EXT4_FEATURE_INCOMPAT_ENCRYPT)
+
+/*
+ * Read-only compat features we support.
+ * If unknown ro compat features are detected, writing to the fs is denied.
+ */
+#define EXT4_FEATURE_RO_COMPAT_SUPP (EXT4_FEATURE_RO_COMPAT_SPARSE_SUPER | \
+ EXT4_FEATURE_RO_COMPAT_LARGE_FILE | \
+ EXT4_FEATURE_RO_COMPAT_HUGE_FILE | \
+ EXT4_FEATURE_RO_COMPAT_GDT_CSUM | \
+ EXT4_FEATURE_RO_COMPAT_DIR_NLINK | \
+ EXT4_FEATURE_RO_COMPAT_EXTRA_ISIZE)
+
#define EXT4_BG_INODE_UNINIT 0x0001
#define EXT4_BG_BLOCK_UNINIT 0x0002
#define EXT4_BG_INODE_ZEROED 0x0004
diff --git a/include/handoff.h b/include/handoff.h
index c0ae7b1..0072ea8 100644
--- a/include/handoff.h
+++ b/include/handoff.h
@@ -32,6 +32,13 @@
void handoff_load_dram_banks(struct spl_handoff *ho);
/**
+ * handoff_get() - Get the SPL handoff information
+ *
+ * Return: Pointer to SPL handoff if received, else NULL
+ */
+struct spl_handoff *handoff_get(void);
+
+/**
* handoff_arch_save() - Save arch-specific info into the handoff area
*
* This is defined to an empty function by default, but arch-specific code can
diff --git a/include/i2c.h b/include/i2c.h
index 4e59009..91917f5 100644
--- a/include/i2c.h
+++ b/include/i2c.h
@@ -645,20 +645,8 @@
*/
#define I2C_RXTX_LEN 128 /* maximum tx/rx buffer length */
-#if !defined(CFG_SYS_I2C_MAX_HOPS)
/* no muxes used bus = i2c adapters */
-#define CFG_SYS_I2C_DIRECT_BUS 1
-#define CFG_SYS_I2C_MAX_HOPS 0
#define CFG_SYS_NUM_I2C_BUSES ll_entry_count(struct i2c_adapter, i2c)
-#else
-/* we use i2c muxes */
-#undef CFG_SYS_I2C_DIRECT_BUS
-#endif
-
-/* define the I2C bus number for RTC and DTT if not already done */
-#if !defined(CFG_SYS_RTC_BUS_NUM)
-#define CFG_SYS_RTC_BUS_NUM 0
-#endif
struct i2c_adapter {
void (*init)(struct i2c_adapter *adap, int speed,
@@ -703,48 +691,13 @@
struct i2c_adapter *i2c_get_adapter(int index);
-#ifndef CFG_SYS_I2C_DIRECT_BUS
-struct i2c_mux {
- int id;
- char name[16];
-};
-
-struct i2c_next_hop {
- struct i2c_mux mux;
- uint8_t chip;
- uint8_t channel;
-};
-
-struct i2c_bus_hose {
- int adapter;
- struct i2c_next_hop next_hop[CFG_SYS_I2C_MAX_HOPS];
-};
-#define I2C_NULL_HOP {{-1, ""}, 0, 0}
-extern struct i2c_bus_hose i2c_bus[];
-
-#define I2C_ADAPTER(bus) i2c_bus[bus].adapter
-#else
#define I2C_ADAPTER(bus) bus
-#endif
#define I2C_BUS gd->cur_i2c_bus
#define I2C_ADAP_NR(bus) i2c_get_adapter(I2C_ADAPTER(bus))
#define I2C_ADAP I2C_ADAP_NR(gd->cur_i2c_bus)
#define I2C_ADAP_HWNR (I2C_ADAP->hwadapnr)
-#ifndef CFG_SYS_I2C_DIRECT_BUS
-#define I2C_MUX_PCA9540_ID 1
-#define I2C_MUX_PCA9540 {I2C_MUX_PCA9540_ID, "PCA9540B"}
-#define I2C_MUX_PCA9542_ID 2
-#define I2C_MUX_PCA9542 {I2C_MUX_PCA9542_ID, "PCA9542A"}
-#define I2C_MUX_PCA9544_ID 3
-#define I2C_MUX_PCA9544 {I2C_MUX_PCA9544_ID, "PCA9544A"}
-#define I2C_MUX_PCA9547_ID 4
-#define I2C_MUX_PCA9547 {I2C_MUX_PCA9547_ID, "PCA9547A"}
-#define I2C_MUX_PCA9548_ID 5
-#define I2C_MUX_PCA9548 {I2C_MUX_PCA9548_ID, "PCA9548"}
-#endif
-
#ifndef I2C_SOFT_DECLARATIONS
# if (defined(CONFIG_AT91RM9200) || \
defined(CONFIG_AT91SAM9260) || defined(CONFIG_AT91SAM9261) || \
@@ -938,66 +891,6 @@
unsigned int i2c_get_bus_speed(void);
#endif /* CONFIG_SYS_I2C_LEGACY */
-/*
- * only for backwardcompatibility, should go away if we switched
- * completely to new multibus support.
- */
-#if CONFIG_IS_ENABLED(SYS_I2C_LEGACY) || defined(CFG_I2C_MULTI_BUS)
-# if !defined(CFG_SYS_MAX_I2C_BUS)
-# define CFG_SYS_MAX_I2C_BUS 2
-# endif
-# define I2C_MULTI_BUS 1
-#else
-# define CFG_SYS_MAX_I2C_BUS 1
-# define I2C_MULTI_BUS 0
-#endif
-
-/* NOTE: These two functions MUST be always_inline to avoid code growth! */
-static inline unsigned int I2C_GET_BUS(void) __attribute__((always_inline));
-static inline unsigned int I2C_GET_BUS(void)
-{
- return I2C_MULTI_BUS ? i2c_get_bus_num() : 0;
-}
-
-static inline void I2C_SET_BUS(unsigned int bus) __attribute__((always_inline));
-static inline void I2C_SET_BUS(unsigned int bus)
-{
- if (I2C_MULTI_BUS)
- i2c_set_bus_num(bus);
-}
-
-/* Multi I2C definitions */
-enum {
- I2C_0, I2C_1, I2C_2, I2C_3, I2C_4, I2C_5, I2C_6, I2C_7,
- I2C_8, I2C_9, I2C_10,
-};
-
-/**
- * Get FDT values for i2c bus.
- *
- * @param blob Device tree blbo
- * Return: the number of I2C bus
- */
-void board_i2c_init(const void *blob);
-
-/**
- * Find the I2C bus number by given a FDT I2C node.
- *
- * @param blob Device tree blbo
- * @param node FDT I2C node to find
- * Return: the number of I2C bus (zero based), or -1 on error
- */
-int i2c_get_bus_num_fdt(int node);
-
-/**
- * Reset the I2C bus represented by the given a FDT I2C node.
- *
- * @param blob Device tree blbo
- * @param node FDT I2C node to find
- * Return: 0 if port was reset, -1 if not found
- */
-int i2c_reset_port_fdt(const void *blob, int node);
-
#endif /* !CONFIG_DM_I2C */
#endif /* _I2C_H_ */
diff --git a/include/linux/compiler_types.h b/include/linux/compiler_types.h
index 1a30601..8b6ce9c 100644
--- a/include/linux/compiler_types.h
+++ b/include/linux/compiler_types.h
@@ -71,6 +71,13 @@
#endif
/*
+ * At least gcc 5.1 or clang 8 are needed.
+ */
+#ifndef COMPILER_HAS_GENERIC_BUILTIN_OVERFLOW
+#error Unsupported compiler
+#endif
+
+/*
* Some architectures need to provide custom definitions of macros provided
* by linux/compiler-*.h, and can do so using asm/compiler.h. We include that
* conditionally rather than using an asm-generic wrapper in order to avoid
diff --git a/include/linux/usb/atmel_usba_udc.h b/include/linux/usb/atmel_usba_udc.h
index c1c8107..37c4f21 100644
--- a/include/linux/usb/atmel_usba_udc.h
+++ b/include/linux/usb/atmel_usba_udc.h
@@ -20,6 +20,8 @@
struct usba_ep_data *ep;
};
+#if !CONFIG_IS_ENABLED(DM_USB_GADGET)
extern int usba_udc_probe(struct usba_platform_data *pdata);
+#endif
#endif /* __LINUX_USB_USBA_H */
diff --git a/include/log.h b/include/log.h
index fc0d598..69dcb33 100644
--- a/include/log.h
+++ b/include/log.h
@@ -125,7 +125,7 @@
* @level: Level of log record (indicating its severity)
* @file: File name of file where log record was generated
* @line: Line number in file where log record was generated
- * @func: Function where log record was generated
+ * @func: Function where log record was generated, NULL if not known
* @fmt: printf() format string for log record
* @...: Optional parameters, according to the format string @fmt
* Return: 0 if log record was emitted, -ve on error
@@ -141,7 +141,7 @@
* @level: Level of log record (indicating its severity)
* @file: File name of file where log record was generated
* @line: Line number in file where log record was generated
- * @func: Function where log record was generated
+ * @func: Function where log record was generated, NULL if not known
* @addr: Starting address to display at start of line
* @data: pointer to data buffer
* @width: data value width. May be 1, 2, or 4.
@@ -193,6 +193,12 @@
#define _LOG_DEBUG 0
#endif
+#ifdef CONFIG_LOGF_FUNC
+#define _log_func __func__
+#else
+#define _log_func NULL
+#endif
+
#if CONFIG_IS_ENABLED(LOG)
/* Emit a log record if the level is less that the maximum */
@@ -201,7 +207,7 @@
if (_LOG_DEBUG != 0 || _l <= _LOG_MAX_LEVEL) \
_log((enum log_category_t)(_cat), \
(enum log_level_t)(_l | _LOG_DEBUG), __FILE__, \
- __LINE__, __func__, \
+ __LINE__, _log_func, \
pr_fmt(_fmt), ##_args); \
})
@@ -211,7 +217,7 @@
if (_LOG_DEBUG != 0 || _l <= _LOG_MAX_LEVEL) \
_log_buffer((enum log_category_t)(_cat), \
(enum log_level_t)(_l | _LOG_DEBUG), __FILE__, \
- __LINE__, __func__, _addr, _data, \
+ __LINE__, _log_func, _addr, _data, \
_width, _count, _linelen); \
})
#else
@@ -314,7 +320,7 @@
#define assert_noisy(x) \
({ bool _val = (x); \
if (!_val) \
- __assert_fail(#x, "?", __LINE__, __func__); \
+ __assert_fail(#x, "?", __LINE__, _log_func); \
_val; \
})
diff --git a/include/os.h b/include/os.h
index 877404a..4371270 100644
--- a/include/os.h
+++ b/include/os.h
@@ -29,7 +29,7 @@
* @fd: File descriptor as returned by os_open()
* @buf: Buffer to place data
* @count: Number of bytes to read
- * Return: number of bytes read, or -1 on error
+ * Return: number of bytes read, or -errno on error
*/
ssize_t os_read(int fd, void *buf, size_t count);
@@ -39,7 +39,7 @@
* @fd: File descriptor as returned by os_open()
* @buf: Buffer containing data to write
* @count: Number of bytes to write
- * Return: number of bytes written, or -1 on error
+ * Return: number of bytes written, or -errno on error
*/
ssize_t os_write(int fd, const void *buf, size_t count);
@@ -49,7 +49,7 @@
* @fd: File descriptor as returned by os_open()
* @offset: File offset (based on whence)
* @whence: Position offset is relative to (see below)
- * Return: new file offset
+ * Return: new file offset, or -errno on error
*/
off_t os_lseek(int fd, off_t offset, int whence);
diff --git a/include/spl.h b/include/spl.h
index 1eebea3..de808cc 100644
--- a/include/spl.h
+++ b/include/spl.h
@@ -282,55 +282,67 @@
#endif
}
+struct spl_load_info;
+
+/**
+ * spl_load_reader() - Read from device
+ *
+ * @load: Information about the load state
+ * @offset: Offset to read from in bytes. This must be a multiple of
+ * @load->bl_len.
+ * @count: Number of bytes to read. This must be a multiple of
+ * @load->bl_len.
+ * @buf: Buffer to read into
+ * @return number of bytes read, 0 on error
+ */
+typedef ulong (*spl_load_reader)(struct spl_load_info *load, ulong sector,
+ ulong count, void *buf);
+
/**
* Information required to load data from a device
*
+ * @read: Function to call to read from the device
* @priv: Private data for the device
* @bl_len: Block length for reading in bytes
- * @read: Function to call to read from the device
*/
struct spl_load_info {
+ spl_load_reader read;
void *priv;
- /**
- * read() - Read from device
- *
- * @load: Information about the load state
- * @offset: Offset to read from in bytes. This must be a multiple of
- * @load->bl_len.
- * @count: Number of bytes to read. This must be a multiple of
- * @load->bl_len.
- * @buf: Buffer to read into
- * @return number of bytes read, 0 on error
- */
- ulong (*read)(struct spl_load_info *load, ulong sector, ulong count,
- void *buf);
#if IS_ENABLED(CONFIG_SPL_LOAD_BLOCK)
int bl_len;
+#endif
};
static inline int spl_get_bl_len(struct spl_load_info *info)
{
+#if IS_ENABLED(CONFIG_SPL_LOAD_BLOCK)
return info->bl_len;
+#else
+ return 1;
+#endif
}
static inline void spl_set_bl_len(struct spl_load_info *info, int bl_len)
{
+#if IS_ENABLED(CONFIG_SPL_LOAD_BLOCK)
info->bl_len = bl_len;
-}
#else
-};
-
-static inline int spl_get_bl_len(struct spl_load_info *info)
-{
- return 1;
+ if (bl_len != 1)
+ panic("CONFIG_SPL_LOAD_BLOCK not enabled");
+#endif
}
-static inline void spl_set_bl_len(struct spl_load_info *info, int bl_len)
+/**
+ * spl_load_init() - Set up a new spl_load_info structure
+ */
+static inline void spl_load_init(struct spl_load_info *load,
+ spl_load_reader h_read, void *priv,
+ uint bl_len)
{
- if (bl_len != 1)
- panic("CONFIG_SPL_LOAD_BLOCK not enabled");
+ load->read = h_read;
+ load->priv = priv;
+ spl_set_bl_len(load, bl_len);
}
-#endif
/*
* We need to know the position of U-Boot in memory so we can jump to it. We
@@ -1073,4 +1085,20 @@
{
return IS_ENABLED(CONFIG_SPL_GZIP) || IS_ENABLED(CONFIG_SPL_LZMA);
}
+
+/**
+ * spl_write_upl_handoff() - Write a Universal Payload hand-off structure
+ *
+ * @spl_image: Information about the image being booted
+ * Return: 0 if OK, -ve on error
+ */
+int spl_write_upl_handoff(struct spl_image_info *spl_image);
+
+/**
+ * spl_upl_init() - Get UPL ready for information to be added
+ *
+ * This must be called before upl_add_image(), etc.
+ */
+void spl_upl_init(void);
+
#endif
diff --git a/include/test/log.h b/include/test/log.h
index e902891..e3362b8 100644
--- a/include/test/log.h
+++ b/include/test/log.h
@@ -13,7 +13,8 @@
#define LOGF_TEST (BIT(LOGF_FUNC) | BIT(LOGF_MSG))
/* Declare a new logging test */
-#define LOG_TEST(_name) UNIT_TEST(_name, 0, log_test)
-#define LOG_TEST_FLAGS(_name, _flags) UNIT_TEST(_name, _flags, log_test)
+#define LOG_TEST(_name) UNIT_TEST(_name, UTF_CONSOLE, log_test)
+#define LOG_TEST_FLAGS(_name, _flags) \
+ UNIT_TEST(_name, _flags | UTF_CONSOLE, log_test)
#endif /* __TEST_LOG_H__ */
diff --git a/include/test/spl.h b/include/test/spl.h
index a2a5f33..5fd28d9 100644
--- a/include/test/spl.h
+++ b/include/test/spl.h
@@ -154,6 +154,6 @@
#define SPL_TEST_DATA_SIZE 4099
/* Flags necessary for accessing DM devices */
-#define DM_FLAGS (UT_TESTF_DM | UT_TESTF_SCAN_FDT)
+#define DM_FLAGS (UTF_DM | UTF_SCAN_FDT)
#endif /* TEST_SPL_H */
diff --git a/include/test/suites.h b/include/test/suites.h
index 365d5f2..2ceef57 100644
--- a/include/test/suites.h
+++ b/include/test/suites.h
@@ -63,5 +63,6 @@
int do_ut_time(struct cmd_tbl *cmdtp, int flag, int argc, char *const argv[]);
int do_ut_unicode(struct cmd_tbl *cmdtp, int flag, int argc,
char *const argv[]);
+int do_ut_upl(struct cmd_tbl *cmdtp, int flag, int argc, char *const argv[]);
#endif /* __TEST_SUITES_H__ */
diff --git a/include/test/test.h b/include/test/test.h
index 838e3ce..92eec2e 100644
--- a/include/test/test.h
+++ b/include/test/test.h
@@ -24,11 +24,11 @@
* @fdt_chksum: crc8 of the device tree contents
* @fdt_copy: Copy of the device tree
* @fdt_size: Size of the device-tree copy
- * @other_fdt: Buffer for the other FDT (UT_TESTF_OTHER_FDT)
- * @other_fdt_size: Size of the other FDT (UT_TESTF_OTHER_FDT)
+ * @other_fdt: Buffer for the other FDT (UTF_OTHER_FDT)
+ * @other_fdt_size: Size of the other FDT (UTF_OTHER_FDT)
* @of_other: Live tree for the other FDT
* @runs_per_test: Number of times to run each test (typically 1)
- * @force_run: true to run tests marked with the UT_TESTF_MANUAL flag
+ * @force_run: true to run tests marked with the UTF_MANUAL flag
* @expect_str: Temporary string used to hold expected string value
* @actual_str: Temporary string used to hold actual string value
*/
@@ -55,24 +55,24 @@
};
/* Test flags for each test */
-enum {
- UT_TESTF_SCAN_PDATA = BIT(0), /* test needs platform data */
- UT_TESTF_PROBE_TEST = BIT(1), /* probe test uclass */
- UT_TESTF_SCAN_FDT = BIT(2), /* scan device tree */
- UT_TESTF_FLAT_TREE = BIT(3), /* test needs flat DT */
- UT_TESTF_LIVE_TREE = BIT(4), /* needs live device tree */
- UT_TESTF_CONSOLE_REC = BIT(5), /* needs console recording */
+enum ut_flags {
+ UTF_SCAN_PDATA = BIT(0), /* test needs platform data */
+ UTF_PROBE_TEST = BIT(1), /* probe test uclass */
+ UTF_SCAN_FDT = BIT(2), /* scan device tree */
+ UTF_FLAT_TREE = BIT(3), /* test needs flat DT */
+ UTF_LIVE_TREE = BIT(4), /* needs live device tree */
+ UTF_CONSOLE = BIT(5), /* needs console recording */
/* do extra driver model init and uninit */
- UT_TESTF_DM = BIT(6),
- UT_TESTF_OTHER_FDT = BIT(7), /* read in other device tree */
+ UTF_DM = BIT(6),
+ UTF_OTHER_FDT = BIT(7), /* read in other device tree */
/*
* Only run if explicitly requested with 'ut -f <suite> <test>'. The
* test name must end in "_norun" so that pytest detects this also,
* since it cannot access the flags.
*/
- UT_TESTF_MANUAL = BIT(8),
- UT_TESTF_ETH_BOOTDEV = BIT(9), /* enable Ethernet bootdevs */
- UT_TESTF_SF_BOOTDEV = BIT(10), /* enable SPI flash bootdevs */
+ UTF_MANUAL = BIT(8),
+ UTF_ETH_BOOTDEV = BIT(9), /* enable Ethernet bootdevs */
+ UTF_SF_BOOTDEV = BIT(10), /* enable SPI flash bootdevs */
};
/**
@@ -109,7 +109,7 @@
* @_name: concatenation of name of the test suite, "_test_", and the name
* of the test
* @_flags: an integer field that can be evaluated by the test suite
- * implementation
+ * implementation (see enum ut_flags)
* @_suite: name of the test suite concatenated with "_test"
*/
#define UNIT_TEST(_name, _flags, _suite) \
diff --git a/include/test/ut.h b/include/test/ut.h
index d3172af..c8838da 100644
--- a/include/test/ut.h
+++ b/include/test/ut.h
@@ -495,7 +495,7 @@
* @select_name: Name of a single test to run (from the list provided). If NULL
* then all tests are run
* @runs_per_test: Number of times to run each test (typically 1)
- * @force_run: Run tests that are marked as manual-only (UT_TESTF_MANUAL)
+ * @force_run: Run tests that are marked as manual-only (UTF_MANUAL)
* @test_insert: String describing a test to run after n other tests run, in the
* format n:name where n is the number of tests to run before this one and
* name is the name of the test to run. This is used to find which test causes
diff --git a/include/upl.h b/include/upl.h
new file mode 100644
index 0000000..2ec5ef1
--- /dev/null
+++ b/include/upl.h
@@ -0,0 +1,382 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * UPL handoff generation
+ *
+ * Copyright 2024 Google LLC
+ * Written by Simon Glass <sjg@chromium.org>
+ */
+
+#ifndef __UPL_WRITE_H
+#define __UPL_WRITE_H
+
+#ifndef USE_HOSTCC
+
+#include <alist.h>
+#include <image.h>
+#include <dm/ofnode_decl.h>
+
+struct unit_test_state;
+
+#define UPLP_ADDRESS_CELLS "#address-cells"
+#define UPLP_SIZE_CELLS "#size-cells"
+
+#define UPLN_OPTIONS "options"
+#define UPLN_UPL_PARAMS "upl-params"
+#define UPLP_SMBIOS "smbios"
+#define UPLP_ACPI "acpi"
+#define UPLP_BOOTMODE "bootmode"
+#define UPLP_ADDR_WIDTH "addr-width"
+#define UPLP_ACPI_NVS_SIZE "acpi-nvs-size"
+
+#define UPLPATH_UPL_IMAGE "/options/upl-image"
+#define UPLN_UPL_IMAGE "upl-image"
+#define UPLN_IMAGE "image"
+#define UPLP_FIT "fit"
+#define UPLP_CONF_OFFSET "conf-offset"
+#define UPLP_LOAD "load"
+#define UPLP_SIZE "size"
+#define UPLP_OFFSET "offset"
+#define UPLP_DESCRIPTION "description"
+
+#define UPLN_MEMORY "memory"
+#define UPLP_HOTPLUGGABLE "hotpluggable"
+
+#define UPLPATH_MEMORY_MAP "/memory-map"
+#define UPLN_MEMORY_MAP "memory-map"
+#define UPLP_USAGE "usage"
+
+#define UPLN_MEMORY_RESERVED "reserved-memory"
+#define UPLPATH_MEMORY_RESERVED "/reserved-memory"
+#define UPLP_NO_MAP "no-map"
+
+#define UPLN_SERIAL "serial"
+#define UPLP_REG "reg"
+#define UPLP_COMPATIBLE "compatible"
+#define UPLP_CLOCK_FREQUENCY "clock-frequency"
+#define UPLP_CURRENT_SPEED "current-speed"
+#define UPLP_REG_IO_SHIFT "reg-io-shift"
+#define UPLP_REG_OFFSET "reg-offset"
+#define UPLP_REG_IO_WIDTH "reg-io-width"
+#define UPLP_VIRTUAL_REG "virtual-reg"
+#define UPLP_ACCESS_TYPE "access-type"
+
+#define UPLN_GRAPHICS "framebuffer"
+#define UPLC_GRAPHICS "simple-framebuffer"
+#define UPLP_WIDTH "width"
+#define UPLP_HEIGHT "height"
+#define UPLP_STRIDE "stride"
+#define UPLP_GRAPHICS_FORMAT "format"
+
+/**
+ * enum upl_boot_mode - Encodes the boot mode
+ *
+ * Each is a bit number from the boot_mode mask
+ */
+enum upl_boot_mode {
+ UPLBM_FULL,
+ UPLBM_MINIMAL,
+ UPLBM_FAST,
+ UPLBM_DIAG,
+ UPLBM_DEFAULT,
+ UPLBM_S2,
+ UPLBM_S3,
+ UPLBM_S4,
+ UPLBM_S5,
+ UPLBM_FACTORY,
+ UPLBM_FLASH,
+ UPLBM_RECOVERY,
+
+ UPLBM_COUNT,
+};
+
+/**
+ * struct upl_image - UPL image informaiton
+ *
+ * @load: Address image was loaded to
+ * @size: Size of image in bytes
+ * @offset: Offset of the image in the FIT (0=none)
+ * @desc: Description of the iamge (taken from the FIT)
+ */
+struct upl_image {
+ ulong load;
+ ulong size;
+ uint offset;
+ const char *description;
+};
+
+/**
+ * struct memregion - Information about a region of memory
+ *
+ * @base: Base address
+ * @size: Size in bytes
+ */
+struct memregion {
+ ulong base;
+ ulong size;
+};
+
+/**
+ * struct upl_mem - Information about physical-memory layout
+ *
+ * TODO: Figure out initial-mapped-area
+ *
+ * @region: Memory region list (struct memregion)
+ * @hotpluggable: true if hotpluggable
+ */
+struct upl_mem {
+ struct alist region;
+ bool hotpluggable;
+};
+
+/**
+ * enum upl_usage - Encodes the usage
+ *
+ * Each is a bit number from the usage mask
+ */
+enum upl_usage {
+ UPLUS_ACPI_RECLAIM,
+ UPLUS_ACPI_NVS,
+ UPLUS_BOOT_CODE,
+ UPLUS_BOOT_DATA,
+ UPLUS_RUNTIME_CODE,
+ UPLUS_RUNTIME_DATA,
+ UPLUS_COUNT
+};
+
+/**
+ * struct upl_memmap - Information about logical-memory layout
+ *
+ * @name: Node name to use
+ * @region: Memory region list (struct memregion)
+ * @usage: Memory-usage mask (enum upl_usage)
+ */
+struct upl_memmap {
+ const char *name;
+ struct alist region;
+ uint usage;
+};
+
+/**
+ * struct upl_memres - Reserved memory
+ *
+ * @name: Node name to use
+ * @region: Reserved memory region list (struct memregion)
+ * @no_map: true to indicate that a virtual mapping must not be created
+ */
+struct upl_memres {
+ const char *name;
+ struct alist region;
+ bool no_map;
+};
+
+enum upl_serial_access_type {
+ UPLSAT_MMIO,
+ UPLSAT_IO,
+};
+
+/* serial defaults */
+enum {
+ UPLD_REG_IO_SHIFT = 0,
+ UPLD_REG_OFFSET = 0,
+ UPLD_REG_IO_WIDTH = 1,
+};
+
+/**
+ * enum upl_access_type - Access types
+ *
+ * @UPLAT_MMIO: Memory-mapped I/O
+ * @UPLAT_IO: Separate I/O
+ */
+enum upl_access_type {
+ UPLAT_MMIO,
+ UPLAT_IO,
+};
+
+/**
+ * struct upl_serial - Serial console
+ *
+ * @compatible: Compatible string (NULL if there is no serial console)
+ * @clock_frequency: Input clock frequency of UART
+ * @current_speed: Current baud rate of UART
+ * @reg: List of base address and size of registers (struct memregion)
+ * @reg_shift_log2: log2 of distance between each register
+ * @reg_offset: Offset of registers from the base address
+ * @reg_width: Register width in bytes
+ * @virtual_reg: Virtual register access (0 for none)
+ * @access_type: Register access type to use
+ */
+struct upl_serial {
+ const char *compatible;
+ uint clock_frequency;
+ uint current_speed;
+ struct alist reg;
+ uint reg_io_shift;
+ uint reg_offset;
+ uint reg_io_width;
+ ulong virtual_reg;
+ enum upl_serial_access_type access_type;
+};
+
+/**
+ * enum upl_graphics_format - Graphics formats
+ *
+ * @UPLGF_ARGB32: 32bpp format using 0xaarrggbb
+ * @UPLGF_ABGR32: 32bpp format using 0xaabbggrr
+ * @UPLGF_ARGB64: 64bpp format using 0xaaaabbbbggggrrrr
+ */
+enum upl_graphics_format {
+ UPLGF_ARGB32,
+ UPLGF_ABGR32,
+ UPLGF_ABGR64,
+};
+
+/**
+ * @reg: List of base address and size of registers (struct memregion)
+ * @width: Width of display in pixels
+ * @height: Height of display in pixels
+ * @stride: Number of bytes from one line to the next
+ * @format: Pixel format
+ */
+struct upl_graphics {
+ struct alist reg;
+ uint width;
+ uint height;
+ uint stride;
+ enum upl_graphics_format format;
+};
+
+/*
+ * Information about the UPL state
+ *
+ * @addr_cells: Number of address cells used in the handoff
+ * @size_cells: Number of size cells used in the handoff
+ * @bootmode: Boot-mode mask (enum upl_boot_mode)
+ * @fit: Address of FIT image that was loaded
+ * @conf_offset: Offset in FIT of the configuration that was selected
+ * @addr_width: Adress-bus width of machine, e.g. 46 for 46 bits
+ * @acpi_nvs_size: Size of the ACPI non-volatile-storage area in bytes
+ * @image: Information about each image (struct upl_image)
+ * @mem: Information about physical-memory regions (struct upl_mem)
+ * @nennap: Information about logical-memory regions (struct upl_memmap)
+ * @nennap: Information about reserved-memory regions (struct upl_memres)
+ */
+struct upl {
+ int addr_cells;
+ int size_cells;
+
+ ulong smbios;
+ ulong acpi;
+ uint bootmode;
+ ulong fit;
+ uint conf_offset;
+ uint addr_width;
+ uint acpi_nvs_size;
+
+ struct alist image;
+ struct alist mem;
+ struct alist memmap;
+ struct alist memres;
+ struct upl_serial serial;
+ struct upl_graphics graphics;
+};
+
+/**
+ * upl_write_handoff() - Write a Unversal Payload handoff structure
+ *
+ * upl: UPL state to write
+ * @root: root node to write it to
+ * @skip_existing: Avoid recreating any nodes which already exist in the
+ * devicetree. For example, if there is a serial node, just leave it alone,
+ * since don't need to create a new one
+ * Return: 0 on success, -ve on error
+ */
+int upl_write_handoff(const struct upl *upl, ofnode root, bool skip_existing);
+
+/**
+ * upl_create_handoff_tree() - Write a Unversal Payload handoff structure
+ *
+ * upl: UPL state to write
+ * @treep: Returns a new tree containing the handoff
+ * Return: 0 on success, -ve on error
+ */
+int upl_create_handoff_tree(const struct upl *upl, oftree *treep);
+
+/**
+ * upl_read_handoff() - Read a Unversal Payload handoff structure
+ *
+ * upl: UPL state to read into
+ * @tree: Devicetree containing the data to read
+ * Return: 0 on success, -ve on error
+ */
+int upl_read_handoff(struct upl *upl, oftree tree);
+
+/**
+ * upl_get_test_data() - Fill a UPL with some test data
+ *
+ * @uts: Test state (can be uninited)
+ * @upl: Returns test data
+ * Return: 0 on success, 1 on error
+ */
+int upl_get_test_data(struct unit_test_state *uts, struct upl *upl);
+#endif /* USE_HOSTCC */
+
+#if CONFIG_IS_ENABLED(UPL) && defined(CONFIG_SPL_BUILD)
+
+/**
+ * upl_set_fit_info() - Set up basic info about the FIT
+ *
+ * @fit: Address of FIT
+ * @conf_offset: Configuration node being used
+ * @entry_addr: Entry address for next phase
+ */
+void upl_set_fit_info(ulong fit, int conf_offset, ulong entry_addr);
+
+/**
+ * upl_set_fit_addr() - Set up the address of the FIT
+ *
+ * @fit: Address of FIT
+ */
+void upl_set_fit_addr(ulong fit);
+
+#else
+static inline void upl_set_fit_addr(ulong fit) {}
+static inline void upl_set_fit_info(ulong fit, int conf_offset,
+ ulong entry_addr) {}
+#endif /* UPL && SPL */
+
+/**
+ * _upl_add_image() - Internal function to add a new image to the UPL
+ *
+ * @node: Image node offset in FIT
+ * @load_addr: Address to which images was loaded
+ * @size: Image size in bytes
+ * @desc: Description of image
+ * Return: 0 if OK, -ENOMEM if out of memory
+ */
+int _upl_add_image(int node, ulong load_addr, ulong size, const char *desc);
+
+/**
+ * upl_add_image() - Add a new image to the UPL
+ *
+ * @fit: Pointer to FIT
+ * @node: Image node offset in FIT
+ * @load_addr: Address to which images was loaded
+ * @size: Image size in bytes
+ * Return: 0 if OK, -ENOMEM if out of memory
+ */
+static inline int upl_add_image(const void *fit, int node, ulong load_addr,
+ ulong size)
+{
+ if (CONFIG_IS_ENABLED(UPL) && IS_ENABLED(CONFIG_SPL_BUILD)) {
+ const char *desc = fdt_getprop(fit, node, FIT_DESC_PROP, NULL);
+
+ return _upl_add_image(node, load_addr, size, desc);
+ }
+
+ return 0;
+}
+
+/** upl_init() - Set up a UPL struct */
+void upl_init(struct upl *upl);
+
+#endif /* __UPL_WRITE_H */
diff --git a/include/video.h b/include/video.h
index 4013a94..606c8a3 100644
--- a/include/video.h
+++ b/include/video.h
@@ -420,4 +420,15 @@
*/
int video_reserve_from_bloblist(struct video_handoff *ho);
+/**
+ * video_get_fb() - Get the first framebuffer address
+ *
+ * This function does not probe video devices, so can only be used after a video
+ * device has been activated.
+ *
+ * Return: address of the framebuffer of the first video device found, or 0 if
+ * there is no device
+ */
+ulong video_get_fb(void);
+
#endif
diff --git a/lib/Makefile b/lib/Makefile
index e389ad0..81b503a 100644
--- a/lib/Makefile
+++ b/lib/Makefile
@@ -147,6 +147,7 @@
obj-$(CONFIG_$(SPL_)OID_REGISTRY) += oid_registry.o
obj-y += abuf.o
+obj-y += alist.o
obj-y += date.o
obj-y += rtc-lib.o
obj-$(CONFIG_LIB_ELF) += elf.o
diff --git a/lib/alist.c b/lib/alist.c
new file mode 100644
index 0000000..b7928ca
--- /dev/null
+++ b/lib/alist.c
@@ -0,0 +1,158 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Handles a contiguous list of pointers which be allocated and freed
+ *
+ * Copyright 2023 Google LLC
+ * Written by Simon Glass <sjg@chromium.org>
+ */
+
+#include <alist.h>
+#include <display_options.h>
+#include <malloc.h>
+#include <stdio.h>
+#include <string.h>
+
+enum {
+ ALIST_INITIAL_SIZE = 4, /* default size of unsized list */
+};
+
+bool alist_init(struct alist *lst, uint obj_size, uint start_size)
+{
+ /* Avoid realloc for the initial size to help malloc_simple */
+ memset(lst, '\0', sizeof(struct alist));
+ if (start_size) {
+ lst->data = calloc(obj_size, start_size);
+ if (!lst->data) {
+ lst->flags = ALISTF_FAIL;
+ return false;
+ }
+ lst->alloc = start_size;
+ }
+ lst->obj_size = obj_size;
+
+ return true;
+}
+
+void alist_uninit(struct alist *lst)
+{
+ free(lst->data);
+
+ /* Clear fields to avoid any confusion */
+ memset(lst, '\0', sizeof(struct alist));
+}
+
+/**
+ * alist_expand_to() - Expand a list to the given size
+ *
+ * @lst: List to modify
+ * @inc_by: Amount to expand to
+ * Return: true if OK, false if out of memory
+ */
+static bool alist_expand_to(struct alist *lst, uint new_alloc)
+{
+ void *new_data;
+
+ if (lst->flags & ALISTF_FAIL)
+ return false;
+
+ /* avoid using realloc() since it increases code size */
+ new_data = malloc(lst->obj_size * new_alloc);
+ if (!new_data) {
+ lst->flags |= ALISTF_FAIL;
+ return false;
+ }
+
+ memcpy(new_data, lst->data, lst->obj_size * lst->alloc);
+ free(lst->data);
+
+ memset(new_data + lst->obj_size * lst->alloc, '\0',
+ lst->obj_size * (new_alloc - lst->alloc));
+ lst->alloc = new_alloc;
+ lst->data = new_data;
+
+ return true;
+}
+
+bool alist_expand_by(struct alist *lst, uint inc_by)
+{
+ return alist_expand_to(lst, lst->alloc + inc_by);
+}
+
+/**
+ * alist_expand_min() - Expand to at least the provided size
+ *
+ * Expands to the lowest power of two which can incorporate the new size
+ *
+ * @lst: alist to expand
+ * @min_alloc: Minimum new allocated size; if 0 then ALIST_INITIAL_SIZE is used
+ * Return: true if OK, false if out of memory
+ */
+static bool alist_expand_min(struct alist *lst, uint min_alloc)
+{
+ uint new_alloc;
+
+ for (new_alloc = lst->alloc ?: ALIST_INITIAL_SIZE;
+ new_alloc < min_alloc;)
+ new_alloc *= 2;
+
+ return alist_expand_to(lst, new_alloc);
+}
+
+const void *alist_get_ptr(const struct alist *lst, uint index)
+{
+ if (index >= lst->count)
+ return NULL;
+
+ return lst->data + index * lst->obj_size;
+}
+
+void *alist_ensure_ptr(struct alist *lst, uint index)
+{
+ uint minsize = index + 1;
+ void *ptr;
+
+ if (index >= lst->alloc && !alist_expand_min(lst, minsize))
+ return NULL;
+
+ ptr = lst->data + index * lst->obj_size;
+ if (minsize >= lst->count)
+ lst->count = minsize;
+
+ return ptr;
+}
+
+void *alist_add_placeholder(struct alist *lst)
+{
+ return alist_ensure_ptr(lst, lst->count);
+}
+
+void *alist_add_ptr(struct alist *lst, void *obj)
+{
+ void *ptr;
+
+ ptr = alist_add_placeholder(lst);
+ if (!ptr)
+ return NULL;
+ memcpy(ptr, obj, lst->obj_size);
+
+ return ptr;
+}
+
+void *alist_uninit_move_ptr(struct alist *alist, size_t *countp)
+{
+ void *ptr;
+
+ if (countp)
+ *countp = alist->count;
+ if (!alist->count) {
+ alist_uninit(alist);
+ return NULL;
+ }
+
+ ptr = alist->data;
+
+ /* Clear everything out so there is no record of the data */
+ alist_init(alist, alist->obj_size, 0);
+
+ return ptr;
+}
diff --git a/lib/asm-offsets.c b/lib/asm-offsets.c
index 4e2dbda..b6bbcbf 100644
--- a/lib/asm-offsets.c
+++ b/lib/asm-offsets.c
@@ -44,7 +44,9 @@
DEFINE(GD_NEW_GD, offsetof(struct global_data, new_gd));
+#if CONFIG_IS_ENABLED(ENV_SUPPORT)
DEFINE(GD_ENV_ADDR, offsetof(struct global_data, env_addr));
+#endif
return 0;
}
diff --git a/lib/elf.c b/lib/elf.c
index dc13935..28ec87b 100644
--- a/lib/elf.c
+++ b/lib/elf.c
@@ -90,6 +90,10 @@
void *dst = (void *)(ulong)phdr->p_paddr;
void *src = (void *)addr + phdr->p_offset;
+ /* Only load PT_LOAD program header */
+ if (phdr->p_type != PT_LOAD)
+ continue;
+
debug("Loading phdr %i to 0x%p (%lu bytes)\n",
i, dst, (ulong)phdr->p_filesz);
if (phdr->p_filesz)
@@ -205,6 +209,10 @@
void *dst = (void *)(uintptr_t)phdr->p_paddr;
void *src = (void *)addr + phdr->p_offset;
+ /* Only load PT_LOAD program header */
+ if (phdr->p_type != PT_LOAD)
+ continue;
+
debug("Loading phdr %i to 0x%p (%i bytes)\n",
i, dst, phdr->p_filesz);
if (phdr->p_filesz)
diff --git a/lib/fdtdec.c b/lib/fdtdec.c
index 6865f78..5edc8dd 100644
--- a/lib/fdtdec.c
+++ b/lib/fdtdec.c
@@ -1685,6 +1685,7 @@
gd->fdt_src = FDTSRC_BLOBLIST;
log_debug("Devicetree is in bloblist at %p\n",
gd->fdt_blob);
+ ret = 0;
} else {
log_debug("No FDT found in bloblist\n");
ret = -ENOENT;
diff --git a/lib/strto.c b/lib/strto.c
index 5157332..f83ac67 100644
--- a/lib/strto.c
+++ b/lib/strto.c
@@ -236,12 +236,14 @@
return NULL;
/* count the number of space-separated strings */
- for (count = *str != '\0', p = str; *p; p++) {
+ for (count = 0, p = str; *p; p++) {
if (*p == ' ') {
count++;
*p = '\0';
}
}
+ if (p != str && p[-1])
+ count++;
/* allocate the pointer array, allowing for a NULL terminator */
ptr = calloc(count + 1, sizeof(char *));
diff --git a/net/wget.c b/net/wget.c
index f1dd7ab..945bfd2 100644
--- a/net/wget.c
+++ b/net/wget.c
@@ -244,7 +244,7 @@
pkt_in_q = (void *)image_load_addr + PKT_QUEUE_OFFSET +
(pkt_q_idx * PKT_QUEUE_PACKET_SIZE);
- ptr1 = map_sysmem((phys_addr_t)pkt_in_q, len);
+ ptr1 = map_sysmem((ulong)pkt_in_q, len);
memcpy(ptr1, pkt, len);
unmap_sysmem(ptr1);
@@ -314,9 +314,8 @@
for (i = 0; i < pkt_q_idx; i++) {
int err;
- ptr1 = map_sysmem(
- (phys_addr_t)(pkt_q[i].pkt),
- pkt_q[i].len);
+ ptr1 = map_sysmem((ulong)pkt_q[i].pkt,
+ pkt_q[i].len);
err = store_block(ptr1,
pkt_q[i].tcp_seq_num -
initial_data_seq_num,
diff --git a/scripts/decodecode b/scripts/decodecode
index 9cef558..6364218 100755
--- a/scripts/decodecode
+++ b/scripts/decodecode
@@ -1,4 +1,4 @@
-#!/bin/sh
+#!/bin/bash
# SPDX-License-Identifier: GPL-2.0
# Disassemble the Code: line in Linux oopses
# usage: decodecode < oops.file
@@ -6,6 +6,9 @@
# options: set env. variable AFLAGS=options to pass options to "as";
# e.g., to decode an i386 oops on an x86_64 system, use:
# AFLAGS=--32 decodecode < 386.oops
+# PC=hex - the PC (program counter) the oops points to
+
+faultlinenum=1
cleanup() {
rm -f $T $T.s $T.o $T.oo $T.aa $T.dis
@@ -60,15 +63,27 @@
4) type=4byte ;;
esac
+if [ -z "$ARCH" ]; then
+ case `uname -m` in
+ aarch64*) ARCH=arm64 ;;
+ arm*) ARCH=arm ;;
+ loongarch*) ARCH=loongarch ;;
+ esac
+fi
+
+# Params: (tmp_file, pc_sub)
disas() {
- ${CROSS_COMPILE}as $AFLAGS -o $1.o $1.s > /dev/null 2>&1
+ t=$1
+ pc_sub=$2
+
+ ${CROSS_COMPILE}as $AFLAGS -o $t.o $t.s > /dev/null 2>&1
if [ "$ARCH" = "arm" ]; then
if [ $width -eq 2 ]; then
OBJDUMPFLAGS="-M force-thumb"
fi
- ${CROSS_COMPILE}strip $1.o
+ ${CROSS_COMPILE}strip $t.o
fi
if [ "$ARCH" = "arm64" ]; then
@@ -76,13 +91,122 @@
type=inst
fi
- ${CROSS_COMPILE}strip $1.o
+ ${CROSS_COMPILE}strip $t.o
fi
- ${CROSS_COMPILE}objdump $OBJDUMPFLAGS -S $1.o | \
- grep -v "/tmp\|Disassembly\|\.text\|^$" > $1.dis 2>&1
+ if [ "$ARCH" = "riscv" ]; then
+ OBJDUMPFLAGS="-M no-aliases --section=.text -D"
+ ${CROSS_COMPILE}strip $t.o
+ fi
+
+ if [ "$ARCH" = "loongarch" ]; then
+ ${CROSS_COMPILE}strip $t.o
+ fi
+
+ if [ $pc_sub -ne 0 ]; then
+ if [ $PC ]; then
+ adj_vma=$(( $PC - $pc_sub ))
+ OBJDUMPFLAGS="$OBJDUMPFLAGS --adjust-vma=$adj_vma"
+ fi
+ fi
+
+ ${CROSS_COMPILE}objdump $OBJDUMPFLAGS -S $t.o | \
+ grep -v "/tmp\|Disassembly\|\.text\|^$" > $t.dis 2>&1
}
+# Match the maximum number of opcode bytes from @op_bytes contained within
+# @opline
+#
+# Params:
+# @op_bytes: The string of bytes from the Code: line
+# @opline: The disassembled line coming from objdump
+#
+# Returns:
+# The max number of opcode bytes from the beginning of @op_bytes which match
+# the opcode bytes in the objdump line.
+get_substr_opcode_bytes_num()
+{
+ local op_bytes=$1
+ local opline=$2
+
+ local retval=0
+ substr=""
+
+ for opc in $op_bytes;
+ do
+ substr+="$opc"
+
+ opcode="$substr"
+ if [ "$ARCH" = "riscv" ]; then
+ opcode=$(echo $opcode | tr ' ' '\n' | tac | tr -d '\n')
+ fi
+
+ # return if opcode bytes do not match @opline anymore
+ if ! echo $opline | grep -q "$opcode";
+ then
+ break
+ fi
+
+ # add trailing space
+ substr+=" "
+ retval=$((retval+1))
+ done
+
+ return $retval
+}
+
+# Return the line number in objdump output to where the IP marker in the Code:
+# line points to
+#
+# Params:
+# @all_code: code in bytes without the marker
+# @dis_file: disassembled file
+# @ip_byte: The byte to which the IP points to
+get_faultlinenum()
+{
+ local all_code="$1"
+ local dis_file="$2"
+
+ # num bytes including IP byte
+ local num_bytes_ip=$(( $3 + 1 * $width ))
+
+ # Add the two header lines (we're counting from 1).
+ local retval=3
+
+ # remove marker
+ all_code=$(echo $all_code | sed -e 's/[<>()]//g')
+
+ while read line
+ do
+ get_substr_opcode_bytes_num "$all_code" "$line"
+ ate_opcodes=$?
+
+ if ! (( $ate_opcodes )); then
+ continue
+ fi
+
+ num_bytes_ip=$((num_bytes_ip - ($ate_opcodes * $width) ))
+ if (( $num_bytes_ip <= 0 )); then
+ break
+ fi
+
+ # Delete matched opcode bytes from all_code. For that, compute
+ # how many chars those opcodes are represented by and include
+ # trailing space.
+ #
+ # a byte is 2 chars, ate_opcodes is also the number of trailing
+ # spaces
+ del_chars=$(( ($ate_opcodes * $width * 2) + $ate_opcodes ))
+
+ all_code=$(echo $all_code | sed -e "s!^.\{$del_chars\}!!")
+
+ let "retval+=1"
+
+ done < $dis_file
+
+ return $retval
+}
+
marker=`expr index "$code" "\<"`
if [ $marker -eq 0 ]; then
marker=`expr index "$code" "\("`
@@ -90,36 +214,39 @@
touch $T.oo
if [ $marker -ne 0 ]; then
+ # How many bytes to subtract from the program counter
+ # in order to get to the beginning virtual address of the
+ # Code:
+ pc_sub=$(( (($marker - 1) / (2 * $width + 1)) * $width ))
echo All code >> $T.oo
echo ======== >> $T.oo
beforemark=`echo "$code"`
echo -n " .$type 0x" > $T.s
+
echo $beforemark | sed -e 's/ /,0x/g; s/[<>()]//g' >> $T.s
- disas $T
+
+ disas $T $pc_sub
+
cat $T.dis >> $T.oo
- rm -f $T.o $T.s $T.dis
-# and fix code at-and-after marker
+ get_faultlinenum "$code" "$T.dis" $pc_sub
+ faultlinenum=$?
+
+ # and fix code at-and-after marker
code=`echo "$code" | cut -c$((${marker} + 1))-`
+
+ rm -f $T.o $T.s $T.dis
fi
+
echo Code starting with the faulting instruction > $T.aa
echo =========================================== >> $T.aa
-code=`echo $code | sed -e 's/ [<(]/ /;s/[>)] / /;s/ /,0x/g; s/[>)]$//'`
+code=`echo $code | sed -e 's/\r//;s/ [<(]/ /;s/[>)] / /;s/ /,0x/g; s/[>)]$//'`
echo -n " .$type 0x" > $T.s
echo $code >> $T.s
-disas $T
+disas $T 0
cat $T.dis >> $T.aa
-# (lines of whole $T.oo) - (lines of $T.aa, i.e. "Code starting") + 3,
-# i.e. the title + the "===..=" line (sed is counting from 1, 0 address is
-# special)
-faultlinenum=$(( $(wc -l $T.oo | cut -d" " -f1) - \
- $(wc -l $T.aa | cut -d" " -f1) + 3))
-
-faultline=`cat $T.dis | head -1 | cut -d":" -f2-`
-faultline=`echo "$faultline" | sed -e 's/\[/\\\[/g; s/\]/\\\]/g'`
-
-cat $T.oo | sed -e "${faultlinenum}s/^\(.*:\)\(.*\)/\1\*\2\t\t<-- trapping instruction/"
+cat $T.oo | sed -e "${faultlinenum}s/^\([^:]*:\)\(.*\)/\1\*\2\t\t<-- trapping instruction/"
echo
cat $T.aa
cleanup
diff --git a/test/bloblist.c b/test/bloblist.c
index 7c63682..fd85c7a 100644
--- a/test/bloblist.c
+++ b/test/bloblist.c
@@ -270,20 +270,15 @@
data = bloblist_ensure(TEST_TAG, TEST_SIZE);
data2 = bloblist_ensure(TEST_TAG2, TEST_SIZE2);
- console_record_reset_enable();
- ut_silence_console(uts);
- console_record_reset();
run_command("bloblist info", 0);
ut_assert_nextline("base: %lx", (ulong)map_to_sysmem(hdr));
ut_assert_nextline("total size: 400 1 KiB");
ut_assert_nextline("used size: 50 80 Bytes");
ut_assert_nextline("free: 3b0 944 Bytes");
- ut_assert_console_end();
- ut_unsilence_console(uts);
return 0;
}
-BLOBLIST_TEST(bloblist_test_cmd_info, 0);
+BLOBLIST_TEST(bloblist_test_cmd_info, UTF_CONSOLE);
/* Test the 'bloblist list' command */
static int bloblist_test_cmd_list(struct unit_test_state *uts)
@@ -296,21 +291,16 @@
data = bloblist_ensure(TEST_TAG, TEST_SIZE);
data2 = bloblist_ensure(TEST_TAG2, TEST_SIZE2);
- console_record_reset_enable();
- ut_silence_console(uts);
- console_record_reset();
run_command("bloblist list", 0);
ut_assert_nextline("Address Size Tag Name");
ut_assert_nextline("%08lx %8x fff000 SPL hand-off",
(ulong)map_to_sysmem(data), TEST_SIZE);
ut_assert_nextline("%08lx %8x 202 Chrome OS vboot context",
(ulong)map_to_sysmem(data2), TEST_SIZE2);
- ut_assert_console_end();
- ut_unsilence_console(uts);
return 0;
}
-BLOBLIST_TEST(bloblist_test_cmd_list, 0);
+BLOBLIST_TEST(bloblist_test_cmd_list, UTF_CONSOLE);
/* Test alignment of bloblist blobs */
static int bloblist_test_align(struct unit_test_state *uts)
diff --git a/test/boot/Makefile b/test/boot/Makefile
index 068522c..d8eded2 100644
--- a/test/boot/Makefile
+++ b/test/boot/Makefile
@@ -2,14 +2,19 @@
#
# Copyright 2021 Google LLC
+ifdef CONFIG_UT_BOOTSTD
obj-$(CONFIG_BOOTSTD) += bootdev.o bootstd_common.o bootflow.o bootmeth.o
obj-$(CONFIG_FIT) += image.o
-obj-$(CONFIG_MEASURED_BOOT) += measurement.o
obj-$(CONFIG_EXPO) += expo.o
obj-$(CONFIG_CEDIT) += cedit.o
+endif
+
+obj-$(CONFIG_MEASURED_BOOT) += measurement.o
ifdef CONFIG_OF_LIVE
obj-$(CONFIG_BOOTMETH_VBE_SIMPLE) += vbe_simple.o
endif
obj-$(CONFIG_BOOTMETH_VBE) += vbe_fixup.o
+
+obj-$(CONFIG_UPL) += upl.o
diff --git a/test/boot/bootdev.c b/test/boot/bootdev.c
index 1bf5929..23ebc61 100644
--- a/test/boot/bootdev.c
+++ b/test/boot/bootdev.c
@@ -28,7 +28,6 @@
{
int probed;
- console_record_reset_enable();
for (probed = 0; probed < 2; probed++) {
int probe_ch = probed ? '+' : ' ';
@@ -49,7 +48,7 @@
return 0;
}
-BOOTSTD_TEST(bootdev_test_cmd_list, UT_TESTF_DM | UT_TESTF_SCAN_FDT);
+BOOTSTD_TEST(bootdev_test_cmd_list, UTF_DM | UTF_SCAN_FDT | UTF_CONSOLE);
/* Check 'bootdev select' and 'info' commands */
static int bootdev_test_cmd_select(struct unit_test_state *uts)
@@ -59,7 +58,6 @@
/* get access to the CLI's cur_bootdev */
ut_assertok(bootstd_get_priv(&std));
- console_record_reset_enable();
ut_asserteq(1, run_command("bootdev info", 0));
ut_assert_nextlinen("Please use");
ut_assert_console_end();
@@ -99,7 +97,7 @@
return 0;
}
-BOOTSTD_TEST(bootdev_test_cmd_select, UT_TESTF_DM | UT_TESTF_SCAN_FDT);
+BOOTSTD_TEST(bootdev_test_cmd_select, UTF_DM | UTF_SCAN_FDT | UTF_CONSOLE);
/* Check bootdev labels */
static int bootdev_test_labels(struct unit_test_state *uts)
@@ -131,8 +129,7 @@
return 0;
}
-BOOTSTD_TEST(bootdev_test_labels, UT_TESTF_DM | UT_TESTF_SCAN_FDT |
- UT_TESTF_ETH_BOOTDEV);
+BOOTSTD_TEST(bootdev_test_labels, UTF_DM | UTF_SCAN_FDT | UTF_ETH_BOOTDEV);
/* Check bootdev_find_by_any() */
static int bootdev_test_any(struct unit_test_state *uts)
@@ -158,7 +155,6 @@
* 9 [ + ] OK mmc mmc1.bootdev
* a [ ] OK mmc mmc0.bootdev
*/
- console_record_reset_enable();
ut_assertok(bootdev_find_by_any("8", &dev, &mflags));
ut_asserteq(UCLASS_BOOTDEV, device_get_uclass_id(dev));
ut_asserteq(BOOTFLOW_METHF_SINGLE_DEV, mflags);
@@ -186,8 +182,8 @@
return 0;
}
-BOOTSTD_TEST(bootdev_test_any, UT_TESTF_DM | UT_TESTF_SCAN_FDT |
- UT_TESTF_ETH_BOOTDEV);
+BOOTSTD_TEST(bootdev_test_any, UTF_DM | UTF_SCAN_FDT | UTF_ETH_BOOTDEV |
+ UTF_CONSOLE);
/*
* Check bootdev ordering with the bootdev-order property and boot_targets
@@ -274,7 +270,7 @@
return 0;
}
-BOOTSTD_TEST(bootdev_test_order, UT_TESTF_DM | UT_TESTF_SCAN_FDT);
+BOOTSTD_TEST(bootdev_test_order, UTF_DM | UTF_SCAN_FDT);
/* Check default bootdev ordering */
static int bootdev_test_order_default(struct unit_test_state *uts)
@@ -301,7 +297,7 @@
return 0;
}
-BOOTSTD_TEST(bootdev_test_order_default, UT_TESTF_DM | UT_TESTF_SCAN_FDT);
+BOOTSTD_TEST(bootdev_test_order_default, UTF_DM | UTF_SCAN_FDT);
/* Check bootdev ordering with the uclass priority */
static int bootdev_test_prio(struct unit_test_state *uts)
@@ -323,7 +319,6 @@
ut_assertok(bootstd_test_drop_bootdev_order(uts));
/* 3 MMC and 3 USB bootdevs: MMC should come before USB */
- console_record_reset_enable();
ut_assertok(bootflow_scan_first(NULL, NULL, &iter, 0, &bflow));
ut_asserteq(-ENODEV, bootflow_scan_next(&iter, &bflow));
ut_asserteq(6, iter.num_devs);
@@ -350,7 +345,7 @@
return 0;
}
-BOOTSTD_TEST(bootdev_test_prio, UT_TESTF_DM | UT_TESTF_SCAN_FDT);
+BOOTSTD_TEST(bootdev_test_prio, UTF_DM | UTF_SCAN_FDT);
/* Check listing hunters */
static int bootdev_test_hunter(struct unit_test_state *uts)
@@ -363,7 +358,6 @@
/* get access to the used hunters */
ut_assertok(bootstd_get_priv(&std));
- console_record_reset_enable();
bootdev_list_hunters(std);
ut_assert_nextline("Prio Used Uclass Hunter");
ut_assert_nextlinen("----");
@@ -390,7 +384,7 @@
return 0;
}
-BOOTSTD_TEST(bootdev_test_hunter, UT_TESTF_DM | UT_TESTF_SCAN_FDT);
+BOOTSTD_TEST(bootdev_test_hunter, UTF_DM | UTF_SCAN_FDT | UTF_CONSOLE);
/* Check 'bootdev hunt' command */
static int bootdev_test_cmd_hunt(struct unit_test_state *uts)
@@ -403,7 +397,6 @@
/* get access to the used hunters */
ut_assertok(bootstd_get_priv(&std));
- console_record_reset_enable();
ut_assertok(run_command("bootdev hunt -l", 0));
ut_assert_nextline("Prio Used Uclass Hunter");
ut_assert_nextlinen("----");
@@ -464,8 +457,8 @@
return 0;
}
-BOOTSTD_TEST(bootdev_test_cmd_hunt, UT_TESTF_DM | UT_TESTF_SCAN_FDT |
- UT_TESTF_ETH_BOOTDEV);
+BOOTSTD_TEST(bootdev_test_cmd_hunt, UTF_DM | UTF_SCAN_FDT | UTF_ETH_BOOTDEV |
+ UTF_CONSOLE);
/* Check searching for bootdevs using the hunters */
static int bootdev_test_hunt_scan(struct unit_test_state *uts)
@@ -485,7 +478,7 @@
return 0;
}
-BOOTSTD_TEST(bootdev_test_hunt_scan, UT_TESTF_DM | UT_TESTF_SCAN_FDT);
+BOOTSTD_TEST(bootdev_test_hunt_scan, UTF_DM | UTF_SCAN_FDT);
/* Check that only bootable partitions are processed */
static int bootdev_test_bootable(struct unit_test_state *uts)
@@ -522,7 +515,7 @@
return 0;
}
-BOOTSTD_TEST(bootdev_test_bootable, UT_TESTF_DM | UT_TESTF_SCAN_FDT);
+BOOTSTD_TEST(bootdev_test_bootable, UTF_DM | UTF_SCAN_FDT);
/* Check hunting for bootdev of a particular priority */
static int bootdev_test_hunt_prio(struct unit_test_state *uts)
@@ -530,7 +523,6 @@
usb_started = false;
test_set_skip_delays(true);
- console_record_reset_enable();
ut_assertok(bootdev_hunt_prio(BOOTDEVP_4_SCAN_FAST, false));
ut_assert_nextline("scanning bus for devices...");
ut_assert_skip_to_line(" Type: Hard Disk");
@@ -547,7 +539,7 @@
return 0;
}
-BOOTSTD_TEST(bootdev_test_hunt_prio, UT_TESTF_DM | UT_TESTF_SCAN_FDT);
+BOOTSTD_TEST(bootdev_test_hunt_prio, UTF_DM | UTF_SCAN_FDT | UTF_CONSOLE);
/* Check hunting for bootdevs with a particular label */
static int bootdev_test_hunt_label(struct unit_test_state *uts)
@@ -562,7 +554,6 @@
ut_assertok(bootstd_get_priv(&std));
/* scan an unknown uclass */
- console_record_reset_enable();
old = (void *)&mflags; /* arbitrary pointer to check against dev */
dev = old;
mflags = 123;
@@ -600,7 +591,7 @@
return 0;
}
-BOOTSTD_TEST(bootdev_test_hunt_label, UT_TESTF_DM | UT_TESTF_SCAN_FDT);
+BOOTSTD_TEST(bootdev_test_hunt_label, UTF_DM | UTF_SCAN_FDT | UTF_CONSOLE);
/* Check iterating to the next label in a list */
static int bootdev_test_next_label(struct unit_test_state *uts)
@@ -627,7 +618,6 @@
dev = NULL;
mflags = 123;
ut_assertok(bootdev_next_label(&iter, &dev, &mflags));
- console_record_reset_enable();
ut_assert_console_end();
ut_assertnonnull(dev);
ut_asserteq_str("mmc0.bootdev", dev->name);
@@ -677,8 +667,8 @@
return 0;
}
-BOOTSTD_TEST(bootdev_test_next_label, UT_TESTF_DM | UT_TESTF_SCAN_FDT |
- UT_TESTF_ETH_BOOTDEV | UT_TESTF_SF_BOOTDEV);
+BOOTSTD_TEST(bootdev_test_next_label, UTF_DM | UTF_SCAN_FDT | UTF_ETH_BOOTDEV |
+ UTF_SF_BOOTDEV | UTF_CONSOLE);
/* Check iterating to the next prioirty in a list */
static int bootdev_test_next_prio(struct unit_test_state *uts)
@@ -703,7 +693,6 @@
iter.flags = BOOTFLOWIF_SHOW;
dev = NULL;
- console_record_reset_enable();
ut_assertok(bootdev_next_prio(&iter, &dev));
ut_assertnonnull(dev);
ut_asserteq_str("mmc2.bootdev", dev->name);
@@ -762,5 +751,5 @@
return 0;
}
-BOOTSTD_TEST(bootdev_test_next_prio, UT_TESTF_DM | UT_TESTF_SCAN_FDT |
- UT_TESTF_SF_BOOTDEV);
+BOOTSTD_TEST(bootdev_test_next_prio, UTF_DM | UTF_SCAN_FDT | UTF_SF_BOOTDEV |
+ UTF_CONSOLE);
diff --git a/test/boot/bootflow.c b/test/boot/bootflow.c
index 8b46256..6ad63af 100644
--- a/test/boot/bootflow.c
+++ b/test/boot/bootflow.c
@@ -50,7 +50,6 @@
/* Check 'bootflow scan/list' commands */
static int bootflow_cmd(struct unit_test_state *uts)
{
- console_record_reset_enable();
ut_assertok(run_command("bootdev select 1", 0));
ut_assert_console_end();
ut_assertok(run_command("bootflow scan -lH", 0));
@@ -76,14 +75,13 @@
return 0;
}
-BOOTSTD_TEST(bootflow_cmd, UT_TESTF_DM | UT_TESTF_SCAN_FDT);
+BOOTSTD_TEST(bootflow_cmd, UTF_DM | UTF_SCAN_FDT | UTF_CONSOLE);
/* Check 'bootflow scan' with a label / seq */
static int bootflow_cmd_label(struct unit_test_state *uts)
{
test_set_eth_enable(false);
- console_record_reset_enable();
ut_assertok(run_command("bootflow scan -lH mmc1", 0));
ut_assert_nextline("Scanning for bootflows with label 'mmc1'");
ut_assert_skip_to_line("(1 bootflow, 1 valid)");
@@ -123,15 +121,14 @@
return 0;
}
-BOOTSTD_TEST(bootflow_cmd_label, UT_TESTF_DM | UT_TESTF_SCAN_FDT |
- UT_TESTF_ETH_BOOTDEV);
+BOOTSTD_TEST(bootflow_cmd_label, UTF_DM | UTF_SCAN_FDT | UTF_ETH_BOOTDEV |
+ UTF_CONSOLE);
/* Check 'bootflow scan/list' commands using all bootdevs */
static int bootflow_cmd_glob(struct unit_test_state *uts)
{
ut_assertok(bootstd_test_drop_bootdev_order(uts));
- console_record_reset_enable();
ut_assertok(run_command("bootflow scan -lGH", 0));
ut_assert_nextline("Scanning for bootflows in all bootdevs");
ut_assert_nextline("Seq Method State Uclass Part Name Filename");
@@ -156,14 +153,13 @@
return 0;
}
-BOOTSTD_TEST(bootflow_cmd_glob, UT_TESTF_DM | UT_TESTF_SCAN_FDT);
+BOOTSTD_TEST(bootflow_cmd_glob, UTF_DM | UTF_SCAN_FDT | UTF_CONSOLE);
/* Check 'bootflow scan -e' */
static int bootflow_cmd_scan_e(struct unit_test_state *uts)
{
ut_assertok(bootstd_test_drop_bootdev_order(uts));
- console_record_reset_enable();
ut_assertok(run_command("bootflow scan -aleGH", 0));
ut_assert_nextline("Scanning for bootflows in all bootdevs");
ut_assert_nextline("Seq Method State Uclass Part Name Filename");
@@ -207,12 +203,11 @@
return 0;
}
-BOOTSTD_TEST(bootflow_cmd_scan_e, UT_TESTF_DM | UT_TESTF_SCAN_FDT);
+BOOTSTD_TEST(bootflow_cmd_scan_e, UTF_DM | UTF_SCAN_FDT | UTF_CONSOLE);
/* Check 'bootflow info' */
static int bootflow_cmd_info(struct unit_test_state *uts)
{
- console_record_reset_enable();
ut_assertok(run_command("bootdev select 1", 0));
ut_assert_console_end();
ut_assertok(run_command("bootflow scan", 0));
@@ -248,12 +243,11 @@
return 0;
}
-BOOTSTD_TEST(bootflow_cmd_info, UT_TESTF_DM | UT_TESTF_SCAN_FDT);
+BOOTSTD_TEST(bootflow_cmd_info, UTF_DM | UTF_SCAN_FDT | UTF_CONSOLE);
/* Check 'bootflow scan -b' to boot the first available bootdev */
static int bootflow_scan_boot(struct unit_test_state *uts)
{
- console_record_reset_enable();
ut_assertok(inject_response(uts));
ut_assertok(run_command("bootflow scan -b", 0));
ut_assert_nextline(
@@ -270,7 +264,7 @@
return 0;
}
-BOOTSTD_TEST(bootflow_scan_boot, UT_TESTF_DM | UT_TESTF_SCAN_FDT);
+BOOTSTD_TEST(bootflow_scan_boot, UTF_DM | UTF_SCAN_FDT | UTF_CONSOLE);
/* Check iterating through available bootflows */
static int bootflow_iter(struct unit_test_state *uts)
@@ -368,7 +362,7 @@
return 0;
}
-BOOTSTD_TEST(bootflow_iter, UT_TESTF_DM | UT_TESTF_SCAN_FDT);
+BOOTSTD_TEST(bootflow_iter, UTF_DM | UTF_SCAN_FDT);
#if defined(CONFIG_SANDBOX) && defined(CONFIG_BOOTMETH_GLOBAL)
/* Check using the system bootdev */
@@ -386,7 +380,6 @@
/* We should get a single 'bootmgr' method right at the end */
bootstd_clear_glob();
- console_record_reset_enable();
ut_assertok(run_command("bootflow scan -lH", 0));
ut_assert_skip_to_line(
" 0 efi_mgr ready (none) 0 <NULL> ");
@@ -396,8 +389,8 @@
return 0;
}
-BOOTSTD_TEST(bootflow_system, UT_TESTF_DM | UT_TESTF_SCAN_PDATA |
- UT_TESTF_SCAN_FDT);
+BOOTSTD_TEST(bootflow_system, UTF_DM | UTF_SCAN_PDATA | UTF_SCAN_FDT |
+ UTF_CONSOLE);
#endif
/* Check disabling a bootmethod if it requests it */
@@ -416,7 +409,6 @@
ut_assertok(bootstd_test_drop_bootdev_order(uts));
bootstd_clear_glob();
- console_record_reset_enable();
ut_assertok(inject_response(uts));
ut_assertok(run_command("bootflow scan -lbH", 0));
@@ -438,7 +430,7 @@
return 0;
}
-BOOTSTD_TEST(bootflow_iter_disable, UT_TESTF_DM | UT_TESTF_SCAN_FDT);
+BOOTSTD_TEST(bootflow_iter_disable, UTF_DM | UTF_SCAN_FDT | UTF_CONSOLE);
/* Check 'bootflow scan' with a bootmeth ordering including a global bootmeth */
static int bootflow_scan_glob_bootmeth(struct unit_test_state *uts)
@@ -452,7 +444,6 @@
* Make sure that the -G flag makes the scan fail, since this is not
* supported when an ordering is provided
*/
- console_record_reset_enable();
ut_assertok(bootmeth_set_order("efi firmware0"));
ut_assertok(run_command("bootflow scan -lGH", 0));
ut_assert_nextline("Scanning for bootflows in all bootdevs");
@@ -479,12 +470,12 @@
return 0;
}
-BOOTSTD_TEST(bootflow_scan_glob_bootmeth, UT_TESTF_DM | UT_TESTF_SCAN_FDT);
+BOOTSTD_TEST(bootflow_scan_glob_bootmeth, UTF_DM | UTF_SCAN_FDT |
+ UTF_CONSOLE);
/* Check 'bootflow boot' to boot a selected bootflow */
static int bootflow_cmd_boot(struct unit_test_state *uts)
{
- console_record_reset_enable();
ut_assertok(run_command("bootdev select 1", 0));
ut_assert_console_end();
ut_assertok(run_command("bootflow scan", 0));
@@ -508,7 +499,7 @@
return 0;
}
-BOOTSTD_TEST(bootflow_cmd_boot, UT_TESTF_DM | UT_TESTF_SCAN_FDT);
+BOOTSTD_TEST(bootflow_cmd_boot, UTF_DM | UTF_SCAN_FDT | UTF_CONSOLE);
/**
* prep_mmc_bootdev() - Set up an mmc bootdev so we can access other distros
@@ -585,7 +576,6 @@
ut_assertok(prep_mmc_bootdev(uts, mmc_dev, bind_cros, &old_order));
- console_record_reset_enable();
ut_assertok(run_command("bootflow scan", 0));
ut_assert_console_end();
@@ -613,7 +603,6 @@
ut_assertok(prep_mmc_bootdev(uts, mmc_dev, true, &old_order));
- console_record_reset_enable();
ut_assertok(run_command("bootflow scan", 0));
/* Android bootflow might print one or two 'ANDROID:*' logs */
ut_check_skipline(uts);
@@ -675,7 +664,7 @@
return 0;
}
-BOOTSTD_TEST(bootflow_cmd_menu, UT_TESTF_DM | UT_TESTF_SCAN_FDT);
+BOOTSTD_TEST(bootflow_cmd_menu, UTF_DM | UTF_SCAN_FDT | UTF_CONSOLE);
/* Check 'bootflow scan -m' to select a bootflow using a menu */
static int bootflow_scan_menu(struct unit_test_state *uts)
@@ -723,8 +712,7 @@
return 0;
}
-BOOTSTD_TEST(bootflow_scan_menu,
- UT_TESTF_DM | UT_TESTF_SCAN_FDT | UT_TESTF_CONSOLE_REC);
+BOOTSTD_TEST(bootflow_scan_menu, UTF_DM | UTF_SCAN_FDT | UTF_CONSOLE);
/* Check 'bootflow scan -mb' to select and boot a bootflow using a menu */
static int bootflow_scan_menu_boot(struct unit_test_state *uts)
@@ -770,8 +758,7 @@
return 0;
}
-BOOTSTD_TEST(bootflow_scan_menu_boot,
- UT_TESTF_DM | UT_TESTF_SCAN_FDT | UT_TESTF_CONSOLE_REC);
+BOOTSTD_TEST(bootflow_scan_menu_boot, UTF_DM | UTF_SCAN_FDT | UTF_CONSOLE);
/* Check searching for a single bootdev using the hunters */
static int bootflow_cmd_hunt_single(struct unit_test_state *uts)
@@ -783,7 +770,6 @@
ut_assertok(bootstd_test_drop_bootdev_order(uts));
- console_record_reset_enable();
ut_assertok(run_command("bootflow scan -l mmc1", 0));
ut_assert_nextline("Scanning for bootflows with label 'mmc1'");
ut_assert_skip_to_line("(1 bootflow, 1 valid)");
@@ -794,7 +780,8 @@
return 0;
}
-BOOTSTD_TEST(bootflow_cmd_hunt_single, UT_TESTF_DM | UT_TESTF_SCAN_FDT);
+BOOTSTD_TEST(bootflow_cmd_hunt_single, UTF_DM | UTF_SCAN_FDT |
+ UTF_CONSOLE);
/* Check searching for a uclass label using the hunters */
static int bootflow_cmd_hunt_label(struct unit_test_state *uts)
@@ -808,7 +795,6 @@
test_set_eth_enable(false);
ut_assertok(bootstd_test_drop_bootdev_order(uts));
- console_record_reset_enable();
ut_assertok(run_command("bootflow scan -l mmc", 0));
/* check that the hunter was used */
@@ -831,7 +817,7 @@
return 0;
}
-BOOTSTD_TEST(bootflow_cmd_hunt_label, UT_TESTF_DM | UT_TESTF_SCAN_FDT);
+BOOTSTD_TEST(bootflow_cmd_hunt_label, UTF_DM | UTF_SCAN_FDT | UTF_CONSOLE);
/**
* check_font() - Check that the font size for an item matches expectations
@@ -891,7 +877,7 @@
return 0;
}
-BOOTSTD_TEST(bootflow_menu_theme, UT_TESTF_DM | UT_TESTF_SCAN_FDT);
+BOOTSTD_TEST(bootflow_menu_theme, UTF_DM | UTF_SCAN_FDT | UTF_CONSOLE);
/**
* check_arg() - Check both the normal case and the buffer-overflow case
@@ -1127,7 +1113,6 @@
{
ut_assertok(run_command("bootflow scan mmc", 0));
ut_assertok(run_command("bootflow sel 0", 0));
- console_record_reset_enable();
ut_asserteq(1, run_command("bootflow cmdline get fred", 0));
ut_assert_nextline("Argument not found");
@@ -1151,13 +1136,11 @@
ut_asserteq(0, run_command("bootflow cmdline set mary abc", 0));
ut_asserteq(0, run_command("bootflow cmdline set mary", 0));
- ut_assert_nextline_empty();
-
ut_assert_console_end();
return 0;
}
-BOOTSTD_TEST(bootflow_cmdline, 0);
+BOOTSTD_TEST(bootflow_cmdline, UTF_CONSOLE);
/* test a few special changes to a long command line */
static int bootflow_cmdline_special(struct unit_test_state *uts)
@@ -1198,7 +1181,7 @@
return 0;
}
-BOOTSTD_TEST(bootflow_cros, 0);
+BOOTSTD_TEST(bootflow_cros, UTF_CONSOLE);
/* Test Android bootmeth */
static int bootflow_android(struct unit_test_state *uts)
@@ -1221,4 +1204,4 @@
return 0;
}
-BOOTSTD_TEST(bootflow_android, 0);
+BOOTSTD_TEST(bootflow_android, UTF_CONSOLE);
diff --git a/test/boot/bootmeth.c b/test/boot/bootmeth.c
index 113b789..518d99c 100644
--- a/test/boot/bootmeth.c
+++ b/test/boot/bootmeth.c
@@ -16,7 +16,6 @@
/* Check 'bootmeth list' command */
static int bootmeth_cmd_list(struct unit_test_state *uts)
{
- console_record_reset_enable();
ut_assertok(run_command("bootmeth list", 0));
ut_assert_nextline("Order Seq Name Description");
ut_assert_nextlinen("---");
@@ -31,13 +30,12 @@
return 0;
}
-BOOTSTD_TEST(bootmeth_cmd_list, UT_TESTF_DM | UT_TESTF_SCAN_FDT);
+BOOTSTD_TEST(bootmeth_cmd_list, UTF_DM | UTF_SCAN_FDT | UTF_CONSOLE);
/* Check 'bootmeth order' command */
static int bootmeth_cmd_order(struct unit_test_state *uts)
{
/* Select just one bootmethod */
- console_record_reset_enable();
ut_assertok(run_command("bootmeth order extlinux", 0));
ut_assert_console_end();
ut_assertnonnull(env_get("bootmeths"));
@@ -104,7 +102,7 @@
return 0;
}
-BOOTSTD_TEST(bootmeth_cmd_order, UT_TESTF_DM | UT_TESTF_SCAN_FDT);
+BOOTSTD_TEST(bootmeth_cmd_order, UTF_DM | UTF_SCAN_FDT | UTF_CONSOLE);
/* Check 'bootmeth order' command with global bootmeths */
static int bootmeth_cmd_order_glob(struct unit_test_state *uts)
@@ -112,7 +110,6 @@
if (!IS_ENABLED(CONFIG_BOOTMETH_GLOBAL))
return -EAGAIN;
- console_record_reset_enable();
ut_assertok(run_command("bootmeth order \"efi firmware0\"", 0));
ut_assert_console_end();
ut_assertok(run_command("bootmeth list", 0));
@@ -128,7 +125,7 @@
return 0;
}
-BOOTSTD_TEST(bootmeth_cmd_order_glob, UT_TESTF_DM | UT_TESTF_SCAN_FDT);
+BOOTSTD_TEST(bootmeth_cmd_order_glob, UTF_DM | UTF_SCAN_FDT | UTF_CONSOLE);
/* Check 'bootmeths' env var */
static int bootmeth_env(struct unit_test_state *uts)
@@ -138,7 +135,6 @@
ut_assertok(bootstd_get_priv(&std));
/* Select just one bootmethod */
- console_record_reset_enable();
ut_assertok(env_set("bootmeths", "extlinux"));
ut_asserteq(1, std->bootmeth_count);
@@ -154,7 +150,7 @@
return 0;
}
-BOOTSTD_TEST(bootmeth_env, UT_TESTF_DM | UT_TESTF_SCAN_FDT);
+BOOTSTD_TEST(bootmeth_env, UTF_DM | UTF_SCAN_FDT | UTF_CONSOLE);
/* Check the get_state_desc() method */
static int bootmeth_state(struct unit_test_state *uts)
@@ -170,4 +166,4 @@
return 0;
}
-BOOTSTD_TEST(bootmeth_state, UT_TESTF_DM | UT_TESTF_SCAN_FDT);
+BOOTSTD_TEST(bootmeth_state, UTF_DM | UTF_SCAN_FDT);
diff --git a/test/boot/cedit.c b/test/boot/cedit.c
index fd19da0..1f7af8e 100644
--- a/test/boot/cedit.c
+++ b/test/boot/cedit.c
@@ -25,8 +25,6 @@
ut_assertok(run_command("cedit load hostfs - cedit.dtb", 0));
- console_record_reset_enable();
-
/*
* ^N Move down to second menu
* ^M Open menu
@@ -52,7 +50,7 @@
return 0;
}
-BOOTSTD_TEST(cedit_base, 0);
+BOOTSTD_TEST(cedit_base, UTF_CONSOLE);
/* Check the cedit write_fdt and read_fdt commands */
static int cedit_fdt(struct unit_test_state *uts)
@@ -70,7 +68,6 @@
void *fdt;
int i;
- console_record_reset_enable();
ut_assertok(run_command("cedit load hostfs - cedit.dtb", 0));
ut_asserteq(ID_SCENE1, cedit_prepare(cur_exp, &vid_priv, &scn));
@@ -122,7 +119,7 @@
return 0;
}
-BOOTSTD_TEST(cedit_fdt, 0);
+BOOTSTD_TEST(cedit_fdt, UTF_CONSOLE);
/* Check the cedit write_env and read_env commands */
static int cedit_env(struct unit_test_state *uts)
@@ -134,7 +131,6 @@
struct scene *scn;
char *str;
- console_record_reset_enable();
ut_assertok(run_command("cedit load hostfs - cedit.dtb", 0));
ut_asserteq(ID_SCENE1, cedit_prepare(cur_exp, &vid_priv, &scn));
@@ -177,7 +173,7 @@
return 0;
}
-BOOTSTD_TEST(cedit_env, 0);
+BOOTSTD_TEST(cedit_env, UTF_CONSOLE);
/* Check the cedit write_cmos and read_cmos commands */
static int cedit_cmos(struct unit_test_state *uts)
@@ -187,7 +183,6 @@
extern struct expo *cur_exp;
struct scene *scn;
- console_record_reset_enable();
ut_assertok(run_command("cedit load hostfs - cedit.dtb", 0));
ut_asserteq(ID_SCENE1, cedit_prepare(cur_exp, &vid_priv, &scn));
@@ -218,4 +213,4 @@
return 0;
}
-BOOTSTD_TEST(cedit_cmos, 0);
+BOOTSTD_TEST(cedit_cmos, UTF_CONSOLE);
diff --git a/test/boot/expo.c b/test/boot/expo.c
index 6ea0184..4b24f50 100644
--- a/test/boot/expo.c
+++ b/test/boot/expo.c
@@ -114,7 +114,7 @@
return 0;
}
-BOOTSTD_TEST(expo_base, UT_TESTF_DM | UT_TESTF_SCAN_FDT);
+BOOTSTD_TEST(expo_base, UTF_DM | UTF_SCAN_FDT);
/* Check creating a scene */
static int expo_scene(struct unit_test_state *uts)
@@ -165,7 +165,7 @@
return 0;
}
-BOOTSTD_TEST(expo_scene, UT_TESTF_DM | UT_TESTF_SCAN_FDT);
+BOOTSTD_TEST(expo_scene, UTF_DM | UTF_SCAN_FDT);
/* Check creating a scene with objects */
static int expo_object(struct unit_test_state *uts)
@@ -225,7 +225,7 @@
return 0;
}
-BOOTSTD_TEST(expo_object, UT_TESTF_DM | UT_TESTF_SCAN_FDT);
+BOOTSTD_TEST(expo_object, UTF_DM | UTF_SCAN_FDT);
/* Check setting object attributes and using themes */
static int expo_object_attr(struct unit_test_state *uts)
@@ -286,7 +286,7 @@
return 0;
}
-BOOTSTD_TEST(expo_object_attr, UT_TESTF_DM | UT_TESTF_SCAN_FDT);
+BOOTSTD_TEST(expo_object_attr, UTF_DM | UTF_SCAN_FDT);
/**
* struct test_iter_priv - private data for expo-iterator test
@@ -432,7 +432,7 @@
return 0;
}
-BOOTSTD_TEST(expo_object_menu, UT_TESTF_DM | UT_TESTF_SCAN_FDT);
+BOOTSTD_TEST(expo_object_menu, UTF_DM | UTF_SCAN_FDT);
/* Check rendering a scene */
static int expo_render_image(struct unit_test_state *uts)
@@ -445,7 +445,6 @@
struct expo *exp;
int id;
- console_record_reset_enable();
ut_assertok(uclass_first_device_err(UCLASS_VIDEO, &dev));
ut_assertok(expo_new(EXPO_NAME, NULL, &exp));
@@ -633,7 +632,7 @@
return 0;
}
-BOOTSTD_TEST(expo_render_image, UT_TESTF_DM | UT_TESTF_SCAN_FDT);
+BOOTSTD_TEST(expo_render_image, UTF_DM | UTF_SCAN_FDT | UTF_CONSOLE);
/* Check building an expo from a devicetree description */
static int expo_test_build(struct unit_test_state *uts)
@@ -712,4 +711,4 @@
return 0;
}
-BOOTSTD_TEST(expo_test_build, UT_TESTF_DM);
+BOOTSTD_TEST(expo_test_build, UTF_DM);
diff --git a/test/boot/upl.c b/test/boot/upl.c
new file mode 100644
index 0000000..99f02b7
--- /dev/null
+++ b/test/boot/upl.c
@@ -0,0 +1,437 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * UPL handoff testing
+ *
+ * Copyright 2024 Google LLC
+ * Written by Simon Glass <sjg@chromium.org>
+ */
+
+#include <abuf.h>
+#include <mapmem.h>
+#include <upl.h>
+#include <dm/ofnode.h>
+#include <test/suites.h>
+#include <test/test.h>
+#include <test/ut.h>
+#include "bootstd_common.h"
+
+/* Declare a new upl test */
+#define UPL_TEST(_name, _flags) UNIT_TEST(_name, _flags, upl_test)
+
+static int add_region(struct unit_test_state *uts, struct alist *lst,
+ ulong base, ulong size)
+{
+ struct memregion region;
+
+ region.base = base;
+ region.size = size;
+ ut_assertnonnull(alist_add(lst, region));
+
+ return 0;
+}
+
+int upl_get_test_data(struct unit_test_state *uts, struct upl *upl)
+{
+ struct upl_memmap memmap;
+ struct upl_memres memres;
+ struct upl_image img;
+ struct upl_mem mem;
+
+ upl_init(upl);
+
+ upl->addr_cells = 1;
+ upl->size_cells = 1;
+ upl->smbios = 0x123;
+ upl->acpi = 0x456;
+ upl->bootmode = BIT(UPLBM_DEFAULT) | BIT(UPLBM_S3);
+ upl->fit = 0x789;
+ upl->conf_offset = 0x234;
+ upl->addr_width = 46;
+ upl->acpi_nvs_size = 0x100;
+
+ /* image[0] */
+ img.load = 0x1;
+ img.size = 0x2;
+ img.offset = 0x3;
+ img.description = "U-Boot";
+ ut_assertnonnull(alist_add(&upl->image, img));
+
+ /* image[1] */
+ img.load = 0x4;
+ img.size = 0x5;
+ img.offset = 0x6;
+ img.description = "ATF";
+ ut_assertnonnull(alist_add(&upl->image, img));
+
+ /* mem[0] : 3 regions */
+ memset(&mem, '\0', sizeof(mem));
+ alist_init_struct(&mem.region, struct memregion);
+ ut_assertok(add_region(uts, &mem.region, 0x10, 0x20));
+ ut_assertok(add_region(uts, &mem.region, 0x30, 0x40));
+ ut_assertok(add_region(uts, &mem.region, 0x40, 0x50));
+ ut_assertnonnull(alist_add(&upl->mem, mem));
+
+ /* mem[0] : 1 region */
+ alist_init_struct(&mem.region, struct memregion);
+ ut_assertok(add_region(uts, &mem.region, 0x70, 0x80));
+ mem.hotpluggable = true;
+ ut_assertnonnull(alist_add(&upl->mem, mem));
+ mem.hotpluggable = false;
+
+ /* memmap[0] : 5 regions */
+ alist_init_struct(&memmap.region, struct memregion);
+ memmap.name = "acpi";
+ memmap.usage = BIT(UPLUS_ACPI_RECLAIM);
+ ut_assertok(add_region(uts, &memmap.region, 0x11, 0x12));
+ ut_assertok(add_region(uts, &memmap.region, 0x13, 0x14));
+ ut_assertok(add_region(uts, &memmap.region, 0x15, 0x16));
+ ut_assertok(add_region(uts, &memmap.region, 0x17, 0x18));
+ ut_assertok(add_region(uts, &memmap.region, 0x19, 0x1a));
+ ut_assertnonnull(alist_add(&upl->memmap, memmap));
+
+ /* memmap[1] : 1 region */
+ memmap.name = "u-boot";
+ memmap.usage = BIT(UPLUS_BOOT_DATA);
+ alist_init_struct(&memmap.region, struct memregion);
+ ut_assertok(add_region(uts, &memmap.region, 0x21, 0x22));
+ ut_assertnonnull(alist_add(&upl->memmap, memmap));
+
+ /* memmap[2] : 1 region */
+ alist_init_struct(&memmap.region, struct memregion);
+ memmap.name = "efi";
+ memmap.usage = BIT(UPLUS_RUNTIME_CODE);
+ ut_assertok(add_region(uts, &memmap.region, 0x23, 0x24));
+ ut_assertnonnull(alist_add(&upl->memmap, memmap));
+
+ /* memmap[3]: 2 regions */
+ alist_init_struct(&memmap.region, struct memregion);
+ memmap.name = "empty";
+ memmap.usage = 0;
+ ut_assertok(add_region(uts, &memmap.region, 0x25, 0x26));
+ ut_assertok(add_region(uts, &memmap.region, 0x27, 0x28));
+ ut_assertnonnull(alist_add(&upl->memmap, memmap));
+
+ /* memmap[4]: 1 region */
+ alist_init_struct(&memmap.region, struct memregion);
+ memmap.name = "acpi-things";
+ memmap.usage = BIT(UPLUS_RUNTIME_CODE) | BIT(UPLUS_ACPI_NVS);
+ ut_assertok(add_region(uts, &memmap.region, 0x29, 0x2a));
+ ut_assertnonnull(alist_add(&upl->memmap, memmap));
+
+ /* memres[0]: 1 region */
+ alist_init_struct(&memres.region, struct memregion);
+ memset(&memres, '\0', sizeof(memres));
+ memres.name = "mmio";
+ ut_assertok(add_region(uts, &memres.region, 0x2b, 0x2c));
+ ut_assertnonnull(alist_add(&upl->memres, memres));
+
+ /* memres[1]: 2 regions */
+ alist_init_struct(&memres.region, struct memregion);
+ memres.name = "memory";
+ ut_assertok(add_region(uts, &memres.region, 0x2d, 0x2e));
+ ut_assertok(add_region(uts, &memres.region, 0x2f, 0x30));
+ memres.no_map = true;
+ ut_assertnonnull(alist_add(&upl->memres, memres));
+
+ upl->serial.compatible = "ns16550a";
+ upl->serial.clock_frequency = 1843200;
+ upl->serial.current_speed = 115200;
+ alist_init_struct(&upl->serial.reg, struct memregion);
+ ut_assertok(add_region(uts, &upl->serial.reg, 0xf1de0000, 0x100));
+ upl->serial.reg_io_shift = 2;
+ upl->serial.reg_offset = 0x40;
+ upl->serial.reg_io_width = 1;
+ upl->serial.virtual_reg = 0x20000000;
+ upl->serial.access_type = UPLSAT_MMIO;
+
+ alist_init_struct(&upl->graphics.reg, struct memregion);
+ ut_assertok(add_region(uts, &upl->graphics.reg, 0xd0000000, 0x10000000));
+ upl->graphics.width = 1280;
+ upl->graphics.height = 1280;
+ upl->graphics.stride = upl->graphics.width * 4;
+ upl->graphics.format = UPLGF_ARGB32;
+
+ return 0;
+}
+
+static int compare_upl_image(struct unit_test_state *uts,
+ const struct upl_image *base,
+ const struct upl_image *cmp)
+{
+ ut_asserteq(base->load, cmp->load);
+ ut_asserteq(base->size, cmp->size);
+ ut_asserteq(base->offset, cmp->offset);
+ ut_asserteq_str(base->description, cmp->description);
+
+ return 0;
+}
+
+static int compare_upl_memregion(struct unit_test_state *uts,
+ const struct memregion *base,
+ const struct memregion *cmp)
+{
+ ut_asserteq(base->base, cmp->base);
+ ut_asserteq(base->size, cmp->size);
+
+ return 0;
+}
+
+static int compare_upl_mem(struct unit_test_state *uts,
+ const struct upl_mem *base,
+ const struct upl_mem *cmp)
+{
+ int i;
+
+ ut_asserteq(base->region.count, cmp->region.count);
+ ut_asserteq(base->hotpluggable, cmp->hotpluggable);
+ for (i = 0; i < base->region.count; i++) {
+ ut_assertok(compare_upl_memregion(uts,
+ alist_get(&base->region, i, struct memregion),
+ alist_get(&cmp->region, i, struct memregion)));
+ }
+
+ return 0;
+}
+
+static int check_device_name(struct unit_test_state *uts, const char *base,
+ const char *cmp)
+{
+ const char *p;
+
+ p = strchr(cmp, '@');
+ if (p) {
+ ut_assertnonnull(p);
+ ut_asserteq_strn(base, cmp);
+ ut_asserteq(p - cmp, strlen(base));
+ } else {
+ ut_asserteq_str(base, cmp);
+ }
+
+ return 0;
+}
+
+static int compare_upl_memmap(struct unit_test_state *uts,
+ const struct upl_memmap *base,
+ const struct upl_memmap *cmp)
+{
+ int i;
+
+ ut_assertok(check_device_name(uts, base->name, cmp->name));
+ ut_asserteq(base->region.count, cmp->region.count);
+ ut_asserteq(base->usage, cmp->usage);
+ for (i = 0; i < base->region.count; i++)
+ ut_assertok(compare_upl_memregion(uts,
+ alist_get(&base->region, i, struct memregion),
+ alist_get(&cmp->region, i, struct memregion)));
+
+ return 0;
+}
+
+static int compare_upl_memres(struct unit_test_state *uts,
+ const struct upl_memres *base,
+ const struct upl_memres *cmp)
+{
+ int i;
+
+ ut_assertok(check_device_name(uts, base->name, cmp->name));
+ ut_asserteq(base->region.count, cmp->region.count);
+ ut_asserteq(base->no_map, cmp->no_map);
+ for (i = 0; i < base->region.count; i++)
+ ut_assertok(compare_upl_memregion(uts,
+ alist_get(&base->region, i, struct memregion),
+ alist_get(&cmp->region, i, struct memregion)));
+
+ return 0;
+}
+
+static int compare_upl_serial(struct unit_test_state *uts,
+ struct upl_serial *base, struct upl_serial *cmp)
+{
+ int i;
+
+ ut_asserteq_str(base->compatible, cmp->compatible);
+ ut_asserteq(base->clock_frequency, cmp->clock_frequency);
+ ut_asserteq(base->current_speed, cmp->current_speed);
+ for (i = 0; i < base->reg.count; i++)
+ ut_assertok(compare_upl_memregion(uts,
+ alist_get(&base->reg, i, struct memregion),
+ alist_get(&cmp->reg, i, struct memregion)));
+ ut_asserteq(base->reg_io_shift, cmp->reg_io_shift);
+ ut_asserteq(base->reg_offset, cmp->reg_offset);
+ ut_asserteq(base->reg_io_width, cmp->reg_io_width);
+ ut_asserteq(base->virtual_reg, cmp->virtual_reg);
+ ut_asserteq(base->access_type, cmp->access_type);
+
+ return 0;
+}
+
+static int compare_upl_graphics(struct unit_test_state *uts,
+ struct upl_graphics *base,
+ struct upl_graphics *cmp)
+{
+ int i;
+
+ for (i = 0; i < base->reg.count; i++)
+ ut_assertok(compare_upl_memregion(uts,
+ alist_get(&base->reg, i, struct memregion),
+ alist_get(&cmp->reg, i, struct memregion)));
+ ut_asserteq(base->width, cmp->width);
+ ut_asserteq(base->height, cmp->height);
+ ut_asserteq(base->stride, cmp->stride);
+ ut_asserteq(base->format, cmp->format);
+
+ return 0;
+}
+
+static int compare_upl(struct unit_test_state *uts, struct upl *base,
+ struct upl *cmp)
+{
+ int i;
+
+ ut_asserteq(base->addr_cells, cmp->addr_cells);
+ ut_asserteq(base->size_cells, cmp->size_cells);
+
+ ut_asserteq(base->smbios, cmp->smbios);
+ ut_asserteq(base->acpi, cmp->acpi);
+ ut_asserteq(base->bootmode, cmp->bootmode);
+ ut_asserteq(base->fit, cmp->fit);
+ ut_asserteq(base->conf_offset, cmp->conf_offset);
+ ut_asserteq(base->addr_width, cmp->addr_width);
+ ut_asserteq(base->acpi_nvs_size, cmp->acpi_nvs_size);
+
+ ut_asserteq(base->image.count, cmp->image.count);
+ for (i = 0; i < base->image.count; i++)
+ ut_assertok(compare_upl_image(uts,
+ alist_get(&base->image, i, struct upl_image),
+ alist_get(&cmp->image, i, struct upl_image)));
+
+ ut_asserteq(base->mem.count, cmp->mem.count);
+ for (i = 0; i < base->mem.count; i++)
+ ut_assertok(compare_upl_mem(uts,
+ alist_get(&base->mem, i, struct upl_mem),
+ alist_get(&cmp->mem, i, struct upl_mem)));
+
+ ut_asserteq(base->memmap.count, cmp->memmap.count);
+ for (i = 0; i < base->memmap.count; i++)
+ ut_assertok(compare_upl_memmap(uts,
+ alist_get(&base->memmap, i, struct upl_memmap),
+ alist_get(&cmp->memmap, i, struct upl_memmap)));
+
+ ut_asserteq(base->memres.count, cmp->memres.count);
+ for (i = 0; i < base->memres.count; i++)
+ ut_assertok(compare_upl_memres(uts,
+ alist_get(&base->memres, i, struct upl_memres),
+ alist_get(&cmp->memres, i, struct upl_memres)));
+
+ ut_assertok(compare_upl_serial(uts, &base->serial, &cmp->serial));
+ ut_assertok(compare_upl_graphics(uts, &base->graphics, &cmp->graphics));
+
+ return 0;
+}
+
+/* Basic test of writing and reading UPL handoff */
+static int upl_test_base(struct unit_test_state *uts)
+{
+ oftree tree, check_tree;
+ struct upl upl, check;
+ struct abuf buf;
+
+ if (!CONFIG_IS_ENABLED(OFNODE_MULTI_TREE))
+ return -EAGAIN; /* skip test */
+ ut_assertok(upl_get_test_data(uts, &upl));
+
+ ut_assertok(upl_create_handoff_tree(&upl, &tree));
+ ut_assertok(oftree_to_fdt(tree, &buf));
+
+ /*
+ * strings in check_tree and therefore check are only valid so long as
+ * buf stays around. As soon as we call abuf_uninit they go away
+ */
+ check_tree = oftree_from_fdt(abuf_data(&buf));
+ ut_assert(ofnode_valid(oftree_path(check_tree, "/")));
+
+ ut_assertok(upl_read_handoff(&check, check_tree));
+ ut_assertok(compare_upl(uts, &upl, &check));
+ abuf_uninit(&buf);
+
+ return 0;
+}
+UPL_TEST(upl_test_base, 0);
+
+/* Test 'upl info' command */
+static int upl_test_info(struct unit_test_state *uts)
+{
+ gd_set_upl(NULL);
+ ut_assertok(run_command("upl info", 0));
+ ut_assert_nextline("UPL state: inactive");
+ ut_assert_console_end();
+
+ gd_set_upl((struct upl *)uts); /* set it to any non-zero value */
+ ut_assertok(run_command("upl info", 0));
+ ut_assert_nextline("UPL state: active");
+ ut_assert_console_end();
+ gd_set_upl(NULL);
+
+ return 0;
+}
+UPL_TEST(upl_test_info, UTF_CONSOLE);
+
+/* Test 'upl read' and 'upl_write' commands */
+static int upl_test_read_write(struct unit_test_state *uts)
+{
+ ulong addr;
+
+ if (!CONFIG_IS_ENABLED(OFNODE_MULTI_TREE))
+ return -EAGAIN; /* skip test */
+ ut_assertok(run_command("upl write", 0));
+
+ addr = env_get_hex("upladdr", 0);
+ ut_assert_nextline("UPL handoff written to %lx size %lx", addr,
+ env_get_hex("uplsize", 0));
+ ut_assert_console_end();
+
+ ut_assertok(run_command("upl read ${upladdr}", 0));
+ ut_assert_nextline("Reading UPL at %lx", addr);
+ ut_assert_console_end();
+
+ return 0;
+}
+UPL_TEST(upl_test_read_write, UTF_CONSOLE);
+
+/* Test UPL passthrough */
+static int upl_test_info_norun(struct unit_test_state *uts)
+{
+ const struct upl_image *img;
+ struct upl *upl = gd_upl();
+ const void *fit;
+
+ ut_assertok(run_command("upl info -v", 0));
+ ut_assert_nextline("UPL state: active");
+ ut_assert_nextline("fit %lx", upl->fit);
+ ut_assert_nextline("conf_offset %x", upl->conf_offset);
+ ut_assert_nextlinen("image 0");
+ ut_assert_nextlinen("image 1");
+ ut_assert_console_end();
+
+ /* check the offsets */
+ fit = map_sysmem(upl->fit, 0);
+ ut_asserteq_str("conf-1", fdt_get_name(fit, upl->conf_offset, NULL));
+
+ ut_asserteq(2, upl->image.count);
+
+ img = alist_get(&upl->image, 1, struct upl_image);
+ ut_asserteq_str("firmware-1", fdt_get_name(fit, img->offset, NULL));
+ ut_asserteq(CONFIG_TEXT_BASE, img->load);
+
+ return 0;
+}
+UPL_TEST(upl_test_info_norun, UTF_CONSOLE | UTF_MANUAL);
+
+int do_ut_upl(struct cmd_tbl *cmdtp, int flag, int argc, char *const argv[])
+{
+ struct unit_test *tests = UNIT_TEST_SUITE_START(upl_test);
+ const int n_ents = UNIT_TEST_SUITE_COUNT(upl_test);
+
+ return cmd_ut_category("cmd_upl", "cmd_upl_", tests, n_ents, argc,
+ argv);
+}
diff --git a/test/boot/vbe_fixup.c b/test/boot/vbe_fixup.c
index 540816e..5bc026d 100644
--- a/test/boot/vbe_fixup.c
+++ b/test/boot/vbe_fixup.c
@@ -51,5 +51,5 @@
return 0;
}
-BOOTSTD_TEST(vbe_test_fixup_norun, UT_TESTF_DM | UT_TESTF_SCAN_FDT |
- UT_TESTF_FLAT_TREE | UT_TESTF_MANUAL);
+BOOTSTD_TEST(vbe_test_fixup_norun, UTF_DM | UTF_SCAN_FDT | UTF_FLAT_TREE |
+ UTF_MANUAL);
diff --git a/test/boot/vbe_simple.c b/test/boot/vbe_simple.c
index 3672b74..4fe4323 100644
--- a/test/boot/vbe_simple.c
+++ b/test/boot/vbe_simple.c
@@ -85,4 +85,4 @@
return 0;
}
-BOOTSTD_TEST(vbe_simple_test_base, UT_TESTF_DM | UT_TESTF_SCAN_FDT);
+BOOTSTD_TEST(vbe_simple_test_base, UTF_DM | UTF_SCAN_FDT);
diff --git a/test/cmd/Makefile b/test/cmd/Makefile
index 478ef4c..8f21349 100644
--- a/test/cmd/Makefile
+++ b/test/cmd/Makefile
@@ -30,7 +30,7 @@
obj-$(CONFIG_CMD_MBR) += mbr.o
obj-$(CONFIG_CMD_READ) += rw.o
obj-$(CONFIG_CMD_SETEXPR) += setexpr.o
+obj-$(CONFIG_CMD_WGET) += wget.o
obj-$(CONFIG_ARM_FFA_TRANSPORT) += armffa.o
endif
obj-$(CONFIG_CMD_TEMPERATURE) += temperature.o
-obj-$(CONFIG_CMD_WGET) += wget.o
diff --git a/test/cmd/addrmap.c b/test/cmd/addrmap.c
index 7b8f49f..b34be89 100644
--- a/test/cmd/addrmap.c
+++ b/test/cmd/addrmap.c
@@ -15,7 +15,6 @@
/* Test 'addrmap' command output */
static int addrmap_test_basic(struct unit_test_state *uts)
{
- ut_assertok(console_record_reset_enable());
ut_assertok(run_command("addrmap", 0));
ut_assert_nextline(" vaddr paddr size");
ut_assert_nextline("================ ================ ================");
@@ -24,7 +23,7 @@
return 0;
}
-ADDRMAP_TEST(addrmap_test_basic, UT_TESTF_CONSOLE_REC);
+ADDRMAP_TEST(addrmap_test_basic, UTF_CONSOLE);
int do_ut_addrmap(struct cmd_tbl *cmdtp, int flag, int argc, char *const argv[])
{
diff --git a/test/cmd/armffa.c b/test/cmd/armffa.c
index 38f40b7..fd578f3 100644
--- a/test/cmd/armffa.c
+++ b/test/cmd/armffa.c
@@ -28,5 +28,4 @@
return 0;
}
-
-DM_TEST(dm_test_armffa_cmd, UT_TESTF_SCAN_FDT | UT_TESTF_CONSOLE_REC);
+DM_TEST(dm_test_armffa_cmd, UTF_SCAN_FDT | UTF_CONSOLE);
diff --git a/test/cmd/bdinfo.c b/test/cmd/bdinfo.c
index 027848c..e624226 100644
--- a/test/cmd/bdinfo.c
+++ b/test/cmd/bdinfo.c
@@ -185,9 +185,6 @@
ut_assert(map_to_sysmem(gd->fdt_blob) == env_get_hex("fdtcontroladdr", 0x1234));
ut_assertok(test_num_l(uts, "fdt_blob",
(ulong)map_to_sysmem(gd->fdt_blob)));
- ut_assertok(test_num_l(uts, "new_fdt",
- (ulong)map_to_sysmem(gd->new_fdt)));
- ut_assertok(test_num_l(uts, "fdt_size", (ulong)gd->fdt_size));
if (IS_ENABLED(CONFIG_VIDEO))
ut_assertok(test_video_info(uts));
@@ -235,22 +232,19 @@
static int bdinfo_test_full(struct unit_test_state *uts)
{
/* Test BDINFO full print */
- ut_assertok(console_record_reset_enable());
ut_assertok(run_commandf("bdinfo"));
ut_assertok(bdinfo_test_all(uts));
ut_assertok(run_commandf("bdinfo -a"));
ut_assertok(bdinfo_test_all(uts));
- ut_assertok(ut_check_console_end(uts));
+ ut_assert_console_end();
return 0;
}
-
-BDINFO_TEST(bdinfo_test_full, UT_TESTF_CONSOLE_REC);
+BDINFO_TEST(bdinfo_test_full, UTF_CONSOLE);
static int bdinfo_test_help(struct unit_test_state *uts)
{
/* Test BDINFO unknown option help text print */
- ut_assertok(console_record_reset_enable());
if (!CONFIG_IS_ENABLED(GETOPT)) {
ut_asserteq(0, run_commandf("bdinfo -h"));
ut_assertok(bdinfo_test_all(uts));
@@ -262,44 +256,39 @@
ut_assert_nextlinen("Usage:");
ut_assert_nextlinen("bdinfo");
}
- ut_assertok(ut_check_console_end(uts));
+ ut_assert_console_end();
return 0;
}
-
-BDINFO_TEST(bdinfo_test_help, UT_TESTF_CONSOLE_REC);
+BDINFO_TEST(bdinfo_test_help, UTF_CONSOLE);
static int bdinfo_test_memory(struct unit_test_state *uts)
{
/* Test BDINFO memory layout only print */
- ut_assertok(console_record_reset_enable());
ut_assertok(run_commandf("bdinfo -m"));
if (!CONFIG_IS_ENABLED(GETOPT))
ut_assertok(bdinfo_test_all(uts));
else
ut_assertok(bdinfo_check_mem(uts));
- ut_assertok(ut_check_console_end(uts));
+ ut_assert_console_end();
return 0;
}
-
-BDINFO_TEST(bdinfo_test_memory, UT_TESTF_CONSOLE_REC);
+BDINFO_TEST(bdinfo_test_memory, UTF_CONSOLE);
static int bdinfo_test_eth(struct unit_test_state *uts)
{
/* Test BDINFO ethernet settings only print */
- ut_assertok(console_record_reset_enable());
ut_assertok(run_commandf("bdinfo -e"));
if (!CONFIG_IS_ENABLED(GETOPT))
ut_assertok(bdinfo_test_all(uts));
else if (IS_ENABLED(CONFIG_CMD_NET))
ut_assertok(test_eth(uts));
- ut_assertok(ut_check_console_end(uts));
+ ut_assert_console_end();
return 0;
}
-
-BDINFO_TEST(bdinfo_test_eth, UT_TESTF_CONSOLE_REC);
+BDINFO_TEST(bdinfo_test_eth, UTF_CONSOLE);
int do_ut_bdinfo(struct cmd_tbl *cmdtp, int flag, int argc, char *const argv[])
{
diff --git a/test/cmd/exit.c b/test/cmd/exit.c
index d310ec8..af58a57 100644
--- a/test/cmd/exit.c
+++ b/test/cmd/exit.c
@@ -33,96 +33,83 @@
* - return value can be printed outside of 'run' command
*/
for (i = -3; i <= 3; i++) {
- ut_assertok(console_record_reset_enable());
ut_assertok(run_commandf("setenv foo 'echo bar ; exit %d ; echo baz' ; run foo ; echo $?", i));
ut_assert_nextline("bar");
ut_assert_nextline("%d", i > 0 ? i : 0);
- ut_assertok(ut_check_console_end(uts));
+ ut_assert_console_end();
- ut_assertok(console_record_reset_enable());
ut_assertok(run_commandf("setenv foo 'echo bar ; exit %d ; echo baz' ; run foo && echo quux ; echo $?", i));
ut_assert_nextline("bar");
if (i <= 0)
ut_assert_nextline("quux");
ut_assert_nextline("%d", i > 0 ? i : 0);
- ut_assertok(ut_check_console_end(uts));
+ ut_assert_console_end();
- ut_assertok(console_record_reset_enable());
ut_assertok(run_commandf("setenv foo 'echo bar ; exit %d ; echo baz' ; run foo || echo quux ; echo $?", i));
ut_assert_nextline("bar");
if (i > 0)
ut_assert_nextline("quux");
/* Either 'exit' returns 0, or 'echo quux' returns 0 */
ut_assert_nextline("0");
- ut_assertok(ut_check_console_end(uts));
+ ut_assert_console_end();
}
/* Validate that 'exit' behaves the same way as 'exit 0' */
- ut_assertok(console_record_reset_enable());
ut_assertok(run_commandf("setenv foo 'echo bar ; exit ; echo baz' ; run foo ; echo $?"));
ut_assert_nextline("bar");
ut_assert_nextline("0");
- ut_assertok(ut_check_console_end(uts));
+ ut_assert_console_end();
- ut_assertok(console_record_reset_enable());
ut_assertok(run_commandf("setenv foo 'echo bar ; exit ; echo baz' ; run foo && echo quux ; echo $?"));
ut_assert_nextline("bar");
ut_assert_nextline("quux");
ut_assert_nextline("0");
- ut_assertok(ut_check_console_end(uts));
+ ut_assert_console_end();
- ut_assertok(console_record_reset_enable());
ut_assertok(run_commandf("setenv foo 'echo bar ; exit ; echo baz' ; run foo || echo quux ; echo $?"));
ut_assert_nextline("bar");
/* Either 'exit' returns 0, or 'echo quux' returns 0 */
ut_assert_nextline("0");
- ut_assertok(ut_check_console_end(uts));
+ ut_assert_console_end();
/* Validate that return value still propagates from 'run' command */
- ut_assertok(console_record_reset_enable());
ut_assertok(run_commandf("setenv foo 'echo bar ; true' ; run foo ; echo $?"));
ut_assert_nextline("bar");
ut_assert_nextline("0");
- ut_assertok(ut_check_console_end(uts));
+ ut_assert_console_end();
- ut_assertok(console_record_reset_enable());
ut_assertok(run_commandf("setenv foo 'echo bar ; true' ; run foo && echo quux ; echo $?"));
ut_assert_nextline("bar");
ut_assert_nextline("quux");
ut_assert_nextline("0");
- ut_assertok(ut_check_console_end(uts));
+ ut_assert_console_end();
- ut_assertok(console_record_reset_enable());
ut_assertok(run_commandf("setenv foo 'echo bar ; true' ; run foo || echo quux ; echo $?"));
ut_assert_nextline("bar");
/* The 'true' returns 0 */
ut_assert_nextline("0");
- ut_assertok(ut_check_console_end(uts));
+ ut_assert_console_end();
- ut_assertok(console_record_reset_enable());
ut_assertok(run_commandf("setenv foo 'echo bar ; false' ; run foo ; echo $?"));
ut_assert_nextline("bar");
ut_assert_nextline("1");
- ut_assertok(ut_check_console_end(uts));
+ ut_assert_console_end();
- ut_assertok(console_record_reset_enable());
ut_assertok(run_commandf("setenv foo 'echo bar ; false' ; run foo && echo quux ; echo $?"));
ut_assert_nextline("bar");
ut_assert_nextline("1");
- ut_assertok(ut_check_console_end(uts));
+ ut_assert_console_end();
- ut_assertok(console_record_reset_enable());
ut_assertok(run_commandf("setenv foo 'echo bar ; false' ; run foo || echo quux ; echo $?"));
ut_assert_nextline("bar");
ut_assert_nextline("quux");
/* The 'echo quux' returns 0 */
ut_assert_nextline("0");
- ut_assertok(ut_check_console_end(uts));
+ ut_assert_console_end();
return 0;
}
-
-EXIT_TEST(cmd_exit_test, UT_TESTF_CONSOLE_REC);
+EXIT_TEST(cmd_exit_test, UTF_CONSOLE);
int do_ut_exit(struct cmd_tbl *cmdtp, int flag, int argc, char *const argv[])
{
diff --git a/test/cmd/fdt.c b/test/cmd/fdt.c
index e09a929..e647851 100644
--- a/test/cmd/fdt.c
+++ b/test/cmd/fdt.c
@@ -28,35 +28,49 @@
/**
* make_test_fdt() - Create an FDT with just a root node
*
- * The size is set to the minimum needed
+ * The size is set to the minimum needed. This also sets the working FDT and
+ * checks that the expected output is received from doing so.
*
* @uts: Test state
* @fdt: Place to write FDT
* @size: Maximum size of space for fdt
+ * @addrp: Returns address of the devicetree
*/
-static int make_test_fdt(struct unit_test_state *uts, void *fdt, int size)
+static int make_test_fdt(struct unit_test_state *uts, void *fdt, int size,
+ ulong *addrp)
{
+ ulong addr;
+
ut_assertok(fdt_create(fdt, size));
ut_assertok(fdt_finish_reservemap(fdt));
ut_assert(fdt_begin_node(fdt, "") >= 0);
ut_assertok(fdt_end_node(fdt));
ut_assertok(fdt_finish(fdt));
+ addr = map_to_sysmem(fdt);
+ set_working_fdt_addr(addr);
+ ut_assert_nextline("Working FDT set to %lx", addr);
+ *addrp = addr;
+
return 0;
}
/**
* make_fuller_fdt() - Create an FDT with root node and properties
*
- * The size is set to the minimum needed
+ * The size is set to the minimum needed. This also sets the working FDT and
+ * checks that the expected output is received from doing so.
*
* @uts: Test state
* @fdt: Place to write FDT
* @size: Maximum size of space for fdt
+ * @addrp: Returns address of the devicetree
*/
-static int make_fuller_fdt(struct unit_test_state *uts, void *fdt, int size)
+static int make_fuller_fdt(struct unit_test_state *uts, void *fdt, int size,
+ ulong *addrp)
{
fdt32_t regs[2] = { cpu_to_fdt32(0x1234), cpu_to_fdt32(0x1000) };
+ ulong addr;
/*
* Assemble the following DT for test purposes:
@@ -138,6 +152,11 @@
ut_assertok(fdt_end_node(fdt));
ut_assertok(fdt_finish(fdt));
+ addr = map_to_sysmem(fdt);
+ set_working_fdt_addr(addr);
+ ut_assert_nextline("Working FDT set to %lx", addr);
+ *addrp = addr;
+
return 0;
}
@@ -149,11 +168,10 @@
ulong addr;
int ret;
- ut_assertok(console_record_reset_enable());
ut_assertok(run_command("fdt addr -c", 0));
ut_assert_nextline("Control fdt: %08lx",
(ulong)map_to_sysmem(gd->fdt_blob));
- ut_assertok(ut_check_console_end(uts));
+ ut_assert_console_end();
/* The working fdt is not set, so this should fail */
set_working_fdt_addr(0);
@@ -166,16 +184,13 @@
*/
if (IS_ENABLED(CONFIG_SANDBOX))
ut_assert_nextline("libfdt fdt_check_header(): FDT_ERR_BADMAGIC");
- ut_assertok(ut_check_console_end(uts));
+ ut_assert_console_end();
/* Set up a working FDT and try again */
- ut_assertok(make_test_fdt(uts, fdt, sizeof(fdt)));
- addr = map_to_sysmem(fdt);
- set_working_fdt_addr(addr);
- ut_assert_nextline("Working FDT set to %lx", addr);
+ ut_assertok(make_test_fdt(uts, fdt, sizeof(fdt), &addr));
ut_assertok(run_command("fdt addr", 0));
ut_assert_nextline("Working fdt: %08lx", (ulong)map_to_sysmem(fdt));
- ut_assertok(ut_check_console_end(uts));
+ ut_assert_console_end();
/* Set the working FDT */
set_working_fdt_addr(0);
@@ -183,7 +198,7 @@
ut_assertok(run_commandf("fdt addr %08lx", addr));
ut_assert_nextline("Working FDT set to %lx", addr);
ut_asserteq(addr, map_to_sysmem(working_fdt));
- ut_assertok(ut_check_console_end(uts));
+ ut_assert_console_end();
set_working_fdt_addr(0);
ut_assert_nextline("Working FDT set to 0");
@@ -195,13 +210,13 @@
gd->fdt_blob = fdt_blob;
ut_assertok(ret);
ut_asserteq(addr, map_to_sysmem(new_fdt));
- ut_assertok(ut_check_console_end(uts));
+ ut_assert_console_end();
/* Test setting an invalid FDT */
fdt[0] = 123;
ut_asserteq(1, run_commandf("fdt addr %08lx", addr));
ut_assert_nextline("libfdt fdt_check_header(): FDT_ERR_BADMAGIC");
- ut_assertok(ut_check_console_end(uts));
+ ut_assert_console_end();
/* Test detecting an invalid FDT */
fdt[0] = 123;
@@ -209,11 +224,11 @@
ut_assert_nextline("Working FDT set to %lx", addr);
ut_asserteq(1, run_commandf("fdt addr"));
ut_assert_nextline("libfdt fdt_check_header(): FDT_ERR_BADMAGIC");
- ut_assertok(ut_check_console_end(uts));
+ ut_assert_console_end();
return 0;
}
-FDT_TEST(fdt_test_addr, UT_TESTF_CONSOLE_REC);
+FDT_TEST(fdt_test_addr, UTF_CONSOLE);
/* Test 'fdt addr' resizing an fdt */
static int fdt_test_addr_resize(struct unit_test_state *uts)
@@ -222,32 +237,29 @@
const int newsize = sizeof(fdt) / 2;
ulong addr;
- ut_assertok(make_test_fdt(uts, fdt, sizeof(fdt)));
- addr = map_to_sysmem(fdt);
- set_working_fdt_addr(addr);
+ ut_assertok(make_test_fdt(uts, fdt, sizeof(fdt), &addr));
/* Test setting and resizing the working FDT to a larger size */
- ut_assertok(console_record_reset_enable());
ut_assertok(run_commandf("fdt addr %08lx %x", addr, newsize));
ut_assert_nextline("Working FDT set to %lx", addr);
- ut_assertok(ut_check_console_end(uts));
+ ut_assert_console_end();
/* Try shrinking it */
ut_assertok(run_commandf("fdt addr %08lx %zx", addr, sizeof(fdt) / 4));
ut_assert_nextline("Working FDT set to %lx", addr);
ut_assert_nextline("New length %d < existing length %d, ignoring",
(int)sizeof(fdt) / 4, newsize);
- ut_assertok(ut_check_console_end(uts));
+ ut_assert_console_end();
/* ...quietly */
ut_assertok(run_commandf("fdt addr -q %08lx %zx", addr, sizeof(fdt) / 4));
- ut_assertok(ut_check_console_end(uts));
+ ut_assert_console_end();
/* We cannot easily provoke errors in fdt_open_into(), so ignore that */
return 0;
}
-FDT_TEST(fdt_test_addr_resize, UT_TESTF_CONSOLE_REC);
+FDT_TEST(fdt_test_addr_resize, UTF_CONSOLE);
static int fdt_test_move(struct unit_test_state *uts)
{
@@ -258,30 +270,26 @@
void *buf;
/* Original source DT */
- ut_assertok(make_test_fdt(uts, fdt, size));
+ ut_assertok(make_test_fdt(uts, fdt, size, &addr));
ts = fdt_totalsize(fdt);
- addr = map_to_sysmem(fdt);
- set_working_fdt_addr(addr);
/* Moved target DT location */
buf = map_sysmem(newaddr, size);
memset(buf, 0, size);
/* Test moving the working FDT to a new location */
- ut_assertok(console_record_reset_enable());
ut_assertok(run_commandf("fdt move %08lx %08lx %x", addr, newaddr, ts));
ut_assert_nextline("Working FDT set to %lx", newaddr);
- ut_assertok(ut_check_console_end(uts));
+ ut_assert_console_end();
/* Compare the source and destination DTs */
- ut_assertok(console_record_reset_enable());
ut_assertok(run_commandf("cmp.b %08lx %08lx %x", addr, newaddr, ts));
ut_assert_nextline("Total of %d byte(s) were the same", ts);
- ut_assertok(ut_check_console_end(uts));
+ ut_assert_console_end();
return 0;
}
-FDT_TEST(fdt_test_move, UT_TESTF_CONSOLE_REC);
+FDT_TEST(fdt_test_move, UTF_CONSOLE);
static int fdt_test_resize(struct unit_test_state *uts)
{
@@ -291,21 +299,18 @@
ulong addr;
/* Original source DT */
- ut_assertok(make_test_fdt(uts, fdt, sizeof(fdt)));
+ ut_assertok(make_test_fdt(uts, fdt, sizeof(fdt), &addr));
fdt_shrink_to_minimum(fdt, 0); /* Resize with 0 extra bytes */
ts = fdt_totalsize(fdt);
- addr = map_to_sysmem(fdt);
- set_working_fdt_addr(addr);
/* Test resizing the working FDT and verify the new space was added */
- ut_assertok(console_record_reset_enable());
ut_assertok(run_commandf("fdt resize %x", newsize));
ut_asserteq(ts + newsize, fdt_totalsize(fdt));
- ut_assertok(ut_check_console_end(uts));
+ ut_assert_console_end();
return 0;
}
-FDT_TEST(fdt_test_resize, UT_TESTF_CONSOLE_REC);
+FDT_TEST(fdt_test_resize, UTF_CONSOLE);
static int fdt_test_print_list_common(struct unit_test_state *uts,
const char *opc, const char *node)
@@ -314,56 +319,50 @@
* Test printing/listing the working FDT
* subnode $node/subnode
*/
- ut_assertok(console_record_reset_enable());
ut_assertok(run_commandf("fdt %s %s/subnode", opc, node));
ut_assert_nextline("subnode {");
ut_assert_nextline("\t#address-cells = <0x00000000>;");
ut_assert_nextline("\t#size-cells = <0x00000000>;");
ut_assert_nextline("\tcompatible = \"u-boot,fdt-subnode-test-device\";");
ut_assert_nextline("};");
- ut_assertok(ut_check_console_end(uts));
+ ut_assert_console_end();
/*
* Test printing/listing the working FDT
* path / string property model
*/
- ut_assertok(console_record_reset_enable());
ut_assertok(run_commandf("fdt %s / model", opc));
ut_assert_nextline("model = \"U-Boot FDT test\"");
- ut_assertok(ut_check_console_end(uts));
+ ut_assert_console_end();
/*
* Test printing/listing the working FDT
* path $node string property compatible
*/
- ut_assertok(console_record_reset_enable());
ut_assertok(run_commandf("fdt %s %s compatible", opc, node));
ut_assert_nextline("compatible = \"u-boot,fdt-test-device1\"");
- ut_assertok(ut_check_console_end(uts));
+ ut_assert_console_end();
/*
* Test printing/listing the working FDT
* path $node stringlist property clock-names
*/
- ut_assertok(console_record_reset_enable());
ut_assertok(run_commandf("fdt %s %s clock-names", opc, node));
ut_assert_nextline("clock-names = \"fixed\", \"i2c\", \"spi\", \"uart2\", \"uart1\"");
- ut_assertok(ut_check_console_end(uts));
+ ut_assert_console_end();
/*
* Test printing/listing the working FDT
* path $node u32 property clock-frequency
*/
- ut_assertok(console_record_reset_enable());
ut_assertok(run_commandf("fdt %s %s clock-frequency", opc, node));
ut_assert_nextline("clock-frequency = <0x00fde800>");
- ut_assertok(ut_check_console_end(uts));
+ ut_assert_console_end();
/*
* Test printing/listing the working FDT
* path $node empty property u-boot,empty-property
*/
- ut_assertok(console_record_reset_enable());
ut_assertok(run_commandf("fdt %s %s u-boot,empty-property", opc, node));
/*
* This is the only 'fdt print' / 'fdt list' incantation which
@@ -371,16 +370,15 @@
* since the beginning of the command 'fdt', keep it.
*/
ut_assert_nextline("%s u-boot,empty-property", node);
- ut_assertok(ut_check_console_end(uts));
+ ut_assert_console_end();
/*
* Test printing/listing the working FDT
* path $node prop-encoded array property regs
*/
- ut_assertok(console_record_reset_enable());
ut_assertok(run_commandf("fdt %s %s regs", opc, node));
ut_assert_nextline("regs = <0x00001234 0x00001000>");
- ut_assertok(ut_check_console_end(uts));
+ ut_assert_console_end();
return 0;
}
@@ -393,12 +391,9 @@
int ret;
/* Original source DT */
- ut_assertok(make_fuller_fdt(uts, fdt, sizeof(fdt)));
- addr = map_to_sysmem(fdt);
- set_working_fdt_addr(addr);
+ ut_assertok(make_fuller_fdt(uts, fdt, sizeof(fdt), &addr));
/* Test printing/listing the working FDT -- node / */
- ut_assertok(console_record_reset_enable());
ut_assertok(run_commandf("fdt %s", opc));
ut_assert_nextline("/ {");
ut_assert_nextline("\t#address-cells = <0x00000001>;");
@@ -429,7 +424,7 @@
}
ut_assert_nextline("\t};");
ut_assert_nextline("};");
- ut_assertok(ut_check_console_end(uts));
+ ut_assert_console_end();
ret = fdt_test_print_list_common(uts, opc, "/test-node@1234");
if (!ret)
@@ -442,13 +437,13 @@
{
return fdt_test_print_list(uts, true);
}
-FDT_TEST(fdt_test_print, UT_TESTF_CONSOLE_REC);
+FDT_TEST(fdt_test_print, UTF_CONSOLE);
static int fdt_test_list(struct unit_test_state *uts)
{
return fdt_test_print_list(uts, false);
}
-FDT_TEST(fdt_test_list, UT_TESTF_CONSOLE_REC);
+FDT_TEST(fdt_test_list, UTF_CONSOLE);
/* Test 'fdt get value' reading an fdt */
static int fdt_test_get_value_string(struct unit_test_state *uts,
@@ -456,15 +451,13 @@
const char *idx, const char *strres,
const int intres)
{
- ut_assertok(console_record_reset_enable());
ut_assertok(run_commandf("fdt get value var %s %s %s",
node, prop, idx ? : ""));
- if (strres) {
+ if (strres)
ut_asserteq_str(strres, env_get("var"));
- } else {
+ else
ut_asserteq(intres, env_get_hex("var", 0x1234));
- }
- ut_assertok(ut_check_console_end(uts));
+ ut_assert_console_end();
return 0;
}
@@ -473,16 +466,20 @@
const char *node)
{
/* Test getting default element of $node node clock-names property */
- fdt_test_get_value_string(uts, node, "clock-names", NULL, "fixed", 0);
+ ut_assertok(fdt_test_get_value_string(uts, node, "clock-names", NULL,
+ "fixed", 0));
/* Test getting 0th element of $node node clock-names property */
- fdt_test_get_value_string(uts, node, "clock-names", "0", "fixed", 0);
+ ut_assertok(fdt_test_get_value_string(uts, node, "clock-names", "0",
+ "fixed", 0));
/* Test getting 1st element of $node node clock-names property */
- fdt_test_get_value_string(uts, node, "clock-names", "1", "i2c", 0);
+ ut_assertok(fdt_test_get_value_string(uts, node, "clock-names", "1",
+ "i2c", 0));
/* Test getting 2nd element of $node node clock-names property */
- fdt_test_get_value_string(uts, node, "clock-names", "2", "spi", 0);
+ ut_assertok(fdt_test_get_value_string(uts, node, "clock-names", "2",
+ "spi", 0));
/*
* Test getting default element of $node node regs property.
@@ -491,29 +488,29 @@
* but only if the array is shorter than 40 characters. Anything
* longer is an error. This is a special case for handling hashes.
*/
- fdt_test_get_value_string(uts, node, "regs", NULL, "3412000000100000", 0);
+ ut_assertok(fdt_test_get_value_string(uts, node, "regs", NULL,
+ "3412000000100000", 0));
/* Test getting 0th element of $node node regs property */
- fdt_test_get_value_string(uts, node, "regs", "0", NULL, 0x1234);
+ ut_assertok(fdt_test_get_value_string(uts, node, "regs", "0", NULL,
+ 0x1234));
/* Test getting 1st element of $node node regs property */
- fdt_test_get_value_string(uts, node, "regs", "1", NULL, 0x1000);
+ ut_assertok(fdt_test_get_value_string(uts, node, "regs", "1", NULL,
+ 0x1000));
/* Test missing 10th element of $node node clock-names property */
- ut_assertok(console_record_reset_enable());
ut_asserteq(1, run_commandf("fdt get value ften %s clock-names 10", node));
- ut_assertok(ut_check_console_end(uts));
+ ut_assert_console_end();
/* Test missing 10th element of $node node regs property */
- ut_assertok(console_record_reset_enable());
ut_asserteq(1, run_commandf("fdt get value ften %s regs 10", node));
- ut_assertok(ut_check_console_end(uts));
+ ut_assert_console_end();
/* Test getting default element of $node node nonexistent property */
- ut_assertok(console_record_reset_enable());
ut_asserteq(1, run_commandf("fdt get value fnone %s nonexistent", node));
ut_assert_nextline("libfdt fdt_getprop(): FDT_ERR_NOTFOUND");
- ut_assertok(ut_check_console_end(uts));
+ ut_assert_console_end();
return 0;
}
@@ -522,118 +519,97 @@
{
char fdt[4096];
ulong addr;
- int ret;
- ut_assertok(make_fuller_fdt(uts, fdt, sizeof(fdt)));
- addr = map_to_sysmem(fdt);
- set_working_fdt_addr(addr);
+ ut_assertok(make_fuller_fdt(uts, fdt, sizeof(fdt), &addr));
- ret = fdt_test_get_value_common(uts, "/test-node@1234");
- if (!ret)
- ret = fdt_test_get_value_common(uts, "testnodealias");
- if (ret)
- return ret;
+ ut_assertok(fdt_test_get_value_common(uts, "/test-node@1234"));
+ ut_assertok(fdt_test_get_value_common(uts, "testnodealias"));
/* Test getting default element of /nonexistent node */
- ut_assertok(console_record_reset_enable());
ut_asserteq(1, run_command("fdt get value fnode /nonexistent nonexistent", 1));
ut_assert_nextline("libfdt fdt_path_offset() returned FDT_ERR_NOTFOUND");
- ut_assertok(ut_check_console_end(uts));
+ ut_assert_console_end();
/* Test getting default element of bad alias */
- ut_assertok(console_record_reset_enable());
ut_asserteq(1, run_command("fdt get value vbadalias badalias nonexistent", 1));
ut_assert_nextline("libfdt fdt_path_offset() returned FDT_ERR_NOTFOUND");
- ut_assertok(ut_check_console_end(uts));
+ ut_assert_console_end();
/* Test getting default element of nonexistent alias */
- ut_assertok(console_record_reset_enable());
ut_asserteq(1, run_command("fdt get value vnoalias noalias nonexistent", 1));
ut_assert_nextline("libfdt fdt_path_offset() returned FDT_ERR_BADPATH");
- ut_assertok(ut_check_console_end(uts));
+ ut_assert_console_end();
return 0;
}
-FDT_TEST(fdt_test_get_value, UT_TESTF_CONSOLE_REC);
+FDT_TEST(fdt_test_get_value, UTF_CONSOLE);
static int fdt_test_get_name(struct unit_test_state *uts)
{
char fdt[4096];
ulong addr;
- ut_assertok(make_fuller_fdt(uts, fdt, sizeof(fdt)));
- addr = map_to_sysmem(fdt);
- set_working_fdt_addr(addr);
+ ut_assertok(make_fuller_fdt(uts, fdt, sizeof(fdt), &addr));
/* Test getting name of node 0 in /, which is /aliases node */
- ut_assertok(console_record_reset_enable());
ut_assertok(run_command("fdt get name nzero / 0", 0));
ut_asserteq_str("aliases", env_get("nzero"));
- ut_assertok(ut_check_console_end(uts));
+ ut_assert_console_end();
/* Test getting name of node 1 in /, which is /test-node@1234 node */
- ut_assertok(console_record_reset_enable());
ut_assertok(run_command("fdt get name none / 1", 0));
ut_asserteq_str("test-node@1234", env_get("none"));
- ut_assertok(ut_check_console_end(uts));
+ ut_assert_console_end();
/* Test getting name of node -1 in /, which is /aliases node, same as 0 */
- ut_assertok(console_record_reset_enable());
ut_assertok(run_command("fdt get name nmone / -1", 0));
ut_asserteq_str("aliases", env_get("nmone"));
- ut_assertok(ut_check_console_end(uts));
+ ut_assert_console_end();
/* Test getting name of node 2 in /, which does not exist */
- ut_assertok(console_record_reset_enable());
ut_asserteq(1, run_command("fdt get name ntwo / 2", 1));
ut_assert_nextline("libfdt node not found");
- ut_assertok(ut_check_console_end(uts));
+ ut_assert_console_end();
/* Test getting name of node 0 in /test-node@1234, which is /subnode node */
- ut_assertok(console_record_reset_enable());
ut_assertok(run_command("fdt get name snzero /test-node@1234 0", 0));
ut_asserteq_str("subnode", env_get("snzero"));
ut_assertok(run_command("fdt get name asnzero testnodealias 0", 0));
ut_asserteq_str("subnode", env_get("asnzero"));
- ut_assertok(ut_check_console_end(uts));
+ ut_assert_console_end();
/* Test getting name of node 1 in /test-node@1234, which does not exist */
- ut_assertok(console_record_reset_enable());
ut_asserteq(1, run_command("fdt get name snone /test-node@1234 1", 1));
ut_assert_nextline("libfdt node not found");
ut_asserteq(1, run_command("fdt get name asnone testnodealias 1", 1));
ut_assert_nextline("libfdt node not found");
- ut_assertok(ut_check_console_end(uts));
+ ut_assert_console_end();
/* Test getting name of node -1 in /test-node@1234, which is /subnode node, same as 0 */
- ut_assertok(console_record_reset_enable());
ut_assertok(run_command("fdt get name snmone /test-node@1234 -1", 0));
ut_asserteq_str("subnode", env_get("snmone"));
ut_assertok(run_command("fdt get name asnmone testnodealias -1", 0));
ut_asserteq_str("subnode", env_get("asnmone"));
- ut_assertok(ut_check_console_end(uts));
+ ut_assert_console_end();
/* Test getting name of nonexistent node */
- ut_assertok(console_record_reset_enable());
ut_asserteq(1, run_command("fdt get name nonode /nonexistent 0", 1));
ut_assert_nextline("libfdt fdt_path_offset() returned FDT_ERR_NOTFOUND");
- ut_assertok(ut_check_console_end(uts));
+ ut_assert_console_end();
/* Test getting name of bad alias */
- ut_assertok(console_record_reset_enable());
ut_asserteq(1, run_command("fdt get name vbadalias badalias 0", 1));
ut_assert_nextline("libfdt fdt_path_offset() returned FDT_ERR_NOTFOUND");
- ut_assertok(ut_check_console_end(uts));
+ ut_assert_console_end();
/* Test getting name of nonexistent alias */
- ut_assertok(console_record_reset_enable());
ut_asserteq(1, run_command("fdt get name vnoalias noalias 0", 1));
ut_assert_nextline("libfdt fdt_path_offset() returned FDT_ERR_BADPATH");
- ut_assertok(ut_check_console_end(uts));
+ ut_assert_console_end();
return 0;
}
-FDT_TEST(fdt_test_get_name, UT_TESTF_CONSOLE_REC);
+FDT_TEST(fdt_test_get_name, UTF_CONSOLE);
static int fdt_test_get_addr_common(struct unit_test_state *uts, char *fdt,
const char *path, const char *prop)
@@ -649,11 +625,10 @@
ut_assertnonnull(prop_ptr);
offset = (char *)prop_ptr - fdt;
- ut_assertok(console_record_reset_enable());
ut_assertok(run_commandf("fdt get addr pstr %s %s", path, prop));
ut_asserteq((ulong)map_sysmem(env_get_hex("fdtaddr", 0x1234), 0),
(ulong)(map_sysmem(env_get_hex("pstr", 0x1234), 0) - offset));
- ut_assertok(ut_check_console_end(uts));
+ ut_assert_console_end();
return 0;
}
@@ -663,57 +638,60 @@
char fdt[4096];
ulong addr;
- ut_assertok(make_fuller_fdt(uts, fdt, sizeof(fdt)));
- addr = map_to_sysmem(fdt);
- set_working_fdt_addr(addr);
+ ut_assertok(make_fuller_fdt(uts, fdt, sizeof(fdt), &addr));
/* Test getting address of root node / string property "compatible" */
- fdt_test_get_addr_common(uts, fdt, "/", "compatible");
+ ut_assertok(fdt_test_get_addr_common(uts, fdt, "/", "compatible"));
/* Test getting address of node /test-node@1234 stringlist property "clock-names" */
- fdt_test_get_addr_common(uts, fdt, "/test-node@1234", "clock-names");
- fdt_test_get_addr_common(uts, fdt, "testnodealias", "clock-names");
+ ut_assertok(fdt_test_get_addr_common(uts, fdt, "/test-node@1234",
+ "clock-names"));
+ ut_assertok(fdt_test_get_addr_common(uts, fdt, "testnodealias",
+ "clock-names"));
/* Test getting address of node /test-node@1234 u32 property "clock-frequency" */
- fdt_test_get_addr_common(uts, fdt, "/test-node@1234", "clock-frequency");
- fdt_test_get_addr_common(uts, fdt, "testnodealias", "clock-frequency");
+ ut_assertok(fdt_test_get_addr_common(uts, fdt, "/test-node@1234",
+ "clock-frequency"));
+ ut_assertok(fdt_test_get_addr_common(uts, fdt, "testnodealias",
+ "clock-frequency"));
/* Test getting address of node /test-node@1234 empty property "u-boot,empty-property" */
- fdt_test_get_addr_common(uts, fdt, "/test-node@1234", "u-boot,empty-property");
- fdt_test_get_addr_common(uts, fdt, "testnodealias", "u-boot,empty-property");
+ ut_assertok(fdt_test_get_addr_common(uts, fdt, "/test-node@1234",
+ "u-boot,empty-property"));
+ ut_assertok(fdt_test_get_addr_common(uts, fdt, "testnodealias",
+ "u-boot,empty-property"));
/* Test getting address of node /test-node@1234 array property "regs" */
- fdt_test_get_addr_common(uts, fdt, "/test-node@1234", "regs");
- fdt_test_get_addr_common(uts, fdt, "testnodealias", "regs");
+ ut_assertok(fdt_test_get_addr_common(uts, fdt, "/test-node@1234",
+ "regs"));
+ ut_assertok(fdt_test_get_addr_common(uts, fdt, "testnodealias",
+ "regs"));
/* Test getting address of node /test-node@1234/subnode non-existent property "noprop" */
- ut_assertok(console_record_reset_enable());
ut_asserteq(1, run_command("fdt get addr pnoprop /test-node@1234/subnode noprop", 1));
ut_assert_nextline("libfdt fdt_getprop(): FDT_ERR_NOTFOUND");
- ut_assertok(ut_check_console_end(uts));
+ ut_assert_console_end();
/* Test getting address of non-existent node /test-node@1234/nonode@1 property "noprop" */
- ut_assertok(console_record_reset_enable());
ut_asserteq(1, run_command("fdt get addr pnonode /test-node@1234/nonode@1 noprop", 1));
ut_assert_nextline("libfdt fdt_path_offset() returned FDT_ERR_NOTFOUND");
- ut_assertok(ut_check_console_end(uts));
+ ut_assert_console_end();
return 0;
}
-FDT_TEST(fdt_test_get_addr, UT_TESTF_CONSOLE_REC);
+FDT_TEST(fdt_test_get_addr, UTF_CONSOLE);
static int fdt_test_get_size_common(struct unit_test_state *uts,
const char *path, const char *prop,
const unsigned int val)
{
- ut_assertok(console_record_reset_enable());
if (prop) {
ut_assertok(run_commandf("fdt get size sstr %s %s", path, prop));
} else {
ut_assertok(run_commandf("fdt get size sstr %s", path));
}
ut_asserteq(val, env_get_hex("sstr", 0x1234));
- ut_assertok(ut_check_console_end(uts));
+ ut_assert_console_end();
return 0;
}
@@ -723,71 +701,72 @@
char fdt[4096];
ulong addr;
- ut_assertok(make_fuller_fdt(uts, fdt, sizeof(fdt)));
- addr = map_to_sysmem(fdt);
- set_working_fdt_addr(addr);
+ ut_assertok(make_fuller_fdt(uts, fdt, sizeof(fdt), &addr));
/* Test getting size of root node / string property "compatible" */
- fdt_test_get_size_common(uts, "/", "compatible", 16);
+ ut_assertok(fdt_test_get_size_common(uts, "/", "compatible", 16));
/* Test getting size of node /test-node@1234 stringlist property "clock-names" */
- fdt_test_get_size_common(uts, "/test-node@1234", "clock-names", 26);
- fdt_test_get_size_common(uts, "testnodealias", "clock-names", 26);
+ ut_assertok(fdt_test_get_size_common(uts, "/test-node@1234",
+ "clock-names", 26));
+ ut_assertok(fdt_test_get_size_common(uts, "testnodealias",
+ "clock-names", 26));
/* Test getting size of node /test-node@1234 u32 property "clock-frequency" */
- fdt_test_get_size_common(uts, "/test-node@1234", "clock-frequency", 4);
- fdt_test_get_size_common(uts, "testnodealias", "clock-frequency", 4);
+ ut_assertok(fdt_test_get_size_common(uts, "/test-node@1234",
+ "clock-frequency", 4));
+ ut_assertok(fdt_test_get_size_common(uts, "testnodealias",
+ "clock-frequency", 4));
/* Test getting size of node /test-node@1234 empty property "u-boot,empty-property" */
- fdt_test_get_size_common(uts, "/test-node@1234", "u-boot,empty-property", 0);
- fdt_test_get_size_common(uts, "testnodealias", "u-boot,empty-property", 0);
+ ut_assertok(fdt_test_get_size_common(uts, "/test-node@1234",
+ "u-boot,empty-property", 0));
+ ut_assertok(fdt_test_get_size_common(uts, "testnodealias",
+ "u-boot,empty-property", 0));
/* Test getting size of node /test-node@1234 array property "regs" */
- fdt_test_get_size_common(uts, "/test-node@1234", "regs", 8);
- fdt_test_get_size_common(uts, "testnodealias", "regs", 8);
+ ut_assertok(fdt_test_get_size_common(uts, "/test-node@1234", "regs",
+ 8));
+ ut_assertok(fdt_test_get_size_common(uts, "testnodealias", "regs", 8));
/* Test getting node count of node / */
- fdt_test_get_size_common(uts, "/", NULL, 2);
+ ut_assertok(fdt_test_get_size_common(uts, "/", NULL, 2));
/* Test getting node count of node /test-node@1234/subnode */
- fdt_test_get_size_common(uts, "/test-node@1234/subnode", NULL, 0);
- fdt_test_get_size_common(uts, "subnodealias", NULL, 0);
+ ut_assertok(fdt_test_get_size_common(uts, "/test-node@1234/subnode",
+ NULL, 0));
+ ut_assertok(fdt_test_get_size_common(uts, "subnodealias", NULL, 0));
/* Test getting size of node /test-node@1234/subnode non-existent property "noprop" */
- ut_assertok(console_record_reset_enable());
ut_asserteq(1, run_command("fdt get size pnoprop /test-node@1234/subnode noprop", 1));
ut_assert_nextline("libfdt fdt_getprop(): FDT_ERR_NOTFOUND");
ut_asserteq(1, run_command("fdt get size pnoprop subnodealias noprop", 1));
ut_assert_nextline("libfdt fdt_getprop(): FDT_ERR_NOTFOUND");
- ut_assertok(ut_check_console_end(uts));
+ ut_assert_console_end();
/* Test getting size of non-existent node /test-node@1234/nonode@1 property "noprop" */
- ut_assertok(console_record_reset_enable());
ut_asserteq(1, run_command("fdt get size pnonode /test-node@1234/nonode@1 noprop", 1));
ut_assert_nextline("libfdt fdt_path_offset() returned FDT_ERR_NOTFOUND");
- ut_assertok(ut_check_console_end(uts));
+ ut_assert_console_end();
/* Test getting node count of non-existent node /test-node@1234/nonode@1 */
- ut_assertok(console_record_reset_enable());
ut_asserteq(1, run_command("fdt get size pnonode /test-node@1234/nonode@1", 1));
ut_assert_nextline("libfdt fdt_path_offset() returned FDT_ERR_NOTFOUND");
- ut_assertok(ut_check_console_end(uts));
+ ut_assert_console_end();
/* Test getting node count of bad alias badalias */
- ut_assertok(console_record_reset_enable());
ut_asserteq(1, run_command("fdt get size pnonode badalias noprop", 1));
ut_assert_nextline("libfdt fdt_path_offset() returned FDT_ERR_NOTFOUND");
- ut_assertok(ut_check_console_end(uts));
+ ut_assert_console_end();
/* Test getting node count of non-existent alias noalias */
- ut_assertok(console_record_reset_enable());
ut_asserteq(1, run_command("fdt get size pnonode noalias", 1));
ut_assert_nextline("libfdt fdt_path_offset() returned FDT_ERR_BADPATH");
- ut_assertok(ut_check_console_end(uts));
+ ut_assert_console_end();
return 0;
}
-FDT_TEST(fdt_test_get_size, UT_TESTF_CONSOLE_REC);
+FDT_TEST(fdt_test_get_size, UTF_CONSOLE);
static int fdt_test_set_single(struct unit_test_state *uts,
const char *path, const char *prop,
@@ -799,7 +778,6 @@
* => fdt set /path property integer
* => fdt set /path property
*/
- ut_assertok(console_record_reset_enable());
if (sval)
ut_assertok(run_commandf("fdt set %s %s %s", path, prop, sval));
else if (integer)
@@ -815,7 +793,7 @@
ut_asserteq(ival, env_get_hex("svar", 0x1234));
else
ut_assertnull(env_get("svar"));
- ut_assertok(ut_check_console_end(uts));
+ ut_assert_console_end();
return 0;
}
@@ -837,7 +815,6 @@
* new array is correctly sized and read past the new array length
* triggers failure.
*/
- ut_assertok(console_record_reset_enable());
if (sval1 && sval2) {
ut_assertok(run_commandf("fdt set %s %s %s %s end", path, prop, sval1, sval2));
ut_assertok(run_commandf("fdt set %s %s %s %s", path, prop, sval1, sval2));
@@ -865,7 +842,7 @@
ut_asserteq(ival2, env_get_hex("svar2", 0x1234));
ut_assertnull(env_get("svarn"));
}
- ut_assertok(ut_check_console_end(uts));
+ ut_assert_console_end();
return 0;
}
@@ -873,14 +850,14 @@
static int fdt_test_set_node(struct unit_test_state *uts,
const char *path, const char *prop)
{
- fdt_test_set_single(uts, path, prop, "new", 0, false);
- fdt_test_set_single(uts, path, prop, "rewrite", 0, false);
- fdt_test_set_single(uts, path, prop, NULL, 42, true);
- fdt_test_set_single(uts, path, prop, NULL, 0, false);
- fdt_test_set_multi(uts, path, prop, NULL, NULL, 42, 1701);
- fdt_test_set_multi(uts, path, prop, NULL, NULL, 74656, 9);
- fdt_test_set_multi(uts, path, prop, "42", "1701", 0, 0);
- fdt_test_set_multi(uts, path, prop, "74656", "9", 0, 0);
+ ut_assertok(fdt_test_set_single(uts, path, prop, "new", 0, false));
+ ut_assertok(fdt_test_set_single(uts, path, prop, "rewrite", 0, false));
+ ut_assertok(fdt_test_set_single(uts, path, prop, NULL, 42, true));
+ ut_assertok(fdt_test_set_single(uts, path, prop, NULL, 0, false));
+ ut_assertok(fdt_test_set_multi(uts, path, prop, NULL, NULL, 42, 1701));
+ ut_assertok(fdt_test_set_multi(uts, path, prop, NULL, NULL, 74656, 9));
+ ut_assertok(fdt_test_set_multi(uts, path, prop, "42", "1701", 0, 0));
+ ut_assertok(fdt_test_set_multi(uts, path, prop, "74656", "9", 0, 0));
return 0;
}
@@ -890,198 +867,173 @@
char fdt[8192];
ulong addr;
- ut_assertok(make_fuller_fdt(uts, fdt, sizeof(fdt)));
+ ut_assertok(make_fuller_fdt(uts, fdt, sizeof(fdt), &addr));
fdt_shrink_to_minimum(fdt, 4096); /* Resize with 4096 extra bytes */
- addr = map_to_sysmem(fdt);
- set_working_fdt_addr(addr);
/* Test setting of root node / existing property "compatible" */
- fdt_test_set_node(uts, "/", "compatible");
+ ut_assertok(fdt_test_set_node(uts, "/", "compatible"));
/* Test setting of root node / new property "newproperty" */
- fdt_test_set_node(uts, "/", "newproperty");
+ ut_assertok(fdt_test_set_node(uts, "/", "newproperty"));
/* Test setting of subnode existing property "compatible" */
- fdt_test_set_node(uts, "/test-node@1234/subnode", "compatible");
- fdt_test_set_node(uts, "subnodealias", "compatible");
+ ut_assertok(fdt_test_set_node(uts, "/test-node@1234/subnode",
+ "compatible"));
+ ut_assertok(fdt_test_set_node(uts, "subnodealias", "compatible"));
/* Test setting of subnode new property "newproperty" */
- fdt_test_set_node(uts, "/test-node@1234/subnode", "newproperty");
- fdt_test_set_node(uts, "subnodealias", "newproperty");
+ ut_assertok(fdt_test_set_node(uts, "/test-node@1234/subnode",
+ "newproperty"));
+ ut_assertok(fdt_test_set_node(uts, "subnodealias", "newproperty"));
/* Test setting property of non-existent node */
- ut_assertok(console_record_reset_enable());
ut_asserteq(1, run_command("fdt set /no-node noprop", 1));
ut_assert_nextline("libfdt fdt_path_offset() returned FDT_ERR_NOTFOUND");
- ut_assertok(ut_check_console_end(uts));
+ ut_assert_console_end();
/* Test setting property of non-existent alias */
- ut_assertok(console_record_reset_enable());
ut_asserteq(1, run_command("fdt set noalias noprop", 1));
ut_assert_nextline("libfdt fdt_path_offset() returned FDT_ERR_BADPATH");
- ut_assertok(ut_check_console_end(uts));
+ ut_assert_console_end();
/* Test setting property of bad alias */
- ut_assertok(console_record_reset_enable());
ut_asserteq(1, run_command("fdt set badalias noprop", 1));
ut_assert_nextline("libfdt fdt_path_offset() returned FDT_ERR_NOTFOUND");
- ut_assertok(ut_check_console_end(uts));
+ ut_assert_console_end();
return 0;
}
-FDT_TEST(fdt_test_set, UT_TESTF_CONSOLE_REC);
+FDT_TEST(fdt_test_set, UTF_CONSOLE);
static int fdt_test_mknode(struct unit_test_state *uts)
{
char fdt[8192];
ulong addr;
- ut_assertok(make_fuller_fdt(uts, fdt, sizeof(fdt)));
+ ut_assertok(make_fuller_fdt(uts, fdt, sizeof(fdt), &addr));
fdt_shrink_to_minimum(fdt, 4096); /* Resize with 4096 extra bytes */
- addr = map_to_sysmem(fdt);
- set_working_fdt_addr(addr);
/* Test creation of new node in / */
- ut_assertok(console_record_reset_enable());
ut_assertok(run_commandf("fdt mknode / newnode"));
ut_assertok(run_commandf("fdt list /newnode"));
ut_assert_nextline("newnode {");
ut_assert_nextline("};");
- ut_assertok(ut_check_console_end(uts));
+ ut_assert_console_end();
/* Test creation of new node in /test-node@1234 */
- ut_assertok(console_record_reset_enable());
ut_assertok(run_commandf("fdt mknode /test-node@1234 newsubnode"));
ut_assertok(run_commandf("fdt list /test-node@1234/newsubnode"));
ut_assert_nextline("newsubnode {");
ut_assert_nextline("};");
- ut_assertok(ut_check_console_end(uts));
+ ut_assert_console_end();
/* Test creation of new node in /test-node@1234 by alias */
- ut_assertok(console_record_reset_enable());
ut_assertok(run_commandf("fdt mknode testnodealias newersubnode"));
ut_assertok(run_commandf("fdt list testnodealias/newersubnode"));
ut_assert_nextline("newersubnode {");
ut_assert_nextline("};");
- ut_assertok(ut_check_console_end(uts));
+ ut_assert_console_end();
/* Test creation of new node in /test-node@1234 over existing node */
- ut_assertok(console_record_reset_enable());
ut_asserteq(1, run_commandf("fdt mknode testnodealias newsubnode"));
ut_assert_nextline("libfdt fdt_add_subnode(): FDT_ERR_EXISTS");
- ut_assertok(ut_check_console_end(uts));
+ ut_assert_console_end();
/* Test creation of new node in /test-node@1234 by alias over existing node */
- ut_assertok(console_record_reset_enable());
ut_asserteq(1, run_commandf("fdt mknode testnodealias newersubnode"));
ut_assert_nextline("libfdt fdt_add_subnode(): FDT_ERR_EXISTS");
- ut_assertok(ut_check_console_end(uts));
+ ut_assert_console_end();
/* Test creation of new node in non-existent node */
- ut_assertok(console_record_reset_enable());
ut_asserteq(1, run_commandf("fdt mknode /no-node newnosubnode"));
ut_assert_nextline("libfdt fdt_path_offset() returned FDT_ERR_NOTFOUND");
- ut_assertok(ut_check_console_end(uts));
+ ut_assert_console_end();
/* Test creation of new node in non-existent alias */
- ut_assertok(console_record_reset_enable());
ut_asserteq(1, run_commandf("fdt mknode noalias newfailsubnode"));
ut_assert_nextline("libfdt fdt_path_offset() returned FDT_ERR_BADPATH");
- ut_assertok(ut_check_console_end(uts));
+ ut_assert_console_end();
/* Test creation of new node in bad alias */
- ut_assertok(console_record_reset_enable());
ut_asserteq(1, run_commandf("fdt mknode badalias newbadsubnode"));
ut_assert_nextline("libfdt fdt_path_offset() returned FDT_ERR_NOTFOUND");
- ut_assertok(ut_check_console_end(uts));
+ ut_assert_console_end();
return 0;
}
-FDT_TEST(fdt_test_mknode, UT_TESTF_CONSOLE_REC);
+FDT_TEST(fdt_test_mknode, UTF_CONSOLE);
static int fdt_test_rm(struct unit_test_state *uts)
{
char fdt[4096];
ulong addr;
- ut_assertok(make_fuller_fdt(uts, fdt, sizeof(fdt)));
- addr = map_to_sysmem(fdt);
- set_working_fdt_addr(addr);
+ ut_assertok(make_fuller_fdt(uts, fdt, sizeof(fdt), &addr));
/* Test removal of property in root node / */
- ut_assertok(console_record_reset_enable());
ut_assertok(run_commandf("fdt print / compatible"));
ut_assert_nextline("compatible = \"u-boot,fdt-test\"");
ut_assertok(run_commandf("fdt rm / compatible"));
ut_asserteq(1, run_commandf("fdt print / compatible"));
ut_assert_nextline("libfdt fdt_getprop(): FDT_ERR_NOTFOUND");
- ut_assertok(ut_check_console_end(uts));
+ ut_assert_console_end();
/* Test removal of property clock-names in subnode /test-node@1234 */
- ut_assertok(console_record_reset_enable());
ut_assertok(run_commandf("fdt print /test-node@1234 clock-names"));
ut_assert_nextline("clock-names = \"fixed\", \"i2c\", \"spi\", \"uart2\", \"uart1\"");
ut_assertok(run_commandf("fdt rm /test-node@1234 clock-names"));
ut_asserteq(1, run_commandf("fdt print /test-node@1234 clock-names"));
ut_assert_nextline("libfdt fdt_getprop(): FDT_ERR_NOTFOUND");
- ut_assertok(ut_check_console_end(uts));
+ ut_assert_console_end();
/* Test removal of property u-boot,empty-property in subnode /test-node@1234 by alias */
- ut_assertok(console_record_reset_enable());
ut_assertok(run_commandf("fdt print testnodealias u-boot,empty-property"));
ut_assert_nextline("testnodealias u-boot,empty-property");
ut_assertok(run_commandf("fdt rm testnodealias u-boot,empty-property"));
ut_asserteq(1, run_commandf("fdt print testnodealias u-boot,empty-property"));
ut_assert_nextline("libfdt fdt_getprop(): FDT_ERR_NOTFOUND");
- ut_assertok(ut_check_console_end(uts));
+ ut_assert_console_end();
/* Test removal of non-existent property noprop in subnode /test-node@1234 */
- ut_assertok(console_record_reset_enable());
ut_asserteq(1, run_commandf("fdt rm /test-node@1234 noprop"));
ut_assert_nextline("libfdt fdt_delprop(): FDT_ERR_NOTFOUND");
- ut_assertok(ut_check_console_end(uts));
+ ut_assert_console_end();
/* Test removal of non-existent node /no-node@5678 */
- ut_assertok(console_record_reset_enable());
ut_asserteq(1, run_commandf("fdt rm /no-node@5678"));
ut_assert_nextline("libfdt fdt_path_offset() returned FDT_ERR_NOTFOUND");
- ut_assertok(ut_check_console_end(uts));
+ ut_assert_console_end();
/* Test removal of subnode /test-node@1234/subnode by alias */
- ut_assertok(console_record_reset_enable());
ut_assertok(run_commandf("fdt rm subnodealias"));
ut_asserteq(1, run_commandf("fdt print /test-node@1234/subnode"));
ut_assert_nextline("libfdt fdt_path_offset() returned FDT_ERR_NOTFOUND");
- ut_assertok(ut_check_console_end(uts));
+ ut_assert_console_end();
/* Test removal of node by non-existent alias */
- ut_assertok(console_record_reset_enable());
ut_asserteq(1, run_commandf("fdt rm noalias"));
ut_assert_nextline("libfdt fdt_path_offset() returned FDT_ERR_BADPATH");
- ut_assertok(ut_check_console_end(uts));
+ ut_assert_console_end();
/* Test removal of node by bad alias */
- ut_assertok(console_record_reset_enable());
ut_asserteq(1, run_commandf("fdt rm noalias"));
ut_assert_nextline("libfdt fdt_path_offset() returned FDT_ERR_BADPATH");
- ut_assertok(ut_check_console_end(uts));
+ ut_assert_console_end();
/* Test removal of node /test-node@1234 */
- ut_assertok(console_record_reset_enable());
ut_assertok(run_commandf("fdt rm /test-node@1234"));
ut_asserteq(1, run_commandf("fdt print /test-node@1234"));
ut_assert_nextline("libfdt fdt_path_offset() returned FDT_ERR_NOTFOUND");
- ut_assertok(ut_check_console_end(uts));
+ ut_assert_console_end();
/* Test removal of node / */
- ut_assertok(console_record_reset_enable());
ut_assertok(run_commandf("fdt rm /"));
ut_asserteq(1, run_commandf("fdt print /"));
- ut_assertok(ut_check_console_end(uts));
+ ut_assert_console_end();
return 0;
}
-FDT_TEST(fdt_test_rm, UT_TESTF_CONSOLE_REC);
+FDT_TEST(fdt_test_rm, UTF_CONSOLE);
static int fdt_test_bootcpu(struct unit_test_state *uts)
{
@@ -1089,46 +1041,39 @@
ulong addr;
int i;
- ut_assertok(make_test_fdt(uts, fdt, sizeof(fdt)));
- addr = map_to_sysmem(fdt);
- set_working_fdt_addr(addr);
+ ut_assertok(make_test_fdt(uts, fdt, sizeof(fdt), &addr));
/* Test getting default bootcpu entry */
- ut_assertok(console_record_reset_enable());
ut_assertok(run_commandf("fdt header get bootcpu boot_cpuid_phys"));
ut_asserteq(0, env_get_ulong("bootcpu", 10, 0x1234));
- ut_assertok(ut_check_console_end(uts));
+ ut_assert_console_end();
/* Test setting and getting new bootcpu entry, twice, to test overwrite */
for (i = 42; i <= 43; i++) {
- ut_assertok(console_record_reset_enable());
ut_assertok(run_commandf("fdt bootcpu %d", i));
- ut_assertok(ut_check_console_end(uts));
+ ut_assert_console_end();
/* Test getting new bootcpu entry */
- ut_assertok(console_record_reset_enable());
ut_assertok(run_commandf("fdt header get bootcpu boot_cpuid_phys"));
ut_asserteq(i, env_get_ulong("bootcpu", 10, 0x1234));
- ut_assertok(ut_check_console_end(uts));
+ ut_assert_console_end();
}
return 0;
}
-FDT_TEST(fdt_test_bootcpu, UT_TESTF_CONSOLE_REC);
+FDT_TEST(fdt_test_bootcpu, UTF_CONSOLE);
static int fdt_test_header_get(struct unit_test_state *uts,
const char *field, const unsigned long val)
{
/* Test getting valid header entry */
- ut_assertok(console_record_reset_enable());
ut_assertok(run_commandf("fdt header get fvar %s", field));
ut_asserteq(val, env_get_hex("fvar", 0x1234));
- ut_assertok(ut_check_console_end(uts));
+ ut_assert_console_end();
/* Test getting malformed header entry */
- ut_assertok(console_record_reset_enable());
ut_asserteq(1, run_commandf("fdt header get fvar typo%stypo", field));
- ut_assertok(ut_check_console_end(uts));
+ ut_assert_console_end();
return 0;
}
@@ -1138,12 +1083,9 @@
char fdt[256];
ulong addr;
- ut_assertok(make_test_fdt(uts, fdt, sizeof(fdt)));
- addr = map_to_sysmem(fdt);
- set_working_fdt_addr(addr);
+ ut_assertok(make_test_fdt(uts, fdt, sizeof(fdt), &addr));
/* Test header print */
- ut_assertok(console_record_reset_enable());
ut_assertok(run_commandf("fdt header"));
ut_assert_nextline("magic:\t\t\t0x%x", fdt_magic(fdt));
ut_assert_nextline("totalsize:\t\t0x%x (%d)", fdt_totalsize(fdt), fdt_totalsize(fdt));
@@ -1157,23 +1099,30 @@
ut_assert_nextline("size_dt_struct:\t\t0x%x", fdt_size_dt_struct(fdt));
ut_assert_nextline("number mem_rsv:\t\t0x%x", fdt_num_mem_rsv(fdt));
ut_assert_nextline_empty();
- ut_assertok(ut_check_console_end(uts));
+ ut_assert_console_end();
/* Test header get */
- fdt_test_header_get(uts, "magic", fdt_magic(fdt));
- fdt_test_header_get(uts, "totalsize", fdt_totalsize(fdt));
- fdt_test_header_get(uts, "off_dt_struct", fdt_off_dt_struct(fdt));
- fdt_test_header_get(uts, "off_dt_strings", fdt_off_dt_strings(fdt));
- fdt_test_header_get(uts, "off_mem_rsvmap", fdt_off_mem_rsvmap(fdt));
- fdt_test_header_get(uts, "version", fdt_version(fdt));
- fdt_test_header_get(uts, "last_comp_version", fdt_last_comp_version(fdt));
- fdt_test_header_get(uts, "boot_cpuid_phys", fdt_boot_cpuid_phys(fdt));
- fdt_test_header_get(uts, "size_dt_strings", fdt_size_dt_strings(fdt));
- fdt_test_header_get(uts, "size_dt_struct", fdt_size_dt_struct(fdt));
+ ut_assertok(fdt_test_header_get(uts, "magic", fdt_magic(fdt)));
+ ut_assertok(fdt_test_header_get(uts, "totalsize", fdt_totalsize(fdt)));
+ ut_assertok(fdt_test_header_get(uts, "off_dt_struct",
+ fdt_off_dt_struct(fdt)));
+ ut_assertok(fdt_test_header_get(uts, "off_dt_strings",
+ fdt_off_dt_strings(fdt)));
+ ut_assertok(fdt_test_header_get(uts, "off_mem_rsvmap",
+ fdt_off_mem_rsvmap(fdt)));
+ ut_assertok(fdt_test_header_get(uts, "version", fdt_version(fdt)));
+ ut_assertok(fdt_test_header_get(uts, "last_comp_version",
+ fdt_last_comp_version(fdt)));
+ ut_assertok(fdt_test_header_get(uts, "boot_cpuid_phys",
+ fdt_boot_cpuid_phys(fdt)));
+ ut_assertok(fdt_test_header_get(uts, "size_dt_strings",
+ fdt_size_dt_strings(fdt)));
+ ut_assertok(fdt_test_header_get(uts, "size_dt_struct",
+ fdt_size_dt_struct(fdt)));
return 0;
}
-FDT_TEST(fdt_test_header, UT_TESTF_CONSOLE_REC);
+FDT_TEST(fdt_test_header, UTF_CONSOLE);
static int fdt_test_memory_cells(struct unit_test_state *uts,
const unsigned int cells)
@@ -1217,16 +1166,16 @@
fdt_shrink_to_minimum(fdt, 4096); /* Resize with 4096 extra bytes */
addr = map_to_sysmem(fdt);
set_working_fdt_addr(addr);
+ ut_assert_nextline("Working FDT set to %lx", addr);
/* Test updating the memory node */
- ut_assertok(console_record_reset_enable());
ut_assertok(run_commandf("fdt memory 0x%s 0x%s", seta, sets));
ut_assertok(run_commandf("fdt print /memory"));
ut_assert_nextline("memory {");
ut_assert_nextline("\tdevice_type = \"memory\";");
ut_assert_nextline("\treg = <%s %s>;", pada, pads);
ut_assert_nextline("};");
- ut_assertok(ut_check_console_end(uts));
+ ut_assert_console_end();
free(sets);
free(seta);
@@ -1244,8 +1193,8 @@
* so far unsupported and fails because of simple_stroull() being
* 64bit tops in the 'fdt memory' command implementation.
*/
- fdt_test_memory_cells(uts, 1);
- fdt_test_memory_cells(uts, 2);
+ ut_assertok(fdt_test_memory_cells(uts, 1));
+ ut_assertok(fdt_test_memory_cells(uts, 2));
/*
* The 'fdt memory' command is limited to /memory node, it does
@@ -1256,31 +1205,27 @@
return 0;
}
-FDT_TEST(fdt_test_memory, UT_TESTF_CONSOLE_REC);
+FDT_TEST(fdt_test_memory, UTF_CONSOLE);
static int fdt_test_rsvmem(struct unit_test_state *uts)
{
char fdt[8192];
ulong addr;
- ut_assertok(make_test_fdt(uts, fdt, sizeof(fdt)));
+ ut_assertok(make_test_fdt(uts, fdt, sizeof(fdt), &addr));
fdt_shrink_to_minimum(fdt, 4096); /* Resize with 4096 extra bytes */
fdt_add_mem_rsv(fdt, 0x42, 0x1701);
fdt_add_mem_rsv(fdt, 0x74656, 0x9);
- addr = map_to_sysmem(fdt);
- set_working_fdt_addr(addr);
/* Test default reserved memory node presence */
- ut_assertok(console_record_reset_enable());
ut_assertok(run_commandf("fdt rsvmem print"));
ut_assert_nextline("index\t\t start\t\t size");
ut_assert_nextline("------------------------------------------------");
ut_assert_nextline(" %x\t%016x\t%016x", 0, 0x42, 0x1701);
ut_assert_nextline(" %x\t%016x\t%016x", 1, 0x74656, 0x9);
- ut_assertok(ut_check_console_end(uts));
+ ut_assert_console_end();
/* Test add new reserved memory node */
- ut_assertok(console_record_reset_enable());
ut_assertok(run_commandf("fdt rsvmem add 0x1234 0x5678"));
ut_assertok(run_commandf("fdt rsvmem print"));
ut_assert_nextline("index\t\t start\t\t size");
@@ -1288,20 +1233,18 @@
ut_assert_nextline(" %x\t%016x\t%016x", 0, 0x42, 0x1701);
ut_assert_nextline(" %x\t%016x\t%016x", 1, 0x74656, 0x9);
ut_assert_nextline(" %x\t%016x\t%016x", 2, 0x1234, 0x5678);
- ut_assertok(ut_check_console_end(uts));
+ ut_assert_console_end();
/* Test delete reserved memory node */
- ut_assertok(console_record_reset_enable());
ut_assertok(run_commandf("fdt rsvmem delete 0"));
ut_assertok(run_commandf("fdt rsvmem print"));
ut_assert_nextline("index\t\t start\t\t size");
ut_assert_nextline("------------------------------------------------");
ut_assert_nextline(" %x\t%016x\t%016x", 0, 0x74656, 0x9);
ut_assert_nextline(" %x\t%016x\t%016x", 1, 0x1234, 0x5678);
- ut_assertok(ut_check_console_end(uts));
+ ut_assert_console_end();
/* Test re-add new reserved memory node */
- ut_assertok(console_record_reset_enable());
ut_assertok(run_commandf("fdt rsvmem add 0x42 0x1701"));
ut_assertok(run_commandf("fdt rsvmem print"));
ut_assert_nextline("index\t\t start\t\t size");
@@ -1309,17 +1252,16 @@
ut_assert_nextline(" %x\t%016x\t%016x", 0, 0x74656, 0x9);
ut_assert_nextline(" %x\t%016x\t%016x", 1, 0x1234, 0x5678);
ut_assert_nextline(" %x\t%016x\t%016x", 2, 0x42, 0x1701);
- ut_assertok(ut_check_console_end(uts));
+ ut_assert_console_end();
/* Test delete nonexistent reserved memory node */
- ut_assertok(console_record_reset_enable());
ut_asserteq(1, run_commandf("fdt rsvmem delete 10"));
ut_assert_nextline("libfdt fdt_del_mem_rsv(): FDT_ERR_NOTFOUND");
- ut_assertok(ut_check_console_end(uts));
+ ut_assert_console_end();
return 0;
}
-FDT_TEST(fdt_test_rsvmem, UT_TESTF_CONSOLE_REC);
+FDT_TEST(fdt_test_rsvmem, UTF_CONSOLE);
static int fdt_test_chosen(struct unit_test_state *uts)
{
@@ -1327,19 +1269,15 @@
char fdt[8192];
ulong addr;
- ut_assertok(make_test_fdt(uts, fdt, sizeof(fdt)));
+ ut_assertok(make_test_fdt(uts, fdt, sizeof(fdt), &addr));
fdt_shrink_to_minimum(fdt, 4096); /* Resize with 4096 extra bytes */
- addr = map_to_sysmem(fdt);
- set_working_fdt_addr(addr);
/* Test default chosen node presence, fail as there is no /chosen node */
- ut_assertok(console_record_reset_enable());
ut_asserteq(1, run_commandf("fdt print /chosen"));
ut_assert_nextline("libfdt fdt_path_offset() returned FDT_ERR_NOTFOUND");
- ut_assertok(ut_check_console_end(uts));
+ ut_assert_console_end();
/* Test add new chosen node without initrd */
- ut_assertok(console_record_reset_enable());
ut_assertok(run_commandf("fdt chosen"));
ut_assertok(run_commandf("fdt print /chosen"));
ut_assert_nextline("chosen {");
@@ -1351,10 +1289,9 @@
!IS_ENABLED(CONFIG_ARMV8_SEC_FIRMWARE_SUPPORT))
ut_assert_nextlinen("\tkaslr-seed = ");
ut_assert_nextline("};");
- ut_assertok(ut_check_console_end(uts));
+ ut_assert_console_end();
/* Test add new chosen node with initrd */
- ut_assertok(console_record_reset_enable());
ut_assertok(run_commandf("fdt chosen 0x1234 0x5678"));
ut_assertok(run_commandf("fdt print /chosen"));
ut_assert_nextline("chosen {");
@@ -1371,11 +1308,11 @@
!IS_ENABLED(CONFIG_ARMV8_SEC_FIRMWARE_SUPPORT))
ut_assert_nextlinen("\tkaslr-seed = ");
ut_assert_nextline("};");
- ut_assertok(ut_check_console_end(uts));
+ ut_assert_console_end();
return 0;
}
-FDT_TEST(fdt_test_chosen, UT_TESTF_CONSOLE_REC);
+FDT_TEST(fdt_test_chosen, UTF_CONSOLE);
static int fdt_test_apply(struct unit_test_state *uts)
{
@@ -1393,6 +1330,7 @@
fdt_shrink_to_minimum(fdt, 4096); /* Resize with 4096 extra bytes */
addr = map_to_sysmem(fdt);
set_working_fdt_addr(addr);
+ ut_assert_nextline("Working FDT set to %lx", addr);
/* Create DTO which adds single property to root node / */
ut_assertok(fdt_create(fdto, sizeof(fdto)));
@@ -1408,16 +1346,14 @@
addro = map_to_sysmem(fdto);
/* Test default DT print */
- ut_assertok(console_record_reset_enable());
ut_assertok(run_commandf("fdt print /"));
ut_assert_nextline("/ {");
ut_assert_nextline("\t__symbols__ {");
ut_assert_nextline("\t};");
ut_assert_nextline("};");
- ut_assertok(ut_check_console_end(uts));
+ ut_assert_console_end();
/* Test simple DTO application */
- ut_assertok(console_record_reset_enable());
ut_assertok(run_commandf("fdt apply 0x%08lx", addro));
ut_assertok(run_commandf("fdt print /"));
ut_assert_nextline("/ {");
@@ -1425,7 +1361,7 @@
ut_assert_nextline("\t__symbols__ {");
ut_assert_nextline("\t};");
ut_assert_nextline("};");
- ut_assertok(ut_check_console_end(uts));
+ ut_assert_console_end();
/*
* Create complex DTO which:
@@ -1462,7 +1398,6 @@
addro = map_to_sysmem(fdto);
/* Test complex DTO application */
- ut_assertok(console_record_reset_enable());
ut_assertok(run_commandf("fdt apply 0x%08lx", addro));
ut_assertok(run_commandf("fdt print /"));
ut_assert_nextline("/ {");
@@ -1479,7 +1414,7 @@
ut_assert_nextline("\t\tsubnodephandle = \"/subnode\";");
ut_assert_nextline("\t};");
ut_assert_nextline("};");
- ut_assertok(ut_check_console_end(uts));
+ ut_assert_console_end();
/*
* Create complex DTO which:
@@ -1506,7 +1441,6 @@
addro = map_to_sysmem(fdto);
/* Test complex DTO application */
- ut_assertok(console_record_reset_enable());
ut_assertok(run_commandf("fdt apply 0x%08lx", addro));
ut_assertok(run_commandf("fdt print /"));
ut_assert_nextline("/ {");
@@ -1523,11 +1457,11 @@
ut_assert_nextline("\t\tsubnodephandle = \"/subnode\";");
ut_assert_nextline("\t};");
ut_assert_nextline("};");
- ut_assertok(ut_check_console_end(uts));
+ ut_assert_console_end();
return 0;
}
-FDT_TEST(fdt_test_apply, UT_TESTF_CONSOLE_REC);
+FDT_TEST(fdt_test_apply, UTF_CONSOLE);
int do_ut_fdt(struct cmd_tbl *cmdtp, int flag, int argc, char *const argv[])
{
diff --git a/test/cmd/font.c b/test/cmd/font.c
index a8905ce..25d365d 100644
--- a/test/cmd/font.c
+++ b/test/cmd/font.c
@@ -26,12 +26,11 @@
ut_assertok(uclass_first_device_err(UCLASS_VIDEO, &dev));
ut_assertok(uclass_first_device_err(UCLASS_VIDEO_CONSOLE, &dev));
- ut_assertok(console_record_reset_enable());
ut_assertok(run_command("font list", 0));
ut_assert_nextline("nimbus_sans_l_regular");
if (IS_ENABLED(CONFIG_CONSOLE_TRUETYPE_CANTORAONE))
ut_assert_nextline("cantoraone_regular");
- ut_assertok(ut_check_console_end(uts));
+ ut_assert_console_end();
ut_assertok(vidconsole_get_font_size(dev, &name, &size));
ut_asserteq_str("nimbus_sans_l_regular", name);
@@ -49,19 +48,19 @@
if (max_metrics < 2) {
ut_asserteq(1, ret);
ut_assert_nextline("Failed (error -7)");
- ut_assertok(ut_check_console_end(uts));
+ ut_assert_console_end();
return 0;
}
ut_assertok(ret);
- ut_assertok(ut_check_console_end(uts));
+ ut_assert_console_end();
ut_assertok(vidconsole_get_font_size(dev, &name, &size));
ut_asserteq_str("cantoraone_regular", name);
ut_asserteq(40, size);
ut_assertok(run_command("font size 30", 0));
- ut_assertok(ut_check_console_end(uts));
+ ut_assert_console_end();
ut_assertok(vidconsole_get_font_size(dev, &name, &size));
ut_asserteq_str("cantoraone_regular", name);
@@ -69,8 +68,8 @@
return 0;
}
-FONT_TEST(font_test_base, UT_TESTF_SCAN_PDATA | UT_TESTF_SCAN_FDT |
- UT_TESTF_CONSOLE_REC | UT_TESTF_DM);
+FONT_TEST(font_test_base, UTF_SCAN_PDATA | UTF_SCAN_FDT | UTF_CONSOLE |
+ UTF_DM);
int do_ut_font(struct cmd_tbl *cmdtp, int flag, int argc, char *const argv[])
{
diff --git a/test/cmd/history.c b/test/cmd/history.c
index 6964bfa..6d9d228 100644
--- a/test/cmd/history.c
+++ b/test/cmd/history.c
@@ -45,4 +45,4 @@
return 0;
}
-LIB_TEST(lib_test_history, UT_TESTF_CONSOLE_REC);
+LIB_TEST(lib_test_history, UTF_CONSOLE);
diff --git a/test/cmd/loadm.c b/test/cmd/loadm.c
index dff8a97..dedb4f7 100644
--- a/test/cmd/loadm.c
+++ b/test/cmd/loadm.c
@@ -23,7 +23,6 @@
static int loadm_test_params(struct unit_test_state *uts)
{
- ut_assertok(console_record_reset_enable());
run_command("loadm", 0);
ut_assert_nextline("loadm - load binary blob from source address to destination address");
@@ -41,7 +40,7 @@
return 0;
}
-LOADM_TEST(loadm_test_params, UT_TESTF_CONSOLE_REC);
+LOADM_TEST(loadm_test_params, UTF_CONSOLE);
static int loadm_test_load (struct unit_test_state *uts)
{
@@ -51,7 +50,6 @@
memset(buf, '\0', BUF_SIZE);
memset(buf, 0xaa, BUF_SIZE / 2);
- ut_assertok(console_record_reset_enable());
run_command("loadm 0x0 0x80 0x80", 0);
ut_assert_nextline("loaded bin to memory: size: 128");
@@ -59,7 +57,7 @@
return 0;
}
-LOADM_TEST(loadm_test_load, UT_TESTF_CONSOLE_REC);
+LOADM_TEST(loadm_test_load, UTF_CONSOLE);
int do_ut_loadm(struct cmd_tbl *cmdtp, int flag, int argc, char *const argv[])
{
diff --git a/test/cmd/mbr.c b/test/cmd/mbr.c
index 235b363..e1a9cdf 100644
--- a/test/cmd/mbr.c
+++ b/test/cmd/mbr.c
@@ -261,11 +261,10 @@
/* Make sure mmc6 exists */
ut_asserteq(6, blk_get_device_by_str("mmc", "6", &mmc_dev_desc));
- ut_assertok(console_record_reset_enable());
ut_assertok(run_commandf("mmc dev 6"));
ut_assert_nextline("switch to partitions #0, OK");
ut_assert_nextline("mmc6 is current device");
- ut_assertok(ut_check_console_end(uts));
+ ut_assert_console_end();
/* Make sure mmc6 is 12+ MiB in size */
ut_assertok(run_commandf("mmc read 0x%lx 0x%lx 1", ra, (ulong)0xBFFE00 / 0x200));
@@ -281,16 +280,16 @@
memset(rbuf, 0, sizeof(rbuf));
ut_assertok(run_commandf("read mmc 6:0 0x%lx 0x%lx 1", ra, ebr_blk));
ut_assertok(memcmp(ebr_wbuf, rbuf, 512));
- ut_assertok(console_record_reset_enable());
ut_assertf(0 == run_commandf(mbr_parts_buf), "Invalid partitions string: %s\n", mbr_parts_buf);
ut_assertok(run_commandf("mbr write mmc 6"));
+ ut_assert_nextlinen("MMC read: dev # 6");
ut_assert_nextline("MBR: write success!");
ut_assertok(run_commandf("mbr verify mmc 6"));
ut_assert_nextline("MBR: verify success!");
memset(rbuf, 0, sizeof(rbuf));
ut_assertok(run_commandf("read mmc 6:0 0x%lx 0x%lx 1", ra, ebr_blk));
ut_assertok(memcmp(ebr_wbuf, rbuf, 512));
- ut_assertok(ut_check_console_end(uts));
+ ut_assert_console_end();
/*
000001b0 00 00 00 00 00 00 00 00 78 56 34 12 00 00 80 05 |........xV4.....|
000001c0 05 01 0e 25 24 01 00 40 00 00 00 08 00 00 00 00 |...%$..@........|
@@ -317,7 +316,6 @@
memset(rbuf, 0, sizeof(rbuf));
ut_assertok(run_commandf("read mmc 6:0 0x%lx 0x%lx 1", ra, ebr_blk));
ut_assertok(memcmp(ebr_wbuf, rbuf, 512));
- ut_assertok(console_record_reset_enable());
ut_assertf(0 == run_commandf(mbr_parts_buf), "Invalid partitions string: %s\n", mbr_parts_buf);
ut_assertok(run_commandf("mbr write mmc 6"));
ut_assert_nextline("MBR: write success!");
@@ -326,7 +324,7 @@
memset(rbuf, 0, sizeof(rbuf));
ut_assertok(run_commandf("read mmc 6:0 0x%lx 0x%lx 1", ra, ebr_blk));
ut_assertok(memcmp(ebr_wbuf, rbuf, 512));
- ut_assertok(ut_check_console_end(uts));
+ ut_assert_console_end();
/*
000001b0 00 00 00 00 00 00 00 00 78 56 34 12 00 00 80 05 |........xV4.....|
000001c0 05 01 0e 25 24 01 00 40 00 00 00 08 00 00 00 25 |...%$..@.......%|
@@ -353,7 +351,6 @@
memset(rbuf, 0, sizeof(rbuf));
ut_assertok(run_commandf("read mmc 6:0 0x%lx 0x%lx 1", ra, ebr_blk));
ut_assertok(memcmp(ebr_wbuf, rbuf, 512));
- ut_assertok(console_record_reset_enable());
ut_assertf(0 == run_commandf(mbr_parts_buf), "Invalid partitions string: %s\n", mbr_parts_buf);
ut_assertok(run_commandf("mbr write mmc 6"));
ut_assert_nextline("MBR: write success!");
@@ -362,7 +359,7 @@
memset(rbuf, 0, sizeof(rbuf));
ut_assertok(run_commandf("read mmc 6:0 0x%lx 0x%lx 1", ra, ebr_blk));
ut_assertok(memcmp(ebr_wbuf, rbuf, 512));
- ut_assertok(ut_check_console_end(uts));
+ ut_assert_console_end();
/*
000001b0 00 00 00 00 00 00 00 00 78 56 34 12 00 00 80 05 |........xV4.....|
000001c0 05 01 0e 25 24 01 00 40 00 00 00 08 00 00 00 25 |...%$..@.......%|
@@ -389,7 +386,6 @@
memset(rbuf, 0, sizeof(rbuf));
ut_assertok(run_commandf("read mmc 6:0 0x%lx 0x%lx 1", ra, ebr_blk));
ut_assertok(memcmp(ebr_wbuf, rbuf, 512));
- ut_assertok(console_record_reset_enable());
ut_assertf(0 == run_commandf(mbr_parts_buf), "Invalid partitions string: %s\n", mbr_parts_buf);
ut_assertok(run_commandf("mbr write mmc 6"));
ut_assert_nextline("MBR: write success!");
@@ -398,7 +394,7 @@
memset(rbuf, 0, sizeof(rbuf));
ut_assertok(run_commandf("read mmc 6:0 0x%lx 0x%lx 1", ra, ebr_blk));
ut_assertok(memcmp(ebr_wbuf, rbuf, 512));
- ut_assertok(ut_check_console_end(uts));
+ ut_assert_console_end();
/*
000001b0 00 00 00 00 00 00 00 00 78 56 34 12 00 00 80 05 |........xV4.....|
000001c0 05 01 0e 25 24 01 00 40 00 00 00 08 00 00 00 25 |...%$..@.......%|
@@ -425,13 +421,12 @@
memset(rbuf, 0, sizeof(rbuf));
ut_assertok(run_commandf("read mmc 6:0 0x%lx 0x%lx 1", ra, ebr_blk));
ut_assertok(memcmp(ebr_wbuf, rbuf, 512));
- ut_assertok(console_record_reset_enable());
ut_assertf(0 == run_commandf(mbr_parts_buf), "Invalid partitions string: %s\n", mbr_parts_buf);
ut_assertf(0 == run_commandf("mbr write mmc 6"), "Invalid partitions string: %s\n", mbr_parts_buf);
ut_assert_nextline("MBR: write success!");
ut_assertok(run_commandf("mbr verify mmc 6"));
ut_assert_nextline("MBR: verify success!");
- ut_assertok(ut_check_console_end(uts));
+ ut_assert_console_end();
/*
000001b0 00 00 00 00 00 00 00 00 78 56 34 12 00 00 80 05 |........xV4.....|
000001c0 05 01 0e 25 24 01 00 40 00 00 00 08 00 00 00 25 |...%$..@.......%|
@@ -465,7 +460,7 @@
}
/* Declare mbr test */
-UNIT_TEST(mbr_test_run, UT_TESTF_CONSOLE_REC, mbr_test);
+UNIT_TEST(mbr_test_run, UTF_CONSOLE, mbr_test);
int do_ut_mbr(struct cmd_tbl *cmdtp, int flag, int argc, char *const argv[])
{
@@ -479,5 +474,4 @@
{
return mbr_test_run(uts);
}
-
-DM_TEST(dm_test_cmd_mbr, UT_TESTF_SCAN_FDT | UT_TESTF_CONSOLE_REC);
+DM_TEST(dm_test_cmd_mbr, UTF_SCAN_FDT | UTF_CONSOLE);
diff --git a/test/cmd/mem_search.c b/test/cmd/mem_search.c
index 55ad2fa..3a031ee 100644
--- a/test/cmd/mem_search.c
+++ b/test/cmd/mem_search.c
@@ -27,7 +27,6 @@
buf[0x31] = 0x12;
buf[0xff] = 0x12;
buf[0x100] = 0x12;
- ut_assertok(console_record_reset_enable());
run_command("ms.b 1 ff 12", 0);
ut_assert_nextline("00000030: 00 12 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ................");
ut_assert_nextline("--");
@@ -43,7 +42,7 @@
return 0;
}
-MEM_TEST(mem_test_ms_b, UT_TESTF_CONSOLE_REC);
+MEM_TEST(mem_test_ms_b, UTF_CONSOLE);
/* Test 'ms' command with 16-bit values */
static int mem_test_ms_w(struct unit_test_state *uts)
@@ -54,7 +53,6 @@
memset(buf, '\0', BUF_SIZE);
buf[0x34 / 2] = 0x1234;
buf[BUF_SIZE / 2] = 0x1234;
- ut_assertok(console_record_reset_enable());
run_command("ms.w 0 80 1234", 0);
ut_assert_nextline("00000030: 0000 0000 1234 0000 0000 0000 0000 0000 ....4...........");
ut_assert_nextline("1 match");
@@ -68,7 +66,7 @@
return 0;
}
-MEM_TEST(mem_test_ms_w, UT_TESTF_CONSOLE_REC);
+MEM_TEST(mem_test_ms_w, UTF_CONSOLE);
/* Test 'ms' command with 32-bit values */
static int mem_test_ms_l(struct unit_test_state *uts)
@@ -79,7 +77,6 @@
memset(buf, '\0', BUF_SIZE);
buf[0x38 / 4] = 0x12345678;
buf[BUF_SIZE / 4] = 0x12345678;
- ut_assertok(console_record_reset_enable());
run_command("ms 0 40 12345678", 0);
ut_assert_nextline("00000030: 00000000 00000000 12345678 00000000 ........xV4.....");
ut_assert_nextline("1 match");
@@ -89,7 +86,6 @@
ut_asserteq(0x38, env_get_hex("memaddr", 0));
ut_asserteq(0x38 / 4, env_get_hex("mempos", 0));
- ut_assertok(console_record_reset_enable());
run_command("ms 0 80 12345679", 0);
ut_assert_nextline("0 matches");
ut_assert_console_end();
@@ -102,7 +98,7 @@
return 0;
}
-MEM_TEST(mem_test_ms_l, UT_TESTF_CONSOLE_REC);
+MEM_TEST(mem_test_ms_l, UTF_CONSOLE);
/* Test 'ms' command with continuation */
static int mem_test_ms_cont(struct unit_test_state *uts)
@@ -116,7 +112,6 @@
memset(buf, '\0', BUF_SIZE);
for (i = 5; i < 0x33; i += 3)
buf[i] = 0x34;
- ut_assertok(console_record_reset_enable());
run_command("ms.b 0 100 34", 0);
ut_assert_nextlinen("00000000: 00 00 00 00 00 34 00 00 34 00 00 34 00 00 34 00");
ut_assert_nextline("--");
@@ -134,7 +129,6 @@
* run_command() ignoes the repeatable flag when using hush, so call
* cmd_process() directly
*/
- ut_assertok(console_record_reset_enable());
cmd_process(CMD_FLAG_REPEAT, 4, args, &repeatable, NULL);
ut_assert_nextlinen("00000020: 34 00 00 34 00 00 34 00 00 34 00 00 34 00 00 34");
ut_assert_nextline("--");
@@ -152,7 +146,7 @@
return 0;
}
-MEM_TEST(mem_test_ms_cont, UT_TESTF_CONSOLE_REC);
+MEM_TEST(mem_test_ms_cont, UTF_CONSOLE);
/* Test that an 'ms' command with continuation stops at the end of the range */
static int mem_test_ms_cont_end(struct unit_test_state *uts)
@@ -167,7 +161,6 @@
buf[0x31] = 0x12;
buf[0xff] = 0x12;
buf[0x100] = 0x12;
- ut_assertok(console_record_reset_enable());
run_command("ms.b 1 ff 12", 0);
ut_assert_nextlinen("00000030");
ut_assert_nextlinen("--");
@@ -181,13 +174,11 @@
*
* This should produce no matches.
*/
- ut_assertok(console_record_reset_enable());
cmd_process(CMD_FLAG_REPEAT, 4, args, &repeatable, NULL);
ut_assert_nextlinen("0 matches");
ut_assert_console_end();
/* One more time */
- ut_assertok(console_record_reset_enable());
cmd_process(CMD_FLAG_REPEAT, 4, args, &repeatable, NULL);
ut_assert_nextlinen("0 matches");
ut_assert_console_end();
@@ -196,7 +187,7 @@
return 0;
}
-MEM_TEST(mem_test_ms_cont_end, UT_TESTF_CONSOLE_REC);
+MEM_TEST(mem_test_ms_cont_end, UTF_CONSOLE);
/* Test 'ms' command with multiple values */
static int mem_test_ms_mult(struct unit_test_state *uts)
@@ -225,7 +216,7 @@
return 0;
}
-MEM_TEST(mem_test_ms_mult, UT_TESTF_CONSOLE_REC);
+MEM_TEST(mem_test_ms_mult, UTF_CONSOLE);
/* Test 'ms' command with string */
static int mem_test_ms_s(struct unit_test_state *uts)
@@ -239,7 +230,6 @@
strcpy(buf + 0x1e, str);
strcpy(buf + 0x63, str);
strcpy(buf + 0xa1, str2);
- ut_assertok(console_record_reset_enable());
run_command("ms.s 0 100 hello", 0);
ut_assert_nextline("00000010: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 68 65 ..............he");
ut_assert_nextline("00000020: 6c 6c 6f 00 00 00 00 00 00 00 00 00 00 00 00 00 llo.............");
@@ -254,7 +244,6 @@
ut_asserteq(0xa1, env_get_hex("memaddr", 0));
ut_asserteq(0xa1, env_get_hex("mempos", 0));
- ut_assertok(console_record_reset_enable());
run_command("ms.s 0 100 hello there", 0);
ut_assert_nextline("000000a0: 00 68 65 6c 6c 6f 74 68 65 72 65 00 00 00 00 00 .hellothere.....");
ut_assert_nextline("1 match");
@@ -268,7 +257,7 @@
return 0;
}
-MEM_TEST(mem_test_ms_s, UT_TESTF_CONSOLE_REC);
+MEM_TEST(mem_test_ms_s, UTF_CONSOLE);
/* Test 'ms' command with limit */
static int mem_test_ms_limit(struct unit_test_state *uts)
@@ -281,7 +270,6 @@
buf[0x31] = 0x12;
buf[0x62] = 0x12;
buf[0x76] = 0x12;
- ut_assertok(console_record_reset_enable());
run_command("ms.b -l2 1 ff 12", 0);
ut_assert_nextline("00000030: 00 12 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ................");
ut_assert_nextline("--");
@@ -297,7 +285,7 @@
return 0;
}
-MEM_TEST(mem_test_ms_limit, UT_TESTF_CONSOLE_REC);
+MEM_TEST(mem_test_ms_limit, UTF_CONSOLE);
/* Test 'ms' command in quiet mode */
static int mem_test_ms_quiet(struct unit_test_state *uts)
@@ -310,7 +298,6 @@
buf[0x31] = 0x12;
buf[0x62] = 0x12;
buf[0x76] = 0x12;
- ut_assertok(console_record_reset_enable());
run_command("ms.b -q -l2 1 ff 12", 0);
ut_assert_console_end();
unmap_sysmem(buf);
@@ -321,4 +308,4 @@
return 0;
}
-MEM_TEST(mem_test_ms_quiet, UT_TESTF_CONSOLE_REC);
+MEM_TEST(mem_test_ms_quiet, UTF_CONSOLE);
diff --git a/test/cmd/pci_mps.c b/test/cmd/pci_mps.c
index 2a64143..a265105 100644
--- a/test/cmd/pci_mps.c
+++ b/test/cmd/pci_mps.c
@@ -27,8 +27,7 @@
return 0;
}
-
-PCI_MPS_TEST(test_pci_mps_safe, UT_TESTF_CONSOLE_REC);
+PCI_MPS_TEST(test_pci_mps_safe, UTF_CONSOLE);
int do_ut_pci_mps(struct cmd_tbl *cmdtp, int flag, int argc,
char * const argv[])
diff --git a/test/cmd/pinmux.c b/test/cmd/pinmux.c
index 4253baa..65974d0 100644
--- a/test/cmd/pinmux.c
+++ b/test/cmd/pinmux.c
@@ -18,23 +18,26 @@
ut_assertok(uclass_get_device(UCLASS_LED, 2, &dev));
/* Test that 'pinmux status <pinname>' displays the selected pin. */
- console_record_reset();
run_command("pinmux status a5", 0);
ut_assert_nextlinen("a5 : gpio output .");
ut_assert_console_end();
- console_record_reset();
run_command("pinmux status P7", 0);
ut_assert_nextlinen("P7 : GPIO2 bias-pull-down input-enable.");
ut_assert_console_end();
- console_record_reset();
run_command("pinmux status P9", 0);
- ut_assert_nextlinen("single-pinctrl pinctrl-single-no-width: missing register width");
+ if (IS_ENABLED(CONFIG_LOGF_FUNC)) {
+ ut_assert_nextlinen(
+ " single_of_to_plat() single-pinctrl pinctrl-single-no-width: missing register width");
+ } else {
+ ut_assert_nextlinen(
+ "single-pinctrl pinctrl-single-no-width: missing register width");
+ }
ut_assert_nextlinen("P9 not found");
ut_assert_console_end();
return 0;
}
-
-DM_TEST(dm_test_cmd_pinmux_status_pinname, UT_TESTF_SCAN_PDATA | UT_TESTF_SCAN_FDT);
+DM_TEST(dm_test_cmd_pinmux_status_pinname, UTF_SCAN_PDATA | UTF_SCAN_FDT |
+ UTF_CONSOLE);
diff --git a/test/cmd/pwm.c b/test/cmd/pwm.c
index cf7ee0e..0d47e2d 100644
--- a/test/cmd/pwm.c
+++ b/test/cmd/pwm.c
@@ -22,8 +22,6 @@
ut_assertok(uclass_get_device(UCLASS_PWM, 0, &dev));
ut_assertnonnull(dev);
- ut_assertok(console_record_reset_enable());
-
/* pwm <invert> <pwm_dev_num> <channel> <polarity> */
/* cros-ec-pwm doesn't support invert */
ut_asserteq(1, run_command("pwm invert 0 0 1", 0));
@@ -49,8 +47,6 @@
ut_assertok(uclass_get_device(UCLASS_PWM, 1, &dev));
ut_assertnonnull(dev);
- ut_assertok(console_record_reset_enable());
-
/* pwm <invert> <pwm_dev_num> <channel> <polarity> */
ut_assertok(run_command("pwm invert 1 0 1", 0));
ut_assert_console_end();
@@ -71,5 +67,4 @@
return 0;
}
-
-DM_TEST(dm_test_pwm_cmd, UT_TESTF_SCAN_PDATA | UT_TESTF_SCAN_FDT | UT_TESTF_CONSOLE_REC);
+DM_TEST(dm_test_pwm_cmd, UTF_SCAN_PDATA | UTF_SCAN_FDT | UTF_CONSOLE);
diff --git a/test/cmd/rw.c b/test/cmd/rw.c
index edd762e..0a856c4 100644
--- a/test/cmd/rw.c
+++ b/test/cmd/rw.c
@@ -87,17 +87,14 @@
ut_assertok(memcmp(wbuf, rbuf, sizeof(wbuf)));
/* Read/write outside partition bounds should be rejected upfront. */
- console_record_reset_enable();
ut_asserteq(1, run_commandf("read mmc 2#data 0x%lx 3 2", ra));
ut_assert_nextlinen("read out of range");
ut_assert_console_end();
- console_record_reset_enable();
ut_asserteq(1, run_commandf("write mmc 2#log 0x%lx 9 2", wa));
ut_assert_nextlinen("write out of range");
ut_assert_console_end();
return 0;
}
-
-DM_TEST(dm_test_read_write, UT_TESTF_SCAN_FDT | UT_TESTF_CONSOLE_REC);
+DM_TEST(dm_test_read_write, UTF_SCAN_FDT | UTF_CONSOLE);
diff --git a/test/cmd/seama.c b/test/cmd/seama.c
index b60f655..28d6b9a 100644
--- a/test/cmd/seama.c
+++ b/test/cmd/seama.c
@@ -16,7 +16,6 @@
static int seama_test_noargs(struct unit_test_state *uts)
{
/* Test that 'seama' with no arguments fails gracefully */
- console_record_reset();
run_command("seama", 0);
ut_assert_nextlinen("seama - Load the SEAMA image and sets envs");
ut_assert_skipline();
@@ -26,12 +25,11 @@
ut_assert_console_end();
return 0;
}
-SEAMA_TEST(seama_test_noargs, UT_TESTF_CONSOLE_REC);
+SEAMA_TEST(seama_test_noargs, UTF_CONSOLE);
static int seama_test_addr(struct unit_test_state *uts)
{
/* Test that loads SEAMA image 0 to address 0x01000000 */
- console_record_reset();
run_command("seama 0x01000000", 0);
ut_assert_nextlinen("Loading SEAMA image 0 from nand0");
ut_assert_nextlinen("SEMA IMAGE:");
@@ -42,12 +40,11 @@
ut_assert_console_end();
return 0;
}
-SEAMA_TEST(seama_test_addr, UT_TESTF_CONSOLE_REC);
+SEAMA_TEST(seama_test_addr, UTF_CONSOLE);
static int seama_test_index(struct unit_test_state *uts)
{
/* Test that loads SEAMA image 0 exlicitly specified */
- console_record_reset();
run_command("seama 0x01000000 0", 0);
ut_assert_nextlinen("Loading SEAMA image 0 from nand0");
ut_assert_nextlinen("SEMA IMAGE:");
@@ -58,7 +55,7 @@
ut_assert_console_end();
return 0;
}
-SEAMA_TEST(seama_test_index, UT_TESTF_CONSOLE_REC);
+SEAMA_TEST(seama_test_index, UTF_CONSOLE);
int do_ut_seama(struct cmd_tbl *cmdtp, int flag, int argc, char *const argv[])
{
diff --git a/test/cmd/setexpr.c b/test/cmd/setexpr.c
index 4c6cc3c..21a3268 100644
--- a/test/cmd/setexpr.c
+++ b/test/cmd/setexpr.c
@@ -63,7 +63,7 @@
return 0;
}
-SETEXPR_TEST(setexpr_test_int, UT_TESTF_CONSOLE_REC);
+SETEXPR_TEST(setexpr_test_int, UTF_CONSOLE);
/* Test 'setexpr' command with + operator */
static int setexpr_test_plus(struct unit_test_state *uts)
@@ -105,7 +105,7 @@
return 0;
}
-SETEXPR_TEST(setexpr_test_plus, UT_TESTF_CONSOLE_REC);
+SETEXPR_TEST(setexpr_test_plus, UTF_CONSOLE);
/* Test 'setexpr' command with other operators */
static int setexpr_test_oper(struct unit_test_state *uts)
@@ -148,7 +148,7 @@
return 0;
}
-SETEXPR_TEST(setexpr_test_oper, UT_TESTF_CONSOLE_REC);
+SETEXPR_TEST(setexpr_test_oper, UTF_CONSOLE);
/* Test 'setexpr' command with regex */
static int setexpr_test_regex(struct unit_test_state *uts)
@@ -192,7 +192,7 @@
return 0;
}
-SETEXPR_TEST(setexpr_test_regex, UT_TESTF_CONSOLE_REC);
+SETEXPR_TEST(setexpr_test_regex, UTF_CONSOLE);
/* Test 'setexpr' command with regex replacement that expands the string */
static int setexpr_test_regex_inc(struct unit_test_state *uts)
@@ -209,7 +209,7 @@
return 0;
}
-SETEXPR_TEST(setexpr_test_regex_inc, UT_TESTF_CONSOLE_REC);
+SETEXPR_TEST(setexpr_test_regex_inc, UTF_CONSOLE);
/* Test setexpr_regex_sub() directly to check buffer usage */
static int setexpr_test_sub(struct unit_test_state *uts)
@@ -249,7 +249,7 @@
return 0;
}
-SETEXPR_TEST(setexpr_test_sub, UT_TESTF_CONSOLE_REC);
+SETEXPR_TEST(setexpr_test_sub, UTF_CONSOLE);
/* Test setexpr_regex_sub() with back references */
static int setexpr_test_backref(struct unit_test_state *uts)
@@ -292,7 +292,7 @@
return 0;
}
-SETEXPR_TEST(setexpr_test_backref, UT_TESTF_CONSOLE_REC);
+SETEXPR_TEST(setexpr_test_backref, UTF_CONSOLE);
/* Test 'setexpr' command with setting strings */
static int setexpr_test_str(struct unit_test_state *uts)
@@ -327,7 +327,7 @@
return 0;
}
-SETEXPR_TEST(setexpr_test_str, UT_TESTF_CONSOLE_REC);
+SETEXPR_TEST(setexpr_test_str, UTF_CONSOLE);
/* Test 'setexpr' command with concatenating strings */
static int setexpr_test_str_oper(struct unit_test_state *uts)
@@ -340,7 +340,6 @@
strcpy(buf, "hello");
strcpy(buf + 0x10, " there");
- ut_assertok(console_record_reset_enable());
start_mem = ut_check_free();
ut_asserteq(1, run_command("setexpr.s fred *0 * *10", 0));
ut_assertok(ut_check_delta(start_mem));
@@ -376,7 +375,7 @@
return 0;
}
-SETEXPR_TEST(setexpr_test_str_oper, UT_TESTF_CONSOLE_REC);
+SETEXPR_TEST(setexpr_test_str_oper, UTF_CONSOLE);
/* Test 'setexpr' command with a string that is too long */
static int setexpr_test_str_long(struct unit_test_state *uts)
@@ -396,7 +395,7 @@
return 0;
}
-SETEXPR_TEST(setexpr_test_str_long, UT_TESTF_CONSOLE_REC);
+SETEXPR_TEST(setexpr_test_str_long, UTF_CONSOLE);
#ifdef CONFIG_CMD_SETEXPR_FMT
/* Test 'setexpr' command with simply setting integers */
@@ -478,8 +477,7 @@
return 0;
}
-
-SETEXPR_TEST(setexpr_test_fmt, UT_TESTF_CONSOLE_REC);
+SETEXPR_TEST(setexpr_test_fmt, UTF_CONSOLE);
#endif
int do_ut_setexpr(struct cmd_tbl *cmdtp, int flag, int argc, char *const argv[])
diff --git a/test/cmd/temperature.c b/test/cmd/temperature.c
index 3649726..309693a 100644
--- a/test/cmd/temperature.c
+++ b/test/cmd/temperature.c
@@ -18,8 +18,6 @@
ut_assertok(uclass_get_device(UCLASS_THERMAL, 0, &dev));
ut_assertnonnull(dev);
- ut_assertok(console_record_reset_enable());
-
/* Test that "temperature list" shows the sandbox device */
ut_assertok(run_command("temperature list", 0));
ut_assert_nextline("| Device | Driver | Parent");
@@ -34,5 +32,4 @@
return 0;
}
-
-DM_TEST(dm_test_cmd_temperature, UT_TESTF_SCAN_FDT | UT_TESTF_CONSOLE_REC);
+DM_TEST(dm_test_cmd_temperature, UTF_SCAN_FDT | UTF_CONSOLE);
diff --git a/test/cmd/test_echo.c b/test/cmd/test_echo.c
index cde74eb..8b306cc 100644
--- a/test/cmd/test_echo.c
+++ b/test/cmd/test_echo.c
@@ -45,16 +45,12 @@
int i;
for (i = 0; i < ARRAY_SIZE(echo_data); ++i) {
- ut_silence_console(uts);
- console_record_reset_enable();
ut_assertok(run_command(echo_data[i].cmd, 0));
- ut_unsilence_console(uts);
console_record_readline(uts->actual_str,
sizeof(uts->actual_str));
ut_asserteq_str(echo_data[i].expected, uts->actual_str);
- ut_assertok(ut_check_console_end(uts));
+ ut_assert_console_end();
}
return 0;
}
-
-LIB_TEST(lib_test_hush_echo, 0);
+LIB_TEST(lib_test_hush_echo, UTF_CONSOLE);
diff --git a/test/cmd/test_pause.c b/test/cmd/test_pause.c
index 3703290..174c31a 100644
--- a/test/cmd/test_pause.c
+++ b/test/cmd/test_pause.c
@@ -14,25 +14,22 @@
static int lib_test_hush_pause(struct unit_test_state *uts)
{
/* Test default message */
- console_record_reset_enable();
/* Cook a newline when the command is expected to pause */
console_in_puts("\n");
ut_assertok(run_command("pause", 0));
console_record_readline(uts->actual_str, sizeof(uts->actual_str));
ut_asserteq_str("Press any key to continue...", uts->actual_str);
- ut_assertok(ut_check_console_end(uts));
+ ut_assert_console_end();
/* Test provided message */
- console_record_reset_enable();
/* Cook a newline when the command is expected to pause */
console_in_puts("\n");
ut_assertok(run_command("pause 'Prompt for pause...'", 0));
console_record_readline(uts->actual_str, sizeof(uts->actual_str));
ut_asserteq_str("Prompt for pause...", uts->actual_str);
- ut_assertok(ut_check_console_end(uts));
+ ut_assert_console_end();
/* Test providing more than one params */
- console_record_reset_enable();
/* No newline cooked here since the command is expected to fail */
ut_asserteq(1, run_command("pause a b", 0));
console_record_readline(uts->actual_str, sizeof(uts->actual_str));
@@ -41,4 +38,4 @@
return 0;
}
-LIB_TEST(lib_test_hush_pause, 0);
+LIB_TEST(lib_test_hush_pause, UTF_CONSOLE);
diff --git a/test/cmd/wget.c b/test/cmd/wget.c
index 356a4dc..fe26fee 100644
--- a/test/cmd/wget.c
+++ b/test/cmd/wget.c
@@ -26,6 +26,8 @@
#define SHIFT_TO_TCPHDRLEN_FIELD(x) ((x) << 4)
#define LEN_B_TO_DW(x) ((x) >> 2)
+int net_set_ack_options(union tcp_build_pkt *b);
+
static int sb_arp_handler(struct udevice *dev, void *packet,
unsigned int len)
{
@@ -105,6 +107,10 @@
const char *payload1 = "HTTP/1.1 200 OK\r\n"
"Content-Length: 30\r\n\r\n\r\n"
"<html><body>Hi</body></html>\r\n";
+ union tcp_build_pkt *b = (union tcp_build_pkt *)tcp;
+ const int recv_payload_len = len - net_set_ack_options(b) - IP_HDR_SIZE - ETHER_HDR_SIZE;
+ static int next_seq;
+ const int bottom_payload_len = 10;
/* Don't allow the buffer to overrun */
if (priv->recv_packets >= PKTBUFSRX)
@@ -119,13 +125,31 @@
tcp_send->tcp_dst = tcp->tcp_src;
data = (void *)tcp_send + IP_TCP_HDR_SIZE;
- if (ntohl(tcp->tcp_seq) == 1 && ntohl(tcp->tcp_ack) == 1) {
+ if (ntohl(tcp->tcp_seq) == 1 && ntohl(tcp->tcp_ack) == 1 && recv_payload_len == 0) {
+ // ignore ACK for three-way handshaking
+ return 0;
+ } else if (ntohl(tcp->tcp_seq) == 1 && ntohl(tcp->tcp_ack) == 1) {
+ // recv HTTP request message and reply top half data
tcp_send->tcp_seq = htonl(ntohl(tcp->tcp_ack));
- tcp_send->tcp_ack = htonl(ntohl(tcp->tcp_seq) + 1);
- payload_len = strlen(payload1);
+ tcp_send->tcp_ack = htonl(ntohl(tcp->tcp_seq) + recv_payload_len);
+
+ payload_len = strlen(payload1) - bottom_payload_len;
memcpy(data, payload1, payload_len);
tcp_send->tcp_flags = TCP_ACK;
+
+ next_seq = ntohl(tcp_send->tcp_seq) + payload_len;
+ } else if (ntohl(tcp->tcp_ack) == next_seq) {
+ // reply bottom half data
+ const int top_payload_len = strlen(payload1) - bottom_payload_len;
+
+ tcp_send->tcp_seq = htonl(next_seq);
+ tcp_send->tcp_ack = htonl(ntohl(tcp->tcp_seq) + recv_payload_len);
+
+ payload_len = bottom_payload_len;
+ memcpy(data, payload1 + top_payload_len, payload_len);
+ tcp_send->tcp_flags = TCP_ACK;
- } else if (ntohl(tcp->tcp_seq) == 2) {
+ } else {
+ // close connection
tcp_send->tcp_seq = htonl(ntohl(tcp->tcp_ack));
tcp_send->tcp_ack = htonl(ntohl(tcp->tcp_seq) + 1);
payload_len = 0;
@@ -148,11 +172,9 @@
pkt_len,
IPPROTO_TCP);
- if (ntohl(tcp->tcp_seq) == 1 || ntohl(tcp->tcp_seq) == 2) {
- priv->recv_packet_length[priv->recv_packets] =
- ETHER_HDR_SIZE + IP_TCP_HDR_SIZE + payload_len;
- ++priv->recv_packets;
- }
+ priv->recv_packet_length[priv->recv_packets] =
+ ETHER_HDR_SIZE + IP_TCP_HDR_SIZE + payload_len;
+ ++priv->recv_packets;
return 0;
}
@@ -191,15 +213,16 @@
env_set("ethrotate", "no");
env_set("loadaddr", "0x20000");
ut_assertok(run_command("wget ${loadaddr} 1.1.2.2:/index.html", 0));
+ ut_assert_nextline("HTTP/1.1 200 OK");
+ ut_assert_nextline("Packets received 5, Transfer Successful");
+ ut_assert_nextline("Bytes transferred = 32 (20 hex)");
sandbox_eth_set_tx_handler(0, NULL);
- ut_assertok(console_record_reset_enable());
run_command("md5sum ${loadaddr} ${filesize}", 0);
ut_assert_nextline("md5 for 00020000 ... 0002001f ==> 234af48e94b0085060249ecb5942ab57");
- ut_assertok(ut_check_console_end(uts));
+ ut_assert_console_end();
return 0;
}
-
-LIB_TEST(net_test_wget, 0);
+LIB_TEST(net_test_wget, UTF_CONSOLE);
diff --git a/test/cmd_ut.c b/test/cmd_ut.c
index 4e4aa8f..38ba89e 100644
--- a/test/cmd_ut.c
+++ b/test/cmd_ut.c
@@ -133,6 +133,9 @@
#ifdef CONFIG_CMD_SEAMA
U_BOOT_CMD_MKENT(seama, CONFIG_SYS_MAXARGS, 1, do_ut_seama, "", ""),
#endif
+#ifdef CONFIG_CMD_UPL
+ U_BOOT_CMD_MKENT(upl, CONFIG_SYS_MAXARGS, 1, do_ut_upl, "", ""),
+#endif
};
static int do_ut_all(struct cmd_tbl *cmdtp, int flag, int argc,
diff --git a/test/common/cread.c b/test/common/cread.c
index e159cae..4926c21 100644
--- a/test/common/cread.c
+++ b/test/common/cread.c
@@ -66,8 +66,6 @@
* print_buffer(0, buf, 1, 7, 0);
*/
- console_record_reset_enable();
-
/* simple input */
*buf = '\0';
ut_asserteq(4, console_in_puts("abc\n"));
@@ -102,4 +100,4 @@
return 0;
}
-COMMON_TEST(cread_test, 0);
+COMMON_TEST(cread_test, UTF_CONSOLE);
diff --git a/test/common/event.c b/test/common/event.c
index de433d3..bfbbf01 100644
--- a/test/common/event.c
+++ b/test/common/event.c
@@ -106,4 +106,4 @@
return 0;
}
-COMMON_TEST(test_event_probe, UT_TESTF_DM | UT_TESTF_SCAN_FDT);
+COMMON_TEST(test_event_probe, UTF_DM | UTF_SCAN_FDT);
diff --git a/test/common/test_autoboot.c b/test/common/test_autoboot.c
index 4ba1dcc..e3050d0 100644
--- a/test/common/test_autoboot.c
+++ b/test/common/test_autoboot.c
@@ -20,7 +20,6 @@
const char *autoboot_prompt =
"Enter password \"a\" in 1 seconds to stop autoboot";
- console_record_reset_enable();
console_in_puts(in);
/* turn on keyed autoboot for the test, if possible */
@@ -91,5 +90,4 @@
return CMD_RET_SUCCESS;
}
-
-COMMON_TEST(test_autoboot, 0);
+COMMON_TEST(test_autoboot, UTF_CONSOLE);
diff --git a/test/dm/acpi.c b/test/dm/acpi.c
index 7da381f..7ccd7f8 100644
--- a/test/dm/acpi.c
+++ b/test/dm/acpi.c
@@ -195,7 +195,7 @@
return 0;
}
-DM_TEST(dm_test_acpi_get_name, UT_TESTF_SCAN_PDATA | UT_TESTF_SCAN_FDT);
+DM_TEST(dm_test_acpi_get_name, UTF_SCAN_PDATA | UTF_SCAN_FDT);
/* Test acpi_get_table_revision() */
static int dm_test_acpi_get_table_revision(struct unit_test_state *uts)
@@ -207,8 +207,7 @@
return 0;
}
-DM_TEST(dm_test_acpi_get_table_revision,
- UT_TESTF_SCAN_PDATA | UT_TESTF_SCAN_FDT);
+DM_TEST(dm_test_acpi_get_table_revision, UTF_SCAN_PDATA | UTF_SCAN_FDT);
/* Test acpi_create_dmar() */
static int dm_test_acpi_create_dmar(struct unit_test_state *uts)
@@ -225,7 +224,7 @@
return 0;
}
-DM_TEST(dm_test_acpi_create_dmar, UT_TESTF_SCAN_PDATA | UT_TESTF_SCAN_FDT);
+DM_TEST(dm_test_acpi_create_dmar, UTF_SCAN_PDATA | UTF_SCAN_FDT);
/* Test acpi_fill_header() */
static int dm_test_acpi_fill_header(struct unit_test_state *uts)
@@ -251,7 +250,7 @@
return 0;
}
-DM_TEST(dm_test_acpi_fill_header, UT_TESTF_SCAN_PDATA | UT_TESTF_SCAN_FDT);
+DM_TEST(dm_test_acpi_fill_header, UTF_SCAN_PDATA | UTF_SCAN_FDT);
/* Test ACPI write_tables() */
static int dm_test_acpi_write_tables(struct unit_test_state *uts)
@@ -297,7 +296,7 @@
return 0;
}
-DM_TEST(dm_test_acpi_write_tables, UT_TESTF_SCAN_PDATA | UT_TESTF_SCAN_FDT);
+DM_TEST(dm_test_acpi_write_tables, UTF_SCAN_PDATA | UTF_SCAN_FDT);
/* Test basic ACPI functions */
static int dm_test_acpi_basic(struct unit_test_state *uts)
@@ -325,7 +324,7 @@
return 0;
}
-DM_TEST(dm_test_acpi_basic, UT_TESTF_SCAN_PDATA | UT_TESTF_SCAN_FDT);
+DM_TEST(dm_test_acpi_basic, UTF_SCAN_PDATA | UTF_SCAN_FDT);
/* Test setup_ctx_and_base_tables */
static int dm_test_acpi_ctx_and_base_tables(struct unit_test_state *uts)
@@ -374,8 +373,7 @@
return 0;
}
-DM_TEST(dm_test_acpi_ctx_and_base_tables,
- UT_TESTF_SCAN_PDATA | UT_TESTF_SCAN_FDT);
+DM_TEST(dm_test_acpi_ctx_and_base_tables, UTF_SCAN_PDATA | UTF_SCAN_FDT);
/* Test 'acpi list' command */
static int dm_test_acpi_cmd_list(struct unit_test_state *uts)
@@ -391,7 +389,6 @@
ut_assertok(acpi_write_dev_tables(&ctx));
- console_record_reset();
run_command("acpi list", 0);
ut_assert_nextline("Name Base Size Detail");
ut_assert_nextline("---- ---------------- ----- ----------------------------");
@@ -418,7 +415,7 @@
return 0;
}
-DM_TEST(dm_test_acpi_cmd_list, UT_TESTF_SCAN_PDATA | UT_TESTF_SCAN_FDT);
+DM_TEST(dm_test_acpi_cmd_list, UTF_SCAN_PDATA | UTF_SCAN_FDT | UTF_CONSOLE);
/* Test 'acpi dump' command */
static int dm_test_acpi_cmd_dump(struct unit_test_state *uts)
@@ -435,13 +432,11 @@
ut_assertok(acpi_write_dev_tables(&ctx));
/* First search for a non-existent table */
- console_record_reset();
run_command("acpi dump rdst", 0);
ut_assert_nextline("Table 'RDST' not found");
ut_assert_console_end();
/* Now a real table */
- console_record_reset();
run_command("acpi dump dmar", 0);
addr = ALIGN(nomap_to_sysmem(ctx.xsdt) + sizeof(struct acpi_xsdt), 64);
ut_assert_nextline("DMAR @ %16lx", addr);
@@ -450,7 +445,7 @@
return 0;
}
-DM_TEST(dm_test_acpi_cmd_dump, UT_TESTF_SCAN_PDATA | UT_TESTF_SCAN_FDT);
+DM_TEST(dm_test_acpi_cmd_dump, UTF_SCAN_PDATA | UTF_SCAN_FDT | UTF_CONSOLE);
/* Test acpi_device_path() */
static int dm_test_acpi_device_path(struct unit_test_state *uts)
@@ -487,7 +482,7 @@
return 0;
}
-DM_TEST(dm_test_acpi_device_path, UT_TESTF_SCAN_PDATA | UT_TESTF_SCAN_FDT);
+DM_TEST(dm_test_acpi_device_path, UTF_SCAN_PDATA | UTF_SCAN_FDT);
/* Test acpi_device_status() */
static int dm_test_acpi_device_status(struct unit_test_state *uts)
@@ -499,7 +494,7 @@
return 0;
}
-DM_TEST(dm_test_acpi_device_status, UT_TESTF_SCAN_PDATA | UT_TESTF_SCAN_FDT);
+DM_TEST(dm_test_acpi_device_status, UTF_SCAN_PDATA | UTF_SCAN_FDT);
/* Test acpi_fill_ssdt() */
static int dm_test_acpi_fill_ssdt(struct unit_test_state *uts)
@@ -530,7 +525,7 @@
return 0;
}
-DM_TEST(dm_test_acpi_fill_ssdt, UT_TESTF_SCAN_PDATA | UT_TESTF_SCAN_FDT);
+DM_TEST(dm_test_acpi_fill_ssdt, UTF_SCAN_PDATA | UTF_SCAN_FDT);
/* Test acpi_inject_dsdt() */
static int dm_test_acpi_inject_dsdt(struct unit_test_state *uts)
@@ -561,7 +556,7 @@
return 0;
}
-DM_TEST(dm_test_acpi_inject_dsdt, UT_TESTF_SCAN_PDATA | UT_TESTF_SCAN_FDT);
+DM_TEST(dm_test_acpi_inject_dsdt, UTF_SCAN_PDATA | UTF_SCAN_FDT);
/* Test 'acpi items' command */
static int dm_test_acpi_cmd_items(struct unit_test_state *uts)
@@ -577,7 +572,6 @@
acpi_reset_items();
ctx.current = buf;
ut_assertok(acpi_fill_ssdt(&ctx));
- console_record_reset();
run_command("acpi items", 0);
ut_assert_nextline("Seq Type Base Size Device/Writer");
ut_assert_nextline("--- ----- -------- ---- -------------");
@@ -588,7 +582,6 @@
acpi_reset_items();
ctx.current = buf;
ut_assertok(acpi_inject_dsdt(&ctx));
- console_record_reset();
run_command("acpi items", 0);
ut_assert_nextlinen("Seq");
ut_assert_nextlinen("---");
@@ -596,7 +589,6 @@
ut_assert_nextline(" 1 dsdt %8lx 2 acpi-test2", addr + 2);
ut_assert_console_end();
- console_record_reset();
run_command("acpi items -d", 0);
ut_assert_nextlinen("Seq");
ut_assert_nextlinen("---");
@@ -610,7 +602,7 @@
return 0;
}
-DM_TEST(dm_test_acpi_cmd_items, UT_TESTF_SCAN_PDATA | UT_TESTF_SCAN_FDT);
+DM_TEST(dm_test_acpi_cmd_items, UTF_SCAN_PDATA | UTF_SCAN_FDT | UTF_CONSOLE);
/* Test 'acpi set' command */
static int dm_test_acpi_cmd_set(struct unit_test_state *uts)
@@ -621,7 +613,6 @@
gd_set_acpi_start(0);
- console_record_reset();
ut_asserteq(0, gd_acpi_start());
ut_assertok(run_command("acpi set", 0));
ut_assert_nextline("ACPI pointer: 0");
@@ -648,7 +639,7 @@
return 0;
}
-DM_TEST(dm_test_acpi_cmd_set, UT_TESTF_SCAN_PDATA | UT_TESTF_SCAN_FDT);
+DM_TEST(dm_test_acpi_cmd_set, UTF_SCAN_PDATA | UTF_SCAN_FDT | UTF_CONSOLE);
/**
* dm_test_write_test_table() - create test ACPI table
diff --git a/test/dm/acpi_dp.c b/test/dm/acpi_dp.c
index 87bd8ae..eaeda2b 100644
--- a/test/dm/acpi_dp.c
+++ b/test/dm/acpi_dp.c
@@ -488,4 +488,4 @@
return 0;
}
-DM_TEST(dm_test_acpi_dp_copy, UT_TESTF_SCAN_PDATA | UT_TESTF_SCAN_FDT);
+DM_TEST(dm_test_acpi_dp_copy, UTF_SCAN_PDATA | UTF_SCAN_FDT);
diff --git a/test/dm/acpigen.c b/test/dm/acpigen.c
index 7113219..3e912fa 100644
--- a/test/dm/acpigen.c
+++ b/test/dm/acpigen.c
@@ -167,7 +167,7 @@
return 0;
}
-DM_TEST(dm_test_acpi_interrupt, UT_TESTF_SCAN_PDATA | UT_TESTF_SCAN_FDT);
+DM_TEST(dm_test_acpi_interrupt, UTF_SCAN_PDATA | UTF_SCAN_FDT);
/* Test emitting a GPIO descriptor */
static int dm_test_acpi_gpio(struct unit_test_state *uts)
@@ -212,7 +212,7 @@
return 0;
}
-DM_TEST(dm_test_acpi_gpio, UT_TESTF_SCAN_PDATA | UT_TESTF_SCAN_FDT);
+DM_TEST(dm_test_acpi_gpio, UTF_SCAN_PDATA | UTF_SCAN_FDT);
/* Test emitting a GPIO descriptor with an interrupt */
static int dm_test_acpi_gpio_irq(struct unit_test_state *uts)
@@ -257,7 +257,7 @@
return 0;
}
-DM_TEST(dm_test_acpi_gpio_irq, UT_TESTF_SCAN_PDATA | UT_TESTF_SCAN_FDT);
+DM_TEST(dm_test_acpi_gpio_irq, UTF_SCAN_PDATA | UTF_SCAN_FDT);
/* Test emitting either a GPIO or interrupt descriptor */
static int dm_test_acpi_interrupt_or_gpio(struct unit_test_state *uts)
@@ -296,8 +296,7 @@
return 0;
}
-DM_TEST(dm_test_acpi_interrupt_or_gpio,
- UT_TESTF_SCAN_PDATA | UT_TESTF_SCAN_FDT);
+DM_TEST(dm_test_acpi_interrupt_or_gpio, UTF_SCAN_PDATA | UTF_SCAN_FDT);
/* Test emitting an I2C descriptor */
static int dm_test_acpi_i2c(struct unit_test_state *uts)
@@ -329,7 +328,7 @@
return 0;
}
-DM_TEST(dm_test_acpi_i2c, UT_TESTF_SCAN_PDATA | UT_TESTF_SCAN_FDT);
+DM_TEST(dm_test_acpi_i2c, UTF_SCAN_PDATA | UTF_SCAN_FDT);
/* Test emitting a SPI descriptor */
static int dm_test_acpi_spi(struct unit_test_state *uts)
@@ -365,7 +364,7 @@
return 0;
}
-DM_TEST(dm_test_acpi_spi, UT_TESTF_SCAN_PDATA | UT_TESTF_SCAN_FDT);
+DM_TEST(dm_test_acpi_spi, UTF_SCAN_PDATA | UTF_SCAN_FDT);
/* Test emitting a length */
static int dm_test_acpi_len(struct unit_test_state *uts)
@@ -806,7 +805,7 @@
return 0;
}
-DM_TEST(dm_test_acpi_gpio_toggle, UT_TESTF_SCAN_PDATA | UT_TESTF_SCAN_FDT);
+DM_TEST(dm_test_acpi_gpio_toggle, UTF_SCAN_PDATA | UTF_SCAN_FDT);
/* Test writing ACPI code to output power-sequence info */
static int dm_test_acpi_power_seq(struct unit_test_state *uts)
@@ -873,7 +872,7 @@
return 0;
}
-DM_TEST(dm_test_acpi_power_seq, UT_TESTF_SCAN_PDATA | UT_TESTF_SCAN_FDT);
+DM_TEST(dm_test_acpi_power_seq, UTF_SCAN_PDATA | UTF_SCAN_FDT);
/* Test writing values */
static int dm_test_acpi_write_values(struct unit_test_state *uts)
@@ -947,7 +946,7 @@
return 0;
}
-DM_TEST(dm_test_acpi_scope, UT_TESTF_SCAN_PDATA | UT_TESTF_SCAN_FDT);
+DM_TEST(dm_test_acpi_scope, UTF_SCAN_PDATA | UTF_SCAN_FDT);
/* Test writing a resource template */
static int dm_test_acpi_resource_template(struct unit_test_state *uts)
diff --git a/test/dm/adc.c b/test/dm/adc.c
index a26a677..e27302b 100644
--- a/test/dm/adc.c
+++ b/test/dm/adc.c
@@ -32,7 +32,7 @@
return 0;
}
-DM_TEST(dm_test_adc_bind, UT_TESTF_SCAN_FDT);
+DM_TEST(dm_test_adc_bind, UTF_SCAN_FDT);
static int dm_test_adc_wrong_channel_selection(struct unit_test_state *uts)
{
@@ -43,7 +43,7 @@
return 0;
}
-DM_TEST(dm_test_adc_wrong_channel_selection, UT_TESTF_SCAN_FDT);
+DM_TEST(dm_test_adc_wrong_channel_selection, UTF_SCAN_FDT);
static int dm_test_adc_supply(struct unit_test_state *uts)
{
@@ -79,7 +79,7 @@
return 0;
}
-DM_TEST(dm_test_adc_supply, UT_TESTF_SCAN_FDT);
+DM_TEST(dm_test_adc_supply, UTF_SCAN_FDT);
struct adc_channel adc_channel_test_data[] = {
{ 0, SANDBOX_ADC_CHANNEL0_DATA },
@@ -104,7 +104,7 @@
return 0;
}
-DM_TEST(dm_test_adc_single_channel_conversion, UT_TESTF_SCAN_FDT);
+DM_TEST(dm_test_adc_single_channel_conversion, UTF_SCAN_FDT);
static int dm_test_adc_multi_channel_conversion(struct unit_test_state *uts)
{
@@ -127,7 +127,7 @@
return 0;
}
-DM_TEST(dm_test_adc_multi_channel_conversion, UT_TESTF_SCAN_FDT);
+DM_TEST(dm_test_adc_multi_channel_conversion, UTF_SCAN_FDT);
static int dm_test_adc_single_channel_shot(struct unit_test_state *uts)
{
@@ -143,7 +143,7 @@
return 0;
}
-DM_TEST(dm_test_adc_single_channel_shot, UT_TESTF_SCAN_FDT);
+DM_TEST(dm_test_adc_single_channel_shot, UTF_SCAN_FDT);
static int dm_test_adc_multi_channel_shot(struct unit_test_state *uts)
{
@@ -163,7 +163,7 @@
return 0;
}
-DM_TEST(dm_test_adc_multi_channel_shot, UT_TESTF_SCAN_FDT);
+DM_TEST(dm_test_adc_multi_channel_shot, UTF_SCAN_FDT);
static const int dm_test_adc_uV_data[SANDBOX_ADC_CHANNELS] = {
((u64)SANDBOX_ADC_CHANNEL0_DATA * SANDBOX_BUCK2_INITIAL_EXPECTED_UV) /
@@ -194,4 +194,4 @@
return 0;
}
-DM_TEST(dm_test_adc_raw_to_uV, UT_TESTF_SCAN_FDT);
+DM_TEST(dm_test_adc_raw_to_uV, UTF_SCAN_FDT);
diff --git a/test/dm/audio.c b/test/dm/audio.c
index 3d1d821..f4d3346 100644
--- a/test/dm/audio.c
+++ b/test/dm/audio.c
@@ -31,4 +31,4 @@
return 0;
}
-DM_TEST(dm_test_audio, UT_TESTF_SCAN_PDATA | UT_TESTF_SCAN_FDT);
+DM_TEST(dm_test_audio, UTF_SCAN_PDATA | UTF_SCAN_FDT);
diff --git a/test/dm/axi.c b/test/dm/axi.c
index 0900a9b..45c46a1 100644
--- a/test/dm/axi.c
+++ b/test/dm/axi.c
@@ -21,8 +21,7 @@
return 0;
}
-
-DM_TEST(dm_test_axi_base, UT_TESTF_SCAN_PDATA | UT_TESTF_SCAN_FDT);
+DM_TEST(dm_test_axi_base, UTF_SCAN_PDATA | UTF_SCAN_FDT);
/* Test that sandbox PCI bus numbering works correctly */
static int dm_test_axi_busnum(struct unit_test_state *uts)
@@ -33,8 +32,7 @@
return 0;
}
-
-DM_TEST(dm_test_axi_busnum, UT_TESTF_SCAN_PDATA | UT_TESTF_SCAN_FDT);
+DM_TEST(dm_test_axi_busnum, UTF_SCAN_PDATA | UTF_SCAN_FDT);
/* Test that we can use the store device correctly */
static int dm_test_axi_store(struct unit_test_state *uts)
@@ -74,5 +72,4 @@
return 0;
}
-
-DM_TEST(dm_test_axi_store, UT_TESTF_SCAN_PDATA | UT_TESTF_SCAN_FDT);
+DM_TEST(dm_test_axi_store, UTF_SCAN_PDATA | UTF_SCAN_FDT);
diff --git a/test/dm/blk.c b/test/dm/blk.c
index d03aec3..aa5cbc6 100644
--- a/test/dm/blk.c
+++ b/test/dm/blk.c
@@ -43,7 +43,7 @@
return 0;
}
-DM_TEST(dm_test_blk_base, UT_TESTF_SCAN_PDATA | UT_TESTF_SCAN_FDT);
+DM_TEST(dm_test_blk_base, UTF_SCAN_PDATA | UTF_SCAN_FDT);
static int count_blk_devices(void)
{
@@ -92,7 +92,7 @@
return 0;
}
-DM_TEST(dm_test_blk_usb, UT_TESTF_SCAN_PDATA | UT_TESTF_SCAN_FDT);
+DM_TEST(dm_test_blk_usb, UTF_SCAN_PDATA | UTF_SCAN_FDT);
/* Test that we can find block devices without probing them */
static int dm_test_blk_find(struct unit_test_state *uts)
@@ -114,7 +114,7 @@
return 0;
}
-DM_TEST(dm_test_blk_find, UT_TESTF_SCAN_PDATA | UT_TESTF_SCAN_FDT);
+DM_TEST(dm_test_blk_find, UTF_SCAN_PDATA | UTF_SCAN_FDT);
/* Test that block device numbering works as expected */
static int dm_test_blk_devnum(struct unit_test_state *uts)
@@ -149,7 +149,7 @@
return 0;
}
-DM_TEST(dm_test_blk_devnum, UT_TESTF_SCAN_PDATA | UT_TESTF_SCAN_FDT);
+DM_TEST(dm_test_blk_devnum, UTF_SCAN_PDATA | UTF_SCAN_FDT);
/* Test that we can get a block from its parent */
static int dm_test_blk_get_from_parent(struct unit_test_state *uts)
@@ -167,7 +167,7 @@
return 0;
}
-DM_TEST(dm_test_blk_get_from_parent, UT_TESTF_SCAN_PDATA | UT_TESTF_SCAN_FDT);
+DM_TEST(dm_test_blk_get_from_parent, UTF_SCAN_PDATA | UTF_SCAN_FDT);
/* Test iteration through block devices */
static int dm_test_blk_iter(struct unit_test_state *uts)
@@ -222,7 +222,7 @@
return 0;
}
-DM_TEST(dm_test_blk_iter, UT_TESTF_SCAN_PDATA | UT_TESTF_SCAN_FDT);
+DM_TEST(dm_test_blk_iter, UTF_SCAN_PDATA | UTF_SCAN_FDT);
/* Test finding fixed/removable block devices */
static int dm_test_blk_flags(struct unit_test_state *uts)
@@ -287,7 +287,7 @@
return 0;
}
-DM_TEST(dm_test_blk_flags, UT_TESTF_SCAN_PDATA | UT_TESTF_SCAN_FDT);
+DM_TEST(dm_test_blk_flags, UTF_SCAN_PDATA | UTF_SCAN_FDT);
/* Test blk_foreach() and friend */
static int dm_test_blk_foreach(struct unit_test_state *uts)
@@ -333,4 +333,4 @@
return 0;
}
-DM_TEST(dm_test_blk_foreach, UT_TESTF_SCAN_PDATA | UT_TESTF_SCAN_FDT);
+DM_TEST(dm_test_blk_foreach, UTF_SCAN_PDATA | UTF_SCAN_FDT);
diff --git a/test/dm/blkmap.c b/test/dm/blkmap.c
index 7581e62..a6a0b4d 100644
--- a/test/dm/blkmap.c
+++ b/test/dm/blkmap.c
@@ -165,8 +165,6 @@
ulong loadaddr = env_get_hex("loadaddr", 0);
struct udevice *dev;
- console_record_reset();
-
ut_assertok(run_command("blkmap info", 0));
ut_assert_console_end();
@@ -197,4 +195,4 @@
ut_assert_console_end();
return 0;
}
-DM_TEST(dm_test_cmd_blkmap, 0);
+DM_TEST(dm_test_cmd_blkmap, UTF_CONSOLE);
diff --git a/test/dm/bootcount.c b/test/dm/bootcount.c
index 9cfc7d4..f66927a 100644
--- a/test/dm/bootcount.c
+++ b/test/dm/bootcount.c
@@ -35,8 +35,7 @@
return 0;
}
-
-DM_TEST(dm_test_bootcount_rtc, UT_TESTF_SCAN_PDATA | UT_TESTF_SCAN_FDT);
+DM_TEST(dm_test_bootcount_rtc, UTF_SCAN_PDATA | UTF_SCAN_FDT);
static int dm_test_bootcount_syscon_four_bytes(struct unit_test_state *uts)
{
@@ -55,9 +54,8 @@
return 0;
}
-
DM_TEST(dm_test_bootcount_syscon_four_bytes,
- UT_TESTF_SCAN_PDATA | UT_TESTF_SCAN_FDT);
+ UTF_SCAN_PDATA | UTF_SCAN_FDT);
static int dm_test_bootcount_syscon_two_bytes(struct unit_test_state *uts)
{
@@ -76,6 +74,4 @@
return 0;
}
-
-DM_TEST(dm_test_bootcount_syscon_two_bytes,
- UT_TESTF_SCAN_PDATA | UT_TESTF_SCAN_FDT);
+DM_TEST(dm_test_bootcount_syscon_two_bytes, UTF_SCAN_PDATA | UTF_SCAN_FDT);
diff --git a/test/dm/bus.c b/test/dm/bus.c
index 95326f2..166a842 100644
--- a/test/dm/bus.c
+++ b/test/dm/bus.c
@@ -41,7 +41,7 @@
return 0;
}
-DM_TEST(dm_test_bus_children, UT_TESTF_SCAN_PDATA | UT_TESTF_SCAN_FDT);
+DM_TEST(dm_test_bus_children, UTF_SCAN_PDATA | UTF_SCAN_FDT);
/* Test our functions for accessing children */
static int dm_test_bus_children_funcs(struct unit_test_state *uts)
@@ -81,7 +81,7 @@
return 0;
}
-DM_TEST(dm_test_bus_children_funcs, UT_TESTF_SCAN_PDATA | UT_TESTF_SCAN_FDT);
+DM_TEST(dm_test_bus_children_funcs, UTF_SCAN_PDATA | UTF_SCAN_FDT);
static int dm_test_bus_children_of_offset(struct unit_test_state *uts)
{
@@ -105,7 +105,7 @@
return 0;
}
DM_TEST(dm_test_bus_children_of_offset,
- UT_TESTF_SCAN_PDATA | UT_TESTF_SCAN_FDT | UT_TESTF_FLAT_TREE);
+ UTF_SCAN_PDATA | UTF_SCAN_FDT | UTF_FLAT_TREE);
/* Test that we can iterate through children */
static int dm_test_bus_children_iterators(struct unit_test_state *uts)
@@ -136,7 +136,7 @@
return 0;
}
DM_TEST(dm_test_bus_children_iterators,
- UT_TESTF_SCAN_PDATA | UT_TESTF_SCAN_FDT);
+ UTF_SCAN_PDATA | UTF_SCAN_FDT);
/* Test that the bus can store data about each child */
static int test_bus_parent_data(struct unit_test_state *uts)
@@ -203,7 +203,7 @@
{
return test_bus_parent_data(uts);
}
-DM_TEST(dm_test_bus_parent_data, UT_TESTF_SCAN_PDATA | UT_TESTF_SCAN_FDT);
+DM_TEST(dm_test_bus_parent_data, UTF_SCAN_PDATA | UTF_SCAN_FDT);
/* As above but the size is controlled by the uclass */
static int dm_test_bus_parent_data_uclass(struct unit_test_state *uts)
@@ -233,7 +233,7 @@
return 0;
}
DM_TEST(dm_test_bus_parent_data_uclass,
- UT_TESTF_SCAN_PDATA | UT_TESTF_SCAN_FDT);
+ UTF_SCAN_PDATA | UTF_SCAN_FDT);
/* Test that the bus ops are called when a child is probed/removed */
static int dm_test_bus_parent_ops(struct unit_test_state *uts)
@@ -270,7 +270,7 @@
return 0;
}
-DM_TEST(dm_test_bus_parent_ops, UT_TESTF_SCAN_PDATA | UT_TESTF_SCAN_FDT);
+DM_TEST(dm_test_bus_parent_ops, UTF_SCAN_PDATA | UTF_SCAN_FDT);
static int test_bus_parent_plat(struct unit_test_state *uts)
{
@@ -345,7 +345,7 @@
{
return test_bus_parent_plat(uts);
}
-DM_TEST(dm_test_bus_parent_plat, UT_TESTF_SCAN_PDATA | UT_TESTF_SCAN_FDT);
+DM_TEST(dm_test_bus_parent_plat, UTF_SCAN_PDATA | UTF_SCAN_FDT);
/* As above but the size is controlled by the uclass */
static int dm_test_bus_parent_plat_uclass(struct unit_test_state *uts)
@@ -374,7 +374,7 @@
return 0;
}
DM_TEST(dm_test_bus_parent_plat_uclass,
- UT_TESTF_SCAN_PDATA | UT_TESTF_SCAN_FDT);
+ UTF_SCAN_PDATA | UTF_SCAN_FDT);
/* Test that the child post_bind method is called */
static int dm_test_bus_child_post_bind(struct unit_test_state *uts)
@@ -395,7 +395,7 @@
return 0;
}
-DM_TEST(dm_test_bus_child_post_bind, UT_TESTF_SCAN_PDATA | UT_TESTF_SCAN_FDT);
+DM_TEST(dm_test_bus_child_post_bind, UTF_SCAN_PDATA | UTF_SCAN_FDT);
/* Test that the child post_bind method is called */
static int dm_test_bus_child_post_bind_uclass(struct unit_test_state *uts)
@@ -417,7 +417,7 @@
return 0;
}
DM_TEST(dm_test_bus_child_post_bind_uclass,
- UT_TESTF_SCAN_PDATA | UT_TESTF_SCAN_FDT);
+ UTF_SCAN_PDATA | UTF_SCAN_FDT);
/*
* Test that the bus' uclass' child_pre_probe() is called before the
@@ -451,7 +451,7 @@
return 0;
}
DM_TEST(dm_test_bus_child_pre_probe_uclass,
- UT_TESTF_SCAN_PDATA | UT_TESTF_SCAN_FDT);
+ UTF_SCAN_PDATA | UTF_SCAN_FDT);
/*
* Test that the bus' uclass' child_post_probe() is called after the
@@ -484,4 +484,4 @@
return 0;
}
DM_TEST(dm_test_bus_child_post_probe_uclass,
- UT_TESTF_SCAN_PDATA | UT_TESTF_SCAN_FDT);
+ UTF_SCAN_PDATA | UTF_SCAN_FDT);
diff --git a/test/dm/button.c b/test/dm/button.c
index 9157ec9..3612f30 100644
--- a/test/dm/button.c
+++ b/test/dm/button.c
@@ -37,7 +37,7 @@
return 0;
}
-DM_TEST(dm_test_button_base, UT_TESTF_SCAN_PDATA | UT_TESTF_SCAN_FDT);
+DM_TEST(dm_test_button_base, UTF_SCAN_PDATA | UTF_SCAN_FDT);
/* Test of the button uclass using the button_gpio driver */
static int dm_test_button_gpio(struct unit_test_state *uts)
@@ -62,7 +62,7 @@
return 0;
}
-DM_TEST(dm_test_button_gpio, UT_TESTF_SCAN_PDATA | UT_TESTF_SCAN_FDT);
+DM_TEST(dm_test_button_gpio, UTF_SCAN_PDATA | UTF_SCAN_FDT);
/* Test obtaining a BUTTON by label */
static int dm_test_button_label(struct unit_test_state *uts)
@@ -83,7 +83,7 @@
return 0;
}
-DM_TEST(dm_test_button_label, UT_TESTF_SCAN_PDATA | UT_TESTF_SCAN_FDT);
+DM_TEST(dm_test_button_label, UTF_SCAN_PDATA | UTF_SCAN_FDT);
/* Test button has linux,code */
static int dm_test_button_linux_code(struct unit_test_state *uts)
@@ -95,7 +95,7 @@
return 0;
}
-DM_TEST(dm_test_button_linux_code, UT_TESTF_SCAN_PDATA | UT_TESTF_SCAN_FDT);
+DM_TEST(dm_test_button_linux_code, UTF_SCAN_PDATA | UTF_SCAN_FDT);
/* Test adc-keys driver */
static int dm_test_button_keys_adc(struct unit_test_state *uts)
@@ -129,7 +129,7 @@
return 0;
}
-DM_TEST(dm_test_button_keys_adc, UT_TESTF_SCAN_PDATA | UT_TESTF_SCAN_FDT);
+DM_TEST(dm_test_button_keys_adc, UTF_SCAN_PDATA | UTF_SCAN_FDT);
/* Test of the button uclass using the button_gpio driver */
static int dm_test_button_cmd(struct unit_test_state *uts)
@@ -225,4 +225,4 @@
return 0;
}
-DM_TEST(dm_test_button_cmd, UT_TESTF_SCAN_PDATA | UT_TESTF_SCAN_FDT);
+DM_TEST(dm_test_button_cmd, UTF_SCAN_PDATA | UTF_SCAN_FDT);
diff --git a/test/dm/cache.c b/test/dm/cache.c
index d2f3bfe..e03e029 100644
--- a/test/dm/cache.c
+++ b/test/dm/cache.c
@@ -18,4 +18,4 @@
return 0;
}
-DM_TEST(dm_test_reset, UT_TESTF_SCAN_FDT);
+DM_TEST(dm_test_reset, UTF_SCAN_FDT);
diff --git a/test/dm/clk.c b/test/dm/clk.c
index a966471..790968e 100644
--- a/test/dm/clk.c
+++ b/test/dm/clk.c
@@ -46,8 +46,7 @@
return 0;
}
-
-DM_TEST(dm_test_clk_base, UT_TESTF_SCAN_FDT);
+DM_TEST(dm_test_clk_base, UTF_SCAN_FDT);
static int dm_test_clk(struct unit_test_state *uts)
{
@@ -187,7 +186,7 @@
ut_assertok(device_remove(dev_test, DM_REMOVE_NORMAL));
return 0;
}
-DM_TEST(dm_test_clk, UT_TESTF_SCAN_FDT);
+DM_TEST(dm_test_clk, UTF_SCAN_FDT);
static int dm_test_clk_bulk(struct unit_test_state *uts)
{
@@ -225,4 +224,4 @@
return 0;
}
-DM_TEST(dm_test_clk_bulk, UT_TESTF_SCAN_FDT);
+DM_TEST(dm_test_clk_bulk, UTF_SCAN_FDT);
diff --git a/test/dm/clk_ccf.c b/test/dm/clk_ccf.c
index 15fba31..ac56f17 100644
--- a/test/dm/clk_ccf.c
+++ b/test/dm/clk_ccf.c
@@ -208,5 +208,4 @@
return 1;
}
-
-DM_TEST(dm_test_clk_ccf, UT_TESTF_SCAN_FDT);
+DM_TEST(dm_test_clk_ccf, UTF_SCAN_FDT);
diff --git a/test/dm/core.c b/test/dm/core.c
index 5bc5e8e..e0c5b9e 100644
--- a/test/dm/core.c
+++ b/test/dm/core.c
@@ -175,7 +175,7 @@
return 0;
}
-DM_TEST(dm_test_autobind_uclass_pdata_alloc, UT_TESTF_SCAN_PDATA);
+DM_TEST(dm_test_autobind_uclass_pdata_alloc, UTF_SCAN_PDATA);
/* compare node names ignoring the unit address */
static int dm_test_compare_node_name(struct unit_test_state *uts)
@@ -188,8 +188,7 @@
return 0;
}
-
-DM_TEST(dm_test_compare_node_name, UT_TESTF_SCAN_PDATA);
+DM_TEST(dm_test_compare_node_name, UTF_SCAN_PDATA);
/* Test that binding with uclass plat setting occurs correctly */
static int dm_test_autobind_uclass_pdata_valid(struct unit_test_state *uts)
@@ -215,7 +214,7 @@
return 0;
}
-DM_TEST(dm_test_autobind_uclass_pdata_valid, UT_TESTF_SCAN_PDATA);
+DM_TEST(dm_test_autobind_uclass_pdata_valid, UTF_SCAN_PDATA);
/* Test that autoprobe finds all the expected devices */
static int dm_test_autoprobe(struct unit_test_state *uts)
@@ -282,7 +281,7 @@
return 0;
}
-DM_TEST(dm_test_autoprobe, UT_TESTF_SCAN_PDATA);
+DM_TEST(dm_test_autoprobe, UTF_SCAN_PDATA);
/* Check that we see the correct plat in each device */
static int dm_test_plat(struct unit_test_state *uts)
@@ -300,7 +299,7 @@
return 0;
}
-DM_TEST(dm_test_plat, UT_TESTF_SCAN_PDATA);
+DM_TEST(dm_test_plat, UTF_SCAN_PDATA);
/* Test that we can bind, probe, remove, unbind a driver */
static int dm_test_lifecycle(struct unit_test_state *uts)
@@ -369,7 +368,7 @@
return 0;
}
-DM_TEST(dm_test_lifecycle, UT_TESTF_SCAN_PDATA | UT_TESTF_PROBE_TEST);
+DM_TEST(dm_test_lifecycle, UTF_SCAN_PDATA | UTF_PROBE_TEST);
/* Test that we can bind/unbind and the lists update correctly */
static int dm_test_ordering(struct unit_test_state *uts)
@@ -424,7 +423,7 @@
return 0;
}
-DM_TEST(dm_test_ordering, UT_TESTF_SCAN_PDATA);
+DM_TEST(dm_test_ordering, UTF_SCAN_PDATA);
/* Check that we can perform operations on a device (do a ping) */
int dm_check_operations(struct unit_test_state *uts, struct udevice *dev,
@@ -482,7 +481,7 @@
return 0;
}
-DM_TEST(dm_test_operations, UT_TESTF_SCAN_PDATA);
+DM_TEST(dm_test_operations, UTF_SCAN_PDATA);
/* Remove all drivers and check that things work */
static int dm_test_remove(struct unit_test_state *uts)
@@ -504,7 +503,7 @@
return 0;
}
-DM_TEST(dm_test_remove, UT_TESTF_SCAN_PDATA | UT_TESTF_PROBE_TEST);
+DM_TEST(dm_test_remove, UTF_SCAN_PDATA | UTF_PROBE_TEST);
/* Remove and recreate everything, check for memory leaks */
static int dm_test_leak(struct unit_test_state *uts)
@@ -1033,7 +1032,7 @@
return 0;
}
-DM_TEST(dm_test_uclass_devices_find, UT_TESTF_SCAN_PDATA);
+DM_TEST(dm_test_uclass_devices_find, UTF_SCAN_PDATA);
static int dm_test_uclass_devices_find_by_name(struct unit_test_state *uts)
{
@@ -1070,7 +1069,7 @@
return 0;
}
-DM_TEST(dm_test_uclass_devices_find_by_name, UT_TESTF_SCAN_FDT);
+DM_TEST(dm_test_uclass_devices_find_by_name, UTF_SCAN_FDT);
static int dm_test_uclass_devices_get(struct unit_test_state *uts)
{
@@ -1086,7 +1085,7 @@
return 0;
}
-DM_TEST(dm_test_uclass_devices_get, UT_TESTF_SCAN_PDATA);
+DM_TEST(dm_test_uclass_devices_get, UTF_SCAN_PDATA);
static int dm_test_uclass_devices_get_by_name(struct unit_test_state *uts)
{
@@ -1129,7 +1128,7 @@
return 0;
}
-DM_TEST(dm_test_uclass_devices_get_by_name, UT_TESTF_SCAN_FDT);
+DM_TEST(dm_test_uclass_devices_get_by_name, UTF_SCAN_FDT);
static int dm_test_device_get_uclass_id(struct unit_test_state *uts)
{
@@ -1140,7 +1139,7 @@
return 0;
}
-DM_TEST(dm_test_device_get_uclass_id, UT_TESTF_SCAN_PDATA);
+DM_TEST(dm_test_device_get_uclass_id, UTF_SCAN_PDATA);
static int dm_test_uclass_names(struct unit_test_state *uts)
{
@@ -1151,7 +1150,7 @@
return 0;
}
-DM_TEST(dm_test_uclass_names, UT_TESTF_SCAN_PDATA);
+DM_TEST(dm_test_uclass_names, UTF_SCAN_PDATA);
static int dm_test_inactive_child(struct unit_test_state *uts)
{
@@ -1181,7 +1180,7 @@
return 0;
}
-DM_TEST(dm_test_inactive_child, UT_TESTF_SCAN_PDATA);
+DM_TEST(dm_test_inactive_child, UTF_SCAN_PDATA);
/* Make sure all bound devices have a sequence number */
static int dm_test_all_have_seq(struct unit_test_state *uts)
@@ -1200,7 +1199,7 @@
return 0;
}
-DM_TEST(dm_test_all_have_seq, UT_TESTF_SCAN_PDATA);
+DM_TEST(dm_test_all_have_seq, UTF_SCAN_PDATA);
#if CONFIG_IS_ENABLED(DM_DMA)
static int dm_test_dma_offset(struct unit_test_state *uts)
@@ -1231,7 +1230,7 @@
return 0;
}
-DM_TEST(dm_test_dma_offset, UT_TESTF_SCAN_PDATA | UT_TESTF_SCAN_FDT);
+DM_TEST(dm_test_dma_offset, UTF_SCAN_PDATA | UTF_SCAN_FDT);
#endif
/* Test dm_get_stats() */
@@ -1245,7 +1244,7 @@
return 0;
}
-DM_TEST(dm_test_get_stats, UT_TESTF_SCAN_FDT);
+DM_TEST(dm_test_get_stats, UTF_SCAN_FDT);
/* Test uclass_find_device_by_name() */
static int dm_test_uclass_find_device(struct unit_test_state *uts)
@@ -1260,7 +1259,7 @@
return 0;
}
-DM_TEST(dm_test_uclass_find_device, UT_TESTF_SCAN_FDT);
+DM_TEST(dm_test_uclass_find_device, UTF_SCAN_FDT);
/* Test getting information about tags attached to devices */
static int dm_test_dev_get_attach(struct unit_test_state *uts)
@@ -1288,7 +1287,7 @@
return 0;
}
-DM_TEST(dm_test_dev_get_attach, UT_TESTF_SCAN_FDT);
+DM_TEST(dm_test_dev_get_attach, UTF_SCAN_FDT);
/* Test getting information about tags attached to bus devices */
static int dm_test_dev_get_attach_bus(struct unit_test_state *uts)
@@ -1340,7 +1339,7 @@
return 0;
}
-DM_TEST(dm_test_dev_get_attach_bus, UT_TESTF_SCAN_FDT);
+DM_TEST(dm_test_dev_get_attach_bus, UTF_SCAN_FDT);
/* Test getting information about tags attached to bus devices */
static int dm_test_dev_get_mem(struct unit_test_state *uts)
@@ -1351,4 +1350,4 @@
return 0;
}
-DM_TEST(dm_test_dev_get_mem, UT_TESTF_SCAN_FDT);
+DM_TEST(dm_test_dev_get_mem, UTF_SCAN_FDT);
diff --git a/test/dm/cpu.c b/test/dm/cpu.c
index 8af2531..9b2f90e 100644
--- a/test/dm/cpu.c
+++ b/test/dm/cpu.c
@@ -47,5 +47,4 @@
return 0;
}
-
-DM_TEST(dm_test_cpu, UT_TESTF_SCAN_FDT);
+DM_TEST(dm_test_cpu, UTF_SCAN_FDT);
diff --git a/test/dm/cros_ec.c b/test/dm/cros_ec.c
index ac0055f..089f667 100644
--- a/test/dm/cros_ec.c
+++ b/test/dm/cros_ec.c
@@ -28,7 +28,7 @@
return 0;
}
-DM_TEST(dm_test_cros_ec_hello, UT_TESTF_SCAN_FDT);
+DM_TEST(dm_test_cros_ec_hello, UTF_SCAN_FDT);
static int dm_test_cros_ec_sku_id(struct unit_test_state *uts)
{
@@ -38,14 +38,13 @@
ut_asserteq(1234, cros_ec_get_sku_id(dev));
/* try the command */
- console_record_reset();
ut_assertok(run_command("crosec sku", 0));
ut_assert_nextline("1234");
ut_assert_console_end();
return 0;
}
-DM_TEST(dm_test_cros_ec_sku_id, UT_TESTF_SCAN_FDT);
+DM_TEST(dm_test_cros_ec_sku_id, UTF_SCAN_FDT | UTF_CONSOLE);
static int dm_test_cros_ec_features(struct unit_test_state *uts)
{
@@ -64,7 +63,6 @@
ut_asserteq(true, cros_ec_check_feature(dev, EC_FEATURE_ISH));
/* try the command */
- console_record_reset();
ut_assertok(run_command("crosec features", 0));
ut_assert_nextline("flash");
ut_assert_nextline("i2c");
@@ -75,7 +73,7 @@
return 0;
}
-DM_TEST(dm_test_cros_ec_features, UT_TESTF_SCAN_FDT);
+DM_TEST(dm_test_cros_ec_features, UTF_SCAN_FDT | UTF_CONSOLE);
static int dm_test_cros_ec_switches(struct unit_test_state *uts)
{
@@ -85,7 +83,6 @@
ut_asserteq(0, cros_ec_get_switches(dev));
/* try the command */
- console_record_reset();
ut_assertok(run_command("crosec switches", 0));
ut_assert_console_end();
@@ -94,14 +91,13 @@
ut_asserteq(EC_SWITCH_LID_OPEN, cros_ec_get_switches(dev));
/* try the command */
- console_record_reset();
ut_assertok(run_command("crosec switches", 0));
ut_assert_nextline("lid open");
ut_assert_console_end();
return 0;
}
-DM_TEST(dm_test_cros_ec_switches, UT_TESTF_SCAN_FDT);
+DM_TEST(dm_test_cros_ec_switches, UTF_SCAN_FDT | UTF_CONSOLE);
static int dm_test_cros_ec_events(struct unit_test_state *uts)
{
@@ -113,7 +109,6 @@
ut_asserteq(0, events);
/* try the command */
- console_record_reset();
ut_assertok(run_command("crosec events", 0));
ut_assert_nextline("00000000");
ut_assert_console_end();
@@ -124,7 +119,6 @@
ut_asserteq(EC_HOST_EVENT_MASK(EC_HOST_EVENT_LID_OPEN), events);
/* try the command */
- console_record_reset();
ut_assertok(run_command("crosec events", 0));
ut_assert_nextline("00000002");
ut_assert_nextline("lid_open");
@@ -138,7 +132,7 @@
return 0;
}
-DM_TEST(dm_test_cros_ec_events, UT_TESTF_SCAN_FDT);
+DM_TEST(dm_test_cros_ec_events, UTF_SCAN_FDT | UTF_CONSOLE);
static int dm_test_cros_ec_vstore(struct unit_test_state *uts)
{
@@ -174,4 +168,4 @@
return 0;
}
-DM_TEST(dm_test_cros_ec_vstore, UT_TESTF_SCAN_FDT);
+DM_TEST(dm_test_cros_ec_vstore, UTF_SCAN_FDT);
diff --git a/test/dm/cros_ec_pwm.c b/test/dm/cros_ec_pwm.c
index f68ee6f..0b6ca8b 100644
--- a/test/dm/cros_ec_pwm.c
+++ b/test/dm/cros_ec_pwm.c
@@ -56,4 +56,4 @@
return 0;
}
-DM_TEST(dm_test_cros_ec_pwm, UT_TESTF_SCAN_PDATA | UT_TESTF_SCAN_FDT);
+DM_TEST(dm_test_cros_ec_pwm, UTF_SCAN_PDATA | UTF_SCAN_FDT);
diff --git a/test/dm/devres.c b/test/dm/devres.c
index 7a3a669..efc5c72 100644
--- a/test/dm/devres.c
+++ b/test/dm/devres.c
@@ -39,7 +39,7 @@
return 0;
}
-DM_TEST(dm_test_devres_alloc, UT_TESTF_SCAN_PDATA);
+DM_TEST(dm_test_devres_alloc, UTF_SCAN_PDATA);
/* Test devm_kfree() can be used to free memory too */
static int dm_test_devres_free(struct unit_test_state *uts)
@@ -67,7 +67,7 @@
return 0;
}
-DM_TEST(dm_test_devres_free, UT_TESTF_SCAN_PDATA);
+DM_TEST(dm_test_devres_free, UTF_SCAN_PDATA);
/* Test that kzalloc() returns memory that is zeroed */
static int dm_test_devres_kzalloc(struct unit_test_state *uts)
@@ -86,7 +86,7 @@
return 0;
}
-DM_TEST(dm_test_devres_kzalloc, UT_TESTF_SCAN_PDATA);
+DM_TEST(dm_test_devres_kzalloc, UTF_SCAN_PDATA);
/* Test that devm_kmalloc_array() allocates an array that can be set */
static int dm_test_devres_kmalloc_array(struct unit_test_state *uts)
@@ -109,7 +109,7 @@
return 0;
}
-DM_TEST(dm_test_devres_kmalloc_array, UT_TESTF_SCAN_PDATA);
+DM_TEST(dm_test_devres_kmalloc_array, UTF_SCAN_PDATA);
/* Test that devm_kcalloc() allocates a zeroed array */
static int dm_test_devres_kcalloc(struct unit_test_state *uts)
@@ -138,7 +138,7 @@
return 0;
}
-DM_TEST(dm_test_devres_kcalloc, UT_TESTF_SCAN_PDATA);
+DM_TEST(dm_test_devres_kcalloc, UTF_SCAN_PDATA);
/* Test devres releases resources automatically as expected */
static int dm_test_devres_phase(struct unit_test_state *uts)
@@ -181,4 +181,4 @@
return 0;
}
-DM_TEST(dm_test_devres_phase, UT_TESTF_SCAN_PDATA | UT_TESTF_SCAN_FDT);
+DM_TEST(dm_test_devres_phase, UTF_SCAN_PDATA | UTF_SCAN_FDT);
diff --git a/test/dm/dma.c b/test/dm/dma.c
index 949710f..be38629 100644
--- a/test/dm/dma.c
+++ b/test/dm/dma.c
@@ -34,7 +34,7 @@
return 0;
}
-DM_TEST(dm_test_dma_m2m, UT_TESTF_SCAN_FDT);
+DM_TEST(dm_test_dma_m2m, UTF_SCAN_FDT);
static int dm_test_dma(struct unit_test_state *uts)
{
@@ -76,7 +76,7 @@
return 0;
}
-DM_TEST(dm_test_dma, UT_TESTF_SCAN_FDT);
+DM_TEST(dm_test_dma, UTF_SCAN_FDT);
static int dm_test_dma_rx(struct unit_test_state *uts)
{
@@ -121,4 +121,4 @@
return 0;
}
-DM_TEST(dm_test_dma_rx, UT_TESTF_SCAN_FDT);
+DM_TEST(dm_test_dma_rx, UTF_SCAN_FDT);
diff --git a/test/dm/dsa.c b/test/dm/dsa.c
index c857106..c6b4e12 100644
--- a/test/dm/dsa.c
+++ b/test/dm/dsa.c
@@ -56,8 +56,7 @@
return 0;
}
-
-DM_TEST(dm_test_dsa_probe, UT_TESTF_SCAN_FDT);
+DM_TEST(dm_test_dsa_probe, UTF_SCAN_FDT);
/* This test sends ping requests with the local address through each DSA port
* via the sandbox DSA master Eth.
@@ -78,5 +77,4 @@
return 0;
}
-
-DM_TEST(dm_test_dsa, UT_TESTF_SCAN_FDT);
+DM_TEST(dm_test_dsa, UTF_SCAN_FDT);
diff --git a/test/dm/dsi_host.c b/test/dm/dsi_host.c
index 68686a4..b927424 100644
--- a/test/dm/dsi_host.c
+++ b/test/dm/dsi_host.c
@@ -54,5 +54,4 @@
return 0;
}
-
-DM_TEST(dm_test_dsi_host, UT_TESTF_SCAN_PDATA | UT_TESTF_SCAN_FDT);
+DM_TEST(dm_test_dsi_host, UTF_SCAN_PDATA | UTF_SCAN_FDT);
diff --git a/test/dm/ecdsa.c b/test/dm/ecdsa.c
index da535c9..d7eac71 100644
--- a/test/dm/ecdsa.c
+++ b/test/dm/ecdsa.c
@@ -35,4 +35,4 @@
return 0;
}
-DM_TEST(dm_test_ecdsa_verify, UT_TESTF_SCAN_PDATA | UT_TESTF_SCAN_FDT);
+DM_TEST(dm_test_ecdsa_verify, UTF_SCAN_PDATA | UTF_SCAN_FDT);
diff --git a/test/dm/efi_media.c b/test/dm/efi_media.c
index 9d0ed0f..0cf7e37 100644
--- a/test/dm/efi_media.c
+++ b/test/dm/efi_media.c
@@ -20,4 +20,4 @@
return 0;
}
-DM_TEST(dm_test_efi_media, UT_TESTF_SCAN_PDATA | UT_TESTF_SCAN_FDT);
+DM_TEST(dm_test_efi_media, UTF_SCAN_PDATA | UTF_SCAN_FDT);
diff --git a/test/dm/eth.c b/test/dm/eth.c
index 820b8cb..4674958 100644
--- a/test/dm/eth.c
+++ b/test/dm/eth.c
@@ -166,7 +166,7 @@
return 0;
}
-DM_TEST(dm_test_ip6_make_lladdr, UT_TESTF_SCAN_FDT);
+DM_TEST(dm_test_ip6_make_lladdr, UTF_SCAN_FDT);
#endif
static int dm_test_eth(struct unit_test_state *uts)
@@ -187,7 +187,7 @@
return 0;
}
-DM_TEST(dm_test_eth, UT_TESTF_SCAN_FDT);
+DM_TEST(dm_test_eth, UTF_SCAN_FDT);
static int dm_test_eth_alias(struct unit_test_state *uts)
{
@@ -211,7 +211,7 @@
return 0;
}
-DM_TEST(dm_test_eth_alias, UT_TESTF_SCAN_FDT);
+DM_TEST(dm_test_eth_alias, UTF_SCAN_FDT);
static int dm_test_eth_prime(struct unit_test_state *uts)
{
@@ -231,7 +231,7 @@
return 0;
}
-DM_TEST(dm_test_eth_prime, UT_TESTF_SCAN_FDT);
+DM_TEST(dm_test_eth_prime, UTF_SCAN_FDT);
/**
* This test case is trying to test the following scenario:
@@ -296,7 +296,7 @@
return 0;
}
-DM_TEST(dm_test_eth_act, UT_TESTF_SCAN_FDT);
+DM_TEST(dm_test_eth_act, UTF_SCAN_FDT);
/* Ensure that all addresses are loaded properly */
static int dm_test_ethaddr(struct unit_test_state *uts)
@@ -329,7 +329,7 @@
return 0;
}
-DM_TEST(dm_test_ethaddr, UT_TESTF_SCAN_FDT);
+DM_TEST(dm_test_ethaddr, UTF_SCAN_FDT);
/* The asserts include a return on fail; cleanup in the caller */
static int _dm_test_eth_rotate1(struct unit_test_state *uts)
@@ -401,7 +401,7 @@
return retval;
}
-DM_TEST(dm_test_eth_rotate, UT_TESTF_SCAN_FDT);
+DM_TEST(dm_test_eth_rotate, UTF_SCAN_FDT);
/* The asserts include a return on fail; cleanup in the caller */
static int _dm_test_net_retry(struct unit_test_state *uts)
@@ -444,7 +444,7 @@
return retval;
}
-DM_TEST(dm_test_net_retry, UT_TESTF_SCAN_FDT);
+DM_TEST(dm_test_net_retry, UTF_SCAN_FDT);
static int sb_check_arp_reply(struct udevice *dev, void *packet,
unsigned int len)
@@ -528,8 +528,7 @@
return 0;
}
-
-DM_TEST(dm_test_eth_async_arp_reply, UT_TESTF_SCAN_FDT);
+DM_TEST(dm_test_eth_async_arp_reply, UTF_SCAN_FDT);
static int sb_check_ping_reply(struct udevice *dev, void *packet,
unsigned int len)
@@ -613,8 +612,7 @@
return 0;
}
-
-DM_TEST(dm_test_eth_async_ping_reply, UT_TESTF_SCAN_FDT);
+DM_TEST(dm_test_eth_async_ping_reply, UTF_SCAN_FDT);
#if IS_ENABLED(CONFIG_IPV6_ROUTER_DISCOVERY)
@@ -659,7 +657,6 @@
return 0;
}
-
DM_TEST(dm_test_validate_ra, 0);
static int dm_test_process_ra(struct unit_test_state *uts)
@@ -698,7 +695,6 @@
return 0;
}
-
DM_TEST(dm_test_process_ra, 0);
#endif
diff --git a/test/dm/extcon.c b/test/dm/extcon.c
index 6a4e22b..91358ab 100644
--- a/test/dm/extcon.c
+++ b/test/dm/extcon.c
@@ -17,5 +17,4 @@
return 0;
}
-
-DM_TEST(dm_test_extcon, UT_TESTF_SCAN_FDT);
+DM_TEST(dm_test_extcon, UTF_SCAN_FDT);
diff --git a/test/dm/fastboot.c b/test/dm/fastboot.c
index 5d938eb..73c43f8 100644
--- a/test/dm/fastboot.c
+++ b/test/dm/fastboot.c
@@ -91,4 +91,4 @@
return 0;
}
-DM_TEST(dm_test_fastboot_mmc_part, UT_TESTF_SCAN_PDATA | UT_TESTF_SCAN_FDT);
+DM_TEST(dm_test_fastboot_mmc_part, UTF_SCAN_PDATA | UTF_SCAN_FDT);
diff --git a/test/dm/fdtdec.c b/test/dm/fdtdec.c
index b484414..1f24f1d 100644
--- a/test/dm/fdtdec.c
+++ b/test/dm/fdtdec.c
@@ -55,7 +55,7 @@
return 0;
}
DM_TEST(dm_test_fdtdec_set_carveout,
- UT_TESTF_SCAN_PDATA | UT_TESTF_SCAN_FDT | UT_TESTF_FLAT_TREE);
+ UTF_SCAN_PDATA | UTF_SCAN_FDT | UTF_FLAT_TREE);
static int dm_test_fdtdec_add_reserved_memory(struct unit_test_state *uts)
{
@@ -128,4 +128,4 @@
return 0;
}
DM_TEST(dm_test_fdtdec_add_reserved_memory,
- UT_TESTF_SCAN_PDATA | UT_TESTF_SCAN_FDT | UT_TESTF_FLAT_TREE);
+ UTF_SCAN_PDATA | UTF_SCAN_FDT | UTF_FLAT_TREE);
diff --git a/test/dm/ffa.c b/test/dm/ffa.c
index fa6d54d..593b717 100644
--- a/test/dm/ffa.c
+++ b/test/dm/ffa.c
@@ -197,8 +197,7 @@
return 0;
}
-
-DM_TEST(dm_test_ffa_ack, UT_TESTF_SCAN_FDT | UT_TESTF_CONSOLE_REC);
+DM_TEST(dm_test_ffa_ack, UTF_SCAN_FDT | UTF_CONSOLE);
static int dm_test_ffa_nack(struct unit_test_state *uts)
{
@@ -256,5 +255,4 @@
return 0;
}
-
-DM_TEST(dm_test_ffa_nack, UT_TESTF_SCAN_FDT | UT_TESTF_CONSOLE_REC);
+DM_TEST(dm_test_ffa_nack, UTF_SCAN_FDT | UTF_CONSOLE);
diff --git a/test/dm/firmware.c b/test/dm/firmware.c
index ec68e81..795f6d5 100644
--- a/test/dm/firmware.c
+++ b/test/dm/firmware.c
@@ -19,4 +19,4 @@
"sandbox-firmware", &dev));
return 0;
}
-DM_TEST(dm_test_firmware_probe, UT_TESTF_SCAN_FDT);
+DM_TEST(dm_test_firmware_probe, UTF_SCAN_FDT);
diff --git a/test/dm/fpga.c b/test/dm/fpga.c
index 8bb3535..fe9f287 100644
--- a/test/dm/fpga.c
+++ b/test/dm/fpga.c
@@ -16,5 +16,4 @@
return 0;
}
-
-DM_TEST(dm_test_fpga, UT_TESTF_SCAN_FDT);
+DM_TEST(dm_test_fpga, UTF_SCAN_FDT);
diff --git a/test/dm/fwu_mdata.c b/test/dm/fwu_mdata.c
index 6154480..b768063 100644
--- a/test/dm/fwu_mdata.c
+++ b/test/dm/fwu_mdata.c
@@ -111,7 +111,7 @@
return 0;
}
-DM_TEST(dm_test_fwu_mdata_read, UT_TESTF_SCAN_FDT);
+DM_TEST(dm_test_fwu_mdata_read, UTF_SCAN_FDT);
static int dm_test_fwu_mdata_write(struct unit_test_state *uts)
{
@@ -142,4 +142,4 @@
return 0;
}
-DM_TEST(dm_test_fwu_mdata_write, UT_TESTF_SCAN_FDT);
+DM_TEST(dm_test_fwu_mdata_write, UTF_SCAN_FDT);
diff --git a/test/dm/gpio.c b/test/dm/gpio.c
index 957ab25..b45946c 100644
--- a/test/dm/gpio.c
+++ b/test/dm/gpio.c
@@ -145,7 +145,7 @@
return 0;
}
-DM_TEST(dm_test_gpio, UT_TESTF_SCAN_PDATA | UT_TESTF_SCAN_FDT);
+DM_TEST(dm_test_gpio, UTF_SCAN_PDATA | UTF_SCAN_FDT);
/* Test that GPIO open-drain/open-source emulation works correctly */
static int dm_test_gpio_opendrain_opensource(struct unit_test_state *uts)
@@ -244,7 +244,7 @@
return 0;
}
DM_TEST(dm_test_gpio_opendrain_opensource,
- UT_TESTF_SCAN_PDATA | UT_TESTF_SCAN_FDT);
+ UTF_SCAN_PDATA | UTF_SCAN_FDT);
/* Test that sandbox anonymous GPIOs work correctly */
static int dm_test_gpio_anon(struct unit_test_state *uts)
@@ -266,7 +266,7 @@
return 0;
}
-DM_TEST(dm_test_gpio_anon, UT_TESTF_SCAN_PDATA | UT_TESTF_SCAN_FDT);
+DM_TEST(dm_test_gpio_anon, UTF_SCAN_PDATA | UTF_SCAN_FDT);
/* Test that gpio_requestf() works as expected */
static int dm_test_gpio_requestf(struct unit_test_state *uts)
@@ -284,7 +284,7 @@
return 0;
}
-DM_TEST(dm_test_gpio_requestf, UT_TESTF_SCAN_PDATA | UT_TESTF_SCAN_FDT);
+DM_TEST(dm_test_gpio_requestf, UTF_SCAN_PDATA | UTF_SCAN_FDT);
/* Test that gpio_request() copies its string */
static int dm_test_gpio_copy(struct unit_test_state *uts)
@@ -306,7 +306,7 @@
return 0;
}
-DM_TEST(dm_test_gpio_copy, UT_TESTF_SCAN_PDATA | UT_TESTF_SCAN_FDT);
+DM_TEST(dm_test_gpio_copy, UTF_SCAN_PDATA | UTF_SCAN_FDT);
/* Test that we don't leak memory with GPIOs */
static int dm_test_gpio_leak(struct unit_test_state *uts)
@@ -318,7 +318,7 @@
return 0;
}
-DM_TEST(dm_test_gpio_leak, UT_TESTF_SCAN_PDATA | UT_TESTF_SCAN_FDT);
+DM_TEST(dm_test_gpio_leak, UTF_SCAN_PDATA | UTF_SCAN_FDT);
/* Test that we can find GPIOs using phandles */
static int dm_test_gpio_phandles(struct unit_test_state *uts)
@@ -392,7 +392,7 @@
return 0;
}
-DM_TEST(dm_test_gpio_phandles, UT_TESTF_SCAN_PDATA | UT_TESTF_SCAN_FDT);
+DM_TEST(dm_test_gpio_phandles, UTF_SCAN_PDATA | UTF_SCAN_FDT);
/* Check the gpio pin configuration get from device tree information */
static int dm_test_gpio_get_dir_flags(struct unit_test_state *uts)
@@ -428,7 +428,7 @@
return 0;
}
-DM_TEST(dm_test_gpio_get_dir_flags, UT_TESTF_SCAN_PDATA | UT_TESTF_SCAN_FDT);
+DM_TEST(dm_test_gpio_get_dir_flags, UTF_SCAN_PDATA | UTF_SCAN_FDT);
/* Test of gpio_get_acpi() */
static int dm_test_gpio_get_acpi(struct unit_test_state *uts)
@@ -457,7 +457,7 @@
return 0;
}
-DM_TEST(dm_test_gpio_get_acpi, UT_TESTF_SCAN_PDATA | UT_TESTF_SCAN_FDT);
+DM_TEST(dm_test_gpio_get_acpi, UTF_SCAN_PDATA | UTF_SCAN_FDT);
/* Test of gpio_get_acpi() with an interrupt GPIO */
static int dm_test_gpio_get_acpi_irq(struct unit_test_state *uts)
@@ -489,7 +489,7 @@
return 0;
}
-DM_TEST(dm_test_gpio_get_acpi_irq, UT_TESTF_SCAN_PDATA | UT_TESTF_SCAN_FDT);
+DM_TEST(dm_test_gpio_get_acpi_irq, UTF_SCAN_PDATA | UTF_SCAN_FDT);
/* Test that we can get/release GPIOs using managed API */
static int dm_test_gpio_devm(struct unit_test_state *uts)
@@ -590,7 +590,7 @@
device_remove(dev2, DM_REMOVE_NORMAL);
return 0;
}
-DM_TEST(dm_test_gpio_devm, UT_TESTF_SCAN_PDATA | UT_TESTF_SCAN_FDT);
+DM_TEST(dm_test_gpio_devm, UTF_SCAN_PDATA | UTF_SCAN_FDT);
static int dm_test_clrset_flags(struct unit_test_state *uts)
{
@@ -631,7 +631,7 @@
return 0;
}
-DM_TEST(dm_test_clrset_flags, UT_TESTF_SCAN_PDATA | UT_TESTF_SCAN_FDT);
+DM_TEST(dm_test_clrset_flags, UTF_SCAN_PDATA | UTF_SCAN_FDT);
/* Check that an active-low GPIO works as expected */
static int dm_test_clrset_flags_invert(struct unit_test_state *uts)
@@ -678,7 +678,7 @@
return 0;
}
-DM_TEST(dm_test_clrset_flags_invert, UT_TESTF_SCAN_PDATA | UT_TESTF_SCAN_FDT);
+DM_TEST(dm_test_clrset_flags_invert, UTF_SCAN_PDATA | UTF_SCAN_FDT);
static int set_gpios(struct unit_test_state *uts, struct gpio_desc *desc,
int count, uint value)
@@ -719,7 +719,7 @@
return 0;
}
DM_TEST(dm_test_gpio_get_values_as_int,
- UT_TESTF_SCAN_PDATA | UT_TESTF_SCAN_FDT);
+ UTF_SCAN_PDATA | UTF_SCAN_FDT);
/* Check that an active-low GPIO works as expected */
static int dm_test_gpio_get_values_as_int_base3(struct unit_test_state *uts)
@@ -776,7 +776,7 @@
return 0;
}
DM_TEST(dm_test_gpio_get_values_as_int_base3,
- UT_TESTF_SCAN_PDATA | UT_TESTF_SCAN_FDT);
+ UTF_SCAN_PDATA | UTF_SCAN_FDT);
/* Check that gpio_get_status return the label of a GPIO configured as GPIOD_AF */
static int dm_test_gpio_function(struct unit_test_state *uts)
@@ -806,4 +806,4 @@
return 0;
}
DM_TEST(dm_test_gpio_function,
- UT_TESTF_SCAN_PDATA | UT_TESTF_SCAN_FDT);
+ UTF_SCAN_PDATA | UTF_SCAN_FDT);
diff --git a/test/dm/host.c b/test/dm/host.c
index e514f84..f577377 100644
--- a/test/dm/host.c
+++ b/test/dm/host.c
@@ -72,7 +72,7 @@
return 0;
}
-DM_TEST(dm_test_host, UT_TESTF_SCAN_FDT);
+DM_TEST(dm_test_host, UTF_SCAN_FDT);
/* reusing the same label should work */
static int dm_test_host_dup(struct unit_test_state *uts)
@@ -106,7 +106,7 @@
return 0;
}
-DM_TEST(dm_test_host_dup, UT_TESTF_SCAN_FDT);
+DM_TEST(dm_test_host_dup, UTF_SCAN_FDT);
/* Basic test of 'host' command */
static int dm_test_cmd_host(struct unit_test_state *uts)
@@ -115,8 +115,6 @@
struct blk_desc *desc;
char fname[256];
- console_record_reset();
-
/* first check 'host info' with binding */
ut_assertok(run_command("host info", 0));
ut_assert_nextline("dev blocks blksz label path");
@@ -199,4 +197,4 @@
return 0;
}
-DM_TEST(dm_test_cmd_host, UT_TESTF_SCAN_FDT);
+DM_TEST(dm_test_cmd_host, UTF_SCAN_FDT | UTF_CONSOLE);
diff --git a/test/dm/hwspinlock.c b/test/dm/hwspinlock.c
index a05b183..58bba52 100644
--- a/test/dm/hwspinlock.c
+++ b/test/dm/hwspinlock.c
@@ -36,5 +36,4 @@
return 0;
}
-
-DM_TEST(dm_test_hwspinlock_base, UT_TESTF_SCAN_PDATA | UT_TESTF_SCAN_FDT);
+DM_TEST(dm_test_hwspinlock_base, UTF_SCAN_PDATA | UTF_SCAN_FDT);
diff --git a/test/dm/i2c.c b/test/dm/i2c.c
index e9cf9f7..40f1f26 100644
--- a/test/dm/i2c.c
+++ b/test/dm/i2c.c
@@ -38,7 +38,7 @@
return 0;
}
-DM_TEST(dm_test_i2c_find, UT_TESTF_SCAN_PDATA | UT_TESTF_SCAN_FDT);
+DM_TEST(dm_test_i2c_find, UTF_SCAN_PDATA | UTF_SCAN_FDT);
static int dm_test_i2c_read_write(struct unit_test_state *uts)
{
@@ -55,7 +55,7 @@
return 0;
}
-DM_TEST(dm_test_i2c_read_write, UT_TESTF_SCAN_PDATA | UT_TESTF_SCAN_FDT);
+DM_TEST(dm_test_i2c_read_write, UTF_SCAN_PDATA | UTF_SCAN_FDT);
static int dm_test_i2c_speed(struct unit_test_state *uts)
{
@@ -77,7 +77,7 @@
return 0;
}
-DM_TEST(dm_test_i2c_speed, UT_TESTF_SCAN_PDATA | UT_TESTF_SCAN_FDT);
+DM_TEST(dm_test_i2c_speed, UTF_SCAN_PDATA | UTF_SCAN_FDT);
static int dm_test_i2c_offset_len(struct unit_test_state *uts)
{
@@ -94,7 +94,7 @@
return 0;
}
-DM_TEST(dm_test_i2c_offset_len, UT_TESTF_SCAN_PDATA | UT_TESTF_SCAN_FDT);
+DM_TEST(dm_test_i2c_offset_len, UTF_SCAN_PDATA | UTF_SCAN_FDT);
static int dm_test_i2c_probe_empty(struct unit_test_state *uts)
{
@@ -109,7 +109,7 @@
return 0;
}
-DM_TEST(dm_test_i2c_probe_empty, UT_TESTF_SCAN_PDATA | UT_TESTF_SCAN_FDT);
+DM_TEST(dm_test_i2c_probe_empty, UTF_SCAN_PDATA | UTF_SCAN_FDT);
static int dm_test_i2c_bytewise(struct unit_test_state *uts)
{
@@ -164,7 +164,7 @@
return 0;
}
-DM_TEST(dm_test_i2c_bytewise, UT_TESTF_SCAN_PDATA | UT_TESTF_SCAN_FDT);
+DM_TEST(dm_test_i2c_bytewise, UTF_SCAN_PDATA | UTF_SCAN_FDT);
static int dm_test_i2c_offset(struct unit_test_state *uts)
{
@@ -237,7 +237,7 @@
return 0;
}
-DM_TEST(dm_test_i2c_offset, UT_TESTF_SCAN_PDATA | UT_TESTF_SCAN_FDT);
+DM_TEST(dm_test_i2c_offset, UTF_SCAN_PDATA | UTF_SCAN_FDT);
static int dm_test_i2c_addr_offset(struct unit_test_state *uts)
{
@@ -301,8 +301,7 @@
return 0;
}
-
-DM_TEST(dm_test_i2c_addr_offset, UT_TESTF_SCAN_PDATA | UT_TESTF_SCAN_FDT);
+DM_TEST(dm_test_i2c_addr_offset, UTF_SCAN_PDATA | UTF_SCAN_FDT);
static int dm_test_i2c_reg_clrset(struct unit_test_state *uts)
{
@@ -331,4 +330,4 @@
return 0;
}
-DM_TEST(dm_test_i2c_reg_clrset, UT_TESTF_SCAN_PDATA | UT_TESTF_SCAN_FDT);
+DM_TEST(dm_test_i2c_reg_clrset, UTF_SCAN_PDATA | UTF_SCAN_FDT);
diff --git a/test/dm/i2s.c b/test/dm/i2s.c
index a3d3a31..cc33669 100644
--- a/test/dm/i2s.c
+++ b/test/dm/i2s.c
@@ -29,4 +29,4 @@
return 0;
}
-DM_TEST(dm_test_i2s, UT_TESTF_SCAN_PDATA | UT_TESTF_SCAN_FDT);
+DM_TEST(dm_test_i2s, UTF_SCAN_PDATA | UTF_SCAN_FDT);
diff --git a/test/dm/iommu.c b/test/dm/iommu.c
index acea5f2..c5dd917 100644
--- a/test/dm/iommu.c
+++ b/test/dm/iommu.c
@@ -38,7 +38,7 @@
return 0;
}
-DM_TEST(dm_test_iommu, UT_TESTF_SCAN_FDT);
+DM_TEST(dm_test_iommu, UTF_SCAN_FDT);
static int dm_test_iommu_noiommu(struct unit_test_state *uts)
{
@@ -66,7 +66,7 @@
return 0;
}
-DM_TEST(dm_test_iommu_noiommu, UT_TESTF_SCAN_FDT);
+DM_TEST(dm_test_iommu_noiommu, UTF_SCAN_FDT);
static int dm_test_iommu_pci(struct unit_test_state *uts)
{
@@ -81,7 +81,7 @@
return 0;
}
-DM_TEST(dm_test_iommu_pci, UT_TESTF_SCAN_FDT);
+DM_TEST(dm_test_iommu_pci, UTF_SCAN_FDT);
static int dm_test_iommu_pci_noiommu(struct unit_test_state *uts)
{
@@ -96,4 +96,4 @@
return 0;
}
-DM_TEST(dm_test_iommu_pci_noiommu, UT_TESTF_SCAN_FDT);
+DM_TEST(dm_test_iommu_pci_noiommu, UTF_SCAN_FDT);
diff --git a/test/dm/irq.c b/test/dm/irq.c
index d22772a..836f2d8 100644
--- a/test/dm/irq.c
+++ b/test/dm/irq.c
@@ -30,7 +30,7 @@
return 0;
}
-DM_TEST(dm_test_irq_base, UT_TESTF_SCAN_PDATA | UT_TESTF_SCAN_FDT);
+DM_TEST(dm_test_irq_base, UTF_SCAN_PDATA | UTF_SCAN_FDT);
/* Test of irq_first_device_type() */
static int dm_test_irq_type(struct unit_test_state *uts)
@@ -42,7 +42,7 @@
return 0;
}
-DM_TEST(dm_test_irq_type, UT_TESTF_SCAN_PDATA | UT_TESTF_SCAN_FDT);
+DM_TEST(dm_test_irq_type, UTF_SCAN_PDATA | UTF_SCAN_FDT);
/* Test of irq_read_and_clear() */
static int dm_test_read_and_clear(struct unit_test_state *uts)
@@ -59,7 +59,7 @@
return 0;
}
-DM_TEST(dm_test_read_and_clear, UT_TESTF_SCAN_PDATA | UT_TESTF_SCAN_FDT);
+DM_TEST(dm_test_read_and_clear, UTF_SCAN_PDATA | UTF_SCAN_FDT);
/* Test of irq_request() */
static int dm_test_request(struct unit_test_state *uts)
@@ -74,7 +74,7 @@
return 0;
}
-DM_TEST(dm_test_request, UT_TESTF_SCAN_PDATA | UT_TESTF_SCAN_FDT);
+DM_TEST(dm_test_request, UTF_SCAN_PDATA | UTF_SCAN_FDT);
/* Test of irq_get_acpi() */
static int dm_test_irq_get_acpi(struct unit_test_state *uts)
@@ -96,4 +96,4 @@
return 0;
}
-DM_TEST(dm_test_irq_get_acpi, UT_TESTF_SCAN_PDATA | UT_TESTF_SCAN_FDT);
+DM_TEST(dm_test_irq_get_acpi, UTF_SCAN_PDATA | UTF_SCAN_FDT);
diff --git a/test/dm/led.c b/test/dm/led.c
index c28fa04..e1509c3 100644
--- a/test/dm/led.c
+++ b/test/dm/led.c
@@ -24,7 +24,7 @@
return 0;
}
-DM_TEST(dm_test_led_base, UT_TESTF_SCAN_PDATA | UT_TESTF_SCAN_FDT);
+DM_TEST(dm_test_led_base, UTF_SCAN_PDATA | UTF_SCAN_FDT);
/* Test of the LED 'default-state' device tree property */
static int dm_test_led_default_state(struct unit_test_state *uts)
@@ -41,7 +41,7 @@
return 0;
}
-DM_TEST(dm_test_led_default_state, UT_TESTF_SCAN_PDATA | UT_TESTF_SCAN_FDT);
+DM_TEST(dm_test_led_default_state, UTF_SCAN_PDATA | UTF_SCAN_FDT);
/* Test of the led uclass using the led_gpio driver */
static int dm_test_led_gpio(struct unit_test_state *uts)
@@ -66,7 +66,7 @@
return 0;
}
-DM_TEST(dm_test_led_gpio, UT_TESTF_SCAN_PDATA | UT_TESTF_SCAN_FDT);
+DM_TEST(dm_test_led_gpio, UTF_SCAN_PDATA | UTF_SCAN_FDT);
/* Test that we can toggle LEDs */
static int dm_test_led_toggle(struct unit_test_state *uts)
@@ -91,7 +91,7 @@
return 0;
}
-DM_TEST(dm_test_led_toggle, UT_TESTF_SCAN_PDATA | UT_TESTF_SCAN_FDT);
+DM_TEST(dm_test_led_toggle, UTF_SCAN_PDATA | UTF_SCAN_FDT);
/* Test obtaining an LED by label */
static int dm_test_led_label(struct unit_test_state *uts)
@@ -112,7 +112,7 @@
return 0;
}
-DM_TEST(dm_test_led_label, UT_TESTF_SCAN_PDATA | UT_TESTF_SCAN_FDT);
+DM_TEST(dm_test_led_label, UTF_SCAN_PDATA | UTF_SCAN_FDT);
/* Test LED blinking */
#ifdef CONFIG_LED_BLINK
@@ -135,5 +135,5 @@
return 0;
}
-DM_TEST(dm_test_led_blink, UT_TESTF_SCAN_PDATA | UT_TESTF_SCAN_FDT);
+DM_TEST(dm_test_led_blink, UTF_SCAN_PDATA | UTF_SCAN_FDT);
#endif
diff --git a/test/dm/mailbox.c b/test/dm/mailbox.c
index 14f72d5..4a0648b 100644
--- a/test/dm/mailbox.c
+++ b/test/dm/mailbox.c
@@ -28,4 +28,4 @@
return 0;
}
-DM_TEST(dm_test_mailbox, UT_TESTF_SCAN_FDT);
+DM_TEST(dm_test_mailbox, UTF_SCAN_FDT);
diff --git a/test/dm/mdio.c b/test/dm/mdio.c
index 7ececf3..6760c98 100644
--- a/test/dm/mdio.c
+++ b/test/dm/mdio.c
@@ -53,5 +53,4 @@
return 0;
}
-
-DM_TEST(dm_test_mdio, UT_TESTF_SCAN_FDT);
+DM_TEST(dm_test_mdio, UTF_SCAN_FDT);
diff --git a/test/dm/mdio_mux.c b/test/dm/mdio_mux.c
index 33a7e97..866feb2 100644
--- a/test/dm/mdio_mux.c
+++ b/test/dm/mdio_mux.c
@@ -76,5 +76,4 @@
return 0;
}
-
-DM_TEST(dm_test_mdio_mux, UT_TESTF_SCAN_FDT);
+DM_TEST(dm_test_mdio_mux, UTF_SCAN_FDT);
diff --git a/test/dm/memory.c b/test/dm/memory.c
index 7d9500a..34e64ba 100644
--- a/test/dm/memory.c
+++ b/test/dm/memory.c
@@ -17,5 +17,4 @@
return 0;
}
-
-DM_TEST(dm_test_memory, UT_TESTF_SCAN_FDT);
+DM_TEST(dm_test_memory, UTF_SCAN_FDT);
diff --git a/test/dm/misc.c b/test/dm/misc.c
index ad856fd..250885d 100644
--- a/test/dm/misc.c
+++ b/test/dm/misc.c
@@ -79,5 +79,4 @@
return 0;
}
-
-DM_TEST(dm_test_misc, UT_TESTF_SCAN_FDT);
+DM_TEST(dm_test_misc, UTF_SCAN_FDT);
diff --git a/test/dm/mmc.c b/test/dm/mmc.c
index c0abea7..cdebb95 100644
--- a/test/dm/mmc.c
+++ b/test/dm/mmc.c
@@ -22,7 +22,7 @@
return 0;
}
-DM_TEST(dm_test_mmc_base, UT_TESTF_SCAN_PDATA | UT_TESTF_SCAN_FDT);
+DM_TEST(dm_test_mmc_base, UTF_SCAN_PDATA | UTF_SCAN_FDT);
static int dm_test_mmc_blk(struct unit_test_state *uts)
{
@@ -50,4 +50,4 @@
return 0;
}
-DM_TEST(dm_test_mmc_blk, UT_TESTF_SCAN_PDATA | UT_TESTF_SCAN_FDT);
+DM_TEST(dm_test_mmc_blk, UTF_SCAN_PDATA | UTF_SCAN_FDT);
diff --git a/test/dm/mux-cmd.c b/test/dm/mux-cmd.c
index d4bb8be..6eb3b28 100644
--- a/test/dm/mux-cmd.c
+++ b/test/dm/mux-cmd.c
@@ -109,7 +109,7 @@
return 0;
}
-DM_TEST(dm_test_cmd_mux_list, UT_TESTF_SCAN_PDATA | UT_TESTF_SCAN_FDT);
+DM_TEST(dm_test_cmd_mux_list, UTF_SCAN_PDATA | UTF_SCAN_FDT | UTF_CONSOLE);
static int dm_test_cmd_mux_select(struct unit_test_state *uts)
{
@@ -143,7 +143,7 @@
return 0;
}
-DM_TEST(dm_test_cmd_mux_select, UT_TESTF_SCAN_PDATA | UT_TESTF_SCAN_FDT);
+DM_TEST(dm_test_cmd_mux_select, UTF_SCAN_PDATA | UTF_SCAN_FDT);
static int dm_test_cmd_mux_deselect(struct unit_test_state *uts)
{
@@ -174,4 +174,4 @@
return 0;
}
-DM_TEST(dm_test_cmd_mux_deselect, UT_TESTF_SCAN_PDATA | UT_TESTF_SCAN_FDT);
+DM_TEST(dm_test_cmd_mux_deselect, UTF_SCAN_PDATA | UTF_SCAN_FDT);
diff --git a/test/dm/mux-emul.c b/test/dm/mux-emul.c
index febd521..de231e4 100644
--- a/test/dm/mux-emul.c
+++ b/test/dm/mux-emul.c
@@ -79,7 +79,7 @@
return 0;
}
-DM_TEST(dm_test_mux_emul_default_state, UT_TESTF_SCAN_PDATA | UT_TESTF_SCAN_FDT);
+DM_TEST(dm_test_mux_emul_default_state, UTF_SCAN_PDATA | UTF_SCAN_FDT);
static int dm_test_mux_emul_select_deselect(struct unit_test_state *uts)
{
@@ -102,4 +102,4 @@
return 0;
}
-DM_TEST(dm_test_mux_emul_select_deselect, UT_TESTF_SCAN_PDATA | UT_TESTF_SCAN_FDT);
+DM_TEST(dm_test_mux_emul_select_deselect, UTF_SCAN_PDATA | UTF_SCAN_FDT);
diff --git a/test/dm/mux-mmio.c b/test/dm/mux-mmio.c
index 3a871a1..3bb1e49 100644
--- a/test/dm/mux-mmio.c
+++ b/test/dm/mux-mmio.c
@@ -85,7 +85,7 @@
return 0;
}
-DM_TEST(dm_test_mux_mmio_select, UT_TESTF_SCAN_PDATA | UT_TESTF_SCAN_FDT);
+DM_TEST(dm_test_mux_mmio_select, UTF_SCAN_PDATA | UTF_SCAN_FDT);
/* Test that managed API for mux work correctly */
static int dm_test_devm_mux_mmio(struct unit_test_state *uts)
@@ -134,4 +134,4 @@
device_remove(dev_b, DM_REMOVE_NORMAL);
return 0;
}
-DM_TEST(dm_test_devm_mux_mmio, UT_TESTF_SCAN_PDATA | UT_TESTF_SCAN_FDT);
+DM_TEST(dm_test_devm_mux_mmio, UTF_SCAN_PDATA | UTF_SCAN_FDT);
diff --git a/test/dm/nand.c b/test/dm/nand.c
index 0b992fd..c7e0985 100644
--- a/test/dm/nand.c
+++ b/test/dm/nand.c
@@ -12,7 +12,7 @@
#include <linux/mtd/mtd.h>
#include <linux/mtd/rawnand.h>
-static int dm_test_nand(struct unit_test_state *uts, int dev, bool end)
+static int run_test_nand(struct unit_test_state *uts, int dev, bool end)
{
nand_erase_options_t opts = { };
struct mtd_info *mtd;
@@ -88,17 +88,34 @@
return 0;
}
-#define DM_NAND_TEST(dev) \
-static int dm_test_nand##dev##_start(struct unit_test_state *uts) \
-{ \
- return dm_test_nand(uts, dev, false); \
-} \
-DM_TEST(dm_test_nand##dev##_start, UT_TESTF_SCAN_FDT); \
-static int dm_test_nand##dev##_end(struct unit_test_state *uts) \
-{ \
- return dm_test_nand(uts, dev, true); \
-} \
-DM_TEST(dm_test_nand##dev##_end, UT_TESTF_SCAN_FDT)
+static int dm_test_nand0_start(struct unit_test_state *uts)
+{
+ ut_assertok(run_test_nand(uts, 0, false));
+
+ return 0;
+}
+DM_TEST(dm_test_nand0_start, UTF_SCAN_FDT);
+
+static int dm_test_nand1_start(struct unit_test_state *uts)
+{
+ ut_assertok(run_test_nand(uts, 1, false));
+
+ return 0;
+}
+DM_TEST(dm_test_nand1_start, UTF_SCAN_FDT);
-DM_NAND_TEST(0);
-DM_NAND_TEST(1);
+static int dm_test_nand0_end(struct unit_test_state *uts)
+{
+ ut_assertok(run_test_nand(uts, 0, true));
+
+ return 0;
+}
+DM_TEST(dm_test_nand0_end, UTF_SCAN_FDT);
+
+static int dm_test_nand1_end(struct unit_test_state *uts)
+{
+ ut_assertok(run_test_nand(uts, 1, true));
+
+ return 0;
+}
+DM_TEST(dm_test_nand1_end, UTF_SCAN_FDT);
diff --git a/test/dm/nop.c b/test/dm/nop.c
index 0c79431..a6f5f82 100644
--- a/test/dm/nop.c
+++ b/test/dm/nop.c
@@ -69,5 +69,4 @@
return 0;
}
-
-DM_TEST(dm_test_nop, UT_TESTF_FLAT_TREE | UT_TESTF_SCAN_FDT);
+DM_TEST(dm_test_nop, UTF_FLAT_TREE | UTF_SCAN_FDT);
diff --git a/test/dm/nvmxip.c b/test/dm/nvmxip.c
index 537959a..a702d0a 100644
--- a/test/dm/nvmxip.c
+++ b/test/dm/nvmxip.c
@@ -142,5 +142,4 @@
return CMD_RET_SUCCESS;
}
-
-DM_TEST(dm_test_nvmxip, UT_TESTF_SCAN_FDT | UT_TESTF_CONSOLE_REC);
+DM_TEST(dm_test_nvmxip, UTF_SCAN_FDT | UTF_CONSOLE);
diff --git a/test/dm/of_platdata.c b/test/dm/of_platdata.c
index d4939e8..6e35bca 100644
--- a/test/dm/of_platdata.c
+++ b/test/dm/of_platdata.c
@@ -20,7 +20,7 @@
return 0;
}
-DM_TEST(dm_test_of_plat_base, UT_TESTF_SCAN_PDATA);
+DM_TEST(dm_test_of_plat_base, UTF_SCAN_PDATA);
/* Test that we can read properties from a device */
static int dm_test_of_plat_props(struct unit_test_state *uts)
@@ -91,7 +91,7 @@
return 0;
}
-DM_TEST(dm_test_of_plat_props, UT_TESTF_SCAN_PDATA);
+DM_TEST(dm_test_of_plat_props, UTF_SCAN_PDATA);
/*
* find_driver_info - recursively find the driver_info for a device
@@ -173,7 +173,7 @@
return 0;
}
-DM_TEST(dm_test_of_plat_dev, UT_TESTF_SCAN_PDATA);
+DM_TEST(dm_test_of_plat_dev, UTF_SCAN_PDATA);
/* Test handling of phandles that point to other devices */
static int dm_test_of_plat_phandle(struct unit_test_state *uts)
@@ -206,7 +206,7 @@
return 0;
}
-DM_TEST(dm_test_of_plat_phandle, UT_TESTF_SCAN_PDATA);
+DM_TEST(dm_test_of_plat_phandle, UTF_SCAN_PDATA);
#if CONFIG_IS_ENABLED(OF_PLATDATA_PARENT)
/* Test that device parents are correctly set up */
@@ -220,7 +220,7 @@
return 0;
}
-DM_TEST(dm_test_of_plat_parent, UT_TESTF_SCAN_PDATA);
+DM_TEST(dm_test_of_plat_parent, UTF_SCAN_PDATA);
#endif
/* Test clocks with of-platdata */
@@ -239,7 +239,7 @@
return 0;
}
-DM_TEST(dm_test_of_plat_clk, UT_TESTF_SCAN_PDATA);
+DM_TEST(dm_test_of_plat_clk, UTF_SCAN_PDATA);
/* Test irqs with of-platdata */
static int dm_test_of_plat_irq(struct unit_test_state *uts)
@@ -258,7 +258,7 @@
return 0;
}
-DM_TEST(dm_test_of_plat_irq, UT_TESTF_SCAN_PDATA);
+DM_TEST(dm_test_of_plat_irq, UTF_SCAN_PDATA);
/* Test GPIOs with of-platdata */
static int dm_test_of_plat_gpio(struct unit_test_state *uts)
@@ -277,4 +277,4 @@
return 0;
}
-DM_TEST(dm_test_of_plat_gpio, UT_TESTF_SCAN_PDATA);
+DM_TEST(dm_test_of_plat_gpio, UTF_SCAN_PDATA);
diff --git a/test/dm/ofnode.c b/test/dm/ofnode.c
index 39191d7..859fc3a 100644
--- a/test/dm/ofnode.c
+++ b/test/dm/ofnode.c
@@ -47,7 +47,7 @@
/* An invalid tree may cause failure or crashes */
if (!oftree_valid(tree))
- ut_reportf("test needs the UT_TESTF_OTHER_FDT flag");
+ ut_reportf("test needs the UTF_OTHER_FDT flag");
return tree;
}
@@ -103,7 +103,7 @@
return 0;
}
DM_TEST(dm_test_ofnode_compatible,
- UT_TESTF_SCAN_PDATA | UT_TESTF_SCAN_FDT);
+ UTF_SCAN_PDATA | UTF_SCAN_FDT);
/* check ofnode_device_is_compatible() with the 'other' FDT */
static int dm_test_ofnode_compatible_ot(struct unit_test_state *uts)
@@ -116,7 +116,7 @@
return 0;
}
-DM_TEST(dm_test_ofnode_compatible_ot, UT_TESTF_SCAN_FDT | UT_TESTF_OTHER_FDT);
+DM_TEST(dm_test_ofnode_compatible_ot, UTF_SCAN_FDT | UTF_OTHER_FDT);
static int dm_test_ofnode_get_by_phandle(struct unit_test_state *uts)
{
@@ -134,7 +134,7 @@
return 0;
}
-DM_TEST(dm_test_ofnode_get_by_phandle, UT_TESTF_SCAN_PDATA | UT_TESTF_SCAN_FDT);
+DM_TEST(dm_test_ofnode_get_by_phandle, UTF_SCAN_PDATA | UTF_SCAN_FDT);
/* test oftree_get_by_phandle() with a the 'other' oftree */
static int dm_test_ofnode_get_by_phandle_ot(struct unit_test_state *uts)
@@ -150,7 +150,7 @@
return 0;
}
DM_TEST(dm_test_ofnode_get_by_phandle_ot,
- UT_TESTF_SCAN_FDT | UT_TESTF_OTHER_FDT);
+ UTF_SCAN_FDT | UTF_OTHER_FDT);
static int check_prop_values(struct unit_test_state *uts, ofnode start,
const char *propname, const char *propval,
@@ -189,7 +189,7 @@
return 0;
}
-DM_TEST(dm_test_ofnode_by_prop_value, UT_TESTF_SCAN_FDT);
+DM_TEST(dm_test_ofnode_by_prop_value, UTF_SCAN_FDT);
/* test ofnode_by_prop_value() with a the 'other' oftree */
static int dm_test_ofnode_by_prop_value_ot(struct unit_test_state *uts)
@@ -202,7 +202,7 @@
return 0;
}
DM_TEST(dm_test_ofnode_by_prop_value_ot,
- UT_TESTF_SCAN_FDT | UT_TESTF_OTHER_FDT);
+ UTF_SCAN_FDT | UTF_OTHER_FDT);
/* test ofnode_read_fmap_entry() */
static int dm_test_ofnode_fmap(struct unit_test_state *uts)
@@ -218,7 +218,7 @@
return 0;
}
-DM_TEST(dm_test_ofnode_fmap, UT_TESTF_SCAN_PDATA | UT_TESTF_SCAN_FDT);
+DM_TEST(dm_test_ofnode_fmap, UTF_SCAN_PDATA | UTF_SCAN_FDT);
/* test ofnode_read_prop() */
static int dm_test_ofnode_read(struct unit_test_state *uts)
@@ -248,7 +248,7 @@
return 0;
}
-DM_TEST(dm_test_ofnode_read, UT_TESTF_SCAN_FDT);
+DM_TEST(dm_test_ofnode_read, UTF_SCAN_FDT);
/* test ofnode_read_prop() with the 'other' tree */
static int dm_test_ofnode_read_ot(struct unit_test_state *uts)
@@ -271,7 +271,7 @@
return 0;
}
-DM_TEST(dm_test_ofnode_read_ot, UT_TESTF_SCAN_FDT | UT_TESTF_OTHER_FDT);
+DM_TEST(dm_test_ofnode_read_ot, UTF_SCAN_FDT | UTF_OTHER_FDT);
/* test ofnode_count_/parse_phandle_with_args() */
static int dm_test_ofnode_phandle(struct unit_test_state *uts)
@@ -347,7 +347,7 @@
return 0;
}
-DM_TEST(dm_test_ofnode_phandle, UT_TESTF_SCAN_PDATA | UT_TESTF_SCAN_FDT);
+DM_TEST(dm_test_ofnode_phandle, UTF_SCAN_PDATA | UTF_SCAN_FDT);
/* test ofnode_count_/parse_phandle_with_args() with 'other' tree */
static int dm_test_ofnode_phandle_ot(struct unit_test_state *uts)
@@ -376,7 +376,7 @@
return 0;
}
-DM_TEST(dm_test_ofnode_phandle_ot, UT_TESTF_OTHER_FDT);
+DM_TEST(dm_test_ofnode_phandle_ot, UTF_OTHER_FDT);
/* test ofnode_read_chosen_string/node/prop() */
static int dm_test_ofnode_read_chosen(struct unit_test_state *uts)
@@ -406,7 +406,7 @@
return 0;
}
-DM_TEST(dm_test_ofnode_read_chosen, UT_TESTF_SCAN_PDATA | UT_TESTF_SCAN_FDT);
+DM_TEST(dm_test_ofnode_read_chosen, UTF_SCAN_PDATA | UTF_SCAN_FDT);
/* test ofnode_get_aliases_node/prop() */
static int dm_test_ofnode_read_aliases(struct unit_test_state *uts)
@@ -429,7 +429,7 @@
return 0;
}
-DM_TEST(dm_test_ofnode_read_aliases, UT_TESTF_SCAN_PDATA | UT_TESTF_SCAN_FDT);
+DM_TEST(dm_test_ofnode_read_aliases, UTF_SCAN_PDATA | UTF_SCAN_FDT);
static int dm_test_ofnode_get_child_count(struct unit_test_state *uts)
{
@@ -450,7 +450,7 @@
return 0;
}
DM_TEST(dm_test_ofnode_get_child_count,
- UT_TESTF_SCAN_PDATA | UT_TESTF_SCAN_FDT);
+ UTF_SCAN_PDATA | UTF_SCAN_FDT);
/* test ofnode_get_child_count() with 'other' tree */
static int dm_test_ofnode_get_child_count_ot(struct unit_test_state *uts)
@@ -473,7 +473,7 @@
return 0;
}
DM_TEST(dm_test_ofnode_get_child_count_ot,
- UT_TESTF_SCAN_FDT | UT_TESTF_OTHER_FDT);
+ UTF_SCAN_FDT | UTF_OTHER_FDT);
static int dm_test_ofnode_is_enabled(struct unit_test_state *uts)
{
@@ -485,7 +485,7 @@
return 0;
}
-DM_TEST(dm_test_ofnode_is_enabled, UT_TESTF_SCAN_PDATA | UT_TESTF_SCAN_FDT);
+DM_TEST(dm_test_ofnode_is_enabled, UTF_SCAN_PDATA | UTF_SCAN_FDT);
/* test ofnode_is_enabled() with 'other' tree */
static int dm_test_ofnode_is_enabled_ot(struct unit_test_state *uts)
@@ -499,7 +499,7 @@
return 0;
}
-DM_TEST(dm_test_ofnode_is_enabled_ot, UT_TESTF_OTHER_FDT);
+DM_TEST(dm_test_ofnode_is_enabled_ot, UTF_OTHER_FDT);
/* test ofnode_get_addr/size() */
static int dm_test_ofnode_get_reg(struct unit_test_state *uts)
@@ -536,7 +536,7 @@
return 0;
}
-DM_TEST(dm_test_ofnode_get_reg, UT_TESTF_SCAN_PDATA | UT_TESTF_SCAN_FDT);
+DM_TEST(dm_test_ofnode_get_reg, UTF_SCAN_PDATA | UTF_SCAN_FDT);
/* test ofnode_get_addr() with 'other' tree */
static int dm_test_ofnode_get_reg_ot(struct unit_test_state *uts)
@@ -550,7 +550,7 @@
return 0;
}
-DM_TEST(dm_test_ofnode_get_reg_ot, UT_TESTF_SCAN_FDT | UT_TESTF_OTHER_FDT);
+DM_TEST(dm_test_ofnode_get_reg_ot, UTF_SCAN_FDT | UTF_OTHER_FDT);
static int dm_test_ofnode_get_path(struct unit_test_state *uts)
{
@@ -571,7 +571,7 @@
return 0;
}
-DM_TEST(dm_test_ofnode_get_path, UT_TESTF_SCAN_PDATA | UT_TESTF_SCAN_FDT);
+DM_TEST(dm_test_ofnode_get_path, UTF_SCAN_PDATA | UTF_SCAN_FDT);
/* test ofnode_get_path() with 'other' tree */
static int dm_test_ofnode_get_path_ot(struct unit_test_state *uts)
@@ -591,7 +591,7 @@
return 0;
}
-DM_TEST(dm_test_ofnode_get_path_ot, UT_TESTF_SCAN_FDT | UT_TESTF_OTHER_FDT);
+DM_TEST(dm_test_ofnode_get_path_ot, UTF_SCAN_FDT | UTF_OTHER_FDT);
/* test ofnode_conf_read_bool/int/str() */
static int dm_test_ofnode_conf(struct unit_test_state *uts)
@@ -607,7 +607,7 @@
return 0;
}
-DM_TEST(dm_test_ofnode_conf, UT_TESTF_SCAN_FDT);
+DM_TEST(dm_test_ofnode_conf, UTF_SCAN_FDT);
static int dm_test_ofnode_options(struct unit_test_state *uts)
{
@@ -644,7 +644,7 @@
return 0;
}
-DM_TEST(dm_test_ofnode_for_each_compatible_node, UT_TESTF_SCAN_FDT);
+DM_TEST(dm_test_ofnode_for_each_compatible_node, UTF_SCAN_FDT);
/* test dm_test_ofnode_string_count/index/list() */
static int dm_test_ofnode_string(struct unit_test_state *uts)
@@ -692,7 +692,7 @@
return 0;
}
-DM_TEST(dm_test_ofnode_string, UT_TESTF_SCAN_FDT);
+DM_TEST(dm_test_ofnode_string, UTF_SCAN_FDT);
/* test error returns from ofnode_read_string_count/index/list() */
static int dm_test_ofnode_string_err(struct unit_test_state *uts)
@@ -742,7 +742,7 @@
return 0;
}
-DM_TEST(dm_test_ofnode_string_err, UT_TESTF_LIVE_TREE);
+DM_TEST(dm_test_ofnode_string_err, UTF_LIVE_TREE);
static int dm_test_ofnode_read_phy_mode(struct unit_test_state *uts)
{
@@ -764,7 +764,7 @@
return 0;
}
-DM_TEST(dm_test_ofnode_read_phy_mode, UT_TESTF_SCAN_FDT);
+DM_TEST(dm_test_ofnode_read_phy_mode, UTF_SCAN_FDT);
/**
* make_ofnode_fdt() - Create an FDT for testing with ofnode
@@ -811,7 +811,7 @@
return 0;
}
-DM_TEST(dm_test_ofnode_aliases, UT_TESTF_SCAN_FDT);
+DM_TEST(dm_test_ofnode_aliases, UTF_SCAN_FDT);
/**
* dm_test_ofnode_root_mult() - Check aliaes on control and 'other' tree
@@ -850,7 +850,7 @@
return 0;
}
-DM_TEST(dm_test_ofnode_root_mult, UT_TESTF_SCAN_FDT);
+DM_TEST(dm_test_ofnode_root_mult, UTF_SCAN_FDT);
/* test ofnode_set_enabled(), ofnode_write_prop() on a livetree */
static int dm_test_ofnode_livetree_writing(struct unit_test_state *uts)
@@ -897,7 +897,7 @@
return 0;
}
DM_TEST(dm_test_ofnode_livetree_writing,
- UT_TESTF_SCAN_PDATA | UT_TESTF_SCAN_FDT);
+ UTF_SCAN_PDATA | UTF_SCAN_FDT);
static int check_write_prop(struct unit_test_state *uts, ofnode node)
{
@@ -940,7 +940,7 @@
return 0;
}
-DM_TEST(dm_test_ofnode_write_copy, UT_TESTF_SCAN_FDT);
+DM_TEST(dm_test_ofnode_write_copy, UTF_SCAN_FDT);
/* test writing a property to the 'other' tree */
static int dm_test_ofnode_write_copy_ot(struct unit_test_state *uts)
@@ -957,7 +957,7 @@
return 0;
}
-DM_TEST(dm_test_ofnode_write_copy_ot, UT_TESTF_SCAN_FDT | UT_TESTF_OTHER_FDT);
+DM_TEST(dm_test_ofnode_write_copy_ot, UTF_SCAN_FDT | UTF_OTHER_FDT);
/* test ofnode_read_u32_index/default() */
static int dm_test_ofnode_u32(struct unit_test_state *uts)
@@ -985,7 +985,7 @@
return 0;
}
-DM_TEST(dm_test_ofnode_u32, UT_TESTF_SCAN_PDATA | UT_TESTF_SCAN_FDT);
+DM_TEST(dm_test_ofnode_u32, UTF_SCAN_PDATA | UTF_SCAN_FDT);
/* test ofnode_read_u32_array() */
static int dm_test_ofnode_u32_array(struct unit_test_state *uts)
@@ -1012,7 +1012,7 @@
return 0;
}
-DM_TEST(dm_test_ofnode_u32_array, UT_TESTF_SCAN_PDATA | UT_TESTF_SCAN_FDT);
+DM_TEST(dm_test_ofnode_u32_array, UTF_SCAN_PDATA | UTF_SCAN_FDT);
/* test ofnode_read_u64() and ofnode_write_u64() */
static int dm_test_ofnode_u64(struct unit_test_state *uts)
@@ -1046,7 +1046,7 @@
return 0;
}
-DM_TEST(dm_test_ofnode_u64, UT_TESTF_SCAN_FDT);
+DM_TEST(dm_test_ofnode_u64, UTF_SCAN_FDT);
static int dm_test_ofnode_add_subnode(struct unit_test_state *uts)
{
@@ -1115,7 +1115,7 @@
return 0;
}
-DM_TEST(dm_test_ofnode_add_subnode, UT_TESTF_SCAN_PDATA | UT_TESTF_SCAN_FDT);
+DM_TEST(dm_test_ofnode_add_subnode, UTF_SCAN_PDATA | UTF_SCAN_FDT);
static int dm_test_ofnode_for_each_prop(struct unit_test_state *uts)
{
@@ -1139,7 +1139,7 @@
return 0;
}
-DM_TEST(dm_test_ofnode_for_each_prop, UT_TESTF_SCAN_FDT);
+DM_TEST(dm_test_ofnode_for_each_prop, UTF_SCAN_FDT);
static int dm_test_ofnode_by_compatible(struct unit_test_state *uts)
{
@@ -1155,7 +1155,7 @@
return 0;
}
-DM_TEST(dm_test_ofnode_by_compatible, UT_TESTF_SCAN_FDT);
+DM_TEST(dm_test_ofnode_by_compatible, UTF_SCAN_FDT);
/* check ofnode_by_compatible() on the 'other' tree */
static int dm_test_ofnode_by_compatible_ot(struct unit_test_state *uts)
@@ -1173,7 +1173,7 @@
return 0;
}
-DM_TEST(dm_test_ofnode_by_compatible_ot, UT_TESTF_SCAN_FDT | UT_TESTF_OTHER_FDT);
+DM_TEST(dm_test_ofnode_by_compatible_ot, UTF_SCAN_FDT | UTF_OTHER_FDT);
static int dm_test_ofnode_find_subnode(struct unit_test_state *uts)
{
@@ -1190,7 +1190,7 @@
return 0;
}
-DM_TEST(dm_test_ofnode_find_subnode, UT_TESTF_SCAN_FDT);
+DM_TEST(dm_test_ofnode_find_subnode, UTF_SCAN_FDT);
/* test ofnode_find_subnode() on the 'other' tree */
static int dm_test_ofnode_find_subnode_ot(struct unit_test_state *uts)
@@ -1209,7 +1209,7 @@
return 0;
}
-DM_TEST(dm_test_ofnode_find_subnode_ot, UT_TESTF_OTHER_FDT);
+DM_TEST(dm_test_ofnode_find_subnode_ot, UTF_OTHER_FDT);
static int dm_test_ofnode_get_name(struct unit_test_state *uts)
{
@@ -1222,7 +1222,7 @@
return 0;
}
-DM_TEST(dm_test_ofnode_get_name, UT_TESTF_SCAN_FDT);
+DM_TEST(dm_test_ofnode_get_name, UTF_SCAN_FDT);
/* try to access more FDTs than is supported */
static int dm_test_ofnode_too_many(struct unit_test_state *uts)
@@ -1259,7 +1259,7 @@
return 0;
}
-DM_TEST(dm_test_ofnode_too_many, UT_TESTF_SCAN_FDT);
+DM_TEST(dm_test_ofnode_too_many, UTF_SCAN_FDT);
static int check_copy_props(struct unit_test_state *uts, ofnode dst, ofnode src)
{
@@ -1304,7 +1304,7 @@
return 0;
}
-DM_TEST(dm_test_ofnode_copy_props, UT_TESTF_SCAN_FDT);
+DM_TEST(dm_test_ofnode_copy_props, UTF_SCAN_FDT);
/* test ofnode_copy_props() with the 'other' tree */
static int dm_test_ofnode_copy_props_ot(struct unit_test_state *uts)
@@ -1318,7 +1318,7 @@
return 0;
}
-DM_TEST(dm_test_ofnode_copy_props_ot, UT_TESTF_SCAN_FDT | UT_TESTF_OTHER_FDT);
+DM_TEST(dm_test_ofnode_copy_props_ot, UTF_SCAN_FDT | UTF_OTHER_FDT);
/* check that the livetree is aligned to a structure boundary */
static int dm_test_livetree_align(struct unit_test_state *uts)
@@ -1344,7 +1344,7 @@
return 0;
}
-DM_TEST(dm_test_livetree_align, UT_TESTF_SCAN_FDT | UT_TESTF_LIVE_TREE);
+DM_TEST(dm_test_livetree_align, UTF_SCAN_FDT | UTF_LIVE_TREE);
/* check that it is possible to load an arbitrary livetree */
static int dm_test_livetree_ensure(struct unit_test_state *uts)
@@ -1363,7 +1363,7 @@
return 0;
}
-DM_TEST(dm_test_livetree_ensure, UT_TESTF_SCAN_FDT);
+DM_TEST(dm_test_livetree_ensure, UTF_SCAN_FDT);
static int dm_test_oftree_new(struct unit_test_state *uts)
{
@@ -1379,7 +1379,7 @@
return 0;
}
-DM_TEST(dm_test_oftree_new, UT_TESTF_SCAN_FDT);
+DM_TEST(dm_test_oftree_new, UTF_SCAN_FDT);
static int check_copy_node(struct unit_test_state *uts, ofnode dst, ofnode src,
ofnode *nodep)
@@ -1428,7 +1428,7 @@
return 0;
}
-DM_TEST(dm_test_ofnode_copy_node, UT_TESTF_SCAN_FDT);
+DM_TEST(dm_test_ofnode_copy_node, UTF_SCAN_FDT);
/* test ofnode_copy_node() with the 'other' tree */
static int dm_test_ofnode_copy_node_ot(struct unit_test_state *uts)
@@ -1442,7 +1442,7 @@
return 0;
}
-DM_TEST(dm_test_ofnode_copy_node_ot, UT_TESTF_SCAN_FDT | UT_TESTF_OTHER_FDT);
+DM_TEST(dm_test_ofnode_copy_node_ot, UTF_SCAN_FDT | UTF_OTHER_FDT);
static int dm_test_ofnode_delete(struct unit_test_state *uts)
{
@@ -1473,7 +1473,7 @@
return 0;
}
-DM_TEST(dm_test_ofnode_delete, UT_TESTF_SCAN_FDT);
+DM_TEST(dm_test_ofnode_delete, UTF_SCAN_FDT);
static int dm_test_oftree_to_fdt(struct unit_test_state *uts)
{
@@ -1495,7 +1495,7 @@
return 0;
}
-DM_TEST(dm_test_oftree_to_fdt, UT_TESTF_SCAN_FDT);
+DM_TEST(dm_test_oftree_to_fdt, UTF_SCAN_FDT);
/* test ofnode_read_bool() and ofnode_write_bool() */
static int dm_test_bool(struct unit_test_state *uts)
@@ -1520,4 +1520,4 @@
return 0;
}
-DM_TEST(dm_test_bool, UT_TESTF_SCAN_FDT);
+DM_TEST(dm_test_bool, UTF_SCAN_FDT);
diff --git a/test/dm/ofread.c b/test/dm/ofread.c
index 69d03c4..069551a 100644
--- a/test/dm/ofread.c
+++ b/test/dm/ofread.c
@@ -45,4 +45,4 @@
return 0;
}
-DM_TEST(dm_test_ofprop_get_property, UT_TESTF_SCAN_PDATA | UT_TESTF_SCAN_FDT);
+DM_TEST(dm_test_ofprop_get_property, UTF_SCAN_PDATA | UTF_SCAN_FDT);
diff --git a/test/dm/osd.c b/test/dm/osd.c
index cf4a3a5..5fb27a3 100644
--- a/test/dm/osd.c
+++ b/test/dm/osd.c
@@ -130,8 +130,7 @@
return 0;
}
-
-DM_TEST(dm_test_osd_basics, UT_TESTF_SCAN_PDATA | UT_TESTF_SCAN_FDT);
+DM_TEST(dm_test_osd_basics, UTF_SCAN_PDATA | UTF_SCAN_FDT);
static int dm_test_osd_extended(struct unit_test_state *uts)
{
@@ -214,5 +213,4 @@
return 0;
}
-
-DM_TEST(dm_test_osd_extended, UT_TESTF_SCAN_PDATA | UT_TESTF_SCAN_FDT);
+DM_TEST(dm_test_osd_extended, UTF_SCAN_PDATA | UTF_SCAN_FDT);
diff --git a/test/dm/p2sb.c b/test/dm/p2sb.c
index 3ada1fc..4cc374e 100644
--- a/test/dm/p2sb.c
+++ b/test/dm/p2sb.c
@@ -24,4 +24,4 @@
return 0;
}
-DM_TEST(dm_test_p2sb_base, UT_TESTF_SCAN_PDATA | UT_TESTF_SCAN_FDT);
+DM_TEST(dm_test_p2sb_base, UTF_SCAN_PDATA | UTF_SCAN_FDT);
diff --git a/test/dm/panel.c b/test/dm/panel.c
index 8be7c39..ce835c9 100644
--- a/test/dm/panel.c
+++ b/test/dm/panel.c
@@ -76,4 +76,4 @@
return 0;
}
-DM_TEST(dm_test_panel, UT_TESTF_SCAN_PDATA | UT_TESTF_SCAN_FDT);
+DM_TEST(dm_test_panel, UTF_SCAN_PDATA | UTF_SCAN_FDT);
diff --git a/test/dm/part.c b/test/dm/part.c
index cabb31d..c5c4b3f 100644
--- a/test/dm/part.c
+++ b/test/dm/part.c
@@ -93,7 +93,7 @@
env_set("bootdevice", oldbootdevice);
return ret;
}
-DM_TEST(dm_test_part, UT_TESTF_SCAN_PDATA | UT_TESTF_SCAN_FDT);
+DM_TEST(dm_test_part, UTF_SCAN_PDATA | UTF_SCAN_FDT);
static int dm_test_part_bootable(struct unit_test_state *uts)
{
@@ -106,7 +106,7 @@
return 0;
}
-DM_TEST(dm_test_part_bootable, UT_TESTF_SCAN_FDT);
+DM_TEST(dm_test_part_bootable, UTF_SCAN_FDT);
static int do_get_info_test(struct unit_test_state *uts,
struct blk_desc *dev_desc, int part, int part_type,
@@ -193,4 +193,4 @@
return 0;
}
-DM_TEST(dm_test_part_get_info_by_type, UT_TESTF_SCAN_PDATA | UT_TESTF_SCAN_FDT);
+DM_TEST(dm_test_part_get_info_by_type, UTF_SCAN_PDATA | UTF_SCAN_FDT);
diff --git a/test/dm/pch.c b/test/dm/pch.c
index b37b856..88e924d 100644
--- a/test/dm/pch.c
+++ b/test/dm/pch.c
@@ -33,7 +33,7 @@
return 0;
}
-DM_TEST(dm_test_pch_base, UT_TESTF_SCAN_PDATA | UT_TESTF_SCAN_FDT);
+DM_TEST(dm_test_pch_base, UTF_SCAN_PDATA | UTF_SCAN_FDT);
/* Test sandbox PCH ioctl */
static int dm_test_pch_ioctl(struct unit_test_state *uts)
@@ -52,4 +52,4 @@
return 0;
}
-DM_TEST(dm_test_pch_ioctl, UT_TESTF_SCAN_PDATA | UT_TESTF_SCAN_FDT);
+DM_TEST(dm_test_pch_ioctl, UTF_SCAN_PDATA | UTF_SCAN_FDT);
diff --git a/test/dm/pci.c b/test/dm/pci.c
index 9b97f2e..6eb19f6 100644
--- a/test/dm/pci.c
+++ b/test/dm/pci.c
@@ -19,7 +19,7 @@
return 0;
}
-DM_TEST(dm_test_pci_base, UT_TESTF_SCAN_PDATA | UT_TESTF_SCAN_FDT);
+DM_TEST(dm_test_pci_base, UTF_SCAN_PDATA | UTF_SCAN_FDT);
/* Test that sandbox PCI bus numbering and device works correctly */
static int dm_test_pci_busdev(struct unit_test_state *uts)
@@ -54,7 +54,7 @@
return 0;
}
-DM_TEST(dm_test_pci_busdev, UT_TESTF_SCAN_PDATA | UT_TESTF_SCAN_FDT);
+DM_TEST(dm_test_pci_busdev, UTF_SCAN_PDATA | UTF_SCAN_FDT);
/* Test that we can use the swapcase device correctly */
static int dm_test_pci_swapcase(struct unit_test_state *uts)
@@ -107,7 +107,7 @@
return 0;
}
-DM_TEST(dm_test_pci_swapcase, UT_TESTF_SCAN_PDATA | UT_TESTF_SCAN_FDT);
+DM_TEST(dm_test_pci_swapcase, UTF_SCAN_PDATA | UTF_SCAN_FDT);
/* Test that we can dynamically bind the device driver correctly */
static int dm_test_pci_drvdata(struct unit_test_state *uts)
@@ -129,7 +129,7 @@
return 0;
}
-DM_TEST(dm_test_pci_drvdata, UT_TESTF_SCAN_PDATA | UT_TESTF_SCAN_FDT);
+DM_TEST(dm_test_pci_drvdata, UTF_SCAN_PDATA | UTF_SCAN_FDT);
/* Test that devices on PCI bus#2 can be accessed correctly */
static int dm_test_pci_mixed(struct unit_test_state *uts)
@@ -192,7 +192,7 @@
return 0;
}
-DM_TEST(dm_test_pci_mixed, UT_TESTF_SCAN_PDATA | UT_TESTF_SCAN_FDT);
+DM_TEST(dm_test_pci_mixed, UTF_SCAN_PDATA | UTF_SCAN_FDT);
/* Test looking up PCI capability and extended capability */
static int dm_test_pci_cap(struct unit_test_state *uts)
@@ -244,7 +244,7 @@
return 0;
}
-DM_TEST(dm_test_pci_cap, UT_TESTF_SCAN_PDATA | UT_TESTF_SCAN_FDT);
+DM_TEST(dm_test_pci_cap, UTF_SCAN_PDATA | UTF_SCAN_FDT);
/* Test looking up BARs in EA capability structure */
static int dm_test_pci_ea(struct unit_test_state *uts)
@@ -293,7 +293,7 @@
return 0;
}
-DM_TEST(dm_test_pci_ea, UT_TESTF_SCAN_PDATA | UT_TESTF_SCAN_FDT);
+DM_TEST(dm_test_pci_ea, UTF_SCAN_PDATA | UTF_SCAN_FDT);
/* Test the dev_read_addr_pci() function */
static int dm_test_pci_addr_flat(struct unit_test_state *uts)
@@ -318,14 +318,14 @@
return 0;
}
-DM_TEST(dm_test_pci_addr_flat, UT_TESTF_SCAN_PDATA | UT_TESTF_SCAN_FDT |
- UT_TESTF_FLAT_TREE);
+DM_TEST(dm_test_pci_addr_flat, UTF_SCAN_PDATA | UTF_SCAN_FDT |
+ UTF_FLAT_TREE);
/*
* Test the dev_read_addr_pci() function with livetree. That function is
* not currently fully implemented, in that it fails to return the BAR address.
* Once that is implemented this test can be removed and dm_test_pci_addr_flat()
- * can be used for both flattree and livetree by removing the UT_TESTF_FLAT_TREE
+ * can be used for both flattree and livetree by removing the UTF_FLAT_TREE
* flag above.
*/
static int dm_test_pci_addr_live(struct unit_test_state *uts)
@@ -343,8 +343,7 @@
return 0;
}
-DM_TEST(dm_test_pci_addr_live, UT_TESTF_SCAN_PDATA | UT_TESTF_SCAN_FDT |
- UT_TESTF_LIVE_TREE);
+DM_TEST(dm_test_pci_addr_live, UTF_SCAN_PDATA | UTF_SCAN_FDT | UTF_LIVE_TREE);
/* Test device_is_on_pci_bus() */
static int dm_test_pci_on_bus(struct unit_test_state *uts)
@@ -358,7 +357,7 @@
return 0;
}
-DM_TEST(dm_test_pci_on_bus, UT_TESTF_SCAN_PDATA | UT_TESTF_SCAN_FDT);
+DM_TEST(dm_test_pci_on_bus, UTF_SCAN_PDATA | UTF_SCAN_FDT);
/*
* Test support for multiple memory regions enabled via
@@ -380,7 +379,7 @@
return 0;
}
-DM_TEST(dm_test_pci_region_multi, UT_TESTF_SCAN_PDATA | UT_TESTF_SCAN_FDT);
+DM_TEST(dm_test_pci_region_multi, UTF_SCAN_PDATA | UTF_SCAN_FDT);
/*
* Test the translation of PCI bus addresses to physical addresses using the
@@ -433,7 +432,7 @@
return 0;
}
-DM_TEST(dm_test_pci_bus_to_phys, UT_TESTF_SCAN_PDATA | UT_TESTF_SCAN_FDT);
+DM_TEST(dm_test_pci_bus_to_phys, UTF_SCAN_PDATA | UTF_SCAN_FDT);
/*
* Test the translation of physical addresses to PCI bus addresses using the
@@ -486,4 +485,4 @@
return 0;
}
-DM_TEST(dm_test_pci_phys_to_bus, UT_TESTF_SCAN_PDATA | UT_TESTF_SCAN_FDT);
+DM_TEST(dm_test_pci_phys_to_bus, UTF_SCAN_PDATA | UTF_SCAN_FDT);
diff --git a/test/dm/pci_ep.c b/test/dm/pci_ep.c
index e82fc53..068b72a 100644
--- a/test/dm/pci_ep.c
+++ b/test/dm/pci_ep.c
@@ -59,5 +59,4 @@
ut_asserteq(sandbox_get_pci_ep_irq_count(bus), 10);
return 0;
}
-
-DM_TEST(dm_test_pci_ep_base, UT_TESTF_SCAN_PDATA | UT_TESTF_SCAN_FDT);
+DM_TEST(dm_test_pci_ep_base, UTF_SCAN_PDATA | UTF_SCAN_FDT);
diff --git a/test/dm/phy.c b/test/dm/phy.c
index d14117f..9b4cff6 100644
--- a/test/dm/phy.c
+++ b/test/dm/phy.c
@@ -68,7 +68,7 @@
return 0;
}
-DM_TEST(dm_test_phy_base, UT_TESTF_SCAN_PDATA | UT_TESTF_SCAN_FDT);
+DM_TEST(dm_test_phy_base, UTF_SCAN_PDATA | UTF_SCAN_FDT);
/* Test of the phy uclass using the sandbox phy driver operations */
static int dm_test_phy_ops(struct unit_test_state *uts)
@@ -140,7 +140,7 @@
return 0;
}
-DM_TEST(dm_test_phy_ops, UT_TESTF_SCAN_PDATA | UT_TESTF_SCAN_FDT);
+DM_TEST(dm_test_phy_ops, UTF_SCAN_PDATA | UTF_SCAN_FDT);
static int dm_test_phy_bulk(struct unit_test_state *uts)
{
@@ -173,7 +173,7 @@
return 0;
}
-DM_TEST(dm_test_phy_bulk, UT_TESTF_SCAN_PDATA | UT_TESTF_SCAN_FDT);
+DM_TEST(dm_test_phy_bulk, UTF_SCAN_PDATA | UTF_SCAN_FDT);
static int dm_test_phy_multi_exit(struct unit_test_state *uts)
{
@@ -232,7 +232,7 @@
return 0;
}
-DM_TEST(dm_test_phy_multi_exit, UT_TESTF_SCAN_PDATA | UT_TESTF_SCAN_FDT);
+DM_TEST(dm_test_phy_multi_exit, UTF_SCAN_PDATA | UTF_SCAN_FDT);
static int dm_test_phy_setup(struct unit_test_state *uts)
{
@@ -261,4 +261,4 @@
return 0;
}
-DM_TEST(dm_test_phy_setup, UT_TESTF_SCAN_PDATA | UT_TESTF_SCAN_FDT);
+DM_TEST(dm_test_phy_setup, UTF_SCAN_PDATA | UTF_SCAN_FDT);
diff --git a/test/dm/phys2bus.c b/test/dm/phys2bus.c
index 1ee2150..0f30c7e 100644
--- a/test/dm/phys2bus.c
+++ b/test/dm/phys2bus.c
@@ -33,4 +33,4 @@
return 0;
}
-DM_TEST(dm_test_phys_to_bus, UT_TESTF_SCAN_PDATA | UT_TESTF_SCAN_FDT);
+DM_TEST(dm_test_phys_to_bus, UTF_SCAN_PDATA | UTF_SCAN_FDT);
diff --git a/test/dm/pinmux.c b/test/dm/pinmux.c
index cfbe3ef..92e5bc8 100644
--- a/test/dm/pinmux.c
+++ b/test/dm/pinmux.c
@@ -68,8 +68,7 @@
return 0;
}
-
-DM_TEST(dm_test_pinmux, UT_TESTF_SCAN_FDT);
+DM_TEST(dm_test_pinmux, UTF_SCAN_FDT);
static int dm_test_pinctrl_single(struct unit_test_state *uts)
{
@@ -143,5 +142,4 @@
ut_asserteq(-EINVAL, ret);
return 0;
}
-
-DM_TEST(dm_test_pinctrl_single, UT_TESTF_SCAN_FDT);
+DM_TEST(dm_test_pinctrl_single, UTF_SCAN_FDT);
diff --git a/test/dm/pmc.c b/test/dm/pmc.c
index bbad1ee..0012279 100644
--- a/test/dm/pmc.c
+++ b/test/dm/pmc.c
@@ -29,4 +29,4 @@
return 0;
}
-DM_TEST(dm_test_pmc_base, UT_TESTF_SCAN_PDATA | UT_TESTF_SCAN_FDT);
+DM_TEST(dm_test_pmc_base, UTF_SCAN_PDATA | UTF_SCAN_FDT);
diff --git a/test/dm/pmic.c b/test/dm/pmic.c
index 53a6f03..70dd18f 100644
--- a/test/dm/pmic.c
+++ b/test/dm/pmic.c
@@ -43,7 +43,7 @@
return 0;
}
-DM_TEST(dm_test_power_pmic_get, UT_TESTF_SCAN_FDT);
+DM_TEST(dm_test_power_pmic_get, UTF_SCAN_FDT);
/* PMIC get method - MC34708 - for 3 bytes transmission */
static int dm_test_power_pmic_mc34708_get(struct unit_test_state *uts)
@@ -52,8 +52,7 @@
return 0;
}
-
-DM_TEST(dm_test_power_pmic_mc34708_get, UT_TESTF_SCAN_FDT);
+DM_TEST(dm_test_power_pmic_mc34708_get, UTF_SCAN_FDT);
/* Test PMIC I/O */
static int dm_test_power_pmic_io(struct unit_test_state *uts)
@@ -82,7 +81,7 @@
return 0;
}
-DM_TEST(dm_test_power_pmic_io, UT_TESTF_SCAN_FDT);
+DM_TEST(dm_test_power_pmic_io, UTF_SCAN_FDT);
#define MC34708_PMIC_REG_COUNT 64
#define MC34708_PMIC_TEST_VAL 0x125534
@@ -99,8 +98,7 @@
return 0;
}
-
-DM_TEST(dm_test_power_pmic_mc34708_regs_check, UT_TESTF_SCAN_FDT);
+DM_TEST(dm_test_power_pmic_mc34708_regs_check, UTF_SCAN_FDT);
static int dm_test_power_pmic_mc34708_rw_val(struct unit_test_state *uts)
{
@@ -126,5 +124,4 @@
return 0;
}
-
-DM_TEST(dm_test_power_pmic_mc34708_rw_val, UT_TESTF_SCAN_FDT);
+DM_TEST(dm_test_power_pmic_mc34708_rw_val, UTF_SCAN_FDT);
diff --git a/test/dm/power-domain.c b/test/dm/power-domain.c
index 120a905..896cf5b 100644
--- a/test/dm/power-domain.c
+++ b/test/dm/power-domain.c
@@ -45,4 +45,4 @@
return 0;
}
-DM_TEST(dm_test_power_domain, UT_TESTF_SCAN_FDT);
+DM_TEST(dm_test_power_domain, UTF_SCAN_FDT);
diff --git a/test/dm/pwm.c b/test/dm/pwm.c
index 8013334..5ccd8bc 100644
--- a/test/dm/pwm.c
+++ b/test/dm/pwm.c
@@ -41,4 +41,4 @@
return 0;
}
-DM_TEST(dm_test_pwm_base, UT_TESTF_SCAN_PDATA | UT_TESTF_SCAN_FDT);
+DM_TEST(dm_test_pwm_base, UTF_SCAN_PDATA | UTF_SCAN_FDT);
diff --git a/test/dm/qfw.c b/test/dm/qfw.c
index 3c35416..b6be5c5 100644
--- a/test/dm/qfw.c
+++ b/test/dm/qfw.c
@@ -23,8 +23,7 @@
return 0;
}
-
-DM_TEST(dm_test_qfw_cpus, UT_TESTF_SCAN_PDATA);
+DM_TEST(dm_test_qfw_cpus, UTF_SCAN_PDATA);
static int dm_test_qfw_firmware_list(struct unit_test_state *uts)
{
@@ -37,5 +36,4 @@
return 0;
}
-
-DM_TEST(dm_test_qfw_firmware_list, UT_TESTF_SCAN_PDATA);
+DM_TEST(dm_test_qfw_firmware_list, UTF_SCAN_PDATA);
diff --git a/test/dm/ram.c b/test/dm/ram.c
index 188c7c3..f3710b1 100644
--- a/test/dm/ram.c
+++ b/test/dm/ram.c
@@ -25,4 +25,4 @@
return 0;
}
-DM_TEST(dm_test_ram_base, UT_TESTF_SCAN_PDATA | UT_TESTF_SCAN_FDT);
+DM_TEST(dm_test_ram_base, UTF_SCAN_PDATA | UTF_SCAN_FDT);
diff --git a/test/dm/read.c b/test/dm/read.c
index 4ecf181..0aa8221 100644
--- a/test/dm/read.c
+++ b/test/dm/read.c
@@ -45,4 +45,4 @@
return 0;
}
-DM_TEST(dm_test_dma_ranges, UT_TESTF_SCAN_PDATA | UT_TESTF_SCAN_FDT);
+DM_TEST(dm_test_dma_ranges, UTF_SCAN_PDATA | UTF_SCAN_FDT);
diff --git a/test/dm/reboot-mode.c b/test/dm/reboot-mode.c
index 160b4da..9a3b2bf 100644
--- a/test/dm/reboot-mode.c
+++ b/test/dm/reboot-mode.c
@@ -39,9 +39,8 @@
return 0;
}
-
DM_TEST(dm_test_reboot_mode_gpio,
- UT_TESTF_PROBE_TEST | UT_TESTF_SCAN_FDT | UT_TESTF_FLAT_TREE);
+ UTF_PROBE_TEST | UTF_SCAN_FDT | UTF_FLAT_TREE);
static int dm_test_reboot_mode_rtc(struct unit_test_state *uts)
{
@@ -65,6 +64,5 @@
return 0;
}
-
DM_TEST(dm_test_reboot_mode_rtc,
- UT_TESTF_PROBE_TEST | UT_TESTF_SCAN_FDT | UT_TESTF_FLAT_TREE);
+ UTF_PROBE_TEST | UTF_SCAN_FDT | UTF_FLAT_TREE);
diff --git a/test/dm/regmap.c b/test/dm/regmap.c
index 1398f8f..5024b47 100644
--- a/test/dm/regmap.c
+++ b/test/dm/regmap.c
@@ -69,7 +69,7 @@
return 0;
}
-DM_TEST(dm_test_regmap_base, UT_TESTF_SCAN_PDATA | UT_TESTF_SCAN_FDT);
+DM_TEST(dm_test_regmap_base, UTF_SCAN_PDATA | UTF_SCAN_FDT);
/* Test we can access a regmap through syscon */
static int dm_test_regmap_syscon(struct unit_test_state *uts)
@@ -94,8 +94,7 @@
return 0;
}
-
-DM_TEST(dm_test_regmap_syscon, UT_TESTF_SCAN_PDATA | UT_TESTF_SCAN_FDT);
+DM_TEST(dm_test_regmap_syscon, UTF_SCAN_PDATA | UTF_SCAN_FDT);
/* Read/Write/Modify test */
static int dm_test_regmap_rw(struct unit_test_state *uts)
@@ -128,8 +127,7 @@
return 0;
}
-
-DM_TEST(dm_test_regmap_rw, UT_TESTF_SCAN_PDATA | UT_TESTF_SCAN_FDT);
+DM_TEST(dm_test_regmap_rw, UTF_SCAN_PDATA | UTF_SCAN_FDT);
/* Get/Set test */
static int dm_test_regmap_getset(struct unit_test_state *uts)
@@ -159,8 +157,7 @@
return 0;
}
-
-DM_TEST(dm_test_regmap_getset, UT_TESTF_SCAN_PDATA | UT_TESTF_SCAN_FDT);
+DM_TEST(dm_test_regmap_getset, UTF_SCAN_PDATA | UTF_SCAN_FDT);
/* Read polling test */
static int dm_test_regmap_poll(struct unit_test_state *uts)
@@ -187,8 +184,7 @@
return 0;
}
-
-DM_TEST(dm_test_regmap_poll, UT_TESTF_SCAN_PDATA | UT_TESTF_SCAN_FDT);
+DM_TEST(dm_test_regmap_poll, UTF_SCAN_PDATA | UTF_SCAN_FDT);
struct regmaptest_priv {
struct regmap *cfg_regmap; /* For testing regmap_config options. */
@@ -324,7 +320,7 @@
return 0;
}
-DM_TEST(dm_test_devm_regmap, UT_TESTF_SCAN_PDATA | UT_TESTF_SCAN_FDT);
+DM_TEST(dm_test_devm_regmap, UTF_SCAN_PDATA | UTF_SCAN_FDT);
static int test_one_field(struct unit_test_state *uts,
struct regmap *regmap,
@@ -383,4 +379,4 @@
return 0;
}
-DM_TEST(dm_test_devm_regmap_field, UT_TESTF_SCAN_PDATA | UT_TESTF_SCAN_FDT);
+DM_TEST(dm_test_devm_regmap_field, UTF_SCAN_PDATA | UTF_SCAN_FDT);
diff --git a/test/dm/regulator.c b/test/dm/regulator.c
index 9e45fd1..532bbd8 100644
--- a/test/dm/regulator.c
+++ b/test/dm/regulator.c
@@ -89,7 +89,7 @@
return 0;
}
-DM_TEST(dm_test_power_regulator_get, UT_TESTF_SCAN_FDT);
+DM_TEST(dm_test_power_regulator_get, UTF_SCAN_FDT);
/* Test regulator set and get Voltage method */
static int dm_test_power_regulator_set_get_voltage(struct unit_test_state *uts)
@@ -116,7 +116,7 @@
return 0;
}
-DM_TEST(dm_test_power_regulator_set_get_voltage, UT_TESTF_SCAN_FDT);
+DM_TEST(dm_test_power_regulator_set_get_voltage, UTF_SCAN_FDT);
/* Test regulator set and get Current method */
static int dm_test_power_regulator_set_get_current(struct unit_test_state *uts)
@@ -155,7 +155,7 @@
return 0;
}
-DM_TEST(dm_test_power_regulator_set_get_current, UT_TESTF_SCAN_FDT);
+DM_TEST(dm_test_power_regulator_set_get_current, UTF_SCAN_FDT);
/* Test regulator set and get Enable method */
static int dm_test_power_regulator_set_get_enable(struct unit_test_state *uts)
@@ -174,7 +174,7 @@
return 0;
}
-DM_TEST(dm_test_power_regulator_set_get_enable, UT_TESTF_SCAN_FDT);
+DM_TEST(dm_test_power_regulator_set_get_enable, UTF_SCAN_FDT);
/* Test regulator set and get enable if allowed method */
static
@@ -195,7 +195,7 @@
return 0;
}
-DM_TEST(dm_test_power_regulator_set_enable_if_allowed, UT_TESTF_SCAN_FDT);
+DM_TEST(dm_test_power_regulator_set_enable_if_allowed, UTF_SCAN_FDT);
/* Test regulator set and get mode method */
static int dm_test_power_regulator_set_get_mode(struct unit_test_state *uts)
@@ -214,7 +214,7 @@
return 0;
}
-DM_TEST(dm_test_power_regulator_set_get_mode, UT_TESTF_SCAN_FDT);
+DM_TEST(dm_test_power_regulator_set_get_mode, UTF_SCAN_FDT);
/* Test regulator set and get suspend Voltage method */
static int dm_test_power_regulator_set_get_suspend_voltage(struct unit_test_state *uts)
@@ -244,7 +244,7 @@
}
return 0;
}
-DM_TEST(dm_test_power_regulator_set_get_suspend_voltage, UT_TESTF_SCAN_FDT);
+DM_TEST(dm_test_power_regulator_set_get_suspend_voltage, UTF_SCAN_FDT);
/* Test regulator set and get suspend Enable method */
static int dm_test_power_regulator_set_get_suspend_enable(struct unit_test_state *uts)
@@ -271,7 +271,7 @@
}
return 0;
}
-DM_TEST(dm_test_power_regulator_set_get_suspend_enable, UT_TESTF_SCAN_FDT);
+DM_TEST(dm_test_power_regulator_set_get_suspend_enable, UTF_SCAN_FDT);
/* Test regulator autoset method */
static int dm_test_power_regulator_autoset(struct unit_test_state *uts)
@@ -304,7 +304,7 @@
return 0;
}
-DM_TEST(dm_test_power_regulator_autoset, UT_TESTF_SCAN_FDT);
+DM_TEST(dm_test_power_regulator_autoset, UTF_SCAN_FDT);
/*
* Struct setting: to keep the expected output settings.
@@ -400,4 +400,4 @@
return 0;
}
-DM_TEST(dm_test_power_regulator_autoset_list, UT_TESTF_SCAN_FDT);
+DM_TEST(dm_test_power_regulator_autoset_list, UTF_SCAN_FDT);
diff --git a/test/dm/remoteproc.c b/test/dm/remoteproc.c
index 444c4dc..921314b 100644
--- a/test/dm/remoteproc.c
+++ b/test/dm/remoteproc.c
@@ -68,7 +68,7 @@
return 0;
}
-DM_TEST(dm_test_remoteproc_base, UT_TESTF_SCAN_PDATA | UT_TESTF_SCAN_FDT);
+DM_TEST(dm_test_remoteproc_base, UTF_SCAN_PDATA | UTF_SCAN_FDT);
#define DEVICE_TO_PHYSICAL_OFFSET 0x1000
/**
@@ -256,4 +256,4 @@
return 0;
}
-DM_TEST(dm_test_remoteproc_elf, UT_TESTF_SCAN_PDATA | UT_TESTF_SCAN_FDT);
+DM_TEST(dm_test_remoteproc_elf, UTF_SCAN_PDATA | UTF_SCAN_FDT);
diff --git a/test/dm/reset.c b/test/dm/reset.c
index d3158bf..dceb6a1 100644
--- a/test/dm/reset.c
+++ b/test/dm/reset.c
@@ -66,8 +66,7 @@
return 0;
}
-
-DM_TEST(dm_test_reset_base, UT_TESTF_SCAN_FDT);
+DM_TEST(dm_test_reset_base, UTF_SCAN_FDT);
static int dm_test_reset(struct unit_test_state *uts)
{
@@ -94,7 +93,7 @@
return 0;
}
-DM_TEST(dm_test_reset, UT_TESTF_SCAN_FDT);
+DM_TEST(dm_test_reset, UTF_SCAN_FDT);
static int dm_test_reset_devm(struct unit_test_state *uts)
{
@@ -119,7 +118,7 @@
return 0;
}
-DM_TEST(dm_test_reset_devm, UT_TESTF_SCAN_FDT);
+DM_TEST(dm_test_reset_devm, UTF_SCAN_FDT);
static int dm_test_reset_bulk(struct unit_test_state *uts)
{
@@ -149,7 +148,7 @@
return 0;
}
-DM_TEST(dm_test_reset_bulk, UT_TESTF_SCAN_FDT);
+DM_TEST(dm_test_reset_bulk, UTF_SCAN_FDT);
static int dm_test_reset_bulk_devm(struct unit_test_state *uts)
{
@@ -181,4 +180,4 @@
return 0;
}
-DM_TEST(dm_test_reset_bulk_devm, UT_TESTF_SCAN_FDT);
+DM_TEST(dm_test_reset_bulk_devm, UTF_SCAN_FDT);
diff --git a/test/dm/rkmtd.c b/test/dm/rkmtd.c
index 3dc9ca1..d1ca5d1 100644
--- a/test/dm/rkmtd.c
+++ b/test/dm/rkmtd.c
@@ -85,7 +85,7 @@
return 0;
}
-DM_TEST(dm_test_rkmtd, UT_TESTF_SCAN_FDT);
+DM_TEST(dm_test_rkmtd, UTF_SCAN_FDT);
/* Reusing the same label should work */
static int dm_test_rkmtd_dup(struct unit_test_state *uts)
@@ -112,7 +112,7 @@
return 0;
}
-DM_TEST(dm_test_rkmtd_dup, UT_TESTF_SCAN_FDT);
+DM_TEST(dm_test_rkmtd_dup, UTF_SCAN_FDT);
/* Basic test of the 'rkmtd' command */
static int dm_test_rkmtd_cmd(struct unit_test_state *uts)
@@ -196,4 +196,4 @@
return 0;
}
-DM_TEST(dm_test_rkmtd_cmd, UT_TESTF_SCAN_FDT | UT_TESTF_CONSOLE_REC);
+DM_TEST(dm_test_rkmtd_cmd, UTF_SCAN_FDT | UTF_CONSOLE);
diff --git a/test/dm/rng.c b/test/dm/rng.c
index c8ed6ca..d7ef072 100644
--- a/test/dm/rng.c
+++ b/test/dm/rng.c
@@ -23,7 +23,7 @@
return 0;
}
-DM_TEST(dm_test_rng_read, UT_TESTF_SCAN_PDATA | UT_TESTF_SCAN_FDT);
+DM_TEST(dm_test_rng_read, UTF_SCAN_PDATA | UTF_SCAN_FDT);
/* Test the rng command */
static int dm_test_rng_cmd(struct unit_test_state *uts)
@@ -33,8 +33,6 @@
ut_assertok(uclass_get_device(UCLASS_RNG, 0, &dev));
ut_assertnonnull(dev);
- ut_assertok(console_record_reset_enable());
-
run_command("rng", 0);
ut_assert_nextlinen("00000000:");
ut_assert_nextlinen("00000010:");
@@ -52,4 +50,4 @@
return 0;
}
-DM_TEST(dm_test_rng_cmd, UT_TESTF_SCAN_PDATA | UT_TESTF_SCAN_FDT | UT_TESTF_CONSOLE_REC);
+DM_TEST(dm_test_rng_cmd, UTF_SCAN_PDATA | UTF_SCAN_FDT | UTF_CONSOLE);
diff --git a/test/dm/rtc.c b/test/dm/rtc.c
index a8aa419..88f080b 100644
--- a/test/dm/rtc.c
+++ b/test/dm/rtc.c
@@ -27,7 +27,7 @@
return 0;
}
-DM_TEST(dm_test_rtc_base, UT_TESTF_SCAN_PDATA | UT_TESTF_SCAN_FDT);
+DM_TEST(dm_test_rtc_base, UTF_SCAN_PDATA | UTF_SCAN_FDT);
static void show_time(const char *msg, struct rtc_time *time)
{
@@ -142,7 +142,7 @@
return 0;
}
-DM_TEST(dm_test_rtc_set_get, UT_TESTF_SCAN_PDATA | UT_TESTF_SCAN_FDT);
+DM_TEST(dm_test_rtc_set_get, UTF_SCAN_PDATA | UTF_SCAN_FDT);
static int dm_test_rtc_read_write(struct unit_test_state *uts)
{
@@ -186,13 +186,11 @@
return 0;
}
-DM_TEST(dm_test_rtc_read_write, UT_TESTF_SCAN_PDATA | UT_TESTF_SCAN_FDT);
+DM_TEST(dm_test_rtc_read_write, UTF_SCAN_PDATA | UTF_SCAN_FDT);
/* Test 'rtc list' command */
static int dm_test_rtc_cmd_list(struct unit_test_state *uts)
{
- console_record_reset();
-
run_command("rtc list", 0);
ut_assert_nextline("RTC #0 - rtc@43");
ut_assert_nextline("RTC #1 - rtc@61");
@@ -200,13 +198,11 @@
return 0;
}
-DM_TEST(dm_test_rtc_cmd_list, UT_TESTF_SCAN_PDATA | UT_TESTF_SCAN_FDT);
+DM_TEST(dm_test_rtc_cmd_list, UTF_SCAN_PDATA | UTF_SCAN_FDT | UTF_CONSOLE);
/* Test 'rtc read' and 'rtc write' commands */
static int dm_test_rtc_cmd_rw(struct unit_test_state *uts)
{
- console_record_reset();
-
run_command("rtc dev 0", 0);
ut_assert_nextline("RTC #0 - rtc@43");
ut_assert_console_end();
@@ -243,7 +239,7 @@
return 0;
}
-DM_TEST(dm_test_rtc_cmd_rw, UT_TESTF_SCAN_PDATA | UT_TESTF_SCAN_FDT);
+DM_TEST(dm_test_rtc_cmd_rw, UTF_SCAN_PDATA | UTF_SCAN_FDT | UTF_CONSOLE);
/* Reset the time */
static int dm_test_rtc_reset(struct unit_test_state *uts)
@@ -280,7 +276,7 @@
return 0;
}
-DM_TEST(dm_test_rtc_reset, UT_TESTF_SCAN_PDATA | UT_TESTF_SCAN_FDT);
+DM_TEST(dm_test_rtc_reset, UTF_SCAN_PDATA | UTF_SCAN_FDT);
/* Check that two RTC devices can be used independently */
static int dm_test_rtc_dual(struct unit_test_state *uts)
@@ -312,4 +308,4 @@
return 0;
}
-DM_TEST(dm_test_rtc_dual, UT_TESTF_SCAN_PDATA | UT_TESTF_SCAN_FDT);
+DM_TEST(dm_test_rtc_dual, UTF_SCAN_PDATA | UTF_SCAN_FDT);
diff --git a/test/dm/scmi.c b/test/dm/scmi.c
index c9a0352..3655594 100644
--- a/test/dm/scmi.c
+++ b/test/dm/scmi.c
@@ -95,7 +95,7 @@
return ret;
}
-DM_TEST(dm_test_scmi_sandbox_agent, UT_TESTF_SCAN_FDT);
+DM_TEST(dm_test_scmi_sandbox_agent, UTF_SCAN_FDT);
static int dm_test_scmi_base(struct unit_test_state *uts)
{
@@ -202,8 +202,7 @@
return 0;
}
-
-DM_TEST(dm_test_scmi_base, UT_TESTF_SCAN_FDT);
+DM_TEST(dm_test_scmi_base, UTF_SCAN_FDT);
static int dm_test_scmi_cmd(struct unit_test_state *uts)
{
@@ -282,8 +281,7 @@
return 0;
}
-
-DM_TEST(dm_test_scmi_cmd, UT_TESTF_SCAN_FDT);
+DM_TEST(dm_test_scmi_cmd, UTF_SCAN_FDT | UTF_CONSOLE);
static int dm_test_scmi_power_domains(struct unit_test_state *uts)
{
@@ -388,8 +386,7 @@
return release_sandbox_scmi_test_devices(uts, dev);
}
-
-DM_TEST(dm_test_scmi_power_domains, UT_TESTF_SCAN_FDT);
+DM_TEST(dm_test_scmi_power_domains, UTF_SCAN_FDT);
static int dm_test_scmi_clocks(struct unit_test_state *uts)
{
@@ -458,7 +455,7 @@
return release_sandbox_scmi_test_devices(uts, dev);
}
-DM_TEST(dm_test_scmi_clocks, UT_TESTF_SCAN_FDT);
+DM_TEST(dm_test_scmi_clocks, UTF_SCAN_FDT);
static int dm_test_scmi_resets(struct unit_test_state *uts)
{
@@ -496,7 +493,7 @@
return release_sandbox_scmi_test_devices(uts, dev);
}
-DM_TEST(dm_test_scmi_resets, UT_TESTF_SCAN_FDT);
+DM_TEST(dm_test_scmi_resets, UTF_SCAN_FDT);
static int dm_test_scmi_voltage_domains(struct unit_test_state *uts)
{
@@ -551,4 +548,4 @@
return release_sandbox_scmi_test_devices(uts, dev);
}
-DM_TEST(dm_test_scmi_voltage_domains, UT_TESTF_SCAN_FDT);
+DM_TEST(dm_test_scmi_voltage_domains, UTF_SCAN_FDT);
diff --git a/test/dm/scsi.c b/test/dm/scsi.c
index 5180159..fbc36a7 100644
--- a/test/dm/scsi.c
+++ b/test/dm/scsi.c
@@ -35,4 +35,4 @@
return 0;
}
-DM_TEST(dm_test_scsi_base, UT_TESTF_SCAN_PDATA | UT_TESTF_SCAN_FDT);
+DM_TEST(dm_test_scsi_base, UTF_SCAN_PDATA | UTF_SCAN_FDT);
diff --git a/test/dm/serial.c b/test/dm/serial.c
index 34c0d4d..4acb14f 100644
--- a/test/dm/serial.c
+++ b/test/dm/serial.c
@@ -87,5 +87,4 @@
return 0;
}
-
-DM_TEST(dm_test_serial, UT_TESTF_SCAN_FDT);
+DM_TEST(dm_test_serial, UTF_SCAN_FDT);
diff --git a/test/dm/sf.c b/test/dm/sf.c
index 0e3a0f1..3684d02 100644
--- a/test/dm/sf.c
+++ b/test/dm/sf.c
@@ -72,7 +72,7 @@
return 0;
}
-DM_TEST(dm_test_spi_flash, UT_TESTF_SCAN_PDATA | UT_TESTF_SCAN_FDT);
+DM_TEST(dm_test_spi_flash, UTF_SCAN_PDATA | UTF_SCAN_FDT);
/* Functional test that sandbox SPI flash works correctly */
static int dm_test_spi_flash_func(struct unit_test_state *uts)
@@ -100,4 +100,4 @@
return 0;
}
-DM_TEST(dm_test_spi_flash_func, UT_TESTF_SCAN_PDATA | UT_TESTF_SCAN_FDT);
+DM_TEST(dm_test_spi_flash_func, UTF_SCAN_PDATA | UTF_SCAN_FDT);
diff --git a/test/dm/simple-bus.c b/test/dm/simple-bus.c
index 8a730ba..d953483 100644
--- a/test/dm/simple-bus.c
+++ b/test/dm/simple-bus.c
@@ -29,4 +29,4 @@
return 0;
}
-DM_TEST(dm_test_simple_bus, UT_TESTF_SCAN_FDT | UT_TESTF_FLAT_TREE);
+DM_TEST(dm_test_simple_bus, UTF_SCAN_FDT | UTF_FLAT_TREE);
diff --git a/test/dm/simple-pm-bus.c b/test/dm/simple-pm-bus.c
index 9949cb3..8ae5e77 100644
--- a/test/dm/simple-pm-bus.c
+++ b/test/dm/simple-pm-bus.c
@@ -41,4 +41,4 @@
return 0;
}
-DM_TEST(dm_test_simple_pm_bus, UT_TESTF_SCAN_FDT);
+DM_TEST(dm_test_simple_pm_bus, UTF_SCAN_FDT);
diff --git a/test/dm/sm.c b/test/dm/sm.c
index 4d95c2a..cf4dab6 100644
--- a/test/dm/sm.c
+++ b/test/dm/sm.c
@@ -60,5 +60,4 @@
return 0;
}
-
-DM_TEST(dm_test_sm, UT_TESTF_SCAN_FDT);
+DM_TEST(dm_test_sm, UTF_SCAN_FDT);
diff --git a/test/dm/smem.c b/test/dm/smem.c
index adcbfe5..89e74cc 100644
--- a/test/dm/smem.c
+++ b/test/dm/smem.c
@@ -23,4 +23,4 @@
return 0;
}
-DM_TEST(dm_test_smem_base, UT_TESTF_SCAN_PDATA | UT_TESTF_SCAN_FDT);
+DM_TEST(dm_test_smem_base, UTF_SCAN_PDATA | UTF_SCAN_FDT);
diff --git a/test/dm/soc.c b/test/dm/soc.c
index cb0ac15..a6b82e5 100644
--- a/test/dm/soc.c
+++ b/test/dm/soc.c
@@ -115,5 +115,4 @@
return 0;
}
-
-DM_TEST(dm_test_soc, UT_TESTF_SCAN_FDT);
+DM_TEST(dm_test_soc, UTF_SCAN_FDT);
diff --git a/test/dm/sound.c b/test/dm/sound.c
index f4e6215..7b55567 100644
--- a/test/dm/sound.c
+++ b/test/dm/sound.c
@@ -43,7 +43,7 @@
return 0;
}
-DM_TEST(dm_test_sound, UT_TESTF_SCAN_PDATA | UT_TESTF_SCAN_FDT);
+DM_TEST(dm_test_sound, UTF_SCAN_PDATA | UTF_SCAN_FDT);
/* Test of the 'start beep' operations */
static int dm_test_sound_beep(struct unit_test_state *uts)
@@ -64,4 +64,4 @@
return 0;
}
-DM_TEST(dm_test_sound_beep, UT_TESTF_SCAN_PDATA | UT_TESTF_SCAN_FDT);
+DM_TEST(dm_test_sound_beep, UTF_SCAN_PDATA | UTF_SCAN_FDT);
diff --git a/test/dm/spi.c b/test/dm/spi.c
index 1ab2dd7..249a923 100644
--- a/test/dm/spi.c
+++ b/test/dm/spi.c
@@ -89,7 +89,7 @@
return 0;
}
-DM_TEST(dm_test_spi_find, UT_TESTF_SCAN_PDATA | UT_TESTF_SCAN_FDT);
+DM_TEST(dm_test_spi_find, UTF_SCAN_PDATA | UTF_SCAN_FDT);
/* dm_test_spi_switch_slaves - Helper function to check whether spi_claim_bus
* operates correctly with two spi slaves.
@@ -168,7 +168,7 @@
return 0;
}
-DM_TEST(dm_test_spi_claim_bus, UT_TESTF_SCAN_PDATA | UT_TESTF_SCAN_FDT);
+DM_TEST(dm_test_spi_claim_bus, UTF_SCAN_PDATA | UTF_SCAN_FDT);
/* Test that sandbox SPI works correctly */
static int dm_test_spi_xfer(struct unit_test_state *uts)
@@ -199,4 +199,4 @@
return 0;
}
-DM_TEST(dm_test_spi_xfer, UT_TESTF_SCAN_PDATA | UT_TESTF_SCAN_FDT);
+DM_TEST(dm_test_spi_xfer, UTF_SCAN_PDATA | UTF_SCAN_FDT);
diff --git a/test/dm/spmi.c b/test/dm/spmi.c
index ee444f3..d706fc9 100644
--- a/test/dm/spmi.c
+++ b/test/dm/spmi.c
@@ -43,7 +43,7 @@
return 0;
}
-DM_TEST(dm_test_spmi_probe, UT_TESTF_SCAN_FDT);
+DM_TEST(dm_test_spmi_probe, UTF_SCAN_FDT);
/* Test if it's possible to read bus directly and indirectly */
static int dm_test_spmi_access(struct unit_test_state *uts)
@@ -68,7 +68,7 @@
return 0;
}
-DM_TEST(dm_test_spmi_access, UT_TESTF_SCAN_FDT);
+DM_TEST(dm_test_spmi_access, UTF_SCAN_FDT);
/* Test if it's possible to access GPIO that should be in pmic */
static int dm_test_spmi_access_peripheral(struct unit_test_state *uts)
@@ -108,4 +108,4 @@
return 0;
}
-DM_TEST(dm_test_spmi_access_peripheral, UT_TESTF_SCAN_FDT);
+DM_TEST(dm_test_spmi_access_peripheral, UTF_SCAN_FDT);
diff --git a/test/dm/syscon-reset.c b/test/dm/syscon-reset.c
index ba19504..5f51c1b 100644
--- a/test/dm/syscon-reset.c
+++ b/test/dm/syscon-reset.c
@@ -55,4 +55,4 @@
return 0;
}
-DM_TEST(dm_test_syscon_reset, UT_TESTF_SCAN_FDT);
+DM_TEST(dm_test_syscon_reset, UTF_SCAN_FDT);
diff --git a/test/dm/syscon.c b/test/dm/syscon.c
index 04d324e..9855859 100644
--- a/test/dm/syscon.c
+++ b/test/dm/syscon.c
@@ -28,7 +28,7 @@
return 0;
}
-DM_TEST(dm_test_syscon_base, UT_TESTF_SCAN_PDATA | UT_TESTF_SCAN_FDT);
+DM_TEST(dm_test_syscon_base, UTF_SCAN_PDATA | UTF_SCAN_FDT);
/* Test system controller finding */
static int dm_test_syscon_by_driver_data(struct unit_test_state *uts)
@@ -45,7 +45,7 @@
return 0;
}
-DM_TEST(dm_test_syscon_by_driver_data, UT_TESTF_SCAN_PDATA | UT_TESTF_SCAN_FDT);
+DM_TEST(dm_test_syscon_by_driver_data, UTF_SCAN_PDATA | UTF_SCAN_FDT);
/* Test system controller by phandle */
static int dm_test_syscon_by_phandle(struct unit_test_state *uts)
@@ -80,4 +80,4 @@
return 0;
}
-DM_TEST(dm_test_syscon_by_phandle, UT_TESTF_SCAN_PDATA | UT_TESTF_SCAN_FDT);
+DM_TEST(dm_test_syscon_by_phandle, UTF_SCAN_PDATA | UTF_SCAN_FDT);
diff --git a/test/dm/sysinfo-gpio.c b/test/dm/sysinfo-gpio.c
index 24a99da..155da3b 100644
--- a/test/dm/sysinfo-gpio.c
+++ b/test/dm/sysinfo-gpio.c
@@ -65,4 +65,4 @@
return 0;
}
-DM_TEST(dm_test_sysinfo_gpio, UT_TESTF_SCAN_PDATA | UT_TESTF_SCAN_FDT);
+DM_TEST(dm_test_sysinfo_gpio, UTF_SCAN_PDATA | UTF_SCAN_FDT);
diff --git a/test/dm/sysinfo.c b/test/dm/sysinfo.c
index 7444a58..6c0d2d7 100644
--- a/test/dm/sysinfo.c
+++ b/test/dm/sysinfo.c
@@ -59,5 +59,4 @@
return 0;
}
-
-DM_TEST(dm_test_sysinfo, UT_TESTF_SCAN_PDATA | UT_TESTF_SCAN_FDT);
+DM_TEST(dm_test_sysinfo, UTF_SCAN_PDATA | UTF_SCAN_FDT);
diff --git a/test/dm/sysreset.c b/test/dm/sysreset.c
index f3a859b..8431aaa 100644
--- a/test/dm/sysreset.c
+++ b/test/dm/sysreset.c
@@ -45,7 +45,7 @@
return 0;
}
-DM_TEST(dm_test_sysreset_base, UT_TESTF_SCAN_PDATA | UT_TESTF_SCAN_FDT);
+DM_TEST(dm_test_sysreset_base, UTF_SCAN_PDATA | UTF_SCAN_FDT);
static int dm_test_sysreset_get_status(struct unit_test_state *uts)
{
@@ -64,7 +64,7 @@
return 0;
}
-DM_TEST(dm_test_sysreset_get_status, UT_TESTF_SCAN_PDATA | UT_TESTF_SCAN_FDT);
+DM_TEST(dm_test_sysreset_get_status, UTF_SCAN_PDATA | UTF_SCAN_FDT);
/* Test that we can walk through the sysreset devices */
static int dm_test_sysreset_walk(struct unit_test_state *uts)
@@ -95,7 +95,7 @@
return 0;
}
-DM_TEST(dm_test_sysreset_walk, UT_TESTF_SCAN_PDATA | UT_TESTF_SCAN_FDT);
+DM_TEST(dm_test_sysreset_walk, UTF_SCAN_PDATA | UTF_SCAN_FDT);
static int dm_test_sysreset_get_last(struct unit_test_state *uts)
{
@@ -114,4 +114,4 @@
return 0;
}
-DM_TEST(dm_test_sysreset_get_last, UT_TESTF_SCAN_PDATA | UT_TESTF_SCAN_FDT);
+DM_TEST(dm_test_sysreset_get_last, UTF_SCAN_PDATA | UTF_SCAN_FDT);
diff --git a/test/dm/tag.c b/test/dm/tag.c
index bce8a35..1412171 100644
--- a/test/dm/tag.c
+++ b/test/dm/tag.c
@@ -29,7 +29,6 @@
return 0;
}
-
DM_TEST(dm_test_tag_ptr, 0);
/*
@@ -49,7 +48,6 @@
return 0;
}
-
DM_TEST(dm_test_tag_val, 0);
/*
@@ -63,7 +61,6 @@
return 0;
}
-
DM_TEST(dm_test_tag_inval, 0);
/*
@@ -79,5 +76,4 @@
return 0;
}
-
DM_TEST(dm_test_tag_del_all, 0);
diff --git a/test/dm/tee.c b/test/dm/tee.c
index bb02a9b..b56c982 100644
--- a/test/dm/tee.c
+++ b/test/dm/tee.c
@@ -215,5 +215,4 @@
return rc;
}
-
-DM_TEST(dm_test_tee, UT_TESTF_SCAN_FDT);
+DM_TEST(dm_test_tee, UTF_SCAN_FDT);
diff --git a/test/dm/test-fdt.c b/test/dm/test-fdt.c
index 31effff..af8cd61 100644
--- a/test/dm/test-fdt.c
+++ b/test/dm/test-fdt.c
@@ -296,7 +296,7 @@
return 0;
}
-DM_TEST(dm_test_fdt_uclass_seq, UT_TESTF_SCAN_PDATA | UT_TESTF_SCAN_FDT);
+DM_TEST(dm_test_fdt_uclass_seq, UTF_SCAN_PDATA | UTF_SCAN_FDT);
/* More tests for sequence numbers */
static int dm_test_fdt_uclass_seq_manual(struct unit_test_state *uts)
@@ -321,7 +321,7 @@
return 0;
}
-DM_TEST(dm_test_fdt_uclass_seq_manual, UT_TESTF_SCAN_PDATA | UT_TESTF_SCAN_FDT);
+DM_TEST(dm_test_fdt_uclass_seq_manual, UTF_SCAN_PDATA | UTF_SCAN_FDT);
static int dm_test_fdt_uclass_seq_more(struct unit_test_state *uts)
{
@@ -360,7 +360,7 @@
return 0;
}
-DM_TEST(dm_test_fdt_uclass_seq_more, UT_TESTF_SCAN_PDATA | UT_TESTF_SCAN_FDT);
+DM_TEST(dm_test_fdt_uclass_seq_more, UTF_SCAN_PDATA | UTF_SCAN_FDT);
/* Test that we can find a device by device tree offset */
static int dm_test_fdt_offset(struct unit_test_state *uts)
@@ -390,7 +390,7 @@
return 0;
}
DM_TEST(dm_test_fdt_offset,
- UT_TESTF_SCAN_PDATA | UT_TESTF_SCAN_FDT | UT_TESTF_FLAT_TREE);
+ UTF_SCAN_PDATA | UTF_SCAN_FDT | UTF_FLAT_TREE);
/**
* Test various error conditions with uclass_first_device(),
@@ -455,7 +455,7 @@
return 0;
}
DM_TEST(dm_test_first_next_device_probeall,
- UT_TESTF_SCAN_PDATA | UT_TESTF_SCAN_FDT);
+ UTF_SCAN_PDATA | UTF_SCAN_FDT);
/* Test iteration through devices in a uclass */
static int dm_test_uclass_foreach(struct unit_test_state *uts)
@@ -476,7 +476,7 @@
return 0;
}
-DM_TEST(dm_test_uclass_foreach, UT_TESTF_SCAN_PDATA | UT_TESTF_SCAN_FDT);
+DM_TEST(dm_test_uclass_foreach, UTF_SCAN_PDATA | UTF_SCAN_FDT);
/**
* check_devices() - Check return values and pointers
@@ -556,7 +556,7 @@
return 0;
}
-DM_TEST(dm_test_first_next_ok_device, UT_TESTF_SCAN_PDATA | UT_TESTF_SCAN_FDT);
+DM_TEST(dm_test_first_next_ok_device, UTF_SCAN_PDATA | UTF_SCAN_FDT);
static const struct udevice_id fdt_dummy_ids[] = {
{ .compatible = "denx,u-boot-fdt-dummy", },
@@ -611,7 +611,7 @@
return 0;
}
-DM_TEST(dm_test_fdt_translation, UT_TESTF_SCAN_PDATA | UT_TESTF_SCAN_FDT);
+DM_TEST(dm_test_fdt_translation, UTF_SCAN_PDATA | UTF_SCAN_FDT);
static int dm_test_fdt_get_addr_ptr_flat(struct unit_test_state *uts)
{
@@ -632,7 +632,7 @@
return 0;
}
DM_TEST(dm_test_fdt_get_addr_ptr_flat,
- UT_TESTF_SCAN_PDATA | UT_TESTF_SCAN_FDT | UT_TESTF_FLAT_TREE);
+ UTF_SCAN_PDATA | UTF_SCAN_FDT | UTF_FLAT_TREE);
static int dm_test_fdt_remap_addr_flat(struct unit_test_state *uts)
{
@@ -652,7 +652,7 @@
return 0;
}
DM_TEST(dm_test_fdt_remap_addr_flat,
- UT_TESTF_SCAN_PDATA | UT_TESTF_SCAN_FDT | UT_TESTF_FLAT_TREE);
+ UTF_SCAN_PDATA | UTF_SCAN_FDT | UTF_FLAT_TREE);
static int dm_test_fdt_remap_addr_index_flat(struct unit_test_state *uts)
{
@@ -674,7 +674,7 @@
return 0;
}
DM_TEST(dm_test_fdt_remap_addr_index_flat,
- UT_TESTF_SCAN_PDATA | UT_TESTF_SCAN_FDT | UT_TESTF_FLAT_TREE);
+ UTF_SCAN_PDATA | UTF_SCAN_FDT | UTF_FLAT_TREE);
static int dm_test_fdt_remap_addr_name_flat(struct unit_test_state *uts)
{
@@ -696,7 +696,7 @@
return 0;
}
DM_TEST(dm_test_fdt_remap_addr_name_flat,
- UT_TESTF_SCAN_PDATA | UT_TESTF_SCAN_FDT | UT_TESTF_FLAT_TREE);
+ UTF_SCAN_PDATA | UTF_SCAN_FDT | UTF_FLAT_TREE);
static int dm_test_fdt_remap_addr_live(struct unit_test_state *uts)
{
@@ -716,7 +716,7 @@
return 0;
}
DM_TEST(dm_test_fdt_remap_addr_live,
- UT_TESTF_SCAN_PDATA | UT_TESTF_SCAN_FDT);
+ UTF_SCAN_PDATA | UTF_SCAN_FDT);
static int dm_test_fdt_remap_addr_index_live(struct unit_test_state *uts)
{
@@ -738,7 +738,7 @@
return 0;
}
DM_TEST(dm_test_fdt_remap_addr_index_live,
- UT_TESTF_SCAN_PDATA | UT_TESTF_SCAN_FDT);
+ UTF_SCAN_PDATA | UTF_SCAN_FDT);
static int dm_test_fdt_remap_addr_name_live(struct unit_test_state *uts)
{
@@ -760,7 +760,7 @@
return 0;
}
DM_TEST(dm_test_fdt_remap_addr_name_live,
- UT_TESTF_SCAN_PDATA | UT_TESTF_SCAN_FDT);
+ UTF_SCAN_PDATA | UTF_SCAN_FDT);
static int dm_test_fdt_disable_enable_by_path(struct unit_test_state *uts)
{
@@ -787,8 +787,7 @@
return 0;
}
-DM_TEST(dm_test_fdt_disable_enable_by_path, UT_TESTF_SCAN_PDATA |
- UT_TESTF_SCAN_FDT);
+DM_TEST(dm_test_fdt_disable_enable_by_path, UTF_SCAN_PDATA | UTF_SCAN_FDT);
/* Test a few uclass phandle functions */
static int dm_test_fdt_phandle(struct unit_test_state *uts)
@@ -810,7 +809,7 @@
return 0;
}
-DM_TEST(dm_test_fdt_phandle, UT_TESTF_SCAN_PDATA | UT_TESTF_SCAN_FDT);
+DM_TEST(dm_test_fdt_phandle, UTF_SCAN_PDATA | UTF_SCAN_FDT);
/* Test device_find_first_child_by_uclass() */
static int dm_test_first_child(struct unit_test_state *uts)
@@ -837,7 +836,7 @@
return 0;
}
-DM_TEST(dm_test_first_child, UT_TESTF_SCAN_PDATA | UT_TESTF_SCAN_FDT);
+DM_TEST(dm_test_first_child, UTF_SCAN_PDATA | UTF_SCAN_FDT);
/* Test integer functions in dm_read_...() */
static int dm_test_read_int(struct unit_test_state *uts)
@@ -901,7 +900,7 @@
return 0;
}
-DM_TEST(dm_test_read_int, UT_TESTF_SCAN_PDATA | UT_TESTF_SCAN_FDT);
+DM_TEST(dm_test_read_int, UTF_SCAN_PDATA | UTF_SCAN_FDT);
static int dm_test_read_int_index(struct unit_test_state *uts)
{
@@ -930,7 +929,7 @@
return 0;
}
-DM_TEST(dm_test_read_int_index, UT_TESTF_SCAN_PDATA | UT_TESTF_SCAN_FDT);
+DM_TEST(dm_test_read_int_index, UTF_SCAN_PDATA | UTF_SCAN_FDT);
static int dm_test_read_phandle(struct unit_test_state *uts)
{
@@ -995,7 +994,7 @@
return 0;
}
-DM_TEST(dm_test_read_phandle, UT_TESTF_SCAN_PDATA | UT_TESTF_SCAN_FDT);
+DM_TEST(dm_test_read_phandle, UTF_SCAN_PDATA | UTF_SCAN_FDT);
/* Test iteration through devices by drvdata */
static int dm_test_uclass_drvdata(struct unit_test_state *uts)
@@ -1016,7 +1015,7 @@
return 0;
}
-DM_TEST(dm_test_uclass_drvdata, UT_TESTF_SCAN_PDATA | UT_TESTF_SCAN_FDT);
+DM_TEST(dm_test_uclass_drvdata, UTF_SCAN_PDATA | UTF_SCAN_FDT);
/* Test device_first_child_ofdata_err(), etc. */
static int dm_test_child_ofdata(struct unit_test_state *uts)
@@ -1035,7 +1034,7 @@
return 0;
}
-DM_TEST(dm_test_child_ofdata, UT_TESTF_SCAN_PDATA | UT_TESTF_SCAN_FDT);
+DM_TEST(dm_test_child_ofdata, UTF_SCAN_PDATA | UTF_SCAN_FDT);
/* Test device_first_child_err(), etc. */
static int dm_test_first_child_probe(struct unit_test_state *uts)
@@ -1054,7 +1053,7 @@
return 0;
}
-DM_TEST(dm_test_first_child_probe, UT_TESTF_SCAN_PDATA | UT_TESTF_SCAN_FDT);
+DM_TEST(dm_test_first_child_probe, UTF_SCAN_PDATA | UTF_SCAN_FDT);
/* Test that ofdata is read for parents before children */
static int dm_test_ofdata_order(struct unit_test_state *uts)
@@ -1079,7 +1078,7 @@
return 0;
}
-DM_TEST(dm_test_ofdata_order, UT_TESTF_SCAN_PDATA | UT_TESTF_SCAN_FDT);
+DM_TEST(dm_test_ofdata_order, UTF_SCAN_PDATA | UTF_SCAN_FDT);
/* Test dev_decode_display_timing() */
static int dm_test_decode_display_timing(struct unit_test_state *uts)
@@ -1159,7 +1158,7 @@
ut_assert(dev_decode_display_timing(dev, 3, &timing));
return 0;
}
-DM_TEST(dm_test_decode_display_timing, UT_TESTF_SCAN_PDATA | UT_TESTF_SCAN_FDT);
+DM_TEST(dm_test_decode_display_timing, UTF_SCAN_PDATA | UTF_SCAN_FDT);
/* Test dev_decode_panel_timing() */
static int dm_test_decode_panel_timing(struct unit_test_state *uts)
@@ -1194,7 +1193,7 @@
return 0;
}
-DM_TEST(dm_test_decode_panel_timing, UT_TESTF_SCAN_PDATA | UT_TESTF_SCAN_FDT);
+DM_TEST(dm_test_decode_panel_timing, UTF_SCAN_PDATA | UTF_SCAN_FDT);
/* Test read_resourcee() */
static int dm_test_read_resource(struct unit_test_state *uts)
@@ -1225,5 +1224,4 @@
return 0;
}
-
-DM_TEST(dm_test_read_resource, UT_TESTF_SCAN_PDATA | UT_TESTF_SCAN_FDT);
+DM_TEST(dm_test_read_resource, UTF_SCAN_PDATA | UTF_SCAN_FDT);
diff --git a/test/dm/timer.c b/test/dm/timer.c
index 7fcefc4..a32059d 100644
--- a/test/dm/timer.c
+++ b/test/dm/timer.c
@@ -23,7 +23,7 @@
return 0;
}
-DM_TEST(dm_test_timer_base, UT_TESTF_SCAN_PDATA | UT_TESTF_SCAN_FDT);
+DM_TEST(dm_test_timer_base, UTF_SCAN_PDATA | UTF_SCAN_FDT);
/*
* Test of timebase fallback
@@ -46,4 +46,4 @@
return 0;
}
DM_TEST(dm_test_timer_timebase_fallback,
- UT_TESTF_SCAN_PDATA | UT_TESTF_SCAN_FDT);
+ UTF_SCAN_PDATA | UTF_SCAN_FDT);
diff --git a/test/dm/tpm.c b/test/dm/tpm.c
index 0e413c0..962a3fd 100644
--- a/test/dm/tpm.c
+++ b/test/dm/tpm.c
@@ -56,7 +56,7 @@
return 0;
}
-DM_TEST(dm_test_tpm, UT_TESTF_SCAN_FDT);
+DM_TEST(dm_test_tpm, UTF_SCAN_FDT);
/* Test report_state */
static int dm_test_tpm_report_state(struct unit_test_state *uts)
@@ -77,7 +77,7 @@
return 0;
}
-DM_TEST(dm_test_tpm_report_state, UT_TESTF_SCAN_FDT);
+DM_TEST(dm_test_tpm_report_state, UTF_SCAN_FDT);
/**
* test_tpm_autostart() - check the tpm_auto_start() call
@@ -114,7 +114,7 @@
return 0;
}
-DM_TEST(dm_test_tpm_autostart, UT_TESTF_SCAN_FDT);
+DM_TEST(dm_test_tpm_autostart, UTF_SCAN_FDT);
static int dm_test_tpm_autostart_reinit(struct unit_test_state *uts)
{
@@ -123,4 +123,4 @@
return 0;
}
-DM_TEST(dm_test_tpm_autostart_reinit, UT_TESTF_SCAN_FDT);
+DM_TEST(dm_test_tpm_autostart_reinit, UTF_SCAN_FDT);
diff --git a/test/dm/usb.c b/test/dm/usb.c
index 0bbea21..fa894c1 100644
--- a/test/dm/usb.c
+++ b/test/dm/usb.c
@@ -33,7 +33,7 @@
return 0;
}
-DM_TEST(dm_test_usb_base, UT_TESTF_SCAN_PDATA | UT_TESTF_SCAN_FDT);
+DM_TEST(dm_test_usb_base, UTF_SCAN_PDATA | UTF_SCAN_FDT);
/*
* Test that we can use the flash stick. This is more of a functional test. It
@@ -82,7 +82,7 @@
return 0;
}
-DM_TEST(dm_test_usb_flash, UT_TESTF_SCAN_PDATA | UT_TESTF_SCAN_FDT);
+DM_TEST(dm_test_usb_flash, UTF_SCAN_PDATA | UTF_SCAN_FDT);
/* test that we can handle multiple storage devices */
static int dm_test_usb_multi(struct unit_test_state *uts)
@@ -98,7 +98,7 @@
return 0;
}
-DM_TEST(dm_test_usb_multi, UT_TESTF_SCAN_PDATA | UT_TESTF_SCAN_FDT);
+DM_TEST(dm_test_usb_multi, UTF_SCAN_PDATA | UTF_SCAN_FDT);
/* test that we have an associated ofnode with the usb device */
static int dm_test_usb_fdt_node(struct unit_test_state *uts)
@@ -120,7 +120,7 @@
return 0;
}
-DM_TEST(dm_test_usb_fdt_node, UT_TESTF_SCAN_PDATA | UT_TESTF_SCAN_FDT);
+DM_TEST(dm_test_usb_fdt_node, UTF_SCAN_PDATA | UTF_SCAN_FDT);
static int count_usb_devices(void)
{
@@ -164,7 +164,7 @@
return 0;
}
-DM_TEST(dm_test_usb_stop, UT_TESTF_SCAN_PDATA | UT_TESTF_SCAN_FDT);
+DM_TEST(dm_test_usb_stop, UTF_SCAN_PDATA | UTF_SCAN_FDT);
/**
* dm_test_usb_keyb() - test USB keyboard driver
@@ -455,4 +455,4 @@
return 0;
}
-DM_TEST(dm_test_usb_keyb, UT_TESTF_SCAN_PDATA | UT_TESTF_SCAN_FDT);
+DM_TEST(dm_test_usb_keyb, UTF_SCAN_PDATA | UTF_SCAN_FDT);
diff --git a/test/dm/video.c b/test/dm/video.c
index 7dfbeb9..e347c14 100644
--- a/test/dm/video.c
+++ b/test/dm/video.c
@@ -42,7 +42,7 @@
return 0;
}
-DM_TEST(dm_test_video_base, UT_TESTF_SCAN_PDATA | UT_TESTF_SCAN_FDT);
+DM_TEST(dm_test_video_base, UTF_SCAN_PDATA | UTF_SCAN_FDT);
/**
* compress_frame_buffer() - Compress the frame buffer and return its size
@@ -175,7 +175,7 @@
return 0;
}
-DM_TEST(dm_test_video_text, UT_TESTF_SCAN_PDATA | UT_TESTF_SCAN_FDT);
+DM_TEST(dm_test_video_text, UTF_SCAN_PDATA | UTF_SCAN_FDT);
static int dm_test_video_text_12x22(struct unit_test_state *uts)
{
@@ -211,7 +211,7 @@
return 0;
}
-DM_TEST(dm_test_video_text_12x22, UT_TESTF_SCAN_PDATA | UT_TESTF_SCAN_FDT);
+DM_TEST(dm_test_video_text_12x22, UTF_SCAN_PDATA | UTF_SCAN_FDT);
/* Test handling of special characters in the console */
static int dm_test_video_chars(struct unit_test_state *uts)
@@ -228,7 +228,7 @@
return 0;
}
-DM_TEST(dm_test_video_chars, UT_TESTF_SCAN_PDATA | UT_TESTF_SCAN_FDT);
+DM_TEST(dm_test_video_chars, UTF_SCAN_PDATA | UTF_SCAN_FDT);
#ifdef CONFIG_VIDEO_ANSI
#define ANSI_ESC "\x1b"
@@ -262,7 +262,7 @@
return 0;
}
-DM_TEST(dm_test_video_ansi, UT_TESTF_SCAN_PDATA | UT_TESTF_SCAN_FDT);
+DM_TEST(dm_test_video_ansi, UTF_SCAN_PDATA | UTF_SCAN_FDT);
#endif
/**
@@ -320,7 +320,7 @@
return 0;
}
-DM_TEST(dm_test_video_context, UT_TESTF_SCAN_PDATA | UT_TESTF_SCAN_FDT);
+DM_TEST(dm_test_video_context, UTF_SCAN_PDATA | UTF_SCAN_FDT);
/* Test rotated text output through the console uclass */
static int dm_test_video_rotation1(struct unit_test_state *uts)
@@ -329,7 +329,7 @@
return 0;
}
-DM_TEST(dm_test_video_rotation1, UT_TESTF_SCAN_PDATA | UT_TESTF_SCAN_FDT);
+DM_TEST(dm_test_video_rotation1, UTF_SCAN_PDATA | UTF_SCAN_FDT);
/* Test rotated text output through the console uclass */
static int dm_test_video_rotation2(struct unit_test_state *uts)
@@ -338,7 +338,7 @@
return 0;
}
-DM_TEST(dm_test_video_rotation2, UT_TESTF_SCAN_PDATA | UT_TESTF_SCAN_FDT);
+DM_TEST(dm_test_video_rotation2, UTF_SCAN_PDATA | UTF_SCAN_FDT);
/* Test rotated text output through the console uclass */
static int dm_test_video_rotation3(struct unit_test_state *uts)
@@ -347,7 +347,7 @@
return 0;
}
-DM_TEST(dm_test_video_rotation3, UT_TESTF_SCAN_PDATA | UT_TESTF_SCAN_FDT);
+DM_TEST(dm_test_video_rotation3, UTF_SCAN_PDATA | UTF_SCAN_FDT);
/* Read a file into memory and return a pointer to it */
static int read_file(struct unit_test_state *uts, const char *fname,
@@ -385,7 +385,7 @@
return 0;
}
-DM_TEST(dm_test_video_bmp, UT_TESTF_SCAN_PDATA | UT_TESTF_SCAN_FDT);
+DM_TEST(dm_test_video_bmp, UTF_SCAN_PDATA | UTF_SCAN_FDT);
/* Test drawing a bitmap file on a 8bpp display */
static int dm_test_video_bmp8(struct unit_test_state *uts)
@@ -404,7 +404,7 @@
return 0;
}
-DM_TEST(dm_test_video_bmp8, UT_TESTF_SCAN_PDATA | UT_TESTF_SCAN_FDT);
+DM_TEST(dm_test_video_bmp8, UTF_SCAN_PDATA | UTF_SCAN_FDT);
/* Test drawing a bitmap file on a 16bpp display */
static int dm_test_video_bmp16(struct unit_test_state *uts)
@@ -427,7 +427,7 @@
return 0;
}
-DM_TEST(dm_test_video_bmp16, UT_TESTF_SCAN_PDATA | UT_TESTF_SCAN_FDT);
+DM_TEST(dm_test_video_bmp16, UTF_SCAN_PDATA | UTF_SCAN_FDT);
/* Test drawing a 24bpp bitmap file on a 16bpp display */
static int dm_test_video_bmp24(struct unit_test_state *uts)
@@ -450,7 +450,7 @@
return 0;
}
-DM_TEST(dm_test_video_bmp24, UT_TESTF_SCAN_PDATA | UT_TESTF_SCAN_FDT);
+DM_TEST(dm_test_video_bmp24, UTF_SCAN_PDATA | UTF_SCAN_FDT);
/* Test drawing a 24bpp bitmap file on a 32bpp display */
static int dm_test_video_bmp24_32(struct unit_test_state *uts)
@@ -473,7 +473,7 @@
return 0;
}
-DM_TEST(dm_test_video_bmp24_32, UT_TESTF_SCAN_PDATA | UT_TESTF_SCAN_FDT);
+DM_TEST(dm_test_video_bmp24_32, UTF_SCAN_PDATA | UTF_SCAN_FDT);
/* Test drawing a bitmap file on a 32bpp display */
static int dm_test_video_bmp32(struct unit_test_state *uts)
@@ -491,7 +491,7 @@
return 0;
}
-DM_TEST(dm_test_video_bmp32, UT_TESTF_SCAN_PDATA | UT_TESTF_SCAN_FDT);
+DM_TEST(dm_test_video_bmp32, UTF_SCAN_PDATA | UTF_SCAN_FDT);
/* Test drawing a compressed bitmap file */
static int dm_test_video_bmp_comp(struct unit_test_state *uts)
@@ -507,7 +507,7 @@
return 0;
}
-DM_TEST(dm_test_video_bmp_comp, UT_TESTF_SCAN_PDATA | UT_TESTF_SCAN_FDT);
+DM_TEST(dm_test_video_bmp_comp, UTF_SCAN_PDATA | UTF_SCAN_FDT);
/* Test drawing a bitmap file on a 32bpp display */
static int dm_test_video_comp_bmp32(struct unit_test_state *uts)
@@ -526,7 +526,7 @@
return 0;
}
-DM_TEST(dm_test_video_comp_bmp32, UT_TESTF_SCAN_PDATA | UT_TESTF_SCAN_FDT);
+DM_TEST(dm_test_video_comp_bmp32, UTF_SCAN_PDATA | UTF_SCAN_FDT);
/* Test drawing a bitmap file on a 8bpp display */
static int dm_test_video_comp_bmp8(struct unit_test_state *uts)
@@ -545,7 +545,7 @@
return 0;
}
-DM_TEST(dm_test_video_comp_bmp8, UT_TESTF_SCAN_PDATA | UT_TESTF_SCAN_FDT);
+DM_TEST(dm_test_video_comp_bmp8, UTF_SCAN_PDATA | UTF_SCAN_FDT);
/* Test TrueType console */
static int dm_test_video_truetype(struct unit_test_state *uts)
@@ -560,7 +560,7 @@
return 0;
}
-DM_TEST(dm_test_video_truetype, UT_TESTF_SCAN_PDATA | UT_TESTF_SCAN_FDT);
+DM_TEST(dm_test_video_truetype, UTF_SCAN_PDATA | UTF_SCAN_FDT);
/* Test scrolling TrueType console */
static int dm_test_video_truetype_scroll(struct unit_test_state *uts)
@@ -581,7 +581,7 @@
return 0;
}
-DM_TEST(dm_test_video_truetype_scroll, UT_TESTF_SCAN_PDATA | UT_TESTF_SCAN_FDT);
+DM_TEST(dm_test_video_truetype_scroll, UTF_SCAN_PDATA | UTF_SCAN_FDT);
/* Test TrueType backspace, within and across lines */
static int dm_test_video_truetype_bs(struct unit_test_state *uts)
@@ -602,4 +602,4 @@
return 0;
}
-DM_TEST(dm_test_video_truetype_bs, UT_TESTF_SCAN_PDATA | UT_TESTF_SCAN_FDT);
+DM_TEST(dm_test_video_truetype_bs, UTF_SCAN_PDATA | UTF_SCAN_FDT);
diff --git a/test/dm/virtio.c b/test/dm/virtio.c
index 3efd7c7..2574c4d 100644
--- a/test/dm/virtio.c
+++ b/test/dm/virtio.c
@@ -29,4 +29,4 @@
return 0;
}
-DM_TEST(dm_test_virtio_missing_ops, UT_TESTF_SCAN_PDATA | UT_TESTF_SCAN_FDT);
+DM_TEST(dm_test_virtio_missing_ops, UTF_SCAN_PDATA | UTF_SCAN_FDT);
diff --git a/test/dm/virtio_device.c b/test/dm/virtio_device.c
index 63dc534..53414e4 100644
--- a/test/dm/virtio_device.c
+++ b/test/dm/virtio_device.c
@@ -44,7 +44,7 @@
return 0;
}
-DM_TEST(dm_test_virtio_base, UT_TESTF_SCAN_PDATA | UT_TESTF_SCAN_FDT);
+DM_TEST(dm_test_virtio_base, UTF_SCAN_PDATA | UTF_SCAN_FDT);
/* Test all of the virtio uclass ops */
static int dm_test_virtio_all_ops(struct unit_test_state *uts)
@@ -93,7 +93,7 @@
return 0;
}
-DM_TEST(dm_test_virtio_all_ops, UT_TESTF_SCAN_PDATA | UT_TESTF_SCAN_FDT);
+DM_TEST(dm_test_virtio_all_ops, UTF_SCAN_PDATA | UTF_SCAN_FDT);
/* Test removal of virtio device driver */
static int dm_test_virtio_remove(struct unit_test_state *uts)
@@ -122,7 +122,7 @@
return 0;
}
-DM_TEST(dm_test_virtio_remove, UT_TESTF_SCAN_PDATA | UT_TESTF_SCAN_FDT);
+DM_TEST(dm_test_virtio_remove, UTF_SCAN_PDATA | UTF_SCAN_FDT);
/* Test all of the virtio ring */
static int dm_test_virtio_ring(struct unit_test_state *uts)
@@ -194,4 +194,4 @@
return 0;
}
-DM_TEST(dm_test_virtio_ring, UT_TESTF_SCAN_PDATA | UT_TESTF_SCAN_FDT);
+DM_TEST(dm_test_virtio_ring, UTF_SCAN_PDATA | UTF_SCAN_FDT);
diff --git a/test/dm/virtio_rng.c b/test/dm/virtio_rng.c
index ab7d862..e404b08 100644
--- a/test/dm/virtio_rng.c
+++ b/test/dm/virtio_rng.c
@@ -48,4 +48,4 @@
return 0;
}
-DM_TEST(dm_test_virtio_rng_check_len, UT_TESTF_SCAN_PDATA | UT_TESTF_SCAN_FDT);
+DM_TEST(dm_test_virtio_rng_check_len, UTF_SCAN_PDATA | UTF_SCAN_FDT);
diff --git a/test/dm/wdt.c b/test/dm/wdt.c
index 1df2da2..541bcba 100644
--- a/test/dm/wdt.c
+++ b/test/dm/wdt.c
@@ -43,7 +43,7 @@
return 0;
}
-DM_TEST(dm_test_wdt_base, UT_TESTF_SCAN_PDATA | UT_TESTF_SCAN_FDT);
+DM_TEST(dm_test_wdt_base, UTF_SCAN_PDATA | UTF_SCAN_FDT);
static int dm_test_wdt_gpio_toggle(struct unit_test_state *uts)
{
@@ -75,7 +75,7 @@
return 0;
}
-DM_TEST(dm_test_wdt_gpio_toggle, UT_TESTF_SCAN_FDT);
+DM_TEST(dm_test_wdt_gpio_toggle, UTF_SCAN_FDT);
static int dm_test_wdt_gpio_level(struct unit_test_state *uts)
{
@@ -107,7 +107,7 @@
return 0;
}
-DM_TEST(dm_test_wdt_gpio_level, UT_TESTF_SCAN_FDT);
+DM_TEST(dm_test_wdt_gpio_level, UTF_SCAN_FDT);
static int dm_test_wdt_watchdog_reset(struct unit_test_state *uts)
{
@@ -159,4 +159,4 @@
return 0;
}
-DM_TEST(dm_test_wdt_watchdog_reset, UT_TESTF_SCAN_FDT);
+DM_TEST(dm_test_wdt_watchdog_reset, UTF_SCAN_FDT);
diff --git a/test/env/cmd_ut_env.c b/test/env/cmd_ut_env.c
index 13e0998..4af0576 100644
--- a/test/env/cmd_ut_env.c
+++ b/test/env/cmd_ut_env.c
@@ -9,6 +9,33 @@
#include <test/suites.h>
#include <test/ut.h>
+static int env_test_env_cmd(struct unit_test_state *uts)
+{
+ ut_assertok(run_command("setenv non_default_var1 1", 0));
+ ut_assert_console_end();
+
+ ut_assertok(run_command("setenv non_default_var2 1", 0));
+ ut_assert_console_end();
+
+ ut_assertok(run_command("env print non_default_var1", 0));
+ ut_assert_nextline("non_default_var1=1");
+ ut_assert_console_end();
+
+ ut_assertok(run_command("env default non_default_var1 non_default_var2", 0));
+ ut_assert_nextline("WARNING: 'non_default_var1' not in imported env, deleting it!");
+ ut_assert_nextline("WARNING: 'non_default_var2' not in imported env, deleting it!");
+ ut_assert_console_end();
+
+ ut_asserteq(1, run_command("env exists non_default_var1", 0));
+ ut_assert_console_end();
+
+ ut_asserteq(1, run_command("env exists non_default_var2", 0));
+ ut_assert_console_end();
+
+ return 0;
+}
+ENV_TEST(env_test_env_cmd, UTF_CONSOLE);
+
int do_ut_env(struct cmd_tbl *cmdtp, int flag, int argc, char *const argv[])
{
struct unit_test *tests = UNIT_TEST_SUITE_START(env_test);
diff --git a/test/env/hashtable.c b/test/env/hashtable.c
index ccdf013..16e4935 100644
--- a/test/env/hashtable.c
+++ b/test/env/hashtable.c
@@ -101,7 +101,6 @@
hdestroy_r(&htab);
return 0;
}
-
ENV_TEST(env_test_htab_fill, 0);
/* Fill the hashtable up halfway an repeateadly delete/create elements
@@ -122,5 +121,4 @@
hdestroy_r(&htab);
return 0;
}
-
ENV_TEST(env_test_htab_deletes, 0);
diff --git a/test/hush/dollar.c b/test/hush/dollar.c
index 4caa07c..91b0970 100644
--- a/test/hush/dollar.c
+++ b/test/hush/dollar.c
@@ -14,7 +14,6 @@
static int hush_test_simple_dollar(struct unit_test_state *uts)
{
- console_record_reset_enable();
ut_assertok(run_command("echo $dollar_foo", 0));
ut_assert_nextline_empty();
ut_assert_console_end();
@@ -121,12 +120,11 @@
return 0;
}
-HUSH_TEST(hush_test_simple_dollar, 0);
+HUSH_TEST(hush_test_simple_dollar, UTF_CONSOLE);
static int hush_test_env_dollar(struct unit_test_state *uts)
{
env_set("env_foo", "bar");
- console_record_reset_enable();
ut_assertok(run_command("echo $env_foo", 0));
ut_assert_nextline("bar");
@@ -154,12 +152,10 @@
return 0;
}
-HUSH_TEST(hush_test_env_dollar, 0);
+HUSH_TEST(hush_test_env_dollar, UTF_CONSOLE);
static int hush_test_command_dollar(struct unit_test_state *uts)
{
- console_record_reset_enable();
-
ut_assertok(run_command("dollar_bar=\"echo bar\"", 0));
ut_assertok(run_command("$dollar_bar", 0));
@@ -222,4 +218,4 @@
return 0;
}
-HUSH_TEST(hush_test_command_dollar, 0);
+HUSH_TEST(hush_test_command_dollar, UTF_CONSOLE);
diff --git a/test/hush/loop.c b/test/hush/loop.c
index d734abf..a9b6a8e 100644
--- a/test/hush/loop.c
+++ b/test/hush/loop.c
@@ -14,8 +14,6 @@
static int hush_test_for(struct unit_test_state *uts)
{
- console_record_reset_enable();
-
ut_assertok(run_command("for loop_i in foo bar quux quux; do echo $loop_i; done", 0));
ut_assert_nextline("foo");
ut_assert_nextline("bar");
@@ -32,12 +30,10 @@
return 0;
}
-HUSH_TEST(hush_test_for, 0);
+HUSH_TEST(hush_test_for, UTF_CONSOLE);
static int hush_test_while(struct unit_test_state *uts)
{
- console_record_reset_enable();
-
if (gd->flags & GD_FLG_HUSH_MODERN_PARSER) {
/*
* Hush 2021 always returns 0 from while loop...
@@ -65,11 +61,10 @@
return 0;
}
-HUSH_TEST(hush_test_while, 0);
+HUSH_TEST(hush_test_while, UTF_CONSOLE);
static int hush_test_until(struct unit_test_state *uts)
{
- console_record_reset_enable();
env_set("loop_bar", "bar");
/*
@@ -87,4 +82,4 @@
env_set("loop_bar", NULL);
return 0;
}
-HUSH_TEST(hush_test_until, 0);
+HUSH_TEST(hush_test_until, UTF_CONSOLE);
diff --git a/test/image/spl_load.c b/test/image/spl_load.c
index 7cbad40..3b62069 100644
--- a/test/image/spl_load.c
+++ b/test/image/spl_load.c
@@ -343,9 +343,7 @@
} else {
struct spl_load_info load;
- spl_set_bl_len(&load, 1);
- load.priv = img;
- load.read = spl_test_read;
+ spl_load_init(&load, spl_test_read, img, 1);
if (type == IMX8)
ut_assertok(spl_load_imx_container(&info_read, &load,
0));
diff --git a/test/image/spl_load_os.c b/test/image/spl_load_os.c
index 7d5fb9b..d17cf11 100644
--- a/test/image/spl_load_os.c
+++ b/test/image/spl_load_os.c
@@ -10,64 +10,14 @@
#include <test/spl.h>
#include <test/ut.h>
-/* Context used for this test */
-struct text_ctx {
- int fd;
-};
-
-static ulong read_fit_image(struct spl_load_info *load, ulong offset,
- ulong size, void *buf)
-{
- struct text_ctx *text_ctx = load->priv;
- off_t ret;
- ssize_t res;
-
- ret = os_lseek(text_ctx->fd, offset, OS_SEEK_SET);
- if (ret != offset) {
- printf("Failed to seek to %zx, got %zx (errno=%d)\n", offset,
- ret, errno);
- return 0;
- }
-
- res = os_read(text_ctx->fd, buf, size);
- if (res == -1) {
- printf("Failed to read %lx bytes, got %ld (errno=%d)\n",
- size, res, errno);
- return 0;
- }
-
- return size;
-}
-
static int spl_test_load(struct unit_test_state *uts)
{
struct spl_image_info image;
- struct legacy_img_hdr *header;
- struct text_ctx text_ctx;
- struct spl_load_info load;
char fname[256];
- int ret;
- int fd;
- memset(&load, '\0', sizeof(load));
- spl_set_bl_len(&load, 512);
- load.read = read_fit_image;
-
- ret = sandbox_find_next_phase(fname, sizeof(fname), true);
- if (ret)
- ut_assertf(0, "%s not found, error %d\n", fname, ret);
-
- header = spl_get_load_buffer(-sizeof(*header), sizeof(*header));
-
- fd = os_open(fname, OS_O_RDONLY);
- ut_assert(fd >= 0);
- ut_asserteq(512, os_read(fd, header, 512));
- text_ctx.fd = fd;
-
- load.priv = &text_ctx;
-
- ut_assertok(spl_load_simple_fit(&image, &load, 0, header));
+ ut_assertok(sandbox_spl_load_fit(fname, sizeof(fname), &image));
return 0;
}
SPL_TEST(spl_test_load, 0);
+
diff --git a/test/lib/Makefile b/test/lib/Makefile
index e75a263..70f14c4 100644
--- a/test/lib/Makefile
+++ b/test/lib/Makefile
@@ -5,6 +5,7 @@
ifeq ($(CONFIG_SPL_BUILD),)
obj-y += cmd_ut_lib.o
obj-y += abuf.o
+obj-y += alist.o
obj-$(CONFIG_EFI_LOADER) += efi_device_path.o
obj-$(CONFIG_EFI_SECURE_BOOT) += efi_image_region.o
obj-y += hexdump.o
diff --git a/test/lib/alist.c b/test/lib/alist.c
new file mode 100644
index 0000000..d41845c
--- /dev/null
+++ b/test/lib/alist.c
@@ -0,0 +1,242 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright 2023 Google LLC
+ * Written by Simon Glass <sjg@chromium.org>
+ */
+
+#include <alist.h>
+#include <string.h>
+#include <test/lib.h>
+#include <test/test.h>
+#include <test/ut.h>
+
+struct my_struct {
+ uint val;
+ uint other_val;
+};
+
+enum {
+ obj_size = sizeof(struct my_struct),
+};
+
+/* Test alist_init() */
+static int lib_test_alist_init(struct unit_test_state *uts)
+{
+ struct alist lst;
+ ulong start;
+
+ start = ut_check_free();
+
+ /* with a size of 0, the fields should be inited, with no memory used */
+ memset(&lst, '\xff', sizeof(lst));
+ ut_assert(alist_init_struct(&lst, struct my_struct));
+ ut_asserteq_ptr(NULL, lst.data);
+ ut_asserteq(0, lst.count);
+ ut_asserteq(0, lst.alloc);
+ ut_assertok(ut_check_delta(start));
+ alist_uninit(&lst);
+ ut_asserteq_ptr(NULL, lst.data);
+ ut_asserteq(0, lst.count);
+ ut_asserteq(0, lst.alloc);
+
+ /* use an impossible size */
+ ut_asserteq(false, alist_init(&lst, obj_size,
+ CONFIG_SYS_MALLOC_LEN));
+ ut_assertnull(lst.data);
+ ut_asserteq(0, lst.count);
+ ut_asserteq(0, lst.alloc);
+
+ /* use a small size */
+ ut_assert(alist_init(&lst, obj_size, 4));
+ ut_assertnonnull(lst.data);
+ ut_asserteq(0, lst.count);
+ ut_asserteq(4, lst.alloc);
+
+ /* free it */
+ alist_uninit(&lst);
+ ut_asserteq_ptr(NULL, lst.data);
+ ut_asserteq(0, lst.count);
+ ut_asserteq(0, lst.alloc);
+ ut_assertok(ut_check_delta(start));
+
+ /* Check for memory leaks */
+ ut_assertok(ut_check_delta(start));
+
+ return 0;
+}
+LIB_TEST(lib_test_alist_init, 0);
+
+/* Test alist_get() and alist_getd() */
+static int lib_test_alist_get(struct unit_test_state *uts)
+{
+ struct alist lst;
+ ulong start;
+ void *ptr;
+
+ start = ut_check_free();
+
+ ut_assert(alist_init(&lst, obj_size, 3));
+ ut_asserteq(0, lst.count);
+ ut_asserteq(3, lst.alloc);
+
+ ut_assertnull(alist_get_ptr(&lst, 2));
+ ut_assertnull(alist_get_ptr(&lst, 3));
+
+ ptr = alist_ensure_ptr(&lst, 1);
+ ut_assertnonnull(ptr);
+ ut_asserteq(2, lst.count);
+ ptr = alist_ensure_ptr(&lst, 2);
+ ut_asserteq(3, lst.count);
+ ut_assertnonnull(ptr);
+
+ ptr = alist_ensure_ptr(&lst, 3);
+ ut_assertnonnull(ptr);
+ ut_asserteq(4, lst.count);
+ ut_asserteq(6, lst.alloc);
+
+ ut_assertnull(alist_get_ptr(&lst, 4));
+
+ alist_uninit(&lst);
+
+ /* Check for memory leaks */
+ ut_assertok(ut_check_delta(start));
+
+ return 0;
+}
+LIB_TEST(lib_test_alist_get, 0);
+
+/* Test alist_has() */
+static int lib_test_alist_has(struct unit_test_state *uts)
+{
+ struct alist lst;
+ ulong start;
+ void *ptr;
+
+ start = ut_check_free();
+
+ ut_assert(alist_init(&lst, obj_size, 3));
+
+ ut_assert(!alist_has(&lst, 0));
+ ut_assert(!alist_has(&lst, 1));
+ ut_assert(!alist_has(&lst, 2));
+ ut_assert(!alist_has(&lst, 3));
+
+ /* create a new one to force expansion */
+ ptr = alist_ensure_ptr(&lst, 4);
+ ut_assertnonnull(ptr);
+
+ ut_assert(alist_has(&lst, 0));
+ ut_assert(alist_has(&lst, 1));
+ ut_assert(alist_has(&lst, 2));
+ ut_assert(alist_has(&lst, 3));
+ ut_assert(alist_has(&lst, 4));
+ ut_assert(!alist_has(&lst, 5));
+
+ alist_uninit(&lst);
+
+ /* Check for memory leaks */
+ ut_assertok(ut_check_delta(start));
+
+ return 0;
+}
+LIB_TEST(lib_test_alist_has, 0);
+
+/* Test alist_ensure() */
+static int lib_test_alist_ensure(struct unit_test_state *uts)
+{
+ struct my_struct *ptr3, *ptr4;
+ struct alist lst;
+ ulong start;
+
+ start = ut_check_free();
+
+ ut_assert(alist_init_struct(&lst, struct my_struct));
+ ut_asserteq(obj_size, lst.obj_size);
+ ut_asserteq(0, lst.count);
+ ut_asserteq(0, lst.alloc);
+ ptr3 = alist_ensure_ptr(&lst, 3);
+ ut_asserteq(4, lst.count);
+ ut_asserteq(4, lst.alloc);
+ ut_assertnonnull(ptr3);
+ ptr3->val = 3;
+
+ ptr4 = alist_ensure_ptr(&lst, 4);
+ ut_asserteq(8, lst.alloc);
+ ut_asserteq(5, lst.count);
+ ut_assertnonnull(ptr4);
+ ptr4->val = 4;
+ ut_asserteq(4, alist_get(&lst, 4, struct my_struct)->val);
+
+ ut_asserteq_ptr(ptr4, alist_ensure(&lst, 4, struct my_struct));
+
+ alist_ensure(&lst, 4, struct my_struct)->val = 44;
+ ut_asserteq(44, alist_get(&lst, 4, struct my_struct)->val);
+ ut_asserteq(3, alist_get(&lst, 3, struct my_struct)->val);
+ ut_assertnull(alist_get(&lst, 7, struct my_struct));
+ ut_asserteq(8, lst.alloc);
+ ut_asserteq(5, lst.count);
+
+ /* add some more, checking handling of malloc() failure */
+ malloc_enable_testing(0);
+ ut_assertnonnull(alist_ensure(&lst, 7, struct my_struct));
+ ut_assertnull(alist_ensure(&lst, 8, struct my_struct));
+ malloc_disable_testing();
+
+ lst.flags &= ~ALISTF_FAIL;
+ ut_assertnonnull(alist_ensure(&lst, 8, struct my_struct));
+ ut_asserteq(16, lst.alloc);
+ ut_asserteq(9, lst.count);
+
+ alist_uninit(&lst);
+
+ /* Check for memory leaks */
+ ut_assertok(ut_check_delta(start));
+
+ return 0;
+}
+LIB_TEST(lib_test_alist_ensure, 0);
+
+/* Test alist_add() bits not tested by lib_test_alist_ensure() */
+static int lib_test_alist_add(struct unit_test_state *uts)
+{
+ struct my_struct data, *ptr, *ptr2;
+ const struct my_struct *chk;
+ struct alist lst;
+ ulong start;
+
+ start = ut_check_free();
+
+ ut_assert(alist_init_struct(&lst, struct my_struct));
+
+ data.val = 123;
+ data.other_val = 456;
+ ptr = alist_add(&lst, data);
+ ut_assertnonnull(ptr);
+ ut_asserteq(4, lst.alloc);
+ ut_asserteq(1, lst.count);
+
+ ut_asserteq(123, ptr->val);
+ ut_asserteq(456, ptr->other_val);
+
+ ptr2 = alist_add_placeholder(&lst);
+ ut_assertnonnull(ptr2);
+
+ ptr2->val = 321;
+ ptr2->other_val = 654;
+
+ chk = alist_get(&lst, 1, struct my_struct);
+ ut_asserteq(321, chk->val);
+ ut_asserteq(654, chk->other_val);
+
+ ptr2 = alist_getw(&lst, 1, struct my_struct);
+ ut_asserteq(321, ptr2->val);
+ ut_asserteq(654, ptr2->other_val);
+
+ alist_uninit(&lst);
+
+ /* Check for memory leaks */
+ ut_assertok(ut_check_delta(start));
+
+ return 0;
+}
+LIB_TEST(lib_test_alist_add, 0);
diff --git a/test/lib/asn1.c b/test/lib/asn1.c
index 4842b70..f0c7819 100644
--- a/test/lib/asn1.c
+++ b/test/lib/asn1.c
@@ -135,7 +135,6 @@
return CMD_RET_SUCCESS;
}
-
LIB_TEST(lib_asn1_x509, 0);
#endif /* CONFIG_X509_CERTIFICATE_PARSER */
@@ -324,7 +323,6 @@
return CMD_RET_SUCCESS;
}
-
LIB_TEST(lib_asn1_pkcs7, 0);
#endif /* CONFIG_PKCS7_MESSAGE_PARSER */
@@ -386,6 +384,5 @@
return CMD_RET_SUCCESS;
}
-
LIB_TEST(lib_asn1_pkey, 0);
#endif /* CONFIG_RSA_PUBLIC_KEY_PARSER */
diff --git a/test/lib/efi_device_path.c b/test/lib/efi_device_path.c
index 290c876..5cc001e 100644
--- a/test/lib/efi_device_path.c
+++ b/test/lib/efi_device_path.c
@@ -45,5 +45,4 @@
return 0;
}
-
LIB_TEST(lib_test_efi_dp_check_length, 0);
diff --git a/test/lib/efi_image_region.c b/test/lib/efi_image_region.c
index 3ca49dc..2102539 100644
--- a/test/lib/efi_image_region.c
+++ b/test/lib/efi_image_region.c
@@ -65,7 +65,6 @@
return 0;
}
-
LIB_TEST(lib_test_efi_image_region_add, 0);
static int lib_test_efi_image_region_sort(struct unit_test_state *uts)
@@ -158,5 +157,4 @@
return 0;
}
-
LIB_TEST(lib_test_efi_image_region_sort, 0);
diff --git a/test/lib/hexdump.c b/test/lib/hexdump.c
index d531a83..7b4592d 100644
--- a/test/lib/hexdump.c
+++ b/test/lib/hexdump.c
@@ -31,7 +31,6 @@
return 0;
}
-
LIB_TEST(lib_test_hex_to_bin, 0);
static int lib_test_hex2bin(struct unit_test_state *uts)
@@ -61,7 +60,6 @@
return 0;
}
-
LIB_TEST(lib_test_hex2bin, 0);
static int lib_test_bin2hex(struct unit_test_state *uts)
@@ -91,5 +89,4 @@
return 0;
}
-
LIB_TEST(lib_test_bin2hex, 0);
diff --git a/test/lib/lmb.c b/test/lib/lmb.c
index 4b5b6e5..3c66138 100644
--- a/test/lib/lmb.c
+++ b/test/lib/lmb.c
@@ -360,7 +360,6 @@
/* simulate 512 MiB RAM beginning at 1.5GiB */
return test_noreserved(uts, 0xE0000000, 4, 1);
}
-
LIB_TEST(lib_test_lmb_noreserved, 0);
static int lib_test_lmb_unaligned_size(struct unit_test_state *uts)
diff --git a/test/lib/rsa.c b/test/lib/rsa.c
index 40f7001..129d03a 100644
--- a/test/lib/rsa.c
+++ b/test/lib/rsa.c
@@ -158,7 +158,6 @@
return CMD_RET_SUCCESS;
}
-
LIB_TEST(lib_rsa_verify_valid, 0);
/**
@@ -200,6 +199,5 @@
return CMD_RET_SUCCESS;
}
-
LIB_TEST(lib_rsa_verify_invalid, 0);
#endif /* RSA_VERIFY_WITH_PKEY */
diff --git a/test/lib/sscanf.c b/test/lib/sscanf.c
index 9fe5521..3a2ec8f 100644
--- a/test/lib/sscanf.c
+++ b/test/lib/sscanf.c
@@ -169,5 +169,4 @@
return 0;
}
-
LIB_TEST(lib_sscanf, 0);
diff --git a/test/lib/string.c b/test/lib/string.c
index d08dbca..8d22f3f 100644
--- a/test/lib/string.c
+++ b/test/lib/string.c
@@ -93,7 +93,6 @@
}
return 0;
}
-
LIB_TEST(lib_memset, 0);
/**
@@ -157,7 +156,6 @@
}
return 0;
}
-
LIB_TEST(lib_memcpy, 0);
/**
@@ -192,7 +190,6 @@
}
return 0;
}
-
LIB_TEST(lib_memmove, 0);
/** lib_memdup() - unit test for memdup() */
diff --git a/test/lib/test_aes.c b/test/lib/test_aes.c
index cfd9d8c..6d9068c 100644
--- a/test/lib/test_aes.c
+++ b/test/lib/test_aes.c
@@ -163,5 +163,4 @@
return ret;
}
-
LIB_TEST(lib_test_aes, 0);
diff --git a/test/lib/test_crc8.c b/test/lib/test_crc8.c
index 0dac97b..52be2dc 100644
--- a/test/lib/test_crc8.c
+++ b/test/lib/test_crc8.c
@@ -25,5 +25,4 @@
return 0;
}
-
LIB_TEST(lib_crc8, 0);
diff --git a/test/lib/test_crypt.c b/test/lib/test_crypt.c
index dcdadd9..b6dd5f0 100644
--- a/test/lib/test_crypt.c
+++ b/test/lib/test_crypt.c
@@ -59,5 +59,4 @@
return CMD_RET_SUCCESS;
}
-
LIB_TEST(lib_crypt, 0);
diff --git a/test/lib/test_errno_str.c b/test/lib/test_errno_str.c
index 67f7644..967ecfd 100644
--- a/test/lib/test_errno_str.c
+++ b/test/lib/test_errno_str.c
@@ -41,5 +41,4 @@
return 0;
}
-
LIB_TEST(lib_errno_str, 0);
diff --git a/test/lib/test_print.c b/test/lib/test_print.c
index c7fc50a..cd7f3f8 100644
--- a/test/lib/test_print.c
+++ b/test/lib/test_print.c
@@ -17,13 +17,10 @@
static int test_print_freq(struct unit_test_state *uts,
uint64_t freq, char *expected)
{
- ut_silence_console(uts);
- console_record_reset_enable();
print_freq(freq, ";\n");
- ut_unsilence_console(uts);
console_record_readline(uts->actual_str, sizeof(uts->actual_str));
ut_asserteq_str(expected, uts->actual_str);
- ut_assertok(ut_check_console_end(uts));
+ ut_assert_console_end();
return 0;
}
@@ -41,19 +38,15 @@
ut_assertok(test_print_freq(uts, 54321987654321, "54321.99 GHz;"));
return 0;
}
-
-LIB_TEST(lib_test_print_freq, 0);
+LIB_TEST(lib_test_print_freq, UTF_CONSOLE);
static int test_print_size(struct unit_test_state *uts,
uint64_t freq, char *expected)
{
- ut_silence_console(uts);
- console_record_reset_enable();
print_size(freq, ";\n");
- ut_unsilence_console(uts);
console_record_readline(uts->actual_str, sizeof(uts->actual_str));
ut_asserteq_str(expected, uts->actual_str);
- ut_assertok(ut_check_console_end(uts));
+ ut_assert_console_end();
return 0;
}
@@ -74,5 +67,4 @@
ut_assertok(test_print_size(uts, 54321987654321, "49.4 TiB;"));
return 0;
}
-
-LIB_TEST(lib_test_print_size, 0);
+LIB_TEST(lib_test_print_size, UTF_CONSOLE);
diff --git a/test/lib/uuid.c b/test/lib/uuid.c
index 0914f2c..8fe65db 100644
--- a/test/lib/uuid.c
+++ b/test/lib/uuid.c
@@ -36,5 +36,4 @@
return 0;
}
-
LIB_TEST(lib_test_uuid_to_le, 0);
diff --git a/test/log/cont_test.c b/test/log/cont_test.c
index 036d44b..32b1c79 100644
--- a/test/log/cont_test.c
+++ b/test/log/cont_test.c
@@ -25,7 +25,6 @@
/* Write two messages, the second continuing the first */
gd->log_fmt = (1 << LOGF_CAT) | (1 << LOGF_LEVEL) | (1 << LOGF_MSG);
gd->default_log_level = LOGL_INFO;
- console_record_reset_enable();
log(LOGC_ARCH, LOGL_ERR, "ea%d\n", 1);
log(LOGC_CONT, LOGL_CONT, "cc%d\n", 2);
gd->default_log_level = log_level;
@@ -33,7 +32,7 @@
gd->flags &= ~GD_FLG_RECORD;
ut_assertok(ut_check_console_line(uts, "ERR.arch, ea1"));
ut_assertok(ut_check_console_line(uts, "ERR.arch, cc2"));
- ut_assertok(ut_check_console_end(uts));
+ ut_assert_console_end();
/* Write a third message which is not a continuation */
gd->log_fmt = (1 << LOGF_CAT) | (1 << LOGF_LEVEL) | (1 << LOGF_MSG);
@@ -44,7 +43,7 @@
gd->log_fmt = log_fmt;
gd->flags &= ~GD_FLG_RECORD;
ut_assertok(ut_check_console_line(uts, "INFO.efi, ie3"));
- ut_assertok(ut_check_console_end(uts));
+ ut_assert_console_end();
/* Write two messages without a newline between them */
gd->log_fmt = (1 << LOGF_CAT) | (1 << LOGF_LEVEL) | (1 << LOGF_MSG);
@@ -56,7 +55,7 @@
gd->log_fmt = log_fmt;
gd->flags &= ~GD_FLG_RECORD;
ut_assertok(ut_check_console_line(uts, "ERR.arch, ea1 cc2"));
- ut_assertok(ut_check_console_end(uts));
+ ut_assert_console_end();
return 0;
}
diff --git a/test/log/log_filter.c b/test/log/log_filter.c
index 9cc891d..d36e9d9 100644
--- a/test/log/log_filter.c
+++ b/test/log/log_filter.c
@@ -24,7 +24,7 @@
return 0;
}
-LOG_TEST_FLAGS(log_test_filter_invalid, UT_TESTF_CONSOLE_REC);
+LOG_TEST_FLAGS(log_test_filter_invalid, UTF_CONSOLE);
/* Test adding and removing filters */
static int log_test_filter(struct unit_test_state *uts)
@@ -38,7 +38,6 @@
ulong filt1, filt2;
#define create_filter(args, filter_num) do {\
- ut_assertok(console_record_reset_enable()); \
ut_assertok(run_command("log filter-add -p " args, 0)); \
ut_assert_skipline(); \
ut_assertok(strict_strtoul(uts->actual_str, 10, &(filter_num))); \
@@ -72,7 +71,6 @@
ut_asserteq(true, filt2_found);
#define remove_filter(filter_num) do { \
- ut_assertok(console_record_reset_enable()); \
snprintf(cmd, sizeof(cmd), "log filter-remove %lu", filter_num); \
ut_assertok(run_command(cmd, 0)); \
ut_assert_console_end(); \
@@ -95,7 +93,6 @@
create_filter("", filt1);
create_filter("", filt2);
- ut_assertok(console_record_reset_enable());
ut_assertok(run_command("log filter-remove -a", 0));
ut_assert_console_end();
@@ -105,4 +102,4 @@
return 0;
}
-LOG_TEST_FLAGS(log_test_filter, UT_TESTF_CONSOLE_REC);
+LOG_TEST_FLAGS(log_test_filter, UTF_CONSOLE);
diff --git a/test/log/log_test.c b/test/log/log_test.c
index 855353a..1c89df4 100644
--- a/test/log/log_test.c
+++ b/test/log/log_test.c
@@ -110,18 +110,16 @@
filt = log_add_filter("console", cat_list, LOGL_MAX, NULL);
ut_assert(filt >= 0);
- ut_assertok(console_record_reset_enable());
log_run_cat(UCLASS_MMC);
check_log_entries_extra();
- ut_assertok(console_record_reset_enable());
log_run_cat(UCLASS_SPI);
check_log_entries_extra();
ut_assertok(log_remove_filter("console", filt));
return 0;
}
-LOG_TEST_FLAGS(log_test_cat_allow, UT_TESTF_CONSOLE_REC);
+LOG_TEST_FLAGS(log_test_cat_allow, UTF_CONSOLE);
/* Check a category filter that should block log entries */
int log_test_cat_deny_implicit(struct unit_test_state *uts)
@@ -134,14 +132,13 @@
filt = log_add_filter("console", cat_list, LOGL_MAX, NULL);
ut_assert(filt >= 0);
- ut_assertok(console_record_reset_enable());
log_run_cat(UCLASS_SPI);
check_log_entries_none();
ut_assertok(log_remove_filter("console", filt));
return 0;
}
-LOG_TEST_FLAGS(log_test_cat_deny_implicit, UT_TESTF_CONSOLE_REC);
+LOG_TEST_FLAGS(log_test_cat_deny_implicit, UTF_CONSOLE);
/* Check passing and failing file filters */
int log_test_file(struct unit_test_state *uts)
@@ -151,18 +148,16 @@
filt = log_add_filter("console", NULL, LOGL_MAX, "file");
ut_assert(filt >= 0);
- ut_assertok(console_record_reset_enable());
log_run_file("file");
check_log_entries_flags(EXPECT_DIRECT | EXPECT_EXTRA | EXPECT_FORCE);
- ut_assertok(console_record_reset_enable());
log_run_file("file2");
check_log_entries_none();
ut_assertok(log_remove_filter("console", filt));
return 0;
}
-LOG_TEST_FLAGS(log_test_file, UT_TESTF_CONSOLE_REC);
+LOG_TEST_FLAGS(log_test_file, UTF_CONSOLE);
/* Check a passing file filter (second in list) */
int log_test_file_second(struct unit_test_state *uts)
@@ -172,14 +167,13 @@
filt = log_add_filter("console", NULL, LOGL_MAX, "file,file2");
ut_assert(filt >= 0);
- ut_assertok(console_record_reset_enable());
log_run_file("file2");
check_log_entries_flags(EXPECT_DIRECT | EXPECT_EXTRA | EXPECT_FORCE);
ut_assertok(log_remove_filter("console", filt));
return 0;
}
-LOG_TEST_FLAGS(log_test_file_second, UT_TESTF_CONSOLE_REC);
+LOG_TEST_FLAGS(log_test_file_second, UTF_CONSOLE);
/* Check a passing file filter (middle of list) */
int log_test_file_mid(struct unit_test_state *uts)
@@ -190,14 +184,13 @@
"file,file2,log/log_test.c");
ut_assert(filt >= 0);
- ut_assertok(console_record_reset_enable());
log_run_file("file2");
check_log_entries_extra();
ut_assertok(log_remove_filter("console", filt));
return 0;
}
-LOG_TEST_FLAGS(log_test_file_mid, UT_TESTF_CONSOLE_REC);
+LOG_TEST_FLAGS(log_test_file_mid, UTF_CONSOLE);
/* Check a log level filter */
int log_test_level(struct unit_test_state *uts)
@@ -207,7 +200,6 @@
filt = log_add_filter("console", NULL, LOGL_WARNING, NULL);
ut_assert(filt >= 0);
- ut_assertok(console_record_reset_enable());
log_run();
check_log_entries_flags_levels(EXPECT_LOG | EXPECT_DIRECT | EXPECT_FORCE,
LOGL_FIRST, LOGL_WARNING);
@@ -215,7 +207,7 @@
ut_assertok(log_remove_filter("console", filt));
return 0;
}
-LOG_TEST_FLAGS(log_test_level, UT_TESTF_CONSOLE_REC);
+LOG_TEST_FLAGS(log_test_level, UTF_CONSOLE);
/* Check two filters, one of which passes everything */
int log_test_double(struct unit_test_state *uts)
@@ -227,7 +219,6 @@
filt2 = log_add_filter("console", NULL, LOGL_MAX, NULL);
ut_assert(filt2 >= 0);
- ut_assertok(console_record_reset_enable());
log_run();
check_log_entries_extra();
@@ -235,7 +226,7 @@
ut_assertok(log_remove_filter("console", filt2));
return 0;
}
-LOG_TEST_FLAGS(log_test_double, UT_TESTF_CONSOLE_REC);
+LOG_TEST_FLAGS(log_test_double, UTF_CONSOLE);
/* Check three filters, which together pass everything */
int log_test_triple(struct unit_test_state *uts)
@@ -249,7 +240,6 @@
filt3 = log_add_filter("console", NULL, LOGL_MAX, "log/log_test.c");
ut_assert(filt3 >= 0);
- ut_assertok(console_record_reset_enable());
log_run_file("file2");
check_log_entries_extra();
@@ -258,13 +248,12 @@
ut_assertok(log_remove_filter("console", filt3));
return 0;
}
-LOG_TEST_FLAGS(log_test_triple, UT_TESTF_CONSOLE_REC);
+LOG_TEST_FLAGS(log_test_triple, UTF_CONSOLE);
int do_log_test_helpers(struct unit_test_state *uts)
{
int i;
- ut_assertok(console_record_reset_enable());
log_err("level %d\n", LOGL_EMERG);
log_err("level %d\n", LOGL_ALERT);
log_err("level %d\n", LOGL_CRIT);
@@ -292,11 +281,10 @@
gd->log_fmt = log_get_default_format();
return ret;
}
-LOG_TEST_FLAGS(log_test_helpers, UT_TESTF_CONSOLE_REC);
+LOG_TEST_FLAGS(log_test_helpers, UTF_CONSOLE);
int do_log_test_disable(struct unit_test_state *uts)
{
- ut_assertok(console_record_reset_enable());
log_err("default\n");
ut_assert_nextline("%*s() default", CONFIG_LOGF_FUNC_PAD, __func__);
@@ -319,7 +307,7 @@
gd->log_fmt = log_get_default_format();
return ret;
}
-LOG_TEST_FLAGS(log_test_disable, UT_TESTF_CONSOLE_REC);
+LOG_TEST_FLAGS(log_test_disable, UTF_CONSOLE);
/* Check denying based on category */
int log_test_cat_deny(struct unit_test_state *uts)
@@ -335,7 +323,6 @@
LOGFF_DENY);
ut_assert(filt2 >= 0);
- ut_assertok(console_record_reset_enable());
log_run_cat(UCLASS_SPI);
check_log_entries_none();
@@ -343,7 +330,7 @@
ut_assertok(log_remove_filter("console", filt2));
return 0;
}
-LOG_TEST_FLAGS(log_test_cat_deny, UT_TESTF_CONSOLE_REC);
+LOG_TEST_FLAGS(log_test_cat_deny, UTF_CONSOLE);
/* Check denying based on file */
int log_test_file_deny(struct unit_test_state *uts)
@@ -356,7 +343,6 @@
LOGFF_DENY);
ut_assert(filt2 >= 0);
- ut_assertok(console_record_reset_enable());
log_run_file("file");
check_log_entries_none();
@@ -364,7 +350,7 @@
ut_assertok(log_remove_filter("console", filt2));
return 0;
}
-LOG_TEST_FLAGS(log_test_file_deny, UT_TESTF_CONSOLE_REC);
+LOG_TEST_FLAGS(log_test_file_deny, UTF_CONSOLE);
/* Check denying based on level */
int log_test_level_deny(struct unit_test_state *uts)
@@ -377,17 +363,16 @@
LOGFF_DENY);
ut_assert(filt2 >= 0);
- ut_assertok(console_record_reset_enable());
log_run();
- check_log_entries_flags_levels(EXPECT_LOG | EXPECT_DIRECT | EXPECT_FORCE,
- LOGL_WARNING + 1,
- min(gd->default_log_level, LOGL_INFO));
+ check_log_entries_flags_levels(
+ EXPECT_LOG | EXPECT_DIRECT | EXPECT_FORCE,
+ LOGL_WARNING + 1, min((int)gd->default_log_level, LOGL_INFO));
ut_assertok(log_remove_filter("console", filt1));
ut_assertok(log_remove_filter("console", filt2));
return 0;
}
-LOG_TEST_FLAGS(log_test_level_deny, UT_TESTF_CONSOLE_REC);
+LOG_TEST_FLAGS(log_test_level_deny, UTF_CONSOLE);
/* Check matching based on minimum level */
int log_test_min(struct unit_test_state *uts)
@@ -401,7 +386,6 @@
LOGFF_DENY | LOGFF_LEVEL_MIN);
ut_assert(filt2 >= 0);
- ut_assertok(console_record_reset_enable());
log_run();
check_log_entries_flags_levels(EXPECT_LOG | EXPECT_DIRECT | EXPECT_FORCE,
LOGL_WARNING, LOGL_INFO - 1);
@@ -410,7 +394,7 @@
ut_assertok(log_remove_filter("console", filt2));
return 0;
}
-LOG_TEST_FLAGS(log_test_min, UT_TESTF_CONSOLE_REC);
+LOG_TEST_FLAGS(log_test_min, UTF_CONSOLE);
/* Check dropped traces */
int log_test_dropped(struct unit_test_state *uts)
@@ -419,8 +403,6 @@
gd->flags &= ~(GD_FLG_LOG_READY);
gd->log_drop_count = 0;
- ut_assertok(console_record_reset_enable());
-
log_run();
ut_asserteq(2 * (LOGL_COUNT - LOGL_FIRST) +
_LOG_MAX_LEVEL - LOGL_FIRST + 1,
@@ -432,7 +414,7 @@
return 0;
}
-LOG_TEST_FLAGS(log_test_dropped, UT_TESTF_CONSOLE_REC);
+LOG_TEST_FLAGS(log_test_dropped, UTF_CONSOLE);
/* Check log_buffer() */
int log_test_buffer(struct unit_test_state *uts)
@@ -446,17 +428,18 @@
for (i = 0; i < 0x11; i++)
buf[i] = i * 0x11;
- ut_assertok(console_record_reset_enable());
log_buffer(LOGC_BOOT, LOGL_INFO, 0, buf, 1, 0x12, 0);
/* This one should product no output due to the debug level */
log_buffer(LOGC_BOOT, LOGL_DEBUG, 0, buf, 1, 0x12, 0);
- ut_assert_nextline("00000000: 00 11 22 33 44 55 66 77 88 99 aa bb cc dd ee ff ..\"3DUfw........");
- ut_assert_nextline("00000010: 10 00 ..");
+ ut_assert_nextline(
+ " log_test_buffer() 00000000: 00 11 22 33 44 55 66 77 88 99 aa bb cc dd ee ff ..\"3DUfw........");
+ ut_assert_nextline(
+ " log_test_buffer() 00000010: 10 00 ..");
ut_assert_console_end();
free(buf);
return 0;
}
-LOG_TEST_FLAGS(log_test_buffer, UT_TESTF_CONSOLE_REC);
+LOG_TEST_FLAGS(log_test_buffer, UTF_CONSOLE);
diff --git a/test/log/nolog_ndebug.c b/test/log/nolog_ndebug.c
index b714a16..4dc0f2d 100644
--- a/test/log/nolog_ndebug.c
+++ b/test/log/nolog_ndebug.c
@@ -21,7 +21,6 @@
int i;
memset(buf, 0, BUFFSIZE);
- console_record_reset_enable();
/* Output a log record at every level */
for (i = LOGL_EMERG; i < LOGL_COUNT; i++)
@@ -31,7 +30,7 @@
/* Since DEBUG is not defined, we expect to not get debug output */
for (i = LOGL_EMERG; i < LOGL_DEBUG; i++)
ut_assertok(ut_check_console_line(uts, "testing level %d", i));
- ut_assertok(ut_check_console_end(uts));
+ ut_assert_console_end();
return 0;
}
diff --git a/test/log/nolog_test.c b/test/log/nolog_test.c
index c4c0fa6..341dbfc 100644
--- a/test/log/nolog_test.c
+++ b/test/log/nolog_test.c
@@ -25,11 +25,10 @@
char buf[BUFFSIZE];
memset(buf, 0, BUFFSIZE);
- console_record_reset_enable();
log_err("testing %s\n", "log_err");
gd->flags &= ~GD_FLG_RECORD;
ut_assertok(ut_check_console_line(uts, "testing log_err"));
- ut_assertok(ut_check_console_end(uts));
+ ut_assert_console_end();
return 0;
}
LOG_TEST(log_test_nolog_err);
@@ -39,11 +38,10 @@
char buf[BUFFSIZE];
memset(buf, 0, BUFFSIZE);
- console_record_reset_enable();
log_warning("testing %s\n", "log_warning");
gd->flags &= ~GD_FLG_RECORD;
ut_assertok(ut_check_console_line(uts, "testing log_warning"));
- ut_assertok(ut_check_console_end(uts));
+ ut_assert_console_end();
return 0;
}
LOG_TEST(log_test_nolog_warning);
@@ -53,11 +51,10 @@
char buf[BUFFSIZE];
memset(buf, 0, BUFFSIZE);
- console_record_reset_enable();
log_notice("testing %s\n", "log_notice");
gd->flags &= ~GD_FLG_RECORD;
ut_assertok(ut_check_console_line(uts, "testing log_notice"));
- ut_assertok(ut_check_console_end(uts));
+ ut_assert_console_end();
return 0;
}
LOG_TEST(log_test_nolog_notice);
@@ -67,11 +64,10 @@
char buf[BUFFSIZE];
memset(buf, 0, BUFFSIZE);
- console_record_reset_enable();
log_err("testing %s\n", "log_info");
gd->flags &= ~GD_FLG_RECORD;
ut_assertok(ut_check_console_line(uts, "testing log_info"));
- ut_assertok(ut_check_console_end(uts));
+ ut_assert_console_end();
return 0;
}
LOG_TEST(log_test_nolog_info);
@@ -83,10 +79,9 @@
char buf[BUFFSIZE];
memset(buf, 0, BUFFSIZE);
- console_record_reset_enable();
debug("testing %s\n", "debug");
gd->flags &= ~GD_FLG_RECORD;
- ut_assertok(ut_check_console_end(uts));
+ ut_assert_console_end();
return 0;
}
LOG_TEST(nolog_test_nodebug);
@@ -96,11 +91,10 @@
char buf[BUFFSIZE];
memset(buf, 0, BUFFSIZE);
- console_record_reset_enable();
log_debug("testing %s\n", "log_debug");
gd->flags &= ~GD_FLG_RECORD;
ut_assert(!strcmp(buf, ""));
- ut_assertok(ut_check_console_end(uts));
+ ut_assert_console_end();
return 0;
}
LOG_TEST(log_test_nolog_nodebug);
@@ -112,11 +106,10 @@
char buf[BUFFSIZE];
memset(buf, 0, BUFFSIZE);
- console_record_reset_enable();
debug("testing %s\n", "debug");
gd->flags &= ~GD_FLG_RECORD;
ut_assertok(ut_check_console_line(uts, "testing debug"));
- ut_assertok(ut_check_console_end(uts));
+ ut_assert_console_end();
return 0;
}
LOG_TEST(nolog_test_debug);
@@ -126,13 +119,12 @@
char buf[BUFFSIZE];
memset(buf, 0, BUFFSIZE);
- console_record_reset_enable();
log_debug("testing %s\n", "log_debug");
log(LOGC_NONE, LOGL_DEBUG, "more %s\n", "log_debug");
gd->flags &= ~GD_FLG_RECORD;
ut_assertok(ut_check_console_line(uts, "testing log_debug"));
ut_assertok(ut_check_console_line(uts, "more log_debug"));
- ut_assertok(ut_check_console_end(uts));
+ ut_assert_console_end();
return 0;
}
LOG_TEST(log_test_nolog_debug);
diff --git a/test/log/pr_cont_test.c b/test/log/pr_cont_test.c
index 30f30d9..7734e92 100644
--- a/test/log/pr_cont_test.c
+++ b/test/log/pr_cont_test.c
@@ -28,14 +28,13 @@
/* Write two messages, the second continuing the first */
gd->log_fmt = BIT(LOGF_MSG);
gd->default_log_level = LOGL_INFO;
- console_record_reset_enable();
pr_err("ea%d ", 1);
pr_cont("cc%d\n", 2);
gd->default_log_level = log_level;
gd->log_fmt = log_fmt;
gd->flags &= ~GD_FLG_RECORD;
ut_assertok(ut_check_console_line(uts, "ea1 cc2"));
- ut_assertok(ut_check_console_end(uts));
+ ut_assert_console_end();
return 0;
}
diff --git a/test/overlay/Kconfig b/test/overlay/Kconfig
index a4f1544..8818489 100644
--- a/test/overlay/Kconfig
+++ b/test/overlay/Kconfig
@@ -1,6 +1,6 @@
config UT_OVERLAY
bool "Enable Device Tree Overlays Unit Tests"
- depends on UNIT_TEST && OF_CONTROL
+ depends on UNIT_TEST && OF_CONTROL && SANDBOX
default y
select OF_LIBFDT_OVERLAY
help
diff --git a/test/print_ut.c b/test/print_ut.c
index 53d3354..f5e607b 100644
--- a/test/print_ut.c
+++ b/test/print_ut.c
@@ -180,14 +180,12 @@
buf[i] = i * 0x11;
/* bytes */
- console_record_reset();
print_buffer(0, buf, 1, 0x12, 0);
ut_assert_nextline("00000000: 00 11 22 33 44 55 66 77 88 99 aa bb cc dd ee ff ..\"3DUfw........");
ut_assert_nextline("00000010: 10 00 ..");
ut_assert_console_end();
/* line length */
- console_record_reset();
print_buffer(0, buf, 1, 0x12, 8);
ut_assert_nextline("00000000: 00 11 22 33 44 55 66 77 ..\"3DUfw");
ut_assert_nextline("00000008: 88 99 aa bb cc dd ee ff ........");
@@ -195,7 +193,6 @@
ut_assert_console_end();
/* long line */
- console_record_reset();
buf[0x41] = 0x41;
print_buffer(0, buf, 1, 0x42, 0x40);
ut_assert_nextline("00000000: 00 11 22 33 44 55 66 77 88 99 aa bb cc dd ee ff 10 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ..\"3DUfw........................................................");
@@ -203,35 +200,30 @@
ut_assert_console_end();
/* address */
- console_record_reset();
print_buffer(0x12345678, buf, 1, 0x12, 0);
ut_assert_nextline("12345678: 00 11 22 33 44 55 66 77 88 99 aa bb cc dd ee ff ..\"3DUfw........");
ut_assert_nextline("12345688: 10 00 ..");
ut_assert_console_end();
/* 16-bit */
- console_record_reset();
print_buffer(0, buf, 2, 9, 0);
ut_assert_nextline("00000000: 1100 3322 5544 7766 9988 bbaa ddcc ffee ..\"3DUfw........");
ut_assert_nextline("00000010: 0010 ..");
ut_assert_console_end();
/* 32-bit */
- console_record_reset();
print_buffer(0, buf, 4, 5, 0);
ut_assert_nextline("00000000: 33221100 77665544 bbaa9988 ffeeddcc ..\"3DUfw........");
ut_assert_nextline("00000010: 00000010 ....");
ut_assert_console_end();
/* 64-bit */
- console_record_reset();
print_buffer(0, buf, 8, 3, 0);
ut_assert_nextline("00000000: 7766554433221100 ffeeddccbbaa9988 ..\"3DUfw........");
ut_assert_nextline("00000010: 0000000000000010 ........");
ut_assert_console_end();
/* ASCII */
- console_record_reset();
buf[1] = 31;
buf[2] = 32;
buf[3] = 33;
@@ -246,7 +238,7 @@
return 0;
}
-PRINT_TEST(print_display_buffer, UT_TESTF_CONSOLE_REC);
+PRINT_TEST(print_display_buffer, UTF_CONSOLE);
static int print_hexdump_line(struct unit_test_state *uts)
{
@@ -272,7 +264,7 @@
return 0;
}
-PRINT_TEST(print_hexdump_line, UT_TESTF_CONSOLE_REC);
+PRINT_TEST(print_hexdump_line, UTF_CONSOLE);
static int print_do_hex_dump(struct unit_test_state *uts)
{
@@ -289,7 +281,6 @@
buf[i] = i * 0x11;
/* bytes */
- console_record_reset();
print_hex_dump_bytes("", DUMP_PREFIX_ADDRESS, buf, 0x12);
ut_assert_nextline("%0*lx: 00 11 22 33 44 55 66 77 88 99 aa bb cc dd ee ff ..\"3DUfw........",
IS_ENABLED(CONFIG_PHYS_64BIT) ? 16 : 8, 0x0UL);
@@ -298,7 +289,6 @@
ut_assert_console_end();
/* line length */
- console_record_reset();
print_hex_dump("", DUMP_PREFIX_ADDRESS, 8, 1, buf, 0x12, true);
ut_assert_nextline("%0*lx: 00 11 22 33 44 55 66 77 ..\"3DUfw",
IS_ENABLED(CONFIG_PHYS_64BIT) ? 16 : 8, 0x0UL);
@@ -310,7 +300,6 @@
unmap_sysmem(buf);
/* long line */
- console_record_reset();
buf[0x41] = 0x41;
print_hex_dump("", DUMP_PREFIX_ADDRESS, 0x40, 1, buf, 0x42, true);
ut_assert_nextline("%0*lx: 00 11 22 33 44 55 66 77 88 99 aa bb cc dd ee ff 10 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ..\"3DUfw........................................................",
@@ -320,7 +309,6 @@
ut_assert_console_end();
/* 16-bit */
- console_record_reset();
print_hex_dump("", DUMP_PREFIX_ADDRESS, 0, 2, buf, 0x12, true);
ut_assert_nextline("%0*lx: 1100 3322 5544 7766 9988 bbaa ddcc ffee ..\"3DUfw........",
IS_ENABLED(CONFIG_PHYS_64BIT) ? 16 : 8, 0x0UL);
@@ -330,7 +318,6 @@
unmap_sysmem(buf);
/* 32-bit */
- console_record_reset();
print_hex_dump("", DUMP_PREFIX_ADDRESS, 0, 4, buf, 0x14, true);
ut_assert_nextline("%0*lx: 33221100 77665544 bbaa9988 ffeeddcc ..\"3DUfw........",
IS_ENABLED(CONFIG_PHYS_64BIT) ? 16 : 8, 0x0UL);
@@ -340,7 +327,6 @@
unmap_sysmem(buf);
/* 64-bit */
- console_record_reset();
print_hex_dump("", DUMP_PREFIX_ADDRESS, 16, 8, buf, 0x18, true);
ut_assert_nextline("%0*lx: 7766554433221100 ffeeddccbbaa9988 ..\"3DUfw........",
IS_ENABLED(CONFIG_PHYS_64BIT) ? 16 : 8, 0x0UL);
@@ -350,7 +336,6 @@
unmap_sysmem(buf);
/* ASCII */
- console_record_reset();
buf[1] = 31;
buf[2] = 32;
buf[3] = 33;
@@ -365,7 +350,7 @@
return 0;
}
-PRINT_TEST(print_do_hex_dump, UT_TESTF_CONSOLE_REC);
+PRINT_TEST(print_do_hex_dump, UTF_CONSOLE);
static int snprint(struct unit_test_state *uts)
{
diff --git a/test/py/tests/test_upl.py b/test/py/tests/test_upl.py
new file mode 100644
index 0000000..3164bda
--- /dev/null
+++ b/test/py/tests/test_upl.py
@@ -0,0 +1,38 @@
+# SPDX-License-Identifier: GPL-2.0+
+# Copyright 2024 Google LLC
+#
+# Test addition of Universal Payload
+
+import os
+
+import pytest
+import u_boot_utils
+
+@pytest.mark.boardspec('sandbox_vpl')
+def test_upl_handoff(u_boot_console):
+ """Test of UPL handoff
+
+ This works by starting up U-Boot VPL, which gets to SPL and then sets up a
+ UPL handoff using the FIT containing U-Boot proper. It then jumps to U-Boot
+ proper and runs a test to check that the parameters are correct.
+
+ The entire FIT is loaded into memory in SPL (in upl_load_from_image()) so
+ that it can be inpected in upl_test_info_norun
+ """
+ cons = u_boot_console
+ ram = os.path.join(cons.config.build_dir, 'ram.bin')
+ fdt = os.path.join(cons.config.build_dir, 'u-boot.dtb')
+
+ # Remove any existing RAM file, so we don't have old data present
+ if os.path.exists(ram):
+ os.remove(ram)
+ flags = ['-m', ram, '-d', fdt, '--upl']
+ cons.restart_uboot_with_flags(flags, use_dtb=False)
+
+ # Make sure that Universal Payload is detected in U-Boot proper
+ output = cons.run_command('upl info')
+ assert 'UPL state: active' == output
+
+ # Check the FIT offsets look correct
+ output = cons.run_command('ut upl -f upl_test_info_norun')
+ assert 'Failures: 0' in output
diff --git a/test/str_ut.c b/test/str_ut.c
index 3897798..96e0489 100644
--- a/test/str_ut.c
+++ b/test/str_ut.c
@@ -342,9 +342,7 @@
ut_asserteq_str("space", ptr[3]);
ut_assertnonnull(ptr[4]);
ut_asserteq_str("", ptr[4]);
- ut_assertnonnull(ptr[5]);
- ut_asserteq_str("", ptr[5]);
- ut_assertnull(ptr[6]);
+ ut_assertnull(ptr[5]);
str_free_list(ptr);
ut_assertok(ut_check_delta(start));
diff --git a/test/test-main.c b/test/test-main.c
index 3fa6f6e..63e8be0 100644
--- a/test/test-main.c
+++ b/test/test-main.c
@@ -181,7 +181,7 @@
{
const char *fname = strrchr(test->file, '/') + 1;
- if (!(test->flags & UT_TESTF_DM))
+ if (!(test->flags & UTF_DM))
return false;
return !strstr(fname, "video") || strstr(test->name, "video_base");
@@ -240,14 +240,14 @@
*
* @tests: List of tests to run
* @count: Number of tests to ru
- * Return: true if any of the tests have the UT_TESTF_DM flag
+ * Return: true if any of the tests have the UTF_DM flag
*/
static bool ut_list_has_dm_tests(struct unit_test *tests, int count)
{
struct unit_test *test;
for (test = tests; test < tests + count; test++) {
- if (test->flags & UT_TESTF_DM)
+ if (test->flags & UTF_DM)
return true;
}
@@ -289,26 +289,26 @@
{
ut_assertok(event_init());
- if (test->flags & UT_TESTF_DM)
+ if (test->flags & UTF_DM)
ut_assertok(dm_test_pre_run(uts));
ut_set_skip_delays(uts, false);
uts->start = mallinfo();
- if (test->flags & UT_TESTF_SCAN_PDATA)
+ if (test->flags & UTF_SCAN_PDATA)
ut_assertok(dm_scan_plat(false));
- if (test->flags & UT_TESTF_PROBE_TEST)
+ if (test->flags & UTF_PROBE_TEST)
ut_assertok(do_autoprobe(uts));
if (CONFIG_IS_ENABLED(OF_REAL) &&
- (test->flags & UT_TESTF_SCAN_FDT)) {
+ (test->flags & UTF_SCAN_FDT)) {
/*
* only set this if we know the ethernet uclass will be created
*/
- eth_set_enable_bootdevs(test->flags & UT_TESTF_ETH_BOOTDEV);
- test_sf_set_enable_bootdevs(test->flags & UT_TESTF_SF_BOOTDEV);
+ eth_set_enable_bootdevs(test->flags & UTF_ETH_BOOTDEV);
+ test_sf_set_enable_bootdevs(test->flags & UTF_SF_BOOTDEV);
ut_assertok(dm_extended_scan(false));
}
@@ -316,10 +316,10 @@
* Do this after FDT scan since dm_scan_other() in bootstd-uclass.c
* checks for the existence of bootstd
*/
- if (test->flags & UT_TESTF_SCAN_PDATA)
+ if (test->flags & UTF_SCAN_PDATA)
ut_assertok(dm_scan_other(false));
- if (IS_ENABLED(CONFIG_SANDBOX) && (test->flags & UT_TESTF_OTHER_FDT)) {
+ if (IS_ENABLED(CONFIG_SANDBOX) && (test->flags & UTF_OTHER_FDT)) {
/* make sure the other FDT is available */
ut_assertok(test_load_other_fdt(uts));
@@ -333,7 +333,7 @@
}
}
- if (test->flags & UT_TESTF_CONSOLE_REC) {
+ if (test->flags & UTF_CONSOLE) {
int ret = console_record_reset_enable();
if (ret) {
@@ -356,7 +356,7 @@
static int test_post_run(struct unit_test_state *uts, struct unit_test *test)
{
ut_unsilence_console(uts);
- if (test->flags & UT_TESTF_DM)
+ if (test->flags & UTF_DM)
ut_assertok(dm_test_post_run(uts));
ut_assertok(cyclic_unregister_all());
ut_assertok(event_uninit());
@@ -403,7 +403,7 @@
const char *note = "";
int ret;
- if ((test->flags & UT_TESTF_DM) && !uts->of_live)
+ if ((test->flags & UTF_DM) && !uts->of_live)
note = " (flat tree)";
printf("Test: %s: %s%s\n", test_name, fname, note);
@@ -450,13 +450,13 @@
{
int runs;
- if ((test->flags & UT_TESTF_OTHER_FDT) && !IS_ENABLED(CONFIG_SANDBOX))
+ if ((test->flags & UTF_OTHER_FDT) && !IS_ENABLED(CONFIG_SANDBOX))
return skip_test(uts);
/* Run with the live tree if possible */
runs = 0;
if (CONFIG_IS_ENABLED(OF_LIVE)) {
- if (!(test->flags & UT_TESTF_FLAT_TREE)) {
+ if (!(test->flags & UTF_FLAT_TREE)) {
uts->of_live = true;
ut_assertok(ut_run_test(uts, test, test->name));
runs++;
@@ -476,10 +476,10 @@
* boards)
*/
if ((!CONFIG_IS_ENABLED(OF_LIVE) ||
- (test->flags & UT_TESTF_SCAN_FDT)) &&
- !(test->flags & UT_TESTF_LIVE_TREE) &&
+ (test->flags & UTF_SCAN_FDT)) &&
+ !(test->flags & UTF_LIVE_TREE) &&
(CONFIG_IS_ENABLED(OFNODE_MULTI_TREE) ||
- !(test->flags & UT_TESTF_OTHER_FDT)) &&
+ !(test->flags & UTF_OTHER_FDT)) &&
(!runs || ut_test_run_on_flattree(test)) &&
!(gd->flags & GD_FLG_FDT_CHANGED)) {
uts->of_live = false;
@@ -540,7 +540,7 @@
if (!test_matches(prefix, test_name, select_name))
continue;
- if (test->flags & UT_TESTF_MANUAL) {
+ if (test->flags & UTF_MANUAL) {
int len;
/*
diff --git a/test/ut.c b/test/ut.c
index ae99831..7454da3 100644
--- a/test/ut.c
+++ b/test/ut.c
@@ -59,9 +59,11 @@
ut_fail(uts, __FILE__, __LINE__, __func__,
"Console record buffer too small - increase CONFIG_CONSOLE_RECORD_OUT_SIZE");
return ret;
+ } else if (ret == -ENOENT) {
+ strcpy(uts->actual_str, "<no-more-output>");
}
- return 0;
+ return ret;
}
int ut_check_console_line(struct unit_test_state *uts, const char *fmt, ...)
@@ -79,8 +81,8 @@
return -EOVERFLOW;
}
ret = readline_check(uts);
- if (ret < 0)
- return ret;
+ if (ret == -ENOENT)
+ return 1;
return strcmp(uts->expect_str, uts->actual_str);
}
diff --git a/tools/buildman/test.py b/tools/buildman/test.py
index bfad309..e9d2c7e 100644
--- a/tools/buildman/test.py
+++ b/tools/buildman/test.py
@@ -779,6 +779,7 @@
tmpdir = self.base_dir
with (patch('time.time', side_effect=self.get_time),
+ patch('time.monotonic', side_effect=self.get_time),
patch('time.sleep', side_effect=self.inc_time),
patch('os.kill', side_effect=self.kill)):
# Grab the process. Since there is no other profcess, this should