Merge patch series "bootm: Refactoring to reduce reliance on CMDLINE (part A)"
To quote the author:
It would be useful to be able to boot an OS when CONFIG_CMDLINE is
disabled. This could allow reduced code size.
Standard boot provides a way to handle programmatic boot, without
scripts, so such a feature is possible. The main impediment is the
inability to use the booting features of U-Boot without a command line.
So the solution is to avoid passing command arguments and the like to
code in boot/
A similar process has taken place with filesystems, for example, where
we have (somewhat) separate Kconfig options for the filesystem commands
and the filesystems themselves.
This series starts the process of refactoring the bootm logic so that
it can be called from standard boot without using the command line.
Mostly it removes the use of argc, argv and cmdtbl from the internal
logic.
Some limited tidy-up is included, but this is kept to smaller patches,
rather than trying to remove all #ifdefs etc. Some function comments
are added, however.
A simple programmatic boot is provided as a starting point.
This work will likely take many series, so this is just the start.
Size growth with this series for firefly-rk3288 (Thumb2) is:
arm: (for 1/1 boards) all +23.0 rodata -49.0 text +72.0
This should be removed by:
https://source.denx.de/u-boot/custodians/u-boot-dm/-/issues/11
but it is not included in this series as it is already large enough.
No functional change is intended in this series.
Changes in v3:
- Add a panic if programmatic boot fails
- Drop RFC tag
Changes in v2:
- Add new patch to adjust position of unmap_sysmem() in boot_get_kernel()
- Add new patch to obtain command arguments
- Fix 'boot_find_os' typo
- Pass in the command name
- Use the command table to provide the command name, instead of "bootm"
diff --git a/.gitignore b/.gitignore
index a1a79e9..3301481 100644
--- a/.gitignore
+++ b/.gitignore
@@ -61,7 +61,6 @@
# Generated files
#
/spl/
-/tools/generated/
/tpl/
/defconfig
diff --git a/Kconfig b/Kconfig
index 7df91d7..00ed1ec 100644
--- a/Kconfig
+++ b/Kconfig
@@ -327,7 +327,7 @@
malloc() region in SDRAM once it is inited.
config TPL_SYS_MALLOC_F
- bool "Enable malloc() pool in SPL"
+ bool "Enable malloc() pool in TPL"
depends on SYS_MALLOC_F && TPL
default y if SPL_SYS_MALLOC_F
help
diff --git a/MAINTAINERS b/MAINTAINERS
index 091e6bb..92814a4 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -58,7 +58,7 @@
ANDROID AB
M: Igor Opaniuk <igor.opaniuk@gmail.com>
-R: Sam Protsenko <joe.skb7@gmail.com>
+R: Sam Protsenko <semen.protsenko@linaro.org>
S: Maintained
F: cmd/ab_select.c
F: common/android_ab.c
@@ -667,11 +667,14 @@
F: tools/sunxi*
ARM TEGRA
-M: Tom Warren <twarren@nvidia.com>
+M: Thierry Reding <treding@nvidia.com>
+M: Svyatoslav Ryhel <clamor95@gmail.com>
S: Maintained
T: git https://source.denx.de/u-boot/custodians/u-boot-tegra.git
-F: arch/arm/mach-tegra/
+F: arch/arm/dts/tegra*
F: arch/arm/include/asm/arch-tegra*/
+F: arch/arm/mach-tegra/
+F: drivers/*/tegra*
ARM TI
M: Tom Rini <trini@konsulko.com>
@@ -950,6 +953,7 @@
DFU
M: Lukasz Majewski <lukma@denx.de>
+M: Mattijs Korpershoek <mkorpershoek@baylibre.com>
S: Maintained
T: git https://source.denx.de/u-boot/custodians/u-boot-dfu.git
F: cmd/dfu.c
@@ -1056,7 +1060,8 @@
F: test/py/tests/test_event_dump.py
FASTBOOT
-S: Orphaned
+M: Mattijs Korpershoek <mkorpershoek@baylibre.com>
+S: Maintained
F: cmd/fastboot.c
F: doc/android/fastboot*.rst
F: include/fastboot.h
@@ -1546,6 +1551,11 @@
S: Maintained
F: drivers/video/tda19988.c
+TI LP5562 LED DRIVER
+M: Rasmus Villemoes <rasmus.villemoes@prevas.dk>
+S: Supported
+F: drivers/led/led_lp5562.c
+
TI SYSTEM SECURITY
M: Andrew F. Davis <afd@ti.com>
S: Supported
diff --git a/Makefile b/Makefile
index b2e9cd3..43998da 100644
--- a/Makefile
+++ b/Makefile
@@ -3,7 +3,7 @@
VERSION = 2024
PATCHLEVEL = 01
SUBLEVEL =
-EXTRAVERSION = -rc2
+EXTRAVERSION = -rc4
NAME =
# *DOCUMENTATION*
@@ -750,6 +750,7 @@
ifeq ($(CONFIG_STACKPROTECTOR),y)
KBUILD_CFLAGS += $(call cc-option,-fstack-protector-strong)
+KBUILD_CFLAGS += $(call cc-option,-mstack-protector-guard=global)
CFLAGS_EFI += $(call cc-option,-fno-stack-protector)
else
KBUILD_CFLAGS += $(call cc-option,-fno-stack-protector)
diff --git a/README b/README
index f26c34a..ab4cda5 100644
--- a/README
+++ b/README
@@ -1191,11 +1191,10 @@
Support for a lightweight UBI (fastmap) scanner and
loader
- CONFIG_SYS_NAND_5_ADDR_CYCLE, CONFIG_SYS_NAND_PAGE_COUNT,
- CONFIG_SYS_NAND_PAGE_SIZE, CONFIG_SYS_NAND_OOBSIZE,
- CONFIG_SYS_NAND_BLOCK_SIZE, CONFIG_SYS_NAND_BAD_BLOCK_POS,
- CFG_SYS_NAND_ECCPOS, CFG_SYS_NAND_ECCSIZE,
- CFG_SYS_NAND_ECCBYTES
+ CONFIG_SYS_NAND_5_ADDR_CYCLE, CONFIG_SYS_NAND_PAGE_SIZE,
+ CONFIG_SYS_NAND_OOBSIZE, CONFIG_SYS_NAND_BLOCK_SIZE,
+ CONFIG_SYS_NAND_BAD_BLOCK_POS, CFG_SYS_NAND_ECCPOS,
+ CFG_SYS_NAND_ECCSIZE, CFG_SYS_NAND_ECCBYTES
Defines the size and behavior of the NAND that SPL uses
to read U-Boot
diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
index a6f0018..1fd7aac 100644
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@ -568,6 +568,7 @@
select GPIO_EXTRA_HEADER
select SPL_BOARD_INIT if SPL && !TARGET_SMARTWEB
select SPL_SEPARATE_BSS if SPL
+ imply SYS_THUMB_BUILD
config ARCH_DAVINCI
bool "TI DaVinci"
diff --git a/arch/arm/cpu/armv7/mpu_v7r.c b/arch/arm/cpu/armv7/mpu_v7r.c
index 57ab640..1d31c63 100644
--- a/arch/arm/cpu/armv7/mpu_v7r.c
+++ b/arch/arm/cpu/armv7/mpu_v7r.c
@@ -2,7 +2,7 @@
/*
* Cortex-R Memory Protection Unit specific code
*
- * Copyright (C) 2018 Texas Instruments Incorporated - http://www.ti.com/
+ * Copyright (C) 2018 Texas Instruments Incorporated - https://www.ti.com/
* Lokesh Vutla <lokeshvutla@ti.com>
*/
diff --git a/arch/arm/cpu/armv8/cache_v8.c b/arch/arm/cpu/armv8/cache_v8.c
index cb1131a..6973340 100644
--- a/arch/arm/cpu/armv8/cache_v8.c
+++ b/arch/arm/cpu/armv8/cache_v8.c
@@ -93,16 +93,10 @@
if (el == 1) {
tcr = TCR_EL1_RSVD | (ips << 32) | TCR_EPD1_DISABLE;
- if (gd->arch.has_hafdbs)
- tcr |= TCR_EL1_HA | TCR_EL1_HD;
} else if (el == 2) {
tcr = TCR_EL2_RSVD | (ips << 16);
- if (gd->arch.has_hafdbs)
- tcr |= TCR_EL2_HA | TCR_EL2_HD;
} else {
tcr = TCR_EL3_RSVD | (ips << 16);
- if (gd->arch.has_hafdbs)
- tcr |= TCR_EL3_HA | TCR_EL3_HD;
}
/* PTWs cacheable, inner/outer WBWA and inner shareable */
@@ -206,9 +200,6 @@
attrs != PTE_BLOCK_MEMTYPE(MT_NORMAL_NC))
continue;
- if (gd->arch.has_hafdbs && (pte & (PTE_RDONLY | PTE_DBM)) != PTE_DBM)
- continue;
-
end = va + BIT(level2shift(level)) - 1;
/* No intersection with RAM? */
@@ -318,7 +309,7 @@
for (i = idx; size; i++) {
u64 next_size, *next_table;
- if (level >= gd->arch.first_block_level &&
+ if (level >= 1 &&
size >= map_size && !(virt & (map_size - 1))) {
if (level == 3)
table[i] = phys | attrs | PTE_TYPE_PAGE;
@@ -357,12 +348,6 @@
if (va_bits < 39)
level = 1;
- if (!gd->arch.first_block_level)
- gd->arch.first_block_level = 1;
-
- if (gd->arch.has_hafdbs)
- attrs |= PTE_DBM | PTE_RDONLY;
-
map_range(map->virt, map->phys, map->size, level,
(u64 *)gd->arch.tlb_addr, attrs);
}
@@ -376,7 +361,7 @@
for (i = idx; size; i++) {
u64 next_size;
- if (level >= gd->arch.first_block_level &&
+ if (level >= 1 &&
size >= map_size && !(virt & (map_size - 1))) {
virt += map_size;
size -= map_size;
@@ -414,16 +399,7 @@
__weak u64 get_page_table_size(void)
{
u64 one_pt = MAX_PTE_ENTRIES * sizeof(u64);
- u64 size, mmfr1;
-
- asm volatile("mrs %0, id_aa64mmfr1_el1" : "=r" (mmfr1));
- if ((mmfr1 & 0xf) == 2) {
- gd->arch.has_hafdbs = true;
- gd->arch.first_block_level = 2;
- } else {
- gd->arch.has_hafdbs = false;
- gd->arch.first_block_level = 1;
- }
+ u64 size;
/* Account for all page tables we would need to cover our memory map */
size = one_pt * count_ranges();
diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile
index e0a0d43..ea420db 100644
--- a/arch/arm/dts/Makefile
+++ b/arch/arm/dts/Makefile
@@ -194,6 +194,7 @@
rk3588-nanopc-t6.dtb \
rk3588s-orangepi-5.dtb \
rk3588-orangepi-5-plus.dtb \
+ rk3588-quartzpro64.dtb \
rk3588s-rock-5a.dtb \
rk3588-rock-5b.dtb
@@ -376,6 +377,12 @@
zynq-cse-nand.dtb \
zynq-cse-nor.dtb \
zynq-cse-qspi-single.dtb \
+ zynq-cse-qspi-parallel.dtb \
+ zynq-cse-qspi-stacked.dtb \
+ zynq-cse-qspi-x1-single.dtb \
+ zynq-cse-qspi-x1-stacked.dtb \
+ zynq-cse-qspi-x2-single.dtb \
+ zynq-cse-qspi-x2-stacked.dtb \
zynq-dlc20-rev1.0.dtb \
zynq-microzed.dtb \
zynq-minized.dtb \
@@ -417,6 +424,13 @@
zynqmp-mini-emmc1.dtb \
zynqmp-mini-nand.dtb \
zynqmp-mini-qspi.dtb \
+ zynqmp-mini-qspi-parallel.dtb \
+ zynqmp-mini-qspi-single.dtb \
+ zynqmp-mini-qspi-stacked.dtb \
+ zynqmp-mini-qspi-x1-single.dtb \
+ zynqmp-mini-qspi-x1-stacked.dtb \
+ zynqmp-mini-qspi-x2-single.dtb \
+ zynqmp-mini-qspi-x2-stacked.dtb \
zynqmp-sc-revB.dtb \
zynqmp-sc-revC.dtb \
zynqmp-sc-vek280-revA.dtbo \
@@ -467,13 +481,27 @@
versal-mini-emmc0.dtb \
versal-mini-emmc1.dtb \
versal-mini-ospi-single.dtb \
+ versal-mini-ospi-stacked.dtb \
+ versal-mini-qspi-parallel.dtb \
versal-mini-qspi-single.dtb \
+ versal-mini-qspi-stacked.dtb \
+ versal-mini-qspi-x1-single.dtb \
+ versal-mini-qspi-x1-stacked.dtb \
+ versal-mini-qspi-x2-single.dtb \
+ versal-mini-qspi-x2-stacked.dtb \
xilinx-versal-virt.dtb
dtb-$(CONFIG_ARCH_VERSAL_NET) += \
versal-net-mini.dtb \
versal-net-mini-emmc.dtb \
versal-net-mini-ospi-single.dtb \
+ versal-net-mini-ospi-stacked.dtb \
versal-net-mini-qspi-single.dtb \
+ versal-net-mini-qspi-parallel.dtb \
+ versal-net-mini-qspi-stacked.dtb \
+ versal-net-mini-qspi-x1-single.dtb \
+ versal-net-mini-qspi-x1-stacked.dtb \
+ versal-net-mini-qspi-x2-single.dtb \
+ versal-net-mini-qspi-x2-stacked.dtb \
xilinx-versal-net-virt.dtb
dtb-$(CONFIG_ARCH_ZYNQMP_R5) += \
zynqmp-r5.dtb
@@ -693,6 +721,7 @@
sun7i-a20-haoyu-marsboard.dtb \
sun7i-a20-hummingbird.dtb \
sun7i-a20-i12-tvbox.dtb \
+ sun7i-a20-icnova-a20-adb4006.dtb \
sun7i-a20-icnova-swac.dtb \
sun7i-a20-itead-ibox.dtb \
sun7i-a20-lamobo-r1.dtb \
@@ -1371,7 +1400,10 @@
k3-j7200-common-proc-board.dtb \
k3-j7200-r5-common-proc-board.dtb \
k3-j721e-sk.dtb \
- k3-j721e-r5-sk.dtb
+ k3-j721e-r5-sk.dtb \
+ k3-j721e-beagleboneai64.dtb \
+ k3-j721e-r5-beagleboneai64.dtb
+
dtb-$(CONFIG_SOC_K3_J721S2) += k3-am68-sk-base-board.dtb\
k3-am68-sk-r5-base-board.dtb\
k3-j721s2-common-proc-board.dtb\
diff --git a/arch/arm/dts/am335x-baltos.dts b/arch/arm/dts/am335x-baltos.dts
index b3c13c9..34b87d4 100644
--- a/arch/arm/dts/am335x-baltos.dts
+++ b/arch/arm/dts/am335x-baltos.dts
@@ -1,5 +1,5 @@
/*
- * Copyright (C) 2012 Texas Instruments Incorporated - http://www.ti.com/
+ * Copyright (C) 2012 Texas Instruments Incorporated - https://www.ti.com/
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
diff --git a/arch/arm/dts/am335x-evm-u-boot.dtsi b/arch/arm/dts/am335x-evm-u-boot.dtsi
index 82a483a..72402c8 100644
--- a/arch/arm/dts/am335x-evm-u-boot.dtsi
+++ b/arch/arm/dts/am335x-evm-u-boot.dtsi
@@ -1,6 +1,6 @@
// SPDX-License-Identifier: GPL-2.0+
/*
- * Copyright (C) 2017 Texas Instruments Incorporated - http://www.ti.com/
+ * Copyright (C) 2017 Texas Instruments Incorporated - https://www.ti.com/
*/
#include "am33xx-u-boot.dtsi"
diff --git a/arch/arm/dts/am335x-evmsk.dts b/arch/arm/dts/am335x-evmsk.dts
index 5d96225..e026765 100644
--- a/arch/arm/dts/am335x-evmsk.dts
+++ b/arch/arm/dts/am335x-evmsk.dts
@@ -5,7 +5,7 @@
/*
* AM335x Starter Kit
- * http://www.ti.com/tool/tmdssk3358
+ * https://www.ti.com/tool/tmdssk3358
*/
/dts-v1/;
diff --git a/arch/arm/dts/am335x-icev2-u-boot.dtsi b/arch/arm/dts/am335x-icev2-u-boot.dtsi
index 67bfac9..ac1feaa 100644
--- a/arch/arm/dts/am335x-icev2-u-boot.dtsi
+++ b/arch/arm/dts/am335x-icev2-u-boot.dtsi
@@ -1,6 +1,6 @@
// SPDX-License-Identifier: GPL-2.0+
/*
- * Copyright (C) 2019 Texas Instruments Incorporated - http://www.ti.com/
+ * Copyright (C) 2019 Texas Instruments Incorporated - https://www.ti.com/
*/
#include "am33xx-u-boot.dtsi"
diff --git a/arch/arm/dts/am335x-icev2.dts b/arch/arm/dts/am335x-icev2.dts
index a542724..bcfdbb7 100644
--- a/arch/arm/dts/am335x-icev2.dts
+++ b/arch/arm/dts/am335x-icev2.dts
@@ -5,7 +5,7 @@
/*
* AM335x ICE V2 board
- * http://www.ti.com/tool/tmdsice3359
+ * https://www.ti.com/tool/tmdsice3359
*/
/dts-v1/;
diff --git a/arch/arm/dts/am335x-pxm2.dtsi b/arch/arm/dts/am335x-pxm2.dtsi
index a51d6ac..a495609 100644
--- a/arch/arm/dts/am335x-pxm2.dtsi
+++ b/arch/arm/dts/am335x-pxm2.dtsi
@@ -3,7 +3,7 @@
* Heiko Schocher <hs@denx.de>
*
* Based on:
- * Copyright (C) 2012 Texas Instruments Incorporated - http://www.ti.com/
+ * Copyright (C) 2012 Texas Instruments Incorporated - https://www.ti.com/
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
diff --git a/arch/arm/dts/am335x-pxm50.dts b/arch/arm/dts/am335x-pxm50.dts
index f4e66d2..69ed32c 100644
--- a/arch/arm/dts/am335x-pxm50.dts
+++ b/arch/arm/dts/am335x-pxm50.dts
@@ -2,7 +2,7 @@
* Copyright (C) 2014 DENX Software Engineering GmbH
* Heiko Schocher <hs@denx.de>
*
- * Copyright (C) 2012 Texas Instruments Incorporated - http://www.ti.com/
+ * Copyright (C) 2012 Texas Instruments Incorporated - https://www.ti.com/
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
diff --git a/arch/arm/dts/am335x-rut.dts b/arch/arm/dts/am335x-rut.dts
index 7760b97..0dcd561 100644
--- a/arch/arm/dts/am335x-rut.dts
+++ b/arch/arm/dts/am335x-rut.dts
@@ -3,7 +3,7 @@
* Heiko Schocher <hs@denx.de>
*
* Based on:
- * Copyright (C) 2012 Texas Instruments Incorporated - http://www.ti.com/
+ * Copyright (C) 2012 Texas Instruments Incorporated - https://www.ti.com/
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
diff --git a/arch/arm/dts/am335x-sancloud-bbe-extended-wifi.dts b/arch/arm/dts/am335x-sancloud-bbe-extended-wifi.dts
index a2676d1..271d1ab 100644
--- a/arch/arm/dts/am335x-sancloud-bbe-extended-wifi.dts
+++ b/arch/arm/dts/am335x-sancloud-bbe-extended-wifi.dts
@@ -1,7 +1,7 @@
// SPDX-License-Identifier: GPL-2.0-only
/*
* Copyright (C) 2021 Sancloud Ltd
- * Copyright (C) 2012 Texas Instruments Incorporated - http://www.ti.com/
+ * Copyright (C) 2012 Texas Instruments Incorporated - https://www.ti.com/
*/
/dts-v1/;
diff --git a/arch/arm/dts/am335x-sancloud-bbe-lite-u-boot.dtsi b/arch/arm/dts/am335x-sancloud-bbe-lite-u-boot.dtsi
index fd47bc2..db02888 100644
--- a/arch/arm/dts/am335x-sancloud-bbe-lite-u-boot.dtsi
+++ b/arch/arm/dts/am335x-sancloud-bbe-lite-u-boot.dtsi
@@ -1,6 +1,6 @@
// SPDX-License-Identifier: GPL-2.0+
/*
- * Copyright (C) 2017 Texas Instruments Incorporated - http://www.ti.com/
+ * Copyright (C) 2017 Texas Instruments Incorporated - https://www.ti.com/
* Copyright (C) 2021 SanCloud Ltd
*/
diff --git a/arch/arm/dts/am335x-sancloud-bbe-lite.dts b/arch/arm/dts/am335x-sancloud-bbe-lite.dts
index 8ffbc72..daa90f6 100644
--- a/arch/arm/dts/am335x-sancloud-bbe-lite.dts
+++ b/arch/arm/dts/am335x-sancloud-bbe-lite.dts
@@ -1,6 +1,6 @@
// SPDX-License-Identifier: GPL-2.0-only
/*
- * Copyright (C) 2012 Texas Instruments Incorporated - http://www.ti.com/
+ * Copyright (C) 2012 Texas Instruments Incorporated - https://www.ti.com/
* Copyright (C) 2021 SanCloud Ltd
*/
/dts-v1/;
diff --git a/arch/arm/dts/am4372-generic-u-boot.dtsi b/arch/arm/dts/am4372-generic-u-boot.dtsi
index 1dd0a5d..40f3756 100644
--- a/arch/arm/dts/am4372-generic-u-boot.dtsi
+++ b/arch/arm/dts/am4372-generic-u-boot.dtsi
@@ -1,6 +1,6 @@
// SPDX-License-Identifier: GPL-2.0+
/*
- * Copyright (C) 2018 Texas Instruments Incorporated - http://www.ti.com/
+ * Copyright (C) 2018 Texas Instruments Incorporated - https://www.ti.com/
*/
#include "am4372-u-boot.dtsi"
diff --git a/arch/arm/dts/am4372-generic.dts b/arch/arm/dts/am4372-generic.dts
index b8a2bb8..2524e04 100644
--- a/arch/arm/dts/am4372-generic.dts
+++ b/arch/arm/dts/am4372-generic.dts
@@ -2,7 +2,7 @@
/*
* Device Tree Source for Generic AM4372 EVM
*
- * Copyright (C) 2018 Texas Instruments Incorporated - http://www.ti.com/
+ * Copyright (C) 2018 Texas Instruments Incorporated - https://www.ti.com/
*/
/dts-v1/;
diff --git a/arch/arm/dts/am4372-u-boot.dtsi b/arch/arm/dts/am4372-u-boot.dtsi
index 2fac2fc..0c498bc 100644
--- a/arch/arm/dts/am4372-u-boot.dtsi
+++ b/arch/arm/dts/am4372-u-boot.dtsi
@@ -1,6 +1,6 @@
// SPDX-License-Identifier: GPL-2.0+
/*
- * Copyright (C) 2018 Texas Instruments Incorporated - http://www.ti.com/
+ * Copyright (C) 2018 Texas Instruments Incorporated - https://www.ti.com/
*/
/{
diff --git a/arch/arm/dts/am437x-gp-evm-u-boot.dtsi b/arch/arm/dts/am437x-gp-evm-u-boot.dtsi
index da0b136..6393170 100644
--- a/arch/arm/dts/am437x-gp-evm-u-boot.dtsi
+++ b/arch/arm/dts/am437x-gp-evm-u-boot.dtsi
@@ -1,5 +1,5 @@
/*
- * Copyright (C) 2017 Texas Instruments Incorporated - http://www.ti.com/
+ * Copyright (C) 2017 Texas Instruments Incorporated - https://www.ti.com/
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
diff --git a/arch/arm/dts/am437x-idk-evm-u-boot.dtsi b/arch/arm/dts/am437x-idk-evm-u-boot.dtsi
index 4e6ad94..7c9f80e 100644
--- a/arch/arm/dts/am437x-idk-evm-u-boot.dtsi
+++ b/arch/arm/dts/am437x-idk-evm-u-boot.dtsi
@@ -1,6 +1,6 @@
// SPDX-License-Identifier: GPL-2.0+
/*
- * Copyright (C) 2018 Texas Instruments Incorporated - http://www.ti.com/
+ * Copyright (C) 2018 Texas Instruments Incorporated - https://www.ti.com/
*/
#include "am4372-u-boot.dtsi"
diff --git a/arch/arm/dts/am437x-sk-evm-u-boot.dtsi b/arch/arm/dts/am437x-sk-evm-u-boot.dtsi
index 43e519c..580ba35 100644
--- a/arch/arm/dts/am437x-sk-evm-u-boot.dtsi
+++ b/arch/arm/dts/am437x-sk-evm-u-boot.dtsi
@@ -1,6 +1,6 @@
// SPDX-License-Identifier: GPL-2.0+
/*
- * Copyright (C) 2018 Texas Instruments Incorporated - http://www.ti.com/
+ * Copyright (C) 2018 Texas Instruments Incorporated - https://www.ti.com/
*/
#include "am4372-u-boot.dtsi"
diff --git a/arch/arm/dts/am571x-idk-u-boot.dtsi b/arch/arm/dts/am571x-idk-u-boot.dtsi
index 6519920..98a7a7e 100644
--- a/arch/arm/dts/am571x-idk-u-boot.dtsi
+++ b/arch/arm/dts/am571x-idk-u-boot.dtsi
@@ -1,5 +1,5 @@
// SPDX-License-Identifier: GPL-2.0+
/*
- * Copyright (C) 2019 Texas Instruments Incorporated - http://www.ti.com/
+ * Copyright (C) 2019 Texas Instruments Incorporated - https://www.ti.com/
*/
#include "am57xx-idk-common-u-boot.dtsi"
diff --git a/arch/arm/dts/am5729-beagleboneai.dts b/arch/arm/dts/am5729-beagleboneai.dts
index f772aef..75a29e6 100644
--- a/arch/arm/dts/am5729-beagleboneai.dts
+++ b/arch/arm/dts/am5729-beagleboneai.dts
@@ -1,6 +1,6 @@
// SPDX-License-Identifier: GPL-2.0
/*
- * Copyright (C) 2014-2019 Texas Instruments Incorporated - http://www.ti.com/
+ * Copyright (C) 2014-2019 Texas Instruments Incorporated - https://www.ti.com/
*/
/dts-v1/;
diff --git a/arch/arm/dts/am572x-idk-u-boot.dtsi b/arch/arm/dts/am572x-idk-u-boot.dtsi
index 6519920..98a7a7e 100644
--- a/arch/arm/dts/am572x-idk-u-boot.dtsi
+++ b/arch/arm/dts/am572x-idk-u-boot.dtsi
@@ -1,5 +1,5 @@
// SPDX-License-Identifier: GPL-2.0+
/*
- * Copyright (C) 2019 Texas Instruments Incorporated - http://www.ti.com/
+ * Copyright (C) 2019 Texas Instruments Incorporated - https://www.ti.com/
*/
#include "am57xx-idk-common-u-boot.dtsi"
diff --git a/arch/arm/dts/am574x-idk-u-boot.dtsi b/arch/arm/dts/am574x-idk-u-boot.dtsi
index 6519920..98a7a7e 100644
--- a/arch/arm/dts/am574x-idk-u-boot.dtsi
+++ b/arch/arm/dts/am574x-idk-u-boot.dtsi
@@ -1,5 +1,5 @@
// SPDX-License-Identifier: GPL-2.0+
/*
- * Copyright (C) 2019 Texas Instruments Incorporated - http://www.ti.com/
+ * Copyright (C) 2019 Texas Instruments Incorporated - https://www.ti.com/
*/
#include "am57xx-idk-common-u-boot.dtsi"
diff --git a/arch/arm/dts/am57xx-beagle-x15-revb1-u-boot.dtsi b/arch/arm/dts/am57xx-beagle-x15-revb1-u-boot.dtsi
index 49b1621..2af4e60 100644
--- a/arch/arm/dts/am57xx-beagle-x15-revb1-u-boot.dtsi
+++ b/arch/arm/dts/am57xx-beagle-x15-revb1-u-boot.dtsi
@@ -1,6 +1,6 @@
// SPDX-License-Identifier: GPL-2.0+
/*
- * Copyright (C) 2019 Texas Instruments Incorporated - http://www.ti.com/
+ * Copyright (C) 2019 Texas Instruments Incorporated - https://www.ti.com/
*/
#include "omap5-u-boot.dtsi"
diff --git a/arch/arm/dts/am57xx-beagle-x15-revc-u-boot.dtsi b/arch/arm/dts/am57xx-beagle-x15-revc-u-boot.dtsi
index 49b1621..2af4e60 100644
--- a/arch/arm/dts/am57xx-beagle-x15-revc-u-boot.dtsi
+++ b/arch/arm/dts/am57xx-beagle-x15-revc-u-boot.dtsi
@@ -1,6 +1,6 @@
// SPDX-License-Identifier: GPL-2.0+
/*
- * Copyright (C) 2019 Texas Instruments Incorporated - http://www.ti.com/
+ * Copyright (C) 2019 Texas Instruments Incorporated - https://www.ti.com/
*/
#include "omap5-u-boot.dtsi"
diff --git a/arch/arm/dts/am57xx-beagle-x15-u-boot.dtsi b/arch/arm/dts/am57xx-beagle-x15-u-boot.dtsi
index 49b1621..2af4e60 100644
--- a/arch/arm/dts/am57xx-beagle-x15-u-boot.dtsi
+++ b/arch/arm/dts/am57xx-beagle-x15-u-boot.dtsi
@@ -1,6 +1,6 @@
// SPDX-License-Identifier: GPL-2.0+
/*
- * Copyright (C) 2019 Texas Instruments Incorporated - http://www.ti.com/
+ * Copyright (C) 2019 Texas Instruments Incorporated - https://www.ti.com/
*/
#include "omap5-u-boot.dtsi"
diff --git a/arch/arm/dts/am57xx-cl-som-am57x-u-boot.dtsi b/arch/arm/dts/am57xx-cl-som-am57x-u-boot.dtsi
index 49b1621..2af4e60 100644
--- a/arch/arm/dts/am57xx-cl-som-am57x-u-boot.dtsi
+++ b/arch/arm/dts/am57xx-cl-som-am57x-u-boot.dtsi
@@ -1,6 +1,6 @@
// SPDX-License-Identifier: GPL-2.0+
/*
- * Copyright (C) 2019 Texas Instruments Incorporated - http://www.ti.com/
+ * Copyright (C) 2019 Texas Instruments Incorporated - https://www.ti.com/
*/
#include "omap5-u-boot.dtsi"
diff --git a/arch/arm/dts/am57xx-idk-common-u-boot.dtsi b/arch/arm/dts/am57xx-idk-common-u-boot.dtsi
index b07aea0..31faec4 100644
--- a/arch/arm/dts/am57xx-idk-common-u-boot.dtsi
+++ b/arch/arm/dts/am57xx-idk-common-u-boot.dtsi
@@ -1,6 +1,6 @@
// SPDX-License-Identifier: GPL-2.0+
/*
- * Copyright (C) 2019 Texas Instruments Incorporated - http://www.ti.com/
+ * Copyright (C) 2019 Texas Instruments Incorporated - https://www.ti.com/
*/
#include "omap5-u-boot.dtsi"
diff --git a/arch/arm/dts/am57xx-sbc-am57x-u-boot.dtsi b/arch/arm/dts/am57xx-sbc-am57x-u-boot.dtsi
index 49b1621..2af4e60 100644
--- a/arch/arm/dts/am57xx-sbc-am57x-u-boot.dtsi
+++ b/arch/arm/dts/am57xx-sbc-am57x-u-boot.dtsi
@@ -1,6 +1,6 @@
// SPDX-License-Identifier: GPL-2.0+
/*
- * Copyright (C) 2019 Texas Instruments Incorporated - http://www.ti.com/
+ * Copyright (C) 2019 Texas Instruments Incorporated - https://www.ti.com/
*/
#include "omap5-u-boot.dtsi"
diff --git a/arch/arm/dts/bitmain-antminer-s9.dts b/arch/arm/dts/bitmain-antminer-s9.dts
index 0228b4b..f5ad95a 100644
--- a/arch/arm/dts/bitmain-antminer-s9.dts
+++ b/arch/arm/dts/bitmain-antminer-s9.dts
@@ -52,6 +52,8 @@
&nfc0 {
status = "okay";
+ #address-cells = <1>;
+ #size-cells = <0>;
nand@0 {
reg = <0>;
};
diff --git a/arch/arm/dts/da850-lcdk-u-boot.dtsi b/arch/arm/dts/da850-lcdk-u-boot.dtsi
index bbaebcb..9ab48bc 100644
--- a/arch/arm/dts/da850-lcdk-u-boot.dtsi
+++ b/arch/arm/dts/da850-lcdk-u-boot.dtsi
@@ -2,7 +2,7 @@
/*
* da850-lcdk U-Boot Additions
*
- * Copyright (C) 2018 Texas Instruments Incorporated - http://www.ti.com/
+ * Copyright (C) 2018 Texas Instruments Incorporated - https://www.ti.com/
*/
/ {
diff --git a/arch/arm/dts/dra7-evm-u-boot.dtsi b/arch/arm/dts/dra7-evm-u-boot.dtsi
index 87b2451..3fe1fb4 100644
--- a/arch/arm/dts/dra7-evm-u-boot.dtsi
+++ b/arch/arm/dts/dra7-evm-u-boot.dtsi
@@ -1,6 +1,6 @@
// SPDX-License-Identifier: GPL-2.0+
/*
- * Copyright (C) 2017 Texas Instruments Incorporated - http://www.ti.com/
+ * Copyright (C) 2017 Texas Instruments Incorporated - https://www.ti.com/
*/
#include "omap5-u-boot.dtsi"
diff --git a/arch/arm/dts/dra7-ipu-common-early-boot.dtsi b/arch/arm/dts/dra7-ipu-common-early-boot.dtsi
index 90fc4cb..afa4595 100644
--- a/arch/arm/dts/dra7-ipu-common-early-boot.dtsi
+++ b/arch/arm/dts/dra7-ipu-common-early-boot.dtsi
@@ -1,6 +1,6 @@
// SPDX-License-Identifier: GPL-2.0+
/*
- * Copyright (C) 2019 Texas Instruments Incorporated - http://www.ti.com/
+ * Copyright (C) 2019 Texas Instruments Incorporated - https://www.ti.com/
*/
/ {
diff --git a/arch/arm/dts/dra71-evm-u-boot.dtsi b/arch/arm/dts/dra71-evm-u-boot.dtsi
index 8e7dc71..339b05f 100644
--- a/arch/arm/dts/dra71-evm-u-boot.dtsi
+++ b/arch/arm/dts/dra71-evm-u-boot.dtsi
@@ -1,6 +1,6 @@
// SPDX-License-Identifier: GPL-2.0+
/*
- * Copyright (C) 2017 Texas Instruments Incorporated - http://www.ti.com/
+ * Copyright (C) 2017 Texas Instruments Incorporated - https://www.ti.com/
*/
#include "omap5-u-boot.dtsi"
diff --git a/arch/arm/dts/dra72-evm-revc-u-boot.dtsi b/arch/arm/dts/dra72-evm-revc-u-boot.dtsi
index 8e7dc71..339b05f 100644
--- a/arch/arm/dts/dra72-evm-revc-u-boot.dtsi
+++ b/arch/arm/dts/dra72-evm-revc-u-boot.dtsi
@@ -1,6 +1,6 @@
// SPDX-License-Identifier: GPL-2.0+
/*
- * Copyright (C) 2017 Texas Instruments Incorporated - http://www.ti.com/
+ * Copyright (C) 2017 Texas Instruments Incorporated - https://www.ti.com/
*/
#include "omap5-u-boot.dtsi"
diff --git a/arch/arm/dts/dra72-evm-u-boot.dtsi b/arch/arm/dts/dra72-evm-u-boot.dtsi
index 91a3b6b..dfdd5c5 100644
--- a/arch/arm/dts/dra72-evm-u-boot.dtsi
+++ b/arch/arm/dts/dra72-evm-u-boot.dtsi
@@ -1,6 +1,6 @@
// SPDX-License-Identifier: GPL-2.0+
/*
- * Copyright (C) 2017 Texas Instruments Incorporated - http://www.ti.com/
+ * Copyright (C) 2017 Texas Instruments Incorporated - https://www.ti.com/
*/
#include "omap5-u-boot.dtsi"
diff --git a/arch/arm/dts/dra76-evm-u-boot.dtsi b/arch/arm/dts/dra76-evm-u-boot.dtsi
index 1216d93..c8da3e4 100644
--- a/arch/arm/dts/dra76-evm-u-boot.dtsi
+++ b/arch/arm/dts/dra76-evm-u-boot.dtsi
@@ -1,6 +1,6 @@
// SPDX-License-Identifier: GPL-2.0+
/*
- * Copyright (C) 2017 Texas Instruments Incorporated - http://www.ti.com/
+ * Copyright (C) 2017 Texas Instruments Incorporated - https://www.ti.com/
*/
#include "omap5-u-boot.dtsi"
diff --git a/arch/arm/dts/k3-am62-main.dtsi b/arch/arm/dts/k3-am62-main.dtsi
index 284b90c..e5c64c8 100644
--- a/arch/arm/dts/k3-am62-main.dtsi
+++ b/arch/arm/dts/k3-am62-main.dtsi
@@ -81,7 +81,8 @@
};
dmss: bus@48000000 {
- compatible = "simple-mfd";
+ bootph-all;
+ compatible = "simple-bus";
#address-cells = <2>;
#size-cells = <2>;
dma-ranges;
@@ -90,6 +91,7 @@
ti,sci-dev-id = <25>;
secure_proxy_main: mailbox@4d000000 {
+ bootph-all;
compatible = "ti,am654-secure-proxy";
#mbox-cells = <1>;
reg-names = "target_data", "rt", "scfg";
@@ -165,6 +167,7 @@
};
dmsc: system-controller@44043000 {
+ bootph-all;
compatible = "ti,k2g-sci";
ti,host-id = <12>;
mbox-names = "rx", "tx";
@@ -174,16 +177,19 @@
reg = <0x00 0x44043000 0x00 0xfe0>;
k3_pds: power-controller {
+ bootph-all;
compatible = "ti,sci-pm-domain";
#power-domain-cells = <2>;
};
k3_clks: clock-controller {
+ bootph-all;
compatible = "ti,k2g-sci-clk";
#clock-cells = <2>;
};
k3_reset: reset-controller {
+ bootph-all;
compatible = "ti,sci-reset";
#reset-cells = <2>;
};
@@ -202,6 +208,7 @@
};
secure_proxy_sa3: mailbox@43600000 {
+ bootph-pre-ram;
compatible = "ti,am654-secure-proxy";
#mbox-cells = <1>;
reg-names = "target_data", "rt", "scfg";
@@ -217,6 +224,7 @@
};
main_pmx0: pinctrl@f4000 {
+ bootph-all;
compatible = "pinctrl-single";
reg = <0x00 0xf4000 0x00 0x2ac>;
#pinctrl-cells = <1>;
@@ -225,12 +233,14 @@
};
main_esm: esm@420000 {
+ bootph-pre-ram;
compatible = "ti,j721e-esm";
reg = <0x00 0x420000 0x00 0x1000>;
ti,esm-pins = <160>, <161>, <162>, <163>, <177>, <178>;
};
main_timer0: timer@2400000 {
+ bootph-all;
compatible = "ti,am654-timer";
reg = <0x00 0x2400000 0x00 0x400>;
interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>;
diff --git a/arch/arm/dts/k3-am62-mcu.dtsi b/arch/arm/dts/k3-am62-mcu.dtsi
index 80a3e1d..0e0b234 100644
--- a/arch/arm/dts/k3-am62-mcu.dtsi
+++ b/arch/arm/dts/k3-am62-mcu.dtsi
@@ -7,6 +7,7 @@
&cbass_mcu {
mcu_pmx0: pinctrl@4084000 {
+ bootph-all;
compatible = "pinctrl-single";
reg = <0x00 0x04084000 0x00 0x88>;
#pinctrl-cells = <1>;
@@ -15,6 +16,7 @@
};
mcu_esm: esm@4100000 {
+ bootph-pre-ram;
compatible = "ti,j721e-esm";
reg = <0x00 0x4100000 0x00 0x1000>;
ti,esm-pins = <0>, <1>, <2>, <85>;
diff --git a/arch/arm/dts/k3-am62-verdin-wifi.dtsi b/arch/arm/dts/k3-am62-verdin-wifi.dtsi
index 90ddc71..a6808b1 100644
--- a/arch/arm/dts/k3-am62-verdin-wifi.dtsi
+++ b/arch/arm/dts/k3-am62-verdin-wifi.dtsi
@@ -35,5 +35,11 @@
&main_uart5 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_uart5>;
+ uart-has-rtscts;
status = "okay";
+
+ bluetooth {
+ compatible = "nxp,88w8987-bt";
+ fw-init-baudrate = <3000000>;
+ };
};
diff --git a/arch/arm/dts/k3-am62-verdin.dtsi b/arch/arm/dts/k3-am62-verdin.dtsi
index 40992e7..5db52f2 100644
--- a/arch/arm/dts/k3-am62-verdin.dtsi
+++ b/arch/arm/dts/k3-am62-verdin.dtsi
@@ -1061,6 +1061,7 @@
vddc-supply = <®_1v2_dsi>;
vddmipi-supply = <®_1v2_dsi>;
vddio-supply = <®_1v8_dsi>;
+ status = "disabled";
dsi_bridge_ports: ports {
#address-cells = <1>;
diff --git a/arch/arm/dts/k3-am62-wakeup.dtsi b/arch/arm/dts/k3-am62-wakeup.dtsi
index eae0528..fef76f5 100644
--- a/arch/arm/dts/k3-am62-wakeup.dtsi
+++ b/arch/arm/dts/k3-am62-wakeup.dtsi
@@ -7,6 +7,7 @@
&cbass_wakeup {
wkup_conf: syscon@43000000 {
+ bootph-all;
compatible = "syscon", "simple-mfd";
reg = <0x00 0x43000000 0x00 0x20000>;
#address-cells = <1>;
@@ -14,6 +15,7 @@
ranges = <0x0 0x00 0x43000000 0x20000>;
chipid: chipid@14 {
+ bootph-all;
compatible = "ti,am654-chipid";
reg = <0x14 0x4>;
};
diff --git a/arch/arm/dts/k3-am62.dtsi b/arch/arm/dts/k3-am62.dtsi
index 11f14ee..f1e1520 100644
--- a/arch/arm/dts/k3-am62.dtsi
+++ b/arch/arm/dts/k3-am62.dtsi
@@ -47,6 +47,7 @@
};
cbass_main: bus@f0000 {
+ bootph-all;
compatible = "simple-bus";
#address-cells = <2>;
#size-cells = <2>;
@@ -86,6 +87,7 @@
<0x00 0x43000000 0x00 0x43000000 0x00 0x00020000>;
cbass_mcu: bus@4000000 {
+ bootph-all;
compatible = "simple-bus";
#address-cells = <2>;
#size-cells = <2>;
@@ -93,6 +95,7 @@
};
cbass_wakeup: bus@b00000 {
+ bootph-all;
compatible = "simple-bus";
#address-cells = <2>;
#size-cells = <2>;
diff --git a/arch/arm/dts/k3-am625-beagleplay-u-boot.dtsi b/arch/arm/dts/k3-am625-beagleplay-u-boot.dtsi
index d6c6baa..a723caa 100644
--- a/arch/arm/dts/k3-am625-beagleplay-u-boot.dtsi
+++ b/arch/arm/dts/k3-am625-beagleplay-u-boot.dtsi
@@ -6,151 +6,49 @@
* Copyright (C) 2022-2023 Robert Nelson, BeagleBoard.org Foundation
*/
-#include "k3-am625-sk-binman.dtsi"
+#include "k3-binman.dtsi"
/ {
chosen {
tick-timer = &main_timer0;
};
- memory@80000000 {
- bootph-all;
- };
-
/* Keep the LEDs on by default to indicate life */
leds {
- bootph-all;
led-0 {
default-state = "on";
- bootph-all;
};
led-1 {
default-state = "on";
- bootph-all;
};
led-2 {
default-state = "on";
- bootph-all;
};
led-3 {
default-state = "on";
- bootph-all;
};
led-4 {
default-state = "on";
- bootph-all;
};
};
};
-&cbass_main {
- bootph-all;
-};
-
&main_timer0 {
clock-frequency = <25000000>;
- bootph-all;
-};
-
-&dmss {
- bootph-all;
-};
-
-&secure_proxy_main {
- bootph-all;
-};
-
-&dmsc {
- bootph-all;
-};
-
-&k3_pds {
- bootph-all;
-};
-
-&k3_clks {
- bootph-all;
-};
-
-&k3_reset {
- bootph-all;
};
&dmsc {
- bootph-all;
k3_sysreset: sysreset-controller {
compatible = "ti,sci-sysreset";
bootph-all;
};
};
-&wkup_conf {
- bootph-all;
-};
-
-&chipid {
- bootph-all;
-};
-
-&main_pmx0 {
- bootph-all;
-};
-
-&main_uart0 {
- bootph-all;
-};
-
-&console_pins_default {
- bootph-all;
-};
-
-&cbass_mcu {
- bootph-all;
-};
-
-&cbass_wakeup {
- bootph-all;
-};
-
-&mcu_pmx0 {
- bootph-all;
-};
-
-&main_i2c0 {
- bootph-all;
-};
-
-&local_i2c_pins_default {
- bootph-all;
-};
-
-&gpio0_pins_default {
- bootph-all;
-};
-
-&main_gpio0 {
- bootph-all;
-};
-
-&main_gpio1 {
- bootph-all;
-};
-
-&sdhci0 {
- /* EMMC */
- bootph-all;
-};
-
-&emmc_pins_default {
- bootph-all;
-};
-
&sd_pins_default {
- bootph-all;
/* Force to use SDCD card detect pin */
pinctrl-single,pins = <
AM62X_IOPAD(0x023c, PIN_INPUT, 0) /* (A21) MMC1_CMD */
@@ -163,33 +61,155 @@
>;
};
-&tps65219 {
- bootph-all;
-};
-
-&sdhci1 {
- bootph-all;
-};
-
-#ifdef CONFIG_TARGET_AM625_A53_EVM
+#ifdef CONFIG_TARGET_AM625_A53_BEAGLEPLAY
+#define SPL_NODTB "spl/u-boot-spl-nodtb.bin"
#define SPL_AM625_BEAGLEPLAY_DTB "spl/dts/k3-am625-beagleplay.dtb"
+#define UBOOT_NODTB "u-boot-nodtb.bin"
#define AM625_BEAGLEPLAY_DTB "arch/arm/dts/k3-am625-beagleplay.dtb"
-&spl_am625_sk_dtb {
- filename = SPL_AM625_BEAGLEPLAY_DTB;
-};
+&binman {
+ ti-dm {
+ filename = "ti-dm.bin";
+ blob-ext {
+ filename = "ti-dm/am62xx/ipc_echo_testb_mcu1_0_release_strip.xer5f";
+ };
+ };
-&am625_sk_dtb {
- filename = AM625_BEAGLEPLAY_DTB;
-};
+ ti-spl_unsigned {
+ filename = "tispl.bin_unsigned";
+ pad-byte = <0xff>;
-&spl_am625_sk_dtb_unsigned {
- filename = SPL_AM625_BEAGLEPLAY_DTB;
-};
+ fit {
+ description = "Configuration to load ATF and SPL";
+ #address-cells = <1>;
-&am625_sk_dtb_unsigned {
- filename = AM625_BEAGLEPLAY_DTB;
-};
+ images {
+
+ atf {
+ description = "ARM Trusted Firmware";
+ type = "firmware";
+ arch = "arm64";
+ compression = "none";
+ os = "arm-trusted-firmware";
+ load = <CONFIG_K3_ATF_LOAD_ADDR>;
+ entry = <CONFIG_K3_ATF_LOAD_ADDR>;
+ atf-bl31 {
+ filename = "bl31.bin";
+ };
+ };
+
+ tee {
+ description = "OP-TEE";
+ type = "tee";
+ arch = "arm64";
+ compression = "none";
+ os = "tee";
+ load = <0x9e800000>;
+ entry = <0x9e800000>;
+ tee-os {
+ filename = "tee-raw.bin";
+ };
+ };
+
+ dm {
+ description = "DM binary";
+ type = "firmware";
+ arch = "arm32";
+ compression = "none";
+ os = "DM";
+ load = <0x89000000>;
+ entry = <0x89000000>;
+ blob-ext {
+ filename = "ti-dm.bin";
+ };
+ };
+ spl {
+ description = "SPL (64-bit)";
+ type = "standalone";
+ os = "U-Boot";
+ arch = "arm64";
+ compression = "none";
+ load = <CONFIG_SPL_TEXT_BASE>;
+ entry = <CONFIG_SPL_TEXT_BASE>;
+ blob {
+ filename = "spl/u-boot-spl-nodtb.bin";
+ };
+ };
+
+ fdt-0 {
+ description = "k3-am625-beagleplay";
+ type = "flat_dt";
+ arch = "arm";
+ compression = "none";
+ spl_am625_bp_dtb_unsigned: blob {
+ filename = SPL_AM625_BEAGLEPLAY_DTB;
+ };
+ };
+ };
+
+ configurations {
+ default = "conf-0";
+
+ conf-0 {
+ description = "k3-am625-beagleplay";
+ firmware = "atf";
+ loadables = "tee", "dm", "spl";
+ fdt = "fdt-0";
+ };
+ };
+ };
+ };
+
+ u-boot_unsigned {
+ filename = "u-boot.img_unsigned";
+ pad-byte = <0xff>;
+
+ fit {
+ description = "FIT image with multiple configurations";
+
+ images {
+ uboot {
+ description = "U-Boot for AM625 board";
+ type = "firmware";
+ os = "u-boot";
+ arch = "arm";
+ compression = "none";
+ load = <CONFIG_TEXT_BASE>;
+ blob {
+ filename = UBOOT_NODTB;
+ };
+ hash {
+ algo = "crc32";
+ };
+ };
+
+ fdt-0 {
+ description = "k3-am625-beagleplay";
+ type = "flat_dt";
+ arch = "arm";
+ compression = "none";
+ am625_bp_dtb_unsigned: blob {
+ filename = AM625_BEAGLEPLAY_DTB;
+ };
+ hash {
+ algo = "crc32";
+ };
+ };
+ };
+
+ configurations {
+ default = "conf-0";
+
+ conf-0 {
+ description = "k3-am625-beagleplay";
+ firmware = "uboot";
+ loadables = "uboot";
+ fdt = "fdt-0";
+ };
+ };
+ };
+ };
+};
#endif
diff --git a/arch/arm/dts/k3-am625-beagleplay.dts b/arch/arm/dts/k3-am625-beagleplay.dts
index 7cfdf56..9a6bd0a 100644
--- a/arch/arm/dts/k3-am625-beagleplay.dts
+++ b/arch/arm/dts/k3-am625-beagleplay.dts
@@ -46,6 +46,7 @@
};
memory@80000000 {
+ bootph-pre-ram;
device_type = "memory";
/* 2G RAM */
reg = <0x00000000 0x80000000 0x00000000 0x80000000>;
@@ -58,7 +59,7 @@
ramoops: ramoops@9ca00000 {
compatible = "ramoops";
- reg = <0x00 0x9c700000 0x00 0x00100000>;
+ reg = <0x00 0x9ca00000 0x00 0x00100000>;
record-size = <0x8000>;
console-size = <0x8000>;
ftrace-size = <0x00>;
@@ -83,6 +84,7 @@
};
vsys_5v0: regulator-1 {
+ bootph-all;
compatible = "regulator-fixed";
regulator-name = "vsys_5v0";
regulator-min-microvolt = <5000000>;
@@ -93,6 +95,7 @@
vdd_3v3: regulator-2 {
/* output of TLV62595DMQR-U12 */
+ bootph-all;
compatible = "regulator-fixed";
regulator-name = "vdd_3v3";
regulator-min-microvolt = <3300000>;
@@ -118,6 +121,7 @@
vdd_3v3_sd: regulator-4 {
/* output of TPS22918DBVR-U21 */
+ bootph-all;
pinctrl-names = "default";
pinctrl-0 = <&vdd_3v3_sd_pins_default>;
@@ -132,6 +136,7 @@
};
vdd_sd_dv: regulator-5 {
+ bootph-all;
compatible = "regulator-gpio";
regulator-name = "sd_hs200_switch";
pinctrl-names = "default";
@@ -146,9 +151,11 @@
};
leds {
+ bootph-all;
compatible = "gpio-leds";
led-0 {
+ bootph-all;
gpios = <&main_gpio0 3 GPIO_ACTIVE_HIGH>;
linux,default-trigger = "heartbeat";
function = LED_FUNCTION_HEARTBEAT;
@@ -156,6 +163,7 @@
};
led-1 {
+ bootph-all;
gpios = <&main_gpio0 4 GPIO_ACTIVE_HIGH>;
linux,default-trigger = "disk-activity";
function = LED_FUNCTION_DISK_ACTIVITY;
@@ -163,16 +171,19 @@
};
led-2 {
+ bootph-all;
gpios = <&main_gpio0 5 GPIO_ACTIVE_HIGH>;
function = LED_FUNCTION_CPU;
};
led-3 {
+ bootph-all;
gpios = <&main_gpio0 6 GPIO_ACTIVE_HIGH>;
function = LED_FUNCTION_LAN;
};
led-4 {
+ bootph-all;
gpios = <&main_gpio0 9 GPIO_ACTIVE_HIGH>;
function = LED_FUNCTION_WLAN;
};
@@ -245,6 +256,7 @@
&main_pmx0 {
gpio0_pins_default: gpio0-default-pins {
+ bootph-all;
pinctrl-single,pins = <
AM62X_IOPAD(0x0004, PIN_INPUT, 7) /* (G25) OSPI0_LBCLKO.GPIO0_1 */
AM62X_IOPAD(0x0008, PIN_INPUT, 7) /* (J24) OSPI0_DQS.GPIO0_2 */
@@ -264,6 +276,7 @@
};
vdd_sd_dv_pins_default: vdd-sd-default-pins {
+ bootph-all;
pinctrl-single,pins = <
AM62X_IOPAD(0x0244, PIN_OUTPUT, 7) /* (C17) MMC1_SDWP.GPIO1_49 */
>;
@@ -283,6 +296,7 @@
};
local_i2c_pins_default: local-i2c-default-pins {
+ bootph-all;
pinctrl-single,pins = <
AM62X_IOPAD(0x01e0, PIN_INPUT_PULLUP, 0) /* (B16) I2C0_SCL */
AM62X_IOPAD(0x01e4, PIN_INPUT_PULLUP, 0) /* (A16) I2C0_SDA */
@@ -321,6 +335,7 @@
};
emmc_pins_default: emmc-default-pins {
+ bootph-all;
pinctrl-single,pins = <
AM62X_IOPAD(0x0220, PIN_INPUT, 0) /* (Y3) MMC0_CMD */
AM62X_IOPAD(0x0218, PIN_INPUT, 0) /* (AB1) MMC0_CLK */
@@ -336,12 +351,14 @@
};
vdd_3v3_sd_pins_default: vdd-3v3-sd-default-pins {
+ bootph-all;
pinctrl-single,pins = <
AM62X_IOPAD(0x01c4, PIN_INPUT, 7) /* (B14) SPI0_D1_GPIO1_19 */
>;
};
sd_pins_default: sd-default-pins {
+ bootph-all;
pinctrl-single,pins = <
AM62X_IOPAD(0x023c, PIN_INPUT, 0) /* (A21) MMC1_CMD */
AM62X_IOPAD(0x0234, PIN_INPUT, 0) /* (B22) MMC1_CLK */
@@ -418,6 +435,7 @@
};
mikrobus_gpio_pins_default: mikrobus-gpio-default-pins {
+ bootph-all;
pinctrl-single,pins = <
AM62X_IOPAD(0x019c, PIN_INPUT, 7) /* (B18) MCASP0_AXR1.GPIO1_9 */
AM62X_IOPAD(0x01a0, PIN_INPUT, 7) /* (E18) MCASP0_AXR0.GPIO1_10 */
@@ -426,6 +444,7 @@
};
console_pins_default: console-default-pins {
+ bootph-all;
pinctrl-single,pins = <
AM62X_IOPAD(0x01c8, PIN_INPUT, 0) /* (D14) UART0_RXD */
AM62X_IOPAD(0x01cc, PIN_OUTPUT, 0) /* (E14) UART0_TXD */
@@ -597,6 +616,7 @@
};
&main_gpio0 {
+ bootph-all;
pinctrl-names = "default";
pinctrl-0 = <&gpio0_pins_default>;
gpio-line-names = "BL_EN_3V3", "SPE_PO_EN", "RTC_INT", /* 0-2 */
@@ -616,6 +636,7 @@
};
&main_gpio1 {
+ bootph-all;
pinctrl-names = "default";
pinctrl-0 = <&mikrobus_gpio_pins_default>;
gpio-line-names = "", "", "", "", "", /* 0-4 */
@@ -633,6 +654,7 @@
};
&main_i2c0 {
+ bootph-all;
pinctrl-names = "default";
pinctrl-0 = <&local_i2c_pins_default>;
clock-frequency = <400000>;
@@ -651,6 +673,7 @@
};
tps65219: pmic@30 {
+ bootph-all;
compatible = "ti,tps65219";
reg = <0x30>;
buck1-supply = <&vsys_5v0>;
@@ -801,6 +824,7 @@
};
&sdhci0 {
+ bootph-all;
pinctrl-names = "default";
pinctrl-0 = <&emmc_pins_default>;
ti,driver-strength-ohm = <50>;
@@ -810,6 +834,7 @@
&sdhci1 {
/* SD/MMC */
+ bootph-all;
pinctrl-names = "default";
pinctrl-0 = <&sd_pins_default>;
@@ -850,6 +875,7 @@
};
&main_uart0 {
+ bootph-all;
pinctrl-names = "default";
pinctrl-0 = <&console_pins_default>;
status = "okay";
@@ -870,6 +896,12 @@
pinctrl-names = "default";
pinctrl-0 = <&wifi_debug_uart_pins_default>;
status = "okay";
+
+ mcu {
+ compatible = "ti,cc1352p7";
+ reset-gpios = <&main_gpio0 72 GPIO_ACTIVE_LOW>;
+ vdds-supply = <&vdd_3v3>;
+ };
};
&dss {
diff --git a/arch/arm/dts/k3-am625-r5-beagleplay.dts b/arch/arm/dts/k3-am625-r5-beagleplay.dts
index 9c9d057..9db58f0 100644
--- a/arch/arm/dts/k3-am625-r5-beagleplay.dts
+++ b/arch/arm/dts/k3-am625-r5-beagleplay.dts
@@ -54,12 +54,7 @@
ti,secure-host;
};
-&mcu_esm {
- bootph-pre-ram;
-};
-
&secure_proxy_sa3 {
- bootph-pre-ram;
/* We require this for boot handshake */
status = "okay";
};
@@ -73,10 +68,6 @@
};
};
-&main_esm {
- bootph-pre-ram;
-};
-
&main_pktdma {
ti,sci = <&dm_tifs>;
};
@@ -84,3 +75,42 @@
&main_bcdma {
ti,sci = <&dm_tifs>;
};
+
+&binman {
+ tiboot3-am62x-gp-evm.bin {
+ filename = "tiboot3-am62x-gp-evm.bin";
+ ti-secure-rom {
+ content = <&u_boot_spl_unsigned>, <&ti_fs_gp>,
+ <&combined_tifs_cfg_gp>, <&combined_dm_cfg_gp>;
+ combined;
+ dm-data;
+ content-sbl = <&u_boot_spl_unsigned>;
+ load = <0x43c00000>;
+ content-sysfw = <&ti_fs_gp>;
+ load-sysfw = <0x40000>;
+ content-sysfw-data = <&combined_tifs_cfg_gp>;
+ load-sysfw-data = <0x67000>;
+ content-dm-data = <&combined_dm_cfg_gp>;
+ load-dm-data = <0x43c3a800>;
+ sw-rev = <1>;
+ keyfile = "ti-degenerate-key.pem";
+ };
+ u_boot_spl_unsigned: u-boot-spl {
+ no-expanded;
+ };
+ ti_fs_gp: ti-fs-gp.bin {
+ filename = "ti-sysfw/ti-fs-firmware-am62x-gp.bin";
+ type = "blob-ext";
+ optional;
+ };
+ combined_tifs_cfg_gp: combined-tifs-cfg-gp.bin {
+ filename = "combined-tifs-cfg.bin";
+ type = "blob-ext";
+ };
+ combined_dm_cfg_gp: combined-dm-cfg-gp.bin {
+ filename = "combined-dm-cfg.bin";
+ type = "blob-ext";
+ };
+
+ };
+};
diff --git a/arch/arm/dts/k3-am625-r5-sk.dts b/arch/arm/dts/k3-am625-r5-sk.dts
index bf21922..6b9f40e 100644
--- a/arch/arm/dts/k3-am625-r5-sk.dts
+++ b/arch/arm/dts/k3-am625-r5-sk.dts
@@ -55,20 +55,11 @@
ti,secure-host;
};
-&mcu_esm {
- bootph-pre-ram;
-};
-
&secure_proxy_sa3 {
- bootph-pre-ram;
/* We require this for boot handshake */
status = "okay";
};
-&main_esm {
- bootph-pre-ram;
-};
-
&cbass_main {
sysctrler: sysctrler {
compatible = "ti,am654-system-controller";
@@ -78,22 +69,14 @@
};
};
-&wkup_uart0_pins_default {
- bootph-pre-ram;
-};
-
-&main_uart1_pins_default {
- bootph-pre-ram;
-};
-
/* WKUP UART0 is used for DM firmware logs */
&wkup_uart0 {
- bootph-pre-ram;
+ status = "okay";
};
/* Main UART1 is used for TIFS firmware logs */
&main_uart1 {
- bootph-pre-ram;
+ status = "okay";
};
&ospi0 {
diff --git a/arch/arm/dts/k3-am625-sk-binman.dtsi b/arch/arm/dts/k3-am625-sk-binman.dtsi
index 41277bf..b7b5368 100644
--- a/arch/arm/dts/k3-am625-sk-binman.dtsi
+++ b/arch/arm/dts/k3-am625-sk-binman.dtsi
@@ -141,10 +141,7 @@
#ifdef CONFIG_TARGET_AM625_A53_EVM
-#define SPL_NODTB "spl/u-boot-spl-nodtb.bin"
#define SPL_AM625_SK_DTB "spl/dts/k3-am625-sk.dtb"
-
-#define UBOOT_NODTB "u-boot-nodtb.bin"
#define AM625_SK_DTB "u-boot.dtb"
&binman {
@@ -155,55 +152,11 @@
};
};
ti-spl {
- filename = "tispl.bin";
- pad-byte = <0xff>;
+ insert-template = <&ti_spl_template>;
fit {
- description = "Configuration to load ATF and SPL";
- #address-cells = <1>;
-
images {
-
- atf {
- description = "ARM Trusted Firmware";
- type = "firmware";
- arch = "arm64";
- compression = "none";
- os = "arm-trusted-firmware";
- load = <CONFIG_K3_ATF_LOAD_ADDR>;
- entry = <CONFIG_K3_ATF_LOAD_ADDR>;
- ti-secure {
- content = <&atf>;
- keyfile = "custMpk.pem";
- };
- atf: atf-bl31 {
- };
- };
-
- tee {
- description = "OP-TEE";
- type = "tee";
- arch = "arm64";
- compression = "none";
- os = "tee";
- load = <0x9e800000>;
- entry = <0x9e800000>;
- ti-secure {
- content = <&tee>;
- keyfile = "custMpk.pem";
- };
- tee: tee-os {
- };
- };
-
dm {
- description = "DM binary";
- type = "firmware";
- arch = "arm32";
- compression = "none";
- os = "DM";
- load = <0x89000000>;
- entry = <0x89000000>;
ti-secure {
content = <&dm>;
keyfile = "custMpk.pem";
@@ -213,23 +166,6 @@
};
};
- spl {
- description = "SPL (64-bit)";
- type = "standalone";
- os = "U-Boot";
- arch = "arm64";
- compression = "none";
- load = <CONFIG_SPL_TEXT_BASE>;
- entry = <CONFIG_SPL_TEXT_BASE>;
- ti-secure {
- content = <&u_boot_spl_nodtb>;
- keyfile = "custMpk.pem";
- };
- u_boot_spl_nodtb: blob-ext {
- filename = SPL_NODTB;
- };
- };
-
fdt-0 {
description = "k3-am625-sk";
type = "flat_dt";
@@ -263,29 +199,12 @@
&binman {
u-boot {
- filename = "u-boot.img";
- pad-byte = <0xff>;
+ insert-template = <&u_boot_template>;
fit {
- description = "FIT image with multiple configurations";
-
images {
uboot {
- description = "U-Boot for AM625 board";
- type = "firmware";
- os = "u-boot";
- arch = "arm";
- compression = "none";
- load = <CONFIG_TEXT_BASE>;
- ti-secure {
- content = <&u_boot_nodtb>;
- keyfile = "custMpk.pem";
- };
- u_boot_nodtb: u-boot-nodtb {
- };
- hash {
- algo = "crc32";
- };
+ description = "U-Boot for AM625 Board";
};
fdt-0 {
@@ -323,67 +242,17 @@
&binman {
ti-spl_unsigned {
- filename = "tispl.bin_unsigned";
- pad-byte = <0xff>;
+ insert-template = <&ti_spl_unsigned_template>;
fit {
- description = "Configuration to load ATF and SPL";
- #address-cells = <1>;
-
images {
- atf {
- description = "ARM Trusted Firmware";
- type = "firmware";
- arch = "arm64";
- compression = "none";
- os = "arm-trusted-firmware";
- load = <CONFIG_K3_ATF_LOAD_ADDR>;
- entry = <CONFIG_K3_ATF_LOAD_ADDR>;
- atf-bl31 {
- filename = "bl31.bin";
- };
- };
-
- tee {
- description = "OP-TEE";
- type = "tee";
- arch = "arm64";
- compression = "none";
- os = "tee";
- load = <0x9e800000>;
- entry = <0x9e800000>;
- tee-os {
- filename = "tee-raw.bin";
- };
- };
-
dm {
- description = "DM binary";
- type = "firmware";
- arch = "arm32";
- compression = "none";
- os = "DM";
- load = <0x89000000>;
- entry = <0x89000000>;
blob-ext {
filename = "ti-dm.bin";
};
};
- spl {
- description = "SPL (64-bit)";
- type = "standalone";
- os = "U-Boot";
- arch = "arm64";
- compression = "none";
- load = <CONFIG_SPL_TEXT_BASE>;
- entry = <CONFIG_SPL_TEXT_BASE>;
- blob {
- filename = "spl/u-boot-spl-nodtb.bin";
- };
- };
-
fdt-0 {
description = "k3-am625-sk";
type = "flat_dt";
@@ -411,26 +280,12 @@
&binman {
u-boot_unsigned {
- filename = "u-boot.img_unsigned";
- pad-byte = <0xff>;
+ insert-template = <&u_boot_unsigned_template>;
fit {
- description = "FIT image with multiple configurations";
-
images {
uboot {
- description = "U-Boot for AM625 board";
- type = "firmware";
- os = "u-boot";
- arch = "arm";
- compression = "none";
- load = <CONFIG_TEXT_BASE>;
- blob {
- filename = UBOOT_NODTB;
- };
- hash {
- algo = "crc32";
- };
+ description = "U-Boot for AM625 Board";
};
fdt-0 {
diff --git a/arch/arm/dts/k3-am625-sk-u-boot.dtsi b/arch/arm/dts/k3-am625-sk-u-boot.dtsi
index b78d34b..fa778b0 100644
--- a/arch/arm/dts/k3-am625-sk-u-boot.dtsi
+++ b/arch/arm/dts/k3-am625-sk-u-boot.dtsi
@@ -8,160 +8,38 @@
/ {
chosen {
- stdout-path = "serial2:115200n8";
tick-timer = &main_timer0;
};
-
- aliases {
- mmc1 = &sdhci1;
- };
-
- memory@80000000 {
- bootph-all;
- };
};
-&main_conf {
- bootph-all;
-};
-
-&cbass_main {
- bootph-all;
-};
-
&main_timer0 {
clock-frequency = <25000000>;
- bootph-all;
-};
-
-&dmss {
- bootph-all;
-};
-
-&secure_proxy_main {
- bootph-all;
-};
-
-&dmsc {
- bootph-all;
-};
-
-&k3_pds {
- bootph-all;
-};
-
-&k3_clks {
- bootph-all;
-};
-
-&k3_reset {
- bootph-all;
-};
-
-&wkup_conf {
- bootph-all;
-};
-
-&chipid {
- bootph-all;
-};
-
-&main_pmx0 {
- bootph-all;
-};
-
-&main_uart0 {
- bootph-all;
-};
-
-&main_uart0_pins_default {
- bootph-all;
-};
-
-&cbass_mcu {
- bootph-all;
-};
-
-&cbass_wakeup {
- bootph-all;
};
-&mcu_pmx0 {
- bootph-all;
+&main_bcdma {
+ reg = <0x00 0x485c0100 0x00 0x100>,
+ <0x00 0x4c000000 0x00 0x20000>,
+ <0x00 0x4a820000 0x00 0x20000>,
+ <0x00 0x4aa40000 0x00 0x20000>,
+ <0x00 0x4bc00000 0x00 0x100000>,
+ <0x00 0x48600000 0x00 0x8000>,
+ <0x00 0x484a4000 0x00 0x2000>,
+ <0x00 0x484c2000 0x00 0x2000>;
+ reg-names = "gcfg", "bchanrt", "rchanrt", "tchanrt",
+ "ringrt" , "cfg", "tchan", "rchan";
};
-&sdhci1 {
- bootph-all;
-};
-
-&main_mmc1_pins_default {
- bootph-all;
-};
-
-&fss {
- bootph-all;
-};
-
-&ospi0_pins_default {
- bootph-all;
-};
-
-&ospi0 {
- bootph-all;
-
- flash@0 {
- bootph-all;
-
- partitions {
- bootph-all;
-
- partition@3fc0000 {
- bootph-all;
- };
- };
- };
-};
-
-&inta_main_dmss {
- bootph-all;
-};
-
&main_pktdma {
- bootph-all;
-};
-
-&cpsw3g_mdio {
- bootph-all;
-};
-
-&cpsw3g_phy0 {
- bootph-all;
-};
-
-&cpsw3g_phy1 {
- bootph-all;
-};
-
-&main_rgmii1_pins_default {
- bootph-all;
-};
-
-&main_rgmii2_pins_default {
- bootph-all;
-};
-
-&phy_gmii_sel {
- bootph-all;
-};
-
-&cpsw3g {
- bootph-all;
- ethernet-ports {
- bootph-all;
- };
-};
-
-&cpsw_port1 {
+ reg = <0x00 0x485c0000 0x00 0x100>,
+ <0x00 0x4a800000 0x00 0x20000>,
+ <0x00 0x4aa00000 0x00 0x20000>,
+ <0x00 0x4b800000 0x00 0x200000>,
+ <0x00 0x485e0000 0x00 0x10000>,
+ <0x00 0x484a0000 0x00 0x2000>,
+ <0x00 0x484c0000 0x00 0x2000>,
+ <0x00 0x48430000 0x00 0x1000>;
+ reg-names = "gcfg", "rchanrt", "tchanrt", "ringrt",
+ "cfg", "tchan", "rchan", "rflow";
bootph-all;
};
diff --git a/arch/arm/dts/k3-am625-sk.dts b/arch/arm/dts/k3-am625-sk.dts
index 7c98c1b..b180924 100644
--- a/arch/arm/dts/k3-am625-sk.dts
+++ b/arch/arm/dts/k3-am625-sk.dts
@@ -31,6 +31,7 @@
vmain_pd: regulator-0 {
/* TPS65988 PD CONTROLLER OUTPUT */
+ bootph-all;
compatible = "regulator-fixed";
regulator-name = "vmain_pd";
regulator-min-microvolt = <5000000>;
@@ -41,6 +42,7 @@
vcc_5v0: regulator-1 {
/* Output of LM34936 */
+ bootph-all;
compatible = "regulator-fixed";
regulator-name = "vcc_5v0";
regulator-min-microvolt = <5000000>;
@@ -52,6 +54,7 @@
vcc_3v3_sys: regulator-2 {
/* output of LM61460-Q1 */
+ bootph-all;
compatible = "regulator-fixed";
regulator-name = "vcc_3v3_sys";
regulator-min-microvolt = <3300000>;
@@ -63,6 +66,7 @@
vdd_mmc1: regulator-3 {
/* TPS22918DBVR */
+ bootph-all;
compatible = "regulator-fixed";
regulator-name = "vdd_mmc1";
regulator-min-microvolt = <3300000>;
@@ -75,6 +79,7 @@
vdd_sd_dv: regulator-4 {
/* Output of TLV71033 */
+ bootph-all;
compatible = "regulator-gpio";
regulator-name = "tlv71033";
pinctrl-names = "default";
@@ -102,6 +107,7 @@
&main_pmx0 {
main_rgmii2_pins_default: main-rgmii2-default-pins {
+ bootph-all;
pinctrl-single,pins = <
AM62X_IOPAD(0x184, PIN_INPUT, 0) /* (AE23) RGMII2_RD0 */
AM62X_IOPAD(0x188, PIN_INPUT, 0) /* (AB20) RGMII2_RD1 */
@@ -119,6 +125,7 @@
};
ospi0_pins_default: ospi0-default-pins {
+ bootph-all;
pinctrl-single,pins = <
AM62X_IOPAD(0x000, PIN_OUTPUT, 0) /* (H24) OSPI0_CLK */
AM62X_IOPAD(0x02c, PIN_OUTPUT, 0) /* (F23) OSPI0_CSn0 */
@@ -135,20 +142,32 @@
};
vdd_sd_dv_pins_default: vdd-sd-dv-default-pins {
+ bootph-all;
pinctrl-single,pins = <
AM62X_IOPAD(0x07c, PIN_OUTPUT, 7) /* (P25) GPMC0_CLK.GPIO0_31 */
>;
};
main_gpio1_ioexp_intr_pins_default: main-gpio1-ioexp-intr-default-pins {
+ bootph-all;
pinctrl-single,pins = <
AM62X_IOPAD(0x01d4, PIN_INPUT, 7) /* (B15) UART0_RTSn.GPIO1_23 */
>;
};
};
+&main_gpio0 {
+ bootph-all;
+};
+
+&main_gpio1 {
+ bootph-all;
+};
+
&main_i2c1 {
+ bootph-all;
exp1: gpio@22 {
+ bootph-all;
compatible = "ti,tca6424";
reg = <0x22>;
gpio-controller;
@@ -207,12 +226,18 @@
};
};
+&fss {
+ bootph-all;
+};
+
&ospi0 {
+ bootph-all;
status = "okay";
pinctrl-names = "default";
pinctrl-0 = <&ospi0_pins_default>;
flash@0 {
+ bootph-all;
compatible = "jedec,spi-nor";
reg = <0x0>;
spi-tx-bus-width = <8>;
@@ -225,6 +250,7 @@
cdns,read-delay = <4>;
partitions {
+ bootph-all;
compatible = "fixed-partitions";
#address-cells = <1>;
#size-cells = <1>;
@@ -260,6 +286,7 @@
};
partition@3fc0000 {
+ bootph-pre-ram;
label = "ospi.phypattern";
reg = <0x3fc0000 0x40000>;
};
diff --git a/arch/arm/dts/k3-am625-verdin-r5.dts b/arch/arm/dts/k3-am625-verdin-r5.dts
index 0cae9c5..305d199 100644
--- a/arch/arm/dts/k3-am625-verdin-r5.dts
+++ b/arch/arm/dts/k3-am625-verdin-r5.dts
@@ -69,16 +69,7 @@
ti,secure-host;
};
-&main_esm {
- bootph-pre-ram;
-};
-
-&mcu_esm {
- bootph-pre-ram;
-};
-
&secure_proxy_sa3 {
- bootph-pre-ram;
/* We require this for boot handshake */
status = "okay";
};
diff --git a/arch/arm/dts/k3-am625-verdin-wifi-dev-binman.dtsi b/arch/arm/dts/k3-am625-verdin-wifi-dev-binman.dtsi
index 089b2a5..ed2c448 100644
--- a/arch/arm/dts/k3-am625-verdin-wifi-dev-binman.dtsi
+++ b/arch/arm/dts/k3-am625-verdin-wifi-dev-binman.dtsi
@@ -5,14 +5,6 @@
#include "k3-binman.dtsi"
-&custmpk_pem {
- filename = "../../ti/keys/custMpk.pem";
-};
-
-&dkey_pem {
- filename = "../../ti/keys/ti-degenerate-key.pem";
-};
-
#ifndef CONFIG_ARM64
&bcfg_yaml {
@@ -214,10 +206,7 @@
#ifdef CONFIG_TARGET_VERDIN_AM62_A53
-#define SPL_NODTB "spl/u-boot-spl-nodtb.bin"
#define SPL_VERDIN_AM62_DTB "spl/dts/k3-am625-verdin-wifi-dev.dtb"
-
-#define UBOOT_NODTB "u-boot-nodtb.bin"
#define VERDIN_AM62_DTB "u-boot.dtb"
&binman {
@@ -228,54 +217,12 @@
};
};
ti-spl {
- filename = "tispl.bin";
- pad-byte = <0xff>;
+ insert-template = <&ti_spl_template>;
fit {
- description = "Configuration to load ATF and SPL";
- #address-cells = <1>;
images {
- atf {
- description = "ARM Trusted Firmware";
- type = "firmware";
- arch = "arm64";
- compression = "none";
- os = "arm-trusted-firmware";
- load = <CONFIG_K3_ATF_LOAD_ADDR>;
- entry = <CONFIG_K3_ATF_LOAD_ADDR>;
- ti-secure {
- content = <&atf>;
- keyfile = "custMpk.pem";
- };
- atf: atf-bl31 {
- };
- };
-
- tee {
- description = "OP-TEE";
- type = "tee";
- arch = "arm64";
- compression = "none";
- os = "tee";
- load = <0x9e800000>;
- entry = <0x9e800000>;
- ti-secure {
- content = <&tee>;
- keyfile = "custMpk.pem";
- };
- tee: tee-os {
- };
- };
-
dm {
- description = "DM binary";
- type = "firmware";
- arch = "arm32";
- compression = "none";
- os = "DM";
- load = <0x89000000>;
- entry = <0x89000000>;
ti-secure {
content = <&dm>;
keyfile = "custMpk.pem";
@@ -285,23 +232,6 @@
};
};
- spl {
- description = "SPL (64-bit)";
- type = "standalone";
- os = "U-Boot";
- arch = "arm64";
- compression = "none";
- load = <CONFIG_SPL_TEXT_BASE>;
- entry = <CONFIG_SPL_TEXT_BASE>;
- ti-secure {
- content = <&u_boot_spl_nodtb>;
- keyfile = "custMpk.pem";
- };
- u_boot_spl_nodtb: blob-ext {
- filename = SPL_NODTB;
- };
- };
-
fdt-0 {
description = "k3-am625-verdin-wifi-dev";
type = "flat_dt";
@@ -333,29 +263,12 @@
&binman {
u-boot {
- filename = "u-boot.img";
- pad-byte = <0xff>;
+ insert-template = <&u_boot_template>;
fit {
- description = "FIT image with multiple configurations";
-
images {
uboot {
- description = "U-Boot for AM625 board";
- type = "firmware";
- os = "u-boot";
- arch = "arm";
- compression = "none";
- load = <CONFIG_TEXT_BASE>;
- ti-secure {
- content = <&u_boot_nodtb>;
- keyfile = "custMpk.pem";
- };
- u_boot_nodtb: u-boot-nodtb {
- };
- hash {
- algo = "crc32";
- };
+ description = "U-Boot fot AM625 Verdin Board";
};
fdt-0 {
@@ -392,66 +305,16 @@
&binman {
ti-spl_unsigned {
- filename = "tispl.bin_unsigned";
- pad-byte = <0xff>;
+ insert-template = <&ti_spl_unsigned_template>;
fit {
- description = "Configuration to load ATF and SPL";
- #address-cells = <1>;
-
images {
- atf {
- description = "ARM Trusted Firmware";
- type = "firmware";
- arch = "arm64";
- compression = "none";
- os = "arm-trusted-firmware";
- load = <CONFIG_K3_ATF_LOAD_ADDR>;
- entry = <CONFIG_K3_ATF_LOAD_ADDR>;
- atf-bl31 {
- filename = "bl31.bin";
- };
- };
-
- tee {
- description = "OP-TEE";
- type = "tee";
- arch = "arm64";
- compression = "none";
- os = "tee";
- load = <0x9e800000>;
- entry = <0x9e800000>;
- tee-os {
- filename = "tee-raw.bin";
- };
- };
-
dm {
- description = "DM binary";
- type = "firmware";
- arch = "arm32";
- compression = "none";
- os = "DM";
- load = <0x89000000>;
- entry = <0x89000000>;
blob-ext {
filename = "ti-dm.bin";
};
};
- spl {
- description = "SPL (64-bit)";
- type = "standalone";
- os = "U-Boot";
- arch = "arm64";
- compression = "none";
- load = <CONFIG_SPL_TEXT_BASE>;
- entry = <CONFIG_SPL_TEXT_BASE>;
- blob {
- filename = "spl/u-boot-spl-nodtb.bin";
- };
- };
-
fdt-0 {
description = "k3-am625-verdin-wifi-dev";
type = "flat_dt";
@@ -479,26 +342,12 @@
&binman {
u-boot_unsigned {
- filename = "u-boot.img_unsigned";
- pad-byte = <0xff>;
+ insert-template = <&u_boot_unsigned_template>;
fit {
- description = "FIT image with multiple configurations";
-
images {
uboot {
- description = "U-Boot for AM625 board";
- type = "firmware";
- os = "u-boot";
- arch = "arm";
- compression = "none";
- load = <CONFIG_TEXT_BASE>;
- blob {
- filename = UBOOT_NODTB;
- };
- hash {
- algo = "crc32";
- };
+ description = "U-Boot for AM625 Verdin Board";
};
fdt-0 {
diff --git a/arch/arm/dts/k3-am625-verdin-wifi-dev-u-boot.dtsi b/arch/arm/dts/k3-am625-verdin-wifi-dev-u-boot.dtsi
index afa24d0..02f34c9 100644
--- a/arch/arm/dts/k3-am625-verdin-wifi-dev-u-boot.dtsi
+++ b/arch/arm/dts/k3-am625-verdin-wifi-dev-u-boot.dtsi
@@ -21,27 +21,38 @@
};
};
-&cbass_main {
- bootph-all;
-
- timer@2400000 {
- clock-frequency = <25000000>;
- bootph-all;
- };
+&main_timer0 {
+ clock-frequency = <25000000>;
};
-&cbass_mcu {
+&main_bcdma {
+ reg = <0x00 0x485c0100 0x00 0x100>,
+ <0x00 0x4c000000 0x00 0x20000>,
+ <0x00 0x4a820000 0x00 0x20000>,
+ <0x00 0x4aa40000 0x00 0x20000>,
+ <0x00 0x4bc00000 0x00 0x100000>,
+ <0x00 0x48600000 0x00 0x8000>,
+ <0x00 0x484a4000 0x00 0x2000>,
+ <0x00 0x484c2000 0x00 0x2000>;
+ reg-names = "gcfg", "bchanrt", "rchanrt", "tchanrt",
+ "ringrt" , "cfg", "tchan", "rchan";
bootph-all;
};
-&cbass_wakeup {
+&main_pktdma {
+ reg = <0x00 0x485c0000 0x00 0x100>,
+ <0x00 0x4a800000 0x00 0x20000>,
+ <0x00 0x4aa00000 0x00 0x20000>,
+ <0x00 0x4b800000 0x00 0x200000>,
+ <0x00 0x485e0000 0x00 0x10000>,
+ <0x00 0x484a0000 0x00 0x2000>,
+ <0x00 0x484c0000 0x00 0x2000>,
+ <0x00 0x48430000 0x00 0x1000>;
+ reg-names = "gcfg", "rchanrt", "tchanrt", "ringrt",
+ "cfg", "tchan", "rchan", "rflow";
bootph-all;
};
-&chipid {
- bootph-all;
-};
-
&cpsw3g {
bootph-all;
};
@@ -71,34 +82,16 @@
};
&dmsc {
- bootph-all;
-
k3_sysreset: sysreset-controller {
compatible = "ti,sci-sysreset";
bootph-all;
};
};
-&dmss {
- bootph-all;
-};
-
&fss {
bootph-all;
};
-&k3_clks {
- bootph-all;
-};
-
-&k3_pds {
- bootph-all;
-};
-
-&k3_reset {
- bootph-all;
-};
-
&main_gpio0 {
bootph-all;
};
@@ -129,10 +122,6 @@
};
};
-&main_pmx0 {
- bootph-all;
-};
-
/* Verdin UART_3, used as the Linux console */
&main_uart0 {
bootph-all;
@@ -143,10 +132,6 @@
bootph-all;
};
-&mcu_pmx0 {
- bootph-all;
-};
-
&pinctrl_ctrl_sleep_moci {
bootph-all;
};
@@ -183,18 +168,10 @@
status = "disabled";
};
-&secure_proxy_main {
- bootph-all;
-};
-
&verdin_ctrl_sleep_moci {
bootph-all;
};
-&wkup_conf {
- bootph-all;
-};
-
/* Verdin UART_2 */
&wkup_uart0 {
bootph-all;
diff --git a/arch/arm/dts/k3-am62a-main.dtsi b/arch/arm/dts/k3-am62a-main.dtsi
index bc4b50b..4ae7fdc 100644
--- a/arch/arm/dts/k3-am62a-main.dtsi
+++ b/arch/arm/dts/k3-am62a-main.dtsi
@@ -48,6 +48,18 @@
#address-cells = <1>;
#size-cells = <1>;
ranges = <0x00 0x00 0x00100000 0x20000>;
+
+ phy_gmii_sel: phy@4044 {
+ compatible = "ti,am654-phy-gmii-sel";
+ reg = <0x4044 0x8>;
+ #phy-cells = <1>;
+ };
+
+ epwm_tbclk: clock-controller@4130 {
+ compatible = "ti,am62-epwm-tbclk";
+ reg = <0x4130 0x4>;
+ #clock-cells = <1>;
+ };
};
dmss: bus@48000000 {
@@ -69,6 +81,67 @@
interrupt-names = "rx_012";
interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
};
+
+ inta_main_dmss: interrupt-controller@48000000 {
+ compatible = "ti,sci-inta";
+ reg = <0x00 0x48000000 0x00 0x100000>;
+ #interrupt-cells = <0>;
+ interrupt-controller;
+ interrupt-parent = <&gic500>;
+ msi-controller;
+ ti,sci = <&dmsc>;
+ ti,sci-dev-id = <28>;
+ ti,interrupt-ranges = <6 70 34>;
+ ti,unmapped-event-sources = <&main_bcdma>, <&main_pktdma>;
+ };
+
+ main_bcdma: dma-controller@485c0100 {
+ compatible = "ti,am64-dmss-bcdma";
+ reg = <0x00 0x485c0100 0x00 0x100>,
+ <0x00 0x4c000000 0x00 0x20000>,
+ <0x00 0x4a820000 0x00 0x20000>,
+ <0x00 0x4aa40000 0x00 0x20000>,
+ <0x00 0x4bc00000 0x00 0x100000>;
+ reg-names = "gcfg", "bchanrt", "rchanrt", "tchanrt", "ringrt";
+ msi-parent = <&inta_main_dmss>;
+ #dma-cells = <3>;
+ ti,sci = <&dmsc>;
+ ti,sci-dev-id = <26>;
+ ti,sci-rm-range-bchan = <0x20>; /* BLOCK_COPY_CHAN */
+ ti,sci-rm-range-rchan = <0x21>; /* SPLIT_TR_RX_CHAN */
+ ti,sci-rm-range-tchan = <0x22>; /* SPLIT_TR_TX_CHAN */
+ };
+
+ main_pktdma: dma-controller@485c0000 {
+ compatible = "ti,am64-dmss-pktdma";
+ reg = <0x00 0x485c0000 0x00 0x100>,
+ <0x00 0x4a800000 0x00 0x20000>,
+ <0x00 0x4aa00000 0x00 0x40000>,
+ <0x00 0x4b800000 0x00 0x400000>;
+ reg-names = "gcfg", "rchanrt", "tchanrt", "ringrt";
+ msi-parent = <&inta_main_dmss>;
+ #dma-cells = <2>;
+ ti,sci = <&dmsc>;
+ ti,sci-dev-id = <30>;
+ ti,sci-rm-range-tchan = <0x23>, /* UNMAPPED_TX_CHAN */
+ <0x24>, /* CPSW_TX_CHAN */
+ <0x25>, /* SAUL_TX_0_CHAN */
+ <0x26>; /* SAUL_TX_1_CHAN */
+ ti,sci-rm-range-tflow = <0x10>, /* RING_UNMAPPED_TX_CHAN */
+ <0x11>, /* RING_CPSW_TX_CHAN */
+ <0x12>, /* RING_SAUL_TX_0_CHAN */
+ <0x13>; /* RING_SAUL_TX_1_CHAN */
+ ti,sci-rm-range-rchan = <0x29>, /* UNMAPPED_RX_CHAN */
+ <0x2b>, /* CPSW_RX_CHAN */
+ <0x2d>, /* SAUL_RX_0_CHAN */
+ <0x2f>, /* SAUL_RX_1_CHAN */
+ <0x31>, /* SAUL_RX_2_CHAN */
+ <0x33>; /* SAUL_RX_3_CHAN */
+ ti,sci-rm-range-rflow = <0x2a>, /* FLOW_UNMAPPED_RX_CHAN */
+ <0x2c>, /* FLOW_CPSW_RX_CHAN */
+ <0x2e>, /* FLOW_SAUL_RX_0/1_CHAN */
+ <0x32>; /* FLOW_SAUL_RX_2/3_CHAN */
+ };
};
dmsc: system-controller@44043000 {
@@ -77,8 +150,8 @@
reg-names = "debug_messages";
ti,host-id = <12>;
mbox-names = "rx", "tx";
- mboxes= <&secure_proxy_main 12>,
- <&secure_proxy_main 13>;
+ mboxes = <&secure_proxy_main 12>,
+ <&secure_proxy_main 13>;
k3_pds: power-controller {
compatible = "ti,sci-pm-domain";
@@ -96,6 +169,21 @@
};
};
+ secure_proxy_sa3: mailbox@43600000 {
+ compatible = "ti,am654-secure-proxy";
+ #mbox-cells = <1>;
+ reg-names = "target_data", "rt", "scfg";
+ reg = <0x00 0x43600000 0x00 0x10000>,
+ <0x00 0x44880000 0x00 0x20000>,
+ <0x00 0x44860000 0x00 0x20000>;
+ /*
+ * Marked Disabled:
+ * Node is incomplete as it is meant for bootloaders and
+ * firmware on non-MPU processors
+ */
+ status = "disabled";
+ };
+
main_pmx0: pinctrl@f4000 {
compatible = "pinctrl-single";
reg = <0x00 0xf4000 0x00 0x2ac>;
@@ -104,6 +192,102 @@
pinctrl-single,function-mask = <0xffffffff>;
};
+ main_timer0: timer@2400000 {
+ compatible = "ti,am654-timer";
+ reg = <0x00 0x2400000 0x00 0x400>;
+ interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&k3_clks 36 2>;
+ clock-names = "fck";
+ assigned-clocks = <&k3_clks 36 2>;
+ assigned-clock-parents = <&k3_clks 36 3>;
+ power-domains = <&k3_pds 36 TI_SCI_PD_EXCLUSIVE>;
+ ti,timer-pwm;
+ };
+
+ main_timer1: timer@2410000 {
+ compatible = "ti,am654-timer";
+ reg = <0x00 0x2410000 0x00 0x400>;
+ interrupts = <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&k3_clks 37 2>;
+ clock-names = "fck";
+ assigned-clocks = <&k3_clks 37 2>;
+ assigned-clock-parents = <&k3_clks 37 3>;
+ power-domains = <&k3_pds 37 TI_SCI_PD_EXCLUSIVE>;
+ ti,timer-pwm;
+ };
+
+ main_timer2: timer@2420000 {
+ compatible = "ti,am654-timer";
+ reg = <0x00 0x2420000 0x00 0x400>;
+ interrupts = <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&k3_clks 38 2>;
+ clock-names = "fck";
+ assigned-clocks = <&k3_clks 38 2>;
+ assigned-clock-parents = <&k3_clks 38 3>;
+ power-domains = <&k3_pds 38 TI_SCI_PD_EXCLUSIVE>;
+ ti,timer-pwm;
+ };
+
+ main_timer3: timer@2430000 {
+ compatible = "ti,am654-timer";
+ reg = <0x00 0x2430000 0x00 0x400>;
+ interrupts = <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&k3_clks 39 2>;
+ clock-names = "fck";
+ assigned-clocks = <&k3_clks 39 2>;
+ assigned-clock-parents = <&k3_clks 39 3>;
+ power-domains = <&k3_pds 39 TI_SCI_PD_EXCLUSIVE>;
+ ti,timer-pwm;
+ };
+
+ main_timer4: timer@2440000 {
+ compatible = "ti,am654-timer";
+ reg = <0x00 0x2440000 0x00 0x400>;
+ interrupts = <GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&k3_clks 40 2>;
+ clock-names = "fck";
+ assigned-clocks = <&k3_clks 40 2>;
+ assigned-clock-parents = <&k3_clks 40 3>;
+ power-domains = <&k3_pds 40 TI_SCI_PD_EXCLUSIVE>;
+ ti,timer-pwm;
+ };
+
+ main_timer5: timer@2450000 {
+ compatible = "ti,am654-timer";
+ reg = <0x00 0x2450000 0x00 0x400>;
+ interrupts = <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&k3_clks 41 2>;
+ clock-names = "fck";
+ assigned-clocks = <&k3_clks 41 2>;
+ assigned-clock-parents = <&k3_clks 41 3>;
+ power-domains = <&k3_pds 41 TI_SCI_PD_EXCLUSIVE>;
+ ti,timer-pwm;
+ };
+
+ main_timer6: timer@2460000 {
+ compatible = "ti,am654-timer";
+ reg = <0x00 0x2460000 0x00 0x400>;
+ interrupts = <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&k3_clks 42 2>;
+ clock-names = "fck";
+ assigned-clocks = <&k3_clks 42 2>;
+ assigned-clock-parents = <&k3_clks 42 3>;
+ power-domains = <&k3_pds 42 TI_SCI_PD_EXCLUSIVE>;
+ ti,timer-pwm;
+ };
+
+ main_timer7: timer@2470000 {
+ compatible = "ti,am654-timer";
+ reg = <0x00 0x2470000 0x00 0x400>;
+ interrupts = <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&k3_clks 43 2>;
+ clock-names = "fck";
+ assigned-clocks = <&k3_clks 43 2>;
+ assigned-clock-parents = <&k3_clks 43 3>;
+ power-domains = <&k3_pds 43 TI_SCI_PD_EXCLUSIVE>;
+ ti,timer-pwm;
+ };
+
main_uart0: serial@2800000 {
compatible = "ti,am64-uart", "ti,am654-uart";
reg = <0x00 0x02800000 0x00 0x100>;
@@ -222,6 +406,39 @@
status = "disabled";
};
+ main_spi0: spi@20100000 {
+ compatible = "ti,am654-mcspi", "ti,omap4-mcspi";
+ reg = <0x00 0x20100000 0x00 0x400>;
+ interrupts = <GIC_SPI 172 IRQ_TYPE_LEVEL_HIGH>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ power-domains = <&k3_pds 141 TI_SCI_PD_EXCLUSIVE>;
+ clocks = <&k3_clks 141 0>;
+ status = "disabled";
+ };
+
+ main_spi1: spi@20110000 {
+ compatible = "ti,am654-mcspi","ti,omap4-mcspi";
+ reg = <0x00 0x20110000 0x00 0x400>;
+ interrupts = <GIC_SPI 173 IRQ_TYPE_LEVEL_HIGH>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ power-domains = <&k3_pds 142 TI_SCI_PD_EXCLUSIVE>;
+ clocks = <&k3_clks 142 0>;
+ status = "disabled";
+ };
+
+ main_spi2: spi@20120000 {
+ compatible = "ti,am654-mcspi","ti,omap4-mcspi";
+ reg = <0x00 0x20120000 0x00 0x400>;
+ interrupts = <GIC_SPI 174 IRQ_TYPE_LEVEL_HIGH>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ power-domains = <&k3_pds 143 TI_SCI_PD_EXCLUSIVE>;
+ clocks = <&k3_clks 143 0>;
+ status = "disabled";
+ };
+
main_gpio_intr: interrupt-controller@a00000 {
compatible = "ti,sci-intr";
reg = <0x00 0x00a00000 0x00 0x800>;
@@ -295,4 +512,368 @@
no-1-8-v;
status = "disabled";
};
+
+ usbss0: dwc3-usb@f900000 {
+ compatible = "ti,am62-usb";
+ reg = <0x00 0x0f900000 0x00 0x800>;
+ clocks = <&k3_clks 161 3>;
+ clock-names = "ref";
+ ti,syscon-phy-pll-refclk = <&wkup_conf 0x4008>;
+ #address-cells = <2>;
+ #size-cells = <2>;
+ power-domains = <&k3_pds 178 TI_SCI_PD_EXCLUSIVE>;
+ ranges;
+ status = "disabled";
+
+ usb0: usb@31000000 {
+ compatible = "snps,dwc3";
+ reg = <0x00 0x31000000 0x00 0x50000>;
+ interrupts = <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>, /* irq.0 */
+ <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>; /* irq.0 */
+ interrupt-names = "host", "peripheral";
+ maximum-speed = "high-speed";
+ dr_mode = "otg";
+ };
+ };
+
+ usbss1: dwc3-usb@f910000 {
+ compatible = "ti,am62-usb";
+ reg = <0x00 0x0f910000 0x00 0x800>;
+ clocks = <&k3_clks 162 3>;
+ clock-names = "ref";
+ ti,syscon-phy-pll-refclk = <&wkup_conf 0x4018>;
+ #address-cells = <2>;
+ #size-cells = <2>;
+ power-domains = <&k3_pds 179 TI_SCI_PD_EXCLUSIVE>;
+ ranges;
+ status = "disabled";
+
+ usb1: usb@31100000 {
+ compatible = "snps,dwc3";
+ reg = <0x00 0x31100000 0x00 0x50000>;
+ interrupts = <GIC_SPI 226 IRQ_TYPE_LEVEL_HIGH>, /* irq.0 */
+ <GIC_SPI 226 IRQ_TYPE_LEVEL_HIGH>; /* irq.0 */
+ interrupt-names = "host", "peripheral";
+ maximum-speed = "high-speed";
+ dr_mode = "otg";
+ };
+ };
+
+ fss: bus@fc00000 {
+ compatible = "simple-bus";
+ reg = <0x00 0x0fc00000 0x00 0x70000>;
+ #address-cells = <2>;
+ #size-cells = <2>;
+ ranges;
+ status = "disabled";
+
+ ospi0: spi@fc40000 {
+ compatible = "ti,am654-ospi", "cdns,qspi-nor";
+ reg = <0x00 0x0fc40000 0x00 0x100>,
+ <0x05 0x00000000 0x01 0x00000000>;
+ interrupts = <GIC_SPI 139 IRQ_TYPE_LEVEL_HIGH>;
+ cdns,fifo-depth = <256>;
+ cdns,fifo-width = <4>;
+ cdns,trigger-address = <0x0>;
+ clocks = <&k3_clks 75 7>;
+ assigned-clocks = <&k3_clks 75 7>;
+ assigned-clock-parents = <&k3_clks 75 8>;
+ assigned-clock-rates = <166666666>;
+ power-domains = <&k3_pds 75 TI_SCI_PD_EXCLUSIVE>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+ };
+
+ cpsw3g: ethernet@8000000 {
+ compatible = "ti,am642-cpsw-nuss";
+ #address-cells = <2>;
+ #size-cells = <2>;
+ reg = <0x0 0x8000000 0x0 0x200000>;
+ reg-names = "cpsw_nuss";
+ ranges = <0x0 0x0 0x0 0x8000000 0x0 0x200000>;
+ clocks = <&k3_clks 13 0>;
+ assigned-clocks = <&k3_clks 13 3>;
+ assigned-clock-parents = <&k3_clks 13 11>;
+ clock-names = "fck";
+ power-domains = <&k3_pds 13 TI_SCI_PD_EXCLUSIVE>;
+ status = "disabled";
+
+ dmas = <&main_pktdma 0xc600 15>,
+ <&main_pktdma 0xc601 15>,
+ <&main_pktdma 0xc602 15>,
+ <&main_pktdma 0xc603 15>,
+ <&main_pktdma 0xc604 15>,
+ <&main_pktdma 0xc605 15>,
+ <&main_pktdma 0xc606 15>,
+ <&main_pktdma 0xc607 15>,
+ <&main_pktdma 0x4600 15>;
+ dma-names = "tx0", "tx1", "tx2", "tx3", "tx4", "tx5", "tx6",
+ "tx7", "rx";
+
+ ethernet-ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ cpsw_port1: port@1 {
+ reg = <1>;
+ ti,mac-only;
+ label = "port1";
+ phys = <&phy_gmii_sel 1>;
+ mac-address = [00 00 00 00 00 00];
+ ti,syscon-efuse = <&wkup_conf 0x200>;
+ };
+
+ cpsw_port2: port@2 {
+ reg = <2>;
+ ti,mac-only;
+ label = "port2";
+ phys = <&phy_gmii_sel 2>;
+ mac-address = [00 00 00 00 00 00];
+ };
+ };
+
+ cpsw3g_mdio: mdio@f00 {
+ compatible = "ti,cpsw-mdio","ti,davinci_mdio";
+ reg = <0x0 0xf00 0x0 0x100>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ clocks = <&k3_clks 13 0>;
+ clock-names = "fck";
+ bus_freq = <1000000>;
+ };
+
+ cpts@3d000 {
+ compatible = "ti,j721e-cpts";
+ reg = <0x0 0x3d000 0x0 0x400>;
+ clocks = <&k3_clks 13 3>;
+ clock-names = "cpts";
+ interrupts-extended = <&gic500 GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "cpts";
+ ti,cpts-ext-ts-inputs = <4>;
+ ti,cpts-periodic-outputs = <2>;
+ };
+ };
+
+ hwspinlock: spinlock@2a000000 {
+ compatible = "ti,am64-hwspinlock";
+ reg = <0x00 0x2a000000 0x00 0x1000>;
+ #hwlock-cells = <1>;
+ };
+
+ mailbox0_cluster0: mailbox@29000000 {
+ compatible = "ti,am64-mailbox";
+ reg = <0x00 0x29000000 0x00 0x200>;
+ interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>;
+ #mbox-cells = <1>;
+ ti,mbox-num-users = <4>;
+ ti,mbox-num-fifos = <16>;
+ };
+
+ mailbox0_cluster1: mailbox@29010000 {
+ compatible = "ti,am64-mailbox";
+ reg = <0x00 0x29010000 0x00 0x200>;
+ interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>;
+ #mbox-cells = <1>;
+ ti,mbox-num-users = <4>;
+ ti,mbox-num-fifos = <16>;
+ };
+
+ mailbox0_cluster2: mailbox@29020000 {
+ compatible = "ti,am64-mailbox";
+ reg = <0x00 0x29020000 0x00 0x200>;
+ interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>;
+ #mbox-cells = <1>;
+ ti,mbox-num-users = <4>;
+ ti,mbox-num-fifos = <16>;
+ };
+
+ mailbox0_cluster3: mailbox@29030000 {
+ compatible = "ti,am64-mailbox";
+ reg = <0x00 0x29030000 0x00 0x200>;
+ interrupts = <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>;
+ #mbox-cells = <1>;
+ ti,mbox-num-users = <4>;
+ ti,mbox-num-fifos = <16>;
+ };
+
+ main_mcan0: can@20701000 {
+ compatible = "bosch,m_can";
+ reg = <0x00 0x20701000 0x00 0x200>,
+ <0x00 0x20708000 0x00 0x8000>;
+ reg-names = "m_can", "message_ram";
+ power-domains = <&k3_pds 98 TI_SCI_PD_EXCLUSIVE>;
+ clocks = <&k3_clks 98 6>, <&k3_clks 98 1>;
+ clock-names = "hclk", "cclk";
+ interrupts = <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 156 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "int0", "int1";
+ bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>;
+ status = "disabled";
+ };
+
+ main_rti0: watchdog@e000000 {
+ compatible = "ti,j7-rti-wdt";
+ reg = <0x00 0x0e000000 0x00 0x100>;
+ clocks = <&k3_clks 125 0>;
+ power-domains = <&k3_pds 125 TI_SCI_PD_EXCLUSIVE>;
+ assigned-clocks = <&k3_clks 125 0>;
+ assigned-clock-parents = <&k3_clks 125 2>;
+ };
+
+ main_rti1: watchdog@e010000 {
+ compatible = "ti,j7-rti-wdt";
+ reg = <0x00 0x0e010000 0x00 0x100>;
+ clocks = <&k3_clks 126 0>;
+ power-domains = <&k3_pds 126 TI_SCI_PD_EXCLUSIVE>;
+ assigned-clocks = <&k3_clks 126 0>;
+ assigned-clock-parents = <&k3_clks 126 2>;
+ };
+
+ main_rti2: watchdog@e020000 {
+ compatible = "ti,j7-rti-wdt";
+ reg = <0x00 0x0e020000 0x00 0x100>;
+ clocks = <&k3_clks 127 0>;
+ power-domains = <&k3_pds 127 TI_SCI_PD_EXCLUSIVE>;
+ assigned-clocks = <&k3_clks 127 0>;
+ assigned-clock-parents = <&k3_clks 127 2>;
+ };
+
+ main_rti3: watchdog@e030000 {
+ compatible = "ti,j7-rti-wdt";
+ reg = <0x00 0x0e030000 0x00 0x100>;
+ clocks = <&k3_clks 128 0>;
+ power-domains = <&k3_pds 128 TI_SCI_PD_EXCLUSIVE>;
+ assigned-clocks = <&k3_clks 128 0>;
+ assigned-clock-parents = <&k3_clks 128 2>;
+ };
+
+ main_rti4: watchdog@e040000 {
+ compatible = "ti,j7-rti-wdt";
+ reg = <0x00 0x0e040000 0x00 0x100>;
+ clocks = <&k3_clks 205 0>;
+ power-domains = <&k3_pds 205 TI_SCI_PD_EXCLUSIVE>;
+ assigned-clocks = <&k3_clks 205 0>;
+ assigned-clock-parents = <&k3_clks 205 2>;
+ };
+
+ epwm0: pwm@23000000 {
+ compatible = "ti,am64-epwm", "ti,am3352-ehrpwm";
+ #pwm-cells = <3>;
+ reg = <0x00 0x23000000 0x00 0x100>;
+ power-domains = <&k3_pds 86 TI_SCI_PD_EXCLUSIVE>;
+ clocks = <&epwm_tbclk 0>, <&k3_clks 86 0>;
+ clock-names = "tbclk", "fck";
+ status = "disabled";
+ };
+
+ epwm1: pwm@23010000 {
+ compatible = "ti,am64-epwm", "ti,am3352-ehrpwm";
+ #pwm-cells = <3>;
+ reg = <0x00 0x23010000 0x00 0x100>;
+ power-domains = <&k3_pds 87 TI_SCI_PD_EXCLUSIVE>;
+ clocks = <&epwm_tbclk 1>, <&k3_clks 87 0>;
+ clock-names = "tbclk", "fck";
+ status = "disabled";
+ };
+
+ epwm2: pwm@23020000 {
+ compatible = "ti,am64-epwm", "ti,am3352-ehrpwm";
+ #pwm-cells = <3>;
+ reg = <0x00 0x23020000 0x00 0x100>;
+ power-domains = <&k3_pds 88 TI_SCI_PD_EXCLUSIVE>;
+ clocks = <&epwm_tbclk 2>, <&k3_clks 88 0>;
+ clock-names = "tbclk", "fck";
+ status = "disabled";
+ };
+
+ ecap0: pwm@23100000 {
+ compatible = "ti,am3352-ecap";
+ #pwm-cells = <3>;
+ reg = <0x00 0x23100000 0x00 0x100>;
+ power-domains = <&k3_pds 51 TI_SCI_PD_EXCLUSIVE>;
+ clocks = <&k3_clks 51 0>;
+ clock-names = "fck";
+ status = "disabled";
+ };
+
+ ecap1: pwm@23110000 {
+ compatible = "ti,am3352-ecap";
+ #pwm-cells = <3>;
+ reg = <0x00 0x23110000 0x00 0x100>;
+ power-domains = <&k3_pds 52 TI_SCI_PD_EXCLUSIVE>;
+ clocks = <&k3_clks 52 0>;
+ clock-names = "fck";
+ status = "disabled";
+ };
+
+ ecap2: pwm@23120000 {
+ compatible = "ti,am3352-ecap";
+ #pwm-cells = <3>;
+ reg = <0x00 0x23120000 0x00 0x100>;
+ power-domains = <&k3_pds 53 TI_SCI_PD_EXCLUSIVE>;
+ clocks = <&k3_clks 53 0>;
+ clock-names = "fck";
+ status = "disabled";
+ };
+
+ mcasp0: audio-controller@2b00000 {
+ compatible = "ti,am33xx-mcasp-audio";
+ reg = <0x00 0x02b00000 0x00 0x2000>,
+ <0x00 0x02b08000 0x00 0x400>;
+ reg-names = "mpu", "dat";
+ interrupts = <GIC_SPI 236 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 235 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "tx", "rx";
+
+ dmas = <&main_bcdma 0 0xc500 0>, <&main_bcdma 0 0x4500 0>;
+ dma-names = "tx", "rx";
+
+ clocks = <&k3_clks 190 0>;
+ clock-names = "fck";
+ assigned-clocks = <&k3_clks 190 0>;
+ assigned-clock-parents = <&k3_clks 190 2>;
+ power-domains = <&k3_pds 190 TI_SCI_PD_EXCLUSIVE>;
+ status = "disabled";
+ };
+
+ mcasp1: audio-controller@2b10000 {
+ compatible = "ti,am33xx-mcasp-audio";
+ reg = <0x00 0x02b10000 0x00 0x2000>,
+ <0x00 0x02b18000 0x00 0x400>;
+ reg-names = "mpu", "dat";
+ interrupts = <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 237 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "tx", "rx";
+
+ dmas = <&main_bcdma 0 0xc501 0>, <&main_bcdma 0 0x4501 0>;
+ dma-names = "tx", "rx";
+
+ clocks = <&k3_clks 191 0>;
+ clock-names = "fck";
+ assigned-clocks = <&k3_clks 191 0>;
+ assigned-clock-parents = <&k3_clks 191 2>;
+ power-domains = <&k3_pds 191 TI_SCI_PD_EXCLUSIVE>;
+ status = "disabled";
+ };
+
+ mcasp2: audio-controller@2b20000 {
+ compatible = "ti,am33xx-mcasp-audio";
+ reg = <0x00 0x02b20000 0x00 0x2000>,
+ <0x00 0x02b28000 0x00 0x400>;
+ reg-names = "mpu", "dat";
+ interrupts = <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 239 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "tx", "rx";
+
+ dmas = <&main_bcdma 0 0xc502 0>, <&main_bcdma 0 0x4502 0>;
+ dma-names = "tx", "rx";
+
+ clocks = <&k3_clks 192 0>;
+ clock-names = "fck";
+ assigned-clocks = <&k3_clks 192 0>;
+ assigned-clock-parents = <&k3_clks 192 2>;
+ power-domains = <&k3_pds 192 TI_SCI_PD_EXCLUSIVE>;
+ status = "disabled";
+ };
};
diff --git a/arch/arm/dts/k3-am62a-mcu.dtsi b/arch/arm/dts/k3-am62a-mcu.dtsi
index 6d1e501..a6d16a9 100644
--- a/arch/arm/dts/k3-am62a-mcu.dtsi
+++ b/arch/arm/dts/k3-am62a-mcu.dtsi
@@ -15,6 +15,51 @@
status = "disabled";
};
+ /*
+ * The MCU domain timer interrupts are routed only to the ESM module,
+ * and not currently available for Linux. The MCU domain timers are
+ * of limited use without interrupts, and likely reserved by the ESM.
+ */
+ mcu_timer0: timer@4800000 {
+ compatible = "ti,am654-timer";
+ reg = <0x00 0x4800000 0x00 0x400>;
+ clocks = <&k3_clks 35 2>;
+ clock-names = "fck";
+ power-domains = <&k3_pds 35 TI_SCI_PD_EXCLUSIVE>;
+ ti,timer-pwm;
+ status = "reserved";
+ };
+
+ mcu_timer1: timer@4810000 {
+ compatible = "ti,am654-timer";
+ reg = <0x00 0x4810000 0x00 0x400>;
+ clocks = <&k3_clks 48 2>;
+ clock-names = "fck";
+ power-domains = <&k3_pds 48 TI_SCI_PD_EXCLUSIVE>;
+ ti,timer-pwm;
+ status = "reserved";
+ };
+
+ mcu_timer2: timer@4820000 {
+ compatible = "ti,am654-timer";
+ reg = <0x00 0x4820000 0x00 0x400>;
+ clocks = <&k3_clks 49 2>;
+ clock-names = "fck";
+ power-domains = <&k3_pds 49 TI_SCI_PD_EXCLUSIVE>;
+ ti,timer-pwm;
+ status = "reserved";
+ };
+
+ mcu_timer3: timer@4830000 {
+ compatible = "ti,am654-timer";
+ reg = <0x00 0x4830000 0x00 0x400>;
+ clocks = <&k3_clks 50 2>;
+ clock-names = "fck";
+ power-domains = <&k3_pds 50 TI_SCI_PD_EXCLUSIVE>;
+ ti,timer-pwm;
+ status = "reserved";
+ };
+
mcu_uart0: serial@4a00000 {
compatible = "ti,am64-uart", "ti,am654-uart";
reg = <0x00 0x04a00000 0x00 0x100>;
@@ -36,4 +81,90 @@
clock-names = "fck";
status = "disabled";
};
+
+ mcu_spi0: spi@4b00000 {
+ compatible = "ti,am654-mcspi", "ti,omap4-mcspi";
+ reg = <0x00 0x04b00000 0x00 0x400>;
+ interrupts = <GIC_SPI 176 IRQ_TYPE_LEVEL_HIGH>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ power-domains = <&k3_pds 147 TI_SCI_PD_EXCLUSIVE>;
+ clocks = <&k3_clks 147 0>;
+ status = "disabled";
+ };
+
+ mcu_spi1: spi@4b10000 {
+ compatible = "ti,am654-mcspi","ti,omap4-mcspi";
+ reg = <0x00 0x04b10000 0x00 0x400>;
+ interrupts = <GIC_SPI 177 IRQ_TYPE_LEVEL_HIGH>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ power-domains = <&k3_pds 148 TI_SCI_PD_EXCLUSIVE>;
+ clocks = <&k3_clks 148 0>;
+ status = "disabled";
+ };
+
+ mcu_gpio_intr: interrupt-controller@4210000 {
+ compatible = "ti,sci-intr";
+ reg = <0x00 0x04210000 0x00 0x200>;
+ ti,intr-trigger-type = <1>;
+ interrupt-controller;
+ interrupt-parent = <&gic500>;
+ #interrupt-cells = <1>;
+ ti,sci = <&dmsc>;
+ ti,sci-dev-id = <5>;
+ ti,interrupt-ranges = <0 104 4>;
+ };
+
+ mcu_gpio0: gpio@4201000 {
+ compatible = "ti,am64-gpio", "ti,keystone-gpio";
+ reg = <0x00 0x04201000 0x00 0x100>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ interrupt-parent = <&mcu_gpio_intr>;
+ interrupts = <30>, <31>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ ti,ngpio = <24>;
+ ti,davinci-gpio-unbanked = <0>;
+ power-domains = <&k3_pds 79 TI_SCI_PD_EXCLUSIVE>;
+ clocks = <&k3_clks 79 0>;
+ clock-names = "gpio";
+ status = "disabled";
+ };
+
+ mcu_rti0: watchdog@4880000 {
+ compatible = "ti,j7-rti-wdt";
+ reg = <0x00 0x04880000 0x00 0x100>;
+ clocks = <&k3_clks 131 0>;
+ power-domains = <&k3_pds 131 TI_SCI_PD_EXCLUSIVE>;
+ assigned-clocks = <&k3_clks 131 0>;
+ assigned-clock-parents = <&k3_clks 131 2>;
+ /* Tightly coupled to M4F */
+ status = "reserved";
+ };
+
+ mcu_mcan0: can@4e08000 {
+ compatible = "bosch,m_can";
+ reg = <0x00 0x4e08000 0x00 0x200>,
+ <0x00 0x4e00000 0x00 0x8000>;
+ reg-names = "m_can", "message_ram";
+ power-domains = <&k3_pds 188 TI_SCI_PD_EXCLUSIVE>;
+ clocks = <&k3_clks 188 6>, <&k3_clks 188 1>;
+ clock-names = "hclk", "cclk";
+ bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>;
+ status = "disabled";
+ };
+
+ mcu_mcan1: can@4e18000 {
+ compatible = "bosch,m_can";
+ reg = <0x00 0x4e18000 0x00 0x200>,
+ <0x00 0x4e10000 0x00 0x8000>;
+ reg-names = "m_can", "message_ram";
+ power-domains = <&k3_pds 189 TI_SCI_PD_EXCLUSIVE>;
+ clocks = <&k3_clks 189 6>, <&k3_clks 189 1>;
+ clock-names = "hclk", "cclk";
+ bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>;
+ status = "disabled";
+ };
};
diff --git a/arch/arm/dts/k3-am62a-sk-binman.dtsi b/arch/arm/dts/k3-am62a-sk-binman.dtsi
index de09430..c5e027d 100644
--- a/arch/arm/dts/k3-am62a-sk-binman.dtsi
+++ b/arch/arm/dts/k3-am62a-sk-binman.dtsi
@@ -144,10 +144,7 @@
#ifdef CONFIG_TARGET_AM62A7_A53_EVM
-#define SPL_NODTB "spl/u-boot-spl-nodtb.bin"
#define SPL_AM62A7_SK_DTB "spl/dts/k3-am62a7-sk.dtb"
-
-#define UBOOT_NODTB "u-boot-nodtb.bin"
#define AM62A7_SK_DTB "u-boot.dtb"
&binman {
@@ -158,55 +155,11 @@
};
};
ti-spl {
- filename = "tispl.bin";
- pad-byte = <0xff>;
+ insert-template = <&ti_spl_template>;
fit {
- description = "Configuration to load ATF and SPL";
- #address-cells = <1>;
-
images {
-
- atf {
- description = "ARM Trusted Firmware";
- type = "firmware";
- arch = "arm64";
- compression = "none";
- os = "arm-trusted-firmware";
- load = <CONFIG_K3_ATF_LOAD_ADDR>;
- entry = <CONFIG_K3_ATF_LOAD_ADDR>;
- ti-secure {
- content = <&atf>;
- keyfile = "custMpk.pem";
- };
- atf: atf-bl31 {
- };
- };
-
- tee {
- description = "OP-TEE";
- type = "tee";
- arch = "arm64";
- compression = "none";
- os = "tee";
- load = <0x9e800000>;
- entry = <0x9e800000>;
- ti-secure {
- content = <&tee>;
- keyfile = "custMpk.pem";
- };
- tee: tee-os {
- };
- };
-
dm {
- description = "DM binary";
- type = "firmware";
- arch = "arm32";
- compression = "none";
- os = "DM";
- load = <0x89000000>;
- entry = <0x89000000>;
ti-secure {
content = <&dm>;
keyfile = "custMpk.pem";
@@ -216,23 +169,6 @@
};
};
- spl {
- description = "SPL (64-bit)";
- type = "standalone";
- os = "U-Boot";
- arch = "arm64";
- compression = "none";
- load = <CONFIG_SPL_TEXT_BASE>;
- entry = <CONFIG_SPL_TEXT_BASE>;
- ti-secure {
- content = <&u_boot_spl_nodtb>;
- keyfile = "custMpk.pem";
- };
- u_boot_spl_nodtb: blob-ext {
- filename = SPL_NODTB;
- };
- };
-
fdt-0 {
description = "k3-am62a7-sk";
type = "flat_dt";
@@ -266,29 +202,12 @@
&binman {
u-boot {
- filename = "u-boot.img";
- pad-byte = <0xff>;
+ insert-template = <&u_boot_template>;
fit {
- description = "FIT image with multiple configurations";
-
images {
uboot {
- description = "U-Boot for AM62Ax board";
- type = "firmware";
- os = "u-boot";
- arch = "arm";
- compression = "none";
- load = <CONFIG_TEXT_BASE>;
- ti-secure {
- content = <&u_boot_nodtb>;
- keyfile = "custMpk.pem";
- };
- u_boot_nodtb: u-boot-nodtb {
- };
- hash {
- algo = "crc32";
- };
+ description = "U-Boot for AM62Ax Board";
};
fdt-0 {
@@ -326,67 +245,16 @@
&binman {
ti-spl_unsigned {
- filename = "tispl.bin_unsigned";
- pad-byte = <0xff>;
+ insert-template = <&ti_spl_unsigned_template>;
fit {
- description = "Configuration to load ATF and SPL";
- #address-cells = <1>;
-
images {
-
- atf {
- description = "ARM Trusted Firmware";
- type = "firmware";
- arch = "arm64";
- compression = "none";
- os = "arm-trusted-firmware";
- load = <CONFIG_K3_ATF_LOAD_ADDR>;
- entry = <CONFIG_K3_ATF_LOAD_ADDR>;
- atf-bl31 {
- filename = "bl31.bin";
- };
- };
-
- tee {
- description = "OP-TEE";
- type = "tee";
- arch = "arm64";
- compression = "none";
- os = "tee";
- load = <0x9e800000>;
- entry = <0x9e800000>;
- tee-os {
- filename = "tee-raw.bin";
- };
- };
-
dm {
- description = "DM binary";
- type = "firmware";
- arch = "arm32";
- compression = "none";
- os = "DM";
- load = <0x89000000>;
- entry = <0x89000000>;
blob-ext {
filename = "ti-dm.bin";
};
};
- spl {
- description = "SPL (64-bit)";
- type = "standalone";
- os = "U-Boot";
- arch = "arm64";
- compression = "none";
- load = <CONFIG_SPL_TEXT_BASE>;
- entry = <CONFIG_SPL_TEXT_BASE>;
- blob {
- filename = "spl/u-boot-spl-nodtb.bin";
- };
- };
-
fdt-0 {
description = "k3-am62a7-sk";
type = "flat_dt";
@@ -414,26 +282,12 @@
&binman {
u-boot_unsigned {
- filename = "u-boot.img_unsigned";
- pad-byte = <0xff>;
+ insert-template = <&u_boot_unsigned_template>;
fit {
- description = "FIT image with multiple configurations";
-
images {
uboot {
- description = "U-Boot for AM62Ax board";
- type = "firmware";
- os = "u-boot";
- arch = "arm";
- compression = "none";
- load = <CONFIG_TEXT_BASE>;
- blob {
- filename = UBOOT_NODTB;
- };
- hash {
- algo = "crc32";
- };
+ description = "U-Boot for AM62Ax Board";
};
fdt-0 {
diff --git a/arch/arm/dts/k3-am62a-thermal.dtsi b/arch/arm/dts/k3-am62a-thermal.dtsi
new file mode 100644
index 0000000..85ce545
--- /dev/null
+++ b/arch/arm/dts/k3-am62a-thermal.dtsi
@@ -0,0 +1,47 @@
+// SPDX-License-Identifier: GPL-2.0
+
+#include <dt-bindings/thermal/thermal.h>
+
+thermal_zones: thermal-zones {
+ main0_thermal: main0-thermal {
+ polling-delay-passive = <250>; /* milliSeconds */
+ polling-delay = <500>; /* milliSeconds */
+ thermal-sensors = <&wkup_vtm0 0>;
+
+ trips {
+ main0_crit: main0-crit {
+ temperature = <125000>; /* milliCelsius */
+ hysteresis = <2000>; /* milliCelsius */
+ type = "critical";
+ };
+ };
+ };
+
+ main1_thermal: main1-thermal {
+ polling-delay-passive = <250>; /* milliSeconds */
+ polling-delay = <500>; /* milliSeconds */
+ thermal-sensors = <&wkup_vtm0 1>;
+
+ trips {
+ main1_crit: main1-crit {
+ temperature = <125000>; /* milliCelsius */
+ hysteresis = <2000>; /* milliCelsius */
+ type = "critical";
+ };
+ };
+ };
+
+ main2_thermal: main2-thermal {
+ polling-delay-passive = <250>; /* milliSeconds */
+ polling-delay = <500>; /* milliSeconds */
+ thermal-sensors = <&wkup_vtm0 2>;
+
+ trips {
+ main2_crit: main2-crit {
+ temperature = <125000>; /* milliCelsius */
+ hysteresis = <2000>; /* milliCelsius */
+ type = "critical";
+ };
+ };
+ };
+};
diff --git a/arch/arm/dts/k3-am62a-wakeup.dtsi b/arch/arm/dts/k3-am62a-wakeup.dtsi
index 99afac4..4e8279f 100644
--- a/arch/arm/dts/k3-am62a-wakeup.dtsi
+++ b/arch/arm/dts/k3-am62a-wakeup.dtsi
@@ -31,7 +31,7 @@
wkup_i2c0: i2c@2b200000 {
compatible = "ti,am64-i2c", "ti,omap4-i2c";
- reg = <0x00 0x02b200000 0x00 0x100>;
+ reg = <0x00 0x2b200000 0x00 0x100>;
interrupts = <GIC_SPI 165 IRQ_TYPE_LEVEL_HIGH>;
#address-cells = <1>;
#size-cells = <0>;
@@ -51,4 +51,23 @@
wakeup-source;
status = "disabled";
};
+
+ wkup_rti0: watchdog@2b000000 {
+ compatible = "ti,j7-rti-wdt";
+ reg = <0x00 0x2b000000 0x00 0x100>;
+ clocks = <&k3_clks 132 0>;
+ power-domains = <&k3_pds 132 TI_SCI_PD_EXCLUSIVE>;
+ assigned-clocks = <&k3_clks 132 0>;
+ assigned-clock-parents = <&k3_clks 132 2>;
+ /* Used by DM firmware */
+ status = "reserved";
+ };
+
+ wkup_vtm0: temperature-sensor@b00000 {
+ compatible = "ti,j7200-vtm";
+ reg = <0x00 0xb00000 0x00 0x400>,
+ <0x00 0xb01000 0x00 0x400>;
+ power-domains = <&k3_pds 95 TI_SCI_PD_EXCLUSIVE>;
+ #thermal-sensor-cells = <1>;
+ };
};
diff --git a/arch/arm/dts/k3-am62a.dtsi b/arch/arm/dts/k3-am62a.dtsi
index 6eb87c3..61a210e 100644
--- a/arch/arm/dts/k3-am62a.dtsi
+++ b/arch/arm/dts/k3-am62a.dtsi
@@ -8,9 +8,10 @@
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/interrupt-controller/irq.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
-#include <dt-bindings/pinctrl/k3.h>
#include <dt-bindings/soc/ti,sci_pm_domain.h>
+#include "k3-pinctrl.h"
+
/ {
model = "Texas Instruments K3 AM62A SoC";
compatible = "ti,am62a7";
@@ -114,6 +115,8 @@
<0x00 0x78100000 0x00 0x78100000 0x00 0x00008000>; /* DM R5 BTCM*/
};
};
+
+ #include "k3-am62a-thermal.dtsi"
};
/* Now include the peripherals for each bus segments */
diff --git a/arch/arm/dts/k3-am62a7-r5-sk.dts b/arch/arm/dts/k3-am62a7-r5-sk.dts
index bbbd9e5..bc05dcb 100644
--- a/arch/arm/dts/k3-am62a7-r5-sk.dts
+++ b/arch/arm/dts/k3-am62a7-r5-sk.dts
@@ -7,7 +7,6 @@
#include "k3-am62a7-sk.dts"
#include "k3-am62a-ddr-1866mhz-32bit.dtsi"
#include "k3-am62a-ddr.dtsi"
-#include "k3-am62a-sk-binman.dtsi"
#include "k3-am62a7-sk-u-boot.dtsi"
@@ -15,35 +14,8 @@
aliases {
remoteproc0 = &sysctrler;
remoteproc1 = &a53_0;
- serial0 = &wkup_uart0;
- serial3 = &main_uart1;
};
- chosen {
- stdout-path = "serial2:115200n8";
- tick-timer = &timer1;
- };
-
- memory@80000000 {
- device_type = "memory";
- /* 4G RAM */
- reg = <0x00000000 0x80000000 0x00000000 0x80000000>,
- <0x00000008 0x80000000 0x00000000 0x80000000>;
- bootph-pre-ram;
- };
-
- reserved-memory {
- #address-cells = <2>;
- #size-cells = <2>;
- ranges;
-
- secure_ddr: optee@9e800000 {
- reg = <0x00 0x9e800000 0x00 0x01800000>; /* for OP-TEE */
- alignment = <0x1000>;
- no-map;
- };
- };
-
a53_0: a53@0 {
compatible = "ti,am654-rproc";
reg = <0x00 0x00a90000 0x00 0x10>;
@@ -81,67 +53,39 @@
ti,secure-host;
};
-&cbass_main {
- sa3_secproxy: secproxy@44880000 {
- compatible = "ti,am654-secure-proxy";
- #mbox-cells = <1>;
- reg = <0x00 0x44880000 0x00 0x20000>,
- <0x0 0x44860000 0x0 0x20000>,
- <0x0 0x43600000 0x0 0x10000>;
- reg-names = "rt", "scfg", "target_data";
- bootph-pre-ram;
- };
+&secure_proxy_sa3 {
+ /* Needed for initial handshake with ROM */
+ status = "okay";
+ bootph-pre-ram;
+};
+&cbass_main {
sysctrler: sysctrler {
compatible = "ti,am654-system-controller";
mboxes= <&secure_proxy_main 1>,
<&secure_proxy_main 0>,
- <&sa3_secproxy 0>;
+ <&secure_proxy_sa3 0>;
mbox-names = "tx", "rx", "boot_notify";
bootph-pre-ram;
};
};
-&mcu_pmx0 {
- status = "okay";
+&wkup_uart0_pins_default {
bootph-pre-ram;
-
- wkup_uart0_pins_default: wkup-uart0-pins-default {
- pinctrl-single,pins = <
- AM62X_MCU_IOPAD(0x02c, PIN_INPUT, 0) /* (C6) WKUP_UART0_CTSn */
- AM62X_MCU_IOPAD(0x030, PIN_OUTPUT, 0) /* (A4) WKUP_UART0_RTSn */
- AM62X_MCU_IOPAD(0x024, PIN_INPUT, 0) /* (B4) WKUP_UART0_RXD */
- AM62X_MCU_IOPAD(0x028, PIN_OUTPUT, 0) /* (C5) WKUP_UART0_TXD */
- >;
- bootph-pre-ram;
- };
};
-&main_pmx0 {
+&main_uart1_pins_default {
bootph-pre-ram;
- main_uart1_pins_default: main-uart1-pins-default {
- pinctrl-single,pins = <
- AM62X_IOPAD(0x194, PIN_INPUT, 2) /* (B19) MCASP0_AXR3.UART1_CTSn */
- AM62X_IOPAD(0x198, PIN_OUTPUT, 2) /* (A19) MCASP0_AXR2.UART1_RTSn */
- AM62X_IOPAD(0x1ac, PIN_INPUT, 2) /* (E19) MCASP0_AFSR.UART1_RXD */
- AM62X_IOPAD(0x1b0, PIN_OUTPUT, 2) /* (A20) MCASP0_ACLKR.UART1_TXD */
- >;
- bootph-pre-ram;
- };
};
/* WKUP UART0 is used for DM firmware logs */
&wkup_uart0 {
- pinctrl-names = "default";
- pinctrl-0 = <&wkup_uart0_pins_default>;
status = "okay";
bootph-pre-ram;
};
/* Main UART1 is used for TIFS firmware logs */
&main_uart1 {
- pinctrl-names = "default";
- pinctrl-0 = <&main_uart1_pins_default>;
status = "okay";
bootph-pre-ram;
};
diff --git a/arch/arm/dts/k3-am62a7-sk-u-boot.dtsi b/arch/arm/dts/k3-am62a7-sk-u-boot.dtsi
index cf938c4..31b89b4 100644
--- a/arch/arm/dts/k3-am62a7-sk-u-boot.dtsi
+++ b/arch/arm/dts/k3-am62a7-sk-u-boot.dtsi
@@ -4,137 +4,186 @@
* Copyright (C) 2022 Texas Instruments Incorporated - https://www.ti.com/
*/
+#include "k3-am62a-sk-binman.dtsi"
+
/ {
chosen {
stdout-path = "serial2:115200n8";
- tick-timer = &timer1;
+ tick-timer = &main_timer0;
};
memory@80000000 {
- bootph-pre-ram;
+ bootph-all;
};
};
-&cbass_main{
- bootph-pre-ram;
+&main_timer0 {
+ bootph-all;
+};
- timer1: timer@2400000 {
- compatible = "ti,omap5430-timer";
- reg = <0x00 0x2400000 0x00 0x80>;
- ti,timer-alwon;
- clock-frequency = <25000000>;
- bootph-pre-ram;
- };
+&cbass_main {
+ bootph-all;
};
&dmss {
- bootph-pre-ram;
+ bootph-all;
};
&secure_proxy_main {
- bootph-pre-ram;
+ bootph-all;
};
&dmsc {
- bootph-pre-ram;
+ bootph-all;
};
&k3_pds {
- bootph-pre-ram;
+ bootph-all;
};
&k3_clks {
- bootph-pre-ram;
+ bootph-all;
};
&k3_reset {
- bootph-pre-ram;
+ bootph-all;
};
&wkup_conf {
- bootph-pre-ram;
+ bootph-all;
};
&chipid {
- bootph-pre-ram;
+ bootph-all;
};
&main_pmx0 {
- bootph-pre-ram;
+ bootph-all;
};
&main_uart0 {
- bootph-pre-ram;
+ bootph-all;
};
&main_uart0_pins_default {
- bootph-pre-ram;
+ bootph-all;
};
-&main_uart1 {
- bootph-pre-ram;
-};
-
&cbass_mcu {
- bootph-pre-ram;
+ bootph-all;
};
&cbass_wakeup {
- bootph-pre-ram;
+ bootph-all;
};
&mcu_pmx0 {
- bootph-pre-ram;
-};
-
-&wkup_uart0 {
- bootph-pre-ram;
+ bootph-all;
};
&main_gpio0 {
- bootph-pre-ram;
+ bootph-all;
};
&main_i2c0 {
- bootph-pre-ram;
+ bootph-all;
};
&main_i2c0_pins_default {
- bootph-pre-ram;
+ bootph-all;
};
&main_i2c1 {
- bootph-pre-ram;
+ bootph-all;
};
&main_i2c1_pins_default {
- bootph-pre-ram;
+ bootph-all;
};
&exp1 {
- bootph-pre-ram;
+ bootph-all;
};
&sdhci1 {
- bootph-pre-ram;
+ bootph-all;
};
&main_mmc1_pins_default {
- bootph-pre-ram;
+ bootph-all;
};
&k3_reset {
- bootph-pre-ram;
+ bootph-all;
};
&dmsc {
- bootph-pre-ram;
+ bootph-all;
k3_sysreset: sysreset-controller {
compatible = "ti,sci-sysreset";
- bootph-pre-ram;
+ bootph-all;
};
};
&vdd_mmc1 {
- bootph-pre-ram;
+ bootph-all;
+};
+
+&main_bcdma {
+ reg = <0x00 0x485c0100 0x00 0x100>,
+ <0x00 0x4c000000 0x00 0x20000>,
+ <0x00 0x4a820000 0x00 0x20000>,
+ <0x00 0x4aa40000 0x00 0x20000>,
+ <0x00 0x4bc00000 0x00 0x100000>,
+ <0x00 0x48600000 0x00 0x8000>,
+ <0x00 0x484a4000 0x00 0x2000>,
+ <0x00 0x484c2000 0x00 0x2000>;
+ reg-names = "gcfg", "bchanrt", "rchanrt", "tchanrt",
+ "ringrt" , "cfg", "tchan", "rchan";
+ bootph-all;
+};
+
+&main_pktdma {
+ reg = <0x00 0x485c0000 0x00 0x100>,
+ <0x00 0x4a800000 0x00 0x20000>,
+ <0x00 0x4aa00000 0x00 0x20000>,
+ <0x00 0x4b800000 0x00 0x200000>,
+ <0x00 0x485e0000 0x00 0x10000>,
+ <0x00 0x484a0000 0x00 0x2000>,
+ <0x00 0x484c0000 0x00 0x2000>,
+ <0x00 0x48430000 0x00 0x1000>;
+ reg-names = "gcfg", "rchanrt", "tchanrt", "ringrt",
+ "cfg", "tchan", "rchan", "rflow";
+ bootph-all;
+};
+
+&main_mdio1_pins_default {
+ bootph-all;
+};
+
+&cpsw3g_mdio {
+ bootph-all;
+};
+
+&cpsw3g_phy0 {
+ bootph-all;
+};
+
+&main_rgmii1_pins_default {
+ bootph-all;
+};
+
+&phy_gmii_sel {
+ bootph-all;
+};
+
+&cpsw3g {
+ bootph-all;
+ ethernet-ports {
+ bootph-all;
+ };
+};
+
+&cpsw_port1 {
+ bootph-all;
};
diff --git a/arch/arm/dts/k3-am62a7-sk.dts b/arch/arm/dts/k3-am62a7-sk.dts
index 270e669..8f64ac2 100644
--- a/arch/arm/dts/k3-am62a7-sk.dts
+++ b/arch/arm/dts/k3-am62a7-sk.dts
@@ -9,15 +9,17 @@
#include <dt-bindings/leds/common.h>
#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/net/ti-dp83867.h>
#include "k3-am62a7.dtsi"
-#include "k3-am62a-sk-binman.dtsi"
/ {
- compatible = "ti,am62a7-sk", "ti,am62a7";
+ compatible = "ti,am62a7-sk", "ti,am62a7";
model = "Texas Instruments AM62A7 SK";
aliases {
+ serial0 = &wkup_uart0;
serial2 = &main_uart0;
+ serial3 = &main_uart1;
mmc1 = &sdhci1;
};
@@ -77,10 +79,10 @@
regulator-boot-on;
};
- vcc_3v3_sys: regulator-2 {
+ vcc_3v3_main: regulator-2 {
/* output of LM5141-Q1 */
compatible = "regulator-fixed";
- regulator-name = "vcc_3v3_sys";
+ regulator-name = "vcc_3v3_main";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
vin-supply = <&vmain_pd>;
@@ -99,6 +101,17 @@
gpio = <&exp1 3 GPIO_ACTIVE_HIGH>;
};
+ vcc_3v3_sys: regulator-4 {
+ /* output of TPS222965DSGT */
+ compatible = "regulator-fixed";
+ regulator-name = "vcc_3v3_sys";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ vin-supply = <&vcc_3v3_main>;
+ regulator-always-on;
+ regulator-boot-on;
+ };
+
leds {
compatible = "gpio-leds";
pinctrl-names = "default";
@@ -111,39 +124,101 @@
function = LED_FUNCTION_HEARTBEAT;
default-state = "off";
};
+ };
+
+ tlv320_mclk: clk-0 {
+ #clock-cells = <0>;
+ compatible = "fixed-clock";
+ clock-frequency = <12288000>;
+ };
+
+ codec_audio: sound {
+ compatible = "simple-audio-card";
+ simple-audio-card,name = "AM62Ax-SKEVM";
+ simple-audio-card,widgets =
+ "Headphone", "Headphone Jack",
+ "Line", "Line In",
+ "Microphone", "Microphone Jack";
+ simple-audio-card,routing =
+ "Headphone Jack", "HPLOUT",
+ "Headphone Jack", "HPROUT",
+ "LINE1L", "Line In",
+ "LINE1R", "Line In",
+ "MIC3R", "Microphone Jack",
+ "Microphone Jack", "Mic Bias";
+ simple-audio-card,format = "dsp_b";
+ simple-audio-card,bitclock-master = <&sound_master>;
+ simple-audio-card,frame-master = <&sound_master>;
+ simple-audio-card,bitclock-inversion;
+
+ simple-audio-card,cpu {
+ sound-dai = <&mcasp1>;
+ };
+
+ sound_master: simple-audio-card,codec {
+ sound-dai = <&tlv320aic3106>;
+ clocks = <&tlv320_mclk>;
+ };
+ };
+};
+
+&mcu_pmx0 {
+ wkup_uart0_pins_default: wkup-uart0-default-pins {
+ pinctrl-single,pins = <
+ AM62AX_MCU_IOPAD(0x0024, PIN_INPUT, 0) /* (C9) WKUP_UART0_RXD */
+ AM62AX_MCU_IOPAD(0x0028, PIN_OUTPUT, 0) /* (E9) WKUP_UART0_TXD */
+ AM62AX_MCU_IOPAD(0x002c, PIN_INPUT, 0) /* (C10) WKUP_UART0_CTSn */
+ AM62AX_MCU_IOPAD(0x0030, PIN_OUTPUT, 0) /* (C8) WKUP_UART0_RTSn */
+ >;
};
};
+/* WKUP UART0 is used for DM firmware logs */
+&wkup_uart0 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&wkup_uart0_pins_default>;
+ status = "reserved";
+};
+
&main_pmx0 {
- main_uart0_pins_default: main-uart0-pins-default {
+ main_uart0_pins_default: main-uart0-default-pins {
pinctrl-single,pins = <
- AM62AX_IOPAD(0x1c8, PIN_INPUT, 0) /* (D14) UART0_RXD */
- AM62AX_IOPAD(0x1cc, PIN_OUTPUT, 0) /* (E14) UART0_TXD */
+ AM62AX_IOPAD(0x1c8, PIN_INPUT, 0) /* (E14) UART0_RXD */
+ AM62AX_IOPAD(0x1cc, PIN_OUTPUT, 0) /* (D15) UART0_TXD */
>;
};
- main_i2c0_pins_default: main-i2c0-pins-default {
+ main_uart1_pins_default: main-uart1-default-pins {
+ pinctrl-single,pins = <
+ AM62AX_IOPAD(0x01e8, PIN_INPUT, 1) /* (C17) I2C1_SCL.UART1_RXD */
+ AM62AX_IOPAD(0x01ec, PIN_OUTPUT, 1) /* (E17) I2C1_SDA.UART1_TXD */
+ AM62AX_IOPAD(0x0194, PIN_INPUT, 2) /* (C19) MCASP0_AXR3.UART1_CTSn */
+ AM62AX_IOPAD(0x0198, PIN_OUTPUT, 2) /* (B19) MCASP0_AXR2.UART1_RTSn */
+ >;
+ };
+
+ main_i2c0_pins_default: main-i2c0-default-pins {
pinctrl-single,pins = <
AM62AX_IOPAD(0x1e0, PIN_INPUT_PULLUP, 0) /* (B16) I2C0_SCL */
AM62AX_IOPAD(0x1e4, PIN_INPUT_PULLUP, 0) /* (A16) I2C0_SDA */
>;
};
- main_i2c1_pins_default: main-i2c1-pins-default {
+ main_i2c1_pins_default: main-i2c1-default-pins {
pinctrl-single,pins = <
AM62AX_IOPAD(0x1e8, PIN_INPUT_PULLUP, 0) /* (B17) I2C1_SCL */
AM62AX_IOPAD(0x1ec, PIN_INPUT_PULLUP, 0) /* (A17) I2C1_SDA */
>;
};
- main_i2c2_pins_default: main-i2c2-pins-default {
+ main_i2c2_pins_default: main-i2c2-default-pins {
pinctrl-single,pins = <
AM62AX_IOPAD(0x0b0, PIN_INPUT_PULLUP, 1) /* (K22) GPMC0_CSn2.I2C2_SCL */
AM62AX_IOPAD(0x0b4, PIN_INPUT_PULLUP, 1) /* (K24) GPMC0_CSn3.I2C2_SDA */
>;
};
- main_mmc1_pins_default: main-mmc1-pins-default {
+ main_mmc1_pins_default: main-mmc1-default-pins {
pinctrl-single,pins = <
AM62AX_IOPAD(0x23c, PIN_INPUT, 0) /* (A21) MMC1_CMD */
AM62AX_IOPAD(0x234, PIN_INPUT, 0) /* (B22) MMC1_CLK */
@@ -155,25 +230,177 @@
>;
};
- usr_led_pins_default: usr-led-pins-default {
+ usr_led_pins_default: usr-led-default-pins {
pinctrl-single,pins = <
AM62AX_IOPAD(0x244, PIN_OUTPUT, 7) /* (D18) MMC1_SDWP.GPIO1_49 */
>;
};
+
+ main_usb1_pins_default: main-usb1-default-pins {
+ pinctrl-single,pins = <
+ AM62AX_IOPAD(0x0258, PIN_OUTPUT, 0) /* (F18) USB1_DRVVBUS */
+ >;
+ };
+
+ main_mdio1_pins_default: main-mdio1-default-pins {
+ pinctrl-single,pins = <
+ AM62AX_IOPAD(0x160, PIN_OUTPUT, 0) /* (V12) MDIO0_MDC */
+ AM62AX_IOPAD(0x15c, PIN_INPUT, 0) /* (V13) MDIO0_MDIO */
+ >;
+ };
+
+ main_rgmii1_pins_default: main-rgmii1-default-pins {
+ pinctrl-single,pins = <
+ AM62AX_IOPAD(0x14c, PIN_INPUT, 0) /* (AB16) RGMII1_RD0 */
+ AM62AX_IOPAD(0x150, PIN_INPUT, 0) /* (V15) RGMII1_RD1 */
+ AM62AX_IOPAD(0x154, PIN_INPUT, 0) /* (W15) RGMII1_RD2 */
+ AM62AX_IOPAD(0x158, PIN_INPUT, 0) /* (V14) RGMII1_RD3 */
+ AM62AX_IOPAD(0x148, PIN_INPUT, 0) /* (AA16) RGMII1_RXC */
+ AM62AX_IOPAD(0x144, PIN_INPUT, 0) /* (AA15) RGMII1_RX_CTL */
+ AM62AX_IOPAD(0x134, PIN_INPUT, 0) /* (Y17) RGMII1_TD0 */
+ AM62AX_IOPAD(0x138, PIN_INPUT, 0) /* (V16) RGMII1_TD1 */
+ AM62AX_IOPAD(0x13c, PIN_INPUT, 0) /* (Y16) RGMII1_TD2 */
+ AM62AX_IOPAD(0x140, PIN_INPUT, 0) /* (AA17) RGMII1_TD3 */
+ AM62AX_IOPAD(0x130, PIN_INPUT, 0) /* (AB17) RGMII1_TXC */
+ AM62AX_IOPAD(0x12c, PIN_INPUT, 0) /* (W16) RGMII1_TX_CTL */
+ >;
+ };
+
+ main_mcasp1_pins_default: main-mcasp1-default-pins {
+ pinctrl-single,pins = <
+ AM62AX_IOPAD(0x090, PIN_INPUT, 2) /* (L19) GPMC0_BE0n_CLE.MCASP1_ACLKX */
+ AM62AX_IOPAD(0x098, PIN_INPUT, 2) /* (R18) GPMC0_WAIT0.MCASP1_AFSX */
+ AM62AX_IOPAD(0x08c, PIN_OUTPUT, 2) /* (K19) GPMC0_WEn.MCASP1_AXR0 */
+ AM62AX_IOPAD(0x084, PIN_INPUT, 2) /* (L18) GPMC0_ADVn_ALE.MCASP1_AXR2 */
+ >;
+ };
};
+&mcu_pmx0 {
+ status = "okay";
+
+ pmic_irq_pins_default: pmic-irq-default-pins {
+ pinctrl-single,pins = <
+ AM62AX_MCU_IOPAD(0x000, PIN_INPUT, 7) /* (E11) MCU_GPIO0_0 */
+ >;
+ };
+};
+
+&mcu_gpio0 {
+ status = "okay";
+};
+
&main_i2c0 {
status = "okay";
pinctrl-names = "default";
pinctrl-0 = <&main_i2c0_pins_default>;
clock-frequency = <400000>;
+
+ typec_pd0: usb-power-controller@3f {
+ compatible = "ti,tps6598x";
+ reg = <0x3f>;
+
+ connector {
+ compatible = "usb-c-connector";
+ label = "USB-C";
+ self-powered;
+ data-role = "dual";
+ power-role = "sink";
+ port {
+ usb_con_hs: endpoint {
+ remote-endpoint = <&usb0_hs_ep>;
+ };
+ };
+ };
+ };
+
+ tps659312: pmic@48 {
+ compatible = "ti,tps6593-q1";
+ reg = <0x48>;
+ ti,primary-pmic;
+ system-power-controller;
+
+ gpio-controller;
+ #gpio-cells = <2>;
+
+ pinctrl-names = "default";
+ pinctrl-0 = <&pmic_irq_pins_default>;
+ interrupt-parent = <&mcu_gpio0>;
+ interrupts = <0 IRQ_TYPE_EDGE_FALLING>;
+
+ buck123-supply = <&vcc_3v3_sys>;
+ buck4-supply = <&vcc_3v3_sys>;
+ buck5-supply = <&vcc_3v3_sys>;
+ ldo1-supply = <&vcc_3v3_sys>;
+ ldo2-supply = <&vcc_3v3_sys>;
+ ldo3-supply = <&buck5>;
+ ldo4-supply = <&vcc_3v3_sys>;
+
+ regulators {
+ buck123: buck123 {
+ regulator-name = "vcc_core";
+ regulator-min-microvolt = <715000>;
+ regulator-max-microvolt = <895000>;
+ regulator-boot-on;
+ regulator-always-on;
+ };
+
+ buck4: buck4 {
+ regulator-name = "vcc_1v1";
+ regulator-min-microvolt = <1100000>;
+ regulator-max-microvolt = <1100000>;
+ regulator-boot-on;
+ regulator-always-on;
+ };
+
+ buck5: buck5 {
+ regulator-name = "vcc_1v8_sys";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-boot-on;
+ regulator-always-on;
+ };
+
+ ldo1: ldo1 {
+ regulator-name = "vddshv5_sdio";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-boot-on;
+ regulator-always-on;
+ };
+
+ ldo2: ldo2 {
+ regulator-name = "vpp_1v8";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-boot-on;
+ regulator-always-on;
+ };
+
+ ldo3: ldo3 {
+ regulator-name = "vcc_0v85";
+ regulator-min-microvolt = <850000>;
+ regulator-max-microvolt = <850000>;
+ regulator-boot-on;
+ regulator-always-on;
+ };
+
+ ldo4: ldo4 {
+ regulator-name = "vdda_1v8";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-boot-on;
+ regulator-always-on;
+ };
+ };
+ };
};
&main_i2c1 {
status = "okay";
pinctrl-names = "default";
pinctrl-0 = <&main_i2c1_pins_default>;
- clock-frequency = <400000>;
+ clock-frequency = <100000>;
exp1: gpio@22 {
compatible = "ti,tca6424";
@@ -194,6 +421,19 @@
"MCASP1_FET_SEL", "UART1_FET_SEL",
"PD_I2C_IRQ", "IO_EXP_TEST_LED";
};
+
+ tlv320aic3106: audio-codec@1b {
+ #sound-dai-cells = <0>;
+ compatible = "ti,tlv320aic3106";
+ reg = <0x1b>;
+ ai3x-micbias-vg = <1>; /* 2.0V */
+
+ /* Regulators */
+ AVDD-supply = <&vcc_3v3_sys>;
+ IOVDD-supply = <&vcc_3v3_sys>;
+ DRVDD-supply = <&vcc_3v3_sys>;
+ DVDD-supply = <&buck5>;
+ };
};
&sdhci1 {
@@ -223,3 +463,84 @@
pinctrl-names = "default";
pinctrl-0 = <&main_uart0_pins_default>;
};
+
+/* Main UART1 is used for TIFS firmware logs */
+&main_uart1 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&main_uart1_pins_default>;
+ status = "reserved";
+};
+
+&usbss0 {
+ status = "okay";
+ ti,vbus-divider;
+};
+
+&usb0 {
+ usb-role-switch;
+
+ port {
+ usb0_hs_ep: endpoint {
+ remote-endpoint = <&usb_con_hs>;
+ };
+ };
+};
+
+&usbss1 {
+ status = "okay";
+};
+
+&usb1 {
+ dr_mode = "host";
+ pinctrl-names = "default";
+ pinctrl-0 = <&main_usb1_pins_default>;
+};
+
+&cpsw3g {
+ status = "okay";
+ pinctrl-names = "default";
+ pinctrl-0 = <&main_rgmii1_pins_default>;
+};
+
+&cpsw_port1 {
+ status = "okay";
+ phy-mode = "rgmii-rxid";
+ phy-handle = <&cpsw3g_phy0>;
+};
+
+&cpsw_port2 {
+ status = "disabled";
+};
+
+&cpsw3g_mdio {
+ status = "okay";
+ pinctrl-names = "default";
+ pinctrl-0 = <&main_mdio1_pins_default>;
+
+ cpsw3g_phy0: ethernet-phy@0 {
+ reg = <0>;
+ ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_00_NS>;
+ ti,fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>;
+ ti,min-output-impedance;
+ };
+};
+
+&mcasp1 {
+ status = "okay";
+ #sound-dai-cells = <0>;
+
+ pinctrl-names = "default";
+ pinctrl-0 = <&main_mcasp1_pins_default>;
+
+ op-mode = <0>; /* MCASP_IIS_MODE */
+ tdm-slots = <2>;
+
+ serial-dir = < /* 0: INACTIVE, 1: TX, 2: RX */
+ 1 0 2 0
+ 0 0 0 0
+ 0 0 0 0
+ 0 0 0 0
+ >;
+ tx-num-evt = <32>;
+ rx-num-evt = <32>;
+};
diff --git a/arch/arm/dts/k3-am62a7.dtsi b/arch/arm/dts/k3-am62a7.dtsi
index 331d89f..58f1c43 100644
--- a/arch/arm/dts/k3-am62a7.dtsi
+++ b/arch/arm/dts/k3-am62a7.dtsi
@@ -95,8 +95,9 @@
L2_0: l2-cache0 {
compatible = "cache";
+ cache-unified;
cache-level = <2>;
- cache-size = <0x40000>;
+ cache-size = <0x80000>;
cache-line-size = <64>;
cache-sets = <512>;
};
diff --git a/arch/arm/dts/k3-am62x-sk-common.dtsi b/arch/arm/dts/k3-am62x-sk-common.dtsi
index 34c8ffc..19f57ea 100644
--- a/arch/arm/dts/k3-am62x-sk-common.dtsi
+++ b/arch/arm/dts/k3-am62x-sk-common.dtsi
@@ -28,6 +28,7 @@
};
memory@80000000 {
+ bootph-pre-ram;
device_type = "memory";
/* 2G RAM */
reg = <0x00000000 0x80000000 0x00000000 0x80000000>;
@@ -114,11 +115,23 @@
clocks = <&tlv320_mclk>;
};
};
+
+ hdmi0: connector-hdmi {
+ compatible = "hdmi-connector";
+ label = "hdmi";
+ type = "a";
+ port {
+ hdmi_connector_in: endpoint {
+ remote-endpoint = <&sii9022_out>;
+ };
+ };
+ };
};
&main_pmx0 {
/* First pad number is ALW package and second is AMC package */
main_uart0_pins_default: main-uart0-default-pins {
+ bootph-all;
pinctrl-single,pins = <
AM62X_IOPAD(0x1c8, PIN_INPUT, 0) /* (D14/A13) UART0_RXD */
AM62X_IOPAD(0x1cc, PIN_OUTPUT, 0) /* (E14/E11) UART0_TXD */
@@ -126,6 +139,7 @@
};
main_uart1_pins_default: main-uart1-default-pins {
+ bootph-pre-ram;
pinctrl-single,pins = <
AM62X_IOPAD(0x194, PIN_INPUT, 2) /* (B19/B18) MCASP0_AXR3.UART1_CTSn */
AM62X_IOPAD(0x198, PIN_OUTPUT, 2) /* (A19/B17) MCASP0_AXR2.UART1_RTSn */
@@ -156,6 +170,7 @@
};
main_mmc0_pins_default: main-mmc0-default-pins {
+ bootph-all;
pinctrl-single,pins = <
AM62X_IOPAD(0x220, PIN_INPUT, 0) /* (Y3/V3) MMC0_CMD */
AM62X_IOPAD(0x218, PIN_INPUT, 0) /* (AB1/Y1) MMC0_CLK */
@@ -171,6 +186,7 @@
};
main_mmc1_pins_default: main-mmc1-default-pins {
+ bootph-all;
pinctrl-single,pins = <
AM62X_IOPAD(0x23c, PIN_INPUT, 0) /* (A21/C18) MMC1_CMD */
AM62X_IOPAD(0x234, PIN_INPUT, 0) /* (B22/A20) MMC1_CLK */
@@ -196,6 +212,7 @@
};
main_rgmii1_pins_default: main-rgmii1-default-pins {
+ bootph-all;
pinctrl-single,pins = <
AM62X_IOPAD(0x14c, PIN_INPUT, 0) /* (AB17/W15) RGMII1_RD0 */
AM62X_IOPAD(0x150, PIN_INPUT, 0) /* (AC17/Y16) RGMII1_RD1 */
@@ -226,10 +243,44 @@
AM62X_IOPAD(0x084, PIN_INPUT, 2) /* (L23/K20) GPMC0_ADVN_ALE.MCASP1_AXR2 */
>;
};
+
+ main_dss0_pins_default: main-dss0-default-pins {
+ pinctrl-single,pins = <
+ AM62X_IOPAD(0x100, PIN_OUTPUT, 0) /* (AC25) VOUT0_VSYNC */
+ AM62X_IOPAD(0x0f8, PIN_OUTPUT, 0) /* (AB24) VOUT0_HSYNC */
+ AM62X_IOPAD(0x104, PIN_OUTPUT, 0) /* (AC24) VOUT0_PCLK */
+ AM62X_IOPAD(0x0fc, PIN_OUTPUT, 0) /* (Y20) VOUT0_DE */
+ AM62X_IOPAD(0x0b8, PIN_OUTPUT, 0) /* (U22) VOUT0_DATA0 */
+ AM62X_IOPAD(0x0bc, PIN_OUTPUT, 0) /* (V24) VOUT0_DATA1 */
+ AM62X_IOPAD(0x0c0, PIN_OUTPUT, 0) /* (W25) VOUT0_DATA2 */
+ AM62X_IOPAD(0x0c4, PIN_OUTPUT, 0) /* (W24) VOUT0_DATA3 */
+ AM62X_IOPAD(0x0c8, PIN_OUTPUT, 0) /* (Y25) VOUT0_DATA4 */
+ AM62X_IOPAD(0x0cc, PIN_OUTPUT, 0) /* (Y24) VOUT0_DATA5 */
+ AM62X_IOPAD(0x0d0, PIN_OUTPUT, 0) /* (Y23) VOUT0_DATA6 */
+ AM62X_IOPAD(0x0d4, PIN_OUTPUT, 0) /* (AA25) VOUT0_DATA7 */
+ AM62X_IOPAD(0x0d8, PIN_OUTPUT, 0) /* (V21) VOUT0_DATA8 */
+ AM62X_IOPAD(0x0dc, PIN_OUTPUT, 0) /* (W21) VOUT0_DATA9 */
+ AM62X_IOPAD(0x0e0, PIN_OUTPUT, 0) /* (V20) VOUT0_DATA10 */
+ AM62X_IOPAD(0x0e4, PIN_OUTPUT, 0) /* (AA23) VOUT0_DATA11 */
+ AM62X_IOPAD(0x0e8, PIN_OUTPUT, 0) /* (AB25) VOUT0_DATA12 */
+ AM62X_IOPAD(0x0ec, PIN_OUTPUT, 0) /* (AA24) VOUT0_DATA13 */
+ AM62X_IOPAD(0x0f0, PIN_OUTPUT, 0) /* (Y22) VOUT0_DATA14 */
+ AM62X_IOPAD(0x0f4, PIN_OUTPUT, 0) /* (AA21) VOUT0_DATA15 */
+ AM62X_IOPAD(0x05c, PIN_OUTPUT, 1) /* (R24) GPMC0_AD8.VOUT0_DATA16 */
+ AM62X_IOPAD(0x060, PIN_OUTPUT, 1) /* (R25) GPMC0_AD9.VOUT0_DATA17 */
+ AM62X_IOPAD(0x064, PIN_OUTPUT, 1) /* (T25) GPMC0_AD10.VOUT0_DATA18 */
+ AM62X_IOPAD(0x068, PIN_OUTPUT, 1) /* (R21) GPMC0_AD11.VOUT0_DATA19 */
+ AM62X_IOPAD(0x06c, PIN_OUTPUT, 1) /* (T22) GPMC0_AD12.VOUT0_DATA20 */
+ AM62X_IOPAD(0x070, PIN_OUTPUT, 1) /* (T24) GPMC0_AD13.VOUT0_DATA21 */
+ AM62X_IOPAD(0x074, PIN_OUTPUT, 1) /* (U25) GPMC0_AD14.VOUT0_DATA22 */
+ AM62X_IOPAD(0x078, PIN_OUTPUT, 1) /* (U24) GPMC0_AD15.VOUT0_DATA23 */
+ >;
+ };
};
&mcu_pmx0 {
wkup_uart0_pins_default: wkup-uart0-default-pins {
+ bootph-pre-ram;
pinctrl-single,pins = <
AM62X_MCU_IOPAD(0x02c, PIN_INPUT, 0) /* (C6/A7) WKUP_UART0_CTSn */
AM62X_MCU_IOPAD(0x030, PIN_OUTPUT, 0) /* (A4/B4) WKUP_UART0_RTSn */
@@ -241,12 +292,14 @@
&wkup_uart0 {
/* WKUP UART0 is used by DM firmware */
+ bootph-pre-ram;
status = "reserved";
pinctrl-names = "default";
pinctrl-0 = <&wkup_uart0_pins_default>;
};
&main_uart0 {
+ bootph-all;
status = "okay";
pinctrl-names = "default";
pinctrl-0 = <&main_uart0_pins_default>;
@@ -254,6 +307,7 @@
&main_uart1 {
/* Main UART1 is used by TIFS firmware */
+ bootph-pre-ram;
status = "reserved";
pinctrl-names = "default";
pinctrl-0 = <&main_uart1_pins_default>;
@@ -300,7 +354,7 @@
status = "okay";
pinctrl-names = "default";
pinctrl-0 = <&main_i2c1_pins_default>;
- clock-frequency = <400000>;
+ clock-frequency = <100000>;
tlv320aic3106: audio-codec@1b {
#sound-dai-cells = <0>;
@@ -313,9 +367,40 @@
IOVDD-supply = <&vcc_3v3_sys>;
DRVDD-supply = <&vcc_3v3_sys>;
};
+
+ sii9022: bridge-hdmi@3b {
+ compatible = "sil,sii9022";
+ reg = <0x3b>;
+ interrupt-parent = <&exp1>;
+ interrupts = <16 IRQ_TYPE_EDGE_FALLING>;
+ #sound-dai-cells = <0>;
+ sil,i2s-data-lanes = < 0 >;
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+
+ sii9022_in: endpoint {
+ remote-endpoint = <&dpi1_out>;
+ };
+ };
+
+ port@1 {
+ reg = <1>;
+
+ sii9022_out: endpoint {
+ remote-endpoint = <&hdmi_connector_in>;
+ };
+ };
+ };
+ };
};
&sdhci0 {
+ bootph-all;
status = "okay";
pinctrl-names = "default";
pinctrl-0 = <&main_mmc0_pins_default>;
@@ -325,6 +410,7 @@
&sdhci1 {
/* SD/MMC */
+ bootph-all;
status = "okay";
pinctrl-names = "default";
pinctrl-0 = <&main_mmc1_pins_default>;
@@ -333,21 +419,25 @@
};
&cpsw3g {
+ bootph-all;
pinctrl-names = "default";
pinctrl-0 = <&main_rgmii1_pins_default>;
};
&cpsw_port1 {
+ bootph-all;
phy-mode = "rgmii-rxid";
phy-handle = <&cpsw3g_phy0>;
};
&cpsw3g_mdio {
+ bootph-all;
status = "okay";
pinctrl-names = "default";
pinctrl-0 = <&main_mdio1_pins_default>;
cpsw3g_phy0: ethernet-phy@0 {
+ bootph-all;
reg = <0>;
ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_00_NS>;
ti,fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>;
@@ -410,3 +500,20 @@
tx-num-evt = <32>;
rx-num-evt = <32>;
};
+
+&dss {
+ status = "okay";
+ pinctrl-names = "default";
+ pinctrl-0 = <&main_dss0_pins_default>;
+};
+
+&dss_ports {
+ /* VP2: DPI Output */
+ port@1 {
+ reg = <1>;
+
+ dpi1_out: endpoint {
+ remote-endpoint = <&sii9022_in>;
+ };
+ };
+};
diff --git a/arch/arm/dts/k3-am642-evm-u-boot.dtsi b/arch/arm/dts/k3-am642-evm-u-boot.dtsi
index 953bbe9..b843078 100644
--- a/arch/arm/dts/k3-am642-evm-u-boot.dtsi
+++ b/arch/arm/dts/k3-am642-evm-u-boot.dtsi
@@ -116,7 +116,30 @@
bootph-all;
};
+&main_bcdma {
+ reg = <0x00 0x485c0100 0x00 0x100>,
+ <0x00 0x4c000000 0x00 0x20000>,
+ <0x00 0x4a820000 0x00 0x20000>,
+ <0x00 0x4aa40000 0x00 0x20000>,
+ <0x00 0x4bc00000 0x00 0x100000>,
+ <0x00 0x48600000 0x00 0x8000>,
+ <0x00 0x484a4000 0x00 0x2000>,
+ <0x00 0x484c2000 0x00 0x2000>;
+ reg-names = "gcfg", "bchanrt", "rchanrt", "tchanrt", "ringrt",
+ "cfg", "tchan", "rchan";
+};
+
&main_pktdma {
+ reg = <0x00 0x485c0000 0x00 0x100>,
+ <0x00 0x4a800000 0x00 0x20000>,
+ <0x00 0x4aa00000 0x00 0x40000>,
+ <0x00 0x4b800000 0x00 0x400000>,
+ <0x00 0x485e0000 0x00 0x20000>,
+ <0x00 0x484a0000 0x00 0x4000>,
+ <0x00 0x484c0000 0x00 0x2000>,
+ <0x00 0x48430000 0x00 0x4000>;
+ reg-names = "gcfg", "rchanrt", "tchanrt", "ringrt", "cfg",
+ "tchan", "rchan", "rflow";
bootph-all;
};
diff --git a/arch/arm/dts/k3-am642-sk-u-boot.dtsi b/arch/arm/dts/k3-am642-sk-u-boot.dtsi
index 40a53df..2eb227c 100644
--- a/arch/arm/dts/k3-am642-sk-u-boot.dtsi
+++ b/arch/arm/dts/k3-am642-sk-u-boot.dtsi
@@ -96,10 +96,6 @@
bootph-all;
};
-&main_pktdma {
- bootph-all;
-};
-
&mdio1_pins_default {
bootph-all;
};
@@ -141,10 +137,30 @@
};
&main_bcdma {
+ reg = <0x00 0x485c0100 0x00 0x100>,
+ <0x00 0x4c000000 0x00 0x20000>,
+ <0x00 0x4a820000 0x00 0x20000>,
+ <0x00 0x4aa40000 0x00 0x20000>,
+ <0x00 0x4bc00000 0x00 0x100000>,
+ <0x00 0x48600000 0x00 0x8000>,
+ <0x00 0x484a4000 0x00 0x2000>,
+ <0x00 0x484c2000 0x00 0x2000>;
+ reg-names = "gcfg", "bchanrt", "rchanrt", "tchanrt", "ringrt",
+ "cfg", "tchan", "rchan";
bootph-all;
};
&main_pktdma {
+ reg = <0x00 0x485c0000 0x00 0x100>,
+ <0x00 0x4a800000 0x00 0x20000>,
+ <0x00 0x4aa00000 0x00 0x40000>,
+ <0x00 0x4b800000 0x00 0x400000>,
+ <0x00 0x485e0000 0x00 0x20000>,
+ <0x00 0x484a0000 0x00 0x4000>,
+ <0x00 0x484c0000 0x00 0x2000>,
+ <0x00 0x48430000 0x00 0x4000>;
+ reg-names = "gcfg", "rchanrt", "tchanrt", "ringrt", "cfg",
+ "tchan", "rchan", "rflow";
bootph-all;
};
diff --git a/arch/arm/dts/k3-am64x-binman.dtsi b/arch/arm/dts/k3-am64x-binman.dtsi
index a5e5400..88df214 100644
--- a/arch/arm/dts/k3-am64x-binman.dtsi
+++ b/arch/arm/dts/k3-am64x-binman.dtsi
@@ -118,87 +118,27 @@
#ifdef CONFIG_TARGET_AM642_A53_EVM
-#define SPL_NODTB "spl/u-boot-spl-nodtb.bin"
#define SPL_AM642_EVM_DTB "spl/dts/k3-am642-evm.dtb"
#define SPL_AM642_SK_DTB "spl/dts/k3-am642-sk.dtb"
-#define UBOOT_NODTB "u-boot-nodtb.bin"
#define AM642_EVM_DTB "u-boot.dtb"
#define AM642_SK_DTB "arch/arm/dts/k3-am642-sk.dtb"
&binman {
ti-spl {
- filename = "tispl.bin";
- pad-byte = <0xff>;
+ insert-template = <&ti_spl_template>;
fit {
description = "Configuration to load ATF and SPL";
#address-cells = <1>;
images {
-
- atf {
- description = "ARM Trusted Firmware";
- type = "firmware";
- arch = "arm64";
- compression = "none";
- os = "arm-trusted-firmware";
- load = <CONFIG_K3_ATF_LOAD_ADDR>;
- entry = <CONFIG_K3_ATF_LOAD_ADDR>;
- ti-secure {
- content = <&atf>;
- keyfile = "custMpk.pem";
- };
- atf: atf-bl31 {
- };
- };
-
- tee {
- description = "OP-TEE";
- type = "tee";
- arch = "arm64";
- compression = "none";
- os = "tee";
- load = <0x9e800000>;
- entry = <0x9e800000>;
- ti-secure {
- content = <&tee>;
- keyfile = "custMpk.pem";
- };
- tee: tee-os {
- };
- };
-
dm {
- description = "DM binary";
- type = "firmware";
- arch = "arm32";
- compression = "none";
- os = "DM";
- load = <0x89000000>;
- entry = <0x89000000>;
blob-ext {
filename = "/dev/null";
};
};
- spl {
- description = "SPL (64-bit)";
- type = "standalone";
- os = "U-Boot";
- arch = "arm64";
- compression = "none";
- load = <CONFIG_SPL_TEXT_BASE>;
- entry = <CONFIG_SPL_TEXT_BASE>;
- ti-secure {
- content = <&u_boot_spl_nodtb>;
- keyfile = "custMpk.pem";
-
- };
- u_boot_spl_nodtb: blob-ext {
- filename = SPL_NODTB;
- };
- };
fdt-0 {
description = "k3-am642-evm";
@@ -254,29 +194,12 @@
&binman {
u-boot {
- filename = "u-boot.img";
- pad-byte = <0xff>;
+ insert-template = <&u_boot_template>;
fit {
- description = "FIT image with multiple configurations";
-
images {
uboot {
- description = "U-Boot for AM64 board";
- type = "firmware";
- os = "u-boot";
- arch = "arm";
- compression = "none";
- load = <CONFIG_TEXT_BASE>;
- ti-secure {
- content = <&u_boot_nodtb>;
- keyfile = "custMpk.pem";
- };
- u_boot_nodtb: u-boot-nodtb {
- };
- hash {
- algo = "crc32";
- };
+ description = "U-Boot for AM64 Board";
};
fdt-0 {
@@ -340,65 +263,17 @@
&binman {
ti-spl_unsigned {
- filename = "tispl.bin_unsigned";
- pad-byte = <0xff>;
+ insert-template = <&ti_spl_unsigned_template>;
fit {
- description = "Configuration to load ATF and SPL";
- #address-cells = <1>;
-
images {
- atf {
- description = "ARM Trusted Firmware";
- type = "firmware";
- arch = "arm64";
- compression = "none";
- os = "arm-trusted-firmware";
- load = <CONFIG_K3_ATF_LOAD_ADDR>;
- entry = <CONFIG_K3_ATF_LOAD_ADDR>;
- atf-bl31 {
- };
- };
-
- tee {
- description = "OP-TEE";
- type = "tee";
- arch = "arm64";
- compression = "none";
- os = "tee";
- load = <0x9e800000>;
- entry = <0x9e800000>;
- tee-os {
- };
- };
-
dm {
- description = "DM binary";
- type = "firmware";
- arch = "arm32";
- compression = "none";
- os = "DM";
- load = <0x89000000>;
- entry = <0x89000000>;
blob-ext {
filename = "/dev/null";
};
};
- spl {
- description = "SPL (64-bit)";
- type = "standalone";
- os = "U-Boot";
- arch = "arm64";
- compression = "none";
- load = <CONFIG_SPL_TEXT_BASE>;
- entry = <CONFIG_SPL_TEXT_BASE>;
- blob {
- filename = "spl/u-boot-spl-nodtb.bin";
- };
- };
-
fdt-0 {
description = "k3-am642-evm";
type = "flat_dt";
@@ -443,26 +318,12 @@
&binman {
u-boot_unsigned {
- filename = "u-boot.img_unsigned";
- pad-byte = <0xff>;
+ insert-template = <&u_boot_unsigned_template>;
fit {
- description = "FIT image with multiple configurations";
-
images {
uboot {
- description = "U-Boot for AM64 board";
- type = "firmware";
- os = "u-boot";
- arch = "arm";
- compression = "none";
- load = <CONFIG_TEXT_BASE>;
- blob {
- filename = UBOOT_NODTB;
- };
- hash {
- algo = "crc32";
- };
+ description = "U-Boot for AM64 Board";
};
fdt-0 {
diff --git a/arch/arm/dts/k3-am654-base-board-ddr4-1600MTs.dtsi b/arch/arm/dts/k3-am654-base-board-ddr4-1600MTs.dtsi
index 5638321..cfea21b 100644
--- a/arch/arm/dts/k3-am654-base-board-ddr4-1600MTs.dtsi
+++ b/arch/arm/dts/k3-am654-base-board-ddr4-1600MTs.dtsi
@@ -1,8 +1,8 @@
// SPDX-License-Identifier: GPL-2.0+
/*
- * Copyright (C) 2020 Texas Instruments Incorporated - http://www.ti.com/
+ * Copyright (C) 2020 Texas Instruments Incorporated - https://www.ti.com/
* This file was generated by AM65x_DRA80xM_EMIF_Tool_2.02.xlsm
- * http://www.ti.com/lit/pdf/spracj0
+ * https://www.ti.com/lit/pdf/spracj0
* Configuration Parameters
* Memory Type: DDR4
* Data Rate: 1600 MT/s
diff --git a/arch/arm/dts/k3-am654-base-board-u-boot.dtsi b/arch/arm/dts/k3-am654-base-board-u-boot.dtsi
index e4cbc47..11d8392 100644
--- a/arch/arm/dts/k3-am654-base-board-u-boot.dtsi
+++ b/arch/arm/dts/k3-am654-base-board-u-boot.dtsi
@@ -1,6 +1,6 @@
// SPDX-License-Identifier: GPL-2.0
/*
- * Copyright (C) 2018-2021 Texas Instruments Incorporated - http://www.ti.com/
+ * Copyright (C) 2018-2021 Texas Instruments Incorporated - https://www.ti.com/
*/
#include "k3-am654-r5-base-board-u-boot.dtsi"
diff --git a/arch/arm/dts/k3-am654-ddr.dtsi b/arch/arm/dts/k3-am654-ddr.dtsi
index 48698cd..9f0586e 100644
--- a/arch/arm/dts/k3-am654-ddr.dtsi
+++ b/arch/arm/dts/k3-am654-ddr.dtsi
@@ -1,6 +1,6 @@
// SPDX-License-Identifier: GPL-2.0+
/*
- * Copyright (C) 2018 Texas Instruments Incorporated - http://www.ti.com/
+ * Copyright (C) 2018 Texas Instruments Incorporated - https://www.ti.com/
*/
/ {
diff --git a/arch/arm/dts/k3-am654-r5-base-board-u-boot.dtsi b/arch/arm/dts/k3-am654-r5-base-board-u-boot.dtsi
index 949320c..2866045 100644
--- a/arch/arm/dts/k3-am654-r5-base-board-u-boot.dtsi
+++ b/arch/arm/dts/k3-am654-r5-base-board-u-boot.dtsi
@@ -1,6 +1,6 @@
// SPDX-License-Identifier: GPL-2.0
/*
- * Copyright (C) 2018-2021 Texas Instruments Incorporated - http://www.ti.com/
+ * Copyright (C) 2018-2021 Texas Instruments Incorporated - https://www.ti.com/
*/
#include <dt-bindings/pinctrl/k3.h>
diff --git a/arch/arm/dts/k3-am654-r5-base-board.dts b/arch/arm/dts/k3-am654-r5-base-board.dts
index 7671875..637a5cc 100644
--- a/arch/arm/dts/k3-am654-r5-base-board.dts
+++ b/arch/arm/dts/k3-am654-r5-base-board.dts
@@ -1,6 +1,6 @@
// SPDX-License-Identifier: GPL-2.0
/*
- * Copyright (C) 2016-2018 Texas Instruments Incorporated - http://www.ti.com/
+ * Copyright (C) 2016-2018 Texas Instruments Incorporated - https://www.ti.com/
*/
/dts-v1/;
diff --git a/arch/arm/dts/k3-am65x-binman.dtsi b/arch/arm/dts/k3-am65x-binman.dtsi
index 59605ca..8cc24da 100644
--- a/arch/arm/dts/k3-am65x-binman.dtsi
+++ b/arch/arm/dts/k3-am65x-binman.dtsi
@@ -42,77 +42,7 @@
};
itb {
filename = "sysfw-am65x_sr2-hs-evm.itb";
- fit {
- description = "SYSFW and Config fragments";
- #address-cells = <1>;
- images {
- sysfw.bin {
- description = "sysfw";
- type = "firmware";
- arch = "arm";
- compression = "none";
- blob-ext {
- filename = "sysfw.bin";
- };
- };
- board-cfg.bin {
- description = "board-cfg";
- type = "firmware";
- arch = "arm";
- compression = "none";
- ti-secure {
- content = <&board_cfg>;
- keyfile = "custMpk.pem";
- };
- board_cfg: board-cfg {
- filename = "board-cfg.bin";
- type = "blob-ext";
- };
- };
- pm-cfg.bin {
- description = "pm-cfg";
- type = "firmware";
- arch = "arm";
- compression = "none";
- ti-secure {
- content = <&pm_cfg>;
- keyfile = "custMpk.pem";
- };
- pm_cfg: pm-cfg {
- filename = "pm-cfg.bin";
- type = "blob-ext";
- };
- };
- rm-cfg.bin {
- description = "rm-cfg";
- type = "firmware";
- arch = "arm";
- compression = "none";
- ti-secure {
- content = <&rm_cfg>;
- keyfile = "custMpk.pem";\
- };
- rm_cfg: rm-cfg {
- filename = "rm-cfg.bin";
- type = "blob-ext";
- };
- };
- sec-cfg.bin {
- description = "sec-cfg";
- type = "firmware";
- arch = "arm";
- compression = "none";
- ti-secure {
- content = <&sec_cfg>;
- keyfile = "custMpk.pem";
- };
- sec_cfg: sec-cfg {
- filename = "sec-cfg.bin";
- type = "blob-ext";
- };
- };
- };
- };
+ insert-template = <&itb_template>;
};
};
@@ -149,55 +79,14 @@
itb_gp {
filename = "sysfw-am65x_sr2-gp-evm.itb";
symlink = "sysfw.itb";
+ insert-template = <&itb_unsigned_template>;
fit {
- description = "SYSFW and Config fragments";
- #address-cells = <1>;
images {
sysfw.bin {
- description = "sysfw";
- type = "firmware";
- arch = "arm";
- compression = "none";
blob-ext {
filename = "sysfw.bin_gp";
};
};
- board-cfg.bin {
- description = "board-cfg";
- type = "firmware";
- arch = "arm";
- compression = "none";
- blob-ext {
- filename = "board-cfg.bin";
- };
- };
- pm-cfg.bin {
- description = "pm-cfg";
- type = "firmware";
- arch = "arm";
- compression = "none";
- blob-ext {
- filename = "pm-cfg.bin";
- };
- };
- rm-cfg.bin {
- description = "rm-cfg";
- type = "firmware";
- arch = "arm";
- compression = "none";
- blob-ext {
- filename = "rm-cfg.bin";
- };
- };
- sec-cfg.bin {
- description = "sec-cfg";
- type = "firmware";
- arch = "arm";
- compression = "none";
- blob-ext {
- filename = "sec-cfg.bin";
- };
- };
};
};
};
@@ -206,86 +95,22 @@
#ifdef CONFIG_TARGET_AM654_A53_EVM
-#define SPL_NODTB "spl/u-boot-spl-nodtb.bin"
#define SPL_AM654_EVM_DTB "spl/dts/k3-am654-base-board.dtb"
-
-#define UBOOT_NODTB "u-boot-nodtb.bin"
#define AM654_EVM_DTB "u-boot.dtb"
&binman {
ti-spl {
- filename = "tispl.bin";
- pad-byte = <0xff>;
+ insert-template = <&ti_spl_template>;
fit {
- description = "Configuration to load ATF and SPL";
- #address-cells = <1>;
-
images {
- atf {
- description = "ARM Trusted Firmware";
- type = "firmware";
- arch = "arm64";
- compression = "none";
- os = "arm-trusted-firmware";
- load = <CONFIG_K3_ATF_LOAD_ADDR>;
- entry = <CONFIG_K3_ATF_LOAD_ADDR>;
- ti-secure {
- content = <&atf>;
- keyfile = "custMpk.pem";
- };
- atf: atf-bl31 {
- };
- };
-
- tee {
- description = "OP-TEE";
- type = "tee";
- arch = "arm64";
- compression = "none";
- os = "tee";
- load = <0x9e800000>;
- entry = <0x9e800000>;
- ti-secure {
- content = <&tee>;
- keyfile = "custMpk.pem";
- };
- tee: tee-os {
- };
- };
-
dm {
- description = "DM binary";
- type = "firmware";
- arch = "arm32";
- compression = "none";
- os = "DM";
- load = <0x89000000>;
- entry = <0x89000000>;
blob-ext {
filename = "/dev/null";
};
};
- spl {
- description = "SPL (64-bit)";
- type = "standalone";
- os = "U-Boot";
- arch = "arm64";
- compression = "none";
- load = <CONFIG_SPL_TEXT_BASE>;
- entry = <CONFIG_SPL_TEXT_BASE>;
- ti-secure {
- content = <&u_boot_spl_nodtb>;
- keyfile = "custMpk.pem";
-
- };
- u_boot_spl_nodtb: blob-ext {
- filename = SPL_NODTB;
- };
- };
-
fdt-0 {
description = "k3-am654-base-board";
type = "flat_dt";
@@ -317,29 +142,12 @@
&binman {
u-boot {
- filename = "u-boot.img";
- pad-byte = <0xff>;
+ insert-template = <&u_boot_template>;
fit {
- description = "FIT image with multiple configurations";
-
images {
uboot {
- description = "U-Boot for AM65 board";
- type = "firmware";
- os = "u-boot";
- arch = "arm";
- compression = "none";
- load = <CONFIG_TEXT_BASE>;
- ti-secure {
- content = <&u_boot_nodtb>;
- keyfile = "custMpk.pem";
- };
- u_boot_nodtb: u-boot-nodtb {
- };
- hash {
- algo = "crc32";
- };
+ description = "U-Boot for AM65 Board";
};
fdt-0 {
@@ -378,67 +186,16 @@
&binman {
ti-spl_unsigned {
- filename = "tispl.bin_unsigned";
- pad-byte = <0xff>;
+ insert-template = <&ti_spl_unsigned_template>;
fit {
- description = "Configuration to load ATF and SPL";
- #address-cells = <1>;
-
images {
-
- atf {
- description = "ARM Trusted Firmware";
- type = "firmware";
- arch = "arm64";
- compression = "none";
- os = "arm-trusted-firmware";
- load = <CONFIG_K3_ATF_LOAD_ADDR>;
- entry = <CONFIG_K3_ATF_LOAD_ADDR>;
- atf-bl31 {
- filename = "bl31.bin";
- };
- };
-
- tee {
- description = "OP-TEE";
- type = "tee";
- arch = "arm64";
- compression = "none";
- os = "tee";
- load = <0x9e800000>;
- entry = <0x9e800000>;
- tee-os {
- filename = "tee-raw.bin";
- };
- };
-
dm {
- description = "DM binary";
- type = "firmware";
- arch = "arm32";
- compression = "none";
- os = "DM";
- load = <0x89000000>;
- entry = <0x89000000>;
blob-ext {
filename = "/dev/null";
};
};
- spl {
- description = "SPL (64-bit)";
- type = "standalone";
- os = "U-Boot";
- arch = "arm64";
- compression = "none";
- load = <CONFIG_SPL_TEXT_BASE>;
- entry = <CONFIG_SPL_TEXT_BASE>;
- blob-ext {
- filename = SPL_NODTB;
- };
- };
-
fdt-0 {
description = "k3-j721e-common-proc-board";
type = "flat_dt";
@@ -466,26 +223,12 @@
&binman {
u-boot_unsigned {
- filename = "u-boot.img_unsigned";
- pad-byte = <0xff>;
+ insert-template = <&u_boot_unsigned_template>;
fit {
- description = "FIT image with multiple configurations";
-
images {
uboot {
- description = "U-Boot for AM65 board";
- type = "firmware";
- os = "u-boot";
- arch = "arm";
- compression = "none";
- load = <CONFIG_TEXT_BASE>;
- blob {
- filename = UBOOT_NODTB;
- };
- hash {
- algo = "crc32";
- };
+ description = "U-Boot for AM65 Board";
};
fdt-0 {
diff --git a/arch/arm/dts/k3-am68-sk-base-board.dts b/arch/arm/dts/k3-am68-sk-base-board.dts
index 5df5946..1e1a82f 100644
--- a/arch/arm/dts/k3-am68-sk-base-board.dts
+++ b/arch/arm/dts/k3-am68-sk-base-board.dts
@@ -553,3 +553,59 @@
};
};
};
+
+&serdes_ln_ctrl {
+ idle-states = <J721S2_SERDES0_LANE0_PCIE1_LANE0>, <J721S2_SERDES0_LANE1_PCIE1_LANE1>,
+ <J721S2_SERDES0_LANE2_USB_SWAP>, <J721S2_SERDES0_LANE3_USB>;
+};
+
+&serdes_refclk {
+ clock-frequency = <100000000>;
+};
+
+&serdes0 {
+ status = "okay";
+
+ serdes0_pcie_link: phy@0 {
+ reg = <0>;
+ cdns,num-lanes = <2>;
+ #phy-cells = <0>;
+ cdns,phy-type = <PHY_TYPE_PCIE>;
+ resets = <&serdes_wiz0 1>, <&serdes_wiz0 2>;
+ };
+
+ serdes0_usb_link: phy@2 {
+ status = "okay";
+ reg = <2>;
+ cdns,num-lanes = <1>;
+ #phy-cells = <0>;
+ cdns,phy-type = <PHY_TYPE_USB3>;
+ resets = <&serdes_wiz0 3>;
+ };
+};
+
+&pcie1_rc {
+ status = "okay";
+ reset-gpios = <&exp1 10 GPIO_ACTIVE_HIGH>;
+ phys = <&serdes0_pcie_link>;
+ phy-names = "pcie-phy";
+ num-lanes = <2>;
+};
+
+&usb_serdes_mux {
+ idle-states = <0>; /* USB0 to SERDES lane 2 */
+};
+
+&usbss0 {
+ status = "okay";
+ pinctrl-0 = <&main_usbss0_pins_default>;
+ pinctrl-names = "default";
+ ti,vbus-divider;
+};
+
+&usb0 {
+ dr_mode = "host";
+ maximum-speed = "super-speed";
+ phys = <&serdes0_usb_link>;
+ phy-names = "cdns3,usb3-phy";
+};
diff --git a/arch/arm/dts/k3-am68-sk-som.dtsi b/arch/arm/dts/k3-am68-sk-som.dtsi
index 6c9139f..20861a0 100644
--- a/arch/arm/dts/k3-am68-sk-som.dtsi
+++ b/arch/arm/dts/k3-am68-sk-som.dtsi
@@ -25,6 +25,108 @@
reg = <0x00 0x9e800000 0x00 0x01800000>;
no-map;
};
+
+ mcu_r5fss0_core0_dma_memory_region: r5f-dma-memory@a0000000 {
+ compatible = "shared-dma-pool";
+ reg = <0x00 0xa0000000 0x00 0x100000>;
+ no-map;
+ };
+
+ mcu_r5fss0_core0_memory_region: r5f-memory@a0100000 {
+ compatible = "shared-dma-pool";
+ reg = <0x00 0xa0100000 0x00 0xf00000>;
+ no-map;
+ };
+
+ mcu_r5fss0_core1_dma_memory_region: r5f-dma-memory@a1000000 {
+ compatible = "shared-dma-pool";
+ reg = <0x00 0xa1000000 0x00 0x100000>;
+ no-map;
+ };
+
+ mcu_r5fss0_core1_memory_region: r5f-memory@a1100000 {
+ compatible = "shared-dma-pool";
+ reg = <0x00 0xa1100000 0x00 0xf00000>;
+ no-map;
+ };
+
+ main_r5fss0_core0_dma_memory_region: r5f-dma-memory@a2000000 {
+ compatible = "shared-dma-pool";
+ reg = <0x00 0xa2000000 0x00 0x100000>;
+ no-map;
+ };
+
+ main_r5fss0_core0_memory_region: r5f-memory@a2100000 {
+ compatible = "shared-dma-pool";
+ reg = <0x00 0xa2100000 0x00 0xf00000>;
+ no-map;
+ };
+
+ main_r5fss0_core1_dma_memory_region: r5f-dma-memory@a3000000 {
+ compatible = "shared-dma-pool";
+ reg = <0x00 0xa3000000 0x00 0x100000>;
+ no-map;
+ };
+
+ main_r5fss0_core1_memory_region: r5f-memory@a3100000 {
+ compatible = "shared-dma-pool";
+ reg = <0x00 0xa3100000 0x00 0xf00000>;
+ no-map;
+ };
+
+ main_r5fss1_core0_dma_memory_region: r5f-dma-memory@a4000000 {
+ compatible = "shared-dma-pool";
+ reg = <0x00 0xa4000000 0x00 0x100000>;
+ no-map;
+ };
+
+ main_r5fss1_core0_memory_region: r5f-memory@a4100000 {
+ compatible = "shared-dma-pool";
+ reg = <0x00 0xa4100000 0x00 0xf00000>;
+ no-map;
+ };
+
+ main_r5fss1_core1_dma_memory_region: r5f-dma-memory@a5000000 {
+ compatible = "shared-dma-pool";
+ reg = <0x00 0xa5000000 0x00 0x100000>;
+ no-map;
+ };
+
+ main_r5fss1_core1_memory_region: r5f-memory@a5100000 {
+ compatible = "shared-dma-pool";
+ reg = <0x00 0xa5100000 0x00 0xf00000>;
+ no-map;
+ };
+
+ c71_0_dma_memory_region: c71-dma-memory@a6000000 {
+ compatible = "shared-dma-pool";
+ reg = <0x00 0xa6000000 0x00 0x100000>;
+ no-map;
+ };
+
+ c71_0_memory_region: c71-memory@a6100000 {
+ compatible = "shared-dma-pool";
+ reg = <0x00 0xa6100000 0x00 0xf00000>;
+ no-map;
+ };
+
+ c71_1_dma_memory_region: c71-dma-memory@a7000000 {
+ compatible = "shared-dma-pool";
+ reg = <0x00 0xa7000000 0x00 0x100000>;
+ no-map;
+ };
+
+ c71_1_memory_region: c71-memory@a7100000 {
+ compatible = "shared-dma-pool";
+ reg = <0x00 0xa7100000 0x00 0xf00000>;
+ no-map;
+ };
+
+ rtos_ipc_memory_region: ipc-memories@a8000000 {
+ reg = <0x00 0xa8000000 0x00 0x01c00000>;
+ alignment = <0x1000>;
+ no-map;
+ };
};
};
@@ -49,3 +151,109 @@
reg = <0x51>;
};
};
+
+&mailbox0_cluster0 {
+ status = "okay";
+ interrupts = <436>;
+ mbox_mcu_r5fss0_core0: mbox-mcu-r5fss0-core0 {
+ ti,mbox-rx = <0 0 0>;
+ ti,mbox-tx = <1 0 0>;
+ };
+
+ mbox_mcu_r5fss0_core1: mbox-mcu-r5fss0-core1 {
+ ti,mbox-rx = <2 0 0>;
+ ti,mbox-tx = <3 0 0>;
+ };
+};
+
+&mailbox0_cluster1 {
+ status = "okay";
+ interrupts = <432>;
+ mbox_main_r5fss0_core0: mbox-main-r5fss0-core0 {
+ ti,mbox-rx = <0 0 0>;
+ ti,mbox-tx = <1 0 0>;
+ };
+
+ mbox_main_r5fss0_core1: mbox-main-r5fss0-core1 {
+ ti,mbox-rx = <2 0 0>;
+ ti,mbox-tx = <3 0 0>;
+ };
+};
+
+&mailbox0_cluster2 {
+ status = "okay";
+ interrupts = <428>;
+ mbox_main_r5fss1_core0: mbox-main-r5fss1-core0 {
+ ti,mbox-rx = <0 0 0>;
+ ti,mbox-tx = <1 0 0>;
+ };
+
+ mbox_main_r5fss1_core1: mbox-main-r5fss1-core1 {
+ ti,mbox-rx = <2 0 0>;
+ ti,mbox-tx = <3 0 0>;
+ };
+};
+
+&mailbox0_cluster4 {
+ status = "okay";
+ interrupts = <420>;
+ mbox_c71_0: mbox-c71-0 {
+ ti,mbox-rx = <0 0 0>;
+ ti,mbox-tx = <1 0 0>;
+ };
+
+ mbox_c71_1: mbox-c71-1 {
+ ti,mbox-rx = <2 0 0>;
+ ti,mbox-tx = <3 0 0>;
+ };
+};
+
+&mcu_r5fss0_core0 {
+ mboxes = <&mailbox0_cluster0>, <&mbox_mcu_r5fss0_core0>;
+ memory-region = <&mcu_r5fss0_core0_dma_memory_region>,
+ <&mcu_r5fss0_core0_memory_region>;
+};
+
+&mcu_r5fss0_core1 {
+ mboxes = <&mailbox0_cluster0>, <&mbox_mcu_r5fss0_core1>;
+ memory-region = <&mcu_r5fss0_core1_dma_memory_region>,
+ <&mcu_r5fss0_core1_memory_region>;
+};
+
+&main_r5fss0_core0 {
+ mboxes = <&mailbox0_cluster1>, <&mbox_main_r5fss0_core0>;
+ memory-region = <&main_r5fss0_core0_dma_memory_region>,
+ <&main_r5fss0_core0_memory_region>;
+};
+
+&main_r5fss0_core1 {
+ mboxes = <&mailbox0_cluster1>, <&mbox_main_r5fss0_core1>;
+ memory-region = <&main_r5fss0_core1_dma_memory_region>,
+ <&main_r5fss0_core1_memory_region>;
+};
+
+&main_r5fss1_core0 {
+ mboxes = <&mailbox0_cluster2>, <&mbox_main_r5fss1_core0>;
+ memory-region = <&main_r5fss1_core0_dma_memory_region>,
+ <&main_r5fss1_core0_memory_region>;
+};
+
+&main_r5fss1_core1 {
+ mboxes = <&mailbox0_cluster2>, <&mbox_main_r5fss1_core1>;
+ memory-region = <&main_r5fss1_core1_dma_memory_region>,
+ <&main_r5fss1_core1_memory_region>;
+};
+
+&c71_0 {
+ status = "okay";
+ mboxes = <&mailbox0_cluster4>, <&mbox_c71_0>;
+ memory-region = <&c71_0_dma_memory_region>,
+ <&c71_0_memory_region>;
+};
+
+&c71_1 {
+ status = "okay";
+ mboxes = <&mailbox0_cluster4>, <&mbox_c71_1>;
+ memory-region = <&c71_1_dma_memory_region>,
+ <&c71_1_memory_region>;
+};
diff --git a/arch/arm/dts/k3-binman.dtsi b/arch/arm/dts/k3-binman.dtsi
index 2ea2dd1..c7513e1 100644
--- a/arch/arm/dts/k3-binman.dtsi
+++ b/arch/arm/dts/k3-binman.dtsi
@@ -13,14 +13,14 @@
custMpk {
filename = "custMpk.pem";
custmpk_pem: blob-ext {
- filename = "../keys/custMpk.pem";
+ filename = "arch/arm/mach-k3/keys/custMpk.pem";
};
};
ti-degenerate-key {
filename = "ti-degenerate-key.pem";
dkey_pem: blob-ext {
- filename = "../keys/ti-degenerate-key.pem";
+ filename = "arch/arm/mach-k3/keys/ti-degenerate-key.pem";
};
};
};
@@ -32,28 +32,28 @@
filename = "board-cfg.bin";
bcfg_yaml: ti-board-config {
config = "board-cfg.yaml";
- schema = "../common/schema.yaml";
+ schema = "board/ti/common/schema.yaml";
};
};
pm-cfg {
filename = "pm-cfg.bin";
pcfg_yaml: ti-board-config {
config = "pm-cfg.yaml";
- schema = "../common/schema.yaml";
+ schema = "board/ti/common/schema.yaml";
};
};
rm-cfg {
filename = "rm-cfg.bin";
rcfg_yaml: ti-board-config {
config = "rm-cfg.yaml";
- schema = "../common/schema.yaml";
+ schema = "board/ti/common/schema.yaml";
};
};
sec-cfg {
filename = "sec-cfg.bin";
scfg_yaml: ti-board-config {
config = "sec-cfg.yaml";
- schema = "../common/schema.yaml";
+ schema = "board/ti/common/schema.yaml";
};
};
combined-tifs-cfg {
@@ -61,19 +61,19 @@
ti-board-config {
bcfg_yaml_tifs: board-cfg {
config = "board-cfg.yaml";
- schema = "../common/schema.yaml";
+ schema = "board/ti/common/schema.yaml";
};
scfg_yaml_tifs: sec-cfg {
config = "sec-cfg.yaml";
- schema = "../common/schema.yaml";
+ schema = "board/ti/common/schema.yaml";
};
pcfg_yaml_tifs: pm-cfg {
config = "pm-cfg.yaml";
- schema = "../common/schema.yaml";
+ schema = "board/ti/common/schema.yaml";
};
rcfg_yaml_tifs: rm-cfg {
config = "rm-cfg.yaml";
- schema = "../common/schema.yaml";
+ schema = "board/ti/common/schema.yaml";
};
};
};
@@ -82,11 +82,11 @@
ti-board-config {
pcfg_yaml_dm: pm-cfg {
config = "pm-cfg.yaml";
- schema = "../common/schema.yaml";
+ schema = "board/ti/common/schema.yaml";
};
rcfg_yaml_dm: rm-cfg {
config = "rm-cfg.yaml";
- schema = "../common/schema.yaml";
+ schema = "board/ti/common/schema.yaml";
};
};
};
@@ -95,22 +95,349 @@
ti-board-config {
bcfg_yaml_sysfw: board-cfg {
config = "board-cfg.yaml";
- schema = "../common/schema.yaml";
+ schema = "board/ti/common/schema.yaml";
};
scfg_yaml_sysfw: sec-cfg {
config = "sec-cfg.yaml";
- schema = "../common/schema.yaml";
+ schema = "board/ti/common/schema.yaml";
};
pcfg_yaml_sysfw: pm-cfg {
config = "pm-cfg.yaml";
- schema = "../common/schema.yaml";
+ schema = "board/ti/common/schema.yaml";
};
rcfg_yaml_sysfw: rm-cfg {
config = "rm-cfg.yaml";
- schema = "../common/schema.yaml";
+ schema = "board/ti/common/schema.yaml";
};
};
};
};
+&binman {
+ itb_template: template-5 {
+ fit {
+ description = "SYSFW and Config fragments";
+ #address-cells = <1>;
+ images {
+ sysfw.bin {
+ description = "sysfw";
+ type = "firmware";
+ arch = "arm";
+ compression = "none";
+ blob-ext {
+ filename = "sysfw.bin";
+ };
+ };
+ board-cfg.bin {
+ description = "board-cfg";
+ type = "firmware";
+ arch = "arm";
+ compression = "none";
+ ti-secure {
+ content = <&board_cfg>;
+ keyfile = "custMpk.pem";
+ };
+ board_cfg: board-cfg {
+ filename = "board-cfg.bin";
+ type = "blob-ext";
+ };
+
+ };
+ pm-cfg.bin {
+ description = "pm-cfg";
+ type = "firmware";
+ arch = "arm";
+ compression = "none";
+ ti-secure {
+ content = <&pm_cfg>;
+ keyfile = "custMpk.pem";
+ };
+ pm_cfg: pm-cfg {
+ filename = "pm-cfg.bin";
+ type = "blob-ext";
+ };
+ };
+ rm-cfg.bin {
+ description = "rm-cfg";
+ type = "firmware";
+ arch = "arm";
+ compression = "none";
+ ti-secure {
+ content = <&rm_cfg>;
+ keyfile = "custMpk.pem";
+ };
+ rm_cfg: rm-cfg {
+ filename = "rm-cfg.bin";
+ type = "blob-ext";
+ };
+ };
+ sec-cfg.bin {
+ description = "sec-cfg";
+ type = "firmware";
+ arch = "arm";
+ compression = "none";
+ ti-secure {
+ content = <&sec_cfg>;
+ keyfile = "custMpk.pem";
+ };
+ sec_cfg: sec-cfg {
+ filename = "sec-cfg.bin";
+ type = "blob-ext";
+ };
+ };
+ };
+ };
+ };
+
+ itb_unsigned_template: template-6 {
+ fit {
+ description = "SYSFW and Config fragments";
+ #address-cells = <1>;
+ images {
+ sysfw.bin {
+ description = "sysfw";
+ type = "firmware";
+ arch = "arm";
+ compression = "none";
+ blob-ext {
+ filename = "sysfw.bin_fs";
+ };
+ };
+ board-cfg.bin {
+ description = "board-cfg";
+ type = "firmware";
+ arch = "arm";
+ compression = "none";
+ board-cfg {
+ filename = "board-cfg.bin";
+ type = "blob-ext";
+ };
+
+ };
+ pm-cfg.bin {
+ description = "pm-cfg";
+ type = "firmware";
+ arch = "arm";
+ compression = "none";
+ pm-cfg {
+ filename = "pm-cfg.bin";
+ type = "blob-ext";
+ };
+ };
+ rm-cfg.bin {
+ description = "rm-cfg";
+ type = "firmware";
+ arch = "arm";
+ compression = "none";
+ rm-cfg {
+ filename = "rm-cfg.bin";
+ type = "blob-ext";
+ };
+ };
+ sec-cfg.bin {
+ description = "sec-cfg";
+ type = "firmware";
+ arch = "arm";
+ compression = "none";
+ sec-cfg {
+ filename = "sec-cfg.bin";
+ type = "blob-ext";
+ };
+ };
+ };
+ };
+ };
+};
+
+#else
+
+&binman {
+ ti_spl_template: template-1 {
+ filename = "tispl.bin";
+ pad-byte = <0xff>;
+
+ fit {
+ description = "Configuration to load ATF and SPL";
+ #address-cells = <1>;
+
+ images {
+
+ atf {
+ description = "ARM Trusted Firmware";
+ type = "firmware";
+ arch = "arm64";
+ compression = "none";
+ os = "arm-trusted-firmware";
+ load = <CONFIG_K3_ATF_LOAD_ADDR>;
+ entry = <CONFIG_K3_ATF_LOAD_ADDR>;
+ ti-secure {
+ content = <&atf>;
+ keyfile = "custMpk.pem";
+ };
+ atf: atf-bl31 {
+ };
+ };
+
+ tee {
+ description = "OP-TEE";
+ type = "tee";
+ arch = "arm64";
+ compression = "none";
+ os = "tee";
+ load = <0x9e800000>;
+ entry = <0x9e800000>;
+ ti-secure {
+ content = <&tee>;
+ keyfile = "custMpk.pem";
+ };
+ tee: tee-os {
+ };
+ };
+
+ dm {
+ description = "DM binary";
+ type = "firmware";
+ arch = "arm32";
+ compression = "none";
+ os = "DM";
+ load = <0x89000000>;
+ entry = <0x89000000>;
+ };
+
+ spl {
+ description = "SPL (64-bit)";
+ type = "standalone";
+ os = "U-Boot";
+ arch = "arm64";
+ compression = "none";
+ load = <CONFIG_SPL_TEXT_BASE>;
+ entry = <CONFIG_SPL_TEXT_BASE>;
+ ti-secure {
+ content = <&u_boot_spl_nodtb>;
+ keyfile = "custMpk.pem";
+
+ };
+ u_boot_spl_nodtb: blob-ext {
+ filename = "spl/u-boot-spl-nodtb.bin";
+ };
+ };
+
+ };
+ };
+ };
+ ti_spl_unsigned_template: template-2 {
+ filename = "tispl.bin_unsigned";
+ pad-byte = <0xff>;
+
+ fit {
+ description = "Configuration to load ATF and SPL";
+ #address-cells = <1>;
+
+ images {
+
+ atf {
+ description = "ARM Trusted Firmware";
+ type = "firmware";
+ arch = "arm64";
+ compression = "none";
+ os = "arm-trusted-firmware";
+ load = <CONFIG_K3_ATF_LOAD_ADDR>;
+ entry = <CONFIG_K3_ATF_LOAD_ADDR>;
+ atf-bl31 {
+ filename = "bl31.bin";
+ };
+ };
+
+ tee {
+ description = "OP-TEE";
+ type = "tee";
+ arch = "arm64";
+ compression = "none";
+ os = "tee";
+ load = <0x9e800000>;
+ entry = <0x9e800000>;
+ tee-os {
+ filename = "tee-raw.bin";
+ };
+ };
+
+ dm {
+ description = "DM binary";
+ type = "firmware";
+ arch = "arm32";
+ compression = "none";
+ os = "DM";
+ load = <0x89000000>;
+ entry = <0x89000000>;
+ };
+
+ spl {
+ description = "SPL (64-bit)";
+ type = "standalone";
+ os = "U-Boot";
+ arch = "arm64";
+ compression = "none";
+ load = <CONFIG_SPL_TEXT_BASE>;
+ entry = <CONFIG_SPL_TEXT_BASE>;
+ blob-ext {
+ filename = "spl/u-boot-spl-nodtb.bin";
+ };
+ };
+ };
+ };
+ };
+ u_boot_template: template-3 {
+ filename = "u-boot.img";
+ pad-byte = <0xff>;
+
+ fit {
+ description = "FIT image with multiple configurations";
+
+ images {
+ uboot {
+ type = "firmware";
+ os = "u-boot";
+ arch = "arm";
+ compression = "none";
+ load = <CONFIG_TEXT_BASE>;
+ ti-secure {
+ content = <&u_boot_nodtb>;
+ keyfile = "custMpk.pem";
+ };
+ u_boot_nodtb: u-boot-nodtb {
+ };
+ hash {
+ algo = "crc32";
+ };
+ };
+ };
+ };
+ };
+ u_boot_unsigned_template: template-4 {
+ filename = "u-boot.img_unsigned";
+ pad-byte = <0xff>;
+
+ fit {
+ description = "FIT image with multiple configurations";
+
+ images {
+ uboot {
+ type = "firmware";
+ os = "u-boot";
+ arch = "arm";
+ compression = "none";
+ load = <CONFIG_TEXT_BASE>;
+ blob {
+ filename = "u-boot-nodtb.bin";
+ };
+ hash {
+ algo = "crc32";
+ };
+ };
+ };
+ };
+ };
+
+};
+
#endif
diff --git a/arch/arm/dts/k3-j7200-binman.dtsi b/arch/arm/dts/k3-j7200-binman.dtsi
index 14f7dea..10c9d6c 100644
--- a/arch/arm/dts/k3-j7200-binman.dtsi
+++ b/arch/arm/dts/k3-j7200-binman.dtsi
@@ -180,10 +180,7 @@
#ifdef CONFIG_TARGET_J7200_A72_EVM
-#define SPL_NODTB "spl/u-boot-spl-nodtb.bin"
#define SPL_J7200_EVM_DTB "spl/dts/k3-j7200-common-proc-board.dtb"
-
-#define UBOOT_NODTB "u-boot-nodtb.bin"
#define J7200_EVM_DTB "u-boot.dtb"
&binman {
@@ -194,82 +191,20 @@
};
};
ti-spl {
- filename = "tispl.bin";
- pad-byte = <0xff>;
+ insert-template = <&ti_spl_template>;
fit {
- description = "Configuration to load ATF and SPL";
- #address-cells = <1>;
-
images {
-
- atf {
- description = "ARM Trusted Firmware";
- type = "firmware";
- arch = "arm64";
- compression = "none";
- os = "arm-trusted-firmware";
- load = <CONFIG_K3_ATF_LOAD_ADDR>;
- entry = <CONFIG_K3_ATF_LOAD_ADDR>;
- ti-secure {
- content = <&atf>;
- keyfile = "custMpk.pem";
- };
- atf: atf-bl31 {
- };
- };
-
- tee {
- description = "OP-TEE";
- type = "tee";
- arch = "arm64";
- compression = "none";
- os = "tee";
- load = <0x9e800000>;
- entry = <0x9e800000>;
- ti-secure {
- content = <&tee>;
- keyfile = "custMpk.pem";
- };
- tee: tee-os {
- };
- };
-
dm {
- description = "DM binary";
- type = "firmware";
- arch = "arm32";
- compression = "none";
- os = "DM";
- load = <0x89000000>;
- entry = <0x89000000>;
ti-secure {
content = <&dm>;
keyfile = "custMpk.pem";
};
-
dm: blob-ext {
filename = "ti-dm.bin";
};
};
- spl {
- description = "SPL (64-bit)";
- type = "standalone";
- os = "U-Boot";
- arch = "arm64";
- compression = "none";
- load = <CONFIG_SPL_TEXT_BASE>;
- entry = <CONFIG_SPL_TEXT_BASE>;
- ti-secure {
- content = <&u_boot_spl_nodtb>;
- keyfile = "custMpk.pem";
- };
- u_boot_spl_nodtb: blob-ext {
- filename = SPL_NODTB;
- };
- };
-
fdt-0 {
description = "k3-j7200-common-proc-board";
type = "flat_dt";
@@ -302,29 +237,12 @@
&binman {
u-boot {
- filename = "u-boot.img";
- pad-byte = <0xff>;
+ insert-template = <&u_boot_template>;
fit {
- description = "FIT image with multiple configurations";
-
images {
uboot {
- description = "U-Boot for J7200 board";
- type = "firmware";
- os = "u-boot";
- arch = "arm";
- compression = "none";
- load = <CONFIG_TEXT_BASE>;
- ti-secure {
- content = <&u_boot_nodtb>;
- keyfile = "custMpk.pem";
- };
- u_boot_nodtb: u-boot-nodtb {
- };
- hash {
- algo = "crc32";
- };
+ description = "U-Boot for J7200 Board";
};
fdt-0 {
@@ -362,67 +280,16 @@
&binman {
ti-spl_unsigned {
- filename = "tispl.bin_unsigned";
- pad-byte = <0xff>;
+ insert-template = <&ti_spl_unsigned_template>;
fit {
- description = "Configuration to load ATF and SPL";
- #address-cells = <1>;
-
images {
-
- atf {
- description = "ARM Trusted Firmware";
- type = "firmware";
- arch = "arm64";
- compression = "none";
- os = "arm-trusted-firmware";
- load = <CONFIG_K3_ATF_LOAD_ADDR>;
- entry = <CONFIG_K3_ATF_LOAD_ADDR>;
- atf-bl31 {
- filename = "bl31.bin";
- };
- };
-
- tee {
- description = "OP-TEE";
- type = "tee";
- arch = "arm64";
- compression = "none";
- os = "tee";
- load = <0x9e800000>;
- entry = <0x9e800000>;
- tee-os {
- filename = "tee-raw.bin";
- };
- };
-
dm {
- description = "DM binary";
- type = "firmware";
- arch = "arm32";
- compression = "none";
- os = "DM";
- load = <0x89000000>;
- entry = <0x89000000>;
blob-ext {
filename = "ti-dm.bin";
};
};
- spl {
- description = "SPL (64-bit)";
- type = "standalone";
- os = "U-Boot";
- arch = "arm64";
- compression = "none";
- load = <CONFIG_SPL_TEXT_BASE>;
- entry = <CONFIG_SPL_TEXT_BASE>;
- blob {
- filename = SPL_NODTB;
- };
- };
-
fdt-1 {
description = "k3-j7200-common-proc-board";
type = "flat_dt";
@@ -450,26 +317,12 @@
&binman {
u-boot_unsigned {
- filename = "u-boot.img_unsigned";
- pad-byte = <0xff>;
+ insert-template = <&u_boot_unsigned_template>;
fit {
- description = "FIT image with multiple configurations";
-
images {
uboot {
- description = "U-Boot for J7200 board";
- type = "firmware";
- os = "u-boot";
- arch = "arm";
- compression = "none";
- load = <CONFIG_TEXT_BASE>;
- blob {
- filename = UBOOT_NODTB;
- };
- hash {
- algo = "crc32";
- };
+ description = "U-Boot for J7200 Board";
};
fdt-1 {
diff --git a/arch/arm/dts/k3-j7200-ddr-evm-lp4-2666.dtsi b/arch/arm/dts/k3-j7200-ddr-evm-lp4-2666.dtsi
index 9ec8dff..f068308 100644
--- a/arch/arm/dts/k3-j7200-ddr-evm-lp4-2666.dtsi
+++ b/arch/arm/dts/k3-j7200-ddr-evm-lp4-2666.dtsi
@@ -1,6 +1,6 @@
// SPDX-License-Identifier: GPL-2.0+
/*
- * Copyright (C) 2019 Texas Instruments Incorporated - http://www.ti.com/
+ * Copyright (C) 2019 Texas Instruments Incorporated - https://www.ti.com/
* This file was generated by the Jacinto7_DDRSS_RegConfigTool, Revision: 0.6.0
* This file was generated on 06/01/2021
*/
diff --git a/arch/arm/dts/k3-j7200-main.dtsi b/arch/arm/dts/k3-j7200-main.dtsi
index cdb1d6b..264913f 100644
--- a/arch/arm/dts/k3-j7200-main.dtsi
+++ b/arch/arm/dts/k3-j7200-main.dtsi
@@ -91,7 +91,7 @@
};
main_navss: bus@30000000 {
- compatible = "simple-mfd";
+ compatible = "simple-bus";
#address-cells = <2>;
#size-cells = <2>;
ranges = <0x00 0x30000000 0x00 0x30000000 0x00 0x0c400000>;
diff --git a/arch/arm/dts/k3-j7200-mcu-wakeup.dtsi b/arch/arm/dts/k3-j7200-mcu-wakeup.dtsi
index 6ffaf85..3fc588b 100644
--- a/arch/arm/dts/k3-j7200-mcu-wakeup.dtsi
+++ b/arch/arm/dts/k3-j7200-mcu-wakeup.dtsi
@@ -318,7 +318,7 @@
};
mcu_navss: bus@28380000 {
- compatible = "simple-mfd";
+ compatible = "simple-bus";
#address-cells = <2>;
#size-cells = <2>;
ranges = <0x00 0x28380000 0x00 0x28380000 0x00 0x03880000>;
@@ -637,4 +637,11 @@
power-domains = <&k3_pds 154 TI_SCI_PD_EXCLUSIVE>;
#thermal-sensor-cells = <1>;
};
+
+ mcu_esm: esm@40800000 {
+ compatible = "ti,j721e-esm";
+ reg = <0x00 0x40800000 0x00 0x1000>;
+ ti,esm-pins = <95>;
+ bootph-pre-ram;
+ };
};
diff --git a/arch/arm/dts/k3-j721e-beagleboneai64-u-boot.dtsi b/arch/arm/dts/k3-j721e-beagleboneai64-u-boot.dtsi
new file mode 100644
index 0000000..f83caf7
--- /dev/null
+++ b/arch/arm/dts/k3-j721e-beagleboneai64-u-boot.dtsi
@@ -0,0 +1,358 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * https://beagleboard.org/ai-64
+ *
+ * Copyright (C) 2022-2023 Texas Instruments Incorporated - https://www.ti.com/
+ * Copyright (C) 2022 Jason Kridner, BeagleBoard.org Foundation
+ * Copyright (C) 2022-2023 Robert Nelson, BeagleBoard.org Foundation
+ */
+
+#include "k3-binman.dtsi"
+
+/ {
+ memory@80000000 {
+ bootph-all;
+ };
+
+ /* Keep the LEDs on by default to indicate life */
+ leds {
+ bootph-all;
+ led-0 {
+ default-state = "on";
+ bootph-all;
+ };
+
+ led-1 {
+ default-state = "on";
+ bootph-all;
+ };
+
+ led-2 {
+ default-state = "on";
+ bootph-all;
+ };
+
+ led-3 {
+ default-state = "on";
+ bootph-all;
+ };
+
+ led-4 {
+ default-state = "on";
+ bootph-all;
+ };
+ };
+};
+
+&cbass_main {
+ bootph-all;
+};
+
+&main_navss {
+ bootph-all;
+};
+
+&cbass_mcu_wakeup {
+ bootph-all;
+
+ chipid@43000014 {
+ bootph-all;
+ };
+};
+
+&mcu_navss {
+ bootph-all;
+};
+
+&mcu_ringacc {
+ reg = <0x0 0x2b800000 0x0 0x400000>,
+ <0x0 0x2b000000 0x0 0x400000>,
+ <0x0 0x28590000 0x0 0x100>,
+ <0x0 0x2a500000 0x0 0x40000>,
+ <0x0 0x28440000 0x0 0x40000>;
+ reg-names = "rt", "fifos", "proxy_gcfg", "proxy_target", "cfg";
+ bootph-all;
+};
+
+&mcu_udmap {
+ reg = <0x0 0x285c0000 0x0 0x100>,
+ <0x0 0x284c0000 0x0 0x4000>,
+ <0x0 0x2a800000 0x0 0x40000>,
+ <0x0 0x284a0000 0x0 0x4000>,
+ <0x0 0x2aa00000 0x0 0x40000>,
+ <0x0 0x28400000 0x0 0x2000>;
+ reg-names = "gcfg", "rchan", "rchanrt", "tchan",
+ "tchanrt", "rflow";
+ bootph-all;
+};
+
+&secure_proxy_main {
+ bootph-all;
+};
+
+&dmsc {
+ bootph-all;
+ k3_sysreset: sysreset-controller {
+ compatible = "ti,sci-sysreset";
+ bootph-all;
+ };
+};
+
+&k3_pds {
+ bootph-all;
+};
+
+&k3_clks {
+ bootph-all;
+};
+
+&k3_reset {
+ bootph-all;
+};
+
+&wkup_pmx0 {
+ bootph-all;
+};
+
+&main_pmx0 {
+ bootph-all;
+};
+
+&main_uart0 {
+ bootph-all;
+};
+
+&main_gpio0 {
+ bootph-all;
+};
+
+&main_uart0_pins_default {
+ bootph-all;
+};
+
+&main_sdhci0 {
+ bootph-all;
+};
+
+&main_sdhci1 {
+ bootph-all;
+ sdhci-caps-mask = <0x00000007 0x00000000>;
+ /delete-property/ cd-gpios;
+ /delete-property/ cd-debounce-delay-ms;
+ /delete-property/ ti,fails-without-test-cd;
+ /delete-property/ no-1-8-v;
+};
+
+&main_mmc1_pins_default {
+ bootph-all;
+};
+
+&mcu_cpsw {
+ bootph-all;
+};
+
+&davinci_mdio {
+ bootph-all;
+};
+
+&phy0 {
+ bootph-all;
+};
+
+&serdes2 {
+ bootph-all;
+};
+
+&serdes_ln_ctrl {
+ bootph-all;
+};
+
+&serdes2_usb_link {
+ bootph-all;
+};
+
+&usb_serdes_mux {
+ bootph-all;
+};
+
+&serdes_wiz2 {
+ bootph-all;
+};
+
+&main_usbss1_pins_default {
+ bootph-all;
+};
+
+&mcu_usbss1_pins_default {
+ bootph-all;
+};
+
+&usbss1 {
+ bootph-all;
+};
+
+&usb1 {
+ bootph-all;
+};
+
+&wkup_i2c0_pins_default {
+ bootph-all;
+};
+
+&wkup_i2c0 {
+ bootph-all;
+};
+
+#ifdef CONFIG_TARGET_J721E_A72_BEAGLEBONEAI64
+
+#define SPL_NODTB "spl/u-boot-spl-nodtb.bin"
+#define SPL_J721E_BBAI64_DTB "spl/dts/k3-j721e-beagleboneai64.dtb"
+
+#define UBOOT_NODTB "u-boot-nodtb.bin"
+#define J721E_BBAI64_DTB "arch/arm/dts/k3-j721e-beagleboneai64.dtb"
+
+&binman {
+ ti-dm {
+ filename = "ti-dm.bin";
+ blob-ext {
+ filename = "ti-dm/j721e/ipc_echo_testb_mcu1_0_release_strip.xer5f";
+ };
+ };
+
+ ti-spl_unsigned {
+ filename = "tispl.bin_unsigned";
+ pad-byte = <0xff>;
+
+ fit {
+ description = "Configuration to load ATF and SPL";
+ #address-cells = <1>;
+
+ images {
+
+ atf {
+ description = "ARM Trusted Firmware";
+ type = "firmware";
+ arch = "arm64";
+ compression = "none";
+ os = "arm-trusted-firmware";
+ load = <CONFIG_K3_ATF_LOAD_ADDR>;
+ entry = <CONFIG_K3_ATF_LOAD_ADDR>;
+ atf-bl31 {
+ filename = "bl31.bin";
+ };
+ };
+
+ tee {
+ description = "OP-TEE";
+ type = "tee";
+ arch = "arm64";
+ compression = "none";
+ os = "tee";
+ load = <0x9e800000>;
+ entry = <0x9e800000>;
+ tee-os {
+ filename = "tee-raw.bin";
+ };
+ };
+
+ dm {
+ description = "DM binary";
+ type = "firmware";
+ arch = "arm32";
+ compression = "none";
+ os = "DM";
+ load = <0x89000000>;
+ entry = <0x89000000>;
+ blob-ext {
+ filename = "ti-dm.bin";
+ };
+ };
+
+ spl {
+ description = "SPL (64-bit)";
+ type = "standalone";
+ os = "U-Boot";
+ arch = "arm64";
+ compression = "none";
+ load = <CONFIG_SPL_TEXT_BASE>;
+ entry = <CONFIG_SPL_TEXT_BASE>;
+ blob-ext {
+ filename = SPL_NODTB;
+ };
+ };
+
+ fdt-0 {
+ description = "k3-j721e-beagleboneai64";
+ type = "flat_dt";
+ arch = "arm";
+ compression = "none";
+ blob {
+ filename = SPL_J721E_BBAI64_DTB;
+ };
+ };
+ };
+
+ configurations {
+ default = "conf-0";
+
+ conf-0 {
+ description = "k3-j721e-beagleboneai64";
+ firmware = "atf";
+ loadables = "tee", "dm", "spl";
+ fdt = "fdt-0";
+ };
+ };
+ };
+ };
+
+ u-boot_unsigned {
+ filename = "u-boot.img_unsigned";
+ pad-byte = <0xff>;
+
+ fit {
+ description = "FIT image with multiple configurations";
+
+ images {
+ uboot {
+ description = "U-Boot for j721e board";
+ type = "firmware";
+ os = "u-boot";
+ arch = "arm";
+ compression = "none";
+ load = <CONFIG_TEXT_BASE>;
+ blob {
+ filename = UBOOT_NODTB;
+ };
+ hash {
+ algo = "crc32";
+ };
+ };
+
+ fdt-0 {
+ description = "k3-j721e-beagleboneai64";
+ type = "flat_dt";
+ arch = "arm";
+ compression = "none";
+ blob {
+ filename = J721E_BBAI64_DTB;
+ };
+ hash {
+ algo = "crc32";
+ };
+ };
+ };
+
+ configurations {
+ default = "conf-0";
+
+ conf-0 {
+ description = "k3-j721e-beagleboneai64";
+ firmware = "uboot";
+ loadables = "uboot";
+ fdt = "fdt-0";
+ };
+ };
+ };
+ };
+};
+#endif
diff --git a/arch/arm/dts/k3-j721e-beagleboneai64.dts b/arch/arm/dts/k3-j721e-beagleboneai64.dts
new file mode 100644
index 0000000..2f95472
--- /dev/null
+++ b/arch/arm/dts/k3-j721e-beagleboneai64.dts
@@ -0,0 +1,993 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * https://beagleboard.org/ai-64
+ * Copyright (C) 2022 Texas Instruments Incorporated - https://www.ti.com/
+ * Copyright (C) 2022 Jason Kridner, BeagleBoard.org Foundation
+ * Copyright (C) 2022 Robert Nelson, BeagleBoard.org Foundation
+ */
+
+/dts-v1/;
+
+#include "k3-j721e.dtsi"
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/input/input.h>
+#include <dt-bindings/leds/common.h>
+#include <dt-bindings/net/ti-dp83867.h>
+#include <dt-bindings/phy/phy-cadence.h>
+
+/ {
+ compatible = "beagle,j721e-beagleboneai64", "ti,j721e";
+ model = "BeagleBoard.org BeagleBone AI-64";
+
+ aliases {
+ serial0 = &wkup_uart0;
+ serial2 = &main_uart0;
+ mmc0 = &main_sdhci0;
+ mmc1 = &main_sdhci1;
+ i2c0 = &wkup_i2c0;
+ i2c1 = &main_i2c6;
+ i2c2 = &main_i2c2;
+ i2c3 = &main_i2c4;
+ };
+
+ chosen {
+ stdout-path = "serial2:115200n8";
+ };
+
+ memory@80000000 {
+ device_type = "memory";
+ /* 4G RAM */
+ reg = <0x00000000 0x80000000 0x00000000 0x80000000>,
+ <0x00000008 0x80000000 0x00000000 0x80000000>;
+ };
+
+ reserved_memory: reserved-memory {
+ #address-cells = <2>;
+ #size-cells = <2>;
+ ranges;
+
+ secure_ddr: optee@9e800000 {
+ reg = <0x00 0x9e800000 0x00 0x01800000>;
+ no-map;
+ };
+
+ mcu_r5fss0_core0_dma_memory_region: r5f-dma-memory@a0000000 {
+ compatible = "shared-dma-pool";
+ reg = <0x00 0xa0000000 0x00 0x100000>;
+ no-map;
+ };
+
+ mcu_r5fss0_core0_memory_region: r5f-memory@a0100000 {
+ compatible = "shared-dma-pool";
+ reg = <0x00 0xa0100000 0x00 0xf00000>;
+ no-map;
+ };
+
+ mcu_r5fss0_core1_dma_memory_region: r5f-dma-memory@a1000000 {
+ compatible = "shared-dma-pool";
+ reg = <0x00 0xa1000000 0x00 0x100000>;
+ no-map;
+ };
+
+ mcu_r5fss0_core1_memory_region: r5f-memory@a1100000 {
+ compatible = "shared-dma-pool";
+ reg = <0x00 0xa1100000 0x00 0xf00000>;
+ no-map;
+ };
+
+ main_r5fss0_core0_dma_memory_region: r5f-dma-memory@a2000000 {
+ compatible = "shared-dma-pool";
+ reg = <0x00 0xa2000000 0x00 0x100000>;
+ no-map;
+ };
+
+ main_r5fss0_core0_memory_region: r5f-memory@a2100000 {
+ compatible = "shared-dma-pool";
+ reg = <0x00 0xa2100000 0x00 0xf00000>;
+ no-map;
+ };
+
+ main_r5fss0_core1_dma_memory_region: r5f-dma-memory@a3000000 {
+ compatible = "shared-dma-pool";
+ reg = <0x00 0xa3000000 0x00 0x100000>;
+ no-map;
+ };
+
+ main_r5fss0_core1_memory_region: r5f-memory@a3100000 {
+ compatible = "shared-dma-pool";
+ reg = <0x00 0xa3100000 0x00 0xf00000>;
+ no-map;
+ };
+
+ main_r5fss1_core0_dma_memory_region: r5f-dma-memory@a4000000 {
+ compatible = "shared-dma-pool";
+ reg = <0x00 0xa4000000 0x00 0x100000>;
+ no-map;
+ };
+
+ main_r5fss1_core0_memory_region: r5f-memory@a4100000 {
+ compatible = "shared-dma-pool";
+ reg = <0x00 0xa4100000 0x00 0xf00000>;
+ no-map;
+ };
+
+ main_r5fss1_core1_dma_memory_region: r5f-dma-memory@a5000000 {
+ compatible = "shared-dma-pool";
+ reg = <0x00 0xa5000000 0x00 0x100000>;
+ no-map;
+ };
+
+ main_r5fss1_core1_memory_region: r5f-memory@a5100000 {
+ compatible = "shared-dma-pool";
+ reg = <0x00 0xa5100000 0x00 0xf00000>;
+ no-map;
+ };
+
+ c66_1_dma_memory_region: c66-dma-memory@a6000000 {
+ compatible = "shared-dma-pool";
+ reg = <0x00 0xa6000000 0x00 0x100000>;
+ no-map;
+ };
+
+ c66_0_memory_region: c66-memory@a6100000 {
+ compatible = "shared-dma-pool";
+ reg = <0x00 0xa6100000 0x00 0xf00000>;
+ no-map;
+ };
+
+ c66_0_dma_memory_region: c66-dma-memory@a7000000 {
+ compatible = "shared-dma-pool";
+ reg = <0x00 0xa7000000 0x00 0x100000>;
+ no-map;
+ };
+
+ c66_1_memory_region: c66-memory@a7100000 {
+ compatible = "shared-dma-pool";
+ reg = <0x00 0xa7100000 0x00 0xf00000>;
+ no-map;
+ };
+
+ c71_0_dma_memory_region: c71-dma-memory@a8000000 {
+ compatible = "shared-dma-pool";
+ reg = <0x00 0xa8000000 0x00 0x100000>;
+ no-map;
+ };
+
+ c71_0_memory_region: c71-memory@a8100000 {
+ compatible = "shared-dma-pool";
+ reg = <0x00 0xa8100000 0x00 0xf00000>;
+ no-map;
+ };
+
+ rtos_ipc_memory_region: ipc-memories@aa000000 {
+ reg = <0x00 0xaa000000 0x00 0x01c00000>;
+ alignment = <0x1000>;
+ no-map;
+ };
+ };
+
+ gpio_keys: gpio-keys {
+ compatible = "gpio-keys";
+ pinctrl-names = "default";
+ pinctrl-0 = <&sw_pwr_pins_default>;
+
+ button-1 {
+ label = "BOOT";
+ linux,code = <BTN_0>;
+ gpios = <&wkup_gpio0 0 GPIO_ACTIVE_LOW>;
+ };
+
+ button-2 {
+ label = "POWER";
+ linux,code = <KEY_POWER>;
+ gpios = <&wkup_gpio0 4 GPIO_ACTIVE_LOW>;
+ };
+ };
+
+ leds {
+ compatible = "gpio-leds";
+ pinctrl-names = "default";
+ pinctrl-0 = <&led_pins_default>;
+
+ led-0 {
+ gpios = <&main_gpio0 96 GPIO_ACTIVE_HIGH>;
+ function = LED_FUNCTION_HEARTBEAT;
+ linux,default-trigger = "heartbeat";
+ };
+
+ led-1 {
+ gpios = <&main_gpio0 95 GPIO_ACTIVE_HIGH>;
+ function = LED_FUNCTION_DISK_ACTIVITY;
+ linux,default-trigger = "mmc0";
+ };
+
+ led-2 {
+ gpios = <&main_gpio0 97 GPIO_ACTIVE_HIGH>;
+ function = LED_FUNCTION_CPU;
+ linux,default-trigger = "cpu";
+ };
+
+ led-3 {
+ gpios = <&main_gpio0 110 GPIO_ACTIVE_HIGH>;
+ function = LED_FUNCTION_DISK_ACTIVITY;
+ linux,default-trigger = "mmc1";
+ };
+
+ led-4 {
+ gpios = <&main_gpio0 109 GPIO_ACTIVE_HIGH>;
+ function = LED_FUNCTION_WLAN;
+ default-state = "off";
+ };
+ };
+
+ evm_12v0: regulator-0 {
+ /* main supply */
+ compatible = "regulator-fixed";
+ regulator-name = "evm_12v0";
+ regulator-min-microvolt = <12000000>;
+ regulator-max-microvolt = <12000000>;
+ regulator-always-on;
+ regulator-boot-on;
+ };
+
+ vsys_3v3: regulator-1 {
+ /* Output of LMS140 */
+ compatible = "regulator-fixed";
+ regulator-name = "vsys_3v3";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ vin-supply = <&evm_12v0>;
+ regulator-always-on;
+ regulator-boot-on;
+ };
+
+ vsys_5v0: regulator-2 {
+ /* Output of LM5140 */
+ compatible = "regulator-fixed";
+ regulator-name = "vsys_5v0";
+ regulator-min-microvolt = <5000000>;
+ regulator-max-microvolt = <5000000>;
+ vin-supply = <&evm_12v0>;
+ regulator-always-on;
+ regulator-boot-on;
+ };
+
+ vdd_mmc1: regulator-3 {
+ compatible = "regulator-fixed";
+ pinctrl-names = "default";
+ pinctrl-0 = <&sd_pwr_en_pins_default>;
+ regulator-name = "vdd_mmc1";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-boot-on;
+ enable-active-high;
+ vin-supply = <&vsys_3v3>;
+ gpio = <&main_gpio0 82 GPIO_ACTIVE_HIGH>;
+ };
+
+ vdd_sd_dv_alt: regulator-4 {
+ compatible = "regulator-gpio";
+ pinctrl-names = "default";
+ pinctrl-0 = <&vdd_sd_dv_alt_pins_default>;
+ regulator-name = "tlv71033";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-boot-on;
+ vin-supply = <&vsys_5v0>;
+ gpios = <&main_gpio0 117 GPIO_ACTIVE_HIGH>;
+ states = <1800000 0x0>,
+ <3300000 0x1>;
+ };
+
+ dp_pwr_3v3: regulator-5 {
+ compatible = "regulator-fixed";
+ pinctrl-names = "default";
+ pinctrl-0 = <&dp0_3v3_en_pins_default>;
+ regulator-name = "dp-pwr";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ gpio = <&main_gpio0 49 GPIO_ACTIVE_HIGH>; /* DP0_PWR_SW_EN */
+ enable-active-high;
+ };
+
+ dp0: connector {
+ compatible = "dp-connector";
+ label = "DP0";
+ type = "full-size";
+ dp-pwr-supply = <&dp_pwr_3v3>;
+
+ port {
+ dp_connector_in: endpoint {
+ remote-endpoint = <&dp0_out>;
+ };
+ };
+ };
+};
+
+&main_pmx0 {
+ led_pins_default: led-default-pins {
+ pinctrl-single,pins = <
+ J721E_IOPAD(0x184, PIN_INPUT, 7) /* (T23) RGMII5_RD0.GPIO0_96 */
+ J721E_IOPAD(0x180, PIN_INPUT, 7) /* (R23) RGMII5_RD1.GPIO0_95 */
+ J721E_IOPAD(0x188, PIN_INPUT, 7) /* (Y28) RGMII6_TX_CTL.GPIO0_97 */
+ J721E_IOPAD(0x1bc, PIN_INPUT, 7) /* (V24) MDIO0_MDC.GPIO0_110 */
+ J721E_IOPAD(0x1b8, PIN_INPUT, 7) /* (V26) MDIO0_MDIO.GPIO0_109 */
+ >;
+ };
+
+ main_mmc1_pins_default: main-mmc1-default-pins {
+ pinctrl-single,pins = <
+ J721E_IOPAD(0x254, PIN_INPUT, 0) /* (R29) MMC1_CMD */
+ J721E_IOPAD(0x250, PIN_INPUT, 0) /* (P25) MMC1_CLK */
+ J721E_IOPAD(0x2ac, PIN_INPUT, 0) /* (P25) MMC1_CLKLB */
+ J721E_IOPAD(0x24c, PIN_INPUT, 0) /* (R24) MMC1_DAT0 */
+ J721E_IOPAD(0x248, PIN_INPUT, 0) /* (P24) MMC1_DAT1 */
+ J721E_IOPAD(0x244, PIN_INPUT, 0) /* (R25) MMC1_DAT2 */
+ J721E_IOPAD(0x240, PIN_INPUT, 0) /* (R26) MMC1_DAT3 */
+ J721E_IOPAD(0x258, PIN_INPUT, 0) /* (P23) MMC1_SDCD */
+ >;
+ };
+
+ main_uart0_pins_default: main-uart0-default-pins {
+ pinctrl-single,pins = <
+ J721E_IOPAD(0x1e8, PIN_INPUT, 0) /* (AB2) UART0_RXD */
+ J721E_IOPAD(0x1ec, PIN_OUTPUT, 0) /* (AB3) UART0_TXD */
+ >;
+ };
+
+ sd_pwr_en_pins_default: sd-pwr-en-default-pins {
+ pinctrl-single,pins = <
+ J721E_IOPAD(0x14c, PIN_INPUT, 7) /* (AA29) PRG0_PRU1_GPO19.GPIO0_82 */
+ >;
+ };
+
+ vdd_sd_dv_alt_pins_default: vdd-sd-dv-alt-default-pins {
+ pinctrl-single,pins = <
+ J721E_IOPAD(0x1d8, PIN_INPUT, 7) /* (W4) SPI1_CS1.GPIO0_117 */
+ >;
+ };
+
+ main_usbss0_pins_default: main-usbss0-default-pins {
+ pinctrl-single,pins = <
+ J721E_IOPAD(0x210, PIN_INPUT, 7) /* (W3) MCAN1_RX.GPIO1_3 - USBC_DIR */
+ >;
+ };
+
+ main_usbss1_pins_default: main-usbss1-default-pins {
+ pinctrl-single,pins = <
+ J721E_IOPAD(0x290, INPUT_DISABLE, 1) /* (U6) USB0_DRVVBUS.USB1_DRVVBUS */
+ >;
+ };
+
+ dp0_3v3_en_pins_default:dp0-3v3-en-default-pins {
+ pinctrl-single,pins = <
+ J721E_IOPAD(0xc8, PIN_INPUT, 7) /* (AE26) PRG0_PRU0_GPO6.GPIO0_49 */
+ >;
+ };
+
+ dp0_pins_default: dp0-default-pins {
+ pinctrl-single,pins = <
+ J721E_IOPAD(0x1c4, PIN_INPUT, 5) /* (Y4) SPI0_CS1.DP0_HPD */
+ >;
+ };
+
+ main_i2c0_pins_default: main-i2c0-default-pins {
+ pinctrl-single,pins = <
+ J721E_IOPAD(0x220, PIN_INPUT_PULLUP, 0) /* (AC5) I2C0_SCL */
+ J721E_IOPAD(0x224, PIN_INPUT_PULLUP, 0) /* (AA5) I2C0_SDA */
+ >;
+ };
+
+ main_i2c1_pins_default: main-i2c1-default-pins {
+ pinctrl-single,pins = <
+ J721E_IOPAD(0x228, PIN_INPUT_PULLUP, 0) /* (Y6) I2C1_SCL */
+ J721E_IOPAD(0x22c, PIN_INPUT_PULLUP, 0) /* (AA6) I2C1_SDA */
+ >;
+ };
+
+ main_i2c2_pins_default: main-i2c2-default-pins {
+ pinctrl-single,pins = <
+ J721E_IOPAD(0x208, PIN_INPUT_PULLUP, 4) /* (W5) MCAN0_RX.I2C2_SCL */
+ J721E_IOPAD(0x20c, PIN_INPUT_PULLUP, 4) /* (W6) MCAN0_TX.I2C2_SDA */
+ J721E_IOPAD(0x138, PIN_INPUT, 7) /* (AE25) PRG0_PRU1_GPO14.GPIO0_77 */
+ J721E_IOPAD(0x13c, PIN_INPUT, 7) /* (AF29) PRG0_PRU1_GPO15.GPIO0_78 */
+ >;
+ };
+
+ main_i2c3_pins_default: main-i2c3-default-pins {
+ pinctrl-single,pins = <
+ J721E_IOPAD(0x270, PIN_INPUT_PULLUP, 4) /* (T26) MMC2_CLK.I2C3_SCL */
+ J721E_IOPAD(0x274, PIN_INPUT_PULLUP, 4) /* (T25) MMC2_CMD.I2C3_SDA */
+ >;
+ };
+
+ main_i2c4_pins_default: main-i2c4-default-pins {
+ pinctrl-single,pins = <
+ J721E_IOPAD(0x1e0, PIN_INPUT_PULLUP, 2) /* (Y5) SPI1_D0.I2C4_SCL */
+ J721E_IOPAD(0x1dc, PIN_INPUT_PULLUP, 2) /* (Y1) SPI1_CLK.I2C4_SDA */
+ J721E_IOPAD(0x30, PIN_INPUT, 7) /* (AF24) PRG1_PRU0_GPO11.GPIO0_12 */
+ J721E_IOPAD(0x34, PIN_INPUT, 7) /* (AJ24) PRG1_PRU0_GPO12.GPIO0_13 */
+ >;
+ };
+
+ main_i2c5_pins_default: main-i2c5-default-pins {
+ pinctrl-single,pins = <
+ J721E_IOPAD(0x150, PIN_INPUT_PULLUP, 2) /* (Y26) PRG0_MDIO0_MDIO.I2C5_SCL */
+ J721E_IOPAD(0x154, PIN_INPUT_PULLUP, 2) /* (AA27) PRG0_MDIO0_MDC.I2C5_SDA */
+ >;
+ };
+
+ main_i2c6_pins_default: main-i2c6-default-pins {
+ pinctrl-single,pins = <
+ J721E_IOPAD(0x1d0, PIN_INPUT_PULLUP, 2) /* (AA3) SPI0_D1.I2C6_SCL */
+ J721E_IOPAD(0x1e4, PIN_INPUT_PULLUP, 2) /* (Y2) SPI1_D1.I2C6_SDA */
+ J721E_IOPAD(0x74, PIN_INPUT, 7) /* (AC21) PRG1_PRU1_GPO7.GPIO0_28 */
+ J721E_IOPAD(0xa4, PIN_INPUT, 7) /* (AH22) PRG1_PRU1_GPO19.GPIO0_40 */
+ >;
+ };
+
+ csi0_gpio_pins_default: csi0-gpio-default-pins {
+ pinctrl-single,pins = <
+ J721E_IOPAD(0x19c, PIN_INPUT_PULLDOWN, 7) /* (W27) RGMII6_TD0.GPIO0_102 */
+ J721E_IOPAD(0x1a0, PIN_INPUT_PULLDOWN, 7) /* (W29) RGMII6_TXC.GPIO0_103 */
+ >;
+ };
+
+ csi1_gpio_pins_default: csi1-gpio-default-pins {
+ pinctrl-single,pins = <
+ J721E_IOPAD(0x198, PIN_INPUT_PULLDOWN, 7) /* (V25) RGMII6_TD1.GPIO0_101 */
+ J721E_IOPAD(0x1b0, PIN_INPUT_PULLDOWN, 7) /* (W24) RGMII6_RD1.GPIO0_107 */
+ >;
+ };
+
+ pcie1_rst_pins_default: pcie1-rst-default-pins {
+ pinctrl-single,pins = <
+ J721E_IOPAD(0x5c, PIN_INPUT, 7) /* (AG23) PRG1_PRU1_GPO1.GPIO0_22 */
+ >;
+ };
+};
+
+&wkup_pmx0 {
+ eeprom_wp_pins_default: eeprom-wp-default-pins {
+ pinctrl-single,pins = <
+ J721E_WKUP_IOPAD(0xc4, PIN_OUTPUT_PULLUP, 7) /* (G24) WKUP_GPIO0_5 */
+ >;
+ };
+
+ mcu_adc0_pins_default: mcu-adc0-default-pins {
+ pinctrl-single,pins = <
+ J721E_WKUP_IOPAD(0x130, PIN_INPUT, 0) /* (K25) MCU_ADC0_AIN0 */
+ J721E_WKUP_IOPAD(0x134, PIN_INPUT, 0) /* (K26) MCU_ADC0_AIN1 */
+ J721E_WKUP_IOPAD(0x138, PIN_INPUT, 0) /* (K28) MCU_ADC0_AIN2 */
+ J721E_WKUP_IOPAD(0x13c, PIN_INPUT, 0) /* (L28) MCU_ADC0_AIN3 */
+ J721E_WKUP_IOPAD(0x140, PIN_INPUT, 0) /* (K24) MCU_ADC0_AIN4 */
+ J721E_WKUP_IOPAD(0x144, PIN_INPUT, 0) /* (K27) MCU_ADC0_AIN5 */
+ J721E_WKUP_IOPAD(0x148, PIN_INPUT, 0) /* (K29) MCU_ADC0_AIN6 */
+ >;
+ };
+
+ mcu_adc1_pins_default: mcu-adc1-default-pins {
+ pinctrl-single,pins = <
+ J721E_WKUP_IOPAD(0x150, PIN_INPUT, 0) /* (N23) MCU_ADC1_AIN0 */
+ >;
+ };
+
+ mikro_bus_pins_default: mikro-bus-default-pins {
+ pinctrl-single,pins = <
+ J721E_WKUP_IOPAD(0x108, PIN_INPUT, 7) /* SDAPULLEN (E26) PMIC_POWER_EN0.WKUP_GPIO0_66 */
+ J721E_WKUP_IOPAD(0xd4, PIN_INPUT, 7) /* SDA (G26) WKUP_GPIO0_9.MCU_I2C1_SDA */
+ J721E_WKUP_IOPAD(0xf4, PIN_INPUT, 7) /* SDA (D25) MCU_I3C0_SDA.WKUP_GPIO0_61 */
+ J721E_WKUP_IOPAD(0xd0, PIN_INPUT, 7) /* SCL (G27) WKUP_GPIO0_8.MCU_I2C1_SCL */
+ J721E_WKUP_IOPAD(0xf0, PIN_INPUT, 7) /* SCL (D26) MCU_I3C0_SCL.WKUP_GPIO0_60 */
+
+ J721E_WKUP_IOPAD(0xb8, PIN_INPUT, 7) /* MOSI (F28) WKUP_GPIO0_2.MCU_SPI1_D1 */
+ J721E_WKUP_IOPAD(0xb4, PIN_INPUT, 7) /* MISO (F25) WKUP_GPIO0_1.MCU_SPI1_D0 */
+ J721E_WKUP_IOPAD(0xb0, PIN_INPUT, 7) /* CLK (F26) WKUP_GPIO0_0.MCU_SPI1_CLK */
+ J721E_WKUP_IOPAD(0xbc, PIN_INPUT, 7) /* CS (F27) WKUP_GPIO0_3.MCU_SPI1_CS0 */
+
+ J721E_WKUP_IOPAD(0x44, PIN_INPUT, 7) /* RX (G22) MCU_OSPI1_D1.WKUP_GPIO0_33 */
+ J721E_WKUP_IOPAD(0x48, PIN_INPUT, 7) /* TX (D23) MCU_OSPI1_D2.WKUP_GPIO0_34 */
+
+ J721E_WKUP_IOPAD(0x4c, PIN_INPUT, 7) /* INT (C23) MCU_OSPI1_D3.WKUP_GPIO0_35 */
+ J721E_WKUP_IOPAD(0x54, PIN_INPUT, 7) /* RST (E22) MCU_OSPI1_CSn1.WKUP_GPIO0_37 */
+ J721E_WKUP_IOPAD(0xdc, PIN_INPUT, 7) /* PWM (H27) WKUP_GPIO0_11 */
+ J721E_WKUP_IOPAD(0xac, PIN_INPUT, 7) /* AN (C29) MCU_MCAN0_RX.WKUP_GPIO0_59 */
+ >;
+ };
+
+ mcu_cpsw_pins_default: mcu-cpsw-default-pins {
+ pinctrl-single,pins = <
+ J721E_WKUP_IOPAD(0x84, PIN_INPUT, 0) /* (B24) MCU_RGMII1_RD0 */
+ J721E_WKUP_IOPAD(0x80, PIN_INPUT, 0) /* (A24) MCU_RGMII1_RD1 */
+ J721E_WKUP_IOPAD(0x7c, PIN_INPUT, 0) /* (D24) MCU_RGMII1_RD2 */
+ J721E_WKUP_IOPAD(0x78, PIN_INPUT, 0) /* (A25) MCU_RGMII1_RD3 */
+ J721E_WKUP_IOPAD(0x74, PIN_INPUT, 0) /* (C24) MCU_RGMII1_RXC */
+ J721E_WKUP_IOPAD(0x5c, PIN_INPUT, 0) /* (C25) MCU_RGMII1_RX_CTL */
+ J721E_WKUP_IOPAD(0x6c, PIN_OUTPUT, 0) /* (B25) MCU_RGMII1_TD0 */
+ J721E_WKUP_IOPAD(0x68, PIN_OUTPUT, 0) /* (A26) MCU_RGMII1_TD1 */
+ J721E_WKUP_IOPAD(0x64, PIN_OUTPUT, 0) /* (A27) MCU_RGMII1_TD2 */
+ J721E_WKUP_IOPAD(0x60, PIN_OUTPUT, 0) /* (A28) MCU_RGMII1_TD3 */
+ J721E_WKUP_IOPAD(0x70, PIN_OUTPUT, 0) /* (B26) MCU_RGMII1_TXC */
+ J721E_WKUP_IOPAD(0x58, PIN_OUTPUT, 0) /* (B27) MCU_RGMII1_TX_CTL */
+ >;
+ };
+
+ mcu_mdio_pins_default: mcu-mdio1-default-pins {
+ pinctrl-single,pins = <
+ J721E_WKUP_IOPAD(0x8c, PIN_OUTPUT, 0) /* (F23) MCU_MDIO0_MDC */
+ J721E_WKUP_IOPAD(0x88, PIN_INPUT, 0) /* (E23) MCU_MDIO0_MDIO */
+ >;
+ };
+
+ sw_pwr_pins_default: sw-pwr-default-pins {
+ pinctrl-single,pins = <
+ J721E_WKUP_IOPAD(0xc0, PIN_INPUT, 7) /* (G25) WKUP_GPIO0_4 */
+ >;
+ };
+
+ wkup_i2c0_pins_default: wkup-i2c0-default-pins {
+ pinctrl-single,pins = <
+ J721E_WKUP_IOPAD(0xf8, PIN_INPUT_PULLUP, 0) /* (J25) WKUP_I2C0_SCL */
+ J721E_WKUP_IOPAD(0xfc, PIN_INPUT_PULLUP, 0) /* (H24) WKUP_I2C0_SDA */
+ >;
+ };
+
+ wkup_uart0_pins_default: wkup-uart0-default-pins {
+ pinctrl-single,pins = <
+ J721E_WKUP_IOPAD(0xa0, PIN_INPUT, 0) /* (J29) WKUP_UART0_RXD */
+ J721E_WKUP_IOPAD(0xa4, PIN_OUTPUT, 0) /* (J28) WKUP_UART0_TXD */
+ >;
+ };
+
+ mcu_usbss1_pins_default: mcu-usbss1-default-pins {
+ pinctrl-single,pins = <
+ J721E_WKUP_IOPAD(0x3c, PIN_OUTPUT_PULLUP, 5) /* (A23) MCU_OSPI1_LBCLKO.WKUP_GPIO0_30 */
+ >;
+ };
+};
+
+&wkup_uart0 {
+ /* Wakeup UART is used by TIFS firmware. */
+ status = "reserved";
+ pinctrl-names = "default";
+ pinctrl-0 = <&wkup_uart0_pins_default>;
+};
+
+&main_uart0 {
+ status = "okay";
+ pinctrl-names = "default";
+ pinctrl-0 = <&main_uart0_pins_default>;
+ /* Shared with ATF on this platform */
+ power-domains = <&k3_pds 146 TI_SCI_PD_SHARED>;
+};
+
+&main_sdhci0 {
+ /* eMMC */
+ status = "okay";
+ non-removable;
+ ti,driver-strength-ohm = <50>;
+ disable-wp;
+};
+
+&main_sdhci1 {
+ /* SD Card */
+ status = "okay";
+ vmmc-supply = <&vdd_mmc1>;
+ vqmmc-supply = <&vdd_sd_dv_alt>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&main_mmc1_pins_default>;
+ ti,driver-strength-ohm = <50>;
+ disable-wp;
+};
+
+&main_i2c0 {
+ status = "okay";
+ pinctrl-names = "default";
+ pinctrl-0 = <&main_i2c0_pins_default>;
+ clock-frequency = <400000>;
+};
+
+&main_i2c1 {
+ status = "okay";
+ pinctrl-names = "default";
+ pinctrl-0 = <&main_i2c1_pins_default>;
+ clock-frequency = <400000>;
+};
+
+&main_i2c2 {
+ /* BBB Header: P9.19 and P9.20 */
+ status = "okay";
+ pinctrl-names = "default";
+ pinctrl-0 = <&main_i2c2_pins_default>;
+ clock-frequency = <100000>;
+};
+
+&main_i2c3 {
+ status = "okay";
+ pinctrl-names = "default";
+ pinctrl-0 = <&main_i2c3_pins_default>;
+ clock-frequency = <400000>;
+};
+
+&main_i2c4 {
+ /* BBB Header: P9.24 and P9.26 */
+ status = "okay";
+ pinctrl-names = "default";
+ pinctrl-0 = <&main_i2c4_pins_default>;
+ clock-frequency = <100000>;
+};
+
+&main_i2c5 {
+ status = "okay";
+ pinctrl-names = "default";
+ pinctrl-0 = <&main_i2c5_pins_default>;
+ clock-frequency = <400000>;
+};
+
+&main_i2c6 {
+ /* BBB Header: P9.17 and P9.18 */
+ status = "okay";
+ pinctrl-names = "default";
+ pinctrl-0 = <&main_i2c6_pins_default>;
+ clock-frequency = <100000>;
+ status = "okay";
+};
+
+&wkup_i2c0 {
+ status = "okay";
+ pinctrl-names = "default";
+ pinctrl-0 = <&wkup_i2c0_pins_default>;
+ clock-frequency = <400000>;
+
+ eeprom@50 {
+ compatible = "atmel,24c04";
+ reg = <0x50>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&eeprom_wp_pins_default>;
+ };
+};
+
+&wkup_gpio0 {
+ status = "okay";
+ pinctrl-names = "default";
+ pinctrl-0 = <&mcu_adc0_pins_default>, <&mcu_adc1_pins_default>,
+ <&mikro_bus_pins_default>;
+};
+
+&main_gpio0 {
+ status = "okay";
+ pinctrl-names = "default";
+ pinctrl-0 = <&csi1_gpio_pins_default>, <&csi0_gpio_pins_default>;
+};
+
+&main_gpio1 {
+ status = "okay";
+};
+
+&usb_serdes_mux {
+ idle-states = <1>, <1>; /* USB0 to SERDES3, USB1 to SERDES2 */
+};
+
+&serdes_ln_ctrl {
+ idle-states = <J721E_SERDES0_LANE0_IP4_UNUSED>, <J721E_SERDES0_LANE1_IP4_UNUSED>,
+ <J721E_SERDES1_LANE0_PCIE1_LANE0>, <J721E_SERDES1_LANE1_PCIE1_LANE1>,
+ <J721E_SERDES2_LANE0_IP1_UNUSED>, <J721E_SERDES2_LANE1_USB3_1>,
+ <J721E_SERDES3_LANE0_USB3_0_SWAP>, <J721E_SERDES3_LANE1_USB3_0>,
+ <J721E_SERDES4_LANE0_EDP_LANE0>, <J721E_SERDES4_LANE1_EDP_LANE1>,
+ <J721E_SERDES4_LANE2_EDP_LANE2>, <J721E_SERDES4_LANE3_EDP_LANE3>;
+};
+
+&serdes_wiz3 {
+ typec-dir-gpios = <&main_gpio1 3 GPIO_ACTIVE_LOW>;
+ typec-dir-debounce-ms = <700>; /* TUSB321, tCCB_DEFAULT 133 ms */
+};
+
+&serdes3 {
+ serdes3_usb_link: phy@0 {
+ reg = <0>;
+ cdns,num-lanes = <2>;
+ #phy-cells = <0>;
+ cdns,phy-type = <PHY_TYPE_USB3>;
+ resets = <&serdes_wiz3 1>, <&serdes_wiz3 2>;
+ };
+};
+
+&serdes4 {
+ torrent_phy_dp: phy@0 {
+ reg = <0>;
+ resets = <&serdes_wiz4 1>;
+ cdns,phy-type = <PHY_TYPE_DP>;
+ cdns,num-lanes = <4>;
+ cdns,max-bit-rate = <5400>;
+ #phy-cells = <0>;
+ };
+};
+
+&mhdp {
+ phys = <&torrent_phy_dp>;
+ phy-names = "dpphy";
+ pinctrl-names = "default";
+ pinctrl-0 = <&dp0_pins_default>;
+};
+
+&usbss0 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&main_usbss0_pins_default>;
+ ti,vbus-divider;
+};
+
+&usb0 {
+ dr_mode = "peripheral";
+ maximum-speed = "super-speed";
+ phys = <&serdes3_usb_link>;
+ phy-names = "cdns3,usb3-phy";
+};
+
+&serdes2 {
+ serdes2_usb_link: phy@1 {
+ reg = <1>;
+ cdns,num-lanes = <1>;
+ #phy-cells = <0>;
+ cdns,phy-type = <PHY_TYPE_USB3>;
+ resets = <&serdes_wiz2 2>;
+ };
+};
+
+&usbss1 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&main_usbss1_pins_default>, <&mcu_usbss1_pins_default>;
+ ti,vbus-divider;
+};
+
+&usb1 {
+ dr_mode = "host";
+ maximum-speed = "super-speed";
+ phys = <&serdes2_usb_link>;
+ phy-names = "cdns3,usb3-phy";
+};
+
+&tscadc0 {
+ status = "okay";
+ /* BBB Header: P9.39, P9.40, P9.37, P9.38, P9.33, P9.36, P9.35 */
+ adc {
+ ti,adc-channels = <0 1 2 3 4 5 6>;
+ };
+};
+
+&tscadc1 {
+ status = "okay";
+ /* MCU mikroBUS Header J10.1 - MCU_ADC1_AIN0 */
+ adc {
+ ti,adc-channels = <0>;
+ };
+};
+
+&mcu_cpsw {
+ pinctrl-names = "default";
+ pinctrl-0 = <&mcu_cpsw_pins_default>;
+};
+
+&davinci_mdio {
+ pinctrl-names = "default";
+ pinctrl-0 = <&mcu_mdio_pins_default>;
+
+ phy0: ethernet-phy@0 {
+ reg = <0>;
+ ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_00_NS>;
+ ti,fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>;
+ };
+};
+
+&cpsw_port1 {
+ phy-mode = "rgmii-rxid";
+ phy-handle = <&phy0>;
+};
+
+&dss {
+ /*
+ * These clock assignments are chosen to enable the following outputs:
+ *
+ * VP0 - DisplayPort SST
+ * VP1 - DPI0
+ * VP2 - DSI
+ * VP3 - DPI1
+ */
+
+ assigned-clocks = <&k3_clks 152 1>, /* VP 1 pixel clock */
+ <&k3_clks 152 4>, /* VP 2 pixel clock */
+ <&k3_clks 152 9>, /* VP 3 pixel clock */
+ <&k3_clks 152 13>; /* VP 4 pixel clock */
+ assigned-clock-parents = <&k3_clks 152 2>, /* PLL16_HSDIV0 */
+ <&k3_clks 152 6>, /* PLL19_HSDIV0 */
+ <&k3_clks 152 11>, /* PLL18_HSDIV0 */
+ <&k3_clks 152 18>; /* PLL23_HSDIV0 */
+};
+
+&dss_ports {
+ port {
+ dpi0_out: endpoint {
+ remote-endpoint = <&dp0_in>;
+ };
+ };
+};
+
+&dp0_ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+ dp0_in: endpoint {
+ remote-endpoint = <&dpi0_out>;
+ };
+ };
+
+ port@4 {
+ reg = <4>;
+ dp0_out: endpoint {
+ remote-endpoint = <&dp_connector_in>;
+ };
+ };
+};
+
+&serdes0 {
+ serdes0_pcie_link: phy@0 {
+ reg = <0>;
+ cdns,num-lanes = <1>;
+ #phy-cells = <0>;
+ cdns,phy-type = <PHY_TYPE_PCIE>;
+ resets = <&serdes_wiz0 1>;
+ };
+};
+
+&serdes1 {
+ serdes1_pcie_link: phy@0 {
+ reg = <0>;
+ cdns,num-lanes = <2>;
+ #phy-cells = <0>;
+ cdns,phy-type = <PHY_TYPE_PCIE>;
+ resets = <&serdes_wiz1 1>, <&serdes_wiz1 2>;
+ };
+};
+
+&pcie1_rc {
+ status = "okay";
+ pinctrl-names = "default";
+ pinctrl-0 = <&pcie1_rst_pins_default>;
+ phys = <&serdes1_pcie_link>;
+ phy-names = "pcie-phy";
+ num-lanes = <2>;
+ max-link-speed = <3>;
+ reset-gpios = <&main_gpio0 22 GPIO_ACTIVE_HIGH>;
+};
+
+&ufs_wrapper {
+ status = "disabled";
+};
+
+&mailbox0_cluster0 {
+ status = "okay";
+ interrupts = <436>;
+
+ mbox_mcu_r5fss0_core0: mbox-mcu-r5fss0-core0 {
+ ti,mbox-rx = <0 0 0>;
+ ti,mbox-tx = <1 0 0>;
+ };
+
+ mbox_mcu_r5fss0_core1: mbox-mcu-r5fss0-core1 {
+ ti,mbox-rx = <2 0 0>;
+ ti,mbox-tx = <3 0 0>;
+ };
+};
+
+&mailbox0_cluster1 {
+ status = "okay";
+ interrupts = <432>;
+
+ mbox_main_r5fss0_core0: mbox-main-r5fss0-core0 {
+ ti,mbox-rx = <0 0 0>;
+ ti,mbox-tx = <1 0 0>;
+ };
+
+ mbox_main_r5fss0_core1: mbox-main-r5fss0-core1 {
+ ti,mbox-rx = <2 0 0>;
+ ti,mbox-tx = <3 0 0>;
+ };
+};
+
+&mailbox0_cluster2 {
+ status = "okay";
+ interrupts = <428>;
+
+ mbox_main_r5fss1_core0: mbox-main-r5fss1-core0 {
+ ti,mbox-rx = <0 0 0>;
+ ti,mbox-tx = <1 0 0>;
+ };
+
+ mbox_main_r5fss1_core1: mbox-main-r5fss1-core1 {
+ ti,mbox-rx = <2 0 0>;
+ ti,mbox-tx = <3 0 0>;
+ };
+};
+
+&mailbox0_cluster3 {
+ status = "okay";
+ interrupts = <424>;
+
+ mbox_c66_0: mbox-c66-0 {
+ ti,mbox-rx = <0 0 0>;
+ ti,mbox-tx = <1 0 0>;
+ };
+
+ mbox_c66_1: mbox-c66-1 {
+ ti,mbox-rx = <2 0 0>;
+ ti,mbox-tx = <3 0 0>;
+ };
+};
+
+&mailbox0_cluster4 {
+ status = "okay";
+ interrupts = <420>;
+
+ mbox_c71_0: mbox-c71-0 {
+ ti,mbox-rx = <0 0 0>;
+ ti,mbox-tx = <1 0 0>;
+ };
+};
+
+&mcu_r5fss0_core0 {
+ mboxes = <&mailbox0_cluster0>, <&mbox_mcu_r5fss0_core0>;
+ memory-region = <&mcu_r5fss0_core0_dma_memory_region>,
+ <&mcu_r5fss0_core0_memory_region>;
+};
+
+&mcu_r5fss0_core1 {
+ mboxes = <&mailbox0_cluster0>, <&mbox_mcu_r5fss0_core1>;
+ memory-region = <&mcu_r5fss0_core1_dma_memory_region>,
+ <&mcu_r5fss0_core1_memory_region>;
+};
+
+&main_r5fss0_core0 {
+ mboxes = <&mailbox0_cluster1>, <&mbox_main_r5fss0_core0>;
+ memory-region = <&main_r5fss0_core0_dma_memory_region>,
+ <&main_r5fss0_core0_memory_region>;
+};
+
+&main_r5fss0_core1 {
+ mboxes = <&mailbox0_cluster1>, <&mbox_main_r5fss0_core1>;
+ memory-region = <&main_r5fss0_core1_dma_memory_region>,
+ <&main_r5fss0_core1_memory_region>;
+};
+
+&main_r5fss1_core0 {
+ mboxes = <&mailbox0_cluster2>, <&mbox_main_r5fss1_core0>;
+ memory-region = <&main_r5fss1_core0_dma_memory_region>,
+ <&main_r5fss1_core0_memory_region>;
+};
+
+&main_r5fss1_core1 {
+ mboxes = <&mailbox0_cluster2>, <&mbox_main_r5fss1_core1>;
+ memory-region = <&main_r5fss1_core1_dma_memory_region>,
+ <&main_r5fss1_core1_memory_region>;
+};
+
+&c66_0 {
+ status = "okay";
+ mboxes = <&mailbox0_cluster3>, <&mbox_c66_0>;
+ memory-region = <&c66_0_dma_memory_region>,
+ <&c66_0_memory_region>;
+};
+
+&c66_1 {
+ status = "okay";
+ mboxes = <&mailbox0_cluster3>, <&mbox_c66_1>;
+ memory-region = <&c66_1_dma_memory_region>,
+ <&c66_1_memory_region>;
+};
+
+&c71_0 {
+ status = "okay";
+ mboxes = <&mailbox0_cluster4>, <&mbox_c71_0>;
+ memory-region = <&c71_0_dma_memory_region>,
+ <&c71_0_memory_region>;
+};
diff --git a/arch/arm/dts/k3-j721e-binman.dtsi b/arch/arm/dts/k3-j721e-binman.dtsi
index 4f566c2..5ddb474 100644
--- a/arch/arm/dts/k3-j721e-binman.dtsi
+++ b/arch/arm/dts/k3-j721e-binman.dtsi
@@ -42,78 +42,7 @@
};
itb {
filename = "sysfw-j721e_sr1_1-hs-evm.itb";
- fit {
- description = "SYSFW and Config fragments";
- #address-cells = <1>;
- images {
- sysfw.bin {
- description = "sysfw";
- type = "firmware";
- arch = "arm";
- compression = "none";
- blob-ext {
- filename = "sysfw.bin";
- };
- };
- board-cfg.bin {
- description = "board-cfg";
- type = "firmware";
- arch = "arm";
- compression = "none";
- ti-secure {
- content = <&board_cfg>;
- keyfile = "custMpk.pem";
- };
- board_cfg: board-cfg {
- filename = "board-cfg.bin";
- type = "blob-ext";
- };
-
- };
- pm-cfg.bin {
- description = "pm-cfg";
- type = "firmware";
- arch = "arm";
- compression = "none";
- ti-secure {
- content = <&pm_cfg>;
- keyfile = "custMpk.pem";
- };
- pm_cfg: pm-cfg {
- filename = "pm-cfg.bin";
- type = "blob-ext";
- };
- };
- rm-cfg.bin {
- description = "rm-cfg";
- type = "firmware";
- arch = "arm";
- compression = "none";
- ti-secure {
- content = <&rm_cfg>;
- keyfile = "custMpk.pem";
- };
- rm_cfg: rm-cfg {
- filename = "rm-cfg.bin";
- type = "blob-ext";
- };
- };
- sec-cfg.bin {
- description = "sec-cfg";
- type = "firmware";
- arch = "arm";
- compression = "none";
- ti-secure {
- content = <&sec_cfg>;
- keyfile = "custMpk.pem";
- };
- sec_cfg: sec-cfg {
- filename = "sec-cfg.bin";
- type = "blob-ext";
- };
- };
- };
- };
+ insert-template = <&itb_template>;
};
};
@@ -145,62 +74,7 @@
};
itb_fs {
filename = "sysfw-j721e_sr2-hs-fs-evm.itb";
- fit {
- description = "SYSFW and Config fragments";
- #address-cells = <1>;
- images {
- sysfw.bin {
- description = "sysfw";
- type = "firmware";
- arch = "arm";
- compression = "none";
- blob-ext {
- filename = "sysfw.bin_fs";
- };
- };
- board-cfg.bin {
- description = "board-cfg";
- type = "firmware";
- arch = "arm";
- compression = "none";
- board-cfg {
- filename = "board-cfg.bin";
- type = "blob-ext";
- };
-
- };
- pm-cfg.bin {
- description = "pm-cfg";
- type = "firmware";
- arch = "arm";
- compression = "none";
- pm-cfg {
- filename = "pm-cfg.bin";
- type = "blob-ext";
- };
- };
- rm-cfg.bin {
- description = "rm-cfg";
- type = "firmware";
- arch = "arm";
- compression = "none";
- rm-cfg {
- filename = "rm-cfg.bin";
- type = "blob-ext";
- };
- };
- sec-cfg.bin {
- description = "sec-cfg";
- type = "firmware";
- arch = "arm";
- compression = "none";
- sec-cfg {
- filename = "sec-cfg.bin";
- type = "blob-ext";
- };
- };
- };
- };
+ insert-template = <&itb_unsigned_template>;
};
};
@@ -237,55 +111,15 @@
itb_gp {
filename = "sysfw-j721e-gp-evm.itb";
symlink = "sysfw.itb";
+ insert-template = <&itb_unsigned_template>;
+
fit {
- description = "SYSFW and Config fragments";
- #address-cells = <1>;
images {
sysfw.bin {
- description = "sysfw";
- type = "firmware";
- arch = "arm";
- compression = "none";
blob-ext {
filename = "sysfw.bin_gp";
};
};
- board-cfg.bin {
- description = "board-cfg";
- type = "firmware";
- arch = "arm";
- compression = "none";
- blob-ext {
- filename = "board-cfg.bin";
- };
- };
- pm-cfg.bin {
- description = "pm-cfg";
- type = "firmware";
- arch = "arm";
- compression = "none";
- blob-ext {
- filename = "pm-cfg.bin";
- };
- };
- rm-cfg.bin {
- description = "rm-cfg";
- type = "firmware";
- arch = "arm";
- compression = "none";
- blob-ext {
- filename = "rm-cfg.bin";
- };
- };
- sec-cfg.bin {
- description = "sec-cfg";
- type = "firmware";
- arch = "arm";
- compression = "none";
- blob-ext {
- filename = "sec-cfg.bin";
- };
- };
};
};
};
@@ -294,11 +128,9 @@
#ifdef CONFIG_TARGET_J721E_A72_EVM
-#define SPL_NODTB "spl/u-boot-spl-nodtb.bin"
#define SPL_J721E_EVM_DTB "spl/dts/k3-j721e-common-proc-board.dtb"
#define SPL_J721E_SK_DTB "spl/dts/k3-j721e-sk.dtb"
-#define UBOOT_NODTB "u-boot-nodtb.bin"
#define J721E_EVM_DTB "u-boot.dtb"
#define J721E_SK_DTB "arch/arm/dts/k3-j721e-sk.dtb"
@@ -310,55 +142,11 @@
};
};
ti-spl {
- filename = "tispl.bin";
- pad-byte = <0xff>;
+ insert-template = <&ti_spl_template>;
fit {
- description = "Configuration to load ATF and SPL";
- #address-cells = <1>;
-
images {
-
- atf {
- description = "ARM Trusted Firmware";
- type = "firmware";
- arch = "arm64";
- compression = "none";
- os = "arm-trusted-firmware";
- load = <CONFIG_K3_ATF_LOAD_ADDR>;
- entry = <CONFIG_K3_ATF_LOAD_ADDR>;
- ti-secure {
- content = <&atf>;
- keyfile = "custMpk.pem";
- };
- atf: atf-bl31 {
- };
- };
-
- tee {
- description = "OP-TEE";
- type = "tee";
- arch = "arm64";
- compression = "none";
- os = "tee";
- load = <0x9e800000>;
- entry = <0x9e800000>;
- ti-secure {
- content = <&tee>;
- keyfile = "custMpk.pem";
- };
- tee: tee-os {
- };
- };
-
dm {
- description = "DM binary";
- type = "firmware";
- arch = "arm32";
- compression = "none";
- os = "DM";
- load = <0x89000000>;
- entry = <0x89000000>;
ti-secure {
content = <&dm>;
keyfile = "custMpk.pem";
@@ -368,24 +156,6 @@
};
};
- spl {
- description = "SPL (64-bit)";
- type = "standalone";
- os = "U-Boot";
- arch = "arm64";
- compression = "none";
- load = <CONFIG_SPL_TEXT_BASE>;
- entry = <CONFIG_SPL_TEXT_BASE>;
- ti-secure {
- content = <&u_boot_spl_nodtb>;
- keyfile = "custMpk.pem";
-
- };
- u_boot_spl_nodtb: blob-ext {
- filename = SPL_NODTB;
- };
- };
-
fdt-0 {
description = "k3-j721e-common-proc-board";
type = "flat_dt";
@@ -439,29 +209,12 @@
&binman {
u-boot {
- filename = "u-boot.img";
- pad-byte = <0xff>;
-
+ insert-template = <&u_boot_template>;
fit {
- description = "FIT image with multiple configurations";
images {
uboot {
- description = "U-Boot for j721e board";
- type = "firmware";
- os = "u-boot";
- arch = "arm";
- compression = "none";
- load = <CONFIG_TEXT_BASE>;
- ti-secure {
- content = <&u_boot_nodtb>;
- keyfile = "custMpk.pem";
- };
- u_boot_nodtb: u-boot-nodtb {
- };
- hash {
- algo = "crc32";
- };
+ description = "U-Boot for J721E Board";
};
fdt-0 {
@@ -524,67 +277,16 @@
&binman {
ti-spl_unsigned {
- filename = "tispl.bin_unsigned";
- pad-byte = <0xff>;
+ insert-template = <&ti_spl_unsigned_template>;
fit {
- description = "Configuration to load ATF and SPL";
- #address-cells = <1>;
-
images {
-
- atf {
- description = "ARM Trusted Firmware";
- type = "firmware";
- arch = "arm64";
- compression = "none";
- os = "arm-trusted-firmware";
- load = <CONFIG_K3_ATF_LOAD_ADDR>;
- entry = <CONFIG_K3_ATF_LOAD_ADDR>;
- atf-bl31 {
- filename = "bl31.bin";
- };
- };
-
- tee {
- description = "OP-TEE";
- type = "tee";
- arch = "arm64";
- compression = "none";
- os = "tee";
- load = <0x9e800000>;
- entry = <0x9e800000>;
- tee-os {
- filename = "tee-raw.bin";
- };
- };
-
dm {
- description = "DM binary";
- type = "firmware";
- arch = "arm32";
- compression = "none";
- os = "DM";
- load = <0x89000000>;
- entry = <0x89000000>;
blob-ext {
filename = "ti-dm.bin";
};
};
- spl {
- description = "SPL (64-bit)";
- type = "standalone";
- os = "U-Boot";
- arch = "arm64";
- compression = "none";
- load = <CONFIG_SPL_TEXT_BASE>;
- entry = <CONFIG_SPL_TEXT_BASE>;
- blob-ext {
- filename = SPL_NODTB;
- };
- };
-
fdt-0 {
description = "k3-j721e-common-proc-board";
type = "flat_dt";
@@ -629,26 +331,12 @@
&binman {
u-boot_unsigned {
- filename = "u-boot.img_unsigned";
- pad-byte = <0xff>;
+ insert-template = <&u_boot_unsigned_template>;
fit {
- description = "FIT image with multiple configurations";
-
images {
uboot {
- description = "U-Boot for j721e board";
- type = "firmware";
- os = "u-boot";
- arch = "arm";
- compression = "none";
- load = <CONFIG_TEXT_BASE>;
- blob {
- filename = UBOOT_NODTB;
- };
- hash {
- algo = "crc32";
- };
+ description = "U-Boot for J721E Board";
};
fdt-0 {
diff --git a/arch/arm/dts/k3-j721e-common-proc-board-u-boot.dtsi b/arch/arm/dts/k3-j721e-common-proc-board-u-boot.dtsi
index cd95907..b77f8d9 100644
--- a/arch/arm/dts/k3-j721e-common-proc-board-u-boot.dtsi
+++ b/arch/arm/dts/k3-j721e-common-proc-board-u-boot.dtsi
@@ -1,6 +1,6 @@
// SPDX-License-Identifier: GPL-2.0
/*
- * Copyright (C) 2018 Texas Instruments Incorporated - http://www.ti.com/
+ * Copyright (C) 2018 Texas Instruments Incorporated - https://www.ti.com/
*/
#include "k3-j721e-binman.dtsi"
diff --git a/arch/arm/dts/k3-j721e-ddr-beagleboneai64-lp4-3200.dtsi b/arch/arm/dts/k3-j721e-ddr-beagleboneai64-lp4-3200.dtsi
new file mode 100644
index 0000000..89e1775
--- /dev/null
+++ b/arch/arm/dts/k3-j721e-ddr-beagleboneai64-lp4-3200.dtsi
@@ -0,0 +1,2200 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2019-2023 Texas Instruments Incorporated - http://www.ti.com/
+ * This file was generated by the Jacinto7_DDRSS_RegConfigTool, Revision: 0.10.1
+ * This file was generated on 02/08/2023
+ * Part Number: Kingston Q3222PM1WDGTK-U
+ * Configuration: LPDDR4-3200, wrDBI enabled, j721e-SK latencies
+ * Also common for:
+ * * Part Number: Samsung K4FBE3D4HM-MGC @ LPDDR4-3200 (instead of 3700)
+ */
+
+#define DDRSS_PLL_FHS_CNT 10
+#define DDRSS_PLL_FREQUENCY_0 27500000
+#define DDRSS_PLL_FREQUENCY_1 800000000
+#define DDRSS_PLL_FREQUENCY_2 800000000
+
+#define DDRSS_CTL_00_DATA 0x00000B00
+#define DDRSS_CTL_01_DATA 0x00000000
+#define DDRSS_CTL_02_DATA 0x00000000
+#define DDRSS_CTL_03_DATA 0x00000000
+#define DDRSS_CTL_04_DATA 0x00000000
+#define DDRSS_CTL_05_DATA 0x00000000
+#define DDRSS_CTL_06_DATA 0x00000000
+#define DDRSS_CTL_07_DATA 0x00002AF8
+#define DDRSS_CTL_08_DATA 0x0001ADAF
+#define DDRSS_CTL_09_DATA 0x00000005
+#define DDRSS_CTL_10_DATA 0x0000006E
+#define DDRSS_CTL_11_DATA 0x0004E200
+#define DDRSS_CTL_12_DATA 0x0030D400
+#define DDRSS_CTL_13_DATA 0x00000005
+#define DDRSS_CTL_14_DATA 0x00000C80
+#define DDRSS_CTL_15_DATA 0x0004E200
+#define DDRSS_CTL_16_DATA 0x0030D400
+#define DDRSS_CTL_17_DATA 0x00000005
+#define DDRSS_CTL_18_DATA 0x00000C80
+#define DDRSS_CTL_19_DATA 0x01010000
+#define DDRSS_CTL_20_DATA 0x02011001
+#define DDRSS_CTL_21_DATA 0x02010000
+#define DDRSS_CTL_22_DATA 0x00020100
+#define DDRSS_CTL_23_DATA 0x0000000B
+#define DDRSS_CTL_24_DATA 0x0000001C
+#define DDRSS_CTL_25_DATA 0x00000000
+#define DDRSS_CTL_26_DATA 0x00000000
+#define DDRSS_CTL_27_DATA 0x03020200
+#define DDRSS_CTL_28_DATA 0x00004040
+#define DDRSS_CTL_29_DATA 0x00100000
+#define DDRSS_CTL_30_DATA 0x00000000
+#define DDRSS_CTL_31_DATA 0x00000000
+#define DDRSS_CTL_32_DATA 0x00000000
+#define DDRSS_CTL_33_DATA 0x00000000
+#define DDRSS_CTL_34_DATA 0x040C0000
+#define DDRSS_CTL_35_DATA 0x0E380E38
+#define DDRSS_CTL_36_DATA 0x00050804
+#define DDRSS_CTL_37_DATA 0x09040008
+#define DDRSS_CTL_38_DATA 0x14000304
+#define DDRSS_CTL_39_DATA 0x15480068
+#define DDRSS_CTL_40_DATA 0x14004220
+#define DDRSS_CTL_41_DATA 0x15480068
+#define DDRSS_CTL_42_DATA 0x20004220
+#define DDRSS_CTL_43_DATA 0x000A0A09
+#define DDRSS_CTL_44_DATA 0x0400078A
+#define DDRSS_CTL_45_DATA 0x17100D04
+#define DDRSS_CTL_46_DATA 0x0C00DB60
+#define DDRSS_CTL_47_DATA 0x17100D0C
+#define DDRSS_CTL_48_DATA 0x0C00DB60
+#define DDRSS_CTL_49_DATA 0x0203040C
+#define DDRSS_CTL_50_DATA 0x21040500
+#define DDRSS_CTL_51_DATA 0x08222122
+#define DDRSS_CTL_52_DATA 0x14000E0A
+#define DDRSS_CTL_53_DATA 0x03010A0A
+#define DDRSS_CTL_54_DATA 0x01010003
+#define DDRSS_CTL_55_DATA 0x04424208
+#define DDRSS_CTL_56_DATA 0x04252504
+#define DDRSS_CTL_57_DATA 0x00002525
+#define DDRSS_CTL_58_DATA 0x00010100
+#define DDRSS_CTL_59_DATA 0x03010000
+#define DDRSS_CTL_60_DATA 0x00001008
+#define DDRSS_CTL_61_DATA 0x000000CE
+#define DDRSS_CTL_62_DATA 0x000001C0
+#define DDRSS_CTL_63_DATA 0x00001858
+#define DDRSS_CTL_64_DATA 0x000001C0
+#define DDRSS_CTL_65_DATA 0x00001858
+#define DDRSS_CTL_66_DATA 0x00000005
+#define DDRSS_CTL_67_DATA 0x00040000
+#define DDRSS_CTL_68_DATA 0x00700012
+#define DDRSS_CTL_69_DATA 0x00700304
+#define DDRSS_CTL_70_DATA 0x00400304
+#define DDRSS_CTL_71_DATA 0x00120103
+#define DDRSS_CTL_72_DATA 0x000C0005
+#define DDRSS_CTL_73_DATA 0x2408000C
+#define DDRSS_CTL_74_DATA 0x05050124
+#define DDRSS_CTL_75_DATA 0x0301030A
+#define DDRSS_CTL_76_DATA 0x03170C08
+#define DDRSS_CTL_77_DATA 0x0C080301
+#define DDRSS_CTL_78_DATA 0x00010317
+#define DDRSS_CTL_79_DATA 0x00100010
+#define DDRSS_CTL_80_DATA 0x01CC01CC
+#define DDRSS_CTL_81_DATA 0x01CC01CC
+#define DDRSS_CTL_82_DATA 0x03050505
+#define DDRSS_CTL_83_DATA 0x03010303
+#define DDRSS_CTL_84_DATA 0x18080C08
+#define DDRSS_CTL_85_DATA 0x03030C03
+#define DDRSS_CTL_86_DATA 0x18080C08
+#define DDRSS_CTL_87_DATA 0x03030C03
+#define DDRSS_CTL_88_DATA 0x03010000
+#define DDRSS_CTL_89_DATA 0x00010000
+#define DDRSS_CTL_90_DATA 0x00000000
+#define DDRSS_CTL_91_DATA 0x00000000
+#define DDRSS_CTL_92_DATA 0x01000000
+#define DDRSS_CTL_93_DATA 0x80104002
+#define DDRSS_CTL_94_DATA 0x00000000
+#define DDRSS_CTL_95_DATA 0x00040005
+#define DDRSS_CTL_96_DATA 0x00000000
+#define DDRSS_CTL_97_DATA 0x00050000
+#define DDRSS_CTL_98_DATA 0x00000004
+#define DDRSS_CTL_99_DATA 0x00000000
+#define DDRSS_CTL_100_DATA 0x00040005
+#define DDRSS_CTL_101_DATA 0x00000000
+#define DDRSS_CTL_102_DATA 0x00003380
+#define DDRSS_CTL_103_DATA 0x00003380
+#define DDRSS_CTL_104_DATA 0x00003380
+#define DDRSS_CTL_105_DATA 0x00003380
+#define DDRSS_CTL_106_DATA 0x00003380
+#define DDRSS_CTL_107_DATA 0x00000000
+#define DDRSS_CTL_108_DATA 0x000005A2
+#define DDRSS_CTL_109_DATA 0x00061600
+#define DDRSS_CTL_110_DATA 0x00061600
+#define DDRSS_CTL_111_DATA 0x00061600
+#define DDRSS_CTL_112_DATA 0x00061600
+#define DDRSS_CTL_113_DATA 0x00061600
+#define DDRSS_CTL_114_DATA 0x00000000
+#define DDRSS_CTL_115_DATA 0x0000AA68
+#define DDRSS_CTL_116_DATA 0x00061600
+#define DDRSS_CTL_117_DATA 0x00061600
+#define DDRSS_CTL_118_DATA 0x00061600
+#define DDRSS_CTL_119_DATA 0x00061600
+#define DDRSS_CTL_120_DATA 0x00061600
+#define DDRSS_CTL_121_DATA 0x00000000
+#define DDRSS_CTL_122_DATA 0x0000AA68
+#define DDRSS_CTL_123_DATA 0x00000000
+#define DDRSS_CTL_124_DATA 0x00000000
+#define DDRSS_CTL_125_DATA 0x00000000
+#define DDRSS_CTL_126_DATA 0x00000000
+#define DDRSS_CTL_127_DATA 0x00000000
+#define DDRSS_CTL_128_DATA 0x00000000
+#define DDRSS_CTL_129_DATA 0x00000000
+#define DDRSS_CTL_130_DATA 0x00000000
+#define DDRSS_CTL_131_DATA 0x08030500
+#define DDRSS_CTL_132_DATA 0x00030803
+#define DDRSS_CTL_133_DATA 0x0A090000
+#define DDRSS_CTL_134_DATA 0x0A090701
+#define DDRSS_CTL_135_DATA 0x0900000E
+#define DDRSS_CTL_136_DATA 0x0907010A
+#define DDRSS_CTL_137_DATA 0x00000E0A
+#define DDRSS_CTL_138_DATA 0x07010A09
+#define DDRSS_CTL_139_DATA 0x000E0A09
+#define DDRSS_CTL_140_DATA 0x07000401
+#define DDRSS_CTL_141_DATA 0x00000000
+#define DDRSS_CTL_142_DATA 0x00000000
+#define DDRSS_CTL_143_DATA 0x00000000
+#define DDRSS_CTL_144_DATA 0x00000000
+#define DDRSS_CTL_145_DATA 0x00000000
+#define DDRSS_CTL_146_DATA 0x00000000
+#define DDRSS_CTL_147_DATA 0x00000000
+#define DDRSS_CTL_148_DATA 0x08080000
+#define DDRSS_CTL_149_DATA 0x01000000
+#define DDRSS_CTL_150_DATA 0x800000C0
+#define DDRSS_CTL_151_DATA 0x800000C0
+#define DDRSS_CTL_152_DATA 0x800000C0
+#define DDRSS_CTL_153_DATA 0x00000000
+#define DDRSS_CTL_154_DATA 0x00001500
+#define DDRSS_CTL_155_DATA 0x00000000
+#define DDRSS_CTL_156_DATA 0x00000001
+#define DDRSS_CTL_157_DATA 0x00000002
+#define DDRSS_CTL_158_DATA 0x0000100E
+#define DDRSS_CTL_159_DATA 0x00000000
+#define DDRSS_CTL_160_DATA 0x00000000
+#define DDRSS_CTL_161_DATA 0x00000000
+#define DDRSS_CTL_162_DATA 0x00000000
+#define DDRSS_CTL_163_DATA 0x00000000
+#define DDRSS_CTL_164_DATA 0x000B0000
+#define DDRSS_CTL_165_DATA 0x000E0006
+#define DDRSS_CTL_166_DATA 0x000E0404
+#define DDRSS_CTL_167_DATA 0x00A00140
+#define DDRSS_CTL_168_DATA 0x0C0C0190
+#define DDRSS_CTL_169_DATA 0x01400190
+#define DDRSS_CTL_170_DATA 0x019000A0
+#define DDRSS_CTL_171_DATA 0x01900C0C
+#define DDRSS_CTL_172_DATA 0x00000000
+#define DDRSS_CTL_173_DATA 0x00000000
+#define DDRSS_CTL_174_DATA 0x00000000
+#define DDRSS_CTL_175_DATA 0x2DD40084
+#define DDRSS_CTL_176_DATA 0xAB002DD4
+#define DDRSS_CTL_177_DATA 0x0000ABAB
+#define DDRSS_CTL_178_DATA 0x45450000
+#define DDRSS_CTL_179_DATA 0x27272745
+#define DDRSS_CTL_180_DATA 0x0F0F0F00
+#define DDRSS_CTL_181_DATA 0x1D000000
+#define DDRSS_CTL_182_DATA 0x00841D1D
+#define DDRSS_CTL_183_DATA 0x2DD42DD4
+#define DDRSS_CTL_184_DATA 0xABABAB00
+#define DDRSS_CTL_185_DATA 0x00000000
+#define DDRSS_CTL_186_DATA 0x27454545
+#define DDRSS_CTL_187_DATA 0x0F002727
+#define DDRSS_CTL_188_DATA 0x00000F0F
+#define DDRSS_CTL_189_DATA 0x1D1D1D00
+#define DDRSS_CTL_190_DATA 0x00000020
+#define DDRSS_CTL_191_DATA 0x00000000
+#define DDRSS_CTL_192_DATA 0x00000001
+#define DDRSS_CTL_193_DATA 0x00000000
+#define DDRSS_CTL_194_DATA 0x01000000
+#define DDRSS_CTL_195_DATA 0x00000001
+#define DDRSS_CTL_196_DATA 0x00000000
+#define DDRSS_CTL_197_DATA 0x00000000
+#define DDRSS_CTL_198_DATA 0x00000000
+#define DDRSS_CTL_199_DATA 0x00000000
+#define DDRSS_CTL_200_DATA 0x00000000
+#define DDRSS_CTL_201_DATA 0x00000000
+#define DDRSS_CTL_202_DATA 0x00000000
+#define DDRSS_CTL_203_DATA 0x00000000
+#define DDRSS_CTL_204_DATA 0x00000000
+#define DDRSS_CTL_205_DATA 0x00000000
+#define DDRSS_CTL_206_DATA 0x02000000
+#define DDRSS_CTL_207_DATA 0x01080101
+#define DDRSS_CTL_208_DATA 0x00000000
+#define DDRSS_CTL_209_DATA 0x00000000
+#define DDRSS_CTL_210_DATA 0x00000000
+#define DDRSS_CTL_211_DATA 0x00000000
+#define DDRSS_CTL_212_DATA 0x00000000
+#define DDRSS_CTL_213_DATA 0x00000000
+#define DDRSS_CTL_214_DATA 0x00000000
+#define DDRSS_CTL_215_DATA 0x00000000
+#define DDRSS_CTL_216_DATA 0x00000000
+#define DDRSS_CTL_217_DATA 0x00000000
+#define DDRSS_CTL_218_DATA 0x00000000
+#define DDRSS_CTL_219_DATA 0x00000000
+#define DDRSS_CTL_220_DATA 0x00000000
+#define DDRSS_CTL_221_DATA 0x00000000
+#define DDRSS_CTL_222_DATA 0x00001000
+#define DDRSS_CTL_223_DATA 0x006403E8
+#define DDRSS_CTL_224_DATA 0x00000000
+#define DDRSS_CTL_225_DATA 0x00000000
+#define DDRSS_CTL_226_DATA 0x00000000
+#define DDRSS_CTL_227_DATA 0x15110000
+#define DDRSS_CTL_228_DATA 0x00040C18
+#define DDRSS_CTL_229_DATA 0xF000C000
+#define DDRSS_CTL_230_DATA 0x0000F000
+#define DDRSS_CTL_231_DATA 0x00000000
+#define DDRSS_CTL_232_DATA 0x00000000
+#define DDRSS_CTL_233_DATA 0xC0000000
+#define DDRSS_CTL_234_DATA 0xF000F000
+#define DDRSS_CTL_235_DATA 0x00000000
+#define DDRSS_CTL_236_DATA 0x00000000
+#define DDRSS_CTL_237_DATA 0x00000000
+#define DDRSS_CTL_238_DATA 0xF000C000
+#define DDRSS_CTL_239_DATA 0x0000F000
+#define DDRSS_CTL_240_DATA 0x00000000
+#define DDRSS_CTL_241_DATA 0x00000000
+#define DDRSS_CTL_242_DATA 0x00030000
+#define DDRSS_CTL_243_DATA 0x00000000
+#define DDRSS_CTL_244_DATA 0x00000000
+#define DDRSS_CTL_245_DATA 0x00000000
+#define DDRSS_CTL_246_DATA 0x00000000
+#define DDRSS_CTL_247_DATA 0x00000000
+#define DDRSS_CTL_248_DATA 0x00000000
+#define DDRSS_CTL_249_DATA 0x00000000
+#define DDRSS_CTL_250_DATA 0x00000000
+#define DDRSS_CTL_251_DATA 0x00000000
+#define DDRSS_CTL_252_DATA 0x00000000
+#define DDRSS_CTL_253_DATA 0x00000000
+#define DDRSS_CTL_254_DATA 0x00000000
+#define DDRSS_CTL_255_DATA 0x00000000
+#define DDRSS_CTL_256_DATA 0x00000000
+#define DDRSS_CTL_257_DATA 0x01000200
+#define DDRSS_CTL_258_DATA 0x00370040
+#define DDRSS_CTL_259_DATA 0x00020008
+#define DDRSS_CTL_260_DATA 0x00400100
+#define DDRSS_CTL_261_DATA 0x00300640
+#define DDRSS_CTL_262_DATA 0x01000200
+#define DDRSS_CTL_263_DATA 0x06400040
+#define DDRSS_CTL_264_DATA 0x00000030
+#define DDRSS_CTL_265_DATA 0x00500003
+#define DDRSS_CTL_266_DATA 0x01000050
+#define DDRSS_CTL_267_DATA 0x03030303
+#define DDRSS_CTL_268_DATA 0x01010000
+#define DDRSS_CTL_269_DATA 0x00000202
+#define DDRSS_CTL_270_DATA 0x00000FFF
+#define DDRSS_CTL_271_DATA 0x1FFF1000
+#define DDRSS_CTL_272_DATA 0x01FF0000
+#define DDRSS_CTL_273_DATA 0x000101FF
+#define DDRSS_CTL_274_DATA 0x0FFF0B00
+#define DDRSS_CTL_275_DATA 0x01010001
+#define DDRSS_CTL_276_DATA 0x01010101
+#define DDRSS_CTL_277_DATA 0x01180101
+#define DDRSS_CTL_278_DATA 0x00030000
+#define DDRSS_CTL_279_DATA 0x00000000
+#define DDRSS_CTL_280_DATA 0x00000000
+#define DDRSS_CTL_281_DATA 0x00000000
+#define DDRSS_CTL_282_DATA 0x00000000
+#define DDRSS_CTL_283_DATA 0x00000000
+#define DDRSS_CTL_284_DATA 0x00000000
+#define DDRSS_CTL_285_DATA 0x00000000
+#define DDRSS_CTL_286_DATA 0x00040101
+#define DDRSS_CTL_287_DATA 0x04010100
+#define DDRSS_CTL_288_DATA 0x00000000
+#define DDRSS_CTL_289_DATA 0x00000000
+#define DDRSS_CTL_290_DATA 0x03030300
+#define DDRSS_CTL_291_DATA 0x00000101
+#define DDRSS_CTL_292_DATA 0x00000000
+#define DDRSS_CTL_293_DATA 0x00000000
+#define DDRSS_CTL_294_DATA 0x00000000
+#define DDRSS_CTL_295_DATA 0x00000000
+#define DDRSS_CTL_296_DATA 0x00000000
+#define DDRSS_CTL_297_DATA 0x00000000
+#define DDRSS_CTL_298_DATA 0x00000000
+#define DDRSS_CTL_299_DATA 0x00000000
+#define DDRSS_CTL_300_DATA 0x00000000
+#define DDRSS_CTL_301_DATA 0x00000000
+#define DDRSS_CTL_302_DATA 0x00000000
+#define DDRSS_CTL_303_DATA 0x00000000
+#define DDRSS_CTL_304_DATA 0x00000000
+#define DDRSS_CTL_305_DATA 0x00000000
+#define DDRSS_CTL_306_DATA 0x00000000
+#define DDRSS_CTL_307_DATA 0x00000000
+#define DDRSS_CTL_308_DATA 0x00000000
+#define DDRSS_CTL_309_DATA 0x00000000
+#define DDRSS_CTL_310_DATA 0x00000000
+#define DDRSS_CTL_311_DATA 0x00000000
+#define DDRSS_CTL_312_DATA 0x00000000
+#define DDRSS_CTL_313_DATA 0x01000000
+#define DDRSS_CTL_314_DATA 0x00020201
+#define DDRSS_CTL_315_DATA 0x01000101
+#define DDRSS_CTL_316_DATA 0x01010001
+#define DDRSS_CTL_317_DATA 0x00010101
+#define DDRSS_CTL_318_DATA 0x05080803
+#define DDRSS_CTL_319_DATA 0x0C081818
+#define DDRSS_CTL_320_DATA 0x0009030C
+#define DDRSS_CTL_321_DATA 0x090B030F
+#define DDRSS_CTL_322_DATA 0x090B0306
+#define DDRSS_CTL_323_DATA 0x0B090006
+#define DDRSS_CTL_324_DATA 0x0100000B
+#define DDRSS_CTL_325_DATA 0x06030601
+#define DDRSS_CTL_326_DATA 0x00000003
+#define DDRSS_CTL_327_DATA 0x00000000
+#define DDRSS_CTL_328_DATA 0x00010000
+#define DDRSS_CTL_329_DATA 0x00280D00
+#define DDRSS_CTL_330_DATA 0x00000001
+#define DDRSS_CTL_331_DATA 0x00030001
+#define DDRSS_CTL_332_DATA 0x00000000
+#define DDRSS_CTL_333_DATA 0x00000000
+#define DDRSS_CTL_334_DATA 0x00000000
+#define DDRSS_CTL_335_DATA 0x00000000
+#define DDRSS_CTL_336_DATA 0x00000000
+#define DDRSS_CTL_337_DATA 0x00000000
+#define DDRSS_CTL_338_DATA 0x00000000
+#define DDRSS_CTL_339_DATA 0x00000000
+#define DDRSS_CTL_340_DATA 0x01000000
+#define DDRSS_CTL_341_DATA 0x00000001
+#define DDRSS_CTL_342_DATA 0x00010100
+#define DDRSS_CTL_343_DATA 0x03030000
+#define DDRSS_CTL_344_DATA 0x00000000
+#define DDRSS_CTL_345_DATA 0x00000000
+#define DDRSS_CTL_346_DATA 0x00000000
+#define DDRSS_CTL_347_DATA 0x00000000
+#define DDRSS_CTL_348_DATA 0x00000000
+#define DDRSS_CTL_349_DATA 0x00000000
+#define DDRSS_CTL_350_DATA 0x00000000
+#define DDRSS_CTL_351_DATA 0x00000000
+#define DDRSS_CTL_352_DATA 0x00000000
+#define DDRSS_CTL_353_DATA 0x00000000
+#define DDRSS_CTL_354_DATA 0x00000000
+#define DDRSS_CTL_355_DATA 0x00000000
+#define DDRSS_CTL_356_DATA 0x00000000
+#define DDRSS_CTL_357_DATA 0x00000000
+#define DDRSS_CTL_358_DATA 0x00000000
+#define DDRSS_CTL_359_DATA 0x00000000
+#define DDRSS_CTL_360_DATA 0x000556AA
+#define DDRSS_CTL_361_DATA 0x000AAAAA
+#define DDRSS_CTL_362_DATA 0x000AA955
+#define DDRSS_CTL_363_DATA 0x00055555
+#define DDRSS_CTL_364_DATA 0x000B3133
+#define DDRSS_CTL_365_DATA 0x0004CD33
+#define DDRSS_CTL_366_DATA 0x0004CECC
+#define DDRSS_CTL_367_DATA 0x000B32CC
+#define DDRSS_CTL_368_DATA 0x00010300
+#define DDRSS_CTL_369_DATA 0x03000100
+#define DDRSS_CTL_370_DATA 0x00000000
+#define DDRSS_CTL_371_DATA 0x00000000
+#define DDRSS_CTL_372_DATA 0x00000000
+#define DDRSS_CTL_373_DATA 0x00000000
+#define DDRSS_CTL_374_DATA 0x00000000
+#define DDRSS_CTL_375_DATA 0x00000000
+#define DDRSS_CTL_376_DATA 0x00000000
+#define DDRSS_CTL_377_DATA 0x00010000
+#define DDRSS_CTL_378_DATA 0x00000404
+#define DDRSS_CTL_379_DATA 0x00000000
+#define DDRSS_CTL_380_DATA 0x00000000
+#define DDRSS_CTL_381_DATA 0x00000000
+#define DDRSS_CTL_382_DATA 0x00000000
+#define DDRSS_CTL_383_DATA 0x00000000
+#define DDRSS_CTL_384_DATA 0x00000000
+#define DDRSS_CTL_385_DATA 0x00000000
+#define DDRSS_CTL_386_DATA 0x00000000
+#define DDRSS_CTL_387_DATA 0x33331B00
+#define DDRSS_CTL_388_DATA 0x000A0000
+#define DDRSS_CTL_389_DATA 0x0000019C
+#define DDRSS_CTL_390_DATA 0x00000200
+#define DDRSS_CTL_391_DATA 0x00000200
+#define DDRSS_CTL_392_DATA 0x00000200
+#define DDRSS_CTL_393_DATA 0x00000200
+#define DDRSS_CTL_394_DATA 0x000004D4
+#define DDRSS_CTL_395_DATA 0x00001018
+#define DDRSS_CTL_396_DATA 0x00000204
+#define DDRSS_CTL_397_DATA 0x000030B0
+#define DDRSS_CTL_398_DATA 0x00000200
+#define DDRSS_CTL_399_DATA 0x00000200
+#define DDRSS_CTL_400_DATA 0x00000200
+#define DDRSS_CTL_401_DATA 0x00000200
+#define DDRSS_CTL_402_DATA 0x00009210
+#define DDRSS_CTL_403_DATA 0x0001E6E0
+#define DDRSS_CTL_404_DATA 0x00000A10
+#define DDRSS_CTL_405_DATA 0x000030B0
+#define DDRSS_CTL_406_DATA 0x00000200
+#define DDRSS_CTL_407_DATA 0x00000200
+#define DDRSS_CTL_408_DATA 0x00000200
+#define DDRSS_CTL_409_DATA 0x00000200
+#define DDRSS_CTL_410_DATA 0x00009210
+#define DDRSS_CTL_411_DATA 0x0001E6E0
+#define DDRSS_CTL_412_DATA 0x02020A10
+#define DDRSS_CTL_413_DATA 0x03030202
+#define DDRSS_CTL_414_DATA 0x00000022
+#define DDRSS_CTL_415_DATA 0x00000000
+#define DDRSS_CTL_416_DATA 0x00000000
+#define DDRSS_CTL_417_DATA 0x00001403
+#define DDRSS_CTL_418_DATA 0x000007D0
+#define DDRSS_CTL_419_DATA 0x00000000
+#define DDRSS_CTL_420_DATA 0x00000000
+#define DDRSS_CTL_421_DATA 0x00030000
+#define DDRSS_CTL_422_DATA 0x0007001F
+#define DDRSS_CTL_423_DATA 0x0016002E
+#define DDRSS_CTL_424_DATA 0x0016002E
+#define DDRSS_CTL_425_DATA 0x00000000
+#define DDRSS_CTL_426_DATA 0x00000000
+#define DDRSS_CTL_427_DATA 0x02000000
+#define DDRSS_CTL_428_DATA 0x01000404
+#define DDRSS_CTL_429_DATA 0x07160716
+#define DDRSS_CTL_430_DATA 0x00000105
+#define DDRSS_CTL_431_DATA 0x00010101
+#define DDRSS_CTL_432_DATA 0x00010101
+#define DDRSS_CTL_433_DATA 0x00010001
+#define DDRSS_CTL_434_DATA 0x00000101
+#define DDRSS_CTL_435_DATA 0x02000201
+#define DDRSS_CTL_436_DATA 0x02010000
+#define DDRSS_CTL_437_DATA 0x00000200
+#define DDRSS_CTL_438_DATA 0x1E060000
+#define DDRSS_CTL_439_DATA 0x0000011E
+#define DDRSS_CTL_440_DATA 0xFFFFFFFF
+#define DDRSS_CTL_441_DATA 0xFFFFFFFF
+#define DDRSS_CTL_442_DATA 0x00000000
+#define DDRSS_CTL_443_DATA 0x00000000
+#define DDRSS_CTL_444_DATA 0x00000000
+#define DDRSS_CTL_445_DATA 0x00000000
+#define DDRSS_CTL_446_DATA 0x00000000
+#define DDRSS_CTL_447_DATA 0x00000000
+#define DDRSS_CTL_448_DATA 0x00000000
+#define DDRSS_CTL_449_DATA 0x00000000
+#define DDRSS_CTL_450_DATA 0x00000000
+#define DDRSS_CTL_451_DATA 0x00000000
+#define DDRSS_CTL_452_DATA 0x00000000
+#define DDRSS_CTL_453_DATA 0x00000000
+#define DDRSS_CTL_454_DATA 0x00000000
+#define DDRSS_CTL_455_DATA 0x00000000
+#define DDRSS_CTL_456_DATA 0x00000000
+#define DDRSS_CTL_457_DATA 0x00000000
+#define DDRSS_CTL_458_DATA 0x00000000
+
+#define DDRSS_PI_00_DATA 0x00000B00
+#define DDRSS_PI_01_DATA 0x00000000
+#define DDRSS_PI_02_DATA 0x00000000
+#define DDRSS_PI_03_DATA 0x00000000
+#define DDRSS_PI_04_DATA 0x00000000
+#define DDRSS_PI_05_DATA 0x00000101
+#define DDRSS_PI_06_DATA 0x00640000
+#define DDRSS_PI_07_DATA 0x00000001
+#define DDRSS_PI_08_DATA 0x00000000
+#define DDRSS_PI_09_DATA 0x00000000
+#define DDRSS_PI_10_DATA 0x00000000
+#define DDRSS_PI_11_DATA 0x00000000
+#define DDRSS_PI_12_DATA 0x00000007
+#define DDRSS_PI_13_DATA 0x00010002
+#define DDRSS_PI_14_DATA 0x0800000F
+#define DDRSS_PI_15_DATA 0x00000103
+#define DDRSS_PI_16_DATA 0x00000005
+#define DDRSS_PI_17_DATA 0x00000000
+#define DDRSS_PI_18_DATA 0x00000000
+#define DDRSS_PI_19_DATA 0x00000000
+#define DDRSS_PI_20_DATA 0x00000000
+#define DDRSS_PI_21_DATA 0x00000000
+#define DDRSS_PI_22_DATA 0x00000000
+#define DDRSS_PI_23_DATA 0x00000000
+#define DDRSS_PI_24_DATA 0x00000000
+#define DDRSS_PI_25_DATA 0x00000000
+#define DDRSS_PI_26_DATA 0x00010100
+#define DDRSS_PI_27_DATA 0x00280A00
+#define DDRSS_PI_28_DATA 0x00000000
+#define DDRSS_PI_29_DATA 0x0F000000
+#define DDRSS_PI_30_DATA 0x00003200
+#define DDRSS_PI_31_DATA 0x00000000
+#define DDRSS_PI_32_DATA 0x00000000
+#define DDRSS_PI_33_DATA 0x01010102
+#define DDRSS_PI_34_DATA 0x00000000
+#define DDRSS_PI_35_DATA 0x000000AA
+#define DDRSS_PI_36_DATA 0x00000055
+#define DDRSS_PI_37_DATA 0x000000B5
+#define DDRSS_PI_38_DATA 0x0000004A
+#define DDRSS_PI_39_DATA 0x00000056
+#define DDRSS_PI_40_DATA 0x000000A9
+#define DDRSS_PI_41_DATA 0x000000A9
+#define DDRSS_PI_42_DATA 0x000000B5
+#define DDRSS_PI_43_DATA 0x00000000
+#define DDRSS_PI_44_DATA 0x00000000
+#define DDRSS_PI_45_DATA 0x000F0F00
+#define DDRSS_PI_46_DATA 0x00000019
+#define DDRSS_PI_47_DATA 0x000007D0
+#define DDRSS_PI_48_DATA 0x00000300
+#define DDRSS_PI_49_DATA 0x00000000
+#define DDRSS_PI_50_DATA 0x00000000
+#define DDRSS_PI_51_DATA 0x01000000
+#define DDRSS_PI_52_DATA 0x00010101
+#define DDRSS_PI_53_DATA 0x00000000
+#define DDRSS_PI_54_DATA 0x00030000
+#define DDRSS_PI_55_DATA 0x0F000000
+#define DDRSS_PI_56_DATA 0x00000017
+#define DDRSS_PI_57_DATA 0x00000000
+#define DDRSS_PI_58_DATA 0x00000000
+#define DDRSS_PI_59_DATA 0x00000000
+#define DDRSS_PI_60_DATA 0x0A0A140A
+#define DDRSS_PI_61_DATA 0x10020101
+#define DDRSS_PI_62_DATA 0x00020805
+#define DDRSS_PI_63_DATA 0x01000404
+#define DDRSS_PI_64_DATA 0x00000000
+#define DDRSS_PI_65_DATA 0x00000000
+#define DDRSS_PI_66_DATA 0x00000100
+#define DDRSS_PI_67_DATA 0x0001010F
+#define DDRSS_PI_68_DATA 0x00340000
+#define DDRSS_PI_69_DATA 0x00000000
+#define DDRSS_PI_70_DATA 0x00000000
+#define DDRSS_PI_71_DATA 0x0000FFFF
+#define DDRSS_PI_72_DATA 0x00000000
+#define DDRSS_PI_73_DATA 0x00080100
+#define DDRSS_PI_74_DATA 0x02000200
+#define DDRSS_PI_75_DATA 0x01000100
+#define DDRSS_PI_76_DATA 0x01000000
+#define DDRSS_PI_77_DATA 0x02000200
+#define DDRSS_PI_78_DATA 0x00000200
+#define DDRSS_PI_79_DATA 0x00000000
+#define DDRSS_PI_80_DATA 0x00000000
+#define DDRSS_PI_81_DATA 0x00000000
+#define DDRSS_PI_82_DATA 0x00000000
+#define DDRSS_PI_83_DATA 0x00000000
+#define DDRSS_PI_84_DATA 0x00000000
+#define DDRSS_PI_85_DATA 0x00000000
+#define DDRSS_PI_86_DATA 0x00000000
+#define DDRSS_PI_87_DATA 0x00000000
+#define DDRSS_PI_88_DATA 0x00000000
+#define DDRSS_PI_89_DATA 0x00000000
+#define DDRSS_PI_90_DATA 0x00000000
+#define DDRSS_PI_91_DATA 0x00000400
+#define DDRSS_PI_92_DATA 0x02010000
+#define DDRSS_PI_93_DATA 0x00080003
+#define DDRSS_PI_94_DATA 0x00080000
+#define DDRSS_PI_95_DATA 0x00000001
+#define DDRSS_PI_96_DATA 0x00000000
+#define DDRSS_PI_97_DATA 0x0000AA00
+#define DDRSS_PI_98_DATA 0x00000000
+#define DDRSS_PI_99_DATA 0x00000000
+#define DDRSS_PI_100_DATA 0x00010000
+#define DDRSS_PI_101_DATA 0x00000000
+#define DDRSS_PI_102_DATA 0x00000000
+#define DDRSS_PI_103_DATA 0x00000000
+#define DDRSS_PI_104_DATA 0x00000000
+#define DDRSS_PI_105_DATA 0x00000000
+#define DDRSS_PI_106_DATA 0x00000000
+#define DDRSS_PI_107_DATA 0x00000000
+#define DDRSS_PI_108_DATA 0x00000000
+#define DDRSS_PI_109_DATA 0x00000000
+#define DDRSS_PI_110_DATA 0x00000000
+#define DDRSS_PI_111_DATA 0x00000000
+#define DDRSS_PI_112_DATA 0x00000000
+#define DDRSS_PI_113_DATA 0x00000000
+#define DDRSS_PI_114_DATA 0x00000000
+#define DDRSS_PI_115_DATA 0x00000000
+#define DDRSS_PI_116_DATA 0x00000000
+#define DDRSS_PI_117_DATA 0x00000000
+#define DDRSS_PI_118_DATA 0x00000000
+#define DDRSS_PI_119_DATA 0x00000000
+#define DDRSS_PI_120_DATA 0x00000000
+#define DDRSS_PI_121_DATA 0x00000000
+#define DDRSS_PI_122_DATA 0x00000000
+#define DDRSS_PI_123_DATA 0x00000000
+#define DDRSS_PI_124_DATA 0x00000000
+#define DDRSS_PI_125_DATA 0x00000008
+#define DDRSS_PI_126_DATA 0x00000000
+#define DDRSS_PI_127_DATA 0x00000000
+#define DDRSS_PI_128_DATA 0x00000000
+#define DDRSS_PI_129_DATA 0x00000000
+#define DDRSS_PI_130_DATA 0x00000000
+#define DDRSS_PI_131_DATA 0x00000000
+#define DDRSS_PI_132_DATA 0x00000000
+#define DDRSS_PI_133_DATA 0x00000000
+#define DDRSS_PI_134_DATA 0x00000002
+#define DDRSS_PI_135_DATA 0x00000000
+#define DDRSS_PI_136_DATA 0x00000000
+#define DDRSS_PI_137_DATA 0x0000000A
+#define DDRSS_PI_138_DATA 0x00000019
+#define DDRSS_PI_139_DATA 0x00000100
+#define DDRSS_PI_140_DATA 0x00000000
+#define DDRSS_PI_141_DATA 0x00000000
+#define DDRSS_PI_142_DATA 0x00000000
+#define DDRSS_PI_143_DATA 0x00000000
+#define DDRSS_PI_144_DATA 0x01000000
+#define DDRSS_PI_145_DATA 0x00010003
+#define DDRSS_PI_146_DATA 0x02000101
+#define DDRSS_PI_147_DATA 0x01030001
+#define DDRSS_PI_148_DATA 0x00010400
+#define DDRSS_PI_149_DATA 0x06000105
+#define DDRSS_PI_150_DATA 0x01070001
+#define DDRSS_PI_151_DATA 0x00000000
+#define DDRSS_PI_152_DATA 0x00000000
+#define DDRSS_PI_153_DATA 0x00000000
+#define DDRSS_PI_154_DATA 0x00010001
+#define DDRSS_PI_155_DATA 0x00000000
+#define DDRSS_PI_156_DATA 0x00000000
+#define DDRSS_PI_157_DATA 0x00000000
+#define DDRSS_PI_158_DATA 0x00000000
+#define DDRSS_PI_159_DATA 0x00000401
+#define DDRSS_PI_160_DATA 0x00000000
+#define DDRSS_PI_161_DATA 0x00010000
+#define DDRSS_PI_162_DATA 0x00000000
+#define DDRSS_PI_163_DATA 0x20200200
+#define DDRSS_PI_164_DATA 0x00000034
+#define DDRSS_PI_165_DATA 0x00000058
+#define DDRSS_PI_166_DATA 0x00020058
+#define DDRSS_PI_167_DATA 0x02000200
+#define DDRSS_PI_168_DATA 0x380E0C04
+#define DDRSS_PI_169_DATA 0x0010380E
+#define DDRSS_PI_170_DATA 0x000000CE
+#define DDRSS_PI_171_DATA 0x000001C0
+#define DDRSS_PI_172_DATA 0x00001858
+#define DDRSS_PI_173_DATA 0x000001C0
+#define DDRSS_PI_174_DATA 0x04001858
+#define DDRSS_PI_175_DATA 0x01010404
+#define DDRSS_PI_176_DATA 0x00001501
+#define DDRSS_PI_177_DATA 0x00150015
+#define DDRSS_PI_178_DATA 0x01000100
+#define DDRSS_PI_179_DATA 0x00000100
+#define DDRSS_PI_180_DATA 0x00000000
+#define DDRSS_PI_181_DATA 0x01010101
+#define DDRSS_PI_182_DATA 0x00000101
+#define DDRSS_PI_183_DATA 0x00000000
+#define DDRSS_PI_184_DATA 0x00000000
+#define DDRSS_PI_185_DATA 0x10040000
+#define DDRSS_PI_186_DATA 0x0A0A0210
+#define DDRSS_PI_187_DATA 0x00040402
+#define DDRSS_PI_188_DATA 0x000D0035
+#define DDRSS_PI_189_DATA 0x001C0044
+#define DDRSS_PI_190_DATA 0x001C0044
+#define DDRSS_PI_191_DATA 0x01010101
+#define DDRSS_PI_192_DATA 0x0003000E
+#define DDRSS_PI_193_DATA 0x00030190
+#define DDRSS_PI_194_DATA 0x01000190
+#define DDRSS_PI_195_DATA 0x000F000F
+#define DDRSS_PI_196_DATA 0x01910100
+#define DDRSS_PI_197_DATA 0x01000191
+#define DDRSS_PI_198_DATA 0x01910191
+#define DDRSS_PI_199_DATA 0x32103200
+#define DDRSS_PI_200_DATA 0x01013210
+#define DDRSS_PI_201_DATA 0x0A070601
+#define DDRSS_PI_202_DATA 0x180F090D
+#define DDRSS_PI_203_DATA 0x180F0911
+#define DDRSS_PI_204_DATA 0x0000C011
+#define DDRSS_PI_205_DATA 0x00C01000
+#define DDRSS_PI_206_DATA 0x00C01000
+#define DDRSS_PI_207_DATA 0x00021000
+#define DDRSS_PI_208_DATA 0x001E000E
+#define DDRSS_PI_209_DATA 0x001E0190
+#define DDRSS_PI_210_DATA 0x00110190
+#define DDRSS_PI_211_DATA 0x32000056
+#define DDRSS_PI_212_DATA 0x00000301
+#define DDRSS_PI_213_DATA 0x005A0030
+#define DDRSS_PI_214_DATA 0x03013212
+#define DDRSS_PI_215_DATA 0x00003000
+#define DDRSS_PI_216_DATA 0x3212005A
+#define DDRSS_PI_217_DATA 0x09000301
+#define DDRSS_PI_218_DATA 0x04010504
+#define DDRSS_PI_219_DATA 0x040006C9
+#define DDRSS_PI_220_DATA 0x0A032001
+#define DDRSS_PI_221_DATA 0x21250D0A
+#define DDRSS_PI_222_DATA 0x00002216
+#define DDRSS_PI_223_DATA 0x4800C570
+#define DDRSS_PI_224_DATA 0x17182006
+#define DDRSS_PI_225_DATA 0x21250D10
+#define DDRSS_PI_226_DATA 0x00002216
+#define DDRSS_PI_227_DATA 0x4800C570
+#define DDRSS_PI_228_DATA 0x17182006
+#define DDRSS_PI_229_DATA 0x00019C10
+#define DDRSS_PI_230_DATA 0x00001018
+#define DDRSS_PI_231_DATA 0x000030B0
+#define DDRSS_PI_232_DATA 0x0001E6E0
+#define DDRSS_PI_233_DATA 0x000030B0
+#define DDRSS_PI_234_DATA 0x0001E6E0
+#define DDRSS_PI_235_DATA 0x01CC0010
+#define DDRSS_PI_236_DATA 0x030301CC
+#define DDRSS_PI_237_DATA 0x002AF803
+#define DDRSS_PI_238_DATA 0x0001ADAF
+#define DDRSS_PI_239_DATA 0x00000005
+#define DDRSS_PI_240_DATA 0x0000006E
+#define DDRSS_PI_241_DATA 0x00000010
+#define DDRSS_PI_242_DATA 0x0004E200
+#define DDRSS_PI_243_DATA 0x0001ADAF
+#define DDRSS_PI_244_DATA 0x00000005
+#define DDRSS_PI_245_DATA 0x00000C80
+#define DDRSS_PI_246_DATA 0x000001CC
+#define DDRSS_PI_247_DATA 0x0004E200
+#define DDRSS_PI_248_DATA 0x0001ADAF
+#define DDRSS_PI_249_DATA 0x00000005
+#define DDRSS_PI_250_DATA 0x00000C80
+#define DDRSS_PI_251_DATA 0x010001CC
+#define DDRSS_PI_252_DATA 0x00370040
+#define DDRSS_PI_253_DATA 0x00010008
+#define DDRSS_PI_254_DATA 0x06400040
+#define DDRSS_PI_255_DATA 0x00010030
+#define DDRSS_PI_256_DATA 0x06400040
+#define DDRSS_PI_257_DATA 0x00000330
+#define DDRSS_PI_258_DATA 0x00500050
+#define DDRSS_PI_259_DATA 0x08040404
+#define DDRSS_PI_260_DATA 0x00000055
+#define DDRSS_PI_261_DATA 0x55083C5A
+#define DDRSS_PI_262_DATA 0x5A000000
+#define DDRSS_PI_263_DATA 0x0055083C
+#define DDRSS_PI_264_DATA 0x3C5A0000
+#define DDRSS_PI_265_DATA 0x00005508
+#define DDRSS_PI_266_DATA 0x0C3C5A00
+#define DDRSS_PI_267_DATA 0x080F0E0D
+#define DDRSS_PI_268_DATA 0x000B0A09
+#define DDRSS_PI_269_DATA 0x00030201
+#define DDRSS_PI_270_DATA 0x01000000
+#define DDRSS_PI_271_DATA 0x04020201
+#define DDRSS_PI_272_DATA 0x00080804
+#define DDRSS_PI_273_DATA 0x00000000
+#define DDRSS_PI_274_DATA 0x00000000
+#define DDRSS_PI_275_DATA 0x45AB0084
+#define DDRSS_PI_276_DATA 0x001D0F27
+#define DDRSS_PI_277_DATA 0x45AB2DD4
+#define DDRSS_PI_278_DATA 0x001D0F27
+#define DDRSS_PI_279_DATA 0x45AB2DD4
+#define DDRSS_PI_280_DATA 0x001D0F27
+#define DDRSS_PI_281_DATA 0x45AB0084
+#define DDRSS_PI_282_DATA 0x001D0F27
+#define DDRSS_PI_283_DATA 0x45AB2DD4
+#define DDRSS_PI_284_DATA 0x001D0F27
+#define DDRSS_PI_285_DATA 0x45AB2DD4
+#define DDRSS_PI_286_DATA 0x001D0F27
+#define DDRSS_PI_287_DATA 0x45AB0084
+#define DDRSS_PI_288_DATA 0x001D0F27
+#define DDRSS_PI_289_DATA 0x45AB2DD4
+#define DDRSS_PI_290_DATA 0x001D0F27
+#define DDRSS_PI_291_DATA 0x45AB2DD4
+#define DDRSS_PI_292_DATA 0x001D0F27
+#define DDRSS_PI_293_DATA 0x45AB0084
+#define DDRSS_PI_294_DATA 0x001D0F27
+#define DDRSS_PI_295_DATA 0x45AB2DD4
+#define DDRSS_PI_296_DATA 0x001D0F27
+#define DDRSS_PI_297_DATA 0x45AB2DD4
+#define DDRSS_PI_298_DATA 0x001D0F27
+#define DDRSS_PI_299_DATA 0x00000000
+
+#define DDRSS_PHY_00_DATA 0x000004F0
+#define DDRSS_PHY_01_DATA 0x00000000
+#define DDRSS_PHY_02_DATA 0x00030200
+#define DDRSS_PHY_03_DATA 0x00000000
+#define DDRSS_PHY_04_DATA 0x00000000
+#define DDRSS_PHY_05_DATA 0x01030000
+#define DDRSS_PHY_06_DATA 0x00010000
+#define DDRSS_PHY_07_DATA 0x01030004
+#define DDRSS_PHY_08_DATA 0x01000000
+#define DDRSS_PHY_09_DATA 0x00000000
+#define DDRSS_PHY_10_DATA 0x00000000
+#define DDRSS_PHY_11_DATA 0x01000001
+#define DDRSS_PHY_12_DATA 0x00000100
+#define DDRSS_PHY_13_DATA 0x000800C0
+#define DDRSS_PHY_14_DATA 0x060100CC
+#define DDRSS_PHY_15_DATA 0x00030066
+#define DDRSS_PHY_16_DATA 0x00000000
+#define DDRSS_PHY_17_DATA 0x00000301
+#define DDRSS_PHY_18_DATA 0x0000AAAA
+#define DDRSS_PHY_19_DATA 0x00005555
+#define DDRSS_PHY_20_DATA 0x0000B5B5
+#define DDRSS_PHY_21_DATA 0x00004A4A
+#define DDRSS_PHY_22_DATA 0x00005656
+#define DDRSS_PHY_23_DATA 0x0000A9A9
+#define DDRSS_PHY_24_DATA 0x0000A9A9
+#define DDRSS_PHY_25_DATA 0x0000B5B5
+#define DDRSS_PHY_26_DATA 0x00000000
+#define DDRSS_PHY_27_DATA 0x00000000
+#define DDRSS_PHY_28_DATA 0x2A000000
+#define DDRSS_PHY_29_DATA 0x00000808
+#define DDRSS_PHY_30_DATA 0x0F000000
+#define DDRSS_PHY_31_DATA 0x00000F0F
+#define DDRSS_PHY_32_DATA 0x10400000
+#define DDRSS_PHY_33_DATA 0x0C002006
+#define DDRSS_PHY_34_DATA 0x00000000
+#define DDRSS_PHY_35_DATA 0x00000000
+#define DDRSS_PHY_36_DATA 0x55555555
+#define DDRSS_PHY_37_DATA 0xAAAAAAAA
+#define DDRSS_PHY_38_DATA 0x55555555
+#define DDRSS_PHY_39_DATA 0xAAAAAAAA
+#define DDRSS_PHY_40_DATA 0x00005555
+#define DDRSS_PHY_41_DATA 0x01000100
+#define DDRSS_PHY_42_DATA 0x00800180
+#define DDRSS_PHY_43_DATA 0x00000001
+#define DDRSS_PHY_44_DATA 0x00000000
+#define DDRSS_PHY_45_DATA 0x00000000
+#define DDRSS_PHY_46_DATA 0x00000000
+#define DDRSS_PHY_47_DATA 0x00000000
+#define DDRSS_PHY_48_DATA 0x00000000
+#define DDRSS_PHY_49_DATA 0x00000000
+#define DDRSS_PHY_50_DATA 0x00000000
+#define DDRSS_PHY_51_DATA 0x00000000
+#define DDRSS_PHY_52_DATA 0x00000000
+#define DDRSS_PHY_53_DATA 0x00000000
+#define DDRSS_PHY_54_DATA 0x00000000
+#define DDRSS_PHY_55_DATA 0x00000000
+#define DDRSS_PHY_56_DATA 0x00000000
+#define DDRSS_PHY_57_DATA 0x00000000
+#define DDRSS_PHY_58_DATA 0x00000000
+#define DDRSS_PHY_59_DATA 0x00000000
+#define DDRSS_PHY_60_DATA 0x00000000
+#define DDRSS_PHY_61_DATA 0x00000000
+#define DDRSS_PHY_62_DATA 0x00000000
+#define DDRSS_PHY_63_DATA 0x00000000
+#define DDRSS_PHY_64_DATA 0x00000000
+#define DDRSS_PHY_65_DATA 0x00000000
+#define DDRSS_PHY_66_DATA 0x00000104
+#define DDRSS_PHY_67_DATA 0x00000120
+#define DDRSS_PHY_68_DATA 0x00000000
+#define DDRSS_PHY_69_DATA 0x00000000
+#define DDRSS_PHY_70_DATA 0x00000000
+#define DDRSS_PHY_71_DATA 0x00000000
+#define DDRSS_PHY_72_DATA 0x00000000
+#define DDRSS_PHY_73_DATA 0x00000000
+#define DDRSS_PHY_74_DATA 0x00000000
+#define DDRSS_PHY_75_DATA 0x00000001
+#define DDRSS_PHY_76_DATA 0x07FF0000
+#define DDRSS_PHY_77_DATA 0x0080081F
+#define DDRSS_PHY_78_DATA 0x00081020
+#define DDRSS_PHY_79_DATA 0x04010000
+#define DDRSS_PHY_80_DATA 0x00000000
+#define DDRSS_PHY_81_DATA 0x00000000
+#define DDRSS_PHY_82_DATA 0x00000000
+#define DDRSS_PHY_83_DATA 0x00000100
+#define DDRSS_PHY_84_DATA 0x01BB0B01
+#define DDRSS_PHY_85_DATA 0x1003BB0B
+#define DDRSS_PHY_86_DATA 0x20000140
+#define DDRSS_PHY_87_DATA 0x07FF0200
+#define DDRSS_PHY_88_DATA 0x0000DD01
+#define DDRSS_PHY_89_DATA 0x10100303
+#define DDRSS_PHY_90_DATA 0x10101010
+#define DDRSS_PHY_91_DATA 0x10101010
+#define DDRSS_PHY_92_DATA 0x00021010
+#define DDRSS_PHY_93_DATA 0x00100010
+#define DDRSS_PHY_94_DATA 0x00100010
+#define DDRSS_PHY_95_DATA 0x00100010
+#define DDRSS_PHY_96_DATA 0x00100010
+#define DDRSS_PHY_97_DATA 0x00050010
+#define DDRSS_PHY_98_DATA 0x51517041
+#define DDRSS_PHY_99_DATA 0x31C06000
+#define DDRSS_PHY_100_DATA 0x07AB0340
+#define DDRSS_PHY_101_DATA 0x00C0C001
+#define DDRSS_PHY_102_DATA 0x0B0A0001
+#define DDRSS_PHY_103_DATA 0x10001000
+#define DDRSS_PHY_104_DATA 0x0C073E42
+#define DDRSS_PHY_105_DATA 0x0F0C2D01
+#define DDRSS_PHY_106_DATA 0x01000140
+#define DDRSS_PHY_107_DATA 0x0C000420
+#define DDRSS_PHY_108_DATA 0x00000198
+#define DDRSS_PHY_109_DATA 0x0A0000D0
+#define DDRSS_PHY_110_DATA 0x00030200
+#define DDRSS_PHY_111_DATA 0x02800000
+#define DDRSS_PHY_112_DATA 0x80800000
+#define DDRSS_PHY_113_DATA 0x000B2010
+#define DDRSS_PHY_114_DATA 0x76543210
+#define DDRSS_PHY_115_DATA 0x00000008
+#define DDRSS_PHY_116_DATA 0x02800280
+#define DDRSS_PHY_117_DATA 0x02800280
+#define DDRSS_PHY_118_DATA 0x02800280
+#define DDRSS_PHY_119_DATA 0x02800280
+#define DDRSS_PHY_120_DATA 0x00000280
+#define DDRSS_PHY_121_DATA 0x0000A000
+#define DDRSS_PHY_122_DATA 0x00A000A0
+#define DDRSS_PHY_123_DATA 0x00A000A0
+#define DDRSS_PHY_124_DATA 0x00A000A0
+#define DDRSS_PHY_125_DATA 0x00A000A0
+#define DDRSS_PHY_126_DATA 0x00A000A0
+#define DDRSS_PHY_127_DATA 0x00A000A0
+#define DDRSS_PHY_128_DATA 0x00A000A0
+#define DDRSS_PHY_129_DATA 0x00A000A0
+#define DDRSS_PHY_130_DATA 0x011900A0
+#define DDRSS_PHY_131_DATA 0x01A00004
+#define DDRSS_PHY_132_DATA 0x00000000
+#define DDRSS_PHY_133_DATA 0x00000000
+#define DDRSS_PHY_134_DATA 0x00080200
+#define DDRSS_PHY_135_DATA 0x00000000
+#define DDRSS_PHY_136_DATA 0x20202000
+#define DDRSS_PHY_137_DATA 0x20202020
+#define DDRSS_PHY_138_DATA 0xF0F02020
+#define DDRSS_PHY_139_DATA 0x00000000
+#define DDRSS_PHY_140_DATA 0x00000000
+#define DDRSS_PHY_141_DATA 0x00000000
+#define DDRSS_PHY_142_DATA 0x00000000
+#define DDRSS_PHY_143_DATA 0x00000000
+#define DDRSS_PHY_144_DATA 0x00000000
+#define DDRSS_PHY_145_DATA 0x00000000
+#define DDRSS_PHY_146_DATA 0x00000000
+#define DDRSS_PHY_147_DATA 0x00000000
+#define DDRSS_PHY_148_DATA 0x00000000
+#define DDRSS_PHY_149_DATA 0x00000000
+#define DDRSS_PHY_150_DATA 0x00000000
+#define DDRSS_PHY_151_DATA 0x00000000
+#define DDRSS_PHY_152_DATA 0x00000000
+#define DDRSS_PHY_153_DATA 0x00000000
+#define DDRSS_PHY_154_DATA 0x00000000
+#define DDRSS_PHY_155_DATA 0x00000000
+#define DDRSS_PHY_156_DATA 0x00000000
+#define DDRSS_PHY_157_DATA 0x00000000
+#define DDRSS_PHY_158_DATA 0x00000000
+#define DDRSS_PHY_159_DATA 0x00000000
+#define DDRSS_PHY_160_DATA 0x00000000
+#define DDRSS_PHY_161_DATA 0x00000000
+#define DDRSS_PHY_162_DATA 0x00000000
+#define DDRSS_PHY_163_DATA 0x00000000
+#define DDRSS_PHY_164_DATA 0x00000000
+#define DDRSS_PHY_165_DATA 0x00000000
+#define DDRSS_PHY_166_DATA 0x00000000
+#define DDRSS_PHY_167_DATA 0x00000000
+#define DDRSS_PHY_168_DATA 0x00000000
+#define DDRSS_PHY_169_DATA 0x00000000
+#define DDRSS_PHY_170_DATA 0x00000000
+#define DDRSS_PHY_171_DATA 0x00000000
+#define DDRSS_PHY_172_DATA 0x00000000
+#define DDRSS_PHY_173_DATA 0x00000000
+#define DDRSS_PHY_174_DATA 0x00000000
+#define DDRSS_PHY_175_DATA 0x00000000
+#define DDRSS_PHY_176_DATA 0x00000000
+#define DDRSS_PHY_177_DATA 0x00000000
+#define DDRSS_PHY_178_DATA 0x00000000
+#define DDRSS_PHY_179_DATA 0x00000000
+#define DDRSS_PHY_180_DATA 0x00000000
+#define DDRSS_PHY_181_DATA 0x00000000
+#define DDRSS_PHY_182_DATA 0x00000000
+#define DDRSS_PHY_183_DATA 0x00000000
+#define DDRSS_PHY_184_DATA 0x00000000
+#define DDRSS_PHY_185_DATA 0x00000000
+#define DDRSS_PHY_186_DATA 0x00000000
+#define DDRSS_PHY_187_DATA 0x00000000
+#define DDRSS_PHY_188_DATA 0x00000000
+#define DDRSS_PHY_189_DATA 0x00000000
+#define DDRSS_PHY_190_DATA 0x00000000
+#define DDRSS_PHY_191_DATA 0x00000000
+#define DDRSS_PHY_192_DATA 0x00000000
+#define DDRSS_PHY_193_DATA 0x00000000
+#define DDRSS_PHY_194_DATA 0x00000000
+#define DDRSS_PHY_195_DATA 0x00000000
+#define DDRSS_PHY_196_DATA 0x00000000
+#define DDRSS_PHY_197_DATA 0x00000000
+#define DDRSS_PHY_198_DATA 0x00000000
+#define DDRSS_PHY_199_DATA 0x00000000
+#define DDRSS_PHY_200_DATA 0x00000000
+#define DDRSS_PHY_201_DATA 0x00000000
+#define DDRSS_PHY_202_DATA 0x00000000
+#define DDRSS_PHY_203_DATA 0x00000000
+#define DDRSS_PHY_204_DATA 0x00000000
+#define DDRSS_PHY_205_DATA 0x00000000
+#define DDRSS_PHY_206_DATA 0x00000000
+#define DDRSS_PHY_207_DATA 0x00000000
+#define DDRSS_PHY_208_DATA 0x00000000
+#define DDRSS_PHY_209_DATA 0x00000000
+#define DDRSS_PHY_210_DATA 0x00000000
+#define DDRSS_PHY_211_DATA 0x00000000
+#define DDRSS_PHY_212_DATA 0x00000000
+#define DDRSS_PHY_213_DATA 0x00000000
+#define DDRSS_PHY_214_DATA 0x00000000
+#define DDRSS_PHY_215_DATA 0x00000000
+#define DDRSS_PHY_216_DATA 0x00000000
+#define DDRSS_PHY_217_DATA 0x00000000
+#define DDRSS_PHY_218_DATA 0x00000000
+#define DDRSS_PHY_219_DATA 0x00000000
+#define DDRSS_PHY_220_DATA 0x00000000
+#define DDRSS_PHY_221_DATA 0x00000000
+#define DDRSS_PHY_222_DATA 0x00000000
+#define DDRSS_PHY_223_DATA 0x00000000
+#define DDRSS_PHY_224_DATA 0x00000000
+#define DDRSS_PHY_225_DATA 0x00000000
+#define DDRSS_PHY_226_DATA 0x00000000
+#define DDRSS_PHY_227_DATA 0x00000000
+#define DDRSS_PHY_228_DATA 0x00000000
+#define DDRSS_PHY_229_DATA 0x00000000
+#define DDRSS_PHY_230_DATA 0x00000000
+#define DDRSS_PHY_231_DATA 0x00000000
+#define DDRSS_PHY_232_DATA 0x00000000
+#define DDRSS_PHY_233_DATA 0x00000000
+#define DDRSS_PHY_234_DATA 0x00000000
+#define DDRSS_PHY_235_DATA 0x00000000
+#define DDRSS_PHY_236_DATA 0x00000000
+#define DDRSS_PHY_237_DATA 0x00000000
+#define DDRSS_PHY_238_DATA 0x00000000
+#define DDRSS_PHY_239_DATA 0x00000000
+#define DDRSS_PHY_240_DATA 0x00000000
+#define DDRSS_PHY_241_DATA 0x00000000
+#define DDRSS_PHY_242_DATA 0x00000000
+#define DDRSS_PHY_243_DATA 0x00000000
+#define DDRSS_PHY_244_DATA 0x00000000
+#define DDRSS_PHY_245_DATA 0x00000000
+#define DDRSS_PHY_246_DATA 0x00000000
+#define DDRSS_PHY_247_DATA 0x00000000
+#define DDRSS_PHY_248_DATA 0x00000000
+#define DDRSS_PHY_249_DATA 0x00000000
+#define DDRSS_PHY_250_DATA 0x00000000
+#define DDRSS_PHY_251_DATA 0x00000000
+#define DDRSS_PHY_252_DATA 0x00000000
+#define DDRSS_PHY_253_DATA 0x00000000
+#define DDRSS_PHY_254_DATA 0x00000000
+#define DDRSS_PHY_255_DATA 0x00000000
+#define DDRSS_PHY_256_DATA 0x000004F0
+#define DDRSS_PHY_257_DATA 0x00000000
+#define DDRSS_PHY_258_DATA 0x00030200
+#define DDRSS_PHY_259_DATA 0x00000000
+#define DDRSS_PHY_260_DATA 0x00000000
+#define DDRSS_PHY_261_DATA 0x01030000
+#define DDRSS_PHY_262_DATA 0x00010000
+#define DDRSS_PHY_263_DATA 0x01030004
+#define DDRSS_PHY_264_DATA 0x01000000
+#define DDRSS_PHY_265_DATA 0x00000000
+#define DDRSS_PHY_266_DATA 0x00000000
+#define DDRSS_PHY_267_DATA 0x01000001
+#define DDRSS_PHY_268_DATA 0x00000100
+#define DDRSS_PHY_269_DATA 0x000800C0
+#define DDRSS_PHY_270_DATA 0x060100CC
+#define DDRSS_PHY_271_DATA 0x00030066
+#define DDRSS_PHY_272_DATA 0x00000000
+#define DDRSS_PHY_273_DATA 0x00000301
+#define DDRSS_PHY_274_DATA 0x0000AAAA
+#define DDRSS_PHY_275_DATA 0x00005555
+#define DDRSS_PHY_276_DATA 0x0000B5B5
+#define DDRSS_PHY_277_DATA 0x00004A4A
+#define DDRSS_PHY_278_DATA 0x00005656
+#define DDRSS_PHY_279_DATA 0x0000A9A9
+#define DDRSS_PHY_280_DATA 0x0000A9A9
+#define DDRSS_PHY_281_DATA 0x0000B5B5
+#define DDRSS_PHY_282_DATA 0x00000000
+#define DDRSS_PHY_283_DATA 0x00000000
+#define DDRSS_PHY_284_DATA 0x2A000000
+#define DDRSS_PHY_285_DATA 0x00000808
+#define DDRSS_PHY_286_DATA 0x0F000000
+#define DDRSS_PHY_287_DATA 0x00000F0F
+#define DDRSS_PHY_288_DATA 0x10400000
+#define DDRSS_PHY_289_DATA 0x0C002006
+#define DDRSS_PHY_290_DATA 0x00000000
+#define DDRSS_PHY_291_DATA 0x00000000
+#define DDRSS_PHY_292_DATA 0x55555555
+#define DDRSS_PHY_293_DATA 0xAAAAAAAA
+#define DDRSS_PHY_294_DATA 0x55555555
+#define DDRSS_PHY_295_DATA 0xAAAAAAAA
+#define DDRSS_PHY_296_DATA 0x00005555
+#define DDRSS_PHY_297_DATA 0x01000100
+#define DDRSS_PHY_298_DATA 0x00800180
+#define DDRSS_PHY_299_DATA 0x00000000
+#define DDRSS_PHY_300_DATA 0x00000000
+#define DDRSS_PHY_301_DATA 0x00000000
+#define DDRSS_PHY_302_DATA 0x00000000
+#define DDRSS_PHY_303_DATA 0x00000000
+#define DDRSS_PHY_304_DATA 0x00000000
+#define DDRSS_PHY_305_DATA 0x00000000
+#define DDRSS_PHY_306_DATA 0x00000000
+#define DDRSS_PHY_307_DATA 0x00000000
+#define DDRSS_PHY_308_DATA 0x00000000
+#define DDRSS_PHY_309_DATA 0x00000000
+#define DDRSS_PHY_310_DATA 0x00000000
+#define DDRSS_PHY_311_DATA 0x00000000
+#define DDRSS_PHY_312_DATA 0x00000000
+#define DDRSS_PHY_313_DATA 0x00000000
+#define DDRSS_PHY_314_DATA 0x00000000
+#define DDRSS_PHY_315_DATA 0x00000000
+#define DDRSS_PHY_316_DATA 0x00000000
+#define DDRSS_PHY_317_DATA 0x00000000
+#define DDRSS_PHY_318_DATA 0x00000000
+#define DDRSS_PHY_319_DATA 0x00000000
+#define DDRSS_PHY_320_DATA 0x00000000
+#define DDRSS_PHY_321_DATA 0x00000000
+#define DDRSS_PHY_322_DATA 0x00000104
+#define DDRSS_PHY_323_DATA 0x00000120
+#define DDRSS_PHY_324_DATA 0x00000000
+#define DDRSS_PHY_325_DATA 0x00000000
+#define DDRSS_PHY_326_DATA 0x00000000
+#define DDRSS_PHY_327_DATA 0x00000000
+#define DDRSS_PHY_328_DATA 0x00000000
+#define DDRSS_PHY_329_DATA 0x00000000
+#define DDRSS_PHY_330_DATA 0x00000000
+#define DDRSS_PHY_331_DATA 0x00000001
+#define DDRSS_PHY_332_DATA 0x07FF0000
+#define DDRSS_PHY_333_DATA 0x0080081F
+#define DDRSS_PHY_334_DATA 0x00081020
+#define DDRSS_PHY_335_DATA 0x04010000
+#define DDRSS_PHY_336_DATA 0x00000000
+#define DDRSS_PHY_337_DATA 0x00000000
+#define DDRSS_PHY_338_DATA 0x00000000
+#define DDRSS_PHY_339_DATA 0x00000100
+#define DDRSS_PHY_340_DATA 0x01BB0B01
+#define DDRSS_PHY_341_DATA 0x1003BB0B
+#define DDRSS_PHY_342_DATA 0x20000140
+#define DDRSS_PHY_343_DATA 0x07FF0200
+#define DDRSS_PHY_344_DATA 0x0000DD01
+#define DDRSS_PHY_345_DATA 0x10100303
+#define DDRSS_PHY_346_DATA 0x10101010
+#define DDRSS_PHY_347_DATA 0x10101010
+#define DDRSS_PHY_348_DATA 0x00021010
+#define DDRSS_PHY_349_DATA 0x00100010
+#define DDRSS_PHY_350_DATA 0x00100010
+#define DDRSS_PHY_351_DATA 0x00100010
+#define DDRSS_PHY_352_DATA 0x00100010
+#define DDRSS_PHY_353_DATA 0x00050010
+#define DDRSS_PHY_354_DATA 0x51517041
+#define DDRSS_PHY_355_DATA 0x31C06000
+#define DDRSS_PHY_356_DATA 0x07AB0340
+#define DDRSS_PHY_357_DATA 0x00C0C001
+#define DDRSS_PHY_358_DATA 0x0B0A0001
+#define DDRSS_PHY_359_DATA 0x10001000
+#define DDRSS_PHY_360_DATA 0x0C073E42
+#define DDRSS_PHY_361_DATA 0x0F0C2D01
+#define DDRSS_PHY_362_DATA 0x01000140
+#define DDRSS_PHY_363_DATA 0x0C000420
+#define DDRSS_PHY_364_DATA 0x00000198
+#define DDRSS_PHY_365_DATA 0x0A0000D0
+#define DDRSS_PHY_366_DATA 0x00030200
+#define DDRSS_PHY_367_DATA 0x02800000
+#define DDRSS_PHY_368_DATA 0x80800000
+#define DDRSS_PHY_369_DATA 0x000B2010
+#define DDRSS_PHY_370_DATA 0x76543210
+#define DDRSS_PHY_371_DATA 0x00000008
+#define DDRSS_PHY_372_DATA 0x02800280
+#define DDRSS_PHY_373_DATA 0x02800280
+#define DDRSS_PHY_374_DATA 0x02800280
+#define DDRSS_PHY_375_DATA 0x02800280
+#define DDRSS_PHY_376_DATA 0x00000280
+#define DDRSS_PHY_377_DATA 0x0000A000
+#define DDRSS_PHY_378_DATA 0x00A000A0
+#define DDRSS_PHY_379_DATA 0x00A000A0
+#define DDRSS_PHY_380_DATA 0x00A000A0
+#define DDRSS_PHY_381_DATA 0x00A000A0
+#define DDRSS_PHY_382_DATA 0x00A000A0
+#define DDRSS_PHY_383_DATA 0x00A000A0
+#define DDRSS_PHY_384_DATA 0x00A000A0
+#define DDRSS_PHY_385_DATA 0x00A000A0
+#define DDRSS_PHY_386_DATA 0x011900A0
+#define DDRSS_PHY_387_DATA 0x01A00004
+#define DDRSS_PHY_388_DATA 0x00000000
+#define DDRSS_PHY_389_DATA 0x00000000
+#define DDRSS_PHY_390_DATA 0x00080200
+#define DDRSS_PHY_391_DATA 0x00000000
+#define DDRSS_PHY_392_DATA 0x20202000
+#define DDRSS_PHY_393_DATA 0x20202020
+#define DDRSS_PHY_394_DATA 0xF0F02020
+#define DDRSS_PHY_395_DATA 0x00000000
+#define DDRSS_PHY_396_DATA 0x00000000
+#define DDRSS_PHY_397_DATA 0x00000000
+#define DDRSS_PHY_398_DATA 0x00000000
+#define DDRSS_PHY_399_DATA 0x00000000
+#define DDRSS_PHY_400_DATA 0x00000000
+#define DDRSS_PHY_401_DATA 0x00000000
+#define DDRSS_PHY_402_DATA 0x00000000
+#define DDRSS_PHY_403_DATA 0x00000000
+#define DDRSS_PHY_404_DATA 0x00000000
+#define DDRSS_PHY_405_DATA 0x00000000
+#define DDRSS_PHY_406_DATA 0x00000000
+#define DDRSS_PHY_407_DATA 0x00000000
+#define DDRSS_PHY_408_DATA 0x00000000
+#define DDRSS_PHY_409_DATA 0x00000000
+#define DDRSS_PHY_410_DATA 0x00000000
+#define DDRSS_PHY_411_DATA 0x00000000
+#define DDRSS_PHY_412_DATA 0x00000000
+#define DDRSS_PHY_413_DATA 0x00000000
+#define DDRSS_PHY_414_DATA 0x00000000
+#define DDRSS_PHY_415_DATA 0x00000000
+#define DDRSS_PHY_416_DATA 0x00000000
+#define DDRSS_PHY_417_DATA 0x00000000
+#define DDRSS_PHY_418_DATA 0x00000000
+#define DDRSS_PHY_419_DATA 0x00000000
+#define DDRSS_PHY_420_DATA 0x00000000
+#define DDRSS_PHY_421_DATA 0x00000000
+#define DDRSS_PHY_422_DATA 0x00000000
+#define DDRSS_PHY_423_DATA 0x00000000
+#define DDRSS_PHY_424_DATA 0x00000000
+#define DDRSS_PHY_425_DATA 0x00000000
+#define DDRSS_PHY_426_DATA 0x00000000
+#define DDRSS_PHY_427_DATA 0x00000000
+#define DDRSS_PHY_428_DATA 0x00000000
+#define DDRSS_PHY_429_DATA 0x00000000
+#define DDRSS_PHY_430_DATA 0x00000000
+#define DDRSS_PHY_431_DATA 0x00000000
+#define DDRSS_PHY_432_DATA 0x00000000
+#define DDRSS_PHY_433_DATA 0x00000000
+#define DDRSS_PHY_434_DATA 0x00000000
+#define DDRSS_PHY_435_DATA 0x00000000
+#define DDRSS_PHY_436_DATA 0x00000000
+#define DDRSS_PHY_437_DATA 0x00000000
+#define DDRSS_PHY_438_DATA 0x00000000
+#define DDRSS_PHY_439_DATA 0x00000000
+#define DDRSS_PHY_440_DATA 0x00000000
+#define DDRSS_PHY_441_DATA 0x00000000
+#define DDRSS_PHY_442_DATA 0x00000000
+#define DDRSS_PHY_443_DATA 0x00000000
+#define DDRSS_PHY_444_DATA 0x00000000
+#define DDRSS_PHY_445_DATA 0x00000000
+#define DDRSS_PHY_446_DATA 0x00000000
+#define DDRSS_PHY_447_DATA 0x00000000
+#define DDRSS_PHY_448_DATA 0x00000000
+#define DDRSS_PHY_449_DATA 0x00000000
+#define DDRSS_PHY_450_DATA 0x00000000
+#define DDRSS_PHY_451_DATA 0x00000000
+#define DDRSS_PHY_452_DATA 0x00000000
+#define DDRSS_PHY_453_DATA 0x00000000
+#define DDRSS_PHY_454_DATA 0x00000000
+#define DDRSS_PHY_455_DATA 0x00000000
+#define DDRSS_PHY_456_DATA 0x00000000
+#define DDRSS_PHY_457_DATA 0x00000000
+#define DDRSS_PHY_458_DATA 0x00000000
+#define DDRSS_PHY_459_DATA 0x00000000
+#define DDRSS_PHY_460_DATA 0x00000000
+#define DDRSS_PHY_461_DATA 0x00000000
+#define DDRSS_PHY_462_DATA 0x00000000
+#define DDRSS_PHY_463_DATA 0x00000000
+#define DDRSS_PHY_464_DATA 0x00000000
+#define DDRSS_PHY_465_DATA 0x00000000
+#define DDRSS_PHY_466_DATA 0x00000000
+#define DDRSS_PHY_467_DATA 0x00000000
+#define DDRSS_PHY_468_DATA 0x00000000
+#define DDRSS_PHY_469_DATA 0x00000000
+#define DDRSS_PHY_470_DATA 0x00000000
+#define DDRSS_PHY_471_DATA 0x00000000
+#define DDRSS_PHY_472_DATA 0x00000000
+#define DDRSS_PHY_473_DATA 0x00000000
+#define DDRSS_PHY_474_DATA 0x00000000
+#define DDRSS_PHY_475_DATA 0x00000000
+#define DDRSS_PHY_476_DATA 0x00000000
+#define DDRSS_PHY_477_DATA 0x00000000
+#define DDRSS_PHY_478_DATA 0x00000000
+#define DDRSS_PHY_479_DATA 0x00000000
+#define DDRSS_PHY_480_DATA 0x00000000
+#define DDRSS_PHY_481_DATA 0x00000000
+#define DDRSS_PHY_482_DATA 0x00000000
+#define DDRSS_PHY_483_DATA 0x00000000
+#define DDRSS_PHY_484_DATA 0x00000000
+#define DDRSS_PHY_485_DATA 0x00000000
+#define DDRSS_PHY_486_DATA 0x00000000
+#define DDRSS_PHY_487_DATA 0x00000000
+#define DDRSS_PHY_488_DATA 0x00000000
+#define DDRSS_PHY_489_DATA 0x00000000
+#define DDRSS_PHY_490_DATA 0x00000000
+#define DDRSS_PHY_491_DATA 0x00000000
+#define DDRSS_PHY_492_DATA 0x00000000
+#define DDRSS_PHY_493_DATA 0x00000000
+#define DDRSS_PHY_494_DATA 0x00000000
+#define DDRSS_PHY_495_DATA 0x00000000
+#define DDRSS_PHY_496_DATA 0x00000000
+#define DDRSS_PHY_497_DATA 0x00000000
+#define DDRSS_PHY_498_DATA 0x00000000
+#define DDRSS_PHY_499_DATA 0x00000000
+#define DDRSS_PHY_500_DATA 0x00000000
+#define DDRSS_PHY_501_DATA 0x00000000
+#define DDRSS_PHY_502_DATA 0x00000000
+#define DDRSS_PHY_503_DATA 0x00000000
+#define DDRSS_PHY_504_DATA 0x00000000
+#define DDRSS_PHY_505_DATA 0x00000000
+#define DDRSS_PHY_506_DATA 0x00000000
+#define DDRSS_PHY_507_DATA 0x00000000
+#define DDRSS_PHY_508_DATA 0x00000000
+#define DDRSS_PHY_509_DATA 0x00000000
+#define DDRSS_PHY_510_DATA 0x00000000
+#define DDRSS_PHY_511_DATA 0x00000000
+#define DDRSS_PHY_512_DATA 0x000004F0
+#define DDRSS_PHY_513_DATA 0x00000000
+#define DDRSS_PHY_514_DATA 0x00030200
+#define DDRSS_PHY_515_DATA 0x00000000
+#define DDRSS_PHY_516_DATA 0x00000000
+#define DDRSS_PHY_517_DATA 0x01030000
+#define DDRSS_PHY_518_DATA 0x00010000
+#define DDRSS_PHY_519_DATA 0x01030004
+#define DDRSS_PHY_520_DATA 0x01000000
+#define DDRSS_PHY_521_DATA 0x00000000
+#define DDRSS_PHY_522_DATA 0x00000000
+#define DDRSS_PHY_523_DATA 0x01000001
+#define DDRSS_PHY_524_DATA 0x00000100
+#define DDRSS_PHY_525_DATA 0x000800C0
+#define DDRSS_PHY_526_DATA 0x060100CC
+#define DDRSS_PHY_527_DATA 0x00030066
+#define DDRSS_PHY_528_DATA 0x00000000
+#define DDRSS_PHY_529_DATA 0x00000301
+#define DDRSS_PHY_530_DATA 0x0000AAAA
+#define DDRSS_PHY_531_DATA 0x00005555
+#define DDRSS_PHY_532_DATA 0x0000B5B5
+#define DDRSS_PHY_533_DATA 0x00004A4A
+#define DDRSS_PHY_534_DATA 0x00005656
+#define DDRSS_PHY_535_DATA 0x0000A9A9
+#define DDRSS_PHY_536_DATA 0x0000A9A9
+#define DDRSS_PHY_537_DATA 0x0000B5B5
+#define DDRSS_PHY_538_DATA 0x00000000
+#define DDRSS_PHY_539_DATA 0x00000000
+#define DDRSS_PHY_540_DATA 0x2A000000
+#define DDRSS_PHY_541_DATA 0x00000808
+#define DDRSS_PHY_542_DATA 0x0F000000
+#define DDRSS_PHY_543_DATA 0x00000F0F
+#define DDRSS_PHY_544_DATA 0x10400000
+#define DDRSS_PHY_545_DATA 0x0C002006
+#define DDRSS_PHY_546_DATA 0x00000000
+#define DDRSS_PHY_547_DATA 0x00000000
+#define DDRSS_PHY_548_DATA 0x55555555
+#define DDRSS_PHY_549_DATA 0xAAAAAAAA
+#define DDRSS_PHY_550_DATA 0x55555555
+#define DDRSS_PHY_551_DATA 0xAAAAAAAA
+#define DDRSS_PHY_552_DATA 0x00005555
+#define DDRSS_PHY_553_DATA 0x01000100
+#define DDRSS_PHY_554_DATA 0x00800180
+#define DDRSS_PHY_555_DATA 0x00000001
+#define DDRSS_PHY_556_DATA 0x00000000
+#define DDRSS_PHY_557_DATA 0x00000000
+#define DDRSS_PHY_558_DATA 0x00000000
+#define DDRSS_PHY_559_DATA 0x00000000
+#define DDRSS_PHY_560_DATA 0x00000000
+#define DDRSS_PHY_561_DATA 0x00000000
+#define DDRSS_PHY_562_DATA 0x00000000
+#define DDRSS_PHY_563_DATA 0x00000000
+#define DDRSS_PHY_564_DATA 0x00000000
+#define DDRSS_PHY_565_DATA 0x00000000
+#define DDRSS_PHY_566_DATA 0x00000000
+#define DDRSS_PHY_567_DATA 0x00000000
+#define DDRSS_PHY_568_DATA 0x00000000
+#define DDRSS_PHY_569_DATA 0x00000000
+#define DDRSS_PHY_570_DATA 0x00000000
+#define DDRSS_PHY_571_DATA 0x00000000
+#define DDRSS_PHY_572_DATA 0x00000000
+#define DDRSS_PHY_573_DATA 0x00000000
+#define DDRSS_PHY_574_DATA 0x00000000
+#define DDRSS_PHY_575_DATA 0x00000000
+#define DDRSS_PHY_576_DATA 0x00000000
+#define DDRSS_PHY_577_DATA 0x00000000
+#define DDRSS_PHY_578_DATA 0x00000104
+#define DDRSS_PHY_579_DATA 0x00000120
+#define DDRSS_PHY_580_DATA 0x00000000
+#define DDRSS_PHY_581_DATA 0x00000000
+#define DDRSS_PHY_582_DATA 0x00000000
+#define DDRSS_PHY_583_DATA 0x00000000
+#define DDRSS_PHY_584_DATA 0x00000000
+#define DDRSS_PHY_585_DATA 0x00000000
+#define DDRSS_PHY_586_DATA 0x00000000
+#define DDRSS_PHY_587_DATA 0x00000001
+#define DDRSS_PHY_588_DATA 0x07FF0000
+#define DDRSS_PHY_589_DATA 0x0080081F
+#define DDRSS_PHY_590_DATA 0x00081020
+#define DDRSS_PHY_591_DATA 0x04010000
+#define DDRSS_PHY_592_DATA 0x00000000
+#define DDRSS_PHY_593_DATA 0x00000000
+#define DDRSS_PHY_594_DATA 0x00000000
+#define DDRSS_PHY_595_DATA 0x00000100
+#define DDRSS_PHY_596_DATA 0x01BB0B01
+#define DDRSS_PHY_597_DATA 0x1003BB0B
+#define DDRSS_PHY_598_DATA 0x20000140
+#define DDRSS_PHY_599_DATA 0x07FF0200
+#define DDRSS_PHY_600_DATA 0x0000DD01
+#define DDRSS_PHY_601_DATA 0x10100303
+#define DDRSS_PHY_602_DATA 0x10101010
+#define DDRSS_PHY_603_DATA 0x10101010
+#define DDRSS_PHY_604_DATA 0x00021010
+#define DDRSS_PHY_605_DATA 0x00100010
+#define DDRSS_PHY_606_DATA 0x00100010
+#define DDRSS_PHY_607_DATA 0x00100010
+#define DDRSS_PHY_608_DATA 0x00100010
+#define DDRSS_PHY_609_DATA 0x00050010
+#define DDRSS_PHY_610_DATA 0x51517041
+#define DDRSS_PHY_611_DATA 0x31C06000
+#define DDRSS_PHY_612_DATA 0x07AB0340
+#define DDRSS_PHY_613_DATA 0x00C0C001
+#define DDRSS_PHY_614_DATA 0x0B0A0001
+#define DDRSS_PHY_615_DATA 0x10001000
+#define DDRSS_PHY_616_DATA 0x0C073E42
+#define DDRSS_PHY_617_DATA 0x0F0C2D01
+#define DDRSS_PHY_618_DATA 0x01000140
+#define DDRSS_PHY_619_DATA 0x0C000420
+#define DDRSS_PHY_620_DATA 0x00000198
+#define DDRSS_PHY_621_DATA 0x0A0000D0
+#define DDRSS_PHY_622_DATA 0x00030200
+#define DDRSS_PHY_623_DATA 0x02800000
+#define DDRSS_PHY_624_DATA 0x80800000
+#define DDRSS_PHY_625_DATA 0x000B2010
+#define DDRSS_PHY_626_DATA 0x76543210
+#define DDRSS_PHY_627_DATA 0x00000008
+#define DDRSS_PHY_628_DATA 0x02800280
+#define DDRSS_PHY_629_DATA 0x02800280
+#define DDRSS_PHY_630_DATA 0x02800280
+#define DDRSS_PHY_631_DATA 0x02800280
+#define DDRSS_PHY_632_DATA 0x00000280
+#define DDRSS_PHY_633_DATA 0x0000A000
+#define DDRSS_PHY_634_DATA 0x00A000A0
+#define DDRSS_PHY_635_DATA 0x00A000A0
+#define DDRSS_PHY_636_DATA 0x00A000A0
+#define DDRSS_PHY_637_DATA 0x00A000A0
+#define DDRSS_PHY_638_DATA 0x00A000A0
+#define DDRSS_PHY_639_DATA 0x00A000A0
+#define DDRSS_PHY_640_DATA 0x00A000A0
+#define DDRSS_PHY_641_DATA 0x00A000A0
+#define DDRSS_PHY_642_DATA 0x011900A0
+#define DDRSS_PHY_643_DATA 0x01A00004
+#define DDRSS_PHY_644_DATA 0x00000000
+#define DDRSS_PHY_645_DATA 0x00000000
+#define DDRSS_PHY_646_DATA 0x00080200
+#define DDRSS_PHY_647_DATA 0x00000000
+#define DDRSS_PHY_648_DATA 0x20202000
+#define DDRSS_PHY_649_DATA 0x20202020
+#define DDRSS_PHY_650_DATA 0xF0F02020
+#define DDRSS_PHY_651_DATA 0x00000000
+#define DDRSS_PHY_652_DATA 0x00000000
+#define DDRSS_PHY_653_DATA 0x00000000
+#define DDRSS_PHY_654_DATA 0x00000000
+#define DDRSS_PHY_655_DATA 0x00000000
+#define DDRSS_PHY_656_DATA 0x00000000
+#define DDRSS_PHY_657_DATA 0x00000000
+#define DDRSS_PHY_658_DATA 0x00000000
+#define DDRSS_PHY_659_DATA 0x00000000
+#define DDRSS_PHY_660_DATA 0x00000000
+#define DDRSS_PHY_661_DATA 0x00000000
+#define DDRSS_PHY_662_DATA 0x00000000
+#define DDRSS_PHY_663_DATA 0x00000000
+#define DDRSS_PHY_664_DATA 0x00000000
+#define DDRSS_PHY_665_DATA 0x00000000
+#define DDRSS_PHY_666_DATA 0x00000000
+#define DDRSS_PHY_667_DATA 0x00000000
+#define DDRSS_PHY_668_DATA 0x00000000
+#define DDRSS_PHY_669_DATA 0x00000000
+#define DDRSS_PHY_670_DATA 0x00000000
+#define DDRSS_PHY_671_DATA 0x00000000
+#define DDRSS_PHY_672_DATA 0x00000000
+#define DDRSS_PHY_673_DATA 0x00000000
+#define DDRSS_PHY_674_DATA 0x00000000
+#define DDRSS_PHY_675_DATA 0x00000000
+#define DDRSS_PHY_676_DATA 0x00000000
+#define DDRSS_PHY_677_DATA 0x00000000
+#define DDRSS_PHY_678_DATA 0x00000000
+#define DDRSS_PHY_679_DATA 0x00000000
+#define DDRSS_PHY_680_DATA 0x00000000
+#define DDRSS_PHY_681_DATA 0x00000000
+#define DDRSS_PHY_682_DATA 0x00000000
+#define DDRSS_PHY_683_DATA 0x00000000
+#define DDRSS_PHY_684_DATA 0x00000000
+#define DDRSS_PHY_685_DATA 0x00000000
+#define DDRSS_PHY_686_DATA 0x00000000
+#define DDRSS_PHY_687_DATA 0x00000000
+#define DDRSS_PHY_688_DATA 0x00000000
+#define DDRSS_PHY_689_DATA 0x00000000
+#define DDRSS_PHY_690_DATA 0x00000000
+#define DDRSS_PHY_691_DATA 0x00000000
+#define DDRSS_PHY_692_DATA 0x00000000
+#define DDRSS_PHY_693_DATA 0x00000000
+#define DDRSS_PHY_694_DATA 0x00000000
+#define DDRSS_PHY_695_DATA 0x00000000
+#define DDRSS_PHY_696_DATA 0x00000000
+#define DDRSS_PHY_697_DATA 0x00000000
+#define DDRSS_PHY_698_DATA 0x00000000
+#define DDRSS_PHY_699_DATA 0x00000000
+#define DDRSS_PHY_700_DATA 0x00000000
+#define DDRSS_PHY_701_DATA 0x00000000
+#define DDRSS_PHY_702_DATA 0x00000000
+#define DDRSS_PHY_703_DATA 0x00000000
+#define DDRSS_PHY_704_DATA 0x00000000
+#define DDRSS_PHY_705_DATA 0x00000000
+#define DDRSS_PHY_706_DATA 0x00000000
+#define DDRSS_PHY_707_DATA 0x00000000
+#define DDRSS_PHY_708_DATA 0x00000000
+#define DDRSS_PHY_709_DATA 0x00000000
+#define DDRSS_PHY_710_DATA 0x00000000
+#define DDRSS_PHY_711_DATA 0x00000000
+#define DDRSS_PHY_712_DATA 0x00000000
+#define DDRSS_PHY_713_DATA 0x00000000
+#define DDRSS_PHY_714_DATA 0x00000000
+#define DDRSS_PHY_715_DATA 0x00000000
+#define DDRSS_PHY_716_DATA 0x00000000
+#define DDRSS_PHY_717_DATA 0x00000000
+#define DDRSS_PHY_718_DATA 0x00000000
+#define DDRSS_PHY_719_DATA 0x00000000
+#define DDRSS_PHY_720_DATA 0x00000000
+#define DDRSS_PHY_721_DATA 0x00000000
+#define DDRSS_PHY_722_DATA 0x00000000
+#define DDRSS_PHY_723_DATA 0x00000000
+#define DDRSS_PHY_724_DATA 0x00000000
+#define DDRSS_PHY_725_DATA 0x00000000
+#define DDRSS_PHY_726_DATA 0x00000000
+#define DDRSS_PHY_727_DATA 0x00000000
+#define DDRSS_PHY_728_DATA 0x00000000
+#define DDRSS_PHY_729_DATA 0x00000000
+#define DDRSS_PHY_730_DATA 0x00000000
+#define DDRSS_PHY_731_DATA 0x00000000
+#define DDRSS_PHY_732_DATA 0x00000000
+#define DDRSS_PHY_733_DATA 0x00000000
+#define DDRSS_PHY_734_DATA 0x00000000
+#define DDRSS_PHY_735_DATA 0x00000000
+#define DDRSS_PHY_736_DATA 0x00000000
+#define DDRSS_PHY_737_DATA 0x00000000
+#define DDRSS_PHY_738_DATA 0x00000000
+#define DDRSS_PHY_739_DATA 0x00000000
+#define DDRSS_PHY_740_DATA 0x00000000
+#define DDRSS_PHY_741_DATA 0x00000000
+#define DDRSS_PHY_742_DATA 0x00000000
+#define DDRSS_PHY_743_DATA 0x00000000
+#define DDRSS_PHY_744_DATA 0x00000000
+#define DDRSS_PHY_745_DATA 0x00000000
+#define DDRSS_PHY_746_DATA 0x00000000
+#define DDRSS_PHY_747_DATA 0x00000000
+#define DDRSS_PHY_748_DATA 0x00000000
+#define DDRSS_PHY_749_DATA 0x00000000
+#define DDRSS_PHY_750_DATA 0x00000000
+#define DDRSS_PHY_751_DATA 0x00000000
+#define DDRSS_PHY_752_DATA 0x00000000
+#define DDRSS_PHY_753_DATA 0x00000000
+#define DDRSS_PHY_754_DATA 0x00000000
+#define DDRSS_PHY_755_DATA 0x00000000
+#define DDRSS_PHY_756_DATA 0x00000000
+#define DDRSS_PHY_757_DATA 0x00000000
+#define DDRSS_PHY_758_DATA 0x00000000
+#define DDRSS_PHY_759_DATA 0x00000000
+#define DDRSS_PHY_760_DATA 0x00000000
+#define DDRSS_PHY_761_DATA 0x00000000
+#define DDRSS_PHY_762_DATA 0x00000000
+#define DDRSS_PHY_763_DATA 0x00000000
+#define DDRSS_PHY_764_DATA 0x00000000
+#define DDRSS_PHY_765_DATA 0x00000000
+#define DDRSS_PHY_766_DATA 0x00000000
+#define DDRSS_PHY_767_DATA 0x00000000
+#define DDRSS_PHY_768_DATA 0x000004F0
+#define DDRSS_PHY_769_DATA 0x00000000
+#define DDRSS_PHY_770_DATA 0x00030200
+#define DDRSS_PHY_771_DATA 0x00000000
+#define DDRSS_PHY_772_DATA 0x00000000
+#define DDRSS_PHY_773_DATA 0x01030000
+#define DDRSS_PHY_774_DATA 0x00010000
+#define DDRSS_PHY_775_DATA 0x01030004
+#define DDRSS_PHY_776_DATA 0x01000000
+#define DDRSS_PHY_777_DATA 0x00000000
+#define DDRSS_PHY_778_DATA 0x00000000
+#define DDRSS_PHY_779_DATA 0x01000001
+#define DDRSS_PHY_780_DATA 0x00000100
+#define DDRSS_PHY_781_DATA 0x000800C0
+#define DDRSS_PHY_782_DATA 0x060100CC
+#define DDRSS_PHY_783_DATA 0x00030066
+#define DDRSS_PHY_784_DATA 0x00000000
+#define DDRSS_PHY_785_DATA 0x00000301
+#define DDRSS_PHY_786_DATA 0x0000AAAA
+#define DDRSS_PHY_787_DATA 0x00005555
+#define DDRSS_PHY_788_DATA 0x0000B5B5
+#define DDRSS_PHY_789_DATA 0x00004A4A
+#define DDRSS_PHY_790_DATA 0x00005656
+#define DDRSS_PHY_791_DATA 0x0000A9A9
+#define DDRSS_PHY_792_DATA 0x0000A9A9
+#define DDRSS_PHY_793_DATA 0x0000B5B5
+#define DDRSS_PHY_794_DATA 0x00000000
+#define DDRSS_PHY_795_DATA 0x00000000
+#define DDRSS_PHY_796_DATA 0x2A000000
+#define DDRSS_PHY_797_DATA 0x00000808
+#define DDRSS_PHY_798_DATA 0x0F000000
+#define DDRSS_PHY_799_DATA 0x00000F0F
+#define DDRSS_PHY_800_DATA 0x10400000
+#define DDRSS_PHY_801_DATA 0x0C002006
+#define DDRSS_PHY_802_DATA 0x00000000
+#define DDRSS_PHY_803_DATA 0x00000000
+#define DDRSS_PHY_804_DATA 0x55555555
+#define DDRSS_PHY_805_DATA 0xAAAAAAAA
+#define DDRSS_PHY_806_DATA 0x55555555
+#define DDRSS_PHY_807_DATA 0xAAAAAAAA
+#define DDRSS_PHY_808_DATA 0x00005555
+#define DDRSS_PHY_809_DATA 0x01000100
+#define DDRSS_PHY_810_DATA 0x00800180
+#define DDRSS_PHY_811_DATA 0x00000000
+#define DDRSS_PHY_812_DATA 0x00000000
+#define DDRSS_PHY_813_DATA 0x00000000
+#define DDRSS_PHY_814_DATA 0x00000000
+#define DDRSS_PHY_815_DATA 0x00000000
+#define DDRSS_PHY_816_DATA 0x00000000
+#define DDRSS_PHY_817_DATA 0x00000000
+#define DDRSS_PHY_818_DATA 0x00000000
+#define DDRSS_PHY_819_DATA 0x00000000
+#define DDRSS_PHY_820_DATA 0x00000000
+#define DDRSS_PHY_821_DATA 0x00000000
+#define DDRSS_PHY_822_DATA 0x00000000
+#define DDRSS_PHY_823_DATA 0x00000000
+#define DDRSS_PHY_824_DATA 0x00000000
+#define DDRSS_PHY_825_DATA 0x00000000
+#define DDRSS_PHY_826_DATA 0x00000000
+#define DDRSS_PHY_827_DATA 0x00000000
+#define DDRSS_PHY_828_DATA 0x00000000
+#define DDRSS_PHY_829_DATA 0x00000000
+#define DDRSS_PHY_830_DATA 0x00000000
+#define DDRSS_PHY_831_DATA 0x00000000
+#define DDRSS_PHY_832_DATA 0x00000000
+#define DDRSS_PHY_833_DATA 0x00000000
+#define DDRSS_PHY_834_DATA 0x00000104
+#define DDRSS_PHY_835_DATA 0x00000120
+#define DDRSS_PHY_836_DATA 0x00000000
+#define DDRSS_PHY_837_DATA 0x00000000
+#define DDRSS_PHY_838_DATA 0x00000000
+#define DDRSS_PHY_839_DATA 0x00000000
+#define DDRSS_PHY_840_DATA 0x00000000
+#define DDRSS_PHY_841_DATA 0x00000000
+#define DDRSS_PHY_842_DATA 0x00000000
+#define DDRSS_PHY_843_DATA 0x00000001
+#define DDRSS_PHY_844_DATA 0x07FF0000
+#define DDRSS_PHY_845_DATA 0x0080081F
+#define DDRSS_PHY_846_DATA 0x00081020
+#define DDRSS_PHY_847_DATA 0x04010000
+#define DDRSS_PHY_848_DATA 0x00000000
+#define DDRSS_PHY_849_DATA 0x00000000
+#define DDRSS_PHY_850_DATA 0x00000000
+#define DDRSS_PHY_851_DATA 0x00000100
+#define DDRSS_PHY_852_DATA 0x01BB0B01
+#define DDRSS_PHY_853_DATA 0x1003BB0B
+#define DDRSS_PHY_854_DATA 0x20000140
+#define DDRSS_PHY_855_DATA 0x07FF0200
+#define DDRSS_PHY_856_DATA 0x0000DD01
+#define DDRSS_PHY_857_DATA 0x10100303
+#define DDRSS_PHY_858_DATA 0x10101010
+#define DDRSS_PHY_859_DATA 0x10101010
+#define DDRSS_PHY_860_DATA 0x00021010
+#define DDRSS_PHY_861_DATA 0x00100010
+#define DDRSS_PHY_862_DATA 0x00100010
+#define DDRSS_PHY_863_DATA 0x00100010
+#define DDRSS_PHY_864_DATA 0x00100010
+#define DDRSS_PHY_865_DATA 0x00050010
+#define DDRSS_PHY_866_DATA 0x51517041
+#define DDRSS_PHY_867_DATA 0x31C06000
+#define DDRSS_PHY_868_DATA 0x07AB0340
+#define DDRSS_PHY_869_DATA 0x00C0C001
+#define DDRSS_PHY_870_DATA 0x0B0A0001
+#define DDRSS_PHY_871_DATA 0x10001000
+#define DDRSS_PHY_872_DATA 0x0C073E42
+#define DDRSS_PHY_873_DATA 0x0F0C2D01
+#define DDRSS_PHY_874_DATA 0x01000140
+#define DDRSS_PHY_875_DATA 0x0C000420
+#define DDRSS_PHY_876_DATA 0x00000198
+#define DDRSS_PHY_877_DATA 0x0A0000D0
+#define DDRSS_PHY_878_DATA 0x00030200
+#define DDRSS_PHY_879_DATA 0x02800000
+#define DDRSS_PHY_880_DATA 0x80800000
+#define DDRSS_PHY_881_DATA 0x000B2010
+#define DDRSS_PHY_882_DATA 0x76543210
+#define DDRSS_PHY_883_DATA 0x00000008
+#define DDRSS_PHY_884_DATA 0x02800280
+#define DDRSS_PHY_885_DATA 0x02800280
+#define DDRSS_PHY_886_DATA 0x02800280
+#define DDRSS_PHY_887_DATA 0x02800280
+#define DDRSS_PHY_888_DATA 0x00000280
+#define DDRSS_PHY_889_DATA 0x0000A000
+#define DDRSS_PHY_890_DATA 0x00A000A0
+#define DDRSS_PHY_891_DATA 0x00A000A0
+#define DDRSS_PHY_892_DATA 0x00A000A0
+#define DDRSS_PHY_893_DATA 0x00A000A0
+#define DDRSS_PHY_894_DATA 0x00A000A0
+#define DDRSS_PHY_895_DATA 0x00A000A0
+#define DDRSS_PHY_896_DATA 0x00A000A0
+#define DDRSS_PHY_897_DATA 0x00A000A0
+#define DDRSS_PHY_898_DATA 0x011900A0
+#define DDRSS_PHY_899_DATA 0x01A00004
+#define DDRSS_PHY_900_DATA 0x00000000
+#define DDRSS_PHY_901_DATA 0x00000000
+#define DDRSS_PHY_902_DATA 0x00080200
+#define DDRSS_PHY_903_DATA 0x00000000
+#define DDRSS_PHY_904_DATA 0x20202000
+#define DDRSS_PHY_905_DATA 0x20202020
+#define DDRSS_PHY_906_DATA 0xF0F02020
+#define DDRSS_PHY_907_DATA 0x00000000
+#define DDRSS_PHY_908_DATA 0x00000000
+#define DDRSS_PHY_909_DATA 0x00000000
+#define DDRSS_PHY_910_DATA 0x00000000
+#define DDRSS_PHY_911_DATA 0x00000000
+#define DDRSS_PHY_912_DATA 0x00000000
+#define DDRSS_PHY_913_DATA 0x00000000
+#define DDRSS_PHY_914_DATA 0x00000000
+#define DDRSS_PHY_915_DATA 0x00000000
+#define DDRSS_PHY_916_DATA 0x00000000
+#define DDRSS_PHY_917_DATA 0x00000000
+#define DDRSS_PHY_918_DATA 0x00000000
+#define DDRSS_PHY_919_DATA 0x00000000
+#define DDRSS_PHY_920_DATA 0x00000000
+#define DDRSS_PHY_921_DATA 0x00000000
+#define DDRSS_PHY_922_DATA 0x00000000
+#define DDRSS_PHY_923_DATA 0x00000000
+#define DDRSS_PHY_924_DATA 0x00000000
+#define DDRSS_PHY_925_DATA 0x00000000
+#define DDRSS_PHY_926_DATA 0x00000000
+#define DDRSS_PHY_927_DATA 0x00000000
+#define DDRSS_PHY_928_DATA 0x00000000
+#define DDRSS_PHY_929_DATA 0x00000000
+#define DDRSS_PHY_930_DATA 0x00000000
+#define DDRSS_PHY_931_DATA 0x00000000
+#define DDRSS_PHY_932_DATA 0x00000000
+#define DDRSS_PHY_933_DATA 0x00000000
+#define DDRSS_PHY_934_DATA 0x00000000
+#define DDRSS_PHY_935_DATA 0x00000000
+#define DDRSS_PHY_936_DATA 0x00000000
+#define DDRSS_PHY_937_DATA 0x00000000
+#define DDRSS_PHY_938_DATA 0x00000000
+#define DDRSS_PHY_939_DATA 0x00000000
+#define DDRSS_PHY_940_DATA 0x00000000
+#define DDRSS_PHY_941_DATA 0x00000000
+#define DDRSS_PHY_942_DATA 0x00000000
+#define DDRSS_PHY_943_DATA 0x00000000
+#define DDRSS_PHY_944_DATA 0x00000000
+#define DDRSS_PHY_945_DATA 0x00000000
+#define DDRSS_PHY_946_DATA 0x00000000
+#define DDRSS_PHY_947_DATA 0x00000000
+#define DDRSS_PHY_948_DATA 0x00000000
+#define DDRSS_PHY_949_DATA 0x00000000
+#define DDRSS_PHY_950_DATA 0x00000000
+#define DDRSS_PHY_951_DATA 0x00000000
+#define DDRSS_PHY_952_DATA 0x00000000
+#define DDRSS_PHY_953_DATA 0x00000000
+#define DDRSS_PHY_954_DATA 0x00000000
+#define DDRSS_PHY_955_DATA 0x00000000
+#define DDRSS_PHY_956_DATA 0x00000000
+#define DDRSS_PHY_957_DATA 0x00000000
+#define DDRSS_PHY_958_DATA 0x00000000
+#define DDRSS_PHY_959_DATA 0x00000000
+#define DDRSS_PHY_960_DATA 0x00000000
+#define DDRSS_PHY_961_DATA 0x00000000
+#define DDRSS_PHY_962_DATA 0x00000000
+#define DDRSS_PHY_963_DATA 0x00000000
+#define DDRSS_PHY_964_DATA 0x00000000
+#define DDRSS_PHY_965_DATA 0x00000000
+#define DDRSS_PHY_966_DATA 0x00000000
+#define DDRSS_PHY_967_DATA 0x00000000
+#define DDRSS_PHY_968_DATA 0x00000000
+#define DDRSS_PHY_969_DATA 0x00000000
+#define DDRSS_PHY_970_DATA 0x00000000
+#define DDRSS_PHY_971_DATA 0x00000000
+#define DDRSS_PHY_972_DATA 0x00000000
+#define DDRSS_PHY_973_DATA 0x00000000
+#define DDRSS_PHY_974_DATA 0x00000000
+#define DDRSS_PHY_975_DATA 0x00000000
+#define DDRSS_PHY_976_DATA 0x00000000
+#define DDRSS_PHY_977_DATA 0x00000000
+#define DDRSS_PHY_978_DATA 0x00000000
+#define DDRSS_PHY_979_DATA 0x00000000
+#define DDRSS_PHY_980_DATA 0x00000000
+#define DDRSS_PHY_981_DATA 0x00000000
+#define DDRSS_PHY_982_DATA 0x00000000
+#define DDRSS_PHY_983_DATA 0x00000000
+#define DDRSS_PHY_984_DATA 0x00000000
+#define DDRSS_PHY_985_DATA 0x00000000
+#define DDRSS_PHY_986_DATA 0x00000000
+#define DDRSS_PHY_987_DATA 0x00000000
+#define DDRSS_PHY_988_DATA 0x00000000
+#define DDRSS_PHY_989_DATA 0x00000000
+#define DDRSS_PHY_990_DATA 0x00000000
+#define DDRSS_PHY_991_DATA 0x00000000
+#define DDRSS_PHY_992_DATA 0x00000000
+#define DDRSS_PHY_993_DATA 0x00000000
+#define DDRSS_PHY_994_DATA 0x00000000
+#define DDRSS_PHY_995_DATA 0x00000000
+#define DDRSS_PHY_996_DATA 0x00000000
+#define DDRSS_PHY_997_DATA 0x00000000
+#define DDRSS_PHY_998_DATA 0x00000000
+#define DDRSS_PHY_999_DATA 0x00000000
+#define DDRSS_PHY_1000_DATA 0x00000000
+#define DDRSS_PHY_1001_DATA 0x00000000
+#define DDRSS_PHY_1002_DATA 0x00000000
+#define DDRSS_PHY_1003_DATA 0x00000000
+#define DDRSS_PHY_1004_DATA 0x00000000
+#define DDRSS_PHY_1005_DATA 0x00000000
+#define DDRSS_PHY_1006_DATA 0x00000000
+#define DDRSS_PHY_1007_DATA 0x00000000
+#define DDRSS_PHY_1008_DATA 0x00000000
+#define DDRSS_PHY_1009_DATA 0x00000000
+#define DDRSS_PHY_1010_DATA 0x00000000
+#define DDRSS_PHY_1011_DATA 0x00000000
+#define DDRSS_PHY_1012_DATA 0x00000000
+#define DDRSS_PHY_1013_DATA 0x00000000
+#define DDRSS_PHY_1014_DATA 0x00000000
+#define DDRSS_PHY_1015_DATA 0x00000000
+#define DDRSS_PHY_1016_DATA 0x00000000
+#define DDRSS_PHY_1017_DATA 0x00000000
+#define DDRSS_PHY_1018_DATA 0x00000000
+#define DDRSS_PHY_1019_DATA 0x00000000
+#define DDRSS_PHY_1020_DATA 0x00000000
+#define DDRSS_PHY_1021_DATA 0x00000000
+#define DDRSS_PHY_1022_DATA 0x00000000
+#define DDRSS_PHY_1023_DATA 0x00000000
+#define DDRSS_PHY_1024_DATA 0x00000000
+#define DDRSS_PHY_1025_DATA 0x00000000
+#define DDRSS_PHY_1026_DATA 0x00000000
+#define DDRSS_PHY_1027_DATA 0x00000000
+#define DDRSS_PHY_1028_DATA 0x00000000
+#define DDRSS_PHY_1029_DATA 0x00000100
+#define DDRSS_PHY_1030_DATA 0x00000200
+#define DDRSS_PHY_1031_DATA 0x00000000
+#define DDRSS_PHY_1032_DATA 0x00000000
+#define DDRSS_PHY_1033_DATA 0x00000000
+#define DDRSS_PHY_1034_DATA 0x00000000
+#define DDRSS_PHY_1035_DATA 0x00400000
+#define DDRSS_PHY_1036_DATA 0x00000080
+#define DDRSS_PHY_1037_DATA 0x00DCBA98
+#define DDRSS_PHY_1038_DATA 0x03000000
+#define DDRSS_PHY_1039_DATA 0x00200000
+#define DDRSS_PHY_1040_DATA 0x00000000
+#define DDRSS_PHY_1041_DATA 0x00000000
+#define DDRSS_PHY_1042_DATA 0x00000000
+#define DDRSS_PHY_1043_DATA 0x00000000
+#define DDRSS_PHY_1044_DATA 0x00000000
+#define DDRSS_PHY_1045_DATA 0x0000002A
+#define DDRSS_PHY_1046_DATA 0x00000015
+#define DDRSS_PHY_1047_DATA 0x00000015
+#define DDRSS_PHY_1048_DATA 0x0000002A
+#define DDRSS_PHY_1049_DATA 0x00000033
+#define DDRSS_PHY_1050_DATA 0x0000000C
+#define DDRSS_PHY_1051_DATA 0x0000000C
+#define DDRSS_PHY_1052_DATA 0x00000033
+#define DDRSS_PHY_1053_DATA 0x00543210
+#define DDRSS_PHY_1054_DATA 0x003F0000
+#define DDRSS_PHY_1055_DATA 0x000F013F
+#define DDRSS_PHY_1056_DATA 0x20202003
+#define DDRSS_PHY_1057_DATA 0x00202020
+#define DDRSS_PHY_1058_DATA 0x20008008
+#define DDRSS_PHY_1059_DATA 0x00000810
+#define DDRSS_PHY_1060_DATA 0x00000F00
+#define DDRSS_PHY_1061_DATA 0x00000000
+#define DDRSS_PHY_1062_DATA 0x00000000
+#define DDRSS_PHY_1063_DATA 0x00000000
+#define DDRSS_PHY_1064_DATA 0x000305FF
+#define DDRSS_PHY_1065_DATA 0x00030000
+#define DDRSS_PHY_1066_DATA 0x00000300
+#define DDRSS_PHY_1067_DATA 0x00000300
+#define DDRSS_PHY_1068_DATA 0x00000300
+#define DDRSS_PHY_1069_DATA 0x00000300
+#define DDRSS_PHY_1070_DATA 0x00000300
+#define DDRSS_PHY_1071_DATA 0x42080010
+#define DDRSS_PHY_1072_DATA 0x0000803E
+#define DDRSS_PHY_1073_DATA 0x00000001
+#define DDRSS_PHY_1074_DATA 0x01000102
+#define DDRSS_PHY_1075_DATA 0x00008000
+#define DDRSS_PHY_1076_DATA 0x00000000
+#define DDRSS_PHY_1077_DATA 0x00000000
+#define DDRSS_PHY_1078_DATA 0x00000000
+#define DDRSS_PHY_1079_DATA 0x00000000
+#define DDRSS_PHY_1080_DATA 0x00000000
+#define DDRSS_PHY_1081_DATA 0x00000000
+#define DDRSS_PHY_1082_DATA 0x00000000
+#define DDRSS_PHY_1083_DATA 0x00000000
+#define DDRSS_PHY_1084_DATA 0x00000000
+#define DDRSS_PHY_1085_DATA 0x00000000
+#define DDRSS_PHY_1086_DATA 0x00000000
+#define DDRSS_PHY_1087_DATA 0x00000000
+#define DDRSS_PHY_1088_DATA 0x00000000
+#define DDRSS_PHY_1089_DATA 0x00000000
+#define DDRSS_PHY_1090_DATA 0x00000000
+#define DDRSS_PHY_1091_DATA 0x00000000
+#define DDRSS_PHY_1092_DATA 0x00000000
+#define DDRSS_PHY_1093_DATA 0x00000000
+#define DDRSS_PHY_1094_DATA 0x00000000
+#define DDRSS_PHY_1095_DATA 0x00000000
+#define DDRSS_PHY_1096_DATA 0x00000000
+#define DDRSS_PHY_1097_DATA 0x00000000
+#define DDRSS_PHY_1098_DATA 0x00000000
+#define DDRSS_PHY_1099_DATA 0x00000000
+#define DDRSS_PHY_1100_DATA 0x00000000
+#define DDRSS_PHY_1101_DATA 0x00000000
+#define DDRSS_PHY_1102_DATA 0x00000000
+#define DDRSS_PHY_1103_DATA 0x00000000
+#define DDRSS_PHY_1104_DATA 0x00000000
+#define DDRSS_PHY_1105_DATA 0x00000000
+#define DDRSS_PHY_1106_DATA 0x00000000
+#define DDRSS_PHY_1107_DATA 0x00000000
+#define DDRSS_PHY_1108_DATA 0x00000000
+#define DDRSS_PHY_1109_DATA 0x00000000
+#define DDRSS_PHY_1110_DATA 0x00000000
+#define DDRSS_PHY_1111_DATA 0x00000000
+#define DDRSS_PHY_1112_DATA 0x00000000
+#define DDRSS_PHY_1113_DATA 0x00000000
+#define DDRSS_PHY_1114_DATA 0x00000000
+#define DDRSS_PHY_1115_DATA 0x00000000
+#define DDRSS_PHY_1116_DATA 0x00000000
+#define DDRSS_PHY_1117_DATA 0x00000000
+#define DDRSS_PHY_1118_DATA 0x00000000
+#define DDRSS_PHY_1119_DATA 0x00000000
+#define DDRSS_PHY_1120_DATA 0x00000000
+#define DDRSS_PHY_1121_DATA 0x00000000
+#define DDRSS_PHY_1122_DATA 0x00000000
+#define DDRSS_PHY_1123_DATA 0x00000000
+#define DDRSS_PHY_1124_DATA 0x00000000
+#define DDRSS_PHY_1125_DATA 0x00000000
+#define DDRSS_PHY_1126_DATA 0x00000000
+#define DDRSS_PHY_1127_DATA 0x00000000
+#define DDRSS_PHY_1128_DATA 0x00000000
+#define DDRSS_PHY_1129_DATA 0x00000000
+#define DDRSS_PHY_1130_DATA 0x00000000
+#define DDRSS_PHY_1131_DATA 0x00000000
+#define DDRSS_PHY_1132_DATA 0x00000000
+#define DDRSS_PHY_1133_DATA 0x00000000
+#define DDRSS_PHY_1134_DATA 0x00000000
+#define DDRSS_PHY_1135_DATA 0x00000000
+#define DDRSS_PHY_1136_DATA 0x00000000
+#define DDRSS_PHY_1137_DATA 0x00000000
+#define DDRSS_PHY_1138_DATA 0x00000000
+#define DDRSS_PHY_1139_DATA 0x00000000
+#define DDRSS_PHY_1140_DATA 0x00000000
+#define DDRSS_PHY_1141_DATA 0x00000000
+#define DDRSS_PHY_1142_DATA 0x00000000
+#define DDRSS_PHY_1143_DATA 0x00000000
+#define DDRSS_PHY_1144_DATA 0x00000000
+#define DDRSS_PHY_1145_DATA 0x00000000
+#define DDRSS_PHY_1146_DATA 0x00000000
+#define DDRSS_PHY_1147_DATA 0x00000000
+#define DDRSS_PHY_1148_DATA 0x00000000
+#define DDRSS_PHY_1149_DATA 0x00000000
+#define DDRSS_PHY_1150_DATA 0x00000000
+#define DDRSS_PHY_1151_DATA 0x00000000
+#define DDRSS_PHY_1152_DATA 0x00000000
+#define DDRSS_PHY_1153_DATA 0x00000000
+#define DDRSS_PHY_1154_DATA 0x00000000
+#define DDRSS_PHY_1155_DATA 0x00000000
+#define DDRSS_PHY_1156_DATA 0x00000000
+#define DDRSS_PHY_1157_DATA 0x00000000
+#define DDRSS_PHY_1158_DATA 0x00000000
+#define DDRSS_PHY_1159_DATA 0x00000000
+#define DDRSS_PHY_1160_DATA 0x00000000
+#define DDRSS_PHY_1161_DATA 0x00000000
+#define DDRSS_PHY_1162_DATA 0x00000000
+#define DDRSS_PHY_1163_DATA 0x00000000
+#define DDRSS_PHY_1164_DATA 0x00000000
+#define DDRSS_PHY_1165_DATA 0x00000000
+#define DDRSS_PHY_1166_DATA 0x00000000
+#define DDRSS_PHY_1167_DATA 0x00000000
+#define DDRSS_PHY_1168_DATA 0x00000000
+#define DDRSS_PHY_1169_DATA 0x00000000
+#define DDRSS_PHY_1170_DATA 0x00000000
+#define DDRSS_PHY_1171_DATA 0x00000000
+#define DDRSS_PHY_1172_DATA 0x00000000
+#define DDRSS_PHY_1173_DATA 0x00000000
+#define DDRSS_PHY_1174_DATA 0x00000000
+#define DDRSS_PHY_1175_DATA 0x00000000
+#define DDRSS_PHY_1176_DATA 0x00000000
+#define DDRSS_PHY_1177_DATA 0x00000000
+#define DDRSS_PHY_1178_DATA 0x00000000
+#define DDRSS_PHY_1179_DATA 0x00000000
+#define DDRSS_PHY_1180_DATA 0x00000000
+#define DDRSS_PHY_1181_DATA 0x00000000
+#define DDRSS_PHY_1182_DATA 0x00000000
+#define DDRSS_PHY_1183_DATA 0x00000000
+#define DDRSS_PHY_1184_DATA 0x00000000
+#define DDRSS_PHY_1185_DATA 0x00000000
+#define DDRSS_PHY_1186_DATA 0x00000000
+#define DDRSS_PHY_1187_DATA 0x00000000
+#define DDRSS_PHY_1188_DATA 0x00000000
+#define DDRSS_PHY_1189_DATA 0x00000000
+#define DDRSS_PHY_1190_DATA 0x00000000
+#define DDRSS_PHY_1191_DATA 0x00000000
+#define DDRSS_PHY_1192_DATA 0x00000000
+#define DDRSS_PHY_1193_DATA 0x00000000
+#define DDRSS_PHY_1194_DATA 0x00000000
+#define DDRSS_PHY_1195_DATA 0x00000000
+#define DDRSS_PHY_1196_DATA 0x00000000
+#define DDRSS_PHY_1197_DATA 0x00000000
+#define DDRSS_PHY_1198_DATA 0x00000000
+#define DDRSS_PHY_1199_DATA 0x00000000
+#define DDRSS_PHY_1200_DATA 0x00000000
+#define DDRSS_PHY_1201_DATA 0x00000000
+#define DDRSS_PHY_1202_DATA 0x00000000
+#define DDRSS_PHY_1203_DATA 0x00000000
+#define DDRSS_PHY_1204_DATA 0x00000000
+#define DDRSS_PHY_1205_DATA 0x00000000
+#define DDRSS_PHY_1206_DATA 0x00000000
+#define DDRSS_PHY_1207_DATA 0x00000000
+#define DDRSS_PHY_1208_DATA 0x00000000
+#define DDRSS_PHY_1209_DATA 0x00000000
+#define DDRSS_PHY_1210_DATA 0x00000000
+#define DDRSS_PHY_1211_DATA 0x00000000
+#define DDRSS_PHY_1212_DATA 0x00000000
+#define DDRSS_PHY_1213_DATA 0x00000000
+#define DDRSS_PHY_1214_DATA 0x00000000
+#define DDRSS_PHY_1215_DATA 0x00000000
+#define DDRSS_PHY_1216_DATA 0x00000000
+#define DDRSS_PHY_1217_DATA 0x00000000
+#define DDRSS_PHY_1218_DATA 0x00000000
+#define DDRSS_PHY_1219_DATA 0x00000000
+#define DDRSS_PHY_1220_DATA 0x00000000
+#define DDRSS_PHY_1221_DATA 0x00000000
+#define DDRSS_PHY_1222_DATA 0x00000000
+#define DDRSS_PHY_1223_DATA 0x00000000
+#define DDRSS_PHY_1224_DATA 0x00000000
+#define DDRSS_PHY_1225_DATA 0x00000000
+#define DDRSS_PHY_1226_DATA 0x00000000
+#define DDRSS_PHY_1227_DATA 0x00000000
+#define DDRSS_PHY_1228_DATA 0x00000000
+#define DDRSS_PHY_1229_DATA 0x00000000
+#define DDRSS_PHY_1230_DATA 0x00000000
+#define DDRSS_PHY_1231_DATA 0x00000000
+#define DDRSS_PHY_1232_DATA 0x00000000
+#define DDRSS_PHY_1233_DATA 0x00000000
+#define DDRSS_PHY_1234_DATA 0x00000000
+#define DDRSS_PHY_1235_DATA 0x00000000
+#define DDRSS_PHY_1236_DATA 0x00000000
+#define DDRSS_PHY_1237_DATA 0x00000000
+#define DDRSS_PHY_1238_DATA 0x00000000
+#define DDRSS_PHY_1239_DATA 0x00000000
+#define DDRSS_PHY_1240_DATA 0x00000000
+#define DDRSS_PHY_1241_DATA 0x00000000
+#define DDRSS_PHY_1242_DATA 0x00000000
+#define DDRSS_PHY_1243_DATA 0x00000000
+#define DDRSS_PHY_1244_DATA 0x00000000
+#define DDRSS_PHY_1245_DATA 0x00000000
+#define DDRSS_PHY_1246_DATA 0x00000000
+#define DDRSS_PHY_1247_DATA 0x00000000
+#define DDRSS_PHY_1248_DATA 0x00000000
+#define DDRSS_PHY_1249_DATA 0x00000000
+#define DDRSS_PHY_1250_DATA 0x00000000
+#define DDRSS_PHY_1251_DATA 0x00000000
+#define DDRSS_PHY_1252_DATA 0x00000000
+#define DDRSS_PHY_1253_DATA 0x00000000
+#define DDRSS_PHY_1254_DATA 0x00000000
+#define DDRSS_PHY_1255_DATA 0x00000000
+#define DDRSS_PHY_1256_DATA 0x00000000
+#define DDRSS_PHY_1257_DATA 0x00000000
+#define DDRSS_PHY_1258_DATA 0x00000000
+#define DDRSS_PHY_1259_DATA 0x00000000
+#define DDRSS_PHY_1260_DATA 0x00000000
+#define DDRSS_PHY_1261_DATA 0x00000000
+#define DDRSS_PHY_1262_DATA 0x00000000
+#define DDRSS_PHY_1263_DATA 0x00000000
+#define DDRSS_PHY_1264_DATA 0x00000000
+#define DDRSS_PHY_1265_DATA 0x00000000
+#define DDRSS_PHY_1266_DATA 0x00000000
+#define DDRSS_PHY_1267_DATA 0x00000000
+#define DDRSS_PHY_1268_DATA 0x00000000
+#define DDRSS_PHY_1269_DATA 0x00000000
+#define DDRSS_PHY_1270_DATA 0x00000000
+#define DDRSS_PHY_1271_DATA 0x00000000
+#define DDRSS_PHY_1272_DATA 0x00000000
+#define DDRSS_PHY_1273_DATA 0x00000000
+#define DDRSS_PHY_1274_DATA 0x00000000
+#define DDRSS_PHY_1275_DATA 0x00000000
+#define DDRSS_PHY_1276_DATA 0x00000000
+#define DDRSS_PHY_1277_DATA 0x00000000
+#define DDRSS_PHY_1278_DATA 0x00000000
+#define DDRSS_PHY_1279_DATA 0x00000000
+#define DDRSS_PHY_1280_DATA 0x00000000
+#define DDRSS_PHY_1281_DATA 0x00010100
+#define DDRSS_PHY_1282_DATA 0x00000000
+#define DDRSS_PHY_1283_DATA 0x00000000
+#define DDRSS_PHY_1284_DATA 0x00050000
+#define DDRSS_PHY_1285_DATA 0x04000000
+#define DDRSS_PHY_1286_DATA 0x00000055
+#define DDRSS_PHY_1287_DATA 0x00000000
+#define DDRSS_PHY_1288_DATA 0x00000000
+#define DDRSS_PHY_1289_DATA 0x00000000
+#define DDRSS_PHY_1290_DATA 0x00000000
+#define DDRSS_PHY_1291_DATA 0x00002001
+#define DDRSS_PHY_1292_DATA 0x0000400F
+#define DDRSS_PHY_1293_DATA 0x50020028
+#define DDRSS_PHY_1294_DATA 0x01010000
+#define DDRSS_PHY_1295_DATA 0x80080001
+#define DDRSS_PHY_1296_DATA 0x10200000
+#define DDRSS_PHY_1297_DATA 0x00000008
+#define DDRSS_PHY_1298_DATA 0x00000000
+#define DDRSS_PHY_1299_DATA 0x01090E00
+#define DDRSS_PHY_1300_DATA 0x00040101
+#define DDRSS_PHY_1301_DATA 0x0000010F
+#define DDRSS_PHY_1302_DATA 0x00000000
+#define DDRSS_PHY_1303_DATA 0x0000FFFF
+#define DDRSS_PHY_1304_DATA 0x00000000
+#define DDRSS_PHY_1305_DATA 0x01010000
+#define DDRSS_PHY_1306_DATA 0x01080402
+#define DDRSS_PHY_1307_DATA 0x01200F02
+#define DDRSS_PHY_1308_DATA 0x00194280
+#define DDRSS_PHY_1309_DATA 0x00000004
+#define DDRSS_PHY_1310_DATA 0x00052000
+#define DDRSS_PHY_1311_DATA 0x00000000
+#define DDRSS_PHY_1312_DATA 0x00000000
+#define DDRSS_PHY_1313_DATA 0x00000000
+#define DDRSS_PHY_1314_DATA 0x00000000
+#define DDRSS_PHY_1315_DATA 0x00000000
+#define DDRSS_PHY_1316_DATA 0x00000000
+#define DDRSS_PHY_1317_DATA 0x01000000
+#define DDRSS_PHY_1318_DATA 0x00000705
+#define DDRSS_PHY_1319_DATA 0x00000054
+#define DDRSS_PHY_1320_DATA 0x00030820
+#define DDRSS_PHY_1321_DATA 0x00010820
+#define DDRSS_PHY_1322_DATA 0x00010820
+#define DDRSS_PHY_1323_DATA 0x00010820
+#define DDRSS_PHY_1324_DATA 0x00010820
+#define DDRSS_PHY_1325_DATA 0x00010820
+#define DDRSS_PHY_1326_DATA 0x00010820
+#define DDRSS_PHY_1327_DATA 0x00010820
+#define DDRSS_PHY_1328_DATA 0x00010820
+#define DDRSS_PHY_1329_DATA 0x00000000
+#define DDRSS_PHY_1330_DATA 0x00000074
+#define DDRSS_PHY_1331_DATA 0x00000400
+#define DDRSS_PHY_1332_DATA 0x00000108
+#define DDRSS_PHY_1333_DATA 0x00000000
+#define DDRSS_PHY_1334_DATA 0x00000000
+#define DDRSS_PHY_1335_DATA 0x00000000
+#define DDRSS_PHY_1336_DATA 0x00000000
+#define DDRSS_PHY_1337_DATA 0x00000000
+#define DDRSS_PHY_1338_DATA 0x03000000
+#define DDRSS_PHY_1339_DATA 0x00000000
+#define DDRSS_PHY_1340_DATA 0x00000000
+#define DDRSS_PHY_1341_DATA 0x00000000
+#define DDRSS_PHY_1342_DATA 0x04102006
+#define DDRSS_PHY_1343_DATA 0x00041020
+#define DDRSS_PHY_1344_DATA 0x01C98C98
+#define DDRSS_PHY_1345_DATA 0x3F400000
+#define DDRSS_PHY_1346_DATA 0x3F3F1F3F
+#define DDRSS_PHY_1347_DATA 0x0000001F
+#define DDRSS_PHY_1348_DATA 0x00000000
+#define DDRSS_PHY_1349_DATA 0x00000000
+#define DDRSS_PHY_1350_DATA 0x00000000
+#define DDRSS_PHY_1351_DATA 0x00010000
+#define DDRSS_PHY_1352_DATA 0x00000000
+#define DDRSS_PHY_1353_DATA 0x00000000
+#define DDRSS_PHY_1354_DATA 0x00000000
+#define DDRSS_PHY_1355_DATA 0x00000000
+#define DDRSS_PHY_1356_DATA 0x76543210
+#define DDRSS_PHY_1357_DATA 0x00010198
+#define DDRSS_PHY_1358_DATA 0x00000000
+#define DDRSS_PHY_1359_DATA 0x00000000
+#define DDRSS_PHY_1360_DATA 0x00000000
+#define DDRSS_PHY_1361_DATA 0x00040700
+#define DDRSS_PHY_1362_DATA 0x00000000
+#define DDRSS_PHY_1363_DATA 0x00000000
+#define DDRSS_PHY_1364_DATA 0x00000000
+#define DDRSS_PHY_1365_DATA 0x00000000
+#define DDRSS_PHY_1366_DATA 0x00000000
+#define DDRSS_PHY_1367_DATA 0x00000002
+#define DDRSS_PHY_1368_DATA 0x00000000
+#define DDRSS_PHY_1369_DATA 0x00000000
+#define DDRSS_PHY_1370_DATA 0x00000000
+#define DDRSS_PHY_1371_DATA 0x00000000
+#define DDRSS_PHY_1372_DATA 0x00000000
+#define DDRSS_PHY_1373_DATA 0x00000000
+#define DDRSS_PHY_1374_DATA 0x00080000
+#define DDRSS_PHY_1375_DATA 0x000007FF
+#define DDRSS_PHY_1376_DATA 0x00000000
+#define DDRSS_PHY_1377_DATA 0x00000000
+#define DDRSS_PHY_1378_DATA 0x00000000
+#define DDRSS_PHY_1379_DATA 0x00000000
+#define DDRSS_PHY_1380_DATA 0x00000000
+#define DDRSS_PHY_1381_DATA 0x00000000
+#define DDRSS_PHY_1382_DATA 0x000FFFFF
+#define DDRSS_PHY_1383_DATA 0x000FFFFF
+#define DDRSS_PHY_1384_DATA 0x0000FFFF
+#define DDRSS_PHY_1385_DATA 0xFFFFFFF0
+#define DDRSS_PHY_1386_DATA 0x030FFFFF
+#define DDRSS_PHY_1387_DATA 0x01FFFFFF
+#define DDRSS_PHY_1388_DATA 0x0000FFFF
+#define DDRSS_PHY_1389_DATA 0x00000000
+#define DDRSS_PHY_1390_DATA 0x00000000
+#define DDRSS_PHY_1391_DATA 0x00000000
+#define DDRSS_PHY_1392_DATA 0x00000000
+#define DDRSS_PHY_1393_DATA 0x0001F7C0
+#define DDRSS_PHY_1394_DATA 0x00000003
+#define DDRSS_PHY_1395_DATA 0x00000000
+#define DDRSS_PHY_1396_DATA 0x00001142
+#define DDRSS_PHY_1397_DATA 0x010207AB
+#define DDRSS_PHY_1398_DATA 0x01000080
+#define DDRSS_PHY_1399_DATA 0x03900390
+#define DDRSS_PHY_1400_DATA 0x03900390
+#define DDRSS_PHY_1401_DATA 0x00000390
+#define DDRSS_PHY_1402_DATA 0x00000390
+#define DDRSS_PHY_1403_DATA 0x00000390
+#define DDRSS_PHY_1404_DATA 0x00000390
+#define DDRSS_PHY_1405_DATA 0x00000005
+#define DDRSS_PHY_1406_DATA 0x01813FFF
+#define DDRSS_PHY_1407_DATA 0x000000FF
+#define DDRSS_PHY_1408_DATA 0x0C000DFF
+#define DDRSS_PHY_1409_DATA 0x30000DFF
+#define DDRSS_PHY_1410_DATA 0x3F0DFF11
+#define DDRSS_PHY_1411_DATA 0x000100F0
+#define DDRSS_PHY_1412_DATA 0x780DFFFF
+#define DDRSS_PHY_1413_DATA 0x00007E31
+#define DDRSS_PHY_1414_DATA 0x000CBF11
+#define DDRSS_PHY_1415_DATA 0x01FF0010
+#define DDRSS_PHY_1416_DATA 0x000CBF11
+#define DDRSS_PHY_1417_DATA 0x01FF0010
+#define DDRSS_PHY_1418_DATA 0x3F0DFF11
+#define DDRSS_PHY_1419_DATA 0x01FF00F0
+#define DDRSS_PHY_1420_DATA 0x3F0DFF11
+#define DDRSS_PHY_1421_DATA 0x01FF00F0
+#define DDRSS_PHY_1422_DATA 0x20040006
diff --git a/arch/arm/dts/k3-j721e-ddr-evm-lp4-4266.dtsi b/arch/arm/dts/k3-j721e-ddr-evm-lp4-4266.dtsi
index 5a6f9b1..66e1581 100644
--- a/arch/arm/dts/k3-j721e-ddr-evm-lp4-4266.dtsi
+++ b/arch/arm/dts/k3-j721e-ddr-evm-lp4-4266.dtsi
@@ -1,6 +1,6 @@
// SPDX-License-Identifier: GPL-2.0+
/*
- * Copyright (C) 2019 Texas Instruments Incorporated - http://www.ti.com/
+ * Copyright (C) 2019 Texas Instruments Incorporated - https://www.ti.com/
* This file was generated by the Jacinto7_DDRSS_RegConfigTool, Revision: 0.9.1
* This file was generated on 07/17/2022
*/
diff --git a/arch/arm/dts/k3-j721e-ddr-sk-lp4-4266.dtsi b/arch/arm/dts/k3-j721e-ddr-sk-lp4-4266.dtsi
index 6c7328e..18f1944 100644
--- a/arch/arm/dts/k3-j721e-ddr-sk-lp4-4266.dtsi
+++ b/arch/arm/dts/k3-j721e-ddr-sk-lp4-4266.dtsi
@@ -1,6 +1,6 @@
// SPDX-License-Identifier: GPL-2.0+
/*
- * Copyright (C) 2019 Texas Instruments Incorporated - http://www.ti.com/
+ * Copyright (C) 2019 Texas Instruments Incorporated - https://www.ti.com/
* This file was generated by the Jacinto7_DDRSS_RegConfigTool, Revision: 0.6.1
* This file was generated on 07/19/2021
*/
diff --git a/arch/arm/dts/k3-j721e-ddr.dtsi b/arch/arm/dts/k3-j721e-ddr.dtsi
index 3a9ea42..7d2ccd9 100644
--- a/arch/arm/dts/k3-j721e-ddr.dtsi
+++ b/arch/arm/dts/k3-j721e-ddr.dtsi
@@ -1,6 +1,6 @@
// SPDX-License-Identifier: GPL-2.0+
/*
- * Copyright (C) 2019 Texas Instruments Incorporated - http://www.ti.com/
+ * Copyright (C) 2019 Texas Instruments Incorporated - https://www.ti.com/
*/
/ {
diff --git a/arch/arm/dts/k3-j721e-main.dtsi b/arch/arm/dts/k3-j721e-main.dtsi
index f6c7e16..746b9f8 100644
--- a/arch/arm/dts/k3-j721e-main.dtsi
+++ b/arch/arm/dts/k3-j721e-main.dtsi
@@ -181,7 +181,7 @@
};
main_navss: bus@30000000 {
- compatible = "simple-mfd";
+ compatible = "simple-bus";
#address-cells = <2>;
#size-cells = <2>;
ranges = <0x00 0x30000000 0x00 0x30000000 0x00 0x0c400000>;
diff --git a/arch/arm/dts/k3-j721e-mcu-wakeup.dtsi b/arch/arm/dts/k3-j721e-mcu-wakeup.dtsi
index 05d6ef1..f7ab771 100644
--- a/arch/arm/dts/k3-j721e-mcu-wakeup.dtsi
+++ b/arch/arm/dts/k3-j721e-mcu-wakeup.dtsi
@@ -440,7 +440,7 @@
};
mcu_navss: bus@28380000 {
- compatible = "simple-mfd";
+ compatible = "simple-bus";
#address-cells = <2>;
#size-cells = <2>;
ranges = <0x00 0x28380000 0x00 0x28380000 0x00 0x03880000>;
@@ -671,4 +671,11 @@
power-domains = <&k3_pds 154 TI_SCI_PD_EXCLUSIVE>;
#thermal-sensor-cells = <1>;
};
+
+ mcu_esm: esm@40800000 {
+ compatible = "ti,j721e-esm";
+ reg = <0x00 0x40800000 0x00 0x1000>;
+ ti,esm-pins = <95>;
+ bootph-pre-ram;
+ };
};
diff --git a/arch/arm/dts/k3-j721e-r5-beagleboneai64.dts b/arch/arm/dts/k3-j721e-r5-beagleboneai64.dts
new file mode 100644
index 0000000..43da4da
--- /dev/null
+++ b/arch/arm/dts/k3-j721e-r5-beagleboneai64.dts
@@ -0,0 +1,185 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * https://beagleboard.org/ai-64
+ *
+ * Copyright (C) 2022-2023 Texas Instruments Incorporated - https://www.ti.com/
+ * Copyright (C) 2022 Jason Kridner, BeagleBoard.org Foundation
+ * Copyright (C) 2022-2023 Robert Nelson, BeagleBoard.org Foundation
+ */
+
+#include "k3-j721e-beagleboneai64.dts"
+#include "k3-j721e-ddr-beagleboneai64-lp4-3200.dtsi"
+#include "k3-j721e-ddr.dtsi"
+
+#include "k3-j721e-beagleboneai64-u-boot.dtsi"
+
+/ {
+ aliases {
+ remoteproc0 = &sysctrler;
+ remoteproc1 = &a72_0;
+ };
+
+ chosen {
+ tick-timer = &mcu_timer0;
+ };
+
+ a72_0: a72@0 {
+ compatible = "ti,am654-rproc";
+ reg = <0x0 0x00a90000 0x0 0x10>;
+ power-domains = <&k3_pds 61 TI_SCI_PD_EXCLUSIVE>,
+ <&k3_pds 202 TI_SCI_PD_EXCLUSIVE>,
+ <&k3_pds 4 TI_SCI_PD_EXCLUSIVE>;
+ resets = <&k3_reset 202 0>;
+ clocks = <&k3_clks 61 1>;
+ assigned-clocks = <&k3_clks 202 2>, <&k3_clks 61 1>;
+ assigned-clock-rates = <2000000000>, <200000000>;
+ ti,sci = <&dmsc>;
+ ti,sci-proc-id = <32>;
+ ti,sci-host-id = <10>;
+ bootph-pre-ram;
+ };
+
+ dm_tifs: dm-tifs {
+ compatible = "ti,j721e-dm-sci";
+ ti,host-id = <3>;
+ ti,secure-host;
+ mbox-names = "rx", "tx";
+ mboxes= <&secure_proxy_mcu 21>,
+ <&secure_proxy_mcu 23>;
+ bootph-pre-ram;
+ };
+};
+
+&dmsc {
+ mboxes= <&secure_proxy_mcu 6>,
+ <&secure_proxy_mcu 8>,
+ <&secure_proxy_mcu 5>;
+ mbox-names = "rx", "tx", "notify";
+ ti,host-id = <4>;
+ ti,secure-host;
+};
+
+&mcu_timer0 {
+ status = "okay";
+ bootph-pre-ram;
+};
+
+&secure_proxy_mcu {
+ bootph-pre-ram;
+ /* We require this for boot handshake */
+ status = "okay";
+};
+
+&cbass_mcu_wakeup {
+ sysctrler: sysctrler {
+ compatible = "ti,am654-system-controller";
+ mboxes= <&secure_proxy_mcu 4>, <&secure_proxy_mcu 5>;
+ mbox-names = "tx", "rx";
+ bootph-pre-ram;
+ };
+};
+
+&mcu_ringacc {
+ ti,sci = <&dm_tifs>;
+};
+
+&mcu_udmap {
+ ti,sci = <&dm_tifs>;
+};
+
+&wkup_uart0_pins_default {
+ bootph-pre-ram;
+};
+
+&wkup_i2c0 {
+ bootph-pre-ram;
+};
+
+&binman {
+ tiboot3-j721e-gp-evm.bin {
+ filename = "tiboot3-j721e-gp-evm.bin";
+ symlink = "tiboot3.bin";
+ ti-secure-rom {
+ content = <&u_boot_spl_unsigned>;
+ core = "public";
+ load = <CONFIG_SPL_TEXT_BASE>;
+ sw-rev = <CONFIG_K3_X509_SWRV>;
+ keyfile = "ti-degenerate-key.pem";
+ };
+ u_boot_spl_unsigned: u-boot-spl {
+ no-expanded;
+ };
+ };
+
+ sysfw_gp {
+ filename = "sysfw.bin_gp";
+ ti-secure-rom {
+ content = <&ti_fs>;
+ core = "secure";
+ load = <0x40000>;
+ sw-rev = <CONFIG_K3_X509_SWRV>;
+ keyfile = "ti-degenerate-key.pem";
+ };
+ ti_fs: ti-fs.bin {
+ filename = "ti-sysfw/ti-fs-firmware-j721e-gp.bin";
+ type = "blob-ext";
+ optional;
+ };
+ };
+
+ itb_gp {
+ filename = "sysfw-j721e-gp-evm.itb";
+ symlink = "sysfw.itb";
+ fit {
+ description = "SYSFW and Config fragments";
+ #address-cells = <1>;
+ images {
+ sysfw.bin {
+ description = "sysfw";
+ type = "firmware";
+ arch = "arm";
+ compression = "none";
+ blob-ext {
+ filename = "sysfw.bin_gp";
+ };
+ };
+ board-cfg.bin {
+ description = "board-cfg";
+ type = "firmware";
+ arch = "arm";
+ compression = "none";
+ blob-ext {
+ filename = "board-cfg.bin";
+ };
+ };
+ pm-cfg.bin {
+ description = "pm-cfg";
+ type = "firmware";
+ arch = "arm";
+ compression = "none";
+ blob-ext {
+ filename = "pm-cfg.bin";
+ };
+ };
+ rm-cfg.bin {
+ description = "rm-cfg";
+ type = "firmware";
+ arch = "arm";
+ compression = "none";
+ blob-ext {
+ filename = "rm-cfg.bin";
+ };
+ };
+ sec-cfg.bin {
+ description = "sec-cfg";
+ type = "firmware";
+ arch = "arm";
+ compression = "none";
+ blob-ext {
+ filename = "sec-cfg.bin";
+ };
+ };
+ };
+ };
+ };
+};
diff --git a/arch/arm/dts/k3-j721e-r5-common-proc-board.dts b/arch/arm/dts/k3-j721e-r5-common-proc-board.dts
index fcd9c71..9655ca2 100644
--- a/arch/arm/dts/k3-j721e-r5-common-proc-board.dts
+++ b/arch/arm/dts/k3-j721e-r5-common-proc-board.dts
@@ -1,6 +1,6 @@
// SPDX-License-Identifier: GPL-2.0
/*
- * Copyright (C) 2019 Texas Instruments Incorporated - http://www.ti.com/
+ * Copyright (C) 2019 Texas Instruments Incorporated - https://www.ti.com/
*/
/dts-v1/;
diff --git a/arch/arm/dts/k3-j721s2-binman.dtsi b/arch/arm/dts/k3-j721s2-binman.dtsi
index 5bca4e9..3922007 100644
--- a/arch/arm/dts/k3-j721s2-binman.dtsi
+++ b/arch/arm/dts/k3-j721s2-binman.dtsi
@@ -141,11 +141,9 @@
#ifdef CONFIG_TARGET_J721S2_A72_EVM
-#define SPL_NODTB "spl/u-boot-spl-nodtb.bin"
#define SPL_J721S2_EVM_DTB "spl/dts/k3-j721s2-common-proc-board.dtb"
#define SPL_AM68_SK_DTB "spl/dts/k3-am68-sk-base-board.dtb"
-#define UBOOT_NODTB "u-boot-nodtb.bin"
#define J721S2_EVM_DTB "u-boot.dtb"
#define AM68_SK_DTB "arch/arm/dts/k3-am68-sk-base-board.dtb"
@@ -157,55 +155,11 @@
};
};
ti-spl {
- filename = "tispl.bin";
- pad-byte = <0xff>;
+ insert-template = <&ti_spl_template>;
fit {
- description = "Configuration to load ATF and SPL";
- #address-cells = <1>;
-
images {
-
- atf {
- description = "ARM Trusted Firmware";
- type = "firmware";
- arch = "arm64";
- compression = "none";
- os = "arm-trusted-firmware";
- load = <CONFIG_K3_ATF_LOAD_ADDR>;
- entry = <CONFIG_K3_ATF_LOAD_ADDR>;
- ti-secure {
- content = <&atf>;
- keyfile = "custMpk.pem";
- };
- atf: atf-bl31 {
- };
- };
-
- tee {
- description = "OP-TEE";
- type = "tee";
- arch = "arm64";
- compression = "none";
- os = "tee";
- load = <0x9e800000>;
- entry = <0x9e800000>;
- ti-secure {
- content = <&tee>;
- keyfile = "custMpk.pem";
- };
- tee: tee-os {
- };
- };
-
dm {
- description = "DM binary";
- type = "firmware";
- arch = "arm32";
- compression = "none";
- os = "DM";
- load = <0x89000000>;
- entry = <0x89000000>;
ti-secure {
content = <&dm>;
keyfile = "custMpk.pem";
@@ -215,23 +169,6 @@
};
};
- spl {
- description = "SPL (64-bit)";
- type = "standalone";
- os = "U-Boot";
- arch = "arm64";
- compression = "none";
- load = <CONFIG_SPL_TEXT_BASE>;
- entry = <CONFIG_SPL_TEXT_BASE>;
- ti-secure {
- content = <&u_boot_spl_nodtb>;
- keyfile = "custMpk.pem";
- };
- u_boot_spl_nodtb: blob-ext {
- filename = SPL_NODTB;
- };
- };
-
fdt-0 {
description = "k3-j721s2-common-proc-board";
type = "flat_dt";
@@ -285,29 +222,12 @@
&binman {
u-boot {
- filename = "u-boot.img";
- pad-byte = <0xff>;
+ insert-template = <&u_boot_template>;
fit {
- description = "FIT image with multiple configurations";
-
images {
uboot {
- description = "U-Boot for J721S2 board";
- type = "firmware";
- os = "u-boot";
- arch = "arm";
- compression = "none";
- load = <CONFIG_TEXT_BASE>;
- ti-secure {
- content = <&u_boot_nodtb>;
- keyfile = "custMpk.pem";
- };
- u_boot_nodtb: u-boot-nodtb {
- };
- hash {
- algo = "crc32";
- };
+ description = "U-Boot for J721S2 Board";
};
fdt-0 {
@@ -371,67 +291,16 @@
&binman {
ti-spl_unsigned {
- filename = "tispl.bin_unsigned";
- pad-byte = <0xff>;
+ insert-template = <&ti_spl_unsigned_template>;
fit {
- description = "Configuration to load ATF and SPL";
- #address-cells = <1>;
-
images {
-
- atf {
- description = "ARM Trusted Firmware";
- type = "firmware";
- arch = "arm64";
- compression = "none";
- os = "arm-trusted-firmware";
- load = <CONFIG_K3_ATF_LOAD_ADDR>;
- entry = <CONFIG_K3_ATF_LOAD_ADDR>;
- atf-bl31 {
- filename = "bl31.bin";
- };
- };
-
- tee {
- description = "OP-TEE";
- type = "tee";
- arch = "arm64";
- compression = "none";
- os = "tee";
- load = <0x9e800000>;
- entry = <0x9e800000>;
- tee-os {
- filename = "tee-raw.bin";
- };
- };
-
dm {
- description = "DM binary";
- type = "firmware";
- arch = "arm32";
- compression = "none";
- os = "DM";
- load = <0x89000000>;
- entry = <0x89000000>;
blob-ext {
filename = "ti-dm.bin";
};
};
- spl {
- description = "SPL (64-bit)";
- type = "standalone";
- os = "U-Boot";
- arch = "arm64";
- compression = "none";
- load = <CONFIG_SPL_TEXT_BASE>;
- entry = <CONFIG_SPL_TEXT_BASE>;
- blob {
- filename = "spl/u-boot-spl-nodtb.bin";
- };
- };
-
fdt-0 {
description = "k3-j721s2-common-proc-board";
type = "flat_dt";
@@ -475,26 +344,12 @@
&binman {
u-boot_unsigned {
- filename = "u-boot.img_unsigned";
- pad-byte = <0xff>;
+ insert-template = <&u_boot_unsigned_template>;
fit {
- description = "FIT image with multiple configurations";
-
images {
uboot {
- description = "U-Boot for J721S2 board";
- type = "firmware";
- os = "u-boot";
- arch = "arm";
- compression = "none";
- load = <CONFIG_TEXT_BASE>;
- blob {
- filename = UBOOT_NODTB;
- };
- hash {
- algo = "crc32";
- };
+ description = "U-Boot for J721S2 Board";
};
fdt-0 {
diff --git a/arch/arm/dts/k3-j721s2-main.dtsi b/arch/arm/dts/k3-j721s2-main.dtsi
index 084f8f5..b03731b 100644
--- a/arch/arm/dts/k3-j721s2-main.dtsi
+++ b/arch/arm/dts/k3-j721s2-main.dtsi
@@ -775,7 +775,7 @@
};
main_navss: bus@30000000 {
- compatible = "simple-mfd";
+ compatible = "simple-bus";
#address-cells = <2>;
#size-cells = <2>;
ranges = <0x00 0x30000000 0x00 0x30000000 0x00 0x0c400000>;
@@ -807,6 +807,7 @@
ti,sci = <&sms>;
ti,sci-dev-id = <265>;
ti,interrupt-ranges = <0 0 256>;
+ ti,unmapped-event-sources = <&main_bcdma_csi>;
};
secure_proxy_main: mailbox@32c00000 {
@@ -1103,6 +1104,22 @@
ti,sci-rm-range-rflow = <0x00>; /* GP RFLOW */
};
+ main_bcdma_csi: dma-controller@311a0000 {
+ compatible = "ti,j721s2-dmss-bcdma-csi";
+ reg = <0x00 0x311a0000 0x00 0x100>,
+ <0x00 0x35d00000 0x00 0x20000>,
+ <0x00 0x35c00000 0x00 0x10000>,
+ <0x00 0x35e00000 0x00 0x80000>;
+ reg-names = "gcfg", "rchanrt", "tchanrt", "ringrt";
+ msi-parent = <&main_udmass_inta>;
+ #dma-cells = <3>;
+ ti,sci = <&sms>;
+ ti,sci-dev-id = <225>;
+ ti,sci-rm-range-rchan = <0x21>;
+ ti,sci-rm-range-tchan = <0x22>;
+ status = "disabled";
+ };
+
cpts@310d0000 {
compatible = "ti,j721e-cpts";
reg = <0x0 0x310d0000 0x0 0x400>;
@@ -1695,4 +1712,217 @@
dss_ports: ports {
};
};
+
+ main_r5fss0: r5fss@5c00000 {
+ compatible = "ti,j721s2-r5fss";
+ ti,cluster-mode = <1>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0x5c00000 0x00 0x5c00000 0x20000>,
+ <0x5d00000 0x00 0x5d00000 0x20000>;
+ power-domains = <&k3_pds 277 TI_SCI_PD_EXCLUSIVE>;
+
+ main_r5fss0_core0: r5f@5c00000 {
+ compatible = "ti,j721s2-r5f";
+ reg = <0x5c00000 0x00010000>,
+ <0x5c10000 0x00010000>;
+ reg-names = "atcm", "btcm";
+ ti,sci = <&sms>;
+ ti,sci-dev-id = <279>;
+ ti,sci-proc-ids = <0x06 0xff>;
+ resets = <&k3_reset 279 1>;
+ firmware-name = "j721s2-main-r5f0_0-fw";
+ ti,atcm-enable = <1>;
+ ti,btcm-enable = <1>;
+ ti,loczrama = <1>;
+ };
+
+ main_r5fss0_core1: r5f@5d00000 {
+ compatible = "ti,j721s2-r5f";
+ reg = <0x5d00000 0x00010000>,
+ <0x5d10000 0x00010000>;
+ reg-names = "atcm", "btcm";
+ ti,sci = <&sms>;
+ ti,sci-dev-id = <280>;
+ ti,sci-proc-ids = <0x07 0xff>;
+ resets = <&k3_reset 280 1>;
+ firmware-name = "j721s2-main-r5f0_1-fw";
+ ti,atcm-enable = <1>;
+ ti,btcm-enable = <1>;
+ ti,loczrama = <1>;
+ };
+ };
+
+ main_r5fss1: r5fss@5e00000 {
+ compatible = "ti,j721s2-r5fss";
+ ti,cluster-mode = <1>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0x5e00000 0x00 0x5e00000 0x20000>,
+ <0x5f00000 0x00 0x5f00000 0x20000>;
+ power-domains = <&k3_pds 278 TI_SCI_PD_EXCLUSIVE>;
+
+ main_r5fss1_core0: r5f@5e00000 {
+ compatible = "ti,j721s2-r5f";
+ reg = <0x5e00000 0x00010000>,
+ <0x5e10000 0x00010000>;
+ reg-names = "atcm", "btcm";
+ ti,sci = <&sms>;
+ ti,sci-dev-id = <281>;
+ ti,sci-proc-ids = <0x08 0xff>;
+ resets = <&k3_reset 281 1>;
+ firmware-name = "j721s2-main-r5f1_0-fw";
+ ti,atcm-enable = <1>;
+ ti,btcm-enable = <1>;
+ ti,loczrama = <1>;
+ };
+
+ main_r5fss1_core1: r5f@5f00000 {
+ compatible = "ti,j721s2-r5f";
+ reg = <0x5f00000 0x00010000>,
+ <0x5f10000 0x00010000>;
+ reg-names = "atcm", "btcm";
+ ti,sci = <&sms>;
+ ti,sci-dev-id = <282>;
+ ti,sci-proc-ids = <0x09 0xff>;
+ resets = <&k3_reset 282 1>;
+ firmware-name = "j721s2-main-r5f1_1-fw";
+ ti,atcm-enable = <1>;
+ ti,btcm-enable = <1>;
+ ti,loczrama = <1>;
+ };
+ };
+
+ c71_0: dsp@64800000 {
+ compatible = "ti,j721s2-c71-dsp";
+ reg = <0x00 0x64800000 0x00 0x00080000>,
+ <0x00 0x64e00000 0x00 0x0000c000>;
+ reg-names = "l2sram", "l1dram";
+ ti,sci = <&sms>;
+ ti,sci-dev-id = <8>;
+ ti,sci-proc-ids = <0x30 0xff>;
+ resets = <&k3_reset 8 1>;
+ firmware-name = "j721s2-c71_0-fw";
+ status = "disabled";
+ };
+
+ c71_1: dsp@65800000 {
+ compatible = "ti,j721s2-c71-dsp";
+ reg = <0x00 0x65800000 0x00 0x00080000>,
+ <0x00 0x65e00000 0x00 0x0000c000>;
+ reg-names = "l2sram", "l1dram";
+ ti,sci = <&sms>;
+ ti,sci-dev-id = <11>;
+ ti,sci-proc-ids = <0x31 0xff>;
+ resets = <&k3_reset 11 1>;
+ firmware-name = "j721s2-c71_1-fw";
+ status = "disabled";
+ };
+
+ main_esm: esm@700000 {
+ compatible = "ti,j721e-esm";
+ reg = <0x00 0x700000 0x00 0x1000>;
+ ti,esm-pins = <688>, <689>;
+ bootph-pre-ram;
+ };
+
+ watchdog0: watchdog@2200000 {
+ compatible = "ti,j7-rti-wdt";
+ reg = <0x00 0x2200000 0x00 0x100>;
+ clocks = <&k3_clks 286 1>;
+ power-domains = <&k3_pds 286 TI_SCI_PD_EXCLUSIVE>;
+ assigned-clocks = <&k3_clks 286 1>;
+ assigned-clock-parents = <&k3_clks 286 5>;
+ };
+
+ watchdog1: watchdog@2210000 {
+ compatible = "ti,j7-rti-wdt";
+ reg = <0x00 0x2210000 0x00 0x100>;
+ clocks = <&k3_clks 287 1>;
+ power-domains = <&k3_pds 287 TI_SCI_PD_EXCLUSIVE>;
+ assigned-clocks = <&k3_clks 287 1>;
+ assigned-clock-parents = <&k3_clks 287 5>;
+ };
+
+ /*
+ * The following RTI instances are coupled with MCU R5Fs, c7x and
+ * GPU so keeping them reserved as these will be used by their
+ * respective firmware
+ */
+ watchdog2: watchdog@22f0000 {
+ compatible = "ti,j7-rti-wdt";
+ reg = <0x00 0x22f0000 0x00 0x100>;
+ clocks = <&k3_clks 290 1>;
+ power-domains = <&k3_pds 290 TI_SCI_PD_EXCLUSIVE>;
+ assigned-clocks = <&k3_clks 290 1>;
+ assigned-clock-parents = <&k3_clks 290 5>;
+ /* reserved for GPU */
+ status = "reserved";
+ };
+
+ watchdog3: watchdog@2300000 {
+ compatible = "ti,j7-rti-wdt";
+ reg = <0x00 0x2300000 0x00 0x100>;
+ clocks = <&k3_clks 288 1>;
+ power-domains = <&k3_pds 288 TI_SCI_PD_EXCLUSIVE>;
+ assigned-clocks = <&k3_clks 288 1>;
+ assigned-clock-parents = <&k3_clks 288 5>;
+ /* reserved for C7X_0 */
+ status = "reserved";
+ };
+
+ watchdog4: watchdog@2310000 {
+ compatible = "ti,j7-rti-wdt";
+ reg = <0x00 0x2310000 0x00 0x100>;
+ clocks = <&k3_clks 289 1>;
+ power-domains = <&k3_pds 289 TI_SCI_PD_EXCLUSIVE>;
+ assigned-clocks = <&k3_clks 289 1>;
+ assigned-clock-parents = <&k3_clks 289 5>;
+ /* reserved for C7X_1 */
+ status = "reserved";
+ };
+
+ watchdog5: watchdog@23c0000 {
+ compatible = "ti,j7-rti-wdt";
+ reg = <0x00 0x23c0000 0x00 0x100>;
+ clocks = <&k3_clks 291 1>;
+ power-domains = <&k3_pds 291 TI_SCI_PD_EXCLUSIVE>;
+ assigned-clocks = <&k3_clks 291 1>;
+ assigned-clock-parents = <&k3_clks 291 5>;
+ /* reserved for MAIN_R5F0_0 */
+ status = "reserved";
+ };
+
+ watchdog6: watchdog@23d0000 {
+ compatible = "ti,j7-rti-wdt";
+ reg = <0x00 0x23d0000 0x00 0x100>;
+ clocks = <&k3_clks 292 1>;
+ power-domains = <&k3_pds 292 TI_SCI_PD_EXCLUSIVE>;
+ assigned-clocks = <&k3_clks 292 1>;
+ assigned-clock-parents = <&k3_clks 292 5>;
+ /* reserved for MAIN_R5F0_1 */
+ status = "reserved";
+ };
+
+ watchdog7: watchdog@23e0000 {
+ compatible = "ti,j7-rti-wdt";
+ reg = <0x00 0x23e0000 0x00 0x100>;
+ clocks = <&k3_clks 293 1>;
+ power-domains = <&k3_pds 293 TI_SCI_PD_EXCLUSIVE>;
+ assigned-clocks = <&k3_clks 293 1>;
+ assigned-clock-parents = <&k3_clks 293 5>;
+ /* reserved for MAIN_R5F1_0 */
+ status = "reserved";
+ };
+
+ watchdog8: watchdog@23f0000 {
+ compatible = "ti,j7-rti-wdt";
+ reg = <0x00 0x23f0000 0x00 0x100>;
+ clocks = <&k3_clks 294 1>;
+ power-domains = <&k3_pds 294 TI_SCI_PD_EXCLUSIVE>;
+ assigned-clocks = <&k3_clks 294 1>;
+ assigned-clock-parents = <&k3_clks 294 5>;
+ /* reserved for MAIN_R5F1_1 */
+ status = "reserved";
+ };
};
diff --git a/arch/arm/dts/k3-j721s2-mcu-wakeup.dtsi b/arch/arm/dts/k3-j721s2-mcu-wakeup.dtsi
index 2ddad93..7254f3b 100644
--- a/arch/arm/dts/k3-j721s2-mcu-wakeup.dtsi
+++ b/arch/arm/dts/k3-j721s2-mcu-wakeup.dtsi
@@ -443,7 +443,7 @@
};
mcu_navss: bus@28380000 {
- compatible = "simple-mfd";
+ compatible = "simple-bus";
#address-cells = <2>;
#size-cells = <2>;
ranges = <0x00 0x28380000 0x00 0x28380000 0x00 0x03880000>;
@@ -655,4 +655,84 @@
power-domains = <&k3_pds 154 TI_SCI_PD_SHARED>;
#thermal-sensor-cells = <1>;
};
+
+ mcu_r5fss0: r5fss@41000000 {
+ compatible = "ti,j721s2-r5fss";
+ ti,cluster-mode = <1>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0x41000000 0x00 0x41000000 0x20000>,
+ <0x41400000 0x00 0x41400000 0x20000>;
+ power-domains = <&k3_pds 283 TI_SCI_PD_EXCLUSIVE>;
+
+ mcu_r5fss0_core0: r5f@41000000 {
+ compatible = "ti,j721s2-r5f";
+ reg = <0x41000000 0x00010000>,
+ <0x41010000 0x00010000>;
+ reg-names = "atcm", "btcm";
+ ti,sci = <&sms>;
+ ti,sci-dev-id = <284>;
+ ti,sci-proc-ids = <0x01 0xff>;
+ resets = <&k3_reset 284 1>;
+ firmware-name = "j721s2-mcu-r5f0_0-fw";
+ ti,atcm-enable = <1>;
+ ti,btcm-enable = <1>;
+ ti,loczrama = <1>;
+ };
+
+ mcu_r5fss0_core1: r5f@41400000 {
+ compatible = "ti,j721s2-r5f";
+ reg = <0x41400000 0x00010000>,
+ <0x41410000 0x00010000>;
+ reg-names = "atcm", "btcm";
+ ti,sci = <&sms>;
+ ti,sci-dev-id = <285>;
+ ti,sci-proc-ids = <0x02 0xff>;
+ resets = <&k3_reset 285 1>;
+ firmware-name = "j721s2-mcu-r5f0_1-fw";
+ ti,atcm-enable = <1>;
+ ti,btcm-enable = <1>;
+ ti,loczrama = <1>;
+ };
+ };
+
+ mcu_esm: esm@40800000 {
+ compatible = "ti,j721e-esm";
+ reg = <0x00 0x40800000 0x00 0x1000>;
+ ti,esm-pins = <95>;
+ bootph-pre-ram;
+ };
+
+ wkup_esm: esm@42080000 {
+ compatible = "ti,j721e-esm";
+ reg = <0x00 0x42080000 0x00 0x1000>;
+ ti,esm-pins = <63>;
+ bootph-pre-ram;
+ };
+
+ /*
+ * The 2 RTI instances are couple with MCU R5Fs so keeping them
+ * reserved as these will be used by their respective firmware
+ */
+ mcu_watchdog0: watchdog@40600000 {
+ compatible = "ti,j7-rti-wdt";
+ reg = <0x00 0x40600000 0x00 0x100>;
+ clocks = <&k3_clks 295 1>;
+ power-domains = <&k3_pds 295 TI_SCI_PD_EXCLUSIVE>;
+ assigned-clocks = <&k3_clks 295 1>;
+ assigned-clock-parents = <&k3_clks 295 5>;
+ /* reserved for MCU_R5F0_0 */
+ status = "reserved";
+ };
+
+ mcu_watchdog1: watchdog@40610000 {
+ compatible = "ti,j7-rti-wdt";
+ reg = <0x00 0x40610000 0x00 0x100>;
+ clocks = <&k3_clks 296 1>;
+ power-domains = <&k3_pds 296 TI_SCI_PD_EXCLUSIVE>;
+ assigned-clocks = <&k3_clks 296 1>;
+ assigned-clock-parents = <&k3_clks 296 5>;
+ /* reserved for MCU_R5F0_1 */
+ status = "reserved";
+ };
};
diff --git a/arch/arm/dts/k3-j721s2-som-p0.dtsi b/arch/arm/dts/k3-j721s2-som-p0.dtsi
index a4006f3..dcad372 100644
--- a/arch/arm/dts/k3-j721s2-som-p0.dtsi
+++ b/arch/arm/dts/k3-j721s2-som-p0.dtsi
@@ -29,6 +29,108 @@
alignment = <0x1000>;
no-map;
};
+
+ mcu_r5fss0_core0_dma_memory_region: r5f-dma-memory@a0000000 {
+ compatible = "shared-dma-pool";
+ reg = <0x00 0xa0000000 0x00 0x100000>;
+ no-map;
+ };
+
+ mcu_r5fss0_core0_memory_region: r5f-memory@a0100000 {
+ compatible = "shared-dma-pool";
+ reg = <0x00 0xa0100000 0x00 0xf00000>;
+ no-map;
+ };
+
+ mcu_r5fss0_core1_dma_memory_region: r5f-dma-memory@a1000000 {
+ compatible = "shared-dma-pool";
+ reg = <0x00 0xa1000000 0x00 0x100000>;
+ no-map;
+ };
+
+ mcu_r5fss0_core1_memory_region: r5f-memory@a1100000 {
+ compatible = "shared-dma-pool";
+ reg = <0x00 0xa1100000 0x00 0xf00000>;
+ no-map;
+ };
+
+ main_r5fss0_core0_dma_memory_region: r5f-dma-memory@a2000000 {
+ compatible = "shared-dma-pool";
+ reg = <0x00 0xa2000000 0x00 0x100000>;
+ no-map;
+ };
+
+ main_r5fss0_core0_memory_region: r5f-memory@a2100000 {
+ compatible = "shared-dma-pool";
+ reg = <0x00 0xa2100000 0x00 0xf00000>;
+ no-map;
+ };
+
+ main_r5fss0_core1_dma_memory_region: r5f-dma-memory@a3000000 {
+ compatible = "shared-dma-pool";
+ reg = <0x00 0xa3000000 0x00 0x100000>;
+ no-map;
+ };
+
+ main_r5fss0_core1_memory_region: r5f-memory@a3100000 {
+ compatible = "shared-dma-pool";
+ reg = <0x00 0xa3100000 0x00 0xf00000>;
+ no-map;
+ };
+
+ main_r5fss1_core0_dma_memory_region: r5f-dma-memory@a4000000 {
+ compatible = "shared-dma-pool";
+ reg = <0x00 0xa4000000 0x00 0x100000>;
+ no-map;
+ };
+
+ main_r5fss1_core0_memory_region: r5f-memory@a4100000 {
+ compatible = "shared-dma-pool";
+ reg = <0x00 0xa4100000 0x00 0xf00000>;
+ no-map;
+ };
+
+ main_r5fss1_core1_dma_memory_region: r5f-dma-memory@a5000000 {
+ compatible = "shared-dma-pool";
+ reg = <0x00 0xa5000000 0x00 0x100000>;
+ no-map;
+ };
+
+ main_r5fss1_core1_memory_region: r5f-memory@a5100000 {
+ compatible = "shared-dma-pool";
+ reg = <0x00 0xa5100000 0x00 0xf00000>;
+ no-map;
+ };
+
+ c71_0_dma_memory_region: c71-dma-memory@a6000000 {
+ compatible = "shared-dma-pool";
+ reg = <0x00 0xa6000000 0x00 0x100000>;
+ no-map;
+ };
+
+ c71_0_memory_region: c71-memory@a6100000 {
+ compatible = "shared-dma-pool";
+ reg = <0x00 0xa6100000 0x00 0xf00000>;
+ no-map;
+ };
+
+ c71_1_dma_memory_region: c71-dma-memory@a7000000 {
+ compatible = "shared-dma-pool";
+ reg = <0x00 0xa7000000 0x00 0x100000>;
+ no-map;
+ };
+
+ c71_1_memory_region: c71-memory@a7100000 {
+ compatible = "shared-dma-pool";
+ reg = <0x00 0xa7100000 0x00 0xf00000>;
+ no-map;
+ };
+
+ rtos_ipc_memory_region: ipc-memories@a8000000 {
+ reg = <0x00 0xa8000000 0x00 0x01c00000>;
+ alignment = <0x1000>;
+ no-map;
+ };
};
mux0: mux-controller {
@@ -151,3 +253,109 @@
cdns,read-delay = <4>;
};
};
+
+&mailbox0_cluster0 {
+ status = "okay";
+ interrupts = <436>;
+ mbox_mcu_r5fss0_core0: mbox-mcu-r5fss0-core0 {
+ ti,mbox-rx = <0 0 0>;
+ ti,mbox-tx = <1 0 0>;
+ };
+
+ mbox_mcu_r5fss0_core1: mbox-mcu-r5fss0-core1 {
+ ti,mbox-rx = <2 0 0>;
+ ti,mbox-tx = <3 0 0>;
+ };
+};
+
+&mailbox0_cluster1 {
+ status = "okay";
+ interrupts = <432>;
+ mbox_main_r5fss0_core0: mbox-main-r5fss0-core0 {
+ ti,mbox-rx = <0 0 0>;
+ ti,mbox-tx = <1 0 0>;
+ };
+
+ mbox_main_r5fss0_core1: mbox-main-r5fss0-core1 {
+ ti,mbox-rx = <2 0 0>;
+ ti,mbox-tx = <3 0 0>;
+ };
+};
+
+&mailbox0_cluster2 {
+ status = "okay";
+ interrupts = <428>;
+ mbox_main_r5fss1_core0: mbox-main-r5fss1-core0 {
+ ti,mbox-rx = <0 0 0>;
+ ti,mbox-tx = <1 0 0>;
+ };
+
+ mbox_main_r5fss1_core1: mbox-main-r5fss1-core1 {
+ ti,mbox-rx = <2 0 0>;
+ ti,mbox-tx = <3 0 0>;
+ };
+};
+
+&mailbox0_cluster4 {
+ status = "okay";
+ interrupts = <420>;
+ mbox_c71_0: mbox-c71-0 {
+ ti,mbox-rx = <0 0 0>;
+ ti,mbox-tx = <1 0 0>;
+ };
+
+ mbox_c71_1: mbox-c71-1 {
+ ti,mbox-rx = <2 0 0>;
+ ti,mbox-tx = <3 0 0>;
+ };
+};
+
+&mcu_r5fss0_core0 {
+ mboxes = <&mailbox0_cluster0>, <&mbox_mcu_r5fss0_core0>;
+ memory-region = <&mcu_r5fss0_core0_dma_memory_region>,
+ <&mcu_r5fss0_core0_memory_region>;
+};
+
+&mcu_r5fss0_core1 {
+ mboxes = <&mailbox0_cluster0>, <&mbox_mcu_r5fss0_core1>;
+ memory-region = <&mcu_r5fss0_core1_dma_memory_region>,
+ <&mcu_r5fss0_core1_memory_region>;
+};
+
+&main_r5fss0_core0 {
+ mboxes = <&mailbox0_cluster1>, <&mbox_main_r5fss0_core0>;
+ memory-region = <&main_r5fss0_core0_dma_memory_region>,
+ <&main_r5fss0_core0_memory_region>;
+};
+
+&main_r5fss0_core1 {
+ mboxes = <&mailbox0_cluster1>, <&mbox_main_r5fss0_core1>;
+ memory-region = <&main_r5fss0_core1_dma_memory_region>,
+ <&main_r5fss0_core1_memory_region>;
+};
+
+&main_r5fss1_core0 {
+ mboxes = <&mailbox0_cluster2>, <&mbox_main_r5fss1_core0>;
+ memory-region = <&main_r5fss1_core0_dma_memory_region>,
+ <&main_r5fss1_core0_memory_region>;
+};
+
+&main_r5fss1_core1 {
+ mboxes = <&mailbox0_cluster2>, <&mbox_main_r5fss1_core1>;
+ memory-region = <&main_r5fss1_core1_dma_memory_region>,
+ <&main_r5fss1_core1_memory_region>;
+};
+
+&c71_0 {
+ status = "okay";
+ mboxes = <&mailbox0_cluster4>, <&mbox_c71_0>;
+ memory-region = <&c71_0_dma_memory_region>,
+ <&c71_0_memory_region>;
+};
+
+&c71_1 {
+ status = "okay";
+ mboxes = <&mailbox0_cluster4>, <&mbox_c71_1>;
+ memory-region = <&c71_1_dma_memory_region>,
+ <&c71_1_memory_region>;
+};
diff --git a/arch/arm/dts/k3-serdes.h b/arch/arm/dts/k3-serdes.h
index 29167f8..21b4886 100644
--- a/arch/arm/dts/k3-serdes.h
+++ b/arch/arm/dts/k3-serdes.h
@@ -111,7 +111,7 @@
#define J721S2_SERDES0_LANE2_EDP_LANE2 0x0
#define J721S2_SERDES0_LANE2_PCIE1_LANE2 0x1
-#define J721S2_SERDES0_LANE2_IP3_UNUSED 0x2
+#define J721S2_SERDES0_LANE2_USB_SWAP 0x2
#define J721S2_SERDES0_LANE2_IP4_UNUSED 0x3
#define J721S2_SERDES0_LANE3_EDP_LANE3 0x0
diff --git a/arch/arm/dts/keystone-clocks.dtsi b/arch/arm/dts/keystone-clocks.dtsi
index 457515b..33742d8 100644
--- a/arch/arm/dts/keystone-clocks.dtsi
+++ b/arch/arm/dts/keystone-clocks.dtsi
@@ -2,7 +2,7 @@
/*
* Device Tree Source for Keystone 2 clock tree
*
- * Copyright (C) 2013-2017 Texas Instruments Incorporated - http://www.ti.com/
+ * Copyright (C) 2013-2017 Texas Instruments Incorporated - https://www.ti.com/
*/
clocks {
diff --git a/arch/arm/dts/keystone-k2e-clocks.dtsi b/arch/arm/dts/keystone-k2e-clocks.dtsi
index f759215..46f8ab3 100644
--- a/arch/arm/dts/keystone-k2e-clocks.dtsi
+++ b/arch/arm/dts/keystone-k2e-clocks.dtsi
@@ -2,7 +2,7 @@
/*
* Keystone 2 Edison SoC specific device tree
*
- * Copyright (C) 2014-2017 Texas Instruments Incorporated - http://www.ti.com/
+ * Copyright (C) 2014-2017 Texas Instruments Incorporated - https://www.ti.com/
*/
clocks {
diff --git a/arch/arm/dts/keystone-k2e-evm-u-boot.dtsi b/arch/arm/dts/keystone-k2e-evm-u-boot.dtsi
index 970d452..953c750 100644
--- a/arch/arm/dts/keystone-k2e-evm-u-boot.dtsi
+++ b/arch/arm/dts/keystone-k2e-evm-u-boot.dtsi
@@ -1,6 +1,6 @@
// SPDX-License-Identifier: GPL-2.0+
/*
- * Copyright (C) 2017 Texas Instruments Incorporated - http://www.ti.com/
+ * Copyright (C) 2017 Texas Instruments Incorporated - https://www.ti.com/
*/
/{
diff --git a/arch/arm/dts/keystone-k2e-evm.dts b/arch/arm/dts/keystone-k2e-evm.dts
index ed76e56..bf88444 100644
--- a/arch/arm/dts/keystone-k2e-evm.dts
+++ b/arch/arm/dts/keystone-k2e-evm.dts
@@ -2,7 +2,7 @@
/*
* Keystone 2 Edison EVM device tree
*
- * Copyright (C) 2013-2017 Texas Instruments Incorporated - http://www.ti.com/
+ * Copyright (C) 2013-2017 Texas Instruments Incorporated - https://www.ti.com/
*/
/dts-v1/;
diff --git a/arch/arm/dts/keystone-k2e-netcp.dtsi b/arch/arm/dts/keystone-k2e-netcp.dtsi
index 45ebb0a..dd61503 100644
--- a/arch/arm/dts/keystone-k2e-netcp.dtsi
+++ b/arch/arm/dts/keystone-k2e-netcp.dtsi
@@ -2,7 +2,7 @@
/*
* Device Tree Source for Keystone 2 Edison Netcp driver
*
- * Copyright (C) 2015-2017 Texas Instruments Incorporated - http://www.ti.com/
+ * Copyright (C) 2015-2017 Texas Instruments Incorporated - https://www.ti.com/
*/
qmss: qmss@2a40000 {
diff --git a/arch/arm/dts/keystone-k2e.dtsi b/arch/arm/dts/keystone-k2e.dtsi
index 496bb31..449cddc 100644
--- a/arch/arm/dts/keystone-k2e.dtsi
+++ b/arch/arm/dts/keystone-k2e.dtsi
@@ -2,7 +2,7 @@
/*
* Keystone 2 Edison soc device tree
*
- * Copyright (C) 2013-2017 Texas Instruments Incorporated - http://www.ti.com/
+ * Copyright (C) 2013-2017 Texas Instruments Incorporated - https://www.ti.com/
*/
/ {
diff --git a/arch/arm/dts/keystone-k2g-evm-u-boot.dtsi b/arch/arm/dts/keystone-k2g-evm-u-boot.dtsi
index 05653af..72b67b2 100644
--- a/arch/arm/dts/keystone-k2g-evm-u-boot.dtsi
+++ b/arch/arm/dts/keystone-k2g-evm-u-boot.dtsi
@@ -1,6 +1,6 @@
// SPDX-License-Identifier: GPL-2.0+
/*
- * Copyright (C) 2017 Texas Instruments Incorporated - http://www.ti.com/
+ * Copyright (C) 2017 Texas Instruments Incorporated - https://www.ti.com/
*/
/{
diff --git a/arch/arm/dts/keystone-k2g-evm.dts b/arch/arm/dts/keystone-k2g-evm.dts
index 6376c62..491fdc4 100644
--- a/arch/arm/dts/keystone-k2g-evm.dts
+++ b/arch/arm/dts/keystone-k2g-evm.dts
@@ -2,7 +2,7 @@
/*
* Device Tree Source for K2G EVM
*
- * Copyright (C) 2016-2017 Texas Instruments Incorporated - http://www.ti.com/
+ * Copyright (C) 2016-2017 Texas Instruments Incorporated - https://www.ti.com/
*/
/dts-v1/;
diff --git a/arch/arm/dts/keystone-k2g-generic-u-boot.dtsi b/arch/arm/dts/keystone-k2g-generic-u-boot.dtsi
index 8e4b36c..3634ed7 100644
--- a/arch/arm/dts/keystone-k2g-generic-u-boot.dtsi
+++ b/arch/arm/dts/keystone-k2g-generic-u-boot.dtsi
@@ -1,6 +1,6 @@
// SPDX-License-Identifier: GPL-2.0+
/*
- * Copyright (C) 2017 Texas Instruments Incorporated - http://www.ti.com/
+ * Copyright (C) 2017 Texas Instruments Incorporated - https://www.ti.com/
*/
/{
diff --git a/arch/arm/dts/keystone-k2g-generic.dts b/arch/arm/dts/keystone-k2g-generic.dts
index fc938a4..dc6c31a 100644
--- a/arch/arm/dts/keystone-k2g-generic.dts
+++ b/arch/arm/dts/keystone-k2g-generic.dts
@@ -2,7 +2,7 @@
/*
* Device Tree Source for Generic 66AK2G0X EVM
*
- * Copyright (C) 2017 Texas Instruments Incorporated - http://www.ti.com/
+ * Copyright (C) 2017 Texas Instruments Incorporated - https://www.ti.com/
*/
/dts-v1/;
diff --git a/arch/arm/dts/keystone-k2g-ice-u-boot.dtsi b/arch/arm/dts/keystone-k2g-ice-u-boot.dtsi
index 8e4b36c..3634ed7 100644
--- a/arch/arm/dts/keystone-k2g-ice-u-boot.dtsi
+++ b/arch/arm/dts/keystone-k2g-ice-u-boot.dtsi
@@ -1,6 +1,6 @@
// SPDX-License-Identifier: GPL-2.0+
/*
- * Copyright (C) 2017 Texas Instruments Incorporated - http://www.ti.com/
+ * Copyright (C) 2017 Texas Instruments Incorporated - https://www.ti.com/
*/
/{
diff --git a/arch/arm/dts/keystone-k2g-ice.dts b/arch/arm/dts/keystone-k2g-ice.dts
index cbdb6bf..b898ae6 100644
--- a/arch/arm/dts/keystone-k2g-ice.dts
+++ b/arch/arm/dts/keystone-k2g-ice.dts
@@ -2,7 +2,7 @@
/*
* Device Tree Source for K2G Industrial Communication Engine EVM
*
- * Copyright (C) 2017 Texas Instruments Incorporated - http://www.ti.com/
+ * Copyright (C) 2017 Texas Instruments Incorporated - https://www.ti.com/
*/
/dts-v1/;
diff --git a/arch/arm/dts/keystone-k2g-netcp.dtsi b/arch/arm/dts/keystone-k2g-netcp.dtsi
index 136cd20..2afb488 100644
--- a/arch/arm/dts/keystone-k2g-netcp.dtsi
+++ b/arch/arm/dts/keystone-k2g-netcp.dtsi
@@ -2,7 +2,7 @@
/*
* Device Tree Source for K2G Netcp driver
*
- * Copyright (C) 2018 Texas Instruments Incorporated - http://www.ti.com/
+ * Copyright (C) 2018 Texas Instruments Incorporated - https://www.ti.com/
*/
qmss: qmss@4020000 {
diff --git a/arch/arm/dts/keystone-k2g.dtsi b/arch/arm/dts/keystone-k2g.dtsi
index f12af43..5c3ff12 100644
--- a/arch/arm/dts/keystone-k2g.dtsi
+++ b/arch/arm/dts/keystone-k2g.dtsi
@@ -2,7 +2,7 @@
/*
* Device Tree Source for K2G SOC
*
- * Copyright (C) 2016-2017 Texas Instruments Incorporated - http://www.ti.com/
+ * Copyright (C) 2016-2017 Texas Instruments Incorporated - https://www.ti.com/
*/
#include <dt-bindings/interrupt-controller/arm-gic.h>
diff --git a/arch/arm/dts/keystone-k2hk-clocks.dtsi b/arch/arm/dts/keystone-k2hk-clocks.dtsi
index 4ba6912..3ca4722 100644
--- a/arch/arm/dts/keystone-k2hk-clocks.dtsi
+++ b/arch/arm/dts/keystone-k2hk-clocks.dtsi
@@ -2,7 +2,7 @@
/*
* Keystone 2 Kepler/Hawking SoC clock nodes
*
- * Copyright (C) 2013-2017 Texas Instruments Incorporated - http://www.ti.com/
+ * Copyright (C) 2013-2017 Texas Instruments Incorporated - https://www.ti.com/
*/
clocks {
diff --git a/arch/arm/dts/keystone-k2hk-evm-u-boot.dtsi b/arch/arm/dts/keystone-k2hk-evm-u-boot.dtsi
index 22df84b..3e38f22 100644
--- a/arch/arm/dts/keystone-k2hk-evm-u-boot.dtsi
+++ b/arch/arm/dts/keystone-k2hk-evm-u-boot.dtsi
@@ -1,6 +1,6 @@
// SPDX-License-Identifier: GPL-2.0+
/*
- * Copyright (C) 2017 Texas Instruments Incorporated - http://www.ti.com/
+ * Copyright (C) 2017 Texas Instruments Incorporated - https://www.ti.com/
*/
/{
diff --git a/arch/arm/dts/keystone-k2hk-evm.dts b/arch/arm/dts/keystone-k2hk-evm.dts
index ea53f3f..6222876 100644
--- a/arch/arm/dts/keystone-k2hk-evm.dts
+++ b/arch/arm/dts/keystone-k2hk-evm.dts
@@ -2,7 +2,7 @@
/*
* Keystone 2 Kepler/Hawking EVM device tree
*
- * Copyright (C) 2013-2017 Texas Instruments Incorporated - http://www.ti.com/
+ * Copyright (C) 2013-2017 Texas Instruments Incorporated - https://www.ti.com/
*/
/dts-v1/;
diff --git a/arch/arm/dts/keystone-k2hk-netcp.dtsi b/arch/arm/dts/keystone-k2hk-netcp.dtsi
index 580af63..3f8c4c2 100644
--- a/arch/arm/dts/keystone-k2hk-netcp.dtsi
+++ b/arch/arm/dts/keystone-k2hk-netcp.dtsi
@@ -2,7 +2,7 @@
/*
* Device Tree Source for Keystone 2 Hawking Netcp driver
*
- * Copyright (C) 2015-2017 Texas Instruments Incorporated - http://www.ti.com/
+ * Copyright (C) 2015-2017 Texas Instruments Incorporated - https://www.ti.com/
*/
qmss: qmss@2a40000 {
diff --git a/arch/arm/dts/keystone-k2hk.dtsi b/arch/arm/dts/keystone-k2hk.dtsi
index ef02f23..e5ab1fb 100644
--- a/arch/arm/dts/keystone-k2hk.dtsi
+++ b/arch/arm/dts/keystone-k2hk.dtsi
@@ -2,7 +2,7 @@
/*
* Keystone 2 Kepler/Hawking soc specific device tree
*
- * Copyright (C) 2013-2017 Texas Instruments Incorporated - http://www.ti.com/
+ * Copyright (C) 2013-2017 Texas Instruments Incorporated - https://www.ti.com/
*/
/ {
diff --git a/arch/arm/dts/keystone-k2l-clocks.dtsi b/arch/arm/dts/keystone-k2l-clocks.dtsi
index 6355280..fcfc2fb 100644
--- a/arch/arm/dts/keystone-k2l-clocks.dtsi
+++ b/arch/arm/dts/keystone-k2l-clocks.dtsi
@@ -2,7 +2,7 @@
/*
* Keystone 2 lamarr SoC clock nodes
*
- * Copyright (C) 2013-2017 Texas Instruments Incorporated - http://www.ti.com/
+ * Copyright (C) 2013-2017 Texas Instruments Incorporated - https://www.ti.com/
*/
clocks {
diff --git a/arch/arm/dts/keystone-k2l-evm-u-boot.dtsi b/arch/arm/dts/keystone-k2l-evm-u-boot.dtsi
index 0a507d0..f1aed14 100644
--- a/arch/arm/dts/keystone-k2l-evm-u-boot.dtsi
+++ b/arch/arm/dts/keystone-k2l-evm-u-boot.dtsi
@@ -1,6 +1,6 @@
// SPDX-License-Identifier: GPL-2.0+
/*
- * Copyright (C) 2019 Texas Instruments Incorporated - http://www.ti.com/
+ * Copyright (C) 2019 Texas Instruments Incorporated - https://www.ti.com/
*/
&usb_phy {
diff --git a/arch/arm/dts/keystone-k2l-evm.dts b/arch/arm/dts/keystone-k2l-evm.dts
index 187f2ca..9d2b454 100644
--- a/arch/arm/dts/keystone-k2l-evm.dts
+++ b/arch/arm/dts/keystone-k2l-evm.dts
@@ -2,7 +2,7 @@
/*
* Keystone 2 Lamarr EVM device tree
*
- * Copyright (C) 2014-2017 Texas Instruments Incorporated - http://www.ti.com/
+ * Copyright (C) 2014-2017 Texas Instruments Incorporated - https://www.ti.com/
*/
/dts-v1/;
diff --git a/arch/arm/dts/keystone-k2l-netcp.dtsi b/arch/arm/dts/keystone-k2l-netcp.dtsi
index 54c1128..2caa058 100644
--- a/arch/arm/dts/keystone-k2l-netcp.dtsi
+++ b/arch/arm/dts/keystone-k2l-netcp.dtsi
@@ -2,7 +2,7 @@
/*
* Device Tree Source for Keystone 2 Lamarr Netcp driver
*
- * Copyright (C) 2015-2017 Texas Instruments Incorporated - http://www.ti.com/
+ * Copyright (C) 2015-2017 Texas Instruments Incorporated - https://www.ti.com/
*/
qmss: qmss@2a40000 {
diff --git a/arch/arm/dts/keystone-k2l.dtsi b/arch/arm/dts/keystone-k2l.dtsi
index dcc83a7..c8893e2 100644
--- a/arch/arm/dts/keystone-k2l.dtsi
+++ b/arch/arm/dts/keystone-k2l.dtsi
@@ -2,7 +2,7 @@
/*
* Keystone 2 Lamarr SoC specific device tree
*
- * Copyright (C) 2014-2017 Texas Instruments Incorporated - http://www.ti.com/
+ * Copyright (C) 2014-2017 Texas Instruments Incorporated - https://www.ti.com/
*/
/ {
diff --git a/arch/arm/dts/keystone.dtsi b/arch/arm/dts/keystone.dtsi
index 2afcab7..1538cce 100644
--- a/arch/arm/dts/keystone.dtsi
+++ b/arch/arm/dts/keystone.dtsi
@@ -1,6 +1,6 @@
// SPDX-License-Identifier: GPL-2.0
/*
- * Copyright (C) 2013-2017 Texas Instruments Incorporated - http://www.ti.com/
+ * Copyright (C) 2013-2017 Texas Instruments Incorporated - https://www.ti.com/
*/
#include <dt-bindings/interrupt-controller/arm-gic.h>
diff --git a/arch/arm/dts/nuvoton-common-npcm8xx.dtsi b/arch/arm/dts/nuvoton-common-npcm8xx.dtsi
index fabe592..1694ef8 100644
--- a/arch/arm/dts/nuvoton-common-npcm8xx.dtsi
+++ b/arch/arm/dts/nuvoton-common-npcm8xx.dtsi
@@ -133,7 +133,16 @@
ranges = <0x0 0x0 0xf0000000 0x00300000>,
<0xfff00000 0x0 0xfff00000 0x00016000>;
- spi1: spi@201000 {
+ host_intf: host_intf@9f000 {
+ compatible = "nuvoton,npcm845-host-intf";
+ reg = <0x9f000 0x1000>;
+ type = "espi";
+ ioaddr = <0x4e>;
+ channel-support = <0xf>;
+ syscon = <&gcr>;
+ };
+
+ pspi: spi@201000 {
compatible = "nuvoton,npcm845-pspi";
reg = <0x201000 0x1000>;
pinctrl-names = "default";
diff --git a/arch/arm/dts/nuvoton-npcm845-evb.dts b/arch/arm/dts/nuvoton-npcm845-evb.dts
index a93666c..0d3aaa0 100644
--- a/arch/arm/dts/nuvoton-npcm845-evb.dts
+++ b/arch/arm/dts/nuvoton-npcm845-evb.dts
@@ -2,6 +2,8 @@
// Copyright (c) 2021 Nuvoton Technology tomer.maimon@nuvoton.com
/dts-v1/;
+
+#include <dt-bindings/phy/nuvoton,npcm-usbphy.h>
#include "nuvoton-npcm845.dtsi"
#include "nuvoton-npcm845-pincfg.dtsi"
@@ -46,10 +48,10 @@
spi1 = &fiu1;
spi3 = &fiu3;
spi4 = &fiux;
- spi5 = &spi1;
+ spi5 = &pspi;
usb0 = &udc0;
usb1 = &ehci1;
- usb2 = &ehci2;
+ usb2 = &udc8;
};
chosen {
@@ -60,6 +62,17 @@
reg = <0x0 0x0 0x0 0x40000000>;
};
+ tpm@0 {
+ compatible = "microsoft,ftpm";
+ };
+
+ firmware {
+ optee {
+ compatible = "linaro,optee-tz";
+ method = "smc";
+ };
+ };
+
vsbr2: vsbr2 {
compatible = "regulator-npcm845";
regulator-name = "vr2";
@@ -149,6 +162,8 @@
snps,reset-active-low;
snps,reset-delays-us = <0 10000 1000000>;
snps,reset-gpio = <&gpio5 2 GPIO_ACTIVE_LOW>; /* gpio162 */
+ phy-supply = <&vsbr2>;
+ phy-supply-microvolt = <1800000>;
status = "okay";
};
@@ -179,7 +194,7 @@
status = "okay";
};
-&spi1 {
+&pspi {
status = "okay";
};
@@ -197,7 +212,7 @@
&udc0 {
status = "okay";
- phys = <&usbphy1 0>;
+ phys = <&usbphy1 NPCM_UDC0_7>;
};
&sdhci0 {
@@ -207,12 +222,12 @@
&ehci1 {
status = "okay";
- phys = <&usbphy2 3>;
+ phys = <&usbphy2 NPCM_USBH1>;
};
-&ehci2 {
+&udc8 {
status = "okay";
- phys = <&usbphy3 4>;
+ phys = <&usbphy3 NPCM_UDC8>;
};
&rng {
diff --git a/arch/arm/dts/nuvoton-npcm8xx-u-boot.dtsi b/arch/arm/dts/nuvoton-npcm8xx-u-boot.dtsi
index e49e564..4c6d5be 100644
--- a/arch/arm/dts/nuvoton-npcm8xx-u-boot.dtsi
+++ b/arch/arm/dts/nuvoton-npcm8xx-u-boot.dtsi
@@ -174,7 +174,7 @@
compatible = "nuvoton,npcm845-usb-phy";
#phy-cells = <1>;
reg = <3>;
- resets = <&rstc3 NPCM8XX_RESET_USBPHY3>;
+ resets = <&rstc4 NPCM8XX_RESET_USBPHY3>;
status = "disabled";
};
};
diff --git a/arch/arm/dts/omap3-u-boot.dtsi b/arch/arm/dts/omap3-u-boot.dtsi
index 7366ff5..bc27937 100644
--- a/arch/arm/dts/omap3-u-boot.dtsi
+++ b/arch/arm/dts/omap3-u-boot.dtsi
@@ -1,5 +1,5 @@
/*
- * Copyright (C) 2017 Texas Instruments Incorporated - http://www.ti.com/
+ * Copyright (C) 2017 Texas Instruments Incorporated - https://www.ti.com/
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
diff --git a/arch/arm/dts/omap5-u-boot.dtsi b/arch/arm/dts/omap5-u-boot.dtsi
index 720e79b..d1de2e7 100644
--- a/arch/arm/dts/omap5-u-boot.dtsi
+++ b/arch/arm/dts/omap5-u-boot.dtsi
@@ -1,5 +1,5 @@
/*
- * Copyright (C) 2017 Texas Instruments Incorporated - http://www.ti.com/
+ * Copyright (C) 2017 Texas Instruments Incorporated - https://www.ti.com/
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
diff --git a/arch/arm/dts/r8a779g0-u-boot.dtsi b/arch/arm/dts/r8a779g0-u-boot.dtsi
index 150657f..cc8beca 100644
--- a/arch/arm/dts/r8a779g0-u-boot.dtsi
+++ b/arch/arm/dts/r8a779g0-u-boot.dtsi
@@ -7,20 +7,10 @@
#include "r8a779x-u-boot.dtsi"
-/ {
- soc {
- rpc: spi@ee200000 {
- compatible = "renesas,r8a779g0-rpc-if", "renesas,rcar-gen4-rpc-if";
- reg = <0 0xee200000 0 0x200>, <0 0x08000000 0 0x04000000>;
- interrupts = <GIC_SPI 225 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cpg CPG_MOD 629>;
- power-domains = <&sysc R8A779G0_PD_ALWAYS_ON>;
- resets = <&cpg 629>;
- bank-width = <2>;
- num-cs = <1>;
- status = "disabled";
- };
- };
+&rpc {
+ reg = <0 0xee200000 0 0x200>, <0 0x08000000 0 0x04000000>;
+ bank-width = <2>;
+ num-cs = <1>;
};
&extalr_clk {
diff --git a/arch/arm/dts/r8a779g0-white-hawk-u-boot.dts b/arch/arm/dts/r8a779g0-white-hawk-u-boot.dts
index efc1b95..bd75603 100644
--- a/arch/arm/dts/r8a779g0-white-hawk-u-boot.dts
+++ b/arch/arm/dts/r8a779g0-white-hawk-u-boot.dts
@@ -28,7 +28,7 @@
#address-cells = <1>;
#size-cells = <0>;
spi-max-frequency = <40000000>;
- status = "okay";
+ status = "disabled";
spi-flash@0 {
#address-cells = <1>;
diff --git a/arch/arm/dts/rk3588-quartzpro64-u-boot.dtsi b/arch/arm/dts/rk3588-quartzpro64-u-boot.dtsi
new file mode 100644
index 0000000..191ec98
--- /dev/null
+++ b/arch/arm/dts/rk3588-quartzpro64-u-boot.dtsi
@@ -0,0 +1,12 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright 2023 Google, Inc
+ */
+
+#include "rk3588-u-boot.dtsi"
+
+/ {
+ chosen {
+ u-boot,spl-boot-order = "same-as-spl", &sdmmc, &sdhci;
+ };
+};
diff --git a/arch/arm/dts/rk3588-quartzpro64.dts b/arch/arm/dts/rk3588-quartzpro64.dts
new file mode 100644
index 0000000..5c59f95
--- /dev/null
+++ b/arch/arm/dts/rk3588-quartzpro64.dts
@@ -0,0 +1,1137 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (c) 2023 Ondřej Jirman <megi@xff.cz>
+ */
+
+/dts-v1/;
+
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/input/input.h>
+#include <dt-bindings/leds/common.h>
+#include <dt-bindings/pinctrl/rockchip.h>
+#include <dt-bindings/usb/pd.h>
+#include "rk3588.dtsi"
+
+/ {
+ model = "PINE64 QuartzPro64";
+ compatible = "pine64,quartzpro64", "rockchip,rk3588";
+
+ aliases {
+ mmc0 = &sdhci;
+ mmc1 = &sdmmc;
+ serial2 = &uart2;
+ };
+
+ chosen {
+ stdout-path = "serial2:1500000n8";
+ };
+
+ adc-keys-0 {
+ compatible = "adc-keys";
+ io-channels = <&saradc 0>;
+ io-channel-names = "buttons";
+ keyup-threshold-microvolt = <1800000>;
+ poll-interval = <100>;
+
+ button-maskrom {
+ label = "Mask Rom";
+ linux,code = <KEY_SETUP>;
+ press-threshold-microvolt = <393>;
+ };
+ };
+
+ adc-keys-1 {
+ compatible = "adc-keys";
+ io-channels = <&saradc 1>;
+ io-channel-names = "buttons";
+ keyup-threshold-microvolt = <1800000>;
+ poll-interval = <100>;
+
+ button-volume-up {
+ label = "V+/REC";
+ linux,code = <KEY_VOLUMEUP>;
+ press-threshold-microvolt = <17821>;
+ };
+
+ button-volume-down {
+ label = "V-";
+ linux,code = <KEY_VOLUMEDOWN>;
+ press-threshold-microvolt = <415384>;
+ };
+
+ button-menu {
+ label = "MENU";
+ linux,code = <KEY_MENU>;
+ press-threshold-microvolt = <890909>;
+ };
+
+ button-esc {
+ label = "ESC";
+ linux,code = <KEY_ESC>;
+ press-threshold-microvolt = <1233962>;
+ };
+ };
+
+ headphone_amp: audio-amplifier-headphone {
+ compatible = "simple-audio-amplifier";
+ enable-gpios = <&gpio1 RK_PD2 GPIO_ACTIVE_HIGH>;
+ sound-name-prefix = "Headphones Amp";
+ };
+
+ speaker_amp: audio-amplifier-speaker {
+ compatible = "simple-audio-amplifier";
+ enable-gpios = <&gpio1 RK_PD3 GPIO_ACTIVE_HIGH>;
+ sound-name-prefix = "Speaker Amp";
+ };
+
+ leds {
+ compatible = "gpio-leds";
+ pinctrl-names = "default";
+ pinctrl-0 = <&led_pins>;
+
+ led-1 {
+ color = <LED_COLOR_ID_ORANGE>;
+ function = LED_FUNCTION_INDICATOR;
+ gpios = <&gpio3 RK_PB7 GPIO_ACTIVE_HIGH>;
+ };
+ };
+
+ sound {
+ compatible = "simple-audio-card";
+ pinctrl-names = "default";
+ pinctrl-0 = <&hp_detect>;
+ simple-audio-card,name = "Analog";
+ simple-audio-card,aux-devs = <&speaker_amp>, <&headphone_amp>;
+ simple-audio-card,format = "i2s";
+ simple-audio-card,mclk-fs = <256>;
+ simple-audio-card,hp-det-gpio = <&gpio1 RK_PD5 GPIO_ACTIVE_LOW>;
+ simple-audio-card,bitclock-master = <&daicpu>;
+ simple-audio-card,frame-master = <&daicpu>;
+ /* SARADC_IN3 is used as MIC detection / key input */
+
+ simple-audio-card,widgets =
+ "Microphone", "Onboard Microphone",
+ "Microphone", "Microphone Jack",
+ "Speaker", "Speaker",
+ "Headphone", "Headphones";
+
+ simple-audio-card,routing =
+ "Headphones", "LOUT1",
+ "Headphones", "ROUT1",
+ "Speaker", "LOUT2",
+ "Speaker", "ROUT2",
+
+ "Headphones", "Headphones Amp OUTL",
+ "Headphones", "Headphones Amp OUTR",
+ "Headphones Amp INL", "LOUT1",
+ "Headphones Amp INR", "ROUT1",
+
+ "Speaker", "Speaker Amp OUTL",
+ "Speaker", "Speaker Amp OUTR",
+ "Speaker Amp INL", "LOUT2",
+ "Speaker Amp INR", "ROUT2",
+
+ /* single ended signal to LINPUT1 */
+ "LINPUT1", "Microphone Jack",
+ "RINPUT1", "Microphone Jack",
+ /* differential signal */
+ "LINPUT2", "Onboard Microphone",
+ "RINPUT2", "Onboard Microphone";
+
+ daicpu: simple-audio-card,cpu {
+ sound-dai = <&i2s0_8ch>;
+ system-clock-frequency = <12288000>;
+ };
+
+ daicodec: simple-audio-card,codec {
+ sound-dai = <&es8388>;
+ system-clock-frequency = <12288000>;
+ };
+ };
+
+ vcc12v_dcin: vcc12v-dcin-regulator {
+ compatible = "regulator-fixed";
+ regulator-name = "vcc12v_dcin";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <12000000>;
+ regulator-max-microvolt = <12000000>;
+ };
+
+ vcc3v3_bt: vcc3v3-bt-regulator {
+ compatible = "regulator-fixed";
+ enable-active-high;
+ gpios = <&gpio3 RK_PA6 GPIO_ACTIVE_HIGH>;
+ regulator-name = "vcc3v3_bt";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ startup-delay-us = <50000>;
+ vin-supply = <&vcc_3v3_s0>;
+ };
+
+ vcc3v3_pcie30: vcc3v3-pcie30-regulator {
+ compatible = "regulator-fixed";
+ enable-active-high;
+ gpios = <&gpio3 RK_PC3 GPIO_ACTIVE_HIGH>;
+ regulator-name = "vcc3v3_pcie30";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ startup-delay-us = <5000>;
+ vin-supply = <&vcc12v_dcin>;
+ };
+
+ vcc3v3_wf: vcc3v3-wf-regulator {
+ compatible = "regulator-fixed";
+ enable-active-high;
+ gpios = <&gpio3 RK_PB1 GPIO_ACTIVE_HIGH>;
+ regulator-name = "vcc3v3_wf";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ startup-delay-us = <50000>;
+ vin-supply = <&vcc_3v3_s0>;
+ };
+
+ vcc4v0_sys: vcc4v0-sys-regulator {
+ compatible = "regulator-fixed";
+ regulator-name = "vcc4v0_sys";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <4000000>;
+ regulator-max-microvolt = <4000000>;
+ vin-supply = <&vcc12v_dcin>;
+ };
+
+ vcc5v0_host: vcc5v0-host-regulator {
+ compatible = "regulator-fixed";
+ enable-active-high;
+ gpio = <&gpio4 RK_PB0 GPIO_ACTIVE_HIGH>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&vcc5v0_host_en>;
+ regulator-name = "vcc5v0_host";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <5000000>;
+ regulator-max-microvolt = <5000000>;
+ vin-supply = <&vcc5v0_usb>;
+ };
+
+ vcc5v0_usb: vcc5v0-usb-regulator {
+ compatible = "regulator-fixed";
+ regulator-name = "vcc5v0_usb";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <5000000>;
+ regulator-max-microvolt = <5000000>;
+ vin-supply = <&vcc12v_dcin>;
+ };
+};
+
+&combphy0_ps {
+ status = "okay";
+};
+
+&combphy1_ps {
+ status = "okay";
+};
+
+&combphy2_psu {
+ status = "okay";
+};
+
+&cpu_b0 {
+ cpu-supply = <&vdd_cpu_big0_s0>;
+};
+
+&cpu_b1 {
+ cpu-supply = <&vdd_cpu_big0_s0>;
+};
+
+&cpu_b2 {
+ cpu-supply = <&vdd_cpu_big1_s0>;
+};
+
+&cpu_b3 {
+ cpu-supply = <&vdd_cpu_big1_s0>;
+};
+
+&cpu_l0 {
+ cpu-supply = <&vdd_cpu_lit_s0>;
+};
+
+&cpu_l1 {
+ cpu-supply = <&vdd_cpu_lit_s0>;
+};
+
+&cpu_l2 {
+ cpu-supply = <&vdd_cpu_lit_s0>;
+};
+
+&cpu_l3 {
+ cpu-supply = <&vdd_cpu_lit_s0>;
+};
+
+&gmac0 {
+ clock_in_out = "output";
+ phy-handle = <&rgmii_phy>;
+ phy-mode = "rgmii-rxid";
+ pinctrl-names = "default";
+ pinctrl-0 = <&gmac0_miim
+ &gmac0_tx_bus2
+ &gmac0_rx_bus2
+ &gmac0_rgmii_clk
+ &gmac0_rgmii_bus>;
+ rx_delay = <0x00>;
+ tx_delay = <0x43>;
+ status = "okay";
+};
+
+&i2c2 {
+ status = "okay";
+
+ hym8563: rtc@51 {
+ compatible = "haoyu,hym8563";
+ reg = <0x51>;
+ #clock-cells = <0>;
+ clock-output-names = "hym8563";
+ interrupt-parent = <&gpio0>;
+ interrupts = <RK_PD4 IRQ_TYPE_LEVEL_LOW>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&hym8563_int>;
+ wakeup-source;
+ };
+};
+
+&i2c7 {
+ status = "okay";
+
+ es8388: audio-codec@11 {
+ compatible = "everest,es8388";
+ reg = <0x11>;
+ assigned-clocks = <&cru I2S0_8CH_MCLKOUT>;
+ assigned-clock-rates = <12288000>;
+ clocks = <&cru I2S0_8CH_MCLKOUT>;
+ clock-names = "mclk";
+ AVDD-supply = <&avcc_1v8_codec_s0>;
+ DVDD-supply = <&avcc_1v8_codec_s0>;
+ HPVDD-supply = <&vcc_3v3_s0>;
+ PVDD-supply = <&vcc_3v3_s0>;
+ #sound-dai-cells = <0>;
+ };
+};
+
+&i2s0_8ch {
+ pinctrl-names = "default";
+ pinctrl-0 = <&i2s0_lrck
+ &i2s0_mclk
+ &i2s0_sclk
+ &i2s0_sdi0
+ &i2s0_sdo0>;
+ status = "okay";
+};
+
+&mdio0 {
+ rgmii_phy: ethernet-phy@1 {
+ /* RTL8211F */
+ compatible = "ethernet-phy-id001c.c916";
+ reg = <0x1>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&rtl8211f_rst>;
+ reset-assert-us = <20000>;
+ reset-deassert-us = <100000>;
+ reset-gpios = <&gpio4 RK_PB3 GPIO_ACTIVE_LOW>;
+ };
+};
+
+&pinctrl {
+ hym8563 {
+ hym8563_int: hym8563-int {
+ rockchip,pins = <0 RK_PD4 RK_FUNC_GPIO &pcfg_pull_up>;
+ };
+ };
+
+ leds {
+ led_pins: led-pins {
+ rockchip,pins = <3 RK_PB7 RK_FUNC_GPIO &pcfg_pull_up>;
+ };
+ };
+
+ rtl8111 {
+ rtl8111_isolate: rtl8111-isolate {
+ rockchip,pins = <1 RK_PA4 RK_FUNC_GPIO &pcfg_pull_up>;
+ };
+ };
+
+ rtl8211f {
+ rtl8211f_rst: rtl8211f-rst {
+ rockchip,pins = <4 RK_PB3 RK_FUNC_GPIO &pcfg_pull_none>;
+ };
+
+ };
+
+ sound {
+ hp_detect: hp-detect {
+ rockchip,pins = <1 RK_PD5 RK_FUNC_GPIO &pcfg_pull_none>;
+ };
+ };
+
+ usb {
+ vcc5v0_host_en: vcc5v0-host-en {
+ rockchip,pins = <4 RK_PB0 RK_FUNC_GPIO &pcfg_pull_none>;
+ };
+ };
+};
+
+/* WIFI */
+&pcie2x1l0 {
+ reset-gpios = <&gpio4 RK_PA5 GPIO_ACTIVE_HIGH>;
+ vpcie3v3-supply = <&vcc3v3_wf>;
+ status = "okay";
+};
+
+/* GMAC1 */
+&pcie2x1l1 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&rtl8111_isolate>;
+ reset-gpios = <&gpio4 RK_PA2 GPIO_ACTIVE_HIGH>;
+ status = "okay";
+};
+
+&pcie30phy {
+ status = "okay";
+};
+
+&pcie3x4 {
+ reset-gpios = <&gpio4 RK_PB6 GPIO_ACTIVE_HIGH>;
+ vpcie3v3-supply = <&vcc3v3_pcie30>;
+ status = "okay";
+};
+
+&saradc {
+ vref-supply = <&vcc_1v8_s0>;
+ status = "okay";
+};
+
+&sata0 {
+ status = "okay";
+};
+
+&sdhci {
+ bus-width = <8>;
+ no-sdio;
+ no-sd;
+ non-removable;
+ max-frequency = <150000000>;
+ mmc-hs400-1_8v;
+ mmc-hs400-enhanced-strobe;
+ status = "okay";
+};
+
+&sdmmc {
+ bus-width = <4>;
+ cap-sd-highspeed;
+ cd-gpios = <&gpio0 RK_PA4 GPIO_ACTIVE_LOW>;
+ disable-wp;
+ max-frequency = <150000000>;
+ no-sdio;
+ no-mmc;
+ sd-uhs-sdr104;
+ vmmc-supply = <&vcc_3v3_s3>;
+ vqmmc-supply = <&vccio_sd_s0>;
+ status = "okay";
+};
+
+&spi2 {
+ assigned-clocks = <&cru CLK_SPI2>;
+ assigned-clock-rates = <200000000>;
+ num-cs = <2>;
+ status = "okay";
+
+ pmic@0 {
+ compatible = "rockchip,rk806";
+ reg = <0x0>;
+ #gpio-cells = <2>;
+ gpio-controller;
+ interrupt-parent = <&gpio0>;
+ interrupts = <7 IRQ_TYPE_LEVEL_LOW>;
+ pinctrl-0 = <&pmic_pins>, <&rk806_dvs1_null>,
+ <&rk806_dvs2_null>, <&rk806_dvs3_null>;
+ pinctrl-names = "default";
+ spi-max-frequency = <1000000>;
+
+ vcc1-supply = <&vcc4v0_sys>;
+ vcc2-supply = <&vcc4v0_sys>;
+ vcc3-supply = <&vcc4v0_sys>;
+ vcc4-supply = <&vcc4v0_sys>;
+ vcc5-supply = <&vcc4v0_sys>;
+ vcc6-supply = <&vcc4v0_sys>;
+ vcc7-supply = <&vcc4v0_sys>;
+ vcc8-supply = <&vcc4v0_sys>;
+ vcc9-supply = <&vcc4v0_sys>;
+ vcc10-supply = <&vcc4v0_sys>;
+ vcc11-supply = <&vcc_2v0_pldo_s3>;
+ vcc12-supply = <&vcc4v0_sys>;
+ vcc13-supply = <&vcc_1v1_nldo_s3>;
+ vcc14-supply = <&vcc_1v1_nldo_s3>;
+ vcca-supply = <&vcc4v0_sys>;
+
+ rk806_dvs1_null: dvs1-null-pins {
+ pins = "gpio_pwrctrl1";
+ function = "pin_fun0";
+ };
+
+ rk806_dvs2_null: dvs2-null-pins {
+ pins = "gpio_pwrctrl2";
+ function = "pin_fun0";
+ };
+
+ rk806_dvs3_null: dvs3-null-pins {
+ pins = "gpio_pwrctrl3";
+ function = "pin_fun0";
+ };
+
+ regulators {
+ vdd_gpu_s0: dcdc-reg1 {
+ regulator-name = "vdd_gpu_s0";
+ regulator-boot-on;
+ regulator-enable-ramp-delay = <400>;
+ regulator-min-microvolt = <550000>;
+ regulator-max-microvolt = <950000>;
+ regulator-ramp-delay = <12500>;
+
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ };
+ };
+
+ vdd_npu_s0: dcdc-reg2 {
+ regulator-name = "vdd_npu_s0";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <550000>;
+ regulator-max-microvolt = <950000>;
+ regulator-ramp-delay = <12500>;
+
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ };
+ };
+
+ vdd_log_s0: dcdc-reg3 {
+ regulator-name = "vdd_log_s0";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <675000>;
+ regulator-max-microvolt = <750000>;
+ regulator-ramp-delay = <12500>;
+
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ regulator-suspend-microvolt = <750000>;
+ };
+ };
+
+ vdd_vdenc_s0: dcdc-reg4 {
+ regulator-name = "vdd_vdenc_s0";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <550000>;
+ regulator-max-microvolt = <950000>;
+ regulator-ramp-delay = <12500>;
+
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ };
+
+ };
+
+ vdd_gpu_mem_s0: dcdc-reg5 {
+ regulator-name = "vdd_gpu_mem_s0";
+ regulator-boot-on;
+ regulator-enable-ramp-delay = <400>;
+ regulator-min-microvolt = <675000>;
+ regulator-max-microvolt = <950000>;
+ regulator-ramp-delay = <12500>;
+
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ };
+
+ };
+
+ vdd_npu_mem_s0: dcdc-reg6 {
+ regulator-name = "vdd_npu_mem_s0";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <675000>;
+ regulator-max-microvolt = <950000>;
+ regulator-ramp-delay = <12500>;
+
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ };
+
+ };
+
+ vcc_2v0_pldo_s3: dcdc-reg7 {
+ regulator-name = "vdd_2v0_pldo_s3";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <2000000>;
+ regulator-max-microvolt = <2000000>;
+ regulator-ramp-delay = <12500>;
+
+ regulator-state-mem {
+ regulator-on-in-suspend;
+ regulator-suspend-microvolt = <2000000>;
+ };
+ };
+
+ vdd_vdenc_mem_s0: dcdc-reg8 {
+ regulator-name = "vdd_vdenc_mem_s0";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <675000>;
+ regulator-max-microvolt = <950000>;
+ regulator-ramp-delay = <12500>;
+
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ };
+ };
+
+ vdd2_ddr_s3: dcdc-reg9 {
+ regulator-name = "vdd2_ddr_s3";
+ regulator-always-on;
+ regulator-boot-on;
+
+ regulator-state-mem {
+ regulator-on-in-suspend;
+ };
+ };
+
+ vcc_1v1_nldo_s3: dcdc-reg10 {
+ regulator-name = "vcc_1v1_nldo_s3";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <1100000>;
+ regulator-max-microvolt = <1100000>;
+ regulator-ramp-delay = <12500>;
+
+ regulator-state-mem {
+ regulator-on-in-suspend;
+ regulator-suspend-microvolt = <1100000>;
+ };
+ };
+
+ avcc_1v8_s0: pldo-reg1 {
+ regulator-name = "avcc_1v8_s0";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-ramp-delay = <12500>;
+
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ };
+ };
+
+ vdd1_1v8_ddr_s3: pldo-reg2 {
+ regulator-name = "vdd1_1v8_ddr_s3";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-ramp-delay = <12500>;
+
+ regulator-state-mem {
+ regulator-on-in-suspend;
+ regulator-suspend-microvolt = <1800000>;
+ };
+ };
+
+ avcc_1v8_codec_s0: pldo-reg3 {
+ regulator-name = "avcc_1v8_codec_s0";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-ramp-delay = <12500>;
+
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ };
+ };
+
+ vcc_3v3_s3: pldo-reg4 {
+ regulator-name = "vcc_3v3_s3";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-ramp-delay = <12500>;
+
+ regulator-state-mem {
+ regulator-on-in-suspend;
+ regulator-suspend-microvolt = <3300000>;
+ };
+ };
+
+ vccio_sd_s0: pldo-reg5 {
+ regulator-name = "vccio_sd_s0";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-ramp-delay = <12500>;
+
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ };
+ };
+
+ vcc_1v8_s3: pldo-reg6 {
+ regulator-name = "vcc_1v8_s3";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-ramp-delay = <12500>;
+
+ regulator-state-mem {
+ regulator-on-in-suspend;
+ regulator-suspend-microvolt = <1800000>;
+ };
+ };
+
+ vdd_0v75_s3: nldo-reg1 {
+ regulator-name = "vdd_0v75_s3";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <750000>;
+ regulator-max-microvolt = <750000>;
+ regulator-ramp-delay = <12500>;
+
+ regulator-state-mem {
+ regulator-on-in-suspend;
+ regulator-suspend-microvolt = <750000>;
+ };
+ };
+
+ /* reserved for LPDDR5, unused? */
+ vdd2l_0v9_ddr_s3: nldo-reg2 {
+ regulator-name = "vdd2l_0v9_ddr_s3";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <900000>;
+ regulator-max-microvolt = <900000>;
+
+ regulator-state-mem {
+ regulator-on-in-suspend;
+ regulator-suspend-microvolt = <900000>;
+ };
+ };
+
+ vdd_0v75_hdmi_edp_s0: nldo-reg3 {
+ regulator-name = "vdd_0v75_hdmi_edp_s0";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <750000>;
+ regulator-max-microvolt = <750000>;
+
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ };
+ };
+
+ avdd_0v75_s0: nldo-reg4 {
+ regulator-name = "avdd_0v75_s0";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <750000>;
+ regulator-max-microvolt = <750000>;
+
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ };
+ };
+
+ vdd_0v85_s0: nldo-reg5 {
+ regulator-name = "vdd_0v85_s0";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <850000>;
+ regulator-max-microvolt = <850000>;
+
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ };
+ };
+ };
+ };
+
+ pmic@1 {
+ compatible = "rockchip,rk806";
+ reg = <0x01>;
+ #gpio-cells = <2>;
+ gpio-controller;
+ interrupt-parent = <&gpio0>;
+ interrupts = <7 IRQ_TYPE_LEVEL_LOW>;
+ pinctrl-0 = <&rk806_slave_dvs1_null>, <&rk806_slave_dvs2_null>,
+ <&rk806_slave_dvs3_null>;
+ pinctrl-names = "default";
+ spi-max-frequency = <1000000>;
+
+ vcc1-supply = <&vcc4v0_sys>;
+ vcc2-supply = <&vcc4v0_sys>;
+ vcc3-supply = <&vcc4v0_sys>;
+ vcc4-supply = <&vcc4v0_sys>;
+ vcc5-supply = <&vcc4v0_sys>;
+ vcc6-supply = <&vcc4v0_sys>;
+ vcc7-supply = <&vcc4v0_sys>;
+ vcc8-supply = <&vcc4v0_sys>;
+ vcc9-supply = <&vcc4v0_sys>;
+ vcc10-supply = <&vcc4v0_sys>;
+ vcc11-supply = <&vcc_2v0_pldo_s3>;
+ vcc12-supply = <&vcc4v0_sys>;
+ vcc13-supply = <&vcc_1v1_nldo_s3>;
+ vcc14-supply = <&vcc_2v0_pldo_s3>;
+ vcca-supply = <&vcc4v0_sys>;
+
+ rk806_slave_dvs1_null: dvs1-null-pins {
+ pins = "gpio_pwrctrl1";
+ function = "pin_fun0";
+ };
+
+ rk806_slave_dvs2_null: dvs2-null-pins {
+ pins = "gpio_pwrctrl2";
+ function = "pin_fun0";
+ };
+
+ rk806_slave_dvs3_null: dvs3-null-pins {
+ pins = "gpio_pwrctrl3";
+ function = "pin_fun0";
+ };
+
+ regulators {
+ vdd_cpu_big1_s0: dcdc-reg1 {
+ regulator-name = "vdd_cpu_big1_s0";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <550000>;
+ regulator-max-microvolt = <1050000>;
+ regulator-ramp-delay = <12500>;
+
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ };
+ };
+
+ vdd_cpu_big0_s0: dcdc-reg2 {
+ regulator-name = "vdd_cpu_big0_s0";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <550000>;
+ regulator-max-microvolt = <1050000>;
+ regulator-ramp-delay = <12500>;
+
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ };
+ };
+
+ vdd_cpu_lit_s0: dcdc-reg3 {
+ regulator-name = "vdd_cpu_lit_s0";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <550000>;
+ regulator-max-microvolt = <950000>;
+ regulator-ramp-delay = <12500>;
+
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ };
+ };
+
+ vcc_3v3_s0: dcdc-reg4 {
+ regulator-name = "vcc_3v3_s0";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-ramp-delay = <12500>;
+
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ };
+ };
+
+ vdd_cpu_big1_mem_s0: dcdc-reg5 {
+ regulator-name = "vdd_cpu_big1_mem_s0";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <675000>;
+ regulator-max-microvolt = <1050000>;
+ regulator-ramp-delay = <12500>;
+
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ };
+ };
+
+
+ vdd_cpu_big0_mem_s0: dcdc-reg6 {
+ regulator-name = "vdd_cpu_big0_mem_s0";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <675000>;
+ regulator-max-microvolt = <1050000>;
+ regulator-ramp-delay = <12500>;
+
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ };
+ };
+
+ vcc_1v8_s0: dcdc-reg7 {
+ regulator-name = "vcc_1v8_s0";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-ramp-delay = <12500>;
+
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ };
+ };
+
+ vdd_cpu_lit_mem_s0: dcdc-reg8 {
+ regulator-name = "vdd_cpu_lit_mem_s0";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <675000>;
+ regulator-max-microvolt = <950000>;
+ regulator-ramp-delay = <12500>;
+
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ };
+ };
+
+ vddq_ddr_s0: dcdc-reg9 {
+ regulator-name = "vddq_ddr_s0";
+ regulator-always-on;
+ regulator-boot-on;
+
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ };
+ };
+
+ vdd_ddr_s0: dcdc-reg10 {
+ regulator-name = "vdd_ddr_s0";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <675000>;
+ regulator-max-microvolt = <900000>;
+ regulator-ramp-delay = <12500>;
+
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ };
+ };
+
+ /* reserved, unused? */
+ vcc_1v8_cam_s0: pldo-reg1 {
+ regulator-name = "vcc_1v8_cam_s0";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-ramp-delay = <12500>;
+
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ };
+ };
+
+ avdd1v8_ddr_pll_s0: pldo-reg2 {
+ regulator-name = "avdd1v8_ddr_pll_s0";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-ramp-delay = <12500>;
+
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ };
+ };
+
+ vdd_1v8_pll_s0: pldo-reg3 {
+ regulator-name = "vdd_1v8_pll_s0";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-ramp-delay = <12500>;
+
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ };
+ };
+
+ /* reserved, unused? */
+ vcc_3v3_sd_s0: pldo-reg4 {
+ regulator-name = "vcc_3v3_sd_s0";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-ramp-delay = <12500>;
+
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ };
+ };
+
+ /* reserved, unused? */
+ vcc_2v8_cam_s0: pldo-reg5 {
+ regulator-name = "vcc_2v8_cam_s0";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <2800000>;
+ regulator-max-microvolt = <2800000>;
+ regulator-ramp-delay = <12500>;
+
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ };
+ };
+
+ /* unused */
+ pldo6_s3: pldo-reg6 {
+ regulator-name = "pldo6_s3";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+
+ regulator-state-mem {
+ regulator-on-in-suspend;
+ regulator-suspend-microvolt = <1800000>;
+ };
+ };
+
+ vdd_0v75_pll_s0: nldo-reg1 {
+ regulator-name = "vdd_0v75_pll_s0";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <750000>;
+ regulator-max-microvolt = <750000>;
+ regulator-ramp-delay = <12500>;
+
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ };
+ };
+
+ vdd_ddr_pll_s0: nldo-reg2 {
+ regulator-name = "vdd_ddr_pll_s0";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <850000>;
+ regulator-max-microvolt = <850000>;
+
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ };
+ };
+
+ avdd_0v85_s0: nldo-reg3 {
+ regulator-name = "avdd_0v85_s0";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <850000>;
+ regulator-max-microvolt = <850000>;
+ regulator-ramp-delay = <12500>;
+
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ };
+ };
+
+ /* reserved, unused */
+ avdd_1v2_cam_s0: nldo-reg4 {
+ regulator-name = "avdd_1v2_cam_s0";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <1200000>;
+ regulator-max-microvolt = <1200000>;
+ regulator-ramp-delay = <12500>;
+
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ };
+ };
+
+ avdd_1v2_s0: nldo-reg5 {
+ regulator-name = "avdd_1v2_s0";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <1200000>;
+ regulator-max-microvolt = <1200000>;
+ regulator-ramp-delay = <12500>;
+
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ };
+ };
+ };
+ };
+};
+
+&tsadc {
+ status = "okay";
+};
+
+&u2phy2 {
+ status = "okay";
+};
+
+&u2phy2_host {
+ phy-supply = <&vcc5v0_host>;
+ status = "okay";
+};
+
+&u2phy3 {
+ status = "okay";
+};
+
+&u2phy3_host {
+ phy-supply = <&vcc5v0_host>;
+ status = "okay";
+};
+
+&uart2 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&uart2m0_xfer>;
+ status = "okay";
+};
+
+&usb_host0_ehci {
+ status = "okay";
+};
+
+&usb_host0_ohci {
+ status = "okay";
+};
+
+&usb_host1_ehci {
+ status = "okay";
+};
+
+&usb_host1_ohci {
+ status = "okay";
+};
diff --git a/arch/arm/dts/rv1126-u-boot.dtsi b/arch/arm/dts/rv1126-u-boot.dtsi
index 5e34827..4485980 100644
--- a/arch/arm/dts/rv1126-u-boot.dtsi
+++ b/arch/arm/dts/rv1126-u-boot.dtsi
@@ -15,6 +15,18 @@
compatible = "rockchip,rv1126-dmc";
bootph-all;
};
+
+ otp: otp@ff5c0000 {
+ compatible = "rockchip,rv1126-otp";
+ reg = <0xff5c0000 0x1000>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ status = "okay";
+
+ cpu_id: id@7 {
+ reg = <0x07 0x10>;
+ };
+ };
};
&gpio0 {
@@ -26,15 +38,15 @@
};
&grf {
- bootph-pre-ram;
+ bootph-all;
};
&pmu {
- bootph-pre-ram;
+ bootph-all;
};
&pmugrf {
- bootph-pre-ram;
+ bootph-all;
};
&xin24m {
diff --git a/arch/arm/dts/stm32mp157c-ev1-u-boot.dtsi b/arch/arm/dts/stm32mp157c-ev1-u-boot.dtsi
index 1f7fdbc..eb283ca 100644
--- a/arch/arm/dts/stm32mp157c-ev1-u-boot.dtsi
+++ b/arch/arm/dts/stm32mp157c-ev1-u-boot.dtsi
@@ -135,20 +135,28 @@
&qspi_bk1_pins_a {
bootph-pre-ram;
- pins1 {
+ pins {
bootph-pre-ram;
};
- pins2 {
+};
+
+&qspi_cs1_pins_a {
+ bootph-pre-ram;
+ pins {
bootph-pre-ram;
};
};
&qspi_bk2_pins_a {
bootph-pre-ram;
- pins1 {
+ pins {
bootph-pre-ram;
};
- pins2 {
+};
+
+&qspi_cs2_pins_a {
+ bootph-pre-ram;
+ pins {
bootph-pre-ram;
};
};
diff --git a/arch/arm/dts/stm32mp15xx-dhcom-u-boot.dtsi b/arch/arm/dts/stm32mp15xx-dhcom-u-boot.dtsi
index f12941b..2f70b06 100644
--- a/arch/arm/dts/stm32mp15xx-dhcom-u-boot.dtsi
+++ b/arch/arm/dts/stm32mp15xx-dhcom-u-boot.dtsi
@@ -134,20 +134,14 @@
&qspi_bk1_pins_a {
bootph-pre-ram;
- pins1 {
+ pins {
bootph-pre-ram;
};
- pins2 {
- bootph-pre-ram;
- };
};
-&qspi_bk2_pins_a {
+&qspi_cs1_pins_a {
bootph-pre-ram;
- pins1 {
- bootph-pre-ram;
- };
- pins2 {
+ pins {
bootph-pre-ram;
};
};
diff --git a/arch/arm/dts/stm32mp15xx-dhcor-u-boot.dtsi b/arch/arm/dts/stm32mp15xx-dhcor-u-boot.dtsi
index eb905ad..552b35d 100644
--- a/arch/arm/dts/stm32mp15xx-dhcor-u-boot.dtsi
+++ b/arch/arm/dts/stm32mp15xx-dhcor-u-boot.dtsi
@@ -98,10 +98,14 @@
&qspi_bk1_pins_a {
bootph-pre-ram;
- pins1 {
+ pins {
bootph-pre-ram;
};
- pins2 {
+};
+
+&qspi_cs1_pins_a {
+ bootph-pre-ram;
+ pins {
bootph-pre-ram;
};
};
diff --git a/arch/arm/dts/tegra20-paz00.dts b/arch/arm/dts/tegra20-paz00.dts
index ecf9fbd..5d8f210 100644
--- a/arch/arm/dts/tegra20-paz00.dts
+++ b/arch/arm/dts/tegra20-paz00.dts
@@ -315,20 +315,19 @@
clock-frequency = <100000>;
};
- nvec@7000c500 {
+ i2c@7000c500 {
compatible = "nvidia,nvec";
- reg = <0x7000c500 0x100>;
- interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>;
- #address-cells = <1>;
- #size-cells = <0>;
+
+ /delete-property/ #address-cells;
+ /delete-property/ #size-cells;
+ /delete-property/ dmas;
+ /delete-property/ dma-names;
+
clock-frequency = <80000>;
request-gpios = <&gpio TEGRA_GPIO(V, 2) GPIO_ACTIVE_HIGH>;
slave-addr = <138>;
- clocks = <&tegra_car TEGRA20_CLK_I2C3>,
- <&tegra_car TEGRA20_CLK_PLL_P_OUT3>;
- clock-names = "div-clk", "fast-clk";
- resets = <&tegra_car 67>;
- reset-names = "i2c";
+
+ status = "okay";
};
i2c@7000d000 {
diff --git a/arch/arm/dts/tegra30-asus-grouper-common.dtsi b/arch/arm/dts/tegra30-asus-grouper-common.dtsi
index fcf31e2..c927738 100644
--- a/arch/arm/dts/tegra30-asus-grouper-common.dtsi
+++ b/arch/arm/dts/tegra30-asus-grouper-common.dtsi
@@ -71,6 +71,13 @@
dr_mode = "otg";
};
+ usb-phy@7d000000 {
+ status = "okay";
+ nvidia,hssync-start-delay = <0>;
+ nvidia,xcvr-lsfslew = <2>;
+ nvidia,xcvr-lsrslew = <2>;
+ };
+
backlight: backlight {
compatible = "pwm-backlight";
diff --git a/arch/arm/dts/tegra30-asus-nexus7-grouper-E1565.dts b/arch/arm/dts/tegra30-asus-nexus7-grouper-E1565.dts
index 945ae40..bfc675c 100644
--- a/arch/arm/dts/tegra30-asus-nexus7-grouper-E1565.dts
+++ b/arch/arm/dts/tegra30-asus-nexus7-grouper-E1565.dts
@@ -35,6 +35,7 @@
regulator-name = "vcore_emmc";
regulator-min-microvolt = <2850000>;
regulator-max-microvolt = <2850000>;
+ regulator-boot-on;
};
};
};
diff --git a/arch/arm/dts/tegra30-asus-nexus7-grouper-PM269.dts b/arch/arm/dts/tegra30-asus-nexus7-grouper-PM269.dts
index 4363bfc..cf03011 100644
--- a/arch/arm/dts/tegra30-asus-nexus7-grouper-PM269.dts
+++ b/arch/arm/dts/tegra30-asus-nexus7-grouper-PM269.dts
@@ -36,6 +36,7 @@
regulator-name = "vdd_emmc_core";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
+ regulator-boot-on;
};
};
};
diff --git a/arch/arm/dts/tegra30-asus-nexus7-tilapia-E1565.dts b/arch/arm/dts/tegra30-asus-nexus7-tilapia-E1565.dts
index 89348fd..ef8b2b5 100644
--- a/arch/arm/dts/tegra30-asus-nexus7-tilapia-E1565.dts
+++ b/arch/arm/dts/tegra30-asus-nexus7-tilapia-E1565.dts
@@ -35,6 +35,7 @@
regulator-name = "vcore_emmc";
regulator-min-microvolt = <2850000>;
regulator-max-microvolt = <2850000>;
+ regulator-boot-on;
};
};
};
diff --git a/arch/arm/dts/tegra30-asus-p1801-t.dts b/arch/arm/dts/tegra30-asus-p1801-t.dts
index 39f7caf..19de984 100644
--- a/arch/arm/dts/tegra30-asus-p1801-t.dts
+++ b/arch/arm/dts/tegra30-asus-p1801-t.dts
@@ -101,6 +101,7 @@
regulator-name = "vdd_emmc_core";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
+ regulator-boot-on;
};
/* uSD slot VDD */
@@ -108,6 +109,7 @@
regulator-name = "vdd_usd";
regulator-min-microvolt = <3100000>;
regulator-max-microvolt = <3100000>;
+ regulator-boot-on;
};
/* uSD slot VDDIO */
@@ -148,17 +150,32 @@
dr_mode = "otg";
};
+ usb-phy@7d000000 {
+ status = "okay";
+ nvidia,hssync-start-delay = <0>;
+ nvidia,xcvr-lsfslew = <2>;
+ nvidia,xcvr-lsrslew = <2>;
+ };
+
/* Mini USB port */
usb2: usb@7d004000 {
status = "okay";
nvidia,vbus-gpio = <&gpio TEGRA_GPIO(H, 7) GPIO_ACTIVE_HIGH>;
};
+ usb-phy@7d004000 {
+ status = "okay";
+ };
+
/* Dock's USB port */
usb3: usb@7d008000 {
status = "okay";
};
+ usb-phy@7d008000 {
+ status = "okay";
+ };
+
/* PMIC has a built-in 32KHz oscillator which is used by PMC */
clk32k_in: clock-32k {
compatible = "fixed-clock";
diff --git a/arch/arm/dts/tegra30-asus-tf600t.dts b/arch/arm/dts/tegra30-asus-tf600t.dts
index fd9d11c..3f11d33 100644
--- a/arch/arm/dts/tegra30-asus-tf600t.dts
+++ b/arch/arm/dts/tegra30-asus-tf600t.dts
@@ -84,12 +84,14 @@
regulator-name = "vdd_1v2_backlight";
regulator-min-microvolt = <1200000>;
regulator-max-microvolt = <1200000>;
+ regulator-boot-on;
};
vcore_lcd: vdd2 {
regulator-name = "vcore_lcd";
regulator-min-microvolt = <1500000>;
regulator-max-microvolt = <1500000>;
+ regulator-boot-on;
};
vdd_1v8_vio: vddio {
@@ -105,6 +107,7 @@
regulator-name = "vdd_emmc_core";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
+ regulator-boot-on;
};
/* uSD slot VDDIO */
@@ -119,6 +122,7 @@
regulator-name = "avdd_dsi_csi";
regulator-min-microvolt = <1200000>;
regulator-max-microvolt = <1200000>;
+ regulator-boot-on;
};
};
};
@@ -161,11 +165,22 @@
dr_mode = "otg";
};
+ usb-phy@7d000000 {
+ status = "okay";
+ nvidia,hssync-start-delay = <0>;
+ nvidia,xcvr-lsfslew = <2>;
+ nvidia,xcvr-lsrslew = <2>;
+ };
+
/* Dock's USB port */
usb3: usb@7d008000 {
status = "okay";
};
+ usb-phy@7d008000 {
+ status = "okay";
+ };
+
backlight: backlight {
compatible = "pwm-backlight";
diff --git a/arch/arm/dts/tegra30-asus-transformer.dtsi b/arch/arm/dts/tegra30-asus-transformer.dtsi
index 888f9ca..c4649ee 100644
--- a/arch/arm/dts/tegra30-asus-transformer.dtsi
+++ b/arch/arm/dts/tegra30-asus-transformer.dtsi
@@ -82,6 +82,7 @@
regulator-name = "vdd_emmc_core";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
+ regulator-boot-on;
};
/* uSD slot VDD */
@@ -89,6 +90,7 @@
regulator-name = "vdd_usd";
regulator-min-microvolt = <3100000>;
regulator-max-microvolt = <3100000>;
+ regulator-boot-on;
};
/* uSD slot VDDIO */
@@ -129,6 +131,13 @@
dr_mode = "otg";
};
+ usb-phy@7d000000 {
+ status = "okay";
+ nvidia,hssync-start-delay = <0>;
+ nvidia,xcvr-lsfslew = <2>;
+ nvidia,xcvr-lsrslew = <2>;
+ };
+
/* Dock's USB port */
usb3: usb@7d008000 {
status = "okay";
diff --git a/arch/arm/dts/tegra30-htc-endeavoru.dts b/arch/arm/dts/tegra30-htc-endeavoru.dts
index 5c7b2de..21cd0f9 100644
--- a/arch/arm/dts/tegra30-htc-endeavoru.dts
+++ b/arch/arm/dts/tegra30-htc-endeavoru.dts
@@ -81,6 +81,7 @@
regulator-name = "avdd_dsi_csi";
regulator-min-microvolt = <1200000>;
regulator-max-microvolt = <1200000>;
+ regulator-boot-on;
};
};
};
@@ -100,6 +101,13 @@
dr_mode = "otg";
};
+ usb-phy@7d000000 {
+ status = "okay";
+ nvidia,hssync-start-delay = <0>;
+ nvidia,xcvr-lsfslew = <2>;
+ nvidia,xcvr-lsrslew = <2>;
+ };
+
backlight: backlight {
compatible = "nvidia,tegra-pwm-backlight";
diff --git a/arch/arm/dts/tegra30-lg-x3.dtsi b/arch/arm/dts/tegra30-lg-x3.dtsi
index 6e52fc5..01936b8 100644
--- a/arch/arm/dts/tegra30-lg-x3.dtsi
+++ b/arch/arm/dts/tegra30-lg-x3.dtsi
@@ -110,6 +110,7 @@
regulator-name = "vdd_ddr_rx";
regulator-min-microvolt = <2850000>;
regulator-max-microvolt = <2850000>;
+ regulator-boot-on;
};
};
};
@@ -152,6 +153,14 @@
dr_mode = "otg";
};
+ usb-phy@7d000000 {
+ status = "okay";
+ nvidia,hssync-start-delay = <0>;
+ nvidia,xcvr-lsfslew = <2>;
+ nvidia,xcvr-lsrslew = <2>;
+ vbus-supply = <&avdd_3v3_periph>;
+ };
+
/* PMIC has a built-in 32KHz oscillator which is used by PMC */
clk32k_in: clock-32k {
compatible = "fixed-clock";
diff --git a/arch/arm/dts/tps6507x.dtsi b/arch/arm/dts/tps6507x.dtsi
index db4809d..6749d3f 100644
--- a/arch/arm/dts/tps6507x.dtsi
+++ b/arch/arm/dts/tps6507x.dtsi
@@ -1,11 +1,11 @@
// SPDX-License-Identifier: GPL-2.0-only
/*
- * Copyright (C) 2013 Texas Instruments Incorporated - http://www.ti.com/
+ * Copyright (C) 2013 Texas Instruments Incorporated - https://www.ti.com/
*/
/*
* Integrated Power Management Chip
- * http://www.ti.com/lit/ds/symlink/tps65070.pdf
+ * https://www.ti.com/lit/ds/symlink/tps65070.pdf
*/
&tps {
diff --git a/arch/arm/dts/tps65217.dtsi b/arch/arm/dts/tps65217.dtsi
index 0d463de..262e0bb 100644
--- a/arch/arm/dts/tps65217.dtsi
+++ b/arch/arm/dts/tps65217.dtsi
@@ -1,11 +1,11 @@
// SPDX-License-Identifier: GPL-2.0-only
/*
- * Copyright (C) 2012 Texas Instruments Incorporated - http://www.ti.com/
+ * Copyright (C) 2012 Texas Instruments Incorporated - https://www.ti.com/
*/
/*
* Integrated Power Management Chip
- * http://www.ti.com/lit/ds/symlink/tps65217.pdf
+ * https://www.ti.com/lit/ds/symlink/tps65217.pdf
*/
&tps {
diff --git a/arch/arm/dts/tps65910.dtsi b/arch/arm/dts/tps65910.dtsi
index a941d1e..ab3a4ff 100644
--- a/arch/arm/dts/tps65910.dtsi
+++ b/arch/arm/dts/tps65910.dtsi
@@ -1,11 +1,11 @@
// SPDX-License-Identifier: GPL-2.0-only
/*
- * Copyright (C) 2012 Texas Instruments Incorporated - http://www.ti.com/
+ * Copyright (C) 2012 Texas Instruments Incorporated - https://www.ti.com/
*/
/*
* Integrated Power Management Chip
- * http://www.ti.com/lit/ds/symlink/tps65910.pdf
+ * https://www.ti.com/lit/ds/symlink/tps65910.pdf
*/
&tps {
diff --git a/arch/arm/dts/twl4030.dtsi b/arch/arm/dts/twl4030.dtsi
index 6cb0a01..f87cea1 100644
--- a/arch/arm/dts/twl4030.dtsi
+++ b/arch/arm/dts/twl4030.dtsi
@@ -1,5 +1,5 @@
/*
- * Copyright (C) 2011 Texas Instruments Incorporated - http://www.ti.com/
+ * Copyright (C) 2011 Texas Instruments Incorporated - https://www.ti.com/
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
diff --git a/arch/arm/dts/twl6030.dtsi b/arch/arm/dts/twl6030.dtsi
index 9d588cf..8da9690 100644
--- a/arch/arm/dts/twl6030.dtsi
+++ b/arch/arm/dts/twl6030.dtsi
@@ -1,11 +1,11 @@
// SPDX-License-Identifier: GPL-2.0-only
/*
- * Copyright (C) 2011 Texas Instruments Incorporated - http://www.ti.com/
+ * Copyright (C) 2011 Texas Instruments Incorporated - https://www.ti.com/
*/
/*
* Integrated Power Management Chip
- * http://www.ti.com/lit/ds/symlink/twl6030.pdf
+ * https://www.ti.com/lit/ds/symlink/twl6030.pdf
*/
&twl {
compatible = "ti,twl6030";
diff --git a/arch/arm/dts/twl6030_omap4.dtsi b/arch/arm/dts/twl6030_omap4.dtsi
index fc498d0..5730e46 100644
--- a/arch/arm/dts/twl6030_omap4.dtsi
+++ b/arch/arm/dts/twl6030_omap4.dtsi
@@ -1,6 +1,6 @@
// SPDX-License-Identifier: GPL-2.0-only
/*
- * Copyright (C) 2013 Texas Instruments Incorporated - http://www.ti.com/
+ * Copyright (C) 2013 Texas Instruments Incorporated - https://www.ti.com/
*/
&twl {
diff --git a/arch/arm/dts/versal-mini-ospi-stacked.dts b/arch/arm/dts/versal-mini-ospi-stacked.dts
new file mode 100644
index 0000000..f46125d
--- /dev/null
+++ b/arch/arm/dts/versal-mini-ospi-stacked.dts
@@ -0,0 +1,22 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Xilinx Versal QSPI Quad Stacked DTS
+ *
+ * Copyright (C) 2018-2020 Xilinx, Inc.
+ */
+
+#include "versal-mini-ospi.dtsi"
+
+/ {
+ model = "Xilinx Versal MINI OSPI STACKED";
+};
+
+&ospi {
+ num-cs = <2>;
+};
+
+&flash0 {
+ reg = <0>, <1>;
+ stacked-memories = /bits/ 64 <0x8000000 0x8000000>; /* 128MB */
+ spi-rx-bus-width = <8>;
+};
diff --git a/arch/arm/dts/versal-mini-qspi-parallel.dts b/arch/arm/dts/versal-mini-qspi-parallel.dts
new file mode 100644
index 0000000..8485cda
--- /dev/null
+++ b/arch/arm/dts/versal-mini-qspi-parallel.dts
@@ -0,0 +1,22 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Xilinx Versal QSPI Quad Parallel DTS
+ *
+ * Copyright (C) 2018-2019 Xilinx, Inc.
+ */
+
+#include "versal-mini-qspi.dtsi"
+
+/ {
+ model = "Xilinx Versal MINI QSPI PARALLEL";
+};
+
+&qspi {
+ num-cs = <2>;
+};
+
+&flash0 {
+ reg = <0>, <1>;
+ parallel-memories = /bits/ 64 <0x8000000 0x8000000>; /* 128MB */
+ spi-rx-bus-width = <4>;
+};
diff --git a/arch/arm/dts/versal-mini-qspi-stacked.dts b/arch/arm/dts/versal-mini-qspi-stacked.dts
new file mode 100644
index 0000000..54d4277
--- /dev/null
+++ b/arch/arm/dts/versal-mini-qspi-stacked.dts
@@ -0,0 +1,22 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Xilinx Versal QSPI Quad Stacked DTS
+ *
+ * Copyright (C) 2018-2019 Xilinx, Inc.
+ */
+
+#include "versal-mini-qspi.dtsi"
+
+/ {
+ model = "Xilinx Versal MINI QSPI STACKED";
+};
+
+&qspi {
+ num-cs = <2>;
+};
+
+&flash0 {
+ reg = <0>, <1>;
+ stacked-memories = /bits/ 64 <0x8000000 0x8000000>; /* 128MB */
+ spi-rx-bus-width = <4>;
+};
diff --git a/arch/arm/dts/versal-mini-qspi-x1-single.dts b/arch/arm/dts/versal-mini-qspi-x1-single.dts
new file mode 100644
index 0000000..4d459a1
--- /dev/null
+++ b/arch/arm/dts/versal-mini-qspi-x1-single.dts
@@ -0,0 +1,17 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Xilinx Versal QSPI x1 Single DTS
+ *
+ * Copyright (C) 2018-2019 Xilinx, Inc.
+ */
+
+#include "versal-mini-qspi.dtsi"
+
+/ {
+ model = "Xilinx Versal MINI QSPI X1 SINGLE";
+};
+
+&flash0 {
+ spi-tx-bus-width = <1>;
+ spi-rx-bus-width = <1>;
+};
diff --git a/arch/arm/dts/versal-mini-qspi-x1-stacked.dts b/arch/arm/dts/versal-mini-qspi-x1-stacked.dts
new file mode 100644
index 0000000..905dc77
--- /dev/null
+++ b/arch/arm/dts/versal-mini-qspi-x1-stacked.dts
@@ -0,0 +1,23 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Xilinx Versal QSPI x1 Stacked DTS
+ *
+ * Copyright (C) 2018-2019 Xilinx, Inc.
+ */
+
+#include "versal-mini-qspi.dtsi"
+
+/ {
+ model = "Xilinx Versal MINI QSPI X1 STACKED";
+};
+
+&qspi {
+ num-cs = <2>;
+};
+
+&flash0 {
+ reg = <0>, <1>;
+ stacked-memories = /bits/ 64 <0x8000000 0x8000000>; /* 128MB */
+ spi-tx-bus-width = <1>;
+ spi-rx-bus-width = <1>;
+};
diff --git a/arch/arm/dts/versal-mini-qspi-x2-single.dts b/arch/arm/dts/versal-mini-qspi-x2-single.dts
new file mode 100644
index 0000000..d25ad7c
--- /dev/null
+++ b/arch/arm/dts/versal-mini-qspi-x2-single.dts
@@ -0,0 +1,17 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Xilinx Versal QSPI x2 Single DTS
+ *
+ * Copyright (C) 2018-2019 Xilinx, Inc.
+ */
+
+#include "versal-mini-qspi.dtsi"
+
+/ {
+ model = "Xilinx Versal MINI QSPI X2 SINGLE";
+};
+
+&flash0 {
+ spi-tx-bus-width = <2>;
+ spi-rx-bus-width = <2>;
+};
diff --git a/arch/arm/dts/versal-mini-qspi-x2-stacked.dts b/arch/arm/dts/versal-mini-qspi-x2-stacked.dts
new file mode 100644
index 0000000..0c9e740
--- /dev/null
+++ b/arch/arm/dts/versal-mini-qspi-x2-stacked.dts
@@ -0,0 +1,23 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Xilinx Versal QSPI x2 Stacked DTS
+ *
+ * Copyright (C) 2018-2019 Xilinx, Inc.
+ */
+
+#include "versal-mini-qspi.dtsi"
+
+/ {
+ model = "Xilinx Versal MINI QSPI X2 STACKED";
+};
+
+&qspi {
+ num-cs = <2>;
+};
+
+&flash0 {
+ reg = <0>, <1>;
+ stacked-memories = /bits/ 64 <0x8000000 0x8000000>; /* 128MB */
+ spi-tx-bus-width = <2>;
+ spi-rx-bus-width = <2>;
+};
diff --git a/arch/arm/dts/versal-net-mini-ospi-stacked.dts b/arch/arm/dts/versal-net-mini-ospi-stacked.dts
new file mode 100644
index 0000000..4bc954a
--- /dev/null
+++ b/arch/arm/dts/versal-net-mini-ospi-stacked.dts
@@ -0,0 +1,22 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Xilinx Versal NET OSPI Quad Stacked DTS
+ *
+ * (C) Copyright 2023, Advanced Micro Devices, Inc.
+ */
+
+#include "versal-net-mini-ospi.dtsi"
+
+/ {
+ model = "Xilinx Versal NET MINI OSPI STACKED";
+};
+
+&ospi {
+ num-cs = <2>;
+};
+
+&flash0 {
+ reg = <0>, <1>;
+ stacked-memories = /bits/ 64 <0x8000000 0x8000000>; /* 128MB */
+ spi-rx-bus-width = <8>;
+};
diff --git a/arch/arm/dts/versal-net-mini-qspi-parallel.dts b/arch/arm/dts/versal-net-mini-qspi-parallel.dts
new file mode 100644
index 0000000..edc2311
--- /dev/null
+++ b/arch/arm/dts/versal-net-mini-qspi-parallel.dts
@@ -0,0 +1,22 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Xilinx Versal NET QSPI Quad Parallel DTS
+ *
+ * (C) Copyright 2023, Advanced Micro Devices, Inc.
+ */
+
+#include "versal-net-mini-qspi.dtsi"
+
+/ {
+ model = "Xilinx Versal NET MINI QSPI PARALLEL";
+};
+
+&qspi {
+ num-cs = <2>;
+};
+
+&flash0 {
+ reg = <0>, <1>;
+ parallel-memories = /bits/ 64 <0x8000000 0x8000000>; /* 128MB */
+ spi-rx-bus-width = <4>;
+};
diff --git a/arch/arm/dts/versal-net-mini-qspi-stacked.dts b/arch/arm/dts/versal-net-mini-qspi-stacked.dts
new file mode 100644
index 0000000..920eed2
--- /dev/null
+++ b/arch/arm/dts/versal-net-mini-qspi-stacked.dts
@@ -0,0 +1,22 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Xilinx Versal NET QSPI Quad Stacked DTS
+ *
+ * (C) Copyright 2023, Advanced Micro Devices, Inc.
+ */
+
+#include "versal-net-mini-qspi.dtsi"
+
+/ {
+ model = "Xilinx Versal NET MINI QSPI STACKED";
+};
+
+&qspi {
+ num-cs = <2>;
+};
+
+&flash0 {
+ reg = <0>, <1>;
+ stacked-memories = /bits/ 64 <0x8000000 0x8000000>; /* 128MB */
+ spi-rx-bus-width = <4>;
+};
diff --git a/arch/arm/dts/versal-net-mini-qspi-x1-single.dts b/arch/arm/dts/versal-net-mini-qspi-x1-single.dts
new file mode 100644
index 0000000..856c79c
--- /dev/null
+++ b/arch/arm/dts/versal-net-mini-qspi-x1-single.dts
@@ -0,0 +1,17 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Xilinx Versal NET QSPI x1 Single DTS
+ *
+ * (C) Copyright 2023, Advanced Micro Devices, Inc.
+ */
+
+#include "versal-net-mini-qspi.dtsi"
+
+/ {
+ model = "Xilinx Versal NET MINI QSPI X1 SINGLE";
+};
+
+&flash0 {
+ spi-tx-bus-width = <1>;
+ spi-rx-bus-width = <1>;
+};
diff --git a/arch/arm/dts/versal-net-mini-qspi-x1-stacked.dts b/arch/arm/dts/versal-net-mini-qspi-x1-stacked.dts
new file mode 100644
index 0000000..5f74d98
--- /dev/null
+++ b/arch/arm/dts/versal-net-mini-qspi-x1-stacked.dts
@@ -0,0 +1,23 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Xilinx Versal NET QSPI x1 Stacked DTS
+ *
+ * (C) Copyright 2023, Advanced Micro Devices, Inc.
+ */
+
+#include "versal-net-mini-qspi.dtsi"
+
+/ {
+ model = "Xilinx Versal NET MINI QSPI X1 STACKED";
+};
+
+&qspi {
+ num-cs = <2>;
+};
+
+&flash0 {
+ reg = <0>, <1>;
+ stacked-memories = /bits/ 64 <0x8000000 0x8000000>; /* 128MB */
+ spi-tx-bus-width = <1>;
+ spi-rx-bus-width = <1>;
+};
diff --git a/arch/arm/dts/versal-net-mini-qspi-x2-single.dts b/arch/arm/dts/versal-net-mini-qspi-x2-single.dts
new file mode 100644
index 0000000..6ceaa24
--- /dev/null
+++ b/arch/arm/dts/versal-net-mini-qspi-x2-single.dts
@@ -0,0 +1,17 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Xilinx Versal NET QSPI x2 Single DTS
+ *
+ * (C) Copyright 2023, Advanced Micro Devices, Inc.
+ */
+
+#include "versal-net-mini-qspi.dtsi"
+
+/ {
+ model = "Xilinx Versal NET MINI QSPI X2 SINGLE";
+};
+
+&flash0 {
+ spi-tx-bus-width = <2>;
+ spi-rx-bus-width = <2>;
+};
diff --git a/arch/arm/dts/versal-net-mini-qspi-x2-stacked.dts b/arch/arm/dts/versal-net-mini-qspi-x2-stacked.dts
new file mode 100644
index 0000000..5f4d0b5
--- /dev/null
+++ b/arch/arm/dts/versal-net-mini-qspi-x2-stacked.dts
@@ -0,0 +1,23 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Xilinx Versal NET QSPI x2 Stacked DTS
+ *
+ * (C) Copyright 2023, Advanced Micro Devices, Inc.
+ */
+
+#include "versal-net-mini-qspi.dtsi"
+
+/ {
+ model = "Xilinx Versal NET MINI QSPI X2 STACKED";
+};
+
+&qspi {
+ num-cs = <2>;
+};
+
+&flash0 {
+ reg = <0>, <1>;
+ stacked-memories = /bits/ 64 <0x8000000 0x8000000>; /* 128MB */
+ spi-tx-bus-width = <2>;
+ spi-rx-bus-width = <2>;
+};
diff --git a/arch/arm/dts/zynq-7000.dtsi b/arch/arm/dts/zynq-7000.dtsi
index fb61fe9..f8c786a 100644
--- a/arch/arm/dts/zynq-7000.dtsi
+++ b/arch/arm/dts/zynq-7000.dtsi
@@ -306,15 +306,11 @@
compatible = "arm,pl353-nand-r2p1";
reg = <0 0 0x1000000>;
status = "disabled";
- #address-cells = <1>;
- #size-cells = <0>;
};
nor0: flash@1,0 {
status = "disabled";
compatible = "cfi-flash";
reg = <1 0 0x2000000>;
- #address-cells = <1>;
- #size-cells = <1>;
};
};
diff --git a/arch/arm/dts/zynq-cse-qspi-parallel.dts b/arch/arm/dts/zynq-cse-qspi-parallel.dts
new file mode 100644
index 0000000..afa6348
--- /dev/null
+++ b/arch/arm/dts/zynq-cse-qspi-parallel.dts
@@ -0,0 +1,22 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Xilinx CSE QSPI Quad Parallel DTS
+ *
+ * Copyright (C) 2015 - 2017 Xilinx, Inc.
+ */
+
+#include "zynq-cse-qspi.dtsi"
+
+/ {
+ model = "Zynq CSE QSPI PARALLEL Board";
+};
+
+&qspi {
+ num-cs = <2>;
+};
+
+&flash0 {
+ reg = <0>, <1>;
+ parallel-memories = /bits/ 64 <0x1000000 0x1000000>; /* 16MB */
+ spi-rx-bus-width = <4>;
+};
diff --git a/arch/arm/dts/zynq-cse-qspi-stacked.dts b/arch/arm/dts/zynq-cse-qspi-stacked.dts
new file mode 100644
index 0000000..47859f7
--- /dev/null
+++ b/arch/arm/dts/zynq-cse-qspi-stacked.dts
@@ -0,0 +1,22 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Xilinx CSE QSPI Quad Stacked DTS
+ *
+ * Copyright (C) 2015 - 2017 Xilinx, Inc.
+ */
+
+#include "zynq-cse-qspi.dtsi"
+
+/ {
+ model = "Zynq CSE QSPI STACKED Board";
+};
+
+&qspi {
+ num-cs = <2>;
+};
+
+&flash0 {
+ reg = <0>, <1>;
+ stacked-memories = /bits/ 64 <0x1000000 0x1000000>; /* 16MB */
+ spi-rx-bus-width = <4>;
+};
diff --git a/arch/arm/dts/zynq-cse-qspi-x1-single.dts b/arch/arm/dts/zynq-cse-qspi-x1-single.dts
new file mode 100644
index 0000000..c14fb42
--- /dev/null
+++ b/arch/arm/dts/zynq-cse-qspi-x1-single.dts
@@ -0,0 +1,16 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Xilinx CSE QSPI x1 Single DTS
+ *
+ * Copyright (C) 2015 - 2017 Xilinx, Inc.
+ */
+
+#include "zynq-cse-qspi.dtsi"
+
+/ {
+ model = "Zynq CSE QSPI X1 SINGLE Board";
+};
+
+&flash0 {
+ spi-rx-bus-width = <1>;
+};
diff --git a/arch/arm/dts/zynq-cse-qspi-x1-stacked.dts b/arch/arm/dts/zynq-cse-qspi-x1-stacked.dts
new file mode 100644
index 0000000..0f4d414
--- /dev/null
+++ b/arch/arm/dts/zynq-cse-qspi-x1-stacked.dts
@@ -0,0 +1,22 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Xilinx CSE QSPI x1 Stacked DTS
+ *
+ * Copyright (C) 2015 - 2017 Xilinx, Inc.
+ */
+
+#include "zynq-cse-qspi.dtsi"
+
+/ {
+ model = "Zynq CSE QSPI X1 STACKED Board";
+};
+
+&qspi {
+ num-cs = <2>;
+};
+
+&flash0 {
+ reg = <0>, <1>;
+ stacked-memories = /bits/ 64 <0x1000000 0x1000000>; /* 16MB */
+ spi-rx-bus-width = <1>;
+};
diff --git a/arch/arm/dts/zynq-cse-qspi-x2-single.dts b/arch/arm/dts/zynq-cse-qspi-x2-single.dts
new file mode 100644
index 0000000..11be063
--- /dev/null
+++ b/arch/arm/dts/zynq-cse-qspi-x2-single.dts
@@ -0,0 +1,16 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Xilinx CSE QSPI x2 Single DTS
+ *
+ * Copyright (C) 2015 - 2017 Xilinx, Inc.
+ */
+
+#include "zynq-cse-qspi.dtsi"
+
+/ {
+ model = "Zynq CSE QSPI X2 SINGLE Board";
+};
+
+&flash0 {
+ spi-rx-bus-width = <2>;
+};
diff --git a/arch/arm/dts/zynq-cse-qspi-x2-stacked.dts b/arch/arm/dts/zynq-cse-qspi-x2-stacked.dts
new file mode 100644
index 0000000..d1b42e9
--- /dev/null
+++ b/arch/arm/dts/zynq-cse-qspi-x2-stacked.dts
@@ -0,0 +1,22 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Xilinx CSE QSPI x2 Stacked DTS
+ *
+ * Copyright (C) 2015 - 2017 Xilinx, Inc.
+ */
+
+#include "zynq-cse-qspi.dtsi"
+
+/ {
+ model = "Zynq CSE QSPI X2 STACKED Board";
+};
+
+&qspi {
+ num-cs = <2>;
+};
+
+&flash0 {
+ reg = <0>, <1>;
+ stacked-memories = /bits/ 64 <0x1000000 0x1000000>; /* 16MB */
+ spi-rx-bus-width = <2>;
+};
diff --git a/arch/arm/dts/zynq-zc702.dts b/arch/arm/dts/zynq-zc702.dts
index 8d47f24..0106d7b 100644
--- a/arch/arm/dts/zynq-zc702.dts
+++ b/arch/arm/dts/zynq-zc702.dts
@@ -406,6 +406,31 @@
spi-tx-bus-width = <1>;
spi-rx-bus-width = <4>;
spi-max-frequency = <50000000>;
+ partitions {
+ compatible = "fixed-partitions";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ partition@0 {
+ label = "qspi-fsbl-uboot";
+ reg = <0x0 0x100000>;
+ };
+ partition@100000 {
+ label = "qspi-linux";
+ reg = <0x100000 0x500000>;
+ };
+ partition@600000 {
+ label = "qspi-device-tree";
+ reg = <0x600000 0x20000>;
+ };
+ partition@620000 {
+ label = "qspi-rootfs";
+ reg = <0x620000 0x5e0000>;
+ };
+ partition@c00000 {
+ label = "qspi-bitstream";
+ reg = <0xc00000 0x400000>;
+ };
+ };
};
};
diff --git a/arch/arm/dts/zynq-zc706.dts b/arch/arm/dts/zynq-zc706.dts
index 03eb016..ceea982 100644
--- a/arch/arm/dts/zynq-zc706.dts
+++ b/arch/arm/dts/zynq-zc706.dts
@@ -309,13 +309,39 @@
&qspi {
bootph-all;
status = "okay";
- num-cs = <1>;
+ num-cs = <2>;
flash@0 {
compatible = "n25q128a11", "jedec,spi-nor";
- reg = <0x0>;
+ reg = <0>, <1>;
+ parallel-memories = /bits/ 64 <0x1000000 0x1000000>; /* 16MB */
spi-tx-bus-width = <1>;
spi-rx-bus-width = <4>;
spi-max-frequency = <50000000>;
+ partitions {
+ compatible = "fixed-partitions";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ partition@0 {
+ label = "qspi-fsbl-uboot";
+ reg = <0x0 0x100000>;
+ };
+ partition@100000 {
+ label = "qspi-linux";
+ reg = <0x100000 0x500000>;
+ };
+ partition@600000 {
+ label = "qspi-device-tree";
+ reg = <0x600000 0x20000>;
+ };
+ partition@620000 {
+ label = "qspi-rootfs";
+ reg = <0x620000 0x5e0000>;
+ };
+ partition@c00000 {
+ label = "qspi-bitstream";
+ reg = <0xc00000 0x400000>;
+ };
+ };
};
};
diff --git a/arch/arm/dts/zynq-zc770-xm010.dts b/arch/arm/dts/zynq-zc770-xm010.dts
index 17680d7..199384b 100644
--- a/arch/arm/dts/zynq-zc770-xm010.dts
+++ b/arch/arm/dts/zynq-zc770-xm010.dts
@@ -69,6 +69,31 @@
spi-tx-bus-width = <1>;
spi-rx-bus-width = <4>;
spi-max-frequency = <50000000>;
+ partitions {
+ compatible = "fixed-partitions";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ partition@0 {
+ label = "qspi-fsbl-uboot";
+ reg = <0x0 0x100000>;
+ };
+ partition@100000 {
+ label = "qspi-linux";
+ reg = <0x100000 0x500000>;
+ };
+ partition@600000 {
+ label = "qspi-device-tree";
+ reg = <0x600000 0x20000>;
+ };
+ partition@620000 {
+ label = "qspi-rootfs";
+ reg = <0x620000 0x5e0000>;
+ };
+ partition@c00000 {
+ label = "qspi-bitstream";
+ reg = <0xc00000 0x400000>;
+ };
+ };
};
};
diff --git a/arch/arm/dts/zynq-zc770-xm011.dts b/arch/arm/dts/zynq-zc770-xm011.dts
index d1e9712..f9a086f 100644
--- a/arch/arm/dts/zynq-zc770-xm011.dts
+++ b/arch/arm/dts/zynq-zc770-xm011.dts
@@ -49,8 +49,27 @@
&nfc0 {
status = "okay";
+ #address-cells = <1>;
+ #size-cells = <0>;
nand@0 {
reg = <0>;
+ partitions {
+ compatible = "fixed-partitions";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ partition@0 {
+ label = "nand-fsbl-uboot";
+ reg = <0x0 0x1000000>;
+ };
+ partition@1000000 {
+ label = "nand-linux";
+ reg = <0x1000000 0x2000000>;
+ };
+ partition@3000000 {
+ label = "nand-rootfs";
+ reg = <0x3000000 0x200000>;
+ };
+ };
};
};
diff --git a/arch/arm/dts/zynq-zc770-xm012.dts b/arch/arm/dts/zynq-zc770-xm012.dts
index 6e36634..24520e7 100644
--- a/arch/arm/dts/zynq-zc770-xm012.dts
+++ b/arch/arm/dts/zynq-zc770-xm012.dts
@@ -56,6 +56,31 @@
&nor0 {
status = "okay";
bank-width = <1>;
+ partitions {
+ compatible = "fixed-partitions";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ partition@0 {
+ label = "nor-fsbl-uboot";
+ reg = <0x0 0x100000>;
+ };
+ partition@100000 {
+ label = "nor-linux";
+ reg = <0x100000 0x500000>;
+ };
+ partition@600000 {
+ label = "nor-device-tree";
+ reg = <0x600000 0x20000>;
+ };
+ partition@620000 {
+ label = "nor-rootfs";
+ reg = <0x620000 0x5e0000>;
+ };
+ partition@c00000 {
+ label = "nor-bitstream";
+ reg = <0xc00000 0x400000>;
+ };
+ };
};
&smcc {
diff --git a/arch/arm/dts/zynq-zc770-xm013.dts b/arch/arm/dts/zynq-zc770-xm013.dts
index 21902fb..add7599 100644
--- a/arch/arm/dts/zynq-zc770-xm013.dts
+++ b/arch/arm/dts/zynq-zc770-xm013.dts
@@ -61,13 +61,39 @@
&qspi {
status = "okay";
- num-cs = <1>;
+ num-cs = <2>;
flash@0 {
compatible = "n25q128a11", "jedec,spi-nor";
- reg = <0x0>;
+ reg = <0>, <1>;
+ parallel-memories = /bits/ 64 <0x1000000 0x1000000>; /* 16MB */
spi-tx-bus-width = <1>;
spi-rx-bus-width = <4>;
spi-max-frequency = <50000000>;
+ partitions {
+ compatible = "fixed-partitions";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ partition@0 {
+ label = "qspi-fsbl-uboot";
+ reg = <0x0 0x100000>;
+ };
+ partition@100000 {
+ label = "qspi-linux";
+ reg = <0x100000 0x500000>;
+ };
+ partition@600000 {
+ label = "qspi-device-tree";
+ reg = <0x600000 0x20000>;
+ };
+ partition@620000 {
+ label = "qspi-rootfs";
+ reg = <0x620000 0x5e0000>;
+ };
+ partition@c00000 {
+ label = "qspi-bitstream";
+ reg = <0xc00000 0x400000>;
+ };
+ };
};
};
diff --git a/arch/arm/dts/zynq-zed.dts b/arch/arm/dts/zynq-zed.dts
index 5320b4b..70bc418 100644
--- a/arch/arm/dts/zynq-zed.dts
+++ b/arch/arm/dts/zynq-zed.dts
@@ -55,8 +55,35 @@
flash@0 {
compatible = "spansion,s25fl256s1", "jedec,spi-nor";
reg = <0>;
- spi-max-frequency = <30000000>;
+ spi-tx-bus-width = <1>;
+ spi-rx-bus-width = <4>;
+ spi-max-frequency = <50000000>;
m25p,fast-read;
+ partitions {
+ compatible = "fixed-partitions";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ partition@0 {
+ label = "qspi-fsbl-uboot";
+ reg = <0x0 0x100000>;
+ };
+ partition@100000 {
+ label = "qspi-linux";
+ reg = <0x100000 0x500000>;
+ };
+ partition@600000 {
+ label = "qspi-device-tree";
+ reg = <0x600000 0x20000>;
+ };
+ partition@620000 {
+ label = "qspi-rootfs";
+ reg = <0x620000 0x5e0000>;
+ };
+ partition@c00000 {
+ label = "qspi-bitstream";
+ reg = <0xc00000 0x400000>;
+ };
+ };
};
};
diff --git a/arch/arm/dts/zynqmp-clk-ccf.dtsi b/arch/arm/dts/zynqmp-clk-ccf.dtsi
index 5f1b0b2..dd4569e 100644
--- a/arch/arm/dts/zynqmp-clk-ccf.dtsi
+++ b/arch/arm/dts/zynqmp-clk-ccf.dtsi
@@ -10,12 +10,6 @@
#include <dt-bindings/clock/xlnx-zynqmp-clk.h>
/ {
- fclk0: fclk0 {
- status = "okay";
- compatible = "xlnx,fclk";
- clocks = <&zynqmp_clk PL0_REF>;
- };
-
pss_ref_clk: pss_ref_clk {
bootph-all;
compatible = "fixed-clock";
diff --git a/arch/arm/dts/zynqmp-m-a2197-01-revA.dts b/arch/arm/dts/zynqmp-m-a2197-01-revA.dts
index 25ef646..83b8a98 100644
--- a/arch/arm/dts/zynqmp-m-a2197-01-revA.dts
+++ b/arch/arm/dts/zynqmp-m-a2197-01-revA.dts
@@ -71,11 +71,13 @@
&qspi {
status = "okay";
+ num-cs = <2>;
flash@0 {
compatible = "m25p80", "jedec,spi-nor"; /* 32MB */
+ reg = <0>, <1>;
+ parallel-memories = /bits/ 64 <0x4000000 0x4000000>; /* 64MB */
#address-cells = <1>;
#size-cells = <1>;
- reg = <0x0>;
spi-tx-bus-width = <4>;
spi-rx-bus-width = <4>;
spi-max-frequency = <108000000>;
diff --git a/arch/arm/dts/zynqmp-m-a2197-02-revA.dts b/arch/arm/dts/zynqmp-m-a2197-02-revA.dts
index ece9e69..dd37b72 100644
--- a/arch/arm/dts/zynqmp-m-a2197-02-revA.dts
+++ b/arch/arm/dts/zynqmp-m-a2197-02-revA.dts
@@ -67,11 +67,13 @@
&qspi {
status = "okay";
+ num-cs = <2>;
flash@0 {
compatible = "m25p80", "jedec,spi-nor"; /* 32MB */
+ reg = <0>, <1>;
+ parallel-memories = /bits/ 64 <0x4000000 0x4000000>; /* 64MB */
#address-cells = <1>;
#size-cells = <1>;
- reg = <0x0>;
spi-tx-bus-width = <4>;
spi-rx-bus-width = <4>;
spi-max-frequency = <108000000>;
diff --git a/arch/arm/dts/zynqmp-m-a2197-03-revA.dts b/arch/arm/dts/zynqmp-m-a2197-03-revA.dts
index 7372968..811ceba 100644
--- a/arch/arm/dts/zynqmp-m-a2197-03-revA.dts
+++ b/arch/arm/dts/zynqmp-m-a2197-03-revA.dts
@@ -67,11 +67,13 @@
&qspi {
status = "okay";
+ num-cs = <2>;
flash@0 {
compatible = "m25p80", "jedec,spi-nor"; /* 32MB */
+ reg = <0>, <1>;
+ parallel-memories = /bits/ 64 <0x4000000 0x4000000>; /* 64MB */
#address-cells = <1>;
#size-cells = <1>;
- reg = <0x0>;
spi-tx-bus-width = <4>;
spi-rx-bus-width = <4>;
spi-max-frequency = <108000000>;
diff --git a/arch/arm/dts/zynqmp-mini-qspi-parallel.dts b/arch/arm/dts/zynqmp-mini-qspi-parallel.dts
new file mode 100644
index 0000000..728e822
--- /dev/null
+++ b/arch/arm/dts/zynqmp-mini-qspi-parallel.dts
@@ -0,0 +1,21 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Xilinx ZynqMP QSPI Quad Parallel DTS
+ *
+ * Copyright (C) 2015 - 2017 Xilinx, Inc.
+ */
+
+#include "zynqmp-mini-qspi.dts"
+
+/ {
+ model = "ZynqMP MINI QSPI PARALLEL";
+};
+
+&qspi {
+ num-cs = <2>;
+};
+
+&flash0 {
+ reg = <0>, <1>;
+ parallel-memories = /bits/ 64 <0x10000000 0x10000000>; /* 256MB */
+};
diff --git a/arch/arm/dts/zynqmp-mini-qspi-single.dts b/arch/arm/dts/zynqmp-mini-qspi-single.dts
new file mode 100644
index 0000000..0f9306e
--- /dev/null
+++ b/arch/arm/dts/zynqmp-mini-qspi-single.dts
@@ -0,0 +1,12 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Xilinx ZynqMP QSPI single DTS
+ *
+ * Copyright (C) 2015 - 2017 Xilinx, Inc.
+ */
+
+#include "zynqmp-mini-qspi.dts"
+
+/ {
+ model = "ZynqMP MINI QSPI SINGLE";
+};
diff --git a/arch/arm/dts/zynqmp-mini-qspi-stacked.dts b/arch/arm/dts/zynqmp-mini-qspi-stacked.dts
new file mode 100644
index 0000000..9a9541b
--- /dev/null
+++ b/arch/arm/dts/zynqmp-mini-qspi-stacked.dts
@@ -0,0 +1,21 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Xilinx ZynqMP QSPI Quad Stacked DTS
+ *
+ * Copyright (C) 2015 - 2017 Xilinx, Inc.
+ */
+
+#include "zynqmp-mini-qspi.dts"
+
+/ {
+ model = "ZynqMP MINI QSPI STACKED";
+};
+
+&qspi {
+ num-cs = <2>;
+};
+
+&flash0 {
+ reg = <0>, <1>;
+ stacked-memories = /bits/ 64 <0x10000000 0x10000000>; /* 256MB */
+};
diff --git a/arch/arm/dts/zynqmp-mini-qspi-x1-single.dts b/arch/arm/dts/zynqmp-mini-qspi-x1-single.dts
new file mode 100644
index 0000000..5af875c
--- /dev/null
+++ b/arch/arm/dts/zynqmp-mini-qspi-x1-single.dts
@@ -0,0 +1,17 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Xilinx ZynqMP QSPI x1 Single DTS
+ *
+ * Copyright (C) 2015 - 2017 Xilinx, Inc.
+ */
+
+#include "zynqmp-mini-qspi.dts"
+
+/ {
+ model = "ZynqMP MINI QSPI X1 SINGLE";
+};
+
+&flash0 {
+ spi-tx-bus-width = <1>;
+ spi-rx-bus-width = <1>;
+};
diff --git a/arch/arm/dts/zynqmp-mini-qspi-x1-stacked.dts b/arch/arm/dts/zynqmp-mini-qspi-x1-stacked.dts
new file mode 100644
index 0000000..ebf890e
--- /dev/null
+++ b/arch/arm/dts/zynqmp-mini-qspi-x1-stacked.dts
@@ -0,0 +1,23 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Xilinx ZynqMP QSPI x1 Stacked DTS
+ *
+ * Copyright (C) 2015 - 2017 Xilinx, Inc.
+ */
+
+#include "zynqmp-mini-qspi.dts"
+
+/ {
+ model = "ZynqMP MINI QSPI X1 STACKED";
+};
+
+&qspi {
+ num-cs = <2>;
+};
+
+&flash0 {
+ reg = <0>, <1>;
+ stacked-memories = /bits/ 64 <0x10000000 0x10000000>; /* 256MB */
+ spi-tx-bus-width = <1>;
+ spi-rx-bus-width = <1>;
+};
diff --git a/arch/arm/dts/zynqmp-mini-qspi-x2-single.dts b/arch/arm/dts/zynqmp-mini-qspi-x2-single.dts
new file mode 100644
index 0000000..a5ab315
--- /dev/null
+++ b/arch/arm/dts/zynqmp-mini-qspi-x2-single.dts
@@ -0,0 +1,17 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Xilinx CSE QSPI x2 Single DTS
+ *
+ * Copyright (C) 2015 - 2017 Xilinx, Inc.
+ */
+
+#include "zynqmp-mini-qspi.dts"
+
+/ {
+ model = "ZynqMP MINI QSPI X2 SINGLE";
+};
+
+&flash0 {
+ spi-tx-bus-width = <2>;
+ spi-rx-bus-width = <2>;
+};
diff --git a/arch/arm/dts/zynqmp-mini-qspi-x2-stacked.dts b/arch/arm/dts/zynqmp-mini-qspi-x2-stacked.dts
new file mode 100644
index 0000000..e234b76
--- /dev/null
+++ b/arch/arm/dts/zynqmp-mini-qspi-x2-stacked.dts
@@ -0,0 +1,23 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Xilinx ZynqMP QSPI x2 Stacked DTS
+ *
+ * Copyright (C) 2015 - 2017 Xilinx, Inc.
+ */
+
+#include "zynqmp-mini-qspi.dts"
+
+/ {
+ model = "ZynqMP MINI QSPI X2 STACKED";
+};
+
+&qspi {
+ num-cs = <2>;
+};
+
+&flash0 {
+ reg = <0>, <1>;
+ stacked-memories = /bits/ 64 <0x10000000 0x10000000>; /* 256MB */
+ spi-tx-bus-width = <2>;
+ spi-rx-bus-width = <2>;
+};
diff --git a/arch/arm/dts/zynqmp-sck-kv-g-revA.dtso b/arch/arm/dts/zynqmp-sck-kv-g-revA.dtso
index 22e7d68..c4f1da9 100644
--- a/arch/arm/dts/zynqmp-sck-kv-g-revA.dtso
+++ b/arch/arm/dts/zynqmp-sck-kv-g-revA.dtso
@@ -190,6 +190,25 @@
&pinctrl0 {
status = "okay";
+ pinctrl_gpio0_default: gpio0-default {
+ conf {
+ groups = "gpio0_38_grp";
+ bias-pull-up;
+ power-source = <IO_STANDARD_LVCMOS18>;
+ };
+
+ mux {
+ groups = "gpio0_38_grp";
+ function = "gpio0";
+ };
+
+ conf-tx {
+ pins = "MIO38";
+ bias-disable;
+ output-enable;
+ };
+ };
+
pinctrl_uart1_default: uart1-default {
conf {
groups = "uart1_9_grp";
@@ -345,6 +364,12 @@
};
};
+&gpio {
+ status = "okay";
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_gpio0_default>;
+};
+
&uart1 {
status = "okay";
pinctrl-names = "default";
diff --git a/arch/arm/dts/zynqmp-sck-kv-g-revB.dtso b/arch/arm/dts/zynqmp-sck-kv-g-revB.dtso
index eadc256..6c5e0e5 100644
--- a/arch/arm/dts/zynqmp-sck-kv-g-revB.dtso
+++ b/arch/arm/dts/zynqmp-sck-kv-g-revB.dtso
@@ -178,6 +178,25 @@
&pinctrl0 {
status = "okay";
+ pinctrl_gpio0_default: gpio0-default {
+ conf {
+ groups = "gpio0_38_grp";
+ bias-pull-up;
+ power-source = <IO_STANDARD_LVCMOS18>;
+ };
+
+ mux {
+ groups = "gpio0_38_grp";
+ function = "gpio0";
+ };
+
+ conf-tx {
+ pins = "MIO38";
+ bias-disable;
+ output-enable;
+ };
+ };
+
pinctrl_uart1_default: uart1-default {
conf {
groups = "uart1_9_grp";
@@ -333,6 +352,12 @@
};
};
+&gpio {
+ status = "okay";
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_gpio0_default>;
+};
+
&uart1 {
status = "okay";
pinctrl-names = "default";
diff --git a/arch/arm/dts/zynqmp-vp-x-a2785-00-revA.dts b/arch/arm/dts/zynqmp-vp-x-a2785-00-revA.dts
index 2f88aa4..9ab8f5b 100644
--- a/arch/arm/dts/zynqmp-vp-x-a2785-00-revA.dts
+++ b/arch/arm/dts/zynqmp-vp-x-a2785-00-revA.dts
@@ -119,9 +119,13 @@
phy-mode = "sgmii"; /* DTG generates this properly 1512 */
is-internal-pcspma;
/* phys = <&psgtr 0 PHY_TYPE_SGMII 0 0>; */
- /* phy-reset-gpios = <&gpio 142 GPIO_ACTIVE_LOW>; */
- phy0: ethernet-phy@0 { /* u131 - M88e1512 */
- reg = <0>;
+ mdio: mdio {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ /* reset-gpios = <&gpio 142 GPIO_ACTIVE_LOW>; */
+ phy0: ethernet-phy@0 { /* u131 - M88e1512 */
+ reg = <0>;
+ };
};
};
diff --git a/arch/arm/dts/zynqmp-vpk120-revA.dts b/arch/arm/dts/zynqmp-vpk120-revA.dts
index 66919f5..ce76e0b 100644
--- a/arch/arm/dts/zynqmp-vpk120-revA.dts
+++ b/arch/arm/dts/zynqmp-vpk120-revA.dts
@@ -120,9 +120,13 @@
phy-mode = "sgmii"; /* DTG generates this properly 1512 */
is-internal-pcspma;
/* phys = <&psgtr 0 PHY_TYPE_SGMII 0 0>; */
- /* phy-reset-gpios = <&gpio 142 GPIO_ACTIVE_LOW>; */
- phy0: ethernet-phy@0 {
- reg = <0>;
+ mdio: mdio {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ /* reset-gpios = <&gpio 142 GPIO_ACTIVE_LOW>; */
+ phy0: ethernet-phy@0 {
+ reg = <0>;
+ };
};
};
diff --git a/arch/arm/dts/zynqmp-zc1751-xm016-dc2.dts b/arch/arm/dts/zynqmp-zc1751-xm016-dc2.dts
index 23a3ff2..160c6c5 100644
--- a/arch/arm/dts/zynqmp-zc1751-xm016-dc2.dts
+++ b/arch/arm/dts/zynqmp-zc1751-xm016-dc2.dts
@@ -141,8 +141,7 @@
reg = <0x0>;
#address-cells = <0x2>;
#size-cells = <0x1>;
- nand-ecc-mode = "soft";
- nand-ecc-algo = "bch";
+ nand-ecc-mode = "hw";
nand-rb = <0>;
label = "main-storage-0";
nand-ecc-step-size = <1024>;
@@ -178,8 +177,7 @@
reg = <0x1>;
#address-cells = <0x2>;
#size-cells = <0x1>;
- nand-ecc-mode = "soft";
- nand-ecc-algo = "bch";
+ nand-ecc-mode = "hw";
nand-rb = <0>;
label = "main-storage-1";
nand-ecc-step-size = <1024>;
diff --git a/arch/arm/dts/zynqmp.dtsi b/arch/arm/dts/zynqmp.dtsi
index f03c201..58a56bc 100644
--- a/arch/arm/dts/zynqmp.dtsi
+++ b/arch/arm/dts/zynqmp.dtsi
@@ -214,16 +214,61 @@
soc_revision: soc-revision@0 {
reg = <0x0 0x4>;
};
+ /* efuse access */
+ efuse_dna: efuse-dna@c {
+ reg = <0xc 0xc>;
+ };
+ efuse_usr0: efuse-usr0@20 {
+ reg = <0x20 0x4>;
+ };
+ efuse_usr1: efuse-usr1@24 {
+ reg = <0x24 0x4>;
+ };
+ efuse_usr2: efuse-usr2@28 {
+ reg = <0x28 0x4>;
+ };
+ efuse_usr3: efuse-usr3@2c {
+ reg = <0x2c 0x4>;
+ };
+ efuse_usr4: efuse-usr4@30 {
+ reg = <0x30 0x4>;
+ };
+ efuse_usr5: efuse-usr5@34 {
+ reg = <0x34 0x4>;
+ };
+ efuse_usr6: efuse-usr6@38 {
+ reg = <0x38 0x4>;
+ };
+ efuse_usr7: efuse-usr7@3c {
+ reg = <0x3c 0x4>;
+ };
+ efuse_miscusr: efuse-miscusr@40 {
+ reg = <0x40 0x4>;
+ };
+ efuse_chash: efuse-chash@50 {
+ reg = <0x50 0x4>;
+ };
+ efuse_pufmisc: efuse-pufmisc@54 {
+ reg = <0x54 0x4>;
+ };
+ efuse_sec: efuse-sec@58 {
+ reg = <0x58 0x4>;
+ };
+ efuse_spkid: efuse-spkid@5c {
+ reg = <0x5c 0x4>;
+ };
+ efuse_ppk0hash: efuse-ppk0hash@a0 {
+ reg = <0xa0 0x30>;
+ };
+ efuse_ppk1hash: efuse-ppk1hash@d0 {
+ reg = <0xd0 0x30>;
+ };
};
zynqmp_pcap: pcap {
compatible = "xlnx,zynqmp-pcap-fpga";
};
- xlnx_aes: zynqmp-aes {
- compatible = "xlnx,zynqmp-aes";
- };
-
zynqmp_reset: reset-controller {
compatible = "xlnx,zynqmp-reset";
#reset-cells = <1>;
@@ -261,7 +306,6 @@
#address-cells = <2>;
#size-cells = <2>;
ranges;
- power-domains = <&zynqmp_firmware PD_PL>;
};
remoteproc {
@@ -344,7 +388,7 @@
clock-names = "clk_main", "clk_apb";
#dma-cells = <1>;
xlnx,bus-width = <128>;
- iommus = <&smmu 0x14e8>;
+ /* iommus = <&smmu 0x14e8>; */
power-domains = <&zynqmp_firmware PD_GDMA>;
};
@@ -357,7 +401,7 @@
clock-names = "clk_main", "clk_apb";
#dma-cells = <1>;
xlnx,bus-width = <128>;
- iommus = <&smmu 0x14e9>;
+ /* iommus = <&smmu 0x14e9>; */
power-domains = <&zynqmp_firmware PD_GDMA>;
};
@@ -370,7 +414,7 @@
clock-names = "clk_main", "clk_apb";
#dma-cells = <1>;
xlnx,bus-width = <128>;
- iommus = <&smmu 0x14ea>;
+ /* iommus = <&smmu 0x14ea>; */
power-domains = <&zynqmp_firmware PD_GDMA>;
};
@@ -383,7 +427,7 @@
clock-names = "clk_main", "clk_apb";
#dma-cells = <1>;
xlnx,bus-width = <128>;
- iommus = <&smmu 0x14eb>;
+ /* iommus = <&smmu 0x14eb>; */
power-domains = <&zynqmp_firmware PD_GDMA>;
};
@@ -396,7 +440,7 @@
clock-names = "clk_main", "clk_apb";
#dma-cells = <1>;
xlnx,bus-width = <128>;
- iommus = <&smmu 0x14ec>;
+ /* iommus = <&smmu 0x14ec>; */
power-domains = <&zynqmp_firmware PD_GDMA>;
};
@@ -409,7 +453,7 @@
clock-names = "clk_main", "clk_apb";
#dma-cells = <1>;
xlnx,bus-width = <128>;
- iommus = <&smmu 0x14ed>;
+ /* iommus = <&smmu 0x14ed>; */
power-domains = <&zynqmp_firmware PD_GDMA>;
};
@@ -422,7 +466,7 @@
clock-names = "clk_main", "clk_apb";
#dma-cells = <1>;
xlnx,bus-width = <128>;
- iommus = <&smmu 0x14ee>;
+ /* iommus = <&smmu 0x14ee>; */
power-domains = <&zynqmp_firmware PD_GDMA>;
};
@@ -435,7 +479,7 @@
clock-names = "clk_main", "clk_apb";
#dma-cells = <1>;
xlnx,bus-width = <128>;
- iommus = <&smmu 0x14ef>;
+ /* iommus = <&smmu 0x14ef>; */
power-domains = <&zynqmp_firmware PD_GDMA>;
};
@@ -480,7 +524,7 @@
clock-names = "clk_main", "clk_apb";
#dma-cells = <1>;
xlnx,bus-width = <64>;
- iommus = <&smmu 0x868>;
+ /* iommus = <&smmu 0x868>; */
power-domains = <&zynqmp_firmware PD_ADMA>;
};
@@ -493,7 +537,7 @@
clock-names = "clk_main", "clk_apb";
#dma-cells = <1>;
xlnx,bus-width = <64>;
- iommus = <&smmu 0x869>;
+ /* iommus = <&smmu 0x869>; */
power-domains = <&zynqmp_firmware PD_ADMA>;
};
@@ -506,7 +550,7 @@
clock-names = "clk_main", "clk_apb";
#dma-cells = <1>;
xlnx,bus-width = <64>;
- iommus = <&smmu 0x86a>;
+ /* iommus = <&smmu 0x86a>; */
power-domains = <&zynqmp_firmware PD_ADMA>;
};
@@ -519,7 +563,7 @@
clock-names = "clk_main", "clk_apb";
#dma-cells = <1>;
xlnx,bus-width = <64>;
- iommus = <&smmu 0x86b>;
+ /* iommus = <&smmu 0x86b>; */
power-domains = <&zynqmp_firmware PD_ADMA>;
};
@@ -532,7 +576,7 @@
clock-names = "clk_main", "clk_apb";
#dma-cells = <1>;
xlnx,bus-width = <64>;
- iommus = <&smmu 0x86c>;
+ /* iommus = <&smmu 0x86c>; */
power-domains = <&zynqmp_firmware PD_ADMA>;
};
@@ -545,7 +589,7 @@
clock-names = "clk_main", "clk_apb";
#dma-cells = <1>;
xlnx,bus-width = <64>;
- iommus = <&smmu 0x86d>;
+ /* iommus = <&smmu 0x86d>; */
power-domains = <&zynqmp_firmware PD_ADMA>;
};
@@ -558,7 +602,7 @@
clock-names = "clk_main", "clk_apb";
#dma-cells = <1>;
xlnx,bus-width = <64>;
- iommus = <&smmu 0x86e>;
+ /* iommus = <&smmu 0x86e>; */
power-domains = <&zynqmp_firmware PD_ADMA>;
};
@@ -571,7 +615,7 @@
clock-names = "clk_main", "clk_apb";
#dma-cells = <1>;
xlnx,bus-width = <64>;
- iommus = <&smmu 0x86f>;
+ /* iommus = <&smmu 0x86f>; */
power-domains = <&zynqmp_firmware PD_ADMA>;
};
@@ -591,7 +635,7 @@
interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
#address-cells = <1>;
#size-cells = <0>;
- iommus = <&smmu 0x872>;
+ /* iommus = <&smmu 0x872>; */
power-domains = <&zynqmp_firmware PD_NAND>;
};
@@ -603,7 +647,7 @@
<GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>;
reg = <0x0 0xff0b0000 0x0 0x1000>;
clock-names = "pclk", "hclk", "tx_clk", "rx_clk", "tsu_clk";
- iommus = <&smmu 0x874>;
+ /* iommus = <&smmu 0x874>; */
power-domains = <&zynqmp_firmware PD_ETH_0>;
resets = <&zynqmp_reset ZYNQMP_RESET_GEM0>;
reset-names = "gem0_rst";
@@ -617,7 +661,7 @@
<GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>;
reg = <0x0 0xff0c0000 0x0 0x1000>;
clock-names = "pclk", "hclk", "tx_clk", "rx_clk", "tsu_clk";
- iommus = <&smmu 0x875>;
+ /* iommus = <&smmu 0x875>; */
power-domains = <&zynqmp_firmware PD_ETH_1>;
resets = <&zynqmp_reset ZYNQMP_RESET_GEM1>;
reset-names = "gem1_rst";
@@ -631,7 +675,7 @@
<GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>;
reg = <0x0 0xff0d0000 0x0 0x1000>;
clock-names = "pclk", "hclk", "tx_clk", "rx_clk", "tsu_clk";
- iommus = <&smmu 0x876>;
+ /* iommus = <&smmu 0x876>; */
power-domains = <&zynqmp_firmware PD_ETH_2>;
resets = <&zynqmp_reset ZYNQMP_RESET_GEM2>;
reset-names = "gem2_rst";
@@ -645,7 +689,7 @@
<GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>;
reg = <0x0 0xff0e0000 0x0 0x1000>;
clock-names = "pclk", "hclk", "tx_clk", "rx_clk", "tsu_clk";
- iommus = <&smmu 0x877>;
+ /* iommus = <&smmu 0x877>; */
power-domains = <&zynqmp_firmware PD_ETH_3>;
resets = <&zynqmp_reset ZYNQMP_RESET_GEM3>;
reset-names = "gem3_rst";
@@ -724,7 +768,7 @@
<0x0 0x0 0x0 0x2 &pcie_intc 0x2>,
<0x0 0x0 0x0 0x3 &pcie_intc 0x3>,
<0x0 0x0 0x0 0x4 &pcie_intc 0x4>;
- iommus = <&smmu 0x4d0>;
+ /* iommus = <&smmu 0x4d0>; */
power-domains = <&zynqmp_firmware PD_PCIE>;
pcie_intc: legacy-interrupt-controller {
interrupt-controller;
@@ -745,7 +789,7 @@
<0x0 0xc0000000 0x0 0x8000000>;
#address-cells = <1>;
#size-cells = <0>;
- iommus = <&smmu 0x873>;
+ /* iommus = <&smmu 0x873>; */
power-domains = <&zynqmp_firmware PD_QSPI>;
};
@@ -777,8 +821,7 @@
interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>;
power-domains = <&zynqmp_firmware PD_SATA>;
resets = <&zynqmp_reset ZYNQMP_RESET_SATA>;
- iommus = <&smmu 0x4c0>, <&smmu 0x4c1>,
- <&smmu 0x4c2>, <&smmu 0x4c3>;
+ /* iommus = <&smmu 0x4c0>, <&smmu 0x4c1>, <&smmu 0x4c2>, <&smmu 0x4c3>; */
/* dma-coherent; */
};
@@ -790,7 +833,7 @@
interrupts = <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>;
reg = <0x0 0xff160000 0x0 0x1000>;
clock-names = "clk_xin", "clk_ahb";
- iommus = <&smmu 0x870>;
+ /* iommus = <&smmu 0x870>; */
#clock-cells = <1>;
clock-output-names = "clk_out_sd0", "clk_in_sd0";
power-domains = <&zynqmp_firmware PD_SD_0>;
@@ -805,7 +848,7 @@
interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>;
reg = <0x0 0xff170000 0x0 0x1000>;
clock-names = "clk_xin", "clk_ahb";
- iommus = <&smmu 0x871>;
+ /* iommus = <&smmu 0x871>; */
#clock-cells = <1>;
clock-output-names = "clk_out_sd1", "clk_in_sd1";
power-domains = <&zynqmp_firmware PD_SD_1>;
@@ -956,11 +999,10 @@
interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>;
- iommus = <&smmu 0x860>;
+ /* iommus = <&smmu 0x860>; */
snps,quirk-frame-length-adjustment = <0x20>;
clock-names = "ref";
snps,enable_guctl1_ipd_quirk;
- snps,xhci-stream-quirk;
snps,resume-hs-terminations;
/* dma-coherent; */
};
@@ -989,11 +1031,10 @@
interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;
- iommus = <&smmu 0x861>;
+ /* iommus = <&smmu 0x861>; */
snps,quirk-frame-length-adjustment = <0x20>;
clock-names = "ref";
snps,enable_guctl1_ipd_quirk;
- snps,xhci-stream-quirk;
snps,resume-hs-terminations;
/* dma-coherent; */
};
@@ -1039,8 +1080,6 @@
compatible = "xlnx,zynqmp-ams-pl";
status = "disabled";
reg = <0x400 0x400>;
- #address-cells = <1>;
- #size-cells = <0>;
};
};
@@ -1052,6 +1091,7 @@
interrupt-parent = <&gic>;
clock-names = "axi_clk";
power-domains = <&zynqmp_firmware PD_DP>;
+ /* iommus = <&smmu 0xce4>; */
#dma-cells = <1>;
};
@@ -1066,6 +1106,7 @@
reg-names = "dp", "blend", "av_buf", "aud";
interrupts = <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>;
interrupt-parent = <&gic>;
+ /* iommus = <&smmu 0xce3>; */
clock-names = "dp_apb_clk", "dp_aud_clk",
"dp_vtc_pixel_clk_in";
power-domains = <&zynqmp_firmware PD_DP>;
diff --git a/arch/arm/include/asm/arch-am33xx/clk_synthesizer.h b/arch/arm/include/asm/arch-am33xx/clk_synthesizer.h
index 7bcafba..8e3d55f 100644
--- a/arch/arm/include/asm/arch-am33xx/clk_synthesizer.h
+++ b/arch/arm/include/asm/arch-am33xx/clk_synthesizer.h
@@ -4,7 +4,7 @@
*
* Clock synthesizer header
*
- * Copyright (C) 2016, Texas Instruments, Incorporated - http://www.ti.com/
+ * Copyright (C) 2016, Texas Instruments, Incorporated - https://www.ti.com/
*/
#ifndef __CLK_SYNTHESIZER_H
diff --git a/arch/arm/include/asm/arch-am33xx/clock.h b/arch/arm/include/asm/arch-am33xx/clock.h
index 67400c2..13960db 100644
--- a/arch/arm/include/asm/arch-am33xx/clock.h
+++ b/arch/arm/include/asm/arch-am33xx/clock.h
@@ -4,7 +4,7 @@
*
* clock header
*
- * Copyright (C) 2011, Texas Instruments Incorporated - http://www.ti.com/
+ * Copyright (C) 2011, Texas Instruments Incorporated - https://www.ti.com/
*/
#ifndef _CLOCKS_H_
diff --git a/arch/arm/include/asm/arch-am33xx/clocks_am33xx.h b/arch/arm/include/asm/arch-am33xx/clocks_am33xx.h
index e5ad507..adb574e 100644
--- a/arch/arm/include/asm/arch-am33xx/clocks_am33xx.h
+++ b/arch/arm/include/asm/arch-am33xx/clocks_am33xx.h
@@ -4,7 +4,7 @@
*
* AM33xx clock define
*
- * Copyright (C) 2013 Texas Instruments Incorporated - http://www.ti.com/
+ * Copyright (C) 2013 Texas Instruments Incorporated - https://www.ti.com/
*/
#ifndef _CLOCKS_AM33XX_H_
diff --git a/arch/arm/include/asm/arch-am33xx/cpu.h b/arch/arm/include/asm/arch-am33xx/cpu.h
index b33e6f7..8ec2585 100644
--- a/arch/arm/include/asm/arch-am33xx/cpu.h
+++ b/arch/arm/include/asm/arch-am33xx/cpu.h
@@ -4,7 +4,7 @@
*
* AM33xx specific header file
*
- * Copyright (C) 2011, Texas Instruments, Incorporated - http://www.ti.com/
+ * Copyright (C) 2011, Texas Instruments, Incorporated - https://www.ti.com/
*/
#ifndef _AM33XX_CPU_H
diff --git a/arch/arm/include/asm/arch-am33xx/ddr_defs.h b/arch/arm/include/asm/arch-am33xx/ddr_defs.h
index 1a03107..6e7a62b 100644
--- a/arch/arm/include/asm/arch-am33xx/ddr_defs.h
+++ b/arch/arm/include/asm/arch-am33xx/ddr_defs.h
@@ -4,7 +4,7 @@
*
* ddr specific header
*
- * Copyright (C) 2011, Texas Instruments, Incorporated - http://www.ti.com/
+ * Copyright (C) 2011, Texas Instruments, Incorporated - https://www.ti.com/
*/
#ifndef _DDR_DEFS_H
diff --git a/arch/arm/include/asm/arch-am33xx/hardware.h b/arch/arm/include/asm/arch-am33xx/hardware.h
index 387f053..33ee915 100644
--- a/arch/arm/include/asm/arch-am33xx/hardware.h
+++ b/arch/arm/include/asm/arch-am33xx/hardware.h
@@ -4,7 +4,7 @@
*
* hardware specific header
*
- * Copyright (C) 2013, Texas Instruments, Incorporated - http://www.ti.com/
+ * Copyright (C) 2013, Texas Instruments, Incorporated - https://www.ti.com/
*/
#ifndef __AM33XX_HARDWARE_H
diff --git a/arch/arm/include/asm/arch-am33xx/hardware_am33xx.h b/arch/arm/include/asm/arch-am33xx/hardware_am33xx.h
index 878ef3e..de597c2 100644
--- a/arch/arm/include/asm/arch-am33xx/hardware_am33xx.h
+++ b/arch/arm/include/asm/arch-am33xx/hardware_am33xx.h
@@ -4,7 +4,7 @@
*
* AM33xx hardware specific header
*
- * Copyright (C) 2013, Texas Instruments, Incorporated - http://www.ti.com/
+ * Copyright (C) 2013, Texas Instruments, Incorporated - https://www.ti.com/
*/
#ifndef __AM33XX_HARDWARE_AM33XX_H
diff --git a/arch/arm/include/asm/arch-am33xx/hardware_am43xx.h b/arch/arm/include/asm/arch-am33xx/hardware_am43xx.h
index 0b73ebd..8786d8c 100644
--- a/arch/arm/include/asm/arch-am33xx/hardware_am43xx.h
+++ b/arch/arm/include/asm/arch-am33xx/hardware_am43xx.h
@@ -4,7 +4,7 @@
*
* AM43xx hardware specific header
*
- * Copyright (C) 2013, Texas Instruments, Incorporated - http://www.ti.com/
+ * Copyright (C) 2013, Texas Instruments, Incorporated - https://www.ti.com/
*/
#ifndef __AM43XX_HARDWARE_AM43XX_H
diff --git a/arch/arm/include/asm/arch-am33xx/mmc_host_def.h b/arch/arm/include/asm/arch-am33xx/mmc_host_def.h
index b1b1896..ed60abf 100644
--- a/arch/arm/include/asm/arch-am33xx/mmc_host_def.h
+++ b/arch/arm/include/asm/arch-am33xx/mmc_host_def.h
@@ -1,7 +1,7 @@
/*
* mmc_host_def.h
*
- * Copyright (C) 2011 Texas Instruments Incorporated - http://www.ti.com/
+ * Copyright (C) 2011 Texas Instruments Incorporated - https://www.ti.com/
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
diff --git a/arch/arm/include/asm/arch-am33xx/mux.h b/arch/arm/include/asm/arch-am33xx/mux.h
index ebb2d30..f704afa 100644
--- a/arch/arm/include/asm/arch-am33xx/mux.h
+++ b/arch/arm/include/asm/arch-am33xx/mux.h
@@ -1,7 +1,7 @@
/*
* mux.h
*
- * Copyright (C) 2013 Texas Instruments Incorporated - http://www.ti.com/
+ * Copyright (C) 2013 Texas Instruments Incorporated - https://www.ti.com/
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
diff --git a/arch/arm/include/asm/arch-am33xx/mux_am33xx.h b/arch/arm/include/asm/arch-am33xx/mux_am33xx.h
index 26bd4b4..c702e4a 100644
--- a/arch/arm/include/asm/arch-am33xx/mux_am33xx.h
+++ b/arch/arm/include/asm/arch-am33xx/mux_am33xx.h
@@ -1,7 +1,7 @@
/*
* mux_am33xx.h
*
- * Copyright (C) 2013 Texas Instruments Incorporated - http://www.ti.com/
+ * Copyright (C) 2013 Texas Instruments Incorporated - https://www.ti.com/
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
diff --git a/arch/arm/include/asm/arch-am33xx/mux_am43xx.h b/arch/arm/include/asm/arch-am33xx/mux_am43xx.h
index f74ae74..24f0041 100644
--- a/arch/arm/include/asm/arch-am33xx/mux_am43xx.h
+++ b/arch/arm/include/asm/arch-am33xx/mux_am43xx.h
@@ -2,7 +2,7 @@
/*
* mux_am43xx.h
*
- * Copyright (C) 2013 Texas Instruments Incorporated - http://www.ti.com/
+ * Copyright (C) 2013 Texas Instruments Incorporated - https://www.ti.com/
*/
#ifndef _MUX_AM43XX_H_
diff --git a/arch/arm/include/asm/arch-am33xx/omap.h b/arch/arm/include/asm/arch-am33xx/omap.h
index 53046de..71a84fe 100644
--- a/arch/arm/include/asm/arch-am33xx/omap.h
+++ b/arch/arm/include/asm/arch-am33xx/omap.h
@@ -2,7 +2,7 @@
/*
* omap.h
*
- * Copyright (C) 2011, Texas Instruments, Incorporated - http://www.ti.com/
+ * Copyright (C) 2011, Texas Instruments, Incorporated - https://www.ti.com/
*
* Author:
* Chandan Nath <chandan.nath@ti.com>
diff --git a/arch/arm/include/asm/arch-am33xx/sys_proto.h b/arch/arm/include/asm/arch-am33xx/sys_proto.h
index be17aad..513cdac 100644
--- a/arch/arm/include/asm/arch-am33xx/sys_proto.h
+++ b/arch/arm/include/asm/arch-am33xx/sys_proto.h
@@ -4,7 +4,7 @@
*
* System information header
*
- * Copyright (C) 2011, Texas Instruments, Incorporated - http://www.ti.com/
+ * Copyright (C) 2011, Texas Instruments, Incorporated - https://www.ti.com/
*/
#ifndef _SYS_PROTO_H_
diff --git a/arch/arm/include/asm/arch-omap3/emif4.h b/arch/arm/include/asm/arch-omap3/emif4.h
index bac43b2..397bb47 100644
--- a/arch/arm/include/asm/arch-omap3/emif4.h
+++ b/arch/arm/include/asm/arch-omap3/emif4.h
@@ -4,7 +4,7 @@
* Vaibhav Hiremath <hvaibhav@ti.com>
*
* Copyright (C) 2010
- * Texas Instruments Incorporated - http://www.ti.com/
+ * Texas Instruments Incorporated - https://www.ti.com/
*/
#ifndef _EMIF_H_
diff --git a/arch/arm/include/asm/arch-omap4/ehci.h b/arch/arm/include/asm/arch-omap4/ehci.h
index 30bdaad..e8fe88f 100644
--- a/arch/arm/include/asm/arch-omap4/ehci.h
+++ b/arch/arm/include/asm/arch-omap4/ehci.h
@@ -4,7 +4,7 @@
* Based on LINUX KERNEL
* drivers/usb/host/ehci-omap.c and drivers/mfd/omap-usb-host.c
*
- * Copyright (C) 2011 Texas Instruments Incorporated - http://www.ti.com
+ * Copyright (C) 2011 Texas Instruments Incorporated - https://www.ti.com
* Author: Govindraj R <govindraj.raja@ti.com>
*/
diff --git a/arch/arm/include/asm/arch-omap4/hardware.h b/arch/arm/include/asm/arch-omap4/hardware.h
index 48dc809..67e3dae 100644
--- a/arch/arm/include/asm/arch-omap4/hardware.h
+++ b/arch/arm/include/asm/arch-omap4/hardware.h
@@ -4,7 +4,7 @@
*
* hardware specific header
*
- * Copyright (C) 2013, Texas Instruments, Incorporated - http://www.ti.com/
+ * Copyright (C) 2013, Texas Instruments, Incorporated - https://www.ti.com/
*/
#ifndef __OMAP_HARDWARE_H
diff --git a/arch/arm/include/asm/arch-omap5/ehci.h b/arch/arm/include/asm/arch-omap5/ehci.h
index 1790b92..3c52a76 100644
--- a/arch/arm/include/asm/arch-omap5/ehci.h
+++ b/arch/arm/include/asm/arch-omap5/ehci.h
@@ -1,6 +1,6 @@
/* SPDX-License-Identifier: GPL-2.0+ */
/*
- * Copyright (C) 2013 Texas Instruments Incorporated - http://www.ti.com*
+ * Copyright (C) 2013 Texas Instruments Incorporated - https://www.ti.com*
* Author: Govindraj R <govindraj.raja@ti.com>
*/
diff --git a/arch/arm/include/asm/arch-omap5/hardware.h b/arch/arm/include/asm/arch-omap5/hardware.h
index b6d26e9..c948c0e 100644
--- a/arch/arm/include/asm/arch-omap5/hardware.h
+++ b/arch/arm/include/asm/arch-omap5/hardware.h
@@ -4,7 +4,7 @@
*
* hardware specific header
*
- * Copyright (C) 2013, Texas Instruments, Incorporated - http://www.ti.com/
+ * Copyright (C) 2013, Texas Instruments, Incorporated - https://www.ti.com/
*/
#ifndef __OMAP_HARDWARE_H
diff --git a/arch/arm/include/asm/arch-rk3066/boot0.h b/arch/arm/include/asm/arch-rk3066/boot0.h
index 28c0fb9..6bf3828 100644
--- a/arch/arm/include/asm/arch-rk3066/boot0.h
+++ b/arch/arm/include/asm/arch-rk3066/boot0.h
@@ -3,6 +3,81 @@
#ifndef __ASM_ARCH_BOOT0_H__
#define __ASM_ARCH_BOOT0_H__
-#include <asm/arch-rockchip/boot0.h>
+#include <asm/arch-rockchip/boot_mode.h>
+
+/*
+ * Execution starts on the instruction following this 4-byte header
+ * (containing the magic 'RK30'). This magic constant will be written into
+ * the final image by the rkimage tool, but we need to reserve space for it here.
+ */
+#ifdef CONFIG_SPL_BUILD
+ b 1f /* if overwritten, entry-address is at the next word */
+1:
+#endif
+
+#if CONFIG_IS_ENABLED(ROCKCHIP_EARLYRETURN_TO_BROM)
+/*
+ * Keep track of the re-entries with help of the lr register.
+ * This binary can be re-used and called from various BROM functions.
+ * Only when it's called from the part that handles SPI, NAND or EMMC
+ * hardware it needs to early return to BROM ones.
+ * In download mode when it handles data on USB OTG and UART0
+ * this section must be skipped.
+ */
+ ldr r3, =CONFIG_ROCKCHIP_BOOT_LR_REG
+ cmp lr, r3 /* if (LR != CONFIG_ROCKCHIP_BOOT_LR_REG) */
+ bne reset /* goto reset; */
+/*
+ * Unlike newer Rockchip SoC models the rk3066 BROM code does not have built-in
+ * support to enter download mode on return to BROM. This binary must check
+ * the boot mode register for the BOOT_BROM_DOWNLOAD flag and reset if it's set.
+ * It then returns to BROM to the end of the function that reads boot blocks.
+ * From there the BROM code goes into a download mode and waits for data
+ * on USB OTG and UART0.
+ */
+ ldr r2, =BOOT_BROM_DOWNLOAD
+ ldr r3, =CONFIG_ROCKCHIP_BOOT_MODE_REG
+ ldr r0, [r3] /* if (readl(CONFIG_ROCKCHIP_BOOT_MODE_REG) != */
+ cmp r0, r2 /* BOOT_BROM_DOWNLOAD) { */
+ bne early_return /* goto early_return; */
+ /* } else { */
+ mov r0, #0
+ str r0, [r3] /* writel(0, CONFIG_ROCKCHIP_BOOT_MODE_REG); */
+
+ ldr r3, =CONFIG_ROCKCHIP_BOOT_RETURN_REG
+ bx r3 /* return to CONFIG_ROCKCHIP_BOOT_RETURN_REG;*/
+ /* } */
+early_return:
+ bx lr /* return to LR in BROM */
+
+SAVE_SP_ADDR:
+ .word 0
+
+ .globl save_boot_params
+save_boot_params:
+ push {r1-r12, lr}
+ ldr r0, =SAVE_SP_ADDR
+ str sp, [r0]
+ b save_boot_params_ret
+
+ .globl back_to_bootrom
+back_to_bootrom:
+ ldr r0, =SAVE_SP_ADDR
+ ldr sp, [r0]
+ mov r0, #0
+ pop {r1-r12, pc}
+#endif
+
+#if (defined(CONFIG_SPL_BUILD))
+/* U-Boot proper of armv7 does not need this */
+ b reset
+#endif
+/*
+ * For armv7, the addr '_start' will be used as vector start address
+ * and is written to the VBAR register, which needs to aligned to 0x20.
+ */
+ .align(5), 0x0
+_start:
+ ARM_VECTORS
#endif
diff --git a/arch/arm/include/asm/arch-sunxi/dram_sun50i_h616.h b/arch/arm/include/asm/arch-sunxi/dram_sun50i_h616.h
index 11774de..a8fdda1 100644
--- a/arch/arm/include/asm/arch-sunxi/dram_sun50i_h616.h
+++ b/arch/arm/include/asm/arch-sunxi/dram_sun50i_h616.h
@@ -130,6 +130,7 @@
#define MSTR_DEVICETYPE_LPDDR2 BIT(2)
#define MSTR_DEVICETYPE_LPDDR3 BIT(3)
#define MSTR_DEVICETYPE_DDR4 BIT(4)
+#define MSTR_DEVICETYPE_LPDDR4 BIT(5)
#define MSTR_DEVICETYPE_MASK GENMASK(5, 0)
#define MSTR_2TMODE BIT(10)
#define MSTR_BUSWIDTH_FULL (0 << 12)
@@ -154,6 +155,7 @@
u32 odt_en;
u32 tpr0;
u32 tpr2;
+ u32 tpr6;
u32 tpr10;
u32 tpr11;
u32 tpr12;
diff --git a/arch/arm/include/asm/arch-sunxi/mmc.h b/arch/arm/include/asm/arch-sunxi/mmc.h
index 8ed3e04..b8d91b5 100644
--- a/arch/arm/include/asm/arch-sunxi/mmc.h
+++ b/arch/arm/include/asm/arch-sunxi/mmc.h
@@ -1,139 +1,8 @@
/* SPDX-License-Identifier: GPL-2.0+ */
-/*
- * (C) Copyright 2007-2011
- * Allwinner Technology Co., Ltd. <www.allwinnertech.com>
- * Aaron <leafy.myeh@allwinnertech.com>
- *
- * MMC register definition for allwinner sunxi platform.
- */
-#ifndef _SUNXI_MMC_H
-#define _SUNXI_MMC_H
-
-#include <linux/types.h>
-
-struct sunxi_mmc {
- u32 gctrl; /* 0x00 global control */
- u32 clkcr; /* 0x04 clock control */
- u32 timeout; /* 0x08 time out */
- u32 width; /* 0x0c bus width */
- u32 blksz; /* 0x10 block size */
- u32 bytecnt; /* 0x14 byte count */
- u32 cmd; /* 0x18 command */
- u32 arg; /* 0x1c argument */
- u32 resp0; /* 0x20 response 0 */
- u32 resp1; /* 0x24 response 1 */
- u32 resp2; /* 0x28 response 2 */
- u32 resp3; /* 0x2c response 3 */
- u32 imask; /* 0x30 interrupt mask */
- u32 mint; /* 0x34 masked interrupt status */
- u32 rint; /* 0x38 raw interrupt status */
- u32 status; /* 0x3c status */
- u32 ftrglevel; /* 0x40 FIFO threshold watermark*/
- u32 funcsel; /* 0x44 function select */
- u32 cbcr; /* 0x48 CIU byte count */
- u32 bbcr; /* 0x4c BIU byte count */
- u32 dbgc; /* 0x50 debug enable */
- u32 res0; /* 0x54 reserved */
- u32 a12a; /* 0x58 Auto command 12 argument */
- u32 ntsr; /* 0x5c New timing set register */
- u32 res1[8];
- u32 dmac; /* 0x80 internal DMA control */
- u32 dlba; /* 0x84 internal DMA descr list base address */
- u32 idst; /* 0x88 internal DMA status */
- u32 idie; /* 0x8c internal DMA interrupt enable */
- u32 chda; /* 0x90 */
- u32 cbda; /* 0x94 */
- u32 res2[26];
-#if defined(CONFIG_SUNXI_GEN_SUN6I) || defined(CONFIG_SUN50I_GEN_H6) || defined(CONFIG_SUNXI_GEN_NCAT2)
- u32 res3[17];
- u32 samp_dl;
- u32 res4[46];
-#endif
- u32 fifo; /* 0x100 / 0x200 FIFO access address */
-};
-
-#define SUNXI_MMC_CLK_POWERSAVE (0x1 << 17)
-#define SUNXI_MMC_CLK_ENABLE (0x1 << 16)
-#define SUNXI_MMC_CLK_DIVIDER_MASK (0xff)
-
-#define SUNXI_MMC_GCTRL_SOFT_RESET (0x1 << 0)
-#define SUNXI_MMC_GCTRL_FIFO_RESET (0x1 << 1)
-#define SUNXI_MMC_GCTRL_DMA_RESET (0x1 << 2)
-#define SUNXI_MMC_GCTRL_RESET (SUNXI_MMC_GCTRL_SOFT_RESET|\
- SUNXI_MMC_GCTRL_FIFO_RESET|\
- SUNXI_MMC_GCTRL_DMA_RESET)
-#define SUNXI_MMC_GCTRL_DMA_ENABLE (0x1 << 5)
-#define SUNXI_MMC_GCTRL_ACCESS_BY_AHB (0x1 << 31)
-
-#define SUNXI_MMC_CMD_RESP_EXPIRE (0x1 << 6)
-#define SUNXI_MMC_CMD_LONG_RESPONSE (0x1 << 7)
-#define SUNXI_MMC_CMD_CHK_RESPONSE_CRC (0x1 << 8)
-#define SUNXI_MMC_CMD_DATA_EXPIRE (0x1 << 9)
-#define SUNXI_MMC_CMD_WRITE (0x1 << 10)
-#define SUNXI_MMC_CMD_AUTO_STOP (0x1 << 12)
-#define SUNXI_MMC_CMD_WAIT_PRE_OVER (0x1 << 13)
-#define SUNXI_MMC_CMD_SEND_INIT_SEQ (0x1 << 15)
-#define SUNXI_MMC_CMD_UPCLK_ONLY (0x1 << 21)
-#define SUNXI_MMC_CMD_START (0x1 << 31)
-
-#define SUNXI_MMC_RINT_RESP_ERROR (0x1 << 1)
-#define SUNXI_MMC_RINT_COMMAND_DONE (0x1 << 2)
-#define SUNXI_MMC_RINT_DATA_OVER (0x1 << 3)
-#define SUNXI_MMC_RINT_TX_DATA_REQUEST (0x1 << 4)
-#define SUNXI_MMC_RINT_RX_DATA_REQUEST (0x1 << 5)
-#define SUNXI_MMC_RINT_RESP_CRC_ERROR (0x1 << 6)
-#define SUNXI_MMC_RINT_DATA_CRC_ERROR (0x1 << 7)
-#define SUNXI_MMC_RINT_RESP_TIMEOUT (0x1 << 8)
-#define SUNXI_MMC_RINT_DATA_TIMEOUT (0x1 << 9)
-#define SUNXI_MMC_RINT_VOLTAGE_CHANGE_DONE (0x1 << 10)
-#define SUNXI_MMC_RINT_FIFO_RUN_ERROR (0x1 << 11)
-#define SUNXI_MMC_RINT_HARD_WARE_LOCKED (0x1 << 12)
-#define SUNXI_MMC_RINT_START_BIT_ERROR (0x1 << 13)
-#define SUNXI_MMC_RINT_AUTO_COMMAND_DONE (0x1 << 14)
-#define SUNXI_MMC_RINT_END_BIT_ERROR (0x1 << 15)
-#define SUNXI_MMC_RINT_SDIO_INTERRUPT (0x1 << 16)
-#define SUNXI_MMC_RINT_CARD_INSERT (0x1 << 30)
-#define SUNXI_MMC_RINT_CARD_REMOVE (0x1 << 31)
-#define SUNXI_MMC_RINT_INTERRUPT_ERROR_BIT \
- (SUNXI_MMC_RINT_RESP_ERROR | \
- SUNXI_MMC_RINT_RESP_CRC_ERROR | \
- SUNXI_MMC_RINT_DATA_CRC_ERROR | \
- SUNXI_MMC_RINT_RESP_TIMEOUT | \
- SUNXI_MMC_RINT_DATA_TIMEOUT | \
- SUNXI_MMC_RINT_VOLTAGE_CHANGE_DONE | \
- SUNXI_MMC_RINT_FIFO_RUN_ERROR | \
- SUNXI_MMC_RINT_HARD_WARE_LOCKED | \
- SUNXI_MMC_RINT_START_BIT_ERROR | \
- SUNXI_MMC_RINT_END_BIT_ERROR) /* 0xbfc2 */
-#define SUNXI_MMC_RINT_INTERRUPT_DONE_BIT \
- (SUNXI_MMC_RINT_AUTO_COMMAND_DONE | \
- SUNXI_MMC_RINT_DATA_OVER | \
- SUNXI_MMC_RINT_COMMAND_DONE | \
- SUNXI_MMC_RINT_VOLTAGE_CHANGE_DONE)
-
-#define SUNXI_MMC_STATUS_RXWL_FLAG (0x1 << 0)
-#define SUNXI_MMC_STATUS_TXWL_FLAG (0x1 << 1)
-#define SUNXI_MMC_STATUS_FIFO_EMPTY (0x1 << 2)
-#define SUNXI_MMC_STATUS_FIFO_FULL (0x1 << 3)
-#define SUNXI_MMC_STATUS_CARD_PRESENT (0x1 << 8)
-#define SUNXI_MMC_STATUS_CARD_DATA_BUSY (0x1 << 9)
-#define SUNXI_MMC_STATUS_DATA_FSM_BUSY (0x1 << 10)
-#define SUNXI_MMC_STATUS_FIFO_LEVEL(reg) (((reg) >> 17) & 0x3fff)
-
-#define SUNXI_MMC_NTSR_MODE_SEL_NEW (0x1 << 31)
-
-#define SUNXI_MMC_IDMAC_RESET (0x1 << 0)
-#define SUNXI_MMC_IDMAC_FIXBURST (0x1 << 1)
-#define SUNXI_MMC_IDMAC_ENABLE (0x1 << 7)
-
-#define SUNXI_MMC_IDIE_TXIRQ (0x1 << 0)
-#define SUNXI_MMC_IDIE_RXIRQ (0x1 << 1)
-
-#define SUNXI_MMC_COMMON_CLK_GATE (1 << 16)
-#define SUNXI_MMC_COMMON_RESET (1 << 18)
-
-#define SUNXI_MMC_CAL_DL_SW_EN (0x1 << 7)
+#ifndef _ASM_ARCH_MMC_H_
+#define _ASM_ARCH_MMC_H_
struct mmc *sunxi_mmc_init(int sdc_no);
-#endif /* _SUNXI_MMC_H */
+
+#endif /* _ASM_ARCH_MMC_H_ */
diff --git a/arch/arm/include/asm/armv8/mmu.h b/arch/arm/include/asm/armv8/mmu.h
index 4f0adb0..ce655ce 100644
--- a/arch/arm/include/asm/armv8/mmu.h
+++ b/arch/arm/include/asm/armv8/mmu.h
@@ -49,13 +49,10 @@
#define PTE_TYPE_BLOCK (1 << 0)
#define PTE_TYPE_VALID (1 << 0)
-#define PTE_RDONLY BIT(7)
-#define PTE_DBM BIT(51)
-
-#define PTE_TABLE_PXN BIT(59)
-#define PTE_TABLE_XN BIT(60)
-#define PTE_TABLE_AP BIT(61)
-#define PTE_TABLE_NS BIT(63)
+#define PTE_TABLE_PXN (1UL << 59)
+#define PTE_TABLE_XN (1UL << 60)
+#define PTE_TABLE_AP (1UL << 61)
+#define PTE_TABLE_NS (1UL << 63)
/*
* Block
@@ -102,15 +99,6 @@
#define TCR_TG0_16K (2 << 14)
#define TCR_EPD1_DISABLE (1 << 23)
-#define TCR_EL1_HA BIT(39)
-#define TCR_EL1_HD BIT(40)
-
-#define TCR_EL2_HA BIT(21)
-#define TCR_EL2_HD BIT(22)
-
-#define TCR_EL3_HA BIT(21)
-#define TCR_EL3_HD BIT(22)
-
#define TCR_EL1_RSVD (1U << 31)
#define TCR_EL2_RSVD (1U << 31 | 1 << 23)
#define TCR_EL3_RSVD (1U << 31 | 1 << 23)
diff --git a/arch/arm/include/asm/ehci-omap.h b/arch/arm/include/asm/ehci-omap.h
index 2b51b5e..662b62c 100644
--- a/arch/arm/include/asm/ehci-omap.h
+++ b/arch/arm/include/asm/ehci-omap.h
@@ -4,7 +4,7 @@
* Based on LINUX KERNEL
* drivers/usb/host/ehci-omap.c and drivers/mfd/omap-usb-host.c
*
- * Copyright (C) 2011 Texas Instruments Incorporated - http://www.ti.com*
+ * Copyright (C) 2011 Texas Instruments Incorporated - https://www.ti.com*
* Author: Govindraj R <govindraj.raja@ti.com>
*/
diff --git a/arch/arm/include/asm/global_data.h b/arch/arm/include/asm/global_data.h
index b385bae..75bd9d5 100644
--- a/arch/arm/include/asm/global_data.h
+++ b/arch/arm/include/asm/global_data.h
@@ -52,8 +52,6 @@
#if defined(CONFIG_ARM64)
unsigned long tlb_fillptr;
unsigned long tlb_emerg;
- unsigned int first_block_level;
- bool has_hafdbs;
#endif
#endif
#ifdef CFG_SYS_MEM_RESERVE_SECURE
diff --git a/arch/arm/include/asm/ti-common/omap_wdt.h b/arch/arm/include/asm/ti-common/omap_wdt.h
index 42d7e4c..855f889 100644
--- a/arch/arm/include/asm/ti-common/omap_wdt.h
+++ b/arch/arm/include/asm/ti-common/omap_wdt.h
@@ -4,7 +4,7 @@
*
* OMAP Watchdog header file
*
- * Copyright (C) 2011, Texas Instruments, Incorporated - http://www.ti.com/
+ * Copyright (C) 2011, Texas Instruments, Incorporated - https://www.ti.com/
*/
#ifndef __OMAP_WDT_H__
diff --git a/arch/arm/mach-davinci/config.mk b/arch/arm/mach-davinci/config.mk
index 4674cae..edbac8e 100644
--- a/arch/arm/mach-davinci/config.mk
+++ b/arch/arm/mach-davinci/config.mk
@@ -1,6 +1,6 @@
# SPDX-License-Identifier: GPL-2.0+
#
-# Copyright (C) 2012, Texas Instruments, Incorporated - http://www.ti.com/
+# Copyright (C) 2012, Texas Instruments, Incorporated - https://www.ti.com/
ifndef CONFIG_SPL_BUILD
INPUTS-$(CONFIG_SPL_FRAMEWORK) += u-boot.ais
endif
diff --git a/arch/arm/mach-exynos/include/mach/gpio.h b/arch/arm/mach-exynos/include/mach/gpio.h
index f9975d7..9eeeb76 100644
--- a/arch/arm/mach-exynos/include/mach/gpio.h
+++ b/arch/arm/mach-exynos/include/mach/gpio.h
@@ -8,6 +8,9 @@
#define __ASM_ARCH_GPIO_H
#ifndef __ASSEMBLY__
+
+#include <asm/arch/cpu.h>
+
struct s5p_gpio_bank {
unsigned int con;
unsigned int dat;
diff --git a/arch/arm/mach-exynos/soc.c b/arch/arm/mach-exynos/soc.c
index a07c87a..aff2b5e 100644
--- a/arch/arm/mach-exynos/soc.c
+++ b/arch/arm/mach-exynos/soc.c
@@ -9,6 +9,7 @@
#include <asm/cache.h>
#include <asm/io.h>
#include <asm/system.h>
+#include <asm/arch/cpu.h>
#ifdef CONFIG_TARGET_ESPRESSO7420
/*
@@ -20,12 +21,14 @@
void *secondary_boot_addr = (void *)_main;
#endif /* CONFIG_TARGET_ESPRESSO7420 */
+#if !CONFIG_IS_ENABLED(SYSRESET)
void reset_cpu(void)
{
#ifdef CONFIG_CPU_V7A
writel(0x1, samsung_get_base_swreset());
#endif
}
+#endif
#if !CONFIG_IS_ENABLED(SYS_DCACHE_OFF)
void enable_caches(void)
diff --git a/arch/arm/mach-imx/spl_imx_romapi.c b/arch/arm/mach-imx/spl_imx_romapi.c
index 93d48e5..b9ff9bb 100644
--- a/arch/arm/mach-imx/spl_imx_romapi.c
+++ b/arch/arm/mach-imx/spl_imx_romapi.c
@@ -53,16 +53,10 @@
}
static ulong spl_romapi_read_seekable(struct spl_load_info *load,
- ulong sector, ulong count,
+ ulong offset, ulong byte,
void *buf)
{
- u32 pagesize = *(u32 *)load->priv;
- ulong byte = count * pagesize;
- u32 offset;
-
- offset = sector * pagesize;
-
- return spl_romapi_raw_seekable_read(offset, byte, buf) / pagesize;
+ return spl_romapi_raw_seekable_read(offset, byte, buf);
}
static int spl_romapi_load_image_seekable(struct spl_image_info *spl_image,
@@ -107,20 +101,18 @@
struct spl_load_info load;
memset(&load, 0, sizeof(load));
- load.bl_len = pagesize;
+ spl_set_bl_len(&load, pagesize);
load.read = spl_romapi_read_seekable;
- load.priv = &pagesize;
- return spl_load_simple_fit(spl_image, &load, offset / pagesize, header);
+ return spl_load_simple_fit(spl_image, &load, offset, header);
} else if (IS_ENABLED(CONFIG_SPL_LOAD_IMX_CONTAINER) &&
valid_container_hdr((void *)header)) {
struct spl_load_info load;
memset(&load, 0, sizeof(load));
- load.bl_len = pagesize;
+ spl_set_bl_len(&load, pagesize);
load.read = spl_romapi_read_seekable;
- load.priv = &pagesize;
- ret = spl_load_imx_container(spl_image, &load, offset / pagesize);
+ ret = spl_load_imx_container(spl_image, &load, offset);
} else {
/* TODO */
puts("Can't support legacy image\n");
@@ -162,7 +154,7 @@
return 0;
}
- ss->end = end;
+ ss->end += bytes;
}
memcpy(buf, (void *)(sector), count);
@@ -285,7 +277,7 @@
ret = rom_api_download_image(p, 0, pg);
if (ret != ROM_API_OKAY) {
- puts("Steam(USB) download failure\n");
+ puts("Stream(USB) download failure\n");
return -1;
}
@@ -305,7 +297,7 @@
ret = rom_api_download_image(p, 0, pg);
if (ret != ROM_API_OKAY) {
- puts("Steam(USB) download failure\n");
+ puts("Stream(USB) download failure\n");
return -1;
}
@@ -342,7 +334,7 @@
ss.pagesize = pagesize;
memset(&load, 0, sizeof(load));
- load.bl_len = 1;
+ spl_set_bl_len(&load, 1);
load.read = spl_romapi_read_stream;
load.priv = &ss;
@@ -366,7 +358,7 @@
printf("ROM download failure %d\n", imagesize);
memset(&load, 0, sizeof(load));
- load.bl_len = 1;
+ spl_set_bl_len(&load, 1);
load.read = spl_ram_load_read;
if (IS_ENABLED(CONFIG_SPL_LOAD_IMX_CONTAINER))
diff --git a/arch/arm/mach-k3/Kconfig b/arch/arm/mach-k3/Kconfig
index 9168bf8..0389842 100644
--- a/arch/arm/mach-k3/Kconfig
+++ b/arch/arm/mach-k3/Kconfig
@@ -24,6 +24,11 @@
endchoice
+if SOC_K3_J721E
+config SOC_K3_J721E_J7200
+ bool "TI's K3 based J7200 SoC variant Family Support"
+endif
+
config SYS_SOC
default "k3"
@@ -109,56 +114,9 @@
Use this option to set the index of the serial device to be used
for the early console during SPL execution.
-config K3_LOAD_SYSFW
- bool
- depends on SPL
-
-config K3_SYSFW_IMAGE_NAME
- string "File name of SYSFW firmware and configuration blob"
- depends on K3_LOAD_SYSFW
- default "sysfw.itb"
- help
- Filename of the combined System Firmware and configuration image tree
- blob to be loaded when booting from a filesystem.
-
-config K3_SYSFW_IMAGE_MMCSD_RAW_MODE_SECT
- hex "MMC sector to load SYSFW firmware and configuration blob from"
- depends on K3_LOAD_SYSFW && SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR
- default 0x3600
- help
- Address on the MMC to load the combined System Firmware and
- configuration image tree blob from, when the MMC is being used
- in raw mode. Units: MMC sectors (1 sector = 512 bytes).
-
-config K3_SYSFW_IMAGE_MMCSD_RAW_MODE_PART
- hex "MMC partition to load SYSFW firmware and configuration blob from"
- depends on K3_LOAD_SYSFW && SYS_MMCSD_RAW_MODE_U_BOOT_USE_PARTITION
- default 2
- help
- Partition on the MMC to the combined System Firmware and configuration
- image tree blob from, when the MMC is being used in raw mode.
-
-config K3_SYSFW_IMAGE_SIZE_MAX
- int "Amount of memory dynamically allocated for loading SYSFW blob"
- depends on K3_LOAD_SYSFW
- default 280000
- help
- Amount of memory (in bytes) reserved through dynamic allocation at
- runtime for loading the combined System Firmware and configuration image
- tree blob. Keep it as tight as possible, as this directly affects the
- overall SPL memory footprint.
-
-config K3_SYSFW_IMAGE_SPI_OFFS
- hex "SPI offset of SYSFW firmware and configuration blob"
- depends on K3_LOAD_SYSFW
- default 0x6C0000
- help
- Offset of the combined System Firmware and configuration image tree
- blob to be loaded when booting from a SPI flash memory.
-
config SYS_K3_SPL_ATF
bool "Start Cortex-A from SPL"
- depends on SPL && CPU_V7R
+ depends on CPU_V7R
help
Enabling this will try to start Cortex-A (typically with ATF)
after SPL from R5.
@@ -172,7 +130,7 @@
config K3_DM_FW
bool "Separate DM firmware image"
- depends on SPL && CPU_V7R && (SOC_K3_J721E || SOC_K3_J721S2 || SOC_K3_AM625 || SOC_K3_AM62A7) && !CLK_TI_SCI && !TI_SCI_POWER_DOMAIN
+ depends on CPU_V7R && (SOC_K3_J721E || SOC_K3_J721S2 || SOC_K3_AM625 || SOC_K3_AM62A7) && !CLK_TI_SCI && !TI_SCI_POWER_DOMAIN
default y
help
Enabling this will indicate that the system has separate DM
@@ -187,12 +145,15 @@
help
SWRV for X509 certificate used for boot images
+if CPU_V7R
+source "arch/arm/mach-k3/r5/Kconfig"
+endif
+
+source "arch/arm/mach-k3/am65x/Kconfig"
+source "arch/arm/mach-k3/am64x/Kconfig"
+source "arch/arm/mach-k3/am62x/Kconfig"
+source "arch/arm/mach-k3/am62ax/Kconfig"
+source "arch/arm/mach-k3/j721e/Kconfig"
+source "arch/arm/mach-k3/j721s2/Kconfig"
+
-source "board/ti/am65x/Kconfig"
-source "board/ti/am64x/Kconfig"
-source "board/ti/am62x/Kconfig"
-source "board/ti/am62ax/Kconfig"
-source "board/ti/j721e/Kconfig"
-source "board/siemens/iot2050/Kconfig"
-source "board/ti/j721s2/Kconfig"
-source "board/toradex/verdin-am62/Kconfig"
endif
diff --git a/arch/arm/mach-k3/Makefile b/arch/arm/mach-k3/Makefile
index fd77b8b..4216137 100644
--- a/arch/arm/mach-k3/Makefile
+++ b/arch/arm/mach-k3/Makefile
@@ -1,14 +1,10 @@
# SPDX-License-Identifier: GPL-2.0+
#
-# Copyright (C) 2017-2018 Texas Instruments Incorporated - http://www.ti.com/
+# Copyright (C) 2017-2018 Texas Instruments Incorporated - https://www.ti.com/
# Lokesh Vutla <lokeshvutla@ti.com>
-obj-$(CONFIG_SOC_K3_J721E) += j721e/ j7200/
-obj-$(CONFIG_SOC_K3_J721S2) += j721s2/
-obj-$(CONFIG_SOC_K3_AM625) += am62x/
-obj-$(CONFIG_SOC_K3_AM62A7) += am62ax/
+obj-$(CONFIG_CPU_V7R) += r5/
obj-$(CONFIG_ARM64) += arm64-mmu.o
-obj-$(CONFIG_CPU_V7R) += r5_mpu.o lowlevel_init.o
obj-$(CONFIG_ARM64) += cache.o
obj-$(CONFIG_OF_LIBFDT) += common_fdt.o
ifeq ($(CONFIG_OF_LIBFDT)$(CONFIG_OF_SYSTEM_SETUP),yy)
@@ -24,6 +20,5 @@
obj-$(CONFIG_SOC_K3_AM642) += am642_init.o
obj-$(CONFIG_SOC_K3_AM625) += am625_init.o
obj-$(CONFIG_SOC_K3_AM62A7) += am62a7_init.o
-obj-$(CONFIG_K3_LOAD_SYSFW) += sysfw-loader.o
endif
obj-y += common.o security.o
diff --git a/arch/arm/mach-k3/am625_init.c b/arch/arm/mach-k3/am625_init.c
index 8fa36f7..1d4ef35 100644
--- a/arch/arm/mach-k3/am625_init.c
+++ b/arch/arm/mach-k3/am625_init.c
@@ -209,7 +209,7 @@
if (ret)
panic("DRAM init failed: %d\n", ret);
}
- spl_enable_dcache();
+ spl_enable_cache();
}
u32 spl_mmc_boot_mode(struct mmc *mmc, const u32 boot_device)
diff --git a/arch/arm/mach-k3/am62ax/Kconfig b/arch/arm/mach-k3/am62ax/Kconfig
new file mode 100644
index 0000000..c5f1ef8
--- /dev/null
+++ b/arch/arm/mach-k3/am62ax/Kconfig
@@ -0,0 +1,36 @@
+# SPDX-License-Identifier: GPL-2.0+
+#
+# Copyright (C) 2023 Texas Instruments Incorporated - https://www.ti.com/
+# Andrew Davis <afd@ti.com>
+
+if SOC_K3_AM62A7
+
+choice
+ prompt "K3 AM62Ax based boards"
+ optional
+
+config TARGET_AM62A7_A53_EVM
+ bool "TI K3 based AM62A7 EVM running on A53"
+ select ARM64
+ select BINMAN
+ imply BOARD
+ imply SPL_BOARD
+ imply TI_I2C_BOARD_DETECT
+
+config TARGET_AM62A7_R5_EVM
+ bool "TI K3 based AM62A7 EVM running on R5"
+ select CPU_V7R
+ select SYS_THUMB_BUILD
+ select K3_LOAD_SYSFW
+ select RAM
+ select SPL_RAM
+ select K3_DDRSS
+ select BINMAN
+ imply SYS_K3_SPL_ATF
+ imply TI_I2C_BOARD_DETECT
+
+endchoice
+
+source "board/ti/am62ax/Kconfig"
+
+endif
diff --git a/arch/arm/mach-k3/am62x/Kconfig b/arch/arm/mach-k3/am62x/Kconfig
new file mode 100644
index 0000000..8091d72
--- /dev/null
+++ b/arch/arm/mach-k3/am62x/Kconfig
@@ -0,0 +1,50 @@
+# SPDX-License-Identifier: GPL-2.0+
+#
+# Copyright (C) 2023 Texas Instruments Incorporated - https://www.ti.com/
+# Andrew Davis <afd@ti.com>
+
+if SOC_K3_AM625
+
+choice
+ prompt "K3 AM62x based boards"
+ optional
+
+config TARGET_AM625_A53_EVM
+ bool "TI K3 based AM625 EVM running on A53"
+ select ARM64
+ select BINMAN
+
+config TARGET_AM625_R5_EVM
+ bool "TI K3 based AM625 EVM running on R5"
+ select CPU_V7R
+ select SYS_THUMB_BUILD
+ select K3_LOAD_SYSFW
+ select RAM
+ select SPL_RAM
+ select K3_DDRSS
+ select BINMAN
+ imply SYS_K3_SPL_ATF
+
+config TARGET_VERDIN_AM62_A53
+ bool "Toradex Verdin AM62 running on A53"
+ select ARM64
+ select BINMAN
+
+config TARGET_VERDIN_AM62_R5
+ bool "Toradex Verdin AM62 running on R5"
+ select CPU_V7R
+ select SYS_THUMB_BUILD
+ select K3_LOAD_SYSFW
+ select RAM
+ select SPL_RAM
+ select K3_DDRSS
+ select BINMAN
+ imply SYS_K3_SPL_ATF
+
+endchoice
+
+source "board/beagle/beagleplay/Kconfig"
+source "board/ti/am62x/Kconfig"
+source "board/toradex/verdin-am62/Kconfig"
+
+endif
diff --git a/arch/arm/mach-k3/am64x/Kconfig b/arch/arm/mach-k3/am64x/Kconfig
new file mode 100644
index 0000000..6f7b003
--- /dev/null
+++ b/arch/arm/mach-k3/am64x/Kconfig
@@ -0,0 +1,36 @@
+# SPDX-License-Identifier: GPL-2.0+
+#
+# Copyright (C) 2023 Texas Instruments Incorporated - https://www.ti.com/
+# Andrew Davis <afd@ti.com>
+
+if SOC_K3_AM642
+
+choice
+ prompt "K3 AM64 based boards"
+ optional
+
+config TARGET_AM642_A53_EVM
+ bool "TI K3 based AM642 EVM running on A53"
+ select ARM64
+ select BINMAN
+ imply BOARD
+ imply SPL_BOARD
+ imply TI_I2C_BOARD_DETECT
+
+config TARGET_AM642_R5_EVM
+ bool "TI K3 based AM642 EVM running on R5"
+ select CPU_V7R
+ select SYS_THUMB_BUILD
+ select K3_LOAD_SYSFW
+ select RAM
+ select SPL_RAM
+ select K3_DDRSS
+ select BINMAN
+ imply SYS_K3_SPL_ATF
+ imply TI_I2C_BOARD_DETECT
+
+endchoice
+
+source "board/ti/am64x/Kconfig"
+
+endif
diff --git a/arch/arm/mach-k3/am654_init.c b/arch/arm/mach-k3/am654_init.c
index 2c5d633..7c2a143 100644
--- a/arch/arm/mach-k3/am654_init.c
+++ b/arch/arm/mach-k3/am654_init.c
@@ -2,7 +2,7 @@
/*
* AM6: SoC specific initialization
*
- * Copyright (C) 2017-2018 Texas Instruments Incorporated - http://www.ti.com/
+ * Copyright (C) 2017-2018 Texas Instruments Incorporated - https://www.ti.com/
* Lokesh Vutla <lokeshvutla@ti.com>
*/
@@ -258,7 +258,7 @@
if (ret)
panic("DRAM init failed: %d\n", ret);
#endif
- spl_enable_dcache();
+ spl_enable_cache();
}
u32 spl_mmc_boot_mode(struct mmc *mmc, const u32 boot_device)
diff --git a/arch/arm/mach-k3/am65x/Kconfig b/arch/arm/mach-k3/am65x/Kconfig
new file mode 100644
index 0000000..f17b641
--- /dev/null
+++ b/arch/arm/mach-k3/am65x/Kconfig
@@ -0,0 +1,45 @@
+# SPDX-License-Identifier: GPL-2.0+
+#
+# Copyright (C) 2023 Texas Instruments Incorporated - https://www.ti.com/
+# Andrew Davis <afd@ti.com>
+
+if SOC_K3_AM654
+
+choice
+ prompt "K3 AM65 based boards"
+ optional
+
+config TARGET_AM654_A53_EVM
+ bool "TI K3 based AM654 EVM running on A53"
+ select ARM64
+ select SYS_DISABLE_DCACHE_OPS
+ select BOARD_LATE_INIT
+ select BINMAN
+ imply TI_I2C_BOARD_DETECT
+
+config TARGET_AM654_R5_EVM
+ bool "TI K3 based AM654 EVM running on R5"
+ select CPU_V7R
+ select SYS_THUMB_BUILD
+ select K3_LOAD_SYSFW
+ select K3_AM654_DDRSS
+ select BINMAN
+ imply SYS_K3_SPL_ATF
+ imply TI_I2C_BOARD_DETECT
+
+config TARGET_IOT2050_A53
+ bool "IOT2050 running on A53"
+ depends on SOC_K3_AM654
+ select ARM64
+ select BOARD_LATE_INIT
+ select SYS_DISABLE_DCACHE_OPS
+ select BINMAN
+ help
+ This builds U-Boot for the IOT2050 devices.
+
+endchoice
+
+source "board/ti/am65x/Kconfig"
+source "board/siemens/iot2050/Kconfig"
+
+endif
diff --git a/arch/arm/mach-k3/arm64-mmu.c b/arch/arm/mach-k3/arm64-mmu.c
index 14e7c89..e8db533 100644
--- a/arch/arm/mach-k3/arm64-mmu.c
+++ b/arch/arm/mach-k3/arm64-mmu.c
@@ -67,12 +67,11 @@
#ifdef CONFIG_SOC_K3_J721E
-#ifdef CONFIG_TARGET_J721E_A72_EVM
-/* NR_DRAM_BANKS + 32bit IO + 64bit IO + terminator */
-#define NR_MMU_REGIONS (CONFIG_NR_DRAM_BANKS + 6)
+#ifdef CONFIG_SOC_K3_J721E_J7200
+#define NR_MMU_REGIONS (CONFIG_NR_DRAM_BANKS + 5)
/* ToDo: Add 64bit IO */
-struct mm_region j721e_mem_map[NR_MMU_REGIONS] = {
+struct mm_region j7200_mem_map[NR_MMU_REGIONS] = {
{
.virt = 0x0UL,
.phys = 0x0UL,
@@ -89,13 +88,13 @@
}, {
.virt = 0xa0000000UL,
.phys = 0xa0000000UL,
- .size = 0x1bc00000UL,
+ .size = 0x04800000UL,
.attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL_NC) |
PTE_BLOCK_NON_SHARE
}, {
- .virt = 0xbbc00000UL,
- .phys = 0xbbc00000UL,
- .size = 0x44400000UL,
+ .virt = 0xa4800000UL,
+ .phys = 0xa4800000UL,
+ .size = 0x5b800000UL,
.attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
PTE_BLOCK_INNER_SHARE
}, {
@@ -112,25 +111,20 @@
PTE_BLOCK_NON_SHARE |
PTE_BLOCK_PXN | PTE_BLOCK_UXN
}, {
- .virt = 0x4d80000000UL,
- .phys = 0x4d80000000UL,
- .size = 0x0002000000UL,
- .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL_NC) |
- PTE_BLOCK_INNER_SHARE
- }, {
/* List terminator */
0,
}
};
-struct mm_region *mem_map = j721e_mem_map;
-#endif /* CONFIG_TARGET_J721E_A72_EVM */
+struct mm_region *mem_map = j7200_mem_map;
-#ifdef CONFIG_TARGET_J7200_A72_EVM
-#define NR_MMU_REGIONS (CONFIG_NR_DRAM_BANKS + 5)
+#else /* CONFIG_SOC_K3_J721E_J7200 */
+
+/* NR_DRAM_BANKS + 32bit IO + 64bit IO + terminator */
+#define NR_MMU_REGIONS (CONFIG_NR_DRAM_BANKS + 6)
/* ToDo: Add 64bit IO */
-struct mm_region j7200_mem_map[NR_MMU_REGIONS] = {
+struct mm_region j721e_mem_map[NR_MMU_REGIONS] = {
{
.virt = 0x0UL,
.phys = 0x0UL,
@@ -147,13 +141,13 @@
}, {
.virt = 0xa0000000UL,
.phys = 0xa0000000UL,
- .size = 0x04800000UL,
+ .size = 0x1bc00000UL,
.attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL_NC) |
PTE_BLOCK_NON_SHARE
}, {
- .virt = 0xa4800000UL,
- .phys = 0xa4800000UL,
- .size = 0x5b800000UL,
+ .virt = 0xbbc00000UL,
+ .phys = 0xbbc00000UL,
+ .size = 0x44400000UL,
.attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
PTE_BLOCK_INNER_SHARE
}, {
@@ -170,13 +164,19 @@
PTE_BLOCK_NON_SHARE |
PTE_BLOCK_PXN | PTE_BLOCK_UXN
}, {
+ .virt = 0x4d80000000UL,
+ .phys = 0x4d80000000UL,
+ .size = 0x0002000000UL,
+ .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL_NC) |
+ PTE_BLOCK_INNER_SHARE
+ }, {
/* List terminator */
0,
}
};
-struct mm_region *mem_map = j7200_mem_map;
-#endif /* CONFIG_TARGET_J7200_A72_EVM */
+struct mm_region *mem_map = j721e_mem_map;
+#endif /* CONFIG_SOC_K3_J721E_J7200 */
#endif /* CONFIG_SOC_K3_J721E */
diff --git a/arch/arm/mach-k3/cache.S b/arch/arm/mach-k3/cache.S
index a5717ea..17cfb12 100644
--- a/arch/arm/mach-k3/cache.S
+++ b/arch/arm/mach-k3/cache.S
@@ -1,6 +1,6 @@
/* SPDX-License-Identifier: GPL-2.0 */
/*
- * Copyright (C) 2020 Texas Instruments Incorporated - http://www.ti.com/
+ * Copyright (C) 2020 Texas Instruments Incorporated - https://www.ti.com/
* Andrew F. Davis <afd@ti.com>
*/
diff --git a/arch/arm/mach-k3/common.c b/arch/arm/mach-k3/common.c
index eff2fff..fd400e7 100644
--- a/arch/arm/mach-k3/common.c
+++ b/arch/arm/mach-k3/common.c
@@ -2,7 +2,7 @@
/*
* K3: Common Architecture initialization
*
- * Copyright (C) 2018 Texas Instruments Incorporated - http://www.ti.com/
+ * Copyright (C) 2018 Texas Instruments Incorporated - https://www.ti.com/
* Lokesh Vutla <lokeshvutla@ti.com>
*/
@@ -521,7 +521,7 @@
}
}
-void spl_enable_dcache(void)
+void spl_enable_cache(void)
{
#if !(defined(CONFIG_SYS_ICACHE_OFF) && defined(CONFIG_SYS_DCACHE_OFF))
phys_addr_t ram_top = CFG_SYS_SDRAM_BASE;
@@ -542,7 +542,7 @@
gd->arch.tlb_addr + gd->arch.tlb_size);
gd->relocaddr = gd->arch.tlb_addr;
- dcache_enable();
+ enable_caches();
#endif
}
diff --git a/arch/arm/mach-k3/common.h b/arch/arm/mach-k3/common.h
index eabb44f..e9db9fb 100644
--- a/arch/arm/mach-k3/common.h
+++ b/arch/arm/mach-k3/common.h
@@ -2,7 +2,7 @@
/*
* K3: Architecture common definitions
*
- * Copyright (C) 2018 Texas Instruments Incorporated - http://www.ti.com/
+ * Copyright (C) 2018 Texas Instruments Incorporated - https://www.ti.com/
* Lokesh Vutla <lokeshvutla@ti.com>
*/
@@ -37,7 +37,7 @@
void remove_fwl_configs(struct fwl_data *fwl_data, size_t fwl_data_size);
int load_firmware(char *name_fw, char *name_loadaddr, u32 *loadaddr);
void k3_sysfw_print_ver(void);
-void spl_enable_dcache(void);
+void spl_enable_cache(void);
void mmr_unlock(uintptr_t base, u32 partition);
bool is_rom_loaded_sysfw(struct rom_extended_boot_data *data);
enum k3_device_type get_device_type(void);
diff --git a/arch/arm/mach-k3/include/mach/am6_hardware.h b/arch/arm/mach-k3/include/mach/am6_hardware.h
index 029041f..9913964 100644
--- a/arch/arm/mach-k3/include/mach/am6_hardware.h
+++ b/arch/arm/mach-k3/include/mach/am6_hardware.h
@@ -2,7 +2,7 @@
/*
* K3: AM6 SoC definitions, structures etc.
*
- * (C) Copyright (C) 2018 Texas Instruments Incorporated - http://www.ti.com/
+ * (C) Copyright (C) 2018 Texas Instruments Incorporated - https://www.ti.com/
*/
#ifndef __ASM_ARCH_AM6_HARDWARE_H
#define __ASM_ARCH_AM6_HARDWARE_H
diff --git a/arch/arm/mach-k3/include/mach/am6_spl.h b/arch/arm/mach-k3/include/mach/am6_spl.h
index 61e0380..4c6950f 100644
--- a/arch/arm/mach-k3/include/mach/am6_spl.h
+++ b/arch/arm/mach-k3/include/mach/am6_spl.h
@@ -1,6 +1,6 @@
/* SPDX-License-Identifier: GPL-2.0+ */
/*
- * Copyright (C) 2018 Texas Instruments Incorporated - http://www.ti.com/
+ * Copyright (C) 2018 Texas Instruments Incorporated - https://www.ti.com/
* Lokesh Vutla <lokeshvutla@ti.com>
*/
#ifndef _ASM_ARCH_AM6_SPL_H_
diff --git a/arch/arm/mach-k3/include/mach/clock.h b/arch/arm/mach-k3/include/mach/clock.h
index e3adbcd..32368ce 100644
--- a/arch/arm/mach-k3/include/mach/clock.h
+++ b/arch/arm/mach-k3/include/mach/clock.h
@@ -2,7 +2,7 @@
/*
* K3: Common SoC clock definitions.
*
- * (C) Copyright (C) 2018 Texas Instruments Incorporated - http://www.ti.com/
+ * (C) Copyright (C) 2018 Texas Instruments Incorporated - https://www.ti.com/
*/
#ifndef __ASM_ARCH_CLOCK_H
#define __ASM_ARCH_CLOCK_H
diff --git a/arch/arm/mach-k3/include/mach/hardware.h b/arch/arm/mach-k3/include/mach/hardware.h
index 65742c4..a1a9dfb 100644
--- a/arch/arm/mach-k3/include/mach/hardware.h
+++ b/arch/arm/mach-k3/include/mach/hardware.h
@@ -1,6 +1,6 @@
/* SPDX-License-Identifier: GPL-2.0+ */
/*
- * Copyright (C) 2018 Texas Instruments Incorporated - http://www.ti.com/
+ * Copyright (C) 2018 Texas Instruments Incorporated - https://www.ti.com/
* Lokesh Vutla <lokeshvutla@ti.com>
*/
#ifndef _ASM_ARCH_HARDWARE_H_
diff --git a/arch/arm/mach-k3/include/mach/j721e_hardware.h b/arch/arm/mach-k3/include/mach/j721e_hardware.h
index 376db38..7803411 100644
--- a/arch/arm/mach-k3/include/mach/j721e_hardware.h
+++ b/arch/arm/mach-k3/include/mach/j721e_hardware.h
@@ -2,7 +2,7 @@
/*
* K3: J721E SoC definitions, structures etc.
*
- * (C) Copyright (C) 2018-2019 Texas Instruments Incorporated - http://www.ti.com/
+ * (C) Copyright (C) 2018-2019 Texas Instruments Incorporated - https://www.ti.com/
*/
#ifndef __ASM_ARCH_J721E_HARDWARE_H
#define __ASM_ARCH_J721E_HARDWARE_H
diff --git a/arch/arm/mach-k3/include/mach/j721e_spl.h b/arch/arm/mach-k3/include/mach/j721e_spl.h
index e894791..ed3d733 100644
--- a/arch/arm/mach-k3/include/mach/j721e_spl.h
+++ b/arch/arm/mach-k3/include/mach/j721e_spl.h
@@ -1,6 +1,6 @@
/* SPDX-License-Identifier: GPL-2.0+ */
/*
- * Copyright (C) 2018-2019 Texas Instruments Incorporated - http://www.ti.com/
+ * Copyright (C) 2018-2019 Texas Instruments Incorporated - https://www.ti.com/
* Lokesh Vutla <lokeshvutla@ti.com>
*/
#ifndef _ASM_ARCH_J721E_SPL_H_
diff --git a/arch/arm/mach-k3/include/mach/j721s2_hardware.h b/arch/arm/mach-k3/include/mach/j721s2_hardware.h
index 7948bcf..ad4fcdd 100644
--- a/arch/arm/mach-k3/include/mach/j721s2_hardware.h
+++ b/arch/arm/mach-k3/include/mach/j721s2_hardware.h
@@ -2,7 +2,7 @@
/*
* K3: J721S2 SoC definitions, structures etc.
*
- * (C) Copyright (C) 2021 Texas Instruments Incorporated - http://www.ti.com/
+ * (C) Copyright (C) 2021 Texas Instruments Incorporated - https://www.ti.com/
*/
#ifndef __ASM_ARCH_J721S2_HARDWARE_H
#define __ASM_ARCH_J721S2_HARDWARE_H
diff --git a/arch/arm/mach-k3/include/mach/j721s2_spl.h b/arch/arm/mach-k3/include/mach/j721s2_spl.h
index 94b6c13..d8fae2c 100644
--- a/arch/arm/mach-k3/include/mach/j721s2_spl.h
+++ b/arch/arm/mach-k3/include/mach/j721s2_spl.h
@@ -1,6 +1,6 @@
/* SPDX-License-Identifier: GPL-2.0+ */
/*
- * Copyright (C) 2021 Texas Instruments Incorporated - http://www.ti.com/
+ * Copyright (C) 2021 Texas Instruments Incorporated - https://www.ti.com/
* David Huang <d-huang@ti.com>
*/
#ifndef _ASM_ARCH_J721S2_SPL_H_
diff --git a/arch/arm/mach-k3/include/mach/spl.h b/arch/arm/mach-k3/include/mach/spl.h
index 356cd89..3ddc7eb 100644
--- a/arch/arm/mach-k3/include/mach/spl.h
+++ b/arch/arm/mach-k3/include/mach/spl.h
@@ -1,6 +1,6 @@
/* SPDX-License-Identifier: GPL-2.0+ */
/*
- * Copyright (C) 2018 Texas Instruments Incorporated - http://www.ti.com/
+ * Copyright (C) 2018 Texas Instruments Incorporated - https://www.ti.com/
* Lokesh Vutla <lokeshvutla@ti.com>
*/
#ifndef _ASM_ARCH_SPL_H_
diff --git a/arch/arm/mach-k3/j7200/Makefile b/arch/arm/mach-k3/j7200/Makefile
deleted file mode 100644
index ff9abd7..0000000
--- a/arch/arm/mach-k3/j7200/Makefile
+++ /dev/null
@@ -1,5 +0,0 @@
-# SPDX-License-Identifier: GPL-2.0+
-#
-# Copyright (C) 2020 Texas Instruments Incorporated - http://www.ti.com/
-obj-y += clk-data.o
-obj-y += dev-data.o
diff --git a/arch/arm/mach-k3/j721e/Kconfig b/arch/arm/mach-k3/j721e/Kconfig
new file mode 100644
index 0000000..0761b82
--- /dev/null
+++ b/arch/arm/mach-k3/j721e/Kconfig
@@ -0,0 +1,58 @@
+# SPDX-License-Identifier: GPL-2.0+
+#
+# Copyright (C) 2023 Texas Instruments Incorporated - https://www.ti.com/
+# Andrew Davis <afd@ti.com>
+
+if SOC_K3_J721E
+
+choice
+ prompt "K3 J721E based boards"
+ optional
+
+config TARGET_J721E_A72_EVM
+ bool "TI K3 based J721E EVM running on A72"
+ select ARM64
+ select BOARD_LATE_INIT
+ imply TI_I2C_BOARD_DETECT
+ select SYS_DISABLE_DCACHE_OPS
+ select BINMAN
+
+config TARGET_J721E_R5_EVM
+ bool "TI K3 based J721E EVM running on R5"
+ select CPU_V7R
+ select SYS_THUMB_BUILD
+ select K3_LOAD_SYSFW
+ select RAM
+ select SPL_RAM
+ select K3_DDRSS
+ select BINMAN
+ imply SYS_K3_SPL_ATF
+ imply TI_I2C_BOARD_DETECT
+
+config TARGET_J7200_A72_EVM
+ bool "TI K3 based J7200 EVM running on A72"
+ select ARM64
+ select SOC_K3_J721E_J7200
+ select BOARD_LATE_INIT
+ imply TI_I2C_BOARD_DETECT
+ select SYS_DISABLE_DCACHE_OPS
+ select BINMAN
+
+config TARGET_J7200_R5_EVM
+ bool "TI K3 based J7200 EVM running on R5"
+ select CPU_V7R
+ select SYS_THUMB_BUILD
+ select K3_LOAD_SYSFW
+ select RAM
+ select SPL_RAM
+ select K3_DDRSS
+ select BINMAN
+ imply SYS_K3_SPL_ATF
+ imply TI_I2C_BOARD_DETECT
+
+endchoice
+
+source "board/beagle/beagleboneai64/Kconfig"
+source "board/ti/j721e/Kconfig"
+
+endif
diff --git a/arch/arm/mach-k3/j721e/Makefile b/arch/arm/mach-k3/j721e/Makefile
deleted file mode 100644
index ff9abd7..0000000
--- a/arch/arm/mach-k3/j721e/Makefile
+++ /dev/null
@@ -1,5 +0,0 @@
-# SPDX-License-Identifier: GPL-2.0+
-#
-# Copyright (C) 2020 Texas Instruments Incorporated - http://www.ti.com/
-obj-y += clk-data.o
-obj-y += dev-data.o
diff --git a/arch/arm/mach-k3/j721e_init.c b/arch/arm/mach-k3/j721e_init.c
index 099301d..c2976c4 100644
--- a/arch/arm/mach-k3/j721e_init.c
+++ b/arch/arm/mach-k3/j721e_init.c
@@ -2,7 +2,7 @@
/*
* J721E: SoC specific initialization
*
- * Copyright (C) 2018-2019 Texas Instruments Incorporated - http://www.ti.com/
+ * Copyright (C) 2018-2019 Texas Instruments Incorporated - https://www.ti.com/
* Lokesh Vutla <lokeshvutla@ti.com>
*/
@@ -286,14 +286,21 @@
if (ret)
panic("DRAM init failed: %d\n", ret);
#endif
- spl_enable_dcache();
+ spl_enable_cache();
}
u32 spl_mmc_boot_mode(struct mmc *mmc, const u32 boot_device)
{
switch (boot_device) {
case BOOT_DEVICE_MMC1:
- return (spl_mmc_emmc_boot_partition(mmc) ? MMCSD_MODE_EMMCBOOT : MMCSD_MODE_FS);
+ if (IS_ENABLED(CONFIG_SUPPORT_EMMC_BOOT)) {
+ if (spl_mmc_emmc_boot_partition(mmc))
+ return MMCSD_MODE_EMMCBOOT;
+ return MMCSD_MODE_FS;
+ }
+ if (IS_ENABLED(CONFIG_SPL_FS_FAT) || IS_ENABLED(CONFIG_SPL_FS_EXT4))
+ return MMCSD_MODE_FS;
+ return MMCSD_MODE_EMMCBOOT;
case BOOT_DEVICE_MMC2:
return MMCSD_MODE_FS;
default:
diff --git a/arch/arm/mach-k3/j721s2/Kconfig b/arch/arm/mach-k3/j721s2/Kconfig
new file mode 100644
index 0000000..8b54c04
--- /dev/null
+++ b/arch/arm/mach-k3/j721s2/Kconfig
@@ -0,0 +1,36 @@
+# SPDX-License-Identifier: GPL-2.0+
+#
+# Copyright (C) 2023 Texas Instruments Incorporated - https://www.ti.com/
+# Andrew Davis <afd@ti.com>
+
+if SOC_K3_J721S2
+
+choice
+ prompt "K3 J721S2 based boards"
+ optional
+
+config TARGET_J721S2_A72_EVM
+ bool "TI K3 based J721S2 EVM running on A72"
+ select ARM64
+ select BOARD_LATE_INIT
+ imply TI_I2C_BOARD_DETECT
+ select SYS_DISABLE_DCACHE_OPS
+ select BINMAN
+
+config TARGET_J721S2_R5_EVM
+ bool "TI K3 based J721S2 EVM running on R5"
+ select CPU_V7R
+ select SYS_THUMB_BUILD
+ select K3_LOAD_SYSFW
+ select RAM
+ select SPL_RAM
+ select K3_DDRSS
+ select BINMAN
+ imply SYS_K3_SPL_ATF
+ imply TI_I2C_BOARD_DETECT
+
+endchoice
+
+source "board/ti/j721s2/Kconfig"
+
+endif
diff --git a/arch/arm/mach-k3/j721s2/Makefile b/arch/arm/mach-k3/j721s2/Makefile
deleted file mode 100644
index 7bcd490..0000000
--- a/arch/arm/mach-k3/j721s2/Makefile
+++ /dev/null
@@ -1,5 +0,0 @@
-# SPDX-License-Identifier: GPL-2.0+
-#
-# Copyright (C) 2021 Texas Instruments Incorporated - http://www.ti.com/
-obj-y += clk-data.o
-obj-y += dev-data.o
diff --git a/arch/arm/mach-k3/j721s2_init.c b/arch/arm/mach-k3/j721s2_init.c
index 7d44810..fb0708b 100644
--- a/arch/arm/mach-k3/j721s2_init.c
+++ b/arch/arm/mach-k3/j721s2_init.c
@@ -2,7 +2,7 @@
/*
* J721E: SoC specific initialization
*
- * Copyright (C) 2021 Texas Instruments Incorporated - http://www.ti.com/
+ * Copyright (C) 2021 Texas Instruments Incorporated - https://www.ti.com/
* David Huang <d-huang@ti.com>
*/
@@ -231,7 +231,7 @@
if (ret)
panic("DRAM 1 init failed: %d\n", ret);
}
- spl_enable_dcache();
+ spl_enable_cache();
}
/* Support for the various EVM / SK families */
diff --git a/board/ti/keys/custMpk.crt b/arch/arm/mach-k3/keys/custMpk.crt
similarity index 100%
rename from board/ti/keys/custMpk.crt
rename to arch/arm/mach-k3/keys/custMpk.crt
diff --git a/board/ti/keys/custMpk.key b/arch/arm/mach-k3/keys/custMpk.key
similarity index 100%
rename from board/ti/keys/custMpk.key
rename to arch/arm/mach-k3/keys/custMpk.key
diff --git a/board/ti/keys/custMpk.pem b/arch/arm/mach-k3/keys/custMpk.pem
similarity index 100%
rename from board/ti/keys/custMpk.pem
rename to arch/arm/mach-k3/keys/custMpk.pem
diff --git a/board/ti/keys/ti-degenerate-key.pem b/arch/arm/mach-k3/keys/ti-degenerate-key.pem
similarity index 100%
rename from board/ti/keys/ti-degenerate-key.pem
rename to arch/arm/mach-k3/keys/ti-degenerate-key.pem
diff --git a/arch/arm/mach-k3/r5/Kconfig b/arch/arm/mach-k3/r5/Kconfig
new file mode 100644
index 0000000..ae79f8f
--- /dev/null
+++ b/arch/arm/mach-k3/r5/Kconfig
@@ -0,0 +1,45 @@
+config K3_LOAD_SYSFW
+ bool
+
+config K3_SYSFW_IMAGE_NAME
+ string "File name of SYSFW firmware and configuration blob"
+ depends on K3_LOAD_SYSFW
+ default "sysfw.itb"
+ help
+ Filename of the combined System Firmware and configuration image tree
+ blob to be loaded when booting from a filesystem.
+
+config K3_SYSFW_IMAGE_MMCSD_RAW_MODE_SECT
+ hex "MMC sector to load SYSFW firmware and configuration blob from"
+ depends on K3_LOAD_SYSFW && SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR
+ default 0x3600
+ help
+ Address on the MMC to load the combined System Firmware and
+ configuration image tree blob from, when the MMC is being used
+ in raw mode. Units: MMC sectors (1 sector = 512 bytes).
+
+config K3_SYSFW_IMAGE_MMCSD_RAW_MODE_PART
+ hex "MMC partition to load SYSFW firmware and configuration blob from"
+ depends on K3_LOAD_SYSFW && SYS_MMCSD_RAW_MODE_U_BOOT_USE_PARTITION
+ default 2
+ help
+ Partition on the MMC to the combined System Firmware and configuration
+ image tree blob from, when the MMC is being used in raw mode.
+
+config K3_SYSFW_IMAGE_SIZE_MAX
+ int "Amount of memory dynamically allocated for loading SYSFW blob"
+ depends on K3_LOAD_SYSFW
+ default 280000
+ help
+ Amount of memory (in bytes) reserved through dynamic allocation at
+ runtime for loading the combined System Firmware and configuration image
+ tree blob. Keep it as tight as possible, as this directly affects the
+ overall SPL memory footprint.
+
+config K3_SYSFW_IMAGE_SPI_OFFS
+ hex "SPI offset of SYSFW firmware and configuration blob"
+ depends on K3_LOAD_SYSFW
+ default 0x6C0000
+ help
+ Offset of the combined System Firmware and configuration image tree
+ blob to be loaded when booting from a SPI flash memory.
diff --git a/arch/arm/mach-k3/r5/Makefile b/arch/arm/mach-k3/r5/Makefile
new file mode 100644
index 0000000..b99199d
--- /dev/null
+++ b/arch/arm/mach-k3/r5/Makefile
@@ -0,0 +1,17 @@
+# SPDX-License-Identifier: GPL-2.0+
+#
+# Copyright (C) 2023 Texas Instruments Incorporated - https://www.ti.com/
+# Andrew Davis <afd@ti.com>
+
+obj-$(CONFIG_SOC_K3_J721E) += j721e/
+obj-$(CONFIG_SOC_K3_J721E) += j7200/
+obj-$(CONFIG_SOC_K3_J721S2) += j721s2/
+obj-$(CONFIG_SOC_K3_AM625) += am62x/
+obj-$(CONFIG_SOC_K3_AM62A7) += am62ax/
+
+obj-y += lowlevel_init.o
+obj-y += r5_mpu.o
+
+ifeq ($(CONFIG_SPL_BUILD),y)
+obj-$(CONFIG_K3_LOAD_SYSFW) += sysfw-loader.o
+endif
diff --git a/arch/arm/mach-k3/am62ax/Makefile b/arch/arm/mach-k3/r5/am62ax/Makefile
similarity index 100%
rename from arch/arm/mach-k3/am62ax/Makefile
rename to arch/arm/mach-k3/r5/am62ax/Makefile
diff --git a/arch/arm/mach-k3/am62ax/am62a_qos_data.c b/arch/arm/mach-k3/r5/am62ax/am62a_qos_data.c
similarity index 100%
rename from arch/arm/mach-k3/am62ax/am62a_qos_data.c
rename to arch/arm/mach-k3/r5/am62ax/am62a_qos_data.c
diff --git a/arch/arm/mach-k3/am62ax/clk-data.c b/arch/arm/mach-k3/r5/am62ax/clk-data.c
similarity index 100%
rename from arch/arm/mach-k3/am62ax/clk-data.c
rename to arch/arm/mach-k3/r5/am62ax/clk-data.c
diff --git a/arch/arm/mach-k3/am62ax/dev-data.c b/arch/arm/mach-k3/r5/am62ax/dev-data.c
similarity index 98%
rename from arch/arm/mach-k3/am62ax/dev-data.c
rename to arch/arm/mach-k3/r5/am62ax/dev-data.c
index abf5d8e..6cced9e 100644
--- a/arch/arm/mach-k3/am62ax/dev-data.c
+++ b/arch/arm/mach-k3/r5/am62ax/dev-data.c
@@ -52,6 +52,7 @@
PSC_DEV(161, &soc_lpsc_list[5]),
PSC_DEV(162, &soc_lpsc_list[6]),
PSC_DEV(75, &soc_lpsc_list[7]),
+ PSC_DEV(36, &soc_lpsc_list[8]),
PSC_DEV(102, &soc_lpsc_list[8]),
PSC_DEV(146, &soc_lpsc_list[8]),
PSC_DEV(166, &soc_lpsc_list[9]),
diff --git a/arch/arm/mach-k3/am62x/Makefile b/arch/arm/mach-k3/r5/am62x/Makefile
similarity index 100%
rename from arch/arm/mach-k3/am62x/Makefile
rename to arch/arm/mach-k3/r5/am62x/Makefile
diff --git a/arch/arm/mach-k3/am62x/clk-data.c b/arch/arm/mach-k3/r5/am62x/clk-data.c
similarity index 100%
rename from arch/arm/mach-k3/am62x/clk-data.c
rename to arch/arm/mach-k3/r5/am62x/clk-data.c
diff --git a/arch/arm/mach-k3/am62x/dev-data.c b/arch/arm/mach-k3/r5/am62x/dev-data.c
similarity index 100%
rename from arch/arm/mach-k3/am62x/dev-data.c
rename to arch/arm/mach-k3/r5/am62x/dev-data.c
diff --git a/arch/arm/mach-k3/r5/j7200/Makefile b/arch/arm/mach-k3/r5/j7200/Makefile
new file mode 100644
index 0000000..0f91cf4
--- /dev/null
+++ b/arch/arm/mach-k3/r5/j7200/Makefile
@@ -0,0 +1,5 @@
+# SPDX-License-Identifier: GPL-2.0+
+#
+# Copyright (C) 2020 Texas Instruments Incorporated - https://www.ti.com/
+obj-y += clk-data.o
+obj-y += dev-data.o
diff --git a/arch/arm/mach-k3/j7200/clk-data.c b/arch/arm/mach-k3/r5/j7200/clk-data.c
similarity index 100%
rename from arch/arm/mach-k3/j7200/clk-data.c
rename to arch/arm/mach-k3/r5/j7200/clk-data.c
diff --git a/arch/arm/mach-k3/j7200/dev-data.c b/arch/arm/mach-k3/r5/j7200/dev-data.c
similarity index 100%
rename from arch/arm/mach-k3/j7200/dev-data.c
rename to arch/arm/mach-k3/r5/j7200/dev-data.c
diff --git a/arch/arm/mach-k3/r5/j721e/Makefile b/arch/arm/mach-k3/r5/j721e/Makefile
new file mode 100644
index 0000000..0f91cf4
--- /dev/null
+++ b/arch/arm/mach-k3/r5/j721e/Makefile
@@ -0,0 +1,5 @@
+# SPDX-License-Identifier: GPL-2.0+
+#
+# Copyright (C) 2020 Texas Instruments Incorporated - https://www.ti.com/
+obj-y += clk-data.o
+obj-y += dev-data.o
diff --git a/arch/arm/mach-k3/j721e/clk-data.c b/arch/arm/mach-k3/r5/j721e/clk-data.c
similarity index 100%
rename from arch/arm/mach-k3/j721e/clk-data.c
rename to arch/arm/mach-k3/r5/j721e/clk-data.c
diff --git a/arch/arm/mach-k3/j721e/dev-data.c b/arch/arm/mach-k3/r5/j721e/dev-data.c
similarity index 100%
rename from arch/arm/mach-k3/j721e/dev-data.c
rename to arch/arm/mach-k3/r5/j721e/dev-data.c
diff --git a/arch/arm/mach-k3/r5/j721s2/Makefile b/arch/arm/mach-k3/r5/j721s2/Makefile
new file mode 100644
index 0000000..e794bff
--- /dev/null
+++ b/arch/arm/mach-k3/r5/j721s2/Makefile
@@ -0,0 +1,5 @@
+# SPDX-License-Identifier: GPL-2.0+
+#
+# Copyright (C) 2021 Texas Instruments Incorporated - https://www.ti.com/
+obj-y += clk-data.o
+obj-y += dev-data.o
diff --git a/arch/arm/mach-k3/j721s2/clk-data.c b/arch/arm/mach-k3/r5/j721s2/clk-data.c
similarity index 100%
rename from arch/arm/mach-k3/j721s2/clk-data.c
rename to arch/arm/mach-k3/r5/j721s2/clk-data.c
diff --git a/arch/arm/mach-k3/j721s2/dev-data.c b/arch/arm/mach-k3/r5/j721s2/dev-data.c
similarity index 100%
rename from arch/arm/mach-k3/j721s2/dev-data.c
rename to arch/arm/mach-k3/r5/j721s2/dev-data.c
diff --git a/arch/arm/mach-k3/lowlevel_init.S b/arch/arm/mach-k3/r5/lowlevel_init.S
similarity index 78%
rename from arch/arm/mach-k3/lowlevel_init.S
rename to arch/arm/mach-k3/r5/lowlevel_init.S
index 70c5d1c..463ab0d 100644
--- a/arch/arm/mach-k3/lowlevel_init.S
+++ b/arch/arm/mach-k3/r5/lowlevel_init.S
@@ -1,6 +1,6 @@
/* SPDX-License-Identifier: GPL-2.0+ */
/*
- * Copyright (C) 2018 Texas Instruments Incorporated - http://www.ti.com/
+ * Copyright (C) 2018 Texas Instruments Incorporated - https://www.ti.com/
* Lokesh Vutla <lokeshvutla@ti.com>
*/
diff --git a/arch/arm/mach-k3/r5_mpu.c b/arch/arm/mach-k3/r5/r5_mpu.c
similarity index 95%
rename from arch/arm/mach-k3/r5_mpu.c
rename to arch/arm/mach-k3/r5/r5_mpu.c
index 6786e7e..3dbbcae 100644
--- a/arch/arm/mach-k3/r5_mpu.c
+++ b/arch/arm/mach-k3/r5/r5_mpu.c
@@ -2,13 +2,14 @@
/*
* K3: R5 MPU region definitions
*
- * Copyright (C) 2017-2018 Texas Instruments Incorporated - http://www.ti.com/
+ * Copyright (C) 2017-2018 Texas Instruments Incorporated - https://www.ti.com/
* Lokesh Vutla <lokeshvutla@ti.com>
*/
+#include <config.h>
#include <asm/io.h>
#include <linux/kernel.h>
-#include "common.h"
+#include <asm/armv7_mpu.h>
struct mpu_region_config k3_mpu_regions[16] = {
/*
diff --git a/arch/arm/mach-k3/sysfw-loader.c b/arch/arm/mach-k3/r5/sysfw-loader.c
similarity index 98%
rename from arch/arm/mach-k3/sysfw-loader.c
rename to arch/arm/mach-k3/r5/sysfw-loader.c
index aa401ae..94d051b 100644
--- a/arch/arm/mach-k3/sysfw-loader.c
+++ b/arch/arm/mach-k3/r5/sysfw-loader.c
@@ -2,7 +2,7 @@
/*
* K3: System Firmware Loader
*
- * Copyright (C) 2019 Texas Instruments Incorporated - http://www.ti.com/
+ * Copyright (C) 2019 Texas Instruments Incorporated - https://www.ti.com/
* Andreas Dannenberg <dannenberg@ti.com>
*/
@@ -22,7 +22,7 @@
#include <spi_flash.h>
#include <asm/io.h>
-#include "common.h"
+#include "../common.h"
DECLARE_GLOBAL_DATA_PTR;
diff --git a/arch/arm/mach-k3/security.c b/arch/arm/mach-k3/security.c
index 3b7c26c..22697a2 100644
--- a/arch/arm/mach-k3/security.c
+++ b/arch/arm/mach-k3/security.c
@@ -2,7 +2,7 @@
/*
* K3: Security functions
*
- * Copyright (C) 2018-2022 Texas Instruments Incorporated - http://www.ti.com/
+ * Copyright (C) 2018-2022 Texas Instruments Incorporated - https://www.ti.com/
* Andrew F. Davis <afd@ti.com>
*/
diff --git a/arch/arm/mach-k3/sysfw-loader.h b/arch/arm/mach-k3/sysfw-loader.h
index b23a9e8..e48c834 100644
--- a/arch/arm/mach-k3/sysfw-loader.h
+++ b/arch/arm/mach-k3/sysfw-loader.h
@@ -1,6 +1,6 @@
/* SPDX-License-Identifier: GPL-2.0+ */
/*
- * Copyright (C) 2019 Texas Instruments Incorporated - http://www.ti.com/
+ * Copyright (C) 2019 Texas Instruments Incorporated - https://www.ti.com/
* Andreas Dannenberg <dannenberg@ti.com>
*/
diff --git a/arch/arm/mach-keystone/clock.c b/arch/arm/mach-keystone/clock.c
index 0c59515..4f19379 100644
--- a/arch/arm/mach-keystone/clock.c
+++ b/arch/arm/mach-keystone/clock.c
@@ -6,7 +6,6 @@
* Texas Instruments Incorporated, <www.ti.com>
*/
-#include <common.h>
#include <asm/arch/clock.h>
#include <asm/arch/clock_defs.h>
#include <linux/bitops.h>
diff --git a/arch/arm/mach-keystone/cmd_clock.c b/arch/arm/mach-keystone/cmd_clock.c
index 72dc394..e9ecc05 100644
--- a/arch/arm/mach-keystone/cmd_clock.c
+++ b/arch/arm/mach-keystone/cmd_clock.c
@@ -6,7 +6,7 @@
* Texas Instruments Incorporated, <www.ti.com>
*/
-#include <common.h>
+#include <vsprintf.h>
#include <command.h>
#include <asm/arch/hardware.h>
#include <asm/arch/clock.h>
diff --git a/arch/arm/mach-keystone/cmd_mon.c b/arch/arm/mach-keystone/cmd_mon.c
index dc97bac..c6e7e2c 100644
--- a/arch/arm/mach-keystone/cmd_mon.c
+++ b/arch/arm/mach-keystone/cmd_mon.c
@@ -6,7 +6,6 @@
* Texas Instruments Incorporated, <www.ti.com>
*/
-#include <common.h>
#include <command.h>
#include <image.h>
#include <mach/mon.h>
diff --git a/arch/arm/mach-keystone/cmd_poweroff.c b/arch/arm/mach-keystone/cmd_poweroff.c
index f0ad917..0ad31ef 100644
--- a/arch/arm/mach-keystone/cmd_poweroff.c
+++ b/arch/arm/mach-keystone/cmd_poweroff.c
@@ -6,7 +6,6 @@
* Texas Instruments Incorporated, <www.ti.com>
*/
-#include <common.h>
#include <command.h>
#include <asm/arch/mon.h>
#include <asm/arch/psc_defs.h>
diff --git a/arch/arm/mach-keystone/ddr3.c b/arch/arm/mach-keystone/ddr3.c
index ea7d0b9..ca0fb70 100644
--- a/arch/arm/mach-keystone/ddr3.c
+++ b/arch/arm/mach-keystone/ddr3.c
@@ -9,7 +9,7 @@
#include <cpu_func.h>
#include <env.h>
#include <asm/io.h>
-#include <common.h>
+#include <vsprintf.h>
#include <asm/arch/msmc.h>
#include <asm/arch/ddr3.h>
#include <asm/arch/psc_defs.h>
diff --git a/arch/arm/mach-keystone/ddr3_spd.c b/arch/arm/mach-keystone/ddr3_spd.c
index 6f7f8ab..d4ff442 100644
--- a/arch/arm/mach-keystone/ddr3_spd.c
+++ b/arch/arm/mach-keystone/ddr3_spd.c
@@ -5,8 +5,8 @@
* (C) Copyright 2015-2016 Texas Instruments Incorporated, <www.ti.com>
*/
-#include <common.h>
#include <log.h>
+#include <string.h>
#include <i2c.h>
#include <ddr_spd.h>
diff --git a/arch/arm/mach-keystone/init.c b/arch/arm/mach-keystone/init.c
index 1954e69..39afaaa 100644
--- a/arch/arm/mach-keystone/init.c
+++ b/arch/arm/mach-keystone/init.c
@@ -6,7 +6,6 @@
* Texas Instruments Incorporated, <www.ti.com>
*/
-#include <common.h>
#include <cpu_func.h>
#include <init.h>
#include <ns16550.h>
diff --git a/arch/arm/mach-keystone/keystone.c b/arch/arm/mach-keystone/keystone.c
index efaabca..8846df3 100644
--- a/arch/arm/mach-keystone/keystone.c
+++ b/arch/arm/mach-keystone/keystone.c
@@ -6,7 +6,6 @@
* Texas Instruments Incorporated, <www.ti.com>
*/
-#include <common.h>
#include <env.h>
#include <init.h>
#include <asm/io.h>
diff --git a/arch/arm/mach-keystone/mon.c b/arch/arm/mach-keystone/mon.c
index b863bab..b945e19 100644
--- a/arch/arm/mach-keystone/mon.c
+++ b/arch/arm/mach-keystone/mon.c
@@ -2,13 +2,12 @@
/*
* K2x: Secure commands file
*
- * Copyright (C) 2012-2019 Texas Instruments Incorporated - http://www.ti.com/
+ * Copyright (C) 2012-2019 Texas Instruments Incorporated - https://www.ti.com/
*/
#include <hang.h>
#include <image.h>
#include <asm/unaligned.h>
-#include <common.h>
#include <command.h>
#include <mach/mon.h>
#include <spl.h>
diff --git a/arch/arm/mach-keystone/msmc.c b/arch/arm/mach-keystone/msmc.c
index f5cadfb..a20e0c9 100644
--- a/arch/arm/mach-keystone/msmc.c
+++ b/arch/arm/mach-keystone/msmc.c
@@ -6,7 +6,6 @@
* Texas Instruments Incorporated, <www.ti.com>
*/
-#include <common.h>
#include <asm/arch/msmc.h>
struct mpax {
diff --git a/arch/arm/mach-keystone/psc.c b/arch/arm/mach-keystone/psc.c
index 145aff8..84d64f3 100644
--- a/arch/arm/mach-keystone/psc.c
+++ b/arch/arm/mach-keystone/psc.c
@@ -6,7 +6,6 @@
* Texas Instruments Incorporated, <www.ti.com>
*/
-#include <common.h>
#include <linux/delay.h>
#include <linux/errno.h>
#include <asm/io.h>
diff --git a/arch/arm/mach-meson/board-info.c b/arch/arm/mach-meson/board-info.c
index 2421acd..95a29da 100644
--- a/arch/arm/mach-meson/board-info.c
+++ b/arch/arm/mach-meson/board-info.c
@@ -168,7 +168,7 @@
return socinfo;
}
-int show_board_info(void)
+int checkboard(void)
{
unsigned int socinfo;
diff --git a/arch/arm/mach-omap2/am33xx/Kconfig b/arch/arm/mach-omap2/am33xx/Kconfig
index 8cb0c57..bd5129b 100644
--- a/arch/arm/mach-omap2/am33xx/Kconfig
+++ b/arch/arm/mach-omap2/am33xx/Kconfig
@@ -105,15 +105,6 @@
select DM_SERIAL
imply CMD_DM
-config TARGET_DRACO
- bool "Support draco"
- select BOARD_LATE_INIT
- select DM
- select DM_GPIO
- select DM_SERIAL
- select FACTORYSET
- imply CMD_DM
-
config TARGET_ETAMIN
bool "Support etamin"
select BOARD_LATE_INIT
diff --git a/arch/arm/mach-omap2/am33xx/Makefile b/arch/arm/mach-omap2/am33xx/Makefile
index 2aa8013..3f1af7f 100644
--- a/arch/arm/mach-omap2/am33xx/Makefile
+++ b/arch/arm/mach-omap2/am33xx/Makefile
@@ -1,6 +1,6 @@
# SPDX-License-Identifier: GPL-2.0+
#
-# Copyright (C) 2011, Texas Instruments, Incorporated - http://www.ti.com/
+# Copyright (C) 2011, Texas Instruments, Incorporated - https://www.ti.com/
obj-$(CONFIG_AM33XX) += clock_am33xx.o
obj-$(CONFIG_AM43XX) += clock_am43xx.o
diff --git a/arch/arm/mach-omap2/am33xx/board.c b/arch/arm/mach-omap2/am33xx/board.c
index 06b4129..09659da 100644
--- a/arch/arm/mach-omap2/am33xx/board.c
+++ b/arch/arm/mach-omap2/am33xx/board.c
@@ -4,7 +4,7 @@
*
* Common board functions for AM33XX based boards
*
- * Copyright (C) 2011, Texas Instruments, Incorporated - http://www.ti.com/
+ * Copyright (C) 2011, Texas Instruments, Incorporated - https://www.ti.com/
*/
#include <common.h>
diff --git a/arch/arm/mach-omap2/am33xx/chilisom.c b/arch/arm/mach-omap2/am33xx/chilisom.c
index 459bac1..d4f2abe 100644
--- a/arch/arm/mach-omap2/am33xx/chilisom.c
+++ b/arch/arm/mach-omap2/am33xx/chilisom.c
@@ -1,6 +1,6 @@
// SPDX-License-Identifier: GPL-2.0+
/*
- * Copyright (C) 2011, Texas Instruments, Incorporated - http://www.ti.com/
+ * Copyright (C) 2011, Texas Instruments, Incorporated - https://www.ti.com/
* Copyright (C) 2017, Grinn - http://grinn-global.com/
*/
diff --git a/arch/arm/mach-omap2/am33xx/clk_synthesizer.c b/arch/arm/mach-omap2/am33xx/clk_synthesizer.c
index c9b9502..0969a40 100644
--- a/arch/arm/mach-omap2/am33xx/clk_synthesizer.c
+++ b/arch/arm/mach-omap2/am33xx/clk_synthesizer.c
@@ -4,7 +4,7 @@
*
* Clock synthesizer apis
*
- * Copyright (C) 2016, Texas Instruments, Incorporated - http://www.ti.com/
+ * Copyright (C) 2016, Texas Instruments, Incorporated - https://www.ti.com/
*/
diff --git a/arch/arm/mach-omap2/am33xx/clock.c b/arch/arm/mach-omap2/am33xx/clock.c
index 130ee6c..3273632 100644
--- a/arch/arm/mach-omap2/am33xx/clock.c
+++ b/arch/arm/mach-omap2/am33xx/clock.c
@@ -5,7 +5,7 @@
* Clock initialization for AM33XX boards.
* Derived from OMAP4 boards
*
- * Copyright (C) 2013, Texas Instruments, Incorporated - http://www.ti.com/
+ * Copyright (C) 2013, Texas Instruments, Incorporated - https://www.ti.com/
*/
#include <common.h>
#include <hang.h>
diff --git a/arch/arm/mach-omap2/am33xx/clock_am33xx.c b/arch/arm/mach-omap2/am33xx/clock_am33xx.c
index cd3b34b..d39e7e4 100644
--- a/arch/arm/mach-omap2/am33xx/clock_am33xx.c
+++ b/arch/arm/mach-omap2/am33xx/clock_am33xx.c
@@ -4,7 +4,7 @@
*
* clocks for AM33XX based boards
*
- * Copyright (C) 2013, Texas Instruments, Incorporated - http://www.ti.com/
+ * Copyright (C) 2013, Texas Instruments, Incorporated - https://www.ti.com/
*/
#include <common.h>
diff --git a/arch/arm/mach-omap2/am33xx/clock_am43xx.c b/arch/arm/mach-omap2/am33xx/clock_am43xx.c
index b98bb99..8039bc2 100644
--- a/arch/arm/mach-omap2/am33xx/clock_am43xx.c
+++ b/arch/arm/mach-omap2/am33xx/clock_am43xx.c
@@ -5,7 +5,7 @@
* clocks for AM43XX based boards
* Derived from AM33XX based boards
*
- * Copyright (C) 2013, Texas Instruments, Incorporated - http://www.ti.com/
+ * Copyright (C) 2013, Texas Instruments, Incorporated - https://www.ti.com/
*/
#include <common.h>
diff --git a/arch/arm/mach-omap2/am33xx/ddr.c b/arch/arm/mach-omap2/am33xx/ddr.c
index 5f970d9..61b95c9 100644
--- a/arch/arm/mach-omap2/am33xx/ddr.c
+++ b/arch/arm/mach-omap2/am33xx/ddr.c
@@ -2,7 +2,7 @@
/*
* DDR Configuration for AM33xx devices.
*
- * Copyright (C) 2011 Texas Instruments Incorporated - http://www.ti.com/
+ * Copyright (C) 2011 Texas Instruments Incorporated - https://www.ti.com/
*/
#include <common.h>
diff --git a/arch/arm/mach-omap2/am33xx/emif4.c b/arch/arm/mach-omap2/am33xx/emif4.c
index bf3da43..b29250b 100644
--- a/arch/arm/mach-omap2/am33xx/emif4.c
+++ b/arch/arm/mach-omap2/am33xx/emif4.c
@@ -4,7 +4,7 @@
*
* AM33XX emif4 configuration file
*
- * Copyright (C) 2011, Texas Instruments, Incorporated - http://www.ti.com/
+ * Copyright (C) 2011, Texas Instruments, Incorporated - https://www.ti.com/
*/
#include <common.h>
diff --git a/arch/arm/mach-omap2/am33xx/mux.c b/arch/arm/mach-omap2/am33xx/mux.c
index aad3ec8..4960559 100644
--- a/arch/arm/mach-omap2/am33xx/mux.c
+++ b/arch/arm/mach-omap2/am33xx/mux.c
@@ -1,7 +1,7 @@
/*
* mux.c
*
- * Copyright (C) 2011 Texas Instruments Incorporated - http://www.ti.com/
+ * Copyright (C) 2011 Texas Instruments Incorporated - https://www.ti.com/
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
diff --git a/arch/arm/mach-omap2/am33xx/sys_info.c b/arch/arm/mach-omap2/am33xx/sys_info.c
index 338f6af..390d540 100644
--- a/arch/arm/mach-omap2/am33xx/sys_info.c
+++ b/arch/arm/mach-omap2/am33xx/sys_info.c
@@ -4,7 +4,7 @@
*
* System information functions
*
- * Copyright (C) 2011, Texas Instruments, Incorporated - http://www.ti.com/
+ * Copyright (C) 2011, Texas Instruments, Incorporated - https://www.ti.com/
*
* Derived from Beagle Board and 3430 SDP code by
* Richard Woodruff <r-woodruff2@ti.com>
diff --git a/arch/arm/mach-omap2/boot-common.c b/arch/arm/mach-omap2/boot-common.c
index 5e4d299..57917da 100644
--- a/arch/arm/mach-omap2/boot-common.c
+++ b/arch/arm/mach-omap2/boot-common.c
@@ -4,7 +4,7 @@
*
* Common bootmode functions for omap based boards
*
- * Copyright (C) 2011, Texas Instruments, Incorporated - http://www.ti.com/
+ * Copyright (C) 2011, Texas Instruments, Incorporated - https://www.ti.com/
*/
#include <common.h>
diff --git a/arch/arm/mach-omap2/config.mk b/arch/arm/mach-omap2/config.mk
index 4f0d259..30d8fb1 100644
--- a/arch/arm/mach-omap2/config.mk
+++ b/arch/arm/mach-omap2/config.mk
@@ -1,5 +1,5 @@
#
-# Copyright (C) 2011, Texas Instruments, Incorporated - http://www.ti.com/
+# Copyright (C) 2011, Texas Instruments, Incorporated - https://www.ti.com/
#
# SPDX-License-Identifier: GPL-2.0+
diff --git a/arch/arm/mach-omap2/config_secure.mk b/arch/arm/mach-omap2/config_secure.mk
index f76262b..40db1ae 100644
--- a/arch/arm/mach-omap2/config_secure.mk
+++ b/arch/arm/mach-omap2/config_secure.mk
@@ -1,6 +1,6 @@
# SPDX-License-Identifier: GPL-2.0+
#
-# Copyright (C) 2016, Texas Instruments, Incorporated - http://www.ti.com/
+# Copyright (C) 2016, Texas Instruments, Incorporated - https://www.ti.com/
quiet_cmd_mkomapsecimg = SECURE $@
ifneq ($(TI_SECURE_DEV_PKG),)
ifneq ($(wildcard $(TI_SECURE_DEV_PKG)/scripts/create-boot-image.sh),)
diff --git a/arch/arm/mach-omap2/omap3/Kconfig b/arch/arm/mach-omap2/omap3/Kconfig
index 3e3e7bd..bd524f8 100644
--- a/arch/arm/mach-omap2/omap3/Kconfig
+++ b/arch/arm/mach-omap2/omap3/Kconfig
@@ -152,7 +152,7 @@
default "omap3"
source "board/logicpd/am3517evm/Kconfig"
-source "board/ti/beagle/Kconfig"
+source "board/beagle/beagle/Kconfig"
source "board/timll/devkit8000/Kconfig"
source "board/ti/omap3evm/Kconfig"
source "board/isee/igep00x0/Kconfig"
diff --git a/arch/arm/mach-omap2/omap3/emif4.c b/arch/arm/mach-omap2/omap3/emif4.c
index 491e7c2..7e5a281 100644
--- a/arch/arm/mach-omap2/omap3/emif4.c
+++ b/arch/arm/mach-omap2/omap3/emif4.c
@@ -6,7 +6,7 @@
* Based on mem.c and sdrc.c
*
* Copyright (C) 2010
- * Texas Instruments Incorporated - http://www.ti.com/
+ * Texas Instruments Incorporated - https://www.ti.com/
*/
#include <common.h>
diff --git a/arch/arm/mach-omap2/omap3/sdrc.c b/arch/arm/mach-omap2/omap3/sdrc.c
index 07f534a..5d43e7c 100644
--- a/arch/arm/mach-omap2/omap3/sdrc.c
+++ b/arch/arm/mach-omap2/omap3/sdrc.c
@@ -7,7 +7,7 @@
* generic init function (mem_init).
*
* Copyright (C) 2004-2010
- * Texas Instruments Incorporated - http://www.ti.com/
+ * Texas Instruments Incorporated - https://www.ti.com/
*
* Copyright (C) 2011
* Corscience GmbH & Co. KG - Simon Schwarz <schwarz@corscience.de>
diff --git a/arch/arm/mach-omap2/vc.c b/arch/arm/mach-omap2/vc.c
index b7f7980..054782e 100644
--- a/arch/arm/mach-omap2/vc.c
+++ b/arch/arm/mach-omap2/vc.c
@@ -1,7 +1,7 @@
/*
* Voltage Controller implementation for OMAP
*
- * Copyright (C) 2012 Texas Instruments Incorporated - http://www.ti.com/
+ * Copyright (C) 2012 Texas Instruments Incorporated - https://www.ti.com/
* Nishanth Menon
*
* This program is free software; you can redistribute it and/or modify
diff --git a/arch/arm/mach-rockchip/Kconfig b/arch/arm/mach-rockchip/Kconfig
index a6c69c3..b577a91 100644
--- a/arch/arm/mach-rockchip/Kconfig
+++ b/arch/arm/mach-rockchip/Kconfig
@@ -359,6 +359,8 @@
select BOARD_LATE_INIT
imply ROCKCHIP_COMMON_BOARD
imply OF_LIBFDT_OVERLAY
+ imply ROCKCHIP_OTP
+ imply MISC_INIT_R
imply TPL_DM
imply TPL_LIBCOMMON_SUPPORT
imply TPL_LIBGENERIC_SUPPORT
@@ -401,7 +403,7 @@
config TPL_ROCKCHIP_BACK_TO_BROM
bool "TPL returns to bootrom"
default y
- select ROCKCHIP_BROM_HELPER
+ select ROCKCHIP_BROM_HELPER if !ROCKCHIP_RK3066
select TPL_BOOTROM_SUPPORT
depends on TPL
help
diff --git a/arch/arm/mach-rockchip/rk3066/Kconfig b/arch/arm/mach-rockchip/rk3066/Kconfig
index 95d7fc8..4a79a82 100644
--- a/arch/arm/mach-rockchip/rk3066/Kconfig
+++ b/arch/arm/mach-rockchip/rk3066/Kconfig
@@ -10,6 +10,14 @@
config ROCKCHIP_BOOT_MODE_REG
default 0x20004040
+config ROCKCHIP_BOOT_LR_REG
+ hex
+ default 0x00001058
+
+config ROCKCHIP_BOOT_RETURN_REG
+ hex
+ default 0x00001100
+
config SYS_SOC
default "rk3066"
diff --git a/arch/arm/mach-rockchip/rk3588/Kconfig b/arch/arm/mach-rockchip/rk3588/Kconfig
index 1ff6b7d..e5282dd 100644
--- a/arch/arm/mach-rockchip/rk3588/Kconfig
+++ b/arch/arm/mach-rockchip/rk3588/Kconfig
@@ -125,6 +125,13 @@
USB PD over USB Type-C
Size: 100mm x 72mm (Pico-ITX form factor)
+config TARGET_QUARTZPRO64_RK3588
+ bool "Pine64 QuartzPro64 RK3588 board"
+ select BOARD_LATE_INIT
+ help
+ Pine64 QuartzPro64 is a Rockchip RK3588 based SBC (Single Board
+ Computer) by Pine64.
+
config ROCKCHIP_BOOT_MODE_REG
default 0xfd588080
@@ -139,6 +146,7 @@
source board/edgeble/neural-compute-module-6/Kconfig
source board/friendlyelec/nanopc-t6-rk3588/Kconfig
+source board/pine64/quartzpro64-rk3588/Kconfig
source board/rockchip/evb_rk3588/Kconfig
source board/radxa/rock5a-rk3588s/Kconfig
source board/radxa/rock5b-rk3588/Kconfig
diff --git a/arch/arm/mach-stm32mp/include/mach/stm32.h b/arch/arm/mach-stm32mp/include/mach/stm32.h
index b31e4a5..46d4698 100644
--- a/arch/arm/mach-stm32mp/include/mach/stm32.h
+++ b/arch/arm/mach-stm32mp/include/mach/stm32.h
@@ -46,10 +46,13 @@
#define TAMP_BOOT_MODE_MASK GENMASK(15, 8)
#define TAMP_BOOT_MODE_SHIFT 8
+#define TAMP_BOOT_AUTH_MASK GENMASK(23, 16)
+#define TAMP_BOOT_AUTH_SHIFT 16
#define TAMP_BOOT_DEVICE_MASK GENMASK(7, 4)
#define TAMP_BOOT_INSTANCE_MASK GENMASK(3, 0)
+#define TAMP_BOOT_AUTH_ST_MASK GENMASK(7, 4)
+#define TAMP_BOOT_PARTITION_MASK GENMASK(3, 0)
#define TAMP_BOOT_FORCED_MASK GENMASK(7, 0)
-#define TAMP_BOOT_DEBUG_ON BIT(16)
enum forced_boot_mode {
BOOT_NORMAL = 0x00,
diff --git a/arch/arm/mach-stm32mp/include/mach/sys_proto.h b/arch/arm/mach-stm32mp/include/mach/sys_proto.h
index 7b2df09..83388fd 100644
--- a/arch/arm/mach-stm32mp/include/mach/sys_proto.h
+++ b/arch/arm/mach-stm32mp/include/mach/sys_proto.h
@@ -92,6 +92,9 @@
/* return boot mode */
u32 get_bootmode(void);
+/* return auth status and partition */
+u32 get_bootauth(void);
+
int get_eth_nb(void);
int setup_mac_address(void);
diff --git a/arch/arm/mach-stm32mp/stm32mp1/cpu.c b/arch/arm/mach-stm32mp/stm32mp1/cpu.c
index e07abbe..55574fd 100644
--- a/arch/arm/mach-stm32mp/stm32mp1/cpu.c
+++ b/arch/arm/mach-stm32mp/stm32mp1/cpu.c
@@ -40,6 +40,13 @@
TAMP_BOOT_MODE_SHIFT;
}
+u32 get_bootauth(void)
+{
+ /* read boot auth status and partition from TAMP backup register */
+ return (readl(TAMP_BOOT_CONTEXT) & TAMP_BOOT_AUTH_MASK) >>
+ TAMP_BOOT_AUTH_SHIFT;
+}
+
/*
* weak function overidde: set the DDR/SYSRAM executable before to enable the
* MMU and configure DACR, for early early_enable_caches (SPL or pre-reloc)
@@ -91,10 +98,10 @@
if (CONFIG_IS_ENABLED(SYS_DCACHE_OFF))
return;
- if (!(CONFIG_IS_ENABLED(SYS_ICACHE_OFF) && CONFIG_IS_ENABLED(SYS_DCACHE_OFF))) {
+#if !(CONFIG_IS_ENABLED(SYS_ICACHE_OFF) && CONFIG_IS_ENABLED(SYS_DCACHE_OFF))
gd->arch.tlb_size = PGTABLE_SIZE;
gd->arch.tlb_addr = (unsigned long)&early_tlb;
- }
+#endif
/* enable MMU (default configuration) */
dcache_enable();
@@ -369,10 +376,26 @@
__weak void stm32mp_misc_init(void)
{
+}
+
+static int setup_boot_auth_info(void)
+{
+ char buf[10];
+ u32 bootauth = get_bootauth();
+
+ snprintf(buf, sizeof(buf), "%d", bootauth >> 4);
+ env_set("boot_auth", buf);
+
+ snprintf(buf, sizeof(buf), "%d", bootauth &
+ (u32)TAMP_BOOT_PARTITION_MASK);
+ env_set("boot_part", buf);
+
+ return 0;
}
int arch_misc_init(void)
{
+ setup_boot_auth_info();
setup_boot_mode();
setup_mac_address();
setup_serial_number();
diff --git a/arch/arm/mach-sunxi/Kconfig b/arch/arm/mach-sunxi/Kconfig
index a10e4c0..a4a8d8e 100644
--- a/arch/arm/mach-sunxi/Kconfig
+++ b/arch/arm/mach-sunxi/Kconfig
@@ -85,6 +85,12 @@
help
TPR2 value from vendor DRAM settings.
+config DRAM_SUN50I_H616_TPR6
+ hex "H616 DRAM TPR6 parameter"
+ default 0x3300c080
+ help
+ TPR6 value from vendor DRAM settings.
+
config DRAM_SUN50I_H616_TPR10
hex "H616 DRAM TPR10 parameter"
help
@@ -462,6 +468,9 @@
config SUNXI_DRAM_LPDDR3
bool
+config SUNXI_DRAM_LPDDR4
+ bool
+
choice
prompt "DRAM Type and Timing"
default SUNXI_DRAM_DDR3_1333 if !MACH_SUN8I_V3S
@@ -505,6 +514,14 @@
This option is the LPDDR3 timing used by the stock boot0 by
Allwinner.
+config SUNXI_DRAM_H616_LPDDR4
+ bool "LPDDR4 DRAM chips on the H616 DRAM controller"
+ select SUNXI_DRAM_LPDDR4
+ depends on DRAM_SUN50I_H616
+ help
+ This option is the LPDDR4 timing used by the stock boot0 by
+ Allwinner.
+
config SUNXI_DRAM_H616_DDR3_1333
bool "DDR3-1333 boot0 timings on the H616 DRAM controller"
select SUNXI_DRAM_DDR3
diff --git a/arch/arm/mach-sunxi/dram_sun50i_h616.c b/arch/arm/mach-sunxi/dram_sun50i_h616.c
index 7e580b6..c5c1331 100644
--- a/arch/arm/mach-sunxi/dram_sun50i_h616.c
+++ b/arch/arm/mach-sunxi/dram_sun50i_h616.c
@@ -6,8 +6,8 @@
* unknown. That's why this driver has plenty of magic numbers. Some
* meaning was nevertheless deduced from strings found in boot0 and
* known meaning of some dram parameters.
- * This driver only supports DDR3 memory and omits logic for all
- * other supported types supported by hardware.
+ * This driver supports DDR3, LPDDR3 and LPDDR4 memory. There is no
+ * DDR4 support yet.
*
* (C) Copyright 2020 Jernej Skrabec <jernej.skrabec@siol.net>
*
@@ -238,64 +238,59 @@
0x08, 0x01, 0x0a, 0x0b, 0x0c, 0x0d, 0x0e, 0x0f,
0x10, 0x11, 0x12, 0x13, 0x14, 0x15, 0x16, 0x07,
0x17, 0x19, 0x1a
+#elif defined(CONFIG_SUNXI_DRAM_H616_LPDDR4)
+ 0x02, 0x00, 0x17, 0x05, 0x04, 0x19, 0x06, 0x07,
+ 0x08, 0x09, 0x0a, 0x0b, 0x0c, 0x0d, 0x0e, 0x0f,
+ 0x10, 0x11, 0x12, 0x13, 0x14, 0x15, 0x16, 0x01,
+ 0x18, 0x03, 0x1a
#endif
};
+#define MASK_BYTE(reg, nr) (((reg) >> ((nr) * 8)) & 0x1f)
static void mctl_phy_configure_odt(const struct dram_para *para)
{
- unsigned int val;
+ uint32_t val_lo, val_hi;
- val = para->dx_dri & 0x1f;
- writel_relaxed(val, SUNXI_DRAM_PHY0_BASE + 0x388);
- writel_relaxed(val, SUNXI_DRAM_PHY0_BASE + 0x38c);
-
- val = (para->dx_dri >> 8) & 0x1f;
- writel_relaxed(val, SUNXI_DRAM_PHY0_BASE + 0x3c8);
- writel_relaxed(val, SUNXI_DRAM_PHY0_BASE + 0x3cc);
-
- val = (para->dx_dri >> 16) & 0x1f;
- writel_relaxed(val, SUNXI_DRAM_PHY0_BASE + 0x408);
- writel_relaxed(val, SUNXI_DRAM_PHY0_BASE + 0x40c);
-
- val = (para->dx_dri >> 24) & 0x1f;
- writel_relaxed(val, SUNXI_DRAM_PHY0_BASE + 0x448);
- writel_relaxed(val, SUNXI_DRAM_PHY0_BASE + 0x44c);
-
- val = para->ca_dri & 0x1f;
- writel_relaxed(val, SUNXI_DRAM_PHY0_BASE + 0x340);
- writel_relaxed(val, SUNXI_DRAM_PHY0_BASE + 0x344);
-
- val = (para->ca_dri >> 8) & 0x1f;
- writel_relaxed(val, SUNXI_DRAM_PHY0_BASE + 0x348);
- writel_relaxed(val, SUNXI_DRAM_PHY0_BASE + 0x34c);
-
- val = para->dx_odt & 0x1f;
- if (para->type == SUNXI_DRAM_TYPE_LPDDR3)
- writel_relaxed(0, SUNXI_DRAM_PHY0_BASE + 0x380);
- else
- writel_relaxed(val, SUNXI_DRAM_PHY0_BASE + 0x380);
- writel_relaxed(val, SUNXI_DRAM_PHY0_BASE + 0x384);
+ /*
+ * This part should be applicable to all memory types, but is
+ * usually found in LPDDR4 bootloaders. Therefore, we will leave
+ * only for this type of memory.
+ */
+ if (para->type == SUNXI_DRAM_TYPE_LPDDR4) {
+ clrsetbits_le32(SUNXI_DRAM_PHY0_BASE + 0x390, BIT(5), BIT(4));
+ clrsetbits_le32(SUNXI_DRAM_PHY0_BASE + 0x3d0, BIT(5), BIT(4));
+ clrsetbits_le32(SUNXI_DRAM_PHY0_BASE + 0x410, BIT(5), BIT(4));
+ clrsetbits_le32(SUNXI_DRAM_PHY0_BASE + 0x450, BIT(5), BIT(4));
+ }
- val = (para->dx_odt >> 8) & 0x1f;
- if (para->type == SUNXI_DRAM_TYPE_LPDDR3)
- writel_relaxed(0, SUNXI_DRAM_PHY0_BASE + 0x3c0);
- else
- writel_relaxed(val, SUNXI_DRAM_PHY0_BASE + 0x3c0);
- writel_relaxed(val, SUNXI_DRAM_PHY0_BASE + 0x3c4);
+ val_lo = para->dx_dri;
+ val_hi = (para->type == SUNXI_DRAM_TYPE_LPDDR4) ? 0x04040404 : para->dx_dri;
+ writel_relaxed(MASK_BYTE(val_lo, 0), SUNXI_DRAM_PHY0_BASE + 0x388);
+ writel_relaxed(MASK_BYTE(val_hi, 0), SUNXI_DRAM_PHY0_BASE + 0x38c);
+ writel_relaxed(MASK_BYTE(val_lo, 1), SUNXI_DRAM_PHY0_BASE + 0x3c8);
+ writel_relaxed(MASK_BYTE(val_hi, 1), SUNXI_DRAM_PHY0_BASE + 0x3cc);
+ writel_relaxed(MASK_BYTE(val_lo, 2), SUNXI_DRAM_PHY0_BASE + 0x408);
+ writel_relaxed(MASK_BYTE(val_hi, 2), SUNXI_DRAM_PHY0_BASE + 0x40c);
+ writel_relaxed(MASK_BYTE(val_lo, 3), SUNXI_DRAM_PHY0_BASE + 0x448);
+ writel_relaxed(MASK_BYTE(val_hi, 3), SUNXI_DRAM_PHY0_BASE + 0x44c);
- val = (para->dx_odt >> 16) & 0x1f;
- if (para->type == SUNXI_DRAM_TYPE_LPDDR3)
- writel_relaxed(0, SUNXI_DRAM_PHY0_BASE + 0x400);
- else
- writel_relaxed(val, SUNXI_DRAM_PHY0_BASE + 0x400);
- writel_relaxed(val, SUNXI_DRAM_PHY0_BASE + 0x404);
+ val_lo = para->ca_dri;
+ val_hi = para->ca_dri;
+ writel_relaxed(MASK_BYTE(val_lo, 0), SUNXI_DRAM_PHY0_BASE + 0x340);
+ writel_relaxed(MASK_BYTE(val_hi, 0), SUNXI_DRAM_PHY0_BASE + 0x344);
+ writel_relaxed(MASK_BYTE(val_lo, 1), SUNXI_DRAM_PHY0_BASE + 0x348);
+ writel_relaxed(MASK_BYTE(val_hi, 1), SUNXI_DRAM_PHY0_BASE + 0x34c);
- val = (para->dx_odt >> 24) & 0x1f;
- if (para->type == SUNXI_DRAM_TYPE_LPDDR3)
- writel_relaxed(0, SUNXI_DRAM_PHY0_BASE + 0x440);
- else
- writel_relaxed(val, SUNXI_DRAM_PHY0_BASE + 0x440);
- writel_relaxed(val, SUNXI_DRAM_PHY0_BASE + 0x444);
+ val_lo = (para->type == SUNXI_DRAM_TYPE_LPDDR3) ? 0 : para->dx_odt;
+ val_hi = (para->type == SUNXI_DRAM_TYPE_LPDDR4) ? 0 : para->dx_odt;
+ writel_relaxed(MASK_BYTE(val_lo, 0), SUNXI_DRAM_PHY0_BASE + 0x380);
+ writel_relaxed(MASK_BYTE(val_hi, 0), SUNXI_DRAM_PHY0_BASE + 0x384);
+ writel_relaxed(MASK_BYTE(val_lo, 1), SUNXI_DRAM_PHY0_BASE + 0x3c0);
+ writel_relaxed(MASK_BYTE(val_hi, 1), SUNXI_DRAM_PHY0_BASE + 0x3c4);
+ writel_relaxed(MASK_BYTE(val_lo, 2), SUNXI_DRAM_PHY0_BASE + 0x400);
+ writel_relaxed(MASK_BYTE(val_hi, 2), SUNXI_DRAM_PHY0_BASE + 0x404);
+ writel_relaxed(MASK_BYTE(val_lo, 3), SUNXI_DRAM_PHY0_BASE + 0x440);
+ writel_relaxed(MASK_BYTE(val_hi, 3), SUNXI_DRAM_PHY0_BASE + 0x444);
dmb();
}
@@ -414,12 +409,18 @@
return result;
}
-static bool mctl_phy_read_training(const struct dram_config *config)
+static bool mctl_phy_read_training(const struct dram_para *para,
+ const struct dram_config *config)
{
u32 val1, val2, *ptr1, *ptr2;
bool result = true;
int i;
+ if (para->type == SUNXI_DRAM_TYPE_LPDDR4) {
+ writel(0, SUNXI_DRAM_PHY0_BASE + 0x800);
+ writel(0, SUNXI_DRAM_PHY0_BASE + 0x81c);
+ }
+
clrsetbits_le32(SUNXI_DRAM_PHY0_BASE + 0x198, 3, 2);
clrsetbits_le32(SUNXI_DRAM_PHY0_BASE + 0x804, 0x3f, 0xf);
clrsetbits_le32(SUNXI_DRAM_PHY0_BASE + 0x808, 0x3f, 0xf);
@@ -600,6 +601,8 @@
clrbits_le32(SUNXI_DRAM_PHY0_BASE + 0x60, 1);
setbits_le32(SUNXI_DRAM_PHY0_BASE + 8, 8);
clrbits_le32(SUNXI_DRAM_PHY0_BASE + 0x190, 0x10);
+ if (para->type == SUNXI_DRAM_TYPE_LPDDR4)
+ clrbits_le32(SUNXI_DRAM_PHY0_BASE + 0x4, 0x80);
if (para->tpr10 & BIT(30))
val = para->tpr11 & 0x3f;
@@ -813,8 +816,9 @@
writel(val, SUNXI_DRAM_PHY0_BASE + 0x7e0);
writel(val, SUNXI_DRAM_PHY0_BASE + 0x7f4);
- if (para->type == SUNXI_DRAM_TYPE_DDR3) {
- val = (para->tpr10 >> 7) & 0x1e;
+ val = (para->tpr10 >> 7) & 0x1e;
+ switch (para->type) {
+ case SUNXI_DRAM_TYPE_DDR3:
if (para->tpr2 & 1) {
writel(val, SUNXI_DRAM_PHY0_BASE + 0x794);
if (config->ranks == 2) {
@@ -840,8 +844,8 @@
writel(val, SUNXI_DRAM_PHY0_BASE + 0x7b8);
}
}
- } else if (para->type == SUNXI_DRAM_TYPE_LPDDR3) {
- val = (para->tpr10 >> 7) & 0x1e;
+ break;
+ case SUNXI_DRAM_TYPE_LPDDR3:
if (para->tpr2 & 1) {
writel(val, SUNXI_DRAM_PHY0_BASE + 0x7a0);
if (config->ranks == 2) {
@@ -855,7 +859,18 @@
writel(val, SUNXI_DRAM_PHY0_BASE + 0x7f8);
}
}
- }
+ break;
+ case SUNXI_DRAM_TYPE_LPDDR4:
+ if (para->tpr2 & 1) {
+ writel(val, SUNXI_DRAM_PHY0_BASE + 0x788);
+ } else {
+ writel(val, SUNXI_DRAM_PHY0_BASE + 0x794);
+ };
+ break;
+ case SUNXI_DRAM_TYPE_DDR4:
+ default:
+ panic("This DRAM setup is currently not supported.\n");
+ };
}
static bool mctl_phy_init(const struct dram_para *para,
@@ -868,30 +883,42 @@
u32 val, val2, *ptr, mr0, mr2;
int i;
+ if (para->type == SUNXI_DRAM_TYPE_LPDDR4)
+ clrbits_le32(SUNXI_DRAM_PHY0_BASE + 0x4,0x80);
+
if (config->bus_full_width)
val = 0xf;
else
val = 3;
clrsetbits_le32(SUNXI_DRAM_PHY0_BASE + 0x3c, 0xf, val);
- if (para->tpr2 & 0x100) {
- if (para->type == SUNXI_DRAM_TYPE_DDR3) {
+ switch (para->type) {
+ case SUNXI_DRAM_TYPE_DDR3:
+ if (para->tpr2 & 0x100) {
val = 9;
val2 = 7;
- } else if (para->type == SUNXI_DRAM_TYPE_LPDDR3) {
- // untested setup: use some values for now
- val = 14;
- val2 = 8;
- }
- } else {
- if (para->type == SUNXI_DRAM_TYPE_DDR3) {
+ } else {
val = 13;
val2 = 9;
- } else if (para->type == SUNXI_DRAM_TYPE_LPDDR3) {
+ }
+ break;
+ case SUNXI_DRAM_TYPE_LPDDR3:
+ if (para->tpr2 & 0x100) {
+ val = 12;
+ val2 = 6;
+ } else {
val = 14;
val2 = 8;
}
- }
+ break;
+ case SUNXI_DRAM_TYPE_LPDDR4:
+ val = 20;
+ val2 = 10;
+ break;
+ case SUNXI_DRAM_TYPE_DDR4:
+ default:
+ panic("This DRAM setup is currently not supported.\n");
+ };
writel(val, SUNXI_DRAM_PHY0_BASE + 0x14);
writel(val, SUNXI_DRAM_PHY0_BASE + 0x35c);
@@ -915,19 +942,40 @@
if (para->tpr10 & TPR10_CA_BIT_DELAY)
mctl_phy_ca_bit_delay_compensation(para, config);
- if (para->type == SUNXI_DRAM_TYPE_DDR3)
- val = 0x80;
- else if (para->type == SUNXI_DRAM_TYPE_LPDDR3)
- val = 0xc0;
+ switch (para->type) {
+ case SUNXI_DRAM_TYPE_DDR3:
+ val = para->tpr6 & 0xff;
+ break;
+ case SUNXI_DRAM_TYPE_LPDDR3:
+ val = para->tpr6 >> 8 & 0xff;
+ break;
+ case SUNXI_DRAM_TYPE_LPDDR4:
+ val = para->tpr6 >> 24 & 0xff;
+ break;
+ case SUNXI_DRAM_TYPE_DDR4:
+ default:
+ panic("This DRAM setup is currently not supported.\n");
+ };
+
writel(val, SUNXI_DRAM_PHY0_BASE + 0x3dc);
writel(val, SUNXI_DRAM_PHY0_BASE + 0x45c);
mctl_phy_configure_odt(para);
- if (para->type == SUNXI_DRAM_TYPE_DDR3)
+ switch (para->type) {
+ case SUNXI_DRAM_TYPE_DDR3:
val = 0x0a;
- else if (para->type == SUNXI_DRAM_TYPE_LPDDR3)
+ break;
+ case SUNXI_DRAM_TYPE_LPDDR3:
val = 0x0b;
+ break;
+ case SUNXI_DRAM_TYPE_LPDDR4:
+ val = 0x0d;
+ break;
+ case SUNXI_DRAM_TYPE_DDR4:
+ default:
+ panic("This DRAM setup is currently not supported.\n");
+ };
clrsetbits_le32(SUNXI_DRAM_PHY0_BASE + 4, 0x7, val);
if (para->clk <= 672)
@@ -977,8 +1025,8 @@
mr0 = 0x1f14;
mr2 = 0x20;
}
-
- if (para->type == SUNXI_DRAM_TYPE_DDR3) {
+ switch (para->type) {
+ case SUNXI_DRAM_TYPE_DDR3:
writel(mr0, &mctl_ctl->mrctrl1);
writel(0x80000030, &mctl_ctl->mrctrl0);
mctl_await_completion(&mctl_ctl->mrctrl0, BIT(31), 0);
@@ -994,7 +1042,8 @@
writel(0, &mctl_ctl->mrctrl1);
writel(0x80003030, &mctl_ctl->mrctrl0);
mctl_await_completion(&mctl_ctl->mrctrl0, BIT(31), 0);
- } else if (para->type == SUNXI_DRAM_TYPE_LPDDR3) {
+ break;
+ case SUNXI_DRAM_TYPE_LPDDR3:
writel(mr0, &mctl_ctl->mrctrl1);
writel(0x800000f0, &mctl_ctl->mrctrl0);
mctl_await_completion(&mctl_ctl->mrctrl0, BIT(31), 0);
@@ -1010,7 +1059,48 @@
writel(0x301, &mctl_ctl->mrctrl1);
writel(0x800000f0, &mctl_ctl->mrctrl0);
mctl_await_completion(&mctl_ctl->mrctrl0, BIT(31), 0);
- }
+ break;
+ case SUNXI_DRAM_TYPE_LPDDR4:
+ writel(0x0, &mctl_ctl->mrctrl1);
+ writel(0x80000030, &mctl_ctl->mrctrl0);
+ mctl_await_completion(&mctl_ctl->mrctrl0, BIT(31), 0);
+
+ writel(0x134, &mctl_ctl->mrctrl1);
+ writel(0x80000030, &mctl_ctl->mrctrl0);
+ mctl_await_completion(&mctl_ctl->mrctrl0, BIT(31), 0);
+
+ writel(0x21b, &mctl_ctl->mrctrl1);
+ writel(0x80000030, &mctl_ctl->mrctrl0);
+ mctl_await_completion(&mctl_ctl->mrctrl0, BIT(31), 0);
+
+ writel(0x333, &mctl_ctl->mrctrl1);
+ writel(0x80000030, &mctl_ctl->mrctrl0);
+ mctl_await_completion(&mctl_ctl->mrctrl0, BIT(31), 0);
+
+ writel(0x403, &mctl_ctl->mrctrl1);
+ writel(0x80000030, &mctl_ctl->mrctrl0);
+ mctl_await_completion(&mctl_ctl->mrctrl0, BIT(31), 0);
+
+ writel(0xb04, &mctl_ctl->mrctrl1);
+ writel(0x80000030, &mctl_ctl->mrctrl0);
+ mctl_await_completion(&mctl_ctl->mrctrl0, BIT(31), 0);
+
+ writel(0xc72, &mctl_ctl->mrctrl1);
+ writel(0x80000030, &mctl_ctl->mrctrl0);
+ mctl_await_completion(&mctl_ctl->mrctrl0, BIT(31), 0);
+
+ writel(0xe09, &mctl_ctl->mrctrl1);
+ writel(0x80000030, &mctl_ctl->mrctrl0);
+ mctl_await_completion(&mctl_ctl->mrctrl0, BIT(31), 0);
+
+ writel(0x1624, &mctl_ctl->mrctrl1);
+ writel(0x80000030, &mctl_ctl->mrctrl0);
+ mctl_await_completion(&mctl_ctl->mrctrl0, BIT(31), 0);
+ break;
+ case SUNXI_DRAM_TYPE_DDR4:
+ default:
+ panic("This DRAM setup is currently not supported.\n");
+ };
writel(0, SUNXI_DRAM_PHY0_BASE + 0x54);
@@ -1040,7 +1130,7 @@
if (para->tpr10 & TPR10_READ_TRAINING) {
for (i = 0; i < 5; i++)
- if (mctl_phy_read_training(config))
+ if (mctl_phy_read_training(para, config))
break;
if (i == 5) {
debug("read training failed!\n");
@@ -1079,17 +1169,29 @@
setbits_le32(&mctl_com->unk_0x008, 0xff00);
+ if (para->type == SUNXI_DRAM_TYPE_LPDDR4)
+ writel(1, SUNXI_DRAM_COM_BASE + 0x50);
clrsetbits_le32(&mctl_ctl->sched[0], 0xff00, 0x3000);
writel(0, &mctl_ctl->hwlpctl);
setbits_le32(&mctl_com->unk_0x008, 0xff00);
- reg_val = MSTR_BURST_LENGTH(8) | MSTR_ACTIVE_RANKS(config->ranks);
- if (para->type == SUNXI_DRAM_TYPE_DDR3)
- reg_val |= MSTR_DEVICETYPE_DDR3 | MSTR_2TMODE;
- else if (para->type == SUNXI_DRAM_TYPE_LPDDR3)
- reg_val |= MSTR_DEVICETYPE_LPDDR3;
+ reg_val = MSTR_ACTIVE_RANKS(config->ranks);
+ switch (para->type) {
+ case SUNXI_DRAM_TYPE_DDR3:
+ reg_val |= MSTR_BURST_LENGTH(8) | MSTR_DEVICETYPE_DDR3 | MSTR_2TMODE;
+ break;
+ case SUNXI_DRAM_TYPE_LPDDR3:
+ reg_val |= MSTR_BURST_LENGTH(8) | MSTR_DEVICETYPE_LPDDR3;
+ break;
+ case SUNXI_DRAM_TYPE_LPDDR4:
+ reg_val |= MSTR_BURST_LENGTH(16) | MSTR_DEVICETYPE_LPDDR4;
+ break;
+ case SUNXI_DRAM_TYPE_DDR4:
+ default:
+ panic("This DRAM setup is currently not supported.\n");
+ };
if (config->bus_full_width)
reg_val |= MSTR_BUSWIDTH_FULL;
else
@@ -1101,10 +1203,20 @@
else
writel(0x0201, &mctl_ctl->odtmap);
- if (para->type == SUNXI_DRAM_TYPE_DDR3)
+ switch (para->type) {
+ case SUNXI_DRAM_TYPE_DDR3:
reg_val = 0x06000400;
- else if (para->type == SUNXI_DRAM_TYPE_LPDDR3)
+ break;
+ case SUNXI_DRAM_TYPE_LPDDR3:
reg_val = 0x09020400;
+ break;
+ case SUNXI_DRAM_TYPE_LPDDR4:
+ reg_val = 0x04000400;
+ break;
+ case SUNXI_DRAM_TYPE_DDR4:
+ default:
+ panic("This DRAM setup is currently not supported.\n");
+ };
writel(reg_val, &mctl_ctl->odtcfg);
writel(reg_val, &mctl_ctl->unk_0x2240);
writel(reg_val, &mctl_ctl->unk_0x3240);
@@ -1124,6 +1236,9 @@
setbits_le32(&mctl_ctl->unk_0x3180, BIT(31) | BIT(30));
setbits_le32(&mctl_ctl->unk_0x4180, BIT(31) | BIT(30));
+ if (para->type == SUNXI_DRAM_TYPE_LPDDR4)
+ setbits_le32(&mctl_ctl->dbictl, 0x1);
+
setbits_le32(&mctl_ctl->rfshctl3, BIT(0));
clrbits_le32(&mctl_ctl->dfimisc, BIT(0));
@@ -1246,6 +1361,8 @@
.type = SUNXI_DRAM_TYPE_DDR3,
#elif defined(CONFIG_SUNXI_DRAM_H616_LPDDR3)
.type = SUNXI_DRAM_TYPE_LPDDR3,
+#elif defined(CONFIG_SUNXI_DRAM_H616_LPDDR4)
+ .type = SUNXI_DRAM_TYPE_LPDDR4,
#endif
.dx_odt = CONFIG_DRAM_SUN50I_H616_DX_ODT,
.dx_dri = CONFIG_DRAM_SUN50I_H616_DX_DRI,
@@ -1253,6 +1370,7 @@
.odt_en = CONFIG_DRAM_SUN50I_H616_ODT_EN,
.tpr0 = CONFIG_DRAM_SUN50I_H616_TPR0,
.tpr2 = CONFIG_DRAM_SUN50I_H616_TPR2,
+ .tpr6 = CONFIG_DRAM_SUN50I_H616_TPR6,
.tpr10 = CONFIG_DRAM_SUN50I_H616_TPR10,
.tpr11 = CONFIG_DRAM_SUN50I_H616_TPR11,
.tpr12 = CONFIG_DRAM_SUN50I_H616_TPR12,
diff --git a/arch/arm/mach-sunxi/dram_sun8i_a23.c b/arch/arm/mach-sunxi/dram_sun8i_a23.c
index 3ed97b5..056cb03 100644
--- a/arch/arm/mach-sunxi/dram_sun8i_a23.c
+++ b/arch/arm/mach-sunxi/dram_sun8i_a23.c
@@ -14,7 +14,7 @@
*
* The register-layout of the sunxi_mctl_phy_reg-s looks a lot like the one
* found in the TI Keystone2 documentation:
- * http://www.ti.com/lit/ug/spruhn7a/spruhn7a.pdf
+ * https://www.ti.com/lit/ug/spruhn7a/spruhn7a.pdf
* "Table4-2 DDR3 PHY Registers"
* This may be used as a (possible) reference for future work / cleanups.
*/
diff --git a/arch/arm/mach-sunxi/dram_timings/Makefile b/arch/arm/mach-sunxi/dram_timings/Makefile
index 8bfd994..5f20341 100644
--- a/arch/arm/mach-sunxi/dram_timings/Makefile
+++ b/arch/arm/mach-sunxi/dram_timings/Makefile
@@ -5,3 +5,4 @@
obj-$(CONFIG_SUNXI_DRAM_H6_DDR3_1333) += h6_ddr3_1333.o
obj-$(CONFIG_SUNXI_DRAM_H616_DDR3_1333) += h616_ddr3_1333.o
obj-$(CONFIG_SUNXI_DRAM_H616_LPDDR3) += h616_lpddr3.o
+obj-$(CONFIG_SUNXI_DRAM_H616_LPDDR4) += h616_lpddr4_2133.o
diff --git a/arch/arm/mach-sunxi/dram_timings/h616_lpddr4_2133.c b/arch/arm/mach-sunxi/dram_timings/h616_lpddr4_2133.c
new file mode 100644
index 0000000..c11cb86
--- /dev/null
+++ b/arch/arm/mach-sunxi/dram_timings/h616_lpddr4_2133.c
@@ -0,0 +1,95 @@
+/*
+ * sun50i H616 LPDDR4-2133 timings, as programmed by Allwinner's boot0
+ * for orangepi zero3 with the H618 and LPDDR4 memory.
+ *
+ * (C) Copyright 2023 Mikhail Kalashnikov <iuncuim@gmail.com>
+ * Based on H6 DDR3 timings:
+ * (C) Copyright 2020 Jernej Skrabec <jernej.skrabec@siol.net>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm/arch/dram.h>
+#include <asm/arch/cpu.h>
+
+void mctl_set_timing_params(const struct dram_para *para)
+{
+ struct sunxi_mctl_ctl_reg * const mctl_ctl =
+ (struct sunxi_mctl_ctl_reg *)SUNXI_DRAM_CTL0_BASE;
+
+ u8 tccd = 4;
+ u8 tfaw = ns_to_t(40);
+ u8 trrd = max(ns_to_t(10), 2);
+ u8 trcd = max(ns_to_t(18), 2);
+ u8 trc = ns_to_t(65);
+ u8 txp = max(ns_to_t(8), 2);
+ u8 trtp = max(ns_to_t(8), 4);
+ u8 trp = ns_to_t(21);
+ u8 tras = ns_to_t(42);
+ u16 trefi = ns_to_t(3904) / 32;
+ u16 trfc = ns_to_t(280);
+ u16 txsr = ns_to_t(190);
+
+ u8 tmrw = max(ns_to_t(14), 5);
+ u8 tmrd = tmrw;
+ u8 tmod = 12;
+ u8 tcke = max(ns_to_t(15), 2);
+ u8 tcksrx = max(ns_to_t(2), 2);
+ u8 tcksre = max(ns_to_t(5), 2);
+ u8 tckesr = tcke;
+ u8 trasmax = (trefi * 9) / 32;
+ u8 txs = 4;
+ u8 txsdll = 16;
+ u8 txsabort = 4;
+ u8 txsfast = 4;
+ u8 tcl = 10;
+ u8 tcwl = 5;
+ u8 t_rdata_en = 17;
+ u8 tphy_wrlat = 5;
+
+ u8 twtp = 24;
+ u8 twr2rd = max(trrd, (u8)4) + 14;
+ u8 trd2wr = (ns_to_t(4) + 17) - ns_to_t(1);
+
+ /* set DRAM timing */
+ writel((twtp << 24) | (tfaw << 16) | (trasmax << 8) | tras,
+ &mctl_ctl->dramtmg[0]);
+ writel((txp << 16) | (trtp << 8) | trc, &mctl_ctl->dramtmg[1]);
+ writel((tcwl << 24) | (tcl << 16) | (trd2wr << 8) | twr2rd,
+ &mctl_ctl->dramtmg[2]);
+ writel((tmrw << 20) | (tmrd << 12) | tmod, &mctl_ctl->dramtmg[3]);
+ writel((trcd << 24) | (tccd << 16) | (trrd << 8) | trp,
+ &mctl_ctl->dramtmg[4]);
+ writel((tcksrx << 24) | (tcksre << 16) | (tckesr << 8) | tcke,
+ &mctl_ctl->dramtmg[5]);
+ /* Value suggested by ZynqMP manual and used by libdram */
+ writel((txp + 2) | 0x02020000, &mctl_ctl->dramtmg[6]);
+ writel((txsfast << 24) | (txsabort << 16) | (txsdll << 8) | txs,
+ &mctl_ctl->dramtmg[8]);
+ writel(0x00020208, &mctl_ctl->dramtmg[9]);
+ writel(0xE0C05, &mctl_ctl->dramtmg[10]);
+ writel(0x440C021C, &mctl_ctl->dramtmg[11]);
+ writel(8, &mctl_ctl->dramtmg[12]);
+ writel(0xA100002, &mctl_ctl->dramtmg[13]);
+ writel(txsr, &mctl_ctl->dramtmg[14]);
+
+ clrsetbits_le32(&mctl_ctl->init[0], 0xC0000FFF, 0x3f0);
+ writel(0x01f20000, &mctl_ctl->init[1]);
+ writel(0x00000d05, &mctl_ctl->init[2]);
+ writel(0, &mctl_ctl->dfimisc);
+ writel(0x0034001b, &mctl_ctl->init[3]);
+ writel(0x00330000, &mctl_ctl->init[4]);
+ writel(0x00040072, &mctl_ctl->init[6]);
+ writel(0x00240009, &mctl_ctl->init[7]);
+
+ clrsetbits_le32(&mctl_ctl->rankctl, 0xff0, 0x660);
+
+ /* Configure DFI timing */
+ writel(tphy_wrlat | 0x2000000 | (t_rdata_en << 16) | 0x808000,
+ &mctl_ctl->dfitmg0);
+ writel(0x100202, &mctl_ctl->dfitmg1);
+
+ /* set refresh timing */
+ writel((trefi << 16) | trfc, &mctl_ctl->rfshtmg);
+}
diff --git a/arch/arm/mach-sunxi/pmic_bus.c b/arch/arm/mach-sunxi/pmic_bus.c
index c090840..8e7625f 100644
--- a/arch/arm/mach-sunxi/pmic_bus.c
+++ b/arch/arm/mach-sunxi/pmic_bus.c
@@ -22,6 +22,7 @@
#define AXP209_I2C_ADDR 0x34
#define AXP305_I2C_ADDR 0x36
+#define AXP313_I2C_ADDR 0x36
#define AXP221_CHIP_ADDR 0x68
@@ -34,6 +35,8 @@
return AXP152_I2C_ADDR;
if (IS_ENABLED(CONFIG_AXP305_POWER))
return AXP305_I2C_ADDR;
+ if (IS_ENABLED(CONFIG_AXP313_POWER))
+ return AXP313_I2C_ADDR;
/* Other AXP2xx and AXP8xx variants */
return AXP209_I2C_ADDR;
diff --git a/arch/arm/mach-sunxi/spl_spi_sunxi.c b/arch/arm/mach-sunxi/spl_spi_sunxi.c
index c2410dd..267cb0b 100644
--- a/arch/arm/mach-sunxi/spl_spi_sunxi.c
+++ b/arch/arm/mach-sunxi/spl_spi_sunxi.c
@@ -354,10 +354,7 @@
struct spl_load_info load;
debug("Found FIT image\n");
- load.dev = NULL;
- load.priv = NULL;
- load.filename = NULL;
- load.bl_len = 1;
+ spl_set_bl_len(&load, 1);
load.read = spi_load_read;
ret = spl_load_simple_fit(spl_image, &load,
load_offset, header);
diff --git a/arch/arm/mach-tegra/board2.c b/arch/arm/mach-tegra/board2.c
index cd40587..8ad76d5 100644
--- a/arch/arm/mach-tegra/board2.c
+++ b/arch/arm/mach-tegra/board2.c
@@ -11,6 +11,7 @@
#include <init.h>
#include <log.h>
#include <ns16550.h>
+#include <power/regulator.h>
#include <usb.h>
#include <asm/global_data.h>
#include <asm/io.h>
@@ -185,6 +186,10 @@
/* prepare the WB code to LP0 location */
warmboot_prepare_code(TEGRA_LP0_ADDR, TEGRA_LP0_SIZE);
#endif
+
+ /* Set up boot-on regulators */
+ regulators_enable_boot_on(_DEBUG);
+
return nvidia_board_init();
}
diff --git a/arch/arm/mach-zynqmp/Kconfig b/arch/arm/mach-zynqmp/Kconfig
index 26b80b7..7e7c87d 100644
--- a/arch/arm/mach-zynqmp/Kconfig
+++ b/arch/arm/mach-zynqmp/Kconfig
@@ -100,30 +100,30 @@
config SPL_ZYNQMP_DRAM_BANK1_BASE
depends on SPL_ZYNQMP_DRAM_ECC_INIT
hex "DRAM Bank1 address"
- default 0x00000000
- help
- Start address of DRAM ECC bank1
+ default 0x00000000
+ help
+ Start address of DRAM ECC bank1
config SPL_ZYNQMP_DRAM_BANK1_LEN
depends on SPL_ZYNQMP_DRAM_ECC_INIT
hex "DRAM Bank1 size"
- default 0x80000000
- help
- Size in bytes of the DRAM ECC bank1
+ default 0x80000000
+ help
+ Size in bytes of the DRAM ECC bank1
config SPL_ZYNQMP_DRAM_BANK2_BASE
depends on SPL_ZYNQMP_DRAM_ECC_INIT
hex "DRAM Bank2 address"
- default 0x800000000
- help
- Start address of DRAM ECC bank2
+ default 0x800000000
+ help
+ Start address of DRAM ECC bank2
config SPL_ZYNQMP_DRAM_BANK2_LEN
depends on SPL_ZYNQMP_DRAM_ECC_INIT
hex "DRAM Bank2 size"
- default 0x0
- help
- Size in bytes of the DRAM ECC bank2. A null size takes no action.
+ default 0x0
+ help
+ Size in bytes of the DRAM ECC bank2. A null size takes no action.
config SYS_MALLOC_F_LEN
default 0x600
diff --git a/arch/mips/include/asm/io.h b/arch/mips/include/asm/io.h
index d3ad669..3774aca 100644
--- a/arch/mips/include/asm/io.h
+++ b/arch/mips/include/asm/io.h
@@ -336,6 +336,22 @@
BUILDIO_MEM(w, u16)
BUILDIO_MEM(l, u32)
BUILDIO_MEM(q, u64)
+#define __raw_readb __raw_readb
+#define __raw_readw __raw_readw
+#define __raw_readl __raw_readl
+#define __raw_readq __raw_readq
+#define __raw_writeb __raw_writeb
+#define __raw_writew __raw_writew
+#define __raw_writel __raw_writel
+#define __raw_writeq __raw_writeq
+#define readb readb
+#define readw readw
+#define readl readl
+#define readq readq
+#define writeb writeb
+#define writew writew
+#define writel writel
+#define writeq writeq
#define __BUILD_IOPORT_PFX(bus, bwlq, type) \
__BUILD_IOPORT_SINGLE(bus, bwlq, type, ) \
@@ -405,7 +421,8 @@
} \
} \
\
-static inline void reads##bwlq(volatile void __iomem *mem, void *addr, \
+static inline void reads##bwlq(const volatile void __iomem *mem, \
+ void *addr, \
unsigned int count) \
{ \
volatile type *__addr = addr; \
@@ -448,8 +465,24 @@
BUILDSTRING(b, u8)
BUILDSTRING(w, u16)
BUILDSTRING(l, u32)
+#define readsb readsb
+#define readsw readsw
+#define readsl readsl
+#define writesb writesb
+#define writesw writesw
+#define writesl writesl
+#define outsb outsb
+#define outsw outsw
+#define outsl outsl
+#define insb insb
+#define insw insw
+#define insl insl
#ifdef CONFIG_64BIT
BUILDSTRING(q, u64)
+#define readsq readsq
+#define writesq writesq
+#define insq insq
+#define outsq outsq
#endif
diff --git a/arch/nios2/include/asm/io.h b/arch/nios2/include/asm/io.h
index 817cd72..321e4fd 100644
--- a/arch/nios2/include/asm/io.h
+++ b/arch/nios2/include/asm/io.h
@@ -94,6 +94,9 @@
unsigned long *p = dst;
while (count--) *p++ = inl (port);
}
+#define insb insb
+#define insw insw
+#define insl insl
static inline void outsb (unsigned long port, const void *src, unsigned long count)
{
@@ -111,6 +114,9 @@
const unsigned long *p = src;
while (count--) outl (*p++, port);
}
+#define outsb outsb
+#define outsw outsw
+#define outsl outsl
/*
* Clear and set bits in one shot. These macros can be used to clear and
diff --git a/arch/powerpc/cpu/mpc8xx/cache.c b/arch/powerpc/cpu/mpc8xx/cache.c
index 4155900..525c87f 100644
--- a/arch/powerpc/cpu/mpc8xx/cache.c
+++ b/arch/powerpc/cpu/mpc8xx/cache.c
@@ -4,7 +4,6 @@
* Christophe Leroy, CS Systemes d'Information, christophe.leroy@c-s.fr
*/
-#include <common.h>
#include <cpu_func.h>
#include <asm/processor.h>
#include <asm/ppc.h>
diff --git a/arch/powerpc/cpu/mpc8xx/cpu.c b/arch/powerpc/cpu/mpc8xx/cpu.c
index 56383ce..b9afd31 100644
--- a/arch/powerpc/cpu/mpc8xx/cpu.c
+++ b/arch/powerpc/cpu/mpc8xx/cpu.c
@@ -16,7 +16,6 @@
* Wolfgang Denk <wd@denx.de>
*/
-#include <common.h>
#include <cpu_func.h>
#include <display_options.h>
#include <net.h>
diff --git a/arch/powerpc/cpu/mpc8xx/cpu_init.c b/arch/powerpc/cpu/mpc8xx/cpu_init.c
index feef792..aac4203 100644
--- a/arch/powerpc/cpu/mpc8xx/cpu_init.c
+++ b/arch/powerpc/cpu/mpc8xx/cpu_init.c
@@ -4,7 +4,6 @@
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
*/
-#include <common.h>
#include <init.h>
#include <watchdog.h>
diff --git a/arch/powerpc/cpu/mpc8xx/fdt.c b/arch/powerpc/cpu/mpc8xx/fdt.c
index b4a26ef..b204a3d 100644
--- a/arch/powerpc/cpu/mpc8xx/fdt.c
+++ b/arch/powerpc/cpu/mpc8xx/fdt.c
@@ -5,7 +5,6 @@
* Code copied & edited from Freescale mpc85xx stuff.
*/
-#include <common.h>
#include <time.h>
#include <asm/global_data.h>
#include <linux/libfdt.h>
diff --git a/arch/powerpc/cpu/mpc8xx/immap.c b/arch/powerpc/cpu/mpc8xx/immap.c
index 40793c2..8c85fc1 100644
--- a/arch/powerpc/cpu/mpc8xx/immap.c
+++ b/arch/powerpc/cpu/mpc8xx/immap.c
@@ -8,7 +8,6 @@
* MPC8xx Internal Memory Map Functions
*/
-#include <common.h>
#include <command.h>
#include <asm/global_data.h>
@@ -16,6 +15,7 @@
#include <asm/cpm_8xx.h>
#include <asm/iopin_8xx.h>
#include <asm/io.h>
+#include <asm/ppc.h>
DECLARE_GLOBAL_DATA_PTR;
diff --git a/arch/powerpc/cpu/mpc8xx/interrupts.c b/arch/powerpc/cpu/mpc8xx/interrupts.c
index eef1951..babef07 100644
--- a/arch/powerpc/cpu/mpc8xx/interrupts.c
+++ b/arch/powerpc/cpu/mpc8xx/interrupts.c
@@ -4,7 +4,7 @@
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
*/
-#include <common.h>
+#include <stdio.h>
#include <irq_func.h>
#include <mpc8xx.h>
#include <mpc8xx_irq.h>
diff --git a/arch/powerpc/cpu/mpc8xx/speed.c b/arch/powerpc/cpu/mpc8xx/speed.c
index 1a882a3..baf8138 100644
--- a/arch/powerpc/cpu/mpc8xx/speed.c
+++ b/arch/powerpc/cpu/mpc8xx/speed.c
@@ -4,12 +4,12 @@
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
*/
-#include <common.h>
#include <clock_legacy.h>
#include <mpc8xx.h>
#include <asm/global_data.h>
#include <asm/processor.h>
#include <asm/io.h>
+#include <asm/immap_8xx.h>
DECLARE_GLOBAL_DATA_PTR;
diff --git a/arch/powerpc/cpu/mpc8xx/traps.c b/arch/powerpc/cpu/mpc8xx/traps.c
index 56794b0..5220c56 100644
--- a/arch/powerpc/cpu/mpc8xx/traps.c
+++ b/arch/powerpc/cpu/mpc8xx/traps.c
@@ -15,7 +15,7 @@
* This file handles the architecture-dependent parts of hardware exceptions
*/
-#include <common.h>
+#include <vsprintf.h>
#include <asm/ptrace.h>
#include <command.h>
#include <asm/processor.h>
diff --git a/arch/powerpc/include/asm/io.h b/arch/powerpc/include/asm/io.h
index f63cae0..2412bb9 100644
--- a/arch/powerpc/include/asm/io.h
+++ b/arch/powerpc/include/asm/io.h
@@ -138,26 +138,37 @@
{
return *(volatile unsigned char *)PCI_FIX_ADDR(addr);
}
+#define __raw_readb __raw_readb
+
static inline unsigned short __raw_readw(const volatile void __iomem *addr)
{
return *(volatile unsigned short *)PCI_FIX_ADDR(addr);
}
+#define __raw_readw __raw_readw
+
static inline unsigned int __raw_readl(const volatile void __iomem *addr)
{
return *(volatile unsigned int *)PCI_FIX_ADDR(addr);
}
+#define __raw_readl __raw_readl
+
static inline void __raw_writeb(unsigned char v, volatile void __iomem *addr)
{
*(volatile unsigned char *)PCI_FIX_ADDR(addr) = v;
}
+#define __raw_writeb __raw_writeb
+
static inline void __raw_writew(unsigned short v, volatile void __iomem *addr)
{
*(volatile unsigned short *)PCI_FIX_ADDR(addr) = v;
}
+#define __raw_writew __raw_writew
+
static inline void __raw_writel(unsigned int v, volatile void __iomem *addr)
{
*(volatile unsigned int *)PCI_FIX_ADDR(addr) = v;
}
+#define __raw_writel __raw_writel
/*
* 8, 16 and 32 bit, big and little endian I/O operations, with barrier.
diff --git a/arch/riscv/include/asm/io.h b/arch/riscv/include/asm/io.h
index 4170877..da16585 100644
--- a/arch/riscv/include/asm/io.h
+++ b/arch/riscv/include/asm/io.h
@@ -218,7 +218,8 @@
#define insw(p, d, l) readsw(__io(p), d, l)
#define insl(p, d, l) readsl(__io(p), d, l)
-static inline void readsb(unsigned int *addr, void *data, int bytelen)
+static inline void readsb(const volatile void __iomem *addr, void *data,
+ unsigned int bytelen)
{
unsigned char *ptr;
unsigned char *ptr2;
@@ -233,7 +234,8 @@
}
}
-static inline void readsw(unsigned int *addr, void *data, int wordlen)
+static inline void readsw(const volatile void __iomem *addr, void *data,
+ unsigned int wordlen)
{
unsigned short *ptr;
unsigned short *ptr2;
@@ -248,7 +250,8 @@
}
}
-static inline void readsl(unsigned int *addr, void *data, int longlen)
+static inline void readsl(const volatile void __iomem *addr, void *data,
+ unsigned int longlen)
{
unsigned int *ptr;
unsigned int *ptr2;
@@ -263,7 +266,8 @@
}
}
-static inline void writesb(unsigned int *addr, const void *data, int bytelen)
+static inline void writesb(volatile void __iomem *addr, const void *data,
+ unsigned int bytelen)
{
unsigned char *ptr;
unsigned char *ptr2;
@@ -278,7 +282,8 @@
}
}
-static inline void writesw(unsigned int *addr, const void *data, int wordlen)
+static inline void writesw(volatile void __iomem *addr, const void *data,
+ unsigned int wordlen)
{
unsigned short *ptr;
unsigned short *ptr2;
@@ -293,7 +298,8 @@
}
}
-static inline void writesl(unsigned int *addr, const void *data, int longlen)
+static inline void writesl(volatile void __iomem *addr, const void *data,
+ unsigned int longlen)
{
unsigned int *ptr;
unsigned int *ptr2;
@@ -307,6 +313,14 @@
longlen--;
}
}
+
+#define readsb readsb
+#define readsw readsw
+#define readsl readsl
+#define writesb writesb
+#define writesw writesw
+#define writesl writesl
+
#endif
#define outb_p(val, port) outb((val), (port))
diff --git a/arch/sandbox/cpu/os.c b/arch/sandbox/cpu/os.c
index 85d0d6a..cbae510 100644
--- a/arch/sandbox/cpu/os.c
+++ b/arch/sandbox/cpu/os.c
@@ -219,7 +219,7 @@
{
void *ptr;
off_t size;
- int ifd;
+ int ifd, ret = 0;
ifd = os_open(pathname, os_flags);
if (ifd < 0) {
@@ -229,23 +229,28 @@
size = os_filesize(ifd);
if (size < 0) {
printf("Cannot get file size of '%s'\n", pathname);
- return -EIO;
+ ret = -EIO;
+ goto out;
}
if ((unsigned long long)size > (unsigned long long)SIZE_MAX) {
printf("File '%s' too large to map\n", pathname);
- return -EIO;
+ ret = -EIO;
+ goto out;
}
ptr = mmap(0, size, PROT_READ | PROT_WRITE, MAP_SHARED, ifd, 0);
if (ptr == MAP_FAILED) {
printf("Can't map file '%s': %s\n", pathname, strerror(errno));
- return -EPERM;
+ ret = -EPERM;
+ goto out;
}
*bufp = ptr;
*sizep = size;
- return 0;
+out:
+ os_close(ifd);
+ return ret;
}
int os_unmap(void *buf, int size)
@@ -282,6 +287,23 @@
return 0;
}
+int os_mktemp(char *fname, off_t size)
+{
+ int fd;
+
+ fd = mkostemp(fname, O_CLOEXEC);
+ if (fd < 0)
+ return -errno;
+
+ if (unlink(fname) < 0)
+ return -errno;
+
+ if (ftruncate(fd, size))
+ return -errno;
+
+ return fd;
+}
+
/* Restore tty state when we exit */
static struct termios orig_term;
static bool term_setup;
diff --git a/arch/sandbox/dts/test.dts b/arch/sandbox/dts/test.dts
index 2887f6c..9131eda 100644
--- a/arch/sandbox/dts/test.dts
+++ b/arch/sandbox/dts/test.dts
@@ -1572,6 +1572,7 @@
other-node = "/some-bus/c-test@5";
int-values = <0x1937 72993>;
u-boot,acpi-ssdt-order = <&acpi_test2 &acpi_test1>;
+ stdout-path = "serial0:115200n8";
chosen-test {
compatible = "denx,u-boot-fdt-test";
reg = <9 1>;
@@ -1913,6 +1914,71 @@
compatible = "sandbox,arm-ffa";
};
};
+
+ nand-controller {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ compatible = "sandbox,nand";
+
+ nand@0 {
+ reg = <0>;
+ nand-ecc-mode = "soft";
+ sandbox,id = [00 e3];
+ sandbox,erasesize = <(8 * 1024)>;
+ sandbox,oobsize = <16>;
+ sandbox,pagesize = <512>;
+ sandbox,pages = <0x2000>;
+ sandbox,err-count = <1>;
+ sandbox,err-step-size = <512>;
+ };
+
+ /* MT29F64G08AKABA */
+ nand@1 {
+ reg = <1>;
+ nand-ecc-mode = "soft_bch";
+ sandbox,id = [2C 48 00 26 89 00 00 00];
+ sandbox,onfi = [
+ 4f 4e 46 49 0e 00 5a 00
+ ff 01 00 00 00 00 03 00
+ 00 00 00 00 00 00 00 00
+ 00 00 00 00 00 00 00 00
+ 4d 49 43 52 4f 4e 20 20
+ 20 20 20 20 4d 54 32 39
+ 46 36 34 47 30 38 41 4b
+ 41 42 41 43 35 20 20 20
+ 2c 00 00 00 00 00 00 00
+ 00 00 00 00 00 00 00 00
+ 00 10 00 00 e0 00 00 02
+ 00 00 1c 00 80 00 00 00
+ 00 10 00 00 02 23 01 50
+ 00 01 05 01 00 00 04 00
+ 04 01 1e 00 00 00 00 00
+ 00 00 00 00 00 00 00 00
+ 0e 1f 00 1f 00 f4 01 ac
+ 0d 19 00 c8 00 00 00 00
+ 00 00 00 00 00 00 0a 07
+ 19 00 00 00 00 00 00 00
+ 00 00 00 00 01 00 01 00
+ 00 00 04 10 01 81 04 02
+ 02 01 1e 90 00 00 00 00
+ 00 00 00 00 00 00 00 00
+ 00 00 00 00 00 00 00 00
+ 00 00 00 00 00 00 00 00
+ 00 00 00 00 00 00 00 00
+ 00 00 00 00 00 00 00 00
+ 00 00 00 00 00 00 00 00
+ 00 00 00 00 00 00 00 00
+ 00 00 00 00 00 00 00 00
+ 00 00 00 00 00 03 20 7d
+ ];
+ sandbox,erasesize = <(512 * 1024)>;
+ sandbox,oobsize = <224>;
+ sandbox,pagesize = <4096>;
+ sandbox,pages = <0x200000>;
+ sandbox,err-count = <3>;
+ sandbox,err-step-size = <512>;
+ };
+ };
};
#include "sandbox_pmic.dtsi"
diff --git a/arch/sandbox/include/asm/io.h b/arch/sandbox/include/asm/io.h
index 31ab728..77a02e5 100644
--- a/arch/sandbox/include/asm/io.h
+++ b/arch/sandbox/include/asm/io.h
@@ -28,20 +28,6 @@
void unmap_physmem(const void *vaddr, unsigned long flags);
#define unmap_physmem unmap_physmem
-#include <asm-generic/io.h>
-
-/* For sandbox, we want addresses to point into our RAM buffer */
-static inline void *map_sysmem(phys_addr_t paddr, unsigned long len)
-{
- return map_physmem(paddr, len, MAP_WRBACK);
-}
-
-/* Remove a previous mapping */
-static inline void unmap_sysmem(const void *vaddr)
-{
- unmap_physmem(vaddr, MAP_WRBACK);
-}
-
/* Map from a pointer to our RAM buffer */
phys_addr_t map_to_sysmem(const void *ptr);
@@ -229,5 +215,19 @@
#include <iotrace.h>
#include <asm/types.h>
+#include <asm-generic/io.h>
+
+/* For sandbox, we want addresses to point into our RAM buffer */
+static inline void *map_sysmem(phys_addr_t paddr, unsigned long len)
+{
+ return map_physmem(paddr, len, MAP_WRBACK);
+}
+
+/* Remove a previous mapping */
+static inline void unmap_sysmem(const void *vaddr)
+{
+ unmap_physmem(vaddr, MAP_WRBACK);
+}
+
#endif
diff --git a/arch/sandbox/include/asm/spl.h b/arch/sandbox/include/asm/spl.h
index f349ea1..4fab24c 100644
--- a/arch/sandbox/include/asm/spl.h
+++ b/arch/sandbox/include/asm/spl.h
@@ -15,6 +15,7 @@
BOOT_DEVICE_CPGMAC,
BOOT_DEVICE_NOR,
BOOT_DEVICE_SPI,
+ BOOT_DEVICE_NAND,
};
/**
diff --git a/arch/x86/cpu/coreboot/Kconfig b/arch/x86/cpu/coreboot/Kconfig
index 178f8ad..085302c 100644
--- a/arch/x86/cpu/coreboot/Kconfig
+++ b/arch/x86/cpu/coreboot/Kconfig
@@ -27,5 +27,7 @@
imply X86_TSC_READ_BASE
imply USE_PREBOOT
select BINMAN if X86_64
+ select SYSINFO
+ imply SYSINFO_EXTRA
endif
diff --git a/arch/x86/dts/coreboot.dts b/arch/x86/dts/coreboot.dts
index 0eb31ca..dfce7c2 100644
--- a/arch/x86/dts/coreboot.dts
+++ b/arch/x86/dts/coreboot.dts
@@ -45,4 +45,8 @@
bootph-some-ram;
compatible = "coreboot-fb";
};
+
+ sysinfo {
+ compatible = "coreboot,sysinfo";
+ };
};
diff --git a/arch/x86/include/asm/io.h b/arch/x86/include/asm/io.h
index 83dc097..5efb2e1 100644
--- a/arch/x86/include/asm/io.h
+++ b/arch/x86/include/asm/io.h
@@ -202,10 +202,16 @@
__INS(b)
__INS(w)
__INS(l)
+#define insb insb
+#define insw insw
+#define insl insl
__OUTS(b)
__OUTS(w)
__OUTS(l)
+#define outsb outsb
+#define outsw outsw
+#define outsl outsl
/* IO space accessors */
#define clrio(type, addr, clear) \
diff --git a/arch/xtensa/include/asm/io.h b/arch/xtensa/include/asm/io.h
index 76a646e..87ad9fa 100644
--- a/arch/xtensa/include/asm/io.h
+++ b/arch/xtensa/include/asm/io.h
@@ -76,6 +76,12 @@
void outsb(unsigned long port, const void *src, unsigned long count);
void outsw(unsigned long port, const void *src, unsigned long count);
void outsl(unsigned long port, const void *src, unsigned long count);
+#define insb insb
+#define insw insw
+#define insl insl
+#define outsb outsb
+#define outsw outsw
+#define outsl outsl
#define IO_SPACE_LIMIT ~0
diff --git a/board/CZ.NIC/turris_mox/turris_mox.c b/board/CZ.NIC/turris_mox/turris_mox.c
index 63b8699..3489bdd 100644
--- a/board/CZ.NIC/turris_mox/turris_mox.c
+++ b/board/CZ.NIC/turris_mox/turris_mox.c
@@ -562,7 +562,7 @@
}
}
-int show_board_info(void)
+int checkboard(void)
{
int i, ret, board_version, ram_size, is_sd;
const char *pub_key, *model;
diff --git a/board/CZ.NIC/turris_omnia/turris_omnia.c b/board/CZ.NIC/turris_omnia/turris_omnia.c
index 19c5043..adeb69a 100644
--- a/board/CZ.NIC/turris_omnia/turris_omnia.c
+++ b/board/CZ.NIC/turris_omnia/turris_omnia.c
@@ -962,7 +962,7 @@
return 0;
}
-int show_board_info(void)
+int checkboard(void)
{
char serial[17];
int err;
diff --git a/board/asus/grouper/Kconfig b/board/asus/grouper/Kconfig
index 47d9bae..f935cce 100644
--- a/board/asus/grouper/Kconfig
+++ b/board/asus/grouper/Kconfig
@@ -9,12 +9,4 @@
config SYS_CONFIG_NAME
default "grouper"
-config GROUPER_TPS65911
- bool "Enable support TI TPS65911 PMIC"
- select CMD_POWEROFF
-
-config GROUPER_MAX77663
- bool "Enable support MAXIM MAX77663 PMIC"
- select CMD_POWEROFF
-
endif
diff --git a/board/asus/grouper/Makefile b/board/asus/grouper/Makefile
index e4a477a..d041cf8 100644
--- a/board/asus/grouper/Makefile
+++ b/board/asus/grouper/Makefile
@@ -7,8 +7,8 @@
# Svyatoslav Ryhel <clamor95@gmail.com>
ifdef CONFIG_SPL_BUILD
-obj-$(CONFIG_GROUPER_MAX77663) += grouper-spl-max.o
-obj-$(CONFIG_GROUPER_TPS65911) += grouper-spl-ti.o
+obj-$(CONFIG_DM_PMIC_MAX77663) += grouper-spl-max.o
+obj-$(CONFIG_DM_PMIC_TPS65910) += grouper-spl-ti.o
endif
obj-y += grouper.o
diff --git a/board/asus/grouper/configs/grouper_E1565.config b/board/asus/grouper/configs/grouper_E1565.config
index 4d8d526..265295c 100644
--- a/board/asus/grouper/configs/grouper_E1565.config
+++ b/board/asus/grouper/configs/grouper_E1565.config
@@ -1,2 +1,6 @@
CONFIG_DEFAULT_DEVICE_TREE="tegra30-asus-nexus7-grouper-E1565"
-CONFIG_GROUPER_MAX77663=y
+CONFIG_CMD_POWEROFF=y
+# CONFIG_MAX77663_GPIO is not set
+CONFIG_DM_PMIC_MAX77663=y
+CONFIG_DM_REGULATOR_MAX77663=y
+CONFIG_SYSRESET_MAX77663=y
diff --git a/board/asus/grouper/configs/grouper_PM269.config b/board/asus/grouper/configs/grouper_PM269.config
index fc768b2..a7ee358 100644
--- a/board/asus/grouper/configs/grouper_PM269.config
+++ b/board/asus/grouper/configs/grouper_PM269.config
@@ -1,2 +1,6 @@
CONFIG_DEFAULT_DEVICE_TREE="tegra30-asus-nexus7-grouper-PM269"
-CONFIG_GROUPER_TPS65911=y
+CONFIG_CMD_POWEROFF=y
+CONFIG_DM_PMIC_TPS65910=y
+# CONFIG_DM_REGULATOR_TPS65910 is not set
+CONFIG_DM_REGULATOR_TPS65911=y
+CONFIG_SYSRESET_TPS65910=y
diff --git a/board/asus/grouper/configs/tilapia.config b/board/asus/grouper/configs/tilapia.config
index 1fb0633..d461b47 100644
--- a/board/asus/grouper/configs/tilapia.config
+++ b/board/asus/grouper/configs/tilapia.config
@@ -1,3 +1,7 @@
CONFIG_DEFAULT_DEVICE_TREE="tegra30-asus-nexus7-tilapia-E1565"
-CONFIG_GROUPER_MAX77663=y
CONFIG_SYS_PROMPT="Tegra30 (Tilapia) # "
+CONFIG_CMD_POWEROFF=y
+# CONFIG_MAX77663_GPIO is not set
+CONFIG_DM_PMIC_MAX77663=y
+CONFIG_DM_REGULATOR_MAX77663=y
+CONFIG_SYSRESET_MAX77663=y
diff --git a/board/asus/grouper/grouper-spl-max.c b/board/asus/grouper/grouper-spl-max.c
index 8443837..3e58bf9 100644
--- a/board/asus/grouper/grouper-spl-max.c
+++ b/board/asus/grouper/grouper-spl-max.c
@@ -9,7 +9,7 @@
* Svyatoslav Ryhel <clamor95@gmail.com>
*/
-#include <common.h>
+#include <asm/arch/tegra.h>
#include <asm/arch-tegra/tegra_i2c.h>
#include <linux/delay.h>
diff --git a/board/asus/grouper/grouper-spl-ti.c b/board/asus/grouper/grouper-spl-ti.c
index e5b78f0..1dcce80 100644
--- a/board/asus/grouper/grouper-spl-ti.c
+++ b/board/asus/grouper/grouper-spl-ti.c
@@ -9,7 +9,7 @@
* Svyatoslav Ryhel <clamor95@gmail.com>
*/
-#include <common.h>
+#include <asm/arch/tegra.h>
#include <asm/arch-tegra/tegra_i2c.h>
#include <linux/delay.h>
diff --git a/board/asus/grouper/grouper.c b/board/asus/grouper/grouper.c
index 5398ec8..dc1d110 100644
--- a/board/asus/grouper/grouper.c
+++ b/board/asus/grouper/grouper.c
@@ -7,105 +7,12 @@
* Svyatoslav Ryhel <clamor95@gmail.com>
*/
-#include <common.h>
#include <dm.h>
#include <fdt_support.h>
-#include <i2c.h>
-#include <log.h>
#include <asm/arch/pinmux.h>
#include <asm/arch/gp_padctrl.h>
-#include <asm/arch/gpio.h>
-#include <asm/gpio.h>
-#include <linux/delay.h>
-#include "pinmux-config-grouper.h"
-
-#define TPS65911_I2C_ADDRESS 0x2D
-
-#define TPS65911_REG_LDO1 0x30
-#define TPS65911_REG_DEVCTRL 0x3F
-#define DEVCTRL_PWR_OFF_MASK BIT(7)
-#define DEVCTRL_DEV_ON_MASK BIT(2)
-#define DEVCTRL_DEV_OFF_MASK BIT(0)
-
-#define MAX77663_I2C_ADDRESS 0x3C
-
-#define MAX77663_REG_SD2 0x18
-#define MAX77663_REG_LDO3 0x29
-#define MAX77663_REG_ONOFF_CFG1 0x41
-#define ONOFF_PWR_OFF BIT(1)
-
-#ifdef CONFIG_CMD_POWEROFF
-#ifdef CONFIG_GROUPER_TPS65911
-int do_poweroff(struct cmd_tbl *cmdtp,
- int flag, int argc, char *const argv[])
-{
- struct udevice *dev;
- uchar data_buffer[1];
- int ret;
-
- ret = i2c_get_chip_for_busnum(0, TPS65911_I2C_ADDRESS, 1, &dev);
- if (ret) {
- log_debug("cannot find PMIC I2C chip\n");
- return 0;
- }
-
- ret = dm_i2c_read(dev, TPS65911_REG_DEVCTRL, data_buffer, 1);
- if (ret)
- return ret;
-
- data_buffer[0] |= DEVCTRL_PWR_OFF_MASK;
-
- ret = dm_i2c_write(dev, TPS65911_REG_DEVCTRL, data_buffer, 1);
- if (ret)
- return ret;
-
- data_buffer[0] |= DEVCTRL_DEV_OFF_MASK;
- data_buffer[0] &= ~DEVCTRL_DEV_ON_MASK;
-
- ret = dm_i2c_write(dev, TPS65911_REG_DEVCTRL, data_buffer, 1);
- if (ret)
- return ret;
-
- // wait some time and then print error
- mdelay(5000);
-
- printf("Failed to power off!!!\n");
- return 1;
-}
-#endif /* CONFIG_GROUPER_TPS65911 */
-
-#ifdef CONFIG_GROUPER_MAX77663
-int do_poweroff(struct cmd_tbl *cmdtp,
- int flag, int argc, char *const argv[])
-{
- struct udevice *dev;
- uchar data_buffer[1];
- int ret;
-
- ret = i2c_get_chip_for_busnum(0, MAX77663_I2C_ADDRESS, 1, &dev);
- if (ret) {
- log_debug("cannot find PMIC I2C chip\n");
- return 0;
- }
-
- ret = dm_i2c_read(dev, MAX77663_REG_ONOFF_CFG1, data_buffer, 1);
- if (ret)
- return ret;
-
- data_buffer[0] |= ONOFF_PWR_OFF;
- ret = dm_i2c_write(dev, MAX77663_REG_ONOFF_CFG1, data_buffer, 1);
- if (ret)
- return ret;
-
- // wait some time and then print error
- mdelay(5000);
-
- printf("Failed to power off!!!\n");
- return 1;
-}
-#endif /* CONFIG_GROUPER_MAX77663 */
-#endif /* CONFIG_CMD_POWEROFF */
+#include "pinmux-config-grouper.h"
/*
* Routine: pinmux_init
@@ -119,64 +26,6 @@
pinmux_config_drvgrp_table(grouper_padctrl,
ARRAY_SIZE(grouper_padctrl));
}
-
-#ifdef CONFIG_MMC_SDHCI_TEGRA
-static void __maybe_unused tps65911_voltage_init(void)
-{
- struct udevice *dev;
- int ret;
-
- ret = i2c_get_chip_for_busnum(0, TPS65911_I2C_ADDRESS, 1, &dev);
- if (ret) {
- log_debug("cannot find PMIC I2C chip\n");
- return;
- }
-
- /* TPS659110: LDO1_REG = 3.3v, ACTIVE to SDMMC4 */
- ret = dm_i2c_reg_write(dev, TPS65911_REG_LDO1, 0xC9);
- if (ret)
- log_debug("vcore_emmc set failed: %d\n", ret);
-}
-
-static void __maybe_unused max77663_voltage_init(void)
-{
- struct udevice *dev;
- int ret;
-
- ret = i2c_get_chip_for_busnum(0, MAX77663_I2C_ADDRESS, 1, &dev);
- if (ret) {
- log_debug("cannot find PMIC I2C chip\n");
- return;
- }
-
- /* 0x60 for 1.8v, bit7:0 = voltage */
- ret = dm_i2c_reg_write(dev, MAX77663_REG_SD2, 0x60);
- if (ret)
- log_debug("vdd_1v8_vio set failed: %d\n", ret);
-
- /* 0xEC for 3.00v, enabled: bit7:6 = 11 = enable, bit5:0 = voltage */
- ret = dm_i2c_reg_write(dev, MAX77663_REG_LDO3, 0xEC);
- if (ret)
- log_debug("vcore_emmc set failed: %d\n", ret);
-}
-
-/*
- * Routine: pin_mux_mmc
- * Description: setup the MMC muxes, power rails, etc.
- */
-void pin_mux_mmc(void)
-{
-#ifdef CONFIG_GROUPER_MAX77663
- /* Bring up eMMC power on MAX PMIC */
- max77663_voltage_init();
-#endif
-
-#ifdef CONFIG_GROUPER_TPS65911
- /* Bring up eMMC power on TI PMIC */
- tps65911_voltage_init();
-#endif
-}
-#endif /* MMC */
#if defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP)
int ft_board_setup(void *blob, struct bd_info *bd)
diff --git a/board/asus/transformer-t30/Kconfig b/board/asus/transformer-t30/Kconfig
index accc999..915436b 100644
--- a/board/asus/transformer-t30/Kconfig
+++ b/board/asus/transformer-t30/Kconfig
@@ -9,14 +9,4 @@
config SYS_CONFIG_NAME
default "transformer-t30"
-config TRANSFORMER_SPI_BOOT
- bool "Enable support for SPI based flash"
- select TEGRA20_SLINK
- select DM_SPI_FLASH
- select SPI_FLASH_WINBOND
- help
- Tegra 3 based Transformers with Windows RT have core
- boot sequence (BCT and EBT) on separate SPI FLASH
- memory with 4MB size.
-
endif
diff --git a/board/asus/transformer-t30/configs/tf600t.config b/board/asus/transformer-t30/configs/tf600t.config
index 18ab4fb..e40d0fd 100644
--- a/board/asus/transformer-t30/configs/tf600t.config
+++ b/board/asus/transformer-t30/configs/tf600t.config
@@ -1,4 +1,4 @@
CONFIG_DEFAULT_DEVICE_TREE="tegra30-asus-tf600t"
-CONFIG_TRANSFORMER_SPI_BOOT=y
CONFIG_BOOTCOMMAND="setenv gpio_button 222; if run check_button; then poweroff; fi; setenv gpio_button 132; if run check_button; then echo Starting SPI flash update ...; run update_spi; fi; run bootcmd_usb0; run bootcmd_mmc1; run bootcmd_mmc0; poweroff;"
+CONFIG_SPI_FLASH_WINBOND=y
CONFIG_USB_GADGET_PRODUCT_NUM=0x4d00
diff --git a/board/asus/transformer-t30/transformer-t30-spl.c b/board/asus/transformer-t30/transformer-t30-spl.c
index 89819b2..952e2c8 100644
--- a/board/asus/transformer-t30/transformer-t30-spl.c
+++ b/board/asus/transformer-t30/transformer-t30-spl.c
@@ -9,7 +9,7 @@
* Svyatoslav Ryhel <clamor95@gmail.com>
*/
-#include <common.h>
+#include <asm/arch/tegra.h>
#include <asm/arch-tegra/tegra_i2c.h>
#include <linux/delay.h>
diff --git a/board/asus/transformer-t30/transformer-t30.c b/board/asus/transformer-t30/transformer-t30.c
index ba795a8..7cac6fd 100644
--- a/board/asus/transformer-t30/transformer-t30.c
+++ b/board/asus/transformer-t30/transformer-t30.c
@@ -9,70 +9,12 @@
/* T30 Transformers derive from Cardhu board */
-#include <common.h>
#include <dm.h>
#include <fdt_support.h>
-#include <i2c.h>
-#include <log.h>
#include <asm/arch/pinmux.h>
#include <asm/arch/gp_padctrl.h>
-#include <asm/arch/gpio.h>
-#include <asm/gpio.h>
-#include <linux/delay.h>
-#include "pinmux-config-transformer.h"
-
-#define TPS65911_I2C_ADDRESS 0x2D
-
-#define TPS65911_VDD1 0x21
-#define TPS65911_VDD1_OP 0x22
-#define TPS65911_LDO1 0x30
-#define TPS65911_LDO2 0x31
-#define TPS65911_LDO3 0x37
-#define TPS65911_LDO5 0x32
-#define TPS65911_LDO6 0x35
-
-#define TPS65911_DEVCTRL 0x3F
-#define DEVCTRL_PWR_OFF_MASK BIT(7)
-#define DEVCTRL_DEV_ON_MASK BIT(2)
-#define DEVCTRL_DEV_OFF_MASK BIT(0)
-
-#ifdef CONFIG_CMD_POWEROFF
-int do_poweroff(struct cmd_tbl *cmdtp, int flag,
- int argc, char *const argv[])
-{
- struct udevice *dev;
- uchar data_buffer[1];
- int ret;
-
- ret = i2c_get_chip_for_busnum(0, TPS65911_I2C_ADDRESS, 1, &dev);
- if (ret) {
- log_debug("cannot find PMIC I2C chip\n");
- return 0;
- }
- ret = dm_i2c_read(dev, TPS65911_DEVCTRL, data_buffer, 1);
- if (ret)
- return ret;
-
- data_buffer[0] |= DEVCTRL_PWR_OFF_MASK;
-
- ret = dm_i2c_write(dev, TPS65911_DEVCTRL, data_buffer, 1);
- if (ret)
- return ret;
-
- data_buffer[0] |= DEVCTRL_DEV_OFF_MASK;
- data_buffer[0] &= ~DEVCTRL_DEV_ON_MASK;
-
- ret = dm_i2c_write(dev, TPS65911_DEVCTRL, data_buffer, 1);
- if (ret)
- return ret;
-
- // wait some time and then print error
- mdelay(5000);
- printf("Failed to power off!!!\n");
- return 1;
-}
-#endif
+#include "pinmux-config-transformer.h"
/*
* Routine: pinmux_init
@@ -91,66 +33,6 @@
ARRAY_SIZE(tf700t_mipi_pinmux));
}
}
-
-#ifdef CONFIG_MMC_SDHCI_TEGRA
-static void tps65911_voltage_init(void)
-{
- struct udevice *dev;
- int ret;
-
- ret = i2c_get_chip_for_busnum(0, TPS65911_I2C_ADDRESS, 1, &dev);
- if (ret) {
- log_debug("cannot find PMIC I2C chip\n");
- return;
- }
-
- /* TPS659110: LDO1_REG = 3.3v, ACTIVE to SDMMC4 */
- ret = dm_i2c_reg_write(dev, TPS65911_LDO1, 0xc9);
- if (ret)
- log_debug("vcore_emmc set failed: %d\n", ret);
-
- if (of_machine_is_compatible("asus,tf600t")) {
- /* TPS659110: VDD1_REG = 1.2v, ACTIVE to backlight */
- ret = dm_i2c_reg_write(dev, TPS65911_VDD1_OP, 0x33);
- if (ret)
- log_debug("vdd_bl set failed: %d\n", ret);
-
- ret = dm_i2c_reg_write(dev, TPS65911_VDD1, 0x0d);
- if (ret)
- log_debug("vdd_bl enable failed: %d\n", ret);
-
- /* TPS659110: LDO5_REG = 3.3v, ACTIVE to SDMMC1 VIO */
- ret = dm_i2c_reg_write(dev, TPS65911_LDO5, 0x65);
- if (ret)
- log_debug("vdd_usd set failed: %d\n", ret);
-
- /* TPS659110: LDO6_REG = 1.2v, ACTIVE to MIPI */
- ret = dm_i2c_reg_write(dev, TPS65911_LDO6, 0x11);
- if (ret)
- log_debug("vdd_mipi set failed: %d\n", ret);
- } else {
- /* TPS659110: LDO2_REG = 3.1v, ACTIVE to SDMMC1 */
- ret = dm_i2c_reg_write(dev, TPS65911_LDO2, 0xb9);
- if (ret)
- log_debug("vdd_usd set failed: %d\n", ret);
-
- /* TPS659110: LDO3_REG = 3.1v, ACTIVE to SDMMC1 VIO */
- ret = dm_i2c_reg_write(dev, TPS65911_LDO3, 0x5d);
- if (ret)
- log_debug("vddio_usd set failed: %d\n", ret);
- }
-}
-
-/*
- * Routine: pin_mux_mmc
- * Description: setup the MMC muxes, power rails, etc.
- */
-void pin_mux_mmc(void)
-{
- /* Bring up uSD and eMMC power */
- tps65911_voltage_init();
-}
-#endif /* MMC */
#if defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP)
int ft_board_setup(void *blob, struct bd_info *bd)
diff --git a/board/ti/beagle/Kconfig b/board/beagle/beagle/Kconfig
similarity index 87%
rename from board/ti/beagle/Kconfig
rename to board/beagle/beagle/Kconfig
index c2eff9e..eade599 100644
--- a/board/ti/beagle/Kconfig
+++ b/board/beagle/beagle/Kconfig
@@ -4,7 +4,7 @@
default "beagle"
config SYS_VENDOR
- default "ti"
+ default "beagle"
config SYS_CONFIG_NAME
default "omap3_beagle"
diff --git a/board/ti/beagle/MAINTAINERS b/board/beagle/beagle/MAINTAINERS
similarity index 84%
rename from board/ti/beagle/MAINTAINERS
rename to board/beagle/beagle/MAINTAINERS
index c1d81d4..c7fa87a 100644
--- a/board/ti/beagle/MAINTAINERS
+++ b/board/beagle/beagle/MAINTAINERS
@@ -1,6 +1,6 @@
BEAGLE BOARD
M: Tom Rini <trini@konsulko.com>
S: Maintained
-F: board/ti/beagle/
+F: board/beagle/beagle/
F: include/configs/omap3_beagle.h
F: configs/omap3_beagle_defconfig
diff --git a/board/ti/beagle/Makefile b/board/beagle/beagle/Makefile
similarity index 100%
rename from board/ti/beagle/Makefile
rename to board/beagle/beagle/Makefile
diff --git a/board/ti/beagle/beagle.c b/board/beagle/beagle/beagle.c
similarity index 100%
rename from board/ti/beagle/beagle.c
rename to board/beagle/beagle/beagle.c
diff --git a/board/ti/beagle/beagle.h b/board/beagle/beagle/beagle.h
similarity index 100%
rename from board/ti/beagle/beagle.h
rename to board/beagle/beagle/beagle.h
diff --git a/board/ti/beagle/led.c b/board/beagle/beagle/led.c
similarity index 100%
rename from board/ti/beagle/led.c
rename to board/beagle/beagle/led.c
diff --git a/board/beagle/beagleboneai64/Kconfig b/board/beagle/beagleboneai64/Kconfig
new file mode 100644
index 0000000..7cfccf9
--- /dev/null
+++ b/board/beagle/beagleboneai64/Kconfig
@@ -0,0 +1,59 @@
+# SPDX-License-Identifier: GPL-2.0+
+#
+# Copyright (C) 2022-2023 Texas Instruments Incorporated - https://www.ti.com/
+# Copyright (C) 2022-2023 Jason Kridner, BeagleBoard.org Foundation
+# Copyright (C) 2022-2023 Robert Nelson, BeagleBoard.org Foundation
+#
+
+choice
+ prompt "BeagleBoard.org J721E/TDA4VM based BeagleBone AI-64 board"
+ optional
+
+config TARGET_J721E_A72_BEAGLEBONEAI64
+ bool "BeagleBoard.org J721E BeagleBone AI-64 running on A72"
+ select ARM64
+ select SYS_DISABLE_DCACHE_OPS
+ select BINMAN
+
+config TARGET_J721E_R5_BEAGLEBONEAI64
+ bool "BeagleBoard.org J721E BeagleBone AI-64 running on R5"
+ select CPU_V7R
+ select SYS_THUMB_BUILD
+ select K3_LOAD_SYSFW
+ select RAM
+ select SPL_RAM
+ select K3_DDRSS
+ select BINMAN
+ imply SYS_K3_SPL_ATF
+
+endchoice
+
+if TARGET_J721E_A72_BEAGLEBONEAI64
+
+config SYS_BOARD
+ default "beagleboneai64"
+
+config SYS_VENDOR
+ default "beagle"
+
+config SYS_CONFIG_NAME
+ default "j721e_evm"
+
+source "board/ti/common/Kconfig"
+
+endif
+
+if TARGET_J721E_R5_BEAGLEBONEAI64
+
+config SYS_BOARD
+ default "beagleboneai64"
+
+config SYS_VENDOR
+ default "beagle"
+
+config SYS_CONFIG_NAME
+ default "j721e_evm"
+
+source "board/ti/common/Kconfig"
+
+endif
diff --git a/board/beagle/beagleboneai64/MAINTAINERS b/board/beagle/beagleboneai64/MAINTAINERS
new file mode 100644
index 0000000..5866dcd
--- /dev/null
+++ b/board/beagle/beagleboneai64/MAINTAINERS
@@ -0,0 +1,6 @@
+BEAGLEBONE-AI64 BOARD
+M: Nishanth Menon <nm@ti.com>
+M: Robert Nelson <robertcnelson@gmail.com>
+M: Tom Rini <trini@konsulko.com>
+S: Maintained
+N: beagleboneai64
diff --git a/board/beagle/beagleboneai64/Makefile b/board/beagle/beagleboneai64/Makefile
new file mode 100644
index 0000000..f2a2526
--- /dev/null
+++ b/board/beagle/beagleboneai64/Makefile
@@ -0,0 +1,10 @@
+# SPDX-License-Identifier: GPL-2.0+
+#
+# https://beagleboard.org/ai-64
+#
+# Copyright (C) 2022-2023 Texas Instruments Incorporated - https://www.ti.com/
+# Copyright (C) 2022-2023 Jason Kridner, BeagleBoard.org Foundation
+# Copyright (C) 2022-2023 Robert Nelson, BeagleBoard.org Foundation
+#
+
+obj-y += beagleboneai64.o
diff --git a/board/beagle/beagleboneai64/beagleboneai64.c b/board/beagle/beagleboneai64/beagleboneai64.c
new file mode 100644
index 0000000..c8c1c78
--- /dev/null
+++ b/board/beagle/beagleboneai64/beagleboneai64.c
@@ -0,0 +1,30 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * https://beagleboard.org/ai-64
+ *
+ * Copyright (C) 2022-2023 Texas Instruments Incorporated - https://www.ti.com/
+ * Copyright (C) 2022-2023 Jason Kridner, BeagleBoard.org Foundation
+ * Copyright (C) 2022-2023 Robert Nelson, BeagleBoard.org Foundation
+ */
+
+#include <cpu_func.h>
+#include <env.h>
+#include <fdt_support.h>
+#include <spl.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+int board_init(void)
+{
+ return 0;
+}
+
+int dram_init(void)
+{
+ return fdtdec_setup_mem_size_base();
+}
+
+int dram_init_banksize(void)
+{
+ return fdtdec_setup_memory_banksize();
+}
diff --git a/board/ti/am62x/beagleplay.env b/board/beagle/beagleboneai64/beagleboneai64.env
similarity index 100%
copy from board/ti/am62x/beagleplay.env
copy to board/beagle/beagleboneai64/beagleboneai64.env
diff --git a/board/beagle/beagleboneai64/board-cfg.yaml b/board/beagle/beagleboneai64/board-cfg.yaml
new file mode 100644
index 0000000..1375dca
--- /dev/null
+++ b/board/beagle/beagleboneai64/board-cfg.yaml
@@ -0,0 +1,36 @@
+# SPDX-License-Identifier: GPL-2.0+
+# Copyright (C) 2022-2023 Texas Instruments Incorporated - https://www.ti.com/
+#
+# Board configuration for J721E
+#
+
+---
+
+board-cfg:
+ rev:
+ boardcfg_abi_maj: 0x0
+ boardcfg_abi_min: 0x1
+ control:
+ subhdr:
+ magic: 0xC1D3
+ size: 7
+ main_isolation_enable: 0x5A
+ main_isolation_hostid: 0x2
+ secproxy:
+ subhdr:
+ magic: 0x1207
+ size: 7
+ scaling_factor: 0x1
+ scaling_profile: 0x1
+ disable_main_nav_secure_proxy: 0
+ msmc:
+ subhdr:
+ magic: 0xA5C3
+ size: 5
+ msmc_cache_size: 0x0
+ debug_cfg:
+ subhdr:
+ magic: 0x020C
+ size: 8
+ trace_dst_enables: 0x00
+ trace_src_enables: 0x00
diff --git a/board/beagle/beagleboneai64/pm-cfg.yaml b/board/beagle/beagleboneai64/pm-cfg.yaml
new file mode 100644
index 0000000..7ae52b3
--- /dev/null
+++ b/board/beagle/beagleboneai64/pm-cfg.yaml
@@ -0,0 +1,12 @@
+# SPDX-License-Identifier: GPL-2.0+
+# Copyright (C) 2022-2023 Texas Instruments Incorporated - https://www.ti.com/
+#
+# Power management configuration for J721E
+#
+
+---
+
+pm-cfg:
+ rev:
+ boardcfg_abi_maj: 0x0
+ boardcfg_abi_min: 0x1
diff --git a/board/beagle/beagleboneai64/rm-cfg.yaml b/board/beagle/beagleboneai64/rm-cfg.yaml
new file mode 100644
index 0000000..9f604cf
--- /dev/null
+++ b/board/beagle/beagleboneai64/rm-cfg.yaml
@@ -0,0 +1,3174 @@
+# SPDX-License-Identifier: GPL-2.0+
+# Copyright (C) 2022-2023 Texas Instruments Incorporated - https://www.ti.com/
+#
+# Resource management configuration for J721E
+#
+
+---
+
+rm-cfg:
+ rm_boardcfg:
+ rev:
+ boardcfg_abi_maj: 0x0
+ boardcfg_abi_min: 0x1
+ host_cfg:
+ subhdr:
+ magic: 0x4C41
+ size: 356
+ host_cfg_entries:
+ - #1
+ host_id: 3
+ allowed_atype: 0x2A
+ allowed_qos: 0xAAAA
+ allowed_orderid: 0xAAAAAAAA
+ allowed_priority: 0xAAAA
+ allowed_sched_priority: 0xAA
+ - #2
+ host_id: 5
+ allowed_atype: 0x2A
+ allowed_qos: 0xAAAA
+ allowed_orderid: 0xAAAAAAAA
+ allowed_priority: 0xAAAA
+ allowed_sched_priority: 0xAA
+ - #3
+ host_id: 12
+ allowed_atype: 0x2A
+ allowed_qos: 0xAAAA
+ allowed_orderid: 0xAAAAAAAA
+ allowed_priority: 0xAAAA
+ allowed_sched_priority: 0xAA
+ - #4
+ host_id: 13
+ allowed_atype: 0x2A
+ allowed_qos: 0xAAAA
+ allowed_orderid: 0xAAAAAAAA
+ allowed_priority: 0xAAAA
+ allowed_sched_priority: 0xAA
+ - #5
+ host_id: 21
+ allowed_atype: 0x2A
+ allowed_qos: 0xAAAA
+ allowed_orderid: 0xAAAAAAAA
+ allowed_priority: 0xAAAA
+ allowed_sched_priority: 0xAA
+ - #6
+ host_id: 26
+ allowed_atype: 0x2A
+ allowed_qos: 0xAAAA
+ allowed_orderid: 0xAAAAAAAA
+ allowed_priority: 0xAAAA
+ allowed_sched_priority: 0xAA
+ - #7
+ host_id: 28
+ allowed_atype: 0x2A
+ allowed_qos: 0xAAAA
+ allowed_orderid: 0xAAAAAAAA
+ allowed_priority: 0xAAAA
+ allowed_sched_priority: 0xAA
+ - #8
+ host_id: 35
+ allowed_atype: 0x2A
+ allowed_qos: 0xAAAA
+ allowed_orderid: 0xAAAAAAAA
+ allowed_priority: 0xAAAA
+ allowed_sched_priority: 0xAA
+ - #9
+ host_id: 37
+ allowed_atype: 0x2A
+ allowed_qos: 0xAAAA
+ allowed_orderid: 0xAAAAAAAA
+ allowed_priority: 0xAAAA
+ allowed_sched_priority: 0xAA
+ - #10
+ host_id: 40
+ allowed_atype: 0x2A
+ allowed_qos: 0xAAAA
+ allowed_orderid: 0xAAAAAAAA
+ allowed_priority: 0xAAAA
+ allowed_sched_priority: 0xAA
+ - #11
+ host_id: 42
+ allowed_atype: 0x2A
+ allowed_qos: 0xAAAA
+ allowed_orderid: 0xAAAAAAAA
+ allowed_priority: 0xAAAA
+ allowed_sched_priority: 0xAA
+ - #12
+ host_id: 0
+ allowed_atype: 0
+ allowed_qos: 0
+ allowed_orderid: 0
+ allowed_priority: 0
+ allowed_sched_priority: 0
+ - #13
+ host_id: 0
+ allowed_atype: 0
+ allowed_qos: 0
+ allowed_orderid: 0
+ allowed_priority: 0
+ allowed_sched_priority: 0
+ - #14
+ host_id: 0
+ allowed_atype: 0
+ allowed_qos: 0
+ allowed_orderid: 0
+ allowed_priority: 0
+ allowed_sched_priority: 0
+ - #15
+ host_id: 0
+ allowed_atype: 0
+ allowed_qos: 0
+ allowed_orderid: 0
+ allowed_priority: 0
+ allowed_sched_priority: 0
+ - #16
+ host_id: 0
+ allowed_atype: 0
+ allowed_qos: 0
+ allowed_orderid: 0
+ allowed_priority: 0
+ allowed_sched_priority: 0
+ - #17
+ host_id: 0
+ allowed_atype: 0
+ allowed_qos: 0
+ allowed_orderid: 0
+ allowed_priority: 0
+ allowed_sched_priority: 0
+ - #18
+ host_id: 0
+ allowed_atype: 0
+ allowed_qos: 0
+ allowed_orderid: 0
+ allowed_priority: 0
+ allowed_sched_priority: 0
+ - #19
+ host_id: 0
+ allowed_atype: 0
+ allowed_qos: 0
+ allowed_orderid: 0
+ allowed_priority: 0
+ allowed_sched_priority: 0
+ - #20
+ host_id: 0
+ allowed_atype: 0
+ allowed_qos: 0
+ allowed_orderid: 0
+ allowed_priority: 0
+ allowed_sched_priority: 0
+ - #21
+ host_id: 0
+ allowed_atype: 0
+ allowed_qos: 0
+ allowed_orderid: 0
+ allowed_priority: 0
+ allowed_sched_priority: 0
+ - #22
+ host_id: 0
+ allowed_atype: 0
+ allowed_qos: 0
+ allowed_orderid: 0
+ allowed_priority: 0
+ allowed_sched_priority: 0
+ - #23
+ host_id: 0
+ allowed_atype: 0
+ allowed_qos: 0
+ allowed_orderid: 0
+ allowed_priority: 0
+ allowed_sched_priority: 0
+ - #24
+ host_id: 0
+ allowed_atype: 0
+ allowed_qos: 0
+ allowed_orderid: 0
+ allowed_priority: 0
+ allowed_sched_priority: 0
+ - #25
+ host_id: 0
+ allowed_atype: 0
+ allowed_qos: 0
+ allowed_orderid: 0
+ allowed_priority: 0
+ allowed_sched_priority: 0
+ - #26
+ host_id: 0
+ allowed_atype: 0
+ allowed_qos: 0
+ allowed_orderid: 0
+ allowed_priority: 0
+ allowed_sched_priority: 0
+ - #27
+ host_id: 0
+ allowed_atype: 0
+ allowed_qos: 0
+ allowed_orderid: 0
+ allowed_priority: 0
+ allowed_sched_priority: 0
+ - #28
+ host_id: 0
+ allowed_atype: 0
+ allowed_qos: 0
+ allowed_orderid: 0
+ allowed_priority: 0
+ allowed_sched_priority: 0
+ - #29
+ host_id: 0
+ allowed_atype: 0
+ allowed_qos: 0
+ allowed_orderid: 0
+ allowed_priority: 0
+ allowed_sched_priority: 0
+ - #30
+ host_id: 0
+ allowed_atype: 0
+ allowed_qos: 0
+ allowed_orderid: 0
+ allowed_priority: 0
+ allowed_sched_priority: 0
+ - #31
+ host_id: 0
+ allowed_atype: 0
+ allowed_qos: 0
+ allowed_orderid: 0
+ allowed_priority: 0
+ allowed_sched_priority: 0
+ - #32
+ host_id: 0
+ allowed_atype: 0
+ allowed_qos: 0
+ allowed_orderid: 0
+ allowed_priority: 0
+ allowed_sched_priority: 0
+ resasg:
+ subhdr:
+ magic: 0x7B25
+ size: 8
+ resasg_entries_size: 3344
+ reserved: 0
+ resasg_entries:
+ -
+ start_resource: 4
+ num_resource: 93
+ type: 7744
+ host_id: 26
+ reserved: 0
+
+ -
+ start_resource: 4
+ num_resource: 93
+ type: 7808
+ host_id: 28
+ reserved: 0
+
+ -
+ start_resource: 0
+ num_resource: 32
+ type: 7872
+ host_id: 128
+ reserved: 0
+
+ -
+ start_resource: 0
+ num_resource: 32
+ type: 8192
+ host_id: 3
+ reserved: 0
+
+ -
+ start_resource: 32
+ num_resource: 32
+ type: 8192
+ host_id: 5
+ reserved: 0
+
+ -
+ start_resource: 0
+ num_resource: 24
+ type: 8320
+ host_id: 3
+ reserved: 0
+
+ -
+ start_resource: 24
+ num_resource: 24
+ type: 8320
+ host_id: 5
+ reserved: 0
+
+ -
+ start_resource: 0
+ num_resource: 8
+ type: 8384
+ host_id: 3
+ reserved: 0
+
+ -
+ start_resource: 8
+ num_resource: 8
+ type: 8384
+ host_id: 5
+ reserved: 0
+
+ -
+ start_resource: 16
+ num_resource: 4
+ type: 8384
+ host_id: 40
+ reserved: 0
+
+ -
+ start_resource: 20
+ num_resource: 4
+ type: 8384
+ host_id: 42
+ reserved: 0
+
+ -
+ start_resource: 24
+ num_resource: 4
+ type: 8384
+ host_id: 35
+ reserved: 0
+
+ -
+ start_resource: 28
+ num_resource: 4
+ type: 8384
+ host_id: 37
+ reserved: 0
+
+ -
+ start_resource: 32
+ num_resource: 4
+ type: 8384
+ host_id: 26
+ reserved: 0
+
+ -
+ start_resource: 36
+ num_resource: 4
+ type: 8384
+ host_id: 28
+ reserved: 0
+
+ -
+ start_resource: 40
+ num_resource: 12
+ type: 8384
+ host_id: 12
+ reserved: 0
+
+ -
+ start_resource: 52
+ num_resource: 12
+ type: 8384
+ host_id: 13
+ reserved: 0
+
+ -
+ start_resource: 0
+ num_resource: 128
+ type: 8576
+ host_id: 35
+ reserved: 0
+
+ -
+ start_resource: 128
+ num_resource: 128
+ type: 8576
+ host_id: 37
+ reserved: 0
+
+ -
+ start_resource: 0
+ num_resource: 128
+ type: 8640
+ host_id: 40
+ reserved: 0
+
+ -
+ start_resource: 128
+ num_resource: 128
+ type: 8640
+ host_id: 42
+ reserved: 0
+
+ -
+ start_resource: 0
+ num_resource: 48
+ type: 8704
+ host_id: 128
+ reserved: 0
+
+ -
+ start_resource: 0
+ num_resource: 8
+ type: 8768
+ host_id: 3
+ reserved: 0
+
+ -
+ start_resource: 8
+ num_resource: 8
+ type: 8768
+ host_id: 5
+ reserved: 0
+
+ -
+ start_resource: 16
+ num_resource: 6
+ type: 8768
+ host_id: 12
+ reserved: 0
+
+ -
+ start_resource: 22
+ num_resource: 6
+ type: 8768
+ host_id: 13
+ reserved: 0
+
+ -
+ start_resource: 28
+ num_resource: 2
+ type: 8768
+ host_id: 35
+ reserved: 0
+
+ -
+ start_resource: 30
+ num_resource: 2
+ type: 8768
+ host_id: 37
+ reserved: 0
+
+ -
+ start_resource: 0
+ num_resource: 64
+ type: 13258
+ host_id: 128
+ reserved: 0
+
+ -
+ start_resource: 20480
+ num_resource: 1024
+ type: 13261
+ host_id: 128
+ reserved: 0
+
+ -
+ start_resource: 0
+ num_resource: 64
+ type: 13322
+ host_id: 128
+ reserved: 0
+
+ -
+ start_resource: 22528
+ num_resource: 1024
+ type: 13325
+ host_id: 128
+ reserved: 0
+
+ -
+ start_resource: 38
+ num_resource: 86
+ type: 13386
+ host_id: 12
+ reserved: 0
+
+ -
+ start_resource: 124
+ num_resource: 32
+ type: 13386
+ host_id: 13
+ reserved: 0
+
+ -
+ start_resource: 156
+ num_resource: 12
+ type: 13386
+ host_id: 40
+ reserved: 0
+
+ -
+ start_resource: 168
+ num_resource: 12
+ type: 13386
+ host_id: 42
+ reserved: 0
+
+ -
+ start_resource: 180
+ num_resource: 12
+ type: 13386
+ host_id: 21
+ reserved: 0
+
+ -
+ start_resource: 192
+ num_resource: 12
+ type: 13386
+ host_id: 26
+ reserved: 0
+
+ -
+ start_resource: 204
+ num_resource: 12
+ type: 13386
+ host_id: 28
+ reserved: 0
+
+ -
+ start_resource: 216
+ num_resource: 28
+ type: 13386
+ host_id: 35
+ reserved: 0
+
+ -
+ start_resource: 244
+ num_resource: 8
+ type: 13386
+ host_id: 37
+ reserved: 0
+
+ -
+ start_resource: 252
+ num_resource: 4
+ type: 13386
+ host_id: 128
+ reserved: 0
+
+ -
+ start_resource: 38
+ num_resource: 1024
+ type: 13389
+ host_id: 12
+ reserved: 0
+
+ -
+ start_resource: 1062
+ num_resource: 512
+ type: 13389
+ host_id: 13
+ reserved: 0
+
+ -
+ start_resource: 1574
+ num_resource: 32
+ type: 13389
+ host_id: 3
+ reserved: 0
+
+ -
+ start_resource: 1606
+ num_resource: 32
+ type: 13389
+ host_id: 5
+ reserved: 0
+
+ -
+ start_resource: 1638
+ num_resource: 256
+ type: 13389
+ host_id: 40
+ reserved: 0
+
+ -
+ start_resource: 1894
+ num_resource: 256
+ type: 13389
+ host_id: 42
+ reserved: 0
+
+ -
+ start_resource: 2150
+ num_resource: 256
+ type: 13389
+ host_id: 21
+ reserved: 0
+
+ -
+ start_resource: 2406
+ num_resource: 256
+ type: 13389
+ host_id: 26
+ reserved: 0
+
+ -
+ start_resource: 2662
+ num_resource: 256
+ type: 13389
+ host_id: 28
+ reserved: 0
+
+ -
+ start_resource: 2918
+ num_resource: 512
+ type: 13389
+ host_id: 35
+ reserved: 0
+
+ -
+ start_resource: 3430
+ num_resource: 256
+ type: 13389
+ host_id: 37
+ reserved: 0
+
+ -
+ start_resource: 3686
+ num_resource: 922
+ type: 13389
+ host_id: 128
+ reserved: 0
+
+ -
+ start_resource: 0
+ num_resource: 4
+ type: 13440
+ host_id: 12
+ reserved: 0
+
+ -
+ start_resource: 4
+ num_resource: 4
+ type: 13440
+ host_id: 13
+ reserved: 0
+
+ -
+ start_resource: 8
+ num_resource: 4
+ type: 13440
+ host_id: 3
+ reserved: 0
+
+ -
+ start_resource: 12
+ num_resource: 4
+ type: 13440
+ host_id: 5
+ reserved: 0
+
+ -
+ start_resource: 16
+ num_resource: 4
+ type: 13440
+ host_id: 40
+ reserved: 0
+
+ -
+ start_resource: 20
+ num_resource: 4
+ type: 13440
+ host_id: 42
+ reserved: 0
+
+ -
+ start_resource: 24
+ num_resource: 4
+ type: 13440
+ host_id: 21
+ reserved: 0
+
+ -
+ start_resource: 28
+ num_resource: 4
+ type: 13440
+ host_id: 26
+ reserved: 0
+
+ -
+ start_resource: 32
+ num_resource: 4
+ type: 13440
+ host_id: 28
+ reserved: 0
+
+ -
+ start_resource: 36
+ num_resource: 12
+ type: 13440
+ host_id: 35
+ reserved: 0
+
+ -
+ start_resource: 48
+ num_resource: 4
+ type: 13440
+ host_id: 37
+ reserved: 0
+
+ -
+ start_resource: 52
+ num_resource: 12
+ type: 13440
+ host_id: 128
+ reserved: 0
+
+ -
+ start_resource: 0
+ num_resource: 1
+ type: 13504
+ host_id: 128
+ reserved: 0
+
+ -
+ start_resource: 440
+ num_resource: 150
+ type: 13505
+ host_id: 12
+ reserved: 0
+
+ -
+ start_resource: 590
+ num_resource: 40
+ type: 13505
+ host_id: 13
+ reserved: 0
+
+ -
+ start_resource: 630
+ num_resource: 6
+ type: 13505
+ host_id: 3
+ reserved: 0
+
+ -
+ start_resource: 636
+ num_resource: 6
+ type: 13505
+ host_id: 5
+ reserved: 0
+
+ -
+ start_resource: 642
+ num_resource: 10
+ type: 13505
+ host_id: 40
+ reserved: 0
+
+ -
+ start_resource: 652
+ num_resource: 10
+ type: 13505
+ host_id: 42
+ reserved: 0
+
+ -
+ start_resource: 662
+ num_resource: 32
+ type: 13505
+ host_id: 21
+ reserved: 0
+
+ -
+ start_resource: 694
+ num_resource: 38
+ type: 13505
+ host_id: 26
+ reserved: 0
+
+ -
+ start_resource: 732
+ num_resource: 12
+ type: 13505
+ host_id: 28
+ reserved: 0
+
+ -
+ start_resource: 744
+ num_resource: 182
+ type: 13505
+ host_id: 35
+ reserved: 0
+
+ -
+ start_resource: 926
+ num_resource: 40
+ type: 13505
+ host_id: 37
+ reserved: 0
+
+ -
+ start_resource: 966
+ num_resource: 8
+ type: 13505
+ host_id: 128
+ reserved: 0
+
+ -
+ start_resource: 316
+ num_resource: 8
+ type: 13506
+ host_id: 12
+ reserved: 0
+
+ -
+ start_resource: 324
+ num_resource: 2
+ type: 13506
+ host_id: 3
+ reserved: 0
+
+ -
+ start_resource: 324
+ num_resource: 0
+ type: 13506
+ host_id: 13
+ reserved: 0
+
+ -
+ start_resource: 326
+ num_resource: 2
+ type: 13506
+ host_id: 5
+ reserved: 0
+
+ -
+ start_resource: 328
+ num_resource: 2
+ type: 13506
+ host_id: 40
+ reserved: 0
+
+ -
+ start_resource: 330
+ num_resource: 2
+ type: 13506
+ host_id: 42
+ reserved: 0
+
+ -
+ start_resource: 332
+ num_resource: 2
+ type: 13506
+ host_id: 21
+ reserved: 0
+
+ -
+ start_resource: 334
+ num_resource: 8
+ type: 13506
+ host_id: 26
+ reserved: 0
+
+ -
+ start_resource: 342
+ num_resource: 2
+ type: 13506
+ host_id: 28
+ reserved: 0
+
+ -
+ start_resource: 344
+ num_resource: 4
+ type: 13506
+ host_id: 35
+ reserved: 0
+
+ -
+ start_resource: 348
+ num_resource: 1
+ type: 13506
+ host_id: 37
+ reserved: 0
+
+ -
+ start_resource: 349
+ num_resource: 47
+ type: 13506
+ host_id: 12
+ reserved: 0
+
+ -
+ start_resource: 396
+ num_resource: 1
+ type: 13506
+ host_id: 13
+ reserved: 0
+
+ -
+ start_resource: 397
+ num_resource: 4
+ type: 13506
+ host_id: 40
+ reserved: 0
+
+ -
+ start_resource: 401
+ num_resource: 4
+ type: 13506
+ host_id: 42
+ reserved: 0
+
+ -
+ start_resource: 405
+ num_resource: 4
+ type: 13506
+ host_id: 21
+ reserved: 0
+
+ -
+ start_resource: 409
+ num_resource: 8
+ type: 13506
+ host_id: 26
+ reserved: 0
+
+ -
+ start_resource: 417
+ num_resource: 6
+ type: 13506
+ host_id: 28
+ reserved: 0
+
+ -
+ start_resource: 423
+ num_resource: 16
+ type: 13506
+ host_id: 35
+ reserved: 0
+
+ -
+ start_resource: 439
+ num_resource: 1
+ type: 13506
+ host_id: 37
+ reserved: 0
+
+ -
+ start_resource: 16
+ num_resource: 8
+ type: 13507
+ host_id: 12
+ reserved: 0
+
+ -
+ start_resource: 24
+ num_resource: 2
+ type: 13507
+ host_id: 3
+ reserved: 0
+
+ -
+ start_resource: 24
+ num_resource: 0
+ type: 13507
+ host_id: 13
+ reserved: 0
+
+ -
+ start_resource: 26
+ num_resource: 2
+ type: 13507
+ host_id: 5
+ reserved: 0
+
+ -
+ start_resource: 28
+ num_resource: 2
+ type: 13507
+ host_id: 40
+ reserved: 0
+
+ -
+ start_resource: 30
+ num_resource: 2
+ type: 13507
+ host_id: 42
+ reserved: 0
+
+ -
+ start_resource: 32
+ num_resource: 2
+ type: 13507
+ host_id: 21
+ reserved: 0
+
+ -
+ start_resource: 34
+ num_resource: 8
+ type: 13507
+ host_id: 26
+ reserved: 0
+
+ -
+ start_resource: 42
+ num_resource: 2
+ type: 13507
+ host_id: 28
+ reserved: 0
+
+ -
+ start_resource: 44
+ num_resource: 4
+ type: 13507
+ host_id: 35
+ reserved: 0
+
+ -
+ start_resource: 48
+ num_resource: 1
+ type: 13507
+ host_id: 37
+ reserved: 0
+
+ -
+ start_resource: 49
+ num_resource: 47
+ type: 13507
+ host_id: 12
+ reserved: 0
+
+ -
+ start_resource: 96
+ num_resource: 1
+ type: 13507
+ host_id: 13
+ reserved: 0
+
+ -
+ start_resource: 97
+ num_resource: 4
+ type: 13507
+ host_id: 40
+ reserved: 0
+
+ -
+ start_resource: 101
+ num_resource: 4
+ type: 13507
+ host_id: 42
+ reserved: 0
+
+ -
+ start_resource: 105
+ num_resource: 4
+ type: 13507
+ host_id: 21
+ reserved: 0
+
+ -
+ start_resource: 109
+ num_resource: 8
+ type: 13507
+ host_id: 26
+ reserved: 0
+
+ -
+ start_resource: 117
+ num_resource: 6
+ type: 13507
+ host_id: 28
+ reserved: 0
+
+ -
+ start_resource: 123
+ num_resource: 10
+ type: 13507
+ host_id: 35
+ reserved: 0
+
+ -
+ start_resource: 133
+ num_resource: 6
+ type: 13507
+ host_id: 37
+ reserved: 0
+
+ -
+ start_resource: 139
+ num_resource: 1
+ type: 13507
+ host_id: 128
+ reserved: 0
+
+ -
+ start_resource: 140
+ num_resource: 16
+ type: 13508
+ host_id: 21
+ reserved: 0
+
+ -
+ start_resource: 156
+ num_resource: 6
+ type: 13508
+ host_id: 26
+ reserved: 0
+
+ -
+ start_resource: 162
+ num_resource: 6
+ type: 13508
+ host_id: 28
+ reserved: 0
+
+ -
+ start_resource: 168
+ num_resource: 2
+ type: 13508
+ host_id: 35
+ reserved: 0
+
+ -
+ start_resource: 170
+ num_resource: 2
+ type: 13508
+ host_id: 37
+ reserved: 0
+
+ -
+ start_resource: 172
+ num_resource: 96
+ type: 13508
+ host_id: 35
+ reserved: 0
+
+ -
+ start_resource: 268
+ num_resource: 32
+ type: 13508
+ host_id: 37
+ reserved: 0
+
+ -
+ start_resource: 304
+ num_resource: 0
+ type: 13509
+ host_id: 12
+ reserved: 0
+
+ -
+ start_resource: 304
+ num_resource: 4
+ type: 13509
+ host_id: 12
+ reserved: 0
+
+ -
+ start_resource: 304
+ num_resource: 0
+ type: 13509
+ host_id: 35
+ reserved: 0
+
+ -
+ start_resource: 308
+ num_resource: 6
+ type: 13509
+ host_id: 35
+ reserved: 0
+
+ -
+ start_resource: 314
+ num_resource: 2
+ type: 13509
+ host_id: 128
+ reserved: 0
+
+ -
+ start_resource: 300
+ num_resource: 0
+ type: 13510
+ host_id: 12
+ reserved: 0
+
+ -
+ start_resource: 300
+ num_resource: 2
+ type: 13510
+ host_id: 12
+ reserved: 0
+
+ -
+ start_resource: 300
+ num_resource: 0
+ type: 13510
+ host_id: 35
+ reserved: 0
+
+ -
+ start_resource: 302
+ num_resource: 2
+ type: 13510
+ host_id: 35
+ reserved: 0
+
+ -
+ start_resource: 4
+ num_resource: 0
+ type: 13511
+ host_id: 12
+ reserved: 0
+
+ -
+ start_resource: 4
+ num_resource: 4
+ type: 13511
+ host_id: 12
+ reserved: 0
+
+ -
+ start_resource: 4
+ num_resource: 0
+ type: 13511
+ host_id: 35
+ reserved: 0
+
+ -
+ start_resource: 8
+ num_resource: 6
+ type: 13511
+ host_id: 35
+ reserved: 0
+
+ -
+ start_resource: 14
+ num_resource: 2
+ type: 13511
+ host_id: 128
+ reserved: 0
+
+ -
+ start_resource: 0
+ num_resource: 0
+ type: 13512
+ host_id: 12
+ reserved: 0
+
+ -
+ start_resource: 0
+ num_resource: 2
+ type: 13512
+ host_id: 12
+ reserved: 0
+
+ -
+ start_resource: 0
+ num_resource: 0
+ type: 13512
+ host_id: 35
+ reserved: 0
+
+ -
+ start_resource: 2
+ num_resource: 2
+ type: 13512
+ host_id: 35
+ reserved: 0
+
+ -
+ start_resource: 2
+ num_resource: 5
+ type: 13514
+ host_id: 12
+ reserved: 0
+
+ -
+ start_resource: 7
+ num_resource: 1
+ type: 13514
+ host_id: 13
+ reserved: 0
+
+ -
+ start_resource: 0
+ num_resource: 3
+ type: 13515
+ host_id: 12
+ reserved: 0
+
+ -
+ start_resource: 3
+ num_resource: 2
+ type: 13515
+ host_id: 13
+ reserved: 0
+
+ -
+ start_resource: 5
+ num_resource: 1
+ type: 13515
+ host_id: 3
+ reserved: 0
+
+ -
+ start_resource: 6
+ num_resource: 1
+ type: 13515
+ host_id: 5
+ reserved: 0
+
+ -
+ start_resource: 7
+ num_resource: 3
+ type: 13515
+ host_id: 40
+ reserved: 0
+
+ -
+ start_resource: 10
+ num_resource: 3
+ type: 13515
+ host_id: 42
+ reserved: 0
+
+ -
+ start_resource: 13
+ num_resource: 3
+ type: 13515
+ host_id: 21
+ reserved: 0
+
+ -
+ start_resource: 16
+ num_resource: 3
+ type: 13515
+ host_id: 26
+ reserved: 0
+
+ -
+ start_resource: 19
+ num_resource: 3
+ type: 13515
+ host_id: 28
+ reserved: 0
+
+ -
+ start_resource: 22
+ num_resource: 6
+ type: 13515
+ host_id: 35
+ reserved: 0
+
+ -
+ start_resource: 28
+ num_resource: 3
+ type: 13515
+ host_id: 37
+ reserved: 0
+
+ -
+ start_resource: 31
+ num_resource: 1
+ type: 13515
+ host_id: 128
+ reserved: 0
+
+ -
+ start_resource: 140
+ num_resource: 16
+ type: 13568
+ host_id: 12
+ reserved: 0
+
+ -
+ start_resource: 156
+ num_resource: 16
+ type: 13568
+ host_id: 13
+ reserved: 0
+
+ -
+ start_resource: 172
+ num_resource: 128
+ type: 13568
+ host_id: 128
+ reserved: 0
+
+ -
+ start_resource: 0
+ num_resource: 1
+ type: 13569
+ host_id: 128
+ reserved: 0
+
+ -
+ start_resource: 49152
+ num_resource: 1024
+ type: 13570
+ host_id: 128
+ reserved: 0
+
+ -
+ start_resource: 0
+ num_resource: 1
+ type: 13571
+ host_id: 128
+ reserved: 0
+
+ -
+ start_resource: 16
+ num_resource: 8
+ type: 13578
+ host_id: 12
+ reserved: 0
+
+ -
+ start_resource: 24
+ num_resource: 2
+ type: 13578
+ host_id: 3
+ reserved: 0
+
+ -
+ start_resource: 24
+ num_resource: 0
+ type: 13578
+ host_id: 13
+ reserved: 0
+
+ -
+ start_resource: 26
+ num_resource: 2
+ type: 13578
+ host_id: 5
+ reserved: 0
+
+ -
+ start_resource: 28
+ num_resource: 2
+ type: 13578
+ host_id: 40
+ reserved: 0
+
+ -
+ start_resource: 30
+ num_resource: 2
+ type: 13578
+ host_id: 42
+ reserved: 0
+
+ -
+ start_resource: 32
+ num_resource: 2
+ type: 13578
+ host_id: 21
+ reserved: 0
+
+ -
+ start_resource: 34
+ num_resource: 8
+ type: 13578
+ host_id: 26
+ reserved: 0
+
+ -
+ start_resource: 42
+ num_resource: 2
+ type: 13578
+ host_id: 28
+ reserved: 0
+
+ -
+ start_resource: 44
+ num_resource: 4
+ type: 13578
+ host_id: 35
+ reserved: 0
+
+ -
+ start_resource: 48
+ num_resource: 1
+ type: 13578
+ host_id: 37
+ reserved: 0
+
+ -
+ start_resource: 49
+ num_resource: 47
+ type: 13578
+ host_id: 12
+ reserved: 0
+
+ -
+ start_resource: 96
+ num_resource: 1
+ type: 13578
+ host_id: 13
+ reserved: 0
+
+ -
+ start_resource: 97
+ num_resource: 4
+ type: 13578
+ host_id: 40
+ reserved: 0
+
+ -
+ start_resource: 101
+ num_resource: 4
+ type: 13578
+ host_id: 42
+ reserved: 0
+
+ -
+ start_resource: 105
+ num_resource: 4
+ type: 13578
+ host_id: 21
+ reserved: 0
+
+ -
+ start_resource: 109
+ num_resource: 8
+ type: 13578
+ host_id: 26
+ reserved: 0
+
+ -
+ start_resource: 117
+ num_resource: 6
+ type: 13578
+ host_id: 28
+ reserved: 0
+
+ -
+ start_resource: 123
+ num_resource: 16
+ type: 13578
+ host_id: 35
+ reserved: 0
+
+ -
+ start_resource: 139
+ num_resource: 1
+ type: 13578
+ host_id: 37
+ reserved: 0
+
+ -
+ start_resource: 4
+ num_resource: 0
+ type: 13579
+ host_id: 12
+ reserved: 0
+
+ -
+ start_resource: 4
+ num_resource: 4
+ type: 13579
+ host_id: 12
+ reserved: 0
+
+ -
+ start_resource: 4
+ num_resource: 0
+ type: 13579
+ host_id: 35
+ reserved: 0
+
+ -
+ start_resource: 8
+ num_resource: 6
+ type: 13579
+ host_id: 35
+ reserved: 0
+
+ -
+ start_resource: 14
+ num_resource: 2
+ type: 13579
+ host_id: 128
+ reserved: 0
+
+ -
+ start_resource: 0
+ num_resource: 0
+ type: 13580
+ host_id: 12
+ reserved: 0
+
+ -
+ start_resource: 0
+ num_resource: 2
+ type: 13580
+ host_id: 12
+ reserved: 0
+
+ -
+ start_resource: 0
+ num_resource: 0
+ type: 13580
+ host_id: 35
+ reserved: 0
+
+ -
+ start_resource: 2
+ num_resource: 2
+ type: 13580
+ host_id: 35
+ reserved: 0
+
+ -
+ start_resource: 16
+ num_resource: 8
+ type: 13581
+ host_id: 12
+ reserved: 0
+
+ -
+ start_resource: 24
+ num_resource: 2
+ type: 13581
+ host_id: 3
+ reserved: 0
+
+ -
+ start_resource: 24
+ num_resource: 0
+ type: 13581
+ host_id: 13
+ reserved: 0
+
+ -
+ start_resource: 26
+ num_resource: 2
+ type: 13581
+ host_id: 5
+ reserved: 0
+
+ -
+ start_resource: 28
+ num_resource: 2
+ type: 13581
+ host_id: 40
+ reserved: 0
+
+ -
+ start_resource: 30
+ num_resource: 2
+ type: 13581
+ host_id: 42
+ reserved: 0
+
+ -
+ start_resource: 32
+ num_resource: 2
+ type: 13581
+ host_id: 21
+ reserved: 0
+
+ -
+ start_resource: 34
+ num_resource: 8
+ type: 13581
+ host_id: 26
+ reserved: 0
+
+ -
+ start_resource: 42
+ num_resource: 2
+ type: 13581
+ host_id: 28
+ reserved: 0
+
+ -
+ start_resource: 44
+ num_resource: 4
+ type: 13581
+ host_id: 35
+ reserved: 0
+
+ -
+ start_resource: 48
+ num_resource: 1
+ type: 13581
+ host_id: 37
+ reserved: 0
+
+ -
+ start_resource: 49
+ num_resource: 47
+ type: 13581
+ host_id: 12
+ reserved: 0
+
+ -
+ start_resource: 96
+ num_resource: 1
+ type: 13581
+ host_id: 13
+ reserved: 0
+
+ -
+ start_resource: 97
+ num_resource: 4
+ type: 13581
+ host_id: 40
+ reserved: 0
+
+ -
+ start_resource: 101
+ num_resource: 4
+ type: 13581
+ host_id: 42
+ reserved: 0
+
+ -
+ start_resource: 105
+ num_resource: 4
+ type: 13581
+ host_id: 21
+ reserved: 0
+
+ -
+ start_resource: 109
+ num_resource: 8
+ type: 13581
+ host_id: 26
+ reserved: 0
+
+ -
+ start_resource: 117
+ num_resource: 6
+ type: 13581
+ host_id: 28
+ reserved: 0
+
+ -
+ start_resource: 123
+ num_resource: 10
+ type: 13581
+ host_id: 35
+ reserved: 0
+
+ -
+ start_resource: 133
+ num_resource: 6
+ type: 13581
+ host_id: 37
+ reserved: 0
+
+ -
+ start_resource: 139
+ num_resource: 1
+ type: 13581
+ host_id: 128
+ reserved: 0
+
+ -
+ start_resource: 140
+ num_resource: 16
+ type: 13582
+ host_id: 21
+ reserved: 0
+
+ -
+ start_resource: 156
+ num_resource: 6
+ type: 13582
+ host_id: 26
+ reserved: 0
+
+ -
+ start_resource: 162
+ num_resource: 6
+ type: 13582
+ host_id: 28
+ reserved: 0
+
+ -
+ start_resource: 168
+ num_resource: 2
+ type: 13582
+ host_id: 35
+ reserved: 0
+
+ -
+ start_resource: 170
+ num_resource: 2
+ type: 13582
+ host_id: 37
+ reserved: 0
+
+ -
+ start_resource: 172
+ num_resource: 96
+ type: 13582
+ host_id: 35
+ reserved: 0
+
+ -
+ start_resource: 268
+ num_resource: 32
+ type: 13582
+ host_id: 37
+ reserved: 0
+
+ -
+ start_resource: 4
+ num_resource: 0
+ type: 13583
+ host_id: 12
+ reserved: 0
+
+ -
+ start_resource: 4
+ num_resource: 4
+ type: 13583
+ host_id: 12
+ reserved: 0
+
+ -
+ start_resource: 4
+ num_resource: 0
+ type: 13583
+ host_id: 35
+ reserved: 0
+
+ -
+ start_resource: 8
+ num_resource: 6
+ type: 13583
+ host_id: 35
+ reserved: 0
+
+ -
+ start_resource: 14
+ num_resource: 2
+ type: 13583
+ host_id: 128
+ reserved: 0
+
+ -
+ start_resource: 0
+ num_resource: 0
+ type: 13584
+ host_id: 12
+ reserved: 0
+
+ -
+ start_resource: 0
+ num_resource: 2
+ type: 13584
+ host_id: 12
+ reserved: 0
+
+ -
+ start_resource: 0
+ num_resource: 0
+ type: 13584
+ host_id: 35
+ reserved: 0
+
+ -
+ start_resource: 2
+ num_resource: 2
+ type: 13584
+ host_id: 35
+ reserved: 0
+
+ -
+ start_resource: 10
+ num_resource: 100
+ type: 13632
+ host_id: 12
+ reserved: 0
+
+ -
+ start_resource: 110
+ num_resource: 32
+ type: 13632
+ host_id: 13
+ reserved: 0
+
+ -
+ start_resource: 142
+ num_resource: 46
+ type: 13632
+ host_id: 21
+ reserved: 0
+
+ -
+ start_resource: 196
+ num_resource: 28
+ type: 13632
+ host_id: 35
+ reserved: 0
+
+ -
+ start_resource: 228
+ num_resource: 28
+ type: 13632
+ host_id: 37
+ reserved: 0
+
+ -
+ start_resource: 260
+ num_resource: 28
+ type: 13632
+ host_id: 40
+ reserved: 0
+
+ -
+ start_resource: 292
+ num_resource: 28
+ type: 13632
+ host_id: 42
+ reserved: 0
+
+ -
+ start_resource: 320
+ num_resource: 24
+ type: 13632
+ host_id: 26
+ reserved: 0
+
+ -
+ start_resource: 352
+ num_resource: 24
+ type: 13632
+ host_id: 28
+ reserved: 0
+
+ -
+ start_resource: 400
+ num_resource: 4
+ type: 13632
+ host_id: 3
+ reserved: 0
+
+ -
+ start_resource: 404
+ num_resource: 4
+ type: 13632
+ host_id: 5
+ reserved: 0
+
+ -
+ start_resource: 16
+ num_resource: 32
+ type: 14922
+ host_id: 12
+ reserved: 0
+
+ -
+ start_resource: 48
+ num_resource: 16
+ type: 14922
+ host_id: 13
+ reserved: 0
+
+ -
+ start_resource: 64
+ num_resource: 64
+ type: 14922
+ host_id: 3
+ reserved: 0
+
+ -
+ start_resource: 128
+ num_resource: 4
+ type: 14922
+ host_id: 5
+ reserved: 0
+
+ -
+ start_resource: 132
+ num_resource: 16
+ type: 14922
+ host_id: 40
+ reserved: 0
+
+ -
+ start_resource: 148
+ num_resource: 16
+ type: 14922
+ host_id: 42
+ reserved: 0
+
+ -
+ start_resource: 164
+ num_resource: 8
+ type: 14922
+ host_id: 21
+ reserved: 0
+
+ -
+ start_resource: 172
+ num_resource: 8
+ type: 14922
+ host_id: 26
+ reserved: 0
+
+ -
+ start_resource: 180
+ num_resource: 8
+ type: 14922
+ host_id: 28
+ reserved: 0
+
+ -
+ start_resource: 188
+ num_resource: 24
+ type: 14922
+ host_id: 35
+ reserved: 0
+
+ -
+ start_resource: 212
+ num_resource: 8
+ type: 14922
+ host_id: 37
+ reserved: 0
+
+ -
+ start_resource: 220
+ num_resource: 36
+ type: 14922
+ host_id: 128
+ reserved: 0
+
+ -
+ start_resource: 16400
+ num_resource: 128
+ type: 14925
+ host_id: 12
+ reserved: 0
+
+ -
+ start_resource: 16528
+ num_resource: 128
+ type: 14925
+ host_id: 13
+ reserved: 0
+
+ -
+ start_resource: 16656
+ num_resource: 256
+ type: 14925
+ host_id: 3
+ reserved: 0
+
+ -
+ start_resource: 16912
+ num_resource: 64
+ type: 14925
+ host_id: 5
+ reserved: 0
+
+ -
+ start_resource: 16976
+ num_resource: 128
+ type: 14925
+ host_id: 40
+ reserved: 0
+
+ -
+ start_resource: 17104
+ num_resource: 128
+ type: 14925
+ host_id: 42
+ reserved: 0
+
+ -
+ start_resource: 17232
+ num_resource: 64
+ type: 14925
+ host_id: 21
+ reserved: 0
+
+ -
+ start_resource: 17296
+ num_resource: 64
+ type: 14925
+ host_id: 26
+ reserved: 0
+
+ -
+ start_resource: 17360
+ num_resource: 64
+ type: 14925
+ host_id: 28
+ reserved: 0
+
+ -
+ start_resource: 17424
+ num_resource: 128
+ type: 14925
+ host_id: 35
+ reserved: 0
+
+ -
+ start_resource: 17552
+ num_resource: 128
+ type: 14925
+ host_id: 37
+ reserved: 0
+
+ -
+ start_resource: 17680
+ num_resource: 240
+ type: 14925
+ host_id: 128
+ reserved: 0
+
+ -
+ start_resource: 1
+ num_resource: 4
+ type: 14976
+ host_id: 12
+ reserved: 0
+
+ -
+ start_resource: 5
+ num_resource: 4
+ type: 14976
+ host_id: 13
+ reserved: 0
+
+ -
+ start_resource: 9
+ num_resource: 4
+ type: 14976
+ host_id: 3
+ reserved: 0
+
+ -
+ start_resource: 13
+ num_resource: 4
+ type: 14976
+ host_id: 5
+ reserved: 0
+
+ -
+ start_resource: 17
+ num_resource: 4
+ type: 14976
+ host_id: 40
+ reserved: 0
+
+ -
+ start_resource: 21
+ num_resource: 4
+ type: 14976
+ host_id: 42
+ reserved: 0
+
+ -
+ start_resource: 25
+ num_resource: 4
+ type: 14976
+ host_id: 21
+ reserved: 0
+
+ -
+ start_resource: 29
+ num_resource: 4
+ type: 14976
+ host_id: 26
+ reserved: 0
+
+ -
+ start_resource: 33
+ num_resource: 4
+ type: 14976
+ host_id: 28
+ reserved: 0
+
+ -
+ start_resource: 37
+ num_resource: 16
+ type: 14976
+ host_id: 35
+ reserved: 0
+
+ -
+ start_resource: 53
+ num_resource: 4
+ type: 14976
+ host_id: 37
+ reserved: 0
+
+ -
+ start_resource: 57
+ num_resource: 7
+ type: 14976
+ host_id: 128
+ reserved: 0
+
+ -
+ start_resource: 0
+ num_resource: 1
+ type: 15040
+ host_id: 128
+ reserved: 0
+
+ -
+ start_resource: 96
+ num_resource: 20
+ type: 15041
+ host_id: 12
+ reserved: 0
+
+ -
+ start_resource: 116
+ num_resource: 8
+ type: 15041
+ host_id: 13
+ reserved: 0
+
+ -
+ start_resource: 124
+ num_resource: 32
+ type: 15041
+ host_id: 3
+ reserved: 0
+
+ -
+ start_resource: 156
+ num_resource: 12
+ type: 15041
+ host_id: 5
+ reserved: 0
+
+ -
+ start_resource: 168
+ num_resource: 8
+ type: 15041
+ host_id: 40
+ reserved: 0
+
+ -
+ start_resource: 176
+ num_resource: 8
+ type: 15041
+ host_id: 42
+ reserved: 0
+
+ -
+ start_resource: 184
+ num_resource: 8
+ type: 15041
+ host_id: 21
+ reserved: 0
+
+ -
+ start_resource: 192
+ num_resource: 8
+ type: 15041
+ host_id: 26
+ reserved: 0
+
+ -
+ start_resource: 200
+ num_resource: 8
+ type: 15041
+ host_id: 28
+ reserved: 0
+
+ -
+ start_resource: 208
+ num_resource: 16
+ type: 15041
+ host_id: 35
+ reserved: 0
+
+ -
+ start_resource: 224
+ num_resource: 8
+ type: 15041
+ host_id: 37
+ reserved: 0
+
+ -
+ start_resource: 232
+ num_resource: 20
+ type: 15041
+ host_id: 128
+ reserved: 0
+
+ -
+ start_resource: 50
+ num_resource: 4
+ type: 15042
+ host_id: 12
+ reserved: 0
+
+ -
+ start_resource: 54
+ num_resource: 2
+ type: 15042
+ host_id: 3
+ reserved: 0
+
+ -
+ start_resource: 54
+ num_resource: 0
+ type: 15042
+ host_id: 13
+ reserved: 0
+
+ -
+ start_resource: 56
+ num_resource: 0
+ type: 15042
+ host_id: 5
+ reserved: 0
+
+ -
+ start_resource: 56
+ num_resource: 1
+ type: 15042
+ host_id: 40
+ reserved: 0
+
+ -
+ start_resource: 57
+ num_resource: 1
+ type: 15042
+ host_id: 42
+ reserved: 0
+
+ -
+ start_resource: 58
+ num_resource: 1
+ type: 15042
+ host_id: 21
+ reserved: 0
+
+ -
+ start_resource: 59
+ num_resource: 1
+ type: 15042
+ host_id: 26
+ reserved: 0
+
+ -
+ start_resource: 60
+ num_resource: 1
+ type: 15042
+ host_id: 28
+ reserved: 0
+
+ -
+ start_resource: 61
+ num_resource: 1
+ type: 15042
+ host_id: 35
+ reserved: 0
+
+ -
+ start_resource: 62
+ num_resource: 1
+ type: 15042
+ host_id: 37
+ reserved: 0
+
+ -
+ start_resource: 63
+ num_resource: 9
+ type: 15042
+ host_id: 12
+ reserved: 0
+
+ -
+ start_resource: 72
+ num_resource: 6
+ type: 15042
+ host_id: 13
+ reserved: 0
+
+ -
+ start_resource: 78
+ num_resource: 3
+ type: 15042
+ host_id: 3
+ reserved: 0
+
+ -
+ start_resource: 81
+ num_resource: 2
+ type: 15042
+ host_id: 5
+ reserved: 0
+
+ -
+ start_resource: 83
+ num_resource: 1
+ type: 15042
+ host_id: 40
+ reserved: 0
+
+ -
+ start_resource: 84
+ num_resource: 1
+ type: 15042
+ host_id: 42
+ reserved: 0
+
+ -
+ start_resource: 85
+ num_resource: 1
+ type: 15042
+ host_id: 21
+ reserved: 0
+
+ -
+ start_resource: 86
+ num_resource: 1
+ type: 15042
+ host_id: 26
+ reserved: 0
+
+ -
+ start_resource: 87
+ num_resource: 1
+ type: 15042
+ host_id: 28
+ reserved: 0
+
+ -
+ start_resource: 88
+ num_resource: 2
+ type: 15042
+ host_id: 35
+ reserved: 0
+
+ -
+ start_resource: 90
+ num_resource: 1
+ type: 15042
+ host_id: 37
+ reserved: 0
+
+ -
+ start_resource: 91
+ num_resource: 2
+ type: 15042
+ host_id: 128
+ reserved: 0
+
+ -
+ start_resource: 2
+ num_resource: 4
+ type: 15043
+ host_id: 12
+ reserved: 0
+
+ -
+ start_resource: 6
+ num_resource: 2
+ type: 15043
+ host_id: 3
+ reserved: 0
+
+ -
+ start_resource: 6
+ num_resource: 0
+ type: 15043
+ host_id: 13
+ reserved: 0
+
+ -
+ start_resource: 8
+ num_resource: 0
+ type: 15043
+ host_id: 5
+ reserved: 0
+
+ -
+ start_resource: 8
+ num_resource: 1
+ type: 15043
+ host_id: 40
+ reserved: 0
+
+ -
+ start_resource: 9
+ num_resource: 1
+ type: 15043
+ host_id: 42
+ reserved: 0
+
+ -
+ start_resource: 10
+ num_resource: 1
+ type: 15043
+ host_id: 21
+ reserved: 0
+
+ -
+ start_resource: 11
+ num_resource: 1
+ type: 15043
+ host_id: 26
+ reserved: 0
+
+ -
+ start_resource: 12
+ num_resource: 1
+ type: 15043
+ host_id: 28
+ reserved: 0
+
+ -
+ start_resource: 13
+ num_resource: 1
+ type: 15043
+ host_id: 35
+ reserved: 0
+
+ -
+ start_resource: 14
+ num_resource: 1
+ type: 15043
+ host_id: 37
+ reserved: 0
+
+ -
+ start_resource: 15
+ num_resource: 9
+ type: 15043
+ host_id: 12
+ reserved: 0
+
+ -
+ start_resource: 24
+ num_resource: 6
+ type: 15043
+ host_id: 13
+ reserved: 0
+
+ -
+ start_resource: 30
+ num_resource: 3
+ type: 15043
+ host_id: 3
+ reserved: 0
+
+ -
+ start_resource: 33
+ num_resource: 2
+ type: 15043
+ host_id: 5
+ reserved: 0
+
+ -
+ start_resource: 35
+ num_resource: 1
+ type: 15043
+ host_id: 40
+ reserved: 0
+
+ -
+ start_resource: 36
+ num_resource: 1
+ type: 15043
+ host_id: 42
+ reserved: 0
+
+ -
+ start_resource: 37
+ num_resource: 1
+ type: 15043
+ host_id: 21
+ reserved: 0
+
+ -
+ start_resource: 38
+ num_resource: 1
+ type: 15043
+ host_id: 26
+ reserved: 0
+
+ -
+ start_resource: 39
+ num_resource: 1
+ type: 15043
+ host_id: 28
+ reserved: 0
+
+ -
+ start_resource: 40
+ num_resource: 2
+ type: 15043
+ host_id: 35
+ reserved: 0
+
+ -
+ start_resource: 42
+ num_resource: 1
+ type: 15043
+ host_id: 37
+ reserved: 0
+
+ -
+ start_resource: 43
+ num_resource: 3
+ type: 15043
+ host_id: 128
+ reserved: 0
+
+ -
+ start_resource: 48
+ num_resource: 0
+ type: 15045
+ host_id: 3
+ reserved: 0
+
+ -
+ start_resource: 48
+ num_resource: 2
+ type: 15045
+ host_id: 3
+ reserved: 0
+
+ -
+ start_resource: 0
+ num_resource: 0
+ type: 15047
+ host_id: 3
+ reserved: 0
+
+ -
+ start_resource: 0
+ num_resource: 2
+ type: 15047
+ host_id: 3
+ reserved: 0
+
+ -
+ start_resource: 2
+ num_resource: 5
+ type: 15050
+ host_id: 12
+ reserved: 0
+
+ -
+ start_resource: 7
+ num_resource: 1
+ type: 15050
+ host_id: 13
+ reserved: 0
+
+ -
+ start_resource: 0
+ num_resource: 3
+ type: 15051
+ host_id: 12
+ reserved: 0
+
+ -
+ start_resource: 3
+ num_resource: 2
+ type: 15051
+ host_id: 13
+ reserved: 0
+
+ -
+ start_resource: 5
+ num_resource: 3
+ type: 15051
+ host_id: 3
+ reserved: 0
+
+ -
+ start_resource: 8
+ num_resource: 3
+ type: 15051
+ host_id: 5
+ reserved: 0
+
+ -
+ start_resource: 11
+ num_resource: 3
+ type: 15051
+ host_id: 40
+ reserved: 0
+
+ -
+ start_resource: 14
+ num_resource: 3
+ type: 15051
+ host_id: 42
+ reserved: 0
+
+ -
+ start_resource: 17
+ num_resource: 3
+ type: 15051
+ host_id: 21
+ reserved: 0
+
+ -
+ start_resource: 20
+ num_resource: 3
+ type: 15051
+ host_id: 26
+ reserved: 0
+
+ -
+ start_resource: 23
+ num_resource: 3
+ type: 15051
+ host_id: 28
+ reserved: 0
+
+ -
+ start_resource: 26
+ num_resource: 3
+ type: 15051
+ host_id: 35
+ reserved: 0
+
+ -
+ start_resource: 29
+ num_resource: 3
+ type: 15051
+ host_id: 37
+ reserved: 0
+
+ -
+ start_resource: 48
+ num_resource: 8
+ type: 15104
+ host_id: 12
+ reserved: 0
+
+ -
+ start_resource: 56
+ num_resource: 4
+ type: 15104
+ host_id: 13
+ reserved: 0
+
+ -
+ start_resource: 60
+ num_resource: 8
+ type: 15104
+ host_id: 3
+ reserved: 0
+
+ -
+ start_resource: 68
+ num_resource: 4
+ type: 15104
+ host_id: 5
+ reserved: 0
+
+ -
+ start_resource: 72
+ num_resource: 4
+ type: 15104
+ host_id: 40
+ reserved: 0
+
+ -
+ start_resource: 76
+ num_resource: 4
+ type: 15104
+ host_id: 42
+ reserved: 0
+
+ -
+ start_resource: 80
+ num_resource: 8
+ type: 15104
+ host_id: 35
+ reserved: 0
+
+ -
+ start_resource: 88
+ num_resource: 4
+ type: 15104
+ host_id: 37
+ reserved: 0
+
+ -
+ start_resource: 92
+ num_resource: 4
+ type: 15104
+ host_id: 128
+ reserved: 0
+
+ -
+ start_resource: 0
+ num_resource: 1
+ type: 15105
+ host_id: 128
+ reserved: 0
+
+ -
+ start_resource: 56320
+ num_resource: 256
+ type: 15106
+ host_id: 128
+ reserved: 0
+
+ -
+ start_resource: 0
+ num_resource: 1
+ type: 15107
+ host_id: 128
+ reserved: 0
+
+ -
+ start_resource: 2
+ num_resource: 4
+ type: 15114
+ host_id: 12
+ reserved: 0
+
+ -
+ start_resource: 6
+ num_resource: 2
+ type: 15114
+ host_id: 3
+ reserved: 0
+
+ -
+ start_resource: 6
+ num_resource: 0
+ type: 15114
+ host_id: 13
+ reserved: 0
+
+ -
+ start_resource: 8
+ num_resource: 0
+ type: 15114
+ host_id: 5
+ reserved: 0
+
+ -
+ start_resource: 8
+ num_resource: 1
+ type: 15114
+ host_id: 40
+ reserved: 0
+
+ -
+ start_resource: 9
+ num_resource: 1
+ type: 15114
+ host_id: 42
+ reserved: 0
+
+ -
+ start_resource: 10
+ num_resource: 1
+ type: 15114
+ host_id: 21
+ reserved: 0
+
+ -
+ start_resource: 11
+ num_resource: 1
+ type: 15114
+ host_id: 26
+ reserved: 0
+
+ -
+ start_resource: 12
+ num_resource: 1
+ type: 15114
+ host_id: 28
+ reserved: 0
+
+ -
+ start_resource: 13
+ num_resource: 1
+ type: 15114
+ host_id: 35
+ reserved: 0
+
+ -
+ start_resource: 14
+ num_resource: 1
+ type: 15114
+ host_id: 37
+ reserved: 0
+
+ -
+ start_resource: 15
+ num_resource: 9
+ type: 15114
+ host_id: 12
+ reserved: 0
+
+ -
+ start_resource: 24
+ num_resource: 6
+ type: 15114
+ host_id: 13
+ reserved: 0
+
+ -
+ start_resource: 30
+ num_resource: 3
+ type: 15114
+ host_id: 3
+ reserved: 0
+
+ -
+ start_resource: 33
+ num_resource: 2
+ type: 15114
+ host_id: 5
+ reserved: 0
+
+ -
+ start_resource: 35
+ num_resource: 1
+ type: 15114
+ host_id: 40
+ reserved: 0
+
+ -
+ start_resource: 36
+ num_resource: 1
+ type: 15114
+ host_id: 42
+ reserved: 0
+
+ -
+ start_resource: 37
+ num_resource: 1
+ type: 15114
+ host_id: 21
+ reserved: 0
+
+ -
+ start_resource: 38
+ num_resource: 1
+ type: 15114
+ host_id: 26
+ reserved: 0
+
+ -
+ start_resource: 39
+ num_resource: 1
+ type: 15114
+ host_id: 28
+ reserved: 0
+
+ -
+ start_resource: 40
+ num_resource: 2
+ type: 15114
+ host_id: 35
+ reserved: 0
+
+ -
+ start_resource: 42
+ num_resource: 1
+ type: 15114
+ host_id: 37
+ reserved: 0
+
+ -
+ start_resource: 43
+ num_resource: 2
+ type: 15114
+ host_id: 128
+ reserved: 0
+
+ -
+ start_resource: 0
+ num_resource: 0
+ type: 15115
+ host_id: 3
+ reserved: 0
+
+ -
+ start_resource: 0
+ num_resource: 2
+ type: 15115
+ host_id: 3
+ reserved: 0
+
+ -
+ start_resource: 2
+ num_resource: 4
+ type: 15117
+ host_id: 12
+ reserved: 0
+
+ -
+ start_resource: 6
+ num_resource: 2
+ type: 15117
+ host_id: 3
+ reserved: 0
+
+ -
+ start_resource: 6
+ num_resource: 0
+ type: 15117
+ host_id: 13
+ reserved: 0
+
+ -
+ start_resource: 8
+ num_resource: 0
+ type: 15117
+ host_id: 5
+ reserved: 0
+
+ -
+ start_resource: 8
+ num_resource: 1
+ type: 15117
+ host_id: 40
+ reserved: 0
+
+ -
+ start_resource: 9
+ num_resource: 1
+ type: 15117
+ host_id: 42
+ reserved: 0
+
+ -
+ start_resource: 10
+ num_resource: 1
+ type: 15117
+ host_id: 21
+ reserved: 0
+
+ -
+ start_resource: 11
+ num_resource: 1
+ type: 15117
+ host_id: 26
+ reserved: 0
+
+ -
+ start_resource: 12
+ num_resource: 1
+ type: 15117
+ host_id: 28
+ reserved: 0
+
+ -
+ start_resource: 13
+ num_resource: 1
+ type: 15117
+ host_id: 35
+ reserved: 0
+
+ -
+ start_resource: 14
+ num_resource: 1
+ type: 15117
+ host_id: 37
+ reserved: 0
+
+ -
+ start_resource: 15
+ num_resource: 9
+ type: 15117
+ host_id: 12
+ reserved: 0
+
+ -
+ start_resource: 24
+ num_resource: 6
+ type: 15117
+ host_id: 13
+ reserved: 0
+
+ -
+ start_resource: 30
+ num_resource: 3
+ type: 15117
+ host_id: 3
+ reserved: 0
+
+ -
+ start_resource: 33
+ num_resource: 2
+ type: 15117
+ host_id: 5
+ reserved: 0
+
+ -
+ start_resource: 35
+ num_resource: 1
+ type: 15117
+ host_id: 40
+ reserved: 0
+
+ -
+ start_resource: 36
+ num_resource: 1
+ type: 15117
+ host_id: 42
+ reserved: 0
+
+ -
+ start_resource: 37
+ num_resource: 1
+ type: 15117
+ host_id: 21
+ reserved: 0
+
+ -
+ start_resource: 38
+ num_resource: 1
+ type: 15117
+ host_id: 26
+ reserved: 0
+
+ -
+ start_resource: 39
+ num_resource: 1
+ type: 15117
+ host_id: 28
+ reserved: 0
+
+ -
+ start_resource: 40
+ num_resource: 2
+ type: 15117
+ host_id: 35
+ reserved: 0
+
+ -
+ start_resource: 42
+ num_resource: 1
+ type: 15117
+ host_id: 37
+ reserved: 0
+
+ -
+ start_resource: 43
+ num_resource: 3
+ type: 15117
+ host_id: 128
+ reserved: 0
+
+ -
+ start_resource: 0
+ num_resource: 0
+ type: 15119
+ host_id: 3
+ reserved: 0
+
+ -
+ start_resource: 0
+ num_resource: 2
+ type: 15119
+ host_id: 3
+ reserved: 0
+
+ -
+ start_resource: 12
+ num_resource: 20
+ type: 15168
+ host_id: 3
+ reserved: 0
+
+ -
+ start_resource: 36
+ num_resource: 28
+ type: 15168
+ host_id: 5
+ reserved: 0
diff --git a/board/beagle/beagleboneai64/sec-cfg.yaml b/board/beagle/beagleboneai64/sec-cfg.yaml
new file mode 100644
index 0000000..1eab588
--- /dev/null
+++ b/board/beagle/beagleboneai64/sec-cfg.yaml
@@ -0,0 +1,380 @@
+# SPDX-License-Identifier: GPL-2.0+
+# Copyright (C) 2022-2023 Texas Instruments Incorporated - https://www.ti.com/
+#
+# Security configuration for J721E
+#
+
+---
+
+sec-cfg:
+ rev:
+ boardcfg_abi_maj: 0x0
+ boardcfg_abi_min: 0x1
+ processor_acl_list:
+ subhdr:
+ magic: 0xF1EA
+ size: 164
+ proc_acl_entries:
+ - #1
+ processor_id: 0
+ proc_access_master: 0
+ proc_access_secondary: [0, 0, 0]
+ - #2
+ processor_id: 0
+ proc_access_master: 0
+ proc_access_secondary: [0, 0, 0]
+ - #3
+ processor_id: 0
+ proc_access_master: 0
+ proc_access_secondary: [0, 0, 0]
+ - #4
+ processor_id: 0
+ proc_access_master: 0
+ proc_access_secondary: [0, 0, 0]
+ - #5
+ processor_id: 0
+ proc_access_master: 0
+ proc_access_secondary: [0, 0, 0]
+ - #6
+ processor_id: 0
+ proc_access_master: 0
+ proc_access_secondary: [0, 0, 0]
+ - #7
+ processor_id: 0
+ proc_access_master: 0
+ proc_access_secondary: [0, 0, 0]
+ - #8
+ processor_id: 0
+ proc_access_master: 0
+ proc_access_secondary: [0, 0, 0]
+ - #9
+ processor_id: 0
+ proc_access_master: 0
+ proc_access_secondary: [0, 0, 0]
+ - #10
+ processor_id: 0
+ proc_access_master: 0
+ proc_access_secondary: [0, 0, 0]
+ - #11
+ processor_id: 0
+ proc_access_master: 0
+ proc_access_secondary: [0, 0, 0]
+ - #12
+ processor_id: 0
+ proc_access_master: 0
+ proc_access_secondary: [0, 0, 0]
+ - #13
+ processor_id: 0
+ proc_access_master: 0
+ proc_access_secondary: [0, 0, 0]
+ - #14
+ processor_id: 0
+ proc_access_master: 0
+ proc_access_secondary: [0, 0, 0]
+ - #15
+ processor_id: 0
+ proc_access_master: 0
+ proc_access_secondary: [0, 0, 0]
+ - #16
+ processor_id: 0
+ proc_access_master: 0
+ proc_access_secondary: [0, 0, 0]
+ - #17
+ processor_id: 0
+ proc_access_master: 0
+ proc_access_secondary: [0, 0, 0]
+ - #18
+ processor_id: 0
+ proc_access_master: 0
+ proc_access_secondary: [0, 0, 0]
+ - #19
+ processor_id: 0
+ proc_access_master: 0
+ proc_access_secondary: [0, 0, 0]
+ - #20
+ processor_id: 0
+ proc_access_master: 0
+ proc_access_secondary: [0, 0, 0]
+ - #21
+ processor_id: 0
+ proc_access_master: 0
+ proc_access_secondary: [0, 0, 0]
+ - #22
+ processor_id: 0
+ proc_access_master: 0
+ proc_access_secondary: [0, 0, 0]
+ - #23
+ processor_id: 0
+ proc_access_master: 0
+ proc_access_secondary: [0, 0, 0]
+ - #24
+ processor_id: 0
+ proc_access_master: 0
+ proc_access_secondary: [0, 0, 0]
+ - #25
+ processor_id: 0
+ proc_access_master: 0
+ proc_access_secondary: [0, 0, 0]
+ - #26
+ processor_id: 0
+ proc_access_master: 0
+ proc_access_secondary: [0, 0, 0]
+ - #27
+ processor_id: 0
+ proc_access_master: 0
+ proc_access_secondary: [0, 0, 0]
+ - #28
+ processor_id: 0
+ proc_access_master: 0
+ proc_access_secondary: [0, 0, 0]
+ - #29
+ processor_id: 0
+ proc_access_master: 0
+ proc_access_secondary: [0, 0, 0]
+ - #30
+ processor_id: 0
+ proc_access_master: 0
+ proc_access_secondary: [0, 0, 0]
+ - #31
+ processor_id: 0
+ proc_access_master: 0
+ proc_access_secondary: [0, 0, 0]
+ - #32
+ processor_id: 0
+ proc_access_master: 0
+ proc_access_secondary: [0, 0, 0]
+
+ host_hierarchy:
+ subhdr:
+ magic: 0x8D27
+ size: 68
+ host_hierarchy_entries:
+ - #1
+ host_id: 0
+ supervisor_host_id: 0
+ - #2
+ host_id: 0
+ supervisor_host_id: 0
+ - #3
+ host_id: 0
+ supervisor_host_id: 0
+ - #4
+ host_id: 0
+ supervisor_host_id: 0
+ - #5
+ host_id: 0
+ supervisor_host_id: 0
+ - #6
+ host_id: 0
+ supervisor_host_id: 0
+ - #7
+ host_id: 0
+ supervisor_host_id: 0
+ - #8
+ host_id: 0
+ supervisor_host_id: 0
+ - #9
+ host_id: 0
+ supervisor_host_id: 0
+ - #10
+ host_id: 0
+ supervisor_host_id: 0
+ - #11
+ host_id: 0
+ supervisor_host_id: 0
+ - #12
+ host_id: 0
+ supervisor_host_id: 0
+ - #13
+ host_id: 0
+ supervisor_host_id: 0
+ - #14
+ host_id: 0
+ supervisor_host_id: 0
+ - #15
+ host_id: 0
+ supervisor_host_id: 0
+ - #16
+ host_id: 0
+ supervisor_host_id: 0
+ - #17
+ host_id: 0
+ supervisor_host_id: 0
+ - #18
+ host_id: 0
+ supervisor_host_id: 0
+ - #19
+ host_id: 0
+ supervisor_host_id: 0
+ - #20
+ host_id: 0
+ supervisor_host_id: 0
+ - #21
+ host_id: 0
+ supervisor_host_id: 0
+ - #22
+ host_id: 0
+ supervisor_host_id: 0
+ - #23
+ host_id: 0
+ supervisor_host_id: 0
+ - #24
+ host_id: 0
+ supervisor_host_id: 0
+ - #25
+ host_id: 0
+ supervisor_host_id: 0
+ - #26
+ host_id: 0
+ supervisor_host_id: 0
+ - #27
+ host_id: 0
+ supervisor_host_id: 0
+ - #28
+ host_id: 0
+ supervisor_host_id: 0
+ - #29
+ host_id: 0
+ supervisor_host_id: 0
+ - #30
+ host_id: 0
+ supervisor_host_id: 0
+ - #31
+ host_id: 0
+ supervisor_host_id: 0
+ - #32
+ host_id: 0
+ supervisor_host_id: 0
+ otp_config:
+ subhdr:
+ magic: 0x4081
+ size: 69
+ otp_entry:
+ - #1
+ host_id: 0
+ host_perms: 0
+ - #2
+ host_id: 0
+ host_perms: 0
+ - #3
+ host_id: 0
+ host_perms: 0
+ - #4
+ host_id: 0
+ host_perms: 0
+ - #5
+ host_id: 0
+ host_perms: 0
+ - #6
+ host_id: 0
+ host_perms: 0
+ - #7
+ host_id: 0
+ host_perms: 0
+ - #8
+ host_id: 0
+ host_perms: 0
+ - #9
+ host_id: 0
+ host_perms: 0
+ - #10
+ host_id: 0
+ host_perms: 0
+ - #11
+ host_id: 0
+ host_perms: 0
+ - #12
+ host_id: 0
+ host_perms: 0
+ - #13
+ host_id: 0
+ host_perms: 0
+ - #14
+ host_id: 0
+ host_perms: 0
+ - #15
+ host_id: 0
+ host_perms: 0
+ - #16
+ host_id: 0
+ host_perms: 0
+ - #17
+ host_id: 0
+ host_perms: 0
+ - #18
+ host_id: 0
+ host_perms: 0
+ - #19
+ host_id: 0
+ host_perms: 0
+ - #20
+ host_id: 0
+ host_perms: 0
+ - #21
+ host_id: 0
+ host_perms: 0
+ - #22
+ host_id: 0
+ host_perms: 0
+ - #23
+ host_id: 0
+ host_perms: 0
+ - #24
+ host_id: 0
+ host_perms: 0
+ - #25
+ host_id: 0
+ host_perms: 0
+ - #26
+ host_id: 0
+ host_perms: 0
+ - #27
+ host_id: 0
+ host_perms: 0
+ - #28
+ host_id: 0
+ host_perms: 0
+ - #29
+ host_id: 0
+ host_perms: 0
+ - #30
+ host_id: 0
+ host_perms: 0
+ - #31
+ host_id: 0
+ host_perms: 0
+ - #32
+ host_id: 0
+ host_perms: 0
+ write_host_id: 0
+ dkek_config:
+ subhdr:
+ magic: 0x5170
+ size: 12
+ allowed_hosts: [128, 0, 0, 0]
+ allow_dkek_export_tisci: 0x5A
+ rsvd: [0, 0, 0]
+ sa2ul_cfg:
+ subhdr:
+ magic: 0x23BE
+ size: 0
+ auth_resource_owner: 0
+ enable_saul_psil_global_config_writes: 0
+ rsvd: [0, 0]
+ sec_dbg_config:
+ subhdr:
+ magic: 0x42AF
+ size: 16
+ allow_jtag_unlock: 0x5A
+ allow_wildcard_unlock: 0x5A
+ allowed_debug_level_rsvd: 0
+ rsvd: 0
+ min_cert_rev: 0x0
+ jtag_unlock_hosts: [0, 0, 0, 0]
+ sec_handover_cfg:
+ subhdr:
+ magic: 0x608F
+ size: 10
+ handover_msg_sender: 0
+ handover_to_host_id: 0
+ rsvd: [0, 0, 0, 0]
diff --git a/board/beagle/beagleplay/Kconfig b/board/beagle/beagleplay/Kconfig
new file mode 100644
index 0000000..7dbd833
--- /dev/null
+++ b/board/beagle/beagleplay/Kconfig
@@ -0,0 +1,60 @@
+# SPDX-License-Identifier: GPL-2.0+
+#
+# Copyright (C) 2022-2023 Texas Instruments Incorporated - https://www.ti.com/
+# Copyright (C) 2022-2023 Robert Nelson, BeagleBoard.org Foundation
+#
+
+choice
+ prompt "BeagleBoard.org AM625 based BeaglePlay board"
+ optional
+
+config TARGET_AM625_A53_BEAGLEPLAY
+ bool "BeagleBoard.org AM625 BeaglePlay running on A53"
+ select ARM64
+ select BINMAN
+
+config TARGET_AM625_R5_BEAGLEPLAY
+ bool "BeagleBoard.org AM625 BeaglePlay running on R5"
+ select CPU_V7R
+ select SYS_THUMB_BUILD
+ select K3_LOAD_SYSFW
+ select RAM
+ select SPL_RAM
+ select K3_DDRSS
+ select BINMAN
+ imply SYS_K3_SPL_ATF
+
+endchoice
+
+if TARGET_AM625_A53_BEAGLEPLAY
+
+config SYS_BOARD
+ default "beagleplay"
+
+config SYS_VENDOR
+ default "beagle"
+
+config SYS_CONFIG_NAME
+ default "am62x_evm"
+
+source "board/ti/common/Kconfig"
+
+endif
+
+if TARGET_AM625_R5_BEAGLEPLAY
+
+config SYS_BOARD
+ default "beagleplay"
+
+config SYS_VENDOR
+ default "beagle"
+
+config SYS_CONFIG_NAME
+ default "am62x_evm"
+
+config SPL_LDSCRIPT
+ default "arch/arm/mach-omap2/u-boot-spl.lds"
+
+source "board/ti/common/Kconfig"
+
+endif
diff --git a/board/beagle/beagleplay/MAINTAINERS b/board/beagle/beagleplay/MAINTAINERS
new file mode 100644
index 0000000..eed996a
--- /dev/null
+++ b/board/beagle/beagleplay/MAINTAINERS
@@ -0,0 +1,6 @@
+BEAGLEPLAY BOARD
+M: Nishanth Menon <nm@ti.com>
+M: Robert Nelson <robertcnelson@gmail.com>
+M: Tom Rini <trini@konsulko.com>
+S: Maintained
+N: beagleplay
diff --git a/board/beagle/beagleplay/Makefile b/board/beagle/beagleplay/Makefile
new file mode 100644
index 0000000..b7a3cdb
--- /dev/null
+++ b/board/beagle/beagleplay/Makefile
@@ -0,0 +1,9 @@
+# SPDX-License-Identifier: GPL-2.0+
+#
+# https://beagleboard.org/play
+#
+# Copyright (C) 2022-2023 Texas Instruments Incorporated - https://www.ti.com/
+# Copyright (C) 2022-2023 Robert Nelson, BeagleBoard.org Foundation
+#
+
+obj-y += beagleplay.o
diff --git a/board/beagle/beagleplay/beagleplay.c b/board/beagle/beagleplay/beagleplay.c
new file mode 100644
index 0000000..1c376de
--- /dev/null
+++ b/board/beagle/beagleplay/beagleplay.c
@@ -0,0 +1,29 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * https://beagleplay.org/
+ *
+ * Copyright (C) 2022-2023 Texas Instruments Incorporated - https://www.ti.com/
+ * Copyright (C) 2022-2023 Robert Nelson, BeagleBoard.org Foundation
+ */
+
+#include <cpu_func.h>
+#include <env.h>
+#include <fdt_support.h>
+#include <spl.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+int board_init(void)
+{
+ return 0;
+}
+
+int dram_init(void)
+{
+ return fdtdec_setup_mem_size_base();
+}
+
+int dram_init_banksize(void)
+{
+ return fdtdec_setup_memory_banksize();
+}
diff --git a/board/ti/am62x/beagleplay.env b/board/beagle/beagleplay/beagleplay.env
similarity index 100%
rename from board/ti/am62x/beagleplay.env
rename to board/beagle/beagleplay/beagleplay.env
diff --git a/board/beagle/beagleplay/board-cfg.yaml b/board/beagle/beagleplay/board-cfg.yaml
new file mode 100644
index 0000000..36cfb55
--- /dev/null
+++ b/board/beagle/beagleplay/board-cfg.yaml
@@ -0,0 +1,36 @@
+# SPDX-License-Identifier: GPL-2.0+
+# Copyright (C) 2022-2023 Texas Instruments Incorporated - https://www.ti.com/
+#
+# Board configuration for AM62
+#
+
+---
+
+board-cfg:
+ rev:
+ boardcfg_abi_maj : 0x0
+ boardcfg_abi_min : 0x1
+ control:
+ subhdr:
+ magic: 0xC1D3
+ size: 7
+ main_isolation_enable : 0x5A
+ main_isolation_hostid : 0x2
+ secproxy:
+ subhdr:
+ magic: 0x1207
+ size: 7
+ scaling_factor : 0x1
+ scaling_profile : 0x1
+ disable_main_nav_secure_proxy : 0
+ msmc:
+ subhdr:
+ magic: 0xA5C3
+ size: 5
+ msmc_cache_size : 0x0
+ debug_cfg:
+ subhdr:
+ magic: 0x020C
+ size: 8
+ trace_dst_enables : 0x00
+ trace_src_enables : 0x00
diff --git a/board/beagle/beagleplay/pm-cfg.yaml b/board/beagle/beagleplay/pm-cfg.yaml
new file mode 100644
index 0000000..5d04cf8
--- /dev/null
+++ b/board/beagle/beagleplay/pm-cfg.yaml
@@ -0,0 +1,12 @@
+# SPDX-License-Identifier: GPL-2.0+
+# Copyright (C) 2022-2023 Texas Instruments Incorporated - https://www.ti.com/
+#
+# Power management configuration for AM62
+#
+
+---
+
+pm-cfg:
+ rev:
+ boardcfg_abi_maj : 0x0
+ boardcfg_abi_min : 0x1
diff --git a/board/beagle/beagleplay/rm-cfg.yaml b/board/beagle/beagleplay/rm-cfg.yaml
new file mode 100644
index 0000000..c28707b
--- /dev/null
+++ b/board/beagle/beagleplay/rm-cfg.yaml
@@ -0,0 +1,1088 @@
+# SPDX-License-Identifier: GPL-2.0+
+# Copyright (C) 2022-2023 Texas Instruments Incorporated - https://www.ti.com/
+#
+# Resource management configuration for AM62
+#
+
+---
+
+rm-cfg:
+ rm_boardcfg:
+ rev:
+ boardcfg_abi_maj : 0x0
+ boardcfg_abi_min : 0x1
+ host_cfg:
+ subhdr:
+ magic: 0x4C41
+ size : 356
+ host_cfg_entries:
+ - #1
+ host_id: 12
+ allowed_atype : 0x2A
+ allowed_qos : 0xAAAA
+ allowed_orderid : 0xAAAAAAAA
+ allowed_priority : 0xAAAA
+ allowed_sched_priority : 0xAA
+ - #2
+ host_id: 30
+ allowed_atype : 0x2A
+ allowed_qos : 0xAAAA
+ allowed_orderid : 0xAAAAAAAA
+ allowed_priority : 0xAAAA
+ allowed_sched_priority : 0xAA
+ - #3
+ host_id: 36
+ allowed_atype : 0x2A
+ allowed_qos : 0xAAAA
+ allowed_orderid : 0xAAAAAAAA
+ allowed_priority : 0xAAAA
+ allowed_sched_priority : 0xAA
+ - #4
+ host_id: 0
+ allowed_atype : 0
+ allowed_qos : 0
+ allowed_orderid : 0
+ allowed_priority : 0
+ allowed_sched_priority : 0
+ - #5
+ host_id: 0
+ allowed_atype : 0
+ allowed_qos : 0
+ allowed_orderid : 0
+ allowed_priority : 0
+ allowed_sched_priority : 0
+ - #6
+ host_id: 0
+ allowed_atype : 0
+ allowed_qos : 0
+ allowed_orderid : 0
+ allowed_priority : 0
+ allowed_sched_priority : 0
+ - #7
+ host_id: 0
+ allowed_atype : 0
+ allowed_qos : 0
+ allowed_orderid : 0
+ allowed_priority : 0
+ allowed_sched_priority : 0
+ - #8
+ host_id: 0
+ allowed_atype : 0
+ allowed_qos : 0
+ allowed_orderid : 0
+ allowed_priority : 0
+ allowed_sched_priority : 0
+ - #9
+ host_id: 0
+ allowed_atype : 0
+ allowed_qos : 0
+ allowed_orderid : 0
+ allowed_priority : 0
+ allowed_sched_priority : 0
+ - #10
+ host_id: 0
+ allowed_atype : 0
+ allowed_qos : 0
+ allowed_orderid : 0
+ allowed_priority : 0
+ allowed_sched_priority : 0
+ - #11
+ host_id: 0
+ allowed_atype : 0
+ allowed_qos : 0
+ allowed_orderid : 0
+ allowed_priority : 0
+ allowed_sched_priority : 0
+ - #12
+ host_id: 0
+ allowed_atype : 0
+ allowed_qos : 0
+ allowed_orderid : 0
+ allowed_priority : 0
+ allowed_sched_priority : 0
+ - #13
+ host_id: 0
+ allowed_atype : 0
+ allowed_qos : 0
+ allowed_orderid : 0
+ allowed_priority : 0
+ allowed_sched_priority : 0
+ - #14
+ host_id: 0
+ allowed_atype : 0
+ allowed_qos : 0
+ allowed_orderid : 0
+ allowed_priority : 0
+ allowed_sched_priority : 0
+ - #15
+ host_id: 0
+ allowed_atype : 0
+ allowed_qos : 0
+ allowed_orderid : 0
+ allowed_priority : 0
+ allowed_sched_priority : 0
+ - #16
+ host_id: 0
+ allowed_atype : 0
+ allowed_qos : 0
+ allowed_orderid : 0
+ allowed_priority : 0
+ allowed_sched_priority : 0
+ - #17
+ host_id: 0
+ allowed_atype : 0
+ allowed_qos : 0
+ allowed_orderid : 0
+ allowed_priority : 0
+ allowed_sched_priority : 0
+ - #18
+ host_id: 0
+ allowed_atype : 0
+ allowed_qos : 0
+ allowed_orderid : 0
+ allowed_priority : 0
+ allowed_sched_priority : 0
+ - #19
+ host_id: 0
+ allowed_atype : 0
+ allowed_qos : 0
+ allowed_orderid : 0
+ allowed_priority : 0
+ allowed_sched_priority : 0
+ - #20
+ host_id: 0
+ allowed_atype : 0
+ allowed_qos : 0
+ allowed_orderid : 0
+ allowed_priority : 0
+ allowed_sched_priority : 0
+ - #21
+ host_id: 0
+ allowed_atype : 0
+ allowed_qos : 0
+ allowed_orderid : 0
+ allowed_priority : 0
+ allowed_sched_priority : 0
+ - #22
+ host_id: 0
+ allowed_atype : 0
+ allowed_qos : 0
+ allowed_orderid : 0
+ allowed_priority : 0
+ allowed_sched_priority : 0
+ - #23
+ host_id: 0
+ allowed_atype : 0
+ allowed_qos : 0
+ allowed_orderid : 0
+ allowed_priority : 0
+ allowed_sched_priority : 0
+ - #24
+ host_id: 0
+ allowed_atype : 0
+ allowed_qos : 0
+ allowed_orderid : 0
+ allowed_priority : 0
+ allowed_sched_priority : 0
+ - #25
+ host_id: 0
+ allowed_atype : 0
+ allowed_qos : 0
+ allowed_orderid : 0
+ allowed_priority : 0
+ allowed_sched_priority : 0
+ - #26
+ host_id: 0
+ allowed_atype : 0
+ allowed_qos : 0
+ allowed_orderid : 0
+ allowed_priority : 0
+ allowed_sched_priority : 0
+ - #27
+ host_id: 0
+ allowed_atype : 0
+ allowed_qos : 0
+ allowed_orderid : 0
+ allowed_priority : 0
+ allowed_sched_priority : 0
+ - #28
+ host_id: 0
+ allowed_atype : 0
+ allowed_qos : 0
+ allowed_orderid : 0
+ allowed_priority : 0
+ allowed_sched_priority : 0
+ - #29
+ host_id: 0
+ allowed_atype : 0
+ allowed_qos : 0
+ allowed_orderid : 0
+ allowed_priority : 0
+ allowed_sched_priority : 0
+ - #30
+ host_id: 0
+ allowed_atype : 0
+ allowed_qos : 0
+ allowed_orderid : 0
+ allowed_priority : 0
+ allowed_sched_priority : 0
+ - #31
+ host_id: 0
+ allowed_atype : 0
+ allowed_qos : 0
+ allowed_orderid : 0
+ allowed_priority : 0
+ allowed_sched_priority : 0
+ - #32
+ host_id: 0
+ allowed_atype : 0
+ allowed_qos : 0
+ allowed_orderid : 0
+ allowed_priority : 0
+ allowed_sched_priority : 0
+ resasg:
+ subhdr:
+ magic: 0x7B25
+ size : 8
+ resasg_entries_size: 960
+ reserved : 0
+ resasg_entries:
+ -
+ start_resource: 0
+ num_resource: 16
+ type: 64
+ host_id: 12
+ reserved: 0
+
+ -
+ start_resource: 16
+ num_resource: 4
+ type: 64
+ host_id: 35
+ reserved: 0
+
+ -
+ start_resource: 16
+ num_resource: 4
+ type: 64
+ host_id: 36
+ reserved: 0
+
+ -
+ start_resource: 20
+ num_resource: 22
+ type: 64
+ host_id: 30
+ reserved: 0
+
+ -
+ start_resource: 0
+ num_resource: 16
+ type: 192
+ host_id: 12
+ reserved: 0
+
+ -
+ start_resource: 34
+ num_resource: 2
+ type: 192
+ host_id: 30
+ reserved: 0
+
+ -
+ start_resource: 0
+ num_resource: 4
+ type: 320
+ host_id: 12
+ reserved: 0
+
+ -
+ start_resource: 4
+ num_resource: 4
+ type: 320
+ host_id: 30
+ reserved: 0
+
+ -
+ start_resource: 0
+ num_resource: 26
+ type: 384
+ host_id: 128
+ reserved: 0
+
+ -
+ start_resource: 50176
+ num_resource: 164
+ type: 1666
+ host_id: 128
+ reserved: 0
+
+ -
+ start_resource: 0
+ num_resource: 1
+ type: 1667
+ host_id: 128
+ reserved: 0
+
+ -
+ start_resource: 0
+ num_resource: 18
+ type: 1677
+ host_id: 12
+ reserved: 0
+
+ -
+ start_resource: 18
+ num_resource: 6
+ type: 1677
+ host_id: 35
+ reserved: 0
+
+ -
+ start_resource: 18
+ num_resource: 6
+ type: 1677
+ host_id: 36
+ reserved: 0
+
+ -
+ start_resource: 24
+ num_resource: 2
+ type: 1677
+ host_id: 30
+ reserved: 0
+
+ -
+ start_resource: 26
+ num_resource: 6
+ type: 1677
+ host_id: 128
+ reserved: 0
+
+ -
+ start_resource: 54
+ num_resource: 18
+ type: 1678
+ host_id: 12
+ reserved: 0
+
+ -
+ start_resource: 72
+ num_resource: 6
+ type: 1678
+ host_id: 35
+ reserved: 0
+
+ -
+ start_resource: 72
+ num_resource: 6
+ type: 1678
+ host_id: 36
+ reserved: 0
+
+ -
+ start_resource: 78
+ num_resource: 2
+ type: 1678
+ host_id: 30
+ reserved: 0
+
+ -
+ start_resource: 80
+ num_resource: 2
+ type: 1678
+ host_id: 128
+ reserved: 0
+
+ -
+ start_resource: 32
+ num_resource: 12
+ type: 1679
+ host_id: 12
+ reserved: 0
+
+ -
+ start_resource: 44
+ num_resource: 6
+ type: 1679
+ host_id: 35
+ reserved: 0
+
+ -
+ start_resource: 44
+ num_resource: 6
+ type: 1679
+ host_id: 36
+ reserved: 0
+
+ -
+ start_resource: 50
+ num_resource: 2
+ type: 1679
+ host_id: 30
+ reserved: 0
+
+ -
+ start_resource: 52
+ num_resource: 2
+ type: 1679
+ host_id: 128
+ reserved: 0
+
+ -
+ start_resource: 0
+ num_resource: 18
+ type: 1696
+ host_id: 12
+ reserved: 0
+
+ -
+ start_resource: 18
+ num_resource: 6
+ type: 1696
+ host_id: 35
+ reserved: 0
+
+ -
+ start_resource: 18
+ num_resource: 6
+ type: 1696
+ host_id: 36
+ reserved: 0
+
+ -
+ start_resource: 24
+ num_resource: 2
+ type: 1696
+ host_id: 30
+ reserved: 0
+
+ -
+ start_resource: 26
+ num_resource: 6
+ type: 1696
+ host_id: 128
+ reserved: 0
+
+ -
+ start_resource: 0
+ num_resource: 18
+ type: 1697
+ host_id: 12
+ reserved: 0
+
+ -
+ start_resource: 18
+ num_resource: 6
+ type: 1697
+ host_id: 35
+ reserved: 0
+
+ -
+ start_resource: 18
+ num_resource: 6
+ type: 1697
+ host_id: 36
+ reserved: 0
+
+ -
+ start_resource: 24
+ num_resource: 2
+ type: 1697
+ host_id: 30
+ reserved: 0
+
+ -
+ start_resource: 26
+ num_resource: 2
+ type: 1697
+ host_id: 128
+ reserved: 0
+
+ -
+ start_resource: 0
+ num_resource: 12
+ type: 1698
+ host_id: 12
+ reserved: 0
+
+ -
+ start_resource: 12
+ num_resource: 6
+ type: 1698
+ host_id: 35
+ reserved: 0
+
+ -
+ start_resource: 12
+ num_resource: 6
+ type: 1698
+ host_id: 36
+ reserved: 0
+
+ -
+ start_resource: 18
+ num_resource: 2
+ type: 1698
+ host_id: 30
+ reserved: 0
+
+ -
+ start_resource: 20
+ num_resource: 2
+ type: 1698
+ host_id: 128
+ reserved: 0
+
+ -
+ start_resource: 5
+ num_resource: 35
+ type: 1802
+ host_id: 12
+ reserved: 0
+
+ -
+ start_resource: 44
+ num_resource: 36
+ type: 1802
+ host_id: 35
+ reserved: 0
+
+ -
+ start_resource: 44
+ num_resource: 36
+ type: 1802
+ host_id: 36
+ reserved: 0
+
+ -
+ start_resource: 168
+ num_resource: 8
+ type: 1802
+ host_id: 30
+ reserved: 0
+
+ -
+ start_resource: 13
+ num_resource: 512
+ type: 1805
+ host_id: 12
+ reserved: 0
+
+ -
+ start_resource: 525
+ num_resource: 256
+ type: 1805
+ host_id: 35
+ reserved: 0
+
+ -
+ start_resource: 525
+ num_resource: 256
+ type: 1805
+ host_id: 36
+ reserved: 0
+
+ -
+ start_resource: 781
+ num_resource: 128
+ type: 1805
+ host_id: 30
+ reserved: 0
+
+ -
+ start_resource: 909
+ num_resource: 627
+ type: 1805
+ host_id: 128
+ reserved: 0
+
+ -
+ start_resource: 0
+ num_resource: 1024
+ type: 1807
+ host_id: 128
+ reserved: 0
+
+ -
+ start_resource: 4096
+ num_resource: 29
+ type: 1808
+ host_id: 128
+ reserved: 0
+
+ -
+ start_resource: 4608
+ num_resource: 99
+ type: 1809
+ host_id: 128
+ reserved: 0
+
+ -
+ start_resource: 5120
+ num_resource: 24
+ type: 1810
+ host_id: 128
+ reserved: 0
+
+ -
+ start_resource: 5632
+ num_resource: 51
+ type: 1811
+ host_id: 128
+ reserved: 0
+
+ -
+ start_resource: 6144
+ num_resource: 51
+ type: 1812
+ host_id: 128
+ reserved: 0
+
+ -
+ start_resource: 6656
+ num_resource: 51
+ type: 1813
+ host_id: 128
+ reserved: 0
+
+ -
+ start_resource: 8192
+ num_resource: 32
+ type: 1814
+ host_id: 128
+ reserved: 0
+
+ -
+ start_resource: 8704
+ num_resource: 32
+ type: 1815
+ host_id: 128
+ reserved: 0
+
+ -
+ start_resource: 9216
+ num_resource: 32
+ type: 1816
+ host_id: 128
+ reserved: 0
+
+ -
+ start_resource: 9728
+ num_resource: 22
+ type: 1817
+ host_id: 128
+ reserved: 0
+
+ -
+ start_resource: 10240
+ num_resource: 22
+ type: 1818
+ host_id: 128
+ reserved: 0
+
+ -
+ start_resource: 10752
+ num_resource: 22
+ type: 1819
+ host_id: 128
+ reserved: 0
+
+ -
+ start_resource: 11264
+ num_resource: 28
+ type: 1820
+ host_id: 128
+ reserved: 0
+
+ -
+ start_resource: 11776
+ num_resource: 28
+ type: 1821
+ host_id: 128
+ reserved: 0
+
+ -
+ start_resource: 12288
+ num_resource: 28
+ type: 1822
+ host_id: 128
+ reserved: 0
+
+ -
+ start_resource: 0
+ num_resource: 1
+ type: 1923
+ host_id: 128
+ reserved: 0
+
+ -
+ start_resource: 0
+ num_resource: 10
+ type: 1936
+ host_id: 12
+ reserved: 0
+
+ -
+ start_resource: 10
+ num_resource: 3
+ type: 1936
+ host_id: 35
+ reserved: 0
+
+ -
+ start_resource: 10
+ num_resource: 3
+ type: 1936
+ host_id: 36
+ reserved: 0
+
+ -
+ start_resource: 13
+ num_resource: 3
+ type: 1936
+ host_id: 30
+ reserved: 0
+
+ -
+ start_resource: 16
+ num_resource: 3
+ type: 1936
+ host_id: 128
+ reserved: 0
+
+ -
+ start_resource: 19
+ num_resource: 64
+ type: 1937
+ host_id: 12
+ reserved: 0
+
+ -
+ start_resource: 19
+ num_resource: 64
+ type: 1937
+ host_id: 36
+ reserved: 0
+
+ -
+ start_resource: 83
+ num_resource: 8
+ type: 1938
+ host_id: 12
+ reserved: 0
+
+ -
+ start_resource: 91
+ num_resource: 8
+ type: 1939
+ host_id: 12
+ reserved: 0
+
+ -
+ start_resource: 99
+ num_resource: 10
+ type: 1942
+ host_id: 12
+ reserved: 0
+
+ -
+ start_resource: 109
+ num_resource: 3
+ type: 1942
+ host_id: 35
+ reserved: 0
+
+ -
+ start_resource: 109
+ num_resource: 3
+ type: 1942
+ host_id: 36
+ reserved: 0
+
+ -
+ start_resource: 112
+ num_resource: 3
+ type: 1942
+ host_id: 30
+ reserved: 0
+
+ -
+ start_resource: 115
+ num_resource: 3
+ type: 1942
+ host_id: 128
+ reserved: 0
+
+ -
+ start_resource: 118
+ num_resource: 16
+ type: 1943
+ host_id: 12
+ reserved: 0
+
+ -
+ start_resource: 118
+ num_resource: 16
+ type: 1943
+ host_id: 36
+ reserved: 0
+
+ -
+ start_resource: 134
+ num_resource: 8
+ type: 1944
+ host_id: 12
+ reserved: 0
+
+ -
+ start_resource: 134
+ num_resource: 8
+ type: 1945
+ host_id: 12
+ reserved: 0
+
+ -
+ start_resource: 142
+ num_resource: 8
+ type: 1946
+ host_id: 12
+ reserved: 0
+
+ -
+ start_resource: 142
+ num_resource: 8
+ type: 1947
+ host_id: 12
+ reserved: 0
+
+ -
+ start_resource: 0
+ num_resource: 10
+ type: 1955
+ host_id: 12
+ reserved: 0
+
+ -
+ start_resource: 10
+ num_resource: 3
+ type: 1955
+ host_id: 35
+ reserved: 0
+
+ -
+ start_resource: 10
+ num_resource: 3
+ type: 1955
+ host_id: 36
+ reserved: 0
+
+ -
+ start_resource: 13
+ num_resource: 3
+ type: 1955
+ host_id: 30
+ reserved: 0
+
+ -
+ start_resource: 16
+ num_resource: 3
+ type: 1955
+ host_id: 128
+ reserved: 0
+
+ -
+ start_resource: 19
+ num_resource: 8
+ type: 1956
+ host_id: 12
+ reserved: 0
+
+ -
+ start_resource: 19
+ num_resource: 8
+ type: 1956
+ host_id: 36
+ reserved: 0
+
+ -
+ start_resource: 27
+ num_resource: 1
+ type: 1957
+ host_id: 12
+ reserved: 0
+
+ -
+ start_resource: 28
+ num_resource: 1
+ type: 1958
+ host_id: 12
+ reserved: 0
+
+ -
+ start_resource: 0
+ num_resource: 10
+ type: 1961
+ host_id: 12
+ reserved: 0
+
+ -
+ start_resource: 10
+ num_resource: 3
+ type: 1961
+ host_id: 35
+ reserved: 0
+
+ -
+ start_resource: 10
+ num_resource: 3
+ type: 1961
+ host_id: 36
+ reserved: 0
+
+ -
+ start_resource: 13
+ num_resource: 3
+ type: 1961
+ host_id: 30
+ reserved: 0
+
+ -
+ start_resource: 16
+ num_resource: 3
+ type: 1961
+ host_id: 128
+ reserved: 0
+
+ -
+ start_resource: 0
+ num_resource: 10
+ type: 1962
+ host_id: 12
+ reserved: 0
+
+ -
+ start_resource: 10
+ num_resource: 3
+ type: 1962
+ host_id: 35
+ reserved: 0
+
+ -
+ start_resource: 10
+ num_resource: 3
+ type: 1962
+ host_id: 36
+ reserved: 0
+
+ -
+ start_resource: 13
+ num_resource: 3
+ type: 1962
+ host_id: 30
+ reserved: 0
+
+ -
+ start_resource: 16
+ num_resource: 3
+ type: 1962
+ host_id: 128
+ reserved: 0
+
+ -
+ start_resource: 19
+ num_resource: 1
+ type: 1963
+ host_id: 12
+ reserved: 0
+
+ -
+ start_resource: 19
+ num_resource: 1
+ type: 1963
+ host_id: 36
+ reserved: 0
+
+ -
+ start_resource: 19
+ num_resource: 16
+ type: 1964
+ host_id: 12
+ reserved: 0
+
+ -
+ start_resource: 19
+ num_resource: 16
+ type: 1964
+ host_id: 36
+ reserved: 0
+
+ -
+ start_resource: 20
+ num_resource: 1
+ type: 1965
+ host_id: 12
+ reserved: 0
+
+ -
+ start_resource: 35
+ num_resource: 8
+ type: 1966
+ host_id: 12
+ reserved: 0
+
+ -
+ start_resource: 21
+ num_resource: 1
+ type: 1967
+ host_id: 12
+ reserved: 0
+
+ -
+ start_resource: 35
+ num_resource: 8
+ type: 1968
+ host_id: 12
+ reserved: 0
+
+ -
+ start_resource: 22
+ num_resource: 1
+ type: 1969
+ host_id: 12
+ reserved: 0
+
+ -
+ start_resource: 43
+ num_resource: 8
+ type: 1970
+ host_id: 12
+ reserved: 0
+
+ -
+ start_resource: 23
+ num_resource: 1
+ type: 1971
+ host_id: 12
+ reserved: 0
+
+ -
+ start_resource: 43
+ num_resource: 8
+ type: 1972
+ host_id: 12
+ reserved: 0
+
+ -
+ start_resource: 0
+ num_resource: 1
+ type: 2112
+ host_id: 128
+ reserved: 0
+
+ -
+ start_resource: 2
+ num_resource: 2
+ type: 2122
+ host_id: 12
+ reserved: 0
diff --git a/board/beagle/beagleplay/sec-cfg.yaml b/board/beagle/beagleplay/sec-cfg.yaml
new file mode 100644
index 0000000..07081ce
--- /dev/null
+++ b/board/beagle/beagleplay/sec-cfg.yaml
@@ -0,0 +1,379 @@
+# SPDX-License-Identifier: GPL-2.0+
+# Copyright (C) 2022-2023 Texas Instruments Incorporated - https://www.ti.com/
+#
+# Security management configuration for AM62
+#
+
+---
+
+sec-cfg:
+ rev:
+ boardcfg_abi_maj : 0x0
+ boardcfg_abi_min : 0x1
+ processor_acl_list:
+ subhdr:
+ magic: 0xF1EA
+ size: 164
+ proc_acl_entries:
+ - #1
+ processor_id: 0
+ proc_access_master: 0
+ proc_access_secondary: [0, 0, 0]
+ - #2
+ processor_id: 0
+ proc_access_master: 0
+ proc_access_secondary: [0, 0, 0]
+ - #3
+ processor_id: 0
+ proc_access_master: 0
+ proc_access_secondary: [0, 0, 0]
+ - #4
+ processor_id: 0
+ proc_access_master: 0
+ proc_access_secondary: [0, 0, 0]
+ - #5
+ processor_id: 0
+ proc_access_master: 0
+ proc_access_secondary: [0, 0, 0]
+ - #6
+ processor_id: 0
+ proc_access_master: 0
+ proc_access_secondary: [0, 0, 0]
+ - #7
+ processor_id: 0
+ proc_access_master: 0
+ proc_access_secondary: [0, 0, 0]
+ - #8
+ processor_id: 0
+ proc_access_master: 0
+ proc_access_secondary: [0, 0, 0]
+ - #9
+ processor_id: 0
+ proc_access_master: 0
+ proc_access_secondary: [0, 0, 0]
+ - #10
+ processor_id: 0
+ proc_access_master: 0
+ proc_access_secondary: [0, 0, 0]
+ - #11
+ processor_id: 0
+ proc_access_master: 0
+ proc_access_secondary: [0, 0, 0]
+ - #12
+ processor_id: 0
+ proc_access_master: 0
+ proc_access_secondary: [0, 0, 0]
+ - #13
+ processor_id: 0
+ proc_access_master: 0
+ proc_access_secondary: [0, 0, 0]
+ - #14
+ processor_id: 0
+ proc_access_master: 0
+ proc_access_secondary: [0, 0, 0]
+ - #15
+ processor_id: 0
+ proc_access_master: 0
+ proc_access_secondary: [0, 0, 0]
+ - #16
+ processor_id: 0
+ proc_access_master: 0
+ proc_access_secondary: [0, 0, 0]
+ - #17
+ processor_id: 0
+ proc_access_master: 0
+ proc_access_secondary: [0, 0, 0]
+ - #18
+ processor_id: 0
+ proc_access_master: 0
+ proc_access_secondary: [0, 0, 0]
+ - #19
+ processor_id: 0
+ proc_access_master: 0
+ proc_access_secondary: [0, 0, 0]
+ - #20
+ processor_id: 0
+ proc_access_master: 0
+ proc_access_secondary: [0, 0, 0]
+ - #21
+ processor_id: 0
+ proc_access_master: 0
+ proc_access_secondary: [0, 0, 0]
+ - #22
+ processor_id: 0
+ proc_access_master: 0
+ proc_access_secondary: [0, 0, 0]
+ - #23
+ processor_id: 0
+ proc_access_master: 0
+ proc_access_secondary: [0, 0, 0]
+ - #24
+ processor_id: 0
+ proc_access_master: 0
+ proc_access_secondary: [0, 0, 0]
+ - #25
+ processor_id: 0
+ proc_access_master: 0
+ proc_access_secondary: [0, 0, 0]
+ - #26
+ processor_id: 0
+ proc_access_master: 0
+ proc_access_secondary: [0, 0, 0]
+ - #27
+ processor_id: 0
+ proc_access_master: 0
+ proc_access_secondary: [0, 0, 0]
+ - #28
+ processor_id: 0
+ proc_access_master: 0
+ proc_access_secondary: [0, 0, 0]
+ - #29
+ processor_id: 0
+ proc_access_master: 0
+ proc_access_secondary: [0, 0, 0]
+ - #30
+ processor_id: 0
+ proc_access_master: 0
+ proc_access_secondary: [0, 0, 0]
+ - #31
+ processor_id: 0
+ proc_access_master: 0
+ proc_access_secondary: [0, 0, 0]
+ - #32
+ processor_id: 0
+ proc_access_master: 0
+ proc_access_secondary: [0, 0, 0]
+ host_hierarchy:
+ subhdr:
+ magic: 0x8D27
+ size: 68
+ host_hierarchy_entries:
+ - #1
+ host_id: 0
+ supervisor_host_id: 0
+ - #2
+ host_id: 0
+ supervisor_host_id: 0
+ - #3
+ host_id: 0
+ supervisor_host_id: 0
+ - #4
+ host_id: 0
+ supervisor_host_id: 0
+ - #5
+ host_id: 0
+ supervisor_host_id: 0
+ - #6
+ host_id: 0
+ supervisor_host_id: 0
+ - #7
+ host_id: 0
+ supervisor_host_id: 0
+ - #8
+ host_id: 0
+ supervisor_host_id: 0
+ - #9
+ host_id: 0
+ supervisor_host_id: 0
+ - #10
+ host_id: 0
+ supervisor_host_id: 0
+ - #11
+ host_id: 0
+ supervisor_host_id: 0
+ - #12
+ host_id: 0
+ supervisor_host_id: 0
+ - #13
+ host_id: 0
+ supervisor_host_id: 0
+ - #14
+ host_id: 0
+ supervisor_host_id: 0
+ - #15
+ host_id: 0
+ supervisor_host_id: 0
+ - #16
+ host_id: 0
+ supervisor_host_id: 0
+ - #17
+ host_id: 0
+ supervisor_host_id: 0
+ - #18
+ host_id: 0
+ supervisor_host_id: 0
+ - #19
+ host_id: 0
+ supervisor_host_id: 0
+ - #20
+ host_id: 0
+ supervisor_host_id: 0
+ - #21
+ host_id: 0
+ supervisor_host_id: 0
+ - #22
+ host_id: 0
+ supervisor_host_id: 0
+ - #23
+ host_id: 0
+ supervisor_host_id: 0
+ - #24
+ host_id: 0
+ supervisor_host_id: 0
+ - #25
+ host_id: 0
+ supervisor_host_id: 0
+ - #26
+ host_id: 0
+ supervisor_host_id: 0
+ - #27
+ host_id: 0
+ supervisor_host_id: 0
+ - #28
+ host_id: 0
+ supervisor_host_id: 0
+ - #29
+ host_id: 0
+ supervisor_host_id: 0
+ - #30
+ host_id: 0
+ supervisor_host_id: 0
+ - #31
+ host_id: 0
+ supervisor_host_id: 0
+ - #32
+ host_id: 0
+ supervisor_host_id: 0
+ otp_config:
+ subhdr:
+ magic: 0x4081
+ size: 69
+ write_host_id : 0
+ otp_entry:
+ - #1
+ host_id: 0
+ host_perms: 0
+ - #2
+ host_id: 0
+ host_perms: 0
+ - #3
+ host_id: 0
+ host_perms: 0
+ - #4
+ host_id: 0
+ host_perms: 0
+ - #5
+ host_id: 0
+ host_perms: 0
+ - #6
+ host_id: 0
+ host_perms: 0
+ - #7
+ host_id: 0
+ host_perms: 0
+ - #8
+ host_id: 0
+ host_perms: 0
+ - #9
+ host_id: 0
+ host_perms: 0
+ - #10
+ host_id: 0
+ host_perms: 0
+ - #11
+ host_id: 0
+ host_perms: 0
+ - #12
+ host_id: 0
+ host_perms: 0
+ - #13
+ host_id: 0
+ host_perms: 0
+ - #14
+ host_id: 0
+ host_perms: 0
+ - #15
+ host_id: 0
+ host_perms: 0
+ - #16
+ host_id: 0
+ host_perms: 0
+ - #17
+ host_id: 0
+ host_perms: 0
+ - #18
+ host_id: 0
+ host_perms: 0
+ - #19
+ host_id: 0
+ host_perms: 0
+ - #20
+ host_id: 0
+ host_perms: 0
+ - #21
+ host_id: 0
+ host_perms: 0
+ - #22
+ host_id: 0
+ host_perms: 0
+ - #23
+ host_id: 0
+ host_perms: 0
+ - #24
+ host_id: 0
+ host_perms: 0
+ - #25
+ host_id: 0
+ host_perms: 0
+ - #26
+ host_id: 0
+ host_perms: 0
+ - #27
+ host_id: 0
+ host_perms: 0
+ - #28
+ host_id: 0
+ host_perms: 0
+ - #29
+ host_id: 0
+ host_perms: 0
+ - #30
+ host_id: 0
+ host_perms: 0
+ - #31
+ host_id: 0
+ host_perms: 0
+ - #32
+ host_id: 0
+ host_perms: 0
+ dkek_config:
+ subhdr:
+ magic: 0x5170
+ size: 12
+ allowed_hosts: [128, 0, 0, 0]
+ allow_dkek_export_tisci : 0x5A
+ rsvd: [0, 0, 0]
+ sa2ul_cfg:
+ subhdr:
+ magic: 0x23BE
+ size : 0
+ auth_resource_owner: 0
+ enable_saul_psil_global_config_writes: 0x5A
+ rsvd: [0, 0]
+ sec_dbg_config:
+ subhdr:
+ magic: 0x42AF
+ size: 16
+ allow_jtag_unlock : 0x5A
+ allow_wildcard_unlock : 0x5A
+ allowed_debug_level_rsvd: 0
+ rsvd: 0
+ min_cert_rev : 0x0
+ jtag_unlock_hosts: [0, 0, 0, 0]
+ sec_handover_cfg:
+ subhdr:
+ magic: 0x608F
+ size: 10
+ handover_msg_sender : 0
+ handover_to_host_id : 0
+ rsvd: [0, 0, 0, 0]
diff --git a/board/bosch/guardian/board.c b/board/bosch/guardian/board.c
index c31e2c8..ee9e6d6 100644
--- a/board/bosch/guardian/board.c
+++ b/board/bosch/guardian/board.c
@@ -4,7 +4,7 @@
*
* Board functions for Bosch Guardian
*
- * Copyright (C) 2011, Texas Instruments, Incorporated - http://www.ti.com/
+ * Copyright (C) 2011, Texas Instruments, Incorporated - https://www.ti.com/
* Copyright (C) 2018 Robert Bosch Power Tools GmbH
*/
diff --git a/board/bosch/guardian/board.h b/board/bosch/guardian/board.h
index b301caf..e1e8c0c 100644
--- a/board/bosch/guardian/board.h
+++ b/board/bosch/guardian/board.h
@@ -4,7 +4,7 @@
*
* Board header for Bosch Guardian
*
- * Copyright (C) 2011, Texas Instruments, Incorporated - http://www.ti.com/
+ * Copyright (C) 2011, Texas Instruments, Incorporated - https://www.ti.com/
* Copyright (C) 2018 Robert Bosch Power Tools GmbH
*/
diff --git a/board/bosch/guardian/mux.c b/board/bosch/guardian/mux.c
index 12c3eb6..53850ff 100644
--- a/board/bosch/guardian/mux.c
+++ b/board/bosch/guardian/mux.c
@@ -2,7 +2,7 @@
/*
* mux.c
*
- * Copyright (C) 2011, Texas Instruments, Incorporated - http://www.ti.com/
+ * Copyright (C) 2011, Texas Instruments, Incorporated - https://www.ti.com/
* Copyright (C) 2018 Robert Bosch Power Tools GmbH
*/
diff --git a/board/bosch/shc/Makefile b/board/bosch/shc/Makefile
index 93f2df3..bac12ed 100644
--- a/board/bosch/shc/Makefile
+++ b/board/bosch/shc/Makefile
@@ -2,7 +2,7 @@
#
# Makefile
#
-# Copyright (C) 2011 Texas Instruments Incorporated - http://www.ti.com/
+# Copyright (C) 2011 Texas Instruments Incorporated - https://www.ti.com/
obj-y := mux.o
obj-y += board.o
diff --git a/board/bosch/shc/board.c b/board/bosch/shc/board.c
index e3a9c00..962a485 100644
--- a/board/bosch/shc/board.c
+++ b/board/bosch/shc/board.c
@@ -8,7 +8,7 @@
* Based on:
* Board functions for TI AM335X based boards
*
- * Copyright (C) 2011, Texas Instruments, Incorporated - http://www.ti.com/
+ * Copyright (C) 2011, Texas Instruments, Incorporated - https://www.ti.com/
*/
#include <common.h>
diff --git a/board/bosch/shc/board.h b/board/bosch/shc/board.h
index 997595b..4cc02f9 100644
--- a/board/bosch/shc/board.h
+++ b/board/bosch/shc/board.h
@@ -8,7 +8,7 @@
* Based on:
* TI AM335x boards information header
*
- * Copyright (C) 2011, Texas Instruments, Incorporated - http://www.ti.com/
+ * Copyright (C) 2011, Texas Instruments, Incorporated - https://www.ti.com/
*/
#ifndef _BOARD_H_
diff --git a/board/bosch/shc/mux.c b/board/bosch/shc/mux.c
index 0a97eaf..f19d186 100644
--- a/board/bosch/shc/mux.c
+++ b/board/bosch/shc/mux.c
@@ -6,7 +6,7 @@
* Heiko Schocher, DENX Software Engineering, hs@denx.de.
*
* Based on:
- * Copyright (C) 2011 Texas Instruments Incorporated - http://www.ti.com/
+ * Copyright (C) 2011 Texas Instruments Incorporated - https://www.ti.com/
*/
#include <common.h>
diff --git a/board/coreboot/coreboot/Makefile b/board/coreboot/coreboot/Makefile
index d292b70..75bfbd1 100644
--- a/board/coreboot/coreboot/Makefile
+++ b/board/coreboot/coreboot/Makefile
@@ -11,3 +11,4 @@
# Daniel Engström, Omicron Ceti AB, daniel@omicron.se.
obj-y += coreboot.o
+obj-$(CONFIG_$(SPL_TPL_)SMBIOS_PARSER) += sysinfo.o
diff --git a/board/coreboot/coreboot/coreboot.c b/board/coreboot/coreboot/coreboot.c
index db855c1..e58dce3 100644
--- a/board/coreboot/coreboot/coreboot.c
+++ b/board/coreboot/coreboot/coreboot.c
@@ -23,50 +23,6 @@
return 0;
}
-#ifdef CONFIG_SMBIOS_PARSER
-int show_board_info(void)
-{
- const struct smbios_entry *smbios = smbios_entry(lib_sysinfo.smbios_start, lib_sysinfo.smbios_size);
-
- if (!smbios)
- goto fallback;
-
- const struct smbios_header *bios = smbios_header(smbios, SMBIOS_BIOS_INFORMATION);
- const struct smbios_header *system = smbios_header(smbios, SMBIOS_SYSTEM_INFORMATION);
- const struct smbios_type0 *t0 = (struct smbios_type0 *)bios;
- const struct smbios_type1 *t1 = (struct smbios_type1 *)system;
-
- if (!t0 || !t1)
- goto fallback;
-
- const char *bios_ver = smbios_string(bios, t0->bios_ver);
- const char *bios_date = smbios_string(bios, t0->bios_release_date);
- const char *model = smbios_string(system, t1->product_name);
- const char *manufacturer = smbios_string(system, t1->manufacturer);
-
- if (!model || !manufacturer || !bios_ver)
- goto fallback;
-
- printf("Vendor: %s\n", manufacturer);
- printf("Model: %s\n", model);
- printf("BIOS Version: %s\n", bios_ver);
- if (bios_date)
- printf("BIOS date: %s\n", bios_date);
-
- return 0;
-
-fallback:
- if (IS_ENABLED(CONFIG_OF_CONTROL)) {
- model = fdt_getprop(gd->fdt_blob, 0, "model", NULL);
-
- if (model)
- printf("Model: %s\n", model);
- }
-
- return checkboard();
-}
-#endif
-
static struct splash_location coreboot_splash_locations[] = {
{
.name = "virtio_fs",
diff --git a/board/coreboot/coreboot/sysinfo.c b/board/coreboot/coreboot/sysinfo.c
new file mode 100644
index 0000000..e0bdc7a
--- /dev/null
+++ b/board/coreboot/coreboot/sysinfo.c
@@ -0,0 +1,89 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * coreboot sysinfo driver
+ *
+ * Copyright 2023 Google LLC
+ * Written by Simon Glass <sjg@chromium.org>
+ */
+
+#include <dm.h>
+#include <smbios.h>
+#include <sysinfo.h>
+#include <asm/cb_sysinfo.h>
+
+struct cb_sysinfo_priv {
+ const struct smbios_header *bios;
+ const struct smbios_header *system;
+ const struct smbios_type0 *t0;
+ const struct smbios_type1 *t1;
+};
+
+static int cb_get_str(struct udevice *dev, int id, size_t size, char *val)
+{
+ struct cb_sysinfo_priv *priv = dev_get_priv(dev);
+ const char *str = NULL;
+
+ switch (id) {
+ case SYSINFO_ID_BOARD_MODEL:
+ if (priv->t1)
+ str = smbios_string(priv->system,
+ priv->t1->product_name);
+ break;
+ case SYSINFO_ID_BOARD_MANUFACTURER:
+ if (priv->t1)
+ str = smbios_string(priv->system,
+ priv->t1->manufacturer);
+ break;
+ case SYSINFO_ID_PRIOR_STAGE_VERSION:
+ if (priv->t0)
+ str = smbios_string(priv->bios, priv->t0->bios_ver);
+ break;
+ case SYSINFO_ID_PRIOR_STAGE_DATE:
+ if (priv->t0)
+ str = smbios_string(priv->bios,
+ priv->t0->bios_release_date);
+ break;
+ }
+ if (!str)
+ return -ENOTSUPP;
+
+ strlcpy(val, str, size);
+
+ return 0;
+}
+
+static int cb_detect(struct udevice *dev)
+{
+ struct cb_sysinfo_priv *priv = dev_get_priv(dev);
+ const struct smbios_entry *smbios;
+
+ smbios = smbios_entry(lib_sysinfo.smbios_start,
+ lib_sysinfo.smbios_size);
+ if (!smbios)
+ return 0;
+
+ priv->bios = smbios_header(smbios, SMBIOS_BIOS_INFORMATION);
+ priv->system = smbios_header(smbios, SMBIOS_SYSTEM_INFORMATION);
+ priv->t0 = (struct smbios_type0 *)priv->bios;
+ priv->t1 = (struct smbios_type1 *)priv->system;
+
+ return 0;
+}
+
+static const struct udevice_id sysinfo_coreboot_ids[] = {
+ { .compatible = "coreboot,sysinfo" },
+ { /* sentinel */ }
+};
+
+static const struct sysinfo_ops sysinfo_coreboot_ops = {
+ .detect = cb_detect,
+ .get_str = cb_get_str,
+};
+
+U_BOOT_DRIVER(sysinfo_coreboot) = {
+ .name = "sysinfo_coreboot",
+ .id = UCLASS_SYSINFO,
+ .of_match = sysinfo_coreboot_ids,
+ .ops = &sysinfo_coreboot_ops,
+ .priv_auto = sizeof(struct cb_sysinfo_priv),
+};
diff --git a/board/cssi/cmpc885/cmpc885.c b/board/cssi/cmpc885/cmpc885.c
index 5e6aa8b..e11cfaf 100644
--- a/board/cssi/cmpc885/cmpc885.c
+++ b/board/cssi/cmpc885/cmpc885.c
@@ -9,7 +9,6 @@
*/
#include <env.h>
-#include <common.h>
#include <mpc8xx.h>
#include <asm/cpm_8xx.h>
#include <asm/io.h>
diff --git a/board/cssi/cmpc885/nand.c b/board/cssi/cmpc885/nand.c
index 3810004..b8989f2 100644
--- a/board/cssi/cmpc885/nand.c
+++ b/board/cssi/cmpc885/nand.c
@@ -7,7 +7,6 @@
*/
#include <config.h>
-#include <common.h>
#include <nand.h>
#include <linux/bitops.h>
#include <linux/mtd/rawnand.h>
diff --git a/board/cssi/cmpc885/sdram.c b/board/cssi/cmpc885/sdram.c
index 7349b85..11a50c3 100644
--- a/board/cssi/cmpc885/sdram.c
+++ b/board/cssi/cmpc885/sdram.c
@@ -4,13 +4,14 @@
* Charles Frey <charles.frey@c-s.fr>
*/
-#include <common.h>
#include <linux/sizes.h>
#include <linux/delay.h>
#include <init.h>
#include <asm/io.h>
#include <mpc8xx.h>
#include <watchdog.h>
+#include <asm/ppc.h>
+#include <asm/immap_8xx.h>
DECLARE_GLOBAL_DATA_PTR;
diff --git a/board/cssi/cmpcpro/cmpcpro.c b/board/cssi/cmpcpro/cmpcpro.c
index 8a30c48..ef30412 100644
--- a/board/cssi/cmpcpro/cmpcpro.c
+++ b/board/cssi/cmpcpro/cmpcpro.c
@@ -4,7 +4,6 @@
*/
#include <command.h>
-#include <common.h>
#include <dm.h>
#include <env.h>
#include <env_internal.h>
diff --git a/board/cssi/mcr3000/mcr3000.c b/board/cssi/mcr3000/mcr3000.c
index 3514f67..8857c9e 100644
--- a/board/cssi/mcr3000/mcr3000.c
+++ b/board/cssi/mcr3000/mcr3000.c
@@ -7,7 +7,6 @@
* Board specific routines for the MCR3000 board
*/
-#include <common.h>
#include <env.h>
#include <hwconfig.h>
#include <init.h>
diff --git a/board/cssi/mcr3000/nand.c b/board/cssi/mcr3000/nand.c
index 11aca4f..5b01d30 100644
--- a/board/cssi/mcr3000/nand.c
+++ b/board/cssi/mcr3000/nand.c
@@ -6,7 +6,6 @@
*/
#include <config.h>
-#include <common.h>
#include <nand.h>
#include <linux/mtd/rawnand.h>
#include <asm/io.h>
diff --git a/board/davinci/da8xxevm/da850evm.c b/board/davinci/da8xxevm/da850evm.c
index 474dca7..05053a8 100644
--- a/board/davinci/da8xxevm/da850evm.c
+++ b/board/davinci/da8xxevm/da850evm.c
@@ -1,6 +1,6 @@
// SPDX-License-Identifier: GPL-2.0+
/*
- * Copyright (C) 2010 Texas Instruments Incorporated - http://www.ti.com/
+ * Copyright (C) 2010 Texas Instruments Incorporated - https://www.ti.com/
*
* Based on da830evm.c. Original Copyrights follow:
*
diff --git a/board/davinci/da8xxevm/omapl138_lcdk.c b/board/davinci/da8xxevm/omapl138_lcdk.c
index 5ffd420..9738e2b 100644
--- a/board/davinci/da8xxevm/omapl138_lcdk.c
+++ b/board/davinci/da8xxevm/omapl138_lcdk.c
@@ -1,6 +1,6 @@
// SPDX-License-Identifier: GPL-2.0+
/*
- * Copyright (C) 2012 Texas Instruments Incorporated - http://www.ti.com/
+ * Copyright (C) 2012 Texas Instruments Incorporated - https://www.ti.com/
*
* Based on da850evm.c. Original Copyrights follow:
*
diff --git a/board/eets/pdu001/README b/board/eets/pdu001/README
index 50e7154..ab10cf9 100644
--- a/board/eets/pdu001/README
+++ b/board/eets/pdu001/README
@@ -14,7 +14,7 @@
The PDU-001 (Processor and Display Unit) is a plugin card for 19" racks. It is
manufactured by EETS GmbH (https://www.eets.ch). The core of the board is a m2
SOM from bytes at work (https://www.bytesatwork.ch) which in turn is based on
-AM3352 SOC from TI (http://www.ti.com).
+AM3352 SOC from TI (https://www.ti.com).
Customization
=============
diff --git a/board/eets/pdu001/board.c b/board/eets/pdu001/board.c
index de224d4..3a52e4a 100644
--- a/board/eets/pdu001/board.c
+++ b/board/eets/pdu001/board.c
@@ -6,7 +6,7 @@
*
* Copyright (C) 2018, EETS GmbH, http://www.eets.ch/
*
- * Copyright (C) 2011, Texas Instruments, Incorporated - http://www.ti.com/
+ * Copyright (C) 2011, Texas Instruments, Incorporated - https://www.ti.com/
*/
#include <common.h>
diff --git a/board/eets/pdu001/board.h b/board/eets/pdu001/board.h
index bfea96e..6ad0fea 100644
--- a/board/eets/pdu001/board.h
+++ b/board/eets/pdu001/board.h
@@ -6,7 +6,7 @@
*
* Copyright (C) 2018 EETS GmbH - http://www.eets.ch/
*
- * Copyright (C) 2011, Texas Instruments, Incorporated - http://www.ti.com/
+ * Copyright (C) 2011, Texas Instruments, Incorporated - https://www.ti.com/
*/
#ifndef _BOARD_H_
diff --git a/board/eets/pdu001/mux.c b/board/eets/pdu001/mux.c
index 886fef6..c97927e 100644
--- a/board/eets/pdu001/mux.c
+++ b/board/eets/pdu001/mux.c
@@ -4,7 +4,7 @@
*
* Copyright (C) 2018 EETS GmbH - http://www.eets.ch/
*
- * Copyright (C) 2011 Texas Instruments Incorporated - http://www.ti.com/
+ * Copyright (C) 2011 Texas Instruments Incorporated - https://www.ti.com/
*/
#include <common.h>
diff --git a/board/emulation/qemu-riscv/Kconfig b/board/emulation/qemu-riscv/Kconfig
index 108e9fd..2709c9c 100644
--- a/board/emulation/qemu-riscv/Kconfig
+++ b/board/emulation/qemu-riscv/Kconfig
@@ -81,5 +81,7 @@
imply USB_XHCI_PCI
imply USB_KEYBOARD
imply CMD_USB
+ imply UFS
+ imply UFS_PCI
endif
diff --git a/board/friendlyarm/nanopi2/onewire.c b/board/friendlyarm/nanopi2/onewire.c
index 56f0f2d..4f0b1e3 100644
--- a/board/friendlyarm/nanopi2/onewire.c
+++ b/board/friendlyarm/nanopi2/onewire.c
@@ -11,16 +11,13 @@
#include <asm/arch/clk.h>
#include <asm/arch/pwm.h>
#include <i2c.h>
+#include <linux/time.h>
#include <irq_func.h>
#include <asm/arch/nexell.h>
#include <asm/arch/nx_gpio.h>
-#ifndef NSEC_PER_SEC
-#define NSEC_PER_SEC 1000000000L
-#endif
-
#define SAMPLE_BPS 9600
#define SAMPLE_IN_US 101 /* (1000000 / BPS) */
diff --git a/board/grinn/chiliboard/board.c b/board/grinn/chiliboard/board.c
index b472ca5..64b32ca 100644
--- a/board/grinn/chiliboard/board.c
+++ b/board/grinn/chiliboard/board.c
@@ -1,6 +1,6 @@
// SPDX-License-Identifier: GPL-2.0+
/*
- * Copyright (C) 2011, Texas Instruments, Incorporated - http://www.ti.com/
+ * Copyright (C) 2011, Texas Instruments, Incorporated - https://www.ti.com/
* Copyright (C) 2017, Grinn - http://grinn-global.com/
*/
diff --git a/board/hisilicon/hikey/MAINTAINERS b/board/hisilicon/hikey/MAINTAINERS
index 11088ee..1045abe 100644
--- a/board/hisilicon/hikey/MAINTAINERS
+++ b/board/hisilicon/hikey/MAINTAINERS
@@ -2,5 +2,6 @@
M: Peter Griffin <peter.griffin@linaro.org>
S: Maintained
F: board/hisilicon/hikey
+F: doc/board/hisilicon/hikey.rst
F: include/configs/hikey.h
F: configs/hikey_defconfig
diff --git a/board/hisilicon/hikey/README b/board/hisilicon/hikey/README
deleted file mode 100644
index 94e8397..0000000
--- a/board/hisilicon/hikey/README
+++ /dev/null
@@ -1,227 +0,0 @@
-Introduction
-============
-
-HiKey is the first certified 96Boards Consumer Edition board. The board/SoC has: -
-* HiSilicon Kirin 6220 eight-core ARM Cortex-A53 64-bit SoC running at 1.2GHz.
-* ARM Mali 450-MP4 GPU
-* 1GB 800MHz LPDDR3 DRAM
-* 4GB eMMC Flash Storage
-* microSD
-* 802.11a/b/g/n WiFi, Bluetooth
-
-The HiKey schematic can be found here: -
-https://github.com/96boards/documentation/blob/master/consumer/hikey/hikey620/hardware-docs/HiKey_schematics_LeMaker_version_Rev_A1.pdf
-
-The SoC datasheet can be found here: -
-https://github.com/96boards/documentation/blob/master/consumer/hikey/hikey620/hardware-docs/Hi6220V100_Multi-Mode_Application_Processor_Function_Description.pdf
-
-Currently the u-boot port supports: -
-* USB
-* eMMC
-* SD card
-* GPIO
-
-The HiKey U-Boot port has been tested with l-loader, booting ATF, which then boots
-U-Boot as the bl33.bin executable.
-
-Compile from source
-===================
-
-First get all the sources
-
- > mkdir -p ~/hikey/src ~/hikey/bin
- > cd ~/hikey/src
- > git clone https://github.com/96boards-hikey/edk2 -b testing/hikey960_v2.5
- > git clone https://github.com/ARM-software/arm-trusted-firmware
- > git clone https://github.com/96boards-hikey/l-loader -b testing/hikey960_v1.2
- > git clone https://github.com/96boards-hikey/OpenPlatformPkg -b testing/hikey960_v1.3.4
- > git clone https://github.com/96boards-hikey/atf-fastboot
- > wget https://snapshots.linaro.org/96boards/reference-platform/components/uefi-staging/latest/hikey/release/hisi-idt.py
-
-Get the BL30 mcuimage.bin binary. It is shipped as part of the UEFI source.
-The latest version can be obtained from the OpenPlatformPkg repo.
-
- > cp OpenPlatformPkg/Platforms/Hisilicon/HiKey/Binary/mcuimage.bin ~/hikey/bin/
-
-Get nvme.img binary
- > wget -P ~/hikey/bin https://snapshots.linaro.org/96boards/reference-platform/components/uefi-staging/latest/hikey/release/nvme.img
-
-Compile U-Boot
-==============
-
- > cd ~/hikey/src/u-boot
- > make CROSS_COMPILE=aarch64-linux-gnu- hikey_config
- > make CROSS_COMPILE=aarch64-linux-gnu-
- > cp u-boot.bin ~/hikey/bin
-
-Compile ARM Trusted Firmware (ATF)
-==================================
-
- > cd ~/hikey/src/arm-trusted-firmware
- > make CROSS_COMPILE=aarch64-linux-gnu- all fip \
- SCP_BL2=~/hikey/bin/mcuimage.bin \
- BL33=~/hikey/bin/u-boot.bin DEBUG=1 PLAT=hikey
-
-Copy the resulting FIP binary
- > cp build/hikey/debug/fip.bin ~/hikey/bin
-
-Compile ATF Fastboot
-====================
-
- > cd ~/hikey/src/atf-fastboot
- > make CROSS_COMPILE=aarch64-linux-gnu- PLAT=hikey DEBUG=1
-
-Compile l-loader
-================
- > cd ~/hikey/src/l-loader
- > ln -sf ~/hikey/src/arm-trusted-firmware/build/hikey/debug/bl1.bin
- > ln -sf ~/hikey/src/arm-trusted-firmware/build/hikey/debug/bl2.bin
- > ln -sf ~/hikey/src/atf-fastboot/build/hikey/debug/bl1.bin fastboot.bin
- > make hikey PTABLE_LST=aosp-8g
-
-Copy the resulting binaries
- > cp *.img ~/hikey/bin
- > cp l-loader.bin ~/hikey/bin
- > cp recovery.bin ~/hikey/bin
-
-These instructions are adapted from
-https://github.com/ARM-software/arm-trusted-firmware/blob/master/docs/plat/hikey.rst
-
-FLASHING
-========
-
-1. Connect the second jumper on J15 BOOT SEL, to go into recovery mode and flash l-loader.bin with
-the hisi-idt.py utility. Then connect a USB A to B mini cable from your PC to the USB OTG port of HiKey and execute the below command.
-
-The command below assumes HiKey enumerated as the first USB serial port
-
- > sudo python ~/hikey/src/hisi-idt.py -d /dev/ttyUSB0 --img1 ~/hikey/bin/recovery.bin
-
-2. Once LED 0 comes on solid, HiKey board should be detected as a fastboot device.
-
- > sudo fastboot devices
-
-0123456789ABCDEF fastboot
-
-3. Flash the images
-
- > sudo fastboot flash ptable ~/hikey/bin/prm_ptable.img
- > sudo fastboot flash loader ~/hikey/bin/l-loader.bin
- > sudo fastboot flash fastboot ~/hikey/bin/fip.bin
- > sudo fastboot flash nvme ~/hikey/bin/nvme.img
-
-4. Disconnect second jumper on J15 BOOT SEL, and reset the board and you will now (hopefully)
- have ATF, booting u-boot from eMMC.
-
- Note: To get USB host working, also disconnect the USB OTG cable used for flashing. Otherwise you
- will get 'dwc_otg_core_host_init: Timeout!' errors.
-
-See working boot trace below on UART3 available at Low Speed Expansion header: -
-
-NOTICE: BL2: v1.5(debug):v1.5-694-g6d4f6aea
-NOTICE: BL2: Built : 09:21:42, Aug 29 2018
-INFO: BL2: Doing platform setup
-INFO: ddr3 rank1 init pass
-INFO: succeed to set ddrc 150mhz
-INFO: ddr3 rank1 init pass
-INFO: succeed to set ddrc 266mhz
-INFO: ddr3 rank1 init pass
-INFO: succeed to set ddrc 400mhz
-INFO: ddr3 rank1 init pass
-INFO: succeed to set ddrc 533mhz
-INFO: ddr3 rank1 init pass
-INFO: succeed to set ddrc 800mhz
-INFO: Samsung DDR
-INFO: ddr test value:0xa5a55a5a
-INFO: BL2: TrustZone: protecting 16777216 bytes of memory at 0x3f000000
-INFO: BL2: TrustZone: protecting 4194304 bytes of memory at 0x3e800000
-INFO: [BDID] [fff91c18] midr: 0x410fd033
-INFO: init_acpu_dvfs: pmic version 17
-INFO: init_acpu_dvfs: ACPU_CHIP_MAX_FREQ=0x186a00.
-INFO: acpu_dvfs_volt_init: success!
-INFO: acpu_dvfs_set_freq: support freq num is 5
-INFO: acpu_dvfs_set_freq: start prof is 0x4
-INFO: acpu_dvfs_set_freq: magic is 0x5a5ac5c5
-INFO: acpu_dvfs_set_freq: voltage:
-INFO: - 0: 0x49
-INFO: - 1: 0x49
-INFO: - 2: 0x50
-INFO: - 3: 0x60
-INFO: - 4: 0x78
-NOTICE: acpu_dvfs_set_freq: set acpu freq success!INFO: BL2: Loading image id 2
-INFO: Loading image id=2 at address 0x1000000
-INFO: Image id=2 loaded: 0x1000000 - 0x1023d00
-INFO: hisi_mcu_load_image: mcu sections 0:
-INFO: hisi_mcu_load_image: src = 0x1000200
-INFO: hisi_mcu_load_image: dst = 0xf6000000
-INFO: hisi_mcu_load_image: size = 31184
-INFO: hisi_mcu_load_image: [SRC 0x1000200] 0x8000 0x3701 0x7695 0x7689
-INFO: hisi_mcu_load_image: [DST 0xf6000000] 0x8000 0x3701 0x7695 0x7689
-INFO: hisi_mcu_load_image: mcu sections 1:
-INFO: hisi_mcu_load_image: src = 0x1007bd0
-INFO: hisi_mcu_load_image: dst = 0x5e00000
-INFO: hisi_mcu_load_image: size = 93828
-INFO: hisi_mcu_load_image: [SRC 0x1007bd0] 0xf000b510 0x2103fb3d 0xf0004604 0xf003fb57
-INFO: hisi_mcu_load_image: [DST 0x5e00000] 0xf000b510 0x2103fb3d 0xf0004604 0xf003fb57
-INFO: hisi_mcu_load_image: mcu sections 2:
-INFO: hisi_mcu_load_image: src = 0x101ea54
-INFO: hisi_mcu_load_image: dst = 0x5e16e84
-INFO: hisi_mcu_load_image: size = 15428
-INFO: hisi_mcu_load_image: [SRC 0x101ea54] 0x9 0x1020640 0x10001 0x8f0d180
-INFO: hisi_mcu_load_image: [DST 0x5e16e84] 0x9 0x1020640 0x10001 0x8f0d180
-INFO: hisi_mcu_load_image: mcu sections 3:
-INFO: hisi_mcu_load_image: src = 0x1022698
-INFO: hisi_mcu_load_image: dst = 0x5e22a10
-INFO: hisi_mcu_load_image: size = 3060
-INFO: hisi_mcu_load_image: [SRC 0x1022698] 0x0 0x0 0x0 0x0
-INFO: hisi_mcu_load_image: [DST 0x5e22a10] 0x0 0x0 0x0 0x0
-INFO: hisi_mcu_load_image: mcu sections 4:
-INFO: hisi_mcu_load_image: src = 0x102328c
-INFO: hisi_mcu_load_image: dst = 0x5e23604
-INFO: hisi_mcu_load_image: size = 2616
-INFO: hisi_mcu_load_image: [SRC 0x102328c] 0xf80000a0 0x0 0xf80000ac 0x0
-INFO: hisi_mcu_load_image: [DST 0x5e23604] 0xf80000a0 0x0 0xf80000ac 0x0
-INFO: hisi_mcu_start_run: AO_SC_SYS_CTRL2=0
-INFO: plat_hikey_bl2_handle_scp_bl2: MCU PC is at 0x42933301
-INFO: plat_hikey_bl2_handle_scp_bl2: AO_SC_PERIPH_CLKSTAT4 is 0x3b018f09
-WARNING: BL2: Platform setup already done!!
-INFO: BL2: Loading image id 3
-INFO: Loading image id=3 at address 0xf9858000
-INFO: Image id=3 loaded: 0xf9858000 - 0xf9860058
-INFO: BL2: Loading image id 5
-INFO: Loading image id=5 at address 0x35000000
-INFO: Image id=5 loaded: 0x35000000 - 0x35061cd2
-NOTICE: BL2: Booting BL31
-INFO: Entry point address = 0xf9858000
-INFO: SPSR = 0x3cd
-NOTICE: BL31: v1.5(debug):v1.5-694-g6d4f6aea
-NOTICE: BL31: Built : 09:21:44, Aug 29 2018
-WARNING: Using deprecated integer interrupt array in gicv2_driver_data_t
-WARNING: Please migrate to using an interrupt_prop_t array
-INFO: ARM GICv2 driver initialized
-INFO: BL31: Initializing runtime services
-INFO: BL31: cortex_a53: CPU workaround for disable_non_temporal_hint was applied
-INFO: BL31: cortex_a53: CPU workaround for 843419 was applied
-INFO: BL31: cortex_a53: CPU workaround for 855873 was applied
-INFO: BL31: Preparing for EL3 exit to normal world
-INFO: Entry point address = 0x35000000
-INFO: SPSR = 0x3c9
-
-
-U-Boot 2018.09-rc1 (Aug 22 2018 - 14:55:49 +0530)hikey
-
-DRAM: 990 MiB
-HI6553 PMIC init
-MMC: config_sd_carddetect: SD card present
-Hisilicon DWMMC: 0, Hisilicon DWMMC: 1
-Loading Environment from FAT... Unable to use mmc 1:1... Failed (-5)
-In: uart@f7113000
-Out: uart@f7113000
-Err: uart@f7113000
-Net: Net Initialization Skipped
-No ethernet found.
-Hit any key to stop autoboot: 0
-starting USB...
-USB0: scanning bus 0 for devices... 2 USB Device(s) found
- scanning usb for storage devices... 0 Storage Device(s) found
- scanning usb for ethernet devices... 0 Ethernet Device(s) found
diff --git a/board/hisilicon/hikey960/MAINTAINERS b/board/hisilicon/hikey960/MAINTAINERS
index 2c98932..a442271 100644
--- a/board/hisilicon/hikey960/MAINTAINERS
+++ b/board/hisilicon/hikey960/MAINTAINERS
@@ -2,5 +2,6 @@
M: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
S: Maintained
F: board/hisilicon/hikey960
+F: doc/board/hisilicon/hikey960.rst
F: include/configs/hikey960.h
F: configs/hikey960_defconfig
diff --git a/board/hisilicon/hikey960/README b/board/hisilicon/hikey960/README
deleted file mode 100644
index e1e330d..0000000
--- a/board/hisilicon/hikey960/README
+++ /dev/null
@@ -1,247 +0,0 @@
-Introduction
-============
-
-HiKey960 is one of the 96Boards Consumer Edition board from HiSilicon.
-The board/SoC has: -
-* HiSilicon Kirin960 (HI3660) SoC with 4xCortex-A73 and 4xCortex-A53
-* ARM Mali G71 MP8 GPU
-* 3GB LPDDR4 SDRAM
-* 32GB UFS Flash Storage
-* microSD
-* 802.11a/b/g/n WiFi, Bluetooth
-
-More information about this board can be found in 96Boards website:
-https://www.96boards.org/product/hikey960/
-
-Currently the u-boot port supports: -
-* SD card
-
-Compile from source
-===================
-
-First get all the sources
-
- > mkdir -p ~/hikey960/src ~/hikey960/bin
- > cd ~/hikey960/src
- > git clone https://github.com/ARM-software/arm-trusted-firmware
- > git clone https://github.com/96boards-hikey/OpenPlatformPkg -b testing/hikey960_v1.3.4
- > git clone https://github.com/96boards-hikey/l-loader -b testing/hikey960_v1.2
- > wget http://snapshots.linaro.org/96boards/reference-platform/components/uefi-staging/latest/hikey960/release/config
- > wget http://snapshots.linaro.org/96boards/reference-platform/components/uefi-staging/latest/hikey960/release/hisi-sec_usb_xloader.img
- > wget http://snapshots.linaro.org/96boards/reference-platform/components/uefi-staging/latest/hikey960/release/hisi-sec_uce_boot.img
- > wget http://snapshots.linaro.org/96boards/reference-platform/components/uefi-staging/latest/hikey960/release/sec_xloader.img
- > wget http://snapshots.linaro.org/96boards/reference-platform/components/uefi-staging/latest/hikey960/release/recovery.bin
- > wget http://snapshots.linaro.org/96boards/reference-platform/components/uefi-staging/latest/hikey960/release/hikey_idt
-
-Get the SCP_BL2 lpm3.img binary. It is shipped as part of the UEFI source.
-The latest version can be obtained from the OpenPlatformPkg repo.
-
- > cp OpenPlatformPkg/Platforms/Hisilicon/HiKey960/Binary/lpm3.img ~/hikey960/bin/
-
-Compile U-Boot
-==============
-
- > cd ~/hikey960/src/u-boot
- > make CROSS_COMPILE=aarch64-linux-gnu- hikey960_defconfig
- > make CROSS_COMPILE=aarch64-linux-gnu-
- > cp u-boot.bin ~/hikey960/bin/
-
-Compile ARM Trusted Firmware (ATF)
-==================================
-
- > cd ~/hikey960/src/arm-trusted-firmware
- > make CROSS_COMPILE=aarch64-linux-gnu- all fip \
- SCP_BL2=~/hikey960/bin/lpm3.img \
- BL33=~/hikey960/bin/u-boot.bin DEBUG=1 PLAT=hikey960
-
-Copy the resulting FIP binary
- > cp build/hikey960/debug/fip.bin ~/hikey960/bin
-
-Compile l-loader
-================
- > cd ~/hikey960/src/l-loader
- > ln -sf ~/hikey960/src/arm-trusted-firmware/build/hikey960/debug/bl1.bin
- > ln -sf ~/hikey960/src/arm-trusted-firmware/build/hikey960/debug/bl2.bin
- > ln -sf ~/hikey960/src/arm-trusted-firmware/build/hikey960/debug/fip.bin
- > ln -sf ~/hikey960/bin/u-boot.bin
- > make hikey960 PTABLE_LST=linux-32g NS_BL1U=u-boot.bin
-
-Copy the resulting binaries
- > cp *.img ~/hikey960/bin
- > cp l-loader.bin ~/hikey960/bin
-
-These instructions are adapted from
-https://github.com/ARM-software/arm-trusted-firmware/blob/master/docs/plat/hikey960.rst
-
-Setup Console
-=============
-
-Install ser2net. Use telnet as the console since UEFI in recovery mode
-output window fails to display in minicom.
-
- > sudo apt-get install ser2net
-
-Configure ser2net
-
- > sudo vi /etc/ser2net.conf
-
-Append one line for serial-over-USB in #ser2net.conf
-
- > 2004:telnet:0:/dev/ttyUSB0:115200 8DATABITS NONE 1STOPBIT banner
-
-Start ser2net
-
- > sudo killall ser2net
- > sudo ser2net -u
-
-Open the console.
-
- > telnet localhost 2004
-
-And you could open the console remotely, too.
-
-Flashing
-========
-
-1. Boot Hikey960 into recovery mode as per the below document:
-https://github.com/96boards/documentation/blob/master/consumer/hikey/hikey960/installation/board-recovery.md
-
-Once Hikey960 is in recovery mode, flash the recovery binary:
-
- > cd ~/hikey960/src
- > chmod +x ./hikey_idt
- > sudo ./hikey_idt -c config -p /dev/ttyUSB1
-
-Now move to the Hikey960 console and press `f` during UEFI boot. This
-will allow the board to boot into fastboot mode. Once the board is in
-fastboot mode, you should see the ID of the HiKey960 board using the
-following command
-
- > sudo fastboot devices
-
-1ED3822A018E3372 fastboot
-
-3. Flash the images
-
-Now, the images can be flashed using fastboot:
-
- > sudo fastboot flash ptable ~/hikey960/bin/prm_ptable.img
- > sudo fastboot flash xloader ~/hikey960/bin/sec_xloader.img
- > sudo fastboot flash fastboot ~/hikey960/bin/l-loader.bin
- > sudo fastboot flash fip ~/hikey960/bin/fip.bin
-
-4. Set the "Boot Mode" switch to OFF position for normal boot mode.
-Then power on HiKey960
-
-Observe the console traces using UART6 on the Low Speed Expansion header:
-
-NOTICE: BL2: v2.1(debug):v2.1-531-g3ee48f40
-NOTICE: BL2: Built : 18:15:58, Aug 2 2019
-INFO: BL2: Doing platform setup
-INFO: UFS LUN0 contains 1024 blocks with 4096-byte size
-INFO: UFS LUN1 contains 1024 blocks with 4096-byte size
-INFO: UFS LUN2 contains 2048 blocks with 4096-byte size
-INFO: UFS LUN3 contains 7805952 blocks with 4096-byte size
-INFO: ufs: change power mode success
-INFO: BL2: Loading image id 2
-INFO: Loading image id=2 at address 0x89c80000
-INFO: Image id=2 loaded: 0x89c80000 - 0x89cb5088
-INFO: BL2: Initiating SCP_BL2 transfer to SCP
-INFO: BL2: SCP_BL2: 0x89c80000@0x35088
-INFO: BL2: SCP_BL2 HEAD:
-INFO: BL2: SCP_BL2 0x7000 0x179 0x159 0x149
-INFO: BL2: SCP_BL2 0x189 0x18b 0x18d 0x0
-INFO: BL2: SCP_BL2 0x0 0x0 0x0 0x18f
-INFO: BL2: SCP_BL2 0x191 0x0 0x193 0x195
-INFO: BL2: SCP_BL2 0x18fd 0x18fd 0x18fd 0x18fd
-INFO: BL2: SCP_BL2 0x18fd 0x18fd 0x18fd 0x18fd
-INFO: BL2: SCP_BL2 0x18fd 0x18fd 0x18fd 0x18fd
-INFO: BL2: SCP_BL2 0x4d454355 0x43494741 0x424d554e 0x21215245
-INFO: BL2: SCP_BL2 0x4a054904 0x42912000 0xf841bfbc 0xe7fa0b04
-INFO: BL2: SCP_BL2 0xb88cf000 0x3b18 0x3d1c 0x6809493e
-INFO: BL2: SCP_BL2 0x4613680a 0x201f102 0xf0002a04 0x600a804c
-INFO: BL2: SCP_BL2 0x204f04f 0xf203fb02 0xf102440a 0x60100204
-INFO: BL2: SCP_BL2 0x160f04f 0xf103fb01 0x68004834 0x61044408
-INFO: BL2: SCP_BL2 0x61866145 0xf8c061c7 0xf8c08020 0xf8c09024
-INFO: BL2: SCP_BL2 0xf8c0a028 0xf3efb02c 0xf3ef8208 0x68118309
-INFO: BL2: SCP_BL2 0xf1026401 0xf0110204 0xbf070f04 0x46113220
-INFO: BL2: SCP_BL2 TAIL:
-INFO: BL2: SCP_BL2 0x0 0x0 0x0 0x0
-INFO: BL2: SCP_BL2 0x0 0x0 0x0 0x0
-INFO: BL2: SCP_BL2 0x0 0x0 0x0 0x0
-INFO: BL2: SCP_BL2 0x0 0x0 0x0 0x0
-INFO: BL2: SCP_BL2 0x0 0x0 0x0 0x0
-INFO: BL2: SCP_BL2 0x0 0x0 0x0 0x0
-INFO: BL2: SCP_BL2 0x0 0x0 0x0 0x0
-INFO: BL2: SCP_BL2 0x0 0x0 0x0 0x0
-INFO: BL2: SCP_BL2 0x0 0x0 0x0 0x0
-INFO: BL2: SCP_BL2 0x0 0x0 0x0 0x0
-INFO: BL2: SCP_BL2 0x0 0x19cad151 0x19b80040 0x0
-INFO: BL2: SCP_BL2 0x0 0x0 0x0 0x0
-INFO: BL2: SCP_BL2 0x0 0x0 0x0 0x0
-INFO: BL2: SCP_BL2 0x0 0x0 0x0 0x0
-INFO: BL2: SCP_BL2 0x0 0x0 0x0 0x0
-INFO: BL2: SCP_BL2 0x0 0x0 0x0 0x0
-INFO: BL2: SCP_BL2 transferred to SCP
-INFO: start fw loading
-INFO: fw load success
-WARNING: BL2: Platform setup already done!!
-INFO: BL2: Loading image id 3
-INFO: Loading image id=3 at address 0x1ac58000
-INFO: Image id=3 loaded: 0x1ac58000 - 0x1ac63024
-INFO: BL2: Loading image id 5
-INFO: Loading image id=5 at address 0x1ac98000
-INFO: Image id=5 loaded: 0x1ac98000 - 0x1ad0819c
-NOTICE: BL2: Booting BL31
-INFO: Entry point address = 0x1ac58000
-INFO: SPSR = 0x3cd
-NOTICE: BL31: v2.1(debug):v2.1-531-g3ee48f40
-NOTICE: BL31: Built : 18:16:01, Aug 2 2019
-INFO: ARM GICv2 driver initialized
-INFO: BL31: Initializing runtime services
-INFO: BL31: cortex_a53: CPU workaround for 855873 was applied
-INFO: plat_setup_psci_ops: sec_entrypoint=0x1ac580fc
-INFO: BL31: Preparing for EL3 exit to normal world
-INFO: Entry point address = 0x1ac98000
-INFO: SPSR = 0x3c9
-
-
-U-Boot 2019.07-00628-g286f05a6fc-dirty (Aug 02 2019 - 17:14:05 +0530)
-Hikey960
-
-DRAM: 3 GiB
-PSCI: v1.1
-MMC: dwmmc1@ff37f000: 0
-Loading Environment from EXT4... ** File not found /uboot.env **
-
-** Unable to read "/uboot.env" from mmc0:2 **
-In: serial@fff32000
-Out: serial@fff32000
-Err: serial@fff32000
-Net: Net Initialization Skipped
-No ethernet found.
-Hit any key to stop autoboot: 0
-switch to partitions #0, OK
-mmc0 is current device
-Scanning mmc 0:1...
-Found /extlinux/extlinux.conf
-Retrieving file: /extlinux/extlinux.conf
-201 bytes read in 12 ms (15.6 KiB/s)
-1: hikey960-kernel
-Retrieving file: /Image
-24689152 bytes read in 4377 ms (5.4 MiB/s)
-append: earlycon=pl011,mmio32,0xfff32000 console=ttyAMA6,115200 rw root=/dev/mmcblk0p2 rot
-Retrieving file: /hi3660-hikey960.dtb
-35047 bytes read in 14 ms (2.4 MiB/s)
-## Flattened Device Tree blob at 10000000
- Booting using the fdt blob at 0x10000000
- Using Device Tree in place at 0000000010000000, end 000000001000b8e6
-
-Starting kernel ...
-
-[ 0.000000] Booting Linux on physical CPU 0x0000000000 [0x410fd034]
-[ 0.000000] Linux version 5.2.0-03138-gd75da80dce39 (mani@Mani-XPS-13-9360) (gcc versi9
-[ 0.000000] Machine model: HiKey960
-[ 0.000000] earlycon: pl11 at MMIO32 0x00000000fff32000 (options '')
-[ 0.000000] printk: bootconsole [pl11] enabled
-[ 0.000000] efi: Getting EFI parameters from FDT:
diff --git a/board/hisilicon/poplar/MAINTAINERS b/board/hisilicon/poplar/MAINTAINERS
index 9c045ea..bfd4a9b 100644
--- a/board/hisilicon/poplar/MAINTAINERS
+++ b/board/hisilicon/poplar/MAINTAINERS
@@ -3,5 +3,6 @@
M: Shawn Guo <shawn.guo@linaro.org>
S: Maintained
F: board/hisilicon/poplar
+F: doc/board/hisilicon/poplar.rst
F: include/configs/poplar.h
F: configs/poplar_defconfig
diff --git a/board/hisilicon/poplar/README b/board/hisilicon/poplar/README
deleted file mode 100644
index 77dcc3b..0000000
--- a/board/hisilicon/poplar/README
+++ /dev/null
@@ -1,288 +0,0 @@
-================================================================================
- Board Information
-================================================================================
-
-Developed by HiSilicon, the board features the Hi3798C V200 with an
-integrated quad-core 64-bit ARM Cortex A53 processor and high
-performance Mali T720 GPU, making it capable of running any commercial
-set-top solution based on Linux or Android. Its high performance
-specification also supports a premium user experience with up to H.265
-HEVC decoding of 4K video at 60 frames per second.
-
-SOC Hisilicon Hi3798CV200
-CPU Quad-core ARM Cortex-A53 64 bit
-DRAM DDR3/3L/4 SDRAM interface, maximum 32-bit data width 2 GB
-USB Two USB 2.0 ports One USB 3.0 ports
-CONSOLE USB-micro port for console support
-ETHERNET 1 GBe Ethernet
-PCIE One PCIe 2.0 interfaces
-JTAG 8-Pin JTAG
-EXPANSION INTERFACE Linaro 96Boards Low Speed Expansion slot
-DIMENSION Standard 160×120 mm 96Boards Enterprice Edition form factor
-WIFI 802.11AC 2*2 with Bluetooth
-CONNECTORS One connector for Smart Card One connector for TSI
-
-
-================================================================================
- BUILD INSTRUCTIONS
-================================================================================
-
-Note of warning:
-================
-
-U-Boot has a *strong* dependency with the l-loader and the arm trusted firmware
-repositories.
-
-The boot sequence is:
- l-loader --> arm_trusted_firmware --> u-boot
-
-U-Boot needs to be aware of the BL31 runtime location and size to avoid writing
-over it. Currently, BL31 is being placed below the kernel text offset (check
-poplar.c) but this could change in the future.
-
-The current version of u-boot has been tested with:
- - https://github.com/Linaro/poplar-l-loader.git
-
- commit f0988698dcc5c08bd0a8f50aa0457e138a5f438c
- Author: Alex Elder <elder@linaro.org>
- Date: Fri Jun 16 08:57:59 2017 -0500
-
- l-loader: use external memory region definitions
-
- The ARM Trusted Firmware code now has a header file that collects
- all the definitions for the memory regions used for its boot stages.
- Include that file where needed, and use the definitions found therein
-
- Signed-off-by: Alex Elder <elder@linaro.org>
-
-
- - https://github.com/Linaro/poplar-arm-trusted-firmware.git
-
- commit 6ac42dd3be13c99aa8ce29a15073e2f19d935f68
- Author: Alex Elder <elder@linaro.org>
- Date: Fri Jun 16 09:24:50 2017 -0500
-
- poplar: define memory regions in a separate file
-
- Separate the definitions for memory regions used for the BL stage
- images and FIP into a new file. The "l-loader" image uses knowledge
- of the sizes and locations of these memory regions, and it can now
- include this (external) header to get these definitions, rather than
- having to make coordinated changes to both code bases.
-
- The new file has a complete set of definitions (more than may be
- required by one or the other user). It also includes a summary of
- how the boot process works, and how it uses these regions.
-
- It should now be relatively easy to adjust the sizes and locations
- of these memory regions, or to add to them (e.g. for TEE).
-
- Signed-off-by: Alex Elder <elder@linaro.org>
-
-
-Compile from source:
-====================
-
-Get all the sources
-
- > mkdir -p ~/poplar/src ~/poplar/bin
- > cd ~/poplar/src
- > git clone https://github.com/Linaro/poplar-l-loader.git l-loader
- > git clone https://github.com/Linaro/poplar-arm-trusted-firmware.git atf
- > git clone https://github.com/Linaro/poplar-u-boot.git u-boot
-
-Make sure you are using the correct branch on each one of these repositories.
-The definition of "correct" might change over time (at this moment in time this
-would be the "latest" branch).
-
-Compile U-Boot:
-===============
-
- Prerequisite:
- # sudo apt-get install device-tree-compiler
-
- > cd ~/poplar/src/u-boot
- > make CROSS_COMPILE=aarch64-linux-gnu- poplar_defconfig
- > make CROSS_COMPILE=aarch64-linux-gnu-
- > cp u-boot.bin ~/poplar/bin
-
-Compile ARM Trusted Firmware (ATF):
-===================================
-
- > cd ~/poplar/src/atf
- > make CROSS_COMPILE=aarch64-linux-gnu- all fip \
- SPD=none BL33=~/poplar/bin/u-boot.bin DEBUG=1 PLAT=poplar
-
-Copy resulting binaries
- > cp build/hi3798cv200/debug/bl1.bin ~/poplar/src/l-loader/atf/
- > cp build/hi3798cv200/debug/fip.bin ~/poplar/src/l-loader/atf/
-
-Compile l-loader:
-=================
-
- > cd ~/poplar/src/l-loader
- > make clean
- > make CROSS_COMPILE=arm-linux-gnueabi-
-
- Due to BootROM requiremets, rename l-loader.bin to fastboot.bin:
- > cp l-loader.bin ~/poplar/bin/fastboot.bin
-
-
-================================================================================
- FLASH INSTRUCTIONS
-================================================================================
-
-Two methods:
-
-Using USB debrick support:
- Copy fastboot.bin to a FAT partition on the USB drive and reboot the
- poplar board while pressing S3(usb_boot).
-
- The system will execute the new u-boot and boot into a shell which you
- can then use to write to eMMC.
-
-Using U-BOOT from shell:
- 1) using AXIS usb ethernet dongle and tftp
- 2) using FAT formated USB drive
-
-
-1. TFTP (USB ethernet dongle)
-=============================
-
-Plug a USB AXIS ethernet dongle on any of the USB2 ports on the Poplar board.
-Copy fastboot.bin to your tftp server.
-In u-boot make sure your network is properly setup.
-
-Then
-
-=> tftp 0x30000000 fastboot.bin
-starting USB...
-USB0: USB EHCI 1.00
-scanning bus 0 for devices... 1 USB Device(s) found
-USB1: USB EHCI 1.00
-scanning bus 1 for devices... 3 USB Device(s) found
- scanning usb for storage devices... 0 Storage Device(s) found
- scanning usb for ethernet devices... 1 Ethernet Device(s) found
-Waiting for Ethernet connection... done.
-Using asx0 device
-TFTP from server 192.168.1.4; our IP address is 192.168.1.10
-Filename 'poplar/fastboot.bin'.
-Load address: 0x30000000
-Loading: #################################################################
- #################################################################
- ###############################################################
- 2 MiB/s
-done
-Bytes transferred = 983040 (f0000 hex)
-
-=> mmc write 0x30000000 0 0x780
-
-MMC write: dev # 0, block # 0, count 1920 ... 1920 blocks written: OK
-=> reset
-
-
-2. USING USB FAT DRIVE
-=======================
-
-Copy fastboot.bin to any partition on a FAT32 formated usb flash drive.
-Enter the uboot prompt
-
-=> fatls usb 0:2
- 983040 fastboot.bin
-
-1 file(s), 0 dir(s)
-
-=> fatload usb 0:2 0x30000000 fastboot.bin
-reading fastboot.bin
-983040 bytes read in 44 ms (21.3 MiB/s)
-
-=> mmc write 0x30000000 0 0x780
-
-MMC write: dev # 0, block # 0, count 1920 ... 1920 blocks written: OK
-
-
-================================================================================
- BOOT TRACE
-================================================================================
-
-Bootrom start
-Boot Media: eMMC
-Decrypt auxiliary code ...OK
-
-lsadc voltage min: 000000FE, max: 000000FF, aver: 000000FE, index: 00000000
-
-Entry boot auxiliary code
-
-Auxiliary code - v1.00
-DDR code - V1.1.2 20160205
-Build: Mar 24 2016 - 17:09:44
-Reg Version: v134
-Reg Time: 2016/03/18 09:44:55
-Reg Name: hi3798cv2dmb_hi3798cv200_ddr3_2gbyte_8bitx4_4layers.reg
-
-Boot auxiliary code success
-Bootrom success
-
-LOADER: Switched to aarch64 mode
-LOADER: Entering ARM TRUSTED FIRMWARE
-LOADER: CPU0 executes at 0x000ce000
-
-INFO: BL1: 0xe1000 - 0xe7000 [size = 24576]
-NOTICE: Booting Trusted Firmware
-NOTICE: BL1: v1.3(debug):v1.3-372-g1ba9c60
-NOTICE: BL1: Built : 17:51:33, Apr 30 2017
-INFO: BL1: RAM 0xe1000 - 0xe7000
-INFO: BL1: Loading BL2
-INFO: Loading image id=1 at address 0xe9000
-INFO: Image id=1 loaded at address 0xe9000, size = 0x5008
-NOTICE: BL1: Booting BL2
-INFO: Entry point address = 0xe9000
-INFO: SPSR = 0x3c5
-NOTICE: BL2: v1.3(debug):v1.3-372-g1ba9c60
-NOTICE: BL2: Built : 17:51:33, Apr 30 2017
-INFO: BL2: Loading BL31
-INFO: Loading image id=3 at address 0x129000
-INFO: Image id=3 loaded at address 0x129000, size = 0x8038
-INFO: BL2: Loading BL33
-INFO: Loading image id=5 at address 0x37000000
-INFO: Image id=5 loaded at address 0x37000000, size = 0x58f17
-NOTICE: BL1: Booting BL31
-INFO: Entry point address = 0x129000
-INFO: SPSR = 0x3cd
-INFO: Boot bl33 from 0x37000000 for 364311 Bytes
-NOTICE: BL31: v1.3(debug):v1.3-372-g1ba9c60
-NOTICE: BL31: Built : 17:51:33, Apr 30 2017
-INFO: BL31: Initializing runtime services
-INFO: BL31: Preparing for EL3 exit to normal world
-INFO: Entry point address = 0x37000000
-INFO: SPSR = 0x3c9
-
-
-U-Boot 2017.05-rc2-00130-gd2255b0 (Apr 30 2017 - 17:51:28 +0200)poplar
-
-Model: HiSilicon Poplar Development Board
-BOARD: Hisilicon HI3798cv200 Poplar
-DRAM: 1 GiB
-MMC: Hisilicon DWMMC: 0
-In: serial@f8b00000
-Out: serial@f8b00000
-Err: serial@f8b00000
-Net: Net Initialization Skipped
-No ethernet found.
-
-Hit any key to stop autoboot: 0
-starting USB...
-USB0: USB EHCI 1.00
-scanning bus 0 for devices... 1 USB Device(s) found
-USB1: USB EHCI 1.00
-scanning bus 1 for devices... 4 USB Device(s) found
- scanning usb for storage devices... 1 Storage Device(s) found
- scanning usb for ethernet devices... 1 Ethernet Device(s) found
-
-USB device 0:
- Device 0: Vendor: SanDisk Rev: 1.00 Prod: Cruzer Blade
- Type: Removable Hard Disk
- Capacity: 7632.0 MB = 7.4 GB (15630336 x 512)
-... is now current device
-Scanning usb 0:1...
-=>
diff --git a/board/htc/endeavoru/endeavoru-spl.c b/board/htc/endeavoru/endeavoru-spl.c
index 7921ff1..2525b50 100644
--- a/board/htc/endeavoru/endeavoru-spl.c
+++ b/board/htc/endeavoru/endeavoru-spl.c
@@ -9,7 +9,7 @@
* Svyatoslav Ryhel <clamor95@gmail.com>
*/
-#include <common.h>
+#include <asm/arch/tegra.h>
#include <asm/arch-tegra/tegra_i2c.h>
#include <linux/delay.h>
diff --git a/board/htc/endeavoru/endeavoru.c b/board/htc/endeavoru/endeavoru.c
index e1a0b24..7fb6125 100644
--- a/board/htc/endeavoru/endeavoru.c
+++ b/board/htc/endeavoru/endeavoru.c
@@ -7,48 +7,11 @@
* Svyatoslav Ryhel <clamor95@gmail.com>
*/
-#include <common.h>
#include <dm.h>
#include <fdt_support.h>
-#include <i2c.h>
-#include <log.h>
#include <asm/arch/pinmux.h>
-#include <asm/arch/gp_padctrl.h>
-#include <asm/arch/gpio.h>
-#include <asm/gpio.h>
-#include <linux/delay.h>
-#include "pinmux-config-endeavoru.h"
-
-#define TPS80032_CTL1_I2C_ADDR 0x48
-#define TPS80032_PHOENIX_DEV_ON 0x25
-#define DEVOFF BIT(0)
-#define TPS80032_LDO1_CFG_STATE 0x9E
-#define TPS80032_LDO1_CFG_VOLTAGE 0x9F
-
-#ifdef CONFIG_CMD_POWEROFF
-int do_poweroff(struct cmd_tbl *cmdtp, int flag,
- int argc, char *const argv[])
-{
- struct udevice *dev;
- int ret;
-
- ret = i2c_get_chip_for_busnum(0, TPS80032_CTL1_I2C_ADDR, 1, &dev);
- if (ret) {
- log_debug("cannot find PMIC I2C chip\n");
- return 0;
- }
- ret = dm_i2c_reg_write(dev, TPS80032_PHOENIX_DEV_ON, DEVOFF);
- if (ret)
- return ret;
-
- // wait some time and then print error
- mdelay(5000);
-
- printf("Failed to power off!!!\n");
- return 1;
-}
-#endif
+#include "pinmux-config-endeavoru.h"
/*
* Routine: pinmux_init
@@ -59,38 +22,6 @@
pinmux_config_pingrp_table(endeavoru_pinmux_common,
ARRAY_SIZE(endeavoru_pinmux_common));
}
-
-#ifdef CONFIG_MMC_SDHCI_TEGRA
-static void tps80032_voltage_init(void)
-{
- struct udevice *dev;
- int ret;
-
- ret = i2c_get_chip_for_busnum(0, TPS80032_CTL1_I2C_ADDR, 1, &dev);
- if (ret)
- log_debug("cannot find PMIC I2C chip\n");
-
- /* TPS80032: LDO1_REG = 1.2v to DSI */
- ret = dm_i2c_reg_write(dev, TPS80032_LDO1_CFG_VOLTAGE, 0x03);
- if (ret)
- log_debug("avdd_dsi_csi voltage set failed: %d\n", ret);
-
- /* TPS80032: LDO1_REG enable */
- ret = dm_i2c_reg_write(dev, TPS80032_LDO1_CFG_STATE, 0x01);
- if (ret)
- log_debug("avdd_dsi_csi enable failed: %d\n", ret);
-}
-
-/*
- * Routine: pin_mux_mmc
- * Description: setup the MMC muxes, power rails, etc.
- */
-void pin_mux_mmc(void)
-{
- /* Bring up DSI power */
- tps80032_voltage_init();
-}
-#endif /* MMC */
#if defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP)
int ft_board_setup(void *blob, struct bd_info *bd)
diff --git a/board/lego/ev3/legoev3.c b/board/lego/ev3/legoev3.c
index 8349260..43afe59 100644
--- a/board/lego/ev3/legoev3.c
+++ b/board/lego/ev3/legoev3.c
@@ -4,7 +4,7 @@
*
* Based on da850evm.c
*
- * Copyright (C) 2010 Texas Instruments Incorporated - http://www.ti.com/
+ * Copyright (C) 2010 Texas Instruments Incorporated - https://www.ti.com/
*
* Based on da830evm.c. Original Copyrights follow:
*
diff --git a/board/lg/x3-t30/x3-t30-spl.c b/board/lg/x3-t30/x3-t30-spl.c
index 864f2de..00f79dd 100644
--- a/board/lg/x3-t30/x3-t30-spl.c
+++ b/board/lg/x3-t30/x3-t30-spl.c
@@ -9,7 +9,7 @@
* Svyatoslav Ryhel <clamor95@gmail.com>
*/
-#include <common.h>
+#include <asm/arch/tegra.h>
#include <asm/arch-tegra/tegra_i2c.h>
#include <linux/delay.h>
diff --git a/board/lg/x3-t30/x3-t30.c b/board/lg/x3-t30/x3-t30.c
index a08e00d..6b9169b 100644
--- a/board/lg/x3-t30/x3-t30.c
+++ b/board/lg/x3-t30/x3-t30.c
@@ -7,60 +7,13 @@
* Svyatoslav Ryhel <clamor95@gmail.com>
*/
-#include <common.h>
#include <dm.h>
#include <fdt_support.h>
-#include <i2c.h>
-#include <log.h>
#include <asm/arch/pinmux.h>
#include <asm/arch/clock.h>
-#include <asm/arch/gpio.h>
-#include <asm/arch/tegra.h>
#include <asm/arch-tegra/fuse.h>
-#include <asm/gpio.h>
-#include <linux/delay.h>
-#include "pinmux-config-x3.h"
-
-#define MAX77663_I2C_ADDR 0x1C
-
-#define MAX77663_REG_SD2 0x18
-#define MAX77663_REG_LDO2 0x27
-#define MAX77663_REG_LDO3 0x29
-#define MAX77663_REG_LDO5 0x2D
-#define MAX77663_REG_ONOFF_CFG1 0x41
-#define ONOFF_PWR_OFF BIT(1)
-
-#ifdef CONFIG_CMD_POWEROFF
-int do_poweroff(struct cmd_tbl *cmdtp, int flag,
- int argc, char *const argv[])
-{
- struct udevice *dev;
- uchar data_buffer[1];
- int ret;
-
- ret = i2c_get_chip_for_busnum(0, MAX77663_I2C_ADDR, 1, &dev);
- if (ret) {
- log_debug("cannot find PMIC I2C chip\n");
- return 0;
- }
-
- ret = dm_i2c_read(dev, MAX77663_REG_ONOFF_CFG1, data_buffer, 1);
- if (ret)
- return ret;
- data_buffer[0] |= ONOFF_PWR_OFF;
-
- ret = dm_i2c_write(dev, MAX77663_REG_ONOFF_CFG1, data_buffer, 1);
- if (ret)
- return ret;
-
- /* wait some time and then print error */
- mdelay(5000);
-
- printf("Failed to power off!!!\n");
- return 1;
-}
-#endif
+#include "pinmux-config-x3.h"
/*
* Routine: pinmux_init
@@ -82,50 +35,6 @@
#endif
}
-#ifdef CONFIG_MMC_SDHCI_TEGRA
-static void max77663_voltage_init(void)
-{
- struct udevice *dev;
- int ret;
-
- ret = i2c_get_chip_for_busnum(0, MAX77663_I2C_ADDR, 1, &dev);
- if (ret) {
- log_debug("cannot find PMIC I2C chip\n");
- return;
- }
-
- /* 0x60 for 1.8v, bit7:0 = voltage */
- ret = dm_i2c_reg_write(dev, MAX77663_REG_SD2, 0x60);
- if (ret)
- log_debug("vdd_1v8_vio set failed: %d\n", ret);
-
- /* 0xF2 for 3.30v, enabled: bit7:6 = 11 = enable, bit5:0 = voltage */
- ret = dm_i2c_reg_write(dev, MAX77663_REG_LDO2, 0xF2);
- if (ret)
- log_debug("avdd_usb set failed: %d\n", ret);
-
- /* 0xEC for 3.00v, enabled: bit7:6 = 11 = enable, bit5:0 = voltage */
- ret = dm_i2c_reg_write(dev, MAX77663_REG_LDO3, 0xEC);
- if (ret)
- log_debug("vdd_usd set failed: %d\n", ret);
-
- /* 0xE9 for 2.85v, enabled: bit7:6 = 11 = enable, bit5:0 = voltage */
- ret = dm_i2c_reg_write(dev, MAX77663_REG_LDO5, 0xE9);
- if (ret)
- log_debug("vcore_emmc set failed: %d\n", ret);
-}
-
-/*
- * Routine: pin_mux_mmc
- * Description: setup the MMC muxes, power rails, etc.
- */
-void pin_mux_mmc(void)
-{
- /* Bring up uSD and eMMC power */
- max77663_voltage_init();
-}
-#endif /* MMC */
-
int nvidia_board_init(void)
{
/* Set up panel bridge clocks */
diff --git a/board/logicpd/am3517evm/Makefile b/board/logicpd/am3517evm/Makefile
index c07a98e9..c7da6e3f 100644
--- a/board/logicpd/am3517evm/Makefile
+++ b/board/logicpd/am3517evm/Makefile
@@ -4,6 +4,6 @@
#
# Based on ti/evm/Makefile
#
-# Copyright (C) 2010 Texas Instruments Incorporated - http://www.ti.com/
+# Copyright (C) 2010 Texas Instruments Incorporated - https://www.ti.com/
obj-y := am3517evm.o
diff --git a/board/logicpd/am3517evm/am3517evm.c b/board/logicpd/am3517evm/am3517evm.c
index e787441..e69a73f 100644
--- a/board/logicpd/am3517evm/am3517evm.c
+++ b/board/logicpd/am3517evm/am3517evm.c
@@ -7,7 +7,7 @@
* Based on ti/evm/evm.c
*
* Copyright (C) 2010
- * Texas Instruments Incorporated - http://www.ti.com/
+ * Texas Instruments Incorporated - https://www.ti.com/
*/
#include <common.h>
diff --git a/board/logicpd/am3517evm/am3517evm.h b/board/logicpd/am3517evm/am3517evm.h
index aec2b41..283b453 100644
--- a/board/logicpd/am3517evm/am3517evm.h
+++ b/board/logicpd/am3517evm/am3517evm.h
@@ -7,7 +7,7 @@
* Based on ti/evm/evm.h
*
* Copyright (C) 2010
- * Texas Instruments Incorporated - http://www.ti.com/
+ * Texas Instruments Incorporated - https://www.ti.com/
*/
#ifndef _AM3517EVM_H_
diff --git a/board/nuvoton/arbel_evb/Kconfig b/board/nuvoton/arbel_evb/Kconfig
index 33c589f..ed1c1ad 100644
--- a/board/nuvoton/arbel_evb/Kconfig
+++ b/board/nuvoton/arbel_evb/Kconfig
@@ -15,4 +15,5 @@
help
Reserve memory for ECC/GFX/OPTEE/TIP/CP.
+source "board/nuvoton/common/Kconfig"
endif
diff --git a/board/nuvoton/arbel_evb/arbel_evb.c b/board/nuvoton/arbel_evb/arbel_evb.c
index 59e1a42..8fc56c1 100644
--- a/board/nuvoton/arbel_evb/arbel_evb.c
+++ b/board/nuvoton/arbel_evb/arbel_evb.c
@@ -7,6 +7,7 @@
#include <dm.h>
#include <asm/io.h>
#include <asm/arch/gcr.h>
+#include "../common/uart.h"
#define SR_MII_CTRL_SWR_BIT15 15
@@ -90,3 +91,9 @@
return 0;
}
+int last_stage_init(void)
+{
+ board_set_console();
+
+ return 0;
+}
diff --git a/board/nuvoton/common/Kconfig b/board/nuvoton/common/Kconfig
new file mode 100644
index 0000000..61de7bc
--- /dev/null
+++ b/board/nuvoton/common/Kconfig
@@ -0,0 +1,9 @@
+if ARCH_NPCM
+
+config SYS_SKIP_UART_INIT
+ bool "Skip UART initialization"
+ depends on NPCM_SERIAL
+ help
+ Select this if the UART you want to use is already
+ initialized by the time U-Boot starts its execution.
+endif
diff --git a/board/nuvoton/common/Makefile b/board/nuvoton/common/Makefile
new file mode 100644
index 0000000..8fd83b2
--- /dev/null
+++ b/board/nuvoton/common/Makefile
@@ -0,0 +1 @@
+obj-$(CONFIG_SYS_SKIP_UART_INIT) += uart.o
diff --git a/board/nuvoton/common/uart.c b/board/nuvoton/common/uart.c
new file mode 100644
index 0000000..b35c795
--- /dev/null
+++ b/board/nuvoton/common/uart.c
@@ -0,0 +1,70 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (c) 2023 Nuvoton Technology Corp.
+ */
+
+#include <clk.h>
+#include <dm.h>
+#include <env.h>
+#include <serial.h>
+#include <linux/delay.h>
+
+#define UART_DLL 0x0
+#define UART_DLM 0x4
+#define UART_LCR 0xc
+#define LCR_DLAB BIT(7)
+
+void board_set_console(void)
+{
+ const unsigned long baudrate_table[] = CFG_SYS_BAUDRATE_TABLE;
+ struct udevice *dev = gd->cur_serial_dev;
+ unsigned int baudrate, max_delta;
+ void __iomem *uart_reg;
+ struct clk clk;
+ char string[32];
+ u32 uart_clk;
+ u8 dll, dlm;
+ u16 divisor;
+ int ret, i;
+
+ if (!dev)
+ return;
+
+ uart_reg = dev_read_addr_ptr(dev);
+ ret = clk_get_by_index(dev, 0, &clk);
+ if (ret)
+ return;
+
+ uart_clk = clk_get_rate(&clk);
+ setbits_8(uart_reg + UART_LCR, LCR_DLAB);
+ dll = readb(uart_reg + UART_DLL);
+ dlm = readb(uart_reg + UART_DLM);
+ clrbits_8(uart_reg + UART_LCR, LCR_DLAB);
+ divisor = dll | (dlm << 8);
+ baudrate = uart_clk / ((16 * (divisor + 2)));
+ for (i = 0; i < ARRAY_SIZE(baudrate_table); ++i) {
+ max_delta = baudrate_table[i] / 20;
+ if (abs(baudrate - baudrate_table[i]) < max_delta) {
+ /* The baudrate is supported */
+ gd->baudrate = baudrate_table[i];
+ break;
+ }
+ }
+
+ if (i == ARRAY_SIZE(baudrate_table)) {
+ /* current baudrate is not suitable, set to default */
+ divisor = DIV_ROUND_CLOSEST(uart_clk, 16 * gd->baudrate) - 2;
+ setbits_8(uart_reg + UART_LCR, LCR_DLAB);
+ writeb(divisor & 0xff, uart_reg + UART_DLL);
+ writeb(divisor >> 8, uart_reg + UART_DLM);
+ clrbits_8(uart_reg + UART_LCR, LCR_DLAB);
+ udelay(100);
+ printf("\r\nUART(source %u): change baudrate from %u to %u\n",
+ uart_clk, baudrate, uart_clk / ((16 * (divisor + 2))));
+ }
+
+ debug("Set env baudrate=%u\n", gd->baudrate);
+ snprintf(string, sizeof(string), "ttyS0,%un8", gd->baudrate);
+ env_set("console", string);
+
+}
diff --git a/board/nuvoton/common/uart.h b/board/nuvoton/common/uart.h
new file mode 100644
index 0000000..9cc8952
--- /dev/null
+++ b/board/nuvoton/common/uart.h
@@ -0,0 +1,11 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (c) 2023 Nuvoton Technology Corp.
+ */
+
+#ifndef _NUVOTON_UART_H
+#define _NUVOTON_UART_H
+
+void board_set_console(void);
+
+#endif /* _NUVOTON_COMMON_H */
diff --git a/board/nuvoton/poleg_evb/Kconfig b/board/nuvoton/poleg_evb/Kconfig
index d3f4c1d..6f7f1ef 100644
--- a/board/nuvoton/poleg_evb/Kconfig
+++ b/board/nuvoton/poleg_evb/Kconfig
@@ -22,4 +22,5 @@
endchoice
+source "board/nuvoton/common/Kconfig"
endif
diff --git a/board/nuvoton/poleg_evb/poleg_evb.c b/board/nuvoton/poleg_evb/poleg_evb.c
index 2052af6..7421911 100644
--- a/board/nuvoton/poleg_evb/poleg_evb.c
+++ b/board/nuvoton/poleg_evb/poleg_evb.c
@@ -10,6 +10,7 @@
#include <asm/io.h>
#include <asm/arch/gcr.h>
#include <asm/mach-types.h>
+#include "../common/uart.h"
DECLARE_GLOBAL_DATA_PTR;
@@ -53,3 +54,10 @@
return 0;
}
+
+int last_stage_init(void)
+{
+ board_set_console();
+
+ return 0;
+}
diff --git a/board/phytec/phycore_am335x_r2/Makefile b/board/phytec/phycore_am335x_r2/Makefile
index ff6f8b4..16ac38f 100644
--- a/board/phytec/phycore_am335x_r2/Makefile
+++ b/board/phytec/phycore_am335x_r2/Makefile
@@ -2,7 +2,7 @@
#
# Makefile
#
-# Copyright (C) 2011 Texas Instruments Incorporated - http://www.ti.com/
+# Copyright (C) 2011 Texas Instruments Incorporated - https://www.ti.com/
ifdef CONFIG_SPL_BUILD
obj-y += mux.o
diff --git a/board/phytec/phycore_am335x_r2/board.c b/board/phytec/phycore_am335x_r2/board.c
index eb573d0..5700eff 100644
--- a/board/phytec/phycore_am335x_r2/board.c
+++ b/board/phytec/phycore_am335x_r2/board.c
@@ -4,7 +4,7 @@
*
* Board functions for Phytec phyCORE-AM335x R2 (PCL060 / PCM060) based boards
*
- * Copyright (C) 2011, Texas Instruments, Incorporated - http://www.ti.com/
+ * Copyright (C) 2011, Texas Instruments, Incorporated - https://www.ti.com/
* Copyright (C) 2013 Lars Poeschel, Lemonage Software GmbH
* Copyright (C) 2015 Wadim Egorov, PHYTEC Messtechnik GmbH
* Copyright (C) 2019 DENX Software Engineering GmbH
diff --git a/board/pine64/quartzpro64-rk3588/Kconfig b/board/pine64/quartzpro64-rk3588/Kconfig
new file mode 100644
index 0000000..96aa792
--- /dev/null
+++ b/board/pine64/quartzpro64-rk3588/Kconfig
@@ -0,0 +1,15 @@
+if TARGET_QUARTZPRO64_RK3588
+
+config SYS_BOARD
+ default "quartzpro64-rk3588"
+
+config SYS_VENDOR
+ default "pine64"
+
+config SYS_CONFIG_NAME
+ default "quartzpro64-rk3588"
+
+config BOARD_SPECIFIC_OPTIONS # dummy
+ def_bool y
+
+endif
diff --git a/board/pine64/quartzpro64-rk3588/MAINTAINERS b/board/pine64/quartzpro64-rk3588/MAINTAINERS
new file mode 100644
index 0000000..a7e944b
--- /dev/null
+++ b/board/pine64/quartzpro64-rk3588/MAINTAINERS
@@ -0,0 +1,8 @@
+QUARTZPRO64-RK3588
+M: Tom Fitzhenry <tom@tom-fitzhenry.me.uk>
+S: Maintained
+F: board/pine64/quartzpro64-rk3588
+F: include/configs/quartzpro64-rk3588.h
+F: configs/quartzpro64-rk3588_defconfig
+F: arch/arm/dts/rk3588-quartzpro64.dts
+F: arch/arm/dts/rk3588-quartzpro64-u-boot.dtsi
diff --git a/board/pine64/quartzpro64-rk3588/Makefile b/board/pine64/quartzpro64-rk3588/Makefile
new file mode 100644
index 0000000..47819d9
--- /dev/null
+++ b/board/pine64/quartzpro64-rk3588/Makefile
@@ -0,0 +1,3 @@
+# SPDX-License-Identifier: GPL-2.0+
+
+obj-y += quartzpro64-rk3588.o
diff --git a/board/pine64/quartzpro64-rk3588/quartzpro64-rk3588.c b/board/pine64/quartzpro64-rk3588/quartzpro64-rk3588.c
new file mode 100644
index 0000000..bda804a
--- /dev/null
+++ b/board/pine64/quartzpro64-rk3588/quartzpro64-rk3588.c
@@ -0,0 +1,39 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright 2023 Google, Inc
+ */
+
+#include <fdtdec.h>
+#include <fdt_support.h>
+
+#ifdef CONFIG_OF_BOARD_SETUP
+int quartzpro64_add_reserved_memory_fdt_nodes(void *new_blob)
+{
+ struct fdt_memory gap1 = {
+ .start = 0x3fc000000,
+ .end = 0x3fc4fffff,
+ };
+ struct fdt_memory gap2 = {
+ .start = 0x3fff00000,
+ .end = 0x3ffffffff,
+ };
+ unsigned long flags = FDTDEC_RESERVED_MEMORY_NO_MAP;
+ unsigned int ret;
+
+ /*
+ * Inject the reserved-memory nodes into the DTS
+ */
+ ret = fdtdec_add_reserved_memory(new_blob, "gap1", &gap1, NULL, 0,
+ NULL, flags);
+ if (ret)
+ return ret;
+
+ return fdtdec_add_reserved_memory(new_blob, "gap2", &gap2, NULL, 0,
+ NULL, flags);
+}
+
+int ft_board_setup(void *blob, struct bd_info *bd)
+{
+ return quartzpro64_add_reserved_memory_fdt_nodes(blob);
+}
+#endif
diff --git a/board/samsung/axy17lte/Kconfig b/board/samsung/axy17lte/Kconfig
index a018547..64a4ffa 100644
--- a/board/samsung/axy17lte/Kconfig
+++ b/board/samsung/axy17lte/Kconfig
@@ -1,11 +1,3 @@
-config SYS_CONFIG_NAME
- string "Board configuration name"
- default "exynos78x0-common.h"
- help
- This option contains information about board configuration name.
- Based on this option include/configs/<CONFIG_SYS_CONFIG_NAME>.h header
- will be used for board configuration.
-
if TARGET_A5Y17LTE
config SYS_BOARD
default "axy17lte"
@@ -16,7 +8,7 @@
default "samsung"
config SYS_CONFIG_NAME
- default "a5y17lte"
+ default "exynos78x0-common"
config EXYNOS7880
bool "Exynos 7880 SOC support"
@@ -33,7 +25,7 @@
default "samsung"
config SYS_CONFIG_NAME
- default "a5y17lte"
+ default "exynos78x0-common"
config EXYNOS7880
bool "Exynos 7880 SOC support"
@@ -50,7 +42,7 @@
default "samsung"
config SYS_CONFIG_NAME
- default "a3y17lte"
+ default "exynos78x0-common"
config EXYNOS7870
bool "Exynos 7870 SOC support"
diff --git a/board/siemens/common/board.c b/board/siemens/common/board.c
index 8fa9197..d077751 100644
--- a/board/siemens/common/board.c
+++ b/board/siemens/common/board.c
@@ -6,7 +6,7 @@
*
* Based on:
* U-Boot file:/board/ti/am335x/board.c
- * Copyright (C) 2011, Texas Instruments, Incorporated - http://www.ti.com/
+ * Copyright (C) 2011, Texas Instruments, Incorporated - https://www.ti.com/
*/
#include <common.h>
diff --git a/board/siemens/draco/Kconfig b/board/siemens/draco/Kconfig
index 1eb8a48..0cdf5bc 100644
--- a/board/siemens/draco/Kconfig
+++ b/board/siemens/draco/Kconfig
@@ -1,19 +1,3 @@
-if TARGET_DRACO
-
-config SYS_BOARD
- default "draco"
-
-config SYS_VENDOR
- default "siemens"
-
-config SYS_SOC
- default "am33xx"
-
-config SYS_CONFIG_NAME
- default "draco"
-
-endif
-
if TARGET_THUBAN
config SYS_BOARD
@@ -26,7 +10,7 @@
default "am33xx"
config SYS_CONFIG_NAME
- default "thuban"
+ default "draco-thuban"
endif
@@ -42,7 +26,7 @@
default "am33xx"
config SYS_CONFIG_NAME
- default "rastaban"
+ default "draco-rastaban"
endif
@@ -58,7 +42,7 @@
default "am33xx"
config SYS_CONFIG_NAME
- default "etamin"
+ default "draco-etamin"
config NAND_CS_INIT
def_bool y
diff --git a/board/siemens/draco/MAINTAINERS b/board/siemens/draco/MAINTAINERS
index c73f18c..82e01eb 100644
--- a/board/siemens/draco/MAINTAINERS
+++ b/board/siemens/draco/MAINTAINERS
@@ -1,11 +1,10 @@
DRACO BOARD
-M: Samuel Egli <samuel.egli@siemens.com>
+M: Enrico Leto <enrico.leto@siemens.com>
S: Maintained
F: board/siemens/draco/
-F: include/configs/draco.h
-F: configs/draco_defconfig
-F: configs/etamin_defconfig
-F: include/configs/thuban.h
-F: configs/thuban_defconfig
-F: include/configs/rastaban.h
-F: configs/rastaban_defconfig
+F: configs/draco-etamin_defconfig
+F: configs/draco-rastaban_defconfig
+F: configs/draco-thuban_defconfig
+F: include/configs/draco-etamin.h
+F: include/configs/draco-rastaban.h
+F: include/configs/draco-thuban.h
diff --git a/board/siemens/draco/Makefile b/board/siemens/draco/Makefile
index 3e3394a..e94456a 100644
--- a/board/siemens/draco/Makefile
+++ b/board/siemens/draco/Makefile
@@ -7,7 +7,7 @@
#
# Based on:
# u-boot:/board/ti/am335x/Makefile
-# Copyright (C) 2011 Texas Instruments Incorporated - http://www.ti.com/
+# Copyright (C) 2011 Texas Instruments Incorporated - https://www.ti.com/
ifdef CONFIG_SPL_BUILD
obj-y := mux.o
diff --git a/board/siemens/draco/board.c b/board/siemens/draco/board.c
index 8874659..8b13d23 100644
--- a/board/siemens/draco/board.c
+++ b/board/siemens/draco/board.c
@@ -9,7 +9,7 @@
* Board functions for TI AM335X based boards
* u-boot:/board/ti/am335x/board.c
*
- * Copyright (C) 2011, Texas Instruments, Incorporated - http://www.ti.com/
+ * Copyright (C) 2011, Texas Instruments, Incorporated - https://www.ti.com/
*/
#include <common.h>
diff --git a/board/siemens/draco/board.h b/board/siemens/draco/board.h
index 7c29a45..f027427 100644
--- a/board/siemens/draco/board.h
+++ b/board/siemens/draco/board.h
@@ -9,7 +9,7 @@
* TI AM335x boards information header
* u-boot:/board/ti/am335x/board.h
*
- * Copyright (C) 2011, Texas Instruments, Incorporated - http://www.ti.com/
+ * Copyright (C) 2011, Texas Instruments, Incorporated - https://www.ti.com/
*/
#ifndef _BOARD_H_
diff --git a/board/siemens/draco/mux.c b/board/siemens/draco/mux.c
index 3f2d41b..2632f05 100644
--- a/board/siemens/draco/mux.c
+++ b/board/siemens/draco/mux.c
@@ -7,7 +7,7 @@
*
* Based on:
* u-boot:/board/ti/am335x/mux.c
- * Copyright (C) 2011 Texas Instruments Incorporated - http://www.ti.com/
+ * Copyright (C) 2011 Texas Instruments Incorporated - https://www.ti.com/
*/
#include <common.h>
diff --git a/board/siemens/iot2050/Kconfig b/board/siemens/iot2050/Kconfig
index a6170aa..96dcfc4 100644
--- a/board/siemens/iot2050/Kconfig
+++ b/board/siemens/iot2050/Kconfig
@@ -6,16 +6,6 @@
# Le Jin <le.jin@siemens.com>
# Jan Kiszka <jan.kiszka@siemens.com>
-config TARGET_IOT2050_A53
- bool "IOT2050 running on A53"
- select ARM64
- select SOC_K3_AM654
- select BOARD_LATE_INIT
- select SYS_DISABLE_DCACHE_OPS
- select BINMAN
- help
- This builds U-Boot for the IOT2050 devices.
-
if TARGET_IOT2050_A53
config SYS_BOARD
diff --git a/board/siemens/pxm2/Makefile b/board/siemens/pxm2/Makefile
index 3e3394a..e94456a 100644
--- a/board/siemens/pxm2/Makefile
+++ b/board/siemens/pxm2/Makefile
@@ -7,7 +7,7 @@
#
# Based on:
# u-boot:/board/ti/am335x/Makefile
-# Copyright (C) 2011 Texas Instruments Incorporated - http://www.ti.com/
+# Copyright (C) 2011 Texas Instruments Incorporated - https://www.ti.com/
ifdef CONFIG_SPL_BUILD
obj-y := mux.o
diff --git a/board/siemens/pxm2/board.c b/board/siemens/pxm2/board.c
index 47f19bc..40aee7c 100644
--- a/board/siemens/pxm2/board.c
+++ b/board/siemens/pxm2/board.c
@@ -9,7 +9,7 @@
*
* Board functions for TI AM335X based boards
*
- * Copyright (C) 2011, Texas Instruments, Incorporated - http://www.ti.com/
+ * Copyright (C) 2011, Texas Instruments, Incorporated - https://www.ti.com/
*/
#include <common.h>
diff --git a/board/siemens/pxm2/board.h b/board/siemens/pxm2/board.h
index af21fc4..9067e4d 100644
--- a/board/siemens/pxm2/board.h
+++ b/board/siemens/pxm2/board.h
@@ -9,7 +9,7 @@
* TI AM335x boards information header
* u-boot:/board/ti/am335x/board.h
*
- * Copyright (C) 2011, Texas Instruments, Incorporated - http://www.ti.com/
+ * Copyright (C) 2011, Texas Instruments, Incorporated - https://www.ti.com/
*/
#ifndef _BOARD_H_
diff --git a/board/siemens/pxm2/mux.c b/board/siemens/pxm2/mux.c
index 2f35bb4..d21ef47 100644
--- a/board/siemens/pxm2/mux.c
+++ b/board/siemens/pxm2/mux.c
@@ -8,7 +8,7 @@
* Based on:
* u-boot:/board/ti/am335x/mux.c
*
- * Copyright (C) 2011 Texas Instruments Incorporated - http://www.ti.com/
+ * Copyright (C) 2011 Texas Instruments Incorporated - https://www.ti.com/
*/
#include <common.h>
diff --git a/board/siemens/pxm2/pmic.h b/board/siemens/pxm2/pmic.h
index 3766046..f4ce7f1 100644
--- a/board/siemens/pxm2/pmic.h
+++ b/board/siemens/pxm2/pmic.h
@@ -4,7 +4,7 @@
* (C) Heiko Schocher, DENX Software Engineering, hs@denx.de.
*
* Based on:
- * Copyright (C) 2011 Texas Instruments Incorporated - http://www.ti.com/
+ * Copyright (C) 2011 Texas Instruments Incorporated - https://www.ti.com/
*/
#ifndef PMIC_H
#define PMIC_H
diff --git a/board/siemens/rut/Makefile b/board/siemens/rut/Makefile
index 3e3394a..e94456a 100644
--- a/board/siemens/rut/Makefile
+++ b/board/siemens/rut/Makefile
@@ -7,7 +7,7 @@
#
# Based on:
# u-boot:/board/ti/am335x/Makefile
-# Copyright (C) 2011 Texas Instruments Incorporated - http://www.ti.com/
+# Copyright (C) 2011 Texas Instruments Incorporated - https://www.ti.com/
ifdef CONFIG_SPL_BUILD
obj-y := mux.o
diff --git a/board/siemens/rut/board.c b/board/siemens/rut/board.c
index a8b196a..bad0b71 100644
--- a/board/siemens/rut/board.c
+++ b/board/siemens/rut/board.c
@@ -7,7 +7,7 @@
* Based on:
* u-boot:/board/ti/am335x/board.c
*
- * Copyright (C) 2011, Texas Instruments, Incorporated - http://www.ti.com/
+ * Copyright (C) 2011, Texas Instruments, Incorporated - https://www.ti.com/
*/
#include <common.h>
diff --git a/board/siemens/rut/board.h b/board/siemens/rut/board.h
index af21fc4..9067e4d 100644
--- a/board/siemens/rut/board.h
+++ b/board/siemens/rut/board.h
@@ -9,7 +9,7 @@
* TI AM335x boards information header
* u-boot:/board/ti/am335x/board.h
*
- * Copyright (C) 2011, Texas Instruments, Incorporated - http://www.ti.com/
+ * Copyright (C) 2011, Texas Instruments, Incorporated - https://www.ti.com/
*/
#ifndef _BOARD_H_
diff --git a/board/siemens/rut/mux.c b/board/siemens/rut/mux.c
index d80120b..894a9bf 100644
--- a/board/siemens/rut/mux.c
+++ b/board/siemens/rut/mux.c
@@ -8,7 +8,7 @@
* Based on:
* u-boot:/board/ti/am335x/mux.c
*
- * Copyright (C) 2011 Texas Instruments Incorporated - http://www.ti.com/
+ * Copyright (C) 2011 Texas Instruments Incorporated - https://www.ti.com/
*/
#include <common.h>
diff --git a/board/solidrun/mx6cuboxi/mx6cuboxi.c b/board/solidrun/mx6cuboxi/mx6cuboxi.c
index e119330..8edabf4 100644
--- a/board/solidrun/mx6cuboxi/mx6cuboxi.c
+++ b/board/solidrun/mx6cuboxi/mx6cuboxi.c
@@ -381,6 +381,7 @@
return (mmc_get_op_cond(mmc, true) < 0) ? 0 : 1;
}
+/* Override the default implementation, DT model is not accurate */
int checkboard(void)
{
request_detect_gpios();
@@ -496,12 +497,6 @@
}
#endif
-/* Override the default implementation, DT model is not accurate */
-int show_board_info(void)
-{
- return checkboard();
-}
-
int board_late_init(void)
{
#ifdef CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG
diff --git a/board/sunxi/MAINTAINERS b/board/sunxi/MAINTAINERS
index 4bbe3f6..0061437 100644
--- a/board/sunxi/MAINTAINERS
+++ b/board/sunxi/MAINTAINERS
@@ -236,6 +236,11 @@
S: Maintained
F: configs/icnova-a20-swac_defconfig
+ICnova-A20-ADB4006 BOARD
+M: Ludwig Kormann <ludwig.kormann@ict42.de>
+S: Maintained
+F: configs/icnova-a20-adb4006_defconfig
+
ITEAD IBOX BOARD
M: Marcus Cooper <codekipper@gmail.com>
S: Maintained
diff --git a/board/sunxi/board.c b/board/sunxi/board.c
index 39ecbe9..8c12c8d 100644
--- a/board/sunxi/board.c
+++ b/board/sunxi/board.c
@@ -34,6 +34,7 @@
#include <asm/global_data.h>
#include <linux/delay.h>
#include <linux/printk.h>
+#include <linux/types.h>
#ifndef CONFIG_ARM64
#include <asm/armv7.h>
#endif
@@ -568,7 +569,8 @@
#if defined CONFIG_AXP152_POWER || defined CONFIG_AXP209_POWER || \
defined CONFIG_AXP221_POWER || defined CONFIG_AXP305_POWER || \
- defined CONFIG_AXP809_POWER || defined CONFIG_AXP818_POWER
+ defined CONFIG_AXP809_POWER || defined CONFIG_AXP818_POWER || \
+ defined CONFIG_AXP313_POWER
power_failed = axp_init();
if (IS_ENABLED(CONFIG_AXP_DISABLE_BOOT_ON_POWERON) && !power_failed) {
@@ -581,50 +583,46 @@
}
}
-#if defined CONFIG_AXP221_POWER || defined CONFIG_AXP809_POWER || \
- defined CONFIG_AXP818_POWER
+#ifdef CONFIG_AXP_DCDC1_VOLT
power_failed |= axp_set_dcdc1(CONFIG_AXP_DCDC1_VOLT);
+ power_failed |= axp_set_dcdc5(CONFIG_AXP_DCDC5_VOLT);
#endif
-#if !defined(CONFIG_AXP305_POWER)
+#ifdef CONFIG_AXP_DCDC2_VOLT
power_failed |= axp_set_dcdc2(CONFIG_AXP_DCDC2_VOLT);
power_failed |= axp_set_dcdc3(CONFIG_AXP_DCDC3_VOLT);
#endif
-#if !defined(CONFIG_AXP209_POWER) && !defined(CONFIG_AXP818_POWER)
+#ifdef CONFIG_AXP_DCDC4_VOLT
power_failed |= axp_set_dcdc4(CONFIG_AXP_DCDC4_VOLT);
#endif
-#if defined CONFIG_AXP221_POWER || defined CONFIG_AXP809_POWER || \
- defined CONFIG_AXP818_POWER
- power_failed |= axp_set_dcdc5(CONFIG_AXP_DCDC5_VOLT);
-#endif
-#if defined CONFIG_AXP221_POWER || defined CONFIG_AXP809_POWER || \
- defined CONFIG_AXP818_POWER
+#ifdef CONFIG_AXP_ALDO1_VOLT
power_failed |= axp_set_aldo1(CONFIG_AXP_ALDO1_VOLT);
#endif
-#if !defined(CONFIG_AXP305_POWER)
+#ifdef CONFIG_AXP_ALDO2_VOLT
power_failed |= axp_set_aldo2(CONFIG_AXP_ALDO2_VOLT);
#endif
-#if !defined(CONFIG_AXP152_POWER) && !defined(CONFIG_AXP305_POWER)
+#ifdef CONFIG_AXP_ALDO3_VOLT
power_failed |= axp_set_aldo3(CONFIG_AXP_ALDO3_VOLT);
#endif
-#ifdef CONFIG_AXP209_POWER
+#ifdef CONFIG_AXP_ALDO4_VOLT
power_failed |= axp_set_aldo4(CONFIG_AXP_ALDO4_VOLT);
#endif
-#if defined(CONFIG_AXP221_POWER) || defined(CONFIG_AXP809_POWER) || \
- defined(CONFIG_AXP818_POWER)
+#ifdef CONFIG_AXP_DLDO1_VOLT
power_failed |= axp_set_dldo(1, CONFIG_AXP_DLDO1_VOLT);
power_failed |= axp_set_dldo(2, CONFIG_AXP_DLDO2_VOLT);
-#if !defined CONFIG_AXP809_POWER
+#endif
+#ifdef CONFIG_AXP_DLDO3_VOLT
power_failed |= axp_set_dldo(3, CONFIG_AXP_DLDO3_VOLT);
power_failed |= axp_set_dldo(4, CONFIG_AXP_DLDO4_VOLT);
#endif
+#ifdef CONFIG_AXP_ELDO1_VOLT
power_failed |= axp_set_eldo(1, CONFIG_AXP_ELDO1_VOLT);
power_failed |= axp_set_eldo(2, CONFIG_AXP_ELDO2_VOLT);
power_failed |= axp_set_eldo(3, CONFIG_AXP_ELDO3_VOLT);
#endif
-#ifdef CONFIG_AXP818_POWER
+#ifdef CONFIG_AXP_FLDO1_VOLT
power_failed |= axp_set_fldo(1, CONFIG_AXP_FLDO1_VOLT);
power_failed |= axp_set_fldo(2, CONFIG_AXP_FLDO2_VOLT);
power_failed |= axp_set_fldo(3, CONFIG_AXP_FLDO3_VOLT);
@@ -633,7 +631,7 @@
#if defined CONFIG_AXP809_POWER || defined CONFIG_AXP818_POWER
power_failed |= axp_set_sw(IS_ENABLED(CONFIG_AXP_SW_ON));
#endif
-#endif
+#endif /* CONFIG_AXPxxx_POWER */
printf("DRAM:");
gd->ram_size = sunxi_dram_init();
printf(" %d MiB\n", (int)(gd->ram_size >> 20));
@@ -941,7 +939,7 @@
#ifdef CONFIG_PINE64_DT_SELECTION
if (strstr(best_dt_name, "-pine64-plus")) {
/* Differentiate the Pine A64 boards by their DRAM size. */
- if ((gd->ram_size == 512 * 1024 * 1024))
+ if (gd->ram_size == SZ_512M)
best_dt_name = "sun50i-a64-pine64";
}
#endif
diff --git a/board/tcl/sl50/board.c b/board/tcl/sl50/board.c
index 839a692..3f7d42f 100644
--- a/board/tcl/sl50/board.c
+++ b/board/tcl/sl50/board.c
@@ -4,7 +4,7 @@
*
* Board functions for TCL SL50 board
*
- * Copyright (C) 2011, Texas Instruments, Incorporated - http://www.ti.com/
+ * Copyright (C) 2011, Texas Instruments, Incorporated - https://www.ti.com/
*/
#include <common.h>
diff --git a/board/tcl/sl50/board.h b/board/tcl/sl50/board.h
index b8b9ed7..e624677 100644
--- a/board/tcl/sl50/board.h
+++ b/board/tcl/sl50/board.h
@@ -4,7 +4,7 @@
*
* TCL SL50 boards information header
*
- * Copyright (C) 2011, Texas Instruments, Incorporated - http://www.ti.com/
+ * Copyright (C) 2011, Texas Instruments, Incorporated - https://www.ti.com/
*/
#ifndef _BOARD_H_
diff --git a/board/tcl/sl50/mux.c b/board/tcl/sl50/mux.c
index b0a1dad..ab90881 100644
--- a/board/tcl/sl50/mux.c
+++ b/board/tcl/sl50/mux.c
@@ -2,7 +2,7 @@
/*
* mux.c
*
- * Copyright (C) 2011, Texas Instruments, Incorporated - http://www.ti.com/
+ * Copyright (C) 2011, Texas Instruments, Incorporated - https://www.ti.com/
*/
#include <common.h>
diff --git a/board/theobroma-systems/ringneck_px30/ringneck-px30.c b/board/theobroma-systems/ringneck_px30/ringneck-px30.c
index bb1bb4a..537ce0d 100644
--- a/board/theobroma-systems/ringneck_px30/ringneck-px30.c
+++ b/board/theobroma-systems/ringneck_px30/ringneck-px30.c
@@ -16,12 +16,14 @@
#include <usb.h>
#include <dm/pinctrl.h>
#include <dm/uclass-internal.h>
+#include <asm/gpio.h>
#include <asm/io.h>
#include <asm/setup.h>
#include <asm/arch-rockchip/clock.h>
#include <asm/arch-rockchip/hardware.h>
#include <asm/arch-rockchip/periph.h>
#include <asm/arch-rockchip/misc.h>
+#include <linux/delay.h>
#include <power/regulator.h>
#include <u-boot/sha256.h>
@@ -169,3 +171,54 @@
return 0;
}
+
+#define STM32_RST 100 /* GPIO3_A4 */
+#define STM32_BOOT 101 /* GPIO3_A5 */
+
+void spl_board_init(void)
+{
+ /*
+ * Glitches on STM32_BOOT and STM32_RST lines during poweroff or power
+ * on may put the STM32 companion microcontroller into DFU mode, let's
+ * always reset it into normal mode instead.
+ * Toggling the STM32_RST line is safe to do with the ATtiny companion
+ * microcontroller variant because it will not trigger an MCU reset
+ * since only a UPDI reset command will. Since a UPDI reset is difficult
+ * to mistakenly trigger, glitches to the lines are theoretically also
+ * incapable of triggering an actual ATtiny reset.
+ */
+ int ret;
+
+ ret = gpio_request(STM32_RST, "STM32_RST");
+ if (ret) {
+ debug("Failed to request STM32_RST\n");
+ return;
+ }
+
+ ret = gpio_request(STM32_BOOT, "STM32_BOOT");
+ if (ret) {
+ debug("Failed to request STM32_BOOT\n");
+ return;
+ }
+
+ /* Rely on HW pull-down for inactive level */
+ ret = gpio_direction_input(STM32_BOOT);
+ if (ret) {
+ debug("Failed to configure STM32_BOOT as input\n");
+ return;
+ }
+
+ ret = gpio_direction_output(STM32_RST, 0);
+ if (ret) {
+ debug("Failed to configure STM32_RST as output low\n");
+ return;
+ }
+
+ mdelay(1);
+
+ ret = gpio_direction_output(STM32_RST, 1);
+ if (ret) {
+ debug("Failed to configure STM32_RST as output high\n");
+ return;
+ }
+}
diff --git a/board/ti/am335x/Makefile b/board/ti/am335x/Makefile
index 3ccf66b..2b1e21a 100644
--- a/board/ti/am335x/Makefile
+++ b/board/ti/am335x/Makefile
@@ -2,7 +2,7 @@
#
# Makefile
#
-# Copyright (C) 2011 Texas Instruments Incorporated - http://www.ti.com/
+# Copyright (C) 2011 Texas Instruments Incorporated - https://www.ti.com/
ifeq ($(CONFIG_$(SPL_)SKIP_LOWLEVEL_INIT),)
obj-y := mux.o
diff --git a/board/ti/am335x/board.c b/board/ti/am335x/board.c
index ecb9fa0..34f987c 100644
--- a/board/ti/am335x/board.c
+++ b/board/ti/am335x/board.c
@@ -4,7 +4,7 @@
*
* Board functions for TI AM335X based boards
*
- * Copyright (C) 2011, Texas Instruments, Incorporated - http://www.ti.com/
+ * Copyright (C) 2011, Texas Instruments, Incorporated - https://www.ti.com/
*/
#include <common.h>
diff --git a/board/ti/am335x/board.h b/board/ti/am335x/board.h
index c296211..1284c16 100644
--- a/board/ti/am335x/board.h
+++ b/board/ti/am335x/board.h
@@ -4,7 +4,7 @@
*
* TI AM335x boards information header
*
- * Copyright (C) 2011, Texas Instruments, Incorporated - http://www.ti.com/
+ * Copyright (C) 2011, Texas Instruments, Incorporated - https://www.ti.com/
*/
#ifndef _BOARD_H_
diff --git a/board/ti/am335x/mux.c b/board/ti/am335x/mux.c
index 7d31ade..0bad154 100644
--- a/board/ti/am335x/mux.c
+++ b/board/ti/am335x/mux.c
@@ -1,7 +1,7 @@
/*
* mux.c
*
- * Copyright (C) 2011 Texas Instruments Incorporated - http://www.ti.com/
+ * Copyright (C) 2011 Texas Instruments Incorporated - https://www.ti.com/
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
diff --git a/board/ti/am43xx/Makefile b/board/ti/am43xx/Makefile
index 8dc1d89..b618f63 100644
--- a/board/ti/am43xx/Makefile
+++ b/board/ti/am43xx/Makefile
@@ -2,7 +2,7 @@
#
# Makefile
#
-# Copyright (C) 2013 Texas Instruments Incorporated - http://www.ti.com/
+# Copyright (C) 2013 Texas Instruments Incorporated - https://www.ti.com/
ifeq ($(CONFIG_$(SPL_)SKIP_LOWLEVEL_INIT),)
obj-y := mux.o
diff --git a/board/ti/am43xx/board.c b/board/ti/am43xx/board.c
index 58bfe7c..ea0d0b9 100644
--- a/board/ti/am43xx/board.c
+++ b/board/ti/am43xx/board.c
@@ -4,7 +4,7 @@
*
* Board functions for TI AM43XX based boards
*
- * Copyright (C) 2013, Texas Instruments, Incorporated - http://www.ti.com/
+ * Copyright (C) 2013, Texas Instruments, Incorporated - https://www.ti.com/
*/
#include <common.h>
diff --git a/board/ti/am43xx/board.h b/board/ti/am43xx/board.h
index 06b7374..37a169a 100644
--- a/board/ti/am43xx/board.h
+++ b/board/ti/am43xx/board.h
@@ -5,7 +5,7 @@
* TI AM437x boards information header
* Derived from AM335x board.
*
- * Copyright (C) 2013, Texas Instruments, Incorporated - http://www.ti.com/
+ * Copyright (C) 2013, Texas Instruments, Incorporated - https://www.ti.com/
*/
#ifndef _BOARD_H_
diff --git a/board/ti/am43xx/mux.c b/board/ti/am43xx/mux.c
index f59e93a..463f1cc 100644
--- a/board/ti/am43xx/mux.c
+++ b/board/ti/am43xx/mux.c
@@ -2,7 +2,7 @@
/*
* mux.c
*
- * Copyright (C) 2013 Texas Instruments Incorporated - http://www.ti.com/
+ * Copyright (C) 2013 Texas Instruments Incorporated - https://www.ti.com/
*/
#include <common.h>
diff --git a/board/ti/am57xx/board.c b/board/ti/am57xx/board.c
index 9ea507a..b004a89 100644
--- a/board/ti/am57xx/board.c
+++ b/board/ti/am57xx/board.c
@@ -1,6 +1,6 @@
// SPDX-License-Identifier: GPL-2.0+
/*
- * Copyright (C) 2014 Texas Instruments Incorporated - http://www.ti.com
+ * Copyright (C) 2014 Texas Instruments Incorporated - https://www.ti.com
*
* Author: Felipe Balbi <balbi@ti.com>
*
diff --git a/board/ti/am57xx/mux_data.h b/board/ti/am57xx/mux_data.h
index 54b7050..f2f428e 100644
--- a/board/ti/am57xx/mux_data.h
+++ b/board/ti/am57xx/mux_data.h
@@ -1,6 +1,6 @@
/* SPDX-License-Identifier: GPL-2.0+ */
/*
- * Copyright (C) 2014 Texas Instruments Incorporated - http://www.ti.com
+ * Copyright (C) 2014 Texas Instruments Incorporated - https://www.ti.com
*
* Author: Felipe Balbi <balbi@ti.com>
*
diff --git a/board/ti/am62ax/Kconfig b/board/ti/am62ax/Kconfig
index 61f289f..51e7b3e 100644
--- a/board/ti/am62ax/Kconfig
+++ b/board/ti/am62ax/Kconfig
@@ -3,32 +3,6 @@
# Copyright (C) 2022 Texas Instruments Incorporated - https://www.ti.com/
#
-choice
- prompt "TI K3 AM62Ax based boards"
- optional
-
-config TARGET_AM62A7_A53_EVM
- bool "TI K3 based AM62A7 EVM running on A53"
- select ARM64
- select BINMAN
- imply BOARD
- imply SPL_BOARD
- imply TI_I2C_BOARD_DETECT
-
-config TARGET_AM62A7_R5_EVM
- bool "TI K3 based AM62A7 EVM running on R5"
- select CPU_V7R
- select SYS_THUMB_BUILD
- select K3_LOAD_SYSFW
- select RAM
- select SPL_RAM
- select K3_DDRSS
- select BINMAN
- imply SYS_K3_SPL_ATF
- imply TI_I2C_BOARD_DETECT
-
-endchoice
-
if TARGET_AM62A7_R5_EVM || TARGET_AM62A7_A53_EVM
config SYS_BOARD
diff --git a/board/ti/am62ax/am62ax.env b/board/ti/am62ax/am62ax.env
index bfed7f3..a6d967e 100644
--- a/board/ti/am62ax/am62ax.env
+++ b/board/ti/am62ax/am62ax.env
@@ -1,16 +1,14 @@
#include <env/ti/ti_common.env>
+#include <env/ti/default_findfdt.env>
#include <env/ti/mmc.env>
-default_device_tree=ti/k3-am62a7-sk.dtb
-findfdt=
- setenv name_fdt ${default_device_tree};
- setenv fdtfile ${name_fdt}
name_kern=Image
console=ttyS2,115200n8
args_all=setenv optargs ${optargs} earlycon=ns16550a,mmio32,0x02800000
${mtdparts}
run_kern=booti ${loadaddr} ${rd_spec} ${fdtaddr}
+boot_targets=mmc1 mmc0 usb pxe dhcp
boot=mmc
mmcdev=1
bootpart=1:2
diff --git a/board/ti/am62x/Kconfig b/board/ti/am62x/Kconfig
index cd17e93..610dacf 100644
--- a/board/ti/am62x/Kconfig
+++ b/board/ti/am62x/Kconfig
@@ -3,28 +3,6 @@
# Copyright (C) 2020-2022 Texas Instruments Incorporated - https://www.ti.com/
# Suman Anna <s-anna@ti.com>
-choice
- prompt "TI K3 AM62x based boards"
- optional
-
-config TARGET_AM625_A53_EVM
- bool "TI K3 based AM625 EVM running on A53"
- select ARM64
- select BINMAN
-
-config TARGET_AM625_R5_EVM
- bool "TI K3 based AM625 EVM running on R5"
- select CPU_V7R
- select SYS_THUMB_BUILD
- select K3_LOAD_SYSFW
- select RAM
- select SPL_RAM
- select K3_DDRSS
- select BINMAN
- imply SYS_K3_SPL_ATF
-
-endchoice
-
if TARGET_AM625_A53_EVM
config SYS_BOARD
diff --git a/board/ti/am62x/MAINTAINERS b/board/ti/am62x/MAINTAINERS
index 6ac4e65..105e741 100644
--- a/board/ti/am62x/MAINTAINERS
+++ b/board/ti/am62x/MAINTAINERS
@@ -6,10 +6,3 @@
F: include/configs/am62x_evm.h
F: configs/am62x_evm_r5_defconfig
F: configs/am62x_evm_a53_defconfig
-
-BEAGLEPLAY BOARD
-M: Nishanth Menon <nm@ti.com>
-M: Robert Nelson <robertcnelson@gmail.com>
-M: Tom Rini <trini@konsulko.com>
-S: Maintained
-N: beagleplay
diff --git a/board/ti/am62x/beagleplay_a53.config b/board/ti/am62x/beagleplay_a53.config
deleted file mode 100644
index f038041..0000000
--- a/board/ti/am62x/beagleplay_a53.config
+++ /dev/null
@@ -1,55 +0,0 @@
-# Defconfig fragment to apply on top of am62x_evm_a53_defconfig
-
-CONFIG_DEFAULT_DEVICE_TREE="k3-am625-beagleplay"
-CONFIG_OF_LIST="k3-am625-beagleplay"
-CONFIG_SPL_OF_LIST="k3-am625-beagleplay"
-CONFIG_BOOTCOMMAND="run set_led_state_start_load;run findfdt; run envboot; bootflow scan -lb;run set_led_state_fail_load"
-CONFIG_EXT4_WRITE=y
-CONFIG_LZO=y
-CONFIG_AUTOBOOT_KEYED=y
-CONFIG_AUTOBOOT_PROMPT="Press SPACE to abort autoboot in %d seconds\n"
-CONFIG_AUTOBOOT_DELAY_STR="d"
-CONFIG_AUTOBOOT_STOP_STR=" "
-# Use the Beagleplay env file
-CONFIG_ENV_SOURCE_FILE="beagleplay"
-# Do not use emmc boot - we will use FS only
-CONFIG_SUPPORT_EMMC_BOOT=n
-CONFIG_MMC_IO_VOLTAGE=y
-# CONFIG_SPL_MMC_IO_VOLTAGE is not set
-CONFIG_MMC_UHS_SUPPORT=y
-# CONFIG_SPL_MMC_UHS_SUPPORT is not set
-CONFIG_MMC_HS200_SUPPORT=y
-# CONFIG_SPL_MMC_HS200_SUPPORT is not set
-# Enable GPIO control
-CONFIG_DM_GPIO=y
-CONFIG_SPL_GPIO=y
-CONFIG_DA8XX_GPIO=y
-CONFIG_CMD_GPIO=y
-CONFIG_CMD_GPIO_READ=y
-# Enable LEDs
-CONFIG_LED=y
-CONFIG_LED_GPIO=y
-CONFIG_SPL_LED=y
-CONFIG_SPL_LED_GPIO=y
-# Enable I2C bus
-CONFIG_SPL_I2C=y
-CONFIG_DM_I2C=y
-CONFIG_SYS_I2C_OMAP24XX=y
-CONFIG_CMD_I2C=y
-# Regulator
-CONFIG_DM_REGULATOR=y
-CONFIG_DM_REGULATOR_FIXED=y
-CONFIG_DM_REGULATOR_GPIO=y
-CONFIG_CMD_REGULATOR=y
-CONFIG_DM_REGULATOR_TPS65219=y
-CONFIG_DM_PMIC=y
-CONFIG_PMIC_TPS65219=y
-CONFIG_CMD_PMIC=y
-# Uses Realtek phy rather than TI phy
-CONFIG_PHY_TI_DP83867=n
-CONFIG_PHY_REALTEK=y
-# No SPI flash on Beagleplay
-CONFIG_SPI=n
-CONFIG_SPI_FLASH=n
-CONFIG_SPL_DM_SPI_FLASH=n
-CONFIG_SPL_SPI_FLASH_SUPPORT=n
diff --git a/board/ti/am62x/beagleplay_r5.config b/board/ti/am62x/beagleplay_r5.config
deleted file mode 100644
index 4ee0375..0000000
--- a/board/ti/am62x/beagleplay_r5.config
+++ /dev/null
@@ -1,15 +0,0 @@
-# Defconfig fragment to apply on top of:
-# am62x_evm_r5_defconfig
-#
-CONFIG_DEFAULT_DEVICE_TREE="k3-am625-r5-beagleplay"
-CONFIG_OF_LIST="k3-am625-r5-beagleplay"
-CONFIG_SPL_OF_LIST="k3-am625-r5-beagleplay"
-# Do spl board init
-CONFIG_SPL_BOARD_INIT=y
-# Do not use emmc boot - we will use FS only
-CONFIG_SUPPORT_EMMC_BOOT=n
-# No SPI flash on Beagleplay
-CONFIG_SPI=n
-CONFIG_SPI_FLASH=n
-CONFIG_SPL_DM_SPI_FLASH=n
-CONFIG_SPL_SPI_FLASH_SUPPORT=n
diff --git a/board/ti/am64x/Kconfig b/board/ti/am64x/Kconfig
index fb596e4..b873476 100644
--- a/board/ti/am64x/Kconfig
+++ b/board/ti/am64x/Kconfig
@@ -2,32 +2,6 @@
#
# Copyright (C) 2020-2021 Texas Instruments Incorporated - https://www.ti.com/
-choice
- prompt "K3 AM64 based boards"
- optional
-
-config TARGET_AM642_A53_EVM
- bool "TI K3 based AM642 EVM running on A53"
- select ARM64
- select BINMAN
- imply BOARD
- imply SPL_BOARD
- imply TI_I2C_BOARD_DETECT
-
-config TARGET_AM642_R5_EVM
- bool "TI K3 based AM642 EVM running on R5"
- select CPU_V7R
- select SYS_THUMB_BUILD
- select K3_LOAD_SYSFW
- select RAM
- select SPL_RAM
- select K3_DDRSS
- select BINMAN
- imply SYS_K3_SPL_ATF
- imply TI_I2C_BOARD_DETECT
-
-endchoice
-
if TARGET_AM642_A53_EVM
config SYS_BOARD
diff --git a/board/ti/am65x/Kconfig b/board/ti/am65x/Kconfig
index 5fd19d6..eb47a25 100644
--- a/board/ti/am65x/Kconfig
+++ b/board/ti/am65x/Kconfig
@@ -1,32 +1,8 @@
# SPDX-License-Identifier: GPL-2.0+
#
-# Copyright (C) 2017-2018 Texas Instruments Incorporated - http://www.ti.com/
+# Copyright (C) 2017-2018 Texas Instruments Incorporated - https://www.ti.com/
# Lokesh Vutla <lokeshvutla@ti.com>
-choice
- prompt "K3 AM65 based boards"
- optional
-
-config TARGET_AM654_A53_EVM
- bool "TI K3 based AM654 EVM running on A53"
- select ARM64
- select SYS_DISABLE_DCACHE_OPS
- select BOARD_LATE_INIT
- select BINMAN
- imply TI_I2C_BOARD_DETECT
-
-config TARGET_AM654_R5_EVM
- bool "TI K3 based AM654 EVM running on R5"
- select CPU_V7R
- select SYS_THUMB_BUILD
- select K3_LOAD_SYSFW
- select K3_AM654_DDRSS
- select BINMAN
- imply SYS_K3_SPL_ATF
- imply TI_I2C_BOARD_DETECT
-
-endchoice
-
if TARGET_AM654_A53_EVM
config SYS_BOARD
diff --git a/board/ti/am65x/Makefile b/board/ti/am65x/Makefile
index 94dddfc..079a86d 100644
--- a/board/ti/am65x/Makefile
+++ b/board/ti/am65x/Makefile
@@ -1,5 +1,5 @@
#
-# Copyright (C) 2017-2018 Texas Instruments Incorporated - http://www.ti.com/
+# Copyright (C) 2017-2018 Texas Instruments Incorporated - https://www.ti.com/
# Lokesh Vutla <lokeshvutla@ti.com>
#
# SPDX-License-Identifier: GPL-2.0+
diff --git a/board/ti/am65x/evm.c b/board/ti/am65x/evm.c
index 97a7095..975eb17 100644
--- a/board/ti/am65x/evm.c
+++ b/board/ti/am65x/evm.c
@@ -2,7 +2,7 @@
/*
* Board specific initialization for AM654 EVM
*
- * Copyright (C) 2017-2018 Texas Instruments Incorporated - http://www.ti.com/
+ * Copyright (C) 2017-2018 Texas Instruments Incorporated - https://www.ti.com/
* Lokesh Vutla <lokeshvutla@ti.com>
*
*/
diff --git a/board/ti/common/Makefile b/board/ti/common/Makefile
index 3172d87b..26bf12e 100644
--- a/board/ti/common/Makefile
+++ b/board/ti/common/Makefile
@@ -1,5 +1,5 @@
# SPDX-License-Identifier: GPL-2.0+
-# Copyright (C) 2015-2016 Texas Instruments Incorporated - http://www.ti.com/
+# Copyright (C) 2015-2016 Texas Instruments Incorporated - https://www.ti.com/
obj-${CONFIG_TI_I2C_BOARD_DETECT} += board_detect.o
obj-${CONFIG_CMD_EXTENSION} += cape_detect.o
diff --git a/board/ti/common/board_detect.c b/board/ti/common/board_detect.c
index ac39b25..0ec6d1a 100644
--- a/board/ti/common/board_detect.c
+++ b/board/ti/common/board_detect.c
@@ -2,7 +2,7 @@
/*
* Library to support early TI EVM EEPROM handling
*
- * Copyright (C) 2015-2016 Texas Instruments Incorporated - http://www.ti.com/
+ * Copyright (C) 2015-2016 Texas Instruments Incorporated - https://www.ti.com/
* Lokesh Vutla
* Steve Kipisz
*/
diff --git a/board/ti/common/board_detect.h b/board/ti/common/board_detect.h
index de7cb52..ca1aa80 100644
--- a/board/ti/common/board_detect.h
+++ b/board/ti/common/board_detect.h
@@ -2,7 +2,7 @@
/*
* Library to support early TI EVM EEPROM handling
*
- * Copyright (C) 2015-2016 Texas Instruments Incorporated - http://www.ti.com
+ * Copyright (C) 2015-2016 Texas Instruments Incorporated - https://www.ti.com
*/
#ifndef __BOARD_DETECT_H
diff --git a/board/ti/j721e/Kconfig b/board/ti/j721e/Kconfig
index e6cb21f..6990f6e 100644
--- a/board/ti/j721e/Kconfig
+++ b/board/ti/j721e/Kconfig
@@ -1,54 +1,8 @@
# SPDX-License-Identifier: GPL-2.0+
#
-# Copyright (C) 2018-2019 Texas Instruments Incorporated - http://www.ti.com/
+# Copyright (C) 2018-2019 Texas Instruments Incorporated - https://www.ti.com/
# Lokesh Vutla <lokeshvutla@ti.com>
-choice
- prompt "K3 J721E based boards"
- optional
-
-config TARGET_J721E_A72_EVM
- bool "TI K3 based J721E EVM running on A72"
- select ARM64
- select BOARD_LATE_INIT
- imply TI_I2C_BOARD_DETECT
- select SYS_DISABLE_DCACHE_OPS
- select BINMAN
-
-config TARGET_J721E_R5_EVM
- bool "TI K3 based J721E EVM running on R5"
- select CPU_V7R
- select SYS_THUMB_BUILD
- select K3_LOAD_SYSFW
- select RAM
- select SPL_RAM
- select K3_DDRSS
- select BINMAN
- imply SYS_K3_SPL_ATF
- imply TI_I2C_BOARD_DETECT
-
-config TARGET_J7200_A72_EVM
- bool "TI K3 based J7200 EVM running on A72"
- select ARM64
- select BOARD_LATE_INIT
- imply TI_I2C_BOARD_DETECT
- select SYS_DISABLE_DCACHE_OPS
- select BINMAN
-
-config TARGET_J7200_R5_EVM
- bool "TI K3 based J7200 EVM running on R5"
- select CPU_V7R
- select SYS_THUMB_BUILD
- select K3_LOAD_SYSFW
- select RAM
- select SPL_RAM
- select K3_DDRSS
- select BINMAN
- imply SYS_K3_SPL_ATF
- imply TI_I2C_BOARD_DETECT
-
-endchoice
-
if TARGET_J721E_A72_EVM
config SYS_BOARD
diff --git a/board/ti/j721e/Makefile b/board/ti/j721e/Makefile
index 97535f5..6e91054 100644
--- a/board/ti/j721e/Makefile
+++ b/board/ti/j721e/Makefile
@@ -1,5 +1,5 @@
#
-# Copyright (C) 2018-2019 Texas Instruments Incorporated - http://www.ti.com/
+# Copyright (C) 2018-2019 Texas Instruments Incorporated - https://www.ti.com/
# Lokesh Vutla <lokeshvutla@ti.com>
#
# SPDX-License-Identifier: GPL-2.0+
diff --git a/board/ti/j721e/evm.c b/board/ti/j721e/evm.c
index de90342..0768385 100644
--- a/board/ti/j721e/evm.c
+++ b/board/ti/j721e/evm.c
@@ -2,26 +2,18 @@
/*
* Board specific initialization for J721E EVM
*
- * Copyright (C) 2018-2019 Texas Instruments Incorporated - http://www.ti.com/
+ * Copyright (C) 2018-2019 Texas Instruments Incorporated - https://www.ti.com/
* Lokesh Vutla <lokeshvutla@ti.com>
*
*/
-#include <env.h>
-#include <fdt_support.h>
#include <generic-phy.h>
#include <image.h>
-#include <init.h>
-#include <log.h>
#include <net.h>
#include <asm/arch/hardware.h>
-#include <asm/global_data.h>
#include <asm/gpio.h>
-#include <asm/io.h>
#include <spl.h>
#include <dm.h>
-#include <dm/uclass-internal.h>
-#include <linux/printk.h>
#include "../common/board_detect.h"
@@ -307,53 +299,54 @@
printf("Detected: %s rev %s\n", ep.name, ep.version);
daughter_card_detect_flags[i] = true;
-#ifndef CONFIG_SPL_BUILD
- int j;
- /*
- * Populate any MAC addresses from daughtercard into the U-Boot
- * environment, starting with a card-specific offset so we can
- * have multiple ext_cards contribute to the MAC pool in a well-
- * defined manner.
- */
- for (j = 0; j < mac_addr_cnt; j++) {
- if (!is_valid_ethaddr((u8 *)mac_addr[j]))
- continue;
+ if (!IS_ENABLED(CONFIG_SPL_BUILD)) {
+ int j;
+ /*
+ * Populate any MAC addresses from daughtercard into the U-Boot
+ * environment, starting with a card-specific offset so we can
+ * have multiple ext_cards contribute to the MAC pool in a well-
+ * defined manner.
+ */
+ for (j = 0; j < mac_addr_cnt; j++) {
+ if (!is_valid_ethaddr((u8 *)mac_addr[j]))
+ continue;
- eth_env_set_enetaddr_by_index("eth",
- ext_cards[i].eth_offset + j,
- (uchar *)mac_addr[j]);
+ eth_env_set_enetaddr_by_index("eth",
+ ext_cards[i].eth_offset + j,
+ (uchar *)mac_addr[j]);
+ }
}
-#endif
}
-#ifndef CONFIG_SPL_BUILD
- char name_overlays[1024] = { 0 };
- for (i = 0; i < ARRAY_SIZE(ext_cards); i++) {
- if (!daughter_card_detect_flags[i])
- continue;
+ if (!IS_ENABLED(CONFIG_SPL_BUILD)) {
+ char name_overlays[1024] = { 0 };
- /* Skip if no overlays are to be added */
- if (!strlen(ext_cards[i].dtbo_name))
- continue;
+ for (i = 0; i < ARRAY_SIZE(ext_cards); i++) {
+ if (!daughter_card_detect_flags[i])
+ continue;
+
+ /* Skip if no overlays are to be added */
+ if (!strlen(ext_cards[i].dtbo_name))
+ continue;
- /*
- * Make sure we are not running out of buffer space by checking
- * if we can fit the new overlay, a trailing space to be used
- * as a separator, plus the terminating zero.
- */
- if (strlen(name_overlays) + strlen(ext_cards[i].dtbo_name) + 2 >
- sizeof(name_overlays))
- return -ENOMEM;
+ /*
+ * Make sure we are not running out of buffer space by checking
+ * if we can fit the new overlay, a trailing space to be used
+ * as a separator, plus the terminating zero.
+ */
+ if (strlen(name_overlays) + strlen(ext_cards[i].dtbo_name) + 2 >
+ sizeof(name_overlays))
+ return -ENOMEM;
- /* Append to our list of overlays */
- strcat(name_overlays, ext_cards[i].dtbo_name);
- strcat(name_overlays, " ");
- }
+ /* Append to our list of overlays */
+ strcat(name_overlays, ext_cards[i].dtbo_name);
+ strcat(name_overlays, " ");
+ }
- /* Apply device tree overlay(s) to the U-Boot environment, if any */
- if (strlen(name_overlays))
- return env_set("name_overlays", name_overlays);
-#endif
+ /* Apply device tree overlay(s) to the U-Boot environment, if any */
+ if (strlen(name_overlays))
+ return env_set("name_overlays", name_overlays);
+ }
return 0;
}
@@ -530,10 +523,8 @@
void spl_board_init(void)
{
-#if defined(CONFIG_ESM_K3) || defined(CONFIG_ESM_PMIC)
struct udevice *dev;
int ret;
-#endif
if ((IS_ENABLED(CONFIG_TARGET_J721E_A72_EVM) ||
IS_ENABLED(CONFIG_TARGET_J7200_A72_EVM)) &&
@@ -542,24 +533,20 @@
probe_daughtercards();
}
-#ifdef CONFIG_ESM_K3
- if (board_ti_k3_is("J721EX-PM2-SOM")) {
+ if (IS_ENABLED(CONFIG_ESM_K3)) {
ret = uclass_get_device_by_driver(UCLASS_MISC,
DM_DRIVER_GET(k3_esm), &dev);
if (ret)
printf("ESM init failed: %d\n", ret);
}
-#endif
-#ifdef CONFIG_ESM_PMIC
- if (board_ti_k3_is("J721EX-PM2-SOM")) {
+ if (IS_ENABLED(CONFIG_ESM_PMIC)) {
ret = uclass_get_device_by_driver(UCLASS_MISC,
DM_DRIVER_GET(pmic_esm),
&dev);
if (ret)
printf("ESM PMIC init failed: %d\n", ret);
}
-#endif
if ((IS_ENABLED(CONFIG_TARGET_J7200_A72_EVM) || IS_ENABLED(CONFIG_TARGET_J721E_A72_EVM)) &&
IS_ENABLED(CONFIG_HBMC_AM654)) {
struct udevice *dev;
diff --git a/board/ti/j721e/j721e.env b/board/ti/j721e/j721e.env
index 8cc8232..cb27bf5 100644
--- a/board/ti/j721e/j721e.env
+++ b/board/ti/j721e/j721e.env
@@ -31,6 +31,7 @@
name_mcur5f0_0fw=/lib/firmware/j7200-mcu-r5f0_0-fw
#endif
+boot_targets=mmc1 mmc0 usb pxe dhcp
boot=mmc
mmcdev=1
bootpart=1:2
diff --git a/board/ti/j721s2/Kconfig b/board/ti/j721s2/Kconfig
index f6d1cb5..40853a8 100644
--- a/board/ti/j721s2/Kconfig
+++ b/board/ti/j721s2/Kconfig
@@ -3,32 +3,6 @@
# Copyright (C) 2021 Texas Instruments Incorporated - https://www.ti.com/
# David Huang <d-huang@ti.com>
-choice
- prompt "K3 J721S2 board"
- optional
-
-config TARGET_J721S2_A72_EVM
- bool "TI K3 based J721S2 EVM running on A72"
- select ARM64
- select BOARD_LATE_INIT
- imply TI_I2C_BOARD_DETECT
- select SYS_DISABLE_DCACHE_OPS
- select BINMAN
-
-config TARGET_J721S2_R5_EVM
- bool "TI K3 based J721S2 EVM running on R5"
- select CPU_V7R
- select SYS_THUMB_BUILD
- select K3_LOAD_SYSFW
- select RAM
- select SPL_RAM
- select K3_DDRSS
- select BINMAN
- imply SYS_K3_SPL_ATF
- imply TI_I2C_BOARD_DETECT
-
-endchoice
-
if TARGET_J721S2_A72_EVM
config SYS_BOARD
diff --git a/board/ti/j721s2/evm.c b/board/ti/j721s2/evm.c
index 7a91138..db71739 100644
--- a/board/ti/j721s2/evm.c
+++ b/board/ti/j721s2/evm.c
@@ -2,7 +2,7 @@
/*
* Board specific initialization for J721S2 EVM
*
- * Copyright (C) 2021 Texas Instruments Incorporated - http://www.ti.com/
+ * Copyright (C) 2021 Texas Instruments Incorporated - https://www.ti.com/
* David Huang <d-huang@ti.com>
*
*/
diff --git a/board/toradex/apalis-imx8/apalis-imx8.c b/board/toradex/apalis-imx8/apalis-imx8.c
index e2bbaba..b351ce6 100644
--- a/board/toradex/apalis-imx8/apalis-imx8.c
+++ b/board/toradex/apalis-imx8/apalis-imx8.c
@@ -215,7 +215,7 @@
build_info();
print_bootinfo();
- return 0;
+ return tdx_checkboard();
}
static enum pcb_rev_t get_pcb_revision(void)
diff --git a/board/toradex/apalis-tk1/apalis-tk1.c b/board/toradex/apalis-tk1/apalis-tk1.c
index 8513431..79a1c92 100644
--- a/board/toradex/apalis-tk1/apalis-tk1.c
+++ b/board/toradex/apalis-tk1/apalis-tk1.c
@@ -95,7 +95,7 @@
{
puts("Model: Toradex Apalis TK1 2GB\n");
- return 0;
+ return tdx_checkboard();
}
#if defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP)
diff --git a/board/toradex/apalis_imx6/apalis_imx6.c b/board/toradex/apalis_imx6/apalis_imx6.c
index fa6b722..dc0e099 100644
--- a/board/toradex/apalis_imx6/apalis_imx6.c
+++ b/board/toradex/apalis_imx6/apalis_imx6.c
@@ -730,7 +730,8 @@
is_cpu_type(MXC_CPU_MX6D) ? "Dual" : "Quad",
(gd->ram_size == 0x80000000) ? "2GB" :
(gd->ram_size == 0x40000000) ? "1GB" : "512MB", it);
- return 0;
+
+ return tdx_checkboard();
}
#if defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP)
diff --git a/board/toradex/apalis_t30/apalis_t30.c b/board/toradex/apalis_t30/apalis_t30.c
index ef71270..b9a2af3 100644
--- a/board/toradex/apalis_t30/apalis_t30.c
+++ b/board/toradex/apalis_t30/apalis_t30.c
@@ -50,7 +50,7 @@
printf("Model: Toradex Apalis T30 %dGB\n",
(gd->ram_size == 0x40000000) ? 1 : 2);
- return 0;
+ return tdx_checkboard();
}
#if defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP)
diff --git a/board/toradex/colibri-imx6ull/colibri-imx6ull.c b/board/toradex/colibri-imx6ull/colibri-imx6ull.c
index 48fdb1e..6c8eeff 100644
--- a/board/toradex/colibri-imx6ull/colibri-imx6ull.c
+++ b/board/toradex/colibri-imx6ull/colibri-imx6ull.c
@@ -206,7 +206,7 @@
{
printf("Model: Toradex Colibri iMX6ULL\n");
- return 0;
+ return tdx_checkboard();
}
#if defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP)
diff --git a/board/toradex/colibri-imx8x/colibri-imx8x.c b/board/toradex/colibri-imx8x/colibri-imx8x.c
index 6c0b097..d8cc72f 100644
--- a/board/toradex/colibri-imx8x/colibri-imx8x.c
+++ b/board/toradex/colibri-imx8x/colibri-imx8x.c
@@ -121,7 +121,7 @@
build_info();
print_bootinfo();
- return 0;
+ return tdx_checkboard();
}
static void select_dt_from_module_version(void)
diff --git a/board/toradex/colibri_imx6/colibri_imx6.c b/board/toradex/colibri_imx6/colibri_imx6.c
index e6c9b10..7635c58 100644
--- a/board/toradex/colibri_imx6/colibri_imx6.c
+++ b/board/toradex/colibri_imx6/colibri_imx6.c
@@ -649,7 +649,8 @@
printf("Model: Toradex Colibri iMX6 %s %sMB%s\n",
is_cpu_type(MXC_CPU_MX6DL) ? "DualLite" : "Solo",
(gd->ram_size == 0x20000000) ? "512" : "256", it);
- return 0;
+
+ return tdx_checkboard();
}
#if defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP)
diff --git a/board/toradex/colibri_imx7/colibri_imx7.c b/board/toradex/colibri_imx7/colibri_imx7.c
index f0356af..c3478b1 100644
--- a/board/toradex/colibri_imx7/colibri_imx7.c
+++ b/board/toradex/colibri_imx7/colibri_imx7.c
@@ -279,7 +279,7 @@
printf("Model: Toradex Colibri iMX7%c\n",
is_cpu_type(MXC_CPU_MX7D) ? 'D' : 'S');
- return 0;
+ return tdx_checkboard();
}
#if defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP)
diff --git a/board/toradex/colibri_t20/colibri_t20.c b/board/toradex/colibri_t20/colibri_t20.c
index 1df9697..5861cf7 100644
--- a/board/toradex/colibri_t20/colibri_t20.c
+++ b/board/toradex/colibri_t20/colibri_t20.c
@@ -77,7 +77,7 @@
(get_nand_dev_by_index(0)->erasesize >> 10 == 512) ?
((gd->ram_size == 0x10000000) ? "1.1B" : "1.1C") : "1.2A");
- return 0;
+ return tdx_checkboard();
}
#if defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP)
diff --git a/board/toradex/colibri_t30/colibri_t30.c b/board/toradex/colibri_t30/colibri_t30.c
index b6b0046..8cef098 100644
--- a/board/toradex/colibri_t30/colibri_t30.c
+++ b/board/toradex/colibri_t30/colibri_t30.c
@@ -32,7 +32,7 @@
{
puts("Model: Toradex Colibri T30 1GB\n");
- return 0;
+ return tdx_checkboard();
}
#if defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP)
diff --git a/board/toradex/colibri_vf/colibri_vf.c b/board/toradex/colibri_vf/colibri_vf.c
index dcef2db..af9f2d3 100644
--- a/board/toradex/colibri_vf/colibri_vf.c
+++ b/board/toradex/colibri_vf/colibri_vf.c
@@ -373,7 +373,7 @@
else
puts("Model: Toradex Colibri VF50\n");
- return 0;
+ return tdx_checkboard();
}
#if defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP)
diff --git a/board/toradex/common/tdx-common.c b/board/toradex/common/tdx-common.c
index d144914..ed8f0a6 100644
--- a/board/toradex/common/tdx-common.c
+++ b/board/toradex/common/tdx-common.c
@@ -96,7 +96,7 @@
return ver_name;
}
-int show_board_info(void)
+int tdx_checkboard(void)
{
unsigned char ethaddr[6];
diff --git a/board/toradex/common/tdx-common.h b/board/toradex/common/tdx-common.h
index d446e9f..44234dc 100644
--- a/board/toradex/common/tdx-common.h
+++ b/board/toradex/common/tdx-common.h
@@ -11,5 +11,6 @@
int ft_common_board_setup(void *blob, struct bd_info *bd);
u32 get_board_revision(void);
+int tdx_checkboard(void);
#endif /* _TDX_COMMON_H */
diff --git a/board/toradex/verdin-am62/Kconfig b/board/toradex/verdin-am62/Kconfig
index e752224..fd65a96 100644
--- a/board/toradex/verdin-am62/Kconfig
+++ b/board/toradex/verdin-am62/Kconfig
@@ -3,28 +3,6 @@
# Copyright 2023 Toradex
#
-choice
- prompt "Toradex Verdin AM62 based boards"
- optional
-
-config TARGET_VERDIN_AM62_A53
- bool "Toradex Verdin AM62 running on A53"
- select ARM64
- select BINMAN
-
-config TARGET_VERDIN_AM62_R5
- bool "Toradex Verdin AM62 running on R5"
- select CPU_V7R
- select SYS_THUMB_BUILD
- select K3_LOAD_SYSFW
- select RAM
- select SPL_RAM
- select K3_DDRSS
- select BINMAN
- imply SYS_K3_SPL_ATF
-
-endchoice
-
if TARGET_VERDIN_AM62_A53
config SYS_BOARD
diff --git a/board/udoo/neo/neo.c b/board/udoo/neo/neo.c
index 730e266..d99d93b 100644
--- a/board/udoo/neo/neo.c
+++ b/board/udoo/neo/neo.c
@@ -212,7 +212,7 @@
}
/* Override the default implementation, DT model is not accurate */
-int show_board_info(void)
+int checkboard(void)
{
int *board_type = (int *)OCRAM_START;
diff --git a/board/vscom/baltos/Makefile b/board/vscom/baltos/Makefile
index 3ccf66b..2b1e21a 100644
--- a/board/vscom/baltos/Makefile
+++ b/board/vscom/baltos/Makefile
@@ -2,7 +2,7 @@
#
# Makefile
#
-# Copyright (C) 2011 Texas Instruments Incorporated - http://www.ti.com/
+# Copyright (C) 2011 Texas Instruments Incorporated - https://www.ti.com/
ifeq ($(CONFIG_$(SPL_)SKIP_LOWLEVEL_INIT),)
obj-y := mux.o
diff --git a/board/vscom/baltos/board.c b/board/vscom/baltos/board.c
index 8f23cda..bc7dc58 100644
--- a/board/vscom/baltos/board.c
+++ b/board/vscom/baltos/board.c
@@ -4,7 +4,7 @@
*
* Board functions for TI AM335X based boards
*
- * Copyright (C) 2011, Texas Instruments, Incorporated - http://www.ti.com/
+ * Copyright (C) 2011, Texas Instruments, Incorporated - https://www.ti.com/
*/
#include <common.h>
diff --git a/board/vscom/baltos/board.h b/board/vscom/baltos/board.h
index 630c9bb..db6e191 100644
--- a/board/vscom/baltos/board.h
+++ b/board/vscom/baltos/board.h
@@ -4,7 +4,7 @@
*
* TI AM335x boards information header
*
- * Copyright (C) 2011, Texas Instruments, Incorporated - http://www.ti.com/
+ * Copyright (C) 2011, Texas Instruments, Incorporated - https://www.ti.com/
*/
#ifndef _BOARD_H_
diff --git a/board/vscom/baltos/mux.c b/board/vscom/baltos/mux.c
index e01899c..7b99cf0 100644
--- a/board/vscom/baltos/mux.c
+++ b/board/vscom/baltos/mux.c
@@ -1,7 +1,7 @@
/*
* mux.c
*
- * Copyright (C) 2011 Texas Instruments Incorporated - http://www.ti.com/
+ * Copyright (C) 2011 Texas Instruments Incorporated - https://www.ti.com/
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
diff --git a/boot/bootdev-uclass.c b/boot/bootdev-uclass.c
index 44ae98a..4926a50 100644
--- a/boot/bootdev-uclass.c
+++ b/boot/bootdev-uclass.c
@@ -784,7 +784,7 @@
if (info->hunt) {
ret = info->hunt(info, show);
log_debug(" - hunt result %d\n", ret);
- if (ret)
+ if (ret && ret != -ENOENT)
return ret;
}
std->hunters_used |= BIT(seq);
diff --git a/boot/bootflow.c b/boot/bootflow.c
index 6922e7e..1ea2966 100644
--- a/boot/bootflow.c
+++ b/boot/bootflow.c
@@ -467,7 +467,8 @@
free(bflow->name);
free(bflow->subdir);
free(bflow->fname);
- free(bflow->buf);
+ if (!(bflow->flags & BOOTFLOWF_STATIC_BUF))
+ free(bflow->buf);
free(bflow->os_name);
free(bflow->fdt_fname);
free(bflow->bootmeth_priv);
diff --git a/boot/bootmeth_efi.c b/boot/bootmeth_efi.c
index ae936c8..9ba7734 100644
--- a/boot/bootmeth_efi.c
+++ b/boot/bootmeth_efi.c
@@ -160,6 +160,7 @@
if (ret)
return log_msg_ret("read", ret);
bflow->buf = map_sysmem(addr, bflow->size);
+ bflow->flags |= BOOTFLOWF_STATIC_BUF;
set_efi_bootdev(desc, bflow);
diff --git a/boot/expo.c b/boot/expo.c
index 139d684..cadb6a0 100644
--- a/boot/expo.c
+++ b/boot/expo.c
@@ -190,10 +190,12 @@
struct udevice *dev = exp->display;
struct video_priv *vid_priv = dev_get_uclass_priv(dev);
struct scene *scn = NULL;
+ enum colour_idx back;
u32 colour;
int ret;
- colour = video_index_to_colour(vid_priv, VID_WHITE);
+ back = CONFIG_IS_ENABLED(SYS_WHITE_ON_BLACK) ? VID_BLACK : VID_WHITE;
+ colour = video_index_to_colour(vid_priv, back);
ret = video_fill(dev, colour);
if (ret)
return log_msg_ret("fill", ret);
diff --git a/boot/fdt_support.c b/boot/fdt_support.c
index 5e49078..b15d077 100644
--- a/boot/fdt_support.c
+++ b/boot/fdt_support.c
@@ -2095,7 +2095,7 @@
printf("failed on fdt_overlay_apply(): %s\n",
fdt_strerror(err));
if (!has_symbols) {
- printf("base fdt does did not have a /__symbols__ node\n");
+ printf("base fdt does not have a /__symbols__ node\n");
printf("make sure you've compiled with -@\n");
}
}
diff --git a/cmd/Kconfig b/cmd/Kconfig
index 629a90a..bebe816 100644
--- a/cmd/Kconfig
+++ b/cmd/Kconfig
@@ -960,7 +960,6 @@
config CMD_BCB
bool "bcb"
- depends on MMC
depends on PARTITIONS
help
Read/modify/write the fields of Bootloader Control Block, usually
@@ -978,7 +977,7 @@
config CMD_BIND
bool "bind/unbind - Bind or unbind a device to/from a driver"
depends on DM
- default y if USB_ETHER
+ imply CMD_DM
help
Bind or unbind a device to/from a driver from the command line.
This is useful in situations where a device may be handled by several
@@ -1521,7 +1520,7 @@
Turndra tsi148 device. See the command help for full details.
config CMD_UFS
- bool "Enable UFS - Universal Flash Subsystem commands"
+ bool "ufs - Universal Flash Storage commands"
depends on UFS
help
"This provides commands to initialise and configure universal flash
@@ -1682,7 +1681,6 @@
menuconfig CMD_NET
bool "Network commands"
default y
- imply NETDEVICES
if CMD_NET
@@ -2534,6 +2532,15 @@
a number of sub-commands for performing EC tasks such as
updating its flash, accessing a small saved context area
and talking to the I2C bus behind the EC (if there is one).
+
+config CMD_SCMI
+ bool "Enable scmi command"
+ depends on SCMI_FIRMWARE
+ default n
+ help
+ This command provides user interfaces to several SCMI (System
+ Control and Management Interface) protocols available on Arm
+ platforms to manage system resources.
endmenu
menu "Filesystem commands"
diff --git a/cmd/Makefile b/cmd/Makefile
index dbeeebe..5ed0e40 100644
--- a/cmd/Makefile
+++ b/cmd/Makefile
@@ -160,6 +160,7 @@
obj-$(CONFIG_CMD_NVME) += nvme.o
obj-$(CONFIG_SANDBOX) += sb.o
obj-$(CONFIG_CMD_SF) += sf.o
+obj-$(CONFIG_CMD_SCMI) += scmi.o
obj-$(CONFIG_CMD_SCSI) += scsi.o disk.o
obj-$(CONFIG_CMD_SHA1SUM) += sha1sum.o
obj-$(CONFIG_CMD_SEAMA) += seama.o
diff --git a/cmd/bcb.c b/cmd/bcb.c
index 02d0c70..f3b9256 100644
--- a/cmd/bcb.c
+++ b/cmd/bcb.c
@@ -25,9 +25,18 @@
BCB_CMD_STORE,
};
-static int bcb_dev = -1;
-static int bcb_part = -1;
+static const char * const fields[] = {
+ "command",
+ "status",
+ "recovery",
+ "stage"
+};
+
static struct bootloader_message bcb __aligned(ARCH_DMA_MINALIGN) = { { 0 } };
+static struct disk_partition partition_data;
+
+static struct blk_desc *block;
+static struct disk_partition *partition = &partition_data;
static int bcb_cmd_get(char *cmd)
{
@@ -53,6 +62,9 @@
switch (cmd) {
case BCB_CMD_LOAD:
+ if (argc != 3 && argc != 4)
+ goto err;
+ break;
case BCB_CMD_FIELD_SET:
if (argc != 3)
goto err;
@@ -78,7 +90,7 @@
return -1;
}
- if (cmd != BCB_CMD_LOAD && (bcb_dev < 0 || bcb_part < 0)) {
+ if (cmd != BCB_CMD_LOAD && !block) {
printf("Error: Please, load BCB first!\n");
return -1;
}
@@ -90,7 +102,7 @@
return -1;
}
-static int bcb_field_get(char *name, char **fieldp, int *sizep)
+static int bcb_field_get(const char *name, char **fieldp, int *sizep)
{
if (!strcmp(name, "command")) {
*fieldp = bcb.command;
@@ -115,25 +127,30 @@
return 0;
}
-static int __bcb_load(int devnum, const char *partp)
+static void __bcb_reset(void)
{
- struct blk_desc *desc;
- struct disk_partition info;
- u64 cnt;
+ block = NULL;
+ partition = &partition_data;
+ memset(&partition_data, 0, sizeof(struct disk_partition));
+ memset(&bcb, 0, sizeof(struct bootloader_message));
+}
+
+static int __bcb_initialize(const char *iface, int devnum, const char *partp)
+{
char *endp;
int part, ret;
- desc = blk_get_devnum_by_uclass_id(UCLASS_MMC, devnum);
- if (!desc) {
+ block = blk_get_dev(iface, devnum);
+ if (!block) {
ret = -ENODEV;
goto err_read_fail;
}
/*
- * always select the USER mmc hwpart in case another
+ * always select the first hwpart in case another
* blk operation selected a different hwpart
*/
- ret = blk_dselect_hwpart(desc, 0);
+ ret = blk_dselect_hwpart(block, 0);
if (IS_ERR_VALUE(ret)) {
ret = -ENODEV;
goto err_read_fail;
@@ -141,59 +158,84 @@
part = simple_strtoul(partp, &endp, 0);
if (*endp == '\0') {
- ret = part_get_info(desc, part, &info);
+ ret = part_get_info(block, part, partition);
if (ret)
goto err_read_fail;
} else {
- part = part_get_info_by_name(desc, partp, &info);
+ part = part_get_info_by_name(block, partp, partition);
if (part < 0) {
ret = part;
goto err_read_fail;
}
}
+ return CMD_RET_SUCCESS;
+
+err_read_fail:
+ printf("Error: %d %d:%s read failed (%d)\n", block->uclass_id,
+ block->devnum, partition->name, ret);
+ __bcb_reset();
+ return CMD_RET_FAILURE;
+}
+
+static int __bcb_load(void)
+{
+ u64 cnt;
+ int ret;
+
- cnt = DIV_ROUND_UP(sizeof(struct bootloader_message), info.blksz);
- if (cnt > info.size)
+ cnt = DIV_ROUND_UP(sizeof(struct bootloader_message), partition->blksz);
+ if (cnt > partition->size)
goto err_too_small;
- if (blk_dread(desc, info.start, cnt, &bcb) != cnt) {
+ if (blk_dread(block, partition->start, cnt, &bcb) != cnt) {
ret = -EIO;
goto err_read_fail;
}
- bcb_dev = desc->devnum;
- bcb_part = part;
- debug("%s: Loaded from mmc %d:%d\n", __func__, bcb_dev, bcb_part);
+ debug("%s: Loaded from %d %d:%s\n", __func__, block->uclass_id,
+ block->devnum, partition->name);
return CMD_RET_SUCCESS;
err_read_fail:
- printf("Error: mmc %d:%s read failed (%d)\n", devnum, partp, ret);
+ printf("Error: %d %d:%s read failed (%d)\n", block->uclass_id,
+ block->devnum, partition->name, ret);
goto err;
err_too_small:
- printf("Error: mmc %d:%s too small!", devnum, partp);
- goto err;
+ printf("Error: %d %d:%s too small!", block->uclass_id,
+ block->devnum, partition->name);
err:
- bcb_dev = -1;
- bcb_part = -1;
-
+ __bcb_reset();
return CMD_RET_FAILURE;
}
static int do_bcb_load(struct cmd_tbl *cmdtp, int flag, int argc,
char * const argv[])
{
+ int ret;
+ int devnum;
char *endp;
- int devnum = simple_strtoul(argv[1], &endp, 0);
+ char *iface = "mmc";
+
+ if (argc == 4) {
+ iface = argv[1];
+ argc--;
+ argv++;
+ }
+ devnum = simple_strtoul(argv[1], &endp, 0);
if (*endp != '\0') {
printf("Error: Device id '%s' not a number\n", argv[1]);
return CMD_RET_FAILURE;
}
- return __bcb_load(devnum, argv[2]);
+ ret = __bcb_initialize(iface, devnum, argv[2]);
+ if (ret != CMD_RET_SUCCESS)
+ return ret;
+
+ return __bcb_load();
}
-static int __bcb_set(char *fieldp, const char *valp)
+static int __bcb_set(const char *fieldp, const char *valp)
{
int size, len;
char *field, *str, *found, *tmp;
@@ -293,31 +335,20 @@
static int __bcb_store(void)
{
- struct blk_desc *desc;
- struct disk_partition info;
u64 cnt;
int ret;
- desc = blk_get_devnum_by_uclass_id(UCLASS_MMC, bcb_dev);
- if (!desc) {
- ret = -ENODEV;
- goto err;
- }
-
- ret = part_get_info(desc, bcb_part, &info);
- if (ret)
- goto err;
+ cnt = DIV_ROUND_UP(sizeof(struct bootloader_message), partition->blksz);
- cnt = DIV_ROUND_UP(sizeof(struct bootloader_message), info.blksz);
-
- if (blk_dwrite(desc, info.start, cnt, &bcb) != cnt) {
+ if (blk_dwrite(block, partition->start, cnt, &bcb) != cnt) {
ret = -EIO;
goto err;
}
return CMD_RET_SUCCESS;
err:
- printf("Error: mmc %d:%d write failed (%d)\n", bcb_dev, bcb_part, ret);
+ printf("Error: %d %d:%s write failed (%d)\n", block->uclass_id,
+ block->devnum, partition->name, ret);
return CMD_RET_FAILURE;
}
@@ -328,23 +359,59 @@
return __bcb_store();
}
-int bcb_write_reboot_reason(int devnum, char *partp, const char *reasonp)
+int bcb_find_partition_and_load(const char *iface, int devnum, char *partp)
{
int ret;
- ret = __bcb_load(devnum, partp);
- if (ret != CMD_RET_SUCCESS)
- return ret;
+ __bcb_reset();
- ret = __bcb_set("command", reasonp);
+ ret = __bcb_initialize(iface, devnum, partp);
if (ret != CMD_RET_SUCCESS)
return ret;
- ret = __bcb_store();
- if (ret != CMD_RET_SUCCESS)
- return ret;
+ return __bcb_load();
+}
- return 0;
+int bcb_load(struct blk_desc *block_description, struct disk_partition *disk_partition)
+{
+ __bcb_reset();
+
+ block = block_description;
+ partition = disk_partition;
+
+ return __bcb_load();
+}
+
+int bcb_set(enum bcb_field field, const char *value)
+{
+ if (field > BCB_FIELD_STAGE)
+ return CMD_RET_FAILURE;
+ return __bcb_set(fields[field], value);
+}
+
+int bcb_get(enum bcb_field field, char *value_out, size_t value_size)
+{
+ int size;
+ char *field_value;
+
+ if (field > BCB_FIELD_STAGE)
+ return CMD_RET_FAILURE;
+ if (bcb_field_get(fields[field], &field_value, &size))
+ return CMD_RET_FAILURE;
+
+ strlcpy(value_out, field_value, value_size);
+
+ return CMD_RET_SUCCESS;
+}
+
+int bcb_store(void)
+{
+ return __bcb_store();
+}
+
+void bcb_reset(void)
+{
+ __bcb_reset();
}
static struct cmd_tbl cmd_bcb_sub[] = {
@@ -385,21 +452,23 @@
U_BOOT_CMD(
bcb, CONFIG_SYS_MAXARGS, 1, do_bcb,
"Load/set/clear/test/dump/store Android BCB fields",
- "load <dev> <part> - load BCB from mmc <dev>:<part>\n"
- "bcb set <field> <val> - set BCB <field> to <val>\n"
- "bcb clear [<field>] - clear BCB <field> or all fields\n"
- "bcb test <field> <op> <val> - test BCB <field> against <val>\n"
- "bcb dump <field> - dump BCB <field>\n"
- "bcb store - store BCB back to mmc\n"
+ "load <interface> <dev> <part> - load BCB from <interface> <dev>:<part>\n"
+ "load <dev> <part> - load BCB from mmc <dev>:<part>\n"
+ "bcb set <field> <val> - set BCB <field> to <val>\n"
+ "bcb clear [<field>] - clear BCB <field> or all fields\n"
+ "bcb test <field> <op> <val> - test BCB <field> against <val>\n"
+ "bcb dump <field> - dump BCB <field>\n"
+ "bcb store - store BCB back to <interface>\n"
"\n"
"Legend:\n"
- "<dev> - MMC device index containing the BCB partition\n"
- "<part> - MMC partition index or name containing the BCB\n"
- "<field> - one of {command,status,recovery,stage,reserved}\n"
- "<op> - the binary operator used in 'bcb test':\n"
- " '=' returns true if <val> matches the string stored in <field>\n"
- " '~' returns true if <val> matches a subset of <field>'s string\n"
- "<val> - string/text provided as input to bcb {set,test}\n"
- " NOTE: any ':' character in <val> will be replaced by line feed\n"
- " during 'bcb set' and used as separator by upper layers\n"
+ "<interface> - storage device interface (virtio, mmc, etc)\n"
+ "<dev> - storage device index containing the BCB partition\n"
+ "<part> - partition index or name containing the BCB\n"
+ "<field> - one of {command,status,recovery,stage,reserved}\n"
+ "<op> - the binary operator used in 'bcb test':\n"
+ " '=' returns true if <val> matches the string stored in <field>\n"
+ " '~' returns true if <val> matches a subset of <field>'s string\n"
+ "<val> - string/text provided as input to bcb {set,test}\n"
+ " NOTE: any ':' character in <val> will be replaced by line feed\n"
+ " during 'bcb set' and used as separator by upper layers\n"
);
diff --git a/cmd/bdinfo.c b/cmd/bdinfo.c
index 1fe13ca..79106ca 100644
--- a/cmd/bdinfo.c
+++ b/cmd/bdinfo.c
@@ -10,6 +10,7 @@
#include <command.h>
#include <dm.h>
#include <env.h>
+#include <getopt.h>
#include <lmb.h>
#include <mapmem.h>
#include <net.h>
@@ -133,10 +134,8 @@
bdinfo_print_num_l(" clock", info.clock);
}
-int do_bdinfo(struct cmd_tbl *cmdtp, int flag, int argc, char *const argv[])
+static int bdinfo_print_all(struct bd_info *bd)
{
- struct bd_info *bd = gd->bd;
-
#ifdef DEBUG
bdinfo_print_num_l("bd address", (ulong)bd);
#endif
@@ -184,8 +183,38 @@
return 0;
}
+int do_bdinfo(struct cmd_tbl *cmdtp, int flag, int argc, char *const argv[])
+{
+ struct bd_info *bd = gd->bd;
+ struct getopt_state gs;
+ int opt;
+
+ if (!CONFIG_IS_ENABLED(GETOPT) || argc == 1)
+ return bdinfo_print_all(bd);
+
+ getopt_init_state(&gs);
+ while ((opt = getopt(&gs, argc, argv, "aem")) > 0) {
+ switch (opt) {
+ case 'a':
+ return bdinfo_print_all(bd);
+ case 'e':
+ if (!IS_ENABLED(CONFIG_CMD_NET))
+ return CMD_RET_USAGE;
+ print_eth();
+ return CMD_RET_SUCCESS;
+ case 'm':
+ print_bi_dram(bd);
+ return CMD_RET_SUCCESS;
+ default:
+ return CMD_RET_USAGE;
+ }
+ }
+
+ return CMD_RET_USAGE;
+}
+
U_BOOT_CMD(
- bdinfo, 1, 1, do_bdinfo,
+ bdinfo, 2, 1, do_bdinfo,
"print Board Info structure",
""
);
diff --git a/cmd/bind.c b/cmd/bind.c
index 4d1b788..be0d4d2 100644
--- a/cmd/bind.c
+++ b/cmd/bind.c
@@ -246,6 +246,8 @@
"Bind a device to a driver",
"<node path> <driver>\n"
"bind <class> <index> <driver>\n"
+ "Use 'dm tree' to list all devices registered in the driver model,\n"
+ "their path, class, index and current driver.\n"
);
U_BOOT_CMD(
@@ -254,4 +256,6 @@
"<node path>\n"
"unbind <class> <index>\n"
"unbind <class> <index> <driver>\n"
+ "Use 'dm tree' to list all devices registered in the driver model,\n"
+ "their path, class, index and current driver.\n"
);
diff --git a/cmd/bootefi.c b/cmd/bootefi.c
index 20e5c94..4d74969 100644
--- a/cmd/bootefi.c
+++ b/cmd/bootefi.c
@@ -356,6 +356,7 @@
efi_status_t ret;
efi_uintn_t exit_data_size = 0;
u16 *exit_data = NULL;
+ struct efi_event *evt;
/* On ARM switch from EL3 or secure mode to EL2 or non-secure mode */
switch_to_non_secure_mode();
@@ -394,6 +395,17 @@
log_err("Failed to remove loadfile2 for initrd\n");
}
+ /* Notify EFI_EVENT_GROUP_RETURN_TO_EFIBOOTMGR event group. */
+ list_for_each_entry(evt, &efi_events, link) {
+ if (evt->group &&
+ !guidcmp(evt->group,
+ &efi_guid_event_group_return_to_efibootmgr)) {
+ efi_signal_event(evt);
+ EFI_CALL(systab.boottime->close_event(evt));
+ break;
+ }
+ }
+
/* Control is returned to U-Boot, disable EFI watchdog */
efi_set_watchdog(0);
diff --git a/cmd/bootflow.c b/cmd/bootflow.c
index ad39ebe..3aeb40d 100644
--- a/cmd/bootflow.c
+++ b/cmd/bootflow.c
@@ -89,6 +89,44 @@
num_valid);
}
+/**
+ * bootflow_handle_menu() - Handle running the menu and updating cur bootflow
+ *
+ * This shows the menu, allows the user to select something and then prints
+ * what happened
+ *
+ * @std: bootstd information
+ * @text_mode: true to run the menu in text mode
+ * @bflowp: Returns selected bootflow, on success
+ * Return: 0 on success (a bootflow was selected), -EAGAIN if nothing was
+ * chosen, other -ve value on other error
+ */
+__maybe_unused static int bootflow_handle_menu(struct bootstd_priv *std,
+ bool text_mode,
+ struct bootflow **bflowp)
+{
+ struct bootflow *bflow;
+ int ret;
+
+ ret = bootflow_menu_run(std, text_mode, &bflow);
+ if (ret) {
+ if (ret == -EAGAIN) {
+ printf("Nothing chosen\n");
+ std->cur_bootflow = NULL;
+ } else {
+ printf("Menu failed (err=%d)\n", ret);
+ }
+
+ return ret;
+ }
+
+ printf("Selected: %s\n", bflow->os_name ? bflow->os_name : bflow->name);
+ std->cur_bootflow = bflow;
+ *bflowp = bflow;
+
+ return 0;
+}
+
static int do_bootflow_scan(struct cmd_tbl *cmdtp, int flag, int argc,
char *const argv[])
{
@@ -455,18 +493,9 @@
if (ret)
return CMD_RET_FAILURE;
- ret = bootflow_menu_run(std, text_mode, &bflow);
- if (ret) {
- if (ret == -EAGAIN)
- printf("Nothing chosen\n");
- else {
- printf("Menu failed (err=%d)\n", ret);
- return CMD_RET_FAILURE;
- }
- }
-
- printf("Selected: %s\n", bflow->os_name ? bflow->os_name : bflow->name);
- std->cur_bootflow = bflow;
+ ret = bootflow_handle_menu(std, text_mode, &bflow);
+ if (ret)
+ return CMD_RET_FAILURE;
return 0;
}
diff --git a/cmd/eficonfig.c b/cmd/eficonfig.c
index e6e8a0a..34a59cb 100644
--- a/cmd/eficonfig.c
+++ b/cmd/eficonfig.c
@@ -528,7 +528,10 @@
p += fp_size;
*((struct efi_device_path *)p) = END;
- dp = efi_dp_append(dp_volume, (struct efi_device_path *)buf);
+ dp = efi_dp_shorten(dp_volume);
+ if (!dp)
+ dp = dp_volume;
+ dp = efi_dp_append(dp, &fp->dp);
free(buf);
return dp;
diff --git a/cmd/efidebug.c b/cmd/efidebug.c
index 201531a..78ef16f 100644
--- a/cmd/efidebug.c
+++ b/cmd/efidebug.c
@@ -19,6 +19,7 @@
#include <log.h>
#include <malloc.h>
#include <mapmem.h>
+#include <net.h>
#include <part.h>
#include <search.h>
#include <linux/ctype.h>
@@ -708,6 +709,65 @@
}
/**
+ * efi_boot_add_uri() - set URI load option
+ *
+ * @argc: Number of arguments
+ * @argv: Argument array
+ * @var_name16: variable name buffer
+ * @var_name16_size: variable name buffer size
+ * @lo: pointer to the load option
+ * @file_path: buffer to set the generated device path pointer
+ * @fp_size: file_path size
+ * Return: CMD_RET_SUCCESS on success,
+ * CMD_RET_USAGE or CMD_RET_RET_FAILURE on failure
+ */
+static int efi_boot_add_uri(int argc, char *const argv[], u16 *var_name16,
+ size_t var_name16_size, struct efi_load_option *lo,
+ struct efi_device_path **file_path,
+ efi_uintn_t *fp_size)
+{
+ int id;
+ char *pos;
+ char *endp;
+ u16 *label;
+ efi_uintn_t uridp_len;
+ struct efi_device_path_uri *uridp;
+
+ if (argc < 3 || lo->label)
+ return CMD_RET_USAGE;
+
+ id = (int)hextoul(argv[1], &endp);
+ if (*endp != '\0' || id > 0xffff)
+ return CMD_RET_USAGE;
+
+ label = efi_convert_string(argv[2]);
+ if (!label)
+ return CMD_RET_FAILURE;
+
+ if (!wget_validate_uri(argv[3])) {
+ printf("ERROR: invalid URI\n");
+ return CMD_RET_FAILURE;
+ }
+
+ efi_create_indexed_name(var_name16, var_name16_size, "Boot", id);
+ lo->label = label;
+
+ uridp_len = sizeof(struct efi_device_path) + strlen(argv[3]) + 1;
+ uridp = efi_alloc(uridp_len + sizeof(END));
+ uridp->dp.type = DEVICE_PATH_TYPE_MESSAGING_DEVICE;
+ uridp->dp.sub_type = DEVICE_PATH_SUB_TYPE_MSG_URI;
+ uridp->dp.length = uridp_len;
+ strcpy(uridp->uri, argv[3]);
+ pos = (char *)uridp + uridp_len;
+ memcpy(pos, &END, sizeof(END));
+
+ *file_path = &uridp->dp;
+ *fp_size += uridp_len + sizeof(END);
+
+ return CMD_RET_SUCCESS;
+}
+
+/**
* do_efi_boot_add() - set UEFI load option
*
* @cmdtp: Command table
@@ -829,6 +889,21 @@
argc -= 1;
argv += 1;
break;
+ case 'u':
+ if (IS_ENABLED(CONFIG_EFI_HTTP_BOOT)) {
+ r = efi_boot_add_uri(argc, argv, var_name16,
+ sizeof(var_name16), &lo,
+ &file_path, &fp_size);
+ if (r != CMD_RET_SUCCESS)
+ goto out;
+ fp_free = file_path;
+ argc -= 3;
+ argv += 3;
+ } else{
+ r = CMD_RET_USAGE;
+ goto out;
+ }
+ break;
default:
r = CMD_RET_USAGE;
goto out;
@@ -1491,6 +1566,9 @@
" -b|-B <bootid> <label> <interface> <devnum>[:<part>] <file path>\n"
" -i|-I <interface> <devnum>[:<part>] <initrd file path>\n"
" (-b, -i for short form device path)\n"
+#if (IS_ENABLED(CONFIG_EFI_HTTP_BOOT))
+ " -u <bootid> <label> <uri>\n"
+#endif
" -s '<optional data>'\n"
"efidebug boot rm <bootid#1> [<bootid#2> [<bootid#3> [...]]]\n"
" - delete UEFI BootXXXX variables\n"
diff --git a/cmd/nand.c b/cmd/nand.c
index 71b8f96..fe834c4 100644
--- a/cmd/nand.c
+++ b/cmd/nand.c
@@ -34,6 +34,7 @@
#include <env.h>
#include <watchdog.h>
#include <malloc.h>
+#include <mapmem.h>
#include <asm/byteorder.h>
#include <jffs2/jffs2.h>
#include <nand.h>
@@ -432,7 +433,7 @@
env_set_hex("nand_erasesize", mtd->erasesize);
}
-static int raw_access(struct mtd_info *mtd, ulong addr, loff_t off,
+static int raw_access(struct mtd_info *mtd, void *buf, loff_t off,
ulong count, int read, int no_verify)
{
int ret = 0;
@@ -440,8 +441,8 @@
while (count--) {
/* Raw access */
mtd_oob_ops_t ops = {
- .datbuf = (u8 *)addr,
- .oobbuf = ((u8 *)addr) + mtd->writesize,
+ .datbuf = buf,
+ .oobbuf = buf + mtd->writesize,
.len = mtd->writesize,
.ooblen = mtd->oobsize,
.mode = MTD_OPS_RAW
@@ -461,7 +462,7 @@
break;
}
- addr += mtd->writesize + mtd->oobsize;
+ buf += mtd->writesize + mtd->oobsize;
off += mtd->writesize;
}
@@ -675,6 +676,7 @@
int read;
int raw = 0;
int no_verify = 0;
+ void *buf;
if (argc < 4)
goto usage;
@@ -730,32 +732,32 @@
}
mtd = get_nand_dev_by_index(dev);
+ buf = map_sysmem(addr, maxsize);
if (!s || !strcmp(s, ".jffs2") ||
!strcmp(s, ".e") || !strcmp(s, ".i")) {
if (read)
ret = nand_read_skip_bad(mtd, off, &rwsize,
- NULL, maxsize,
- (u_char *)addr);
+ NULL, maxsize, buf);
else
ret = nand_write_skip_bad(mtd, off, &rwsize,
- NULL, maxsize,
- (u_char *)addr,
+ NULL, maxsize, buf,
WITH_WR_VERIFY);
#ifdef CONFIG_CMD_NAND_TRIMFFS
} else if (!strcmp(s, ".trimffs")) {
if (read) {
printf("Unknown nand command suffix '%s'\n", s);
+ unmap_sysmem(buf);
return 1;
}
ret = nand_write_skip_bad(mtd, off, &rwsize, NULL,
- maxsize, (u_char *)addr,
+ maxsize, buf,
WITH_DROP_FFS | WITH_WR_VERIFY);
#endif
} else if (!strcmp(s, ".oob")) {
/* out-of-band data */
mtd_oob_ops_t ops = {
- .oobbuf = (u8 *)addr,
+ .oobbuf = buf,
.ooblen = rwsize,
.mode = MTD_OPS_RAW
};
@@ -765,13 +767,15 @@
else
ret = mtd_write_oob(mtd, off, &ops);
} else if (raw) {
- ret = raw_access(mtd, addr, off, pagecount, read,
+ ret = raw_access(mtd, buf, off, pagecount, read,
no_verify);
} else {
printf("Unknown nand command suffix '%s'.\n", s);
+ unmap_sysmem(buf);
return 1;
}
+ unmap_sysmem(buf);
printf(" %zu bytes %s: %s\n", rwsize,
read ? "read" : "written", ret ? "ERROR" : "OK");
diff --git a/cmd/remoteproc.c b/cmd/remoteproc.c
index ca3b436..ea8724a 100644
--- a/cmd/remoteproc.c
+++ b/cmd/remoteproc.c
@@ -1,7 +1,7 @@
// SPDX-License-Identifier: GPL-2.0+
/*
* (C) Copyright 2015
- * Texas Instruments Incorporated - http://www.ti.com/
+ * Texas Instruments Incorporated - https://www.ti.com/
*/
#include <common.h>
#include <command.h>
diff --git a/cmd/scmi.c b/cmd/scmi.c
new file mode 100644
index 0000000..664062c
--- /dev/null
+++ b/cmd/scmi.c
@@ -0,0 +1,384 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * SCMI (System Control and Management Interface) utility command
+ *
+ * Copyright (c) 2023 Linaro Limited
+ * Author: AKASHI Takahiro
+ */
+
+#include <command.h>
+#include <exports.h>
+#include <scmi_agent.h>
+#include <scmi_agent-uclass.h>
+#include <stdlib.h>
+#include <asm/types.h>
+#include <dm/device.h>
+#include <dm/uclass.h> /* uclass_get_device */
+#include <linux/bitfield.h>
+#include <linux/bitops.h>
+
+struct {
+ enum scmi_std_protocol id;
+ const char *name;
+} protocol_name[] = {
+ {SCMI_PROTOCOL_ID_BASE, "Base"},
+ {SCMI_PROTOCOL_ID_POWER_DOMAIN, "Power domain management"},
+ {SCMI_PROTOCOL_ID_SYSTEM, "System power management"},
+ {SCMI_PROTOCOL_ID_PERF, "Performance domain management"},
+ {SCMI_PROTOCOL_ID_CLOCK, "Clock management"},
+ {SCMI_PROTOCOL_ID_SENSOR, "Sensor management"},
+ {SCMI_PROTOCOL_ID_RESET_DOMAIN, "Reset domain management"},
+ {SCMI_PROTOCOL_ID_VOLTAGE_DOMAIN, "Voltage domain management"},
+};
+
+/**
+ * get_agent() - get SCMI agent device
+ *
+ * Return: Pointer to SCMI agent device on success, NULL on failure
+ */
+static struct udevice *get_agent(void)
+{
+ struct udevice *agent;
+
+ if (uclass_get_device(UCLASS_SCMI_AGENT, 0, &agent)) {
+ printf("Cannot find any SCMI agent\n");
+ return NULL;
+ }
+
+ return agent;
+}
+
+/**
+ * get_base_proto() - get SCMI base protocol device
+ * @agent: SCMI agent device
+ *
+ * Return: Pointer to SCMI base protocol device on success,
+ * NULL on failure
+ */
+static struct udevice *get_base_proto(struct udevice *agent)
+{
+ struct udevice *base_proto;
+
+ if (!agent) {
+ agent = get_agent();
+ if (!agent)
+ return NULL;
+ }
+
+ base_proto = scmi_get_protocol(agent, SCMI_PROTOCOL_ID_BASE);
+ if (!base_proto) {
+ printf("SCMI base protocol not found\n");
+ return NULL;
+ }
+
+ return base_proto;
+}
+
+/**
+ * get_proto_name() - get the name of SCMI protocol
+ *
+ * @id: SCMI Protocol ID
+ *
+ * Get the printable name of the protocol, @id
+ *
+ * Return: Name string on success, NULL on failure
+ */
+static const char *get_proto_name(enum scmi_std_protocol id)
+{
+ int i;
+
+ for (i = 0; i < ARRAY_SIZE(protocol_name); i++)
+ if (id == protocol_name[i].id)
+ return protocol_name[i].name;
+
+ return NULL;
+}
+
+/**
+ * do_scmi_info() - get the information of SCMI services
+ *
+ * @cmdtp: Command table
+ * @flag: Command flag
+ * @argc: Number of arguments
+ * @argv: Argument array
+ *
+ * Get the information of SCMI services using various interfaces
+ * provided by the Base protocol.
+ *
+ * Return: CMD_RET_SUCCESS on success, CMD_RET_RET_FAILURE on failure
+ */
+static int do_scmi_info(struct cmd_tbl *cmdtp, int flag, int argc,
+ char * const argv[])
+{
+ struct udevice *agent, *base_proto;
+ u32 agent_id, num_protocols;
+ u8 *agent_name, *protocols;
+ int i, ret;
+
+ if (argc != 1)
+ return CMD_RET_USAGE;
+
+ agent = get_agent();
+ if (!agent)
+ return CMD_RET_FAILURE;
+ base_proto = get_base_proto(agent);
+ if (!base_proto)
+ return CMD_RET_FAILURE;
+
+ printf("SCMI device: %s\n", agent->name);
+ printf(" protocol version: 0x%x\n", scmi_version(agent));
+ printf(" # of agents: %d\n", scmi_num_agents(agent));
+ for (i = 0; i < scmi_num_agents(agent); i++) {
+ ret = scmi_base_discover_agent(base_proto, i, &agent_id,
+ &agent_name);
+ if (ret) {
+ if (ret != -EOPNOTSUPP)
+ printf("base_discover_agent() failed for id: %d (%d)\n",
+ i, ret);
+ break;
+ }
+ printf(" %c%2d: %s\n", i == scmi_agent_id(agent) ? '>' : ' ',
+ i, agent_name);
+ free(agent_name);
+ }
+ printf(" # of protocols: %d\n", scmi_num_protocols(agent));
+ num_protocols = scmi_num_protocols(agent);
+ protocols = scmi_protocols(agent);
+ if (protocols)
+ for (i = 0; i < num_protocols; i++)
+ printf(" %s\n", get_proto_name(protocols[i]));
+ printf(" vendor: %s\n", scmi_vendor(agent));
+ printf(" sub vendor: %s\n", scmi_sub_vendor(agent));
+ printf(" impl version: 0x%x\n", scmi_impl_version(agent));
+
+ return CMD_RET_SUCCESS;
+}
+
+/**
+ * do_scmi_set_dev() - set access permission to device
+ *
+ * @cmdtp: Command table
+ * @flag: Command flag
+ * @argc: Number of arguments
+ * @argv: Argument array
+ *
+ * Set access permission to device with SCMI_BASE_SET_DEVICE_PERMISSIONS
+ *
+ * Return: CMD_RET_SUCCESS on success, CMD_RET_RET_FAILURE on failure
+ */
+static int do_scmi_set_dev(struct cmd_tbl *cmdtp, int flag, int argc,
+ char * const argv[])
+{
+ u32 agent_id, device_id, flags, attributes;
+ char *end;
+ struct udevice *base_proto;
+ int ret;
+
+ if (argc != 4)
+ return CMD_RET_USAGE;
+
+ agent_id = simple_strtoul(argv[1], &end, 16);
+ if (*end != '\0')
+ return CMD_RET_USAGE;
+
+ device_id = simple_strtoul(argv[2], &end, 16);
+ if (*end != '\0')
+ return CMD_RET_USAGE;
+
+ flags = simple_strtoul(argv[3], &end, 16);
+ if (*end != '\0')
+ return CMD_RET_USAGE;
+
+ base_proto = get_base_proto(NULL);
+ if (!base_proto)
+ return CMD_RET_FAILURE;
+
+ ret = scmi_base_protocol_message_attrs(base_proto,
+ SCMI_BASE_SET_DEVICE_PERMISSIONS,
+ &attributes);
+ if (ret) {
+ printf("This operation is not supported\n");
+ return CMD_RET_FAILURE;
+ }
+
+ ret = scmi_base_set_device_permissions(base_proto, agent_id,
+ device_id, flags);
+ if (ret) {
+ printf("%s access to device:%u failed (%d)\n",
+ flags ? "Allowing" : "Denying", device_id, ret);
+ return CMD_RET_FAILURE;
+ }
+
+ return CMD_RET_SUCCESS;
+}
+
+/**
+ * do_scmi_set_proto() - set protocol permission to device
+ *
+ * @cmdtp: Command table
+ * @flag: Command flag
+ * @argc: Number of arguments
+ * @argv: Argument array
+ *
+ * Set protocol permission to device with SCMI_BASE_SET_PROTOCOL_PERMISSIONS
+ *
+ * Return: CMD_RET_SUCCESS on success, CMD_RET_RET_FAILURE on failure
+ */
+static int do_scmi_set_proto(struct cmd_tbl *cmdtp, int flag, int argc,
+ char * const argv[])
+{
+ u32 agent_id, device_id, protocol_id, flags, attributes;
+ char *end;
+ struct udevice *base_proto;
+ int ret;
+
+ if (argc != 5)
+ return CMD_RET_USAGE;
+
+ agent_id = simple_strtoul(argv[1], &end, 16);
+ if (*end != '\0')
+ return CMD_RET_USAGE;
+
+ device_id = simple_strtoul(argv[2], &end, 16);
+ if (*end != '\0')
+ return CMD_RET_USAGE;
+
+ protocol_id = simple_strtoul(argv[3], &end, 16);
+ if (*end != '\0')
+ return CMD_RET_USAGE;
+
+ flags = simple_strtoul(argv[4], &end, 16);
+ if (*end != '\0')
+ return CMD_RET_USAGE;
+
+ base_proto = get_base_proto(NULL);
+ if (!base_proto)
+ return CMD_RET_FAILURE;
+
+ ret = scmi_base_protocol_message_attrs(base_proto,
+ SCMI_BASE_SET_PROTOCOL_PERMISSIONS,
+ &attributes);
+ if (ret) {
+ printf("This operation is not supported\n");
+ return CMD_RET_FAILURE;
+ }
+
+ ret = scmi_base_set_protocol_permissions(base_proto, agent_id,
+ device_id, protocol_id,
+ flags);
+ if (ret) {
+ printf("%s access to protocol:0x%x on device:%u failed (%d)\n",
+ flags ? "Allowing" : "Denying", protocol_id, device_id,
+ ret);
+ return CMD_RET_FAILURE;
+ }
+
+ return CMD_RET_SUCCESS;
+}
+
+/**
+ * do_scmi_reset() - reset platform resource settings
+ *
+ * @cmdtp: Command table
+ * @flag: Command flag
+ * @argc: Number of arguments
+ * @argv: Argument array
+ *
+ * Reset platform resource settings with BASE_RESET_AGENT_CONFIGURATION
+ *
+ * Return: CMD_RET_SUCCESS on success, CMD_RET_RET_FAILURE on failure
+ */
+static int do_scmi_reset(struct cmd_tbl *cmdtp, int flag, int argc,
+ char * const argv[])
+{
+ u32 agent_id, flags, attributes;
+ char *end;
+ struct udevice *base_proto;
+ int ret;
+
+ if (argc != 3)
+ return CMD_RET_USAGE;
+
+ agent_id = simple_strtoul(argv[1], &end, 16);
+ if (*end != '\0')
+ return CMD_RET_USAGE;
+
+ flags = simple_strtoul(argv[2], &end, 16);
+ if (*end != '\0')
+ return CMD_RET_USAGE;
+
+ base_proto = get_base_proto(NULL);
+ if (!base_proto)
+ return CMD_RET_FAILURE;
+
+ ret = scmi_base_protocol_message_attrs(base_proto,
+ SCMI_BASE_RESET_AGENT_CONFIGURATION,
+ &attributes);
+ if (ret) {
+ printf("Reset is not supported\n");
+ return CMD_RET_FAILURE;
+ }
+
+ ret = scmi_base_reset_agent_configuration(base_proto, agent_id, flags);
+ if (ret) {
+ printf("Reset failed (%d)\n", ret);
+ return CMD_RET_FAILURE;
+ }
+
+ return CMD_RET_SUCCESS;
+}
+
+static struct cmd_tbl cmd_scmi_sub[] = {
+ U_BOOT_CMD_MKENT(info, CONFIG_SYS_MAXARGS, 1,
+ do_scmi_info, "", ""),
+ U_BOOT_CMD_MKENT(perm_dev, CONFIG_SYS_MAXARGS, 1,
+ do_scmi_set_dev, "", ""),
+ U_BOOT_CMD_MKENT(perm_proto, CONFIG_SYS_MAXARGS, 1,
+ do_scmi_set_proto, "", ""),
+ U_BOOT_CMD_MKENT(reset, CONFIG_SYS_MAXARGS, 1,
+ do_scmi_reset, "", ""),
+};
+
+/**
+ * do_scmi() - SCMI utility
+ *
+ * @cmdtp: Command table
+ * @flag: Command flag
+ * @argc: Number of arguments
+ * @argv: Argument array
+ *
+ * Provide user interfaces to SCMI protocols.
+ *
+ * Return: CMD_RET_SUCCESS on success,
+ * CMD_RET_USAGE or CMD_RET_RET_FAILURE on failure
+ */
+static int do_scmi(struct cmd_tbl *cmdtp, int flag,
+ int argc, char *const argv[])
+{
+ struct cmd_tbl *cp;
+
+ if (argc < 2)
+ return CMD_RET_USAGE;
+
+ argc--; argv++;
+
+ cp = find_cmd_tbl(argv[0], cmd_scmi_sub, ARRAY_SIZE(cmd_scmi_sub));
+ if (!cp)
+ return CMD_RET_USAGE;
+
+ return cp->cmd(cmdtp, flag, argc, argv);
+}
+
+static char scmi_help_text[] =
+ " - SCMI utility\n"
+ " info - get the info of SCMI services\n"
+ " perm_dev <agent-id in hex> <device-id in hex> <flags in hex>\n"
+ " - set access permission to device\n"
+ " perm_proto <agent-id in hex> <device-id in hex> <protocol-id in hex> <flags in hex>\n"
+ " - set protocol permission to device\n"
+ " reset <agent-id in hex> <flags in hex>\n"
+ " - reset platform resource settings\n"
+ "";
+
+U_BOOT_CMD(scmi, CONFIG_SYS_MAXARGS, 0, do_scmi, "SCMI utility",
+ scmi_help_text);
diff --git a/cmd/sf.c b/cmd/sf.c
index 30b2bd5..730996c 100644
--- a/cmd/sf.c
+++ b/cmd/sf.c
@@ -604,7 +604,7 @@
ret = do_spi_flash_read_write(argc, argv);
else if (strcmp(cmd, "erase") == 0)
ret = do_spi_flash_erase(argc, argv);
- else if (strcmp(cmd, "protect") == 0)
+ else if (IS_ENABLED(CONFIG_SPI_FLASH_LOCK) && strcmp(cmd, "protect") == 0)
ret = do_spi_protect(argc, argv);
else if (IS_ENABLED(CONFIG_CMD_SF_TEST) && !strcmp(cmd, "test"))
ret = do_spi_flash_test(argc, argv);
@@ -629,8 +629,10 @@
"sf update addr offset|partition len - erase and write `len' bytes from memory\n"
" at `addr' to flash at `offset'\n"
" or to start of mtd `partition'\n"
+#ifdef CONFIG_SPI_FLASH_LOCK
"sf protect lock/unlock sector len - protect/unprotect 'len' bytes starting\n"
" at address 'sector'"
+#endif
#ifdef CONFIG_CMD_SF_TEST
"\nsf test offset len - run a very basic destructive test"
#endif
diff --git a/cmd/ti/Makefile b/cmd/ti/Makefile
index 87f85b2..5f9c64f 100644
--- a/cmd/ti/Makefile
+++ b/cmd/ti/Makefile
@@ -1,5 +1,5 @@
# SPDX-License-Identifier: GPL-2.0+
-# Copyright (C) 2017 Texas Instruments Incorporated - http://www.ti.com/
+# Copyright (C) 2017 Texas Instruments Incorporated - https://www.ti.com/
obj-$(CONFIG_CMD_DDR3) += ddr3.o
obj-$(CONFIG_CMD_PD) += pd.o
diff --git a/cmd/ufs.c b/cmd/ufs.c
index 143e946..536bd85 100644
--- a/cmd/ufs.c
+++ b/cmd/ufs.c
@@ -2,7 +2,7 @@
/**
* ufs.c - UFS specific U-Boot commands
*
- * Copyright (C) 2019 Texas Instruments Incorporated - http://www.ti.com
+ * Copyright (C) 2019 Texas Instruments Incorporated - https://www.ti.com
*
*/
#include <common.h>
@@ -32,6 +32,6 @@
}
U_BOOT_CMD(ufs, 3, 1, do_ufs,
- "UFS sub system",
+ "UFS sub-system",
"init [dev] - init UFS subsystem\n"
);
diff --git a/common/board_info.c b/common/board_info.c
index e0f2d93..f4c385a 100644
--- a/common/board_info.c
+++ b/common/board_info.c
@@ -15,41 +15,65 @@
return 0;
}
-/*
- * Check sysinfo for board information. Failing that if the root node of the DTB
- * has a "model" property, show it.
- *
- * Then call checkboard().
- */
-int __weak show_board_info(void)
+static const struct to_show {
+ const char *name;
+ enum sysinfo_id id;
+} to_show[] = {
+ { "Manufacturer", SYSINFO_ID_BOARD_MANUFACTURER},
+ { "Prior-stage version", SYSINFO_ID_PRIOR_STAGE_VERSION },
+ { "Prior-stage date", SYSINFO_ID_PRIOR_STAGE_DATE },
+ { /* sentinel */ }
+};
+
+static int try_sysinfo(void)
+{
+ struct udevice *dev;
+ char str[80];
+ int ret;
+
+ /* This might provide more detail */
+ ret = sysinfo_get(&dev);
+ if (ret)
+ return ret;
+
+ ret = sysinfo_detect(dev);
+ if (ret)
+ return ret;
+
+ ret = sysinfo_get_str(dev, SYSINFO_ID_BOARD_MODEL, sizeof(str), str);
+ if (ret)
+ return ret;
+ printf("Model: %s\n", str);
+
+ if (IS_ENABLED(CONFIG_SYSINFO_EXTRA)) {
+ const struct to_show *item;
+
+ for (item = to_show; item->id; item++) {
+ ret = sysinfo_get_str(dev, item->id, sizeof(str), str);
+ if (!ret)
+ printf("%s: %s\n", item->name, str);
+ }
+ }
+
+ return 0;
+}
+
+int show_board_info(void)
{
if (IS_ENABLED(CONFIG_OF_CONTROL)) {
- struct udevice *dev;
- const char *model;
- char str[80];
int ret = -ENOSYS;
- if (IS_ENABLED(CONFIG_SYSINFO)) {
- /* This might provide more detail */
- ret = sysinfo_get(&dev);
- if (!ret) {
- ret = sysinfo_detect(dev);
- if (!ret) {
- ret = sysinfo_get_str(dev,
- SYSINFO_ID_BOARD_MODEL,
- sizeof(str), str);
- }
- }
- }
+ if (IS_ENABLED(CONFIG_SYSINFO))
+ ret = try_sysinfo();
/* Fail back to the main 'model' if available */
- if (ret)
- model = fdt_getprop(gd->fdt_blob, 0, "model", NULL);
- else
- model = str;
+ if (ret) {
+ const char *model;
- if (model)
- printf("Model: %s\n", model);
+ model = fdt_getprop(gd->fdt_blob, 0, "model", NULL);
+ if (model)
+ printf("Model: %s\n", model);
+ }
}
return checkboard();
diff --git a/common/bootstage.c b/common/bootstage.c
index a68d883..0e6d807 100644
--- a/common/bootstage.c
+++ b/common/bootstage.c
@@ -137,7 +137,7 @@
rec->flags = flags;
rec->id = id;
} else {
- log_warning("Bootstage space exhasuted\n");
+ log_warning("Bootstage space exhausted\n");
}
}
diff --git a/common/spl/Kconfig b/common/spl/Kconfig
index 25cd18a..fc284a5 100644
--- a/common/spl/Kconfig
+++ b/common/spl/Kconfig
@@ -183,6 +183,7 @@
config SPL_SHOW_ERRORS
bool "Show more information when something goes wrong"
+ depends on SPL_LIBCOMMON_SUPPORT
help
This enabled more verbose error messages and checking when something
goes wrong in SPL. For example, it shows the error code when U-Boot
@@ -279,8 +280,15 @@
spl_board_init() from board_init_r(). This function should be
provided by the board.
+config SPL_LOAD_BLOCK
+ bool
+ help
+ Support loading images from block devices. This adds a bl_len member
+ to struct spl_load_info.
+
config SPL_BOOTROM_SUPPORT
bool "Support returning to the BOOTROM"
+ select SPL_LOAD_BLOCK if MACH_IMX
help
Some platforms (e.g. the Rockchip RK3368) provide support in their
ROM for loading the next boot-stage after performing basic setup
@@ -473,6 +481,11 @@
banner ("U-Boot SPL ..."). This function should be provided by
the board.
+config SPL_SYS_MMCSD_RAW_MODE
+ bool
+ help
+ Support booting from an MMC without a filesystem.
+
config SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR
bool "MMC raw mode: by sector"
default y if ARCH_SUNXI || ARCH_DAVINCI || ARCH_UNIPHIER || \
@@ -481,6 +494,8 @@
ARCH_AT91 || ARCH_ZYNQ || ARCH_KEYSTONE || OMAP34XX || \
OMAP44XX || OMAP54XX || AM33XX || AM43XX || \
TARGET_SIFIVE_UNLEASHED || TARGET_SIFIVE_UNMATCHED
+ select SPL_LOAD_BLOCK if SPL_MMC
+ select SPL_SYS_MMCSD_RAW_MODE if SPL_MMC
help
Use sector number for specifying U-Boot location on MMC/SD in
raw mode.
@@ -517,6 +532,8 @@
config SYS_MMCSD_RAW_MODE_U_BOOT_USE_PARTITION
bool "MMC Raw mode: by partition"
+ select SPL_LOAD_BLOCK if SPL_MMC
+ select SPL_SYS_MMCSD_RAW_MODE if SPL_MMC
help
Use a partition for loading U-Boot when using MMC/SD in raw mode.
@@ -683,6 +700,22 @@
filesystem from within SPL. Support for the underlying block
device (e.g. MMC or USB) must be enabled separately.
+config SPL_FS_FAT_DMA_ALIGN
+ bool "Use DMA-aligned buffers with FAT"
+ depends on SPL_FS_FAT
+ select SPL_LOAD_BLOCK
+ default y if SPL_LOAD_FIT
+ help
+ The FAT filesystem driver tries to ensure that the reads it issues to
+ the block subsystem use DMA-aligned buffers. If the supplied buffer is
+ not DMA-aligned, the FAT driver will use a bounce-buffer and read
+ block-by-block. This is separate from the bounce-buffer used by the
+ block subsystem (CONFIG_BOUNCE_BUFFER).
+
+ Enable this config to align buffers passed to the FAT filesystem
+ driver. This will speed up reads, but will increase the size of U-Boot
+ by around 60 bytes.
+
config SPL_FS_LOAD_PAYLOAD_NAME
string "File to load for U-Boot from the filesystem"
depends on SPL_FS_EXT4 || SPL_FS_FAT || SPL_FS_SQUASHFS || SPL_SEMIHOSTING
@@ -857,7 +890,7 @@
allows DRAM to be set up before loading U-Boot into that DRAM,
where it can run.
-config SPL_MTD_SUPPORT
+config SPL_MTD
bool "Support MTD drivers"
help
Enable support for MTD (Memory Technology Device) within SPL. MTD
@@ -876,6 +909,7 @@
config SPL_NAND_SUPPORT
bool "Support NAND flash"
+ select SPL_LOAD_BLOCK
help
Enable support for NAND (Negative AND) flash in SPL. NAND flash
can be used to allow SPL to load U-Boot from supported devices.
@@ -1101,6 +1135,8 @@
config SPL_FALCON_BOOT_MMCSD
bool "Enable Falcon boot from MMC or SD media"
depends on SPL_OS_BOOT && SPL_MMC
+ select SPL_LOAD_BLOCK
+ select SPL_SYS_MMCSD_RAW_MODE
help
Select this if the Falcon mode OS image mode is on MMC or SD media.
@@ -1259,7 +1295,6 @@
config SPL_NVME
bool "NVM Express device support"
depends on BLK
- select HAVE_BLOCK_DEVICE
select FS_LOADER
select SPL_BLK_FS
help
diff --git a/common/spl/Makefile b/common/spl/Makefile
index 4f8eb2e..4809f9c 100644
--- a/common/spl/Makefile
+++ b/common/spl/Makefile
@@ -1,7 +1,7 @@
# SPDX-License-Identifier: GPL-2.0+
#
# (C) Copyright 2012
-# Texas Instruments Incorporated - http://www.ti.com/
+# Texas Instruments Incorporated - https://www.ti.com/
# Aneesh V <aneesh@ti.com>
# Based on common/Makefile.
#
diff --git a/common/spl/spl.c b/common/spl/spl.c
index 732d90d..3ce5bfe 100644
--- a/common/spl/spl.c
+++ b/common/spl/spl.c
@@ -19,6 +19,7 @@
#include <mapmem.h>
#include <serial.h>
#include <spl.h>
+#include <spl_load.h>
#include <system-constants.h>
#include <asm/global_data.h>
#include <asm-generic/gpio.h>
@@ -352,6 +353,15 @@
return 0;
}
+#if SPL_LOAD_USERS > 1
+int spl_load(struct spl_image_info *spl_image,
+ const struct spl_boot_device *bootdev, struct spl_load_info *info,
+ size_t size, size_t offset)
+{
+ return _spl_load(spl_image, bootdev, info, size, offset);
+}
+#endif
+
__weak void __noreturn jump_to_image_no_args(struct spl_image_info *spl_image)
{
typedef void __noreturn (*image_entry_noargs_t)(void);
@@ -718,8 +728,7 @@
ret = boot_from_devices(&spl_image, spl_boot_list,
ARRAY_SIZE(spl_boot_list));
if (ret) {
- if (CONFIG_IS_ENABLED(SHOW_ERRORS) &&
- CONFIG_IS_ENABLED(LIBCOMMON_SUPPORT))
+ if (CONFIG_IS_ENABLED(SHOW_ERRORS))
printf(SPL_TPL_PROMPT "failed to boot from all boot devices (err=%d)\n",
ret);
else
diff --git a/common/spl/spl_blk_fs.c b/common/spl/spl_blk_fs.c
index 63825d6..04eac6f 100644
--- a/common/spl/spl_blk_fs.c
+++ b/common/spl/spl_blk_fs.c
@@ -7,12 +7,15 @@
#include <common.h>
#include <spl.h>
+#include <spl_load.h>
#include <image.h>
#include <fs.h>
+#include <asm/cache.h>
#include <asm/io.h>
struct blk_dev {
const char *ifname;
+ const char *filename;
char dev_part_str[8];
};
@@ -30,11 +33,11 @@
return ret;
}
- ret = fs_read(load->filename, virt_to_phys(buf), file_offset, size,
+ ret = fs_read(dev->filename, virt_to_phys(buf), file_offset, size,
&actlen);
if (ret < 0) {
printf("spl: error reading image %s. Err - %d\n",
- load->filename, ret);
+ dev->filename, ret);
return ret;
}
@@ -46,10 +49,10 @@
enum uclass_id uclass_id, int devnum, int partnum)
{
const char *filename = CONFIG_SPL_FS_LOAD_PAYLOAD_NAME;
- struct legacy_img_hdr *header;
struct blk_desc *blk_desc;
- loff_t actlen, filesize;
+ loff_t filesize;
struct blk_dev dev;
+ struct spl_load_info load;
int ret;
blk_desc = blk_get_devnum_by_uclass_id(uclass_id, devnum);
@@ -59,8 +62,8 @@
}
blk_show_device(uclass_id, devnum);
- header = spl_get_load_buffer(-sizeof(*header), sizeof(*header));
+ dev.filename = filename;
dev.ifname = blk_get_uclass_name(uclass_id);
snprintf(dev.dev_part_str, sizeof(dev.dev_part_str) - 1, "%x:%x",
devnum, partnum);
@@ -68,63 +71,21 @@
if (ret) {
printf("spl: unable to set blk_dev %s %s. Err - %d\n",
dev.ifname, dev.dev_part_str, ret);
- goto out;
- }
-
- ret = fs_read(filename, virt_to_phys(header), 0,
- sizeof(struct legacy_img_hdr), &actlen);
- if (ret) {
- printf("spl: unable to read file %s. Err - %d\n", filename,
- ret);
- goto out;
- }
-
- if (IS_ENABLED(CONFIG_SPL_LOAD_FIT) &&
- image_get_magic(header) == FDT_MAGIC) {
- struct spl_load_info load;
-
- debug("Found FIT\n");
- load.read = spl_fit_read;
- load.bl_len = 1;
- load.filename = (void *)filename;
- load.priv = &dev;
-
- return spl_load_simple_fit(spl_image, &load, 0, header);
- }
-
- ret = spl_parse_image_header(spl_image, bootdev, header);
- if (ret) {
- printf("spl: unable to parse image header. Err - %d\n",
- ret);
- goto out;
- }
-
- ret = fs_set_blk_dev(dev.ifname, dev.dev_part_str, FS_TYPE_ANY);
- if (ret) {
- printf("spl: unable to set blk_dev %s %s. Err - %d\n",
- dev.ifname, dev.dev_part_str, ret);
- goto out;
+ return ret;
}
ret = fs_size(filename, &filesize);
if (ret) {
printf("spl: unable to get file size: %s. Err - %d\n",
filename, ret);
- goto out;
- }
-
- ret = fs_set_blk_dev(dev.ifname, dev.dev_part_str, FS_TYPE_ANY);
- if (ret) {
- printf("spl: unable to set blk_dev %s %s. Err - %d\n",
- dev.ifname, dev.dev_part_str, ret);
- goto out;
+ return ret;
}
- ret = fs_read(filename, (ulong)spl_image->load_addr, 0, filesize,
- &actlen);
- if (ret)
- printf("spl: unable to read file %s. Err - %d\n",
- filename, ret);
-out:
- return ret;
+ load.read = spl_fit_read;
+ if (IS_ENABLED(CONFIG_SPL_FS_FAT_DMA_ALIGN))
+ spl_set_bl_len(&load, ARCH_DMA_MINALIGN);
+ else
+ spl_set_bl_len(&load, 1);
+ load.priv = &dev;
+ return spl_load(spl_image, bootdev, &load, filesize, 0);
}
diff --git a/common/spl/spl_ext.c b/common/spl/spl_ext.c
index af836ca..2be6f04 100644
--- a/common/spl/spl_ext.c
+++ b/common/spl/spl_ext.c
@@ -2,25 +2,35 @@
#include <common.h>
#include <env.h>
-#include <mapmem.h>
#include <part.h>
#include <spl.h>
+#include <spl_load.h>
#include <asm/u-boot.h>
#include <ext4fs.h>
#include <errno.h>
#include <image.h>
+static ulong spl_fit_read(struct spl_load_info *load, ulong file_offset,
+ ulong size, void *buf)
+{
+ int ret;
+ loff_t actlen;
+
+ ret = ext4fs_read(buf, file_offset, size, &actlen);
+ if (ret)
+ return ret;
+ return actlen;
+}
+
int spl_load_image_ext(struct spl_image_info *spl_image,
struct spl_boot_device *bootdev,
struct blk_desc *block_dev, int partition,
const char *filename)
{
s32 err;
- struct legacy_img_hdr *header;
- loff_t filelen, actlen;
+ loff_t filelen;
struct disk_partition part_info = {};
-
- header = spl_get_load_buffer(-sizeof(*header), sizeof(*header));
+ struct spl_load_info load;
if (part_get_info(block_dev, partition, &part_info)) {
printf("spl: no partition table found\n");
@@ -29,7 +39,7 @@
ext4fs_set_blk_dev(block_dev, &part_info);
- err = ext4fs_mount(part_info.size);
+ err = ext4fs_mount();
if (!err) {
#ifdef CONFIG_SPL_LIBCOMMON_SUPPORT
printf("%s: ext4fs mount err - %d\n", __func__, err);
@@ -42,20 +52,10 @@
puts("spl: ext4fs_open failed\n");
goto end;
}
- err = ext4fs_read((char *)header, 0, sizeof(struct legacy_img_hdr), &actlen);
- if (err < 0) {
- puts("spl: ext4fs_read failed\n");
- goto end;
- }
-
- err = spl_parse_image_header(spl_image, bootdev, header);
- if (err < 0) {
- puts("spl: ext: failed to parse image header\n");
- goto end;
- }
- err = ext4fs_read(map_sysmem(spl_image->load_addr, filelen), 0, filelen,
- &actlen);
+ spl_set_bl_len(&load, 1);
+ load.read = spl_fit_read;
+ err = spl_load(spl_image, bootdev, &load, filelen, 0);
end:
#ifdef CONFIG_SPL_LIBCOMMON_SUPPORT
@@ -84,7 +84,7 @@
ext4fs_set_blk_dev(block_dev, &part_info);
- err = ext4fs_mount(part_info.size);
+ err = ext4fs_mount();
if (!err) {
#ifdef CONFIG_SPL_LIBCOMMON_SUPPORT
printf("%s: ext4fs mount err - %d\n", __func__, err);
diff --git a/common/spl/spl_fat.c b/common/spl/spl_fat.c
index 014074f..a52f9e1 100644
--- a/common/spl/spl_fat.c
+++ b/common/spl/spl_fat.c
@@ -11,8 +11,8 @@
#include <common.h>
#include <env.h>
#include <log.h>
-#include <mapmem.h>
#include <spl.h>
+#include <spl_load.h>
#include <asm/u-boot.h>
#include <fat.h>
#include <errno.h>
@@ -51,7 +51,7 @@
{
loff_t actread;
int ret;
- char *filename = (char *)load->filename;
+ char *filename = load->priv;
ret = fat_read_file(filename, buf, file_offset, size, &actread);
if (ret)
@@ -66,59 +66,41 @@
const char *filename)
{
int err;
- struct legacy_img_hdr *header;
+ loff_t size;
+ struct spl_load_info load;
err = spl_register_fat_device(block_dev, partition);
if (err)
goto end;
- header = spl_get_load_buffer(-sizeof(*header), sizeof(*header));
-
- err = file_fat_read(filename, header, sizeof(struct legacy_img_hdr));
- if (err <= 0)
- goto end;
-
- if (IS_ENABLED(CONFIG_SPL_LOAD_FIT_FULL) &&
- image_get_magic(header) == FDT_MAGIC) {
- err = file_fat_read(filename,
- map_sysmem(CONFIG_SYS_LOAD_ADDR, 0), 0);
- if (err <= 0)
- goto end;
- err = spl_parse_image_header(spl_image, bootdev,
- map_sysmem(CONFIG_SYS_LOAD_ADDR,
- err));
- if (err == -EAGAIN)
- return err;
- if (err == 0)
- err = 1;
- } else if (IS_ENABLED(CONFIG_SPL_LOAD_FIT) &&
- image_get_magic(header) == FDT_MAGIC) {
- struct spl_load_info load;
-
- debug("Found FIT\n");
- load.read = spl_fit_read;
- load.bl_len = 1;
- load.filename = (void *)filename;
- load.priv = NULL;
-
- return spl_load_simple_fit(spl_image, &load, 0, header);
- } else {
- err = spl_parse_image_header(spl_image, bootdev, header);
+ /*
+ * Avoid pulling in this function for other image types since we are
+ * very short on space on some boards.
+ */
+ if (IS_ENABLED(CONFIG_SPL_LOAD_FIT_FULL)) {
+ err = fat_size(filename, &size);
if (err)
goto end;
-
- err = file_fat_read(filename, map_sysmem(spl_image->load_addr,
- spl_image->size), 0);
+ } else {
+ size = 0;
}
+ load.read = spl_fit_read;
+ if (IS_ENABLED(CONFIG_SPL_FS_FAT_DMA_ALIGN))
+ spl_set_bl_len(&load, ARCH_DMA_MINALIGN);
+ else
+ spl_set_bl_len(&load, 1);
+ load.priv = (void *)filename;
+ err = spl_load(spl_image, bootdev, &load, size, 0);
+
end:
#ifdef CONFIG_SPL_LIBCOMMON_SUPPORT
- if (err <= 0)
+ if (err < 0)
printf("%s: error reading image %s, err - %d\n",
__func__, filename, err);
#endif
- return (err <= 0);
+ return err;
}
#if CONFIG_IS_ENABLED(OS_BOOT)
diff --git a/common/spl/spl_fit.c b/common/spl/spl_fit.c
index 70d8d59..872df0c 100644
--- a/common/spl/spl_fit.c
+++ b/common/spl/spl_fit.c
@@ -14,7 +14,6 @@
#include <mapmem.h>
#include <spl.h>
#include <sysinfo.h>
-#include <asm/cache.h>
#include <asm/global_data.h>
#include <asm/io.h>
#include <linux/libfdt.h>
@@ -172,29 +171,12 @@
static int get_aligned_image_offset(struct spl_load_info *info, int offset)
{
- /*
- * If it is a FS read, get the first address before offset which is
- * aligned to ARCH_DMA_MINALIGN. If it is raw read return the
- * block number to which offset belongs.
- */
- if (info->filename)
- return offset & ~(ARCH_DMA_MINALIGN - 1);
-
- return offset / info->bl_len;
+ return ALIGN_DOWN(offset, spl_get_bl_len(info));
}
static int get_aligned_image_overhead(struct spl_load_info *info, int offset)
{
- /*
- * If it is a FS read, get the difference between the offset and
- * the first address before offset which is aligned to
- * ARCH_DMA_MINALIGN. If it is raw read return the offset within the
- * block.
- */
- if (info->filename)
- return offset & (ARCH_DMA_MINALIGN - 1);
-
- return offset % info->bl_len;
+ return offset & (spl_get_bl_len(info) - 1);
}
static int get_aligned_image_size(struct spl_load_info *info, int data_size,
@@ -202,10 +184,7 @@
{
data_size = data_size + get_aligned_image_overhead(info, offset);
- if (info->filename)
- return data_size;
-
- return (data_size + info->bl_len - 1) / info->bl_len;
+ return ALIGN(data_size, spl_get_bl_len(info));
}
/**
@@ -222,7 +201,7 @@
*
* Return: 0 on success or a negative error number.
*/
-static int load_simple_fit(struct spl_load_info *info, ulong sector,
+static int load_simple_fit(struct spl_load_info *info, ulong fit_offset,
const struct spl_fit_info *ctx, int node,
struct spl_image_info *image_info)
{
@@ -234,7 +213,6 @@
void *load_ptr;
void *src;
ulong overhead;
- int nr_sectors;
uint8_t image_comp = -1, type = -1;
const void *data;
const void *fit = ctx->fit;
@@ -291,11 +269,12 @@
length = len;
overhead = get_aligned_image_overhead(info, offset);
- nr_sectors = get_aligned_image_size(info, length, offset);
+ size = get_aligned_image_size(info, length, offset);
if (info->read(info,
- sector + get_aligned_image_offset(info, offset),
- nr_sectors, src_ptr) != nr_sectors)
+ fit_offset +
+ get_aligned_image_offset(info, offset), size,
+ src_ptr) < length)
return -EIO;
debug("External data: dst=%p, offset=%x, size=%lx\n",
@@ -380,7 +359,7 @@
}
static int spl_fit_append_fdt(struct spl_image_info *spl_image,
- struct spl_load_info *info, ulong sector,
+ struct spl_load_info *info, ulong offset,
const struct spl_fit_info *ctx)
{
struct spl_image_info image_info;
@@ -414,7 +393,7 @@
spl_image->fdt_addr = map_sysmem(image_info.load_addr, size);
memcpy(spl_image->fdt_addr, gd->fdt_blob, size);
} else {
- ret = load_simple_fit(info, sector, ctx, node, &image_info);
+ ret = load_simple_fit(info, offset, ctx, node, &image_info);
if (ret < 0)
return ret;
@@ -465,7 +444,7 @@
__func__);
}
image_info.load_addr = (ulong)tmpbuffer;
- ret = load_simple_fit(info, sector, ctx, node,
+ ret = load_simple_fit(info, offset, ctx, node,
&image_info);
if (ret < 0)
break;
@@ -642,7 +621,7 @@
}
static int spl_fit_load_fpga(struct spl_fit_info *ctx,
- struct spl_load_info *info, ulong sector)
+ struct spl_load_info *info, ulong offset)
{
int node, ret;
@@ -657,7 +636,7 @@
warn_deprecated("'fpga' property in config node. Use 'loadables'");
/* Load the image and set up the fpga_image structure */
- ret = load_simple_fit(info, sector, ctx, node, &fpga_image);
+ ret = load_simple_fit(info, offset, ctx, node, &fpga_image);
if (ret) {
printf("%s: Cannot load the FPGA: %i\n", __func__, ret);
return ret;
@@ -667,11 +646,10 @@
}
static int spl_simple_fit_read(struct spl_fit_info *ctx,
- struct spl_load_info *info, ulong sector,
+ struct spl_load_info *info, ulong offset,
const void *fit_header)
{
unsigned long count, size;
- int sectors;
void *buf;
/*
@@ -690,13 +668,13 @@
* For FIT with data embedded, data is loaded as part of FIT image.
* For FIT with external data, data is not loaded in this step.
*/
- sectors = get_aligned_image_size(info, size, 0);
- buf = board_spl_fit_buffer_addr(size, sectors, info->bl_len);
+ size = get_aligned_image_size(info, size, 0);
+ buf = board_spl_fit_buffer_addr(size, size, 1);
- count = info->read(info, sector, sectors, buf);
+ count = info->read(info, offset, size, buf);
ctx->fit = buf;
- debug("fit read sector %lx, sectors=%d, dst=%p, count=%lu, size=0x%lx\n",
- sector, sectors, buf, count, size);
+ debug("fit read offset %lx, size=%lu, dst=%p, count=%lu\n",
+ offset, size, buf, count);
return (count == 0) ? -EIO : 0;
}
@@ -728,7 +706,7 @@
}
int spl_load_simple_fit(struct spl_image_info *spl_image,
- struct spl_load_info *info, ulong sector, void *fit)
+ struct spl_load_info *info, ulong offset, void *fit)
{
struct spl_image_info image_info;
struct spl_fit_info ctx;
@@ -737,7 +715,7 @@
int index = 0;
int firmware_node;
- ret = spl_simple_fit_read(&ctx, info, sector, fit);
+ ret = spl_simple_fit_read(&ctx, info, offset, fit);
if (ret < 0)
return ret;
@@ -752,7 +730,7 @@
return ret;
if (IS_ENABLED(CONFIG_SPL_FPGA))
- spl_fit_load_fpga(&ctx, info, sector);
+ spl_fit_load_fpga(&ctx, info, offset);
/*
* Find the U-Boot image using the following search order:
@@ -782,7 +760,7 @@
}
/* Load the image and set up the spl_image structure */
- ret = load_simple_fit(info, sector, &ctx, node, spl_image);
+ ret = load_simple_fit(info, offset, &ctx, node, spl_image);
if (ret)
return ret;
@@ -800,7 +778,7 @@
* We allow this to fail, as the U-Boot image might embed its FDT.
*/
if (os_takes_devicetree(spl_image->os)) {
- ret = spl_fit_append_fdt(spl_image, info, sector, &ctx);
+ ret = spl_fit_append_fdt(spl_image, info, offset, &ctx);
if (ret < 0 && spl_image->os != IH_OS_U_BOOT)
return ret;
}
@@ -823,7 +801,7 @@
continue;
image_info.load_addr = 0;
- ret = load_simple_fit(info, sector, &ctx, node, &image_info);
+ ret = load_simple_fit(info, offset, &ctx, node, &image_info);
if (ret < 0) {
printf("%s: can't load image loadables index %d (ret = %d)\n",
__func__, index, ret);
@@ -837,7 +815,7 @@
debug("Loadable is %s\n", genimg_get_os_name(os_type));
if (os_takes_devicetree(os_type)) {
- spl_fit_append_fdt(&image_info, info, sector, &ctx);
+ spl_fit_append_fdt(&image_info, info, offset, &ctx);
spl_image->fdt_addr = image_info.fdt_addr;
}
diff --git a/common/spl/spl_imx_container.c b/common/spl/spl_imx_container.c
index 127802f..b4ea924 100644
--- a/common/spl/spl_imx_container.c
+++ b/common/spl/spl_imx_container.c
@@ -19,11 +19,10 @@
struct spl_load_info *info,
struct container_hdr *container,
int image_index,
- u32 container_sector)
+ ulong container_offset)
{
struct boot_img_t *images;
- ulong sector;
- u32 sectors;
+ ulong offset, overhead, size;
if (image_index > container->num_images) {
debug("Invalid image number\n");
@@ -33,22 +32,21 @@
images = (struct boot_img_t *)((u8 *)container +
sizeof(struct container_hdr));
- if (images[image_index].offset % info->bl_len) {
+ if (!IS_ALIGNED(images[image_index].offset, spl_get_bl_len(info))) {
printf("%s: image%d offset not aligned to %u\n",
- __func__, image_index, info->bl_len);
+ __func__, image_index, spl_get_bl_len(info));
return NULL;
}
- sectors = roundup(images[image_index].size, info->bl_len) /
- info->bl_len;
- sector = images[image_index].offset / info->bl_len +
- container_sector;
+ size = ALIGN(images[image_index].size, spl_get_bl_len(info));
+ offset = images[image_index].offset + container_offset;
- debug("%s: container: %p sector: %lu sectors: %u\n", __func__,
- container, sector, sectors);
- if (info->read(info, sector, sectors,
- map_sysmem(images[image_index].dst,
- images[image_index].size)) != sectors) {
+ debug("%s: container: %p offset: %lu size: %lu\n", __func__,
+ container, offset, size);
+ if (info->read(info, offset, size,
+ map_sysmem(images[image_index].dst - overhead,
+ images[image_index].size)) <
+ images[image_index].size) {
printf("%s wrong\n", __func__);
return NULL;
}
@@ -62,15 +60,13 @@
}
static int read_auth_container(struct spl_image_info *spl_image,
- struct spl_load_info *info, ulong sector)
+ struct spl_load_info *info, ulong offset)
{
struct container_hdr *container = NULL;
u16 length;
- u32 sectors;
int i, size, ret = 0;
- size = roundup(CONTAINER_HDR_ALIGNMENT, info->bl_len);
- sectors = size / info->bl_len;
+ size = ALIGN(CONTAINER_HDR_ALIGNMENT, spl_get_bl_len(info));
/*
* It will not override the ATF code, so safe to use it here,
@@ -80,9 +76,10 @@
if (!container)
return -ENOMEM;
- debug("%s: container: %p sector: %lu sectors: %u\n", __func__,
- container, sector, sectors);
- if (info->read(info, sector, sectors, container) != sectors) {
+ debug("%s: container: %p offset: %lu size: %u\n", __func__,
+ container, offset, size);
+ if (info->read(info, offset, size, container) <
+ CONTAINER_HDR_ALIGNMENT) {
ret = -EIO;
goto end;
}
@@ -103,18 +100,16 @@
debug("Container length %u\n", length);
if (length > CONTAINER_HDR_ALIGNMENT) {
- size = roundup(length, info->bl_len);
- sectors = size / info->bl_len;
+ size = ALIGN(length, spl_get_bl_len(info));
free(container);
container = malloc(size);
if (!container)
return -ENOMEM;
- debug("%s: container: %p sector: %lu sectors: %u\n",
- __func__, container, sector, sectors);
- if (info->read(info, sector, sectors, container) !=
- sectors) {
+ debug("%s: container: %p offset: %lu size: %u\n",
+ __func__, container, offset, size);
+ if (info->read(info, offset, size, container) < length) {
ret = -EIO;
goto end;
}
@@ -129,7 +124,7 @@
for (i = 0; i < container->num_images; i++) {
struct boot_img_t *image = read_auth_image(spl_image, info,
container, i,
- sector);
+ offset);
if (!image) {
ret = -EINVAL;
@@ -154,7 +149,7 @@
}
int spl_load_imx_container(struct spl_image_info *spl_image,
- struct spl_load_info *info, ulong sector)
+ struct spl_load_info *info, ulong offset)
{
- return read_auth_container(spl_image, info, sector);
+ return read_auth_container(spl_image, info, offset);
}
diff --git a/common/spl/spl_legacy.c b/common/spl/spl_legacy.c
index 51656fb..08687ca 100644
--- a/common/spl/spl_legacy.c
+++ b/common/spl/spl_legacy.c
@@ -82,89 +82,39 @@
return 0;
}
-/*
- * This function is added explicitly to avoid code size increase, when
- * no compression method is enabled. The compiler will optimize the
- * following switch/case statement in spl_load_legacy_img() away due to
- * Dead Code Elimination.
- */
-static inline int spl_image_get_comp(const struct legacy_img_hdr *hdr)
+int spl_load_legacy_lzma(struct spl_image_info *spl_image,
+ struct spl_load_info *load, ulong offset)
{
- if (IS_ENABLED(CONFIG_SPL_LZMA))
- return image_get_comp(hdr);
-
- return IH_COMP_NONE;
-}
-
-int spl_load_legacy_img(struct spl_image_info *spl_image,
- struct spl_boot_device *bootdev,
- struct spl_load_info *load, ulong offset,
- struct legacy_img_hdr *hdr)
-{
- __maybe_unused SizeT lzma_len;
- __maybe_unused void *src;
- ulong dataptr;
+ SizeT lzma_len = LZMA_LEN;
+ void *src;
+ ulong dataptr, overhead, size;
int ret;
- /*
- * If the payload is compressed, the decompressed data should be
- * directly write to its load address.
- */
- if (spl_image_get_comp(hdr) != IH_COMP_NONE)
- spl_image->flags |= SPL_COPY_PAYLOAD_ONLY;
-
- ret = spl_parse_image_header(spl_image, bootdev, hdr);
- if (ret)
- return ret;
-
- /* Read image */
- switch (spl_image_get_comp(hdr)) {
- case IH_COMP_NONE:
- dataptr = offset;
-
- /*
- * Image header will be skipped only if SPL_COPY_PAYLOAD_ONLY
- * is set
- */
- if (spl_image->flags & SPL_COPY_PAYLOAD_ONLY)
- dataptr += sizeof(*hdr);
+ /* dataptr points to compressed payload */
+ dataptr = ALIGN_DOWN(sizeof(struct legacy_img_hdr),
+ spl_get_bl_len(load));
+ overhead = sizeof(struct legacy_img_hdr) - dataptr;
+ size = ALIGN(spl_image->size + overhead, spl_get_bl_len(load));
+ dataptr += offset;
- load->read(load, dataptr, spl_image->size,
- map_sysmem(spl_image->load_addr, spl_image->size));
- break;
-
- case IH_COMP_LZMA:
- lzma_len = LZMA_LEN;
-
- /* dataptr points to compressed payload */
- dataptr = offset + sizeof(*hdr);
-
- debug("LZMA: Decompressing %08lx to %08lx\n",
- dataptr, spl_image->load_addr);
- src = malloc(spl_image->size);
- if (!src) {
- printf("Unable to allocate %d bytes for LZMA\n",
- spl_image->size);
- return -ENOMEM;
- }
-
- load->read(load, dataptr, spl_image->size, src);
- ret = lzmaBuffToBuffDecompress(map_sysmem(spl_image->load_addr,
- spl_image->size),
- &lzma_len, src, spl_image->size);
- if (ret) {
- printf("LZMA decompression error: %d\n", ret);
- return ret;
- }
-
- spl_image->size = lzma_len;
- break;
+ debug("LZMA: Decompressing %08lx to %08lx\n",
+ dataptr, spl_image->load_addr);
+ src = malloc(size);
+ if (!src) {
+ printf("Unable to allocate %d bytes for LZMA\n",
+ spl_image->size);
+ return -ENOMEM;
+ }
- default:
- debug("Compression method %s is not supported\n",
- genimg_get_comp_short_name(image_get_comp(hdr)));
- return -EINVAL;
+ load->read(load, dataptr, size, src);
+ ret = lzmaBuffToBuffDecompress(map_sysmem(spl_image->load_addr,
+ spl_image->size), &lzma_len,
+ src + overhead, spl_image->size);
+ if (ret) {
+ printf("LZMA decompression error: %d\n", ret);
+ return ret;
}
+ spl_image->size = lzma_len;
return 0;
}
diff --git a/common/spl/spl_mmc.c b/common/spl/spl_mmc.c
index 82689da..3d032bb 100644
--- a/common/spl/spl_mmc.c
+++ b/common/spl/spl_mmc.c
@@ -8,9 +8,9 @@
#include <common.h>
#include <dm.h>
#include <log.h>
-#include <mapmem.h>
#include <part.h>
#include <spl.h>
+#include <spl_load.h>
#include <linux/compiler.h>
#include <errno.h>
#include <asm/u-boot.h>
@@ -19,55 +19,14 @@
#include <image.h>
#include <imx_container.h>
-static int mmc_load_legacy(struct spl_image_info *spl_image,
- struct spl_boot_device *bootdev,
- struct mmc *mmc,
- ulong sector, struct legacy_img_hdr *header)
+static ulong h_spl_load_read(struct spl_load_info *load, ulong off,
+ ulong size, void *buf)
{
- u32 image_offset_sectors;
- u32 image_size_sectors;
- unsigned long count;
- u32 image_offset;
- int ret;
-
- ret = spl_parse_image_header(spl_image, bootdev, header);
- if (ret)
- return ret;
-
- /* convert offset to sectors - round down */
- image_offset_sectors = spl_image->offset / mmc->read_bl_len;
- /* calculate remaining offset */
- image_offset = spl_image->offset % mmc->read_bl_len;
-
- /* convert size to sectors - round up */
- image_size_sectors = (spl_image->size + mmc->read_bl_len - 1) /
- mmc->read_bl_len;
-
- /* Read the header too to avoid extra memcpy */
- count = blk_dread(mmc_get_blk_desc(mmc),
- sector + image_offset_sectors,
- image_size_sectors,
- map_sysmem(spl_image->load_addr,
- image_size_sectors * mmc->read_bl_len));
- debug("read %x sectors to %lx\n", image_size_sectors,
- spl_image->load_addr);
- if (count != image_size_sectors)
- return -EIO;
-
- if (image_offset)
- memmove((void *)(ulong)spl_image->load_addr,
- (void *)(ulong)spl_image->load_addr + image_offset,
- spl_image->size);
-
- return 0;
-}
+ struct blk_desc *bd = load->priv;
+ lbaint_t sector = off >> bd->log2blksz;
+ lbaint_t count = size >> bd->log2blksz;
-static ulong h_spl_load_read(struct spl_load_info *load, ulong sector,
- ulong count, void *buf)
-{
- struct mmc *mmc = load->dev;
-
- return blk_dread(mmc_get_blk_desc(mmc), sector, count, buf);
+ return blk_dread(bd, sector, count, buf) << bd->log2blksz;
}
static __maybe_unused unsigned long spl_mmc_raw_uboot_offset(int part)
@@ -85,48 +44,14 @@
struct spl_boot_device *bootdev,
struct mmc *mmc, unsigned long sector)
{
- unsigned long count;
- struct legacy_img_hdr *header;
+ int ret;
struct blk_desc *bd = mmc_get_blk_desc(mmc);
- int ret = 0;
-
- header = spl_get_load_buffer(-sizeof(*header), bd->blksz);
-
- /* read image header to find the image size & load address */
- count = blk_dread(bd, sector, 1, header);
- debug("hdr read sector %lx, count=%lu\n", sector, count);
- if (count == 0) {
- ret = -EIO;
- goto end;
- }
-
- if (IS_ENABLED(CONFIG_SPL_LOAD_FIT) &&
- image_get_magic(header) == FDT_MAGIC) {
- struct spl_load_info load;
-
- debug("Found FIT\n");
- load.dev = mmc;
- load.priv = NULL;
- load.filename = NULL;
- load.bl_len = mmc->read_bl_len;
- load.read = h_spl_load_read;
- ret = spl_load_simple_fit(spl_image, &load, sector, header);
- } else if (IS_ENABLED(CONFIG_SPL_LOAD_IMX_CONTAINER) &&
- valid_container_hdr((void *)header)) {
- struct spl_load_info load;
-
- load.dev = mmc;
- load.priv = NULL;
- load.filename = NULL;
- load.bl_len = mmc->read_bl_len;
- load.read = h_spl_load_read;
-
- ret = spl_load_imx_container(spl_image, &load, sector);
- } else {
- ret = mmc_load_legacy(spl_image, bootdev, mmc, sector, header);
- }
+ struct spl_load_info load;
-end:
+ load.priv = bd;
+ spl_set_bl_len(&load, bd->blksz);
+ load.read = h_spl_load_read;
+ ret = spl_load(spl_image, bootdev, &load, 0, sector << bd->log2blksz);
if (ret) {
#ifdef CONFIG_SPL_LIBCOMMON_SUPPORT
puts("mmc_load_image_raw_sector: mmc block read error\n");
diff --git a/common/spl/spl_nand.c b/common/spl/spl_nand.c
index 07916be..3b0a152 100644
--- a/common/spl/spl_nand.c
+++ b/common/spl/spl_nand.c
@@ -10,7 +10,9 @@
#include <imx_container.h>
#include <log.h>
#include <spl.h>
+#include <spl_load.h>
#include <asm/io.h>
+#include <mapmem.h>
#include <nand.h>
#include <linux/libfdt_env.h>
#include <fdt.h>
@@ -32,7 +34,8 @@
nand_spl_load_image(spl_nand_get_uboot_raw_page(),
CFG_SYS_NAND_U_BOOT_SIZE,
- (void *)CFG_SYS_NAND_U_BOOT_DST);
+ map_sysmem(CFG_SYS_NAND_U_BOOT_DST,
+ CFG_SYS_NAND_U_BOOT_SIZE));
spl_set_header_raw_uboot(spl_image);
nand_deselect();
@@ -40,104 +43,45 @@
}
#else
-static ulong spl_nand_fit_read(struct spl_load_info *load, ulong offs,
- ulong size, void *dst)
+__weak u32 nand_spl_adjust_offset(u32 sector, u32 offs)
{
- int err;
- ulong sector;
-
- sector = *(int *)load->priv;
- offs *= load->bl_len;
- size *= load->bl_len;
- offs = sector + nand_spl_adjust_offset(sector, offs - sector);
- err = nand_spl_load_image(offs, size, dst);
- if (err)
- return 0;
-
- return size / load->bl_len;
+ return offs;
}
-static ulong spl_nand_legacy_read(struct spl_load_info *load, ulong offs,
- ulong size, void *dst)
+static ulong spl_nand_read(struct spl_load_info *load, ulong offs, ulong size,
+ void *dst)
{
int err;
+ ulong sector;
debug("%s: offs %lx, size %lx, dst %p\n",
__func__, offs, size, dst);
+ sector = *(int *)load->priv;
+ offs = sector + nand_spl_adjust_offset(sector, offs - sector);
err = nand_spl_load_image(offs, size, dst);
+ spl_set_bl_len(load, nand_page_size());
if (err)
return 0;
return size;
}
-struct mtd_info * __weak nand_get_mtd(void)
-{
- return NULL;
-}
-
static int spl_nand_load_element(struct spl_image_info *spl_image,
- struct spl_boot_device *bootdev,
- int offset, struct legacy_img_hdr *header)
+ struct spl_boot_device *bootdev, int offset)
{
- struct mtd_info *mtd = nand_get_mtd();
- int bl_len = mtd ? mtd->writesize : 1;
- int err;
-
- err = nand_spl_load_image(offset, sizeof(*header), (void *)header);
- if (err)
- return err;
-
- if (IS_ENABLED(CONFIG_SPL_LOAD_FIT) &&
- image_get_magic(header) == FDT_MAGIC) {
- struct spl_load_info load;
-
- debug("Found FIT\n");
- load.dev = NULL;
- load.priv = &offset;
- load.filename = NULL;
- load.bl_len = bl_len;
- load.read = spl_nand_fit_read;
- return spl_load_simple_fit(spl_image, &load, offset / bl_len, header);
- } else if (IS_ENABLED(CONFIG_SPL_LOAD_IMX_CONTAINER) &&
- valid_container_hdr((void *)header)) {
- struct spl_load_info load;
-
- load.dev = NULL;
- load.priv = NULL;
- load.filename = NULL;
- load.bl_len = bl_len;
- load.read = spl_nand_fit_read;
- return spl_load_imx_container(spl_image, &load, offset / bl_len);
- } else if (IS_ENABLED(CONFIG_SPL_LEGACY_IMAGE_FORMAT) &&
- image_get_magic(header) == IH_MAGIC) {
- struct spl_load_info load;
+ struct spl_load_info load;
- debug("Found legacy image\n");
- load.dev = NULL;
- load.priv = NULL;
- load.filename = NULL;
- load.bl_len = 1;
- load.read = spl_nand_legacy_read;
-
- return spl_load_legacy_img(spl_image, bootdev, &load, offset, header);
- } else {
- err = spl_parse_image_header(spl_image, bootdev, header);
- if (err)
- return err;
- return nand_spl_load_image(offset, spl_image->size,
- (void *)(ulong)spl_image->load_addr);
- }
+ load.priv = &offset;
+ spl_set_bl_len(&load, 1);
+ load.read = spl_nand_read;
+ return spl_load(spl_image, bootdev, &load, 0, offset);
}
static int spl_nand_load_image(struct spl_image_info *spl_image,
struct spl_boot_device *bootdev)
{
int err;
- struct legacy_img_hdr *header;
- int *src __attribute__((unused));
- int *dst __attribute__((unused));
#ifdef CONFIG_SPL_NAND_SOFTECC
debug("spl: nand - using sw ecc\n");
@@ -146,10 +90,12 @@
#endif
nand_init();
- header = spl_get_load_buffer(0, sizeof(*header));
-
#if CONFIG_IS_ENABLED(OS_BOOT)
if (!spl_start_uboot()) {
+ int *src, *dst;
+ struct legacy_img_hdr *header =
+ spl_get_load_buffer(0, sizeof(*header));
+
/*
* load parameter image
* load to temp position since nand_spl_load_image reads
@@ -192,20 +138,18 @@
}
#endif
#ifdef CONFIG_NAND_ENV_DST
- spl_nand_load_element(spl_image, bootdev, CONFIG_ENV_OFFSET, header);
+ spl_nand_load_element(spl_image, bootdev, CONFIG_ENV_OFFSET);
#ifdef CONFIG_ENV_OFFSET_REDUND
- spl_nand_load_element(spl_image, bootdev, CONFIG_ENV_OFFSET_REDUND, header);
+ spl_nand_load_element(spl_image, bootdev, CONFIG_ENV_OFFSET_REDUND);
#endif
#endif
/* Load u-boot */
- err = spl_nand_load_element(spl_image, bootdev, spl_nand_get_uboot_raw_page(),
- header);
+ err = spl_nand_load_element(spl_image, bootdev, spl_nand_get_uboot_raw_page());
#ifdef CONFIG_SYS_NAND_U_BOOT_OFFS_REDUND
#if CONFIG_SYS_NAND_U_BOOT_OFFS != CONFIG_SYS_NAND_U_BOOT_OFFS_REDUND
if (err)
err = spl_nand_load_element(spl_image, bootdev,
- CONFIG_SYS_NAND_U_BOOT_OFFS_REDUND,
- header);
+ CONFIG_SYS_NAND_U_BOOT_OFFS_REDUND);
#endif
#endif
nand_deselect();
diff --git a/common/spl/spl_net.c b/common/spl/spl_net.c
index f01d4df..898f9df 100644
--- a/common/spl/spl_net.c
+++ b/common/spl/spl_net.c
@@ -11,8 +11,8 @@
#include <errno.h>
#include <image.h>
#include <log.h>
-#include <mapmem.h>
#include <spl.h>
+#include <spl_load.h>
#include <net.h>
#include <linux/libfdt.h>
@@ -29,8 +29,7 @@
static int spl_net_load_image(struct spl_image_info *spl_image,
struct spl_boot_device *bootdev)
{
- struct legacy_img_hdr *header = map_sysmem(image_load_addr,
- sizeof(*header));
+ struct spl_load_info load;
int rv;
env_init();
@@ -49,27 +48,9 @@
return rv;
}
- if (IS_ENABLED(CONFIG_SPL_LOAD_FIT) &&
- image_get_magic(header) == FDT_MAGIC) {
- struct spl_load_info load;
-
- debug("Found FIT\n");
- load.bl_len = 1;
- load.read = spl_net_load_read;
- rv = spl_load_simple_fit(spl_image, &load, 0, header);
- } else {
- debug("Legacy image\n");
-
- rv = spl_parse_image_header(spl_image, bootdev, header);
- if (rv)
- return rv;
-
- memcpy(map_sysmem(spl_image->load_addr, spl_image->size),
- map_sysmem(image_load_addr, spl_image->size),
- spl_image->size);
- }
-
- return rv;
+ spl_set_bl_len(&load, 1);
+ load.read = spl_net_load_read;
+ return spl_load(spl_image, bootdev, &load, 0, 0);
}
#endif
diff --git a/common/spl/spl_nor.c b/common/spl/spl_nor.c
index 236b071..7074511 100644
--- a/common/spl/spl_nor.c
+++ b/common/spl/spl_nor.c
@@ -7,8 +7,8 @@
#include <image.h>
#include <imx_container.h>
#include <log.h>
-#include <mapmem.h>
#include <spl.h>
+#include <spl_load.h>
static ulong spl_nor_load_read(struct spl_load_info *load, ulong sector,
ulong count, void *buf)
@@ -28,8 +28,7 @@
static int spl_nor_load_image(struct spl_image_info *spl_image,
struct spl_boot_device *bootdev)
{
- struct legacy_img_hdr *header;
- __maybe_unused struct spl_load_info load;
+ struct spl_load_info load;
/*
* Loading of the payload to SDRAM is done with skipping of
@@ -43,13 +42,14 @@
* Load Linux from its location in NOR flash to its defined
* location in SDRAM
*/
- header = (void *)CONFIG_SYS_OS_BASE;
+ const struct legacy_img_hdr *header =
+ (const struct legacy_img_hdr *)CONFIG_SYS_OS_BASE;
#ifdef CONFIG_SPL_LOAD_FIT
if (image_get_magic(header) == FDT_MAGIC) {
int ret;
debug("Found FIT\n");
- load.bl_len = 1;
+ spl_set_bl_len(&load, 1);
load.read = spl_nor_load_read;
ret = spl_load_simple_fit(spl_image, &load,
@@ -93,34 +93,8 @@
* Load real U-Boot from its location in NOR flash to its
* defined location in SDRAM
*/
- header = map_sysmem(spl_nor_get_uboot_base(), sizeof(*header));
-#ifdef CONFIG_SPL_LOAD_FIT
- if (image_get_magic(header) == FDT_MAGIC) {
- debug("Found FIT format U-Boot\n");
- load.bl_len = 1;
- load.read = spl_nor_load_read;
- return spl_load_simple_fit(spl_image, &load,
- spl_nor_get_uboot_base(),
- (void *)header);
- }
-#endif
- if (IS_ENABLED(CONFIG_SPL_LOAD_IMX_CONTAINER) &&
- valid_container_hdr((void *)header)) {
- load.bl_len = 1;
- load.read = spl_nor_load_read;
- return spl_load_imx_container(spl_image, &load,
- spl_nor_get_uboot_base());
- }
-
- /* Legacy image handling */
- if (IS_ENABLED(CONFIG_SPL_LEGACY_IMAGE_FORMAT)) {
- load.bl_len = 1;
- load.read = spl_nor_load_read;
- return spl_load_legacy_img(spl_image, bootdev, &load,
- spl_nor_get_uboot_base(),
- header);
- }
-
- return -EINVAL;
+ spl_set_bl_len(&load, 1);
+ load.read = spl_nor_load_read;
+ return spl_load(spl_image, bootdev, &load, 0, spl_nor_get_uboot_base());
}
SPL_LOAD_IMAGE_METHOD("NOR", 0, BOOT_DEVICE_NOR, spl_nor_load_image);
diff --git a/common/spl/spl_ram.c b/common/spl/spl_ram.c
index 4158ed1..8aeda23 100644
--- a/common/spl/spl_ram.c
+++ b/common/spl/spl_ram.c
@@ -70,7 +70,7 @@
struct spl_load_info load;
debug("Found FIT\n");
- load.bl_len = 1;
+ spl_set_bl_len(&load, 1);
load.read = spl_ram_load_read;
ret = spl_load_simple_fit(spl_image, &load, 0, header);
} else {
diff --git a/common/spl/spl_semihosting.c b/common/spl/spl_semihosting.c
index f7dd289..941fa91 100644
--- a/common/spl/spl_semihosting.c
+++ b/common/spl/spl_semihosting.c
@@ -8,34 +8,19 @@
#include <log.h>
#include <semihosting.h>
#include <spl.h>
-
-static int smh_read_full(long fd, void *memp, size_t len)
-{
- long read;
-
- read = smh_read(fd, memp, len);
- if (read < 0)
- return read;
- if (read != len)
- return -EIO;
- return 0;
-}
+#include <spl_load.h>
static ulong smh_fit_read(struct spl_load_info *load, ulong file_offset,
ulong size, void *buf)
{
- long fd;
+ long fd = *(long *)load->priv;
ulong ret;
- fd = smh_open(load->filename, MODE_READ | MODE_BINARY);
- if (fd < 0) {
- log_debug("could not open %s: %ld\n", load->filename, fd);
+ if (smh_seek(fd, file_offset))
return 0;
- }
- ret = smh_read(fd, buf, size);
- smh_close(fd);
- return ret;
+ ret = smh_read(fd, buf, size);
+ return ret < 0 ? 0 : ret;
}
static int spl_smh_load_image(struct spl_image_info *spl_image,
@@ -44,8 +29,7 @@
const char *filename = CONFIG_SPL_FS_LOAD_PAYLOAD_NAME;
int ret;
long fd, len;
- struct legacy_img_hdr *header =
- spl_get_load_buffer(-sizeof(*header), sizeof(*header));
+ struct spl_load_info load;
fd = smh_open(filename, MODE_READ | MODE_BINARY);
if (fd < 0) {
@@ -60,39 +44,10 @@
}
len = ret;
- ret = smh_read_full(fd, header, sizeof(struct legacy_img_hdr));
- if (ret) {
- log_debug("could not read image header: %d\n", ret);
- goto out;
- }
-
- if (IS_ENABLED(CONFIG_SPL_LOAD_FIT) &&
- image_get_magic(header) == FDT_MAGIC) {
- struct spl_load_info load;
-
- debug("Found FIT\n");
- load.read = smh_fit_read;
- load.bl_len = 1;
- load.filename = filename;
- load.priv = NULL;
- smh_close(fd);
-
- return spl_load_simple_fit(spl_image, &load, 0, header);
- }
-
- ret = spl_parse_image_header(spl_image, bootdev, header);
- if (ret) {
- log_debug("failed to parse image header: %d\n", ret);
- goto out;
- }
-
- ret = smh_seek(fd, 0);
- if (ret) {
- log_debug("could not seek to start of image: %d\n", ret);
- goto out;
- }
-
- ret = smh_read_full(fd, (void *)spl_image->load_addr, len);
+ load.read = smh_fit_read;
+ spl_set_bl_len(&load, 1);
+ load.priv = &fd;
+ ret = spl_load(spl_image, bootdev, &load, len, 0);
if (ret)
log_debug("could not read %s: %d\n", filename, ret);
out:
diff --git a/common/spl/spl_spi.c b/common/spl/spl_spi.c
index 3ac4b1b..89de73c 100644
--- a/common/spl/spl_spi.c
+++ b/common/spl/spl_spi.c
@@ -12,54 +12,19 @@
#include <image.h>
#include <imx_container.h>
#include <log.h>
-#include <mapmem.h>
#include <spi.h>
#include <spi_flash.h>
#include <errno.h>
#include <spl.h>
+#include <spl_load.h>
#include <asm/global_data.h>
#include <asm/io.h>
#include <dm/ofnode.h>
-#if CONFIG_IS_ENABLED(OS_BOOT)
-/*
- * Load the kernel, check for a valid header we can parse, and if found load
- * the kernel and then device tree.
- */
-static int spi_load_image_os(struct spl_image_info *spl_image,
- struct spl_boot_device *bootdev,
- struct spi_flash *flash,
- struct legacy_img_hdr *header)
-{
- int err;
-
- /* Read for a header, parse or error out. */
- spi_flash_read(flash, CFG_SYS_SPI_KERNEL_OFFS, sizeof(*header),
- (void *)header);
-
- if (image_get_magic(header) != IH_MAGIC)
- return -1;
-
- err = spl_parse_image_header(spl_image, bootdev, header);
- if (err)
- return err;
-
- spi_flash_read(flash, CFG_SYS_SPI_KERNEL_OFFS,
- spl_image->size, (void *)spl_image->load_addr);
-
- /* Read device tree. */
- spi_flash_read(flash, CFG_SYS_SPI_ARGS_OFFS,
- CFG_SYS_SPI_ARGS_SIZE,
- (void *)CONFIG_SPL_PAYLOAD_ARGS_ADDR);
-
- return 0;
-}
-#endif
-
static ulong spl_spi_fit_read(struct spl_load_info *load, ulong sector,
ulong count, void *buf)
{
- struct spi_flash *flash = load->dev;
+ struct spi_flash *flash = load->priv;
ulong ret;
ret = spi_flash_read(flash, sector, count, buf);
@@ -95,9 +60,9 @@
int err = 0;
unsigned int payload_offs;
struct spi_flash *flash;
- struct legacy_img_hdr *header;
unsigned int sf_bus = spl_spi_boot_bus();
unsigned int sf_cs = spl_spi_boot_cs();
+ struct spl_load_info load;
/*
* Load U-Boot image from SPI flash into RAM
@@ -112,81 +77,32 @@
return -ENODEV;
}
- payload_offs = spl_spi_get_uboot_offs(flash);
+ load.priv = flash;
+ spl_set_bl_len(&load, 1);
+ load.read = spl_spi_fit_read;
- header = spl_get_load_buffer(-sizeof(*header), sizeof(*header));
+#if CONFIG_IS_ENABLED(OS_BOOT)
+ if (spl_start_uboot()) {
+ int err = spl_load(spl_image, bootdev, &load, 0,
+ CFG_SYS_SPI_KERNEL_OFFS);
- if (CONFIG_IS_ENABLED(OF_REAL)) {
- payload_offs = ofnode_conf_read_int("u-boot,spl-payload-offset",
- payload_offs);
+ if (!err)
+ /* Read device tree. */
+ return spi_flash_read(flash, CFG_SYS_SPI_ARGS_OFFS,
+ CFG_SYS_SPI_ARGS_SIZE,
+ (void *)CONFIG_SPL_PAYLOAD_ARGS_ADDR);
}
-
-#if CONFIG_IS_ENABLED(OS_BOOT)
- if (spl_start_uboot() || spi_load_image_os(spl_image, bootdev, flash, header))
#endif
- {
- /* Load u-boot, mkimage header is 64 bytes. */
- err = spi_flash_read(flash, payload_offs, sizeof(*header),
- (void *)header);
- if (err) {
- debug("%s: Failed to read from SPI flash (err=%d)\n",
- __func__, err);
- return err;
- }
-
- if (IS_ENABLED(CONFIG_SPL_LOAD_FIT_FULL) &&
- image_get_magic(header) == FDT_MAGIC) {
- u32 size = roundup(fdt_totalsize(header), 4);
- err = spi_flash_read(flash, payload_offs,
- size,
- map_sysmem(CONFIG_SYS_LOAD_ADDR,
- size));
- if (err)
- return err;
- err = spl_parse_image_header(spl_image, bootdev,
- phys_to_virt(CONFIG_SYS_LOAD_ADDR));
- } else if (IS_ENABLED(CONFIG_SPL_LOAD_FIT) &&
- image_get_magic(header) == FDT_MAGIC) {
- struct spl_load_info load;
-
- debug("Found FIT\n");
- load.dev = flash;
- load.priv = NULL;
- load.filename = NULL;
- load.bl_len = 1;
- load.read = spl_spi_fit_read;
- err = spl_load_simple_fit(spl_image, &load,
- payload_offs,
- header);
- } else if (IS_ENABLED(CONFIG_SPL_LOAD_IMX_CONTAINER) &&
- valid_container_hdr((void *)header)) {
- struct spl_load_info load;
-
- load.dev = flash;
- load.priv = NULL;
- load.filename = NULL;
- load.bl_len = 1;
- load.read = spl_spi_fit_read;
-
- err = spl_load_imx_container(spl_image, &load,
- payload_offs);
- } else {
- err = spl_parse_image_header(spl_image, bootdev, header);
- if (err)
- return err;
- err = spi_flash_read(flash, payload_offs + spl_image->offset,
- spl_image->size,
- map_sysmem(spl_image->load_addr,
- spl_image->size));
- }
- if (IS_ENABLED(CONFIG_SPI_FLASH_SOFT_RESET)) {
- err = spi_nor_remove(flash);
- if (err)
- return err;
- }
+ payload_offs = spl_spi_get_uboot_offs(flash);
+ if (CONFIG_IS_ENABLED(OF_REAL)) {
+ payload_offs = ofnode_conf_read_int("u-boot,spl-payload-offset",
+ payload_offs);
}
+ err = spl_load(spl_image, bootdev, &load, 0, payload_offs);
+ if (IS_ENABLED(CONFIG_SPI_FLASH_SOFT_RESET))
+ err = spi_nor_remove(flash);
return err;
}
/* Use priorty 1 so that boards can override this */
diff --git a/common/spl/spl_ymodem.c b/common/spl/spl_ymodem.c
index 038b443..1faaa2c 100644
--- a/common/spl/spl_ymodem.c
+++ b/common/spl/spl_ymodem.c
@@ -134,10 +134,8 @@
struct ymodem_fit_info info;
debug("Found FIT\n");
- load.dev = NULL;
load.priv = (void *)&info;
- load.filename = NULL;
- load.bl_len = 1;
+ spl_set_bl_len(&load, 1);
info.buf = buf;
info.image_read = BUF_SIZE;
load.read = ymodem_read_fit;
diff --git a/common/stackprot.c b/common/stackprot.c
index d5b7061..6495951 100644
--- a/common/stackprot.c
+++ b/common/stackprot.c
@@ -18,3 +18,8 @@
panic("Stack smashing detected in function:\n%p relocated from %p",
ra, ra - gd->reloc_off);
}
+
+void __stack_chk_fail_local(void)
+{
+ __stack_chk_fail();
+}
diff --git a/common/usb_hub.c b/common/usb_hub.c
index 85c0822..70279f3 100644
--- a/common/usb_hub.c
+++ b/common/usb_hub.c
@@ -395,6 +395,13 @@
break;
}
+ /*
+ * USB 2.0 7.1.7.5: devices must be able to accept a SetAddress()
+ * request (refer to Section 11.24.2 and Section 9.4 respectively)
+ * after the reset recovery time 10 ms
+ */
+ mdelay(10);
+
#if CONFIG_IS_ENABLED(DM_USB)
struct udevice *child;
diff --git a/common/usb_storage.c b/common/usb_storage.c
index 35c656d..774d5bd 100644
--- a/common/usb_storage.c
+++ b/common/usb_storage.c
@@ -102,6 +102,7 @@
trans_reset transport_reset; /* reset routine */
trans_cmnd transport; /* transport routine */
unsigned short max_xfer_blk; /* maximum transfer blocks */
+ bool cmd12; /* use 12-byte commands (RBC/UFI) */
};
#if !CONFIG_IS_ENABLED(BLK)
@@ -359,7 +360,7 @@
{
int i;
printf("SRB: len %d datalen 0x%lX\n ", pccb->cmdlen, pccb->datalen);
- for (i = 0; i < 12; i++)
+ for (i = 0; i < pccb->cmdlen; i++)
printf("%02X ", pccb->cmd[i]);
printf("\n");
}
@@ -898,7 +899,7 @@
psrb->cmd[4] = 18;
psrb->datalen = 18;
psrb->pdata = &srb->sense_buf[0];
- psrb->cmdlen = 12;
+ psrb->cmdlen = us->cmd12 ? 12 : 6;
/* issue the command */
result = usb_stor_CB_comdat(psrb, us);
debug("auto request returned %d\n", result);
@@ -999,7 +1000,7 @@
srb->cmd[1] = srb->lun << 5;
srb->cmd[4] = 36;
srb->datalen = 36;
- srb->cmdlen = 12;
+ srb->cmdlen = ss->cmd12 ? 12 : 6;
i = ss->transport(srb, ss);
debug("inquiry returns %d\n", i);
if (i == 0)
@@ -1024,7 +1025,7 @@
srb->cmd[4] = 18;
srb->datalen = 18;
srb->pdata = &srb->sense_buf[0];
- srb->cmdlen = 12;
+ srb->cmdlen = ss->cmd12 ? 12 : 6;
ss->transport(srb, ss);
debug("Request Sense returned %02X %02X %02X\n",
srb->sense_buf[2], srb->sense_buf[12],
@@ -1042,7 +1043,7 @@
srb->cmd[0] = SCSI_TST_U_RDY;
srb->cmd[1] = srb->lun << 5;
srb->datalen = 0;
- srb->cmdlen = 12;
+ srb->cmdlen = ss->cmd12 ? 12 : 6;
if (ss->transport(srb, ss) == USB_STOR_TRANSPORT_GOOD) {
ss->flags |= USB_READY;
return 0;
@@ -1074,7 +1075,7 @@
srb->cmd[0] = SCSI_RD_CAPAC;
srb->cmd[1] = srb->lun << 5;
srb->datalen = 8;
- srb->cmdlen = 12;
+ srb->cmdlen = ss->cmd12 ? 12 : 10;
if (ss->transport(srb, ss) == USB_STOR_TRANSPORT_GOOD)
return 0;
} while (retry--);
@@ -1094,7 +1095,7 @@
srb->cmd[5] = ((unsigned char) (start)) & 0xff;
srb->cmd[7] = ((unsigned char) (blocks >> 8)) & 0xff;
srb->cmd[8] = (unsigned char) blocks & 0xff;
- srb->cmdlen = 12;
+ srb->cmdlen = ss->cmd12 ? 12 : 10;
debug("read10: start %lx blocks %x\n", start, blocks);
return ss->transport(srb, ss);
}
@@ -1111,7 +1112,7 @@
srb->cmd[5] = ((unsigned char) (start)) & 0xff;
srb->cmd[7] = ((unsigned char) (blocks >> 8)) & 0xff;
srb->cmd[8] = (unsigned char) blocks & 0xff;
- srb->cmdlen = 12;
+ srb->cmdlen = ss->cmd12 ? 12 : 10;
debug("write10: start %lx blocks %x\n", start, blocks);
return ss->transport(srb, ss);
}
@@ -1417,6 +1418,11 @@
printf("Sorry, protocol %d not yet supported.\n", ss->subclass);
return 0;
}
+
+ /* UFI uses 12-byte commands (like RBC, unlike SCSI) */
+ if (ss->subclass == US_SC_UFI)
+ ss->cmd12 = true;
+
if (ss->ep_int) {
/* we had found an interrupt endpoint, prepare irq pipe
* set up the IRQ pipe and handler
diff --git a/configs/a3y17lte_defconfig b/configs/a3y17lte_defconfig
index 42fcd2a..043f3a0 100644
--- a/configs/a3y17lte_defconfig
+++ b/configs/a3y17lte_defconfig
@@ -1,5 +1,4 @@
CONFIG_ARM=y
-CONFIG_SYS_CONFIG_NAME="exynos78x0-common"
CONFIG_SKIP_LOWLEVEL_INIT=y
CONFIG_COUNTER_FREQUENCY=26000000
CONFIG_ARCH_EXYNOS=y
diff --git a/configs/a5y17lte_defconfig b/configs/a5y17lte_defconfig
index 3b80536..14590f6 100644
--- a/configs/a5y17lte_defconfig
+++ b/configs/a5y17lte_defconfig
@@ -1,5 +1,4 @@
CONFIG_ARM=y
-CONFIG_SYS_CONFIG_NAME="exynos78x0-common"
CONFIG_SKIP_LOWLEVEL_INIT=y
CONFIG_COUNTER_FREQUENCY=26000000
CONFIG_ARCH_EXYNOS=y
diff --git a/configs/a7y17lte_defconfig b/configs/a7y17lte_defconfig
index 9390e35..ccb0bf2 100644
--- a/configs/a7y17lte_defconfig
+++ b/configs/a7y17lte_defconfig
@@ -1,5 +1,4 @@
CONFIG_ARM=y
-CONFIG_SYS_CONFIG_NAME="exynos78x0-common"
CONFIG_SKIP_LOWLEVEL_INIT=y
CONFIG_COUNTER_FREQUENCY=26000000
CONFIG_ARCH_EXYNOS=y
diff --git a/configs/am335x_baltos_defconfig b/configs/am335x_baltos_defconfig
index 16993ef..0599ae2 100644
--- a/configs/am335x_baltos_defconfig
+++ b/configs/am335x_baltos_defconfig
@@ -22,7 +22,7 @@
CONFIG_SPL_SYS_MALLOC_SIZE=0x800000
CONFIG_SPL_FS_EXT4=y
CONFIG_SPL_I2C=y
-CONFIG_SPL_MTD_SUPPORT=y
+CONFIG_SPL_MTD=y
CONFIG_SPL_NAND_DRIVERS=y
CONFIG_SPL_NAND_ECC=y
CONFIG_SPL_NAND_BASE=y
@@ -67,7 +67,6 @@
CONFIG_MTD_RAW_NAND=y
CONFIG_SYS_NAND_BLOCK_SIZE=0x20000
CONFIG_SYS_NAND_ONFI_DETECTION=y
-CONFIG_SYS_NAND_PAGE_COUNT=0x40
CONFIG_SYS_NAND_PAGE_SIZE=0x800
CONFIG_SYS_NAND_OOBSIZE=0x40
CONFIG_SYS_NAND_U_BOOT_LOCATIONS=y
diff --git a/configs/am335x_evm_defconfig b/configs/am335x_evm_defconfig
index f048e60..5d38dad 100644
--- a/configs/am335x_evm_defconfig
+++ b/configs/am335x_evm_defconfig
@@ -26,7 +26,7 @@
CONFIG_SPL_ETH=y
# CONFIG_SPL_FS_EXT4 is not set
CONFIG_SPL_FS_LOAD_PAYLOAD_NAME="u-boot.img"
-CONFIG_SPL_MTD_SUPPORT=y
+CONFIG_SPL_MTD=y
CONFIG_SPL_MUSB_NEW=y
CONFIG_SPL_NAND_DRIVERS=y
CONFIG_SPL_NAND_ECC=y
@@ -84,7 +84,6 @@
CONFIG_MTD_RAW_NAND=y
CONFIG_SYS_NAND_BLOCK_SIZE=0x20000
CONFIG_SYS_NAND_ONFI_DETECTION=y
-CONFIG_SYS_NAND_PAGE_COUNT=0x40
CONFIG_SYS_NAND_PAGE_SIZE=0x800
CONFIG_SYS_NAND_OOBSIZE=0x40
CONFIG_SYS_NAND_U_BOOT_LOCATIONS=y
diff --git a/configs/am335x_evm_spiboot_defconfig b/configs/am335x_evm_spiboot_defconfig
index 9866246..fff5265 100644
--- a/configs/am335x_evm_spiboot_defconfig
+++ b/configs/am335x_evm_spiboot_defconfig
@@ -13,6 +13,7 @@
# CONFIG_OF_LIBFDT_OVERLAY is not set
# CONFIG_SPL_MMC is not set
CONFIG_SPL=y
+# CONFIG_SPL_FS_FAT is not set
CONFIG_SPL_SPI_FLASH_SUPPORT=y
CONFIG_SPL_SPI=y
CONFIG_TIMESTAMP=y
@@ -27,8 +28,7 @@
CONFIG_SPL_SYS_MALLOC_SIZE=0x800000
CONFIG_SPL_FIT_IMAGE_TINY=y
# CONFIG_SPL_FS_EXT4 is not set
-CONFIG_SPL_FS_LOAD_PAYLOAD_NAME="u-boot.img"
-CONFIG_SPL_MTD_SUPPORT=y
+CONFIG_SPL_MTD=y
# CONFIG_SPL_NAND_SUPPORT is not set
CONFIG_SPL_DM_SPI_FLASH=y
CONFIG_SPL_SPI_LOAD=y
diff --git a/configs/am335x_guardian_defconfig b/configs/am335x_guardian_defconfig
index 01d848c..5369e46 100644
--- a/configs/am335x_guardian_defconfig
+++ b/configs/am335x_guardian_defconfig
@@ -99,7 +99,6 @@
CONFIG_NAND_OMAP_ECCSCHEME_BCH16_CODE_HW=y
CONFIG_SYS_NAND_BLOCK_SIZE=0x40000
CONFIG_SYS_NAND_ONFI_DETECTION=y
-CONFIG_SYS_NAND_PAGE_COUNT=0x40
CONFIG_SYS_NAND_PAGE_SIZE=0x1000
CONFIG_SYS_NAND_OOBSIZE=0x100
CONFIG_SYS_NAND_U_BOOT_LOCATIONS=y
diff --git a/configs/am335x_hs_evm_defconfig b/configs/am335x_hs_evm_defconfig
index b961b6c..ea46e58 100644
--- a/configs/am335x_hs_evm_defconfig
+++ b/configs/am335x_hs_evm_defconfig
@@ -27,7 +27,7 @@
# CONFIG_SPL_ENV_SUPPORT is not set
# CONFIG_SPL_FS_EXT4 is not set
CONFIG_SPL_FS_LOAD_PAYLOAD_NAME="u-boot.img"
-CONFIG_SPL_MTD_SUPPORT=y
+CONFIG_SPL_MTD=y
# CONFIG_SPL_NAND_SUPPORT is not set
CONFIG_SPL_NAND_DRIVERS=y
CONFIG_SPL_NAND_ECC=y
diff --git a/configs/am335x_hs_evm_uart_defconfig b/configs/am335x_hs_evm_uart_defconfig
index b5d8eac..7886557 100644
--- a/configs/am335x_hs_evm_uart_defconfig
+++ b/configs/am335x_hs_evm_uart_defconfig
@@ -29,7 +29,7 @@
CONFIG_SPL_FIT_IMAGE_TINY=y
# CONFIG_SPL_ENV_SUPPORT is not set
# CONFIG_SPL_FS_EXT4 is not set
-CONFIG_SPL_MTD_SUPPORT=y
+CONFIG_SPL_MTD=y
# CONFIG_SPL_NAND_SUPPORT is not set
CONFIG_SPL_NAND_DRIVERS=y
CONFIG_SPL_NAND_ECC=y
diff --git a/configs/am335x_igep003x_defconfig b/configs/am335x_igep003x_defconfig
index 4dd6366..e2c5b70 100644
--- a/configs/am335x_igep003x_defconfig
+++ b/configs/am335x_igep003x_defconfig
@@ -24,7 +24,7 @@
CONFIG_SPL_SYS_MALLOC_SIZE=0x800000
CONFIG_SPL_FS_EXT4=y
CONFIG_SPL_I2C=y
-CONFIG_SPL_MTD_SUPPORT=y
+CONFIG_SPL_MTD=y
CONFIG_SPL_NAND_DRIVERS=y
CONFIG_SPL_NAND_ECC=y
CONFIG_SPL_NAND_BASE=y
@@ -85,7 +85,6 @@
CONFIG_MTD_RAW_NAND=y
CONFIG_SYS_NAND_BLOCK_SIZE=0x20000
CONFIG_SYS_NAND_ONFI_DETECTION=y
-CONFIG_SYS_NAND_PAGE_COUNT=0x40
CONFIG_SYS_NAND_PAGE_SIZE=0x800
CONFIG_SYS_NAND_OOBSIZE=0x40
CONFIG_MTD_UBI_FASTMAP=y
diff --git a/configs/am335x_sl50_defconfig b/configs/am335x_sl50_defconfig
index 9ba376f..fb61dd7 100644
--- a/configs/am335x_sl50_defconfig
+++ b/configs/am335x_sl50_defconfig
@@ -28,7 +28,7 @@
CONFIG_SPL_ENV_SUPPORT=y
CONFIG_SPL_FS_EXT4=y
CONFIG_SPL_I2C=y
-CONFIG_SPL_MTD_SUPPORT=y
+CONFIG_SPL_MTD=y
# CONFIG_SPL_NAND_SUPPORT is not set
CONFIG_SPL_NAND_DRIVERS=y
CONFIG_SPL_NAND_ECC=y
diff --git a/configs/am3517_evm_defconfig b/configs/am3517_evm_defconfig
index 0a83ac9..a96936c 100644
--- a/configs/am3517_evm_defconfig
+++ b/configs/am3517_evm_defconfig
@@ -26,7 +26,7 @@
# CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR is not set
# CONFIG_SPL_FS_EXT4 is not set
# CONFIG_SPL_I2C is not set
-CONFIG_SPL_MTD_SUPPORT=y
+CONFIG_SPL_MTD=y
CONFIG_SPL_NAND_DRIVERS=y
CONFIG_SPL_NAND_ECC=y
CONFIG_SPL_NAND_SIMPLE=y
@@ -75,7 +75,6 @@
CONFIG_MTD_RAW_NAND=y
CONFIG_NAND_OMAP_ECCSCHEME_BCH8_CODE_HW_DETECTION_SW=y
CONFIG_SYS_NAND_BLOCK_SIZE=0x20000
-CONFIG_SYS_NAND_PAGE_COUNT=0x40
CONFIG_SYS_NAND_PAGE_SIZE=0x800
CONFIG_SYS_NAND_OOBSIZE=0x40
CONFIG_SYS_NAND_BUSWIDTH_16BIT=y
diff --git a/configs/am43xx_evm_defconfig b/configs/am43xx_evm_defconfig
index 6571afd..d5ce299 100644
--- a/configs/am43xx_evm_defconfig
+++ b/configs/am43xx_evm_defconfig
@@ -22,7 +22,7 @@
CONFIG_SPL_SYS_MALLOC_SIZE=0x800000
CONFIG_SPL_ETH=y
CONFIG_SPL_FS_LOAD_PAYLOAD_NAME="u-boot.img"
-CONFIG_SPL_MTD_SUPPORT=y
+CONFIG_SPL_MTD=y
CONFIG_SPL_NAND_DRIVERS=y
CONFIG_SPL_NAND_ECC=y
CONFIG_SPL_NAND_BASE=y
@@ -72,7 +72,6 @@
CONFIG_NAND_OMAP_ECCSCHEME_BCH16_CODE_HW=y
CONFIG_SYS_NAND_BLOCK_SIZE=0x40000
CONFIG_SYS_NAND_ONFI_DETECTION=y
-CONFIG_SYS_NAND_PAGE_COUNT=0x40
CONFIG_SYS_NAND_PAGE_SIZE=0x1000
CONFIG_SYS_NAND_OOBSIZE=0xe0
CONFIG_SYS_NAND_U_BOOT_LOCATIONS=y
diff --git a/configs/am43xx_evm_rtconly_defconfig b/configs/am43xx_evm_rtconly_defconfig
index e84aed4..a0a9e8a 100644
--- a/configs/am43xx_evm_rtconly_defconfig
+++ b/configs/am43xx_evm_rtconly_defconfig
@@ -21,7 +21,7 @@
CONFIG_SPL_SYS_MALLOC=y
CONFIG_SPL_SYS_MALLOC_SIZE=0x800000
CONFIG_SPL_FS_LOAD_PAYLOAD_NAME="u-boot.img"
-CONFIG_SPL_MTD_SUPPORT=y
+CONFIG_SPL_MTD=y
CONFIG_SPL_NAND_DRIVERS=y
CONFIG_SPL_NAND_ECC=y
CONFIG_SPL_NAND_BASE=y
@@ -62,7 +62,6 @@
CONFIG_NAND_OMAP_ECCSCHEME_BCH16_CODE_HW=y
CONFIG_SYS_NAND_BLOCK_SIZE=0x40000
CONFIG_SYS_NAND_ONFI_DETECTION=y
-CONFIG_SYS_NAND_PAGE_COUNT=0x40
CONFIG_SYS_NAND_PAGE_SIZE=0x1000
CONFIG_SYS_NAND_OOBSIZE=0xe0
CONFIG_SYS_NAND_U_BOOT_LOCATIONS=y
diff --git a/configs/am43xx_evm_usbhost_boot_defconfig b/configs/am43xx_evm_usbhost_boot_defconfig
index 0cae324..cd47806 100644
--- a/configs/am43xx_evm_usbhost_boot_defconfig
+++ b/configs/am43xx_evm_usbhost_boot_defconfig
@@ -20,7 +20,7 @@
CONFIG_SPL_SYS_MALLOC=y
CONFIG_SPL_SYS_MALLOC_SIZE=0x800000
CONFIG_SPL_FS_LOAD_PAYLOAD_NAME="u-boot.img"
-CONFIG_SPL_MTD_SUPPORT=y
+CONFIG_SPL_MTD=y
CONFIG_SPL_NAND_DRIVERS=y
CONFIG_SPL_NAND_ECC=y
CONFIG_SPL_NAND_BASE=y
@@ -75,7 +75,6 @@
CONFIG_NAND_OMAP_ECCSCHEME_BCH16_CODE_HW=y
CONFIG_SYS_NAND_BLOCK_SIZE=0x40000
CONFIG_SYS_NAND_ONFI_DETECTION=y
-CONFIG_SYS_NAND_PAGE_COUNT=0x40
CONFIG_SYS_NAND_PAGE_SIZE=0x1000
CONFIG_SYS_NAND_OOBSIZE=0xe0
CONFIG_SYS_NAND_U_BOOT_LOCATIONS=y
diff --git a/configs/am43xx_hs_evm_defconfig b/configs/am43xx_hs_evm_defconfig
index 370ee96..d721664 100644
--- a/configs/am43xx_hs_evm_defconfig
+++ b/configs/am43xx_hs_evm_defconfig
@@ -28,7 +28,7 @@
CONFIG_SPL_SYS_MALLOC_SIZE=0x800000
CONFIG_SPL_ETH=y
CONFIG_SPL_FS_LOAD_PAYLOAD_NAME="u-boot.img"
-CONFIG_SPL_MTD_SUPPORT=y
+CONFIG_SPL_MTD=y
CONFIG_SPL_NAND_DRIVERS=y
CONFIG_SPL_NAND_ECC=y
CONFIG_SPL_NAND_BASE=y
@@ -68,7 +68,6 @@
CONFIG_NAND_OMAP_ECCSCHEME_BCH16_CODE_HW=y
CONFIG_SYS_NAND_BLOCK_SIZE=0x40000
CONFIG_SYS_NAND_ONFI_DETECTION=y
-CONFIG_SYS_NAND_PAGE_COUNT=0x40
CONFIG_SYS_NAND_PAGE_SIZE=0x1000
CONFIG_SYS_NAND_OOBSIZE=0xe0
CONFIG_SYS_NAND_U_BOOT_LOCATIONS=y
diff --git a/configs/am62ax_evm_a53_defconfig b/configs/am62ax_evm_a53_defconfig
index d0a34c7..3808358 100644
--- a/configs/am62ax_evm_a53_defconfig
+++ b/configs/am62ax_evm_a53_defconfig
@@ -21,8 +21,9 @@
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
CONFIG_SPL_LOAD_FIT=y
CONFIG_SPL_LOAD_FIT_ADDRESS=0x81000000
-CONFIG_DISTRO_DEFAULTS=y
-CONFIG_BOOTCOMMAND="run envboot; run distro_bootcmd;"
+CONFIG_BOOTSTD_FULL=y
+CONFIG_BOOTSTD_DEFAULTS=y
+CONFIG_BOOTCOMMAND="run envboot; bootflow scan -lb"
CONFIG_SPL_MAX_SIZE=0x58000
CONFIG_SPL_PAD_TO=0x0
CONFIG_SPL_HAS_BSS_LINKER_SECTION=y
@@ -42,7 +43,6 @@
CONFIG_MULTI_DTB_FIT=y
CONFIG_SPL_MULTI_DTB_FIT=y
CONFIG_SPL_MULTI_DTB_FIT_NO_COMPRESSION=y
-# CONFIG_NET is not set
CONFIG_SPL_DM=y
CONFIG_SPL_DM_SEQ_ALIAS=y
CONFIG_REGMAP=y
@@ -51,6 +51,8 @@
CONFIG_CLK=y
CONFIG_SPL_CLK=y
CONFIG_CLK_TI_SCI=y
+CONFIG_DMA_CHANNELS=y
+CONFIG_TI_K3_NAVSS_UDMA=y
CONFIG_TI_SCI_PROTOCOL=y
# CONFIG_GPIO is not set
# CONFIG_I2C is not set
@@ -60,6 +62,10 @@
CONFIG_MMC_SDHCI_ADMA=y
CONFIG_SPL_MMC_SDHCI_ADMA=y
CONFIG_MMC_SDHCI_AM654=y
+CONFIG_PHY_TI_DP83867=y
+CONFIG_PHY_FIXED=y
+CONFIG_TI_AM65_CPSW_NUSS=y
+CONFIG_PHY=y
CONFIG_PINCTRL=y
CONFIG_SPL_PINCTRL=y
CONFIG_PINCTRL_SINGLE=y
diff --git a/configs/am62ax_evm_r5_defconfig b/configs/am62ax_evm_r5_defconfig
index d52de8b..4070415 100644
--- a/configs/am62ax_evm_r5_defconfig
+++ b/configs/am62ax_evm_r5_defconfig
@@ -43,7 +43,7 @@
CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x400
CONFIG_SPL_DMA=y
CONFIG_SPL_DM_MAILBOX=y
-CONFIG_SPL_MTD_SUPPORT=y
+CONFIG_SPL_MTD=y
CONFIG_SPL_DM_SPI_FLASH=y
CONFIG_SPL_DM_RESET=y
CONFIG_SPL_POWER_DOMAIN=y
diff --git a/configs/am62x_beagleplay_a53_defconfig b/configs/am62x_beagleplay_a53_defconfig
new file mode 100644
index 0000000..03ca3ac
--- /dev/null
+++ b/configs/am62x_beagleplay_a53_defconfig
@@ -0,0 +1,118 @@
+CONFIG_ARM=y
+CONFIG_ARCH_K3=y
+CONFIG_SYS_MALLOC_F_LEN=0x8000
+CONFIG_SPL_GPIO=y
+CONFIG_SPL_LIBCOMMON_SUPPORT=y
+CONFIG_SPL_LIBGENERIC_SUPPORT=y
+CONFIG_NR_DRAM_BANKS=2
+CONFIG_SOC_K3_AM625=y
+CONFIG_K3_ATF_LOAD_ADDR=0x9e780000
+CONFIG_TARGET_AM625_A53_BEAGLEPLAY=y
+CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y
+CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x80b80000
+CONFIG_DM_GPIO=y
+CONFIG_DEFAULT_DEVICE_TREE="k3-am625-beagleplay"
+CONFIG_SPL_TEXT_BASE=0x80080000
+CONFIG_OF_LIBFDT_OVERLAY=y
+CONFIG_DM_RESET=y
+CONFIG_SPL_MMC=y
+CONFIG_SPL_SERIAL=y
+CONFIG_SPL_STACK_R_ADDR=0x82000000
+CONFIG_SPL_SIZE_LIMIT=0x40000
+CONFIG_SPL_SIZE_LIMIT_PROVIDE_STACK=0x800
+CONFIG_SPL_FS_FAT=y
+CONFIG_SPL_LIBDISK_SUPPORT=y
+# CONFIG_PSCI_RESET is not set
+# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
+CONFIG_SPL_LOAD_FIT=y
+CONFIG_SPL_LOAD_FIT_ADDRESS=0x81000000
+CONFIG_BOOTSTD_FULL=y
+CONFIG_BOOTSTD_DEFAULTS=y
+CONFIG_AUTOBOOT_KEYED=y
+CONFIG_AUTOBOOT_PROMPT="Press SPACE to abort autoboot in %d seconds\n"
+CONFIG_AUTOBOOT_DELAY_STR="d"
+CONFIG_AUTOBOOT_STOP_STR=" "
+CONFIG_BOOTCOMMAND="run set_led_state_start_load;run findfdt; run envboot; bootflow scan -lb;run set_led_state_fail_load"
+CONFIG_SPL_MAX_SIZE=0x58000
+CONFIG_SPL_HAS_BSS_LINKER_SECTION=y
+CONFIG_SPL_BSS_START_ADDR=0x80c80000
+CONFIG_SPL_BSS_MAX_SIZE=0x80000
+CONFIG_SPL_SYS_REPORT_STACK_F_USAGE=y
+CONFIG_SPL_SYS_MALLOC_SIMPLE=y
+CONFIG_SPL_STACK_R=y
+CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR=y
+CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x1400
+CONFIG_SPL_FS_LOAD_PAYLOAD_NAME="u-boot.img"
+CONFIG_SPL_I2C=y
+CONFIG_SPL_DM_MAILBOX=y
+CONFIG_SPL_POWER_DOMAIN=y
+CONFIG_SPL_YMODEM_SUPPORT=y
+CONFIG_SYS_BOOTM_LEN=0x800000
+CONFIG_CMD_GPIO=y
+CONFIG_CMD_GPIO_READ=y
+CONFIG_CMD_I2C=y
+CONFIG_CMD_MMC=y
+CONFIG_CMD_PMIC=y
+CONFIG_CMD_REGULATOR=y
+CONFIG_OF_CONTROL=y
+CONFIG_SPL_OF_CONTROL=y
+CONFIG_MULTI_DTB_FIT=y
+CONFIG_SPL_MULTI_DTB_FIT=y
+CONFIG_SPL_MULTI_DTB_FIT_NO_COMPRESSION=y
+CONFIG_NET_RANDOM_ETHADDR=y
+CONFIG_SPL_DM=y
+CONFIG_SPL_DM_SEQ_ALIAS=y
+CONFIG_REGMAP=y
+CONFIG_SPL_REGMAP=y
+CONFIG_SPL_OF_TRANSLATE=y
+CONFIG_CLK=y
+CONFIG_SPL_CLK=y
+CONFIG_CLK_TI_SCI=y
+CONFIG_DMA_CHANNELS=y
+CONFIG_TI_K3_NAVSS_UDMA=y
+CONFIG_TI_SCI_PROTOCOL=y
+CONFIG_DA8XX_GPIO=y
+CONFIG_DM_I2C=y
+CONFIG_SYS_I2C_OMAP24XX=y
+CONFIG_LED=y
+CONFIG_SPL_LED=y
+CONFIG_LED_GPIO=y
+CONFIG_SPL_LED_GPIO=y
+CONFIG_DM_MAILBOX=y
+CONFIG_K3_SEC_PROXY=y
+CONFIG_MMC_IO_VOLTAGE=y
+CONFIG_MMC_UHS_SUPPORT=y
+CONFIG_MMC_HS200_SUPPORT=y
+CONFIG_MMC_SDHCI=y
+CONFIG_MMC_SDHCI_ADMA=y
+CONFIG_SPL_MMC_SDHCI_ADMA=y
+CONFIG_MMC_SDHCI_AM654=y
+CONFIG_PHY_REALTEK=y
+CONFIG_PHY_TI=y
+CONFIG_PHY_FIXED=y
+CONFIG_TI_AM65_CPSW_NUSS=y
+CONFIG_PHY=y
+CONFIG_PINCTRL=y
+CONFIG_SPL_PINCTRL=y
+CONFIG_PINCTRL_SINGLE=y
+CONFIG_POWER_DOMAIN=y
+CONFIG_TI_SCI_POWER_DOMAIN=y
+CONFIG_DM_PMIC=y
+CONFIG_PMIC_TPS65219=y
+CONFIG_DM_REGULATOR=y
+CONFIG_DM_REGULATOR_FIXED=y
+CONFIG_DM_REGULATOR_GPIO=y
+CONFIG_DM_REGULATOR_TPS65219=y
+CONFIG_K3_SYSTEM_CONTROLLER=y
+CONFIG_REMOTEPROC_TI_K3_ARM64=y
+CONFIG_RESET_TI_SCI=y
+CONFIG_DM_SERIAL=y
+CONFIG_SOC_DEVICE=y
+CONFIG_SOC_DEVICE_TI_K3=y
+CONFIG_SOC_TI=y
+CONFIG_SYSRESET=y
+CONFIG_SPL_SYSRESET=y
+CONFIG_SYSRESET_TI_SCI=y
+CONFIG_EXT4_WRITE=y
+CONFIG_FS_FAT_MAX_CLUSTSIZE=16384
+CONFIG_LZO=y
diff --git a/configs/am62x_beagleplay_r5_defconfig b/configs/am62x_beagleplay_r5_defconfig
new file mode 100644
index 0000000..2f3264b
--- /dev/null
+++ b/configs/am62x_beagleplay_r5_defconfig
@@ -0,0 +1,110 @@
+CONFIG_ARM=y
+CONFIG_ARCH_K3=y
+CONFIG_SYS_MALLOC_LEN=0x08000000
+CONFIG_SYS_MALLOC_F_LEN=0x9000
+CONFIG_SPL_LIBCOMMON_SUPPORT=y
+CONFIG_SPL_LIBGENERIC_SUPPORT=y
+CONFIG_NR_DRAM_BANKS=2
+CONFIG_SOC_K3_AM625=y
+CONFIG_TARGET_AM625_R5_BEAGLEPLAY=y
+CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y
+CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x43c3a7f0
+CONFIG_ENV_SIZE=0x20000
+CONFIG_DM_GPIO=y
+CONFIG_SPL_DM_SPI=y
+CONFIG_DEFAULT_DEVICE_TREE="k3-am625-r5-beagleplay"
+CONFIG_SPL_TEXT_BASE=0x43c00000
+CONFIG_DM_RESET=y
+CONFIG_SPL_MMC=y
+CONFIG_SPL_SERIAL=y
+CONFIG_SPL_DRIVERS_MISC=y
+CONFIG_SPL_STACK_R_ADDR=0x82000000
+CONFIG_SPL_SYS_MALLOC_F_LEN=0x7000
+CONFIG_SPL_SIZE_LIMIT=0x3A7F0
+CONFIG_SPL_SIZE_LIMIT_PROVIDE_STACK=0x3500
+CONFIG_SPL_FS_FAT=y
+CONFIG_SPL_LIBDISK_SUPPORT=y
+CONFIG_SPL_SPI=y
+CONFIG_SPL_LOAD_FIT=y
+CONFIG_SPL_LOAD_FIT_ADDRESS=0x80080000
+# CONFIG_DISPLAY_CPUINFO is not set
+CONFIG_SPL_SIZE_LIMIT_SUBTRACT_GD=y
+CONFIG_SPL_SIZE_LIMIT_SUBTRACT_MALLOC=y
+CONFIG_SPL_MAX_SIZE=0x3B000
+CONFIG_SPL_PAD_TO=0x0
+CONFIG_SPL_HAS_BSS_LINKER_SECTION=y
+CONFIG_SPL_BSS_START_ADDR=0x43c3b000
+CONFIG_SPL_BSS_MAX_SIZE=0x3000
+CONFIG_SPL_SYS_REPORT_STACK_F_USAGE=y
+CONFIG_SPL_SYS_MALLOC_SIMPLE=y
+CONFIG_SPL_STACK_R=y
+CONFIG_SPL_SEPARATE_BSS=y
+CONFIG_SPL_SYS_MALLOC=y
+CONFIG_SPL_HAS_CUSTOM_MALLOC_START=y
+CONFIG_SPL_CUSTOM_SYS_MALLOC_ADDR=0x84000000
+CONFIG_SPL_SYS_MALLOC_SIZE=0x1000000
+CONFIG_SPL_EARLY_BSS=y
+CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR=y
+CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x400
+CONFIG_SPL_DM_MAILBOX=y
+CONFIG_SPL_DM_RESET=y
+CONFIG_SPL_POWER_DOMAIN=y
+CONFIG_SPL_RAM_SUPPORT=y
+CONFIG_SPL_RAM_DEVICE=y
+CONFIG_SPL_REMOTEPROC=y
+CONFIG_SPL_YMODEM_SUPPORT=y
+CONFIG_HUSH_PARSER=y
+CONFIG_CMD_ASKENV=y
+CONFIG_CMD_DFU=y
+CONFIG_CMD_GPT=y
+CONFIG_CMD_MMC=y
+CONFIG_CMD_REMOTEPROC=y
+# CONFIG_CMD_SETEXPR is not set
+CONFIG_CMD_TIME=y
+CONFIG_CMD_FAT=y
+CONFIG_OF_CONTROL=y
+CONFIG_SPL_OF_CONTROL=y
+CONFIG_SPL_MULTI_DTB_FIT=y
+CONFIG_SPL_MULTI_DTB_FIT_NO_COMPRESSION=y
+CONFIG_SYS_RELOC_GD_ENV_ADDR=y
+# CONFIG_NET is not set
+CONFIG_SPL_DM=y
+CONFIG_SPL_DM_SEQ_ALIAS=y
+CONFIG_REGMAP=y
+CONFIG_SPL_REGMAP=y
+CONFIG_SPL_OF_TRANSLATE=y
+CONFIG_CLK=y
+CONFIG_SPL_CLK=y
+CONFIG_SPL_CLK_CCF=y
+CONFIG_SPL_CLK_K3_PLL=y
+CONFIG_SPL_CLK_K3=y
+CONFIG_TI_SCI_PROTOCOL=y
+CONFIG_DA8XX_GPIO=y
+CONFIG_DM_MAILBOX=y
+CONFIG_K3_SEC_PROXY=y
+CONFIG_SPL_MISC=y
+CONFIG_ESM_K3=y
+CONFIG_MMC_SDHCI=y
+CONFIG_MMC_SDHCI_ADMA=y
+CONFIG_SPL_MMC_SDHCI_ADMA=y
+CONFIG_MMC_SDHCI_AM654=y
+CONFIG_PINCTRL=y
+# CONFIG_PINCTRL_GENERIC is not set
+CONFIG_SPL_PINCTRL=y
+# CONFIG_SPL_PINCTRL_GENERIC is not set
+CONFIG_PINCTRL_SINGLE=y
+CONFIG_POWER_DOMAIN=y
+CONFIG_TI_POWER_DOMAIN=y
+CONFIG_K3_SYSTEM_CONTROLLER=y
+CONFIG_REMOTEPROC_TI_K3_ARM64=y
+CONFIG_RESET_TI_SCI=y
+CONFIG_SPECIFY_CONSOLE_INDEX=y
+CONFIG_DM_SERIAL=y
+CONFIG_SOC_DEVICE=y
+CONFIG_SOC_DEVICE_TI_K3=y
+CONFIG_SOC_TI=y
+CONFIG_TIMER=y
+CONFIG_SPL_TIMER=y
+CONFIG_OMAP_TIMER=y
+CONFIG_LIB_RATIONAL=y
+CONFIG_SPL_LIB_RATIONAL=y
diff --git a/configs/am65x_evm_a53_defconfig b/configs/am65x_evm_a53_defconfig
index f436986..55289b9 100644
--- a/configs/am65x_evm_a53_defconfig
+++ b/configs/am65x_evm_a53_defconfig
@@ -52,7 +52,7 @@
CONFIG_SPL_FS_LOAD_PAYLOAD_NAME="u-boot.img"
CONFIG_SPL_I2C=y
CONFIG_SPL_DM_MAILBOX=y
-CONFIG_SPL_MTD_SUPPORT=y
+CONFIG_SPL_MTD=y
CONFIG_SPL_DM_SPI_FLASH=y
CONFIG_SPL_DM_RESET=y
CONFIG_SPL_POWER_DOMAIN=y
diff --git a/configs/am65x_evm_r5_usbdfu_defconfig b/configs/am65x_evm_r5_usbdfu_defconfig
index f610b2d..6b0bb12 100644
--- a/configs/am65x_evm_r5_usbdfu_defconfig
+++ b/configs/am65x_evm_r5_usbdfu_defconfig
@@ -21,7 +21,6 @@
CONFIG_SPL_STACK_R_ADDR=0x82000000
CONFIG_SPL_SIZE_LIMIT=0x7ec00
CONFIG_SPL_SIZE_LIMIT_PROVIDE_STACK=0x2000
-CONFIG_SPL_FS_FAT=y
CONFIG_SPL_LIBDISK_SUPPORT=y
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
CONFIG_SPL_LOAD_FIT=y
diff --git a/configs/arbel_evb_defconfig b/configs/arbel_evb_defconfig
index 6cfb5a7..e2714d1 100644
--- a/configs/arbel_evb_defconfig
+++ b/configs/arbel_evb_defconfig
@@ -4,6 +4,8 @@
CONFIG_SYS_MALLOC_LEN=0x240000
CONFIG_SYS_MALLOC_F_LEN=0x1000
CONFIG_NR_DRAM_BANKS=2
+CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y
+CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x06208000
CONFIG_ENV_SIZE=0x40000
CONFIG_ENV_OFFSET=0x3C0000
CONFIG_ENV_SECT_SIZE=0x1000
@@ -19,10 +21,12 @@
CONFIG_FIT_VERBOSE=y
CONFIG_USE_BOOTCOMMAND=y
CONFIG_BOOTCOMMAND="run common_bootargs; run romboot"
+CONFIG_LAST_STAGE_INIT=y
CONFIG_HUSH_PARSER=y
CONFIG_SYS_PROMPT="U-Boot>"
CONFIG_SYS_MAXARGS=32
CONFIG_SYS_BOOTM_LEN=0x1400000
+CONFIG_CMD_MEMTEST=y
CONFIG_CMD_FUSE=y
CONFIG_CMD_GPIO=y
CONFIG_CMD_GPT=y
@@ -31,6 +35,7 @@
CONFIG_CMD_PART=y
CONFIG_CMD_SPI=y
CONFIG_CMD_USB=y
+CONFIG_CMD_USB_MASS_STORAGE=y
CONFIG_CMD_DHCP=y
CONFIG_CMD_MII=y
CONFIG_CMD_PING=y
@@ -39,6 +44,7 @@
CONFIG_CMD_UUID=y
CONFIG_CMD_HASH=y
CONFIG_CMD_TPM=y
+CONFIG_CMD_EXT4=y
CONFIG_CMD_FAT=y
CONFIG_CMD_FS_GENERIC=y
CONFIG_ENV_IS_IN_SPI_FLASH=y
@@ -49,6 +55,7 @@
CONFIG_NPCM_SHA=y
CONFIG_NPCM_GPIO=y
CONFIG_DM_I2C=y
+CONFIG_SYS_I2C_NPCM=y
# CONFIG_INPUT is not set
CONFIG_MISC=y
CONFIG_NPCM_HOST=y
@@ -87,12 +94,17 @@
CONFIG_USB=y
CONFIG_USB_EHCI_HCD=y
CONFIG_USB_EHCI_NPCM=y
-CONFIG_USB_EHCI_GENERIC=y
CONFIG_USB_OHCI_HCD=y
-CONFIG_USB_OHCI_GENERIC=y
CONFIG_USB_OHCI_NPCM=y
CONFIG_USB_STORAGE=y
+CONFIG_USB_GADGET=y
+CONFIG_USB_GADGET_MANUFACTURER="Nuvoton"
+CONFIG_USB_GADGET_VENDOR_NUM=0x0416
+CONFIG_USB_GADGET_PRODUCT_NUM=0xffff
+CONFIG_CI_UDC=y
+CONFIG_USB_GADGET_DOWNLOAD=y
CONFIG_LIB_HW_RAND=y
CONFIG_TPM=y
CONFIG_SHA_HW_ACCEL=y
# CONFIG_EFI_LOADER is not set
+CONFIG_SYS_SKIP_UART_INIT=y
diff --git a/configs/axm_defconfig b/configs/axm_defconfig
index f9c0214..e1a01b2 100644
--- a/configs/axm_defconfig
+++ b/configs/axm_defconfig
@@ -86,7 +86,6 @@
# CONFIG_SYS_NAND_USE_FLASH_BBT is not set
CONFIG_NAND_ATMEL=y
CONFIG_SYS_NAND_BLOCK_SIZE=0x20000
-CONFIG_SYS_NAND_PAGE_COUNT=0x40
CONFIG_SYS_NAND_PAGE_SIZE=0x800
CONFIG_SYS_NAND_OOBSIZE=0x40
CONFIG_SYS_NAND_U_BOOT_LOCATIONS=y
diff --git a/configs/chiliboard_defconfig b/configs/chiliboard_defconfig
index 06642d2..0cd649d 100644
--- a/configs/chiliboard_defconfig
+++ b/configs/chiliboard_defconfig
@@ -63,7 +63,6 @@
CONFIG_MTD_RAW_NAND=y
CONFIG_SYS_NAND_BLOCK_SIZE=0x20000
CONFIG_SYS_NAND_ONFI_DETECTION=y
-CONFIG_SYS_NAND_PAGE_COUNT=0x40
CONFIG_SYS_NAND_PAGE_SIZE=0x800
CONFIG_SYS_NAND_OOBSIZE=0x40
CONFIG_SYS_NAND_U_BOOT_LOCATIONS=y
diff --git a/configs/ci20_mmc_defconfig b/configs/ci20_mmc_defconfig
index 6621ca9..bf522e1 100644
--- a/configs/ci20_mmc_defconfig
+++ b/configs/ci20_mmc_defconfig
@@ -47,7 +47,6 @@
CONFIG_ENV_IS_IN_MMC=y
CONFIG_SYS_RELOC_GD_ENV_ADDR=y
CONFIG_VERSION_VARIABLE=y
-# CONFIG_DM_WARN is not set
# CONFIG_DM_DEVICE_REMOVE is not set
CONFIG_JZ4780_EFUSE=y
CONFIG_MMC=y
diff --git a/configs/cm_t43_defconfig b/configs/cm_t43_defconfig
index 73ccefd..1a558b0 100644
--- a/configs/cm_t43_defconfig
+++ b/configs/cm_t43_defconfig
@@ -37,7 +37,7 @@
CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x480
CONFIG_SPL_FS_EXT4=y
CONFIG_SPL_I2C=y
-CONFIG_SPL_MTD_SUPPORT=y
+CONFIG_SPL_MTD=y
# CONFIG_SPL_NAND_SUPPORT is not set
CONFIG_SPL_NAND_DRIVERS=y
CONFIG_SPL_NAND_ECC=y
diff --git a/configs/corvus_defconfig b/configs/corvus_defconfig
index ecf61f0..5eaa6db 100644
--- a/configs/corvus_defconfig
+++ b/configs/corvus_defconfig
@@ -81,7 +81,6 @@
# CONFIG_SYS_NAND_USE_FLASH_BBT is not set
CONFIG_NAND_ATMEL=y
CONFIG_SYS_NAND_BLOCK_SIZE=0x20000
-CONFIG_SYS_NAND_PAGE_COUNT=0x40
CONFIG_SYS_NAND_PAGE_SIZE=0x800
CONFIG_SYS_NAND_OOBSIZE=0x40
CONFIG_SYS_NAND_U_BOOT_LOCATIONS=y
diff --git a/configs/da850evm_nand_defconfig b/configs/da850evm_nand_defconfig
index 5f6f5d7..62b8edd 100644
--- a/configs/da850evm_nand_defconfig
+++ b/configs/da850evm_nand_defconfig
@@ -88,7 +88,6 @@
CONFIG_SYS_NAND_USE_FLASH_BBT=y
CONFIG_NAND_DAVINCI=y
CONFIG_SYS_NAND_BLOCK_SIZE=0x20000
-CONFIG_SYS_NAND_PAGE_COUNT=0x40
CONFIG_SYS_NAND_PAGE_SIZE=0x800
CONFIG_SYS_NAND_OOBSIZE=0x40
CONFIG_SYS_NAND_U_BOOT_LOCATIONS=y
diff --git a/configs/devkit3250_defconfig b/configs/devkit3250_defconfig
index ec4031d..569b156 100644
--- a/configs/devkit3250_defconfig
+++ b/configs/devkit3250_defconfig
@@ -73,7 +73,6 @@
CONFIG_SYS_NAND_USE_FLASH_BBT=y
CONFIG_NAND_LPC32XX_SLC=y
CONFIG_SYS_NAND_BLOCK_SIZE=0x20000
-CONFIG_SYS_NAND_PAGE_COUNT=0x40
CONFIG_SYS_NAND_PAGE_SIZE=0x800
CONFIG_SYS_NAND_OOBSIZE=0x40
# CONFIG_SYS_NAND_5_ADDR_CYCLE is not set
diff --git a/configs/devkit8000_defconfig b/configs/devkit8000_defconfig
index ef16da1..a7f8244 100644
--- a/configs/devkit8000_defconfig
+++ b/configs/devkit8000_defconfig
@@ -77,7 +77,6 @@
CONFIG_MTD_RAW_NAND=y
CONFIG_NAND_OMAP_ECCSCHEME_HAM1_CODE_HW=y
CONFIG_SYS_NAND_BLOCK_SIZE=0x20000
-CONFIG_SYS_NAND_PAGE_COUNT=0x40
CONFIG_SYS_NAND_PAGE_SIZE=0x800
CONFIG_SYS_NAND_OOBSIZE=0x40
CONFIG_SYS_NAND_BUSWIDTH_16BIT=y
diff --git a/configs/dra7xx_evm_defconfig b/configs/dra7xx_evm_defconfig
index 19ca89f..c3a3ec2 100644
--- a/configs/dra7xx_evm_defconfig
+++ b/configs/dra7xx_evm_defconfig
@@ -104,7 +104,6 @@
CONFIG_MTD_RAW_NAND=y
CONFIG_SYS_NAND_BLOCK_SIZE=0x20000
CONFIG_SYS_NAND_ONFI_DETECTION=y
-CONFIG_SYS_NAND_PAGE_COUNT=0x40
CONFIG_SYS_NAND_PAGE_SIZE=0x800
CONFIG_SYS_NAND_OOBSIZE=0x40
CONFIG_SYS_NAND_BUSWIDTH_16BIT=y
diff --git a/configs/etamin_defconfig b/configs/draco-etamin_defconfig
similarity index 91%
rename from configs/etamin_defconfig
rename to configs/draco-etamin_defconfig
index c0ce7a3..ef7c7c1 100644
--- a/configs/etamin_defconfig
+++ b/configs/draco-etamin_defconfig
@@ -2,7 +2,6 @@
CONFIG_ARCH_OMAP2PLUS=y
CONFIG_TEXT_BASE=0x80100000
CONFIG_SYS_MALLOC_LEN=0x1000000
-CONFIG_SPL_GPIO=y
CONFIG_SPL_LIBCOMMON_SUPPORT=y
CONFIG_SPL_LIBGENERIC_SUPPORT=y
CONFIG_NR_DRAM_BANKS=1
@@ -10,7 +9,6 @@
CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x4030ff00
CONFIG_ENV_SIZE=0x2000
CONFIG_ENV_OFFSET=0x980000
-CONFIG_SPL_DM_SPI=y
CONFIG_DEFAULT_DEVICE_TREE="am335x-draco"
CONFIG_AM33XX=y
CONFIG_SYS_MPUCLK=300
@@ -22,8 +20,6 @@
CONFIG_ENV_OFFSET_REDUND=0xB80000
CONFIG_SPL_FS_FAT=y
CONFIG_SPL_LIBDISK_SUPPORT=y
-CONFIG_SPL_SPI_FLASH_SUPPORT=y
-CONFIG_SPL_SPI=y
CONFIG_SYS_LOAD_ADDR=0x81000000
CONFIG_ENV_VARS_UBOOT_CONFIG=y
CONFIG_BOOTDELAY=3
@@ -36,7 +32,6 @@
CONFIG_USE_PREBOOT=y
CONFIG_SYS_CONSOLE_INFO_QUIET=y
# CONFIG_DISPLAY_BOARDINFO is not set
-CONFIG_ARCH_MISC_INIT=y
CONFIG_SPL_BSS_START_ADDR=0x80000000
CONFIG_SPL_SYS_MALLOC=y
CONFIG_SPL_HAS_CUSTOM_MALLOC_START=y
@@ -45,9 +40,6 @@
CONFIG_SPL_NAND_DRIVERS=y
CONFIG_SPL_NAND_ECC=y
CONFIG_SPL_NAND_BASE=y
-CONFIG_SPL_DM_SPI_FLASH=y
-CONFIG_SPL_SPI_LOAD=y
-CONFIG_SYS_SPI_U_BOOT_OFFS=0x20000
CONFIG_SPL_WATCHDOG=y
CONFIG_SPL_YMODEM_SUPPORT=y
# CONFIG_SPL_AM33XX_ENABLE_RTC32K_OSC is not set
@@ -76,7 +68,6 @@
CONFIG_MTDPARTS_DEFAULT="mtdparts=omap2-nand_concat:512k(spl),512k(spl.backup1),512k(spl.backup2),512k(spl.backup3),7680k(u-boot),2048k(u-boot.env0),2048k(u-boot.env1),2048k(mtdoops),-(rootfs)"
CONFIG_CMD_UBI=y
CONFIG_OF_CONTROL=y
-CONFIG_SPL_OF_CONTROL=y
CONFIG_OF_EMBED=y
CONFIG_ENV_OVERWRITE=y
CONFIG_ENV_IS_IN_NAND=y
@@ -91,6 +82,8 @@
# CONFIG_SPL_BLK is not set
CONFIG_BOOTCOUNT_LIMIT=y
CONFIG_BOOTCOUNT_ENV=y
+CONFIG_CLK=y
+CONFIG_CLK_TI_CTRL=y
CONFIG_DFU_NAND=y
CONFIG_SYS_DFU_DATA_BUF_SIZE=0x100000
CONFIG_SYS_I2C_LEGACY=y
@@ -104,13 +97,10 @@
CONFIG_NAND_OMAP_ECCSCHEME_BCH16_CODE_HW=y
CONFIG_SYS_NAND_BLOCK_SIZE=0x80000
CONFIG_SYS_NAND_ONFI_DETECTION=y
-CONFIG_SYS_NAND_PAGE_COUNT=0x80
CONFIG_SYS_NAND_PAGE_SIZE=0x1000
CONFIG_SYS_NAND_OOBSIZE=0xe0
CONFIG_SYS_NAND_U_BOOT_LOCATIONS=y
CONFIG_SYS_NAND_U_BOOT_OFFS=0x200000
-CONFIG_DM_SPI_FLASH=y
-CONFIG_SPI_FLASH_WINBOND=y
CONFIG_MTD_UBI_FASTMAP=y
CONFIG_MTD_UBI_FASTMAP_AUTOCONVERT=1
CONFIG_PHY_SMSC=y
diff --git a/configs/rastaban_defconfig b/configs/draco-rastaban_defconfig
similarity index 89%
rename from configs/rastaban_defconfig
rename to configs/draco-rastaban_defconfig
index 9f538a2..b293ed5 100644
--- a/configs/rastaban_defconfig
+++ b/configs/draco-rastaban_defconfig
@@ -2,27 +2,22 @@
CONFIG_ARCH_OMAP2PLUS=y
CONFIG_TEXT_BASE=0x80100000
CONFIG_SYS_MALLOC_LEN=0x1000000
-CONFIG_SPL_GPIO=y
CONFIG_SPL_LIBCOMMON_SUPPORT=y
CONFIG_SPL_LIBGENERIC_SUPPORT=y
CONFIG_NR_DRAM_BANKS=1
CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y
CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x4030ff00
CONFIG_ENV_SIZE=0x2000
-CONFIG_SPL_DM_SPI=y
CONFIG_DEFAULT_DEVICE_TREE="am335x-draco"
CONFIG_AM33XX=y
CONFIG_SYS_MPUCLK=300
CONFIG_TARGET_RASTABAN=y
-CONFIG_SPL_MMC=y
CONFIG_SPL_SERIAL=y
CONFIG_BOOTCOUNT_BOOTLIMIT=3
CONFIG_SPL=y
CONFIG_ENV_OFFSET_REDUND=0x2E0000
CONFIG_SPL_FS_FAT=y
CONFIG_SPL_LIBDISK_SUPPORT=y
-CONFIG_SPL_SPI_FLASH_SUPPORT=y
-CONFIG_SPL_SPI=y
CONFIG_SYS_LOAD_ADDR=0x81000000
CONFIG_ENV_VARS_UBOOT_CONFIG=y
CONFIG_BOOTDELAY=3
@@ -35,18 +30,15 @@
CONFIG_USE_PREBOOT=y
CONFIG_SYS_CONSOLE_INFO_QUIET=y
# CONFIG_DISPLAY_BOARDINFO is not set
-CONFIG_ARCH_MISC_INIT=y
CONFIG_SPL_BSS_START_ADDR=0x80000000
CONFIG_SPL_SYS_MALLOC=y
CONFIG_SPL_HAS_CUSTOM_MALLOC_START=y
CONFIG_SPL_CUSTOM_SYS_MALLOC_ADDR=0x80208000
+# CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR is not set
CONFIG_SPL_I2C=y
CONFIG_SPL_NAND_DRIVERS=y
CONFIG_SPL_NAND_ECC=y
CONFIG_SPL_NAND_BASE=y
-CONFIG_SPL_DM_SPI_FLASH=y
-CONFIG_SPL_SPI_LOAD=y
-CONFIG_SYS_SPI_U_BOOT_OFFS=0x20000
CONFIG_SPL_WATCHDOG=y
CONFIG_SPL_YMODEM_SUPPORT=y
# CONFIG_SPL_AM33XX_ENABLE_RTC32K_OSC is not set
@@ -59,7 +51,6 @@
# CONFIG_CMD_FLASH is not set
CONFIG_CMD_GPIO=y
CONFIG_CMD_I2C=y
-CONFIG_CMD_MMC=y
CONFIG_CMD_NAND=y
CONFIG_CMD_USB=y
# CONFIG_CMD_SETEXPR is not set
@@ -75,7 +66,6 @@
CONFIG_MTDPARTS_DEFAULT="mtdparts=omap2-nand.0:128k(spl),128k(spl.backup1),128k(spl.backup2),128k(spl.backup3),1920k(u-boot),512k(u-boot.env0),512k(u-boot.env1),300m(rootfs),512k(mtdoops),-(configuration)"
CONFIG_CMD_UBI=y
CONFIG_OF_CONTROL=y
-CONFIG_SPL_OF_CONTROL=y
CONFIG_OF_EMBED=y
CONFIG_ENV_OVERWRITE=y
CONFIG_ENV_IS_IN_NAND=y
@@ -90,23 +80,21 @@
# CONFIG_SPL_BLK is not set
CONFIG_BOOTCOUNT_LIMIT=y
CONFIG_BOOTCOUNT_ENV=y
+CONFIG_CLK=y
+CONFIG_CLK_TI_CTRL=y
CONFIG_DFU_NAND=y
CONFIG_SYS_DFU_DATA_BUF_SIZE=0x100000
CONFIG_SYS_I2C_LEGACY=y
CONFIG_SPL_SYS_I2C_LEGACY=y
-# CONFIG_SPL_DM_MMC is not set
-CONFIG_MMC_OMAP_HS=y
+# CONFIG_MMC is not set
CONFIG_MTD=y
CONFIG_MTD_RAW_NAND=y
CONFIG_SYS_NAND_BLOCK_SIZE=0x20000
CONFIG_SYS_NAND_ONFI_DETECTION=y
-CONFIG_SYS_NAND_PAGE_COUNT=0x40
CONFIG_SYS_NAND_PAGE_SIZE=0x800
CONFIG_SYS_NAND_OOBSIZE=0x40
CONFIG_SYS_NAND_U_BOOT_LOCATIONS=y
CONFIG_SYS_NAND_U_BOOT_OFFS=0x80000
-CONFIG_DM_SPI_FLASH=y
-CONFIG_SPI_FLASH_WINBOND=y
CONFIG_MTD_UBI_FASTMAP=y
CONFIG_MTD_UBI_FASTMAP_AUTOCONVERT=1
CONFIG_PHY_SMSC=y
diff --git a/configs/thuban_defconfig b/configs/draco-thuban_defconfig
similarity index 88%
rename from configs/thuban_defconfig
rename to configs/draco-thuban_defconfig
index 116700e..6c03732 100644
--- a/configs/thuban_defconfig
+++ b/configs/draco-thuban_defconfig
@@ -2,27 +2,22 @@
CONFIG_ARCH_OMAP2PLUS=y
CONFIG_TEXT_BASE=0x80100000
CONFIG_SYS_MALLOC_LEN=0x1000000
-CONFIG_SPL_GPIO=y
CONFIG_SPL_LIBCOMMON_SUPPORT=y
CONFIG_SPL_LIBGENERIC_SUPPORT=y
CONFIG_NR_DRAM_BANKS=1
CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y
CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x4030ff00
CONFIG_ENV_SIZE=0x2000
-CONFIG_SPL_DM_SPI=y
CONFIG_DEFAULT_DEVICE_TREE="am335x-draco"
CONFIG_AM33XX=y
CONFIG_SYS_MPUCLK=300
CONFIG_TARGET_THUBAN=y
-CONFIG_SPL_MMC=y
CONFIG_SPL_SERIAL=y
CONFIG_BOOTCOUNT_BOOTLIMIT=3
CONFIG_SPL=y
CONFIG_ENV_OFFSET_REDUND=0x2E0000
CONFIG_SPL_FS_FAT=y
CONFIG_SPL_LIBDISK_SUPPORT=y
-CONFIG_SPL_SPI_FLASH_SUPPORT=y
-CONFIG_SPL_SPI=y
CONFIG_SYS_LOAD_ADDR=0x81000000
CONFIG_ENV_VARS_UBOOT_CONFIG=y
CONFIG_BOOTDELAY=3
@@ -35,18 +30,15 @@
CONFIG_USE_PREBOOT=y
CONFIG_SYS_CONSOLE_INFO_QUIET=y
# CONFIG_DISPLAY_BOARDINFO is not set
-CONFIG_ARCH_MISC_INIT=y
CONFIG_SPL_BSS_START_ADDR=0x80000000
CONFIG_SPL_SYS_MALLOC=y
CONFIG_SPL_HAS_CUSTOM_MALLOC_START=y
CONFIG_SPL_CUSTOM_SYS_MALLOC_ADDR=0x80208000
+# CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR is not set
CONFIG_SPL_I2C=y
CONFIG_SPL_NAND_DRIVERS=y
CONFIG_SPL_NAND_ECC=y
CONFIG_SPL_NAND_BASE=y
-CONFIG_SPL_DM_SPI_FLASH=y
-CONFIG_SPL_SPI_LOAD=y
-CONFIG_SYS_SPI_U_BOOT_OFFS=0x20000
CONFIG_SPL_WATCHDOG=y
CONFIG_SPL_YMODEM_SUPPORT=y
# CONFIG_SPL_AM33XX_ENABLE_RTC32K_OSC is not set
@@ -59,7 +51,6 @@
# CONFIG_CMD_FLASH is not set
CONFIG_CMD_GPIO=y
CONFIG_CMD_I2C=y
-CONFIG_CMD_MMC=y
CONFIG_CMD_NAND=y
CONFIG_CMD_USB=y
# CONFIG_CMD_SETEXPR is not set
@@ -75,7 +66,6 @@
CONFIG_MTDPARTS_DEFAULT="mtdparts=omap2-nand.0:128k(spl),128k(spl.backup1),128k(spl.backup2),128k(spl.backup3),1920k(u-boot),512k(u-boot.env0),512k(u-boot.env1),512k(mtdoops),-(rootfs)"
CONFIG_CMD_UBI=y
CONFIG_OF_CONTROL=y
-CONFIG_SPL_OF_CONTROL=y
CONFIG_OF_EMBED=y
CONFIG_ENV_OVERWRITE=y
CONFIG_ENV_IS_IN_NAND=y
@@ -90,23 +80,21 @@
# CONFIG_SPL_BLK is not set
CONFIG_BOOTCOUNT_LIMIT=y
CONFIG_BOOTCOUNT_ENV=y
+CONFIG_CLK=y
+CONFIG_CLK_TI_CTRL=y
CONFIG_DFU_NAND=y
CONFIG_SYS_DFU_DATA_BUF_SIZE=0x100000
CONFIG_SYS_I2C_LEGACY=y
CONFIG_SPL_SYS_I2C_LEGACY=y
-# CONFIG_SPL_DM_MMC is not set
-CONFIG_MMC_OMAP_HS=y
+# CONFIG_MMC is not set
CONFIG_MTD=y
CONFIG_MTD_RAW_NAND=y
CONFIG_SYS_NAND_BLOCK_SIZE=0x20000
CONFIG_SYS_NAND_ONFI_DETECTION=y
-CONFIG_SYS_NAND_PAGE_COUNT=0x40
CONFIG_SYS_NAND_PAGE_SIZE=0x800
CONFIG_SYS_NAND_OOBSIZE=0x40
CONFIG_SYS_NAND_U_BOOT_LOCATIONS=y
CONFIG_SYS_NAND_U_BOOT_OFFS=0x80000
-CONFIG_DM_SPI_FLASH=y
-CONFIG_SPI_FLASH_WINBOND=y
CONFIG_MTD_UBI_FASTMAP=y
CONFIG_MTD_UBI_FASTMAP_AUTOCONVERT=1
CONFIG_PHY_SMSC=y
diff --git a/configs/draco_defconfig b/configs/draco_defconfig
deleted file mode 100644
index ee19920..0000000
--- a/configs/draco_defconfig
+++ /dev/null
@@ -1,127 +0,0 @@
-CONFIG_ARM=y
-CONFIG_ARCH_OMAP2PLUS=y
-CONFIG_TEXT_BASE=0x80100000
-CONFIG_SYS_MALLOC_LEN=0x1000000
-CONFIG_SPL_GPIO=y
-CONFIG_SPL_LIBCOMMON_SUPPORT=y
-CONFIG_SPL_LIBGENERIC_SUPPORT=y
-CONFIG_NR_DRAM_BANKS=1
-CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y
-CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x4030ff00
-CONFIG_ENV_SIZE=0x2000
-CONFIG_SPL_DM_SPI=y
-CONFIG_DEFAULT_DEVICE_TREE="am335x-draco"
-CONFIG_AM33XX=y
-CONFIG_SYS_MPUCLK=300
-CONFIG_TARGET_DRACO=y
-CONFIG_SPL_MMC=y
-CONFIG_SPL_SERIAL=y
-CONFIG_BOOTCOUNT_BOOTLIMIT=3
-CONFIG_SPL=y
-CONFIG_ENV_OFFSET_REDUND=0x2E0000
-CONFIG_SPL_FS_FAT=y
-CONFIG_SPL_LIBDISK_SUPPORT=y
-CONFIG_SPL_SPI_FLASH_SUPPORT=y
-CONFIG_SPL_SPI=y
-CONFIG_SYS_LOAD_ADDR=0x81000000
-CONFIG_ENV_VARS_UBOOT_CONFIG=y
-CONFIG_BOOTDELAY=3
-CONFIG_AUTOBOOT_KEYED=y
-CONFIG_AUTOBOOT_PROMPT="Autobooting in %d seconds, press \"<Esc><Esc>\" to stop\n"
-CONFIG_AUTOBOOT_STOP_STR="\x1b\x1b"
-CONFIG_BOOT_RETRY=y
-CONFIG_BOOT_RETRY_TIME=60
-CONFIG_RESET_TO_RETRY=y
-CONFIG_USE_PREBOOT=y
-CONFIG_SYS_CONSOLE_INFO_QUIET=y
-# CONFIG_DISPLAY_BOARDINFO is not set
-CONFIG_ARCH_MISC_INIT=y
-CONFIG_SPL_BSS_START_ADDR=0x80000000
-CONFIG_SPL_SYS_MALLOC=y
-CONFIG_SPL_HAS_CUSTOM_MALLOC_START=y
-CONFIG_SPL_CUSTOM_SYS_MALLOC_ADDR=0x80208000
-CONFIG_SPL_I2C=y
-CONFIG_SPL_NAND_DRIVERS=y
-CONFIG_SPL_NAND_ECC=y
-CONFIG_SPL_NAND_BASE=y
-CONFIG_SPL_DM_SPI_FLASH=y
-CONFIG_SPL_SPI_LOAD=y
-CONFIG_SYS_SPI_U_BOOT_OFFS=0x20000
-CONFIG_SPL_WATCHDOG=y
-CONFIG_SPL_YMODEM_SUPPORT=y
-# CONFIG_SPL_AM33XX_ENABLE_RTC32K_OSC is not set
-CONFIG_HUSH_PARSER=y
-CONFIG_SYS_PROMPT="U-Boot# "
-CONFIG_SYS_MAXARGS=32
-CONFIG_SYS_PBSIZE=1049
-CONFIG_CMD_ASKENV=y
-CONFIG_CMD_DFU=y
-# CONFIG_CMD_FLASH is not set
-CONFIG_CMD_GPIO=y
-CONFIG_CMD_I2C=y
-CONFIG_CMD_MMC=y
-CONFIG_CMD_NAND=y
-CONFIG_CMD_USB=y
-# CONFIG_CMD_SETEXPR is not set
-CONFIG_CMD_DHCP=y
-CONFIG_BOOTP_DNS2=y
-CONFIG_CMD_MII=y
-CONFIG_CMD_PING=y
-CONFIG_CMD_CACHE=y
-CONFIG_CMD_TIME=y
-CONFIG_CMD_EXT2=y
-CONFIG_CMD_MTDPARTS=y
-CONFIG_MTDIDS_DEFAULT="nand0=omap2-nand.0"
-CONFIG_MTDPARTS_DEFAULT="mtdparts=omap2-nand.0:128k(spl),128k(spl.backup1),128k(spl.backup2),128k(spl.backup3),1920k(u-boot),512k(u-boot.env0),512k(u-boot.env1),512k(mtdoops),-(rootfs)"
-CONFIG_CMD_UBI=y
-CONFIG_OF_CONTROL=y
-CONFIG_SPL_OF_CONTROL=y
-CONFIG_OF_EMBED=y
-CONFIG_ENV_OVERWRITE=y
-CONFIG_ENV_IS_IN_NAND=y
-CONFIG_ENV_RANGE=0x80000
-CONFIG_SYS_REDUNDAND_ENVIRONMENT=y
-CONFIG_SYS_RELOC_GD_ENV_ADDR=y
-CONFIG_NET_RETRY_COUNT=10
-CONFIG_BOOTP_SEND_HOSTNAME=y
-CONFIG_USE_ROOTPATH=y
-CONFIG_ROOTPATH="/opt/eldk"
-CONFIG_SPL_DM=y
-# CONFIG_SPL_BLK is not set
-CONFIG_BOOTCOUNT_LIMIT=y
-CONFIG_BOOTCOUNT_ENV=y
-CONFIG_DFU_NAND=y
-CONFIG_SYS_DFU_DATA_BUF_SIZE=0x100000
-CONFIG_SYS_I2C_LEGACY=y
-CONFIG_SPL_SYS_I2C_LEGACY=y
-# CONFIG_SPL_DM_MMC is not set
-CONFIG_MMC_OMAP_HS=y
-CONFIG_MTD=y
-CONFIG_MTD_RAW_NAND=y
-CONFIG_SYS_NAND_BLOCK_SIZE=0x20000
-CONFIG_SYS_NAND_ONFI_DETECTION=y
-CONFIG_SYS_NAND_PAGE_COUNT=0x40
-CONFIG_SYS_NAND_PAGE_SIZE=0x800
-CONFIG_SYS_NAND_OOBSIZE=0x40
-CONFIG_SYS_NAND_U_BOOT_LOCATIONS=y
-CONFIG_SYS_NAND_U_BOOT_OFFS=0x80000
-CONFIG_DM_SPI_FLASH=y
-CONFIG_SPI_FLASH_WINBOND=y
-CONFIG_MTD_UBI_FASTMAP=y
-CONFIG_MTD_UBI_FASTMAP_AUTOCONVERT=1
-CONFIG_PHY_SMSC=y
-CONFIG_DRIVER_TI_CPSW=y
-CONFIG_SPI=y
-CONFIG_DM_SPI=y
-CONFIG_OMAP3_SPI=y
-CONFIG_USB=y
-# CONFIG_SPL_DM_USB is not set
-CONFIG_USB_MUSB_HOST=y
-CONFIG_USB_MUSB_GADGET=y
-CONFIG_USB_MUSB_DSPS=y
-CONFIG_USB_GADGET=y
-CONFIG_USB_GADGET_MANUFACTURER="Siemens AG"
-CONFIG_USB_GADGET_VENDOR_NUM=0x0908
-CONFIG_USB_GADGET_PRODUCT_NUM=0x02d2
-CONFIG_USB_GADGET_DOWNLOAD=y
-CONFIG_USB_ETHER=y
diff --git a/configs/eDPU_defconfig b/configs/eDPU_defconfig
index f51df78..238f91c 100644
--- a/configs/eDPU_defconfig
+++ b/configs/eDPU_defconfig
@@ -81,6 +81,7 @@
CONFIG_DM_REGULATOR_FIXED=y
CONFIG_DM_REGULATOR_GPIO=y
# CONFIG_SCSI is not set
+CONFIG_DEFAULT_ENV_IS_RW=y
CONFIG_MVEBU_A3700_UART=y
CONFIG_MVEBU_A3700_SPI=y
CONFIG_SYSINFO=y
diff --git a/configs/efi-x86_app32_defconfig b/configs/efi-x86_app32_defconfig
index 682ba5b..e2e6f42 100644
--- a/configs/efi-x86_app32_defconfig
+++ b/configs/efi-x86_app32_defconfig
@@ -21,7 +21,6 @@
CONFIG_CMD_BOOTZ=y
CONFIG_CMD_PART=y
# CONFIG_CMD_SCSI is not set
-# CONFIG_CMD_NET is not set
CONFIG_CMD_TIME=y
CONFIG_CMD_EXT2=y
CONFIG_CMD_EXT4=y
@@ -36,7 +35,7 @@
CONFIG_SYS_RELOC_GD_ENV_ADDR=y
CONFIG_USE_BOOTFILE=y
CONFIG_BOOTFILE="bzImage"
-CONFIG_USE_ROOTPATH=y
+# CONFIG_NET is not set
CONFIG_REGMAP=y
CONFIG_SYSCON=y
# CONFIG_REGEX is not set
diff --git a/configs/efi-x86_app64_defconfig b/configs/efi-x86_app64_defconfig
index d6b6c3d..14b5cd0 100644
--- a/configs/efi-x86_app64_defconfig
+++ b/configs/efi-x86_app64_defconfig
@@ -22,7 +22,6 @@
CONFIG_CMD_BOOTZ=y
CONFIG_CMD_PART=y
# CONFIG_CMD_SCSI is not set
-# CONFIG_CMD_NET is not set
CONFIG_CMD_CACHE=y
CONFIG_CMD_TIME=y
CONFIG_CMD_EXT2=y
@@ -38,7 +37,7 @@
CONFIG_SYS_RELOC_GD_ENV_ADDR=y
CONFIG_USE_BOOTFILE=y
CONFIG_BOOTFILE="bzImage"
-CONFIG_USE_ROOTPATH=y
+# CONFIG_NET is not set
CONFIG_REGMAP=y
CONFIG_SYSCON=y
CONFIG_CONSOLE_SCROLL_LINES=5
diff --git a/configs/endeavoru_defconfig b/configs/endeavoru_defconfig
index d605acd..7212675 100644
--- a/configs/endeavoru_defconfig
+++ b/configs/endeavoru_defconfig
@@ -44,6 +44,7 @@
CONFIG_CMD_UMS_ABORT_KEYED=y
# CONFIG_CMD_SETEXPR is not set
CONFIG_CMD_PAUSE=y
+CONFIG_CMD_REGULATOR=y
CONFIG_CMD_EXT4_WRITE=y
# CONFIG_SPL_DOS_PARTITION is not set
# CONFIG_SPL_EFI_PARTITION is not set
@@ -61,10 +62,13 @@
CONFIG_SYS_I2C_TEGRA=y
CONFIG_BUTTON_KEYBOARD=y
CONFIG_DM_PMIC=y
+CONFIG_DM_PMIC_TPS80031=y
CONFIG_DM_REGULATOR=y
CONFIG_DM_REGULATOR_FIXED=y
+CONFIG_DM_REGULATOR_TPS80031=y
CONFIG_PWM_TEGRA=y
CONFIG_SYS_NS16550=y
+CONFIG_SYSRESET_TPS80031=y
CONFIG_USB=y
CONFIG_USB_EHCI_HCD=y
CONFIG_USB_EHCI_TEGRA=y
diff --git a/configs/gardena-smart-gateway-at91sam_defconfig b/configs/gardena-smart-gateway-at91sam_defconfig
index 439fcc0..0fb92ff 100644
--- a/configs/gardena-smart-gateway-at91sam_defconfig
+++ b/configs/gardena-smart-gateway-at91sam_defconfig
@@ -99,7 +99,6 @@
CONFIG_NAND_ATMEL=y
CONFIG_SPL_GENERATE_ATMEL_PMECC_HEADER=y
CONFIG_SYS_NAND_BLOCK_SIZE=0x20000
-CONFIG_SYS_NAND_PAGE_COUNT=0x40
CONFIG_SYS_NAND_PAGE_SIZE=0x800
CONFIG_SYS_NAND_OOBSIZE=0x40
CONFIG_SYS_NAND_U_BOOT_LOCATIONS=y
diff --git a/configs/grouper_common_defconfig b/configs/grouper_common_defconfig
index 258d7b1..616540f 100644
--- a/configs/grouper_common_defconfig
+++ b/configs/grouper_common_defconfig
@@ -43,6 +43,7 @@
CONFIG_CMD_UMS_ABORT_KEYED=y
# CONFIG_CMD_SETEXPR is not set
CONFIG_CMD_PAUSE=y
+CONFIG_CMD_REGULATOR=y
CONFIG_CMD_EXT4_WRITE=y
# CONFIG_SPL_DOS_PARTITION is not set
# CONFIG_SPL_EFI_PARTITION is not set
diff --git a/configs/icnova-a20-adb4006_defconfig b/configs/icnova-a20-adb4006_defconfig
new file mode 100644
index 0000000..22cbb61
--- /dev/null
+++ b/configs/icnova-a20-adb4006_defconfig
@@ -0,0 +1,21 @@
+CONFIG_ARM=y
+CONFIG_ARCH_SUNXI=y
+CONFIG_DEFAULT_DEVICE_TREE="sun7i-a20-icnova-a20-adb4006"
+CONFIG_SPL=y
+CONFIG_MACH_SUN7I=y
+CONFIG_DRAM_CLK=384
+CONFIG_AHCI=y
+# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
+CONFIG_SPL_I2C=y
+CONFIG_SCSI_AHCI=y
+CONFIG_SYS_64BIT_LBA=y
+CONFIG_SYS_I2C_MVTWSI=y
+CONFIG_SYS_I2C_SLAVE=0x7f
+CONFIG_SYS_I2C_SPEED=400000
+CONFIG_ETH_DESIGNWARE=y
+CONFIG_MII=y
+CONFIG_SUN7I_GMAC=y
+CONFIG_AXP_ALDO4_VOLT=2800
+CONFIG_SCSI=y
+CONFIG_USB_EHCI_HCD=y
+CONFIG_USB_OHCI_HCD=y
diff --git a/configs/igep00x0_defconfig b/configs/igep00x0_defconfig
index 993bbe2..34439cf 100644
--- a/configs/igep00x0_defconfig
+++ b/configs/igep00x0_defconfig
@@ -24,7 +24,7 @@
CONFIG_SPL_SYS_MALLOC=y
CONFIG_SPL_SYS_MALLOC_SIZE=0x800000
# CONFIG_SPL_FS_EXT4 is not set
-CONFIG_SPL_MTD_SUPPORT=y
+CONFIG_SPL_MTD=y
CONFIG_SPL_NAND_DRIVERS=y
CONFIG_SPL_NAND_ECC=y
CONFIG_SPL_NAND_SIMPLE=y
@@ -78,7 +78,6 @@
CONFIG_MTD_RAW_NAND=y
CONFIG_NAND_OMAP_ECCSCHEME_BCH8_CODE_HW_DETECTION_SW=y
CONFIG_SYS_NAND_BLOCK_SIZE=0x20000
-CONFIG_SYS_NAND_PAGE_COUNT=0x40
CONFIG_SYS_NAND_PAGE_SIZE=0x800
CONFIG_SYS_NAND_OOBSIZE=0x40
CONFIG_SYS_NAND_BUSWIDTH_16BIT=y
diff --git a/configs/imx6q_bosch_acc_defconfig b/configs/imx6q_bosch_acc_defconfig
index 05bab03..6abb795 100644
--- a/configs/imx6q_bosch_acc_defconfig
+++ b/configs/imx6q_bosch_acc_defconfig
@@ -63,7 +63,6 @@
# CONFIG_CMD_ITEST is not set
# CONFIG_CMD_SOURCE is not set
# CONFIG_CMD_SETEXPR is not set
-# CONFIG_CMD_NET is not set
# CONFIG_CMD_BLOCK_CACHE is not set
# CONFIG_CMD_SLEEP is not set
# CONFIG_CMD_MP is not set
@@ -82,7 +81,7 @@
CONFIG_ENV_WRITEABLE_LIST=y
CONFIG_ENV_ACCESS_IGNORE_FORCE=y
CONFIG_VERSION_VARIABLE=y
-CONFIG_TFTP_BLOCKSIZE=512
+# CONFIG_NET is not set
CONFIG_SPL_DM=y
CONFIG_BOOTCOUNT_LIMIT=y
CONFIG_DM_BOOTCOUNT=y
diff --git a/configs/imx6ulz_smm_m2_defconfig b/configs/imx6ulz_smm_m2_defconfig
index d6edc71..c471e04 100644
--- a/configs/imx6ulz_smm_m2_defconfig
+++ b/configs/imx6ulz_smm_m2_defconfig
@@ -25,7 +25,7 @@
CONFIG_SPL_BSS_START_ADDR=0x84100000
CONFIG_SPL_SYS_MALLOC=y
CONFIG_SPL_DMA=y
-CONFIG_SPL_MTD_SUPPORT=y
+CONFIG_SPL_MTD=y
CONFIG_SPL_NAND_SUPPORT=y
CONFIG_SPL_WATCHDOG=y
CONFIG_CMD_DM=y
diff --git a/configs/imx8mn_bsh_smm_s2_defconfig b/configs/imx8mn_bsh_smm_s2_defconfig
index 657eb35..a9c0297 100644
--- a/configs/imx8mn_bsh_smm_s2_defconfig
+++ b/configs/imx8mn_bsh_smm_s2_defconfig
@@ -43,7 +43,7 @@
CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x300
CONFIG_SPL_DMA=y
CONFIG_SPL_I2C=y
-CONFIG_SPL_MTD_SUPPORT=y
+CONFIG_SPL_MTD=y
CONFIG_SPL_NAND_SUPPORT=y
CONFIG_SPL_NAND_BASE=y
CONFIG_SPL_NAND_IDENT=y
diff --git a/configs/j7200_evm_a72_defconfig b/configs/j7200_evm_a72_defconfig
index cb4a141..c0f31f5 100644
--- a/configs/j7200_evm_a72_defconfig
+++ b/configs/j7200_evm_a72_defconfig
@@ -29,10 +29,11 @@
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
CONFIG_SPL_LOAD_FIT=y
CONFIG_SPL_LOAD_FIT_ADDRESS=0x81000000
-CONFIG_DISTRO_DEFAULTS=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_OF_SYSTEM_SETUP=y
-CONFIG_BOOTCOMMAND="run envboot; run distro_bootcmd;"
+CONFIG_BOOTSTD_FULL=y
+CONFIG_BOOTSTD_DEFAULTS=y
+CONFIG_BOOTCOMMAND="run envboot; bootflow scan -lb"
CONFIG_LOGLEVEL=7
CONFIG_SPL_MAX_SIZE=0xc0000
CONFIG_SPL_HAS_BSS_LINKER_SECTION=y
@@ -50,7 +51,7 @@
CONFIG_SPL_FS_LOAD_PAYLOAD_NAME="u-boot.img"
CONFIG_SPL_I2C=y
CONFIG_SPL_DM_MAILBOX=y
-CONFIG_SPL_MTD_SUPPORT=y
+CONFIG_SPL_MTD=y
CONFIG_SPL_DM_SPI_FLASH=y
CONFIG_SPL_NOR_SUPPORT=y
CONFIG_SPL_DM_RESET=y
@@ -138,7 +139,6 @@
CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y
CONFIG_FLASH_CFI_MTD=y
CONFIG_SYS_FLASH_CFI=y
-CONFIG_HBMC_AM654=y
CONFIG_SYS_MAX_FLASH_BANKS_DETECT=y
CONFIG_DM_SPI_FLASH=y
CONFIG_SPI_FLASH_STMICRO=y
diff --git a/configs/j7200_evm_r5_defconfig b/configs/j7200_evm_r5_defconfig
index d25dd81..069b2ac 100644
--- a/configs/j7200_evm_r5_defconfig
+++ b/configs/j7200_evm_r5_defconfig
@@ -48,7 +48,7 @@
CONFIG_SPL_FS_EXT4=y
CONFIG_SPL_I2C=y
CONFIG_SPL_DM_MAILBOX=y
-CONFIG_SPL_MTD_SUPPORT=y
+CONFIG_SPL_MTD=y
CONFIG_SPL_DM_SPI_FLASH=y
CONFIG_SPL_NOR_SUPPORT=y
CONFIG_SPL_DM_RESET=y
@@ -114,7 +114,6 @@
CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y
CONFIG_FLASH_CFI_MTD=y
CONFIG_SYS_FLASH_CFI=y
-CONFIG_HBMC_AM654=y
CONFIG_SYS_MAX_FLASH_BANKS_DETECT=y
CONFIG_DM_SPI_FLASH=y
CONFIG_SPI_FLASH_SFDP_SUPPORT=y
diff --git a/configs/j721e_beagleboneai64_a72_defconfig b/configs/j721e_beagleboneai64_a72_defconfig
new file mode 100644
index 0000000..9e16c98
--- /dev/null
+++ b/configs/j721e_beagleboneai64_a72_defconfig
@@ -0,0 +1,171 @@
+CONFIG_ARM=y
+CONFIG_ARCH_K3=y
+CONFIG_SYS_MALLOC_LEN=0x2000000
+CONFIG_SYS_MALLOC_F_LEN=0x8000
+CONFIG_SPL_GPIO=y
+CONFIG_SPL_LIBCOMMON_SUPPORT=y
+CONFIG_SPL_LIBGENERIC_SUPPORT=y
+CONFIG_NR_DRAM_BANKS=2
+CONFIG_SOC_K3_J721E=y
+CONFIG_TARGET_J721E_A72_BEAGLEBONEAI64=y
+CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y
+CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x80480000
+CONFIG_ENV_SIZE=0x20000
+CONFIG_DM_GPIO=y
+CONFIG_SPL_DM_SPI=y
+CONFIG_DEFAULT_DEVICE_TREE="k3-j721e-beagleboneai64"
+CONFIG_SPL_TEXT_BASE=0x80080000
+CONFIG_OF_LIBFDT_OVERLAY=y
+CONFIG_DM_RESET=y
+CONFIG_SPL_MMC=y
+CONFIG_SPL_SERIAL=y
+CONFIG_SPL_DRIVERS_MISC=y
+CONFIG_SPL_STACK_R_ADDR=0x82000000
+CONFIG_SPL_FS_FAT=y
+CONFIG_SPL_LIBDISK_SUPPORT=y
+# CONFIG_PSCI_RESET is not set
+# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
+CONFIG_SPL_LOAD_FIT=y
+CONFIG_SPL_LOAD_FIT_ADDRESS=0x81000000
+CONFIG_BOOTSTD_FULL=y
+CONFIG_BOOTSTD_DEFAULTS=y
+CONFIG_AUTOBOOT_KEYED=y
+CONFIG_AUTOBOOT_PROMPT="Press SPACE to abort autoboot in %d seconds\n"
+CONFIG_AUTOBOOT_DELAY_STR="d"
+CONFIG_AUTOBOOT_STOP_STR=" "
+CONFIG_OF_SYSTEM_SETUP=y
+CONFIG_BOOTCOMMAND="run set_led_state_start_load;run findfdt; run envboot; bootflow scan -lb;run set_led_state_fail_load"
+CONFIG_LOGLEVEL=7
+CONFIG_SPL_MAX_SIZE=0xc0000
+CONFIG_SPL_HAS_BSS_LINKER_SECTION=y
+CONFIG_SPL_BSS_START_ADDR=0x80a00000
+CONFIG_SPL_BSS_MAX_SIZE=0x80000
+CONFIG_SPL_SYS_MALLOC_SIMPLE=y
+CONFIG_SPL_STACK_R=y
+CONFIG_SPL_SYS_MALLOC=y
+CONFIG_SPL_SYS_MALLOC_SIZE=0x800000
+CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR=y
+CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x1400
+CONFIG_SPL_DMA=y
+CONFIG_SPL_ENV_SUPPORT=y
+CONFIG_SPL_FS_LOAD_PAYLOAD_NAME="u-boot.img"
+CONFIG_SPL_I2C=y
+CONFIG_SPL_DM_MAILBOX=y
+CONFIG_SPL_MTD_SUPPORT=y
+CONFIG_SPL_NOR_SUPPORT=y
+CONFIG_SPL_DM_RESET=y
+CONFIG_SPL_POWER_DOMAIN=y
+CONFIG_SPL_RAM_SUPPORT=y
+CONFIG_SPL_RAM_DEVICE=y
+CONFIG_SYS_SPI_U_BOOT_OFFS=0x280000
+CONFIG_SPL_YMODEM_SUPPORT=y
+CONFIG_SYS_MAXARGS=64
+CONFIG_CMD_ASKENV=y
+CONFIG_CMD_DFU=y
+CONFIG_CMD_GPIO=y
+CONFIG_CMD_GPIO_READ=y
+CONFIG_CMD_GPT=y
+CONFIG_CMD_I2C=y
+CONFIG_CMD_MMC=y
+CONFIG_CMD_REMOTEPROC=y
+CONFIG_CMD_USB=y
+CONFIG_CMD_USB_MASS_STORAGE=y
+CONFIG_CMD_TIME=y
+CONFIG_CMD_EXT4_WRITE=y
+CONFIG_MMC_SPEED_MODE_SET=y
+# CONFIG_ISO_PARTITION is not set
+# CONFIG_SPL_EFI_PARTITION is not set
+CONFIG_OF_CONTROL=y
+CONFIG_SPL_OF_CONTROL=y
+CONFIG_MULTI_DTB_FIT=y
+CONFIG_SPL_MULTI_DTB_FIT=y
+CONFIG_SPL_MULTI_DTB_FIT_NO_COMPRESSION=y
+CONFIG_SYS_REDUNDAND_ENVIRONMENT=y
+CONFIG_SYS_RELOC_GD_ENV_ADDR=y
+CONFIG_NET_RANDOM_ETHADDR=y
+CONFIG_SPL_DM=y
+CONFIG_SPL_DM_SEQ_ALIAS=y
+CONFIG_REGMAP=y
+CONFIG_SPL_REGMAP=y
+CONFIG_SPL_SYSCON=y
+CONFIG_SPL_OF_TRANSLATE=y
+CONFIG_CLK=y
+CONFIG_SPL_CLK=y
+CONFIG_CLK_TI_SCI=y
+CONFIG_DFU_MMC=y
+CONFIG_DFU_RAM=y
+CONFIG_SYS_DFU_DATA_BUF_SIZE=0x20000
+CONFIG_SYS_DFU_MAX_FILE_SIZE=0x800000
+CONFIG_DMA_CHANNELS=y
+CONFIG_TI_K3_NAVSS_UDMA=y
+CONFIG_USB_FUNCTION_FASTBOOT=y
+CONFIG_FASTBOOT_BUF_ADDR=0x82000000
+CONFIG_FASTBOOT_BUF_SIZE=0x2F000000
+CONFIG_FASTBOOT_FLASH=y
+CONFIG_FASTBOOT_FLASH_MMC_DEV=0
+CONFIG_FASTBOOT_CMD_OEM_FORMAT=y
+CONFIG_TI_SCI_PROTOCOL=y
+CONFIG_DA8XX_GPIO=y
+CONFIG_DM_I2C=y
+CONFIG_DM_I2C_GPIO=y
+CONFIG_SYS_I2C_OMAP24XX=y
+CONFIG_LED=y
+CONFIG_SPL_LED=y
+CONFIG_LED_GPIO=y
+CONFIG_SPL_LED_GPIO=y
+CONFIG_DM_MAILBOX=y
+CONFIG_K3_SEC_PROXY=y
+CONFIG_MMC_IO_VOLTAGE=y
+CONFIG_MMC_UHS_SUPPORT=y
+CONFIG_MMC_HS200_SUPPORT=y
+CONFIG_MMC_SDHCI=y
+CONFIG_MMC_SDHCI_ADMA=y
+CONFIG_SPL_MMC_SDHCI_ADMA=y
+CONFIG_MMC_SDHCI_AM654=y
+CONFIG_MTD_UBI=y
+CONFIG_MULTIPLEXER=y
+CONFIG_MUX_MMIO=y
+CONFIG_PHY_TI_DP83867=y
+CONFIG_PHY_FIXED=y
+CONFIG_TI_AM65_CPSW_NUSS=y
+CONFIG_PHY=y
+CONFIG_SPL_PHY=y
+CONFIG_PINCTRL=y
+# CONFIG_PINCTRL_GENERIC is not set
+CONFIG_SPL_PINCTRL=y
+# CONFIG_SPL_PINCTRL_GENERIC is not set
+CONFIG_PINCTRL_SINGLE=y
+CONFIG_POWER_DOMAIN=y
+CONFIG_TI_SCI_POWER_DOMAIN=y
+CONFIG_DM_REGULATOR=y
+CONFIG_DM_REGULATOR_FIXED=y
+CONFIG_DM_REGULATOR_GPIO=y
+CONFIG_RAM=y
+CONFIG_SPL_RAM=y
+CONFIG_REMOTEPROC_TI_K3_DSP=y
+CONFIG_REMOTEPROC_TI_K3_R5F=y
+CONFIG_RESET_TI_SCI=y
+CONFIG_SCSI=y
+CONFIG_DM_SCSI=y
+CONFIG_DM_SERIAL=y
+CONFIG_SOC_DEVICE=y
+CONFIG_SOC_DEVICE_TI_K3=y
+CONFIG_SOC_TI=y
+CONFIG_SYSRESET=y
+CONFIG_SPL_SYSRESET=y
+CONFIG_SYSRESET_TI_SCI=y
+CONFIG_USB=y
+CONFIG_DM_USB_GADGET=y
+CONFIG_SPL_DM_USB_GADGET=y
+CONFIG_USB_XHCI_HCD=y
+CONFIG_USB_CDNS3=y
+CONFIG_USB_CDNS3_GADGET=y
+CONFIG_USB_CDNS3_HOST=y
+CONFIG_SPL_USB_CDNS3_GADGET=y
+CONFIG_USB_GADGET=y
+CONFIG_SPL_USB_GADGET=y
+CONFIG_USB_GADGET_MANUFACTURER="Texas Instruments"
+CONFIG_USB_GADGET_VENDOR_NUM=0x0451
+CONFIG_USB_GADGET_PRODUCT_NUM=0x6163
+CONFIG_SPL_DFU=y
+CONFIG_LZO=y
diff --git a/configs/j721e_beagleboneai64_r5_defconfig b/configs/j721e_beagleboneai64_r5_defconfig
new file mode 100644
index 0000000..5e6ad7b
--- /dev/null
+++ b/configs/j721e_beagleboneai64_r5_defconfig
@@ -0,0 +1,131 @@
+CONFIG_ARM=y
+CONFIG_ARCH_K3=y
+CONFIG_SYS_MALLOC_LEN=0x2000000
+CONFIG_SYS_MALLOC_F_LEN=0x70000
+CONFIG_SPL_GPIO=y
+CONFIG_SPL_LIBCOMMON_SUPPORT=y
+CONFIG_SPL_LIBGENERIC_SUPPORT=y
+CONFIG_SOC_K3_J721E=y
+CONFIG_K3_EARLY_CONS=y
+CONFIG_TARGET_J721E_R5_BEAGLEBONEAI64=y
+CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y
+CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x41cf59f0
+CONFIG_ENV_SIZE=0x20000
+CONFIG_DM_GPIO=y
+CONFIG_DEFAULT_DEVICE_TREE="k3-j721e-r5-beagleboneai64"
+CONFIG_SPL_TEXT_BASE=0x41c00000
+CONFIG_DM_RESET=y
+CONFIG_SPL_MMC=y
+CONFIG_SPL_SERIAL=y
+CONFIG_SPL_DRIVERS_MISC=y
+CONFIG_SPL_STACK_R_ADDR=0x82000000
+CONFIG_SPL_SIZE_LIMIT=0xf59f0
+CONFIG_SPL_SIZE_LIMIT_PROVIDE_STACK=0x4000
+CONFIG_SPL_FS_FAT=y
+CONFIG_SPL_LIBDISK_SUPPORT=y
+# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
+CONFIG_SPL_LOAD_FIT=y
+CONFIG_SPL_LOAD_FIT_ADDRESS=0x80080000
+CONFIG_USE_BOOTCOMMAND=y
+# CONFIG_DISPLAY_CPUINFO is not set
+CONFIG_SPL_SIZE_LIMIT_SUBTRACT_GD=y
+CONFIG_SPL_SIZE_LIMIT_SUBTRACT_MALLOC=y
+CONFIG_SPL_MAX_SIZE=0xf59f0
+CONFIG_SPL_HAS_BSS_LINKER_SECTION=y
+CONFIG_SPL_BSS_START_ADDR=0x41cf59f0
+CONFIG_SPL_BSS_MAX_SIZE=0xa000
+CONFIG_SPL_STACK_R=y
+CONFIG_SPL_SEPARATE_BSS=y
+CONFIG_SPL_SYS_MALLOC=y
+CONFIG_SPL_HAS_CUSTOM_MALLOC_START=y
+CONFIG_SPL_CUSTOM_SYS_MALLOC_ADDR=0x84000000
+CONFIG_SPL_SYS_MALLOC_SIZE=0x1000000
+CONFIG_SPL_EARLY_BSS=y
+CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR=y
+CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x400
+CONFIG_SPL_DMA=y
+CONFIG_SPL_ENV_SUPPORT=y
+CONFIG_SPL_FS_EXT4=y
+CONFIG_SPL_I2C=y
+CONFIG_SPL_DM_MAILBOX=y
+CONFIG_SPL_DM_RESET=y
+CONFIG_SPL_POWER_DOMAIN=y
+CONFIG_SPL_RAM_SUPPORT=y
+CONFIG_SPL_RAM_DEVICE=y
+CONFIG_SPL_REMOTEPROC=y
+CONFIG_SPL_YMODEM_SUPPORT=y
+CONFIG_HUSH_PARSER=y
+CONFIG_SYS_MAXARGS=64
+CONFIG_SYS_BOOTM_LEN=0x4000000
+CONFIG_CMD_DFU=y
+CONFIG_CMD_GPT=y
+CONFIG_CMD_MMC=y
+CONFIG_CMD_REMOTEPROC=y
+# CONFIG_CMD_SETEXPR is not set
+CONFIG_CMD_TIME=y
+CONFIG_CMD_FAT=y
+CONFIG_OF_CONTROL=y
+CONFIG_SPL_OF_CONTROL=y
+CONFIG_OF_LIST="k3-j721e-r5-common-proc-board"
+CONFIG_SPL_MULTI_DTB_FIT=y
+CONFIG_SPL_OF_LIST="k3-j721e-r5-beagleboneai64"
+CONFIG_SPL_MULTI_DTB_FIT_NO_COMPRESSION=y
+CONFIG_ENV_OVERWRITE=y
+CONFIG_SYS_RELOC_GD_ENV_ADDR=y
+CONFIG_SPL_DM=y
+CONFIG_SPL_DM_SEQ_ALIAS=y
+CONFIG_REGMAP=y
+CONFIG_SPL_REGMAP=y
+CONFIG_SYSCON=y
+CONFIG_SPL_SYSCON=y
+CONFIG_SPL_OF_TRANSLATE=y
+CONFIG_CLK=y
+CONFIG_SPL_CLK=y
+CONFIG_SPL_CLK_CCF=y
+CONFIG_SPL_CLK_K3_PLL=y
+CONFIG_SPL_CLK_K3=y
+CONFIG_SYS_DFU_DATA_BUF_SIZE=0x5000
+CONFIG_DMA_CHANNELS=y
+CONFIG_TI_K3_NAVSS_UDMA=y
+CONFIG_TI_SCI_PROTOCOL=y
+CONFIG_DA8XX_GPIO=y
+CONFIG_DM_I2C=y
+CONFIG_I2C_SET_DEFAULT_BUS_NUM=y
+CONFIG_SYS_I2C_OMAP24XX=y
+CONFIG_DM_MAILBOX=y
+CONFIG_K3_SEC_PROXY=y
+CONFIG_FS_LOADER=y
+CONFIG_SPL_FS_LOADER=y
+CONFIG_SPL_MMC_HS200_SUPPORT=y
+CONFIG_MMC_SDHCI=y
+CONFIG_SPL_MMC_SDHCI_ADMA=y
+CONFIG_MMC_SDHCI_AM654=y
+CONFIG_PINCTRL=y
+# CONFIG_PINCTRL_GENERIC is not set
+CONFIG_SPL_PINCTRL=y
+# CONFIG_SPL_PINCTRL_GENERIC is not set
+CONFIG_PINCTRL_SINGLE=y
+CONFIG_POWER_DOMAIN=y
+CONFIG_TI_POWER_DOMAIN=y
+CONFIG_DM_PMIC=y
+CONFIG_PMIC_TPS65941=y
+CONFIG_DM_REGULATOR=y
+CONFIG_SPL_DM_REGULATOR=y
+CONFIG_DM_REGULATOR_TPS65941=y
+CONFIG_K3_SYSTEM_CONTROLLER=y
+CONFIG_REMOTEPROC_TI_K3_ARM64=y
+CONFIG_RESET_TI_SCI=y
+CONFIG_DM_SERIAL=y
+CONFIG_SOC_DEVICE=y
+CONFIG_SOC_DEVICE_TI_K3=y
+CONFIG_SOC_TI=y
+CONFIG_SYSRESET=y
+CONFIG_SPL_SYSRESET=y
+CONFIG_SYSRESET_TI_SCI=y
+CONFIG_TIMER=y
+CONFIG_SPL_TIMER=y
+CONFIG_OMAP_TIMER=y
+CONFIG_FS_EXT4=y
+CONFIG_FS_FAT_MAX_CLUSTSIZE=16384
+CONFIG_LIB_RATIONAL=y
+CONFIG_SPL_LIB_RATIONAL=y
diff --git a/configs/j721e_evm_a72_defconfig b/configs/j721e_evm_a72_defconfig
index 99e0e16..82fa1b1 100644
--- a/configs/j721e_evm_a72_defconfig
+++ b/configs/j721e_evm_a72_defconfig
@@ -29,10 +29,11 @@
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
CONFIG_SPL_LOAD_FIT=y
CONFIG_SPL_LOAD_FIT_ADDRESS=0x81000000
-CONFIG_DISTRO_DEFAULTS=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_OF_SYSTEM_SETUP=y
-CONFIG_BOOTCOMMAND="run envboot; run distro_bootcmd;"
+CONFIG_BOOTSTD_FULL=y
+CONFIG_BOOTSTD_DEFAULTS=y
+CONFIG_BOOTCOMMAND="run envboot; bootflow scan -lb"
CONFIG_LOGLEVEL=7
CONFIG_SPL_MAX_SIZE=0xc0000
CONFIG_SPL_HAS_BSS_LINKER_SECTION=y
@@ -50,7 +51,7 @@
CONFIG_SPL_FS_LOAD_PAYLOAD_NAME="u-boot.img"
CONFIG_SPL_I2C=y
CONFIG_SPL_DM_MAILBOX=y
-CONFIG_SPL_MTD_SUPPORT=y
+CONFIG_SPL_MTD=y
CONFIG_SPL_DM_SPI_FLASH=y
CONFIG_SPL_NOR_SUPPORT=y
CONFIG_SPL_DM_RESET=y
diff --git a/configs/j721e_evm_r5_defconfig b/configs/j721e_evm_r5_defconfig
index e76ab59..55169bb 100644
--- a/configs/j721e_evm_r5_defconfig
+++ b/configs/j721e_evm_r5_defconfig
@@ -53,7 +53,7 @@
CONFIG_SPL_FS_EXT4=y
CONFIG_SPL_I2C=y
CONFIG_SPL_DM_MAILBOX=y
-CONFIG_SPL_MTD_SUPPORT=y
+CONFIG_SPL_MTD=y
CONFIG_SPL_DM_SPI_FLASH=y
CONFIG_SPL_NOR_SUPPORT=y
CONFIG_SPL_DM_RESET=y
diff --git a/configs/j721s2_evm_a72_defconfig b/configs/j721s2_evm_a72_defconfig
index 876f078..a7adb92 100644
--- a/configs/j721s2_evm_a72_defconfig
+++ b/configs/j721s2_evm_a72_defconfig
@@ -49,7 +49,7 @@
CONFIG_SPL_FS_LOAD_PAYLOAD_NAME="u-boot.img"
CONFIG_SPL_I2C=y
CONFIG_SPL_DM_MAILBOX=y
-CONFIG_SPL_MTD_SUPPORT=y
+CONFIG_SPL_MTD=y
CONFIG_SPL_DM_SPI_FLASH=y
CONFIG_SPL_NOR_SUPPORT=y
CONFIG_SPL_DM_RESET=y
diff --git a/configs/j721s2_evm_r5_defconfig b/configs/j721s2_evm_r5_defconfig
index 4990e27..c0fdd86 100644
--- a/configs/j721s2_evm_r5_defconfig
+++ b/configs/j721s2_evm_r5_defconfig
@@ -55,7 +55,7 @@
CONFIG_SPL_FS_EXT4=y
CONFIG_SPL_I2C=y
CONFIG_SPL_DM_MAILBOX=y
-CONFIG_SPL_MTD_SUPPORT=y
+CONFIG_SPL_MTD=y
CONFIG_SPL_DM_SPI_FLASH=y
CONFIG_SPL_NOR_SUPPORT=y
CONFIG_SPL_DM_RESET=y
diff --git a/configs/m53menlo_defconfig b/configs/m53menlo_defconfig
index ef9e15d..e1ddc0a 100644
--- a/configs/m53menlo_defconfig
+++ b/configs/m53menlo_defconfig
@@ -90,7 +90,6 @@
CONFIG_NAND_MXC=y
CONFIG_MXC_NAND_HWECC=y
CONFIG_SYS_NAND_BLOCK_SIZE=0x20000
-CONFIG_SYS_NAND_PAGE_COUNT=0x40
CONFIG_SYS_NAND_PAGE_SIZE=0x800
CONFIG_SYS_NAND_OOBSIZE=0x40
CONFIG_SYS_NAND_U_BOOT_LOCATIONS=y
diff --git a/configs/mk808_defconfig b/configs/mk808_defconfig
index bf851cb..70b1032 100644
--- a/configs/mk808_defconfig
+++ b/configs/mk808_defconfig
@@ -70,7 +70,6 @@
CONFIG_SYS_RELOC_GD_ENV_ADDR=y
# CONFIG_NET is not set
CONFIG_TPL_DM=y
-# CONFIG_DM_WARN is not set
CONFIG_REGMAP=y
CONFIG_SPL_REGMAP=y
CONFIG_TPL_REGMAP=y
diff --git a/configs/mvebu_db-88f3720_defconfig b/configs/mvebu_db-88f3720_defconfig
index 8295670..51518cf 100644
--- a/configs/mvebu_db-88f3720_defconfig
+++ b/configs/mvebu_db-88f3720_defconfig
@@ -69,6 +69,7 @@
CONFIG_MVEBU_COMPHY_SUPPORT=y
CONFIG_PINCTRL=y
CONFIG_PINCTRL_ARMADA_37XX=y
+CONFIG_DEFAULT_ENV_IS_RW=y
CONFIG_MVEBU_A3700_UART=y
CONFIG_MVEBU_A3700_SPI=y
CONFIG_USB=y
diff --git a/configs/mvebu_espressobin-88f3720_defconfig b/configs/mvebu_espressobin-88f3720_defconfig
index 6c68c23..227607a 100644
--- a/configs/mvebu_espressobin-88f3720_defconfig
+++ b/configs/mvebu_espressobin-88f3720_defconfig
@@ -88,6 +88,7 @@
CONFIG_PINCTRL=y
CONFIG_PINCTRL_ARMADA_37XX=y
CONFIG_DM_REGULATOR_GPIO=y
+CONFIG_DEFAULT_ENV_IS_RW=y
CONFIG_MVEBU_A3700_UART=y
CONFIG_MVEBU_A3700_SPI=y
CONFIG_USB=y
diff --git a/configs/neu2-io-rv1126_defconfig b/configs/neu2-io-rv1126_defconfig
index f02c38c..2fb5a84 100644
--- a/configs/neu2-io-rv1126_defconfig
+++ b/configs/neu2-io-rv1126_defconfig
@@ -17,7 +17,6 @@
CONFIG_DEFAULT_FDT_FILE="rv1126-edgeble-neu2-io.dtb"
# CONFIG_DISPLAY_CPUINFO is not set
CONFIG_DISPLAY_BOARDINFO_LATE=y
-CONFIG_MISC_INIT_R=y
CONFIG_SPL_PAD_TO=0x7f8000
CONFIG_SPL_NO_BSS_LIMIT=y
# CONFIG_SPL_RAW_IMAGE_SUPPORT is not set
diff --git a/configs/nsa325_defconfig b/configs/nsa325_defconfig
index 539fcc4..1f05d3b 100644
--- a/configs/nsa325_defconfig
+++ b/configs/nsa325_defconfig
@@ -56,7 +56,6 @@
CONFIG_VERSION_VARIABLE=y
CONFIG_NET_RANDOM_ETHADDR=y
CONFIG_NETCONSOLE=y
-# CONFIG_DM_WARN is not set
CONFIG_SATA_MV=y
CONFIG_SYS_SATA_MAX_DEVICE=2
CONFIG_LBA48=y
diff --git a/configs/omap35_logic_defconfig b/configs/omap35_logic_defconfig
index 539b0cf..5040af0 100644
--- a/configs/omap35_logic_defconfig
+++ b/configs/omap35_logic_defconfig
@@ -30,7 +30,7 @@
# CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR is not set
# CONFIG_SPL_FS_EXT4 is not set
# CONFIG_SPL_I2C is not set
-CONFIG_SPL_MTD_SUPPORT=y
+CONFIG_SPL_MTD=y
CONFIG_SPL_NAND_DRIVERS=y
CONFIG_SPL_NAND_ECC=y
CONFIG_SPL_NAND_SIMPLE=y
@@ -74,7 +74,6 @@
CONFIG_MTD_RAW_NAND=y
CONFIG_NAND_OMAP_ECCSCHEME_BCH8_CODE_HW_DETECTION_SW=y
CONFIG_SYS_NAND_BLOCK_SIZE=0x20000
-CONFIG_SYS_NAND_PAGE_COUNT=0x40
CONFIG_SYS_NAND_PAGE_SIZE=0x800
CONFIG_SYS_NAND_OOBSIZE=0x40
CONFIG_SYS_NAND_BUSWIDTH_16BIT=y
diff --git a/configs/omap35_logic_somlv_defconfig b/configs/omap35_logic_somlv_defconfig
index f14ce3d..1ea35c7 100644
--- a/configs/omap35_logic_somlv_defconfig
+++ b/configs/omap35_logic_somlv_defconfig
@@ -31,7 +31,7 @@
# CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR is not set
# CONFIG_SPL_FS_EXT4 is not set
# CONFIG_SPL_I2C is not set
-CONFIG_SPL_MTD_SUPPORT=y
+CONFIG_SPL_MTD=y
CONFIG_SPL_NAND_DRIVERS=y
CONFIG_SPL_NAND_ECC=y
CONFIG_SPL_NAND_SIMPLE=y
@@ -83,7 +83,6 @@
CONFIG_MTD_RAW_NAND=y
CONFIG_NAND_OMAP_ECCSCHEME_BCH8_CODE_HW_DETECTION_SW=y
CONFIG_SYS_NAND_BLOCK_SIZE=0x20000
-CONFIG_SYS_NAND_PAGE_COUNT=0x40
CONFIG_SYS_NAND_PAGE_SIZE=0x800
CONFIG_SYS_NAND_OOBSIZE=0x40
CONFIG_SYS_NAND_BUSWIDTH_16BIT=y
diff --git a/configs/omap3_beagle_defconfig b/configs/omap3_beagle_defconfig
index cabd365..c8c9ae0 100644
--- a/configs/omap3_beagle_defconfig
+++ b/configs/omap3_beagle_defconfig
@@ -22,7 +22,7 @@
CONFIG_SPL_SYS_MALLOC=y
CONFIG_SPL_SYS_MALLOC_SIZE=0x800000
# CONFIG_SPL_FS_EXT4 is not set
-CONFIG_SPL_MTD_SUPPORT=y
+CONFIG_SPL_MTD=y
CONFIG_SPL_NAND_DRIVERS=y
CONFIG_SPL_NAND_ECC=y
CONFIG_SPL_NAND_SIMPLE=y
@@ -83,7 +83,6 @@
CONFIG_MTD_RAW_NAND=y
CONFIG_NAND_OMAP_ECCSCHEME_HAM1_CODE_HW=y
CONFIG_SYS_NAND_BLOCK_SIZE=0x20000
-CONFIG_SYS_NAND_PAGE_COUNT=0x40
CONFIG_SYS_NAND_PAGE_SIZE=0x800
CONFIG_SYS_NAND_OOBSIZE=0x40
CONFIG_SYS_NAND_BUSWIDTH_16BIT=y
diff --git a/configs/omap3_evm_defconfig b/configs/omap3_evm_defconfig
index 33ff39f..93427f3 100644
--- a/configs/omap3_evm_defconfig
+++ b/configs/omap3_evm_defconfig
@@ -22,7 +22,7 @@
CONFIG_SPL_SYS_MALLOC=y
CONFIG_SPL_SYS_MALLOC_SIZE=0x800000
# CONFIG_SPL_FS_EXT4 is not set
-CONFIG_SPL_MTD_SUPPORT=y
+CONFIG_SPL_MTD=y
CONFIG_SPL_NAND_DRIVERS=y
CONFIG_SPL_NAND_ECC=y
CONFIG_SPL_NAND_SIMPLE=y
@@ -74,7 +74,6 @@
CONFIG_MTD_RAW_NAND=y
CONFIG_NAND_OMAP_ECCSCHEME_BCH8_CODE_HW_DETECTION_SW=y
CONFIG_SYS_NAND_BLOCK_SIZE=0x20000
-CONFIG_SYS_NAND_PAGE_COUNT=0x40
CONFIG_SYS_NAND_PAGE_SIZE=0x800
CONFIG_SYS_NAND_OOBSIZE=0x40
CONFIG_SYS_NAND_BUSWIDTH_16BIT=y
diff --git a/configs/omap3_logic_defconfig b/configs/omap3_logic_defconfig
index 7d3d602..729586b 100644
--- a/configs/omap3_logic_defconfig
+++ b/configs/omap3_logic_defconfig
@@ -29,7 +29,7 @@
# CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR is not set
# CONFIG_SPL_FS_EXT4 is not set
# CONFIG_SPL_I2C is not set
-CONFIG_SPL_MTD_SUPPORT=y
+CONFIG_SPL_MTD=y
CONFIG_SPL_NAND_DRIVERS=y
CONFIG_SPL_NAND_ECC=y
CONFIG_SPL_NAND_SIMPLE=y
@@ -73,7 +73,6 @@
CONFIG_MTD_RAW_NAND=y
CONFIG_NAND_OMAP_ECCSCHEME_BCH8_CODE_HW_DETECTION_SW=y
CONFIG_SYS_NAND_BLOCK_SIZE=0x20000
-CONFIG_SYS_NAND_PAGE_COUNT=0x40
CONFIG_SYS_NAND_PAGE_SIZE=0x800
CONFIG_SYS_NAND_OOBSIZE=0x40
CONFIG_SYS_NAND_BUSWIDTH_16BIT=y
diff --git a/configs/omap3_logic_somlv_defconfig b/configs/omap3_logic_somlv_defconfig
index 0141a42..f0f326d 100644
--- a/configs/omap3_logic_somlv_defconfig
+++ b/configs/omap3_logic_somlv_defconfig
@@ -31,7 +31,7 @@
# CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR is not set
# CONFIG_SPL_FS_EXT4 is not set
# CONFIG_SPL_I2C is not set
-CONFIG_SPL_MTD_SUPPORT=y
+CONFIG_SPL_MTD=y
CONFIG_SPL_NAND_DRIVERS=y
CONFIG_SPL_NAND_ECC=y
CONFIG_SPL_NAND_SIMPLE=y
@@ -84,7 +84,6 @@
CONFIG_MTD_RAW_NAND=y
CONFIG_NAND_OMAP_ECCSCHEME_BCH8_CODE_HW_DETECTION_SW=y
CONFIG_SYS_NAND_BLOCK_SIZE=0x20000
-CONFIG_SYS_NAND_PAGE_COUNT=0x40
CONFIG_SYS_NAND_PAGE_SIZE=0x800
CONFIG_SYS_NAND_OOBSIZE=0x40
CONFIG_SYS_NAND_BUSWIDTH_16BIT=y
diff --git a/configs/omapl138_lcdk_defconfig b/configs/omapl138_lcdk_defconfig
index 47feff2..63554d5 100644
--- a/configs/omapl138_lcdk_defconfig
+++ b/configs/omapl138_lcdk_defconfig
@@ -84,7 +84,6 @@
CONFIG_SYS_NAND_USE_FLASH_BBT=y
CONFIG_NAND_DAVINCI=y
CONFIG_SYS_NAND_BLOCK_SIZE=0x20000
-CONFIG_SYS_NAND_PAGE_COUNT=0x40
CONFIG_SYS_NAND_PAGE_SIZE=0x800
CONFIG_SYS_NAND_OOBSIZE=0x40
CONFIG_SYS_NAND_BUSWIDTH_16BIT=y
diff --git a/configs/origen_defconfig b/configs/origen_defconfig
index 3a71d6e..5e55b71 100644
--- a/configs/origen_defconfig
+++ b/configs/origen_defconfig
@@ -35,13 +35,13 @@
CONFIG_CMD_GPT=y
CONFIG_CMD_MMC=y
CONFIG_CMD_USB_MASS_STORAGE=y
-# CONFIG_CMD_NET is not set
CONFIG_CMD_CACHE=y
# CONFIG_CMD_SLEEP is not set
CONFIG_CMD_EXT4_WRITE=y
CONFIG_OF_CONTROL=y
CONFIG_ENV_OVERWRITE=y
CONFIG_SYS_RELOC_GD_ENV_ADDR=y
+# CONFIG_NET is not set
CONFIG_DFU_MMC=y
CONFIG_SYS_DFU_DATA_BUF_SIZE=0x2000000
CONFIG_MMC_DW=y
diff --git a/configs/phycore-am335x-r2-regor_defconfig b/configs/phycore-am335x-r2-regor_defconfig
index 4bdf882..cbfe1cf 100644
--- a/configs/phycore-am335x-r2-regor_defconfig
+++ b/configs/phycore-am335x-r2-regor_defconfig
@@ -28,7 +28,7 @@
CONFIG_SPL_SYS_MALLOC=y
CONFIG_SPL_SYS_MALLOC_SIZE=0x800000
CONFIG_SPL_I2C=y
-CONFIG_SPL_MTD_SUPPORT=y
+CONFIG_SPL_MTD=y
CONFIG_SPL_NAND_DRIVERS=y
CONFIG_SPL_NAND_ECC=y
CONFIG_SPL_NAND_BASE=y
@@ -76,7 +76,6 @@
CONFIG_MTD_RAW_NAND=y
CONFIG_SYS_NAND_BLOCK_SIZE=0x20000
CONFIG_SYS_NAND_ONFI_DETECTION=y
-CONFIG_SYS_NAND_PAGE_COUNT=0x40
CONFIG_SYS_NAND_PAGE_SIZE=0x800
CONFIG_SYS_NAND_OOBSIZE=0x40
CONFIG_SYS_NAND_U_BOOT_LOCATIONS=y
diff --git a/configs/phycore-am335x-r2-wega_defconfig b/configs/phycore-am335x-r2-wega_defconfig
index 7644fbe..b91b966 100644
--- a/configs/phycore-am335x-r2-wega_defconfig
+++ b/configs/phycore-am335x-r2-wega_defconfig
@@ -28,7 +28,7 @@
CONFIG_SPL_SYS_MALLOC=y
CONFIG_SPL_SYS_MALLOC_SIZE=0x800000
CONFIG_SPL_I2C=y
-CONFIG_SPL_MTD_SUPPORT=y
+CONFIG_SPL_MTD=y
CONFIG_SPL_NAND_DRIVERS=y
CONFIG_SPL_NAND_ECC=y
CONFIG_SPL_NAND_BASE=y
@@ -76,7 +76,6 @@
CONFIG_MTD_RAW_NAND=y
CONFIG_SYS_NAND_BLOCK_SIZE=0x20000
CONFIG_SYS_NAND_ONFI_DETECTION=y
-CONFIG_SYS_NAND_PAGE_COUNT=0x40
CONFIG_SYS_NAND_PAGE_SIZE=0x800
CONFIG_SYS_NAND_OOBSIZE=0x40
CONFIG_SYS_NAND_U_BOOT_LOCATIONS=y
diff --git a/configs/pogo_v4_defconfig b/configs/pogo_v4_defconfig
index ff6411d..101f20f 100644
--- a/configs/pogo_v4_defconfig
+++ b/configs/pogo_v4_defconfig
@@ -56,7 +56,6 @@
CONFIG_NET_RANDOM_ETHADDR=y
CONFIG_NETCONSOLE=y
CONFIG_SYS_FAULT_ECHO_LINK_DOWN=y
-# CONFIG_DM_WARN is not set
CONFIG_SATA_MV=y
CONFIG_SYS_SATA_MAX_DEVICE=1
CONFIG_LBA48=y
diff --git a/configs/poplar_defconfig b/configs/poplar_defconfig
index f0ab231..b6e0c31 100644
--- a/configs/poplar_defconfig
+++ b/configs/poplar_defconfig
@@ -22,6 +22,7 @@
# CONFIG_ISO_PARTITION is not set
CONFIG_ENV_IS_IN_MMC=y
CONFIG_SYS_RELOC_GD_ENV_ADDR=y
+CONFIG_NET_RANDOM_ETHADDR=y
CONFIG_USB_FUNCTION_FASTBOOT=y
CONFIG_FASTBOOT_BUF_ADDR=0x20000000
CONFIG_FASTBOOT_BUF_SIZE=0x10000000
diff --git a/configs/pxm2_defconfig b/configs/pxm2_defconfig
index 2ea007d..e1d1066 100644
--- a/configs/pxm2_defconfig
+++ b/configs/pxm2_defconfig
@@ -99,7 +99,6 @@
CONFIG_MTD_RAW_NAND=y
CONFIG_SYS_NAND_BLOCK_SIZE=0x20000
CONFIG_SYS_NAND_ONFI_DETECTION=y
-CONFIG_SYS_NAND_PAGE_COUNT=0x40
CONFIG_SYS_NAND_PAGE_SIZE=0x800
CONFIG_SYS_NAND_OOBSIZE=0x40
CONFIG_SYS_NAND_U_BOOT_LOCATIONS=y
diff --git a/configs/quartzpro64-rk3588_defconfig b/configs/quartzpro64-rk3588_defconfig
new file mode 100644
index 0000000..85af4c4
--- /dev/null
+++ b/configs/quartzpro64-rk3588_defconfig
@@ -0,0 +1,71 @@
+CONFIG_ARM=y
+CONFIG_SKIP_LOWLEVEL_INIT=y
+CONFIG_COUNTER_FREQUENCY=24000000
+CONFIG_ARCH_ROCKCHIP=y
+CONFIG_TEXT_BASE=0x00a00000
+CONFIG_SPL_LIBCOMMON_SUPPORT=y
+CONFIG_SPL_LIBGENERIC_SUPPORT=y
+CONFIG_NR_DRAM_BANKS=2
+CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y
+CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0xc00000
+CONFIG_DEFAULT_DEVICE_TREE="rk3588-quartzpro64"
+CONFIG_ROCKCHIP_RK3588=y
+CONFIG_SPL_ROCKCHIP_COMMON_BOARD=y
+CONFIG_SPL_SERIAL=y
+CONFIG_SPL_STACK_R_ADDR=0x600000
+CONFIG_TARGET_QUARTZPRO64_RK3588=y
+CONFIG_SPL_STACK=0x400000
+CONFIG_DEBUG_UART_BASE=0xFEB50000
+CONFIG_DEBUG_UART_CLOCK=24000000
+CONFIG_SYS_LOAD_ADDR=0xc00800
+CONFIG_DEBUG_UART=y
+CONFIG_FIT=y
+CONFIG_FIT_VERBOSE=y
+CONFIG_SPL_FIT_SIGNATURE=y
+CONFIG_SPL_LOAD_FIT=y
+CONFIG_LEGACY_IMAGE_FORMAT=y
+CONFIG_OF_BOARD_SETUP=y
+CONFIG_DEFAULT_FDT_FILE="rockchip/rk3588-quartzpro64.dtb"
+# CONFIG_DISPLAY_CPUINFO is not set
+CONFIG_DISPLAY_BOARDINFO_LATE=y
+CONFIG_SPL_MAX_SIZE=0x40000
+CONFIG_SPL_PAD_TO=0x7f8000
+CONFIG_SPL_HAS_BSS_LINKER_SECTION=y
+CONFIG_SPL_BSS_START_ADDR=0x4000000
+CONFIG_SPL_BSS_MAX_SIZE=0x4000
+# CONFIG_SPL_RAW_IMAGE_SUPPORT is not set
+# CONFIG_SPL_SHARES_INIT_SP_ADDR is not set
+CONFIG_SPL_STACK_R=y
+CONFIG_SPL_ATF=y
+CONFIG_CMD_GPIO=y
+CONFIG_CMD_GPT=y
+CONFIG_CMD_MMC=y
+# CONFIG_CMD_SETEXPR is not set
+CONFIG_CMD_REGULATOR=y
+# CONFIG_SPL_DOS_PARTITION is not set
+CONFIG_SPL_OF_CONTROL=y
+CONFIG_OF_LIVE=y
+CONFIG_OF_SPL_REMOVE_PROPS="clock-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents"
+CONFIG_SPL_REGMAP=y
+CONFIG_SPL_SYSCON=y
+CONFIG_SPL_CLK=y
+CONFIG_ROCKCHIP_GPIO=y
+CONFIG_SYS_I2C_ROCKCHIP=y
+CONFIG_MISC=y
+CONFIG_SUPPORT_EMMC_RPMB=y
+CONFIG_MMC_DW=y
+CONFIG_MMC_DW_ROCKCHIP=y
+CONFIG_MMC_SDHCI=y
+CONFIG_MMC_SDHCI_SDMA=y
+CONFIG_MMC_SDHCI_ROCKCHIP=y
+CONFIG_PHY_REALTEK=y
+CONFIG_DWC_ETH_QOS=y
+CONFIG_DWC_ETH_QOS_ROCKCHIP=y
+CONFIG_REGULATOR_PWM=y
+CONFIG_PWM_ROCKCHIP=y
+CONFIG_SPL_RAM=y
+CONFIG_BAUDRATE=1500000
+CONFIG_DEBUG_UART_SHIFT=2
+CONFIG_SYS_NS16550_MEM32=y
+CONFIG_SYSRESET=y
+CONFIG_ERRNO_STR=y
diff --git a/configs/ringneck-px30_defconfig b/configs/ringneck-px30_defconfig
index b4666d0..b314636 100644
--- a/configs/ringneck-px30_defconfig
+++ b/configs/ringneck-px30_defconfig
@@ -38,6 +38,7 @@
CONFIG_SPL_HAS_BSS_LINKER_SECTION=y
CONFIG_SPL_BSS_START_ADDR=0x4000000
CONFIG_SPL_BSS_MAX_SIZE=0x4000
+CONFIG_SPL_BOARD_INIT=y
CONFIG_SPL_BOOTROM_SUPPORT=y
# CONFIG_SPL_RAW_IMAGE_SUPPORT is not set
# CONFIG_SPL_SHARES_INIT_SP_ADDR is not set
@@ -53,6 +54,7 @@
# CONFIG_CMD_LZMADEC is not set
# CONFIG_CMD_UNZIP is not set
CONFIG_CMD_GPT=y
+CONFIG_CMD_I2C=y
# CONFIG_CMD_LOADB is not set
# CONFIG_CMD_LOADS is not set
CONFIG_CMD_MMC=y
diff --git a/configs/rut_defconfig b/configs/rut_defconfig
index ccf2566..248073b 100644
--- a/configs/rut_defconfig
+++ b/configs/rut_defconfig
@@ -99,7 +99,6 @@
CONFIG_MTD_RAW_NAND=y
CONFIG_SYS_NAND_BLOCK_SIZE=0x20000
CONFIG_SYS_NAND_ONFI_DETECTION=y
-CONFIG_SYS_NAND_PAGE_COUNT=0x40
CONFIG_SYS_NAND_PAGE_SIZE=0x800
CONFIG_SYS_NAND_OOBSIZE=0x40
CONFIG_SYS_NAND_U_BOOT_LOCATIONS=y
diff --git a/configs/s5pc210_universal_defconfig b/configs/s5pc210_universal_defconfig
index f585c51..ac236c8 100644
--- a/configs/s5pc210_universal_defconfig
+++ b/configs/s5pc210_universal_defconfig
@@ -33,7 +33,6 @@
CONFIG_CMD_I2C=y
CONFIG_CMD_MMC=y
CONFIG_CMD_USB_MASS_STORAGE=y
-# CONFIG_CMD_NET is not set
CONFIG_CMD_CACHE=y
# CONFIG_CMD_SLEEP is not set
CONFIG_CMD_EXT4_WRITE=y
@@ -42,6 +41,7 @@
CONFIG_ENV_OVERWRITE=y
CONFIG_SYS_RELOC_GD_ENV_ADDR=y
CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y
+# CONFIG_NET is not set
CONFIG_DFU_MMC=y
CONFIG_SYS_DFU_DATA_BUF_SIZE=0x2000000
CONFIG_SYS_I2C_S3C24X0=y
diff --git a/configs/sama5d3_xplained_nandflash_defconfig b/configs/sama5d3_xplained_nandflash_defconfig
index a1b6122..a0802f9 100644
--- a/configs/sama5d3_xplained_nandflash_defconfig
+++ b/configs/sama5d3_xplained_nandflash_defconfig
@@ -86,7 +86,6 @@
CONFIG_SPL_GENERATE_ATMEL_PMECC_HEADER=y
CONFIG_SYS_NAND_BLOCK_SIZE=0x20000
CONFIG_SYS_NAND_ONFI_DETECTION=y
-CONFIG_SYS_NAND_PAGE_COUNT=0x40
CONFIG_SYS_NAND_PAGE_SIZE=0x800
CONFIG_SYS_NAND_OOBSIZE=0x40
CONFIG_SYS_NAND_U_BOOT_LOCATIONS=y
diff --git a/configs/sama5d3xek_nandflash_defconfig b/configs/sama5d3xek_nandflash_defconfig
index 6278a6c..d96bb91 100644
--- a/configs/sama5d3xek_nandflash_defconfig
+++ b/configs/sama5d3xek_nandflash_defconfig
@@ -90,7 +90,6 @@
CONFIG_SPL_GENERATE_ATMEL_PMECC_HEADER=y
CONFIG_SYS_NAND_BLOCK_SIZE=0x20000
CONFIG_SYS_NAND_ONFI_DETECTION=y
-CONFIG_SYS_NAND_PAGE_COUNT=0x40
CONFIG_SYS_NAND_PAGE_SIZE=0x800
CONFIG_SYS_NAND_OOBSIZE=0x40
CONFIG_SYS_NAND_U_BOOT_LOCATIONS=y
diff --git a/configs/sama5d4_xplained_nandflash_defconfig b/configs/sama5d4_xplained_nandflash_defconfig
index d12f749..68101a1 100644
--- a/configs/sama5d4_xplained_nandflash_defconfig
+++ b/configs/sama5d4_xplained_nandflash_defconfig
@@ -84,7 +84,6 @@
CONFIG_SPL_GENERATE_ATMEL_PMECC_HEADER=y
CONFIG_SYS_NAND_BLOCK_SIZE=0x40000
CONFIG_SYS_NAND_ONFI_DETECTION=y
-CONFIG_SYS_NAND_PAGE_COUNT=0x40
CONFIG_SYS_NAND_PAGE_SIZE=0x1000
CONFIG_SYS_NAND_OOBSIZE=0xe0
CONFIG_SYS_NAND_U_BOOT_LOCATIONS=y
diff --git a/configs/sama5d4ek_nandflash_defconfig b/configs/sama5d4ek_nandflash_defconfig
index 27bfcdf..b8062db 100644
--- a/configs/sama5d4ek_nandflash_defconfig
+++ b/configs/sama5d4ek_nandflash_defconfig
@@ -81,7 +81,6 @@
CONFIG_SPL_GENERATE_ATMEL_PMECC_HEADER=y
CONFIG_SYS_NAND_BLOCK_SIZE=0x40000
CONFIG_SYS_NAND_ONFI_DETECTION=y
-CONFIG_SYS_NAND_PAGE_COUNT=0x40
CONFIG_SYS_NAND_PAGE_SIZE=0x1000
CONFIG_SYS_NAND_OOBSIZE=0xe0
CONFIG_SYS_NAND_U_BOOT_LOCATIONS=y
diff --git a/configs/sandbox64_defconfig b/configs/sandbox64_defconfig
index 6e80780..a29100e 100644
--- a/configs/sandbox64_defconfig
+++ b/configs/sandbox64_defconfig
@@ -1,4 +1,5 @@
CONFIG_TEXT_BASE=0
+CONFIG_SYS_MALLOC_LEN=0x6000000
CONFIG_NR_DRAM_BANKS=1
CONFIG_ENV_SIZE=0x2000
CONFIG_DEFAULT_DEVICE_TREE="sandbox64"
@@ -49,6 +50,7 @@
CONFIG_CMD_IDE=y
CONFIG_CMD_I2C=y
CONFIG_CMD_LOADM=y
+CONFIG_CMD_MTD=y
CONFIG_CMD_OSD=y
CONFIG_CMD_PCI=y
CONFIG_CMD_READ=y
@@ -166,6 +168,13 @@
CONFIG_I2C_EEPROM=y
CONFIG_MMC_SANDBOX=y
CONFIG_MTD=y
+CONFIG_DM_MTD=y
+CONFIG_MTD_RAW_NAND=y
+CONFIG_SYS_MAX_NAND_DEVICE=8
+CONFIG_SYS_NAND_USE_FLASH_BBT=y
+CONFIG_NAND_SANDBOX=y
+CONFIG_SYS_NAND_ONFI_DETECTION=y
+CONFIG_SYS_NAND_PAGE_SIZE=0x200
CONFIG_SPI_FLASH_SANDBOX=y
CONFIG_BOOTDEV_SPI_FLASH=y
CONFIG_SPI_FLASH_ATMEL=y
@@ -261,6 +270,7 @@
CONFIG_TPM=y
CONFIG_LZ4=y
CONFIG_ERRNO_STR=y
+CONFIG_GETOPT=y
CONFIG_EFI_RUNTIME_UPDATE_CAPSULE=y
CONFIG_EFI_CAPSULE_ON_DISK=y
CONFIG_EFI_CAPSULE_FIRMWARE_RAW=y
diff --git a/configs/sandbox_defconfig b/configs/sandbox_defconfig
index e615656..af3e7d8 100644
--- a/configs/sandbox_defconfig
+++ b/configs/sandbox_defconfig
@@ -1,4 +1,5 @@
CONFIG_TEXT_BASE=0
+CONFIG_SYS_MALLOC_LEN=0x6000000
CONFIG_NR_DRAM_BANKS=1
CONFIG_ENV_SIZE=0x2000
CONFIG_DEFAULT_DEVICE_TREE="sandbox"
@@ -73,6 +74,7 @@
CONFIG_CMD_I2C=y
CONFIG_CMD_LOADM=y
CONFIG_CMD_LSBLK=y
+CONFIG_CMD_MTD=y
CONFIG_CMD_MUX=y
CONFIG_CMD_OSD=y
CONFIG_CMD_PCI=y
@@ -120,6 +122,7 @@
CONFIG_CMD_AES=y
CONFIG_CMD_TPM=y
CONFIG_CMD_TPM_TEST=y
+CONFIG_CMD_SCMI=y
CONFIG_CMD_BTRFS=y
CONFIG_CMD_CBFS=y
CONFIG_CMD_CRAMFS=y
@@ -215,6 +218,13 @@
CONFIG_MMC_SANDBOX=y
CONFIG_MMC_SDHCI=y
CONFIG_MTD=y
+CONFIG_DM_MTD=y
+CONFIG_MTD_RAW_NAND=y
+CONFIG_SYS_MAX_NAND_DEVICE=8
+CONFIG_SYS_NAND_USE_FLASH_BBT=y
+CONFIG_NAND_SANDBOX=y
+CONFIG_SYS_NAND_ONFI_DETECTION=y
+CONFIG_SYS_NAND_PAGE_SIZE=0x200
CONFIG_SPI_FLASH_SANDBOX=y
CONFIG_BOOTDEV_SPI_FLASH=y
CONFIG_SPI_FLASH_ATMEL=y
@@ -338,6 +348,7 @@
CONFIG_ECDSA_VERIFY=y
CONFIG_TPM=y
CONFIG_ERRNO_STR=y
+CONFIG_GETOPT=y
CONFIG_EFI_RUNTIME_UPDATE_CAPSULE=y
CONFIG_EFI_CAPSULE_ON_DISK=y
CONFIG_EFI_CAPSULE_FIRMWARE_RAW=y
diff --git a/configs/sandbox_noinst_defconfig b/configs/sandbox_noinst_defconfig
index 1fd074b..8cfe30b 100644
--- a/configs/sandbox_noinst_defconfig
+++ b/configs/sandbox_noinst_defconfig
@@ -50,6 +50,13 @@
CONFIG_SPL_FS_EXT4=y
CONFIG_SPL_I2C=y
CONFIG_SPL_MMC_WRITE=y
+CONFIG_SPL_MTD=y
+CONFIG_SPL_NAND_SUPPORT=y
+CONFIG_SPL_NAND_DRIVERS=y
+CONFIG_SPL_NAND_ECC=y
+CONFIG_SPL_NAND_SOFTECC=y
+CONFIG_SPL_NAND_BASE=y
+CONFIG_SPL_NAND_IDENT=y
CONFIG_SPL_DM_SPI_FLASH=y
CONFIG_SPL_NET=y
CONFIG_SPL_NOR_SUPPORT=y
@@ -79,6 +86,7 @@
CONFIG_CMD_GPT=y
CONFIG_CMD_IDE=y
CONFIG_CMD_I2C=y
+CONFIG_CMD_MTD=y
CONFIG_CMD_OSD=y
CONFIG_CMD_PCI=y
CONFIG_CMD_REMOTEPROC=y
@@ -179,6 +187,18 @@
CONFIG_SPL_PWRSEQ=y
CONFIG_FS_LOADER=y
CONFIG_MMC_SANDBOX=y
+CONFIG_MTD=y
+CONFIG_DM_MTD=y
+CONFIG_MTD_CONCAT=y
+CONFIG_MTD_RAW_NAND=y
+CONFIG_SYS_MAX_NAND_DEVICE=8
+CONFIG_SYS_NAND_USE_FLASH_BBT=y
+CONFIG_NAND_SANDBOX=y
+CONFIG_SYS_NAND_BLOCK_SIZE=0x2000
+CONFIG_SYS_NAND_ONFI_DETECTION=y
+CONFIG_SYS_NAND_PAGE_SIZE=0x200
+CONFIG_SYS_NAND_U_BOOT_LOCATIONS=y
+CONFIG_SYS_NAND_U_BOOT_OFFS=0x0
CONFIG_SPI_FLASH_SANDBOX=y
CONFIG_SPI_FLASH_ATMEL=y
CONFIG_SPI_FLASH_EON=y
diff --git a/configs/smartweb_defconfig b/configs/smartweb_defconfig
index 10cbccb..80d2c0f 100644
--- a/configs/smartweb_defconfig
+++ b/configs/smartweb_defconfig
@@ -84,7 +84,6 @@
# CONFIG_SYS_NAND_USE_FLASH_BBT is not set
CONFIG_NAND_ATMEL=y
CONFIG_SYS_NAND_BLOCK_SIZE=0x20000
-CONFIG_SYS_NAND_PAGE_COUNT=0x40
CONFIG_SYS_NAND_PAGE_SIZE=0x800
CONFIG_SYS_NAND_OOBSIZE=0x40
CONFIG_SYS_NAND_U_BOOT_LOCATIONS=y
diff --git a/configs/socfpga_secu1_defconfig b/configs/socfpga_secu1_defconfig
index b8052f1..6a4106a 100644
--- a/configs/socfpga_secu1_defconfig
+++ b/configs/socfpga_secu1_defconfig
@@ -43,7 +43,7 @@
# CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR is not set
CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_PARTITION=0x1
# CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_PARTITION_TYPE is not set
-CONFIG_SPL_MTD_SUPPORT=y
+CONFIG_SPL_MTD=y
CONFIG_SPL_NAND_SUPPORT=y
CONFIG_SYS_MAXARGS=32
CONFIG_SYS_BOOTM_LEN=0x4000000
diff --git a/configs/stm32746g-eval_spl_defconfig b/configs/stm32746g-eval_spl_defconfig
index 3864e21..f9711be 100644
--- a/configs/stm32746g-eval_spl_defconfig
+++ b/configs/stm32746g-eval_spl_defconfig
@@ -34,7 +34,7 @@
CONFIG_SPL_NO_BSS_LIMIT=y
CONFIG_SPL_BOARD_INIT=y
CONFIG_SPL_SYS_MALLOC_SIMPLE=y
-CONFIG_SPL_MTD_SUPPORT=y
+CONFIG_SPL_MTD=y
CONFIG_SPL_XIP_SUPPORT=y
CONFIG_SPL_PAYLOAD_ARGS_ADDR=0x80c0000
CONFIG_SPL_DM_RESET=y
diff --git a/configs/stm32f746-disco_spl_defconfig b/configs/stm32f746-disco_spl_defconfig
index b2a7861..a2b740c 100644
--- a/configs/stm32f746-disco_spl_defconfig
+++ b/configs/stm32f746-disco_spl_defconfig
@@ -34,7 +34,7 @@
CONFIG_SPL_NO_BSS_LIMIT=y
CONFIG_SPL_BOARD_INIT=y
CONFIG_SPL_SYS_MALLOC_SIMPLE=y
-CONFIG_SPL_MTD_SUPPORT=y
+CONFIG_SPL_MTD=y
CONFIG_SPL_XIP_SUPPORT=y
CONFIG_SPL_PAYLOAD_ARGS_ADDR=0x80c0000
CONFIG_SPL_DM_RESET=y
diff --git a/configs/stm32f769-disco_spl_defconfig b/configs/stm32f769-disco_spl_defconfig
index 3462203..37d22f8 100644
--- a/configs/stm32f769-disco_spl_defconfig
+++ b/configs/stm32f769-disco_spl_defconfig
@@ -33,7 +33,7 @@
CONFIG_SPL_NO_BSS_LIMIT=y
CONFIG_SPL_BOARD_INIT=y
CONFIG_SPL_SYS_MALLOC_SIMPLE=y
-CONFIG_SPL_MTD_SUPPORT=y
+CONFIG_SPL_MTD=y
CONFIG_SPL_XIP_SUPPORT=y
CONFIG_SPL_PAYLOAD_ARGS_ADDR=0x81c0000
CONFIG_SPL_DM_RESET=y
diff --git a/configs/stm32mp15_basic_defconfig b/configs/stm32mp15_basic_defconfig
index 6df0935..be553ad 100644
--- a/configs/stm32mp15_basic_defconfig
+++ b/configs/stm32mp15_basic_defconfig
@@ -40,7 +40,7 @@
CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_PARTITION=3
CONFIG_SPL_ENV_SUPPORT=y
CONFIG_SPL_I2C=y
-CONFIG_SPL_MTD_SUPPORT=y
+CONFIG_SPL_MTD=y
CONFIG_SPL_DM_SPI_FLASH=y
CONFIG_SPL_POWER=y
CONFIG_SPL_SPI_FLASH_MTD=y
diff --git a/configs/stm32mp15_dhcom_basic_defconfig b/configs/stm32mp15_dhcom_basic_defconfig
index b6cd0a4..f4dbbf3 100644
--- a/configs/stm32mp15_dhcom_basic_defconfig
+++ b/configs/stm32mp15_dhcom_basic_defconfig
@@ -25,6 +25,8 @@
CONFIG_SYS_LOAD_ADDR=0xc2000000
CONFIG_SYS_MEMTEST_START=0xc0000000
CONFIG_SYS_MEMTEST_END=0xc4000000
+CONFIG_HAS_BOARD_SIZE_LIMIT=y
+CONFIG_BOARD_SIZE_LIMIT=1441792
CONFIG_FIT=y
CONFIG_SPL_LOAD_FIT=y
CONFIG_SPL_LOAD_FIT_ADDRESS=0xc1000000
@@ -47,7 +49,7 @@
CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_PARTITION=3
CONFIG_SPL_ENV_SUPPORT=y
CONFIG_SPL_I2C=y
-CONFIG_SPL_MTD_SUPPORT=y
+CONFIG_SPL_MTD=y
CONFIG_SPL_DM_SPI_FLASH=y
CONFIG_SPL_POWER=y
CONFIG_SPL_RAM_SUPPORT=y
@@ -76,7 +78,10 @@
CONFIG_CMD_SPI=y
CONFIG_CMD_USB=y
CONFIG_CMD_USB_MASS_STORAGE=y
+CONFIG_CMD_DHCP6=y
+CONFIG_CMD_TFTPPUT=y
CONFIG_SYS_DISABLE_AUTOLOAD=y
+CONFIG_CMD_WGET=y
CONFIG_CMD_BOOTCOUNT=y
CONFIG_CMD_CACHE=y
CONFIG_CMD_TIME=y
@@ -101,6 +106,8 @@
CONFIG_TFTP_TSIZE=y
CONFIG_USE_SERVERIP=y
CONFIG_SERVERIP="192.168.1.1"
+CONFIG_PROT_TCP_SACK=y
+CONFIG_IPV6=y
CONFIG_STM32_ADC=y
CONFIG_SPL_BLOCK_CACHE=y
CONFIG_BOOTCOUNT_LIMIT=y
diff --git a/configs/stm32mp15_dhcor_basic_defconfig b/configs/stm32mp15_dhcor_basic_defconfig
index d1acf9c..d4ead98 100644
--- a/configs/stm32mp15_dhcor_basic_defconfig
+++ b/configs/stm32mp15_dhcor_basic_defconfig
@@ -23,6 +23,8 @@
CONFIG_SPL_SPI=y
# CONFIG_ARMV7_VIRT is not set
CONFIG_SYS_LOAD_ADDR=0xc2000000
+CONFIG_HAS_BOARD_SIZE_LIMIT=y
+CONFIG_BOARD_SIZE_LIMIT=1441792
CONFIG_FIT=y
CONFIG_SPL_LOAD_FIT=y
CONFIG_SPL_LOAD_FIT_ADDRESS=0xc1000000
@@ -45,7 +47,7 @@
CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_PARTITION=3
CONFIG_SPL_ENV_SUPPORT=y
CONFIG_SPL_I2C=y
-CONFIG_SPL_MTD_SUPPORT=y
+CONFIG_SPL_MTD=y
CONFIG_SPL_DM_SPI_FLASH=y
CONFIG_SPL_POWER=y
CONFIG_SPL_RAM_SUPPORT=y
@@ -74,7 +76,10 @@
CONFIG_CMD_SPI=y
CONFIG_CMD_USB=y
CONFIG_CMD_USB_MASS_STORAGE=y
+CONFIG_CMD_DHCP6=y
+CONFIG_CMD_TFTPPUT=y
CONFIG_SYS_DISABLE_AUTOLOAD=y
+CONFIG_CMD_WGET=y
CONFIG_CMD_BOOTCOUNT=y
CONFIG_CMD_CACHE=y
CONFIG_CMD_TIME=y
@@ -99,6 +104,8 @@
CONFIG_TFTP_TSIZE=y
CONFIG_USE_SERVERIP=y
CONFIG_SERVERIP="192.168.1.1"
+CONFIG_PROT_TCP_SACK=y
+CONFIG_IPV6=y
CONFIG_STM32_ADC=y
CONFIG_SPL_BLOCK_CACHE=y
CONFIG_BOOTCOUNT_LIMIT=y
diff --git a/configs/stm32mp25_defconfig b/configs/stm32mp25_defconfig
index 8423943..75f27c9 100644
--- a/configs/stm32mp25_defconfig
+++ b/configs/stm32mp25_defconfig
@@ -23,7 +23,6 @@
CONFIG_CMD_CLK=y
CONFIG_CMD_GPIO=y
# CONFIG_CMD_LOADB is not set
-# CONFIG_CMD_NET is not set
CONFIG_CMD_CACHE=y
CONFIG_CMD_TIME=y
CONFIG_CMD_RNG=y
@@ -31,6 +30,7 @@
CONFIG_CMD_REGULATOR=y
CONFIG_CMD_LOG=y
CONFIG_OF_LIVE=y
+# CONFIG_NET is not set
CONFIG_GPIO_HOG=y
CONFIG_DM_I2C=y
CONFIG_SYS_I2C_STM32F7=y
diff --git a/configs/taurus_defconfig b/configs/taurus_defconfig
index cc57551..9be30c8 100644
--- a/configs/taurus_defconfig
+++ b/configs/taurus_defconfig
@@ -94,7 +94,6 @@
# CONFIG_SYS_NAND_USE_FLASH_BBT is not set
CONFIG_NAND_ATMEL=y
CONFIG_SYS_NAND_BLOCK_SIZE=0x20000
-CONFIG_SYS_NAND_PAGE_COUNT=0x40
CONFIG_SYS_NAND_PAGE_SIZE=0x800
CONFIG_SYS_NAND_OOBSIZE=0x40
CONFIG_SYS_NAND_U_BOOT_LOCATIONS=y
diff --git a/configs/thunderx_88xx_defconfig b/configs/thunderx_88xx_defconfig
index 5c24b38..0c71b29 100644
--- a/configs/thunderx_88xx_defconfig
+++ b/configs/thunderx_88xx_defconfig
@@ -32,8 +32,8 @@
# CONFIG_CMD_EDITENV is not set
# CONFIG_CMD_SAVEENV is not set
# CONFIG_CMD_ENV_EXISTS is not set
-# CONFIG_CMD_NET is not set
CONFIG_SYS_RELOC_GD_ENV_ADDR=y
+# CONFIG_NET is not set
# CONFIG_MMC is not set
CONFIG_DM_SERIAL=y
CONFIG_DEBUG_UART_SKIP_INIT=y
diff --git a/configs/transformer_t30_defconfig b/configs/transformer_t30_defconfig
index 092c0aa..8d828c1 100644
--- a/configs/transformer_t30_defconfig
+++ b/configs/transformer_t30_defconfig
@@ -45,6 +45,7 @@
CONFIG_CMD_UMS_ABORT_KEYED=y
# CONFIG_CMD_SETEXPR is not set
CONFIG_CMD_PAUSE=y
+CONFIG_CMD_REGULATOR=y
CONFIG_CMD_EXT4_WRITE=y
# CONFIG_SPL_DOS_PARTITION is not set
# CONFIG_SPL_EFI_PARTITION is not set
@@ -65,10 +66,14 @@
CONFIG_I2C_MUX_GPIO=y
CONFIG_BUTTON_KEYBOARD=y
CONFIG_DM_PMIC=y
+CONFIG_DM_PMIC_TPS65910=y
CONFIG_DM_REGULATOR=y
CONFIG_DM_REGULATOR_FIXED=y
+CONFIG_DM_REGULATOR_TPS65911=y
CONFIG_PWM_TEGRA=y
CONFIG_SYS_NS16550=y
+CONFIG_TEGRA20_SLINK=y
+CONFIG_SYSRESET_TPS65910=y
CONFIG_USB=y
CONFIG_USB_EHCI_HCD=y
CONFIG_USB_EHCI_TEGRA=y
diff --git a/configs/trats2_defconfig b/configs/trats2_defconfig
index 6c4909f..045c74f 100644
--- a/configs/trats2_defconfig
+++ b/configs/trats2_defconfig
@@ -36,7 +36,6 @@
CONFIG_CMD_I2C=y
CONFIG_CMD_MMC=y
CONFIG_CMD_USB_MASS_STORAGE=y
-# CONFIG_CMD_NET is not set
CONFIG_CMD_CACHE=y
# CONFIG_CMD_SLEEP is not set
CONFIG_CMD_EXT4_WRITE=y
@@ -44,6 +43,7 @@
CONFIG_ENV_OVERWRITE=y
CONFIG_SYS_RELOC_GD_ENV_ADDR=y
CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y
+# CONFIG_NET is not set
CONFIG_DFU_MMC=y
CONFIG_SYS_DFU_DATA_BUF_SIZE=0x2000000
CONFIG_DM_I2C_GPIO=y
diff --git a/configs/trats_defconfig b/configs/trats_defconfig
index 78484c0..b1adaef 100644
--- a/configs/trats_defconfig
+++ b/configs/trats_defconfig
@@ -35,7 +35,6 @@
CONFIG_CMD_I2C=y
CONFIG_CMD_MMC=y
CONFIG_CMD_USB_MASS_STORAGE=y
-# CONFIG_CMD_NET is not set
CONFIG_CMD_CACHE=y
# CONFIG_CMD_SLEEP is not set
CONFIG_CMD_EXT4_WRITE=y
@@ -43,6 +42,7 @@
CONFIG_ENV_OVERWRITE=y
CONFIG_SYS_RELOC_GD_ENV_ADDR=y
CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y
+# CONFIG_NET is not set
CONFIG_DFU_MMC=y
CONFIG_SYS_DFU_DATA_BUF_SIZE=0x2000000
CONFIG_DM_I2C_GPIO=y
diff --git a/configs/uDPU_defconfig b/configs/uDPU_defconfig
index 988f9ed..d3f1466 100644
--- a/configs/uDPU_defconfig
+++ b/configs/uDPU_defconfig
@@ -81,6 +81,7 @@
CONFIG_DM_REGULATOR_FIXED=y
CONFIG_DM_REGULATOR_GPIO=y
# CONFIG_SCSI is not set
+CONFIG_DEFAULT_ENV_IS_RW=y
CONFIG_MVEBU_A3700_UART=y
CONFIG_MVEBU_A3700_SPI=y
CONFIG_SYSINFO=y
diff --git a/configs/x3_t30_defconfig b/configs/x3_t30_defconfig
index a151f58..90cbc20 100644
--- a/configs/x3_t30_defconfig
+++ b/configs/x3_t30_defconfig
@@ -45,6 +45,7 @@
CONFIG_CMD_UMS_ABORT_KEYED=y
# CONFIG_CMD_SETEXPR is not set
CONFIG_CMD_PAUSE=y
+CONFIG_CMD_REGULATOR=y
CONFIG_CMD_EXT4_WRITE=y
# CONFIG_SPL_DOS_PARTITION is not set
# CONFIG_SPL_EFI_PARTITION is not set
@@ -64,11 +65,14 @@
CONFIG_SYS_I2C_TEGRA=y
CONFIG_BUTTON_KEYBOARD=y
CONFIG_DM_PMIC=y
+CONFIG_DM_PMIC_MAX77663=y
CONFIG_DM_REGULATOR=y
+CONFIG_DM_REGULATOR_MAX77663=y
CONFIG_DM_REGULATOR_FIXED=y
CONFIG_PWM_TEGRA=y
CONFIG_SYS_NS16550=y
CONFIG_TEGRA20_SLINK=y
+CONFIG_SYSRESET_MAX77663=y
CONFIG_USB=y
CONFIG_USB_EHCI_HCD=y
CONFIG_USB_EHCI_TEGRA=y
diff --git a/configs/xilinx_versal_mini_defconfig b/configs/xilinx_versal_mini_defconfig
index d6d6dc1..222da5a 100644
--- a/configs/xilinx_versal_mini_defconfig
+++ b/configs/xilinx_versal_mini_defconfig
@@ -59,7 +59,6 @@
# CONFIG_CMD_SLEEP is not set
CONFIG_SYS_RELOC_GD_ENV_ADDR=y
# CONFIG_NET is not set
-# CONFIG_DM_WARN is not set
# CONFIG_DM_DEVICE_REMOVE is not set
# CONFIG_MMC is not set
CONFIG_ARM_DCC=y
diff --git a/configs/xilinx_versal_mini_emmc0_defconfig b/configs/xilinx_versal_mini_emmc0_defconfig
index 858bb35..1d73790 100644
--- a/configs/xilinx_versal_mini_emmc0_defconfig
+++ b/configs/xilinx_versal_mini_emmc0_defconfig
@@ -57,7 +57,6 @@
CONFIG_OF_EMBED=y
CONFIG_SYS_RELOC_GD_ENV_ADDR=y
# CONFIG_NET is not set
-# CONFIG_DM_WARN is not set
# CONFIG_DM_DEVICE_REMOVE is not set
CONFIG_MMC_SDHCI=y
CONFIG_MMC_SDHCI_ZYNQ=y
diff --git a/configs/xilinx_versal_mini_emmc1_defconfig b/configs/xilinx_versal_mini_emmc1_defconfig
index 2488ede..747f20d 100644
--- a/configs/xilinx_versal_mini_emmc1_defconfig
+++ b/configs/xilinx_versal_mini_emmc1_defconfig
@@ -57,7 +57,6 @@
CONFIG_OF_EMBED=y
CONFIG_SYS_RELOC_GD_ENV_ADDR=y
# CONFIG_NET is not set
-# CONFIG_DM_WARN is not set
# CONFIG_DM_DEVICE_REMOVE is not set
CONFIG_MMC_SDHCI=y
CONFIG_MMC_SDHCI_ZYNQ=y
diff --git a/configs/xilinx_versal_mini_ospi_defconfig b/configs/xilinx_versal_mini_ospi_defconfig
index 389ca50..96be5b9 100644
--- a/configs/xilinx_versal_mini_ospi_defconfig
+++ b/configs/xilinx_versal_mini_ospi_defconfig
@@ -51,12 +51,12 @@
# CONFIG_CMD_SOURCE is not set
# CONFIG_CMD_SETEXPR is not set
# CONFIG_NET is not set
-# CONFIG_DM_WARN is not set
# CONFIG_DM_DEVICE_REMOVE is not set
# CONFIG_MMC is not set
CONFIG_DM_SPI_FLASH=y
CONFIG_SPI_FLASH_SOFT_RESET=y
CONFIG_SPI_FLASH_SOFT_RESET_ON_BOOT=y
+# CONFIG_SPI_FLASH_LOCK is not set
CONFIG_SPI_FLASH_GIGADEVICE=y
CONFIG_SPI_FLASH_ISSI=y
CONFIG_SPI_FLASH_MACRONIX=y
diff --git a/configs/xilinx_versal_mini_qspi_defconfig b/configs/xilinx_versal_mini_qspi_defconfig
index 5724aa3..7181b89 100644
--- a/configs/xilinx_versal_mini_qspi_defconfig
+++ b/configs/xilinx_versal_mini_qspi_defconfig
@@ -53,7 +53,6 @@
# CONFIG_CMD_SETEXPR is not set
# CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG is not set
# CONFIG_NET is not set
-# CONFIG_DM_WARN is not set
# CONFIG_DM_DEVICE_REMOVE is not set
# CONFIG_GPIO is not set
# CONFIG_I2C is not set
@@ -61,6 +60,7 @@
# CONFIG_MMC is not set
CONFIG_DM_SPI_FLASH=y
# CONFIG_SPI_FLASH_SMART_HWCAPS is not set
+# CONFIG_SPI_FLASH_LOCK is not set
# CONFIG_SPI_FLASH_UNLOCK_ALL is not set
CONFIG_SPI_FLASH_GIGADEVICE=y
CONFIG_SPI_FLASH_ISSI=y
diff --git a/configs/xilinx_versal_net_mini_defconfig b/configs/xilinx_versal_net_mini_defconfig
index 3f45630..7dac1ec 100644
--- a/configs/xilinx_versal_net_mini_defconfig
+++ b/configs/xilinx_versal_net_mini_defconfig
@@ -62,7 +62,6 @@
CONFIG_OF_EMBED=y
CONFIG_SYS_RELOC_GD_ENV_ADDR=y
# CONFIG_NET is not set
-# CONFIG_DM_WARN is not set
# CONFIG_DM_DEVICE_REMOVE is not set
# CONFIG_GPIO is not set
# CONFIG_I2C is not set
diff --git a/configs/xilinx_versal_net_mini_emmc_defconfig b/configs/xilinx_versal_net_mini_emmc_defconfig
index 1d79eff..fc88eee 100644
--- a/configs/xilinx_versal_net_mini_emmc_defconfig
+++ b/configs/xilinx_versal_net_mini_emmc_defconfig
@@ -51,7 +51,6 @@
CONFIG_OF_EMBED=y
CONFIG_SYS_RELOC_GD_ENV_ADDR=y
# CONFIG_NET is not set
-# CONFIG_DM_WARN is not set
# CONFIG_DM_DEVICE_REMOVE is not set
CONFIG_MMC_HS200_SUPPORT=y
CONFIG_MMC_SDHCI=y
diff --git a/configs/xilinx_versal_net_mini_ospi_defconfig b/configs/xilinx_versal_net_mini_ospi_defconfig
index 0656b23..1ba6e08 100644
--- a/configs/xilinx_versal_net_mini_ospi_defconfig
+++ b/configs/xilinx_versal_net_mini_ospi_defconfig
@@ -50,12 +50,12 @@
# CONFIG_CMD_SOURCE is not set
# CONFIG_CMD_SETEXPR is not set
# CONFIG_NET is not set
-# CONFIG_DM_WARN is not set
# CONFIG_DM_DEVICE_REMOVE is not set
# CONFIG_MMC is not set
CONFIG_DM_SPI_FLASH=y
CONFIG_SPI_FLASH_SOFT_RESET=y
CONFIG_SPI_FLASH_SOFT_RESET_ON_BOOT=y
+# CONFIG_SPI_FLASH_LOCK is not set
CONFIG_SPI_FLASH_GIGADEVICE=y
CONFIG_SPI_FLASH_ISSI=y
CONFIG_SPI_FLASH_MACRONIX=y
diff --git a/configs/xilinx_versal_net_mini_qspi_defconfig b/configs/xilinx_versal_net_mini_qspi_defconfig
index c0e9ba9..c9497bb 100644
--- a/configs/xilinx_versal_net_mini_qspi_defconfig
+++ b/configs/xilinx_versal_net_mini_qspi_defconfig
@@ -52,7 +52,6 @@
# CONFIG_CMD_SETEXPR is not set
# CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG is not set
# CONFIG_NET is not set
-# CONFIG_DM_WARN is not set
# CONFIG_DM_DEVICE_REMOVE is not set
# CONFIG_GPIO is not set
# CONFIG_I2C is not set
@@ -60,6 +59,7 @@
# CONFIG_MMC is not set
CONFIG_DM_SPI_FLASH=y
# CONFIG_SPI_FLASH_SMART_HWCAPS is not set
+# CONFIG_SPI_FLASH_LOCK is not set
# CONFIG_SPI_FLASH_UNLOCK_ALL is not set
CONFIG_SPI_FLASH_ISSI=y
CONFIG_SPI_FLASH_MACRONIX=y
diff --git a/configs/xilinx_versal_net_virt_defconfig b/configs/xilinx_versal_net_virt_defconfig
index ccc9431..0553ac6 100644
--- a/configs/xilinx_versal_net_virt_defconfig
+++ b/configs/xilinx_versal_net_virt_defconfig
@@ -85,6 +85,7 @@
CONFIG_MMC_UHS_SUPPORT=y
CONFIG_MMC_HS400_SUPPORT=y
CONFIG_MMC_SDHCI=y
+CONFIG_MMC_SDHCI_ADMA=y
CONFIG_MMC_SDHCI_ZYNQ=y
CONFIG_ZYNQ_SDHCI_MIN_FREQ=100000
CONFIG_MTD=y
diff --git a/configs/xilinx_versal_virt_defconfig b/configs/xilinx_versal_virt_defconfig
index b588887..6a2c03c 100644
--- a/configs/xilinx_versal_virt_defconfig
+++ b/configs/xilinx_versal_virt_defconfig
@@ -6,6 +6,7 @@
CONFIG_TEXT_BASE=0x8000000
CONFIG_SYS_MALLOC_F_LEN=0x100000
CONFIG_NR_DRAM_BANKS=36
+CONFIG_SF_DEFAULT_SPEED=30000000
CONFIG_DEFAULT_DEVICE_TREE="xilinx-versal-virt"
CONFIG_OF_LIBFDT_OVERLAY=y
CONFIG_DM_RESET=y
diff --git a/configs/xilinx_zynq_virt_defconfig b/configs/xilinx_zynq_virt_defconfig
index 817fb41..c3ee9be 100644
--- a/configs/xilinx_zynq_virt_defconfig
+++ b/configs/xilinx_zynq_virt_defconfig
@@ -126,6 +126,8 @@
CONFIG_SPI_FLASH_STMICRO=y
CONFIG_SPI_FLASH_SST=y
CONFIG_SPI_FLASH_WINBOND=y
+# CONFIG_SPI_FLASH_USE_4K_SECTORS is not set
+CONFIG_SPI_FLASH_MTD=y
CONFIG_PHY_MARVELL=y
CONFIG_PHY_MICREL=y
CONFIG_PHY_MICREL_KSZ90X1=y
diff --git a/configs/xilinx_zynqmp_mini_defconfig b/configs/xilinx_zynqmp_mini_defconfig
index fc768b6..694fa11 100644
--- a/configs/xilinx_zynqmp_mini_defconfig
+++ b/configs/xilinx_zynqmp_mini_defconfig
@@ -55,7 +55,6 @@
CONFIG_OF_EMBED=y
CONFIG_SYS_RELOC_GD_ENV_ADDR=y
# CONFIG_NET is not set
-# CONFIG_DM_WARN is not set
# CONFIG_DM_DEVICE_REMOVE is not set
# CONFIG_DM_MAILBOX is not set
# CONFIG_MMC is not set
diff --git a/configs/xilinx_zynqmp_mini_emmc0_defconfig b/configs/xilinx_zynqmp_mini_emmc0_defconfig
index 72b1ad4..f81b772 100644
--- a/configs/xilinx_zynqmp_mini_emmc0_defconfig
+++ b/configs/xilinx_zynqmp_mini_emmc0_defconfig
@@ -66,7 +66,6 @@
CONFIG_OF_EMBED=y
CONFIG_SYS_RELOC_GD_ENV_ADDR=y
# CONFIG_NET is not set
-# CONFIG_DM_WARN is not set
# CONFIG_DM_DEVICE_REMOVE is not set
CONFIG_SPL_DM_SEQ_ALIAS=y
# CONFIG_DM_MAILBOX is not set
diff --git a/configs/xilinx_zynqmp_mini_emmc1_defconfig b/configs/xilinx_zynqmp_mini_emmc1_defconfig
index 310aad4..6501ec3 100644
--- a/configs/xilinx_zynqmp_mini_emmc1_defconfig
+++ b/configs/xilinx_zynqmp_mini_emmc1_defconfig
@@ -66,7 +66,6 @@
CONFIG_OF_EMBED=y
CONFIG_SYS_RELOC_GD_ENV_ADDR=y
# CONFIG_NET is not set
-# CONFIG_DM_WARN is not set
# CONFIG_DM_DEVICE_REMOVE is not set
CONFIG_SPL_DM_SEQ_ALIAS=y
# CONFIG_DM_MAILBOX is not set
diff --git a/configs/xilinx_zynqmp_mini_nand_defconfig b/configs/xilinx_zynqmp_mini_nand_defconfig
index ce224f8..bfe93dc 100644
--- a/configs/xilinx_zynqmp_mini_nand_defconfig
+++ b/configs/xilinx_zynqmp_mini_nand_defconfig
@@ -51,7 +51,6 @@
CONFIG_OF_EMBED=y
CONFIG_SYS_RELOC_GD_ENV_ADDR=y
# CONFIG_NET is not set
-# CONFIG_DM_WARN is not set
# CONFIG_DM_DEVICE_REMOVE is not set
# CONFIG_DM_MAILBOX is not set
# CONFIG_MMC is not set
diff --git a/configs/xilinx_zynqmp_mini_nand_single_defconfig b/configs/xilinx_zynqmp_mini_nand_single_defconfig
index ce23cb1..91f5aa2 100644
--- a/configs/xilinx_zynqmp_mini_nand_single_defconfig
+++ b/configs/xilinx_zynqmp_mini_nand_single_defconfig
@@ -51,7 +51,6 @@
CONFIG_OF_EMBED=y
CONFIG_SYS_RELOC_GD_ENV_ADDR=y
# CONFIG_NET is not set
-# CONFIG_DM_WARN is not set
# CONFIG_DM_DEVICE_REMOVE is not set
# CONFIG_DM_MAILBOX is not set
# CONFIG_MMC is not set
diff --git a/configs/xilinx_zynqmp_mini_qspi_defconfig b/configs/xilinx_zynqmp_mini_qspi_defconfig
index a1adfb9..afbf6f6 100644
--- a/configs/xilinx_zynqmp_mini_qspi_defconfig
+++ b/configs/xilinx_zynqmp_mini_qspi_defconfig
@@ -11,6 +11,8 @@
CONFIG_DEFAULT_DEVICE_TREE="zynqmp-mini-qspi"
CONFIG_SPL_STACK=0xfffffffc
CONFIG_SPL=y
+# CONFIG_SPL_FS_FAT is not set
+# CONFIG_SPL_LIBDISK_SUPPORT is not set
CONFIG_SYS_MEM_RSVD_FOR_MMU=y
CONFIG_ZYNQMP_NO_DDR=y
# CONFIG_PSCI_RESET is not set
@@ -67,7 +69,6 @@
CONFIG_OF_EMBED=y
CONFIG_SYS_RELOC_GD_ENV_ADDR=y
# CONFIG_NET is not set
-# CONFIG_DM_WARN is not set
# CONFIG_DM_DEVICE_REMOVE is not set
CONFIG_SPL_DM_SEQ_ALIAS=y
# CONFIG_FIRMWARE is not set
@@ -77,6 +78,7 @@
# CONFIG_DM_MAILBOX is not set
# CONFIG_MMC is not set
# CONFIG_SPI_FLASH_SMART_HWCAPS is not set
+# CONFIG_SPI_FLASH_LOCK is not set
# CONFIG_SPI_FLASH_UNLOCK_ALL is not set
CONFIG_SPI_FLASH_GIGADEVICE=y
CONFIG_SPI_FLASH_ISSI=y
@@ -89,7 +91,6 @@
CONFIG_ARM_DCC=y
CONFIG_SPI=y
CONFIG_ZYNQMP_GQSPI=y
-# CONFIG_FAT_WRITE is not set
CONFIG_PANIC_HANG=y
# CONFIG_GZIP is not set
# CONFIG_LMB is not set
diff --git a/configs/xtfpga_defconfig b/configs/xtfpga_defconfig
index cbe7cdb..fc5b666 100644
--- a/configs/xtfpga_defconfig
+++ b/configs/xtfpga_defconfig
@@ -32,7 +32,6 @@
CONFIG_USE_BOOTFILE=y
CONFIG_BOOTFILE="uImage"
CONFIG_VERSION_VARIABLE=y
-# CONFIG_DM_WARN is not set
# CONFIG_DM_DEVICE_REMOVE is not set
# CONFIG_DM_STDIO is not set
# CONFIG_DM_SEQ_ALIAS is not set
diff --git a/configs/zynq_cse_nand_defconfig b/configs/zynq_cse_nand_defconfig
index 19f653f..f7b7581 100644
--- a/configs/zynq_cse_nand_defconfig
+++ b/configs/zynq_cse_nand_defconfig
@@ -13,6 +13,8 @@
CONFIG_SPL_STACK_R_ADDR=0x200000
CONFIG_SPL_STACK=0xfffffe00
CONFIG_SPL=y
+# CONFIG_SPL_FS_FAT is not set
+# CONFIG_SPL_LIBDISK_SUPPORT is not set
CONFIG_SYS_LOAD_ADDR=0x0
CONFIG_REMAKE_ELF=y
CONFIG_SYS_CUSTOM_LDSCRIPT=y
@@ -69,7 +71,6 @@
CONFIG_ENV_OVERWRITE=y
CONFIG_SYS_RELOC_GD_ENV_ADDR=y
# CONFIG_NET is not set
-# CONFIG_DM_WARN is not set
# CONFIG_DM_DEVICE_REMOVE is not set
CONFIG_SPL_DM_SEQ_ALIAS=y
# CONFIG_MMC is not set
diff --git a/configs/zynq_cse_nor_defconfig b/configs/zynq_cse_nor_defconfig
index 64df1f0..2a50f38 100644
--- a/configs/zynq_cse_nor_defconfig
+++ b/configs/zynq_cse_nor_defconfig
@@ -13,6 +13,8 @@
CONFIG_SPL_STACK_R_ADDR=0x200000
CONFIG_SPL_STACK=0xfffffe00
CONFIG_SPL=y
+# CONFIG_SPL_FS_FAT is not set
+# CONFIG_SPL_LIBDISK_SUPPORT is not set
CONFIG_SYS_LOAD_ADDR=0x0
CONFIG_REMAKE_ELF=y
CONFIG_SYS_CUSTOM_LDSCRIPT=y
@@ -68,7 +70,6 @@
CONFIG_ENV_OVERWRITE=y
CONFIG_SYS_RELOC_GD_ENV_ADDR=y
# CONFIG_NET is not set
-# CONFIG_DM_WARN is not set
# CONFIG_DM_DEVICE_REMOVE is not set
CONFIG_SPL_DM_SEQ_ALIAS=y
# CONFIG_MMC is not set
diff --git a/configs/zynq_cse_qspi_defconfig b/configs/zynq_cse_qspi_defconfig
index 9368fb4..db1fc53 100644
--- a/configs/zynq_cse_qspi_defconfig
+++ b/configs/zynq_cse_qspi_defconfig
@@ -16,6 +16,8 @@
CONFIG_SPL=y
CONFIG_DEBUG_UART_BASE=0x0
CONFIG_DEBUG_UART_CLOCK=0
+# CONFIG_SPL_FS_FAT is not set
+# CONFIG_SPL_LIBDISK_SUPPORT is not set
# CONFIG_ZYNQ_DDRC_INIT is not set
# CONFIG_CMD_ZYNQ is not set
CONFIG_SYS_LOAD_ADDR=0x0
@@ -77,7 +79,6 @@
CONFIG_ENV_OVERWRITE=y
CONFIG_SYS_RELOC_GD_ENV_ADDR=y
# CONFIG_NET is not set
-# CONFIG_DM_WARN is not set
# CONFIG_DM_DEVICE_REMOVE is not set
CONFIG_SPL_DM_SEQ_ALIAS=y
# CONFIG_MMC is not set
diff --git a/doc/README.davinci b/doc/README.davinci
index f368f99..ea81279 100644
--- a/doc/README.davinci
+++ b/doc/README.davinci
@@ -70,7 +70,7 @@
2) TI OMAP-L138 LCDK
http://focus.ti.com/docs/prod/folders/print/omap-l138.html
-http://www.ti.com/tool/TMDXLCDK138
+https://www.ti.com/tool/TMDXLCDK138
Davinci special defines
=======================
diff --git a/doc/README.omap3 b/doc/README.omap3
index 3a1ac81..d1e6be9 100644
--- a/doc/README.omap3
+++ b/doc/README.omap3
@@ -163,8 +163,8 @@
[1] OMAP3:
-http://www.ti.com/omap3 (high volume) and
-http://www.ti.com/omap35x (broad market)
+https://www.ti.com/omap3 (high volume) and
+https://www.ti.com/omap35x (broad market)
[2] OMAP3530 BeagleBoard:
diff --git a/doc/README.serial_dt_baud b/doc/README.serial_dt_baud
new file mode 100644
index 0000000..f8768d0
--- /dev/null
+++ b/doc/README.serial_dt_baud
@@ -0,0 +1,41 @@
+Fetch serial baudrate from DT
+-----------------------------
+
+To support fetching of baudrate from DT, the following is done:-
+
+The baudrate configured in Kconfig symbol CONFIG_BAUDRATE is taken by default by serial.
+If change of baudrate is required then the Kconfig symbol CONFIG_BAUDRATE needs to
+changed and U-Boot recompilation is required or the U-Boot environment needs to be updated.
+
+To avoid this, add support to fetch the baudrate directly from the device tree file and
+update the environment.
+
+The default environment stores the default baudrate value. When default baudrate and dtb
+baudrate are not same glitches are seen on the serial.
+So, the environment also needs to be updated with the dtb baudrate to avoid the glitches on
+the serial which is enabled by OF_SERIAL_BAUD.
+
+The Kconfig SPL_ENV_SUPPORT needs to be enabled to allow patching in SPL.
+
+The Kconfig DEFAULT_ENV_IS_RW which is enabled by OF_SERIAL_BAUD with making the environment
+writable.
+
+The ofnode_read_baud() function parses and fetches the baudrate value from the DT. This value
+is validated and updated to baudrate during serial init. Padding is added at the end of the
+default environment and the dt baudrate is updated with the latest value.
+
+Example:-
+
+The serial port options are of the form "bbbbpnf", where "bbbb" is the baud rate, "p" is parity ("n", "o", or "e"),
+"n" is number of bits, and "f" is flow control ("r" for RTS or omit it). Default is "115200n8".
+
+chosen {
+ bootargs = "earlycon console=ttyPS0,115200 clk_ignore_unused root=/dev/ram0 rw init_fatal_sh=1";
+ stdout-path = "serial0:115200n8";
+ };
+
+From the chosen node, stdout-path property is obtained as string.
+
+ stdout-path = "serial0:115200n8";
+
+The string is parsed to get the baudrate 115200. This string is converted to integer and updated to the environment.
diff --git a/doc/android/bcb.rst b/doc/android/bcb.rst
index 8861608..2226517 100644
--- a/doc/android/bcb.rst
+++ b/doc/android/bcb.rst
@@ -41,23 +41,25 @@
bcb - Load/set/clear/test/dump/store Android BCB fields
Usage:
- bcb load <dev> <part> - load BCB from mmc <dev>:<part>
- bcb set <field> <val> - set BCB <field> to <val>
- bcb clear [<field>] - clear BCB <field> or all fields
- bcb test <field> <op> <val> - test BCB <field> against <val>
- bcb dump <field> - dump BCB <field>
- bcb store - store BCB back to mmc
+ bcb load <interface> <dev> <part> - load BCB from <interface> <dev>:<part>
+ load <dev> <part> - load BCB from mmc <dev>:<part>
+ bcb set <field> <val> - set BCB <field> to <val>
+ bcb clear [<field>] - clear BCB <field> or all fields
+ bcb test <field> <op> <val> - test BCB <field> against <val>
+ bcb dump <field> - dump BCB <field>
+ bcb store - store BCB back to <interface>
Legend:
- <dev> - MMC device index containing the BCB partition
- <part> - MMC partition index or name containing the BCB
- <field> - one of {command,status,recovery,stage,reserved}
- <op> - the binary operator used in 'bcb test':
- '=' returns true if <val> matches the string stored in <field>
- '~' returns true if <val> matches a subset of <field>'s string
- <val> - string/text provided as input to bcb {set,test}
- NOTE: any ':' character in <val> will be replaced by line feed
- during 'bcb set' and used as separator by upper layers
+ <interface> - storage device interface (virtio, mmc, etc)
+ <dev> - storage device index containing the BCB partition
+ <part> - partition index or name containing the BCB
+ <field> - one of {command,status,recovery,stage,reserved}
+ <op> - the binary operator used in 'bcb test':
+ '=' returns true if <val> matches the string stored in <field>
+ '~' returns true if <val> matches a subset of <field>'s string
+ <val> - string/text provided as input to bcb {set,test}
+ NOTE: any ':' character in <val> will be replaced by line feed
+ during 'bcb set' and used as separator by upper layers
'bcb'. Example of getting reboot reason
@@ -91,7 +93,7 @@
CONFIG_PARTITIONS=y
CONFIG_MMC=y
- CONFIG_BCB=y
+ CONFIG_CMD_BCB=y
.. [1] https://android.googlesource.com/platform/bootable/recovery
.. [2] https://source.android.com/devices/bootloader
diff --git a/doc/arch/arm64.ffa.rst b/doc/arch/arm64.ffa.rst
index 4ecdc31..f966f8b 100644
--- a/doc/arch/arm64.ffa.rst
+++ b/doc/arch/arm64.ffa.rst
@@ -40,7 +40,7 @@
- Sandbox FF-A test cases.
FF-A and SMC specifications
--------------------------------------------
+---------------------------
The current implementation of the U-Boot FF-A support relies on
`FF-A v1.0 specification`_ and uses SMC32 calling convention which
@@ -56,12 +56,12 @@
The FF-A support uses 64-bit registers as per `SMC Calling Convention v1.2 specification`_.
Supported hardware
---------------------------------
+------------------
Aarch64 plaforms
Configuration
-----------------------
+-------------
CONFIG_ARM_FFA_TRANSPORT
Enables the FF-A support. Turn this on if you want to use FF-A
@@ -70,7 +70,7 @@
When using sandbox, the sandbox FF-A emulator and FF-A sandbox driver will be used.
FF-A ABIs under the hood
----------------------------------------
+------------------------
Invoking an FF-A ABI involves providing to the secure world/hypervisor the
expected arguments from the ABI.
@@ -89,7 +89,7 @@
This methodology applies to all the FF-A ABIs.
FF-A bus discovery on Arm 64-bit platforms
----------------------------------------------
+------------------------------------------
When CONFIG_ARM_FFA_TRANSPORT is enabled, the FF-A bus is considered as
an architecture feature and discovered using ARM_SMCCC_FEATURES mechanism.
@@ -136,7 +136,7 @@
and can be probed again if needed.
Requirements for clients
--------------------------------------
+------------------------
When using the FF-A bus with EFI, clients must query the SPs they are looking for
during EFI boot-time mode using the service UUID.
@@ -159,13 +159,13 @@
The calling convention between U-Boot and the secure world stays the same: SMC32.
Requirements for user drivers
--------------------------------------
+-----------------------------
Users who want to implement their custom FF-A device driver while reusing the FF-A Uclass can do so
by implementing their own invoke_ffa_fn() in the user driver.
The bus driver layer
-------------------------------
+--------------------
FF-A support comes on top of the SMCCC layer and is implemented by the FF-A Uclass drivers/firmware/arm-ffa/arm-ffa-uclass.c
@@ -210,7 +210,7 @@
- FF-A bus can be compiled and used without EFI
Relationship between the sandbox emulator and the FF-A device
----------------------------------------------------------------
+-------------------------------------------------------------
::
@@ -222,7 +222,7 @@
ffa 0 [ ] sandbox_arm_ffa `-- sandbox-arm-ffa
The armffa command
------------------------------------
+------------------
armffa is a command showcasing how to use the FF-A bus and how to invoke the driver operations.
diff --git a/doc/board/AndesTech/ae350.rst b/doc/board/AndesTech/ae350.rst
index 42a2b4d..99622fd 100644
--- a/doc/board/AndesTech/ae350.rst
+++ b/doc/board/AndesTech/ae350.rst
@@ -1,7 +1,7 @@
.. SPDX-License-Identifier: GPL-2.0+
AE350
-======
+=====
AE350 is the mainline SoC produced by Andes Technology using AndesV5 CPU core
based on RISC-V architecture.
diff --git a/doc/board/actions/cubieboard7.rst b/doc/board/actions/cubieboard7.rst
index 74f2b12..1f73fc4 100644
--- a/doc/board/actions/cubieboard7.rst
+++ b/doc/board/actions/cubieboard7.rst
@@ -20,7 +20,7 @@
getting into u-boot prompt is easy.
Enter ADFU Mode
-----------------
+---------------
Before write the firmware, let the development board entering the ADFU mode: insert
one end of the USB cable to the PC, press and hold the ADFU button, and then connect
@@ -28,7 +28,7 @@
the ADFU button, after connecting it will enter the ADFU mode.
Check whether entered ADFU Mode
---------------------------------
+-------------------------------
The user needs to run the following command on the PC side to check if the ADFU
device is detected. ID realted to "Actions Semiconductor Co., Ltd" means that
diff --git a/doc/board/actions/index.rst b/doc/board/actions/index.rst
index c596879..e925fcd 100644
--- a/doc/board/actions/index.rst
+++ b/doc/board/actions/index.rst
@@ -2,7 +2,7 @@
.. Copyright (C) 2020 Amit Singh Tomar <amittomer25@gmail.com>
Actions
-========
+=======
.. toctree::
:maxdepth: 2
diff --git a/doc/board/armltd/index.rst b/doc/board/armltd/index.rst
index fc1d75a..052a969 100644
--- a/doc/board/armltd/index.rst
+++ b/doc/board/armltd/index.rst
@@ -1,7 +1,7 @@
.. SPDX-License-Identifier: GPL-2.0
Arm Ltd
-=============
+=======
.. toctree::
:maxdepth: 2
diff --git a/doc/board/ti/am62x_beagleplay.rst b/doc/board/beagle/am62x_beagleplay.rst
similarity index 87%
rename from doc/board/ti/am62x_beagleplay.rst
rename to doc/board/beagle/am62x_beagleplay.rst
index 39913b2..7784e62 100644
--- a/doc/board/ti/am62x_beagleplay.rst
+++ b/doc/board/beagle/am62x_beagleplay.rst
@@ -23,7 +23,7 @@
----------
Below is the pictorial representation of boot flow:
-.. image:: img/boot_diagram_k3_current.svg
+.. image:: ../ti/img/boot_diagram_k3_current.svg
:alt: Boot flow diagram
- On this platform, 'TI Foundational Security' (TIFS) functions as the
@@ -34,7 +34,7 @@
Sources:
--------
-.. include:: k3.rst
+.. include:: ../ti/k3.rst
:start-after: .. k3_rst_include_start_boot_sources
:end-before: .. k3_rst_include_end_boot_sources
@@ -42,35 +42,35 @@
----------------
0. Setup the environment variables:
-.. include:: k3.rst
+.. include:: ../ti/k3.rst
:start-after: .. k3_rst_include_start_common_env_vars_desc
:end-before: .. k3_rst_include_end_common_env_vars_desc
-.. include:: k3.rst
+.. include:: ../ti/k3.rst
:start-after: .. k3_rst_include_start_board_env_vars_desc
:end-before: .. k3_rst_include_end_board_env_vars_desc
Set the variables corresponding to this platform:
-.. include:: k3.rst
+.. include:: ../ti/k3.rst
:start-after: .. k3_rst_include_start_common_env_vars_defn
:end-before: .. k3_rst_include_end_common_env_vars_defn
-.. code-block:: bash
+.. prompt:: bash $
- $ export UBOOT_CFG_CORTEXR="am62x_evm_r5_defconfig beagleplay_r5.config"
- $ export UBOOT_CFG_CORTEXA="am62x_evm_a53_defconfig beagleplay_a53.config"
- $ export TFA_BOARD=lite
- $ # we dont use any extra TFA parameters
- $ unset TFA_EXTRA_ARGS
- $ export OPTEE_PLATFORM=k3-am62x
- $ export OPTEE_EXTRA_ARGS="CFG_WITH_SOFTWARE_PRNG=y"
+ export UBOOT_CFG_CORTEXR=am62x_beagleplay_r5_defconfig
+ export UBOOT_CFG_CORTEXA=am62x_beagleplay_a53_defconfig
+ export TFA_BOARD=lite
+ # we dont use any extra TFA parameters
+ unset TFA_EXTRA_ARGS
+ export OPTEE_PLATFORM=k3-am62x
+ export OPTEE_EXTRA_ARGS="CFG_WITH_SOFTWARE_PRNG=y"
-.. include:: am62x_sk.rst
+.. include:: ../ti/am62x_sk.rst
:start-after: .. am62x_evm_rst_include_start_build_steps
:end-before: .. am62x_evm_rst_include_end_build_steps
Target Images
---------------
+-------------
Copy the below images to an SD card and boot:
* tiboot3-am62x-gp-evm.bin from R5 build as tiboot3.bin
@@ -82,12 +82,12 @@
- tiboot3.bin
-.. image:: img/multi_cert_tiboot3.bin.svg
+.. image:: ../ti/img/multi_cert_tiboot3.bin.svg
:alt: tiboot3.bin image format
- tispl.bin
-.. image:: img/dm_tispl.bin.svg
+.. image:: ../ti/img/dm_tispl.bin.svg
:alt: tispl.bin image format
Additional hardware for U-Boot development
@@ -109,7 +109,7 @@
depends on the SD card quality.
Flash to uSD card or how to deal with "bricked" Board
---------------------------------------------------------
+-----------------------------------------------------
When deploying or working on Linux, it's common to use the onboard
eMMC. However, avoiding the eMMC and using the uSD card is safer when
@@ -174,24 +174,24 @@
The following are the steps from Linux shell to program eMMC:
-.. code-block:: bash
+.. prompt:: bash #
- # # Enable Boot0 boot
- # mmc bootpart enable 1 2 /dev/mmcblk0
- # mmc bootbus set single_backward x1 x8 /dev/mmcblk0
- # mmc hwreset enable /dev/mmcblk0
+ # Enable Boot0 boot
+ mmc bootpart enable 1 2 /dev/mmcblk0
+ mmc bootbus set single_backward x1 x8 /dev/mmcblk0
+ mmc hwreset enable /dev/mmcblk0
- # # Clear eMMC boot0
- # echo '0' >> /sys/class/block/mmcblk0boot0/force_ro
- # dd if=/dev/zero of=/dev/mmcblk0boot0 count=32 bs=128k
- # # Write tiboot3.bin
- # dd if=tiboot3.bin of=/dev/mmcblk0boot0 bs=128k
+ # Clear eMMC boot0
+ echo '0' >> /sys/class/block/mmcblk0boot0/force_ro
+ dd if=/dev/zero of=/dev/mmcblk0boot0 count=32 bs=128k
+ # Write tiboot3.bin
+ dd if=tiboot3.bin of=/dev/mmcblk0boot0 bs=128k
- # # Copy the rest of the boot binaries
- # mount /dev/mmcblk0p1 /boot/firmware
- # cp tispl.bin /boot/firmware
- # cp u-boot.img /boot/firmware
- # sync
+ # Copy the rest of the boot binaries
+ mount /dev/mmcblk0p1 /boot/firmware
+ cp tispl.bin /boot/firmware
+ cp u-boot.img /boot/firmware
+ sync
.. warning ::
@@ -240,7 +240,7 @@
A53 SPL DDR Memory Layout
-------------------------
-.. include:: am62x_sk.rst
+.. include:: ../ti/am62x_sk.rst
:start-after: .. am62x_evm_rst_include_start_ddr_mem_layout
:end-before: .. am62x_evm_rst_include_end_ddr_mem_layout
@@ -284,11 +284,11 @@
environment's distribution needs to be updated, it might be necessary to
build OpenOCD from the source.
-.. include:: k3.rst
+.. include:: ../ti/k3.rst
:start-after: .. k3_rst_include_start_openocd_connect_tag_connect
:end-before: .. k3_rst_include_end_openocd_connect_tag_connect
-.. include:: k3.rst
+.. include:: ../ti/k3.rst
:start-after: .. k3_rst_include_start_openocd_cfg_external_intro
:end-before: .. k3_rst_include_end_openocd_cfg_external_intro
diff --git a/doc/board/ti/img/beagleplay_emmc.svg b/doc/board/beagle/img/beagleplay_emmc.svg
similarity index 100%
rename from doc/board/ti/img/beagleplay_emmc.svg
rename to doc/board/beagle/img/beagleplay_emmc.svg
diff --git a/doc/board/beagle/index.rst b/doc/board/beagle/index.rst
new file mode 100644
index 0000000..9124546
--- /dev/null
+++ b/doc/board/beagle/index.rst
@@ -0,0 +1,14 @@
+.. SPDX-License-Identifier: GPL-2.0+
+
+BeagleBoard.org
+###############
+
+
+ARM based boards
+----------------
+
+.. toctree::
+ :maxdepth: 2
+
+ am62x_beagleplay
+ j721e_beagleboneai64
diff --git a/doc/board/ti/am62x_beagleplay.rst b/doc/board/beagle/j721e_beagleboneai64.rst
similarity index 62%
copy from doc/board/ti/am62x_beagleplay.rst
copy to doc/board/beagle/j721e_beagleboneai64.rst
index 39913b2..d6b9c8c 100644
--- a/doc/board/ti/am62x_beagleplay.rst
+++ b/doc/board/beagle/j721e_beagleboneai64.rst
@@ -1,40 +1,44 @@
.. SPDX-License-Identifier: GPL-2.0+ OR BSD-3-Clause
.. sectionauthor:: Nishanth Menon <nm@ti.com>
-AM62x Beagleboard.org Beagleplay
-================================
+J721E/TDA4VM Beagleboard.org BeagleBone AI-64
+=============================================
Introduction:
-------------
-BeagleBoard.org BeaglePlay is an easy to use, affordable open source
-hardware single board computer based on the Texas Instruments AM625
-SoC that allows you to create connected devices that work even at long
-distances using IEEE 802.15.4g LR-WPAN and IEEE 802.3cg 10Base-T1L.
-Expansion is provided over open standards based mikroBUS, Grove and
-QWIIC headers among other interfaces.
+BeagleBoard.org BeagleBone AI-64 is an open source hardware single
+board computer based on the Texas Instruments TDA4VM SoC featuring
+dual-core 2.0GHz Arm Cortex-A72 processor, C7x+MMA and 2 C66x
+floating-point VLIW DSPs, 3x dual ARM Cortex-R5 co-processors,
+2x 6-core Programmable Real-Time Unit and Industrial Communication
+SubSystem, PowerVR Rogue 8XE GE8430 3D GPU. The board features 4GB
+DDR4, USB3.0 Type-C, 2x USB SS Type-A, miniDisplayPort, 2x 4-lane
+CSI, DSI, 16GB eMMC flash, 1G Ethernet, M.2 E-key for WiFi/BT, and
+BeagleBone expansion headers.
Further information can be found at:
-* Product Page: https://beagleplay.org/
-* Hardware documentation: https://git.beagleboard.org/beagleplay/beagleplay
+* Product Page: https://beagleboard.org/ai-64
+* Hardware documentation: https://git.beagleboard.org/beagleboard/beaglebone-ai-64
Boot Flow:
----------
Below is the pictorial representation of boot flow:
-.. image:: img/boot_diagram_k3_current.svg
+.. image:: ../ti/img/boot_diagram_j721e.svg
:alt: Boot flow diagram
-- On this platform, 'TI Foundational Security' (TIFS) functions as the
- security enclave master while 'Device Manager' (DM), also known as the
- 'TISCI server' in "TI terminology", offers all the essential services.
- The A53 or M4F (Aux core) sends requests to TIFS/DM to accomplish these
- services, as illustrated in the diagram above.
+- On this platform, DMSC runs 'TI Foundational Security' (TIFS) which
+ functions as the security enclave master. The 'Device Manager' (DM),
+ also known as the 'TISCI server' in "TI terminology", running on boot
+ R5F, offers all the essential services required for device management.
+ The A72, C7x, C6x or R5F (Aux cores) sends requests to TIFS/DM to
+ accomplish the needed services, as illustrated in the diagram above.
Sources:
--------
-.. include:: k3.rst
+.. include:: ../ti/k3.rst
:start-after: .. k3_rst_include_start_boot_sources
:end-before: .. k3_rst_include_end_boot_sources
@@ -42,38 +46,39 @@
----------------
0. Setup the environment variables:
-.. include:: k3.rst
+.. include:: ../ti/k3.rst
:start-after: .. k3_rst_include_start_common_env_vars_desc
:end-before: .. k3_rst_include_end_common_env_vars_desc
-.. include:: k3.rst
+.. include:: ../ti/k3.rst
:start-after: .. k3_rst_include_start_board_env_vars_desc
:end-before: .. k3_rst_include_end_board_env_vars_desc
Set the variables corresponding to this platform:
-.. include:: k3.rst
+.. include:: ../ti/k3.rst
:start-after: .. k3_rst_include_start_common_env_vars_defn
:end-before: .. k3_rst_include_end_common_env_vars_defn
-.. code-block:: bash
+.. prompt:: bash $
- $ export UBOOT_CFG_CORTEXR="am62x_evm_r5_defconfig beagleplay_r5.config"
- $ export UBOOT_CFG_CORTEXA="am62x_evm_a53_defconfig beagleplay_a53.config"
- $ export TFA_BOARD=lite
- $ # we dont use any extra TFA parameters
- $ unset TFA_EXTRA_ARGS
- $ export OPTEE_PLATFORM=k3-am62x
- $ export OPTEE_EXTRA_ARGS="CFG_WITH_SOFTWARE_PRNG=y"
+ export UBOOT_CFG_CORTEXR=j721e_beagleboneai64_r5_defconfig
+ export UBOOT_CFG_CORTEXA=j721e_beagleboneai64_a72_defconfig
+ export TFA_BOARD=generic
+ # we dont use any extra TFA parameters
+ unset TFA_EXTRA_ARGS
+ export OPTEE_PLATFORM=k3-j721e
+ # we dont use any extra OP-TEE parameters
+ unset OPTEE_EXTRA_ARGS
-.. include:: am62x_sk.rst
- :start-after: .. am62x_evm_rst_include_start_build_steps
- :end-before: .. am62x_evm_rst_include_end_build_steps
+.. include:: ../ti/j721e_evm.rst
+ :start-after: .. j721e_evm_rst_include_start_build_steps
+ :end-before: .. j721e_evm_rst_include_end_build_steps
Target Images
--------------
Copy the below images to an SD card and boot:
-* tiboot3-am62x-gp-evm.bin from R5 build as tiboot3.bin
+* tiboot3-j721e-gp-evm.bin from R5 build as tiboot3.bin
* tispl.bin_unsigned from Cortex-A build as tispl.bin
* u-boot.img_unsigned from Cortex-A build as u-boot.img
@@ -82,30 +87,35 @@
- tiboot3.bin
-.. image:: img/multi_cert_tiboot3.bin.svg
+.. image:: ../ti/img/no_multi_cert_tiboot3.bin.svg
:alt: tiboot3.bin image format
- tispl.bin
-.. image:: img/dm_tispl.bin.svg
+.. image:: ../ti/img/dm_tispl.bin.svg
:alt: tispl.bin image format
+- sysfw.itb
+
+.. image:: ../ti/img/sysfw.itb.svg
+ :alt: sysfw.itb image format
+
Additional hardware for U-Boot development
------------------------------------------
-* Serial Console is critical for U-Boot development on BeaglePlay. See
- `BeaglePlay serial console documentation
- <https://docs.beagleboard.org/latest/boards/beagleplay/demos-and-tutorials/using-serial-console.html>`_.
+* Serial Console is critical for U-Boot development on BeagleBone AI-64. See
+ `BeagleBone AI-64 connector documentation
+ <https://docs.beagleboard.org/latest/boards/beaglebone/ai-64/ch07.html>`_.
* uSD is preferred option over eMMC, and a SD/MMC reader will be needed.
* (optionally) JTAG is useful when working with very early stages of boot.
Default storage options
-----------------------
-There are multiple storage media options on BeaglePlay, but primarily:
+There are multiple storage media options on BeagleBone AI-64, but primarily:
* Onboard eMMC (default) - reliable, fast and meant for deployment use.
-* SD/MMC card interface (hold 'USR' switch and power on) - Entirely
+* SD/MMC card interface (hold 'BOOT' switch and power on) - Entirely
depends on the SD card quality.
Flash to uSD card or how to deal with "bricked" Board
@@ -127,7 +137,7 @@
The simplest option is to start with a standard distribution
image like those in `BeagleBoard.org Distros Page
<https://www.beagleboard.org/distros>`_ and download a disk image for
-BeaglePlay. Pick a 16GB+ uSD card to be on the safer side.
+BeagleBone AI-64. Pick a 16GB+ uSD card to be on the safer side.
With an SD/MMC Card reader and `Balena Etcher
<https://etcher.balena.io/>`_, having a functional setup in minutes is
@@ -170,28 +180,28 @@
boot1 partition depends on A/B update requirements.
.. image:: img/beagleplay_emmc.svg
- :alt: eMMC partitions and boot file organization for BeaglePlay
+ :alt: eMMC partitions and boot file organization for BeagleBone AI-64
The following are the steps from Linux shell to program eMMC:
-.. code-block:: bash
+.. prompt:: bash #
- # # Enable Boot0 boot
- # mmc bootpart enable 1 2 /dev/mmcblk0
- # mmc bootbus set single_backward x1 x8 /dev/mmcblk0
- # mmc hwreset enable /dev/mmcblk0
+ # Enable Boot0 boot
+ mmc bootpart enable 1 2 /dev/mmcblk0
+ mmc bootbus set single_backward x1 x8 /dev/mmcblk0
+ mmc hwreset enable /dev/mmcblk0
- # # Clear eMMC boot0
- # echo '0' >> /sys/class/block/mmcblk0boot0/force_ro
- # dd if=/dev/zero of=/dev/mmcblk0boot0 count=32 bs=128k
- # # Write tiboot3.bin
- # dd if=tiboot3.bin of=/dev/mmcblk0boot0 bs=128k
+ # Clear eMMC boot0
+ echo '0' >> /sys/class/block/mmcblk0boot0/force_ro
+ dd if=/dev/zero of=/dev/mmcblk0boot0 count=32 bs=128k
+ # Write tiboot3.bin
+ dd if=tiboot3.bin of=/dev/mmcblk0boot0 bs=128k
- # # Copy the rest of the boot binaries
- # mount /dev/mmcblk0p1 /boot/firmware
- # cp tispl.bin /boot/firmware
- # cp u-boot.img /boot/firmware
- # sync
+ # Copy the rest of the boot binaries
+ mount /dev/mmcblk0p1 /boot/firmware
+ cp tispl.bin /boot/firmware
+ cp u-boot.img /boot/firmware
+ sync
.. warning ::
@@ -233,41 +243,36 @@
.. warning ::
- If the "red" power LED is not glowing, the system power supply is not
- functional. Please refer to `BeaglePlay documentation
- <https://beagleplay.org/>`_ for further information.
-
-A53 SPL DDR Memory Layout
--------------------------
-
-.. include:: am62x_sk.rst
- :start-after: .. am62x_evm_rst_include_start_ddr_mem_layout
- :end-before: .. am62x_evm_rst_include_end_ddr_mem_layout
+ The green LED very next to the serial connector labelled "WKUP UART0"
+ is the power LED (LED6). This is the same color as the rest of the USR
+ LEDs. If the "green" LED6 power LED is not glowing, the system power
+ supply is not functional. Please refer to `BeagleBone AI-64 documentation
+ <https://beagleboard.org/ai-64/>`_ for further information.
Switch Setting for Boot Mode
----------------------------
-The boot time option is configured via "USR" button on the board.
-See `Beagleplay Schematics <https://git.beagleboard.org/beagleplay/beagleplay/-/blob/main/BeaglePlay_sch.pdf>`_
+The boot time option is configured via "BOOT" button on the board.
+See `BeagleBone AI-64 Schematics <https://git.beagleboard.org/beagleboard/beaglebone-ai-64/-/blob/main/BeagleBone_AI-64_SCH.pdf>`_
for details.
.. list-table:: Boot Modes
:widths: 16 16 16
:header-rows: 1
- * - USR Switch Position
+ * - BOOT Switch Position
- Primary Boot
- Secondary Boot
* - Not Pressed
- eMMC
- - UART
+ - SD Card
* - Pressed
- - SD/MMC File System (FS) mode
- - USB Device Firmware Upgrade (DFU) mode
+ - SD Card
+ - SD Card
-To switch to SD card boot mode, hold the USR button while powering on
+To switch to SD card boot mode, hold the BOOT button while powering on
with Type-C power supply, then release when power LED lights up.
Debugging U-Boot
@@ -284,15 +289,15 @@
environment's distribution needs to be updated, it might be necessary to
build OpenOCD from the source.
-.. include:: k3.rst
+.. include:: ../ti/k3.rst
:start-after: .. k3_rst_include_start_openocd_connect_tag_connect
:end-before: .. k3_rst_include_end_openocd_connect_tag_connect
-.. include:: k3.rst
+.. include:: ../ti/k3.rst
:start-after: .. k3_rst_include_start_openocd_cfg_external_intro
:end-before: .. k3_rst_include_end_openocd_cfg_external_intro
-For example, with BeaglePlay (AM62X platform), the openocd_connect.cfg:
+For example, with BeagleBone AI-64 (J721e platform), the openocd_connect.cfg:
.. code-block:: tcl
@@ -310,7 +315,7 @@
if { ![info exists SOC] } {
# Set the SoC of interest
- set SOC am625
+ set SOC j721e
}
source [find target/ti_k3.cfg]
diff --git a/doc/board/emulation/qemu-riscv.rst b/doc/board/emulation/qemu-riscv.rst
index 61137bc..8a5eb1e 100644
--- a/doc/board/emulation/qemu-riscv.rst
+++ b/doc/board/emulation/qemu-riscv.rst
@@ -131,7 +131,13 @@
-drive if=none,file=riscv64.img,format=raw,id=mydisk \
-device ide-hd,drive=mydisk,bus=ahci.0
-You will have to run 'scsi scan' to use it.
+or alternatively attach an emulated UFS::
+
+ -device ufs,id=ufs0 \
+ -drive if=none,file=test.img,format=raw,id=lun0 \
+ -device ufs-lu,drive=lun0,bus=ufs0
+
+You will have to run 'scsi scan' to use them.
A video console can be emulated in RISC-V virt machine by removing "-nographic"
and adding::
diff --git a/doc/board/hisilicon/hikey.rst b/doc/board/hisilicon/hikey.rst
new file mode 100644
index 0000000..8038a24
--- /dev/null
+++ b/doc/board/hisilicon/hikey.rst
@@ -0,0 +1,261 @@
+.. SPDX-License-Identifier: GPL-2.0-or-later
+
+HiKey board
+###########
+
+Introduction
+============
+
+HiKey is the first certified 96Boards Consumer Edition board. The board/SoC has:
+
+* HiSilicon Kirin 6220 eight-core ARM Cortex-A53 64-bit SoC running at 1.2GHz.
+* ARM Mali 450-MP4 GPU
+* 1GB 800MHz LPDDR3 DRAM
+* 4GB eMMC Flash Storage
+* microSD
+* 802.11a/b/g/n WiFi, Bluetooth
+
+The HiKey schematic can be found here:
+https://github.com/96boards/documentation/blob/master/consumer/hikey/hikey620/hardware-docs/HiKey_schematics_LeMaker_version_Rev_A1.pdf
+
+The SoC datasheet can be found here:
+https://github.com/96boards/documentation/blob/master/consumer/hikey/hikey620/hardware-docs/Hi6220V100_Multi-Mode_Application_Processor_Function_Description.pdf
+
+Currently the u-boot port supports:
+
+* USB
+* eMMC
+* SD card
+* GPIO
+
+The HiKey U-Boot port has been tested with l-loader, booting ATF, which then
+boots U-Boot as the bl33.bin executable.
+
+Compile from source
+===================
+
+First get all the sources
+
+.. code-block:: bash
+
+ mkdir -p ~/hikey/src ~/hikey/bin
+ cd ~/hikey/src
+ git clone https://github.com/96boards-hikey/edk2 -b testing/hikey960_v2.5
+ git clone https://github.com/ARM-software/arm-trusted-firmware
+ git clone https://github.com/96boards-hikey/l-loader -b testing/hikey960_v1.2
+ git clone https://github.com/96boards-hikey/OpenPlatformPkg -b testing/hikey960_v1.3.4
+ git clone https://github.com/96boards-hikey/atf-fastboot
+ wget https://snapshots.linaro.org/96boards/reference-platform/components/uefi-staging/latest/hikey/release/hisi-idt.py
+
+Get the BL30 mcuimage.bin binary. It is shipped as part of the UEFI source.
+The latest version can be obtained from the OpenPlatformPkg repo.
+
+.. code-block:: bash
+
+ cp OpenPlatformPkg/Platforms/Hisilicon/HiKey/Binary/mcuimage.bin ~/hikey/bin/
+
+Get nvme.img binary
+
+.. code-block:: bash
+
+ wget -P ~/hikey/bin https://snapshots.linaro.org/96boards/reference-platform/components/uefi-staging/latest/hikey/release/nvme.img
+
+Compile U-Boot
+==============
+
+.. code-block:: bash
+
+ cd ~/hikey/src/u-boot
+ make CROSS_COMPILE=aarch64-linux-gnu- hikey_config
+ make CROSS_COMPILE=aarch64-linux-gnu-
+ cp u-boot.bin ~/hikey/bin
+
+Compile ARM Trusted Firmware (ATF)
+==================================
+
+.. code-block:: bash
+
+ cd ~/hikey/src/arm-trusted-firmware
+ make CROSS_COMPILE=aarch64-linux-gnu- all fip \
+ SCP_BL2=~/hikey/bin/mcuimage.bin \
+ BL33=~/hikey/bin/u-boot.bin DEBUG=1 PLAT=hikey
+
+Copy the resulting FIP binary
+
+.. code-block:: bash
+
+ cp build/hikey/debug/fip.bin ~/hikey/bin
+
+Compile ATF Fastboot
+====================
+
+.. code-block:: bash
+
+ cd ~/hikey/src/atf-fastboot
+ make CROSS_COMPILE=aarch64-linux-gnu- PLAT=hikey DEBUG=1
+
+Compile l-loader
+================
+
+.. code-block:: bash
+
+ cd ~/hikey/src/l-loader
+ ln -sf ~/hikey/src/arm-trusted-firmware/build/hikey/debug/bl1.bin
+ ln -sf ~/hikey/src/arm-trusted-firmware/build/hikey/debug/bl2.bin
+ ln -sf ~/hikey/src/atf-fastboot/build/hikey/debug/bl1.bin fastboot.bin
+ make hikey PTABLE_LST=aosp-8g
+
+Copy the resulting binaries
+
+.. code-block:: bash
+
+ cp *.img ~/hikey/bin
+ cp l-loader.bin ~/hikey/bin
+ cp recovery.bin ~/hikey/bin
+
+These instructions are adapted from
+https://github.com/ARM-software/arm-trusted-firmware/blob/master/docs/plat/hikey.rst
+
+Flashing
+========
+
+1. Connect the second jumper on J15 BOOT SEL, to go into recovery mode and flash l-loader.bin with
+the hisi-idt.py utility. Then connect a USB A to B mini cable from your PC to the USB OTG port of HiKey and execute the below command.
+
+The command below assumes HiKey enumerated as the first USB serial port
+
+.. code-block:: bash
+
+ sudo python ~/hikey/src/hisi-idt.py -d /dev/ttyUSB0 --img1 ~/hikey/bin/recovery.bin
+
+2. Once LED 0 comes on solid, HiKey board should be detected as a fastboot device.
+
+.. code-block::
+
+ sudo fastboot devices
+
+ 0123456789ABCDEF fastboot
+
+3. Flash the images
+
+.. code-block::
+
+ sudo fastboot flash ptable ~/hikey/bin/prm_ptable.img
+ sudo fastboot flash loader ~/hikey/bin/l-loader.bin
+ sudo fastboot flash fastboot ~/hikey/bin/fip.bin
+ sudo fastboot flash nvme ~/hikey/bin/nvme.img
+
+4. Disconnect second jumper on J15 BOOT SEL, and reset the board and you will now (hopefully)
+ have ATF, booting u-boot from eMMC.
+
+ Note: To get USB host working, also disconnect the USB OTG cable used for flashing. Otherwise you
+ will get 'dwc_otg_core_host_init: Timeout!' errors.
+
+See working boot trace below on UART3 available at Low Speed Expansion header::
+
+ NOTICE: BL2: v1.5(debug):v1.5-694-g6d4f6aea
+ NOTICE: BL2: Built : 09:21:42, Aug 29 2018
+ INFO: BL2: Doing platform setup
+ INFO: ddr3 rank1 init pass
+ INFO: succeed to set ddrc 150mhz
+ INFO: ddr3 rank1 init pass
+ INFO: succeed to set ddrc 266mhz
+ INFO: ddr3 rank1 init pass
+ INFO: succeed to set ddrc 400mhz
+ INFO: ddr3 rank1 init pass
+ INFO: succeed to set ddrc 533mhz
+ INFO: ddr3 rank1 init pass
+ INFO: succeed to set ddrc 800mhz
+ INFO: Samsung DDR
+ INFO: ddr test value:0xa5a55a5a
+ INFO: BL2: TrustZone: protecting 16777216 bytes of memory at 0x3f000000
+ INFO: BL2: TrustZone: protecting 4194304 bytes of memory at 0x3e800000
+ INFO: [BDID] [fff91c18] midr: 0x410fd033
+ INFO: init_acpu_dvfs: pmic version 17
+ INFO: init_acpu_dvfs: ACPU_CHIP_MAX_FREQ=0x186a00.
+ INFO: acpu_dvfs_volt_init: success!
+ INFO: acpu_dvfs_set_freq: support freq num is 5
+ INFO: acpu_dvfs_set_freq: start prof is 0x4
+ INFO: acpu_dvfs_set_freq: magic is 0x5a5ac5c5
+ INFO: acpu_dvfs_set_freq: voltage:
+ INFO: - 0: 0x49
+ INFO: - 1: 0x49
+ INFO: - 2: 0x50
+ INFO: - 3: 0x60
+ INFO: - 4: 0x78
+ NOTICE: acpu_dvfs_set_freq: set acpu freq success!INFO: BL2: Loading image id 2
+ INFO: Loading image id=2 at address 0x1000000
+ INFO: Image id=2 loaded: 0x1000000 - 0x1023d00
+ INFO: hisi_mcu_load_image: mcu sections 0:
+ INFO: hisi_mcu_load_image: src = 0x1000200
+ INFO: hisi_mcu_load_image: dst = 0xf6000000
+ INFO: hisi_mcu_load_image: size = 31184
+ INFO: hisi_mcu_load_image: [SRC 0x1000200] 0x8000 0x3701 0x7695 0x7689
+ INFO: hisi_mcu_load_image: [DST 0xf6000000] 0x8000 0x3701 0x7695 0x7689
+ INFO: hisi_mcu_load_image: mcu sections 1:
+ INFO: hisi_mcu_load_image: src = 0x1007bd0
+ INFO: hisi_mcu_load_image: dst = 0x5e00000
+ INFO: hisi_mcu_load_image: size = 93828
+ INFO: hisi_mcu_load_image: [SRC 0x1007bd0] 0xf000b510 0x2103fb3d 0xf0004604 0xf003fb57
+ INFO: hisi_mcu_load_image: [DST 0x5e00000] 0xf000b510 0x2103fb3d 0xf0004604 0xf003fb57
+ INFO: hisi_mcu_load_image: mcu sections 2:
+ INFO: hisi_mcu_load_image: src = 0x101ea54
+ INFO: hisi_mcu_load_image: dst = 0x5e16e84
+ INFO: hisi_mcu_load_image: size = 15428
+ INFO: hisi_mcu_load_image: [SRC 0x101ea54] 0x9 0x1020640 0x10001 0x8f0d180
+ INFO: hisi_mcu_load_image: [DST 0x5e16e84] 0x9 0x1020640 0x10001 0x8f0d180
+ INFO: hisi_mcu_load_image: mcu sections 3:
+ INFO: hisi_mcu_load_image: src = 0x1022698
+ INFO: hisi_mcu_load_image: dst = 0x5e22a10
+ INFO: hisi_mcu_load_image: size = 3060
+ INFO: hisi_mcu_load_image: [SRC 0x1022698] 0x0 0x0 0x0 0x0
+ INFO: hisi_mcu_load_image: [DST 0x5e22a10] 0x0 0x0 0x0 0x0
+ INFO: hisi_mcu_load_image: mcu sections 4:
+ INFO: hisi_mcu_load_image: src = 0x102328c
+ INFO: hisi_mcu_load_image: dst = 0x5e23604
+ INFO: hisi_mcu_load_image: size = 2616
+ INFO: hisi_mcu_load_image: [SRC 0x102328c] 0xf80000a0 0x0 0xf80000ac 0x0
+ INFO: hisi_mcu_load_image: [DST 0x5e23604] 0xf80000a0 0x0 0xf80000ac 0x0
+ INFO: hisi_mcu_start_run: AO_SC_SYS_CTRL2=0
+ INFO: plat_hikey_bl2_handle_scp_bl2: MCU PC is at 0x42933301
+ INFO: plat_hikey_bl2_handle_scp_bl2: AO_SC_PERIPH_CLKSTAT4 is 0x3b018f09
+ WARNING: BL2: Platform setup already done!!
+ INFO: BL2: Loading image id 3
+ INFO: Loading image id=3 at address 0xf9858000
+ INFO: Image id=3 loaded: 0xf9858000 - 0xf9860058
+ INFO: BL2: Loading image id 5
+ INFO: Loading image id=5 at address 0x35000000
+ INFO: Image id=5 loaded: 0x35000000 - 0x35061cd2
+ NOTICE: BL2: Booting BL31
+ INFO: Entry point address = 0xf9858000
+ INFO: SPSR = 0x3cd
+ NOTICE: BL31: v1.5(debug):v1.5-694-g6d4f6aea
+ NOTICE: BL31: Built : 09:21:44, Aug 29 2018
+ WARNING: Using deprecated integer interrupt array in gicv2_driver_data_t
+ WARNING: Please migrate to using an interrupt_prop_t array
+ INFO: ARM GICv2 driver initialized
+ INFO: BL31: Initializing runtime services
+ INFO: BL31: cortex_a53: CPU workaround for disable_non_temporal_hint was applied
+ INFO: BL31: cortex_a53: CPU workaround for 843419 was applied
+ INFO: BL31: cortex_a53: CPU workaround for 855873 was applied
+ INFO: BL31: Preparing for EL3 exit to normal world
+ INFO: Entry point address = 0x35000000
+ INFO: SPSR = 0x3c9
+
+ U-Boot 2018.09-rc1 (Aug 22 2018 - 14:55:49 +0530)hikey
+
+ DRAM: 990 MiB
+ HI6553 PMIC init
+ MMC: config_sd_carddetect: SD card present
+ Hisilicon DWMMC: 0, Hisilicon DWMMC: 1
+ Loading Environment from FAT... Unable to use mmc 1:1... Failed (-5)
+ In: uart@f7113000
+ Out: uart@f7113000
+ Err: uart@f7113000
+ Net: Net Initialization Skipped
+ No ethernet found.
+ Hit any key to stop autoboot: 0
+ starting USB...
+ USB0: scanning bus 0 for devices... 2 USB Device(s) found
+ scanning usb for storage devices... 0 Storage Device(s) found
+ scanning usb for ethernet devices... 0 Ethernet Device(s) found
diff --git a/doc/board/hisilicon/hikey960.rst b/doc/board/hisilicon/hikey960.rst
new file mode 100644
index 0000000..93e983b
--- /dev/null
+++ b/doc/board/hisilicon/hikey960.rst
@@ -0,0 +1,284 @@
+.. SPDX-License-Identifier: GPL-2.0-or-later
+
+HiKey960 board
+##############
+
+Introduction
+============
+
+HiKey960 is one of the 96Boards Consumer Edition board from HiSilicon.
+The board/SoC has:
+
+* HiSilicon Kirin960 (HI3660) SoC with 4xCortex-A73 and 4xCortex-A53
+* ARM Mali G71 MP8 GPU
+* 3GB LPDDR4 SDRAM
+* 32GB UFS Flash Storage
+* microSD
+* 802.11a/b/g/n WiFi, Bluetooth
+
+More information about this board can be found in 96Boards website:
+https://www.96boards.org/product/hikey960/
+
+Currently the u-boot port supports:
+
+* SD card
+
+Compile from source
+===================
+
+First get all the sources
+
+.. code-block:: bash
+
+ mkdir -p ~/hikey960/src ~/hikey960/bin
+ cd ~/hikey960/src
+ git clone https://github.com/ARM-software/arm-trusted-firmware
+ git clone https://github.com/96boards-hikey/OpenPlatformPkg -b testing/hikey960_v1.3.4
+ git clone https://github.com/96boards-hikey/l-loader -b testing/hikey960_v1.2
+ wget http://snapshots.linaro.org/reference-platform/components/uefi-staging/123/hikey960/release/config
+ wget http://snapshots.linaro.org/reference-platform/components/uefi-staging/123/hikey960/release/hisi-sec_usb_xloader.img
+ wget http://snapshots.linaro.org/reference-platform/components/uefi-staging/123/hikey960/release/hisi-sec_uce_boot.img
+ wget http://snapshots.linaro.org/reference-platform/components/uefi-staging/123/hikey960/release/hisi-sec_xloader.img
+ wget http://snapshots.linaro.org/reference-platform/components/uefi-staging/123/hikey960/release/recovery.bin
+ wget http://snapshots.linaro.org/reference-platform/components/uefi-staging/123/hikey960/release/hikey_idt
+
+Get the SCP_BL2 lpm3.img binary. It is shipped as part of the UEFI source.
+The latest version can be obtained from the OpenPlatformPkg repo.
+
+.. code-block:: bash
+
+ cp OpenPlatformPkg/Platforms/Hisilicon/HiKey960/Binary/lpm3.img ~/hikey960/bin/
+
+Compile U-Boot
+==============
+
+.. code-block:: bash
+
+ cd ~/hikey960/src/u-boot
+ make CROSS_COMPILE=aarch64-linux-gnu- hikey960_defconfig
+ make CROSS_COMPILE=aarch64-linux-gnu-
+ cp u-boot.bin ~/hikey960/bin/
+
+Compile ARM Trusted Firmware (ATF)
+==================================
+
+.. code-block:: bash
+
+ cd ~/hikey960/src/arm-trusted-firmware
+ make CROSS_COMPILE=aarch64-linux-gnu- all fip \
+ SCP_BL2=~/hikey960/bin/lpm3.img \
+ BL33=~/hikey960/bin/u-boot.bin DEBUG=1 PLAT=hikey960
+
+Copy the resulting FIP binary
+
+.. code-block:: bash
+
+ cp build/hikey960/debug/fip.bin ~/hikey960/bin
+
+Compile l-loader
+================
+
+.. code-block:: bash
+
+ cd ~/hikey960/src/l-loader
+ ln -sf ~/hikey960/src/arm-trusted-firmware/build/hikey960/debug/bl1.bin
+ ln -sf ~/hikey960/src/arm-trusted-firmware/build/hikey960/debug/bl2.bin
+ ln -sf ~/hikey960/src/arm-trusted-firmware/build/hikey960/debug/fip.bin
+ ln -sf ~/hikey960/bin/u-boot.bin
+ make hikey960 PTABLE_LST=linux-32g NS_BL1U=u-boot.bin
+
+Copy the resulting binaries
+
+.. code-block:: bash
+
+ cp *.img ~/hikey960/bin
+ cp l-loader.bin ~/hikey960/bin
+
+These instructions are adapted from
+https://github.com/ARM-software/arm-trusted-firmware/blob/master/docs/plat/hikey960.rst
+
+Setup console
+=============
+
+Install ser2net. Use telnet as the console since UEFI in recovery mode
+output window fails to display in minicom.
+
+.. code-block:: bash
+
+ sudo apt-get install ser2net
+
+Configure ser2net
+
+.. code-block:: bash
+
+ sudo vi /etc/ser2net.conf
+
+Append one line for serial-over-USB in #ser2net.conf
+
+ 2004:telnet:0:/dev/ttyUSB0:115200 8DATABITS NONE 1STOPBIT banner
+
+Start ser2net
+
+.. code-block:: bash
+
+ sudo killall ser2net
+ sudo ser2net -u
+
+Open the console.
+
+.. code-block:: bash
+
+ telnet localhost 2004
+
+And you could open the console remotely, too.
+
+Flashing
+========
+
+1. Boot Hikey960 into recovery mode as per the below document:
+https://github.com/96boards/documentation/blob/master/consumer/hikey/hikey960/installation/board-recovery.md
+
+Once Hikey960 is in recovery mode, flash the recovery binary:
+
+.. code-block:: bash
+
+ cd ~/hikey960/src
+ chmod +x ./hikey_idt
+ sudo ./hikey_idt -c config -p /dev/ttyUSB1
+
+Now move to the Hikey960 console and press `f` during UEFI boot. This
+will allow the board to boot into fastboot mode. Once the board is in
+fastboot mode, you should see the ID of the HiKey960 board using the
+following command
+
+.. code-block:: bash
+
+ sudo fastboot devices
+
+ 1ED3822A018E3372 fastboot
+
+3. Flash the images
+
+Now, the images can be flashed using fastboot:
+
+.. code-block:: bash
+
+ sudo fastboot flash ptable ~/hikey960/bin/prm_ptable.img
+ sudo fastboot flash xloader ~/hikey960/bin/hisi-sec_xloader.img
+ sudo fastboot flash fastboot ~/hikey960/bin/l-loader.bin
+ sudo fastboot flash fip ~/hikey960/bin/fip.bin
+
+4. Set the "Boot Mode" switch to OFF position for normal boot mode.
+Then power on HiKey960
+
+Observe the console traces using UART6 on the Low Speed Expansion header::
+
+ NOTICE: BL2: v2.1(debug):v2.1-531-g3ee48f40
+ NOTICE: BL2: Built : 18:15:58, Aug 2 2019
+ INFO: BL2: Doing platform setup
+ INFO: UFS LUN0 contains 1024 blocks with 4096-byte size
+ INFO: UFS LUN1 contains 1024 blocks with 4096-byte size
+ INFO: UFS LUN2 contains 2048 blocks with 4096-byte size
+ INFO: UFS LUN3 contains 7805952 blocks with 4096-byte size
+ INFO: ufs: change power mode success
+ INFO: BL2: Loading image id 2
+ INFO: Loading image id=2 at address 0x89c80000
+ INFO: Image id=2 loaded: 0x89c80000 - 0x89cb5088
+ INFO: BL2: Initiating SCP_BL2 transfer to SCP
+ INFO: BL2: SCP_BL2: 0x89c80000@0x35088
+ INFO: BL2: SCP_BL2 HEAD:
+ INFO: BL2: SCP_BL2 0x7000 0x179 0x159 0x149
+ INFO: BL2: SCP_BL2 0x189 0x18b 0x18d 0x0
+ INFO: BL2: SCP_BL2 0x0 0x0 0x0 0x18f
+ INFO: BL2: SCP_BL2 0x191 0x0 0x193 0x195
+ INFO: BL2: SCP_BL2 0x18fd 0x18fd 0x18fd 0x18fd
+ INFO: BL2: SCP_BL2 0x18fd 0x18fd 0x18fd 0x18fd
+ INFO: BL2: SCP_BL2 0x18fd 0x18fd 0x18fd 0x18fd
+ INFO: BL2: SCP_BL2 0x4d454355 0x43494741 0x424d554e 0x21215245
+ INFO: BL2: SCP_BL2 0x4a054904 0x42912000 0xf841bfbc 0xe7fa0b04
+ INFO: BL2: SCP_BL2 0xb88cf000 0x3b18 0x3d1c 0x6809493e
+ INFO: BL2: SCP_BL2 0x4613680a 0x201f102 0xf0002a04 0x600a804c
+ INFO: BL2: SCP_BL2 0x204f04f 0xf203fb02 0xf102440a 0x60100204
+ INFO: BL2: SCP_BL2 0x160f04f 0xf103fb01 0x68004834 0x61044408
+ INFO: BL2: SCP_BL2 0x61866145 0xf8c061c7 0xf8c08020 0xf8c09024
+ INFO: BL2: SCP_BL2 0xf8c0a028 0xf3efb02c 0xf3ef8208 0x68118309
+ INFO: BL2: SCP_BL2 0xf1026401 0xf0110204 0xbf070f04 0x46113220
+ INFO: BL2: SCP_BL2 TAIL:
+ INFO: BL2: SCP_BL2 0x0 0x0 0x0 0x0
+ INFO: BL2: SCP_BL2 0x0 0x0 0x0 0x0
+ INFO: BL2: SCP_BL2 0x0 0x0 0x0 0x0
+ INFO: BL2: SCP_BL2 0x0 0x0 0x0 0x0
+ INFO: BL2: SCP_BL2 0x0 0x0 0x0 0x0
+ INFO: BL2: SCP_BL2 0x0 0x0 0x0 0x0
+ INFO: BL2: SCP_BL2 0x0 0x0 0x0 0x0
+ INFO: BL2: SCP_BL2 0x0 0x0 0x0 0x0
+ INFO: BL2: SCP_BL2 0x0 0x0 0x0 0x0
+ INFO: BL2: SCP_BL2 0x0 0x0 0x0 0x0
+ INFO: BL2: SCP_BL2 0x0 0x19cad151 0x19b80040 0x0
+ INFO: BL2: SCP_BL2 0x0 0x0 0x0 0x0
+ INFO: BL2: SCP_BL2 0x0 0x0 0x0 0x0
+ INFO: BL2: SCP_BL2 0x0 0x0 0x0 0x0
+ INFO: BL2: SCP_BL2 0x0 0x0 0x0 0x0
+ INFO: BL2: SCP_BL2 0x0 0x0 0x0 0x0
+ INFO: BL2: SCP_BL2 transferred to SCP
+ INFO: start fw loading
+ INFO: fw load success
+ WARNING: BL2: Platform setup already done!!
+ INFO: BL2: Loading image id 3
+ INFO: Loading image id=3 at address 0x1ac58000
+ INFO: Image id=3 loaded: 0x1ac58000 - 0x1ac63024
+ INFO: BL2: Loading image id 5
+ INFO: Loading image id=5 at address 0x1ac98000
+ INFO: Image id=5 loaded: 0x1ac98000 - 0x1ad0819c
+ NOTICE: BL2: Booting BL31
+ INFO: Entry point address = 0x1ac58000
+ INFO: SPSR = 0x3cd
+ NOTICE: BL31: v2.1(debug):v2.1-531-g3ee48f40
+ NOTICE: BL31: Built : 18:16:01, Aug 2 2019
+ INFO: ARM GICv2 driver initialized
+ INFO: BL31: Initializing runtime services
+ INFO: BL31: cortex_a53: CPU workaround for 855873 was applied
+ INFO: plat_setup_psci_ops: sec_entrypoint=0x1ac580fc
+ INFO: BL31: Preparing for EL3 exit to normal world
+ INFO: Entry point address = 0x1ac98000
+ INFO: SPSR = 0x3c9
+
+ U-Boot 2019.07-00628-g286f05a6fc-dirty (Aug 02 2019 - 17:14:05 +0530)
+ Hikey960
+
+ DRAM: 3 GiB
+ PSCI: v1.1
+ MMC: dwmmc1@ff37f000: 0
+ Loading Environment from EXT4... ** File not found /uboot.env **
+
+ ** Unable to read "/uboot.env" from mmc0:2 **
+ In: serial@fff32000
+ Out: serial@fff32000
+ Err: serial@fff32000
+ Net: Net Initialization Skipped
+ No ethernet found.
+ Hit any key to stop autoboot: 0
+ switch to partitions #0, OK
+ mmc0 is current device
+ Scanning mmc 0:1...
+ Found /extlinux/extlinux.conf
+ Retrieving file: /extlinux/extlinux.conf
+ 201 bytes read in 12 ms (15.6 KiB/s)
+ 1: hikey960-kernel
+ Retrieving file: /Image
+ 24689152 bytes read in 4377 ms (5.4 MiB/s)
+ append: earlycon=pl011,mmio32,0xfff32000 console=ttyAMA6,115200 rw root=/dev/mmcblk0p2 rot
+ Retrieving file: /hi3660-hikey960.dtb
+ 35047 bytes read in 14 ms (2.4 MiB/s)
+ ## Flattened Device Tree blob at 10000000
+ Booting using the fdt blob at 0x10000000
+ Using Device Tree in place at 0000000010000000, end 000000001000b8e6
+
+ Starting kernel ...
+
+ [ 0.000000] Booting Linux on physical CPU 0x0000000000 [0x410fd034]
+ [ 0.000000] Linux version 5.2.0-03138-gd75da80dce39 (mani@Mani-XPS-13-9360) (gcc versi9
+ [ 0.000000] Machine model: HiKey960
+ [ 0.000000] earlycon: pl11 at MMIO32 0x00000000fff32000 (options '')
+ [ 0.000000] printk: bootconsole [pl11] enabled
+ [ 0.000000] efi: Getting EFI parameters from FDT:
diff --git a/doc/board/hisilicon/index.rst b/doc/board/hisilicon/index.rst
new file mode 100644
index 0000000..5455b76
--- /dev/null
+++ b/doc/board/hisilicon/index.rst
@@ -0,0 +1,11 @@
+.. SPDX-License-Identifier: GPL-2.0-or-later
+
+HiSilicon
+=========
+
+.. toctree::
+ :maxdepth: 2
+
+ hikey
+ hikey960
+ poplar
diff --git a/doc/board/hisilicon/poplar.rst b/doc/board/hisilicon/poplar.rst
new file mode 100644
index 0000000..0fccc14
--- /dev/null
+++ b/doc/board/hisilicon/poplar.rst
@@ -0,0 +1,302 @@
+.. SPDX-License-Identifier: GPL-2.0-or-later
+
+Poplar board
+############
+
+Board Information
+=================
+
+Developed by HiSilicon, the board features the Hi3798C V200 with an
+integrated quad-core 64-bit ARM Cortex A53 processor and high
+performance Mali T720 GPU, making it capable of running any commercial
+set-top solution based on Linux or Android. Its high performance
+specification also supports a premium user experience with up to H.265
+HEVC decoding of 4K video at 60 frames per second.
+
+* SOC Hisilicon Hi3798CV200
+* CPU Quad-core ARM Cortex-A53 64 bit
+* DRAM DDR3/3L/4 SDRAM interface, maximum 32-bit data width 2 GB
+* USB Two USB 2.0 ports One USB 3.0 ports
+* CONSOLE USB-micro port for console support
+* ETHERNET 1 GBe Ethernet
+* PCIE One PCIe 2.0 interfaces
+* JTAG 8-Pin JTAG
+* EXPANSION INTERFACE Linaro 96Boards Low Speed Expansion slot
+* DIMENSION Standard 160×120 mm 96Boards Enterprice Edition form factor
+* WIFI 802.11AC 2*2 with Bluetooth
+* CONNECTORS One connector for Smart Card One connector for TSI
+
+Build instructions
+==================
+
+.. note::
+
+ U-Boot has a **strong** dependency with the l-loader and the ARM trusted
+ firmware repositories.
+
+The boot sequence is::
+
+ l-loader --> arm_trusted_firmware --> U-Boot
+
+U-Boot needs to be aware of the BL31 runtime location and size to avoid writing
+over it. Currently, BL31 is being placed below the kernel text offset (check
+poplar.c) but this could change in the future.
+
+The current version of U-Boot has been tested with
+
+- https://github.com/Linaro/poplar-l-loader.git::
+
+ commit f0988698dcc5c08bd0a8f50aa0457e138a5f438c
+ Author: Alex Elder <elder@linaro.org>
+ Date: Fri Jun 16 08:57:59 2017 -0500
+
+ l-loader: use external memory region definitions
+
+ The ARM Trusted Firmware code now has a header file that collects
+ all the definitions for the memory regions used for its boot stages.
+ Include that file where needed, and use the definitions found therein
+
+ Signed-off-by: Alex Elder <elder@linaro.org>
+
+- https://github.com/Linaro/poplar-arm-trusted-firmware.git::
+
+ commit 6ac42dd3be13c99aa8ce29a15073e2f19d935f68
+ Author: Alex Elder <elder@linaro.org>
+ Date: Fri Jun 16 09:24:50 2017 -0500
+
+ poplar: define memory regions in a separate file
+
+ Separate the definitions for memory regions used for the BL stage
+ images and FIP into a new file. The "l-loader" image uses knowledge
+ of the sizes and locations of these memory regions, and it can now
+ include this (external) header to get these definitions, rather than
+ having to make coordinated changes to both code bases.
+
+ The new file has a complete set of definitions (more than may be
+ required by one or the other user). It also includes a summary of
+ how the boot process works, and how it uses these regions.
+
+ It should now be relatively easy to adjust the sizes and locations
+ of these memory regions, or to add to them (e.g. for TEE).
+
+ Signed-off-by: Alex Elder <elder@linaro.org>
+
+
+Compile from source
+-------------------
+
+Get all the sources
+
+.. code-block:: bash
+
+ mkdir -p ~/poplar/src ~/poplar/bin
+ cd ~/poplar/src
+ git clone https://github.com/Linaro/poplar-l-loader.git l-loader
+ git clone https://github.com/Linaro/poplar-arm-trusted-firmware.git atf
+ git clone https://github.com/Linaro/poplar-U-Boot.git U-Boot
+
+Make sure you are using the correct branch on each one of these repositories.
+The definition of "correct" might change over time (at this moment in time this
+would be the "latest" branch).
+
+Compile U-Boot
+~~~~~~~~~~~~~~
+
+Prerequisite:
+
+.. code-block:: bash
+
+ sudo apt-get install device-tree-compiler
+
+.. code-block:: bash
+
+ cd ~/poplar/src/U-Boot
+ make CROSS_COMPILE=aarch64-linux-gnu- poplar_defconfig
+ make CROSS_COMPILE=aarch64-linux-gnu-
+ cp U-Boot.bin ~/poplar/bin
+
+Compile ARM Trusted Firmware (ATF)
+~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
+
+.. code-block:: bash
+
+ cd ~/poplar/src/atf
+ make CROSS_COMPILE=aarch64-linux-gnu- all fip \
+ SPD=none BL33=~/poplar/bin/U-Boot.bin DEBUG=1 PLAT=poplar
+
+Copy resulting binaries
+
+.. code-block:: bash
+
+ cp build/hi3798cv200/debug/bl1.bin ~/poplar/src/l-loader/atf/
+ cp build/hi3798cv200/debug/fip.bin ~/poplar/src/l-loader/atf/
+
+Compile l-loader
+~~~~~~~~~~~~~~~~
+
+.. code-block:: bash
+
+ cd ~/poplar/src/l-loader
+ make clean
+ make CROSS_COMPILE=arm-linux-gnueabi-
+
+Due to BootROM requiremets, rename l-loader.bin to fastboot.bin:
+
+.. code-block:: bash
+
+ cp l-loader.bin ~/poplar/bin/fastboot.bin
+
+Flash instructions
+==================
+
+Two methods:
+
+Using USB debrick support
+ Copy fastboot.bin to a FAT partition on the USB drive and reboot the
+ poplar board while pressing S3(usb_boot).
+
+ The system will execute the new U-Boot and boot into a shell which you
+ can then use to write to eMMC.
+
+Using U-BOOT from shell
+ 1) using AXIS usb ethernet dongle and tftp
+ 2) using FAT formated USB drive
+
+Flash using TFTP (USB ethernet dongle)
+--------------------------------------
+
+Plug a USB AXIS ethernet dongle on any of the USB2 ports on the Poplar board.
+Copy fastboot.bin to your tftp server.
+In U-Boot make sure your network is properly setup.
+
+Then::
+
+ => tftp 0x30000000 fastboot.bin
+ starting USB...
+ USB0: USB EHCI 1.00
+ scanning bus 0 for devices... 1 USB Device(s) found
+ USB1: USB EHCI 1.00
+ scanning bus 1 for devices... 3 USB Device(s) found
+ scanning usb for storage devices... 0 Storage Device(s) found
+ scanning usb for ethernet devices... 1 Ethernet Device(s) found
+ Waiting for Ethernet connection... done.
+ Using asx0 device
+ TFTP from server 192.168.1.4; our IP address is 192.168.1.10
+ Filename 'poplar/fastboot.bin'.
+ Load address: 0x30000000
+ Loading: #################################################################
+ #################################################################
+ ###############################################################
+ 2 MiB/s
+ done
+ Bytes transferred = 983040 (f0000 hex)
+
+ => mmc write 0x30000000 0 0x780
+
+ MMC write: dev # 0, block # 0, count 1920 ... 1920 blocks written: OK
+ => reset
+
+Flash using USB FAT drive
+-------------------------
+
+Copy fastboot.bin to any partition on a FAT32 formated usb flash drive.
+Enter the uboot prompt::
+
+ => fatls usb 0:2
+ 983040 fastboot.bin
+
+ 1 file(s), 0 dir(s)
+
+ => fatload usb 0:2 0x30000000 fastboot.bin
+ reading fastboot.bin
+ 983040 bytes read in 44 ms (21.3 MiB/s)
+
+ => mmc write 0x30000000 0 0x780
+
+ MMC write: dev # 0, block # 0, count 1920 ... 1920 blocks written: OK
+
+Boot trace
+==========
+
+::
+
+ Bootrom start
+ Boot Media: eMMC
+ Decrypt auxiliary code ...OK
+
+ lsadc voltage min: 000000FE, max: 000000FF, aver: 000000FE, index: 00000000
+
+ Entry boot auxiliary code
+
+ Auxiliary code - v1.00
+ DDR code - V1.1.2 20160205
+ Build: Mar 24 2016 - 17:09:44
+ Reg Version: v134
+ Reg Time: 2016/03/18 09:44:55
+ Reg Name: hi3798cv2dmb_hi3798cv200_ddr3_2gbyte_8bitx4_4layers.reg
+
+ Boot auxiliary code success
+ Bootrom success
+
+ LOADER: Switched to aarch64 mode
+ LOADER: Entering ARM TRUSTED FIRMWARE
+ LOADER: CPU0 executes at 0x000ce000
+
+ INFO: BL1: 0xe1000 - 0xe7000 [size = 24576]
+ NOTICE: Booting Trusted Firmware
+ NOTICE: BL1: v1.3(debug):v1.3-372-g1ba9c60
+ NOTICE: BL1: Built : 17:51:33, Apr 30 2017
+ INFO: BL1: RAM 0xe1000 - 0xe7000
+ INFO: BL1: Loading BL2
+ INFO: Loading image id=1 at address 0xe9000
+ INFO: Image id=1 loaded at address 0xe9000, size = 0x5008
+ NOTICE: BL1: Booting BL2
+ INFO: Entry point address = 0xe9000
+ INFO: SPSR = 0x3c5
+ NOTICE: BL2: v1.3(debug):v1.3-372-g1ba9c60
+ NOTICE: BL2: Built : 17:51:33, Apr 30 2017
+ INFO: BL2: Loading BL31
+ INFO: Loading image id=3 at address 0x129000
+ INFO: Image id=3 loaded at address 0x129000, size = 0x8038
+ INFO: BL2: Loading BL33
+ INFO: Loading image id=5 at address 0x37000000
+ INFO: Image id=5 loaded at address 0x37000000, size = 0x58f17
+ NOTICE: BL1: Booting BL31
+ INFO: Entry point address = 0x129000
+ INFO: SPSR = 0x3cd
+ INFO: Boot bl33 from 0x37000000 for 364311 Bytes
+ NOTICE: BL31: v1.3(debug):v1.3-372-g1ba9c60
+ NOTICE: BL31: Built : 17:51:33, Apr 30 2017
+ INFO: BL31: Initializing runtime services
+ INFO: BL31: Preparing for EL3 exit to normal world
+ INFO: Entry point address = 0x37000000
+ INFO: SPSR = 0x3c9
+
+ U-Boot 2017.05-rc2-00130-gd2255b0 (Apr 30 2017 - 17:51:28 +0200)poplar
+
+ Model: HiSilicon Poplar Development Board
+ BOARD: Hisilicon HI3798cv200 Poplar
+ DRAM: 1 GiB
+ MMC: Hisilicon DWMMC: 0
+ In: serial@f8b00000
+ Out: serial@f8b00000
+ Err: serial@f8b00000
+ Net: Net Initialization Skipped
+ No ethernet found.
+
+ Hit any key to stop autoboot: 0
+ starting USB...
+ USB0: USB EHCI 1.00
+ scanning bus 0 for devices... 1 USB Device(s) found
+ USB1: USB EHCI 1.00
+ scanning bus 1 for devices... 4 USB Device(s) found
+ scanning usb for storage devices... 1 Storage Device(s) found
+ scanning usb for ethernet devices... 1 Ethernet Device(s) found
+
+ USB device 0:
+ Device 0: Vendor: SanDisk Rev: 1.00 Prod: Cruzer Blade
+ Type: Removable Hard Disk
+ Capacity: 7632.0 MB = 7.4 GB (15630336 x 512)
+ ... is now current device
+ Scanning usb 0:1...
+ =>
diff --git a/doc/board/index.rst b/doc/board/index.rst
index 35dd3bc..c96e5fd 100644
--- a/doc/board/index.rst
+++ b/doc/board/index.rst
@@ -17,6 +17,7 @@
asus/index
atmel/index
beacon/index
+ beagle/index
broadcom/index
bsh/index
cloos/index
@@ -26,6 +27,7 @@
gateworks/index
google/index
highbank/index
+ hisilicon/index
htc/index
intel/index
kontron/index
diff --git a/doc/board/mediatek/index.rst b/doc/board/mediatek/index.rst
index 38cd8cb..c55d5ae 100644
--- a/doc/board/mediatek/index.rst
+++ b/doc/board/mediatek/index.rst
@@ -1,7 +1,7 @@
.. SPDX-License-Identifier: GPL-2.0+
Mediatek
-=========
+========
.. toctree::
:maxdepth: 2
diff --git a/doc/board/nxp/imx8mm_evk.rst b/doc/board/nxp/imx8mm_evk.rst
index 327ce6e..bb11029 100644
--- a/doc/board/nxp/imx8mm_evk.rst
+++ b/doc/board/nxp/imx8mm_evk.rst
@@ -36,7 +36,7 @@
$ cp firmware-imx-8.9/firmware/ddr/synopsys/lpddr4*.bin $(builddir)
Build U-Boot for sd card
---------------------------
+------------------------
.. code-block:: bash
@@ -54,8 +54,8 @@
----
Set Boot switch to SD boot
-Build U-Boot for qspi flash card
-------------------------------------
+Build U-Boot for qspi flash card
+--------------------------------
.. code-block:: bash
@@ -81,7 +81,8 @@
$ sf write $loadaddr 0x00 <size_of_flash.bin_in_hex>
Boot from QSPI Flash
------------------------
+--------------------
+
Set Boot Switch to QSPI Flash
Pin configuration for imx8mm_revC evk to boot from qspi flash
diff --git a/doc/board/nxp/ls1046ardb.rst b/doc/board/nxp/ls1046ardb.rst
index 49b4842..8c0bc82 100644
--- a/doc/board/nxp/ls1046ardb.rst
+++ b/doc/board/nxp/ls1046ardb.rst
@@ -54,7 +54,7 @@
- ARM JTAG support
Memory map from core's view
-----------------------------
+---------------------------
================== ================== ================ =====
Start Address End Address Description Size
diff --git a/doc/board/nxp/mx6ul_14x14_evk.rst b/doc/board/nxp/mx6ul_14x14_evk.rst
index 3e57ba1..c135a21 100644
--- a/doc/board/nxp/mx6ul_14x14_evk.rst
+++ b/doc/board/nxp/mx6ul_14x14_evk.rst
@@ -4,7 +4,7 @@
===============
How to use U-Boot on Freescale MX6UL 14x14 EVK
------------------------------------------------
+----------------------------------------------
- Build U-Boot for MX6UL 14x14 EVK:
diff --git a/doc/board/openpiton/riscv64.rst b/doc/board/openpiton/riscv64.rst
index 3a97793..c379fbf 100644
--- a/doc/board/openpiton/riscv64.rst
+++ b/doc/board/openpiton/riscv64.rst
@@ -11,14 +11,14 @@
running full-stack Debian linux.
RISC-V Standard Bootflow
--------------------------
+------------------------
Currently, OpenPiton implements RISC-V standard bootflow in the following steps
mover.S -> u-boot-spl -> opensbi -> u-boot -> Linux
This board supports S-mode u-boot as well as M-mode SPL
Building OpenPition
----------------------
+-------------------
If you'd like to build OpenPiton, please go to OpenPiton github repo
(at https://github.com/PrincetonUniversity/openpiton) to build from the latest
diff --git a/doc/board/purism/librem5.rst b/doc/board/purism/librem5.rst
index fb050c6..a7975e1 100644
--- a/doc/board/purism/librem5.rst
+++ b/doc/board/purism/librem5.rst
@@ -1,7 +1,7 @@
.. SPDX-License-Identifier: GPL-2.0+
Librem5
-==========
+=======
U-Boot for the Purism Librem5 phone
diff --git a/doc/board/qualcomm/sdm845.rst b/doc/board/qualcomm/sdm845.rst
index d3f218e..a65f00d 100644
--- a/doc/board/qualcomm/sdm845.rst
+++ b/doc/board/qualcomm/sdm845.rst
@@ -2,10 +2,11 @@
.. sectionauthor:: Dzmitry Sankouski <dsankouski@gmail.com>
Snapdragon 845
-================
+==============
About this
----------
+
This document describes the information about Qualcomm Snapdragon 845
supported boards and it's usage steps.
@@ -17,8 +18,10 @@
Installation
------------
+
Build
^^^^^
+
Setup ``CROSS_COMPILE`` for aarch64 and build U-Boot for your board::
$ export CROSS_COMPILE=<aarch64 toolchain prefix>
@@ -29,10 +32,12 @@
Generate FIT image
^^^^^^^^^^^^^^^^^^
+
See doc/uImage.FIT for more details
Pack android boot image
^^^^^^^^^^^^^^^^^^^^^^^
+
We'll assemble android boot image with ``u-boot.bin`` instead of linux kernel,
and FIT image instead of ``initramfs``. Android bootloader expect gzipped kernel
with appended dtb, so let's mimic linux to satisfy stock bootloader.
diff --git a/doc/board/rockchip/rockchip.rst b/doc/board/rockchip/rockchip.rst
index ffbebd0..18d0b6f 100644
--- a/doc/board/rockchip/rockchip.rst
+++ b/doc/board/rockchip/rockchip.rst
@@ -116,6 +116,7 @@
- Edgeble Neural Compute Module 6A SoM - Neu6a (neu6a-io-rk3588)
- Edgeble Neural Compute Module 6B SoM - Neu6b (neu6b-io-rk3588)
- FriendlyElec NanoPC-T6 (nanopc-t6-rk3588)
+ - Pine64 QuartzPro64 (quartzpro64-rk3588)
- Radxa ROCK 5A (rock5a-rk3588s)
- Radxa ROCK 5B (rock5b-rk3588)
- Xunlong Orange Pi 5 (orangepi-5-rk3588s)
diff --git a/doc/board/samsung/index.rst b/doc/board/samsung/index.rst
index c904372..971805e 100644
--- a/doc/board/samsung/index.rst
+++ b/doc/board/samsung/index.rst
@@ -1,7 +1,7 @@
.. SPDX-License-Identifier: GPL-2.0+
Samsung
-========
+=======
.. toctree::
:maxdepth: 2
diff --git a/doc/board/st/st-dt.rst b/doc/board/st/st-dt.rst
index 67e16ef..2a285c8 100644
--- a/doc/board/st/st-dt.rst
+++ b/doc/board/st/st-dt.rst
@@ -2,7 +2,7 @@
.. sectionauthor:: Patrick Delaunay <patrick.delaunay@foss.st.com>
U-Boot device tree bindings
-----------------------------
+---------------------------
The U-Boot specific bindings are defined in the U-Boot directory:
doc/device-tree-bindings
diff --git a/doc/board/st/stm32_MCU.rst b/doc/board/st/stm32_MCU.rst
index 7ff7c73..61650bc 100644
--- a/doc/board/st/stm32_MCU.rst
+++ b/doc/board/st/stm32_MCU.rst
@@ -2,7 +2,7 @@
.. sectionauthor:: Patrice Chotard <patrice.chotardy@foss.st.com>
STM32 MCU boards
-=================
+================
This is a quick instruction for setup STM32 MCU boards.
diff --git a/doc/board/starfive/visionfive2.rst b/doc/board/starfive/visionfive2.rst
index 9ee758e..6cb033e 100644
--- a/doc/board/starfive/visionfive2.rst
+++ b/doc/board/starfive/visionfive2.rst
@@ -4,7 +4,8 @@
====================
JH7110 RISC-V SoC
----------------------
+-----------------
+
The JH7110 is 4+1 64-bit RISC-V SoC from StarFive.
The StarFive VisionFive2 development platform is based on JH7110 and capable
diff --git a/doc/board/thead/index.rst b/doc/board/thead/index.rst
index 41566d3..2c4b3fb 100644
--- a/doc/board/thead/index.rst
+++ b/doc/board/thead/index.rst
@@ -1,7 +1,7 @@
.. SPDX-License-Identifier: GPL-2.0+
T-HEAD
-========
+======
.. toctree::
:maxdepth: 1
diff --git a/doc/board/ti/am335x_evm.rst b/doc/board/ti/am335x_evm.rst
index 2ba651e..7a3125d 100644
--- a/doc/board/ti/am335x_evm.rst
+++ b/doc/board/ti/am335x_evm.rst
@@ -59,7 +59,7 @@
devices are part of a secure development package (SECDEV) that can be
downloaded from:
- http://www.ti.com/mysecuresoftware (login required)
+ https://www.ti.com/mysecuresoftware (login required)
The secure development package is access controlled due to NDA and export
control restrictions. Access must be requested and granted by TI before the
@@ -84,8 +84,7 @@
Within the SECDEV package exists an image creation script:
-.. prompt:: bash
- :prompts: $
+.. prompt:: bash $
${TI_SECURE_DEV_PKG}/scripts/create-boot-image.sh
@@ -97,8 +96,7 @@
The script is basically the only required interface to the TI SECDEV
package for creating a bootable SPL image for secure TI devices.
-.. prompt:: bash
- :prompts: $
+.. prompt:: bash $
create-boot-image.sh \
<IMAGE_FLAG> <INPUT_FILE> <OUTPUT_FILE> <SPL_LOAD_ADDR>
@@ -184,8 +182,7 @@
SECDEV package. Within the SECDEV package exists a script to process
an input binary image:
-.. prompt:: bash
- :prompts: $
+.. prompt:: bash $
${TI_SECURE_DEV_PKG}/scripts/secure-binary-image.sh
@@ -206,8 +203,7 @@
Invoking the secure-binary-image script for Secure Devices
^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
-.. prompt:: bash
- :prompts: $
+.. prompt:: bash $
secure-binary-image.sh <INPUT_FILE> <OUTPUT_FILE>
@@ -247,8 +243,7 @@
2. Flashing NAND via MMC/SD
-.. prompt:: bash
- :prompts: =>
+.. prompt:: bash =>
# select BOOTSEL to MMC/SD boot and boot from MMC/SD card
mmc rescan
@@ -334,8 +329,7 @@
write garbage into the area, you must delete it from the partition table
first.
-.. prompt:: bash
- :prompts: =>
+.. prompt:: bash =>
# Ensure we are able to talk with this mmc device
mmc rescan
@@ -366,8 +360,7 @@
afterwards) along with a Falcon Mode aware MLO and the FAT partition has
already been created and marked bootable:
-.. prompt:: bash
- :prompts: =>
+.. prompt:: bash =>
mmc rescan
# Load kernel and device tree into memory, perform export
@@ -386,8 +379,7 @@
So then you:
-.. prompt:: bash
- :prompts: =>
+.. prompt:: bash =>
fatwrite mmc 0:1 0x80f80000 args 8928
@@ -400,8 +392,7 @@
along with a Falcon Mode aware MLO written to the correct locations for
booting and mtdparts have been configured correctly for the board:
-.. prompt:: bash
- :prompts: =>
+.. prompt:: bash =>
nand read ${loadaddr} kernel
load nand rootfs ${fdtaddr} /boot/am335x-evm.dtb
@@ -425,8 +416,7 @@
device, so the user can easily configure their platform differently from
the command line:
-.. prompt:: bash
- :prompts: =>
+.. prompt:: bash =>
dm tree
@@ -444,8 +434,7 @@
Typically here any network command performed using the usb_ether
interface would work, while using other gadgets would fail:
-.. prompt:: bash
- :prompts: =>
+.. prompt:: bash =>
fastboot usb 0
@@ -462,8 +451,7 @@
use the unbind command specifying the class and index parameters (as
shown above in the 'dm tree' output) to target the driver to unbind:
-.. prompt:: bash
- :prompts: =>
+.. prompt:: bash =>
unbind ethernet 1
@@ -471,8 +459,7 @@
first USB device controller, the fastboot gadget will now be able to
bind with it:
-.. prompt:: bash
- :prompts: =>
+.. prompt:: bash =>
dm tree
diff --git a/doc/board/ti/am62ax_sk.rst b/doc/board/ti/am62ax_sk.rst
new file mode 100644
index 0000000..60726b6
--- /dev/null
+++ b/doc/board/ti/am62ax_sk.rst
@@ -0,0 +1,213 @@
+.. SPDX-License-Identifier: GPL-2.0+ OR BSD-3-Clause
+.. sectionauthor:: Jai Luthra <j-luthra@ti.com>
+
+AM62A Platforms
+===============
+
+Introduction:
+-------------
+The AM62A SoC family is built on the K3 Multicore SoC architecture platform,
+providing a deep learning accelerator, multi-camera support with ISP, video
+transcoder and other BOM-saving integrations.
+The AM62A SoC enables cost-sensitive automotive applications including driver
+and in-cabin monitoring systems, next generation of eMirror system, as well as
+a broad set of industrial applications in Factory Automation, Building
+Automation, Robotics and more.
+
+Some highlights of this SoC are:
+
+* Quad-Cortex-A53s (running up to 1.4GHz) in a single cluster.
+* Cortex-R5F for general-purpose or safety usage.
+* Deep Learning Accelerator with Single-core C7x Vector DSP with MMA (up to
+ 1.0GHz).
+* Vision Processing Accelerator (VPAC) with a 315MPixel/s ISP (up to 5MP @
+ 60fps) supporting 16-bit RAW input with RGB-IR separation.
+* 4K Video encoder and decoder for HEVC (Level 5.1 High-tier) and H.264 (Level
+ 5.2) supporting upto 240MPixels/s and MJPEG encoder at 416MPixels/s
+* Single display with 24-bit RGB parallel (DPI) interface supporting upto
+ 165Mhz pixel clock for 2K resolution.
+* Integrated Giga-bit Ethernet switch supporting up to a total of two
+ external ports (TSN capable).
+* 9xUARTs, 5xSPI, 6xI2C, 2xUSB2, 3xCAN-FD, 3x eMMC and SD, GPMC for
+ NAND/FPGA connection, OSPI memory controller, 3xMcASP for audio,
+ 1x CSI-RX-4L for Camera, eCAP/eQEP, ePWM, among other peripherals.
+* Dedicated Centralized System Controller for Security, Power, and
+ Resource Management.
+* Multiple low power modes support, ex: Deep sleep, Standby, MCU-only,
+ enabling battery powered system design.
+
+More details can be found in the Technical Reference Manual:
+https://www.ti.com/lit/pdf/spruj16
+
+Platform information:
+
+* https://www.ti.com/tool/SK-AM62A-LP
+
+Boot Flow:
+----------
+Below is the pictorial representation of boot flow:
+
+.. image:: img/boot_diagram_k3_current.svg
+ :alt: Boot flow diagram
+
+- Here TIFS acts as master and provides all the critical services. R5/A53
+ requests TIFS to get these services done as shown in the above diagram.
+
+Sources:
+--------
+
+.. include:: ../ti/k3.rst
+ :start-after: .. k3_rst_include_start_boot_sources
+ :end-before: .. k3_rst_include_end_boot_sources
+
+Build procedure:
+----------------
+0. Setup the environment variables:
+
+.. include:: ../ti/k3.rst
+ :start-after: .. k3_rst_include_start_common_env_vars_desc
+ :end-before: .. k3_rst_include_end_common_env_vars_desc
+
+.. include:: ../ti/k3.rst
+ :start-after: .. k3_rst_include_start_board_env_vars_desc
+ :end-before: .. k3_rst_include_end_board_env_vars_desc
+
+Set the variables corresponding to this platform:
+
+.. include:: ../ti/k3.rst
+ :start-after: .. k3_rst_include_start_common_env_vars_defn
+ :end-before: .. k3_rst_include_end_common_env_vars_defn
+.. code-block:: bash
+
+ $ export UBOOT_CFG_CORTEXR=am62ax_evm_r5_defconfig
+ $ export UBOOT_CFG_CORTEXA=am62ax_evm_a53_defconfig
+ $ export TFA_BOARD=lite
+ $ # we dont use any extra TFA parameters
+ $ unset TFA_EXTRA_ARGS
+ $ export OPTEE_PLATFORM=k3-am62ax
+ $ # we dont use any extra OPTEE parameters
+ $ unset OPTEE_EXTRA_ARGS
+
+1. Trusted Firmware-A:
+
+.. include:: ../ti/k3.rst
+ :start-after: .. k3_rst_include_start_build_steps_tfa
+ :end-before: .. k3_rst_include_end_build_steps_tfa
+
+2. OP-TEE:
+
+.. include:: ../ti/k3.rst
+ :start-after: .. k3_rst_include_start_build_steps_optee
+ :end-before: .. k3_rst_include_end_build_steps_optee
+
+3. U-Boot:
+
+* 3.1 R5:
+
+.. include:: ../ti/k3.rst
+ :start-after: .. k3_rst_include_start_build_steps_spl_r5
+ :end-before: .. k3_rst_include_end_build_steps_spl_r5
+
+* 3.2 A53:
+
+.. include:: ../ti/k3.rst
+ :start-after: .. k3_rst_include_start_build_steps_uboot
+ :end-before: .. k3_rst_include_end_build_steps_uboot
+
+Target Images
+--------------
+In order to boot we need tiboot3.bin, tispl.bin and u-boot.img. Each SoC
+variant (GP, HS-FS, HS-SE) requires a different source for these files.
+
+ - GP
+
+ * tiboot3-am62ax-gp-evm.bin from step 3.1
+ * tispl.bin_unsigned, u-boot.img_unsigned from step 3.2
+
+ - HS-FS
+
+ * tiboot3-am62ax-hs-fs-evm.bin from step 3.1
+ * tispl.bin, u-boot.img from step 3.2
+
+ - HS-SE
+
+ * tiboot3-am62ax-hs-evm.bin from step 3.1
+ * tispl.bin, u-boot.img from step 3.2
+
+Image formats:
+--------------
+
+- tiboot3.bin
+
+.. image:: img/multi_cert_tiboot3.bin.svg
+ :alt: tiboot3.bin image format
+
+- tispl.bin
+
+.. image:: img/dm_tispl.bin.svg
+ :alt: tispl.bin image format
+
+Switch Setting for Boot Mode
+----------------------------
+
+Boot Mode pins provide means to select the boot mode and options before the
+device is powered up. After every POR, they are the main source to populate
+the Boot Parameter Tables.
+
+The following table shows some common boot modes used on AM62 platform. More
+details can be found in the Technical Reference Manual:
+https://www.ti.com/lit/pdf/spruj16 under the `Boot Mode Pins` section.
+
+.. list-table:: Boot Modes
+ :widths: 16 16 16
+ :header-rows: 1
+
+ * - Switch Label
+ - SW2: 12345678
+ - SW3: 12345678
+
+ * - SD
+ - 01000000
+ - 11000010
+
+ * - OSPI
+ - 00000000
+ - 11001110
+
+ * - EMMC
+ - 00000000
+ - 11010010
+
+ * - UART
+ - 00000000
+ - 11011100
+
+ * - USB DFU
+ - 00000000
+ - 11001010
+
+For SW2 and SW1, the switch state in the "ON" position = 1.
+
+Debugging U-Boot
+----------------
+
+See :ref:`Common Debugging environment - OpenOCD<k3_rst_refer_openocd>`: for
+detailed setup information.
+
+.. warning::
+
+ **OpenOCD support since**: August 2023 (git master)
+
+ Until the next stable release of OpenOCD is available in your development
+ environment's distribution, it might be necessary to build OpenOCD `from the
+ source <https://github.com/openocd-org/openocd>`_.
+
+.. include:: k3.rst
+ :start-after: .. k3_rst_include_start_openocd_connect_XDS110
+ :end-before: .. k3_rst_include_end_openocd_connect_XDS110
+
+To start OpenOCD and connect to the board
+
+.. code-block:: bash
+
+ openocd -f board/ti_am62a7evm.cfg
diff --git a/doc/board/ti/am62x_sk.rst b/doc/board/ti/am62x_sk.rst
index d7437c6..b12dc85 100644
--- a/doc/board/ti/am62x_sk.rst
+++ b/doc/board/ti/am62x_sk.rst
@@ -2,7 +2,7 @@
.. sectionauthor:: Vignesh Raghavendra <vigneshr@ti.com>
AM62 Platforms
-===============
+==============
Introduction:
-------------
@@ -76,15 +76,15 @@
.. include:: ../ti/k3.rst
:start-after: .. k3_rst_include_start_common_env_vars_defn
:end-before: .. k3_rst_include_end_common_env_vars_defn
-.. code-block:: bash
+.. prompt:: bash $
- $ export UBOOT_CFG_CORTEXR=am62x_evm_r5_defconfig
- $ export UBOOT_CFG_CORTEXA=am62x_evm_a53_defconfig
- $ export TFA_BOARD=lite
- $ # we dont use any extra TFA parameters
- $ unset TFA_EXTRA_ARGS
- $ export OPTEE_PLATFORM=k3-am62x
- $ export OPTEE_EXTRA_ARGS="CFG_WITH_SOFTWARE_PRNG=y"
+ export UBOOT_CFG_CORTEXR=am62x_evm_r5_defconfig
+ export UBOOT_CFG_CORTEXA=am62x_evm_a53_defconfig
+ export TFA_BOARD=lite
+ # we dont use any extra TFA parameters
+ unset TFA_EXTRA_ARGS
+ export OPTEE_PLATFORM=k3-am62x
+ export OPTEE_EXTRA_ARGS="CFG_WITH_SOFTWARE_PRNG=y"
.. am62x_evm_rst_include_start_build_steps
@@ -117,7 +117,8 @@
.. am62x_evm_rst_include_end_build_steps
Target Images
---------------
+-------------
+
In order to boot we need tiboot3.bin, tispl.bin and u-boot.img. Each SoC
variant (GP, HS-FS, HS-SE) requires a different source for these files.
@@ -270,6 +271,6 @@
To start OpenOCD and connect to the board
-.. code-block:: bash
+.. prompt:: bash $
openocd -f board/ti_am625evm.cfg
diff --git a/doc/board/ti/am64x_evm.rst b/doc/board/ti/am64x_evm.rst
index db27461..6ae35b3 100644
--- a/doc/board/ti/am64x_evm.rst
+++ b/doc/board/ti/am64x_evm.rst
@@ -65,16 +65,16 @@
.. include:: k3.rst
:start-after: .. k3_rst_include_start_common_env_vars_defn
:end-before: .. k3_rst_include_end_common_env_vars_defn
-.. code-block:: bash
+.. prompt:: bash $
- $ export UBOOT_CFG_CORTEXR=am64x_evm_r5_defconfig
- $ export UBOOT_CFG_CORTEXA=am64x_evm_a53_defconfig
- $ export TFA_BOARD=lite
- $ # we dont use any extra TFA parameters
- $ unset TFA_EXTRA_ARGS
- $ export OPTEE_PLATFORM=k3-am64x
- $ # we dont use any extra TFA parameters
- $ unset OPTEE_EXTRA_ARGS
+ export UBOOT_CFG_CORTEXR=am64x_evm_r5_defconfig
+ export UBOOT_CFG_CORTEXA=am64x_evm_a53_defconfig
+ export TFA_BOARD=lite
+ # we dont use any extra TFA parameters
+ unset TFA_EXTRA_ARGS
+ export OPTEE_PLATFORM=k3-am64x
+ # we dont use any extra TFA parameters
+ unset OPTEE_EXTRA_ARGS
.. am64x_evm_rst_include_start_build_steps
@@ -107,7 +107,8 @@
.. am64x_evm_rst_include_end_build_steps
Target Images
---------------
+-------------
+
In order to boot we need tiboot3.bin, tispl.bin and u-boot.img. Each SoC
variant (GP, HS-FS, HS-SE) requires a different source for these files.
diff --git a/doc/board/ti/am65x_evm.rst b/doc/board/ti/am65x_evm.rst
index 7cebb1c..89011c0 100644
--- a/doc/board/ti/am65x_evm.rst
+++ b/doc/board/ti/am65x_evm.rst
@@ -22,7 +22,7 @@
3. MAIN domain:
* Quad core 64-bit ARM Cortex-A53
-More info can be found in TRM: http://www.ti.com/lit/pdf/spruid7
+More info can be found in TRM: https://www.ti.com/lit/pdf/spruid7
Platform information:
@@ -75,16 +75,16 @@
.. include:: k3.rst
:start-after: .. k3_rst_include_start_common_env_vars_defn
:end-before: .. k3_rst_include_end_common_env_vars_defn
-.. code-block:: bash
+.. prompt:: bash $
- $ export UBOOT_CFG_CORTEXR=am65x_evm_r5_defconfig
- $ export UBOOT_CFG_CORTEXA=am65x_evm_a53_defconfig
- $ export TFA_BOARD=generic
- $ # we dont use any extra TFA parameters
- $ unset TFA_EXTRA_ARGS
- $ export OPTEE_PLATFORM=k3-am65x
- $ # we dont use any extra OP-TEE parameters
- $ unset OPTEE_EXTRA_ARGS
+ export UBOOT_CFG_CORTEXR=am65x_evm_r5_defconfig
+ export UBOOT_CFG_CORTEXA=am65x_evm_a53_defconfig
+ export TFA_BOARD=generic
+ # we dont use any extra TFA parameters
+ unset TFA_EXTRA_ARGS
+ export OPTEE_PLATFORM=k3-am65x
+ # we dont use any extra OP-TEE parameters
+ unset OPTEE_EXTRA_ARGS
.. am65x_evm_rst_include_start_build_steps
@@ -117,7 +117,8 @@
.. am65x_evm_rst_include_end_build_steps
Target Images
---------------
+-------------
+
In order to boot we need tiboot3.bin, sysfw.itb, tispl.bin and u-boot.img.
Each SoC variant (GP and HS) requires a different source for these files.
@@ -159,32 +160,32 @@
u-boot.img, and sysfw.itb from an SD card and write them to the eMMC boot0
partition at respective addresses.
-.. code-block:: text
+.. prompt:: bash =>
- => mmc dev 0 1
- => fatload mmc 1 ${loadaddr} tiboot3.bin
- => mmc write ${loadaddr} 0x0 0x400
- => fatload mmc 1 ${loadaddr} tispl.bin
- => mmc write ${loadaddr} 0x400 0x1000
- => fatload mmc 1 ${loadaddr} u-boot.img
- => mmc write ${loadaddr} 0x1400 0x2000
- => fatload mmc 1 ${loadaddr} sysfw.itb
- => mmc write ${loadaddr} 0x3600 0x800
+ mmc dev 0 1
+ fatload mmc 1 ${loadaddr} tiboot3.bin
+ mmc write ${loadaddr} 0x0 0x400
+ fatload mmc 1 ${loadaddr} tispl.bin
+ mmc write ${loadaddr} 0x400 0x1000
+ fatload mmc 1 ${loadaddr} u-boot.img
+ mmc write ${loadaddr} 0x1400 0x2000
+ fatload mmc 1 ${loadaddr} sysfw.itb
+ mmc write ${loadaddr} 0x3600 0x800
To give the ROM access to the boot partition, the following commands must be
used for the first time:
-.. code-block:: text
+.. prompt:: bash =>
- => mmc partconf 0 1 1 1
- => mmc bootbus 0 1 0 0
+ mmc partconf 0 1 1 1
+ mmc bootbus 0 1 0 0
To create a software partition for the rootfs, the following command can be
used:
-.. code-block:: text
+.. prompt:: bash =>
- => gpt write mmc 0 ${partitions}
+ gpt write mmc 0 ${partitions}
eMMC layout:
@@ -194,11 +195,11 @@
Kernel image and DT are expected to be present in the /boot folder of rootfs.
To boot kernel from eMMC, use the following commands:
-.. code-block:: text
+.. prompt:: bash =>
- => setenv mmcdev 0
- => setenv bootpart 0
- => boot
+ setenv mmcdev 0
+ setenv bootpart 0
+ boot
OSPI:
-----
@@ -210,17 +211,17 @@
and sysfw.itb over tftp and then flash those to OSPI at their respective
addresses.
-.. code-block:: text
+.. prompt:: bash =>
- => sf probe
- => tftp ${loadaddr} tiboot3.bin
- => sf update $loadaddr 0x0 $filesize
- => tftp ${loadaddr} tispl.bin
- => sf update $loadaddr 0x80000 $filesize
- => tftp ${loadaddr} u-boot.img
- => sf update $loadaddr 0x280000 $filesize
- => tftp ${loadaddr} sysfw.itb
- => sf update $loadaddr 0x6C0000 $filesize
+ sf probe
+ tftp ${loadaddr} tiboot3.bin
+ sf update $loadaddr 0x0 $filesize
+ tftp ${loadaddr} tispl.bin
+ sf update $loadaddr 0x80000 $filesize
+ tftp ${loadaddr} u-boot.img
+ sf update $loadaddr 0x280000 $filesize
+ tftp ${loadaddr} sysfw.itb
+ sf update $loadaddr 0x6C0000 $filesize
Flash layout for OSPI:
@@ -233,10 +234,10 @@
To boot kernel from OSPI, at the U-Boot prompt:
-.. code-block:: text
+.. prompt:: bash =>
- => setenv boot ubi
- => boot
+ setenv boot ubi
+ boot
UART:
-----
@@ -280,19 +281,19 @@
Example bash script sequence for running on a Linux host PC feeding all boot
artifacts needed to the device:
-.. code-block:: text
+.. prompt:: bash $
- MCU_DEV=/dev/ttyUSB1
- MAIN_DEV=/dev/ttyUSB0
+ MCU_DEV=/dev/ttyUSB1
+ MAIN_DEV=/dev/ttyUSB0
- stty -F $MCU_DEV 115200 cs8 -cstopb -parenb
- stty -F $MAIN_DEV 115200 cs8 -cstopb -parenb
+ stty -F $MCU_DEV 115200 cs8 -cstopb -parenb
+ stty -F $MAIN_DEV 115200 cs8 -cstopb -parenb
- sb --xmodem tiboot3.bin > $MCU_DEV < $MCU_DEV
- sb --ymodem sysfw.itb > $MCU_DEV < $MCU_DEV
- sb --ymodem tispl.bin > $MAIN_DEV < $MAIN_DEV
- sleep 1
- sb --xmodem u-boot.img > $MAIN_DEV < $MAIN_DEV
+ sb --xmodem tiboot3.bin > $MCU_DEV < $MCU_DEV
+ sb --ymodem sysfw.itb > $MCU_DEV < $MCU_DEV
+ sb --ymodem tispl.bin > $MAIN_DEV < $MAIN_DEV
+ sleep 1
+ sb --xmodem u-boot.img > $MAIN_DEV < $MAIN_DEV
Debugging U-Boot
----------------
@@ -314,6 +315,6 @@
To start OpenOCD and connect to the board
-.. code-block:: bash
+.. prompt:: bash $
openocd -f board/ti_am654evm.cfg
diff --git a/doc/board/ti/dra7xx_evm.rst b/doc/board/ti/dra7xx_evm.rst
index 4503b5e..8e5d955 100644
--- a/doc/board/ti/dra7xx_evm.rst
+++ b/doc/board/ti/dra7xx_evm.rst
@@ -71,8 +71,7 @@
'mmc bootbus' to set the required rate (see TRM) and 'mmc partconfig' to
set boot0 as the boot device.
-.. prompt:: bash
- :prompts: =>
+.. prompt:: bash =>
setenv autoload no
usb start
diff --git a/doc/board/ti/j7200_evm.rst b/doc/board/ti/j7200_evm.rst
index bcf8dc1..d4a823f 100644
--- a/doc/board/ti/j7200_evm.rst
+++ b/doc/board/ti/j7200_evm.rst
@@ -64,16 +64,16 @@
.. include:: k3.rst
:start-after: .. k3_rst_include_start_common_env_vars_defn
:end-before: .. k3_rst_include_end_common_env_vars_defn
-.. code-block:: bash
+.. prompt:: bash $
- $ export UBOOT_CFG_CORTEXR=j7200_evm_r5_defconfig
- $ export UBOOT_CFG_CORTEXA=j7200_evm_a72_defconfig
- $ export TFA_BOARD=generic
- $ # we dont use any extra TFA parameters
- $ unset TFA_EXTRA_ARGS
- $ export OPTEE_PLATFORM=k3-j7200
- $ # we dont use any extra OP-TEE parameters
- $ unset OPTEE_EXTRA_ARGS
+ export UBOOT_CFG_CORTEXR=j7200_evm_r5_defconfig
+ export UBOOT_CFG_CORTEXA=j7200_evm_a72_defconfig
+ export TFA_BOARD=generic
+ # we dont use any extra TFA parameters
+ unset TFA_EXTRA_ARGS
+ export OPTEE_PLATFORM=k3-j7200
+ # we dont use any extra OP-TEE parameters
+ unset OPTEE_EXTRA_ARGS
.. j7200_evm_rst_include_start_build_steps
@@ -106,7 +106,8 @@
.. j7200_evm_rst_include_end_build_steps
Target Images
---------------
+-------------
+
In order to boot we need tiboot3.bin, tispl.bin and u-boot.img. Each SoC
variant (GP, HS-FS, HS-SE) requires a different source for these files.
@@ -225,6 +226,6 @@
To start OpenOCD and connect to the board
-.. code-block:: bash
+.. prompt:: bash $
openocd -f board/ti_j7200evm.cfg
diff --git a/doc/board/ti/j721e_evm.rst b/doc/board/ti/j721e_evm.rst
index cadaac0..a422a9b 100644
--- a/doc/board/ti/j721e_evm.rst
+++ b/doc/board/ti/j721e_evm.rst
@@ -27,7 +27,7 @@
* 2 x C66x Digital signal processor sub system
* C71x Digital signal processor sub-system with MMA.
-More info can be found in TRM: http://www.ti.com/lit/pdf/spruil1
+More info can be found in TRM: https://www.ti.com/lit/pdf/spruil1
Platform information:
@@ -48,7 +48,7 @@
Sources:
--------
-.. include:: k3.rst
+.. include:: ../ti/k3.rst
:start-after: .. k3_rst_include_start_boot_sources
:end-before: .. k3_rst_include_end_boot_sources
@@ -56,42 +56,42 @@
----------------
0. Setup the environment variables:
-.. include:: k3.rst
+.. include:: ../ti/k3.rst
:start-after: .. k3_rst_include_start_common_env_vars_desc
:end-before: .. k3_rst_include_end_common_env_vars_desc
-.. include:: k3.rst
+.. include:: ../ti/k3.rst
:start-after: .. k3_rst_include_start_board_env_vars_desc
:end-before: .. k3_rst_include_end_board_env_vars_desc
Set the variables corresponding to this platform:
-.. include:: k3.rst
+.. include:: ../ti/k3.rst
:start-after: .. k3_rst_include_start_common_env_vars_defn
:end-before: .. k3_rst_include_end_common_env_vars_defn
-.. code-block:: bash
+.. prompt:: bash $
- $ export UBOOT_CFG_CORTEXR=j721e_evm_r5_defconfig
- $ export UBOOT_CFG_CORTEXA=j721e_evm_a72_defconfig
- $ export TFA_BOARD=generic
- $ # we dont use any extra TFA parameters
- $ unset TFA_EXTRA_ARGS
- $ export OPTEE_PLATFORM=k3-j721e
- $ # we dont use any extra OP-TEE parameters
- $ unset OPTEE_EXTRA_ARGS
+ export UBOOT_CFG_CORTEXR=j721e_evm_r5_defconfig
+ export UBOOT_CFG_CORTEXA=j721e_evm_a72_defconfig
+ export TFA_BOARD=generic
+ # we dont use any extra TFA parameters
+ unset TFA_EXTRA_ARGS
+ export OPTEE_PLATFORM=k3-j721e
+ # we dont use any extra OP-TEE parameters
+ unset OPTEE_EXTRA_ARGS
.. j721e_evm_rst_include_start_build_steps
1. Trusted Firmware-A:
-.. include:: k3.rst
+.. include:: ../ti/k3.rst
:start-after: .. k3_rst_include_start_build_steps_tfa
:end-before: .. k3_rst_include_end_build_steps_tfa
2. OP-TEE:
-.. include:: k3.rst
+.. include:: ../ti/k3.rst
:start-after: .. k3_rst_include_start_build_steps_optee
:end-before: .. k3_rst_include_end_build_steps_optee
@@ -99,19 +99,20 @@
* 3.1 R5:
-.. include:: k3.rst
+.. include:: ../ti/k3.rst
:start-after: .. k3_rst_include_start_build_steps_spl_r5
:end-before: .. k3_rst_include_end_build_steps_spl_r5
* 3.2 A72:
-.. include:: k3.rst
+.. include:: ../ti/k3.rst
:start-after: .. k3_rst_include_start_build_steps_uboot
:end-before: .. k3_rst_include_end_build_steps_uboot
.. j721e_evm_rst_include_end_build_steps
Target Images
---------------
+-------------
+
In order to boot we need tiboot3.bin, sysfw.itb, tispl.bin and u-boot.img.
Each SoC variant (GP, HS-FS and HS-SE) requires a different source for these
files.
@@ -202,17 +203,17 @@
and sysfw.itb over tftp and then flash those to OSPI at their respective
addresses.
-.. code-block:: text
+.. prompt:: bash =>
- => sf probe
- => tftp ${loadaddr} tiboot3.bin
- => sf update $loadaddr 0x0 $filesize
- => tftp ${loadaddr} tispl.bin
- => sf update $loadaddr 0x80000 $filesize
- => tftp ${loadaddr} u-boot.img
- => sf update $loadaddr 0x280000 $filesize
- => tftp ${loadaddr} sysfw.itb
- => sf update $loadaddr 0x6C0000 $filesize
+ sf probe
+ tftp ${loadaddr} tiboot3.bin
+ sf update $loadaddr 0x0 $filesize
+ tftp ${loadaddr} tispl.bin
+ sf update $loadaddr 0x80000 $filesize
+ tftp ${loadaddr} u-boot.img
+ sf update $loadaddr 0x280000 $filesize
+ tftp ${loadaddr} sysfw.itb
+ sf update $loadaddr 0x6C0000 $filesize
Flash layout for OSPI:
@@ -248,12 +249,12 @@
environment's distribution needs to be updated, it might be necessary to
build OpenOCD from the source.
-.. include:: k3.rst
+.. include:: ../ti/k3.rst
:start-after: .. k3_rst_include_start_openocd_connect_XDS110
:end-before: .. k3_rst_include_end_openocd_connect_XDS110
To start OpenOCD and connect to the board
-.. code-block:: bash
+.. prompt:: bash $
openocd -f board/ti_j721eevm.cfg
diff --git a/doc/board/ti/j721s2_evm.rst b/doc/board/ti/j721s2_evm.rst
index fec2aca..f5c48c9 100644
--- a/doc/board/ti/j721s2_evm.rst
+++ b/doc/board/ti/j721s2_evm.rst
@@ -6,6 +6,7 @@
Introduction:
-------------
+
The J721S2 family of SoCs are part of K3 Multicore SoC architecture platform
targeting automotive applications. They are designed as a low power, high
performance and highly integrated device architecture, adding significant
@@ -38,6 +39,7 @@
Boot Flow:
----------
+
Below is the pictorial representation of boot flow:
.. image:: img/boot_diagram_k3_current.svg
@@ -60,6 +62,7 @@
Build procedure:
----------------
+
0. Setup the environment variables:
.. include:: k3.rst
@@ -75,15 +78,15 @@
.. include:: k3.rst
:start-after: .. k3_rst_include_start_common_env_vars_defn
:end-before: .. k3_rst_include_end_common_env_vars_defn
-.. code-block:: bash
+.. prompt:: bash $
- $ export UBOOT_CFG_CORTEXR=j721s2_evm_r5_defconfig
- $ export UBOOT_CFG_CORTEXA=j721s2_evm_a72_defconfig
- $ export TFA_BOARD=generic
- $ export TFA_EXTRA_ARGS="K3_USART=0x8"
- $ # The following is not a typo, j784s4 is the OP-TEE platform for j721s2
- $ export OPTEE_PLATFORM=k3-j784s4
- $ export OPTEE_EXTRA_ARGS="CFG_CONSOLE_UART=0x8"
+ export UBOOT_CFG_CORTEXR=j721s2_evm_r5_defconfig
+ export UBOOT_CFG_CORTEXA=j721s2_evm_a72_defconfig
+ export TFA_BOARD=generic
+ export TFA_EXTRA_ARGS="K3_USART=0x8"
+ # The following is not a typo, j784s4 is the OP-TEE platform for j721s2
+ export OPTEE_PLATFORM=k3-j784s4
+ export OPTEE_EXTRA_ARGS="CFG_CONSOLE_UART=0x8"
.. j721s2_evm_rst_include_start_build_steps
@@ -120,7 +123,8 @@
.. j721s2_evm_rst_include_end_build_steps
Target Images
---------------
+-------------
+
In order to boot we need tiboot3.bin, tispl.bin and u-boot.img. Each SoC
variant (GP, HS-FS, HS-SE) requires a different source for these files.
@@ -296,7 +300,7 @@
To start OpenOCD and connect to the board
-.. code-block:: bash
+.. prompt:: bash $
openocd -f board/ti_j721s2evm.cfg
diff --git a/doc/board/ti/k3.rst b/doc/board/ti/k3.rst
index 89d70db..a127215 100644
--- a/doc/board/ti/k3.rst
+++ b/doc/board/ti/k3.rst
@@ -30,12 +30,14 @@
.. toctree::
:maxdepth: 1
- am62x_beagleplay
+ am62ax_sk
am62x_sk
+ ../beagle/am62x_beagleplay
../toradex/verdin-am62
am64x_evm
am65x_evm
j7200_evm
+ ../beagle/j721e_beagleboneai64
j721e_evm
j721s2_evm
@@ -197,7 +199,7 @@
.. k3_rst_include_end_common_env_vars_desc
.. k3_rst_include_start_common_env_vars_defn
-.. prompt:: bash
+.. prompt:: bash $
export CC32=arm-linux-gnueabihf-
export CC64=aarch64-linux-gnu-
@@ -238,7 +240,7 @@
.. k3_rst_include_end_board_env_vars_desc
Building tiboot3.bin
-^^^^^^^^^^^^^^^^^^^^^
+^^^^^^^^^^^^^^^^^^^^
1. To generate the U-Boot SPL for the wakeup domain, use the following
commands, substituting :code:`{SOC}` for the name of your device (eg:
@@ -247,7 +249,7 @@
uses the split binary flow)
.. k3_rst_include_start_build_steps_spl_r5
-.. prompt:: bash
+.. prompt:: bash $
# inside u-boot source
make $UBOOT_CFG_CORTEXR
@@ -273,7 +275,7 @@
UBoot SPL will only look for and load the files with these names.
Building tispl.bin
-^^^^^^^^^^^^^^^^^^^
+^^^^^^^^^^^^^^^^^^
The `tispl.bin` is a standard fitImage combining the firmware need for
the main domain to function properly as well as Device Management (DM)
@@ -283,7 +285,7 @@
application cores on the main domain.
.. k3_rst_include_start_build_steps_tfa
-.. prompt:: bash
+.. prompt:: bash $
# inside trusted-firmware-a source
make CROSS_COMPILE=$CC64 ARCH=aarch64 PLAT=k3 SPD=opteed $TFA_EXTRA_ARGS \
@@ -299,7 +301,7 @@
using the TrustZone technology built into the core.
.. k3_rst_include_start_build_steps_optee
-.. prompt:: bash
+.. prompt:: bash $
# inside optee_os source
make CROSS_COMPILE=$CC32 CROSS_COMPILE64=$CC64 CFG_ARM64_core=y $OPTEE_EXTRA_ARGS \
@@ -311,7 +313,7 @@
64bit core in the main domain.
.. k3_rst_include_start_build_steps_uboot
-.. prompt:: bash
+.. prompt:: bash $
# inside u-boot source
make $UBOOT_CFG_CORTEXA
@@ -410,14 +412,14 @@
be passing to mkimage for signing the fitImage and embedding the key in
the u-boot dtb.
- .. prompt:: bash
+ .. prompt:: bash $
mkimage -r -f fitImage.its -k $UBOOT_PATH/board/ti/keys -K
$UBOOT_PATH/build/a72/dts/dt.dtb
For signing a secondary platform, pass the -K parameter to that DTB
- .. prompt:: bash
+ .. prompt:: bash $
mkimage -f fitImage.its -k $UBOOT_PATH/board/ti/keys -K
$UBOOT_PATH/build/a72/arch/arm/dts/k3-j721e-sk.dtb
@@ -476,8 +478,7 @@
**Writing to MMC/EMMC**
-.. prompt:: bash
- :prompts: =>
+.. prompt:: bash =>
env export -t $loadaddr <list of variables>
fatwrite mmc ${mmcdev} ${loadaddr} ${bootenvfile} ${filesize}
@@ -490,8 +491,7 @@
If manually needs to be done then the environment can be read from the
filesystem and then imported
-.. prompt:: bash
- :prompts: =>
+.. prompt:: bash =>
fatload mmc ${mmcdev} ${loadaddr} ${bootenvfile}
env import -t ${loadaddr} ${filesize}
@@ -551,7 +551,7 @@
box support by OpenOCD. The board-specific documentation will
cover the details and any adapter/dongle recommendations.
-.. prompt:: bash
+.. prompt:: bash $
openocd -v
@@ -569,7 +569,7 @@
other package managers. Please refer to the `OpenOCD Documentation
<https://openocd.org/>`_ for more recent installation steps.
-.. prompt:: bash
+.. prompt:: bash $
# Check the packages to be installed: needs deb-src in sources.list
sudo apt build-dep openocd
@@ -599,7 +599,7 @@
if building from a source, ensure that the udev rules are installed
correctly to ensure a sane system.
-.. prompt:: bash
+.. prompt:: bash $
# Go to the OpenOCD source directory
cd openocd
@@ -617,7 +617,7 @@
Most systems come with gdb-multiarch package.
-.. prompt:: bash
+.. prompt:: bash $
# Install gdb-multiarch package
sudo apt-get install gdb-multiarch
@@ -833,7 +833,7 @@
.. k3_rst_include_start_openocd_cfg_XDS110
-.. prompt:: bash
+.. prompt:: bash $
openocd -f board/{board_of_choice}.cfg
@@ -847,7 +847,7 @@
<https://github.com/openocd-org/openocd/blob/master/tcl/target/ti_k3.cfg#L59>`_
to decide if the SoC is supported or not.
-.. prompt:: bash
+.. prompt:: bash $
openocd -f openocd_connect.cfg
@@ -922,13 +922,13 @@
GDB-based IDE. To start up GDB in the terminal, run the following
command.
-.. prompt:: bash
+.. prompt:: bash $
gdb-multiarch
To connect to your desired core, run the following command within GDB:
-.. code-block:: bash
+.. prompt:: bash (gdb)
target extended-remote localhost:{port for desired core}
@@ -945,13 +945,13 @@
* Prior to relocation:
-.. code-block:: bash
+.. prompt:: bash (gdb)
symbol-file {path to elf file}
* After relocation:
-.. code-block:: bash
+.. prompt:: bash (gdb)
# Drop old symbol file
symbol-file
@@ -962,7 +962,7 @@
In the above example of AM625,
-.. code-block:: bash
+.. prompt:: bash (gdb)
target extended-remote localhost:3338 <- R5F (Wakeup Domain)
target extended-remote localhost:3334 <- A53 (Main Domain)
@@ -982,7 +982,7 @@
needed and run the following GDB commands to step out of the debug
loop set in the ``board_init_f`` function.
-.. code-block:: bash
+.. prompt:: bash (gdb)
set x = 0
continue
diff --git a/doc/board/ti/ks2_evm.rst b/doc/board/ti/ks2_evm.rst
index 0a78903..16c2e57 100644
--- a/doc/board/ti/ks2_evm.rst
+++ b/doc/board/ti/ks2_evm.rst
@@ -17,17 +17,17 @@
The K2HK board is based on Texas Instruments Keystone2 family of SoCs: K2H, K2K.
More details on these SoCs are available at company websites:
-K2K: http://www.ti.com/product/tci6638k2k
-K2H: http://www.ti.com/product/tci6638k2h
+K2K: https://www.ti.com/product/tci6638k2k
+K2H: https://www.ti.com/product/tci6638k2h
The K2E SoC details are available at
- http://www.ti.com/lit/ds/symlink/66ak2e05.pdf
+ https://www.ti.com/lit/ds/symlink/66ak2e05.pdf
The K2L SoC details are available at
- http://www.ti.com/lit/ds/symlink/tci6630k2l.pdf
+ https://www.ti.com/lit/ds/symlink/tci6630k2l.pdf
The K2G SoC details are available at
- http://www.ti.com/lit/ds/symlink/66ak2g02.pdf
+ https://www.ti.com/lit/ds/symlink/66ak2g02.pdf
Board Configuration
-------------------
@@ -122,8 +122,7 @@
To build u-boot.bin, u-boot-spi.gph, MLO:
-.. prompt:: bash
- :prompts: $
+.. prompt:: bash $
make k2hk_evm_defconfig
make
@@ -197,8 +196,7 @@
4. Free Run the target as described earlier (step 4) to get U-Boot prompt
5. At the U-Boot console type following to setup U-Boot environment variables.
-.. prompt:: bash
- :prompts: =>
+.. prompt:: bash =>
setenv addr_uboot 0x87000000
setenv filesize <size in hex of u-boot-spi.gph rounded to hex 0x10000>
@@ -226,8 +224,7 @@
4. Free Run the target as described earlier (step 4) to get U-Boot prompt
5. At the U-Boot console type following to setup U-Boot environment variables.
-.. prompt:: bash
- :prompts: =>
+.. prompt:: bash =>
setenv filesize <size in hex of MLO rounded to hex 0x10000>
run burn_uboot_nand
@@ -249,10 +246,10 @@
1. On the regular UART port start xmodem transfer of the u-boot.bin
2. Using BMC terminal set the ARM-UART bootmode and reboot the EVM
-.. prompt:: bash
+.. prompt:: bash BMC>
- BMC> bootmode #4
- MBC> reboot
+ bootmode #4
+ reboot
3. When xmodem is complete you should see the U-Boot starts on the UART port
diff --git a/doc/board/xilinx/xilinx.rst b/doc/board/xilinx/xilinx.rst
index 8c9afb4..5464625 100644
--- a/doc/board/xilinx/xilinx.rst
+++ b/doc/board/xilinx/xilinx.rst
@@ -2,7 +2,7 @@
.. (C) Copyright 2019 Xilinx, Inc.
U-Boot device tree bindings
-----------------------------
+---------------------------
All the device tree bindings used in U-Boot are specified in Linux
kernel. Please refer dt bindings from below specified paths in Linux
diff --git a/doc/build/gcc.rst b/doc/build/gcc.rst
index 23501de..3c64657 100644
--- a/doc/build/gcc.rst
+++ b/doc/build/gcc.rst
@@ -66,7 +66,7 @@
Depending on the build target further packages may be needed:
* sandbox with lcd: sdl2-dev
-* riscv64 S-mode targests: opensbi
+* riscv64 S-mode targets: opensbi
* some arm64 targets: arm-trusted-firmware
Prerequisites
diff --git a/doc/build/source.rst b/doc/build/source.rst
index 470f793..d21ee05 100644
--- a/doc/build/source.rst
+++ b/doc/build/source.rst
@@ -1,5 +1,5 @@
Obtaining the source
-=====================
+====================
The source of the U-Boot project is maintained in a Git repository.
diff --git a/doc/develop/bootstd.rst b/doc/develop/bootstd.rst
index 51cd573..496e24b 100644
--- a/doc/develop/bootstd.rst
+++ b/doc/develop/bootstd.rst
@@ -247,7 +247,7 @@
Name of the flattened device tree (FDT) file to load, e.g.
"rockchip/rk3399-rockpro64.dtb"
-fdtaddr_addr_r
+fdt_addr_r
Address at which to load the FDT, e.g. 0x01f00000
fdtoverlay_addr_r (needed if overlays are used)
diff --git a/doc/develop/driver-model/ethernet.rst b/doc/develop/driver-model/ethernet.rst
index cdbccca..73c3a72 100644
--- a/doc/develop/driver-model/ethernet.rst
+++ b/doc/develop/driver-model/ethernet.rst
@@ -1,5 +1,5 @@
Ethernet Driver Guide
-=======================
+=====================
The networking stack in Das U-Boot is designed for multiple network devices
to be easily added and controlled at runtime. This guide is meant for people
@@ -14,7 +14,7 @@
the two and hints about porting will be handled at the end.
Driver framework
-------------------
+----------------
A network driver following the driver model must declare itself using
the UCLASS_ETH .id field in the U-Boot driver struct:
@@ -67,7 +67,7 @@
bits for internal PHYs, etc.).
Driver methods
-----------------
+--------------
The real work will be done in the driver method functions the driver provides
by defining the members of struct eth_ops:
@@ -158,7 +158,7 @@
CONFIG_PHYLIB / CONFIG_CMD_MII
---------------------------------
+------------------------------
If your device supports banging arbitrary values on the MII bus (pretty much
every device does), you should add support for the mii command. Doing so is
@@ -193,7 +193,7 @@
................................................................
Legacy network drivers
-------------------------
+----------------------
!!! WARNING !!!
@@ -221,7 +221,7 @@
initialising a network driver is as follows:
Old network driver registration
-~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
+~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
When U-Boot initializes, it will call the common function eth_initialize().
This will in turn call the board-specific board_eth_init() (or if that fails,
diff --git a/doc/develop/driver-model/migration.rst b/doc/develop/driver-model/migration.rst
index fe1ae21..03fea94 100644
--- a/doc/develop/driver-model/migration.rst
+++ b/doc/develop/driver-model/migration.rst
@@ -100,7 +100,7 @@
other base driver model options in time for inclusion in the 2021.10 release.
CFG_SYS_TIMER_RATE and CFG_SYS_TIMER_COUNTER
---------------------------------------------------
+--------------------------------------------
Deadline: 2023.01
These are legacy options which have been replaced by driver model.
diff --git a/doc/develop/driver-model/nvmxip.rst b/doc/develop/driver-model/nvmxip.rst
index e85dc22..4a7650c 100644
--- a/doc/develop/driver-model/nvmxip.rst
+++ b/doc/develop/driver-model/nvmxip.rst
@@ -1,7 +1,7 @@
.. SPDX-License-Identifier: GPL-2.0+
NVM XIP Block Storage Emulation Driver
-=======================================
+======================================
Summary
-------
@@ -54,12 +54,12 @@
The implementation is generic and can be used by different platforms.
Supported hardware
---------------------------------
+------------------
Any plaform supporting readq().
Configuration
-----------------------
+-------------
config NVMXIP
This option allows the emulation of a block storage device
@@ -77,7 +77,7 @@
write their own driver (same as nvmxip_qspi in addition to the custom settings).
Device Tree nodes
---------------------
+-----------------
Multiple QSPI XIP flash devices can be used at the same time by describing them through DT
nodes.
diff --git a/doc/develop/driver-model/remoteproc-framework.rst b/doc/develop/driver-model/remoteproc-framework.rst
index 566495a..03a0bd0 100644
--- a/doc/develop/driver-model/remoteproc-framework.rst
+++ b/doc/develop/driver-model/remoteproc-framework.rst
@@ -1,6 +1,6 @@
.. SPDX-License-Identifier: GPL-2.0+
.. (C) Copyright 2015
-.. Texas Instruments Incorporated - http://www.ti.com/
+.. Texas Instruments Incorporated - https://www.ti.com/
Remote Processor Framework
==========================
diff --git a/doc/develop/driver-model/soc-framework.rst b/doc/develop/driver-model/soc-framework.rst
index 2609fda..357e7fc 100644
--- a/doc/develop/driver-model/soc-framework.rst
+++ b/doc/develop/driver-model/soc-framework.rst
@@ -1,6 +1,6 @@
.. SPDX-License-Identifier: GPL-2.0+
.. (C) Copyright 2020
-.. Texas Instruments Incorporated - http://www.ti.com/
+.. Texas Instruments Incorporated - https://www.ti.com/
SOC ID Framework
================
diff --git a/doc/develop/driver-model/spi-howto.rst b/doc/develop/driver-model/spi-howto.rst
index 97fbf75..9dc3b9b 100644
--- a/doc/develop/driver-model/spi-howto.rst
+++ b/doc/develop/driver-model/spi-howto.rst
@@ -218,7 +218,7 @@
Write of_to_plat() [for device tree only]
--------------------------------------------------
+-----------------------------------------
This method will convert information in the device tree node into a C
structure in your driver (called platform data). If you are not using
diff --git a/doc/develop/falcon.rst b/doc/develop/falcon.rst
index 2f25fc8..8a46c0e 100644
--- a/doc/develop/falcon.rst
+++ b/doc/develop/falcon.rst
@@ -220,7 +220,7 @@
The kernel is loaded directly by the SPL without passing through U-Boot.
Example with FDT: a3m071 board
--------------------------------
+------------------------------
To boot the Linux kernel from the SPL, the DT blob (fdt) needs to get
prepared/patched first. U-Boot usually inserts some dynamic values into
diff --git a/doc/develop/release_cycle.rst b/doc/develop/release_cycle.rst
index 0e75345..37e9fc1 100644
--- a/doc/develop/release_cycle.rst
+++ b/doc/develop/release_cycle.rst
@@ -68,9 +68,9 @@
* U-Boot v2024.01-rc2 was released on Mon 06 November 2023.
-.. * U-Boot v2024.01-rc3 was released on Mon 20 November 2023.
+* U-Boot v2024.01-rc3 was released on Mon 20 November 2023.
-.. * U-Boot v2024.01-rc4 was released on Mon 04 December 2023.
+* U-Boot v2024.01-rc4 was released on Mon 04 December 2023.
.. * U-Boot v2024.01-rc5 was released on Mon 18 December 2023.
diff --git a/doc/develop/uefi/uefi.rst b/doc/develop/uefi/uefi.rst
index fb16ac7..6bc9d92 100644
--- a/doc/develop/uefi/uefi.rst
+++ b/doc/develop/uefi/uefi.rst
@@ -642,6 +642,40 @@
As of U-Boot v2020.10 UEFI variables cannot be set at runtime. The U-Boot
command 'efidebug' can be used to set the variables.
+UEFI HTTP Boot
+~~~~~~~~~~~~~~
+
+HTTP Boot provides the capability for system deployment and configuration
+over the network. HTTP Boot can be activated by specifying::
+
+ CONFIG_EFI_HTTP_BOOT
+
+Enabling that will automatically select::
+
+ CONFIG_CMD_DNS
+ CONFIG_CMD_WGET
+ CONFIG_BLKMAP
+
+Set up the load option specifying the target URI::
+
+ efidebug boot add -u 1 netinst http://foo/bar
+
+When this load option is selected as boot selection, resolve the
+host ip address by dns, then download the file with wget.
+If the downloaded file extension is .iso or .img file, efibootmgr tries to
+mount the image and boot with the default file(e.g. EFI/BOOT/BOOTAA64.EFI).
+If the downloaded file is PE-COFF image, load the downloaded file and
+start it.
+
+The current implementation tries to resolve the IP address as a host name.
+If the uri is like "http://192.168.1.1/foobar",
+the dns process tries to resolve the host "192.168.1.1" and it will
+end up with "host not found".
+
+We need to preset the "httpserverip" environment variable to proceed the wget::
+
+ setenv httpserverip 192.168.1.1
+
Executing the built in hello world application
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
diff --git a/doc/device-tree-bindings/clock/ti,cdce9xx.txt b/doc/device-tree-bindings/clock/ti,cdce9xx.txt
index 0d01f2d..62701d2 100644
--- a/doc/device-tree-bindings/clock/ti,cdce9xx.txt
+++ b/doc/device-tree-bindings/clock/ti,cdce9xx.txt
@@ -4,10 +4,10 @@
This binding uses the common clock binding[1].
[1] Documentation/devicetree/bindings/clock/clock-bindings.txt
-[2] http://www.ti.com/product/cdce913
-[3] http://www.ti.com/product/cdce925
-[4] http://www.ti.com/product/cdce937
-[5] http://www.ti.com/product/cdce949
+[2] https://www.ti.com/product/cdce913
+[3] https://www.ti.com/product/cdce925
+[4] https://www.ti.com/product/cdce937
+[5] https://www.ti.com/product/cdce949
The driver provides clock sources for each output Y1 through Y5.
diff --git a/doc/device-tree-bindings/leds/leds-lp5562.txt b/doc/device-tree-bindings/leds/leds-lp5562.txt
new file mode 100644
index 0000000..4e0c742
--- /dev/null
+++ b/doc/device-tree-bindings/leds/leds-lp5562.txt
@@ -0,0 +1,63 @@
+LEDs connected to TI LP5562 controller
+
+This driver works with a TI LP5562 4-channel LED controller.
+CONFIG_LED_BLINK is supported using the controller engines. However
+there are only 3 engines available for the 4 channels. This means
+that the blue and white channels share the same engine. When both
+blue and white LEDs are set to blink, they will share the same blink
+rate. Changing the blink rate of the blue LED will affect the white
+LED and vice-versa. Manual on/off is handled independently for all 4
+channels.
+
+Required properties:
+ - compatible : should be "ti,lp5562".
+ - #address-cells : must be 1.
+ - #size-cells : must be 0.
+ - reg : LP5562 LED controller I2C address.
+
+Optional properties:
+ - enable-gpios : Enable GPIO
+ - clock-mode : u8, configures the clock mode:
+ - 0 # automode
+ - 1 # internal
+ - 2 # external
+
+Each LED is represented as a sub-node of the ti,lp5562 device.
+
+LED sub-node required properties:
+ - reg : Zero-based channel identifier:
+ - 0 red
+ - 1 green
+ - 2 blue
+ - 3 white
+
+LED sub-node optional properties:
+ - chan-name : name of LED
+ - max-cur : LED current at max brightness in 100uA steps (0x00 - 0xFF)
+ Default : 100 (10 mA)
+
+Example:
+ leds0: lp5562@30 {
+ compatible = "ti,lp5562";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ enable-gpios = <&gpio3 9 GPIO_ACTIVE_HIGH>;
+ reg = <0x30>;
+ clock-mode = /bits/8 <1>;
+
+ led@0 {
+ reg = <0>;
+ chan-name = "red";
+ max-cur = /bits/ 8 <200>; /* 20mA */
+ };
+ led@1 {
+ reg = <1>;
+ chan-name = "green";
+ max-cur = /bits/ 8 <200>; /* 20mA */
+ };
+ led@2 {
+ reg = <2>;
+ chan-name = "blue";
+ max-cur = /bits/ 8 <200>; /* 20mA */
+ };
+ };
diff --git a/doc/device-tree-bindings/misc/esm-k3.txt b/doc/device-tree-bindings/misc/esm-k3.txt
deleted file mode 100644
index 01c8b6b..0000000
--- a/doc/device-tree-bindings/misc/esm-k3.txt
+++ /dev/null
@@ -1,25 +0,0 @@
-Texas Instruments K3 ESM Binding
-======================
-
-ESM (Error Signaling Module) is an IP block on TI K3 devices that allows
-handling of safety events somewhat similar to what interrupt controller
-would do. The safety signals have their separate paths within the SoC,
-and they are handled by the ESM, which routes them to the proper
-destination, which can be system reset, interrupt controller, etc. In
-the simplest configuration the signals are just routed to reset the
-SoC.
-
-Required properties :
-- compatible : "ti,j721e-esm"
-- ti,esm-pins : integer array of esm events IDs to route to external event
- pin which can be used to reset the SoC. The array can
- have arbitrary amount of event IDs listed on it.
-
-Example
-=======
-
- main_esm: esm@700000 {
- compatible = "ti,j721e-esm";
- reg = <0x0 0x700000 0x0 0x1000>;
- ti,esm-pins = <344>, <345>;
- };
diff --git a/doc/device-tree-bindings/misc/ti,j721e-esm.yaml b/doc/device-tree-bindings/misc/ti,j721e-esm.yaml
new file mode 100644
index 0000000..0c9a844
--- /dev/null
+++ b/doc/device-tree-bindings/misc/ti,j721e-esm.yaml
@@ -0,0 +1,53 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+# Copyright (C) 2022 Texas Instruments Incorporated
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/misc/ti,j721e-esm.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Texas Instruments K3 ESM
+
+maintainers:
+ - Neha Malcom Francis <n-francis@ti.com>
+
+description:
+ The ESM (Error Signaling Module) is an IP block on TI K3 devices
+ that allows handling of safety events somewhat similar to what interrupt
+ controller would do. The safety signals have their separate paths within
+ the SoC, and they are handled by the ESM, which routes them to the proper
+ destination, which can be system reset, interrupt controller, etc. In the
+ simplest configuration the signals are just routed to reset the SoC.
+
+properties:
+ compatible:
+ const: ti,j721e-esm
+
+ reg:
+ maxItems: 1
+
+ ti,esm-pins:
+ $ref: /schemas/types.yaml#/definitions/uint32-array
+ description:
+ integer array of ESM interrupt pins to route to external event pin
+ which can be used to reset the SoC.
+ minItems: 1
+ maxItems: 255
+
+required:
+ - compatible
+ - reg
+ - ti,esm-pins
+
+additionalProperties: false
+
+examples:
+ - |
+ bus {
+ #address-cells = <2>;
+ #size-cells = <2>;
+ esm@700000 {
+ compatible = "ti,j721e-esm";
+ reg = <0x0 0x700000 0x0 0x1000>;
+ ti,esm-pins = <344>, <345>;
+ };
+ };
diff --git a/doc/device-tree-bindings/nand/sandbox,nand.txt b/doc/device-tree-bindings/nand/sandbox,nand.txt
new file mode 100644
index 0000000..0a723d7
--- /dev/null
+++ b/doc/device-tree-bindings/nand/sandbox,nand.txt
@@ -0,0 +1,57 @@
+Sandbox NAND
+============
+
+The sandbox NAND controller emulates a NAND controller and attached devices.
+
+Required properties:
+- compatible: "sandbox,nand"
+- #address-cells: Must be 1
+- #size-cells: Must be 0
+
+Any number of child nodes may be present, each representing a NAND device:
+
+Required Properties:
+- reg: The chip-select(s) to use. Only single-die devices are supported for now.
+- sandbox,id: An array of bytes to be reported by the READID (0x90) command
+- sandbox,erasesize: The block size (erase size) of the device, in bytes. Must
+ be a power-of-two multiple of the page size.
+- sandbox,oobsize: The size of the OOB area per page, in bytes.
+- sandbox,pagesize: The page size (write size) of the device, in bytes. Must be
+ a power of two.
+- sandbox,pages: The total number of pages in the device.
+- sandbox,err-count: Number of bit errors to inject per step.
+- sandbox,err-step-size: Size of the step to use when injecting errors, in
+ bytes. Must evenly divide the page size.
+
+Optional properties:
+- sandbox,onfi: The complete ONFI parameter page, including the CRC. Should be
+ exactly 256 bytes.
+- Any common NAND chip properties as documented by Linux's
+ Documentation/devicetree/bindings/mtd/raw-nand-chip.yaml
+
+To match U-Boot's error correction capabilities, errors are only injected into
+the data area and the ECC codes. Other data in the OOB area is never corrupted.
+Generally, sandbox,err-step-size should be the same as the ECC step size, and
+sandbox,err-count should be less than the number of correctable bit errors (the
+ECC strength).
+
+Example
+-------
+
+nand-controller {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ compatible = "sandbox,nand";
+
+ nand@0 {
+ reg = <0>;
+ nand-ecc-mode = "soft";
+ sandbox,id = [00 e3];
+ sandbox,erasesize = <(8 * 1024)>;
+ sandbox,oobsize = <16>;
+ sandbox,pagesize = <512>;
+ sandbox,pages = <0x2000>;
+ sandbox,err-count = <1>;
+ sandbox,err-step-size = <512>;
+ };
+};
diff --git a/doc/device-tree-bindings/video/tilcdc/tilcdc.txt b/doc/device-tree-bindings/video/tilcdc/tilcdc.txt
index 7bf1bb4..7600801 100644
--- a/doc/device-tree-bindings/video/tilcdc/tilcdc.txt
+++ b/doc/device-tree-bindings/video/tilcdc/tilcdc.txt
@@ -46,7 +46,7 @@
crossed and LCD_DATA[0:4] is for Red[3:7] and LCD_DATA[11:15] is
for Blue[3-7]. For more details see section 3.1.1 in AM335x
Silicon Errata:
- http://www.ti.com/general/docs/lit/getliterature.tsp?baseLiteratureNumber=sprz360
+ https://www.ti.com/general/docs/lit/getliterature.tsp?baseLiteratureNumber=sprz360
Example:
diff --git a/doc/sphinx/load_config.py b/doc/sphinx/load_config.py
index eeb394b..8b416bf 100644
--- a/doc/sphinx/load_config.py
+++ b/doc/sphinx/load_config.py
@@ -3,7 +3,7 @@
import os
import sys
-from sphinx.util.pycompat import execfile_
+from sphinx.util.osutil import fs_encoding
# ------------------------------------------------------------------------------
def loadConfig(namespace):
@@ -48,7 +48,9 @@
sys.stdout.write("load additional sphinx-config: %s\n" % config_file)
config = namespace.copy()
config['__file__'] = config_file
- execfile_(config_file, config)
+ with open(config_file, 'rb') as f:
+ code = compile(f.read(), fs_encoding, 'exec')
+ exec(code, config)
del config['__file__']
namespace.update(config)
else:
diff --git a/doc/usage/cmd/askenv.rst b/doc/usage/cmd/askenv.rst
index 347bd59..b85cefa 100644
--- a/doc/usage/cmd/askenv.rst
+++ b/doc/usage/cmd/askenv.rst
@@ -1,7 +1,7 @@
.. SPDX-License-Identifier: GPL-2.0+:
askenv command
-===============
+==============
Synopsis
--------
diff --git a/doc/usage/cmd/bootdev.rst b/doc/usage/cmd/bootdev.rst
index 6c68d0b..fb638b5 100644
--- a/doc/usage/cmd/bootdev.rst
+++ b/doc/usage/cmd/bootdev.rst
@@ -76,7 +76,7 @@
bootdev select
-~~~~~~~~~~~~~~~~~
+~~~~~~~~~~~~~~
Use this to select a particular bootdev. You can select it by the sequence
number or name, as shown in `bootdev list`.
@@ -89,7 +89,7 @@
bootdev info
-~~~~~~~~~~~~~~~
+~~~~~~~~~~~~
This shows information on the current bootdev, with the format looking like
this:
diff --git a/doc/usage/cmd/bootflow.rst b/doc/usage/cmd/bootflow.rst
index 9c5ea9c..2198ff6 100644
--- a/doc/usage/cmd/bootflow.rst
+++ b/doc/usage/cmd/bootflow.rst
@@ -15,6 +15,7 @@
bootflow read
bootflow boot
bootflow cmdline [set|get|clear|delete|auto] <param> [<value>]
+ bootfloe menu [-t]
Description
-----------
@@ -24,6 +25,9 @@
See :doc:`../../develop/bootstd` for more information.
+Note that `CONFIG_BOOTSTD_FULL` (which enables `CONFIG_CMD_BOOTFLOW_FULL) must
+be enabled to obtain full functionality with this command. Otherwise, it only
+supports `bootflow scan` which scans and boots the first available bootflow.
bootflow scan
~~~~~~~~~~~~~
@@ -247,6 +251,16 @@
output appears on the serial port. This is only supported by the 16550 serial
driver so far.
+bootflow menu
+~~~~~~~~~~~~~
+
+This shows a menu with available bootflows. The user can select a particular
+bootflow, which then becomes the current one.
+
+The `-t` flag requests a text menu. Otherwise, if a display is available, a
+graphical menu is shown.
+
+
Example
-------
@@ -658,6 +672,56 @@
77b7e4e0: 320fc000 08e8ba0f c031300f b8d0000f ...2.....01.....
77b7e4f0: 00000020 6ad8000f 00858d10 50000002 ......j.......P
+This shows using a text menu to boot an OS::
+
+ => bootflow scan
+ => bootfl list
+ => bootfl menu -t
+ U-Boot : Boot Menu
+
+ UP and DOWN to choose, ENTER to select
+
+ > 0 mmc1 mmc1.bootdev.whole
+ 1 mmc1 Fedora-Workstation-armhfp-31-1.9 (5.3.7-301.fc31.armv7hl)
+ 2 mmc1 mmc1.bootdev.part_1
+ 3 mmc4 mmc4.bootdev.whole
+ 4 mmc4 Armbian
+ 5 mmc4 mmc4.bootdev.part_1
+ 6 mmc5 mmc5.bootdev.whole
+ 7 mmc5 ChromeOS
+ 8 mmc5 ChromeOS
+ U-Boot : Boot Menu
+
+ UP and DOWN to choose, ENTER to select
+
+ 0 mmc1 mmc1.bootdev.whole
+ > 1 mmc1 Fedora-Workstation-armhfp-31-1.9 (5.3.7-301.fc31.armv7hl)
+ 2 mmc1 mmc1.bootdev.part_1
+ 3 mmc4 mmc4.bootdev.whole
+ 4 mmc4 Armbian
+ 5 mmc4 mmc4.bootdev.part_1
+ 6 mmc5 mmc5.bootdev.whole
+ 7 mmc5 ChromeOS
+ 8 mmc5 ChromeOS
+ U-Boot : Boot Menu
+
+ Selected: Fedora-Workstation-armhfp-31-1.9 (5.3.7-301.fc31.armv7hl)
+ => bootfl boot
+ ** Booting bootflow 'mmc1.bootdev.part_1' with extlinux
+ Ignoring unknown command: ui
+ Ignoring malformed menu command: autoboot
+ Ignoring malformed menu command: hidden
+ Ignoring unknown command: totaltimeout
+ Fedora-Workstation-armhfp-31-1.9 Boot Options.
+ 1: Fedora-Workstation-armhfp-31-1.9 (5.3.7-301.fc31.armv7hl)
+ Enter choice: 1
+ 1: Fedora-Workstation-armhfp-31-1.9 (5.3.7-301.fc31.armv7hl)
+ Retrieving file: /vmlinuz-5.3.7-301.fc31.armv7hl
+ Retrieving file: /initramfs-5.3.7-301.fc31.armv7hl.img
+ append: ro root=UUID=9732b35b-4cd5-458b-9b91-80f7047e0b8a rhgb quiet LANG=en_US.UTF-8 cma=192MB cma=256MB
+ Retrieving file: /dtb-5.3.7-301.fc31.armv7hl/sandbox.dtb
+ ...
+
Return value
------------
@@ -667,6 +731,9 @@
return value $? is 1. If the boot succeeds but for some reason the Operating
System returns, then $? is 0, indicating success.
+For `bootflow menu` the return value is $? is 0 (true) if an option was choses,
+else 1.
+
For other subcommands, the return value $? is always 0 (true).
diff --git a/doc/usage/cmd/cat.rst b/doc/usage/cmd/cat.rst
index 5ef4731..5aaf497 100644
--- a/doc/usage/cmd/cat.rst
+++ b/doc/usage/cmd/cat.rst
@@ -1,7 +1,7 @@
.. SPDX-License-Identifier: GPL-2.0+:
cat command
-===============
+===========
Synopsis
--------
diff --git a/doc/usage/cmd/coninfo.rst b/doc/usage/cmd/coninfo.rst
index f913148..76cb6c3 100644
--- a/doc/usage/cmd/coninfo.rst
+++ b/doc/usage/cmd/coninfo.rst
@@ -21,7 +21,7 @@
list of device names.
Example
---------
+-------
.. code-block:: console
diff --git a/doc/usage/cmd/mmc.rst b/doc/usage/cmd/mmc.rst
index c0924ba..8394f64 100644
--- a/doc/usage/cmd/mmc.rst
+++ b/doc/usage/cmd/mmc.rst
@@ -1,7 +1,7 @@
.. SPDX-License-Identifier: GPL-2.0+:
mmc command
-============
+===========
Synopsis
--------
diff --git a/doc/usage/cmd/part.rst b/doc/usage/cmd/part.rst
index 8a594aa..eee5225 100644
--- a/doc/usage/cmd/part.rst
+++ b/doc/usage/cmd/part.rst
@@ -1,7 +1,7 @@
.. SPDX-License-Identifier: GPL-2.0+:
part command
-===============
+============
Synopis
-------
diff --git a/doc/usage/cmd/qfw.rst b/doc/usage/cmd/qfw.rst
index ec13e09..e734b26 100644
--- a/doc/usage/cmd/qfw.rst
+++ b/doc/usage/cmd/qfw.rst
@@ -15,7 +15,7 @@
Description
-----------
-The *qfw* command is used to retrieve information form the QEMU firmware.
+The *qfw* command is used to retrieve information from the QEMU firmware.
The *qfw list* sub-command displays the QEMU firmware files.
diff --git a/doc/usage/cmd/scmi.rst b/doc/usage/cmd/scmi.rst
new file mode 100644
index 0000000..9ea7e0e
--- /dev/null
+++ b/doc/usage/cmd/scmi.rst
@@ -0,0 +1,126 @@
+.. SPDX-License-Identifier: GPL-2.0+:
+
+scmi command
+============
+
+Synopsis
+--------
+
+::
+
+ scmi info
+ scmi perm_dev <agent id> <device id> <flags>
+ scmi perm_proto <agent id> <device id> <protocol id> <flags>
+ scmi reset <agent id> <flags>
+
+Description
+-----------
+
+Arm System Control and Management Interface (SCMI hereafter) is a set of
+standardised interfaces to manage system resources, like clocks, power
+domains, pin controls, reset and so on, in a system-wide manner.
+
+An entity which provides those services is called a SCMI firmware (or
+SCMI server if you like) may be placed/implemented by EL3 software or
+by a dedicated system control processor (SCP) or else.
+
+A user of SCMI interfaces, including U-Boot, is called a SCMI agent and
+may issues commands, which are defined in each protocol for specific system
+resources, to SCMI server via a communication channel, called a transport.
+Those interfaces are independent from the server's implementation thanks to
+a transport layer.
+
+For more details, see the `SCMI specification`_.
+
+While most of system resources managed under SCMI protocols are implemented
+and handled as standard U-Boot devices, for example clk_scmi, scmi command
+provides additional management functionality against SCMI server.
+
+scmi info
+~~~~~~~~~
+ Show base information about SCMI server and supported protocols
+
+scmi perm_dev
+~~~~~~~~~~~~~
+ Allow or deny access permission to the device
+
+scmi perm_proto
+~~~~~~~~~~~~~~~
+ Allow or deny access to the protocol on the device
+
+scmi reset
+~~~~~~~~~~
+ Reset the already-configured permissions against the device
+
+Parameters are used as follows:
+
+<agent id>
+ SCMI Agent ID, hex value
+
+<device id>
+ SCMI Device ID, hex value
+
+ Please note that what a device means is not defined
+ in the specification.
+
+<protocol id>
+ SCMI Protocol ID, hex value
+
+ It must not be 0x10 (base protocol)
+
+<flags>
+ Flags to control the action, hex value
+
+ 0 to deny, 1 to allow. The other values are reserved and allowed
+ values may depend on the implemented version of SCMI server in
+ the future. See SCMI specification for more details.
+
+Example
+-------
+
+Obtain basic information about SCMI server:
+
+::
+
+ => scmi info
+ SCMI device: scmi
+ protocol version: 0x20000
+ # of agents: 3
+ 0: platform
+ > 1: OSPM
+ 2: PSCI
+ # of protocols: 4
+ Power domain management
+ Performance domain management
+ Clock management
+ Sensor management
+ vendor: Linaro
+ sub vendor: PMWG
+ impl version: 0x20b0000
+
+Ask for access permission to device#0:
+
+::
+
+ => scmi perm_dev 1 0 1
+
+Reset configurations with all access permission settings retained:
+
+::
+
+ => scmi reset 1 0
+
+Configuration
+-------------
+
+The scmi command is only available if CONFIG_CMD_SCMI=y.
+Default n because this command is mainly for debug purpose.
+
+Return value
+------------
+
+The return value ($?) is set to 0 if the operation succeeded,
+1 if the operation failed or -1 if the operation failed due to
+a syntax error.
+
+.. _`SCMI specification`: https://developer.arm.com/documentation/den0056/e/?lang=en
diff --git a/doc/usage/cmd/wdt.rst b/doc/usage/cmd/wdt.rst
index 8d80433..8bb8b36 100644
--- a/doc/usage/cmd/wdt.rst
+++ b/doc/usage/cmd/wdt.rst
@@ -1,7 +1,7 @@
.. SPDX-License-Identifier: GPL-2.0+:
wdt command
-============
+===========
Synopsis
--------
diff --git a/doc/usage/cmd/xxd.rst b/doc/usage/cmd/xxd.rst
index 0de1223..13bb438 100644
--- a/doc/usage/cmd/xxd.rst
+++ b/doc/usage/cmd/xxd.rst
@@ -1,7 +1,7 @@
.. SPDX-License-Identifier: GPL-2.0+:
xxd command
-===============
+===========
Synopsis
--------
diff --git a/doc/usage/fit/beaglebone_vboot.rst b/doc/usage/fit/beaglebone_vboot.rst
index 0580ee1..a102be1 100644
--- a/doc/usage/fit/beaglebone_vboot.rst
+++ b/doc/usage/fit/beaglebone_vboot.rst
@@ -86,7 +86,7 @@
Step 2: Build Linux
---------------------
+-------------------
a. Find the kernel image ('Image') and device tree (.dtb) file you plan to
use. In our case it is am335x-boneblack.dtb and it is built with the kernel.
diff --git a/doc/usage/index.rst b/doc/usage/index.rst
index d8e23fc..1a626c0 100644
--- a/doc/usage/index.rst
+++ b/doc/usage/index.rst
@@ -94,6 +94,7 @@
cmd/rng
cmd/saves
cmd/sbi
+ cmd/scmi
cmd/scp03
cmd/seama
cmd/setexpr
diff --git a/doc/usage/measured_boot.rst b/doc/usage/measured_boot.rst
index 0aad590..9691904 100644
--- a/doc/usage/measured_boot.rst
+++ b/doc/usage/measured_boot.rst
@@ -1,7 +1,7 @@
.. SPDX-License-Identifier: GPL-2.0+
Measured Boot
-=====================
+=============
U-Boot can perform a measured boot, the process of hashing various components
of the boot process, extending the results in the TPM and logging the
@@ -16,7 +16,7 @@
against the hash results of previous boots.
Requirements
----------------------
+------------
* A hardware TPM 2.0 supported by the U-Boot drivers
* CONFIG_TPM=y
diff --git a/drivers/ata/sata.c b/drivers/ata/sata.c
index be1ee01..784d9bbe 100644
--- a/drivers/ata/sata.c
+++ b/drivers/ata/sata.c
@@ -61,7 +61,7 @@
ret = uclass_find_first_device(UCLASS_AHCI, &dev);
if (ret || !dev) {
printf("Cannot find SATA device (err=%d)\n", ret);
- return -ENOSYS;
+ return -ENOENT;
}
ret = device_remove(dev, DM_REMOVE_NORMAL);
diff --git a/drivers/block/Kconfig b/drivers/block/Kconfig
index b897cf1..6ad1888 100644
--- a/drivers/block/Kconfig
+++ b/drivers/block/Kconfig
@@ -13,7 +13,7 @@
config SPL_LEGACY_BLOCK
bool # "Enable Legacy Block Device"
- depends on SPL && !DM_SPL
+ depends on SPL
default y if SPL_MMC || SPL_USB_STORAGE || SCSI || NVME || IDE
default y if SPL_AHCI_PCI
help
diff --git a/drivers/block/Makefile b/drivers/block/Makefile
index fdcba5c..fe6a1fc 100644
--- a/drivers/block/Makefile
+++ b/drivers/block/Makefile
@@ -15,7 +15,8 @@
endif
obj-$(CONFIG_SANDBOX) += sandbox.o host-uclass.o host_dev.o
obj-$(CONFIG_$(SPL_TPL_)BLOCK_CACHE) += blkcache.o
-obj-$(CONFIG_BLKMAP) += blkmap.o
+obj-$(CONFIG_$(SPL_TPL_)BLKMAP) += blkmap.o
+obj-$(CONFIG_$(SPL_TPL_)BLKMAP) += blkmap_helper.o
obj-$(CONFIG_EFI_MEDIA) += efi-media-uclass.o
obj-$(CONFIG_EFI_MEDIA_SANDBOX) += sb_efi_media.o
diff --git a/drivers/block/blkmap.c b/drivers/block/blkmap.c
index 149a4ca..2120140 100644
--- a/drivers/block/blkmap.c
+++ b/drivers/block/blkmap.c
@@ -66,21 +66,6 @@
void (*destroy)(struct blkmap *bm, struct blkmap_slice *bms);
};
-/**
- * struct blkmap - Block map
- *
- * Data associated with a blkmap.
- *
- * @label: Human readable name of this blkmap
- * @blk: Underlying block device
- * @slices: List of slices associated with this blkmap
- */
-struct blkmap {
- char *label;
- struct udevice *blk;
- struct list_head slices;
-};
-
static bool blkmap_slice_contains(struct blkmap_slice *bms, lbaint_t blknr)
{
return (blknr >= bms->blknr) && (blknr < (bms->blknr + bms->blkcnt));
diff --git a/drivers/block/blkmap_helper.c b/drivers/block/blkmap_helper.c
new file mode 100644
index 0000000..bfba141
--- /dev/null
+++ b/drivers/block/blkmap_helper.c
@@ -0,0 +1,53 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * blkmap helper function
+ *
+ * Copyright (c) 2023, Linaro Limited
+ */
+
+#include <blk.h>
+#include <blkmap.h>
+#include <dm/device.h>
+#include <dm/device-internal.h>
+
+int blkmap_create_ramdisk(const char *label, ulong image_addr, ulong image_size,
+ struct udevice **devp)
+{
+ int ret;
+ lbaint_t blknum;
+ struct blkmap *bm;
+ struct blk_desc *desc;
+ struct udevice *bm_dev;
+
+ ret = blkmap_create(label, &bm_dev);
+ if (ret) {
+ log_err("failed to create blkmap\n");
+ return ret;
+ }
+
+ bm = dev_get_plat(bm_dev);
+ desc = dev_get_uclass_plat(bm->blk);
+ blknum = image_size >> desc->log2blksz;
+ ret = blkmap_map_pmem(bm_dev, 0, blknum, image_addr);
+ if (ret) {
+ log_err("Unable to map %#llx at block %d : %d\n",
+ (unsigned long long)image_addr, 0, ret);
+ goto err;
+ }
+ log_info("Block %d+0x" LBAF " mapped to %#llx\n", 0, blknum,
+ (unsigned long long)image_addr);
+
+ ret = device_probe(bm->blk);
+ if (ret)
+ goto err;
+
+ if (devp)
+ *devp = bm_dev;
+
+ return 0;
+
+err:
+ blkmap_destroy(bm_dev);
+
+ return ret;
+}
diff --git a/drivers/clk/Makefile b/drivers/clk/Makefile
index 26bf429..af27ceb 100644
--- a/drivers/clk/Makefile
+++ b/drivers/clk/Makefile
@@ -27,7 +27,6 @@
obj-$(CONFIG_ARCH_SOCFPGA) += altera/
obj-$(CONFIG_ARCH_STM32) += stm32/
obj-$(CONFIG_ARCH_STM32MP) += stm32/
-obj-$(CONFIG_ARCH_SUNXI) += sunxi/
obj-$(CONFIG_CLK_AT91) += at91/
obj-$(CONFIG_CLK_BCM6345) += clk_bcm6345.o
obj-$(CONFIG_CLK_BOSTON) += clk_boston.o
@@ -43,6 +42,7 @@
obj-$(CONFIG_CLK_RENESAS) += renesas/
obj-$(CONFIG_$(SPL_TPL_)CLK_SCMI) += clk_scmi.o
obj-$(CONFIG_CLK_SIFIVE) += sifive/
+obj-$(CONFIG_CLK_SUNXI) += sunxi/
obj-$(CONFIG_CLK_UNIPHIER) += uniphier/
obj-$(CONFIG_CLK_VERSACLOCK) += clk_versaclock.o
obj-$(CONFIG_CLK_VERSAL) += clk_versal.o
diff --git a/drivers/clk/at91/clk-main.c b/drivers/clk/at91/clk-main.c
index b52d926..025c7a7 100644
--- a/drivers/clk/at91/clk-main.c
+++ b/drivers/clk/at91/clk-main.c
@@ -17,6 +17,7 @@
#include <linux/clk/at91_pmc.h>
#include <linux/delay.h>
#include <linux/io.h>
+#include <linux/time.h>
#include "pmc.h"
#define UBOOT_DM_CLK_AT91_MAIN_RC "at91-main-rc-clk"
@@ -25,7 +26,6 @@
#define UBOOT_DM_CLK_AT91_SAM9X5_MAIN "at91-sam9x5-main-clk"
#define MOR_KEY_MASK GENMASK(23, 16)
-#define USEC_PER_SEC 1000000UL
#define SLOW_CLOCK_FREQ 32768
#define clk_main_parent_select(s) (((s) & \
diff --git a/drivers/clk/clk-cdce9xx.c b/drivers/clk/clk-cdce9xx.c
index f23465d..b8700f5 100644
--- a/drivers/clk/clk-cdce9xx.c
+++ b/drivers/clk/clk-cdce9xx.c
@@ -2,7 +2,7 @@
/*
* Texas Instruments CDCE913/925/937/949 clock synthesizer driver
*
- * Copyright (C) 2019 Texas Instruments Incorporated - http://www.ti.com/
+ * Copyright (C) 2019 Texas Instruments Incorporated - https://www.ti.com/
* Tero Kristo <t-kristo@ti.com>
*
* Based on Linux kernel clk-cdce925.c.
diff --git a/drivers/clk/exynos/clk-pll.h b/drivers/clk/exynos/clk-pll.h
index c79aac4..7b7af5e 100644
--- a/drivers/clk/exynos/clk-pll.h
+++ b/drivers/clk/exynos/clk-pll.h
@@ -5,4 +5,9 @@
* Thomas Abraham <thomas.ab@samsung.com>
*/
+#ifndef __EXYNOS_CLK_PLL_H
+#define __EXYNOS_CLK_PLL_H
+
unsigned long pll145x_get_rate(unsigned int *con1, unsigned long fin_freq);
+
+#endif /* __EXYNOS_CLK_PLL_H */
diff --git a/drivers/clk/ti/clk-k3-pll.c b/drivers/clk/ti/clk-k3-pll.c
index c1158c1..8323e6e 100644
--- a/drivers/clk/ti/clk-k3-pll.c
+++ b/drivers/clk/ti/clk-k3-pll.c
@@ -2,7 +2,7 @@
/*
* Texas Instruments K3 SoC PLL clock driver
*
- * Copyright (C) 2020-2021 Texas Instruments Incorporated - http://www.ti.com/
+ * Copyright (C) 2020-2021 Texas Instruments Incorporated - https://www.ti.com/
* Tero Kristo <t-kristo@ti.com>
*/
diff --git a/drivers/clk/ti/clk-k3.c b/drivers/clk/ti/clk-k3.c
index 10f7240..eb76195 100644
--- a/drivers/clk/ti/clk-k3.c
+++ b/drivers/clk/ti/clk-k3.c
@@ -2,7 +2,7 @@
/*
* Texas Instruments K3 clock driver
*
- * Copyright (C) 2020-2021 Texas Instruments Incorporated - http://www.ti.com/
+ * Copyright (C) 2020-2021 Texas Instruments Incorporated - https://www.ti.com/
* Tero Kristo <t-kristo@ti.com>
*/
diff --git a/drivers/clk/ti/clk-sci.c b/drivers/clk/ti/clk-sci.c
index 8fc3254..9e5760d 100644
--- a/drivers/clk/ti/clk-sci.c
+++ b/drivers/clk/ti/clk-sci.c
@@ -2,7 +2,7 @@
/*
* Texas Instruments System Control Interface (TI SCI) clock driver
*
- * Copyright (C) 2018 Texas Instruments Incorporated - http://www.ti.com/
+ * Copyright (C) 2018 Texas Instruments Incorporated - https://www.ti.com/
* Andreas Dannenberg <dannenberg@ti.com>
*
* Loosely based on Linux kernel sci-clk.c...
diff --git a/drivers/core/Kconfig b/drivers/core/Kconfig
index fe5c41d..1081d61 100644
--- a/drivers/core/Kconfig
+++ b/drivers/core/Kconfig
@@ -48,7 +48,6 @@
config DM_WARN
bool "Enable warnings in driver model"
depends on DM
- default y
help
Enable this to see warnings related to driver model.
@@ -88,7 +87,7 @@
config SPL_DM_STATS
bool "Collect and show driver model stats in SPL"
- depends on DM_SPL
+ depends on SPL_DM
help
Enable this to collect and display memory statistics about driver
model. This can help to figure out where all the memory is going and
diff --git a/drivers/core/ofnode.c b/drivers/core/ofnode.c
index 29a4294..f72ea41 100644
--- a/drivers/core/ofnode.c
+++ b/drivers/core/ofnode.c
@@ -991,6 +991,24 @@
return ofnode_path(prop);
}
+int ofnode_read_baud(void)
+{
+ const char *str, *p;
+ u32 baud;
+
+ str = ofnode_read_chosen_string("stdout-path");
+ if (!str)
+ return -EINVAL;
+
+ /* Parse string serial0:115200n8 */
+ p = strchr(str, ':');
+ if (!p)
+ return -EINVAL;
+
+ baud = dectoul(p + 1, NULL);
+ return baud;
+}
+
const void *ofnode_read_aliases_prop(const char *propname, int *sizep)
{
ofnode node;
diff --git a/drivers/dfu/Kconfig b/drivers/dfu/Kconfig
index 8771678..0360d9d 100644
--- a/drivers/dfu/Kconfig
+++ b/drivers/dfu/Kconfig
@@ -112,5 +112,14 @@
the buffer once we've been given the whole file. Define
this to the maximum filesize (in bytes) for the buffer.
If undefined it defaults to the CONFIG_SYS_DFU_DATA_BUF_SIZE.
+
+config DFU_NAME_MAX_SIZE
+ int "Size of the name to be added in dfu entity"
+ default 32
+ depends on DFU
+ help
+ This value is used to maximum size. If name is longer than default size,
+ we need to change the proper maximum size.
+
endif
endmenu
diff --git a/drivers/dma/ti/Makefile b/drivers/dma/ti/Makefile
index 6807eb8..f4e0271 100644
--- a/drivers/dma/ti/Makefile
+++ b/drivers/dma/ti/Makefile
@@ -8,3 +8,4 @@
k3-psil-data-$(CONFIG_SOC_K3_J721S2) += k3-psil-j721s2.o
k3-psil-data-$(CONFIG_SOC_K3_AM642) += k3-psil-am64.o
k3-psil-data-$(CONFIG_SOC_K3_AM625) += k3-psil-am62.o
+k3-psil-data-$(CONFIG_SOC_K3_AM62A7) += k3-psil-am62a.o
diff --git a/drivers/dma/ti/k3-psil-am62a.c b/drivers/dma/ti/k3-psil-am62a.c
new file mode 100644
index 0000000..ca9d71f
--- /dev/null
+++ b/drivers/dma/ti/k3-psil-am62a.c
@@ -0,0 +1,196 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (C) 2022 Texas Instruments Incorporated - https://www.ti.com
+ */
+
+#include <linux/kernel.h>
+
+#include "k3-psil-priv.h"
+
+#define PSIL_PDMA_XY_TR(x) \
+ { \
+ .thread_id = x, \
+ .ep_config = { \
+ .ep_type = PSIL_EP_PDMA_XY, \
+ .mapped_channel_id = -1, \
+ .default_flow_id = -1, \
+ }, \
+ }
+
+#define PSIL_PDMA_XY_PKT(x) \
+ { \
+ .thread_id = x, \
+ .ep_config = { \
+ .ep_type = PSIL_EP_PDMA_XY, \
+ .mapped_channel_id = -1, \
+ .default_flow_id = -1, \
+ .pkt_mode = 1, \
+ }, \
+ }
+
+#define PSIL_ETHERNET(x, ch, flow_base, flow_cnt) \
+ { \
+ .thread_id = x, \
+ .ep_config = { \
+ .ep_type = PSIL_EP_NATIVE, \
+ .pkt_mode = 1, \
+ .needs_epib = 1, \
+ .psd_size = 16, \
+ .mapped_channel_id = ch, \
+ .flow_start = flow_base, \
+ .flow_num = flow_cnt, \
+ .default_flow_id = flow_base, \
+ }, \
+ }
+
+#define PSIL_SAUL(x, ch, flow_base, flow_cnt, default_flow, tx) \
+ { \
+ .thread_id = x, \
+ .ep_config = { \
+ .ep_type = PSIL_EP_NATIVE, \
+ .pkt_mode = 1, \
+ .needs_epib = 1, \
+ .psd_size = 64, \
+ .mapped_channel_id = ch, \
+ .flow_start = flow_base, \
+ .flow_num = flow_cnt, \
+ .default_flow_id = default_flow, \
+ .notdpkt = tx, \
+ }, \
+ }
+
+#define PSIL_PDMA_MCASP(x) \
+ { \
+ .thread_id = x, \
+ .ep_config = { \
+ .ep_type = PSIL_EP_PDMA_XY, \
+ .pdma_acc32 = 1, \
+ .pdma_burst = 1, \
+ }, \
+ }
+
+#define PSIL_CSI2RX(x) \
+ { \
+ .thread_id = x, \
+ .ep_config = { \
+ .ep_type = PSIL_EP_NATIVE, \
+ }, \
+ }
+
+/* PSI-L source thread IDs, used for RX (DMA_DEV_TO_MEM) */
+static struct psil_ep am62a_src_ep_map[] = {
+ /* SAUL */
+ PSIL_SAUL(0x7504, 20, 35, 8, 35, 0),
+ PSIL_SAUL(0x7505, 21, 35, 8, 36, 0),
+ PSIL_SAUL(0x7506, 22, 43, 8, 43, 0),
+ PSIL_SAUL(0x7507, 23, 43, 8, 44, 0),
+ /* PDMA_MAIN0 - SPI0-3 */
+ PSIL_PDMA_XY_PKT(0x4302),
+ PSIL_PDMA_XY_PKT(0x4303),
+ PSIL_PDMA_XY_PKT(0x4304),
+ PSIL_PDMA_XY_PKT(0x4305),
+ PSIL_PDMA_XY_PKT(0x4306),
+ PSIL_PDMA_XY_PKT(0x4307),
+ PSIL_PDMA_XY_PKT(0x4308),
+ PSIL_PDMA_XY_PKT(0x4309),
+ PSIL_PDMA_XY_PKT(0x430a),
+ PSIL_PDMA_XY_PKT(0x430b),
+ PSIL_PDMA_XY_PKT(0x430c),
+ PSIL_PDMA_XY_PKT(0x430d),
+ /* PDMA_MAIN1 - UART0-6 */
+ PSIL_PDMA_XY_PKT(0x4400),
+ PSIL_PDMA_XY_PKT(0x4401),
+ PSIL_PDMA_XY_PKT(0x4402),
+ PSIL_PDMA_XY_PKT(0x4403),
+ PSIL_PDMA_XY_PKT(0x4404),
+ PSIL_PDMA_XY_PKT(0x4405),
+ PSIL_PDMA_XY_PKT(0x4406),
+ /* PDMA_MAIN2 - MCASP0-2 */
+ PSIL_PDMA_MCASP(0x4500),
+ PSIL_PDMA_MCASP(0x4501),
+ PSIL_PDMA_MCASP(0x4502),
+ /* CPSW3G */
+ PSIL_ETHERNET(0x4600, 19, 19, 16),
+ /* CSI2RX */
+ PSIL_CSI2RX(0x5000),
+ PSIL_CSI2RX(0x5001),
+ PSIL_CSI2RX(0x5002),
+ PSIL_CSI2RX(0x5003),
+ PSIL_CSI2RX(0x5004),
+ PSIL_CSI2RX(0x5005),
+ PSIL_CSI2RX(0x5006),
+ PSIL_CSI2RX(0x5007),
+ PSIL_CSI2RX(0x5008),
+ PSIL_CSI2RX(0x5009),
+ PSIL_CSI2RX(0x500a),
+ PSIL_CSI2RX(0x500b),
+ PSIL_CSI2RX(0x500c),
+ PSIL_CSI2RX(0x500d),
+ PSIL_CSI2RX(0x500e),
+ PSIL_CSI2RX(0x500f),
+ PSIL_CSI2RX(0x5010),
+ PSIL_CSI2RX(0x5011),
+ PSIL_CSI2RX(0x5012),
+ PSIL_CSI2RX(0x5013),
+ PSIL_CSI2RX(0x5014),
+ PSIL_CSI2RX(0x5015),
+ PSIL_CSI2RX(0x5016),
+ PSIL_CSI2RX(0x5017),
+ PSIL_CSI2RX(0x5018),
+ PSIL_CSI2RX(0x5019),
+ PSIL_CSI2RX(0x501a),
+ PSIL_CSI2RX(0x501b),
+ PSIL_CSI2RX(0x501c),
+ PSIL_CSI2RX(0x501d),
+ PSIL_CSI2RX(0x501e),
+ PSIL_CSI2RX(0x501f),
+};
+
+/* PSI-L destination thread IDs, used for TX (DMA_MEM_TO_DEV) */
+static struct psil_ep am62a_dst_ep_map[] = {
+ /* SAUL */
+ PSIL_SAUL(0xf500, 27, 83, 8, 83, 1),
+ PSIL_SAUL(0xf501, 28, 91, 8, 91, 1),
+ /* PDMA_MAIN0 - SPI0-3 */
+ PSIL_PDMA_XY_PKT(0xc302),
+ PSIL_PDMA_XY_PKT(0xc303),
+ PSIL_PDMA_XY_PKT(0xc304),
+ PSIL_PDMA_XY_PKT(0xc305),
+ PSIL_PDMA_XY_PKT(0xc306),
+ PSIL_PDMA_XY_PKT(0xc307),
+ PSIL_PDMA_XY_PKT(0xc308),
+ PSIL_PDMA_XY_PKT(0xc309),
+ PSIL_PDMA_XY_PKT(0xc30a),
+ PSIL_PDMA_XY_PKT(0xc30b),
+ PSIL_PDMA_XY_PKT(0xc30c),
+ PSIL_PDMA_XY_PKT(0xc30d),
+ /* PDMA_MAIN1 - UART0-6 */
+ PSIL_PDMA_XY_PKT(0xc400),
+ PSIL_PDMA_XY_PKT(0xc401),
+ PSIL_PDMA_XY_PKT(0xc402),
+ PSIL_PDMA_XY_PKT(0xc403),
+ PSIL_PDMA_XY_PKT(0xc404),
+ PSIL_PDMA_XY_PKT(0xc405),
+ PSIL_PDMA_XY_PKT(0xc406),
+ /* PDMA_MAIN2 - MCASP0-2 */
+ PSIL_PDMA_MCASP(0xc500),
+ PSIL_PDMA_MCASP(0xc501),
+ PSIL_PDMA_MCASP(0xc502),
+ /* CPSW3G */
+ PSIL_ETHERNET(0xc600, 19, 19, 8),
+ PSIL_ETHERNET(0xc601, 20, 27, 8),
+ PSIL_ETHERNET(0xc602, 21, 35, 8),
+ PSIL_ETHERNET(0xc603, 22, 43, 8),
+ PSIL_ETHERNET(0xc604, 23, 51, 8),
+ PSIL_ETHERNET(0xc605, 24, 59, 8),
+ PSIL_ETHERNET(0xc606, 25, 67, 8),
+ PSIL_ETHERNET(0xc607, 26, 75, 8),
+};
+
+struct psil_ep_map am62a_ep_map = {
+ .name = "am62a",
+ .src = am62a_src_ep_map,
+ .src_count = ARRAY_SIZE(am62a_src_ep_map),
+ .dst = am62a_dst_ep_map,
+ .dst_count = ARRAY_SIZE(am62a_dst_ep_map),
+};
diff --git a/drivers/dma/ti/k3-psil-am64.c b/drivers/dma/ti/k3-psil-am64.c
index 15742c3..6180e2a 100644
--- a/drivers/dma/ti/k3-psil-am64.c
+++ b/drivers/dma/ti/k3-psil-am64.c
@@ -1,6 +1,6 @@
// SPDX-License-Identifier: GPL-2.0
/*
- * Copyright (C) 2020 Texas Instruments Incorporated - http://www.ti.com
+ * Copyright (C) 2020 Texas Instruments Incorporated - https://www.ti.com
* Author: Peter Ujfalusi <peter.ujfalusi@ti.com>
*/
diff --git a/drivers/dma/ti/k3-psil-am654.c b/drivers/dma/ti/k3-psil-am654.c
index d16c075..ce86600 100644
--- a/drivers/dma/ti/k3-psil-am654.c
+++ b/drivers/dma/ti/k3-psil-am654.c
@@ -1,6 +1,6 @@
// SPDX-License-Identifier: GPL-2.0
/*
- * Copyright (C) 2019 Texas Instruments Incorporated - http://www.ti.com
+ * Copyright (C) 2019 Texas Instruments Incorporated - https://www.ti.com
* Author: Peter Ujfalusi <peter.ujfalusi@ti.com>
*/
diff --git a/drivers/dma/ti/k3-psil-priv.h b/drivers/dma/ti/k3-psil-priv.h
index 28078c6..83f873b 100644
--- a/drivers/dma/ti/k3-psil-priv.h
+++ b/drivers/dma/ti/k3-psil-priv.h
@@ -1,6 +1,6 @@
/* SPDX-License-Identifier: GPL-2.0 */
/*
- * Copyright (C) 2019 Texas Instruments Incorporated - http://www.ti.com
+ * Copyright (C) 2019 Texas Instruments Incorporated - https://www.ti.com
*/
#ifndef K3_PSIL_PRIV_H_
@@ -42,5 +42,6 @@
extern struct psil_ep_map j721s2_ep_map;
extern struct psil_ep_map am64_ep_map;
extern struct psil_ep_map am62_ep_map;
+extern struct psil_ep_map am62a_ep_map;
#endif /* K3_PSIL_PRIV_H_ */
diff --git a/drivers/dma/ti/k3-psil.c b/drivers/dma/ti/k3-psil.c
index f23c8ca..d4d4fed 100644
--- a/drivers/dma/ti/k3-psil.c
+++ b/drivers/dma/ti/k3-psil.c
@@ -1,6 +1,6 @@
// SPDX-License-Identifier: GPL-2.0
/*
- * Copyright (C) 2019 Texas Instruments Incorporated - http://www.ti.com
+ * Copyright (C) 2019 Texas Instruments Incorporated - https://www.ti.com
* Author: Peter Ujfalusi <peter.ujfalusi@ti.com>
*/
@@ -26,6 +26,8 @@
soc_ep_map = &am64_ep_map;
else if (IS_ENABLED(CONFIG_SOC_K3_AM625))
soc_ep_map = &am62_ep_map;
+ else if (IS_ENABLED(CONFIG_SOC_K3_AM62A7))
+ soc_ep_map = &am62a_ep_map;
}
if (thread_id & K3_PSIL_DST_THREAD_ID_OFFSET && soc_ep_map->dst) {
diff --git a/drivers/dma/ti/k3-psil.h b/drivers/dma/ti/k3-psil.h
index 1e0fe06..af60a99 100644
--- a/drivers/dma/ti/k3-psil.h
+++ b/drivers/dma/ti/k3-psil.h
@@ -1,6 +1,6 @@
/* SPDX-License-Identifier: GPL-2.0 */
/*
- * Copyright (C) 2019 Texas Instruments Incorporated - http://www.ti.com
+ * Copyright (C) 2019 Texas Instruments Incorporated - https://www.ti.com
*/
#ifndef K3_PSIL_H_
diff --git a/drivers/dma/ti/k3-udma-hwdef.h b/drivers/dma/ti/k3-udma-hwdef.h
index 5d50bbc..3d6b4d1 100644
--- a/drivers/dma/ti/k3-udma-hwdef.h
+++ b/drivers/dma/ti/k3-udma-hwdef.h
@@ -1,6 +1,6 @@
/* SPDX-License-Identifier: GPL-2.0+ */
/*
- * Copyright (C) 2018 Texas Instruments Incorporated - http://www.ti.com
+ * Copyright (C) 2018 Texas Instruments Incorporated - https://www.ti.com
*
*
* This program is free software; you can redistribute it and/or modify
diff --git a/drivers/dma/ti/k3-udma.c b/drivers/dma/ti/k3-udma.c
index 9273c70..8a62d63 100644
--- a/drivers/dma/ti/k3-udma.c
+++ b/drivers/dma/ti/k3-udma.c
@@ -1,6 +1,6 @@
// SPDX-License-Identifier: GPL-2.0+
/*
- * Copyright (C) 2018 Texas Instruments Incorporated - http://www.ti.com
+ * Copyright (C) 2018 Texas Instruments Incorporated - https://www.ti.com
* Author: Peter Ujfalusi <peter.ujfalusi@ti.com>
*/
#define pr_fmt(fmt) "udma: " fmt
diff --git a/drivers/fastboot/fb_common.c b/drivers/fastboot/fb_common.c
index 4e9d9b7..3576b06 100644
--- a/drivers/fastboot/fb_common.c
+++ b/drivers/fastboot/fb_common.c
@@ -91,6 +91,7 @@
*/
int __weak fastboot_set_reboot_flag(enum fastboot_reboot_reason reason)
{
+ int ret;
static const char * const boot_cmds[] = {
[FASTBOOT_REBOOT_REASON_BOOTLOADER] = "bootonce-bootloader",
[FASTBOOT_REBOOT_REASON_FASTBOOTD] = "boot-fastboot",
@@ -105,7 +106,18 @@
if (reason >= FASTBOOT_REBOOT_REASONS_COUNT)
return -EINVAL;
- return bcb_write_reboot_reason(mmc_dev, "misc", boot_cmds[reason]);
+ ret = bcb_find_partition_and_load("mmc", mmc_dev, "misc");
+ if (ret)
+ goto out;
+
+ ret = bcb_set(BCB_FIELD_COMMAND, boot_cmds[reason]);
+ if (ret)
+ goto out;
+
+ ret = bcb_store();
+out:
+ bcb_reset();
+ return ret;
}
/**
diff --git a/drivers/firmware/firmware-zynqmp.c b/drivers/firmware/firmware-zynqmp.c
index 43fb7fa..8ea15c7 100644
--- a/drivers/firmware/firmware-zynqmp.c
+++ b/drivers/firmware/firmware-zynqmp.c
@@ -203,6 +203,8 @@
/* Check feature check API version */
ret = xilinx_pm_request(PM_FEATURE_CHECK, api_id, 0, 0, 0,
ret_payload);
+ if (ret)
+ return ret;
/* Return feature check version */
return ret_payload[1] & FIRMWARE_VERSION_MASK;
diff --git a/drivers/firmware/scmi/sandbox-scmi_agent.c b/drivers/firmware/scmi/sandbox-scmi_agent.c
index 9f5f497..cc9011c 100644
--- a/drivers/firmware/scmi/sandbox-scmi_agent.c
+++ b/drivers/firmware/scmi/sandbox-scmi_agent.c
@@ -66,10 +66,10 @@
};
static u8 protocols[] = {
- SCMI_PROTOCOL_ID_POWER_DOMAIN,
- SCMI_PROTOCOL_ID_CLOCK,
- SCMI_PROTOCOL_ID_RESET_DOMAIN,
- SCMI_PROTOCOL_ID_VOLTAGE_DOMAIN,
+ CONFIG_IS_ENABLED(SCMI_POWER_DOMAIN, (SCMI_PROTOCOL_ID_POWER_DOMAIN,))
+ CONFIG_IS_ENABLED(CLK_SCMI, (SCMI_PROTOCOL_ID_CLOCK,))
+ CONFIG_IS_ENABLED(RESET_SCMI, (SCMI_PROTOCOL_ID_RESET_DOMAIN,))
+ CONFIG_IS_ENABLED(DM_REGULATOR_SCMI, (SCMI_PROTOCOL_ID_VOLTAGE_DOMAIN,))
};
#define NUM_PROTOCOLS ARRAY_SIZE(protocols)
@@ -576,7 +576,7 @@
domain_id = *(u32 *)msg->in_msg;
out = (struct scmi_pwd_attrs_out *)msg->out_msg;
- if (domain_id > ARRAY_SIZE(scmi_pwdom)) {
+ if (domain_id >= ARRAY_SIZE(scmi_pwdom)) {
out->status = SCMI_NOT_FOUND;
return 0;
@@ -613,7 +613,7 @@
in = (struct scmi_pwd_state_set_in *)msg->in_msg;
status = (s32 *)msg->out_msg;
- if (in->domain_id > ARRAY_SIZE(scmi_pwdom)) {
+ if (in->domain_id >= ARRAY_SIZE(scmi_pwdom)) {
*status = SCMI_NOT_FOUND;
return 0;
@@ -653,7 +653,7 @@
domain_id = *(u32 *)msg->in_msg;
out = (struct scmi_pwd_state_get_out *)msg->out_msg;
- if (domain_id > ARRAY_SIZE(scmi_pwdom)) {
+ if (domain_id >= ARRAY_SIZE(scmi_pwdom)) {
out->status = SCMI_NOT_FOUND;
return 0;
@@ -686,7 +686,7 @@
domain_id = *(u32 *)msg->in_msg;
out = (struct scmi_pwd_name_get_out *)msg->out_msg;
- if (domain_id > ARRAY_SIZE(scmi_pwdom)) {
+ if (domain_id >= ARRAY_SIZE(scmi_pwdom)) {
out->status = SCMI_NOT_FOUND;
return 0;
@@ -1124,6 +1124,13 @@
return chan->channel_id;
}
+static int sandbox_proto_not_supported(struct scmi_msg *msg)
+{
+ *(u32 *)msg->out_msg = SCMI_NOT_SUPPORTED;
+
+ return 0;
+}
+
static int sandbox_scmi_test_process_msg(struct udevice *dev,
struct scmi_channel *channel,
struct scmi_msg *msg)
@@ -1160,6 +1167,9 @@
}
break;
case SCMI_PROTOCOL_ID_POWER_DOMAIN:
+ if (!CONFIG_IS_ENABLED(SCMI_POWER_DOMAIN))
+ return sandbox_proto_not_supported(msg);
+
switch (msg->message_id) {
case SCMI_PROTOCOL_VERSION:
return sandbox_scmi_pwd_protocol_version(dev, msg);
@@ -1180,6 +1190,9 @@
}
break;
case SCMI_PROTOCOL_ID_CLOCK:
+ if (!CONFIG_IS_ENABLED(CLK_SCMI))
+ return sandbox_proto_not_supported(msg);
+
switch (msg->message_id) {
case SCMI_PROTOCOL_ATTRIBUTES:
return sandbox_scmi_clock_protocol_attribs(dev, msg);
@@ -1196,6 +1209,9 @@
}
break;
case SCMI_PROTOCOL_ID_RESET_DOMAIN:
+ if (!CONFIG_IS_ENABLED(RESET_SCMI))
+ return sandbox_proto_not_supported(msg);
+
switch (msg->message_id) {
case SCMI_RESET_DOMAIN_ATTRIBUTES:
return sandbox_scmi_rd_attribs(dev, msg);
@@ -1206,6 +1222,9 @@
}
break;
case SCMI_PROTOCOL_ID_VOLTAGE_DOMAIN:
+ if (!CONFIG_IS_ENABLED(DM_REGULATOR_SCMI))
+ return sandbox_proto_not_supported(msg);
+
switch (msg->message_id) {
case SCMI_VOLTAGE_DOMAIN_ATTRIBUTES:
return sandbox_scmi_voltd_attribs(dev, msg);
@@ -1224,8 +1243,7 @@
case SCMI_PROTOCOL_ID_SYSTEM:
case SCMI_PROTOCOL_ID_PERF:
case SCMI_PROTOCOL_ID_SENSOR:
- *(u32 *)msg->out_msg = SCMI_NOT_SUPPORTED;
- return 0;
+ return sandbox_proto_not_supported(msg);
default:
break;
}
diff --git a/drivers/firmware/scmi/sandbox-scmi_devices.c b/drivers/firmware/scmi/sandbox-scmi_devices.c
index facb5b0..603e2bb 100644
--- a/drivers/firmware/scmi/sandbox-scmi_devices.c
+++ b/drivers/firmware/scmi/sandbox-scmi_devices.c
@@ -62,12 +62,13 @@
if (!devices)
return 0;
- for (n = 0; n < SCMI_TEST_DEVICES_RD_COUNT; n++) {
- int ret2 = reset_free(devices->reset + n);
+ if (CONFIG_IS_ENABLED(RESET_SCMI))
+ for (n = 0; n < SCMI_TEST_DEVICES_RD_COUNT; n++) {
+ int ret2 = reset_free(devices->reset + n);
- if (ret2 && !ret)
- ret = ret2;
- }
+ if (ret2 && !ret)
+ ret = ret2;
+ }
return ret;
}
@@ -89,39 +90,53 @@
.regul_count = SCMI_TEST_DEVICES_VOLTD_COUNT,
};
- ret = power_domain_get_by_index(dev, priv->devices.pwdom, 0);
- if (ret) {
- dev_err(dev, "%s: Failed on power domain\n", __func__);
- return ret;
- }
-
- for (n = 0; n < SCMI_TEST_DEVICES_CLK_COUNT; n++) {
- ret = clk_get_by_index(dev, n, priv->devices.clk + n);
+ if (CONFIG_IS_ENABLED(SCMI_POWER_DOMAIN)) {
+ ret = power_domain_get_by_index(dev, priv->devices.pwdom, 0);
if (ret) {
- dev_err(dev, "%s: Failed on clk %zu\n", __func__, n);
+ dev_err(dev, "%s: Failed on power domain\n", __func__);
return ret;
}
}
- for (n = 0; n < SCMI_TEST_DEVICES_RD_COUNT; n++) {
- ret = reset_get_by_index(dev, n, priv->devices.reset + n);
- if (ret) {
- dev_err(dev, "%s: Failed on reset %zu\n", __func__, n);
- goto err_reset;
+ if (CONFIG_IS_ENABLED(CLK_SCMI)) {
+ for (n = 0; n < SCMI_TEST_DEVICES_CLK_COUNT; n++) {
+ ret = clk_get_by_index(dev, n, priv->devices.clk + n);
+ if (ret) {
+ dev_err(dev, "%s: Failed on clk %zu\n",
+ __func__, n);
+ return ret;
+ }
}
}
- for (n = 0; n < SCMI_TEST_DEVICES_VOLTD_COUNT; n++) {
- char name[32];
+ if (CONFIG_IS_ENABLED(RESET_SCMI)) {
+ for (n = 0; n < SCMI_TEST_DEVICES_RD_COUNT; n++) {
+ ret = reset_get_by_index(dev, n,
+ priv->devices.reset + n);
+ if (ret) {
+ dev_err(dev, "%s: Failed on reset %zu\n",
+ __func__, n);
+ goto err_reset;
+ }
+ }
+ }
- ret = snprintf(name, sizeof(name), "regul%zu-supply", n);
- assert(ret >= 0 && ret < sizeof(name));
+ if (CONFIG_IS_ENABLED(DM_REGULATOR_SCMI)) {
+ for (n = 0; n < SCMI_TEST_DEVICES_VOLTD_COUNT; n++) {
+ char name[32];
- ret = device_get_supply_regulator(dev, name,
- priv->devices.regul + n);
- if (ret) {
- dev_err(dev, "%s: Failed on voltd %zu\n", __func__, n);
- goto err_regul;
+ ret = snprintf(name, sizeof(name), "regul%zu-supply",
+ n);
+ assert(ret >= 0 && ret < sizeof(name));
+
+ ret = device_get_supply_regulator(dev, name,
+ priv->devices.regul
+ + n);
+ if (ret) {
+ dev_err(dev, "%s: Failed on voltd %zu\n",
+ __func__, n);
+ goto err_regul;
+ }
}
}
@@ -130,8 +145,9 @@
err_regul:
n = SCMI_TEST_DEVICES_RD_COUNT;
err_reset:
- for (; n > 0; n--)
- reset_free(priv->devices.reset + n - 1);
+ if (CONFIG_IS_ENABLED(RESET_SCMI))
+ for (; n > 0; n--)
+ reset_free(priv->devices.reset + n - 1);
return ret;
}
diff --git a/drivers/firmware/ti_sci.c b/drivers/firmware/ti_sci.c
index 166bd78..6e9f93e 100644
--- a/drivers/firmware/ti_sci.c
+++ b/drivers/firmware/ti_sci.c
@@ -3,7 +3,7 @@
* Texas Instruments System Control Interface Protocol Driver
* Based on drivers/firmware/ti_sci.c from Linux.
*
- * Copyright (C) 2018 Texas Instruments Incorporated - http://www.ti.com/
+ * Copyright (C) 2018 Texas Instruments Incorporated - https://www.ti.com/
* Lokesh Vutla <lokeshvutla@ti.com>
*/
diff --git a/drivers/firmware/ti_sci.h b/drivers/firmware/ti_sci.h
index 101210e..bb8bc7b 100644
--- a/drivers/firmware/ti_sci.h
+++ b/drivers/firmware/ti_sci.h
@@ -6,7 +6,7 @@
* The system works in a message response protocol
* See: http://processors.wiki.ti.com/index.php/TISCI for details
*
- * Copyright (C) 2018 Texas Instruments Incorporated - http://www.ti.com/
+ * Copyright (C) 2018 Texas Instruments Incorporated - https://www.ti.com/
* Based on drivers/firmware/ti_sci.h from Linux.
*
*/
diff --git a/drivers/firmware/ti_sci_static_data.h b/drivers/firmware/ti_sci_static_data.h
index 1a461fa..567ce89 100644
--- a/drivers/firmware/ti_sci_static_data.h
+++ b/drivers/firmware/ti_sci_static_data.h
@@ -1,6 +1,6 @@
/* SPDX-License-Identifier: BSD-3-Clause */
/*
- * Copyright (C) 2021 Texas Instruments Incorporated - http://www.ti.com/
+ * Copyright (C) 2021 Texas Instruments Incorporated - https://www.ti.com/
*
*/
diff --git a/drivers/gpio/pcf8575_gpio.c b/drivers/gpio/pcf8575_gpio.c
index d5930d9..f38e215 100644
--- a/drivers/gpio/pcf8575_gpio.c
+++ b/drivers/gpio/pcf8575_gpio.c
@@ -2,7 +2,7 @@
/*
* PCF8575 I2C GPIO EXPANDER DRIVER
*
- * Copyright (C) 2016 Texas Instruments Incorporated - http://www.ti.com/
+ * Copyright (C) 2016 Texas Instruments Incorporated - https://www.ti.com/
*
* Vignesh R <vigneshr@ti.com>
*
diff --git a/drivers/i2c/i2c-uclass.c b/drivers/i2c/i2c-uclass.c
index 5405067..98f9585 100644
--- a/drivers/i2c/i2c-uclass.c
+++ b/drivers/i2c/i2c-uclass.c
@@ -427,7 +427,7 @@
goto err_exit;
}
- ret = dev_read_u32(parent, "i2cbcdev", &phandle);
+ ret = dev_read_u32(parent, prop_name, &phandle);
if (ret)
goto err_exit;
diff --git a/drivers/i2c/stm32f7_i2c.c b/drivers/i2c/stm32f7_i2c.c
index b6c7178..eaa1d69 100644
--- a/drivers/i2c/stm32f7_i2c.c
+++ b/drivers/i2c/stm32f7_i2c.c
@@ -20,6 +20,7 @@
#include <linux/err.h>
#include <linux/io.h>
#include <linux/printk.h>
+#include <linux/time.h>
/* STM32 I2C registers */
struct stm32_i2c_regs {
@@ -121,8 +122,6 @@
#define STM32_SCLH_MAX BIT(8)
#define STM32_SCLL_MAX BIT(8)
-#define STM32_NSEC_PER_SEC 1000000000L
-
/**
* struct stm32_i2c_spec - private i2c specification timing
* @rate: I2C bus speed (Hz)
@@ -591,7 +590,7 @@
struct stm32_i2c_timings *s)
{
struct stm32_i2c_timings *v;
- u32 i2cbus = DIV_ROUND_CLOSEST(STM32_NSEC_PER_SEC,
+ u32 i2cbus = DIV_ROUND_CLOSEST(NSEC_PER_SEC,
setup->speed_freq);
u32 clk_error_prev = i2cbus;
u32 clk_min, clk_max;
@@ -607,8 +606,8 @@
dnf_delay = setup->dnf * i2cclk;
tsync = af_delay_min + dnf_delay + (2 * i2cclk);
- clk_max = STM32_NSEC_PER_SEC / specs->rate_min;
- clk_min = STM32_NSEC_PER_SEC / specs->rate_max;
+ clk_max = NSEC_PER_SEC / specs->rate_min;
+ clk_min = NSEC_PER_SEC / specs->rate_max;
/*
* Among Prescaler possibilities discovered above figures out SCL Low
@@ -686,7 +685,7 @@
const struct stm32_i2c_spec *specs;
struct stm32_i2c_timings *v, *_v;
struct list_head solutions;
- u32 i2cclk = DIV_ROUND_CLOSEST(STM32_NSEC_PER_SEC, setup->clock_src);
+ u32 i2cclk = DIV_ROUND_CLOSEST(NSEC_PER_SEC, setup->clock_src);
int ret;
specs = get_specs(setup->speed_freq);
diff --git a/drivers/led/Kconfig b/drivers/led/Kconfig
index 996b757..9837960 100644
--- a/drivers/led/Kconfig
+++ b/drivers/led/Kconfig
@@ -49,6 +49,14 @@
This option enables support for LEDs connected to the Cortina
Access CAxxxx SOCs.
+config LED_LP5562
+ bool "LED Support for LP5562"
+ depends on LED && DM_I2C
+ help
+ This option enables support for LEDs connected to the TI LP5562
+ 4 channel I2C LED controller. Driver fully supports blink on the
+ B/G/R LEDs. White LED can blink, but re-uses the period from blue.
+
config LED_PWM
bool "LED PWM"
depends on LED && DM_PWM
diff --git a/drivers/led/Makefile b/drivers/led/Makefile
index 49ae919..2bcb858 100644
--- a/drivers/led/Makefile
+++ b/drivers/led/Makefile
@@ -11,3 +11,4 @@
obj-$(CONFIG_LED_PWM) += led_pwm.o
obj-$(CONFIG_$(SPL_)LED_GPIO) += led_gpio.o
obj-$(CONFIG_LED_CORTINA) += led_cortina.o
+obj-$(CONFIG_LED_LP5562) += led_lp5562.o
diff --git a/drivers/led/led-uclass.c b/drivers/led/led-uclass.c
index 68ca3c2..a4be56f 100644
--- a/drivers/led/led-uclass.c
+++ b/drivers/led/led-uclass.c
@@ -11,9 +11,27 @@
#include <errno.h>
#include <led.h>
#include <dm/device-internal.h>
+#include <dm/lists.h>
#include <dm/root.h>
#include <dm/uclass-internal.h>
+int led_bind_generic(struct udevice *parent, const char *driver_name)
+{
+ struct udevice *dev;
+ ofnode node;
+ int ret;
+
+ dev_for_each_subnode(node, parent) {
+ ret = device_bind_driver_to_node(parent, driver_name,
+ ofnode_get_name(node),
+ node, &dev);
+ if (ret)
+ return ret;
+ }
+
+ return 0;
+}
+
int led_get_by_label(const char *label, struct udevice **devp)
{
struct udevice *dev;
@@ -71,8 +89,10 @@
struct led_uc_plat *uc_plat = dev_get_uclass_plat(dev);
const char *default_state;
- uc_plat->label = dev_read_string(dev, "label");
if (!uc_plat->label)
+ uc_plat->label = dev_read_string(dev, "label");
+
+ if (!uc_plat->label && !dev_read_string(dev, "compatible"))
uc_plat->label = ofnode_get_name(dev_ofnode(dev));
uc_plat->default_state = LEDST_COUNT;
diff --git a/drivers/led/led_gpio.c b/drivers/led/led_gpio.c
index fbed151..71421de 100644
--- a/drivers/led/led_gpio.c
+++ b/drivers/led/led_gpio.c
@@ -11,7 +11,6 @@
#include <log.h>
#include <malloc.h>
#include <asm/gpio.h>
-#include <dm/lists.h>
struct led_gpio_priv {
struct gpio_desc gpio;
@@ -80,19 +79,7 @@
static int led_gpio_bind(struct udevice *parent)
{
- struct udevice *dev;
- ofnode node;
- int ret;
-
- dev_for_each_subnode(node, parent) {
- ret = device_bind_driver_to_node(parent, "gpio_led",
- ofnode_get_name(node),
- node, &dev);
- if (ret)
- return ret;
- }
-
- return 0;
+ return led_bind_generic(parent, "gpio_led");
}
static const struct led_ops gpio_led_ops = {
diff --git a/drivers/led/led_lp5562.c b/drivers/led/led_lp5562.c
new file mode 100644
index 0000000..431d7e1
--- /dev/null
+++ b/drivers/led/led_lp5562.c
@@ -0,0 +1,577 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2018 Doug Zobel <douglas.zobel@climate.com>
+ *
+ * Driver for TI lp5562 4 channel LED driver. There are only 3
+ * engines available for the 4 LEDs, so white and blue LEDs share
+ * the same engine. This means that the blink period is shared
+ * between them. Changing the period of blue blink will affect
+ * the white period (and vice-versa). Blue and white On/Off
+ * states remain independent (as would PWM brightness if that's
+ * ever added to the LED core).
+ */
+
+#include <dm.h>
+#include <errno.h>
+#include <led.h>
+#include <i2c.h>
+#include <asm/gpio.h>
+#include <linux/delay.h>
+
+#define DEFAULT_CURRENT 100 /* 10 mA */
+#define MIN_BLINK_PERIOD 32 /* ms */
+#define MAX_BLINK_PERIOD 2248 /* ms */
+
+/* Register Map */
+#define REG_ENABLE 0x00
+#define REG_OP_MODE 0x01
+#define REG_B_PWM 0x02
+#define REG_G_PWM 0x03
+#define REG_R_PWM 0x04
+#define REG_B_CUR 0x05
+#define REG_G_CUR 0x06
+#define REG_R_CUR 0x07
+#define REG_CONFIG 0x08
+#define REG_ENG1_PC 0x09
+#define REG_ENG2_PC 0x0A
+#define REG_ENG3_PC 0x0B
+#define REG_STATUS 0x0C
+#define REG_RESET 0x0D
+#define REG_W_PWM 0x0E
+#define REG_W_CUR 0x0F
+#define REG_ENG1_MEM_BEGIN 0x10
+#define REG_ENG2_MEM_BEGIN 0x30
+#define REG_ENG3_MEM_BEGIN 0x50
+#define REG_LED_MAP 0x70
+
+/* LED Register Values */
+/* 0x00 ENABLE */
+#define REG_ENABLE_CHIP_ENABLE (0x1 << 6)
+#define REG_ENABLE_ENG_EXEC_HOLD 0x0
+#define REG_ENABLE_ENG_EXEC_RUN 0x2
+#define REG_ENABLE_ENG_EXEC_MASK 0x3
+
+/* 0x01 OP MODE */
+#define REG_OP_MODE_DISABLED 0x0
+#define REG_OP_MODE_LOAD_SRAM 0x1
+#define REG_OP_MODE_RUN 0x2
+#define REG_OP_MODE_MASK 0x3
+
+/* 0x02, 0x03, 0x04, 0x0E PWM */
+#define REG_PWM_MIN_VALUE 0
+#define REG_PWM_MAX_VALUE 0xFF
+
+/* 0x08 CONFIG */
+#define REG_CONFIG_EXT_CLK 0x0
+#define REG_CONFIG_INT_CLK 0x1
+#define REG_CONFIG_AUTO_CLK 0x2
+#define REG_CONFIG_CLK_MASK 0x3
+
+/* 0x0D RESET */
+#define REG_RESET_RESET 0xFF
+
+/* 0x70 LED MAP */
+#define REG_LED_MAP_ENG_MASK 0x03
+#define REG_LED_MAP_W_ENG_SHIFT 6
+#define REG_LED_MAP_R_ENG_SHIFT 4
+#define REG_LED_MAP_G_ENG_SHIFT 2
+#define REG_LED_MAP_B_ENG_SHIFT 0
+
+/* Engine program related */
+#define REG_ENGINE_MEM_SIZE 0x20
+#define LED_PGRM_RAMP_INCREMENT_SHIFT 0
+#define LED_PGRM_RAMP_SIGN_SHIFT 7
+#define LED_PGRM_RAMP_STEP_SHIFT 8
+#define LED_PGRM_RAMP_PRESCALE_SHIFT 14
+
+struct lp5562_led_wrap_priv {
+ struct gpio_desc enable_gpio;
+};
+
+struct lp5562_led_priv {
+ u8 reg_pwm;
+ u8 reg_current;
+ u8 map_shift;
+ u8 enginenum;
+};
+
+/* enum values map to LED_MAP (0x70) values */
+enum lp5562_led_ctl_mode {
+ I2C = 0x0,
+#ifdef CONFIG_LED_BLINK
+ ENGINE1 = 0x1,
+ ENGINE2 = 0x2,
+ ENGINE3 = 0x3
+#endif
+};
+
+/*
+ * Update a register value
+ * dev - I2C udevice (parent of led)
+ * regnum - register number to update
+ * value - value to write to register
+ * mask - mask of bits that should be changed
+ */
+static int lp5562_led_reg_update(struct udevice *dev, int regnum,
+ u8 value, u8 mask)
+{
+ int ret;
+
+ if (mask == 0xFF)
+ ret = dm_i2c_reg_write(dev, regnum, value);
+ else
+ ret = dm_i2c_reg_clrset(dev, regnum, mask, value);
+
+
+ /*
+ * Data sheet says "Delay between consecutive I2C writes to
+ * ENABLE register (00h) need to be longer than 488 μs
+ * (typical)." and "Delay between consecutive I2C writes to
+ * OP_MODE register need to be longer than 153 μs (typ)."
+ *
+ * The linux driver does usleep_range(500, 600) and
+ * usleep_range(200, 300), respectively.
+ */
+ switch (regnum) {
+ case REG_ENABLE:
+ udelay(600);
+ break;
+ case REG_OP_MODE:
+ udelay(300);
+ break;
+ }
+
+ return ret;
+}
+
+#ifdef CONFIG_LED_BLINK
+/*
+ * Program the lp5562 engine
+ * dev - I2C udevice (parent of led)
+ * program - array of commands
+ * size - number of commands in program array (1-16)
+ * engine - engine number (1-3)
+ */
+static int lp5562_led_program_engine(struct udevice *dev, u16 *program,
+ u8 size, u8 engine)
+{
+ int ret, cmd;
+ u8 engine_reg = REG_ENG1_MEM_BEGIN +
+ ((engine - 1) * REG_ENGINE_MEM_SIZE);
+ u8 shift = (3 - engine) * 2;
+ __be16 prog_be[16];
+
+ if (size < 1 || size > 16 || engine < 1 || engine > 3)
+ return -EINVAL;
+
+ for (cmd = 0; cmd < size; cmd++)
+ prog_be[cmd] = cpu_to_be16(program[cmd]);
+
+ /* set engine mode to 'disabled' */
+ ret = lp5562_led_reg_update(dev, REG_OP_MODE,
+ REG_OP_MODE_DISABLED << shift,
+ REG_OP_MODE_MASK << shift);
+ if (ret != 0)
+ goto done;
+
+ /* set exec mode to 'hold' */
+ ret = lp5562_led_reg_update(dev, REG_ENABLE,
+ REG_ENABLE_ENG_EXEC_HOLD << shift,
+ REG_ENABLE_ENG_EXEC_MASK << shift);
+ if (ret != 0)
+ goto done;
+
+ /* set engine mode to 'load SRAM' */
+ ret = lp5562_led_reg_update(dev, REG_OP_MODE,
+ REG_OP_MODE_LOAD_SRAM << shift,
+ REG_OP_MODE_MASK << shift);
+ if (ret != 0)
+ goto done;
+
+ /* send the re-ordered program sequence */
+ ret = dm_i2c_write(dev, engine_reg, (uchar *)prog_be, sizeof(u16) * size);
+ if (ret != 0)
+ goto done;
+
+ /* set engine mode to 'run' */
+ ret = lp5562_led_reg_update(dev, REG_OP_MODE,
+ REG_OP_MODE_RUN << shift,
+ REG_OP_MODE_MASK << shift);
+ if (ret != 0)
+ goto done;
+
+ /* set engine exec to 'run' */
+ ret = lp5562_led_reg_update(dev, REG_ENABLE,
+ REG_ENABLE_ENG_EXEC_RUN << shift,
+ REG_ENABLE_ENG_EXEC_MASK << shift);
+
+done:
+ return ret;
+}
+
+/*
+ * Get the LED's current control mode (I2C or ENGINE[1-3])
+ * dev - led udevice (child udevice)
+ */
+static enum lp5562_led_ctl_mode lp5562_led_get_control_mode(struct udevice *dev)
+{
+ struct lp5562_led_priv *priv = dev_get_priv(dev);
+ u8 data;
+ enum lp5562_led_ctl_mode mode = I2C;
+
+ if (dm_i2c_read(dev_get_parent(dev), REG_LED_MAP, &data, 1) == 0)
+ mode = (data & (REG_LED_MAP_ENG_MASK << priv->map_shift))
+ >> priv->map_shift;
+
+ return mode;
+}
+#endif
+
+/*
+ * Set the LED's control mode to I2C or ENGINE[1-3]
+ * dev - led udevice (child udevice)
+ * mode - mode to change to
+ */
+static int lp5562_led_set_control_mode(struct udevice *dev,
+ enum lp5562_led_ctl_mode mode)
+{
+ struct lp5562_led_priv *priv = dev_get_priv(dev);
+
+ return (lp5562_led_reg_update(dev_get_parent(dev), REG_LED_MAP,
+ mode << priv->map_shift,
+ REG_LED_MAP_ENG_MASK << priv->map_shift));
+}
+
+/*
+ * Return the LED's PWM value; If LED is in BLINK state, then it is
+ * under engine control mode which doesn't use this PWM value.
+ * dev - led udevice (child udevice)
+ */
+static int lp5562_led_get_pwm(struct udevice *dev)
+{
+ struct lp5562_led_priv *priv = dev_get_priv(dev);
+ u8 data;
+
+ if (dm_i2c_read(dev_get_parent(dev), priv->reg_pwm, &data, 1) != 0)
+ return -EINVAL;
+
+ return data;
+}
+
+/*
+ * Set the LED's PWM value and configure it to use this (I2C mode).
+ * dev - led udevice (child udevice)
+ * value - PWM value (0 - 255)
+ */
+static int lp5562_led_set_pwm(struct udevice *dev, u8 value)
+{
+ struct lp5562_led_priv *priv = dev_get_priv(dev);
+
+ if (lp5562_led_reg_update(dev_get_parent(dev), priv->reg_pwm,
+ value, 0xff) != 0)
+ return -EINVAL;
+
+ /* set LED to I2C register mode */
+ return lp5562_led_set_control_mode(dev, I2C);
+}
+
+/*
+ * Return the led's current state
+ * dev - led udevice (child udevice)
+ *
+ */
+static enum led_state_t lp5562_led_get_state(struct udevice *dev)
+{
+ enum led_state_t state = LEDST_ON;
+
+ if (lp5562_led_get_pwm(dev) == REG_PWM_MIN_VALUE)
+ state = LEDST_OFF;
+
+#ifdef CONFIG_LED_BLINK
+ if (lp5562_led_get_control_mode(dev) != I2C)
+ state = LEDST_BLINK;
+#endif
+
+ return state;
+}
+
+/*
+ * Set the led state
+ * dev - led udevice (child udevice)
+ * state - State to set the LED to
+ */
+static int lp5562_led_set_state(struct udevice *dev, enum led_state_t state)
+{
+#ifdef CONFIG_LED_BLINK
+ struct lp5562_led_priv *priv = dev_get_priv(dev);
+#endif
+
+ switch (state) {
+ case LEDST_OFF:
+ return lp5562_led_set_pwm(dev, REG_PWM_MIN_VALUE);
+ case LEDST_ON:
+ return lp5562_led_set_pwm(dev, REG_PWM_MAX_VALUE);
+#ifdef CONFIG_LED_BLINK
+ case LEDST_BLINK:
+ return lp5562_led_set_control_mode(dev, priv->enginenum);
+#endif
+ case LEDST_TOGGLE:
+ if (lp5562_led_get_state(dev) == LEDST_OFF)
+ return lp5562_led_set_state(dev, LEDST_ON);
+ else
+ return lp5562_led_set_state(dev, LEDST_OFF);
+ break;
+ default:
+ return -EINVAL;
+ }
+
+ return 0;
+}
+
+#ifdef CONFIG_LED_BLINK
+/*
+ * Set the blink period of an LED; note blue and white share the same
+ * engine so changing the period of one affects the other.
+ * dev - led udevice (child udevice)
+ * period_ms - blink period in ms
+ */
+static int lp5562_led_set_period(struct udevice *dev, int period_ms)
+{
+ struct lp5562_led_priv *priv = dev_get_priv(dev);
+ u8 opcode = 0;
+ u16 program[7];
+ u16 wait_time;
+
+ /* Blink is implemented as an engine program. Simple on/off
+ * for short periods, or fade in/fade out for longer periods:
+ *
+ * if (period_ms < 500):
+ * set PWM to 100%
+ * pause for period / 2
+ * set PWM to 0%
+ * pause for period / 2
+ * goto start
+ *
+ * else
+ * raise PWM 0% -> 50% in 62.7 ms
+ * raise PWM 50% -> 100% in 62.7 ms
+ * pause for (period - 4 * 62.7) / 2
+ * lower PWM 100% -> 50% in 62.7 ms
+ * lower PWM 50% -> 0% in 62.7 ms
+ * pause for (period - 4 * 62.7) / 2
+ * goto start
+ */
+
+ if (period_ms < MIN_BLINK_PERIOD)
+ period_ms = MIN_BLINK_PERIOD;
+ else if (period_ms > MAX_BLINK_PERIOD)
+ period_ms = MAX_BLINK_PERIOD;
+
+ if (period_ms < 500) {
+ /* Simple on/off blink */
+ wait_time = period_ms / 2;
+
+ /* 1st command is full brightness */
+ program[opcode++] =
+ (1 << LED_PGRM_RAMP_PRESCALE_SHIFT) |
+ REG_PWM_MAX_VALUE;
+
+ /* 2nd command is wait (period / 2) using 15.6ms steps */
+ program[opcode++] =
+ (1 << LED_PGRM_RAMP_PRESCALE_SHIFT) |
+ (((wait_time * 10) / 156) << LED_PGRM_RAMP_STEP_SHIFT) |
+ (0 << LED_PGRM_RAMP_INCREMENT_SHIFT);
+
+ /* 3rd command is 0% brightness */
+ program[opcode++] =
+ (1 << LED_PGRM_RAMP_PRESCALE_SHIFT);
+
+ /* 4th command is wait (period / 2) using 15.6ms steps */
+ program[opcode++] =
+ (1 << LED_PGRM_RAMP_PRESCALE_SHIFT) |
+ (((wait_time * 10) / 156) << LED_PGRM_RAMP_STEP_SHIFT) |
+ (0 << LED_PGRM_RAMP_INCREMENT_SHIFT);
+
+ /* 5th command: repeat */
+ program[opcode++] = 0x00;
+ } else {
+ /* fade-in / fade-out blink */
+ wait_time = ((period_ms - 251) / 2);
+
+ /* ramp up time is 256 * 0.49ms (125.4ms) done in 2 steps */
+ /* 1st command is ramp up 1/2 way */
+ program[opcode++] =
+ (0 << LED_PGRM_RAMP_PRESCALE_SHIFT) |
+ (1 << LED_PGRM_RAMP_STEP_SHIFT) |
+ (127 << LED_PGRM_RAMP_INCREMENT_SHIFT);
+
+ /* 2nd command is ramp up rest of the way */
+ program[opcode++] =
+ (0 << LED_PGRM_RAMP_PRESCALE_SHIFT) |
+ (1 << LED_PGRM_RAMP_STEP_SHIFT) |
+ (127 << LED_PGRM_RAMP_INCREMENT_SHIFT);
+
+ /* 3rd: wait ((period - 2 * ramp_time) / 2) (15.6ms steps) */
+ program[opcode++] =
+ (1 << LED_PGRM_RAMP_PRESCALE_SHIFT) |
+ (((wait_time * 10) / 156) << LED_PGRM_RAMP_STEP_SHIFT) |
+ (0 << LED_PGRM_RAMP_INCREMENT_SHIFT);
+
+ /* ramp down is same as ramp up with sign bit set */
+ /* 4th command is ramp down 1/2 way */
+ program[opcode++] =
+ (0 << LED_PGRM_RAMP_PRESCALE_SHIFT) |
+ (1 << LED_PGRM_RAMP_STEP_SHIFT) |
+ (1 << LED_PGRM_RAMP_SIGN_SHIFT) |
+ (127 << LED_PGRM_RAMP_INCREMENT_SHIFT);
+
+ /* 5th command is ramp down rest of the way */
+ program[opcode++] =
+ (0 << LED_PGRM_RAMP_PRESCALE_SHIFT) |
+ (1 << LED_PGRM_RAMP_STEP_SHIFT) |
+ (1 << LED_PGRM_RAMP_SIGN_SHIFT) |
+ (127 << LED_PGRM_RAMP_INCREMENT_SHIFT);
+
+ /* 6th: wait ((period - 2 * ramp_time) / 2) (15.6ms steps) */
+ program[opcode++] =
+ (1 << LED_PGRM_RAMP_PRESCALE_SHIFT) |
+ (((wait_time * 10) / 156) << LED_PGRM_RAMP_STEP_SHIFT) |
+ (0 << LED_PGRM_RAMP_INCREMENT_SHIFT);
+
+ /* 7th command: repeat */
+ program[opcode++] = 0x00;
+ }
+
+ return lp5562_led_program_engine(dev_get_parent(dev), program,
+ opcode, priv->enginenum);
+}
+#endif
+
+static const struct led_ops lp5562_led_ops = {
+ .get_state = lp5562_led_get_state,
+ .set_state = lp5562_led_set_state,
+#ifdef CONFIG_LED_BLINK
+ .set_period = lp5562_led_set_period,
+#endif
+};
+
+static int lp5562_led_probe(struct udevice *dev)
+{
+ struct lp5562_led_priv *priv = dev_get_priv(dev);
+ u8 current;
+ int ret = 0;
+
+ /* Child LED nodes */
+ switch (dev_read_addr(dev)) {
+ case 0:
+ priv->reg_current = REG_R_CUR;
+ priv->reg_pwm = REG_R_PWM;
+ priv->map_shift = REG_LED_MAP_R_ENG_SHIFT;
+ priv->enginenum = 1;
+ break;
+ case 1:
+ priv->reg_current = REG_G_CUR;
+ priv->reg_pwm = REG_G_PWM;
+ priv->map_shift = REG_LED_MAP_G_ENG_SHIFT;
+ priv->enginenum = 2;
+ break;
+ case 2:
+ priv->reg_current = REG_B_CUR;
+ priv->reg_pwm = REG_B_PWM;
+ priv->map_shift = REG_LED_MAP_B_ENG_SHIFT;
+ priv->enginenum = 3; /* shared with white */
+ break;
+ case 3:
+ priv->reg_current = REG_W_CUR;
+ priv->map_shift = REG_LED_MAP_W_ENG_SHIFT;
+ priv->enginenum = 3; /* shared with blue */
+ break;
+ default:
+ return -EINVAL;
+ }
+
+ current = dev_read_u8_default(dev, "max-cur", DEFAULT_CURRENT);
+
+ ret = lp5562_led_reg_update(dev_get_parent(dev), priv->reg_current,
+ current, 0xff);
+
+ return ret;
+}
+
+static int lp5562_led_bind(struct udevice *dev)
+{
+ struct led_uc_plat *uc_plat = dev_get_uclass_plat(dev);
+
+ /*
+ * For the child nodes, parse a "chan-name" property, since
+ * the DT bindings for this device use that instead of
+ * "label".
+ */
+ uc_plat->label = dev_read_string(dev, "chan-name");
+
+ return 0;
+}
+
+U_BOOT_DRIVER(lp5562_led) = {
+ .name = "lp5562-led",
+ .id = UCLASS_LED,
+ .bind = lp5562_led_bind,
+ .probe = lp5562_led_probe,
+ .priv_auto = sizeof(struct lp5562_led_priv),
+ .ops = &lp5562_led_ops,
+};
+
+
+static int lp5562_led_wrap_probe(struct udevice *dev)
+{
+ struct lp5562_led_wrap_priv *priv = dev_get_priv(dev);
+ u8 clock_mode;
+ int ret;
+
+ /* Enable gpio if needed */
+ if (gpio_request_by_name(dev, "enabled-gpios", 0,
+ &priv->enable_gpio, GPIOD_IS_OUT) == 0) {
+ dm_gpio_set_value(&priv->enable_gpio, 1);
+ udelay(1000);
+ }
+
+ /* Ensure all registers have default values. */
+ ret = lp5562_led_reg_update(dev, REG_RESET, REG_RESET_RESET, 0xff);
+ if (ret)
+ return ret;
+ udelay(10000);
+
+ /* Enable the chip */
+ ret = lp5562_led_reg_update(dev, REG_ENABLE, REG_ENABLE_CHIP_ENABLE, 0xff);
+ if (ret)
+ return ret;
+
+ /*
+ * The DT bindings say 0=auto, 1=internal, 2=external, while
+ * the register[0:1] values are 0=external, 1=internal,
+ * 2=auto.
+ */
+ clock_mode = dev_read_u8_default(dev, "clock-mode", 0);
+ ret = lp5562_led_reg_update(dev, REG_CONFIG, 2 - clock_mode, REG_CONFIG_CLK_MASK);
+
+ return ret;
+}
+
+static int lp5562_led_wrap_bind(struct udevice *dev)
+{
+ return led_bind_generic(dev, "lp5562-led");
+}
+
+static const struct udevice_id lp5562_led_ids[] = {
+ { .compatible = "ti,lp5562" },
+ { /* sentinel */ }
+};
+
+U_BOOT_DRIVER(lp5562_led_wrap) = {
+ .name = "lp5562-led-wrap",
+ .id = UCLASS_NOP,
+ .of_match = lp5562_led_ids,
+ .bind = lp5562_led_wrap_bind,
+ .probe = lp5562_led_wrap_probe,
+ .priv_auto = sizeof(struct lp5562_led_wrap_priv),
+};
diff --git a/drivers/led/led_pwm.c b/drivers/led/led_pwm.c
index 7c8eae9..ae6de30 100644
--- a/drivers/led/led_pwm.c
+++ b/drivers/led/led_pwm.c
@@ -9,7 +9,6 @@
#include <errno.h>
#include <led.h>
#include <malloc.h>
-#include <dm/lists.h>
#include <pwm.h>
#define LEDS_PWM_DRIVER_NAME "led_pwm"
@@ -136,18 +135,7 @@
static int led_pwm_bind(struct udevice *parent)
{
- struct udevice *dev;
- ofnode node;
- int ret;
-
- dev_for_each_subnode(node, parent) {
- ret = device_bind_driver_to_node(parent, LEDS_PWM_DRIVER_NAME,
- ofnode_get_name(node),
- node, &dev);
- if (ret)
- return ret;
- }
- return 0;
+ return led_bind_generic(parent, LEDS_PWM_DRIVER_NAME);
}
static const struct led_ops led_pwm_ops = {
diff --git a/drivers/mailbox/k3-sec-proxy.c b/drivers/mailbox/k3-sec-proxy.c
index e0a18d8..05f6b17 100644
--- a/drivers/mailbox/k3-sec-proxy.c
+++ b/drivers/mailbox/k3-sec-proxy.c
@@ -2,7 +2,7 @@
/*
* Texas Instruments' K3 Secure proxy Driver
*
- * Copyright (C) 2017-2018 Texas Instruments Incorporated - http://www.ti.com/
+ * Copyright (C) 2017-2018 Texas Instruments Incorporated - https://www.ti.com/
* Lokesh Vutla <lokeshvutla@ti.com>
*/
diff --git a/drivers/memory/stm32-fmc2-ebi.c b/drivers/memory/stm32-fmc2-ebi.c
index 212bb4f..a722a38 100644
--- a/drivers/memory/stm32-fmc2-ebi.c
+++ b/drivers/memory/stm32-fmc2-ebi.c
@@ -14,6 +14,7 @@
#include <linux/err.h>
#include <linux/iopoll.h>
#include <linux/ioport.h>
+#include <linux/time.h>
/* FMC2 Controller Registers */
#define FMC2_BCR1 0x0
@@ -90,8 +91,6 @@
#define FMC2_BTR_DATLAT_MAX 0xf
#define FMC2_PCSCNTR_CSCOUNT_MAX 0xff
-#define FMC2_NSEC_PER_SEC 1000000000L
-
enum stm32_fmc2_ebi_bank {
FMC2_EBI1 = 0,
FMC2_EBI2,
@@ -279,7 +278,7 @@
int cs, u32 setup)
{
unsigned long hclk = clk_get_rate(&ebi->clk);
- unsigned long hclkp = FMC2_NSEC_PER_SEC / (hclk / 1000);
+ unsigned long hclkp = NSEC_PER_SEC / (hclk / 1000);
return DIV_ROUND_UP(setup * 1000, hclkp);
}
diff --git a/drivers/memory/ti-aemif.c b/drivers/memory/ti-aemif.c
index c4bc88c..41325eb 100644
--- a/drivers/memory/ti-aemif.c
+++ b/drivers/memory/ti-aemif.c
@@ -7,6 +7,7 @@
*/
#include <common.h>
+#include <asm/arch/hardware.h>
#include <asm/ti-common/ti-aemif.h>
#define AEMIF_WAITCYCLE_CONFIG (KS2_AEMIF_CNTRL_BASE + 0x4)
diff --git a/drivers/memory/ti-gpmc.c b/drivers/memory/ti-gpmc.c
index f511a52..775e78c 100644
--- a/drivers/memory/ti-gpmc.c
+++ b/drivers/memory/ti-gpmc.c
@@ -2,7 +2,7 @@
/*
* Texas Instruments GPMC Driver
*
- * Copyright (C) 2021 Texas Instruments Incorporated - http://www.ti.com/
+ * Copyright (C) 2021 Texas Instruments Incorporated - https://www.ti.com/
*/
#include <asm/io.h>
diff --git a/drivers/memory/ti-gpmc.h b/drivers/memory/ti-gpmc.h
index 90f8e65..6fe098a 100644
--- a/drivers/memory/ti-gpmc.h
+++ b/drivers/memory/ti-gpmc.h
@@ -2,7 +2,7 @@
/*
* Texas Instruments GPMC Driver
*
- * Copyright (C) 2021 Texas Instruments Incorporated - http://www.ti.com/
+ * Copyright (C) 2021 Texas Instruments Incorporated - https://www.ti.com/
*/
/* GPMC register offsets */
diff --git a/drivers/misc/esm_pmic.c b/drivers/misc/esm_pmic.c
index b971f32..a518f75 100644
--- a/drivers/misc/esm_pmic.c
+++ b/drivers/misc/esm_pmic.c
@@ -2,7 +2,7 @@
/*
* PMIC Error Signal Monitor driver
*
- * Copyright (C) 2019 Texas Instruments Incorporated - http://www.ti.com/
+ * Copyright (C) 2019 Texas Instruments Incorporated - https://www.ti.com/
* Tero Kristo <t-kristo@ti.com>
*
*/
diff --git a/drivers/misc/k3_avs.c b/drivers/misc/k3_avs.c
index 9a08824..0d29eff 100644
--- a/drivers/misc/k3_avs.c
+++ b/drivers/misc/k3_avs.c
@@ -2,7 +2,7 @@
/*
* Texas Instruments' K3 Clas 0 Adaptive Voltage Scaling driver
*
- * Copyright (C) 2019 Texas Instruments Incorporated - http://www.ti.com/
+ * Copyright (C) 2019 Texas Instruments Incorporated - https://www.ti.com/
* Tero Kristo <t-kristo@ti.com>
*
*/
diff --git a/drivers/misc/k3_esm.c b/drivers/misc/k3_esm.c
index 41faeb3..f6ac18b 100644
--- a/drivers/misc/k3_esm.c
+++ b/drivers/misc/k3_esm.c
@@ -2,7 +2,7 @@
/*
* Texas Instruments' K3 Error Signalling Module driver
*
- * Copyright (C) 2019 Texas Instruments Incorporated - http://www.ti.com/
+ * Copyright (C) 2019 Texas Instruments Incorporated - https://www.ti.com/
* Tero Kristo <t-kristo@ti.com>
*
*/
diff --git a/drivers/misc/rockchip-otp.c b/drivers/misc/rockchip-otp.c
index 4814e0e..4f75708 100644
--- a/drivers/misc/rockchip-otp.c
+++ b/drivers/misc/rockchip-otp.c
@@ -61,11 +61,20 @@
#define RK3588_OTPC_INT_ST 0x0084
#define RK3588_RD_DONE BIT(1)
+#define RV1126_OTP_NVM_CEB 0x00
+#define RV1126_OTP_NVM_RSTB 0x04
+#define RV1126_OTP_NVM_ST 0x18
+#define RV1126_OTP_NVM_RADDR 0x1C
+#define RV1126_OTP_NVM_RSTART 0x20
+#define RV1126_OTP_NVM_RDATA 0x24
+#define RV1126_OTP_READ_ST 0x30
+
struct rockchip_otp_plat {
void __iomem *base;
};
struct rockchip_otp_data {
+ int (*init)(struct udevice *dev);
int (*read)(struct udevice *dev, int offset, void *buf, int size);
int offset;
int size;
@@ -232,6 +241,48 @@
return 0;
}
+static int rockchip_rv1126_otp_init(struct udevice *dev)
+{
+ struct rockchip_otp_plat *otp = dev_get_plat(dev);
+ int ret;
+
+ writel(0x0, otp->base + RV1126_OTP_NVM_CEB);
+ ret = rockchip_otp_poll_timeout(otp, 0x1, RV1126_OTP_NVM_ST);
+
+ if (ret)
+ return ret;
+
+ writel(0x1, otp->base + RV1126_OTP_NVM_RSTB);
+ ret = rockchip_otp_poll_timeout(otp, 0x4, RV1126_OTP_NVM_ST);
+
+ if (ret)
+ return ret;
+
+ return 0;
+}
+
+static int rockchip_rv1126_otp_read(struct udevice *dev, int offset, void *buf,
+ int size)
+{
+ struct rockchip_otp_plat *otp = dev_get_plat(dev);
+ u32 status = 0;
+ u8 *buffer = buf;
+ int ret = 0;
+
+ while (size--) {
+ writel(offset++, otp->base + RV1126_OTP_NVM_RADDR);
+ writel(0x1, otp->base + RV1126_OTP_NVM_RSTART);
+ ret = readl_poll_timeout(otp->base + RV1126_OTP_READ_ST,
+ status, !status, OTPC_TIMEOUT);
+ if (ret)
+ return ret;
+
+ *buffer++ = (u8)(readl(otp->base + RV1126_OTP_NVM_RDATA) & 0xFF);
+ }
+
+ return 0;
+}
+
static int rockchip_otp_read(struct udevice *dev, int offset,
void *buf, int size)
{
@@ -286,6 +337,20 @@
return 0;
}
+static int rockchip_otp_probe(struct udevice *dev)
+{
+ struct rockchip_otp_data *data;
+
+ data = (struct rockchip_otp_data *)dev_get_driver_data(dev);
+ if (!data)
+ return -EINVAL;
+
+ if (data->init)
+ return data->init(dev);
+
+ return 0;
+}
+
static const struct rockchip_otp_data px30_data = {
.read = rockchip_px30_otp_read,
.size = 0x40,
@@ -304,6 +369,12 @@
.block_size = 4,
};
+static const struct rockchip_otp_data rv1126_data = {
+ .init = rockchip_rv1126_otp_init,
+ .read = rockchip_rv1126_otp_read,
+ .size = 0x40,
+};
+
static const struct udevice_id rockchip_otp_ids[] = {
{
.compatible = "rockchip,px30-otp",
@@ -321,6 +392,10 @@
.compatible = "rockchip,rk3588-otp",
.data = (ulong)&rk3588_data,
},
+ {
+ .compatible = "rockchip,rv1126-otp",
+ .data = (ulong)&rv1126_data,
+ },
{}
};
@@ -331,4 +406,5 @@
.of_to_plat = rockchip_otp_of_to_plat,
.plat_auto = sizeof(struct rockchip_otp_plat),
.ops = &rockchip_otp_ops,
+ .probe = rockchip_otp_probe,
};
diff --git a/drivers/mmc/am654_sdhci.c b/drivers/mmc/am654_sdhci.c
index fd667ae..05595bd 100644
--- a/drivers/mmc/am654_sdhci.c
+++ b/drivers/mmc/am654_sdhci.c
@@ -1,6 +1,6 @@
// SPDX-License-Identifier: GPL-2.0+
/*
- * Copyright (C) 2018 Texas Instruments Incorporated - http://www.ti.com/
+ * Copyright (C) 2018 Texas Instruments Incorporated - https://www.ti.com/
*
* Texas Instruments' K3 SD Host Controller Interface
*/
diff --git a/drivers/mmc/octeontx_hsmmc.h b/drivers/mmc/octeontx_hsmmc.h
index 70844b1..9849121 100644
--- a/drivers/mmc/octeontx_hsmmc.h
+++ b/drivers/mmc/octeontx_hsmmc.h
@@ -32,8 +32,6 @@
*/
#define MMC_TIMEOUT_SHORT 20
-#define NSEC_PER_SEC 1000000000L
-
#define MAX_NO_OF_TAPS 64
#define EXT_CSD_POWER_CLASS 187 /* R/W */
diff --git a/drivers/mmc/renesas-sdhi.c b/drivers/mmc/renesas-sdhi.c
index 8cd501c..97aaf1e 100644
--- a/drivers/mmc/renesas-sdhi.c
+++ b/drivers/mmc/renesas-sdhi.c
@@ -318,7 +318,7 @@
RENESAS_SDHI_SCC_DTCNTL_TAPNUM_MASK;
}
-static void renesas_sdhi_reset_tuning(struct tmio_sd_priv *priv)
+static void renesas_sdhi_reset_tuning(struct tmio_sd_priv *priv, bool clk_disable)
{
u32 reg;
@@ -350,6 +350,12 @@
reg = tmio_sd_readl(priv, RENESAS_SDHI_SCC_RVSCNTL);
reg &= ~RENESAS_SDHI_SCC_RVSCNTL_RVSEN;
tmio_sd_writel(priv, reg, RENESAS_SDHI_SCC_RVSCNTL);
+
+ if (clk_disable) {
+ reg = tmio_sd_readl(priv, TMIO_SD_CLKCTL);
+ reg &= ~TMIO_SD_CLKCTL_SCLKEN;
+ tmio_sd_writel(priv, reg, TMIO_SD_CLKCTL);
+ }
}
static int renesas_sdhi_hs400(struct udevice *dev)
@@ -629,7 +635,7 @@
out:
if (ret < 0) {
dev_warn(dev, "Tuning procedure failed\n");
- renesas_sdhi_reset_tuning(priv);
+ renesas_sdhi_reset_tuning(priv, true);
}
return ret;
@@ -668,7 +674,7 @@
(mmc->selected_mode != UHS_SDR104) &&
(mmc->selected_mode != MMC_HS_200) &&
(mmc->selected_mode != MMC_HS_400)) {
- renesas_sdhi_reset_tuning(priv);
+ renesas_sdhi_reset_tuning(priv, mmc->clk_disable);
}
#endif
@@ -1095,7 +1101,7 @@
CONFIG_IS_ENABLED(MMC_HS200_SUPPORT) || \
CONFIG_IS_ENABLED(MMC_HS400_SUPPORT)
if (priv->caps & TMIO_SD_CAP_RCAR_UHS)
- renesas_sdhi_reset_tuning(priv);
+ renesas_sdhi_reset_tuning(priv, true);
#endif
return 0;
diff --git a/drivers/mmc/sunxi_mmc.c b/drivers/mmc/sunxi_mmc.c
index 4d6351b..714706d 100644
--- a/drivers/mmc/sunxi_mmc.c
+++ b/drivers/mmc/sunxi_mmc.c
@@ -25,10 +25,14 @@
#include <asm/io.h>
#include <asm/arch/clock.h>
#include <asm/arch/cpu.h>
+#if !CONFIG_IS_ENABLED(DM_MMC)
#include <asm/arch/mmc.h>
+#endif
#include <linux/delay.h>
#include <sunxi_gpio.h>
+#include "sunxi_mmc.h"
+
#ifndef CCM_MMC_CTRL_MODE_SEL_NEW
#define CCM_MMC_CTRL_MODE_SEL_NEW 0
#endif
@@ -701,13 +705,13 @@
{ .compatible = "allwinner,sun7i-a20-mmc" },
{ .compatible = "allwinner,sun8i-a83t-emmc" },
{ .compatible = "allwinner,sun9i-a80-mmc" },
+ { .compatible = "allwinner,sun20i-d1-mmc" },
{ .compatible = "allwinner,sun50i-a64-mmc" },
{ .compatible = "allwinner,sun50i-a64-emmc" },
{ .compatible = "allwinner,sun50i-h6-mmc" },
{ .compatible = "allwinner,sun50i-h6-emmc" },
{ .compatible = "allwinner,sun50i-a100-mmc" },
{ .compatible = "allwinner,sun50i-a100-emmc" },
- { .compatible = "allwinner,sun20i-d1-mmc" },
{ /* sentinel */ }
};
diff --git a/drivers/mmc/sunxi_mmc.h b/drivers/mmc/sunxi_mmc.h
new file mode 100644
index 0000000..f4ae5a7
--- /dev/null
+++ b/drivers/mmc/sunxi_mmc.h
@@ -0,0 +1,138 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * (C) Copyright 2007-2011
+ * Allwinner Technology Co., Ltd. <www.allwinnertech.com>
+ * Aaron <leafy.myeh@allwinnertech.com>
+ *
+ * MMC register definition for allwinner sunxi platform.
+ */
+
+#ifndef _SUNXI_MMC_H
+#define _SUNXI_MMC_H
+
+#include <linux/types.h>
+
+struct sunxi_mmc {
+ u32 gctrl; /* 0x00 global control */
+ u32 clkcr; /* 0x04 clock control */
+ u32 timeout; /* 0x08 time out */
+ u32 width; /* 0x0c bus width */
+ u32 blksz; /* 0x10 block size */
+ u32 bytecnt; /* 0x14 byte count */
+ u32 cmd; /* 0x18 command */
+ u32 arg; /* 0x1c argument */
+ u32 resp0; /* 0x20 response 0 */
+ u32 resp1; /* 0x24 response 1 */
+ u32 resp2; /* 0x28 response 2 */
+ u32 resp3; /* 0x2c response 3 */
+ u32 imask; /* 0x30 interrupt mask */
+ u32 mint; /* 0x34 masked interrupt status */
+ u32 rint; /* 0x38 raw interrupt status */
+ u32 status; /* 0x3c status */
+ u32 ftrglevel; /* 0x40 FIFO threshold watermark*/
+ u32 funcsel; /* 0x44 function select */
+ u32 cbcr; /* 0x48 CIU byte count */
+ u32 bbcr; /* 0x4c BIU byte count */
+ u32 dbgc; /* 0x50 debug enable */
+ u32 res0; /* 0x54 reserved */
+ u32 a12a; /* 0x58 Auto command 12 argument */
+ u32 ntsr; /* 0x5c New timing set register */
+ u32 res1[8];
+ u32 dmac; /* 0x80 internal DMA control */
+ u32 dlba; /* 0x84 internal DMA descr list base address */
+ u32 idst; /* 0x88 internal DMA status */
+ u32 idie; /* 0x8c internal DMA interrupt enable */
+ u32 chda; /* 0x90 */
+ u32 cbda; /* 0x94 */
+ u32 res2[26];
+#if defined(CONFIG_SUNXI_GEN_SUN6I) || defined(CONFIG_SUN50I_GEN_H6) || defined(CONFIG_SUNXI_GEN_NCAT2)
+ u32 res3[17];
+ u32 samp_dl;
+ u32 res4[46];
+#endif
+ u32 fifo; /* 0x100 / 0x200 FIFO access address */
+};
+
+#define SUNXI_MMC_CLK_POWERSAVE (0x1 << 17)
+#define SUNXI_MMC_CLK_ENABLE (0x1 << 16)
+#define SUNXI_MMC_CLK_DIVIDER_MASK (0xff)
+
+#define SUNXI_MMC_GCTRL_SOFT_RESET (0x1 << 0)
+#define SUNXI_MMC_GCTRL_FIFO_RESET (0x1 << 1)
+#define SUNXI_MMC_GCTRL_DMA_RESET (0x1 << 2)
+#define SUNXI_MMC_GCTRL_RESET (SUNXI_MMC_GCTRL_SOFT_RESET|\
+ SUNXI_MMC_GCTRL_FIFO_RESET|\
+ SUNXI_MMC_GCTRL_DMA_RESET)
+#define SUNXI_MMC_GCTRL_DMA_ENABLE (0x1 << 5)
+#define SUNXI_MMC_GCTRL_ACCESS_BY_AHB (0x1 << 31)
+
+#define SUNXI_MMC_CMD_RESP_EXPIRE (0x1 << 6)
+#define SUNXI_MMC_CMD_LONG_RESPONSE (0x1 << 7)
+#define SUNXI_MMC_CMD_CHK_RESPONSE_CRC (0x1 << 8)
+#define SUNXI_MMC_CMD_DATA_EXPIRE (0x1 << 9)
+#define SUNXI_MMC_CMD_WRITE (0x1 << 10)
+#define SUNXI_MMC_CMD_AUTO_STOP (0x1 << 12)
+#define SUNXI_MMC_CMD_WAIT_PRE_OVER (0x1 << 13)
+#define SUNXI_MMC_CMD_SEND_INIT_SEQ (0x1 << 15)
+#define SUNXI_MMC_CMD_UPCLK_ONLY (0x1 << 21)
+#define SUNXI_MMC_CMD_START (0x1 << 31)
+
+#define SUNXI_MMC_RINT_RESP_ERROR (0x1 << 1)
+#define SUNXI_MMC_RINT_COMMAND_DONE (0x1 << 2)
+#define SUNXI_MMC_RINT_DATA_OVER (0x1 << 3)
+#define SUNXI_MMC_RINT_TX_DATA_REQUEST (0x1 << 4)
+#define SUNXI_MMC_RINT_RX_DATA_REQUEST (0x1 << 5)
+#define SUNXI_MMC_RINT_RESP_CRC_ERROR (0x1 << 6)
+#define SUNXI_MMC_RINT_DATA_CRC_ERROR (0x1 << 7)
+#define SUNXI_MMC_RINT_RESP_TIMEOUT (0x1 << 8)
+#define SUNXI_MMC_RINT_DATA_TIMEOUT (0x1 << 9)
+#define SUNXI_MMC_RINT_VOLTAGE_CHANGE_DONE (0x1 << 10)
+#define SUNXI_MMC_RINT_FIFO_RUN_ERROR (0x1 << 11)
+#define SUNXI_MMC_RINT_HARD_WARE_LOCKED (0x1 << 12)
+#define SUNXI_MMC_RINT_START_BIT_ERROR (0x1 << 13)
+#define SUNXI_MMC_RINT_AUTO_COMMAND_DONE (0x1 << 14)
+#define SUNXI_MMC_RINT_END_BIT_ERROR (0x1 << 15)
+#define SUNXI_MMC_RINT_SDIO_INTERRUPT (0x1 << 16)
+#define SUNXI_MMC_RINT_CARD_INSERT (0x1 << 30)
+#define SUNXI_MMC_RINT_CARD_REMOVE (0x1 << 31)
+#define SUNXI_MMC_RINT_INTERRUPT_ERROR_BIT \
+ (SUNXI_MMC_RINT_RESP_ERROR | \
+ SUNXI_MMC_RINT_RESP_CRC_ERROR | \
+ SUNXI_MMC_RINT_DATA_CRC_ERROR | \
+ SUNXI_MMC_RINT_RESP_TIMEOUT | \
+ SUNXI_MMC_RINT_DATA_TIMEOUT | \
+ SUNXI_MMC_RINT_VOLTAGE_CHANGE_DONE | \
+ SUNXI_MMC_RINT_FIFO_RUN_ERROR | \
+ SUNXI_MMC_RINT_HARD_WARE_LOCKED | \
+ SUNXI_MMC_RINT_START_BIT_ERROR | \
+ SUNXI_MMC_RINT_END_BIT_ERROR) /* 0xbfc2 */
+#define SUNXI_MMC_RINT_INTERRUPT_DONE_BIT \
+ (SUNXI_MMC_RINT_AUTO_COMMAND_DONE | \
+ SUNXI_MMC_RINT_DATA_OVER | \
+ SUNXI_MMC_RINT_COMMAND_DONE | \
+ SUNXI_MMC_RINT_VOLTAGE_CHANGE_DONE)
+
+#define SUNXI_MMC_STATUS_RXWL_FLAG (0x1 << 0)
+#define SUNXI_MMC_STATUS_TXWL_FLAG (0x1 << 1)
+#define SUNXI_MMC_STATUS_FIFO_EMPTY (0x1 << 2)
+#define SUNXI_MMC_STATUS_FIFO_FULL (0x1 << 3)
+#define SUNXI_MMC_STATUS_CARD_PRESENT (0x1 << 8)
+#define SUNXI_MMC_STATUS_CARD_DATA_BUSY (0x1 << 9)
+#define SUNXI_MMC_STATUS_DATA_FSM_BUSY (0x1 << 10)
+#define SUNXI_MMC_STATUS_FIFO_LEVEL(reg) (((reg) >> 17) & 0x3fff)
+
+#define SUNXI_MMC_NTSR_MODE_SEL_NEW (0x1 << 31)
+
+#define SUNXI_MMC_IDMAC_RESET (0x1 << 0)
+#define SUNXI_MMC_IDMAC_FIXBURST (0x1 << 1)
+#define SUNXI_MMC_IDMAC_ENABLE (0x1 << 7)
+
+#define SUNXI_MMC_IDIE_TXIRQ (0x1 << 0)
+#define SUNXI_MMC_IDIE_RXIRQ (0x1 << 1)
+
+#define SUNXI_MMC_COMMON_CLK_GATE (1 << 16)
+#define SUNXI_MMC_COMMON_RESET (1 << 18)
+
+#define SUNXI_MMC_CAL_DL_SW_EN (0x1 << 7)
+
+#endif /* _SUNXI_MMC_H */
diff --git a/drivers/mtd/Makefile b/drivers/mtd/Makefile
index c638980..c2fc80b 100644
--- a/drivers/mtd/Makefile
+++ b/drivers/mtd/Makefile
@@ -31,7 +31,7 @@
else
ifneq ($(mtd-y),)
-obj-$(CONFIG_SPL_MTD_SUPPORT) += mtd.o
+obj-$(CONFIG_SPL_MTD) += mtd.o
endif
obj-$(CONFIG_$(SPL_TPL_)NAND_SUPPORT) += nand/
obj-$(CONFIG_SPL_ONENAND_SUPPORT) += onenand/
diff --git a/drivers/mtd/hbmc-am654.c b/drivers/mtd/hbmc-am654.c
index c86e504..8161087 100644
--- a/drivers/mtd/hbmc-am654.c
+++ b/drivers/mtd/hbmc-am654.c
@@ -1,6 +1,6 @@
// SPDX-License-Identifier: GPL-2.0
//
-// Copyright (C) 2019 Texas Instruments Incorporated - http://www.ti.com/
+// Copyright (C) 2019 Texas Instruments Incorporated - https://www.ti.com/
// Author: Vignesh Raghavendra <vigneshr@ti.com>
#include <common.h>
diff --git a/drivers/mtd/nand/raw/Kconfig b/drivers/mtd/nand/raw/Kconfig
index a13e6f5..bb9994b 100644
--- a/drivers/mtd/nand/raw/Kconfig
+++ b/drivers/mtd/nand/raw/Kconfig
@@ -447,6 +447,22 @@
This enables the driver for the NAND flash device found on
PXA3xx processors (NFCv1) and also on Armada 370/XP (NFCv2).
+config NAND_SANDBOX
+ bool "Support for NAND in sandbox"
+ depends on SANDBOX
+ select SYS_NAND_SELF_INIT
+ select SPL_SYS_NAND_SELF_INIT
+ select SPL_NAND_INIT
+ select SYS_NAND_SOFT_ECC
+ select BCH
+ select NAND_ECC_BCH
+ imply CMD_NAND
+ help
+ Enable a dummy NAND driver for sandbox. It simulates any number of
+ arbitrary NAND chips with a RAM buffer. It will also inject errors to
+ test ECC. At the moment, only 8-bit busses and single-chip devices are
+ supported.
+
config NAND_SUNXI
bool "Support for NAND on Allwinner SoCs"
default ARCH_SUNXI
@@ -659,20 +675,13 @@
And fetching device parameters flashed on device, by parsing
ONFI parameter page.
-config SYS_NAND_PAGE_COUNT
- hex "NAND chip page count"
- depends on SPL_NAND_SUPPORT && (NAND_ATMEL || NAND_MXC || \
- SPL_NAND_AM33XX_BCH || SPL_NAND_LOAD || SPL_NAND_SIMPLE || \
- NAND_OMAP_GPMC)
- help
- Number of pages in the NAND chip.
-
config SYS_NAND_PAGE_SIZE
hex "NAND chip page size"
depends on ARCH_SUNXI || NAND_OMAP_GPMC || NAND_LPC32XX_SLC || \
SPL_NAND_SIMPLE || (NAND_MXC && SPL_NAND_SUPPORT) || \
MVEBU_SPL_BOOT_DEVICE_NAND || \
- (NAND_ATMEL && SPL_NAND_SUPPORT) || SPL_GENERATE_ATMEL_PMECC_HEADER
+ (NAND_ATMEL && SPL_NAND_SUPPORT) || \
+ SPL_GENERATE_ATMEL_PMECC_HEADER || NAND_SANDBOX
depends on !NAND_MXS && !NAND_DENALI_DT && !NAND_LPC32XX_MLC && !NAND_MT7621
help
Number of data bytes in one page for the NAND chip on the
diff --git a/drivers/mtd/nand/raw/Makefile b/drivers/mtd/nand/raw/Makefile
index add2b4c..ddbba89 100644
--- a/drivers/mtd/nand/raw/Makefile
+++ b/drivers/mtd/nand/raw/Makefile
@@ -70,6 +70,7 @@
obj-$(CONFIG_TEGRA_NAND) += tegra_nand.o
obj-$(CONFIG_NAND_OMAP_GPMC) += omap_gpmc.o
obj-$(CONFIG_NAND_OMAP_ELM) += omap_elm.o
+obj-$(CONFIG_NAND_SANDBOX) += sand_nand.o
obj-$(CONFIG_NAND_SUNXI) += sunxi_nand.o
obj-$(CONFIG_NAND_MXIC) += mxic_nand.o
obj-$(CONFIG_NAND_ZYNQ) += zynq_nand.o
diff --git a/drivers/mtd/nand/raw/am335x_spl_bch.c b/drivers/mtd/nand/raw/am335x_spl_bch.c
index 6ab3f1f..6831af9 100644
--- a/drivers/mtd/nand/raw/am335x_spl_bch.c
+++ b/drivers/mtd/nand/raw/am335x_spl_bch.c
@@ -11,6 +11,7 @@
#include <common.h>
#include <nand.h>
+#include <system-constants.h>
#include <asm/io.h>
#include <linux/delay.h>
#include <linux/mtd/nand_ecc.h>
@@ -32,7 +33,7 @@
u8 cmd)
{
struct nand_chip *this = mtd_to_nand(mtd);
- int page_addr = page + block * CONFIG_SYS_NAND_PAGE_COUNT;
+ int page_addr = page + block * SYS_NAND_BLOCK_PAGES;
void (*hwctrl)(struct mtd_info *mtd, int cmd,
unsigned int ctrl) = this->cmd_ctrl;
@@ -217,6 +218,11 @@
nand_command(0, 0, 0, NAND_CMD_RESET);
}
+unsigned int nand_page_size(void)
+{
+ return nand_to_mtd(&nand_chip)->writesize;
+}
+
/* Unselect after operation */
void nand_deselect(void)
{
diff --git a/drivers/mtd/nand/raw/atmel/nand-controller.c b/drivers/mtd/nand/raw/atmel/nand-controller.c
index fa962ba..a2151f9 100644
--- a/drivers/mtd/nand/raw/atmel/nand-controller.c
+++ b/drivers/mtd/nand/raw/atmel/nand-controller.c
@@ -64,6 +64,7 @@
#include <linux/mfd/syscon/atmel-smc.h>
#include <linux/mtd/rawnand.h>
#include <linux/mtd/mtd.h>
+#include <linux/time.h>
#include <mach/at91_sfr.h>
#include <nand.h>
#include <regmap.h>
@@ -71,8 +72,6 @@
#include "pmecc.h"
-#define NSEC_PER_SEC 1000000000L
-
#define ATMEL_HSMC_NFC_CFG 0x0
#define ATMEL_HSMC_NFC_CFG_SPARESIZE(x) (((x) / 4) << 24)
#define ATMEL_HSMC_NFC_CFG_SPARESIZE_MASK GENMASK(30, 24)
@@ -352,40 +351,6 @@
return ret;
}
-static void iowrite8_rep(void *addr, const uint8_t *buf, int len)
-{
- int i;
-
- for (i = 0; i < len; i++)
- writeb(buf[i], addr);
-}
-
-static void ioread8_rep(void *addr, uint8_t *buf, int len)
-{
- int i;
-
- for (i = 0; i < len; i++)
- buf[i] = readb(addr);
-}
-
-static void ioread16_rep(void *addr, void *buf, int len)
-{
- int i;
- u16 *p = (u16 *)buf;
-
- for (i = 0; i < len; i++)
- p[i] = readw(addr);
-}
-
-static void iowrite16_rep(void *addr, const void *buf, int len)
-{
- int i;
- u16 *p = (u16 *)buf;
-
- for (i = 0; i < len; i++)
- writew(p[i], addr);
-}
-
static u8 atmel_nand_read_byte(struct mtd_info *mtd)
{
struct nand_chip *chip = mtd_to_nand(mtd);
diff --git a/drivers/mtd/nand/raw/atmel_nand.c b/drivers/mtd/nand/raw/atmel_nand.c
index 6b17e74..6d94e7a 100644
--- a/drivers/mtd/nand/raw/atmel_nand.c
+++ b/drivers/mtd/nand/raw/atmel_nand.c
@@ -12,6 +12,7 @@
#include <common.h>
#include <log.h>
+#include <system-constants.h>
#include <asm/gpio.h>
#include <asm/arch/gpio.h>
#include <dm/device_compat.h>
@@ -1258,7 +1259,7 @@
static int nand_command(int block, int page, uint32_t offs, u8 cmd)
{
struct nand_chip *this = mtd_to_nand(mtd);
- int page_addr = page + block * CONFIG_SYS_NAND_PAGE_COUNT;
+ int page_addr = page + block * SYS_NAND_BLOCK_PAGES;
void (*hwctrl)(struct mtd_info *mtd, int cmd,
unsigned int ctrl) = this->cmd_ctrl;
@@ -1359,7 +1360,7 @@
if (nand_chip.select_chip)
nand_chip.select_chip(mtd, 0);
- page_addr = page + block * CONFIG_SYS_NAND_PAGE_COUNT;
+ page_addr = page + block * SYS_NAND_BLOCK_PAGES;
hwctrl(mtd, NAND_CMD_ERASE1, NAND_CTRL_CLE | NAND_CTRL_CHANGE);
/* Row address */
hwctrl(mtd, (page_addr & 0xff), NAND_CTRL_ALE | NAND_CTRL_CHANGE);
@@ -1451,6 +1452,11 @@
nand_chip.select_chip(mtd, 0);
}
+unsigned int nand_page_size(void)
+{
+ return nand_to_mtd(&nand_chip)->writesize;
+}
+
void nand_deselect(void)
{
if (nand_chip.select_chip)
diff --git a/drivers/mtd/nand/raw/denali_spl.c b/drivers/mtd/nand/raw/denali_spl.c
index 690279c..165a233 100644
--- a/drivers/mtd/nand/raw/denali_spl.c
+++ b/drivers/mtd/nand/raw/denali_spl.c
@@ -234,4 +234,9 @@
return 0;
}
+unsigned int nand_page_size(void)
+{
+ return page_size;
+}
+
void nand_deselect(void) {}
diff --git a/drivers/mtd/nand/raw/fsl_ifc_spl.c b/drivers/mtd/nand/raw/fsl_ifc_spl.c
index c67065e..69d26f1 100644
--- a/drivers/mtd/nand/raw/fsl_ifc_spl.c
+++ b/drivers/mtd/nand/raw/fsl_ifc_spl.c
@@ -106,6 +106,8 @@
return __raw_readw((u16 *)marker) != 0xffff;
}
+static int saved_page_size;
+
int nand_spl_load_image(uint32_t offs, unsigned int uboot_size, void *vdst)
{
struct fsl_ifc_fcm *gregs = (void *)CFG_SYS_IFC_ADDR;
@@ -150,6 +152,7 @@
if (port_size == 8)
bad_marker = 5;
}
+ saved_page_size = page_size;
ver = ifc_in32(&gregs->ifc_rev);
if (ver >= FSL_IFC_V2_0_0)
@@ -300,6 +303,11 @@
#ifndef CONFIG_TPL_NAND_INIT
void nand_init(void)
{
+}
+
+unsigned int nand_page_size(void)
+{
+ return saved_page_size;
}
void nand_deselect(void)
diff --git a/drivers/mtd/nand/raw/lpc32xx_nand_mlc.c b/drivers/mtd/nand/raw/lpc32xx_nand_mlc.c
index ac2e669..f8ae216 100644
--- a/drivers/mtd/nand/raw/lpc32xx_nand_mlc.c
+++ b/drivers/mtd/nand/raw/lpc32xx_nand_mlc.c
@@ -765,4 +765,9 @@
return 0;
}
+unsigned int nand_page_size(void)
+{
+ return BYTES_PER_PAGE;
+}
+
#endif /* CONFIG_SPL_BUILD */
diff --git a/drivers/mtd/nand/raw/mt7621_nand_spl.c b/drivers/mtd/nand/raw/mt7621_nand_spl.c
index 114fc8b..a2be9ba 100644
--- a/drivers/mtd/nand/raw/mt7621_nand_spl.c
+++ b/drivers/mtd/nand/raw/mt7621_nand_spl.c
@@ -203,6 +203,11 @@
return SZ_2G;
}
+unsigned int nand_page_size(void)
+{
+ return nfc_dev.nand.mtd.writesize;
+}
+
void nand_deselect(void)
{
}
diff --git a/drivers/mtd/nand/raw/mxc_nand_spl.c b/drivers/mtd/nand/raw/mxc_nand_spl.c
index 309e75d..a855c99 100644
--- a/drivers/mtd/nand/raw/mxc_nand_spl.c
+++ b/drivers/mtd/nand/raw/mxc_nand_spl.c
@@ -13,6 +13,7 @@
#include <common.h>
#include <hang.h>
#include <nand.h>
+#include <system-constants.h>
#include <linux/mtd/rawnand.h>
#include <asm/arch/imx-regs.h>
#include <asm/io.h>
@@ -304,13 +305,13 @@
* Check if we have crossed a block boundary, and if so
* check for bad block.
*/
- if (!(page % CONFIG_SYS_NAND_PAGE_COUNT)) {
+ if (!(page % SYS_NAND_BLOCK_PAGES)) {
/*
* Yes, new block. See if this block is good. If not,
* loop until we find a good block.
*/
while (is_badblock(page)) {
- page = page + CONFIG_SYS_NAND_PAGE_COUNT;
+ page = page + SYS_NAND_BLOCK_PAGES;
/* Check i we've reached the end of flash. */
if (page >= maxpages)
return -1;
@@ -350,3 +351,8 @@
void nand_init(void) {}
void nand_deselect(void) {}
+
+unsigned int nand_page_size(void)
+{
+ return CONFIG_SYS_NAND_PAGE_SIZE;
+}
diff --git a/drivers/mtd/nand/raw/mxs_nand.c b/drivers/mtd/nand/raw/mxs_nand.c
index 65eab4c8..fd65772 100644
--- a/drivers/mtd/nand/raw/mxs_nand.c
+++ b/drivers/mtd/nand/raw/mxs_nand.c
@@ -31,6 +31,7 @@
#include <linux/errno.h>
#include <linux/mtd/rawnand.h>
#include <linux/sizes.h>
+#include <linux/time.h>
#include <linux/types.h>
#include <linux/math64.h>
@@ -52,8 +53,6 @@
#endif
#define MXS_NAND_BCH_TIMEOUT 10000
-#define USEC_PER_SEC 1000000
-#define NSEC_PER_SEC 1000000000L
#define TO_CYCLES(duration, period) DIV_ROUND_UP_ULL(duration, period)
diff --git a/drivers/mtd/nand/raw/mxs_nand_spl.c b/drivers/mtd/nand/raw/mxs_nand_spl.c
index 3006629..f7d3f02 100644
--- a/drivers/mtd/nand/raw/mxs_nand_spl.c
+++ b/drivers/mtd/nand/raw/mxs_nand_spl.c
@@ -295,6 +295,11 @@
return 0;
}
+unsigned int nand_page_size(void)
+{
+ return nand_to_mtd(&nand_chip)->writesize;
+}
+
void nand_deselect(void)
{
}
diff --git a/drivers/mtd/nand/raw/nand.c b/drivers/mtd/nand/raw/nand.c
index eacd99c..4c18861 100644
--- a/drivers/mtd/nand/raw/nand.c
+++ b/drivers/mtd/nand/raw/nand.c
@@ -60,13 +60,11 @@
sprintf(dev_name[devnum], "nand%d", devnum);
mtd->name = dev_name[devnum];
-#ifdef CONFIG_MTD
/*
* Add MTD device so that we can reference it later
* via the mtdcore infrastructure (e.g. ubi).
*/
add_mtd_device(mtd);
-#endif
total_nand_size += mtd->size / 1024;
@@ -76,6 +74,23 @@
return 0;
}
+void nand_unregister(struct mtd_info *mtd)
+{
+ int devnum = nand_mtd_to_devnum(mtd);
+
+ if (devnum < 0)
+ return;
+
+ if (nand_curr_device == devnum)
+ nand_curr_device = -1;
+
+ total_nand_size -= mtd->size / 1024;
+
+ del_mtd_device(nand_info[devnum]);
+
+ nand_info[devnum] = NULL;
+}
+
#if !CONFIG_IS_ENABLED(SYS_NAND_SELF_INIT)
static void nand_init_chip(int i)
{
@@ -100,6 +115,8 @@
#endif
#ifdef CONFIG_MTD_CONCAT
+struct mtd_info *concat_mtd;
+
static void create_mtd_concat(void)
{
struct mtd_info *nand_info_list[CONFIG_SYS_MAX_NAND_DEVICE];
@@ -114,28 +131,40 @@
}
}
if (nand_devices_found > 1) {
- struct mtd_info *mtd;
char c_mtd_name[16];
/*
* We detected multiple devices. Concatenate them together.
*/
sprintf(c_mtd_name, "nand%d", nand_devices_found);
- mtd = mtd_concat_create(nand_info_list, nand_devices_found,
- c_mtd_name);
+ concat_mtd = mtd_concat_create(nand_info_list,
+ nand_devices_found, c_mtd_name);
- if (mtd == NULL)
+ if (!concat_mtd)
return;
- nand_register(nand_devices_found, mtd);
+ nand_register(nand_devices_found, concat_mtd);
}
return;
}
+
+static void destroy_mtd_concat(void)
+{
+ if (!concat_mtd)
+ return;
+
+ mtd_concat_destroy(concat_mtd);
+ concat_mtd = NULL;
+}
#else
static void create_mtd_concat(void)
{
}
+
+static void destroy_mtd_concat(void)
+{
+}
#endif
unsigned long nand_size(void)
@@ -143,10 +172,10 @@
return total_nand_size;
}
+static int initialized;
+
void nand_init(void)
{
- static int initialized;
-
/*
* Avoid initializing NAND Flash multiple times,
* otherwise it will calculate a wrong total size.
@@ -174,3 +203,22 @@
create_mtd_concat();
}
+
+void nand_reinit(void)
+{
+ int i;
+
+ destroy_mtd_concat();
+ for (i = 0; i < CONFIG_SYS_MAX_NAND_DEVICE; i++)
+ assert(!nand_info[i]);
+
+ initialized = 0;
+ nand_init();
+}
+
+unsigned int nand_page_size(void)
+{
+ struct mtd_info *mtd = get_nand_dev_by_index(nand_curr_device);
+
+ return mtd ? mtd->writesize : 1;
+}
diff --git a/drivers/mtd/nand/raw/nand_base.c b/drivers/mtd/nand/raw/nand_base.c
index 6b4adcf..c40a0f2 100644
--- a/drivers/mtd/nand/raw/nand_base.c
+++ b/drivers/mtd/nand/raw/nand_base.c
@@ -245,39 +245,6 @@
chip->write_buf(mtd, (uint8_t *)&word, 2);
}
-static void iowrite8_rep(void *addr, const uint8_t *buf, int len)
-{
- int i;
-
- for (i = 0; i < len; i++)
- writeb(buf[i], addr);
-}
-static void ioread8_rep(void *addr, uint8_t *buf, int len)
-{
- int i;
-
- for (i = 0; i < len; i++)
- buf[i] = readb(addr);
-}
-
-static void ioread16_rep(void *addr, void *buf, int len)
-{
- int i;
- u16 *p = (u16 *) buf;
-
- for (i = 0; i < len; i++)
- p[i] = readw(addr);
-}
-
-static void iowrite16_rep(void *addr, void *buf, int len)
-{
- int i;
- u16 *p = (u16 *) buf;
-
- for (i = 0; i < len; i++)
- writew(p[i], addr);
-}
-
/**
* nand_write_buf - [DEFAULT] write buffer to chip
* @mtd: MTD device structure
@@ -4462,17 +4429,14 @@
else if (chip->jedec_version)
pr_info("%s %s\n", manufacturer_desc->name,
chip->jedec_params.model);
- else
+ else if (manufacturer_desc)
pr_info("%s %s\n", manufacturer_desc->name, type->name);
#else
if (chip->jedec_version)
pr_info("%s %s\n", manufacturer_desc->name,
chip->jedec_params.model);
- else
+ else if (manufacturer_desc)
pr_info("%s %s\n", manufacturer_desc->name, type->name);
-
- pr_info("%s %s\n", manufacturer_desc->name,
- type->name);
#endif
pr_info("%d MiB, %s, erase size: %d KiB, page size: %d, OOB size: %d\n",
diff --git a/drivers/mtd/nand/raw/nand_spl_loaders.c b/drivers/mtd/nand/raw/nand_spl_loaders.c
index 156b44d..db4213e 100644
--- a/drivers/mtd/nand/raw/nand_spl_loaders.c
+++ b/drivers/mtd/nand/raw/nand_spl_loaders.c
@@ -12,8 +12,11 @@
while (block <= lastblock) {
if (!nand_is_bad_block(block)) {
/* Skip bad blocks */
- while (page < CONFIG_SYS_NAND_PAGE_COUNT) {
+ while (size && page < SYS_NAND_BLOCK_PAGES) {
nand_read_page(block, page, dst);
+
+ size -= min(size, CONFIG_SYS_NAND_PAGE_SIZE -
+ page_offset);
/*
* When offs is not aligned to page address the
* extra offset is copied to dst as well. Copy
diff --git a/drivers/mtd/nand/raw/nand_spl_simple.c b/drivers/mtd/nand/raw/nand_spl_simple.c
index 2f3af9e..80d6e0e 100644
--- a/drivers/mtd/nand/raw/nand_spl_simple.c
+++ b/drivers/mtd/nand/raw/nand_spl_simple.c
@@ -6,6 +6,7 @@
#include <common.h>
#include <nand.h>
+#include <system-constants.h>
#include <asm/io.h>
#include <linux/mtd/nand_ecc.h>
#include <linux/mtd/rawnand.h>
@@ -27,7 +28,7 @@
u8 cmd)
{
struct nand_chip *this = mtd_to_nand(mtd);
- int page_addr = page + block * CONFIG_SYS_NAND_PAGE_COUNT;
+ int page_addr = page + block * SYS_NAND_BLOCK_PAGES;
while (!this->dev_ready(mtd))
;
@@ -59,7 +60,7 @@
u8 cmd)
{
struct nand_chip *this = mtd_to_nand(mtd);
- int page_addr = page + block * CONFIG_SYS_NAND_PAGE_COUNT;
+ int page_addr = page + block * SYS_NAND_BLOCK_PAGES;
void (*hwctrl)(struct mtd_info *mtd, int cmd,
unsigned int ctrl) = this->cmd_ctrl;
@@ -226,6 +227,11 @@
nand_chip.select_chip(mtd, 0);
}
+unsigned int nand_page_size(void)
+{
+ return nand_to_mtd(&nand_chip)->writesize;
+}
+
/* Unselect after operation */
void nand_deselect(void)
{
diff --git a/drivers/mtd/nand/raw/octeontx_nand.c b/drivers/mtd/nand/raw/octeontx_nand.c
index 65a03d2..3b20685 100644
--- a/drivers/mtd/nand/raw/octeontx_nand.c
+++ b/drivers/mtd/nand/raw/octeontx_nand.c
@@ -24,6 +24,7 @@
#include <linux/mtd/nand_bch.h>
#include <linux/mtd/nand_ecc.h>
#include <linux/mtd/rawnand.h>
+#include <linux/time.h>
#include <asm/global_data.h>
#include <asm/io.h>
#include <asm/types.h>
@@ -291,7 +292,6 @@
#define OCTEONTX_NAND_DRIVER_NAME "octeontx_nand"
#define NDF_TIMEOUT 1000 /** Timeout in ms */
-#define USEC_PER_SEC 1000000 /** Linux compatibility */
#ifndef NAND_MAX_CHIPS
# define NAND_MAX_CHIPS 8 /** Linux compatibility */
#endif
diff --git a/drivers/mtd/nand/raw/omap_gpmc.c b/drivers/mtd/nand/raw/omap_gpmc.c
index 1a5ed0d..0e25bd5 100644
--- a/drivers/mtd/nand/raw/omap_gpmc.c
+++ b/drivers/mtd/nand/raw/omap_gpmc.c
@@ -6,6 +6,7 @@
#include <common.h>
#include <log.h>
+#include <system-constants.h>
#include <asm/io.h>
#include <dm/uclass.h>
#include <linux/errno.h>
@@ -1298,7 +1299,7 @@
static int nand_read_page(int block, int page, uchar *dst)
{
- int page_addr = block * CONFIG_SYS_NAND_PAGE_COUNT + page;
+ int page_addr = block * SYS_NAND_BLOCK_PAGES + page;
loff_t ofs = page_addr * CONFIG_SYS_NAND_PAGE_SIZE;
int ret;
size_t len = CONFIG_SYS_NAND_PAGE_SIZE;
diff --git a/drivers/mtd/nand/raw/sand_nand.c b/drivers/mtd/nand/raw/sand_nand.c
new file mode 100644
index 0000000..229d7b5
--- /dev/null
+++ b/drivers/mtd/nand/raw/sand_nand.c
@@ -0,0 +1,707 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) Sean Anderson <seanga2@gmail.com>
+ */
+
+#define LOG_CATEGORY UCLASS_MTD
+#include <errno.h>
+#include <hexdump.h>
+#include <log.h>
+#include <nand.h>
+#include <os.h>
+#include <rand.h>
+#include <spl.h>
+#include <system-constants.h>
+#include <dm/device_compat.h>
+#include <dm/read.h>
+#include <dm/uclass.h>
+#include <asm/bitops.h>
+#include <linux/bitmap.h>
+#include <linux/mtd/rawnand.h>
+#include <linux/sizes.h>
+
+enum sand_nand_state {
+ STATE_READY,
+ STATE_IDLE,
+ STATE_READ,
+ STATE_READ_ID,
+ STATE_READ_ONFI,
+ STATE_PARAM_ONFI,
+ STATE_STATUS,
+ STATE_PROG,
+ STATE_ERASE,
+};
+
+static const char *const state_name[] = {
+ [STATE_READY] = "READY",
+ [STATE_IDLE] = "IDLE",
+ [STATE_READ] = "READ",
+ [STATE_READ_ID] = "READ_ID",
+ [STATE_READ_ONFI] = "READ_ONFI",
+ [STATE_PARAM_ONFI] = "PARAM_ONFI",
+ [STATE_STATUS] = "STATUS",
+ [STATE_PROG] = "PROG",
+ [STATE_ERASE] = "ERASE",
+};
+
+/**
+ * struct sand_nand_chip - Per-device private data
+ * @nand: The nand chip
+ * @node: The next device in this controller
+ * @programmed: Bitmap of whether sectors are programmed
+ * @id: ID to report for NAND_CMD_READID
+ * @id_len: Length of @id
+ * @onfi: Three copies of ONFI parameter page
+ * @status: Status to report for NAND_CMD_STATUS
+ * @chunksize: Size of one "chunk" (page + oob) in bytes
+ * @pageize: Size of one page in bytes
+ * @pages: Total number of pages
+ * @pages_per_erase: Number of pages per eraseblock
+ * @err_count: Number of errors to inject per @err_step_bits of data
+ * @err_step_bits: Number of data bits per error "step"
+ * @err_steps: Number of err steps in a page
+ * @cs: Chip select for this device
+ * @state: Current state of the device
+ * @column: Column of the most-recent command
+ * @page_addr: Page address of the most-recent command
+ * @fd: File descriptor for the backing data
+ * @fd_page_addr: Page address that @fd is seek'd to
+ * @selected: Whether this device is selected
+ * @tmp: "Cache" buffer used to store transferred data before committing it
+ * @tmp_dirty: Whether @tmp is dirty (modified) or clean (all ones)
+ *
+ * Data is stored with the OOB area in-line. For example, with 512-byte pages
+ * and and 16-byte OOB areas, the first page would start at offset 0, the second
+ * at offset 528, the third at offset 1056, and so on
+ */
+struct sand_nand_chip {
+ struct nand_chip nand;
+ struct list_head node;
+ long *programmed;
+ const u8 *id;
+ u32 chunksize, pagesize, pages, pages_per_erase;
+ u32 err_count, err_step_bits, err_steps, ecc_bits;
+ unsigned int cs;
+ enum sand_nand_state state;
+ int column, page_addr, fd, fd_page_addr;
+ bool selected, tmp_dirty;
+ u8 status;
+ u8 id_len;
+ u8 tmp[NAND_MAX_PAGESIZE + NAND_MAX_OOBSIZE];
+ u8 onfi[sizeof(struct nand_onfi_params) * 3];
+};
+
+#define SAND_DEBUG(chip, fmt, ...) \
+ dev_dbg((chip)->nand.mtd.dev, "%u (%s): " fmt, (chip)->cs, \
+ state_name[(chip)->state], ##__VA_ARGS__)
+
+static inline void to_state(struct sand_nand_chip *chip,
+ enum sand_nand_state new_state)
+{
+ if (new_state != chip->state)
+ SAND_DEBUG(chip, "to state %s\n", state_name[new_state]);
+ chip->state = new_state;
+}
+
+static inline struct sand_nand_chip *to_sand_nand(struct nand_chip *nand)
+{
+ return container_of(nand, struct sand_nand_chip, nand);
+}
+
+struct sand_nand_priv {
+ struct list_head chips;
+};
+
+static int sand_nand_dev_ready(struct mtd_info *mtd)
+{
+ return 1;
+}
+
+static int sand_nand_wait(struct mtd_info *mtd, struct nand_chip *chip)
+{
+ u8 status;
+
+ return nand_status_op(chip, &status) ?: status;
+}
+
+static int sand_nand_seek(struct sand_nand_chip *chip)
+{
+ if (chip->fd_page_addr == chip->page_addr)
+ return 0;
+
+ if (os_lseek(chip->fd, (off_t)chip->page_addr * chip->chunksize,
+ OS_SEEK_SET) < 0) {
+ SAND_DEBUG(chip, "could not seek: %d\n", errno);
+ return -EIO;
+ }
+
+ chip->fd_page_addr = chip->page_addr;
+ return 0;
+}
+
+static void sand_nand_inject_error(struct sand_nand_chip *chip,
+ unsigned int step, unsigned int pos)
+{
+ int byte, index;
+
+ if (pos < chip->err_step_bits) {
+ __change_bit(step * chip->err_step_bits + pos, chip->tmp);
+ return;
+ }
+
+ /*
+ * Only ECC bytes are covered in the OOB area, so
+ * pretend that those are the only bytes which can have
+ * errors.
+ */
+ byte = (pos - chip->err_step_bits + step * chip->ecc_bits) / 8;
+ index = chip->nand.ecc.layout->eccpos[byte];
+ /* Avoid endianness issues by working with bytes */
+ chip->tmp[chip->pagesize + index] ^= BIT(pos & 0x7);
+}
+
+static int sand_nand_read(struct sand_nand_chip *chip)
+{
+ unsigned int i, stop = 0;
+
+ if (chip->column == chip->pagesize)
+ stop = chip->err_step_bits;
+
+ if (test_bit(chip->page_addr, chip->programmed)) {
+ if (sand_nand_seek(chip))
+ return -EIO;
+
+ if (os_read(chip->fd, chip->tmp, chip->chunksize) !=
+ chip->chunksize) {
+ SAND_DEBUG(chip, "could not read: %d\n", errno);
+ return -EIO;
+ }
+ chip->fd_page_addr++;
+ } else if (chip->tmp_dirty) {
+ memset(chip->tmp + chip->column, 0xff,
+ chip->chunksize - chip->column);
+ }
+
+ /*
+ * Inject some errors; this is Method A from "An Efficient Algorithm for
+ * Sequential Random Sampling" (Vitter 87). This is still slow when
+ * generating a lot (dozens) of ECC errors.
+ *
+ * To avoid generating too many errors in any one ECC step, we separate
+ * our error generation by ECC step.
+ */
+ chip->tmp_dirty = true;
+ for (i = 0; i < chip->err_steps; i++) {
+ u32 bit_errors = chip->err_count;
+ unsigned int j = chip->err_step_bits + chip->ecc_bits;
+
+ while (bit_errors) {
+ unsigned int u = rand();
+ float quot = 1ULL << 32;
+
+ do {
+ quot *= j - bit_errors;
+ quot /= j;
+ j--;
+
+ if (j < stop)
+ goto next;
+ } while (u < quot);
+
+ sand_nand_inject_error(chip, i, j);
+ bit_errors--;
+ }
+next:
+ ;
+ }
+
+ return 0;
+}
+
+static void sand_nand_command(struct mtd_info *mtd, unsigned int command,
+ int column, int page_addr)
+{
+ struct nand_chip *nand = mtd_to_nand(mtd);
+ struct sand_nand_chip *chip = to_sand_nand(nand);
+ enum sand_nand_state new_state = chip->state;
+
+ SAND_DEBUG(chip, "command=%02x column=%d page_addr=%d\n", command,
+ column, page_addr);
+
+ if (!chip->selected)
+ return;
+
+ switch (chip->state) {
+ case STATE_READY:
+ if (command == NAND_CMD_RESET)
+ goto reset;
+ break;
+ case STATE_PROG:
+ new_state = STATE_IDLE;
+ if (command != NAND_CMD_PAGEPROG ||
+ test_and_set_bit(chip->page_addr, chip->programmed)) {
+ chip->status |= NAND_STATUS_FAIL;
+ break;
+ }
+
+ if (sand_nand_seek(chip)) {
+ chip->status |= NAND_STATUS_FAIL;
+ break;
+ }
+
+ if (os_write(chip->fd, chip->tmp, chip->chunksize) !=
+ chip->chunksize) {
+ SAND_DEBUG(chip, "could not write: %d\n", errno);
+ chip->status |= NAND_STATUS_FAIL;
+ break;
+ }
+
+ chip->fd_page_addr++;
+ break;
+ case STATE_ERASE:
+ new_state = STATE_IDLE;
+ if (command != NAND_CMD_ERASE2) {
+ chip->status |= NAND_STATUS_FAIL;
+ break;
+ }
+
+ if (chip->page_addr < 0 ||
+ chip->page_addr >= chip->pages ||
+ chip->page_addr % chip->pages_per_erase)
+ chip->status |= NAND_STATUS_FAIL;
+ else
+ bitmap_clear(chip->programmed, chip->page_addr,
+ chip->pages_per_erase);
+ break;
+ default:
+ chip->column = column;
+ chip->page_addr = page_addr;
+ switch (command) {
+ case NAND_CMD_READOOB:
+ if (column >= 0)
+ chip->column += chip->pagesize;
+ fallthrough;
+ case NAND_CMD_READ0:
+ new_state = STATE_IDLE;
+ if (page_addr < 0 || page_addr >= chip->pages)
+ break;
+
+ if (chip->column < 0 || chip->column >= chip->chunksize)
+ break;
+
+ if (sand_nand_read(chip))
+ break;
+
+ chip->page_addr = page_addr;
+ new_state = STATE_READ;
+ break;
+ case NAND_CMD_ERASE1:
+ new_state = STATE_ERASE;
+ chip->status = ~NAND_STATUS_FAIL;
+ break;
+ case NAND_CMD_STATUS:
+ new_state = STATE_STATUS;
+ chip->column = 0;
+ break;
+ case NAND_CMD_SEQIN:
+ new_state = STATE_PROG;
+ chip->status = ~NAND_STATUS_FAIL;
+ if (page_addr < 0 || page_addr >= chip->pages ||
+ chip->column < 0 ||
+ chip->column >= chip->chunksize) {
+ chip->status |= NAND_STATUS_FAIL;
+ } else if (chip->tmp_dirty) {
+ memset(chip->tmp, 0xff, chip->chunksize);
+ chip->tmp_dirty = false;
+ }
+ break;
+ case NAND_CMD_READID:
+ if (chip->onfi[0] && column == 0x20)
+ new_state = STATE_READ_ONFI;
+ else
+ new_state = STATE_READ_ID;
+ chip->column = 0;
+ break;
+ case NAND_CMD_PARAM:
+ if (chip->onfi[0] && !column)
+ new_state = STATE_PARAM_ONFI;
+ else
+ new_state = STATE_IDLE;
+ break;
+ case NAND_CMD_RESET:
+reset:
+ new_state = STATE_IDLE;
+ chip->column = -1;
+ chip->page_addr = -1;
+ chip->status = ~NAND_STATUS_FAIL;
+ break;
+ default:
+ new_state = STATE_IDLE;
+ SAND_DEBUG(chip, "Unsupported command %02x\n", command);
+ }
+ }
+
+ to_state(chip, new_state);
+}
+
+static void sand_nand_select_chip(struct mtd_info *mtd, int n)
+{
+ struct nand_chip *nand = mtd_to_nand(mtd);
+ struct sand_nand_chip *chip = to_sand_nand(nand);
+
+ chip->selected = !n;
+}
+
+static void sand_nand_read_buf(struct mtd_info *mtd, u8 *buf, int len)
+{
+ struct nand_chip *nand = mtd_to_nand(mtd);
+ struct sand_nand_chip *chip = to_sand_nand(nand);
+ unsigned int to_copy;
+ int src_len = 0;
+ const u8 *src = NULL;
+
+ if (!chip->selected)
+ goto copy;
+
+ switch (chip->state) {
+ case STATE_READ:
+ src = chip->tmp;
+ src_len = chip->chunksize;
+ break;
+ case STATE_READ_ID:
+ src = chip->id;
+ src_len = chip->id_len;
+ break;
+ case STATE_READ_ONFI:
+ src = "ONFI";
+ src_len = 4;
+ break;
+ case STATE_PARAM_ONFI:
+ src = chip->onfi;
+ src_len = sizeof(chip->onfi);
+ break;
+ case STATE_STATUS:
+ src = &chip->status;
+ src_len = 1;
+ break;
+ default:
+ break;
+ }
+
+copy:
+ if (chip->column >= 0)
+ to_copy = max(min(len, src_len - chip->column), 0);
+ else
+ to_copy = 0;
+ memcpy(buf, src + chip->column, to_copy);
+ memset(buf + to_copy, 0xff, len - to_copy);
+ chip->column += to_copy;
+
+ if (len == 1) {
+ SAND_DEBUG(chip, "read [ %02x ]\n", buf[0]);
+ } else if (src_len) {
+ SAND_DEBUG(chip, "read %d bytes\n", len);
+#ifdef VERBOSE_DEBUG
+ print_hex_dump_bytes("", DUMP_PREFIX_OFFSET, buf, len);
+#endif
+ }
+
+ if (src_len && chip->column == src_len)
+ to_state(chip, STATE_IDLE);
+}
+
+static u8 sand_nand_read_byte(struct mtd_info *mtd)
+{
+ u8 ret;
+
+ sand_nand_read_buf(mtd, &ret, 1);
+ return ret;
+}
+
+static u16 sand_nand_read_word(struct mtd_info *mtd)
+{
+ struct nand_chip *nand = mtd_to_nand(mtd);
+ struct sand_nand_chip *chip = to_sand_nand(nand);
+
+ SAND_DEBUG(chip, "16-bit access unsupported\n");
+ return sand_nand_read_byte(mtd) | 0xff00;
+}
+
+static void sand_nand_write_buf(struct mtd_info *mtd, const u8 *buf, int len)
+{
+ struct nand_chip *nand = mtd_to_nand(mtd);
+ struct sand_nand_chip *chip = to_sand_nand(nand);
+
+ SAND_DEBUG(chip, "write %d bytes\n", len);
+#ifdef VERBOSE_DEBUG
+ print_hex_dump_bytes("", DUMP_PREFIX_OFFSET, buf, len);
+#endif
+
+ if (chip->state != STATE_PROG || chip->status & NAND_STATUS_FAIL)
+ return;
+
+ chip->tmp_dirty = true;
+ len = min((unsigned int)len, chip->chunksize - chip->column);
+ memcpy(chip->tmp + chip->column, buf, len);
+ chip->column += len;
+}
+
+static struct nand_chip *nand_chip;
+
+int sand_nand_remove(struct udevice *dev)
+{
+ struct sand_nand_priv *priv = dev_get_priv(dev);
+ struct sand_nand_chip *chip;
+
+ list_for_each_entry(chip, &priv->chips, node) {
+ struct nand_chip *nand = &chip->nand;
+
+ if (nand_chip == nand)
+ nand_chip = NULL;
+
+ nand_unregister(nand_to_mtd(nand));
+ free(chip->programmed);
+ os_close(chip->fd);
+ free(chip);
+ }
+
+ return 0;
+}
+
+static int sand_nand_probe(struct udevice *dev)
+{
+ struct sand_nand_priv *priv = dev_get_priv(dev);
+ struct sand_nand_chip *chip;
+ int ret, devnum = 0;
+ ofnode np;
+
+ INIT_LIST_HEAD(&priv->chips);
+
+ dev_for_each_subnode(np, dev) {
+ struct nand_chip *nand;
+ struct mtd_info *mtd;
+ u32 erasesize, oobsize, pagesize, pages;
+ u32 err_count, err_step_size;
+ off_t expected_size;
+ char filename[30];
+ fdt_addr_t cs;
+ const u8 *id, *onfi;
+ int id_len, onfi_len;
+
+ cs = ofnode_get_addr_size_index_notrans(np, 0, NULL);
+ if (cs == FDT_ADDR_T_NONE) {
+ dev_dbg(dev, "Invalid cs for chip %s\n",
+ ofnode_get_name(np));
+ ret = -ENOENT;
+ goto err;
+ }
+
+ id = ofnode_read_prop(np, "sandbox,id", &id_len);
+ if (!id) {
+ dev_dbg(dev, "No sandbox,id property for chip %s\n",
+ ofnode_get_name(np));
+ ret = -EINVAL;
+ goto err;
+ }
+
+ onfi = ofnode_read_prop(np, "sandbox,onfi", &onfi_len);
+ if (onfi && onfi_len != sizeof(struct nand_onfi_params)) {
+ dev_dbg(dev, "Invalid length %d for onfi params\n",
+ onfi_len);
+ ret = -EINVAL;
+ goto err;
+ }
+
+ ret = ofnode_read_u32(np, "sandbox,erasesize", &erasesize);
+ if (ret) {
+ dev_dbg(dev, "No sandbox,erasesize property for chip %s",
+ ofnode_get_name(np));
+ goto err;
+ }
+
+ ret = ofnode_read_u32(np, "sandbox,oobsize", &oobsize);
+ if (ret) {
+ dev_dbg(dev, "No sandbox,oobsize property for chip %s",
+ ofnode_get_name(np));
+ goto err;
+ }
+
+ ret = ofnode_read_u32(np, "sandbox,pagesize", &pagesize);
+ if (ret) {
+ dev_dbg(dev, "No sandbox,pagesize property for chip %s",
+ ofnode_get_name(np));
+ goto err;
+ }
+
+ ret = ofnode_read_u32(np, "sandbox,pages", &pages);
+ if (ret) {
+ dev_dbg(dev, "No sandbox,pages property for chip %s",
+ ofnode_get_name(np));
+ goto err;
+ }
+
+ ret = ofnode_read_u32(np, "sandbox,err-count", &err_count);
+ if (ret) {
+ dev_dbg(dev,
+ "No sandbox,err-count property for chip %s",
+ ofnode_get_name(np));
+ goto err;
+ }
+
+ ret = ofnode_read_u32(np, "sandbox,err-step-size",
+ &err_step_size);
+ if (ret) {
+ dev_dbg(dev,
+ "No sandbox,err-step-size property for chip %s",
+ ofnode_get_name(np));
+ goto err;
+ }
+
+ chip = calloc(sizeof(*chip), 1);
+ if (!chip) {
+ ret = -ENOMEM;
+ goto err;
+ }
+
+ chip->cs = cs;
+ chip->id = id;
+ chip->id_len = id_len;
+ chip->chunksize = pagesize + oobsize;
+ chip->pagesize = pagesize;
+ chip->pages = pages;
+ chip->pages_per_erase = erasesize / pagesize;
+ memset(chip->tmp, 0xff, chip->chunksize);
+
+ chip->err_count = err_count;
+ chip->err_step_bits = err_step_size * 8;
+ chip->err_steps = pagesize / err_step_size;
+
+ expected_size = (off_t)pages * chip->chunksize;
+ snprintf(filename, sizeof(filename),
+ "/tmp/u-boot.nand%d.XXXXXX", devnum);
+ chip->fd = os_mktemp(filename, expected_size);
+ if (chip->fd < 0) {
+ dev_dbg(dev, "Could not create temp file %s\n",
+ filename);
+ ret = chip->fd;
+ goto err_chip;
+ }
+
+ chip->programmed = calloc(sizeof(long),
+ BITS_TO_LONGS(pages));
+ if (!chip->programmed) {
+ ret = -ENOMEM;
+ goto err_fd;
+ }
+
+ if (onfi) {
+ memcpy(chip->onfi, onfi, onfi_len);
+ memcpy(chip->onfi + onfi_len, onfi, onfi_len);
+ memcpy(chip->onfi + 2 * onfi_len, onfi, onfi_len);
+ }
+
+ nand = &chip->nand;
+ nand->options = spl_in_proper() ? 0 : NAND_SKIP_BBTSCAN;
+ nand->flash_node = np;
+ nand->dev_ready = sand_nand_dev_ready;
+ nand->cmdfunc = sand_nand_command;
+ nand->waitfunc = sand_nand_wait;
+ nand->select_chip = sand_nand_select_chip;
+ nand->read_byte = sand_nand_read_byte;
+ nand->read_word = sand_nand_read_word;
+ nand->read_buf = sand_nand_read_buf;
+ nand->write_buf = sand_nand_write_buf;
+ nand->ecc.options = NAND_ECC_GENERIC_ERASED_CHECK;
+
+ mtd = nand_to_mtd(nand);
+ mtd->dev = dev;
+
+ ret = nand_scan(mtd, CONFIG_SYS_NAND_MAX_CHIPS);
+ if (ret) {
+ dev_dbg(dev, "Could not scan chip %s: %d\n",
+ ofnode_get_name(np), ret);
+ goto err_prog;
+ }
+ chip->ecc_bits = nand->ecc.layout->eccbytes * 8 /
+ chip->err_steps;
+
+ ret = nand_register(devnum, mtd);
+ if (ret) {
+ dev_dbg(dev, "Could not register nand %d: %d\n", devnum,
+ ret);
+ goto err_prog;
+ }
+
+ if (!nand_chip)
+ nand_chip = nand;
+
+ list_add_tail(&chip->node, &priv->chips);
+ devnum++;
+ continue;
+
+err_prog:
+ free(chip->programmed);
+err_fd:
+ os_close(chip->fd);
+err_chip:
+ free(chip);
+ goto err;
+ }
+
+ return 0;
+
+err:
+ sand_nand_remove(dev);
+ return ret;
+}
+
+static const struct udevice_id sand_nand_ids[] = {
+ { .compatible = "sandbox,nand" },
+ { }
+};
+
+U_BOOT_DRIVER(sand_nand) = {
+ .name = "sand-nand",
+ .id = UCLASS_MTD,
+ .of_match = sand_nand_ids,
+ .probe = sand_nand_probe,
+ .remove = sand_nand_remove,
+ .priv_auto = sizeof(struct sand_nand_priv),
+};
+
+void board_nand_init(void)
+{
+ struct udevice *dev;
+ int err;
+
+ err = uclass_get_device_by_driver(UCLASS_MTD, DM_DRIVER_REF(sand_nand),
+ &dev);
+ if (err && err != -ENODEV)
+ log_info("Failed to get sandbox NAND: %d\n", err);
+}
+
+#if IS_ENABLED(CONFIG_SPL_BUILD) && IS_ENABLED(CONFIG_SPL_NAND_INIT)
+void nand_deselect(void)
+{
+ nand_chip->select_chip(nand_to_mtd(nand_chip), -1);
+}
+
+static int nand_is_bad_block(int block)
+{
+ struct mtd_info *mtd = nand_to_mtd(nand_chip);
+
+ return mtd_block_isbad(mtd, block << mtd->erasesize_shift);
+}
+
+static int nand_read_page(int block, int page, uchar *dst)
+{
+ struct mtd_info *mtd = nand_to_mtd(nand_chip);
+ loff_t ofs = ((loff_t)block << mtd->erasesize_shift) +
+ ((loff_t)page << mtd->writesize_shift);
+ size_t len = mtd->writesize;
+
+ return nand_read(mtd, ofs, &len, dst);
+}
+
+#include "nand_spl_loaders.c"
+#endif /* CONFIG_SPL_NAND_INIT */
diff --git a/drivers/mtd/nand/raw/stm32_fmc2_nand.c b/drivers/mtd/nand/raw/stm32_fmc2_nand.c
index 64be648..3528824 100644
--- a/drivers/mtd/nand/raw/stm32_fmc2_nand.c
+++ b/drivers/mtd/nand/raw/stm32_fmc2_nand.c
@@ -22,6 +22,7 @@
#include <linux/ioport.h>
#include <linux/mtd/rawnand.h>
#include <linux/printk.h>
+#include <linux/time.h>
/* Bad block marker length */
#define FMC2_BBM_LEN 2
@@ -127,8 +128,6 @@
#define FMC2_BCHDSR4_EBP7 GENMASK(12, 0)
#define FMC2_BCHDSR4_EBP8 GENMASK(28, 16)
-#define FMC2_NSEC_PER_SEC 1000000000L
-
#define FMC2_TIMEOUT_5S 5000000
enum stm32_fmc2_ecc {
@@ -603,7 +602,7 @@
struct stm32_fmc2_nand *nand = to_fmc2_nand(chip);
struct stm32_fmc2_timings *tims = &nand->timings;
unsigned long hclk = clk_get_rate(&nfc->clk);
- unsigned long hclkp = FMC2_NSEC_PER_SEC / (hclk / 1000);
+ unsigned long hclkp = NSEC_PER_SEC / (hclk / 1000);
unsigned long timing, tar, tclr, thiz, twait;
unsigned long tset_mem, tset_att, thold_mem, thold_att;
diff --git a/drivers/mtd/nand/raw/sunxi_nand_spl.c b/drivers/mtd/nand/raw/sunxi_nand_spl.c
index 6de0b0a..c9b8c78 100644
--- a/drivers/mtd/nand/raw/sunxi_nand_spl.c
+++ b/drivers/mtd/nand/raw/sunxi_nand_spl.c
@@ -524,9 +524,10 @@
return 0;
}
+static struct nfc_config conf;
+
int nand_spl_load_image(uint32_t offs, unsigned int size, void *dest)
{
- static struct nfc_config conf = { };
int ret;
ret = nand_detect_config(&conf, offs, dest);
@@ -536,6 +537,11 @@
return nand_read_buffer(&conf, offs, size, dest);
}
+unsigned int nand_page_size(void)
+{
+ return conf.page_size;
+}
+
void nand_deselect(void)
{
struct sunxi_ccm_reg *const ccm =
diff --git a/drivers/mtd/onenand/onenand_uboot.c b/drivers/mtd/onenand/onenand_uboot.c
index 04791df..ecacabe 100644
--- a/drivers/mtd/onenand/onenand_uboot.c
+++ b/drivers/mtd/onenand/onenand_uboot.c
@@ -44,14 +44,12 @@
puts("Flex-");
puts("OneNAND: ");
-#ifdef CONFIG_MTD
/*
* Add MTD device so that we can reference it later
* via the mtdcore infrastructure (e.g. ubi).
*/
onenand_mtd.name = dev_name;
add_mtd_device(&onenand_mtd);
-#endif
}
print_size(onenand_chip.chipsize, "\n");
}
diff --git a/drivers/mtd/spi/Kconfig b/drivers/mtd/spi/Kconfig
index 2b2efc8..732b076 100644
--- a/drivers/mtd/spi/Kconfig
+++ b/drivers/mtd/spi/Kconfig
@@ -134,6 +134,13 @@
Bank/Extended address registers are used to access the flash
which has size > 16MiB in 3-byte addressing.
+config SPI_FLASH_LOCK
+ bool "Enable the Locking feature"
+ default y
+ help
+ Enable the SPI flash lock support. By default this is set to y.
+ If you intend not to use the lock support you should say n here.
+
config SPI_FLASH_UNLOCK_ALL
bool "Unlock the entire SPI flash on u-boot startup"
default y
diff --git a/drivers/mtd/spi/spi-nor-core.c b/drivers/mtd/spi/spi-nor-core.c
index db20feb..9a1801b 100644
--- a/drivers/mtd/spi/spi-nor-core.c
+++ b/drivers/mtd/spi/spi-nor-core.c
@@ -1100,6 +1100,7 @@
}
#endif
+#if defined(CONFIG_SPI_FLASH_LOCK)
#if defined(CONFIG_SPI_FLASH_STMICRO) || defined(CONFIG_SPI_FLASH_SST)
/* Write status register and ensure bits in mask match written values */
static int write_sr_and_check(struct spi_nor *nor, u8 status_new, u8 mask)
@@ -1387,6 +1388,7 @@
return stm_is_unlocked_sr(nor, ofs, len, status);
}
#endif /* CONFIG_SPI_FLASH_STMICRO */
+#endif
static const struct flash_info *spi_nor_read_id(struct spi_nor *nor)
{
@@ -1462,6 +1464,7 @@
return ret;
}
+#if defined(CONFIG_SPI_FLASH_LOCK)
#ifdef CONFIG_SPI_FLASH_SST
/*
* sst26 flash series has its own block protection implementation:
@@ -1730,6 +1733,8 @@
return ret;
}
#endif
+#endif
+
/*
* Write an address range to the nor chip. Data must be written in
* FLASH_PAGESIZE chunks. The address range may be any size provided
@@ -4104,6 +4109,7 @@
mtd->_read = spi_nor_read;
mtd->_write = spi_nor_write;
+#if defined(CONFIG_SPI_FLASH_LOCK)
#if defined(CONFIG_SPI_FLASH_STMICRO) || defined(CONFIG_SPI_FLASH_SST)
/* NOR protection support for STmicro/Micron chips and similar */
if (JEDEC_MFR(info) == SNOR_MFR_ST ||
@@ -4127,7 +4133,7 @@
nor->flash_is_unlocked = sst26_is_unlocked;
}
#endif
-
+#endif
if (info->flags & USE_FSR)
nor->flags |= SNOR_F_USE_FSR;
if (info->flags & SPI_NOR_HAS_TB)
diff --git a/drivers/mtd/spi/spi-nor-ids.c b/drivers/mtd/spi/spi-nor-ids.c
index 77eb9f3..3cb132d 100644
--- a/drivers/mtd/spi/spi-nor-ids.c
+++ b/drivers/mtd/spi/spi-nor-ids.c
@@ -3,7 +3,7 @@
*
* Copyright (C) 2013 Jagannadha Sutradharudu Teki, Xilinx Inc.
* Copyright (C) 2016 Jagan Teki <jagan@openedev.com>
- * Copyright (C) 2018 Texas Instruments Incorporated - http://www.ti.com/
+ * Copyright (C) 2018 Texas Instruments Incorporated - https://www.ti.com/
*/
#include <common.h>
diff --git a/drivers/mux/mux-uclass.c b/drivers/mux/mux-uclass.c
index 8870305..c98576c 100644
--- a/drivers/mux/mux-uclass.c
+++ b/drivers/mux/mux-uclass.c
@@ -7,7 +7,7 @@
* Copyright (C) 2017 Axentia Technologies AB
* Author: Peter Rosin <peda@axentia.se>
*
- * Copyright (C) 2017-2018 Texas Instruments Incorporated - http://www.ti.com/
+ * Copyright (C) 2017-2018 Texas Instruments Incorporated - https://www.ti.com/
* Jean-Jacques Hiblot <jjhiblot@ti.com>
*/
diff --git a/drivers/net/phy/et1011c.c b/drivers/net/phy/et1011c.c
index fa48314..db879bc 100644
--- a/drivers/net/phy/et1011c.c
+++ b/drivers/net/phy/et1011c.c
@@ -3,7 +3,7 @@
* ET1011C PHY driver
*
* Derived from Linux kernel driver by Chaithrika U S
- * Copyright (C) 2013, Texas Instruments, Incorporated - http://www.ti.com/
+ * Copyright (C) 2013, Texas Instruments, Incorporated - https://www.ti.com/
*/
#include <config.h>
#include <phy.h>
diff --git a/drivers/net/sun8i_emac.c b/drivers/net/sun8i_emac.c
index 4ba9ee1..a12f7e3 100644
--- a/drivers/net/sun8i_emac.c
+++ b/drivers/net/sun8i_emac.c
@@ -168,9 +168,7 @@
struct clk ephy_clk;
struct reset_ctl tx_rst;
struct reset_ctl ephy_rst;
-#if CONFIG_IS_ENABLED(DM_GPIO)
struct gpio_desc reset_gpio;
-#endif
struct udevice *phy_reg;
};
@@ -617,7 +615,6 @@
return ret;
}
-#if CONFIG_IS_ENABLED(DM_GPIO)
static int sun8i_mdio_reset(struct mii_dev *bus)
{
struct udevice *dev = bus->priv;
@@ -649,7 +646,6 @@
return 0;
}
-#endif
static int sun8i_mdio_init(const char *name, struct udevice *priv)
{
@@ -664,9 +660,7 @@
bus->write = sun8i_mdio_write;
snprintf(bus->name, sizeof(bus->name), name);
bus->priv = (void *)priv;
-#if CONFIG_IS_ENABLED(DM_GPIO)
bus->reset = sun8i_mdio_reset;
-#endif
return mdio_register(bus);
}
@@ -783,9 +777,7 @@
const fdt32_t *reg;
int node = dev_of_offset(dev);
int offset = 0;
-#if CONFIG_IS_ENABLED(DM_GPIO)
int reset_flags = GPIOD_IS_OUT;
-#endif
int ret;
pdata->iobase = dev_read_addr(dev);
@@ -872,7 +864,6 @@
printf("%s: Invalid RX delay value %d\n", __func__,
sun8i_pdata->rx_delay_ps);
-#if CONFIG_IS_ENABLED(DM_GPIO)
if (fdtdec_get_bool(gd->fdt_blob, dev_of_offset(dev),
"snps,reset-active-low"))
reset_flags |= GPIOD_ACTIVE_LOW;
@@ -887,7 +878,6 @@
} else if (ret == -ENOENT) {
ret = 0;
}
-#endif
return 0;
}
diff --git a/drivers/net/ti/Kconfig b/drivers/net/ti/Kconfig
index 02660e4..c75f4186 100644
--- a/drivers/net/ti/Kconfig
+++ b/drivers/net/ti/Kconfig
@@ -1,6 +1,6 @@
# SPDX-License-Identifier: GPL-2.0+
#
-# Copyright (C) 2018 Texas Instruments Incorporated - http://www.ti.com/
+# Copyright (C) 2018 Texas Instruments Incorporated - https://www.ti.com/
config DRIVER_TI_CPSW
bool "TI Common Platform Ethernet Switch"
diff --git a/drivers/net/ti/Makefile b/drivers/net/ti/Makefile
index 8d3808b..0ce0cf2 100644
--- a/drivers/net/ti/Makefile
+++ b/drivers/net/ti/Makefile
@@ -1,6 +1,6 @@
# SPDX-License-Identifier: GPL-2.0+
#
-# Copyright (C) 2018 Texas Instruments Incorporated - http://www.ti.com/
+# Copyright (C) 2018 Texas Instruments Incorporated - https://www.ti.com/
obj-$(CONFIG_DRIVER_TI_CPSW) += cpsw.o cpsw-common.o cpsw_mdio.o
obj-$(CONFIG_DRIVER_TI_EMAC) += davinci_emac.o
diff --git a/drivers/net/ti/cpsw.c b/drivers/net/ti/cpsw.c
index 877be7f..9a5e964 100644
--- a/drivers/net/ti/cpsw.c
+++ b/drivers/net/ti/cpsw.c
@@ -2,7 +2,7 @@
/*
* CPSW Ethernet Switch Driver
*
- * Copyright (C) 2010-2018 Texas Instruments Incorporated - http://www.ti.com/
+ * Copyright (C) 2010-2018 Texas Instruments Incorporated - https://www.ti.com/
*/
#include <common.h>
diff --git a/drivers/net/ti/cpsw_mdio.c b/drivers/net/ti/cpsw_mdio.c
index ac791fa..74cc956 100644
--- a/drivers/net/ti/cpsw_mdio.c
+++ b/drivers/net/ti/cpsw_mdio.c
@@ -2,7 +2,7 @@
/*
* CPSW MDIO generic driver for TI AMxx/K2x/EMAC devices.
*
- * Copyright (C) 2018 Texas Instruments Incorporated - http://www.ti.com/
+ * Copyright (C) 2018 Texas Instruments Incorporated - https://www.ti.com/
*/
#include <common.h>
diff --git a/drivers/net/ti/cpsw_mdio.h b/drivers/net/ti/cpsw_mdio.h
index 9b98763..ddf65a4 100644
--- a/drivers/net/ti/cpsw_mdio.h
+++ b/drivers/net/ti/cpsw_mdio.h
@@ -2,7 +2,7 @@
/*
* CPSW MDIO generic driver API for TI AMxx/K2x/EMAC devices.
*
- * Copyright (C) 2018 Texas Instruments Incorporated - http://www.ti.com/
+ * Copyright (C) 2018 Texas Instruments Incorporated - https://www.ti.com/
*/
#ifndef CPSW_MDIO_H_
diff --git a/drivers/phy/Makefile b/drivers/phy/Makefile
index 5d4de86..2e87231 100644
--- a/drivers/phy/Makefile
+++ b/drivers/phy/Makefile
@@ -1,6 +1,6 @@
# SPDX-License-Identifier: GPL-2.0+
#
-# Copyright (C) 2017 Texas Instruments Incorporated - http://www.ti.com/
+# Copyright (C) 2017 Texas Instruments Incorporated - https://www.ti.com/
# Written by Jean-Jacques Hiblot <jjhiblot@ti.com>
obj-y += allwinner/
diff --git a/drivers/phy/cadence/phy-cadence-sierra.c b/drivers/phy/cadence/phy-cadence-sierra.c
index fc5044f..4bb8a0c 100644
--- a/drivers/phy/cadence/phy-cadence-sierra.c
+++ b/drivers/phy/cadence/phy-cadence-sierra.c
@@ -7,7 +7,7 @@
* Copyright (c) 2018 Cadence Design Systems
* Author: Alan Douglas <adouglas@cadence.com>
*
- * Copyright (C) 2019 Texas Instruments Incorporated - http://www.ti.com/
+ * Copyright (C) 2019 Texas Instruments Incorporated - https://www.ti.com/
* Jean-Jacques Hiblot <jjhiblot@ti.com>
*
*/
diff --git a/drivers/phy/keystone-usb-phy.c b/drivers/phy/keystone-usb-phy.c
index 6799e23..3bb9c08 100644
--- a/drivers/phy/keystone-usb-phy.c
+++ b/drivers/phy/keystone-usb-phy.c
@@ -1,6 +1,6 @@
// SPDX-License-Identifier: GPL-2.0+
/*
- * Copyright (C) 2017 Texas Instruments Incorporated - http://www.ti.com/
+ * Copyright (C) 2017 Texas Instruments Incorporated - https://www.ti.com/
* Written by Jean-Jacques Hiblot <jjhiblot@ti.com>
*/
diff --git a/drivers/phy/meson-axg-mipi-dphy.c b/drivers/phy/meson-axg-mipi-dphy.c
index cf2a1cd..a69b6c9 100644
--- a/drivers/phy/meson-axg-mipi-dphy.c
+++ b/drivers/phy/meson-axg-mipi-dphy.c
@@ -25,6 +25,7 @@
#include <linux/bitops.h>
#include <linux/compat.h>
#include <linux/bitfield.h>
+#include <linux/time.h>
/* [31] soft reset for the phy.
* 1: reset. 0: dessert the reset.
@@ -170,8 +171,6 @@
#define MIPI_DSI_TEST_CTRL0 0x3c
#define MIPI_DSI_TEST_CTRL1 0x40
-#define NSEC_PER_MSEC 1000000L
-
struct phy_meson_axg_mipi_dphy_priv {
struct regmap *regmap;
#if CONFIG_IS_ENABLED(CLK)
diff --git a/drivers/phy/nop-phy.c b/drivers/phy/nop-phy.c
index d0904f4..c53e321 100644
--- a/drivers/phy/nop-phy.c
+++ b/drivers/phy/nop-phy.c
@@ -1,6 +1,6 @@
// SPDX-License-Identifier: GPL-2.0+
/*
- * Copyright (C) 2017 Texas Instruments Incorporated - http://www.ti.com/
+ * Copyright (C) 2017 Texas Instruments Incorporated - https://www.ti.com/
* Written by Jean-Jacques Hiblot <jjhiblot@ti.com>
*/
diff --git a/drivers/phy/omap-usb2-phy.c b/drivers/phy/omap-usb2-phy.c
index 2a9604c..d3d3806 100644
--- a/drivers/phy/omap-usb2-phy.c
+++ b/drivers/phy/omap-usb2-phy.c
@@ -2,7 +2,7 @@
/*
* OMAP USB2 PHY LAYER
*
- * Copyright (C) 2018 Texas Instruments Incorporated - http://www.ti.com
+ * Copyright (C) 2018 Texas Instruments Incorporated - https://www.ti.com
* Written by Jean-Jacques Hiblot <jjhiblot@ti.com>
*/
diff --git a/drivers/phy/phy-core-mipi-dphy.c b/drivers/phy/phy-core-mipi-dphy.c
index ba5f648..bb61816 100644
--- a/drivers/phy/phy-core-mipi-dphy.c
+++ b/drivers/phy/phy-core-mipi-dphy.c
@@ -6,11 +6,10 @@
#include <common.h>
#include <div64.h>
+#include <linux/time.h>
#include <phy-mipi-dphy.h>
-#define PSEC_PER_SEC 1000000000000LL
-
/*
* Minimum D-PHY timings based on MIPI D-PHY specification. Derived
* from the valid ranges specified in Section 6.9, Table 14, Page 41
diff --git a/drivers/phy/phy-uclass.c b/drivers/phy/phy-uclass.c
index 22f2fe9..0dcfe25 100644
--- a/drivers/phy/phy-uclass.c
+++ b/drivers/phy/phy-uclass.c
@@ -1,6 +1,6 @@
// SPDX-License-Identifier: GPL-2.0+
/*
- * Copyright (C) 2017 Texas Instruments Incorporated - http://www.ti.com/
+ * Copyright (C) 2017 Texas Instruments Incorporated - https://www.ti.com/
* Written by Jean-Jacques Hiblot <jjhiblot@ti.com>
*/
diff --git a/drivers/phy/rockchip/phy-rockchip-inno-dsidphy.c b/drivers/phy/rockchip/phy-rockchip-inno-dsidphy.c
index 9ed7af0..5be76e0 100644
--- a/drivers/phy/rockchip/phy-rockchip-inno-dsidphy.c
+++ b/drivers/phy/rockchip/phy-rockchip-inno-dsidphy.c
@@ -15,6 +15,7 @@
#include <linux/clk-provider.h>
#include <linux/delay.h>
#include <linux/math64.h>
+#include <linux/time.h>
#include <phy-mipi-dphy.h>
#include <reset.h>
@@ -186,8 +187,6 @@
#define DSI_PHY_STATUS 0xb0
#define PHY_LOCK BIT(0)
-#define PSEC_PER_SEC 1000000000000LL
-
#define msleep(a) udelay(a * 1000)
enum phy_max_rate {
diff --git a/drivers/phy/sandbox-phy.c b/drivers/phy/sandbox-phy.c
index 7b3d988..7e123da 100644
--- a/drivers/phy/sandbox-phy.c
+++ b/drivers/phy/sandbox-phy.c
@@ -1,6 +1,6 @@
// SPDX-License-Identifier: GPL-2.0+
/*
- * Copyright (C) 2017 Texas Instruments Incorporated - http://www.ti.com/
+ * Copyright (C) 2017 Texas Instruments Incorporated - https://www.ti.com/
* Written by Jean-Jacques Hiblot <jjhiblot@ti.com>
*/
diff --git a/drivers/phy/ti-pipe3-phy.c b/drivers/phy/ti-pipe3-phy.c
index 3137358..29a35ae 100644
--- a/drivers/phy/ti-pipe3-phy.c
+++ b/drivers/phy/ti-pipe3-phy.c
@@ -1,6 +1,6 @@
// SPDX-License-Identifier: GPL-2.0+
/*
- * Copyright (C) 2017 Texas Instruments Incorporated - http://www.ti.com/
+ * Copyright (C) 2017 Texas Instruments Incorporated - https://www.ti.com/
* Written by Jean-Jacques Hiblot <jjhiblot@ti.com>
*/
diff --git a/drivers/phy/ti/phy-j721e-wiz.c b/drivers/phy/ti/phy-j721e-wiz.c
index 7261339..daf62f5 100644
--- a/drivers/phy/ti/phy-j721e-wiz.c
+++ b/drivers/phy/ti/phy-j721e-wiz.c
@@ -1,6 +1,6 @@
// SPDX-License-Identifier: GPL-2.0+
/*
- * Copyright (C) 2017-2018 Texas Instruments Incorporated - http://www.ti.com/
+ * Copyright (C) 2017-2018 Texas Instruments Incorporated - https://www.ti.com/
* Jean-Jacques Hiblot <jjhiblot@ti.com>
*/
diff --git a/drivers/pinctrl/sunxi/pinctrl-sunxi.c b/drivers/pinctrl/sunxi/pinctrl-sunxi.c
index bdf6360..37ea937 100644
--- a/drivers/pinctrl/sunxi/pinctrl-sunxi.c
+++ b/drivers/pinctrl/sunxi/pinctrl-sunxi.c
@@ -50,7 +50,7 @@
uint pin_selector)
{
const struct sunxi_pinctrl_desc *desc = dev_get_priv(dev);
- static char pin_name[sizeof("PN31")];
+ static char pin_name[sizeof("PN31")] __section(".data");
snprintf(pin_name, sizeof(pin_name), "P%c%d",
pin_selector / SUNXI_GPIOS_PER_BANK + desc->first_bank + 'A',
diff --git a/drivers/power/Kconfig b/drivers/power/Kconfig
index 7f3b990..2395720 100644
--- a/drivers/power/Kconfig
+++ b/drivers/power/Kconfig
@@ -101,6 +101,15 @@
Select this to enable support for the axp305 pmic found on most
H616 boards.
+config AXP313_POWER
+ bool "axp313 pmic support"
+ depends on MACH_SUN50I_H616
+ select AXP_PMIC_BUS
+ select CMD_POWEROFF
+ ---help---
+ Select this to enable support for the AXP313 PMIC found on some
+ H616 boards.
+
config AXP809_POWER
bool "axp809 pmic support"
depends on MACH_SUN9I
@@ -143,9 +152,10 @@
config AXP_DCDC2_VOLT
int "axp pmic dcdc2 voltage"
- depends on AXP152_POWER || AXP209_POWER || AXP221_POWER || AXP809_POWER || AXP818_POWER
+ depends on AXP152_POWER || AXP209_POWER || AXP221_POWER || AXP809_POWER || AXP818_POWER || AXP313_POWER
default 900 if AXP818_POWER
default 1400 if AXP152_POWER || AXP209_POWER
+ default 1000 if AXP313_POWER
default 1200 if MACH_SUN6I
default 1100 if MACH_SUN8I
default 0 if MACH_SUN9I
@@ -158,13 +168,15 @@
On A80 boards dcdc2 powers the GPU and can be left off.
On A83T boards dcdc2 is used for VDD-CPUA(cluster 0) and should be 0.9V.
On R40 boards dcdc2 is VDD-CPU and should be 1.1V
+ On boards using the AXP313 it's often VDD-CPU.
config AXP_DCDC3_VOLT
int "axp pmic dcdc3 voltage"
- depends on AXP152_POWER || AXP209_POWER || AXP221_POWER || AXP809_POWER || AXP818_POWER
+ depends on AXP152_POWER || AXP209_POWER || AXP221_POWER || AXP809_POWER || AXP818_POWER || AXP313_POWER
default 900 if AXP809_POWER || AXP818_POWER
default 1500 if AXP152_POWER
default 1250 if AXP209_POWER
+ default 1100 if AXP313_POWER
default 1100 if MACH_SUN8I_R40
default 1200 if MACH_SUN6I || MACH_SUN8I
---help---
@@ -177,10 +189,11 @@
On A80 boards dcdc3 is used for VDD-CPUA(cluster 0) and should be 0.9V.
On A83T boards dcdc3 is used for VDD-CPUB(cluster 1) and should be 0.9V.
On R40 boards dcdc3 is VDD-SYS and VDD-GPU and should be 1.1V.
+ On boards using the AXP313 it's often VDD-DRAM and should be 1.1V for LPDDR4.
config AXP_DCDC4_VOLT
int "axp pmic dcdc4 voltage"
- depends on AXP152_POWER || AXP221_POWER || AXP809_POWER || AXP818_POWER || AXP305_POWER
+ depends on AXP152_POWER || AXP221_POWER || AXP809_POWER || AXP305_POWER
default 1250 if AXP152_POWER
default 1200 if MACH_SUN6I
default 0 if MACH_SUN8I
diff --git a/drivers/power/Makefile b/drivers/power/Makefile
index ba64b2c..c7ee459 100644
--- a/drivers/power/Makefile
+++ b/drivers/power/Makefile
@@ -12,6 +12,7 @@
obj-$(CONFIG_AXP209_POWER) += axp209.o
obj-$(CONFIG_AXP221_POWER) += axp221.o
obj-$(CONFIG_AXP305_POWER) += axp305.o
+obj-$(CONFIG_AXP313_POWER) += axp313.o
obj-$(CONFIG_AXP809_POWER) += axp809.o
obj-$(CONFIG_AXP818_POWER) += axp818.o
obj-$(CONFIG_EXYNOS_TMU) += exynos-tmu.o
diff --git a/drivers/power/axp313.c b/drivers/power/axp313.c
new file mode 100644
index 0000000..bbc9e91
--- /dev/null
+++ b/drivers/power/axp313.c
@@ -0,0 +1,134 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * AXP313(a) driver
+ *
+ * (C) Copyright 2023 Arm Ltd.
+ *
+ * Based on axp305.c
+ * (C) Copyright 2020 Jernej Skrabec <jernej.skrabec@siol.net>
+ * (C) Copyright 2014 Hans de Goede <hdegoede@redhat.com>
+ * (C) Copyright 2013 Oliver Schinagl <oliver@schinagl.nl>
+ */
+
+#include <common.h>
+#include <command.h>
+#include <errno.h>
+#include <asm/arch/pmic_bus.h>
+#include <axp_pmic.h>
+
+enum axp313_reg {
+ AXP313_CHIP_VERSION = 0x03,
+ AXP313_OUTPUT_CTRL = 0x10,
+ AXP313_DCDC1_CTRL = 0x13,
+ AXP313_SHUTDOWN = 0x1a,
+};
+
+#define AXP313_CHIP_VERSION_MASK 0xcf
+#define AXP313_CHIP_VERSION_AXP1530 0x48
+#define AXP313_CHIP_VERSION_AXP313A 0x4b
+#define AXP313_CHIP_VERSION_AXP313B 0x4c
+
+#define AXP313_DCDC_SPLIT_OFFSET 71
+#define AXP313_DCDC_SPLIT_MVOLT 1200
+
+#define AXP313_POWEROFF BIT(7)
+
+static u8 mvolt_to_cfg(int mvolt, int min, int max, int div)
+{
+ if (mvolt < min)
+ mvolt = min;
+ else if (mvolt > max)
+ mvolt = max;
+
+ return (mvolt - min) / div;
+}
+
+static int axp_set_dcdc(int dcdc_num, unsigned int mvolt)
+{
+ int ret;
+ u8 cfg, enable_mask = 1U << (dcdc_num - 1);
+ int volt_reg = AXP313_DCDC1_CTRL + dcdc_num - 1;
+ int max_mV;
+
+ switch (dcdc_num) {
+ case 1:
+ case 2:
+ max_mV = 1540;
+ break;
+ case 3:
+ /*
+ * The manual defines a different split point, but tests
+ * show that it's the same 1200mV as for DCDC1/2.
+ */
+ max_mV = 1840;
+ break;
+ default:
+ return -EINVAL;
+ }
+
+ if (mvolt > AXP313_DCDC_SPLIT_MVOLT)
+ cfg = AXP313_DCDC_SPLIT_OFFSET + mvolt_to_cfg(mvolt,
+ AXP313_DCDC_SPLIT_MVOLT + 20, max_mV, 20);
+ else
+ cfg = mvolt_to_cfg(mvolt, 500, AXP313_DCDC_SPLIT_MVOLT, 10);
+
+ if (mvolt == 0)
+ return pmic_bus_clrbits(AXP313_OUTPUT_CTRL, enable_mask);
+
+ debug("DCDC%d: writing 0x%x to reg 0x%x\n", dcdc_num, cfg, volt_reg);
+ ret = pmic_bus_write(volt_reg, cfg);
+ if (ret)
+ return ret;
+
+ return pmic_bus_setbits(AXP313_OUTPUT_CTRL, enable_mask);
+}
+
+int axp_set_dcdc2(unsigned int mvolt)
+{
+ return axp_set_dcdc(2, mvolt);
+}
+
+int axp_set_dcdc3(unsigned int mvolt)
+{
+ return axp_set_dcdc(3, mvolt);
+}
+
+int axp_init(void)
+{
+ u8 axp_chip_id;
+ int ret;
+
+ ret = pmic_bus_init();
+ if (ret)
+ return ret;
+
+ ret = pmic_bus_read(AXP313_CHIP_VERSION, &axp_chip_id);
+ if (ret)
+ return ret;
+
+ axp_chip_id &= AXP313_CHIP_VERSION_MASK;
+ switch (axp_chip_id) {
+ case AXP313_CHIP_VERSION_AXP1530:
+ case AXP313_CHIP_VERSION_AXP313A:
+ case AXP313_CHIP_VERSION_AXP313B:
+ break;
+ default:
+ debug("unknown PMIC: 0x%x\n", axp_chip_id);
+ return -EINVAL;
+ }
+
+ return ret;
+}
+
+#if !CONFIG_IS_ENABLED(ARM_PSCI_FW) && !IS_ENABLED(CONFIG_SYSRESET_CMD_POWEROFF)
+int do_poweroff(struct cmd_tbl *cmdtp, int flag, int argc, char *const argv[])
+{
+ pmic_bus_write(AXP313_SHUTDOWN, AXP313_POWEROFF);
+
+ /* infinite loop during shutdown */
+ while (1) {}
+
+ /* not reached */
+ return 0;
+}
+#endif
diff --git a/drivers/power/domain/ti-power-domain.c b/drivers/power/domain/ti-power-domain.c
index 9e71513..b34c982 100644
--- a/drivers/power/domain/ti-power-domain.c
+++ b/drivers/power/domain/ti-power-domain.c
@@ -2,7 +2,7 @@
/*
* Texas Instruments power domain driver
*
- * Copyright (C) 2020-2021 Texas Instruments Incorporated - http://www.ti.com/
+ * Copyright (C) 2020-2021 Texas Instruments Incorporated - https://www.ti.com/
* Tero Kristo <t-kristo@ti.com>
*/
diff --git a/drivers/power/domain/ti-sci-power-domain.c b/drivers/power/domain/ti-sci-power-domain.c
index 0140e5e..8d6abe1 100644
--- a/drivers/power/domain/ti-sci-power-domain.c
+++ b/drivers/power/domain/ti-sci-power-domain.c
@@ -2,7 +2,7 @@
/*
* Texas Instruments System Control Interface (TI SCI) power domain driver
*
- * Copyright (C) 2018 Texas Instruments Incorporated - http://www.ti.com/
+ * Copyright (C) 2018 Texas Instruments Incorporated - https://www.ti.com/
* Andreas Dannenberg <dannenberg@ti.com>
*
* Loosely based on Linux kernel ti_sci_pm_domains.c...
diff --git a/drivers/power/pmic/axp.c b/drivers/power/pmic/axp.c
index 025dac2..0e1e45f 100644
--- a/drivers/power/pmic/axp.c
+++ b/drivers/power/pmic/axp.c
@@ -87,6 +87,7 @@
{ .compatible = "x-powers,axp209", .data = AXP209_ID },
{ .compatible = "x-powers,axp221", .data = AXP221_ID },
{ .compatible = "x-powers,axp223", .data = AXP223_ID },
+ { .compatible = "x-powers,axp313a", .data = AXP313_ID },
{ .compatible = "x-powers,axp803", .data = AXP803_ID },
{ .compatible = "x-powers,axp806", .data = AXP806_ID },
{ .compatible = "x-powers,axp809", .data = AXP809_ID },
diff --git a/drivers/power/pmic/pmic_tps62362.c b/drivers/power/pmic/pmic_tps62362.c
index 59190d6..6426d14 100644
--- a/drivers/power/pmic/pmic_tps62362.c
+++ b/drivers/power/pmic/pmic_tps62362.c
@@ -1,6 +1,6 @@
// SPDX-License-Identifier: GPL-2.0+
/*
- * (C) Copyright 2014 Texas Instruments Incorporated - http://www.ti.com
+ * (C) Copyright 2014 Texas Instruments Incorporated - https://www.ti.com
* Author: Felipe Balbi <balbi@ti.com>
*/
diff --git a/drivers/power/regulator/axp_regulator.c b/drivers/power/regulator/axp_regulator.c
index 02f320e..d27e095 100644
--- a/drivers/power/regulator/axp_regulator.c
+++ b/drivers/power/regulator/axp_regulator.c
@@ -173,6 +173,22 @@
{ }
};
+/*
+ * The "dcdc1" regulator has another range, beyond 1.54V up to 3.4V, in
+ * steps of 100mV. We cannot model this easily, but also don't need that,
+ * since it's typically only used for ~1.1V anyway, so just ignore it.
+ * Also the DCDC3 regulator is described wrongly in the (available) manual,
+ * experiments show that the split point is at 1200mV, as for DCDC1/2.
+ */
+static const struct axp_regulator_plat axp313_regulators[] = {
+ { "dcdc1", 0x10, BIT(0), 0x13, 0x7f, 500, 1540, 10, 70 },
+ { "dcdc2", 0x10, BIT(1), 0x14, 0x7f, 500, 1540, 10, 70 },
+ { "dcdc3", 0x10, BIT(2), 0x15, 0x7f, 500, 1840, 10, 70 },
+ { "aldo1", 0x10, BIT(3), 0x16, 0x1f, 500, 3500, 100, NA },
+ { "dldo1", 0x10, BIT(4), 0x17, 0x1f, 500, 3500, 100, NA },
+ { }
+};
+
static const struct axp_regulator_plat axp803_regulators[] = {
{ "dcdc1", 0x10, BIT(0), 0x20, 0x1f, 1600, 3400, 100, NA },
{ "dcdc2", 0x10, BIT(1), 0x21, 0x7f, 500, 1300, 10, 70 },
@@ -274,6 +290,7 @@
[AXP209_ID] = axp20x_regulators,
[AXP221_ID] = axp22x_regulators,
[AXP223_ID] = axp22x_regulators,
+ [AXP313_ID] = axp313_regulators,
[AXP803_ID] = axp803_regulators,
[AXP806_ID] = axp806_regulators,
[AXP809_ID] = axp809_regulators,
diff --git a/drivers/power/regulator/tps62360_regulator.c b/drivers/power/regulator/tps62360_regulator.c
index b9f4504..7014b19 100644
--- a/drivers/power/regulator/tps62360_regulator.c
+++ b/drivers/power/regulator/tps62360_regulator.c
@@ -1,6 +1,6 @@
// SPDX-License-Identifier: GPL-2.0+
/*
- * Copyright (C) 2019 Texas Instruments Incorporated - http://www.ti.com/
+ * Copyright (C) 2019 Texas Instruments Incorporated - https://www.ti.com/
* Tero Kristo <t-kristo@ti.com>
*/
diff --git a/drivers/pwm/pwm-aspeed.c b/drivers/pwm/pwm-aspeed.c
index ba98641..b03472d 100644
--- a/drivers/pwm/pwm-aspeed.c
+++ b/drivers/pwm/pwm-aspeed.c
@@ -49,6 +49,7 @@
#include <dm/device_compat.h>
#include <linux/math64.h>
#include <linux/bitfield.h>
+#include <linux/time.h>
#include <asm/io.h>
/* The channel number of Aspeed pwm controller */
@@ -77,8 +78,6 @@
/* PWM fixed value */
#define PWM_ASPEED_FIXED_PERIOD 0xff
-#define NSEC_PER_SEC 1000000000L
-
struct aspeed_pwm_priv {
struct clk clk;
struct regmap *regmap;
diff --git a/drivers/pwm/pwm-at91.c b/drivers/pwm/pwm-at91.c
index 95597aee..3ff1fb6 100644
--- a/drivers/pwm/pwm-at91.c
+++ b/drivers/pwm/pwm-at91.c
@@ -14,11 +14,11 @@
#include <dm.h>
#include <linux/bitops.h>
#include <linux/io.h>
+#include <linux/time.h>
#include <pwm.h>
#define PERIOD_BITS 16
#define PWM_MAX_PRES 10
-#define NSEC_PER_SEC 1000000000L
#define PWM_ENA 0x04
#define PWM_CHANNEL_OFFSET 0x20
diff --git a/drivers/pwm/pwm-cadence-ttc.c b/drivers/pwm/pwm-cadence-ttc.c
index dc3b314..d9f6736 100644
--- a/drivers/pwm/pwm-cadence-ttc.c
+++ b/drivers/pwm/pwm-cadence-ttc.c
@@ -17,6 +17,7 @@
#include <linux/bitfield.h>
#include <linux/math64.h>
#include <linux/log2.h>
+#include <linux/time.h>
#include <dm/device_compat.h>
#define CLOCK_CONTROL 0
@@ -37,8 +38,6 @@
#define COUNTER_INTERVAL_ENABLE BIT(1)
#define COUNTER_COUNTING_DISABLE BIT(0)
-#define NSEC_PER_SEC 1000000000L
-
#define TTC_REG(reg, channel) ((reg) + (channel) * sizeof(u32))
#define TTC_CLOCK_CONTROL(reg, channel) \
TTC_REG((reg) + CLOCK_CONTROL, (channel))
diff --git a/drivers/pwm/pwm-meson.c b/drivers/pwm/pwm-meson.c
index 2311910..6095972 100644
--- a/drivers/pwm/pwm-meson.c
+++ b/drivers/pwm/pwm-meson.c
@@ -26,8 +26,7 @@
#include <linux/math64.h>
#include <linux/bitfield.h>
#include <linux/clk-provider.h>
-
-#define NSEC_PER_SEC 1000000000L
+#include <linux/time.h>
#define REG_PWM_A 0x0
#define REG_PWM_B 0x4
diff --git a/drivers/pwm/pwm-mtk.c b/drivers/pwm/pwm-mtk.c
index 11e7444..ad845ed 100644
--- a/drivers/pwm/pwm-mtk.c
+++ b/drivers/pwm/pwm-mtk.c
@@ -12,6 +12,7 @@
#include <div64.h>
#include <linux/bitops.h>
#include <linux/io.h>
+#include <linux/time.h>
/* PWM registers and bits definitions */
#define PWMCON 0x00
@@ -27,8 +28,6 @@
#define PWM_CLK_DIV_MAX 7
#define MAX_PWM_NUM 8
-#define NSEC_PER_SEC 1000000000L
-
enum mtk_pwm_reg_ver {
PWM_REG_V1,
PWM_REG_V2,
diff --git a/drivers/pwm/pwm-ti-ehrpwm.c b/drivers/pwm/pwm-ti-ehrpwm.c
index f099145..fefa3c6 100644
--- a/drivers/pwm/pwm-ti-ehrpwm.c
+++ b/drivers/pwm/pwm-ti-ehrpwm.c
@@ -14,8 +14,7 @@
#include <dm/device_compat.h>
#include <pwm.h>
#include <asm/io.h>
-
-#define NSEC_PER_SEC 1000000000L
+#include <linux/time.h>
/* Time base module registers */
#define TI_EHRPWM_TBCTL 0x00
diff --git a/drivers/ram/k3-am654-ddrss.c b/drivers/ram/k3-am654-ddrss.c
index 4a8a6a9..cff8ffc 100644
--- a/drivers/ram/k3-am654-ddrss.c
+++ b/drivers/ram/k3-am654-ddrss.c
@@ -2,7 +2,7 @@
/*
* Texas Instruments' AM654 DDRSS driver
*
- * Copyright (C) 2018 Texas Instruments Incorporated - http://www.ti.com/
+ * Copyright (C) 2018 Texas Instruments Incorporated - https://www.ti.com/
* Lokesh Vutla <lokeshvutla@ti.com>
*/
diff --git a/drivers/ram/k3-am654-ddrss.h b/drivers/ram/k3-am654-ddrss.h
index c87f186..9d03ae1 100644
--- a/drivers/ram/k3-am654-ddrss.h
+++ b/drivers/ram/k3-am654-ddrss.h
@@ -2,7 +2,7 @@
/*
* AM654: DDRSS Register definitions and structures.
*
- * Copyright (C) 2018 Texas Instruments Incorporated - http://www.ti.com/
+ * Copyright (C) 2018 Texas Instruments Incorporated - https://www.ti.com/
* Lokesh Vutla <lokeshvutla@ti.com>
*
*/
diff --git a/drivers/ram/k3-ddrss/Makefile b/drivers/ram/k3-ddrss/Makefile
index ba5d9a2..823d188 100644
--- a/drivers/ram/k3-ddrss/Makefile
+++ b/drivers/ram/k3-ddrss/Makefile
@@ -1,6 +1,6 @@
# SPDX-License-Identifier: GPL-2.0+
#
-# Copyright (C) 2019-2022 Texas Instruments Incorporated - http://www.ti.com/
+# Copyright (C) 2019-2022 Texas Instruments Incorporated - https://www.ti.com/
#
obj-$(CONFIG_K3_DDRSS) += k3-ddrss.o
diff --git a/drivers/ram/k3-ddrss/k3-ddrss.c b/drivers/ram/k3-ddrss/k3-ddrss.c
index 5b6089e..a5c9b82 100644
--- a/drivers/ram/k3-ddrss/k3-ddrss.c
+++ b/drivers/ram/k3-ddrss/k3-ddrss.c
@@ -2,7 +2,7 @@
/*
* Texas Instruments' K3 DDRSS driver
*
- * Copyright (C) 2020-2021 Texas Instruments Incorporated - http://www.ti.com/
+ * Copyright (C) 2020-2021 Texas Instruments Incorporated - https://www.ti.com/
*/
#include <common.h>
diff --git a/drivers/remoteproc/Kconfig b/drivers/remoteproc/Kconfig
index 27e4a60..781de53 100644
--- a/drivers/remoteproc/Kconfig
+++ b/drivers/remoteproc/Kconfig
@@ -1,7 +1,7 @@
# SPDX-License-Identifier: GPL-2.0+
#
# (C) Copyright 2015
-# Texas Instruments Incorporated - http://www.ti.com/
+# Texas Instruments Incorporated - https://www.ti.com/
#
menu "Remote Processor drivers"
diff --git a/drivers/remoteproc/Makefile b/drivers/remoteproc/Makefile
index fbe9c17..e09ed1a 100644
--- a/drivers/remoteproc/Makefile
+++ b/drivers/remoteproc/Makefile
@@ -1,7 +1,7 @@
# SPDX-License-Identifier: GPL-2.0+
#
# (C) Copyright 2015
-# Texas Instruments Incorporated - http://www.ti.com/
+# Texas Instruments Incorporated - https://www.ti.com/
#
obj-$(CONFIG_$(SPL_)REMOTEPROC) += rproc-uclass.o rproc-elf-loader.o
diff --git a/drivers/remoteproc/ipu_rproc.c b/drivers/remoteproc/ipu_rproc.c
index b4a06bc..996e658 100644
--- a/drivers/remoteproc/ipu_rproc.c
+++ b/drivers/remoteproc/ipu_rproc.c
@@ -2,7 +2,7 @@
/*
* IPU remoteproc driver for various SoCs
*
- * Copyright (C) 2019 Texas Instruments Incorporated - http://www.ti.com/
+ * Copyright (C) 2019 Texas Instruments Incorporated - https://www.ti.com/
* Angela Stegmaier <angelabaker@ti.com>
* Venkateswara Rao Mandela <venkat.mandela@ti.com>
* Keerthy <j-keerthy@ti.com>
diff --git a/drivers/remoteproc/k3_system_controller.c b/drivers/remoteproc/k3_system_controller.c
index e2affe6..071de40 100644
--- a/drivers/remoteproc/k3_system_controller.c
+++ b/drivers/remoteproc/k3_system_controller.c
@@ -2,7 +2,7 @@
/*
* Texas Instruments' K3 System Controller Driver
*
- * Copyright (C) 2017-2018 Texas Instruments Incorporated - http://www.ti.com/
+ * Copyright (C) 2017-2018 Texas Instruments Incorporated - https://www.ti.com/
* Lokesh Vutla <lokeshvutla@ti.com>
*/
diff --git a/drivers/remoteproc/pru_rproc.c b/drivers/remoteproc/pru_rproc.c
index 924070a..6ec55e2 100644
--- a/drivers/remoteproc/pru_rproc.c
+++ b/drivers/remoteproc/pru_rproc.c
@@ -2,7 +2,7 @@
/*
* PRU-RTU remoteproc driver for various SoCs
*
- * Copyright (C) 2018 Texas Instruments Incorporated - http://www.ti.com/
+ * Copyright (C) 2018 Texas Instruments Incorporated - https://www.ti.com/
* Keerthy <j-keerthy@ti.com>
*/
diff --git a/drivers/remoteproc/rproc-uclass.c b/drivers/remoteproc/rproc-uclass.c
index ece534c..28b362c 100644
--- a/drivers/remoteproc/rproc-uclass.c
+++ b/drivers/remoteproc/rproc-uclass.c
@@ -1,7 +1,7 @@
// SPDX-License-Identifier: GPL-2.0+
/*
* (C) Copyright 2015
- * Texas Instruments Incorporated - http://www.ti.com/
+ * Texas Instruments Incorporated - https://www.ti.com/
*/
#define LOG_CATEGORY UCLASS_REMOTEPROC
diff --git a/drivers/remoteproc/sandbox_testproc.c b/drivers/remoteproc/sandbox_testproc.c
index d360cf3..f76f68e 100644
--- a/drivers/remoteproc/sandbox_testproc.c
+++ b/drivers/remoteproc/sandbox_testproc.c
@@ -1,7 +1,7 @@
// SPDX-License-Identifier: GPL-2.0+
/*
* (C) Copyright 2015
- * Texas Instruments Incorporated - http://www.ti.com/
+ * Texas Instruments Incorporated - https://www.ti.com/
*/
#define pr_fmt(fmt) "%s: " fmt, __func__
#include <common.h>
diff --git a/drivers/remoteproc/ti_k3_arm64_rproc.c b/drivers/remoteproc/ti_k3_arm64_rproc.c
index 99f1100..767493c 100644
--- a/drivers/remoteproc/ti_k3_arm64_rproc.c
+++ b/drivers/remoteproc/ti_k3_arm64_rproc.c
@@ -2,7 +2,7 @@
/*
* Texas Instruments' K3 ARM64 Remoteproc driver
*
- * Copyright (C) 2018 Texas Instruments Incorporated - http://www.ti.com/
+ * Copyright (C) 2018 Texas Instruments Incorporated - https://www.ti.com/
* Lokesh Vutla <lokeshvutla@ti.com>
*
*/
diff --git a/drivers/remoteproc/ti_k3_dsp_rproc.c b/drivers/remoteproc/ti_k3_dsp_rproc.c
index 1a2e9dd..576de4b 100644
--- a/drivers/remoteproc/ti_k3_dsp_rproc.c
+++ b/drivers/remoteproc/ti_k3_dsp_rproc.c
@@ -2,7 +2,7 @@
/*
* Texas Instruments' K3 DSP Remoteproc driver
*
- * Copyright (C) 2018-2020 Texas Instruments Incorporated - http://www.ti.com/
+ * Copyright (C) 2018-2020 Texas Instruments Incorporated - https://www.ti.com/
* Lokesh Vutla <lokeshvutla@ti.com>
* Suman Anna <s-anna@ti.com>
*/
diff --git a/drivers/remoteproc/ti_power_proc.c b/drivers/remoteproc/ti_power_proc.c
index 6887a3c..f55df4a 100644
--- a/drivers/remoteproc/ti_power_proc.c
+++ b/drivers/remoteproc/ti_power_proc.c
@@ -1,7 +1,7 @@
// SPDX-License-Identifier: GPL-2.0+
/*
* (C) Copyright 2015-2016
- * Texas Instruments Incorporated - http://www.ti.com/
+ * Texas Instruments Incorporated - https://www.ti.com/
*/
#define pr_fmt(fmt) "%s: " fmt, __func__
#include <common.h>
diff --git a/drivers/remoteproc/ti_sci_proc.h b/drivers/remoteproc/ti_sci_proc.h
index 36351da..167a714 100644
--- a/drivers/remoteproc/ti_sci_proc.h
+++ b/drivers/remoteproc/ti_sci_proc.h
@@ -2,7 +2,7 @@
/*
* Texas Instruments TI-SCI Processor Controller Helper Functions
*
- * Copyright (C) 2018-2019 Texas Instruments Incorporated - http://www.ti.com/
+ * Copyright (C) 2018-2019 Texas Instruments Incorporated - https://www.ti.com/
* Lokesh Vutla <lokeshvutla@ti.com>
* Suman Anna <s-anna@ti.com>
*/
diff --git a/drivers/reset/reset-dra7.c b/drivers/reset/reset-dra7.c
index a9589d4..05101a9 100644
--- a/drivers/reset/reset-dra7.c
+++ b/drivers/reset/reset-dra7.c
@@ -2,7 +2,7 @@
/*
* Texas Instruments DRA7 reset driver
*
- * Copyright (C) 2019 Texas Instruments Incorporated - http://www.ti.com/
+ * Copyright (C) 2019 Texas Instruments Incorporated - https://www.ti.com/
* Author: Keerthy <j-keerthy@ti.com>
*/
diff --git a/drivers/reset/reset-ti-sci.c b/drivers/reset/reset-ti-sci.c
index f353327..fd654a0 100644
--- a/drivers/reset/reset-ti-sci.c
+++ b/drivers/reset/reset-ti-sci.c
@@ -2,7 +2,7 @@
/*
* Texas Instruments System Control Interface (TI SCI) reset driver
*
- * Copyright (C) 2018 Texas Instruments Incorporated - http://www.ti.com/
+ * Copyright (C) 2018 Texas Instruments Incorporated - https://www.ti.com/
* Andreas Dannenberg <dannenberg@ti.com>
*
* Loosely based on Linux kernel reset-ti-sci.c...
diff --git a/drivers/scsi/scsi.c b/drivers/scsi/scsi.c
index 363047d..79ee400 100644
--- a/drivers/scsi/scsi.c
+++ b/drivers/scsi/scsi.c
@@ -292,6 +292,7 @@
pccb->cmd[0] = SCSI_RD_CAPAC10;
pccb->cmd[1] = pccb->lun << 5;
pccb->cmdlen = 10;
+ pccb->dma_dir = DMA_FROM_DEVICE;
pccb->msgout[0] = SCSI_IDENTIFY; /* NOT USED */
pccb->datalen = 8;
@@ -368,15 +369,12 @@
*/
static void scsi_init_dev_desc_priv(struct blk_desc *dev_desc)
{
+ memset(dev_desc, 0, sizeof(struct blk_desc));
dev_desc->target = 0xff;
dev_desc->lun = 0xff;
dev_desc->log2blksz =
LOG2_INVALID(typeof(dev_desc->log2blksz));
dev_desc->type = DEV_TYPE_UNKNOWN;
- dev_desc->vendor[0] = 0;
- dev_desc->product[0] = 0;
- dev_desc->revision[0] = 0;
- dev_desc->removable = false;
#if IS_ENABLED(CONFIG_BOUNCE_BUFFER)
dev_desc->bb = true;
#endif /* CONFIG_BOUNCE_BUFFER */
@@ -440,6 +438,7 @@
for (count = 0; count < 3; count++) {
pccb->datalen = 0;
+ pccb->dma_dir = DMA_NONE;
scsi_setup_test_unit_ready(pccb);
err = scsi_exec(dev, pccb);
if (!err)
diff --git a/drivers/serial/Kconfig b/drivers/serial/Kconfig
index 9f0f84c..6628a88 100644
--- a/drivers/serial/Kconfig
+++ b/drivers/serial/Kconfig
@@ -24,6 +24,21 @@
in the SPL stage (most drivers) or for choosing a default baudrate
in the absence of an environment setting (serial_mxc.c).
+config OF_SERIAL_BAUD
+ bool "Fetch serial baudrate from device tree"
+ depends on DM_SERIAL && SPL_ENV_SUPPORT
+ select DEFAULT_ENV_IS_RW
+ help
+ Select this to enable fetching and setting of the baudrate
+ configured in the DT. Replace the default baudrate with the DT
+ baudrate and also set it to the environment.
+
+config DEFAULT_ENV_IS_RW
+ bool "Make default environment as writable"
+ help
+ Select this to enable to make default environment writable. This
+ allows modifying the default environment.
+
config REQUIRE_SERIAL_CONSOLE
bool "Require a serial port for console"
# Running without a serial console is not supported by the
diff --git a/drivers/serial/serial-uclass.c b/drivers/serial/serial-uclass.c
index df6a387..e4fa393 100644
--- a/drivers/serial/serial-uclass.c
+++ b/drivers/serial/serial-uclass.c
@@ -155,12 +155,61 @@
}
#endif /* CONFIG_SERIAL_PRESENT */
+/**
+ * check_valid_baudrate() - Check whether baudrate is valid or not
+ *
+ * @baud: baud rate to check
+ * Return: 0 if OK, -ve on error
+ */
+static int check_valid_baudrate(int baud)
+{
+ int i;
+
+ for (i = 0; i < ARRAY_SIZE(baudrate_table); ++i) {
+ if (baud == baudrate_table[i])
+ return 0;
+ }
+
+ return -EINVAL;
+}
+
+int fetch_baud_from_dtb(void)
+{
+ int baud_value, ret;
+
+ baud_value = ofnode_read_baud();
+ ret = check_valid_baudrate(baud_value);
+ if (ret)
+ return ret;
+
+ return baud_value;
+}
+
/* Called prior to relocation */
int serial_init(void)
{
#if CONFIG_IS_ENABLED(SERIAL_PRESENT)
serial_find_console_or_panic();
gd->flags |= GD_FLG_SERIAL_READY;
+
+ if (IS_ENABLED(CONFIG_OF_SERIAL_BAUD)) {
+ int ret = 0;
+ char *ptr = (char*)&default_environment[0];
+
+ /*
+ * Fetch the baudrate from the dtb and update the value in the
+ * default environment.
+ */
+ ret = fetch_baud_from_dtb();
+ if (ret != -EINVAL && ret != -EFAULT) {
+ gd->baudrate = ret;
+
+ while (*ptr != '\0' && *(ptr + 1) != '\0')
+ ptr++;
+ ptr += 2;
+ sprintf(ptr, "baudrate=%d", gd->baudrate);
+ }
+ }
serial_setbrg();
#endif
diff --git a/drivers/serial/serial_msm_geni.c b/drivers/serial/serial_msm_geni.c
index 78fd938..b8bc614 100644
--- a/drivers/serial/serial_msm_geni.c
+++ b/drivers/serial/serial_msm_geni.c
@@ -13,14 +13,13 @@
#include <dm.h>
#include <errno.h>
#include <linux/delay.h>
+#include <linux/time.h>
#include <misc.h>
#include <serial.h>
#define UART_OVERSAMPLING 32
#define STALE_TIMEOUT 160
-#define USEC_PER_SEC 1000000L
-
/* Registers*/
#define GENI_FORCE_DEFAULT_REG 0x20
#define GENI_SER_M_CLK_CFG 0x48
diff --git a/drivers/serial/serial_npcm.c b/drivers/serial/serial_npcm.c
index 76ac7cb..6bf3a94 100644
--- a/drivers/serial/serial_npcm.c
+++ b/drivers/serial/serial_npcm.c
@@ -83,8 +83,11 @@
struct npcm_uart *uart = plat->reg;
u16 divisor;
+ if (IS_ENABLED(CONFIG_SYS_SKIP_UART_INIT))
+ return 0;
+
/* BaudOut = UART Clock / (16 * [Divisor + 2]) */
- divisor = DIV_ROUND_CLOSEST(plat->uart_clk, 16 * baudrate + 2) - 2;
+ divisor = DIV_ROUND_CLOSEST(plat->uart_clk, 16 * baudrate) - 2;
setbits_8(&uart->lcr, LCR_DLAB);
writeb(divisor & 0xff, &uart->dll);
@@ -97,29 +100,35 @@
static int npcm_serial_probe(struct udevice *dev)
{
struct npcm_serial_plat *plat = dev_get_plat(dev);
- struct npcm_uart *uart = plat->reg;
+ struct npcm_uart *uart;
struct clk clk, parent;
u32 freq;
int ret;
plat->reg = dev_read_addr_ptr(dev);
- freq = dev_read_u32_default(dev, "clock-frequency", 0);
+ uart = plat->reg;
- ret = clk_get_by_index(dev, 0, &clk);
- if (ret < 0)
- return ret;
+ if (!IS_ENABLED(CONFIG_SYS_SKIP_UART_INIT)) {
+ freq = dev_read_u32_default(dev, "clock-frequency", 24000000);
- ret = clk_get_by_index(dev, 1, &parent);
- if (!ret) {
- ret = clk_set_parent(&clk, &parent);
- if (ret)
+ ret = clk_get_by_index(dev, 0, &clk);
+ if (ret < 0)
return ret;
- }
- ret = clk_set_rate(&clk, freq);
- if (ret < 0)
- return ret;
- plat->uart_clk = ret;
+ ret = clk_get_by_index(dev, 1, &parent);
+ if (!ret) {
+ ret = clk_set_parent(&clk, &parent);
+ if (ret)
+ return ret;
+ }
+
+ if (freq) {
+ ret = clk_set_rate(&clk, freq);
+ if (ret < 0)
+ return ret;
+ }
+ plat->uart_clk = clk_get_rate(&clk);
+ }
/* Disable all interrupt */
writeb(0, &uart->ier);
diff --git a/drivers/serial/serial_omap.c b/drivers/serial/serial_omap.c
index 26310b0..49ced8f 100644
--- a/drivers/serial/serial_omap.c
+++ b/drivers/serial/serial_omap.c
@@ -2,7 +2,7 @@
/*
* Texas Instruments' OMAP serial driver
*
- * Copyright (C) 2018 Texas Instruments Incorporated - http://www.ti.com/
+ * Copyright (C) 2018 Texas Instruments Incorporated - https://www.ti.com/
* Lokesh Vutla <lokeshvutla@ti.com>
*/
diff --git a/drivers/serial/serial_s5p.c b/drivers/serial/serial_s5p.c
index 7aeb8c0..7d04dcf 100644
--- a/drivers/serial/serial_s5p.c
+++ b/drivers/serial/serial_s5p.c
@@ -7,7 +7,6 @@
* based on drivers/serial/s3c64xx.c
*/
-#include <common.h>
#include <dm.h>
#include <errno.h>
#include <fdtdec.h>
@@ -21,32 +20,39 @@
#include <serial.h>
#include <clk.h>
-DECLARE_GLOBAL_DATA_PTR;
-
enum {
PORT_S5P = 0,
PORT_S5L
};
+#define UFCON_FIFO_EN BIT(0)
+#define UFCON_RX_FIFO_RESET BIT(1)
+#define UMCON_RESET_VAL 0x0
+#define ULCON_WORD_8_BIT 0x3
+#define UCON_RX_IRQ_OR_POLLING BIT(0)
+#define UCON_TX_IRQ_OR_POLLING BIT(2)
+#define UCON_RX_ERR_IRQ_EN BIT(6)
+#define UCON_TX_IRQ_LEVEL BIT(9)
+
#define S5L_RX_FIFO_COUNT_SHIFT 0
#define S5L_RX_FIFO_COUNT_MASK (0xf << S5L_RX_FIFO_COUNT_SHIFT)
-#define S5L_RX_FIFO_FULL (1 << 8)
+#define S5L_RX_FIFO_FULL BIT(8)
#define S5L_TX_FIFO_COUNT_SHIFT 4
#define S5L_TX_FIFO_COUNT_MASK (0xf << S5L_TX_FIFO_COUNT_SHIFT)
-#define S5L_TX_FIFO_FULL (1 << 9)
+#define S5L_TX_FIFO_FULL BIT(9)
#define S5P_RX_FIFO_COUNT_SHIFT 0
#define S5P_RX_FIFO_COUNT_MASK (0xff << S5P_RX_FIFO_COUNT_SHIFT)
-#define S5P_RX_FIFO_FULL (1 << 8)
+#define S5P_RX_FIFO_FULL BIT(8)
#define S5P_TX_FIFO_COUNT_SHIFT 16
#define S5P_TX_FIFO_COUNT_MASK (0xff << S5P_TX_FIFO_COUNT_SHIFT)
-#define S5P_TX_FIFO_FULL (1 << 24)
+#define S5P_TX_FIFO_FULL BIT(24)
/* Information about a serial port */
struct s5p_serial_plat {
- struct s5p_uart *reg; /* address of registers in physical memory */
- u8 reg_width; /* register width */
- u8 port_id; /* uart port number */
+ struct s5p_uart *reg; /* address of registers in physical memory */
+ u8 reg_width; /* register width */
+ u8 port_id; /* uart port number */
u8 rx_fifo_count_shift;
u8 tx_fifo_count_shift;
u32 rx_fifo_count_mask;
@@ -59,7 +65,7 @@
* The coefficient, used to calculate the baudrate on S5P UARTs is
* calculated as
* C = UBRDIV * 16 + number_of_set_bits_in_UDIVSLOT
- * however, section 31.6.11 of the datasheet doesn't recomment using 1 for 1,
+ * however, section 31.6.11 of the datasheet doesn't recommend using 1 for 1,
* 3 for 2, ... (2^n - 1) for n, instead, they suggest using these constants:
*/
static const int udivslot[] = {
@@ -83,13 +89,15 @@
static void __maybe_unused s5p_serial_init(struct s5p_uart *uart)
{
- /* enable FIFOs, auto clear Rx FIFO */
- writel(0x3, &uart->ufcon);
- writel(0, &uart->umcon);
- /* 8N1 */
- writel(0x3, &uart->ulcon);
+ /* Enable FIFOs, auto clear Rx FIFO */
+ writel(UFCON_FIFO_EN | UFCON_RX_FIFO_RESET, &uart->ufcon);
+ /* No auto flow control, disable nRTS signal */
+ writel(UMCON_RESET_VAL, &uart->umcon);
+ /* 8N1, no parity bit */
+ writel(ULCON_WORD_8_BIT, &uart->ulcon);
/* No interrupts, no DMA, pure polling */
- writel(0x245, &uart->ucon);
+ writel(UCON_RX_IRQ_OR_POLLING | UCON_TX_IRQ_OR_POLLING |
+ UCON_RX_ERR_IRQ_EN | UCON_TX_IRQ_LEVEL, &uart->ucon);
}
static void __maybe_unused s5p_serial_baud(struct s5p_uart *uart, u8 reg_width,
@@ -118,7 +126,7 @@
#if IS_ENABLED(CONFIG_CLK_EXYNOS) || IS_ENABLED(CONFIG_ARCH_APPLE)
struct clk clk;
- u32 ret;
+ int ret;
ret = clk_get_by_index(dev, 1, &clk);
if (ret < 0)
@@ -213,16 +221,13 @@
{
struct s5p_serial_plat *plat = dev_get_plat(dev);
const ulong port_type = dev_get_driver_data(dev);
- fdt_addr_t addr;
- addr = dev_read_addr(dev);
- if (addr == FDT_ADDR_T_NONE)
+ plat->reg = dev_read_addr_ptr(dev);
+ if (!plat->reg)
return -EINVAL;
- plat->reg = (struct s5p_uart *)addr;
plat->reg_width = dev_read_u32_default(dev, "reg-io-width", 1);
- plat->port_id = fdtdec_get_int(gd->fdt_blob, dev_of_offset(dev),
- "id", dev_seq(dev));
+ plat->port_id = dev_read_u8_default(dev, "id", dev_seq(dev));
if (port_type == PORT_S5L) {
plat->rx_fifo_count_shift = S5L_RX_FIFO_COUNT_SHIFT;
@@ -244,10 +249,10 @@
}
static const struct dm_serial_ops s5p_serial_ops = {
- .putc = s5p_serial_putc,
- .pending = s5p_serial_pending,
- .getc = s5p_serial_getc,
- .setbrg = s5p_serial_setbrg,
+ .putc = s5p_serial_putc,
+ .pending = s5p_serial_pending,
+ .getc = s5p_serial_getc,
+ .setbrg = s5p_serial_setbrg,
};
static const struct udevice_id s5p_serial_ids[] = {
@@ -257,13 +262,13 @@
};
U_BOOT_DRIVER(serial_s5p) = {
- .name = "serial_s5p",
- .id = UCLASS_SERIAL,
- .of_match = s5p_serial_ids,
- .of_to_plat = s5p_serial_of_to_plat,
+ .name = "serial_s5p",
+ .id = UCLASS_SERIAL,
+ .of_match = s5p_serial_ids,
+ .of_to_plat = s5p_serial_of_to_plat,
.plat_auto = sizeof(struct s5p_serial_plat),
- .probe = s5p_serial_probe,
- .ops = &s5p_serial_ops,
+ .probe = s5p_serial_probe,
+ .ops = &s5p_serial_ops,
};
#endif
@@ -291,10 +296,12 @@
struct s5p_uart *uart = (struct s5p_uart *)CONFIG_VAL(DEBUG_UART_BASE);
#if IS_ENABLED(CONFIG_ARCH_APPLE)
- while (readl(&uart->ufstat) & S5L_TX_FIFO_FULL);
+ while (readl(&uart->ufstat) & S5L_TX_FIFO_FULL)
+ ;
writel(ch, &uart->utxh);
#else
- while (readl(&uart->ufstat) & S5P_TX_FIFO_FULL);
+ while (readl(&uart->ufstat) & S5P_TX_FIFO_FULL)
+ ;
writeb(ch, &uart->utxh);
#endif
}
diff --git a/drivers/soc/soc-uclass.c b/drivers/soc/soc-uclass.c
index dfad32d..8b3044f 100644
--- a/drivers/soc/soc-uclass.c
+++ b/drivers/soc/soc-uclass.c
@@ -1,6 +1,6 @@
// SPDX-License-Identifier: GPL-2.0+
/*
- * (C) Copyright 2020 - Texas Instruments Incorporated - http://www.ti.com/
+ * (C) Copyright 2020 - Texas Instruments Incorporated - https://www.ti.com/
* Dave Gerlach <d-gerlach@ti.com>
*/
diff --git a/drivers/soc/soc_sandbox.c b/drivers/soc/soc_sandbox.c
index 5c82ad8..15fdd99 100644
--- a/drivers/soc/soc_sandbox.c
+++ b/drivers/soc/soc_sandbox.c
@@ -2,7 +2,7 @@
/*
* Sandbox driver for the SOC uclass
*
- * (C) Copyright 2020 - Texas Instruments Incorporated - http://www.ti.com/
+ * (C) Copyright 2020 - Texas Instruments Incorporated - https://www.ti.com/
* Dave Gerlach <d-gerlach@ti.com>
*/
diff --git a/drivers/soc/soc_ti_k3.c b/drivers/soc/soc_ti_k3.c
index b720131..355a536 100644
--- a/drivers/soc/soc_ti_k3.c
+++ b/drivers/soc/soc_ti_k3.c
@@ -1,6 +1,6 @@
// SPDX-License-Identifier: GPL-2.0+
/*
- * Copyright (C) 2020 Texas Instruments Incorporated - http://www.ti.com/
+ * Copyright (C) 2020 Texas Instruments Incorporated - https://www.ti.com/
* Dave Gerlach <d-gerlach@ti.com>
*/
diff --git a/drivers/soc/ti/k3-navss-ringacc.c b/drivers/soc/ti/k3-navss-ringacc.c
index e028896..7a2fbb0 100644
--- a/drivers/soc/ti/k3-navss-ringacc.c
+++ b/drivers/soc/ti/k3-navss-ringacc.c
@@ -2,7 +2,7 @@
/*
* TI K3 AM65x NAVSS Ring accelerator Manager (RA) subsystem driver
*
- * Copyright (C) 2018 Texas Instruments Incorporated - http://www.ti.com
+ * Copyright (C) 2018 Texas Instruments Incorporated - https://www.ti.com
*/
#include <common.h>
diff --git a/drivers/soc/ti/keystone_serdes.c b/drivers/soc/ti/keystone_serdes.c
index 2ece1a8..0e1bf8f 100644
--- a/drivers/soc/ti/keystone_serdes.c
+++ b/drivers/soc/ti/keystone_serdes.c
@@ -8,6 +8,7 @@
#include <errno.h>
#include <common.h>
+#include <asm/io.h>
#include <asm/ti-common/keystone_serdes.h>
#include <linux/bitops.h>
diff --git a/drivers/spi/cadence_ospi_versal.c b/drivers/spi/cadence_ospi_versal.c
index a7685a2..e02a3b3 100644
--- a/drivers/spi/cadence_ospi_versal.c
+++ b/drivers/spi/cadence_ospi_versal.c
@@ -44,8 +44,10 @@
priv->regbase + CQSPI_REG_INDIR_TRIG_ADDR_RANGE);
writel(CQSPI_DFLT_DMA_PERIPH_CFG,
priv->regbase + CQSPI_REG_DMA_PERIPH_CFG);
- writel((unsigned long)rxbuf, priv->regbase +
+ writel(lower_32_bits((unsigned long)rxbuf), priv->regbase +
CQSPI_DMA_DST_ADDR_REG);
+ writel(upper_32_bits((unsigned long)rxbuf), priv->regbase +
+ CQSPI_DMA_DST_ADDR_MSB_REG);
writel(priv->trigger_address, priv->regbase +
CQSPI_DMA_SRC_RD_ADDR_REG);
writel(bytes_to_dma, priv->regbase +
diff --git a/drivers/spi/cadence_qspi.c b/drivers/spi/cadence_qspi.c
index cc3a54f..2efd626 100644
--- a/drivers/spi/cadence_qspi.c
+++ b/drivers/spi/cadence_qspi.c
@@ -7,7 +7,6 @@
#include <common.h>
#include <clk.h>
#include <log.h>
-#include <asm-generic/io.h>
#include <dm.h>
#include <fdtdec.h>
#include <malloc.h>
@@ -17,13 +16,13 @@
#include <dm/device_compat.h>
#include <linux/err.h>
#include <linux/errno.h>
+#include <linux/io.h>
#include <linux/sizes.h>
+#include <linux/time.h>
#include <zynqmp_firmware.h>
#include "cadence_qspi.h"
#include <dt-bindings/power/xlnx-versal-power.h>
-#define NSEC_PER_SEC 1000000000L
-
#define CQSPI_STIG_READ 0
#define CQSPI_STIG_WRITE 1
#define CQSPI_READ 2
diff --git a/drivers/spi/davinci_spi.c b/drivers/spi/davinci_spi.c
index 9ebc4ed..25f5e9f 100644
--- a/drivers/spi/davinci_spi.c
+++ b/drivers/spi/davinci_spi.c
@@ -1,6 +1,6 @@
// SPDX-License-Identifier: GPL-2.0+
/*
- * Copyright (C) 2009 Texas Instruments Incorporated - http://www.ti.com/
+ * Copyright (C) 2009 Texas Instruments Incorporated - https://www.ti.com/
*
* Driver for SPI controller on DaVinci. Based on atmel_spi.c
* by Atmel Corporation
diff --git a/drivers/spi/fsl_dspi.c b/drivers/spi/fsl_dspi.c
index f8ec268..89907cb 100644
--- a/drivers/spi/fsl_dspi.c
+++ b/drivers/spi/fsl_dspi.c
@@ -27,9 +27,7 @@
#include <linux/bitops.h>
#include <linux/delay.h>
#include <linux/printk.h>
-
-/* linux/include/time.h */
-#define NSEC_PER_SEC 1000000000L
+#include <linux/time.h>
DECLARE_GLOBAL_DATA_PTR;
diff --git a/drivers/spi/meson_spifc_a1.c b/drivers/spi/meson_spifc_a1.c
index 099c4c0..cca4deb 100644
--- a/drivers/spi/meson_spifc_a1.c
+++ b/drivers/spi/meson_spifc_a1.c
@@ -16,6 +16,7 @@
#include <spi-mem.h>
#include <asm/io.h>
#include <linux/log2.h>
+#include <linux/time.h>
#include <linux/iopoll.h>
#include <linux/bitfield.h>
@@ -117,7 +118,7 @@
return readl_poll_timeout(spifc->base + SPIFC_A1_USER_CTRL0_REG,
val, (val & mask) == mask,
- 200 * 1000);
+ 200 * USEC_PER_MSEC);
}
static void amlogic_spifc_a1_drain_buffer(struct amlogic_spifc_a1 *spifc,
@@ -129,7 +130,7 @@
writel(SPIFC_A1_DBUF_AUTO_UPDATE_ADDR,
spifc->base + SPIFC_A1_DBUF_CTRL_REG);
- readsl(spifc->base + SPIFC_A1_DBUF_DATA_REG, buf, count);
+ ioread32_rep(spifc->base + SPIFC_A1_DBUF_DATA_REG, buf, count);
if (pad) {
data = readl(spifc->base + SPIFC_A1_DBUF_DATA_REG);
@@ -146,7 +147,7 @@
writel(SPIFC_A1_DBUF_DIR | SPIFC_A1_DBUF_AUTO_UPDATE_ADDR,
spifc->base + SPIFC_A1_DBUF_CTRL_REG);
- writesl(spifc->base + SPIFC_A1_DBUF_DATA_REG, buf, count);
+ iowrite32_rep(spifc->base + SPIFC_A1_DBUF_DATA_REG, buf, count);
if (pad) {
memcpy(&data, buf + len - pad, pad);
diff --git a/drivers/spi/omap3_spi.c b/drivers/spi/omap3_spi.c
index ff7b55f..5cce6ba 100644
--- a/drivers/spi/omap3_spi.c
+++ b/drivers/spi/omap3_spi.c
@@ -6,7 +6,7 @@
* Copyright (C) 2010 Dirk Behme <dirk.behme@googlemail.com>
*
* Driver for McSPI controller on OMAP3. Based on davinci_spi.c
- * Copyright (C) 2009 Texas Instruments Incorporated - http://www.ti.com/
+ * Copyright (C) 2009 Texas Instruments Incorporated - https://www.ti.com/
*
* Copyright (C) 2007 Atmel Corporation
*
diff --git a/drivers/spi/spi-mem-nodm.c b/drivers/spi/spi-mem-nodm.c
index f9cadcc..6d9ab61 100644
--- a/drivers/spi/spi-mem-nodm.c
+++ b/drivers/spi/spi-mem-nodm.c
@@ -1,6 +1,6 @@
// SPDX-License-Identifier: GPL-2.0+
/*
- * Copyright (C) 2018 Texas Instruments Incorporated - http://www.ti.com/
+ * Copyright (C) 2018 Texas Instruments Incorporated - https://www.ti.com/
*/
#include <errno.h>
diff --git a/drivers/spi/zynqmp_gqspi.c b/drivers/spi/zynqmp_gqspi.c
index ec59ef58..a323994 100644
--- a/drivers/spi/zynqmp_gqspi.c
+++ b/drivers/spi/zynqmp_gqspi.c
@@ -5,6 +5,8 @@
* Xilinx ZynqMP Generic Quad-SPI(QSPI) controller driver(master mode only)
*/
+#define LOG_CATEGORY UCLASS_SPI
+
#include <common.h>
#include <cpu_func.h>
#include <log.h>
@@ -192,8 +194,6 @@
{
struct zynqmp_qspi_plat *plat = dev_get_plat(bus);
- debug("%s\n", __func__);
-
plat->regs = (struct zynqmp_qspi_regs *)(dev_read_addr(bus) +
GQSPI_REG_OFFSET);
plat->dma_regs = (struct zynqmp_qspi_dma_regs *)
@@ -250,7 +250,7 @@
case 4:
return GQSPI_SPI_MODE_QSPI;
default:
- debug("Unsupported bus width %u\n", buswidth);
+ log_warning("Unsupported bus width %u\n", buswidth);
return GQSPI_SPI_MODE_SPI;
}
}
@@ -262,6 +262,8 @@
u32 config_reg, ier;
int ret = 0;
+ log_content("%s, GFIFO_CMD: 0x%X\n", __func__, gqspi_fifo_reg);
+
writel(gqspi_fifo_reg, ®s->genfifo);
config_reg = readl(®s->confr);
@@ -278,7 +280,7 @@
ret = wait_for_bit_le32(®s->isr, GQSPI_IXR_GFEMTY_MASK, 1,
GQSPI_TIMEOUT, 1);
if (ret)
- printf("%s Timeout\n", __func__);
+ log_warning("%s, Timeout\n", __func__);
}
@@ -286,6 +288,8 @@
{
u32 gqspi_fifo_reg = 0;
+ log_debug("%s, assert: %d\r\n", __func__, is_on);
+
if (is_on) {
gqspi_fifo_reg = zynqmp_qspi_bus_select(priv);
gqspi_fifo_reg |= GQSPI_SPI_MODE_SPI |
@@ -295,8 +299,6 @@
gqspi_fifo_reg |= GQSPI_IMD_DATA_CS_DEASSERT;
}
- debug("GFIFO_CMD_CS: 0x%x\n", gqspi_fifo_reg);
-
zynqmp_qspi_fill_gen_fifo(priv, gqspi_fifo_reg);
}
@@ -311,8 +313,8 @@
clk_rate = plat->frequency;
reqhz = (clk_rate / (GQSPI_BAUD_DIV_SHIFT << baudrateval));
- debug("%s, req_hz:%d, clk_rate:%d, baudrateval:%d\n",
- __func__, reqhz, clk_rate, baudrateval);
+ log_debug("%s, clk_rate:%d, baudrateval:%d, bus_clk: %d\n",
+ __func__, clk_rate, baudrateval, reqhz);
if (!(IS_ENABLED(CONFIG_ARCH_VERSAL) ||
IS_ENABLED(CONFIG_ARCH_VERSAL_NET))) {
@@ -362,7 +364,8 @@
u32 confr;
u8 baud_rate_val = 0;
+ log_debug("%s, Speed: %d, Max: %d\n", __func__, speed, plat->frequency);
+
- debug("%s\n", __func__);
if (speed > plat->frequency)
speed = plat->frequency;
@@ -383,9 +386,8 @@
confr &= ~GQSPI_BAUD_DIV_MASK;
confr |= (baud_rate_val << 3);
writel(confr, ®s->confr);
- zynqmp_qspi_set_tapdelay(bus, baud_rate_val);
- debug("regs=%p, speed=%d\n", priv->regs, plat->speed_hz);
+ zynqmp_qspi_set_tapdelay(bus, baud_rate_val);
}
return 0;
@@ -399,8 +401,6 @@
unsigned long clock;
int ret;
- debug("%s: bus:%p, priv:%p\n", __func__, bus, priv);
-
priv->regs = plat->regs;
priv->dma_regs = plat->dma_regs;
priv->io_mode = plat->io_mode;
@@ -416,7 +416,6 @@
dev_err(bus, "failed to get rate\n");
return clock;
}
- debug("%s: CLK %ld\n", __func__, clock);
ret = clk_enable(&clk);
if (ret) {
@@ -429,6 +428,8 @@
/* init the zynq spi hw */
zynqmp_qspi_init_hw(priv);
+ log_debug("%s, Rerence clock frequency: %ld\n", __func__, clock);
+
return 0;
}
@@ -438,7 +439,8 @@
struct zynqmp_qspi_regs *regs = priv->regs;
u32 confr;
- debug("%s\n", __func__);
+ log_debug("%s, 0x%X\n", __func__, mode);
+
/* Set the SPI Clock phase and polarities */
confr = readl(®s->confr);
confr &= ~(GQSPI_CONFIG_CPHA_MASK | GQSPI_CONFIG_CPOL_MASK);
@@ -461,16 +463,11 @@
u32 *buf = (u32 *)priv->tx_buf;
u32 len = size;
- debug("TxFIFO: 0x%x, size: 0x%x\n", readl(®s->isr),
- size);
-
while (size) {
ret = wait_for_bit_le32(®s->isr, GQSPI_IXR_TXNFULL_MASK, 1,
GQSPI_TIMEOUT, 1);
- if (ret) {
- printf("%s: Timeout\n", __func__);
- return ret;
- }
+ if (ret)
+ return log_msg_ret("Timeout\n", ret);
if (size >= 4) {
writel(*buf, ®s->txd0r);
@@ -501,10 +498,8 @@
ret = wait_for_bit_le32(®s->isr, GQSPI_IXR_TXFIFOEMPTY_MASK, 1,
GQSPI_TIMEOUT, 1);
- if (ret) {
- printf("%s: Timeout\n", __func__);
- return ret;
- }
+ if (ret)
+ return log_msg_ret("Timeout\n", ret);
priv->tx_buf += len;
return 0;
@@ -516,6 +511,9 @@
u32 gen_fifo_cmd;
u8 i, dummy_cycles, addr;
+ log_debug("%s, opcode: 0x%0X, addr.nbytes: %d, dummy.mbytes: %d\r\n",
+ __func__, op->cmd.opcode, op->addr.nbytes, op->dummy.nbytes);
+
/* Send opcode */
gen_fifo_cmd = zynqmp_qspi_bus_select(priv);
gen_fifo_cmd |= zynqmp_qspi_genfifo_mode(op->cmd.buswidth);
@@ -532,8 +530,6 @@
gen_fifo_cmd |= GQSPI_GFIFO_TX;
gen_fifo_cmd |= addr;
- debug("GFIFO_CMD_Cmd = 0x%x\n", gen_fifo_cmd);
-
zynqmp_qspi_fill_gen_fifo(priv, gen_fifo_cmd);
}
@@ -583,6 +579,8 @@
u32 len;
int ret = 0;
+ log_debug("%s, length: %d\r\n", __func__, priv->len);
+
gen_fifo_cmd = zynqmp_qspi_bus_select(priv);
gen_fifo_cmd |= zynqmp_qspi_genfifo_mode(priv->op->data.buswidth);
gen_fifo_cmd |= GQSPI_GFIFO_TX | GQSPI_GFIFO_DATA_XFR_MASK;
@@ -591,8 +589,6 @@
len = zynqmp_qspi_calc_exp(priv, &gen_fifo_cmd);
zynqmp_qspi_fill_gen_fifo(priv, gen_fifo_cmd);
- debug("GFIFO_CMD_TX:0x%x\n", gen_fifo_cmd);
-
if (gen_fifo_cmd & GQSPI_GFIFO_EXP_MASK)
ret = zynqmp_qspi_fill_tx_fifo(priv, 1 << len);
else
@@ -608,7 +604,6 @@
u32 gen_fifo_cmd, u32 *buf)
{
u32 len;
- u32 actuallen = priv->len;
u32 config_reg, ier, isr;
u32 timeout = GQSPI_TIMEOUT;
struct zynqmp_qspi_regs *regs = priv->regs;
@@ -623,7 +618,7 @@
else
priv->bytes_to_receive = len;
zynqmp_qspi_fill_gen_fifo(priv, gen_fifo_cmd);
- debug("GFIFO_CMD_RX:0x%x\n", gen_fifo_cmd);
+
/* Manual start */
config_reg = readl(®s->confr);
config_reg |= GQSPI_STRT_GEN_FIFO;
@@ -652,13 +647,8 @@
}
}
- debug("buf:0x%lx, rxbuf:0x%lx, *buf:0x%x len: 0x%x\n",
- (unsigned long)buf, (unsigned long)priv->rx_buf,
- *buf, actuallen);
- if (!timeout) {
- printf("IO timeout: %d\n", readl(®s->isr));
- return -1;
- }
+ if (!timeout)
+ return log_msg_retz("Timeout\n", timeout);
}
return 0;
@@ -695,26 +685,18 @@
while (priv->len) {
zynqmp_qspi_calc_exp(priv, &gen_fifo_cmd);
zynqmp_qspi_fill_gen_fifo(priv, gen_fifo_cmd);
-
- debug("GFIFO_CMD_RX:0x%x\n", gen_fifo_cmd);
}
ret = wait_for_bit_le32(&dma_regs->dmaisr,
GQSPI_DMA_DST_I_STS_DONE, 1,
GQSPI_TIMEOUT, 1);
- if (ret) {
- printf("DMA Timeout:0x%x\n", readl(&dma_regs->dmaisr));
- return -ETIMEDOUT;
- }
+ if (ret)
+ return log_msg_ret("Timeout:\n", ret);
invalidate_dcache_range(addr, addr + size);
writel(GQSPI_DMA_DST_I_STS_DONE, &dma_regs->dmaisr);
- debug("buf:0x%lx, rxbuf:0x%lx, *buf:0x%x len: 0x%x\n",
- (unsigned long)buf, (unsigned long)priv->rx_buf, *buf,
- actuallen);
-
if (buf != priv->rx_buf)
memcpy(priv->rx_buf, buf, actuallen);
@@ -731,6 +713,8 @@
u32 *buf;
u32 actuallen = priv->len;
+ log_debug("%s, length: %d\r\n", __func__, priv->len);
+
gen_fifo_cmd = zynqmp_qspi_bus_select(priv);
gen_fifo_cmd |= zynqmp_qspi_genfifo_mode(priv->op->data.buswidth);
gen_fifo_cmd |= GQSPI_GFIFO_RX | GQSPI_GFIFO_DATA_XFR_MASK;
diff --git a/drivers/sysinfo/Kconfig b/drivers/sysinfo/Kconfig
index e35f7cb..2030e4b 100644
--- a/drivers/sysinfo/Kconfig
+++ b/drivers/sysinfo/Kconfig
@@ -8,6 +8,13 @@
if SYSINFO
+config SYSINFO_EXTRA
+ bool "Show extra information on startup"
+ help
+ Enable this to see extra information on startup. Normally only the
+ model is shown, but with this option the vendor and any prior-stage
+ firmware's version and date are shown as well.
+
config SPL_SYSINFO
depends on SPL_DM
bool "Enable board driver support in SPL"
diff --git a/drivers/sysreset/poweroff_gpio.c b/drivers/sysreset/poweroff_gpio.c
index a5c24fd..ad04e4b 100644
--- a/drivers/sysreset/poweroff_gpio.c
+++ b/drivers/sysreset/poweroff_gpio.c
@@ -33,7 +33,7 @@
int r;
if (type != SYSRESET_POWER_OFF)
- return -ENOSYS;
+ return -EPROTONOSUPPORT;
debug("GPIO poweroff\n");
diff --git a/drivers/sysreset/sysreset-ti-sci.c b/drivers/sysreset/sysreset-ti-sci.c
index 81bfd67..5fc05c4 100644
--- a/drivers/sysreset/sysreset-ti-sci.c
+++ b/drivers/sysreset/sysreset-ti-sci.c
@@ -2,7 +2,7 @@
/*
* Texas Instruments System Control Interface (TI SCI) system reset driver
*
- * Copyright (C) 2018 Texas Instruments Incorporated - http://www.ti.com/
+ * Copyright (C) 2018 Texas Instruments Incorporated - https://www.ti.com/
* Andreas Dannenberg <dannenberg@ti.com>
*/
diff --git a/drivers/sysreset/sysreset_psci.c b/drivers/sysreset/sysreset_psci.c
index a8a4152..aa09d0b 100644
--- a/drivers/sysreset/sysreset_psci.c
+++ b/drivers/sysreset/sysreset_psci.c
@@ -25,7 +25,7 @@
psci_sys_poweroff();
break;
default:
- return -ENOSYS;
+ return -EPROTONOSUPPORT;
}
return -EINPROGRESS;
diff --git a/drivers/sysreset/sysreset_sandbox.c b/drivers/sysreset/sysreset_sandbox.c
index f485a13..c12eda8 100644
--- a/drivers/sysreset/sysreset_sandbox.c
+++ b/drivers/sysreset/sysreset_sandbox.c
@@ -21,7 +21,7 @@
state->last_sysreset = type;
break;
default:
- return -ENOSYS;
+ return -EPROTONOSUPPORT;
}
if (!state->sysreset_allowed[type])
return -EACCES;
@@ -70,7 +70,7 @@
return -EACCES;
sandbox_exit();
default:
- return -ENOSYS;
+ return -EPROTONOSUPPORT;
}
if (!state->sysreset_allowed[type])
return -EACCES;
diff --git a/drivers/sysreset/sysreset_watchdog.c b/drivers/sysreset/sysreset_watchdog.c
index ceada2e..6db5aa7 100644
--- a/drivers/sysreset/sysreset_watchdog.c
+++ b/drivers/sysreset/sysreset_watchdog.c
@@ -29,7 +29,7 @@
return ret;
break;
default:
- return -ENOSYS;
+ return -EPROTONOSUPPORT;
}
return -EINPROGRESS;
diff --git a/drivers/sysreset/sysreset_x86.c b/drivers/sysreset/sysreset_x86.c
index 4936fdb..dc772b5 100644
--- a/drivers/sysreset/sysreset_x86.c
+++ b/drivers/sysreset/sysreset_x86.c
@@ -87,7 +87,7 @@
return ret;
return -EINPROGRESS;
default:
- return -ENOSYS;
+ return -EPROTONOSUPPORT;
}
outb(value, IO_PORT_RESET);
diff --git a/drivers/thermal/ti-bandgap.c b/drivers/thermal/ti-bandgap.c
index 0b533d4..0ea17a9 100644
--- a/drivers/thermal/ti-bandgap.c
+++ b/drivers/thermal/ti-bandgap.c
@@ -1,7 +1,7 @@
/*
* TI Bandgap temperature sensor driver
*
- * Copyright (C) 2017 Texas Instruments Incorporated - http://www.ti.com/
+ * Copyright (C) 2017 Texas Instruments Incorporated - https://www.ti.com/
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
diff --git a/drivers/timer/timer-uclass.c b/drivers/timer/timer-uclass.c
index 0c2018b..60ff655 100644
--- a/drivers/timer/timer-uclass.c
+++ b/drivers/timer/timer-uclass.c
@@ -66,13 +66,13 @@
err = clk_get_by_index(dev, 0, &timer_clk);
if (!err) {
ret = clk_get_rate(&timer_clk);
- if (IS_ERR_VALUE(ret))
- return ret;
- uc_priv->clock_rate = ret;
- } else {
- uc_priv->clock_rate =
- dev_read_u32_default(dev, "clock-frequency", 0);
+ if (!IS_ERR_VALUE(ret)) {
+ uc_priv->clock_rate = ret;
+ return 0;
+ }
}
+
+ uc_priv->clock_rate = dev_read_u32_default(dev, "clock-frequency", 0);
}
return 0;
diff --git a/drivers/tpm/tpm2_tis_core.c b/drivers/tpm/tpm2_tis_core.c
index 985a816..81b9210 100644
--- a/drivers/tpm/tpm2_tis_core.c
+++ b/drivers/tpm/tpm2_tis_core.c
@@ -224,9 +224,6 @@
u8 status;
int ret;
- if (!chip)
- return -ENODEV;
-
ret = tpm_tis_request_locality(dev, 0);
if (ret < 0)
return -EBUSY;
diff --git a/drivers/ufs/Kconfig b/drivers/ufs/Kconfig
index ee021c7..7da46fa 100644
--- a/drivers/ufs/Kconfig
+++ b/drivers/ufs/Kconfig
@@ -15,6 +15,17 @@
This selects the platform driver for the Cadence UFS host
controller present on present TI's J721e devices.
+config UFS_PCI
+ bool "PCI bus based UFS Controller support"
+ depends on PCI && UFS
+ help
+ This selects the PCI UFS Host Controller Interface. Select this if
+ you have UFS Host Controller with PCI Interface.
+
+ If you have a controller with this interface, say Y here.
+
+ If unsure, say N.
+
config TI_J721E_UFS
bool "Glue Layer driver for UFS on TI J721E devices"
help
diff --git a/drivers/ufs/Makefile b/drivers/ufs/Makefile
index 4f3344f..67c4262 100644
--- a/drivers/ufs/Makefile
+++ b/drivers/ufs/Makefile
@@ -1,9 +1,10 @@
# SPDX-License-Identifier: GPL-2.0
#
-# Copyright (C) 2019 Texas Instruments Incorporated - http://www.ti.com
+# Copyright (C) 2019 Texas Instruments Incorporated - https://www.ti.com
#
obj-$(CONFIG_UFS) += ufs.o ufs-uclass.o
obj-$(CONFIG_CADENCE_UFS) += cdns-platform.o
obj-$(CONFIG_TI_J721E_UFS) += ti-j721e-ufs.o
+obj-$(CONFIG_UFS_PCI) += ufs-pci.o
obj-$(CONFIG_UFS_RENESAS) += ufs-renesas.o
diff --git a/drivers/ufs/cdns-platform.c b/drivers/ufs/cdns-platform.c
index 1e62e25..d1f3469 100644
--- a/drivers/ufs/cdns-platform.c
+++ b/drivers/ufs/cdns-platform.c
@@ -2,7 +2,7 @@
/**
* cdns-platform.c - Platform driver for Cadence UFSHCI device
*
- * Copyright (C) 2019 Texas Instruments Incorporated - http://www.ti.com
+ * Copyright (C) 2019 Texas Instruments Incorporated - https://www.ti.com
*/
#include <clk.h>
@@ -13,11 +13,10 @@
#include <dm/device_compat.h>
#include <linux/bitops.h>
#include <linux/err.h>
+#include <linux/time.h>
#include "ufs.h"
-#define USEC_PER_SEC 1000000L
-
#define CDNS_UFS_REG_HCLKDIV 0xFC
#define CDNS_UFS_REG_PHY_XCFGD1 0x113C
diff --git a/drivers/ufs/ti-j721e-ufs.c b/drivers/ufs/ti-j721e-ufs.c
index d875269..1860e0d 100644
--- a/drivers/ufs/ti-j721e-ufs.c
+++ b/drivers/ufs/ti-j721e-ufs.c
@@ -1,6 +1,6 @@
// SPDX-License-Identifier: GPL-2.0+
/*
- * Copyright (C) 2019 Texas Instruments Incorporated - http://www.ti.com/
+ * Copyright (C) 2019 Texas Instruments Incorporated - https://www.ti.com/
*/
#include <asm/io.h>
diff --git a/drivers/ufs/ufs-pci.c b/drivers/ufs/ufs-pci.c
new file mode 100644
index 0000000..ad41358
--- /dev/null
+++ b/drivers/ufs/ufs-pci.c
@@ -0,0 +1,45 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2023 tinylab.org
+ * Author: Bin Meng <bmeng@tinylab.org>
+ */
+
+#include <common.h>
+#include <dm.h>
+#include <errno.h>
+#include <pci.h>
+#include <ufs.h>
+#include <dm/device_compat.h>
+#include "ufs.h"
+
+static int ufs_pci_bind(struct udevice *dev)
+{
+ struct udevice *scsi_dev;
+
+ return ufs_scsi_bind(dev, &scsi_dev);
+}
+
+static int ufs_pci_probe(struct udevice *dev)
+{
+ int err;
+
+ err = ufshcd_probe(dev, NULL);
+ if (err)
+ dev_err(dev, "%s failed (ret=%d)\n", __func__, err);
+
+ return err;
+}
+
+U_BOOT_DRIVER(ufs_pci) = {
+ .name = "ufs_pci",
+ .id = UCLASS_UFS,
+ .bind = ufs_pci_bind,
+ .probe = ufs_pci_probe,
+};
+
+static struct pci_device_id ufs_supported[] = {
+ { PCI_DEVICE(PCI_VENDOR_ID_REDHAT, PCI_DEVICE_ID_REDHAT_UFS) },
+ {},
+};
+
+U_BOOT_PCI_DEVICE(ufs_pci, ufs_supported);
diff --git a/drivers/ufs/ufs-uclass.c b/drivers/ufs/ufs-uclass.c
index ceea30c..92fcdf4 100644
--- a/drivers/ufs/ufs-uclass.c
+++ b/drivers/ufs/ufs-uclass.c
@@ -1,8 +1,8 @@
// SPDX-License-Identifier: GPL-2.0
/**
- * ufs-uclass.c - Universal Flash Subsystem (UFS) Uclass driver
+ * ufs-uclass.c - Universal Flash Storage (UFS) Uclass driver
*
- * Copyright (C) 2019 Texas Instruments Incorporated - http://www.ti.com
+ * Copyright (C) 2019 Texas Instruments Incorporated - https://www.ti.com
*/
#define LOG_CATEGORY UCLASS_UFS
diff --git a/drivers/ufs/ufs.c b/drivers/ufs/ufs.c
index 7c48d57..e4400f3 100644
--- a/drivers/ufs/ufs.c
+++ b/drivers/ufs/ufs.c
@@ -1,11 +1,11 @@
// SPDX-License-Identifier: GPL-2.0+
/**
- * ufs.c - Universal Flash Subsystem (UFS) driver
+ * ufs.c - Universal Flash Storage (UFS) driver
*
* Taken from Linux Kernel v5.2 (drivers/scsi/ufs/ufshcd.c) and ported
* to u-boot.
*
- * Copyright (C) 2019 Texas Instruments Incorporated - http://www.ti.com
+ * Copyright (C) 2019 Texas Instruments Incorporated - https://www.ti.com
*/
#include <bouncebuf.h>
@@ -320,7 +320,7 @@
UIC_ARG_MPHY_TX_GEN_SEL_INDEX(i)),
0);
if (err) {
- dev_err(hba->dev, "%s: TX LCC Disable failed, peer = %d, lane = %d, err = %d",
+ dev_err(hba->dev, "%s: TX LCC Disable failed, peer = %d, lane = %d, err = %d\n",
__func__, peer, i, err);
break;
}
@@ -441,7 +441,7 @@
ufshcd_enable_run_stop_reg(hba);
} else {
dev_err(hba->dev,
- "Host controller not ready to process requests");
+ "Host controller not ready to process requests\n");
err = -EIO;
goto out;
}
@@ -930,7 +930,7 @@
memcpy(hba->dev_cmd.query.descriptor, descp, resp_len);
} else {
dev_warn(hba->dev,
- "%s: Response size is bigger than buffer",
+ "%s: Response size is bigger than buffer\n",
__func__);
return -EINVAL;
}
@@ -1179,11 +1179,11 @@
&header_len);
if (ret) {
- dev_err(hba->dev, "%s: Failed to get descriptor header id %d",
+ dev_err(hba->dev, "%s: Failed to get descriptor header id %d\n",
__func__, desc_id);
return ret;
} else if (desc_id != header[QUERY_DESC_DESC_TYPE_OFFSET]) {
- dev_warn(hba->dev, "%s: descriptor header id %d and desc_id %d mismatch",
+ dev_warn(hba->dev, "%s: descriptor header id %d and desc_id %d mismatch\n",
__func__, header[QUERY_DESC_DESC_TYPE_OFFSET],
desc_id);
ret = -EINVAL;
@@ -1302,7 +1302,7 @@
/* Sanity checks */
if (ret || !buff_len) {
- dev_err(hba->dev, "%s: Failed to get full descriptor length",
+ dev_err(hba->dev, "%s: Failed to get full descriptor length\n",
__func__);
return ret;
}
@@ -1323,14 +1323,14 @@
&buff_len);
if (ret) {
- dev_err(hba->dev, "%s: Failed reading descriptor. desc_id %d, desc_index %d, param_offset %d, ret %d",
+ dev_err(hba->dev, "%s: Failed reading descriptor. desc_id %d, desc_index %d, param_offset %d, ret %d\n",
__func__, desc_id, desc_index, param_offset, ret);
goto out;
}
/* Sanity check */
if (desc_buf[QUERY_DESC_DESC_TYPE_OFFSET] != desc_id) {
- dev_err(hba->dev, "%s: invalid desc_id %d in descriptor header",
+ dev_err(hba->dev, "%s: invalid desc_id %d in descriptor header\n",
__func__, desc_buf[QUERY_DESC_DESC_TYPE_OFFSET]);
ret = -EINVAL;
goto out;
@@ -1914,6 +1914,7 @@
struct ufs_hba *hba = dev_get_uclass_priv(ufs_dev);
struct scsi_plat *scsi_plat;
struct udevice *scsi_dev;
+ void __iomem *mmio_base;
int err;
device_find_first_child(ufs_dev, &scsi_dev);
@@ -1927,7 +1928,14 @@
hba->dev = ufs_dev;
hba->ops = hba_ops;
- hba->mmio_base = dev_read_addr_ptr(ufs_dev);
+
+ if (device_is_on_pci_bus(ufs_dev)) {
+ mmio_base = dm_pci_map_bar(ufs_dev, PCI_BASE_ADDRESS_0, 0, 0,
+ PCI_REGION_TYPE, PCI_REGION_MEM);
+ } else {
+ mmio_base = dev_read_addr_ptr(ufs_dev);
+ }
+ hba->mmio_base = mmio_base;
/* Set descriptor lengths to specification defaults */
ufshcd_def_desc_sizes(hba);
@@ -1945,7 +1953,8 @@
hba->version != UFSHCI_VERSION_11 &&
hba->version != UFSHCI_VERSION_20 &&
hba->version != UFSHCI_VERSION_21 &&
- hba->version != UFSHCI_VERSION_30)
+ hba->version != UFSHCI_VERSION_30 &&
+ hba->version != UFSHCI_VERSION_31)
dev_err(hba->dev, "invalid UFS version 0x%x\n",
hba->version);
diff --git a/drivers/ufs/ufs.h b/drivers/ufs/ufs.h
index 9daaf03..816a5ce 100644
--- a/drivers/ufs/ufs.h
+++ b/drivers/ufs/ufs.h
@@ -782,6 +782,7 @@
UFSHCI_VERSION_20 = 0x00000200, /* 2.0 */
UFSHCI_VERSION_21 = 0x00000210, /* 2.1 */
UFSHCI_VERSION_30 = 0x00000300, /* 3.0 */
+ UFSHCI_VERSION_31 = 0x00000310, /* 3.1 */
};
/* Interrupt disable masks */
diff --git a/drivers/usb/cdns3/cdns3-ti.c b/drivers/usb/cdns3/cdns3-ti.c
index 8958f01..2e44aad 100644
--- a/drivers/usb/cdns3/cdns3-ti.c
+++ b/drivers/usb/cdns3/cdns3-ti.c
@@ -2,11 +2,10 @@
/**
* cdns_ti-ti.c - TI specific Glue layer for Cadence USB Controller
*
- * Copyright (C) 2019 Texas Instruments Incorporated - http://www.ti.com
+ * Copyright (C) 2019 Texas Instruments Incorporated - https://www.ti.com
*/
#include <common.h>
-#include <asm-generic/io.h>
#include <clk.h>
#include <dm.h>
#include <dm/device_compat.h>
diff --git a/drivers/usb/dwc3/core.c b/drivers/usb/dwc3/core.c
index 7ca9d09..4b4fcd8 100644
--- a/drivers/usb/dwc3/core.c
+++ b/drivers/usb/dwc3/core.c
@@ -2,7 +2,7 @@
/**
* core.c - DesignWare USB3 DRD Controller Core file
*
- * Copyright (C) 2015 Texas Instruments Incorporated - http://www.ti.com
+ * Copyright (C) 2015 Texas Instruments Incorporated - https://www.ti.com
*
* Authors: Felipe Balbi <balbi@ti.com>,
* Sebastian Andrzej Siewior <bigeasy@linutronix.de>
@@ -31,6 +31,7 @@
#include <linux/usb/gadget.h>
#include <linux/bitfield.h>
#include <linux/math64.h>
+#include <linux/time.h>
#include "core.h"
#include "gadget.h"
@@ -38,8 +39,6 @@
#include "linux-compat.h"
-#define NSEC_PER_SEC 1000000000L
-
static LIST_HEAD(dwc3_list);
/* -------------------------------------------------------------------------- */
diff --git a/drivers/usb/dwc3/core.h b/drivers/usb/dwc3/core.h
index 532746d..4162a68 100644
--- a/drivers/usb/dwc3/core.h
+++ b/drivers/usb/dwc3/core.h
@@ -2,7 +2,7 @@
/**
* core.h - DesignWare USB3 DRD Core Header
*
- * Copyright (C) 2015 Texas Instruments Incorporated - http://www.ti.com
+ * Copyright (C) 2015 Texas Instruments Incorporated - https://www.ti.com
*
* Authors: Felipe Balbi <balbi@ti.com>,
* Sebastian Andrzej Siewior <bigeasy@linutronix.de>
diff --git a/drivers/usb/dwc3/dwc3-generic.c b/drivers/usb/dwc3/dwc3-generic.c
index 744fde8..6fb2de8 100644
--- a/drivers/usb/dwc3/dwc3-generic.c
+++ b/drivers/usb/dwc3/dwc3-generic.c
@@ -610,6 +610,7 @@
{ .compatible = "rockchip,rk3328-dwc3", .data = (ulong)&rk_ops },
{ .compatible = "rockchip,rk3399-dwc3" },
{ .compatible = "rockchip,rk3568-dwc3", .data = (ulong)&rk_ops },
+ { .compatible = "rockchip,rk3588-dwc3", .data = (ulong)&rk_ops },
{ .compatible = "qcom,dwc3" },
{ .compatible = "fsl,imx8mp-dwc3", .data = (ulong)&imx8mp_ops },
{ .compatible = "fsl,imx8mq-dwc3" },
diff --git a/drivers/usb/dwc3/dwc3-meson-g12a.c b/drivers/usb/dwc3/dwc3-meson-g12a.c
index e0356e6..1960352 100644
--- a/drivers/usb/dwc3/dwc3-meson-g12a.c
+++ b/drivers/usb/dwc3/dwc3-meson-g12a.c
@@ -8,13 +8,13 @@
#include <common.h>
#include <log.h>
-#include <asm-generic/io.h>
#include <dm.h>
#include <dm/device-internal.h>
#include <dm/lists.h>
#include <dwc3-uboot.h>
#include <generic-phy.h>
#include <linux/delay.h>
+#include <linux/io.h>
#include <linux/printk.h>
#include <linux/usb/ch9.h>
#include <linux/usb/gadget.h>
diff --git a/drivers/usb/dwc3/dwc3-meson-gxl.c b/drivers/usb/dwc3/dwc3-meson-gxl.c
index d56f274..cbe8aaa 100644
--- a/drivers/usb/dwc3/dwc3-meson-gxl.c
+++ b/drivers/usb/dwc3/dwc3-meson-gxl.c
@@ -8,12 +8,12 @@
#define DEBUG
#include <common.h>
-#include <asm-generic/io.h>
#include <dm.h>
#include <dm/device-internal.h>
#include <dm/lists.h>
#include <dwc3-uboot.h>
#include <generic-phy.h>
+#include <linux/io.h>
#include <linux/usb/ch9.h>
#include <linux/usb/gadget.h>
#include <malloc.h>
diff --git a/drivers/usb/dwc3/dwc3-omap.c b/drivers/usb/dwc3/dwc3-omap.c
index ff4ebfb..4fadb4a 100644
--- a/drivers/usb/dwc3/dwc3-omap.c
+++ b/drivers/usb/dwc3/dwc3-omap.c
@@ -2,7 +2,7 @@
/**
* dwc3-omap.c - OMAP Specific Glue layer
*
- * Copyright (C) 2015 Texas Instruments Incorporated - http://www.ti.com
+ * Copyright (C) 2015 Texas Instruments Incorporated - https://www.ti.com
*
* Authors: Felipe Balbi <balbi@ti.com>,
* Sebastian Andrzej Siewior <bigeasy@linutronix.de>
diff --git a/drivers/usb/dwc3/ep0.c b/drivers/usb/dwc3/ep0.c
index 75ac993..1133cf8 100644
--- a/drivers/usb/dwc3/ep0.c
+++ b/drivers/usb/dwc3/ep0.c
@@ -2,7 +2,7 @@
/**
* ep0.c - DesignWare USB3 DRD Controller Endpoint 0 Handling
*
- * Copyright (C) 2015 Texas Instruments Incorporated - http://www.ti.com
+ * Copyright (C) 2015 Texas Instruments Incorporated - https://www.ti.com
*
* Authors: Felipe Balbi <balbi@ti.com>,
* Sebastian Andrzej Siewior <bigeasy@linutronix.de>
diff --git a/drivers/usb/dwc3/gadget.c b/drivers/usb/dwc3/gadget.c
index 68cf32c..406d36c 100644
--- a/drivers/usb/dwc3/gadget.c
+++ b/drivers/usb/dwc3/gadget.c
@@ -2,7 +2,7 @@
/**
* gadget.c - DesignWare USB3 DRD Controller Gadget Framework Link
*
- * Copyright (C) 2015 Texas Instruments Incorporated - http://www.ti.com
+ * Copyright (C) 2015 Texas Instruments Incorporated - https://www.ti.com
*
* Authors: Felipe Balbi <balbi@ti.com>,
* Sebastian Andrzej Siewior <bigeasy@linutronix.de>
diff --git a/drivers/usb/dwc3/gadget.h b/drivers/usb/dwc3/gadget.h
index 7806ce5..f28a975 100644
--- a/drivers/usb/dwc3/gadget.h
+++ b/drivers/usb/dwc3/gadget.h
@@ -2,7 +2,7 @@
/**
* gadget.h - DesignWare USB3 DRD Gadget Header
*
- * Copyright (C) 2015 Texas Instruments Incorporated - http://www.ti.com
+ * Copyright (C) 2015 Texas Instruments Incorporated - https://www.ti.com
*
* Authors: Felipe Balbi <balbi@ti.com>,
* Sebastian Andrzej Siewior <bigeasy@linutronix.de>
diff --git a/drivers/usb/dwc3/io.h b/drivers/usb/dwc3/io.h
index 2407f82..04791d4 100644
--- a/drivers/usb/dwc3/io.h
+++ b/drivers/usb/dwc3/io.h
@@ -2,7 +2,7 @@
/**
* io.h - DesignWare USB3 DRD IO Header
*
- * Copyright (C) 2014 Texas Instruments Incorporated - http://www.ti.com
+ * Copyright (C) 2014 Texas Instruments Incorporated - https://www.ti.com
*
* Authors: Felipe Balbi <balbi@ti.com>,
* Sebastian Andrzej Siewior <bigeasy@linutronix.de>
diff --git a/drivers/usb/dwc3/linux-compat.h b/drivers/usb/dwc3/linux-compat.h
index 3bb0bda..563f872 100644
--- a/drivers/usb/dwc3/linux-compat.h
+++ b/drivers/usb/dwc3/linux-compat.h
@@ -2,7 +2,7 @@
/**
* linux-compat.h - DesignWare USB3 Linux Compatibiltiy Adapter Header
*
- * Copyright (C) 2015 Texas Instruments Incorporated - http://www.ti.com
+ * Copyright (C) 2015 Texas Instruments Incorporated - https://www.ti.com
*
* Authors: Kishon Vijay Abraham I <kishon@ti.com>
*
diff --git a/drivers/usb/dwc3/ti_usb_phy.c b/drivers/usb/dwc3/ti_usb_phy.c
index f476810..8ae1308 100644
--- a/drivers/usb/dwc3/ti_usb_phy.c
+++ b/drivers/usb/dwc3/ti_usb_phy.c
@@ -2,7 +2,7 @@
/**
* ti_usb_phy.c - USB3 and USB3 PHY programming for dwc3
*
- * Copyright (C) 2015 Texas Instruments Incorporated - http://www.ti.com
+ * Copyright (C) 2015 Texas Instruments Incorporated - https://www.ti.com
*
* Author: Kishon Vijay Abraham I <kishon@ti.com>
*
diff --git a/drivers/usb/gadget/Kconfig b/drivers/usb/gadget/Kconfig
index 4eccc5e..c72a804 100644
--- a/drivers/usb/gadget/Kconfig
+++ b/drivers/usb/gadget/Kconfig
@@ -17,6 +17,7 @@
bool "USB Gadget Support"
depends on DM
select DM_USB
+ imply CMD_BIND
help
USB is a master/slave protocol, organized with one master
host (such as a PC) controlling up to 127 peripheral devices.
diff --git a/drivers/usb/gadget/ci_udc.c b/drivers/usb/gadget/ci_udc.c
index 2bfacfe..750d471 100644
--- a/drivers/usb/gadget/ci_udc.c
+++ b/drivers/usb/gadget/ci_udc.c
@@ -13,6 +13,7 @@
#include <cpu_func.h>
#include <net.h>
#include <malloc.h>
+#include <wait_bit.h>
#include <asm/byteorder.h>
#include <asm/cache.h>
#include <linux/delay.h>
@@ -354,12 +355,49 @@
return 0;
}
+static int ep_disable(int num, int in)
+{
+ struct ci_udc *udc = (struct ci_udc *)controller.ctrl->hcor;
+ unsigned int ep_bit, enable_bit;
+ int err;
+
+ if (in) {
+ ep_bit = EPT_TX(num);
+ enable_bit = CTRL_TXE;
+ } else {
+ ep_bit = EPT_RX(num);
+ enable_bit = CTRL_RXE;
+ }
+
+ /* clear primed buffers */
+ do {
+ writel(ep_bit, &udc->epflush);
+ err = wait_for_bit_le32(&udc->epflush, ep_bit, false, 1000, false);
+ if (err)
+ return err;
+ } while (readl(&udc->epstat) & ep_bit);
+
+ /* clear enable bit */
+ clrbits_le32(&udc->epctrl[num], enable_bit);
+
+ return 0;
+}
+
static int ci_ep_disable(struct usb_ep *ep)
{
struct ci_ep *ci_ep = container_of(ep, struct ci_ep, ep);
+ int num, in, err;
+
+ num = ci_ep->desc->bEndpointAddress & USB_ENDPOINT_NUMBER_MASK;
+ in = (ci_ep->desc->bEndpointAddress & USB_DIR_IN) != 0;
+
+ err = ep_disable(num, in);
+ if (err)
+ return err;
ci_ep->desc = NULL;
ep->desc = NULL;
+ ci_ep->req_primed = false;
return 0;
}
diff --git a/drivers/usb/gadget/f_fastboot.c b/drivers/usb/gadget/f_fastboot.c
index 741775a..9f322c9 100644
--- a/drivers/usb/gadget/f_fastboot.c
+++ b/drivers/usb/gadget/f_fastboot.c
@@ -520,7 +520,7 @@
cmdbuf[req->actual] = '\0';
cmd = fastboot_handle_command(cmdbuf, response);
} else {
- pr_err("buffer overflow");
+ pr_err("buffer overflow\n");
fastboot_fail("buffer overflow", response);
}
diff --git a/drivers/usb/gadget/f_mass_storage.c b/drivers/usb/gadget/f_mass_storage.c
index 1d17331..c725aed 100644
--- a/drivers/usb/gadget/f_mass_storage.c
+++ b/drivers/usb/gadget/f_mass_storage.c
@@ -327,6 +327,7 @@
unsigned int short_packet_received:1;
unsigned int bad_lun_okay:1;
unsigned int running:1;
+ unsigned int eject:1;
int thread_wakeup_needed;
struct completion thread_notifier;
@@ -669,6 +670,10 @@
}
if (k == 10) {
+ /* Handle START-STOP UNIT */
+ if (common->eject)
+ return -EPIPE;
+
/* Handle CTRL+C */
if (ctrlc())
return -EPIPE;
@@ -1325,6 +1330,8 @@
return -EINVAL;
}
+ common->eject = 1;
+
return 0;
}
diff --git a/drivers/usb/gadget/f_sdp.c b/drivers/usb/gadget/f_sdp.c
index ee9384f..ca2760c 100644
--- a/drivers/usb/gadget/f_sdp.c
+++ b/drivers/usb/gadget/f_sdp.c
@@ -744,7 +744,7 @@
{
debug("%s: sector %lx, count %lx, buf %lx\n",
__func__, sector, count, (ulong)buf);
- memcpy(buf, (void *)(load->dev + sector), count);
+ memcpy(buf, (void *)(load->priv + sector), count);
return count;
}
@@ -844,8 +844,8 @@
struct spl_load_info load;
debug("Found FIT\n");
- load.dev = header;
- load.bl_len = 1;
+ load.priv = header;
+ spl_set_bl_len(&load, 1);
load.read = sdp_load_read;
spl_load_simple_fit(spl_image, &load, 0,
header);
@@ -857,8 +857,8 @@
valid_container_hdr((void *)header)) {
struct spl_load_info load;
- load.dev = header;
- load.bl_len = 1;
+ load.priv = header;
+ spl_set_bl_len(&load, 1);
load.read = sdp_load_read;
spl_load_imx_container(spl_image, &load, 0);
return SDP_EXIT;
diff --git a/drivers/usb/gadget/udc/udc-core.c b/drivers/usb/gadget/udc/udc-core.c
index 7f73926..ba658d9 100644
--- a/drivers/usb/gadget/udc/udc-core.c
+++ b/drivers/usb/gadget/udc/udc-core.c
@@ -2,7 +2,7 @@
/**
* udc-core.c - Core UDC Framework
*
- * Copyright (C) 2015 Texas Instruments Incorporated - http://www.ti.com
+ * Copyright (C) 2015 Texas Instruments Incorporated - https://www.ti.com
*
* Author: Felipe Balbi <balbi@ti.com>
*
@@ -323,6 +323,7 @@
int usb_gadget_probe_driver(struct usb_gadget_driver *driver)
{
struct usb_udc *udc = NULL;
+ unsigned int udc_count = 0;
int ret;
if (!driver || !driver->bind || !driver->setup)
@@ -330,12 +331,22 @@
mutex_lock(&udc_lock);
list_for_each_entry(udc, &udc_list, list) {
+ udc_count++;
+
/* For now we take the first one */
if (!udc->driver)
goto found;
}
- printf("couldn't find an available UDC\n");
+ if (!udc_count)
+ printf("No UDC available in the system\n");
+ else
+ /* When this happens, users should 'unbind <class> <index>'
+ * using the output of 'dm tree' and looking at the line right
+ * after the USB peripheral/device controller.
+ */
+ printf("All UDCs in use (%d available), use the unbind command\n",
+ udc_count);
mutex_unlock(&udc_lock);
return -ENODEV;
found:
diff --git a/drivers/usb/gadget/udc/udc-uclass.c b/drivers/usb/gadget/udc/udc-uclass.c
index 3e43312..30ee1ca 100644
--- a/drivers/usb/gadget/udc/udc-uclass.c
+++ b/drivers/usb/gadget/udc/udc-uclass.c
@@ -1,6 +1,6 @@
// SPDX-License-Identifier: GPL-2.0+
/*
- * Copyright (C) 2018 Texas Instruments Incorporated - http://www.ti.com
+ * Copyright (C) 2018 Texas Instruments Incorporated - https://www.ti.com
* Written by Jean-Jacques Hiblot <jjhiblot@ti.com>
*/
diff --git a/drivers/usb/host/Kconfig b/drivers/usb/host/Kconfig
index b501ea5..35610ff 100644
--- a/drivers/usb/host/Kconfig
+++ b/drivers/usb/host/Kconfig
@@ -90,7 +90,7 @@
config USB_XHCI_PCI
bool "Support for PCI-based xHCI USB controller"
- depends on DM_USB
+ depends on DM_USB && PCI
default y if X86
help
Enables support for the PCI-based xHCI controller.
diff --git a/drivers/usb/host/dwc3-of-simple.c b/drivers/usb/host/dwc3-of-simple.c
index 66b3e96..f9df59d 100644
--- a/drivers/usb/host/dwc3-of-simple.c
+++ b/drivers/usb/host/dwc3-of-simple.c
@@ -2,7 +2,7 @@
/*
* dwc3-of-simple.c - OF glue layer for simple integrations
*
- * Copyright (c) 2015 Texas Instruments Incorporated - http://www.ti.com
+ * Copyright (c) 2015 Texas Instruments Incorporated - https://www.ti.com
*
* Author: Felipe Balbi <balbi@ti.com>
*
diff --git a/drivers/usb/host/xhci-ring.c b/drivers/usb/host/xhci-ring.c
index c8260cb..b60661f 100644
--- a/drivers/usb/host/xhci-ring.c
+++ b/drivers/usb/host/xhci-ring.c
@@ -202,6 +202,7 @@
bool more_trbs_coming, unsigned int *trb_fields)
{
struct xhci_generic_trb *trb;
+ dma_addr_t addr;
int i;
trb = &ring->enqueue->generic;
@@ -211,9 +212,11 @@
xhci_flush_cache((uintptr_t)trb, sizeof(struct xhci_generic_trb));
+ addr = xhci_trb_virt_to_dma(ring->enq_seg, (union xhci_trb *)trb);
+
inc_enq(ctrl, ring, more_trbs_coming);
- return xhci_trb_virt_to_dma(ring->enq_seg, (union xhci_trb *)trb);
+ return addr;
}
/**
@@ -243,7 +246,8 @@
puts("WARN waiting for error on ep to be cleared\n");
return -EINVAL;
case EP_STATE_HALTED:
- puts("WARN halted endpoint, queueing URB anyway.\n");
+ puts("WARN endpoint is halted\n");
+ return -EINVAL;
case EP_STATE_STOPPED:
case EP_STATE_RUNNING:
debug("EP STATE RUNNING.\n");
@@ -466,7 +470,8 @@
continue;
type = TRB_FIELD_TO_TYPE(le32_to_cpu(event->event_cmd.flags));
- if (type == expected)
+ if (type == expected ||
+ (expected == TRB_NONE && type != TRB_PORT_STATUS))
return event;
if (type == TRB_PORT_STATUS)
@@ -492,8 +497,9 @@
if (expected == TRB_TRANSFER)
return NULL;
+ printf("XHCI timeout on event type %d...\n", expected);
+
- printf("XHCI timeout on event type %d... cannot recover.\n", expected);
- BUG();
+ return NULL;
}
/*
@@ -511,6 +517,9 @@
printf("Resetting EP %d...\n", ep_index);
xhci_queue_command(ctrl, 0, udev->slot_id, ep_index, TRB_RESET_EP);
event = xhci_wait_for_event(ctrl, TRB_COMPLETION);
+ if (!event)
+ return;
+
field = le32_to_cpu(event->trans_event.flags);
BUG_ON(TRB_TO_SLOT_ID(field) != udev->slot_id);
xhci_acknowledge_event(ctrl);
@@ -519,6 +528,9 @@
(void *)((uintptr_t)ring->enqueue | ring->cycle_state));
xhci_queue_command(ctrl, addr, udev->slot_id, ep_index, TRB_SET_DEQ);
event = xhci_wait_for_event(ctrl, TRB_COMPLETION);
+ if (!event)
+ return;
+
BUG_ON(TRB_TO_SLOT_ID(le32_to_cpu(event->event_cmd.flags))
!= udev->slot_id || GET_COMP_CODE(le32_to_cpu(
event->event_cmd.status)) != COMP_SUCCESS);
@@ -538,29 +550,49 @@
struct xhci_ctrl *ctrl = xhci_get_ctrl(udev);
struct xhci_ring *ring = ctrl->devs[udev->slot_id]->eps[ep_index].ring;
union xhci_trb *event;
+ xhci_comp_code comp;
+ trb_type type;
u64 addr;
u32 field;
xhci_queue_command(ctrl, 0, udev->slot_id, ep_index, TRB_STOP_RING);
- event = xhci_wait_for_event(ctrl, TRB_TRANSFER);
- field = le32_to_cpu(event->trans_event.flags);
- BUG_ON(TRB_TO_SLOT_ID(field) != udev->slot_id);
- BUG_ON(TRB_TO_EP_INDEX(field) != ep_index);
- BUG_ON(GET_COMP_CODE(le32_to_cpu(event->trans_event.transfer_len
- != COMP_STOP)));
- xhci_acknowledge_event(ctrl);
+ event = xhci_wait_for_event(ctrl, TRB_NONE);
+ if (!event)
+ return;
- event = xhci_wait_for_event(ctrl, TRB_COMPLETION);
- BUG_ON(TRB_TO_SLOT_ID(le32_to_cpu(event->event_cmd.flags))
- != udev->slot_id || GET_COMP_CODE(le32_to_cpu(
- event->event_cmd.status)) != COMP_SUCCESS);
+ type = TRB_FIELD_TO_TYPE(le32_to_cpu(event->event_cmd.flags));
+ if (type == TRB_TRANSFER) {
+ field = le32_to_cpu(event->trans_event.flags);
+ BUG_ON(TRB_TO_SLOT_ID(field) != udev->slot_id);
+ BUG_ON(TRB_TO_EP_INDEX(field) != ep_index);
+ BUG_ON(GET_COMP_CODE(le32_to_cpu(event->trans_event.transfer_len
+ != COMP_STOP)));
+ xhci_acknowledge_event(ctrl);
+
+ event = xhci_wait_for_event(ctrl, TRB_COMPLETION);
+ if (!event)
+ return;
+ type = TRB_FIELD_TO_TYPE(le32_to_cpu(event->event_cmd.flags));
+
+ } else {
+ printf("abort_td: Expected a TRB_TRANSFER TRB first\n");
+ }
+
+ comp = GET_COMP_CODE(le32_to_cpu(event->event_cmd.status));
+ BUG_ON(type != TRB_COMPLETION ||
+ TRB_TO_SLOT_ID(le32_to_cpu(event->event_cmd.flags))
+ != udev->slot_id || (comp != COMP_SUCCESS && comp
+ != COMP_CTX_STATE));
xhci_acknowledge_event(ctrl);
addr = xhci_trb_virt_to_dma(ring->enq_seg,
(void *)((uintptr_t)ring->enqueue | ring->cycle_state));
xhci_queue_command(ctrl, addr, udev->slot_id, ep_index, TRB_SET_DEQ);
event = xhci_wait_for_event(ctrl, TRB_COMPLETION);
+ if (!event)
+ return;
+
BUG_ON(TRB_TO_SLOT_ID(le32_to_cpu(event->event_cmd.flags))
!= udev->slot_id || GET_COMP_CODE(le32_to_cpu(
event->event_cmd.status)) != COMP_SUCCESS);
@@ -644,6 +676,14 @@
ep_ctx = xhci_get_ep_ctx(ctrl, virt_dev->out_ctx, ep_index);
+ /*
+ * If the endpoint was halted due to a prior error, resume it before
+ * the next transfer. It is the responsibility of the upper layer to
+ * have dealt with whatever caused the error.
+ */
+ if ((le32_to_cpu(ep_ctx->ep_info) & EP_STATE_MASK) == EP_STATE_HALTED)
+ reset_ep(udev, ep_index);
+
ring = virt_dev->eps[ep_index].ring;
/*
* How much data is (potentially) left before the 64KB boundary?
diff --git a/drivers/usb/host/xhci.c b/drivers/usb/host/xhci.c
index 5cacf07..d13cbff 100644
--- a/drivers/usb/host/xhci.c
+++ b/drivers/usb/host/xhci.c
@@ -451,6 +451,9 @@
xhci_queue_command(ctrl, in_ctx->dma, udev->slot_id, 0,
ctx_change ? TRB_EVAL_CONTEXT : TRB_CONFIG_EP);
event = xhci_wait_for_event(ctrl, TRB_COMPLETION);
+ if (!event)
+ return -ETIMEDOUT;
+
BUG_ON(TRB_TO_SLOT_ID(le32_to_cpu(event->event_cmd.flags))
!= udev->slot_id);
@@ -647,6 +650,9 @@
xhci_queue_command(ctrl, virt_dev->in_ctx->dma,
slot_id, 0, TRB_ADDR_DEV);
event = xhci_wait_for_event(ctrl, TRB_COMPLETION);
+ if (!event)
+ return -ETIMEDOUT;
+
BUG_ON(TRB_TO_SLOT_ID(le32_to_cpu(event->event_cmd.flags)) != slot_id);
switch (GET_COMP_CODE(le32_to_cpu(event->event_cmd.status))) {
@@ -722,6 +728,9 @@
xhci_queue_command(ctrl, 0, 0, 0, TRB_ENABLE_SLOT);
event = xhci_wait_for_event(ctrl, TRB_COMPLETION);
+ if (!event)
+ return -ETIMEDOUT;
+
BUG_ON(GET_COMP_CODE(le32_to_cpu(event->event_cmd.status))
!= COMP_SUCCESS);
diff --git a/drivers/usb/musb-new/musb_io.h b/drivers/usb/musb-new/musb_io.h
index 72a5365..19b12f3 100644
--- a/drivers/usb/musb-new/musb_io.h
+++ b/drivers/usb/musb-new/musb_io.h
@@ -14,31 +14,7 @@
#ifndef __MUSB_LINUX_PLATFORM_ARCH_H__
#define __MUSB_LINUX_PLATFORM_ARCH_H__
-#ifndef __UBOOT__
#include <linux/io.h>
-#else
-#include <asm/io.h>
-#endif
-
-#if !defined(CONFIG_ARM) && !defined(CONFIG_SUPERH) \
- && !defined(CONFIG_PPC32) \
- && !defined(CONFIG_PPC64) && !defined(CONFIG_MIPS) \
- && !defined(CONFIG_M68K)
-static inline void readsl(const void __iomem *addr, void *buf, int len)
- { insl((unsigned long)addr, buf, len); }
-static inline void readsw(const void __iomem *addr, void *buf, int len)
- { insw((unsigned long)addr, buf, len); }
-static inline void readsb(const void __iomem *addr, void *buf, int len)
- { insb((unsigned long)addr, buf, len); }
-
-static inline void writesl(const void __iomem *addr, const void *buf, int len)
- { outsl((unsigned long)addr, buf, len); }
-static inline void writesw(const void __iomem *addr, const void *buf, int len)
- { outsw((unsigned long)addr, buf, len); }
-static inline void writesb(const void __iomem *addr, const void *buf, int len)
- { outsb((unsigned long)addr, buf, len); }
-
-#endif
/* NOTE: these offsets are all in bytes */
diff --git a/drivers/usb/ulpi/omap-ulpi-viewport.c b/drivers/usb/ulpi/omap-ulpi-viewport.c
index 8d71db0..1b01cd4 100644
--- a/drivers/usb/ulpi/omap-ulpi-viewport.c
+++ b/drivers/usb/ulpi/omap-ulpi-viewport.c
@@ -3,7 +3,7 @@
* OMAP ulpi viewport support
* Based on drivers/usb/ulpi/ulpi-viewport.c
*
- * Copyright (C) 2011 Texas Instruments Incorporated - http://www.ti.com
+ * Copyright (C) 2011 Texas Instruments Incorporated - https://www.ti.com
* Author: Govindraj R <govindraj.raja@ti.com>
*/
diff --git a/drivers/video/dw_mipi_dsi.c b/drivers/video/dw_mipi_dsi.c
index 22fef7e..a7e0784 100644
--- a/drivers/video/dw_mipi_dsi.c
+++ b/drivers/video/dw_mipi_dsi.c
@@ -22,6 +22,7 @@
#include <linux/bitops.h>
#include <linux/delay.h>
#include <linux/iopoll.h>
+#include <linux/time.h>
#include <video_bridge.h>
#define HWVER_131 0x31333100 /* IP version 1.31 */
@@ -214,8 +215,6 @@
#define PHY_STATUS_TIMEOUT_US 10000
#define CMD_PKT_STATUS_TIMEOUT_US 20000
-#define MSEC_PER_SEC 1000
-
struct dw_mipi_dsi {
struct mipi_dsi_host dsi_host;
struct mipi_dsi_device *device;
diff --git a/drivers/video/rockchip/dw_mipi_dsi_rockchip.c b/drivers/video/rockchip/dw_mipi_dsi_rockchip.c
index 1a5ab78..5e75b6e 100644
--- a/drivers/video/rockchip/dw_mipi_dsi_rockchip.c
+++ b/drivers/video/rockchip/dw_mipi_dsi_rockchip.c
@@ -30,12 +30,11 @@
#include <asm/io.h>
#include <dm/device-internal.h>
#include <linux/bitops.h>
+#include <linux/time.h>
#include <asm/arch-rockchip/clock.h>
#include <asm/arch-rockchip/hardware.h>
-#define USEC_PER_SEC 1000000L
-
/*
* DSI wrapper registers & bit definitions
* Note: registers are named as in the Reference Manual
diff --git a/drivers/video/tegra20/tegra-dsi.c b/drivers/video/tegra20/tegra-dsi.c
index b4cf4fa..a48f9c8 100644
--- a/drivers/video/tegra20/tegra-dsi.c
+++ b/drivers/video/tegra20/tegra-dsi.c
@@ -14,6 +14,7 @@
#include <panel.h>
#include <linux/delay.h>
#include <linux/err.h>
+#include <linux/time.h>
#include <power/regulator.h>
#include <asm/gpio.h>
@@ -24,9 +25,6 @@
#include "mipi-phy.h"
-#define USEC_PER_SEC 1000000L
-#define NSEC_PER_SEC 1000000000L
-
struct tegra_dsi_priv {
struct mipi_dsi_host host;
struct mipi_dsi_device device;
diff --git a/drivers/virtio/virtio_rng.c b/drivers/virtio/virtio_rng.c
index b85545c..786359a 100644
--- a/drivers/virtio/virtio_rng.c
+++ b/drivers/virtio/virtio_rng.c
@@ -20,7 +20,7 @@
static int virtio_rng_read(struct udevice *dev, void *data, size_t len)
{
int ret;
- unsigned int rsize;
+ unsigned int rsize = 1;
unsigned char buf[BUFFER_SIZE] __aligned(4);
unsigned char *ptr = data;
struct virtio_sg sg;
@@ -29,7 +29,12 @@
while (len) {
sg.addr = buf;
- sg.length = min(len, sizeof(buf));
+ /*
+ * Work around implementations which always return 8 bytes
+ * less than requested, down to 0 bytes, which would
+ * cause an endless loop otherwise.
+ */
+ sg.length = min(rsize ? len : len + 8, sizeof(buf));
sgs[0] = &sg;
ret = virtqueue_add(priv->rng_vq, sgs, 0, 1);
diff --git a/drivers/watchdog/s5p_wdt.c b/drivers/watchdog/s5p_wdt.c
index 5ad7d26..80524a0 100644
--- a/drivers/watchdog/s5p_wdt.c
+++ b/drivers/watchdog/s5p_wdt.c
@@ -6,6 +6,7 @@
#include <common.h>
#include <asm/io.h>
+#include <asm/arch/cpu.h>
#include <asm/arch/watchdog.h>
#define PRESCALER_VAL 255
diff --git a/drivers/watchdog/sunxi_wdt.c b/drivers/watchdog/sunxi_wdt.c
index b40a1d2..8eeac93 100644
--- a/drivers/watchdog/sunxi_wdt.c
+++ b/drivers/watchdog/sunxi_wdt.c
@@ -9,8 +9,7 @@
#include <wdt.h>
#include <asm/io.h>
#include <linux/delay.h>
-
-#define MSEC_PER_SEC 1000
+#include <linux/time.h>
#define WDT_MAX_TIMEOUT 16
#define WDT_TIMEOUT_MASK 0xf
diff --git a/drivers/watchdog/wdt-uclass.c b/drivers/watchdog/wdt-uclass.c
index ed32928..417e8d7 100644
--- a/drivers/watchdog/wdt-uclass.c
+++ b/drivers/watchdog/wdt-uclass.c
@@ -7,6 +7,7 @@
#include <common.h>
#include <cyclic.h>
+#include <div64.h>
#include <dm.h>
#include <errno.h>
#include <hang.h>
@@ -141,7 +142,7 @@
printf("WDT: Started %s with%s servicing %s (%ds timeout)\n",
dev->name, IS_ENABLED(CONFIG_WATCHDOG) ? "" : "out",
- str, priv->timeout);
+ str, (u32)lldiv(timeout_ms, 1000));
}
return ret;
diff --git a/drivers/xen/pvblock.c b/drivers/xen/pvblock.c
index 4ad548d..1df04e2 100644
--- a/drivers/xen/pvblock.c
+++ b/drivers/xen/pvblock.c
@@ -632,7 +632,8 @@
memcpy(blk_dev->bounce_buffer, buffer, desc->blksz);
aiocb.aio_nbytes = unaligned ? desc->blksz :
- min((size_t)(BLKIF_MAX_SEGMENTS_PER_REQUEST * PAGE_SIZE),
+ min((size_t)((BLKIF_MAX_SEGMENTS_PER_REQUEST - 1)
+ * PAGE_SIZE),
(size_t)(blocks_todo * desc->blksz));
blkfront_io(&aiocb, write);
diff --git a/env/ext4.c b/env/ext4.c
index 47e05a4..da26705 100644
--- a/env/ext4.c
+++ b/env/ext4.c
@@ -77,7 +77,7 @@
dev = dev_desc->devnum;
ext4fs_set_blk_dev(dev_desc, &info);
- if (!ext4fs_mount(info.size)) {
+ if (!ext4fs_mount()) {
printf("\n** Unable to use %s %s for saveenv **\n",
ifname, dev_and_part);
return 1;
@@ -160,7 +160,7 @@
dev = dev_desc->devnum;
ext4fs_set_blk_dev(dev_desc, &info);
- if (!ext4fs_mount(info.size)) {
+ if (!ext4fs_mount()) {
printf("\n** Unable to use %s %s for loading the env **\n",
ifname, dev_and_part);
goto err_env_relocate;
diff --git a/fs/btrfs/btrfs.c b/fs/btrfs/btrfs.c
index 4cdbbbe..1149a3b 100644
--- a/fs/btrfs/btrfs.c
+++ b/fs/btrfs/btrfs.c
@@ -228,7 +228,7 @@
{
struct btrfs_fs_info *fs_info = current_fs_info;
struct btrfs_root *root;
- loff_t real_size = 0;
+ loff_t real_size;
u64 ino;
u8 type;
int ret;
@@ -246,16 +246,13 @@
return -EINVAL;
}
- if (!len) {
- ret = btrfs_size(file, &real_size);
- if (ret < 0) {
- error("Failed to get inode size: %s", file);
- return ret;
- }
- len = real_size;
+ ret = btrfs_size(file, &real_size);
+ if (ret < 0) {
+ error("Failed to get inode size: %s", file);
+ return ret;
}
- if (len > real_size - offset)
+ if (!len || len > real_size - offset)
len = real_size - offset;
ret = btrfs_file_read(root, ino, offset, len, buf);
diff --git a/fs/ext4/ext4_common.c b/fs/ext4/ext4_common.c
index f50de7c..ea9b922 100644
--- a/fs/ext4/ext4_common.c
+++ b/fs/ext4/ext4_common.c
@@ -2368,7 +2368,7 @@
return -1;
}
-int ext4fs_mount(unsigned part_length)
+int ext4fs_mount(void)
{
struct ext2_data *data;
int status;
diff --git a/fs/ext4/ext4fs.c b/fs/ext4/ext4fs.c
index 4c89152..3b12ec5 100644
--- a/fs/ext4/ext4fs.c
+++ b/fs/ext4/ext4fs.c
@@ -233,7 +233,7 @@
{
ext4fs_set_blk_dev(fs_dev_desc, fs_partition);
- if (!ext4fs_mount(fs_partition->size)) {
+ if (!ext4fs_mount()) {
ext4fs_close();
return -1;
}
diff --git a/fs/fat/fat.c b/fs/fat/fat.c
index 8ff1fd0..14e53cf 100644
--- a/fs/fat/fat.c
+++ b/fs/fat/fat.c
@@ -18,12 +18,17 @@
#include <fs.h>
#include <log.h>
#include <asm/byteorder.h>
+#include <asm/unaligned.h>
#include <part.h>
#include <malloc.h>
#include <memalign.h>
#include <asm/cache.h>
#include <linux/compiler.h>
#include <linux/ctype.h>
+#include <linux/log2.h>
+
+/* maximum number of clusters for FAT12 */
+#define MAX_FAT12 0xFF4
/*
* Convert a string to lowercase. Converts at most 'len' characters,
@@ -484,6 +489,73 @@
}
/*
+ * Determine if the FAT type is FAT12 or FAT16
+ *
+ * Based on fat_fill_super() from the Linux kernel's fs/fat/inode.c
+ */
+static int determine_legacy_fat_bits(const boot_sector *bs)
+{
+ u16 fat_start = bs->reserved;
+ u32 dir_start = fat_start + bs->fats * bs->fat_length;
+ u32 rootdir_sectors = get_unaligned_le16(bs->dir_entries) *
+ sizeof(dir_entry) /
+ get_unaligned_le16(bs->sector_size);
+ u32 data_start = dir_start + rootdir_sectors;
+ u16 sectors = get_unaligned_le16(bs->sectors);
+ u32 total_sectors = sectors ? sectors : bs->total_sect;
+ u32 total_clusters = (total_sectors - data_start) /
+ bs->cluster_size;
+
+ return (total_clusters > MAX_FAT12) ? 16 : 12;
+}
+
+/*
+ * Determines if the boot sector's media field is valid
+ *
+ * Based on fat_valid_media() from Linux kernel's include/linux/msdos_fs.h
+ */
+static int fat_valid_media(u8 media)
+{
+ return media >= 0xf8 || media == 0xf0;
+}
+
+/*
+ * Determines if the given boot sector is valid
+ *
+ * Based on fat_read_bpb() from the Linux kernel's fs/fat/inode.c
+ */
+static int is_bootsector_valid(const boot_sector *bs)
+{
+ u16 sector_size = get_unaligned_le16(bs->sector_size);
+ u16 dir_per_block = sector_size / sizeof(dir_entry);
+
+ if (!bs->reserved)
+ return 0;
+
+ if (!bs->fats)
+ return 0;
+
+ if (!fat_valid_media(bs->media))
+ return 0;
+
+ if (!is_power_of_2(sector_size) ||
+ sector_size < 512 ||
+ sector_size > 4096)
+ return 0;
+
+ if (!is_power_of_2(bs->cluster_size))
+ return 0;
+
+ if (!bs->fat_length && !bs->fat32_length)
+ return 0;
+
+ if (get_unaligned_le16(bs->dir_entries) & (dir_per_block - 1))
+ return 0;
+
+ return 1;
+}
+
+/*
* Read boot sector and volume info from a FAT filesystem
*/
static int
@@ -506,7 +578,8 @@
if (disk_read(0, 1, block) < 0) {
debug("Error: reading block\n");
- goto fail;
+ ret = -1;
+ goto out_free;
}
memcpy(bs, block, sizeof(boot_sector));
@@ -516,8 +589,14 @@
bs->heads = FAT2CPU16(bs->heads);
bs->total_sect = FAT2CPU32(bs->total_sect);
+ if (!is_bootsector_valid(bs)) {
+ debug("Error: bootsector is invalid\n");
+ ret = -1;
+ goto out_free;
+ }
+
/* FAT32 entries */
- if (bs->fat_length == 0) {
+ if (!bs->fat_length && bs->fat32_length) {
/* Assume FAT32 */
bs->fat32_length = FAT2CPU32(bs->fat32_length);
bs->flags = FAT2CPU16(bs->flags);
@@ -528,28 +607,11 @@
*fatsize = 32;
} else {
vistart = (volume_info *)&(bs->fat32_length);
- *fatsize = 0;
+ *fatsize = determine_legacy_fat_bits(bs);
}
memcpy(volinfo, vistart, sizeof(volume_info));
- if (*fatsize == 32) {
- if (strncmp(FAT32_SIGN, vistart->fs_type, SIGNLEN) == 0)
- goto exit;
- } else {
- if (strncmp(FAT12_SIGN, vistart->fs_type, SIGNLEN) == 0) {
- *fatsize = 12;
- goto exit;
- }
- if (strncmp(FAT16_SIGN, vistart->fs_type, SIGNLEN) == 0) {
- *fatsize = 16;
- goto exit;
- }
- }
-
- debug("Error: broken fs_type sign\n");
-fail:
- ret = -1;
-exit:
+out_free:
free(block);
return ret;
}
@@ -571,7 +633,7 @@
mydata->total_sect = bs.total_sect;
} else {
mydata->fatlength = bs.fat_length;
- mydata->total_sect = (bs.sectors[1] << 8) + bs.sectors[0];
+ mydata->total_sect = get_unaligned_le16(bs.sectors);
if (!mydata->total_sect)
mydata->total_sect = bs.total_sect;
}
@@ -583,7 +645,7 @@
mydata->rootdir_sect = mydata->fat_sect + mydata->fatlength * bs.fats;
- mydata->sect_size = (bs.sector_size[1] << 8) + bs.sector_size[0];
+ mydata->sect_size = get_unaligned_le16(bs.sector_size);
mydata->clust_size = bs.cluster_size;
if (mydata->sect_size != cur_part_info.blksz) {
log_err("FAT sector size mismatch (fs=%u, dev=%lu)\n",
@@ -607,8 +669,7 @@
(mydata->clust_size * 2);
mydata->root_cluster = bs.root_cluster;
} else {
- mydata->rootdir_size = ((bs.dir_entries[1] * (int)256 +
- bs.dir_entries[0]) *
+ mydata->rootdir_size = (get_unaligned_le16(bs.dir_entries) *
sizeof(dir_entry)) /
mydata->sect_size;
mydata->data_begin = mydata->rootdir_sect +
@@ -1157,9 +1218,8 @@
memcpy(vol_label, volinfo.volume_label, 11);
vol_label[11] = '\0';
- volinfo.fs_type[5] = '\0';
- printf("Filesystem: %s \"%s\"\n", volinfo.fs_type, vol_label);
+ printf("Filesystem: FAT%d \"%s\"\n", fatsize, vol_label);
return 0;
}
diff --git a/fs/squashfs/sqfs_decompressor.c b/fs/squashfs/sqfs_decompressor.c
index 6b3e01c..cfd1153 100644
--- a/fs/squashfs/sqfs_decompressor.c
+++ b/fs/squashfs/sqfs_decompressor.c
@@ -18,6 +18,10 @@
#include <u-boot/zlib.h>
#endif
+#if IS_ENABLED(CONFIG_LZ4)
+#include <u-boot/lz4.h>
+#endif
+
#if IS_ENABLED(CONFIG_ZSTD)
#include <linux/zstd.h>
#endif
@@ -38,6 +42,10 @@
case SQFS_COMP_ZLIB:
break;
#endif
+#if IS_ENABLED(CONFIG_LZ4)
+ case SQFS_COMP_LZ4:
+ break;
+#endif
#if IS_ENABLED(CONFIG_ZSTD)
case SQFS_COMP_ZSTD:
ctxt->zstd_workspace = malloc(zstd_dctx_workspace_bound());
@@ -66,6 +74,10 @@
case SQFS_COMP_ZLIB:
break;
#endif
+#if IS_ENABLED(CONFIG_LZ4)
+ case SQFS_COMP_LZ4:
+ break;
+#endif
#if IS_ENABLED(CONFIG_ZSTD)
case SQFS_COMP_ZSTD:
free(ctxt->zstd_workspace);
@@ -139,6 +151,17 @@
break;
#endif
+#if IS_ENABLED(CONFIG_LZ4)
+ case SQFS_COMP_LZ4:
+ ret = LZ4_decompress_safe(source, dest, src_len, *dest_len);
+ if (ret < 0) {
+ printf("LZ4 decompression failed.\n");
+ return -EINVAL;
+ }
+
+ ret = 0;
+ break;
+#endif
#if IS_ENABLED(CONFIG_ZSTD)
case SQFS_COMP_ZSTD:
ret = sqfs_zstd_decompress(ctxt, dest, *dest_len, source, src_len);
diff --git a/fs/squashfs/sqfs_decompressor.h b/fs/squashfs/sqfs_decompressor.h
index 892cfb6..c48b74f 100644
--- a/fs/squashfs/sqfs_decompressor.h
+++ b/fs/squashfs/sqfs_decompressor.h
@@ -18,41 +18,6 @@
#define SQFS_COMP_LZ4 5
#define SQFS_COMP_ZSTD 6
-/* LZMA does not support any compression options */
-
-struct squashfs_gzip_opts {
- u32 compression_level;
- u16 window_size;
- u16 strategies;
-};
-
-struct squashfs_xz_opts {
- u32 dictionary_size;
- u32 executable_filters;
-};
-
-struct squashfs_lz4_opts {
- u32 version;
- u32 flags;
-};
-
-struct squashfs_zstd_opts {
- u32 compression_level;
-};
-
-struct squashfs_lzo_opts {
- u32 algorithm;
- u32 level;
-};
-
-union squashfs_compression_opts {
- struct squashfs_gzip_opts *gzip;
- struct squashfs_xz_opts *xz;
- struct squashfs_lz4_opts *lz4;
- struct squashfs_zstd_opts *zstd;
- struct squashfs_lzo_opts *lzo;
-};
-
int sqfs_decompress(struct squashfs_ctxt *ctxt, void *dest,
unsigned long *dest_len, void *source, u32 src_len);
int sqfs_decompressor_init(struct squashfs_ctxt *ctxt);
diff --git a/fs/squashfs/sqfs_filesystem.h b/fs/squashfs/sqfs_filesystem.h
index 5440b6c..be56498 100644
--- a/fs/squashfs/sqfs_filesystem.h
+++ b/fs/squashfs/sqfs_filesystem.h
@@ -13,7 +13,6 @@
#include <part.h>
#include <stdint.h>
-#define SQFS_UNCOMPRESSED_DATA 0x0002
#define SQFS_MAGIC_NUMBER 0x73717368
/* The three first members of squashfs_dir_index make a total of 12 bytes */
#define SQFS_DIR_INDEX_BASE_LENGTH 12
@@ -23,7 +22,6 @@
#define SQFS_MAX_ENTRIES 512
/* Metadata blocks start by a 2-byte length header */
#define SQFS_HEADER_SIZE 2
-#define SQFS_LREG_INODE_MIN_SIZE 56
#define SQFS_DIR_HEADER_SIZE 12
#define SQFS_MISC_ENTRY_TYPE -1
#define SQFS_EMPTY_FILE_SIZE 3
diff --git a/fs/squashfs/sqfs_utils.h b/fs/squashfs/sqfs_utils.h
index 1260abe..41f13e8 100644
--- a/fs/squashfs/sqfs_utils.h
+++ b/fs/squashfs/sqfs_utils.h
@@ -15,11 +15,8 @@
#define SQFS_FRAGMENT_INDEX_OFFSET(A) ((A) % SQFS_MAX_ENTRIES)
#define SQFS_FRAGMENT_INDEX(A) ((A) / SQFS_MAX_ENTRIES)
#define SQFS_BLOCK_SIZE(A) ((A) & GENMASK(23, 0))
-#define SQFS_CHECK_FLAG(flag, bit) (((flag) >> (bit)) & 1)
/* Useful for both fragment and data blocks */
#define SQFS_COMPRESSED_BLOCK(A) (!((A) & BIT(24)))
-/* SQFS_COMPRESSED_DATA strictly used with super block's 'flags' member */
-#define SQFS_COMPRESSED_DATA(A) (!((A) & 0x0002))
#define SQFS_IS_FRAGMENTED(A) ((A) != 0xFFFFFFFF)
/*
* These two macros work as getters for a metada block header, retrieving the
@@ -28,22 +25,4 @@
#define SQFS_COMPRESSED_METADATA(A) (!((A) & BIT(15)))
#define SQFS_METADATA_SIZE(A) ((A) & GENMASK(14, 0))
-struct squashfs_super_block_flags {
- /* check: unused
- * uncompressed_ids: not supported
- */
- bool uncompressed_inodes;
- bool uncompressed_data;
- bool check;
- bool uncompressed_frags;
- bool no_frags;
- bool always_frags;
- bool duplicates;
- bool exportable;
- bool uncompressed_xattrs;
- bool no_xattrs;
- bool compressor_options;
- bool uncompressed_ids;
-};
-
#endif /* SQFS_UTILS_H */
diff --git a/fs/ubifs/ubifs.h b/fs/ubifs/ubifs.h
index 67b13c8..b4e761c 100644
--- a/fs/ubifs/ubifs.h
+++ b/fs/ubifs/ubifs.h
@@ -68,7 +68,6 @@
void iput(struct inode *inode);
/* linux/include/time.h */
-#define NSEC_PER_SEC 1000000000L
#define get_seconds() 0
#define CURRENT_TIME_SEC ((struct timespec) { get_seconds(), 0 })
diff --git a/include/asm-generic/io.h b/include/asm-generic/io.h
index 7a2f0db..13d99cf 100644
--- a/include/asm-generic/io.h
+++ b/include/asm-generic/io.h
@@ -105,5 +105,353 @@
}
#endif
+/*
+ * __raw_{read,write}{b,w,l,q}() access memory in native endianness.
+ *
+ * On some architectures memory mapped IO needs to be accessed differently.
+ * On the simple architectures, we just read/write the memory location
+ * directly.
+ */
+
+#ifndef __raw_readb
+#define __raw_readb __raw_readb
+static inline u8 __raw_readb(const volatile void __iomem *addr)
+{
+ return *(const volatile u8 __force *)addr;
+}
+#endif
+
+#ifndef __raw_readw
+#define __raw_readw __raw_readw
+static inline u16 __raw_readw(const volatile void __iomem *addr)
+{
+ return *(const volatile u16 __force *)addr;
+}
+#endif
+
+#ifndef __raw_readl
+#define __raw_readl __raw_readl
+static inline u32 __raw_readl(const volatile void __iomem *addr)
+{
+ return *(const volatile u32 __force *)addr;
+}
+#endif
+
+#ifdef CONFIG_64BIT
+#ifndef __raw_readq
+#define __raw_readq __raw_readq
+static inline u64 __raw_readq(const volatile void __iomem *addr)
+{
+ return *(const volatile u64 __force *)addr;
+}
+#endif
+#endif /* CONFIG_64BIT */
+
+#ifndef __raw_writeb
+#define __raw_writeb __raw_writeb
+static inline void __raw_writeb(u8 value, volatile void __iomem *addr)
+{
+ *(volatile u8 __force *)addr = value;
+}
+#endif
+
+#ifndef __raw_writew
+#define __raw_writew __raw_writew
+static inline void __raw_writew(u16 value, volatile void __iomem *addr)
+{
+ *(volatile u16 __force *)addr = value;
+}
+#endif
+
+#ifndef __raw_writel
+#define __raw_writel __raw_writel
+static inline void __raw_writel(u32 value, volatile void __iomem *addr)
+{
+ *(volatile u32 __force *)addr = value;
+}
+#endif
+
+#ifdef CONFIG_64BIT
+#ifndef __raw_writeq
+#define __raw_writeq __raw_writeq
+static inline void __raw_writeq(u64 value, volatile void __iomem *addr)
+{
+ *(volatile u64 __force *)addr = value;
+}
+#endif
+#endif /* CONFIG_64BIT */
+
+/*
+ * {read,write}s{b,w,l,q}() repeatedly access the same memory address in
+ * native endianness in 8-, 16-, 32- or 64-bit chunks (@count times).
+ */
+#ifndef readsb
+#define readsb readsb
+static inline void readsb(const volatile void __iomem *addr, void *buffer,
+ unsigned int count)
+{
+ if (count) {
+ u8 *buf = buffer;
+
+ do {
+ u8 x = __raw_readb(addr);
+ *buf++ = x;
+ } while (--count);
+ }
+}
+#endif
+
+#ifndef readsw
+#define readsw readsw
+static inline void readsw(const volatile void __iomem *addr, void *buffer,
+ unsigned int count)
+{
+ if (count) {
+ u16 *buf = buffer;
+
+ do {
+ u16 x = __raw_readw(addr);
+ *buf++ = x;
+ } while (--count);
+ }
+}
+#endif
+
+#ifndef readsl
+#define readsl readsl
+static inline void readsl(const volatile void __iomem *addr, void *buffer,
+ unsigned int count)
+{
+ if (count) {
+ u32 *buf = buffer;
+
+ do {
+ u32 x = __raw_readl(addr);
+ *buf++ = x;
+ } while (--count);
+ }
+}
+#endif
+
+#ifdef CONFIG_64BIT
+#ifndef readsq
+#define readsq readsq
+static inline void readsq(const volatile void __iomem *addr, void *buffer,
+ unsigned int count)
+{
+ if (count) {
+ u64 *buf = buffer;
+
+ do {
+ u64 x = __raw_readq(addr);
+ *buf++ = x;
+ } while (--count);
+ }
+}
+#endif
+#endif /* CONFIG_64BIT */
+
+#ifndef writesb
+#define writesb writesb
+static inline void writesb(volatile void __iomem *addr, const void *buffer,
+ unsigned int count)
+{
+ if (count) {
+ const u8 *buf = buffer;
+
+ do {
+ __raw_writeb(*buf++, addr);
+ } while (--count);
+ }
+}
+#endif
+
+#ifndef writesw
+#define writesw writesw
+static inline void writesw(volatile void __iomem *addr, const void *buffer,
+ unsigned int count)
+{
+ if (count) {
+ const u16 *buf = buffer;
+
+ do {
+ __raw_writew(*buf++, addr);
+ } while (--count);
+ }
+}
+#endif
+
+#ifndef writesl
+#define writesl writesl
+static inline void writesl(volatile void __iomem *addr, const void *buffer,
+ unsigned int count)
+{
+ if (count) {
+ const u32 *buf = buffer;
+
+ do {
+ __raw_writel(*buf++, addr);
+ } while (--count);
+ }
+}
+#endif
+
+#ifdef CONFIG_64BIT
+#ifndef writesq
+#define writesq writesq
+static inline void writesq(volatile void __iomem *addr, const void *buffer,
+ unsigned int count)
+{
+ if (count) {
+ const u64 *buf = buffer;
+
+ do {
+ __raw_writeq(*buf++, addr);
+ } while (--count);
+ }
+}
+#endif
+#endif /* CONFIG_64BIT */
+
+#ifndef PCI_IOBASE
+#define PCI_IOBASE ((void __iomem *)0)
+#endif
+
+/*
+ * {in,out}s{b,w,l}{,_p}() are variants of the above that repeatedly access a
+ * single I/O port multiple times.
+ */
+
+#ifndef insb
+#define insb insb
+static inline void insb(unsigned long addr, void *buffer, unsigned int count)
+{
+ readsb(PCI_IOBASE + addr, buffer, count);
+}
+#endif
+
+#ifndef insw
+#define insw insw
+static inline void insw(unsigned long addr, void *buffer, unsigned int count)
+{
+ readsw(PCI_IOBASE + addr, buffer, count);
+}
+#endif
+
+#ifndef insl
+#define insl insl
+static inline void insl(unsigned long addr, void *buffer, unsigned int count)
+{
+ readsl(PCI_IOBASE + addr, buffer, count);
+}
+#endif
+
+#ifndef outsb
+#define outsb outsb
+static inline void outsb(unsigned long addr, const void *buffer,
+ unsigned int count)
+{
+ writesb(PCI_IOBASE + addr, buffer, count);
+}
+#endif
+
+#ifndef outsw
+#define outsw outsw
+static inline void outsw(unsigned long addr, const void *buffer,
+ unsigned int count)
+{
+ writesw(PCI_IOBASE + addr, buffer, count);
+}
+#endif
+
+#ifndef outsl
+#define outsl outsl
+static inline void outsl(unsigned long addr, const void *buffer,
+ unsigned int count)
+{
+ writesl(PCI_IOBASE + addr, buffer, count);
+}
+#endif
+
+#ifndef ioread8_rep
+#define ioread8_rep ioread8_rep
+static inline void ioread8_rep(const volatile void __iomem *addr, void *buffer,
+ unsigned int count)
+{
+ readsb(addr, buffer, count);
+}
+#endif
+
+#ifndef ioread16_rep
+#define ioread16_rep ioread16_rep
+static inline void ioread16_rep(const volatile void __iomem *addr,
+ void *buffer, unsigned int count)
+{
+ readsw(addr, buffer, count);
+}
+#endif
+
+#ifndef ioread32_rep
+#define ioread32_rep ioread32_rep
+static inline void ioread32_rep(const volatile void __iomem *addr,
+ void *buffer, unsigned int count)
+{
+ readsl(addr, buffer, count);
+}
+#endif
+
+#ifdef CONFIG_64BIT
+#ifndef ioread64_rep
+#define ioread64_rep ioread64_rep
+static inline void ioread64_rep(const volatile void __iomem *addr,
+ void *buffer, unsigned int count)
+{
+ readsq(addr, buffer, count);
+}
+#endif
+#endif /* CONFIG_64BIT */
+
+#ifndef iowrite8_rep
+#define iowrite8_rep iowrite8_rep
+static inline void iowrite8_rep(volatile void __iomem *addr,
+ const void *buffer,
+ unsigned int count)
+{
+ writesb(addr, buffer, count);
+}
+#endif
+
+#ifndef iowrite16_rep
+#define iowrite16_rep iowrite16_rep
+static inline void iowrite16_rep(volatile void __iomem *addr,
+ const void *buffer,
+ unsigned int count)
+{
+ writesw(addr, buffer, count);
+}
+#endif
+
+#ifndef iowrite32_rep
+#define iowrite32_rep iowrite32_rep
+static inline void iowrite32_rep(volatile void __iomem *addr,
+ const void *buffer,
+ unsigned int count)
+{
+ writesl(addr, buffer, count);
+}
+#endif
+
+#ifdef CONFIG_64BIT
+#ifndef iowrite64_rep
+#define iowrite64_rep iowrite64_rep
+static inline void iowrite64_rep(volatile void __iomem *addr,
+ const void *buffer,
+ unsigned int count)
+{
+ writesq(addr, buffer, count);
+}
+#endif
+#endif /* CONFIG_64BIT */
+
#endif /* !__ASSEMBLY__ */
#endif /* __ASM_GENERIC_IO_H__ */
diff --git a/include/axp_pmic.h b/include/axp_pmic.h
index 4ac6486..aabafc8 100644
--- a/include/axp_pmic.h
+++ b/include/axp_pmic.h
@@ -32,6 +32,7 @@
AXP209_ID,
AXP221_ID,
AXP223_ID,
+ AXP313_ID,
AXP803_ID,
AXP806_ID,
AXP809_ID,
diff --git a/include/bcb.h b/include/bcb.h
index 5edb17a..1941d8c 100644
--- a/include/bcb.h
+++ b/include/bcb.h
@@ -8,14 +8,69 @@
#ifndef __BCB_H__
#define __BCB_H__
+#include <part.h>
+
+enum bcb_field {
+ BCB_FIELD_COMMAND,
+ BCB_FIELD_STATUS,
+ BCB_FIELD_RECOVERY,
+ BCB_FIELD_STAGE
+};
+
#if IS_ENABLED(CONFIG_CMD_BCB)
-int bcb_write_reboot_reason(int devnum, char *partp, const char *reasonp);
+
+int bcb_find_partition_and_load(const char *iface,
+ int devnum, char *partp);
+int bcb_load(struct blk_desc *block_description,
+ struct disk_partition *disk_partition);
+int bcb_set(enum bcb_field field, const char *value);
+
+/**
+ * bcb_get() - get the field value.
+ * @field: field to get
+ * @value_out: buffer to copy bcb field value to
+ * @value_size: buffer size to avoid overflow in case
+ * value_out is smaller then the field value
+ */
+int bcb_get(enum bcb_field field, char *value_out, size_t value_size);
+
+int bcb_store(void);
+void bcb_reset(void);
+
#else
+
#include <linux/errno.h>
-static inline int bcb_write_reboot_reason(int devnum, char *partp, const char *reasonp)
+
+static inline int bcb_load(struct blk_desc *block_description,
+ struct disk_partition *disk_partition)
{
return -EOPNOTSUPP;
}
+
+static inline int bcb_find_partition_and_load(const char *iface,
+ int devnum, char *partp)
+{
+ return -EOPNOTSUPP;
+}
+
+static inline int bcb_set(enum bcb_field field, const char *value)
+{
+ return -EOPNOTSUPP;
+}
+
+static inline int bcb_get(enum bcb_field field, char *value_out)
+{
+ return -EOPNOTSUPP;
+}
+
+static inline int bcb_store(void)
+{
+ return -EOPNOTSUPP;
+}
+
+static inline void bcb_reset(void)
+{
+}
#endif
#endif /* __BCB_H__ */
diff --git a/include/blkmap.h b/include/blkmap.h
index af54583..30dc84a 100644
--- a/include/blkmap.h
+++ b/include/blkmap.h
@@ -7,6 +7,23 @@
#ifndef _BLKMAP_H
#define _BLKMAP_H
+#include <dm/lists.h>
+
+/**
+ * struct blkmap - Block map
+ *
+ * Data associated with a blkmap.
+ *
+ * @label: Human readable name of this blkmap
+ * @blk: Underlying block device
+ * @slices: List of slices associated with this blkmap
+ */
+struct blkmap {
+ char *label;
+ struct udevice *blk;
+ struct list_head slices;
+};
+
/**
* blkmap_map_linear() - Map region of other block device
*
@@ -74,4 +91,16 @@
*/
int blkmap_destroy(struct udevice *dev);
+/**
+ * blkmap_create_ramdisk() - Create new ramdisk with blkmap
+ *
+ * @label: Label of the new blkmap
+ * @image_addr: Target memory start address of this mapping
+ * @image_size: Target memory size of this mapping
+ * @devp: Updated with the address of the created blkmap device
+ * Returns: 0 on success, negative error code on failure
+ */
+int blkmap_create_ramdisk(const char *label, ulong image_addr, ulong image_size,
+ struct udevice **devp);
+
#endif /* _BLKMAP_H */
diff --git a/include/bootdev.h b/include/bootdev.h
index c136267..2cee883 100644
--- a/include/bootdev.h
+++ b/include/bootdev.h
@@ -66,7 +66,7 @@
*
* @info: Info structure describing this hunter
* @show: true to show information from the hunter
- * Returns: 0 if OK, -ve on error
+ * Returns: 0 if OK, -ENOENT on device not found, otherwise -ve on error
*/
typedef int (*bootdev_hunter_func)(struct bootdev_hunter *info, bool show);
diff --git a/include/bootflow.h b/include/bootflow.h
index 44d3741..fede8f2 100644
--- a/include/bootflow.h
+++ b/include/bootflow.h
@@ -43,9 +43,12 @@
* and it is using the prior-stage FDT, which is the U-Boot control FDT.
* This is only possible with the EFI bootmeth (distro-efi) and only when
* CONFIG_OF_HAS_PRIOR_STAGE is enabled
+ * @BOOTFLOWF_STATIC_BUF: Indicates that @bflow->buf is statically set, rather
+ * than being allocated by malloc().
*/
enum bootflow_flags_t {
BOOTFLOWF_USE_PRIOR_FDT = 1 << 0,
+ BOOTFLOWF_STATIC_BUF = 1 << 1,
};
/**
@@ -72,7 +75,7 @@
* @fname: Filename of bootflow file (allocated)
* @logo: Logo to display for this bootflow (BMP format)
* @logo_size: Size of the logo in bytes
- * @buf: Bootflow file contents (allocated)
+ * @buf: Bootflow file contents (allocated unless @flags & BOOTFLOWF_STATIC_BUF)
* @size: Size of bootflow file in bytes
* @err: Error number received (0 if OK)
* @os_name: Name of the OS / distro being booted, or NULL if not known
diff --git a/include/configs/am335x_evm.h b/include/configs/am335x_evm.h
index 504b1f0..67f4656 100644
--- a/include/configs/am335x_evm.h
+++ b/include/configs/am335x_evm.h
@@ -1,7 +1,7 @@
/*
* am335x_evm.h
*
- * Copyright (C) 2011 Texas Instruments Incorporated - http://www.ti.com/
+ * Copyright (C) 2011 Texas Instruments Incorporated - https://www.ti.com/
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
diff --git a/include/configs/am335x_shc.h b/include/configs/am335x_shc.h
index ee6f622..dedef91 100644
--- a/include/configs/am335x_shc.h
+++ b/include/configs/am335x_shc.h
@@ -6,7 +6,7 @@
* Based on:
* am335x_evm.h
*
- * Copyright (C) 2011 Texas Instruments Incorporated - http://www.ti.com/
+ * Copyright (C) 2011 Texas Instruments Incorporated - https://www.ti.com/
*/
#ifndef __CONFIG_AM335X_SHC_H
diff --git a/include/configs/am43xx_evm.h b/include/configs/am43xx_evm.h
index 7ee7b7e..9834289 100644
--- a/include/configs/am43xx_evm.h
+++ b/include/configs/am43xx_evm.h
@@ -2,7 +2,7 @@
/*
* am43xx_evm.h
*
- * Copyright (C) 2013 Texas Instruments Incorporated - http://www.ti.com/
+ * Copyright (C) 2013 Texas Instruments Incorporated - https://www.ti.com/
*/
#ifndef __CONFIG_AM43XX_EVM_H
diff --git a/include/configs/am65x_evm.h b/include/configs/am65x_evm.h
index 9e90239..811dc0f 100644
--- a/include/configs/am65x_evm.h
+++ b/include/configs/am65x_evm.h
@@ -2,7 +2,7 @@
/*
* Configuration header file for K3 AM654 EVM
*
- * Copyright (C) 2017-2018 Texas Instruments Incorporated - http://www.ti.com/
+ * Copyright (C) 2017-2018 Texas Instruments Incorporated - https://www.ti.com/
* Lokesh Vutla <lokeshvutla@ti.com>
*/
diff --git a/include/configs/baltos.h b/include/configs/baltos.h
index e794638..cc54b51 100644
--- a/include/configs/baltos.h
+++ b/include/configs/baltos.h
@@ -1,7 +1,7 @@
/*
* am335x_evm.h
*
- * Copyright (C) 2011 Texas Instruments Incorporated - http://www.ti.com/
+ * Copyright (C) 2011 Texas Instruments Incorporated - https://www.ti.com/
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
diff --git a/include/configs/da850evm.h b/include/configs/da850evm.h
index cef4042..416aa96 100644
--- a/include/configs/da850evm.h
+++ b/include/configs/da850evm.h
@@ -1,6 +1,6 @@
/* SPDX-License-Identifier: GPL-2.0+ */
/*
- * Copyright (C) 2010 Texas Instruments Incorporated - http://www.ti.com/
+ * Copyright (C) 2010 Texas Instruments Incorporated - https://www.ti.com/
*
* Based on davinci_dvevm.h. Original Copyrights follow:
*
diff --git a/include/configs/etamin.h b/include/configs/draco-etamin.h
similarity index 98%
rename from include/configs/etamin.h
rename to include/configs/draco-etamin.h
index d07b4e9..97585a4 100644
--- a/include/configs/etamin.h
+++ b/include/configs/draco-etamin.h
@@ -6,7 +6,7 @@
* Based on:
* U-Boot file:/include/configs/am335x_evm.h
*
- * Copyright (C) 2011 Texas Instruments Incorporated - http://www.ti.com/
+ * Copyright (C) 2011 Texas Instruments Incorporated - https://www.ti.com/
*/
#ifndef __CONFIG_ETAMIN_H
diff --git a/include/configs/rastaban.h b/include/configs/draco-rastaban.h
similarity index 93%
rename from include/configs/rastaban.h
rename to include/configs/draco-rastaban.h
index 2efb4d2..0991ebf 100644
--- a/include/configs/rastaban.h
+++ b/include/configs/draco-rastaban.h
@@ -6,7 +6,7 @@
* Based on:
* U-Boot file:/include/configs/am335x_evm.h
*
- * Copyright (C) 2011 Texas Instruments Incorporated - http://www.ti.com/
+ * Copyright (C) 2011 Texas Instruments Incorporated - https://www.ti.com/
*/
#ifndef __CONFIG_RASTABAN_H
diff --git a/include/configs/thuban.h b/include/configs/draco-thuban.h
similarity index 92%
rename from include/configs/thuban.h
rename to include/configs/draco-thuban.h
index a5913e1..f4c04c5 100644
--- a/include/configs/thuban.h
+++ b/include/configs/draco-thuban.h
@@ -6,7 +6,7 @@
* Based on:
* U-Boot file:/include/configs/am335x_evm.h
*
- * Copyright (C) 2011 Texas Instruments Incorporated - http://www.ti.com/
+ * Copyright (C) 2011 Texas Instruments Incorporated - https://www.ti.com/
*/
#ifndef __CONFIG_THUBAN_H
diff --git a/include/configs/draco.h b/include/configs/draco.h
deleted file mode 100644
index 4c67174..0000000
--- a/include/configs/draco.h
+++ /dev/null
@@ -1,41 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0+ */
-/*
- * (C) Copyright 2013 Siemens Schweiz AG
- * (C) Heiko Schocher, DENX Software Engineering, hs@denx.de.
- *
- * Based on:
- * U-Boot file:/include/configs/am335x_evm.h
- *
- * Copyright (C) 2011 Texas Instruments Incorporated - http://www.ti.com/
- */
-
-#ifndef __CONFIG_DRACO_H
-#define __CONFIG_DRACO_H
-
-#include "siemens-am33x-common.h"
-
-#define DDR_PLL_FREQ 303
-
-#define BOARD_DFU_BUTTON_GPIO 27 /* Use as default */
-#define GPIO_LAN9303_NRST 88 /* GPIO2_24 = gpio88 */
-
-#define CFG_ENV_SETTINGS_BUTTONS_AND_LEDS \
- "button_dfu0=27\0" \
- "led0=103,1,0\0" \
- "led1=64,0,1\0"
-
- /* Physical Memory Map */
-#define CFG_MAX_RAM_BANK_SIZE (1024 << 20) /* 1GB */
-
-/* Default env settings */
-#define CFG_EXTRA_ENV_SETTINGS \
- "hostname=draco\0" \
- "ubi_off=2048\0"\
- "nand_img_size=0x400000\0" \
- "optargs=\0" \
- "preboot=draco_led 0\0" \
- CFG_ENV_SETTINGS_BUTTONS_AND_LEDS \
- CFG_ENV_SETTINGS_V2 \
- CFG_ENV_SETTINGS_NAND_V2
-
-#endif /* ! __CONFIG_DRACO_H */
diff --git a/include/configs/legoev3.h b/include/configs/legoev3.h
index ff96658..a50f948 100644
--- a/include/configs/legoev3.h
+++ b/include/configs/legoev3.h
@@ -4,7 +4,7 @@
*
* Based on da850evm.h
*
- * Copyright (C) 2010 Texas Instruments Incorporated - http://www.ti.com/
+ * Copyright (C) 2010 Texas Instruments Incorporated - https://www.ti.com/
*
* Based on davinci_dvevm.h. Original Copyrights follow:
*
diff --git a/include/configs/mvebu_armada-37xx.h b/include/configs/mvebu_armada-37xx.h
index 76e148f..18b55be 100644
--- a/include/configs/mvebu_armada-37xx.h
+++ b/include/configs/mvebu_armada-37xx.h
@@ -30,7 +30,6 @@
/*
* Environment
*/
-#define DEFAULT_ENV_IS_RW /* required for configuring default fdtfile= */
#ifdef CONFIG_MMC
#define BOOT_TARGET_DEVICES_MMC(func, i) func(MMC, mmc, i)
diff --git a/include/configs/omap3_evm.h b/include/configs/omap3_evm.h
index f449677..2cb2e52 100644
--- a/include/configs/omap3_evm.h
+++ b/include/configs/omap3_evm.h
@@ -2,7 +2,7 @@
/*
* Configuration settings for the TI OMAP3 EVM board.
*
- * Copyright (C) 2006-2011 Texas Instruments Incorporated - http://www.ti.com/
+ * Copyright (C) 2006-2011 Texas Instruments Incorporated - https://www.ti.com/
*
* Author :
* Manikandan Pillai <mani.pillai@ti.com>
diff --git a/include/configs/omapl138_lcdk.h b/include/configs/omapl138_lcdk.h
index fc2655a..5b7eb0b 100644
--- a/include/configs/omapl138_lcdk.h
+++ b/include/configs/omapl138_lcdk.h
@@ -1,6 +1,6 @@
/* SPDX-License-Identifier: GPL-2.0 */
/*
- * Copyright (C) 2010 Texas Instruments Incorporated - http://www.ti.com/
+ * Copyright (C) 2010 Texas Instruments Incorporated - https://www.ti.com/
*
* Based on davinci_dvevm.h. Original Copyrights follow:
*
diff --git a/include/configs/pdu001.h b/include/configs/pdu001.h
index 80b14b0..24d7dcd 100644
--- a/include/configs/pdu001.h
+++ b/include/configs/pdu001.h
@@ -4,7 +4,7 @@
*
* Copyright (C) 2018 EETS GmbH - http://www.eets.ch/
*
- * Copyright (C) 2011 Texas Instruments Incorporated - http://www.ti.com/
+ * Copyright (C) 2011 Texas Instruments Incorporated - https://www.ti.com/
*/
#ifndef __CONFIG_PDU001_H
diff --git a/include/configs/phycore_am335x_r2.h b/include/configs/phycore_am335x_r2.h
index 8668da6..060a150 100644
--- a/include/configs/phycore_am335x_r2.h
+++ b/include/configs/phycore_am335x_r2.h
@@ -4,7 +4,7 @@
*
* Phytec phyCORE-AM335x R2 (PCL060 / PCM060) boards information header
*
- * Copyright (C) 2011, Texas Instruments, Incorporated - http://www.ti.com/
+ * Copyright (C) 2011, Texas Instruments, Incorporated - https://www.ti.com/
* Copyright (C) 2013 Lars Poeschel, Lemonage Software GmbH
* Copyright (C) 2019 DENX Software Engineering GmbH
*/
diff --git a/include/configs/poplar.h b/include/configs/poplar.h
index 6e8adf9..629b335 100644
--- a/include/configs/poplar.h
+++ b/include/configs/poplar.h
@@ -37,11 +37,11 @@
"env_mmc_blknum=0xf80\0" \
"env_mmc_nblks=0x80\0" \
"kernel_addr_r=0x30000000\0" \
- "pxefile_addr_r=0x32000000\0" \
- "scriptaddr=0x32000000\0" \
- "fdt_addr_r=0x32200000\0" \
+ "pxefile_addr_r=0x33000000\0" \
+ "scriptaddr=0x33000000\0" \
+ "fdt_addr_r=0x33200000\0" \
"fdtfile=hisilicon/hi3798cv200-poplar.dtb\0" \
- "ramdisk_addr_r=0x32400000\0" \
+ "ramdisk_addr_r=0x33400000\0" \
BOOTENV
#endif /* _POPLAR_H_ */
diff --git a/include/configs/pxm2.h b/include/configs/pxm2.h
index b701e52..040178b 100644
--- a/include/configs/pxm2.h
+++ b/include/configs/pxm2.h
@@ -7,7 +7,7 @@
* Based on:
* U-Boot file:/include/configs/am335x_evm.h
*
- * Copyright (C) 2011 Texas Instruments Incorporated - http://www.ti.com/
+ * Copyright (C) 2011 Texas Instruments Incorporated - https://www.ti.com/
*/
#ifndef __CONFIG_PXM2_H
diff --git a/include/configs/quartzpro64-rk3588.h b/include/configs/quartzpro64-rk3588.h
new file mode 100644
index 0000000..a1faa2a
--- /dev/null
+++ b/include/configs/quartzpro64-rk3588.h
@@ -0,0 +1,14 @@
+/* SPDX-License-Identifier: GPL-2.0+
+ * Copyright 2023 Google, Inc
+ */
+
+#ifndef __QUARTZPRO64_RK3588_H
+#define __QUARTZPRO64_RK3588_H
+
+#define ROCKCHIP_DEVICE_SETTINGS \
+ "stdout=serial,vidconsole\0" \
+ "stderr=serial,vidconsole\0"
+
+#include <configs/rk3588_common.h>
+
+#endif /* __QUARTZPRO64_RK3588_H */
diff --git a/include/configs/rut.h b/include/configs/rut.h
index 4002bc4..7cc2bd5 100644
--- a/include/configs/rut.h
+++ b/include/configs/rut.h
@@ -7,7 +7,7 @@
* Based on:
* U-Boot file:/include/configs/am335x_evm.h
*
- * Copyright (C) 2011 Texas Instruments Incorporated - http://www.ti.com/
+ * Copyright (C) 2011 Texas Instruments Incorporated - https://www.ti.com/
*/
#ifndef __CONFIG_RUT_H
diff --git a/include/configs/siemens-am33x-common.h b/include/configs/siemens-am33x-common.h
index 7def657..6b1d5ca 100644
--- a/include/configs/siemens-am33x-common.h
+++ b/include/configs/siemens-am33x-common.h
@@ -7,7 +7,7 @@
* Based on:
* U-Boot file:/include/configs/am335x_evm.h
*
- * Copyright (C) 2011 Texas Instruments Incorporated - http://www.ti.com/
+ * Copyright (C) 2011 Texas Instruments Incorporated - https://www.ti.com/
*/
#ifndef __CONFIG_SIEMENS_AM33X_COMMON_H
diff --git a/include/configs/ti_am335x_common.h b/include/configs/ti_am335x_common.h
index 20f8643..c827a9c 100644
--- a/include/configs/ti_am335x_common.h
+++ b/include/configs/ti_am335x_common.h
@@ -2,10 +2,10 @@
/*
* ti_am335x_common.h
*
- * Copyright (C) 2013 Texas Instruments Incorporated - http://www.ti.com/
+ * Copyright (C) 2013 Texas Instruments Incorporated - https://www.ti.com/
*
* For more details, please see the technical documents listed at
- * http://www.ti.com/product/am3359#technicaldocuments
+ * https://www.ti.com/product/am3359#technicaldocuments
*/
#ifndef __CONFIG_TI_AM335X_COMMON_H__
diff --git a/include/configs/ti_armv7_common.h b/include/configs/ti_armv7_common.h
index 4e30d0d..3def7b1 100644
--- a/include/configs/ti_armv7_common.h
+++ b/include/configs/ti_armv7_common.h
@@ -2,7 +2,7 @@
/*
* ti_armv7_common.h
*
- * Copyright (C) 2013 Texas Instruments Incorporated - http://www.ti.com/
+ * Copyright (C) 2013 Texas Instruments Incorporated - https://www.ti.com/
*
* The various ARMv7 SoCs from TI all share a number of IP blocks when
* implementing a given feature. Rather than define these in every
diff --git a/include/configs/ti_armv7_keystone2.h b/include/configs/ti_armv7_keystone2.h
index 72c04d8..b36207c 100644
--- a/include/configs/ti_armv7_keystone2.h
+++ b/include/configs/ti_armv7_keystone2.h
@@ -9,23 +9,10 @@
#ifndef __CONFIG_KS2_EVM_H
#define __CONFIG_KS2_EVM_H
-/* U-Boot Build Configuration */
-
-/* SoC Configuration */
-
/* Memory Configuration */
#define CFG_SYS_LPAE_SDRAM_BASE 0x800000000
#define CFG_MAX_RAM_BANK_SIZE (2 << 30) /* 2GB */
-#ifdef CONFIG_SYS_MALLOC_F_LEN
-#define SPL_MALLOC_F_SIZE CONFIG_SYS_MALLOC_F_LEN
-#else
-#define SPL_MALLOC_F_SIZE 0
-#endif
-
-/* SPL SPI Loader Configuration */
-#define KEYSTONE_SPL_STACK_SIZE (8 * 1024)
-
/* SRAM scratch space entries */
#define SRAM_SCRATCH_SPACE_ADDR 0xc0c23fc
@@ -53,8 +40,6 @@
#define CFG_KSNET_SERDES_SGMII2_BASE KS2_SGMII_SERDES2_BASE
#define CFG_KSNET_SERDES_LANES_PER_SGMII KS2_LANES_PER_SGMII_SERDES
-/* EEPROM definitions */
-
/* NAND Configuration */
#define CFG_SYS_NAND_MASK_CLE 0x4000
#define CFG_SYS_NAND_MASK_ALE 0x2000
@@ -63,18 +48,10 @@
#define CFG_SYS_NAND_LARGEPAGE
#define CFG_SYS_NAND_BASE_LIST { 0x30000000, }
-
-
-/* U-Boot general configuration */
-
-/* EDMA3 */
-
-
/* Now for the remaining common defines */
#include <configs/ti_armv7_common.h>
/* we may include files below only after all above definitions */
-#include <asm/arch/hardware.h>
#include <asm/arch/clock.h>
#ifndef CONFIG_SOC_K2G
#define CFG_SYS_HZ_CLOCK ks_clk_get_rate(KS2_CLK1_6)
diff --git a/include/configs/ti_armv7_omap.h b/include/configs/ti_armv7_omap.h
index d34042a..0b8b1ac 100644
--- a/include/configs/ti_armv7_omap.h
+++ b/include/configs/ti_armv7_omap.h
@@ -2,7 +2,7 @@
/*
* ti_armv7_omap.h
*
- * Copyright (C) 2015 Texas Instruments Incorporated - http://www.ti.com/
+ * Copyright (C) 2015 Texas Instruments Incorporated - https://www.ti.com/
*
* The various ARMv7 SoCs from TI all share a number of IP blocks when
* implementing a given feature. This is meant to isolate the features
diff --git a/include/configs/ti_omap3_common.h b/include/configs/ti_omap3_common.h
index 36a05b6..45f7179 100644
--- a/include/configs/ti_omap3_common.h
+++ b/include/configs/ti_omap3_common.h
@@ -2,12 +2,12 @@
/*
* ti_omap3_common.h
*
- * Copyright (C) 2013 Texas Instruments Incorporated - http://www.ti.com/
+ * Copyright (C) 2013 Texas Instruments Incorporated - https://www.ti.com/
*
* For more details, please see the technical documents listed at
- * http://www.ti.com/product/omap3530
- * http://www.ti.com/product/omap3630
- * http://www.ti.com/product/dm3730
+ * https://www.ti.com/product/omap3530
+ * https://www.ti.com/product/omap3630
+ * https://www.ti.com/product/dm3730
*/
#ifndef __CONFIG_TI_OMAP3_COMMON_H__
diff --git a/include/configs/ti_omap5_common.h b/include/configs/ti_omap5_common.h
index 4e5aa74..26494ae 100644
--- a/include/configs/ti_omap5_common.h
+++ b/include/configs/ti_omap5_common.h
@@ -10,7 +10,7 @@
* TI OMAP5 AND DRA7XX common configuration settings
*
* For more details, please see the technical documents listed at
- * http://www.ti.com/product/omap5432
+ * https://www.ti.com/product/omap5432
*/
#ifndef __CONFIG_TI_OMAP5_COMMON_H
diff --git a/include/cpsw.h b/include/cpsw.h
index 786f8b3..5e05099 100644
--- a/include/cpsw.h
+++ b/include/cpsw.h
@@ -1,7 +1,7 @@
/*
* CPSW Ethernet Switch Driver
*
- * Copyright (C) 2010 Texas Instruments Incorporated - http://www.ti.com/
+ * Copyright (C) 2010 Texas Instruments Incorporated - https://www.ti.com/
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
diff --git a/include/dfu.h b/include/dfu.h
index 68b5ca4..2f42781 100644
--- a/include/dfu.h
+++ b/include/dfu.h
@@ -98,7 +98,12 @@
int dev_num;
};
+
+#if defined(CONFIG_DFU_NAME_MAX_SIZE)
+#define DFU_NAME_SIZE CONFIG_DFU_NAME_MAX_SIZE
+#else
#define DFU_NAME_SIZE 32
+#endif
#ifndef DFU_DEFAULT_POLL_TIMEOUT
#define DFU_DEFAULT_POLL_TIMEOUT 0
#endif
diff --git a/include/dm/ofnode.h b/include/dm/ofnode.h
index 19e97a9..5795115 100644
--- a/include/dm/ofnode.h
+++ b/include/dm/ofnode.h
@@ -977,12 +977,22 @@
ofnode ofnode_get_chosen_node(const char *propname);
/**
- * ofnode_read_aliases_prop() - get the value of a aliases property
+ * ofnode_read_baud() - get the baudrate from string value of chosen property
*
- * This looks for a property within the /aliases node and returns its value
+ * This looks for stdout-path property within the /chosen node and parses its
+ * value to return baudrate.
*
* This only works with the control FDT.
*
+ * Return: baudrate value if found, else -ve error code
+ */
+int ofnode_read_baud(void);
+
+/**
+ * ofnode_read_aliases_prop() - get the value of a aliases property
+ *
+ * This looks for a property within the /aliases node and returns its value
+ *
* @propname: Property name to look for
* @sizep: Returns size of property, or `FDT_ERR_...` error code if function
* returns NULL
diff --git a/include/dm/util.h b/include/dm/util.h
index 89206cc..95c3527 100644
--- a/include/dm/util.h
+++ b/include/dm/util.h
@@ -11,9 +11,7 @@
#if CONFIG_IS_ENABLED(DM_WARN)
#define dm_warn(fmt...) log(LOGC_DM, LOGL_WARNING, ##fmt)
#else
-static inline void dm_warn(const char *fmt, ...)
-{
-}
+#define dm_warn(fmt...) log(LOGC_DM, LOGL_DEBUG, ##fmt)
#endif
struct list_head;
diff --git a/include/dt-bindings/net/mscc-phy-vsc8531.h b/include/dt-bindings/net/mscc-phy-vsc8531.h
index 61f5287..c340437 100644
--- a/include/dt-bindings/net/mscc-phy-vsc8531.h
+++ b/include/dt-bindings/net/mscc-phy-vsc8531.h
@@ -28,13 +28,4 @@
#define VSC8531_FORCE_LED_OFF 14
#define VSC8531_FORCE_LED_ON 15
-#define VSC8531_RGMII_CLK_DELAY_0_2_NS 0
-#define VSC8531_RGMII_CLK_DELAY_0_8_NS 1
-#define VSC8531_RGMII_CLK_DELAY_1_1_NS 2
-#define VSC8531_RGMII_CLK_DELAY_1_7_NS 3
-#define VSC8531_RGMII_CLK_DELAY_2_0_NS 4
-#define VSC8531_RGMII_CLK_DELAY_2_3_NS 5
-#define VSC8531_RGMII_CLK_DELAY_2_6_NS 6
-#define VSC8531_RGMII_CLK_DELAY_3_4_NS 7
-
#endif
diff --git a/include/dt-bindings/phy/nuvoton,npcm-usbphy.h b/include/dt-bindings/phy/nuvoton,npcm-usbphy.h
new file mode 100644
index 0000000..46946d3
--- /dev/null
+++ b/include/dt-bindings/phy/nuvoton,npcm-usbphy.h
@@ -0,0 +1,14 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+// Copyright (c) 2023 Nuvoton Technology corporation.
+
+#ifndef _DT_BINDINGS_NPCM_USBPHY_H
+#define _DT_BINDINGS_NPCM_USBPHY_H
+
+#define NPCM_UDC0_7 0
+#define NPCM_UDC8 1
+#define NPCM_UDC9 2
+#define NPCM_USBH1 3
+#define NPCM_USBH2 4
+#define NPCM_MAX_USB_CTRL_ID 4
+
+#endif
diff --git a/include/dt-bindings/pinctrl/dra.h b/include/dt-bindings/pinctrl/dra.h
index b543eeb..765c385 100644
--- a/include/dt-bindings/pinctrl/dra.h
+++ b/include/dt-bindings/pinctrl/dra.h
@@ -1,7 +1,7 @@
/*
* This header provides constants for DRA pinctrl bindings.
*
- * Copyright (C) 2013 Texas Instruments Incorporated - http://www.ti.com/
+ * Copyright (C) 2013 Texas Instruments Incorporated - https://www.ti.com/
* Author: Rajendra Nayak <rnayak@ti.com>
*
* This program is free software; you can redistribute it and/or modify
diff --git a/include/dt-bindings/reset/ti-syscon.h b/include/dt-bindings/reset/ti-syscon.h
index 884fd91..1427ff1 100644
--- a/include/dt-bindings/reset/ti-syscon.h
+++ b/include/dt-bindings/reset/ti-syscon.h
@@ -1,7 +1,7 @@
/*
* TI Syscon Reset definitions
*
- * Copyright (C) 2015-2016 Texas Instruments Incorporated - http://www.ti.com/
+ * Copyright (C) 2015-2016 Texas Instruments Incorporated - https://www.ti.com/
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
diff --git a/include/dwc3-omap-uboot.h b/include/dwc3-omap-uboot.h
index 9e0e717..ed92bfc 100644
--- a/include/dwc3-omap-uboot.h
+++ b/include/dwc3-omap-uboot.h
@@ -1,7 +1,7 @@
/* SPDX-License-Identifier: GPL-2.0 */
/* include/dwc3_omap_uboot.h
*
- * Copyright (c) 2015 Texas Instruments Incorporated - http://www.ti.com
+ * Copyright (c) 2015 Texas Instruments Incorporated - https://www.ti.com
*
* Designware SuperSpeed OMAP Glue uboot init
*/
diff --git a/include/dwc3-uboot.h b/include/dwc3-uboot.h
index bb0436c..35cfbb9 100644
--- a/include/dwc3-uboot.h
+++ b/include/dwc3-uboot.h
@@ -1,7 +1,7 @@
/* SPDX-License-Identifier: GPL-2.0 */
/* include/dwc3-uboot.h
*
- * Copyright (c) 2015 Texas Instruments Incorporated - http://www.ti.com
+ * Copyright (c) 2015 Texas Instruments Incorporated - https://www.ti.com
*
* Designware SuperSpeed USB uboot init
*/
diff --git a/include/efi_api.h b/include/efi_api.h
index 8f5ef5f..0e92cb8 100644
--- a/include/efi_api.h
+++ b/include/efi_api.h
@@ -192,7 +192,7 @@
struct efi_event *event,
void *context),
void *notify_context,
- efi_guid_t *event_group,
+ const efi_guid_t *event_group,
struct efi_event **event);
};
@@ -404,6 +404,9 @@
#define EFI_EVENT_GROUP_RESET_SYSTEM \
EFI_GUID(0x62da6a56, 0x13fb, 0x485a, 0xa8, 0xda, \
0xa3, 0xdd, 0x79, 0x12, 0xcb, 0x6b)
+#define EFI_EVENT_GROUP_RETURN_TO_EFIBOOTMGR \
+ EFI_GUID(0xb4a40fe6, 0x9149, 0x4f29, 0x94, 0x47, \
+ 0x49, 0x38, 0x7a, 0x7f, 0xab, 0x87)
/* EFI Configuration Table and GUID definitions */
#define NULL_GUID \
diff --git a/include/efi_loader.h b/include/efi_loader.h
index 247be06..664dae2 100644
--- a/include/efi_loader.h
+++ b/include/efi_loader.h
@@ -289,6 +289,8 @@
extern const efi_guid_t efi_guid_event_group_ready_to_boot;
/* event group ResetSystem() invoked (before ExitBootServices) */
extern const efi_guid_t efi_guid_event_group_reset_system;
+/* event group return to efibootmgr */
+extern const efi_guid_t efi_guid_event_group_return_to_efibootmgr;
/* GUID of the device tree table */
extern const efi_guid_t efi_guid_fdt;
extern const efi_guid_t efi_guid_loaded_image;
@@ -684,7 +686,7 @@
void (EFIAPI *notify_function) (
struct efi_event *event,
void *context),
- void *notify_context, efi_guid_t *group,
+ void *notify_context, const efi_guid_t *group,
struct efi_event **event);
/* Call this to set a timer */
efi_status_t efi_set_timer(struct efi_event *event, enum efi_timer_delay type,
diff --git a/include/env/ti/dfu.h b/include/env/ti/dfu.h
index 3c90570..10bcf33 100644
--- a/include/env/ti/dfu.h
+++ b/include/env/ti/dfu.h
@@ -1,6 +1,6 @@
/* SPDX-License-Identifier: GPL-2.0+ */
/*
- * Copyright (C) 2016 Texas Instruments Incorporated - http://www.ti.com
+ * Copyright (C) 2016 Texas Instruments Incorporated - https://www.ti.com
*
* Environment variable definitions for DFU on TI boards.
*/
diff --git a/include/env/ti/k3_dfu.h b/include/env/ti/k3_dfu.h
index a16a3ad..098f5f5 100644
--- a/include/env/ti/k3_dfu.h
+++ b/include/env/ti/k3_dfu.h
@@ -1,6 +1,6 @@
/* SPDX-License-Identifier: GPL-2.0+ */
/*
- * Copyright (C) 2019 Texas Instruments Incorporated - http://www.ti.com
+ * Copyright (C) 2019 Texas Instruments Incorporated - https://www.ti.com
*
* Environment variable definitions for DFU on TI K3 SoCs.
*
diff --git a/include/env/ti/k3_rproc.h b/include/env/ti/k3_rproc.h
index 3418cb4..a467d75 100644
--- a/include/env/ti/k3_rproc.h
+++ b/include/env/ti/k3_rproc.h
@@ -1,6 +1,6 @@
/* SPDX-License-Identifier: GPL-2.0+ */
/*
- * Copyright (C) 2019 Texas Instruments Incorporated - http://www.ti.com
+ * Copyright (C) 2019 Texas Instruments Incorporated - https://www.ti.com
*
* rproc environment variable definitions for various TI K3 SoCs.
*/
diff --git a/include/env/ti/mmc.h b/include/env/ti/mmc.h
index 769ea9d..d07189b 100644
--- a/include/env/ti/mmc.h
+++ b/include/env/ti/mmc.h
@@ -1,6 +1,6 @@
/* SPDX-License-Identifier: GPL-2.0+ */
/*
- * Copyright (C) 2017 Texas Instruments Incorporated - http://www.ti.com
+ * Copyright (C) 2017 Texas Instruments Incorporated - https://www.ti.com
*
* Environment variable definitions for MMC/SD on TI boards.
*/
diff --git a/include/env/ti/nand.h b/include/env/ti/nand.h
index 7d00afa..0e0da45 100644
--- a/include/env/ti/nand.h
+++ b/include/env/ti/nand.h
@@ -1,6 +1,6 @@
/* SPDX-License-Identifier: GPL-2.0+ */
/*
- * Copyright (C) 2019 Texas Instruments Incorporated - http://www.ti.com
+ * Copyright (C) 2019 Texas Instruments Incorporated - https://www.ti.com
*
* Environment variable definitions for NAND on TI boards.
*/
diff --git a/include/env/ti/ufs.h b/include/env/ti/ufs.h
index 6619ec9..c192f3a 100644
--- a/include/env/ti/ufs.h
+++ b/include/env/ti/ufs.h
@@ -1,6 +1,6 @@
/* SPDX-License-Identifier: GPL-2.0+ */
/*
- * Copyright (C) 2019 Texas Instruments Incorporated - http://www.ti.com
+ * Copyright (C) 2019 Texas Instruments Incorporated - https://www.ti.com
*
* Environment variable definitions for UFS on TI boards.
*/
diff --git a/include/env_default.h b/include/env_default.h
index b16c22d..2ca4a08 100644
--- a/include/env_default.h
+++ b/include/env_default.h
@@ -21,7 +21,7 @@
{
#elif defined(DEFAULT_ENV_INSTANCE_STATIC)
static char default_environment[] = {
-#elif defined(DEFAULT_ENV_IS_RW)
+#elif defined(CONFIG_DEFAULT_ENV_IS_RW)
char default_environment[] = {
#else
const char default_environment[] = {
@@ -42,7 +42,7 @@
#if defined(CONFIG_BOOTDELAY)
"bootdelay=" __stringify(CONFIG_BOOTDELAY) "\0"
#endif
-#if defined(CONFIG_BAUDRATE) && (CONFIG_BAUDRATE >= 0)
+#if !defined(CONFIG_OF_SERIAL_BAUD) && defined(CONFIG_BAUDRATE) && (CONFIG_BAUDRATE >= 0)
"baudrate=" __stringify(CONFIG_BAUDRATE) "\0"
#endif
#ifdef CONFIG_LOADS_ECHO
@@ -119,6 +119,10 @@
#ifdef CFG_EXTRA_ENV_SETTINGS
CFG_EXTRA_ENV_SETTINGS
#endif
+#ifdef CONFIG_OF_SERIAL_BAUD
+ /* Padding for baudrate at the end when environment is writable */
+ "\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0"
+#endif
"\0"
#else /* CONFIG_USE_DEFAULT_ENV_FILE */
#include "generated/defaultenv_autogenerated.h"
diff --git a/include/env_internal.h b/include/env_internal.h
index ae7816d..5c289d6 100644
--- a/include/env_internal.h
+++ b/include/env_internal.h
@@ -89,7 +89,7 @@
extern env_t embedded_environment;
#endif /* ENV_IS_EMBEDDED */
-#ifdef DEFAULT_ENV_IS_RW
+#ifdef CONFIG_DEFAULT_ENV_IS_RW
extern char default_environment[];
#else
extern const char default_environment[];
diff --git a/include/ext4fs.h b/include/ext4fs.h
index dd66d27..d96edfd 100644
--- a/include/ext4fs.h
+++ b/include/ext4fs.h
@@ -147,7 +147,7 @@
struct ext_filesystem *get_fs(void);
int ext4fs_open(const char *filename, loff_t *len);
int ext4fs_read(char *buf, loff_t offset, loff_t len, loff_t *actread);
-int ext4fs_mount(unsigned part_length);
+int ext4fs_mount(void);
void ext4fs_close(void);
void ext4fs_reinit_global(void);
int ext4fs_ls(const char *dirname);
diff --git a/include/fat.h b/include/fat.h
index a9756fb..3dce99a 100644
--- a/include/fat.h
+++ b/include/fat.h
@@ -34,12 +34,6 @@
/* Maximum number of entry for long file name according to spec */
#define MAX_LFN_SLOT 20
-/* Filesystem identifiers */
-#define FAT12_SIGN "FAT12 "
-#define FAT16_SIGN "FAT16 "
-#define FAT32_SIGN "FAT32 "
-#define SIGNLEN 8
-
/* File attributes */
#define ATTR_RO 1
#define ATTR_HIDDEN 2
diff --git a/include/generic-phy.h b/include/generic-phy.h
index bee4de8..eaab749 100644
--- a/include/generic-phy.h
+++ b/include/generic-phy.h
@@ -1,6 +1,6 @@
/* SPDX-License-Identifier: GPL-2.0+ */
/*
- * Copyright (C) 2017 Texas Instruments Incorporated - http://www.ti.com/
+ * Copyright (C) 2017 Texas Instruments Incorporated - https://www.ti.com/
* Written by Jean-Jacques Hiblot <jjhiblot@ti.com>
*/
diff --git a/include/init.h b/include/init.h
index d57a24f..9a1951d 100644
--- a/include/init.h
+++ b/include/init.h
@@ -292,6 +292,17 @@
/* common/board_info.c */
int checkboard(void);
+
+/**
+ * show_board_info() - Show board information
+ *
+ * Check sysinfo for board information. Failing that if the root node of the DTB
+ * has a "model" property, show it.
+ *
+ * Then call checkboard().
+ *
+ * Return 0 if OK, -ve on error
+ */
int show_board_info(void);
/**
diff --git a/include/k3-avs.h b/include/k3-avs.h
index e3c3caf..1014d5d 100644
--- a/include/k3-avs.h
+++ b/include/k3-avs.h
@@ -2,7 +2,7 @@
/*
* Texas Instruments' K3 Adaptive Voltage Scaling driver
*
- * Copyright (C) 2019 Texas Instruments Incorporated - http://www.ti.com/
+ * Copyright (C) 2019 Texas Instruments Incorporated - https://www.ti.com/
* Tero Kristo <t-kristo@ti.com>
*
*/
diff --git a/include/k3-clk.h b/include/k3-clk.h
index 49ba53d..1b6ab8f 100644
--- a/include/k3-clk.h
+++ b/include/k3-clk.h
@@ -1,6 +1,6 @@
/* SPDX-License-Identifier: GPL-2.0+ */
/*
- * (C) Copyright 2020-2021 Texas Instruments Incorporated - http://www.ti.com
+ * (C) Copyright 2020-2021 Texas Instruments Incorporated - https://www.ti.com
* Tero Kristo <t-kristo@ti.com>
*/
diff --git a/include/k3-dev.h b/include/k3-dev.h
index d288ae3..072e10b 100644
--- a/include/k3-dev.h
+++ b/include/k3-dev.h
@@ -2,7 +2,7 @@
/*
* Texas Instruments K3 Device Platform Data
*
- * Copyright (C) 2020 Texas Instruments Incorporated - http://www.ti.com/
+ * Copyright (C) 2020 Texas Instruments Incorporated - https://www.ti.com/
*/
#ifndef __K3_DEV_H__
#define __K3_DEV_H__
diff --git a/include/led.h b/include/led.h
index 3290410..a635316 100644
--- a/include/led.h
+++ b/include/led.h
@@ -110,4 +110,12 @@
*/
int led_set_period(struct udevice *dev, int period_ms);
+/**
+ * led_bind_generic() - bind children of parent to given driver
+ *
+ * @parent: Top-level LED device
+ * @driver_name: Driver for handling individual child nodes
+ */
+int led_bind_generic(struct udevice *parent, const char *driver_name);
+
#endif
diff --git a/include/linux/mtd/mtd.h b/include/linux/mtd/mtd.h
index 09f5269..7a66c7a 100644
--- a/include/linux/mtd/mtd.h
+++ b/include/linux/mtd/mtd.h
@@ -552,8 +552,20 @@
#ifdef __UBOOT__
/* drivers/mtd/mtdcore.h */
+#if CONFIG_IS_ENABLED(MTD)
int add_mtd_device(struct mtd_info *mtd);
int del_mtd_device(struct mtd_info *mtd);
+#else
+static inline int add_mtd_device(struct mtd_info *mtd)
+{
+ return -ENOSYS;
+}
+
+static inline int del_mtd_device(struct mtd_info *mtd)
+{
+ return -ENOSYS;
+}
+#endif
#ifdef CONFIG_MTD_PARTITIONS
int add_mtd_partitions(struct mtd_info *, const struct mtd_partition *, int);
diff --git a/include/linux/soc/ti/cppi5.h b/include/linux/soc/ti/cppi5.h
index 3a55c3e..c5d7ebd 100644
--- a/include/linux/soc/ti/cppi5.h
+++ b/include/linux/soc/ti/cppi5.h
@@ -2,7 +2,7 @@
/*
* CPPI5 descriptors interface
*
- * Copyright (C) 2018 Texas Instruments Incorporated - http://www.ti.com
+ * Copyright (C) 2018 Texas Instruments Incorporated - https://www.ti.com
*/
#ifndef __TI_CPPI5_H__
diff --git a/include/linux/soc/ti/k3-navss-ringacc.h b/include/linux/soc/ti/k3-navss-ringacc.h
index 0ad8f20..30fb903 100644
--- a/include/linux/soc/ti/k3-navss-ringacc.h
+++ b/include/linux/soc/ti/k3-navss-ringacc.h
@@ -2,7 +2,7 @@
/*
* TI K3 AM65x NAVSS Ring accelerator Manager (RA) subsystem driver
*
- * Copyright (C) 2018 Texas Instruments Incorporated - http://www.ti.com
+ * Copyright (C) 2018 Texas Instruments Incorporated - https://www.ti.com
*/
#ifndef __SOC_TI_K3_NAVSS_RINGACC_API_H_
diff --git a/include/linux/soc/ti/k3-sec-proxy.h b/include/linux/soc/ti/k3-sec-proxy.h
index f34854c..c3a83f1 100644
--- a/include/linux/soc/ti/k3-sec-proxy.h
+++ b/include/linux/soc/ti/k3-sec-proxy.h
@@ -2,7 +2,7 @@
/*
* Texas Instruments' K3 Secure proxy
*
- * Copyright (C) 2017-2018 Texas Instruments Incorporated - http://www.ti.com/
+ * Copyright (C) 2017-2018 Texas Instruments Incorporated - https://www.ti.com/
* Lokesh Vutla <lokeshvutla@ti.com>
*
*/
diff --git a/include/linux/soc/ti/ti-udma.h b/include/linux/soc/ti/ti-udma.h
index 04e354f..89faf69 100644
--- a/include/linux/soc/ti/ti-udma.h
+++ b/include/linux/soc/ti/ti-udma.h
@@ -1,6 +1,6 @@
/* SPDX-License-Identifier: GPL-2.0 */
/*
- * Copyright (C) 2018 Texas Instruments Incorporated - http://www.ti.com
+ * Copyright (C) 2018 Texas Instruments Incorporated - https://www.ti.com
* Author: Peter Ujfalusi <peter.ujfalusi@ti.com>
*/
diff --git a/include/linux/soc/ti/ti_sci_protocol.h b/include/linux/soc/ti/ti_sci_protocol.h
index 7f99418..8e4c43c 100644
--- a/include/linux/soc/ti/ti_sci_protocol.h
+++ b/include/linux/soc/ti/ti_sci_protocol.h
@@ -3,7 +3,7 @@
* Texas Instruments System Control Interface Protocol
* Based on include/linux/soc/ti/ti_sci_protocol.h from Linux.
*
- * Copyright (C) 2018 Texas Instruments Incorporated - http://www.ti.com/
+ * Copyright (C) 2018 Texas Instruments Incorporated - https://www.ti.com/
* Nishanth Menon
* Lokesh Vutla <lokeshvutla@ti.com>
*/
diff --git a/include/linux/time.h b/include/linux/time.h
index 14ff5b6..14a144d 100644
--- a/include/linux/time.h
+++ b/include/linux/time.h
@@ -11,6 +11,15 @@
#define _REENT_ONLY
+#define MSEC_PER_SEC 1000L
+#define USEC_PER_MSEC 1000L
+#define NSEC_PER_USEC 1000L
+#define NSEC_PER_MSEC 1000000L
+#define USEC_PER_SEC 1000000L
+#define NSEC_PER_SEC 1000000000L
+#define PSEC_PER_SEC 1000000000000LL
+#define FSEC_PER_SEC 1000000000000000LL
+
#define SECSPERMIN 60L
#define MINSPERHOUR 60L
#define HOURSPERDAY 24L
diff --git a/include/linux/usb/dwc3-omap.h b/include/linux/usb/dwc3-omap.h
index 62180e3..d5737ed 100644
--- a/include/linux/usb/dwc3-omap.h
+++ b/include/linux/usb/dwc3-omap.h
@@ -1,7 +1,7 @@
/* SPDX-License-Identifier: GPL-2.0+ */
/* include/linux/usb/dwc3-omap.h
*
- * Copyright (c) 2014 Texas Instruments Incorporated - http://www.ti.com
+ * Copyright (c) 2014 Texas Instruments Incorporated - https://www.ti.com
*
* Designware SuperSpeed Glue
*/
diff --git a/include/linux/usb/otg.h b/include/linux/usb/otg.h
index 5d0dac9..e7e3d25 100644
--- a/include/linux/usb/otg.h
+++ b/include/linux/usb/otg.h
@@ -1,7 +1,7 @@
/* SPDX-License-Identifier: GPL-2.0+ */
/* include/linux/usb/otg.h
*
- * Copyright (c) 2015 Texas Instruments Incorporated - http://www.ti.com
+ * Copyright (c) 2015 Texas Instruments Incorporated - https://www.ti.com
*
* USB OTG (On The Go) defines
*/
diff --git a/include/mtd/cfi_flash.h b/include/mtd/cfi_flash.h
index 52cd1c4..f4aecaa 100644
--- a/include/mtd/cfi_flash.h
+++ b/include/mtd/cfi_flash.h
@@ -163,7 +163,7 @@
#if defined(CONFIG_SYS_MAX_FLASH_BANKS_DETECT)
/* map to cfi_flash_num_flash_banks only when supported */
#if IS_ENABLED(CONFIG_FLASH_CFI_DRIVER) && \
- (!IS_ENABLED(CONFIG_SPL_BUILD) || IS_ENABLED(CONFIG_SPL_MTD_SUPPORT))
+ (!IS_ENABLED(CONFIG_SPL_BUILD) || IS_ENABLED(CONFIG_SPL_MTD))
#define CFI_FLASH_BANKS (cfi_flash_num_flash_banks)
/* board code can update this variable before CFI detection */
extern int cfi_flash_num_flash_banks;
diff --git a/include/mux-internal.h b/include/mux-internal.h
index 93e3a5c..67fa289 100644
--- a/include/mux-internal.h
+++ b/include/mux-internal.h
@@ -5,7 +5,7 @@
* Copyright (C) 2017 Axentia Technologies AB
* Author: Peter Rosin <peda@axentia.se>
*
- * Copyright (C) 2017-2018 Texas Instruments Incorporated - http://www.ti.com/
+ * Copyright (C) 2017-2018 Texas Instruments Incorporated - https://www.ti.com/
* Jean-Jacques Hiblot <jjhiblot@ti.com>
*/
diff --git a/include/mux.h b/include/mux.h
index c92d887..e5deaba 100644
--- a/include/mux.h
+++ b/include/mux.h
@@ -10,7 +10,7 @@
* Copyright (C) 2017 Axentia Technologies AB
* Author: Peter Rosin <peda@axentia.se>
*
- * Copyright (C) 2017-2018 Texas Instruments Incorporated - http://www.ti.com/
+ * Copyright (C) 2017-2018 Texas Instruments Incorporated - https://www.ti.com/
* Jean-Jacques Hiblot <jjhiblot@ti.com>
*/
diff --git a/include/nand.h b/include/nand.h
index 70c1286..220ffa2 100644
--- a/include/nand.h
+++ b/include/nand.h
@@ -11,7 +11,9 @@
#include <config.h>
extern void nand_init(void);
+void nand_reinit(void);
unsigned long nand_size(void);
+unsigned int nand_page_size(void);
#include <linux/compat.h>
#include <linux/mtd/mtd.h>
@@ -21,6 +23,7 @@
#if CONFIG_IS_ENABLED(SYS_NAND_SELF_INIT)
void board_nand_init(void);
int nand_register(int devnum, struct mtd_info *mtd);
+void nand_unregister(struct mtd_info *mtd);
#else
struct nand_chip;
diff --git a/include/net.h b/include/net.h
index e63a946..ac511ea 100644
--- a/include/net.h
+++ b/include/net.h
@@ -930,4 +930,21 @@
static inline void eth_set_enable_bootdevs(bool enable) {}
#endif
+/**
+ * wget_with_dns() - runs dns host IP address resulution before wget
+ *
+ * @dst_addr: destination address to download the file
+ * @uri: uri string of target file of wget
+ * Return: downloaded file size, negative if failed
+ */
+int wget_with_dns(ulong dst_addr, char *uri);
+
+/**
+ * wget_validate_uri() - varidate the uri
+ *
+ * @uri: uri string of target file of wget
+ * Return: true if uri is valid, false if uri is invalid
+ */
+bool wget_validate_uri(char *uri);
+
#endif /* __NET_H__ */
diff --git a/include/os.h b/include/os.h
index fc8a1b1..877404a 100644
--- a/include/os.h
+++ b/include/os.h
@@ -109,6 +109,19 @@
int os_persistent_file(char *buf, int maxsize, const char *fname);
/**
+ * os_mktemp() - Create a temporary file
+ * @fname: The template to use for the file name. This must end with 6 Xs. It
+ * will be modified to the opened filename on success.
+ * @size: The size of the file
+ *
+ * Create a temporary file using @fname as a template, unlink it, and truncate
+ * it to @size.
+ *
+ * Return: A file descriptor, or negative errno on error
+ */
+int os_mktemp(char *fname, off_t size);
+
+/**
* os_exit() - access to the OS exit() system call
*
* This exits with the supplied return code, which should be 0 to indicate
diff --git a/include/pci_ids.h b/include/pci_ids.h
index 88b0a64..b63bf45 100644
--- a/include/pci_ids.h
+++ b/include/pci_ids.h
@@ -1363,6 +1363,13 @@
#define PCI_DEVICE_ID_XILINX_HAMMERFALL_DSP 0x3fc5
#define PCI_DEVICE_ID_XILINX_HAMMERFALL_DSP_MADI 0x3fc6
+/* Per https://www.qemu.org/docs/master/specs/pci-ids.html */
+#define PCI_VENDOR_ID_REDHAT 0x1b36
+#define PCI_DEVICE_ID_REDHAT_SDHCI 0x0007
+#define PCI_DEVICE_ID_REDHAT_XHCI 0x000d
+#define PCI_DEVICE_ID_REDHAT_NVME 0x0010
+#define PCI_DEVICE_ID_REDHAT_UFS 0x0013
+
#define PCI_VENDOR_ID_INIT 0x1101
#define PCI_VENDOR_ID_CREATIVE 0x1102 /* duplicate: ECTIVA */
diff --git a/include/power/tps62362.h b/include/power/tps62362.h
index f0fc538..df06c28 100644
--- a/include/power/tps62362.h
+++ b/include/power/tps62362.h
@@ -1,6 +1,6 @@
/* SPDX-License-Identifier: GPL-2.0+ */
/*
- * (C) Copyright 2014 Texas Instruments Incorporated - http://www.ti.com
+ * (C) Copyright 2014 Texas Instruments Incorporated - https://www.ti.com
* Author: Felipe Balbi <balbi@ti.com>
*/
diff --git a/include/power/tps65217.h b/include/power/tps65217.h
index 669a94a..7862b31 100644
--- a/include/power/tps65217.h
+++ b/include/power/tps65217.h
@@ -3,7 +3,7 @@
* (C) Copyright 2011-2013
* Texas Instruments, <www.ti.com>
*
- * For more details, please see the TRM at http://www.ti.com/product/tps65217a
+ * For more details, please see the TRM at https://www.ti.com/product/tps65217a
*/
#ifndef __POWER_TPS65217_H__
diff --git a/include/power/tps65910.h b/include/power/tps65910.h
index 21b2a21..ccc759a 100644
--- a/include/power/tps65910.h
+++ b/include/power/tps65910.h
@@ -3,7 +3,7 @@
* (C) Copyright 2011-2013
* Texas Instruments, <www.ti.com>
*
- * For more details, please see the TRM at http://www.ti.com/product/tps65910
+ * For more details, please see the TRM at https://www.ti.com/product/tps65910
*/
#ifndef __POWER_TPS65910_H__
#define __POWER_TPS65910_H__
diff --git a/include/remoteproc.h b/include/remoteproc.h
index f48054d..a11dc8a 100644
--- a/include/remoteproc.h
+++ b/include/remoteproc.h
@@ -1,7 +1,7 @@
/* SPDX-License-Identifier: GPL-2.0 */
/*
* (C) Copyright 2015
- * Texas Instruments Incorporated - http://www.ti.com/
+ * Texas Instruments Incorporated - https://www.ti.com/
*/
#ifndef _RPROC_H_
diff --git a/include/serial.h b/include/serial.h
index 205889d..d129dc3 100644
--- a/include/serial.h
+++ b/include/serial.h
@@ -339,6 +339,13 @@
*/
int serial_getinfo(struct udevice *dev, struct serial_device_info *info);
+/**
+ * fetch_baud_from_dtb() - Fetch the baudrate value from DT
+ *
+ * Return: baudrate if OK, -ve on error
+ */
+int fetch_baud_from_dtb(void);
+
void atmel_serial_initialize(void);
void mcf_serial_initialize(void);
void mpc85xx_serial_initialize(void);
diff --git a/include/soc.h b/include/soc.h
index a52a300..850db28 100644
--- a/include/soc.h
+++ b/include/soc.h
@@ -1,6 +1,6 @@
/* SPDX-License-Identifier: GPL-2.0+ */
/*
- * (C) Copyright 2020 - Texas Instruments Incorporated - http://www.ti.com/
+ * (C) Copyright 2020 - Texas Instruments Incorporated - https://www.ti.com/
* Dave Gerlach <d-gerlach@ti.com>
*/
diff --git a/include/spl.h b/include/spl.h
index 8ff20ad..0952188 100644
--- a/include/spl.h
+++ b/include/spl.h
@@ -285,30 +285,53 @@
/**
* Information required to load data from a device
*
- * @dev: Pointer to the device, e.g. struct mmc *
* @priv: Private data for the device
* @bl_len: Block length for reading in bytes
- * @filename: Name of the fit image file.
* @read: Function to call to read from the device
*/
struct spl_load_info {
- void *dev;
void *priv;
- int bl_len;
- const char *filename;
/**
* read() - Read from device
*
* @load: Information about the load state
- * @sector: Sector number to read from (each @load->bl_len bytes)
- * @count: Number of sectors to read
+ * @offset: Offset to read from in bytes. This must be a multiple of
+ * @load->bl_len.
+ * @count: Number of bytes to read. This must be a multiple of
+ * @load->bl_len.
* @buf: Buffer to read into
- * @return number of sectors read, 0 on error
+ * @return number of bytes read, 0 on error
*/
ulong (*read)(struct spl_load_info *load, ulong sector, ulong count,
void *buf);
+#if IS_ENABLED(CONFIG_SPL_LOAD_BLOCK)
+ int bl_len;
};
+static inline int spl_get_bl_len(struct spl_load_info *info)
+{
+ return info->bl_len;
+}
+
+static inline void spl_set_bl_len(struct spl_load_info *info, int bl_len)
+{
+ info->bl_len = bl_len;
+}
+#else
+};
+
+static inline int spl_get_bl_len(struct spl_load_info *info)
+{
+ return 1;
+}
+
+static inline void spl_set_bl_len(struct spl_load_info *info, int bl_len)
+{
+ if (bl_len != 1)
+ panic("CONFIG_SPL_LOAD_BLOCK not enabled");
+}
+#endif
+
/*
* We need to know the position of U-Boot in memory so we can jump to it. We
* allow any U-Boot binary to be used (u-boot.bin, u-boot-nodtb.bin,
@@ -370,7 +393,8 @@
* spl_load_simple_fit() - Loads a fit image from a device.
* @spl_image: Image description to set up
* @info: Structure containing the information required to load data.
- * @sector: Sector number where FIT image is located in the device
+ * @offset: Offset where FIT image is located in the device. Must be aligned
+ * to the device's bl_len.
* @fdt: Pointer to the copied FIT header.
*
* Reads the FIT image @sector in the device. Loads u-boot image to
@@ -378,12 +402,25 @@
* Returns 0 on success.
*/
int spl_load_simple_fit(struct spl_image_info *spl_image,
- struct spl_load_info *info, ulong sector, void *fdt);
+ struct spl_load_info *info, ulong offset, void *fdt);
#define SPL_COPY_PAYLOAD_ONLY 1
#define SPL_FIT_FOUND 2
/**
+ * spl_load_legacy_lzma() - Load an LZMA-compressed legacy image
+ * @spl_image: Image description (already set up)
+ * @load: Structure containing the information required to load data.
+ * @offset: Pointer to image
+ *
+ * Load/decompress an LZMA-compressed legacy image from the device.
+ *
+ * Return: 0 on success, or a negative error on failure
+ */
+int spl_load_legacy_lzma(struct spl_image_info *spl_image,
+ struct spl_load_info *load, ulong offset);
+
+/**
* spl_load_legacy_img() - Loads a legacy image from a device.
* @spl_image: Image description to set up
* @load: Structure containing the information required to load data.
@@ -404,13 +441,14 @@
* spl_load_imx_container() - Loads a imx container image from a device.
* @spl_image: Image description to set up
* @info: Structure containing the information required to load data.
- * @sector: Sector number where container image is located in the device
+ * @sector: Offset where container image is located in the device. Must be
+ * aligned to the device block size.
*
* Reads the container image @sector in the device. Loads u-boot image to
* specified load address.
*/
int spl_load_imx_container(struct spl_image_info *spl_image,
- struct spl_load_info *info, ulong sector);
+ struct spl_load_info *info, ulong offset);
/* SPL common functions */
void preloader_console_init(void);
diff --git a/include/spl_load.h b/include/spl_load.h
new file mode 100644
index 0000000..1c2b296
--- /dev/null
+++ b/include/spl_load.h
@@ -0,0 +1,144 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (C) Sean Anderson <seanga2@gmail.com>
+ */
+#ifndef _SPL_LOAD_H_
+#define _SPL_LOAD_H_
+
+#include <image.h>
+#include <imx_container.h>
+#include <mapmem.h>
+#include <spl.h>
+
+static inline int _spl_load(struct spl_image_info *spl_image,
+ const struct spl_boot_device *bootdev,
+ struct spl_load_info *info, size_t size,
+ size_t offset)
+{
+ struct legacy_img_hdr *header =
+ spl_get_load_buffer(-sizeof(*header), sizeof(*header));
+ ulong base_offset, image_offset, overhead;
+ int read, ret;
+
+ read = info->read(info, offset, ALIGN(sizeof(*header),
+ spl_get_bl_len(info)), header);
+ if (read < sizeof(*header))
+ return -EIO;
+
+ if (image_get_magic(header) == FDT_MAGIC) {
+ if (IS_ENABLED(CONFIG_SPL_LOAD_FIT_FULL)) {
+ void *buf;
+
+ /*
+ * In order to support verifying images in the FIT, we
+ * need to load the whole FIT into memory. Try and
+ * guess how much we need to load by using the total
+ * size. This will fail for FITs with external data,
+ * but there's not much we can do about that.
+ */
+ if (!size)
+ size = round_up(fdt_totalsize(header), 4);
+ buf = map_sysmem(CONFIG_SYS_LOAD_ADDR, size);
+ read = info->read(info, offset,
+ ALIGN(size, spl_get_bl_len(info)),
+ buf);
+ if (read < size)
+ return -EIO;
+
+ return spl_parse_image_header(spl_image, bootdev, buf);
+ }
+
+ if (IS_ENABLED(CONFIG_SPL_LOAD_FIT))
+ return spl_load_simple_fit(spl_image, info, offset,
+ header);
+ }
+
+ if (IS_ENABLED(CONFIG_SPL_LOAD_IMX_CONTAINER) &&
+ valid_container_hdr((void *)header))
+ return spl_load_imx_container(spl_image, info, offset);
+
+ if (IS_ENABLED(CONFIG_SPL_LZMA) &&
+ image_get_magic(header) == IH_MAGIC &&
+ image_get_comp(header) == IH_COMP_LZMA) {
+ spl_image->flags |= SPL_COPY_PAYLOAD_ONLY;
+ ret = spl_parse_image_header(spl_image, bootdev, header);
+ if (ret)
+ return ret;
+
+ return spl_load_legacy_lzma(spl_image, info, offset);
+ }
+
+ ret = spl_parse_image_header(spl_image, bootdev, header);
+ if (ret)
+ return ret;
+
+ base_offset = spl_image->offset;
+ /* Only NOR sets this flag. */
+ if (IS_ENABLED(CONFIG_SPL_NOR_SUPPORT) &&
+ spl_image->flags & SPL_COPY_PAYLOAD_ONLY)
+ base_offset += sizeof(*header);
+ image_offset = ALIGN_DOWN(base_offset, spl_get_bl_len(info));
+ overhead = base_offset - image_offset;
+ size = ALIGN(spl_image->size + overhead, spl_get_bl_len(info));
+
+ read = info->read(info, offset + image_offset, size,
+ map_sysmem(spl_image->load_addr - overhead, size));
+ return read < spl_image->size ? -EIO : 0;
+}
+
+/*
+ * Although spl_load results in size reduction for callers, this is generally
+ * not enough to counteract the bloat if there is only one caller. The core
+ * problem is that the compiler can't optimize across translation units. The
+ * general solution to this is CONFIG_LTO, but that is not available on all
+ * architectures. Perform a pseudo-LTO just for this function by declaring it
+ * inline if there is one caller, and extern otherwise.
+ */
+#define SPL_LOAD_USERS \
+ IS_ENABLED(CONFIG_SPL_BLK_FS) + \
+ IS_ENABLED(CONFIG_SPL_FS_EXT4) + \
+ IS_ENABLED(CONFIG_SPL_FS_FAT) + \
+ IS_ENABLED(CONFIG_SPL_SYS_MMCSD_RAW_MODE) + \
+ (IS_ENABLED(CONFIG_SPL_NAND_SUPPORT) && !IS_ENABLED(CONFIG_SPL_UBI)) + \
+ IS_ENABLED(CONFIG_SPL_NET) + \
+ IS_ENABLED(CONFIG_SPL_NOR_SUPPORT) + \
+ IS_ENABLED(CONFIG_SPL_SEMIHOSTING) + \
+ IS_ENABLED(CONFIG_SPL_SPI_LOAD) + \
+ 0
+
+#if SPL_LOAD_USERS > 1
+/**
+ * spl_load() - Parse a header and load the image
+ * @spl_image: Image data which will be filled in by this function
+ * @bootdev: The device to load from
+ * @info: Describes how to load additional information from @bootdev. At the
+ * minimum, read() and bl_len must be populated.
+ * @size: The size of the image, in bytes, if it is known in advance. Some boot
+ * devices (such as filesystems) know how big an image is before parsing
+ * the header. If 0, then the size will be determined from the header.
+ * @offset: The offset from the start of @bootdev, in bytes. This should have
+ * the offset @header was loaded from. It will be added to any offsets
+ * passed to @info->read().
+ *
+ * This function determines the image type (FIT, legacy, i.MX, raw, etc), calls
+ * the appropriate parsing function, determines the load address, and the loads
+ * the image from storage. It is designed to replace ad-hoc image loading which
+ * may not support all image types (especially when config options are
+ * involved).
+ *
+ * Return: 0 on success, or a negative error on failure
+ */
+int spl_load(struct spl_image_info *spl_image,
+ const struct spl_boot_device *bootdev, struct spl_load_info *info,
+ size_t size, size_t offset);
+#else
+static inline int spl_load(struct spl_image_info *spl_image,
+ const struct spl_boot_device *bootdev,
+ struct spl_load_info *info, size_t size,
+ size_t offset)
+{
+ return _spl_load(spl_image, bootdev, info, size, offset);
+}
+#endif
+
+#endif /* _SPL_LOAD_H_ */
diff --git a/include/sysinfo.h b/include/sysinfo.h
index b140d74..f2c1aa2 100644
--- a/include/sysinfo.h
+++ b/include/sysinfo.h
@@ -46,6 +46,9 @@
/* For show_board_info() */
SYSINFO_ID_BOARD_MODEL,
+ SYSINFO_ID_BOARD_MANUFACTURER,
+ SYSINFO_ID_PRIOR_STAGE_VERSION,
+ SYSINFO_ID_PRIOR_STAGE_DATE,
/* First value available for downstream/board used */
SYSINFO_ID_USER = 0x1000,
diff --git a/include/system-constants.h b/include/system-constants.h
index 5937156..d688629 100644
--- a/include/system-constants.h
+++ b/include/system-constants.h
@@ -41,4 +41,8 @@
#define SPL_PAYLOAD_ARGS_ADDR 0
#endif
+/* Number of pages per block */
+#define SYS_NAND_BLOCK_PAGES \
+ (CONFIG_SYS_NAND_BLOCK_SIZE / CONFIG_SYS_NAND_PAGE_SIZE)
+
#endif
diff --git a/include/test/spl.h b/include/test/spl.h
index c1f6465..a2a5f33 100644
--- a/include/test/spl.h
+++ b/include/test/spl.h
@@ -81,6 +81,10 @@
int check_image_info(struct unit_test_state *uts, struct spl_image_info *info1,
struct spl_image_info *info2);
+/* Some compressed data and it size */
+extern const char lzma_compressed[];
+extern const size_t lzma_compressed_size;
+
/**
* typedef write_image_t - Callback for writing an image
* @uts: Current unit test state
diff --git a/include/ti-usb-phy-uboot.h b/include/ti-usb-phy-uboot.h
index cd2ba40..feeddb8 100644
--- a/include/ti-usb-phy-uboot.h
+++ b/include/ti-usb-phy-uboot.h
@@ -1,7 +1,7 @@
/* SPDX-License-Identifier: GPL-2.0+ */
/* include/ti_usb_phy_uboot.h
*
- * Copyright (c) 2014 Texas Instruments Incorporated - http://www.ti.com
+ * Copyright (c) 2014 Texas Instruments Incorporated - https://www.ti.com
*
* USB2 and USB3 PHY uboot init
*/
diff --git a/include/usb/xhci.h b/include/usb/xhci.h
index 4a4ac10..04d16a2 100644
--- a/include/usb/xhci.h
+++ b/include/usb/xhci.h
@@ -901,6 +901,8 @@
/* TRB type IDs */
typedef enum {
+ /* reserved, used as a software sentinel */
+ TRB_NONE = 0,
/* bulk, interrupt, isoc scatter/gather, and control data stage */
TRB_NORMAL = 1,
/* setup stage for control transfers */
diff --git a/include/video.h b/include/video.h
index 5048116..4d8df9b 100644
--- a/include/video.h
+++ b/include/video.h
@@ -21,9 +21,12 @@
* @align: Frame-buffer alignment, indicating the memory boundary the frame
* buffer should start on. If 0, 1MB is assumed
* @size: Frame-buffer size, in bytes
- * @base: Base address of frame buffer, 0 if not yet known
- * @copy_base: Base address of a hardware copy of the frame buffer. See
- * CONFIG_VIDEO_COPY.
+ * @base: Base address of frame buffer, 0 if not yet known. If CONFIG_VIDEO_COPY
+ * is enabled, this is the software copy, so writes to this will not be
+ * visible until vidconsole_sync_copy() is called. If CONFIG_VIDEO_COPY is
+ * disabled, this is the hardware framebuffer.
+ * @copy_base: Base address of a hardware copy of the frame buffer. If
+ * CONFIG_VIDEO_COPY is disabled, this is not used.
* @copy_size: Size of copy framebuffer, used if @size is 0
* @hide_logo: Hide the logo (used for testing)
*/
diff --git a/lib/efi_loader/Kconfig b/lib/efi_loader/Kconfig
index 547dfd7..ea80734 100644
--- a/lib/efi_loader/Kconfig
+++ b/lib/efi_loader/Kconfig
@@ -133,18 +133,20 @@
config EFI_VAR_BUF_SIZE
int "Memory size of the UEFI variable store"
- default 16384 if EFI_MM_COMM_TEE
- default 65536
+ default 131072
range 4096 2147483647
help
This defines the size in bytes of the memory area reserved for keeping
UEFI variables.
- When using StandAloneMM (CONFIG_EFI_MM_COMM_TEE=y) this value should
- match the value of PcdFlashNvStorageVariableSize used to compile the
- StandAloneMM module.
+ When using StandAloneMM (CONFIG_EFI_MM_COMM_TEE=y) is used the
+ available size for storing variables is defined in
+ PcdFlashNvStorageVariableSize.
+ That value is probed at runtime from U-Boot. In that case,
+ EFI_VAR_BUF_SIZE represents the memory U-Boot reserves to present
+ runtime variables to the OS.
- Minimum 4096, default 65536, or 16384 when using StandAloneMM.
+ Minimum 4096, default 131072
config EFI_GET_TIME
bool "GetTime() runtime service"
@@ -477,4 +479,13 @@
replace the transfer via the device-tree. The latter is not
possible on systems using ACPI.
+config EFI_HTTP_BOOT
+ bool "EFI HTTP Boot support"
+ select CMD_DNS
+ select CMD_WGET
+ select BLKMAP
+ help
+ Enabling this option adds EFI HTTP Boot support. It allows to
+ directly boot from network.
+
endif
diff --git a/lib/efi_loader/efi_bootmgr.c b/lib/efi_loader/efi_bootmgr.c
index a40762c..48153bd 100644
--- a/lib/efi_loader/efi_bootmgr.c
+++ b/lib/efi_loader/efi_bootmgr.c
@@ -7,10 +7,14 @@
#define LOG_CATEGORY LOGC_EFI
+#include <blk.h>
+#include <blkmap.h>
#include <common.h>
#include <charset.h>
+#include <dm.h>
#include <log.h>
#include <malloc.h>
+#include <net.h>
#include <efi_default_filename.h>
#include <efi_loader.h>
#include <efi_variable.h>
@@ -19,6 +23,23 @@
static const struct efi_boot_services *bs;
static const struct efi_runtime_services *rs;
+/**
+ * struct uridp_context - uri device path resource
+ *
+ * @image_size: image size
+ * @image_addr: image address
+ * @loaded_dp: pointer to loaded device path
+ * @ramdisk_blk_dev: pointer to the ramdisk blk device
+ * @mem_handle: efi_handle to the loaded PE-COFF image
+ */
+struct uridp_context {
+ ulong image_size;
+ ulong image_addr;
+ struct efi_device_path *loaded_dp;
+ struct udevice *ramdisk_blk_dev;
+ efi_handle_t mem_handle;
+};
+
const efi_guid_t efi_guid_bootmenu_auto_generated =
EFICONFIG_AUTO_GENERATED_ENTRY_GUID;
@@ -169,6 +190,364 @@
}
/**
+ * mount_image() - mount the image with blkmap
+ *
+ * @lo_label: u16 label string of load option
+ * @addr: image address
+ * @size: image size
+ * Return: pointer to the UCLASS_BLK udevice, NULL if failed
+ */
+static struct udevice *mount_image(u16 *lo_label, ulong addr, ulong size)
+{
+ int err;
+ struct blkmap *bm;
+ struct udevice *bm_dev;
+ char *label = NULL, *p;
+
+ label = efi_alloc(utf16_utf8_strlen(lo_label) + 1);
+ if (!label)
+ return NULL;
+
+ p = label;
+ utf16_utf8_strcpy(&p, lo_label);
+ err = blkmap_create_ramdisk(label, addr, size, &bm_dev);
+ if (err) {
+ efi_free_pool(label);
+ return NULL;
+ }
+ bm = dev_get_plat(bm_dev);
+
+ efi_free_pool(label);
+
+ return bm->blk;
+}
+
+/**
+ * search_default_file() - search default file
+ *
+ * @dev: pointer to the UCLASS_BLK or UCLASS_PARTITION udevice
+ * @loaded_dp: pointer to default file device path
+ * Return: status code
+ */
+static efi_status_t search_default_file(struct udevice *dev,
+ struct efi_device_path **loaded_dp)
+{
+ efi_status_t ret;
+ efi_handle_t handle;
+ u16 *default_file_name = NULL;
+ struct efi_file_handle *root, *f;
+ struct efi_device_path *dp = NULL, *fp = NULL;
+ struct efi_simple_file_system_protocol *file_system;
+ struct efi_device_path *device_path, *full_path = NULL;
+
+ if (dev_tag_get_ptr(dev, DM_TAG_EFI, (void **)&handle)) {
+ log_warning("DM_TAG_EFI not found\n");
+ return EFI_INVALID_PARAMETER;
+ }
+
+ ret = EFI_CALL(bs->open_protocol(handle, &efi_guid_device_path,
+ (void **)&device_path, efi_root, NULL,
+ EFI_OPEN_PROTOCOL_GET_PROTOCOL));
+ if (ret != EFI_SUCCESS)
+ return ret;
+
+ ret = EFI_CALL(bs->open_protocol(handle, &efi_simple_file_system_protocol_guid,
+ (void **)&file_system, efi_root, NULL,
+ EFI_OPEN_PROTOCOL_GET_PROTOCOL));
+ if (ret != EFI_SUCCESS)
+ return ret;
+
+ ret = EFI_CALL(file_system->open_volume(file_system, &root));
+ if (ret != EFI_SUCCESS)
+ return ret;
+
+ full_path = expand_media_path(device_path);
+ ret = efi_dp_split_file_path(full_path, &dp, &fp);
+ if (ret != EFI_SUCCESS)
+ goto err;
+
+ default_file_name = efi_dp_str(fp);
+ efi_free_pool(dp);
+ efi_free_pool(fp);
+ if (!default_file_name) {
+ ret = EFI_OUT_OF_RESOURCES;
+ goto err;
+ }
+
+ ret = EFI_CALL(root->open(root, &f, default_file_name,
+ EFI_FILE_MODE_READ, 0));
+ efi_free_pool(default_file_name);
+ if (ret != EFI_SUCCESS)
+ goto err;
+
+ EFI_CALL(f->close(f));
+ EFI_CALL(root->close(root));
+
+ *loaded_dp = full_path;
+
+ return EFI_SUCCESS;
+
+err:
+ EFI_CALL(root->close(root));
+ efi_free_pool(full_path);
+
+ return ret;
+}
+
+/**
+ * check_disk_has_default_file() - load the default file
+ *
+ * @blk: pointer to the UCLASS_BLK udevice
+ * @dp: pointer to default file device path
+ * Return: status code
+ */
+static efi_status_t check_disk_has_default_file(struct udevice *blk,
+ struct efi_device_path **dp)
+{
+ efi_status_t ret;
+ struct udevice *partition;
+
+ /* image that has no partition table but a file system */
+ ret = search_default_file(blk, dp);
+ if (ret == EFI_SUCCESS)
+ return ret;
+
+ /* try the partitions */
+ device_foreach_child(partition, blk) {
+ enum uclass_id id;
+
+ id = device_get_uclass_id(partition);
+ if (id != UCLASS_PARTITION)
+ continue;
+
+ ret = search_default_file(partition, dp);
+ if (ret == EFI_SUCCESS)
+ return ret;
+ }
+
+ return EFI_NOT_FOUND;
+}
+
+/**
+ * prepare_loaded_image() - prepare ramdisk for downloaded image
+ *
+ * @label: label of load option
+ * @addr: image address
+ * @size: image size
+ * @dp: pointer to default file device path
+ * @blk: pointer to created blk udevice
+ * Return: status code
+ */
+static efi_status_t prepare_loaded_image(u16 *label, ulong addr, ulong size,
+ struct efi_device_path **dp,
+ struct udevice **blk)
+{
+ efi_status_t ret;
+ struct udevice *ramdisk_blk;
+
+ ramdisk_blk = mount_image(label, addr, size);
+ if (!ramdisk_blk)
+ return EFI_LOAD_ERROR;
+
+ ret = check_disk_has_default_file(ramdisk_blk, dp);
+ if (ret != EFI_SUCCESS) {
+ log_info("Cannot boot from downloaded image\n");
+ goto err;
+ }
+
+ /*
+ * TODO: expose the ramdisk to OS.
+ * Need to pass the ramdisk information by the architecture-specific
+ * methods such as 'pmem' device-tree node.
+ */
+ ret = efi_add_memory_map(addr, size, EFI_RESERVED_MEMORY_TYPE);
+ if (ret != EFI_SUCCESS) {
+ log_err("Memory reservation failed\n");
+ goto err;
+ }
+
+ *blk = ramdisk_blk;
+
+ return EFI_SUCCESS;
+
+err:
+ if (blkmap_destroy(ramdisk_blk->parent))
+ log_err("Destroying blkmap failed\n");
+
+ return ret;
+}
+
+/**
+ * efi_bootmgr_release_uridp_resource() - cleanup uri device path resource
+ *
+ * @ctx: event context
+ * Return: status code
+ */
+efi_status_t efi_bootmgr_release_uridp_resource(struct uridp_context *ctx)
+{
+ efi_status_t ret = EFI_SUCCESS;
+
+ if (!ctx)
+ return ret;
+
+ /* cleanup for iso or img image */
+ if (ctx->ramdisk_blk_dev) {
+ ret = efi_add_memory_map(ctx->image_addr, ctx->image_size,
+ EFI_CONVENTIONAL_MEMORY);
+ if (ret != EFI_SUCCESS)
+ log_err("Reclaiming memory failed\n");
+
+ if (blkmap_destroy(ctx->ramdisk_blk_dev->parent)) {
+ log_err("Destroying blkmap failed\n");
+ ret = EFI_DEVICE_ERROR;
+ }
+ }
+
+ /* cleanup for PE-COFF image */
+ if (ctx->mem_handle) {
+ ret = efi_uninstall_multiple_protocol_interfaces(
+ ctx->mem_handle, &efi_guid_device_path, ctx->loaded_dp,
+ NULL);
+ if (ret != EFI_SUCCESS)
+ log_err("Uninstall device_path protocol failed\n");
+ }
+
+ efi_free_pool(ctx->loaded_dp);
+ free(ctx);
+
+ return ret;
+}
+
+/**
+ * efi_bootmgr_image_return_notify() - return to efibootmgr callback
+ *
+ * @event: the event for which this notification function is registered
+ * @context: event context
+ */
+static void EFIAPI efi_bootmgr_image_return_notify(struct efi_event *event,
+ void *context)
+{
+ efi_status_t ret;
+
+ EFI_ENTRY("%p, %p", event, context);
+ ret = efi_bootmgr_release_uridp_resource(context);
+ EFI_EXIT(ret);
+}
+
+/**
+ * try_load_from_uri_path() - Handle the URI device path
+ *
+ * @uridp: uri device path
+ * @lo_label: label of load option
+ * @handle: pointer to handle for newly installed image
+ * Return: status code
+ */
+static efi_status_t try_load_from_uri_path(struct efi_device_path_uri *uridp,
+ u16 *lo_label,
+ efi_handle_t *handle)
+{
+ char *s;
+ int err;
+ int uri_len;
+ efi_status_t ret;
+ void *source_buffer;
+ efi_uintn_t source_size;
+ struct uridp_context *ctx;
+ struct udevice *blk = NULL;
+ struct efi_event *event = NULL;
+ efi_handle_t mem_handle = NULL;
+ struct efi_device_path *loaded_dp;
+ static ulong image_size, image_addr;
+
+ ctx = calloc(1, sizeof(struct uridp_context));
+ if (!ctx)
+ return EFI_OUT_OF_RESOURCES;
+
+ s = env_get("loadaddr");
+ if (!s) {
+ log_err("Error: loadaddr is not set\n");
+ ret = EFI_INVALID_PARAMETER;
+ goto err;
+ }
+
+ image_addr = hextoul(s, NULL);
+ err = wget_with_dns(image_addr, uridp->uri);
+ if (err < 0) {
+ ret = EFI_INVALID_PARAMETER;
+ goto err;
+ }
+
+ image_size = env_get_hex("filesize", 0);
+ if (!image_size) {
+ ret = EFI_INVALID_PARAMETER;
+ goto err;
+ }
+
+ /*
+ * If the file extension is ".iso" or ".img", mount it and try to load
+ * the default file.
+ * If the file is PE-COFF image, load the downloaded file.
+ */
+ uri_len = strlen(uridp->uri);
+ if (!strncmp(&uridp->uri[uri_len - 4], ".iso", 4) ||
+ !strncmp(&uridp->uri[uri_len - 4], ".img", 4)) {
+ ret = prepare_loaded_image(lo_label, image_addr, image_size,
+ &loaded_dp, &blk);
+ if (ret != EFI_SUCCESS)
+ goto err;
+
+ source_buffer = NULL;
+ source_size = 0;
+ } else if (efi_check_pe((void *)image_addr, image_size, NULL) == EFI_SUCCESS) {
+ /*
+ * loaded_dp must exist until efi application returns,
+ * will be freed in return_to_efibootmgr event callback.
+ */
+ loaded_dp = efi_dp_from_mem(EFI_RESERVED_MEMORY_TYPE,
+ (uintptr_t)image_addr, image_size);
+ ret = efi_install_multiple_protocol_interfaces(
+ &mem_handle, &efi_guid_device_path, loaded_dp, NULL);
+ if (ret != EFI_SUCCESS)
+ goto err;
+
+ source_buffer = (void *)image_addr;
+ source_size = image_size;
+ } else {
+ log_err("Error: file type is not supported\n");
+ ret = EFI_UNSUPPORTED;
+ goto err;
+ }
+
+ ctx->image_size = image_size;
+ ctx->image_addr = image_addr;
+ ctx->loaded_dp = loaded_dp;
+ ctx->ramdisk_blk_dev = blk;
+ ctx->mem_handle = mem_handle;
+
+ ret = EFI_CALL(efi_load_image(false, efi_root, loaded_dp, source_buffer,
+ source_size, handle));
+ if (ret != EFI_SUCCESS)
+ goto err;
+
+ /* create event for cleanup when the image returns or error occurs */
+ ret = efi_create_event(EVT_NOTIFY_SIGNAL, TPL_CALLBACK,
+ efi_bootmgr_image_return_notify, ctx,
+ &efi_guid_event_group_return_to_efibootmgr,
+ &event);
+ if (ret != EFI_SUCCESS) {
+ log_err("Creating event failed\n");
+ goto err;
+ }
+
+ return ret;
+
+err:
+ efi_bootmgr_release_uridp_resource(ctx);
+
+ return ret;
+}
+
+/**
* try_load_entry() - try to load image for boot option
*
* Attempt to load load-option number 'n', returning device_path and file_path
@@ -211,6 +590,13 @@
if (EFI_DP_TYPE(lo.file_path, MEDIA_DEVICE, FILE_PATH)) {
/* file_path doesn't contain a device path */
ret = try_load_from_short_path(lo.file_path, handle);
+ } else if (EFI_DP_TYPE(lo.file_path, MESSAGING_DEVICE, MSG_URI)) {
+ if (IS_ENABLED(CONFIG_EFI_HTTP_BOOT))
+ ret = try_load_from_uri_path(
+ (struct efi_device_path_uri *)lo.file_path,
+ lo.label, handle);
+ else
+ ret = EFI_LOAD_ERROR;
} else {
file_path = expand_media_path(lo.file_path);
ret = EFI_CALL(efi_load_image(true, efi_root, file_path,
diff --git a/lib/efi_loader/efi_boottime.c b/lib/efi_loader/efi_boottime.c
index 0b7579c..3767fa2 100644
--- a/lib/efi_loader/efi_boottime.c
+++ b/lib/efi_loader/efi_boottime.c
@@ -90,6 +90,9 @@
/* event group ResetSystem() invoked (before ExitBootServices) */
const efi_guid_t efi_guid_event_group_reset_system =
EFI_EVENT_GROUP_RESET_SYSTEM;
+/* event group return to efibootmgr */
+const efi_guid_t efi_guid_event_group_return_to_efibootmgr =
+ EFI_EVENT_GROUP_RETURN_TO_EFIBOOTMGR;
/* GUIDs of the Load File and Load File2 protocols */
const efi_guid_t efi_guid_load_file_protocol = EFI_LOAD_FILE_PROTOCOL_GUID;
const efi_guid_t efi_guid_load_file2_protocol = EFI_LOAD_FILE2_PROTOCOL_GUID;
@@ -712,7 +715,7 @@
void (EFIAPI *notify_function) (
struct efi_event *event,
void *context),
- void *notify_context, efi_guid_t *group,
+ void *notify_context, const efi_guid_t *group,
struct efi_event **event)
{
struct efi_event *evt;
@@ -790,7 +793,7 @@
struct efi_event *event,
void *context),
void *notify_context,
- efi_guid_t *event_group,
+ const efi_guid_t *event_group,
struct efi_event **event)
{
efi_status_t ret;
diff --git a/lib/efi_loader/efi_disk.c b/lib/efi_loader/efi_disk.c
index f0d7611..b808a7f 100644
--- a/lib/efi_loader/efi_disk.c
+++ b/lib/efi_loader/efi_disk.c
@@ -690,6 +690,13 @@
return -1;
}
+ /* only do the boot option management when UEFI sub-system is initialized */
+ if (IS_ENABLED(CONFIG_CMD_BOOTEFI_BOOTMGR) && efi_obj_list_initialized == EFI_SUCCESS) {
+ ret = efi_bootmgr_update_media_device_boot_option();
+ if (ret != EFI_SUCCESS)
+ return -1;
+ }
+
return 0;
}
@@ -742,6 +749,17 @@
dev_tag_del(dev, DM_TAG_EFI);
return 0;
+
+ /*
+ * TODO A flag to distinguish below 2 different scenarios of this
+ * function call is needed:
+ * a) Unplugging of a removable media under U-Boot
+ * b) U-Boot exiting and booting an OS
+ * In case of scenario a), efi_bootmgr_update_media_device_boot_option()
+ * needs to be invoked here to update the boot options and remove the
+ * unnecessary ones.
+ */
+
}
/**
diff --git a/lib/efi_loader/efi_gop.c b/lib/efi_loader/efi_gop.c
index 778b693..a09db31 100644
--- a/lib/efi_loader/efi_gop.c
+++ b/lib/efi_loader/efi_gop.c
@@ -10,6 +10,7 @@
#include <efi_loader.h>
#include <log.h>
#include <malloc.h>
+#include <mapmem.h>
#include <video.h>
#include <asm/global_data.h>
@@ -467,10 +468,10 @@
struct efi_gop_obj *gopobj;
u32 bpix, format, col, row;
u64 fb_base, fb_size;
- void *fb;
efi_status_t ret;
struct udevice *vdev;
struct video_priv *priv;
+ struct video_uc_plat *plat;
/* We only support a single video output device for now */
if (uclass_first_device_err(UCLASS_VIDEO, &vdev)) {
@@ -483,9 +484,10 @@
format = priv->format;
col = video_get_xsize(vdev);
row = video_get_ysize(vdev);
- fb_base = (uintptr_t)priv->fb;
- fb_size = priv->fb_size;
- fb = priv->fb;
+
+ plat = dev_get_uclass_plat(vdev);
+ fb_base = IS_ENABLED(CONFIG_VIDEO_COPY) ? plat->copy_base : plat->base;
+ fb_size = plat->size;
switch (bpix) {
case VIDEO_BPP16:
@@ -547,7 +549,7 @@
}
gopobj->info.pixels_per_scanline = col;
gopobj->bpix = bpix;
- gopobj->fb = fb;
+ gopobj->fb = map_sysmem(fb_base, fb_size);
return EFI_SUCCESS;
}
diff --git a/lib/efi_loader/efi_setup.c b/lib/efi_loader/efi_setup.c
index e6de685..37359a7 100644
--- a/lib/efi_loader/efi_setup.c
+++ b/lib/efi_loader/efi_setup.c
@@ -245,6 +245,13 @@
if (ret != EFI_SUCCESS)
goto out;
+ if (IS_ENABLED(CONFIG_CMD_BOOTEFI_BOOTMGR)) {
+ /* update boot option after variable service initialized */
+ ret = efi_bootmgr_update_media_device_boot_option();
+ if (ret != EFI_SUCCESS)
+ goto out;
+ }
+
/* Define supported languages */
ret = efi_init_platform_lang();
if (ret != EFI_SUCCESS)
diff --git a/lib/efi_loader/efi_smbios.c b/lib/efi_loader/efi_smbios.c
index 48446f6..0fbf51b 100644
--- a/lib/efi_loader/efi_smbios.c
+++ b/lib/efi_loader/efi_smbios.c
@@ -49,25 +49,27 @@
static int install_smbios_table(void)
{
- ulong addr;
- void *buf;
+ u64 addr;
+ efi_status_t ret;
if (!IS_ENABLED(CONFIG_GENERATE_SMBIOS_TABLE) || IS_ENABLED(CONFIG_X86))
return 0;
- /* Align the table to a 4KB boundary to keep EFI happy */
- buf = memalign(SZ_4K, TABLE_SIZE);
- if (!buf)
+ addr = SZ_4G;
+ ret = efi_allocate_pages(EFI_ALLOCATE_MAX_ADDRESS,
+ EFI_RUNTIME_SERVICES_DATA,
+ efi_size_in_pages(TABLE_SIZE), &addr);
+ if (ret != EFI_SUCCESS)
return log_msg_ret("mem", -ENOMEM);
- addr = map_to_sysmem(buf);
+ addr = map_to_sysmem((void *)(uintptr_t)addr);
if (!write_smbios_table(addr)) {
log_err("Failed to write SMBIOS table\n");
return log_msg_ret("smbios", -EINVAL);
}
/* Make a note of where we put it */
- log_debug("SMBIOS tables written to %lx\n", addr);
+ log_debug("SMBIOS tables written to %llx\n", addr);
gd->arch.smbios_start = addr;
return 0;
diff --git a/lib/efi_loader/efi_tcg2.c b/lib/efi_loader/efi_tcg2.c
index 2eaa12b..463ea4c 100644
--- a/lib/efi_loader/efi_tcg2.c
+++ b/lib/efi_loader/efi_tcg2.c
@@ -944,8 +944,11 @@
* Add SCRTM version to the log if previous firmmware
* doesn't pass an eventlog.
*/
- if (!elog.found)
+ if (!elog.found) {
ret = efi_append_scrtm_version(dev);
+ if (ret != EFI_SUCCESS)
+ goto free_pool;
+ }
ret = create_final_event();
if (ret != EFI_SUCCESS)
diff --git a/lib/efi_loader/efi_var_file.c b/lib/efi_loader/efi_var_file.c
index 62e071b..d7dba05 100644
--- a/lib/efi_loader/efi_var_file.c
+++ b/lib/efi_loader/efi_var_file.c
@@ -204,8 +204,11 @@
* File ubootefi.var is read from the EFI system partitions and the variables
* stored in the file are created.
*
- * In case the file does not exist yet or a variable cannot be set EFI_SUCCESS
- * is returned.
+ * On first boot the file ubootefi.var does not exist yet. This is why we must
+ * return EFI_SUCCESS in this case.
+ *
+ * If the variable file is corrupted, e.g. incorrect CRC32, we do not want to
+ * stop the boot process. We deliberately return EFI_SUCCESS in this case, too.
*
* Return: status code
*/
diff --git a/lib/slre.c b/lib/slre.c
index e82a9e7..e1a5044 100644
--- a/lib/slre.c
+++ b/lib/slre.c
@@ -686,6 +686,7 @@
}
if (!slre_compile(&slre, argv[1])) {
+ (void) fclose(fp);
fprintf(stderr, "Error compiling slre: %s\n", slre.err_str);
return 1;
}
diff --git a/net/Kconfig b/net/Kconfig
index 4215889..8c80b3a 100644
--- a/net/Kconfig
+++ b/net/Kconfig
@@ -5,6 +5,7 @@
menuconfig NET
bool "Networking support"
default y
+ imply NETDEVICES
if NET
diff --git a/net/wget.c b/net/wget.c
index 8bb4d72..6ae2237 100644
--- a/net/wget.c
+++ b/net/wget.c
@@ -4,15 +4,20 @@
* Copyright Duncan Hare <dh@synoia.com> 2017
*/
+#include <asm/global_data.h>
#include <command.h>
#include <common.h>
#include <display_options.h>
#include <env.h>
#include <image.h>
+#include <lmb.h>
#include <mapmem.h>
#include <net.h>
#include <net/tcp.h>
#include <net/wget.h>
+#include <stdlib.h>
+
+DECLARE_GLOBAL_DATA_PTR;
static const char bootfile1[] = "GET ";
static const char bootfile3[] = " HTTP/1.0\r\n\r\n";
@@ -56,6 +61,29 @@
static unsigned int retry_tcp_seq_num; /* TCP retry sequence number */
static int retry_len; /* TCP retry length */
+static ulong wget_load_size;
+
+/**
+ * wget_init_max_size() - initialize maximum load size
+ *
+ * Return: 0 if success, -1 if fails
+ */
+static int wget_init_load_size(void)
+{
+ struct lmb lmb;
+ phys_size_t max_size;
+
+ lmb_init_and_reserve(&lmb, gd->bd, (void *)gd->fdt_blob);
+
+ max_size = lmb_get_free_size(&lmb, image_load_addr);
+ if (!max_size)
+ return -1;
+
+ wget_load_size = max_size;
+
+ return 0;
+}
+
/**
* store_block() - store block in memory
* @src: source of data
@@ -64,10 +92,25 @@
*/
static inline int store_block(uchar *src, unsigned int offset, unsigned int len)
{
+ ulong store_addr = image_load_addr + offset;
ulong newsize = offset + len;
uchar *ptr;
+ if (IS_ENABLED(CONFIG_LMB)) {
+ ulong end_addr = image_load_addr + wget_load_size;
+
- ptr = map_sysmem(image_load_addr + offset, len);
+ if (!end_addr)
+ end_addr = ULONG_MAX;
+
+ if (store_addr < image_load_addr ||
+ store_addr + len > end_addr) {
+ printf("\nwget error: ");
+ printf("trying to overwrite reserved memory...\n");
+ return -1;
+ }
+ }
+
+ ptr = map_sysmem(store_addr, len);
memcpy(ptr, src, len);
unmap_sysmem(ptr);
@@ -248,25 +291,39 @@
net_boot_file_size = 0;
- if (len > hlen)
- store_block(pkt + hlen, 0, len - hlen);
+ if (len > hlen) {
+ if (store_block(pkt + hlen, 0, len - hlen) != 0) {
+ wget_loop_state = NETLOOP_FAIL;
+ wget_fail("wget: store error\n", tcp_seq_num, tcp_ack_num, action);
+ net_set_state(NETLOOP_FAIL);
+ return;
+ }
+ }
debug_cond(DEBUG_WGET,
"wget: Connected Pkt %p hlen %x\n",
pkt, hlen);
for (i = 0; i < pkt_q_idx; i++) {
+ int err;
+
ptr1 = map_sysmem(
(phys_addr_t)(pkt_q[i].pkt),
pkt_q[i].len);
- store_block(ptr1,
- pkt_q[i].tcp_seq_num -
- initial_data_seq_num,
- pkt_q[i].len);
+ err = store_block(ptr1,
+ pkt_q[i].tcp_seq_num -
+ initial_data_seq_num,
+ pkt_q[i].len);
unmap_sysmem(ptr1);
debug_cond(DEBUG_WGET,
"wget: Connctd pkt Q %p len %x\n",
pkt_q[i].pkt, pkt_q[i].len);
+ if (err) {
+ wget_loop_state = NETLOOP_FAIL;
+ wget_fail("wget: store error\n", tcp_seq_num, tcp_ack_num, action);
+ net_set_state(NETLOOP_FAIL);
+ return;
+ }
}
}
}
@@ -338,6 +395,7 @@
len) != 0) {
wget_fail("wget: store error\n",
tcp_seq_num, tcp_ack_num, action);
+ net_set_state(NETLOOP_FAIL);
return;
}
@@ -428,6 +486,15 @@
debug_cond(DEBUG_WGET,
"\nwget:Load address: 0x%lx\nLoading: *\b", image_load_addr);
+ if (IS_ENABLED(CONFIG_LMB)) {
+ if (wget_init_load_size()) {
+ printf("\nwget error: ");
+ printf("trying to overwrite reserved memory...\n");
+ net_set_state(NETLOOP_FAIL);
+ return;
+ }
+ }
+
net_set_timeout_handler(wget_timeout, wget_timeout_handler);
tcp_set_tcp_handler(wget_handler);
@@ -446,3 +513,127 @@
wget_send(TCP_SYN, 0, 0, 0);
}
+
+#if (IS_ENABLED(CONFIG_CMD_DNS))
+int wget_with_dns(ulong dst_addr, char *uri)
+{
+ int ret;
+ char *s, *host_name, *file_name, *str_copy;
+
+ /*
+ * Download file using wget.
+ *
+ * U-Boot wget takes the target uri in this format.
+ * "<http server ip>:<file path>" e.g.) 192.168.1.1:/sample/test.iso
+ * Need to resolve the http server ip address before starting wget.
+ */
+ str_copy = strdup(uri);
+ if (!str_copy)
+ return -ENOMEM;
+
+ s = str_copy + strlen("http://");
+ host_name = strsep(&s, "/");
+ if (!s) {
+ log_err("Error: invalied uri, no file path\n");
+ ret = -EINVAL;
+ goto out;
+ }
+ file_name = s;
+
+ /* TODO: If the given uri has ip address for the http server, skip dns */
+ net_dns_resolve = host_name;
+ net_dns_env_var = "httpserverip";
+ if (net_loop(DNS) < 0) {
+ log_err("Error: dns lookup of %s failed, check setup\n", net_dns_resolve);
+ ret = -EINVAL;
+ goto out;
+ }
+ s = env_get("httpserverip");
+ if (!s) {
+ ret = -EINVAL;
+ goto out;
+ }
+
+ strlcpy(net_boot_file_name, s, sizeof(net_boot_file_name));
+ strlcat(net_boot_file_name, ":/", sizeof(net_boot_file_name)); /* append '/' which is removed by strsep() */
+ strlcat(net_boot_file_name, file_name, sizeof(net_boot_file_name));
+ image_load_addr = dst_addr;
+ ret = net_loop(WGET);
+
+out:
+ free(str_copy);
+
+ return ret;
+}
+#endif
+
+/**
+ * wget_validate_uri() - validate the uri for wget
+ *
+ * @uri: uri string
+ *
+ * This function follows the current U-Boot wget implementation.
+ * scheme: only "http:" is supported
+ * authority:
+ * - user information: not supported
+ * - host: supported
+ * - port: not supported(always use the default port)
+ *
+ * Uri is expected to be correctly percent encoded.
+ * This is the minimum check, control codes(0x1-0x19, 0x7F, except '\0')
+ * and space character(0x20) are not allowed.
+ *
+ * TODO: stricter uri conformance check
+ *
+ * Return: true on success, false on failure
+ */
+bool wget_validate_uri(char *uri)
+{
+ char c;
+ bool ret = true;
+ char *str_copy, *s, *authority;
+
+ for (c = 0x1; c < 0x21; c++) {
+ if (strchr(uri, c)) {
+ log_err("invalid character is used\n");
+ return false;
+ }
+ }
+ if (strchr(uri, 0x7f)) {
+ log_err("invalid character is used\n");
+ return false;
+ }
+
+ if (strncmp(uri, "http://", 7)) {
+ log_err("only http:// is supported\n");
+ return false;
+ }
+ str_copy = strdup(uri);
+ if (!str_copy)
+ return false;
+
+ s = str_copy + strlen("http://");
+ authority = strsep(&s, "/");
+ if (!s) {
+ log_err("invalid uri, no file path\n");
+ ret = false;
+ goto out;
+ }
+ s = strchr(authority, '@');
+ if (s) {
+ log_err("user information is not supported\n");
+ ret = false;
+ goto out;
+ }
+ s = strchr(authority, ':');
+ if (s) {
+ log_err("user defined port is not supported\n");
+ ret = false;
+ goto out;
+ }
+
+out:
+ free(str_copy);
+
+ return ret;
+}
diff --git a/scripts/Makefile.spl b/scripts/Makefile.spl
index 32f4384..e450ffd 100644
--- a/scripts/Makefile.spl
+++ b/scripts/Makefile.spl
@@ -7,7 +7,7 @@
# Daniel Schwierzeck, daniel.schwierzeck@googlemail.com.
#
# (C) Copyright 2011
-# Texas Instruments Incorporated - http://www.ti.com/
+# Texas Instruments Incorporated - https://www.ti.com/
# Aneesh V <aneesh@ti.com>
# Based on top-level Makefile.
#
diff --git a/test/boot/bootflow.c b/test/boot/bootflow.c
index f640db8..b97c566 100644
--- a/test/boot/bootflow.c
+++ b/test/boot/bootflow.c
@@ -511,19 +511,27 @@
/**
* prep_mmc_bootdev() - Set up an mmc bootdev so we can access other distros
*
+ * After calling this function, set std->bootdev_order to *@old_orderp to
+ * restore normal operation of bootstd (i.e. with the original bootdev order)
+ *
* @uts: Unit test state
- * @mmc_dev: MMC device to use, e.g. "mmc4"
+ * @mmc_dev: MMC device to use, e.g. "mmc4". Note that this must remain valid
+ * in the caller until
+ * @bind_cros: true to bind the ChromiumOS bootmeth
+ * @old_orderp: Returns the original bootdev order, which must be restored
* Returns 0 on success, -ve on failure
*/
static int prep_mmc_bootdev(struct unit_test_state *uts, const char *mmc_dev,
- bool bind_cros)
+ bool bind_cros, const char ***old_orderp)
{
- const char *order[] = {"mmc2", "mmc1", mmc_dev, NULL};
+ static const char *order[] = {"mmc2", "mmc1", NULL, NULL};
struct udevice *dev, *bootstd;
struct bootstd_priv *std;
const char **old_order;
ofnode root, node;
+ order[2] = mmc_dev;
+
/* Enable the mmc4 node since we need a second bootflow */
root = oftree_root(oftree_default());
node = ofnode_find_subnode(root, mmc_dev);
@@ -546,26 +554,49 @@
std = dev_get_priv(bootstd);
old_order = std->bootdev_order;
std->bootdev_order = order;
+ *old_orderp = old_order;
+
+ return 0;
+}
+
+/**
+ * scan_mmc_bootdev() - Set up an mmc bootdev so we can access other distros
+ *
+ * @uts: Unit test state
+ * @mmc_dev: MMC device to use, e.g. "mmc4"
+ * @bind_cros: true to bind the ChromiumOS bootmeth
+ * Returns 0 on success, -ve on failure
+ */
+static int scan_mmc_bootdev(struct unit_test_state *uts, const char *mmc_dev,
+ bool bind_cros)
+{
+ struct bootstd_priv *std;
+ struct udevice *bootstd;
+ const char **old_order;
+
+ ut_assertok(prep_mmc_bootdev(uts, mmc_dev, bind_cros, &old_order));
console_record_reset_enable();
ut_assertok(run_command("bootflow scan", 0));
ut_assert_console_end();
/* Restore the order used by the device tree */
+ ut_assertok(uclass_first_device_err(UCLASS_BOOTSTD, &bootstd));
+ std = dev_get_priv(bootstd);
std->bootdev_order = old_order;
return 0;
}
/**
- * prep_mmc4_bootdev() - Set up the mmc4 bootdev so we can access a fake Armbian
+ * scan_mmc4_bootdev() - Set up the mmc4 bootdev so we can access a fake Armbian
*
* @uts: Unit test state
* Returns 0 on success, -ve on failure
*/
-static int prep_mmc4_bootdev(struct unit_test_state *uts)
+static int scan_mmc4_bootdev(struct unit_test_state *uts)
{
- ut_assertok(prep_mmc_bootdev(uts, "mmc4", false));
+ ut_assertok(scan_mmc_bootdev(uts, "mmc4", false));
return 0;
}
@@ -573,9 +604,13 @@
/* Check 'bootflow menu' to select a bootflow */
static int bootflow_cmd_menu(struct unit_test_state *uts)
{
+ struct bootstd_priv *std;
char prev[3];
+ /* get access to the current bootflow */
+ ut_assertok(bootstd_get_priv(&std));
+
- ut_assertok(prep_mmc4_bootdev(uts));
+ ut_assertok(scan_mmc4_bootdev(uts));
/* Add keypresses to move to and select the second one in the list */
prev[0] = CTL_CH('n');
@@ -585,8 +620,19 @@
ut_assertok(run_command("bootflow menu", 0));
ut_assert_nextline("Selected: Armbian");
+ ut_assertnonnull(std->cur_bootflow);
ut_assert_console_end();
+ /* Check not selecting anything */
+ prev[0] = '\e';
+ prev[1] = '\0';
+ ut_asserteq(1, console_in_puts(prev));
+
+ ut_asserteq(1, run_command("bootflow menu", 0));
+ ut_assertnull(std->cur_bootflow);
+ ut_assert_nextline("Nothing chosen");
+ ut_assert_console_end();
+
return 0;
}
BOOTSTD_TEST(bootflow_cmd_menu, UT_TESTF_DM | UT_TESTF_SCAN_FDT);
@@ -681,7 +727,7 @@
ofnode node;
int i;
- ut_assertok(prep_mmc4_bootdev(uts));
+ ut_assertok(scan_mmc4_bootdev(uts));
ut_assertok(bootflow_menu_new(&exp));
node = ofnode_path("/bootstd/theme");
@@ -996,7 +1042,7 @@
/* Test ChromiumOS bootmeth */
static int bootflow_cros(struct unit_test_state *uts)
{
- ut_assertok(prep_mmc_bootdev(uts, "mmc5", true));
+ ut_assertok(scan_mmc_bootdev(uts, "mmc5", true));
ut_assertok(run_command("bootflow list", 0));
ut_assert_nextlinen("Showing all");
diff --git a/test/cmd/bdinfo.c b/test/cmd/bdinfo.c
index 8c09281..053f222 100644
--- a/test/cmd/bdinfo.c
+++ b/test/cmd/bdinfo.c
@@ -130,17 +130,11 @@
return 0;
}
-static int bdinfo_test_move(struct unit_test_state *uts)
+static int bdinfo_check_mem(struct unit_test_state *uts)
{
struct bd_info *bd = gd->bd;
int i;
- /* Test moving the working BDINFO to a new location */
- ut_assertok(console_record_reset_enable());
- ut_assertok(run_commandf("bdinfo"));
-
- ut_assertok(test_num_l(uts, "boot_params", 0));
-
for (i = 0; i < CONFIG_NR_DRAM_BANKS; ++i) {
if (bd->bi_dram[i].size) {
ut_assertok(test_num_l(uts, "DRAM bank", i));
@@ -151,6 +145,15 @@
}
}
+ return 0;
+}
+
+static int bdinfo_test_all(struct unit_test_state *uts)
+{
+ ut_assertok(test_num_l(uts, "boot_params", 0));
+
+ ut_assertok(bdinfo_check_mem(uts));
+
/* CONFIG_SYS_HAS_SRAM testing not supported */
ut_assertok(test_num_l(uts, "flashstart", 0));
ut_assertok(test_num_l(uts, "flashsize", 0));
@@ -211,13 +214,78 @@
(unsigned long long)gd->ram_top));
ut_assertok(test_num_l(uts, "malloc base", gd_malloc_start()));
}
+
+ return 0;
+}
+
+static int bdinfo_test_full(struct unit_test_state *uts)
+{
+ /* Test BDINFO full print */
+ ut_assertok(console_record_reset_enable());
+ ut_assertok(run_commandf("bdinfo"));
+ ut_assertok(bdinfo_test_all(uts));
+ ut_assertok(run_commandf("bdinfo -a"));
+ ut_assertok(bdinfo_test_all(uts));
+ ut_assertok(ut_check_console_end(uts));
+
+ return 0;
+}
+
+BDINFO_TEST(bdinfo_test_full, UT_TESTF_CONSOLE_REC);
+
+static int bdinfo_test_help(struct unit_test_state *uts)
+{
+ /* Test BDINFO unknown option help text print */
+ ut_assertok(console_record_reset_enable());
+ if (!CONFIG_IS_ENABLED(GETOPT)) {
+ ut_asserteq(0, run_commandf("bdinfo -h"));
+ ut_assertok(bdinfo_test_all(uts));
+ } else {
+ ut_asserteq(1, run_commandf("bdinfo -h"));
+ ut_assert_nextlinen("bdinfo: invalid option -- h");
+ ut_assert_nextlinen("bdinfo - print Board Info structure");
+ ut_assert_nextline_empty();
+ ut_assert_nextlinen("Usage:");
+ ut_assert_nextlinen("bdinfo");
+ }
+ ut_assertok(ut_check_console_end(uts));
+
+ return 0;
+}
+
+BDINFO_TEST(bdinfo_test_help, UT_TESTF_CONSOLE_REC);
+static int bdinfo_test_memory(struct unit_test_state *uts)
+{
+ /* Test BDINFO memory layout only print */
+ ut_assertok(console_record_reset_enable());
+ ut_assertok(run_commandf("bdinfo -m"));
+ if (!CONFIG_IS_ENABLED(GETOPT))
+ ut_assertok(bdinfo_test_all(uts));
+ else
+ ut_assertok(bdinfo_check_mem(uts));
+ ut_assertok(ut_check_console_end(uts));
+
+ return 0;
+}
+
+BDINFO_TEST(bdinfo_test_memory, UT_TESTF_CONSOLE_REC);
+
+static int bdinfo_test_eth(struct unit_test_state *uts)
+{
+ /* Test BDINFO ethernet settings only print */
+ ut_assertok(console_record_reset_enable());
+ ut_assertok(run_commandf("bdinfo -e"));
+ if (!CONFIG_IS_ENABLED(GETOPT))
+ ut_assertok(bdinfo_test_all(uts));
+ else if (IS_ENABLED(CONFIG_CMD_NET))
+ ut_assertok(test_eth(uts));
ut_assertok(ut_check_console_end(uts));
return 0;
}
-BDINFO_TEST(bdinfo_test_move, UT_TESTF_CONSOLE_REC);
+BDINFO_TEST(bdinfo_test_eth, UT_TESTF_CONSOLE_REC);
int do_ut_bdinfo(struct cmd_tbl *cmdtp, int flag, int argc, char *const argv[])
{
diff --git a/test/cmd/mbr.c b/test/cmd/mbr.c
index 5d74021..46b78e7 100644
--- a/test/cmd/mbr.c
+++ b/test/cmd/mbr.c
@@ -205,16 +205,14 @@
bytes_remaining -= cur_str_size;
}
- else if (num_parts == 5) {
- cur_str_size = sizeof(mbr_parts_p5);
- if (cur_str_size + 1 > bytes_remaining)
- return 1;
- strcat(cur_buf, mbr_parts_p5);
- bytes_remaining -= cur_str_size;
+ else if (num_parts == 5) {
+ cur_str_size = sizeof(mbr_parts_p5);
+ if (cur_str_size + 1 > bytes_remaining)
+ return 1;
+ strcat(cur_buf, mbr_parts_p5);
+ bytes_remaining -= cur_str_size;
- }
- else if (num_parts > 5)
- return 1;
+ }
}
}
}
diff --git a/test/dm/Makefile b/test/dm/Makefile
index cb82d83..a3ce7b3 100644
--- a/test/dm/Makefile
+++ b/test/dm/Makefile
@@ -73,6 +73,7 @@
obj-$(CONFIG_MULTIPLEXER) += mux-emul.o
obj-$(CONFIG_MUX_MMIO) += mux-mmio.o
obj-y += fdtdec.o
+obj-$(CONFIG_MTD_RAW_NAND) += nand.o
obj-$(CONFIG_UT_DM) += nop.o
obj-y += ofnode.o
obj-y += ofread.o
diff --git a/test/dm/eth.c b/test/dm/eth.c
index d05d2a9..bb3dcc6 100644
--- a/test/dm/eth.c
+++ b/test/dm/eth.c
@@ -263,12 +263,16 @@
/* Prepare the test scenario */
for (i = 0; i < DM_TEST_ETH_NUM; i++) {
+ char *addr;
+
ut_assertok(uclass_find_device_by_name(UCLASS_ETH,
ethname[i], &dev[i]));
ut_assertok(device_remove(dev[i], DM_REMOVE_NORMAL));
/* Invalidate MAC address */
- strncpy(ethaddr[i], env_get(addrname[i]), 17);
+ addr = env_get(addrname[i]);
+ ut_assertnonnull(addr);
+ strncpy(ethaddr[i], addr, 17);
/* Must disable access protection for ethaddr before clearing */
env_set(".flags", addrname[i]);
env_set(addrname[i], NULL);
@@ -312,12 +316,16 @@
for (i = 0; i < ARRAY_SIZE(addr); i++) {
char addrname[10];
+ char *env_addr;
if (i)
snprintf(addrname, sizeof(addrname), "eth%daddr", i + 1);
else
strcpy(addrname, "ethaddr");
- ut_asserteq_str(addr[i], env_get(addrname));
+
+ env_addr = env_get(addrname);
+ ut_assertnonnull(env_addr);
+ ut_asserteq_str(addr[i], env_addr);
}
return 0;
diff --git a/test/dm/mux-emul.c b/test/dm/mux-emul.c
index 58233ed..c6aeeb7 100644
--- a/test/dm/mux-emul.c
+++ b/test/dm/mux-emul.c
@@ -1,6 +1,6 @@
// SPDX-License-Identifier: GPL-2.0+
/*
- * Copyright (C) 2020 Texas Instruments Incorporated - http://www.ti.com/
+ * Copyright (C) 2020 Texas Instruments Incorporated - https://www.ti.com/
* Pratyush Yadav <p.yadav@ti.com>
*/
#include <common.h>
diff --git a/test/dm/mux-mmio.c b/test/dm/mux-mmio.c
index fd353d8..27c881d 100644
--- a/test/dm/mux-mmio.c
+++ b/test/dm/mux-mmio.c
@@ -1,6 +1,6 @@
// SPDX-License-Identifier: GPL-2.0+
/*
- * Copyright (C) 2017-2018 Texas Instruments Incorporated - http://www.ti.com/
+ * Copyright (C) 2017-2018 Texas Instruments Incorporated - https://www.ti.com/
* Jean-Jacques Hiblot <jjhiblot@ti.com>
*/
diff --git a/test/dm/nand.c b/test/dm/nand.c
new file mode 100644
index 0000000..0b992fd
--- /dev/null
+++ b/test/dm/nand.c
@@ -0,0 +1,104 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2023 Sean Anderson <seanga2@gmail.com>
+ */
+
+#include <nand.h>
+#include <part.h>
+#include <rand.h>
+#include <dm/test.h>
+#include <test/test.h>
+#include <test/ut.h>
+#include <linux/mtd/mtd.h>
+#include <linux/mtd/rawnand.h>
+
+static int dm_test_nand(struct unit_test_state *uts, int dev, bool end)
+{
+ nand_erase_options_t opts = { };
+ struct mtd_info *mtd;
+ size_t length;
+ loff_t size;
+ char *buf;
+ int *gold;
+ u8 oob[NAND_MAX_OOBSIZE];
+ int i;
+ loff_t off = 0;
+ mtd_oob_ops_t ops = { };
+
+ /* Seed RNG for bit errors */
+ srand((off >> 32) ^ off ^ ~dev);
+
+ mtd = get_nand_dev_by_index(dev);
+ ut_assertnonnull(mtd);
+ size = mtd->erasesize * 4;
+ length = size;
+
+ buf = malloc(size);
+ ut_assertnonnull(buf);
+ gold = malloc(size);
+ ut_assertnonnull(gold);
+
+ /* Mark a block as bad */
+ ut_assertok(mtd_block_markbad(mtd, off + mtd->erasesize));
+
+ /* Erase some stuff */
+ if (end)
+ off = mtd->size - size - mtd->erasesize;
+ opts.offset = off;
+ opts.length = size;
+ opts.spread = 1;
+ opts.lim = U32_MAX;
+ ut_assertok(nand_erase_opts(mtd, &opts));
+
+ /* Make sure everything is erased */
+ memset(gold, 0xff, size);
+ ut_assertok(nand_read_skip_bad(mtd, off, &length, NULL, U64_MAX, buf));
+ ut_asserteq(size, length);
+ ut_asserteq_mem(gold, buf, size);
+
+ /* ...but our bad block marker is still there */
+ ops.oobbuf = oob;
+ ops.ooblen = mtd->oobsize;
+ ut_assertok(mtd_read_oob(mtd, mtd->erasesize, &ops));
+ ut_asserteq(0, oob[mtd_to_nand(mtd)->badblockpos]);
+
+ /* Generate some data and write it */
+ for (i = 0; i < size / sizeof(int); i++)
+ gold[i] = rand();
+ ut_assertok(nand_write_skip_bad(mtd, off, &length, NULL, U64_MAX,
+ (void *)gold, 0));
+ ut_asserteq(size, length);
+
+ /* Verify */
+ ut_assertok(nand_read_skip_bad(mtd, off, &length, NULL, U64_MAX, buf));
+ ut_asserteq(size, length);
+ ut_asserteq_mem(gold, buf, size);
+
+ /* Erase some blocks */
+ memset(((char *)gold) + mtd->erasesize, 0xff, mtd->erasesize * 2);
+ opts.offset = off + mtd->erasesize;
+ opts.length = mtd->erasesize * 2;
+ ut_assertok(nand_erase_opts(mtd, &opts));
+
+ /* Verify */
+ ut_assertok(nand_read_skip_bad(mtd, off, &length, NULL, U64_MAX, buf));
+ ut_asserteq(size, length);
+ ut_asserteq_mem(gold, buf, size);
+
+ return 0;
+}
+
+#define DM_NAND_TEST(dev) \
+static int dm_test_nand##dev##_start(struct unit_test_state *uts) \
+{ \
+ return dm_test_nand(uts, dev, false); \
+} \
+DM_TEST(dm_test_nand##dev##_start, UT_TESTF_SCAN_FDT); \
+static int dm_test_nand##dev##_end(struct unit_test_state *uts) \
+{ \
+ return dm_test_nand(uts, dev, true); \
+} \
+DM_TEST(dm_test_nand##dev##_end, UT_TESTF_SCAN_FDT)
+
+DM_NAND_TEST(0);
+DM_NAND_TEST(1);
diff --git a/test/dm/nop.c b/test/dm/nop.c
index 75b9e7b..f7d9a0f 100644
--- a/test/dm/nop.c
+++ b/test/dm/nop.c
@@ -2,7 +2,7 @@
/*
* Test for the NOP uclass
*
- * (C) Copyright 2019 - Texas Instruments Incorporated - http://www.ti.com/
+ * (C) Copyright 2019 - Texas Instruments Incorporated - https://www.ti.com/
* Jean-Jacques Hiblot <jjhiblot@ti.com>
*/
diff --git a/test/dm/phy.c b/test/dm/phy.c
index 4f91abc..0cf3689 100644
--- a/test/dm/phy.c
+++ b/test/dm/phy.c
@@ -1,6 +1,6 @@
// SPDX-License-Identifier: GPL-2.0+
/*
- * Copyright (C) 2017 Texas Instruments Incorporated - http://www.ti.com/
+ * Copyright (C) 2017 Texas Instruments Incorporated - https://www.ti.com/
* Written by Jean-Jacques Hiblot <jjhiblot@ti.com>
*/
diff --git a/test/dm/remoteproc.c b/test/dm/remoteproc.c
index 7a8ff47..f6f9e50 100644
--- a/test/dm/remoteproc.c
+++ b/test/dm/remoteproc.c
@@ -1,7 +1,7 @@
// SPDX-License-Identifier: GPL-2.0+
/*
* (C) Copyright 2015
- * Texas Instruments Incorporated - http://www.ti.com/
+ * Texas Instruments Incorporated - https://www.ti.com/
*/
#include <common.h>
#include <dm.h>
diff --git a/test/dm/scmi.c b/test/dm/scmi.c
index da45314..e80667e 100644
--- a/test/dm/scmi.c
+++ b/test/dm/scmi.c
@@ -19,6 +19,7 @@
#include <scmi_agent.h>
#include <scmi_agent-uclass.h>
#include <scmi_protocols.h>
+#include <vsprintf.h>
#include <asm/scmi_test.h>
#include <dm/device-internal.h>
#include <dm/test.h>
@@ -206,6 +207,86 @@
DM_TEST(dm_test_scmi_base, UT_TESTF_SCAN_FDT);
+static int dm_test_scmi_cmd(struct unit_test_state *uts)
+{
+ struct udevice *agent_dev;
+ int num_proto = 0;
+ char cmd_out[30];
+
+ if (!CONFIG_IS_ENABLED(CMD_SCMI))
+ return -EAGAIN;
+
+ /* preparation */
+ ut_assertok(uclass_get_device_by_name(UCLASS_SCMI_AGENT, "scmi",
+ &agent_dev));
+ ut_assertnonnull(agent_dev);
+
+ /*
+ * Estimate the number of provided protocols.
+ * This estimation is correct as far as a corresponding
+ * protocol support is added to sandbox fake serer.
+ */
+ if (CONFIG_IS_ENABLED(POWER_DOMAIN))
+ num_proto++;
+ if (CONFIG_IS_ENABLED(CLK_SCMI))
+ num_proto++;
+ if (CONFIG_IS_ENABLED(RESET_SCMI))
+ num_proto++;
+ if (CONFIG_IS_ENABLED(DM_REGULATOR_SCMI))
+ num_proto++;
+
+ /* scmi info */
+ ut_assertok(run_command("scmi info", 0));
+
+ ut_assert_nextline("SCMI device: scmi");
+ snprintf(cmd_out, 30, " protocol version: 0x%x",
+ SCMI_BASE_PROTOCOL_VERSION);
+ ut_assert_nextline(cmd_out);
+ ut_assert_nextline(" # of agents: 2");
+ ut_assert_nextline(" 0: platform");
+ ut_assert_nextline(" > 1: OSPM");
+ snprintf(cmd_out, 30, " # of protocols: %d", num_proto);
+ ut_assert_nextline(cmd_out);
+ if (CONFIG_IS_ENABLED(SCMI_POWER_DOMAIN))
+ ut_assert_nextline(" Power domain management");
+ if (CONFIG_IS_ENABLED(CLK_SCMI))
+ ut_assert_nextline(" Clock management");
+ if (CONFIG_IS_ENABLED(RESET_SCMI))
+ ut_assert_nextline(" Reset domain management");
+ if (CONFIG_IS_ENABLED(DM_REGULATOR_SCMI))
+ ut_assert_nextline(" Voltage domain management");
+ ut_assert_nextline(" vendor: U-Boot");
+ ut_assert_nextline(" sub vendor: Sandbox");
+ ut_assert_nextline(" impl version: 0x1");
+
+ ut_assert_console_end();
+
+ /* scmi perm_dev */
+ ut_assertok(run_command("scmi perm_dev 1 0 1", 0));
+ ut_assert_console_end();
+
+ ut_assert(run_command("scmi perm_dev 1 0 0", 0));
+ ut_assert_nextline("Denying access to device:0 failed (-13)");
+ ut_assert_console_end();
+
+ /* scmi perm_proto */
+ ut_assertok(run_command("scmi perm_proto 1 0 14 1", 0));
+ ut_assert_console_end();
+
+ ut_assert(run_command("scmi perm_proto 1 0 14 0", 0));
+ ut_assert_nextline("Denying access to protocol:0x14 on device:0 failed (-13)");
+ ut_assert_console_end();
+
+ /* scmi reset */
+ ut_assert(run_command("scmi reset 1 1", 0));
+ ut_assert_nextline("Reset failed (-13)");
+ ut_assert_console_end();
+
+ return 0;
+}
+
+DM_TEST(dm_test_scmi_cmd, UT_TESTF_SCAN_FDT);
+
static int dm_test_scmi_power_domains(struct unit_test_state *uts)
{
struct sandbox_scmi_agent *agent;
@@ -217,6 +298,9 @@
u8 *name;
int ret;
+ if (!CONFIG_IS_ENABLED(SCMI_POWER_DOMAIN))
+ return -EAGAIN;
+
/* preparation */
ut_assertok(load_sandbox_scmi_test_devices(uts, &agent, &dev));
ut_assertnonnull(agent);
@@ -317,6 +401,9 @@
int ret_dev;
int ret;
+ if (!CONFIG_IS_ENABLED(CLK_SCMI))
+ return -EAGAIN;
+
ret = load_sandbox_scmi_test_devices(uts, &agent, &dev);
if (ret)
return ret;
@@ -382,6 +469,9 @@
struct udevice *agent_dev, *reset_dev, *dev = NULL;
int ret;
+ if (!CONFIG_IS_ENABLED(RESET_SCMI))
+ return -EAGAIN;
+
ret = load_sandbox_scmi_test_devices(uts, &agent, &dev);
if (ret)
return ret;
@@ -418,6 +508,9 @@
struct udevice *dev;
struct udevice *regul0_dev;
+ if (!CONFIG_IS_ENABLED(DM_REGULATOR_SCMI))
+ return -EAGAIN;
+
ut_assertok(load_sandbox_scmi_test_devices(uts, &agent, &dev));
scmi_devices = sandbox_scmi_devices_ctx(dev);
diff --git a/test/dm/serial.c b/test/dm/serial.c
index 37d17a6..34b783e 100644
--- a/test/dm/serial.c
+++ b/test/dm/serial.c
@@ -29,6 +29,7 @@
&dev_serial));
ut_assertok(serial_tstc());
+ ut_asserteq(115200, fetch_baud_from_dtb());
/*
* test with default config which is the only one supported by
* sandbox_serial driver
diff --git a/test/dm/soc.c b/test/dm/soc.c
index 17e1b5b..8f6c97f 100644
--- a/test/dm/soc.c
+++ b/test/dm/soc.c
@@ -2,7 +2,7 @@
/*
* Test for the SOC uclass
*
- * (C) Copyright 2020 - Texas Instruments Incorporated - http://www.ti.com/
+ * (C) Copyright 2020 - Texas Instruments Incorporated - https://www.ti.com/
* Dave Gerlach <d-gerlach@ti.com>
*/
diff --git a/test/dm/sysreset.c b/test/dm/sysreset.c
index 691683c..5aa69e0 100644
--- a/test/dm/sysreset.c
+++ b/test/dm/sysreset.c
@@ -27,8 +27,8 @@
/* Device 1 is the warm sysreset device */
ut_assertok(uclass_get_device(UCLASS_SYSRESET, 1, &dev));
ut_asserteq(-EACCES, sysreset_request(dev, SYSRESET_WARM));
- ut_asserteq(-ENOSYS, sysreset_request(dev, SYSRESET_COLD));
- ut_asserteq(-ENOSYS, sysreset_request(dev, SYSRESET_POWER));
+ ut_asserteq(-EPROTONOSUPPORT, sysreset_request(dev, SYSRESET_COLD));
+ ut_asserteq(-EPROTONOSUPPORT, sysreset_request(dev, SYSRESET_POWER));
state->sysreset_allowed[SYSRESET_WARM] = true;
ut_asserteq(-EINPROGRESS, sysreset_request(dev, SYSRESET_WARM));
@@ -36,7 +36,7 @@
/* Device 2 is the cold sysreset device */
ut_assertok(uclass_get_device(UCLASS_SYSRESET, 2, &dev));
- ut_asserteq(-ENOSYS, sysreset_request(dev, SYSRESET_WARM));
+ ut_asserteq(-EPROTONOSUPPORT, sysreset_request(dev, SYSRESET_WARM));
state->sysreset_allowed[SYSRESET_COLD] = false;
ut_asserteq(-EACCES, sysreset_request(dev, SYSRESET_COLD));
state->sysreset_allowed[SYSRESET_COLD] = true;
diff --git a/test/image/Kconfig b/test/image/Kconfig
index 8f9e6ae..45b6e8c 100644
--- a/test/image/Kconfig
+++ b/test/image/Kconfig
@@ -23,6 +23,15 @@
help
Test filesystems and the various load methods which use them.
+config SPL_UT_LOAD_NAND
+ bool "Test loading from NAND flash"
+ depends on SANDBOX && SPL_OF_REAL
+ depends on SPL_NAND_SUPPORT
+ depends on SPL_MTD
+ default y
+ help
+ Test the NAND flash load method.
+
config SPL_UT_LOAD_NET
bool "Test loading over TFTP"
depends on SANDBOX && SPL_OF_REAL
@@ -43,6 +52,7 @@
config SPL_UT_LOAD_OS
bool "Test loading from the host OS"
depends on SANDBOX && SPL_LOAD_FIT
+ select SPL_LOAD_BLOCK
default y
help
Smoke test to ensure that loading U-boot works in sandbox.
diff --git a/test/image/Makefile b/test/image/Makefile
index b302101..11ed257 100644
--- a/test/image/Makefile
+++ b/test/image/Makefile
@@ -4,6 +4,7 @@
obj-y += spl_load.o
obj-$(CONFIG_SPL_UT_LOAD_FS) += spl_load_fs.o
+obj-$(CONFIG_SPL_UT_LOAD_NAND) += spl_load_nand.o
obj-$(CONFIG_SPL_UT_LOAD_NET) += spl_load_net.o
obj-$(CONFIG_SPL_NOR_SUPPORT) += spl_load_nor.o
obj-$(CONFIG_SPL_UT_LOAD_OS) += spl_load_os.o
diff --git a/test/image/spl_load.c b/test/image/spl_load.c
index ab4c14d..e1036ef 100644
--- a/test/image/spl_load.c
+++ b/test/image/spl_load.c
@@ -342,12 +342,11 @@
if (check_image_info(uts, &info_write, &info_read))
return CMD_RET_FAILURE;
} else {
- struct spl_load_info load = {
- .bl_len = 1,
- .priv = img,
- .read = spl_test_read,
- };
+ struct spl_load_info load;
+ spl_set_bl_len(&load, 1);
+ load.priv = img;
+ load.read = spl_test_read;
if (type == IMX8)
ut_assertok(spl_load_imx_container(&info_read, &load,
0));
@@ -375,7 +374,7 @@
* LZMA is too complex to generate on the fly, so let's use some data I put in
* the oven^H^H^H^H compressed earlier
*/
-static const char lzma_compressed[] = {
+const char lzma_compressed[] = {
0x5d, 0x00, 0x00, 0x80, 0x00, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
0xff, 0x00, 0x02, 0x05, 0x55, 0x4e, 0x82, 0xbc, 0xc2, 0x42, 0xf6, 0x88,
0x6c, 0x99, 0xd6, 0x82, 0x48, 0xa6, 0x06, 0x67, 0xf8, 0x46, 0x7c, 0xe9,
@@ -611,6 +610,8 @@
0x1e, 0xff, 0xff, 0x80, 0x8e, 0x00, 0x00
};
+const size_t lzma_compressed_size = sizeof(lzma_compressed);
+
int do_spl_test_load(struct unit_test_state *uts, const char *test_name,
enum spl_test_image type, struct spl_image_loader *loader,
int (*write_image)(struct unit_test_state *, void *, size_t))
diff --git a/test/image/spl_load_fs.c b/test/image/spl_load_fs.c
index 297ab08..a89189e 100644
--- a/test/image/spl_load_fs.c
+++ b/test/image/spl_load_fs.c
@@ -220,7 +220,7 @@
bs->root_cluster = cpu_to_le32(root_sector);
vi->ext_boot_sign = 0x29;
- memcpy(vi->fs_type, FAT32_SIGN, sizeof(vi->fs_type));
+ memcpy(vi->fs_type, "FAT32 ", sizeof(vi->fs_type));
memcpy(dst + 0x1fe, "\x55\xAA", 2);
@@ -320,10 +320,11 @@
const char *filename = CONFIG_SPL_FS_LOAD_PAYLOAD_NAME;
struct blk_desc *dev_desc;
size_t fs_size, fs_data, img_size, img_data,
- data_size = SPL_TEST_DATA_SIZE;
+ plain_size = SPL_TEST_DATA_SIZE;
struct spl_image_info info_write = {
.name = test_name,
- .size = data_size,
+ .size = type == LEGACY_LZMA ? lzma_compressed_size :
+ plain_size,
}, info_read = { };
struct disk_partition part = {
.start = 1,
@@ -335,7 +336,7 @@
.boot_device = loader->boot_device,
};
void *fs;
- char *data;
+ char *data, *plain;
img_size = create_image(NULL, type, &info_write, &img_data);
ut_assert(img_size);
@@ -345,7 +346,15 @@
ut_assertnonnull(fs);
data = fs + fs_data + img_data;
- generate_data(data, data_size, test_name);
+ if (type == LEGACY_LZMA) {
+ plain = malloc(plain_size);
+ ut_assertnonnull(plain);
+ generate_data(plain, plain_size, "lzma");
+ memcpy(data, lzma_compressed, lzma_compressed_size);
+ } else {
+ plain = data;
+ generate_data(plain, plain_size, test_name);
+ }
ut_asserteq(img_size, create_image(fs + fs_data, type, &info_write,
NULL));
ut_asserteq(fs_size, create_fs(fs, img_size, filename, NULL));
@@ -366,8 +375,12 @@
ut_assertok(loader->load_image(&info_read, &bootdev));
if (check_image_info(uts, &info_write, &info_read))
return CMD_RET_FAILURE;
- ut_asserteq_mem(data, phys_to_virt(info_write.load_addr), data_size);
+ if (type == LEGACY_LZMA)
+ ut_asserteq(plain_size, info_read.size);
+ ut_asserteq_mem(plain, phys_to_virt(info_write.load_addr), plain_size);
+ if (type == LEGACY_LZMA)
+ free(plain);
free(fs);
return 0;
}
@@ -382,6 +395,8 @@
return spl_test_mmc_fs(uts, test_name, type, create_ext2, true);
}
SPL_IMG_TEST(spl_test_blk, LEGACY, DM_FLAGS);
+SPL_IMG_TEST(spl_test_blk, LEGACY_LZMA, DM_FLAGS);
+SPL_IMG_TEST(spl_test_blk, IMX8, DM_FLAGS);
SPL_IMG_TEST(spl_test_blk, FIT_EXTERNAL, DM_FLAGS);
SPL_IMG_TEST(spl_test_blk, FIT_INTERNAL, DM_FLAGS);
@@ -409,12 +424,10 @@
spl_mmc_clear_cache();
spl_fat_force_reregister();
- if (type == LEGACY &&
- spl_test_mmc_fs(uts, test_name, type, create_ext2, false))
+ if (spl_test_mmc_fs(uts, test_name, type, create_ext2, false))
return CMD_RET_FAILURE;
- if (type != IMX8 &&
- spl_test_mmc_fs(uts, test_name, type, create_fat, false))
+ if (spl_test_mmc_fs(uts, test_name, type, create_fat, false))
return CMD_RET_FAILURE;
return do_spl_test_load(uts, test_name, type,
@@ -423,6 +436,7 @@
spl_test_mmc_write_image);
}
SPL_IMG_TEST(spl_test_mmc, LEGACY, DM_FLAGS);
+SPL_IMG_TEST(spl_test_mmc, LEGACY_LZMA, DM_FLAGS);
SPL_IMG_TEST(spl_test_mmc, IMX8, DM_FLAGS);
SPL_IMG_TEST(spl_test_mmc, FIT_EXTERNAL, DM_FLAGS);
SPL_IMG_TEST(spl_test_mmc, FIT_INTERNAL, DM_FLAGS);
diff --git a/test/image/spl_load_nand.c b/test/image/spl_load_nand.c
new file mode 100644
index 0000000..ec24220
--- /dev/null
+++ b/test/image/spl_load_nand.c
@@ -0,0 +1,56 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2023 Sean Anderson <seanga2@gmail.com>
+ */
+
+#include <nand.h>
+#include <spl.h>
+#include <test/spl.h>
+#include <test/ut.h>
+
+uint32_t spl_nand_get_uboot_raw_page(void);
+
+static int spl_test_nand_write_image(struct unit_test_state *uts, void *img,
+ size_t img_size)
+{
+ uint32_t off = spl_nand_get_uboot_raw_page();
+ struct mtd_info *mtd;
+ struct erase_info erase = { };
+ size_t length;
+
+ nand_reinit();
+ mtd = get_nand_dev_by_index(0);
+ ut_assertnonnull(mtd);
+
+ /* Mark the first block as bad to test that it gets skipped */
+ ut_assertok(mtd_block_markbad(mtd, off & ~mtd->erasesize_mask));
+ off += mtd->erasesize;
+
+ erase.mtd = mtd;
+ erase.len = img_size + (off & mtd->erasesize_mask);
+ erase.len += mtd->erasesize_mask;
+ erase.len &= ~mtd->erasesize_mask;
+ erase.addr = off & ~mtd->erasesize_mask;
+ erase.scrub = 1;
+ ut_assertok(mtd_erase(mtd, &erase));
+
+ ut_assertok(mtd_write(mtd, off, img_size, &length, img));
+
+ return 0;
+}
+
+static int spl_test_nand(struct unit_test_state *uts, const char *test_name,
+ enum spl_test_image type)
+{
+ return do_spl_test_load(uts, test_name, type,
+ SPL_LOAD_IMAGE_GET(1, BOOT_DEVICE_NAND,
+ spl_nand_load_image),
+ spl_test_nand_write_image);
+}
+SPL_IMG_TEST(spl_test_nand, LEGACY, DM_FLAGS);
+SPL_IMG_TEST(spl_test_nand, LEGACY_LZMA, DM_FLAGS);
+SPL_IMG_TEST(spl_test_nand, IMX8, DM_FLAGS);
+SPL_IMG_TEST(spl_test_nand, FIT_INTERNAL, DM_FLAGS);
+#if !IS_ENABLED(CONFIG_SPL_LOAD_FIT_FULL)
+SPL_IMG_TEST(spl_test_nand, FIT_EXTERNAL, DM_FLAGS);
+#endif
diff --git a/test/image/spl_load_net.c b/test/image/spl_load_net.c
index f570cef..9d067a7 100644
--- a/test/image/spl_load_net.c
+++ b/test/image/spl_load_net.c
@@ -248,5 +248,7 @@
return ret;
}
SPL_IMG_TEST(spl_test_net, LEGACY, DM_FLAGS);
+SPL_IMG_TEST(spl_test_net, LEGACY_LZMA, DM_FLAGS);
+SPL_IMG_TEST(spl_test_net, IMX8, DM_FLAGS);
SPL_IMG_TEST(spl_test_net, FIT_INTERNAL, DM_FLAGS);
SPL_IMG_TEST(spl_test_net, FIT_EXTERNAL, DM_FLAGS);
diff --git a/test/image/spl_load_nor.c b/test/image/spl_load_nor.c
index a62bb60..de56863 100644
--- a/test/image/spl_load_nor.c
+++ b/test/image/spl_load_nor.c
@@ -36,4 +36,6 @@
SPL_IMG_TEST(spl_test_nor, LEGACY_LZMA, 0);
SPL_IMG_TEST(spl_test_nor, IMX8, 0);
SPL_IMG_TEST(spl_test_nor, FIT_INTERNAL, 0);
+#if !IS_ENABLED(CONFIG_SPL_LOAD_FIT_FULL)
SPL_IMG_TEST(spl_test_nor, FIT_EXTERNAL, 0);
+#endif
diff --git a/test/image/spl_load_os.c b/test/image/spl_load_os.c
index 49edf15..26228a8 100644
--- a/test/image/spl_load_os.c
+++ b/test/image/spl_load_os.c
@@ -16,14 +16,13 @@
int fd;
};
-static ulong read_fit_image(struct spl_load_info *load, ulong sector,
- ulong count, void *buf)
+static ulong read_fit_image(struct spl_load_info *load, ulong offset,
+ ulong size, void *buf)
{
struct text_ctx *text_ctx = load->priv;
- off_t offset, ret;
+ off_t ret;
ssize_t res;
- offset = sector * load->bl_len;
ret = os_lseek(text_ctx->fd, offset, OS_SEEK_SET);
if (ret != offset) {
printf("Failed to seek to %zx, got %zx (errno=%d)\n", offset,
@@ -31,14 +30,14 @@
return 0;
}
- res = os_read(text_ctx->fd, buf, count * load->bl_len);
+ res = os_read(text_ctx->fd, buf, size);
if (res == -1) {
printf("Failed to read %lx bytes, got %ld (errno=%d)\n",
- count * load->bl_len, res, errno);
+ size, res, errno);
return 0;
}
- return count;
+ return size;
}
static int spl_test_load(struct unit_test_state *uts)
@@ -52,13 +51,12 @@
int fd;
memset(&load, '\0', sizeof(load));
- load.bl_len = 512;
+ spl_set_bl_len(&load, 512);
load.read = read_fit_image;
ret = sandbox_find_next_phase(fname, sizeof(fname), true);
if (ret)
ut_assertf(0, "%s not found, error %d\n", fname, ret);
- load.filename = fname;
header = spl_get_load_buffer(-sizeof(*header), sizeof(*header));
diff --git a/test/image/spl_load_spi.c b/test/image/spl_load_spi.c
index 8f9b6e0..54a9546 100644
--- a/test/image/spl_load_spi.c
+++ b/test/image/spl_load_spi.c
@@ -34,6 +34,7 @@
spl_test_spi_write_image);
}
SPL_IMG_TEST(spl_test_spi, LEGACY, DM_FLAGS);
+SPL_IMG_TEST(spl_test_spi, LEGACY_LZMA, DM_FLAGS);
SPL_IMG_TEST(spl_test_spi, IMX8, DM_FLAGS);
SPL_IMG_TEST(spl_test_spi, FIT_INTERNAL, DM_FLAGS);
#if !IS_ENABLED(CONFIG_SPL_LOAD_FIT_FULL)
diff --git a/test/py/tests/fs_helper.py b/test/py/tests/fs_helper.py
index 9882ddb..380f4c4 100644
--- a/test/py/tests/fs_helper.py
+++ b/test/py/tests/fs_helper.py
@@ -9,7 +9,7 @@
import os
from subprocess import call, check_call, check_output, CalledProcessError
-def mk_fs(config, fs_type, size, prefix):
+def mk_fs(config, fs_type, size, prefix, size_gran = 0x100000):
"""Create a file system volume
Args:
@@ -17,6 +17,7 @@
fs_type (str): File system type, e.g. 'ext4'
size (int): Size of file system in bytes
prefix (str): Prefix string of volume's file name
+ size_gran (int): Size granularity of file system image in bytes
Raises:
CalledProcessError: if any error occurs when creating the filesystem
@@ -24,7 +25,9 @@
fs_img = f'{prefix}.{fs_type}.img'
fs_img = os.path.join(config.persistent_data_dir, fs_img)
- if fs_type == 'fat16':
+ if fs_type == 'fat12':
+ mkfs_opt = '-F 12'
+ elif fs_type == 'fat16':
mkfs_opt = '-F 16'
elif fs_type == 'fat32':
mkfs_opt = '-F 32'
@@ -36,7 +39,7 @@
else:
fs_lnxtype = fs_type
- count = (size + 0x100000 - 1) // 0x100000
+ count = (size + size_gran - 1) // size_gran
# Some distributions do not add /sbin to the default PATH, where mkfs lives
if '/sbin' not in os.environ["PATH"].split(os.pathsep):
@@ -44,7 +47,7 @@
try:
check_call(f'rm -f {fs_img}', shell=True)
- check_call(f'dd if=/dev/zero of={fs_img} bs=1M count={count}',
+ check_call(f'dd if=/dev/zero of={fs_img} bs={size_gran} count={count}',
shell=True)
check_call(f'mkfs.{fs_lnxtype} {mkfs_opt} {fs_img}', shell=True)
if fs_type == 'ext4':
diff --git a/test/py/tests/test_efi_secboot/test_signed.py b/test/py/tests/test_efi_secboot/test_signed.py
index ca52e85..2f862a2 100644
--- a/test/py/tests/test_efi_secboot/test_signed.py
+++ b/test/py/tests/test_efi_secboot/test_signed.py
@@ -29,7 +29,7 @@
output = u_boot_console.run_command_list([
'host bind 0 %s' % disk_img,
'efidebug boot add -b 1 HELLO1 host 0:1 /helloworld.efi.signed -s ""',
- 'efidebug boot next 1',
+ 'efidebug boot order 1',
'bootefi bootmgr'])
assert 'Hello, world!' in ''.join(output)
@@ -37,7 +37,7 @@
# Test Case 1b, run unsigned image if no PK
output = u_boot_console.run_command_list([
'efidebug boot add -b 2 HELLO2 host 0:1 /helloworld.efi -s ""',
- 'efidebug boot next 2',
+ 'efidebug boot order 2',
'bootefi bootmgr'])
assert 'Hello, world!' in ''.join(output)
@@ -59,13 +59,13 @@
assert 'Failed to set EFI variable' not in ''.join(output)
output = u_boot_console.run_command_list([
'efidebug boot add -b 1 HELLO1 host 0:1 /helloworld.efi.signed -s ""',
- 'efidebug boot next 1',
+ 'efidebug boot order 1',
'efidebug test bootmgr'])
assert('\'HELLO1\' failed' in ''.join(output))
assert('efi_start_image() returned: 26' in ''.join(output))
output = u_boot_console.run_command_list([
'efidebug boot add -b 2 HELLO2 host 0:1 /helloworld.efi -s ""',
- 'efidebug boot next 2',
+ 'efidebug boot order 2',
'efidebug test bootmgr'])
assert '\'HELLO2\' failed' in ''.join(output)
assert 'efi_start_image() returned: 26' in ''.join(output)
@@ -77,12 +77,12 @@
'setenv -e -nv -bs -rt -at -i 4000000:$filesize db'])
assert 'Failed to set EFI variable' not in ''.join(output)
output = u_boot_console.run_command_list([
- 'efidebug boot next 2',
+ 'efidebug boot order 2',
'efidebug test bootmgr'])
assert '\'HELLO2\' failed' in ''.join(output)
assert 'efi_start_image() returned: 26' in ''.join(output)
output = u_boot_console.run_command_list([
- 'efidebug boot next 1',
+ 'efidebug boot order 1',
'bootefi bootmgr'])
assert 'Hello, world!' in ''.join(output)
@@ -105,7 +105,7 @@
assert 'Failed to set EFI variable' not in ''.join(output)
output = u_boot_console.run_command_list([
'efidebug boot add -b 1 HELLO host 0:1 /helloworld.efi.signed -s ""',
- 'efidebug boot next 1',
+ 'efidebug boot order 1',
'efidebug test bootmgr'])
assert '\'HELLO\' failed' in ''.join(output)
assert 'efi_start_image() returned: 26' in ''.join(output)
@@ -117,7 +117,7 @@
'setenv -e -nv -bs -rt -at -i 4000000:$filesize db'])
assert 'Failed to set EFI variable' not in ''.join(output)
output = u_boot_console.run_command_list([
- 'efidebug boot next 1',
+ 'efidebug boot order 1',
'efidebug test bootmgr'])
assert '\'HELLO\' failed' in ''.join(output)
assert 'efi_start_image() returned: 26' in ''.join(output)
@@ -143,7 +143,7 @@
assert 'Failed to set EFI variable' not in ''.join(output)
output = u_boot_console.run_command_list([
'efidebug boot add -b 1 HELLO host 0:1 /helloworld.efi.signed -s ""',
- 'efidebug boot next 1',
+ 'efidebug boot order 1',
'efidebug test bootmgr'])
assert '\'HELLO\' failed' in ''.join(output)
assert 'efi_start_image() returned: 26' in ''.join(output)
@@ -170,7 +170,7 @@
assert 'Failed to set EFI variable' not in ''.join(output)
output = u_boot_console.run_command_list([
'efidebug boot add -b 1 HELLO host 0:1 /helloworld.efi.signed_2sigs -s ""',
- 'efidebug boot next 1',
+ 'efidebug boot order 1',
'efidebug test bootmgr'])
assert 'Hello, world!' in ''.join(output)
@@ -181,7 +181,7 @@
'setenv -e -nv -bs -rt -at -a -i 4000000:$filesize db'])
assert 'Failed to set EFI variable' not in ''.join(output)
output = u_boot_console.run_command_list([
- 'efidebug boot next 1',
+ 'efidebug boot order 1',
'efidebug test bootmgr'])
assert 'Hello, world!' in ''.join(output)
@@ -193,7 +193,7 @@
'setenv -e -nv -bs -rt -at -i 4000000:$filesize dbx'])
assert 'Failed to set EFI variable' not in ''.join(output)
output = u_boot_console.run_command_list([
- 'efidebug boot next 1',
+ 'efidebug boot order 1',
'efidebug test bootmgr'])
assert '\'HELLO\' failed' in ''.join(output)
assert 'efi_start_image() returned: 26' in ''.join(output)
@@ -205,7 +205,7 @@
'setenv -e -nv -bs -rt -at -a -i 4000000:$filesize dbx'])
assert 'Failed to set EFI variable' not in ''.join(output)
output = u_boot_console.run_command_list([
- 'efidebug boot next 1',
+ 'efidebug boot order 1',
'efidebug test bootmgr'])
assert '\'HELLO\' failed' in ''.join(output)
assert 'efi_start_image() returned: 26' in ''.join(output)
@@ -230,7 +230,7 @@
assert 'Failed to set EFI variable' not in ''.join(output)
output = u_boot_console.run_command_list([
'efidebug boot add -b 1 HELLO host 0:1 /helloworld.efi.signed_2sigs -s ""',
- 'efidebug boot next 1',
+ 'efidebug boot order 1',
'efidebug test bootmgr'])
assert '\'HELLO\' failed' in ''.join(output)
assert 'efi_start_image() returned: 26' in ''.join(output)
@@ -254,7 +254,7 @@
assert 'Failed to set EFI variable' not in ''.join(output)
output = u_boot_console.run_command_list([
'efidebug boot add -b 1 HELLO host 0:1 /helloworld.efi.signed -s ""',
- 'efidebug boot next 1',
+ 'efidebug boot order 1',
'bootefi bootmgr'])
assert 'Hello, world!' in ''.join(output)
@@ -265,7 +265,7 @@
'setenv -e -nv -bs -rt -at -i 4000000:$filesize dbx'])
assert 'Failed to set EFI variable' not in ''.join(output)
output = u_boot_console.run_command_list([
- 'efidebug boot next 1',
+ 'efidebug boot order 1',
'efidebug test bootmgr'])
assert '\'HELLO\' failed' in ''.join(output)
assert 'efi_start_image() returned: 26' in ''.join(output)
@@ -279,7 +279,7 @@
'setenv -e -nv -bs -rt -at -i 4000000:$filesize dbx'])
assert 'Failed to set EFI variable' not in ''.join(output)
output = u_boot_console.run_command_list([
- 'efidebug boot next 1',
+ 'efidebug boot order 1',
'efidebug test bootmgr'])
assert '\'HELLO\' failed' in ''.join(output)
assert 'efi_start_image() returned: 26' in ''.join(output)
@@ -307,7 +307,7 @@
assert 'Failed to set EFI variable' not in ''.join(output)
output = u_boot_console.run_command_list([
'efidebug boot add -b 1 HELLO host 0:1 /helloworld.efi.signed_2sigs -s ""',
- 'efidebug boot next 1',
+ 'efidebug boot order 1',
'efidebug test bootmgr'])
assert '\'HELLO\' failed' in ''.join(output)
assert 'efi_start_image() returned: 26' in ''.join(output)
@@ -330,7 +330,7 @@
assert 'Failed to set EFI variable' not in ''.join(output)
output = u_boot_console.run_command_list([
'efidebug boot add -b 1 HELLO host 0:1 /helloworld.efi.signed_2sigs -s ""',
- 'efidebug boot next 1',
+ 'efidebug boot order 1',
'efidebug test bootmgr'])
assert '\'HELLO\' failed' in ''.join(output)
assert 'efi_start_image() returned: 26' in ''.join(output)
@@ -349,7 +349,7 @@
output = u_boot_console.run_command_list([
'host bind 0 %s' % disk_img,
'efidebug boot add -b 1 HELLO1 host 0:1 /helloworld_forged.efi.signed -s ""',
- 'efidebug boot next 1',
+ 'efidebug boot order 1',
'efidebug test bootmgr'])
assert('hELLO, world!' in ''.join(output))
@@ -364,7 +364,7 @@
'setenv -e -nv -bs -rt -at -i 4000000:$filesize PK'])
assert 'Failed to set EFI variable' not in ''.join(output)
output = u_boot_console.run_command_list([
- 'efidebug boot next 1',
+ 'efidebug boot order 1',
'efidebug test bootmgr'])
assert(not 'hELLO, world!' in ''.join(output))
assert('\'HELLO1\' failed' in ''.join(output))
diff --git a/test/py/tests/test_efi_secboot/test_signed_intca.py b/test/py/tests/test_efi_secboot/test_signed_intca.py
index d8d599d..8d9a5f3 100644
--- a/test/py/tests/test_efi_secboot/test_signed_intca.py
+++ b/test/py/tests/test_efi_secboot/test_signed_intca.py
@@ -40,7 +40,7 @@
output = u_boot_console.run_command_list([
'efidebug boot add -b 1 HELLO_a host 0:1 /helloworld.efi.signed_a -s ""',
- 'efidebug boot next 1',
+ 'efidebug boot order 1',
'efidebug test bootmgr'])
assert '\'HELLO_a\' failed' in ''.join(output)
assert 'efi_start_image() returned: 26' in ''.join(output)
@@ -49,7 +49,7 @@
# Test Case 1b, signed and authenticated by root CA
output = u_boot_console.run_command_list([
'efidebug boot add -b 2 HELLO_ab host 0:1 /helloworld.efi.signed_ab -s ""',
- 'efidebug boot next 2',
+ 'efidebug boot order 2',
'bootefi bootmgr'])
assert 'Hello, world!' in ''.join(output)
@@ -71,7 +71,7 @@
output = u_boot_console.run_command_list([
'efidebug boot add -b 1 HELLO_abc host 0:1 /helloworld.efi.signed_abc -s ""',
- 'efidebug boot next 1',
+ 'efidebug boot order 1',
'efidebug test bootmgr'])
assert '\'HELLO_abc\' failed' in ''.join(output)
assert 'efi_start_image() returned: 26' in ''.join(output)
@@ -81,7 +81,7 @@
output = u_boot_console.run_command_list([
'fatload host 0:1 4000000 db_b.auth',
'setenv -e -nv -bs -rt -at -i 4000000:$filesize db',
- 'efidebug boot next 1',
+ 'efidebug boot order 1',
'efidebug test bootmgr'])
assert '\'HELLO_abc\' failed' in ''.join(output)
assert 'efi_start_image() returned: 26' in ''.join(output)
@@ -91,7 +91,7 @@
output = u_boot_console.run_command_list([
'fatload host 0:1 4000000 db_c.auth',
'setenv -e -nv -bs -rt -at -i 4000000:$filesize db',
- 'efidebug boot next 1',
+ 'efidebug boot order 1',
'efidebug test bootmgr'])
assert 'Hello, world!' in ''.join(output)
@@ -117,7 +117,7 @@
output = u_boot_console.run_command_list([
'efidebug boot add -b 1 HELLO_abc host 0:1 /helloworld.efi.signed_abc -s ""',
- 'efidebug boot next 1',
+ 'efidebug boot order 1',
'efidebug test bootmgr'])
assert 'Hello, world!' in ''.join(output)
# Or,
@@ -129,7 +129,7 @@
output = u_boot_console.run_command_list([
'fatload host 0:1 4000000 dbx_c.auth',
'setenv -e -nv -bs -rt -at -i 4000000:$filesize dbx',
- 'efidebug boot next 1',
+ 'efidebug boot order 1',
'efidebug test bootmgr'])
assert '\'HELLO_abc\' failed' in ''.join(output)
assert 'efi_start_image() returned: 26' in ''.join(output)
diff --git a/test/py/tests/test_efi_secboot/test_unsigned.py b/test/py/tests/test_efi_secboot/test_unsigned.py
index df63f0d..7c078f2 100644
--- a/test/py/tests/test_efi_secboot/test_unsigned.py
+++ b/test/py/tests/test_efi_secboot/test_unsigned.py
@@ -36,11 +36,11 @@
output = u_boot_console.run_command_list([
'efidebug boot add -b 1 HELLO host 0:1 /helloworld.efi -s ""',
- 'efidebug boot next 1',
+ 'efidebug boot order 1',
'bootefi bootmgr'])
assert '\'HELLO\' failed' in ''.join(output)
output = u_boot_console.run_command_list([
- 'efidebug boot next 1',
+ 'efidebug boot order 1',
'efidebug test bootmgr'])
assert 'efi_start_image() returned: 26' in ''.join(output)
assert 'Hello, world!' not in ''.join(output)
@@ -65,7 +65,7 @@
output = u_boot_console.run_command_list([
'efidebug boot add -b 1 HELLO host 0:1 /helloworld.efi -s ""',
- 'efidebug boot next 1',
+ 'efidebug boot order 1',
'bootefi bootmgr'])
assert 'Hello, world!' in ''.join(output)
@@ -89,11 +89,11 @@
output = u_boot_console.run_command_list([
'efidebug boot add -b 1 HELLO host 0:1 /helloworld.efi -s ""',
- 'efidebug boot next 1',
+ 'efidebug boot order 1',
'bootefi bootmgr'])
assert '\'HELLO\' failed' in ''.join(output)
output = u_boot_console.run_command_list([
- 'efidebug boot next 1',
+ 'efidebug boot order 1',
'efidebug test bootmgr'])
assert 'efi_start_image() returned: 26' in ''.join(output)
assert 'Hello, world!' not in ''.join(output)
@@ -107,11 +107,11 @@
output = u_boot_console.run_command_list([
'efidebug boot add -b 1 HELLO host 0:1 /helloworld.efi -s ""',
- 'efidebug boot next 1',
+ 'efidebug boot order 1',
'bootefi bootmgr'])
assert '\'HELLO\' failed' in ''.join(output)
output = u_boot_console.run_command_list([
- 'efidebug boot next 1',
+ 'efidebug boot order 1',
'efidebug test bootmgr'])
assert 'efi_start_image() returned: 26' in ''.join(output)
assert 'Hello, world!' not in ''.join(output)
diff --git a/test/py/tests/test_fs/conftest.py b/test/py/tests/test_fs/conftest.py
index 0d87d18..fca5448 100644
--- a/test/py/tests/test_fs/conftest.py
+++ b/test/py/tests/test_fs/conftest.py
@@ -9,12 +9,14 @@
from subprocess import call, check_call, check_output, CalledProcessError
from fstest_defs import *
import u_boot_utils as util
+# pylint: disable=E0611
from tests import fs_helper
supported_fs_basic = ['fat16', 'fat32', 'ext4']
-supported_fs_ext = ['fat16', 'fat32']
-supported_fs_mkdir = ['fat16', 'fat32']
-supported_fs_unlink = ['fat16', 'fat32']
+supported_fs_ext = ['fat12', 'fat16', 'fat32']
+supported_fs_fat = ['fat12', 'fat16']
+supported_fs_mkdir = ['fat12', 'fat16', 'fat32']
+supported_fs_unlink = ['fat12', 'fat16', 'fat32']
supported_fs_symlink = ['ext4']
#
@@ -49,6 +51,7 @@
"""
global supported_fs_basic
global supported_fs_ext
+ global supported_fs_fat
global supported_fs_mkdir
global supported_fs_unlink
global supported_fs_symlink
@@ -61,6 +64,7 @@
print('*** FS TYPE modified: %s' % supported_fs)
supported_fs_basic = intersect(supported_fs, supported_fs_basic)
supported_fs_ext = intersect(supported_fs, supported_fs_ext)
+ supported_fs_fat = intersect(supported_fs, supported_fs_fat)
supported_fs_mkdir = intersect(supported_fs, supported_fs_mkdir)
supported_fs_unlink = intersect(supported_fs, supported_fs_unlink)
supported_fs_symlink = intersect(supported_fs, supported_fs_symlink)
@@ -83,6 +87,9 @@
if 'fs_obj_ext' in metafunc.fixturenames:
metafunc.parametrize('fs_obj_ext', supported_fs_ext,
indirect=True, scope='module')
+ if 'fs_obj_fat' in metafunc.fixturenames:
+ metafunc.parametrize('fs_obj_fat', supported_fs_fat,
+ indirect=True, scope='module')
if 'fs_obj_mkdir' in metafunc.fixturenames:
metafunc.parametrize('fs_obj_mkdir', supported_fs_mkdir,
indirect=True, scope='module')
@@ -624,3 +631,44 @@
finally:
call('rmdir %s' % mount_dir, shell=True)
call('rm -f %s' % fs_img, shell=True)
+
+#
+# Fixture for fat test
+#
+@pytest.fixture()
+def fs_obj_fat(request, u_boot_config):
+ """Set up a file system to be used in fat test.
+
+ Args:
+ request: Pytest request object.
+ u_boot_config: U-Boot configuration.
+
+ Return:
+ A fixture for fat test, i.e. a duplet of file system type and
+ volume file name.
+ """
+
+ # the maximum size of a FAT12 filesystem resulting in 4084 clusters
+ MAX_FAT12_SIZE = 261695 * 1024
+
+ # the minimum size of a FAT16 filesystem that can be created with
+ # mkfs.vfat resulting in 4087 clusters
+ MIN_FAT16_SIZE = 8208 * 1024
+
+ fs_type = request.param
+ fs_img = ''
+
+ fs_ubtype = fstype_to_ubname(fs_type)
+ check_ubconfig(u_boot_config, fs_ubtype)
+
+ fs_size = MAX_FAT12_SIZE if fs_type == 'fat12' else MIN_FAT16_SIZE
+
+ try:
+ # the volume size depends on the filesystem
+ fs_img = fs_helper.mk_fs(u_boot_config, fs_type, fs_size, f'{fs_size}', 1024)
+ except:
+ pytest.skip('Setup failed for filesystem: ' + fs_type)
+ return
+ else:
+ yield [fs_ubtype, fs_img]
+ call('rm -f %s' % fs_img, shell=True)
diff --git a/test/py/tests/test_fs/test_erofs.py b/test/py/tests/test_fs/test_erofs.py
index 458a52b..87ad8f2 100644
--- a/test/py/tests/test_fs/test_erofs.py
+++ b/test/py/tests/test_fs/test_erofs.py
@@ -196,6 +196,15 @@
"""
build_dir = u_boot_console.config.build_dir
+ # If the EFI subsystem is enabled and initialized, EFI subsystem tries to
+ # add EFI boot option when the new disk is detected. If there is no EFI
+ # System Partition exists, EFI subsystem outputs error messages and
+ # it ends up with test failure.
+ # Restart U-Boot to clear the previous state.
+ # TODO: Ideally EFI test cases need to be fixed, but it will
+ # increase the number of system reset.
+ u_boot_console.restart_uboot()
+
try:
# setup test environment
make_erofs_image(build_dir)
diff --git a/test/py/tests/test_fs/test_fs_fat.py b/test/py/tests/test_fs/test_fs_fat.py
new file mode 100644
index 0000000..4009d0b
--- /dev/null
+++ b/test/py/tests/test_fs/test_fs_fat.py
@@ -0,0 +1,25 @@
+# SPDX-License-Identifier: GPL-2.0+
+# Copyright (c) 2023 Weidmüller Interface GmbH & Co. KG
+# Author: Christian Taedcke <christian.taedcke@weidmueller.com>
+#
+# U-Boot File System: FAT Test
+
+"""
+This test verifies fat specific file system behaviour.
+"""
+
+import pytest
+import re
+
+@pytest.mark.boardspec('sandbox')
+@pytest.mark.slow
+class TestFsFat(object):
+ def test_fs_fat1(self, u_boot_console, fs_obj_fat):
+ """Test that `fstypes` prints a result which includes `sandbox`."""
+ fs_type,fs_img = fs_obj_fat
+ with u_boot_console.log.section('Test Case 1 - fatinfo'):
+ # Test Case 1 - ls
+ output = u_boot_console.run_command_list([
+ 'host bind 0 %s' % fs_img,
+ 'fatinfo host 0:0'])
+ assert(re.search('Filesystem: %s' % fs_type.upper(), ''.join(output)))
diff --git a/test/py/tests/test_fs/test_squashfs/test_sqfs_ls.py b/test/py/tests/test_fs/test_squashfs/test_sqfs_ls.py
index 527a556..a20a7d1 100644
--- a/test/py/tests/test_fs/test_squashfs/test_sqfs_ls.py
+++ b/test/py/tests/test_fs/test_squashfs/test_sqfs_ls.py
@@ -118,6 +118,15 @@
"""
build_dir = u_boot_console.config.build_dir
+ # If the EFI subsystem is enabled and initialized, EFI subsystem tries to
+ # add EFI boot option when the new disk is detected. If there is no EFI
+ # System Partition exists, EFI subsystem outputs error messages and
+ # it ends up with test failure.
+ # Restart U-Boot to clear the previous state.
+ # TODO: Ideally EFI test cases need to be fixed, but it will
+ # increase the number of system reset.
+ u_boot_console.restart_uboot()
+
# setup test environment
check_mksquashfs_version()
generate_sqfs_src_dir(build_dir)
diff --git a/test/py/tests/test_net.py b/test/py/tests/test_net.py
index b2241ae..2495608 100644
--- a/test/py/tests/test_net.py
+++ b/test/py/tests/test_net.py
@@ -7,6 +7,7 @@
import pytest
import u_boot_utils
import uuid
+import datetime
"""
Note: This test relies on boardenv_* containing configuration values to define
@@ -51,6 +52,8 @@
'addr': 0x10000000,
'size': 5058624,
'crc32': 'c2244b26',
+ 'timeout': 50000,
+ 'fnu': 'ubtest-upload.bin',
}
# Details regarding a file that may be read from a NFS server. This variable
@@ -326,3 +329,71 @@
assert expected_text_default in output
assert "Config file 'default.boot' found" in output
+
+@pytest.mark.buildconfigspec("cmd_crc32")
+@pytest.mark.buildconfigspec("cmd_net")
+@pytest.mark.buildconfigspec("cmd_tftpput")
+def test_net_tftpput(u_boot_console):
+ """Test the tftpput command.
+
+ A file is downloaded from the TFTP server and then uploaded to the TFTP
+ server, its size and its CRC32 are validated.
+
+ The details of the file to download are provided by the boardenv_* file;
+ see the comment at the beginning of this file.
+ """
+
+ if not net_set_up:
+ pytest.skip("Network not initialized")
+
+ f = u_boot_console.config.env.get("env__net_tftp_readable_file", None)
+ if not f:
+ pytest.skip("No TFTP readable file to read")
+
+ addr = f.get("addr", None)
+ if not addr:
+ addr = u_boot_utils.find_ram_base(u_boot_console)
+
+ sz = f.get("size", None)
+ timeout = f.get("timeout", u_boot_console.p.timeout)
+ fn = f["fn"]
+ fnu = f.get("fnu", "_".join([datetime.datetime.now().strftime("%y%m%d%H%M%S"), fn]))
+ expected_text = "Bytes transferred = "
+ if sz:
+ expected_text += "%d" % sz
+
+ with u_boot_console.temporary_timeout(timeout):
+ output = u_boot_console.run_command("tftpboot %x %s" % (addr, fn))
+
+ assert "TIMEOUT" not in output
+ assert expected_text in output
+
+ expected_tftpb_crc = f.get("crc32", None)
+
+ output = u_boot_console.run_command("crc32 $fileaddr $filesize")
+ assert expected_tftpb_crc in output
+
+ with u_boot_console.temporary_timeout(timeout):
+ output = u_boot_console.run_command(
+ "tftpput $fileaddr $filesize $serverip:%s" % (fnu)
+ )
+
+ expected_text = "Bytes transferred = "
+ if sz:
+ expected_text += "%d" % sz
+ addr = addr + sz
+ assert "TIMEOUT" not in output
+ assert "Access violation" not in output
+ assert expected_text in output
+
+ with u_boot_console.temporary_timeout(timeout):
+ output = u_boot_console.run_command("tftpboot %x %s" % (addr, fnu))
+
+ expected_text = "Bytes transferred = "
+ if sz:
+ expected_text += "%d" % sz
+ assert "TIMEOUT" not in output
+ assert expected_text in output
+
+ output = u_boot_console.run_command("crc32 $fileaddr $filesize")
+ assert expected_tftpb_crc in output
diff --git a/test/py/tests/test_ut.py b/test/py/tests/test_ut.py
index 1d9149a..0e3a48e 100644
--- a/test/py/tests/test_ut.py
+++ b/test/py/tests/test_ut.py
@@ -9,6 +9,7 @@
import pytest
import u_boot_utils
+# pylint: disable=E0611
from tests import fs_helper
def mkdir_cond(dirname):
diff --git a/tools/.gitignore b/tools/.gitignore
index 941d38d..0108c56 100644
--- a/tools/.gitignore
+++ b/tools/.gitignore
@@ -34,7 +34,7 @@
/relocate-rela
/spl_size_limit
/sunxi-spl-image-builder
-/tools/generated/**/*.c
+/generated/**/*.c
/update_octeon_header
/version.h
/xway-swap-bytes
diff --git a/tools/binman/entries.rst b/tools/binman/entries.rst
index 2402adb..61de7f1 100644
--- a/tools/binman/entries.rst
+++ b/tools/binman/entries.rst
@@ -1,5 +1,5 @@
Binman Entry Documentation
-===========================
+==========================
This file describes the entry types supported by binman. These entry types can
be placed in an image one by one to build up a final firmware image. It is
diff --git a/tools/patman/__main__.py b/tools/patman/__main__.py
index 197ac1a..f645b38 100755
--- a/tools/patman/__main__.py
+++ b/tools/patman/__main__.py
@@ -6,197 +6,93 @@
"""See README for more information"""
-from argparse import ArgumentParser
try:
- import importlib.resources
+ from importlib import resources
except ImportError:
# for Python 3.6
- import importlib_resources
+ import importlib_resources as resources
import os
import re
import sys
import traceback
-if __name__ == "__main__":
- # Allow 'from patman import xxx to work'
- our_path = os.path.dirname(os.path.realpath(__file__))
- sys.path.append(os.path.join(our_path, '..'))
+# Allow 'from patman import xxx to work'
+# pylint: disable=C0413
+our_path = os.path.dirname(os.path.realpath(__file__))
+sys.path.append(os.path.join(our_path, '..'))
# Our modules
+from patman import cmdline
from patman import control
-from patman import func_test
-from patman import gitutil
-from patman import project
-from patman import settings
from u_boot_pylib import terminal
from u_boot_pylib import test_util
from u_boot_pylib import tools
-epilog = '''Create patches from commits in a branch, check them and email them
-as specified by tags you place in the commits. Use -n to do a dry run first.'''
-
-parser = ArgumentParser(epilog=epilog)
-parser.add_argument('-b', '--branch', type=str,
- help="Branch to process (by default, the current branch)")
-parser.add_argument('-c', '--count', dest='count', type=int,
- default=-1, help='Automatically create patches from top n commits')
-parser.add_argument('-e', '--end', type=int, default=0,
- help='Commits to skip at end of patch list')
-parser.add_argument('-D', '--debug', action='store_true',
- help='Enabling debugging (provides a full traceback on error)')
-parser.add_argument('-p', '--project', default=project.detect_project(),
- help="Project name; affects default option values and "
- "aliases [default: %(default)s]")
-parser.add_argument('-P', '--patchwork-url',
- default='https://patchwork.ozlabs.org',
- help='URL of patchwork server [default: %(default)s]')
-parser.add_argument('-s', '--start', dest='start', type=int,
- default=0, help='Commit to start creating patches from (0 = HEAD)')
-parser.add_argument('-v', '--verbose', action='store_true', dest='verbose',
- default=False, help='Verbose output of errors and warnings')
-parser.add_argument('-H', '--full-help', action='store_true', dest='full_help',
- default=False, help='Display the README file')
-
-subparsers = parser.add_subparsers(dest='cmd')
-send = subparsers.add_parser(
- 'send', help='Format, check and email patches (default command)')
-send.add_argument('-i', '--ignore-errors', action='store_true',
- dest='ignore_errors', default=False,
- help='Send patches email even if patch errors are found')
-send.add_argument('-l', '--limit-cc', dest='limit', type=int, default=None,
- help='Limit the cc list to LIMIT entries [default: %(default)s]')
-send.add_argument('-m', '--no-maintainers', action='store_false',
- dest='add_maintainers', default=True,
- help="Don't cc the file maintainers automatically")
-send.add_argument(
- '--get-maintainer-script', dest='get_maintainer_script', type=str,
- action='store',
- default=os.path.join(gitutil.get_top_level(), 'scripts',
- 'get_maintainer.pl') + ' --norolestats',
- help='File name of the get_maintainer.pl (or compatible) script.')
-send.add_argument('-n', '--dry-run', action='store_true', dest='dry_run',
- default=False, help="Do a dry run (create but don't email patches)")
-send.add_argument('-r', '--in-reply-to', type=str, action='store',
- help="Message ID that this series is in reply to")
-send.add_argument('-t', '--ignore-bad-tags', action='store_true',
- default=False,
- help='Ignore bad tags / aliases (default=warn)')
-send.add_argument('-T', '--thread', action='store_true', dest='thread',
- default=False, help='Create patches as a single thread')
-send.add_argument('--cc-cmd', dest='cc_cmd', type=str, action='store',
- default=None, help='Output cc list for patch file (used by git)')
-send.add_argument('--no-binary', action='store_true', dest='ignore_binary',
- default=False,
- help="Do not output contents of changes in binary files")
-send.add_argument('--no-check', action='store_false', dest='check_patch',
- default=True,
- help="Don't check for patch compliance")
-send.add_argument('--tree', dest='check_patch_use_tree', default=False,
- action='store_true',
- help=("Set `tree` to True. If `tree` is False then we'll "
- "pass '--no-tree' to checkpatch (default: tree=%(default)s)"))
-send.add_argument('--no-tree', dest='check_patch_use_tree',
- action='store_false', help="Set `tree` to False")
-send.add_argument('--no-tags', action='store_false', dest='process_tags',
- default=True, help="Don't process subject tags as aliases")
-send.add_argument('--no-signoff', action='store_false', dest='add_signoff',
- default=True, help="Don't add Signed-off-by to patches")
-send.add_argument('--smtp-server', type=str,
- help="Specify the SMTP server to 'git send-email'")
-send.add_argument('--keep-change-id', action='store_true',
- help='Preserve Change-Id tags in patches to send.')
-send.add_argument('patchfiles', nargs='*')
+def run_patman():
+ """Run patamn
-# Only add the 'test' action if the test data files are available.
-if os.path.exists(func_test.TEST_DATA_DIR):
- test_parser = subparsers.add_parser('test', help='Run tests')
- test_parser.add_argument('testname', type=str, default=None, nargs='?',
- help="Specify the test to run")
+ This is the main program. It collects arguments and runs either the tests or
+ the control module.
+ """
+ args = cmdline.parse_args()
-status = subparsers.add_parser('status',
- help='Check status of patches in patchwork')
-status.add_argument('-C', '--show-comments', action='store_true',
- help='Show comments from each patch')
-status.add_argument('-d', '--dest-branch', type=str,
- help='Name of branch to create with collected responses')
-status.add_argument('-f', '--force', action='store_true',
- help='Force overwriting an existing branch')
+ if not args.debug:
+ sys.tracebacklimit = 0
-# Parse options twice: first to get the project and second to handle
-# defaults properly (which depends on project)
-# Use parse_known_args() in case 'cmd' is omitted
-argv = sys.argv[1:]
-args, rest = parser.parse_known_args(argv)
-if hasattr(args, 'project'):
- settings.Setup(parser, args.project)
- args, rest = parser.parse_known_args(argv)
+ # Run our meagre tests
+ if args.cmd == 'test':
+ # pylint: disable=C0415
+ from patman import func_test
+ from patman import test_checkpatch
-# If we have a command, it is safe to parse all arguments
-if args.cmd:
- args = parser.parse_args(argv)
-else:
- # No command, so insert it after the known arguments and before the ones
- # that presumably relate to the 'send' subcommand
- nargs = len(rest)
- argv = argv[:-nargs] + ['send'] + rest
- args = parser.parse_args(argv)
+ result = test_util.run_test_suites(
+ 'patman', False, False, False, None, None, None,
+ [test_checkpatch.TestPatch, func_test.TestFunctional,
+ 'gitutil', 'settings'])
-if __name__ != "__main__":
- pass
+ sys.exit(0 if result.wasSuccessful() else 1)
-if not args.debug:
- sys.tracebacklimit = 0
+ # Process commits, produce patches files, check them, email them
+ elif args.cmd == 'send':
+ # Called from git with a patch filename as argument
+ # Printout a list of additional CC recipients for this patch
+ if args.cc_cmd:
+ re_line = re.compile(r'(\S*) (.*)')
+ with open(args.cc_cmd, 'r', encoding='utf-8') as inf:
+ for line in inf.readlines():
+ match = re_line.match(line)
+ if match and match.group(1) == args.patchfiles[0]:
+ for cca in match.group(2).split('\0'):
+ cca = cca.strip()
+ if cca:
+ print(cca)
-# Run our meagre tests
-if args.cmd == 'test':
- from patman import func_test
- from patman import test_checkpatch
+ elif args.full_help:
+ with resources.path('patman', 'README.rst') as readme:
+ tools.print_full_help(str(readme))
+ else:
+ # If we are not processing tags, no need to warning about bad ones
+ if not args.process_tags:
+ args.ignore_bad_tags = True
+ control.send(args)
- result = test_util.run_test_suites(
- 'patman', False, False, False, None, None, None,
- [test_checkpatch.TestPatch, func_test.TestFunctional,
- 'gitutil', 'settings'])
+ # Check status of patches in patchwork
+ elif args.cmd == 'status':
+ ret_code = 0
+ try:
+ control.patchwork_status(args.branch, args.count, args.start, args.end,
+ args.dest_branch, args.force,
+ args.show_comments, args.patchwork_url)
+ except Exception as exc:
+ terminal.tprint(f'patman: {type(exc).__name__}: {exc}',
+ colour=terminal.Color.RED)
+ if args.debug:
+ print()
+ traceback.print_exc()
+ ret_code = 1
+ sys.exit(ret_code)
- sys.exit(0 if result.wasSuccessful() else 1)
-# Process commits, produce patches files, check them, email them
-elif args.cmd == 'send':
- # Called from git with a patch filename as argument
- # Printout a list of additional CC recipients for this patch
- if args.cc_cmd:
- fd = open(args.cc_cmd, 'r')
- re_line = re.compile('(\S*) (.*)')
- for line in fd.readlines():
- match = re_line.match(line)
- if match and match.group(1) == args.patchfiles[0]:
- for cc in match.group(2).split('\0'):
- cc = cc.strip()
- if cc:
- print(cc)
- fd.close()
-
- elif args.full_help:
- with importlib.resources.path('patman', 'README.rst') as readme:
- tools.print_full_help(str(readme))
- else:
- # If we are not processing tags, no need to warning about bad ones
- if not args.process_tags:
- args.ignore_bad_tags = True
- control.send(args)
-
-# Check status of patches in patchwork
-elif args.cmd == 'status':
- ret_code = 0
- try:
- control.patchwork_status(args.branch, args.count, args.start, args.end,
- args.dest_branch, args.force,
- args.show_comments, args.patchwork_url)
- except Exception as e:
- terminal.tprint('patman: %s: %s' % (type(e).__name__, e),
- colour=terminal.Color.RED)
- if args.debug:
- print()
- traceback.print_exc()
- ret_code = 1
- sys.exit(ret_code)
+if __name__ == "__main__":
+ sys.exit(run_patman())
diff --git a/tools/patman/cmdline.py b/tools/patman/cmdline.py
new file mode 100644
index 0000000..d6496c0
--- /dev/null
+++ b/tools/patman/cmdline.py
@@ -0,0 +1,147 @@
+# SPDX-License-Identifier: GPL-2.0+
+#
+# Copyright 2023 Google LLC
+#
+
+"""Handles parsing of buildman arguments
+
+This creates the argument parser and uses it to parse the arguments passed in
+"""
+
+import argparse
+import os
+import pathlib
+import sys
+
+from patman import gitutil
+from patman import project
+from patman import settings
+
+PATMAN_DIR = pathlib.Path(__file__).parent
+HAS_TESTS = os.path.exists(PATMAN_DIR / "func_test.py")
+
+def parse_args():
+ """Parse command line arguments from sys.argv[]
+
+ Returns:
+ tuple containing:
+ options: command line options
+ args: command lin arguments
+ """
+ epilog = '''Create patches from commits in a branch, check them and email
+ them as specified by tags you place in the commits. Use -n to do a dry
+ run first.'''
+
+ parser = argparse.ArgumentParser(epilog=epilog)
+ parser.add_argument('-b', '--branch', type=str,
+ help="Branch to process (by default, the current branch)")
+ parser.add_argument('-c', '--count', dest='count', type=int,
+ default=-1, help='Automatically create patches from top n commits')
+ parser.add_argument('-e', '--end', type=int, default=0,
+ help='Commits to skip at end of patch list')
+ parser.add_argument('-D', '--debug', action='store_true',
+ help='Enabling debugging (provides a full traceback on error)')
+ parser.add_argument('-p', '--project', default=project.detect_project(),
+ help="Project name; affects default option values and "
+ "aliases [default: %(default)s]")
+ parser.add_argument('-P', '--patchwork-url',
+ default='https://patchwork.ozlabs.org',
+ help='URL of patchwork server [default: %(default)s]')
+ parser.add_argument('-s', '--start', dest='start', type=int,
+ default=0, help='Commit to start creating patches from (0 = HEAD)')
+ parser.add_argument(
+ '-v', '--verbose', action='store_true', dest='verbose', default=False,
+ help='Verbose output of errors and warnings')
+ parser.add_argument(
+ '-H', '--full-help', action='store_true', dest='full_help',
+ default=False, help='Display the README file')
+
+ subparsers = parser.add_subparsers(dest='cmd')
+ send = subparsers.add_parser(
+ 'send', help='Format, check and email patches (default command)')
+ send.add_argument('-i', '--ignore-errors', action='store_true',
+ dest='ignore_errors', default=False,
+ help='Send patches email even if patch errors are found')
+ send.add_argument('-l', '--limit-cc', dest='limit', type=int, default=None,
+ help='Limit the cc list to LIMIT entries [default: %(default)s]')
+ send.add_argument('-m', '--no-maintainers', action='store_false',
+ dest='add_maintainers', default=True,
+ help="Don't cc the file maintainers automatically")
+ send.add_argument(
+ '--get-maintainer-script', dest='get_maintainer_script', type=str,
+ action='store',
+ default=os.path.join(gitutil.get_top_level(), 'scripts',
+ 'get_maintainer.pl') + ' --norolestats',
+ help='File name of the get_maintainer.pl (or compatible) script.')
+ send.add_argument('-n', '--dry-run', action='store_true', dest='dry_run',
+ default=False, help="Do a dry run (create but don't email patches)")
+ send.add_argument('-r', '--in-reply-to', type=str, action='store',
+ help="Message ID that this series is in reply to")
+ send.add_argument('-t', '--ignore-bad-tags', action='store_true',
+ default=False,
+ help='Ignore bad tags / aliases (default=warn)')
+ send.add_argument('-T', '--thread', action='store_true', dest='thread',
+ default=False, help='Create patches as a single thread')
+ send.add_argument('--cc-cmd', dest='cc_cmd', type=str, action='store',
+ default=None, help='Output cc list for patch file (used by git)')
+ send.add_argument('--no-binary', action='store_true', dest='ignore_binary',
+ default=False,
+ help="Do not output contents of changes in binary files")
+ send.add_argument('--no-check', action='store_false', dest='check_patch',
+ default=True,
+ help="Don't check for patch compliance")
+ send.add_argument(
+ '--tree', dest='check_patch_use_tree', default=False,
+ action='store_true',
+ help=("Set `tree` to True. If `tree` is False then we'll pass "
+ "'--no-tree' to checkpatch (default: tree=%(default)s)"))
+ send.add_argument('--no-tree', dest='check_patch_use_tree',
+ action='store_false', help="Set `tree` to False")
+ send.add_argument(
+ '--no-tags', action='store_false', dest='process_tags', default=True,
+ help="Don't process subject tags as aliases")
+ send.add_argument('--no-signoff', action='store_false', dest='add_signoff',
+ default=True, help="Don't add Signed-off-by to patches")
+ send.add_argument('--smtp-server', type=str,
+ help="Specify the SMTP server to 'git send-email'")
+ send.add_argument('--keep-change-id', action='store_true',
+ help='Preserve Change-Id tags in patches to send.')
+
+ send.add_argument('patchfiles', nargs='*')
+
+ # Only add the 'test' action if the test data files are available.
+ if HAS_TESTS:
+ test_parser = subparsers.add_parser('test', help='Run tests')
+ test_parser.add_argument('testname', type=str, default=None, nargs='?',
+ help="Specify the test to run")
+
+ status = subparsers.add_parser('status',
+ help='Check status of patches in patchwork')
+ status.add_argument('-C', '--show-comments', action='store_true',
+ help='Show comments from each patch')
+ status.add_argument(
+ '-d', '--dest-branch', type=str,
+ help='Name of branch to create with collected responses')
+ status.add_argument('-f', '--force', action='store_true',
+ help='Force overwriting an existing branch')
+
+ # Parse options twice: first to get the project and second to handle
+ # defaults properly (which depends on project)
+ # Use parse_known_args() in case 'cmd' is omitted
+ argv = sys.argv[1:]
+ args, rest = parser.parse_known_args(argv)
+ if hasattr(args, 'project'):
+ settings.Setup(parser, args.project)
+ args, rest = parser.parse_known_args(argv)
+
+ # If we have a command, it is safe to parse all arguments
+ if args.cmd:
+ args = parser.parse_args(argv)
+ else:
+ # No command, so insert it after the known arguments and before the ones
+ # that presumably relate to the 'send' subcommand
+ nargs = len(rest)
+ argv = argv[:-nargs] + ['send'] + rest
+ args = parser.parse_args(argv)
+
+ return args
diff --git a/tools/renesas_spkgimage.c b/tools/renesas_spkgimage.c
index 5cd81dd..ce3b2b2 100644
--- a/tools/renesas_spkgimage.c
+++ b/tools/renesas_spkgimage.c
@@ -147,7 +147,8 @@
/* Check the marker bytes */
if (memcmp(header->marker, marker, 4)) {
- fprintf(stderr, "Error: invalid marker bytes\n");
+ if (param->type == IH_TYPE_RENESAS_SPKG)
+ fprintf(stderr, "Error: invalid marker bytes\n");
return -EINVAL;
}
