tree 87c48bc6742a97768be857d92f18976665d3feef
parent 7c5eca759f34c045b118feaa8235a5c556e4b23a
author Stefan Agner <stefan@agner.ch> 1398269871 +0200
committer Albert ARIBAUD <albert.u.boot@aribaud.net> 1401025572 +0200

arm: vf610: add DDR_SEL_PAD_CONTR register

Set DDR_SEL_PAD_CONTR register explicitly to DDR3 which solves RAM
issues with newer silicon (1.1). This register was added in revision
4 of the Vybrid Reference Manual.

Signed-off-by: Stefan Agner <stefan@agner.ch>