diff --git a/arch/arm/mach-rmobile/Kconfig.64 b/arch/arm/mach-rmobile/Kconfig.64
index 5db93ac..c79b39d 100644
--- a/arch/arm/mach-rmobile/Kconfig.64
+++ b/arch/arm/mach-rmobile/Kconfig.64
@@ -20,11 +20,17 @@
 	help
           Support for Renesas R-Car Gen3 platform
 
+config TARGET_ULCB
+	bool "ULCB board"
+	help
+          Support for Renesas R-Car Gen3 ULCB platform
+
 endchoice
 
 config SYS_SOC
 	default "rmobile"
 
 source "board/renesas/salvator-x/Kconfig"
+source "board/renesas/ulcb/Kconfig"
 
 endif
diff --git a/board/renesas/ulcb/Kconfig b/board/renesas/ulcb/Kconfig
new file mode 100644
index 0000000..1e9a10d
--- /dev/null
+++ b/board/renesas/ulcb/Kconfig
@@ -0,0 +1,15 @@
+if TARGET_ULCB
+
+config SYS_SOC
+	default "rmobile"
+
+config SYS_BOARD
+	default "ulcb"
+
+config SYS_VENDOR
+	default "renesas"
+
+config SYS_CONFIG_NAME
+	default "ulcb"
+
+endif
diff --git a/board/renesas/ulcb/MAINTAINERS b/board/renesas/ulcb/MAINTAINERS
new file mode 100644
index 0000000..e7cdc52
--- /dev/null
+++ b/board/renesas/ulcb/MAINTAINERS
@@ -0,0 +1,7 @@
+ULCB BOARD
+M:	Marek Vasut <marek.vasut+renesas@gmail.com>
+S:	Maintained
+F:	board/renesas/ulcb/
+F:	include/configs/ulcb.h
+F:	configs/r8a7795_ulcb_defconfig
+F:	configs/r8a7796_ulcb_defconfig
diff --git a/board/renesas/ulcb/Makefile b/board/renesas/ulcb/Makefile
new file mode 100644
index 0000000..6fe0b48
--- /dev/null
+++ b/board/renesas/ulcb/Makefile
@@ -0,0 +1,9 @@
+#
+# board/renesas/ulcb/Makefile
+#
+# Copyright (C) 2017 Renesas Electronics Corporation
+#
+# SPDX-License-Identifier: GPL-2.0+
+#
+
+obj-y	:= ulcb.o cpld.o ../rcar-common/common.o
diff --git a/board/renesas/ulcb/cpld.c b/board/renesas/ulcb/cpld.c
new file mode 100644
index 0000000..f9384b0
--- /dev/null
+++ b/board/renesas/ulcb/cpld.c
@@ -0,0 +1,167 @@
+/*
+ * ULCB board CPLD access support
+ *
+ * Copyright (C) 2017 Renesas Electronics Corporation
+ * Copyright (C) 2017 Cogent Embedded, Inc.
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <common.h>
+#include <spi.h>
+#include <asm/io.h>
+#include <asm/gpio.h>
+
+#define SCLK			GPIO_GP_6_8
+#define SSTBZ			GPIO_GP_2_3
+#define MOSI			GPIO_GP_6_7
+#define MISO			GPIO_GP_6_10
+
+#define CPLD_ADDR_MODE		0x00 /* RW */
+#define CPLD_ADDR_MUX		0x02 /* RW */
+#define CPLD_ADDR_DIPSW6	0x08 /* R */
+#define CPLD_ADDR_RESET		0x80 /* RW */
+#define CPLD_ADDR_VERSION	0xFF /* R */
+
+static int cpld_initialized;
+
+int spi_cs_is_valid(unsigned int bus, unsigned int cs)
+{
+	/* Always valid */
+	return 1;
+}
+
+void spi_cs_activate(struct spi_slave *slave)
+{
+	/* Always active */
+}
+
+void spi_cs_deactivate(struct spi_slave *slave)
+{
+	/* Always active */
+}
+
+void ulcb_softspi_sda(int set)
+{
+	gpio_set_value(MOSI, set);
+}
+
+void ulcb_softspi_scl(int set)
+{
+	gpio_set_value(SCLK, set);
+}
+
+unsigned char ulcb_softspi_read(void)
+{
+	return !!gpio_get_value(MISO);
+}
+
+static void cpld_rw(u8 write)
+{
+	gpio_set_value(MOSI, write);
+	gpio_set_value(SSTBZ, 0);
+	gpio_set_value(SCLK, 1);
+	gpio_set_value(SCLK, 0);
+	gpio_set_value(SSTBZ, 1);
+}
+
+static u32 cpld_read(u8 addr)
+{
+	u32 data = 0;
+
+	spi_xfer(NULL, 8, &addr, NULL, SPI_XFER_BEGIN | SPI_XFER_END);
+
+	cpld_rw(0);
+
+	spi_xfer(NULL, 32, NULL, &data, SPI_XFER_BEGIN | SPI_XFER_END);
+
+	return swab32(data);
+}
+
+static void cpld_write(u8 addr, u32 data)
+{
+	data = swab32(data);
+
+	spi_xfer(NULL, 32, &data, NULL, SPI_XFER_BEGIN | SPI_XFER_END);
+
+	spi_xfer(NULL, 8, NULL, &addr, SPI_XFER_BEGIN | SPI_XFER_END);
+
+	cpld_rw(1);
+}
+
+static void cpld_init(void)
+{
+	if (cpld_initialized)
+		return;
+
+	/* PULL-UP on MISO line */
+	setbits_le32(PFC_PUEN5, PUEN_SSI_SDATA4);
+
+	gpio_request(SCLK, NULL);
+	gpio_request(SSTBZ, NULL);
+	gpio_request(MOSI, NULL);
+	gpio_request(MISO, NULL);
+
+	gpio_direction_output(SCLK, 0);
+	gpio_direction_output(SSTBZ, 1);
+	gpio_direction_output(MOSI, 0);
+	gpio_direction_input(MISO);
+
+	/* Dummy read */
+	cpld_read(CPLD_ADDR_VERSION);
+
+	cpld_initialized = 1;
+}
+
+static int do_cpld(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
+{
+	u32 addr, val;
+
+	cpld_init();
+
+	if (argc == 2 && strcmp(argv[1], "info") == 0) {
+		printf("CPLD version:\t\t\t0x%08x\n",
+		       cpld_read(CPLD_ADDR_VERSION));
+		printf("H3 Mode setting (MD0..28):\t0x%08x\n",
+		       cpld_read(CPLD_ADDR_MODE));
+		printf("Multiplexer settings:\t\t0x%08x\n",
+		       cpld_read(CPLD_ADDR_MUX));
+		printf("DIPSW (SW6):\t\t\t0x%08x\n",
+		       cpld_read(CPLD_ADDR_DIPSW6));
+		return 0;
+	}
+
+	if (argc < 3)
+		return CMD_RET_USAGE;
+
+	addr = simple_strtoul(argv[2], NULL, 16);
+	if (!(addr == CPLD_ADDR_VERSION || addr == CPLD_ADDR_MODE ||
+	      addr == CPLD_ADDR_MUX || addr == CPLD_ADDR_DIPSW6 ||
+	      addr == CPLD_ADDR_RESET)) {
+		printf("Invalid CPLD register address\n");
+		return CMD_RET_USAGE;
+	}
+
+	if (argc == 3 && strcmp(argv[1], "read") == 0) {
+		printf("0x%x\n", cpld_read(addr));
+	} else if (argc == 4 && strcmp(argv[1], "write") == 0) {
+		val = simple_strtoul(argv[3], NULL, 16);
+		cpld_write(addr, val);
+	}
+
+	return 0;
+}
+
+U_BOOT_CMD(
+	cpld, 4, 1, do_cpld,
+	"CPLD access",
+	"info\n"
+	"cpld read addr\n"
+	"cpld write addr val\n"
+);
+
+void reset_cpu(ulong addr)
+{
+	cpld_init();
+	cpld_write(CPLD_ADDR_RESET, 1);
+}
diff --git a/board/renesas/ulcb/ulcb.c b/board/renesas/ulcb/ulcb.c
new file mode 100644
index 0000000..4005ec8
--- /dev/null
+++ b/board/renesas/ulcb/ulcb.c
@@ -0,0 +1,257 @@
+/*
+ * board/renesas/ulcb/ulcb.c
+ *     This file is ULCB board support.
+ *
+ * Copyright (C) 2017 Renesas Electronics Corporation
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <malloc.h>
+#include <netdev.h>
+#include <dm.h>
+#include <dm/platform_data/serial_sh.h>
+#include <asm/processor.h>
+#include <asm/mach-types.h>
+#include <asm/io.h>
+#include <linux/errno.h>
+#include <asm/arch/sys_proto.h>
+#include <asm/gpio.h>
+#include <asm/arch/gpio.h>
+#include <asm/arch/rmobile.h>
+#include <asm/arch/rcar-mstp.h>
+#include <asm/arch/sh_sdhi.h>
+#include <i2c.h>
+#include <mmc.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+#define CPGWPCR	0xE6150904
+#define CPGWPR  0xE615090C
+
+#define CLK2MHZ(clk)	(clk / 1000 / 1000)
+void s_init(void)
+{
+	struct rcar_rwdt *rwdt = (struct rcar_rwdt *)RWDT_BASE;
+	struct rcar_swdt *swdt = (struct rcar_swdt *)SWDT_BASE;
+
+	/* Watchdog init */
+	writel(0xA5A5A500, &rwdt->rwtcsra);
+	writel(0xA5A5A500, &swdt->swtcsra);
+
+	writel(0xA5A50000, CPGWPCR);
+	writel(0xFFFFFFFF, CPGWPR);
+}
+
+#define GSX_MSTP112		BIT(12)	/* 3DG */
+#define TMU0_MSTP125		BIT(25)	/* secure */
+#define TMU1_MSTP124		BIT(24)	/* non-secure */
+#define SCIF2_MSTP310		BIT(10)	/* SCIF2 */
+#define ETHERAVB_MSTP812	BIT(12)
+#define DVFS_MSTP926		BIT(26)
+#define SD0_MSTP314		BIT(14)
+#define SD1_MSTP313		BIT(13)
+#define SD2_MSTP312		BIT(12)	/* either MMC0 */
+
+#define SD0CKCR			0xE6150074
+#define SD1CKCR			0xE6150078
+#define SD2CKCR			0xE6150268
+#define SD3CKCR			0xE615026C
+
+int board_early_init_f(void)
+{
+	/* TMU0,1 */		/* which use ? */
+	mstp_clrbits_le32(MSTPSR1, SMSTPCR1, TMU0_MSTP125 | TMU1_MSTP124);
+	/* SCIF2 */
+	mstp_clrbits_le32(MSTPSR3, SMSTPCR3, SCIF2_MSTP310);
+	/* EHTERAVB */
+	mstp_clrbits_le32(MSTPSR8, SMSTPCR8, ETHERAVB_MSTP812);
+	/* eMMC */
+	mstp_clrbits_le32(MSTPSR3, SMSTPCR3, SD1_MSTP313 | SD2_MSTP312);
+	/* SDHI0 */
+	mstp_clrbits_le32(MSTPSR3, SMSTPCR3, SD0_MSTP314);
+
+	writel(0, SD0CKCR);
+	writel(0, SD1CKCR);
+	writel(0, SD2CKCR);
+	writel(0, SD3CKCR);
+
+#if defined(CONFIG_SYS_I2C) && defined(CONFIG_SYS_I2C_SH)
+	/* DVFS for reset */
+	mstp_clrbits_le32(MSTPSR9, SMSTPCR9, DVFS_MSTP926);
+#endif
+	return 0;
+}
+
+/* SYSC */
+/* R/- 32 Power status register 2(3DG) */
+#define	SYSC_PWRSR2	0xE6180100
+/* -/W 32 Power resume control register 2 (3DG) */
+#define	SYSC_PWRONCR2	0xE618010C
+
+int board_init(void)
+{
+	/* adress of boot parameters */
+	gd->bd->bi_boot_params = CONFIG_SYS_TEXT_BASE + 0x50000;
+
+	/* Init PFC controller */
+#if defined(CONFIG_R8A7795)
+	r8a7795_pinmux_init();
+#elif defined(CONFIG_R8A7796)
+	r8a7796_pinmux_init();
+#endif
+
+	/* USB1 pull-up */
+	setbits_le32(PFC_PUEN6, PUEN_USB1_OVC | PUEN_USB1_PWEN);
+
+#ifdef CONFIG_RAVB
+	/* EtherAVB Enable */
+	/* GPSR2 */
+	gpio_request(GPIO_GFN_AVB_AVTP_CAPTURE_A, NULL);
+	gpio_request(GPIO_GFN_AVB_AVTP_MATCH_A, NULL);
+	gpio_request(GPIO_GFN_AVB_LINK, NULL);
+	gpio_request(GPIO_GFN_AVB_PHY_INT, NULL);
+	gpio_request(GPIO_GFN_AVB_MAGIC, NULL);
+	gpio_request(GPIO_GFN_AVB_MDC, NULL);
+
+	/* IPSR0 */
+	gpio_request(GPIO_IFN_AVB_MDC, NULL);
+	gpio_request(GPIO_IFN_AVB_MAGIC, NULL);
+	gpio_request(GPIO_IFN_AVB_PHY_INT, NULL);
+	gpio_request(GPIO_IFN_AVB_LINK, NULL);
+	gpio_request(GPIO_IFN_AVB_AVTP_MATCH_A, NULL);
+	gpio_request(GPIO_IFN_AVB_AVTP_CAPTURE_A, NULL);
+	/* IPSR1 */
+	gpio_request(GPIO_FN_AVB_AVTP_PPS, NULL);
+	/* IPSR2 */
+	gpio_request(GPIO_FN_AVB_AVTP_MATCH_B, NULL);
+	/* IPSR3 */
+	gpio_request(GPIO_FN_AVB_AVTP_CAPTURE_B, NULL);
+
+	/* AVB_PHY_RST */
+	gpio_request(GPIO_GP_2_10, NULL);
+	gpio_direction_output(GPIO_GP_2_10, 0);
+	mdelay(20);
+	gpio_set_value(GPIO_GP_2_10, 1);
+	udelay(1);
+#endif
+
+	return 0;
+}
+
+static struct eth_pdata salvator_x_ravb_platdata = {
+	.iobase		= 0xE6800000,
+	.phy_interface	= 0,
+	.max_speed	= 1000,
+};
+
+U_BOOT_DEVICE(salvator_x_ravb) = {
+	.name		= "ravb",
+	.platdata	= &salvator_x_ravb_platdata,
+};
+
+#ifdef CONFIG_SH_SDHI
+int board_mmc_init(bd_t *bis)
+{
+	int ret = -ENODEV;
+
+	/* SDHI0 */
+	gpio_request(GPIO_GFN_SD0_DAT0, NULL);
+	gpio_request(GPIO_GFN_SD0_DAT1, NULL);
+	gpio_request(GPIO_GFN_SD0_DAT2, NULL);
+	gpio_request(GPIO_GFN_SD0_DAT3, NULL);
+	gpio_request(GPIO_GFN_SD0_CLK, NULL);
+	gpio_request(GPIO_GFN_SD0_CMD, NULL);
+	gpio_request(GPIO_GFN_SD0_CD, NULL);
+	gpio_request(GPIO_GFN_SD0_WP, NULL);
+
+	gpio_request(GPIO_GP_5_2, NULL);
+	gpio_request(GPIO_GP_5_1, NULL);
+	gpio_direction_output(GPIO_GP_5_2, 1);	/* power on */
+	gpio_direction_output(GPIO_GP_5_1, 1);	/* 1: 3.3V, 0: 1.8V */
+
+	ret = sh_sdhi_init(CONFIG_SYS_SH_SDHI0_BASE, 0,
+			   SH_SDHI_QUIRK_64BIT_BUF);
+	if (ret)
+		return ret;
+
+	/* SDHI1/SDHI2 eMMC */
+	gpio_request(GPIO_GFN_SD1_DAT0, NULL);
+	gpio_request(GPIO_GFN_SD1_DAT1, NULL);
+	gpio_request(GPIO_GFN_SD1_DAT2, NULL);
+	gpio_request(GPIO_GFN_SD1_DAT3, NULL);
+	gpio_request(GPIO_GFN_SD2_DAT0, NULL);
+	gpio_request(GPIO_GFN_SD2_DAT1, NULL);
+	gpio_request(GPIO_GFN_SD2_DAT2, NULL);
+	gpio_request(GPIO_GFN_SD2_DAT3, NULL);
+	gpio_request(GPIO_GFN_SD2_CLK, NULL);
+#if defined(CONFIG_R8A7795)
+	gpio_request(GPIO_GFN_SD2_CMD, NULL);
+#elif defined(CONFIG_R8A7796)
+	gpio_request(GPIO_FN_SD2_CMD, NULL);
+#else
+#error Only R8A7795 and R87796 is supported
+#endif
+	gpio_request(GPIO_GP_5_3, NULL);
+	gpio_request(GPIO_GP_5_9, NULL);
+	gpio_direction_output(GPIO_GP_5_3, 0);	/* 1: 3.3V, 0: 1.8V */
+	gpio_direction_output(GPIO_GP_5_9, 0);	/* 1: 3.3V, 0: 1.8V */
+
+	ret = sh_sdhi_init(CONFIG_SYS_SH_SDHI2_BASE, 1,
+			   SH_SDHI_QUIRK_64BIT_BUF);
+
+	return ret;
+}
+#endif
+
+int dram_init(void)
+{
+	gd->ram_size = PHYS_SDRAM_1_SIZE;
+#if (CONFIG_NR_DRAM_BANKS >= 2)
+	gd->ram_size += PHYS_SDRAM_2_SIZE;
+#endif
+#if (CONFIG_NR_DRAM_BANKS >= 3)
+	gd->ram_size += PHYS_SDRAM_3_SIZE;
+#endif
+#if (CONFIG_NR_DRAM_BANKS >= 4)
+	gd->ram_size += PHYS_SDRAM_4_SIZE;
+#endif
+
+	return 0;
+}
+
+int dram_init_banksize(void)
+{
+	gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
+	gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE;
+#if (CONFIG_NR_DRAM_BANKS >= 2)
+	gd->bd->bi_dram[1].start = PHYS_SDRAM_2;
+	gd->bd->bi_dram[1].size = PHYS_SDRAM_2_SIZE;
+#endif
+#if (CONFIG_NR_DRAM_BANKS >= 3)
+	gd->bd->bi_dram[2].start = PHYS_SDRAM_3;
+	gd->bd->bi_dram[2].size = PHYS_SDRAM_3_SIZE;
+#endif
+#if (CONFIG_NR_DRAM_BANKS >= 4)
+	gd->bd->bi_dram[3].start = PHYS_SDRAM_4;
+	gd->bd->bi_dram[3].size = PHYS_SDRAM_4_SIZE;
+#endif
+	return 0;
+}
+
+const struct rmobile_sysinfo sysinfo = {
+	CONFIG_RCAR_BOARD_STRING
+};
+
+static const struct sh_serial_platdata serial_platdata = {
+	.base = SCIF2_BASE,
+	.type = PORT_SCIF,
+	.clk = CONFIG_SH_SCIF_CLK_FREQ,
+	.clk_mode = INT_CLK,
+};
+
+U_BOOT_DEVICE(salvator_x_scif2) = {
+	.name = "serial_sh",
+	.platdata = &serial_platdata,
+};
diff --git a/configs/r8a7795_ulcb_defconfig b/configs/r8a7795_ulcb_defconfig
new file mode 100644
index 0000000..fd5fd55
--- /dev/null
+++ b/configs/r8a7795_ulcb_defconfig
@@ -0,0 +1,21 @@
+CONFIG_ARM=y
+CONFIG_ARCH_RMOBILE=y
+CONFIG_SYS_MALLOC_F_LEN=0x2000
+CONFIG_RCAR_GEN3=y
+CONFIG_TARGET_ULCB=y
+CONFIG_DEFAULT_FDT_FILE="r8a7795-h3ulcb.dtb"
+CONFIG_VERSION_VARIABLE=y
+CONFIG_CMD_BOOTZ=y
+# CONFIG_CMD_IMLS is not set
+CONFIG_CMD_MMC=y
+CONFIG_CMD_USB=y
+CONFIG_CMD_DHCP=y
+CONFIG_CMD_MII=y
+CONFIG_CMD_PING=y
+CONFIG_SH_SDHI=y
+CONFIG_DM_ETH=y
+CONFIG_RENESAS_RAVB=y
+CONFIG_USB=y
+CONFIG_USB_EHCI_HCD=y
+CONFIG_USB_STORAGE=y
+CONFIG_OF_LIBFDT=y
diff --git a/configs/r8a7796_ulcb_defconfig b/configs/r8a7796_ulcb_defconfig
new file mode 100644
index 0000000..96f903b
--- /dev/null
+++ b/configs/r8a7796_ulcb_defconfig
@@ -0,0 +1,22 @@
+CONFIG_ARM=y
+CONFIG_ARCH_RMOBILE=y
+CONFIG_SYS_MALLOC_F_LEN=0x2000
+CONFIG_RCAR_GEN3=y
+CONFIG_R8A7796=y
+CONFIG_TARGET_ULCB=y
+CONFIG_DEFAULT_FDT_FILE="r8a7796-m3ulcb.dtb"
+CONFIG_VERSION_VARIABLE=y
+CONFIG_CMD_BOOTZ=y
+# CONFIG_CMD_IMLS is not set
+CONFIG_CMD_MMC=y
+CONFIG_CMD_USB=y
+CONFIG_CMD_DHCP=y
+CONFIG_CMD_MII=y
+CONFIG_CMD_PING=y
+CONFIG_SH_SDHI=y
+CONFIG_DM_ETH=y
+CONFIG_RENESAS_RAVB=y
+CONFIG_USB=y
+CONFIG_USB_EHCI_HCD=y
+CONFIG_USB_STORAGE=y
+CONFIG_OF_LIBFDT=y
diff --git a/include/configs/ulcb.h b/include/configs/ulcb.h
new file mode 100644
index 0000000..857fc9f
--- /dev/null
+++ b/include/configs/ulcb.h
@@ -0,0 +1,110 @@
+/*
+ * include/configs/ulcb.h
+ *     This file is ULCB board configuration.
+ *
+ * Copyright (C) 2017 Renesas Electronics Corporation
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#ifndef __ULCB_H
+#define __ULCB_H
+
+#undef DEBUG
+
+#define CONFIG_RCAR_BOARD_STRING "ULCB"
+
+#include "rcar-gen3-common.h"
+
+/* M3 ULCB has 2 banks, each with 1 GiB of RAM */
+#if defined(CONFIG_R8A7796)
+#undef PHYS_SDRAM_1_SIZE
+#undef PHYS_SDRAM_2_SIZE
+#define PHYS_SDRAM_1_SIZE		(0x40000000u - DRAM_RSV_SIZE)
+#define PHYS_SDRAM_2_SIZE		0x40000000u
+#endif
+
+/* SCIF */
+#define CONFIG_SCIF_CONSOLE
+#define CONFIG_CONS_SCIF2
+#define CONFIG_CONS_INDEX	2
+#define CONFIG_SH_SCIF_CLK_FREQ        CONFIG_S3D4_CLK_FREQ
+
+/* [A] Hyper Flash */
+/* use to RPC(SPI Multi I/O Bus Controller) */
+
+/* Ethernet RAVB */
+#define CONFIG_NET_MULTI
+#define CONFIG_PHY_MICREL
+#define CONFIG_BITBANGMII
+#define CONFIG_BITBANGMII_MULTI
+
+/* Board Clock */
+/* XTAL_CLK : 33.33MHz */
+#define RCAR_XTAL_CLK		33333333u
+#define CONFIG_SYS_CLK_FREQ	RCAR_XTAL_CLK
+/* ch0to2 CPclk, ch3to11 S3D2_PEREclk, ch12to14 S3D2_RTclk */
+/* CPclk 16.66MHz, S3D2 133.33MHz , S3D4 66.66MHz          */
+#define CONFIG_CP_CLK_FREQ	(CONFIG_SYS_CLK_FREQ / 2)
+#define CONFIG_PLL1_CLK_FREQ	(CONFIG_SYS_CLK_FREQ * 192 / 2)
+#define CONFIG_S3D2_CLK_FREQ	(266666666u/2)
+#define CONFIG_S3D4_CLK_FREQ	(266666666u/4)
+
+/* Generic Timer Definitions (use in assembler source) */
+#define COUNTER_FREQUENCY	0xFE502A	/* 16.66MHz from CPclk */
+
+/* Generic Interrupt Controller Definitions */
+#define CONFIG_GICV2
+#define GICD_BASE	0xF1010000
+#define GICC_BASE	0xF1020000
+
+/* CPLD SPI */
+#define CONFIG_CMD_SPI
+#define CONFIG_SOFT_SPI
+#define SPI_DELAY	udelay(0)
+#define SPI_SDA(val)	ulcb_softspi_sda(val)
+#define SPI_SCL(val)	ulcb_softspi_scl(val)
+#define SPI_READ	ulcb_softspi_read()
+#ifndef	__ASSEMBLY__
+void ulcb_softspi_sda(int);
+void ulcb_softspi_scl(int);
+unsigned char ulcb_softspi_read(void);
+#endif
+
+/* i2c */
+#define CONFIG_SYS_I2C
+#define CONFIG_SYS_I2C_SH
+#define CONFIG_SYS_I2C_SLAVE		0x60
+#define CONFIG_SYS_I2C_SH_NUM_CONTROLLERS	1
+#define CONFIG_SYS_I2C_SH_SPEED0	400000
+#define CONFIG_SH_I2C_DATA_HIGH		4
+#define CONFIG_SH_I2C_DATA_LOW		5
+#define CONFIG_SH_I2C_CLOCK		10000000
+
+#define CONFIG_SYS_I2C_POWERIC_ADDR	0x30
+
+/* USB */
+#ifdef CONFIG_R8A7795
+#define CONFIG_USB_MAX_CONTROLLER_COUNT	3
+#else
+#define CONFIG_USB_MAX_CONTROLLER_COUNT	2
+#endif
+
+/* SDHI */
+#define CONFIG_SH_SDHI_FREQ		200000000
+
+/* Environment in eMMC, at the end of 2nd "boot sector" */
+#define CONFIG_ENV_IS_IN_MMC
+#define CONFIG_ENV_OFFSET		(-CONFIG_ENV_SIZE)
+#define CONFIG_SYS_MMC_ENV_DEV		1
+#define CONFIG_SYS_MMC_ENV_PART		2
+
+/* Module stop status bits */
+/* MFIS, SCIF1 */
+#define CONFIG_SMSTP2_ENA	0x00002040
+/* SCIF2 */
+#define CONFIG_SMSTP3_ENA	0x00000400
+/* INTC-AP, IRQC */
+#define CONFIG_SMSTP4_ENA	0x00000180
+
+#endif /* __ULCB_H */