tree 150b647ed02a9b925602e732fc61fb656c4eb52c
parent 78e32acc1bb9999ad6fcc005ed395ae6f75308a3
author Chris Packham <chris.packham@alliedtelesis.co.nz> 1551388273 +1300
committer Stefan Roese <sr@denx.de> 1552983725 +0100

mv_ddr: ddr3: fix tRAS timimg parameter

Based on the JEDEC standard JESD79-3F. The tRAS timings should include
the highest speed bins at a given frequency. This is similar to commit
683c67b ("mv_ddr: ddr3: fix tfaw timimg parameter") where the wrong
comparison was used in the initial implementation.

Signed-off-by: Chris Packham <chris.packham@alliedtelesis.co.nz>

[https://github.com/MarvellEmbeddedProcessors/mv-ddr-marvell/pull/15]
Signed-off-by: Chris Packham <judge.packham@gmail.com>
Signed-off-by: Stefan Roese <sr@denx.de>