tree dadc24e75dfbce9b3b312cb4f3c6f7779041835f
parent f1edae95955d66a77c7744c690b7fbca87ee14ed
author Icenowy Zheng <icenowy@aosc.io> 1538839412 +0800
committer Jagan Teki <jagan@amarulasolutions.com> 1539153247 +0530

sunxi: fix DRAM gate/reset sequence of H6

Currently the DRAM bus gate and reset is changed at the same time in
H6 DRAM initialization code, which disobeys the user manual's
programming guide.

Fix the sequence by follow the sequence suggested by the user manual
(ungate the bus clock after release the reset signal).

By some experiments it seems to fix the DRAM size detection failure that
rarely happens.

Signed-off-by: Icenowy Zheng <icenowy@aosc.io>
Acked-by: Maxime Ripard <maxime.ripard@bootlin.com>
Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>