commit ac15c64d1872b4174e3b596968930db0eedfa7ba
author Álvaro Fernández Rojas <noltari@gmail.com> Sat Feb 03 10:30:27 2018 +0100
committer Daniel Schwierzeck <daniel.schwierzeck@gmail.com> Wed Mar 21 23:23:13 2018 +0100
tree 0b3bfa236472f6cda4044c4cfd6069d9a5429c3c
parent 3f5512578dcf0ef5529ad8aa8dff83f1c0e69641

MIPS: add support for Broadcom MIPS BCM6362 SoC family

Signed-off-by: Álvaro Fernández Rojas <noltari@gmail.com>

include/dt-bindings/clock/bcm6362-clock.h

diff --git a/include/dt-bindings/clock/bcm6362-clock.h b/include/dt-bindings/clock/bcm6362-clock.h
new file mode 100644
index 0000000..6b11a9f
--- /dev/null
+++ b/include/dt-bindings/clock/bcm6362-clock.h
@@ -0,0 +1,33 @@
+/*
+ * Copyright (C) 2018 Álvaro Fernández Rojas <noltari@gmail.com>
+ *
+ * Derived from linux/arch/mips/include/asm/mach-bcm63xx/bcm63xx_regs.h
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef __DT_BINDINGS_CLOCK_BCM6362_H
+#define __DT_BINDINGS_CLOCK_BCM6362_H
+
+#define BCM6362_CLK_GLESS	0
+#define BCM6362_CLK_ADSL_QPROC	1
+#define BCM6362_CLK_ADSL_AFE	2
+#define BCM6362_CLK_ADSL	3
+#define BCM6362_CLK_MIPS	4
+#define BCM6362_CLK_WLAN_OCP	5
+#define BCM6362_CLK_SWPKT_USB	7
+#define BCM6362_CLK_SWPKT_SAR	8
+#define BCM6362_CLK_SAR		9
+#define BCM6362_CLK_ROBOSW	10
+#define BCM6362_CLK_PCM		11
+#define BCM6362_CLK_USBD	12
+#define BCM6362_CLK_USBH	13
+#define BCM6362_CLK_IPSEC	14
+#define BCM6362_CLK_SPI		15
+#define BCM6362_CLK_HSSPI	16
+#define BCM6362_CLK_PCIE	17
+#define BCM6362_CLK_FAP		18
+#define BCM6362_CLK_PHYMIPS	19
+#define BCM6362_CLK_NAND	20
+
+#endif /* __DT_BINDINGS_CLOCK_BCM6362_H */

include/dt-bindings/power-domain/bcm6362-power-domain.h

diff --git a/include/dt-bindings/power-domain/bcm6362-power-domain.h b/include/dt-bindings/power-domain/bcm6362-power-domain.h
new file mode 100644
index 0000000..3178b00
--- /dev/null
+++ b/include/dt-bindings/power-domain/bcm6362-power-domain.h
@@ -0,0 +1,25 @@
+/*
+ * Copyright (C) 2018 Álvaro Fernández Rojas <noltari@gmail.com>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef __DT_BINDINGS_POWER_DOMAIN_BCM6362_H
+#define __DT_BINDINGS_POWER_DOMAIN_BCM6362_H
+
+#define BCM6362_PWR_SAR		0
+#define BCM6362_PWR_IPSEC	1
+#define BCM6362_PWR_MIPS	2
+#define BCM6362_PWR_DECT	3
+#define BCM6362_PWR_USBH	4
+#define BCM6362_PWR_USBD	5
+#define BCM6362_PWR_ROBOSW	6
+#define BCM6362_PWR_PCM		7
+#define BCM6362_PWR_PERIPH	8
+#define BCM6362_PWR_ADSL_PHY	9
+#define BCM6362_PWR_GMII_PADS	10
+#define BCM6362_PWR_FAP		11
+#define BCM6362_PWR_PCIE	12
+#define BCM6362_PWR_WLAN_PADS	13
+
+#endif /* __DT_BINDINGS_POWER_DOMAIN_BCM6362_H */

include/dt-bindings/reset/bcm6362-reset.h

diff --git a/include/dt-bindings/reset/bcm6362-reset.h b/include/dt-bindings/reset/bcm6362-reset.h
new file mode 100644
index 0000000..ffa46a6
--- /dev/null
+++ b/include/dt-bindings/reset/bcm6362-reset.h
@@ -0,0 +1,28 @@
+/*
+ * Copyright (C) 2018 Álvaro Fernández Rojas <noltari@gmail.com>
+ *
+ * Derived from linux/arch/mips/include/asm/mach-bcm63xx/bcm63xx_regs.h
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef __DT_BINDINGS_RESET_BCM6362_H
+#define __DT_BINDINGS_RESET_BCM6362_H
+
+#define BCM6362_RST_SPI		0
+#define BCM6362_RST_IPSEC	1
+#define BCM6362_RST_EPHY	2
+#define BCM6362_RST_SAR		3
+#define BCM6362_RST_ENETSW	4
+#define BCM6362_RST_USBD	5
+#define BCM6362_RST_USBH	6
+#define BCM6362_RST_PCM		7
+#define BCM6362_RST_PCIE_CORE	8
+#define BCM6362_RST_PCIE	9
+#define BCM6362_RST_PCIE_EXT	10
+#define BCM6362_RST_WLAN_SHIM	11
+#define BCM6362_RST_DDR_PHY	12
+#define BCM6362_RST_FAP		13
+#define BCM6362_RST_WLAN_UBUS	14
+
+#endif /* __DT_BINDINGS_RESET_BCM6362_H */