tree 887c79cae29ea018dadb7373b872cb3a037baab0
parent 8fc9d3af5df9081ee0fed21f2fcaceb1195b2d16
author Wenyou Yang <wenyou.yang@atmel.com> 1493170350 +0800
committer Jaehoon Chung <jh80.chung@samsung.com> 1494840502 +0900

mmc: sdhci: Fix maximum clock for programmable clock mode

In the programmable clock mode, the SDCLK frequency is incorrectly
assigned when the maximum clock has been assigned during probe,
this causes the SDHCI not work well.

In the programmable clock mode, when calculating the SDCLK Frequency
Select, when the maximum clock has been assigned, it is the actual
value, should not be multiplied by host->clk_mul. Otherwise, the
maximum clock is multiplied host->clk_mul by the base clock achieved
from the BASECLKF field of the Capabilities 0 Register.

Signed-off-by: Wenyou Yang <wenyou.yang@atmel.com>