clk: starfive: jh7110: Add security clocks
Add STGCLK_SEC_HCLK and STGCLK_SEC_MISCAHB clocks for JH7110 TRNG
device.
Signed-off-by: Chanho Park <chanho61.park@samsung.com>
Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
diff --git a/drivers/clk/starfive/clk-jh7110.c b/drivers/clk/starfive/clk-jh7110.c
index 31aaf33..a835541 100644
--- a/drivers/clk/starfive/clk-jh7110.c
+++ b/drivers/clk/starfive/clk-jh7110.c
@@ -539,6 +539,16 @@
"pcie1_tl", "stg_axiahb",
OFFSET(JH7110_STGCLK_PCIE1_TL)));
+ /* Security clocks */
+ clk_dm(JH7110_STG_ID_TRANS(JH7110_STGCLK_SEC_HCLK),
+ starfive_clk_gate(priv->reg,
+ "sec_ahb", "stg_axiahb",
+ OFFSET(JH7110_STGCLK_SEC_HCLK)));
+ clk_dm(JH7110_STG_ID_TRANS(JH7110_STGCLK_SEC_MISCAHB),
+ starfive_clk_gate(priv->reg,
+ "sec_misc_ahb", "stg_axiahb",
+ OFFSET(JH7110_STGCLK_SEC_MISCAHB)));
+
return 0;
}