tree 07de292e9c7270f10fe067390c8d251de2d92c39
parent 643e31bbb014d317739599958f0731248a820bdd
author Patrick Delaunay <patrick.delaunay@st.com> 1599216919 +0200
committer Patrick Delaunay <patrick.delaunay@st.com> 1603296740 +0200

stm32mp: limit size of cacheable DDR in pre-reloc stage

In pre-reloc stage, U-Boot marks cacheable the DDR limited by
the new config CONFIG_DDR_CACHEABLE_SIZE.

This patch allows to avoid any speculative access to DDR protected by
firewall and used by OP-TEE; the "no-map" reserved memory
node in DT are assumed after this limit:
STM32_DDR_BASE + DDR_CACHEABLE_SIZE.

Without security, in basic boot, the value is equal to STM32_DDR_SIZE.

Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
Reviewed-by: Patrice Chotard <patrice.chotard@st.com>