commit ab3d15435ce276b30bb85f6c4860ca078a3f6fa3
author Sean Anderson <sean.anderson@seco.com> Tue Nov 23 15:03:47 2021 -0500
committer Jaehoon Chung <jh80.chung@samsung.com> Wed Jan 12 09:56:40 2022 +0900
tree 2d5a8a3d22818a056bc9382716a0d0f3cf781ae4
parent 3e3307909ad94831bf190f2d97241cbf58d9be27

mmc: fsl_esdhc_imx: set sysctl register for clock initialization

[ fsl_esdhc commit 263ddfc3454ead3a988adef39b962479adce2b28 ]

The initial clock setting should be through sysctl register only,
while the mmc_set_clock() will call mmc_set_ios() introduce other
configurations like bus width, mode, and so on.

Signed-off-by: Yangbo Lu <yangbo.lu@nxp.com>
Signed-off-by: Sean Anderson <sean.anderson@seco.com>

drivers/mmc/fsl_esdhc_imx.c

diff --git a/drivers/mmc/fsl_esdhc_imx.c b/drivers/mmc/fsl_esdhc_imx.c
index 25e912b..9299635 100644
--- a/drivers/mmc/fsl_esdhc_imx.c
+++ b/drivers/mmc/fsl_esdhc_imx.c
@@ -1020,7 +1020,7 @@
 		esdhc_setbits32(&regs->sysctl, SYSCTL_HCKEN | SYSCTL_IPGEN);
 
 	/* Set the initial clock speed */
-	mmc_set_clock(mmc, 400000, MMC_CLK_ENABLE);
+	set_sysctl(priv, mmc, 400000);
 
 	/* Disable the BRR and BWR bits in IRQSTAT */
 	esdhc_clrbits32(&regs->irqstaten, IRQSTATEN_BRR | IRQSTATEN_BWR);