Gitiles
Code Review
Sign In
git01.mediatek.com
/
filogic
/
uboot
/
ab3055a42fdea8999f15bf4c5b7e9330a608cb85
/
.
/
board
/
freescale
/
t208xqds
/
t2081_sd_rcw.cfg
blob: daced6796ba1b9c431273ea766193f8809a78100 [
file
] [
log
] [
blame
]
#PBL preamble and RCW header
aa55aa55
010e0100
#Default SerDes Protocol: 0x6C
#Core/DDR: 1533Mhz/2133MT/s
12100017
15000000
00000000
00000000
6c000002
00008000
68104000
c1000000
00000000
00000000
00000000
000307fc
00000000
00000000
00000000
00000004