Add support for multiple PHYs.
diff --git a/cpu/arm920t/at91rm9200/ether.c b/cpu/arm920t/at91rm9200/ether.c
index ca5b7d1..67008d0 100644
--- a/cpu/arm920t/at91rm9200/ether.c
+++ b/cpu/arm920t/at91rm9200/ether.c
@@ -23,6 +23,7 @@
#include <at91rm9200_net.h>
#include <net.h>
+#include <miiphy.h>
/* ----- Ethernet Buffer definitions ----- */
@@ -150,7 +151,6 @@
return TRUE;
}
-
int eth_init (bd_t * bd)
{
int ret;
@@ -265,8 +265,9 @@
{
};
-#if (CONFIG_COMMANDS & CFG_CMD_MII)
-int miiphy_read(unsigned char addr, unsigned char reg, unsigned short * value)
+#if defined(CONFIG_MII) || (CONFIG_COMMANDS & CFG_CMD_MII)
+int at91rm9200_miiphy_read(char *devname, unsigned char addr,
+ unsigned char reg, unsigned short * value)
{
at91rm9200_EmacEnableMDIO (p_mac);
at91rm9200_EmacReadPhy (p_mac, reg, value);
@@ -274,14 +275,24 @@
return 0;
}
-int miiphy_write(unsigned char addr, unsigned char reg, unsigned short value)
+int at91rm9200_miiphy_write(char *devname, unsigned char addr,
+ unsigned char reg, unsigned short value)
{
at91rm9200_EmacEnableMDIO (p_mac);
at91rm9200_EmacWritePhy (p_mac, reg, &value);
at91rm9200_EmacDisableMDIO (p_mac);
return 0;
}
+
+#endif /* defined(CONFIG_MII) || (CONFIG_COMMANDS & CFG_CMD_MII) */
+
+int at91rm9200_miiphy_initialize(bd_t *bis)
+{
+#if defined(CONFIG_MII) || (CONFIG_COMMANDS & CFG_CMD_MII)
+ miiphy_register("at91rm9200phy", at91rm9200_miiphy_read, at91rm9200_miiphy_write);
+#endif
+ return 0;
+}
-#endif /* CONFIG_COMMANDS & CFG_CMD_MII */
#endif /* CONFIG_COMMANDS & CFG_CMD_NET */
diff --git a/cpu/mcf52x2/fec.c b/cpu/mcf52x2/fec.c
index 623a01d..3bf3c8d 100644
--- a/cpu/mcf52x2/fec.c
+++ b/cpu/mcf52x2/fec.c
@@ -519,7 +519,8 @@
* Otherwise they hang in mii_send() !!! Sorry!
*****************************************************************************/
-int miiphy_read (unsigned char addr, unsigned char reg, unsigned short *value)
+int mcf52x2_miiphy_read (char *devname, unsigned char addr,
+ unsigned char reg, unsigned short *value)
{
short rdreg; /* register working value */
@@ -537,7 +538,8 @@
return 0;
}
-int miiphy_write (unsigned char addr, unsigned char reg, unsigned short value)
+int mcf52x2_miiphy_write (char *devname, unsigned char addr,
+ unsigned char reg, unsigned short value)
{
short rdreg; /* register working value */
@@ -554,5 +556,15 @@
return 0;
}
#endif /* (CONFIG_COMMANDS & CFG_CMD_MII) && !defined(CONFIG_BITBANGMII) */
-
#endif /* CFG_CMD_NET, FEC_ENET */
+
+int mcf52x2_miiphy_initialize(bd_t *bis)
+{
+#if (CONFIG_COMMANDS & CFG_CMD_NET) && defined(FEC_ENET)
+#if (CONFIG_COMMANDS & CFG_CMD_MII) && !defined(CONFIG_BITBANGMII)
+ miiphy_register("mcf52x2phy", mcf52x2_miiphy_read, mcf52x2_miiphy_write);
+#endif
+#endif
+ return 0;
+}
+
diff --git a/cpu/mips/au1x00_eth.c b/cpu/mips/au1x00_eth.c
index b7a7652..9ce9b35 100644
--- a/cpu/mips/au1x00_eth.c
+++ b/cpu/mips/au1x00_eth.c
@@ -63,6 +63,10 @@
#include <asm/io.h>
#include <asm/au1x00.h>
+#if (CONFIG_COMMANDS & CFG_CMD_MII)
+#include <miiphy.h>
+#endif
+
/* Ethernet Transmit and Receive Buffers */
#define DBUF_LENGTH 1520
#define PKT_MAXBUF_SIZE 1518
@@ -233,11 +237,17 @@
eth_register(dev);
+#if (CONFIG_COMMANDS & CFG_CMD_MII)
+ miiphy_register(dev->name,
+ au1x00_miiphy_read, au1x00_miiphy_write);
+#endif
+
return 1;
}
#if (CONFIG_COMMANDS & CFG_CMD_MII)
-int miiphy_read(unsigned char addr, unsigned char reg, unsigned short * value)
+int au1x00_miiphy_read(char *devname, unsigned char addr,
+ unsigned char reg, unsigned short * value)
{
volatile u32 *mii_control_reg = (volatile u32*)(ETH0_BASE+MAC_MII_CNTRL);
volatile u32 *mii_data_reg = (volatile u32*)(ETH0_BASE+MAC_MII_DATA);
@@ -269,7 +279,8 @@
return 0;
}
-int miiphy_write(unsigned char addr, unsigned char reg, unsigned short value)
+int au1x00_miiphy_write(char *devname, unsigned char addr,
+ unsigned char reg, unsigned short value)
{
volatile u32 *mii_control_reg = (volatile u32*)(ETH0_BASE+MAC_MII_CNTRL);
volatile u32 *mii_data_reg = (volatile u32*)(ETH0_BASE+MAC_MII_DATA);
diff --git a/cpu/mpc5xxx/fec.c b/cpu/mpc5xxx/fec.c
index eadb7ec..86c8ce6 100644
--- a/cpu/mpc5xxx/fec.c
+++ b/cpu/mpc5xxx/fec.c
@@ -19,9 +19,13 @@
#if (CONFIG_COMMANDS & CFG_CMD_NET) && defined(CONFIG_NET_MULTI) && \
defined(CONFIG_MPC5xxx_FEC)
+#if !(defined(CONFIG_MII) || (CONFIG_COMMANDS & CFG_CMD_MII))
+#error "CONFIG_MII has to be defined!"
+#endif
+
#if (DEBUG & 0x60)
-static void tfifo_print(mpc5xxx_fec_priv *fec);
-static void rfifo_print(mpc5xxx_fec_priv *fec);
+static void tfifo_print(char *devname, mpc5xxx_fec_priv *fec);
+static void rfifo_print(char *devname, mpc5xxx_fec_priv *fec);
#endif /* DEBUG */
#if (DEBUG & 0x40)
@@ -35,9 +39,12 @@
uint8 head[16]; /* MAC header(6 + 6 + 2) + 2(aligned) */
} NBUF;
+int fec5xxx_miiphy_read(char *devname, uint8 phyAddr, uint8 regAddr, uint16 * retVal);
+int fec5xxx_miiphy_write(char *devname, uint8 phyAddr, uint8 regAddr, uint16 data);
+
/********************************************************************/
#if (DEBUG & 0x2)
-static void mpc5xxx_fec_phydump (void)
+static void mpc5xxx_fec_phydump (char *devname)
{
uint16 phyStatus, i;
uint8 phyAddr = CONFIG_PHY_ADDR;
@@ -55,7 +62,7 @@
for (i = 0; i < 32; i++) {
if (reg_mask[i]) {
- miiphy_read(phyAddr, i, &phyStatus);
+ miiphy_read(devname, phyAddr, i, &phyStatus);
printf("Mii reg %d: 0x%04x\n", i, phyStatus);
}
}
@@ -457,7 +464,7 @@
/*
* Reset PHY, then delay 300ns
*/
- miiphy_write(phyAddr, 0x0, 0x8000);
+ miiphy_write(dev->name, phyAddr, 0x0, 0x8000);
udelay(1000);
if (fec->xcv_type == MII10) {
@@ -467,11 +474,11 @@
#if (DEBUG & 0x2)
printf("Forcing 10 Mbps ethernet link... ");
#endif
- miiphy_read(phyAddr, 0x1, &phyStatus);
+ miiphy_read(dev->name, phyAddr, 0x1, &phyStatus);
/*
- miiphy_write(fec, phyAddr, 0x0, 0x0100);
+ miiphy_write(dev->name, fec, phyAddr, 0x0, 0x0100);
*/
- miiphy_write(phyAddr, 0x0, 0x0180);
+ miiphy_write(dev->name, phyAddr, 0x0, 0x0180);
timeout = 20;
do { /* wait for link status to go down */
@@ -482,7 +489,7 @@
#endif
break;
}
- miiphy_read(phyAddr, 0x1, &phyStatus);
+ miiphy_read(dev->name, phyAddr, 0x1, &phyStatus);
#if (DEBUG & 0x2)
printf("=");
#endif
@@ -495,7 +502,7 @@
printf("failed. Link is down.\n");
break;
}
- miiphy_read(phyAddr, 0x1, &phyStatus);
+ miiphy_read(dev->name, phyAddr, 0x1, &phyStatus);
#if (DEBUG & 0x2)
printf("+");
#endif
@@ -508,12 +515,12 @@
/*
* Set the auto-negotiation advertisement register bits
*/
- miiphy_write(phyAddr, 0x4, 0x01e1);
+ miiphy_write(dev->name, phyAddr, 0x4, 0x01e1);
/*
* Set MDIO bit 0.12 = 1(&& bit 0.9=1?) to enable auto-negotiation
*/
- miiphy_write(phyAddr, 0x0, 0x1200);
+ miiphy_write(dev->name, phyAddr, 0x0, 0x1200);
/*
* Wait for AN completion
@@ -529,7 +536,7 @@
return -1;
}
- if (miiphy_read(phyAddr, 0x1, &phyStatus) != 0) {
+ if (miiphy_read(dev->name, phyAddr, 0x1, &phyStatus) != 0) {
#if (DEBUG & 0x2)
printf("PHY auto neg 1 failed 0x%04x...\n", phyStatus);
#endif
@@ -546,7 +553,7 @@
#if (DEBUG & 0x2)
if (fec->xcv_type != SEVENWIRE)
- mpc5xxx_fec_phydump ();
+ mpc5xxx_fec_phydump (dev->name);
#endif
@@ -631,7 +638,7 @@
#if (DEBUG & 0x60)
/********************************************************************/
-static void tfifo_print(mpc5xxx_fec_priv *fec)
+static void tfifo_print(char *devname, mpc5xxx_fec_priv *fec)
{
uint16 phyAddr = CONFIG_PHY_ADDR;
uint16 phyStatus;
@@ -639,7 +646,7 @@
if ((fec->eth->tfifo_lrf_ptr != fec->eth->tfifo_lwf_ptr)
|| (fec->eth->tfifo_rdptr != fec->eth->tfifo_wrptr)) {
- miiphy_read(phyAddr, 0x1, &phyStatus);
+ miiphy_read(devname, phyAddr, 0x1, &phyStatus);
printf("\nphyStatus: 0x%04x\n", phyStatus);
printf("ecntrl: 0x%08x\n", fec->eth->ecntrl);
printf("ievent: 0x%08x\n", fec->eth->ievent);
@@ -655,7 +662,7 @@
}
}
-static void rfifo_print(mpc5xxx_fec_priv *fec)
+static void rfifo_print(char *devname, mpc5xxx_fec_priv *fec)
{
uint16 phyAddr = CONFIG_PHY_ADDR;
uint16 phyStatus;
@@ -663,7 +670,7 @@
if ((fec->eth->rfifo_lrf_ptr != fec->eth->rfifo_lwf_ptr)
|| (fec->eth->rfifo_rdptr != fec->eth->rfifo_wrptr)) {
- miiphy_read(phyAddr, 0x1, &phyStatus);
+ miiphy_read(devname, phyAddr, 0x1, &phyStatus);
printf("\nphyStatus: 0x%04x\n", phyStatus);
printf("ecntrl: 0x%08x\n", fec->eth->ecntrl);
printf("ievent: 0x%08x\n", fec->eth->ievent);
@@ -694,7 +701,7 @@
#if (DEBUG & 0x20)
printf("tbd status: 0x%04x\n", fec->tbdBase[0].status);
- tfifo_print(fec);
+ tfifo_print(dev->name, fec);
#endif
/*
@@ -737,7 +744,7 @@
*/
if (fec->xcv_type != SEVENWIRE) {
uint16 phyStatus;
- miiphy_read(0, 0x1, &phyStatus);
+ miiphy_read(dev->name, 0, 0x1, &phyStatus);
}
/*
@@ -745,11 +752,11 @@
*/
#if (DEBUG & 0x20)
- tfifo_print(fec);
+ tfifo_print(dev->name, fec);
#endif
SDMA_TASK_ENABLE (FEC_XMIT_TASK_NO);
#if (DEBUG & 0x20)
- tfifo_print(fec);
+ tfifo_print(dev->name, fec);
#endif
#if (DEBUG & 0x8)
printf( "+" );
@@ -896,6 +903,11 @@
sprintf(dev->name, "FEC ETHERNET");
eth_register(dev);
+#if defined(CONFIG_MII) || (CONFIG_COMMANDS & CFG_CMD_MII)
+ miiphy_register (dev->name,
+ fec5xxx_miiphy_read, fec5xxx_miiphy_write);
+#endif
+
/*
* Try to set the mac address now. The fec mac address is
* a garbage after reset. When not using fec for booting
@@ -912,12 +924,13 @@
}
mpc5xxx_fec_init_phy(dev, bis);
+
return 1;
}
/* MII-interface related functions */
/********************************************************************/
-int miiphy_read(uint8 phyAddr, uint8 regAddr, uint16 * retVal)
+int fec5xxx_miiphy_read(char *devname, uint8 phyAddr, uint8 regAddr, uint16 * retVal)
{
ethernet_regs *eth = (ethernet_regs *)MPC5XXX_FEC;
uint32 reg; /* convenient holder for the PHY register */
@@ -959,7 +972,7 @@
}
/********************************************************************/
-int miiphy_write(uint8 phyAddr, uint8 regAddr, uint16 data)
+int fec5xxx_miiphy_write(char *devname, uint8 phyAddr, uint8 regAddr, uint16 data)
{
ethernet_regs *eth = (ethernet_regs *)MPC5XXX_FEC;
uint32 reg; /* convenient holder for the PHY register */
diff --git a/cpu/mpc8220/fec.c b/cpu/mpc8220/fec.c
index d5cd22e..1201e79 100644
--- a/cpu/mpc8220/fec.c
+++ b/cpu/mpc8220/fec.c
@@ -18,11 +18,13 @@
#if (CONFIG_COMMANDS & CFG_CMD_NET) && defined(CONFIG_NET_MULTI) && \
defined(CONFIG_MPC8220_FEC)
-/*#if (CONFIG_COMMANDS & CFG_CMD_NET)*/
+#if !(defined(CONFIG_MII) || (CONFIG_COMMANDS & CFG_CMD_MII))
+#error "CONFIG_MII has to be defined!"
+#endif
#ifdef DEBUG
-static void tfifo_print (mpc8220_fec_priv * fec);
-static void rfifo_print (mpc8220_fec_priv * fec);
+static void tfifo_print (char *devname, mpc8220_fec_priv * fec);
+static void rfifo_print (char *devname, mpc8220_fec_priv * fec);
#endif /* DEBUG */
#ifdef DEBUG
@@ -36,9 +38,12 @@
u8 head[16]; /* MAC header(6 + 6 + 2) + 2(aligned) */
} NBUF;
+int fec8220_miiphy_read (char *devname, u8 phyAddr, u8 regAddr, u16 * retVal);
+int fec8220_miiphy_write (char *devname, u8 phyAddr, u8 regAddr, u16 data);
+
/********************************************************************/
#ifdef DEBUG
-static void mpc8220_fec_phydump (void)
+static void mpc8220_fec_phydump (char *devname)
{
u16 phyStatus, i;
u8 phyAddr = CONFIG_PHY_ADDR;
@@ -56,7 +61,7 @@
for (i = 0; i < 32; i++) {
if (reg_mask[i]) {
- miiphy_read (phyAddr, i, &phyStatus);
+ miiphy_read (devname, phyAddr, i, &phyStatus);
printf ("Mii reg %d: 0x%04x\n", i, phyStatus);
}
}
@@ -400,7 +405,7 @@
/*
* Reset PHY, then delay 300ns
*/
- miiphy_write (phyAddr, 0x0, 0x8000);
+ miiphy_write (dev->name, phyAddr, 0x0, 0x8000);
udelay (1000);
if (fec->xcv_type == MII10) {
@@ -410,11 +415,11 @@
#ifdef DEBUG
printf ("Forcing 10 Mbps ethernet link... ");
#endif
- miiphy_read (phyAddr, 0x1, &phyStatus);
+ miiphy_read (dev->name, phyAddr, 0x1, &phyStatus);
/*
miiphy_write(fec, phyAddr, 0x0, 0x0100);
*/
- miiphy_write (phyAddr, 0x0, 0x0180);
+ miiphy_write (dev->name, phyAddr, 0x0, 0x0180);
timeout = 20;
do { /* wait for link status to go down */
@@ -425,7 +430,7 @@
#endif
break;
}
- miiphy_read (phyAddr, 0x1, &phyStatus);
+ miiphy_read (dev->name, phyAddr, 0x1, &phyStatus);
#ifdef DEBUG
printf ("=");
#endif
@@ -438,7 +443,7 @@
printf ("failed. Link is down.\n");
break;
}
- miiphy_read (phyAddr, 0x1, &phyStatus);
+ miiphy_read (dev->name, phyAddr, 0x1, &phyStatus);
#ifdef DEBUG
printf ("+");
#endif
@@ -451,12 +456,12 @@
/*
* Set the auto-negotiation advertisement register bits
*/
- miiphy_write (phyAddr, 0x4, 0x01e1);
+ miiphy_write (dev->name, phyAddr, 0x4, 0x01e1);
/*
* Set MDIO bit 0.12 = 1(&& bit 0.9=1?) to enable auto-negotiation
*/
- miiphy_write (phyAddr, 0x0, 0x1200);
+ miiphy_write (dev->name, phyAddr, 0x0, 0x1200);
/*
* Wait for AN completion
@@ -472,7 +477,7 @@
return -1;
}
- if (miiphy_read (phyAddr, 0x1, &phyStatus) !=
+ if (miiphy_read (dev->name, phyAddr, 0x1, &phyStatus) !=
0) {
#ifdef DEBUG
printf ("PHY auto neg 1 failed 0x%04x...\n", phyStatus);
@@ -495,7 +500,7 @@
#ifdef DEBUG
if (fec->xcv_type != SEVENWIRE)
- mpc8220_fec_phydump ();
+ mpc8220_fec_phydump (dev->name);
#endif
/*
@@ -518,7 +523,7 @@
#ifdef DEBUG
if (fec->xcv_type != SEVENWIRE)
- mpc8220_fec_phydump ();
+ mpc8220_fec_phydump (dev->name);
#endif
/*
@@ -573,7 +578,7 @@
#ifdef DEBUG
/********************************************************************/
-static void tfifo_print (mpc8220_fec_priv * fec)
+static void tfifo_print (char *devname, mpc8220_fec_priv * fec)
{
u16 phyAddr = CONFIG_PHY_ADDR;
u16 phyStatus;
@@ -581,7 +586,7 @@
if ((fec->eth->tfifo_lrf_ptr != fec->eth->tfifo_lwf_ptr)
|| (fec->eth->tfifo_rdptr != fec->eth->tfifo_wrptr)) {
- miiphy_read (phyAddr, 0x1, &phyStatus);
+ miiphy_read (devname, phyAddr, 0x1, &phyStatus);
printf ("\nphyStatus: 0x%04x\n", phyStatus);
printf ("ecntrl: 0x%08x\n", fec->eth->ecntrl);
printf ("ievent: 0x%08x\n", fec->eth->ievent);
@@ -597,7 +602,7 @@
}
}
-static void rfifo_print (mpc8220_fec_priv * fec)
+static void rfifo_print (char *devname, mpc8220_fec_priv * fec)
{
u16 phyAddr = CONFIG_PHY_ADDR;
u16 phyStatus;
@@ -605,7 +610,7 @@
if ((fec->eth->rfifo_lrf_ptr != fec->eth->rfifo_lwf_ptr)
|| (fec->eth->rfifo_rdptr != fec->eth->rfifo_wrptr)) {
- miiphy_read (phyAddr, 0x1, &phyStatus);
+ miiphy_read (devname, phyAddr, 0x1, &phyStatus);
printf ("\nphyStatus: 0x%04x\n", phyStatus);
printf ("ecntrl: 0x%08x\n", fec->eth->ecntrl);
printf ("ievent: 0x%08x\n", fec->eth->ievent);
@@ -636,7 +641,7 @@
#ifdef DEBUG
printf ("tbd status: 0x%04x\n", fec->tbdBase[0].status);
- tfifo_print (fec);
+ tfifo_print (dev->name, fec);
#endif
/*
@@ -680,7 +685,7 @@
if (fec->xcv_type != SEVENWIRE) {
u16 phyStatus;
- miiphy_read (0, 0x1, &phyStatus);
+ miiphy_read (dev->name, 0, 0x1, &phyStatus);
}
/*
@@ -688,13 +693,13 @@
*/
#ifdef DEBUG
- tfifo_print (fec);
+ tfifo_print (dev->name, fec);
#endif
DMA_TASK_ENABLE (FEC_XMIT_TASK_NO);
#ifdef DEBUG
- tfifo_print (fec);
+ tfifo_print (dev->name, fec);
#endif
#ifdef DEBUG
@@ -842,6 +847,11 @@
sprintf (dev->name, "FEC ETHERNET");
eth_register (dev);
+#if defined(CONFIG_MII) || (CONFIG_COMMANDS & CFG_CMD_MII)
+ miiphy_register (dev->name,
+ fec8220_miiphy_read, fec8220_miiphy_write);
+#endif
+
/*
* Try to set the mac address now. The fec mac address is
* a garbage after reset. When not using fec for booting
@@ -875,7 +885,7 @@
/* MII-interface related functions */
/********************************************************************/
-int miiphy_read (u8 phyAddr, u8 regAddr, u16 * retVal)
+int fec8220_miiphy_read (char *devname, u8 phyAddr, u8 regAddr, u16 * retVal)
{
ethernet_regs *eth = (ethernet_regs *) MMAP_FEC1;
u32 reg; /* convenient holder for the PHY register */
@@ -919,7 +929,7 @@
}
/********************************************************************/
-int miiphy_write (u8 phyAddr, u8 regAddr, u16 data)
+int fec8220_miiphy_write (char *devname, u8 phyAddr, u8 regAddr, u16 data)
{
ethernet_regs *eth = (ethernet_regs *) MMAP_FEC1;
u32 reg; /* convenient holder for the PHY register */
diff --git a/cpu/mpc8260/ether_fcc.c b/cpu/mpc8260/ether_fcc.c
index 0393afa..ed3515f 100644
--- a/cpu/mpc8260/ether_fcc.c
+++ b/cpu/mpc8260/ether_fcc.c
@@ -47,6 +47,10 @@
#include <config.h>
#include <net.h>
+#if defined(CONFIG_MII) || (CONFIG_COMMANDS & CFG_CMD_MII)
+#include <miiphy.h>
+#endif
+
#if defined(CONFIG_ETHER_ON_FCC) && (CONFIG_COMMANDS & CFG_CMD_NET) && \
defined(CONFIG_NET_MULTI)
@@ -386,6 +390,12 @@
dev->recv = fec_recv;
eth_register(dev);
+
+#if (defined(CONFIG_MII) || (CONFIG_COMMANDS & CFG_CMD_MII)) \
+ && defined(CONFIG_BITBANGMII)
+ miiphy_register(dev->name,
+ bb_miiphy_read, bb_miiphy_write);
+#endif
}
return 1;
diff --git a/cpu/mpc85xx/ether_fcc.c b/cpu/mpc85xx/ether_fcc.c
index cbbb3a4..7edb294 100644
--- a/cpu/mpc85xx/ether_fcc.c
+++ b/cpu/mpc85xx/ether_fcc.c
@@ -48,6 +48,10 @@
#include <config.h>
#include <net.h>
+#if defined(CONFIG_MII) || (CONFIG_COMMANDS & CFG_CMD_MII)
+#include <miiphy.h>
+#endif
+
#if defined(CONFIG_CPM2)
#if defined(CONFIG_ETHER_ON_FCC) && (CONFIG_COMMANDS & CFG_CMD_NET) && \
@@ -451,6 +455,12 @@
dev->recv = fec_recv;
eth_register(dev);
+
+#if (defined(CONFIG_MII) || (CONFIG_COMMANDS & CFG_CMD_MII)) \
+ && defined(CONFIG_BITBANGMII)
+ miiphy_register(dev->name,
+ bb_miiphy_read, bb_miiphy_write);
+#endif
}
return 1;
diff --git a/cpu/mpc8xx/fec.c b/cpu/mpc8xx/fec.c
index f8f56a3..d2f5d88 100644
--- a/cpu/mpc8xx/fec.c
+++ b/cpu/mpc8xx/fec.c
@@ -46,6 +46,11 @@
#if defined(WANT_MII)
#include <miiphy.h>
+
+#if !(defined(CONFIG_MII) || (CONFIG_COMMANDS & CFG_CMD_MII))
+#error "CONFIG_MII has to be defined!"
+#endif
+
#endif
#if defined(CONFIG_RMII) && !defined(WANT_MII)
@@ -56,6 +61,11 @@
static int mii_discover_phy(struct eth_device *dev);
#endif
+int fec8xx_miiphy_read(char *devname, unsigned char addr,
+ unsigned char reg, unsigned short *value);
+int fec8xx_miiphy_write(char *devname, unsigned char addr,
+ unsigned char reg, unsigned short value);
+
static struct ether_fcc_info_s
{
int ether_index;
@@ -169,6 +179,11 @@
dev->recv = fec_recv;
eth_register(dev);
+
+#if defined(CONFIG_MII) || (CONFIG_COMMANDS & CFG_CMD_MII)
+ miiphy_register(dev->name,
+ fec8xx_miiphy_read, fec8xx_miiphy_write);
+#endif
}
return 1;
}
@@ -712,7 +727,7 @@
/*
* adapt the RMII speed to the speed of the phy
*/
- if (miiphy_speed (efis->actual_phy_addr) == _100BASET) {
+ if (miiphy_speed (dev->name, efis->actual_phy_addr) == _100BASET) {
fec_100Mbps (dev);
} else {
fec_10Mbps (dev);
@@ -723,7 +738,7 @@
/*
* adapt to the half/full speed settings
*/
- if (miiphy_duplex (efis->actual_phy_addr) == FULL) {
+ if (miiphy_duplex (dev->name, efis->actual_phy_addr) == FULL) {
fec_full_duplex (dev);
} else {
fec_half_duplex (dev);
@@ -969,7 +984,8 @@
* Otherwise they hang in mii_send() !!! Sorry!
*****************************************************************************/
-int miiphy_read(unsigned char addr, unsigned char reg, unsigned short *value)
+int fec8xx_miiphy_read(char *devname, unsigned char addr,
+ unsigned char reg, unsigned short *value)
{
short rdreg; /* register working value */
@@ -985,7 +1001,8 @@
return 0;
}
-int miiphy_write(unsigned char addr, unsigned char reg, unsigned short value)
+int fec8xx_miiphy_write(char *devname, unsigned char addr,
+ unsigned char reg, unsigned short value)
{
short rdreg; /* register working value */
#ifdef MII_DEBUG
diff --git a/cpu/ppc4xx/4xx_enet.c b/cpu/ppc4xx/4xx_enet.c
index d3f1de4..2d2918e 100644
--- a/cpu/ppc4xx/4xx_enet.c
+++ b/cpu/ppc4xx/4xx_enet.c
@@ -142,7 +142,6 @@
struct eth_device *emac0_dev = NULL;
#endif
-
/*-----------------------------------------------------------------------------+
* Prototypes and externals.
*-----------------------------------------------------------------------------*/
@@ -154,6 +153,11 @@
unsigned long mal_errr);
static void emac_err (struct eth_device *dev, unsigned long isr);
+extern int phy_setup_aneg (char *devname, unsigned char addr);
+extern int emac4xx_miiphy_read (char *devname, unsigned char addr,
+ unsigned char reg, unsigned short *value);
+extern int emac4xx_miiphy_write (char *devname, unsigned char addr,
+ unsigned char reg, unsigned short value);
/*-----------------------------------------------------------------------------+
| ppc_4xx_eth_halt
@@ -191,9 +195,6 @@
return;
}
-extern int phy_setup_aneg (unsigned char addr);
-extern int miiphy_reset (unsigned char addr);
-
#if defined (CONFIG_440GX)
int ppc_4xx_eth_setup_bridge(int devnum, bd_t * bis)
{
@@ -447,7 +448,7 @@
* otherwise, just check the speeds & feeds
*/
if (hw_p->first_init == 0) {
- miiphy_reset (reg);
+ miiphy_reset (dev->name, reg);
#if defined(CONFIG_440GX)
#if defined(CONFIG_CIS8201_PHY)
@@ -457,9 +458,9 @@
*/
if ( ((devnum == 2) || (devnum ==3)) && (4 == ethgroup) ) {
#if defined(CONFIG_CIS8201_SHORT_ETCH)
- miiphy_write (reg, 23, 0x1300);
+ miiphy_write (dev->name, reg, 23, 0x1300);
#else
- miiphy_write (reg, 23, 0x1000);
+ miiphy_write (dev->name, reg, 23, 0x1000);
#endif
/*
* Vitesse VSC8201/Cicada CIS8201 errata:
@@ -467,26 +468,26 @@
* This work around (provided by Vitesse) changes
* the default timer convergence from 8ms to 12ms
*/
- miiphy_write (reg, 0x1f, 0x2a30);
- miiphy_write (reg, 0x08, 0x0200);
- miiphy_write (reg, 0x1f, 0x52b5);
- miiphy_write (reg, 0x02, 0x0004);
- miiphy_write (reg, 0x01, 0x0671);
- miiphy_write (reg, 0x00, 0x8fae);
- miiphy_write (reg, 0x1f, 0x2a30);
- miiphy_write (reg, 0x08, 0x0000);
- miiphy_write (reg, 0x1f, 0x0000);
+ miiphy_write (dev->name, reg, 0x1f, 0x2a30);
+ miiphy_write (dev->name, reg, 0x08, 0x0200);
+ miiphy_write (dev->name, reg, 0x1f, 0x52b5);
+ miiphy_write (dev->name, reg, 0x02, 0x0004);
+ miiphy_write (dev->name, reg, 0x01, 0x0671);
+ miiphy_write (dev->name, reg, 0x00, 0x8fae);
+ miiphy_write (dev->name, reg, 0x1f, 0x2a30);
+ miiphy_write (dev->name, reg, 0x08, 0x0000);
+ miiphy_write (dev->name, reg, 0x1f, 0x0000);
/* end Vitesse/Cicada errata */
}
#endif
#endif
/* Start/Restart autonegotiation */
- phy_setup_aneg (reg);
+ phy_setup_aneg (dev->name, reg);
udelay (1000);
}
#endif /* defined(CONFIG_PHY_RESET) */
- miiphy_read (reg, PHY_BMSR, ®_short);
+ miiphy_read (dev->name, reg, PHY_BMSR, ®_short);
/*
* Wait if PHY is capable of autonegotiation and autonegotiation is not complete
@@ -508,7 +509,7 @@
putc ('.');
}
udelay (1000); /* 1 ms */
- miiphy_read (reg, PHY_BMSR, ®_short);
+ miiphy_read (dev->name, reg, PHY_BMSR, ®_short);
}
puts (" done\n");
@@ -516,8 +517,8 @@
}
#endif /* #ifndef CONFIG_CS8952_PHY */
- speed = miiphy_speed (reg);
- duplex = miiphy_duplex (reg);
+ speed = miiphy_speed (dev->name, reg);
+ duplex = miiphy_duplex (dev->name, reg);
if (hw_p->print_speed) {
hw_p->print_speed = 0;
@@ -1470,6 +1471,10 @@
#else
emac0_dev = dev;
#endif
+#if defined(CONFIG_MII) || (CONFIG_COMMANDS & CFG_CMD_MII)
+ miiphy_register (dev->name,
+ emac4xx_miiphy_read, emac4xx_miiphy_write);
+#endif
} /* end for each supported device */
return (1);
@@ -1505,6 +1510,16 @@
{
return (ppc_4xx_eth_rx(emac0_dev));
}
+
+int emac4xx_miiphy_initialize (bd_t * bis)
+{
+#if defined(CONFIG_MII) || (CONFIG_COMMANDS & CFG_CMD_MII)
+ miiphy_register ("ppc_4xx_eth0",
+ emac4xx_miiphy_read, emac4xx_miiphy_write);
+#endif
+
+ return 0;
+}
#endif /* !defined(CONFIG_NET_MULTI) */
#endif /* #if (CONFIG_COMMANDS & CFG_CMD_NET) */
diff --git a/cpu/ppc4xx/miiphy.c b/cpu/ppc4xx/miiphy.c
index 24f9154..f319eb8 100644
--- a/cpu/ppc4xx/miiphy.c
+++ b/cpu/ppc4xx/miiphy.c
@@ -55,14 +55,14 @@
/* Dump out to the screen PHY regs */
/***********************************************************/
-void miiphy_dump (unsigned char addr)
+void miiphy_dump (char *devname, unsigned char addr)
{
unsigned long i;
unsigned short data;
for (i = 0; i < 0x1A; i++) {
- if (miiphy_read (addr, i, &data)) {
+ if (miiphy_read (devname, addr, i, &data)) {
printf ("read error for reg %lx\n", i);
return;
}
@@ -79,21 +79,21 @@
/***********************************************************/
/* (Re)start autonegotiation */
/***********************************************************/
-int phy_setup_aneg (unsigned char addr)
+int phy_setup_aneg (char *devname, unsigned char addr)
{
unsigned short ctl, adv;
/* Setup standard advertise */
- miiphy_read (addr, PHY_ANAR, &adv);
+ miiphy_read (devname, addr, PHY_ANAR, &adv);
adv |= (PHY_ANLPAR_ACK | PHY_ANLPAR_RF | PHY_ANLPAR_T4 |
PHY_ANLPAR_TXFD | PHY_ANLPAR_TX | PHY_ANLPAR_10FD |
PHY_ANLPAR_10);
- miiphy_write (addr, PHY_ANAR, adv);
+ miiphy_write (devname, addr, PHY_ANAR, adv);
/* Start/Restart aneg */
- miiphy_read (addr, PHY_BMCR, &ctl);
+ miiphy_read (devname, addr, PHY_BMCR, &ctl);
ctl |= (PHY_BMCR_AUTON | PHY_BMCR_RST_NEG);
- miiphy_write (addr, PHY_BMCR, ctl);
+ miiphy_write (devname, addr, PHY_BMCR, ctl);
return 0;
}
@@ -142,7 +142,8 @@
}
-int miiphy_read (unsigned char addr, unsigned char reg, unsigned short *value)
+int emac4xx_miiphy_read (char *devname, unsigned char addr,
+ unsigned char reg, unsigned short *value)
{
unsigned long sta_reg; /* STA scratch area */
unsigned long i;
@@ -207,7 +208,8 @@
/* write a phy reg and return the value with a rc */
/***********************************************************/
-int miiphy_write (unsigned char addr, unsigned char reg, unsigned short value)
+int emac4xx_miiphy_write (char *devname, unsigned char addr,
+ unsigned char reg, unsigned short value)
{
unsigned long sta_reg; /* STA scratch area */
unsigned long i;