Merge tag 'video-for-v2021.04' of https://source.denx.de/u-boot/custodians/u-boot-video
- drop unprintable characters from video font header
diff --git a/.azure-pipelines.yml b/.azure-pipelines.yml
index a627942..506e0c0 100644
--- a/.azure-pipelines.yml
+++ b/.azure-pipelines.yml
@@ -148,7 +148,7 @@
export UBOOT_TRAVIS_BUILD_DIR=/tmp/sandbox_spl
export PYTHONPATH=${UBOOT_TRAVIS_BUILD_DIR}/scripts/dtc/pylibfdt
export PATH=${UBOOT_TRAVIS_BUILD_DIR}/scripts/dtc:${PATH}
- ./tools/buildman/buildman -o ${UBOOT_TRAVIS_BUILD_DIR} -w sandbox_spl
+ ./tools/buildman/buildman -T0 -o ${UBOOT_TRAVIS_BUILD_DIR} -w sandbox_spl
./tools/binman/binman --toolpath ${UBOOT_TRAVIS_BUILD_DIR}/tools test
./tools/buildman/buildman -t
./tools/dtoc/dtoc -t
@@ -295,7 +295,7 @@
cat << "EOF" >> test.sh
# the below corresponds to .gitlab-ci.yml "before_script"
cd ${WORK_DIR}
- git clone --depth=1 git://github.com/swarren/uboot-test-hooks.git /tmp/uboot-test-hooks
+ git clone --depth=1 https://source.denx.de/u-boot/u-boot-test-hooks /tmp/uboot-test-hooks
ln -s travis-ci /tmp/uboot-test-hooks/bin/`hostname`
ln -s travis-ci /tmp/uboot-test-hooks/py/`hostname`
grub-mkimage --prefix=\"\" -o ~/grub_x86.efi -O i386-efi normal echo lsefimmap lsefi lsefisystab efinet tftp minicmd
diff --git a/.gitlab-ci.yml b/.gitlab-ci.yml
index 2cdcd86..4fb9aa1 100644
--- a/.gitlab-ci.yml
+++ b/.gitlab-ci.yml
@@ -1,7 +1,7 @@
# SPDX-License-Identifier: GPL-2.0+
# Grab our configured image. The source for this is found at:
-# https://gitlab.denx.de/u-boot/gitlab-ci-runner
+# https://source.denx.de/u-boot/gitlab-ci-runner
image: trini/u-boot-gitlab-ci-runner:bionic-20200807-02Sep2020
# We run some tests in different order, to catch some failures quicker.
@@ -15,7 +15,7 @@
stage: test.py
before_script:
# Clone uboot-test-hooks
- - git clone --depth=1 git://github.com/swarren/uboot-test-hooks.git /tmp/uboot-test-hooks
+ - git clone --depth=1 https://source.denx.de/u-boot/u-boot-test-hooks /tmp/uboot-test-hooks
- ln -s travis-ci /tmp/uboot-test-hooks/bin/`hostname`
- ln -s travis-ci /tmp/uboot-test-hooks/py/`hostname`
- grub-mkimage --prefix="" -o ~/grub_x86.efi -O i386-efi normal echo lsefimmap lsefi lsefisystab efinet tftp minicmd
@@ -168,7 +168,7 @@
export UBOOT_TRAVIS_BUILD_DIR=/tmp/sandbox_spl;
export PYTHONPATH="${UBOOT_TRAVIS_BUILD_DIR}/scripts/dtc/pylibfdt";
export PATH="${UBOOT_TRAVIS_BUILD_DIR}/scripts/dtc:${PATH}";
- ./tools/buildman/buildman -o ${UBOOT_TRAVIS_BUILD_DIR} -w sandbox_spl;
+ ./tools/buildman/buildman -T0 -o ${UBOOT_TRAVIS_BUILD_DIR} -w sandbox_spl;
./tools/binman/binman --toolpath ${UBOOT_TRAVIS_BUILD_DIR}/tools test;
./tools/buildman/buildman -t;
./tools/dtoc/dtoc -t;
diff --git a/MAINTAINERS b/MAINTAINERS
index b82b7ad..c6dd9bf 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -75,7 +75,7 @@
M: Eugeniy Paltsev <Eugeniy.Paltsev@synopsys.com>
S: Maintained
L: uboot-snps-arc@synopsys.com
-T: git https://gitlab.denx.de/u-boot/custodians/u-boot-arc.git
+T: git https://source.denx.de/u-boot/custodians/u-boot-arc.git
F: arch/arc/
F: board/synopsys/
@@ -111,7 +111,7 @@
ARM
M: Tom Rini <trini@konsulko.com>
S: Maintained
-T: git https://gitlab.denx.de/u-boot/custodians/u-boot-arm.git
+T: git https://source.denx.de/u-boot/custodians/u-boot-arm.git
F: arch/arm/
F: cmd/arm/
@@ -120,7 +120,7 @@
M: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
M: Ley Foon Tan <ley.foon.tan@intel.com>
S: Maintainted
-T: git https://gitlab.denx.de/u-boot/custodians/u-boot-socfpga.git
+T: git https://source.denx.de/u-boot/custodians/u-boot-socfpga.git
F: arch/arm/mach-socfpga/
F: drivers/sysreset/sysreset_socfpga*
@@ -128,7 +128,7 @@
M: Neil Armstrong <narmstrong@baylibre.com>
S: Maintained
L: u-boot-amlogic@groups.io
-T: git https://gitlab.denx.de/u-boot/custodians/u-boot-amlogic.git
+T: git https://source.denx.de/u-boot/custodians/u-boot-amlogic.git
F: arch/arm/mach-meson/
F: arch/arm/include/asm/arch-meson/
F: drivers/clk/meson/
@@ -160,7 +160,7 @@
F: drivers/pinctrl/aspeed/
N: aspeed
-ARM BROADCOM BCM283X
+ARM BROADCOM BCM283X / BCM27XX
M: Matthias Brugger <mbrugger@suse.com>
S: Maintained
F: arch/arm/dts/bcm283*
@@ -175,6 +175,8 @@
F: include/dm/platform_data/serial_bcm283x_mu.h
F: include/dt-bindings/pinctrl/bcm2835.h
F: drivers/pinctrl/broadcom/
+F: configs/rpi_*
+T: git https://source.denx.de/u-boot/custodians/u-boot-arm.git
ARM BROADCOM BCMSTB
M: Thomas Fitzsimmons <fitzsim@fitzsim.org>
@@ -218,7 +220,7 @@
M: Fabio Estevam <festevam@gmail.com>
R: NXP i.MX U-Boot Team <uboot-imx@nxp.com>
S: Maintained
-T: git https://gitlab.denx.de/u-boot/custodians/u-boot-imx.git
+T: git https://source.denx.de/u-boot/custodians/u-boot-imx.git
F: arch/arm/cpu/arm1136/mx*/
F: arch/arm/cpu/arm926ejs/mx*/
F: arch/arm/cpu/armv7/vf610/
@@ -255,7 +257,7 @@
ARM MARVELL KIRKWOOD ARMADA-XP ARMADA-38X ARMADA-37XX ARMADA-7K/8K
M: Stefan Roese <sr@denx.de>
S: Maintained
-T: git https://gitlab.denx.de/u-boot/custodians/u-boot-marvell.git
+T: git https://source.denx.de/u-boot/custodians/u-boot-marvell.git
F: arch/arm/mach-kirkwood/
F: arch/arm/mach-mvebu/
F: drivers/ata/ahci_mvebu.c
@@ -269,7 +271,7 @@
ARM MARVELL PXA
M: Marek Vasut <marex@denx.de>
S: Maintained
-T: git https://gitlab.denx.de/u-boot/custodians/u-boot-pxa.git
+T: git https://source.denx.de/u-boot/custodians/u-boot-pxa.git
F: arch/arm/cpu/pxa/
F: arch/arm/include/asm/arch-pxa/
@@ -305,7 +307,7 @@
ARM MICROCHIP/ATMEL AT91
M: Eugen Hristev <eugen.hristev@microchip.com>
S: Maintained
-T: git https://gitlab.denx.de/u-boot/custodians/u-boot-atmel.git
+T: git https://source.denx.de/u-boot/custodians/u-boot-atmel.git
F: arch/arm/mach-at91/
F: board/atmel/
F: drivers/cpu/at91_cpu.c
@@ -345,7 +347,7 @@
M: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
M: Marek Vasut <marek.vasut+renesas@gmail.com>
S: Maintained
-T: git https://gitlab.denx.de/u-boot/custodians/u-boot-sh.git
+T: git https://source.denx.de/u-boot/custodians/u-boot-sh.git
F: arch/arm/mach-rmobile/
ARM ROCKCHIP
@@ -353,7 +355,7 @@
M: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
M: Kever Yang <kever.yang@rock-chips.com>
S: Maintained
-T: git https://gitlab.denx.de/u-boot/custodians/u-boot-rockchip.git
+T: git https://source.denx.de/u-boot/custodians/u-boot-rockchip.git
F: arch/arm/include/asm/arch-rockchip/
F: arch/arm/mach-rockchip/
F: board/rockchip/
@@ -375,7 +377,7 @@
ARM SAMSUNG
M: Minkyu Kang <mk7.kang@samsung.com>
S: Maintained
-T: git https://gitlab.denx.de/u-boot/custodians/u-boot-samsung.git
+T: git https://source.denx.de/u-boot/custodians/u-boot-samsung.git
F: arch/arm/mach-exynos/
F: arch/arm/mach-s5pc1xx/
F: arch/arm/cpu/armv7/s5p-common/
@@ -394,7 +396,7 @@
ARM STI
M: Patrice Chotard <patrice.chotard@foss.st.com>
S: Maintained
-T: git https://gitlab.denx.de/u-boot/custodians/u-boot-stm.git
+T: git https://source.denx.de/u-boot/custodians/u-boot-stm.git
F: arch/arm/mach-sti/
F: arch/arm/include/asm/arch-sti*/
F: drivers/phy/sti_usb_phy.c
@@ -413,7 +415,7 @@
ARM STM SPEAR
#M: Vipin Kumar <vipin.kumar@st.com>
S: Orphaned (Since 2016-02)
-T: git https://gitlab.denx.de/u-boot/custodians/u-boot-stm.git
+T: git https://source.denx.de/u-boot/custodians/u-boot-stm.git
F: arch/arm/cpu/arm926ejs/spear/
F: arch/arm/include/asm/arch-spear/
@@ -421,7 +423,7 @@
M: Patrick Delaunay <patrick.delaunay@foss.st.com>
M: Patrice Chotard <patrice.chotard@foss.st.com>
L: uboot-stm32@st-md-mailman.stormreply.com (moderated for non-subscribers)
-T: git https://gitlab.denx.de/u-boot/custodians/u-boot-stm.git
+T: git https://source.denx.de/u-boot/custodians/u-boot-stm.git
S: Maintained
F: arch/arm/mach-stm32mp/
F: doc/board/st/
@@ -471,7 +473,7 @@
M: Jagan Teki <jagan@amarulasolutions.com>
M: Andre Przywara <andre.przywara@arm.com>
S: Maintained
-T: git https://gitlab.denx.de/u-boot/custodians/u-boot-sunxi.git
+T: git https://source.denx.de/u-boot/custodians/u-boot-sunxi.git
F: arch/arm/cpu/armv7/sunxi/
F: arch/arm/include/asm/arch-sunxi/
F: arch/arm/mach-sunxi/
@@ -480,14 +482,14 @@
ARM TEGRA
M: Tom Warren <twarren@nvidia.com>
S: Maintained
-T: git https://gitlab.denx.de/u-boot/custodians/u-boot-tegra.git
+T: git https://source.denx.de/u-boot/custodians/u-boot-tegra.git
F: arch/arm/mach-tegra/
F: arch/arm/include/asm/arch-tegra*/
ARM TI
M: Lokesh Vutla <lokeshvutla@ti.com>
S: Maintained
-T: git https://gitlab.denx.de/u-boot/custodians/u-boot-ti.git
+T: git https://source.denx.de/u-boot/custodians/u-boot-ti.git
F: arch/arm/mach-davinci/
F: arch/arm/mach-k3/
F: arch/arm/mach-keystone/
@@ -536,7 +538,7 @@
ARM VERSAL
M: Michal Simek <michal.simek@xilinx.com>
S: Maintained
-T: git https://gitlab.denx.de/u-boot/custodians/u-boot-microblaze.git
+T: git https://source.denx.de/u-boot/custodians/u-boot-microblaze.git
F: arch/arm/mach-versal/
F: drivers/watchdog/xilinx_wwdt.c
N: (?<!uni)versal
@@ -551,7 +553,7 @@
ARM ZYNQ
M: Michal Simek <monstr@monstr.eu>
S: Maintained
-T: git https://gitlab.denx.de/u-boot/custodians/u-boot-microblaze.git
+T: git https://source.denx.de/u-boot/custodians/u-boot-microblaze.git
F: arch/arm/mach-zynq/
F: doc/board/xilinx/
F: doc/device-tree-bindings/video/syncoam,seps525.txt
@@ -577,7 +579,7 @@
ARM ZYNQMP
M: Michal Simek <michal.simek@xilinx.com>
S: Maintained
-T: git https://gitlab.denx.de/u-boot/custodians/u-boot-microblaze.git
+T: git https://source.denx.de/u-boot/custodians/u-boot-microblaze.git
F: arch/arm/mach-zynqmp/
F: drivers/clk/clk_zynqmp.c
F: driver/firmware/firmware-zynqmp.c
@@ -607,7 +609,7 @@
ARM ZYNQMP R5
M: Michal Simek <michal.simek@xilinx.com>
S: Maintained
-T: git https://gitlab.denx.de/u-boot/custodians/u-boot-microblaze.git
+T: git https://source.denx.de/u-boot/custodians/u-boot-microblaze.git
F: arch/arm/mach-zynqmp-r5/
ARM PHYTIUM
@@ -639,14 +641,14 @@
CFI FLASH
M: Stefan Roese <sr@denx.de>
S: Maintained
-T: git https://gitlab.denx.de/u-boot/custodians/u-boot-cfi-flash.git
+T: git https://source.denx.de/u-boot/custodians/u-boot-cfi-flash.git
F: drivers/mtd/cfi_flash.c
F: drivers/mtd/jedec_flash.c
CLOCK
M: Lukasz Majewski <lukma@denx.de>
S: Maintained
-T: git https://gitlab.denx.de/u-boot/custodians/u-boot-clk.git
+T: git https://source.denx.de/u-boot/custodians/u-boot-clk.git
F: drivers/clk/
F: drivers/clk/imx/
@@ -654,20 +656,21 @@
M: Huan Wang <alison.wang@nxp.com>
M: Angelo Dureghello <angelo@sysam.it>
S: Maintained
-T: git https://gitlab.denx.de/u-boot/custodians/u-boot-coldfire.git
+T: git https://source.denx.de/u-boot/custodians/u-boot-coldfire.git
F: arch/m68k/
F: doc/arch/m68k.rst
DFU
M: Lukasz Majewski <lukma@denx.de>
S: Maintained
-T: git https://gitlab.denx.de/u-boot/custodians/u-boot-dfu.git
+T: git https://source.denx.de/u-boot/custodians/u-boot-dfu.git
F: cmd/dfu.c
F: cmd/usb_*.c
F: common/dfu.c
F: common/update.c
F: common/usb_storage.c
F: doc/api/dfu.rst
+F: doc/usage/dfu.rst
F: drivers/dfu/
F: drivers/usb/gadget/
F: include/dfu.h
@@ -675,7 +678,7 @@
DRIVER MODEL
M: Simon Glass <sjg@chromium.org>
S: Maintained
-T: git https://gitlab.denx.de/u-boot/custodians/u-boot-dm.git
+T: git https://source.denx.de/u-boot/custodians/u-boot-dm.git
F: doc/driver-model/
F: drivers/core/
F: include/dm/
@@ -685,7 +688,7 @@
M: Heinrich Schuchardt <xypron.glpk@gmx.de>
R: Alexander Graf <agraf@csgraf.de>
S: Maintained
-T: git https://gitlab.denx.de/u-boot/custodians/u-boot-efi.git
+T: git https://source.denx.de/u-boot/custodians/u-boot-efi.git
F: doc/api/efi.rst
F: doc/uefi/*
F: doc/usage/bootefi.rst
@@ -708,6 +711,7 @@
F: cmd/nvedit_efi.c
F: tools/efivar.py
F: tools/file2include.c
+F: tools/mkeficapsule.c
EFI VARIABLES VIA OP-TEE
M: Ilias Apalodimas <ilias.apalodimas@linaro.org>
@@ -728,7 +732,7 @@
FPGA
M: Michal Simek <michal.simek@xilinx.com>
S: Maintained
-T: git https://gitlab.denx.de/u-boot/custodians/u-boot-microblaze.git
+T: git https://source.denx.de/u-boot/custodians/u-boot-microblaze.git
F: drivers/fpga/
F: cmd/fpga.c
F: include/fpga.h
@@ -736,7 +740,7 @@
FLATTENED DEVICE TREE
M: Simon Glass <sjg@chromium.org>
S: Maintained
-T: git https://gitlab.denx.de/u-boot/custodians/u-boot-fdt.git
+T: git https://source.denx.de/u-boot/custodians/u-boot-fdt.git
F: lib/fdtdec*
F: lib/libfdt/
F: include/fdt*
@@ -747,25 +751,25 @@
FREEBSD
M: Rafal Jaworowski <raj@semihalf.com>
S: Maintained
-T: git https://gitlab.denx.de/u-boot/custodians/u-boot-freebsd.git
+T: git https://source.denx.de/u-boot/custodians/u-boot-freebsd.git
FREESCALE QORIQ
M: Priyanka Jain <priyanka.jain@nxp.com>
S: Maintained
-T: git https://gitlab.denx.de/u-boot/custodians/u-boot-fsl-qoriq.git
+T: git https://source.denx.de/u-boot/custodians/u-boot-fsl-qoriq.git
F: drivers/watchdog/sp805_wdt.c
F: drivers/watchdog/sbsa_gwdt.c
I2C
M: Heiko Schocher <hs@denx.de>
S: Maintained
-T: git https://gitlab.denx.de/u-boot/custodians/u-boot-i2c.git
+T: git https://source.denx.de/u-boot/custodians/u-boot-i2c.git
F: drivers/i2c/
LOGGING
M: Simon Glass <sjg@chromium.org>
S: Maintained
-T: git https://gitlab.denx.de/u-boot/u-boot.git
+T: git https://source.denx.de/u-boot/u-boot.git
F: common/log*
F: cmd/log.c
F: doc/develop/logging.rst
@@ -784,7 +788,7 @@
MICROBLAZE
M: Michal Simek <monstr@monstr.eu>
S: Maintained
-T: git https://gitlab.denx.de/u-boot/custodians/u-boot-microblaze.git
+T: git https://source.denx.de/u-boot/custodians/u-boot-microblaze.git
F: arch/microblaze/
F: cmd/mfsl.c
F: drivers/gpio/xilinx_gpio.c
@@ -799,7 +803,7 @@
MIPS
M: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
S: Maintained
-T: git https://gitlab.denx.de/u-boot/custodians/u-boot-mips.git
+T: git https://source.denx.de/u-boot/custodians/u-boot-mips.git
F: arch/mips/
MIPS CORTINA ACCESS CAxxxx
@@ -876,26 +880,26 @@
MMC
M: Peng Fan <peng.fan@nxp.com>
S: Maintained
-T: git https://gitlab.denx.de/u-boot/custodians/u-boot-mmc.git
+T: git https://source.denx.de/u-boot/custodians/u-boot-mmc.git
F: drivers/mmc/
NAND FLASH
#M: Scott Wood <oss@buserror.net>
S: Orphaned (Since 2018-07)
-T: git https://gitlab.denx.de/u-boot/custodians/u-boot-nand-flash.git
+T: git https://source.denx.de/u-boot/custodians/u-boot-nand-flash.git
F: drivers/mtd/nand/raw/
NDS32
M: Rick Chen <rick@andestech.com>
S: Maintained
-T: git https://gitlab.denx.de/u-boot/custodians/u-boot-nds32.git
+T: git https://source.denx.de/u-boot/custodians/u-boot-nds32.git
F: arch/nds32/
NETWORK
M: Joe Hershberger <joe.hershberger@ni.com>
M: Ramon Fried <rfried.dev@gmail.com>
S: Maintained
-T: git https://gitlab.denx.de/u-boot/custodians/u-boot-net.git
+T: git https://source.denx.de/u-boot/custodians/u-boot-net.git
F: drivers/net/
F: include/net.h
F: net/
@@ -903,13 +907,13 @@
NIOS
M: Thomas Chou <thomas@wytron.com.tw>
S: Maintained
-T: git https://gitlab.denx.de/u-boot/custodians/u-boot-nios.git
+T: git https://source.denx.de/u-boot/custodians/u-boot-nios.git
F: arch/nios2/
ONENAND
#M: Lukasz Majewski <l.majewski@majess.pl>
S: Orphaned (Since 2017-01)
-T: git https://gitlab.denx.de/u-boot/custodians/u-boot-onenand.git
+T: git https://source.denx.de/u-boot/custodians/u-boot-onenand.git
F: drivers/mtd/onenand/
PATMAN
@@ -931,7 +935,7 @@
POWER
M: Jaehoon Chung <jh80.chung@samsung.com>
S: Maintained
-T: git https://gitlab.denx.de/u-boot/custodians/u-boot-pmic.git
+T: git https://source.denx.de/u-boot/custodians/u-boot-pmic.git
F: drivers/power/
POWERPC
@@ -942,13 +946,13 @@
POWERPC MPC8XX
M: Christophe Leroy <christophe.leroy@c-s.fr>
S: Maintained
-T: git https://gitlab.denx.de/u-boot/custodians/u-boot-mpc8xx.git
+T: git https://source.denx.de/u-boot/custodians/u-boot-mpc8xx.git
F: arch/powerpc/cpu/mpc8xx/
POWERPC MPC83XX
M: Mario Six <mario.six@gdsys.cc>
S: Maintained
-T: git https://gitlab.denx.de/u-boot/custodians/u-boot-mpc83xx.git
+T: git https://source.denx.de/u-boot/custodians/u-boot-mpc83xx.git
F: drivers/ram/mpc83xx_sdram.c
F: include/dt-bindings/memory/mpc83xx-sdram.h
F: drivers/sysreset/sysreset_mpc83xx.c
@@ -966,19 +970,19 @@
POWERPC MPC85XX
M: Priyanka Jain <priyanka.jain@nxp.com>
S: Maintained
-T: git https://gitlab.denx.de/u-boot/custodians/u-boot-mpc85xx.git
+T: git https://source.denx.de/u-boot/custodians/u-boot-mpc85xx.git
F: arch/powerpc/cpu/mpc85xx/
POWERPC MPC86XX
M: Priyanka Jain <priyanka.jain@nxp.com>
S: Maintained
-T: git https://gitlab.denx.de/u-boot/custodians/u-boot-mpc86xx.git
+T: git https://source.denx.de/u-boot/custodians/u-boot-mpc86xx.git
F: arch/powerpc/cpu/mpc86xx/
RISC-V
M: Rick Chen <rick@andestech.com>
S: Maintained
-T: git https://gitlab.denx.de/u-boot/custodians/u-boot-riscv.git
+T: git https://source.denx.de/u-boot/custodians/u-boot-riscv.git
F: arch/riscv/
F: cmd/riscv/
F: doc/usage/sbi.rst
@@ -1023,13 +1027,13 @@
M: Marek Vasut <marek.vasut+renesas@gmail.com>
M: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
S: Maintained
-T: git https://gitlab.denx.de/u-boot/custodians/u-boot-sh.git
+T: git https://source.denx.de/u-boot/custodians/u-boot-sh.git
F: arch/sh/
SPI
M: Jagan Teki <jagan@amarulasolutions.com>
S: Maintained
-T: git https://gitlab.denx.de/u-boot/custodians/u-boot-spi.git
+T: git https://source.denx.de/u-boot/custodians/u-boot-spi.git
F: drivers/spi/
F: include/spi*
@@ -1127,7 +1131,7 @@
M: Kyungmin Park <kmpark@infradead.org>
M: Heiko Schocher <hs@denx.de>
S: Maintained
-T: git https://gitlab.denx.de/u-boot/custodians/u-boot-ubi.git
+T: git https://source.denx.de/u-boot/custodians/u-boot-ubi.git
F: drivers/mtd/ubi/
UFS
@@ -1138,7 +1142,7 @@
USB
M: Marek Vasut <marex@denx.de>
S: Maintained
-T: git https://gitlab.denx.de/u-boot/custodians/u-boot-usb.git
+T: git https://source.denx.de/u-boot/custodians/u-boot-usb.git
F: drivers/usb/
F: common/usb.c
F: common/usb_kbd.c
@@ -1147,14 +1151,14 @@
USB xHCI
M: Bin Meng <bmeng.cn@gmail.com>
S: Maintained
-T: git https://gitlab.denx.de/u-boot/custodians/u-boot-usb.git topic-xhci
+T: git https://source.denx.de/u-boot/custodians/u-boot-usb.git topic-xhci
F: drivers/usb/host/xhci*
F: include/usb/xhci.h
VIDEO
M: Anatolij Gustschin <agust@denx.de>
S: Maintained
-T: git https://gitlab.denx.de/u-boot/custodians/u-boot-video.git
+T: git https://source.denx.de/u-boot/custodians/u-boot-video.git
F: drivers/video/
F: common/lcd*.c
F: include/lcd*.h
@@ -1164,7 +1168,7 @@
M: Simon Glass <sjg@chromium.org>
M: Bin Meng <bmeng.cn@gmail.com>
S: Maintained
-T: git https://gitlab.denx.de/u-boot/custodians/u-boot-x86.git
+T: git https://source.denx.de/u-boot/custodians/u-boot-x86.git
F: arch/x86/
F: cmd/x86/
@@ -1194,7 +1198,7 @@
L: u-boot@lists.denx.de
Q: http://patchwork.ozlabs.org/project/uboot/list/
S: Maintained
-T: git https://gitlab.denx.de/u-boot/u-boot.git
+T: git https://source.denx.de/u-boot/u-boot.git
F: configs/tools-only_defconfig
F: *
F: */
diff --git a/Makefile b/Makefile
index 4da46de..3ebb38b 100644
--- a/Makefile
+++ b/Makefile
@@ -3,7 +3,7 @@
VERSION = 2021
PATCHLEVEL = 04
SUBLEVEL =
-EXTRAVERSION = -rc2
+EXTRAVERSION = -rc4
NAME =
# *DOCUMENTATION*
@@ -792,6 +792,7 @@
libs-y += drivers/usb/common/
libs-y += drivers/usb/emul/
libs-y += drivers/usb/eth/
+libs-$(CONFIG_USB_DEVICE) += drivers/usb/gadget/
libs-$(CONFIG_USB_GADGET) += drivers/usb/gadget/
libs-$(CONFIG_USB_GADGET) += drivers/usb/gadget/udc/
libs-y += drivers/usb/host/
@@ -1263,11 +1264,6 @@
$(if $(CONFIG_X86_16BIT_INIT),-R .start16 -R .resetvec) \
$(if $(CONFIG_MPC85XX_HAVE_RESET_VECTOR),-R .bootpg -R .resetvec)
-OBJCOPYFLAGS_u-boot-spl.hex = $(OBJCOPYFLAGS_u-boot.hex)
-
-spl/u-boot-spl.hex: spl/u-boot-spl FORCE
- $(call if_changed,objcopy)
-
binary_size_check: u-boot-nodtb.bin FORCE
@file_size=$(shell wc -c u-boot-nodtb.bin | awk '{print $$1}') ; \
map_size=$(shell cat u-boot.map | \
@@ -1386,6 +1382,7 @@
-a $(CONFIG_SYS_TEXT_BASE) -e $(CONFIG_SYS_UBOOT_START) \
-p $(CONFIG_FIT_EXTERNAL_OFFSET) \
-n "U-Boot $(UBOOTRELEASE) for $(BOARD) board" -E \
+ $(patsubst %,-b arch/$(ARCH)/dts/%.dtb,$(subst ",,$(DEVICE_TREE))) \
$(patsubst %,-b arch/$(ARCH)/dts/%.dtb,$(subst ",,$(CONFIG_OF_LIST))) \
$(patsubst %,-b arch/$(ARCH)/dts/%.dtbo,$(subst ",,$(CONFIG_OF_OVERLAY_LIST)))
else
@@ -1546,9 +1543,12 @@
endif
endif
-u-boot-with-spl.imx u-boot-with-nand-spl.imx: SPL u-boot.bin FORCE
+u-boot.uim: u-boot.bin FORCE
$(Q)$(MAKE) $(build)=arch/arm/mach-imx $@
+u-boot-with-spl.imx u-boot-with-nand-spl.imx: SPL $(if $(CONFIG_OF_SEPARATE),u-boot.img,u-boot.uim) FORCE
+ $(Q)$(MAKE) $(build)=arch/arm/mach-imx $@
+
MKIMAGEFLAGS_u-boot.ubl = -n $(UBL_CONFIG) -T ublimage -e $(CONFIG_SYS_TEXT_BASE)
u-boot.ubl: u-boot-with-spl.bin FORCE
@@ -1935,6 +1935,12 @@
@:
$(SPL_SIZE_CHECK)
+spl/u-boot-spl-dtb.bin: spl/u-boot-spl
+ @:
+
+spl/u-boot-spl-dtb.hex: spl/u-boot-spl
+ @:
+
spl/u-boot-spl: tools prepare \
$(if $(CONFIG_OF_SEPARATE)$(CONFIG_OF_EMBED)$(CONFIG_SPL_OF_PLATDATA),dts/dt.dtb) \
$(if $(CONFIG_OF_SEPARATE)$(CONFIG_OF_EMBED)$(CONFIG_TPL_OF_PLATDATA),dts/dt.dtb)
diff --git a/README b/README
index b962ba7..a565748 100644
--- a/README
+++ b/README
@@ -58,8 +58,8 @@
=========================
The U-Boot source code is maintained in the Git repository at
-https://gitlab.denx.de/u-boot/u-boot.git ; you can browse it online at
-https://gitlab.denx.de/u-boot/u-boot
+https://source.denx.de/u-boot/u-boot.git ; you can browse it online at
+https://source.denx.de/u-boot/u-boot
The "Tags" links on this page allow you to download tarballs of
any version you might be interested in. Official releases are also
diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
index d51abbe..3307f2b 100644
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@ -970,7 +970,7 @@
bool "Altera SOCFPGA family"
select ARCH_EARLY_INIT_R
select ARCH_MISC_INIT if !TARGET_SOCFPGA_ARRIA10
- select ARM64 if TARGET_SOCFPGA_STRATIX10 || TARGET_SOCFPGA_AGILEX
+ select ARM64 if TARGET_SOCFPGA_SOC64
select CPU_V7A if TARGET_SOCFPGA_GEN5 || TARGET_SOCFPGA_ARRIA10
select DM
select DM_SERIAL
@@ -982,7 +982,7 @@
select SPL_LIBGENERIC_SUPPORT
select SPL_NAND_SUPPORT if SPL_NAND_DENALI
select SPL_OF_CONTROL
- select SPL_SEPARATE_BSS if TARGET_SOCFPGA_STRATIX10 || TARGET_SOCFPGA_AGILEX
+ select SPL_SEPARATE_BSS if TARGET_SOCFPGA_SOC64
select SPL_SERIAL_SUPPORT
select SPL_SYSRESET
select SPL_WATCHDOG_SUPPORT
@@ -991,7 +991,7 @@
select SYS_THUMB_BUILD if TARGET_SOCFPGA_GEN5 || TARGET_SOCFPGA_ARRIA10
select SYSRESET
select SYSRESET_SOCFPGA if TARGET_SOCFPGA_GEN5 || TARGET_SOCFPGA_ARRIA10
- select SYSRESET_SOCFPGA_SOC64 if TARGET_SOCFPGA_STRATIX10 || TARGET_SOCFPGA_AGILEX
+ select SYSRESET_SOCFPGA_SOC64 if TARGET_SOCFPGA_SOC64
imply CMD_DM
imply CMD_MTDPARTS
imply CRC32_VERIFY
diff --git a/arch/arm/cpu/armv8/fsl-layerscape/Kconfig b/arch/arm/cpu/armv8/fsl-layerscape/Kconfig
index 4d46587..ae0b7b2 100644
--- a/arch/arm/cpu/armv8/fsl-layerscape/Kconfig
+++ b/arch/arm/cpu/armv8/fsl-layerscape/Kconfig
@@ -640,3 +640,13 @@
help
For some SoC(such as LS1043A and LS1046A), USB and QE-HDLC multiplex use
pins, select it when the pins are assigned to USB.
+
+config SYS_FSL_BOOTROM_BASE
+ hex
+ depends on FSL_LSCH2
+ default 0
+
+config SYS_FSL_BOOTROM_SIZE
+ hex
+ depends on FSL_LSCH2
+ default 0x1000000
diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile
index 33e483f..c671082 100644
--- a/arch/arm/dts/Makefile
+++ b/arch/arm/dts/Makefile
@@ -648,10 +648,17 @@
vf610-pcm052.dtb \
vf610-bk4r1.dtb
+dtb-$(CONFIG_MX23) += \
+ imx23-evk.dtb
+
dtb-$(CONFIG_MX28) += \
imx28-xea.dtb
+dtb-$(CONFIG_MX51) += \
+ imx51-babbage.dtb
+
dtb-$(CONFIG_MX53) += imx53-cx9020.dtb \
+ imx53-qsb.dtb \
imx53-kp.dtb \
imx53-m53menlo.dtb
@@ -783,6 +790,10 @@
dtb-$(CONFIG_ARCH_IMX8M) += \
imx8mm-evk.dtb \
+ imx8mm-venice.dtb \
+ imx8mm-venice-gw71xx-0x.dtb \
+ imx8mm-venice-gw72xx-0x.dtb \
+ imx8mm-venice-gw73xx-0x.dtb \
imx8mm-verdin.dtb \
phycore-imx8mm.dtb \
imx8mn-ddr4-evk.dtb \
diff --git a/arch/arm/dts/armada-385-turris-omnia-u-boot.dtsi b/arch/arm/dts/armada-385-turris-omnia-u-boot.dtsi
index 1b46797..af0655d 100644
--- a/arch/arm/dts/armada-385-turris-omnia-u-boot.dtsi
+++ b/arch/arm/dts/armada-385-turris-omnia-u-boot.dtsi
@@ -41,10 +41,7 @@
&spi0 {
u-boot,dm-pre-reloc;
- spi-flash@0 {
- compatible = "jedec,spi-nor";
- reg = <0>;
- spi-max-frequency = <40000000>;
+ spi-nor@0 {
u-boot,dm-pre-reloc;
};
};
diff --git a/arch/arm/dts/fsl-imx8qm-apalis.dts b/arch/arm/dts/fsl-imx8qm-apalis.dts
index 5187b79..0d8d3b3 100644
--- a/arch/arm/dts/fsl-imx8qm-apalis.dts
+++ b/arch/arm/dts/fsl-imx8qm-apalis.dts
@@ -503,7 +503,7 @@
pinctrl-0 = <&pinctrl_fec1>;
fsl,magic-packet;
phy-handle = <ðphy0>;
- phy-mode = "rgmii";
+ phy-mode = "rgmii-id";
phy-reset-duration = <10>;
phy-reset-gpios = <&gpio1 11 1>;
status = "okay";
diff --git a/arch/arm/dts/fsl-imx8qxp-apalis.dts b/arch/arm/dts/fsl-imx8qxp-apalis.dts
index 6bd231b..9cb3d3a 100644
--- a/arch/arm/dts/fsl-imx8qxp-apalis.dts
+++ b/arch/arm/dts/fsl-imx8qxp-apalis.dts
@@ -229,7 +229,7 @@
pinctrl-0 = <&pinctrl_fec1>;
fsl,magic-packet;
phy-handle = <ðphy0>;
- phy-mode = "rgmii";
+ phy-mode = "rgmii-id";
phy-reset-duration = <10>;
phy-reset-post-delay = <150>;
phy-reset-gpios = <&gpio3 4 GPIO_ACTIVE_LOW>;
diff --git a/arch/arm/dts/imx23-evk-u-boot.dtsi b/arch/arm/dts/imx23-evk-u-boot.dtsi
new file mode 100644
index 0000000..165e220
--- /dev/null
+++ b/arch/arm/dts/imx23-evk-u-boot.dtsi
@@ -0,0 +1,4 @@
+// SPDX-License-Identifier: GPL-2.0+
+
+#include "imx23-u-boot.dtsi"
+
diff --git a/arch/arm/dts/imx23-evk.dts b/arch/arm/dts/imx23-evk.dts
new file mode 100644
index 0000000..8cbaf1c
--- /dev/null
+++ b/arch/arm/dts/imx23-evk.dts
@@ -0,0 +1,145 @@
+// SPDX-License-Identifier: GPL-2.0+
+//
+// Copyright 2012 Freescale Semiconductor, Inc.
+
+/dts-v1/;
+#include "imx23.dtsi"
+
+/ {
+ model = "Freescale i.MX23 Evaluation Kit";
+ compatible = "fsl,imx23-evk", "fsl,imx23";
+
+ memory@40000000 {
+ device_type = "memory";
+ reg = <0x40000000 0x08000000>;
+ };
+
+ reg_vddio_sd0: regulator-vddio-sd0 {
+ compatible = "regulator-fixed";
+ regulator-name = "vddio-sd0";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ gpio = <&gpio1 29 0>;
+ };
+
+ reg_lcd_3v3: regulator-lcd-3v3 {
+ compatible = "regulator-fixed";
+ regulator-name = "lcd-3v3";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ gpio = <&gpio1 18 0>;
+ enable-active-high;
+ };
+
+ reg_lcd_5v: regulator-lcd-5v {
+ compatible = "regulator-fixed";
+ regulator-name = "lcd-5v";
+ regulator-min-microvolt = <5000000>;
+ regulator-max-microvolt = <5000000>;
+ };
+
+ panel {
+ compatible = "sii,43wvf1g";
+ backlight = <&backlight_display>;
+ dvdd-supply = <®_lcd_3v3>;
+ avdd-supply = <®_lcd_5v>;
+
+ port {
+ panel_in: endpoint {
+ remote-endpoint = <&display_out>;
+ };
+ };
+ };
+
+ apb@80000000 {
+ apbh@80000000 {
+ nand-controller@8000c000 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&gpmi_pins_a &gpmi_pins_fixup>;
+ status = "okay";
+ };
+
+ ssp0: spi@80010000 {
+ compatible = "fsl,imx23-mmc";
+ pinctrl-names = "default";
+ pinctrl-0 = <&mmc0_4bit_pins_a &mmc0_pins_fixup>;
+ bus-width = <4>;
+ wp-gpios = <&gpio1 30 0>;
+ vmmc-supply = <®_vddio_sd0>;
+ status = "okay";
+ };
+
+ pinctrl@80018000 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&hog_pins_a>;
+
+ hog_pins_a: hog@0 {
+ reg = <0>;
+ fsl,pinmux-ids = <
+ MX23_PAD_LCD_RESET__GPIO_1_18
+ MX23_PAD_PWM3__GPIO_1_29
+ MX23_PAD_PWM4__GPIO_1_30
+ MX23_PAD_SSP1_DETECT__SSP1_DETECT
+ >;
+ fsl,drive-strength = <MXS_DRIVE_4mA>;
+ fsl,voltage = <MXS_VOLTAGE_HIGH>;
+ fsl,pull-up = <MXS_PULL_DISABLE>;
+ };
+ };
+
+ lcdif@80030000 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&lcdif_24bit_pins_a>;
+ status = "okay";
+
+ port {
+ display_out: endpoint {
+ remote-endpoint = <&panel_in>;
+ };
+ };
+ };
+ };
+
+ apbx@80040000 {
+ lradc@80050000 {
+ status = "okay";
+ fsl,lradc-touchscreen-wires = <4>;
+ };
+
+ pwm: pwm@80064000 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pwm2_pins_a>;
+ status = "okay";
+ };
+
+ auart0: serial@8006c000 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&auart0_pins_a>;
+ status = "okay";
+ };
+
+ duart: serial@80070000 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&duart_pins_a>;
+ status = "okay";
+ };
+
+ usbphy0: usbphy@8007c000 {
+ status = "okay";
+ };
+ };
+ };
+
+ ahb@80080000 {
+ usb0: usb@80080000 {
+ status = "okay";
+ };
+ };
+
+ backlight_display: backlight {
+ compatible = "pwm-backlight";
+ pwms = <&pwm 2 5000000>;
+ brightness-levels = <0 4 8 16 32 64 128 255>;
+ default-brightness-level = <6>;
+ };
+};
diff --git a/arch/arm/dts/imx23-pinfunc.h b/arch/arm/dts/imx23-pinfunc.h
new file mode 100644
index 0000000..5c0f32c
--- /dev/null
+++ b/arch/arm/dts/imx23-pinfunc.h
@@ -0,0 +1,333 @@
+/*
+ * Header providing constants for i.MX23 pinctrl bindings.
+ *
+ * Copyright (C) 2013 Lothar Waßmann <LW@KARO-electronics.de>
+ *
+ * The code contained herein is licensed under the GNU General Public
+ * License. You may obtain a copy of the GNU General Public License
+ * Version 2 at the following locations:
+ *
+ * http://www.opensource.org/licenses/gpl-license.html
+ * http://www.gnu.org/copyleft/gpl.html
+ */
+
+#ifndef __DT_BINDINGS_MX23_PINCTRL_H__
+#define __DT_BINDINGS_MX23_PINCTRL_H__
+
+#include "mxs-pinfunc.h"
+
+#define MX23_PAD_GPMI_D00__GPMI_D00 0x0000
+#define MX23_PAD_GPMI_D01__GPMI_D01 0x0010
+#define MX23_PAD_GPMI_D02__GPMI_D02 0x0020
+#define MX23_PAD_GPMI_D03__GPMI_D03 0x0030
+#define MX23_PAD_GPMI_D04__GPMI_D04 0x0040
+#define MX23_PAD_GPMI_D05__GPMI_D05 0x0050
+#define MX23_PAD_GPMI_D06__GPMI_D06 0x0060
+#define MX23_PAD_GPMI_D07__GPMI_D07 0x0070
+#define MX23_PAD_GPMI_D08__GPMI_D08 0x0080
+#define MX23_PAD_GPMI_D09__GPMI_D09 0x0090
+#define MX23_PAD_GPMI_D10__GPMI_D10 0x00a0
+#define MX23_PAD_GPMI_D11__GPMI_D11 0x00b0
+#define MX23_PAD_GPMI_D12__GPMI_D12 0x00c0
+#define MX23_PAD_GPMI_D13__GPMI_D13 0x00d0
+#define MX23_PAD_GPMI_D14__GPMI_D14 0x00e0
+#define MX23_PAD_GPMI_D15__GPMI_D15 0x00f0
+#define MX23_PAD_GPMI_CLE__GPMI_CLE 0x0100
+#define MX23_PAD_GPMI_ALE__GPMI_ALE 0x0110
+#define MX23_PAD_GPMI_CE2N__GPMI_CE2N 0x0120
+#define MX23_PAD_GPMI_RDY0__GPMI_RDY0 0x0130
+#define MX23_PAD_GPMI_RDY1__GPMI_RDY1 0x0140
+#define MX23_PAD_GPMI_RDY2__GPMI_RDY2 0x0150
+#define MX23_PAD_GPMI_RDY3__GPMI_RDY3 0x0160
+#define MX23_PAD_GPMI_WPN__GPMI_WPN 0x0170
+#define MX23_PAD_GPMI_WRN__GPMI_WRN 0x0180
+#define MX23_PAD_GPMI_RDN__GPMI_RDN 0x0190
+#define MX23_PAD_AUART1_CTS__AUART1_CTS 0x01a0
+#define MX23_PAD_AUART1_RTS__AUART1_RTS 0x01b0
+#define MX23_PAD_AUART1_RX__AUART1_RX 0x01c0
+#define MX23_PAD_AUART1_TX__AUART1_TX 0x01d0
+#define MX23_PAD_I2C_SCL__I2C_SCL 0x01e0
+#define MX23_PAD_I2C_SDA__I2C_SDA 0x01f0
+#define MX23_PAD_LCD_D00__LCD_D00 0x1000
+#define MX23_PAD_LCD_D01__LCD_D01 0x1010
+#define MX23_PAD_LCD_D02__LCD_D02 0x1020
+#define MX23_PAD_LCD_D03__LCD_D03 0x1030
+#define MX23_PAD_LCD_D04__LCD_D04 0x1040
+#define MX23_PAD_LCD_D05__LCD_D05 0x1050
+#define MX23_PAD_LCD_D06__LCD_D06 0x1060
+#define MX23_PAD_LCD_D07__LCD_D07 0x1070
+#define MX23_PAD_LCD_D08__LCD_D08 0x1080
+#define MX23_PAD_LCD_D09__LCD_D09 0x1090
+#define MX23_PAD_LCD_D10__LCD_D10 0x10a0
+#define MX23_PAD_LCD_D11__LCD_D11 0x10b0
+#define MX23_PAD_LCD_D12__LCD_D12 0x10c0
+#define MX23_PAD_LCD_D13__LCD_D13 0x10d0
+#define MX23_PAD_LCD_D14__LCD_D14 0x10e0
+#define MX23_PAD_LCD_D15__LCD_D15 0x10f0
+#define MX23_PAD_LCD_D16__LCD_D16 0x1100
+#define MX23_PAD_LCD_D17__LCD_D17 0x1110
+#define MX23_PAD_LCD_RESET__LCD_RESET 0x1120
+#define MX23_PAD_LCD_RS__LCD_RS 0x1130
+#define MX23_PAD_LCD_WR__LCD_WR 0x1140
+#define MX23_PAD_LCD_CS__LCD_CS 0x1150
+#define MX23_PAD_LCD_DOTCK__LCD_DOTCK 0x1160
+#define MX23_PAD_LCD_ENABLE__LCD_ENABLE 0x1170
+#define MX23_PAD_LCD_HSYNC__LCD_HSYNC 0x1180
+#define MX23_PAD_LCD_VSYNC__LCD_VSYNC 0x1190
+#define MX23_PAD_PWM0__PWM0 0x11a0
+#define MX23_PAD_PWM1__PWM1 0x11b0
+#define MX23_PAD_PWM2__PWM2 0x11c0
+#define MX23_PAD_PWM3__PWM3 0x11d0
+#define MX23_PAD_PWM4__PWM4 0x11e0
+#define MX23_PAD_SSP1_CMD__SSP1_CMD 0x2000
+#define MX23_PAD_SSP1_DETECT__SSP1_DETECT 0x2010
+#define MX23_PAD_SSP1_DATA0__SSP1_DATA0 0x2020
+#define MX23_PAD_SSP1_DATA1__SSP1_DATA1 0x2030
+#define MX23_PAD_SSP1_DATA2__SSP1_DATA2 0x2040
+#define MX23_PAD_SSP1_DATA3__SSP1_DATA3 0x2050
+#define MX23_PAD_SSP1_SCK__SSP1_SCK 0x2060
+#define MX23_PAD_ROTARYA__ROTARYA 0x2070
+#define MX23_PAD_ROTARYB__ROTARYB 0x2080
+#define MX23_PAD_EMI_A00__EMI_A00 0x2090
+#define MX23_PAD_EMI_A01__EMI_A01 0x20a0
+#define MX23_PAD_EMI_A02__EMI_A02 0x20b0
+#define MX23_PAD_EMI_A03__EMI_A03 0x20c0
+#define MX23_PAD_EMI_A04__EMI_A04 0x20d0
+#define MX23_PAD_EMI_A05__EMI_A05 0x20e0
+#define MX23_PAD_EMI_A06__EMI_A06 0x20f0
+#define MX23_PAD_EMI_A07__EMI_A07 0x2100
+#define MX23_PAD_EMI_A08__EMI_A08 0x2110
+#define MX23_PAD_EMI_A09__EMI_A09 0x2120
+#define MX23_PAD_EMI_A10__EMI_A10 0x2130
+#define MX23_PAD_EMI_A11__EMI_A11 0x2140
+#define MX23_PAD_EMI_A12__EMI_A12 0x2150
+#define MX23_PAD_EMI_BA0__EMI_BA0 0x2160
+#define MX23_PAD_EMI_BA1__EMI_BA1 0x2170
+#define MX23_PAD_EMI_CASN__EMI_CASN 0x2180
+#define MX23_PAD_EMI_CE0N__EMI_CE0N 0x2190
+#define MX23_PAD_EMI_CE1N__EMI_CE1N 0x21a0
+#define MX23_PAD_GPMI_CE1N__GPMI_CE1N 0x21b0
+#define MX23_PAD_GPMI_CE0N__GPMI_CE0N 0x21c0
+#define MX23_PAD_EMI_CKE__EMI_CKE 0x21d0
+#define MX23_PAD_EMI_RASN__EMI_RASN 0x21e0
+#define MX23_PAD_EMI_WEN__EMI_WEN 0x21f0
+#define MX23_PAD_EMI_D00__EMI_D00 0x3000
+#define MX23_PAD_EMI_D01__EMI_D01 0x3010
+#define MX23_PAD_EMI_D02__EMI_D02 0x3020
+#define MX23_PAD_EMI_D03__EMI_D03 0x3030
+#define MX23_PAD_EMI_D04__EMI_D04 0x3040
+#define MX23_PAD_EMI_D05__EMI_D05 0x3050
+#define MX23_PAD_EMI_D06__EMI_D06 0x3060
+#define MX23_PAD_EMI_D07__EMI_D07 0x3070
+#define MX23_PAD_EMI_D08__EMI_D08 0x3080
+#define MX23_PAD_EMI_D09__EMI_D09 0x3090
+#define MX23_PAD_EMI_D10__EMI_D10 0x30a0
+#define MX23_PAD_EMI_D11__EMI_D11 0x30b0
+#define MX23_PAD_EMI_D12__EMI_D12 0x30c0
+#define MX23_PAD_EMI_D13__EMI_D13 0x30d0
+#define MX23_PAD_EMI_D14__EMI_D14 0x30e0
+#define MX23_PAD_EMI_D15__EMI_D15 0x30f0
+#define MX23_PAD_EMI_DQM0__EMI_DQM0 0x3100
+#define MX23_PAD_EMI_DQM1__EMI_DQM1 0x3110
+#define MX23_PAD_EMI_DQS0__EMI_DQS0 0x3120
+#define MX23_PAD_EMI_DQS1__EMI_DQS1 0x3130
+#define MX23_PAD_EMI_CLK__EMI_CLK 0x3140
+#define MX23_PAD_EMI_CLKN__EMI_CLKN 0x3150
+#define MX23_PAD_GPMI_D00__LCD_D8 0x0001
+#define MX23_PAD_GPMI_D01__LCD_D9 0x0011
+#define MX23_PAD_GPMI_D02__LCD_D10 0x0021
+#define MX23_PAD_GPMI_D03__LCD_D11 0x0031
+#define MX23_PAD_GPMI_D04__LCD_D12 0x0041
+#define MX23_PAD_GPMI_D05__LCD_D13 0x0051
+#define MX23_PAD_GPMI_D06__LCD_D14 0x0061
+#define MX23_PAD_GPMI_D07__LCD_D15 0x0071
+#define MX23_PAD_GPMI_D08__LCD_D18 0x0081
+#define MX23_PAD_GPMI_D09__LCD_D19 0x0091
+#define MX23_PAD_GPMI_D10__LCD_D20 0x00a1
+#define MX23_PAD_GPMI_D11__LCD_D21 0x00b1
+#define MX23_PAD_GPMI_D12__LCD_D22 0x00c1
+#define MX23_PAD_GPMI_D13__LCD_D23 0x00d1
+#define MX23_PAD_GPMI_D14__AUART2_RX 0x00e1
+#define MX23_PAD_GPMI_D15__AUART2_TX 0x00f1
+#define MX23_PAD_GPMI_CLE__LCD_D16 0x0101
+#define MX23_PAD_GPMI_ALE__LCD_D17 0x0111
+#define MX23_PAD_GPMI_CE2N__ATA_A2 0x0121
+#define MX23_PAD_AUART1_RTS__IR_CLK 0x01b1
+#define MX23_PAD_AUART1_RX__IR_RX 0x01c1
+#define MX23_PAD_AUART1_TX__IR_TX 0x01d1
+#define MX23_PAD_I2C_SCL__GPMI_RDY2 0x01e1
+#define MX23_PAD_I2C_SDA__GPMI_CE2N 0x01f1
+#define MX23_PAD_LCD_D00__ETM_DA8 0x1001
+#define MX23_PAD_LCD_D01__ETM_DA9 0x1011
+#define MX23_PAD_LCD_D02__ETM_DA10 0x1021
+#define MX23_PAD_LCD_D03__ETM_DA11 0x1031
+#define MX23_PAD_LCD_D04__ETM_DA12 0x1041
+#define MX23_PAD_LCD_D05__ETM_DA13 0x1051
+#define MX23_PAD_LCD_D06__ETM_DA14 0x1061
+#define MX23_PAD_LCD_D07__ETM_DA15 0x1071
+#define MX23_PAD_LCD_D08__ETM_DA0 0x1081
+#define MX23_PAD_LCD_D09__ETM_DA1 0x1091
+#define MX23_PAD_LCD_D10__ETM_DA2 0x10a1
+#define MX23_PAD_LCD_D11__ETM_DA3 0x10b1
+#define MX23_PAD_LCD_D12__ETM_DA4 0x10c1
+#define MX23_PAD_LCD_D13__ETM_DA5 0x10d1
+#define MX23_PAD_LCD_D14__ETM_DA6 0x10e1
+#define MX23_PAD_LCD_D15__ETM_DA7 0x10f1
+#define MX23_PAD_LCD_RESET__ETM_TCTL 0x1121
+#define MX23_PAD_LCD_RS__ETM_TCLK 0x1131
+#define MX23_PAD_LCD_DOTCK__GPMI_RDY3 0x1161
+#define MX23_PAD_LCD_ENABLE__I2C_SCL 0x1171
+#define MX23_PAD_LCD_HSYNC__I2C_SDA 0x1181
+#define MX23_PAD_LCD_VSYNC__LCD_BUSY 0x1191
+#define MX23_PAD_PWM0__ROTARYA 0x11a1
+#define MX23_PAD_PWM1__ROTARYB 0x11b1
+#define MX23_PAD_PWM2__GPMI_RDY3 0x11c1
+#define MX23_PAD_PWM3__ETM_TCTL 0x11d1
+#define MX23_PAD_PWM4__ETM_TCLK 0x11e1
+#define MX23_PAD_SSP1_DETECT__GPMI_CE3N 0x2011
+#define MX23_PAD_SSP1_DATA1__I2C_SCL 0x2031
+#define MX23_PAD_SSP1_DATA2__I2C_SDA 0x2041
+#define MX23_PAD_ROTARYA__AUART2_RTS 0x2071
+#define MX23_PAD_ROTARYB__AUART2_CTS 0x2081
+#define MX23_PAD_GPMI_D00__SSP2_DATA0 0x0002
+#define MX23_PAD_GPMI_D01__SSP2_DATA1 0x0012
+#define MX23_PAD_GPMI_D02__SSP2_DATA2 0x0022
+#define MX23_PAD_GPMI_D03__SSP2_DATA3 0x0032
+#define MX23_PAD_GPMI_D04__SSP2_DATA4 0x0042
+#define MX23_PAD_GPMI_D05__SSP2_DATA5 0x0052
+#define MX23_PAD_GPMI_D06__SSP2_DATA6 0x0062
+#define MX23_PAD_GPMI_D07__SSP2_DATA7 0x0072
+#define MX23_PAD_GPMI_D08__SSP1_DATA4 0x0082
+#define MX23_PAD_GPMI_D09__SSP1_DATA5 0x0092
+#define MX23_PAD_GPMI_D10__SSP1_DATA6 0x00a2
+#define MX23_PAD_GPMI_D11__SSP1_DATA7 0x00b2
+#define MX23_PAD_GPMI_D15__GPMI_CE3N 0x00f2
+#define MX23_PAD_GPMI_RDY0__SSP2_DETECT 0x0132
+#define MX23_PAD_GPMI_RDY1__SSP2_CMD 0x0142
+#define MX23_PAD_GPMI_WRN__SSP2_SCK 0x0182
+#define MX23_PAD_AUART1_CTS__SSP1_DATA4 0x01a2
+#define MX23_PAD_AUART1_RTS__SSP1_DATA5 0x01b2
+#define MX23_PAD_AUART1_RX__SSP1_DATA6 0x01c2
+#define MX23_PAD_AUART1_TX__SSP1_DATA7 0x01d2
+#define MX23_PAD_I2C_SCL__AUART1_TX 0x01e2
+#define MX23_PAD_I2C_SDA__AUART1_RX 0x01f2
+#define MX23_PAD_LCD_D08__SAIF2_SDATA0 0x1082
+#define MX23_PAD_LCD_D09__SAIF1_SDATA0 0x1092
+#define MX23_PAD_LCD_D10__SAIF_MCLK_BITCLK 0x10a2
+#define MX23_PAD_LCD_D11__SAIF_LRCLK 0x10b2
+#define MX23_PAD_LCD_D12__SAIF2_SDATA1 0x10c2
+#define MX23_PAD_LCD_D13__SAIF2_SDATA2 0x10d2
+#define MX23_PAD_LCD_D14__SAIF1_SDATA2 0x10e2
+#define MX23_PAD_LCD_D15__SAIF1_SDATA1 0x10f2
+#define MX23_PAD_LCD_D16__SAIF_ALT_BITCLK 0x1102
+#define MX23_PAD_LCD_RESET__GPMI_CE3N 0x1122
+#define MX23_PAD_PWM0__DUART_RX 0x11a2
+#define MX23_PAD_PWM1__DUART_TX 0x11b2
+#define MX23_PAD_PWM3__AUART1_CTS 0x11d2
+#define MX23_PAD_PWM4__AUART1_RTS 0x11e2
+#define MX23_PAD_SSP1_CMD__JTAG_TDO 0x2002
+#define MX23_PAD_SSP1_DETECT__USB_OTG_ID 0x2012
+#define MX23_PAD_SSP1_DATA0__JTAG_TDI 0x2022
+#define MX23_PAD_SSP1_DATA1__JTAG_TCLK 0x2032
+#define MX23_PAD_SSP1_DATA2__JTAG_RTCK 0x2042
+#define MX23_PAD_SSP1_DATA3__JTAG_TMS 0x2052
+#define MX23_PAD_SSP1_SCK__JTAG_TRST 0x2062
+#define MX23_PAD_ROTARYA__SPDIF 0x2072
+#define MX23_PAD_ROTARYB__GPMI_CE3N 0x2082
+#define MX23_PAD_GPMI_D00__GPIO_0_0 0x0003
+#define MX23_PAD_GPMI_D01__GPIO_0_1 0x0013
+#define MX23_PAD_GPMI_D02__GPIO_0_2 0x0023
+#define MX23_PAD_GPMI_D03__GPIO_0_3 0x0033
+#define MX23_PAD_GPMI_D04__GPIO_0_4 0x0043
+#define MX23_PAD_GPMI_D05__GPIO_0_5 0x0053
+#define MX23_PAD_GPMI_D06__GPIO_0_6 0x0063
+#define MX23_PAD_GPMI_D07__GPIO_0_7 0x0073
+#define MX23_PAD_GPMI_D08__GPIO_0_8 0x0083
+#define MX23_PAD_GPMI_D09__GPIO_0_9 0x0093
+#define MX23_PAD_GPMI_D10__GPIO_0_10 0x00a3
+#define MX23_PAD_GPMI_D11__GPIO_0_11 0x00b3
+#define MX23_PAD_GPMI_D12__GPIO_0_12 0x00c3
+#define MX23_PAD_GPMI_D13__GPIO_0_13 0x00d3
+#define MX23_PAD_GPMI_D14__GPIO_0_14 0x00e3
+#define MX23_PAD_GPMI_D15__GPIO_0_15 0x00f3
+#define MX23_PAD_GPMI_CLE__GPIO_0_16 0x0103
+#define MX23_PAD_GPMI_ALE__GPIO_0_17 0x0113
+#define MX23_PAD_GPMI_CE2N__GPIO_0_18 0x0123
+#define MX23_PAD_GPMI_RDY0__GPIO_0_19 0x0133
+#define MX23_PAD_GPMI_RDY1__GPIO_0_20 0x0143
+#define MX23_PAD_GPMI_RDY2__GPIO_0_21 0x0153
+#define MX23_PAD_GPMI_RDY3__GPIO_0_22 0x0163
+#define MX23_PAD_GPMI_WPN__GPIO_0_23 0x0173
+#define MX23_PAD_GPMI_WRN__GPIO_0_24 0x0183
+#define MX23_PAD_GPMI_RDN__GPIO_0_25 0x0193
+#define MX23_PAD_AUART1_CTS__GPIO_0_26 0x01a3
+#define MX23_PAD_AUART1_RTS__GPIO_0_27 0x01b3
+#define MX23_PAD_AUART1_RX__GPIO_0_28 0x01c3
+#define MX23_PAD_AUART1_TX__GPIO_0_29 0x01d3
+#define MX23_PAD_I2C_SCL__GPIO_0_30 0x01e3
+#define MX23_PAD_I2C_SDA__GPIO_0_31 0x01f3
+#define MX23_PAD_LCD_D00__GPIO_1_0 0x1003
+#define MX23_PAD_LCD_D01__GPIO_1_1 0x1013
+#define MX23_PAD_LCD_D02__GPIO_1_2 0x1023
+#define MX23_PAD_LCD_D03__GPIO_1_3 0x1033
+#define MX23_PAD_LCD_D04__GPIO_1_4 0x1043
+#define MX23_PAD_LCD_D05__GPIO_1_5 0x1053
+#define MX23_PAD_LCD_D06__GPIO_1_6 0x1063
+#define MX23_PAD_LCD_D07__GPIO_1_7 0x1073
+#define MX23_PAD_LCD_D08__GPIO_1_8 0x1083
+#define MX23_PAD_LCD_D09__GPIO_1_9 0x1093
+#define MX23_PAD_LCD_D10__GPIO_1_10 0x10a3
+#define MX23_PAD_LCD_D11__GPIO_1_11 0x10b3
+#define MX23_PAD_LCD_D12__GPIO_1_12 0x10c3
+#define MX23_PAD_LCD_D13__GPIO_1_13 0x10d3
+#define MX23_PAD_LCD_D14__GPIO_1_14 0x10e3
+#define MX23_PAD_LCD_D15__GPIO_1_15 0x10f3
+#define MX23_PAD_LCD_D16__GPIO_1_16 0x1103
+#define MX23_PAD_LCD_D17__GPIO_1_17 0x1113
+#define MX23_PAD_LCD_RESET__GPIO_1_18 0x1123
+#define MX23_PAD_LCD_RS__GPIO_1_19 0x1133
+#define MX23_PAD_LCD_WR__GPIO_1_20 0x1143
+#define MX23_PAD_LCD_CS__GPIO_1_21 0x1153
+#define MX23_PAD_LCD_DOTCK__GPIO_1_22 0x1163
+#define MX23_PAD_LCD_ENABLE__GPIO_1_23 0x1173
+#define MX23_PAD_LCD_HSYNC__GPIO_1_24 0x1183
+#define MX23_PAD_LCD_VSYNC__GPIO_1_25 0x1193
+#define MX23_PAD_PWM0__GPIO_1_26 0x11a3
+#define MX23_PAD_PWM1__GPIO_1_27 0x11b3
+#define MX23_PAD_PWM2__GPIO_1_28 0x11c3
+#define MX23_PAD_PWM3__GPIO_1_29 0x11d3
+#define MX23_PAD_PWM4__GPIO_1_30 0x11e3
+#define MX23_PAD_SSP1_CMD__GPIO_2_0 0x2003
+#define MX23_PAD_SSP1_DETECT__GPIO_2_1 0x2013
+#define MX23_PAD_SSP1_DATA0__GPIO_2_2 0x2023
+#define MX23_PAD_SSP1_DATA1__GPIO_2_3 0x2033
+#define MX23_PAD_SSP1_DATA2__GPIO_2_4 0x2043
+#define MX23_PAD_SSP1_DATA3__GPIO_2_5 0x2053
+#define MX23_PAD_SSP1_SCK__GPIO_2_6 0x2063
+#define MX23_PAD_ROTARYA__GPIO_2_7 0x2073
+#define MX23_PAD_ROTARYB__GPIO_2_8 0x2083
+#define MX23_PAD_EMI_A00__GPIO_2_9 0x2093
+#define MX23_PAD_EMI_A01__GPIO_2_10 0x20a3
+#define MX23_PAD_EMI_A02__GPIO_2_11 0x20b3
+#define MX23_PAD_EMI_A03__GPIO_2_12 0x20c3
+#define MX23_PAD_EMI_A04__GPIO_2_13 0x20d3
+#define MX23_PAD_EMI_A05__GPIO_2_14 0x20e3
+#define MX23_PAD_EMI_A06__GPIO_2_15 0x20f3
+#define MX23_PAD_EMI_A07__GPIO_2_16 0x2103
+#define MX23_PAD_EMI_A08__GPIO_2_17 0x2113
+#define MX23_PAD_EMI_A09__GPIO_2_18 0x2123
+#define MX23_PAD_EMI_A10__GPIO_2_19 0x2133
+#define MX23_PAD_EMI_A11__GPIO_2_20 0x2143
+#define MX23_PAD_EMI_A12__GPIO_2_21 0x2153
+#define MX23_PAD_EMI_BA0__GPIO_2_22 0x2163
+#define MX23_PAD_EMI_BA1__GPIO_2_23 0x2173
+#define MX23_PAD_EMI_CASN__GPIO_2_24 0x2183
+#define MX23_PAD_EMI_CE0N__GPIO_2_25 0x2193
+#define MX23_PAD_EMI_CE1N__GPIO_2_26 0x21a3
+#define MX23_PAD_GPMI_CE1N__GPIO_2_27 0x21b3
+#define MX23_PAD_GPMI_CE0N__GPIO_2_28 0x21c3
+#define MX23_PAD_EMI_CKE__GPIO_2_29 0x21d3
+#define MX23_PAD_EMI_RASN__GPIO_2_30 0x21e3
+#define MX23_PAD_EMI_WEN__GPIO_2_31 0x21f3
+
+#endif /* __DT_BINDINGS_MX23_PINCTRL_H__ */
diff --git a/arch/arm/dts/imx23-u-boot.dtsi b/arch/arm/dts/imx23-u-boot.dtsi
new file mode 100644
index 0000000..5e87aca
--- /dev/null
+++ b/arch/arm/dts/imx23-u-boot.dtsi
@@ -0,0 +1,14 @@
+// SPDX-License-Identifier: GPL-2.0+
+
+&gpio0 {
+ gpio-ranges = <&pinctrl 0 0 32>;
+};
+
+&gpio1 {
+ gpio-ranges = <&pinctrl 0 32 31>;
+};
+
+&gpio2 {
+ gpio-ranges = <&pinctrl 0 63 32>;
+};
+
diff --git a/arch/arm/dts/imx23.dtsi b/arch/arm/dts/imx23.dtsi
new file mode 100644
index 0000000..4cfec77
--- /dev/null
+++ b/arch/arm/dts/imx23.dtsi
@@ -0,0 +1,636 @@
+// SPDX-License-Identifier: GPL-2.0+
+//
+// Copyright 2012 Freescale Semiconductor, Inc.
+
+#include "imx23-pinfunc.h"
+
+/ {
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ interrupt-parent = <&icoll>;
+ /*
+ * The decompressor and also some bootloaders rely on a
+ * pre-existing /chosen node to be available to insert the
+ * command line and merge other ATAGS info.
+ */
+ chosen {};
+
+ aliases {
+ gpio0 = &gpio0;
+ gpio1 = &gpio1;
+ gpio2 = &gpio2;
+ serial0 = &auart0;
+ serial1 = &auart1;
+ spi0 = &ssp0;
+ spi1 = &ssp1;
+ usbphy0 = &usbphy0;
+ };
+
+ cpus {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ cpu@0 {
+ compatible = "arm,arm926ej-s";
+ device_type = "cpu";
+ reg = <0>;
+ };
+ };
+
+ apb@80000000 {
+ compatible = "simple-bus";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ reg = <0x80000000 0x80000>;
+ ranges;
+
+ apbh@80000000 {
+ compatible = "simple-bus";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ reg = <0x80000000 0x40000>;
+ ranges;
+
+ icoll: interrupt-controller@80000000 {
+ compatible = "fsl,imx23-icoll", "fsl,icoll";
+ interrupt-controller;
+ #interrupt-cells = <1>;
+ reg = <0x80000000 0x2000>;
+ };
+
+ dma_apbh: dma-apbh@80004000 {
+ compatible = "fsl,imx23-dma-apbh";
+ reg = <0x80004000 0x2000>;
+ interrupts = <0 14 20 0
+ 13 13 13 13>;
+ interrupt-names = "empty", "ssp0", "ssp1", "empty",
+ "gpmi0", "gpmi1", "gpmi2", "gpmi3";
+ #dma-cells = <1>;
+ dma-channels = <8>;
+ clocks = <&clks 15>;
+ };
+
+ ecc@80008000 {
+ reg = <0x80008000 0x2000>;
+ status = "disabled";
+ };
+
+ nand-controller@8000c000 {
+ compatible = "fsl,imx23-gpmi-nand";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ reg = <0x8000c000 0x2000>, <0x8000a000 0x2000>;
+ reg-names = "gpmi-nand", "bch";
+ interrupts = <56>;
+ interrupt-names = "bch";
+ clocks = <&clks 34>;
+ clock-names = "gpmi_io";
+ dmas = <&dma_apbh 4>;
+ dma-names = "rx-tx";
+ status = "disabled";
+ };
+
+ ssp0: spi@80010000 {
+ reg = <0x80010000 0x2000>;
+ interrupts = <15>;
+ clocks = <&clks 33>;
+ dmas = <&dma_apbh 1>;
+ dma-names = "rx-tx";
+ status = "disabled";
+ };
+
+ etm@80014000 {
+ reg = <0x80014000 0x2000>;
+ status = "disabled";
+ };
+
+ pinctrl: pinctrl@80018000 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ compatible = "fsl,imx23-pinctrl", "simple-bus";
+ reg = <0x80018000 0x2000>;
+
+ gpio0: gpio@0 {
+ compatible = "fsl,imx23-gpio", "fsl,mxs-gpio";
+ reg = <0>;
+ interrupts = <16>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+
+ gpio1: gpio@1 {
+ compatible = "fsl,imx23-gpio", "fsl,mxs-gpio";
+ reg = <1>;
+ interrupts = <17>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+
+ gpio2: gpio@2 {
+ compatible = "fsl,imx23-gpio", "fsl,mxs-gpio";
+ reg = <2>;
+ interrupts = <18>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+
+ duart_pins_a: duart@0 {
+ reg = <0>;
+ fsl,pinmux-ids = <
+ MX23_PAD_PWM0__DUART_RX
+ MX23_PAD_PWM1__DUART_TX
+ >;
+ fsl,drive-strength = <MXS_DRIVE_4mA>;
+ fsl,voltage = <MXS_VOLTAGE_HIGH>;
+ fsl,pull-up = <MXS_PULL_DISABLE>;
+ };
+
+ auart0_pins_a: auart0@0 {
+ reg = <0>;
+ fsl,pinmux-ids = <
+ MX23_PAD_AUART1_RX__AUART1_RX
+ MX23_PAD_AUART1_TX__AUART1_TX
+ MX23_PAD_AUART1_CTS__AUART1_CTS
+ MX23_PAD_AUART1_RTS__AUART1_RTS
+ >;
+ fsl,drive-strength = <MXS_DRIVE_4mA>;
+ fsl,voltage = <MXS_VOLTAGE_HIGH>;
+ fsl,pull-up = <MXS_PULL_DISABLE>;
+ };
+
+ auart0_2pins_a: auart0-2pins@0 {
+ reg = <0>;
+ fsl,pinmux-ids = <
+ MX23_PAD_I2C_SCL__AUART1_TX
+ MX23_PAD_I2C_SDA__AUART1_RX
+ >;
+ fsl,drive-strength = <MXS_DRIVE_4mA>;
+ fsl,voltage = <MXS_VOLTAGE_HIGH>;
+ fsl,pull-up = <MXS_PULL_DISABLE>;
+ };
+
+ auart1_2pins_a: auart1-2pins@0 {
+ reg = <0>;
+ fsl,pinmux-ids = <
+ MX23_PAD_GPMI_D14__AUART2_RX
+ MX23_PAD_GPMI_D15__AUART2_TX
+ >;
+ fsl,drive-strength = <MXS_DRIVE_4mA>;
+ fsl,voltage = <MXS_VOLTAGE_HIGH>;
+ fsl,pull-up = <MXS_PULL_DISABLE>;
+ };
+
+ gpmi_pins_a: gpmi-nand@0 {
+ reg = <0>;
+ fsl,pinmux-ids = <
+ MX23_PAD_GPMI_D00__GPMI_D00
+ MX23_PAD_GPMI_D01__GPMI_D01
+ MX23_PAD_GPMI_D02__GPMI_D02
+ MX23_PAD_GPMI_D03__GPMI_D03
+ MX23_PAD_GPMI_D04__GPMI_D04
+ MX23_PAD_GPMI_D05__GPMI_D05
+ MX23_PAD_GPMI_D06__GPMI_D06
+ MX23_PAD_GPMI_D07__GPMI_D07
+ MX23_PAD_GPMI_CLE__GPMI_CLE
+ MX23_PAD_GPMI_ALE__GPMI_ALE
+ MX23_PAD_GPMI_RDY0__GPMI_RDY0
+ MX23_PAD_GPMI_RDY1__GPMI_RDY1
+ MX23_PAD_GPMI_WPN__GPMI_WPN
+ MX23_PAD_GPMI_WRN__GPMI_WRN
+ MX23_PAD_GPMI_RDN__GPMI_RDN
+ MX23_PAD_GPMI_CE1N__GPMI_CE1N
+ MX23_PAD_GPMI_CE0N__GPMI_CE0N
+ >;
+ fsl,drive-strength = <MXS_DRIVE_4mA>;
+ fsl,voltage = <MXS_VOLTAGE_HIGH>;
+ fsl,pull-up = <MXS_PULL_DISABLE>;
+ };
+
+ gpmi_pins_fixup: gpmi-pins-fixup@0 {
+ reg = <0>;
+ fsl,pinmux-ids = <
+ MX23_PAD_GPMI_WPN__GPMI_WPN
+ MX23_PAD_GPMI_WRN__GPMI_WRN
+ MX23_PAD_GPMI_RDN__GPMI_RDN
+ >;
+ fsl,drive-strength = <MXS_DRIVE_12mA>;
+ };
+
+ mmc0_4bit_pins_a: mmc0-4bit@0 {
+ reg = <0>;
+ fsl,pinmux-ids = <
+ MX23_PAD_SSP1_DATA0__SSP1_DATA0
+ MX23_PAD_SSP1_DATA1__SSP1_DATA1
+ MX23_PAD_SSP1_DATA2__SSP1_DATA2
+ MX23_PAD_SSP1_DATA3__SSP1_DATA3
+ MX23_PAD_SSP1_CMD__SSP1_CMD
+ MX23_PAD_SSP1_SCK__SSP1_SCK
+ >;
+ fsl,drive-strength = <MXS_DRIVE_8mA>;
+ fsl,voltage = <MXS_VOLTAGE_HIGH>;
+ fsl,pull-up = <MXS_PULL_ENABLE>;
+ };
+
+ mmc0_8bit_pins_a: mmc0-8bit@0 {
+ reg = <0>;
+ fsl,pinmux-ids = <
+ MX23_PAD_SSP1_DATA0__SSP1_DATA0
+ MX23_PAD_SSP1_DATA1__SSP1_DATA1
+ MX23_PAD_SSP1_DATA2__SSP1_DATA2
+ MX23_PAD_SSP1_DATA3__SSP1_DATA3
+ MX23_PAD_GPMI_D08__SSP1_DATA4
+ MX23_PAD_GPMI_D09__SSP1_DATA5
+ MX23_PAD_GPMI_D10__SSP1_DATA6
+ MX23_PAD_GPMI_D11__SSP1_DATA7
+ MX23_PAD_SSP1_CMD__SSP1_CMD
+ MX23_PAD_SSP1_DETECT__SSP1_DETECT
+ MX23_PAD_SSP1_SCK__SSP1_SCK
+ >;
+ fsl,drive-strength = <MXS_DRIVE_8mA>;
+ fsl,voltage = <MXS_VOLTAGE_HIGH>;
+ fsl,pull-up = <MXS_PULL_ENABLE>;
+ };
+
+ mmc0_pins_fixup: mmc0-pins-fixup@0 {
+ reg = <0>;
+ fsl,pinmux-ids = <
+ MX23_PAD_SSP1_DETECT__SSP1_DETECT
+ MX23_PAD_SSP1_SCK__SSP1_SCK
+ >;
+ fsl,pull-up = <MXS_PULL_DISABLE>;
+ };
+
+ mmc0_sck_cfg: mmc0-sck-cfg@0 {
+ reg = <0>;
+ fsl,pinmux-ids = <
+ MX23_PAD_SSP1_SCK__SSP1_SCK
+ >;
+ fsl,pull-up = <MXS_PULL_DISABLE>;
+ };
+
+ mmc1_4bit_pins_a: mmc1-4bit@0 {
+ reg = <0>;
+ fsl,pinmux-ids = <
+ MX23_PAD_GPMI_D00__SSP2_DATA0
+ MX23_PAD_GPMI_D01__SSP2_DATA1
+ MX23_PAD_GPMI_D02__SSP2_DATA2
+ MX23_PAD_GPMI_D03__SSP2_DATA3
+ MX23_PAD_GPMI_RDY1__SSP2_CMD
+ MX23_PAD_GPMI_WRN__SSP2_SCK
+ >;
+ fsl,drive-strength = <MXS_DRIVE_8mA>;
+ fsl,voltage = <MXS_VOLTAGE_HIGH>;
+ fsl,pull-up = <MXS_PULL_ENABLE>;
+ };
+
+ mmc1_8bit_pins_a: mmc1-8bit@0 {
+ reg = <0>;
+ fsl,pinmux-ids = <
+ MX23_PAD_GPMI_D00__SSP2_DATA0
+ MX23_PAD_GPMI_D01__SSP2_DATA1
+ MX23_PAD_GPMI_D02__SSP2_DATA2
+ MX23_PAD_GPMI_D03__SSP2_DATA3
+ MX23_PAD_GPMI_D04__SSP2_DATA4
+ MX23_PAD_GPMI_D05__SSP2_DATA5
+ MX23_PAD_GPMI_D06__SSP2_DATA6
+ MX23_PAD_GPMI_D07__SSP2_DATA7
+ MX23_PAD_GPMI_RDY1__SSP2_CMD
+ MX23_PAD_GPMI_WRN__SSP2_SCK
+ >;
+ fsl,drive-strength = <MXS_DRIVE_8mA>;
+ fsl,voltage = <MXS_VOLTAGE_HIGH>;
+ fsl,pull-up = <MXS_PULL_ENABLE>;
+ };
+
+ pwm2_pins_a: pwm2@0 {
+ reg = <0>;
+ fsl,pinmux-ids = <
+ MX23_PAD_PWM2__PWM2
+ >;
+ fsl,drive-strength = <MXS_DRIVE_4mA>;
+ fsl,voltage = <MXS_VOLTAGE_HIGH>;
+ fsl,pull-up = <MXS_PULL_DISABLE>;
+ };
+
+ lcdif_24bit_pins_a: lcdif-24bit@0 {
+ reg = <0>;
+ fsl,pinmux-ids = <
+ MX23_PAD_LCD_D00__LCD_D00
+ MX23_PAD_LCD_D01__LCD_D01
+ MX23_PAD_LCD_D02__LCD_D02
+ MX23_PAD_LCD_D03__LCD_D03
+ MX23_PAD_LCD_D04__LCD_D04
+ MX23_PAD_LCD_D05__LCD_D05
+ MX23_PAD_LCD_D06__LCD_D06
+ MX23_PAD_LCD_D07__LCD_D07
+ MX23_PAD_LCD_D08__LCD_D08
+ MX23_PAD_LCD_D09__LCD_D09
+ MX23_PAD_LCD_D10__LCD_D10
+ MX23_PAD_LCD_D11__LCD_D11
+ MX23_PAD_LCD_D12__LCD_D12
+ MX23_PAD_LCD_D13__LCD_D13
+ MX23_PAD_LCD_D14__LCD_D14
+ MX23_PAD_LCD_D15__LCD_D15
+ MX23_PAD_LCD_D16__LCD_D16
+ MX23_PAD_LCD_D17__LCD_D17
+ MX23_PAD_GPMI_D08__LCD_D18
+ MX23_PAD_GPMI_D09__LCD_D19
+ MX23_PAD_GPMI_D10__LCD_D20
+ MX23_PAD_GPMI_D11__LCD_D21
+ MX23_PAD_GPMI_D12__LCD_D22
+ MX23_PAD_GPMI_D13__LCD_D23
+ MX23_PAD_LCD_DOTCK__LCD_DOTCK
+ MX23_PAD_LCD_ENABLE__LCD_ENABLE
+ MX23_PAD_LCD_HSYNC__LCD_HSYNC
+ MX23_PAD_LCD_VSYNC__LCD_VSYNC
+ >;
+ fsl,drive-strength = <MXS_DRIVE_4mA>;
+ fsl,voltage = <MXS_VOLTAGE_HIGH>;
+ fsl,pull-up = <MXS_PULL_DISABLE>;
+ };
+
+ spi2_pins_a: spi2@0 {
+ reg = <0>;
+ fsl,pinmux-ids = <
+ MX23_PAD_GPMI_WRN__SSP2_SCK
+ MX23_PAD_GPMI_RDY1__SSP2_CMD
+ MX23_PAD_GPMI_D00__SSP2_DATA0
+ MX23_PAD_GPMI_D03__SSP2_DATA3
+ >;
+ fsl,drive-strength = <MXS_DRIVE_8mA>;
+ fsl,voltage = <MXS_VOLTAGE_HIGH>;
+ fsl,pull-up = <MXS_PULL_ENABLE>;
+ };
+
+ i2c_pins_a: i2c@0 {
+ reg = <0>;
+ fsl,pinmux-ids = <
+ MX23_PAD_I2C_SCL__I2C_SCL
+ MX23_PAD_I2C_SDA__I2C_SDA
+ >;
+ fsl,drive-strength = <MXS_DRIVE_8mA>;
+ fsl,voltage = <MXS_VOLTAGE_HIGH>;
+ fsl,pull-up = <MXS_PULL_ENABLE>;
+ };
+
+ i2c_pins_b: i2c@1 {
+ reg = <1>;
+ fsl,pinmux-ids = <
+ MX23_PAD_LCD_ENABLE__I2C_SCL
+ MX23_PAD_LCD_HSYNC__I2C_SDA
+ >;
+ fsl,drive-strength = <MXS_DRIVE_8mA>;
+ fsl,voltage = <MXS_VOLTAGE_HIGH>;
+ fsl,pull-up = <MXS_PULL_ENABLE>;
+ };
+
+ i2c_pins_c: i2c@2 {
+ reg = <2>;
+ fsl,pinmux-ids = <
+ MX23_PAD_SSP1_DATA1__I2C_SCL
+ MX23_PAD_SSP1_DATA2__I2C_SDA
+ >;
+ fsl,drive-strength = <MXS_DRIVE_8mA>;
+ fsl,voltage = <MXS_VOLTAGE_HIGH>;
+ fsl,pull-up = <MXS_PULL_ENABLE>;
+ };
+ };
+
+ digctl@8001c000 {
+ compatible = "fsl,imx23-digctl";
+ reg = <0x8001c000 2000>;
+ status = "disabled";
+ };
+
+ emi@80020000 {
+ reg = <0x80020000 0x2000>;
+ status = "disabled";
+ };
+
+ dma_apbx: dma-apbx@80024000 {
+ compatible = "fsl,imx23-dma-apbx";
+ reg = <0x80024000 0x2000>;
+ interrupts = <7 5 9 26
+ 19 0 25 23
+ 60 58 9 0
+ 0 0 0 0>;
+ interrupt-names = "audio-adc", "audio-dac", "spdif-tx", "i2c",
+ "saif0", "empty", "auart0-rx", "auart0-tx",
+ "auart1-rx", "auart1-tx", "saif1", "empty",
+ "empty", "empty", "empty", "empty";
+ #dma-cells = <1>;
+ dma-channels = <16>;
+ clocks = <&clks 16>;
+ };
+
+ dcp: crypto@80028000 {
+ compatible = "fsl,imx23-dcp";
+ reg = <0x80028000 0x2000>;
+ interrupts = <53 54>;
+ status = "okay";
+ };
+
+ pxp@8002a000 {
+ reg = <0x8002a000 0x2000>;
+ status = "disabled";
+ };
+
+ efuse@8002c000 {
+ compatible = "fsl,imx23-ocotp", "fsl,ocotp";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ reg = <0x8002c000 0x2000>;
+ clocks = <&clks 15>;
+ };
+
+ axi-ahb@8002e000 {
+ reg = <0x8002e000 0x2000>;
+ status = "disabled";
+ };
+
+ lcdif@80030000 {
+ compatible = "fsl,imx23-lcdif";
+ reg = <0x80030000 2000>;
+ interrupts = <46 45>;
+ clocks = <&clks 38>;
+ status = "disabled";
+ };
+
+ ssp1: spi@80034000 {
+ reg = <0x80034000 0x2000>;
+ interrupts = <2>;
+ clocks = <&clks 33>;
+ dmas = <&dma_apbh 2>;
+ dma-names = "rx-tx";
+ status = "disabled";
+ };
+
+ tvenc@80038000 {
+ reg = <0x80038000 0x2000>;
+ status = "disabled";
+ };
+ };
+
+ apbx@80040000 {
+ compatible = "simple-bus";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ reg = <0x80040000 0x40000>;
+ ranges;
+
+ clks: clkctrl@80040000 {
+ compatible = "fsl,imx23-clkctrl", "fsl,clkctrl";
+ reg = <0x80040000 0x2000>;
+ #clock-cells = <1>;
+ };
+
+ saif0: saif@80042000 {
+ reg = <0x80042000 0x2000>;
+ dmas = <&dma_apbx 4>;
+ dma-names = "rx-tx";
+ status = "disabled";
+ };
+
+ power@80044000 {
+ reg = <0x80044000 0x2000>;
+ status = "disabled";
+ };
+
+ saif1: saif@80046000 {
+ reg = <0x80046000 0x2000>;
+ dmas = <&dma_apbx 10>;
+ dma-names = "rx-tx";
+ status = "disabled";
+ };
+
+ audio-out@80048000 {
+ reg = <0x80048000 0x2000>;
+ dmas = <&dma_apbx 1>;
+ dma-names = "tx";
+ status = "disabled";
+ };
+
+ audio-in@8004c000 {
+ reg = <0x8004c000 0x2000>;
+ dmas = <&dma_apbx 0>;
+ dma-names = "rx";
+ status = "disabled";
+ };
+
+ lradc: lradc@80050000 {
+ compatible = "fsl,imx23-lradc";
+ reg = <0x80050000 0x2000>;
+ interrupts = <36 37 38 39 40 41 42 43 44>;
+ status = "disabled";
+ clocks = <&clks 26>;
+ #io-channel-cells = <1>;
+ };
+
+ spdif@80054000 {
+ reg = <0x80054000 2000>;
+ dmas = <&dma_apbx 2>;
+ dma-names = "tx";
+ status = "disabled";
+ };
+
+ i2c: i2c@80058000 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ compatible = "fsl,imx23-i2c";
+ reg = <0x80058000 0x2000>;
+ interrupts = <27>;
+ clock-frequency = <100000>;
+ dmas = <&dma_apbx 3>;
+ dma-names = "rx-tx";
+ status = "disabled";
+ };
+
+ rtc@8005c000 {
+ compatible = "fsl,imx23-rtc", "fsl,stmp3xxx-rtc";
+ reg = <0x8005c000 0x2000>;
+ interrupts = <22>;
+ };
+
+ pwm: pwm@80064000 {
+ compatible = "fsl,imx23-pwm";
+ reg = <0x80064000 0x2000>;
+ clocks = <&clks 30>;
+ #pwm-cells = <2>;
+ fsl,pwm-number = <5>;
+ status = "disabled";
+ };
+
+ timrot@80068000 {
+ compatible = "fsl,imx23-timrot", "fsl,timrot";
+ reg = <0x80068000 0x2000>;
+ interrupts = <28 29 30 31>;
+ clocks = <&clks 28>;
+ };
+
+ auart0: serial@8006c000 {
+ compatible = "fsl,imx23-auart";
+ reg = <0x8006c000 0x2000>;
+ interrupts = <24>;
+ clocks = <&clks 32>;
+ dmas = <&dma_apbx 6>, <&dma_apbx 7>;
+ dma-names = "rx", "tx";
+ status = "disabled";
+ };
+
+ auart1: serial@8006e000 {
+ compatible = "fsl,imx23-auart";
+ reg = <0x8006e000 0x2000>;
+ interrupts = <59>;
+ clocks = <&clks 32>;
+ dmas = <&dma_apbx 8>, <&dma_apbx 9>;
+ dma-names = "rx", "tx";
+ status = "disabled";
+ };
+
+ duart: serial@80070000 {
+ compatible = "arm,pl011", "arm,primecell";
+ reg = <0x80070000 0x2000>;
+ interrupts = <0>;
+ clocks = <&clks 32>, <&clks 16>;
+ clock-names = "uart", "apb_pclk";
+ status = "disabled";
+ };
+
+ usbphy0: usbphy@8007c000 {
+ compatible = "fsl,imx23-usbphy";
+ reg = <0x8007c000 0x2000>;
+ clocks = <&clks 41>;
+ status = "disabled";
+ };
+ };
+ };
+
+ ahb@80080000 {
+ compatible = "simple-bus";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ reg = <0x80080000 0x80000>;
+ ranges;
+
+ usb0: usb@80080000 {
+ compatible = "fsl,imx23-usb", "fsl,imx27-usb";
+ reg = <0x80080000 0x40000>;
+ interrupts = <11>;
+ fsl,usbphy = <&usbphy0>;
+ clocks = <&clks 40>;
+ status = "disabled";
+ };
+ };
+
+ iio-hwmon {
+ compatible = "iio-hwmon";
+ io-channels = <&lradc 8>;
+ };
+};
diff --git a/arch/arm/dts/imx51-babbage.dts b/arch/arm/dts/imx51-babbage.dts
new file mode 100644
index 0000000..552196d
--- /dev/null
+++ b/arch/arm/dts/imx51-babbage.dts
@@ -0,0 +1,726 @@
+// SPDX-License-Identifier: GPL-2.0+
+//
+// Copyright 2011 Freescale Semiconductor, Inc.
+// Copyright 2011 Linaro Ltd.
+
+/dts-v1/;
+#include "imx51.dtsi"
+
+/ {
+ model = "Freescale i.MX51 Babbage Board";
+ compatible = "fsl,imx51-babbage", "fsl,imx51";
+
+ chosen {
+ stdout-path = &uart1;
+ };
+
+ memory@90000000 {
+ device_type = "memory";
+ reg = <0x90000000 0x20000000>;
+ };
+
+ ckih1 {
+ clock-frequency = <22579200>;
+ };
+
+ clk_osc: clk-osc {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <26000000>;
+ };
+
+ clk_osc_gate: clk-osc-gate {
+ compatible = "gpio-gate-clock";
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_clk26mhz_osc>;
+ clocks = <&clk_osc>;
+ #clock-cells = <0>;
+ enable-gpios = <&gpio3 1 GPIO_ACTIVE_HIGH>;
+ };
+
+ clk_audio: clk-audio {
+ compatible = "gpio-gate-clock";
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_clk26mhz_audio>;
+ clocks = <&clk_osc_gate>;
+ #clock-cells = <0>;
+ enable-gpios = <&gpio4 26 GPIO_ACTIVE_LOW>;
+ };
+
+ clk_usb: clk-usb {
+ compatible = "gpio-gate-clock";
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_clk26mhz_usb>;
+ clocks = <&clk_osc_gate>;
+ #clock-cells = <0>;
+ enable-gpios = <&gpio2 1 GPIO_ACTIVE_LOW>;
+ };
+
+ display1: disp1 {
+ compatible = "fsl,imx-parallel-display";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ interface-pix-fmt = "rgb24";
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_ipu_disp1>;
+
+ port@0 {
+ reg = <0>;
+
+ display0_in: endpoint {
+ remote-endpoint = <&ipu_di0_disp1>;
+ };
+ };
+
+ port@1 {
+ reg = <1>;
+
+ parallel_display_out: endpoint {
+ remote-endpoint = <&tfp410_in>;
+ };
+ };
+ };
+
+ display2: disp2 {
+ compatible = "fsl,imx-parallel-display";
+ interface-pix-fmt = "rgb565";
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_ipu_disp2>;
+ status = "disabled";
+ display-timings {
+ native-mode = <&timing1>;
+ timing1: claawvga {
+ clock-frequency = <27000000>;
+ hactive = <800>;
+ vactive = <480>;
+ hback-porch = <40>;
+ hfront-porch = <60>;
+ vback-porch = <10>;
+ vfront-porch = <10>;
+ hsync-len = <20>;
+ vsync-len = <10>;
+ hsync-active = <0>;
+ vsync-active = <0>;
+ de-active = <1>;
+ pixelclk-active = <0>;
+ };
+ };
+
+ port {
+ display1_in: endpoint {
+ remote-endpoint = <&ipu_di1_disp2>;
+ };
+ };
+ };
+
+ dvi-connector {
+ compatible = "dvi-connector";
+ digital;
+
+ port {
+ dvi_connector_in: endpoint {
+ remote-endpoint = <&tfp410_out>;
+ };
+ };
+ };
+
+ dvi-encoder {
+ compatible = "ti,tfp410";
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+
+ tfp410_in: endpoint {
+ remote-endpoint = <¶llel_display_out>;
+ };
+ };
+
+ port@1 {
+ reg = <1>;
+
+ tfp410_out: endpoint {
+ remote-endpoint = <&dvi_connector_in>;
+ };
+ };
+ };
+ };
+
+ gpio-keys {
+ compatible = "gpio-keys";
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_gpio_keys>;
+
+ power {
+ label = "Power Button";
+ gpios = <&gpio2 21 GPIO_ACTIVE_HIGH>;
+ linux,code = <KEY_POWER>;
+ wakeup-source;
+ };
+ };
+
+ leds {
+ compatible = "gpio-leds";
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_gpio_leds>;
+
+ led-diagnostic {
+ label = "diagnostic";
+ gpios = <&gpio2 6 GPIO_ACTIVE_HIGH>;
+ };
+ };
+
+ regulators {
+ compatible = "simple-bus";
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ reg_hub_reset: regulator@0 {
+ compatible = "regulator-fixed";
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_usbotgreg>;
+ reg = <0>;
+ regulator-name = "hub_reset";
+ regulator-min-microvolt = <5000000>;
+ regulator-max-microvolt = <5000000>;
+ gpio = <&gpio1 7 GPIO_ACTIVE_HIGH>;
+ enable-active-high;
+ };
+ };
+
+ sound {
+ compatible = "fsl,imx51-babbage-sgtl5000",
+ "fsl,imx-audio-sgtl5000";
+ model = "imx51-babbage-sgtl5000";
+ ssi-controller = <&ssi2>;
+ audio-codec = <&sgtl5000>;
+ audio-routing =
+ "MIC_IN", "Mic Jack",
+ "Mic Jack", "Mic Bias",
+ "Headphone Jack", "HP_OUT";
+ mux-int-port = <2>;
+ mux-ext-port = <3>;
+ };
+
+ usbphy1: usbphy1 {
+ compatible = "usb-nop-xceiv";
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_usbh1reg>;
+ clocks = <&clk_usb>;
+ clock-names = "main_clk";
+ reset-gpios = <&gpio2 5 GPIO_ACTIVE_LOW>;
+ vcc-supply = <&vusb_reg>;
+ #phy-cells = <0>;
+ };
+};
+
+&audmux {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_audmux>;
+ status = "okay";
+};
+
+&ecspi1 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_ecspi1>;
+ cs-gpios = <&gpio4 24 GPIO_ACTIVE_HIGH>,
+ <&gpio4 25 GPIO_ACTIVE_LOW>;
+ status = "okay";
+
+ pmic: mc13892@0 {
+ compatible = "fsl,mc13892";
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_pmic>;
+ spi-max-frequency = <6000000>;
+ spi-cs-high;
+ reg = <0>;
+ interrupt-parent = <&gpio1>;
+ interrupts = <8 IRQ_TYPE_LEVEL_HIGH>;
+ fsl,mc13xxx-uses-adc;
+ fsl,mc13xxx-uses-rtc;
+
+ regulators {
+ sw1_reg: sw1 {
+ regulator-min-microvolt = <600000>;
+ regulator-max-microvolt = <1375000>;
+ regulator-boot-on;
+ regulator-always-on;
+ };
+
+ sw2_reg: sw2 {
+ regulator-min-microvolt = <900000>;
+ regulator-max-microvolt = <1850000>;
+ regulator-boot-on;
+ regulator-always-on;
+ };
+
+ sw3_reg: sw3 {
+ regulator-min-microvolt = <1100000>;
+ regulator-max-microvolt = <1850000>;
+ regulator-boot-on;
+ regulator-always-on;
+ };
+
+ sw4_reg: sw4 {
+ regulator-min-microvolt = <1100000>;
+ regulator-max-microvolt = <1850000>;
+ regulator-boot-on;
+ regulator-always-on;
+ };
+
+ vpll_reg: vpll {
+ regulator-min-microvolt = <1050000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-boot-on;
+ regulator-always-on;
+ };
+
+ vdig_reg: vdig {
+ regulator-min-microvolt = <1650000>;
+ regulator-max-microvolt = <1650000>;
+ regulator-boot-on;
+ };
+
+ vsd_reg: vsd {
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <3150000>;
+ };
+
+ vusb_reg: vusb {
+ regulator-boot-on;
+ };
+
+ vusb2_reg: vusb2 {
+ regulator-min-microvolt = <2400000>;
+ regulator-max-microvolt = <2775000>;
+ regulator-boot-on;
+ regulator-always-on;
+ };
+
+ vvideo_reg: vvideo {
+ regulator-min-microvolt = <2775000>;
+ regulator-max-microvolt = <2775000>;
+ };
+
+ vaudio_reg: vaudio {
+ regulator-min-microvolt = <2300000>;
+ regulator-max-microvolt = <3000000>;
+ };
+
+ vcam_reg: vcam {
+ regulator-min-microvolt = <2500000>;
+ regulator-max-microvolt = <3000000>;
+ };
+
+ vgen1_reg: vgen1 {
+ regulator-min-microvolt = <1200000>;
+ regulator-max-microvolt = <1200000>;
+ };
+
+ vgen2_reg: vgen2 {
+ regulator-min-microvolt = <1200000>;
+ regulator-max-microvolt = <3150000>;
+ regulator-always-on;
+ };
+
+ vgen3_reg: vgen3 {
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <2900000>;
+ regulator-always-on;
+ };
+ };
+ };
+
+ flash: at45db321d@1 {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ compatible = "atmel,at45db321d", "atmel,at45", "atmel,dataflash";
+ spi-max-frequency = <25000000>;
+ reg = <1>;
+
+ partition@0 {
+ label = "U-Boot";
+ reg = <0x0 0x40000>;
+ read-only;
+ };
+
+ partition@40000 {
+ label = "Kernel";
+ reg = <0x40000 0x3c0000>;
+ };
+ };
+};
+
+&esdhc1 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_esdhc1>;
+ cd-gpios = <&gpio1 0 GPIO_ACTIVE_LOW>;
+ wp-gpios = <&gpio1 1 GPIO_ACTIVE_HIGH>;
+ status = "okay";
+};
+
+&esdhc2 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_esdhc2>;
+ cd-gpios = <&gpio1 6 GPIO_ACTIVE_LOW>;
+ wp-gpios = <&gpio1 5 GPIO_ACTIVE_HIGH>;
+ status = "okay";
+};
+
+&fec {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_fec>;
+ phy-mode = "mii";
+ phy-reset-gpios = <&gpio2 14 GPIO_ACTIVE_LOW>;
+ phy-reset-duration = <1>;
+ status = "okay";
+};
+
+&i2c1 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_i2c1>;
+ status = "okay";
+};
+
+&i2c2 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_i2c2>;
+ status = "okay";
+
+ sgtl5000: codec@a {
+ compatible = "fsl,sgtl5000";
+ reg = <0x0a>;
+ #sound-dai-cells = <0>;
+ clocks = <&clk_audio>;
+ VDDA-supply = <&vdig_reg>;
+ VDDIO-supply = <&vvideo_reg>;
+ };
+};
+
+&ipu_di0_disp1 {
+ remote-endpoint = <&display0_in>;
+};
+
+&ipu_di1_disp2 {
+ remote-endpoint = <&display1_in>;
+};
+
+&kpp {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_kpp>;
+ linux,keymap = <
+ MATRIX_KEY(0, 0, KEY_UP)
+ MATRIX_KEY(0, 1, KEY_DOWN)
+ MATRIX_KEY(0, 2, KEY_VOLUMEDOWN)
+ MATRIX_KEY(0, 3, KEY_HOME)
+ MATRIX_KEY(1, 0, KEY_RIGHT)
+ MATRIX_KEY(1, 1, KEY_LEFT)
+ MATRIX_KEY(1, 2, KEY_ENTER)
+ MATRIX_KEY(1, 3, KEY_VOLUMEUP)
+ MATRIX_KEY(2, 0, KEY_F6)
+ MATRIX_KEY(2, 1, KEY_F8)
+ MATRIX_KEY(2, 2, KEY_F9)
+ MATRIX_KEY(2, 3, KEY_F10)
+ MATRIX_KEY(3, 0, KEY_F1)
+ MATRIX_KEY(3, 1, KEY_F2)
+ MATRIX_KEY(3, 2, KEY_F3)
+ MATRIX_KEY(3, 3, KEY_POWER)
+ >;
+ status = "okay";
+};
+
+&pmu {
+ secure-reg-access;
+};
+
+&ssi2 {
+ status = "okay";
+};
+
+&uart1 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_uart1>;
+ uart-has-rtscts;
+ status = "okay";
+};
+
+&uart2 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_uart2>;
+ status = "okay";
+};
+
+&uart3 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_uart3>;
+ uart-has-rtscts;
+ status = "okay";
+};
+
+&usbh1 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_usbh1>;
+ vbus-supply = <®_hub_reset>;
+ fsl,usbphy = <&usbphy1>;
+ phy_type = "ulpi";
+ status = "okay";
+};
+
+&usbphy0 {
+ vcc-supply = <&vusb_reg>;
+};
+
+&usbotg {
+ dr_mode = "otg";
+ disable-over-current;
+ phy_type = "utmi_wide";
+ status = "okay";
+};
+
+&iomuxc {
+ imx51-babbage {
+ pinctrl_audmux: audmuxgrp {
+ fsl,pins = <
+ MX51_PAD_AUD3_BB_TXD__AUD3_TXD 0x80000000
+ MX51_PAD_AUD3_BB_RXD__AUD3_RXD 0x80000000
+ MX51_PAD_AUD3_BB_CK__AUD3_TXC 0x80000000
+ MX51_PAD_AUD3_BB_FS__AUD3_TXFS 0x80000000
+ >;
+ };
+
+ pinctrl_clk26mhz_audio: clk26mhzaudiocgrp {
+ fsl,pins = <
+ MX51_PAD_CSPI1_RDY__GPIO4_26 0x85
+ >;
+ };
+
+ pinctrl_clk26mhz_osc: clk26mhzoscgrp {
+ fsl,pins = <
+ MX51_PAD_DI1_PIN12__GPIO3_1 0x85
+ >;
+ };
+
+ pinctrl_clk26mhz_usb: clk26mhzusbgrp {
+ fsl,pins = <
+ MX51_PAD_EIM_D17__GPIO2_1 0x85
+ >;
+ };
+
+ pinctrl_ecspi1: ecspi1grp {
+ fsl,pins = <
+ MX51_PAD_CSPI1_MISO__ECSPI1_MISO 0x185
+ MX51_PAD_CSPI1_MOSI__ECSPI1_MOSI 0x185
+ MX51_PAD_CSPI1_SCLK__ECSPI1_SCLK 0x185
+ MX51_PAD_CSPI1_SS0__GPIO4_24 0x85 /* CS0 */
+ MX51_PAD_CSPI1_SS1__GPIO4_25 0x85 /* CS1 */
+ >;
+ };
+
+ pinctrl_esdhc1: esdhc1grp {
+ fsl,pins = <
+ MX51_PAD_SD1_CMD__SD1_CMD 0x400020d5
+ MX51_PAD_SD1_CLK__SD1_CLK 0x20d5
+ MX51_PAD_SD1_DATA0__SD1_DATA0 0x20d5
+ MX51_PAD_SD1_DATA1__SD1_DATA1 0x20d5
+ MX51_PAD_SD1_DATA2__SD1_DATA2 0x20d5
+ MX51_PAD_SD1_DATA3__SD1_DATA3 0x20d5
+ MX51_PAD_GPIO1_0__GPIO1_0 0x100
+ MX51_PAD_GPIO1_1__GPIO1_1 0x100
+ >;
+ };
+
+ pinctrl_esdhc2: esdhc2grp {
+ fsl,pins = <
+ MX51_PAD_SD2_CMD__SD2_CMD 0x400020d5
+ MX51_PAD_SD2_CLK__SD2_CLK 0x20d5
+ MX51_PAD_SD2_DATA0__SD2_DATA0 0x20d5
+ MX51_PAD_SD2_DATA1__SD2_DATA1 0x20d5
+ MX51_PAD_SD2_DATA2__SD2_DATA2 0x20d5
+ MX51_PAD_SD2_DATA3__SD2_DATA3 0x20d5
+ MX51_PAD_GPIO1_5__GPIO1_5 0x100 /* WP */
+ MX51_PAD_GPIO1_6__GPIO1_6 0x100 /* CD */
+ >;
+ };
+
+ pinctrl_fec: fecgrp {
+ fsl,pins = <
+ MX51_PAD_EIM_EB2__FEC_MDIO 0x000001f5
+ MX51_PAD_EIM_EB3__FEC_RDATA1 0x00000085
+ MX51_PAD_EIM_CS2__FEC_RDATA2 0x00000085
+ MX51_PAD_EIM_CS3__FEC_RDATA3 0x00000085
+ MX51_PAD_EIM_CS4__FEC_RX_ER 0x00000180
+ MX51_PAD_EIM_CS5__FEC_CRS 0x00000180
+ MX51_PAD_NANDF_RB2__FEC_COL 0x00000180
+ MX51_PAD_NANDF_RB3__FEC_RX_CLK 0x00000180
+ MX51_PAD_NANDF_D9__FEC_RDATA0 0x00002180
+ MX51_PAD_NANDF_D8__FEC_TDATA0 0x00002004
+ MX51_PAD_NANDF_CS2__FEC_TX_ER 0x00002004
+ MX51_PAD_NANDF_CS3__FEC_MDC 0x00002004
+ MX51_PAD_NANDF_CS4__FEC_TDATA1 0x00002004
+ MX51_PAD_NANDF_CS5__FEC_TDATA2 0x00002004
+ MX51_PAD_NANDF_CS6__FEC_TDATA3 0x00002004
+ MX51_PAD_NANDF_CS7__FEC_TX_EN 0x00002004
+ MX51_PAD_NANDF_RDY_INT__FEC_TX_CLK 0x00002180
+ MX51_PAD_NANDF_D11__FEC_RX_DV 0x000020a4
+ MX51_PAD_EIM_A20__GPIO2_14 0x00000085 /* Phy Reset */
+ >;
+ };
+
+ pinctrl_gpio_keys: gpiokeysgrp {
+ fsl,pins = <
+ MX51_PAD_EIM_A27__GPIO2_21 0x5
+ >;
+ };
+
+ pinctrl_gpio_leds: gpioledsgrp {
+ fsl,pins = <
+ MX51_PAD_EIM_D22__GPIO2_6 0x80000000
+ >;
+ };
+
+ pinctrl_i2c1: i2c1grp {
+ fsl,pins = <
+ MX51_PAD_EIM_D19__I2C1_SCL 0x400001ed
+ MX51_PAD_EIM_D16__I2C1_SDA 0x400001ed
+ >;
+ };
+
+ pinctrl_i2c2: i2c2grp {
+ fsl,pins = <
+ MX51_PAD_KEY_COL4__I2C2_SCL 0x400001ed
+ MX51_PAD_KEY_COL5__I2C2_SDA 0x400001ed
+ >;
+ };
+
+ pinctrl_ipu_disp1: ipudisp1grp {
+ fsl,pins = <
+ MX51_PAD_DISP1_DAT0__DISP1_DAT0 0x5
+ MX51_PAD_DISP1_DAT1__DISP1_DAT1 0x5
+ MX51_PAD_DISP1_DAT2__DISP1_DAT2 0x5
+ MX51_PAD_DISP1_DAT3__DISP1_DAT3 0x5
+ MX51_PAD_DISP1_DAT4__DISP1_DAT4 0x5
+ MX51_PAD_DISP1_DAT5__DISP1_DAT5 0x5
+ MX51_PAD_DISP1_DAT6__DISP1_DAT6 0x5
+ MX51_PAD_DISP1_DAT7__DISP1_DAT7 0x5
+ MX51_PAD_DISP1_DAT8__DISP1_DAT8 0x5
+ MX51_PAD_DISP1_DAT9__DISP1_DAT9 0x5
+ MX51_PAD_DISP1_DAT10__DISP1_DAT10 0x5
+ MX51_PAD_DISP1_DAT11__DISP1_DAT11 0x5
+ MX51_PAD_DISP1_DAT12__DISP1_DAT12 0x5
+ MX51_PAD_DISP1_DAT13__DISP1_DAT13 0x5
+ MX51_PAD_DISP1_DAT14__DISP1_DAT14 0x5
+ MX51_PAD_DISP1_DAT15__DISP1_DAT15 0x5
+ MX51_PAD_DISP1_DAT16__DISP1_DAT16 0x5
+ MX51_PAD_DISP1_DAT17__DISP1_DAT17 0x5
+ MX51_PAD_DISP1_DAT18__DISP1_DAT18 0x5
+ MX51_PAD_DISP1_DAT19__DISP1_DAT19 0x5
+ MX51_PAD_DISP1_DAT20__DISP1_DAT20 0x5
+ MX51_PAD_DISP1_DAT21__DISP1_DAT21 0x5
+ MX51_PAD_DISP1_DAT22__DISP1_DAT22 0x5
+ MX51_PAD_DISP1_DAT23__DISP1_DAT23 0x5
+ MX51_PAD_DI1_PIN2__DI1_PIN2 0x5
+ MX51_PAD_DI1_PIN3__DI1_PIN3 0x5
+ >;
+ };
+
+ pinctrl_ipu_disp2: ipudisp2grp {
+ fsl,pins = <
+ MX51_PAD_DISP2_DAT0__DISP2_DAT0 0x5
+ MX51_PAD_DISP2_DAT1__DISP2_DAT1 0x5
+ MX51_PAD_DISP2_DAT2__DISP2_DAT2 0x5
+ MX51_PAD_DISP2_DAT3__DISP2_DAT3 0x5
+ MX51_PAD_DISP2_DAT4__DISP2_DAT4 0x5
+ MX51_PAD_DISP2_DAT5__DISP2_DAT5 0x5
+ MX51_PAD_DISP2_DAT6__DISP2_DAT6 0x5
+ MX51_PAD_DISP2_DAT7__DISP2_DAT7 0x5
+ MX51_PAD_DISP2_DAT8__DISP2_DAT8 0x5
+ MX51_PAD_DISP2_DAT9__DISP2_DAT9 0x5
+ MX51_PAD_DISP2_DAT10__DISP2_DAT10 0x5
+ MX51_PAD_DISP2_DAT11__DISP2_DAT11 0x5
+ MX51_PAD_DISP2_DAT12__DISP2_DAT12 0x5
+ MX51_PAD_DISP2_DAT13__DISP2_DAT13 0x5
+ MX51_PAD_DISP2_DAT14__DISP2_DAT14 0x5
+ MX51_PAD_DISP2_DAT15__DISP2_DAT15 0x5
+ MX51_PAD_DI2_PIN2__DI2_PIN2 0x5
+ MX51_PAD_DI2_PIN3__DI2_PIN3 0x5
+ MX51_PAD_DI2_DISP_CLK__DI2_DISP_CLK 0x5
+ MX51_PAD_DI_GP4__DI2_PIN15 0x5
+ >;
+ };
+
+ pinctrl_kpp: kppgrp {
+ fsl,pins = <
+ MX51_PAD_KEY_ROW0__KEY_ROW0 0xe0
+ MX51_PAD_KEY_ROW1__KEY_ROW1 0xe0
+ MX51_PAD_KEY_ROW2__KEY_ROW2 0xe0
+ MX51_PAD_KEY_ROW3__KEY_ROW3 0xe0
+ MX51_PAD_KEY_COL0__KEY_COL0 0xe8
+ MX51_PAD_KEY_COL1__KEY_COL1 0xe8
+ MX51_PAD_KEY_COL2__KEY_COL2 0xe8
+ MX51_PAD_KEY_COL3__KEY_COL3 0xe8
+ >;
+ };
+
+ pinctrl_pmic: pmicgrp {
+ fsl,pins = <
+ MX51_PAD_GPIO1_8__GPIO1_8 0xe5 /* IRQ */
+ >;
+ };
+
+ pinctrl_uart1: uart1grp {
+ fsl,pins = <
+ MX51_PAD_UART1_RXD__UART1_RXD 0x1c5
+ MX51_PAD_UART1_TXD__UART1_TXD 0x1c5
+ MX51_PAD_UART1_RTS__UART1_RTS 0x1c5
+ MX51_PAD_UART1_CTS__UART1_CTS 0x1c5
+ >;
+ };
+
+ pinctrl_uart2: uart2grp {
+ fsl,pins = <
+ MX51_PAD_UART2_RXD__UART2_RXD 0x1c5
+ MX51_PAD_UART2_TXD__UART2_TXD 0x1c5
+ >;
+ };
+
+ pinctrl_uart3: uart3grp {
+ fsl,pins = <
+ MX51_PAD_EIM_D25__UART3_RXD 0x1c5
+ MX51_PAD_EIM_D26__UART3_TXD 0x1c5
+ MX51_PAD_EIM_D27__UART3_RTS 0x1c5
+ MX51_PAD_EIM_D24__UART3_CTS 0x1c5
+ >;
+ };
+
+ pinctrl_usbh1: usbh1grp {
+ fsl,pins = <
+ MX51_PAD_USBH1_CLK__USBH1_CLK 0x80000000
+ MX51_PAD_USBH1_DIR__USBH1_DIR 0x80000000
+ MX51_PAD_USBH1_NXT__USBH1_NXT 0x80000000
+ MX51_PAD_USBH1_DATA0__USBH1_DATA0 0x80000000
+ MX51_PAD_USBH1_DATA1__USBH1_DATA1 0x80000000
+ MX51_PAD_USBH1_DATA2__USBH1_DATA2 0x80000000
+ MX51_PAD_USBH1_DATA3__USBH1_DATA3 0x80000000
+ MX51_PAD_USBH1_DATA4__USBH1_DATA4 0x80000000
+ MX51_PAD_USBH1_DATA5__USBH1_DATA5 0x80000000
+ MX51_PAD_USBH1_DATA6__USBH1_DATA6 0x80000000
+ MX51_PAD_USBH1_DATA7__USBH1_DATA7 0x80000000
+ >;
+ };
+
+ pinctrl_usbh1reg: usbh1reggrp {
+ fsl,pins = <
+ MX51_PAD_EIM_D21__GPIO2_5 0x85
+ >;
+ };
+
+ pinctrl_usbotgreg: usbotgreggrp {
+ fsl,pins = <
+ MX51_PAD_GPIO1_7__GPIO1_7 0x85
+ >;
+ };
+ };
+};
diff --git a/arch/arm/dts/imx51-pinfunc.h b/arch/arm/dts/imx51-pinfunc.h
new file mode 100644
index 0000000..910e0ec
--- /dev/null
+++ b/arch/arm/dts/imx51-pinfunc.h
@@ -0,0 +1,768 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+/*
+ * Copyright 2013 Freescale Semiconductor, Inc.
+ */
+
+#ifndef __DTS_IMX51_PINFUNC_H
+#define __DTS_IMX51_PINFUNC_H
+
+/*
+ * The pin function ID is a tuple of
+ * <mux_reg conf_reg input_reg mux_mode input_val>
+ */
+#define MX51_PAD_EIM_D16__AUD4_RXFS 0x05c 0x3f0 0x000 0x5 0x0
+#define MX51_PAD_EIM_D16__AUD5_TXD 0x05c 0x3f0 0x8d8 0x7 0x0
+#define MX51_PAD_EIM_D16__EIM_D16 0x05c 0x3f0 0x000 0x0 0x0
+#define MX51_PAD_EIM_D16__GPIO2_0 0x05c 0x3f0 0x000 0x1 0x0
+#define MX51_PAD_EIM_D16__I2C1_SDA 0x05c 0x3f0 0x9b4 0x4 0x0
+#define MX51_PAD_EIM_D16__UART2_CTS 0x05c 0x3f0 0x000 0x3 0x0
+#define MX51_PAD_EIM_D16__USBH2_DATA0 0x05c 0x3f0 0x000 0x2 0x0
+#define MX51_PAD_EIM_D17__AUD5_RXD 0x060 0x3f4 0x8d4 0x7 0x0
+#define MX51_PAD_EIM_D17__EIM_D17 0x060 0x3f4 0x000 0x0 0x0
+#define MX51_PAD_EIM_D17__GPIO2_1 0x060 0x3f4 0x000 0x1 0x0
+#define MX51_PAD_EIM_D17__UART2_RXD 0x060 0x3f4 0x9ec 0x3 0x0
+#define MX51_PAD_EIM_D17__UART3_CTS 0x060 0x3f4 0x000 0x4 0x0
+#define MX51_PAD_EIM_D17__USBH2_DATA1 0x060 0x3f4 0x000 0x2 0x0
+#define MX51_PAD_EIM_D18__AUD5_TXC 0x064 0x3f8 0x8e4 0x7 0x0
+#define MX51_PAD_EIM_D18__EIM_D18 0x064 0x3f8 0x000 0x0 0x0
+#define MX51_PAD_EIM_D18__GPIO2_2 0x064 0x3f8 0x000 0x1 0x0
+#define MX51_PAD_EIM_D18__UART2_TXD 0x064 0x3f8 0x000 0x3 0x0
+#define MX51_PAD_EIM_D18__UART3_RTS 0x064 0x3f8 0x9f0 0x4 0x1
+#define MX51_PAD_EIM_D18__USBH2_DATA2 0x064 0x3f8 0x000 0x2 0x0
+#define MX51_PAD_EIM_D19__AUD4_RXC 0x068 0x3fc 0x000 0x5 0x0
+#define MX51_PAD_EIM_D19__AUD5_TXFS 0x068 0x3fc 0x8e8 0x7 0x0
+#define MX51_PAD_EIM_D19__EIM_D19 0x068 0x3fc 0x000 0x0 0x0
+#define MX51_PAD_EIM_D19__GPIO2_3 0x068 0x3fc 0x000 0x1 0x0
+#define MX51_PAD_EIM_D19__I2C1_SCL 0x068 0x3fc 0x9b0 0x4 0x0
+#define MX51_PAD_EIM_D19__UART2_RTS 0x068 0x3fc 0x9e8 0x3 0x1
+#define MX51_PAD_EIM_D19__USBH2_DATA3 0x068 0x3fc 0x000 0x2 0x0
+#define MX51_PAD_EIM_D20__AUD4_TXD 0x06c 0x400 0x8c8 0x5 0x0
+#define MX51_PAD_EIM_D20__EIM_D20 0x06c 0x400 0x000 0x0 0x0
+#define MX51_PAD_EIM_D20__GPIO2_4 0x06c 0x400 0x000 0x1 0x0
+#define MX51_PAD_EIM_D20__SRTC_ALARM_DEB 0x06c 0x400 0x000 0x4 0x0
+#define MX51_PAD_EIM_D20__USBH2_DATA4 0x06c 0x400 0x000 0x2 0x0
+#define MX51_PAD_EIM_D21__AUD4_RXD 0x070 0x404 0x8c4 0x5 0x0
+#define MX51_PAD_EIM_D21__EIM_D21 0x070 0x404 0x000 0x0 0x0
+#define MX51_PAD_EIM_D21__GPIO2_5 0x070 0x404 0x000 0x1 0x0
+#define MX51_PAD_EIM_D21__SRTC_ALARM_DEB 0x070 0x404 0x000 0x3 0x0
+#define MX51_PAD_EIM_D21__USBH2_DATA5 0x070 0x404 0x000 0x2 0x0
+#define MX51_PAD_EIM_D22__AUD4_TXC 0x074 0x408 0x8cc 0x5 0x0
+#define MX51_PAD_EIM_D22__EIM_D22 0x074 0x408 0x000 0x0 0x0
+#define MX51_PAD_EIM_D22__GPIO2_6 0x074 0x408 0x000 0x1 0x0
+#define MX51_PAD_EIM_D22__USBH2_DATA6 0x074 0x408 0x000 0x2 0x0
+#define MX51_PAD_EIM_D23__AUD4_TXFS 0x078 0x40c 0x8d0 0x5 0x0
+#define MX51_PAD_EIM_D23__EIM_D23 0x078 0x40c 0x000 0x0 0x0
+#define MX51_PAD_EIM_D23__GPIO2_7 0x078 0x40c 0x000 0x1 0x0
+#define MX51_PAD_EIM_D23__SPDIF_OUT1 0x078 0x40c 0x000 0x4 0x0
+#define MX51_PAD_EIM_D23__USBH2_DATA7 0x078 0x40c 0x000 0x2 0x0
+#define MX51_PAD_EIM_D24__AUD6_RXFS 0x07c 0x410 0x8f8 0x5 0x0
+#define MX51_PAD_EIM_D24__EIM_D24 0x07c 0x410 0x000 0x0 0x0
+#define MX51_PAD_EIM_D24__GPIO2_8 0x07c 0x410 0x000 0x1 0x0
+#define MX51_PAD_EIM_D24__I2C2_SDA 0x07c 0x410 0x9bc 0x4 0x0
+#define MX51_PAD_EIM_D24__UART3_CTS 0x07c 0x410 0x000 0x3 0x0
+#define MX51_PAD_EIM_D24__USBOTG_DATA0 0x07c 0x410 0x000 0x2 0x0
+#define MX51_PAD_EIM_D25__EIM_D25 0x080 0x414 0x000 0x0 0x0
+#define MX51_PAD_EIM_D25__KEY_COL6 0x080 0x414 0x9c8 0x1 0x0
+#define MX51_PAD_EIM_D25__UART2_CTS 0x080 0x414 0x000 0x4 0x0
+#define MX51_PAD_EIM_D25__UART3_RXD 0x080 0x414 0x9f4 0x3 0x0
+#define MX51_PAD_EIM_D25__USBOTG_DATA1 0x080 0x414 0x000 0x2 0x0
+#define MX51_PAD_EIM_D26__EIM_D26 0x084 0x418 0x000 0x0 0x0
+#define MX51_PAD_EIM_D26__KEY_COL7 0x084 0x418 0x9cc 0x1 0x0
+#define MX51_PAD_EIM_D26__UART2_RTS 0x084 0x418 0x9e8 0x4 0x3
+#define MX51_PAD_EIM_D26__UART3_TXD 0x084 0x418 0x000 0x3 0x0
+#define MX51_PAD_EIM_D26__USBOTG_DATA2 0x084 0x418 0x000 0x2 0x0
+#define MX51_PAD_EIM_D27__AUD6_RXC 0x088 0x41c 0x8f4 0x5 0x0
+#define MX51_PAD_EIM_D27__EIM_D27 0x088 0x41c 0x000 0x0 0x0
+#define MX51_PAD_EIM_D27__GPIO2_9 0x088 0x41c 0x000 0x1 0x0
+#define MX51_PAD_EIM_D27__I2C2_SCL 0x088 0x41c 0x9b8 0x4 0x0
+#define MX51_PAD_EIM_D27__UART3_RTS 0x088 0x41c 0x9f0 0x3 0x3
+#define MX51_PAD_EIM_D27__USBOTG_DATA3 0x088 0x41c 0x000 0x2 0x0
+#define MX51_PAD_EIM_D28__AUD6_TXD 0x08c 0x420 0x8f0 0x5 0x0
+#define MX51_PAD_EIM_D28__EIM_D28 0x08c 0x420 0x000 0x0 0x0
+#define MX51_PAD_EIM_D28__KEY_ROW4 0x08c 0x420 0x9d0 0x1 0x0
+#define MX51_PAD_EIM_D28__USBOTG_DATA4 0x08c 0x420 0x000 0x2 0x0
+#define MX51_PAD_EIM_D29__AUD6_RXD 0x090 0x424 0x8ec 0x5 0x0
+#define MX51_PAD_EIM_D29__EIM_D29 0x090 0x424 0x000 0x0 0x0
+#define MX51_PAD_EIM_D29__KEY_ROW5 0x090 0x424 0x9d4 0x1 0x0
+#define MX51_PAD_EIM_D29__USBOTG_DATA5 0x090 0x424 0x000 0x2 0x0
+#define MX51_PAD_EIM_D30__AUD6_TXC 0x094 0x428 0x8fc 0x5 0x0
+#define MX51_PAD_EIM_D30__EIM_D30 0x094 0x428 0x000 0x0 0x0
+#define MX51_PAD_EIM_D30__KEY_ROW6 0x094 0x428 0x9d8 0x1 0x0
+#define MX51_PAD_EIM_D30__USBOTG_DATA6 0x094 0x428 0x000 0x2 0x0
+#define MX51_PAD_EIM_D31__AUD6_TXFS 0x098 0x42c 0x900 0x5 0x0
+#define MX51_PAD_EIM_D31__EIM_D31 0x098 0x42c 0x000 0x0 0x0
+#define MX51_PAD_EIM_D31__KEY_ROW7 0x098 0x42c 0x9dc 0x1 0x0
+#define MX51_PAD_EIM_D31__USBOTG_DATA7 0x098 0x42c 0x000 0x2 0x0
+#define MX51_PAD_EIM_A16__EIM_A16 0x09c 0x430 0x000 0x0 0x0
+#define MX51_PAD_EIM_A16__GPIO2_10 0x09c 0x430 0x000 0x1 0x0
+#define MX51_PAD_EIM_A16__OSC_FREQ_SEL0 0x09c 0x430 0x000 0x7 0x0
+#define MX51_PAD_EIM_A17__EIM_A17 0x0a0 0x434 0x000 0x0 0x0
+#define MX51_PAD_EIM_A17__GPIO2_11 0x0a0 0x434 0x000 0x1 0x0
+#define MX51_PAD_EIM_A17__OSC_FREQ_SEL1 0x0a0 0x434 0x000 0x7 0x0
+#define MX51_PAD_EIM_A18__BOOT_LPB0 0x0a4 0x438 0x000 0x7 0x0
+#define MX51_PAD_EIM_A18__EIM_A18 0x0a4 0x438 0x000 0x0 0x0
+#define MX51_PAD_EIM_A18__GPIO2_12 0x0a4 0x438 0x000 0x1 0x0
+#define MX51_PAD_EIM_A19__BOOT_LPB1 0x0a8 0x43c 0x000 0x7 0x0
+#define MX51_PAD_EIM_A19__EIM_A19 0x0a8 0x43c 0x000 0x0 0x0
+#define MX51_PAD_EIM_A19__GPIO2_13 0x0a8 0x43c 0x000 0x1 0x0
+#define MX51_PAD_EIM_A20__BOOT_UART_SRC0 0x0ac 0x440 0x000 0x7 0x0
+#define MX51_PAD_EIM_A20__EIM_A20 0x0ac 0x440 0x000 0x0 0x0
+#define MX51_PAD_EIM_A20__GPIO2_14 0x0ac 0x440 0x000 0x1 0x0
+#define MX51_PAD_EIM_A21__BOOT_UART_SRC1 0x0b0 0x444 0x000 0x7 0x0
+#define MX51_PAD_EIM_A21__EIM_A21 0x0b0 0x444 0x000 0x0 0x0
+#define MX51_PAD_EIM_A21__GPIO2_15 0x0b0 0x444 0x000 0x1 0x0
+#define MX51_PAD_EIM_A22__EIM_A22 0x0b4 0x448 0x000 0x0 0x0
+#define MX51_PAD_EIM_A22__GPIO2_16 0x0b4 0x448 0x000 0x1 0x0
+#define MX51_PAD_EIM_A23__BOOT_HPN_EN 0x0b8 0x44c 0x000 0x7 0x0
+#define MX51_PAD_EIM_A23__EIM_A23 0x0b8 0x44c 0x000 0x0 0x0
+#define MX51_PAD_EIM_A23__GPIO2_17 0x0b8 0x44c 0x000 0x1 0x0
+#define MX51_PAD_EIM_A24__EIM_A24 0x0bc 0x450 0x000 0x0 0x0
+#define MX51_PAD_EIM_A24__GPIO2_18 0x0bc 0x450 0x000 0x1 0x0
+#define MX51_PAD_EIM_A24__USBH2_CLK 0x0bc 0x450 0x000 0x2 0x0
+#define MX51_PAD_EIM_A25__DISP1_PIN4 0x0c0 0x454 0x000 0x6 0x0
+#define MX51_PAD_EIM_A25__EIM_A25 0x0c0 0x454 0x000 0x0 0x0
+#define MX51_PAD_EIM_A25__GPIO2_19 0x0c0 0x454 0x000 0x1 0x0
+#define MX51_PAD_EIM_A25__USBH2_DIR 0x0c0 0x454 0x000 0x2 0x0
+#define MX51_PAD_EIM_A26__CSI1_DATA_EN 0x0c4 0x458 0x9a0 0x5 0x0
+#define MX51_PAD_EIM_A26__DISP2_EXT_CLK 0x0c4 0x458 0x908 0x6 0x0
+#define MX51_PAD_EIM_A26__EIM_A26 0x0c4 0x458 0x000 0x0 0x0
+#define MX51_PAD_EIM_A26__GPIO2_20 0x0c4 0x458 0x000 0x1 0x0
+#define MX51_PAD_EIM_A26__USBH2_STP 0x0c4 0x458 0x000 0x2 0x0
+#define MX51_PAD_EIM_A27__CSI2_DATA_EN 0x0c8 0x45c 0x99c 0x5 0x0
+#define MX51_PAD_EIM_A27__DISP1_PIN1 0x0c8 0x45c 0x9a4 0x6 0x0
+#define MX51_PAD_EIM_A27__EIM_A27 0x0c8 0x45c 0x000 0x0 0x0
+#define MX51_PAD_EIM_A27__GPIO2_21 0x0c8 0x45c 0x000 0x1 0x0
+#define MX51_PAD_EIM_A27__USBH2_NXT 0x0c8 0x45c 0x000 0x2 0x0
+#define MX51_PAD_EIM_EB0__EIM_EB0 0x0cc 0x460 0x000 0x0 0x0
+#define MX51_PAD_EIM_EB1__EIM_EB1 0x0d0 0x464 0x000 0x0 0x0
+#define MX51_PAD_EIM_EB2__AUD5_RXFS 0x0d4 0x468 0x8e0 0x6 0x0
+#define MX51_PAD_EIM_EB2__CSI1_D2 0x0d4 0x468 0x000 0x5 0x0
+#define MX51_PAD_EIM_EB2__EIM_EB2 0x0d4 0x468 0x000 0x0 0x0
+#define MX51_PAD_EIM_EB2__FEC_MDIO 0x0d4 0x468 0x954 0x3 0x0
+#define MX51_PAD_EIM_EB2__GPIO2_22 0x0d4 0x468 0x000 0x1 0x0
+#define MX51_PAD_EIM_EB2__GPT_CMPOUT1 0x0d4 0x468 0x000 0x7 0x0
+#define MX51_PAD_EIM_EB3__AUD5_RXC 0x0d8 0x46c 0x8dc 0x6 0x0
+#define MX51_PAD_EIM_EB3__CSI1_D3 0x0d8 0x46c 0x000 0x5 0x0
+#define MX51_PAD_EIM_EB3__EIM_EB3 0x0d8 0x46c 0x000 0x0 0x0
+#define MX51_PAD_EIM_EB3__FEC_RDATA1 0x0d8 0x46c 0x95c 0x3 0x0
+#define MX51_PAD_EIM_EB3__GPIO2_23 0x0d8 0x46c 0x000 0x1 0x0
+#define MX51_PAD_EIM_EB3__GPT_CMPOUT2 0x0d8 0x46c 0x000 0x7 0x0
+#define MX51_PAD_EIM_OE__EIM_OE 0x0dc 0x470 0x000 0x0 0x0
+#define MX51_PAD_EIM_OE__GPIO2_24 0x0dc 0x470 0x000 0x1 0x0
+#define MX51_PAD_EIM_CS0__EIM_CS0 0x0e0 0x474 0x000 0x0 0x0
+#define MX51_PAD_EIM_CS0__GPIO2_25 0x0e0 0x474 0x000 0x1 0x0
+#define MX51_PAD_EIM_CS1__EIM_CS1 0x0e4 0x478 0x000 0x0 0x0
+#define MX51_PAD_EIM_CS1__GPIO2_26 0x0e4 0x478 0x000 0x1 0x0
+#define MX51_PAD_EIM_CS2__AUD5_TXD 0x0e8 0x47c 0x8d8 0x6 0x1
+#define MX51_PAD_EIM_CS2__CSI1_D4 0x0e8 0x47c 0x000 0x5 0x0
+#define MX51_PAD_EIM_CS2__EIM_CS2 0x0e8 0x47c 0x000 0x0 0x0
+#define MX51_PAD_EIM_CS2__FEC_RDATA2 0x0e8 0x47c 0x960 0x3 0x0
+#define MX51_PAD_EIM_CS2__GPIO2_27 0x0e8 0x47c 0x000 0x1 0x0
+#define MX51_PAD_EIM_CS2__USBOTG_STP 0x0e8 0x47c 0x000 0x2 0x0
+#define MX51_PAD_EIM_CS3__AUD5_RXD 0x0ec 0x480 0x8d4 0x6 0x1
+#define MX51_PAD_EIM_CS3__CSI1_D5 0x0ec 0x480 0x000 0x5 0x0
+#define MX51_PAD_EIM_CS3__EIM_CS3 0x0ec 0x480 0x000 0x0 0x0
+#define MX51_PAD_EIM_CS3__FEC_RDATA3 0x0ec 0x480 0x964 0x3 0x0
+#define MX51_PAD_EIM_CS3__GPIO2_28 0x0ec 0x480 0x000 0x1 0x0
+#define MX51_PAD_EIM_CS3__USBOTG_NXT 0x0ec 0x480 0x000 0x2 0x0
+#define MX51_PAD_EIM_CS4__AUD5_TXC 0x0f0 0x484 0x8e4 0x6 0x1
+#define MX51_PAD_EIM_CS4__CSI1_D6 0x0f0 0x484 0x000 0x5 0x0
+#define MX51_PAD_EIM_CS4__EIM_CS4 0x0f0 0x484 0x000 0x0 0x0
+#define MX51_PAD_EIM_CS4__FEC_RX_ER 0x0f0 0x484 0x970 0x3 0x0
+#define MX51_PAD_EIM_CS4__GPIO2_29 0x0f0 0x484 0x000 0x1 0x0
+#define MX51_PAD_EIM_CS4__USBOTG_CLK 0x0f0 0x484 0x000 0x2 0x0
+#define MX51_PAD_EIM_CS5__AUD5_TXFS 0x0f4 0x488 0x8e8 0x6 0x1
+#define MX51_PAD_EIM_CS5__CSI1_D7 0x0f4 0x488 0x000 0x5 0x0
+#define MX51_PAD_EIM_CS5__DISP1_EXT_CLK 0x0f4 0x488 0x904 0x4 0x0
+#define MX51_PAD_EIM_CS5__EIM_CS5 0x0f4 0x488 0x000 0x0 0x0
+#define MX51_PAD_EIM_CS5__FEC_CRS 0x0f4 0x488 0x950 0x3 0x0
+#define MX51_PAD_EIM_CS5__GPIO2_30 0x0f4 0x488 0x000 0x1 0x0
+#define MX51_PAD_EIM_CS5__USBOTG_DIR 0x0f4 0x488 0x000 0x2 0x0
+#define MX51_PAD_EIM_DTACK__EIM_DTACK 0x0f8 0x48c 0x000 0x0 0x0
+#define MX51_PAD_EIM_DTACK__GPIO2_31 0x0f8 0x48c 0x000 0x1 0x0
+#define MX51_PAD_EIM_LBA__EIM_LBA 0x0fc 0x494 0x000 0x0 0x0
+#define MX51_PAD_EIM_LBA__GPIO3_1 0x0fc 0x494 0x978 0x1 0x0
+#define MX51_PAD_EIM_CRE__EIM_CRE 0x100 0x4a0 0x000 0x0 0x0
+#define MX51_PAD_EIM_CRE__GPIO3_2 0x100 0x4a0 0x97c 0x1 0x0
+#define MX51_PAD_DRAM_CS1__DRAM_CS1 0x104 0x4d0 0x000 0x0 0x0
+#define MX51_PAD_NANDF_WE_B__GPIO3_3 0x108 0x4e4 0x980 0x3 0x0
+#define MX51_PAD_NANDF_WE_B__NANDF_WE_B 0x108 0x4e4 0x000 0x0 0x0
+#define MX51_PAD_NANDF_WE_B__PATA_DIOW 0x108 0x4e4 0x000 0x1 0x0
+#define MX51_PAD_NANDF_WE_B__SD3_DATA0 0x108 0x4e4 0x93c 0x2 0x0
+#define MX51_PAD_NANDF_RE_B__GPIO3_4 0x10c 0x4e8 0x984 0x3 0x0
+#define MX51_PAD_NANDF_RE_B__NANDF_RE_B 0x10c 0x4e8 0x000 0x0 0x0
+#define MX51_PAD_NANDF_RE_B__PATA_DIOR 0x10c 0x4e8 0x000 0x1 0x0
+#define MX51_PAD_NANDF_RE_B__SD3_DATA1 0x10c 0x4e8 0x940 0x2 0x0
+#define MX51_PAD_NANDF_ALE__GPIO3_5 0x110 0x4ec 0x988 0x3 0x0
+#define MX51_PAD_NANDF_ALE__NANDF_ALE 0x110 0x4ec 0x000 0x0 0x0
+#define MX51_PAD_NANDF_ALE__PATA_BUFFER_EN 0x110 0x4ec 0x000 0x1 0x0
+#define MX51_PAD_NANDF_CLE__GPIO3_6 0x114 0x4f0 0x98c 0x3 0x0
+#define MX51_PAD_NANDF_CLE__NANDF_CLE 0x114 0x4f0 0x000 0x0 0x0
+#define MX51_PAD_NANDF_CLE__PATA_RESET_B 0x114 0x4f0 0x000 0x1 0x0
+#define MX51_PAD_NANDF_WP_B__GPIO3_7 0x118 0x4f4 0x990 0x3 0x0
+#define MX51_PAD_NANDF_WP_B__NANDF_WP_B 0x118 0x4f4 0x000 0x0 0x0
+#define MX51_PAD_NANDF_WP_B__PATA_DMACK 0x118 0x4f4 0x000 0x1 0x0
+#define MX51_PAD_NANDF_WP_B__SD3_DATA2 0x118 0x4f4 0x944 0x2 0x0
+#define MX51_PAD_NANDF_RB0__ECSPI2_SS1 0x11c 0x4f8 0x930 0x5 0x0
+#define MX51_PAD_NANDF_RB0__GPIO3_8 0x11c 0x4f8 0x994 0x3 0x0
+#define MX51_PAD_NANDF_RB0__NANDF_RB0 0x11c 0x4f8 0x000 0x0 0x0
+#define MX51_PAD_NANDF_RB0__PATA_DMARQ 0x11c 0x4f8 0x000 0x1 0x0
+#define MX51_PAD_NANDF_RB0__SD3_DATA3 0x11c 0x4f8 0x948 0x2 0x0
+#define MX51_PAD_NANDF_RB1__CSPI_MOSI 0x120 0x4fc 0x91c 0x6 0x0
+#define MX51_PAD_NANDF_RB1__ECSPI2_RDY 0x120 0x4fc 0x000 0x2 0x0
+#define MX51_PAD_NANDF_RB1__GPIO3_9 0x120 0x4fc 0x000 0x3 0x0
+#define MX51_PAD_NANDF_RB1__NANDF_RB1 0x120 0x4fc 0x000 0x0 0x0
+#define MX51_PAD_NANDF_RB1__PATA_IORDY 0x120 0x4fc 0x000 0x1 0x0
+#define MX51_PAD_NANDF_RB1__SD4_CMD 0x120 0x4fc 0x000 0x5 0x0
+#define MX51_PAD_NANDF_RB2__DISP2_WAIT 0x124 0x500 0x9a8 0x5 0x0
+#define MX51_PAD_NANDF_RB2__ECSPI2_SCLK 0x124 0x500 0x000 0x2 0x0
+#define MX51_PAD_NANDF_RB2__FEC_COL 0x124 0x500 0x94c 0x1 0x0
+#define MX51_PAD_NANDF_RB2__GPIO3_10 0x124 0x500 0x000 0x3 0x0
+#define MX51_PAD_NANDF_RB2__NANDF_RB2 0x124 0x500 0x000 0x0 0x0
+#define MX51_PAD_NANDF_RB2__USBH3_H3_DP 0x124 0x500 0x000 0x7 0x0
+#define MX51_PAD_NANDF_RB2__USBH3_NXT 0x124 0x500 0xa20 0x6 0x0
+#define MX51_PAD_NANDF_RB3__DISP1_WAIT 0x128 0x504 0x000 0x5 0x0
+#define MX51_PAD_NANDF_RB3__ECSPI2_MISO 0x128 0x504 0x000 0x2 0x0
+#define MX51_PAD_NANDF_RB3__FEC_RX_CLK 0x128 0x504 0x968 0x1 0x0
+#define MX51_PAD_NANDF_RB3__GPIO3_11 0x128 0x504 0x000 0x3 0x0
+#define MX51_PAD_NANDF_RB3__NANDF_RB3 0x128 0x504 0x000 0x0 0x0
+#define MX51_PAD_NANDF_RB3__USBH3_CLK 0x128 0x504 0x9f8 0x6 0x0
+#define MX51_PAD_NANDF_RB3__USBH3_H3_DM 0x128 0x504 0x000 0x7 0x0
+#define MX51_PAD_GPIO_NAND__GPIO_NAND 0x12c 0x514 0x998 0x0 0x0
+#define MX51_PAD_GPIO_NAND__PATA_INTRQ 0x12c 0x514 0x000 0x1 0x0
+#define MX51_PAD_NANDF_CS0__GPIO3_16 0x130 0x518 0x000 0x3 0x0
+#define MX51_PAD_NANDF_CS0__NANDF_CS0 0x130 0x518 0x000 0x0 0x0
+#define MX51_PAD_NANDF_CS1__GPIO3_17 0x134 0x51c 0x000 0x3 0x0
+#define MX51_PAD_NANDF_CS1__NANDF_CS1 0x134 0x51c 0x000 0x0 0x0
+#define MX51_PAD_NANDF_CS2__CSPI_SCLK 0x138 0x520 0x914 0x6 0x0
+#define MX51_PAD_NANDF_CS2__FEC_TX_ER 0x138 0x520 0x000 0x2 0x0
+#define MX51_PAD_NANDF_CS2__GPIO3_18 0x138 0x520 0x000 0x3 0x0
+#define MX51_PAD_NANDF_CS2__NANDF_CS2 0x138 0x520 0x000 0x0 0x0
+#define MX51_PAD_NANDF_CS2__PATA_CS_0 0x138 0x520 0x000 0x1 0x0
+#define MX51_PAD_NANDF_CS2__SD4_CLK 0x138 0x520 0x000 0x5 0x0
+#define MX51_PAD_NANDF_CS2__USBH3_H1_DP 0x138 0x520 0x000 0x7 0x0
+#define MX51_PAD_NANDF_CS3__FEC_MDC 0x13c 0x524 0x000 0x2 0x0
+#define MX51_PAD_NANDF_CS3__GPIO3_19 0x13c 0x524 0x000 0x3 0x0
+#define MX51_PAD_NANDF_CS3__NANDF_CS3 0x13c 0x524 0x000 0x0 0x0
+#define MX51_PAD_NANDF_CS3__PATA_CS_1 0x13c 0x524 0x000 0x1 0x0
+#define MX51_PAD_NANDF_CS3__SD4_DAT0 0x13c 0x524 0x000 0x5 0x0
+#define MX51_PAD_NANDF_CS3__USBH3_H1_DM 0x13c 0x524 0x000 0x7 0x0
+#define MX51_PAD_NANDF_CS4__FEC_TDATA1 0x140 0x528 0x000 0x2 0x0
+#define MX51_PAD_NANDF_CS4__GPIO3_20 0x140 0x528 0x000 0x3 0x0
+#define MX51_PAD_NANDF_CS4__NANDF_CS4 0x140 0x528 0x000 0x0 0x0
+#define MX51_PAD_NANDF_CS4__PATA_DA_0 0x140 0x528 0x000 0x1 0x0
+#define MX51_PAD_NANDF_CS4__SD4_DAT1 0x140 0x528 0x000 0x5 0x0
+#define MX51_PAD_NANDF_CS4__USBH3_STP 0x140 0x528 0xa24 0x7 0x0
+#define MX51_PAD_NANDF_CS5__FEC_TDATA2 0x144 0x52c 0x000 0x2 0x0
+#define MX51_PAD_NANDF_CS5__GPIO3_21 0x144 0x52c 0x000 0x3 0x0
+#define MX51_PAD_NANDF_CS5__NANDF_CS5 0x144 0x52c 0x000 0x0 0x0
+#define MX51_PAD_NANDF_CS5__PATA_DA_1 0x144 0x52c 0x000 0x1 0x0
+#define MX51_PAD_NANDF_CS5__SD4_DAT2 0x144 0x52c 0x000 0x5 0x0
+#define MX51_PAD_NANDF_CS5__USBH3_DIR 0x144 0x52c 0xa1c 0x7 0x0
+#define MX51_PAD_NANDF_CS6__CSPI_SS3 0x148 0x530 0x928 0x7 0x0
+#define MX51_PAD_NANDF_CS6__FEC_TDATA3 0x148 0x530 0x000 0x2 0x0
+#define MX51_PAD_NANDF_CS6__GPIO3_22 0x148 0x530 0x000 0x3 0x0
+#define MX51_PAD_NANDF_CS6__NANDF_CS6 0x148 0x530 0x000 0x0 0x0
+#define MX51_PAD_NANDF_CS6__PATA_DA_2 0x148 0x530 0x000 0x1 0x0
+#define MX51_PAD_NANDF_CS6__SD4_DAT3 0x148 0x530 0x000 0x5 0x0
+#define MX51_PAD_NANDF_CS7__FEC_TX_EN 0x14c 0x534 0x000 0x1 0x0
+#define MX51_PAD_NANDF_CS7__GPIO3_23 0x14c 0x534 0x000 0x3 0x0
+#define MX51_PAD_NANDF_CS7__NANDF_CS7 0x14c 0x534 0x000 0x0 0x0
+#define MX51_PAD_NANDF_CS7__SD3_CLK 0x14c 0x534 0x000 0x5 0x0
+#define MX51_PAD_NANDF_RDY_INT__ECSPI2_SS0 0x150 0x538 0x000 0x2 0x0
+#define MX51_PAD_NANDF_RDY_INT__FEC_TX_CLK 0x150 0x538 0x974 0x1 0x0
+#define MX51_PAD_NANDF_RDY_INT__GPIO3_24 0x150 0x538 0x000 0x3 0x0
+#define MX51_PAD_NANDF_RDY_INT__NANDF_RDY_INT 0x150 0x538 0x938 0x0 0x0
+#define MX51_PAD_NANDF_RDY_INT__SD3_CMD 0x150 0x538 0x000 0x5 0x0
+#define MX51_PAD_NANDF_D15__ECSPI2_MOSI 0x154 0x53c 0x000 0x2 0x0
+#define MX51_PAD_NANDF_D15__GPIO3_25 0x154 0x53c 0x000 0x3 0x0
+#define MX51_PAD_NANDF_D15__NANDF_D15 0x154 0x53c 0x000 0x0 0x0
+#define MX51_PAD_NANDF_D15__PATA_DATA15 0x154 0x53c 0x000 0x1 0x0
+#define MX51_PAD_NANDF_D15__SD3_DAT7 0x154 0x53c 0x000 0x5 0x0
+#define MX51_PAD_NANDF_D14__ECSPI2_SS3 0x158 0x540 0x934 0x2 0x0
+#define MX51_PAD_NANDF_D14__GPIO3_26 0x158 0x540 0x000 0x3 0x0
+#define MX51_PAD_NANDF_D14__NANDF_D14 0x158 0x540 0x000 0x0 0x0
+#define MX51_PAD_NANDF_D14__PATA_DATA14 0x158 0x540 0x000 0x1 0x0
+#define MX51_PAD_NANDF_D14__SD3_DAT6 0x158 0x540 0x000 0x5 0x0
+#define MX51_PAD_NANDF_D13__ECSPI2_SS2 0x15c 0x544 0x000 0x2 0x0
+#define MX51_PAD_NANDF_D13__GPIO3_27 0x15c 0x544 0x000 0x3 0x0
+#define MX51_PAD_NANDF_D13__NANDF_D13 0x15c 0x544 0x000 0x0 0x0
+#define MX51_PAD_NANDF_D13__PATA_DATA13 0x15c 0x544 0x000 0x1 0x0
+#define MX51_PAD_NANDF_D13__SD3_DAT5 0x15c 0x544 0x000 0x5 0x0
+#define MX51_PAD_NANDF_D12__ECSPI2_SS1 0x160 0x548 0x930 0x2 0x1
+#define MX51_PAD_NANDF_D12__GPIO3_28 0x160 0x548 0x000 0x3 0x0
+#define MX51_PAD_NANDF_D12__NANDF_D12 0x160 0x548 0x000 0x0 0x0
+#define MX51_PAD_NANDF_D12__PATA_DATA12 0x160 0x548 0x000 0x1 0x0
+#define MX51_PAD_NANDF_D12__SD3_DAT4 0x160 0x548 0x000 0x5 0x0
+#define MX51_PAD_NANDF_D11__FEC_RX_DV 0x164 0x54c 0x96c 0x2 0x0
+#define MX51_PAD_NANDF_D11__GPIO3_29 0x164 0x54c 0x000 0x3 0x0
+#define MX51_PAD_NANDF_D11__NANDF_D11 0x164 0x54c 0x000 0x0 0x0
+#define MX51_PAD_NANDF_D11__PATA_DATA11 0x164 0x54c 0x000 0x1 0x0
+#define MX51_PAD_NANDF_D11__SD3_DATA3 0x164 0x54c 0x948 0x5 0x1
+#define MX51_PAD_NANDF_D10__GPIO3_30 0x168 0x550 0x000 0x3 0x0
+#define MX51_PAD_NANDF_D10__NANDF_D10 0x168 0x550 0x000 0x0 0x0
+#define MX51_PAD_NANDF_D10__PATA_DATA10 0x168 0x550 0x000 0x1 0x0
+#define MX51_PAD_NANDF_D10__SD3_DATA2 0x168 0x550 0x944 0x5 0x1
+#define MX51_PAD_NANDF_D9__FEC_RDATA0 0x16c 0x554 0x958 0x2 0x0
+#define MX51_PAD_NANDF_D9__GPIO3_31 0x16c 0x554 0x000 0x3 0x0
+#define MX51_PAD_NANDF_D9__NANDF_D9 0x16c 0x554 0x000 0x0 0x0
+#define MX51_PAD_NANDF_D9__PATA_DATA9 0x16c 0x554 0x000 0x1 0x0
+#define MX51_PAD_NANDF_D9__SD3_DATA1 0x16c 0x554 0x940 0x5 0x1
+#define MX51_PAD_NANDF_D8__FEC_TDATA0 0x170 0x558 0x000 0x2 0x0
+#define MX51_PAD_NANDF_D8__GPIO4_0 0x170 0x558 0x000 0x3 0x0
+#define MX51_PAD_NANDF_D8__NANDF_D8 0x170 0x558 0x000 0x0 0x0
+#define MX51_PAD_NANDF_D8__PATA_DATA8 0x170 0x558 0x000 0x1 0x0
+#define MX51_PAD_NANDF_D8__SD3_DATA0 0x170 0x558 0x93c 0x5 0x1
+#define MX51_PAD_NANDF_D7__GPIO4_1 0x174 0x55c 0x000 0x3 0x0
+#define MX51_PAD_NANDF_D7__NANDF_D7 0x174 0x55c 0x000 0x0 0x0
+#define MX51_PAD_NANDF_D7__PATA_DATA7 0x174 0x55c 0x000 0x1 0x0
+#define MX51_PAD_NANDF_D7__USBH3_DATA0 0x174 0x55c 0x9fc 0x5 0x0
+#define MX51_PAD_NANDF_D6__GPIO4_2 0x178 0x560 0x000 0x3 0x0
+#define MX51_PAD_NANDF_D6__NANDF_D6 0x178 0x560 0x000 0x0 0x0
+#define MX51_PAD_NANDF_D6__PATA_DATA6 0x178 0x560 0x000 0x1 0x0
+#define MX51_PAD_NANDF_D6__SD4_LCTL 0x178 0x560 0x000 0x2 0x0
+#define MX51_PAD_NANDF_D6__USBH3_DATA1 0x178 0x560 0xa00 0x5 0x0
+#define MX51_PAD_NANDF_D5__GPIO4_3 0x17c 0x564 0x000 0x3 0x0
+#define MX51_PAD_NANDF_D5__NANDF_D5 0x17c 0x564 0x000 0x0 0x0
+#define MX51_PAD_NANDF_D5__PATA_DATA5 0x17c 0x564 0x000 0x1 0x0
+#define MX51_PAD_NANDF_D5__SD4_WP 0x17c 0x564 0x000 0x2 0x0
+#define MX51_PAD_NANDF_D5__USBH3_DATA2 0x17c 0x564 0xa04 0x5 0x0
+#define MX51_PAD_NANDF_D4__GPIO4_4 0x180 0x568 0x000 0x3 0x0
+#define MX51_PAD_NANDF_D4__NANDF_D4 0x180 0x568 0x000 0x0 0x0
+#define MX51_PAD_NANDF_D4__PATA_DATA4 0x180 0x568 0x000 0x1 0x0
+#define MX51_PAD_NANDF_D4__SD4_CD 0x180 0x568 0x000 0x2 0x0
+#define MX51_PAD_NANDF_D4__USBH3_DATA3 0x180 0x568 0xa08 0x5 0x0
+#define MX51_PAD_NANDF_D3__GPIO4_5 0x184 0x56c 0x000 0x3 0x0
+#define MX51_PAD_NANDF_D3__NANDF_D3 0x184 0x56c 0x000 0x0 0x0
+#define MX51_PAD_NANDF_D3__PATA_DATA3 0x184 0x56c 0x000 0x1 0x0
+#define MX51_PAD_NANDF_D3__SD4_DAT4 0x184 0x56c 0x000 0x2 0x0
+#define MX51_PAD_NANDF_D3__USBH3_DATA4 0x184 0x56c 0xa0c 0x5 0x0
+#define MX51_PAD_NANDF_D2__GPIO4_6 0x188 0x570 0x000 0x3 0x0
+#define MX51_PAD_NANDF_D2__NANDF_D2 0x188 0x570 0x000 0x0 0x0
+#define MX51_PAD_NANDF_D2__PATA_DATA2 0x188 0x570 0x000 0x1 0x0
+#define MX51_PAD_NANDF_D2__SD4_DAT5 0x188 0x570 0x000 0x2 0x0
+#define MX51_PAD_NANDF_D2__USBH3_DATA5 0x188 0x570 0xa10 0x5 0x0
+#define MX51_PAD_NANDF_D1__GPIO4_7 0x18c 0x574 0x000 0x3 0x0
+#define MX51_PAD_NANDF_D1__NANDF_D1 0x18c 0x574 0x000 0x0 0x0
+#define MX51_PAD_NANDF_D1__PATA_DATA1 0x18c 0x574 0x000 0x1 0x0
+#define MX51_PAD_NANDF_D1__SD4_DAT6 0x18c 0x574 0x000 0x2 0x0
+#define MX51_PAD_NANDF_D1__USBH3_DATA6 0x18c 0x574 0xa14 0x5 0x0
+#define MX51_PAD_NANDF_D0__GPIO4_8 0x190 0x578 0x000 0x3 0x0
+#define MX51_PAD_NANDF_D0__NANDF_D0 0x190 0x578 0x000 0x0 0x0
+#define MX51_PAD_NANDF_D0__PATA_DATA0 0x190 0x578 0x000 0x1 0x0
+#define MX51_PAD_NANDF_D0__SD4_DAT7 0x190 0x578 0x000 0x2 0x0
+#define MX51_PAD_NANDF_D0__USBH3_DATA7 0x190 0x578 0xa18 0x5 0x0
+#define MX51_PAD_CSI1_D8__CSI1_D8 0x194 0x57c 0x000 0x0 0x0
+#define MX51_PAD_CSI1_D8__GPIO3_12 0x194 0x57c 0x998 0x3 0x1
+#define MX51_PAD_CSI1_D9__CSI1_D9 0x198 0x580 0x000 0x0 0x0
+#define MX51_PAD_CSI1_D9__GPIO3_13 0x198 0x580 0x000 0x3 0x0
+#define MX51_PAD_CSI1_D10__CSI1_D10 0x19c 0x584 0x000 0x0 0x0
+#define MX51_PAD_CSI1_D11__CSI1_D11 0x1a0 0x588 0x000 0x0 0x0
+#define MX51_PAD_CSI1_D12__CSI1_D12 0x1a4 0x58c 0x000 0x0 0x0
+#define MX51_PAD_CSI1_D13__CSI1_D13 0x1a8 0x590 0x000 0x0 0x0
+#define MX51_PAD_CSI1_D14__CSI1_D14 0x1ac 0x594 0x000 0x0 0x0
+#define MX51_PAD_CSI1_D15__CSI1_D15 0x1b0 0x598 0x000 0x0 0x0
+#define MX51_PAD_CSI1_D16__CSI1_D16 0x1b4 0x59c 0x000 0x0 0x0
+#define MX51_PAD_CSI1_D17__CSI1_D17 0x1b8 0x5a0 0x000 0x0 0x0
+#define MX51_PAD_CSI1_D18__CSI1_D18 0x1bc 0x5a4 0x000 0x0 0x0
+#define MX51_PAD_CSI1_D19__CSI1_D19 0x1c0 0x5a8 0x000 0x0 0x0
+#define MX51_PAD_CSI1_VSYNC__CSI1_VSYNC 0x1c4 0x5ac 0x000 0x0 0x0
+#define MX51_PAD_CSI1_VSYNC__GPIO3_14 0x1c4 0x5ac 0x000 0x3 0x0
+#define MX51_PAD_CSI1_HSYNC__CSI1_HSYNC 0x1c8 0x5b0 0x000 0x0 0x0
+#define MX51_PAD_CSI1_HSYNC__GPIO3_15 0x1c8 0x5b0 0x000 0x3 0x0
+#define MX51_PAD_CSI1_PIXCLK__CSI1_PIXCLK 0x000 0x5b4 0x000 0x0 0x0
+#define MX51_PAD_CSI1_MCLK__CSI1_MCLK 0x000 0x5b8 0x000 0x0 0x0
+#define MX51_PAD_CSI2_D12__CSI2_D12 0x1cc 0x5bc 0x000 0x0 0x0
+#define MX51_PAD_CSI2_D12__GPIO4_9 0x1cc 0x5bc 0x000 0x3 0x0
+#define MX51_PAD_CSI2_D13__CSI2_D13 0x1d0 0x5c0 0x000 0x0 0x0
+#define MX51_PAD_CSI2_D13__GPIO4_10 0x1d0 0x5c0 0x000 0x3 0x0
+#define MX51_PAD_CSI2_D14__CSI2_D14 0x1d4 0x5c4 0x000 0x0 0x0
+#define MX51_PAD_CSI2_D15__CSI2_D15 0x1d8 0x5c8 0x000 0x0 0x0
+#define MX51_PAD_CSI2_D16__CSI2_D16 0x1dc 0x5cc 0x000 0x0 0x0
+#define MX51_PAD_CSI2_D17__CSI2_D17 0x1e0 0x5d0 0x000 0x0 0x0
+#define MX51_PAD_CSI2_D18__CSI2_D18 0x1e4 0x5d4 0x000 0x0 0x0
+#define MX51_PAD_CSI2_D18__GPIO4_11 0x1e4 0x5d4 0x000 0x3 0x0
+#define MX51_PAD_CSI2_D19__CSI2_D19 0x1e8 0x5d8 0x000 0x0 0x0
+#define MX51_PAD_CSI2_D19__GPIO4_12 0x1e8 0x5d8 0x000 0x3 0x0
+#define MX51_PAD_CSI2_VSYNC__CSI2_VSYNC 0x1ec 0x5dc 0x000 0x0 0x0
+#define MX51_PAD_CSI2_VSYNC__GPIO4_13 0x1ec 0x5dc 0x000 0x3 0x0
+#define MX51_PAD_CSI2_HSYNC__CSI2_HSYNC 0x1f0 0x5e0 0x000 0x0 0x0
+#define MX51_PAD_CSI2_HSYNC__GPIO4_14 0x1f0 0x5e0 0x000 0x3 0x0
+#define MX51_PAD_CSI2_PIXCLK__CSI2_PIXCLK 0x1f4 0x5e4 0x000 0x0 0x0
+#define MX51_PAD_CSI2_PIXCLK__GPIO4_15 0x1f4 0x5e4 0x000 0x3 0x0
+#define MX51_PAD_I2C1_CLK__GPIO4_16 0x1f8 0x5e8 0x000 0x3 0x0
+#define MX51_PAD_I2C1_CLK__I2C1_CLK 0x1f8 0x5e8 0x000 0x0 0x0
+#define MX51_PAD_I2C1_DAT__GPIO4_17 0x1fc 0x5ec 0x000 0x3 0x0
+#define MX51_PAD_I2C1_DAT__I2C1_DAT 0x1fc 0x5ec 0x000 0x0 0x0
+#define MX51_PAD_AUD3_BB_TXD__AUD3_TXD 0x200 0x5f0 0x000 0x0 0x0
+#define MX51_PAD_AUD3_BB_TXD__GPIO4_18 0x200 0x5f0 0x000 0x3 0x0
+#define MX51_PAD_AUD3_BB_RXD__AUD3_RXD 0x204 0x5f4 0x000 0x0 0x0
+#define MX51_PAD_AUD3_BB_RXD__GPIO4_19 0x204 0x5f4 0x000 0x3 0x0
+#define MX51_PAD_AUD3_BB_RXD__UART3_RXD 0x204 0x5f4 0x9f4 0x1 0x2
+#define MX51_PAD_AUD3_BB_CK__AUD3_TXC 0x208 0x5f8 0x000 0x0 0x0
+#define MX51_PAD_AUD3_BB_CK__GPIO4_20 0x208 0x5f8 0x000 0x3 0x0
+#define MX51_PAD_AUD3_BB_FS__AUD3_TXFS 0x20c 0x5fc 0x000 0x0 0x0
+#define MX51_PAD_AUD3_BB_FS__GPIO4_21 0x20c 0x5fc 0x000 0x3 0x0
+#define MX51_PAD_AUD3_BB_FS__UART3_TXD 0x20c 0x5fc 0x000 0x1 0x0
+#define MX51_PAD_CSPI1_MOSI__ECSPI1_MOSI 0x210 0x600 0x000 0x0 0x0
+#define MX51_PAD_CSPI1_MOSI__GPIO4_22 0x210 0x600 0x000 0x3 0x0
+#define MX51_PAD_CSPI1_MOSI__I2C1_SDA 0x210 0x600 0x9b4 0x1 0x1
+#define MX51_PAD_CSPI1_MISO__AUD4_RXD 0x214 0x604 0x8c4 0x1 0x1
+#define MX51_PAD_CSPI1_MISO__ECSPI1_MISO 0x214 0x604 0x000 0x0 0x0
+#define MX51_PAD_CSPI1_MISO__GPIO4_23 0x214 0x604 0x000 0x3 0x0
+#define MX51_PAD_CSPI1_SS0__AUD4_TXC 0x218 0x608 0x8cc 0x1 0x1
+#define MX51_PAD_CSPI1_SS0__ECSPI1_SS0 0x218 0x608 0x000 0x0 0x0
+#define MX51_PAD_CSPI1_SS0__GPIO4_24 0x218 0x608 0x000 0x3 0x0
+#define MX51_PAD_CSPI1_SS1__AUD4_TXD 0x21c 0x60c 0x8c8 0x1 0x1
+#define MX51_PAD_CSPI1_SS1__ECSPI1_SS1 0x21c 0x60c 0x000 0x0 0x0
+#define MX51_PAD_CSPI1_SS1__GPIO4_25 0x21c 0x60c 0x000 0x3 0x0
+#define MX51_PAD_CSPI1_RDY__AUD4_TXFS 0x220 0x610 0x8d0 0x1 0x1
+#define MX51_PAD_CSPI1_RDY__ECSPI1_RDY 0x220 0x610 0x000 0x0 0x0
+#define MX51_PAD_CSPI1_RDY__GPIO4_26 0x220 0x610 0x000 0x3 0x0
+#define MX51_PAD_CSPI1_SCLK__ECSPI1_SCLK 0x224 0x614 0x000 0x0 0x0
+#define MX51_PAD_CSPI1_SCLK__GPIO4_27 0x224 0x614 0x000 0x3 0x0
+#define MX51_PAD_CSPI1_SCLK__I2C1_SCL 0x224 0x614 0x9b0 0x1 0x1
+#define MX51_PAD_UART1_RXD__GPIO4_28 0x228 0x618 0x000 0x3 0x0
+#define MX51_PAD_UART1_RXD__UART1_RXD 0x228 0x618 0x9e4 0x0 0x0
+#define MX51_PAD_UART1_TXD__GPIO4_29 0x22c 0x61c 0x000 0x3 0x0
+#define MX51_PAD_UART1_TXD__PWM2_PWMO 0x22c 0x61c 0x000 0x1 0x0
+#define MX51_PAD_UART1_TXD__UART1_TXD 0x22c 0x61c 0x000 0x0 0x0
+#define MX51_PAD_UART1_RTS__GPIO4_30 0x230 0x620 0x000 0x3 0x0
+#define MX51_PAD_UART1_RTS__UART1_RTS 0x230 0x620 0x9e0 0x0 0x0
+#define MX51_PAD_UART1_CTS__GPIO4_31 0x234 0x624 0x000 0x3 0x0
+#define MX51_PAD_UART1_CTS__UART1_CTS 0x234 0x624 0x000 0x0 0x0
+#define MX51_PAD_UART2_RXD__FIRI_TXD 0x238 0x628 0x000 0x1 0x0
+#define MX51_PAD_UART2_RXD__GPIO1_20 0x238 0x628 0x000 0x3 0x0
+#define MX51_PAD_UART2_RXD__UART2_RXD 0x238 0x628 0x9ec 0x0 0x2
+#define MX51_PAD_UART2_TXD__FIRI_RXD 0x23c 0x62c 0x000 0x1 0x0
+#define MX51_PAD_UART2_TXD__GPIO1_21 0x23c 0x62c 0x000 0x3 0x0
+#define MX51_PAD_UART2_TXD__UART2_TXD 0x23c 0x62c 0x000 0x0 0x0
+#define MX51_PAD_UART3_RXD__CSI1_D0 0x240 0x630 0x000 0x2 0x0
+#define MX51_PAD_UART3_RXD__GPIO1_22 0x240 0x630 0x000 0x3 0x0
+#define MX51_PAD_UART3_RXD__UART1_DTR 0x240 0x630 0x000 0x0 0x0
+#define MX51_PAD_UART3_RXD__UART3_RXD 0x240 0x630 0x9f4 0x1 0x4
+#define MX51_PAD_UART3_TXD__CSI1_D1 0x244 0x634 0x000 0x2 0x0
+#define MX51_PAD_UART3_TXD__GPIO1_23 0x244 0x634 0x000 0x3 0x0
+#define MX51_PAD_UART3_TXD__UART1_DSR 0x244 0x634 0x000 0x0 0x0
+#define MX51_PAD_UART3_TXD__UART3_TXD 0x244 0x634 0x000 0x1 0x0
+#define MX51_PAD_OWIRE_LINE__GPIO1_24 0x248 0x638 0x000 0x3 0x0
+#define MX51_PAD_OWIRE_LINE__OWIRE_LINE 0x248 0x638 0x000 0x0 0x0
+#define MX51_PAD_OWIRE_LINE__SPDIF_OUT 0x248 0x638 0x000 0x6 0x0
+#define MX51_PAD_KEY_ROW0__KEY_ROW0 0x24c 0x63c 0x000 0x0 0x0
+#define MX51_PAD_KEY_ROW1__KEY_ROW1 0x250 0x640 0x000 0x0 0x0
+#define MX51_PAD_KEY_ROW2__KEY_ROW2 0x254 0x644 0x000 0x0 0x0
+#define MX51_PAD_KEY_ROW3__KEY_ROW3 0x258 0x648 0x000 0x0 0x0
+#define MX51_PAD_KEY_COL0__KEY_COL0 0x25c 0x64c 0x000 0x0 0x0
+#define MX51_PAD_KEY_COL0__PLL1_BYP 0x25c 0x64c 0x90c 0x7 0x0
+#define MX51_PAD_KEY_COL1__KEY_COL1 0x260 0x650 0x000 0x0 0x0
+#define MX51_PAD_KEY_COL1__PLL2_BYP 0x260 0x650 0x910 0x7 0x0
+#define MX51_PAD_KEY_COL2__KEY_COL2 0x264 0x654 0x000 0x0 0x0
+#define MX51_PAD_KEY_COL2__PLL3_BYP 0x264 0x654 0x000 0x7 0x0
+#define MX51_PAD_KEY_COL3__KEY_COL3 0x268 0x658 0x000 0x0 0x0
+#define MX51_PAD_KEY_COL4__I2C2_SCL 0x26c 0x65c 0x9b8 0x3 0x1
+#define MX51_PAD_KEY_COL4__KEY_COL4 0x26c 0x65c 0x000 0x0 0x0
+#define MX51_PAD_KEY_COL4__SPDIF_OUT1 0x26c 0x65c 0x000 0x6 0x0
+#define MX51_PAD_KEY_COL4__UART1_RI 0x26c 0x65c 0x000 0x1 0x0
+#define MX51_PAD_KEY_COL4__UART3_RTS 0x26c 0x65c 0x9f0 0x2 0x4
+#define MX51_PAD_KEY_COL5__I2C2_SDA 0x270 0x660 0x9bc 0x3 0x1
+#define MX51_PAD_KEY_COL5__KEY_COL5 0x270 0x660 0x000 0x0 0x0
+#define MX51_PAD_KEY_COL5__UART1_DCD 0x270 0x660 0x000 0x1 0x0
+#define MX51_PAD_KEY_COL5__UART3_CTS 0x270 0x660 0x000 0x2 0x0
+#define MX51_PAD_USBH1_CLK__CSPI_SCLK 0x278 0x678 0x914 0x1 0x1
+#define MX51_PAD_USBH1_CLK__GPIO1_25 0x278 0x678 0x000 0x2 0x0
+#define MX51_PAD_USBH1_CLK__I2C2_SCL 0x278 0x678 0x9b8 0x5 0x2
+#define MX51_PAD_USBH1_CLK__USBH1_CLK 0x278 0x678 0x000 0x0 0x0
+#define MX51_PAD_USBH1_DIR__CSPI_MOSI 0x27c 0x67c 0x91c 0x1 0x1
+#define MX51_PAD_USBH1_DIR__GPIO1_26 0x27c 0x67c 0x000 0x2 0x0
+#define MX51_PAD_USBH1_DIR__I2C2_SDA 0x27c 0x67c 0x9bc 0x5 0x2
+#define MX51_PAD_USBH1_DIR__USBH1_DIR 0x27c 0x67c 0x000 0x0 0x0
+#define MX51_PAD_USBH1_STP__CSPI_RDY 0x280 0x680 0x000 0x1 0x0
+#define MX51_PAD_USBH1_STP__GPIO1_27 0x280 0x680 0x000 0x2 0x0
+#define MX51_PAD_USBH1_STP__UART3_RXD 0x280 0x680 0x9f4 0x5 0x6
+#define MX51_PAD_USBH1_STP__USBH1_STP 0x280 0x680 0x000 0x0 0x0
+#define MX51_PAD_USBH1_NXT__CSPI_MISO 0x284 0x684 0x918 0x1 0x0
+#define MX51_PAD_USBH1_NXT__GPIO1_28 0x284 0x684 0x000 0x2 0x0
+#define MX51_PAD_USBH1_NXT__UART3_TXD 0x284 0x684 0x000 0x5 0x0
+#define MX51_PAD_USBH1_NXT__USBH1_NXT 0x284 0x684 0x000 0x0 0x0
+#define MX51_PAD_USBH1_DATA0__GPIO1_11 0x288 0x688 0x000 0x2 0x0
+#define MX51_PAD_USBH1_DATA0__UART2_CTS 0x288 0x688 0x000 0x1 0x0
+#define MX51_PAD_USBH1_DATA0__USBH1_DATA0 0x288 0x688 0x000 0x0 0x0
+#define MX51_PAD_USBH1_DATA1__GPIO1_12 0x28c 0x68c 0x000 0x2 0x0
+#define MX51_PAD_USBH1_DATA1__UART2_RXD 0x28c 0x68c 0x9ec 0x1 0x4
+#define MX51_PAD_USBH1_DATA1__USBH1_DATA1 0x28c 0x68c 0x000 0x0 0x0
+#define MX51_PAD_USBH1_DATA2__GPIO1_13 0x290 0x690 0x000 0x2 0x0
+#define MX51_PAD_USBH1_DATA2__UART2_TXD 0x290 0x690 0x000 0x1 0x0
+#define MX51_PAD_USBH1_DATA2__USBH1_DATA2 0x290 0x690 0x000 0x0 0x0
+#define MX51_PAD_USBH1_DATA3__GPIO1_14 0x294 0x694 0x000 0x2 0x0
+#define MX51_PAD_USBH1_DATA3__UART2_RTS 0x294 0x694 0x9e8 0x1 0x5
+#define MX51_PAD_USBH1_DATA3__USBH1_DATA3 0x294 0x694 0x000 0x0 0x0
+#define MX51_PAD_USBH1_DATA4__CSPI_SS0 0x298 0x698 0x000 0x1 0x0
+#define MX51_PAD_USBH1_DATA4__GPIO1_15 0x298 0x698 0x000 0x2 0x0
+#define MX51_PAD_USBH1_DATA4__USBH1_DATA4 0x298 0x698 0x000 0x0 0x0
+#define MX51_PAD_USBH1_DATA5__CSPI_SS1 0x29c 0x69c 0x920 0x1 0x0
+#define MX51_PAD_USBH1_DATA5__GPIO1_16 0x29c 0x69c 0x000 0x2 0x0
+#define MX51_PAD_USBH1_DATA5__USBH1_DATA5 0x29c 0x69c 0x000 0x0 0x0
+#define MX51_PAD_USBH1_DATA6__CSPI_SS3 0x2a0 0x6a0 0x928 0x1 0x1
+#define MX51_PAD_USBH1_DATA6__GPIO1_17 0x2a0 0x6a0 0x000 0x2 0x0
+#define MX51_PAD_USBH1_DATA6__USBH1_DATA6 0x2a0 0x6a0 0x000 0x0 0x0
+#define MX51_PAD_USBH1_DATA7__ECSPI1_SS3 0x2a4 0x6a4 0x000 0x1 0x0
+#define MX51_PAD_USBH1_DATA7__ECSPI2_SS3 0x2a4 0x6a4 0x934 0x5 0x1
+#define MX51_PAD_USBH1_DATA7__GPIO1_18 0x2a4 0x6a4 0x000 0x2 0x0
+#define MX51_PAD_USBH1_DATA7__USBH1_DATA7 0x2a4 0x6a4 0x000 0x0 0x0
+#define MX51_PAD_DI1_PIN11__DI1_PIN11 0x2a8 0x6a8 0x000 0x0 0x0
+#define MX51_PAD_DI1_PIN11__ECSPI1_SS2 0x2a8 0x6a8 0x000 0x7 0x0
+#define MX51_PAD_DI1_PIN11__GPIO3_0 0x2a8 0x6a8 0x000 0x4 0x0
+#define MX51_PAD_DI1_PIN12__DI1_PIN12 0x2ac 0x6ac 0x000 0x0 0x0
+#define MX51_PAD_DI1_PIN12__GPIO3_1 0x2ac 0x6ac 0x978 0x4 0x1
+#define MX51_PAD_DI1_PIN13__DI1_PIN13 0x2b0 0x6b0 0x000 0x0 0x0
+#define MX51_PAD_DI1_PIN13__GPIO3_2 0x2b0 0x6b0 0x97c 0x4 0x1
+#define MX51_PAD_DI1_D0_CS__DI1_D0_CS 0x2b4 0x6b4 0x000 0x0 0x0
+#define MX51_PAD_DI1_D0_CS__GPIO3_3 0x2b4 0x6b4 0x980 0x4 0x1
+#define MX51_PAD_DI1_D1_CS__DI1_D1_CS 0x2b8 0x6b8 0x000 0x0 0x0
+#define MX51_PAD_DI1_D1_CS__DISP1_PIN14 0x2b8 0x6b8 0x000 0x2 0x0
+#define MX51_PAD_DI1_D1_CS__DISP1_PIN5 0x2b8 0x6b8 0x000 0x3 0x0
+#define MX51_PAD_DI1_D1_CS__GPIO3_4 0x2b8 0x6b8 0x984 0x4 0x1
+#define MX51_PAD_DISPB2_SER_DIN__DISP1_PIN1 0x2bc 0x6bc 0x9a4 0x2 0x1
+#define MX51_PAD_DISPB2_SER_DIN__DISPB2_SER_DIN 0x2bc 0x6bc 0x9c4 0x0 0x0
+#define MX51_PAD_DISPB2_SER_DIN__GPIO3_5 0x2bc 0x6bc 0x988 0x4 0x1
+#define MX51_PAD_DISPB2_SER_DIO__DISP1_PIN6 0x2c0 0x6c0 0x000 0x3 0x0
+#define MX51_PAD_DISPB2_SER_DIO__DISPB2_SER_DIO 0x2c0 0x6c0 0x9c4 0x0 0x1
+#define MX51_PAD_DISPB2_SER_DIO__GPIO3_6 0x2c0 0x6c0 0x98c 0x4 0x1
+#define MX51_PAD_DISPB2_SER_CLK__DISP1_PIN17 0x2c4 0x6c4 0x000 0x2 0x0
+#define MX51_PAD_DISPB2_SER_CLK__DISP1_PIN7 0x2c4 0x6c4 0x000 0x3 0x0
+#define MX51_PAD_DISPB2_SER_CLK__DISPB2_SER_CLK 0x2c4 0x6c4 0x000 0x0 0x0
+#define MX51_PAD_DISPB2_SER_CLK__GPIO3_7 0x2c4 0x6c4 0x990 0x4 0x1
+#define MX51_PAD_DISPB2_SER_RS__DISP1_PIN16 0x2c8 0x6c8 0x000 0x2 0x0
+#define MX51_PAD_DISPB2_SER_RS__DISP1_PIN8 0x2c8 0x6c8 0x000 0x3 0x0
+#define MX51_PAD_DISPB2_SER_RS__DISPB2_SER_RS 0x2c8 0x6c8 0x000 0x0 0x0
+#define MX51_PAD_DISPB2_SER_RS__GPIO3_8 0x2c8 0x6c8 0x994 0x4 0x1
+#define MX51_PAD_DISP1_DAT0__DISP1_DAT0 0x2cc 0x6cc 0x000 0x0 0x0
+#define MX51_PAD_DISP1_DAT1__DISP1_DAT1 0x2d0 0x6d0 0x000 0x0 0x0
+#define MX51_PAD_DISP1_DAT2__DISP1_DAT2 0x2d4 0x6d4 0x000 0x0 0x0
+#define MX51_PAD_DISP1_DAT3__DISP1_DAT3 0x2d8 0x6d8 0x000 0x0 0x0
+#define MX51_PAD_DISP1_DAT4__DISP1_DAT4 0x2dc 0x6dc 0x000 0x0 0x0
+#define MX51_PAD_DISP1_DAT5__DISP1_DAT5 0x2e0 0x6e0 0x000 0x0 0x0
+#define MX51_PAD_DISP1_DAT6__BOOT_USB_SRC 0x2e4 0x6e4 0x000 0x7 0x0
+#define MX51_PAD_DISP1_DAT6__DISP1_DAT6 0x2e4 0x6e4 0x000 0x0 0x0
+#define MX51_PAD_DISP1_DAT7__BOOT_EEPROM_CFG 0x2e8 0x6e8 0x000 0x7 0x0
+#define MX51_PAD_DISP1_DAT7__DISP1_DAT7 0x2e8 0x6e8 0x000 0x0 0x0
+#define MX51_PAD_DISP1_DAT8__BOOT_SRC0 0x2ec 0x6ec 0x000 0x7 0x0
+#define MX51_PAD_DISP1_DAT8__DISP1_DAT8 0x2ec 0x6ec 0x000 0x0 0x0
+#define MX51_PAD_DISP1_DAT9__BOOT_SRC1 0x2f0 0x6f0 0x000 0x7 0x0
+#define MX51_PAD_DISP1_DAT9__DISP1_DAT9 0x2f0 0x6f0 0x000 0x0 0x0
+#define MX51_PAD_DISP1_DAT10__BOOT_SPARE_SIZE 0x2f4 0x6f4 0x000 0x7 0x0
+#define MX51_PAD_DISP1_DAT10__DISP1_DAT10 0x2f4 0x6f4 0x000 0x0 0x0
+#define MX51_PAD_DISP1_DAT11__BOOT_LPB_FREQ2 0x2f8 0x6f8 0x000 0x7 0x0
+#define MX51_PAD_DISP1_DAT11__DISP1_DAT11 0x2f8 0x6f8 0x000 0x0 0x0
+#define MX51_PAD_DISP1_DAT12__BOOT_MLC_SEL 0x2fc 0x6fc 0x000 0x7 0x0
+#define MX51_PAD_DISP1_DAT12__DISP1_DAT12 0x2fc 0x6fc 0x000 0x0 0x0
+#define MX51_PAD_DISP1_DAT13__BOOT_MEM_CTL0 0x300 0x700 0x000 0x7 0x0
+#define MX51_PAD_DISP1_DAT13__DISP1_DAT13 0x300 0x700 0x000 0x0 0x0
+#define MX51_PAD_DISP1_DAT14__BOOT_MEM_CTL1 0x304 0x704 0x000 0x7 0x0
+#define MX51_PAD_DISP1_DAT14__DISP1_DAT14 0x304 0x704 0x000 0x0 0x0
+#define MX51_PAD_DISP1_DAT15__BOOT_BUS_WIDTH 0x308 0x708 0x000 0x7 0x0
+#define MX51_PAD_DISP1_DAT15__DISP1_DAT15 0x308 0x708 0x000 0x0 0x0
+#define MX51_PAD_DISP1_DAT16__BOOT_PAGE_SIZE0 0x30c 0x70c 0x000 0x7 0x0
+#define MX51_PAD_DISP1_DAT16__DISP1_DAT16 0x30c 0x70c 0x000 0x0 0x0
+#define MX51_PAD_DISP1_DAT17__BOOT_PAGE_SIZE1 0x310 0x710 0x000 0x7 0x0
+#define MX51_PAD_DISP1_DAT17__DISP1_DAT17 0x310 0x710 0x000 0x0 0x0
+#define MX51_PAD_DISP1_DAT18__BOOT_WEIM_MUXED0 0x314 0x714 0x000 0x7 0x0
+#define MX51_PAD_DISP1_DAT18__DISP1_DAT18 0x314 0x714 0x000 0x0 0x0
+#define MX51_PAD_DISP1_DAT18__DISP2_PIN11 0x314 0x714 0x000 0x5 0x0
+#define MX51_PAD_DISP1_DAT18__DISP2_PIN5 0x314 0x714 0x000 0x4 0x0
+#define MX51_PAD_DISP1_DAT19__BOOT_WEIM_MUXED1 0x318 0x718 0x000 0x7 0x0
+#define MX51_PAD_DISP1_DAT19__DISP1_DAT19 0x318 0x718 0x000 0x0 0x0
+#define MX51_PAD_DISP1_DAT19__DISP2_PIN12 0x318 0x718 0x000 0x5 0x0
+#define MX51_PAD_DISP1_DAT19__DISP2_PIN6 0x318 0x718 0x000 0x4 0x0
+#define MX51_PAD_DISP1_DAT20__BOOT_MEM_TYPE0 0x31c 0x71c 0x000 0x7 0x0
+#define MX51_PAD_DISP1_DAT20__DISP1_DAT20 0x31c 0x71c 0x000 0x0 0x0
+#define MX51_PAD_DISP1_DAT20__DISP2_PIN13 0x31c 0x71c 0x000 0x5 0x0
+#define MX51_PAD_DISP1_DAT20__DISP2_PIN7 0x31c 0x71c 0x000 0x4 0x0
+#define MX51_PAD_DISP1_DAT21__BOOT_MEM_TYPE1 0x320 0x720 0x000 0x7 0x0
+#define MX51_PAD_DISP1_DAT21__DISP1_DAT21 0x320 0x720 0x000 0x0 0x0
+#define MX51_PAD_DISP1_DAT21__DISP2_PIN14 0x320 0x720 0x000 0x5 0x0
+#define MX51_PAD_DISP1_DAT21__DISP2_PIN8 0x320 0x720 0x000 0x4 0x0
+#define MX51_PAD_DISP1_DAT22__BOOT_LPB_FREQ0 0x324 0x724 0x000 0x7 0x0
+#define MX51_PAD_DISP1_DAT22__DISP1_DAT22 0x324 0x724 0x000 0x0 0x0
+#define MX51_PAD_DISP1_DAT22__DISP2_D0_CS 0x324 0x724 0x000 0x6 0x0
+#define MX51_PAD_DISP1_DAT22__DISP2_DAT16 0x324 0x724 0x000 0x5 0x0
+#define MX51_PAD_DISP1_DAT23__BOOT_LPB_FREQ1 0x328 0x728 0x000 0x7 0x0
+#define MX51_PAD_DISP1_DAT23__DISP1_DAT23 0x328 0x728 0x000 0x0 0x0
+#define MX51_PAD_DISP1_DAT23__DISP2_D1_CS 0x328 0x728 0x000 0x6 0x0
+#define MX51_PAD_DISP1_DAT23__DISP2_DAT17 0x328 0x728 0x000 0x5 0x0
+#define MX51_PAD_DISP1_DAT23__DISP2_SER_CS 0x328 0x728 0x000 0x4 0x0
+#define MX51_PAD_DI1_PIN3__DI1_PIN3 0x32c 0x72c 0x000 0x0 0x0
+#define MX51_PAD_DI1_PIN2__DI1_PIN2 0x330 0x734 0x000 0x0 0x0
+#define MX51_PAD_DI_GP2__DISP1_SER_CLK 0x338 0x740 0x000 0x0 0x0
+#define MX51_PAD_DI_GP2__DISP2_WAIT 0x338 0x740 0x9a8 0x2 0x1
+#define MX51_PAD_DI_GP3__CSI1_DATA_EN 0x33c 0x744 0x9a0 0x3 0x1
+#define MX51_PAD_DI_GP3__DISP1_SER_DIO 0x33c 0x744 0x9c0 0x0 0x0
+#define MX51_PAD_DI_GP3__FEC_TX_ER 0x33c 0x744 0x000 0x2 0x0
+#define MX51_PAD_DI2_PIN4__CSI2_DATA_EN 0x340 0x748 0x99c 0x3 0x1
+#define MX51_PAD_DI2_PIN4__DI2_PIN4 0x340 0x748 0x000 0x0 0x0
+#define MX51_PAD_DI2_PIN4__FEC_CRS 0x340 0x748 0x950 0x2 0x1
+#define MX51_PAD_DI2_PIN2__DI2_PIN2 0x344 0x74c 0x000 0x0 0x0
+#define MX51_PAD_DI2_PIN2__FEC_MDC 0x344 0x74c 0x000 0x2 0x0
+#define MX51_PAD_DI2_PIN3__DI2_PIN3 0x348 0x750 0x000 0x0 0x0
+#define MX51_PAD_DI2_PIN3__FEC_MDIO 0x348 0x750 0x954 0x2 0x1
+#define MX51_PAD_DI2_DISP_CLK__DI2_DISP_CLK 0x34c 0x754 0x000 0x0 0x0
+#define MX51_PAD_DI2_DISP_CLK__FEC_RDATA1 0x34c 0x754 0x95c 0x2 0x1
+#define MX51_PAD_DI_GP4__DI2_PIN15 0x350 0x758 0x000 0x4 0x0
+#define MX51_PAD_DI_GP4__DISP1_SER_DIN 0x350 0x758 0x9c0 0x0 0x1
+#define MX51_PAD_DI_GP4__DISP2_PIN1 0x350 0x758 0x000 0x3 0x0
+#define MX51_PAD_DI_GP4__FEC_RDATA2 0x350 0x758 0x960 0x2 0x1
+#define MX51_PAD_DISP2_DAT0__DISP2_DAT0 0x354 0x75c 0x000 0x0 0x0
+#define MX51_PAD_DISP2_DAT0__FEC_RDATA3 0x354 0x75c 0x964 0x2 0x1
+#define MX51_PAD_DISP2_DAT0__KEY_COL6 0x354 0x75c 0x9c8 0x4 0x1
+#define MX51_PAD_DISP2_DAT0__UART3_RXD 0x354 0x75c 0x9f4 0x5 0x8
+#define MX51_PAD_DISP2_DAT0__USBH3_CLK 0x354 0x75c 0x9f8 0x3 0x1
+#define MX51_PAD_DISP2_DAT1__DISP2_DAT1 0x358 0x760 0x000 0x0 0x0
+#define MX51_PAD_DISP2_DAT1__FEC_RX_ER 0x358 0x760 0x970 0x2 0x1
+#define MX51_PAD_DISP2_DAT1__KEY_COL7 0x358 0x760 0x9cc 0x4 0x1
+#define MX51_PAD_DISP2_DAT1__UART3_TXD 0x358 0x760 0x000 0x5 0x0
+#define MX51_PAD_DISP2_DAT1__USBH3_DIR 0x358 0x760 0xa1c 0x3 0x1
+#define MX51_PAD_DISP2_DAT2__DISP2_DAT2 0x35c 0x764 0x000 0x0 0x0
+#define MX51_PAD_DISP2_DAT3__DISP2_DAT3 0x360 0x768 0x000 0x0 0x0
+#define MX51_PAD_DISP2_DAT4__DISP2_DAT4 0x364 0x76c 0x000 0x0 0x0
+#define MX51_PAD_DISP2_DAT5__DISP2_DAT5 0x368 0x770 0x000 0x0 0x0
+#define MX51_PAD_DISP2_DAT6__DISP2_DAT6 0x36c 0x774 0x000 0x0 0x0
+#define MX51_PAD_DISP2_DAT6__FEC_TDATA1 0x36c 0x774 0x000 0x2 0x0
+#define MX51_PAD_DISP2_DAT6__GPIO1_19 0x36c 0x774 0x000 0x5 0x0
+#define MX51_PAD_DISP2_DAT6__KEY_ROW4 0x36c 0x774 0x9d0 0x4 0x1
+#define MX51_PAD_DISP2_DAT6__USBH3_STP 0x36c 0x774 0xa24 0x3 0x1
+#define MX51_PAD_DISP2_DAT7__DISP2_DAT7 0x370 0x778 0x000 0x0 0x0
+#define MX51_PAD_DISP2_DAT7__FEC_TDATA2 0x370 0x778 0x000 0x2 0x0
+#define MX51_PAD_DISP2_DAT7__GPIO1_29 0x370 0x778 0x000 0x5 0x0
+#define MX51_PAD_DISP2_DAT7__KEY_ROW5 0x370 0x778 0x9d4 0x4 0x1
+#define MX51_PAD_DISP2_DAT7__USBH3_NXT 0x370 0x778 0xa20 0x3 0x1
+#define MX51_PAD_DISP2_DAT8__DISP2_DAT8 0x374 0x77c 0x000 0x0 0x0
+#define MX51_PAD_DISP2_DAT8__FEC_TDATA3 0x374 0x77c 0x000 0x2 0x0
+#define MX51_PAD_DISP2_DAT8__GPIO1_30 0x374 0x77c 0x000 0x5 0x0
+#define MX51_PAD_DISP2_DAT8__KEY_ROW6 0x374 0x77c 0x9d8 0x4 0x1
+#define MX51_PAD_DISP2_DAT8__USBH3_DATA0 0x374 0x77c 0x9fc 0x3 0x1
+#define MX51_PAD_DISP2_DAT9__AUD6_RXC 0x378 0x780 0x8f4 0x4 0x1
+#define MX51_PAD_DISP2_DAT9__DISP2_DAT9 0x378 0x780 0x000 0x0 0x0
+#define MX51_PAD_DISP2_DAT9__FEC_TX_EN 0x378 0x780 0x000 0x2 0x0
+#define MX51_PAD_DISP2_DAT9__GPIO1_31 0x378 0x780 0x000 0x5 0x0
+#define MX51_PAD_DISP2_DAT9__USBH3_DATA1 0x378 0x780 0xa00 0x3 0x1
+#define MX51_PAD_DISP2_DAT10__DISP2_DAT10 0x37c 0x784 0x000 0x0 0x0
+#define MX51_PAD_DISP2_DAT10__DISP2_SER_CS 0x37c 0x784 0x000 0x5 0x0
+#define MX51_PAD_DISP2_DAT10__FEC_COL 0x37c 0x784 0x94c 0x2 0x1
+#define MX51_PAD_DISP2_DAT10__KEY_ROW7 0x37c 0x784 0x9dc 0x4 0x1
+#define MX51_PAD_DISP2_DAT10__USBH3_DATA2 0x37c 0x784 0xa04 0x3 0x1
+#define MX51_PAD_DISP2_DAT11__AUD6_TXD 0x380 0x788 0x8f0 0x4 0x1
+#define MX51_PAD_DISP2_DAT11__DISP2_DAT11 0x380 0x788 0x000 0x0 0x0
+#define MX51_PAD_DISP2_DAT11__FEC_RX_CLK 0x380 0x788 0x968 0x2 0x1
+#define MX51_PAD_DISP2_DAT11__GPIO1_10 0x380 0x788 0x000 0x7 0x0
+#define MX51_PAD_DISP2_DAT11__USBH3_DATA3 0x380 0x788 0xa08 0x3 0x1
+#define MX51_PAD_DISP2_DAT12__AUD6_RXD 0x384 0x78c 0x8ec 0x4 0x1
+#define MX51_PAD_DISP2_DAT12__DISP2_DAT12 0x384 0x78c 0x000 0x0 0x0
+#define MX51_PAD_DISP2_DAT12__FEC_RX_DV 0x384 0x78c 0x96c 0x2 0x1
+#define MX51_PAD_DISP2_DAT12__USBH3_DATA4 0x384 0x78c 0xa0c 0x3 0x1
+#define MX51_PAD_DISP2_DAT13__AUD6_TXC 0x388 0x790 0x8fc 0x4 0x1
+#define MX51_PAD_DISP2_DAT13__DISP2_DAT13 0x388 0x790 0x000 0x0 0x0
+#define MX51_PAD_DISP2_DAT13__FEC_TX_CLK 0x388 0x790 0x974 0x2 0x1
+#define MX51_PAD_DISP2_DAT13__USBH3_DATA5 0x388 0x790 0xa10 0x3 0x1
+#define MX51_PAD_DISP2_DAT14__AUD6_TXFS 0x38c 0x794 0x900 0x4 0x1
+#define MX51_PAD_DISP2_DAT14__DISP2_DAT14 0x38c 0x794 0x000 0x0 0x0
+#define MX51_PAD_DISP2_DAT14__FEC_RDATA0 0x38c 0x794 0x958 0x2 0x1
+#define MX51_PAD_DISP2_DAT14__USBH3_DATA6 0x38c 0x794 0xa14 0x3 0x1
+#define MX51_PAD_DISP2_DAT15__AUD6_RXFS 0x390 0x798 0x8f8 0x4 0x1
+#define MX51_PAD_DISP2_DAT15__DISP1_SER_CS 0x390 0x798 0x000 0x5 0x0
+#define MX51_PAD_DISP2_DAT15__DISP2_DAT15 0x390 0x798 0x000 0x0 0x0
+#define MX51_PAD_DISP2_DAT15__FEC_TDATA0 0x390 0x798 0x000 0x2 0x0
+#define MX51_PAD_DISP2_DAT15__USBH3_DATA7 0x390 0x798 0xa18 0x3 0x1
+#define MX51_PAD_SD1_CMD__AUD5_RXFS 0x394 0x79c 0x8e0 0x1 0x1
+#define MX51_PAD_SD1_CMD__CSPI_MOSI 0x394 0x79c 0x91c 0x2 0x2
+#define MX51_PAD_SD1_CMD__SD1_CMD 0x394 0x79c 0x000 0x0 0x0
+#define MX51_PAD_SD1_CLK__AUD5_RXC 0x398 0x7a0 0x8dc 0x1 0x1
+#define MX51_PAD_SD1_CLK__CSPI_SCLK 0x398 0x7a0 0x914 0x2 0x2
+#define MX51_PAD_SD1_CLK__SD1_CLK 0x398 0x7a0 0x000 0x0 0x0
+#define MX51_PAD_SD1_DATA0__AUD5_TXD 0x39c 0x7a4 0x8d8 0x1 0x2
+#define MX51_PAD_SD1_DATA0__CSPI_MISO 0x39c 0x7a4 0x918 0x2 0x1
+#define MX51_PAD_SD1_DATA0__SD1_DATA0 0x39c 0x7a4 0x000 0x0 0x0
+#define MX51_PAD_EIM_DA0__EIM_DA0 0x01c 0x000 0x000 0x0 0x0
+#define MX51_PAD_EIM_DA1__EIM_DA1 0x020 0x000 0x000 0x0 0x0
+#define MX51_PAD_EIM_DA2__EIM_DA2 0x024 0x000 0x000 0x0 0x0
+#define MX51_PAD_EIM_DA3__EIM_DA3 0x028 0x000 0x000 0x0 0x0
+#define MX51_PAD_SD1_DATA1__AUD5_RXD 0x3a0 0x7a8 0x8d4 0x1 0x2
+#define MX51_PAD_SD1_DATA1__SD1_DATA1 0x3a0 0x7a8 0x000 0x0 0x0
+#define MX51_PAD_EIM_DA4__EIM_DA4 0x02c 0x000 0x000 0x0 0x0
+#define MX51_PAD_EIM_DA5__EIM_DA5 0x030 0x000 0x000 0x0 0x0
+#define MX51_PAD_EIM_DA6__EIM_DA6 0x034 0x000 0x000 0x0 0x0
+#define MX51_PAD_EIM_DA7__EIM_DA7 0x038 0x000 0x000 0x0 0x0
+#define MX51_PAD_SD1_DATA2__AUD5_TXC 0x3a4 0x7ac 0x8e4 0x1 0x2
+#define MX51_PAD_SD1_DATA2__SD1_DATA2 0x3a4 0x7ac 0x000 0x0 0x0
+#define MX51_PAD_EIM_DA10__EIM_DA10 0x044 0x000 0x000 0x0 0x0
+#define MX51_PAD_EIM_DA11__EIM_DA11 0x048 0x000 0x000 0x0 0x0
+#define MX51_PAD_EIM_DA8__EIM_DA8 0x03c 0x000 0x000 0x0 0x0
+#define MX51_PAD_EIM_DA9__EIM_DA9 0x040 0x000 0x000 0x0 0x0
+#define MX51_PAD_SD1_DATA3__AUD5_TXFS 0x3a8 0x7b0 0x8e8 0x1 0x2
+#define MX51_PAD_SD1_DATA3__CSPI_SS1 0x3a8 0x7b0 0x920 0x2 0x1
+#define MX51_PAD_SD1_DATA3__SD1_DATA3 0x3a8 0x7b0 0x000 0x0 0x0
+#define MX51_PAD_GPIO1_0__CSPI_SS2 0x3ac 0x7b4 0x924 0x2 0x0
+#define MX51_PAD_GPIO1_0__GPIO1_0 0x3ac 0x7b4 0x000 0x1 0x0
+#define MX51_PAD_GPIO1_0__SD1_CD 0x3ac 0x7b4 0x000 0x0 0x0
+#define MX51_PAD_GPIO1_1__CSPI_MISO 0x3b0 0x7b8 0x918 0x2 0x2
+#define MX51_PAD_GPIO1_1__GPIO1_1 0x3b0 0x7b8 0x000 0x1 0x0
+#define MX51_PAD_GPIO1_1__SD1_WP 0x3b0 0x7b8 0x000 0x0 0x0
+#define MX51_PAD_EIM_DA12__EIM_DA12 0x04c 0x000 0x000 0x0 0x0
+#define MX51_PAD_EIM_DA13__EIM_DA13 0x050 0x000 0x000 0x0 0x0
+#define MX51_PAD_EIM_DA14__EIM_DA14 0x054 0x000 0x000 0x0 0x0
+#define MX51_PAD_EIM_DA15__EIM_DA15 0x058 0x000 0x000 0x0 0x0
+#define MX51_PAD_SD2_CMD__CSPI_MOSI 0x3b4 0x7bc 0x91c 0x2 0x3
+#define MX51_PAD_SD2_CMD__I2C1_SCL 0x3b4 0x7bc 0x9b0 0x1 0x2
+#define MX51_PAD_SD2_CMD__SD2_CMD 0x3b4 0x7bc 0x000 0x0 0x0
+#define MX51_PAD_SD2_CLK__CSPI_SCLK 0x3b8 0x7c0 0x914 0x2 0x3
+#define MX51_PAD_SD2_CLK__I2C1_SDA 0x3b8 0x7c0 0x9b4 0x1 0x2
+#define MX51_PAD_SD2_CLK__SD2_CLK 0x3b8 0x7c0 0x000 0x0 0x0
+#define MX51_PAD_SD2_DATA0__CSPI_MISO 0x3bc 0x7c4 0x918 0x2 0x3
+#define MX51_PAD_SD2_DATA0__SD1_DAT4 0x3bc 0x7c4 0x000 0x1 0x0
+#define MX51_PAD_SD2_DATA0__SD2_DATA0 0x3bc 0x7c4 0x000 0x0 0x0
+#define MX51_PAD_SD2_DATA1__SD1_DAT5 0x3c0 0x7c8 0x000 0x1 0x0
+#define MX51_PAD_SD2_DATA1__SD2_DATA1 0x3c0 0x7c8 0x000 0x0 0x0
+#define MX51_PAD_SD2_DATA1__USBH3_H2_DP 0x3c0 0x7c8 0x000 0x2 0x0
+#define MX51_PAD_SD2_DATA2__SD1_DAT6 0x3c4 0x7cc 0x000 0x1 0x0
+#define MX51_PAD_SD2_DATA2__SD2_DATA2 0x3c4 0x7cc 0x000 0x0 0x0
+#define MX51_PAD_SD2_DATA2__USBH3_H2_DM 0x3c4 0x7cc 0x000 0x2 0x0
+#define MX51_PAD_SD2_DATA3__CSPI_SS2 0x3c8 0x7d0 0x924 0x2 0x1
+#define MX51_PAD_SD2_DATA3__SD1_DAT7 0x3c8 0x7d0 0x000 0x1 0x0
+#define MX51_PAD_SD2_DATA3__SD2_DATA3 0x3c8 0x7d0 0x000 0x0 0x0
+#define MX51_PAD_GPIO1_2__CCM_OUT_2 0x3cc 0x7d4 0x000 0x5 0x0
+#define MX51_PAD_GPIO1_2__GPIO1_2 0x3cc 0x7d4 0x000 0x0 0x0
+#define MX51_PAD_GPIO1_2__I2C2_SCL 0x3cc 0x7d4 0x9b8 0x2 0x3
+#define MX51_PAD_GPIO1_2__PLL1_BYP 0x3cc 0x7d4 0x90c 0x7 0x1
+#define MX51_PAD_GPIO1_2__PWM1_PWMO 0x3cc 0x7d4 0x000 0x1 0x0
+#define MX51_PAD_GPIO1_3__GPIO1_3 0x3d0 0x7d8 0x000 0x0 0x0
+#define MX51_PAD_GPIO1_3__I2C2_SDA 0x3d0 0x7d8 0x9bc 0x2 0x3
+#define MX51_PAD_GPIO1_3__PLL2_BYP 0x3d0 0x7d8 0x910 0x7 0x1
+#define MX51_PAD_GPIO1_3__PWM2_PWMO 0x3d0 0x7d8 0x000 0x1 0x0
+#define MX51_PAD_PMIC_INT_REQ__PMIC_INT_REQ 0x3d4 0x7fc 0x000 0x0 0x0
+#define MX51_PAD_PMIC_INT_REQ__PMIC_PMU_IRQ_B 0x3d4 0x7fc 0x000 0x1 0x0
+#define MX51_PAD_GPIO1_4__DISP2_EXT_CLK 0x3d8 0x804 0x908 0x4 0x1
+#define MX51_PAD_GPIO1_4__EIM_RDY 0x3d8 0x804 0x938 0x3 0x1
+#define MX51_PAD_GPIO1_4__GPIO1_4 0x3d8 0x804 0x000 0x0 0x0
+#define MX51_PAD_GPIO1_4__WDOG1_WDOG_B 0x3d8 0x804 0x000 0x2 0x0
+#define MX51_PAD_GPIO1_5__CSI2_MCLK 0x3dc 0x808 0x000 0x6 0x0
+#define MX51_PAD_GPIO1_5__DISP2_PIN16 0x3dc 0x808 0x000 0x3 0x0
+#define MX51_PAD_GPIO1_5__GPIO1_5 0x3dc 0x808 0x000 0x0 0x0
+#define MX51_PAD_GPIO1_5__WDOG2_WDOG_B 0x3dc 0x808 0x000 0x2 0x0
+#define MX51_PAD_GPIO1_6__DISP2_PIN17 0x3e0 0x80c 0x000 0x4 0x0
+#define MX51_PAD_GPIO1_6__GPIO1_6 0x3e0 0x80c 0x000 0x0 0x0
+#define MX51_PAD_GPIO1_6__REF_EN_B 0x3e0 0x80c 0x000 0x3 0x0
+#define MX51_PAD_GPIO1_7__CCM_OUT_0 0x3e4 0x810 0x000 0x3 0x0
+#define MX51_PAD_GPIO1_7__GPIO1_7 0x3e4 0x810 0x000 0x0 0x0
+#define MX51_PAD_GPIO1_7__SD2_WP 0x3e4 0x810 0x000 0x6 0x0
+#define MX51_PAD_GPIO1_7__SPDIF_OUT1 0x3e4 0x810 0x000 0x2 0x0
+#define MX51_PAD_GPIO1_8__CSI2_DATA_EN 0x3e8 0x814 0x99c 0x2 0x2
+#define MX51_PAD_GPIO1_8__GPIO1_8 0x3e8 0x814 0x000 0x0 0x0
+#define MX51_PAD_GPIO1_8__SD2_CD 0x3e8 0x814 0x000 0x6 0x0
+#define MX51_PAD_GPIO1_8__USBH3_PWR 0x3e8 0x814 0x000 0x1 0x0
+#define MX51_PAD_GPIO1_9__CCM_OUT_1 0x3ec 0x818 0x000 0x3 0x0
+#define MX51_PAD_GPIO1_9__DISP2_D1_CS 0x3ec 0x818 0x000 0x2 0x0
+#define MX51_PAD_GPIO1_9__DISP2_SER_CS 0x3ec 0x818 0x000 0x7 0x0
+#define MX51_PAD_GPIO1_9__GPIO1_9 0x3ec 0x818 0x000 0x0 0x0
+#define MX51_PAD_GPIO1_9__SD2_LCTL 0x3ec 0x818 0x000 0x6 0x0
+#define MX51_PAD_GPIO1_9__USBH3_OC 0x3ec 0x818 0x000 0x1 0x0
+
+#endif /* __DTS_IMX51_PINFUNC_H */
diff --git a/arch/arm/dts/imx51.dtsi b/arch/arm/dts/imx51.dtsi
new file mode 100644
index 0000000..7ebb46c
--- /dev/null
+++ b/arch/arm/dts/imx51.dtsi
@@ -0,0 +1,654 @@
+// SPDX-License-Identifier: GPL-2.0+
+//
+// Copyright 2011 Freescale Semiconductor, Inc.
+// Copyright 2011 Linaro Ltd.
+
+#include "imx51-pinfunc.h"
+#include <dt-bindings/clock/imx5-clock.h>
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/input/input.h>
+#include <dt-bindings/interrupt-controller/irq.h>
+
+/ {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ /*
+ * The decompressor and also some bootloaders rely on a
+ * pre-existing /chosen node to be available to insert the
+ * command line and merge other ATAGS info.
+ */
+ chosen {};
+
+ aliases {
+ ethernet0 = &fec;
+ gpio0 = &gpio1;
+ gpio1 = &gpio2;
+ gpio2 = &gpio3;
+ gpio3 = &gpio4;
+ i2c0 = &i2c1;
+ i2c1 = &i2c2;
+ mmc0 = &esdhc1;
+ mmc1 = &esdhc2;
+ mmc2 = &esdhc3;
+ mmc3 = &esdhc4;
+ serial0 = &uart1;
+ serial1 = &uart2;
+ serial2 = &uart3;
+ spi0 = &ecspi1;
+ spi1 = &ecspi2;
+ spi2 = &cspi;
+ };
+
+ tzic: tz-interrupt-controller@e0000000 {
+ compatible = "fsl,imx51-tzic", "fsl,tzic";
+ interrupt-controller;
+ #interrupt-cells = <1>;
+ reg = <0xe0000000 0x4000>;
+ };
+
+ clocks {
+ ckil {
+ compatible = "fsl,imx-ckil", "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <32768>;
+ };
+
+ ckih1 {
+ compatible = "fsl,imx-ckih1", "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <0>;
+ };
+
+ ckih2 {
+ compatible = "fsl,imx-ckih2", "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <0>;
+ };
+
+ osc {
+ compatible = "fsl,imx-osc", "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <24000000>;
+ };
+ };
+
+ cpus {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ cpu: cpu@0 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a8";
+ reg = <0>;
+ clock-latency = <62500>;
+ clocks = <&clks IMX5_CLK_CPU_PODF>;
+ clock-names = "cpu";
+ operating-points = <
+ 166000 1000000
+ 600000 1050000
+ 800000 1100000
+ >;
+ voltage-tolerance = <5>;
+ };
+ };
+
+ pmu: pmu {
+ compatible = "arm,cortex-a8-pmu";
+ interrupt-parent = <&tzic>;
+ interrupts = <77>;
+ };
+
+ usbphy0: usbphy0 {
+ compatible = "usb-nop-xceiv";
+ clocks = <&clks IMX5_CLK_USB_PHY_GATE>;
+ clock-names = "main_clk";
+ #phy-cells = <0>;
+ };
+
+ capture-subsystem {
+ compatible = "fsl,imx-capture-subsystem";
+ ports = <&ipu_csi0>, <&ipu_csi1>;
+ };
+
+ display-subsystem {
+ compatible = "fsl,imx-display-subsystem";
+ ports = <&ipu_di0>, <&ipu_di1>;
+ };
+
+ soc {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ compatible = "simple-bus";
+ interrupt-parent = <&tzic>;
+ ranges;
+
+ iram: sram@1ffe0000 {
+ compatible = "mmio-sram";
+ reg = <0x1ffe0000 0x20000>;
+ };
+
+ gpu: gpu@30000000 {
+ compatible = "amd,imageon-200.1", "amd,imageon";
+ reg = <0x30000000 0x20000>;
+ reg-names = "kgsl_3d0_reg_memory";
+ interrupts = <12>;
+ interrupt-names = "kgsl_3d0_irq";
+ clocks = <&clks IMX5_CLK_GPU3D_GATE>, <&clks IMX5_CLK_GARB_GATE>;
+ clock-names = "core_clk", "mem_iface_clk";
+ };
+
+ ipu: ipu@40000000 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ compatible = "fsl,imx51-ipu";
+ reg = <0x40000000 0x20000000>;
+ interrupts = <11 10>;
+ clocks = <&clks IMX5_CLK_IPU_GATE>,
+ <&clks IMX5_CLK_IPU_DI0_GATE>,
+ <&clks IMX5_CLK_IPU_DI1_GATE>;
+ clock-names = "bus", "di0", "di1";
+ resets = <&src 2>;
+
+ ipu_csi0: port@0 {
+ reg = <0>;
+ };
+
+ ipu_csi1: port@1 {
+ reg = <1>;
+ };
+
+ ipu_di0: port@2 {
+ reg = <2>;
+
+ ipu_di0_disp1: endpoint {
+ };
+ };
+
+ ipu_di1: port@3 {
+ reg = <3>;
+
+ ipu_di1_disp2: endpoint {
+ };
+ };
+ };
+
+ bus@70000000 { /* AIPS1 */
+ compatible = "fsl,aips-bus", "simple-bus";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ reg = <0x70000000 0x10000000>;
+ ranges;
+
+ spba@70000000 {
+ compatible = "fsl,spba-bus", "simple-bus";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ reg = <0x70000000 0x40000>;
+ ranges;
+
+ esdhc1: mmc@70004000 {
+ compatible = "fsl,imx51-esdhc";
+ reg = <0x70004000 0x4000>;
+ interrupts = <1>;
+ clocks = <&clks IMX5_CLK_ESDHC1_IPG_GATE>,
+ <&clks IMX5_CLK_DUMMY>,
+ <&clks IMX5_CLK_ESDHC1_PER_GATE>;
+ clock-names = "ipg", "ahb", "per";
+ status = "disabled";
+ };
+
+ esdhc2: mmc@70008000 {
+ compatible = "fsl,imx51-esdhc";
+ reg = <0x70008000 0x4000>;
+ interrupts = <2>;
+ clocks = <&clks IMX5_CLK_ESDHC2_IPG_GATE>,
+ <&clks IMX5_CLK_DUMMY>,
+ <&clks IMX5_CLK_ESDHC2_PER_GATE>;
+ clock-names = "ipg", "ahb", "per";
+ bus-width = <4>;
+ status = "disabled";
+ };
+
+ uart3: serial@7000c000 {
+ compatible = "fsl,imx51-uart", "fsl,imx21-uart";
+ reg = <0x7000c000 0x4000>;
+ interrupts = <33>;
+ clocks = <&clks IMX5_CLK_UART3_IPG_GATE>,
+ <&clks IMX5_CLK_UART3_PER_GATE>;
+ clock-names = "ipg", "per";
+ status = "disabled";
+ };
+
+ ecspi1: spi@70010000 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ compatible = "fsl,imx51-ecspi";
+ reg = <0x70010000 0x4000>;
+ interrupts = <36>;
+ clocks = <&clks IMX5_CLK_ECSPI1_IPG_GATE>,
+ <&clks IMX5_CLK_ECSPI1_PER_GATE>;
+ clock-names = "ipg", "per";
+ status = "disabled";
+ };
+
+ ssi2: ssi@70014000 {
+ #sound-dai-cells = <0>;
+ compatible = "fsl,imx51-ssi", "fsl,imx21-ssi";
+ reg = <0x70014000 0x4000>;
+ interrupts = <30>;
+ clocks = <&clks IMX5_CLK_SSI2_IPG_GATE>,
+ <&clks IMX5_CLK_SSI2_ROOT_GATE>;
+ clock-names = "ipg", "baud";
+ dmas = <&sdma 24 1 0>,
+ <&sdma 25 1 0>;
+ dma-names = "rx", "tx";
+ fsl,fifo-depth = <15>;
+ status = "disabled";
+ };
+
+ esdhc3: mmc@70020000 {
+ compatible = "fsl,imx51-esdhc";
+ reg = <0x70020000 0x4000>;
+ interrupts = <3>;
+ clocks = <&clks IMX5_CLK_ESDHC3_IPG_GATE>,
+ <&clks IMX5_CLK_DUMMY>,
+ <&clks IMX5_CLK_ESDHC3_PER_GATE>;
+ clock-names = "ipg", "ahb", "per";
+ bus-width = <4>;
+ status = "disabled";
+ };
+
+ esdhc4: mmc@70024000 {
+ compatible = "fsl,imx51-esdhc";
+ reg = <0x70024000 0x4000>;
+ interrupts = <4>;
+ clocks = <&clks IMX5_CLK_ESDHC4_IPG_GATE>,
+ <&clks IMX5_CLK_DUMMY>,
+ <&clks IMX5_CLK_ESDHC4_PER_GATE>;
+ clock-names = "ipg", "ahb", "per";
+ bus-width = <4>;
+ status = "disabled";
+ };
+ };
+
+ aipstz1: bridge@73f00000 {
+ compatible = "fsl,imx51-aipstz";
+ reg = <0x73f00000 0x60>;
+ };
+
+ usbotg: usb@73f80000 {
+ compatible = "fsl,imx51-usb", "fsl,imx27-usb";
+ reg = <0x73f80000 0x0200>;
+ interrupts = <18>;
+ clocks = <&clks IMX5_CLK_USBOH3_GATE>;
+ fsl,usbmisc = <&usbmisc 0>;
+ fsl,usbphy = <&usbphy0>;
+ status = "disabled";
+ };
+
+ usbh1: usb@73f80200 {
+ compatible = "fsl,imx51-usb", "fsl,imx27-usb";
+ reg = <0x73f80200 0x0200>;
+ interrupts = <14>;
+ clocks = <&clks IMX5_CLK_USBOH3_GATE>;
+ fsl,usbmisc = <&usbmisc 1>;
+ dr_mode = "host";
+ status = "disabled";
+ };
+
+ usbh2: usb@73f80400 {
+ compatible = "fsl,imx51-usb", "fsl,imx27-usb";
+ reg = <0x73f80400 0x0200>;
+ interrupts = <16>;
+ clocks = <&clks IMX5_CLK_USBOH3_GATE>;
+ fsl,usbmisc = <&usbmisc 2>;
+ dr_mode = "host";
+ status = "disabled";
+ };
+
+ usbh3: usb@73f80600 {
+ compatible = "fsl,imx51-usb", "fsl,imx27-usb";
+ reg = <0x73f80600 0x0200>;
+ interrupts = <17>;
+ clocks = <&clks IMX5_CLK_USBOH3_GATE>;
+ fsl,usbmisc = <&usbmisc 3>;
+ dr_mode = "host";
+ status = "disabled";
+ };
+
+ usbmisc: usbmisc@73f80800 {
+ #index-cells = <1>;
+ compatible = "fsl,imx51-usbmisc";
+ reg = <0x73f80800 0x200>;
+ clocks = <&clks IMX5_CLK_USBOH3_GATE>;
+ };
+
+ gpio1: gpio@73f84000 {
+ compatible = "fsl,imx51-gpio", "fsl,imx35-gpio";
+ reg = <0x73f84000 0x4000>;
+ interrupts = <50 51>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+
+ gpio2: gpio@73f88000 {
+ compatible = "fsl,imx51-gpio", "fsl,imx35-gpio";
+ reg = <0x73f88000 0x4000>;
+ interrupts = <52 53>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+
+ gpio3: gpio@73f8c000 {
+ compatible = "fsl,imx51-gpio", "fsl,imx35-gpio";
+ reg = <0x73f8c000 0x4000>;
+ interrupts = <54 55>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+
+ gpio4: gpio@73f90000 {
+ compatible = "fsl,imx51-gpio", "fsl,imx35-gpio";
+ reg = <0x73f90000 0x4000>;
+ interrupts = <56 57>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+
+ kpp: kpp@73f94000 {
+ compatible = "fsl,imx51-kpp", "fsl,imx21-kpp";
+ reg = <0x73f94000 0x4000>;
+ interrupts = <60>;
+ clocks = <&clks IMX5_CLK_DUMMY>;
+ status = "disabled";
+ };
+
+ wdog1: watchdog@73f98000 {
+ compatible = "fsl,imx51-wdt", "fsl,imx21-wdt";
+ reg = <0x73f98000 0x4000>;
+ interrupts = <58>;
+ clocks = <&clks IMX5_CLK_DUMMY>;
+ };
+
+ wdog2: watchdog@73f9c000 {
+ compatible = "fsl,imx51-wdt", "fsl,imx21-wdt";
+ reg = <0x73f9c000 0x4000>;
+ interrupts = <59>;
+ clocks = <&clks IMX5_CLK_DUMMY>;
+ status = "disabled";
+ };
+
+ gpt: timer@73fa0000 {
+ compatible = "fsl,imx51-gpt", "fsl,imx31-gpt";
+ reg = <0x73fa0000 0x4000>;
+ interrupts = <39>;
+ clocks = <&clks IMX5_CLK_GPT_IPG_GATE>,
+ <&clks IMX5_CLK_GPT_HF_GATE>;
+ clock-names = "ipg", "per";
+ };
+
+ iomuxc: iomuxc@73fa8000 {
+ compatible = "fsl,imx51-iomuxc";
+ reg = <0x73fa8000 0x4000>;
+ };
+
+ pwm1: pwm@73fb4000 {
+ #pwm-cells = <3>;
+ compatible = "fsl,imx51-pwm", "fsl,imx27-pwm";
+ reg = <0x73fb4000 0x4000>;
+ clocks = <&clks IMX5_CLK_PWM1_IPG_GATE>,
+ <&clks IMX5_CLK_PWM1_HF_GATE>;
+ clock-names = "ipg", "per";
+ interrupts = <61>;
+ };
+
+ pwm2: pwm@73fb8000 {
+ #pwm-cells = <3>;
+ compatible = "fsl,imx51-pwm", "fsl,imx27-pwm";
+ reg = <0x73fb8000 0x4000>;
+ clocks = <&clks IMX5_CLK_PWM2_IPG_GATE>,
+ <&clks IMX5_CLK_PWM2_HF_GATE>;
+ clock-names = "ipg", "per";
+ interrupts = <94>;
+ };
+
+ uart1: serial@73fbc000 {
+ compatible = "fsl,imx51-uart", "fsl,imx21-uart";
+ reg = <0x73fbc000 0x4000>;
+ interrupts = <31>;
+ clocks = <&clks IMX5_CLK_UART1_IPG_GATE>,
+ <&clks IMX5_CLK_UART1_PER_GATE>;
+ clock-names = "ipg", "per";
+ status = "disabled";
+ };
+
+ uart2: serial@73fc0000 {
+ compatible = "fsl,imx51-uart", "fsl,imx21-uart";
+ reg = <0x73fc0000 0x4000>;
+ interrupts = <32>;
+ clocks = <&clks IMX5_CLK_UART2_IPG_GATE>,
+ <&clks IMX5_CLK_UART2_PER_GATE>;
+ clock-names = "ipg", "per";
+ status = "disabled";
+ };
+
+ src: reset-controller@73fd0000 {
+ compatible = "fsl,imx51-src";
+ reg = <0x73fd0000 0x4000>;
+ interrupts = <75>;
+ #reset-cells = <1>;
+ };
+
+ clks: ccm@73fd4000{
+ compatible = "fsl,imx51-ccm";
+ reg = <0x73fd4000 0x4000>;
+ interrupts = <0 71 0x04 0 72 0x04>;
+ #clock-cells = <1>;
+ };
+ };
+
+ bus@80000000 { /* AIPS2 */
+ compatible = "fsl,aips-bus", "simple-bus";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ reg = <0x80000000 0x10000000>;
+ ranges;
+
+ aipstz2: bridge@83f00000 {
+ compatible = "fsl,imx51-aipstz";
+ reg = <0x83f00000 0x60>;
+ };
+
+ iim: efuse@83f98000 {
+ compatible = "fsl,imx51-iim", "fsl,imx27-iim";
+ reg = <0x83f98000 0x4000>;
+ interrupts = <69>;
+ clocks = <&clks IMX5_CLK_IIM_GATE>;
+ };
+
+ tigerp: tigerp@83fa0000 {
+ compatible = "fsl,imx51-tigerp";
+ reg = <0x83fa0000 0x28>;
+ };
+
+ owire: owire@83fa4000 {
+ compatible = "fsl,imx51-owire", "fsl,imx21-owire";
+ reg = <0x83fa4000 0x4000>;
+ interrupts = <88>;
+ clocks = <&clks IMX5_CLK_OWIRE_GATE>;
+ status = "disabled";
+ };
+
+ ecspi2: spi@83fac000 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ compatible = "fsl,imx51-ecspi";
+ reg = <0x83fac000 0x4000>;
+ interrupts = <37>;
+ clocks = <&clks IMX5_CLK_ECSPI2_IPG_GATE>,
+ <&clks IMX5_CLK_ECSPI2_PER_GATE>;
+ clock-names = "ipg", "per";
+ status = "disabled";
+ };
+
+ sdma: sdma@83fb0000 {
+ compatible = "fsl,imx51-sdma", "fsl,imx35-sdma";
+ reg = <0x83fb0000 0x4000>;
+ interrupts = <6>;
+ clocks = <&clks IMX5_CLK_SDMA_GATE>,
+ <&clks IMX5_CLK_AHB>;
+ clock-names = "ipg", "ahb";
+ #dma-cells = <3>;
+ fsl,sdma-ram-script-name = "imx/sdma/sdma-imx51.bin";
+ };
+
+ cspi: spi@83fc0000 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ compatible = "fsl,imx51-cspi", "fsl,imx35-cspi";
+ reg = <0x83fc0000 0x4000>;
+ interrupts = <38>;
+ clocks = <&clks IMX5_CLK_CSPI_IPG_GATE>,
+ <&clks IMX5_CLK_CSPI_IPG_GATE>;
+ clock-names = "ipg", "per";
+ status = "disabled";
+ };
+
+ i2c2: i2c@83fc4000 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ compatible = "fsl,imx51-i2c", "fsl,imx21-i2c";
+ reg = <0x83fc4000 0x4000>;
+ interrupts = <63>;
+ clocks = <&clks IMX5_CLK_I2C2_GATE>;
+ status = "disabled";
+ };
+
+ i2c1: i2c@83fc8000 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ compatible = "fsl,imx51-i2c", "fsl,imx21-i2c";
+ reg = <0x83fc8000 0x4000>;
+ interrupts = <62>;
+ clocks = <&clks IMX5_CLK_I2C1_GATE>;
+ status = "disabled";
+ };
+
+ ssi1: ssi@83fcc000 {
+ #sound-dai-cells = <0>;
+ compatible = "fsl,imx51-ssi", "fsl,imx21-ssi";
+ reg = <0x83fcc000 0x4000>;
+ interrupts = <29>;
+ clocks = <&clks IMX5_CLK_SSI1_IPG_GATE>,
+ <&clks IMX5_CLK_SSI1_ROOT_GATE>;
+ clock-names = "ipg", "baud";
+ dmas = <&sdma 28 0 0>,
+ <&sdma 29 0 0>;
+ dma-names = "rx", "tx";
+ fsl,fifo-depth = <15>;
+ status = "disabled";
+ };
+
+ audmux: audmux@83fd0000 {
+ compatible = "fsl,imx51-audmux", "fsl,imx31-audmux";
+ reg = <0x83fd0000 0x4000>;
+ clocks = <&clks IMX5_CLK_DUMMY>;
+ clock-names = "audmux";
+ status = "disabled";
+ };
+
+ m4if: m4if@83fd8000 {
+ compatible = "fsl,imx51-m4if";
+ reg = <0x83fd8000 0x1000>;
+ };
+
+ weim: weim@83fda000 {
+ #address-cells = <2>;
+ #size-cells = <1>;
+ compatible = "fsl,imx51-weim";
+ reg = <0x83fda000 0x1000>;
+ clocks = <&clks IMX5_CLK_EMI_SLOW_GATE>;
+ ranges = <
+ 0 0 0xb0000000 0x08000000
+ 1 0 0xb8000000 0x08000000
+ 2 0 0xc0000000 0x08000000
+ 3 0 0xc8000000 0x04000000
+ 4 0 0xcc000000 0x02000000
+ 5 0 0xce000000 0x02000000
+ >;
+ status = "disabled";
+ };
+
+ nfc: nand@83fdb000 {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ compatible = "fsl,imx51-nand";
+ reg = <0x83fdb000 0x1000 0xcfff0000 0x10000>;
+ interrupts = <8>;
+ clocks = <&clks IMX5_CLK_NFC_GATE>;
+ status = "disabled";
+ };
+
+ pata: pata@83fe0000 {
+ compatible = "fsl,imx51-pata", "fsl,imx27-pata";
+ reg = <0x83fe0000 0x4000>;
+ interrupts = <70>;
+ clocks = <&clks IMX5_CLK_PATA_GATE>;
+ status = "disabled";
+ };
+
+ ssi3: ssi@83fe8000 {
+ #sound-dai-cells = <0>;
+ compatible = "fsl,imx51-ssi", "fsl,imx21-ssi";
+ reg = <0x83fe8000 0x4000>;
+ interrupts = <96>;
+ clocks = <&clks IMX5_CLK_SSI3_IPG_GATE>,
+ <&clks IMX5_CLK_SSI3_ROOT_GATE>;
+ clock-names = "ipg", "baud";
+ dmas = <&sdma 46 0 0>,
+ <&sdma 47 0 0>;
+ dma-names = "rx", "tx";
+ fsl,fifo-depth = <15>;
+ status = "disabled";
+ };
+
+ fec: ethernet@83fec000 {
+ compatible = "fsl,imx51-fec", "fsl,imx27-fec";
+ reg = <0x83fec000 0x4000>;
+ interrupts = <87>;
+ clocks = <&clks IMX5_CLK_FEC_GATE>,
+ <&clks IMX5_CLK_FEC_GATE>,
+ <&clks IMX5_CLK_FEC_GATE>;
+ clock-names = "ipg", "ahb", "ptp";
+ status = "disabled";
+ };
+
+ vpu: vpu@83ff4000 {
+ compatible = "fsl,imx51-vpu", "cnm,codahx4";
+ reg = <0x83ff4000 0x1000>;
+ interrupts = <9>;
+ clocks = <&clks IMX5_CLK_VPU_REFERENCE_GATE>,
+ <&clks IMX5_CLK_VPU_GATE>;
+ clock-names = "per", "ahb";
+ resets = <&src 1>;
+ iram = <&iram>;
+ };
+
+ sahara: crypto@83ff8000 {
+ compatible = "fsl,imx53-sahara", "fsl,imx51-sahara";
+ reg = <0x83ff8000 0x4000>;
+ interrupts = <19 20>;
+ clocks = <&clks IMX5_CLK_SAHARA_IPG_GATE>,
+ <&clks IMX5_CLK_SAHARA_IPG_GATE>;
+ clock-names = "ipg", "ahb";
+ };
+ };
+ };
+};
diff --git a/arch/arm/dts/imx53-qsb-common.dtsi b/arch/arm/dts/imx53-qsb-common.dtsi
new file mode 100644
index 0000000..fe42440
--- /dev/null
+++ b/arch/arm/dts/imx53-qsb-common.dtsi
@@ -0,0 +1,387 @@
+// SPDX-License-Identifier: GPL-2.0+
+//
+// Copyright 2011 Freescale Semiconductor, Inc.
+// Copyright 2011 Linaro Ltd.
+
+#include "imx53.dtsi"
+
+/ {
+ chosen {
+ stdout-path = &uart1;
+ };
+
+ memory@70000000 {
+ device_type = "memory";
+ reg = <0x70000000 0x20000000>,
+ <0xb0000000 0x20000000>;
+ };
+
+ display0: disp0 {
+ compatible = "fsl,imx-parallel-display";
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_ipu_disp0>;
+
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+
+ port@0 {
+ reg = <0>;
+
+ display0_in: endpoint {
+ remote-endpoint = <&ipu_di0_disp0>;
+ };
+ };
+
+ port@1 {
+ reg = <1>;
+
+ display_out: endpoint {
+ remote-endpoint = <&panel_in>;
+ };
+ };
+ };
+
+ gpio-keys {
+ compatible = "gpio-keys";
+
+ power {
+ label = "Power Button";
+ gpios = <&gpio1 8 GPIO_ACTIVE_LOW>;
+ linux,code = <KEY_POWER>;
+ };
+
+ volume-up {
+ label = "Volume Up";
+ gpios = <&gpio2 14 GPIO_ACTIVE_LOW>;
+ linux,code = <KEY_VOLUMEUP>;
+ wakeup-source;
+ };
+
+ volume-down {
+ label = "Volume Down";
+ gpios = <&gpio2 15 GPIO_ACTIVE_LOW>;
+ linux,code = <KEY_VOLUMEDOWN>;
+ wakeup-source;
+ };
+ };
+
+ leds {
+ compatible = "gpio-leds";
+ pinctrl-names = "default";
+ pinctrl-0 = <&led_pin_gpio7_7>;
+
+ user {
+ label = "Heartbeat";
+ gpios = <&gpio7 7 0>;
+ linux,default-trigger = "heartbeat";
+ };
+ };
+
+ panel {
+ compatible = "sii,43wvf1g";
+
+ port {
+ panel_in: endpoint {
+ remote-endpoint = <&display_out>;
+ };
+ };
+ };
+
+ regulators {
+ compatible = "simple-bus";
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ reg_3p2v: regulator@0 {
+ compatible = "regulator-fixed";
+ reg = <0>;
+ regulator-name = "3P2V";
+ regulator-min-microvolt = <3200000>;
+ regulator-max-microvolt = <3200000>;
+ regulator-always-on;
+ };
+
+ reg_usb_vbus: regulator@1 {
+ compatible = "regulator-fixed";
+ reg = <1>;
+ regulator-name = "usb_vbus";
+ regulator-min-microvolt = <5000000>;
+ regulator-max-microvolt = <5000000>;
+ gpio = <&gpio7 8 0>;
+ enable-active-high;
+ };
+ };
+
+ sound {
+ compatible = "fsl,imx53-qsb-sgtl5000",
+ "fsl,imx-audio-sgtl5000";
+ model = "imx53-qsb-sgtl5000";
+ ssi-controller = <&ssi2>;
+ audio-codec = <&sgtl5000>;
+ audio-routing =
+ "MIC_IN", "Mic Jack",
+ "Mic Jack", "Mic Bias",
+ "Headphone Jack", "HP_OUT";
+ mux-int-port = <2>;
+ mux-ext-port = <5>;
+ };
+};
+
+&cpu0 {
+ /* CPU rated to 1GHz, not 1.2GHz as per the default settings */
+ operating-points = <
+ /* kHz uV */
+ 166666 850000
+ 400000 900000
+ 800000 1050000
+ 1000000 1200000
+ >;
+};
+
+&esdhc1 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_esdhc1>;
+ cd-gpios = <&gpio3 13 GPIO_ACTIVE_LOW>;
+ status = "okay";
+};
+
+&ipu_di0_disp0 {
+ remote-endpoint = <&display0_in>;
+};
+
+&ssi2 {
+ status = "okay";
+};
+
+&esdhc3 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_esdhc3>;
+ cd-gpios = <&gpio3 11 GPIO_ACTIVE_LOW>;
+ wp-gpios = <&gpio3 12 GPIO_ACTIVE_HIGH>;
+ bus-width = <8>;
+ status = "okay";
+};
+
+&iomuxc {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_hog>;
+
+ imx53-qsb {
+ pinctrl_hog: hoggrp {
+ fsl,pins = <
+ MX53_PAD_GPIO_8__GPIO1_8 0x80000000
+ MX53_PAD_PATA_DATA14__GPIO2_14 0x80000000
+ MX53_PAD_PATA_DATA15__GPIO2_15 0x80000000
+ MX53_PAD_EIM_DA11__GPIO3_11 0x80000000
+ MX53_PAD_EIM_DA12__GPIO3_12 0x80000000
+ MX53_PAD_PATA_DA_0__GPIO7_6 0x80000000
+ MX53_PAD_PATA_DA_2__GPIO7_8 0x80000000
+ MX53_PAD_GPIO_16__GPIO7_11 0x80000000
+ >;
+ };
+
+ led_pin_gpio7_7: led_gpio7_7 {
+ fsl,pins = <
+ MX53_PAD_PATA_DA_1__GPIO7_7 0x80000000
+ >;
+ };
+
+ pinctrl_audmux: audmuxgrp {
+ fsl,pins = <
+ MX53_PAD_KEY_COL0__AUDMUX_AUD5_TXC 0x80000000
+ MX53_PAD_KEY_ROW0__AUDMUX_AUD5_TXD 0x80000000
+ MX53_PAD_KEY_COL1__AUDMUX_AUD5_TXFS 0x80000000
+ MX53_PAD_KEY_ROW1__AUDMUX_AUD5_RXD 0x80000000
+ >;
+ };
+
+ pinctrl_codec: codecgrp {
+ fsl,pins = <
+ MX53_PAD_GPIO_0__CCM_SSI_EXT1_CLK 0x1c4
+ >;
+ };
+
+ pinctrl_esdhc1: esdhc1grp {
+ fsl,pins = <
+ MX53_PAD_SD1_DATA0__ESDHC1_DAT0 0x1d5
+ MX53_PAD_SD1_DATA1__ESDHC1_DAT1 0x1d5
+ MX53_PAD_SD1_DATA2__ESDHC1_DAT2 0x1d5
+ MX53_PAD_SD1_DATA3__ESDHC1_DAT3 0x1d5
+ MX53_PAD_SD1_CMD__ESDHC1_CMD 0x1d5
+ MX53_PAD_SD1_CLK__ESDHC1_CLK 0x1d5
+ MX53_PAD_EIM_DA13__GPIO3_13 0xe4
+ >;
+ };
+
+ pinctrl_esdhc3: esdhc3grp {
+ fsl,pins = <
+ MX53_PAD_PATA_DATA8__ESDHC3_DAT0 0x1d5
+ MX53_PAD_PATA_DATA9__ESDHC3_DAT1 0x1d5
+ MX53_PAD_PATA_DATA10__ESDHC3_DAT2 0x1d5
+ MX53_PAD_PATA_DATA11__ESDHC3_DAT3 0x1d5
+ MX53_PAD_PATA_DATA0__ESDHC3_DAT4 0x1d5
+ MX53_PAD_PATA_DATA1__ESDHC3_DAT5 0x1d5
+ MX53_PAD_PATA_DATA2__ESDHC3_DAT6 0x1d5
+ MX53_PAD_PATA_DATA3__ESDHC3_DAT7 0x1d5
+ MX53_PAD_PATA_RESET_B__ESDHC3_CMD 0x1d5
+ MX53_PAD_PATA_IORDY__ESDHC3_CLK 0x1d5
+ >;
+ };
+
+ pinctrl_fec: fecgrp {
+ fsl,pins = <
+ MX53_PAD_FEC_MDC__FEC_MDC 0x4
+ MX53_PAD_FEC_MDIO__FEC_MDIO 0x1fc
+ MX53_PAD_FEC_REF_CLK__FEC_TX_CLK 0x180
+ MX53_PAD_FEC_RX_ER__FEC_RX_ER 0x180
+ MX53_PAD_FEC_CRS_DV__FEC_RX_DV 0x180
+ MX53_PAD_FEC_RXD1__FEC_RDATA_1 0x180
+ MX53_PAD_FEC_RXD0__FEC_RDATA_0 0x180
+ MX53_PAD_FEC_TX_EN__FEC_TX_EN 0x4
+ MX53_PAD_FEC_TXD1__FEC_TDATA_1 0x4
+ MX53_PAD_FEC_TXD0__FEC_TDATA_0 0x4
+ >;
+ };
+
+ /* open drain */
+ pinctrl_i2c1: i2c1grp {
+ fsl,pins = <
+ MX53_PAD_CSI0_DAT8__I2C1_SDA 0x400001ec
+ MX53_PAD_CSI0_DAT9__I2C1_SCL 0x400001ec
+ >;
+ };
+
+ pinctrl_i2c2: i2c2grp {
+ fsl,pins = <
+ MX53_PAD_KEY_ROW3__I2C2_SDA 0xc0000000
+ MX53_PAD_KEY_COL3__I2C2_SCL 0xc0000000
+ >;
+ };
+
+ pinctrl_ipu_disp0: ipudisp0grp {
+ fsl,pins = <
+ MX53_PAD_DI0_DISP_CLK__IPU_DI0_DISP_CLK 0x5
+ MX53_PAD_DI0_PIN15__IPU_DI0_PIN15 0x5
+ MX53_PAD_DI0_PIN2__IPU_DI0_PIN2 0x5
+ MX53_PAD_DI0_PIN3__IPU_DI0_PIN3 0x5
+ MX53_PAD_DISP0_DAT0__IPU_DISP0_DAT_0 0x5
+ MX53_PAD_DISP0_DAT1__IPU_DISP0_DAT_1 0x5
+ MX53_PAD_DISP0_DAT2__IPU_DISP0_DAT_2 0x5
+ MX53_PAD_DISP0_DAT3__IPU_DISP0_DAT_3 0x5
+ MX53_PAD_DISP0_DAT4__IPU_DISP0_DAT_4 0x5
+ MX53_PAD_DISP0_DAT5__IPU_DISP0_DAT_5 0x5
+ MX53_PAD_DISP0_DAT6__IPU_DISP0_DAT_6 0x5
+ MX53_PAD_DISP0_DAT7__IPU_DISP0_DAT_7 0x5
+ MX53_PAD_DISP0_DAT8__IPU_DISP0_DAT_8 0x5
+ MX53_PAD_DISP0_DAT9__IPU_DISP0_DAT_9 0x5
+ MX53_PAD_DISP0_DAT10__IPU_DISP0_DAT_10 0x5
+ MX53_PAD_DISP0_DAT11__IPU_DISP0_DAT_11 0x5
+ MX53_PAD_DISP0_DAT12__IPU_DISP0_DAT_12 0x5
+ MX53_PAD_DISP0_DAT13__IPU_DISP0_DAT_13 0x5
+ MX53_PAD_DISP0_DAT14__IPU_DISP0_DAT_14 0x5
+ MX53_PAD_DISP0_DAT15__IPU_DISP0_DAT_15 0x5
+ MX53_PAD_DISP0_DAT16__IPU_DISP0_DAT_16 0x5
+ MX53_PAD_DISP0_DAT17__IPU_DISP0_DAT_17 0x5
+ MX53_PAD_DISP0_DAT18__IPU_DISP0_DAT_18 0x5
+ MX53_PAD_DISP0_DAT19__IPU_DISP0_DAT_19 0x5
+ MX53_PAD_DISP0_DAT20__IPU_DISP0_DAT_20 0x5
+ MX53_PAD_DISP0_DAT21__IPU_DISP0_DAT_21 0x5
+ MX53_PAD_DISP0_DAT22__IPU_DISP0_DAT_22 0x5
+ MX53_PAD_DISP0_DAT23__IPU_DISP0_DAT_23 0x5
+ >;
+ };
+
+ pinctrl_vga_sync: vgasync-grp {
+ fsl,pins = <
+ /* VGA_HSYNC, VSYNC with max drive strength */
+ MX53_PAD_EIM_OE__IPU_DI1_PIN7 0xe6
+ MX53_PAD_EIM_RW__IPU_DI1_PIN8 0xe6
+ >;
+ };
+
+ pinctrl_uart1: uart1grp {
+ fsl,pins = <
+ MX53_PAD_CSI0_DAT10__UART1_TXD_MUX 0x1e4
+ MX53_PAD_CSI0_DAT11__UART1_RXD_MUX 0x1e4
+ >;
+ };
+ };
+};
+
+&tve {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_vga_sync>;
+ ddc-i2c-bus = <&i2c2>;
+ fsl,tve-mode = "vga";
+ fsl,hsync-pin = <7>; /* IPU DI1 PIN7 via EIM_OE */
+ fsl,vsync-pin = <8>; /* IPU DI1 PIN8 via EIM_RW */
+ status = "okay";
+};
+
+&uart1 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_uart1>;
+ status = "okay";
+};
+
+&i2c2 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_i2c2>;
+ status = "okay";
+
+ sgtl5000: codec@a {
+ compatible = "fsl,sgtl5000";
+ reg = <0x0a>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_codec>;
+ #sound-dai-cells = <0>;
+ VDDA-supply = <®_3p2v>;
+ VDDIO-supply = <®_3p2v>;
+ clocks = <&clks IMX5_CLK_SSI_EXT1_GATE>;
+ };
+};
+
+&i2c1 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_i2c1>;
+ status = "okay";
+
+ accelerometer: mma8450@1c {
+ compatible = "fsl,mma8450";
+ reg = <0x1c>;
+ };
+};
+
+&audmux {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_audmux>;
+ status = "okay";
+};
+
+&fec {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_fec>;
+ phy-mode = "rmii";
+ phy-reset-gpios = <&gpio7 6 GPIO_ACTIVE_LOW>;
+ status = "okay";
+};
+
+&sata {
+ status = "okay";
+};
+
+&vpu {
+ status = "okay";
+};
+
+&usbh1 {
+ vbus-supply = <®_usb_vbus>;
+ phy_type = "utmi";
+ status = "okay";
+};
+
+&usbotg {
+ dr_mode = "peripheral";
+ status = "okay";
+};
diff --git a/arch/arm/dts/imx53-qsb.dts b/arch/arm/dts/imx53-qsb.dts
new file mode 100644
index 0000000..6831836
--- /dev/null
+++ b/arch/arm/dts/imx53-qsb.dts
@@ -0,0 +1,111 @@
+// SPDX-License-Identifier: GPL-2.0+
+//
+// Copyright 2011 Freescale Semiconductor, Inc.
+// Copyright 2011 Linaro Ltd.
+
+/dts-v1/;
+#include "imx53-qsb-common.dtsi"
+
+/ {
+ model = "Freescale i.MX53 Quick Start Board";
+ compatible = "fsl,imx53-qsb", "fsl,imx53";
+};
+
+&i2c1 {
+ pmic: dialog@48 {
+ compatible = "dlg,da9053-aa", "dlg,da9052";
+ reg = <0x48>;
+ interrupt-parent = <&gpio7>;
+ interrupts = <11 IRQ_TYPE_LEVEL_LOW>; /* low-level active IRQ at GPIO7_11 */
+
+ regulators {
+ buck1_reg: buck1 {
+ regulator-min-microvolt = <500000>;
+ regulator-max-microvolt = <2075000>;
+ regulator-always-on;
+ };
+
+ buck2_reg: buck2 {
+ regulator-min-microvolt = <500000>;
+ regulator-max-microvolt = <2075000>;
+ regulator-always-on;
+ };
+
+ buck3_reg: buck3 {
+ regulator-min-microvolt = <925000>;
+ regulator-max-microvolt = <2500000>;
+ regulator-always-on;
+ };
+
+ buck4_reg: buck4 {
+ regulator-min-microvolt = <925000>;
+ regulator-max-microvolt = <2500000>;
+ regulator-always-on;
+ };
+
+ ldo1_reg: ldo1 {
+ regulator-min-microvolt = <600000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-boot-on;
+ regulator-always-on;
+ };
+
+ ldo2_reg: ldo2 {
+ regulator-min-microvolt = <600000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-always-on;
+ };
+
+ ldo3_reg: ldo3 {
+ regulator-min-microvolt = <1725000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-always-on;
+ };
+
+ ldo4_reg: ldo4 {
+ regulator-min-microvolt = <1725000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-always-on;
+ };
+
+ ldo5_reg: ldo5 {
+ regulator-min-microvolt = <1200000>;
+ regulator-max-microvolt = <3600000>;
+ regulator-always-on;
+ };
+
+ ldo6_reg: ldo6 {
+ regulator-min-microvolt = <1200000>;
+ regulator-max-microvolt = <3600000>;
+ regulator-always-on;
+ };
+
+ ldo7_reg: ldo7 {
+ regulator-min-microvolt = <2750000>;
+ regulator-max-microvolt = <2750000>;
+ };
+
+ ldo8_reg: ldo8 {
+ regulator-min-microvolt = <1200000>;
+ regulator-max-microvolt = <3600000>;
+ regulator-always-on;
+ };
+
+ ldo9_reg: ldo9 {
+ regulator-min-microvolt = <1250000>;
+ regulator-max-microvolt = <3600000>;
+ regulator-always-on;
+ };
+
+ ldo10_reg: ldo10 {
+ regulator-min-microvolt = <1200000>;
+ regulator-max-microvolt = <3600000>;
+ regulator-always-on;
+ };
+ };
+ };
+};
+
+&tve {
+ dac-supply = <&ldo7_reg>;
+};
diff --git a/arch/arm/dts/imx8mm-venice-gw700x-u-boot.dtsi b/arch/arm/dts/imx8mm-venice-gw700x-u-boot.dtsi
new file mode 100644
index 0000000..a4487e2
--- /dev/null
+++ b/arch/arm/dts/imx8mm-venice-gw700x-u-boot.dtsi
@@ -0,0 +1,105 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright 2021 Gateworks Corporation
+ */
+
+&{/soc@0} {
+ u-boot,dm-pre-reloc;
+ u-boot,dm-spl;
+};
+
+&clk {
+ u-boot,dm-spl;
+ u-boot,dm-pre-reloc;
+ /delete-property/ assigned-clocks;
+ /delete-property/ assigned-clock-parents;
+ /delete-property/ assigned-clock-rates;
+};
+
+&osc_24m {
+ u-boot,dm-spl;
+ u-boot,dm-pre-reloc;
+};
+
+&aips1 {
+ u-boot,dm-spl;
+ u-boot,dm-pre-reloc;
+};
+
+&aips2 {
+ u-boot,dm-spl;
+};
+
+&aips3 {
+ u-boot,dm-spl;
+};
+
+&iomuxc {
+ u-boot,dm-spl;
+};
+
+&gpio1 {
+ u-boot,dm-spl;
+};
+
+&gpio2 {
+ u-boot,dm-spl;
+};
+
+&gpio3 {
+ u-boot,dm-spl;
+};
+
+&gpio4 {
+ u-boot,dm-spl;
+};
+
+&gpio5 {
+ u-boot,dm-spl;
+};
+
+&uart2 {
+ u-boot,dm-spl;
+};
+
+&pinctrl_uart2 {
+ u-boot,dm-spl;
+};
+
+&usdhc3 {
+ u-boot,dm-spl;
+};
+
+&pinctrl_usdhc3 {
+ u-boot,dm-spl;
+};
+
+&i2c1 {
+ u-boot,dm-spl;
+};
+
+&pinctrl_i2c1 {
+ u-boot,dm-spl;
+};
+
+&i2c2 {
+ u-boot,dm-spl;
+};
+
+&pinctrl_i2c2 {
+ u-boot,dm-spl;
+};
+
+&fec1 {
+ phy-reset-gpios = <&gpio3 0 GPIO_ACTIVE_LOW>;
+ phy-reset-duration = <1>;
+ phy-reset-post-delay = <1>;
+};
+
+&{/soc@0/bus@30800000/i2c@30a20000/pmic@69} {
+ u-boot,dm-spl;
+};
+
+&{/soc@0/bus@30800000/i2c@30a20000/pmic@69/regulators} {
+ u-boot,dm-spl;
+};
diff --git a/arch/arm/dts/imx8mm-venice-gw700x.dtsi b/arch/arm/dts/imx8mm-venice-gw700x.dtsi
new file mode 100644
index 0000000..c769fad
--- /dev/null
+++ b/arch/arm/dts/imx8mm-venice-gw700x.dtsi
@@ -0,0 +1,495 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright 2020 Gateworks Corporation
+ */
+
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/input/linux-event-codes.h>
+#include <dt-bindings/net/ti-dp83867.h>
+
+/ {
+ memory@40000000 {
+ device_type = "memory";
+ reg = <0x0 0x40000000 0 0x80000000>;
+ };
+
+ gpio-keys {
+ compatible = "gpio-keys";
+
+ user-pb {
+ label = "user_pb";
+ gpios = <&gpio 2 GPIO_ACTIVE_LOW>;
+ linux,code = <BTN_0>;
+ };
+
+ user-pb1x {
+ label = "user_pb1x";
+ linux,code = <BTN_1>;
+ interrupt-parent = <&gsc>;
+ interrupts = <0>;
+ };
+
+ key-erased {
+ label = "key_erased";
+ linux,code = <BTN_2>;
+ interrupt-parent = <&gsc>;
+ interrupts = <1>;
+ };
+
+ eeprom-wp {
+ label = "eeprom_wp";
+ linux,code = <BTN_3>;
+ interrupt-parent = <&gsc>;
+ interrupts = <2>;
+ };
+
+ tamper {
+ label = "tamper";
+ linux,code = <BTN_4>;
+ interrupt-parent = <&gsc>;
+ interrupts = <5>;
+ };
+
+ switch-hold {
+ label = "switch_hold";
+ linux,code = <BTN_5>;
+ interrupt-parent = <&gsc>;
+ interrupts = <7>;
+ };
+ };
+};
+
+&A53_0 {
+ cpu-supply = <&buck3_reg>;
+};
+
+&A53_1 {
+ cpu-supply = <&buck3_reg>;
+};
+
+&A53_2 {
+ cpu-supply = <&buck3_reg>;
+};
+
+&A53_3 {
+ cpu-supply = <&buck3_reg>;
+};
+
+&ddrc {
+ operating-points-v2 = <&ddrc_opp_table>;
+
+ ddrc_opp_table: opp-table {
+ compatible = "operating-points-v2";
+
+ opp-25M {
+ opp-hz = /bits/ 64 <25000000>;
+ };
+
+ opp-100M {
+ opp-hz = /bits/ 64 <100000000>;
+ };
+
+ opp-750M {
+ opp-hz = /bits/ 64 <750000000>;
+ };
+ };
+};
+
+&fec1 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_fec1>;
+ phy-mode = "rgmii-id";
+ phy-handle = <ðphy0>;
+ status = "okay";
+
+ mdio {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ ethphy0: ethernet-phy@0 {
+ compatible = "ethernet-phy-ieee802.3-c22";
+ reg = <0>;
+ ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_00_NS>;
+ ti,tx-internal-delay = <DP83867_RGMIIDCTL_2_00_NS>;
+ tx-fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>;
+ rx-fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>;
+ };
+ };
+};
+
+&i2c1 {
+ clock-frequency = <100000>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_i2c1>;
+ status = "okay";
+
+ gsc: gsc@20 {
+ compatible = "gw,gsc";
+ reg = <0x20>;
+ pinctrl-0 = <&pinctrl_gsc>;
+ interrupt-parent = <&gpio2>;
+ interrupts = <6 IRQ_TYPE_EDGE_FALLING>;
+ interrupt-controller;
+ #interrupt-cells = <1>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ adc {
+ compatible = "gw,gsc-adc";
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ channel@6 {
+ gw,mode = <0>;
+ reg = <0x06>;
+ label = "temp";
+ };
+
+ channel@8 {
+ gw,mode = <1>;
+ reg = <0x08>;
+ label = "vdd_bat";
+ };
+
+ channel@16 {
+ gw,mode = <4>;
+ reg = <0x16>;
+ label = "fan_tach";
+ };
+
+ channel@82 {
+ gw,mode = <2>;
+ reg = <0x82>;
+ label = "vdd_vin";
+ gw,voltage-divider-ohms = <22100 1000>;
+ };
+
+ channel@84 {
+ gw,mode = <2>;
+ reg = <0x84>;
+ label = "vdd_adc1";
+ gw,voltage-divider-ohms = <10000 10000>;
+ };
+
+ channel@86 {
+ gw,mode = <2>;
+ reg = <0x86>;
+ label = "vdd_adc2";
+ gw,voltage-divider-ohms = <10000 10000>;
+ };
+
+ channel@88 {
+ gw,mode = <2>;
+ reg = <0x88>;
+ label = "vdd_dram";
+ };
+
+ channel@8c {
+ gw,mode = <2>;
+ reg = <0x8c>;
+ label = "vdd_1p2";
+ };
+
+ channel@8e {
+ gw,mode = <2>;
+ reg = <0x8e>;
+ label = "vdd_1p0";
+ };
+
+ channel@90 {
+ gw,mode = <2>;
+ reg = <0x90>;
+ label = "vdd_2p5";
+ gw,voltage-divider-ohms = <10000 10000>;
+ };
+
+ channel@92 {
+ gw,mode = <2>;
+ reg = <0x92>;
+ label = "vdd_3p3";
+ gw,voltage-divider-ohms = <10000 10000>;
+ };
+
+ channel@98 {
+ gw,mode = <2>;
+ reg = <0x98>;
+ label = "vdd_0p95";
+ };
+
+ channel@9a {
+ gw,mode = <2>;
+ reg = <0x9a>;
+ label = "vdd_1p8";
+ };
+
+ channel@a2 {
+ gw,mode = <2>;
+ reg = <0xa2>;
+ label = "vdd_gsc";
+ gw,voltage-divider-ohms = <10000 10000>;
+ };
+ };
+
+ fan-controller@0 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ compatible = "gw,gsc-fan";
+ reg = <0x0a>;
+ };
+ };
+
+ gpio: gpio@23 {
+ compatible = "nxp,pca9555";
+ reg = <0x23>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ interrupt-parent = <&gsc>;
+ interrupts = <4>;
+ };
+
+ eeprom@50 {
+ compatible = "atmel,24c02";
+ reg = <0x50>;
+ pagesize = <16>;
+ };
+
+ eeprom@51 {
+ compatible = "atmel,24c02";
+ reg = <0x51>;
+ pagesize = <16>;
+ };
+
+ eeprom@52 {
+ compatible = "atmel,24c02";
+ reg = <0x52>;
+ pagesize = <16>;
+ };
+
+ eeprom@53 {
+ compatible = "atmel,24c02";
+ reg = <0x53>;
+ pagesize = <16>;
+ };
+
+ rtc@68 {
+ compatible = "dallas,ds1672";
+ reg = <0x68>;
+ };
+
+ pmic@69 {
+ compatible = "mps,mp5416";
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_pmic>;
+ reg = <0x69>;
+
+ regulators {
+ buck1 {
+ regulator-name = "vdd_0p95";
+ regulator-min-microvolt = <805000>;
+ regulator-max-microvolt = <1000000>;
+ regulator-max-microamp = <2500000>;
+ regulator-boot-on;
+ };
+
+ buck2 {
+ regulator-name = "vdd_soc";
+ regulator-min-microvolt = <805000>;
+ regulator-max-microvolt = <900000>;
+ regulator-max-microamp = <1000000>;
+ regulator-boot-on;
+ };
+
+ buck3_reg: buck3 {
+ regulator-name = "vdd_arm";
+ regulator-min-microvolt = <805000>;
+ regulator-max-microvolt = <1000000>;
+ regulator-max-microamp = <2200000>;
+ regulator-boot-on;
+ };
+
+ buck4 {
+ regulator-name = "vdd_1p8";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-max-microamp = <500000>;
+ regulator-boot-on;
+ };
+
+ ldo1 {
+ regulator-name = "nvcc_snvs_1p8";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-max-microamp = <300000>;
+ regulator-boot-on;
+ };
+
+ ldo2 {
+ regulator-name = "vdd_snvs_0p8";
+ regulator-min-microvolt = <800000>;
+ regulator-max-microvolt = <800000>;
+ regulator-boot-on;
+ };
+
+ ldo3 {
+ regulator-name = "vdd_0p95";
+ regulator-min-microvolt = <800000>;
+ regulator-max-microvolt = <800000>;
+ regulator-boot-on;
+ };
+
+ ldo4 {
+ regulator-name = "vdd_1p8";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-boot-on;
+ };
+ };
+ };
+};
+
+&i2c2 {
+ clock-frequency = <400000>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_i2c2>;
+ status = "okay";
+
+ eeprom@52 {
+ compatible = "atmel,24c32";
+ reg = <0x52>;
+ pagesize = <32>;
+ };
+};
+
+/* console */
+&uart2 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_uart2>;
+ status = "okay";
+};
+
+/* eMMC */
+&usdhc3 {
+ pinctrl-names = "default", "state_100mhz", "state_200mhz";
+ pinctrl-0 = <&pinctrl_usdhc3>;
+ pinctrl-1 = <&pinctrl_usdhc3_100mhz>;
+ pinctrl-2 = <&pinctrl_usdhc3_200mhz>;
+ bus-width = <8>;
+ non-removable;
+ status = "okay";
+};
+
+&wdog1 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_wdog>;
+ fsl,ext-reset-output;
+ status = "okay";
+};
+
+&iomuxc {
+ pinctrl_fec1: fec1grp {
+ fsl,pins = <
+ MX8MM_IOMUXC_ENET_MDC_ENET1_MDC 0x3
+ MX8MM_IOMUXC_ENET_MDIO_ENET1_MDIO 0x3
+ MX8MM_IOMUXC_ENET_TD3_ENET1_RGMII_TD3 0x1f
+ MX8MM_IOMUXC_ENET_TD2_ENET1_RGMII_TD2 0x1f
+ MX8MM_IOMUXC_ENET_TD1_ENET1_RGMII_TD1 0x1f
+ MX8MM_IOMUXC_ENET_TD0_ENET1_RGMII_TD0 0x1f
+ MX8MM_IOMUXC_ENET_RD3_ENET1_RGMII_RD3 0x91
+ MX8MM_IOMUXC_ENET_RD2_ENET1_RGMII_RD2 0x91
+ MX8MM_IOMUXC_ENET_RD1_ENET1_RGMII_RD1 0x91
+ MX8MM_IOMUXC_ENET_RD0_ENET1_RGMII_RD0 0x91
+ MX8MM_IOMUXC_ENET_TXC_ENET1_RGMII_TXC 0x1f
+ MX8MM_IOMUXC_ENET_RXC_ENET1_RGMII_RXC 0x91
+ MX8MM_IOMUXC_ENET_RX_CTL_ENET1_RGMII_RX_CTL 0x91
+ MX8MM_IOMUXC_ENET_TX_CTL_ENET1_RGMII_TX_CTL 0x1f
+ MX8MM_IOMUXC_NAND_ALE_GPIO3_IO0 0x19
+ >;
+ };
+
+ pinctrl_gsc: gscgrp {
+ fsl,pins = <
+ MX8MM_IOMUXC_SD1_DATA4_GPIO2_IO6 0x159
+ >;
+ };
+
+ pinctrl_i2c1: i2c1grp {
+ fsl,pins = <
+ MX8MM_IOMUXC_I2C1_SCL_I2C1_SCL 0x400001c3
+ MX8MM_IOMUXC_I2C1_SDA_I2C1_SDA 0x400001c3
+ >;
+ };
+
+ pinctrl_i2c2: i2c2grp {
+ fsl,pins = <
+ MX8MM_IOMUXC_I2C2_SCL_I2C2_SCL 0x400001c3
+ MX8MM_IOMUXC_I2C2_SDA_I2C2_SDA 0x400001c3
+ >;
+ };
+
+ pinctrl_pmic: pmicgrp {
+ fsl,pins = <
+ MX8MM_IOMUXC_GPIO1_IO03_GPIO1_IO3 0x41
+ >;
+ };
+
+ pinctrl_uart2: uart2grp {
+ fsl,pins = <
+ MX8MM_IOMUXC_UART2_RXD_UART2_DCE_RX 0x140
+ MX8MM_IOMUXC_UART2_TXD_UART2_DCE_TX 0x140
+ >;
+ };
+
+ pinctrl_usdhc3: usdhc3grp {
+ fsl,pins = <
+ MX8MM_IOMUXC_NAND_WE_B_USDHC3_CLK 0x190
+ MX8MM_IOMUXC_NAND_WP_B_USDHC3_CMD 0x1d0
+ MX8MM_IOMUXC_NAND_DATA04_USDHC3_DATA0 0x1d0
+ MX8MM_IOMUXC_NAND_DATA05_USDHC3_DATA1 0x1d0
+ MX8MM_IOMUXC_NAND_DATA06_USDHC3_DATA2 0x1d0
+ MX8MM_IOMUXC_NAND_DATA07_USDHC3_DATA3 0x1d0
+ MX8MM_IOMUXC_NAND_RE_B_USDHC3_DATA4 0x1d0
+ MX8MM_IOMUXC_NAND_CE2_B_USDHC3_DATA5 0x1d0
+ MX8MM_IOMUXC_NAND_CE3_B_USDHC3_DATA6 0x1d0
+ MX8MM_IOMUXC_NAND_CLE_USDHC3_DATA7 0x1d0
+ MX8MM_IOMUXC_NAND_CE1_B_USDHC3_STROBE 0x190
+ >;
+ };
+
+ pinctrl_usdhc3_100mhz: usdhc3-100mhzgrp {
+ fsl,pins = <
+ MX8MM_IOMUXC_NAND_WE_B_USDHC3_CLK 0x194
+ MX8MM_IOMUXC_NAND_WP_B_USDHC3_CMD 0x1d4
+ MX8MM_IOMUXC_NAND_DATA04_USDHC3_DATA0 0x1d4
+ MX8MM_IOMUXC_NAND_DATA05_USDHC3_DATA1 0x1d4
+ MX8MM_IOMUXC_NAND_DATA06_USDHC3_DATA2 0x1d4
+ MX8MM_IOMUXC_NAND_DATA07_USDHC3_DATA3 0x1d4
+ MX8MM_IOMUXC_NAND_RE_B_USDHC3_DATA4 0x1d4
+ MX8MM_IOMUXC_NAND_CE2_B_USDHC3_DATA5 0x1d4
+ MX8MM_IOMUXC_NAND_CE3_B_USDHC3_DATA6 0x1d4
+ MX8MM_IOMUXC_NAND_CLE_USDHC3_DATA7 0x1d4
+ MX8MM_IOMUXC_NAND_CE1_B_USDHC3_STROBE 0x194
+ >;
+ };
+
+ pinctrl_usdhc3_200mhz: usdhc3-200mhzgrp {
+ fsl,pins = <
+ MX8MM_IOMUXC_NAND_WE_B_USDHC3_CLK 0x196
+ MX8MM_IOMUXC_NAND_WP_B_USDHC3_CMD 0x1d6
+ MX8MM_IOMUXC_NAND_DATA04_USDHC3_DATA0 0x1d6
+ MX8MM_IOMUXC_NAND_DATA05_USDHC3_DATA1 0x1d6
+ MX8MM_IOMUXC_NAND_DATA06_USDHC3_DATA2 0x1d6
+ MX8MM_IOMUXC_NAND_DATA07_USDHC3_DATA3 0x1d6
+ MX8MM_IOMUXC_NAND_RE_B_USDHC3_DATA4 0x1d6
+ MX8MM_IOMUXC_NAND_CE2_B_USDHC3_DATA5 0x1d6
+ MX8MM_IOMUXC_NAND_CE3_B_USDHC3_DATA6 0x1d6
+ MX8MM_IOMUXC_NAND_CLE_USDHC3_DATA7 0x1d6
+ MX8MM_IOMUXC_NAND_CE1_B_USDHC3_STROBE 0x196
+ >;
+ };
+
+ pinctrl_wdog: wdoggrp {
+ fsl,pins = <
+ MX8MM_IOMUXC_GPIO1_IO02_WDOG1_WDOG_B 0xc6
+ >;
+ };
+};
diff --git a/arch/arm/dts/imx8mm-venice-gw71xx-0x-u-boot.dtsi b/arch/arm/dts/imx8mm-venice-gw71xx-0x-u-boot.dtsi
new file mode 100644
index 0000000..f5d52c2
--- /dev/null
+++ b/arch/arm/dts/imx8mm-venice-gw71xx-0x-u-boot.dtsi
@@ -0,0 +1,5 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright 2021 Gateworks Corporation
+ */
+#include "imx8mm-venice-gw700x-u-boot.dtsi"
diff --git a/arch/arm/dts/imx8mm-venice-gw71xx-0x.dts b/arch/arm/dts/imx8mm-venice-gw71xx-0x.dts
new file mode 100644
index 0000000..3f88c4a
--- /dev/null
+++ b/arch/arm/dts/imx8mm-venice-gw71xx-0x.dts
@@ -0,0 +1,19 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright 2020 Gateworks Corporation
+ */
+
+/dts-v1/;
+
+#include "imx8mm.dtsi"
+#include "imx8mm-venice-gw700x.dtsi"
+#include "imx8mm-venice-gw71xx.dtsi"
+
+/ {
+ model = "Gateworks Venice GW71xx-0x i.MX8MM Development Kit";
+ compatible = "gw,imx8mm-gw71xx-0x", "fsl,imx8mm";
+
+ chosen {
+ stdout-path = &uart2;
+ };
+};
diff --git a/arch/arm/dts/imx8mm-venice-gw71xx.dtsi b/arch/arm/dts/imx8mm-venice-gw71xx.dtsi
new file mode 100644
index 0000000..905b68a
--- /dev/null
+++ b/arch/arm/dts/imx8mm-venice-gw71xx.dtsi
@@ -0,0 +1,186 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright 2020 Gateworks Corporation
+ */
+
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/leds/common.h>
+
+/ {
+ aliases {
+ usb0 = &usbotg1;
+ usb1 = &usbotg2;
+ };
+
+ led-controller {
+ compatible = "gpio-leds";
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_gpio_leds>;
+
+ led-0 {
+ function = LED_FUNCTION_STATUS;
+ color = <LED_COLOR_ID_GREEN>;
+ gpios = <&gpio5 5 GPIO_ACTIVE_HIGH>;
+ default-state = "on";
+ linux,default-trigger = "heartbeat";
+ };
+
+ led-1 {
+ function = LED_FUNCTION_STATUS;
+ color = <LED_COLOR_ID_RED>;
+ gpios = <&gpio5 4 GPIO_ACTIVE_HIGH>;
+ default-state = "off";
+ };
+ };
+
+ pps {
+ compatible = "pps-gpio";
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_pps>;
+ gpios = <&gpio1 15 GPIO_ACTIVE_HIGH>;
+ status = "okay";
+ };
+
+ reg_usb_otg1_vbus: regulator-usb-otg1 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_reg_usb1_en>;
+ compatible = "regulator-fixed";
+ regulator-name = "usb_otg1_vbus";
+ gpio = <&gpio1 12 GPIO_ACTIVE_HIGH>;
+ enable-active-high;
+ regulator-min-microvolt = <5000000>;
+ regulator-max-microvolt = <5000000>;
+ };
+};
+
+/* off-board header */
+&ecspi2 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_spi2>;
+ cs-gpios = <&gpio5 13 GPIO_ACTIVE_HIGH>;
+ status = "okay";
+};
+
+&i2c2 {
+ clock-frequency = <400000>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_i2c2>;
+ status = "okay";
+
+ accelerometer@19 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_accel>;
+ compatible = "st,lis2de12";
+ reg = <0x19>;
+ st,drdy-int-pin = <1>;
+ interrupt-parent = <&gpio4>;
+ interrupts = <5 IRQ_TYPE_LEVEL_LOW>;
+ interrupt-names = "INT1";
+ };
+};
+
+/* off-board header */
+&i2c3 {
+ clock-frequency = <400000>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_i2c3>;
+ status = "okay";
+};
+
+/* GPS */
+&uart1 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_uart1>;
+ status = "okay";
+};
+
+/* off-board header */
+&uart3 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_uart3>;
+ status = "okay";
+};
+
+&usbotg1 {
+ dr_mode = "otg";
+ vbus-supply = <®_usb_otg1_vbus>;
+ status = "okay";
+};
+
+&usbotg2 {
+ dr_mode = "host";
+ status = "okay";
+};
+
+&iomuxc {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_hog>;
+
+ pinctrl_hog: hoggrp {
+ fsl,pins = <
+ MX8MM_IOMUXC_SPDIF_TX_GPIO5_IO3 0x40000041 /* PLUG_TEST */
+ MX8MM_IOMUXC_GPIO1_IO06_GPIO1_IO6 0x40000041 /* PCI_USBSEL */
+ MX8MM_IOMUXC_SAI1_RXD5_GPIO4_IO7 0x40000041 /* PCIE_WDIS# */
+ MX8MM_IOMUXC_GPIO1_IO07_GPIO1_IO7 0x40000041 /* DIO0 */
+ MX8MM_IOMUXC_GPIO1_IO09_GPIO1_IO9 0x40000041 /* DIO1 */
+ MX8MM_IOMUXC_SAI1_RXD1_GPIO4_IO3 0x40000041 /* DIO2 */
+ MX8MM_IOMUXC_SAI1_RXD2_GPIO4_IO4 0x40000041 /* DIO2 */
+ >;
+ };
+
+ pinctrl_accel: accelgrp {
+ fsl,pins = <
+ MX8MM_IOMUXC_SAI1_RXD3_GPIO4_IO5 0x159
+ >;
+ };
+
+ pinctrl_gpio_leds: gpioledgrp {
+ fsl,pins = <
+ MX8MM_IOMUXC_SPDIF_EXT_CLK_GPIO5_IO5 0x19
+ MX8MM_IOMUXC_SPDIF_RX_GPIO5_IO4 0x19
+ >;
+ };
+
+ pinctrl_i2c3: i2c3grp {
+ fsl,pins = <
+ MX8MM_IOMUXC_I2C3_SCL_I2C3_SCL 0x400001c3
+ MX8MM_IOMUXC_I2C3_SDA_I2C3_SDA 0x400001c3
+ >;
+ };
+
+ pinctrl_pps: ppsgrp {
+ fsl,pins = <
+ MX8MM_IOMUXC_GPIO1_IO15_GPIO1_IO15 0x41
+ >;
+ };
+
+ pinctrl_reg_usb1_en: regusb1grp {
+ fsl,pins = <
+ MX8MM_IOMUXC_GPIO1_IO12_GPIO1_IO12 0x41
+ MX8MM_IOMUXC_GPIO1_IO13_USB1_OTG_OC 0x41
+ >;
+ };
+
+ pinctrl_spi2: spi2grp {
+ fsl,pins = <
+ MX8MM_IOMUXC_ECSPI2_SCLK_ECSPI2_SCLK 0xd6
+ MX8MM_IOMUXC_ECSPI2_MOSI_ECSPI2_MOSI 0xd6
+ MX8MM_IOMUXC_ECSPI2_SCLK_ECSPI2_SCLK 0xd6
+ MX8MM_IOMUXC_ECSPI2_SS0_GPIO5_IO13 0xd6
+ >;
+ };
+
+ pinctrl_uart1: uart1grp {
+ fsl,pins = <
+ MX8MM_IOMUXC_UART1_RXD_UART1_DCE_RX 0x140
+ MX8MM_IOMUXC_UART1_TXD_UART1_DCE_TX 0x140
+ >;
+ };
+
+ pinctrl_uart3: uart3grp {
+ fsl,pins = <
+ MX8MM_IOMUXC_UART3_RXD_UART3_DCE_RX 0x140
+ MX8MM_IOMUXC_UART3_TXD_UART3_DCE_TX 0x140
+ >;
+ };
+};
diff --git a/arch/arm/dts/imx8mm-venice-gw72xx-0x-u-boot.dtsi b/arch/arm/dts/imx8mm-venice-gw72xx-0x-u-boot.dtsi
new file mode 100644
index 0000000..f5d52c2
--- /dev/null
+++ b/arch/arm/dts/imx8mm-venice-gw72xx-0x-u-boot.dtsi
@@ -0,0 +1,5 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright 2021 Gateworks Corporation
+ */
+#include "imx8mm-venice-gw700x-u-boot.dtsi"
diff --git a/arch/arm/dts/imx8mm-venice-gw72xx-0x.dts b/arch/arm/dts/imx8mm-venice-gw72xx-0x.dts
new file mode 100644
index 0000000..641be3a
--- /dev/null
+++ b/arch/arm/dts/imx8mm-venice-gw72xx-0x.dts
@@ -0,0 +1,19 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright 2020 Gateworks Corporation
+ */
+
+/dts-v1/;
+
+#include "imx8mm.dtsi"
+#include "imx8mm-venice-gw700x.dtsi"
+#include "imx8mm-venice-gw72xx.dtsi"
+
+/ {
+ model = "Gateworks Venice GW72xx-0x i.MX8MM Development Kit";
+ compatible = "gw,imx8mm-gw72xx-0x", "fsl,imx8mm";
+
+ chosen {
+ stdout-path = &uart2;
+ };
+};
diff --git a/arch/arm/dts/imx8mm-venice-gw72xx.dtsi b/arch/arm/dts/imx8mm-venice-gw72xx.dtsi
new file mode 100644
index 0000000..b7c91bd
--- /dev/null
+++ b/arch/arm/dts/imx8mm-venice-gw72xx.dtsi
@@ -0,0 +1,311 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright 2020 Gateworks Corporation
+ */
+
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/leds/common.h>
+
+/ {
+ aliases {
+ usb0 = &usbotg1;
+ usb1 = &usbotg2;
+ };
+
+ led-controller {
+ compatible = "gpio-leds";
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_gpio_leds>;
+
+ led-0 {
+ function = LED_FUNCTION_STATUS;
+ color = <LED_COLOR_ID_GREEN>;
+ gpios = <&gpio5 5 GPIO_ACTIVE_HIGH>;
+ default-state = "on";
+ linux,default-trigger = "heartbeat";
+ };
+
+ led-1 {
+ function = LED_FUNCTION_STATUS;
+ color = <LED_COLOR_ID_RED>;
+ gpios = <&gpio5 4 GPIO_ACTIVE_HIGH>;
+ default-state = "off";
+ };
+ };
+
+ pps {
+ compatible = "pps-gpio";
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_pps>;
+ gpios = <&gpio1 15 GPIO_ACTIVE_HIGH>;
+ status = "okay";
+ };
+
+ reg_3p3v: regulator-3p3v {
+ compatible = "regulator-fixed";
+ regulator-name = "3P3V";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-always-on;
+ };
+
+ reg_usb_otg1_vbus: regulator-usb-otg1 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_reg_usb1_en>;
+ compatible = "regulator-fixed";
+ regulator-name = "usb_otg1_vbus";
+ gpio = <&gpio1 12 GPIO_ACTIVE_HIGH>;
+ enable-active-high;
+ regulator-min-microvolt = <5000000>;
+ regulator-max-microvolt = <5000000>;
+ };
+
+ reg_usb_otg2_vbus: regulator-usb-otg2 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_reg_usb2_en>;
+ compatible = "regulator-fixed";
+ regulator-name = "usb_otg2_vbus";
+ gpio = <&gpio1 8 GPIO_ACTIVE_HIGH>;
+ enable-active-high;
+ regulator-min-microvolt = <5000000>;
+ regulator-max-microvolt = <5000000>;
+ };
+};
+
+/* off-board header */
+&ecspi2 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_spi2>;
+ cs-gpios = <&gpio5 13 GPIO_ACTIVE_HIGH>;
+ status = "okay";
+};
+
+&i2c2 {
+ clock-frequency = <400000>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_i2c2>;
+ status = "okay";
+
+ accelerometer@19 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_accel>;
+ compatible = "st,lis2de12";
+ reg = <0x19>;
+ st,drdy-int-pin = <1>;
+ interrupt-parent = <&gpio4>;
+ interrupts = <5 IRQ_TYPE_LEVEL_LOW>;
+ interrupt-names = "INT1";
+ };
+};
+
+/* off-board header */
+&i2c3 {
+ clock-frequency = <400000>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_i2c3>;
+ status = "okay";
+};
+
+/* off-board header */
+&sai3 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_sai3>;
+ assigned-clocks = <&clk IMX8MM_CLK_SAI3>;
+ assigned-clock-parents = <&clk IMX8MM_AUDIO_PLL1_OUT>;
+ assigned-clock-rates = <24576000>;
+ status = "okay";
+};
+
+/* GPS */
+&uart1 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_uart1>;
+ status = "okay";
+};
+
+/* off-board header */
+&uart3 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_uart3>;
+ status = "okay";
+};
+
+/* RS232 */
+&uart4 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_uart4>;
+ status = "okay";
+};
+
+&usbotg1 {
+ dr_mode = "otg";
+ vbus-supply = <®_usb_otg1_vbus>;
+ status = "okay";
+};
+
+&usbotg2 {
+ dr_mode = "host";
+ vbus-supply = <®_usb_otg2_vbus>;
+ status = "okay";
+};
+
+/* microSD */
+&usdhc2 {
+ pinctrl-names = "default", "state_100mhz", "state_200mhz";
+ pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>;
+ pinctrl-1 = <&pinctrl_usdhc2_100mhz>, <&pinctrl_usdhc2_gpio>;
+ pinctrl-2 = <&pinctrl_usdhc2_200mhz>, <&pinctrl_usdhc2_gpio>;
+ cd-gpios = <&gpio2 12 GPIO_ACTIVE_LOW>;
+ bus-width = <4>;
+ vmmc-supply = <®_3p3v>;
+ status = "okay";
+};
+
+&iomuxc {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_hog>;
+
+ pinctrl_hog: hoggrp {
+ fsl,pins = <
+ MX8MM_IOMUXC_SPDIF_TX_GPIO5_IO3 0x40000041 /* PLUG_TEST */
+ MX8MM_IOMUXC_GPIO1_IO06_GPIO1_IO6 0x40000041 /* PCI_USBSEL */
+ MX8MM_IOMUXC_SAI1_RXD5_GPIO4_IO7 0x40000041 /* PCIE_WDIS# */
+ MX8MM_IOMUXC_GPIO1_IO07_GPIO1_IO7 0x40000041 /* DIO0 */
+ MX8MM_IOMUXC_GPIO1_IO09_GPIO1_IO9 0x40000041 /* DIO1 */
+ MX8MM_IOMUXC_GPIO1_IO00_GPIO1_IO0 0x40000104 /* RS485_TERM */
+ MX8MM_IOMUXC_SAI1_RXFS_GPIO4_IO0 0x40000104 /* RS485 */
+ MX8MM_IOMUXC_SAI1_RXD0_GPIO4_IO2 0x40000104 /* RS485_HALF */
+ >;
+ };
+
+ pinctrl_accel: accelgrp {
+ fsl,pins = <
+ MX8MM_IOMUXC_SAI1_RXD3_GPIO4_IO5 0x159
+ >;
+ };
+
+ pinctrl_gpio_leds: gpioledgrp {
+ fsl,pins = <
+ MX8MM_IOMUXC_SPDIF_EXT_CLK_GPIO5_IO5 0x19
+ MX8MM_IOMUXC_SPDIF_RX_GPIO5_IO4 0x19
+ >;
+ };
+
+ pinctrl_i2c3: i2c3grp {
+ fsl,pins = <
+ MX8MM_IOMUXC_I2C3_SCL_I2C3_SCL 0x400001c3
+ MX8MM_IOMUXC_I2C3_SDA_I2C3_SDA 0x400001c3
+ >;
+ };
+
+ pinctrl_pps: ppsgrp {
+ fsl,pins = <
+ MX8MM_IOMUXC_GPIO1_IO15_GPIO1_IO15 0x41
+ >;
+ };
+
+ pinctrl_reg_usb1_en: regusb1grp {
+ fsl,pins = <
+ MX8MM_IOMUXC_GPIO1_IO12_GPIO1_IO12 0x41
+ MX8MM_IOMUXC_GPIO1_IO13_USB1_OTG_OC 0x41
+ >;
+ };
+
+ pinctrl_reg_usb2_en: regusb2grp {
+ fsl,pins = <
+ MX8MM_IOMUXC_GPIO1_IO08_GPIO1_IO8 0x41
+ >;
+ };
+
+ pinctrl_sai3: sai3grp {
+ fsl,pins = <
+ MX8MM_IOMUXC_SAI3_TXFS_SAI3_TX_SYNC 0xd6
+ MX8MM_IOMUXC_SAI3_TXC_SAI3_TX_BCLK 0xd6
+ MX8MM_IOMUXC_SAI3_MCLK_SAI3_MCLK 0xd6
+ MX8MM_IOMUXC_SAI3_TXD_SAI3_TX_DATA0 0xd6
+ MX8MM_IOMUXC_SAI3_RXD_SAI3_RX_DATA0 0xd6
+ >;
+ };
+
+ pinctrl_spi2: spi2grp {
+ fsl,pins = <
+ MX8MM_IOMUXC_ECSPI2_SCLK_ECSPI2_SCLK 0xd6
+ MX8MM_IOMUXC_ECSPI2_MOSI_ECSPI2_MOSI 0xd6
+ MX8MM_IOMUXC_ECSPI2_SCLK_ECSPI2_SCLK 0xd6
+ MX8MM_IOMUXC_ECSPI2_SS0_GPIO5_IO13 0xd6
+ >;
+ };
+
+ pinctrl_uart1: uart1grp {
+ fsl,pins = <
+ MX8MM_IOMUXC_UART1_RXD_UART1_DCE_RX 0x140
+ MX8MM_IOMUXC_UART1_TXD_UART1_DCE_TX 0x140
+ >;
+ };
+
+ pinctrl_uart3: uart3grp {
+ fsl,pins = <
+ MX8MM_IOMUXC_UART3_RXD_UART3_DCE_RX 0x140
+ MX8MM_IOMUXC_UART3_TXD_UART3_DCE_TX 0x140
+ >;
+ };
+
+ pinctrl_uart4: uart4grp {
+ fsl,pins = <
+ MX8MM_IOMUXC_UART4_RXD_UART4_DCE_RX 0x140
+ MX8MM_IOMUXC_UART4_TXD_UART4_DCE_TX 0x140
+ >;
+ };
+
+ pinctrl_usdhc1: usdhc1grp {
+ fsl,pins = <
+ MX8MM_IOMUXC_SD1_CLK_USDHC1_CLK 0x190
+ MX8MM_IOMUXC_SD1_CMD_USDHC1_CMD 0x1d0
+ MX8MM_IOMUXC_SD1_DATA0_USDHC1_DATA0 0x1d0
+ MX8MM_IOMUXC_SD1_DATA1_USDHC1_DATA1 0x1d0
+ MX8MM_IOMUXC_SD1_DATA2_USDHC1_DATA2 0x1d0
+ MX8MM_IOMUXC_SD1_DATA3_USDHC1_DATA3 0x1d0
+ >;
+ };
+
+ pinctrl_usdhc2: usdhc2grp {
+ fsl,pins = <
+ MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK 0x190
+ MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d0
+ MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d0
+ MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d0
+ MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d0
+ MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d0
+ >;
+ };
+
+ pinctrl_usdhc2_100mhz: usdhc2-100mhzgrp {
+ fsl,pins = <
+ MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK 0x194
+ MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d4
+ MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d4
+ MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d4
+ MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d4
+ MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d4
+ >;
+ };
+
+ pinctrl_usdhc2_200mhz: usdhc2-200mhzgrp {
+ fsl,pins = <
+ MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK 0x196
+ MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d6
+ MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d6
+ MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d6
+ MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d6
+ MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d6
+ >;
+ };
+
+ pinctrl_usdhc2_gpio: usdhc2gpiogrp {
+ fsl,pins = <
+ MX8MM_IOMUXC_SD2_CD_B_GPIO2_IO12 0x1c4
+ MX8MM_IOMUXC_SD2_RESET_B_USDHC2_RESET_B 0x1d0
+ MX8MM_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0x1d0
+ >;
+ };
+};
diff --git a/arch/arm/dts/imx8mm-venice-gw73xx-0x-u-boot.dtsi b/arch/arm/dts/imx8mm-venice-gw73xx-0x-u-boot.dtsi
new file mode 100644
index 0000000..f5d52c2
--- /dev/null
+++ b/arch/arm/dts/imx8mm-venice-gw73xx-0x-u-boot.dtsi
@@ -0,0 +1,5 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright 2021 Gateworks Corporation
+ */
+#include "imx8mm-venice-gw700x-u-boot.dtsi"
diff --git a/arch/arm/dts/imx8mm-venice-gw73xx-0x.dts b/arch/arm/dts/imx8mm-venice-gw73xx-0x.dts
new file mode 100644
index 0000000..6905437
--- /dev/null
+++ b/arch/arm/dts/imx8mm-venice-gw73xx-0x.dts
@@ -0,0 +1,19 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright 2020 Gateworks Corporation
+ */
+
+/dts-v1/;
+
+#include "imx8mm.dtsi"
+#include "imx8mm-venice-gw700x.dtsi"
+#include "imx8mm-venice-gw73xx.dtsi"
+
+/ {
+ model = "Gateworks Venice GW73xx-0x i.MX8MM Development Kit";
+ compatible = "gw,imx8mm-gw73xx-0x", "fsl,imx8mm";
+
+ chosen {
+ stdout-path = &uart2;
+ };
+};
diff --git a/arch/arm/dts/imx8mm-venice-gw73xx.dtsi b/arch/arm/dts/imx8mm-venice-gw73xx.dtsi
new file mode 100644
index 0000000..d2ffd62
--- /dev/null
+++ b/arch/arm/dts/imx8mm-venice-gw73xx.dtsi
@@ -0,0 +1,362 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright 2020 Gateworks Corporation
+ */
+
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/leds/common.h>
+
+/ {
+ aliases {
+ usb0 = &usbotg1;
+ usb1 = &usbotg2;
+ };
+
+ led-controller {
+ compatible = "gpio-leds";
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_gpio_leds>;
+
+ led-0 {
+ function = LED_FUNCTION_STATUS;
+ color = <LED_COLOR_ID_GREEN>;
+ gpios = <&gpio5 5 GPIO_ACTIVE_HIGH>;
+ default-state = "on";
+ linux,default-trigger = "heartbeat";
+ };
+
+ led-1 {
+ function = LED_FUNCTION_STATUS;
+ color = <LED_COLOR_ID_RED>;
+ gpios = <&gpio5 4 GPIO_ACTIVE_HIGH>;
+ default-state = "off";
+ };
+ };
+
+ pps {
+ compatible = "pps-gpio";
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_pps>;
+ gpios = <&gpio1 15 GPIO_ACTIVE_HIGH>;
+ status = "okay";
+ };
+
+ reg_1p8v: regulator-1p8v {
+ compatible = "regulator-fixed";
+ regulator-name = "1P8V";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-always-on;
+ };
+
+ reg_3p3v: regulator-3p3v {
+ compatible = "regulator-fixed";
+ regulator-name = "3P3V";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-always-on;
+ };
+
+ reg_usb_otg1_vbus: regulator-usb-otg1 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_reg_usb1_en>;
+ compatible = "regulator-fixed";
+ regulator-name = "usb_otg1_vbus";
+ gpio = <&gpio1 12 GPIO_ACTIVE_HIGH>;
+ enable-active-high;
+ regulator-min-microvolt = <5000000>;
+ regulator-max-microvolt = <5000000>;
+ };
+
+ reg_usb_otg2_vbus: regulator-usb-otg2 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_reg_usb2_en>;
+ compatible = "regulator-fixed";
+ regulator-name = "usb_otg2_vbus";
+ gpio = <&gpio1 8 GPIO_ACTIVE_HIGH>;
+ enable-active-high;
+ regulator-min-microvolt = <5000000>;
+ regulator-max-microvolt = <5000000>;
+ };
+
+ reg_wifi_en: regulator-wifi-en {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_reg_wl>;
+ compatible = "regulator-fixed";
+ regulator-name = "wl";
+ gpio = <&gpio1 5 GPIO_ACTIVE_HIGH>;
+ startup-delay-us = <100>;
+ enable-active-high;
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ };
+};
+
+/* off-board header */
+&ecspi2 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_spi2>;
+ cs-gpios = <&gpio5 13 GPIO_ACTIVE_HIGH>;
+ status = "okay";
+};
+
+&i2c2 {
+ clock-frequency = <400000>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_i2c2>;
+ status = "okay";
+
+ accelerometer@19 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_accel>;
+ compatible = "st,lis2de12";
+ reg = <0x19>;
+ st,drdy-int-pin = <1>;
+ interrupt-parent = <&gpio4>;
+ interrupts = <5 IRQ_TYPE_LEVEL_LOW>;
+ interrupt-names = "INT1";
+ };
+};
+
+/* off-board header */
+&i2c3 {
+ clock-frequency = <400000>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_i2c3>;
+ status = "okay";
+};
+
+/* off-board header */
+&sai3 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_sai3>;
+ assigned-clocks = <&clk IMX8MM_CLK_SAI3>;
+ assigned-clock-parents = <&clk IMX8MM_AUDIO_PLL1_OUT>;
+ assigned-clock-rates = <24576000>;
+ status = "okay";
+};
+
+/* GPS */
+&uart1 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_uart1>;
+ status = "okay";
+};
+
+/* bluetooth HCI */
+&uart3 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_uart3>, <&pinctrl_bten>;
+ cts-gpios = <&gpio5 8 GPIO_ACTIVE_LOW>;
+ rts-gpios = <&gpio5 9 GPIO_ACTIVE_LOW>;
+ status = "okay";
+
+ bluetooth {
+ compatible = "brcm,bcm4330-bt";
+ shutdown-gpios = <&gpio1 3 GPIO_ACTIVE_HIGH>;
+ };
+};
+
+/* RS232 */
+&uart4 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_uart4>;
+ status = "okay";
+};
+
+&usbotg1 {
+ dr_mode = "otg";
+ vbus-supply = <®_usb_otg1_vbus>;
+ status = "okay";
+};
+
+&usbotg2 {
+ dr_mode = "host";
+ vbus-supply = <®_usb_otg2_vbus>;
+ status = "okay";
+};
+
+/* SDIO WiFi */
+&usdhc1 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_usdhc1>;
+ bus-width = <4>;
+ non-removable;
+ vmmc-supply = <®_wifi_en>;
+ status = "okay";
+};
+
+/* microSD */
+&usdhc2 {
+ pinctrl-names = "default", "state_100mhz", "state_200mhz";
+ pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>;
+ pinctrl-1 = <&pinctrl_usdhc2_100mhz>, <&pinctrl_usdhc2_gpio>;
+ pinctrl-2 = <&pinctrl_usdhc2_200mhz>, <&pinctrl_usdhc2_gpio>;
+ cd-gpios = <&gpio2 12 GPIO_ACTIVE_LOW>;
+ bus-width = <4>;
+ vmmc-supply = <®_3p3v>;
+ status = "okay";
+};
+
+&iomuxc {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_hog>;
+
+ pinctrl_hog: hoggrp {
+ fsl,pins = <
+ MX8MM_IOMUXC_SPDIF_TX_GPIO5_IO3 0x40000041 /* PLUG_TEST */
+ MX8MM_IOMUXC_GPIO1_IO06_GPIO1_IO6 0x40000041 /* PCI_USBSEL */
+ MX8MM_IOMUXC_SAI1_RXD5_GPIO4_IO7 0x40000041 /* PCIE_WDIS# */
+ MX8MM_IOMUXC_GPIO1_IO07_GPIO1_IO7 0x40000041 /* DIO0 */
+ MX8MM_IOMUXC_GPIO1_IO09_GPIO1_IO9 0x40000041 /* DIO1 */
+ MX8MM_IOMUXC_GPIO1_IO00_GPIO1_IO0 0x40000104 /* RS485_TERM */
+ MX8MM_IOMUXC_SAI1_RXFS_GPIO4_IO0 0x40000104 /* RS485 */
+ MX8MM_IOMUXC_SAI1_RXD0_GPIO4_IO2 0x40000104 /* RS485_HALF */
+ >;
+ };
+
+ pinctrl_accel: accelgrp {
+ fsl,pins = <
+ MX8MM_IOMUXC_SAI1_RXD3_GPIO4_IO5 0x159
+ >;
+ };
+
+ pinctrl_bten: btengrp {
+ fsl,pins = <
+ MX8MM_IOMUXC_GPIO1_IO03_GPIO1_IO3 0x41
+ >;
+ };
+
+ pinctrl_gpio_leds: gpioledgrp {
+ fsl,pins = <
+ MX8MM_IOMUXC_SPDIF_EXT_CLK_GPIO5_IO5 0x19
+ MX8MM_IOMUXC_SPDIF_RX_GPIO5_IO4 0x19
+ >;
+ };
+
+ pinctrl_i2c3: i2c3grp {
+ fsl,pins = <
+ MX8MM_IOMUXC_I2C3_SCL_I2C3_SCL 0x400001c3
+ MX8MM_IOMUXC_I2C3_SDA_I2C3_SDA 0x400001c3
+ >;
+ };
+
+ pinctrl_pps: ppsgrp {
+ fsl,pins = <
+ MX8MM_IOMUXC_GPIO1_IO15_GPIO1_IO15 0x41
+ >;
+ };
+
+ pinctrl_reg_wl: regwlgrp {
+ fsl,pins = <
+ MX8MM_IOMUXC_GPIO1_IO05_GPIO1_IO5 0x41
+ >;
+ };
+
+ pinctrl_reg_usb1_en: regusb1grp {
+ fsl,pins = <
+ MX8MM_IOMUXC_GPIO1_IO12_GPIO1_IO12 0x41
+ MX8MM_IOMUXC_GPIO1_IO13_USB1_OTG_OC 0x41
+ >;
+ };
+
+ pinctrl_reg_usb2_en: regusb2grp {
+ fsl,pins = <
+ MX8MM_IOMUXC_GPIO1_IO08_GPIO1_IO8 0x41
+ >;
+ };
+
+ pinctrl_sai3: sai3grp {
+ fsl,pins = <
+ MX8MM_IOMUXC_SAI3_TXFS_SAI3_TX_SYNC 0xd6
+ MX8MM_IOMUXC_SAI3_TXC_SAI3_TX_BCLK 0xd6
+ MX8MM_IOMUXC_SAI3_MCLK_SAI3_MCLK 0xd6
+ MX8MM_IOMUXC_SAI3_TXD_SAI3_TX_DATA0 0xd6
+ MX8MM_IOMUXC_SAI3_RXD_SAI3_RX_DATA0 0xd6
+ >;
+ };
+
+ pinctrl_spi2: spi2grp {
+ fsl,pins = <
+ MX8MM_IOMUXC_ECSPI2_SCLK_ECSPI2_SCLK 0xd6
+ MX8MM_IOMUXC_ECSPI2_MOSI_ECSPI2_MOSI 0xd6
+ MX8MM_IOMUXC_ECSPI2_SCLK_ECSPI2_SCLK 0xd6
+ MX8MM_IOMUXC_ECSPI2_SS0_GPIO5_IO13 0xd6
+ >;
+ };
+
+ pinctrl_uart1: uart1grp {
+ fsl,pins = <
+ MX8MM_IOMUXC_UART1_RXD_UART1_DCE_RX 0x140
+ MX8MM_IOMUXC_UART1_TXD_UART1_DCE_TX 0x140
+ >;
+ };
+
+ pinctrl_uart3: uart3grp {
+ fsl,pins = <
+ MX8MM_IOMUXC_UART3_RXD_UART3_DCE_RX 0x140
+ MX8MM_IOMUXC_UART3_TXD_UART3_DCE_TX 0x140
+ MX8MM_IOMUXC_ECSPI1_MISO_GPIO5_IO8 0x140
+ MX8MM_IOMUXC_ECSPI1_SS0_GPIO5_IO9 0x140
+ >;
+ };
+
+ pinctrl_uart4: uart4grp {
+ fsl,pins = <
+ MX8MM_IOMUXC_UART4_RXD_UART4_DCE_RX 0x140
+ MX8MM_IOMUXC_UART4_TXD_UART4_DCE_TX 0x140
+ >;
+ };
+
+ pinctrl_usdhc1: usdhc1grp {
+ fsl,pins = <
+ MX8MM_IOMUXC_SD1_CLK_USDHC1_CLK 0x190
+ MX8MM_IOMUXC_SD1_CMD_USDHC1_CMD 0x1d0
+ MX8MM_IOMUXC_SD1_DATA0_USDHC1_DATA0 0x1d0
+ MX8MM_IOMUXC_SD1_DATA1_USDHC1_DATA1 0x1d0
+ MX8MM_IOMUXC_SD1_DATA2_USDHC1_DATA2 0x1d0
+ MX8MM_IOMUXC_SD1_DATA3_USDHC1_DATA3 0x1d0
+ >;
+ };
+
+ pinctrl_usdhc2: usdhc2grp {
+ fsl,pins = <
+ MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK 0x190
+ MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d0
+ MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d0
+ MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d0
+ MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d0
+ MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d0
+ >;
+ };
+
+ pinctrl_usdhc2_100mhz: usdhc2-100mhzgrp {
+ fsl,pins = <
+ MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK 0x194
+ MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d4
+ MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d4
+ MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d4
+ MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d4
+ MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d4
+ >;
+ };
+
+ pinctrl_usdhc2_200mhz: usdhc2-200mhzgrp {
+ fsl,pins = <
+ MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK 0x196
+ MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d6
+ MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d6
+ MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d6
+ MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d6
+ MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d6
+ >;
+ };
+
+ pinctrl_usdhc2_gpio: usdhc2gpiogrp {
+ fsl,pins = <
+ MX8MM_IOMUXC_SD2_CD_B_GPIO2_IO12 0x1c4
+ MX8MM_IOMUXC_SD2_RESET_B_USDHC2_RESET_B 0x1d0
+ MX8MM_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0x1d0
+ >;
+ };
+};
diff --git a/arch/arm/dts/imx8mm-venice-u-boot.dtsi b/arch/arm/dts/imx8mm-venice-u-boot.dtsi
new file mode 100644
index 0000000..5b06d87
--- /dev/null
+++ b/arch/arm/dts/imx8mm-venice-u-boot.dtsi
@@ -0,0 +1,103 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright 2021 Gateworks Corporation
+ */
+
+/ {
+ wdt-reboot {
+ compatible = "wdt-reboot";
+ wdt = <&wdog1>;
+ u-boot,dm-spl;
+ };
+};
+
+&{/soc@0} {
+ u-boot,dm-pre-reloc;
+ u-boot,dm-spl;
+};
+
+&clk {
+ u-boot,dm-spl;
+ u-boot,dm-pre-reloc;
+ /delete-property/ assigned-clocks;
+ /delete-property/ assigned-clock-parents;
+ /delete-property/ assigned-clock-rates;
+};
+
+&osc_24m {
+ u-boot,dm-spl;
+ u-boot,dm-pre-reloc;
+};
+
+&aips1 {
+ u-boot,dm-spl;
+ u-boot,dm-pre-reloc;
+};
+
+&aips2 {
+ u-boot,dm-spl;
+};
+
+&aips3 {
+ u-boot,dm-spl;
+};
+
+&iomuxc {
+ u-boot,dm-spl;
+};
+
+&gpio1 {
+ u-boot,dm-spl;
+};
+
+&gpio2 {
+ u-boot,dm-spl;
+};
+
+&gpio3 {
+ u-boot,dm-spl;
+};
+
+&gpio4 {
+ u-boot,dm-spl;
+};
+
+&gpio5 {
+ u-boot,dm-spl;
+};
+
+&uart2 {
+ u-boot,dm-spl;
+};
+
+&pinctrl_uart2 {
+ u-boot,dm-spl;
+};
+
+&usdhc3 {
+ u-boot,dm-spl;
+};
+
+&pinctrl_usdhc3 {
+ u-boot,dm-spl;
+};
+
+&i2c1 {
+ u-boot,dm-spl;
+};
+
+&pinctrl_i2c1 {
+ u-boot,dm-spl;
+};
+
+&i2c2 {
+ u-boot,dm-spl;
+};
+
+&pinctrl_i2c2 {
+ u-boot,dm-spl;
+};
+
+&wdog1 {
+ u-boot,dm-spl;
+};
diff --git a/arch/arm/dts/imx8mm-venice.dts b/arch/arm/dts/imx8mm-venice.dts
new file mode 100644
index 0000000..54505a0
--- /dev/null
+++ b/arch/arm/dts/imx8mm-venice.dts
@@ -0,0 +1,152 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright 2021 Gateworks Corporation
+ */
+
+/dts-v1/;
+
+#include "imx8mm.dtsi"
+
+/ {
+ model = "Gateworks Venice i.MX8MM board";
+ compatible = "gw,imx8mm-venice", "fsl,imx8mm";
+
+ chosen {
+ stdout-path = &uart2;
+ };
+
+ memory@40000000 {
+ device_type = "memory";
+ reg = <0x0 0x40000000 0 0x80000000>;
+ };
+};
+
+&i2c1 {
+ clock-frequency = <100000>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_i2c1>;
+ status = "okay";
+
+ eeprom@51 {
+ compatible = "atmel,24c02";
+ reg = <0x51>;
+ pagesize = <16>;
+ };
+};
+
+&i2c2 {
+ clock-frequency = <400000>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_i2c2>;
+ status = "okay";
+
+ eeprom@52 {
+ compatible = "atmel,24c32";
+ reg = <0x52>;
+ pagesize = <32>;
+ };
+};
+
+/* console */
+&uart2 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_uart2>;
+ status = "okay";
+};
+
+/* eMMC */
+&usdhc3 {
+ assigned-clocks = <&clk IMX8MM_CLK_USDHC3_ROOT>;
+ assigned-clock-rates = <400000000>;
+ pinctrl-names = "default", "state_100mhz", "state_200mhz";
+ pinctrl-0 = <&pinctrl_usdhc3>;
+ pinctrl-1 = <&pinctrl_usdhc3_100mhz>;
+ pinctrl-2 = <&pinctrl_usdhc3_200mhz>;
+ bus-width = <8>;
+ non-removable;
+ status = "okay";
+};
+
+&wdog1 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_wdog>;
+ fsl,ext-reset-output;
+ status = "okay";
+};
+
+&iomuxc {
+ pinctrl_i2c1: i2c1grp {
+ fsl,pins = <
+ MX8MM_IOMUXC_I2C1_SCL_I2C1_SCL 0x400001c3
+ MX8MM_IOMUXC_I2C1_SDA_I2C1_SDA 0x400001c3
+ >;
+ };
+
+ pinctrl_i2c2: i2c2grp {
+ fsl,pins = <
+ MX8MM_IOMUXC_I2C2_SCL_I2C2_SCL 0x400001c3
+ MX8MM_IOMUXC_I2C2_SDA_I2C2_SDA 0x400001c3
+ >;
+ };
+
+ pinctrl_uart2: uart2grp {
+ fsl,pins = <
+ MX8MM_IOMUXC_UART2_RXD_UART2_DCE_RX 0x140
+ MX8MM_IOMUXC_UART2_TXD_UART2_DCE_TX 0x140
+ >;
+ };
+
+ pinctrl_usdhc3: usdhc3grp {
+ fsl,pins = <
+ MX8MM_IOMUXC_NAND_WE_B_USDHC3_CLK 0x190
+ MX8MM_IOMUXC_NAND_WP_B_USDHC3_CMD 0x1d0
+ MX8MM_IOMUXC_NAND_DATA04_USDHC3_DATA0 0x1d0
+ MX8MM_IOMUXC_NAND_DATA05_USDHC3_DATA1 0x1d0
+ MX8MM_IOMUXC_NAND_DATA06_USDHC3_DATA2 0x1d0
+ MX8MM_IOMUXC_NAND_DATA07_USDHC3_DATA3 0x1d0
+ MX8MM_IOMUXC_NAND_RE_B_USDHC3_DATA4 0x1d0
+ MX8MM_IOMUXC_NAND_CE2_B_USDHC3_DATA5 0x1d0
+ MX8MM_IOMUXC_NAND_CE3_B_USDHC3_DATA6 0x1d0
+ MX8MM_IOMUXC_NAND_CLE_USDHC3_DATA7 0x1d0
+ MX8MM_IOMUXC_NAND_CE1_B_USDHC3_STROBE 0x190
+ >;
+ };
+
+ pinctrl_usdhc3_100mhz: usdhc3grp100mhz {
+ fsl,pins = <
+ MX8MM_IOMUXC_NAND_WE_B_USDHC3_CLK 0x194
+ MX8MM_IOMUXC_NAND_WP_B_USDHC3_CMD 0x1d4
+ MX8MM_IOMUXC_NAND_DATA04_USDHC3_DATA0 0x1d4
+ MX8MM_IOMUXC_NAND_DATA05_USDHC3_DATA1 0x1d4
+ MX8MM_IOMUXC_NAND_DATA06_USDHC3_DATA2 0x1d4
+ MX8MM_IOMUXC_NAND_DATA07_USDHC3_DATA3 0x1d4
+ MX8MM_IOMUXC_NAND_RE_B_USDHC3_DATA4 0x1d4
+ MX8MM_IOMUXC_NAND_CE2_B_USDHC3_DATA5 0x1d4
+ MX8MM_IOMUXC_NAND_CE3_B_USDHC3_DATA6 0x1d4
+ MX8MM_IOMUXC_NAND_CLE_USDHC3_DATA7 0x1d4
+ MX8MM_IOMUXC_NAND_CE1_B_USDHC3_STROBE 0x194
+ >;
+ };
+
+ pinctrl_usdhc3_200mhz: usdhc3grp200mhz {
+ fsl,pins = <
+ MX8MM_IOMUXC_NAND_WE_B_USDHC3_CLK 0x196
+ MX8MM_IOMUXC_NAND_WP_B_USDHC3_CMD 0x1d6
+ MX8MM_IOMUXC_NAND_DATA04_USDHC3_DATA0 0x1d6
+ MX8MM_IOMUXC_NAND_DATA05_USDHC3_DATA1 0x1d6
+ MX8MM_IOMUXC_NAND_DATA06_USDHC3_DATA2 0x1d6
+ MX8MM_IOMUXC_NAND_DATA07_USDHC3_DATA3 0x1d6
+ MX8MM_IOMUXC_NAND_RE_B_USDHC3_DATA4 0x1d6
+ MX8MM_IOMUXC_NAND_CE2_B_USDHC3_DATA5 0x1d6
+ MX8MM_IOMUXC_NAND_CE3_B_USDHC3_DATA6 0x1d6
+ MX8MM_IOMUXC_NAND_CLE_USDHC3_DATA7 0x1d6
+ MX8MM_IOMUXC_NAND_CE1_B_USDHC3_STROBE 0x196
+ >;
+ };
+
+ pinctrl_wdog: wdoggrp {
+ fsl,pins = <
+ MX8MM_IOMUXC_GPIO1_IO02_WDOG1_WDOG_B 0xc6
+ >;
+ };
+};
diff --git a/arch/arm/dts/imx8mp-evk-u-boot.dtsi b/arch/arm/dts/imx8mp-evk-u-boot.dtsi
index 0bf6ef5..6a91404 100644
--- a/arch/arm/dts/imx8mp-evk-u-boot.dtsi
+++ b/arch/arm/dts/imx8mp-evk-u-boot.dtsi
@@ -142,4 +142,6 @@
&fec {
phy-reset-gpios = <&gpio4 2 GPIO_ACTIVE_LOW>;
+ phy-reset-duration = <15>;
+ phy-reset-post-delay = <100>;
};
diff --git a/arch/arm/dts/imx8mq-evk-u-boot.dtsi b/arch/arm/dts/imx8mq-evk-u-boot.dtsi
index 44af663..2cfc12b 100644
--- a/arch/arm/dts/imx8mq-evk-u-boot.dtsi
+++ b/arch/arm/dts/imx8mq-evk-u-boot.dtsi
@@ -1,9 +1,5 @@
// SPDX-License-Identifier: (GPL-2.0 OR MIT)
-®_usdhc2_vmmc {
- u-boot,off-on-delay-us = <20000>;
-};
-
&usdhc1 {
mmc-hs400-1_8v;
};
diff --git a/arch/arm/dts/socfpga_soc64_fit-u-boot.dtsi b/arch/arm/dts/socfpga_soc64_fit-u-boot.dtsi
index cf36559..4b30473 100644
--- a/arch/arm/dts/socfpga_soc64_fit-u-boot.dtsi
+++ b/arch/arm/dts/socfpga_soc64_fit-u-boot.dtsi
@@ -117,4 +117,26 @@
};
};
+#if defined(CONFIG_SOCFPGA_SECURE_VAB_AUTH)
+&uboot_blob {
+ filename = "signed-u-boot-nodtb.bin";
+};
+
+&atf_blob {
+ filename = "signed-bl31.bin";
+};
+
+&uboot_fdt_blob {
+ filename = "signed-u-boot.dtb";
+};
+
+&kernel_blob {
+ filename = "signed-Image";
+};
+
+&kernel_fdt_blob {
+ filename = "signed-linux.dtb";
+};
+#endif
+
#endif
diff --git a/arch/arm/dts/stm32mp15-pinctrl.dtsi b/arch/arm/dts/stm32mp15-pinctrl.dtsi
index dd4bd1e..20a59e8 100644
--- a/arch/arm/dts/stm32mp15-pinctrl.dtsi
+++ b/arch/arm/dts/stm32mp15-pinctrl.dtsi
@@ -1971,86 +1971,6 @@
};
};
- uart4_pins_a: uart4-0 {
- pins1 {
- pinmux = <STM32_PINMUX('G', 11, AF6)>; /* UART4_TX */
- bias-disable;
- drive-push-pull;
- slew-rate = <0>;
- };
- pins2 {
- pinmux = <STM32_PINMUX('B', 2, AF8)>; /* UART4_RX */
- bias-disable;
- };
- };
-
- uart4_pins_b: uart4-1 {
- pins1 {
- pinmux = <STM32_PINMUX('D', 1, AF8)>; /* UART4_TX */
- bias-disable;
- drive-push-pull;
- slew-rate = <0>;
- };
- pins2 {
- pinmux = <STM32_PINMUX('B', 2, AF8)>; /* UART4_RX */
- bias-disable;
- };
- };
-
- uart4_pins_c: uart4-2 {
- pins1 {
- pinmux = <STM32_PINMUX('G', 11, AF6)>; /* UART4_TX */
- bias-disable;
- drive-push-pull;
- slew-rate = <0>;
- };
- pins2 {
- pinmux = <STM32_PINMUX('B', 2, AF8)>; /* UART4_RX */
- bias-disable;
- };
- };
-
- uart7_pins_a: uart7-0 {
- pins1 {
- pinmux = <STM32_PINMUX('E', 8, AF7)>; /* UART4_TX */
- bias-disable;
- drive-push-pull;
- slew-rate = <0>;
- };
- pins2 {
- pinmux = <STM32_PINMUX('E', 7, AF7)>, /* UART4_RX */
- <STM32_PINMUX('E', 10, AF7)>, /* UART4_CTS */
- <STM32_PINMUX('E', 9, AF7)>; /* UART4_RTS */
- bias-disable;
- };
- };
-
- uart7_pins_b: uart7-1 {
- pins1 {
- pinmux = <STM32_PINMUX('F', 7, AF7)>; /* UART7_TX */
- bias-disable;
- drive-push-pull;
- slew-rate = <0>;
- };
- pins2 {
- pinmux = <STM32_PINMUX('F', 6, AF7)>; /* UART7_RX */
- bias-disable;
- };
- };
-
- uart8_pins_a: uart8-0 {
- pins1 {
- pinmux = <STM32_PINMUX('E', 1, AF8)>; /* UART8_TX */
- bias-disable;
- drive-push-pull;
- slew-rate = <0>;
- };
- pins2 {
- pinmux = <STM32_PINMUX('E', 0, AF8)>; /* UART8_RX */
- bias-disable;
- };
- };
-
usbotg_hs_pins_a: usbotg-hs-0 {
pins {
pinmux = <STM32_PINMUX('A', 10, ANALOG)>; /* OTG_ID */
diff --git a/arch/arm/dts/stm32mp151.dtsi b/arch/arm/dts/stm32mp151.dtsi
index eedea6f..b564fc6 100644
--- a/arch/arm/dts/stm32mp151.dtsi
+++ b/arch/arm/dts/stm32mp151.dtsi
@@ -1136,6 +1136,10 @@
reg = <0x50000000 0x1000>;
#clock-cells = <1>;
#reset-cells = <1>;
+
+ clock-names = "hse", "hsi", "csi", "lse", "lsi";
+ clocks = <&clk_hse>, <&clk_hsi>, <&clk_csi>,
+ <&clk_lse>, <&clk_lsi>;
};
pwr_regulators: pwr@50001000 {
diff --git a/arch/arm/include/asm/arch-fsl-layerscape/cpu.h b/arch/arm/include/asm/arch-fsl-layerscape/cpu.h
index 4335aa0..c51b65e 100644
--- a/arch/arm/include/asm/arch-fsl-layerscape/cpu.h
+++ b/arch/arm/include/asm/arch-fsl-layerscape/cpu.h
@@ -69,8 +69,6 @@
#define CONFIG_SYS_FSL_DRAM_SIZE2 0x7F80000000
#endif
#elif defined(CONFIG_FSL_LSCH2)
-#define CONFIG_SYS_FSL_BOOTROM_BASE 0x0
-#define CONFIG_SYS_FSL_BOOTROM_SIZE 0x1000000
#define CONFIG_SYS_FSL_CCSR_BASE 0x1000000
#define CONFIG_SYS_FSL_CCSR_SIZE 0xf000000
#define CONFIG_SYS_FSL_DCSR_BASE 0x20000000
diff --git a/arch/arm/include/asm/arch-imx8/imx-regs.h b/arch/arm/include/asm/arch-imx8/imx-regs.h
index 6333ff4..ed6e05e 100644
--- a/arch/arm/include/asm/arch-imx8/imx-regs.h
+++ b/arch/arm/include/asm/arch-imx8/imx-regs.h
@@ -26,6 +26,8 @@
#define LPI2C4_BASE_ADDR 0x5A830000
#define LPI2C5_BASE_ADDR 0x5A840000
+#define FEC_QUIRK_ENET_MAC
+
#ifdef CONFIG_IMX8QXP
#define LVDS0_PHYCTRL_BASE 0x56221000
#define LVDS1_PHYCTRL_BASE 0x56241000
diff --git a/arch/arm/include/asm/arch-imx8m/imx-regs.h b/arch/arm/include/asm/arch-imx8m/imx-regs.h
index f571115..3f50014 100644
--- a/arch/arm/include/asm/arch-imx8m/imx-regs.h
+++ b/arch/arm/include/asm/arch-imx8m/imx-regs.h
@@ -63,6 +63,7 @@
#define DDR_CSD1_BASE_ADDR 0x40000000
#define IOMUXC_GPR_GPR1_GPR_ENET_QOS_INTF_SEL_MASK 0x70000
+#define FEC_QUIRK_ENET_MAC
#if !defined(__ASSEMBLY__)
#include <asm/types.h>
diff --git a/arch/arm/include/asm/global_data.h b/arch/arm/include/asm/global_data.h
index 5a935d3..fba655f 100644
--- a/arch/arm/include/asm/global_data.h
+++ b/arch/arm/include/asm/global_data.h
@@ -7,6 +7,8 @@
#ifndef __ASM_GBL_DATA_H
#define __ASM_GBL_DATA_H
+#ifndef __ASSEMBLY__
+
#include <asm/types.h>
#include <linux/types.h>
@@ -125,4 +127,6 @@
#endif
}
+#endif /* __ASSEMBLY__ */
+
#endif /* __ASM_GBL_DATA_H */
diff --git a/arch/arm/mach-imx/Makefile b/arch/arm/mach-imx/Makefile
index 1aa26a5..e6b4654 100644
--- a/arch/arm/mach-imx/Makefile
+++ b/arch/arm/mach-imx/Makefile
@@ -202,10 +202,10 @@
quiet_cmd_pad_cat = CAT $@
cmd_pad_cat = $(cmd_objcopy) && $(append) || rm -f $@
-u-boot-with-spl.imx: SPL u-boot.uim FORCE
+u-boot-with-spl.imx: SPL $(if $(CONFIG_OF_SEPARATE),u-boot.img,u-boot.uim) FORCE
$(call if_changed,pad_cat)
-u-boot-with-nand-spl.imx: spl/u-boot-nand-spl.imx u-boot.uim FORCE
+u-boot-with-nand-spl.imx: spl/u-boot-nand-spl.imx $(if $(CONFIG_OF_SEPARATE),u-boot.img,u-boot.uim) FORCE
$(call if_changed,pad_cat)
quiet_cmd_u-boot-nand-spl_imx = GEN $@
diff --git a/arch/arm/mach-imx/imx8m/Kconfig b/arch/arm/mach-imx/imx8m/Kconfig
index c455f7b..12b8d0d 100644
--- a/arch/arm/mach-imx/imx8m/Kconfig
+++ b/arch/arm/mach-imx/imx8m/Kconfig
@@ -43,6 +43,12 @@
select SUPPORT_SPL
select IMX8M_LPDDR4
+config TARGET_IMX8MM_VENICE
+ bool "Support Gateworks Venice iMX8M Mini module"
+ select IMX8MM
+ select SUPPORT_SPL
+ select IMX8M_LPDDR4
+
config TARGET_IMX8MN_DDR4_EVK
bool "imx8mn DDR4 EVK board"
select IMX8MN
@@ -95,6 +101,7 @@
source "board/freescale/imx8mm_evk/Kconfig"
source "board/freescale/imx8mn_evk/Kconfig"
source "board/freescale/imx8mp_evk/Kconfig"
+source "board/gateworks/venice/Kconfig"
source "board/google/imx8mq_phanbell/Kconfig"
source "board/technexion/pico-imx8mq/Kconfig"
source "board/toradex/verdin-imx8mm/Kconfig"
diff --git a/arch/arm/mach-imx/imx8m/soc.c b/arch/arm/mach-imx/imx8m/soc.c
index 5456c10..5f37282 100644
--- a/arch/arm/mach-imx/imx8m/soc.c
+++ b/arch/arm/mach-imx/imx8m/soc.c
@@ -154,6 +154,17 @@
struct mm_region *mem_map = imx8m_mem_map;
+static unsigned int imx8m_find_dram_entry_in_mem_map(void)
+{
+ int i;
+
+ for (i = 0; i < ARRAY_SIZE(imx8m_mem_map); i++)
+ if (imx8m_mem_map[i].phys == CONFIG_SYS_SDRAM_BASE)
+ return i;
+
+ hang(); /* Entry not found, this must never happen. */
+}
+
void enable_caches(void)
{
/* If OPTEE runs, remove OPTEE memory from MMU table to avoid speculative prefetch */
@@ -167,10 +178,11 @@
* please make sure that entry initial value matches
* imx8m_mem_map for DRAM1
*/
- int entry = 5;
+ int entry = imx8m_find_dram_entry_in_mem_map();
u64 attrs = imx8m_mem_map[entry].attrs;
- while (i < CONFIG_NR_DRAM_BANKS && entry < 8) {
+ while (i < CONFIG_NR_DRAM_BANKS &&
+ entry < ARRAY_SIZE(imx8m_mem_map)) {
if (gd->bd->bi_dram[i].start == 0)
break;
imx8m_mem_map[entry].phys = gd->bd->bi_dram[i].start;
@@ -198,6 +210,7 @@
int dram_init(void)
{
+ unsigned int entry = imx8m_find_dram_entry_in_mem_map();
phys_size_t sdram_size;
int ret;
@@ -212,7 +225,7 @@
gd->ram_size = sdram_size;
/* also update the SDRAM size in the mem_map used externally */
- imx8m_mem_map[5].size = sdram_size;
+ imx8m_mem_map[entry].size = sdram_size;
#ifdef PHYS_SDRAM_2_SIZE
gd->ram_size += PHYS_SDRAM_2_SIZE;
diff --git a/arch/arm/mach-imx/mx2/Kconfig b/arch/arm/mach-imx/mx2/Kconfig
index 30a331a..fad5dcc 100644
--- a/arch/arm/mach-imx/mx2/Kconfig
+++ b/arch/arm/mach-imx/mx2/Kconfig
@@ -8,12 +8,6 @@
prompt "MX25 board select"
optional
-config TARGET_MX25PDK
- bool "Support mx25pdk"
- select BOARD_LATE_INIT
- select CPU_ARM926EJS
- select BOARD_EARLY_INIT_F
-
config TARGET_ZMX25
bool "Support zmx25"
select BOARD_LATE_INIT
@@ -24,7 +18,6 @@
config SYS_SOC
default "mx25"
-source "board/freescale/mx25pdk/Kconfig"
source "board/syteco/zmx25/Kconfig"
endif
diff --git a/arch/arm/mach-imx/mx5/Kconfig b/arch/arm/mach-imx/mx5/Kconfig
index bde37bb..4ee7f6b 100644
--- a/arch/arm/mach-imx/mx5/Kconfig
+++ b/arch/arm/mach-imx/mx5/Kconfig
@@ -44,10 +44,6 @@
select BOARD_LATE_INIT
select MX51
-config TARGET_MX53ARD
- bool "Support mx53ard"
- select MX53
-
config TARGET_MX53CX9020
bool "Support CX9020"
select BOARD_LATE_INIT
@@ -72,10 +68,6 @@
help
Enable support for the GE Healthcare PPD.
-config TARGET_MX53SMD
- bool "Support mx53smd"
- select MX53
-
config TARGET_TS4800
bool "Support TS4800"
select MX51
@@ -91,10 +83,8 @@
source "board/beckhoff/mx53cx9020/Kconfig"
source "board/freescale/mx51evk/Kconfig"
-source "board/freescale/mx53ard/Kconfig"
source "board/freescale/mx53evk/Kconfig"
source "board/freescale/mx53loco/Kconfig"
-source "board/freescale/mx53smd/Kconfig"
source "board/ge/mx53ppd/Kconfig"
source "board/inversepath/usbarmory/Kconfig"
source "board/k+p/kp_imx53/Kconfig"
diff --git a/arch/arm/mach-imx/mx6/Kconfig b/arch/arm/mach-imx/mx6/Kconfig
index 513d007..92fb4c4 100644
--- a/arch/arm/mach-imx/mx6/Kconfig
+++ b/arch/arm/mach-imx/mx6/Kconfig
@@ -554,11 +554,6 @@
config TARGET_SECOMX6
bool "secomx6 boards"
-config TARGET_SKSIMX6
- bool "sks-imx6"
- depends on MX6QDL
- select SUPPORT_SPL
-
config TARGET_SOMLABS_VISIONSOM_6ULL
bool "visionsom-6ull"
depends on MX6ULL
@@ -737,7 +732,6 @@
source "board/liebherr/mccmon6/Kconfig"
source "board/logicpd/imx6/Kconfig"
source "board/seco/Kconfig"
-source "board/sks-kinkel/sksimx6/Kconfig"
source "board/solidrun/mx6cuboxi/Kconfig"
source "board/somlabs/visionsom-6ull/Kconfig"
source "board/technexion/pico-imx6/Kconfig"
diff --git a/arch/arm/mach-imx/mx6/soc.c b/arch/arm/mach-imx/mx6/soc.c
index bf6dddf..aacfc85 100644
--- a/arch/arm/mach-imx/mx6/soc.c
+++ b/arch/arm/mach-imx/mx6/soc.c
@@ -7,6 +7,7 @@
*/
#include <common.h>
+#include <env.h>
#include <init.h>
#include <linux/delay.h>
#include <linux/errno.h>
@@ -696,11 +697,47 @@
#endif
#ifdef CONFIG_ARCH_MISC_INIT
+/*
+ * UNIQUE_ID describes a unique ID based on silicon wafer
+ * and die X/Y position
+ *
+ * UNIQUE_ID offset 0x410
+ * 31:0 fuse 0
+ * FSL-wide unique, encoded LOT ID STD II/SJC CHALLENGE/ Unique ID
+ *
+ * UNIQUE_ID offset 0x420
+ * 31:24 fuse 1
+ * The X-coordinate of the die location on the wafer/SJC CHALLENGE/ Unique ID
+ * 23:16 fuse 1
+ * The Y-coordinate of the die location on the wafer/SJC CHALLENGE/ Unique ID
+ * 15:11 fuse 1
+ * The wafer number of the wafer on which the device was fabricated/SJC
+ * CHALLENGE/ Unique ID
+ * 10:0 fuse 1
+ * FSL-wide unique, encoded LOT ID STD II/SJC CHALLENGE/ Unique ID
+ */
+static void setup_serial_number(void)
+{
+ char serial_string[17];
+ struct ocotp_regs *ocotp = (struct ocotp_regs *)OCOTP_BASE_ADDR;
+ struct fuse_bank *bank = &ocotp->bank[0];
+ struct fuse_bank0_regs *fuse =
+ (struct fuse_bank0_regs *)bank->fuse_regs;
+
+ if (env_get("serial#"))
+ return;
+
+ snprintf(serial_string, sizeof(serial_string), "%08x%08x",
+ fuse->uid_low, fuse->uid_high);
+ env_set("serial#", serial_string);
+}
+
int arch_misc_init(void)
{
#ifdef CONFIG_FSL_CAAM
sec_init();
#endif
+ setup_serial_number();
return 0;
}
#endif
diff --git a/arch/arm/mach-mvebu/include/mach/cpu.h b/arch/arm/mach-mvebu/include/mach/cpu.h
index c3f8ad8..52473ad 100644
--- a/arch/arm/mach-mvebu/include/mach/cpu.h
+++ b/arch/arm/mach-mvebu/include/mach/cpu.h
@@ -164,7 +164,7 @@
int ddr3_init(void);
/* Auto Voltage Scaling */
-#if defined(CONFIG_ARMADA_38X) || defined(CONFIG_ARMADA_39X)
+#if defined(CONFIG_ARMADA_38X)
void mv_avs_init(void);
void mv_rtc_config(void);
#else
diff --git a/arch/arm/mach-mvebu/serdes/a38x/high_speed_env_spec.c b/arch/arm/mach-mvebu/serdes/a38x/high_speed_env_spec.c
index ae2a361..3b41c7d 100644
--- a/arch/arm/mach-mvebu/serdes/a38x/high_speed_env_spec.c
+++ b/arch/arm/mach-mvebu/serdes/a38x/high_speed_env_spec.c
@@ -14,11 +14,6 @@
#include "sys_env_lib.h"
#include "ctrl_pex.h"
-#if defined(CONFIG_ARMADA_38X)
-#elif defined(CONFIG_ARMADA_39X)
-#else
-#error "No device is defined"
-#endif
/*
@@ -79,11 +74,6 @@
{ NA, 0x6, NA, NA, 0x4, NA, NA }, /* USB3_HOST0 */
{ NA, NA, NA, 0x5, NA, 0x4, NA }, /* USB3_HOST1 */
{ NA, NA, NA, 0x6, 0x5, 0x5, NA }, /* USB3_DEVICE */
-#ifdef CONFIG_ARMADA_39X
- { NA, NA, 0x5, NA, 0x8, NA, 0x2 }, /* SGMII3 */
- { NA, NA, NA, 0x8, 0x9, 0x8, 0x4 }, /* XAUI */
- { NA, NA, NA, NA, NA, 0x8, 0x4 }, /* RXAUI */
-#endif
{ 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, NA } /* DEFAULT_SERDES */
};
@@ -798,11 +788,9 @@
*/
u8 hws_ctrl_serdes_rev_get(void)
{
-#ifdef CONFIG_ARMADA_38X
/* for A38x-Z1 */
if (sys_env_device_rev_get() == MV_88F68XX_Z1_ID)
return MV_SERDES_REV_1_2;
-#endif
/* for A39x-Z1, A38x-A0 */
return MV_SERDES_REV_2_1;
@@ -1351,9 +1339,6 @@
case SGMII0:
case SGMII1:
case SGMII2:
-#ifdef CONFIG_ARMADA_39X
- case SGMII3:
-#endif
if (baud_rate == SERDES_SPEED_1_25_GBPS)
seq_id = SGMII_1_25_SPEED_CONFIG_SEQ;
else if (baud_rate == SERDES_SPEED_3_125_GBPS)
@@ -1362,14 +1347,6 @@
case QSGMII:
seq_id = QSGMII_5_SPEED_CONFIG_SEQ;
break;
-#ifdef CONFIG_ARMADA_39X
- case XAUI:
- seq_id = XAUI_3_125_SPEED_CONFIG_SEQ;
- break;
- case RXAUI:
- seq_id = RXAUI_6_25_SPEED_CONFIG_SEQ;
- break;
-#endif
default:
return SERDES_LAST_SEQ;
}
@@ -2054,13 +2031,6 @@
(serdes_num,
PEX_CONFIG_REF_CLOCK_100MHZ_SEQ));
return MV_OK;
-#ifdef CONFIG_ARMADA_39X
- case REF_CLOCK_40MHZ:
- CHECK_STATUS(mv_seq_exec
- (serdes_num,
- PEX_CONFIG_REF_CLOCK_40MHZ_SEQ));
- return MV_OK;
-#endif
default:
printf
("%s: Error: ref_clock %d for SerDes lane #%d, type %d is not supported\n",
@@ -2104,22 +2074,6 @@
return MV_BAD_PARAM;
}
break;
-#ifdef CONFIG_ARMADA_39X
- case SGMII3:
- case XAUI:
- case RXAUI:
- if (ref_clock == REF_CLOCK_25MHZ) {
- data1 = POWER_AND_PLL_CTRL_REG_25MHZ_VAL_1;
- } else if (ref_clock == REF_CLOCK_40MHZ) {
- data1 = POWER_AND_PLL_CTRL_REG_40MHZ_VAL;
- } else {
- printf
- ("hws_ref_clock_set: ref clock is not valid for serdes type %d\n",
- serdes_type);
- return MV_BAD_PARAM;
- }
- break;
-#endif
default:
DEBUG_INIT_S("hws_ref_clock_set: not supported serdes type\n");
return MV_BAD_PARAM;
diff --git a/arch/arm/mach-mvebu/serdes/a38x/sys_env_lib.c b/arch/arm/mach-mvebu/serdes/a38x/sys_env_lib.c
index 3c4c7e0..950680a 100644
--- a/arch/arm/mach-mvebu/serdes/a38x/sys_env_lib.c
+++ b/arch/arm/mach-mvebu/serdes/a38x/sys_env_lib.c
@@ -12,7 +12,6 @@
#include "seq_exec.h"
#include "sys_env_lib.h"
-#ifdef CONFIG_ARMADA_38X
enum unit_id sys_env_soc_unit_nums[MAX_UNITS_ID][MAX_DEV_ID_NUM] = {
/* 6820 6810 6811 6828 */
/* PEX_UNIT_ID */ { 4, 3, 3, 4},
@@ -24,19 +23,6 @@
/* XAUI_UNIT_ID */ { 0, 0, 0, 0},
/* RXAUI_UNIT_ID */ { 0, 0, 0, 0}
};
-#else /* if (CONFIG_ARMADA_39X) */
-enum unit_id sys_env_soc_unit_nums[MAX_UNITS_ID][MAX_DEV_ID_NUM] = {
-/* 6920 6928 */
-/* PEX_UNIT_ID */ { 4, 4},
-/* ETH_GIG_UNIT_ID */ { 3, 4},
-/* USB3H_UNIT_ID */ { 1, 2},
-/* USB3D_UNIT_ID */ { 0, 1},
-/* SATA_UNIT_ID */ { 0, 4},
-/* QSGMII_UNIT_ID */ { 0, 1},
-/* XAUI_UNIT_ID */ { 1, 1},
-/* RXAUI_UNIT_ID */ { 1, 1}
-};
-#endif
u32 g_dev_id = -1;
@@ -202,11 +188,7 @@
return ctrl_id;
default:
/* Device ID Default for A38x: 6820 , for A39x: 6920 */
- #ifdef CONFIG_ARMADA_38X
default_ctrl_id = MV_6820_DEV_ID;
- #else
- default_ctrl_id = MV_6920_DEV_ID;
- #endif
printf("%s: Error retrieving device ID (%x), using default ID = %x\n",
__func__, ctrl_id, default_ctrl_id);
return default_ctrl_id;
@@ -261,9 +243,6 @@
{
u32 i, val;
- if (!(IS_ENABLED(CONFIG_ARMADA_38X) || IS_ENABLED(CONFIG_ARMADA_39X)))
- return;
-
/* Activate pipe0 for read/write transaction, and set XBAR client number #1 */
val = 0x1 << DFX_PIPE_SELECT_PIPE0_ACTIVE_OFFS |
0x1 << DFX_PIPE_SELECT_XBAR_CLIENT_SEL_OFFS;
@@ -278,9 +257,6 @@
{
u32 sar_freq;
- if (!(IS_ENABLED(CONFIG_ARMADA_38X) || IS_ENABLED(CONFIG_ARMADA_39X)))
- return;
-
reg_write(AVS_DEBUG_CNTR_REG, AVS_DEBUG_CNTR_DEFAULT_VALUE);
reg_write(AVS_DEBUG_CNTR_REG, AVS_DEBUG_CNTR_DEFAULT_VALUE);
diff --git a/arch/arm/mach-mvebu/serdes/a38x/sys_env_lib.h b/arch/arm/mach-mvebu/serdes/a38x/sys_env_lib.h
index 17cd811..118bf56 100644
--- a/arch/arm/mach-mvebu/serdes/a38x/sys_env_lib.h
+++ b/arch/arm/mach-mvebu/serdes/a38x/sys_env_lib.h
@@ -118,12 +118,8 @@
/* TWSI addresses */
/* starting from A38x A0, i2c address of EEPROM is 0x57 */
-#ifdef CONFIG_ARMADA_39X
-#define EEPROM_I2C_ADDR 0x50
-#else
#define EEPROM_I2C_ADDR (sys_env_device_rev_get() == \
MV_88F68XX_Z1_ID ? 0x50 : 0x57)
-#endif
#define RD_GET_MODE_ADDR 0x4c
#define DB_GET_MODE_SLM1363_ADDR 0x25
#define DB_GET_MODE_SLM1364_ADDR 0x24
@@ -216,7 +212,6 @@
#define A39X_MV_MARVELL_BOARD_NUM (A39X_MV_MAX_MARVELL_BOARD_ID - \
A39X_MARVELL_BOARD_ID_BASE)
-#ifdef CONFIG_ARMADA_38X
#define CUTOMER_BOARD_ID_BASE A38X_CUSTOMER_BOARD_ID_BASE
#define CUSTOMER_BOARD_ID0 A38X_CUSTOMER_BOARD_ID0
#define CUSTOMER_BOARD_ID1 A38X_CUSTOMER_BOARD_ID1
@@ -227,18 +222,6 @@
#define MV_MARVELL_BOARD_NUM A38X_MV_MARVELL_BOARD_NUM
#define MV_DEFAULT_BOARD_ID DB_68XX_ID
#define MV_DEFAULT_DEVICE_ID MV_6811
-#elif defined(CONFIG_ARMADA_39X)
-#define CUTOMER_BOARD_ID_BASE A39X_CUSTOMER_BOARD_ID_BASE
-#define CUSTOMER_BOARD_ID0 A39X_CUSTOMER_BOARD_ID0
-#define CUSTOMER_BOARD_ID1 A39X_CUSTOMER_BOARD_ID1
-#define MV_MAX_CUSTOMER_BOARD_ID A39X_MV_MAX_CUSTOMER_BOARD_ID
-#define MV_CUSTOMER_BOARD_NUM A39X_MV_CUSTOMER_BOARD_NUM
-#define MARVELL_BOARD_ID_BASE A39X_MARVELL_BOARD_ID_BASE
-#define MV_MAX_MARVELL_BOARD_ID A39X_MV_MAX_MARVELL_BOARD_ID
-#define MV_MARVELL_BOARD_NUM A39X_MV_MARVELL_BOARD_NUM
-#define MV_DEFAULT_BOARD_ID A39X_DB_69XX_ID
-#define MV_DEFAULT_DEVICE_ID MV_6920
-#endif
#define MV_INVALID_BOARD_ID 0xffffffff
@@ -295,11 +278,7 @@
#define MV_6920_INDEX 0
#define MV_6928_INDEX 1
-#ifdef CONFIG_ARMADA_38X
#define MAX_DEV_ID_NUM 4
-#else
-#define MAX_DEV_ID_NUM 2
-#endif
#define MV_6820_INDEX 0
#define MV_6810_INDEX 1
@@ -340,21 +319,13 @@
* If suspend to RAM is not supported set '-1'
*/
#ifdef CONFIG_CUSTOMER_BOARD_SUPPORT
-#ifdef CONFIG_ARMADA_38X
#define MV_BOARD_WAKEUP_GPIO_INFO { \
{A38X_CUSTOMER_BOARD_ID0, -1 }, \
{A38X_CUSTOMER_BOARD_ID0, -1 }, \
};
-#else
-#define MV_BOARD_WAKEUP_GPIO_INFO { \
- {A39X_CUSTOMER_BOARD_ID0, -1 }, \
- {A39X_CUSTOMER_BOARD_ID0, -1 }, \
-};
-#endif /* CONFIG_ARMADA_38X */
#else
-#ifdef CONFIG_ARMADA_38X
#define MV_BOARD_WAKEUP_GPIO_INFO { \
{RD_NAS_68XX_ID, -2 }, \
{DB_68XX_ID, -1 }, \
@@ -364,12 +335,6 @@
{DB_BP_6821_ID, -2 }, \
{DB_AMC_6820_ID, -2 }, \
};
-#else
-#define MV_BOARD_WAKEUP_GPIO_INFO { \
- {A39X_RD_69XX_ID, -1 }, \
- {A39X_DB_69XX_ID, -1 }, \
-};
-#endif /* CONFIG_ARMADA_38X */
#endif /* CONFIG_CUSTOMER_BOARD_SUPPORT */
u32 mv_board_tclk_get(void);
diff --git a/arch/arm/mach-omap2/omap3/board.c b/arch/arm/mach-omap2/omap3/board.c
index 4da8df4..029bd54 100644
--- a/arch/arm/mach-omap2/omap3/board.c
+++ b/arch/arm/mach-omap2/omap3/board.c
@@ -179,6 +179,8 @@
hw_data_init();
}
+#if !defined(CONFIG_SKIP_LOWLEVEL_INIT) && \
+ !defined(CONFIG_SKIP_LOWLEVEL_INIT_ONLY)
/******************************************************************************
* Routine: s_init
* Description: Does early system init of muxing and clocks.
@@ -207,6 +209,7 @@
ehci_clocks_enable();
#endif
}
+#endif
#ifdef CONFIG_SPL_BUILD
void board_init_f(ulong dummy)
diff --git a/arch/arm/mach-omap2/omap3/lowlevel_init.S b/arch/arm/mach-omap2/omap3/lowlevel_init.S
index 2a05b5e..4fa8941 100644
--- a/arch/arm/mach-omap2/omap3/lowlevel_init.S
+++ b/arch/arm/mach-omap2/omap3/lowlevel_init.S
@@ -45,7 +45,7 @@
ENTRY(cpy_clk_code)
/* Copy DPLL code into SRAM */
adr r0, go_to_speed /* copy from start of go_to_speed... */
- adr r2, lowlevel_init /* ... up to start of low_level_init */
+ adr r2, go_to_speed_end /* ... up to start of go_to_speed_end */
next2:
ldmia r0!, {r3 - r10} /* copy from source address [r0] */
stmia r1!, {r3 - r10} /* copy to target address [r1] */
@@ -167,8 +167,11 @@
pll_div_val5:
.word CLSEL1_EMU_VAL
+go_to_speed_end:
#endif
+#if !defined(CONFIG_SKIP_LOWLEVEL_INIT) && \
+ !defined(CONFIG_SKIP_LOWLEVEL_INIT_ONLY)
ENTRY(lowlevel_init)
ldr sp, SRAM_STACK
str ip, [sp] /* stash ip register */
@@ -187,6 +190,7 @@
b s_init
ENDPROC(lowlevel_init)
+#endif
/* the literal pools origin */
.ltorg
diff --git a/arch/arm/mach-socfpga/Kconfig b/arch/arm/mach-socfpga/Kconfig
index 4d4ff16..0c35406 100644
--- a/arch/arm/mach-socfpga/Kconfig
+++ b/arch/arm/mach-socfpga/Kconfig
@@ -6,6 +6,21 @@
config NR_DRAM_BANKS
default 1
+config SOCFPGA_SECURE_VAB_AUTH
+ bool "Enable boot image authentication with Secure Device Manager"
+ depends on TARGET_SOCFPGA_AGILEX
+ select FIT_IMAGE_POST_PROCESS
+ select SHA384
+ select SHA512_ALGO
+ select SPL_FIT_IMAGE_POST_PROCESS
+ help
+ All images loaded from FIT will be authenticated by Secure Device
+ Manager.
+
+config SOCFPGA_SECURE_VAB_AUTH_ALLOW_NON_FIT_IMAGE
+ bool "Allow non-FIT VAB signed images"
+ depends on SOCFPGA_SECURE_VAB_AUTH
+
config SPL_SIZE_LIMIT
default 0x10000 if TARGET_SOCFPGA_GEN5
@@ -38,6 +53,7 @@
select FPGA_INTEL_SDM_MAILBOX
select NCORE_CACHE
select SPL_CLK if SPL
+ select TARGET_SOCFPGA_SOC64
config TARGET_SOCFPGA_ARRIA5
bool
@@ -75,12 +91,16 @@
imply SPL_SYS_MALLOC_SIMPLE
imply SPL_USE_TINY_PRINTF
+config TARGET_SOCFPGA_SOC64
+ bool
+
config TARGET_SOCFPGA_STRATIX10
bool
select ARMV8_MULTIENTRY
select ARMV8_SET_SMPEN
select BINMAN if SPL_ATF
select FPGA_INTEL_SDM_MAILBOX
+ select TARGET_SOCFPGA_SOC64
choice
prompt "Altera SOCFPGA board select"
diff --git a/arch/arm/mach-socfpga/Makefile b/arch/arm/mach-socfpga/Makefile
index 82b681d..9e63296 100644
--- a/arch/arm/mach-socfpga/Makefile
+++ b/arch/arm/mach-socfpga/Makefile
@@ -4,6 +4,7 @@
# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
#
# Copyright (C) 2012-2017 Altera Corporation <www.altera.com>
+# Copyright (C) 2017-2020 Intel Corporation <www.intel.com>
obj-y += board.o
obj-y += clock_manager.o
@@ -47,8 +48,10 @@
obj-y += misc_s10.o
obj-y += mmu-arm64_s10.o
obj-y += reset_manager_s10.o
+obj-$(CONFIG_SOCFPGA_SECURE_VAB_AUTH) += secure_vab.o
obj-y += system_manager_s10.o
obj-y += timer_s10.o
+obj-$(CONFIG_SOCFPGA_SECURE_VAB_AUTH) += vab.o
obj-y += wrap_pinmux_config_s10.o
obj-y += wrap_pll_config_s10.o
endif
diff --git a/arch/arm/mach-socfpga/board.c b/arch/arm/mach-socfpga/board.c
index 2a6af9d..81aa07c 100644
--- a/arch/arm/mach-socfpga/board.c
+++ b/arch/arm/mach-socfpga/board.c
@@ -6,14 +6,17 @@
*/
#include <common.h>
-#include <errno.h>
-#include <fdtdec.h>
-#include <init.h>
-#include <asm/arch/reset_manager.h>
#include <asm/arch/clock_manager.h>
#include <asm/arch/misc.h>
+#include <asm/arch/reset_manager.h>
+#include <asm/arch/secure_vab.h>
#include <asm/global_data.h>
#include <asm/io.h>
+#include <errno.h>
+#include <fdtdec.h>
+#include <hang.h>
+#include <image.h>
+#include <init.h>
#include <log.h>
#include <usb.h>
#include <usb/dwc2_udc.h>
@@ -98,3 +101,37 @@
return 0;
}
#endif
+
+#if IS_ENABLED(CONFIG_FIT_IMAGE_POST_PROCESS)
+void board_fit_image_post_process(void **p_image, size_t *p_size)
+{
+ if (IS_ENABLED(CONFIG_SOCFPGA_SECURE_VAB_AUTH)) {
+ if (socfpga_vendor_authentication(p_image, p_size))
+ hang();
+ }
+}
+#endif
+
+#if !IS_ENABLED(CONFIG_SPL_BUILD) && IS_ENABLED(CONFIG_FIT)
+void board_prep_linux(bootm_headers_t *images)
+{
+ if (!IS_ENABLED(CONFIG_SECURE_VAB_AUTH_ALLOW_NON_FIT_IMAGE)) {
+ /*
+ * Ensure the OS is always booted from FIT and with
+ * VAB signed certificate
+ */
+ if (!images->fit_uname_cfg) {
+ printf("Please use FIT with VAB signed images!\n");
+ hang();
+ }
+
+ env_set_hex("fdt_addr", (ulong)images->ft_addr);
+ debug("images->ft_addr = 0x%08lx\n", (ulong)images->ft_addr);
+ }
+
+ if (IS_ENABLED(CONFIG_CADENCE_QSPI)) {
+ if (env_get("linux_qspi_enable"))
+ run_command(env_get("linux_qspi_enable"), 0);
+ }
+}
+#endif
diff --git a/arch/arm/mach-socfpga/include/mach/mailbox_s10.h b/arch/arm/mach-socfpga/include/mach/mailbox_s10.h
index 4d78311..fbaf115 100644
--- a/arch/arm/mach-socfpga/include/mach/mailbox_s10.h
+++ b/arch/arm/mach-socfpga/include/mach/mailbox_s10.h
@@ -118,6 +118,7 @@
#define MBOX_RECONFIG_MSEL 7
#define MBOX_RECONFIG_DATA 8
#define MBOX_RECONFIG_STATUS 9
+#define MBOX_VAB_SRC_CERT 11
#define MBOX_QSPI_OPEN 50
#define MBOX_QSPI_CLOSE 51
#define MBOX_QSPI_DIRECT 59
diff --git a/arch/arm/mach-socfpga/include/mach/reset_manager.h b/arch/arm/mach-socfpga/include/mach/reset_manager.h
index 7844ad1..8c25325 100644
--- a/arch/arm/mach-socfpga/include/mach/reset_manager.h
+++ b/arch/arm/mach-socfpga/include/mach/reset_manager.h
@@ -43,8 +43,7 @@
#include <asm/arch/reset_manager_gen5.h>
#elif defined(CONFIG_TARGET_SOCFPGA_ARRIA10)
#include <asm/arch/reset_manager_arria10.h>
-#elif defined(CONFIG_TARGET_SOCFPGA_STRATIX10) || \
- defined(CONFIG_TARGET_SOCFPGA_AGILEX)
+#elif defined(CONFIG_TARGET_SOCFPGA_SOC64)
#include <asm/arch/reset_manager_soc64.h>
#endif
diff --git a/arch/arm/mach-socfpga/include/mach/secure_vab.h b/arch/arm/mach-socfpga/include/mach/secure_vab.h
new file mode 100644
index 0000000..4258858
--- /dev/null
+++ b/arch/arm/mach-socfpga/include/mach/secure_vab.h
@@ -0,0 +1,63 @@
+/* SPDX-License-Identifier: GPL-2.0
+ *
+ * Copyright (C) 2020 Intel Corporation <www.intel.com>
+ *
+ */
+
+#ifndef _SECURE_VAB_H_
+#define _SECURE_VAB_H_
+
+#include <linux/sizes.h>
+#include <linux/stddef.h>
+#include <u-boot/sha512.h>
+
+#define VAB_DATA_SZ 64
+
+#define SDM_CERT_MAGIC_NUM 0x25D04E7F
+#define FCS_HPS_VAB_MAGIC_NUM 0xD0564142
+
+#define MAX_CERT_SIZE (SZ_4K)
+
+/*
+ * struct fcs_hps_vab_certificate_data
+ * @vab_cert_magic_num: VAB Certificate Magic Word (0xD0564142)
+ * @flags: TBD
+ * @fcs_data: Data words being certificate signed.
+ * @cert_sign_keychain: Certificate Signing Keychain
+ */
+struct fcs_hps_vab_certificate_data {
+ u32 vab_cert_magic_num; /* offset 0x10 */
+ u32 flags;
+ u8 rsvd0_1[8];
+ u8 fcs_sha384[SHA384_SUM_LEN]; /* offset 0x20 */
+};
+
+/*
+ * struct fcs_hps_vab_certificate_header
+ * @cert_magic_num: Certificate Magic Word (0x25D04E7F)
+ * @cert_data_sz: size of this certificate header (0x80)
+ * Includes magic number all the way to the certificate
+ * signing keychain (excludes cert. signing keychain)
+ * @cert_ver: Certificate Version
+ * @cert_type: Certificate Type
+ * @data: VAB HPS Image Certificate data
+ */
+struct fcs_hps_vab_certificate_header {
+ u32 cert_magic_num; /* offset 0 */
+ u32 cert_data_sz;
+ u32 cert_ver;
+ u32 cert_type;
+ struct fcs_hps_vab_certificate_data d; /* offset 0x10 */
+ /* keychain starts at offset 0x50 */
+};
+
+#define VAB_CERT_HEADER_SIZE sizeof(struct fcs_hps_vab_certificate_header)
+#define VAB_CERT_MAGIC_OFFSET offsetof \
+ (struct fcs_hps_vab_certificate_header, d)
+#define VAB_CERT_FIT_SHA384_OFFSET offsetof \
+ (struct fcs_hps_vab_certificate_data, \
+ fcs_sha384[0])
+
+int socfpga_vendor_authentication(void **p_image, size_t *p_size);
+
+#endif /* _SECURE_VAB_H_ */
diff --git a/arch/arm/mach-socfpga/include/mach/system_manager.h b/arch/arm/mach-socfpga/include/mach/system_manager.h
index f816954..5603eaa 100644
--- a/arch/arm/mach-socfpga/include/mach/system_manager.h
+++ b/arch/arm/mach-socfpga/include/mach/system_manager.h
@@ -8,8 +8,7 @@
phys_addr_t socfpga_get_sysmgr_addr(void);
-#if defined(CONFIG_TARGET_SOCFPGA_STRATIX10) || \
- defined(CONFIG_TARGET_SOCFPGA_AGILEX)
+#if defined(CONFIG_TARGET_SOCFPGA_SOC64)
#include <asm/arch/system_manager_soc64.h>
#else
#define SYSMGR_ROMCODEGRP_CTRL_WARMRSTCFGPINMUX BIT(0)
diff --git a/arch/arm/mach-socfpga/secure_vab.c b/arch/arm/mach-socfpga/secure_vab.c
new file mode 100644
index 0000000..e2db588
--- /dev/null
+++ b/arch/arm/mach-socfpga/secure_vab.c
@@ -0,0 +1,186 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (C) 2020 Intel Corporation <www.intel.com>
+ *
+ */
+
+#include <asm/arch/mailbox_s10.h>
+#include <asm/arch/secure_vab.h>
+#include <asm/arch/smc_api.h>
+#include <asm/unaligned.h>
+#include <common.h>
+#include <exports.h>
+#include <linux/errno.h>
+#include <linux/intel-smc.h>
+#include <log.h>
+
+#define CHUNKSZ_PER_WD_RESET (256 * SZ_1K)
+
+/*
+ * Read the length of the VAB certificate from the end of image
+ * and calculate the actual image size (excluding the VAB certificate).
+ */
+static size_t get_img_size(u8 *img_buf, size_t img_buf_sz)
+{
+ u8 *img_buf_end = img_buf + img_buf_sz;
+ u32 cert_sz = get_unaligned_le32(img_buf_end - sizeof(u32));
+ u8 *p = img_buf_end - cert_sz - sizeof(u32);
+
+ /* Ensure p is pointing within the img_buf */
+ if (p < img_buf || p > (img_buf_end - VAB_CERT_HEADER_SIZE))
+ return 0;
+
+ if (get_unaligned_le32(p) == SDM_CERT_MAGIC_NUM)
+ return (size_t)(p - img_buf);
+
+ return 0;
+}
+
+/*
+ * Vendor Authorized Boot (VAB) is a security feature for authenticating
+ * the images such as U-Boot, ARM trusted Firmware, Linux kernel,
+ * device tree blob and etc loaded from FIT. User can also trigger
+ * the VAB authentication from U-Boot command.
+ *
+ * This function extracts the VAB certificate and signature block
+ * appended at the end of the image, then send to Secure Device Manager
+ * (SDM) for authentication. This function will validate the SHA384
+ * of the image against the SHA384 hash stored in the VAB certificate
+ * before sending the VAB certificate to SDM for authentication.
+ *
+ * RETURN
+ * 0 if authentication success or
+ * if authentication is not required and bypassed on a non-secure device
+ * negative error code if authentication fail
+ */
+int socfpga_vendor_authentication(void **p_image, size_t *p_size)
+{
+ int retry_count = 20;
+ u8 hash384[SHA384_SUM_LEN];
+ u64 img_addr, mbox_data_addr;
+ size_t img_sz, mbox_data_sz;
+ u8 *cert_hash_ptr, *mbox_relocate_data_addr;
+ u32 resp = 0, resp_len = 1;
+ int ret;
+
+ img_addr = (uintptr_t)*p_image;
+
+ debug("Authenticating image at address 0x%016llx (%ld bytes)\n",
+ img_addr, *p_size);
+
+ img_sz = get_img_size((u8 *)img_addr, *p_size);
+ debug("img_sz = %ld\n", img_sz);
+
+ if (!img_sz) {
+ puts("VAB certificate not found in image!\n");
+ return -ENOKEY;
+ }
+
+ if (!IS_ALIGNED(img_sz, sizeof(u32))) {
+ printf("Image size (%ld bytes) not aliged to 4 bytes!\n",
+ img_sz);
+ return -EBFONT;
+ }
+
+ /* Generate HASH384 from the image */
+ sha384_csum_wd((u8 *)img_addr, img_sz, hash384, CHUNKSZ_PER_WD_RESET);
+
+ cert_hash_ptr = (u8 *)(img_addr + img_sz + VAB_CERT_MAGIC_OFFSET +
+ VAB_CERT_FIT_SHA384_OFFSET);
+
+ /*
+ * Compare the SHA384 found in certificate against the SHA384
+ * calculated from image
+ */
+ if (memcmp(hash384, cert_hash_ptr, SHA384_SUM_LEN)) {
+ puts("SHA384 not match!\n");
+ return -EKEYREJECTED;
+ }
+
+ mbox_data_addr = img_addr + img_sz - sizeof(u32);
+ /* Size in word (32bits) */
+ mbox_data_sz = (ALIGN(*p_size - img_sz, sizeof(u32))) >> 2;
+
+ debug("mbox_data_addr = 0x%016llx\n", mbox_data_addr);
+ debug("mbox_data_sz = %ld words\n", mbox_data_sz);
+
+ /*
+ * Relocate certificate to first memory block before trigger SMC call
+ * to send mailbox command because ATF only able to access first
+ * memory block.
+ */
+ mbox_relocate_data_addr = (u8 *)malloc(mbox_data_sz * sizeof(u32));
+ if (!mbox_relocate_data_addr) {
+ puts("Out of memory for VAB certificate relocation!\n");
+ return -ENOMEM;
+ }
+
+ memcpy(mbox_relocate_data_addr, (u8 *)mbox_data_addr, mbox_data_sz * sizeof(u32));
+ *(u32 *)mbox_relocate_data_addr = 0;
+
+ debug("mbox_relocate_data_addr = 0x%p\n", mbox_relocate_data_addr);
+
+ do {
+ if (!IS_ENABLED(CONFIG_SPL_BUILD) && IS_ENABLED(CONFIG_SPL_ATF)) {
+ /* Invoke SMC call to ATF to send the VAB certificate to SDM */
+ ret = smc_send_mailbox(MBOX_VAB_SRC_CERT, mbox_data_sz,
+ (u32 *)mbox_relocate_data_addr, 0, &resp_len,
+ &resp);
+ } else {
+ /* Send the VAB certficate to SDM for authentication */
+ ret = mbox_send_cmd(MBOX_ID_UBOOT, MBOX_VAB_SRC_CERT,
+ MBOX_CMD_DIRECT, mbox_data_sz,
+ (u32 *)mbox_relocate_data_addr, 0, &resp_len,
+ &resp);
+ }
+ /* If SDM is not available, just delay 50ms and retry again */
+ if (ret == MBOX_RESP_DEVICE_BUSY)
+ mdelay(50);
+ else
+ break;
+ } while (--retry_count);
+
+ /* Free the relocate certificate memory space */
+ free(mbox_relocate_data_addr);
+
+ /* Exclude the size of the VAB certificate from image size */
+ *p_size = img_sz;
+
+ debug("ret = 0x%08x, resp = 0x%08x, resp_len = %d\n", ret, resp,
+ resp_len);
+
+ if (ret) {
+ /*
+ * Unsupported mailbox command or device not in the
+ * owned/secure state
+ */
+ if (ret == MBOX_RESP_NOT_ALLOWED_UNDER_SECURITY_SETTINGS) {
+ /* SDM bypass authentication */
+ printf("%s 0x%016llx (%ld bytes)\n",
+ "Image Authentication bypassed at address",
+ img_addr, img_sz);
+ return 0;
+ }
+ puts("VAB certificate authentication failed in SDM");
+ if (ret == MBOX_RESP_DEVICE_BUSY) {
+ puts(" (SDM busy timeout)\n");
+ return -ETIMEDOUT;
+ } else if (ret == MBOX_RESP_UNKNOWN) {
+ puts(" (Not supported)\n");
+ return -ESRCH;
+ }
+ puts("\n");
+ return -EKEYREJECTED;
+ } else {
+ /* If Certificate Process Status has error */
+ if (resp) {
+ puts("VAB certificate process failed\n");
+ return -ENOEXEC;
+ }
+ }
+
+ printf("%s 0x%016llx (%ld bytes)\n",
+ "Image Authentication passed at address", img_addr, img_sz);
+
+ return 0;
+}
diff --git a/arch/arm/mach-socfpga/vab.c b/arch/arm/mach-socfpga/vab.c
new file mode 100644
index 0000000..85b3f30
--- /dev/null
+++ b/arch/arm/mach-socfpga/vab.c
@@ -0,0 +1,34 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (C) 2020 Intel Corporation <www.intel.com>
+ *
+ */
+
+#include <asm/arch/secure_vab.h>
+#include <command.h>
+#include <common.h>
+#include <linux/ctype.h>
+
+static int do_vab(struct cmd_tbl *cmdtp, int flag, int argc,
+ char *const argv[])
+{
+ unsigned long addr, len;
+
+ if (argc < 3)
+ return CMD_RET_USAGE;
+
+ addr = simple_strtoul(argv[1], NULL, 16);
+ len = simple_strtoul(argv[2], NULL, 16);
+
+ if (socfpga_vendor_authentication((void *)&addr, (size_t *)&len) != 0)
+ return CMD_RET_FAILURE;
+
+ return 0;
+}
+
+U_BOOT_CMD(
+ vab, 3, 2, do_vab,
+ "perform vendor authorization",
+ "addr len - authorize 'len' bytes starting at\n"
+ " 'addr' via vendor public key"
+);
diff --git a/arch/arm/mach-stm32mp/Kconfig b/arch/arm/mach-stm32mp/Kconfig
index f538d7c..079d66a 100644
--- a/arch/arm/mach-stm32mp/Kconfig
+++ b/arch/arm/mach-stm32mp/Kconfig
@@ -121,23 +121,6 @@
help
Say y to enable STM32 Extended TrustZone Protection
-config CMD_STM32PROG
- bool "command stm32prog for STM32CudeProgrammer"
- select DFU
- select DFU_RAM
- select DFU_VIRT
- select PARTITION_TYPE_GUID
- imply CMD_GPT if MMC
- imply CMD_MTD if MTD
- imply DFU_MMC if MMC
- imply DFU_MTD if MTD
- help
- activate a specific command stm32prog for STM32MP soc family
- witch update the device with the tools STM32CubeProgrammer,
- using UART with STM32 protocol or USB with DFU protocol
- NB: access to not volatile memory (NOR/NAND/SD/eMMC) is based
- on U-Boot DFU framework
-
config CMD_STM32KEY
bool "command stm32key to fuse public key hash"
default y
@@ -177,6 +160,7 @@
default 64000000
endif
+source "arch/arm/mach-stm32mp/cmd_stm32prog/Kconfig"
source "board/st/stm32mp1/Kconfig"
source "board/dhelectronics/dh_stm32mp1/Kconfig"
diff --git a/arch/arm/mach-stm32mp/Makefile b/arch/arm/mach-stm32mp/Makefile
index c8aa24d..aa39867 100644
--- a/arch/arm/mach-stm32mp/Makefile
+++ b/arch/arm/mach-stm32mp/Makefile
@@ -11,7 +11,7 @@
ifdef CONFIG_SPL_BUILD
obj-y += spl.o
else
-obj-$(CONFIG_CMD_STM32PROG) += cmd_stm32prog/
+obj-y += cmd_stm32prog/
obj-$(CONFIG_CMD_STM32KEY) += cmd_stm32key.o
obj-$(CONFIG_ARMV7_PSCI) += psci.o
obj-$(CONFIG_TFABOOT) += boot_params.o
diff --git a/arch/arm/mach-stm32mp/bsec.c b/arch/arm/mach-stm32mp/bsec.c
index 88c7aec..fe39bd8 100644
--- a/arch/arm/mach-stm32mp/bsec.c
+++ b/arch/arm/mach-stm32mp/bsec.c
@@ -6,6 +6,7 @@
#define LOG_CATEGORY UCLASS_MISC
#include <common.h>
+#include <clk.h>
#include <dm.h>
#include <log.h>
#include <misc.h>
@@ -490,6 +491,15 @@
{
int otp;
struct stm32mp_bsec_plat *plat;
+ struct clk_bulk clk_bulk;
+ int ret;
+
+ ret = clk_get_bulk(dev, &clk_bulk);
+ if (!ret) {
+ ret = clk_enable_bulk(&clk_bulk);
+ if (ret)
+ return ret;
+ }
/*
* update unlocked shadow for OTP cleared by the rom code
diff --git a/arch/arm/mach-stm32mp/cmd_stm32prog/Kconfig b/arch/arm/mach-stm32mp/cmd_stm32prog/Kconfig
new file mode 100644
index 0000000..f4c0d18
--- /dev/null
+++ b/arch/arm/mach-stm32mp/cmd_stm32prog/Kconfig
@@ -0,0 +1,34 @@
+
+config CMD_STM32PROG
+ bool "command stm32prog for STM32CudeProgrammer"
+ select DFU
+ select DFU_RAM
+ select DFU_VIRT
+ select PARTITION_TYPE_GUID
+ imply CMD_GPT if MMC
+ imply CMD_MTD if MTD
+ imply DFU_MMC if MMC
+ imply DFU_MTD if MTD
+ help
+ activate a specific command stm32prog for STM32MP soc family
+ witch update the device with the tools STM32CubeProgrammer
+ NB: access to not volatile memory (NOR/NAND/SD/eMMC) is based
+ on U-Boot DFU framework
+
+config CMD_STM32PROG_USB
+ bool "support stm32prog over USB"
+ depends on CMD_STM32PROG
+ default y
+ help
+ activate the command "stm32prog usb" for STM32MP soc family
+ witch update the device with the tools STM32CubeProgrammer,
+ using USB with DFU protocol
+
+config CMD_STM32PROG_SERIAL
+ bool "support stm32prog over UART"
+ depends on CMD_STM32PROG
+ default y
+ help
+ activate the command "stm32prog serial" for STM32MP soc family
+ with the tools STM32CubeProgrammer using U-Boot serial device
+ and UART protocol.
\ No newline at end of file
diff --git a/arch/arm/mach-stm32mp/cmd_stm32prog/Makefile b/arch/arm/mach-stm32mp/cmd_stm32prog/Makefile
index 548a378..b57e1bf 100644
--- a/arch/arm/mach-stm32mp/cmd_stm32prog/Makefile
+++ b/arch/arm/mach-stm32mp/cmd_stm32prog/Makefile
@@ -3,7 +3,7 @@
# Copyright (C) 2020, STMicroelectronics - All Rights Reserved
#
-obj-y += cmd_stm32prog.o
-obj-y += stm32prog.o
-obj-y += stm32prog_serial.o
-obj-y += stm32prog_usb.o
+obj-$(CONFIG_CMD_STM32PROG) += cmd_stm32prog.o
+obj-$(CONFIG_CMD_STM32PROG) += stm32prog.o
+obj-$(CONFIG_CMD_STM32PROG_SERIAL) += stm32prog_serial.o
+obj-$(CONFIG_CMD_STM32PROG_USB) += stm32prog_usb.o
diff --git a/arch/arm/mach-stm32mp/cmd_stm32prog/cmd_stm32prog.c b/arch/arm/mach-stm32mp/cmd_stm32prog/cmd_stm32prog.c
index 34a6be6..a7e2861 100644
--- a/arch/arm/mach-stm32mp/cmd_stm32prog/cmd_stm32prog.c
+++ b/arch/arm/mach-stm32mp/cmd_stm32prog/cmd_stm32prog.c
@@ -50,9 +50,9 @@
if (argc < 3 || argc > 5)
return CMD_RET_USAGE;
- if (!strcmp(argv[1], "usb"))
+ if (IS_ENABLED(CONFIG_CMD_STM32PROG_USB) && !strcmp(argv[1], "usb"))
link = LINK_USB;
- else if (!strcmp(argv[1], "serial"))
+ else if (IS_ENABLED(CONFIG_CMD_STM32PROG_SERIAL) && !strcmp(argv[1], "serial"))
link = LINK_SERIAL;
if (link == LINK_UNDEFINED) {
diff --git a/arch/arm/mach-stm32mp/cmd_stm32prog/stm32prog.h b/arch/arm/mach-stm32mp/cmd_stm32prog/stm32prog.h
index be482c3..18af99c 100644
--- a/arch/arm/mach-stm32mp/cmd_stm32prog/stm32prog.h
+++ b/arch/arm/mach-stm32mp/cmd_stm32prog/stm32prog.h
@@ -177,9 +177,30 @@
/* Main function */
int stm32prog_init(struct stm32prog_data *data, ulong addr, ulong size);
+void stm32prog_clean(struct stm32prog_data *data);
+
+#ifdef CONFIG_CMD_STM32PROG_SERIAL
int stm32prog_serial_init(struct stm32prog_data *data, int link_dev);
bool stm32prog_serial_loop(struct stm32prog_data *data);
+#else
+static inline int stm32prog_serial_init(struct stm32prog_data *data, int link_dev)
+{
+ return -ENOSYS;
+}
+
+static inline bool stm32prog_serial_loop(struct stm32prog_data *data)
+{
+ return false;
+}
+#endif
+
+#ifdef CONFIG_CMD_STM32PROG_USB
bool stm32prog_usb_loop(struct stm32prog_data *data, int dev);
-void stm32prog_clean(struct stm32prog_data *data);
+#else
+static inline bool stm32prog_usb_loop(struct stm32prog_data *data, int dev)
+{
+ return false;
+}
+#endif
#endif
diff --git a/arch/arm/mach-stm32mp/cmd_stm32prog/stm32prog_serial.c b/arch/arm/mach-stm32mp/cmd_stm32prog/stm32prog_serial.c
index 373ca20..a51e5e3 100644
--- a/arch/arm/mach-stm32mp/cmd_stm32prog/stm32prog_serial.c
+++ b/arch/arm/mach-stm32mp/cmd_stm32prog/stm32prog_serial.c
@@ -187,35 +187,18 @@
int stm32prog_serial_init(struct stm32prog_data *data, int link_dev)
{
struct udevice *dev = NULL;
- int node;
- char alias[10];
- const char *path;
struct dm_serial_ops *ops;
/* no parity, 8 bits, 1 stop */
u32 serial_config = SERIAL_DEFAULT_CONFIG;
down_serial_dev = NULL;
- sprintf(alias, "serial%d", link_dev);
- path = fdt_get_alias(gd->fdt_blob, alias);
- if (!path) {
- log_err("%s alias not found", alias);
+ if (uclass_get_device_by_seq(UCLASS_SERIAL, link_dev, &dev)) {
+ log_err("serial %d device not found\n", link_dev);
return -ENODEV;
}
- node = fdt_path_offset(gd->fdt_blob, path);
- if (!uclass_get_device_by_of_offset(UCLASS_SERIAL, node,
- &dev)) {
- down_serial_dev = dev;
- } else if (node > 0 &&
- !lists_bind_fdt(gd->dm_root, offset_to_ofnode(node),
- &dev, false)) {
- if (!device_probe(dev))
- down_serial_dev = dev;
- }
- if (!down_serial_dev) {
- log_err("%s = %s device not found", alias, path);
- return -ENODEV;
- }
+
+ down_serial_dev = dev;
/* force silent console on uart only when used */
if (gd->cur_serial_dev == down_serial_dev)
@@ -226,11 +209,11 @@
ops = serial_get_ops(down_serial_dev);
if (!ops) {
- log_err("%s = %s missing ops", alias, path);
+ log_err("serial %d = %s missing ops\n", link_dev, dev->name);
return -ENODEV;
}
if (!ops->setconfig) {
- log_err("%s = %s missing setconfig", alias, path);
+ log_err("serial %d = %s missing setconfig\n", link_dev, dev->name);
return -ENODEV;
}
diff --git a/arch/arm/mach-stm32mp/cpu.c b/arch/arm/mach-stm32mp/cpu.c
index 3faa4ec..bc2db53 100644
--- a/arch/arm/mach-stm32mp/cpu.c
+++ b/arch/arm/mach-stm32mp/cpu.c
@@ -223,8 +223,10 @@
if (CONFIG_IS_ENABLED(SYS_DCACHE_OFF))
return;
- gd->arch.tlb_size = PGTABLE_SIZE;
- gd->arch.tlb_addr = (unsigned long)&early_tlb;
+ if (!(CONFIG_IS_ENABLED(SYS_ICACHE_OFF) && CONFIG_IS_ENABLED(SYS_DCACHE_OFF))) {
+ gd->arch.tlb_size = PGTABLE_SIZE;
+ gd->arch.tlb_addr = (unsigned long)&early_tlb;
+ }
dcache_enable();
@@ -265,7 +267,8 @@
boot_mode = get_bootmode();
- if ((boot_mode & TAMP_BOOT_DEVICE_MASK) == BOOT_SERIAL_UART)
+ if (IS_ENABLED(CONFIG_CMD_STM32PROG_SERIAL) &&
+ (boot_mode & TAMP_BOOT_DEVICE_MASK) == BOOT_SERIAL_UART)
gd->flags |= GD_FLG_SILENT | GD_FLG_DISABLE_CONSOLE;
#if defined(CONFIG_DEBUG_UART) && \
!defined(CONFIG_TFABOOT) && \
@@ -465,7 +468,6 @@
unsigned int instance = (boot_mode & TAMP_BOOT_INSTANCE_MASK) - 1;
u32 forced_mode = (boot_ctx & TAMP_BOOT_FORCED_MASK);
struct udevice *dev;
- int alias;
log_debug("%s: boot_ctx=0x%x => boot_mode=%x, instance=%d forced=%x\n",
__func__, boot_ctx, boot_mode, instance, forced_mode);
@@ -473,19 +475,23 @@
case BOOT_SERIAL_UART:
if (instance > ARRAY_SIZE(serial_addr))
break;
- /* serial : search associated alias in devicetree */
+ /* serial : search associated node in devicetree */
sprintf(cmd, "serial@%x", serial_addr[instance]);
- if (uclass_get_device_by_name(UCLASS_SERIAL, cmd, &dev))
+ if (uclass_get_device_by_name(UCLASS_SERIAL, cmd, &dev)) {
+ /* restore console on error */
+ if (IS_ENABLED(CONFIG_CMD_STM32PROG_SERIAL))
+ gd->flags &= ~(GD_FLG_SILENT |
+ GD_FLG_DISABLE_CONSOLE);
+ printf("uart%d = %s not found in device tree!\n",
+ instance, cmd);
break;
- if (fdtdec_get_alias_seq(gd->fdt_blob, "serial",
- dev_of_offset(dev), &alias))
- break;
- sprintf(cmd, "%d", alias);
+ }
+ sprintf(cmd, "%d", dev_seq(dev));
env_set("boot_device", "serial");
env_set("boot_instance", cmd);
/* restore console on uart when not used */
- if (gd->cur_serial_dev != dev) {
+ if (IS_ENABLED(CONFIG_CMD_STM32PROG_SERIAL) && gd->cur_serial_dev != dev) {
gd->flags &= ~(GD_FLG_SILENT |
GD_FLG_DISABLE_CONSOLE);
printf("serial boot with console enabled!\n");
diff --git a/arch/arm/mach-zynqmp/include/mach/hardware.h b/arch/arm/mach-zynqmp/include/mach/hardware.h
index b328837..3d3c48e 100644
--- a/arch/arm/mach-zynqmp/include/mach/hardware.h
+++ b/arch/arm/mach-zynqmp/include/mach/hardware.h
@@ -128,8 +128,8 @@
#define ZYNQMP_CSU_VERSION_EMPTY_SHIFT 20
-#define ZYNQMP_SILICON_VER_MASK 0xF000
-#define ZYNQMP_SILICON_VER_SHIFT 12
+#define ZYNQMP_SILICON_VER_MASK 0xF
+#define ZYNQMP_SILICON_VER_SHIFT 0
struct csu_regs {
u32 reserved0[4];
diff --git a/arch/powerpc/cpu/mpc85xx/Kconfig b/arch/powerpc/cpu/mpc85xx/Kconfig
index 870ab80..124c22f 100644
--- a/arch/powerpc/cpu/mpc85xx/Kconfig
+++ b/arch/powerpc/cpu/mpc85xx/Kconfig
@@ -51,23 +51,22 @@
config TARGET_MPC8541CDS
bool "Support MPC8541CDS"
select ARCH_MPC8541
+ select FSL_VIA
config TARGET_MPC8548CDS
bool "Support MPC8548CDS"
select ARCH_MPC8548
+ select FSL_VIA
config TARGET_MPC8555CDS
bool "Support MPC8555CDS"
select ARCH_MPC8555
+ select FSL_VIA
config TARGET_MPC8568MDS
bool "Support MPC8568MDS"
select ARCH_MPC8568
-config TARGET_MPC8569MDS
- bool "Support MPC8569MDS"
- select ARCH_MPC8569
-
config TARGET_P1010RDB_PA
bool "Support P1010RDB_PA"
select ARCH_P1010
@@ -473,19 +472,6 @@
select SYS_FSL_SEC_BE
select SYS_FSL_SEC_COMPAT_2
-config ARCH_MPC8569
- bool
- select FSL_LAW
- select SYS_FSL_ERRATUM_A004508
- select SYS_FSL_ERRATUM_A005125
- select FSL_PCIE_RESET
- select SYS_FSL_HAS_DDR3
- select SYS_FSL_HAS_SEC
- select SYS_FSL_SEC_BE
- select SYS_FSL_SEC_COMPAT_2
- select FSL_ELBC
- imply CMD_NAND
-
config ARCH_MPC8572
bool
select FSL_LAW
@@ -1102,7 +1088,6 @@
ARCH_MPC8555 || \
ARCH_MPC8560 || \
ARCH_MPC8568 || \
- ARCH_MPC8569 || \
ARCH_MPC8572 || \
ARCH_P1010 || \
ARCH_P1011 || \
@@ -1335,8 +1320,7 @@
ARCH_P2020
default 10 if ARCH_MPC8544 || \
ARCH_MPC8548 || \
- ARCH_MPC8568 || \
- ARCH_MPC8569
+ ARCH_MPC8568
default 8 if ARCH_MPC8540 || \
ARCH_MPC8541 || \
ARCH_MPC8555 || \
@@ -1428,16 +1412,18 @@
Defines divider of platform clock(clock input to
eLBC controller).
+config FSL_VIA
+ bool
+
+source "board/emulation/qemu-ppce500/Kconfig"
source "board/freescale/corenet_ds/Kconfig"
source "board/freescale/mpc8541cds/Kconfig"
source "board/freescale/mpc8548cds/Kconfig"
source "board/freescale/mpc8555cds/Kconfig"
source "board/freescale/mpc8568mds/Kconfig"
-source "board/freescale/mpc8569mds/Kconfig"
source "board/freescale/p1010rdb/Kconfig"
source "board/freescale/p1_p2_rdb_pc/Kconfig"
source "board/freescale/p2041rdb/Kconfig"
-source "board/freescale/qemu-ppce500/Kconfig"
source "board/freescale/t102xrdb/Kconfig"
source "board/freescale/t104xrdb/Kconfig"
source "board/freescale/t208xqds/Kconfig"
diff --git a/arch/powerpc/cpu/mpc85xx/Makefile b/arch/powerpc/cpu/mpc85xx/Makefile
index 019fce6..14e4662 100644
--- a/arch/powerpc/cpu/mpc85xx/Makefile
+++ b/arch/powerpc/cpu/mpc85xx/Makefile
@@ -65,7 +65,6 @@
obj-$(CONFIG_ARCH_MPC8544) += mpc8544_serdes.o
obj-$(CONFIG_ARCH_MPC8548) += mpc8548_serdes.o
obj-$(CONFIG_ARCH_MPC8568) += mpc8568_serdes.o
-obj-$(CONFIG_ARCH_MPC8569) += mpc8569_serdes.o
obj-$(CONFIG_ARCH_MPC8572) += mpc8572_serdes.o
obj-$(CONFIG_ARCH_P1010) += p1010_serdes.o
obj-$(CONFIG_ARCH_P1011) += p1021_serdes.o
diff --git a/arch/powerpc/cpu/mpc85xx/cpu.c b/arch/powerpc/cpu/mpc85xx/cpu.c
index 5170610..fc25bb2 100644
--- a/arch/powerpc/cpu/mpc85xx/cpu.c
+++ b/arch/powerpc/cpu/mpc85xx/cpu.c
@@ -395,7 +395,9 @@
void print_reginfo(void)
{
print_tlbcam();
+#ifdef CONFIG_FSL_LAW
print_laws();
+#endif
#if defined(CONFIG_FSL_LBC)
print_lbc_regs();
#endif
diff --git a/arch/powerpc/cpu/mpc85xx/cpu_init_early.c b/arch/powerpc/cpu/mpc85xx/cpu_init_early.c
index 4195ecc..5a0d33b 100644
--- a/arch/powerpc/cpu/mpc85xx/cpu_init_early.c
+++ b/arch/powerpc/cpu/mpc85xx/cpu_init_early.c
@@ -123,7 +123,9 @@
setbits_be32(&gur->pmuxcr, MPC85xx_PMUXCR_LCLK_IFC_CS3);
#endif
+#ifdef CONFIG_FSL_LAW
init_laws();
+#endif
/*
* Work Around for IFC Erratum A003399, issue will hit only when execution
diff --git a/arch/powerpc/cpu/mpc85xx/mpc8569_serdes.c b/arch/powerpc/cpu/mpc85xx/mpc8569_serdes.c
deleted file mode 100644
index eb54b82..0000000
--- a/arch/powerpc/cpu/mpc85xx/mpc8569_serdes.c
+++ /dev/null
@@ -1,67 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * Copyright 2010 Freescale Semiconductor, Inc.
- */
-
-#include <config.h>
-#include <common.h>
-#include <log.h>
-#include <asm/io.h>
-#include <asm/immap_85xx.h>
-#include <asm/fsl_serdes.h>
-
-#define SRDS1_MAX_LANES 4
-
-static u32 serdes1_prtcl_map;
-
-static u8 serdes1_cfg_tbl[][SRDS1_MAX_LANES] = {
- [0x0] = {PCIE1, NONE, NONE, NONE},
- [0x1] = {SRIO1, SRIO2, SGMII_TSEC1, SGMII_TSEC2},
- [0x2] = {SRIO1, SRIO2, SGMII_TSEC1, SGMII_TSEC2},
- [0x3] = {SRIO1, SRIO2, NONE, NONE},
- [0x4] = {PCIE1, NONE, SGMII_TSEC1, SGMII_TSEC2},
- [0x5] = {PCIE1, PCIE1, SGMII_TSEC1, SGMII_TSEC2},
- [0x6] = {PCIE1, NONE, SRIO1, SRIO2},
- [0x7] = {PCIE1, PCIE1, SRIO1, SRIO2},
- [0x8] = {PCIE1, PCIE1, SRIO1, SRIO2},
- [0x9] = {SRIO1, SRIO1, SRIO1, SRIO1},
- [0xa] = {SRIO1, SRIO1, SRIO1, SRIO1},
- [0xb] = {SRIO1, SRIO1, SRIO1, SRIO1},
- [0xc] = {PCIE1, SRIO1, SGMII_TSEC1, SGMII_TSEC2},
- [0xf] = {PCIE1, PCIE1, PCIE1, PCIE1},
-};
-
-int is_serdes_configured(enum srds_prtcl prtcl)
-{
- if (!(serdes1_prtcl_map & (1 << NONE)))
- fsl_serdes_init();
-
- return (1 << prtcl) & serdes1_prtcl_map;
-}
-
-void fsl_serdes_init(void)
-{
- ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
- u32 pordevsr = in_be32(&gur->pordevsr);
- u32 srds_cfg = (pordevsr & MPC85xx_PORDEVSR_IO_SEL) >>
- MPC85xx_PORDEVSR_IO_SEL_SHIFT;
- int lane;
-
- if (serdes1_prtcl_map & (1 << NONE))
- return;
-
- debug("PORDEVSR[IO_SEL_SRDS] = %x\n", srds_cfg);
-
- if (srds_cfg >= ARRAY_SIZE(serdes1_cfg_tbl)) {
- printf("Invalid PORDEVSR[IO_SEL_SRDS] = %d\n", srds_cfg);
- return;
- }
-
- for (lane = 0; lane < SRDS1_MAX_LANES; lane++) {
- enum srds_prtcl lane_prtcl = serdes1_cfg_tbl[srds_cfg][lane];
- serdes1_prtcl_map |= (1 << lane_prtcl);
- }
-
- /* Set the first bit to indicate serdes has been initialized */
- serdes1_prtcl_map |= (1 << NONE);
-}
diff --git a/arch/powerpc/cpu/mpc85xx/speed.c b/arch/powerpc/cpu/mpc85xx/speed.c
index 09653c7..9c89ce5 100644
--- a/arch/powerpc/cpu/mpc85xx/speed.c
+++ b/arch/powerpc/cpu/mpc85xx/speed.c
@@ -630,7 +630,7 @@
gd->arch.i2c2_clk = gd->arch.i2c1_clk;
#if defined(CONFIG_FSL_ESDHC)
-#if defined(CONFIG_ARCH_MPC8569) || defined(CONFIG_ARCH_P1010)
+#if defined(CONFIG_ARCH_P1010)
gd->arch.sdhc_clk = gd->bus_clk;
#else
gd->arch.sdhc_clk = gd->bus_clk / 2;
diff --git a/arch/powerpc/cpu/mpc85xx/start.S b/arch/powerpc/cpu/mpc85xx/start.S
index dd784e7..f41e82a 100644
--- a/arch/powerpc/cpu/mpc85xx/start.S
+++ b/arch/powerpc/cpu/mpc85xx/start.S
@@ -344,39 +344,6 @@
mtspr DBCR0,r0
#endif
-#ifdef CONFIG_ARCH_MPC8569
-#define CONFIG_SYS_LBC_ADDR (CONFIG_SYS_CCSRBAR_DEFAULT + 0x5000)
-#define CONFIG_SYS_LBCR_ADDR (CONFIG_SYS_LBC_ADDR + 0xd0)
-
- /* MPC8569 Rev.0 silcon needs to set bit 13 of LBCR to allow elBC to
- * use address space which is more than 12bits, and it must be done in
- * the 4K boot page. So we set this bit here.
- */
-
- /* create a temp mapping TLB0[0] for LBCR */
- create_tlb0_entry 0, \
- 0, BOOKE_PAGESZ_4K, \
- CONFIG_SYS_LBC_ADDR, MAS2_I|MAS2_G, \
- CONFIG_SYS_LBC_ADDR, MAS3_SW|MAS3_SR, \
- 0, r6
-
- /* Set LBCR register */
- lis r4,CONFIG_SYS_LBCR_ADDR@h
- ori r4,r4,CONFIG_SYS_LBCR_ADDR@l
-
- lis r5,CONFIG_SYS_LBC_LBCR@h
- ori r5,r5,CONFIG_SYS_LBC_LBCR@l
- stw r5,0(r4)
- isync
-
- /* invalidate this temp TLB */
- lis r4,CONFIG_SYS_LBC_ADDR@h
- ori r4,r4,CONFIG_SYS_LBC_ADDR@l
- tlbivax 0,r4
- isync
-
-#endif /* CONFIG_ARCH_MPC8569 */
-
/*
* Search for the TLB that covers the code we're executing, and shrink it
* so that it covers only this 4K page. That will ensure that any other
diff --git a/arch/powerpc/include/asm/arch-mpc85xx/gpio.h b/arch/powerpc/include/asm/arch-mpc85xx/gpio.h
index c7086a8..79ba786 100644
--- a/arch/powerpc/include/asm/arch-mpc85xx/gpio.h
+++ b/arch/powerpc/include/asm/arch-mpc85xx/gpio.h
@@ -18,7 +18,7 @@
#endif
struct mpc8xxx_gpio_plat {
- ulong addr;
+ phys_addr_t addr;
unsigned long size;
uint ngpios;
};
diff --git a/arch/powerpc/include/asm/config_mpc85xx.h b/arch/powerpc/include/asm/config_mpc85xx.h
index f25ba1a..4d70259 100644
--- a/arch/powerpc/include/asm/config_mpc85xx.h
+++ b/arch/powerpc/include/asm/config_mpc85xx.h
@@ -38,16 +38,6 @@
#define CONFIG_SYS_FSL_RMU
#define CONFIG_SYS_FSL_SRIO_MSG_UNIT_NUM 2
-#elif defined(CONFIG_ARCH_MPC8569)
-#define QE_MURAM_SIZE 0x20000UL
-#define MAX_QE_RISC 4
-#define QE_NUM_OF_SNUM 46
-#define CONFIG_SYS_FSL_SRIO_MAX_PORTS 1
-#define CONFIG_SYS_FSL_SRIO_OB_WIN_NUM 9
-#define CONFIG_SYS_FSL_SRIO_IB_WIN_NUM 5
-#define CONFIG_SYS_FSL_RMU
-#define CONFIG_SYS_FSL_SRIO_MSG_UNIT_NUM 2
-
#elif defined(CONFIG_ARCH_P1010)
#define CONFIG_FSL_SDHC_V2_3
#define CONFIG_TSECV2
diff --git a/arch/powerpc/include/asm/immap_85xx.h b/arch/powerpc/include/asm/immap_85xx.h
index bfa601e..905613f 100644
--- a/arch/powerpc/include/asm/immap_85xx.h
+++ b/arch/powerpc/include/asm/immap_85xx.h
@@ -272,6 +272,7 @@
u32 gpier;
u32 gpimr;
u32 gpicr;
+ u32 gpibe;
} ccsr_gpio_t;
#endif
@@ -2204,15 +2205,8 @@
u32 gpiocr; /* GPIO control */
#endif
u8 res3[12];
-#if defined(CONFIG_ARCH_MPC8569)
- u32 plppar1; /* Platform port pin assignment 1 */
- u32 plppar2; /* Platform port pin assignment 2 */
- u32 plpdir1; /* Platform port pin direction 1 */
- u32 plpdir2; /* Platform port pin direction 2 */
-#else
u32 gpoutdr; /* General-purpose output data */
u8 res4[12];
-#endif
u32 gpindr; /* General-purpose input data */
u8 res5[12];
u32 pmuxcr; /* Alt. function signal multiplex control */
@@ -2478,7 +2472,7 @@
u32 svr; /* System version */
u8 res10[8];
u32 rstcr; /* Reset control */
-#if defined(CONFIG_ARCH_MPC8568) || defined(CONFIG_ARCH_MPC8569)
+#if defined(CONFIG_ARCH_MPC8568)
u8 res11a[76];
par_io_t qe_par_io[7];
u8 res11b[1600];
diff --git a/arch/powerpc/include/asm/io.h b/arch/powerpc/include/asm/io.h
index 6d76e3e..998a82a 100644
--- a/arch/powerpc/include/asm/io.h
+++ b/arch/powerpc/include/asm/io.h
@@ -10,7 +10,10 @@
#include <asm/byteorder.h>
#ifdef CONFIG_ADDR_MAP
+#include <asm/global_data.h>
#include <addr_map.h>
+
+DECLARE_GLOBAL_DATA_PTR;
#endif
#define SIO_CONFIG_RA 0x398
@@ -303,20 +306,20 @@
static inline void *phys_to_virt(phys_addr_t paddr)
{
#ifdef CONFIG_ADDR_MAP
- return addrmap_phys_to_virt(paddr);
-#else
- return (void *)((unsigned long)paddr);
+ if (gd->flags & GD_FLG_RELOC)
+ return addrmap_phys_to_virt(paddr);
#endif
+ return (void *)((unsigned long)paddr);
}
#define phys_to_virt phys_to_virt
static inline phys_addr_t virt_to_phys(void * vaddr)
{
#ifdef CONFIG_ADDR_MAP
- return addrmap_virt_to_phys(vaddr);
-#else
- return (phys_addr_t)((unsigned long)vaddr);
+ if (gd->flags & GD_FLG_RELOC)
+ return addrmap_virt_to_phys(vaddr);
#endif
+ return (phys_addr_t)((unsigned long)vaddr);
}
#define virt_to_phys virt_to_phys
diff --git a/arch/riscv/dts/k210-maix-bit.dts b/arch/riscv/dts/k210-maix-bit.dts
index e4dea20..902dcfd 100644
--- a/arch/riscv/dts/k210-maix-bit.dts
+++ b/arch/riscv/dts/k210-maix-bit.dts
@@ -200,6 +200,8 @@
compatible = "jedec,spi-nor";
reg = <0>;
spi-max-frequency = <50000000>;
+ spi-tx-bus-width = <4>;
+ spi-rx-bus-width = <4>;
m25p,fast-read;
broken-flash-reset;
};
diff --git a/arch/sandbox/dts/test.dts b/arch/sandbox/dts/test.dts
index d4195b4..2600360 100644
--- a/arch/sandbox/dts/test.dts
+++ b/arch/sandbox/dts/test.dts
@@ -2,6 +2,7 @@
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/gpio/sandbox-gpio.h>
+#include <dt-bindings/input/input.h>
#include <dt-bindings/pinctrl/sandbox-pinmux.h>
#include <dt-bindings/mux/mux.h>
@@ -69,6 +70,30 @@
};
};
+ buttons2 {
+ compatible = "adc-keys";
+ io-channels = <&adc 3>;
+ keyup-threshold-microvolt = <3000000>;
+
+ button-up {
+ label = "button3";
+ linux,code = <KEY_F3>;
+ press-threshold-microvolt = <1500000>;
+ };
+
+ button-down {
+ label = "button4";
+ linux,code = <KEY_F4>;
+ press-threshold-microvolt = <1000000>;
+ };
+
+ button-enter {
+ label = "button5";
+ linux,code = <KEY_F5>;
+ press-threshold-microvolt = <500000>;
+ };
+ };
+
cros_ec: cros-ec {
reg = <0 0>;
compatible = "google,cros-ec-sandbox";
@@ -608,8 +633,9 @@
i2c-eeprom = <&bootcount_i2c>;
};
- adc@0 {
+ adc: adc@0 {
compatible = "sandbox,adc";
+ #io-channel-cells = <1>;
vdd-supply = <&buck2>;
vss-microvolts = <0>;
};
diff --git a/arch/x86/Kconfig b/arch/x86/Kconfig
index eddf2a7..5b089af 100644
--- a/arch/x86/Kconfig
+++ b/arch/x86/Kconfig
@@ -1001,6 +1001,28 @@
config PCIEX_LENGTH_64MB
bool
+config INTEL_SOC
+ bool
+ help
+ This is enabled on Intel SoCs that can support various advanced
+ features such as power management (requiring asm/arch/pm.h), system
+ agent (asm/arch/systemagent.h) and an I/O map for ACPI
+ (asm/arch/iomap.h).
+
+ This cannot be selected in a defconfig file. It must be enabled by a
+ 'select' in the SoC's Kconfig.
+
+if INTEL_SOC
+
+config INTEL_ACPIGEN
+ bool "Support ACPI table generation for Intel SoCs"
+ depends on ACPIGEN
+ help
+ This option adds some functions used for programmatic generation of
+ ACPI tables on Intel SoCs. This provides features for writing CPU
+ information such as P states and T stages. Also included is a way
+ to create a GNVS table and set it up.
+
config INTEL_GMA_ACPI
bool "Generate ACPI table for Intel GMA graphics"
help
@@ -1023,4 +1045,6 @@
Select this option for Atom-based platforms which use the SWSMISCI
register (0xe0) rather than the SWSCI register (0xe8).
+endif # INTEL_SOC
+
endmenu
diff --git a/arch/x86/cpu/apollolake/Kconfig b/arch/x86/cpu/apollolake/Kconfig
index f5dbd6c..590fe31 100644
--- a/arch/x86/cpu/apollolake/Kconfig
+++ b/arch/x86/cpu/apollolake/Kconfig
@@ -9,6 +9,7 @@
select HAVE_FSP
select ARCH_MISC_INIT
select USE_CAR
+ select INTEL_SOC
select INTEL_PMC
select TPL_X86_TSC_TIMER_NATIVE
select SPL_PCH_SUPPORT
diff --git a/arch/x86/cpu/intel_common/lpc.c b/arch/x86/cpu/intel_common/lpc.c
index 23befbe..f31fddb 100644
--- a/arch/x86/cpu/intel_common/lpc.c
+++ b/arch/x86/cpu/intel_common/lpc.c
@@ -53,7 +53,7 @@
count = fdtdec_get_int_array_count(gd->fdt_blob, dev_of_offset(dev),
"intel,gen-dec", (u32 *)values,
- sizeof(values) / sizeof(u32));
+ sizeof(values) / (sizeof(u32)));
if (count < 0)
return -EINVAL;
diff --git a/arch/x86/include/asm/intel_gnvs.h b/arch/x86/include/asm/intel_gnvs.h
index 69a2081..fc743dc 100644
--- a/arch/x86/include/asm/intel_gnvs.h
+++ b/arch/x86/include/asm/intel_gnvs.h
@@ -107,6 +107,10 @@
u8 unused2[0x1000 - 0x100]; /* Pad out to 4096 bytes */
#endif
};
+#ifdef CONFIG_CHROMEOS
check_member(acpi_global_nvs, chromeos, GNVS_CHROMEOS_ACPI_OFFSET);
+#else
+check_member(acpi_global_nvs, unused2, GNVS_CHROMEOS_ACPI_OFFSET);
+#endif
#endif /* _INTEL_GNVS_H_ */
diff --git a/board/CZ.NIC/turris_omnia/turris_omnia.c b/board/CZ.NIC/turris_omnia/turris_omnia.c
index 0353d58..1d3cefe 100644
--- a/board/CZ.NIC/turris_omnia/turris_omnia.c
+++ b/board/CZ.NIC/turris_omnia/turris_omnia.c
@@ -286,6 +286,7 @@
MV_DDR_TIM_2T} }, /* timing */
BUS_MASK_32BIT, /* Busses mask */
MV_DDR_CFG_DEFAULT, /* ddr configuration data source */
+ NOT_COMBINED, /* ddr twin-die combined */
{ {0} }, /* raw spd data */
{0} /* timing parameters */
};
@@ -308,6 +309,7 @@
MV_DDR_TIM_2T} }, /* timing */
BUS_MASK_32BIT, /* Busses mask */
MV_DDR_CFG_DEFAULT, /* ddr configuration data source */
+ NOT_COMBINED, /* ddr twin-die combined */
{ {0} }, /* raw spd data */
{0} /* timing parameters */
};
diff --git a/board/Marvell/db-88f6820-amc/db-88f6820-amc.c b/board/Marvell/db-88f6820-amc/db-88f6820-amc.c
index 163a1b3..122c63d 100644
--- a/board/Marvell/db-88f6820-amc/db-88f6820-amc.c
+++ b/board/Marvell/db-88f6820-amc/db-88f6820-amc.c
@@ -73,6 +73,7 @@
MV_DDR_TIM_DEFAULT} }, /* timing */
BUS_MASK_32BIT, /* Busses mask */
MV_DDR_CFG_DEFAULT, /* ddr configuration data source */
+ NOT_COMBINED, /* ddr twin-die combined */
{ {0} }, /* raw spd data */
{0} /* timing parameters */
};
diff --git a/board/Marvell/db-88f6820-gp/db-88f6820-gp.c b/board/Marvell/db-88f6820-gp/db-88f6820-gp.c
index 06307e5..1edc1cb 100644
--- a/board/Marvell/db-88f6820-gp/db-88f6820-gp.c
+++ b/board/Marvell/db-88f6820-gp/db-88f6820-gp.c
@@ -94,6 +94,7 @@
MV_DDR_TIM_DEFAULT} }, /* timing */
BUS_MASK_32BIT, /* Busses mask */
MV_DDR_CFG_DEFAULT, /* ddr configuration data source */
+ NOT_COMBINED, /* ddr twin-die combined */
{ {0} }, /* raw spd data */
{0} /* timing parameters */
};
diff --git a/board/alliedtelesis/x530/x530.c b/board/alliedtelesis/x530/x530.c
index d602092..7bcfa82 100644
--- a/board/alliedtelesis/x530/x530.c
+++ b/board/alliedtelesis/x530/x530.c
@@ -68,6 +68,7 @@
MV_DDR_TIM_2T} }, /* timing */
BUS_MASK_32BIT_ECC, /* subphys mask */
MV_DDR_CFG_DEFAULT, /* ddr configuration data source */
+ NOT_COMBINED, /* ddr twin-die combined */
{ {0} }, /* raw spd data */
{0}, /* timing parameters */
{ {0} }, /* electrical configuration */
diff --git a/board/beacon/imx8mn/Kconfig b/board/beacon/imx8mn/Kconfig
index 6ed17c0..2bcfb25 100644
--- a/board/beacon/imx8mn/Kconfig
+++ b/board/beacon/imx8mn/Kconfig
@@ -13,6 +13,10 @@
bool "Force to use nominal mode for SOC and ARM"
default n
+config IMX8MN_BEACON_2GB_LPDDR
+ bool "Enable 2GB LPDDR"
+ default n
+
source "board/freescale/common/Kconfig"
endif
diff --git a/board/beacon/imx8mn/MAINTAINERS b/board/beacon/imx8mn/MAINTAINERS
index 4e3fc71..4805cb2 100644
--- a/board/beacon/imx8mn/MAINTAINERS
+++ b/board/beacon/imx8mn/MAINTAINERS
@@ -4,3 +4,4 @@
F: board/beacon/imx8mn/
F: include/configs/imx8mn_beacon.h
F: configs/imx8mn_beacon_defconfig
+F: configs/imx8mn_beacon_2g_defconfig
diff --git a/board/beacon/imx8mn/Makefile b/board/beacon/imx8mn/Makefile
index 9e842de..d620ccb 100644
--- a/board/beacon/imx8mn/Makefile
+++ b/board/beacon/imx8mn/Makefile
@@ -8,6 +8,9 @@
obj-y += ../../freescale/common/
ifdef CONFIG_SPL_BUILD
obj-y += spl.o
-obj-$(CONFIG_IMX8M_LPDDR4) += lpddr4_timing.o
-obj-$(CONFIG_IMX8M_DDR4) += ddr4_timing.o
+ifdef CONFIG_IMX8MN_BEACON_2GB_LPDDR
+obj-y += lpddr4_2g_timing.o
+else
+obj-y += lpddr4_timing.o
+endif
endif
diff --git a/board/beacon/imx8mn/lpddr4_2g_timing.c b/board/beacon/imx8mn/lpddr4_2g_timing.c
new file mode 100644
index 0000000..3c32d80
--- /dev/null
+++ b/board/beacon/imx8mn/lpddr4_2g_timing.c
@@ -0,0 +1,1440 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright 2019 NXP
+ *
+ * Generated code from MX8M_DDR_tool
+ * Align with uboot-imx_v2018.03_4.14.78_1.0.0_ga
+ */
+
+#include <linux/kernel.h>
+#include <asm/arch/ddr.h>
+
+struct dram_cfg_param ddr_ddrc_cfg[] = {
+ /** Initialize DDRC registers **/
+ { 0x3d400304, 0x1 },
+ { 0x3d400030, 0x1 },
+ { 0x3d400000, 0xa3080020 },
+ { 0x3d400020, 0x202 },
+ { 0x3d400024, 0x3e800 },
+ { 0x3d400064, 0x3000e0 },
+ { 0x3d4000d0, 0xc003061c },
+ { 0x3d4000d4, 0x9e0000 },
+ { 0x3d4000dc, 0xd4002d },
+ { 0x3d4000e0, 0x310000 },
+ { 0x3d4000e8, 0x66004d },
+ { 0x3d4000ec, 0x16004d },
+ { 0x3d400100, 0x1a200d22 },
+ { 0x3d400104, 0x60633 },
+ { 0x3d40010c, 0xc0c000 },
+ { 0x3d400110, 0xf04080f },
+ { 0x3d400114, 0x2040c0c },
+ { 0x3d400118, 0x1010007 },
+ { 0x3d40011c, 0x401 },
+ { 0x3d400130, 0x20600 },
+ { 0x3d400134, 0xc100002 },
+ { 0x3d400138, 0xe6 },
+ { 0x3d400144, 0xa00050 },
+ { 0x3d400180, 0x3200018 },
+ { 0x3d400184, 0x28061a8 },
+ { 0x3d400188, 0x0 },
+ { 0x3d400190, 0x497820a },
+ { 0x3d400194, 0x80303 },
+ { 0x3d4001b4, 0x170a },
+ { 0x3d4001a0, 0xe0400018 },
+ { 0x3d4001a4, 0xdf00e4 },
+ { 0x3d4001a8, 0x80000000 },
+ { 0x3d4001b0, 0x11 },
+ { 0x3d4001c0, 0x1 },
+ { 0x3d4001c4, 0x1 },
+ { 0x3d4000f4, 0xc99 },
+ { 0x3d400108, 0x70e1617 },
+ { 0x3d400200, 0x17 },
+ { 0x3d40020c, 0x0 },
+ { 0x3d400210, 0x1f1f },
+ { 0x3d400204, 0x80808 },
+ { 0x3d400214, 0x7070707 },
+ { 0x3d400218, 0x7070707 },
+ { 0x3d400250, 0x29001701 },
+ { 0x3d400254, 0x2c },
+ { 0x3d40025c, 0x4000030 },
+ { 0x3d400264, 0x900093e7 },
+ { 0x3d40026c, 0x2005574 },
+ { 0x3d400400, 0x111 },
+ { 0x3d400408, 0x72ff },
+ { 0x3d400494, 0x2100e07 },
+ { 0x3d400498, 0x620096 },
+ { 0x3d40049c, 0x1100e07 },
+ { 0x3d4004a0, 0xc8012c },
+ { 0x3d402020, 0x0 },
+ { 0x3d402024, 0x7d00 },
+ { 0x3d402050, 0x20d040 },
+ { 0x3d402064, 0x6001c },
+ { 0x3d4020dc, 0x840000 },
+ { 0x3d4020e0, 0x310000 },
+ { 0x3d4020e8, 0x66004d },
+ { 0x3d4020ec, 0x16004d },
+ { 0x3d402100, 0xa040105 },
+ { 0x3d402104, 0x30407 },
+ { 0x3d402108, 0x203060b },
+ { 0x3d40210c, 0x505000 },
+ { 0x3d402110, 0x2040202 },
+ { 0x3d402114, 0x2030202 },
+ { 0x3d402118, 0x1010004 },
+ { 0x3d40211c, 0x301 },
+ { 0x3d402130, 0x20300 },
+ { 0x3d402134, 0xa100002 },
+ { 0x3d402138, 0x1d },
+ { 0x3d402144, 0x14000a },
+ { 0x3d402180, 0x640004 },
+ { 0x3d402190, 0x3818200 },
+ { 0x3d402194, 0x80303 },
+ { 0x3d4021b4, 0x100 },
+ { 0x3d4020f4, 0xc99 },
+ { 0x3d403020, 0x0 },
+ { 0x3d403024, 0x1f40 },
+ { 0x3d403050, 0x20d040 },
+ { 0x3d403064, 0x30007 },
+ { 0x3d4030dc, 0x840000 },
+ { 0x3d4030e0, 0x310000 },
+ { 0x3d4030e8, 0x66004d },
+ { 0x3d4030ec, 0x16004d },
+ { 0x3d403100, 0xa010102 },
+ { 0x3d403104, 0x30404 },
+ { 0x3d403108, 0x203060b },
+ { 0x3d40310c, 0x505000 },
+ { 0x3d403110, 0x2040202 },
+ { 0x3d403114, 0x2030202 },
+ { 0x3d403118, 0x1010004 },
+ { 0x3d40311c, 0x301 },
+ { 0x3d403130, 0x20300 },
+ { 0x3d403134, 0xa100002 },
+ { 0x3d403138, 0x8 },
+ { 0x3d403144, 0x50003 },
+ { 0x3d403180, 0x190004 },
+ { 0x3d403190, 0x3818200 },
+ { 0x3d403194, 0x80303 },
+ { 0x3d4031b4, 0x100 },
+ { 0x3d4030f4, 0xc99 },
+ { 0x3d400028, 0x0 },
+};
+
+/* PHY Initialize Configuration */
+struct dram_cfg_param ddr_ddrphy_cfg[] = {
+ { 0x100a0, 0x0 },
+ { 0x100a1, 0x1 },
+ { 0x100a2, 0x3 },
+ { 0x100a3, 0x2 },
+ { 0x100a4, 0x4 },
+ { 0x100a5, 0x5 },
+ { 0x100a6, 0x7 },
+ { 0x100a7, 0x6 },
+ { 0x110a0, 0x0 },
+ { 0x110a1, 0x1 },
+ { 0x110a2, 0x2 },
+ { 0x110a3, 0x3 },
+ { 0x110a4, 0x5 },
+ { 0x110a5, 0x4 },
+ { 0x110a6, 0x6 },
+ { 0x110a7, 0x7 },
+ { 0x1005f, 0x1ff },
+ { 0x1015f, 0x1ff },
+ { 0x1105f, 0x1ff },
+ { 0x1115f, 0x1ff },
+ { 0x11005f, 0x1ff },
+ { 0x11015f, 0x1ff },
+ { 0x11105f, 0x1ff },
+ { 0x11115f, 0x1ff },
+ { 0x21005f, 0x1ff },
+ { 0x21015f, 0x1ff },
+ { 0x21105f, 0x1ff },
+ { 0x21115f, 0x1ff },
+ { 0x55, 0x1ff },
+ { 0x1055, 0x1ff },
+ { 0x2055, 0x1ff },
+ { 0x3055, 0x1ff },
+ { 0x4055, 0x1ff },
+ { 0x5055, 0x1ff },
+ { 0x6055, 0x1ff },
+ { 0x7055, 0x1ff },
+ { 0x8055, 0x1ff },
+ { 0x9055, 0x1ff },
+ { 0x200c5, 0x19 },
+ { 0x1200c5, 0x7 },
+ { 0x2200c5, 0x7 },
+ { 0x2002e, 0x2 },
+ { 0x12002e, 0x2 },
+ { 0x22002e, 0x2 },
+ { 0x90204, 0x0 },
+ { 0x190204, 0x0 },
+ { 0x290204, 0x0 },
+ { 0x20024, 0x1a3 },
+ { 0x2003a, 0x2 },
+ { 0x120024, 0x1a3 },
+ { 0x2003a, 0x2 },
+ { 0x220024, 0x1a3 },
+ { 0x2003a, 0x2 },
+ { 0x20056, 0x3 },
+ { 0x120056, 0x3 },
+ { 0x220056, 0x3 },
+ { 0x1004d, 0xe00 },
+ { 0x1014d, 0xe00 },
+ { 0x1104d, 0xe00 },
+ { 0x1114d, 0xe00 },
+ { 0x11004d, 0xe00 },
+ { 0x11014d, 0xe00 },
+ { 0x11104d, 0xe00 },
+ { 0x11114d, 0xe00 },
+ { 0x21004d, 0xe00 },
+ { 0x21014d, 0xe00 },
+ { 0x21104d, 0xe00 },
+ { 0x21114d, 0xe00 },
+ { 0x10049, 0xeba },
+ { 0x10149, 0xeba },
+ { 0x11049, 0xeba },
+ { 0x11149, 0xeba },
+ { 0x110049, 0xeba },
+ { 0x110149, 0xeba },
+ { 0x111049, 0xeba },
+ { 0x111149, 0xeba },
+ { 0x210049, 0xeba },
+ { 0x210149, 0xeba },
+ { 0x211049, 0xeba },
+ { 0x211149, 0xeba },
+ { 0x43, 0x63 },
+ { 0x1043, 0x63 },
+ { 0x2043, 0x63 },
+ { 0x3043, 0x63 },
+ { 0x4043, 0x63 },
+ { 0x5043, 0x63 },
+ { 0x6043, 0x63 },
+ { 0x7043, 0x63 },
+ { 0x8043, 0x63 },
+ { 0x9043, 0x63 },
+ { 0x20018, 0x1 },
+ { 0x20075, 0x4 },
+ { 0x20050, 0x0 },
+ { 0x20008, 0x320 },
+ { 0x120008, 0x64 },
+ { 0x220008, 0x19 },
+ { 0x20088, 0x9 },
+ { 0x200b2, 0xdc },
+ { 0x10043, 0x5a1 },
+ { 0x10143, 0x5a1 },
+ { 0x11043, 0x5a1 },
+ { 0x11143, 0x5a1 },
+ { 0x1200b2, 0xdc },
+ { 0x110043, 0x5a1 },
+ { 0x110143, 0x5a1 },
+ { 0x111043, 0x5a1 },
+ { 0x111143, 0x5a1 },
+ { 0x2200b2, 0xdc },
+ { 0x210043, 0x5a1 },
+ { 0x210143, 0x5a1 },
+ { 0x211043, 0x5a1 },
+ { 0x211143, 0x5a1 },
+ { 0x200fa, 0x1 },
+ { 0x1200fa, 0x1 },
+ { 0x2200fa, 0x1 },
+ { 0x20019, 0x1 },
+ { 0x120019, 0x1 },
+ { 0x220019, 0x1 },
+ { 0x200f0, 0x660 },
+ { 0x200f1, 0x0 },
+ { 0x200f2, 0x4444 },
+ { 0x200f3, 0x8888 },
+ { 0x200f4, 0x5665 },
+ { 0x200f5, 0x0 },
+ { 0x200f6, 0x0 },
+ { 0x200f7, 0xf000 },
+ { 0x20025, 0x0 },
+ { 0x2002d, 0x0 },
+ { 0x12002d, 0x0 },
+ { 0x22002d, 0x0 },
+ { 0x2005b, 0x7529 },
+ { 0x2005c, 0x0 },
+ { 0x200c7, 0x21 },
+ { 0x200ca, 0x24 },
+ { 0x200cc, 0x1f7 },
+ { 0x1200c7, 0x21 },
+ { 0x1200ca, 0x24 },
+ { 0x1200cc, 0x1f7 },
+ { 0x2200c7, 0x21 },
+ { 0x2200ca, 0x24 },
+ { 0x2200cc, 0x1f7 },
+ { 0x2007d, 0x212 },
+ { 0x12007d, 0x212 },
+ { 0x22007d, 0x212 },
+ { 0x2007c, 0x61 },
+ { 0x12007c, 0x61 },
+ { 0x22007c, 0x61 },
+ { 0x1004a, 0x500 },
+ { 0x1104a, 0x500 },
+ { 0x2002c, 0x0 },
+};
+
+/* ddr phy trained csr */
+struct dram_cfg_param ddr_ddrphy_trained_csr[] = {
+ {0x0200b2, 0x0},
+ {0x1200b2, 0x0},
+ {0x2200b2, 0x0},
+ {0x0200cb, 0x0},
+ {0x010043, 0x0},
+ {0x110043, 0x0},
+ {0x210043, 0x0},
+ {0x010143, 0x0},
+ {0x110143, 0x0},
+ {0x210143, 0x0},
+ {0x011043, 0x0},
+ {0x111043, 0x0},
+ {0x211043, 0x0},
+ {0x011143, 0x0},
+ {0x111143, 0x0},
+ {0x211143, 0x0},
+ {0x000080, 0x0},
+ {0x100080, 0x0},
+ {0x200080, 0x0},
+ {0x001080, 0x0},
+ {0x101080, 0x0},
+ {0x201080, 0x0},
+ {0x002080, 0x0},
+ {0x102080, 0x0},
+ {0x202080, 0x0},
+ {0x003080, 0x0},
+ {0x103080, 0x0},
+ {0x203080, 0x0},
+ {0x004080, 0x0},
+ {0x104080, 0x0},
+ {0x204080, 0x0},
+ {0x005080, 0x0},
+ {0x105080, 0x0},
+ {0x205080, 0x0},
+ {0x006080, 0x0},
+ {0x106080, 0x0},
+ {0x206080, 0x0},
+ {0x007080, 0x0},
+ {0x107080, 0x0},
+ {0x207080, 0x0},
+ {0x008080, 0x0},
+ {0x108080, 0x0},
+ {0x208080, 0x0},
+ {0x009080, 0x0},
+ {0x109080, 0x0},
+ {0x209080, 0x0},
+ {0x010080, 0x0},
+ {0x110080, 0x0},
+ {0x210080, 0x0},
+ {0x010180, 0x0},
+ {0x110180, 0x0},
+ {0x210180, 0x0},
+ {0x011080, 0x0},
+ {0x111080, 0x0},
+ {0x211080, 0x0},
+ {0x011180, 0x0},
+ {0x111180, 0x0},
+ {0x211180, 0x0},
+ {0x010081, 0x0},
+ {0x110081, 0x0},
+ {0x210081, 0x0},
+ {0x010181, 0x0},
+ {0x110181, 0x0},
+ {0x210181, 0x0},
+ {0x011081, 0x0},
+ {0x111081, 0x0},
+ {0x211081, 0x0},
+ {0x011181, 0x0},
+ {0x111181, 0x0},
+ {0x211181, 0x0},
+ {0x0100d0, 0x0},
+ {0x1100d0, 0x0},
+ {0x2100d0, 0x0},
+ {0x0101d0, 0x0},
+ {0x1101d0, 0x0},
+ {0x2101d0, 0x0},
+ {0x0110d0, 0x0},
+ {0x1110d0, 0x0},
+ {0x2110d0, 0x0},
+ {0x0111d0, 0x0},
+ {0x1111d0, 0x0},
+ {0x2111d0, 0x0},
+ {0x0100d1, 0x0},
+ {0x1100d1, 0x0},
+ {0x2100d1, 0x0},
+ {0x0101d1, 0x0},
+ {0x1101d1, 0x0},
+ {0x2101d1, 0x0},
+ {0x0110d1, 0x0},
+ {0x1110d1, 0x0},
+ {0x2110d1, 0x0},
+ {0x0111d1, 0x0},
+ {0x1111d1, 0x0},
+ {0x2111d1, 0x0},
+ {0x010068, 0x0},
+ {0x010168, 0x0},
+ {0x010268, 0x0},
+ {0x010368, 0x0},
+ {0x010468, 0x0},
+ {0x010568, 0x0},
+ {0x010668, 0x0},
+ {0x010768, 0x0},
+ {0x010868, 0x0},
+ {0x011068, 0x0},
+ {0x011168, 0x0},
+ {0x011268, 0x0},
+ {0x011368, 0x0},
+ {0x011468, 0x0},
+ {0x011568, 0x0},
+ {0x011668, 0x0},
+ {0x011768, 0x0},
+ {0x011868, 0x0},
+ {0x010069, 0x0},
+ {0x010169, 0x0},
+ {0x010269, 0x0},
+ {0x010369, 0x0},
+ {0x010469, 0x0},
+ {0x010569, 0x0},
+ {0x010669, 0x0},
+ {0x010769, 0x0},
+ {0x010869, 0x0},
+ {0x011069, 0x0},
+ {0x011169, 0x0},
+ {0x011269, 0x0},
+ {0x011369, 0x0},
+ {0x011469, 0x0},
+ {0x011569, 0x0},
+ {0x011669, 0x0},
+ {0x011769, 0x0},
+ {0x011869, 0x0},
+ {0x01008c, 0x0},
+ {0x11008c, 0x0},
+ {0x21008c, 0x0},
+ {0x01018c, 0x0},
+ {0x11018c, 0x0},
+ {0x21018c, 0x0},
+ {0x01108c, 0x0},
+ {0x11108c, 0x0},
+ {0x21108c, 0x0},
+ {0x01118c, 0x0},
+ {0x11118c, 0x0},
+ {0x21118c, 0x0},
+ {0x01008d, 0x0},
+ {0x11008d, 0x0},
+ {0x21008d, 0x0},
+ {0x01018d, 0x0},
+ {0x11018d, 0x0},
+ {0x21018d, 0x0},
+ {0x01108d, 0x0},
+ {0x11108d, 0x0},
+ {0x21108d, 0x0},
+ {0x01118d, 0x0},
+ {0x11118d, 0x0},
+ {0x21118d, 0x0},
+ {0x0100c0, 0x0},
+ {0x1100c0, 0x0},
+ {0x2100c0, 0x0},
+ {0x0101c0, 0x0},
+ {0x1101c0, 0x0},
+ {0x2101c0, 0x0},
+ {0x0102c0, 0x0},
+ {0x1102c0, 0x0},
+ {0x2102c0, 0x0},
+ {0x0103c0, 0x0},
+ {0x1103c0, 0x0},
+ {0x2103c0, 0x0},
+ {0x0104c0, 0x0},
+ {0x1104c0, 0x0},
+ {0x2104c0, 0x0},
+ {0x0105c0, 0x0},
+ {0x1105c0, 0x0},
+ {0x2105c0, 0x0},
+ {0x0106c0, 0x0},
+ {0x1106c0, 0x0},
+ {0x2106c0, 0x0},
+ {0x0107c0, 0x0},
+ {0x1107c0, 0x0},
+ {0x2107c0, 0x0},
+ {0x0108c0, 0x0},
+ {0x1108c0, 0x0},
+ {0x2108c0, 0x0},
+ {0x0110c0, 0x0},
+ {0x1110c0, 0x0},
+ {0x2110c0, 0x0},
+ {0x0111c0, 0x0},
+ {0x1111c0, 0x0},
+ {0x2111c0, 0x0},
+ {0x0112c0, 0x0},
+ {0x1112c0, 0x0},
+ {0x2112c0, 0x0},
+ {0x0113c0, 0x0},
+ {0x1113c0, 0x0},
+ {0x2113c0, 0x0},
+ {0x0114c0, 0x0},
+ {0x1114c0, 0x0},
+ {0x2114c0, 0x0},
+ {0x0115c0, 0x0},
+ {0x1115c0, 0x0},
+ {0x2115c0, 0x0},
+ {0x0116c0, 0x0},
+ {0x1116c0, 0x0},
+ {0x2116c0, 0x0},
+ {0x0117c0, 0x0},
+ {0x1117c0, 0x0},
+ {0x2117c0, 0x0},
+ {0x0118c0, 0x0},
+ {0x1118c0, 0x0},
+ {0x2118c0, 0x0},
+ {0x0100c1, 0x0},
+ {0x1100c1, 0x0},
+ {0x2100c1, 0x0},
+ {0x0101c1, 0x0},
+ {0x1101c1, 0x0},
+ {0x2101c1, 0x0},
+ {0x0102c1, 0x0},
+ {0x1102c1, 0x0},
+ {0x2102c1, 0x0},
+ {0x0103c1, 0x0},
+ {0x1103c1, 0x0},
+ {0x2103c1, 0x0},
+ {0x0104c1, 0x0},
+ {0x1104c1, 0x0},
+ {0x2104c1, 0x0},
+ {0x0105c1, 0x0},
+ {0x1105c1, 0x0},
+ {0x2105c1, 0x0},
+ {0x0106c1, 0x0},
+ {0x1106c1, 0x0},
+ {0x2106c1, 0x0},
+ {0x0107c1, 0x0},
+ {0x1107c1, 0x0},
+ {0x2107c1, 0x0},
+ {0x0108c1, 0x0},
+ {0x1108c1, 0x0},
+ {0x2108c1, 0x0},
+ {0x0110c1, 0x0},
+ {0x1110c1, 0x0},
+ {0x2110c1, 0x0},
+ {0x0111c1, 0x0},
+ {0x1111c1, 0x0},
+ {0x2111c1, 0x0},
+ {0x0112c1, 0x0},
+ {0x1112c1, 0x0},
+ {0x2112c1, 0x0},
+ {0x0113c1, 0x0},
+ {0x1113c1, 0x0},
+ {0x2113c1, 0x0},
+ {0x0114c1, 0x0},
+ {0x1114c1, 0x0},
+ {0x2114c1, 0x0},
+ {0x0115c1, 0x0},
+ {0x1115c1, 0x0},
+ {0x2115c1, 0x0},
+ {0x0116c1, 0x0},
+ {0x1116c1, 0x0},
+ {0x2116c1, 0x0},
+ {0x0117c1, 0x0},
+ {0x1117c1, 0x0},
+ {0x2117c1, 0x0},
+ {0x0118c1, 0x0},
+ {0x1118c1, 0x0},
+ {0x2118c1, 0x0},
+ {0x010020, 0x0},
+ {0x110020, 0x0},
+ {0x210020, 0x0},
+ {0x011020, 0x0},
+ {0x111020, 0x0},
+ {0x211020, 0x0},
+ {0x020072, 0x0},
+ {0x020073, 0x0},
+ {0x020074, 0x0},
+ {0x0100aa, 0x0},
+ {0x0110aa, 0x0},
+ {0x020010, 0x0},
+ {0x120010, 0x0},
+ {0x220010, 0x0},
+ {0x020011, 0x0},
+ {0x120011, 0x0},
+ {0x220011, 0x0},
+ {0x0100ae, 0x0},
+ {0x1100ae, 0x0},
+ {0x2100ae, 0x0},
+ {0x0100af, 0x0},
+ {0x1100af, 0x0},
+ {0x2100af, 0x0},
+ {0x0110ae, 0x0},
+ {0x1110ae, 0x0},
+ {0x2110ae, 0x0},
+ {0x0110af, 0x0},
+ {0x1110af, 0x0},
+ {0x2110af, 0x0},
+ {0x020020, 0x0},
+ {0x120020, 0x0},
+ {0x220020, 0x0},
+ {0x0100a0, 0x0},
+ {0x0100a1, 0x0},
+ {0x0100a2, 0x0},
+ {0x0100a3, 0x0},
+ {0x0100a4, 0x0},
+ {0x0100a5, 0x0},
+ {0x0100a6, 0x0},
+ {0x0100a7, 0x0},
+ {0x0110a0, 0x0},
+ {0x0110a1, 0x0},
+ {0x0110a2, 0x0},
+ {0x0110a3, 0x0},
+ {0x0110a4, 0x0},
+ {0x0110a5, 0x0},
+ {0x0110a6, 0x0},
+ {0x0110a7, 0x0},
+ {0x02007c, 0x0},
+ {0x12007c, 0x0},
+ {0x22007c, 0x0},
+ {0x02007d, 0x0},
+ {0x12007d, 0x0},
+ {0x22007d, 0x0},
+ {0x0400fd, 0x0},
+ {0x0400c0, 0x0},
+ {0x090201, 0x0},
+ {0x190201, 0x0},
+ {0x290201, 0x0},
+ {0x090202, 0x0},
+ {0x190202, 0x0},
+ {0x290202, 0x0},
+ {0x090203, 0x0},
+ {0x190203, 0x0},
+ {0x290203, 0x0},
+ {0x090204, 0x0},
+ {0x190204, 0x0},
+ {0x290204, 0x0},
+ {0x090205, 0x0},
+ {0x190205, 0x0},
+ {0x290205, 0x0},
+ {0x090206, 0x0},
+ {0x190206, 0x0},
+ {0x290206, 0x0},
+ {0x090207, 0x0},
+ {0x190207, 0x0},
+ {0x290207, 0x0},
+ {0x090208, 0x0},
+ {0x190208, 0x0},
+ {0x290208, 0x0},
+ {0x010062, 0x0},
+ {0x010162, 0x0},
+ {0x010262, 0x0},
+ {0x010362, 0x0},
+ {0x010462, 0x0},
+ {0x010562, 0x0},
+ {0x010662, 0x0},
+ {0x010762, 0x0},
+ {0x010862, 0x0},
+ {0x011062, 0x0},
+ {0x011162, 0x0},
+ {0x011262, 0x0},
+ {0x011362, 0x0},
+ {0x011462, 0x0},
+ {0x011562, 0x0},
+ {0x011662, 0x0},
+ {0x011762, 0x0},
+ {0x011862, 0x0},
+ {0x020077, 0x0},
+ {0x010001, 0x0},
+ {0x011001, 0x0},
+ {0x010040, 0x0},
+ {0x010140, 0x0},
+ {0x010240, 0x0},
+ {0x010340, 0x0},
+ {0x010440, 0x0},
+ {0x010540, 0x0},
+ {0x010640, 0x0},
+ {0x010740, 0x0},
+ {0x010840, 0x0},
+ {0x010030, 0x0},
+ {0x010130, 0x0},
+ {0x010230, 0x0},
+ {0x010330, 0x0},
+ {0x010430, 0x0},
+ {0x010530, 0x0},
+ {0x010630, 0x0},
+ {0x010730, 0x0},
+ {0x010830, 0x0},
+ {0x011040, 0x0},
+ {0x011140, 0x0},
+ {0x011240, 0x0},
+ {0x011340, 0x0},
+ {0x011440, 0x0},
+ {0x011540, 0x0},
+ {0x011640, 0x0},
+ {0x011740, 0x0},
+ {0x011840, 0x0},
+ {0x011030, 0x0},
+ {0x011130, 0x0},
+ {0x011230, 0x0},
+ {0x011330, 0x0},
+ {0x011430, 0x0},
+ {0x011530, 0x0},
+ {0x011630, 0x0},
+ {0x011730, 0x0},
+ {0x011830, 0x0},
+};
+
+/* P0 message block paremeter for training firmware */
+struct dram_cfg_param ddr_fsp0_cfg[] = {
+ { 0xd0000, 0x0 },
+ { 0x54003, 0xc80 },
+ { 0x54004, 0x2 },
+ { 0x54005, 0x2228 },
+ { 0x54006, 0x11 },
+ { 0x54008, 0x131f },
+ { 0x54009, 0xc8 },
+ { 0x5400b, 0x2 },
+ { 0x5400f, 0x100 },
+ { 0x54012, 0x310 },
+ { 0x54019, 0x2dd4 },
+ { 0x5401a, 0x31 },
+ { 0x5401b, 0x4d66 },
+ { 0x5401c, 0x4d00 },
+ { 0x5401e, 0x16 },
+ { 0x5401f, 0x2dd4 },
+ { 0x54020, 0x31 },
+ { 0x54021, 0x4d66 },
+ { 0x54022, 0x4d00 },
+ { 0x54024, 0x16 },
+ { 0x54032, 0xd400 },
+ { 0x54033, 0x312d },
+ { 0x54034, 0x6600 },
+ { 0x54035, 0x4d },
+ { 0x54036, 0x4d },
+ { 0x54037, 0x1600 },
+ { 0x54038, 0xd400 },
+ { 0x54039, 0x312d },
+ { 0x5403a, 0x6600 },
+ { 0x5403b, 0x4d },
+ { 0x5403c, 0x4d },
+ { 0x5403d, 0x1600 },
+ { 0xd0000, 0x1 },
+};
+
+/* P1 message block paremeter for training firmware */
+struct dram_cfg_param ddr_fsp1_cfg[] = {
+ { 0xd0000, 0x0 },
+ { 0x54002, 0x101 },
+ { 0x54003, 0x190 },
+ { 0x54004, 0x2 },
+ { 0x54005, 0x2228 },
+ { 0x54006, 0x11 },
+ { 0x54008, 0x121f },
+ { 0x54009, 0xc8 },
+ { 0x5400b, 0x2 },
+ { 0x5400f, 0x100 },
+ { 0x54012, 0x310 },
+ { 0x54019, 0x84 },
+ { 0x5401a, 0x31 },
+ { 0x5401b, 0x4d66 },
+ { 0x5401c, 0x4d00 },
+ { 0x5401e, 0x16 },
+ { 0x5401f, 0x84 },
+ { 0x54020, 0x31 },
+ { 0x54021, 0x4d66 },
+ { 0x54022, 0x4d00 },
+ { 0x54024, 0x16 },
+ { 0x54032, 0x8400 },
+ { 0x54033, 0x3100 },
+ { 0x54034, 0x6600 },
+ { 0x54035, 0x4d },
+ { 0x54036, 0x4d },
+ { 0x54037, 0x1600 },
+ { 0x54038, 0x8400 },
+ { 0x54039, 0x3100 },
+ { 0x5403a, 0x6600 },
+ { 0x5403b, 0x4d },
+ { 0x5403c, 0x4d },
+ { 0x5403d, 0x1600 },
+ { 0xd0000, 0x1 },
+};
+
+/* P2 message block paremeter for training firmware */
+struct dram_cfg_param ddr_fsp2_cfg[] = {
+ { 0xd0000, 0x0 },
+ { 0x54002, 0x102 },
+ { 0x54003, 0x64 },
+ { 0x54004, 0x2 },
+ { 0x54005, 0x2228 },
+ { 0x54006, 0x11 },
+ { 0x54008, 0x121f },
+ { 0x54009, 0xc8 },
+ { 0x5400b, 0x2 },
+ { 0x5400f, 0x100 },
+ { 0x54012, 0x310 },
+ { 0x54019, 0x84 },
+ { 0x5401a, 0x31 },
+ { 0x5401b, 0x4d66 },
+ { 0x5401c, 0x4d00 },
+ { 0x5401e, 0x16 },
+ { 0x5401f, 0x84 },
+ { 0x54020, 0x31 },
+ { 0x54021, 0x4d66 },
+ { 0x54022, 0x4d00 },
+ { 0x54024, 0x16 },
+ { 0x54032, 0x8400 },
+ { 0x54033, 0x3100 },
+ { 0x54034, 0x6600 },
+ { 0x54035, 0x4d },
+ { 0x54036, 0x4d },
+ { 0x54037, 0x1600 },
+ { 0x54038, 0x8400 },
+ { 0x54039, 0x3100 },
+ { 0x5403a, 0x6600 },
+ { 0x5403b, 0x4d },
+ { 0x5403c, 0x4d },
+ { 0x5403d, 0x1600 },
+ { 0xd0000, 0x1 },
+};
+
+/* P0 2D message block paremeter for training firmware */
+struct dram_cfg_param ddr_fsp0_2d_cfg[] = {
+ { 0xd0000, 0x0 },
+ { 0x54003, 0xc80 },
+ { 0x54004, 0x2 },
+ { 0x54005, 0x2228 },
+ { 0x54006, 0x11 },
+ { 0x54008, 0x61 },
+ { 0x54009, 0xc8 },
+ { 0x5400b, 0x2 },
+ { 0x5400d, 0x100 },
+ { 0x5400f, 0x100 },
+ { 0x54010, 0x1f7f },
+ { 0x54012, 0x310 },
+ { 0x54019, 0x2dd4 },
+ { 0x5401a, 0x31 },
+ { 0x5401b, 0x4d66 },
+ { 0x5401c, 0x4d00 },
+ { 0x5401e, 0x16 },
+ { 0x5401f, 0x2dd4 },
+ { 0x54020, 0x31 },
+ { 0x54021, 0x4d66 },
+ { 0x54022, 0x4d00 },
+ { 0x54024, 0x16 },
+ { 0x54032, 0xd400 },
+ { 0x54033, 0x312d },
+ { 0x54034, 0x6600 },
+ { 0x54035, 0x4d },
+ { 0x54036, 0x4d },
+ { 0x54037, 0x1600 },
+ { 0x54038, 0xd400 },
+ { 0x54039, 0x312d },
+ { 0x5403a, 0x6600 },
+ { 0x5403b, 0x4d },
+ { 0x5403c, 0x4d },
+ { 0x5403d, 0x1600 },
+ { 0xd0000, 0x1 },
+};
+
+/* DRAM PHY init engine image */
+struct dram_cfg_param ddr_phy_pie[] = {
+ { 0xd0000, 0x0 },
+ { 0x90000, 0x10 },
+ { 0x90001, 0x400 },
+ { 0x90002, 0x10e },
+ { 0x90003, 0x0 },
+ { 0x90004, 0x0 },
+ { 0x90005, 0x8 },
+ { 0x90029, 0xb },
+ { 0x9002a, 0x480 },
+ { 0x9002b, 0x109 },
+ { 0x9002c, 0x8 },
+ { 0x9002d, 0x448 },
+ { 0x9002e, 0x139 },
+ { 0x9002f, 0x8 },
+ { 0x90030, 0x478 },
+ { 0x90031, 0x109 },
+ { 0x90032, 0x0 },
+ { 0x90033, 0xe8 },
+ { 0x90034, 0x109 },
+ { 0x90035, 0x2 },
+ { 0x90036, 0x10 },
+ { 0x90037, 0x139 },
+ { 0x90038, 0xb },
+ { 0x90039, 0x7c0 },
+ { 0x9003a, 0x139 },
+ { 0x9003b, 0x44 },
+ { 0x9003c, 0x633 },
+ { 0x9003d, 0x159 },
+ { 0x9003e, 0x14f },
+ { 0x9003f, 0x630 },
+ { 0x90040, 0x159 },
+ { 0x90041, 0x47 },
+ { 0x90042, 0x633 },
+ { 0x90043, 0x149 },
+ { 0x90044, 0x4f },
+ { 0x90045, 0x633 },
+ { 0x90046, 0x179 },
+ { 0x90047, 0x8 },
+ { 0x90048, 0xe0 },
+ { 0x90049, 0x109 },
+ { 0x9004a, 0x0 },
+ { 0x9004b, 0x7c8 },
+ { 0x9004c, 0x109 },
+ { 0x9004d, 0x0 },
+ { 0x9004e, 0x1 },
+ { 0x9004f, 0x8 },
+ { 0x90050, 0x0 },
+ { 0x90051, 0x45a },
+ { 0x90052, 0x9 },
+ { 0x90053, 0x0 },
+ { 0x90054, 0x448 },
+ { 0x90055, 0x109 },
+ { 0x90056, 0x40 },
+ { 0x90057, 0x633 },
+ { 0x90058, 0x179 },
+ { 0x90059, 0x1 },
+ { 0x9005a, 0x618 },
+ { 0x9005b, 0x109 },
+ { 0x9005c, 0x40c0 },
+ { 0x9005d, 0x633 },
+ { 0x9005e, 0x149 },
+ { 0x9005f, 0x8 },
+ { 0x90060, 0x4 },
+ { 0x90061, 0x48 },
+ { 0x90062, 0x4040 },
+ { 0x90063, 0x633 },
+ { 0x90064, 0x149 },
+ { 0x90065, 0x0 },
+ { 0x90066, 0x4 },
+ { 0x90067, 0x48 },
+ { 0x90068, 0x40 },
+ { 0x90069, 0x633 },
+ { 0x9006a, 0x149 },
+ { 0x9006b, 0x10 },
+ { 0x9006c, 0x4 },
+ { 0x9006d, 0x18 },
+ { 0x9006e, 0x0 },
+ { 0x9006f, 0x4 },
+ { 0x90070, 0x78 },
+ { 0x90071, 0x549 },
+ { 0x90072, 0x633 },
+ { 0x90073, 0x159 },
+ { 0x90074, 0xd49 },
+ { 0x90075, 0x633 },
+ { 0x90076, 0x159 },
+ { 0x90077, 0x94a },
+ { 0x90078, 0x633 },
+ { 0x90079, 0x159 },
+ { 0x9007a, 0x441 },
+ { 0x9007b, 0x633 },
+ { 0x9007c, 0x149 },
+ { 0x9007d, 0x42 },
+ { 0x9007e, 0x633 },
+ { 0x9007f, 0x149 },
+ { 0x90080, 0x1 },
+ { 0x90081, 0x633 },
+ { 0x90082, 0x149 },
+ { 0x90083, 0x0 },
+ { 0x90084, 0xe0 },
+ { 0x90085, 0x109 },
+ { 0x90086, 0xa },
+ { 0x90087, 0x10 },
+ { 0x90088, 0x109 },
+ { 0x90089, 0x9 },
+ { 0x9008a, 0x3c0 },
+ { 0x9008b, 0x149 },
+ { 0x9008c, 0x9 },
+ { 0x9008d, 0x3c0 },
+ { 0x9008e, 0x159 },
+ { 0x9008f, 0x18 },
+ { 0x90090, 0x10 },
+ { 0x90091, 0x109 },
+ { 0x90092, 0x0 },
+ { 0x90093, 0x3c0 },
+ { 0x90094, 0x109 },
+ { 0x90095, 0x18 },
+ { 0x90096, 0x4 },
+ { 0x90097, 0x48 },
+ { 0x90098, 0x18 },
+ { 0x90099, 0x4 },
+ { 0x9009a, 0x58 },
+ { 0x9009b, 0xb },
+ { 0x9009c, 0x10 },
+ { 0x9009d, 0x109 },
+ { 0x9009e, 0x1 },
+ { 0x9009f, 0x10 },
+ { 0x900a0, 0x109 },
+ { 0x900a1, 0x5 },
+ { 0x900a2, 0x7c0 },
+ { 0x900a3, 0x109 },
+ { 0x40000, 0x811 },
+ { 0x40020, 0x880 },
+ { 0x40040, 0x0 },
+ { 0x40060, 0x0 },
+ { 0x40001, 0x4008 },
+ { 0x40021, 0x83 },
+ { 0x40041, 0x4f },
+ { 0x40061, 0x0 },
+ { 0x40002, 0x4040 },
+ { 0x40022, 0x83 },
+ { 0x40042, 0x51 },
+ { 0x40062, 0x0 },
+ { 0x40003, 0x811 },
+ { 0x40023, 0x880 },
+ { 0x40043, 0x0 },
+ { 0x40063, 0x0 },
+ { 0x40004, 0x720 },
+ { 0x40024, 0xf },
+ { 0x40044, 0x1740 },
+ { 0x40064, 0x0 },
+ { 0x40005, 0x16 },
+ { 0x40025, 0x83 },
+ { 0x40045, 0x4b },
+ { 0x40065, 0x0 },
+ { 0x40006, 0x716 },
+ { 0x40026, 0xf },
+ { 0x40046, 0x2001 },
+ { 0x40066, 0x0 },
+ { 0x40007, 0x716 },
+ { 0x40027, 0xf },
+ { 0x40047, 0x2800 },
+ { 0x40067, 0x0 },
+ { 0x40008, 0x716 },
+ { 0x40028, 0xf },
+ { 0x40048, 0xf00 },
+ { 0x40068, 0x0 },
+ { 0x40009, 0x720 },
+ { 0x40029, 0xf },
+ { 0x40049, 0x1400 },
+ { 0x40069, 0x0 },
+ { 0x4000a, 0xe08 },
+ { 0x4002a, 0xc15 },
+ { 0x4004a, 0x0 },
+ { 0x4006a, 0x0 },
+ { 0x4000b, 0x625 },
+ { 0x4002b, 0x15 },
+ { 0x4004b, 0x0 },
+ { 0x4006b, 0x0 },
+ { 0x4000c, 0x4028 },
+ { 0x4002c, 0x80 },
+ { 0x4004c, 0x0 },
+ { 0x4006c, 0x0 },
+ { 0x4000d, 0xe08 },
+ { 0x4002d, 0xc1a },
+ { 0x4004d, 0x0 },
+ { 0x4006d, 0x0 },
+ { 0x4000e, 0x625 },
+ { 0x4002e, 0x1a },
+ { 0x4004e, 0x0 },
+ { 0x4006e, 0x0 },
+ { 0x4000f, 0x4040 },
+ { 0x4002f, 0x80 },
+ { 0x4004f, 0x0 },
+ { 0x4006f, 0x0 },
+ { 0x40010, 0x2604 },
+ { 0x40030, 0x15 },
+ { 0x40050, 0x0 },
+ { 0x40070, 0x0 },
+ { 0x40011, 0x708 },
+ { 0x40031, 0x5 },
+ { 0x40051, 0x0 },
+ { 0x40071, 0x2002 },
+ { 0x40012, 0x8 },
+ { 0x40032, 0x80 },
+ { 0x40052, 0x0 },
+ { 0x40072, 0x0 },
+ { 0x40013, 0x2604 },
+ { 0x40033, 0x1a },
+ { 0x40053, 0x0 },
+ { 0x40073, 0x0 },
+ { 0x40014, 0x708 },
+ { 0x40034, 0xa },
+ { 0x40054, 0x0 },
+ { 0x40074, 0x2002 },
+ { 0x40015, 0x4040 },
+ { 0x40035, 0x80 },
+ { 0x40055, 0x0 },
+ { 0x40075, 0x0 },
+ { 0x40016, 0x60a },
+ { 0x40036, 0x15 },
+ { 0x40056, 0x1200 },
+ { 0x40076, 0x0 },
+ { 0x40017, 0x61a },
+ { 0x40037, 0x15 },
+ { 0x40057, 0x1300 },
+ { 0x40077, 0x0 },
+ { 0x40018, 0x60a },
+ { 0x40038, 0x1a },
+ { 0x40058, 0x1200 },
+ { 0x40078, 0x0 },
+ { 0x40019, 0x642 },
+ { 0x40039, 0x1a },
+ { 0x40059, 0x1300 },
+ { 0x40079, 0x0 },
+ { 0x4001a, 0x4808 },
+ { 0x4003a, 0x880 },
+ { 0x4005a, 0x0 },
+ { 0x4007a, 0x0 },
+ { 0x900a4, 0x0 },
+ { 0x900a5, 0x790 },
+ { 0x900a6, 0x11a },
+ { 0x900a7, 0x8 },
+ { 0x900a8, 0x7aa },
+ { 0x900a9, 0x2a },
+ { 0x900aa, 0x10 },
+ { 0x900ab, 0x7b2 },
+ { 0x900ac, 0x2a },
+ { 0x900ad, 0x0 },
+ { 0x900ae, 0x7c8 },
+ { 0x900af, 0x109 },
+ { 0x900b0, 0x10 },
+ { 0x900b1, 0x10 },
+ { 0x900b2, 0x109 },
+ { 0x900b3, 0x10 },
+ { 0x900b4, 0x2a8 },
+ { 0x900b5, 0x129 },
+ { 0x900b6, 0x8 },
+ { 0x900b7, 0x370 },
+ { 0x900b8, 0x129 },
+ { 0x900b9, 0xa },
+ { 0x900ba, 0x3c8 },
+ { 0x900bb, 0x1a9 },
+ { 0x900bc, 0xc },
+ { 0x900bd, 0x408 },
+ { 0x900be, 0x199 },
+ { 0x900bf, 0x14 },
+ { 0x900c0, 0x790 },
+ { 0x900c1, 0x11a },
+ { 0x900c2, 0x8 },
+ { 0x900c3, 0x4 },
+ { 0x900c4, 0x18 },
+ { 0x900c5, 0xe },
+ { 0x900c6, 0x408 },
+ { 0x900c7, 0x199 },
+ { 0x900c8, 0x8 },
+ { 0x900c9, 0x8568 },
+ { 0x900ca, 0x108 },
+ { 0x900cb, 0x18 },
+ { 0x900cc, 0x790 },
+ { 0x900cd, 0x16a },
+ { 0x900ce, 0x8 },
+ { 0x900cf, 0x1d8 },
+ { 0x900d0, 0x169 },
+ { 0x900d1, 0x10 },
+ { 0x900d2, 0x8558 },
+ { 0x900d3, 0x168 },
+ { 0x900d4, 0x70 },
+ { 0x900d5, 0x788 },
+ { 0x900d6, 0x16a },
+ { 0x900d7, 0x1ff8 },
+ { 0x900d8, 0x85a8 },
+ { 0x900d9, 0x1e8 },
+ { 0x900da, 0x50 },
+ { 0x900db, 0x798 },
+ { 0x900dc, 0x16a },
+ { 0x900dd, 0x60 },
+ { 0x900de, 0x7a0 },
+ { 0x900df, 0x16a },
+ { 0x900e0, 0x8 },
+ { 0x900e1, 0x8310 },
+ { 0x900e2, 0x168 },
+ { 0x900e3, 0x8 },
+ { 0x900e4, 0xa310 },
+ { 0x900e5, 0x168 },
+ { 0x900e6, 0xa },
+ { 0x900e7, 0x408 },
+ { 0x900e8, 0x169 },
+ { 0x900e9, 0x6e },
+ { 0x900ea, 0x0 },
+ { 0x900eb, 0x68 },
+ { 0x900ec, 0x0 },
+ { 0x900ed, 0x408 },
+ { 0x900ee, 0x169 },
+ { 0x900ef, 0x0 },
+ { 0x900f0, 0x8310 },
+ { 0x900f1, 0x168 },
+ { 0x900f2, 0x0 },
+ { 0x900f3, 0xa310 },
+ { 0x900f4, 0x168 },
+ { 0x900f5, 0x1ff8 },
+ { 0x900f6, 0x85a8 },
+ { 0x900f7, 0x1e8 },
+ { 0x900f8, 0x68 },
+ { 0x900f9, 0x798 },
+ { 0x900fa, 0x16a },
+ { 0x900fb, 0x78 },
+ { 0x900fc, 0x7a0 },
+ { 0x900fd, 0x16a },
+ { 0x900fe, 0x68 },
+ { 0x900ff, 0x790 },
+ { 0x90100, 0x16a },
+ { 0x90101, 0x8 },
+ { 0x90102, 0x8b10 },
+ { 0x90103, 0x168 },
+ { 0x90104, 0x8 },
+ { 0x90105, 0xab10 },
+ { 0x90106, 0x168 },
+ { 0x90107, 0xa },
+ { 0x90108, 0x408 },
+ { 0x90109, 0x169 },
+ { 0x9010a, 0x58 },
+ { 0x9010b, 0x0 },
+ { 0x9010c, 0x68 },
+ { 0x9010d, 0x0 },
+ { 0x9010e, 0x408 },
+ { 0x9010f, 0x169 },
+ { 0x90110, 0x0 },
+ { 0x90111, 0x8b10 },
+ { 0x90112, 0x168 },
+ { 0x90113, 0x0 },
+ { 0x90114, 0xab10 },
+ { 0x90115, 0x168 },
+ { 0x90116, 0x0 },
+ { 0x90117, 0x1d8 },
+ { 0x90118, 0x169 },
+ { 0x90119, 0x80 },
+ { 0x9011a, 0x790 },
+ { 0x9011b, 0x16a },
+ { 0x9011c, 0x18 },
+ { 0x9011d, 0x7aa },
+ { 0x9011e, 0x6a },
+ { 0x9011f, 0xa },
+ { 0x90120, 0x0 },
+ { 0x90121, 0x1e9 },
+ { 0x90122, 0x8 },
+ { 0x90123, 0x8080 },
+ { 0x90124, 0x108 },
+ { 0x90125, 0xf },
+ { 0x90126, 0x408 },
+ { 0x90127, 0x169 },
+ { 0x90128, 0xc },
+ { 0x90129, 0x0 },
+ { 0x9012a, 0x68 },
+ { 0x9012b, 0x9 },
+ { 0x9012c, 0x0 },
+ { 0x9012d, 0x1a9 },
+ { 0x9012e, 0x0 },
+ { 0x9012f, 0x408 },
+ { 0x90130, 0x169 },
+ { 0x90131, 0x0 },
+ { 0x90132, 0x8080 },
+ { 0x90133, 0x108 },
+ { 0x90134, 0x8 },
+ { 0x90135, 0x7aa },
+ { 0x90136, 0x6a },
+ { 0x90137, 0x0 },
+ { 0x90138, 0x8568 },
+ { 0x90139, 0x108 },
+ { 0x9013a, 0xb7 },
+ { 0x9013b, 0x790 },
+ { 0x9013c, 0x16a },
+ { 0x9013d, 0x1f },
+ { 0x9013e, 0x0 },
+ { 0x9013f, 0x68 },
+ { 0x90140, 0x8 },
+ { 0x90141, 0x8558 },
+ { 0x90142, 0x168 },
+ { 0x90143, 0xf },
+ { 0x90144, 0x408 },
+ { 0x90145, 0x169 },
+ { 0x90146, 0xd },
+ { 0x90147, 0x0 },
+ { 0x90148, 0x68 },
+ { 0x90149, 0x0 },
+ { 0x9014a, 0x408 },
+ { 0x9014b, 0x169 },
+ { 0x9014c, 0x0 },
+ { 0x9014d, 0x8558 },
+ { 0x9014e, 0x168 },
+ { 0x9014f, 0x8 },
+ { 0x90150, 0x3c8 },
+ { 0x90151, 0x1a9 },
+ { 0x90152, 0x3 },
+ { 0x90153, 0x370 },
+ { 0x90154, 0x129 },
+ { 0x90155, 0x20 },
+ { 0x90156, 0x2aa },
+ { 0x90157, 0x9 },
+ { 0x90158, 0x0 },
+ { 0x90159, 0x400 },
+ { 0x9015a, 0x10e },
+ { 0x9015b, 0x8 },
+ { 0x9015c, 0xe8 },
+ { 0x9015d, 0x109 },
+ { 0x9015e, 0x0 },
+ { 0x9015f, 0x8140 },
+ { 0x90160, 0x10c },
+ { 0x90161, 0x10 },
+ { 0x90162, 0x8138 },
+ { 0x90163, 0x10c },
+ { 0x90164, 0x8 },
+ { 0x90165, 0x7c8 },
+ { 0x90166, 0x101 },
+ { 0x90167, 0x8 },
+ { 0x90168, 0x448 },
+ { 0x90169, 0x109 },
+ { 0x9016a, 0xf },
+ { 0x9016b, 0x7c0 },
+ { 0x9016c, 0x109 },
+ { 0x9016d, 0x0 },
+ { 0x9016e, 0xe8 },
+ { 0x9016f, 0x109 },
+ { 0x90170, 0x47 },
+ { 0x90171, 0x630 },
+ { 0x90172, 0x109 },
+ { 0x90173, 0x8 },
+ { 0x90174, 0x618 },
+ { 0x90175, 0x109 },
+ { 0x90176, 0x8 },
+ { 0x90177, 0xe0 },
+ { 0x90178, 0x109 },
+ { 0x90179, 0x0 },
+ { 0x9017a, 0x7c8 },
+ { 0x9017b, 0x109 },
+ { 0x9017c, 0x8 },
+ { 0x9017d, 0x8140 },
+ { 0x9017e, 0x10c },
+ { 0x9017f, 0x0 },
+ { 0x90180, 0x1 },
+ { 0x90181, 0x8 },
+ { 0x90182, 0x8 },
+ { 0x90183, 0x4 },
+ { 0x90184, 0x8 },
+ { 0x90185, 0x8 },
+ { 0x90186, 0x7c8 },
+ { 0x90187, 0x101 },
+ { 0x90006, 0x0 },
+ { 0x90007, 0x0 },
+ { 0x90008, 0x8 },
+ { 0x90009, 0x0 },
+ { 0x9000a, 0x0 },
+ { 0x9000b, 0x0 },
+ { 0xd00e7, 0x400 },
+ { 0x90017, 0x0 },
+ { 0x9001f, 0x29 },
+ { 0x90026, 0x6a },
+ { 0x400d0, 0x0 },
+ { 0x400d1, 0x101 },
+ { 0x400d2, 0x105 },
+ { 0x400d3, 0x107 },
+ { 0x400d4, 0x10f },
+ { 0x400d5, 0x202 },
+ { 0x400d6, 0x20a },
+ { 0x400d7, 0x20b },
+ { 0x2003a, 0x2 },
+ { 0x2000b, 0x64 },
+ { 0x2000c, 0xc8 },
+ { 0x2000d, 0x7d0 },
+ { 0x2000e, 0x2c },
+ { 0x12000b, 0xc },
+ { 0x12000c, 0x19 },
+ { 0x12000d, 0xfa },
+ { 0x12000e, 0x10 },
+ { 0x22000b, 0x3 },
+ { 0x22000c, 0x6 },
+ { 0x22000d, 0x3e },
+ { 0x22000e, 0x10 },
+ { 0x9000c, 0x0 },
+ { 0x9000d, 0x173 },
+ { 0x9000e, 0x60 },
+ { 0x9000f, 0x6110 },
+ { 0x90010, 0x2152 },
+ { 0x90011, 0xdfbd },
+ { 0x90012, 0x2060 },
+ { 0x90013, 0x6152 },
+ { 0x20010, 0x5a },
+ { 0x20011, 0x3 },
+ { 0x120010, 0x5a },
+ { 0x120011, 0x3 },
+ { 0x220010, 0x5a },
+ { 0x220011, 0x3 },
+ { 0x40080, 0xe0 },
+ { 0x40081, 0x12 },
+ { 0x40082, 0xe0 },
+ { 0x40083, 0x12 },
+ { 0x40084, 0xe0 },
+ { 0x40085, 0x12 },
+ { 0x140080, 0xe0 },
+ { 0x140081, 0x12 },
+ { 0x140082, 0xe0 },
+ { 0x140083, 0x12 },
+ { 0x140084, 0xe0 },
+ { 0x140085, 0x12 },
+ { 0x240080, 0xe0 },
+ { 0x240081, 0x12 },
+ { 0x240082, 0xe0 },
+ { 0x240083, 0x12 },
+ { 0x240084, 0xe0 },
+ { 0x240085, 0x12 },
+ { 0x400fd, 0xf },
+ { 0x10011, 0x1 },
+ { 0x10012, 0x1 },
+ { 0x10013, 0x180 },
+ { 0x10018, 0x1 },
+ { 0x10002, 0x6209 },
+ { 0x100b2, 0x1 },
+ { 0x101b4, 0x1 },
+ { 0x102b4, 0x1 },
+ { 0x103b4, 0x1 },
+ { 0x104b4, 0x1 },
+ { 0x105b4, 0x1 },
+ { 0x106b4, 0x1 },
+ { 0x107b4, 0x1 },
+ { 0x108b4, 0x1 },
+ { 0x11011, 0x1 },
+ { 0x11012, 0x1 },
+ { 0x11013, 0x180 },
+ { 0x11018, 0x1 },
+ { 0x11002, 0x6209 },
+ { 0x110b2, 0x1 },
+ { 0x111b4, 0x1 },
+ { 0x112b4, 0x1 },
+ { 0x113b4, 0x1 },
+ { 0x114b4, 0x1 },
+ { 0x115b4, 0x1 },
+ { 0x116b4, 0x1 },
+ { 0x117b4, 0x1 },
+ { 0x118b4, 0x1 },
+ { 0x20089, 0x1 },
+ { 0x20088, 0x19 },
+ { 0xc0080, 0x2 },
+ { 0xd0000, 0x1 }
+};
+
+struct dram_fsp_msg ddr_dram_fsp_msg[] = {
+ {
+ /* P0 3200mts 1D */
+ .drate = 3200,
+ .fw_type = FW_1D_IMAGE,
+ .fsp_cfg = ddr_fsp0_cfg,
+ .fsp_cfg_num = ARRAY_SIZE(ddr_fsp0_cfg),
+ },
+ {
+ /* P1 400mts 1D */
+ .drate = 400,
+ .fw_type = FW_1D_IMAGE,
+ .fsp_cfg = ddr_fsp1_cfg,
+ .fsp_cfg_num = ARRAY_SIZE(ddr_fsp1_cfg),
+ },
+ {
+ /* P2 100mts 1D */
+ .drate = 100,
+ .fw_type = FW_1D_IMAGE,
+ .fsp_cfg = ddr_fsp2_cfg,
+ .fsp_cfg_num = ARRAY_SIZE(ddr_fsp2_cfg),
+ },
+ {
+ /* P0 3200mts 2D */
+ .drate = 3200,
+ .fw_type = FW_2D_IMAGE,
+ .fsp_cfg = ddr_fsp0_2d_cfg,
+ .fsp_cfg_num = ARRAY_SIZE(ddr_fsp0_2d_cfg),
+ },
+};
+
+/* ddr timing config params */
+struct dram_timing_info dram_timing = {
+ .ddrc_cfg = ddr_ddrc_cfg,
+ .ddrc_cfg_num = ARRAY_SIZE(ddr_ddrc_cfg),
+ .ddrphy_cfg = ddr_ddrphy_cfg,
+ .ddrphy_cfg_num = ARRAY_SIZE(ddr_ddrphy_cfg),
+ .fsp_msg = ddr_dram_fsp_msg,
+ .fsp_msg_num = ARRAY_SIZE(ddr_dram_fsp_msg),
+ .ddrphy_trained_csr = ddr_ddrphy_trained_csr,
+ .ddrphy_trained_csr_num = ARRAY_SIZE(ddr_ddrphy_trained_csr),
+ .ddrphy_pie = ddr_phy_pie,
+ .ddrphy_pie_num = ARRAY_SIZE(ddr_phy_pie),
+ .fsp_table = { 3200, 400, 100, },
+};
diff --git a/board/freescale/qemu-ppce500/Kconfig b/board/emulation/qemu-ppce500/Kconfig
similarity index 86%
rename from board/freescale/qemu-ppce500/Kconfig
rename to board/emulation/qemu-ppce500/Kconfig
index 236cd17..4312d98 100644
--- a/board/freescale/qemu-ppce500/Kconfig
+++ b/board/emulation/qemu-ppce500/Kconfig
@@ -4,7 +4,7 @@
default "qemu-ppce500"
config SYS_VENDOR
- default "freescale"
+ default "emulation"
config SYS_CONFIG_NAME
default "qemu-ppce500"
diff --git a/board/emulation/qemu-ppce500/MAINTAINERS b/board/emulation/qemu-ppce500/MAINTAINERS
new file mode 100644
index 0000000..7317983
--- /dev/null
+++ b/board/emulation/qemu-ppce500/MAINTAINERS
@@ -0,0 +1,7 @@
+QEMU-PPCE500 BOARD
+M: Alexander Graf <agraf@csgraf.de>
+M: Bin Meng <bmeng.cn@gmail.com>
+S: Maintained
+F: board/emulation/qemu-ppce500/
+F: include/configs/qemu-ppce500.h
+F: configs/qemu-ppce500_defconfig
diff --git a/board/freescale/qemu-ppce500/Makefile b/board/emulation/qemu-ppce500/Makefile
similarity index 100%
rename from board/freescale/qemu-ppce500/Makefile
rename to board/emulation/qemu-ppce500/Makefile
diff --git a/board/freescale/qemu-ppce500/qemu-ppce500.c b/board/emulation/qemu-ppce500/qemu-ppce500.c
similarity index 66%
rename from board/freescale/qemu-ppce500/qemu-ppce500.c
rename to board/emulation/qemu-ppce500/qemu-ppce500.c
index aa5774f..daa103c 100644
--- a/board/freescale/qemu-ppce500/qemu-ppce500.c
+++ b/board/emulation/qemu-ppce500/qemu-ppce500.c
@@ -1,11 +1,13 @@
// SPDX-License-Identifier: GPL-2.0+
/*
* Copyright 2007,2009-2014 Freescale Semiconductor, Inc.
+ * Copyright (C) 2021, Bin Meng <bmeng.cn@gmail.com>
*/
#include <common.h>
#include <command.h>
#include <cpu_func.h>
+#include <dm.h>
#include <env.h>
#include <init.h>
#include <log.h>
@@ -23,12 +25,17 @@
#include <fdtdec.h>
#include <errno.h>
#include <malloc.h>
+#include <virtio_types.h>
+#include <virtio.h>
DECLARE_GLOBAL_DATA_PTR;
static void *get_fdt_virt(void)
{
- return (void *)CONFIG_SYS_TMPVIRT;
+ if (gd->flags & GD_FLG_RELOC)
+ return (void *)gd->fdt_blob;
+ else
+ return (void *)CONFIG_SYS_TMPVIRT;
}
static uint64_t get_fdt_phys(void)
@@ -74,33 +81,14 @@
return r;
}
-int board_early_init_f(void)
-{
- return 0;
-}
-
int checkboard(void)
{
return 0;
}
-static int pci_map_region(void *fdt, int pci_node, int range_id,
- phys_size_t *ppaddr, pci_addr_t *pvaddr,
- pci_size_t *psize, ulong *pmap_addr)
+static int pci_map_region(phys_addr_t paddr, phys_size_t size, ulong *pmap_addr)
{
- uint64_t addr;
- uint64_t size;
ulong map_addr;
- int r;
-
- r = fdt_read_range(fdt, pci_node, range_id, NULL, &addr, &size);
- if (r)
- return r;
-
- if (ppaddr)
- *ppaddr = addr;
- if (psize)
- *psize = size;
if (!pmap_addr)
return 0;
@@ -115,90 +103,52 @@
return -1;
/* Map virtual memory for range */
- assert(!tlb_map_range(map_addr, addr, size, TLB_MAP_IO));
+ assert(!tlb_map_range(map_addr, paddr, size, TLB_MAP_IO));
*pmap_addr = map_addr + size;
- if (pvaddr)
- *pvaddr = map_addr;
-
return 0;
}
-void pci_init_board(void)
+int misc_init_r(void)
{
- struct pci_controller *pci_hoses;
- void *fdt = get_fdt_virt();
- int pci_node = -1;
- int pci_num = 0;
- int pci_count = 0;
+ struct udevice *dev;
+ struct pci_region *io;
+ struct pci_region *mem;
+ struct pci_region *pre;
ulong map_addr;
+ int ret;
- puts("\n");
+ /* Ensure PCI is probed */
+ uclass_first_device(UCLASS_PCI, &dev);
+
+ pci_get_regions(dev, &io, &mem, &pre);
/* Start MMIO and PIO range maps above RAM */
map_addr = CONFIG_SYS_PCI_MAP_START;
- /* Count and allocate PCI buses */
- pci_node = fdt_node_offset_by_prop_value(fdt, pci_node,
- "device_type", "pci", 4);
- while (pci_node != -FDT_ERR_NOTFOUND) {
- pci_node = fdt_node_offset_by_prop_value(fdt, pci_node,
- "device_type", "pci", 4);
- pci_count++;
- }
-
- if (pci_count) {
- pci_hoses = malloc(sizeof(struct pci_controller) * pci_count);
- } else {
- printf("PCI: disabled\n\n");
- return;
- }
-
- /* Spawn PCI buses based on device tree */
- pci_node = fdt_node_offset_by_prop_value(fdt, pci_node,
- "device_type", "pci", 4);
- while (pci_node != -FDT_ERR_NOTFOUND) {
- struct fsl_pci_info pci_info = { };
- const fdt32_t *reg;
- int r;
+ /* Map MMIO range */
+ ret = pci_map_region(mem->phys_start, mem->size, &map_addr);
+ if (ret)
+ return ret;
- reg = fdt_getprop(fdt, pci_node, "reg", NULL);
- pci_info.regs = fdt_translate_address(fdt, pci_node, reg);
+ /* Map PIO range */
+ ret = pci_map_region(io->phys_start, io->size, &map_addr);
+ if (ret)
+ return ret;
- /* Map MMIO range */
- r = pci_map_region(fdt, pci_node, 0, &pci_info.mem_phys, NULL,
- &pci_info.mem_size, &map_addr);
- if (r)
- break;
-
- /* Map PIO range */
- r = pci_map_region(fdt, pci_node, 1, &pci_info.io_phys, NULL,
- &pci_info.io_size, &map_addr);
- if (r)
- break;
-
- /*
- * The PCI framework finds virtual addresses for the buses
- * through our address map, so tell it the physical addresses.
- */
- pci_info.mem_bus = pci_info.mem_phys;
- pci_info.io_bus = pci_info.io_phys;
-
- /* Instantiate */
- pci_info.pci_num = pci_num + 1;
-
- fsl_setup_hose(&pci_hoses[pci_num], pci_info.regs);
- printf("PCI: base address %lx\n", pci_info.regs);
-
- fsl_pci_init_port(&pci_info, &pci_hoses[pci_num], pci_num);
+ /*
+ * Make sure virtio bus is enumerated so that peripherals
+ * on the virtio bus can be discovered by their drivers.
+ */
+ virtio_init();
- /* Jump to next PCI node */
- pci_node = fdt_node_offset_by_prop_value(fdt, pci_node,
- "device_type", "pci", 4);
- pci_num++;
- }
+ /*
+ * U-Boot is relocated to RAM already, let's delete the temporary FDT
+ * virtual-physical mapping that was used in the pre-relocation phase.
+ */
+ disable_tlb(find_tlb_idx((void *)CONFIG_SYS_TMPVIRT, 1));
- puts("\n");
+ return 0;
}
int last_stage_init(void)
@@ -219,9 +169,6 @@
if (prop && (len >= 8))
env_set_hex("qemu_kernel_addr", *prop);
- /* Give the user a variable for the host fdt */
- env_set_hex("fdt_addr_r", (ulong)fdt);
-
return 0;
}
@@ -241,30 +188,6 @@
panic("Couldn't determine RAM size");
}
-int board_eth_init(struct bd_info *bis)
-{
- return pci_eth_init(bis);
-}
-
-#if defined(CONFIG_OF_BOARD_SETUP)
-int ft_board_setup(void *blob, struct bd_info *bd)
-{
- FT_FSL_PCI_SETUP;
-
- return 0;
-}
-#endif
-
-void print_laws(void)
-{
- /* We don't emulate LAWs yet */
-}
-
-phys_size_t fixed_sdram(void)
-{
- return get_linear_ram_size();
-}
-
phys_size_t fsl_ddr_sdram_size(void)
{
return get_linear_ram_size();
@@ -303,11 +226,6 @@
1024 * 1024, TLB_MAP_RAM));
}
-void init_laws(void)
-{
- /* We don't emulate LAWs yet */
-}
-
static uint32_t get_cpu_freq(void)
{
void *fdt = get_fdt_virt();
@@ -380,3 +298,19 @@
{
return (1 << cpu_numcores()) - 1;
}
+
+/**
+ * Return the virtual address of FDT that was passed by QEMU
+ *
+ * @return virtual address of FDT received from QEMU in r3 register
+ */
+void *board_fdt_blob_setup(void)
+{
+ return get_fdt_virt();
+}
+
+/* See CONFIG_SYS_NS16550_CLK in arch/powerpc/include/asm/config.h */
+int get_serial_clock(void)
+{
+ return get_bus_freq(0);
+}
diff --git a/board/freescale/common/Kconfig b/board/freescale/common/Kconfig
index 1b1fd69..17db755 100644
--- a/board/freescale/common/Kconfig
+++ b/board/freescale/common/Kconfig
@@ -21,18 +21,37 @@
esbc_validate - validate signature using RSA verification
esbc_halt - put the core in spin loop (Secure Boot Only)
+config VID
+ depends on DM_I2C
+ bool "Enable Freescale VID"
+ help
+ This option enables setting core voltage based on individual
+ values saved in SoC fuses.
+
config VOL_MONITOR_LTC3882_READ
depends on VID
bool "Enable the LTC3882 voltage monitor read"
- default n
help
This option enables LTC3882 voltage monitor read
- functionality. It is used by common VID driver.
+ functionality. It is used by the common VID driver.
config VOL_MONITOR_LTC3882_SET
depends on VID
bool "Enable the LTC3882 voltage monitor set"
- default n
help
This option enables LTC3882 voltage monitor set
- functionality. It is used by common VID driver.
+ functionality. It is used by the common VID driver.
+
+config VOL_MONITOR_ISL68233_READ
+ depends on VID
+ bool "Enable the ISL68233 voltage monitor read"
+ help
+ This option enables ISL68233 voltage monitor read
+ functionality. It is used by the common VID driver.
+
+config VOL_MONITOR_ISL68233_SET
+ depends on VID
+ bool "Enable the ISL68233 voltage monitor set"
+ help
+ This option enables ISL68233 voltage monitor set
+ functionality. It is used by the common VID driver.
diff --git a/board/freescale/common/pq-mds-pib.c b/board/freescale/common/pq-mds-pib.c
index ae66039..596cd00 100644
--- a/board/freescale/common/pq-mds-pib.c
+++ b/board/freescale/common/pq-mds-pib.c
@@ -63,20 +63,7 @@
#endif
#if defined(CONFIG_PQ_MDS_PIB_ATM)
-#if defined(CONFIG_TARGET_MPC8569MDS)
- val8 = 0;
- i2c_write(0x20, 0x6, 1, &val8, 1);
- i2c_write(0x20, 0x7, 1, &val8, 1);
-
- val8 = 0xdf;
- i2c_write(0x20, 0x2, 1, &val8, 1);
- val8 = 0xf7;
- i2c_write(0x20, 0x3, 1, &val8, 1);
-
- eieio();
-
- printf("QOC3 ATM card on PMC0\n");
-#elif defined(CONFIG_TARGET_MPC832XEMDS)
+#if defined(CONFIG_TARGET_MPC832XEMDS)
val8 = 0;
i2c_write(0x26, 0x7, 1, &val8, 1);
val8 = 0xf7;
diff --git a/board/freescale/common/vid.c b/board/freescale/common/vid.c
index 20f5421..6e82962 100644
--- a/board/freescale/common/vid.c
+++ b/board/freescale/common/vid.c
@@ -2,6 +2,7 @@
/*
* Copyright 2014 Freescale Semiconductor, Inc.
* Copyright 2020 NXP
+ * Copyright 2020 Stephen Carlson <stcarlso@linux.microsoft.com>
*/
#include <common.h>
@@ -21,14 +22,22 @@
#include <linux/delay.h>
#include "vid.h"
+/* Voltages are generally handled in mV to keep them as integers */
+#define MV_PER_V 1000
+
+/*
+ * Select the channel on the I2C mux (on some NXP boards) that contains
+ * the voltage regulator to use for VID. Return 0 for success or nonzero
+ * for failure.
+ */
int __weak i2c_multiplexer_select_vid_channel(u8 channel)
{
return 0;
}
/*
- * Compensate for a board specific voltage drop between regulator and SoC
- * return a value in mV
+ * Compensate for a board specific voltage drop between regulator and SoC.
+ * Returns the voltage offset in mV.
*/
int __weak board_vdd_drop_compensation(void)
{
@@ -36,13 +45,94 @@
}
/*
- * Board specific settings for specific voltage value
+ * Performs any board specific adjustments after the VID voltage has been
+ * set. Return 0 for success or nonzero for failure.
*/
int __weak board_adjust_vdd(int vdd)
{
+ return 0;
+}
+
+/*
+ * Processor specific method of converting the fuse value read from VID
+ * registers into the core voltage to supply. Return the voltage in mV.
+ */
+u16 __weak soc_get_fuse_vid(int vid_index)
+{
+ /* Default VDD for Layerscape Chassis 1 devices */
+ static const u16 vdd[32] = {
+ 0, /* unused */
+ 9875, /* 0.9875V */
+ 9750,
+ 9625,
+ 9500,
+ 9375,
+ 9250,
+ 9125,
+ 9000,
+ 8875,
+ 8750,
+ 8625,
+ 8500,
+ 8375,
+ 8250,
+ 8125,
+ 10000, /* 1.0000V */
+ 10125,
+ 10250,
+ 10375,
+ 10500,
+ 10625,
+ 10750,
+ 10875,
+ 11000,
+ 0, /* reserved */
+ };
+ return vdd[vid_index];
+}
+
+#ifndef I2C_VOL_MONITOR_ADDR
+#define I2C_VOL_MONITOR_ADDR 0
+#endif
+
+#if CONFIG_IS_ENABLED(DM_I2C)
+#define DEVICE_HANDLE_T struct udevice *
+
+#ifndef I2C_VOL_MONITOR_BUS
+#define I2C_VOL_MONITOR_BUS 0
+#endif
+
+/* If DM is in use, retrieve the udevice chip for the specified bus number */
+static int vid_get_device(int address, DEVICE_HANDLE_T *dev)
+{
+ int ret = i2c_get_chip_for_busnum(I2C_VOL_MONITOR_BUS, address, 1, dev);
+
+ if (ret)
+ printf("VID: Bus %d has no device with address 0x%02X\n",
+ I2C_VOL_MONITOR_BUS, address);
+ return ret;
+}
+
+#define I2C_READ(dev, register, data, length) \
+ dm_i2c_read(dev, register, data, length)
+#define I2C_WRITE(dev, register, data, length) \
+ dm_i2c_write(dev, register, data, length)
+#else
+#define DEVICE_HANDLE_T int
+
+/* If DM is not in use, I2C addresses are passed directly */
+static int vid_get_device(int address, DEVICE_HANDLE_T *dev)
+{
+ *dev = address;
return 0;
}
+#define I2C_READ(dev, register, data, length) \
+ i2c_read(dev, register, 1, data, length)
+#define I2C_WRITE(dev, register, data, length) \
+ i2c_write(dev, register, 1, data, length)
+#endif
+
#if defined(CONFIG_VOL_MONITOR_IR36021_SET) || \
defined(CONFIG_VOL_MONITOR_IR36021_READ)
/*
@@ -60,30 +150,22 @@
*/
static int find_ir_chip_on_i2c(void)
{
- int i2caddress;
- int ret;
- u8 byte;
- int i;
+ int i2caddress, ret, i;
+ u8 mfrID;
const int ir_i2c_addr[] = {0x38, 0x08, 0x09};
-#if CONFIG_IS_ENABLED(DM_I2C)
- struct udevice *dev;
-#endif
+ DEVICE_HANDLE_T dev;
/* Check all the address */
for (i = 0; i < (sizeof(ir_i2c_addr)/sizeof(ir_i2c_addr[0])); i++) {
i2caddress = ir_i2c_addr[i];
-#if !CONFIG_IS_ENABLED(DM_I2C)
- ret = i2c_read(i2caddress,
- IR36021_MFR_ID_OFFSET, 1, (void *)&byte,
- sizeof(byte));
-#else
- ret = i2c_get_chip_for_busnum(0, i2caddress, 1, &dev);
- if (!ret)
- ret = dm_i2c_read(dev, IR36021_MFR_ID_OFFSET,
- (void *)&byte, sizeof(byte));
-#endif
- if ((ret >= 0) && (byte == IR36021_MFR_ID))
- return i2caddress;
+ ret = vid_get_device(i2caddress, &dev);
+ if (!ret) {
+ ret = I2C_READ(dev, IR36021_MFR_ID_OFFSET,
+ (void *)&mfrID, sizeof(mfrID));
+ /* If manufacturer ID matches the IR36021 */
+ if (!ret && mfrID == IR36021_MFR_ID)
+ return i2caddress;
+ }
}
return -1;
}
@@ -117,35 +199,33 @@
int i, ret, voltage_read = 0;
u16 vol_mon;
u8 buf[2];
-#if CONFIG_IS_ENABLED(DM_I2C)
- struct udevice *dev;
-#endif
+ DEVICE_HANDLE_T dev;
+
+ /* Open device handle */
+ ret = vid_get_device(i2caddress, &dev);
+ if (ret)
+ return ret;
for (i = 0; i < NUM_READINGS; i++) {
-#if !CONFIG_IS_ENABLED(DM_I2C)
- ret = i2c_read(I2C_VOL_MONITOR_ADDR,
- I2C_VOL_MONITOR_BUS_V_OFFSET, 1,
- (void *)&buf, 2);
-#else
- ret = i2c_get_chip_for_busnum(0, I2C_VOL_MONITOR_ADDR, 1, &dev);
- if (!ret)
- ret = dm_i2c_read(dev, I2C_VOL_MONITOR_BUS_V_OFFSET,
- (void *)&buf, 2);
-#endif
+ ret = I2C_READ(dev, I2C_VOL_MONITOR_BUS_V_OFFSET,
+ (void *)&buf[0], sizeof(buf));
if (ret) {
printf("VID: failed to read core voltage\n");
return ret;
}
+
vol_mon = (buf[0] << 8) | buf[1];
if (vol_mon & I2C_VOL_MONITOR_BUS_V_OVF) {
printf("VID: Core voltage sensor error\n");
return -1;
}
+
debug("VID: bus voltage reads 0x%04x\n", vol_mon);
/* LSB = 4mv */
voltage_read += (vol_mon >> I2C_VOL_MONITOR_BUS_V_SHIFT) * 4;
udelay(WAIT_FOR_ADC);
}
+
/* calculate the average */
voltage_read /= NUM_READINGS;
@@ -153,30 +233,25 @@
}
#endif
-/* read voltage from IR */
#ifdef CONFIG_VOL_MONITOR_IR36021_READ
+/* read voltage from IR */
static int read_voltage_from_IR(int i2caddress)
{
int i, ret, voltage_read = 0;
u16 vol_mon;
u8 buf;
-#if CONFIG_IS_ENABLED(DM_I2C)
- struct udevice *dev;
-#endif
+ DEVICE_HANDLE_T dev;
+
+ /* Open device handle */
+ ret = vid_get_device(i2caddress, &dev);
+ if (ret)
+ return ret;
for (i = 0; i < NUM_READINGS; i++) {
-#if !CONFIG_IS_ENABLED(DM_I2C)
- ret = i2c_read(i2caddress,
- IR36021_LOOP1_VOUT_OFFSET,
- 1, (void *)&buf, 1);
-#else
- ret = i2c_get_chip_for_busnum(0, i2caddress, 1, &dev);
- if (!ret)
- ret = dm_i2c_read(dev, IR36021_LOOP1_VOUT_OFFSET,
- (void *)&buf, 1);
-#endif
+ ret = I2C_READ(dev, IR36021_LOOP1_VOUT_OFFSET, (void *)&buf,
+ sizeof(buf));
if (ret) {
- printf("VID: failed to read vcpu\n");
+ printf("VID: failed to read core voltage\n");
return ret;
}
vol_mon = buf;
@@ -188,7 +263,7 @@
/* Resolution is 1/128V. We scale up here to get 1/128mV
* and divide at the end
*/
- voltage_read += vol_mon * 1000;
+ voltage_read += vol_mon * MV_PER_V;
udelay(WAIT_FOR_ADC);
}
/* Scale down to the real mV as IR resolution is 1/128V, rounding up */
@@ -206,49 +281,94 @@
}
#endif
-#ifdef CONFIG_VOL_MONITOR_LTC3882_READ
-/* read the current value of the LTC Regulator Voltage */
-static int read_voltage_from_LTC(int i2caddress)
+#if defined(CONFIG_VOL_MONITOR_ISL68233_READ) || \
+ defined(CONFIG_VOL_MONITOR_LTC3882_READ) || \
+ defined(CONFIG_VOL_MONITOR_ISL68233_SET) || \
+ defined(CONFIG_VOL_MONITOR_LTC3882_SET)
+
+/*
+ * The message displayed if the VOUT exponent causes a resolution
+ * worse than 1.0 V (if exponent is >= 0).
+ */
+#define VOUT_WARNING "VID: VOUT_MODE exponent has resolution worse than 1 V!\n"
+
+/* Checks the PMBus voltage monitor for the format used for voltage values */
+static int get_pmbus_multiplier(DEVICE_HANDLE_T dev)
{
- int ret, vcode = 0;
- u8 chan = PWM_CHANNEL0;
+ u8 mode;
+ int exponent, multiplier, ret;
-#if !CONFIG_IS_ENABLED(DM_I2C)
- /* select the PAGE 0 using PMBus commands PAGE for VDD*/
- ret = i2c_write(I2C_VOL_MONITOR_ADDR,
- PMBUS_CMD_PAGE, 1, &chan, 1);
-#else
- struct udevice *dev;
+ ret = I2C_READ(dev, PMBUS_CMD_VOUT_MODE, &mode, sizeof(mode));
+ if (ret) {
+ printf("VID: unable to determine voltage multiplier\n");
+ return 1;
+ }
+
+ /* Upper 3 bits is mode, lower 5 bits is exponent */
+ exponent = (int)mode & 0x1F;
+ mode >>= 5;
+ switch (mode) {
+ case 0:
+ /* Linear, 5 bit twos component exponent */
+ if (exponent & 0x10) {
+ multiplier = 1 << (16 - (exponent & 0xF));
+ } else {
+ /* If exponent is >= 0, then resolution is 1 V! */
+ printf(VOUT_WARNING);
+ multiplier = 1;
+ }
+ break;
+ case 1:
+ /* VID code identifier */
+ printf("VID: custom VID codes are not supported\n");
+ multiplier = MV_PER_V;
+ break;
+ default:
+ /* Direct, in mV */
+ multiplier = MV_PER_V;
+ break;
+ }
- ret = i2c_get_chip_for_busnum(0, I2C_VOL_MONITOR_ADDR, 1, &dev);
- if (!ret)
- ret = dm_i2c_write(dev, PMBUS_CMD_PAGE, &chan, 1);
+ debug("VID: calculated multiplier is %d\n", multiplier);
+ return multiplier;
+}
#endif
- if (ret) {
- printf("VID: failed to select VDD Page 0\n");
+
+#if defined(CONFIG_VOL_MONITOR_ISL68233_READ) || \
+ defined(CONFIG_VOL_MONITOR_LTC3882_READ)
+static int read_voltage_from_pmbus(int i2caddress)
+{
+ int ret, multiplier, vout;
+ u8 channel = PWM_CHANNEL0;
+ u16 vcode;
+ DEVICE_HANDLE_T dev;
+
+ /* Open device handle */
+ ret = vid_get_device(i2caddress, &dev);
+ if (ret)
return ret;
- }
-#if !CONFIG_IS_ENABLED(DM_I2C)
- /*read the output voltage using PMBus command READ_VOUT*/
- ret = i2c_read(I2C_VOL_MONITOR_ADDR,
- PMBUS_CMD_READ_VOUT, 1, (void *)&vcode, 2);
-#else
- ret = dm_i2c_read(dev, PMBUS_CMD_READ_VOUT, (void *)&vcode, 2);
+ /* Select the right page */
+ ret = I2C_WRITE(dev, PMBUS_CMD_PAGE, &channel, sizeof(channel));
if (ret) {
- printf("VID: failed to read the volatge\n");
+ printf("VID: failed to select VDD page %d\n", channel);
return ret;
}
-#endif
+
+ /* VOUT is little endian */
+ ret = I2C_READ(dev, PMBUS_CMD_READ_VOUT, (void *)&vcode, sizeof(vcode));
if (ret) {
- printf("VID: failed to read the volatge\n");
+ printf("VID: failed to read core voltage\n");
return ret;
}
- /* Scale down to the real mV as LTC resolution is 1/4096V,rounding up */
- vcode = DIV_ROUND_UP(vcode * 1000, 4096);
-
- return vcode;
+ /* Scale down to the real mV */
+ multiplier = get_pmbus_multiplier(dev);
+ vout = (int)vcode;
+ /* Multiplier 1000 (direct mode) requires no change to convert */
+ if (multiplier != MV_PER_V)
+ vout = DIV_ROUND_UP(vout * MV_PER_V, multiplier);
+ return vout - board_vdd_drop_compensation();
}
#endif
@@ -256,13 +376,14 @@
{
int voltage_read;
#ifdef CONFIG_VOL_MONITOR_INA220
- voltage_read = read_voltage_from_INA220(i2caddress);
+ voltage_read = read_voltage_from_INA220(I2C_VOL_MONITOR_ADDR);
#elif defined CONFIG_VOL_MONITOR_IR36021_READ
voltage_read = read_voltage_from_IR(i2caddress);
-#elif defined CONFIG_VOL_MONITOR_LTC3882_READ
- voltage_read = read_voltage_from_LTC(i2caddress);
+#elif defined(CONFIG_VOL_MONITOR_ISL68233_READ) || \
+ defined(CONFIG_VOL_MONITOR_LTC3882_READ)
+ voltage_read = read_voltage_from_pmbus(i2caddress);
#else
- return -1;
+ voltage_read = -1;
#endif
return voltage_read;
}
@@ -300,7 +421,7 @@
}
/*
- * this function keeps reading the voltage until it is stable or until the
+ * Blocks and reads the VID voltage until it stabilizes, or the
* timeout expires
*/
static int wait_for_voltage_stable(int i2caddress)
@@ -310,9 +431,9 @@
vdd = read_voltage(i2caddress);
udelay(NUM_READINGS * WAIT_FOR_ADC);
- /* wait until voltage is stable */
vdd_current = read_voltage(i2caddress);
- /* The maximum timeout is
+ /*
+ * The maximum timeout is
* MAX_LOOP_WAIT_VOL_STABLE * NUM_READINGS * WAIT_FOR_ADC
*/
for (timeout = MAX_LOOP_WAIT_VOL_STABLE;
@@ -327,12 +448,18 @@
return vdd_current;
}
-/* Set the voltage to the IR chip */
+/* Sets the VID voltage using the IR36021 */
static int set_voltage_to_IR(int i2caddress, int vdd)
{
int wait, vdd_last;
int ret;
u8 vid;
+ DEVICE_HANDLE_T dev;
+
+ /* Open device handle */
+ ret = vid_get_device(i2caddress, &dev);
+ if (ret)
+ return ret;
/* Compensate for a board specific voltage drop between regulator and
* SoC before converting into an IR VID value
@@ -344,20 +471,10 @@
vid = DIV_ROUND_UP(vdd - 245, 5);
#endif
-#if !CONFIG_IS_ENABLED(DM_I2C)
- ret = i2c_write(i2caddress, IR36021_LOOP1_MANUAL_ID_OFFSET,
- 1, (void *)&vid, sizeof(vid));
-#else
- struct udevice *dev;
-
- ret = i2c_get_chip_for_busnum(0, i2caddress, 1, &dev);
- if (!ret)
- ret = dm_i2c_write(dev, IR36021_LOOP1_MANUAL_ID_OFFSET,
- (void *)&vid, sizeof(vid));
-
-#endif
+ ret = I2C_WRITE(dev, IR36021_LOOP1_MANUAL_ID_OFFSET, (void *)&vid,
+ sizeof(vid));
if (ret) {
- printf("VID: failed to write VID\n");
+ printf("VID: failed to write new voltage\n");
return -1;
}
wait = wait_for_new_voltage(vdd, i2caddress);
@@ -371,81 +488,59 @@
debug("VID: Current voltage is %d mV\n", vdd_last);
return vdd_last;
}
-
#endif
-#ifdef CONFIG_VOL_MONITOR_LTC3882_SET
-/* this function sets the VDD and returns the value set */
-static int set_voltage_to_LTC(int i2caddress, int vdd)
+#if defined(CONFIG_VOL_MONITOR_ISL68233_SET) || \
+ defined(CONFIG_VOL_MONITOR_LTC3882_SET)
+static int set_voltage_to_pmbus(int i2caddress, int vdd)
{
int ret, vdd_last, vdd_target = vdd;
- int count = 100, temp = 0;
+ int count = MAX_LOOP_WAIT_NEW_VOL, temp = 0, multiplier;
unsigned char value;
- /* Scale up to the LTC resolution is 1/4096V */
- vdd = (vdd * 4096) / 1000;
+ /* The data to be sent with the PMBus command PAGE_PLUS_WRITE */
+ u8 buffer[5] = { 0x04, PWM_CHANNEL0, PMBUS_CMD_VOUT_COMMAND, 0, 0 };
+ DEVICE_HANDLE_T dev;
- /* 5-byte buffer which needs to be sent following the
- * PMBus command PAGE_PLUS_WRITE.
- */
- u8 buff[5] = {0x04, PWM_CHANNEL0, PMBUS_CMD_VOUT_COMMAND,
- vdd & 0xFF, (vdd & 0xFF00) >> 8};
+ /* Open device handle */
+ ret = vid_get_device(i2caddress, &dev);
+ if (ret)
+ return ret;
- /* Write the desired voltage code to the regulator */
-#if !CONFIG_IS_ENABLED(DM_I2C)
+ /* Scale up to the proper value for the VOUT command, little endian */
+ multiplier = get_pmbus_multiplier(dev);
+ vdd += board_vdd_drop_compensation();
+ if (multiplier != MV_PER_V)
+ vdd = DIV_ROUND_UP(vdd * multiplier, MV_PER_V);
+ buffer[3] = vdd & 0xFF;
+ buffer[4] = (vdd & 0xFF00) >> 8;
+
/* Check write protect state */
- ret = i2c_read(I2C_VOL_MONITOR_ADDR,
- PMBUS_CMD_WRITE_PROTECT, 1,
- (void *)&value, sizeof(value));
+ ret = I2C_READ(dev, PMBUS_CMD_WRITE_PROTECT, (void *)&value,
+ sizeof(value));
if (ret)
goto exit;
if (value != EN_WRITE_ALL_CMD) {
value = EN_WRITE_ALL_CMD;
- ret = i2c_write(I2C_VOL_MONITOR_ADDR,
- PMBUS_CMD_WRITE_PROTECT, 1,
+ ret = I2C_WRITE(dev, PMBUS_CMD_WRITE_PROTECT,
(void *)&value, sizeof(value));
if (ret)
goto exit;
}
- ret = i2c_write(I2C_VOL_MONITOR_ADDR,
- PMBUS_CMD_PAGE_PLUS_WRITE, 1,
- (void *)&buff, sizeof(buff));
-#else
- struct udevice *dev;
-
- ret = i2c_get_chip_for_busnum(0, I2C_VOL_MONITOR_ADDR, 1, &dev);
- if (!ret) {
- /* Check write protect state */
- ret = dm_i2c_read(dev,
- PMBUS_CMD_WRITE_PROTECT,
- (void *)&value, sizeof(value));
- if (ret)
- goto exit;
-
- if (value != EN_WRITE_ALL_CMD) {
- value = EN_WRITE_ALL_CMD;
- ret = dm_i2c_write(dev,
- PMBUS_CMD_WRITE_PROTECT,
- (void *)&value, sizeof(value));
- if (ret)
- goto exit;
- }
-
- ret = dm_i2c_write(dev, PMBUS_CMD_PAGE_PLUS_WRITE,
- (void *)&buff, sizeof(buff));
- }
-#endif
-exit:
+ /* Write the desired voltage code to the regulator */
+ ret = I2C_WRITE(dev, PMBUS_CMD_PAGE_PLUS_WRITE, (void *)&buffer[0],
+ sizeof(buffer));
if (ret) {
- printf("VID: I2C failed to write to the volatge regulator\n");
+ printf("VID: I2C failed to write to the voltage regulator\n");
return -1;
}
- /* Wait for the volatge to get to the desired value */
+exit:
+ /* Wait for the voltage to get to the desired value */
do {
- vdd_last = read_voltage_from_LTC(i2caddress);
+ vdd_last = read_voltage_from_pmbus(i2caddress);
if (vdd_last < 0) {
printf("VID: Couldn't read sensor abort VID adjust\n");
return -1;
@@ -464,325 +559,80 @@
#ifdef CONFIG_VOL_MONITOR_IR36021_SET
vdd_last = set_voltage_to_IR(i2caddress, vdd);
-#elif defined CONFIG_VOL_MONITOR_LTC3882_SET
- vdd_last = set_voltage_to_LTC(i2caddress, vdd);
+#elif defined(CONFIG_VOL_MONITOR_ISL68233_SET) || \
+ defined(CONFIG_VOL_MONITOR_LTC3882_SET)
+ vdd_last = set_voltage_to_pmbus(i2caddress, vdd);
#else
#error Specific voltage monitor must be defined
#endif
return vdd_last;
}
-#ifdef CONFIG_FSL_LSCH3
int adjust_vdd(ulong vdd_override)
{
int re_enable = disable_interrupts();
+#if defined(CONFIG_FSL_LSCH2) || defined(CONFIG_FSL_LSCH3)
struct ccsr_gur *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
- u32 fusesr;
-#if defined(CONFIG_VOL_MONITOR_IR36021_SET) || \
- defined(CONFIG_VOL_MONITOR_IR36021_READ)
- u8 vid, buf;
#else
- u8 vid;
+ ccsr_gur_t __iomem *gur =
+ (void __iomem *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
#endif
- int vdd_target, vdd_current, vdd_last;
- int ret, i2caddress = 0;
+ u8 vid;
+ u32 fusesr;
+ int vdd_current, vdd_last, vdd_target;
+ int ret, i2caddress = I2C_VOL_MONITOR_ADDR;
unsigned long vdd_string_override;
char *vdd_string;
-#if defined(CONFIG_ARCH_LX2160A) || defined(CONFIG_ARCH_LX2162A)
- static const u16 vdd[32] = {
- 8250,
- 7875,
- 7750,
- 0, /* reserved */
- 0, /* reserved */
- 0, /* reserved */
- 0, /* reserved */
- 0, /* reserved */
- 0, /* reserved */
- 0, /* reserved */
- 0, /* reserved */
- 0, /* reserved */
- 0, /* reserved */
- 0, /* reserved */
- 0, /* reserved */
- 0, /* reserved */
- 8000,
- 8125,
- 8250,
- 0, /* reserved */
- 8500,
- 0, /* reserved */
- 0, /* reserved */
- 0, /* reserved */
- 0, /* reserved */
- 0, /* reserved */
- 0, /* reserved */
- 0, /* reserved */
- 0, /* reserved */
- 0, /* reserved */
- 0, /* reserved */
- 0, /* reserved */
- };
-#else
-#ifdef CONFIG_ARCH_LS1088A
- static const uint16_t vdd[32] = {
- 10250,
- 9875,
- 9750,
- 0, /* reserved */
- 0, /* reserved */
- 0, /* reserved */
- 0, /* reserved */
- 0, /* reserved */
- 9000,
- 0, /* reserved */
- 0, /* reserved */
- 0, /* reserved */
- 0, /* reserved */
- 0, /* reserved */
- 0, /* reserved */
- 0, /* reserved */
- 10000, /* 1.0000V */
- 10125,
- 10250,
- 0, /* reserved */
- 0, /* reserved */
- 0, /* reserved */
- 0, /* reserved */
- 0, /* reserved */
- 0, /* reserved */
- 0, /* reserved */
- 0, /* reserved */
- 0, /* reserved */
- 0, /* reserved */
- 0, /* reserved */
- 0, /* reserved */
- 0, /* reserved */
- };
-
-#else
- static const uint16_t vdd[32] = {
- 10500,
- 0, /* reserved */
- 9750,
- 0, /* reserved */
- 9500,
- 0, /* reserved */
- 0, /* reserved */
- 0, /* reserved */
- 9000, /* reserved */
- 0, /* reserved */
- 0, /* reserved */
- 0, /* reserved */
- 0, /* reserved */
- 0, /* reserved */
- 0, /* reserved */
- 0, /* reserved */
- 10000, /* 1.0000V */
- 0, /* reserved */
- 10250,
- 0, /* reserved */
- 10500,
- 0, /* reserved */
- 0, /* reserved */
- 0, /* reserved */
- 0, /* reserved */
- 0, /* reserved */
- 0, /* reserved */
- 0, /* reserved */
- 0, /* reserved */
- 0, /* reserved */
- 0, /* reserved */
- 0, /* reserved */
- };
-#endif
-#endif
- struct vdd_drive {
- u8 vid;
- unsigned voltage;
- };
- ret = i2c_multiplexer_select_vid_channel(I2C_MUX_CH_VOL_MONITOR);
- if (ret) {
- debug("VID: I2C failed to switch channel\n");
- ret = -1;
- goto exit;
- }
#if defined(CONFIG_VOL_MONITOR_IR36021_SET) || \
defined(CONFIG_VOL_MONITOR_IR36021_READ)
- ret = find_ir_chip_on_i2c();
- if (ret < 0) {
- printf("VID: Could not find voltage regulator on I2C.\n");
- ret = -1;
- goto exit;
- } else {
- i2caddress = ret;
- debug("VID: IR Chip found on I2C address 0x%02x\n", i2caddress);
- }
-
- /* check IR chip work on Intel mode*/
-#if !CONFIG_IS_ENABLED(DM_I2C)
- ret = i2c_read(i2caddress,
- IR36021_INTEL_MODE_OOFSET,
- 1, (void *)&buf, 1);
-#else
- struct udevice *dev;
-
- ret = i2c_get_chip_for_busnum(0, i2caddress, 1, &dev);
- if (!ret)
- ret = dm_i2c_read(dev, IR36021_INTEL_MODE_OOFSET,
- (void *)&buf, 1);
-#endif
- if (ret) {
- printf("VID: failed to read IR chip mode.\n");
- ret = -1;
- goto exit;
- }
-
- if ((buf & IR36021_MODE_MASK) != IR36021_INTEL_MODE) {
- printf("VID: IR Chip is not used in Intel mode.\n");
- ret = -1;
- goto exit;
- }
+ u8 buf;
+ DEVICE_HANDLE_T dev;
#endif
- /* get the voltage ID from fuse status register */
+ /*
+ * VID is used according to the table below
+ * ---------------------------------------
+ * | DA_V |
+ * |-------------------------------------|
+ * | 5b00000 | 5b00001-5b11110 | 5b11111 |
+ * ---------------+---------+-----------------+---------|
+ * | D | 5b00000 | NO VID | VID = DA_V | NO VID |
+ * | A |----------+---------+-----------------+---------|
+ * | _ | 5b00001 |VID = | VID = |VID = |
+ * | V | ~ | DA_V_ALT| DA_V_ALT | DA_A_VLT|
+ * | _ | 5b11110 | | | |
+ * | A |----------+---------+-----------------+---------|
+ * | L | 5b11111 | No VID | VID = DA_V | NO VID |
+ * | T | | | | |
+ * ------------------------------------------------------
+ */
+#if defined(CONFIG_FSL_LSCH3)
fusesr = in_le32(&gur->dcfg_fusesr);
vid = (fusesr >> FSL_CHASSIS3_DCFG_FUSESR_ALTVID_SHIFT) &
- FSL_CHASSIS3_DCFG_FUSESR_ALTVID_MASK;
- if ((vid == 0) || (vid == FSL_CHASSIS3_DCFG_FUSESR_ALTVID_MASK)) {
+ FSL_CHASSIS3_DCFG_FUSESR_ALTVID_MASK;
+ if (vid == 0 || vid == FSL_CHASSIS3_DCFG_FUSESR_ALTVID_MASK) {
vid = (fusesr >> FSL_CHASSIS3_DCFG_FUSESR_VID_SHIFT) &
- FSL_CHASSIS3_DCFG_FUSESR_VID_MASK;
- }
- vdd_target = vdd[vid];
-
- /* check override variable for overriding VDD */
- vdd_string = env_get(CONFIG_VID_FLS_ENV);
- if (vdd_override == 0 && vdd_string &&
- !strict_strtoul(vdd_string, 10, &vdd_string_override))
- vdd_override = vdd_string_override;
-
- if (vdd_override >= VDD_MV_MIN && vdd_override <= VDD_MV_MAX) {
- vdd_target = vdd_override * 10; /* convert to 1/10 mV */
- debug("VDD override is %lu\n", vdd_override);
- } else if (vdd_override != 0) {
- printf("Invalid value.\n");
+ FSL_CHASSIS3_DCFG_FUSESR_VID_MASK;
}
-
- /* divide and round up by 10 to get a value in mV */
- vdd_target = DIV_ROUND_UP(vdd_target, 10);
- if (vdd_target == 0) {
- debug("VID: VID not used\n");
- ret = 0;
- goto exit;
- } else if (vdd_target < VDD_MV_MIN || vdd_target > VDD_MV_MAX) {
- /* Check vdd_target is in valid range */
- printf("VID: Target VID %d mV is not in range.\n",
- vdd_target);
- ret = -1;
- goto exit;
- } else {
- debug("VID: vid = %d mV\n", vdd_target);
- }
-
- /*
- * Read voltage monitor to check real voltage.
- */
- vdd_last = read_voltage(i2caddress);
- if (vdd_last < 0) {
- printf("VID: Couldn't read sensor abort VID adjustment\n");
- ret = -1;
- goto exit;
+#elif defined(CONFIG_FSL_LSCH2)
+ fusesr = in_be32(&gur->dcfg_fusesr);
+ vid = (fusesr >> FSL_CHASSIS2_DCFG_FUSESR_ALTVID_SHIFT) &
+ FSL_CHASSIS2_DCFG_FUSESR_ALTVID_MASK;
+ if (vid == 0 || vid == FSL_CHASSIS2_DCFG_FUSESR_ALTVID_MASK) {
+ vid = (fusesr >> FSL_CHASSIS2_DCFG_FUSESR_VID_SHIFT) &
+ FSL_CHASSIS2_DCFG_FUSESR_VID_MASK;
}
- vdd_current = vdd_last;
- debug("VID: Core voltage is currently at %d mV\n", vdd_last);
-
-#ifdef CONFIG_VOL_MONITOR_LTC3882_SET
- /* Set the target voltage */
- vdd_last = vdd_current = set_voltage(i2caddress, vdd_target);
#else
- /*
- * Adjust voltage to at or one step above target.
- * As measurements are less precise than setting the values
- * we may run through dummy steps that cancel each other
- * when stepping up and then down.
- */
- while (vdd_last > 0 &&
- vdd_last < vdd_target) {
- vdd_current += IR_VDD_STEP_UP;
- vdd_last = set_voltage(i2caddress, vdd_current);
- }
- while (vdd_last > 0 &&
- vdd_last > vdd_target + (IR_VDD_STEP_DOWN - 1)) {
- vdd_current -= IR_VDD_STEP_DOWN;
- vdd_last = set_voltage(i2caddress, vdd_current);
+ fusesr = in_be32(&gur->dcfg_fusesr);
+ vid = (fusesr >> FSL_CORENET_DCFG_FUSESR_ALTVID_SHIFT) &
+ FSL_CORENET_DCFG_FUSESR_ALTVID_MASK;
+ if (vid == 0 || vid == FSL_CORENET_DCFG_FUSESR_ALTVID_MASK) {
+ vid = (fusesr >> FSL_CORENET_DCFG_FUSESR_VID_SHIFT) &
+ FSL_CORENET_DCFG_FUSESR_VID_MASK;
}
-
#endif
- if (board_adjust_vdd(vdd_target) < 0) {
- ret = -1;
- goto exit;
- }
-
- if (vdd_last > 0)
- printf("VID: Core voltage after adjustment is at %d mV\n",
- vdd_last);
- else
- ret = -1;
-exit:
- if (re_enable)
- enable_interrupts();
- i2c_multiplexer_select_vid_channel(I2C_MUX_CH_DEFAULT);
- return ret;
-}
-#else /* !CONFIG_FSL_LSCH3 */
-int adjust_vdd(ulong vdd_override)
-{
- int re_enable = disable_interrupts();
-#if defined(CONFIG_FSL_LSCH2)
- struct ccsr_gur *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
-#else
- ccsr_gur_t __iomem *gur =
- (void __iomem *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
-#endif
- u32 fusesr;
- u8 vid, buf;
- int vdd_target, vdd_current, vdd_last;
- int ret, i2caddress;
- unsigned long vdd_string_override;
- char *vdd_string;
- static const uint16_t vdd[32] = {
- 0, /* unused */
- 9875, /* 0.9875V */
- 9750,
- 9625,
- 9500,
- 9375,
- 9250,
- 9125,
- 9000,
- 8875,
- 8750,
- 8625,
- 8500,
- 8375,
- 8250,
- 8125,
- 10000, /* 1.0000V */
- 10125,
- 10250,
- 10375,
- 10500,
- 10625,
- 10750,
- 10875,
- 11000,
- 0, /* reserved */
- };
- struct vdd_drive {
- u8 vid;
- unsigned voltage;
- };
+ vdd_target = soc_get_fuse_vid((int)vid);
ret = i2c_multiplexer_select_vid_channel(I2C_MUX_CH_VOL_MONITOR);
if (ret) {
@@ -790,6 +640,7 @@
ret = -1;
goto exit;
}
+
#if defined(CONFIG_VOL_MONITOR_IR36021_SET) || \
defined(CONFIG_VOL_MONITOR_IR36021_READ)
ret = find_ir_chip_on_i2c();
@@ -802,19 +653,13 @@
debug("VID: IR Chip found on I2C address 0x%02x\n", i2caddress);
}
- /* check IR chip work on Intel mode*/
-#if !CONFIG_IS_ENABLED(DM_I2C)
- ret = i2c_read(i2caddress,
- IR36021_INTEL_MODE_OOFSET,
- 1, (void *)&buf, 1);
-#else
- struct udevice *dev;
+ ret = vid_get_device(i2caddress, &dev);
+ if (ret)
+ return ret;
- ret = i2c_get_chip_for_busnum(0, i2caddress, 1, &dev);
- if (!ret)
- ret = dm_i2c_read(dev, IR36021_INTEL_MODE_OOFSET,
- (void *)&buf, 1);
-#endif
+ /* check IR chip work on Intel mode */
+ ret = I2C_READ(dev, IR36021_INTEL_MODE_OFFSET, (void *)&buf,
+ sizeof(buf));
if (ret) {
printf("VID: failed to read IR chip mode.\n");
ret = -1;
@@ -827,52 +672,18 @@
}
#endif
- /* get the voltage ID from fuse status register */
- fusesr = in_be32(&gur->dcfg_fusesr);
- /*
- * VID is used according to the table below
- * ---------------------------------------
- * | DA_V |
- * |-------------------------------------|
- * | 5b00000 | 5b00001-5b11110 | 5b11111 |
- * ---------------+---------+-----------------+---------|
- * | D | 5b00000 | NO VID | VID = DA_V | NO VID |
- * | A |----------+---------+-----------------+---------|
- * | _ | 5b00001 |VID = | VID = |VID = |
- * | V | ~ | DA_V_ALT| DA_V_ALT | DA_A_VLT|
- * | _ | 5b11110 | | | |
- * | A |----------+---------+-----------------+---------|
- * | L | 5b11111 | No VID | VID = DA_V | NO VID |
- * | T | | | | |
- * ------------------------------------------------------
- */
-#ifdef CONFIG_FSL_LSCH2
- vid = (fusesr >> FSL_CHASSIS2_DCFG_FUSESR_ALTVID_SHIFT) &
- FSL_CHASSIS2_DCFG_FUSESR_ALTVID_MASK;
- if ((vid == 0) || (vid == FSL_CHASSIS2_DCFG_FUSESR_ALTVID_MASK)) {
- vid = (fusesr >> FSL_CHASSIS2_DCFG_FUSESR_VID_SHIFT) &
- FSL_CHASSIS2_DCFG_FUSESR_VID_MASK;
- }
-#else
- vid = (fusesr >> FSL_CORENET_DCFG_FUSESR_ALTVID_SHIFT) &
- FSL_CORENET_DCFG_FUSESR_ALTVID_MASK;
- if ((vid == 0) || (vid == FSL_CORENET_DCFG_FUSESR_ALTVID_MASK)) {
- vid = (fusesr >> FSL_CORENET_DCFG_FUSESR_VID_SHIFT) &
- FSL_CORENET_DCFG_FUSESR_VID_MASK;
- }
-#endif
- vdd_target = vdd[vid];
-
/* check override variable for overriding VDD */
vdd_string = env_get(CONFIG_VID_FLS_ENV);
+ debug("VID: Initial VDD value is %d mV\n",
+ DIV_ROUND_UP(vdd_target, 10));
if (vdd_override == 0 && vdd_string &&
!strict_strtoul(vdd_string, 10, &vdd_string_override))
vdd_override = vdd_string_override;
if (vdd_override >= VDD_MV_MIN && vdd_override <= VDD_MV_MAX) {
vdd_target = vdd_override * 10; /* convert to 1/10 mV */
- debug("VDD override is %lu\n", vdd_override);
+ debug("VID: VDD override is %lu\n", vdd_override);
} else if (vdd_override != 0) {
- printf("Invalid value.\n");
+ printf("VID: Invalid VDD value.\n");
}
if (vdd_target == 0) {
debug("VID: VID not used\n");
@@ -895,6 +706,13 @@
}
vdd_current = vdd_last;
debug("VID: Core voltage is currently at %d mV\n", vdd_last);
+
+#if defined(CONFIG_VOL_MONITOR_LTC3882_SET) || \
+ defined(CONFIG_VOL_MONITOR_ISL68233_SET)
+ /* Set the target voltage */
+ vdd_current = set_voltage(i2caddress, vdd_target);
+ vdd_last = vdd_current;
+#else
/*
* Adjust voltage to at or one step above target.
* As measurements are less precise than setting the values
@@ -911,6 +729,13 @@
vdd_current -= IR_VDD_STEP_DOWN;
vdd_last = set_voltage(i2caddress, vdd_current);
}
+#endif
+
+ /* Board specific adjustments */
+ if (board_adjust_vdd(vdd_target) < 0) {
+ ret = -1;
+ goto exit;
+ }
if (vdd_last > 0)
printf("VID: Core voltage after adjustment is at %d mV\n",
@@ -925,11 +750,10 @@
return ret;
}
-#endif
static int print_vdd(void)
{
- int vdd_last, ret, i2caddress = 0;
+ int vdd_last, ret, i2caddress = I2C_VOL_MONITOR_ADDR;
ret = i2c_multiplexer_select_vid_channel(I2C_MUX_CH_VOL_MONITOR);
if (ret) {
diff --git a/board/freescale/common/vid.h b/board/freescale/common/vid.h
index 5bbaeca..b34c080b 100644
--- a/board/freescale/common/vid.h
+++ b/board/freescale/common/vid.h
@@ -7,16 +7,17 @@
#ifndef __VID_H_
#define __VID_H_
+/* IR36021 command codes */
#define IR36021_LOOP1_MANUAL_ID_OFFSET 0x6A
#define IR36021_LOOP1_VOUT_OFFSET 0x9A
#define IR36021_MFR_ID_OFFSET 0x92
#define IR36021_MFR_ID 0x43
-#define IR36021_INTEL_MODE_OOFSET 0x14
+#define IR36021_INTEL_MODE_OFFSET 0x14
#define IR36021_MODE_MASK 0x20
#define IR36021_INTEL_MODE 0x00
#define IR36021_AMD_MODE 0x20
-/* step the IR regulator in 5mV increments */
+/* Step the IR regulator in 5mV increments */
#define IR_VDD_STEP_DOWN 5
#define IR_VDD_STEP_UP 5
@@ -50,15 +51,16 @@
#define VDD_MV_MAX 925
#endif
-#if defined(CONFIG_TARGET_LX2160AQDS) || defined(CONFIG_TARGET_LX2162AQDS) || \
-defined(CONFIG_TARGET_LX2160ARDB)
/* PM Bus commands code for LTC3882*/
#define PWM_CHANNEL0 0x0
#define PMBUS_CMD_PAGE 0x0
#define PMBUS_CMD_READ_VOUT 0x8B
+#define PMBUS_CMD_VOUT_MODE 0x20
#define PMBUS_CMD_VOUT_COMMAND 0x21
#define PMBUS_CMD_PAGE_PLUS_WRITE 0x05
+#if defined(CONFIG_TARGET_LX2160AQDS) || defined(CONFIG_TARGET_LX2162AQDS) || \
+defined(CONFIG_TARGET_LX2160ARDB)
/* Voltage monitor on channel 2*/
#define I2C_VOL_MONITOR_BUS_V_OFFSET 0x2
#define I2C_VOL_MONITOR_BUS_V_OVF 0x1
@@ -68,5 +70,6 @@
#endif
int adjust_vdd(ulong vdd_override);
+u16 soc_get_fuse_vid(int vid_index);
#endif /* __VID_H_ */
diff --git a/board/freescale/corenet_ds/MAINTAINERS b/board/freescale/corenet_ds/MAINTAINERS
index e22cf70..f0da86a 100644
--- a/board/freescale/corenet_ds/MAINTAINERS
+++ b/board/freescale/corenet_ds/MAINTAINERS
@@ -19,9 +19,3 @@
F: configs/P5040DS_SDCARD_defconfig
F: configs/P5040DS_SPIFLASH_defconfig
F: configs/P5040DS_SECURE_BOOT_defconfig
-
-CORENET_DS_SECURE_BOOT BOARD
-M: Ruchika Gupta <ruchika.gupta@nxp.com>
-S: Maintained
-F: configs/P3041DS_NAND_SECURE_BOOT_defconfig
-F: configs/P5040DS_NAND_SECURE_BOOT_defconfig
diff --git a/board/freescale/ls1012afrdm/MAINTAINERS b/board/freescale/ls1012afrdm/MAINTAINERS
index 480b6bb..5fc7e93 100644
--- a/board/freescale/ls1012afrdm/MAINTAINERS
+++ b/board/freescale/ls1012afrdm/MAINTAINERS
@@ -1,5 +1,4 @@
LS1012AFRDM BOARD
-M: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
M: Rajesh Bhagat <rajesh.bhagat@nxp.com>
S: Maintained
F: board/freescale/ls1012afrdm/
@@ -10,12 +9,9 @@
F: configs/ls1012afrwy_tfa_SECURE_BOOT_defconfig
LS1012AFRWY BOARD
-M: Bhaskar Upadhaya <bhaskar.upadhaya@nxp.com>
+M: Pramod Kumar <pramod.kumar_1@nxp.com>
S: Maintained
F: board/freescale/ls1012afrwy/
F: include/configs/ls1012afrwy.h
F: configs/ls1012afrwy_qspi_defconfig
-
-M: Vinitha V Pillai <vinitha.pillai@nxp.com>
-S: Maintained
F: configs/ls1012afrwy_qspi_SECURE_BOOT_defconfig
diff --git a/board/freescale/ls1012aqds/MAINTAINERS b/board/freescale/ls1012aqds/MAINTAINERS
index dbd4670..c1bb8d5 100644
--- a/board/freescale/ls1012aqds/MAINTAINERS
+++ b/board/freescale/ls1012aqds/MAINTAINERS
@@ -1,6 +1,6 @@
LS1012AQDS BOARD
-M: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
M: Rajesh Bhagat <rajesh.bhagat@nxp.com>
+M: Pramod Kumar <pramod.kumar_1@nxp.com>
S: Maintained
F: board/freescale/ls1012aqds/
F: include/configs/ls1012aqds.h
diff --git a/board/freescale/ls1012ardb/MAINTAINERS b/board/freescale/ls1012ardb/MAINTAINERS
index 60e184d..b0c008b 100644
--- a/board/freescale/ls1012ardb/MAINTAINERS
+++ b/board/freescale/ls1012ardb/MAINTAINERS
@@ -1,6 +1,6 @@
LS1012ARDB BOARD
-M: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
M: Rajesh Bhagat <rajesh.bhagat@nxp.com>
+M: Pramod Kumar <pramod.kumar_1@nxp.com>
S: Maintained
F: board/freescale/ls1012ardb/
F: include/configs/ls1012ardb.h
@@ -8,13 +8,10 @@
F: configs/ls1012ardb_tfa_defconfig
F: configs/ls1012ardb_tfa_SECURE_BOOT_defconfig
F: configs/ls1012a2g5rdb_tfa_defconfig
-
-M: Sumit Garg <sumit.garg@nxp.com>
-S: Maintained
F: configs/ls1012ardb_qspi_SECURE_BOOT_defconfig
LS1012A2G5RDB BOARD
-M: Bhaskar Upadhaya <bhaskar.upadhaya@nxp.com>
+M: Pramod Kumar <pramod.kumar_1@nxp.com>
S: Maintained
F: board/freescale/ls1012ardb/
F: include/configs/ls1012a2g5rdb.h
diff --git a/board/freescale/ls1021aiot/MAINTAINERS b/board/freescale/ls1021aiot/MAINTAINERS
index 2dab798..65f21be 100644
--- a/board/freescale/ls1021aiot/MAINTAINERS
+++ b/board/freescale/ls1021aiot/MAINTAINERS
@@ -1,5 +1,5 @@
LS1021AIOT BOARD
-M: Feng Li <feng.li_2@nxp.com>
+M: Alison Wang <alison.wang@nxp.com>
S: Maintained
F: board/freescale/ls1021aiot/
F: include/configs/ls1021aiot.h
diff --git a/board/freescale/ls1021atwr/MAINTAINERS b/board/freescale/ls1021atwr/MAINTAINERS
index c8b93c6..7ab8347 100644
--- a/board/freescale/ls1021atwr/MAINTAINERS
+++ b/board/freescale/ls1021atwr/MAINTAINERS
@@ -9,7 +9,4 @@
F: configs/ls1021atwr_sdcard_ifc_defconfig
F: configs/ls1021atwr_sdcard_qspi_defconfig
F: configs/ls1021atwr_qspi_defconfig
-
-M: Sumit Garg <sumit.garg@nxp.com>
-S: Maintained
F: configs/ls1021atwr_sdcard_ifc_SECURE_BOOT_defconfig
diff --git a/board/freescale/ls1028a/MAINTAINERS b/board/freescale/ls1028a/MAINTAINERS
index 5b7a8db..9e7b069 100644
--- a/board/freescale/ls1028a/MAINTAINERS
+++ b/board/freescale/ls1028a/MAINTAINERS
@@ -1,6 +1,4 @@
LS1028AQDS BOARD
-M: Sudhanshu Gupta <sudhanshu.gupta@nxp.com>
-M: Rai Harninder <harninder.rai@nxp.com>
M: Rajesh Bhagat <rajesh.bhagat@nxp.com>
M: Tang Yuantian <andy.tang@nxp.com>
S: Maintained
@@ -11,8 +9,6 @@
F: configs/ls1028aqds_tfa_lpuart_defconfig
LS1028ARDB BOARD
-M: Sudhanshu Gupta <sudhanshu.gupta@nxp.com>
-M: Rai Harninder <harninder.rai@nxp.com>
M: Rajesh Bhagat <rajesh.bhagat@nxp.com>
M: Tang Yuantian <andy.tang@nxp.com>
S: Maintained
diff --git a/board/freescale/ls1043ardb/MAINTAINERS b/board/freescale/ls1043ardb/MAINTAINERS
index ed62396..36e7331 100644
--- a/board/freescale/ls1043ardb/MAINTAINERS
+++ b/board/freescale/ls1043ardb/MAINTAINERS
@@ -10,10 +10,6 @@
F: configs/ls1043ardb_sdcard_defconfig
F: configs/ls1043ardb_tfa_defconfig
F: configs/ls1043ardb_tfa_SECURE_BOOT_defconfig
-
-LS1043A_SECURE_BOOT BOARD
-M: Ruchika Gupta <ruchika.gupta@nxp.com>
-S: Maintained
F: configs/ls1043ardb_SECURE_BOOT_defconfig
F: configs/ls1043ardb_sdcard_SECURE_BOOT_defconfig
F: configs/ls1043ardb_nand_SECURE_BOOT_defconfig
diff --git a/board/freescale/ls1046aqds/MAINTAINERS b/board/freescale/ls1046aqds/MAINTAINERS
index 39a48da..72c4253 100644
--- a/board/freescale/ls1046aqds/MAINTAINERS
+++ b/board/freescale/ls1046aqds/MAINTAINERS
@@ -12,7 +12,4 @@
F: configs/ls1046aqds_lpuart_defconfig
F: configs/ls1046aqds_tfa_defconfig
F: configs/ls1046aqds_tfa_SECURE_BOOT_defconfig
-
-M: Sumit Garg <sumit.garg@nxp.com>
-S: Maintained
F: configs/ls1046aqds_SECURE_BOOT_defconfig
diff --git a/board/freescale/ls1046ardb/MAINTAINERS b/board/freescale/ls1046ardb/MAINTAINERS
index 8b4b45e..efdea22 100644
--- a/board/freescale/ls1046ardb/MAINTAINERS
+++ b/board/freescale/ls1046ardb/MAINTAINERS
@@ -11,13 +11,6 @@
F: configs/ls1046ardb_emmc_defconfig
F: configs/ls1046ardb_tfa_defconfig
F: configs/ls1046ardb_tfa_SECURE_BOOT_defconfig
-
-LS1046A_SECURE_BOOT BOARD
-M: Ruchika Gupta <ruchika.gupta@nxp.com>
-S: Maintained
F: configs/ls1046ardb_SECURE_BOOT_defconfig
F: configs/ls1046ardb_sdcard_SECURE_BOOT_defconfig
-
-M: Sumit Garg <sumit.garg@nxp.com>
-S: Maintained
F: configs/ls1046ardb_qspi_SECURE_BOOT_defconfig
diff --git a/board/freescale/ls1088a/MAINTAINERS b/board/freescale/ls1088a/MAINTAINERS
index 98ecb88e..5c7925a 100644
--- a/board/freescale/ls1088a/MAINTAINERS
+++ b/board/freescale/ls1088a/MAINTAINERS
@@ -1,5 +1,4 @@
LS1088ARDB BOARD
-M: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
M: Ashish Kumar <Ashish.Kumar@nxp.com>
M: Rajesh Bhagat <rajesh.bhagat@nxp.com>
S: Maintained
@@ -11,7 +10,6 @@
F: configs/ls1088ardb_tfa_SECURE_BOOT_defconfig
LS1088AQDS BOARD
-M: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
M: Ashish Kumar <Ashish.Kumar@nxp.com>
M: Rajesh Bhagat <rajesh.bhagat@nxp.com>
S: Maintained
@@ -25,17 +23,15 @@
LS1088AQDS_QSPI_SECURE_BOOT BOARD
M: Udit Agarwal <udit.agarwal@nxp.com>
-M: Vinitha Pillai-B57223 <vinitha.pillai@nxp.com>
S: Maintained
F: configs/ls1088aqds_qspi_SECURE_BOOT_defconfig
LS1088ARDB_QSPI_SECURE_BOOT BOARD
M: Udit Agarwal <udit.agarwal@nxp.com>
-M: Vinitha Pillai-B57223 <vinitha.pillai@nxp.com>
S: Maintained
F: configs/ls1088ardb_qspi_SECURE_BOOT_defconfig
LS1088ARDB_SD_SECURE_BOOT BOARD
-M: Sumit Garg <sumit.garg@nxp.com>
+M: Udit Agarwal <udit.agarwal@nxp.com>
S: Maintained
F: configs/ls1088ardb_sdcard_qspi_SECURE_BOOT_defconfig
diff --git a/board/freescale/ls1088a/ls1088a.c b/board/freescale/ls1088a/ls1088a.c
index e76ea01..f5dc449 100644
--- a/board/freescale/ls1088a/ls1088a.c
+++ b/board/freescale/ls1088a/ls1088a.c
@@ -186,6 +186,46 @@
return 0;
}
+
+u16 soc_get_fuse_vid(int vid_index)
+{
+ static const u16 vdd[32] = {
+ 10250,
+ 9875,
+ 9750,
+ 0, /* reserved */
+ 0, /* reserved */
+ 0, /* reserved */
+ 0, /* reserved */
+ 0, /* reserved */
+ 9000,
+ 0, /* reserved */
+ 0, /* reserved */
+ 0, /* reserved */
+ 0, /* reserved */
+ 0, /* reserved */
+ 0, /* reserved */
+ 0, /* reserved */
+ 10000, /* 1.0000V */
+ 10125,
+ 10250,
+ 0, /* reserved */
+ 0, /* reserved */
+ 0, /* reserved */
+ 0, /* reserved */
+ 0, /* reserved */
+ 0, /* reserved */
+ 0, /* reserved */
+ 0, /* reserved */
+ 0, /* reserved */
+ 0, /* reserved */
+ 0, /* reserved */
+ 0, /* reserved */
+ 0, /* reserved */
+ };
+
+ return vdd[vid_index];
+};
#endif
int is_pb_board(void)
diff --git a/board/freescale/ls2080aqds/MAINTAINERS b/board/freescale/ls2080aqds/MAINTAINERS
index e3d7635..84735dc 100644
--- a/board/freescale/ls2080aqds/MAINTAINERS
+++ b/board/freescale/ls2080aqds/MAINTAINERS
@@ -1,5 +1,5 @@
LS2080A BOARD
-M: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>, Priyanka Jain <priyanka.jain@nxp.com>
+M: Priyanka Jain <priyanka.jain@nxp.com>
M: Rajesh Bhagat <rajesh.bhagat@nxp.com>
S: Maintained
F: board/freescale/ls2080aqds/
@@ -10,8 +10,4 @@
F: configs/ls2080aqds_qspi_defconfig
F: configs/ls2080aqds_sdcard_defconfig
F: configs/ls2088aqds_tfa_defconfig
-
-LS2080A_SECURE_BOOT BOARD
-#M: Saksham Jain <saksham.jain@nxp.freescale.com>
-S: Orphan (since 2018-05)
F: configs/ls2080aqds_SECURE_BOOT_defconfig
diff --git a/board/freescale/ls2080ardb/MAINTAINERS b/board/freescale/ls2080ardb/MAINTAINERS
index 113b7ab..6e25b82 100644
--- a/board/freescale/ls2080ardb/MAINTAINERS
+++ b/board/freescale/ls2080ardb/MAINTAINERS
@@ -1,5 +1,5 @@
LS2080A BOARD
-M: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>, Priyanka Jain <priyanka.jain@nxp.com>
+M: Priyanka Jain <priyanka.jain@nxp.com>
S: Maintained
F: board/freescale/ls2080ardb/
F: board/freescale/ls2080a/ls2080ardb.c
@@ -21,8 +21,8 @@
F: configs/ls2081ardb_defconfig
LS2080A_SECURE_BOOT BOARD
-#M: Saksham Jain <saksham.jain@nxp.freescale.com>
-S: Orphan (since 2018-05)
+M: Udit Agarwal <udit.agarwal@nxp.com>
+S: Maintained
F: configs/ls2080ardb_SECURE_BOOT_defconfig
LS2088A_QSPI_SECURE_BOOT BOARD
diff --git a/board/freescale/ls2080ardb/ls2080ardb.c b/board/freescale/ls2080ardb/ls2080ardb.c
index c5ae02b..3a026b0 100644
--- a/board/freescale/ls2080ardb/ls2080ardb.c
+++ b/board/freescale/ls2080ardb/ls2080ardb.c
@@ -43,6 +43,48 @@
MUX_TYPE_DSPI,
};
+#ifdef CONFIG_VID
+u16 soc_get_fuse_vid(int vid_index)
+{
+ static const u16 vdd[32] = {
+ 10500,
+ 0, /* reserved */
+ 9750,
+ 0, /* reserved */
+ 9500,
+ 0, /* reserved */
+ 0, /* reserved */
+ 0, /* reserved */
+ 9000, /* reserved */
+ 0, /* reserved */
+ 0, /* reserved */
+ 0, /* reserved */
+ 0, /* reserved */
+ 0, /* reserved */
+ 0, /* reserved */
+ 0, /* reserved */
+ 10000, /* 1.0000V */
+ 0, /* reserved */
+ 10250,
+ 0, /* reserved */
+ 10500,
+ 0, /* reserved */
+ 0, /* reserved */
+ 0, /* reserved */
+ 0, /* reserved */
+ 0, /* reserved */
+ 0, /* reserved */
+ 0, /* reserved */
+ 0, /* reserved */
+ 0, /* reserved */
+ 0, /* reserved */
+ 0, /* reserved */
+ };
+
+ return vdd[vid_index];
+};
+#endif
+
unsigned long long get_qixis_addr(void)
{
unsigned long long addr;
diff --git a/board/freescale/lx2160a/MAINTAINERS b/board/freescale/lx2160a/MAINTAINERS
index c627417..cc69de2 100644
--- a/board/freescale/lx2160a/MAINTAINERS
+++ b/board/freescale/lx2160a/MAINTAINERS
@@ -16,7 +16,6 @@
LX2160AQDS BOARD
M: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com>
-M: Pankaj Bansal <pankaj.bansal@nxp.com>
S: Maintained
F: board/freescale/lx2160a/eth_lx2160aqds.h
F: include/configs/lx2160aqds.h
diff --git a/board/freescale/lx2160a/lx2160a.c b/board/freescale/lx2160a/lx2160a.c
index b32e487..47a7024 100644
--- a/board/freescale/lx2160a/lx2160a.c
+++ b/board/freescale/lx2160a/lx2160a.c
@@ -649,6 +649,48 @@
}
#endif
+#ifdef CONFIG_VID
+u16 soc_get_fuse_vid(int vid_index)
+{
+ static const u16 vdd[32] = {
+ 8250,
+ 7875,
+ 7750,
+ 0, /* reserved */
+ 0, /* reserved */
+ 0, /* reserved */
+ 0, /* reserved */
+ 0, /* reserved */
+ 0, /* reserved */
+ 0, /* reserved */
+ 0, /* reserved */
+ 0, /* reserved */
+ 0, /* reserved */
+ 0, /* reserved */
+ 0, /* reserved */
+ 0, /* reserved */
+ 8000,
+ 8125,
+ 8250,
+ 0, /* reserved */
+ 8500,
+ 0, /* reserved */
+ 0, /* reserved */
+ 0, /* reserved */
+ 0, /* reserved */
+ 0, /* reserved */
+ 0, /* reserved */
+ 0, /* reserved */
+ 0, /* reserved */
+ 0, /* reserved */
+ 0, /* reserved */
+ 0, /* reserved */
+ };
+
+ return vdd[vid_index];
+};
+#endif
+
#ifdef CONFIG_FSL_MC_ENET
extern int fdt_fixup_board_phy(void *fdt);
diff --git a/board/freescale/mpc8569mds/Kconfig b/board/freescale/mpc8569mds/Kconfig
deleted file mode 100644
index 4871857..0000000
--- a/board/freescale/mpc8569mds/Kconfig
+++ /dev/null
@@ -1,12 +0,0 @@
-if TARGET_MPC8569MDS
-
-config SYS_BOARD
- default "mpc8569mds"
-
-config SYS_VENDOR
- default "freescale"
-
-config SYS_CONFIG_NAME
- default "MPC8569MDS"
-
-endif
diff --git a/board/freescale/mpc8569mds/MAINTAINERS b/board/freescale/mpc8569mds/MAINTAINERS
deleted file mode 100644
index 9df3f3c..0000000
--- a/board/freescale/mpc8569mds/MAINTAINERS
+++ /dev/null
@@ -1,7 +0,0 @@
-MPC8569MDS BOARD
-M: Priyanka Jain <priyanka.jain@nxp.com>
-S: Maintained
-F: board/freescale/mpc8569mds/
-F: include/configs/MPC8569MDS.h
-F: configs/MPC8569MDS_defconfig
-F: configs/MPC8569MDS_ATM_defconfig
diff --git a/board/freescale/mpc8569mds/Makefile b/board/freescale/mpc8569mds/Makefile
deleted file mode 100644
index 45718df..0000000
--- a/board/freescale/mpc8569mds/Makefile
+++ /dev/null
@@ -1,11 +0,0 @@
-# SPDX-License-Identifier: GPL-2.0+
-#
-# Copyright 2004-2009 Freescale Semiconductor.
-# (C) Copyright 2001-2006
-# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
-
-obj-y += mpc8569mds.o
-obj-y += bcsr.o
-obj-y += ddr.o
-obj-y += law.o
-obj-y += tlb.o
diff --git a/board/freescale/mpc8569mds/README b/board/freescale/mpc8569mds/README
deleted file mode 100644
index 86c3ccd..0000000
--- a/board/freescale/mpc8569mds/README
+++ /dev/null
@@ -1,77 +0,0 @@
-Overview
---------
-MPC8569MDS is composed of two boards - PB (Processor Board) and PIB (Platform
-I/O Board). The mpc8569 PowerTM processor is mounted on PB board.
-
-Building U-Boot
------------
- make MPC8569MDS_config
- make
-
-Memory Map
-----------
-0x0000_0000 0x7fff_ffff DDR 2G
-0xa000_0000 0xbfff_ffff PCIe MEM 512MB
-0xe000_0000 0xe00f_ffff CCSRBAR 1M
-0xe280_0000 0xe2ff_ffff PCIe I/O 8M
-0xc000_0000 0xdfff_ffff SRIO 512MB
-0xf000_0000 0xf3ff_ffff SDRAM 64MB
-0xf800_0000 0xf800_7fff BCSR 32KB
-0xf800_8000 0xf800_ffff PIB (CS4) 32KB
-0xf801_0000 0xf801_7fff PIB (CS5) 32KB
-0xfe00_0000 0xffff_ffff Flash 32MB
-
-
-Flashing U-Boot Images
----------------
-
-Use the following commands to program U-Boot image into flash:
-
- => tftp 1000000 u-boot.bin
- => protect off all
- => erase fff80000 ffffffff
- => cp.b 1000000 fff80000 80000
-
-
-Setting the correct MAC addresses
------------------------
-The command - "mac", is introduced to set on-board system EEPROM in the format
-defined in board/freescale/common/sys_eeprom.c. we must set all 8 MAC
-addresses for the MPC8569MDS's 8 Ethernet ports and save it by "mac save" when
-we first get the board. The commands are as follows:
- => mac i NXID /* Set NXID to this EEPROM */
- => mac e 01 /* Set Errata, this value is not defined by hardware
- designer, we can set whatever we want */
- => mac n a0 /* Set Serial Number. This is not defined by hardware
- designer, we can set whatever we want */
- => mac date 090512080000 /* Set the date in YYMMDDhhmmss format */
-
- => mac p 8 /* Set the number of mac ports, it should be 8 */
- => mac 0 xx:xx:xx:xx:xx:xx /* xx:xx:xx:xx:xx:xx should be the real mac
- address, you can refer to the value on
- the sticker of the rear side of the board
- */
- .....
- => mac 7 xx:xx:xx:xx:xx:xx
- => mac read
- => mac save
-
-After resetting the board, the ethxaddrs will be filled with the mac addresses
-if such environment variables are blank(never been set before). If the ethxaddr
-has been set but we want to update it, we can use the following commands:
- => setenv ethxaddr /* x = "none",1,2,3,4,5,6,7 */
- => save
- => reset
-
-
-Programming the ucode to flash
----------------------------------
-MPC8569 doesn't have ROM in QE, so we must upload the microcode(ucode) to QE's
-IRAM so that the QE can work. The ucode binary can be downloaded from
-http://opensource.freescale.com/firmware/, and it must be programmed to
-the address 0xfff0000 in the flash. Otherwise, the QE can't work and uboot
-hangs at "Net:"
-
-
-Please note the above two steps(setting mac addresses and programming ucode) are
-very important to get the board booting up and working properly.
diff --git a/board/freescale/mpc8569mds/bcsr.c b/board/freescale/mpc8569mds/bcsr.c
deleted file mode 100644
index 9ed00f6..0000000
--- a/board/freescale/mpc8569mds/bcsr.c
+++ /dev/null
@@ -1,50 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * Copyright (C) 2009 Freescale Semiconductor, Inc.
- */
-
-#include <common.h>
-#include <flash.h>
-#include <asm/io.h>
-
-#include "bcsr.h"
-
-void enable_8569mds_flash_write(void)
-{
- setbits_8((u8 *)(CONFIG_SYS_BCSR_BASE + 17), BCSR17_FLASH_nWP);
-}
-
-void disable_8569mds_flash_write(void)
-{
- clrbits_8((u8 *)(CONFIG_SYS_BCSR_BASE + 17), BCSR17_FLASH_nWP);
-}
-
-void enable_8569mds_qe_uec(void)
-{
-#if defined(CONFIG_SYS_UCC_RGMII_MODE)
- setbits_8((u8 *)(CONFIG_SYS_BCSR_BASE + 7),
- BCSR7_UCC1_GETH_EN | BCSR7_UCC1_RGMII_EN);
- setbits_8((u8 *)(CONFIG_SYS_BCSR_BASE + 8),
- BCSR8_UCC2_GETH_EN | BCSR8_UCC2_RGMII_EN);
- setbits_8((u8 *)(CONFIG_SYS_BCSR_BASE + 9),
- BCSR9_UCC3_GETH_EN | BCSR9_UCC3_RGMII_EN);
- setbits_8((u8 *)(CONFIG_SYS_BCSR_BASE + 10),
- BCSR10_UCC4_GETH_EN | BCSR10_UCC4_RGMII_EN);
-#elif defined(CONFIG_SYS_UCC_RMII_MODE)
- /* Set UCC1-4 working at RMII mode */
- clrbits_8((u8 *)(CONFIG_SYS_BCSR_BASE + 7),
- BCSR7_UCC1_GETH_EN | BCSR7_UCC1_RGMII_EN);
- clrbits_8((u8 *)(CONFIG_SYS_BCSR_BASE + 8),
- BCSR8_UCC2_GETH_EN | BCSR8_UCC2_RGMII_EN);
- clrbits_8((u8 *)(CONFIG_SYS_BCSR_BASE + 9),
- BCSR9_UCC3_GETH_EN | BCSR9_UCC3_RGMII_EN);
- clrbits_8((u8 *)(CONFIG_SYS_BCSR_BASE + 10),
- BCSR10_UCC4_GETH_EN | BCSR10_UCC4_RGMII_EN);
- setbits_8((u8 *)(CONFIG_SYS_BCSR_BASE + 9), BCSR9_UCC3_RMII_EN);
-#endif
-}
-
-void disable_8569mds_brd_eeprom_write_protect(void)
-{
- clrbits_8((u8 *)(CONFIG_SYS_BCSR_BASE + 7), BCSR7_BRD_WRT_PROTECT);
-}
diff --git a/board/freescale/mpc8569mds/bcsr.h b/board/freescale/mpc8569mds/bcsr.h
deleted file mode 100644
index fee0fe7..0000000
--- a/board/freescale/mpc8569mds/bcsr.h
+++ /dev/null
@@ -1,71 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0+ */
-/*
- * Copyright (C) 2009 Freescale Semiconductor, Inc.
- */
-
-#ifndef __BCSR_H_
-#define __BCSR_H_
-
-#include <common.h>
-
-/* BCSR Bit definitions*/
-/****************************************/
-/* BCSR defines */
-/****************************************/
-#define BCSR6_UPC1_EN 0x80
-#define BCSR6_UPC1_POS_EN 0x40
-#define BCSR6_UPC1_ADDR_EN 0x20
-#define BCSR6_UPC1_DEV2 0x10
-#define BCSR6_SD_CARD_1BIT 0x08
-#define BCSR6_SD_CARD_4BITS 0x04
-#define BCSR6_TDM2G_EN 0x02
-#define BCSR6_UCC7_RMII_EN 0x01
-
-#define BCSR7_UCC1_GETH_EN 0x80
-#define BCSR7_UCC1_RGMII_EN 0x40
-#define BCSR7_UCC1_RTBI_EN 0x20
-#define BCSR7_GETHRST_MRVL 0x04
-#define BCSR7_BRD_WRT_PROTECT 0x02
-
-#define BCSR8_UCC2_GETH_EN 0x80
-#define BCSR8_UCC2_RGMII_EN 0x40
-#define BCSR8_UCC2_RTBI_EN 0x20
-#define BCSR8_UEM_MARVEL_RESET 0x02
-
-#define BCSR9_UCC3_GETH_EN 0x80
-#define BCSR9_UCC3_RGMII_EN 0x40
-#define BCSR9_UCC3_RTBI_EN 0x20
-#define BCSR9_UCC3_RMII_EN 0x10
-#define BCSR9_UCC3_UEM_MICREL 0x01
-
-#define BCSR10_UCC4_GETH_EN 0x80
-#define BCSR10_UCC4_RGMII_EN 0x40
-#define BCSR10_UCC4_RTBI_EN 0x20
-
-#define BCSR11_LED0 0x40
-#define BCSR11_LED1 0x20
-#define BCSR11_LED2 0x10
-
-#define BCSR12_UCC6_RMII_EN 0x20
-#define BCSR12_UCC8_RMII_EN 0x20
-
-#define BCSR15_SMII6_DIS 0x08
-#define BCSR15_SMII8_DIS 0x04
-#define BCSR15_QEUART_EN 0x01
-
-#define BCSR16_UPC1_DEV2 0x02
-
-#define BCSR17_nUSBEN 0x80
-#define BCSR17_nUSBLOWSPD 0x40
-#define BCSR17_USBVCC 0x20
-#define BCSR17_USBMODE 0x10
-#define BCSR17_FLASH_nWP 0x01
-
-/*BCSR Utils functions*/
-
-void enable_8569mds_flash_write(void);
-void disable_8569mds_flash_write(void);
-void enable_8569mds_qe_uec(void);
-void disable_8569mds_brd_eeprom_write_protect(void);
-
-#endif /* __BCSR_H_ */
diff --git a/board/freescale/mpc8569mds/ddr.c b/board/freescale/mpc8569mds/ddr.c
deleted file mode 100644
index d049611..0000000
--- a/board/freescale/mpc8569mds/ddr.c
+++ /dev/null
@@ -1,63 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0
-/*
- * Copyright 2009 Freescale Semiconductor, Inc.
- */
-
-#include <common.h>
-
-#include <fsl_ddr_sdram.h>
-#include <fsl_ddr_dimm_params.h>
-
-void fsl_ddr_board_options(memctl_options_t *popts,
- dimm_params_t *pdimm,
- unsigned int ctrl_num)
-{
- /*
- * Factors to consider for clock adjust:
- * - number of chips on bus
- * - position of slot
- * - DDR1 vs. DDR2?
- * - ???
- *
- * This needs to be determined on a board-by-board basis.
- * 0110 3/4 cycle late
- * 0111 7/8 cycle late
- */
- popts->clk_adjust = 4;
-
- /*
- * Factors to consider for CPO:
- * - frequency
- * - ddr1 vs. ddr2
- */
- popts->cpo_override = 0xff;
-
- /*
- * Factors to consider for write data delay:
- * - number of DIMMs
- *
- * 1 = 1/4 clock delay
- * 2 = 1/2 clock delay
- * 3 = 3/4 clock delay
- * 4 = 1 clock delay
- * 5 = 5/4 clock delay
- * 6 = 3/2 clock delay
- */
- popts->write_data_delay = 2;
-
- /*
- * Enable half drive strength
- */
- popts->half_strength_driver_enable = 1;
-
- /* Write leveling override */
- popts->wrlvl_en = 1;
- popts->wrlvl_override = 1;
- popts->wrlvl_sample = 0xa;
- popts->wrlvl_start = 0x4;
-
- /* Rtt and Rtt_W override */
- popts->rtt_override = 1;
- popts->rtt_override_value = DDR3_RTT_60_OHM;
- popts->rtt_wr_override_value = 0; /* Rtt_WR= dynamic ODT off */
-}
diff --git a/board/freescale/mpc8569mds/law.c b/board/freescale/mpc8569mds/law.c
deleted file mode 100644
index 35cdd75..0000000
--- a/board/freescale/mpc8569mds/law.c
+++ /dev/null
@@ -1,40 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * Copyright 2009-2011 Freescale Semiconductor, Inc.
- *
- * (C) Copyright 2000
- * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
- */
-
-#include <common.h>
-#include <asm/fsl_law.h>
-#include <asm/mmu.h>
-
-/*
- * LAW(Local Access Window) configuration:
- *
- *0) 0x0000_0000 0x7fff_ffff DDR 2G
- *1) 0xa000_0000 0xbfff_ffff PCIe MEM 512MB
- *-) 0xe000_0000 0xe00f_ffff CCSR 1M
- *2) 0xe280_0000 0xe2ff_ffff PCIe I/O 8M
- *3) 0xc000_0000 0xdfff_ffff SRIO 512MB
- *4.a) 0xf000_0000 0xf3ff_ffff SDRAM 64MB
- *4.b) 0xf800_0000 0xf800_7fff BCSR 32KB
- *4.c) 0xf800_8000 0xf800_ffff PIB (CS4) 32KB
- *4.d) 0xf801_0000 0xf801_7fff PIB (CS5) 32KB
- *4.e) 0xfe00_0000 0xffff_ffff Flash 32MB
- *
- *Notes:
- * CCSRBAR and L2-as-SRAM don't need a configured Local Access Window.
- * If flash is 8M at default position (last 8M), no LAW needed.
- *
- */
-
-struct law_entry law_table[] = {
-#ifndef CONFIG_SPD_EEPROM
- SET_LAW(CONFIG_SYS_DDR_SDRAM_BASE, LAW_SIZE_1G, LAW_TRGT_IF_DDR),
-#endif
- SET_LAW(CONFIG_SYS_BCSR_BASE_PHYS, LAW_SIZE_128M, LAW_TRGT_IF_LBC),
-};
-
-int num_law_entries = ARRAY_SIZE(law_table);
diff --git a/board/freescale/mpc8569mds/mpc8569mds.c b/board/freescale/mpc8569mds/mpc8569mds.c
deleted file mode 100644
index 1d2cffb..0000000
--- a/board/freescale/mpc8569mds/mpc8569mds.c
+++ /dev/null
@@ -1,590 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * Copyright 2009-2010 Freescale Semiconductor.
- *
- * (C) Copyright 2002 Scott McNutt <smcnutt@artesyncp.com>
- */
-
-#include <common.h>
-#include <console.h>
-#include <flash.h>
-#include <hwconfig.h>
-#include <init.h>
-#include <log.h>
-#include <pci.h>
-#include <asm/processor.h>
-#include <asm/mmu.h>
-#include <asm/cache.h>
-#include <asm/immap_85xx.h>
-#include <asm/fsl_pci.h>
-#include <fsl_ddr_sdram.h>
-#include <asm/fsl_serdes.h>
-#include <asm/io.h>
-#include <spd_sdram.h>
-#include <i2c.h>
-#include <ioports.h>
-#include <linux/delay.h>
-#include <linux/libfdt.h>
-#include <fdt_support.h>
-#include <fsl_esdhc.h>
-#include <phy.h>
-
-#include "bcsr.h"
-#if defined(CONFIG_PQ_MDS_PIB)
-#include "../common/pq-mds-pib.h"
-#endif
-
-const qe_iop_conf_t qe_iop_conf_tab[] = {
- /* QE_MUX_MDC */
- {2, 31, 1, 0, 1}, /* QE_MUX_MDC */
-
- /* QE_MUX_MDIO */
- {2, 30, 3, 0, 2}, /* QE_MUX_MDIO */
-
-#if defined(CONFIG_SYS_UCC_RGMII_MODE)
- /* UCC_1_RGMII */
- {2, 11, 2, 0, 1}, /* CLK12 */
- {0, 0, 1, 0, 3}, /* ENET1_TXD0_SER1_TXD0 */
- {0, 1, 1, 0, 3}, /* ENET1_TXD1_SER1_TXD1 */
- {0, 2, 1, 0, 1}, /* ENET1_TXD2_SER1_TXD2 */
- {0, 3, 1, 0, 2}, /* ENET1_TXD3_SER1_TXD3 */
- {0, 6, 2, 0, 3}, /* ENET1_RXD0_SER1_RXD0 */
- {0, 7, 2, 0, 1}, /* ENET1_RXD1_SER1_RXD1 */
- {0, 8, 2, 0, 2}, /* ENET1_RXD2_SER1_RXD2 */
- {0, 9, 2, 0, 2}, /* ENET1_RXD3_SER1_RXD3 */
- {0, 4, 1, 0, 2}, /* ENET1_TX_EN_SER1_RTS_B */
- {0, 12, 2, 0, 3}, /* ENET1_RX_DV_SER1_CTS_B */
- {2, 8, 2, 0, 1}, /* ENET1_GRXCLK */
- {2, 20, 1, 0, 2}, /* ENET1_GTXCLK */
-
- /* UCC_2_RGMII */
- {2, 16, 2, 0, 3}, /* CLK17 */
- {0, 14, 1, 0, 2}, /* ENET2_TXD0_SER2_TXD0 */
- {0, 15, 1, 0, 2}, /* ENET2_TXD1_SER2_TXD1 */
- {0, 16, 1, 0, 1}, /* ENET2_TXD2_SER2_TXD2 */
- {0, 17, 1, 0, 1}, /* ENET2_TXD3_SER2_TXD3 */
- {0, 20, 2, 0, 2}, /* ENET2_RXD0_SER2_RXD0 */
- {0, 21, 2, 0, 1}, /* ENET2_RXD1_SER2_RXD1 */
- {0, 22, 2, 0, 1}, /* ENET2_RXD2_SER2_RXD2 */
- {0, 23, 2, 0, 1}, /* ENET2_RXD3_SER2_RXD3 */
- {0, 18, 1, 0, 2}, /* ENET2_TX_EN_SER2_RTS_B */
- {0, 26, 2, 0, 3}, /* ENET2_RX_DV_SER2_CTS_B */
- {2, 3, 2, 0, 1}, /* ENET2_GRXCLK */
- {2, 2, 1, 0, 2}, /* ENET2_GTXCLK */
-
- /* UCC_3_RGMII */
- {2, 11, 2, 0, 1}, /* CLK12 */
- {0, 29, 1, 0, 2}, /* ENET3_TXD0_SER3_TXD0 */
- {0, 30, 1, 0, 3}, /* ENET3_TXD1_SER3_TXD1 */
- {0, 31, 1, 0, 2}, /* ENET3_TXD2_SER3_TXD2 */
- {1, 0, 1, 0, 3}, /* ENET3_TXD3_SER3_TXD3 */
- {1, 3, 2, 0, 3}, /* ENET3_RXD0_SER3_RXD0 */
- {1, 4, 2, 0, 1}, /* ENET3_RXD1_SER3_RXD1 */
- {1, 5, 2, 0, 2}, /* ENET3_RXD2_SER3_RXD2 */
- {1, 6, 2, 0, 3}, /* ENET3_RXD3_SER3_RXD3 */
- {1, 1, 1, 0, 1}, /* ENET3_TX_EN_SER3_RTS_B */
- {1, 9, 2, 0, 3}, /* ENET3_RX_DV_SER3_CTS_B */
- {2, 9, 2, 0, 2}, /* ENET3_GRXCLK */
- {2, 25, 1, 0, 2}, /* ENET3_GTXCLK */
-
- /* UCC_4_RGMII */
- {2, 16, 2, 0, 3}, /* CLK17 */
- {1, 12, 1, 0, 2}, /* ENET4_TXD0_SER4_TXD0 */
- {1, 13, 1, 0, 2}, /* ENET4_TXD1_SER4_TXD1 */
- {1, 14, 1, 0, 1}, /* ENET4_TXD2_SER4_TXD2 */
- {1, 15, 1, 0, 2}, /* ENET4_TXD3_SER4_TXD3 */
- {1, 18, 2, 0, 2}, /* ENET4_RXD0_SER4_RXD0 */
- {1, 19, 2, 0, 1}, /* ENET4_RXD1_SER4_RXD1 */
- {1, 20, 2, 0, 1}, /* ENET4_RXD2_SER4_RXD2 */
- {1, 21, 2, 0, 2}, /* ENET4_RXD3_SER4_RXD3 */
- {1, 16, 1, 0, 2}, /* ENET4_TX_EN_SER4_RTS_B */
- {1, 24, 2, 0, 3}, /* ENET4_RX_DV_SER4_CTS_B */
- {2, 17, 2, 0, 2}, /* ENET4_GRXCLK */
- {2, 24, 1, 0, 2}, /* ENET4_GTXCLK */
-
-#elif defined(CONFIG_SYS_UCC_RMII_MODE)
- /* UCC_1_RMII */
- {2, 15, 2, 0, 1}, /* CLK16 */
- {0, 0, 1, 0, 3}, /* ENET1_TXD0_SER1_TXD0 */
- {0, 1, 1, 0, 3}, /* ENET1_TXD1_SER1_TXD1 */
- {0, 6, 2, 0, 3}, /* ENET1_RXD0_SER1_RXD0 */
- {0, 7, 2, 0, 1}, /* ENET1_RXD1_SER1_RXD1 */
- {0, 4, 1, 0, 2}, /* ENET1_TX_EN_SER1_RTS_B */
- {0, 12, 2, 0, 3}, /* ENET1_RX_DV_SER1_CTS_B */
-
- /* UCC_2_RMII */
- {2, 15, 2, 0, 1}, /* CLK16 */
- {0, 14, 1, 0, 2}, /* ENET2_TXD0_SER2_TXD0 */
- {0, 15, 1, 0, 2}, /* ENET2_TXD1_SER2_TXD1 */
- {0, 20, 2, 0, 2}, /* ENET2_RXD0_SER2_RXD0 */
- {0, 21, 2, 0, 1}, /* ENET2_RXD1_SER2_RXD1 */
- {0, 18, 1, 0, 2}, /* ENET2_TX_EN_SER2_RTS_B */
- {0, 26, 2, 0, 3}, /* ENET2_RX_DV_SER2_CTS_B */
-
- /* UCC_3_RMII */
- {2, 15, 2, 0, 1}, /* CLK16 */
- {0, 29, 1, 0, 2}, /* ENET3_TXD0_SER3_TXD0 */
- {0, 30, 1, 0, 3}, /* ENET3_TXD1_SER3_TXD1 */
- {1, 3, 2, 0, 3}, /* ENET3_RXD0_SER3_RXD0 */
- {1, 4, 2, 0, 1}, /* ENET3_RXD1_SER3_RXD1 */
- {1, 1, 1, 0, 1}, /* ENET3_TX_EN_SER3_RTS_B */
- {1, 9, 2, 0, 3}, /* ENET3_RX_DV_SER3_CTS_B */
-
- /* UCC_4_RMII */
- {2, 15, 2, 0, 1}, /* CLK16 */
- {1, 12, 1, 0, 2}, /* ENET4_TXD0_SER4_TXD0 */
- {1, 13, 1, 0, 2}, /* ENET4_TXD1_SER4_TXD1 */
- {1, 18, 2, 0, 2}, /* ENET4_RXD0_SER4_RXD0 */
- {1, 19, 2, 0, 1}, /* ENET4_RXD1_SER4_RXD1 */
- {1, 16, 1, 0, 2}, /* ENET4_TX_EN_SER4_RTS_B */
- {1, 24, 2, 0, 3}, /* ENET4_RX_DV_SER4_CTS_B */
-#endif
-
- /* UART1 is muxed with QE PortF bit [9-12].*/
- {5, 12, 2, 0, 3}, /* UART1_SIN */
- {5, 9, 1, 0, 3}, /* UART1_SOUT */
- {5, 10, 2, 0, 3}, /* UART1_CTS_B */
- {5, 11, 1, 0, 2}, /* UART1_RTS_B */
-
- /* QE UART */
- {0, 19, 1, 0, 2}, /* QEUART_TX */
- {1, 17, 2, 0, 3}, /* QEUART_RX */
- {0, 25, 1, 0, 1}, /* QEUART_RTS */
- {1, 23, 2, 0, 1}, /* QEUART_CTS */
-
- /* QE USB */
- {5, 3, 1, 0, 1}, /* USB_OE */
- {5, 4, 1, 0, 2}, /* USB_TP */
- {5, 5, 1, 0, 2}, /* USB_TN */
- {5, 6, 2, 0, 2}, /* USB_RP */
- {5, 7, 2, 0, 1}, /* USB_RX */
- {5, 8, 2, 0, 1}, /* USB_RN */
- {2, 4, 2, 0, 2}, /* CLK5 */
-
- /* SPI Flash, M25P40 */
- {4, 27, 3, 0, 1}, /* SPI_MOSI */
- {4, 28, 3, 0, 1}, /* SPI_MISO */
- {4, 29, 3, 0, 1}, /* SPI_CLK */
- {4, 30, 1, 0, 0}, /* SPI_SEL, GPIO */
-
- {0, 0, 0, 0, QE_IOP_TAB_END} /* END of table */
-};
-
-void local_bus_init(void);
-
-int board_early_init_f (void)
-{
- /*
- * Initialize local bus.
- */
- local_bus_init ();
-
- enable_8569mds_flash_write();
-
-#ifdef CONFIG_QE
- enable_8569mds_qe_uec();
-#endif
-
-#if CONFIG_SYS_I2C2_OFFSET
- /* Enable I2C2 signals instead of SD signals */
- volatile struct ccsr_gur *gur;
- gur = (struct ccsr_gur *)(CONFIG_SYS_IMMR + 0xe0000);
- gur->plppar1 &= ~PLPPAR1_I2C_BIT_MASK;
- gur->plppar1 |= PLPPAR1_I2C2_VAL;
- gur->plpdir1 &= ~PLPDIR1_I2C_BIT_MASK;
- gur->plpdir1 |= PLPDIR1_I2C2_VAL;
-
- disable_8569mds_brd_eeprom_write_protect();
-#endif
-
- return 0;
-}
-
-int board_early_init_r(void)
-{
- const unsigned int flashbase = CONFIG_SYS_NAND_BASE;
- const u8 flash_esel = 0;
-
- /*
- * Remap Boot flash to caching-inhibited
- * so that flash can be erased properly.
- */
-
- /* Flush d-cache and invalidate i-cache of any FLASH data */
- flush_dcache();
- invalidate_icache();
-
- /* invalidate existing TLB entry for flash */
- disable_tlb(flash_esel);
-
- set_tlb(1, flashbase, CONFIG_SYS_NAND_BASE, /* tlb, epn, rpn */
- MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, /* perms, wimge */
- 0, flash_esel, /* ts, esel */
- BOOKE_PAGESZ_64M, 1); /* tsize, iprot */
-
- return 0;
-}
-
-int checkboard (void)
-{
- printf ("Board: 8569 MDS\n");
-
- return 0;
-}
-
-#if !defined(CONFIG_SPD_EEPROM)
-phys_size_t fixed_sdram(void)
-{
- struct ccsr_ddr __iomem *ddr =
- (struct ccsr_ddr __iomem *)CONFIG_SYS_FSL_DDR_ADDR;
- uint d_init;
-
- out_be32(&ddr->cs0_bnds, CONFIG_SYS_DDR_CS0_BNDS);
- out_be32(&ddr->cs0_config, CONFIG_SYS_DDR_CS0_CONFIG);
- out_be32(&ddr->timing_cfg_3, CONFIG_SYS_DDR_TIMING_3);
- out_be32(&ddr->timing_cfg_0, CONFIG_SYS_DDR_TIMING_0);
- out_be32(&ddr->timing_cfg_1, CONFIG_SYS_DDR_TIMING_1);
- out_be32(&ddr->timing_cfg_2, CONFIG_SYS_DDR_TIMING_2);
- out_be32(&ddr->sdram_cfg, CONFIG_SYS_DDR_SDRAM_CFG);
- out_be32(&ddr->sdram_cfg_2, CONFIG_SYS_DDR_SDRAM_CFG_2);
- out_be32(&ddr->sdram_mode, CONFIG_SYS_DDR_SDRAM_MODE);
- out_be32(&ddr->sdram_mode_2, CONFIG_SYS_DDR_SDRAM_MODE_2);
- out_be32(&ddr->sdram_interval, CONFIG_SYS_DDR_SDRAM_INTERVAL);
- out_be32(&ddr->sdram_data_init, CONFIG_SYS_DDR_DATA_INIT);
- out_be32(&ddr->sdram_clk_cntl, CONFIG_SYS_DDR_SDRAM_CLK_CNTL);
- out_be32(&ddr->timing_cfg_4, CONFIG_SYS_DDR_TIMING_4);
- out_be32(&ddr->timing_cfg_5, CONFIG_SYS_DDR_TIMING_5);
- out_be32(&ddr->ddr_zq_cntl, CONFIG_SYS_DDR_ZQ_CNTL);
- out_be32(&ddr->ddr_wrlvl_cntl, CONFIG_SYS_DDR_WRLVL_CNTL);
- out_be32(&ddr->sdram_cfg_2, CONFIG_SYS_DDR_SDRAM_CFG_2);
-#if defined (CONFIG_DDR_ECC)
- out_be32(&ddr->err_int_en, CONFIG_SYS_DDR_ERR_INT_EN);
- out_be32(&ddr->err_disable, CONFIG_SYS_DDR_ERR_DIS);
- out_be32(&ddr->err_sbe, CONFIG_SYS_DDR_SBE);
-#endif
- udelay(500);
-
- out_be32(&ddr->sdram_cfg, CONFIG_SYS_DDR_CONTROL);
-#if defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER)
- d_init = 1;
- debug("DDR - 1st controller: memory initializing\n");
- /*
- * Poll until memory is initialized.
- * 512 Meg at 400 might hit this 200 times or so.
- */
- while ((ddr->sdram_cfg_2 & (d_init << 4)) != 0) {
- udelay(1000);
- }
- debug("DDR: memory initialized\n\n");
- udelay(500);
-#endif
- return CONFIG_SYS_SDRAM_SIZE * 1024 * 1024;
-}
-#endif
-
-/*
- * Initialize Local Bus
- */
-void
-local_bus_init(void)
-{
- volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
- volatile fsl_lbc_t *lbc = LBC_BASE_ADDR;
-
- uint clkdiv;
- sys_info_t sysinfo;
-
- get_sys_info(&sysinfo);
- clkdiv = (lbc->lcrr & LCRR_CLKDIV) * 2;
-
- out_be32(&gur->lbiuiplldcr1, 0x00078080);
- if (clkdiv == 16)
- out_be32(&gur->lbiuiplldcr0, 0x7c0f1bf0);
- else if (clkdiv == 8)
- out_be32(&gur->lbiuiplldcr0, 0x6c0f1bf0);
- else if (clkdiv == 4)
- out_be32(&gur->lbiuiplldcr0, 0x5c0f1bf0);
-
- out_be32(&lbc->lcrr, (u32)in_be32(&lbc->lcrr)| 0x00030000);
-}
-
-static void fdt_board_disable_serial(void *blob, struct bd_info *bd,
- const char *alias)
-{
- const char *status = "disabled";
- int off;
- int err;
-
- off = fdt_path_offset(blob, alias);
- if (off < 0) {
- printf("WARNING: could not find %s alias: %s.\n", alias,
- fdt_strerror(off));
- return;
- }
-
- err = fdt_setprop(blob, off, "status", status, strlen(status) + 1);
- if (err) {
- printf("WARNING: could not set status for serial0: %s.\n",
- fdt_strerror(err));
- return;
- }
-}
-
-/*
- * Because of an erratum in prototype boards it is impossible to use eSDHC
- * without disabling UART0 (which makes it quite easy to 'brick' the board
- * by simply issung 'setenv hwconfig esdhc', and not able to interact with
- * U-Boot anylonger).
- *
- * So, but default we assume that the board is a prototype, which is a most
- * safe assumption. There is no way to determine board revision from a
- * register, so we use hwconfig.
- */
-
-static int prototype_board(void)
-{
- if (hwconfig_subarg("board", "rev", NULL))
- return hwconfig_subarg_cmp("board", "rev", "prototype");
- return 1;
-}
-
-static int esdhc_disables_uart0(void)
-{
- return prototype_board() ||
- hwconfig_subarg_cmp("esdhc", "mode", "4-bits");
-}
-
-static void fdt_board_fixup_qe_uart(void *blob, struct bd_info *bd)
-{
- u8 *bcsr = (u8 *)CONFIG_SYS_BCSR_BASE;
- const char *devtype = "serial";
- const char *compat = "ucc_uart";
- const char *clk = "brg9";
- u32 portnum = 0;
- int off = -1;
-
- if (!hwconfig("qe_uart"))
- return;
-
- if (hwconfig("esdhc") && esdhc_disables_uart0()) {
- printf("QE UART: won't enable with esdhc.\n");
- return;
- }
-
- fdt_board_disable_serial(blob, bd, "serial1");
-
- while (1) {
- const u32 *idx;
- int len;
-
- off = fdt_node_offset_by_compatible(blob, off, "ucc_geth");
- if (off < 0) {
- printf("WARNING: unable to fixup device tree for "
- "QE UART\n");
- return;
- }
-
- idx = fdt_getprop(blob, off, "cell-index", &len);
- if (!idx || len != sizeof(*idx) || *idx != fdt32_to_cpu(2))
- continue;
- break;
- }
-
- fdt_setprop(blob, off, "device_type", devtype, strlen(devtype) + 1);
- fdt_setprop(blob, off, "compatible", compat, strlen(compat) + 1);
- fdt_setprop(blob, off, "tx-clock-name", clk, strlen(clk) + 1);
- fdt_setprop(blob, off, "rx-clock-name", clk, strlen(clk) + 1);
- fdt_setprop(blob, off, "port-number", &portnum, sizeof(portnum));
-
- setbits_8(&bcsr[15], BCSR15_QEUART_EN);
-}
-
-#ifdef CONFIG_FSL_ESDHC
-
-int board_mmc_init(struct bd_info *bd)
-{
- struct ccsr_gur *gur = (struct ccsr_gur *)CONFIG_SYS_MPC85xx_GUTS_ADDR;
- u8 *bcsr = (u8 *)CONFIG_SYS_BCSR_BASE;
- u8 bcsr6 = BCSR6_SD_CARD_1BIT;
-
- if (!hwconfig("esdhc"))
- return 0;
-
- printf("Enabling eSDHC...\n"
- " For eSDHC to function, I2C2 ");
- if (esdhc_disables_uart0()) {
- printf("and UART0 should be disabled.\n");
- printf(" Redirecting stderr, stdout and stdin to UART1...\n");
- console_assign(stderr, "eserial1");
- console_assign(stdout, "eserial1");
- console_assign(stdin, "eserial1");
- printf("Switched to UART1 (initial log has been printed to "
- "UART0).\n");
-
- clrsetbits_be32(&gur->plppar1, PLPPAR1_UART0_BIT_MASK,
- PLPPAR1_ESDHC_4BITS_VAL);
- clrsetbits_be32(&gur->plpdir1, PLPDIR1_UART0_BIT_MASK,
- PLPDIR1_ESDHC_4BITS_VAL);
- bcsr6 |= BCSR6_SD_CARD_4BITS;
- } else {
- printf("should be disabled.\n");
- }
-
- /* Assign I2C2 signals to eSDHC. */
- clrsetbits_be32(&gur->plppar1, PLPPAR1_I2C_BIT_MASK,
- PLPPAR1_ESDHC_VAL);
- clrsetbits_be32(&gur->plpdir1, PLPDIR1_I2C_BIT_MASK,
- PLPDIR1_ESDHC_VAL);
-
- /* Mux I2C2 (and optionally UART0) signals to eSDHC. */
- setbits_8(&bcsr[6], bcsr6);
-
- return fsl_esdhc_mmc_init(bd);
-}
-
-static void fdt_board_fixup_esdhc(void *blob, struct bd_info *bd)
-{
- const char *status = "disabled";
- int off = -1;
-
- if (!hwconfig("esdhc"))
- return;
-
- if (esdhc_disables_uart0())
- fdt_board_disable_serial(blob, bd, "serial0");
-
- while (1) {
- const u32 *idx;
- int len;
-
- off = fdt_node_offset_by_compatible(blob, off, "fsl-i2c");
- if (off < 0)
- break;
-
- idx = fdt_getprop(blob, off, "cell-index", &len);
- if (!idx || len != sizeof(*idx))
- continue;
-
- if (*idx == 1) {
- fdt_setprop(blob, off, "status", status,
- strlen(status) + 1);
- break;
- }
- }
-
- if (hwconfig_subarg_cmp("esdhc", "mode", "4-bits")) {
- off = fdt_node_offset_by_compatible(blob, -1, "fsl,esdhc");
- if (off < 0) {
- printf("WARNING: could not find esdhc node\n");
- return;
- }
- fdt_delprop(blob, off, "sdhci,1-bit-only");
- }
-}
-#else
-static inline void fdt_board_fixup_esdhc(void *blob, struct bd_info *bd) {}
-#endif
-
-static void fdt_board_fixup_qe_usb(void *blob, struct bd_info *bd)
-{
- u8 *bcsr = (u8 *)CONFIG_SYS_BCSR_BASE;
-
- if (hwconfig_subarg_cmp("qe_usb", "speed", "low"))
- clrbits_8(&bcsr[17], BCSR17_nUSBLOWSPD);
- else
- setbits_8(&bcsr[17], BCSR17_nUSBLOWSPD);
-
- if (hwconfig_subarg_cmp("qe_usb", "mode", "peripheral")) {
- clrbits_8(&bcsr[17], BCSR17_USBVCC);
- clrbits_8(&bcsr[17], BCSR17_USBMODE);
- do_fixup_by_compat(blob, "fsl,mpc8569-qe-usb", "mode",
- "peripheral", sizeof("peripheral"), 1);
- } else {
- setbits_8(&bcsr[17], BCSR17_USBVCC);
- setbits_8(&bcsr[17], BCSR17_USBMODE);
- }
-
- clrbits_8(&bcsr[17], BCSR17_nUSBEN);
-}
-
-#ifdef CONFIG_PCI
-void pci_init_board(void)
-{
-#if defined(CONFIG_PQ_MDS_PIB)
- pib_init();
-#endif
-
- fsl_pcie_init_board(0);
-}
-#endif /* CONFIG_PCI */
-
-#if defined(CONFIG_OF_BOARD_SETUP)
-int ft_board_setup(void *blob, struct bd_info *bd)
-{
-#if defined(CONFIG_SYS_UCC_RMII_MODE)
- int nodeoff, off, err;
- unsigned int val;
- const u32 *ph;
- const u32 *index;
-
- /* fixup device tree for supporting rmii mode */
- nodeoff = -1;
- while ((nodeoff = fdt_node_offset_by_compatible(blob, nodeoff,
- "ucc_geth")) >= 0) {
- err = fdt_setprop_string(blob, nodeoff, "tx-clock-name",
- "clk16");
- if (err < 0) {
- printf("WARNING: could not set tx-clock-name %s.\n",
- fdt_strerror(err));
- break;
- }
-
- err = fdt_fixup_phy_connection(blob, nodeoff,
- PHY_INTERFACE_MODE_RMII);
-
- if (err < 0) {
- printf("WARNING: could not set phy-connection-type "
- "%s.\n", fdt_strerror(err));
- break;
- }
-
- index = fdt_getprop(blob, nodeoff, "cell-index", 0);
- if (index == NULL) {
- printf("WARNING: could not get cell-index of ucc\n");
- break;
- }
-
- ph = fdt_getprop(blob, nodeoff, "phy-handle", 0);
- if (ph == NULL) {
- printf("WARNING: could not get phy-handle of ucc\n");
- break;
- }
-
- off = fdt_node_offset_by_phandle(blob, *ph);
- if (off < 0) {
- printf("WARNING: could not get phy node %s.\n",
- fdt_strerror(err));
- break;
- }
-
- val = 0x7 + *index; /* RMII phy address starts from 0x8 */
-
- err = fdt_setprop(blob, off, "reg", &val, sizeof(u32));
- if (err < 0) {
- printf("WARNING: could not set reg for phy-handle "
- "%s.\n", fdt_strerror(err));
- break;
- }
- }
-#endif
- ft_cpu_setup(blob, bd);
-
- FT_FSL_PCI_SETUP;
-
- fdt_board_fixup_esdhc(blob, bd);
- fdt_board_fixup_qe_uart(blob, bd);
- fdt_board_fixup_qe_usb(blob, bd);
-
- return 0;
-}
-#endif
diff --git a/board/freescale/mpc8569mds/tlb.c b/board/freescale/mpc8569mds/tlb.c
deleted file mode 100644
index fdbac54..0000000
--- a/board/freescale/mpc8569mds/tlb.c
+++ /dev/null
@@ -1,94 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * Copyright 2009-2010 Freescale Semiconductor, Inc.
- *
- * (C) Copyright 2000
- * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
- */
-
-#include <common.h>
-#include <asm/mmu.h>
-
-struct fsl_e_tlb_entry tlb_table[] = {
- /* TLB 0 - for temp stack in cache */
- SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR, CONFIG_SYS_INIT_RAM_ADDR,
- MAS3_SX|MAS3_SW|MAS3_SR, 0,
- 0, 0, BOOKE_PAGESZ_4K, 0),
- SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 4 * 1024,
- CONFIG_SYS_INIT_RAM_ADDR + 4 * 1024,
- MAS3_SX|MAS3_SW|MAS3_SR, 0,
- 0, 0, BOOKE_PAGESZ_4K, 0),
- SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 8 * 1024,
- CONFIG_SYS_INIT_RAM_ADDR + 8 * 1024,
- MAS3_SX|MAS3_SW|MAS3_SR, 0,
- 0, 0, BOOKE_PAGESZ_4K, 0),
- SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 12 * 1024,
- CONFIG_SYS_INIT_RAM_ADDR + 12 * 1024,
- MAS3_SX|MAS3_SW|MAS3_SR, 0,
- 0, 0, BOOKE_PAGESZ_4K, 0),
-
- /* TLB 1 Initializations */
- /*
- * TLBe 0: 64M write-through, guarded
- * Out of reset this entry is only 4K.
- * 0xfc000000 32MB NAND FLASH (CS3)
- * 0xfe000000 32MB NOR FLASH (CS0)
- */
-#ifdef CONFIG_NAND_SPL
- SET_TLB_ENTRY(1, CONFIG_SYS_NAND_BASE, CONFIG_SYS_NAND_BASE,
- MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
- 0, 0, BOOKE_PAGESZ_1M, 1),
-#else
- SET_TLB_ENTRY(1, CONFIG_SYS_NAND_BASE, CONFIG_SYS_NAND_BASE,
- MAS3_SX|MAS3_SW|MAS3_SR, MAS2_W|MAS2_G,
- 0, 0, BOOKE_PAGESZ_64M, 1),
-#endif
- /*
- * TLBe 1: 256KB Non-cacheable, guarded
- * 0xf8000000 32K BCSR
- * 0xf8008000 32K PIB (CS4)
- * 0xf8010000 32K PIB (CS5)
- */
- SET_TLB_ENTRY(1, CONFIG_SYS_BCSR_BASE, CONFIG_SYS_BCSR_BASE_PHYS,
- MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
- 0, 1, BOOKE_PAGESZ_256K, 1),
-
- /*
- * TLBe 2: 256M Non-cacheable, guarded
- * 0xa00000000 256M PCIe MEM (lower half)
- */
- SET_TLB_ENTRY(1, CONFIG_SYS_PCIE1_MEM_VIRT, CONFIG_SYS_PCIE1_MEM_PHYS,
- MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
- 0, 2, BOOKE_PAGESZ_256M, 1),
-
- /*
- * TLBe 3: 256M Non-cacheable, guarded
- * 0xb00000000 256M PCIe MEM (higher half)
- */
- SET_TLB_ENTRY(1, (CONFIG_SYS_PCIE1_MEM_VIRT + 0x10000000),
- (CONFIG_SYS_PCIE1_MEM_PHYS + 0x10000000),
- MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
- 0, 3, BOOKE_PAGESZ_256M, 1),
-
- /*
- * TLBe 4: 64M Non-cacheable, guarded
- * 0xe000_0000 1M CCSRBAR
- * 0xe280_0000 8M PCIe IO
- */
- SET_TLB_ENTRY(1, CONFIG_SYS_CCSRBAR, CONFIG_SYS_CCSRBAR_PHYS,
- MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
- 0, 4, BOOKE_PAGESZ_64M, 1),
-
-#if defined(CONFIG_SYS_RAMBOOT) && defined(CONFIG_SYS_INIT_L2_ADDR)
- /* *I*G - L2SRAM */
- SET_TLB_ENTRY(1, CONFIG_SYS_INIT_L2_ADDR, CONFIG_SYS_INIT_L2_ADDR_PHYS,
- MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
- 0, 5, BOOKE_PAGESZ_256K, 1),
- SET_TLB_ENTRY(1, CONFIG_SYS_INIT_L2_ADDR + 0x40000,
- CONFIG_SYS_INIT_L2_ADDR_PHYS + 0x40000,
- MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
- 0, 6, BOOKE_PAGESZ_256K, 1),
-#endif
-};
-
-int num_tlb_entries = ARRAY_SIZE(tlb_table);
diff --git a/board/freescale/mx23evk/MAINTAINERS b/board/freescale/mx23evk/MAINTAINERS
index b03ad6a..122b70c 100644
--- a/board/freescale/mx23evk/MAINTAINERS
+++ b/board/freescale/mx23evk/MAINTAINERS
@@ -1,6 +1,8 @@
MX23EVK BOARD
+M: Fabio Estevam <festevam@gmail.com>
M: Otavio Salvador <otavio@ossystems.com.br>
S: Maintained
F: board/freescale/mx23evk/
+F: arch/arm/dts/imx23-evk.dts
F: include/configs/mx23evk.h
F: configs/mx23evk_defconfig
diff --git a/board/freescale/mx23evk/mx23evk.c b/board/freescale/mx23evk/mx23evk.c
index 605cdec..df4fb39 100644
--- a/board/freescale/mx23evk/mx23evk.c
+++ b/board/freescale/mx23evk/mx23evk.c
@@ -54,26 +54,3 @@
return 0;
}
-
-#ifdef CONFIG_CMD_MMC
-static int mx23evk_mmc_wp(int id)
-{
- if (id != 0) {
- printf("MXS MMC: Invalid card selected (card id = %d)\n", id);
- return 1;
- }
-
- return gpio_get_value(MX23_PAD_PWM4__GPIO_1_30);
-}
-
-int board_mmc_init(struct bd_info *bis)
-{
- /* Configure WP as input */
- gpio_direction_input(MX23_PAD_PWM4__GPIO_1_30);
-
- /* Configure MMC0 Power Enable */
- gpio_direction_output(MX23_PAD_PWM3__GPIO_1_29, 0);
-
- return mxsmmc_initialize(bis, 0, mx23evk_mmc_wp, NULL);
-}
-#endif
diff --git a/board/freescale/mx25pdk/Kconfig b/board/freescale/mx25pdk/Kconfig
deleted file mode 100644
index af06b4c..0000000
--- a/board/freescale/mx25pdk/Kconfig
+++ /dev/null
@@ -1,15 +0,0 @@
-if TARGET_MX25PDK
-
-config SYS_BOARD
- default "mx25pdk"
-
-config SYS_VENDOR
- default "freescale"
-
-config SYS_SOC
- default "mx25"
-
-config SYS_CONFIG_NAME
- default "mx25pdk"
-
-endif
diff --git a/board/freescale/mx25pdk/MAINTAINERS b/board/freescale/mx25pdk/MAINTAINERS
deleted file mode 100644
index fa4651e..0000000
--- a/board/freescale/mx25pdk/MAINTAINERS
+++ /dev/null
@@ -1,6 +0,0 @@
-MX25PDK BOARD
-M: Fabio Estevam <fabio.estevam@nxp.com>
-S: Maintained
-F: board/freescale/mx25pdk/
-F: include/configs/mx25pdk.h
-F: configs/mx25pdk_defconfig
diff --git a/board/freescale/mx25pdk/Makefile b/board/freescale/mx25pdk/Makefile
deleted file mode 100644
index d3697d3..0000000
--- a/board/freescale/mx25pdk/Makefile
+++ /dev/null
@@ -1,7 +0,0 @@
-# SPDX-License-Identifier: GPL-2.0+
-#
-# Copyright (C) 2007, Guennadi Liakhovetski <lg@denx.de>
-#
-# (C) Copyright 2011 Freescale Semiconductor, Inc.
-
-obj-y := mx25pdk.o
diff --git a/board/freescale/mx25pdk/imximage.cfg b/board/freescale/mx25pdk/imximage.cfg
deleted file mode 100644
index 762ccd0..0000000
--- a/board/freescale/mx25pdk/imximage.cfg
+++ /dev/null
@@ -1,64 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0+ */
-/*
- * (C) Copyright 2009
- * Stefano Babic DENX Software Engineering sbabic@denx.de.
- *
- * Refer doc/imx/mkimage/imximage.txt for more details about how-to configure
- * and create imximage boot image
- *
- * The syntax is taken as close as possible with the kwbimage
- */
-
-/*
- * Boot Device : one of
- * spi, sd (the board has no nand neither onenand)
- */
-BOOT_FROM sd
-
-/*
- * Device Configuration Data (DCD)
- *
- * Each entry must have the format:
- * Addr-type Address Value
- *
- * where:
- * Addr-type register length (1,2 or 4 bytes)
- * Address absolute address of the register
- * value value to be stored in the register
- */
-/* EIM config-CS5 init -- CPLD */
-DATA 4 0xB8002050 0x0000D843
-DATA 4 0xB8002054 0x22252521
-DATA 4 0xB8002058 0x22220A00
-
-/* DDR2 init */
-DATA 4 0xB8001004 0x0076E83A
-DATA 4 0xB8001010 0x00000204
-DATA 4 0xB8001000 0x92210000
-DATA 4 0x80000f00 0x12344321
-DATA 4 0xB8001000 0xB2210000
-DATA 1 0x82000000 0xda
-DATA 1 0x83000000 0xda
-DATA 1 0x81000400 0xda
-DATA 1 0x80000333 0xda
-
-DATA 4 0xB8001000 0x92210000
-DATA 1 0x80000400 0x12345678
-
-DATA 4 0xB8001000 0xA2210000
-DATA 4 0x80000000 0x87654321
-DATA 4 0x80000000 0x87654321
-
-DATA 4 0xB8001000 0xB2210000
-DATA 1 0x80000233 0xda
-DATA 1 0x81000780 0xda
-DATA 1 0x81000400 0xda
-DATA 4 0xB8001000 0x82216080
-DATA 4 0x43FAC454 0x00001000
-
-DATA 4 0x53F80008 0x20034000
-
-/* Enable the clocks */
-DATA 4 0x53f8000c 0x1fffffff
-DATA 4 0x53f80010 0xffffffff
-DATA 4 0x53f80014 0xfdfff
diff --git a/board/freescale/mx25pdk/mx25pdk.c b/board/freescale/mx25pdk/mx25pdk.c
deleted file mode 100644
index 3b445a4..0000000
--- a/board/freescale/mx25pdk/mx25pdk.c
+++ /dev/null
@@ -1,199 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * (C) Copyright 2011 Freescale Semiconductor, Inc.
- *
- * Author: Fabio Estevam <fabio.estevam@freescale.com>
- */
-
-#include <common.h>
-#include <init.h>
-#include <asm/global_data.h>
-#include <asm/io.h>
-#include <asm/gpio.h>
-#include <asm/arch/imx-regs.h>
-#include <asm/arch/iomux-mx25.h>
-#include <asm/arch/clock.h>
-#include <mmc.h>
-#include <fsl_esdhc_imx.h>
-#include <i2c.h>
-#include <linux/delay.h>
-#include <power/pmic.h>
-#include <fsl_pmic.h>
-#include <mc34704.h>
-
-#define FEC_RESET_B IMX_GPIO_NR(4, 8)
-#define FEC_ENABLE_B IMX_GPIO_NR(2, 3)
-#define CARD_DETECT IMX_GPIO_NR(2, 1)
-
-DECLARE_GLOBAL_DATA_PTR;
-
-#ifdef CONFIG_FSL_ESDHC_IMX
-struct fsl_esdhc_cfg esdhc_cfg[1] = {
- {IMX_MMC_SDHC1_BASE},
-};
-#endif
-
-/*
- * FIXME: need to revisit this
- * The original code enabled PUE and 100-k pull-down without PKE, so the right
- * value here is likely:
- * 0 for no pull
- * or:
- * PAD_CTL_PUS_100K_DOWN for 100-k pull-down
- */
-#define FEC_OUT_PAD_CTRL 0
-
-#define I2C_PAD_CTRL (PAD_CTL_HYS | PAD_CTL_PUS_100K_UP | \
- PAD_CTL_ODE)
-
-static void mx25pdk_fec_init(void)
-{
- static const iomux_v3_cfg_t fec_pads[] = {
- MX25_PAD_FEC_TX_CLK__FEC_TX_CLK,
- MX25_PAD_FEC_RX_DV__FEC_RX_DV,
- MX25_PAD_FEC_RDATA0__FEC_RDATA0,
- NEW_PAD_CTRL(MX25_PAD_FEC_TDATA0__FEC_TDATA0, FEC_OUT_PAD_CTRL),
- NEW_PAD_CTRL(MX25_PAD_FEC_TX_EN__FEC_TX_EN, FEC_OUT_PAD_CTRL),
- NEW_PAD_CTRL(MX25_PAD_FEC_MDC__FEC_MDC, FEC_OUT_PAD_CTRL),
- MX25_PAD_FEC_MDIO__FEC_MDIO,
- MX25_PAD_FEC_RDATA1__FEC_RDATA1,
- NEW_PAD_CTRL(MX25_PAD_FEC_TDATA1__FEC_TDATA1, FEC_OUT_PAD_CTRL),
-
- NEW_PAD_CTRL(MX25_PAD_D12__GPIO_4_8, 0), /* FEC_RESET_B */
- NEW_PAD_CTRL(MX25_PAD_A17__GPIO_2_3, 0), /* FEC_ENABLE_B */
- };
-
- static const iomux_v3_cfg_t i2c_pads[] = {
- NEW_PAD_CTRL(MX25_PAD_I2C1_CLK__I2C1_CLK, I2C_PAD_CTRL),
- NEW_PAD_CTRL(MX25_PAD_I2C1_DAT__I2C1_DAT, I2C_PAD_CTRL),
- };
-
- imx_iomux_v3_setup_multiple_pads(fec_pads, ARRAY_SIZE(fec_pads));
-
- /* Assert RESET and ENABLE low */
- gpio_direction_output(FEC_RESET_B, 0);
- gpio_direction_output(FEC_ENABLE_B, 0);
-
- udelay(10);
-
- /* Deassert RESET and ENABLE */
- gpio_set_value(FEC_RESET_B, 1);
- gpio_set_value(FEC_ENABLE_B, 1);
-
- /* Setup I2C pins so that PMIC can turn on PHY supply */
- imx_iomux_v3_setup_multiple_pads(i2c_pads, ARRAY_SIZE(i2c_pads));
-}
-
-int dram_init(void)
-{
- /* dram_init must store complete ramsize in gd->ram_size */
- gd->ram_size = get_ram_size((void *)CONFIG_SYS_SDRAM_BASE,
- PHYS_SDRAM_1_SIZE);
- return 0;
-}
-
-/*
- * Set up input pins with hysteresis and 100-k pull-ups
- */
-#define UART1_IN_PAD_CTRL (PAD_CTL_HYS | PAD_CTL_PUS_100K_UP)
-/*
- * FIXME: need to revisit this
- * The original code enabled PUE and 100-k pull-down without PKE, so the right
- * value here is likely:
- * 0 for no pull
- * or:
- * PAD_CTL_PUS_100K_DOWN for 100-k pull-down
- */
-#define UART1_OUT_PAD_CTRL 0
-
-static void mx25pdk_uart1_init(void)
-{
- static const iomux_v3_cfg_t uart1_pads[] = {
- NEW_PAD_CTRL(MX25_PAD_UART1_RXD__UART1_RXD, UART1_IN_PAD_CTRL),
- NEW_PAD_CTRL(MX25_PAD_UART1_TXD__UART1_TXD, UART1_OUT_PAD_CTRL),
- NEW_PAD_CTRL(MX25_PAD_UART1_RTS__UART1_RTS, UART1_OUT_PAD_CTRL),
- NEW_PAD_CTRL(MX25_PAD_UART1_CTS__UART1_CTS, UART1_IN_PAD_CTRL),
- };
-
- imx_iomux_v3_setup_multiple_pads(uart1_pads, ARRAY_SIZE(uart1_pads));
-}
-
-int board_early_init_f(void)
-{
- mx25pdk_uart1_init();
-
- return 0;
-}
-
-int board_init(void)
-{
- /* address of boot parameters */
- gd->bd->bi_boot_params = PHYS_SDRAM_1 + 0x100;
-
- return 0;
-}
-
-int board_late_init(void)
-{
- struct pmic *p;
- int ret;
-
- mx25pdk_fec_init();
-
- ret = pmic_init(I2C_0);
- if (ret)
- return ret;
-
- p = pmic_get("FSL_PMIC");
- if (!p)
- return -ENODEV;
-
- /* Turn on Ethernet PHY and LCD supplies */
- pmic_reg_write(p, MC34704_GENERAL2_REG, ONOFFE | ONOFFA);
-
- return 0;
-}
-
-#ifdef CONFIG_FSL_ESDHC_IMX
-int board_mmc_getcd(struct mmc *mmc)
-{
- /* Set up the Card Detect pin. */
- imx_iomux_v3_setup_pad(NEW_PAD_CTRL(MX25_PAD_A15__GPIO_2_1, 0));
-
- gpio_direction_input(CARD_DETECT);
- return !gpio_get_value(CARD_DETECT);
-}
-
-int board_mmc_init(struct bd_info *bis)
-{
- static const iomux_v3_cfg_t sdhc1_pads[] = {
- NEW_PAD_CTRL(MX25_PAD_SD1_CMD__SD1_CMD, NO_PAD_CTRL),
- NEW_PAD_CTRL(MX25_PAD_SD1_CLK__SD1_CLK, NO_PAD_CTRL),
- NEW_PAD_CTRL(MX25_PAD_SD1_DATA0__SD1_DATA0, NO_PAD_CTRL),
- NEW_PAD_CTRL(MX25_PAD_SD1_DATA1__SD1_DATA1, NO_PAD_CTRL),
- NEW_PAD_CTRL(MX25_PAD_SD1_DATA2__SD1_DATA2, NO_PAD_CTRL),
- NEW_PAD_CTRL(MX25_PAD_SD1_DATA3__SD1_DATA3, NO_PAD_CTRL),
- };
-
- imx_iomux_v3_setup_multiple_pads(sdhc1_pads, ARRAY_SIZE(sdhc1_pads));
-
- /*
- * Set the eSDHC1 PER clock to the maximum frequency lower than or equal
- * to 50 MHz that can be obtained, which requires to use UPLL as the
- * clock source. This actually gives 48 MHz.
- */
- imx_set_perclk(MXC_ESDHC1_CLK, true, 50000000);
- esdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC1_CLK);
- return fsl_esdhc_initialize(bis, &esdhc_cfg[0]);
-}
-#endif
-
-int checkboard(void)
-{
- puts("Board: MX25PDK\n");
-
- return 0;
-}
-
-/* Lowlevel init isn't used on mx25pdk, so just provide a dummy one here */
-void lowlevel_init(void) {}
diff --git a/board/freescale/mx51evk/MAINTAINERS b/board/freescale/mx51evk/MAINTAINERS
index 0e5f22c..1ca55f7 100644
--- a/board/freescale/mx51evk/MAINTAINERS
+++ b/board/freescale/mx51evk/MAINTAINERS
@@ -1,4 +1,5 @@
MX51EVK BOARD
+M: Fabio Estevam <festevam@gmail.com>
M: Stefano Babic <sbabic@denx.de>
S: Maintained
F: board/freescale/mx51evk/
diff --git a/board/freescale/mx51evk/mx51evk.c b/board/freescale/mx51evk/mx51evk.c
index ac48e76..c8439a6 100644
--- a/board/freescale/mx51evk/mx51evk.c
+++ b/board/freescale/mx51evk/mx51evk.c
@@ -27,13 +27,6 @@
DECLARE_GLOBAL_DATA_PTR;
-#ifdef CONFIG_FSL_ESDHC_IMX
-struct fsl_esdhc_cfg esdhc_cfg[2] = {
- {MMC_SDHC1_BASE_ADDR},
- {MMC_SDHC2_BASE_ADDR},
-};
-#endif
-
int dram_init(void)
{
/* dram_init must store complete ramsize in gd->ram_size */
@@ -64,34 +57,6 @@
imx_iomux_v3_setup_multiple_pads(uart_pads, ARRAY_SIZE(uart_pads));
}
-static void setup_iomux_fec(void)
-{
- static const iomux_v3_cfg_t fec_pads[] = {
- NEW_PAD_CTRL(MX51_PAD_EIM_EB2__FEC_MDIO, PAD_CTL_HYS |
- PAD_CTL_PUS_22K_UP | PAD_CTL_ODE |
- PAD_CTL_DSE_HIGH | PAD_CTL_SRE_FAST),
- MX51_PAD_NANDF_CS3__FEC_MDC,
- NEW_PAD_CTRL(MX51_PAD_EIM_CS3__FEC_RDATA3, MX51_PAD_CTRL_2),
- NEW_PAD_CTRL(MX51_PAD_EIM_CS2__FEC_RDATA2, MX51_PAD_CTRL_2),
- NEW_PAD_CTRL(MX51_PAD_EIM_EB3__FEC_RDATA1, MX51_PAD_CTRL_2),
- MX51_PAD_NANDF_D9__FEC_RDATA0,
- MX51_PAD_NANDF_CS6__FEC_TDATA3,
- MX51_PAD_NANDF_CS5__FEC_TDATA2,
- MX51_PAD_NANDF_CS4__FEC_TDATA1,
- MX51_PAD_NANDF_D8__FEC_TDATA0,
- MX51_PAD_NANDF_CS7__FEC_TX_EN,
- MX51_PAD_NANDF_CS2__FEC_TX_ER,
- MX51_PAD_NANDF_RDY_INT__FEC_TX_CLK,
- NEW_PAD_CTRL(MX51_PAD_NANDF_RB2__FEC_COL, MX51_PAD_CTRL_4),
- NEW_PAD_CTRL(MX51_PAD_NANDF_RB3__FEC_RX_CLK, MX51_PAD_CTRL_4),
- MX51_PAD_EIM_CS5__FEC_CRS,
- MX51_PAD_EIM_CS4__FEC_RX_ER,
- NEW_PAD_CTRL(MX51_PAD_NANDF_D11__FEC_RX_DV, MX51_PAD_CTRL_4),
- };
-
- imx_iomux_v3_setup_multiple_pads(fec_pads, ARRAY_SIZE(fec_pads));
-}
-
#ifdef CONFIG_MXC_SPI
static void setup_iomux_spi(void)
{
@@ -112,64 +77,6 @@
}
#endif
-#ifdef CONFIG_USB_EHCI_MX5
-#define MX51EVK_USBH1_HUB_RST IMX_GPIO_NR(1, 7)
-#define MX51EVK_USBH1_STP IMX_GPIO_NR(1, 27)
-#define MX51EVK_USB_CLK_EN_B IMX_GPIO_NR(2, 1)
-#define MX51EVK_USB_PHY_RESET IMX_GPIO_NR(2, 5)
-
-static void setup_usb_h1(void)
-{
- static const iomux_v3_cfg_t usb_h1_pads[] = {
- MX51_PAD_USBH1_CLK__USBH1_CLK,
- MX51_PAD_USBH1_DIR__USBH1_DIR,
- MX51_PAD_USBH1_STP__USBH1_STP,
- MX51_PAD_USBH1_NXT__USBH1_NXT,
- MX51_PAD_USBH1_DATA0__USBH1_DATA0,
- MX51_PAD_USBH1_DATA1__USBH1_DATA1,
- MX51_PAD_USBH1_DATA2__USBH1_DATA2,
- MX51_PAD_USBH1_DATA3__USBH1_DATA3,
- MX51_PAD_USBH1_DATA4__USBH1_DATA4,
- MX51_PAD_USBH1_DATA5__USBH1_DATA5,
- MX51_PAD_USBH1_DATA6__USBH1_DATA6,
- MX51_PAD_USBH1_DATA7__USBH1_DATA7,
-
- NEW_PAD_CTRL(MX51_PAD_GPIO1_7__GPIO1_7, 0), /* H1 hub reset */
- MX51_PAD_EIM_D17__GPIO2_1,
- MX51_PAD_EIM_D21__GPIO2_5, /* PHY reset */
- };
-
- imx_iomux_v3_setup_multiple_pads(usb_h1_pads, ARRAY_SIZE(usb_h1_pads));
-}
-
-int board_ehci_hcd_init(int port)
-{
- /* Set USBH1_STP to GPIO and toggle it */
- imx_iomux_v3_setup_pad(NEW_PAD_CTRL(MX51_PAD_USBH1_STP__GPIO1_27,
- MX51_USBH_PAD_CTRL));
-
- gpio_direction_output(MX51EVK_USBH1_STP, 0);
- gpio_direction_output(MX51EVK_USB_PHY_RESET, 0);
- mdelay(10);
- gpio_set_value(MX51EVK_USBH1_STP, 1);
-
- /* Set back USBH1_STP to be function */
- imx_iomux_v3_setup_pad(MX51_PAD_USBH1_STP__USBH1_STP);
-
- /* De-assert USB PHY RESETB */
- gpio_set_value(MX51EVK_USB_PHY_RESET, 1);
-
- /* Drive USB_CLK_EN_B line low */
- gpio_direction_output(MX51EVK_USB_CLK_EN_B, 0);
-
- /* Reset USB hub */
- gpio_direction_output(MX51EVK_USBH1_HUB_RST, 0);
- mdelay(2);
- gpio_set_value(MX51EVK_USBH1_HUB_RST, 1);
- return 0;
-}
-#endif
-
static void power_init(void)
{
unsigned int val;
@@ -258,6 +165,7 @@
imx_iomux_v3_setup_pad(NEW_PAD_CTRL(MX51_PAD_EIM_A20__GPIO2_14,
NO_PAD_CTRL));
+ gpio_request(IMX_GPIO_NR(2, 14), "gpio2_14");
gpio_direction_output(IMX_GPIO_NR(2, 14), 0);
udelay(500);
@@ -265,101 +173,9 @@
gpio_set_value(IMX_GPIO_NR(2, 14), 1);
}
-#ifdef CONFIG_FSL_ESDHC_IMX
-int board_mmc_getcd(struct mmc *mmc)
-{
- struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv;
- int ret;
-
- imx_iomux_v3_setup_pad(NEW_PAD_CTRL(MX51_PAD_GPIO1_0__GPIO1_0,
- NO_PAD_CTRL));
- gpio_direction_input(IMX_GPIO_NR(1, 0));
- imx_iomux_v3_setup_pad(NEW_PAD_CTRL(MX51_PAD_GPIO1_6__GPIO1_6,
- NO_PAD_CTRL));
- gpio_direction_input(IMX_GPIO_NR(1, 6));
-
- if (cfg->esdhc_base == MMC_SDHC1_BASE_ADDR)
- ret = !gpio_get_value(IMX_GPIO_NR(1, 0));
- else
- ret = !gpio_get_value(IMX_GPIO_NR(1, 6));
-
- return ret;
-}
-
-int board_mmc_init(struct bd_info *bis)
-{
- static const iomux_v3_cfg_t sd1_pads[] = {
- NEW_PAD_CTRL(MX51_PAD_SD1_CMD__SD1_CMD, PAD_CTL_DSE_MAX |
- PAD_CTL_HYS | PAD_CTL_PUS_47K_UP | PAD_CTL_SRE_FAST),
- NEW_PAD_CTRL(MX51_PAD_SD1_CLK__SD1_CLK, PAD_CTL_DSE_MAX |
- PAD_CTL_PUS_47K_UP | PAD_CTL_SRE_FAST),
- NEW_PAD_CTRL(MX51_PAD_SD1_DATA0__SD1_DATA0, PAD_CTL_DSE_MAX |
- PAD_CTL_HYS | PAD_CTL_PUS_47K_UP | PAD_CTL_SRE_FAST),
- NEW_PAD_CTRL(MX51_PAD_SD1_DATA1__SD1_DATA1, PAD_CTL_DSE_MAX |
- PAD_CTL_HYS | PAD_CTL_PUS_47K_UP | PAD_CTL_SRE_FAST),
- NEW_PAD_CTRL(MX51_PAD_SD1_DATA2__SD1_DATA2, PAD_CTL_DSE_MAX |
- PAD_CTL_HYS | PAD_CTL_PUS_47K_UP | PAD_CTL_SRE_FAST),
- NEW_PAD_CTRL(MX51_PAD_SD1_DATA3__SD1_DATA3, PAD_CTL_DSE_MAX |
- PAD_CTL_HYS | PAD_CTL_PUS_100K_DOWN | PAD_CTL_SRE_FAST),
- NEW_PAD_CTRL(MX51_PAD_GPIO1_0__SD1_CD, PAD_CTL_HYS),
- NEW_PAD_CTRL(MX51_PAD_GPIO1_1__SD1_WP, PAD_CTL_HYS),
- };
-
- static const iomux_v3_cfg_t sd2_pads[] = {
- NEW_PAD_CTRL(MX51_PAD_SD2_CMD__SD2_CMD,
- PAD_CTL_DSE_MAX | PAD_CTL_SRE_FAST),
- NEW_PAD_CTRL(MX51_PAD_SD2_CLK__SD2_CLK,
- PAD_CTL_DSE_MAX | PAD_CTL_SRE_FAST),
- NEW_PAD_CTRL(MX51_PAD_SD2_DATA0__SD2_DATA0,
- PAD_CTL_DSE_MAX | PAD_CTL_SRE_FAST),
- NEW_PAD_CTRL(MX51_PAD_SD2_DATA1__SD2_DATA1,
- PAD_CTL_DSE_MAX | PAD_CTL_SRE_FAST),
- NEW_PAD_CTRL(MX51_PAD_SD2_DATA2__SD2_DATA2,
- PAD_CTL_DSE_MAX | PAD_CTL_SRE_FAST),
- NEW_PAD_CTRL(MX51_PAD_SD2_DATA3__SD2_DATA3,
- PAD_CTL_DSE_MAX | PAD_CTL_SRE_FAST),
- NEW_PAD_CTRL(MX51_PAD_GPIO1_6__GPIO1_6, PAD_CTL_HYS),
- NEW_PAD_CTRL(MX51_PAD_GPIO1_5__GPIO1_5, PAD_CTL_HYS),
- };
-
- u32 index;
- int ret;
-
- esdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK);
- esdhc_cfg[1].sdhc_clk = mxc_get_clock(MXC_ESDHC2_CLK);
-
- for (index = 0; index < CONFIG_SYS_FSL_ESDHC_NUM;
- index++) {
- switch (index) {
- case 0:
- imx_iomux_v3_setup_multiple_pads(sd1_pads,
- ARRAY_SIZE(sd1_pads));
- break;
- case 1:
- imx_iomux_v3_setup_multiple_pads(sd2_pads,
- ARRAY_SIZE(sd2_pads));
- break;
- default:
- printf("Warning: you configured more ESDHC controller"
- "(%d) as supported by the board(2)\n",
- CONFIG_SYS_FSL_ESDHC_NUM);
- return -EINVAL;
- }
- ret = fsl_esdhc_initialize(bis, &esdhc_cfg[index]);
- if (ret)
- return ret;
- }
- return 0;
-}
-#endif
-
int board_early_init_f(void)
{
setup_iomux_uart();
- setup_iomux_fec();
-#ifdef CONFIG_USB_EHCI_MX5
- setup_usb_h1();
-#endif
setup_iomux_lcd();
return 0;
diff --git a/board/freescale/mx53ard/Kconfig b/board/freescale/mx53ard/Kconfig
deleted file mode 100644
index 41f46a0..0000000
--- a/board/freescale/mx53ard/Kconfig
+++ /dev/null
@@ -1,15 +0,0 @@
-if TARGET_MX53ARD
-
-config SYS_BOARD
- default "mx53ard"
-
-config SYS_VENDOR
- default "freescale"
-
-config SYS_SOC
- default "mx5"
-
-config SYS_CONFIG_NAME
- default "mx53ard"
-
-endif
diff --git a/board/freescale/mx53ard/MAINTAINERS b/board/freescale/mx53ard/MAINTAINERS
deleted file mode 100644
index fa81afe..0000000
--- a/board/freescale/mx53ard/MAINTAINERS
+++ /dev/null
@@ -1,6 +0,0 @@
-MX53ARD BOARD
-M: Fabio Estevam <fabio.estevam@nxp.com>
-S: Maintained
-F: board/freescale/mx53ard/
-F: include/configs/mx53ard.h
-F: configs/mx53ard_defconfig
diff --git a/board/freescale/mx53ard/Makefile b/board/freescale/mx53ard/Makefile
deleted file mode 100644
index e963a24..0000000
--- a/board/freescale/mx53ard/Makefile
+++ /dev/null
@@ -1,7 +0,0 @@
-# SPDX-License-Identifier: GPL-2.0+
-#
-# Copyright (C) 2007, Guennadi Liakhovetski <lg@denx.de>
-#
-# (C) Copyright 2011 Freescale Semiconductor, Inc.
-
-obj-y := mx53ard.o
diff --git a/board/freescale/mx53ard/imximage_dd3.cfg b/board/freescale/mx53ard/imximage_dd3.cfg
deleted file mode 100644
index fd03318..0000000
--- a/board/freescale/mx53ard/imximage_dd3.cfg
+++ /dev/null
@@ -1,82 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0+ */
-/*
- * (C) Copyright 2009
- * Stefano Babic DENX Software Engineering sbabic@denx.de.
- *
- * Refer doc/imx/mkimage/imximage.txt for more details about how-to configure
- * and create imximage boot image
- *
- * The syntax is taken as close as possible with the kwbimage
- */
-
-/* image version */
-IMAGE_VERSION 2
-
-/*
- * Boot Device : one of
- * spi, sd (the board has no nand neither onenand)
- */
-BOOT_FROM sd
-
-/*
- * Device Configuration Data (DCD)
- *
- * Each entry must have the format:
- * Addr-type Address Value
- *
- * where:
- * Addr-type register length (1,2 or 4 bytes)
- * Address absolute address of the register
- * value value to be stored in the register
- */
-DATA 4 0x53fa8554 0x00300000
-DATA 4 0x53fa8558 0x00300040
-DATA 4 0x53fa8560 0x00300000
-DATA 4 0x53fa8564 0x00300040
-DATA 4 0x53fa8568 0x00300040
-DATA 4 0x53fa8570 0x00300000
-DATA 4 0x53fa8574 0x00300000
-DATA 4 0x53fa8578 0x00300000
-DATA 4 0x53fa857c 0x00300040
-DATA 4 0x53fa8580 0x00300040
-DATA 4 0x53fa8584 0x00300000
-DATA 4 0x53fa8588 0x00300000
-DATA 4 0x53fa8590 0x00300040
-DATA 4 0x53fa8594 0x00300000
-DATA 4 0x53fa86f0 0x00300000
-DATA 4 0x53fa86f4 0x00000000
-DATA 4 0x53fa86fc 0x00000000
-DATA 4 0x53fa8714 0x00000000
-DATA 4 0x53fa8718 0x00300000
-DATA 4 0x53fa871c 0x00300000
-DATA 4 0x53fa8720 0x00300000
-DATA 4 0x53fa8724 0x04000000
-DATA 4 0x53fa8728 0x00300000
-DATA 4 0x53fa872c 0x00300000
-DATA 4 0x63fd9088 0x35343535
-DATA 4 0x63fd9090 0x4d444c44
-DATA 4 0x63fd907c 0x01370138
-DATA 4 0x63fd9080 0x013b013c
-DATA 4 0x63fd9018 0x00011740
-DATA 4 0x63fd9000 0xc3190000
-DATA 4 0x63fd900c 0x9f5152e3
-DATA 4 0x63fd9010 0xb68e8a63
-DATA 4 0x63fd9014 0x01ff00db
-DATA 4 0x63fd902c 0x000026d2
-DATA 4 0x63fd9030 0x009f0e21
-DATA 4 0x63fd9008 0x12273030
-DATA 4 0x63fd9004 0x0002002d
-DATA 4 0x63fd901c 0x00008032
-DATA 4 0x63fd901c 0x00008033
-DATA 4 0x63fd901c 0x00028031
-DATA 4 0x63fd901c 0x052080b0
-DATA 4 0x63fd901c 0x04008040
-DATA 4 0x63fd901c 0x0000803a
-DATA 4 0x63fd901c 0x0000803b
-DATA 4 0x63fd901c 0x00028039
-DATA 4 0x63fd901c 0x05208138
-DATA 4 0x63fd901c 0x04008048
-DATA 4 0x63fd9020 0x00005800
-DATA 4 0x63fd9040 0x05380003
-DATA 4 0x63fd9058 0x00022227
-DATA 4 0x63fd901C 0x00000000
diff --git a/board/freescale/mx53ard/mx53ard.c b/board/freescale/mx53ard/mx53ard.c
deleted file mode 100644
index f9ec5ca..0000000
--- a/board/freescale/mx53ard/mx53ard.c
+++ /dev/null
@@ -1,319 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * (C) Copyright 2011 Freescale Semiconductor, Inc.
- */
-
-#include <common.h>
-#include <init.h>
-#include <net.h>
-#include <asm/global_data.h>
-#include <asm/io.h>
-#include <asm/arch/imx-regs.h>
-#include <asm/arch/sys_proto.h>
-#include <asm/arch/crm_regs.h>
-#include <asm/arch/clock.h>
-#include <asm/arch/iomux-mx53.h>
-#include <linux/errno.h>
-#include <netdev.h>
-#include <mmc.h>
-#include <fsl_esdhc_imx.h>
-#include <asm/gpio.h>
-
-#define ETHERNET_INT IMX_GPIO_NR(2, 31)
-
-DECLARE_GLOBAL_DATA_PTR;
-
-int dram_init(void)
-{
- u32 size1, size2;
-
- size1 = get_ram_size((void *)PHYS_SDRAM_1, PHYS_SDRAM_1_SIZE);
- size2 = get_ram_size((void *)PHYS_SDRAM_2, PHYS_SDRAM_2_SIZE);
-
- gd->ram_size = size1 + size2;
-
- return 0;
-}
-int dram_init_banksize(void)
-{
- gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
- gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE;
-
- gd->bd->bi_dram[1].start = PHYS_SDRAM_2;
- gd->bd->bi_dram[1].size = PHYS_SDRAM_2_SIZE;
-
- return 0;
-}
-
-#ifdef CONFIG_NAND_MXC
-static void setup_iomux_nand(void)
-{
- static const iomux_v3_cfg_t nand_pads[] = {
- NEW_PAD_CTRL(MX53_PAD_NANDF_CS0__EMI_NANDF_CS_0,
- PAD_CTL_DSE_HIGH),
- NEW_PAD_CTRL(MX53_PAD_NANDF_CS1__EMI_NANDF_CS_1,
- PAD_CTL_DSE_HIGH),
- NEW_PAD_CTRL(MX53_PAD_NANDF_RB0__EMI_NANDF_RB_0,
- PAD_CTL_PUS_100K_UP),
- NEW_PAD_CTRL(MX53_PAD_NANDF_CLE__EMI_NANDF_CLE,
- PAD_CTL_DSE_HIGH),
- NEW_PAD_CTRL(MX53_PAD_NANDF_ALE__EMI_NANDF_ALE,
- PAD_CTL_DSE_HIGH),
- NEW_PAD_CTRL(MX53_PAD_NANDF_WP_B__EMI_NANDF_WP_B,
- PAD_CTL_PUS_100K_UP),
- NEW_PAD_CTRL(MX53_PAD_NANDF_RE_B__EMI_NANDF_RE_B,
- PAD_CTL_DSE_HIGH),
- NEW_PAD_CTRL(MX53_PAD_NANDF_WE_B__EMI_NANDF_WE_B,
- PAD_CTL_DSE_HIGH),
- NEW_PAD_CTRL(MX53_PAD_EIM_DA0__EMI_NAND_WEIM_DA_0,
- PAD_CTL_PKE | PAD_CTL_DSE_HIGH),
- NEW_PAD_CTRL(MX53_PAD_EIM_DA1__EMI_NAND_WEIM_DA_1,
- PAD_CTL_PKE | PAD_CTL_DSE_HIGH),
- NEW_PAD_CTRL(MX53_PAD_EIM_DA2__EMI_NAND_WEIM_DA_2,
- PAD_CTL_PKE | PAD_CTL_DSE_HIGH),
- NEW_PAD_CTRL(MX53_PAD_EIM_DA3__EMI_NAND_WEIM_DA_3,
- PAD_CTL_PKE | PAD_CTL_DSE_HIGH),
- NEW_PAD_CTRL(MX53_PAD_EIM_DA4__EMI_NAND_WEIM_DA_4,
- PAD_CTL_PKE | PAD_CTL_DSE_HIGH),
- NEW_PAD_CTRL(MX53_PAD_EIM_DA5__EMI_NAND_WEIM_DA_5,
- PAD_CTL_PKE | PAD_CTL_DSE_HIGH),
- NEW_PAD_CTRL(MX53_PAD_EIM_DA6__EMI_NAND_WEIM_DA_6,
- PAD_CTL_PKE | PAD_CTL_DSE_HIGH),
- NEW_PAD_CTRL(MX53_PAD_EIM_DA7__EMI_NAND_WEIM_DA_7,
- PAD_CTL_PKE | PAD_CTL_DSE_HIGH),
- };
-
- u32 i, reg;
-
- reg = __raw_readl(M4IF_BASE_ADDR + 0xc);
- reg &= ~M4IF_GENP_WEIM_MM_MASK;
- __raw_writel(reg, M4IF_BASE_ADDR + 0xc);
- for (i = 0x4; i < 0x94; i += 0x18) {
- reg = __raw_readl(WEIM_BASE_ADDR + i);
- reg &= ~WEIM_GCR2_MUX16_BYP_GRANT_MASK;
- __raw_writel(reg, WEIM_BASE_ADDR + i);
- }
-
- imx_iomux_v3_setup_multiple_pads(nand_pads, ARRAY_SIZE(nand_pads));
-}
-#else
-static void setup_iomux_nand(void)
-{
-}
-#endif
-
-#define UART_PAD_CTRL (PAD_CTL_HYS | PAD_CTL_DSE_HIGH | \
- PAD_CTL_PUS_100K_UP | PAD_CTL_ODE)
-
-static void setup_iomux_uart(void)
-{
- static const iomux_v3_cfg_t uart_pads[] = {
- NEW_PAD_CTRL(MX53_PAD_PATA_DMACK__UART1_RXD_MUX, UART_PAD_CTRL),
- NEW_PAD_CTRL(MX53_PAD_PATA_DIOW__UART1_TXD_MUX, UART_PAD_CTRL),
- };
-
- imx_iomux_v3_setup_multiple_pads(uart_pads, ARRAY_SIZE(uart_pads));
-}
-
-#ifdef CONFIG_FSL_ESDHC_IMX
-struct fsl_esdhc_cfg esdhc_cfg[2] = {
- {MMC_SDHC1_BASE_ADDR},
- {MMC_SDHC2_BASE_ADDR},
-};
-
-int board_mmc_getcd(struct mmc *mmc)
-{
- struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv;
- int ret;
-
- imx_iomux_v3_setup_pad(MX53_PAD_GPIO_1__GPIO1_1);
- gpio_direction_input(IMX_GPIO_NR(1, 1));
- imx_iomux_v3_setup_pad(MX53_PAD_GPIO_4__GPIO1_4);
- gpio_direction_input(IMX_GPIO_NR(1, 4));
-
- if (cfg->esdhc_base == MMC_SDHC1_BASE_ADDR)
- ret = !gpio_get_value(IMX_GPIO_NR(1, 1));
- else
- ret = !gpio_get_value(IMX_GPIO_NR(1, 4));
-
- return ret;
-}
-
-#define SD_CMD_PAD_CTRL (PAD_CTL_HYS | PAD_CTL_DSE_HIGH | \
- PAD_CTL_PUS_100K_UP)
-#define SD_CLK_PAD_CTRL (PAD_CTL_PUS_47K_UP | PAD_CTL_DSE_HIGH)
-#define SD_PAD_CTRL (PAD_CTL_HYS | PAD_CTL_PUS_47K_UP | \
- PAD_CTL_DSE_HIGH)
-
-int board_mmc_init(struct bd_info *bis)
-{
- static const iomux_v3_cfg_t sd1_pads[] = {
- NEW_PAD_CTRL(MX53_PAD_SD1_CMD__ESDHC1_CMD, SD_CMD_PAD_CTRL),
- NEW_PAD_CTRL(MX53_PAD_SD1_CLK__ESDHC1_CLK, SD_CLK_PAD_CTRL),
- NEW_PAD_CTRL(MX53_PAD_SD1_DATA0__ESDHC1_DAT0, SD_PAD_CTRL),
- NEW_PAD_CTRL(MX53_PAD_SD1_DATA1__ESDHC1_DAT1, SD_PAD_CTRL),
- NEW_PAD_CTRL(MX53_PAD_SD1_DATA2__ESDHC1_DAT2, SD_PAD_CTRL),
- NEW_PAD_CTRL(MX53_PAD_SD1_DATA3__ESDHC1_DAT3, SD_PAD_CTRL),
- };
-
- static const iomux_v3_cfg_t sd2_pads[] = {
- NEW_PAD_CTRL(MX53_PAD_SD2_CMD__ESDHC2_CMD, SD_CMD_PAD_CTRL),
- NEW_PAD_CTRL(MX53_PAD_SD2_CLK__ESDHC2_CLK, SD_CLK_PAD_CTRL),
- NEW_PAD_CTRL(MX53_PAD_SD2_DATA0__ESDHC2_DAT0, SD_PAD_CTRL),
- NEW_PAD_CTRL(MX53_PAD_SD2_DATA1__ESDHC2_DAT1, SD_PAD_CTRL),
- NEW_PAD_CTRL(MX53_PAD_SD2_DATA2__ESDHC2_DAT2, SD_PAD_CTRL),
- NEW_PAD_CTRL(MX53_PAD_SD2_DATA3__ESDHC2_DAT3, SD_PAD_CTRL),
- NEW_PAD_CTRL(MX53_PAD_PATA_DATA12__ESDHC2_DAT4, SD_PAD_CTRL),
- NEW_PAD_CTRL(MX53_PAD_PATA_DATA13__ESDHC2_DAT5, SD_PAD_CTRL),
- NEW_PAD_CTRL(MX53_PAD_PATA_DATA14__ESDHC2_DAT6, SD_PAD_CTRL),
- NEW_PAD_CTRL(MX53_PAD_PATA_DATA15__ESDHC2_DAT7, SD_PAD_CTRL),
- };
-
- u32 index;
- int ret;
-
- esdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK);
- esdhc_cfg[1].sdhc_clk = mxc_get_clock(MXC_ESDHC2_CLK);
-
- for (index = 0; index < CONFIG_SYS_FSL_ESDHC_NUM; index++) {
- switch (index) {
- case 0:
- imx_iomux_v3_setup_multiple_pads(sd1_pads,
- ARRAY_SIZE(sd1_pads));
- break;
- case 1:
- imx_iomux_v3_setup_multiple_pads(sd2_pads,
- ARRAY_SIZE(sd2_pads));
- break;
- default:
- printf("Warning: you configured more ESDHC controller"
- "(%d) as supported by the board(2)\n",
- CONFIG_SYS_FSL_ESDHC_NUM);
- return -EINVAL;
- }
- ret = fsl_esdhc_initialize(bis, &esdhc_cfg[index]);
- if (ret)
- return ret;
- }
-
- return 0;
-}
-#endif
-
-static void weim_smc911x_iomux(void)
-{
- static const iomux_v3_cfg_t weim_smc911x_pads[] = {
- /* Data bus */
- NEW_PAD_CTRL(MX53_PAD_EIM_D16__EMI_WEIM_D_16,
- PAD_CTL_PKE | PAD_CTL_DSE_HIGH),
- NEW_PAD_CTRL(MX53_PAD_EIM_D17__EMI_WEIM_D_17,
- PAD_CTL_PKE | PAD_CTL_DSE_HIGH),
- NEW_PAD_CTRL(MX53_PAD_EIM_D18__EMI_WEIM_D_18,
- PAD_CTL_PKE | PAD_CTL_DSE_HIGH),
- NEW_PAD_CTRL(MX53_PAD_EIM_D19__EMI_WEIM_D_19,
- PAD_CTL_PKE | PAD_CTL_DSE_HIGH),
- NEW_PAD_CTRL(MX53_PAD_EIM_D20__EMI_WEIM_D_20,
- PAD_CTL_PKE | PAD_CTL_DSE_HIGH),
- NEW_PAD_CTRL(MX53_PAD_EIM_D21__EMI_WEIM_D_21,
- PAD_CTL_PKE | PAD_CTL_DSE_HIGH),
- NEW_PAD_CTRL(MX53_PAD_EIM_D22__EMI_WEIM_D_22,
- PAD_CTL_PKE | PAD_CTL_DSE_HIGH),
- NEW_PAD_CTRL(MX53_PAD_EIM_D23__EMI_WEIM_D_23,
- PAD_CTL_PKE | PAD_CTL_DSE_HIGH),
- NEW_PAD_CTRL(MX53_PAD_EIM_D24__EMI_WEIM_D_24,
- PAD_CTL_PKE | PAD_CTL_DSE_HIGH),
- NEW_PAD_CTRL(MX53_PAD_EIM_D25__EMI_WEIM_D_25,
- PAD_CTL_PKE | PAD_CTL_DSE_HIGH),
- NEW_PAD_CTRL(MX53_PAD_EIM_D26__EMI_WEIM_D_26,
- PAD_CTL_PKE | PAD_CTL_DSE_HIGH),
- NEW_PAD_CTRL(MX53_PAD_EIM_D27__EMI_WEIM_D_27,
- PAD_CTL_PKE | PAD_CTL_DSE_HIGH),
- NEW_PAD_CTRL(MX53_PAD_EIM_D28__EMI_WEIM_D_28,
- PAD_CTL_PKE | PAD_CTL_DSE_HIGH),
- NEW_PAD_CTRL(MX53_PAD_EIM_D29__EMI_WEIM_D_29,
- PAD_CTL_PKE | PAD_CTL_DSE_HIGH),
- NEW_PAD_CTRL(MX53_PAD_EIM_D30__EMI_WEIM_D_30,
- PAD_CTL_PKE | PAD_CTL_DSE_HIGH),
- NEW_PAD_CTRL(MX53_PAD_EIM_D31__EMI_WEIM_D_31,
- PAD_CTL_PKE | PAD_CTL_DSE_HIGH),
-
- /* Address lines */
- NEW_PAD_CTRL(MX53_PAD_EIM_DA0__EMI_NAND_WEIM_DA_0,
- PAD_CTL_PKE | PAD_CTL_DSE_HIGH),
- NEW_PAD_CTRL(MX53_PAD_EIM_DA1__EMI_NAND_WEIM_DA_1,
- PAD_CTL_PKE | PAD_CTL_DSE_HIGH),
- NEW_PAD_CTRL(MX53_PAD_EIM_DA2__EMI_NAND_WEIM_DA_2,
- PAD_CTL_PKE | PAD_CTL_DSE_HIGH),
- NEW_PAD_CTRL(MX53_PAD_EIM_DA3__EMI_NAND_WEIM_DA_3,
- PAD_CTL_PKE | PAD_CTL_DSE_HIGH),
- NEW_PAD_CTRL(MX53_PAD_EIM_DA4__EMI_NAND_WEIM_DA_4,
- PAD_CTL_PKE | PAD_CTL_DSE_HIGH),
- NEW_PAD_CTRL(MX53_PAD_EIM_DA5__EMI_NAND_WEIM_DA_5,
- PAD_CTL_PKE | PAD_CTL_DSE_HIGH),
- NEW_PAD_CTRL(MX53_PAD_EIM_DA6__EMI_NAND_WEIM_DA_6,
- PAD_CTL_PKE | PAD_CTL_DSE_HIGH),
-
- /* other EIM signals for ethernet */
- MX53_PAD_EIM_OE__EMI_WEIM_OE,
- MX53_PAD_EIM_RW__EMI_WEIM_RW,
- MX53_PAD_EIM_CS1__EMI_WEIM_CS_1,
- };
-
- /* ETHERNET_INT as GPIO2_31 */
- imx_iomux_v3_setup_pad(MX53_PAD_EIM_EB3__GPIO2_31);
- gpio_direction_input(ETHERNET_INT);
-
- /* WEIM bus */
- imx_iomux_v3_setup_multiple_pads(weim_smc911x_pads,
- ARRAY_SIZE(weim_smc911x_pads));
-}
-
-static void weim_cs1_settings(void)
-{
- struct weim *weim_regs = (struct weim *)WEIM_BASE_ADDR;
-
- writel(MX53ARD_CS1GCR1, &weim_regs->cs1gcr1);
- writel(0x0, &weim_regs->cs1gcr2);
- writel(MX53ARD_CS1RCR1, &weim_regs->cs1rcr1);
- writel(MX53ARD_CS1RCR2, &weim_regs->cs1rcr2);
- writel(MX53ARD_CS1WCR1, &weim_regs->cs1wcr1);
- writel(0x0, &weim_regs->cs1wcr2);
- writel(0x0, &weim_regs->wcr);
-
- set_chipselect_size(CS0_64M_CS1_64M);
-}
-
-int board_early_init_f(void)
-{
- setup_iomux_nand();
- setup_iomux_uart();
- return 0;
-}
-
-int board_init(void)
-{
- /* address of boot parameters */
- gd->bd->bi_boot_params = PHYS_SDRAM_1 + 0x100;
-
- return 0;
-}
-
-int board_eth_init(struct bd_info *bis)
-{
- int rc = -ENODEV;
-
- weim_smc911x_iomux();
- weim_cs1_settings();
-
-#ifdef CONFIG_SMC911X
- rc = smc911x_initialize(0, CONFIG_SMC911X_BASE);
-#endif
- return rc;
-}
-
-int checkboard(void)
-{
- puts("Board: MX53ARD\n");
-
- return 0;
-}
diff --git a/board/freescale/mx53loco/MAINTAINERS b/board/freescale/mx53loco/MAINTAINERS
index b4bd1a1..6c23751 100644
--- a/board/freescale/mx53loco/MAINTAINERS
+++ b/board/freescale/mx53loco/MAINTAINERS
@@ -1,4 +1,5 @@
MX53LOCO BOARD
+M: Fabio Estevam <festevam@gmail.com>
M: Jason Liu <jason.hui.liu@nxp.com>
S: Maintained
F: board/freescale/mx53loco/
diff --git a/board/freescale/mx53loco/mx53loco.c b/board/freescale/mx53loco/mx53loco.c
index ee54a61..0888630 100644
--- a/board/freescale/mx53loco/mx53loco.c
+++ b/board/freescale/mx53loco/mx53loco.c
@@ -18,10 +18,8 @@
#include <env.h>
#include <linux/errno.h>
#include <asm/mach-imx/mx5_video.h>
-#include <netdev.h>
#include <i2c.h>
#include <input.h>
-#include <mmc.h>
#include <fsl_esdhc_imx.h>
#include <asm/gpio.h>
#include <power/pmic.h>
@@ -62,127 +60,6 @@
imx_iomux_v3_setup_multiple_pads(uart_pads, ARRAY_SIZE(uart_pads));
}
-#ifdef CONFIG_USB_EHCI_MX5
-int board_ehci_hcd_init(int port)
-{
- /* request VBUS power enable pin, GPIO7_8 */
- imx_iomux_v3_setup_pad(MX53_PAD_PATA_DA_2__GPIO7_8);
- gpio_direction_output(IMX_GPIO_NR(7, 8), 1);
- return 0;
-}
-#endif
-
-static void setup_iomux_fec(void)
-{
- static const iomux_v3_cfg_t fec_pads[] = {
- NEW_PAD_CTRL(MX53_PAD_FEC_MDIO__FEC_MDIO, PAD_CTL_HYS |
- PAD_CTL_DSE_HIGH | PAD_CTL_PUS_22K_UP | PAD_CTL_ODE),
- NEW_PAD_CTRL(MX53_PAD_FEC_MDC__FEC_MDC, PAD_CTL_DSE_HIGH),
- NEW_PAD_CTRL(MX53_PAD_FEC_RXD1__FEC_RDATA_1,
- PAD_CTL_HYS | PAD_CTL_PKE),
- NEW_PAD_CTRL(MX53_PAD_FEC_RXD0__FEC_RDATA_0,
- PAD_CTL_HYS | PAD_CTL_PKE),
- NEW_PAD_CTRL(MX53_PAD_FEC_TXD1__FEC_TDATA_1, PAD_CTL_DSE_HIGH),
- NEW_PAD_CTRL(MX53_PAD_FEC_TXD0__FEC_TDATA_0, PAD_CTL_DSE_HIGH),
- NEW_PAD_CTRL(MX53_PAD_FEC_TX_EN__FEC_TX_EN, PAD_CTL_DSE_HIGH),
- NEW_PAD_CTRL(MX53_PAD_FEC_REF_CLK__FEC_TX_CLK,
- PAD_CTL_HYS | PAD_CTL_PKE),
- NEW_PAD_CTRL(MX53_PAD_FEC_RX_ER__FEC_RX_ER,
- PAD_CTL_HYS | PAD_CTL_PKE),
- NEW_PAD_CTRL(MX53_PAD_FEC_CRS_DV__FEC_RX_DV,
- PAD_CTL_HYS | PAD_CTL_PKE),
- };
-
- imx_iomux_v3_setup_multiple_pads(fec_pads, ARRAY_SIZE(fec_pads));
-}
-
-#ifdef CONFIG_FSL_ESDHC_IMX
-struct fsl_esdhc_cfg esdhc_cfg[2] = {
- {MMC_SDHC1_BASE_ADDR},
- {MMC_SDHC3_BASE_ADDR},
-};
-
-int board_mmc_getcd(struct mmc *mmc)
-{
- struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv;
- int ret;
-
- imx_iomux_v3_setup_pad(MX53_PAD_EIM_DA11__GPIO3_11);
- gpio_direction_input(IMX_GPIO_NR(3, 11));
- imx_iomux_v3_setup_pad(MX53_PAD_EIM_DA13__GPIO3_13);
- gpio_direction_input(IMX_GPIO_NR(3, 13));
-
- if (cfg->esdhc_base == MMC_SDHC1_BASE_ADDR)
- ret = !gpio_get_value(IMX_GPIO_NR(3, 13));
- else
- ret = !gpio_get_value(IMX_GPIO_NR(3, 11));
-
- return ret;
-}
-
-#define SD_CMD_PAD_CTRL (PAD_CTL_HYS | PAD_CTL_DSE_HIGH | \
- PAD_CTL_PUS_100K_UP)
-#define SD_PAD_CTRL (PAD_CTL_HYS | PAD_CTL_PUS_47K_UP | \
- PAD_CTL_DSE_HIGH)
-
-int board_mmc_init(struct bd_info *bis)
-{
- static const iomux_v3_cfg_t sd1_pads[] = {
- NEW_PAD_CTRL(MX53_PAD_SD1_CMD__ESDHC1_CMD, SD_CMD_PAD_CTRL),
- NEW_PAD_CTRL(MX53_PAD_SD1_CLK__ESDHC1_CLK, SD_PAD_CTRL),
- NEW_PAD_CTRL(MX53_PAD_SD1_DATA0__ESDHC1_DAT0, SD_PAD_CTRL),
- NEW_PAD_CTRL(MX53_PAD_SD1_DATA1__ESDHC1_DAT1, SD_PAD_CTRL),
- NEW_PAD_CTRL(MX53_PAD_SD1_DATA2__ESDHC1_DAT2, SD_PAD_CTRL),
- NEW_PAD_CTRL(MX53_PAD_SD1_DATA3__ESDHC1_DAT3, SD_PAD_CTRL),
- MX53_PAD_EIM_DA13__GPIO3_13,
- };
-
- static const iomux_v3_cfg_t sd2_pads[] = {
- NEW_PAD_CTRL(MX53_PAD_PATA_RESET_B__ESDHC3_CMD,
- SD_CMD_PAD_CTRL),
- NEW_PAD_CTRL(MX53_PAD_PATA_IORDY__ESDHC3_CLK, SD_PAD_CTRL),
- NEW_PAD_CTRL(MX53_PAD_PATA_DATA8__ESDHC3_DAT0, SD_PAD_CTRL),
- NEW_PAD_CTRL(MX53_PAD_PATA_DATA9__ESDHC3_DAT1, SD_PAD_CTRL),
- NEW_PAD_CTRL(MX53_PAD_PATA_DATA10__ESDHC3_DAT2, SD_PAD_CTRL),
- NEW_PAD_CTRL(MX53_PAD_PATA_DATA11__ESDHC3_DAT3, SD_PAD_CTRL),
- NEW_PAD_CTRL(MX53_PAD_PATA_DATA0__ESDHC3_DAT4, SD_PAD_CTRL),
- NEW_PAD_CTRL(MX53_PAD_PATA_DATA1__ESDHC3_DAT5, SD_PAD_CTRL),
- NEW_PAD_CTRL(MX53_PAD_PATA_DATA2__ESDHC3_DAT6, SD_PAD_CTRL),
- NEW_PAD_CTRL(MX53_PAD_PATA_DATA3__ESDHC3_DAT7, SD_PAD_CTRL),
- MX53_PAD_EIM_DA11__GPIO3_11,
- };
-
- u32 index;
- int ret;
-
- esdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK);
- esdhc_cfg[1].sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK);
-
- for (index = 0; index < CONFIG_SYS_FSL_ESDHC_NUM; index++) {
- switch (index) {
- case 0:
- imx_iomux_v3_setup_multiple_pads(sd1_pads,
- ARRAY_SIZE(sd1_pads));
- break;
- case 1:
- imx_iomux_v3_setup_multiple_pads(sd2_pads,
- ARRAY_SIZE(sd2_pads));
- break;
- default:
- printf("Warning: you configured more ESDHC controller"
- "(%d) as supported by the board(2)\n",
- CONFIG_SYS_FSL_ESDHC_NUM);
- return -EINVAL;
- }
- ret = fsl_esdhc_initialize(bis, &esdhc_cfg[index]);
- if (ret)
- return ret;
- }
-
- return 0;
-}
-#endif
-
#define I2C_PAD_CTRL (PAD_CTL_SRE_FAST | PAD_CTL_DSE_HIGH | \
PAD_CTL_PUS_100K_UP | PAD_CTL_ODE)
@@ -327,7 +204,6 @@
int board_early_init_f(void)
{
setup_iomux_uart();
- setup_iomux_fec();
setup_iomux_lcd();
return 0;
diff --git a/board/freescale/mx53smd/Kconfig b/board/freescale/mx53smd/Kconfig
deleted file mode 100644
index 1195d33..0000000
--- a/board/freescale/mx53smd/Kconfig
+++ /dev/null
@@ -1,15 +0,0 @@
-if TARGET_MX53SMD
-
-config SYS_BOARD
- default "mx53smd"
-
-config SYS_VENDOR
- default "freescale"
-
-config SYS_SOC
- default "mx5"
-
-config SYS_CONFIG_NAME
- default "mx53smd"
-
-endif
diff --git a/board/freescale/mx53smd/MAINTAINERS b/board/freescale/mx53smd/MAINTAINERS
deleted file mode 100644
index 17ec376..0000000
--- a/board/freescale/mx53smd/MAINTAINERS
+++ /dev/null
@@ -1,6 +0,0 @@
-MX53SMD BOARD
-M: Fabio Estevam <fabio.estevam@nxp.com>
-S: Maintained
-F: board/freescale/mx53smd/
-F: include/configs/mx53smd.h
-F: configs/mx53smd_defconfig
diff --git a/board/freescale/mx53smd/Makefile b/board/freescale/mx53smd/Makefile
deleted file mode 100644
index f034757..0000000
--- a/board/freescale/mx53smd/Makefile
+++ /dev/null
@@ -1,7 +0,0 @@
-# SPDX-License-Identifier: GPL-2.0+
-#
-# Copyright (C) 2007, Guennadi Liakhovetski <lg@denx.de>
-#
-# (C) Copyright 2011 Freescale Semiconductor, Inc.
-
-obj-y := mx53smd.o
diff --git a/board/freescale/mx53smd/imximage.cfg b/board/freescale/mx53smd/imximage.cfg
deleted file mode 100644
index fd03318..0000000
--- a/board/freescale/mx53smd/imximage.cfg
+++ /dev/null
@@ -1,82 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0+ */
-/*
- * (C) Copyright 2009
- * Stefano Babic DENX Software Engineering sbabic@denx.de.
- *
- * Refer doc/imx/mkimage/imximage.txt for more details about how-to configure
- * and create imximage boot image
- *
- * The syntax is taken as close as possible with the kwbimage
- */
-
-/* image version */
-IMAGE_VERSION 2
-
-/*
- * Boot Device : one of
- * spi, sd (the board has no nand neither onenand)
- */
-BOOT_FROM sd
-
-/*
- * Device Configuration Data (DCD)
- *
- * Each entry must have the format:
- * Addr-type Address Value
- *
- * where:
- * Addr-type register length (1,2 or 4 bytes)
- * Address absolute address of the register
- * value value to be stored in the register
- */
-DATA 4 0x53fa8554 0x00300000
-DATA 4 0x53fa8558 0x00300040
-DATA 4 0x53fa8560 0x00300000
-DATA 4 0x53fa8564 0x00300040
-DATA 4 0x53fa8568 0x00300040
-DATA 4 0x53fa8570 0x00300000
-DATA 4 0x53fa8574 0x00300000
-DATA 4 0x53fa8578 0x00300000
-DATA 4 0x53fa857c 0x00300040
-DATA 4 0x53fa8580 0x00300040
-DATA 4 0x53fa8584 0x00300000
-DATA 4 0x53fa8588 0x00300000
-DATA 4 0x53fa8590 0x00300040
-DATA 4 0x53fa8594 0x00300000
-DATA 4 0x53fa86f0 0x00300000
-DATA 4 0x53fa86f4 0x00000000
-DATA 4 0x53fa86fc 0x00000000
-DATA 4 0x53fa8714 0x00000000
-DATA 4 0x53fa8718 0x00300000
-DATA 4 0x53fa871c 0x00300000
-DATA 4 0x53fa8720 0x00300000
-DATA 4 0x53fa8724 0x04000000
-DATA 4 0x53fa8728 0x00300000
-DATA 4 0x53fa872c 0x00300000
-DATA 4 0x63fd9088 0x35343535
-DATA 4 0x63fd9090 0x4d444c44
-DATA 4 0x63fd907c 0x01370138
-DATA 4 0x63fd9080 0x013b013c
-DATA 4 0x63fd9018 0x00011740
-DATA 4 0x63fd9000 0xc3190000
-DATA 4 0x63fd900c 0x9f5152e3
-DATA 4 0x63fd9010 0xb68e8a63
-DATA 4 0x63fd9014 0x01ff00db
-DATA 4 0x63fd902c 0x000026d2
-DATA 4 0x63fd9030 0x009f0e21
-DATA 4 0x63fd9008 0x12273030
-DATA 4 0x63fd9004 0x0002002d
-DATA 4 0x63fd901c 0x00008032
-DATA 4 0x63fd901c 0x00008033
-DATA 4 0x63fd901c 0x00028031
-DATA 4 0x63fd901c 0x052080b0
-DATA 4 0x63fd901c 0x04008040
-DATA 4 0x63fd901c 0x0000803a
-DATA 4 0x63fd901c 0x0000803b
-DATA 4 0x63fd901c 0x00028039
-DATA 4 0x63fd901c 0x05208138
-DATA 4 0x63fd901c 0x04008048
-DATA 4 0x63fd9020 0x00005800
-DATA 4 0x63fd9040 0x05380003
-DATA 4 0x63fd9058 0x00022227
-DATA 4 0x63fd901C 0x00000000
diff --git a/board/freescale/mx53smd/mx53smd.c b/board/freescale/mx53smd/mx53smd.c
deleted file mode 100644
index 2f91a05..0000000
--- a/board/freescale/mx53smd/mx53smd.c
+++ /dev/null
@@ -1,159 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * (C) Copyright 2011 Freescale Semiconductor, Inc.
- */
-
-#include <common.h>
-#include <init.h>
-#include <asm/global_data.h>
-#include <asm/io.h>
-#include <asm/arch/imx-regs.h>
-#include <asm/arch/sys_proto.h>
-#include <asm/arch/crm_regs.h>
-#include <asm/arch/clock.h>
-#include <asm/arch/iomux-mx53.h>
-#include <linux/errno.h>
-#include <netdev.h>
-#include <mmc.h>
-#include <fsl_esdhc_imx.h>
-#include <asm/gpio.h>
-
-DECLARE_GLOBAL_DATA_PTR;
-
-int dram_init(void)
-{
- u32 size1, size2;
-
- size1 = get_ram_size((void *)PHYS_SDRAM_1, PHYS_SDRAM_1_SIZE);
- size2 = get_ram_size((void *)PHYS_SDRAM_2, PHYS_SDRAM_2_SIZE);
-
- gd->ram_size = size1 + size2;
-
- return 0;
-}
-int dram_init_banksize(void)
-{
- gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
- gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE;
-
- gd->bd->bi_dram[1].start = PHYS_SDRAM_2;
- gd->bd->bi_dram[1].size = PHYS_SDRAM_2_SIZE;
-
- return 0;
-}
-
-#define UART_PAD_CTRL (PAD_CTL_HYS | PAD_CTL_DSE_HIGH | \
- PAD_CTL_PUS_100K_UP | PAD_CTL_ODE)
-
-static void setup_iomux_uart(void)
-{
- static const iomux_v3_cfg_t uart_pads[] = {
- NEW_PAD_CTRL(MX53_PAD_CSI0_DAT11__UART1_RXD_MUX, UART_PAD_CTRL),
- NEW_PAD_CTRL(MX53_PAD_CSI0_DAT10__UART1_TXD_MUX, UART_PAD_CTRL),
- };
-
- imx_iomux_v3_setup_multiple_pads(uart_pads, ARRAY_SIZE(uart_pads));
-}
-
-static void setup_iomux_fec(void)
-{
- static const iomux_v3_cfg_t fec_pads[] = {
- NEW_PAD_CTRL(MX53_PAD_FEC_MDIO__FEC_MDIO, PAD_CTL_HYS |
- PAD_CTL_DSE_HIGH | PAD_CTL_PUS_22K_UP | PAD_CTL_ODE),
- NEW_PAD_CTRL(MX53_PAD_FEC_MDC__FEC_MDC, PAD_CTL_DSE_HIGH),
- NEW_PAD_CTRL(MX53_PAD_FEC_RXD1__FEC_RDATA_1,
- PAD_CTL_HYS | PAD_CTL_PKE),
- NEW_PAD_CTRL(MX53_PAD_FEC_RXD0__FEC_RDATA_0,
- PAD_CTL_HYS | PAD_CTL_PKE),
- NEW_PAD_CTRL(MX53_PAD_FEC_TXD1__FEC_TDATA_1, PAD_CTL_DSE_HIGH),
- NEW_PAD_CTRL(MX53_PAD_FEC_TXD0__FEC_TDATA_0, PAD_CTL_DSE_HIGH),
- NEW_PAD_CTRL(MX53_PAD_FEC_TX_EN__FEC_TX_EN, PAD_CTL_DSE_HIGH),
- NEW_PAD_CTRL(MX53_PAD_FEC_REF_CLK__FEC_TX_CLK,
- PAD_CTL_HYS | PAD_CTL_PKE),
- NEW_PAD_CTRL(MX53_PAD_FEC_RX_ER__FEC_RX_ER,
- PAD_CTL_HYS | PAD_CTL_PKE),
- NEW_PAD_CTRL(MX53_PAD_FEC_CRS_DV__FEC_RX_DV,
- PAD_CTL_HYS | PAD_CTL_PKE),
- };
-
- imx_iomux_v3_setup_multiple_pads(fec_pads, ARRAY_SIZE(fec_pads));
-}
-
-#ifdef CONFIG_FSL_ESDHC_IMX
-struct fsl_esdhc_cfg esdhc_cfg[1] = {
- {MMC_SDHC1_BASE_ADDR},
-};
-
-int board_mmc_getcd(struct mmc *mmc)
-{
- imx_iomux_v3_setup_pad(MX53_PAD_EIM_DA13__GPIO3_13);
- gpio_direction_input(IMX_GPIO_NR(3, 13));
- return !gpio_get_value(IMX_GPIO_NR(3, 13));
-}
-
-#define SD_CMD_PAD_CTRL (PAD_CTL_HYS | PAD_CTL_DSE_HIGH | \
- PAD_CTL_PUS_100K_UP)
-#define SD_PAD_CTRL (PAD_CTL_HYS | PAD_CTL_PUS_47K_UP | \
- PAD_CTL_DSE_HIGH)
-
-int board_mmc_init(struct bd_info *bis)
-{
- static const iomux_v3_cfg_t sd1_pads[] = {
- NEW_PAD_CTRL(MX53_PAD_SD1_CMD__ESDHC1_CMD, SD_CMD_PAD_CTRL),
- NEW_PAD_CTRL(MX53_PAD_SD1_CLK__ESDHC1_CLK, SD_PAD_CTRL),
- NEW_PAD_CTRL(MX53_PAD_SD1_DATA0__ESDHC1_DAT0, SD_PAD_CTRL),
- NEW_PAD_CTRL(MX53_PAD_SD1_DATA1__ESDHC1_DAT1, SD_PAD_CTRL),
- NEW_PAD_CTRL(MX53_PAD_SD1_DATA2__ESDHC1_DAT2, SD_PAD_CTRL),
- NEW_PAD_CTRL(MX53_PAD_SD1_DATA3__ESDHC1_DAT3, SD_PAD_CTRL),
- MX53_PAD_EIM_DA13__GPIO3_13,
- };
-
- u32 index;
- int ret;
-
- esdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK);
-
- for (index = 0; index < CONFIG_SYS_FSL_ESDHC_NUM; index++) {
- switch (index) {
- case 0:
- imx_iomux_v3_setup_multiple_pads(sd1_pads,
- ARRAY_SIZE(sd1_pads));
- break;
-
- default:
- printf("Warning: you configured more ESDHC controller"
- "(%d) as supported by the board(1)\n",
- CONFIG_SYS_FSL_ESDHC_NUM);
- return -EINVAL;
- }
- ret = fsl_esdhc_initialize(bis, &esdhc_cfg[index]);
- if (ret)
- return ret;
- }
-
- return 0;
-}
-#endif
-
-int board_early_init_f(void)
-{
- setup_iomux_uart();
- setup_iomux_fec();
-
- return 0;
-}
-
-int board_init(void)
-{
- /* address of boot parameters */
- gd->bd->bi_boot_params = PHYS_SDRAM_1 + 0x100;
-
- return 0;
-}
-
-int checkboard(void)
-{
- puts("Board: MX53SMD\n");
-
- return 0;
-}
diff --git a/board/freescale/qemu-ppce500/MAINTAINERS b/board/freescale/qemu-ppce500/MAINTAINERS
deleted file mode 100644
index 77d0a4a..0000000
--- a/board/freescale/qemu-ppce500/MAINTAINERS
+++ /dev/null
@@ -1,6 +0,0 @@
-QEMU-PPCE500 BOARD
-M: Alexander Graf <agraf@suse.de>
-S: Maintained
-F: board/freescale/qemu-ppce500/
-F: include/configs/qemu-ppce500.h
-F: configs/qemu-ppce500_defconfig
diff --git a/board/gateworks/venice/Kconfig b/board/gateworks/venice/Kconfig
new file mode 100644
index 0000000..64cb97c
--- /dev/null
+++ b/board/gateworks/venice/Kconfig
@@ -0,0 +1,12 @@
+if TARGET_IMX8MM_VENICE
+
+config SYS_BOARD
+ default "venice"
+
+config SYS_VENDOR
+ default "gateworks"
+
+config SYS_CONFIG_NAME
+ default "imx8mm_venice"
+
+endif
diff --git a/board/gateworks/venice/MAINTAINERS b/board/gateworks/venice/MAINTAINERS
new file mode 100644
index 0000000..07b9e2a
--- /dev/null
+++ b/board/gateworks/venice/MAINTAINERS
@@ -0,0 +1,7 @@
+i.MX8MM Venice
+M: Tim Harvey <tharvey@gateworks.com>
+S: Maintained
+F: arch/arm/dts/imx8mm-venice*
+F: board/gateworks/venice/
+F: include/configs/venice.h
+F: configs/imx8mm_venice_defconfig
diff --git a/board/gateworks/venice/Makefile b/board/gateworks/venice/Makefile
new file mode 100644
index 0000000..08f5c62
--- /dev/null
+++ b/board/gateworks/venice/Makefile
@@ -0,0 +1,12 @@
+#
+# Copyright 2021 Gateworks Corporation
+#
+# SPDX-License-Identifier: GPL-2.0+
+#
+
+obj-y += imx8mm_venice.o gsc.o
+
+ifdef CONFIG_SPL_BUILD
+obj-y += spl.o
+obj-$(CONFIG_IMX8M_LPDDR4) += lpddr4_timing.o
+endif
diff --git a/board/gateworks/venice/README b/board/gateworks/venice/README
new file mode 100644
index 0000000..6a0ab1e
--- /dev/null
+++ b/board/gateworks/venice/README
@@ -0,0 +1,34 @@
+U-Boot for the Gateworks i.MX8M Mini Venice Development Kit boards
+
+Quick Start
+===========
+- Build the ARM Trusted firmware binary
+- Get ddr firmware
+- Build U-Boot
+- Flash to eMMC
+- Boot
+
+Get and Build the ARM Trusted firmware
+======================================
+$ git clone https://source.codeaurora.org/external/imx/imx-atf
+$ git checkout imx_5.4.47_2.2.0
+$ make PLAT=imx8mm CROSS_COMPILE=aarch64-linux-gnu- bl31
+$ cp build/imx8mm/release/bl31.bin .
+
+Get the DDR Firmware
+====================
+$ wget https://www.nxp.com/lgfiles/NMG/MAD/YOCTO/firmware-imx-8.9.bin
+$ chmod +x firmware-imx-8.9.bin
+$ ./firmware-imx-8.9.bin
+$ cp firmware-imx-8.9/firmware/ddr/synopsys/lpddr4*.bin .
+
+Build U-Boot
+============
+$ make imx8mm_venice_defconfig
+$ make flash.bin CROSS_COMPILE=aarch64-linux-gnu- ATF_LOAD_ADDR=0x920000
+
+Update eMMC
+===========
+=> tftpboot $loadaddr flash.bin
+=> setexpr blkcnt $filesize + 0x1ff && setexpr blkcnt $blkcnt / 0x200
+=> mmc dev 2 && mmc write $loadaddr 0x42 $blkcnt
diff --git a/board/gateworks/venice/gsc.c b/board/gateworks/venice/gsc.c
new file mode 100644
index 0000000..ad3f8d9
--- /dev/null
+++ b/board/gateworks/venice/gsc.c
@@ -0,0 +1,687 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright 2021 Gateworks Corporation
+ */
+
+#include <common.h>
+#include <command.h>
+#include <hang.h>
+#include <hexdump.h>
+#include <i2c.h>
+#include <linux/delay.h>
+#include <dm/uclass.h>
+
+#include "gsc.h"
+
+DECLARE_GLOBAL_DATA_PTR;
+
+struct venice_board_info som_info;
+struct venice_board_info base_info;
+char venice_model[32];
+
+/* return a mac address from EEPROM info */
+int gsc_getmac(int index, uint8_t *address)
+{
+ int i, j;
+ u32 maclow, machigh;
+ u64 mac;
+
+ j = 0;
+ if (som_info.macno) {
+ maclow = som_info.mac[5];
+ maclow |= som_info.mac[4] << 8;
+ maclow |= som_info.mac[3] << 16;
+ maclow |= som_info.mac[2] << 24;
+ machigh = som_info.mac[1];
+ machigh |= som_info.mac[0] << 8;
+ mac = machigh;
+ mac <<= 32;
+ mac |= maclow;
+ for (i = 0; i < som_info.macno; i++, j++) {
+ if (index == j)
+ goto out;
+ }
+ }
+
+ maclow = base_info.mac[5];
+ maclow |= base_info.mac[4] << 8;
+ maclow |= base_info.mac[3] << 16;
+ maclow |= base_info.mac[2] << 24;
+ machigh = base_info.mac[1];
+ machigh |= base_info.mac[0] << 8;
+ mac = machigh;
+ mac <<= 32;
+ mac |= maclow;
+ for (i = 0; i < base_info.macno; i++, j++) {
+ if (index == j)
+ goto out;
+ }
+
+ return -EINVAL;
+
+out:
+ mac += i;
+ address[0] = (mac >> 40) & 0xff;
+ address[1] = (mac >> 32) & 0xff;
+ address[2] = (mac >> 24) & 0xff;
+ address[3] = (mac >> 16) & 0xff;
+ address[4] = (mac >> 8) & 0xff;
+ address[5] = (mac >> 0) & 0xff;
+
+ return 0;
+}
+
+/* System Controller registers */
+enum {
+ GSC_SC_CTRL0 = 0,
+ GSC_SC_CTRL1 = 1,
+ GSC_SC_STATUS = 10,
+ GSC_SC_FWCRC = 12,
+ GSC_SC_FWVER = 14,
+ GSC_SC_WP = 15,
+ GSC_SC_RST_CAUSE = 16,
+ GSC_SC_THERM_PROTECT = 19,
+};
+
+/* System Controller Control1 bits */
+enum {
+ GSC_SC_CTRL1_WDTIME = 4, /* 1 = 60s timeout, 0 = 30s timeout */
+ GSC_SC_CTRL1_WDEN = 5, /* 1 = enable, 0 = disable */
+ GSC_SC_CTRL1_BOOT_CHK = 6, /* 1 = enable alt boot check */
+ GSC_SC_CTRL1_WDDIS = 7, /* 1 = disable boot watchdog */
+};
+
+/* System Controller Interrupt bits */
+enum {
+ GSC_SC_IRQ_PB = 0, /* Pushbutton switch */
+ GSC_SC_IRQ_SECURE = 1, /* Secure Key erase operation complete */
+ GSC_SC_IRQ_EEPROM_WP = 2, /* EEPROM write violation */
+ GSC_SC_IRQ_GPIO = 4, /* GPIO change */
+ GSC_SC_IRQ_TAMPER = 5, /* Tamper detect */
+ GSC_SC_IRQ_WATCHDOG = 6, /* Watchdog trip */
+ GSC_SC_IRQ_PBLONG = 7, /* Pushbutton long hold */
+};
+
+/* System Controller WP bits */
+enum {
+ GSC_SC_WP_ALL = 0, /* Write Protect All EEPROM regions */
+ GSC_SC_WP_BOARDINFO = 1, /* Write Protect Board Info region */
+};
+
+/* System Controller Reset Cause */
+enum {
+ GSC_SC_RST_CAUSE_VIN = 0,
+ GSC_SC_RST_CAUSE_PB = 1,
+ GSC_SC_RST_CAUSE_WDT = 2,
+ GSC_SC_RST_CAUSE_CPU = 3,
+ GSC_SC_RST_CAUSE_TEMP_LOCAL = 4,
+ GSC_SC_RST_CAUSE_TEMP_REMOTE = 5,
+ GSC_SC_RST_CAUSE_SLEEP = 6,
+ GSC_SC_RST_CAUSE_BOOT_WDT = 7,
+ GSC_SC_RST_CAUSE_BOOT_WDT_MAN = 8,
+ GSC_SC_RST_CAUSE_SOFT_PWR = 9,
+ GSC_SC_RST_CAUSE_MAX = 10,
+};
+
+static struct udevice *gsc_get_dev(int busno, int slave)
+{
+ struct udevice *dev;
+ int ret;
+
+#if (IS_ENABLED(CONFIG_SPL_BUILD))
+ ret = i2c_get_chip_for_busnum(busno + 1, slave, 1, &dev);
+ if (ret)
+ return NULL;
+#else
+ struct udevice *bus;
+
+ busno--;
+
+ ret = uclass_get_device_by_seq(UCLASS_I2C, busno, &bus);
+ if (ret) {
+ printf("i2c%d: no bus %d\n", busno + 1, ret);
+ return NULL;
+ }
+ ret = i2c_get_chip(bus, slave, 1, &dev);
+ if (ret) {
+ printf("i2c%d@0x%02x: no chip %d\n", busno + 1, slave, ret);
+ return NULL;
+ }
+#endif
+
+ return dev;
+}
+
+static int gsc_read_eeprom(int bus, int slave, int alen, struct venice_board_info *info)
+{
+ int i;
+ int chksum;
+ unsigned char *buf = (unsigned char *)info;
+ struct udevice *dev;
+ int ret;
+
+ /* probe device */
+ dev = gsc_get_dev(bus, slave);
+ if (!dev) {
+ if (slave == GSC_EEPROM_ADDR)
+ puts("ERROR: Failed to probe EEPROM\n");
+ return -ENODEV;
+ }
+
+ /* read eeprom config section */
+ memset(info, 0, sizeof(*info));
+ ret = i2c_set_chip_offset_len(dev, alen);
+ if (ret) {
+ puts("EEPROM: Failed to set alen\n");
+ return ret;
+ }
+ ret = dm_i2c_read(dev, 0x00, buf, sizeof(*info));
+ if (ret) {
+ if (slave == GSC_EEPROM_ADDR)
+ printf("EEPROM: Failed to read EEPROM\n");
+ return ret;
+ }
+
+ /* validate checksum */
+ for (chksum = 0, i = 0; i < (int)sizeof(*info) - 2; i++)
+ chksum += buf[i];
+ if ((info->chksum[0] != chksum >> 8) ||
+ (info->chksum[1] != (chksum & 0xff))) {
+ printf("EEPROM: I2C%d@0x%02x: Invalid Model in EEPROM\n", bus, slave);
+ print_hex_dump_bytes("", DUMP_PREFIX_NONE, buf, sizeof(*info));
+ memset(info, 0, sizeof(*info));
+ return -EINVAL;
+ }
+
+ /* sanity check valid model */
+ if (info->model[0] != 'G' || info->model[1] != 'W') {
+ printf("EEPROM: I2C%d@0x%02x: Invalid Model in EEPROM\n", bus, slave);
+ print_hex_dump_bytes("", DUMP_PREFIX_NONE, buf, sizeof(*info));
+ memset(info, 0, sizeof(*info));
+ return -EINVAL;
+ }
+
+ return 0;
+}
+
+static const char *gsc_get_rst_cause(struct udevice *dev)
+{
+ static char str[64];
+ static const char * const names[] = {
+ "VIN",
+ "PB",
+ "WDT",
+ "CPU",
+ "TEMP_L",
+ "TEMP_R",
+ "SLEEP",
+ "BOOT_WDT1",
+ "BOOT_WDT2",
+ "SOFT_PWR",
+ };
+ unsigned char reg;
+
+ /* reset cause */
+ str[0] = 0;
+ if (!dm_i2c_read(dev, GSC_SC_RST_CAUSE, ®, 1)) {
+ if (reg < ARRAY_SIZE(names))
+ sprintf(str, "%s", names[reg]);
+ else
+ sprintf(str, "0x%02x", reg);
+ }
+
+ /* thermal protection */
+ if (!dm_i2c_read(dev, GSC_SC_THERM_PROTECT, ®, 1)) {
+ reg |= 1;
+ dm_i2c_write(dev, GSC_SC_THERM_PROTECT, ®, 1);
+ strcat(str, " Thermal Protection Enabled");
+ }
+
+ return str;
+}
+
+/* display hardware monitor ADC channels */
+int gsc_hwmon(void)
+{
+ const void *fdt = gd->fdt_blob;
+ struct udevice *dev;
+ int node, reg, mode, len, val, offset;
+ const char *label;
+ u8 buf[2];
+ int ret;
+
+ node = fdt_node_offset_by_compatible(fdt, -1, "gw,gsc-adc");
+ if (node <= 0)
+ return node;
+
+ /* probe device */
+ dev = gsc_get_dev(1, GSC_HWMON_ADDR);
+ if (!dev) {
+ puts("ERROR: Failed to probe GSC HWMON\n");
+ return -ENODEV;
+ }
+
+ /* iterate over hwmon nodes */
+ node = fdt_first_subnode(fdt, node);
+ while (node > 0) {
+ reg = fdtdec_get_int(fdt, node, "reg", -1);
+ mode = fdtdec_get_int(fdt, node, "gw,mode", -1);
+ offset = fdtdec_get_int(fdt, node, "gw,voltage-offset-microvolt", 0);
+ label = fdt_stringlist_get(fdt, node, "label", 0, NULL);
+
+ if ((reg == -1) || (mode == -1) || !label)
+ printf("invalid dt:%s\n", fdt_get_name(fdt, node, NULL));
+
+ memset(buf, 0, sizeof(buf));
+ ret = dm_i2c_read(dev, reg, buf, sizeof(buf));
+ if (ret) {
+ printf("i2c error: %d\n", ret);
+ continue;
+ }
+ val = buf[0] | buf[1] << 8;
+ if (val >= 0) {
+ const u32 *div;
+ int r[2];
+
+ switch (mode) {
+ case 0: /* temperature (C*10) */
+ if (val > 0x8000)
+ val -= 0xffff;
+ printf("%-8s: %d.%ldC\n", label, val / 10, abs(val % 10));
+ break;
+ case 1: /* prescaled voltage */
+ if (val != 0xffff)
+ printf("%-8s: %d.%03dV\n", label, val / 1000, val % 1000);
+ break;
+ case 2: /* scaled based on ref volt and resolution */
+ val *= 2500;
+ val /= 1 << 12;
+
+ /* apply pre-scaler voltage divider */
+ div = fdt_getprop(fdt, node, "gw,voltage-divider-ohms", &len);
+ if (div && (len == sizeof(uint32_t) * 2)) {
+ r[0] = fdt32_to_cpu(div[0]);
+ r[1] = fdt32_to_cpu(div[1]);
+ if (r[0] && r[1]) {
+ val *= (r[0] + r[1]);
+ val /= r[1];
+ }
+ }
+
+ /* adjust by offset */
+ val += offset;
+
+ printf("%-8s: %d.%03dV\n", label, val / 1000, val % 1000);
+ break;
+ }
+ }
+ node = fdt_next_subnode(fdt, node);
+ }
+
+ return 0;
+}
+
+/* determine BOM revision from model */
+int get_bom_rev(const char *str)
+{
+ int rev_bom = 0;
+ int i;
+
+ for (i = strlen(str) - 1; i > 0; i--) {
+ if (str[i] == '-')
+ break;
+ if (str[i] >= '1' && str[i] <= '9') {
+ rev_bom = str[i] - '0';
+ break;
+ }
+ }
+ return rev_bom;
+}
+
+/* determine PCB revision from model */
+char get_pcb_rev(const char *str)
+{
+ char rev_pcb = 'A';
+ int i;
+
+ for (i = strlen(str) - 1; i > 0; i--) {
+ if (str[i] == '-')
+ break;
+ if (str[i] >= 'A') {
+ rev_pcb = str[i];
+ break;
+ }
+ }
+ return rev_pcb;
+}
+
+/*
+ * get dt name based on model and detail level:
+ *
+ * For boards that are a combination of a SoM plus a Baseboard:
+ * Venice SoM part numbers are GW70xx where xx is:
+ * 7000-7019: same PCB with som dt of '0x'
+ * 7020-7039: same PCB with som dt of '2x'
+ * 7040-7059: same PCB with som dt of '4x'
+ * 7060-7079: same PCB with som dt of '6x'
+ * 7080-7099: same PCB with som dt of '8x'
+ * Venice Baseboard part numbers are GW7xxx where xxx is:
+ * 7100-7199: same PCB with base dt of '71xx'
+ * 7200-7299: same PCB with base dt of '72xx'
+ * 7300-7399: same PCB with base dt of '73xx'
+ * 7400-7499: same PCB with base dt of '74xx'
+ * 7500-7599: same PCB with base dt of '75xx'
+ * 7600-7699: same PCB with base dt of '76xx'
+ * 7700-7799: same PCB with base dt of '77xx'
+ * 7800-7899: same PCB with base dt of '78xx'
+ * DT name is comprised of:
+ * gw<base dt>-<som dt>-[base-pcb-rev][base-bom-rev][som-pcb-rev][som-bom-rev]
+ *
+ * For board models from 7900-7999 each PCB is unique with its own dt:
+ * DT name is comprised:
+ * gw<model>-[pcb-rev][bom-rev]
+ *
+ */
+#define snprintfcat(dest, sz, fmt, ...) \
+ snprintf((dest) + strlen(dest), (sz) - strlen(dest), fmt, ##__VA_ARGS__)
+const char *gsc_get_dtb_name(int level, char *buf, int sz)
+{
+ const char *pre = "imx8mm-venice-gw";
+ int model, rev_pcb, rev_bom;
+
+ model = ((som_info.model[2] - '0') * 1000)
+ + ((som_info.model[3] - '0') * 100)
+ + ((som_info.model[4] - '0') * 10)
+ + (som_info.model[5] - '0');
+ rev_pcb = tolower(get_pcb_rev(som_info.model));
+ rev_bom = get_bom_rev(som_info.model);
+
+ /* som + baseboard*/
+ if (base_info.model[0]) {
+ /* baseboard id: 7100-7199->71; 7200-7299->72; etc */
+ int base = ((base_info.model[2] - '0') * 10) + (base_info.model[3] - '0');
+ /* som id: 7000-7019->1; 7020-7039->2; etc */
+ int som = ((model % 100) / 20) * 2;
+ int rev_base_pcb = tolower(get_pcb_rev(base_info.model));
+ int rev_base_bom = get_bom_rev(base_info.model);
+
+ snprintf(buf, sz, "%s%2dxx-%dx", pre, base, som);
+ switch (level) {
+ case 0: /* full model (ie gw73xx-0x-a1a1) */
+ if (rev_base_bom)
+ snprintfcat(buf, sz, "-%c%d", rev_base_pcb, rev_base_bom);
+ else
+ snprintfcat(buf, sz, "-%c", rev_base_pcb);
+ if (rev_bom)
+ snprintfcat(buf, sz, "%c%d", rev_pcb, rev_bom);
+ else
+ snprintfcat(buf, sz, "%c", rev_pcb);
+ break;
+ case 1: /* don't care about SoM revision */
+ if (rev_base_bom)
+ snprintfcat(buf, sz, "-%c%d", rev_base_pcb, rev_base_bom);
+ else
+ snprintfcat(buf, sz, "-%c", rev_base_pcb);
+ snprintfcat(buf, sz, "xx");
+ break;
+ case 2: /* don't care about baseboard revision */
+ snprintfcat(buf, sz, "-xx");
+ if (rev_bom)
+ snprintfcat(buf, sz, "%c%d", rev_pcb, rev_bom);
+ else
+ snprintfcat(buf, sz, "%c", rev_pcb);
+ break;
+ case 3: /* don't care about SoM/baseboard revision */
+ break;
+ default:
+ return NULL;
+ }
+ } else {
+ snprintf(buf, sz, "%s%04d", pre, model);
+ switch (level) {
+ case 0: /* full model wth PCB and BOM revision first (ie gw7901-a1) */
+ if (rev_bom)
+ snprintfcat(buf, sz, "-%c%d", rev_pcb, rev_bom);
+ else
+ snprintfcat(buf, sz, "-%c", rev_pcb);
+ break;
+ case 1: /* don't care about BOM revision */
+ snprintfcat(buf, sz, "-%c", rev_pcb);
+ break;
+ case 2: /* don't care about PCB or BOM revision */
+ break;
+ default:
+ return NULL;
+ }
+ }
+
+ return buf;
+}
+
+static int gsc_read(void)
+{
+ int ret;
+
+ ret = gsc_read_eeprom(1, GSC_EEPROM_ADDR, 1, &som_info);
+ if (ret) {
+ memset(&som_info, 0, sizeof(som_info));
+ return ret;
+ }
+
+ /* read optional baseboard EEPROM */
+ return gsc_read_eeprom(2, 0x52, 2, &base_info);
+}
+
+static int gsc_info(int verbose)
+{
+ struct udevice *dev;
+ unsigned char buf[16];
+ char rev_pcb;
+ int rev_bom;
+
+ if (!base_info.model[0]) {
+ strcpy(venice_model, som_info.model);
+ printf("Model : %s\n", som_info.model);
+ printf("Serial : %d\n", som_info.serial);
+ printf("MFGDate : %02x-%02x-%02x%02x\n",
+ som_info.mfgdate[0], som_info.mfgdate[1],
+ som_info.mfgdate[2], som_info.mfgdate[3]);
+ } else {
+ sprintf(venice_model, "GW%c%c%c%c-%c%c-",
+ som_info.model[2], /* family */
+ base_info.model[3], /* baseboard */
+ base_info.model[4], base_info.model[5], /* subload of baseboard */
+ som_info.model[4], som_info.model[5]); /* last 2digits of SOM */
+
+ /* baseboard revision */
+ rev_pcb = get_pcb_rev(base_info.model);
+ rev_bom = get_bom_rev(base_info.model);
+ if (rev_bom)
+ sprintf(venice_model + strlen(venice_model), "%c%d", rev_pcb, rev_bom);
+ else
+ sprintf(venice_model + strlen(venice_model), "%c", rev_pcb);
+ /* som revision */
+ rev_pcb = get_pcb_rev(som_info.model);
+ rev_bom = get_bom_rev(som_info.model);
+ if (rev_bom)
+ sprintf(venice_model + strlen(venice_model), "%c%d", rev_pcb, rev_bom);
+ else
+ sprintf(venice_model + strlen(venice_model), "%c", rev_pcb);
+
+ if (verbose > 1) {
+ printf("SOM : %s %d %02x-%02x-%02x%02x\n",
+ som_info.model, som_info.serial,
+ som_info.mfgdate[0], som_info.mfgdate[1],
+ som_info.mfgdate[2], som_info.mfgdate[3]);
+ printf("BASE : %s %d %02x-%02x-%02x%02x\n",
+ base_info.model, base_info.serial,
+ base_info.mfgdate[0], base_info.mfgdate[1],
+ base_info.mfgdate[2], base_info.mfgdate[3]);
+ }
+ printf("Model : %s\n", venice_model);
+ printf("Serial : %d\n", som_info.serial);
+ printf("MFGDate : %02x-%02x-%02x%02x\n",
+ som_info.mfgdate[0], som_info.mfgdate[1],
+ som_info.mfgdate[2], som_info.mfgdate[3]);
+ }
+
+ /* Display RTC */
+ puts("RTC : ");
+ dev = gsc_get_dev(1, GSC_RTC_ADDR);
+ if (!dev) {
+ puts("Failed to probe GSC RTC\n");
+ } else {
+ dm_i2c_read(dev, 0, buf, 6);
+ printf("%d\n", buf[0] | buf[1] << 8 | buf[2] << 16 | buf[3] << 24);
+ }
+
+ return 0;
+}
+
+int gsc_init(int quiet)
+{
+ unsigned char buf[16];
+ struct udevice *dev;
+ int ret;
+
+ /*
+ * On a board with a missing/depleted backup battery for GSC, the
+ * board may be ready to probe the GSC before its firmware is
+ * running. We will wait here indefinately for the GSC/EEPROM.
+ */
+ while (1) {
+ /* probe device */
+ dev = gsc_get_dev(1, GSC_SC_ADDR);
+ if (dev)
+ break;
+ mdelay(1);
+ }
+
+ ret = dm_i2c_read(dev, 0, buf, sizeof(buf));
+ if (ret) {
+ puts("ERROR: Failed reading GSC\n");
+ return ret;
+ }
+ gsc_read();
+
+ /* banner */
+ if (!quiet) {
+ printf("GSC : v%d 0x%04x", buf[GSC_SC_FWVER],
+ buf[GSC_SC_FWCRC] | buf[GSC_SC_FWCRC + 1] << 8);
+ printf(" RST:%s", gsc_get_rst_cause(dev));
+ printf("\n");
+ gsc_info(1);
+ }
+
+ if (ret)
+ hang();
+
+ return ((16 << som_info.sdram_size) / 1024);
+}
+
+const char *gsc_get_model(void)
+{
+ return venice_model;
+}
+
+#if !(IS_ENABLED(CONFIG_SPL_BUILD))
+static int gsc_sleep(unsigned long secs)
+{
+ unsigned char reg;
+ struct udevice *dev;
+ int ret;
+
+ /* probe device */
+ dev = gsc_get_dev(1, GSC_SC_ADDR);
+ if (!dev)
+ return -ENODEV;
+
+ printf("GSC Sleeping for %ld seconds\n", secs);
+ reg = (secs >> 24) & 0xff;
+ ret = dm_i2c_write(dev, 9, ®, 1);
+ if (ret)
+ goto err;
+ reg = (secs >> 16) & 0xff;
+ ret = dm_i2c_write(dev, 8, ®, 1);
+ if (ret)
+ goto err;
+ reg = (secs >> 8) & 0xff;
+ ret = dm_i2c_write(dev, 7, ®, 1);
+ if (ret)
+ goto err;
+ reg = secs & 0xff;
+ ret = dm_i2c_write(dev, 6, ®, 1);
+ if (ret)
+ goto err;
+ ret = dm_i2c_read(dev, GSC_SC_CTRL1, ®, 1);
+ if (ret)
+ goto err;
+ reg |= (1 << 2);
+ ret = dm_i2c_write(dev, GSC_SC_CTRL1, ®, 1);
+ if (ret)
+ goto err;
+ reg &= ~(1 << 2);
+ reg |= 0x3;
+ ret = dm_i2c_write(dev, GSC_SC_CTRL1, ®, 1);
+ if (ret)
+ goto err;
+
+ return 0;
+
+err:
+ printf("i2c error\n");
+ return ret;
+}
+
+static int gsc_boot_wd_disable(void)
+{
+ u8 reg;
+ struct udevice *dev;
+ int ret;
+
+ /* probe device */
+ dev = gsc_get_dev(1, GSC_SC_ADDR);
+ if (!dev)
+ return -ENODEV;
+
+ ret = dm_i2c_read(dev, GSC_SC_CTRL1, ®, 1);
+ if (ret)
+ goto err;
+ reg |= (1 << GSC_SC_CTRL1_WDDIS);
+ reg &= ~(1 << GSC_SC_CTRL1_BOOT_CHK);
+ ret = dm_i2c_write(dev, GSC_SC_CTRL1, ®, 1);
+ if (ret)
+ goto err;
+ puts("GSC : boot watchdog disabled\n");
+
+ return 0;
+
+err:
+ printf("i2c error");
+ return ret;
+}
+
+static int do_gsc(struct cmd_tbl *cmdtp, int flag, int argc, char * const argv[])
+{
+ if (argc < 2)
+ return gsc_info(2);
+
+ if (strcasecmp(argv[1], "sleep") == 0) {
+ if (argc < 3)
+ return CMD_RET_USAGE;
+ if (!gsc_sleep(simple_strtoul(argv[2], NULL, 10)))
+ return CMD_RET_SUCCESS;
+ } else if (strcasecmp(argv[1], "hwmon") == 0) {
+ if (!gsc_hwmon())
+ return CMD_RET_SUCCESS;
+ } else if (strcasecmp(argv[1], "wd-disable") == 0) {
+ if (!gsc_boot_wd_disable())
+ return CMD_RET_SUCCESS;
+ }
+
+ return CMD_RET_USAGE;
+}
+
+U_BOOT_CMD(gsc, 4, 1, do_gsc, "Gateworks System Controller",
+ "[sleep <secs>]|[hwmon]|[wd-disable]\n");
+#endif
diff --git a/board/gateworks/venice/gsc.h b/board/gateworks/venice/gsc.h
new file mode 100644
index 0000000..27b0211
--- /dev/null
+++ b/board/gateworks/venice/gsc.h
@@ -0,0 +1,39 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright 2021 Gateworks Corporation
+ */
+
+#ifndef _GSC_H_
+#define _GSC_H_
+
+/* I2C slave addresses */
+#define GSC_SC_ADDR 0x20
+#define GSC_RTC_ADDR 0x68
+#define GSC_HWMON_ADDR 0x29
+#define GSC_EEPROM_ADDR 0x51
+
+struct venice_board_info {
+ u8 mac[6]; /* 0x00: MAC base */
+ char equiv_dts[16]; /* 0x06: equivalent device-tree */
+ u8 res0[2]; /* 0x16: reserved */
+ u32 serial; /* 0x18: Serial Number */
+ u8 res1[4]; /* 0x1C: reserved */
+ u8 mfgdate[4]; /* 0x20: MFG date */
+ u8 macno; /* 0x24: number of mac addrs */
+ u8 res2[6]; /* 0x25 */
+ u8 sdram_size; /* 0x2B: (16 << n) MB */
+ u8 sdram_speed; /* 0x2C: (33.333 * n) MHz */
+ u8 sdram_width; /* 0x2D: (8 << n) bit */
+ u8 res3[2]; /* 0x2E */
+ char model[16]; /* 0x30: model string */
+ u8 res4[14]; /* 0x40 */
+ u8 chksum[2]; /* 0x4E */
+};
+
+int gsc_init(int quiet);
+int gsc_hwmon(void);
+const char *gsc_get_model(void);
+const char *gsc_get_dtb_name(int level, char *buf, int len);
+int gsc_getmac(int index, uint8_t *enetaddr);
+
+#endif
diff --git a/board/gateworks/venice/imx8mm_venice.c b/board/gateworks/venice/imx8mm_venice.c
new file mode 100644
index 0000000..1d51b6e
--- /dev/null
+++ b/board/gateworks/venice/imx8mm_venice.c
@@ -0,0 +1,133 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright 2021 Gateworks Corporation
+ */
+
+#include <common.h>
+#include <init.h>
+#include <led.h>
+#include <linux/delay.h>
+#include <miiphy.h>
+#include <netdev.h>
+
+#include <asm/arch/clock.h>
+#include <asm/arch/sys_proto.h>
+#include <asm/io.h>
+
+#include "gsc.h"
+
+DECLARE_GLOBAL_DATA_PTR;
+
+int board_phys_sdram_size(phys_size_t *size)
+{
+ int ddr_size = readl(M4_BOOTROM_BASE_ADDR);
+
+ if (ddr_size == 0x4) {
+ *size = 0x100000000;
+ } else if (ddr_size == 0x3) {
+ *size = 0xc0000000;
+ } else if (ddr_size == 0x2) {
+ *size = 0x80000000;
+ } else if (ddr_size == 0x1) {
+ *size = 0x40000000;
+ } else {
+ printf("Unknown DDR type!!!\n");
+ *size = 0x40000000;
+ }
+
+ return 0;
+}
+
+int board_fit_config_name_match(const char *name)
+{
+ int i = 0;
+ const char *dtb;
+ char buf[32];
+
+ do {
+ dtb = gsc_get_dtb_name(i++, buf, sizeof(buf));
+ if (!strcmp(dtb, name))
+ return 0;
+ } while (dtb);
+
+ return -1;
+}
+
+#if (IS_ENABLED(CONFIG_FEC_MXC))
+static int setup_fec(void)
+{
+ struct iomuxc_gpr_base_regs *gpr =
+ (struct iomuxc_gpr_base_regs *)IOMUXC_GPR_BASE_ADDR;
+
+ /* Use 125M anatop REF_CLK1 for ENET1, not from external */
+ clrsetbits_le32(&gpr->gpr[1], 0x2000, 0);
+
+ return 0;
+}
+
+int board_phy_config(struct phy_device *phydev)
+{
+ unsigned short val;
+
+ switch (phydev->phy_id) {
+ case 0x2000a231: /* TI DP83867 GbE PHY */
+ puts("DP83867 ");
+ /* LED configuration */
+ val = 0;
+ val |= 0x5 << 4; /* LED1(Amber;Speed) : 1000BT link */
+ val |= 0xb << 8; /* LED2(Green;Link/Act): blink for TX/RX act */
+ phy_write(phydev, MDIO_DEVAD_NONE, 24, val);
+ break;
+ }
+
+ if (phydev->drv->config)
+ phydev->drv->config(phydev);
+
+ return 0;
+}
+#endif // IS_ENABLED(CONFIG_FEC_MXC)
+
+int board_init(void)
+{
+ gsc_init(1);
+
+ if (IS_ENABLED(CONFIG_FEC_MXC))
+ setup_fec();
+
+ gsc_hwmon();
+
+ return 0;
+}
+
+int board_late_init(void)
+{
+ const char *ethmac;
+ char env[32];
+ int ret, i;
+ u8 enetaddr[6];
+
+ led_default_state();
+
+ /* Set mac addrs */
+ i = 0;
+ do {
+ if (i)
+ sprintf(env, "eth%daddr", i);
+ else
+ sprintf(env, "ethaddr");
+ ethmac = env_get(env);
+ if (!ethmac) {
+ ret = gsc_getmac(i, enetaddr);
+ if (!ret)
+ eth_env_set_enetaddr(env, enetaddr);
+ }
+ i++;
+ } while (!ret);
+
+ return 0;
+}
+
+int board_mmc_get_env_dev(int devno)
+{
+ return devno;
+}
diff --git a/board/gateworks/venice/lpddr4_timing.c b/board/gateworks/venice/lpddr4_timing.c
new file mode 100644
index 0000000..47e93e1
--- /dev/null
+++ b/board/gateworks/venice/lpddr4_timing.c
@@ -0,0 +1,2505 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright 2021 Gateworks Corporation
+ *
+ * Generated code from MX8M_DDR_tool
+ */
+
+#include <linux/kernel.h>
+#include <common.h>
+#include <asm/arch/ddr.h>
+#include <asm/arch/lpddr4_define.h>
+
+static struct dram_cfg_param lpddr4_ddrc_cfg_1gb[] = {
+ /** Initialize DDRC registers **/
+ { 0x3d400304, 0x1 },
+ { 0x3d400030, 0x1 },
+ { 0x3d400000, 0xa1080020 },
+ { 0x3d400020, 0x223 },
+ { 0x3d400024, 0x3a980 },
+ { 0x3d400064, 0x5b0087 },
+ { 0x3d4000d0, 0xc00305ba },
+ { 0x3d4000d4, 0x940000 },
+ { 0x3d4000dc, 0xd4002d },
+ { 0x3d4000e0, 0x310000 },
+ { 0x3d4000e8, 0x66004d },
+ { 0x3d4000ec, 0x16004d },
+ { 0x3d400100, 0x191e1920 },
+ { 0x3d400104, 0x60630 },
+ { 0x3d40010c, 0xb0b000 },
+ { 0x3d400110, 0xe04080e },
+ { 0x3d400114, 0x2040c0c },
+ { 0x3d400118, 0x1010007 },
+ { 0x3d40011c, 0x401 },
+ { 0x3d400130, 0x20600 },
+ { 0x3d400134, 0xc100002 },
+ { 0x3d400138, 0x8d },
+ { 0x3d400144, 0x96004b },
+ { 0x3d400180, 0x2ee0017 },
+ { 0x3d400184, 0x2605b8e },
+ { 0x3d400188, 0x0 },
+ { 0x3d400190, 0x497820a },
+ { 0x3d400194, 0x80303 },
+ { 0x3d4001b4, 0x170a },
+ { 0x3d4001a0, 0xe0400018 },
+ { 0x3d4001a4, 0xdf00e4 },
+ { 0x3d4001a8, 0x80000000 },
+ { 0x3d4001b0, 0x11 },
+ { 0x3d4001c0, 0x1 },
+ { 0x3d4001c4, 0x1 },
+ { 0x3d4000f4, 0xc99 },
+ { 0x3d400108, 0x70e1617 },
+ { 0x3d400200, 0x1f },
+ { 0x3d40020c, 0x0 },
+ { 0x3d400210, 0x1f1f },
+ { 0x3d400204, 0x80808 },
+ { 0x3d400214, 0x7070707 },
+ { 0x3d400218, 0xf070707 },
+ { 0x3d400250, 0x29001701 },
+ { 0x3d400254, 0x2c },
+ { 0x3d40025c, 0x4000030 },
+ { 0x3d400264, 0x900093e7 },
+ { 0x3d40026c, 0x2005574 },
+ { 0x3d400400, 0x111 },
+ { 0x3d400408, 0x72ff },
+ { 0x3d400494, 0x2100e07 },
+ { 0x3d400498, 0x620096 },
+ { 0x3d40049c, 0x1100e07 },
+ { 0x3d4004a0, 0xc8012c },
+ { 0x3d402020, 0x21 },
+ { 0x3d402024, 0x7d00 },
+ { 0x3d402050, 0x20d040 },
+ { 0x3d402064, 0xc0012 },
+ { 0x3d4020dc, 0x840000 },
+ { 0x3d4020e0, 0x310000 },
+ { 0x3d4020e8, 0x66004d },
+ { 0x3d4020ec, 0x16004d },
+ { 0x3d402100, 0xa040305 },
+ { 0x3d402104, 0x30407 },
+ { 0x3d402108, 0x203060b },
+ { 0x3d40210c, 0x505000 },
+ { 0x3d402110, 0x2040202 },
+ { 0x3d402114, 0x2030202 },
+ { 0x3d402118, 0x1010004 },
+ { 0x3d40211c, 0x301 },
+ { 0x3d402130, 0x20300 },
+ { 0x3d402134, 0xa100002 },
+ { 0x3d402138, 0x13 },
+ { 0x3d402144, 0x14000a },
+ { 0x3d402180, 0x640004 },
+ { 0x3d402190, 0x3818200 },
+ { 0x3d402194, 0x80303 },
+ { 0x3d4021b4, 0x100 },
+ { 0x3d4020f4, 0xc99 },
+ { 0x3d403020, 0x21 },
+ { 0x3d403024, 0x1f40 },
+ { 0x3d403050, 0x20d040 },
+ { 0x3d403064, 0x30005 },
+ { 0x3d4030dc, 0x840000 },
+ { 0x3d4030e0, 0x310000 },
+ { 0x3d4030e8, 0x66004d },
+ { 0x3d4030ec, 0x16004d },
+ { 0x3d403100, 0xa010102 },
+ { 0x3d403104, 0x30404 },
+ { 0x3d403108, 0x203060b },
+ { 0x3d40310c, 0x505000 },
+ { 0x3d403110, 0x2040202 },
+ { 0x3d403114, 0x2030202 },
+ { 0x3d403118, 0x1010004 },
+ { 0x3d40311c, 0x301 },
+ { 0x3d403130, 0x20300 },
+ { 0x3d403134, 0xa100002 },
+ { 0x3d403138, 0x5 },
+ { 0x3d403144, 0x50003 },
+ { 0x3d403180, 0x190004 },
+ { 0x3d403190, 0x3818200 },
+ { 0x3d403194, 0x80303 },
+ { 0x3d4031b4, 0x100 },
+ { 0x3d4030f4, 0xc99 },
+ { 0x3d400028, 0x0 },
+};
+
+/* PHY Initialize Configuration */
+static struct dram_cfg_param lpddr4_ddrphy_cfg_1gb[] = {
+ { 0x100a0, 0x0 },
+ { 0x100a1, 0x1 },
+ { 0x100a2, 0x2 },
+ { 0x100a3, 0x3 },
+ { 0x100a4, 0x4 },
+ { 0x100a5, 0x5 },
+ { 0x100a6, 0x6 },
+ { 0x100a7, 0x7 },
+ { 0x110a0, 0x0 },
+ { 0x110a1, 0x1 },
+ { 0x110a2, 0x3 },
+ { 0x110a3, 0x4 },
+ { 0x110a4, 0x5 },
+ { 0x110a5, 0x2 },
+ { 0x110a6, 0x7 },
+ { 0x110a7, 0x6 },
+ { 0x120a0, 0x0 },
+ { 0x120a1, 0x1 },
+ { 0x120a2, 0x3 },
+ { 0x120a3, 0x2 },
+ { 0x120a4, 0x5 },
+ { 0x120a5, 0x4 },
+ { 0x120a6, 0x7 },
+ { 0x120a7, 0x6 },
+ { 0x130a0, 0x0 },
+ { 0x130a1, 0x1 },
+ { 0x130a2, 0x2 },
+ { 0x130a3, 0x3 },
+ { 0x130a4, 0x4 },
+ { 0x130a5, 0x5 },
+ { 0x130a6, 0x6 },
+ { 0x130a7, 0x7 },
+ { 0x1005f, 0x1ff },
+ { 0x1015f, 0x1ff },
+ { 0x1105f, 0x1ff },
+ { 0x1115f, 0x1ff },
+ { 0x1205f, 0x1ff },
+ { 0x1215f, 0x1ff },
+ { 0x1305f, 0x1ff },
+ { 0x1315f, 0x1ff },
+ { 0x11005f, 0x1ff },
+ { 0x11015f, 0x1ff },
+ { 0x11105f, 0x1ff },
+ { 0x11115f, 0x1ff },
+ { 0x11205f, 0x1ff },
+ { 0x11215f, 0x1ff },
+ { 0x11305f, 0x1ff },
+ { 0x11315f, 0x1ff },
+ { 0x21005f, 0x1ff },
+ { 0x21015f, 0x1ff },
+ { 0x21105f, 0x1ff },
+ { 0x21115f, 0x1ff },
+ { 0x21205f, 0x1ff },
+ { 0x21215f, 0x1ff },
+ { 0x21305f, 0x1ff },
+ { 0x21315f, 0x1ff },
+ { 0x55, 0x1ff },
+ { 0x1055, 0x1ff },
+ { 0x2055, 0x1ff },
+ { 0x3055, 0x1ff },
+ { 0x4055, 0x1ff },
+ { 0x5055, 0x1ff },
+ { 0x6055, 0x1ff },
+ { 0x7055, 0x1ff },
+ { 0x8055, 0x1ff },
+ { 0x9055, 0x1ff },
+ { 0x200c5, 0x19 },
+ { 0x1200c5, 0x7 },
+ { 0x2200c5, 0x7 },
+ { 0x2002e, 0x2 },
+ { 0x12002e, 0x2 },
+ { 0x22002e, 0x2 },
+ { 0x90204, 0x0 },
+ { 0x190204, 0x0 },
+ { 0x290204, 0x0 },
+ { 0x20024, 0x1ab },
+ { 0x2003a, 0x0 },
+ { 0x120024, 0x1ab },
+ { 0x2003a, 0x0 },
+ { 0x220024, 0x1ab },
+ { 0x2003a, 0x0 },
+ { 0x20056, 0x3 },
+ { 0x120056, 0x3 },
+ { 0x220056, 0x3 },
+ { 0x1004d, 0xe00 },
+ { 0x1014d, 0xe00 },
+ { 0x1104d, 0xe00 },
+ { 0x1114d, 0xe00 },
+ { 0x1204d, 0xe00 },
+ { 0x1214d, 0xe00 },
+ { 0x1304d, 0xe00 },
+ { 0x1314d, 0xe00 },
+ { 0x11004d, 0xe00 },
+ { 0x11014d, 0xe00 },
+ { 0x11104d, 0xe00 },
+ { 0x11114d, 0xe00 },
+ { 0x11204d, 0xe00 },
+ { 0x11214d, 0xe00 },
+ { 0x11304d, 0xe00 },
+ { 0x11314d, 0xe00 },
+ { 0x21004d, 0xe00 },
+ { 0x21014d, 0xe00 },
+ { 0x21104d, 0xe00 },
+ { 0x21114d, 0xe00 },
+ { 0x21204d, 0xe00 },
+ { 0x21214d, 0xe00 },
+ { 0x21304d, 0xe00 },
+ { 0x21314d, 0xe00 },
+ { 0x10049, 0xeba },
+ { 0x10149, 0xeba },
+ { 0x11049, 0xeba },
+ { 0x11149, 0xeba },
+ { 0x12049, 0xeba },
+ { 0x12149, 0xeba },
+ { 0x13049, 0xeba },
+ { 0x13149, 0xeba },
+ { 0x110049, 0xeba },
+ { 0x110149, 0xeba },
+ { 0x111049, 0xeba },
+ { 0x111149, 0xeba },
+ { 0x112049, 0xeba },
+ { 0x112149, 0xeba },
+ { 0x113049, 0xeba },
+ { 0x113149, 0xeba },
+ { 0x210049, 0xeba },
+ { 0x210149, 0xeba },
+ { 0x211049, 0xeba },
+ { 0x211149, 0xeba },
+ { 0x212049, 0xeba },
+ { 0x212149, 0xeba },
+ { 0x213049, 0xeba },
+ { 0x213149, 0xeba },
+ { 0x43, 0x63 },
+ { 0x1043, 0x63 },
+ { 0x2043, 0x63 },
+ { 0x3043, 0x63 },
+ { 0x4043, 0x63 },
+ { 0x5043, 0x63 },
+ { 0x6043, 0x63 },
+ { 0x7043, 0x63 },
+ { 0x8043, 0x63 },
+ { 0x9043, 0x63 },
+ { 0x20018, 0x3 },
+ { 0x20075, 0x4 },
+ { 0x20050, 0x0 },
+ { 0x20008, 0x2ee },
+ { 0x120008, 0x64 },
+ { 0x220008, 0x19 },
+ { 0x20088, 0x9 },
+ { 0x200b2, 0xdc },
+ { 0x10043, 0x5a1 },
+ { 0x10143, 0x5a1 },
+ { 0x11043, 0x5a1 },
+ { 0x11143, 0x5a1 },
+ { 0x12043, 0x5a1 },
+ { 0x12143, 0x5a1 },
+ { 0x13043, 0x5a1 },
+ { 0x13143, 0x5a1 },
+ { 0x1200b2, 0xdc },
+ { 0x110043, 0x5a1 },
+ { 0x110143, 0x5a1 },
+ { 0x111043, 0x5a1 },
+ { 0x111143, 0x5a1 },
+ { 0x112043, 0x5a1 },
+ { 0x112143, 0x5a1 },
+ { 0x113043, 0x5a1 },
+ { 0x113143, 0x5a1 },
+ { 0x2200b2, 0xdc },
+ { 0x210043, 0x5a1 },
+ { 0x210143, 0x5a1 },
+ { 0x211043, 0x5a1 },
+ { 0x211143, 0x5a1 },
+ { 0x212043, 0x5a1 },
+ { 0x212143, 0x5a1 },
+ { 0x213043, 0x5a1 },
+ { 0x213143, 0x5a1 },
+ { 0x200fa, 0x1 },
+ { 0x1200fa, 0x1 },
+ { 0x2200fa, 0x1 },
+ { 0x20019, 0x1 },
+ { 0x120019, 0x1 },
+ { 0x220019, 0x1 },
+ { 0x200f0, 0x660 },
+ { 0x200f1, 0x0 },
+ { 0x200f2, 0x4444 },
+ { 0x200f3, 0x8888 },
+ { 0x200f4, 0x5665 },
+ { 0x200f5, 0x0 },
+ { 0x200f6, 0x0 },
+ { 0x200f7, 0xf000 },
+ { 0x20025, 0x0 },
+ { 0x2002d, 0x0 },
+ { 0x12002d, 0x0 },
+ { 0x22002d, 0x0 },
+ { 0x200c7, 0x21 },
+ { 0x200ca, 0x24 },
+ { 0x1200c7, 0x21 },
+ { 0x1200ca, 0x24 },
+ { 0x2200c7, 0x21 },
+ { 0x2200ca, 0x24 },
+};
+
+/* ddr phy trained csr */
+static struct dram_cfg_param lpddr4_ddrphy_trained_csr[] = {
+ { 0x200b2, 0x0 },
+ { 0x1200b2, 0x0 },
+ { 0x2200b2, 0x0 },
+ { 0x200cb, 0x0 },
+ { 0x10043, 0x0 },
+ { 0x110043, 0x0 },
+ { 0x210043, 0x0 },
+ { 0x10143, 0x0 },
+ { 0x110143, 0x0 },
+ { 0x210143, 0x0 },
+ { 0x11043, 0x0 },
+ { 0x111043, 0x0 },
+ { 0x211043, 0x0 },
+ { 0x11143, 0x0 },
+ { 0x111143, 0x0 },
+ { 0x211143, 0x0 },
+ { 0x12043, 0x0 },
+ { 0x112043, 0x0 },
+ { 0x212043, 0x0 },
+ { 0x12143, 0x0 },
+ { 0x112143, 0x0 },
+ { 0x212143, 0x0 },
+ { 0x13043, 0x0 },
+ { 0x113043, 0x0 },
+ { 0x213043, 0x0 },
+ { 0x13143, 0x0 },
+ { 0x113143, 0x0 },
+ { 0x213143, 0x0 },
+ { 0x80, 0x0 },
+ { 0x100080, 0x0 },
+ { 0x200080, 0x0 },
+ { 0x1080, 0x0 },
+ { 0x101080, 0x0 },
+ { 0x201080, 0x0 },
+ { 0x2080, 0x0 },
+ { 0x102080, 0x0 },
+ { 0x202080, 0x0 },
+ { 0x3080, 0x0 },
+ { 0x103080, 0x0 },
+ { 0x203080, 0x0 },
+ { 0x4080, 0x0 },
+ { 0x104080, 0x0 },
+ { 0x204080, 0x0 },
+ { 0x5080, 0x0 },
+ { 0x105080, 0x0 },
+ { 0x205080, 0x0 },
+ { 0x6080, 0x0 },
+ { 0x106080, 0x0 },
+ { 0x206080, 0x0 },
+ { 0x7080, 0x0 },
+ { 0x107080, 0x0 },
+ { 0x207080, 0x0 },
+ { 0x8080, 0x0 },
+ { 0x108080, 0x0 },
+ { 0x208080, 0x0 },
+ { 0x9080, 0x0 },
+ { 0x109080, 0x0 },
+ { 0x209080, 0x0 },
+ { 0x10080, 0x0 },
+ { 0x110080, 0x0 },
+ { 0x210080, 0x0 },
+ { 0x10180, 0x0 },
+ { 0x110180, 0x0 },
+ { 0x210180, 0x0 },
+ { 0x11080, 0x0 },
+ { 0x111080, 0x0 },
+ { 0x211080, 0x0 },
+ { 0x11180, 0x0 },
+ { 0x111180, 0x0 },
+ { 0x211180, 0x0 },
+ { 0x12080, 0x0 },
+ { 0x112080, 0x0 },
+ { 0x212080, 0x0 },
+ { 0x12180, 0x0 },
+ { 0x112180, 0x0 },
+ { 0x212180, 0x0 },
+ { 0x13080, 0x0 },
+ { 0x113080, 0x0 },
+ { 0x213080, 0x0 },
+ { 0x13180, 0x0 },
+ { 0x113180, 0x0 },
+ { 0x213180, 0x0 },
+ { 0x10081, 0x0 },
+ { 0x110081, 0x0 },
+ { 0x210081, 0x0 },
+ { 0x10181, 0x0 },
+ { 0x110181, 0x0 },
+ { 0x210181, 0x0 },
+ { 0x11081, 0x0 },
+ { 0x111081, 0x0 },
+ { 0x211081, 0x0 },
+ { 0x11181, 0x0 },
+ { 0x111181, 0x0 },
+ { 0x211181, 0x0 },
+ { 0x12081, 0x0 },
+ { 0x112081, 0x0 },
+ { 0x212081, 0x0 },
+ { 0x12181, 0x0 },
+ { 0x112181, 0x0 },
+ { 0x212181, 0x0 },
+ { 0x13081, 0x0 },
+ { 0x113081, 0x0 },
+ { 0x213081, 0x0 },
+ { 0x13181, 0x0 },
+ { 0x113181, 0x0 },
+ { 0x213181, 0x0 },
+ { 0x100d0, 0x0 },
+ { 0x1100d0, 0x0 },
+ { 0x2100d0, 0x0 },
+ { 0x101d0, 0x0 },
+ { 0x1101d0, 0x0 },
+ { 0x2101d0, 0x0 },
+ { 0x110d0, 0x0 },
+ { 0x1110d0, 0x0 },
+ { 0x2110d0, 0x0 },
+ { 0x111d0, 0x0 },
+ { 0x1111d0, 0x0 },
+ { 0x2111d0, 0x0 },
+ { 0x120d0, 0x0 },
+ { 0x1120d0, 0x0 },
+ { 0x2120d0, 0x0 },
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+ { 0x13640, 0x0 },
+ { 0x13740, 0x0 },
+ { 0x13840, 0x0 },
+ { 0x13030, 0x0 },
+ { 0x13130, 0x0 },
+ { 0x13230, 0x0 },
+ { 0x13330, 0x0 },
+ { 0x13430, 0x0 },
+ { 0x13530, 0x0 },
+ { 0x13630, 0x0 },
+ { 0x13730, 0x0 },
+ { 0x13830, 0x0 },
+};
+
+/* P0 message block paremeter for training firmware */
+static struct dram_cfg_param lpddr4_fsp0_cfg_1gb[] = {
+ { 0xd0000, 0x0 },
+ { 0x54000, 0x0 },
+ { 0x54001, 0x0 },
+ { 0x54002, 0x0 },
+ { 0x54003, 0xbb8 },
+ { 0x54004, 0x2 },
+ { 0x54005, 0x2228 },
+ { 0x54006, 0x11 },
+ { 0x54007, 0x0 },
+ { 0x54008, 0x131f },
+ { 0x54009, 0xc8 },
+ { 0x5400a, 0x0 },
+ { 0x5400b, 0x2 },
+ { 0x5400c, 0x0 },
+ { 0x5400d, 0x0 },
+ { 0x5400e, 0x0 },
+ { 0x5400f, 0x0 },
+ { 0x54010, 0x0 },
+ { 0x54011, 0x0 },
+ { 0x54012, 0x110 },
+ { 0x54013, 0x0 },
+ { 0x54014, 0x0 },
+ { 0x54015, 0x0 },
+ { 0x54016, 0x0 },
+ { 0x54017, 0x0 },
+ { 0x54018, 0x0 },
+ { 0x54019, 0x2dd4 },
+ { 0x5401a, 0x31 },
+ { 0x5401b, 0x4d66 },
+ { 0x5401c, 0x4d00 },
+ { 0x5401d, 0x0 },
+ { 0x5401e, 0x16 },
+ { 0x5401f, 0x2dd4 },
+ { 0x54020, 0x31 },
+ { 0x54021, 0x4d66 },
+ { 0x54022, 0x4d00 },
+ { 0x54023, 0x0 },
+ { 0x54024, 0x16 },
+ { 0x54025, 0x0 },
+ { 0x54026, 0x0 },
+ { 0x54027, 0x0 },
+ { 0x54028, 0x0 },
+ { 0x54029, 0x0 },
+ { 0x5402a, 0x0 },
+ { 0x5402b, 0x1000 },
+ { 0x5402c, 0x1 },
+ { 0x5402d, 0x0 },
+ { 0x5402e, 0x0 },
+ { 0x5402f, 0x0 },
+ { 0x54030, 0x0 },
+ { 0x54031, 0x0 },
+ { 0x54032, 0xd400 },
+ { 0x54033, 0x312d },
+ { 0x54034, 0x6600 },
+ { 0x54035, 0x4d },
+ { 0x54036, 0x4d },
+ { 0x54037, 0x1600 },
+ { 0x54038, 0xd400 },
+ { 0x54039, 0x312d },
+ { 0x5403a, 0x6600 },
+ { 0x5403b, 0x4d },
+ { 0x5403c, 0x4d },
+ { 0x5403d, 0x1600 },
+ { 0x5403e, 0x0 },
+ { 0x5403f, 0x0 },
+ { 0x54040, 0x0 },
+ { 0x54041, 0x0 },
+ { 0x54042, 0x0 },
+ { 0x54043, 0x0 },
+ { 0x54044, 0x0 },
+ { 0xd0000, 0x1 },
+};
+
+/* P1 message block paremeter for training firmware */
+static struct dram_cfg_param lpddr4_fsp1_cfg_1gb[] = {
+ { 0xd0000, 0x0 },
+ { 0x54000, 0x0 },
+ { 0x54001, 0x0 },
+ { 0x54002, 0x101 },
+ { 0x54003, 0x190 },
+ { 0x54004, 0x2 },
+ { 0x54005, 0x2228 },
+ { 0x54006, 0x11 },
+ { 0x54007, 0x0 },
+ { 0x54008, 0x121f },
+ { 0x54009, 0xc8 },
+ { 0x5400a, 0x0 },
+ { 0x5400b, 0x2 },
+ { 0x5400c, 0x0 },
+ { 0x5400d, 0x0 },
+ { 0x5400e, 0x0 },
+ { 0x5400f, 0x0 },
+ { 0x54010, 0x0 },
+ { 0x54011, 0x0 },
+ { 0x54012, 0x110 },
+ { 0x54013, 0x0 },
+ { 0x54014, 0x0 },
+ { 0x54015, 0x0 },
+ { 0x54016, 0x0 },
+ { 0x54017, 0x0 },
+ { 0x54018, 0x0 },
+ { 0x54019, 0x84 },
+ { 0x5401a, 0x31 },
+ { 0x5401b, 0x4d66 },
+ { 0x5401c, 0x4d00 },
+ { 0x5401d, 0x0 },
+ { 0x5401e, 0x16 },
+ { 0x5401f, 0x84 },
+ { 0x54020, 0x31 },
+ { 0x54021, 0x4d66 },
+ { 0x54022, 0x4d00 },
+ { 0x54023, 0x0 },
+ { 0x54024, 0x16 },
+ { 0x54025, 0x0 },
+ { 0x54026, 0x0 },
+ { 0x54027, 0x0 },
+ { 0x54028, 0x0 },
+ { 0x54029, 0x0 },
+ { 0x5402a, 0x0 },
+ { 0x5402b, 0x1000 },
+ { 0x5402c, 0x1 },
+ { 0x5402d, 0x0 },
+ { 0x5402e, 0x0 },
+ { 0x5402f, 0x0 },
+ { 0x54030, 0x0 },
+ { 0x54031, 0x0 },
+ { 0x54032, 0x8400 },
+ { 0x54033, 0x3100 },
+ { 0x54034, 0x6600 },
+ { 0x54035, 0x4d },
+ { 0x54036, 0x4d },
+ { 0x54037, 0x1600 },
+ { 0x54038, 0x8400 },
+ { 0x54039, 0x3100 },
+ { 0x5403a, 0x6600 },
+ { 0x5403b, 0x4d },
+ { 0x5403c, 0x4d },
+ { 0x5403d, 0x1600 },
+ { 0x5403e, 0x0 },
+ { 0x5403f, 0x0 },
+ { 0x54040, 0x0 },
+ { 0x54041, 0x0 },
+ { 0x54042, 0x0 },
+ { 0x54043, 0x0 },
+ { 0x54044, 0x0 },
+ { 0xd0000, 0x1 },
+};
+
+/* P2 message block paremeter for training firmware */
+static struct dram_cfg_param lpddr4_fsp2_cfg_1gb[] = {
+ { 0xd0000, 0x0 },
+ { 0x54000, 0x0 },
+ { 0x54001, 0x0 },
+ { 0x54002, 0x102 },
+ { 0x54003, 0x64 },
+ { 0x54004, 0x2 },
+ { 0x54005, 0x2228 },
+ { 0x54006, 0x11 },
+ { 0x54007, 0x0 },
+ { 0x54008, 0x121f },
+ { 0x54009, 0xc8 },
+ { 0x5400a, 0x0 },
+ { 0x5400b, 0x2 },
+ { 0x5400c, 0x0 },
+ { 0x5400d, 0x0 },
+ { 0x5400e, 0x0 },
+ { 0x5400f, 0x0 },
+ { 0x54010, 0x0 },
+ { 0x54011, 0x0 },
+ { 0x54012, 0x110 },
+ { 0x54013, 0x0 },
+ { 0x54014, 0x0 },
+ { 0x54015, 0x0 },
+ { 0x54016, 0x0 },
+ { 0x54017, 0x0 },
+ { 0x54018, 0x0 },
+ { 0x54019, 0x84 },
+ { 0x5401a, 0x31 },
+ { 0x5401b, 0x4d66 },
+ { 0x5401c, 0x4d00 },
+ { 0x5401d, 0x0 },
+ { 0x5401e, 0x16 },
+ { 0x5401f, 0x84 },
+ { 0x54020, 0x31 },
+ { 0x54021, 0x4d66 },
+ { 0x54022, 0x4d00 },
+ { 0x54023, 0x0 },
+ { 0x54024, 0x16 },
+ { 0x54025, 0x0 },
+ { 0x54026, 0x0 },
+ { 0x54027, 0x0 },
+ { 0x54028, 0x0 },
+ { 0x54029, 0x0 },
+ { 0x5402a, 0x0 },
+ { 0x5402b, 0x1000 },
+ { 0x5402c, 0x1 },
+ { 0x5402d, 0x0 },
+ { 0x5402e, 0x0 },
+ { 0x5402f, 0x0 },
+ { 0x54030, 0x0 },
+ { 0x54031, 0x0 },
+ { 0x54032, 0x8400 },
+ { 0x54033, 0x3100 },
+ { 0x54034, 0x6600 },
+ { 0x54035, 0x4d },
+ { 0x54036, 0x4d },
+ { 0x54037, 0x1600 },
+ { 0x54038, 0x8400 },
+ { 0x54039, 0x3100 },
+ { 0x5403a, 0x6600 },
+ { 0x5403b, 0x4d },
+ { 0x5403c, 0x4d },
+ { 0x5403d, 0x1600 },
+ { 0x5403e, 0x0 },
+ { 0x5403f, 0x0 },
+ { 0x54040, 0x0 },
+ { 0x54041, 0x0 },
+ { 0x54042, 0x0 },
+ { 0x54043, 0x0 },
+ { 0x54044, 0x0 },
+ { 0xd0000, 0x1 },
+};
+
+/* P0 2D message block paremeter for training firmware */
+static struct dram_cfg_param lpddr4_fsp0_2d_cfg_1gb[] = {
+ { 0xd0000, 0x0 },
+ { 0x54000, 0x0 },
+ { 0x54001, 0x0 },
+ { 0x54002, 0x0 },
+ { 0x54003, 0xbb8 },
+ { 0x54004, 0x2 },
+ { 0x54005, 0x2228 },
+ { 0x54006, 0x11 },
+ { 0x54007, 0x0 },
+ { 0x54008, 0x61 },
+ { 0x54009, 0xc8 },
+ { 0x5400a, 0x0 },
+ { 0x5400b, 0x2 },
+ { 0x5400c, 0x0 },
+ { 0x5400d, 0x100 },
+ { 0x5400e, 0x0 },
+ { 0x5400f, 0x100 },
+ { 0x54010, 0x1f7f },
+ { 0x54011, 0x0 },
+ { 0x54012, 0x110 },
+ { 0x54013, 0x0 },
+ { 0x54014, 0x0 },
+ { 0x54015, 0x0 },
+ { 0x54016, 0x0 },
+ { 0x54017, 0x0 },
+ { 0x54018, 0x0 },
+ { 0x54019, 0x2dd4 },
+ { 0x5401a, 0x31 },
+ { 0x5401b, 0x4d66 },
+ { 0x5401c, 0x4d00 },
+ { 0x5401d, 0x0 },
+ { 0x5401e, 0x16 },
+ { 0x5401f, 0x2dd4 },
+ { 0x54020, 0x31 },
+ { 0x54021, 0x4d66 },
+ { 0x54022, 0x4d00 },
+ { 0x54023, 0x0 },
+ { 0x54024, 0x16 },
+ { 0x54025, 0x0 },
+ { 0x54026, 0x0 },
+ { 0x54027, 0x0 },
+ { 0x54028, 0x0 },
+ { 0x54029, 0x0 },
+ { 0x5402a, 0x0 },
+ { 0x5402b, 0x1000 },
+ { 0x5402c, 0x1 },
+ { 0x5402d, 0x0 },
+ { 0x5402e, 0x0 },
+ { 0x5402f, 0x0 },
+ { 0x54030, 0x0 },
+ { 0x54031, 0x0 },
+ { 0x54032, 0xd400 },
+ { 0x54033, 0x312d },
+ { 0x54034, 0x6600 },
+ { 0x54035, 0x4d },
+ { 0x54036, 0x4d },
+ { 0x54037, 0x1600 },
+ { 0x54038, 0xd400 },
+ { 0x54039, 0x312d },
+ { 0x5403a, 0x6600 },
+ { 0x5403b, 0x4d },
+ { 0x5403c, 0x4d },
+ { 0x5403d, 0x1600 },
+ { 0x5403e, 0x0 },
+ { 0x5403f, 0x0 },
+ { 0x54040, 0x0 },
+ { 0x54041, 0x0 },
+ { 0x54042, 0x0 },
+ { 0x54043, 0x0 },
+ { 0x54044, 0x0 },
+ { 0xd0000, 0x1 },
+};
+
+/* DRAM PHY init engine image */
+struct dram_cfg_param lpddr4_phy_pie[] = {
+ { 0xd0000, 0x0 },
+ { 0x90000, 0x10 },
+ { 0x90001, 0x400 },
+ { 0x90002, 0x10e },
+ { 0x90003, 0x0 },
+ { 0x90004, 0x0 },
+ { 0x90005, 0x8 },
+ { 0x90029, 0xb },
+ { 0x9002a, 0x480 },
+ { 0x9002b, 0x109 },
+ { 0x9002c, 0x8 },
+ { 0x9002d, 0x448 },
+ { 0x9002e, 0x139 },
+ { 0x9002f, 0x8 },
+ { 0x90030, 0x478 },
+ { 0x90031, 0x109 },
+ { 0x90032, 0x0 },
+ { 0x90033, 0xe8 },
+ { 0x90034, 0x109 },
+ { 0x90035, 0x2 },
+ { 0x90036, 0x10 },
+ { 0x90037, 0x139 },
+ { 0x90038, 0xf },
+ { 0x90039, 0x7c0 },
+ { 0x9003a, 0x139 },
+ { 0x9003b, 0x44 },
+ { 0x9003c, 0x630 },
+ { 0x9003d, 0x159 },
+ { 0x9003e, 0x14f },
+ { 0x9003f, 0x630 },
+ { 0x90040, 0x159 },
+ { 0x90041, 0x47 },
+ { 0x90042, 0x630 },
+ { 0x90043, 0x149 },
+ { 0x90044, 0x4f },
+ { 0x90045, 0x630 },
+ { 0x90046, 0x179 },
+ { 0x90047, 0x8 },
+ { 0x90048, 0xe0 },
+ { 0x90049, 0x109 },
+ { 0x9004a, 0x0 },
+ { 0x9004b, 0x7c8 },
+ { 0x9004c, 0x109 },
+ { 0x9004d, 0x0 },
+ { 0x9004e, 0x1 },
+ { 0x9004f, 0x8 },
+ { 0x90050, 0x0 },
+ { 0x90051, 0x45a },
+ { 0x90052, 0x9 },
+ { 0x90053, 0x0 },
+ { 0x90054, 0x448 },
+ { 0x90055, 0x109 },
+ { 0x90056, 0x40 },
+ { 0x90057, 0x630 },
+ { 0x90058, 0x179 },
+ { 0x90059, 0x1 },
+ { 0x9005a, 0x618 },
+ { 0x9005b, 0x109 },
+ { 0x9005c, 0x40c0 },
+ { 0x9005d, 0x630 },
+ { 0x9005e, 0x149 },
+ { 0x9005f, 0x8 },
+ { 0x90060, 0x4 },
+ { 0x90061, 0x48 },
+ { 0x90062, 0x4040 },
+ { 0x90063, 0x630 },
+ { 0x90064, 0x149 },
+ { 0x90065, 0x0 },
+ { 0x90066, 0x4 },
+ { 0x90067, 0x48 },
+ { 0x90068, 0x40 },
+ { 0x90069, 0x630 },
+ { 0x9006a, 0x149 },
+ { 0x9006b, 0x10 },
+ { 0x9006c, 0x4 },
+ { 0x9006d, 0x18 },
+ { 0x9006e, 0x0 },
+ { 0x9006f, 0x4 },
+ { 0x90070, 0x78 },
+ { 0x90071, 0x549 },
+ { 0x90072, 0x630 },
+ { 0x90073, 0x159 },
+ { 0x90074, 0xd49 },
+ { 0x90075, 0x630 },
+ { 0x90076, 0x159 },
+ { 0x90077, 0x94a },
+ { 0x90078, 0x630 },
+ { 0x90079, 0x159 },
+ { 0x9007a, 0x441 },
+ { 0x9007b, 0x630 },
+ { 0x9007c, 0x149 },
+ { 0x9007d, 0x42 },
+ { 0x9007e, 0x630 },
+ { 0x9007f, 0x149 },
+ { 0x90080, 0x1 },
+ { 0x90081, 0x630 },
+ { 0x90082, 0x149 },
+ { 0x90083, 0x0 },
+ { 0x90084, 0xe0 },
+ { 0x90085, 0x109 },
+ { 0x90086, 0xa },
+ { 0x90087, 0x10 },
+ { 0x90088, 0x109 },
+ { 0x90089, 0x9 },
+ { 0x9008a, 0x3c0 },
+ { 0x9008b, 0x149 },
+ { 0x9008c, 0x9 },
+ { 0x9008d, 0x3c0 },
+ { 0x9008e, 0x159 },
+ { 0x9008f, 0x18 },
+ { 0x90090, 0x10 },
+ { 0x90091, 0x109 },
+ { 0x90092, 0x0 },
+ { 0x90093, 0x3c0 },
+ { 0x90094, 0x109 },
+ { 0x90095, 0x18 },
+ { 0x90096, 0x4 },
+ { 0x90097, 0x48 },
+ { 0x90098, 0x18 },
+ { 0x90099, 0x4 },
+ { 0x9009a, 0x58 },
+ { 0x9009b, 0xa },
+ { 0x9009c, 0x10 },
+ { 0x9009d, 0x109 },
+ { 0x9009e, 0x2 },
+ { 0x9009f, 0x10 },
+ { 0x900a0, 0x109 },
+ { 0x900a1, 0x5 },
+ { 0x900a2, 0x7c0 },
+ { 0x900a3, 0x109 },
+ { 0x900a4, 0x10 },
+ { 0x900a5, 0x10 },
+ { 0x900a6, 0x109 },
+ { 0x40000, 0x811 },
+ { 0x40020, 0x880 },
+ { 0x40040, 0x0 },
+ { 0x40060, 0x0 },
+ { 0x40001, 0x4008 },
+ { 0x40021, 0x83 },
+ { 0x40041, 0x4f },
+ { 0x40061, 0x0 },
+ { 0x40002, 0x4040 },
+ { 0x40022, 0x83 },
+ { 0x40042, 0x51 },
+ { 0x40062, 0x0 },
+ { 0x40003, 0x811 },
+ { 0x40023, 0x880 },
+ { 0x40043, 0x0 },
+ { 0x40063, 0x0 },
+ { 0x40004, 0x720 },
+ { 0x40024, 0xf },
+ { 0x40044, 0x1740 },
+ { 0x40064, 0x0 },
+ { 0x40005, 0x16 },
+ { 0x40025, 0x83 },
+ { 0x40045, 0x4b },
+ { 0x40065, 0x0 },
+ { 0x40006, 0x716 },
+ { 0x40026, 0xf },
+ { 0x40046, 0x2001 },
+ { 0x40066, 0x0 },
+ { 0x40007, 0x716 },
+ { 0x40027, 0xf },
+ { 0x40047, 0x2800 },
+ { 0x40067, 0x0 },
+ { 0x40008, 0x716 },
+ { 0x40028, 0xf },
+ { 0x40048, 0xf00 },
+ { 0x40068, 0x0 },
+ { 0x40009, 0x720 },
+ { 0x40029, 0xf },
+ { 0x40049, 0x1400 },
+ { 0x40069, 0x0 },
+ { 0x4000a, 0xe08 },
+ { 0x4002a, 0xc15 },
+ { 0x4004a, 0x0 },
+ { 0x4006a, 0x0 },
+ { 0x4000b, 0x623 },
+ { 0x4002b, 0x15 },
+ { 0x4004b, 0x0 },
+ { 0x4006b, 0x0 },
+ { 0x4000c, 0x4028 },
+ { 0x4002c, 0x80 },
+ { 0x4004c, 0x0 },
+ { 0x4006c, 0x0 },
+ { 0x4000d, 0xe08 },
+ { 0x4002d, 0xc1a },
+ { 0x4004d, 0x0 },
+ { 0x4006d, 0x0 },
+ { 0x4000e, 0x623 },
+ { 0x4002e, 0x1a },
+ { 0x4004e, 0x0 },
+ { 0x4006e, 0x0 },
+ { 0x4000f, 0x4040 },
+ { 0x4002f, 0x80 },
+ { 0x4004f, 0x0 },
+ { 0x4006f, 0x0 },
+ { 0x40010, 0x2604 },
+ { 0x40030, 0x15 },
+ { 0x40050, 0x0 },
+ { 0x40070, 0x0 },
+ { 0x40011, 0x708 },
+ { 0x40031, 0x5 },
+ { 0x40051, 0x0 },
+ { 0x40071, 0x2002 },
+ { 0x40012, 0x8 },
+ { 0x40032, 0x80 },
+ { 0x40052, 0x0 },
+ { 0x40072, 0x0 },
+ { 0x40013, 0x2604 },
+ { 0x40033, 0x1a },
+ { 0x40053, 0x0 },
+ { 0x40073, 0x0 },
+ { 0x40014, 0x708 },
+ { 0x40034, 0xa },
+ { 0x40054, 0x0 },
+ { 0x40074, 0x2002 },
+ { 0x40015, 0x4040 },
+ { 0x40035, 0x80 },
+ { 0x40055, 0x0 },
+ { 0x40075, 0x0 },
+ { 0x40016, 0x60a },
+ { 0x40036, 0x15 },
+ { 0x40056, 0x1200 },
+ { 0x40076, 0x0 },
+ { 0x40017, 0x61a },
+ { 0x40037, 0x15 },
+ { 0x40057, 0x1300 },
+ { 0x40077, 0x0 },
+ { 0x40018, 0x60a },
+ { 0x40038, 0x1a },
+ { 0x40058, 0x1200 },
+ { 0x40078, 0x0 },
+ { 0x40019, 0x642 },
+ { 0x40039, 0x1a },
+ { 0x40059, 0x1300 },
+ { 0x40079, 0x0 },
+ { 0x4001a, 0x4808 },
+ { 0x4003a, 0x880 },
+ { 0x4005a, 0x0 },
+ { 0x4007a, 0x0 },
+ { 0x900a7, 0x0 },
+ { 0x900a8, 0x790 },
+ { 0x900a9, 0x11a },
+ { 0x900aa, 0x8 },
+ { 0x900ab, 0x7aa },
+ { 0x900ac, 0x2a },
+ { 0x900ad, 0x10 },
+ { 0x900ae, 0x7b2 },
+ { 0x900af, 0x2a },
+ { 0x900b0, 0x0 },
+ { 0x900b1, 0x7c8 },
+ { 0x900b2, 0x109 },
+ { 0x900b3, 0x10 },
+ { 0x900b4, 0x2a8 },
+ { 0x900b5, 0x129 },
+ { 0x900b6, 0x8 },
+ { 0x900b7, 0x370 },
+ { 0x900b8, 0x129 },
+ { 0x900b9, 0xa },
+ { 0x900ba, 0x3c8 },
+ { 0x900bb, 0x1a9 },
+ { 0x900bc, 0xc },
+ { 0x900bd, 0x408 },
+ { 0x900be, 0x199 },
+ { 0x900bf, 0x14 },
+ { 0x900c0, 0x790 },
+ { 0x900c1, 0x11a },
+ { 0x900c2, 0x8 },
+ { 0x900c3, 0x4 },
+ { 0x900c4, 0x18 },
+ { 0x900c5, 0xe },
+ { 0x900c6, 0x408 },
+ { 0x900c7, 0x199 },
+ { 0x900c8, 0x8 },
+ { 0x900c9, 0x8568 },
+ { 0x900ca, 0x108 },
+ { 0x900cb, 0x18 },
+ { 0x900cc, 0x790 },
+ { 0x900cd, 0x16a },
+ { 0x900ce, 0x8 },
+ { 0x900cf, 0x1d8 },
+ { 0x900d0, 0x169 },
+ { 0x900d1, 0x10 },
+ { 0x900d2, 0x8558 },
+ { 0x900d3, 0x168 },
+ { 0x900d4, 0x70 },
+ { 0x900d5, 0x788 },
+ { 0x900d6, 0x16a },
+ { 0x900d7, 0x1ff8 },
+ { 0x900d8, 0x85a8 },
+ { 0x900d9, 0x1e8 },
+ { 0x900da, 0x50 },
+ { 0x900db, 0x798 },
+ { 0x900dc, 0x16a },
+ { 0x900dd, 0x60 },
+ { 0x900de, 0x7a0 },
+ { 0x900df, 0x16a },
+ { 0x900e0, 0x8 },
+ { 0x900e1, 0x8310 },
+ { 0x900e2, 0x168 },
+ { 0x900e3, 0x8 },
+ { 0x900e4, 0xa310 },
+ { 0x900e5, 0x168 },
+ { 0x900e6, 0xa },
+ { 0x900e7, 0x408 },
+ { 0x900e8, 0x169 },
+ { 0x900e9, 0x6e },
+ { 0x900ea, 0x0 },
+ { 0x900eb, 0x68 },
+ { 0x900ec, 0x0 },
+ { 0x900ed, 0x408 },
+ { 0x900ee, 0x169 },
+ { 0x900ef, 0x0 },
+ { 0x900f0, 0x8310 },
+ { 0x900f1, 0x168 },
+ { 0x900f2, 0x0 },
+ { 0x900f3, 0xa310 },
+ { 0x900f4, 0x168 },
+ { 0x900f5, 0x1ff8 },
+ { 0x900f6, 0x85a8 },
+ { 0x900f7, 0x1e8 },
+ { 0x900f8, 0x68 },
+ { 0x900f9, 0x798 },
+ { 0x900fa, 0x16a },
+ { 0x900fb, 0x78 },
+ { 0x900fc, 0x7a0 },
+ { 0x900fd, 0x16a },
+ { 0x900fe, 0x68 },
+ { 0x900ff, 0x790 },
+ { 0x90100, 0x16a },
+ { 0x90101, 0x8 },
+ { 0x90102, 0x8b10 },
+ { 0x90103, 0x168 },
+ { 0x90104, 0x8 },
+ { 0x90105, 0xab10 },
+ { 0x90106, 0x168 },
+ { 0x90107, 0xa },
+ { 0x90108, 0x408 },
+ { 0x90109, 0x169 },
+ { 0x9010a, 0x58 },
+ { 0x9010b, 0x0 },
+ { 0x9010c, 0x68 },
+ { 0x9010d, 0x0 },
+ { 0x9010e, 0x408 },
+ { 0x9010f, 0x169 },
+ { 0x90110, 0x0 },
+ { 0x90111, 0x8b10 },
+ { 0x90112, 0x168 },
+ { 0x90113, 0x0 },
+ { 0x90114, 0xab10 },
+ { 0x90115, 0x168 },
+ { 0x90116, 0x0 },
+ { 0x90117, 0x1d8 },
+ { 0x90118, 0x169 },
+ { 0x90119, 0x80 },
+ { 0x9011a, 0x790 },
+ { 0x9011b, 0x16a },
+ { 0x9011c, 0x18 },
+ { 0x9011d, 0x7aa },
+ { 0x9011e, 0x6a },
+ { 0x9011f, 0xa },
+ { 0x90120, 0x0 },
+ { 0x90121, 0x1e9 },
+ { 0x90122, 0x8 },
+ { 0x90123, 0x8080 },
+ { 0x90124, 0x108 },
+ { 0x90125, 0xf },
+ { 0x90126, 0x408 },
+ { 0x90127, 0x169 },
+ { 0x90128, 0xc },
+ { 0x90129, 0x0 },
+ { 0x9012a, 0x68 },
+ { 0x9012b, 0x9 },
+ { 0x9012c, 0x0 },
+ { 0x9012d, 0x1a9 },
+ { 0x9012e, 0x0 },
+ { 0x9012f, 0x408 },
+ { 0x90130, 0x169 },
+ { 0x90131, 0x0 },
+ { 0x90132, 0x8080 },
+ { 0x90133, 0x108 },
+ { 0x90134, 0x8 },
+ { 0x90135, 0x7aa },
+ { 0x90136, 0x6a },
+ { 0x90137, 0x0 },
+ { 0x90138, 0x8568 },
+ { 0x90139, 0x108 },
+ { 0x9013a, 0xb7 },
+ { 0x9013b, 0x790 },
+ { 0x9013c, 0x16a },
+ { 0x9013d, 0x1f },
+ { 0x9013e, 0x0 },
+ { 0x9013f, 0x68 },
+ { 0x90140, 0x8 },
+ { 0x90141, 0x8558 },
+ { 0x90142, 0x168 },
+ { 0x90143, 0xf },
+ { 0x90144, 0x408 },
+ { 0x90145, 0x169 },
+ { 0x90146, 0xc },
+ { 0x90147, 0x0 },
+ { 0x90148, 0x68 },
+ { 0x90149, 0x0 },
+ { 0x9014a, 0x408 },
+ { 0x9014b, 0x169 },
+ { 0x9014c, 0x0 },
+ { 0x9014d, 0x8558 },
+ { 0x9014e, 0x168 },
+ { 0x9014f, 0x8 },
+ { 0x90150, 0x3c8 },
+ { 0x90151, 0x1a9 },
+ { 0x90152, 0x3 },
+ { 0x90153, 0x370 },
+ { 0x90154, 0x129 },
+ { 0x90155, 0x20 },
+ { 0x90156, 0x2aa },
+ { 0x90157, 0x9 },
+ { 0x90158, 0x0 },
+ { 0x90159, 0x400 },
+ { 0x9015a, 0x10e },
+ { 0x9015b, 0x8 },
+ { 0x9015c, 0xe8 },
+ { 0x9015d, 0x109 },
+ { 0x9015e, 0x0 },
+ { 0x9015f, 0x8140 },
+ { 0x90160, 0x10c },
+ { 0x90161, 0x10 },
+ { 0x90162, 0x8138 },
+ { 0x90163, 0x10c },
+ { 0x90164, 0x8 },
+ { 0x90165, 0x7c8 },
+ { 0x90166, 0x101 },
+ { 0x90167, 0x8 },
+ { 0x90168, 0x0 },
+ { 0x90169, 0x8 },
+ { 0x9016a, 0x8 },
+ { 0x9016b, 0x448 },
+ { 0x9016c, 0x109 },
+ { 0x9016d, 0xf },
+ { 0x9016e, 0x7c0 },
+ { 0x9016f, 0x109 },
+ { 0x90170, 0x0 },
+ { 0x90171, 0xe8 },
+ { 0x90172, 0x109 },
+ { 0x90173, 0x47 },
+ { 0x90174, 0x630 },
+ { 0x90175, 0x109 },
+ { 0x90176, 0x8 },
+ { 0x90177, 0x618 },
+ { 0x90178, 0x109 },
+ { 0x90179, 0x8 },
+ { 0x9017a, 0xe0 },
+ { 0x9017b, 0x109 },
+ { 0x9017c, 0x0 },
+ { 0x9017d, 0x7c8 },
+ { 0x9017e, 0x109 },
+ { 0x9017f, 0x8 },
+ { 0x90180, 0x8140 },
+ { 0x90181, 0x10c },
+ { 0x90182, 0x0 },
+ { 0x90183, 0x1 },
+ { 0x90184, 0x8 },
+ { 0x90185, 0x8 },
+ { 0x90186, 0x4 },
+ { 0x90187, 0x8 },
+ { 0x90188, 0x8 },
+ { 0x90189, 0x7c8 },
+ { 0x9018a, 0x101 },
+ { 0x90006, 0x0 },
+ { 0x90007, 0x0 },
+ { 0x90008, 0x8 },
+ { 0x90009, 0x0 },
+ { 0x9000a, 0x0 },
+ { 0x9000b, 0x0 },
+ { 0xd00e7, 0x400 },
+ { 0x90017, 0x0 },
+ { 0x9001f, 0x2a },
+ { 0x90026, 0x6a },
+ { 0x400d0, 0x0 },
+ { 0x400d1, 0x101 },
+ { 0x400d2, 0x105 },
+ { 0x400d3, 0x107 },
+ { 0x400d4, 0x10f },
+ { 0x400d5, 0x202 },
+ { 0x400d6, 0x20a },
+ { 0x400d7, 0x20b },
+ { 0x2003a, 0x2 },
+ { 0x2000b, 0x5d },
+ { 0x2000c, 0xbb },
+ { 0x2000d, 0x753 },
+ { 0x2000e, 0x2c },
+ { 0x12000b, 0xc },
+ { 0x12000c, 0x19 },
+ { 0x12000d, 0xfa },
+ { 0x12000e, 0x10 },
+ { 0x22000b, 0x3 },
+ { 0x22000c, 0x6 },
+ { 0x22000d, 0x3e },
+ { 0x22000e, 0x10 },
+ { 0x9000c, 0x0 },
+ { 0x9000d, 0x173 },
+ { 0x9000e, 0x60 },
+ { 0x9000f, 0x6110 },
+ { 0x90010, 0x2152 },
+ { 0x90011, 0xdfbd },
+ { 0x90012, 0x60 },
+ { 0x90013, 0x6152 },
+ { 0x20010, 0x5a },
+ { 0x20011, 0x3 },
+ { 0x120010, 0x5a },
+ { 0x120011, 0x3 },
+ { 0x220010, 0x5a },
+ { 0x220011, 0x3 },
+ { 0x40080, 0xe0 },
+ { 0x40081, 0x12 },
+ { 0x40082, 0xe0 },
+ { 0x40083, 0x12 },
+ { 0x40084, 0xe0 },
+ { 0x40085, 0x12 },
+ { 0x140080, 0xe0 },
+ { 0x140081, 0x12 },
+ { 0x140082, 0xe0 },
+ { 0x140083, 0x12 },
+ { 0x140084, 0xe0 },
+ { 0x140085, 0x12 },
+ { 0x240080, 0xe0 },
+ { 0x240081, 0x12 },
+ { 0x240082, 0xe0 },
+ { 0x240083, 0x12 },
+ { 0x240084, 0xe0 },
+ { 0x240085, 0x12 },
+ { 0x400fd, 0xf },
+ { 0x10011, 0x1 },
+ { 0x10012, 0x1 },
+ { 0x10013, 0x180 },
+ { 0x10018, 0x1 },
+ { 0x10002, 0x6209 },
+ { 0x100b2, 0x1 },
+ { 0x101b4, 0x1 },
+ { 0x102b4, 0x1 },
+ { 0x103b4, 0x1 },
+ { 0x104b4, 0x1 },
+ { 0x105b4, 0x1 },
+ { 0x106b4, 0x1 },
+ { 0x107b4, 0x1 },
+ { 0x108b4, 0x1 },
+ { 0x11011, 0x1 },
+ { 0x11012, 0x1 },
+ { 0x11013, 0x180 },
+ { 0x11018, 0x1 },
+ { 0x11002, 0x6209 },
+ { 0x110b2, 0x1 },
+ { 0x111b4, 0x1 },
+ { 0x112b4, 0x1 },
+ { 0x113b4, 0x1 },
+ { 0x114b4, 0x1 },
+ { 0x115b4, 0x1 },
+ { 0x116b4, 0x1 },
+ { 0x117b4, 0x1 },
+ { 0x118b4, 0x1 },
+ { 0x12011, 0x1 },
+ { 0x12012, 0x1 },
+ { 0x12013, 0x180 },
+ { 0x12018, 0x1 },
+ { 0x12002, 0x6209 },
+ { 0x120b2, 0x1 },
+ { 0x121b4, 0x1 },
+ { 0x122b4, 0x1 },
+ { 0x123b4, 0x1 },
+ { 0x124b4, 0x1 },
+ { 0x125b4, 0x1 },
+ { 0x126b4, 0x1 },
+ { 0x127b4, 0x1 },
+ { 0x128b4, 0x1 },
+ { 0x13011, 0x1 },
+ { 0x13012, 0x1 },
+ { 0x13013, 0x180 },
+ { 0x13018, 0x1 },
+ { 0x13002, 0x6209 },
+ { 0x130b2, 0x1 },
+ { 0x131b4, 0x1 },
+ { 0x132b4, 0x1 },
+ { 0x133b4, 0x1 },
+ { 0x134b4, 0x1 },
+ { 0x135b4, 0x1 },
+ { 0x136b4, 0x1 },
+ { 0x137b4, 0x1 },
+ { 0x138b4, 0x1 },
+ { 0x2003a, 0x2 },
+ { 0xc0080, 0x2 },
+ { 0xd0000, 0x1 },
+};
+
+static struct dram_fsp_msg lpddr4_dram_fsp_msg_1gb[] = {
+ {
+ /* P0 3000mts 1D */
+ .drate = 3000,
+ .fw_type = FW_1D_IMAGE,
+ .fsp_cfg = lpddr4_fsp0_cfg_1gb,
+ .fsp_cfg_num = ARRAY_SIZE(lpddr4_fsp0_cfg_1gb),
+ },
+ {
+ /* P1 400mts 1D */
+ .drate = 400,
+ .fw_type = FW_1D_IMAGE,
+ .fsp_cfg = lpddr4_fsp1_cfg_1gb,
+ .fsp_cfg_num = ARRAY_SIZE(lpddr4_fsp1_cfg_1gb),
+ },
+ {
+ /* P2 100mts 1D */
+ .drate = 100,
+ .fw_type = FW_1D_IMAGE,
+ .fsp_cfg = lpddr4_fsp2_cfg_1gb,
+ .fsp_cfg_num = ARRAY_SIZE(lpddr4_fsp2_cfg_1gb),
+ },
+ {
+ /* P0 3000mts 2D */
+ .drate = 3000,
+ .fw_type = FW_2D_IMAGE,
+ .fsp_cfg = lpddr4_fsp0_2d_cfg_1gb,
+ .fsp_cfg_num = ARRAY_SIZE(lpddr4_fsp0_2d_cfg_1gb),
+ },
+};
+
+/* lpddr4 timing config params */
+struct dram_timing_info dram_timing_1gb = {
+ .ddrc_cfg = lpddr4_ddrc_cfg_1gb,
+ .ddrc_cfg_num = ARRAY_SIZE(lpddr4_ddrc_cfg_1gb),
+ .ddrphy_cfg = lpddr4_ddrphy_cfg_1gb,
+ .ddrphy_cfg_num = ARRAY_SIZE(lpddr4_ddrphy_cfg_1gb),
+ .fsp_msg = lpddr4_dram_fsp_msg_1gb,
+ .fsp_msg_num = ARRAY_SIZE(lpddr4_dram_fsp_msg_1gb),
+ .ddrphy_trained_csr = lpddr4_ddrphy_trained_csr,
+ .ddrphy_trained_csr_num = ARRAY_SIZE(lpddr4_ddrphy_trained_csr),
+ .ddrphy_pie = lpddr4_phy_pie,
+ .ddrphy_pie_num = ARRAY_SIZE(lpddr4_phy_pie),
+ .fsp_table = { 3000, 400, 100, },
+};
+
+static struct dram_cfg_param lpddr4_ddrc_cfg_4gb[] = {
+ /** Initialize DDRC registers **/
+ { 0x3d400304, 0x1 },
+ { 0x3d400030, 0x1 },
+ { 0x3d400000, 0xa3080020 },
+ { 0x3d400020, 0x223 },
+ { 0x3d400024, 0x3a980 },
+ { 0x3d400064, 0x5b00d2 },
+ { 0x3d4000d0, 0xc00305ba },
+ { 0x3d4000d4, 0x940000 },
+ { 0x3d4000dc, 0xd4002d },
+ { 0x3d4000e0, 0x310000 },
+ { 0x3d4000e8, 0x66004d },
+ { 0x3d4000ec, 0x16004d },
+ { 0x3d400100, 0x191e1920 },
+ { 0x3d400104, 0x60630 },
+ { 0x3d40010c, 0xb0b000 },
+ { 0x3d400110, 0xe04080e },
+ { 0x3d400114, 0x2040c0c },
+ { 0x3d400118, 0x1010007 },
+ { 0x3d40011c, 0x401 },
+ { 0x3d400130, 0x20600 },
+ { 0x3d400134, 0xc100002 },
+ { 0x3d400138, 0xd8 },
+ { 0x3d400144, 0x96004b },
+ { 0x3d400180, 0x2ee0017 },
+ { 0x3d400184, 0x2605b8e },
+ { 0x3d400188, 0x0 },
+ { 0x3d400190, 0x497820a },
+ { 0x3d400194, 0x80303 },
+ { 0x3d4001b4, 0x170a },
+ { 0x3d4001a0, 0xe0400018 },
+ { 0x3d4001a4, 0xdf00e4 },
+ { 0x3d4001a8, 0x80000000 },
+ { 0x3d4001b0, 0x11 },
+ { 0x3d4001c0, 0x1 },
+ { 0x3d4001c4, 0x1 },
+ { 0x3d4000f4, 0xc99 },
+ { 0x3d400108, 0x70e1617 },
+ { 0x3d400200, 0x17 },
+ { 0x3d40020c, 0x0 },
+ { 0x3d400210, 0x1f1f },
+ { 0x3d400204, 0x80808 },
+ { 0x3d400214, 0x7070707 },
+ { 0x3d400218, 0x7070707 },
+ { 0x3d400250, 0x29001701 },
+ { 0x3d400254, 0x2c },
+ { 0x3d40025c, 0x4000030 },
+ { 0x3d400264, 0x900093e7 },
+ { 0x3d40026c, 0x2005574 },
+ { 0x3d400400, 0x111 },
+ { 0x3d400408, 0x72ff },
+ { 0x3d400494, 0x2100e07 },
+ { 0x3d400498, 0x620096 },
+ { 0x3d40049c, 0x1100e07 },
+ { 0x3d4004a0, 0xc8012c },
+ { 0x3d402020, 0x21 },
+ { 0x3d402024, 0x7d00 },
+ { 0x3d402050, 0x20d040 },
+ { 0x3d402064, 0xc001c },
+ { 0x3d4020dc, 0x840000 },
+ { 0x3d4020e0, 0x310000 },
+ { 0x3d4020e8, 0x66004d },
+ { 0x3d4020ec, 0x16004d },
+ { 0x3d402100, 0xa040305 },
+ { 0x3d402104, 0x30407 },
+ { 0x3d402108, 0x203060b },
+ { 0x3d40210c, 0x505000 },
+ { 0x3d402110, 0x2040202 },
+ { 0x3d402114, 0x2030202 },
+ { 0x3d402118, 0x1010004 },
+ { 0x3d40211c, 0x301 },
+ { 0x3d402130, 0x20300 },
+ { 0x3d402134, 0xa100002 },
+ { 0x3d402138, 0x1d },
+ { 0x3d402144, 0x14000a },
+ { 0x3d402180, 0x640004 },
+ { 0x3d402190, 0x3818200 },
+ { 0x3d402194, 0x80303 },
+ { 0x3d4021b4, 0x100 },
+ { 0x3d4020f4, 0xc99 },
+ { 0x3d403020, 0x21 },
+ { 0x3d403024, 0x1f40 },
+ { 0x3d403050, 0x20d040 },
+ { 0x3d403064, 0x30007 },
+ { 0x3d4030dc, 0x840000 },
+ { 0x3d4030e0, 0x310000 },
+ { 0x3d4030e8, 0x66004d },
+ { 0x3d4030ec, 0x16004d },
+ { 0x3d403100, 0xa010102 },
+ { 0x3d403104, 0x30404 },
+ { 0x3d403108, 0x203060b },
+ { 0x3d40310c, 0x505000 },
+ { 0x3d403110, 0x2040202 },
+ { 0x3d403114, 0x2030202 },
+ { 0x3d403118, 0x1010004 },
+ { 0x3d40311c, 0x301 },
+ { 0x3d403130, 0x20300 },
+ { 0x3d403134, 0xa100002 },
+ { 0x3d403138, 0x8 },
+ { 0x3d403144, 0x50003 },
+ { 0x3d403180, 0x190004 },
+ { 0x3d403190, 0x3818200 },
+ { 0x3d403194, 0x80303 },
+ { 0x3d4031b4, 0x100 },
+ { 0x3d4030f4, 0xc99 },
+ { 0x3d400028, 0x0 },
+};
+
+/* PHY Initialize Configuration */
+static struct dram_cfg_param lpddr4_ddrphy_cfg_4gb[] = {
+ { 0x100a0, 0x0 },
+ { 0x100a1, 0x1 },
+ { 0x100a2, 0x2 },
+ { 0x100a3, 0x3 },
+ { 0x100a4, 0x4 },
+ { 0x100a5, 0x5 },
+ { 0x100a6, 0x6 },
+ { 0x100a7, 0x7 },
+ { 0x110a0, 0x0 },
+ { 0x110a1, 0x1 },
+ { 0x110a2, 0x3 },
+ { 0x110a3, 0x4 },
+ { 0x110a4, 0x5 },
+ { 0x110a5, 0x2 },
+ { 0x110a6, 0x7 },
+ { 0x110a7, 0x6 },
+ { 0x120a0, 0x0 },
+ { 0x120a1, 0x1 },
+ { 0x120a2, 0x3 },
+ { 0x120a3, 0x2 },
+ { 0x120a4, 0x5 },
+ { 0x120a5, 0x4 },
+ { 0x120a6, 0x7 },
+ { 0x120a7, 0x6 },
+ { 0x130a0, 0x0 },
+ { 0x130a1, 0x1 },
+ { 0x130a2, 0x2 },
+ { 0x130a3, 0x3 },
+ { 0x130a4, 0x4 },
+ { 0x130a5, 0x5 },
+ { 0x130a6, 0x6 },
+ { 0x130a7, 0x7 },
+ { 0x1005f, 0x1ff },
+ { 0x1015f, 0x1ff },
+ { 0x1105f, 0x1ff },
+ { 0x1115f, 0x1ff },
+ { 0x1205f, 0x1ff },
+ { 0x1215f, 0x1ff },
+ { 0x1305f, 0x1ff },
+ { 0x1315f, 0x1ff },
+ { 0x11005f, 0x1ff },
+ { 0x11015f, 0x1ff },
+ { 0x11105f, 0x1ff },
+ { 0x11115f, 0x1ff },
+ { 0x11205f, 0x1ff },
+ { 0x11215f, 0x1ff },
+ { 0x11305f, 0x1ff },
+ { 0x11315f, 0x1ff },
+ { 0x21005f, 0x1ff },
+ { 0x21015f, 0x1ff },
+ { 0x21105f, 0x1ff },
+ { 0x21115f, 0x1ff },
+ { 0x21205f, 0x1ff },
+ { 0x21215f, 0x1ff },
+ { 0x21305f, 0x1ff },
+ { 0x21315f, 0x1ff },
+ { 0x55, 0x1ff },
+ { 0x1055, 0x1ff },
+ { 0x2055, 0x1ff },
+ { 0x3055, 0x1ff },
+ { 0x4055, 0x1ff },
+ { 0x5055, 0x1ff },
+ { 0x6055, 0x1ff },
+ { 0x7055, 0x1ff },
+ { 0x8055, 0x1ff },
+ { 0x9055, 0x1ff },
+ { 0x200c5, 0x19 },
+ { 0x1200c5, 0x7 },
+ { 0x2200c5, 0x7 },
+ { 0x2002e, 0x2 },
+ { 0x12002e, 0x2 },
+ { 0x22002e, 0x2 },
+ { 0x90204, 0x0 },
+ { 0x190204, 0x0 },
+ { 0x290204, 0x0 },
+ { 0x20024, 0x1ab },
+ { 0x2003a, 0x0 },
+ { 0x120024, 0x1ab },
+ { 0x2003a, 0x0 },
+ { 0x220024, 0x1ab },
+ { 0x2003a, 0x0 },
+ { 0x20056, 0x3 },
+ { 0x120056, 0x3 },
+ { 0x220056, 0x3 },
+ { 0x1004d, 0xe00 },
+ { 0x1014d, 0xe00 },
+ { 0x1104d, 0xe00 },
+ { 0x1114d, 0xe00 },
+ { 0x1204d, 0xe00 },
+ { 0x1214d, 0xe00 },
+ { 0x1304d, 0xe00 },
+ { 0x1314d, 0xe00 },
+ { 0x11004d, 0xe00 },
+ { 0x11014d, 0xe00 },
+ { 0x11104d, 0xe00 },
+ { 0x11114d, 0xe00 },
+ { 0x11204d, 0xe00 },
+ { 0x11214d, 0xe00 },
+ { 0x11304d, 0xe00 },
+ { 0x11314d, 0xe00 },
+ { 0x21004d, 0xe00 },
+ { 0x21014d, 0xe00 },
+ { 0x21104d, 0xe00 },
+ { 0x21114d, 0xe00 },
+ { 0x21204d, 0xe00 },
+ { 0x21214d, 0xe00 },
+ { 0x21304d, 0xe00 },
+ { 0x21314d, 0xe00 },
+ { 0x10049, 0xeba },
+ { 0x10149, 0xeba },
+ { 0x11049, 0xeba },
+ { 0x11149, 0xeba },
+ { 0x12049, 0xeba },
+ { 0x12149, 0xeba },
+ { 0x13049, 0xeba },
+ { 0x13149, 0xeba },
+ { 0x110049, 0xeba },
+ { 0x110149, 0xeba },
+ { 0x111049, 0xeba },
+ { 0x111149, 0xeba },
+ { 0x112049, 0xeba },
+ { 0x112149, 0xeba },
+ { 0x113049, 0xeba },
+ { 0x113149, 0xeba },
+ { 0x210049, 0xeba },
+ { 0x210149, 0xeba },
+ { 0x211049, 0xeba },
+ { 0x211149, 0xeba },
+ { 0x212049, 0xeba },
+ { 0x212149, 0xeba },
+ { 0x213049, 0xeba },
+ { 0x213149, 0xeba },
+ { 0x43, 0x63 },
+ { 0x1043, 0x63 },
+ { 0x2043, 0x63 },
+ { 0x3043, 0x63 },
+ { 0x4043, 0x63 },
+ { 0x5043, 0x63 },
+ { 0x6043, 0x63 },
+ { 0x7043, 0x63 },
+ { 0x8043, 0x63 },
+ { 0x9043, 0x63 },
+ { 0x20018, 0x3 },
+ { 0x20075, 0x4 },
+ { 0x20050, 0x0 },
+ { 0x20008, 0x2ee },
+ { 0x120008, 0x64 },
+ { 0x220008, 0x19 },
+ { 0x20088, 0x9 },
+ { 0x200b2, 0xdc },
+ { 0x10043, 0x5a1 },
+ { 0x10143, 0x5a1 },
+ { 0x11043, 0x5a1 },
+ { 0x11143, 0x5a1 },
+ { 0x12043, 0x5a1 },
+ { 0x12143, 0x5a1 },
+ { 0x13043, 0x5a1 },
+ { 0x13143, 0x5a1 },
+ { 0x1200b2, 0xdc },
+ { 0x110043, 0x5a1 },
+ { 0x110143, 0x5a1 },
+ { 0x111043, 0x5a1 },
+ { 0x111143, 0x5a1 },
+ { 0x112043, 0x5a1 },
+ { 0x112143, 0x5a1 },
+ { 0x113043, 0x5a1 },
+ { 0x113143, 0x5a1 },
+ { 0x2200b2, 0xdc },
+ { 0x210043, 0x5a1 },
+ { 0x210143, 0x5a1 },
+ { 0x211043, 0x5a1 },
+ { 0x211143, 0x5a1 },
+ { 0x212043, 0x5a1 },
+ { 0x212143, 0x5a1 },
+ { 0x213043, 0x5a1 },
+ { 0x213143, 0x5a1 },
+ { 0x200fa, 0x1 },
+ { 0x1200fa, 0x1 },
+ { 0x2200fa, 0x1 },
+ { 0x20019, 0x1 },
+ { 0x120019, 0x1 },
+ { 0x220019, 0x1 },
+ { 0x200f0, 0x660 },
+ { 0x200f1, 0x0 },
+ { 0x200f2, 0x4444 },
+ { 0x200f3, 0x8888 },
+ { 0x200f4, 0x5665 },
+ { 0x200f5, 0x0 },
+ { 0x200f6, 0x0 },
+ { 0x200f7, 0xf000 },
+ { 0x20025, 0x0 },
+ { 0x2002d, 0x0 },
+ { 0x12002d, 0x0 },
+ { 0x22002d, 0x0 },
+ { 0x200c7, 0x21 },
+ { 0x1200c7, 0x21 },
+ { 0x2200c7, 0x21 },
+ { 0x200ca, 0x24 },
+ { 0x1200ca, 0x24 },
+ { 0x2200ca, 0x24 },
+};
+
+/* P0 message block paremeter for training firmware */
+static struct dram_cfg_param lpddr4_fsp0_cfg_4gb[] = {
+ { 0xd0000, 0x0 },
+ { 0x54003, 0xbb8 },
+ { 0x54004, 0x2 },
+ { 0x54005, 0x2228 },
+ { 0x54006, 0x11 },
+ { 0x54008, 0x131f },
+ { 0x54009, 0xc8 },
+ { 0x5400b, 0x2 },
+ { 0x54012, 0x310 },
+ { 0x54019, 0x2dd4 },
+ { 0x5401a, 0x31 },
+ { 0x5401b, 0x4d66 },
+ { 0x5401c, 0x4d00 },
+ { 0x5401e, 0x16 },
+ { 0x5401f, 0x2dd4 },
+ { 0x54020, 0x31 },
+ { 0x54021, 0x4d66 },
+ { 0x54022, 0x4d00 },
+ { 0x54024, 0x16 },
+ { 0x5402b, 0x1000 },
+ { 0x5402c, 0x3 },
+ { 0x54032, 0xd400 },
+ { 0x54033, 0x312d },
+ { 0x54034, 0x6600 },
+ { 0x54035, 0x4d },
+ { 0x54036, 0x4d },
+ { 0x54037, 0x1600 },
+ { 0x54038, 0xd400 },
+ { 0x54039, 0x312d },
+ { 0x5403a, 0x6600 },
+ { 0x5403b, 0x4d },
+ { 0x5403c, 0x4d },
+ { 0x5403d, 0x1600 },
+ { 0xd0000, 0x1 },
+};
+
+/* P1 message block paremeter for training firmware */
+static struct dram_cfg_param lpddr4_fsp1_cfg_4gb[] = {
+ { 0xd0000, 0x0 },
+ { 0x54002, 0x101 },
+ { 0x54003, 0x190 },
+ { 0x54004, 0x2 },
+ { 0x54005, 0x2228 },
+ { 0x54006, 0x11 },
+ { 0x54008, 0x121f },
+ { 0x54009, 0xc8 },
+ { 0x5400b, 0x2 },
+ { 0x54012, 0x310 },
+ { 0x54019, 0x84 },
+ { 0x5401a, 0x31 },
+ { 0x5401b, 0x4d66 },
+ { 0x5401c, 0x4d00 },
+ { 0x5401e, 0x16 },
+ { 0x5401f, 0x84 },
+ { 0x54020, 0x31 },
+ { 0x54021, 0x4d66 },
+ { 0x54022, 0x4d00 },
+ { 0x54024, 0x16 },
+ { 0x5402b, 0x1000 },
+ { 0x5402c, 0x3 },
+ { 0x54032, 0x8400 },
+ { 0x54033, 0x3100 },
+ { 0x54034, 0x6600 },
+ { 0x54035, 0x4d },
+ { 0x54036, 0x4d },
+ { 0x54037, 0x1600 },
+ { 0x54038, 0x8400 },
+ { 0x54039, 0x3100 },
+ { 0x5403a, 0x6600 },
+ { 0x5403b, 0x4d },
+ { 0x5403c, 0x4d },
+ { 0x5403d, 0x1600 },
+ { 0xd0000, 0x1 },
+};
+
+/* P2 message block paremeter for training firmware */
+static struct dram_cfg_param lpddr4_fsp2_cfg_4gb[] = {
+ { 0xd0000, 0x0 },
+ { 0x54002, 0x102 },
+ { 0x54003, 0x64 },
+ { 0x54004, 0x2 },
+ { 0x54005, 0x2228 },
+ { 0x54006, 0x11 },
+ { 0x54008, 0x121f },
+ { 0x54009, 0xc8 },
+ { 0x5400b, 0x2 },
+ { 0x54012, 0x310 },
+ { 0x54019, 0x84 },
+ { 0x5401a, 0x31 },
+ { 0x5401b, 0x4d66 },
+ { 0x5401c, 0x4d00 },
+ { 0x5401e, 0x16 },
+ { 0x5401f, 0x84 },
+ { 0x54020, 0x31 },
+ { 0x54021, 0x4d66 },
+ { 0x54022, 0x4d00 },
+ { 0x54024, 0x16 },
+ { 0x5402b, 0x1000 },
+ { 0x5402c, 0x3 },
+ { 0x54032, 0x8400 },
+ { 0x54033, 0x3100 },
+ { 0x54034, 0x6600 },
+ { 0x54035, 0x4d },
+ { 0x54036, 0x4d },
+ { 0x54037, 0x1600 },
+ { 0x54038, 0x8400 },
+ { 0x54039, 0x3100 },
+ { 0x5403a, 0x6600 },
+ { 0x5403b, 0x4d },
+ { 0x5403c, 0x4d },
+ { 0x5403d, 0x1600 },
+ { 0xd0000, 0x1 },
+};
+
+/* P0 2D message block paremeter for training firmware */
+static struct dram_cfg_param lpddr4_fsp0_2d_cfg_4gb[] = {
+ { 0xd0000, 0x0 },
+ { 0x54003, 0xbb8 },
+ { 0x54004, 0x2 },
+ { 0x54005, 0x2228 },
+ { 0x54006, 0x11 },
+ { 0x54008, 0x61 },
+ { 0x54009, 0xc8 },
+ { 0x5400b, 0x2 },
+ { 0x5400d, 0x100 },
+ { 0x5400f, 0x100 },
+ { 0x54010, 0x1f7f },
+ { 0x54012, 0x310 },
+ { 0x54019, 0x2dd4 },
+ { 0x5401a, 0x31 },
+ { 0x5401b, 0x4d66 },
+ { 0x5401c, 0x4d00 },
+ { 0x5401e, 0x16 },
+ { 0x5401f, 0x2dd4 },
+ { 0x54020, 0x31 },
+ { 0x54021, 0x4d66 },
+ { 0x54022, 0x4d00 },
+ { 0x54024, 0x16 },
+ { 0x5402b, 0x1000 },
+ { 0x5402c, 0x3 },
+ { 0x54032, 0xd400 },
+ { 0x54033, 0x312d },
+ { 0x54034, 0x6600 },
+ { 0x54035, 0x4d },
+ { 0x54036, 0x4d },
+ { 0x54037, 0x1600 },
+ { 0x54038, 0xd400 },
+ { 0x54039, 0x312d },
+ { 0x5403a, 0x6600 },
+ { 0x5403b, 0x4d },
+ { 0x5403c, 0x4d },
+ { 0x5403d, 0x1600 },
+ { 0xd0000, 0x1 },
+};
+
+static struct dram_fsp_msg lpddr4_dram_fsp_msg_4gb[] = {
+ {
+ /* P0 3000mts 1D */
+ .drate = 3000,
+ .fw_type = FW_1D_IMAGE,
+ .fsp_cfg = lpddr4_fsp0_cfg_4gb,
+ .fsp_cfg_num = ARRAY_SIZE(lpddr4_fsp0_cfg_4gb),
+ },
+ {
+ /* P1 400mts 1D */
+ .drate = 400,
+ .fw_type = FW_1D_IMAGE,
+ .fsp_cfg = lpddr4_fsp1_cfg_4gb,
+ .fsp_cfg_num = ARRAY_SIZE(lpddr4_fsp1_cfg_4gb),
+ },
+ {
+ /* P2 100mts 1D */
+ .drate = 100,
+ .fw_type = FW_1D_IMAGE,
+ .fsp_cfg = lpddr4_fsp2_cfg_4gb,
+ .fsp_cfg_num = ARRAY_SIZE(lpddr4_fsp2_cfg_4gb),
+ },
+ {
+ /* P0 3000mts 2D */
+ .drate = 3000,
+ .fw_type = FW_2D_IMAGE,
+ .fsp_cfg = lpddr4_fsp0_2d_cfg_4gb,
+ .fsp_cfg_num = ARRAY_SIZE(lpddr4_fsp0_2d_cfg_4gb),
+ },
+};
+
+/* lpddr4 timing config params */
+struct dram_timing_info dram_timing_4gb = {
+ .ddrc_cfg = lpddr4_ddrc_cfg_4gb,
+ .ddrc_cfg_num = ARRAY_SIZE(lpddr4_ddrc_cfg_4gb),
+ .ddrphy_cfg = lpddr4_ddrphy_cfg_4gb,
+ .ddrphy_cfg_num = ARRAY_SIZE(lpddr4_ddrphy_cfg_4gb),
+ .fsp_msg = lpddr4_dram_fsp_msg_4gb,
+ .fsp_msg_num = ARRAY_SIZE(lpddr4_dram_fsp_msg_4gb),
+ .ddrphy_trained_csr = lpddr4_ddrphy_trained_csr,
+ .ddrphy_trained_csr_num = ARRAY_SIZE(lpddr4_ddrphy_trained_csr),
+ .ddrphy_pie = lpddr4_phy_pie,
+ .ddrphy_pie_num = ARRAY_SIZE(lpddr4_phy_pie),
+ .fsp_table = { 3000, 400, 100, },
+};
diff --git a/board/gateworks/venice/lpddr4_timing.h b/board/gateworks/venice/lpddr4_timing.h
new file mode 100644
index 0000000..94445f8
--- /dev/null
+++ b/board/gateworks/venice/lpddr4_timing.h
@@ -0,0 +1,12 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright 2021 Gateworks Corporation
+ */
+
+#ifndef __LPDDR4_TIMING_H__
+#define __LPDDR4_TIMING_H__
+
+extern struct dram_timing_info dram_timing_1gb;
+extern struct dram_timing_info dram_timing_4gb;
+
+#endif /* __LPDDR4_TIMING_H__ */
diff --git a/board/gateworks/venice/spl.c b/board/gateworks/venice/spl.c
new file mode 100644
index 0000000..ea500d4
--- /dev/null
+++ b/board/gateworks/venice/spl.c
@@ -0,0 +1,205 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright 2021 Gateworks Corporation
+ */
+
+#include <common.h>
+#include <cpu_func.h>
+#include <hang.h>
+#include <i2c.h>
+#include <image.h>
+#include <init.h>
+#include <log.h>
+#include <spl.h>
+#include <asm/io.h>
+#include <asm/mach-imx/gpio.h>
+#include <asm/mach-imx/iomux-v3.h>
+#include <asm/arch/clock.h>
+#include <asm/arch/imx8mm_pins.h>
+#include <asm/arch/sys_proto.h>
+#include <asm/mach-imx/boot_mode.h>
+#include <asm/arch/ddr.h>
+#include <asm-generic/gpio.h>
+
+#include <dm/uclass.h>
+#include <dm/device.h>
+#include <dm/uclass-internal.h>
+#include <dm/device-internal.h>
+
+#include <power/mp5416.h>
+
+#include "gsc.h"
+#include "lpddr4_timing.h"
+
+#define PCIE_RSTN IMX_GPIO_NR(4, 6)
+
+DECLARE_GLOBAL_DATA_PTR;
+
+static void spl_dram_init(int size)
+{
+ struct dram_timing_info *dram_timing;
+
+ switch (size) {
+ case 1:
+ dram_timing = &dram_timing_1gb;
+ break;
+ case 4:
+ dram_timing = &dram_timing_4gb;
+ break;
+ default:
+ printf("Unknown DDR configuration: %d GiB\n", size);
+ dram_timing = &dram_timing_1gb;
+ size = 1;
+ }
+
+ printf("DRAM : LPDDR4 %d GiB\n", size);
+ ddr_init(dram_timing);
+ writel(size, M4_BOOTROM_BASE_ADDR);
+}
+
+#define UART_PAD_CTRL (PAD_CTL_DSE6 | PAD_CTL_FSEL1)
+#define WDOG_PAD_CTRL (PAD_CTL_DSE6 | PAD_CTL_ODE | PAD_CTL_PUE | PAD_CTL_PE)
+
+static iomux_v3_cfg_t const uart_pads[] = {
+ IMX8MM_PAD_UART2_RXD_UART2_RX | MUX_PAD_CTRL(UART_PAD_CTRL),
+ IMX8MM_PAD_UART2_TXD_UART2_TX | MUX_PAD_CTRL(UART_PAD_CTRL),
+};
+
+static iomux_v3_cfg_t const wdog_pads[] = {
+ IMX8MM_PAD_GPIO1_IO02_WDOG1_WDOG_B | MUX_PAD_CTRL(WDOG_PAD_CTRL),
+};
+
+int board_early_init_f(void)
+{
+ struct wdog_regs *wdog = (struct wdog_regs *)WDOG1_BASE_ADDR;
+
+ imx_iomux_v3_setup_multiple_pads(wdog_pads, ARRAY_SIZE(wdog_pads));
+
+ set_wdog_reset(wdog);
+
+ imx_iomux_v3_setup_multiple_pads(uart_pads, ARRAY_SIZE(uart_pads));
+
+ return 0;
+}
+
+/*
+ * Model specific PMIC adjustments necessary prior to DRAM init
+ *
+ * Note that we can not use pmic dm drivers here as we have a generic
+ * venice dt that does not have board-specific pmic's defined.
+ *
+ * Instead we must use dm_i2c.
+ */
+static int power_init_board(void)
+{
+ const char *model = gsc_get_model();
+ struct udevice *bus;
+ struct udevice *dev;
+ int ret;
+
+ if ((!strncmp(model, "GW71", 4)) ||
+ (!strncmp(model, "GW72", 4)) ||
+ (!strncmp(model, "GW73", 4))) {
+ ret = uclass_get_device_by_name(UCLASS_I2C, "i2c@30a20000", &bus);
+ if (ret) {
+ printf("PMIC : failed I2C1 probe: %d\n", ret);
+ return ret;
+ }
+ ret = dm_i2c_probe(bus, 0x69, 0, &dev);
+ if (ret) {
+ printf("PMIC : failed probe: %d\n", ret);
+ return ret;
+ }
+ puts("PMIC : MP5416\n");
+
+ /* set VDD_ARM SW3 to 0.92V for 1.6GHz */
+ dm_i2c_reg_write(dev, MP5416_VSET_SW3,
+ BIT(7) | MP5416_VSET_SW3_SVAL(920000));
+ }
+
+ return 0;
+}
+
+void board_init_f(ulong dummy)
+{
+ struct udevice *dev;
+ int ret;
+ int dram_sz;
+
+ arch_cpu_init();
+
+ init_uart_clk(1);
+
+ board_early_init_f();
+
+ timer_init();
+
+ preloader_console_init();
+
+ /* Clear the BSS. */
+ memset(__bss_start, 0, __bss_end - __bss_start);
+
+ ret = spl_early_init();
+ if (ret) {
+ debug("spl_early_init() failed: %d\n", ret);
+ hang();
+ }
+
+ ret = uclass_get_device_by_name(UCLASS_CLK,
+ "clock-controller@30380000",
+ &dev);
+ if (ret < 0) {
+ printf("Failed to find clock node. Check device tree\n");
+ hang();
+ }
+
+ enable_tzc380();
+
+ /* need to hold PCIe switch in reset otherwise it can lock i2c bus EEPROM is on */
+ gpio_request(PCIE_RSTN, "perst#");
+ gpio_direction_output(PCIE_RSTN, 0);
+
+ /* GSC */
+ dram_sz = gsc_init(0);
+
+ /* PMIC */
+ power_init_board();
+
+ /* DDR initialization */
+ spl_dram_init(dram_sz);
+
+ board_init_r(NULL, 0);
+}
+
+/* determine prioritized order of boot devices to load U-Boot from */
+void board_boot_order(u32 *spl_boot_list)
+{
+ /*
+ * If the SPL was loaded via serial loader, we try to get
+ * U-Boot proper via USB SDP.
+ */
+ if (spl_boot_device() == BOOT_DEVICE_BOARD)
+ spl_boot_list[0] = BOOT_DEVICE_BOARD;
+
+ /* we have only eMMC in default venice dt */
+ spl_boot_list[0] = BOOT_DEVICE_MMC1;
+}
+
+/* return boot device based on where the SPL was loaded from */
+int spl_board_boot_device(enum boot_device boot_dev_spl)
+{
+ switch (boot_dev_spl) {
+ case USB_BOOT:
+ return BOOT_DEVICE_BOARD;
+ /* SDHC2 */
+ case SD2_BOOT:
+ case MMC2_BOOT:
+ return BOOT_DEVICE_MMC1;
+ /* SDHC3 */
+ case SD3_BOOT:
+ case MMC3_BOOT:
+ return BOOT_DEVICE_MMC2;
+ default:
+ return BOOT_DEVICE_NONE;
+ }
+}
diff --git a/board/gdsys/a38x/controlcenterdc.c b/board/gdsys/a38x/controlcenterdc.c
index ba57a27..4f1dc3b 100644
--- a/board/gdsys/a38x/controlcenterdc.c
+++ b/board/gdsys/a38x/controlcenterdc.c
@@ -71,6 +71,7 @@
MV_DDR_TIM_DEFAULT} }, /* timing */
BUS_MASK_32BIT, /* Busses mask */
MV_DDR_CFG_DEFAULT, /* ddr configuration data source */
+ NOT_COMBINED, /* ddr twin-die combined */
{ {0} }, /* raw spd data */
{0} /* timing parameters */
diff --git a/board/intel/agilex-socdk/MAINTAINERS b/board/intel/agilex-socdk/MAINTAINERS
index 18edbdc..fd05e9a 100644
--- a/board/intel/agilex-socdk/MAINTAINERS
+++ b/board/intel/agilex-socdk/MAINTAINERS
@@ -6,3 +6,8 @@
F: include/configs/socfpga_agilex_socdk.h
F: configs/socfpga_agilex_atf_defconfig
F: configs/socfpga_agilex_defconfig
+
+SOCFPGA BOARD WITH VAB
+M: Siew Chin Lim <elly.siew.chin.lim@intel.com>
+S: Maintained
+F: configs/socfpga_agilex_vab_defconfig
diff --git a/board/kobol/helios4/helios4.c b/board/kobol/helios4/helios4.c
index adb091c..9c5b687 100644
--- a/board/kobol/helios4/helios4.c
+++ b/board/kobol/helios4/helios4.c
@@ -71,6 +71,7 @@
MV_DDR_TIM_DEFAULT} }, /* timing */
BUS_MASK_32BIT_ECC, /* Busses mask */
MV_DDR_CFG_DEFAULT, /* ddr configuration data source */
+ NOT_COMBINED, /* ddr twin-die combined */
{ {0} }, /* raw spd data */
{0} /* timing parameters */
};
diff --git a/board/nokia/rx51/rx51.c b/board/nokia/rx51/rx51.c
index 1f508d5..7bd5fbd 100644
--- a/board/nokia/rx51/rx51.c
+++ b/board/nokia/rx51/rx51.c
@@ -40,9 +40,24 @@
#include <asm/arch/sys_proto.h>
#include <asm/arch/mmc_host_def.h>
-#include "rx51.h"
#include "tag_omap.h"
+/* Needed for ROM SMC call */
+struct emu_hal_params_rx51 {
+ u32 num_params;
+ u32 param1;
+ u32 param2;
+ u32 param3;
+ u32 param4;
+};
+
+#define ONENAND_GPMC_CONFIG1_RX51 0xfb001202
+#define ONENAND_GPMC_CONFIG2_RX51 0x00111100
+#define ONENAND_GPMC_CONFIG3_RX51 0x00020200
+#define ONENAND_GPMC_CONFIG4_RX51 0x11001102
+#define ONENAND_GPMC_CONFIG5_RX51 0x03101616
+#define ONENAND_GPMC_CONFIG6_RX51 0x90060000
+
DECLARE_GLOBAL_DATA_PTR;
GraphicDevice gdev;
@@ -468,17 +483,6 @@
return 0;
}
-/*
- * Routine: set_muxconf_regs
- * Description: Setting up the configuration Mux registers specific to the
- * hardware. Many pins need to be moved from protect to primary
- * mode.
- */
-void set_muxconf_regs(void)
-{
- MUX_RX51();
-}
-
static unsigned long int twl_wd_time; /* last time of watchdog reset */
static unsigned long int twl_i2c_lock;
diff --git a/board/nokia/rx51/rx51.h b/board/nokia/rx51/rx51.h
deleted file mode 100644
index 4eff823..0000000
--- a/board/nokia/rx51/rx51.h
+++ /dev/null
@@ -1,377 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0+ */
-/*
- * (C) Copyright 2012
- * Ивайло Димитров <freemangordon@abv.bg>
- *
- * (C) Copyright 2011-2012
- * Pali Rohár <pali@kernel.org>
- *
- * (C) Copyright 2008
- * Dirk Behme <dirk.behme@gmail.com>
- */
-#ifndef _RX51_H_
-#define _RX51_H_
-
-/* Needed for ROM SMC call */
-struct emu_hal_params_rx51 {
- u32 num_params;
- u32 param1;
- u32 param2;
- u32 param3;
- u32 param4;
-};
-
-/*
- * IEN - Input Enable
- * IDIS - Input Disable
- * PTD - Pull type Down
- * PTU - Pull type Up
- * DIS - Pull type selection is inactive
- * EN - Pull type selection is active
- * M0 - Mode 0
- * The commented string gives the final mux configuration for that pin
- */
-#define MUX_RX51() \
-/* SDRC */\
- MUX_VAL(CP(SDRC_D0), (IEN | PTD | DIS | M0)) /*SDRC_D0*/\
- MUX_VAL(CP(SDRC_D1), (IEN | PTD | DIS | M0)) /*SDRC_D1*/\
- MUX_VAL(CP(SDRC_D2), (IEN | PTD | DIS | M0)) /*SDRC_D2*/\
- MUX_VAL(CP(SDRC_D3), (IEN | PTD | DIS | M0)) /*SDRC_D3*/\
- MUX_VAL(CP(SDRC_D4), (IEN | PTD | DIS | M0)) /*SDRC_D4*/\
- MUX_VAL(CP(SDRC_D5), (IEN | PTD | DIS | M0)) /*SDRC_D5*/\
- MUX_VAL(CP(SDRC_D6), (IEN | PTD | DIS | M0)) /*SDRC_D6*/\
- MUX_VAL(CP(SDRC_D7), (IEN | PTD | DIS | M0)) /*SDRC_D7*/\
- MUX_VAL(CP(SDRC_D8), (IEN | PTD | DIS | M0)) /*SDRC_D8*/\
- MUX_VAL(CP(SDRC_D9), (IEN | PTD | DIS | M0)) /*SDRC_D9*/\
- MUX_VAL(CP(SDRC_D10), (IEN | PTD | DIS | M0)) /*SDRC_D10*/\
- MUX_VAL(CP(SDRC_D11), (IEN | PTD | DIS | M0)) /*SDRC_D11*/\
- MUX_VAL(CP(SDRC_D12), (IEN | PTD | DIS | M0)) /*SDRC_D12*/\
- MUX_VAL(CP(SDRC_D13), (IEN | PTD | DIS | M0)) /*SDRC_D13*/\
- MUX_VAL(CP(SDRC_D14), (IEN | PTD | DIS | M0)) /*SDRC_D14*/\
- MUX_VAL(CP(SDRC_D15), (IEN | PTD | DIS | M0)) /*SDRC_D15*/\
- MUX_VAL(CP(SDRC_D16), (IEN | PTD | DIS | M0)) /*SDRC_D16*/\
- MUX_VAL(CP(SDRC_D17), (IEN | PTD | DIS | M0)) /*SDRC_D17*/\
- MUX_VAL(CP(SDRC_D18), (IEN | PTD | DIS | M0)) /*SDRC_D18*/\
- MUX_VAL(CP(SDRC_D19), (IEN | PTD | DIS | M0)) /*SDRC_D19*/\
- MUX_VAL(CP(SDRC_D20), (IEN | PTD | DIS | M0)) /*SDRC_D20*/\
- MUX_VAL(CP(SDRC_D21), (IEN | PTD | DIS | M0)) /*SDRC_D21*/\
- MUX_VAL(CP(SDRC_D22), (IEN | PTD | DIS | M0)) /*SDRC_D22*/\
- MUX_VAL(CP(SDRC_D23), (IEN | PTD | DIS | M0)) /*SDRC_D23*/\
- MUX_VAL(CP(SDRC_D24), (IEN | PTD | DIS | M0)) /*SDRC_D24*/\
- MUX_VAL(CP(SDRC_D25), (IEN | PTD | DIS | M0)) /*SDRC_D25*/\
- MUX_VAL(CP(SDRC_D26), (IEN | PTD | DIS | M0)) /*SDRC_D26*/\
- MUX_VAL(CP(SDRC_D27), (IEN | PTD | DIS | M0)) /*SDRC_D27*/\
- MUX_VAL(CP(SDRC_D28), (IEN | PTD | DIS | M0)) /*SDRC_D28*/\
- MUX_VAL(CP(SDRC_D29), (IEN | PTD | DIS | M0)) /*SDRC_D29*/\
- MUX_VAL(CP(SDRC_D30), (IEN | PTD | DIS | M0)) /*SDRC_D30*/\
- MUX_VAL(CP(SDRC_D31), (IEN | PTD | DIS | M0)) /*SDRC_D31*/\
- MUX_VAL(CP(SDRC_CLK), (IEN | PTD | DIS | M0)) /*SDRC_CLK*/\
- MUX_VAL(CP(SDRC_DQS0), (IEN | PTD | DIS | M0)) /*SDRC_DQS0*/\
- MUX_VAL(CP(SDRC_DQS1), (IEN | PTD | DIS | M0)) /*SDRC_DQS1*/\
- MUX_VAL(CP(SDRC_DQS2), (IEN | PTD | DIS | M0)) /*SDRC_DQS2*/\
- MUX_VAL(CP(SDRC_DQS3), (IEN | PTD | DIS | M0)) /*SDRC_DQS3*/\
-/* GPMC */\
- MUX_VAL(CP(GPMC_A1), (IDIS | PTD | DIS | M0)) /*GPMC_A1*/\
- MUX_VAL(CP(GPMC_A2), (IDIS | PTD | DIS | M0)) /*GPMC_A2*/\
- MUX_VAL(CP(GPMC_A3), (IDIS | PTD | DIS | M0)) /*GPMC_A3*/\
- MUX_VAL(CP(GPMC_A4), (IDIS | PTD | DIS | M0)) /*GPMC_A4*/\
- MUX_VAL(CP(GPMC_A5), (IDIS | PTD | DIS | M0)) /*GPMC_A5*/\
- MUX_VAL(CP(GPMC_A6), (IDIS | PTD | DIS | M0)) /*GPMC_A6*/\
- MUX_VAL(CP(GPMC_A7), (IDIS | PTD | DIS | M0)) /*GPMC_A7*/\
- MUX_VAL(CP(GPMC_A8), (IDIS | PTD | DIS | M0)) /*GPMC_A8*/\
- MUX_VAL(CP(GPMC_A9), (IDIS | PTD | DIS | M0)) /*GPMC_A9*/\
- MUX_VAL(CP(GPMC_A10), (IDIS | PTD | DIS | M0)) /*GPMC_A10*/\
- MUX_VAL(CP(GPMC_D0), (IEN | PTD | DIS | M0)) /*GPMC_D0*/\
- MUX_VAL(CP(GPMC_D1), (IEN | PTD | DIS | M0)) /*GPMC_D1*/\
- MUX_VAL(CP(GPMC_D2), (IEN | PTD | DIS | M0)) /*GPMC_D2*/\
- MUX_VAL(CP(GPMC_D3), (IEN | PTD | DIS | M0)) /*GPMC_D3*/\
- MUX_VAL(CP(GPMC_D4), (IEN | PTD | DIS | M0)) /*GPMC_D4*/\
- MUX_VAL(CP(GPMC_D5), (IEN | PTD | DIS | M0)) /*GPMC_D5*/\
- MUX_VAL(CP(GPMC_D6), (IEN | PTD | DIS | M0)) /*GPMC_D6*/\
- MUX_VAL(CP(GPMC_D7), (IEN | PTD | DIS | M0)) /*GPMC_D7*/\
- MUX_VAL(CP(GPMC_D8), (IEN | PTD | DIS | M0)) /*GPMC_D8*/\
- MUX_VAL(CP(GPMC_D9), (IEN | PTD | DIS | M0)) /*GPMC_D9*/\
- MUX_VAL(CP(GPMC_D10), (IEN | PTD | DIS | M0)) /*GPMC_D10*/\
- MUX_VAL(CP(GPMC_D11), (IEN | PTD | DIS | M0)) /*GPMC_D11*/\
- MUX_VAL(CP(GPMC_D12), (IEN | PTD | DIS | M0)) /*GPMC_D12*/\
- MUX_VAL(CP(GPMC_D13), (IEN | PTD | DIS | M0)) /*GPMC_D13*/\
- MUX_VAL(CP(GPMC_D14), (IEN | PTD | DIS | M0)) /*GPMC_D14*/\
- MUX_VAL(CP(GPMC_D15), (IEN | PTD | DIS | M0)) /*GPMC_D15*/\
- MUX_VAL(CP(GPMC_NCS0), (IDIS | PTU | EN | M0)) /*GPMC_nCS0*/\
- MUX_VAL(CP(GPMC_NCS1), (IDIS | PTU | EN | M0)) /*GPMC_nCS1*/\
- MUX_VAL(CP(GPMC_NCS2), (IDIS | PTU | EN | M0)) /*GPMC_nCS2*/\
- MUX_VAL(CP(GPMC_NCS3), (IDIS | PTU | EN | M0)) /*GPMC_nCS3*/\
- MUX_VAL(CP(GPMC_NCS4), (IDIS | PTU | EN | M0)) /*GPMC_nCS4*/\
- MUX_VAL(CP(GPMC_NCS5), (IDIS | PTD | DIS | M0)) /*GPMC_nCS5*/\
- MUX_VAL(CP(GPMC_NCS6), (IEN | PTD | DIS | M1)) /*nDMA_REQ2*/\
- MUX_VAL(CP(GPMC_NCS7), (IEN | PTU | EN | M1)) /*nDMA_REQ3*/\
- MUX_VAL(CP(GPMC_NBE1), (IEN | PTD | DIS | M0)) /*GPMC_nBE1*/\
- MUX_VAL(CP(GPMC_WAIT2), (IEN | PTU | EN | M0)) /*GPMC_WAIT2*/\
- MUX_VAL(CP(GPMC_WAIT3), (IEN | PTU | EN | M0)) /*GPMC_WAIT3*/\
- MUX_VAL(CP(GPMC_CLK), (IDIS | PTD | DIS | M0)) /*GPMC_CLK*/\
- MUX_VAL(CP(GPMC_NADV_ALE), (IDIS | PTD | DIS | M0)) /*GPMC_nADV*/\
- MUX_VAL(CP(GPMC_NOE), (IDIS | PTD | DIS | M0)) /*GPMC_nOE*/\
- MUX_VAL(CP(GPMC_NWE), (IDIS | PTD | DIS | M0)) /*GPMC_nWE*/\
- MUX_VAL(CP(GPMC_NBE0_CLE), (IDIS | PTD | DIS | M0)) /*GPMC_nBE0*/\
- MUX_VAL(CP(GPMC_NWP), (IEN | PTD | DIS | M0)) /*GPMC_nWP*/\
- MUX_VAL(CP(GPMC_WAIT0), (IEN | PTU | EN | M0)) /*GPMC_WAIT0*/\
- MUX_VAL(CP(GPMC_WAIT1), (IEN | PTU | EN | M0)) /*GPMC_WAIT1*/\
-/* DSS */\
- MUX_VAL(CP(DSS_PCLK), (IDIS | PTD | DIS | M0)) /*DSS_PCLK*/\
- MUX_VAL(CP(DSS_HSYNC), (IDIS | PTD | DIS | M0)) /*DSS_HSYNC*/\
- MUX_VAL(CP(DSS_VSYNC), (IDIS | PTD | DIS | M0)) /*DSS_VSYNC*/\
- MUX_VAL(CP(DSS_ACBIAS), (IDIS | PTD | DIS | M0)) /*DSS_ACBIAS*/\
- MUX_VAL(CP(DSS_DATA0), (IDIS | PTD | DIS | M0)) /*DSS_DATA0*/\
- MUX_VAL(CP(DSS_DATA1), (IDIS | PTD | DIS | M0)) /*DSS_DATA1*/\
- MUX_VAL(CP(DSS_DATA2), (IDIS | PTD | DIS | M0)) /*DSS_DATA2*/\
- MUX_VAL(CP(DSS_DATA3), (IDIS | PTD | DIS | M0)) /*DSS_DATA3*/\
- MUX_VAL(CP(DSS_DATA4), (IDIS | PTD | DIS | M0)) /*DSS_DATA4*/\
- MUX_VAL(CP(DSS_DATA5), (IDIS | PTD | DIS | M0)) /*DSS_DATA5*/\
- MUX_VAL(CP(DSS_DATA6), (IDIS | PTD | DIS | M0)) /*DSS_DATA6*/\
- MUX_VAL(CP(DSS_DATA7), (IDIS | PTD | DIS | M0)) /*DSS_DATA7*/\
- MUX_VAL(CP(DSS_DATA8), (IDIS | PTD | DIS | M0)) /*DSS_DATA8*/\
- MUX_VAL(CP(DSS_DATA9), (IDIS | PTD | DIS | M0)) /*DSS_DATA9*/\
- MUX_VAL(CP(DSS_DATA10), (IDIS | PTD | DIS | M0)) /*DSS_DATA10*/\
- MUX_VAL(CP(DSS_DATA11), (IDIS | PTD | DIS | M0)) /*DSS_DATA11*/\
- MUX_VAL(CP(DSS_DATA12), (IDIS | PTD | DIS | M0)) /*DSS_DATA12*/\
- MUX_VAL(CP(DSS_DATA13), (IDIS | PTD | DIS | M0)) /*DSS_DATA13*/\
- MUX_VAL(CP(DSS_DATA14), (IDIS | PTD | DIS | M0)) /*DSS_DATA14*/\
- MUX_VAL(CP(DSS_DATA15), (IDIS | PTD | DIS | M0)) /*DSS_DATA15*/\
- MUX_VAL(CP(DSS_DATA16), (IDIS | PTD | DIS | M0)) /*DSS_DATA16*/\
- MUX_VAL(CP(DSS_DATA17), (IDIS | PTD | DIS | M0)) /*DSS_DATA17*/\
- MUX_VAL(CP(DSS_DATA18), (IDIS | PTD | DIS | M0)) /*DSS_DATA18*/\
- MUX_VAL(CP(DSS_DATA19), (IDIS | PTD | DIS | M0)) /*DSS_DATA19*/\
- MUX_VAL(CP(DSS_DATA20), (IDIS | PTD | DIS | M0)) /*DSS_DATA20*/\
- MUX_VAL(CP(DSS_DATA21), (IDIS | PTD | DIS | M0)) /*DSS_DATA21*/\
- MUX_VAL(CP(DSS_DATA22), (IDIS | PTD | DIS | M0)) /*DSS_DATA22*/\
- MUX_VAL(CP(DSS_DATA23), (IDIS | PTD | DIS | M0)) /*DSS_DATA23*/\
-/* CAMERA */\
- MUX_VAL(CP(CAM_HS), (IEN | PTU | EN | M0)) /*CAM_HS*/\
- MUX_VAL(CP(CAM_VS), (IEN | PTU | EN | M0)) /*CAM_VS*/\
- MUX_VAL(CP(CAM_XCLKA), (IDIS | PTD | DIS | M0)) /*CAM_XCLKA*/\
- MUX_VAL(CP(CAM_PCLK), (IEN | PTU | EN | M0)) /*CAM_PCLK*/\
- MUX_VAL(CP(CAM_FLD), (IDIS | PTD | DIS | M4)) /*GPIO_98*/\
- MUX_VAL(CP(CAM_D0), (IEN | PTD | DIS | M0)) /*CAM_D0*/\
- MUX_VAL(CP(CAM_D1), (IEN | PTD | DIS | M0)) /*CAM_D1*/\
- MUX_VAL(CP(CAM_D2), (IEN | PTD | DIS | M0)) /*CAM_D2*/\
- MUX_VAL(CP(CAM_D3), (IEN | PTD | DIS | M0)) /*CAM_D3*/\
- MUX_VAL(CP(CAM_D4), (IEN | PTD | DIS | M0)) /*CAM_D4*/\
- MUX_VAL(CP(CAM_D5), (IEN | PTD | DIS | M0)) /*CAM_D5*/\
- MUX_VAL(CP(CAM_D6), (IEN | PTD | DIS | M0)) /*CAM_D6*/\
- MUX_VAL(CP(CAM_D7), (IEN | PTD | DIS | M0)) /*CAM_D7*/\
- MUX_VAL(CP(CAM_D8), (IEN | PTD | DIS | M0)) /*CAM_D8*/\
- MUX_VAL(CP(CAM_D9), (IEN | PTD | DIS | M0)) /*CAM_D9*/\
- MUX_VAL(CP(CAM_D10), (IEN | PTD | DIS | M0)) /*CAM_D10*/\
- MUX_VAL(CP(CAM_D11), (IEN | PTD | DIS | M0)) /*CAM_D11*/\
- MUX_VAL(CP(CAM_XCLKB), (IDIS | PTD | DIS | M0)) /*CAM_XCLKB*/\
- MUX_VAL(CP(CAM_WEN), (IEN | PTD | DIS | M4)) /*GPIO_167*/\
- MUX_VAL(CP(CAM_STROBE), (IDIS | PTD | DIS | M0)) /*CAM_STROBE*/\
- MUX_VAL(CP(CSI2_DX0), (IEN | PTD | DIS | M0)) /*CSI2_DX0*/\
- MUX_VAL(CP(CSI2_DY0), (IEN | PTD | DIS | M0)) /*CSI2_DY0*/\
- MUX_VAL(CP(CSI2_DX1), (IEN | PTD | DIS | M0)) /*CSI2_DX1*/\
- MUX_VAL(CP(CSI2_DY1), (IEN | PTD | DIS | M0)) /*CSI2_DY1*/\
-/* Audio Interface */\
- MUX_VAL(CP(MCBSP2_FSX), (IEN | PTD | DIS | M0)) /*McBSP2_FSX*/\
- MUX_VAL(CP(MCBSP2_CLKX), (IEN | PTD | DIS | M0)) /*McBSP2_CLK*/\
- MUX_VAL(CP(MCBSP2_DR), (IEN | PTD | DIS | M0)) /*McBSP2_DR*/\
- MUX_VAL(CP(MCBSP2_DX), (IDIS | PTD | DIS | M0)) /*McBSP2_DX*/\
-/* Expansion card */\
- MUX_VAL(CP(MMC1_CLK), (IDIS | PTU | EN | M0)) /*MMC1_CLK*/\
- MUX_VAL(CP(MMC1_CMD), (IEN | PTU | EN | M0)) /*MMC1_CMD*/\
- MUX_VAL(CP(MMC1_DAT0), (IEN | PTU | EN | M0)) /*MMC1_DAT0*/\
- MUX_VAL(CP(MMC1_DAT1), (IEN | PTU | EN | M0)) /*MMC1_DAT1*/\
- MUX_VAL(CP(MMC1_DAT2), (IEN | PTU | EN | M0)) /*MMC1_DAT2*/\
- MUX_VAL(CP(MMC1_DAT3), (IEN | PTU | EN | M0)) /*MMC1_DAT3*/\
- MUX_VAL(CP(MMC1_DAT4), (IEN | PTU | EN | M0)) /*MMC1_DAT4*/\
- MUX_VAL(CP(MMC1_DAT5), (IEN | PTU | EN | M0)) /*MMC1_DAT5*/\
- MUX_VAL(CP(MMC1_DAT6), (IEN | PTU | EN | M0)) /*MMC1_DAT6*/\
- MUX_VAL(CP(MMC1_DAT7), (IEN | PTU | EN | M0)) /*MMC1_DAT7*/\
-/* Wireless LAN */\
- MUX_VAL(CP(MMC2_CLK), (IEN | PTU | EN | M4)) /*GPIO_130*/\
- MUX_VAL(CP(MMC2_CMD), (IEN | PTU | EN | M4)) /*GPIO_131*/\
- MUX_VAL(CP(MMC2_DAT0), (IEN | PTU | EN | M4)) /*GPIO_132*/\
- MUX_VAL(CP(MMC2_DAT1), (IEN | PTU | EN | M4)) /*GPIO_133*/\
- MUX_VAL(CP(MMC2_DAT2), (IEN | PTU | EN | M4)) /*GPIO_134*/\
- MUX_VAL(CP(MMC2_DAT3), (IEN | PTU | EN | M4)) /*GPIO_135*/\
- MUX_VAL(CP(MMC2_DAT4), (IEN | PTU | EN | M4)) /*GPIO_136*/\
- MUX_VAL(CP(MMC2_DAT5), (IEN | PTU | EN | M4)) /*GPIO_137*/\
- MUX_VAL(CP(MMC2_DAT6), (IEN | PTU | EN | M4)) /*GPIO_138*/\
- MUX_VAL(CP(MMC2_DAT7), (IEN | PTU | EN | M4)) /*GPIO_139*/\
-/* Bluetooth */\
- MUX_VAL(CP(MCBSP3_DX), (IEN | PTD | DIS | M1)) /*UART2_CTS*/\
- MUX_VAL(CP(MCBSP3_DR), (IDIS | PTD | DIS | M1)) /*UART2_RTS*/\
- MUX_VAL(CP(MCBSP3_CLKX), (IDIS | PTD | DIS | M1)) /*UART2_TX*/\
- MUX_VAL(CP(MCBSP3_FSX), (IEN | PTD | DIS | M1)) /*UART2_RX*/\
- MUX_VAL(CP(UART2_CTS), (IEN | PTD | DIS | M4)) /*GPIO_144*/\
- MUX_VAL(CP(UART2_RTS), (IEN | PTD | DIS | M4)) /*GPIO_145*/\
- MUX_VAL(CP(UART2_TX), (IEN | PTD | DIS | M4)) /*GPIO_146*/\
- MUX_VAL(CP(UART2_RX), (IEN | PTD | DIS | M4)) /*GPIO_147*/\
-/* Modem Interface */\
- MUX_VAL(CP(UART1_TX), (IDIS | PTD | DIS | M0)) /*UART1_TX*/\
- MUX_VAL(CP(UART1_RTS), (IDIS | PTD | DIS | M4)) /*GPIO_149*/\
- MUX_VAL(CP(UART1_CTS), (IDIS | PTD | DIS | M4)) /*GPIO_150*/\
- MUX_VAL(CP(UART1_RX), (IEN | PTD | DIS | M0)) /*UART1_RX*/\
- MUX_VAL(CP(MCBSP4_CLKX), (IEN | PTD | DIS | M1)) /*SSI1_DAT*/\
- MUX_VAL(CP(MCBSP4_DR), (IEN | PTD | DIS | M1)) /*SSI1_FLAG*/\
- MUX_VAL(CP(MCBSP4_DX), (IEN | PTD | DIS | M1)) /*SSI1_RDY*/\
- MUX_VAL(CP(MCBSP4_FSX), (IEN | PTD | DIS | M1)) /*SSI1_WAKE*/\
- MUX_VAL(CP(MCBSP1_CLKR), (IDIS | PTD | DIS | M4)) /*GPIO_156*/\
- MUX_VAL(CP(MCBSP1_FSR), (IDIS | PTU | EN | M4)) /*GPIO_157*/\
- MUX_VAL(CP(MCBSP1_DX), (IDIS | PTD | DIS | M4)) /*GPIO_158*/\
- MUX_VAL(CP(MCBSP1_DR), (IDIS | PTD | DIS | M4)) /*GPIO_159*/\
- MUX_VAL(CP(MCBSP_CLKS), (IEN | PTU | DIS | M0)) /*McBSP_CLKS*/\
- MUX_VAL(CP(MCBSP1_FSX), (IDIS | PTD | DIS | M4)) /*GPIO_161*/\
- MUX_VAL(CP(MCBSP1_CLKX), (IDIS | PTD | DIS | M4)) /*GPIO_162*/\
-/* Serial Interface */\
- MUX_VAL(CP(UART3_CTS_RCTX), (IEN | PTD | EN | M0)) /*UART3_CTS*/\
- MUX_VAL(CP(UART3_RTS_SD), (IDIS | PTD | DIS | M0)) /*UART3_RTS*/\
- MUX_VAL(CP(UART3_RX_IRRX), (IEN | PTD | DIS | M0)) /*UART3_RX*/\
- MUX_VAL(CP(UART3_TX_IRTX), (IDIS | PTD | DIS | M0)) /*UART3_TX*/\
- MUX_VAL(CP(HSUSB0_CLK), (IEN | PTD | DIS | M0)) /*HSUSB0_CLK*/\
- MUX_VAL(CP(HSUSB0_STP), (IDIS | PTU | EN | M0)) /*HSUSB0_STP*/\
- MUX_VAL(CP(HSUSB0_DIR), (IEN | PTD | DIS | M0)) /*HSUSB0_DIR*/\
- MUX_VAL(CP(HSUSB0_NXT), (IEN | PTD | DIS | M0)) /*HSUSB0_NXT*/\
- MUX_VAL(CP(HSUSB0_DATA0), (IEN | PTD | DIS | M0)) /*HSUSB0_DA0*/\
- MUX_VAL(CP(HSUSB0_DATA1), (IEN | PTD | DIS | M0)) /*HSUSB0_DA1*/\
- MUX_VAL(CP(HSUSB0_DATA2), (IEN | PTD | DIS | M0)) /*HSUSB0_DA2*/\
- MUX_VAL(CP(HSUSB0_DATA3), (IEN | PTD | DIS | M0)) /*HSUSB0_DA3*/\
- MUX_VAL(CP(HSUSB0_DATA4), (IEN | PTD | DIS | M0)) /*HSUSB0_DA4*/\
- MUX_VAL(CP(HSUSB0_DATA5), (IEN | PTD | DIS | M0)) /*HSUSB0_DA5*/\
- MUX_VAL(CP(HSUSB0_DATA6), (IEN | PTD | DIS | M0)) /*HSUSB0_DA6*/\
- MUX_VAL(CP(HSUSB0_DATA7), (IEN | PTD | DIS | M0)) /*HSUSB0_DA7*/\
- MUX_VAL(CP(I2C1_SCL), (IEN | PTU | EN | M0)) /*I2C1_SCL*/\
- MUX_VAL(CP(I2C1_SDA), (IEN | PTU | EN | M0)) /*I2C1_SDA*/\
- MUX_VAL(CP(I2C2_SCL), (IEN | PTU | EN | M4)) /*GPIO_168*/\
- MUX_VAL(CP(I2C2_SDA), (IEN | PTU | EN | M4)) /*GPIO_183*/\
- MUX_VAL(CP(I2C3_SCL), (IEN | PTU | EN | M0)) /*I2C3_SCL*/\
- MUX_VAL(CP(I2C3_SDA), (IEN | PTU | EN | M0)) /*I2C3_SDA*/\
- MUX_VAL(CP(I2C4_SCL), (IEN | PTU | EN | M0)) /*I2C4_SCL*/\
- MUX_VAL(CP(I2C4_SDA), (IEN | PTU | EN | M0)) /*I2C4_SDA*/\
- MUX_VAL(CP(HDQ_SIO), (IDIS | PTU | EN | M4)) /*GPIO_170*/\
- MUX_VAL(CP(MCSPI1_CLK), (IEN | PTU | EN | M4)) /*GPIO_171*/\
- MUX_VAL(CP(MCSPI1_SIMO), (IEN | PTU | EN | M4)) /*GPIO_172*/\
- MUX_VAL(CP(MCSPI1_SOMI), (IEN | PTD | DIS | M0)) /*McSPI1_SOM*/\
- MUX_VAL(CP(MCSPI1_CS0), (IEN | PTD | EN | M0)) /*McSPI1_CS0*/\
- MUX_VAL(CP(MCSPI1_CS1), (IDIS | PTD | EN | M0)) /*McSPI1_CS1*/\
- MUX_VAL(CP(MCSPI1_CS2), (IDIS | PTD | DIS | M4)) /*GPIO_176*/\
-/* USB EHCI (port 2) */\
- MUX_VAL(CP(MCSPI1_CS3), (IEN | PTU | DIS | M3)) /*HSUSB2_DA2*/\
- MUX_VAL(CP(MCSPI2_CLK), (IEN | PTU | DIS | M3)) /*HSUSB2_DA7*/\
- MUX_VAL(CP(MCSPI2_SIMO), (IEN | PTU | DIS | M3)) /*HSUSB2_DA4*/\
- MUX_VAL(CP(MCSPI2_SOMI), (IEN | PTU | DIS | M3)) /*HSUSB2_DA5*/\
- MUX_VAL(CP(MCSPI2_CS0), (IEN | PTU | DIS | M3)) /*HSUSB2_DA6*/\
- MUX_VAL(CP(MCSPI2_CS1), (IEN | PTU | DIS | M3)) /*HSUSB2_DA3*/\
- MUX_VAL(CP(ETK_D10_ES2), (IDIS | PTU | DIS | M3)) /*HSUSB2_CLK*/\
- MUX_VAL(CP(ETK_D11_ES2), (IDIS | PTU | DIS | M3)) /*HSUSB2_STP*/\
- MUX_VAL(CP(ETK_D12_ES2), (IEN | PTU | DIS | M3)) /*HSUSB2_DIR*/\
- MUX_VAL(CP(ETK_D13_ES2), (IEN | PTU | DIS | M3)) /*HSUSB2_NXT*/\
- MUX_VAL(CP(ETK_D14_ES2), (IEN | PTU | DIS | M3)) /*HSUSB2_DA0*/\
- MUX_VAL(CP(ETK_D15_ES2), (IEN | PTU | DIS | M3)) /*HSUSB2_DA1*/\
-/* Control and debug */\
- MUX_VAL(CP(SYS_32K), (IEN | PTD | DIS | M0)) /*SYS_32K*/\
- MUX_VAL(CP(SYS_CLKREQ), (IEN | PTD | DIS | M0)) /*SYS_CLKREQ*/\
- MUX_VAL(CP(SYS_NIRQ), (IEN | PTU | EN | M0)) /*SYS_nIRQ*/\
- MUX_VAL(CP(SYS_BOOT0), (IEN | PTD | DIS | M4)) /*GPIO_2*/\
- MUX_VAL(CP(SYS_BOOT1), (IEN | PTD | DIS | M4)) /*GPIO_3*/\
- MUX_VAL(CP(SYS_BOOT2), (IEN | PTD | DIS | M4)) /*MMC1_WP*/\
- MUX_VAL(CP(SYS_BOOT3), (IEN | PTD | DIS | M4)) /*GPIO_5*/\
- MUX_VAL(CP(SYS_BOOT4), (IEN | PTD | DIS | M4)) /*GPIO_6*/\
- MUX_VAL(CP(SYS_BOOT5), (IEN | PTD | DIS | M4)) /*GPIO_7*/\
- MUX_VAL(CP(SYS_BOOT6), (IDIS | PTD | DIS | M4)) /*GPIO_8*/\
- MUX_VAL(CP(SYS_OFF_MODE), (IEN | PTD | DIS | M0)) /*SYS_OFF_MD*/\
- MUX_VAL(CP(SYS_CLKOUT1), (IEN | PTD | DIS | M0)) /*SYS_CLKOUT*/\
- MUX_VAL(CP(SYS_CLKOUT2), (IEN | PTU | EN | M4)) /*GPIO_186*/\
- MUX_VAL(CP(ETK_CLK_ES2), (IDIS | PTU | EN | M3)) /*HSUSB1_STP*/\
- MUX_VAL(CP(ETK_CTL_ES2), (IDIS | PTU | DIS | M3)) /*HSUSB1_CLK*/\
- MUX_VAL(CP(ETK_D0_ES2), (IEN | PTU | DIS | M3)) /*HSUSB1_DA0*/\
- MUX_VAL(CP(ETK_D1_ES2), (IEN | PTU | DIS | M3)) /*HSUSB1_DA1*/\
- MUX_VAL(CP(ETK_D2_ES2), (IEN | PTU | DIS | M3)) /*HSUSB1_DA2*/\
- MUX_VAL(CP(ETK_D3_ES2), (IEN | PTU | DIS | M3)) /*HSUSB1_DA7*/\
- MUX_VAL(CP(ETK_D4_ES2), (IEN | PTU | DIS | M3)) /*HSUSB1_DA4*/\
- MUX_VAL(CP(ETK_D5_ES2), (IEN | PTU | DIS | M3)) /*HSUSB1_DA5*/\
- MUX_VAL(CP(ETK_D6_ES2), (IEN | PTU | DIS | M3)) /*HSUSB1_DA6*/\
- MUX_VAL(CP(ETK_D7_ES2), (IEN | PTU | DIS | M3)) /*HSUSB1_DA3*/\
- MUX_VAL(CP(ETK_D8_ES2), (IEN | PTU | DIS | M3)) /*HSUSB1_DIR*/\
- MUX_VAL(CP(ETK_D9_ES2), (IEN | PTU | DIS | M3)) /*HSUSB1_NXT*/\
- MUX_VAL(CP(D2D_MCAD1), (IEN | PTD | EN | M0)) /*d2d_mcad1*/\
- MUX_VAL(CP(D2D_MCAD2), (IEN | PTD | EN | M0)) /*d2d_mcad2*/\
- MUX_VAL(CP(D2D_MCAD3), (IEN | PTD | EN | M0)) /*d2d_mcad3*/\
- MUX_VAL(CP(D2D_MCAD4), (IEN | PTD | EN | M0)) /*d2d_mcad4*/\
- MUX_VAL(CP(D2D_MCAD5), (IEN | PTD | EN | M0)) /*d2d_mcad5*/\
- MUX_VAL(CP(D2D_MCAD6), (IEN | PTD | EN | M0)) /*d2d_mcad6*/\
- MUX_VAL(CP(D2D_MCAD7), (IEN | PTD | EN | M0)) /*d2d_mcad7*/\
- MUX_VAL(CP(D2D_MCAD8), (IEN | PTD | EN | M0)) /*d2d_mcad8*/\
- MUX_VAL(CP(D2D_MCAD9), (IEN | PTD | EN | M0)) /*d2d_mcad9*/\
- MUX_VAL(CP(D2D_MCAD10), (IEN | PTD | EN | M0)) /*d2d_mcad10*/\
- MUX_VAL(CP(D2D_MCAD11), (IEN | PTD | EN | M0)) /*d2d_mcad11*/\
- MUX_VAL(CP(D2D_MCAD12), (IEN | PTD | EN | M0)) /*d2d_mcad12*/\
- MUX_VAL(CP(D2D_MCAD13), (IEN | PTD | EN | M0)) /*d2d_mcad13*/\
- MUX_VAL(CP(D2D_MCAD14), (IEN | PTD | EN | M0)) /*d2d_mcad14*/\
- MUX_VAL(CP(D2D_MCAD15), (IEN | PTD | EN | M0)) /*d2d_mcad15*/\
- MUX_VAL(CP(D2D_MCAD16), (IEN | PTD | EN | M0)) /*d2d_mcad16*/\
- MUX_VAL(CP(D2D_MCAD17), (IEN | PTD | EN | M0)) /*d2d_mcad17*/\
- MUX_VAL(CP(D2D_MCAD18), (IEN | PTD | EN | M0)) /*d2d_mcad18*/\
- MUX_VAL(CP(D2D_MCAD19), (IEN | PTD | EN | M0)) /*d2d_mcad19*/\
- MUX_VAL(CP(D2D_MCAD20), (IEN | PTD | EN | M0)) /*d2d_mcad20*/\
- MUX_VAL(CP(D2D_MCAD21), (IEN | PTD | EN | M0)) /*d2d_mcad21*/\
- MUX_VAL(CP(D2D_MCAD22), (IEN | PTD | EN | M0)) /*d2d_mcad22*/\
- MUX_VAL(CP(D2D_MCAD23), (IEN | PTD | EN | M0)) /*d2d_mcad23*/\
- MUX_VAL(CP(D2D_MCAD24), (IEN | PTD | EN | M0)) /*d2d_mcad24*/\
- MUX_VAL(CP(D2D_MCAD25), (IEN | PTD | EN | M0)) /*d2d_mcad25*/\
- MUX_VAL(CP(D2D_MCAD26), (IEN | PTD | EN | M0)) /*d2d_mcad26*/\
- MUX_VAL(CP(D2D_MCAD27), (IEN | PTD | EN | M0)) /*d2d_mcad27*/\
- MUX_VAL(CP(D2D_MCAD28), (IEN | PTD | EN | M0)) /*d2d_mcad28*/\
- MUX_VAL(CP(D2D_MCAD29), (IEN | PTD | EN | M0)) /*d2d_mcad29*/\
- MUX_VAL(CP(D2D_MCAD30), (IEN | PTD | EN | M0)) /*d2d_mcad30*/\
- MUX_VAL(CP(D2D_MCAD31), (IEN | PTD | EN | M0)) /*d2d_mcad31*/\
- MUX_VAL(CP(D2D_MCAD32), (IEN | PTD | EN | M0)) /*d2d_mcad32*/\
- MUX_VAL(CP(D2D_MCAD33), (IEN | PTD | EN | M0)) /*d2d_mcad33*/\
- MUX_VAL(CP(D2D_MCAD34), (IEN | PTD | EN | M0)) /*d2d_mcad34*/\
- MUX_VAL(CP(D2D_MCAD35), (IEN | PTD | EN | M0)) /*d2d_mcad35*/\
- MUX_VAL(CP(D2D_MCAD36), (IEN | PTD | EN | M0)) /*d2d_mcad36*/\
- MUX_VAL(CP(D2D_CLK26MI), (IEN | PTD | DIS | M0)) /*d2d_clk26m*/\
- MUX_VAL(CP(D2D_NRESPWRON), (IEN | PTD | EN | M0)) /*d2d_nrespw*/\
- MUX_VAL(CP(D2D_NRESWARM), (IEN | PTU | EN | M0)) /*d2d_nreswa*/\
- MUX_VAL(CP(D2D_ARM9NIRQ), (IEN | PTD | DIS | M0)) /*d2d_arm9ni*/\
- MUX_VAL(CP(D2D_UMA2P6FIQ), (IEN | PTD | DIS | M0)) /*d2d_uma2p6*/\
- MUX_VAL(CP(D2D_SPINT), (IEN | PTD | EN | M0)) /*d2d_spint*/\
- MUX_VAL(CP(D2D_FRINT), (IEN | PTD | EN | M0)) /*d2d_frint*/\
- MUX_VAL(CP(D2D_DMAREQ0), (IEN | PTD | DIS | M0)) /*d2d_dmare0*/\
- MUX_VAL(CP(D2D_DMAREQ1), (IEN | PTD | DIS | M0)) /*d2d_dmare1*/\
- MUX_VAL(CP(D2D_DMAREQ2), (IEN | PTD | DIS | M0)) /*d2d_dmare2*/\
- MUX_VAL(CP(D2D_DMAREQ3), (IEN | PTD | DIS | M0)) /*d2d_dmare3*/\
- MUX_VAL(CP(D2D_N3GTRST), (IEN | PTD | DIS | M0)) /*d2d_n3gtrs*/\
- MUX_VAL(CP(D2D_N3GTDI), (IEN | PTD | DIS | M0)) /*d2d_n3gtdi*/\
- MUX_VAL(CP(D2D_N3GTDO), (IEN | PTD | DIS | M0)) /*d2d_n3gtdo*/\
- MUX_VAL(CP(D2D_N3GTMS), (IEN | PTD | DIS | M0)) /*d2d_n3gtms*/\
- MUX_VAL(CP(D2D_N3GTCK), (IEN | PTD | DIS | M0)) /*d2d_n3gtck*/\
- MUX_VAL(CP(D2D_N3GRTCK), (IEN | PTD | DIS | M0)) /*d2d_n3grtc*/\
- MUX_VAL(CP(D2D_MSTDBY), (IEN | PTU | EN | M0)) /*d2d_mstdby*/\
- MUX_VAL(CP(D2D_SWAKEUP), (IEN | PTD | EN | M0)) /*d2d_swakeu*/\
- MUX_VAL(CP(D2D_IDLEREQ), (IEN | PTD | DIS | M0)) /*d2d_idlere*/\
- MUX_VAL(CP(D2D_IDLEACK), (IEN | PTU | EN | M0)) /*d2d_idleac*/\
- MUX_VAL(CP(D2D_MWRITE), (IEN | PTD | DIS | M0)) /*d2d_mwrite*/\
- MUX_VAL(CP(D2D_SWRITE), (IEN | PTD | DIS | M0)) /*d2d_swrite*/\
- MUX_VAL(CP(D2D_MREAD), (IEN | PTD | DIS | M0)) /*d2d_mread*/\
- MUX_VAL(CP(D2D_SREAD), (IEN | PTD | DIS | M0)) /*d2d_sread*/\
- MUX_VAL(CP(D2D_MBUSFLAG), (IEN | PTD | DIS | M0)) /*d2d_mbusfl*/\
- MUX_VAL(CP(D2D_SBUSFLAG), (IEN | PTD | DIS | M0)) /*d2d_sbusfl*/\
- MUX_VAL(CP(SDRC_CKE0), (IDIS | PTU | EN | M0)) /*sdrc_cke0*/\
- MUX_VAL(CP(SDRC_CKE1), (IDIS | PTU | EN | M0)) /*sdrc_cke1*/
-
-#define MUX_RX51_C() \
- MUX_VAL(CP(MCBSP3_DX), (IEN | PTD | DIS | M4)) /*GPIO_140*/\
- MUX_VAL(CP(MCBSP3_DR), (IEN | PTD | DIS | M4)) /*GPIO_142*/\
- MUX_VAL(CP(MCBSP3_CLKX), (IEN | PTD | DIS | M4)) /*GPIO_141*/\
- MUX_VAL(CP(UART2_CTS), (IEN | PTU | EN | M0)) /*UART2_CTS*/\
- MUX_VAL(CP(UART2_RTS), (IDIS | PTD | DIS | M0)) /*UART2_RTS*/\
- MUX_VAL(CP(UART2_TX), (IDIS | PTD | DIS | M0)) /*UART2_TX*/
-
-#define ONENAND_GPMC_CONFIG1_RX51 0xfb001202
-#define ONENAND_GPMC_CONFIG2_RX51 0x00111100
-#define ONENAND_GPMC_CONFIG3_RX51 0x00020200
-#define ONENAND_GPMC_CONFIG4_RX51 0x11001102
-#define ONENAND_GPMC_CONFIG5_RX51 0x03101616
-#define ONENAND_GPMC_CONFIG6_RX51 0x90060000
-
-#endif
diff --git a/board/samsung/common/misc.c b/board/samsung/common/misc.c
index d48ba7e..b3b1bbc 100644
--- a/board/samsung/common/misc.c
+++ b/board/samsung/common/misc.c
@@ -117,32 +117,33 @@
#ifdef CONFIG_LCD_MENU
static int power_key_pressed(u32 reg)
{
-#if !CONFIG_IS_ENABLED(DM_I2C) /* TODO(maintainer): Convert to driver model */
- struct pmic *pmic;
+ struct udevice *dev;
+ int ret;
u32 status;
u32 mask;
- pmic = pmic_get(KEY_PWR_PMIC_NAME);
- if (!pmic) {
- printf("%s: Not found\n", KEY_PWR_PMIC_NAME);
+ if (IS_ENABLED(CONFIG_TARGET_TRATS))
+ ret = pmic_get("max8997-pmic", &dev);
+ else if (IS_ENABLED(CONFIG_TARGET_TRATS2))
+ ret = pmic_get("max77686-pmic", &dev);
+ else if (IS_ENABLED(CONFIG_TARGET_S5PC210_UNIVERSAL))
+ ret = pmic_get("max8998-pmic", &dev);
+ else
return 0;
- }
- if (pmic_probe(pmic))
- return 0;
+ if (ret)
+ return ret;
if (reg == KEY_PWR_STATUS_REG)
mask = KEY_PWR_STATUS_MASK;
else
mask = KEY_PWR_INTERRUPT_MASK;
- if (pmic_reg_read(pmic, reg, &status))
- return 0;
+ status = pmic_reg_read(dev, reg);
+ if (status < 0)
+ return status;
return !!(status & mask);
-#else
- return 0;
-#endif
}
static int key_pressed(int key)
diff --git a/board/samsung/espresso7420/MAINTAINERS b/board/samsung/espresso7420/MAINTAINERS
index e3b2394..9145ad4 100644
--- a/board/samsung/espresso7420/MAINTAINERS
+++ b/board/samsung/espresso7420/MAINTAINERS
@@ -1,5 +1,5 @@
ESPRESSO7420 Board
-M: Thomas Abraham <thomas.ab@samsung.com>
+M: Minkyu Kang <mk7.kang@samsung.com>
S: Maintained
F: board/samsung/espresso7420/
F: include/configs/espresso7420.h
diff --git a/board/samsung/goni/MAINTAINERS b/board/samsung/goni/MAINTAINERS
index 248ec3c..7643f9c 100644
--- a/board/samsung/goni/MAINTAINERS
+++ b/board/samsung/goni/MAINTAINERS
@@ -1,5 +1,5 @@
GONI BOARD
-M: Robert Baldyga <r.baldyga@samsung.com>
+M: Jaehoon Chung <jh80.chung@samsung.com>
S: Maintained
F: board/samsung/goni/
F: include/configs/s5p_goni.h
diff --git a/board/samsung/origen/MAINTAINERS b/board/samsung/origen/MAINTAINERS
index 8bf373e..8fb8f81 100644
--- a/board/samsung/origen/MAINTAINERS
+++ b/board/samsung/origen/MAINTAINERS
@@ -1,5 +1,5 @@
ORIGEN BOARD
-M: Chander Kashyap <k.chander@samsung.com>
+M: Minkyu Kang <mk7.kang@samsung.com>
S: Maintained
F: board/samsung/origen/
F: include/configs/origen.h
diff --git a/board/samsung/smdk5250/MAINTAINERS b/board/samsung/smdk5250/MAINTAINERS
index cde966f..c60b6f8 100644
--- a/board/samsung/smdk5250/MAINTAINERS
+++ b/board/samsung/smdk5250/MAINTAINERS
@@ -1,12 +1,12 @@
SMDK5250 BOARD
-M: Chander Kashyap <k.chander@samsung.com>
+M: Jaehoon Chung <jh80.chung@samsung.com>
S: Maintained
F: board/samsung/smdk5250/
F: include/configs/smdk5250.h
F: configs/smdk5250_defconfig
SNOW BOARD
-M: Akshay Saraswat <akshay.s@samsung.com>
+M: Jaehoon Chung <jh80.chung@samsung.com>
S: Maintained
F: include/configs/snow.h
F: configs/snow_defconfig
diff --git a/board/samsung/smdk5420/MAINTAINERS b/board/samsung/smdk5420/MAINTAINERS
index 31c0036..217ff71 100644
--- a/board/samsung/smdk5420/MAINTAINERS
+++ b/board/samsung/smdk5420/MAINTAINERS
@@ -1,5 +1,5 @@
SMDK5420 BOARD
-M: Akshay Saraswat <akshay.s@samsung.com>
+M: Jaehoon Chung <jh80.chung@samsung.com>
S: Maintained
F: board/samsung/smdk5420/
F: include/configs/peach-pit.h
diff --git a/board/samsung/smdkv310/MAINTAINERS b/board/samsung/smdkv310/MAINTAINERS
index 1e058cb..4fa1531 100644
--- a/board/samsung/smdkv310/MAINTAINERS
+++ b/board/samsung/smdkv310/MAINTAINERS
@@ -1,5 +1,5 @@
SMDKV310 BOARD
-M: Chander Kashyap <k.chander@samsung.com>
+M: Jaehoon Chung <jh80.chung@samsung.com>
S: Maintained
F: board/samsung/smdkv310/
F: include/configs/smdkv310.h
diff --git a/board/sks-kinkel/sksimx6/Kconfig b/board/sks-kinkel/sksimx6/Kconfig
deleted file mode 100644
index 3efdf9d..0000000
--- a/board/sks-kinkel/sksimx6/Kconfig
+++ /dev/null
@@ -1,11 +0,0 @@
-if TARGET_SKSIMX6
-
-config SYS_BOARD
- default "sksimx6"
-
-config SYS_VENDOR
- default "sks-kinkel"
-
-config SYS_CONFIG_NAME
- default "sksimx6"
-endif
diff --git a/board/sks-kinkel/sksimx6/MAINTAINERS b/board/sks-kinkel/sksimx6/MAINTAINERS
deleted file mode 100644
index c1527bf..0000000
--- a/board/sks-kinkel/sksimx6/MAINTAINERS
+++ /dev/null
@@ -1,6 +0,0 @@
-SKS-Kinkel sksimx6
-M: Stefano Babic <sbabic@denx.de>
-S: Maintained
-F: board/sks-kinkel/sksimx6/
-F: include/configs/sksimx6.h
-F: configs/sksimx6_defconfig
diff --git a/board/sks-kinkel/sksimx6/Makefile b/board/sks-kinkel/sksimx6/Makefile
deleted file mode 100644
index 1828fad..0000000
--- a/board/sks-kinkel/sksimx6/Makefile
+++ /dev/null
@@ -1,2 +0,0 @@
-#
-obj-y := sksimx6.o
diff --git a/board/sks-kinkel/sksimx6/sksimx6.c b/board/sks-kinkel/sksimx6/sksimx6.c
deleted file mode 100644
index cec3ade..0000000
--- a/board/sks-kinkel/sksimx6/sksimx6.c
+++ /dev/null
@@ -1,431 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * Copyright (C) 2016 Stefano Babic <sbabic@denx.de>
- */
-
-#include <common.h>
-#include <command.h>
-#include <init.h>
-#include <net.h>
-#include <asm/arch/clock.h>
-#include <asm/arch/imx-regs.h>
-#include <asm/arch/iomux.h>
-#include <asm/arch/mx6-pins.h>
-#include <asm/global_data.h>
-#include <linux/delay.h>
-#include <linux/errno.h>
-#include <asm/gpio.h>
-#include <asm/mach-imx/iomux-v3.h>
-#include <asm/mach-imx/video.h>
-#include <mmc.h>
-#include <fsl_esdhc_imx.h>
-#include <asm/arch/crm_regs.h>
-#include <asm/io.h>
-#include <asm/arch/sys_proto.h>
-#include <spl.h>
-#include <netdev.h>
-#include <miiphy.h>
-#include <micrel.h>
-
-#include <common.h>
-#include <malloc.h>
-#include <fuse.h>
-
-DECLARE_GLOBAL_DATA_PTR;
-
-#define UART_PAD_CTRL (PAD_CTL_PUS_100K_UP | \
- PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | \
- PAD_CTL_SRE_FAST | PAD_CTL_HYS)
-
-#define USDHC_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \
- PAD_CTL_PUS_22K_UP | PAD_CTL_SPEED_LOW | \
- PAD_CTL_DSE_80ohm | PAD_CTL_SRE_FAST | PAD_CTL_HYS)
-
-#define I2C_PAD_CTRL (PAD_CTL_PUS_100K_UP | \
- PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | PAD_CTL_HYS | \
- PAD_CTL_ODE | PAD_CTL_SRE_FAST)
-
-#define ENET_PAD_CTRL (PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \
- PAD_CTL_DSE_40ohm | PAD_CTL_HYS)
-
-static iomux_v3_cfg_t const uart1_pads[] = {
- IOMUX_PADS(PAD_CSI0_DAT10__UART1_TX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL)),
- IOMUX_PADS(PAD_CSI0_DAT11__UART1_RX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL)),
-};
-
-static iomux_v3_cfg_t const gpios_pads[] = {
- IOMUX_PADS(PAD_EIM_A24__GPIO5_IO04 | MUX_PAD_CTRL(NO_PAD_CTRL)),
-};
-
-static iomux_v3_cfg_t const usdhc2_pads[] = {
- IOMUX_PADS(PAD_SD2_CLK__SD2_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
- IOMUX_PADS(PAD_SD2_CMD__SD2_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
- IOMUX_PADS(PAD_SD2_DAT0__SD2_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
- IOMUX_PADS(PAD_SD2_DAT1__SD2_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
- IOMUX_PADS(PAD_SD2_DAT2__SD2_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
- IOMUX_PADS(PAD_SD2_DAT3__SD2_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
- IOMUX_PADS(PAD_NANDF_D0__GPIO2_IO00 | MUX_PAD_CTRL(NO_PAD_CTRL)),/* CD */
-};
-
-static iomux_v3_cfg_t const enet_pads[] = {
- IOMUX_PADS(PAD_ENET_MDIO__ENET_MDIO | MUX_PAD_CTRL(ENET_PAD_CTRL)),
- IOMUX_PADS(PAD_ENET_MDC__ENET_MDC | MUX_PAD_CTRL(ENET_PAD_CTRL)),
- IOMUX_PADS(PAD_RGMII_TXC__RGMII_TXC | MUX_PAD_CTRL(ENET_PAD_CTRL)),
- IOMUX_PADS(PAD_RGMII_TD0__RGMII_TD0 | MUX_PAD_CTRL(ENET_PAD_CTRL)),
- IOMUX_PADS(PAD_RGMII_TD1__RGMII_TD1 | MUX_PAD_CTRL(ENET_PAD_CTRL)),
- IOMUX_PADS(PAD_RGMII_TD2__RGMII_TD2 | MUX_PAD_CTRL(ENET_PAD_CTRL)),
- IOMUX_PADS(PAD_RGMII_TD3__RGMII_TD3 | MUX_PAD_CTRL(ENET_PAD_CTRL)),
- IOMUX_PADS(PAD_RGMII_RXC__RGMII_RXC | MUX_PAD_CTRL(ENET_PAD_CTRL)),
- IOMUX_PADS(PAD_RGMII_RD0__RGMII_RD0 | MUX_PAD_CTRL(ENET_PAD_CTRL)),
- IOMUX_PADS(PAD_RGMII_RD1__RGMII_RD1 | MUX_PAD_CTRL(ENET_PAD_CTRL)),
- IOMUX_PADS(PAD_RGMII_RD2__RGMII_RD2 | MUX_PAD_CTRL(ENET_PAD_CTRL)),
- IOMUX_PADS(PAD_RGMII_RD3__RGMII_RD3 | MUX_PAD_CTRL(ENET_PAD_CTRL)),
- IOMUX_PADS(PAD_ENET_REF_CLK__ENET_TX_CLK |
- MUX_PAD_CTRL(ENET_PAD_CTRL)),
- IOMUX_PADS(PAD_RGMII_TX_CTL__RGMII_TX_CTL |
- MUX_PAD_CTRL(ENET_PAD_CTRL)),
- IOMUX_PADS(PAD_RGMII_RX_CTL__RGMII_RX_CTL |
- MUX_PAD_CTRL(ENET_PAD_CTRL)),
- IOMUX_PADS(PAD_ENET_CRS_DV__GPIO1_IO25 | MUX_PAD_CTRL(NO_PAD_CTRL)),
-};
-
-iomux_v3_cfg_t const enet_pads1[] = {
- /* pin 35 - 1 (PHY_AD2) on reset */
- IOMUX_PADS(PAD_RGMII_RXC__GPIO6_IO30 | MUX_PAD_CTRL(NO_PAD_CTRL)),
- /* pin 32 - 1 - (MODE0) all */
- IOMUX_PADS(PAD_RGMII_RD0__GPIO6_IO25 | MUX_PAD_CTRL(NO_PAD_CTRL)),
- /* pin 31 - 1 - (MODE1) all */
- IOMUX_PADS(PAD_RGMII_RD1__GPIO6_IO27 | MUX_PAD_CTRL(NO_PAD_CTRL)),
- /* pin 28 - 1 - (MODE2) all */
- IOMUX_PADS(PAD_RGMII_RD2__GPIO6_IO28 | MUX_PAD_CTRL(NO_PAD_CTRL)),
- /* pin 27 - 1 - (MODE3) all */
- IOMUX_PADS(PAD_RGMII_RD3__GPIO6_IO29 | MUX_PAD_CTRL(NO_PAD_CTRL)),
- /* pin 33 - 1 - (CLK125_EN) 125Mhz clockout enabled */
- IOMUX_PADS(PAD_RGMII_RX_CTL__GPIO6_IO24 | MUX_PAD_CTRL(NO_PAD_CTRL)),
- /* pin 42 PHY nRST */
- IOMUX_PADS(PAD_ENET_CRS_DV__GPIO1_IO25 | MUX_PAD_CTRL(NO_PAD_CTRL)),
-};
-
-static int mx6_rgmii_rework(struct phy_device *phydev)
-{
-
- /* min rx data delay */
- ksz9021_phy_extended_write(phydev, MII_KSZ9021_EXT_RGMII_RX_DATA_SKEW,
- 0x0);
- /* min tx data delay */
- ksz9021_phy_extended_write(phydev, MII_KSZ9021_EXT_RGMII_TX_DATA_SKEW,
- 0x0);
- /* max rx/tx clock delay, min rx/tx control */
- ksz9021_phy_extended_write(phydev, MII_KSZ9021_EXT_RGMII_CLOCK_SKEW,
- 0xf0f0);
-
- return 0;
-}
-
-int board_phy_config(struct phy_device *phydev)
-{
- mx6_rgmii_rework(phydev);
-
- if (phydev->drv->config)
- return phydev->drv->config(phydev);
-
- return 0;
-}
-
-#define ENET_NRST IMX_GPIO_NR(1, 25)
-
-void setup_iomux_enet(void)
-{
- SETUP_IOMUX_PADS(enet_pads);
-
-}
-
-int board_eth_init(struct bd_info *bis)
-{
- uint32_t base = IMX_FEC_BASE;
- struct mii_dev *bus = NULL;
- struct phy_device *phydev = NULL;
- int ret;
-
- setup_iomux_enet();
-
- bus = fec_get_miibus(base, -1);
- if (!bus)
- return -EINVAL;
- /* scan phy */
- phydev = phy_find_by_mask(bus, (0xf << CONFIG_FEC_MXC_PHYADDR),
- PHY_INTERFACE_MODE_RGMII);
-
- if (!phydev) {
- ret = -EINVAL;
- goto free_bus;
- }
- ret = fec_probe(bis, -1, base, bus, phydev);
- if (ret)
- goto free_phydev;
-
- return 0;
-
-free_phydev:
- free(phydev);
-free_bus:
- free(bus);
- return ret;
-}
-
-int board_early_init_f(void)
-{
- SETUP_IOMUX_PADS(uart1_pads);
-
- return 0;
-}
-
-int board_init(void)
-{
- /* Address of boot parameters */
- gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
-
- /* Take in reset the ATMega processor */
- SETUP_IOMUX_PADS(gpios_pads);
- gpio_direction_output(IMX_GPIO_NR(5, 4), 0);
-
- return 0;
-}
-
-int dram_init(void)
-{
- gd->ram_size = imx_ddr_size();
-
- return 0;
-}
-
-struct fsl_esdhc_cfg usdhc_cfg[1] = {
- {USDHC2_BASE_ADDR, 0},
-};
-
-#define USDHC2_CD_GPIO IMX_GPIO_NR(2, 0)
-int board_mmc_getcd(struct mmc *mmc)
-{
- struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv;
- int ret = 0;
-
- if (cfg->esdhc_base == USDHC2_BASE_ADDR)
- ret = 1;
-
- return ret;
-}
-
-int board_mmc_init(struct bd_info *bis)
-{
- int ret;
-
- SETUP_IOMUX_PADS(usdhc2_pads);
- gpio_direction_input(USDHC2_CD_GPIO);
- usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK);
- usdhc_cfg[0].max_bus_width = 4;
-
- ret = fsl_esdhc_initialize(bis, &usdhc_cfg[0]);
- if (ret) {
- printf("Warning: failed to initialize mmc dev \n");
- return ret;
- }
-
- return 0;
-}
-
-#if defined(CONFIG_SPL_BUILD)
-#include <asm/arch/mx6-ddr.h>
-
-/*
- * Driving strength:
- * 0x30 == 40 Ohm
- * 0x28 == 48 Ohm
- */
-#define IMX6SDL_DRIVE_STRENGTH 0x230
-
-
-/* configure MX6SOLO/DUALLITE mmdc DDR io registers */
-struct mx6sdl_iomux_ddr_regs mx6sdl_ddr_ioregs = {
- .dram_sdclk_0 = IMX6SDL_DRIVE_STRENGTH,
- .dram_sdclk_1 = IMX6SDL_DRIVE_STRENGTH,
- .dram_cas = IMX6SDL_DRIVE_STRENGTH,
- .dram_ras = IMX6SDL_DRIVE_STRENGTH,
- .dram_reset = IMX6SDL_DRIVE_STRENGTH,
- .dram_sdcke0 = IMX6SDL_DRIVE_STRENGTH,
- .dram_sdcke1 = IMX6SDL_DRIVE_STRENGTH,
- .dram_sdba2 = 0x00000000,
- .dram_sdodt0 = IMX6SDL_DRIVE_STRENGTH,
- .dram_sdodt1 = IMX6SDL_DRIVE_STRENGTH,
- .dram_sdqs0 = IMX6SDL_DRIVE_STRENGTH,
- .dram_sdqs1 = IMX6SDL_DRIVE_STRENGTH,
- .dram_sdqs2 = IMX6SDL_DRIVE_STRENGTH,
- .dram_sdqs3 = IMX6SDL_DRIVE_STRENGTH,
- .dram_sdqs4 = IMX6SDL_DRIVE_STRENGTH,
- .dram_sdqs5 = IMX6SDL_DRIVE_STRENGTH,
- .dram_sdqs6 = IMX6SDL_DRIVE_STRENGTH,
- .dram_sdqs7 = IMX6SDL_DRIVE_STRENGTH,
- .dram_dqm0 = IMX6SDL_DRIVE_STRENGTH,
- .dram_dqm1 = IMX6SDL_DRIVE_STRENGTH,
- .dram_dqm2 = IMX6SDL_DRIVE_STRENGTH,
- .dram_dqm3 = IMX6SDL_DRIVE_STRENGTH,
- .dram_dqm4 = IMX6SDL_DRIVE_STRENGTH,
- .dram_dqm5 = IMX6SDL_DRIVE_STRENGTH,
- .dram_dqm6 = IMX6SDL_DRIVE_STRENGTH,
- .dram_dqm7 = IMX6SDL_DRIVE_STRENGTH,
-};
-
-/* configure MX6SOLO/DUALLITE mmdc GRP io registers */
-struct mx6sdl_iomux_grp_regs mx6sdl_grp_ioregs = {
- .grp_ddr_type = 0x000c0000,
- .grp_ddrmode_ctl = 0x00020000,
- .grp_ddrpke = 0x00000000,
- .grp_addds = IMX6SDL_DRIVE_STRENGTH,
- .grp_ctlds = IMX6SDL_DRIVE_STRENGTH,
- .grp_ddrmode = 0x00020000,
- .grp_b0ds = IMX6SDL_DRIVE_STRENGTH,
- .grp_b1ds = IMX6SDL_DRIVE_STRENGTH,
- .grp_b2ds = IMX6SDL_DRIVE_STRENGTH,
- .grp_b3ds = IMX6SDL_DRIVE_STRENGTH,
- .grp_b4ds = IMX6SDL_DRIVE_STRENGTH,
- .grp_b5ds = IMX6SDL_DRIVE_STRENGTH,
- .grp_b6ds = IMX6SDL_DRIVE_STRENGTH,
- .grp_b7ds = IMX6SDL_DRIVE_STRENGTH,
-};
-
-/* MT41K128M16JT-125 */
-static struct mx6_ddr3_cfg mt41k128m16jt_125 = {
- /* quad = 1066, duallite = 800 */
- .mem_speed = 1066,
- .density = 2,
- .width = 16,
- .banks = 8,
- .rowaddr = 14,
- .coladdr = 10,
- .pagesz = 2,
- .trcd = 1375,
- .trcmin = 4875,
- .trasmin = 3500,
- .SRT = 0,
-};
-
-static struct mx6_mmdc_calibration mx6dl_1g_mmdc_calib = {
- .p0_mpwldectrl0 = 0x0043004E,
- .p0_mpwldectrl1 = 0x003D003F,
- .p1_mpwldectrl0 = 0x00230021,
- .p1_mpwldectrl1 = 0x0028003E,
- .p0_mpdgctrl0 = 0x42580250,
- .p0_mpdgctrl1 = 0x0238023C,
- .p1_mpdgctrl0 = 0x422C0238,
- .p1_mpdgctrl1 = 0x02180228,
- .p0_mprddlctl = 0x44464A46,
- .p1_mprddlctl = 0x44464A42,
- .p0_mpwrdlctl = 0x36343236,
- .p1_mpwrdlctl = 0x36343230,
-};
-
-/* DDR 64bit 1GB */
-static struct mx6_ddr_sysinfo mem_qdl = {
- .dsize = 2,
- .cs1_mirror = 0,
- /* config for full 4GB range so that get_mem_size() works */
- .cs_density = 32,
- .ncs = 1,
- .bi_on = 1,
- .rtt_nom = 1,
- .rtt_wr = 1,
- .ralat = 5,
- .walat = 0,
- .mif3_mode = 3,
- .rst_to_cke = 0x23,
- .sde_to_rst = 0x10,
- .refsel = 1, /* Refresh cycles at 32KHz */
- .refr = 7, /* 8 refresh commands per refresh cycle */
-};
-
-static void ccgr_init(void)
-{
- struct mxc_ccm_reg *ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
-
- /* set the default clock gate to save power */
- writel(0x00C03F3F, &ccm->CCGR0);
- writel(0x0030FC03, &ccm->CCGR1);
- writel(0x0FFFC000, &ccm->CCGR2);
- writel(0x3FF00000, &ccm->CCGR3);
- writel(0x00FFF300, &ccm->CCGR4);
- writel(0xFFFFFFFF, &ccm->CCGR5);
- writel(0x000003FF, &ccm->CCGR6);
-}
-
-static void spl_dram_init(void)
-{
- if (is_cpu_type(MXC_CPU_MX6DL)) {
- mt41k128m16jt_125.mem_speed = 800;
- mem_qdl.rtt_nom = 1;
- mem_qdl.rtt_wr = 1;
-
- mx6sdl_dram_iocfg(64, &mx6sdl_ddr_ioregs, &mx6sdl_grp_ioregs);
- mx6_dram_cfg(&mem_qdl, &mx6dl_1g_mmdc_calib, &mt41k128m16jt_125);
- } else {
- printf("Wrong CPU for this board\n");
- return;
- }
-
- udelay(100);
-
-#ifdef CONFIG_MX6_DDRCAL
-
- /* Perform DDR DRAM calibration */
- mmdc_do_write_level_calibration(&mem_qdl);
- mmdc_do_dqs_calibration(&mem_qdl);
-#endif
-}
-
-static void check_bootcfg(void)
-{
- u32 val5, val6;
-
- fuse_sense(0, 5, &val5);
- fuse_sense(0, 6, &val6);
- /* Check if boot from MMC */
- if (val6 & 0x10) {
- puts("BT_FUSE_SEL already fused, will do nothing\n");
- return;
- }
- fuse_prog(0, 5, 0x00000840);
- /* BT_FUSE_SEL */
- fuse_prog(0, 6, 0x00000010);
-
- do_reset(NULL, 0, 0, NULL);
-}
-
-void board_init_f(ulong dummy)
-{
- ccgr_init();
-
- /* setup AIPS and disable watchdog */
- arch_cpu_init();
-
- gpr_init();
-
- /* iomux */
- board_early_init_f();
-
- /* setup GP timer */
- timer_init();
-
- /* UART clocks enabled and gd valid - init serial console */
- preloader_console_init();
-
- /* DDR initialization */
- spl_dram_init();
-
- /* Set fuses for new boards and reboot if not set */
- check_bootcfg();
-
- /* Clear the BSS. */
- memset(__bss_start, 0, __bss_end - __bss_start);
-
- /* load/boot image from boot device */
- board_init_r(NULL, 0);
-}
-#endif
diff --git a/board/solidrun/clearfog/clearfog.c b/board/solidrun/clearfog/clearfog.c
index 7b2accf..c920cf8 100644
--- a/board/solidrun/clearfog/clearfog.c
+++ b/board/solidrun/clearfog/clearfog.c
@@ -142,6 +142,7 @@
MV_DDR_TIM_DEFAULT} }, /* timing */
BUS_MASK_32BIT, /* Busses mask */
MV_DDR_CFG_DEFAULT, /* ddr configuration data source */
+ NOT_COMBINED, /* ddr twin-die combined */
{ {0} }, /* raw spd data */
{0}, /* timing parameters */
{ {0} }, /* electrical configuration */
diff --git a/board/st/common/MAINTAINERS b/board/st/common/MAINTAINERS
index c4e0c5f..0c6db54 100644
--- a/board/st/common/MAINTAINERS
+++ b/board/st/common/MAINTAINERS
@@ -1,6 +1,6 @@
ST BOARDS
M: Patrick Delaunay <patrick.delaunay@foss.st.com>
L: uboot-stm32@st-md-mailman.stormreply.com (moderated for non-subscribers)
-T: git https://gitlab.denx.de/u-boot/custodians/u-boot-stm.git
+T: git https://source.denx.de/u-boot/custodians/u-boot-stm.git
S: Maintained
F: board/st/common/
diff --git a/board/st/common/stm32mp_dfu.c b/board/st/common/stm32mp_dfu.c
index 5633a6c..00d1fb8 100644
--- a/board/st/common/stm32mp_dfu.c
+++ b/board/st/common/stm32mp_dfu.c
@@ -143,7 +143,8 @@
board_get_alt_info_mtd(mtd, buf);
}
- if (IS_ENABLED(CONFIG_DFU_VIRT)) {
+ if (IS_ENABLED(CONFIG_DFU_VIRT) &&
+ IS_ENABLED(CMD_STM32PROG_USB)) {
strncat(buf, "&virt 0=OTP", DFU_ALT_BUF_LEN);
if (IS_ENABLED(CONFIG_PMIC_STPMIC1))
@@ -217,7 +218,7 @@
return dfu_pmic_read(offset, buf, len);
}
- if (CONFIG_IS_ENABLED(CMD_STM32PROG) &&
+ if (IS_ENABLED(CONFIG_CMD_STM32PROG_USB) &&
dfu->data.virt.dev_num >= STM32PROG_VIRT_FIRST_DEV_NUM)
return stm32prog_read_medium_virt(dfu, offset, buf, len);
@@ -228,7 +229,7 @@
int dfu_write_medium_virt(struct dfu_entity *dfu, u64 offset,
void *buf, long *len)
{
- if (CONFIG_IS_ENABLED(CMD_STM32PROG) &&
+ if (IS_ENABLED(CONFIG_CMD_STM32PROG_USB) &&
dfu->data.virt.dev_num >= STM32PROG_VIRT_FIRST_DEV_NUM)
return stm32prog_write_medium_virt(dfu, offset, buf, len);
@@ -237,7 +238,7 @@
int __weak dfu_get_medium_size_virt(struct dfu_entity *dfu, u64 *size)
{
- if (CONFIG_IS_ENABLED(CMD_STM32PROG) &&
+ if (IS_ENABLED(CONFIG_CMD_STM32PROG_USB) &&
dfu->data.virt.dev_num >= STM32PROG_VIRT_FIRST_DEV_NUM)
return stm32prog_get_medium_size_virt(dfu, size);
diff --git a/board/st/common/stm32mp_mtdparts.c b/board/st/common/stm32mp_mtdparts.c
index 69eb108..f074fc1 100644
--- a/board/st/common/stm32mp_mtdparts.c
+++ b/board/st/common/stm32mp_mtdparts.c
@@ -122,28 +122,24 @@
log_debug("mtd device = %s\n", dev->name);
}
- if (nor || nand) {
+ if (nand) {
mtd = get_mtd_device_nm("nand0");
if (!IS_ERR_OR_NULL(mtd)) {
- const char *mtd_boot = CONFIG_MTDPARTS_NAND0_BOOT;
const char *mtd_tee = CONFIG_MTDPARTS_NAND0_TEE;
-
board_set_mtdparts("nand0", ids, parts,
- !nor ? mtd_boot : NULL,
+ CONFIG_MTDPARTS_NAND0_BOOT,
!nor && tee ? mtd_tee : NULL,
"-(UBI)");
put_mtd_device(mtd);
}
}
- if (nor || spinand) {
+ if (spinand) {
mtd = get_mtd_device_nm("spi-nand0");
if (!IS_ERR_OR_NULL(mtd)) {
- const char *mtd_boot = CONFIG_MTDPARTS_SPINAND0_BOOT;
const char *mtd_tee = CONFIG_MTDPARTS_SPINAND0_TEE;
-
board_set_mtdparts("spi-nand0", ids, parts,
- !nor ? mtd_boot : NULL,
+ CONFIG_MTDPARTS_SPINAND0_BOOT,
!nor && tee ? mtd_tee : NULL,
"-(UBI)");
put_mtd_device(mtd);
@@ -152,11 +148,9 @@
if (nor) {
if (!uclass_get_device(UCLASS_SPI_FLASH, 0, &dev)) {
- const char *mtd_boot = CONFIG_MTDPARTS_NOR0_BOOT;
const char *mtd_tee = CONFIG_MTDPARTS_NOR0_TEE;
-
board_set_mtdparts("nor0", ids, parts,
- mtd_boot,
+ CONFIG_MTDPARTS_NOR0_BOOT,
tee ? mtd_tee : NULL,
"-(nor_user)");
}
diff --git a/board/st/stm32f429-discovery/stm32f429-discovery.c b/board/st/stm32f429-discovery/stm32f429-discovery.c
index 9d8fc9f..46fcf90 100644
--- a/board/st/stm32f429-discovery/stm32f429-discovery.c
+++ b/board/st/stm32f429-discovery/stm32f429-discovery.c
@@ -51,11 +51,6 @@
return 0;
}
-int board_early_init_f(void)
-{
- return 0;
-}
-
int board_init(void)
{
gd->bd->bi_boot_params = gd->bd->bi_dram[0].start + 0x100;
diff --git a/board/st/stm32f429-evaluation/stm32f429-evaluation.c b/board/st/stm32f429-evaluation/stm32f429-evaluation.c
index 96b4c25..3b6df1f 100644
--- a/board/st/stm32f429-evaluation/stm32f429-evaluation.c
+++ b/board/st/stm32f429-evaluation/stm32f429-evaluation.c
@@ -45,11 +45,6 @@
return 0;
}
-int board_early_init_f(void)
-{
- return 0;
-}
-
int board_init(void)
{
gd->bd->bi_boot_params = gd->bd->bi_dram[0].start + 0x100;
diff --git a/board/st/stm32f469-discovery/stm32f469-discovery.c b/board/st/stm32f469-discovery/stm32f469-discovery.c
index 742fd67..c5df9b0 100644
--- a/board/st/stm32f469-discovery/stm32f469-discovery.c
+++ b/board/st/stm32f469-discovery/stm32f469-discovery.c
@@ -45,11 +45,6 @@
return 0;
}
-int board_early_init_f(void)
-{
- return 0;
-}
-
int board_init(void)
{
gd->bd->bi_boot_params = gd->bd->bi_dram[0].start + 0x100;
diff --git a/board/st/stm32f746-disco/stm32f746-disco.c b/board/st/stm32f746-disco/stm32f746-disco.c
index 40450ca..143cc6e 100644
--- a/board/st/stm32f746-disco/stm32f746-disco.c
+++ b/board/st/stm32f746-disco/stm32f746-disco.c
@@ -48,11 +48,6 @@
return fdtdec_setup_memory_banksize();
}
-int board_early_init_f(void)
-{
- return 0;
-}
-
#ifdef CONFIG_SPL_BUILD
#ifdef CONFIG_SPL_OS_BOOT
int spl_start_uboot(void)
diff --git a/board/st/stm32h743-disco/stm32h743-disco.c b/board/st/stm32h743-disco/stm32h743-disco.c
index 405836a..4091d5f 100644
--- a/board/st/stm32h743-disco/stm32h743-disco.c
+++ b/board/st/stm32h743-disco/stm32h743-disco.c
@@ -36,21 +36,11 @@
return 0;
}
-int board_early_init_f(void)
-{
- return 0;
-}
-
u32 get_board_rev(void)
{
return 0;
}
-int board_late_init(void)
-{
- return 0;
-}
-
int board_init(void)
{
gd->bd->bi_boot_params = gd->bd->bi_dram[0].start + 0x100;
diff --git a/board/st/stm32h743-eval/stm32h743-eval.c b/board/st/stm32h743-eval/stm32h743-eval.c
index 405836a..4091d5f 100644
--- a/board/st/stm32h743-eval/stm32h743-eval.c
+++ b/board/st/stm32h743-eval/stm32h743-eval.c
@@ -36,21 +36,11 @@
return 0;
}
-int board_early_init_f(void)
-{
- return 0;
-}
-
u32 get_board_rev(void)
{
return 0;
}
-int board_late_init(void)
-{
- return 0;
-}
-
int board_init(void)
{
gd->bd->bi_boot_params = gd->bd->bi_dram[0].start + 0x100;
diff --git a/board/st/stm32mp1/MAINTAINERS b/board/st/stm32mp1/MAINTAINERS
index bd5c07d..fe8fc6f 100644
--- a/board/st/stm32mp1/MAINTAINERS
+++ b/board/st/stm32mp1/MAINTAINERS
@@ -1,7 +1,7 @@
STM32MP1 BOARD
M: Patrick Delaunay <patrick.delaunay@foss.st.com>
L: uboot-stm32@st-md-mailman.stormreply.com (moderated for non-subscribers)
-T: git https://gitlab.denx.de/u-boot/custodians/u-boot-stm.git
+T: git https://source.denx.de/u-boot/custodians/u-boot-stm.git
S: Maintained
F: arch/arm/dts/stm32mp15*
F: board/st/stm32mp1/
diff --git a/board/st/stm32mp1/stm32mp1.c b/board/st/stm32mp1/stm32mp1.c
index ab85d8b..759181f 100644
--- a/board/st/stm32mp1/stm32mp1.c
+++ b/board/st/stm32mp1/stm32mp1.c
@@ -862,8 +862,14 @@
int mmc_get_env_dev(void)
{
- u32 bootmode = get_bootmode();
+ u32 bootmode;
+
+ if (CONFIG_SYS_MMC_ENV_DEV >= 0)
+ return CONFIG_SYS_MMC_ENV_DEV;
+
+ bootmode = get_bootmode();
+ /* use boot instance to select the correct mmc device identifier */
return (bootmode & TAMP_BOOT_INSTANCE_MASK) - 1;
}
diff --git a/board/ti/j721e/README b/board/ti/j721e/README
index 757a59c..c33afa4 100644
--- a/board/ti/j721e/README
+++ b/board/ti/j721e/README
@@ -132,7 +132,7 @@
Branch: master
4. U-Boot:
- Tree: https://gitlab.denx.de/u-boot/u-boot
+ Tree: https://source.denx.de/u-boot/u-boot
Branch: master
Build procedure:
diff --git a/board/xilinx/common/board.c b/board/xilinx/common/board.c
index 4a83d93..475628b 100644
--- a/board/xilinx/common/board.c
+++ b/board/xilinx/common/board.c
@@ -327,7 +327,7 @@
if (!IS_ENABLED(CONFIG_SPL_BUILD) &&
!IS_ENABLED(CONFIG_VERSAL_NO_DDR) &&
- !IS_ENABLED(CONFIG_VERSAL_NO_DDR)) {
+ !IS_ENABLED(CONFIG_ZYNQMP_NO_DDR)) {
fdt_blob = (void *)CONFIG_XILINX_OF_BOARD_DTB_ADDR;
if (fdt_magic(fdt_blob) == FDT_MAGIC)
diff --git a/board/xilinx/microblaze-generic/MAINTAINERS b/board/xilinx/microblaze-generic/MAINTAINERS
index 9a42a8b..29ed32f 100644
--- a/board/xilinx/microblaze-generic/MAINTAINERS
+++ b/board/xilinx/microblaze-generic/MAINTAINERS
@@ -1,7 +1,7 @@
MICROBLAZE-GENERIC BOARD
M: Michal Simek <monstr@monstr.eu>
S: Maintained
-T: git https://gitlab.denx.de/u-boot/custodians/u-boot-microblaze.git
+T: git https://source.denx.de/u-boot/custodians/u-boot-microblaze.git
F: board/xilinx/microblaze-generic/
F: include/configs/microblaze-generic.h
F: configs/microblaze-generic_defconfig
diff --git a/board/xilinx/versal/MAINTAINERS b/board/xilinx/versal/MAINTAINERS
index 0d40196..bbab051 100644
--- a/board/xilinx/versal/MAINTAINERS
+++ b/board/xilinx/versal/MAINTAINERS
@@ -1,7 +1,7 @@
XILINX_VERSAL BOARDS
M: Michal Simek <michal.simek@xilinx.com>
S: Maintained
-T: git https://gitlab.denx.de/u-boot/custodians/u-boot-microblaze.git
+T: git https://source.denx.de/u-boot/custodians/u-boot-microblaze.git
F: arch/arm/dts/versal*
F: board/xilinx/versal/
F: include/configs/xilinx_versal*
diff --git a/board/xilinx/zynq/MAINTAINERS b/board/xilinx/zynq/MAINTAINERS
index ce760ab..b5b9e2f 100644
--- a/board/xilinx/zynq/MAINTAINERS
+++ b/board/xilinx/zynq/MAINTAINERS
@@ -1,7 +1,7 @@
ZYNQ BOARD
M: Michal Simek <monstr@monstr.eu>
S: Maintained
-T: git https://gitlab.denx.de/u-boot/custodians/u-boot-microblaze.git
+T: git https://source.denx.de/u-boot/custodians/u-boot-microblaze.git
F: arch/arm/dts/zynq-*
F: board/xilinx/zynq/
F: include/configs/zynq*.h
diff --git a/board/xilinx/zynq/board.c b/board/xilinx/zynq/board.c
index 49ff3f0..7533ddd 100644
--- a/board/xilinx/zynq/board.c
+++ b/board/xilinx/zynq/board.c
@@ -25,6 +25,9 @@
int board_init(void)
{
+ if (IS_ENABLED(CONFIG_SPL_BUILD))
+ printf("Silicon version:\t%d\n", zynq_get_silicon_version());
+
return 0;
}
diff --git a/board/xilinx/zynqmp/MAINTAINERS b/board/xilinx/zynqmp/MAINTAINERS
index a631b38..56c6379 100644
--- a/board/xilinx/zynqmp/MAINTAINERS
+++ b/board/xilinx/zynqmp/MAINTAINERS
@@ -1,7 +1,7 @@
XILINX_ZYNQMP BOARDS
M: Michal Simek <michal.simek@xilinx.com>
S: Maintained
-T: git https://gitlab.denx.de/u-boot/custodians/u-boot-microblaze.git
+T: git https://source.denx.de/u-boot/custodians/u-boot-microblaze.git
F: arch/arm/dts/zynqmp-*
F: arch/arm/dts/avnet-ultra96*
F: board/xilinx/common/
diff --git a/board/xilinx/zynqmp/zynqmp-zc1275-revA b/board/xilinx/zynqmp/zynqmp-zcu1275-revA
similarity index 100%
rename from board/xilinx/zynqmp/zynqmp-zc1275-revA
rename to board/xilinx/zynqmp/zynqmp-zcu1275-revA
diff --git a/board/xilinx/zynqmp/zynqmp-zc1275-revB/psu_init_gpl.c b/board/xilinx/zynqmp/zynqmp-zcu1275-revB/psu_init_gpl.c
similarity index 100%
rename from board/xilinx/zynqmp/zynqmp-zc1275-revB/psu_init_gpl.c
rename to board/xilinx/zynqmp/zynqmp-zcu1275-revB/psu_init_gpl.c
diff --git a/board/xilinx/zynqmp/zynqmp.c b/board/xilinx/zynqmp/zynqmp.c
index 43e322f..4466717 100644
--- a/board/xilinx/zynqmp/zynqmp.c
+++ b/board/xilinx/zynqmp/zynqmp.c
@@ -329,6 +329,7 @@
if (sizeof(CONFIG_ZYNQMP_SPL_PM_CFG_OBJ_FILE) > 1)
zynqmp_pmufw_load_config_object(zynqmp_pm_cfg_obj,
zynqmp_pm_cfg_obj_size);
+ printf("Silicon version:\t%d\n", zynqmp_get_silicon_version());
#else
if (CONFIG_IS_ENABLED(DM_I2C) && CONFIG_IS_ENABLED(I2C_EEPROM))
xilinx_read_eeprom();
@@ -496,11 +497,7 @@
env_set("reset_reason", reason);
- ret = zynqmp_mmio_write((ulong)&crlapb_base->reset_reason, ~0, ~0);
- if (ret)
- return -EINVAL;
-
- return ret;
+ return 0;
}
static int set_fdtfile(void)
diff --git a/cmd/Kconfig b/cmd/Kconfig
index 928a2a0..eff238c 100644
--- a/cmd/Kconfig
+++ b/cmd/Kconfig
@@ -97,6 +97,13 @@
between the firmware and OS, and is particularly useful when you
want to make hardware changes without the OS needing to be adjusted.
+config CMD_ADDRMAP
+ bool "addrmap"
+ depends on ADDR_MAP
+ default y
+ help
+ List non-identity virtual-physical memory mappings for 32-bit CPUs.
+
config CMD_BDI
bool "bdinfo"
default y
@@ -1188,6 +1195,7 @@
config CMD_PINMUX
bool "pinmux - show pins muxing"
+ depends on PINCTRL
default y if PINCTRL
help
Parse all available pin-controllers and show pins muxing. This
@@ -1337,6 +1345,7 @@
config CMD_VIRTIO
bool "virtio"
depends on VIRTIO
+ depends on HAVE_BLOCK_DEVICE
default y if VIRTIO
help
VirtIO block device support
diff --git a/cmd/Makefile b/cmd/Makefile
index 176bf92..567e2b7 100644
--- a/cmd/Makefile
+++ b/cmd/Makefile
@@ -13,6 +13,7 @@
# command
obj-$(CONFIG_CMD_ACPI) += acpi.o
+obj-$(CONFIG_CMD_ADDRMAP) += addrmap.o
obj-$(CONFIG_CMD_AES) += aes.o
obj-$(CONFIG_CMD_AB_SELECT) += ab_select.o
obj-$(CONFIG_CMD_ADC) += adc.o
diff --git a/cmd/ab_select.c b/cmd/ab_select.c
index 6298fcf..3e46663 100644
--- a/cmd/ab_select.c
+++ b/cmd/ab_select.c
@@ -22,7 +22,8 @@
/* Lookup the "misc" partition from argv[2] and argv[3] */
if (part_get_info_by_dev_and_name_or_num(argv[2], argv[3],
- &dev_desc, &part_info) < 0) {
+ &dev_desc, &part_info,
+ false) < 0) {
return CMD_RET_FAILURE;
}
diff --git a/cmd/addrmap.c b/cmd/addrmap.c
new file mode 100644
index 0000000..bd23549
--- /dev/null
+++ b/cmd/addrmap.c
@@ -0,0 +1,35 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2021, Bin Meng <bmeng.cn@gmail.com>
+ */
+
+#include <common.h>
+#include <command.h>
+#include <addr_map.h>
+
+static int do_addrmap(struct cmd_tbl *cmdtp, int flag, int argc,
+ char *const argv[])
+{
+ int i;
+
+ printf(" vaddr paddr size\n");
+ printf("================ ================ ================\n");
+
+ for (i = 0; i < CONFIG_SYS_NUM_ADDR_MAP; i++) {
+ if (address_map[i].size == 0)
+ continue;
+
+ printf("%16.8lx %16.8llx %16.8llx\n",
+ address_map[i].vaddr,
+ (unsigned long long)address_map[i].paddr,
+ (unsigned long long)address_map[i].size);
+ }
+
+ return 0;
+}
+
+U_BOOT_CMD(
+ addrmap, 1, 1, do_addrmap,
+ "List non-identity virtual-physical memory mappings for 32-bit CPUs",
+ ""
+);
diff --git a/cmd/efidebug.c b/cmd/efidebug.c
index bbbcb0a..55c7abe 100644
--- a/cmd/efidebug.c
+++ b/cmd/efidebug.c
@@ -72,7 +72,7 @@
capsule->capsule_image_size);
}
- ret = EFI_CALL(RT->update_capsule(&capsule, 1, (u64)NULL));
+ ret = EFI_CALL(RT->update_capsule(&capsule, 1, 0));
if (ret) {
printf("Cannot handle a capsule at %p", capsule);
return CMD_RET_FAILURE;
@@ -507,6 +507,10 @@
"System Partition",
PARTITION_SYSTEM_GUID
},
+ {
+ "Firmware Management",
+ EFI_FIRMWARE_MANAGEMENT_PROTOCOL_GUID
+ },
/* Configuration table GUIDs */
{
"ACPI table",
diff --git a/cmd/pwm.c b/cmd/pwm.c
index 5849fc5..e1f97c7 100644
--- a/cmd/pwm.c
+++ b/cmd/pwm.c
@@ -34,11 +34,9 @@
argc -= 2;
argv += 2;
- if (argc > 0) {
- str_pwm = *argv;
- argc--;
- argv++;
- }
+ str_pwm = *argv;
+ argc--;
+ argv++;
if (!str_pwm)
return CMD_RET_USAGE;
@@ -46,15 +44,23 @@
switch (*str_cmd) {
case 'i':
sub_cmd = PWM_SET_INVERT;
+ if (argc != 2)
+ return CMD_RET_USAGE;
break;
case 'c':
sub_cmd = PWM_SET_CONFIG;
+ if (argc != 3)
+ return CMD_RET_USAGE;
break;
case 'e':
sub_cmd = PWM_SET_ENABLE;
+ if (argc != 1)
+ return CMD_RET_USAGE;
break;
case 'd':
sub_cmd = PWM_SET_DISABLE;
+ if (argc != 1)
+ return CMD_RET_USAGE;
break;
default:
return CMD_RET_USAGE;
@@ -67,38 +73,29 @@
return cmd_process_error(cmdtp, ret);
}
- if (argc > 0) {
- str_channel = *argv;
- channel = simple_strtoul(str_channel, NULL, 10);
- argc--;
- argv++;
- } else {
- return CMD_RET_USAGE;
- }
+ str_channel = *argv;
+ channel = simple_strtoul(str_channel, NULL, 10);
+ argc--;
+ argv++;
- if (sub_cmd == PWM_SET_INVERT && argc > 0) {
+ if (sub_cmd == PWM_SET_INVERT) {
str_enable = *argv;
pwm_enable = simple_strtoul(str_enable, NULL, 10);
ret = pwm_set_invert(dev, channel, pwm_enable);
- } else if (sub_cmd == PWM_SET_CONFIG && argc == 2) {
+ } else if (sub_cmd == PWM_SET_CONFIG) {
str_period = *argv;
argc--;
argv++;
period_ns = simple_strtoul(str_period, NULL, 10);
- if (argc > 0) {
- str_duty = *argv;
- duty_ns = simple_strtoul(str_duty, NULL, 10);
- }
+ str_duty = *argv;
+ duty_ns = simple_strtoul(str_duty, NULL, 10);
ret = pwm_set_config(dev, channel, period_ns, duty_ns);
} else if (sub_cmd == PWM_SET_ENABLE) {
ret = pwm_set_enable(dev, channel, 1);
} else if (sub_cmd == PWM_SET_DISABLE) {
ret = pwm_set_enable(dev, channel, 0);
- } else {
- printf("PWM arguments missing\n");
- return CMD_RET_FAILURE;
}
if (ret) {
diff --git a/cmd/riscv/sbi.c b/cmd/riscv/sbi.c
index 2c905f1..90c0811 100644
--- a/cmd/riscv/sbi.c
+++ b/cmd/riscv/sbi.c
@@ -43,6 +43,7 @@
{ 0x00735049, "IPI Extension" },
{ 0x52464E43, "RFENCE Extension" },
{ 0x0048534D, "Hart State Management Extension" },
+ { 0x53525354, "System Reset Extension" },
};
static int do_sbi(struct cmd_tbl *cmdtp, int flag, int argc,
diff --git a/cmd/sf.c b/cmd/sf.c
index c0d6a8f..46346fb 100644
--- a/cmd/sf.c
+++ b/cmd/sf.c
@@ -344,8 +344,11 @@
}
ret = spi_flash_erase(flash, offset, size);
- printf("SF: %zu bytes @ %#x Erased: %s\n", (size_t)size, (u32)offset,
- ret ? "ERROR" : "OK");
+ printf("SF: %zu bytes @ %#x Erased: ", (size_t)size, (u32)offset);
+ if (ret)
+ printf("ERROR %d\n", ret);
+ else
+ printf("OK\n");
return ret == 0 ? 0 : 1;
}
@@ -442,20 +445,22 @@
ulong offset, uint8_t *vbuf)
{
struct test_info test;
- int i;
+ int err, i;
printf("SPI flash test:\n");
memset(&test, '\0', sizeof(test));
test.base_ms = get_timer(0);
test.bytes = len;
- if (spi_flash_erase(flash, offset, len)) {
- printf("Erase failed\n");
+ err = spi_flash_erase(flash, offset, len);
+ if (err) {
+ printf("Erase failed (err = %d)\n", err);
return -1;
}
spi_test_next_stage(&test);
- if (spi_flash_read(flash, offset, len, vbuf)) {
- printf("Check read failed\n");
+ err = spi_flash_read(flash, offset, len, vbuf);
+ if (err) {
+ printf("Check read failed (err = %d)\n", err);
return -1;
}
for (i = 0; i < len; i++) {
@@ -468,15 +473,17 @@
}
spi_test_next_stage(&test);
- if (spi_flash_write(flash, offset, len, buf)) {
- printf("Write failed\n");
+ err = spi_flash_write(flash, offset, len, buf);
+ if (err) {
+ printf("Write failed (err = %d)\n", err);
return -1;
}
memset(vbuf, '\0', len);
spi_test_next_stage(&test);
- if (spi_flash_read(flash, offset, len, vbuf)) {
- printf("Read failed\n");
+ err = spi_flash_read(flash, offset, len, vbuf);
+ if (err) {
+ printf("Read failed (ret = %d)\n", err);
return -1;
}
spi_test_next_stage(&test);
diff --git a/common/Kconfig.boot b/common/Kconfig.boot
index 7532e55..9c335f4 100644
--- a/common/Kconfig.boot
+++ b/common/Kconfig.boot
@@ -138,7 +138,7 @@
config FIT_IMAGE_POST_PROCESS
bool "Enable post-processing of FIT artifacts after loading by U-Boot"
- depends on TI_SECURE_DEVICE
+ depends on TI_SECURE_DEVICE || SOCFPGA_SECURE_VAB_AUTH
help
Allows doing any sort of manipulation to blobs after they got extracted
from FIT images like stripping off headers or modifying the size of the
@@ -181,6 +181,8 @@
config SPL_FIT_SIGNATURE
bool "Enable signature verification of FIT firmware within SPL"
depends on SPL_DM
+ depends on SPL_LOAD_FIT || SPL_LOAD_FIT_FULL
+ select FIT_SIGNATURE
select SPL_FIT
select SPL_CRYPTO_SUPPORT
select SPL_HASH_SUPPORT
@@ -447,6 +449,7 @@
config BOOTSTAGE_RECORD_COUNT
int "Number of boot stage records to store"
+ depends on BOOTSTAGE
default 30
help
This is the size of the bootstage record list and is the maximum
@@ -454,6 +457,7 @@
config SPL_BOOTSTAGE_RECORD_COUNT
int "Number of boot stage records to store for SPL"
+ depends on SPL_BOOTSTAGE
default 5
help
This is the size of the bootstage record list and is the maximum
@@ -461,6 +465,7 @@
config TPL_BOOTSTAGE_RECORD_COUNT
int "Number of boot stage records to store for TPL"
+ depends on TPL_BOOTSTAGE
default 5
help
This is the size of the bootstage record list and is the maximum
diff --git a/common/avb_verify.c b/common/avb_verify.c
index db10d0f..0520a71 100644
--- a/common/avb_verify.c
+++ b/common/avb_verify.c
@@ -369,7 +369,7 @@
}
ret = part_get_info_by_name(mmc_blk, partition, &part->info);
- if (!ret) {
+ if (ret < 0) {
printf("Can't find partition '%s'\n", partition);
goto err;
}
diff --git a/common/board_r.c b/common/board_r.c
index 9793439..c835ff8e 100644
--- a/common/board_r.c
+++ b/common/board_r.c
@@ -626,6 +626,9 @@
#ifdef CONFIG_DM
initr_dm,
#endif
+#ifdef CONFIG_ADDR_MAP
+ initr_addr_map,
+#endif
#if defined(CONFIG_ARM) || defined(CONFIG_NDS32) || defined(CONFIG_RISCV) || \
defined(CONFIG_SANDBOX)
board_init, /* Setup chipselects */
@@ -661,9 +664,6 @@
initr_manual_reloc_cmdtable,
#endif
arch_initr_trap,
-#ifdef CONFIG_ADDR_MAP
- initr_addr_map,
-#endif
#if defined(CONFIG_BOARD_EARLY_INIT_R)
board_early_init_r,
#endif
diff --git a/common/bootstage.c b/common/bootstage.c
index d5b78b9..2c0110c 100644
--- a/common/bootstage.c
+++ b/common/bootstage.c
@@ -349,7 +349,7 @@
}
if (data->rec_count > RECORD_COUNT)
printf("Overflowed internal boot id table by %d entries\n"
- "Please increase CONFIG_(SPL_)BOOTSTAGE_RECORD_COUNT\n",
+ "Please increase CONFIG_(SPL_TPL_)BOOTSTAGE_RECORD_COUNT\n",
data->rec_count - RECORD_COUNT);
puts("\nAccumulated time:\n");
diff --git a/common/fdt_support.c b/common/fdt_support.c
index 08d540b..e624bbd 100644
--- a/common/fdt_support.c
+++ b/common/fdt_support.c
@@ -1668,22 +1668,36 @@
}
/*
- * Read a property of size <prop_len>. Currently only supports 1 or 2 cells.
+ * Read a property of size <prop_len>. Currently only supports 1 or 2 cells,
+ * or 3 cells specially for a PCI address.
*/
static int fdt_read_prop(const fdt32_t *prop, int prop_len, int cell_off,
uint64_t *val, int cells)
{
- const fdt32_t *prop32 = &prop[cell_off];
- const unaligned_fdt64_t *prop64 = (const fdt64_t *)&prop[cell_off];
+ const fdt32_t *prop32;
+ const unaligned_fdt64_t *prop64;
if ((cell_off + cells) > prop_len)
return -FDT_ERR_NOSPACE;
+ prop32 = &prop[cell_off];
+
+ /*
+ * Special handling for PCI address in PCI bus <ranges>
+ *
+ * PCI child address is made up of 3 cells. Advance the cell offset
+ * by 1 so that the PCI child address can be correctly read.
+ */
+ if (cells == 3)
+ cell_off += 1;
+ prop64 = (const fdt64_t *)&prop[cell_off];
+
switch (cells) {
case 1:
*val = fdt32_to_cpu(*prop32);
break;
case 2:
+ case 3:
*val = fdt64_to_cpu(*prop64);
break;
default:
diff --git a/common/image-fdt.c b/common/image-fdt.c
index 61ce6e5..a287b66 100644
--- a/common/image-fdt.c
+++ b/common/image-fdt.c
@@ -576,11 +576,18 @@
fdt_fixup_pstore(blob);
#endif
if (IMAGE_OF_BOARD_SETUP) {
- fdt_ret = ft_board_setup(blob, gd->bd);
- if (fdt_ret) {
- printf("ERROR: board-specific fdt fixup failed: %s\n",
- fdt_strerror(fdt_ret));
- goto err;
+ const char *skip_board_fixup;
+
+ skip_board_fixup = env_get("skip_board_fixup");
+ if (skip_board_fixup && ((int)simple_strtol(skip_board_fixup, NULL, 10) == 1)) {
+ printf("skip board fdt fixup\n");
+ } else {
+ fdt_ret = ft_board_setup(blob, gd->bd);
+ if (fdt_ret) {
+ printf("ERROR: board-specific fdt fixup failed: %s\n",
+ fdt_strerror(fdt_ret));
+ goto err;
+ }
}
}
if (IMAGE_OF_SYSTEM_SETUP) {
diff --git a/common/image-fit.c b/common/image-fit.c
index 28b3d2b..94501b1 100644
--- a/common/image-fit.c
+++ b/common/image-fit.c
@@ -1651,7 +1651,7 @@
/* mandatory / node 'timestamp' property */
if (!fdt_getprop(fit, 0, FIT_TIMESTAMP_PROP, NULL)) {
log_debug("Wrong FIT format: no timestamp\n");
- return -ENODATA;
+ return -EBADMSG;
}
}
diff --git a/common/image.c b/common/image.c
index a6500f5..51854aa 100644
--- a/common/image.c
+++ b/common/image.c
@@ -462,13 +462,16 @@
else
ret = -ENOSPC;
break;
-#ifdef CONFIG_GZIP
+#ifndef USE_HOSTCC
+#if CONFIG_IS_ENABLED(GZIP)
case IH_COMP_GZIP: {
ret = gunzip(load_buf, unc_len, image_buf, &image_len);
break;
}
#endif /* CONFIG_GZIP */
-#ifdef CONFIG_BZIP2
+#endif
+#ifndef USE_HOSTCC
+#if CONFIG_IS_ENABLED(BZIP2)
case IH_COMP_BZIP2: {
uint size = unc_len;
@@ -484,7 +487,9 @@
break;
}
#endif /* CONFIG_BZIP2 */
-#ifdef CONFIG_LZMA
+#endif
+#ifndef USE_HOSTCC
+#if CONFIG_IS_ENABLED(LZMA)
case IH_COMP_LZMA: {
SizeT lzma_len = unc_len;
@@ -494,7 +499,9 @@
break;
}
#endif /* CONFIG_LZMA */
-#ifdef CONFIG_LZO
+#endif
+#ifndef USE_HOSTCC
+#if CONFIG_IS_ENABLED(LZO)
case IH_COMP_LZO: {
size_t size = unc_len;
@@ -503,7 +510,9 @@
break;
}
#endif /* CONFIG_LZO */
-#ifdef CONFIG_LZ4
+#endif
+#ifndef USE_HOSTCC
+#if CONFIG_IS_ENABLED(LZ4)
case IH_COMP_LZ4: {
size_t size = unc_len;
@@ -512,7 +521,9 @@
break;
}
#endif /* CONFIG_LZ4 */
-#ifdef CONFIG_ZSTD
+#endif
+#ifndef USE_HOSTCC
+#if CONFIG_IS_ENABLED(ZSTD)
case IH_COMP_ZSTD: {
size_t size = unc_len;
ZSTD_DStream *dstream;
@@ -562,6 +573,7 @@
break;
}
#endif /* CONFIG_ZSTD */
+#endif
default:
printf("Unimplemented compression type %d\n", comp);
return -ENOSYS;
diff --git a/common/usb_kbd.c b/common/usb_kbd.c
index 60c6027..afad260 100644
--- a/common/usb_kbd.c
+++ b/common/usb_kbd.c
@@ -443,6 +443,7 @@
struct usb_interface *iface;
struct usb_endpoint_descriptor *ep;
struct usb_kbd_pdata *data;
+ int epNum;
if (dev->descriptor.bNumConfigurations != 1)
return 0;
@@ -458,19 +459,21 @@
if (iface->desc.bInterfaceProtocol != USB_PROT_HID_KEYBOARD)
return 0;
- if (iface->desc.bNumEndpoints != 1)
- return 0;
+ for (epNum = 0; epNum < iface->desc.bNumEndpoints; epNum++) {
+ ep = &iface->ep_desc[epNum];
- ep = &iface->ep_desc[0];
+ /* Check if endpoint is interrupt IN endpoint */
+ if ((ep->bmAttributes & 3) != 3)
+ continue;
- /* Check if endpoint 1 is interrupt endpoint */
- if (!(ep->bEndpointAddress & 0x80))
- return 0;
+ if (ep->bEndpointAddress & 0x80)
+ break;
+ }
- if ((ep->bmAttributes & 3) != 3)
+ if (epNum == iface->desc.bNumEndpoints)
return 0;
- debug("USB KBD: found set protocol...\n");
+ debug("USB KBD: found interrupt EP: 0x%x\n", ep->bEndpointAddress);
data = malloc(sizeof(struct usb_kbd_pdata));
if (!data) {
@@ -498,13 +501,15 @@
data->last_report = -1;
/* We found a USB Keyboard, install it. */
+ debug("USB KBD: set boot protocol\n");
usb_set_protocol(dev, iface->desc.bInterfaceNumber, 0);
- debug("USB KBD: found set idle...\n");
#if !defined(CONFIG_SYS_USB_EVENT_POLL_VIA_CONTROL_EP) && \
!defined(CONFIG_SYS_USB_EVENT_POLL_VIA_INT_QUEUE)
+ debug("USB KBD: set idle interval...\n");
usb_set_idle(dev, iface->desc.bInterfaceNumber, REPEAT_RATE / 4, 0);
#else
+ debug("USB KBD: set idle interval=0...\n");
usb_set_idle(dev, iface->desc.bInterfaceNumber, 0, 0);
#endif
diff --git a/configs/MPC837XERDB_defconfig b/configs/MPC837XERDB_defconfig
index 0e61c59..63ce36d 100644
--- a/configs/MPC837XERDB_defconfig
+++ b/configs/MPC837XERDB_defconfig
@@ -3,6 +3,7 @@
CONFIG_ENV_SIZE=0x4000
CONFIG_ENV_SECT_SIZE=0x10000
CONFIG_SYS_CLK_FREQ=66666667
+CONFIG_DEFAULT_DEVICE_TREE="mpc8379erdb"
CONFIG_MPC83xx=y
CONFIG_HIGH_BATS=y
CONFIG_TARGET_MPC837XERDB=y
@@ -160,13 +161,12 @@
CONFIG_CMD_DATE=y
CONFIG_CMD_EXT2=y
CONFIG_CMD_FAT=y
-CONFIG_ENV_OVERWRITE=y
CONFIG_OF_CONTROL=y
-CONFIG_DEFAULT_DEVICE_TREE="mpc8379erdb"
+CONFIG_ENV_OVERWRITE=y
CONFIG_ENV_ADDR=0xFE080000
CONFIG_DM=y
-CONFIG_DM_MMC=y
CONFIG_FSL_SATA=y
+CONFIG_DM_MMC=y
CONFIG_FSL_ESDHC=y
CONFIG_MTD_NOR_FLASH=y
CONFIG_FLASH_CFI_DRIVER=y
@@ -186,4 +186,3 @@
CONFIG_SYS_NS16550=y
CONFIG_USB=y
CONFIG_USB_EHCI_HCD=y
-CONFIG_USB_STORAGE=y
diff --git a/configs/MPC8569MDS_ATM_defconfig b/configs/MPC8569MDS_ATM_defconfig
deleted file mode 100644
index b1f4789..0000000
--- a/configs/MPC8569MDS_ATM_defconfig
+++ /dev/null
@@ -1,40 +0,0 @@
-CONFIG_PPC=y
-CONFIG_SYS_TEXT_BASE=0xFFF80000
-CONFIG_ENV_SIZE=0x2000
-CONFIG_ENV_SECT_SIZE=0x20000
-CONFIG_MPC85xx=y
-# CONFIG_CMD_ERRATA is not set
-CONFIG_TARGET_MPC8569MDS=y
-CONFIG_OF_BOARD_SETUP=y
-CONFIG_OF_STDOUT_VIA_ALIAS=y
-CONFIG_SYS_EXTRA_OPTIONS="ATM"
-CONFIG_BOOTDELAY=10
-CONFIG_BOARD_EARLY_INIT_F=y
-CONFIG_BOARD_EARLY_INIT_R=y
-# CONFIG_MISC_INIT_R is not set
-CONFIG_HUSH_PARSER=y
-CONFIG_CMD_REGINFO=y
-CONFIG_CMD_IMLS=y
-CONFIG_CMD_I2C=y
-CONFIG_CMD_MMC=y
-CONFIG_CMD_PCI=y
-CONFIG_CMD_DHCP=y
-CONFIG_CMD_MII=y
-CONFIG_CMD_PING=y
-# CONFIG_CMD_HASH is not set
-CONFIG_CMD_EXT2=y
-CONFIG_CMD_FAT=y
-CONFIG_ENV_OVERWRITE=y
-CONFIG_ENV_IS_IN_FLASH=y
-CONFIG_ENV_ADDR=0xFFF60000
-CONFIG_FSL_ESDHC=y
-CONFIG_MTD=y
-CONFIG_MTD_NOR_FLASH=y
-CONFIG_FLASH_CFI_DRIVER=y
-CONFIG_SYS_FLASH_CFI=y
-CONFIG_MTD_RAW_NAND=y
-CONFIG_E1000=y
-CONFIG_QE=y
-CONFIG_SYS_QE_FMAN_FW_IN_NOR=y
-CONFIG_SYS_NS16550=y
-CONFIG_OF_LIBFDT=y
diff --git a/configs/MPC8569MDS_defconfig b/configs/MPC8569MDS_defconfig
deleted file mode 100644
index 1f0f3dc..0000000
--- a/configs/MPC8569MDS_defconfig
+++ /dev/null
@@ -1,39 +0,0 @@
-CONFIG_PPC=y
-CONFIG_SYS_TEXT_BASE=0xFFF80000
-CONFIG_ENV_SIZE=0x2000
-CONFIG_ENV_SECT_SIZE=0x20000
-CONFIG_MPC85xx=y
-# CONFIG_CMD_ERRATA is not set
-CONFIG_TARGET_MPC8569MDS=y
-CONFIG_OF_BOARD_SETUP=y
-CONFIG_OF_STDOUT_VIA_ALIAS=y
-CONFIG_BOOTDELAY=10
-CONFIG_BOARD_EARLY_INIT_F=y
-CONFIG_BOARD_EARLY_INIT_R=y
-# CONFIG_MISC_INIT_R is not set
-CONFIG_HUSH_PARSER=y
-CONFIG_CMD_REGINFO=y
-CONFIG_CMD_IMLS=y
-CONFIG_CMD_I2C=y
-CONFIG_CMD_MMC=y
-CONFIG_CMD_PCI=y
-CONFIG_CMD_DHCP=y
-CONFIG_CMD_MII=y
-CONFIG_CMD_PING=y
-# CONFIG_CMD_HASH is not set
-CONFIG_CMD_EXT2=y
-CONFIG_CMD_FAT=y
-CONFIG_ENV_OVERWRITE=y
-CONFIG_ENV_IS_IN_FLASH=y
-CONFIG_ENV_ADDR=0xFFF60000
-CONFIG_FSL_ESDHC=y
-CONFIG_MTD=y
-CONFIG_MTD_NOR_FLASH=y
-CONFIG_FLASH_CFI_DRIVER=y
-CONFIG_SYS_FLASH_CFI=y
-CONFIG_MTD_RAW_NAND=y
-CONFIG_E1000=y
-CONFIG_QE=y
-CONFIG_SYS_QE_FMAN_FW_IN_NOR=y
-CONFIG_SYS_NS16550=y
-CONFIG_OF_LIBFDT=y
diff --git a/configs/P2041RDB_SECURE_BOOT_defconfig b/configs/P2041RDB_SECURE_BOOT_defconfig
deleted file mode 100644
index c42e583..0000000
--- a/configs/P2041RDB_SECURE_BOOT_defconfig
+++ /dev/null
@@ -1,62 +0,0 @@
-CONFIG_PPC=y
-CONFIG_SYS_TEXT_BASE=0xEFF40000
-CONFIG_ENV_SIZE=0x2000
-CONFIG_NXP_ESBC=y
-CONFIG_DEFAULT_DEVICE_TREE="p2041rdb"
-CONFIG_MPC85xx=y
-CONFIG_TARGET_P2041RDB=y
-CONFIG_MPC85XX_HAVE_RESET_VECTOR=y
-CONFIG_FIT=y
-CONFIG_FIT_VERBOSE=y
-CONFIG_OF_BOARD_SETUP=y
-CONFIG_OF_STDOUT_VIA_ALIAS=y
-CONFIG_BOOTDELAY=10
-CONFIG_BOARD_EARLY_INIT_F=y
-CONFIG_BOARD_EARLY_INIT_R=y
-CONFIG_HUSH_PARSER=y
-CONFIG_CMD_IMLS=y
-CONFIG_CMD_GREPENV=y
-CONFIG_CMD_DM=y
-CONFIG_CMD_I2C=y
-CONFIG_CMD_MMC=y
-CONFIG_CMD_SF=y
-CONFIG_CMD_USB=y
-CONFIG_CMD_DHCP=y
-CONFIG_CMD_MII=y
-CONFIG_CMD_PING=y
-CONFIG_MP=y
-CONFIG_CMD_EXT2=y
-CONFIG_CMD_FAT=y
-CONFIG_OF_CONTROL=y
-CONFIG_ENV_OVERWRITE=y
-CONFIG_DM=y
-CONFIG_FSL_ESDHC=y
-CONFIG_MTD=y
-CONFIG_MTD_NOR_FLASH=y
-CONFIG_FLASH_CFI_DRIVER=y
-CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y
-CONFIG_SYS_FLASH_CFI=y
-CONFIG_SPI_FLASH=y
-CONFIG_SF_DEFAULT_MODE=0
-CONFIG_SF_DEFAULT_SPEED=10000000
-CONFIG_SPI_FLASH_SPANSION=y
-CONFIG_PHYLIB=y
-CONFIG_PHYLIB_10G=y
-CONFIG_PHY_TERANETICS=y
-CONFIG_PHY_VITESSE=y
-CONFIG_DM_ETH=y
-CONFIG_DM_MDIO=y
-CONFIG_PHY_GIGE=y
-CONFIG_FMAN_ENET=y
-CONFIG_MII=y
-CONFIG_SYS_QE_FMAN_FW_IN_NOR=y
-CONFIG_SYS_NS16550=y
-CONFIG_SPI=y
-CONFIG_FSL_ESPI=y
-CONFIG_USB=y
-CONFIG_USB_STORAGE=y
-CONFIG_ADDR_MAP=y
-CONFIG_SYS_NUM_ADDR_MAP=64
-CONFIG_RSA=y
-CONFIG_SPL_RSA=y
-CONFIG_RSA_SOFTWARE_EXP=y
diff --git a/configs/P2041RDB_SRIO_PCIE_BOOT_defconfig b/configs/P2041RDB_SRIO_PCIE_BOOT_defconfig
deleted file mode 100644
index 822a91b..0000000
--- a/configs/P2041RDB_SRIO_PCIE_BOOT_defconfig
+++ /dev/null
@@ -1,53 +0,0 @@
-CONFIG_PPC=y
-CONFIG_SYS_TEXT_BASE=0xFFF40000
-CONFIG_ENV_SIZE=0x2000
-CONFIG_MPC85xx=y
-CONFIG_TARGET_P2041RDB=y
-CONFIG_FIT=y
-CONFIG_FIT_VERBOSE=y
-CONFIG_OF_BOARD_SETUP=y
-CONFIG_OF_STDOUT_VIA_ALIAS=y
-CONFIG_SYS_EXTRA_OPTIONS="SRIO_PCIE_BOOT_SLAVE"
-CONFIG_BOOTDELAY=10
-CONFIG_BOARD_EARLY_INIT_F=y
-CONFIG_BOARD_EARLY_INIT_R=y
-CONFIG_HUSH_PARSER=y
-CONFIG_CMD_GREPENV=y
-# CONFIG_CMD_FLASH is not set
-CONFIG_CMD_I2C=y
-CONFIG_CMD_MMC=y
-CONFIG_CMD_SF=y
-CONFIG_CMD_USB=y
-CONFIG_CMD_DHCP=y
-CONFIG_CMD_MII=y
-CONFIG_CMD_PING=y
-CONFIG_MP=y
-CONFIG_CMD_EXT2=y
-CONFIG_CMD_FAT=y
-CONFIG_ENV_OVERWRITE=y
-CONFIG_ENV_IS_IN_REMOTE=y
-CONFIG_ENV_ADDR=0xFFE20000
-CONFIG_FSL_CAAM=y
-CONFIG_FSL_ESDHC=y
-CONFIG_MTD=y
-CONFIG_SPI_FLASH=y
-CONFIG_SF_DEFAULT_MODE=0
-CONFIG_SF_DEFAULT_SPEED=10000000
-CONFIG_SPI_FLASH_SPANSION=y
-CONFIG_PHYLIB=y
-CONFIG_PHYLIB_10G=y
-CONFIG_PHY_TERANETICS=y
-CONFIG_PHY_VITESSE=y
-CONFIG_PHY_GIGE=y
-CONFIG_E1000=y
-CONFIG_FMAN_ENET=y
-CONFIG_MII=y
-CONFIG_SYS_QE_FMAN_FW_IN_REMOTE=y
-CONFIG_SYS_NS16550=y
-CONFIG_SPI=y
-CONFIG_FSL_ESPI=y
-CONFIG_USB=y
-CONFIG_USB_STORAGE=y
-CONFIG_ADDR_MAP=y
-CONFIG_SYS_NUM_ADDR_MAP=64
-CONFIG_OF_LIBFDT=y
diff --git a/configs/P3041DS_SRIO_PCIE_BOOT_defconfig b/configs/P3041DS_SRIO_PCIE_BOOT_defconfig
deleted file mode 100644
index 76ac6ab..0000000
--- a/configs/P3041DS_SRIO_PCIE_BOOT_defconfig
+++ /dev/null
@@ -1,53 +0,0 @@
-CONFIG_PPC=y
-CONFIG_SYS_TEXT_BASE=0xFFF40000
-CONFIG_ENV_SIZE=0x2000
-CONFIG_MPC85xx=y
-CONFIG_TARGET_P3041DS=y
-CONFIG_FIT=y
-CONFIG_FIT_VERBOSE=y
-CONFIG_OF_BOARD_SETUP=y
-CONFIG_OF_STDOUT_VIA_ALIAS=y
-CONFIG_SYS_EXTRA_OPTIONS="SRIO_PCIE_BOOT_SLAVE"
-CONFIG_BOOTDELAY=10
-CONFIG_BOARD_EARLY_INIT_F=y
-CONFIG_BOARD_EARLY_INIT_R=y
-CONFIG_HUSH_PARSER=y
-CONFIG_CMD_GREPENV=y
-# CONFIG_CMD_FLASH is not set
-CONFIG_CMD_I2C=y
-CONFIG_CMD_MMC=y
-CONFIG_CMD_SF=y
-CONFIG_CMD_USB=y
-CONFIG_CMD_DHCP=y
-CONFIG_CMD_MII=y
-CONFIG_CMD_PING=y
-CONFIG_MP=y
-CONFIG_CMD_EXT2=y
-CONFIG_CMD_FAT=y
-CONFIG_ENV_OVERWRITE=y
-CONFIG_ENV_IS_IN_REMOTE=y
-CONFIG_ENV_ADDR=0xFFE20000
-CONFIG_FSL_CAAM=y
-CONFIG_FSL_ESDHC=y
-CONFIG_MTD=y
-CONFIG_SPI_FLASH=y
-CONFIG_SF_DEFAULT_MODE=0
-CONFIG_SF_DEFAULT_SPEED=10000000
-CONFIG_SPI_FLASH_SPANSION=y
-CONFIG_PHYLIB=y
-CONFIG_PHYLIB_10G=y
-CONFIG_PHY_TERANETICS=y
-CONFIG_PHY_VITESSE=y
-CONFIG_PHY_GIGE=y
-CONFIG_E1000=y
-CONFIG_FMAN_ENET=y
-CONFIG_MII=y
-CONFIG_SYS_QE_FMAN_FW_IN_REMOTE=y
-CONFIG_SYS_NS16550=y
-CONFIG_SPI=y
-CONFIG_FSL_ESPI=y
-CONFIG_USB=y
-CONFIG_USB_STORAGE=y
-CONFIG_ADDR_MAP=y
-CONFIG_SYS_NUM_ADDR_MAP=64
-CONFIG_OF_LIBFDT=y
diff --git a/configs/P4080DS_SRIO_PCIE_BOOT_defconfig b/configs/P4080DS_SRIO_PCIE_BOOT_defconfig
deleted file mode 100644
index 5bfce4b..0000000
--- a/configs/P4080DS_SRIO_PCIE_BOOT_defconfig
+++ /dev/null
@@ -1,51 +0,0 @@
-CONFIG_PPC=y
-CONFIG_SYS_TEXT_BASE=0xFFF40000
-CONFIG_ENV_SIZE=0x2000
-CONFIG_MPC85xx=y
-CONFIG_TARGET_P4080DS=y
-CONFIG_FIT=y
-CONFIG_FIT_VERBOSE=y
-CONFIG_OF_BOARD_SETUP=y
-CONFIG_OF_STDOUT_VIA_ALIAS=y
-CONFIG_SYS_EXTRA_OPTIONS="SRIO_PCIE_BOOT_SLAVE"
-CONFIG_BOOTDELAY=10
-CONFIG_BOARD_EARLY_INIT_F=y
-CONFIG_BOARD_EARLY_INIT_R=y
-CONFIG_HUSH_PARSER=y
-CONFIG_CMD_GREPENV=y
-CONFIG_CMD_I2C=y
-CONFIG_CMD_MMC=y
-CONFIG_CMD_SF=y
-CONFIG_CMD_USB=y
-CONFIG_CMD_DHCP=y
-CONFIG_CMD_MII=y
-CONFIG_CMD_PING=y
-CONFIG_MP=y
-CONFIG_CMD_EXT2=y
-CONFIG_CMD_FAT=y
-CONFIG_ENV_OVERWRITE=y
-CONFIG_ENV_IS_IN_REMOTE=y
-CONFIG_ENV_ADDR=0xFFE20000
-CONFIG_FSL_CAAM=y
-CONFIG_FSL_ESDHC=y
-CONFIG_SPI_FLASH=y
-CONFIG_SF_DEFAULT_MODE=0
-CONFIG_SF_DEFAULT_SPEED=10000000
-CONFIG_SPI_FLASH_SPANSION=y
-CONFIG_PHYLIB=y
-CONFIG_PHYLIB_10G=y
-CONFIG_PHY_TERANETICS=y
-CONFIG_PHY_VITESSE=y
-CONFIG_PHY_GIGE=y
-CONFIG_E1000=y
-CONFIG_FMAN_ENET=y
-CONFIG_MII=y
-CONFIG_SYS_QE_FMAN_FW_IN_REMOTE=y
-CONFIG_SYS_NS16550=y
-CONFIG_SPI=y
-CONFIG_FSL_ESPI=y
-CONFIG_USB=y
-CONFIG_USB_STORAGE=y
-CONFIG_ADDR_MAP=y
-CONFIG_SYS_NUM_ADDR_MAP=64
-CONFIG_OF_LIBFDT=y
diff --git a/configs/T2080RDB_SECURE_BOOT_defconfig b/configs/T2080RDB_SECURE_BOOT_defconfig
deleted file mode 100644
index b82a4cc..0000000
--- a/configs/T2080RDB_SECURE_BOOT_defconfig
+++ /dev/null
@@ -1,66 +0,0 @@
-CONFIG_PPC=y
-CONFIG_SYS_TEXT_BASE=0xEFF40000
-CONFIG_SYS_MEMTEST_START=0x00200000
-CONFIG_SYS_MEMTEST_END=0x00400000
-CONFIG_ENV_SIZE=0x2000
-CONFIG_NXP_ESBC=y
-CONFIG_MPC85xx=y
-CONFIG_TARGET_T2080RDB=y
-# CONFIG_SYS_MALLOC_F is not set
-CONFIG_FIT=y
-CONFIG_FIT_VERBOSE=y
-CONFIG_OF_BOARD_SETUP=y
-CONFIG_OF_STDOUT_VIA_ALIAS=y
-CONFIG_BOOTDELAY=10
-CONFIG_BOARD_EARLY_INIT_R=y
-CONFIG_HUSH_PARSER=y
-CONFIG_CMD_IMLS=y
-CONFIG_CMD_MEMTEST=y
-CONFIG_SYS_ALT_MEMTEST=y
-CONFIG_CMD_I2C=y
-CONFIG_CMD_MMC=y
-CONFIG_CMD_SF=y
-CONFIG_CMD_USB=y
-CONFIG_CMD_DHCP=y
-CONFIG_CMD_MII=y
-CONFIG_CMD_PING=y
-CONFIG_MP=y
-CONFIG_CMD_EXT2=y
-CONFIG_CMD_FAT=y
-CONFIG_CMD_MTDPARTS=y
-CONFIG_MTDIDS_DEFAULT="nor0=fe8000000.nor,nand0=fff800000.flash,spi0=spife110000.1"
-CONFIG_MTDPARTS_DEFAULT="mtdparts=fe8000000.nor:1m(uboot),5m(kernel),128k(dtb),96m(fs),-(user);fff800000.flash:1m(uboot),5m(kernel),128k(dtb),96m(fs),-(user);spife110000.1:1m(uboot),5m(kernel),128k(dtb),-(user)"
-# CONFIG_CMD_IRQ is not set
-CONFIG_ENV_OVERWRITE=y
-CONFIG_SYS_RELOC_GD_ENV_ADDR=y
-CONFIG_DM=y
-CONFIG_FSL_ESDHC=y
-CONFIG_MTD=y
-CONFIG_MTD_NOR_FLASH=y
-CONFIG_FLASH_CFI_DRIVER=y
-CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y
-CONFIG_FLASH_CFI_MTD=y
-CONFIG_SYS_FLASH_CFI=y
-CONFIG_SPI_FLASH=y
-CONFIG_SF_DEFAULT_MODE=0
-CONFIG_SF_DEFAULT_SPEED=10000000
-CONFIG_SPI_FLASH_STMICRO=y
-CONFIG_PHYLIB=y
-CONFIG_PHY_AQUANTIA=y
-CONFIG_PHY_CORTINA=y
-CONFIG_PHY_REALTEK=y
-CONFIG_E1000=y
-CONFIG_FMAN_ENET=y
-CONFIG_MII=y
-CONFIG_SYS_QE_FMAN_FW_IN_NOR=y
-CONFIG_SYS_NS16550=y
-CONFIG_SPI=y
-CONFIG_FSL_ESPI=y
-CONFIG_USB=y
-CONFIG_USB_STORAGE=y
-CONFIG_ADDR_MAP=y
-CONFIG_SYS_NUM_ADDR_MAP=64
-CONFIG_RSA=y
-CONFIG_SPL_RSA=y
-CONFIG_RSA_SOFTWARE_EXP=y
-CONFIG_OF_LIBFDT=y
diff --git a/configs/T2080RDB_SRIO_PCIE_BOOT_defconfig b/configs/T2080RDB_SRIO_PCIE_BOOT_defconfig
deleted file mode 100644
index 54579fa..0000000
--- a/configs/T2080RDB_SRIO_PCIE_BOOT_defconfig
+++ /dev/null
@@ -1,56 +0,0 @@
-CONFIG_PPC=y
-CONFIG_SYS_TEXT_BASE=0xFFF40000
-CONFIG_SYS_MEMTEST_START=0x00200000
-CONFIG_SYS_MEMTEST_END=0x00400000
-CONFIG_ENV_SIZE=0x2000
-CONFIG_MPC85xx=y
-CONFIG_TARGET_T2080RDB=y
-CONFIG_FIT=y
-CONFIG_FIT_VERBOSE=y
-CONFIG_OF_BOARD_SETUP=y
-CONFIG_OF_STDOUT_VIA_ALIAS=y
-CONFIG_SYS_EXTRA_OPTIONS="SRIO_PCIE_BOOT_SLAVE"
-CONFIG_BOOTDELAY=10
-CONFIG_BOARD_EARLY_INIT_R=y
-CONFIG_HUSH_PARSER=y
-CONFIG_CMD_MEMTEST=y
-CONFIG_SYS_ALT_MEMTEST=y
-# CONFIG_CMD_FLASH is not set
-CONFIG_CMD_I2C=y
-CONFIG_CMD_MMC=y
-CONFIG_CMD_SF=y
-CONFIG_CMD_USB=y
-CONFIG_CMD_DHCP=y
-CONFIG_CMD_MII=y
-CONFIG_CMD_PING=y
-CONFIG_MP=y
-CONFIG_CMD_EXT2=y
-CONFIG_CMD_FAT=y
-# CONFIG_CMD_IRQ is not set
-CONFIG_ENV_OVERWRITE=y
-CONFIG_ENV_IS_IN_REMOTE=y
-CONFIG_ENV_ADDR=0xFFE20000
-CONFIG_FSL_CAAM=y
-CONFIG_FSL_ESDHC=y
-CONFIG_MTD=y
-CONFIG_SPI_FLASH=y
-CONFIG_SF_DEFAULT_MODE=0
-CONFIG_SF_DEFAULT_SPEED=10000000
-CONFIG_SPI_FLASH_STMICRO=y
-CONFIG_PHYLIB=y
-CONFIG_PHY_AQUANTIA=y
-CONFIG_PHY_CORTINA=y
-CONFIG_SYS_CORTINA_FW_IN_REMOTE=y
-CONFIG_PHY_REALTEK=y
-CONFIG_E1000=y
-CONFIG_FMAN_ENET=y
-CONFIG_MII=y
-CONFIG_SYS_QE_FMAN_FW_IN_REMOTE=y
-CONFIG_SYS_NS16550=y
-CONFIG_SPI=y
-CONFIG_FSL_ESPI=y
-CONFIG_USB=y
-CONFIG_USB_STORAGE=y
-CONFIG_ADDR_MAP=y
-CONFIG_SYS_NUM_ADDR_MAP=64
-CONFIG_OF_LIBFDT=y
diff --git a/configs/am3517_evm_defconfig b/configs/am3517_evm_defconfig
index bae0e0a..0bc7bf7 100644
--- a/configs/am3517_evm_defconfig
+++ b/configs/am3517_evm_defconfig
@@ -15,6 +15,7 @@
CONFIG_DISTRO_DEFAULTS=y
CONFIG_BOOTDELAY=10
# CONFIG_USE_BOOTCOMMAND is not set
+CONFIG_SPL_ALLOC_BD=y
CONFIG_SPL_SYS_MALLOC_SIMPLE=y
CONFIG_SPL_SEPARATE_BSS=y
# CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR is not set
diff --git a/configs/am65x_evm_a53_defconfig b/configs/am65x_evm_a53_defconfig
index 0b5a27f..1f2d78d 100644
--- a/configs/am65x_evm_a53_defconfig
+++ b/configs/am65x_evm_a53_defconfig
@@ -98,7 +98,6 @@
CONFIG_I2C_SET_DEFAULT_BUS_NUM=y
CONFIG_DM_I2C_GPIO=y
CONFIG_SYS_I2C_OMAP24XX=y
-CONFIG_DM_KEYBOARD=y
CONFIG_DM_MAILBOX=y
CONFIG_K3_SEC_PROXY=y
CONFIG_DM_MMC=y
diff --git a/configs/am65x_evm_r5_defconfig b/configs/am65x_evm_r5_defconfig
index b9b1101..57f3300 100644
--- a/configs/am65x_evm_r5_defconfig
+++ b/configs/am65x_evm_r5_defconfig
@@ -17,6 +17,8 @@
CONFIG_SPL_SERIAL_SUPPORT=y
CONFIG_SPL_DRIVERS_MISC_SUPPORT=y
CONFIG_SPL_STACK_R_ADDR=0x82000000
+CONFIG_SPL_SIZE_LIMIT=0x7ec00
+CONFIG_SPL_SIZE_LIMIT_PROVIDE_STACK=0x2000
CONFIG_SPL_FS_FAT=y
CONFIG_SPL_LIBDISK_SUPPORT=y
CONFIG_SPL_SPI_FLASH_SUPPORT=y
@@ -27,6 +29,9 @@
# CONFIG_USE_SPL_FIT_GENERATOR is not set
CONFIG_USE_BOOTCOMMAND=y
# CONFIG_DISPLAY_CPUINFO is not set
+CONFIG_SPL_SIZE_LIMIT_SUBTRACT_GD=y
+CONFIG_SPL_SIZE_LIMIT_SUBTRACT_MALLOC=y
+CONFIG_SPL_SYS_REPORT_STACK_F_USAGE=y
CONFIG_SPL_STACK_R=y
CONFIG_SPL_SEPARATE_BSS=y
CONFIG_SPL_EARLY_BSS=y
diff --git a/configs/am65x_hs_evm_a53_defconfig b/configs/am65x_hs_evm_a53_defconfig
index 7d467c1..a9737d0 100644
--- a/configs/am65x_hs_evm_a53_defconfig
+++ b/configs/am65x_hs_evm_a53_defconfig
@@ -92,7 +92,6 @@
CONFIG_DM_I2C=y
CONFIG_I2C_SET_DEFAULT_BUS_NUM=y
CONFIG_SYS_I2C_OMAP24XX=y
-CONFIG_DM_KEYBOARD=y
CONFIG_DM_MAILBOX=y
CONFIG_K3_SEC_PROXY=y
CONFIG_DM_MMC=y
diff --git a/configs/chromebook_coral_defconfig b/configs/chromebook_coral_defconfig
index ab73a0a..0811ffd 100644
--- a/configs/chromebook_coral_defconfig
+++ b/configs/chromebook_coral_defconfig
@@ -20,6 +20,7 @@
CONFIG_INTEL_CAR_CQOS=y
CONFIG_X86_OFFSET_U_BOOT=0xffd00000
CONFIG_X86_OFFSET_SPL=0xffe80000
+CONFIG_INTEL_ACPIGEN=y
CONFIG_INTEL_GENERIC_WIFI=y
CONFIG_CHROMEOS=y
CONFIG_BOOTSTAGE=y
@@ -76,7 +77,6 @@
CONFIG_REGMAP=y
CONFIG_SYSCON=y
CONFIG_SPL_OF_TRANSLATE=y
-CONFIG_INTEL_ACPIGEN=y
CONFIG_CPU=y
CONFIG_DM_I2C=y
CONFIG_SYS_I2C_DW=y
diff --git a/configs/cm_fx6_defconfig b/configs/cm_fx6_defconfig
index 86e4135..aed25b6 100644
--- a/configs/cm_fx6_defconfig
+++ b/configs/cm_fx6_defconfig
@@ -63,7 +63,6 @@
CONFIG_BOUNCE_BUFFER=y
CONFIG_DWC_AHSATA=y
# CONFIG_DWC_AHSATA_AHCI is not set
-CONFIG_DM_KEYBOARD=y
CONFIG_DM_MMC=y
CONFIG_FSL_USDHC=y
CONFIG_MTD=y
diff --git a/configs/dh_imx6_defconfig b/configs/dh_imx6_defconfig
index 7bb6ce1..b8c0f86 100644
--- a/configs/dh_imx6_defconfig
+++ b/configs/dh_imx6_defconfig
@@ -4,6 +4,7 @@
CONFIG_SPL_GPIO_SUPPORT=y
CONFIG_SPL_LIBCOMMON_SUPPORT=y
CONFIG_SPL_LIBGENERIC_SUPPORT=y
+CONFIG_SYS_MALLOC_F_LEN=0x1000
CONFIG_NR_DRAM_BANKS=1
CONFIG_SYS_MEMTEST_START=0x10000000
CONFIG_SYS_MEMTEST_END=0x20000000
@@ -28,8 +29,8 @@
CONFIG_DEFAULT_DEVICE_TREE="imx6q-dhcom-pdk2"
CONFIG_AHCI=y
CONFIG_DISTRO_DEFAULTS=y
-# CONFIG_SYS_MALLOC_F is not set
CONFIG_FIT=y
+CONFIG_FIT_VERBOSE=y
CONFIG_SPL_FIT=y
# CONFIG_USE_SPL_FIT_GENERATOR is not set
CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=arch/arm/mach-imx/spl_sd.cfg"
@@ -54,14 +55,12 @@
CONFIG_CMD_TIME=y
CONFIG_CMD_EXT4_WRITE=y
CONFIG_OF_CONTROL=y
-CONFIG_SPL_OF_CONTROL=y
CONFIG_OF_LIST="imx6q-dhcom-pdk2 imx6dl-dhcom-pdk2"
CONFIG_MULTI_DTB_FIT=y
CONFIG_ENV_OVERWRITE=y
CONFIG_ENV_IS_IN_SPI_FLASH=y
CONFIG_SYS_REDUNDAND_ENVIRONMENT=y
CONFIG_SYS_RELOC_GD_ENV_ADDR=y
-CONFIG_SPL_DM=y
CONFIG_BOUNCE_BUFFER=y
CONFIG_DWC_AHSATA=y
CONFIG_BOOTCOUNT_LIMIT=y
@@ -108,5 +107,5 @@
CONFIG_USB_GADGET_DOWNLOAD=y
CONFIG_WATCHDOG_TIMEOUT_MSECS=60000
CONFIG_IMX_WATCHDOG=y
-# CONFIG_SPL_WDT is not set
CONFIG_BZIP2=y
+CONFIG_OF_LIBFDT_OVERLAY=y
diff --git a/configs/firefly-rk3288_defconfig b/configs/firefly-rk3288_defconfig
index 6c04123..b3c2234 100644
--- a/configs/firefly-rk3288_defconfig
+++ b/configs/firefly-rk3288_defconfig
@@ -48,7 +48,6 @@
CONFIG_FASTBOOT_CMD_OEM_FORMAT=y
CONFIG_ROCKCHIP_GPIO=y
CONFIG_SYS_I2C_ROCKCHIP=y
-CONFIG_DM_KEYBOARD=y
CONFIG_LED=y
CONFIG_LED_GPIO=y
CONFIG_MMC_DW=y
diff --git a/configs/hikey_defconfig b/configs/hikey_defconfig
index 5fb4823..d2bb196 100644
--- a/configs/hikey_defconfig
+++ b/configs/hikey_defconfig
@@ -24,8 +24,10 @@
CONFIG_DM_MMC=y
CONFIG_MMC_DW=y
CONFIG_MMC_DW_K3=y
+CONFIG_DM_ETH=y
CONFIG_CONS_INDEX=4
CONFIG_USB=y
+CONFIG_DM_USB=y
CONFIG_USB_DWC2=y
CONFIG_USB_HOST_ETHER=y
CONFIG_USB_ETHER_ASIX=y
diff --git a/configs/imx8mm_venice_defconfig b/configs/imx8mm_venice_defconfig
new file mode 100644
index 0000000..a15c364
--- /dev/null
+++ b/configs/imx8mm_venice_defconfig
@@ -0,0 +1,113 @@
+CONFIG_ARM=y
+CONFIG_ARCH_IMX8M=y
+CONFIG_SYS_TEXT_BASE=0x40200000
+CONFIG_SPL_GPIO_SUPPORT=y
+CONFIG_SPL_LIBCOMMON_SUPPORT=y
+CONFIG_SPL_LIBGENERIC_SUPPORT=y
+CONFIG_SYS_MALLOC_F_LEN=0x10000
+CONFIG_SYS_MEMTEST_START=0x40000000
+CONFIG_SYS_MEMTEST_END=0x80000000
+CONFIG_ENV_SIZE=0x8000
+CONFIG_ENV_OFFSET=0xff0000
+CONFIG_SYS_I2C_MXC_I2C1=y
+CONFIG_SYS_I2C_MXC_I2C2=y
+CONFIG_SYS_I2C_MXC_I2C3=y
+CONFIG_DM_GPIO=y
+CONFIG_SPL_TEXT_BASE=0x7E1000
+CONFIG_TARGET_IMX8MM_VENICE=y
+CONFIG_SPL_MMC_SUPPORT=y
+CONFIG_SPL_SERIAL_SUPPORT=y
+CONFIG_SPL_DRIVERS_MISC_SUPPORT=y
+CONFIG_SPL=y
+CONFIG_ENV_OFFSET_REDUND=0xff8000
+CONFIG_DEFAULT_DEVICE_TREE="imx8mm-venice"
+CONFIG_DISTRO_DEFAULTS=y
+CONFIG_FIT=y
+CONFIG_FIT_EXTERNAL_OFFSET=0x3000
+CONFIG_SPL_LOAD_FIT=y
+CONFIG_SPL_LOAD_FIT_FULL=y
+CONFIG_SPL_FIT_GENERATOR="arch/arm/mach-imx/mkimage_fit_atf.sh"
+CONFIG_OF_SYSTEM_SETUP=y
+CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=arch/arm/mach-imx/imx8m/imximage-8mm-lpddr4.cfg"
+# CONFIG_USE_BOOTCOMMAND is not set
+CONFIG_USE_PREBOOT=y
+CONFIG_PREBOOT="gsc wd-disable"
+CONFIG_BOARD_LATE_INIT=y
+CONFIG_SPL_SEPARATE_BSS=y
+CONFIG_SPL_I2C_SUPPORT=y
+CONFIG_SPL_POWER_SUPPORT=y
+CONFIG_SPL_WATCHDOG_SUPPORT=y
+CONFIG_SYS_PROMPT="u-boot=> "
+# CONFIG_CMD_EXPORTENV is not set
+# CONFIG_CMD_IMPORTENV is not set
+# CONFIG_CMD_CRC32 is not set
+CONFIG_CMD_MEMTEST=y
+CONFIG_CMD_CLK=y
+CONFIG_CMD_FUSE=y
+CONFIG_CMD_GPIO=y
+CONFIG_CMD_I2C=y
+CONFIG_CMD_MMC=y
+CONFIG_CMD_CACHE=y
+CONFIG_CMD_TIME=y
+CONFIG_CMD_UUID=y
+CONFIG_CMD_PMIC=y
+CONFIG_CMD_REGULATOR=y
+CONFIG_CMD_EXT4_WRITE=y
+# CONFIG_ISO_PARTITION is not set
+# CONFIG_SPL_EFI_PARTITION is not set
+CONFIG_OF_CONTROL=y
+CONFIG_SPL_OF_CONTROL=y
+CONFIG_OF_LIST="imx8mm-venice-gw71xx-0x imx8mm-venice-gw72xx-0x imx8mm-venice-gw73xx-0x"
+CONFIG_ENV_IS_IN_MMC=y
+CONFIG_SYS_REDUNDAND_ENVIRONMENT=y
+CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y
+CONFIG_NET_RANDOM_ETHADDR=y
+CONFIG_IP_DEFRAG=y
+CONFIG_TFTP_BLOCKSIZE=4096
+CONFIG_SPL_DM=y
+CONFIG_SPL_CLK_COMPOSITE_CCF=y
+CONFIG_CLK_COMPOSITE_CCF=y
+CONFIG_SPL_CLK_IMX8MM=y
+CONFIG_CLK_IMX8MM=y
+CONFIG_MXC_GPIO=y
+CONFIG_DM_I2C=y
+CONFIG_SYS_I2C_MXC=y
+CONFIG_LED=y
+CONFIG_LED_BLINK=y
+CONFIG_LED_GPIO=y
+CONFIG_DM_MMC=y
+CONFIG_SUPPORT_EMMC_BOOT=y
+CONFIG_MMC_IO_VOLTAGE=y
+CONFIG_SPL_MMC_IO_VOLTAGE=y
+CONFIG_MMC_UHS_SUPPORT=y
+CONFIG_SPL_MMC_UHS_SUPPORT=y
+CONFIG_MMC_HS400_ES_SUPPORT=y
+CONFIG_MMC_HS400_SUPPORT=y
+CONFIG_SPL_MMC_HS400_SUPPORT=y
+CONFIG_FSL_USDHC=y
+CONFIG_PHYLIB=y
+CONFIG_PHY_TI_DP83867=y
+CONFIG_DM_ETH=y
+CONFIG_PHY_GIGE=y
+CONFIG_FEC_MXC=y
+CONFIG_MII=y
+CONFIG_PINCTRL=y
+CONFIG_SPL_PINCTRL=y
+CONFIG_PINCTRL_IMX8M=y
+CONFIG_DM_PMIC=y
+CONFIG_DM_PMIC_BD71837=y
+CONFIG_SPL_DM_PMIC_BD71837=y
+CONFIG_DM_PMIC_MP5416=y
+CONFIG_SPL_DM_PMIC_MP5416=y
+CONFIG_DM_REGULATOR=y
+CONFIG_DM_REGULATOR_FIXED=y
+CONFIG_DM_REGULATOR_GPIO=y
+CONFIG_MXC_UART=y
+CONFIG_SYSRESET=y
+CONFIG_SPL_SYSRESET=y
+CONFIG_SYSRESET_PSCI=y
+CONFIG_SYSRESET_WATCHDOG=y
+CONFIG_DM_THERMAL=y
+CONFIG_IMX_TMU=y
+CONFIG_IMX_WATCHDOG=y
+CONFIG_HEXDUMP=y
diff --git a/configs/imx8mn_beacon_2g_defconfig b/configs/imx8mn_beacon_2g_defconfig
new file mode 100644
index 0000000..58b8e49
--- /dev/null
+++ b/configs/imx8mn_beacon_2g_defconfig
@@ -0,0 +1,133 @@
+CONFIG_ARM=y
+CONFIG_ARCH_IMX8M=y
+CONFIG_SYS_TEXT_BASE=0x40200000
+CONFIG_SPL_GPIO_SUPPORT=y
+CONFIG_SPL_LIBCOMMON_SUPPORT=y
+CONFIG_SPL_LIBGENERIC_SUPPORT=y
+CONFIG_SYS_MALLOC_F_LEN=0x10000
+CONFIG_NR_DRAM_BANKS=1
+CONFIG_SYS_MEMTEST_START=0x40000000
+CONFIG_SYS_MEMTEST_END=0x44000000
+CONFIG_ENV_SIZE=0x2000
+CONFIG_ENV_OFFSET=0xFFFFDE00
+CONFIG_SYS_I2C_MXC_I2C1=y
+CONFIG_SYS_I2C_MXC_I2C2=y
+CONFIG_SYS_I2C_MXC_I2C3=y
+CONFIG_DM_GPIO=y
+CONFIG_SPL_TEXT_BASE=0x912000
+CONFIG_TARGET_IMX8MN_BEACON=y
+CONFIG_IMX8MN_BEACON_2GB_LPDDR=y
+CONFIG_SPL_SERIAL_SUPPORT=y
+CONFIG_SPL_DRIVERS_MISC_SUPPORT=y
+CONFIG_SPL_SYS_MALLOC_F_LEN=0x2000
+CONFIG_SPL=y
+CONFIG_SPL_IMX_ROMAPI_LOADADDR=0x48000000
+CONFIG_DEFAULT_DEVICE_TREE="imx8mn-beacon-kit"
+CONFIG_FIT=y
+CONFIG_FIT_EXTERNAL_OFFSET=0x3000
+CONFIG_SPL_LOAD_FIT=y
+CONFIG_SPL_FIT_GENERATOR="arch/arm/mach-imx/mkimage_fit_atf.sh"
+CONFIG_OF_SYSTEM_SETUP=y
+CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=arch/arm/mach-imx/imx8m/imximage-8mn-lpddr4.cfg"
+CONFIG_DEFAULT_FDT_FILE="imx8mn-beacon-kit.dtb"
+CONFIG_ARCH_MISC_INIT=y
+CONFIG_SPL_BOARD_INIT=y
+CONFIG_SPL_BOOTROM_SUPPORT=y
+CONFIG_SPL_SEPARATE_BSS=y
+CONFIG_SPL_I2C_SUPPORT=y
+CONFIG_SPL_POWER_SUPPORT=y
+CONFIG_HUSH_PARSER=y
+CONFIG_SYS_PROMPT="u-boot=> "
+# CONFIG_BOOTM_NETBSD is not set
+# CONFIG_CMD_EXPORTENV is not set
+# CONFIG_CMD_IMPORTENV is not set
+CONFIG_CMD_ERASEENV=y
+# CONFIG_CMD_CRC32 is not set
+CONFIG_CMD_MEMTEST=y
+CONFIG_CMD_CLK=y
+CONFIG_CMD_FUSE=y
+CONFIG_CMD_GPIO=y
+CONFIG_CMD_I2C=y
+CONFIG_CMD_MMC=y
+CONFIG_CMD_PART=y
+CONFIG_CMD_DHCP=y
+CONFIG_CMD_MII=y
+CONFIG_CMD_PING=y
+CONFIG_CMD_CACHE=y
+CONFIG_CMD_REGULATOR=y
+CONFIG_CMD_EXT2=y
+CONFIG_CMD_EXT4=y
+CONFIG_CMD_EXT4_WRITE=y
+CONFIG_CMD_FAT=y
+CONFIG_OF_CONTROL=y
+CONFIG_SPL_OF_CONTROL=y
+CONFIG_OF_SPL_REMOVE_PROPS="interrupt-parent interrupts"
+CONFIG_ENV_IS_IN_MMC=y
+CONFIG_SYS_RELOC_GD_ENV_ADDR=y
+CONFIG_SYS_MMC_ENV_DEV=2
+CONFIG_SYS_MMC_ENV_PART=2
+CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y
+CONFIG_NET_RANDOM_ETHADDR=y
+CONFIG_SPL_DM=y
+CONFIG_REGMAP=y
+CONFIG_SYSCON=y
+CONFIG_SPL_CLK_COMPOSITE_CCF=y
+CONFIG_CLK_COMPOSITE_CCF=y
+CONFIG_SPL_CLK_IMX8MN=y
+CONFIG_CLK_IMX8MN=y
+CONFIG_USB_FUNCTION_FASTBOOT=y
+CONFIG_FASTBOOT_BUF_ADDR=0x42800000
+CONFIG_FASTBOOT_BUF_SIZE=0x40000000
+CONFIG_FASTBOOT_FLASH=y
+CONFIG_FASTBOOT_FLASH_MMC_DEV=0
+CONFIG_MXC_GPIO=y
+CONFIG_DM_PCA953X=y
+CONFIG_DM_I2C=y
+CONFIG_SYS_I2C_MXC=y
+CONFIG_DM_MMC=y
+CONFIG_SUPPORT_EMMC_BOOT=y
+CONFIG_MMC_IO_VOLTAGE=y
+CONFIG_MMC_UHS_SUPPORT=y
+CONFIG_MMC_HS400_ES_SUPPORT=y
+CONFIG_MMC_HS400_SUPPORT=y
+CONFIG_FSL_USDHC=y
+CONFIG_DM_SPI_FLASH=y
+CONFIG_SF_DEFAULT_MODE=0
+CONFIG_SF_DEFAULT_SPEED=40000000
+CONFIG_SPI_FLASH_BAR=y
+CONFIG_SPI_FLASH_STMICRO=y
+CONFIG_PHYLIB=y
+CONFIG_PHY_ATHEROS=y
+CONFIG_DM_ETH=y
+CONFIG_PHY_GIGE=y
+CONFIG_FEC_MXC=y
+CONFIG_MII=y
+CONFIG_PINCTRL=y
+CONFIG_PINCTRL_IMX8M=y
+CONFIG_DM_PMIC=y
+# CONFIG_SPL_PMIC_CHILDREN is not set
+CONFIG_DM_PMIC_BD71837=y
+CONFIG_DM_REGULATOR=y
+CONFIG_DM_REGULATOR_BD71837=y
+CONFIG_DM_REGULATOR_FIXED=y
+CONFIG_DM_REGULATOR_GPIO=y
+CONFIG_DM_RESET=y
+CONFIG_DM_SERIAL=y
+# CONFIG_SPL_DM_SERIAL is not set
+CONFIG_MXC_UART=y
+CONFIG_SPI=y
+CONFIG_DM_SPI=y
+CONFIG_SYSRESET=y
+CONFIG_SYSRESET_PSCI=y
+CONFIG_DM_THERMAL=y
+CONFIG_USB=y
+CONFIG_DM_USB=y
+# CONFIG_SPL_DM_USB is not set
+CONFIG_USB_EHCI_HCD=y
+CONFIG_USB_GADGET=y
+CONFIG_USB_GADGET_MANUFACTURER="FSL"
+CONFIG_USB_GADGET_VENDOR_NUM=0x0525
+CONFIG_USB_GADGET_PRODUCT_NUM=0xa4a5
+CONFIG_CI_UDC=y
+CONFIG_SDP_LOADADDR=0x0
+CONFIG_OF_LIBFDT_OVERLAY=y
diff --git a/configs/khadas-vim3_defconfig b/configs/khadas-vim3_defconfig
index 5d16652..bc17430 100644
--- a/configs/khadas-vim3_defconfig
+++ b/configs/khadas-vim3_defconfig
@@ -31,6 +31,8 @@
CONFIG_NET_RANDOM_ETHADDR=y
CONFIG_ADC=y
CONFIG_SARADC_MESON=y
+CONFIG_BUTTON=y
+CONFIG_BUTTON_ADC=y
CONFIG_DM_I2C=y
CONFIG_SYS_I2C_MESON=y
CONFIG_DM_MMC=y
diff --git a/configs/khadas-vim3l_defconfig b/configs/khadas-vim3l_defconfig
index 6b13ce0..c187792 100644
--- a/configs/khadas-vim3l_defconfig
+++ b/configs/khadas-vim3l_defconfig
@@ -31,6 +31,8 @@
CONFIG_NET_RANDOM_ETHADDR=y
CONFIG_ADC=y
CONFIG_SARADC_MESON=y
+CONFIG_BUTTON=y
+CONFIG_BUTTON_ADC=y
CONFIG_DM_I2C=y
CONFIG_SYS_I2C_MESON=y
CONFIG_DM_MMC=y
diff --git a/configs/kontron_sl28_defconfig b/configs/kontron_sl28_defconfig
index d567096..1c781e0 100644
--- a/configs/kontron_sl28_defconfig
+++ b/configs/kontron_sl28_defconfig
@@ -79,13 +79,12 @@
# CONFIG_SPI_FLASH_USE_4K_SECTORS is not set
CONFIG_PHYLIB=y
CONFIG_PHY_ATHEROS=y
+CONFIG_PHY_FIXED=y
CONFIG_DM_ETH=y
CONFIG_DM_MDIO=y
+CONFIG_DM_DSA=y
CONFIG_PHY_GIGE=y
CONFIG_E1000=y
-CONFIG_FSL_ENETC=y
-CONFIG_PHY_FIXED=y
-CONFIG_DM_DSA=y
CONFIG_MSCC_FELIX_SWITCH=y
CONFIG_NVME=y
CONFIG_PCI=y
diff --git a/configs/libretech-cc_v2_defconfig b/configs/libretech-cc_v2_defconfig
index 017e81b..86f88db 100644
--- a/configs/libretech-cc_v2_defconfig
+++ b/configs/libretech-cc_v2_defconfig
@@ -31,7 +31,6 @@
CONFIG_SYS_RELOC_GD_ENV_ADDR=y
CONFIG_NET_RANDOM_ETHADDR=y
CONFIG_SARADC_MESON=y
-CONFIG_DM_KEYBOARD=y
CONFIG_DM_MMC=y
CONFIG_MMC_MESON_GX=y
CONFIG_MTD=y
diff --git a/configs/libretech-s905d-pc_defconfig b/configs/libretech-s905d-pc_defconfig
index 9d4c880..85dfd9c 100644
--- a/configs/libretech-s905d-pc_defconfig
+++ b/configs/libretech-s905d-pc_defconfig
@@ -33,7 +33,6 @@
CONFIG_ENV_IS_IN_SPI_FLASH=y
CONFIG_NET_RANDOM_ETHADDR=y
CONFIG_SARADC_MESON=y
-CONFIG_DM_KEYBOARD=y
CONFIG_DM_MMC=y
CONFIG_MMC_MESON_GX=y
CONFIG_MTD=y
diff --git a/configs/libretech-s912-pc_defconfig b/configs/libretech-s912-pc_defconfig
index cf600c1..a515833 100644
--- a/configs/libretech-s912-pc_defconfig
+++ b/configs/libretech-s912-pc_defconfig
@@ -32,7 +32,6 @@
CONFIG_ENV_IS_IN_SPI_FLASH=y
CONFIG_NET_RANDOM_ETHADDR=y
CONFIG_SARADC_MESON=y
-CONFIG_DM_KEYBOARD=y
CONFIG_DM_MMC=y
CONFIG_MMC_MESON_GX=y
CONFIG_MTD=y
diff --git a/configs/ls1028aqds_tfa_SECURE_BOOT_defconfig b/configs/ls1028aqds_tfa_SECURE_BOOT_defconfig
index 93b13b4..a2bc6c6 100644
--- a/configs/ls1028aqds_tfa_SECURE_BOOT_defconfig
+++ b/configs/ls1028aqds_tfa_SECURE_BOOT_defconfig
@@ -56,15 +56,14 @@
CONFIG_PHY_AQUANTIA=y
CONFIG_PHY_ATHEROS=y
CONFIG_PHY_VITESSE=y
+CONFIG_PHY_FIXED=y
CONFIG_DM_ETH=y
CONFIG_DM_MDIO=y
CONFIG_DM_MDIO_MUX=y
-CONFIG_E1000=y
-CONFIG_FSL_ENETC=y
-CONFIG_MDIO_MUX_I2CREG=y
-CONFIG_PHY_FIXED=y
CONFIG_DM_DSA=y
+CONFIG_E1000=y
CONFIG_MSCC_FELIX_SWITCH=y
+CONFIG_MDIO_MUX_I2CREG=y
CONFIG_NVME=y
CONFIG_PCI=y
CONFIG_DM_PCI=y
diff --git a/configs/ls1028aqds_tfa_defconfig b/configs/ls1028aqds_tfa_defconfig
index c915069..66e008b 100644
--- a/configs/ls1028aqds_tfa_defconfig
+++ b/configs/ls1028aqds_tfa_defconfig
@@ -62,15 +62,14 @@
CONFIG_PHY_AQUANTIA=y
CONFIG_PHY_ATHEROS=y
CONFIG_PHY_VITESSE=y
+CONFIG_PHY_FIXED=y
CONFIG_DM_ETH=y
CONFIG_DM_MDIO=y
CONFIG_DM_MDIO_MUX=y
-CONFIG_E1000=y
-CONFIG_FSL_ENETC=y
-CONFIG_MDIO_MUX_I2CREG=y
-CONFIG_PHY_FIXED=y
CONFIG_DM_DSA=y
+CONFIG_E1000=y
CONFIG_MSCC_FELIX_SWITCH=y
+CONFIG_MDIO_MUX_I2CREG=y
CONFIG_NVME=y
CONFIG_PCI=y
CONFIG_DM_PCI=y
diff --git a/configs/ls1028ardb_tfa_SECURE_BOOT_defconfig b/configs/ls1028ardb_tfa_SECURE_BOOT_defconfig
index 45d9f40..dd18918 100644
--- a/configs/ls1028ardb_tfa_SECURE_BOOT_defconfig
+++ b/configs/ls1028ardb_tfa_SECURE_BOOT_defconfig
@@ -54,13 +54,12 @@
CONFIG_PHYLIB=y
CONFIG_PHY_ATHEROS=y
CONFIG_PHY_VITESSE=y
+CONFIG_PHY_FIXED=y
CONFIG_DM_ETH=y
CONFIG_DM_MDIO=y
+CONFIG_DM_DSA=y
CONFIG_PHY_GIGE=y
CONFIG_E1000=y
-CONFIG_FSL_ENETC=y
-CONFIG_PHY_FIXED=y
-CONFIG_DM_DSA=y
CONFIG_MSCC_FELIX_SWITCH=y
CONFIG_NVME=y
CONFIG_PCI=y
diff --git a/configs/ls1028ardb_tfa_defconfig b/configs/ls1028ardb_tfa_defconfig
index cff68a3..9f5116b 100644
--- a/configs/ls1028ardb_tfa_defconfig
+++ b/configs/ls1028ardb_tfa_defconfig
@@ -60,13 +60,12 @@
CONFIG_PHYLIB=y
CONFIG_PHY_ATHEROS=y
CONFIG_PHY_VITESSE=y
+CONFIG_PHY_FIXED=y
CONFIG_DM_ETH=y
CONFIG_DM_MDIO=y
+CONFIG_DM_DSA=y
CONFIG_PHY_GIGE=y
CONFIG_E1000=y
-CONFIG_FSL_ENETC=y
-CONFIG_PHY_FIXED=y
-CONFIG_DM_DSA=y
CONFIG_MSCC_FELIX_SWITCH=y
CONFIG_NVME=y
CONFIG_PCI=y
diff --git a/configs/mt7623n_bpir2_defconfig b/configs/mt7623n_bpir2_defconfig
index d36ff56..fb20cb1 100644
--- a/configs/mt7623n_bpir2_defconfig
+++ b/configs/mt7623n_bpir2_defconfig
@@ -53,3 +53,4 @@
CONFIG_MTK_TIMER=y
CONFIG_WDT_MTK=y
CONFIG_LZMA=y
+# CONFIG_EFI_GRUB_ARM32_WORKAROUND is not set
diff --git a/configs/mvebu_espressobin-88f3720_defconfig b/configs/mvebu_espressobin-88f3720_defconfig
index 4956199..212bc00 100644
--- a/configs/mvebu_espressobin-88f3720_defconfig
+++ b/configs/mvebu_espressobin-88f3720_defconfig
@@ -32,12 +32,14 @@
CONFIG_CMD_PCI=y
CONFIG_CMD_SPI=y
CONFIG_CMD_USB=y
-# CONFIG_CMD_SETEXPR is not set
CONFIG_CMD_TFTPPUT=y
CONFIG_CMD_CACHE=y
CONFIG_CMD_TIME=y
CONFIG_CMD_MVEBU_BUBT=y
+CONFIG_CMD_BTRFS=y
CONFIG_CMD_EXT4_WRITE=y
+CONFIG_CMD_SQUASHFS=y
+CONFIG_CMD_FS_UUID=y
CONFIG_MAC_PARTITION=y
CONFIG_ENV_OVERWRITE=y
CONFIG_ENV_IS_IN_SPI_FLASH=y
@@ -65,6 +67,7 @@
CONFIG_PHY_GIGE=y
CONFIG_E1000=y
CONFIG_MVNETA=y
+CONFIG_NVME=y
CONFIG_PCI=y
CONFIG_DM_PCI=y
CONFIG_PCI_AARDVARK=y
@@ -86,4 +89,3 @@
CONFIG_USB_ETHER_RTL8152=y
CONFIG_USB_ETHER_SMSC95XX=y
CONFIG_SHA1=y
-CONFIG_SHA256=y
diff --git a/configs/mx23evk_defconfig b/configs/mx23evk_defconfig
index 0e3d977..99881f3 100644
--- a/configs/mx23evk_defconfig
+++ b/configs/mx23evk_defconfig
@@ -7,16 +7,19 @@
CONFIG_NR_DRAM_BANKS=1
CONFIG_ENV_SIZE=0x4000
CONFIG_ENV_OFFSET=0x40000
+CONFIG_DM_GPIO=y
CONFIG_SPL_TEXT_BASE=0x00001000
CONFIG_TARGET_MX23EVK=y
CONFIG_SPL_SERIAL_SUPPORT=y
CONFIG_SPL=y
+CONFIG_DEFAULT_DEVICE_TREE="imx23-evk"
CONFIG_SYS_CONSOLE_IS_IN_ENV=y
# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_ARCH_MISC_INIT=y
# CONFIG_SPL_FRAMEWORK is not set
CONFIG_HUSH_PARSER=y
CONFIG_CMD_BOOTZ=y
+CONFIG_CMD_DM=y
CONFIG_CMD_GPIO=y
CONFIG_CMD_MMC=y
CONFIG_CMD_USB=y
@@ -24,17 +27,22 @@
CONFIG_CMD_CACHE=y
CONFIG_CMD_EXT2=y
CONFIG_CMD_FAT=y
+CONFIG_OF_CONTROL=y
CONFIG_ENV_OVERWRITE=y
CONFIG_ENV_IS_IN_MMC=y
CONFIG_SYS_RELOC_GD_ENV_ADDR=y
CONFIG_VERSION_VARIABLE=y
# CONFIG_NET is not set
+CONFIG_DM=y
CONFIG_MXS_GPIO=y
+CONFIG_DM_MMC=y
CONFIG_MMC_MXS=y
+CONFIG_PINCTRL=y
+CONFIG_DM_REGULATOR=y
+CONFIG_DM_REGULATOR_FIXED=y
+CONFIG_DM_REGULATOR_GPIO=y
CONFIG_CONS_INDEX=0
CONFIG_USB=y
+CONFIG_DM_USB=y
CONFIG_USB_EHCI_HCD=y
CONFIG_USB_STORAGE=y
-CONFIG_SPLASH_SCREEN=y
-CONFIG_VIDEO_BMP_GZIP=y
-CONFIG_OF_LIBFDT=y
diff --git a/configs/mx25pdk_defconfig b/configs/mx25pdk_defconfig
deleted file mode 100644
index 58d4244..0000000
--- a/configs/mx25pdk_defconfig
+++ /dev/null
@@ -1,31 +0,0 @@
-CONFIG_ARM=y
-CONFIG_ARCH_MX25=y
-CONFIG_SYS_TEXT_BASE=0x81200000
-CONFIG_NR_DRAM_BANKS=1
-CONFIG_ENV_SIZE=0x2000
-CONFIG_ENV_OFFSET=0x60000
-CONFIG_TARGET_MX25PDK=y
-CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/freescale/mx25pdk/imximage.cfg"
-CONFIG_DEFAULT_FDT_FILE="imx25-pdk.dtb"
-CONFIG_HUSH_PARSER=y
-CONFIG_CMD_BOOTZ=y
-CONFIG_CMD_FUSE=y
-CONFIG_CMD_I2C=y
-CONFIG_CMD_MMC=y
-# CONFIG_CMD_SETEXPR is not set
-CONFIG_CMD_DHCP=y
-CONFIG_CMD_MII=y
-CONFIG_CMD_PING=y
-CONFIG_CMD_CACHE=y
-CONFIG_CMD_DATE=y
-CONFIG_CMD_FS_GENERIC=y
-CONFIG_DOS_PARTITION=y
-CONFIG_ENV_OVERWRITE=y
-CONFIG_ENV_IS_IN_MMC=y
-CONFIG_SYS_RELOC_GD_ENV_ADDR=y
-CONFIG_FSL_ESDHC_IMX=y
-CONFIG_MII=y
-CONFIG_MXC_UART=y
-CONFIG_FS_EXT4=y
-CONFIG_FS_FAT=y
-CONFIG_OF_LIBFDT=y
diff --git a/configs/mx51evk_defconfig b/configs/mx51evk_defconfig
index 343816f..557a1b5 100644
--- a/configs/mx51evk_defconfig
+++ b/configs/mx51evk_defconfig
@@ -5,15 +5,19 @@
CONFIG_ENV_SIZE=0x2000
CONFIG_ENV_OFFSET=0xC0000
CONFIG_TARGET_MX51EVK=y
+CONFIG_DM_GPIO=y
# CONFIG_CMD_BMODE is not set
+CONFIG_DEFAULT_DEVICE_TREE="imx51-babbage"
CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/freescale/mx51evk/imximage.cfg"
CONFIG_USE_PREBOOT=y
CONFIG_SYS_CONSOLE_IS_IN_ENV=y
CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE=y
CONFIG_HUSH_PARSER=y
CONFIG_CMD_BOOTZ=y
+CONFIG_CMD_DM=y
CONFIG_CMD_FUSE=y
CONFIG_CMD_MMC=y
+# CONFIG_CMD_PINMUX is not set
CONFIG_CMD_SPI=y
CONFIG_CMD_USB=y
# CONFIG_CMD_SETEXPR is not set
@@ -22,16 +26,30 @@
CONFIG_CMD_PING=y
CONFIG_CMD_DATE=y
CONFIG_CMD_FAT=y
+CONFIG_OF_CONTROL=y
CONFIG_ENV_OVERWRITE=y
CONFIG_ENV_IS_IN_MMC=y
CONFIG_SYS_RELOC_GD_ENV_ADDR=y
+CONFIG_DM=y
+CONFIG_DM_MMC=y
CONFIG_FSL_ESDHC_IMX=y
CONFIG_MTD=y
+CONFIG_PHYLIB=y
+CONFIG_PHY_SMSC=y
+CONFIG_PHY_FIXED=y
+CONFIG_DM_ETH=y
+CONFIG_FEC_MXC=y
CONFIG_MII=y
+CONFIG_PINCTRL=y
+CONFIG_PINCTRL_IMX5=y
+CONFIG_DM_REGULATOR=y
+CONFIG_DM_REGULATOR_FIXED=y
+CONFIG_DM_REGULATOR_GPIO=y
CONFIG_MXC_UART=y
CONFIG_SPI=y
CONFIG_MXC_SPI=y
CONFIG_USB=y
+CONFIG_DM_USB=y
CONFIG_USB_EHCI_MX5=y
CONFIG_USB_STORAGE=y
CONFIG_USB_HOST_ETHER=y
@@ -39,4 +57,3 @@
CONFIG_USB_ETHER_SMSC95XX=y
CONFIG_SYS_WHITE_ON_BLACK=y
CONFIG_SPLASH_SCREEN=y
-CONFIG_OF_LIBFDT=y
diff --git a/configs/mx53ard_defconfig b/configs/mx53ard_defconfig
deleted file mode 100644
index 7ccd40e..0000000
--- a/configs/mx53ard_defconfig
+++ /dev/null
@@ -1,31 +0,0 @@
-CONFIG_ARM=y
-CONFIG_ARCH_MX5=y
-CONFIG_SYS_TEXT_BASE=0x77800000
-CONFIG_NR_DRAM_BANKS=2
-CONFIG_ENV_SIZE=0x2000
-CONFIG_ENV_OFFSET=0x60000
-CONFIG_TARGET_MX53ARD=y
-# CONFIG_CMD_BMODE is not set
-CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/freescale/mx53ard/imximage_dd3.cfg"
-CONFIG_DEFAULT_FDT_FILE="imx53-ard.dtb"
-CONFIG_HUSH_PARSER=y
-CONFIG_CMD_BOOTZ=y
-CONFIG_CMD_I2C=y
-CONFIG_CMD_MMC=y
-CONFIG_CMD_DHCP=y
-CONFIG_CMD_MII=y
-CONFIG_CMD_PING=y
-CONFIG_CMD_FAT=y
-CONFIG_ENV_OVERWRITE=y
-CONFIG_ENV_IS_IN_MMC=y
-CONFIG_SYS_RELOC_GD_ENV_ADDR=y
-CONFIG_FSL_ESDHC_IMX=y
-CONFIG_MTD=y
-CONFIG_MTD_RAW_NAND=y
-CONFIG_SYS_NAND_USE_FLASH_BBT=y
-CONFIG_NAND_MXC=y
-CONFIG_MII=y
-CONFIG_SMC911X=y
-CONFIG_SMC911X_BASE=0xF4000000
-CONFIG_MXC_UART=y
-CONFIG_OF_LIBFDT=y
diff --git a/configs/mx53loco_defconfig b/configs/mx53loco_defconfig
index a1096a7..2828889 100644
--- a/configs/mx53loco_defconfig
+++ b/configs/mx53loco_defconfig
@@ -1,11 +1,14 @@
CONFIG_ARM=y
CONFIG_ARCH_MX5=y
CONFIG_SYS_TEXT_BASE=0x77800000
+CONFIG_SYS_MALLOC_F_LEN=0x8000
CONFIG_NR_DRAM_BANKS=2
CONFIG_ENV_SIZE=0x2000
CONFIG_ENV_OFFSET=0xC0000
CONFIG_TARGET_MX53LOCO=y
+CONFIG_DM_GPIO=y
# CONFIG_CMD_BMODE is not set
+CONFIG_DEFAULT_DEVICE_TREE="imx53-qsb"
CONFIG_SUPPORT_RAW_INITRD=y
CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/freescale/mx53loco/imximage.cfg"
CONFIG_USE_PREBOOT=y
@@ -13,8 +16,9 @@
CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE=y
CONFIG_HUSH_PARSER=y
CONFIG_CMD_BOOTZ=y
+CONFIG_CMD_DM=y
CONFIG_CMD_MMC=y
-CONFIG_CMD_SATA=y
+# CONFIG_CMD_PINMUX is not set
CONFIG_CMD_USB=y
# CONFIG_CMD_SETEXPR is not set
CONFIG_CMD_DHCP=y
@@ -23,15 +27,28 @@
CONFIG_CMD_EXT2=y
CONFIG_CMD_FAT=y
CONFIG_CMD_FS_GENERIC=y
+CONFIG_OF_CONTROL=y
CONFIG_ENV_OVERWRITE=y
CONFIG_ENV_IS_IN_MMC=y
CONFIG_SYS_RELOC_GD_ENV_ADDR=y
-CONFIG_DWC_AHSATA=y
+CONFIG_DM=y
+CONFIG_DM_MMC=y
CONFIG_FSL_ESDHC_IMX=y
CONFIG_MTD=y
+CONFIG_PHYLIB=y
+CONFIG_PHY_SMSC=y
+CONFIG_PHY_FIXED=y
+CONFIG_DM_ETH=y
+CONFIG_FEC_MXC=y
CONFIG_MII=y
+CONFIG_PINCTRL=y
+CONFIG_PINCTRL_IMX5=y
+CONFIG_DM_REGULATOR=y
+CONFIG_DM_REGULATOR_FIXED=y
+CONFIG_DM_REGULATOR_GPIO=y
CONFIG_MXC_UART=y
CONFIG_USB=y
+CONFIG_DM_USB=y
CONFIG_USB_EHCI_MX5=y
CONFIG_USB_STORAGE=y
CONFIG_USB_HOST_ETHER=y
@@ -40,4 +57,3 @@
CONFIG_USB_ETHER_SMSC95XX=y
CONFIG_SYS_WHITE_ON_BLACK=y
CONFIG_SPLASH_SCREEN=y
-CONFIG_OF_LIBFDT=y
diff --git a/configs/mx53smd_defconfig b/configs/mx53smd_defconfig
deleted file mode 100644
index 0513bf5..0000000
--- a/configs/mx53smd_defconfig
+++ /dev/null
@@ -1,25 +0,0 @@
-CONFIG_ARM=y
-CONFIG_ARCH_MX5=y
-CONFIG_SYS_TEXT_BASE=0x77800000
-CONFIG_NR_DRAM_BANKS=2
-CONFIG_ENV_SIZE=0x2000
-CONFIG_ENV_OFFSET=0x60000
-CONFIG_TARGET_MX53SMD=y
-# CONFIG_CMD_BMODE is not set
-CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/freescale/mx53smd/imximage.cfg"
-CONFIG_HUSH_PARSER=y
-CONFIG_CMD_I2C=y
-CONFIG_CMD_MMC=y
-# CONFIG_CMD_SETEXPR is not set
-CONFIG_CMD_DHCP=y
-CONFIG_CMD_MII=y
-CONFIG_CMD_PING=y
-CONFIG_CMD_FAT=y
-CONFIG_ENV_OVERWRITE=y
-CONFIG_ENV_IS_IN_MMC=y
-CONFIG_SYS_RELOC_GD_ENV_ADDR=y
-CONFIG_FSL_ESDHC_IMX=y
-CONFIG_MTD=y
-CONFIG_MII=y
-CONFIG_MXC_UART=y
-CONFIG_OF_LIBFDT=y
diff --git a/configs/mx6sabreauto_defconfig b/configs/mx6sabreauto_defconfig
index 4faf49e..4f4e7ac 100644
--- a/configs/mx6sabreauto_defconfig
+++ b/configs/mx6sabreauto_defconfig
@@ -27,6 +27,7 @@
# CONFIG_CONSOLE_MUX is not set
CONFIG_SYS_CONSOLE_IS_IN_ENV=y
CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE=y
+CONFIG_SPL_LEGACY_IMAGE_SUPPORT=y
CONFIG_SPL_SEPARATE_BSS=y
CONFIG_SPL_FIT_IMAGE_TINY=y
CONFIG_SPL_FS_EXT4=y
diff --git a/configs/mx6sabresd_defconfig b/configs/mx6sabresd_defconfig
index 0016fba..e527533 100644
--- a/configs/mx6sabresd_defconfig
+++ b/configs/mx6sabresd_defconfig
@@ -26,6 +26,7 @@
# CONFIG_CONSOLE_MUX is not set
CONFIG_SYS_CONSOLE_IS_IN_ENV=y
CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE=y
+CONFIG_SPL_LEGACY_IMAGE_SUPPORT=y
CONFIG_SPL_SEPARATE_BSS=y
CONFIG_SPL_FIT_IMAGE_TINY=y
CONFIG_SPL_USB_HOST_SUPPORT=y
diff --git a/configs/nokia_rx51_defconfig b/configs/nokia_rx51_defconfig
index 9744d1c..312ca3a 100644
--- a/configs/nokia_rx51_defconfig
+++ b/configs/nokia_rx51_defconfig
@@ -4,6 +4,7 @@
CONFIG_SYS_TEXT_BASE=0x80008000
CONFIG_NR_DRAM_BANKS=2
CONFIG_TARGET_NOKIA_RX51=y
+CONFIG_OPTIMIZE_INLINING=y
# CONFIG_SYS_MALLOC_F is not set
# CONFIG_FIT is not set
CONFIG_BOOTDELAY=30
@@ -12,10 +13,10 @@
CONFIG_USE_PREBOOT=y
CONFIG_PREBOOT="run preboot"
CONFIG_CONSOLE_MUX=y
+# CONFIG_SYS_DEVICE_NULLDEV is not set
CONFIG_HUSH_PARSER=y
CONFIG_SYS_PROMPT="Nokia RX-51 # "
# CONFIG_CMD_BDI is not set
-# CONFIG_CMD_BOOTD is not set
# CONFIG_BOOTM_NETBSD is not set
# CONFIG_BOOTM_PLAN9 is not set
# CONFIG_BOOTM_RTEMS is not set
@@ -46,9 +47,11 @@
CONFIG_SYS_RELOC_GD_ENV_ADDR=y
# CONFIG_NET is not set
CONFIG_DM=y
+# CONFIG_DM_WARN is not set
# CONFIG_DM_DEVICE_REMOVE is not set
+# CONFIG_DM_SEQ_ALIAS is not set
+# CONFIG_BLOCK_CACHE is not set
CONFIG_DM_I2C=y
-CONFIG_TWL4030_LED=y
CONFIG_DM_MMC=y
# CONFIG_MMC_HW_PARTITIONING is not set
# CONFIG_MMC_VERBOSE is not set
@@ -58,10 +61,8 @@
CONFIG_SYS_NS16550=y
CONFIG_SPI=y
CONFIG_USB=y
-CONFIG_USB_MUSB_HCD=y
CONFIG_USB_MUSB_UDC=y
CONFIG_USB_OMAP3=y
-CONFIG_TWL4030_USB=y
CONFIG_CFB_CONSOLE=y
CONFIG_CFB_CONSOLE_ANSI=y
# CONFIG_VGA_AS_SINGLE_DEVICE is not set
diff --git a/configs/omap35_logic_defconfig b/configs/omap35_logic_defconfig
index ec0ba11..fa751e3 100644
--- a/configs/omap35_logic_defconfig
+++ b/configs/omap35_logic_defconfig
@@ -19,6 +19,7 @@
CONFIG_PREBOOT="setenv preboot;saveenv;"
CONFIG_DEFAULT_FDT_FILE="logicpd-torpedo-35xx-devkit.dtb"
CONFIG_SYS_CONSOLE_INFO_QUIET=y
+CONFIG_SPL_ALLOC_BD=y
CONFIG_SPL_SYS_MALLOC_SIMPLE=y
CONFIG_SPL_SEPARATE_BSS=y
# CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR is not set
diff --git a/configs/omap35_logic_somlv_defconfig b/configs/omap35_logic_somlv_defconfig
index 3c9f002..e6655c7 100644
--- a/configs/omap35_logic_somlv_defconfig
+++ b/configs/omap35_logic_somlv_defconfig
@@ -18,6 +18,7 @@
CONFIG_PREBOOT="setenv preboot;saveenv;"
CONFIG_DEFAULT_FDT_FILE="logicpd-som-lv-35xx-devkit.dtb"
CONFIG_SYS_CONSOLE_INFO_QUIET=y
+CONFIG_SPL_ALLOC_BD=y
CONFIG_SPL_SYS_MALLOC_SIMPLE=y
CONFIG_SPL_SEPARATE_BSS=y
# CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR is not set
diff --git a/configs/omap3_logic_defconfig b/configs/omap3_logic_defconfig
index 4e37237..5414880 100644
--- a/configs/omap3_logic_defconfig
+++ b/configs/omap3_logic_defconfig
@@ -18,6 +18,7 @@
CONFIG_USE_PREBOOT=y
CONFIG_PREBOOT="setenv preboot;saveenv;"
CONFIG_SYS_CONSOLE_INFO_QUIET=y
+CONFIG_SPL_ALLOC_BD=y
CONFIG_SPL_SYS_MALLOC_SIMPLE=y
CONFIG_SPL_SEPARATE_BSS=y
# CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR is not set
diff --git a/configs/omap3_logic_somlv_defconfig b/configs/omap3_logic_somlv_defconfig
index 5947f4b..3edd6d1 100644
--- a/configs/omap3_logic_somlv_defconfig
+++ b/configs/omap3_logic_somlv_defconfig
@@ -19,6 +19,7 @@
CONFIG_PREBOOT="setenv preboot;saveenv;"
CONFIG_DEFAULT_FDT_FILE="logicpd-som-lv-37xx-devkit.dtb"
CONFIG_SYS_CONSOLE_INFO_QUIET=y
+CONFIG_SPL_ALLOC_BD=y
CONFIG_SPL_SYS_MALLOC_SIMPLE=y
CONFIG_SPL_SEPARATE_BSS=y
# CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR is not set
diff --git a/configs/pinebook-pro-rk3399_defconfig b/configs/pinebook-pro-rk3399_defconfig
index a471c3e..c4bab29 100644
--- a/configs/pinebook-pro-rk3399_defconfig
+++ b/configs/pinebook-pro-rk3399_defconfig
@@ -40,7 +40,6 @@
CONFIG_SPL_DM_SEQ_ALIAS=y
CONFIG_ROCKCHIP_GPIO=y
CONFIG_SYS_I2C_ROCKCHIP=y
-CONFIG_DM_KEYBOARD=y
CONFIG_LED=y
CONFIG_LED_GPIO=y
CONFIG_MISC=y
diff --git a/configs/qemu-ppce500_defconfig b/configs/qemu-ppce500_defconfig
index d17c556..536fe7d 100644
--- a/configs/qemu-ppce500_defconfig
+++ b/configs/qemu-ppce500_defconfig
@@ -6,28 +6,47 @@
CONFIG_TARGET_QEMU_PPCE500=y
CONFIG_FIT=y
CONFIG_FIT_VERBOSE=y
-CONFIG_OF_BOARD_SETUP=y
CONFIG_OF_STDOUT_VIA_ALIAS=y
CONFIG_BOOTDELAY=1
# CONFIG_DISPLAY_BOARDINFO is not set
-CONFIG_BOARD_EARLY_INIT_F=y
CONFIG_LAST_STAGE_INIT=y
-# CONFIG_MISC_INIT_R is not set
CONFIG_HUSH_PARSER=y
CONFIG_CMD_REGINFO=y
CONFIG_CMD_BOOTZ=y
CONFIG_CMD_GREPENV=y
+CONFIG_CMD_DM=y
+CONFIG_CMD_GPIO=y
CONFIG_CMD_PCI=y
+CONFIG_CMD_POWEROFF=y
CONFIG_CMD_DHCP=y
CONFIG_CMD_PING=y
# CONFIG_CMD_HASH is not set
CONFIG_CMD_EXT2=y
CONFIG_DOS_PARTITION=y
+CONFIG_OF_CONTROL=y
+CONFIG_OF_BOARD=y
CONFIG_ENV_OVERWRITE=y
CONFIG_SYS_RELOC_GD_ENV_ADDR=y
+CONFIG_DM=y
+CONFIG_BLK=y
+CONFIG_HAVE_BLOCK_DEVICE=y
+CONFIG_MPC8XXX_GPIO=y
+CONFIG_DM_I2C=y
+CONFIG_SYS_I2C_FSL=y
# CONFIG_MMC is not set
+CONFIG_DM_ETH=y
CONFIG_E1000=y
+CONFIG_DM_PCI=y
+CONFIG_PCI_MPC85XX=y
+CONFIG_DM_RTC=y
+CONFIG_DM_SERIAL=y
CONFIG_SYS_NS16550=y
+CONFIG_SYSRESET=y
+# CONFIG_SYSRESET_CMD_RESET is not set
+CONFIG_SYSRESET_CMD_POWEROFF=y
+CONFIG_POWEROFF_GPIO=y
+CONFIG_VIRTIO_PCI=y
+CONFIG_VIRTIO_NET=y
+CONFIG_VIRTIO_BLK=y
CONFIG_ADDR_MAP=y
CONFIG_PANIC_HANG=y
-CONFIG_OF_LIBFDT=y
diff --git a/configs/rock960-rk3399_defconfig b/configs/rock960-rk3399_defconfig
index 56ebaeb..28d1fc5 100644
--- a/configs/rock960-rk3399_defconfig
+++ b/configs/rock960-rk3399_defconfig
@@ -33,7 +33,6 @@
CONFIG_SYS_MMC_ENV_DEV=1
CONFIG_ROCKCHIP_GPIO=y
CONFIG_SYS_I2C_ROCKCHIP=y
-CONFIG_DM_KEYBOARD=y
CONFIG_MMC_DW=y
CONFIG_MMC_DW_ROCKCHIP=y
CONFIG_MMC_SDHCI=y
diff --git a/configs/rockpro64-rk3399_defconfig b/configs/rockpro64-rk3399_defconfig
index 1d4f544..e9a01ec 100644
--- a/configs/rockpro64-rk3399_defconfig
+++ b/configs/rockpro64-rk3399_defconfig
@@ -35,7 +35,6 @@
CONFIG_SPL_DM_SEQ_ALIAS=y
CONFIG_ROCKCHIP_GPIO=y
CONFIG_SYS_I2C_ROCKCHIP=y
-CONFIG_DM_KEYBOARD=y
CONFIG_MISC=y
CONFIG_ROCKCHIP_EFUSE=y
CONFIG_MMC_DW=y
diff --git a/configs/rpi_0_w_defconfig b/configs/rpi_0_w_defconfig
index 93d790a..0156599 100644
--- a/configs/rpi_0_w_defconfig
+++ b/configs/rpi_0_w_defconfig
@@ -21,7 +21,6 @@
CONFIG_ENV_FAT_DEVICE_AND_PART="0:1"
CONFIG_SYS_RELOC_GD_ENV_ADDR=y
CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y
-CONFIG_DM_KEYBOARD=y
CONFIG_DM_MMC=y
CONFIG_MMC_SDHCI=y
CONFIG_MMC_SDHCI_BCM2835=y
diff --git a/configs/rpi_2_defconfig b/configs/rpi_2_defconfig
index 33f27cf..1ad0626 100644
--- a/configs/rpi_2_defconfig
+++ b/configs/rpi_2_defconfig
@@ -21,7 +21,6 @@
CONFIG_ENV_FAT_DEVICE_AND_PART="0:1"
CONFIG_SYS_RELOC_GD_ENV_ADDR=y
CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y
-CONFIG_DM_KEYBOARD=y
CONFIG_DM_MMC=y
CONFIG_MMC_SDHCI=y
CONFIG_MMC_SDHCI_BCM2835=y
@@ -42,3 +41,4 @@
CONFIG_CONSOLE_SCROLL_LINES=10
CONFIG_PHYS_TO_BUS=y
CONFIG_OF_LIBFDT_OVERLAY=y
+# CONFIG_EFI_GRUB_ARM32_WORKAROUND is not set
diff --git a/configs/rpi_3_32b_defconfig b/configs/rpi_3_32b_defconfig
index cdc67cb..a14d7ee 100644
--- a/configs/rpi_3_32b_defconfig
+++ b/configs/rpi_3_32b_defconfig
@@ -22,7 +22,6 @@
CONFIG_ENV_FAT_DEVICE_AND_PART="0:1"
CONFIG_SYS_RELOC_GD_ENV_ADDR=y
CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y
-CONFIG_DM_KEYBOARD=y
CONFIG_DM_MMC=y
CONFIG_MMC_SDHCI=y
CONFIG_MMC_SDHCI_BCM2835=y
diff --git a/configs/rpi_3_b_plus_defconfig b/configs/rpi_3_b_plus_defconfig
index 1321ee6..ebab0b4 100644
--- a/configs/rpi_3_b_plus_defconfig
+++ b/configs/rpi_3_b_plus_defconfig
@@ -22,7 +22,6 @@
CONFIG_ENV_FAT_DEVICE_AND_PART="0:1"
CONFIG_SYS_RELOC_GD_ENV_ADDR=y
CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y
-CONFIG_DM_KEYBOARD=y
CONFIG_DM_MMC=y
CONFIG_MMC_SDHCI=y
CONFIG_MMC_SDHCI_BCM2835=y
diff --git a/configs/rpi_3_defconfig b/configs/rpi_3_defconfig
index 7075d39..4aedfb1 100644
--- a/configs/rpi_3_defconfig
+++ b/configs/rpi_3_defconfig
@@ -22,7 +22,6 @@
CONFIG_ENV_FAT_DEVICE_AND_PART="0:1"
CONFIG_SYS_RELOC_GD_ENV_ADDR=y
CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y
-CONFIG_DM_KEYBOARD=y
CONFIG_DM_MMC=y
CONFIG_MMC_SDHCI=y
CONFIG_MMC_SDHCI_BCM2835=y
diff --git a/configs/rpi_4_32b_defconfig b/configs/rpi_4_32b_defconfig
index 0a5d3ff..0cbdd5f 100644
--- a/configs/rpi_4_32b_defconfig
+++ b/configs/rpi_4_32b_defconfig
@@ -24,7 +24,6 @@
CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y
CONFIG_DM_DMA=y
CONFIG_DFU_MMC=y
-CONFIG_DM_KEYBOARD=y
CONFIG_DM_MMC=y
CONFIG_MMC_SDHCI=y
CONFIG_MMC_SDHCI_SDMA=y
@@ -37,6 +36,8 @@
CONFIG_PINCTRL=y
# CONFIG_PINCTRL_GENERIC is not set
CONFIG_DM_RESET=y
+CONFIG_DM_RNG=y
+CONFIG_RNG_IPROC200=y
# CONFIG_REQUIRE_SERIAL_CONSOLE is not set
CONFIG_USB=y
CONFIG_DM_USB=y
diff --git a/configs/rpi_4_defconfig b/configs/rpi_4_defconfig
index cb6ee77..3f21f99 100644
--- a/configs/rpi_4_defconfig
+++ b/configs/rpi_4_defconfig
@@ -24,7 +24,6 @@
CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y
CONFIG_DM_DMA=y
CONFIG_DFU_MMC=y
-CONFIG_DM_KEYBOARD=y
CONFIG_DM_MMC=y
CONFIG_MMC_SDHCI=y
CONFIG_MMC_SDHCI_SDMA=y
diff --git a/configs/rpi_arm64_defconfig b/configs/rpi_arm64_defconfig
index 4d69026..d282d50 100644
--- a/configs/rpi_arm64_defconfig
+++ b/configs/rpi_arm64_defconfig
@@ -21,7 +21,6 @@
CONFIG_ENV_FAT_DEVICE_AND_PART="0:1"
CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y
CONFIG_DM_DMA=y
-CONFIG_DM_KEYBOARD=y
CONFIG_DM_MMC=y
CONFIG_MMC_SDHCI=y
CONFIG_MMC_SDHCI_SDMA=y
diff --git a/configs/rpi_defconfig b/configs/rpi_defconfig
index bba36ca..7863810 100644
--- a/configs/rpi_defconfig
+++ b/configs/rpi_defconfig
@@ -21,7 +21,6 @@
CONFIG_ENV_FAT_DEVICE_AND_PART="0:1"
CONFIG_SYS_RELOC_GD_ENV_ADDR=y
CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y
-CONFIG_DM_KEYBOARD=y
CONFIG_DM_MMC=y
CONFIG_MMC_SDHCI=y
CONFIG_MMC_SDHCI_BCM2835=y
diff --git a/configs/sandbox64_defconfig b/configs/sandbox64_defconfig
index 634c195..cfda834 100644
--- a/configs/sandbox64_defconfig
+++ b/configs/sandbox64_defconfig
@@ -111,6 +111,8 @@
CONFIG_DM_DEMO_SIMPLE=y
CONFIG_DM_DEMO_SHAPE=y
CONFIG_DFU_SF=y
+CONFIG_FASTBOOT_FLASH=y
+CONFIG_FASTBOOT_FLASH_MMC_DEV=0
CONFIG_GPIO_HOG=y
CONFIG_DM_GPIO_LOOKUP_LABEL=y
CONFIG_PM8916_GPIO=y
diff --git a/configs/sandbox_defconfig b/configs/sandbox_defconfig
index fc1df31..5bc90d0 100644
--- a/configs/sandbox_defconfig
+++ b/configs/sandbox_defconfig
@@ -123,6 +123,7 @@
CONFIG_DM_BOOTCOUNT_RTC=y
CONFIG_DM_BOOTCOUNT_I2C_EEPROM=y
CONFIG_BUTTON=y
+CONFIG_BUTTON_ADC=y
CONFIG_BUTTON_GPIO=y
CONFIG_CLK=y
CONFIG_CLK_COMPOSITE_CCF=y
@@ -136,6 +137,8 @@
CONFIG_DMA=y
CONFIG_DMA_CHANNELS=y
CONFIG_SANDBOX_DMA=y
+CONFIG_FASTBOOT_FLASH=y
+CONFIG_FASTBOOT_FLASH_MMC_DEV=0
CONFIG_GPIO_HOG=y
CONFIG_DM_GPIO_LOOKUP_LABEL=y
CONFIG_PM8916_GPIO=y
diff --git a/configs/sksimx6_defconfig b/configs/sksimx6_defconfig
deleted file mode 100644
index 9b37061..0000000
--- a/configs/sksimx6_defconfig
+++ /dev/null
@@ -1,53 +0,0 @@
-CONFIG_ARM=y
-CONFIG_ARCH_MX6=y
-CONFIG_SYS_TEXT_BASE=0x17800000
-CONFIG_SPL_GPIO_SUPPORT=y
-CONFIG_SPL_LIBCOMMON_SUPPORT=y
-CONFIG_SPL_LIBGENERIC_SUPPORT=y
-CONFIG_NR_DRAM_BANKS=1
-CONFIG_ENV_SIZE=0x4000
-CONFIG_ENV_OFFSET=0x60000
-CONFIG_MX6QDL=y
-CONFIG_MX6_DDRCAL=y
-CONFIG_TARGET_SKSIMX6=y
-CONFIG_SPL_TEXT_BASE=0x00908000
-CONFIG_SPL_MMC_SUPPORT=y
-CONFIG_SPL_SERIAL_SUPPORT=y
-CONFIG_SPL=y
-CONFIG_ENV_OFFSET_REDUND=0x64000
-CONFIG_SPL_LIBDISK_SUPPORT=y
-CONFIG_DISTRO_DEFAULTS=y
-CONFIG_FIT=y
-CONFIG_FIT_VERBOSE=y
-CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=arch/arm/mach-imx/spl_sd.cfg"
-CONFIG_BOOTDELAY=1
-# CONFIG_USE_BOOTCOMMAND is not set
-CONFIG_SILENT_CONSOLE=y
-CONFIG_SILENT_U_BOOT_ONLY=y
-CONFIG_BOARD_EARLY_INIT_F=y
-CONFIG_SPL_FS_EXT4=y
-CONFIG_SPL_I2C_SUPPORT=y
-CONFIG_SPL_WATCHDOG_SUPPORT=y
-CONFIG_CMD_GPIO=y
-CONFIG_CMD_MMC=y
-CONFIG_CMD_CACHE=y
-CONFIG_CMD_EXT4_WRITE=y
-CONFIG_ENV_OVERWRITE=y
-CONFIG_ENV_IS_IN_MMC=y
-CONFIG_SYS_REDUNDAND_ENVIRONMENT=y
-CONFIG_SYS_RELOC_GD_ENV_ADDR=y
-CONFIG_VERSION_VARIABLE=y
-CONFIG_DM=y
-CONFIG_BOUNCE_BUFFER=y
-CONFIG_FSL_USDHC=y
-CONFIG_MTD=y
-CONFIG_PHYLIB=y
-CONFIG_PHY_MICREL=y
-CONFIG_PHY_MICREL_KSZ90X1=y
-CONFIG_PHY_MICREL_KSZ8XXX=y
-CONFIG_FEC_MXC=y
-CONFIG_MII=y
-CONFIG_MXC_UART=y
-CONFIG_DM_THERMAL=y
-CONFIG_IMX_THERMAL=y
-CONFIG_OF_LIBFDT=y
diff --git a/configs/socfpga_agilex_atf_defconfig b/configs/socfpga_agilex_atf_defconfig
index ebe6ce6..7adda02 100644
--- a/configs/socfpga_agilex_atf_defconfig
+++ b/configs/socfpga_agilex_atf_defconfig
@@ -20,6 +20,8 @@
CONFIG_BOOTDELAY=5
CONFIG_USE_BOOTARGS=y
CONFIG_BOOTARGS="earlycon"
+CONFIG_USE_BOOTCOMMAND=y
+CONFIG_BOOTCOMMAND="run fatscript; run mmcfitload; run linux_qspi_enable; run mmcfitboot"
CONFIG_SPL_CACHE=y
CONFIG_SPL_SPI_LOAD=y
CONFIG_SPL_ATF=y
diff --git a/configs/socfpga_agilex_defconfig b/configs/socfpga_agilex_defconfig
index 230d3c2..3d5d39f 100644
--- a/configs/socfpga_agilex_defconfig
+++ b/configs/socfpga_agilex_defconfig
@@ -18,6 +18,8 @@
CONFIG_BOOTDELAY=5
CONFIG_USE_BOOTARGS=y
CONFIG_BOOTARGS="earlycon"
+CONFIG_USE_BOOTCOMMAND=y
+CONFIG_BOOTCOMMAND="run fatscript; run mmcload; run linux_qspi_enable; run mmcboot"
CONFIG_SPL_CACHE=y
CONFIG_SPL_SPI_LOAD=y
CONFIG_HUSH_PARSER=y
diff --git a/configs/socfpga_agilex_vab_defconfig b/configs/socfpga_agilex_vab_defconfig
new file mode 100644
index 0000000..bca663e
--- /dev/null
+++ b/configs/socfpga_agilex_vab_defconfig
@@ -0,0 +1,75 @@
+CONFIG_ARM=y
+CONFIG_SPL_LDSCRIPT="arch/arm/mach-socfpga/u-boot-spl-soc64.lds"
+CONFIG_ARCH_SOCFPGA=y
+CONFIG_SYS_TEXT_BASE=0x200000
+CONFIG_SYS_MALLOC_F_LEN=0x2000
+CONFIG_NR_DRAM_BANKS=2
+CONFIG_ENV_SIZE=0x1000
+CONFIG_ENV_OFFSET=0x200
+CONFIG_SYS_SPI_U_BOOT_OFFS=0x02000000
+CONFIG_DM_GPIO=y
+CONFIG_SPL_TEXT_BASE=0xFFE00000
+CONFIG_SOCFPGA_SECURE_VAB_AUTH=y
+CONFIG_TARGET_SOCFPGA_AGILEX_SOCDK=y
+CONFIG_IDENT_STRING="socfpga_agilex"
+CONFIG_SPL_FS_FAT=y
+CONFIG_DEFAULT_DEVICE_TREE="socfpga_agilex_socdk"
+CONFIG_FIT=y
+CONFIG_SPL_LOAD_FIT=y
+CONFIG_SPL_LOAD_FIT_ADDRESS=0x02000000
+# CONFIG_USE_SPL_FIT_GENERATOR is not set
+# CONFIG_LEGACY_IMAGE_FORMAT is not set
+CONFIG_BOOTDELAY=5
+CONFIG_USE_BOOTARGS=y
+CONFIG_BOOTARGS="earlycon"
+CONFIG_USE_BOOTCOMMAND=y
+CONFIG_BOOTCOMMAND="run fatscript; run mmcfitload; run mmcfitboot"
+CONFIG_SPL_CACHE=y
+CONFIG_SPL_SPI_LOAD=y
+CONFIG_SPL_ATF=y
+CONFIG_SPL_ATF_NO_PLATFORM_PARAM=y
+CONFIG_HUSH_PARSER=y
+CONFIG_SYS_PROMPT="SOCFPGA_AGILEX # "
+CONFIG_CMD_MEMTEST=y
+CONFIG_CMD_GPIO=y
+CONFIG_CMD_I2C=y
+CONFIG_CMD_MMC=y
+CONFIG_CMD_SPI=y
+CONFIG_CMD_USB=y
+CONFIG_CMD_DHCP=y
+CONFIG_CMD_MII=y
+CONFIG_CMD_PING=y
+CONFIG_CMD_CACHE=y
+CONFIG_CMD_EXT4=y
+CONFIG_CMD_FAT=y
+CONFIG_CMD_FS_GENERIC=y
+CONFIG_ENV_IS_IN_MMC=y
+CONFIG_NET_RANDOM_ETHADDR=y
+CONFIG_SPL_DM_SEQ_ALIAS=y
+CONFIG_SPL_ALTERA_SDRAM=y
+CONFIG_DWAPB_GPIO=y
+CONFIG_DM_I2C=y
+CONFIG_SYS_I2C_DW=y
+CONFIG_DM_MMC=y
+CONFIG_MMC_DW=y
+CONFIG_MTD=y
+CONFIG_SF_DEFAULT_MODE=0x2003
+CONFIG_SPI_FLASH_SPANSION=y
+CONFIG_SPI_FLASH_STMICRO=y
+CONFIG_PHY_MICREL=y
+CONFIG_PHY_MICREL_KSZ90X1=y
+CONFIG_DM_ETH=y
+CONFIG_ETH_DESIGNWARE=y
+CONFIG_MII=y
+CONFIG_DM_RESET=y
+CONFIG_SPI=y
+CONFIG_CADENCE_QSPI=y
+CONFIG_DESIGNWARE_SPI=y
+CONFIG_USB=y
+CONFIG_DM_USB=y
+CONFIG_USB_DWC2=y
+CONFIG_USB_STORAGE=y
+CONFIG_DESIGNWARE_WATCHDOG=y
+CONFIG_WDT=y
+# CONFIG_SPL_USE_TINY_PRINTF is not set
+CONFIG_PANIC_HANG=y
diff --git a/configs/socfpga_stratix10_atf_defconfig b/configs/socfpga_stratix10_atf_defconfig
index d1b1211..8dbb742 100644
--- a/configs/socfpga_stratix10_atf_defconfig
+++ b/configs/socfpga_stratix10_atf_defconfig
@@ -20,6 +20,8 @@
CONFIG_BOOTDELAY=5
CONFIG_USE_BOOTARGS=y
CONFIG_BOOTARGS="earlycon"
+CONFIG_USE_BOOTCOMMAND=y
+CONFIG_BOOTCOMMAND="run fatscript; run mmcfitload; run linux_qspi_enable; run mmcfitboot"
CONFIG_SPL_SPI_LOAD=y
CONFIG_SPL_ATF=y
CONFIG_SPL_ATF_NO_PLATFORM_PARAM=y
diff --git a/configs/socfpga_stratix10_defconfig b/configs/socfpga_stratix10_defconfig
index 3df44bb..2d145e1 100644
--- a/configs/socfpga_stratix10_defconfig
+++ b/configs/socfpga_stratix10_defconfig
@@ -20,6 +20,8 @@
CONFIG_BOOTDELAY=5
CONFIG_USE_BOOTARGS=y
CONFIG_BOOTARGS="earlycon"
+CONFIG_USE_BOOTCOMMAND=y
+CONFIG_BOOTCOMMAND="run fatscript; run mmcload; run linux_qspi_enable; run mmcboot"
CONFIG_SPL_SPI_LOAD=y
CONFIG_HUSH_PARSER=y
CONFIG_SYS_PROMPT="SOCFPGA_STRATIX10 # "
diff --git a/configs/stm32f429-discovery_defconfig b/configs/stm32f429-discovery_defconfig
index 99bf64a..a1721fd 100644
--- a/configs/stm32f429-discovery_defconfig
+++ b/configs/stm32f429-discovery_defconfig
@@ -14,7 +14,6 @@
CONFIG_BOOTARGS="console=ttyS0,115200 earlyprintk consoleblank=0 ignore_loglevel"
# CONFIG_DISPLAY_CPUINFO is not set
# CONFIG_DISPLAY_BOARDINFO is not set
-CONFIG_BOARD_EARLY_INIT_F=y
CONFIG_MISC_INIT_R=y
CONFIG_HUSH_PARSER=y
CONFIG_SYS_PROMPT="U-Boot > "
diff --git a/configs/stm32f429-evaluation_defconfig b/configs/stm32f429-evaluation_defconfig
index 4511ac8..55505ea 100644
--- a/configs/stm32f429-evaluation_defconfig
+++ b/configs/stm32f429-evaluation_defconfig
@@ -11,7 +11,6 @@
CONFIG_BOOTDELAY=3
# CONFIG_USE_BOOTCOMMAND is not set
# CONFIG_DISPLAY_CPUINFO is not set
-CONFIG_BOARD_EARLY_INIT_F=y
CONFIG_MISC_INIT_R=y
CONFIG_SYS_PROMPT="U-Boot > "
CONFIG_CMD_IMLS=y
diff --git a/configs/stm32f469-discovery_defconfig b/configs/stm32f469-discovery_defconfig
index d13794e..3760397 100644
--- a/configs/stm32f469-discovery_defconfig
+++ b/configs/stm32f469-discovery_defconfig
@@ -11,7 +11,6 @@
CONFIG_BOOTDELAY=3
# CONFIG_USE_BOOTCOMMAND is not set
# CONFIG_DISPLAY_CPUINFO is not set
-CONFIG_BOARD_EARLY_INIT_F=y
CONFIG_MISC_INIT_R=y
CONFIG_SYS_PROMPT="U-Boot > "
CONFIG_CMD_IMLS=y
diff --git a/configs/stm32f746-disco_defconfig b/configs/stm32f746-disco_defconfig
index 106ef28..e6585e5 100644
--- a/configs/stm32f746-disco_defconfig
+++ b/configs/stm32f746-disco_defconfig
@@ -18,7 +18,6 @@
# CONFIG_USE_BOOTCOMMAND is not set
# CONFIG_DISPLAY_CPUINFO is not set
# CONFIG_DISPLAY_BOARDINFO is not set
-CONFIG_BOARD_EARLY_INIT_F=y
CONFIG_BOARD_LATE_INIT=y
CONFIG_SYS_PROMPT="U-Boot > "
CONFIG_CMD_GPT=y
diff --git a/configs/stm32f769-disco_defconfig b/configs/stm32f769-disco_defconfig
index cc3fad6..6dc9668 100644
--- a/configs/stm32f769-disco_defconfig
+++ b/configs/stm32f769-disco_defconfig
@@ -18,8 +18,6 @@
# CONFIG_USE_BOOTCOMMAND is not set
# CONFIG_DISPLAY_CPUINFO is not set
# CONFIG_DISPLAY_BOARDINFO is not set
-CONFIG_BOARD_EARLY_INIT_F=y
-CONFIG_BOARD_LATE_INIT=y
CONFIG_SYS_PROMPT="U-Boot > "
CONFIG_CMD_GPT=y
# CONFIG_RANDOM_UUID is not set
diff --git a/configs/stm32h743-disco_defconfig b/configs/stm32h743-disco_defconfig
index 788da28..4f4144c 100644
--- a/configs/stm32h743-disco_defconfig
+++ b/configs/stm32h743-disco_defconfig
@@ -15,8 +15,6 @@
# CONFIG_USE_BOOTCOMMAND is not set
CONFIG_DEFAULT_FDT_FILE="stm32h743i-disco"
# CONFIG_DISPLAY_CPUINFO is not set
-CONFIG_BOARD_EARLY_INIT_F=y
-CONFIG_BOARD_LATE_INIT=y
CONFIG_SYS_PROMPT="U-Boot > "
CONFIG_CMD_GPT=y
CONFIG_CMD_MMC=y
diff --git a/configs/stm32h743-eval_defconfig b/configs/stm32h743-eval_defconfig
index d752f5e..1812485 100644
--- a/configs/stm32h743-eval_defconfig
+++ b/configs/stm32h743-eval_defconfig
@@ -15,8 +15,6 @@
# CONFIG_USE_BOOTCOMMAND is not set
CONFIG_DEFAULT_FDT_FILE="stm32h743i-eval"
# CONFIG_DISPLAY_CPUINFO is not set
-CONFIG_BOARD_EARLY_INIT_F=y
-CONFIG_BOARD_LATE_INIT=y
CONFIG_SYS_PROMPT="U-Boot > "
CONFIG_CMD_GPT=y
CONFIG_CMD_MMC=y
diff --git a/configs/stm32mp15_basic_defconfig b/configs/stm32mp15_basic_defconfig
index def6a51..fbca482 100644
--- a/configs/stm32mp15_basic_defconfig
+++ b/configs/stm32mp15_basic_defconfig
@@ -20,6 +20,7 @@
CONFIG_DEFAULT_DEVICE_TREE="stm32mp157c-ev1"
CONFIG_DISTRO_DEFAULTS=y
CONFIG_FIT=y
+CONFIG_BOOTDELAY=1
CONFIG_BOOTCOMMAND="run bootcmd_stm32mp"
CONFIG_SPL_LOG=y
CONFIG_BOARD_EARLY_INIT_F=y
@@ -34,6 +35,7 @@
CONFIG_SYS_PROMPT="STM32MP> "
CONFIG_CMD_ADTIMG=y
CONFIG_CMD_ERASEENV=y
+CONFIG_CMD_NVEDIT_EFI=y
CONFIG_CMD_MEMINFO=y
CONFIG_CMD_MEMTEST=y
CONFIG_CMD_ADC=y
@@ -49,6 +51,7 @@
CONFIG_CMD_USB_MASS_STORAGE=y
CONFIG_CMD_BMP=y
CONFIG_CMD_CACHE=y
+CONFIG_CMD_EFIDEBUG=y
CONFIG_CMD_TIME=y
CONFIG_CMD_TIMER=y
CONFIG_CMD_PMIC=y
@@ -69,6 +72,7 @@
CONFIG_ENV_UBI_VOLUME="uboot_config"
CONFIG_ENV_UBI_VOLUME_REDUND="uboot_config_r"
CONFIG_SYS_RELOC_GD_ENV_ADDR=y
+CONFIG_SYS_MMC_ENV_DEV=-1
# CONFIG_SPL_ENV_IS_NOWHERE is not set
# CONFIG_SPL_ENV_IS_IN_SPI_FLASH is not set
CONFIG_STM32_ADC=y
@@ -164,4 +168,5 @@
CONFIG_WDT=y
CONFIG_WDT_STM32MP=y
CONFIG_ERRNO_STR=y
+# CONFIG_HEXDUMP is not set
CONFIG_FDT_FIXUP_PARTITIONS=y
diff --git a/configs/stm32mp15_dhcom_basic_defconfig b/configs/stm32mp15_dhcom_basic_defconfig
index ed285e9..e36d34d 100644
--- a/configs/stm32mp15_dhcom_basic_defconfig
+++ b/configs/stm32mp15_dhcom_basic_defconfig
@@ -19,6 +19,7 @@
CONFIG_SPL_LOAD_FIT=y
CONFIG_SPL_FIT_SOURCE="board/dhelectronics/dh_stm32mp1/u-boot-dhcom.its"
# CONFIG_USE_SPL_FIT_GENERATOR is not set
+CONFIG_BOOTDELAY=1
CONFIG_BOOTCOMMAND="run bootcmd_stm32mp"
CONFIG_BOARD_EARLY_INIT_F=y
CONFIG_SPL_LEGACY_IMAGE_SUPPORT=y
diff --git a/configs/stm32mp15_dhcor_basic_defconfig b/configs/stm32mp15_dhcor_basic_defconfig
index a662056..4794b1a 100644
--- a/configs/stm32mp15_dhcor_basic_defconfig
+++ b/configs/stm32mp15_dhcor_basic_defconfig
@@ -17,6 +17,7 @@
CONFIG_SPL_LOAD_FIT=y
CONFIG_SPL_FIT_SOURCE="board/dhelectronics/dh_stm32mp1/u-boot-dhcor.its"
# CONFIG_USE_SPL_FIT_GENERATOR is not set
+CONFIG_BOOTDELAY=1
CONFIG_BOOTCOMMAND="run bootcmd_stm32mp"
CONFIG_BOARD_EARLY_INIT_F=y
CONFIG_SPL_LEGACY_IMAGE_SUPPORT=y
diff --git a/configs/stm32mp15_trusted_defconfig b/configs/stm32mp15_trusted_defconfig
index da31b74..ba9a660 100644
--- a/configs/stm32mp15_trusted_defconfig
+++ b/configs/stm32mp15_trusted_defconfig
@@ -13,10 +13,12 @@
CONFIG_DEFAULT_DEVICE_TREE="stm32mp157c-ev1"
CONFIG_DISTRO_DEFAULTS=y
CONFIG_FIT=y
+CONFIG_BOOTDELAY=1
CONFIG_BOOTCOMMAND="run bootcmd_stm32mp"
CONFIG_SYS_PROMPT="STM32MP> "
CONFIG_CMD_ADTIMG=y
CONFIG_CMD_ERASEENV=y
+CONFIG_CMD_NVEDIT_EFI=y
CONFIG_CMD_MEMINFO=y
CONFIG_CMD_MEMTEST=y
CONFIG_CMD_ADC=y
@@ -32,6 +34,7 @@
CONFIG_CMD_USB_MASS_STORAGE=y
CONFIG_CMD_BMP=y
CONFIG_CMD_CACHE=y
+CONFIG_CMD_EFIDEBUG=y
CONFIG_CMD_TIME=y
CONFIG_CMD_TIMER=y
CONFIG_CMD_PMIC=y
@@ -50,7 +53,9 @@
CONFIG_ENV_UBI_VOLUME="uboot_config"
CONFIG_ENV_UBI_VOLUME_REDUND="uboot_config_r"
CONFIG_SYS_RELOC_GD_ENV_ADDR=y
+CONFIG_SYS_MMC_ENV_DEV=-1
CONFIG_STM32_ADC=y
+CONFIG_CLK_SCMI=y
CONFIG_SET_DFU_ALT_INFO=y
CONFIG_USB_FUNCTION_FASTBOOT=y
CONFIG_FASTBOOT_BUF_ADDR=0xC0000000
@@ -107,6 +112,7 @@
CONFIG_DM_REGULATOR_STM32_VREFBUF=y
CONFIG_DM_REGULATOR_STPMIC1=y
CONFIG_REMOTEPROC_STM32_COPRO=y
+CONFIG_RESET_SCMI=y
CONFIG_DM_RNG=y
CONFIG_RNG_STM32MP1=y
CONFIG_DM_RTC=y
@@ -144,4 +150,5 @@
CONFIG_WDT=y
CONFIG_WDT_STM32MP=y
CONFIG_ERRNO_STR=y
+# CONFIG_HEXDUMP is not set
CONFIG_FDT_FIXUP_PARTITIONS=y
diff --git a/configs/tbs2910_defconfig b/configs/tbs2910_defconfig
index 239e9ed..b71657a 100644
--- a/configs/tbs2910_defconfig
+++ b/configs/tbs2910_defconfig
@@ -67,7 +67,6 @@
CONFIG_DWC_AHSATA=y
CONFIG_DM_I2C=y
CONFIG_SYS_I2C_MXC=y
-CONFIG_DM_KEYBOARD=y
CONFIG_DM_MMC=y
CONFIG_FSL_USDHC=y
CONFIG_PHYLIB=y
diff --git a/configs/turris_mox_defconfig b/configs/turris_mox_defconfig
index dde7437..f938fbb 100644
--- a/configs/turris_mox_defconfig
+++ b/configs/turris_mox_defconfig
@@ -61,10 +61,10 @@
CONFIG_PHY_MARVELL=y
CONFIG_PHY_GIGE=y
CONFIG_MVNETA=y
+CONFIG_NVME=y
CONFIG_PCI=y
CONFIG_DM_PCI=y
CONFIG_PCI_AARDVARK=y
-# CONFIG_PCI_PNP is not set
CONFIG_MVEBU_COMPHY_SUPPORT=y
CONFIG_PINCTRL=y
CONFIG_PINCTRL_ARMADA_37XX=y
@@ -78,6 +78,7 @@
CONFIG_USB=y
CONFIG_DM_USB=y
CONFIG_USB_XHCI_HCD=y
+CONFIG_USB_XHCI_PCI=y
CONFIG_USB_EHCI_HCD=y
CONFIG_USB_HOST_ETHER=y
CONFIG_USB_ETHER_ASIX=y
diff --git a/configs/vexpress_aemv8a_semi_defconfig b/configs/vexpress_aemv8a_semi_defconfig
index a26137e..2ecb776 100644
--- a/configs/vexpress_aemv8a_semi_defconfig
+++ b/configs/vexpress_aemv8a_semi_defconfig
@@ -2,7 +2,7 @@
CONFIG_TARGET_VEXPRESS64_BASE_FVP=y
CONFIG_SYS_TEXT_BASE=0x88000000
CONFIG_SYS_MALLOC_F_LEN=0x2000
-CONFIG_NR_DRAM_BANKS=1
+CONFIG_NR_DRAM_BANKS=2
CONFIG_SYS_MEMTEST_START=0x80000000
CONFIG_SYS_MEMTEST_END=0xff000000
CONFIG_ENV_SIZE=0x40000
diff --git a/disk/part.c b/disk/part.c
index 85b1af5..80ced2b 100644
--- a/disk/part.c
+++ b/disk/part.c
@@ -355,7 +355,7 @@
}
#endif /* CONFIG_HAVE_BLOCK_DEVICE */
- return -1;
+ return -ENOENT;
}
int part_get_info_whole_disk(struct blk_desc *dev_desc,
@@ -417,7 +417,7 @@
*dev_desc = get_dev_hwpart(ifname, dev, hwpart);
if (!(*dev_desc) || ((*dev_desc)->type == DEV_TYPE_UNKNOWN)) {
debug("** Bad device %s %s **\n", ifname, dev_hwpart_str);
- dev = -ENOENT;
+ dev = -ENODEV;
goto cleanup;
}
@@ -441,7 +441,7 @@
struct blk_desc **dev_desc,
struct disk_partition *info, int allow_whole_dev)
{
- int ret = -1;
+ int ret;
const char *part_str;
char *dup_str = NULL;
const char *dev_str;
@@ -483,7 +483,7 @@
if (0 == strcmp(ifname, "ubi")) {
if (!ubifs_is_mounted()) {
printf("UBIFS not mounted, use ubifsmount to mount volume first!\n");
- return -1;
+ return -EINVAL;
}
*dev_desc = NULL;
@@ -505,6 +505,7 @@
/* If still no dev_part_str, it's an error */
if (!dev_part_str) {
printf("** No device specified **\n");
+ ret = -ENODEV;
goto cleanup;
}
@@ -521,8 +522,10 @@
/* Look up the device */
dev = blk_get_device_by_str(ifname, dev_str, dev_desc);
- if (dev < 0)
+ if (dev < 0) {
+ ret = dev;
goto cleanup;
+ }
/* Convert partition ID string to number */
if (!part_str || !*part_str) {
@@ -539,6 +542,7 @@
if (*ep || (part == 0 && !allow_whole_dev)) {
printf("** Bad partition specification %s %s **\n",
ifname, dev_part_str);
+ ret = -ENOENT;
goto cleanup;
}
}
@@ -552,6 +556,7 @@
if (!(*dev_desc)->lba) {
printf("** Bad device size - %s %s **\n", ifname,
dev_str);
+ ret = -EINVAL;
goto cleanup;
}
@@ -563,6 +568,7 @@
if ((part > 0) || (!allow_whole_dev)) {
printf("** No partition table - %s %s **\n", ifname,
dev_str);
+ ret = -EPROTONOSUPPORT;
goto cleanup;
}
@@ -631,7 +637,6 @@
*info = tmpinfo;
} else {
printf("** No valid partitions found **\n");
- ret = -1;
goto cleanup;
}
}
@@ -639,7 +644,7 @@
printf("** Invalid partition type \"%.32s\""
" (expect \"" BOOT_PART_TYPE "\")\n",
info->type);
- ret = -1;
+ ret = -EINVAL;
goto cleanup;
}
@@ -675,7 +680,7 @@
}
}
- return -1;
+ return -ENOENT;
}
int part_get_info_by_name(struct blk_desc *dev_desc, const char *name,
@@ -688,12 +693,13 @@
* Get partition info from device number and partition name.
*
* Parse a device number and partition name string in the form of
- * "device_num#partition_name", for example "0#misc". If the partition
- * is found, sets dev_desc and part_info accordingly with the information
- * of the partition with the given partition_name.
+ * "devicenum.hwpartnum#partition_name", for example "0.1#misc". devicenum and
+ * hwpartnum are both optional, defaulting to 0. If the partition is found,
+ * sets dev_desc and part_info accordingly with the information of the
+ * partition with the given partition_name.
*
* @param[in] dev_iface Device interface
- * @param[in] dev_part_str Input string argument, like "0#misc"
+ * @param[in] dev_part_str Input string argument, like "0.1#misc"
* @param[out] dev_desc Place to store the device description pointer
* @param[out] part_info Place to store the partition information
* @return 0 on success, or a negative on error
@@ -703,53 +709,57 @@
struct blk_desc **dev_desc,
struct disk_partition *part_info)
{
- char *ep;
- const char *part_str;
- int dev_num;
+ char *dup_str = NULL;
+ const char *dev_str, *part_str;
+ int ret;
+ /* Separate device and partition name specification */
part_str = strchr(dev_part_str, '#');
- if (!part_str || part_str == dev_part_str)
- return -EINVAL;
-
- dev_num = simple_strtoul(dev_part_str, &ep, 16);
- if (ep != part_str) {
- /* Not all the first part before the # was parsed. */
+ if (part_str) {
+ dup_str = strdup(dev_part_str);
+ dup_str[part_str - dev_part_str] = 0;
+ dev_str = dup_str;
+ part_str++;
+ } else {
return -EINVAL;
}
- part_str++;
- *dev_desc = blk_get_dev(dev_iface, dev_num);
- if (!*dev_desc) {
- printf("Could not find %s %d\n", dev_iface, dev_num);
- return -EINVAL;
- }
- if (part_get_info_by_name(*dev_desc, part_str, part_info) < 0) {
+ ret = blk_get_device_by_str(dev_iface, dev_str, dev_desc);
+ if (ret)
+ goto cleanup;
+
+ ret = part_get_info_by_name(*dev_desc, part_str, part_info);
+ if (ret < 0)
printf("Could not find \"%s\" partition\n", part_str);
- return -EINVAL;
- }
- return 0;
+
+cleanup:
+ free(dup_str);
+ return ret;
}
int part_get_info_by_dev_and_name_or_num(const char *dev_iface,
const char *dev_part_str,
struct blk_desc **dev_desc,
- struct disk_partition *part_info)
+ struct disk_partition *part_info,
+ int allow_whole_dev)
{
+ int ret;
+
/* Split the part_name if passed as "$dev_num#part_name". */
- if (!part_get_info_by_dev_and_name(dev_iface, dev_part_str,
- dev_desc, part_info))
- return 0;
+ ret = part_get_info_by_dev_and_name(dev_iface, dev_part_str,
+ dev_desc, part_info);
+ if (ret >= 0)
+ return ret;
/*
* Couldn't lookup by name, try looking up the partition description
* directly.
*/
- if (blk_get_device_part_str(dev_iface, dev_part_str,
- dev_desc, part_info, 1) < 0) {
+ ret = blk_get_device_part_str(dev_iface, dev_part_str,
+ dev_desc, part_info, allow_whole_dev);
+ if (ret < 0)
printf("Couldn't find partition %s %s\n",
dev_iface, dev_part_str);
- return -EINVAL;
- }
- return 0;
+ return ret;
}
void part_set_generic_name(const struct blk_desc *dev_desc,
diff --git a/doc/README.dfu b/doc/README.dfu
deleted file mode 100644
index eacd5bb..0000000
--- a/doc/README.dfu
+++ /dev/null
@@ -1,311 +0,0 @@
-# SPDX-License-Identifier: GPL-2.0+
-
-Device Firmware Upgrade (DFU)
-
-Overview:
-
- The Device Firmware Upgrade (DFU) allows to download and upload firmware
- to/from U-Boot connected over USB.
-
- U-boot follows the Universal Serial Bus Device Class Specification for
- Device Firmware Upgrade Version 1.1 the USB forum (DFU v1.1 in www.usb.org).
-
- U-Boot implements this DFU capability (CONFIG_DFU) with the command dfu
- (cmd/dfu.c / CONFIG_CMD_DFU) based on:
- - the DFU stack (common/dfu.c and common/spl/spl_dfu.c), based on the
- USB DFU download gadget (drivers/usb/gadget/f_dfu.c)
- - The access to mediums is done in DFU backends (driver/dfu)
-
- Today the supported DFU backends are:
- - MMC (RAW or FAT / EXT2 / EXT3 / EXT4 file system / SKIP / SCRIPT)
- - NAND
- - RAM
- - SF (serial flash)
- - MTD (all MTD device: NAND, SPI-NOR, SPI-NAND,...)
- - virtual
-
- These DFU backends are also used by
- - the dfutftp (see README.dfutftp)
- - the thordown command (cmd/thordown.c and gadget/f_thor.c)
-
- The "virtual" backend is a generic DFU backend to support a board specific
- target (for example OTP), only based on the weak functions:
- - dfu_write_medium_virt
- - dfu_get_medium_size_virt
- - dfu_read_medium_virt
-
-Configuration Options:
- CONFIG_DFU
- CONFIG_DFU_OVER_USB
- CONFIG_DFU_MMC
- CONFIG_DFU_MTD
- CONFIG_DFU_NAND
- CONFIG_DFU_RAM
- CONFIG_DFU_SF
- CONFIG_DFU_SF_PART
- CONFIG_DFU_TIMEOUT
- CONFIG_DFU_VIRTUAL
- CONFIG_CMD_DFU
-
-Environment variables:
- the dfu command uses 3 environments variables:
- "dfu_alt_info" : the DFU setting for the USB download gadget with a semicolon
- separated string of information on each alternate:
- dfu_alt_info="<alt1>;<alt2>;....;<altN>"
-
- when several devices are used, the format is:
- - <interface> <dev>'='alternate list (';' separated)
- - each interface is separated by '&'
- dfu_alt_info=\
- "<interface1> <dev1>=<alt1>;....;<altN>&"\
- "<interface2> <dev2>=<altN+1>;....;<altM>&"\
- ...\
- "<interfaceI> <devI>=<altY+1>;....;<altZ>&"
-
- "dfu_bufsiz" : size of the DFU buffer, when absent, use
- CONFIG_SYS_DFU_DATA_BUF_SIZE (8 MiB by default)
-
- "dfu_hash_algo" : name of the hash algorithm to use
-
-Commands:
- dfu <USB_controller> [<interface> <dev>] list
- list the alternate device defined in "dfu_alt_info"
-
- dfu <USB_controller> [<interface> <dev>] [<timeout>]
- start the dfu stack on the USB instance with the selected medium
- backend and use the "dfu_alt_info" variable to configure the
- alternate setting and link each one with the medium
- The dfu command continue until receive a ^C in console or
- a DFU detach transaction from HOST. If CONFIG_DFU_TIMEOUT option
- is enabled and <timeout> parameter is present in the command line,
- the DFU operation will be aborted automatically after <timeout>
- seconds of waiting remote to initiate DFU session.
-
- The possible values of <interface> are :
- (with <USB controller> = 0 in the dfu command example)
-
- "mmc" (for eMMC and SD card)
- cmd: dfu 0 mmc <dev>
- each element in "dfu_alt_info" =
- <name> raw <offset> <size> [mmcpart <num>] raw access to mmc device
- <name> part <dev> <part_id> [mmcpart <num>] raw access to partition
- <name> fat <dev> <part_id> [mmcpart <num>] file in FAT partition
- <name> ext4 <dev> <part_id> [mmcpart <num>] file in EXT4 partition
- <name> skip 0 0 ignore flashed data
- <name> script 0 0 execute commands in shell
-
- with <partid> being the GPT or DOS partition index,
- with <num> being the eMMC hardware partition number.
-
- A value of environment variable dfu_alt_info for eMMC could be:
-
- "u-boot raw 0x3e 0x800 mmcpart 1;bl2 raw 0x1e 0x1d mmcpart 1"
-
- A value of environment variable dfu_alt_info for SD card could be:
-
- "u-boot raw 0x80 0x800;uImage ext4 0 2"
-
- If don't want to flash given image file to storage, use "skip" type
- entity.
- - It can be used to protect flashing wrong image for the specific board.
- - Especailly, this layout will be useful when thor protocol is used,
- which performs flashing in batch mode, where more than one file is
- processed.
- For example, if one makes a single tar file with support for the two
- boards with u-boot-<board1>.bin and u-boot-<board2>.bin files, one
- can use it to flash a proper u-boot image on both without a failure:
-
- "u-boot-<board1>.bin raw 0x80 0x800; u-boot-<board2>.bin skip 0 0"
-
- When flashing new system image requires do some more complex things
- than just writing data to the storage medium, one can use 'script'
- type. Data written to such entity will be executed as a command list
- in the u-boot's shell. This for example allows to re-create partition
- layout and even set new dfu_alt_info for the newly created paritions.
- Such script would look like:
- --->8---
- setenv dfu_alt_info ...
- setenv mbr_parts ...
- mbr write ...
- --->8---
- Please note that this means that user will be able to execute any
- arbitrary commands just like in the u-boot's shell.
-
- "nand" (raw slc nand device)
- cmd: dfu 0 nand <dev>
- each element in "dfu_alt_info" =
- <name> raw <offset> <size> raw access to mmc device
- <name> part <dev> <part_id> raw acces to partition
- <name> partubi <dev> <part_id> raw acces to ubi partition
-
- with <partid> is the MTD partition index
-
- "ram"
- cmd: dfu 0 ram <dev>
- (<dev> is not used for RAM target)
- each element in "dfu_alt_info" =
- <name> ram <offset> <size> raw access to ram
-
- "sf" (serial flash : NOR)
- cmd: dfu 0 sf <dev>
- each element in "dfu_alt_info" =
- <name> raw <offset> <size> raw access to sf device
- <name> part <dev> <part_id> raw acces to partition
- <name> partubi <dev> <part_id> raw acces to ubi partition
-
- with <partid> is the MTD partition index
-
- "mtd" (all MTD device: NAND, SPI-NOR, SPI-NAND,...)
- cmd: dfu 0 mtd <dev>
- with <dev> the mtd identifier as defined in mtd command
- (nand0, nor0, spi-nand0,...)
- each element in "dfu_alt_info" =
- <name> raw <offset> <size> raw access to mtd device
- <name> part <dev> <part_id> raw acces to partition
- <name> partubi <dev> <part_id> raw acces to ubi partition
-
- with <partid> is the MTD partition index
-
- "virt"
- cmd: dfu 0 virt <dev>
- each element in "dfu_alt_info" =
- <name>
-
- <interface> and <dev> are absent:
- the dfu command to use multiple devices
- cmd: dfu 0 list
- cmd: dfu 0
- "dfu_alt_info" variable provides the list of <interface> <dev> with
- alternate list separated by '&' with the same format for each <alt>
- mmc <dev>=<alt1>;....;<altN>
- nand <dev>=<alt1>;....;<altN>
- ram <dev>=<alt1>;....;<altN>
- sf <dev>=<alt1>;....;<altN>
- mtd <dev>=<alt1>;....;<altN>
- virt <dev>=<alt1>;....;<altN>
-
-Callbacks:
- The weak callback functions can be implemented to manage specific behavior
- - dfu_initiated_callback : called when the DFU transaction is started,
- used to initiase the device
- - dfu_flush_callback : called at the end of the DFU write after DFU
- manifestation, used to manage the device when
- DFU transaction is closed
-
-Host tools:
- When U-Boot runs the dfu stack, the DFU host tools can be used
- to send/receive firmwares on each configurated alternate.
-
- For example dfu-util is a host side implementation of the DFU 1.1
- specifications(http://dfu-util.sourceforge.net/) which works with U-Boot.
-
-Usage:
- Example 1: firmware located in eMMC or SD card, with:
- - alternate 1 (alt=1) for SPL partition (GPT partition 1)
- - alternate 2 (alt=2) for U-Boot partition (GPT partition 2)
-
- The U-Boot configuration is:
-
- U-Boot> env set dfu_alt_info "spl part 0 1;u-boot part 0 2"
-
- U-Boot> dfu 0 mmc 0 list
- DFU alt settings list:
- dev: eMMC alt: 0 name: spl layout: RAW_ADDR
- dev: eMMC alt: 1 name: u-boot layout: RAW_ADDR
-
- Boot> dfu 0 mmc 0
-
- On the Host side:
-
- list the available alternate setting:
-
- $> dfu-util -l
- dfu-util 0.9
-
- Copyright 2005-2009 Weston Schmidt, Harald Welte and OpenMoko Inc.
- Copyright 2010-2016 Tormod Volden and Stefan Schmidt
- This program is Free Software and has ABSOLUTELY NO WARRANTY
- Please report bugs to http://sourceforge.net/p/dfu-util/tickets/
-
- Found DFU: [0483:5720] ver=0200, devnum=45, cfg=1, intf=0, path="3-1.3.1", \
- alt=1, name="u-boot", serial="003A00203438510D36383238"
- Found DFU: [0483:5720] ver=0200, devnum=45, cfg=1, intf=0, path="3-1.3.1", \
- alt=0, name="spl", serial="003A00203438510D36383238"
-
- To download to U-Boot, use -D option
-
- $> dfu-util -a 0 -D u-boot-spl.bin
- $> dfu-util -a 1 -D u-boot.bin
-
- To upload from U-Boot, use -U option
-
- $> dfu-util -a 0 -U u-boot-spl.bin
- $> dfu-util -a 1 -U u-boot.bin
-
- To request a DFU detach and reset the USB connection:
- $> dfu-util -a 0 -e -R
-
-
- Example 2: firmware located in NOR (sf) and NAND, with:
- - alternate 1 (alt=1) for SPL partition (NOR GPT partition 1)
- - alternate 2 (alt=2) for U-Boot partition (NOR GPT partition 2)
- - alternate 3 (alt=3) for U-Boot-env partition (NOR GPT partition 3)
- - alternate 4 (alt=4) for UBI partition (NAND GPT partition 1)
-
- U-Boot> env set dfu_alt_info \
- "sf 0:0:10000000:0=spl part 0 1;u-boot part 0 2; \
- u-boot-env part 0 3&nand 0=UBI partubi 0,1"
-
- U-Boot> dfu 0 list
-
- DFU alt settings list:
- dev: SF alt: 0 name: spl layout: RAW_ADDR
- dev: SF alt: 1 name: ssbl layout: RAW_ADDR
- dev: SF alt: 2 name: u-boot-env layout: RAW_ADDR
- dev: NAND alt: 3 name: UBI layout: RAW_ADDR
-
- U-Boot> dfu 0
-
- $> dfu-util -l
- Found DFU: [0483:5720] ver=9999, devnum=96, cfg=1,\
- intf=0, alt=3, name="UBI", serial="002700333338511934383330"
- Found DFU: [0483:5720] ver=9999, devnum=96, cfg=1,\
- intf=0, alt=2, name="u-boot-env", serial="002700333338511934383330"
- Found DFU: [0483:5720] ver=9999, devnum=96, cfg=1,\
- intf=0, alt=1, name="u-boot", serial="002700333338511934383330"
- Found DFU: [0483:5720] ver=9999, devnum=96, cfg=1,\
- intf=0, alt=0, name="spl", serial="002700333338511934383330"
-
- Same example with MTD backend
-
- U-Boot> env set dfu_alt_info \
- "mtd nor0=spl part 1;u-boot part 2;u-boot-env part 3&"\
- "mtd nand0=UBI partubi 1"
-
- U-Boot> dfu 0 list
- using id 'nor0,0'
- using id 'nor0,1'
- using id 'nor0,2'
- using id 'nand0,0'
- DFU alt settings list:
- dev: MTD alt: 0 name: spl layout: RAW_ADDR
- dev: MTD alt: 1 name: u-boot layout: RAW_ADDR
- dev: MTD alt: 2 name: u-boot-env layout: RAW_ADDR
- dev: MTD alt: 3 name: UBI layout: RAW_ADDR
-
- Example 3: firmware located in SD Card (mmc) and virtual partition on
- OTP and PMIC not volatile memory
- - alternate 1 (alt=1) for scard
- - alternate 2 (alt=2) for OTP (virtual)
- - alternate 3 (alt=3) for PMIC NVM (virtual)
-
- U-Boot> env set dfu_alt_info \
- "mmc 0=sdcard raw 0 0x100000&"\
- "virt 0=otp" \
- "virt 1=pmic"
-
- U-Boot> dfu 0 list
- DFU alt settings list:
- dev: eMMC alt: 0 name: sdcard layout: RAW_ADDR
- dev: VIRT alt: 1 name: otp layout: RAW_ADDR
- dev: VIRT alt: 2 name: pmic layout: RAW_ADDR
diff --git a/doc/README.nokia_rx51 b/doc/README.nokia_rx51
index 320b5ef..84d1912 100644
--- a/doc/README.nokia_rx51
+++ b/doc/README.nokia_rx51
@@ -24,8 +24,7 @@
There is support for hardware watchdog. Hardware watchdog is started by
NOLO so u-boot must kick watchdog to prevent reboot device (but not very
often, max every 2 seconds). There is also support for framebuffer display
-output with ANSI escape codes and the N900 HW keyboard input. USB tty works
-but is disabled because it prevents the current Maemo kernel from booting.
+output with ANSI escape codes and the N900 HW keyboard input.
When U-Boot is starting it enable IBE bit in Auxiliary Control Register,
which is needed for Thumb-2 ISA support. It is workaround for errata 430973.
@@ -49,10 +48,6 @@
Available additional commands/variables:
- * run sercon - Use serial port for control
- * run usbcon - Use usbtty for control
- * run vgacon - Use framebuffer and HW keyboard for control (default)
-
* run sdboot - Boot from external SD card (see boot order)
* run emmcboot - Boot from internal eMMC memory (see boot order)
* run attachboot - Boot attached kernel image (attached to U-Boot binary)
@@ -87,14 +82,6 @@
and u-boot standard output is set to serial then setup_console_atag is
automatically set to 1. So output from Maemo kernel would go to serial port.
-USB TTY:
-
- Maemo kernel 2.6.28 will crash if u-boot enable usb tty. So USB TTY is disabled.
- For enabling USB TTY just add this line to file include/configs/nokia_rx51.h
-
- #define CONFIG_USB_TTY
-
-
UBIFS support:
UBIFS support is disabled, because U-Boot image is too big and cannot be
diff --git a/doc/android/fastboot-protocol.rst b/doc/android/fastboot-protocol.rst
index e723659..e8cbd7f 100644
--- a/doc/android/fastboot-protocol.rst
+++ b/doc/android/fastboot-protocol.rst
@@ -144,6 +144,11 @@
"powerdown" Power off the device.
+ "ucmd" execute any bootloader command and wait until it
+ finishs.
+
+ "acmd" execute any bootloader command, do not wait.
+
Client Variables
----------------
diff --git a/doc/android/fastboot.rst b/doc/android/fastboot.rst
index 16b1139..7611f07 100644
--- a/doc/android/fastboot.rst
+++ b/doc/android/fastboot.rst
@@ -19,6 +19,8 @@
- ``reboot``
- ``reboot-bootloader``
- ``set_active`` (only a stub implementation which always succeeds)
+- ``ucmd`` (if enabled)
+- ``acmd`` (if enabled)
The following OEM commands are supported (if enabled):
@@ -154,6 +156,10 @@
controller, SD/MMC controller) or disk index. The partition index starts
from ``1`` and describes the partition number on the particular device.
+Alternatively, partition types may be specified using :ref:`U-Boot's partition
+syntax <partitions>`. This allows specifying partitions like ``0.1``,
+``0#boot``, or ``:3``. The interface is always ``mmc``.
+
Writing Partition Table
-----------------------
diff --git a/doc/board/emulation/index.rst b/doc/board/emulation/index.rst
index a09ead1..be66b6b 100644
--- a/doc/board/emulation/index.rst
+++ b/doc/board/emulation/index.rst
@@ -8,6 +8,7 @@
qemu-arm
qemu-mips
+ qemu-ppce500
qemu-riscv
qemu-x86
qemu_capsule_update
diff --git a/doc/board/emulation/qemu-ppce500.rst b/doc/board/emulation/qemu-ppce500.rst
new file mode 100644
index 0000000..0a5c86c
--- /dev/null
+++ b/doc/board/emulation/qemu-ppce500.rst
@@ -0,0 +1,88 @@
+.. SPDX-License-Identifier: GPL-2.0+
+.. Copyright (C) 2021, Bin Meng <bmeng.cn@gmail.com>
+
+QEMU PPC E500
+=============
+
+QEMU for PPC supports a special 'ppce500' machine designed for emulation and
+virtualization purposes. This document describes how to run U-Boot under it.
+
+The QEMU ppce500 machine models a generic PowerPC E500 virtual machine with
+support for the VirtIO standard networking device connected to the built-in
+PCI host controller. Some common devices in the CCSBAR space are modeled,
+including MPIC, 16550A UART devices, GPIO, I2C and PCI host controller with
+MSI delivery to MPIC. It uses device-tree to pass configuration information
+to guest software.
+
+Building U-Boot
+---------------
+Set the CROSS_COMPILE environment variable as usual, and run::
+
+ $ make qemu-ppce500_defconfig
+ $ make
+
+Running U-Boot
+--------------
+The minimal QEMU command line to get U-Boot up and running is::
+
+ $ qemu-system-ppc -nographic -machine ppce500 -bios u-boot
+
+You can also run U-Boot using 'qemu-system-ppc64'::
+
+ $ qemu-system-ppc64 -nographic -machine ppce500 -bios u-boot
+
+The commands above create a target with 128 MiB memory by default. A freely
+configurable amount of RAM can be created via the '-m' parameter. For example,
+'-m 2G' creates 2 GiB memory for the target, and the memory node in the
+embedded DTB created by QEMU reflects the new setting.
+
+Both qemu-system-ppc and qemu-system-ppc64 provide emulation for the following
+32-bit PowerPC CPUs:
+
+* e500v2
+* e500mc
+
+Additionally qemu-system-ppc64 provides support for the following 64-bit CPUs:
+
+* e5500
+* e6500
+
+The CPU type can be specified via the '-cpu' command line. If not specified,
+it creates a machine with e500v2 core. The following example shows an e6500
+based machine creation::
+
+ $ qemu-system-ppc64 -nographic -machine ppce500 -cpu e6500 -bios u-boot
+
+When U-Boot boots, you will notice the following::
+
+ CPU: Unknown, Version: 0.0, (0x00000000)
+ Core: e6500, Version: 2.0, (0x80400020)
+
+This is because we only specified a core name to QEMU and it does not have a
+meaningful SVR value which represents an actual SoC that integrates such core.
+You can specify a real world SoC device that QEMU has built-in support but all
+these SoCs are e500v2 based MPC85xx series, hence you cannot test anything
+built for P4080 (e500mc), P5020 (e5500) and T2080 (e6500).
+
+By default a VirtIO standard PCI networking device is connected as an ethernet
+interface at PCI address 0.1.0, but we can switch that to an e1000 NIC by::
+
+ $ qemu-system-ppc -nographic -machine ppce500 -bios u-boot \
+ -nic tap,ifname=tap0,script=no,downscript=no,model=e1000
+
+VirtIO BLK driver is also enabled to support booting from a disk image where
+a kernel image is stored. Append the following to QEMU::
+
+ -drive file=disk.img,format=raw,id=disk0 -device virtio-blk-pci,drive=disk0
+
+Pericom pt7c4338 RTC is supported so we can use the 'date' command::
+
+ => date
+ Date: 2021-02-18 (Thursday) Time: 15:33:20
+
+Additionally, 'poweroff' command is supported to shut down the QEMU session::
+
+ => poweroff
+ poweroff ...
+
+These have been tested in QEMU 5.2.0.
diff --git a/doc/board/freescale/imx8mp_evk.rst b/doc/board/freescale/imx8mp_evk.rst
index ccffcf7..796a761 100644
--- a/doc/board/freescale/imx8mp_evk.rst
+++ b/doc/board/freescale/imx8mp_evk.rst
@@ -16,27 +16,21 @@
Get and Build the ARM Trusted firmware
--------------------------------------
-Note: $(srctree) is the U-Boot source directory
Get ATF from: https://source.codeaurora.org/external/imx/imx-atf
-branch: imx_5.4.47_2.2.0
+branch: imx_5.4.70_2.3.0
.. code-block:: bash
$ make PLAT=imx8mp bl31
- $ cp build/imx8mp/release/bl31.bin $(srctree)
Get the ddr firmware
--------------------
.. code-block:: bash
- $ wget https://www.nxp.com/lgfiles/NMG/MAD/YOCTO/firmware-imx-8.9.bin
- $ chmod +x firmware-imx-8.9.bin
- $ ./firmware-imx-8.9.bin
- $ cp firmware-imx-8.9/firmware/ddr/synopsys/lpddr4_pmu_train_1d_dmem_201904.bin $(srctree)/lpddr4_pmu_train_1d_dmem.bin
- $ cp firmware-imx-8.9/firmware/ddr/synopsys/lpddr4_pmu_train_1d_imem_201904.bin $(srctree)/lpddr4_pmu_train_1d_imem.bin
- $ cp firmware-imx-8.9/firmware/ddr/synopsys/lpddr4_pmu_train_2d_dmem_201904.bin $(srctree)/lpddr4_pmu_train_2d_dmem.bin
- $ cp firmware-imx-8.9/firmware/ddr/synopsys/lpddr4_pmu_train_2d_imem_201904.bin $(srctree)/lpddr4_pmu_train_2d_imem.bin
+ $ wget https://www.nxp.com/lgfiles/NMG/MAD/YOCTO/firmware-imx-8.10.bin
+ $ chmod +x firmware-imx-8.10.bin
+ $ ./firmware-imx-8.10.bin
Build U-Boot
------------
@@ -44,15 +38,20 @@
.. code-block:: bash
$ export CROSS_COMPILE=aarch64-poky-linux-
- $ make imx8mp_evk_defconfig
- $ export ATF_LOAD_ADDR=0x960000
- $ make flash.bin
+ $ make O=build imx8mp_evk_defconfig
+ $ cp ../imx-atf/build/imx8mp/release/bl31.bin ./build/bl31.bin
+ $ cp ../firmware-imx-8.10/firmware/ddr/synopsys/lpddr4_pmu_train_1d_dmem_202006.bin ./build/lpddr4_pmu_train_1d_dmem.bin
+ $ cp ../firmware-imx-8.10/firmware/ddr/synopsys/lpddr4_pmu_train_1d_imem_202006.bin ./build/lpddr4_pmu_train_1d_imem.bin
+ $ cp ../firmware-imx-8.10/firmware/ddr/synopsys/lpddr4_pmu_train_2d_dmem_202006.bin ./build/lpddr4_pmu_train_2d_dmem.bin
+ $ cp ../firmware-imx-8.10/firmware/ddr/synopsys/lpddr4_pmu_train_2d_imem_202006.bin ./build/lpddr4_pmu_train_2d_imem.bin
+ $ export ATF_LOAD_ADDR=0x970000
+ $ make O=build flash.bin
Burn the flash.bin to the MicroSD card at offset 32KB:
.. code-block:: bash
- $sudo dd if=flash.bin of=/dev/sd[x] bs=1K seek=32 conv=notrunc; sync
+ $sudo dd if=build/flash.bin of=/dev/sd[x] bs=1K seek=32 conv=notrunc; sync
Boot
----
diff --git a/doc/board/intel/slimbootloader.rst b/doc/board/intel/slimbootloader.rst
index a8c41b1..18f1cc0 100644
--- a/doc/board/intel/slimbootloader.rst
+++ b/doc/board/intel/slimbootloader.rst
@@ -170,7 +170,7 @@
$ python BuildLoader.py build <qemu or apl> -p "OsLoader.efi:LLDR:Lz4;u-boot:U-BT:Lzma"
-.. _U-Boot: https://gitlab.denx.de/
+.. _U-Boot: https://source.denx.de/
.. _`Slim Bootloader`: https://github.com/slimbootloader/
.. _`Intel FSP`: https://github.com/IntelFsp/
.. _`Getting Started`: https://slimbootloader.github.io/getting-started/
diff --git a/doc/board/sipeed/maix.rst b/doc/board/sipeed/maix.rst
index bf945b3..ef79297 100644
--- a/doc/board/sipeed/maix.rst
+++ b/doc/board/sipeed/maix.rst
@@ -258,7 +258,7 @@
"""""""""
To load an image off of SPI flash, first set up a partition as described in
-:ref:`partitions`. Then, use ``mtd`` to load that partition
+:ref:`k210_partitions`. Then, use ``mtd`` to load that partition
.. code-block:: none
@@ -401,7 +401,7 @@
stored in the first 1 MiB or so of this flash. U-Boot's environment is stored at
the end of flash.
-.. _partitions:
+.. _k210_partitions:
Partitions
""""""""""
diff --git a/doc/board/st/stm32mp1.rst b/doc/board/st/stm32mp1.rst
index 20f5c9e..f0c2b09 100644
--- a/doc/board/st/stm32mp1.rst
+++ b/doc/board/st/stm32mp1.rst
@@ -237,7 +237,8 @@
- For Basic boot
- FSBL = spl/u-boot-spl.stm32
- - SSBL = u-boot.img
+ - SSBL = u-boot.img (without CONFIG_SPL_LOAD_FIT) or
+ u-boot.itb (with CONFIG_SPL_LOAD_FIT=y)
Switch Setting for Boot Mode
----------------------------
@@ -347,7 +348,9 @@
# dd if=u-boot-spl.stm32 of=/dev/mmcblk0p1
# dd if=u-boot-spl.stm32 of=/dev/mmcblk0p2
- # dd if=u-boot.img of=/dev/mmcblk0p3
+ # dd if=u-boot.img of=/dev/mmcblk0p3 # Without CONFIG_SPL_LOAD_FIT
+ OR
+ dd if=u-boot.itb of=/dev/mmcblk0p3 # With CONFIG_SPL_LOAD_FIT=y
for trusted boot mode: ::
@@ -363,8 +366,9 @@
You can use U-Boot to copy binary in eMMC.
In the next example, you need to boot from SD card and the images
-(u-boot-spl.stm32, u-boot.img) are presents on SD card (mmc 0)
-in ext4 partition 4 (bootfs).
+(u-boot-spl.stm32, u-boot.img for systems without CONFIG_SPL_LOAD_FIT
+or u-boot.itb for systems with CONFIG_SPL_LOAD_FIT=y) are presents on
+SD card (mmc 0) in ext4 partition 4 (bootfs).
To boot from SD card, select BootPinMode = 1 0 1 and reset.
@@ -387,7 +391,9 @@
c) copy U-Boot in first GPT partition of eMMC::
- # ext4load mmc 0:4 0xC0000000 u-boo t.img
+ # ext4load mmc 0:4 0xC0000000 u-boot.img # Without CONFIG_SPL_LOAD_FIT
+ OR
+ ext4load mmc 0:4 0xC0000000 u-boot.itb # With CONFIG_SPL_LOAD_FIT=y
# mmc dev 1
# part start mmc 1 1 partstart
# mmc write ${fileaddr} ${partstart} ${filesize}
diff --git a/doc/build/source.rst b/doc/build/source.rst
index 75720e2..470f793 100644
--- a/doc/build/source.rst
+++ b/doc/build/source.rst
@@ -7,7 +7,7 @@
.. code-block:: bash
- git clone https://gitlab.denx.de/u-boot/u-boot.git
+ git clone https://source.denx.de/u-boot/u-boot.git
A mirror of the source is maintained on Github
diff --git a/doc/develop/py_testing.rst b/doc/develop/py_testing.rst
index f71e837..7f01858 100644
--- a/doc/develop/py_testing.rst
+++ b/doc/develop/py_testing.rst
@@ -301,7 +301,7 @@
Examples
''''''''
-https://github.com/swarren/uboot-test-hooks contains some working example hook
+https://source.denx.de/u-boot/u-boot-test-hooks contains some working example hook
scripts, and may be useful as a reference when implementing hook scripts for
your platform. These scripts are not considered part of U-Boot itself.
diff --git a/doc/device-tree-bindings/input/adc-keys.txt b/doc/device-tree-bindings/input/adc-keys.txt
new file mode 100644
index 0000000..6c8be6a
--- /dev/null
+++ b/doc/device-tree-bindings/input/adc-keys.txt
@@ -0,0 +1,67 @@
+ADC attached resistor ladder buttons
+------------------------------------
+
+Required properties:
+ - compatible: "adc-keys"
+ - io-channels: Phandle to an ADC channel
+ - io-channel-names = "buttons";
+ - keyup-threshold-microvolt: Voltage above or equal to which all the keys are
+ considered up.
+
+Optional properties:
+ - poll-interval: Poll interval time in milliseconds
+ - autorepeat: Boolean, Enable auto repeat feature of Linux input
+ subsystem.
+
+Each button (key) is represented as a sub-node of "adc-keys":
+
+Required subnode-properties:
+ - label: Descriptive name of the key.
+ - linux,code: Keycode to emit.
+ - press-threshold-microvolt: voltage above or equal to which this key is
+ considered pressed.
+
+No two values of press-threshold-microvolt may be the same.
+All values of press-threshold-microvolt must be less than
+keyup-threshold-microvolt.
+
+Example:
+
+#include <dt-bindings/input/input.h>
+
+ adc-keys {
+ compatible = "adc-keys";
+ io-channels = <&lradc 0>;
+ io-channel-names = "buttons";
+ keyup-threshold-microvolt = <2000000>;
+
+ button-up {
+ label = "Volume Up";
+ linux,code = <KEY_VOLUMEUP>;
+ press-threshold-microvolt = <1500000>;
+ };
+
+ button-down {
+ label = "Volume Down";
+ linux,code = <KEY_VOLUMEDOWN>;
+ press-threshold-microvolt = <1000000>;
+ };
+
+ button-enter {
+ label = "Enter";
+ linux,code = <KEY_ENTER>;
+ press-threshold-microvolt = <500000>;
+ };
+ };
+
++--------------------------------+------------------------+
+| 2.000.000 <= value | no key pressed |
++--------------------------------+------------------------+
+| 1.500.000 <= value < 2.000.000 | KEY_VOLUMEUP pressed |
++--------------------------------+------------------------+
+| 1.000.000 <= value < 1.500.000 | KEY_VOLUMEDOWN pressed |
++--------------------------------+------------------------+
+| 500.000 <= value < 1.000.000 | KEY_ENTER pressed |
++--------------------------------+------------------------+
+| value < 500.000 | no key pressed |
++--------------------------------+------------------------+
diff --git a/doc/usage/addrmap.rst b/doc/usage/addrmap.rst
new file mode 100644
index 0000000..472fd54
--- /dev/null
+++ b/doc/usage/addrmap.rst
@@ -0,0 +1,41 @@
+.. SPDX-License-Identifier: GPL-2.0+
+
+addrmap command
+===============
+
+Synopsis
+--------
+
+::
+
+ addrmap
+
+Description
+-----------
+
+The addrmap command is used to display non-identity virtual-physical memory
+mappings for 32-bit CPUs.
+
+The output may look like:
+
+::
+
+ => addrmap
+ vaddr paddr size
+ ================ ================ ================
+ e0000000 fe0000000 00100000
+ 00000000 00000000 04000000
+ 04000000 04000000 04000000
+ 80000000 c00000000 10000000
+ 90000000 c10000000 10000000
+ a0000000 fe1000000 00010000
+
+The first column indicates the virtual address.
+The second column indicates the physical address.
+The third column indicates the mapped size.
+
+Configuration
+-------------
+
+To use the addrmap command you must specify CONFIG_CMD_ADDRMAP=y.
+It is automatically turned on when CONFIG_ADDR_MAP is set.
diff --git a/doc/usage/dfu.rst b/doc/usage/dfu.rst
new file mode 100644
index 0000000..11c8807
--- /dev/null
+++ b/doc/usage/dfu.rst
@@ -0,0 +1,404 @@
+.. SPDX-License-Identifier: GPL-2.0+
+
+Device Firmware Upgrade (DFU)
+=============================
+
+Overview
+--------
+
+The Device Firmware Upgrade (DFU) allows to download and upload firmware
+to/from U-Boot connected over USB.
+
+U-boot follows the Universal Serial Bus Device Class Specification for
+Device Firmware Upgrade Version 1.1 the USB forum (DFU v1.1 in www.usb.org).
+
+U-Boot implements this DFU capability (CONFIG_DFU) with the command dfu
+(cmd/dfu.c / CONFIG_CMD_DFU) based on:
+
+- the DFU stack (common/dfu.c and common/spl/spl_dfu.c), based on the
+ USB DFU download gadget (drivers/usb/gadget/f_dfu.c)
+- The access to mediums is done in DFU backends (driver/dfu)
+
+Today the supported DFU backends are:
+
+- MMC (RAW or FAT / EXT2 / EXT3 / EXT4 file system / SKIP / SCRIPT)
+- NAND
+- RAM
+- SF (serial flash)
+- MTD (all MTD device: NAND, SPI-NOR, SPI-NAND,...)
+- virtual
+
+These DFU backends are also used by
+
+- the dfutftp (see README.dfutftp)
+- the thordown command (cmd/thordown.c and gadget/f_thor.c)
+
+The "virtual" backend is a generic DFU backend to support a board specific
+target (for example OTP), only based on the weak functions:
+
+- dfu_write_medium_virt
+- dfu_get_medium_size_virt
+- dfu_read_medium_virt
+
+Configuration Options
+---------------------
+
+The following configuration option are relevant for device firmware upgrade:
+
+* CONFIG_DFU
+* CONFIG_DFU_OVER_USB
+* CONFIG_DFU_MMC
+* CONFIG_DFU_MTD
+* CONFIG_DFU_NAND
+* CONFIG_DFU_RAM
+* CONFIG_DFU_SF
+* CONFIG_DFU_SF_PART
+* CONFIG_DFU_TIMEOUT
+* CONFIG_DFU_VIRTUAL
+* CONFIG_CMD_DFU
+
+Environment variables
+---------------------
+
+The dfu command uses 3 environments variables:
+
+dfu_alt_info
+ The DFU setting for the USB download gadget with a semicolon separated
+ string of information on each alternate::
+
+ dfu_alt_info="<alt1>;<alt2>;....;<altN>"
+
+ When several devices are used, the format is:
+
+ - <interface> <dev>'='alternate list (';' separated)
+ - each interface is separated by '&'::
+
+ dfu_alt_info=\
+ "<interface1> <dev1>=<alt1>;....;<altN>&"\
+ "<interface2> <dev2>=<altN+1>;....;<altM>&"\
+ ...\
+ "<interfaceI> <devI>=<altY+1>;....;<altZ>&"
+
+dfu_bufsiz
+ size of the DFU buffer, when absent, defaults to
+ CONFIG_SYS_DFU_DATA_BUF_SIZE (8 MiB by default)
+
+dfu_hash_algo
+ name of the hash algorithm to use
+
+Commands
+--------
+
+dfu <USB_controller> [<interface> <dev>] list
+ list the alternate device defined in *dfu_alt_info*
+
+dfu <USB_controller> [<interface> <dev>] [<timeout>]
+ start the dfu stack on the USB instance with the selected medium
+ backend and use the *dfu_alt_info* variable to configure the
+ alternate setting and link each one with the medium
+ The dfu command continue until receive a ^C in console or
+ a DFU detach transaction from HOST. If CONFIG_DFU_TIMEOUT option
+ is enabled and <timeout> parameter is present in the command line,
+ the DFU operation will be aborted automatically after <timeout>
+ seconds of waiting remote to initiate DFU session.
+
+The possible values of <interface> are (with <USB controller> = 0 in the dfu
+command example)
+
+mmc
+ for eMMC and SD card::
+
+ dfu 0 mmc <dev>
+
+ each element in *dfu_alt_info* being
+
+ * <name> raw <offset> <size> [mmcpart <num>] raw access to mmc device
+ * <name> part <dev> <part_id> [mmcpart <num>] raw access to partition
+ * <name> fat <dev> <part_id> [mmcpart <num>] file in FAT partition
+ * <name> ext4 <dev> <part_id> [mmcpart <num>] file in EXT4 partition
+ * <name> skip 0 0 ignore flashed data
+ * <name> script 0 0 execute commands in shell
+
+ with
+
+ partid
+ being the GPT or DOS partition index,
+ num
+ being the eMMC hardware partition number.
+
+ A value of environment variable *dfu_alt_info* for eMMC could be::
+
+ u-boot raw 0x3e 0x800 mmcpart 1;bl2 raw 0x1e 0x1d mmcpart 1
+
+ A value of environment variable *dfu_alt_info* for SD card could be::
+
+ u-boot raw 0x80 0x800;uImage ext4 0 2
+
+ If don't want to flash given image file to storage, use "skip" type
+ entity.
+
+ - It can be used to protect flashing wrong image for the specific board.
+ - Especailly, this layout will be useful when thor protocol is used,
+ which performs flashing in batch mode, where more than one file is
+ processed.
+
+ For example, if one makes a single tar file with support for the two
+ boards with u-boot-<board1>.bin and u-boot-<board2>.bin files, one
+ can use it to flash a proper u-boot image on both without a failure::
+
+ u-boot-<board1>.bin raw 0x80 0x800; u-boot-<board2>.bin skip 0 0
+
+ When flashing new system image requires do some more complex things
+ than just writing data to the storage medium, one can use 'script'
+ type. Data written to such entity will be executed as a command list
+ in the u-boot's shell. This for example allows to re-create partition
+ layout and even set new *dfu_alt_info* for the newly created paritions.
+ Such script would look like::
+
+ setenv dfu_alt_info ...
+ setenv mbr_parts ...
+ mbr write ...
+
+ Please note that this means that user will be able to execute any
+ arbitrary commands just like in the u-boot's shell.
+
+nand
+ raw slc nand device::
+
+ dfu 0 nand <dev>
+
+ each element in *dfu_alt_info* being either of
+
+ * <name> raw <offset> <size> raw access to mmc device
+ * <name> part <dev> <part_id> raw acces to partition
+ * <name> partubi <dev> <part_id> raw acces to ubi partition
+
+ with
+
+ partid
+ is the MTD partition index
+
+ram
+ raw access to ram::
+
+ dfu 0 ram <dev>
+
+ dev
+ is not used for RAM target
+
+ each element in *dfu_alt_info* being::
+
+ <name> ram <offset> <size> raw access to ram
+
+sf
+ serial flash : NOR::
+
+ cmd: dfu 0 sf <dev>
+
+ each element in *dfu_alt_info* being either of:
+
+ * <name> raw <offset> <size> raw access to sf device
+ * <name> part <dev> <part_id> raw acces to partition
+ * <name> partubi <dev> <part_id> raw acces to ubi partition
+
+ with
+
+ partid
+ is the MTD partition index
+
+mtd
+ all MTD device: NAND, SPI-NOR, SPI-NAND,...::
+
+ cmd: dfu 0 mtd <dev>
+
+ with
+
+ dev
+ the mtd identifier as defined in mtd command
+ (nand0, nor0, spi-nand0,...)
+
+ each element in *dfu_alt_info* being either of:
+
+ * <name> raw <offset> <size> forraw access to mtd device
+ * <name> part <dev> <part_id> for raw acces to partition
+ * <name> partubi <dev> <part_id> for raw acces to ubi partition
+
+ with
+
+ partid
+ is the MTD partition index
+
+virt
+ virtual flash back end for DFU
+
+ ::
+
+ cmd: dfu 0 virt <dev>
+
+ each element in *dfu_alt_info* being:
+
+ * <name>
+
+<interface> and <dev> are absent, the dfu command to use multiple devices::
+
+ cmd: dfu 0 list
+ cmd: dfu 0
+
+*dfu_alt_info* variable provides the list of <interface> <dev> with
+alternate list separated by '&' with the same format for each <alt>::
+
+ mmc <dev>=<alt1>;....;<altN>
+ nand <dev>=<alt1>;....;<altN>
+ ram <dev>=<alt1>;....;<altN>
+ sf <dev>=<alt1>;....;<altN>
+ mtd <dev>=<alt1>;....;<altN>
+ virt <dev>=<alt1>;....;<altN>
+
+Callbacks
+---------
+
+The weak callback functions can be implemented to manage specific behavior
+
+dfu_initiated_callback
+ called when the DFU transaction is started, used to initiase the device
+
+dfu_flush_callback
+ called at the end of the DFU write after DFU manifestation, used to manage
+ the device when DFU transaction is closed
+
+Host tools
+----------
+
+When U-Boot runs the dfu stack, the DFU host tools can be used
+to send/receive firmwares on each configurated alternate.
+
+For example dfu-util is a host side implementation of the DFU 1.1
+specifications(http://dfu-util.sourceforge.net/) which works with U-Boot.
+
+Usage
+-----
+
+Example 1: firmware located in eMMC or SD card, with:
+
+- alternate 1 (alt=1) for SPL partition (GPT partition 1)
+- alternate 2 (alt=2) for U-Boot partition (GPT partition 2)
+
+The U-Boot configuration is::
+
+ U-Boot> env set dfu_alt_info "spl part 0 1;u-boot part 0 2"
+
+ U-Boot> dfu 0 mmc 0 list
+ DFU alt settings list:
+ dev: eMMC alt: 0 name: spl layout: RAW_ADDR
+ dev: eMMC alt: 1 name: u-boot layout: RAW_ADDR
+
+ Boot> dfu 0 mmc 0
+
+On the Host side:
+
+list the available alternate setting::
+
+ $> dfu-util -l
+ dfu-util 0.9
+
+ Copyright 2005-2009 Weston Schmidt, Harald Welte and OpenMoko Inc.
+ Copyright 2010-2016 Tormod Volden and Stefan Schmidt
+ This program is Free Software and has ABSOLUTELY NO WARRANTY
+ Please report bugs to http://sourceforge.net/p/dfu-util/tickets/
+
+ Found DFU: [0483:5720] ver=0200, devnum=45, cfg=1, intf=0, path="3-1.3.1", \
+ alt=1, name="u-boot", serial="003A00203438510D36383238"
+ Found DFU: [0483:5720] ver=0200, devnum=45, cfg=1, intf=0, path="3-1.3.1", \
+ alt=0, name="spl", serial="003A00203438510D36383238"
+
+ To download to U-Boot, use -D option
+
+ $> dfu-util -a 0 -D u-boot-spl.bin
+ $> dfu-util -a 1 -D u-boot.bin
+
+ To upload from U-Boot, use -U option
+
+ $> dfu-util -a 0 -U u-boot-spl.bin
+ $> dfu-util -a 1 -U u-boot.bin
+
+ To request a DFU detach and reset the USB connection:
+ $> dfu-util -a 0 -e -R
+
+
+Example 2: firmware located in NOR (sf) and NAND, with:
+
+- alternate 1 (alt=1) for SPL partition (NOR GPT partition 1)
+- alternate 2 (alt=2) for U-Boot partition (NOR GPT partition 2)
+- alternate 3 (alt=3) for U-Boot-env partition (NOR GPT partition 3)
+- alternate 4 (alt=4) for UBI partition (NAND GPT partition 1)
+
+::
+
+ U-Boot> env set dfu_alt_info \
+ "sf 0:0:10000000:0=spl part 0 1;u-boot part 0 2; \
+ u-boot-env part 0 3&nand 0=UBI partubi 0,1"
+
+ U-Boot> dfu 0 list
+
+ DFU alt settings list:
+ dev: SF alt: 0 name: spl layout: RAW_ADDR
+ dev: SF alt: 1 name: ssbl layout: RAW_ADDR
+ dev: SF alt: 2 name: u-boot-env layout: RAW_ADDR
+ dev: NAND alt: 3 name: UBI layout: RAW_ADDR
+
+ U-Boot> dfu 0
+
+::
+
+ $> dfu-util -l
+ Found DFU: [0483:5720] ver=9999, devnum=96, cfg=1,\
+ intf=0, alt=3, name="UBI", serial="002700333338511934383330"
+ Found DFU: [0483:5720] ver=9999, devnum=96, cfg=1,\
+ intf=0, alt=2, name="u-boot-env", serial="002700333338511934383330"
+ Found DFU: [0483:5720] ver=9999, devnum=96, cfg=1,\
+ intf=0, alt=1, name="u-boot", serial="002700333338511934383330"
+ Found DFU: [0483:5720] ver=9999, devnum=96, cfg=1,\
+ intf=0, alt=0, name="spl", serial="002700333338511934383330"
+
+Same example with MTD backend
+
+::
+
+ U-Boot> env set dfu_alt_info \
+ "mtd nor0=spl part 1;u-boot part 2;u-boot-env part 3&"\
+ "mtd nand0=UBI partubi 1"
+
+ U-Boot> dfu 0 list
+ using id 'nor0,0'
+ using id 'nor0,1'
+ using id 'nor0,2'
+ using id 'nand0,0'
+ DFU alt settings list:
+ dev: MTD alt: 0 name: spl layout: RAW_ADDR
+ dev: MTD alt: 1 name: u-boot layout: RAW_ADDR
+ dev: MTD alt: 2 name: u-boot-env layout: RAW_ADDR
+ dev: MTD alt: 3 name: UBI layout: RAW_ADDR
+
+Example 3
+
+firmware located in SD Card (mmc) and virtual partition on OTP and PMIC not
+volatile memory
+
+- alternate 1 (alt=1) for scard
+- alternate 2 (alt=2) for OTP (virtual)
+- alternate 3 (alt=3) for PMIC NVM (virtual)
+
+::
+
+ U-Boot> env set dfu_alt_info \
+ "mmc 0=sdcard raw 0 0x100000&"\
+ "virt 0=otp" \
+ "virt 1=pmic"
+
+::
+
+ U-Boot> dfu 0 list
+ DFU alt settings list:
+ dev: eMMC alt: 0 name: sdcard layout: RAW_ADDR
+ dev: VIRT alt: 1 name: otp layout: RAW_ADDR
+ dev: VIRT alt: 2 name: pmic layout: RAW_ADDR
diff --git a/doc/usage/index.rst b/doc/usage/index.rst
index a8842bf..6c59bba 100644
--- a/doc/usage/index.rst
+++ b/doc/usage/index.rst
@@ -4,8 +4,10 @@
.. toctree::
:maxdepth: 1
+ dfu
fdt_overlays
netconsole
+ partitions
Shell commands
--------------
@@ -13,6 +15,7 @@
.. toctree::
:maxdepth: 1
+ addrmap
base
bootefi
booti
diff --git a/doc/usage/partitions.rst b/doc/usage/partitions.rst
new file mode 100644
index 0000000..2c1a12b
--- /dev/null
+++ b/doc/usage/partitions.rst
@@ -0,0 +1,80 @@
+.. SPDX-License-Identifier: GPL-2.0+
+.. _partitions:
+
+Partitions
+==========
+
+Synopsis
+--------
+
+::
+
+ <command> <interface> [devnum][.hwpartnum][:partnum|#partname]
+
+Description
+-----------
+
+Many U-Boot commands allow specifying partitions (or whole disks) using a
+generic syntax.
+
+interface
+ The interface used to access the partition's device, like ``mmc`` or
+ ``scsi``. For a full list of supported interfaces, consult the
+ ``if_typename_str`` array in ``drivers/block/blk-uclass.c``
+
+devnum
+ The device number. This defaults to 0.
+
+hwpartnum
+ The hardware partition number. All devices have at least one hardware
+ partition. On most devices, hardware partition 0 specifies the whole
+ device. On eMMC devices, hardware partition 0 is the user partition,
+ hardware partitions 1 and 2 are the boot partitions, hardware partition
+ 3 is the RPMB partition, and further partitions are general-purpose
+ user-created partitions. The default hardware partition number is 0.
+
+partnum
+ The partition number, starting from 1. The partition number 0 specifies
+ that the whole device is to be used as one "partition."
+
+partname
+ The partition name. This is the partition label for GPT partitions. For
+ MBR partitions, the following syntax is used::
+
+ <devtype><devletter><partnum>
+
+ devtype
+ A device type like ``mmcsd`` or ``hd``. See the
+ ``part_set_generic_name`` function in ``disk/part.c`` for a
+ complete list.
+
+ devletter
+ The device number as an offset from ``a``. For example, device
+ number 2 would have a device letter of ``c``.
+
+ partnum
+ The partition number. This is the same as above.
+
+If neither ``partname`` nor ``partnum`` is specified and there is a partition
+table, then partition 1 is used. If there is no partition table, then the whole
+device is used as one "partition." If none of ``devnum``, ``hwpartnum``,
+``partnum``, or ``partname`` is specified, or only ``-`` is specified, then
+``devnum`` defaults to the value of the ``bootdevice`` environmental variable.
+
+Examples
+--------
+
+List the root directory contents on MMC device 2, hardware partition 1,
+and partition number 3::
+
+ ls mmc 2.1:3 /
+
+Load ``/kernel.itb`` to address ``0x80000000`` from SCSI device 0, hardware partition
+0, and the partition labeled ``boot``::
+
+ load scsi #boot 0x80000000 /kernel.itb
+
+Print the partition UUID of the SATA device ``$bootdevice``, hardware partition
+0, and partition number 0::
+
+ part uuid sata -
diff --git a/drivers/adc/meson-saradc.c b/drivers/adc/meson-saradc.c
index 21db558..1a45a3a 100644
--- a/drivers/adc/meson-saradc.c
+++ b/drivers/adc/meson-saradc.c
@@ -18,6 +18,7 @@
#include <linux/delay.h>
#include <linux/math64.h>
#include <linux/bitfield.h>
+#include <power/regulator.h>
#define MESON_SAR_ADC_REG0 0x00
#define MESON_SAR_ADC_REG0_PANEL_DETECT BIT(31)
@@ -656,7 +657,10 @@
static int meson_saradc_probe(struct udevice *dev)
{
+ struct adc_uclass_plat *uc_pdata = dev_get_uclass_plat(dev);
struct meson_saradc_priv *priv = dev_get_priv(dev);
+ struct udevice *vref;
+ int vref_uv;
int ret;
ret = regmap_init_mem(dev_ofnode(dev), &priv->regmap);
@@ -675,6 +679,23 @@
priv->active_channel = -1;
+ ret = device_get_supply_regulator(dev, "vref-supply", &vref);
+ if (ret) {
+ printf("can't get vref-supply: %d\n", ret);
+ return ret;
+ }
+
+ vref_uv = regulator_get_value(vref);
+ if (vref_uv < 0) {
+ printf("can't get vref-supply value: %d\n", vref_uv);
+ return vref_uv;
+ }
+
+ /* VDD supplied by common vref pin */
+ uc_pdata->vdd_supply = vref;
+ uc_pdata->vdd_microvolts = vref_uv;
+ uc_pdata->vss_microvolts = 0;
+
return 0;
}
diff --git a/drivers/block/sandbox.c b/drivers/block/sandbox.c
index 9d7d68c..e2f229b 100644
--- a/drivers/block/sandbox.c
+++ b/drivers/block/sandbox.c
@@ -231,6 +231,18 @@
}
#ifdef CONFIG_BLK
+
+int sandbox_host_unbind(struct udevice *dev)
+{
+ struct host_block_dev *host_dev;
+
+ /* Data validity is checked in host_dev_bind() */
+ host_dev = dev_get_plat(dev);
+ os_close(host_dev->fd);
+
+ return 0;
+}
+
static const struct blk_ops sandbox_host_blk_ops = {
.read = host_block_read,
.write = host_block_write,
@@ -240,6 +252,7 @@
.name = "sandbox_host_blk",
.id = UCLASS_BLK,
.ops = &sandbox_host_blk_ops,
+ .unbind = sandbox_host_unbind,
.plat_auto = sizeof(struct host_block_dev),
};
#else
diff --git a/drivers/button/Kconfig b/drivers/button/Kconfig
index 6b3ec7e..6db3c5e 100644
--- a/drivers/button/Kconfig
+++ b/drivers/button/Kconfig
@@ -9,6 +9,14 @@
can provide access to board-specific buttons. Use of the device tree
for configuration is encouraged.
+config BUTTON_ADC
+ bool "Button adc"
+ depends on BUTTON
+ help
+ Enable support for buttons which are connected to Analog to Digital
+ Converter device. The ADC driver must use driver model. Buttons are
+ configured using the device tree.
+
config BUTTON_GPIO
bool "Button gpio"
depends on BUTTON
diff --git a/drivers/button/Makefile b/drivers/button/Makefile
index fcc10eb..bbd18af 100644
--- a/drivers/button/Makefile
+++ b/drivers/button/Makefile
@@ -3,4 +3,5 @@
# Copyright (C) 2020 Philippe Reynes <philippe.reynes@softathome.com>
obj-$(CONFIG_BUTTON) += button-uclass.o
+obj-$(CONFIG_BUTTON_ADC) += button-adc.o
obj-$(CONFIG_BUTTON_GPIO) += button-gpio.o
diff --git a/drivers/button/button-adc.c b/drivers/button/button-adc.c
new file mode 100644
index 0000000..fd896c7
--- /dev/null
+++ b/drivers/button/button-adc.c
@@ -0,0 +1,146 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (C) 2021 Samsung Electronics Co., Ltd.
+ * http://www.samsung.com
+ * Author: Marek Szyprowski <m.szyprowski@samsung.com>
+ */
+
+#include <common.h>
+#include <adc.h>
+#include <button.h>
+#include <log.h>
+#include <dm.h>
+#include <dm/lists.h>
+#include <dm/of_access.h>
+#include <dm/uclass-internal.h>
+
+/**
+ * struct button_adc_priv - private data for button-adc driver.
+ *
+ * @adc: Analog to Digital Converter device to which button is connected.
+ * @channel: channel of the ADC device to probe the button state.
+ * @min: minimal uV value to consider button as pressed.
+ * @max: maximal uV value to consider button as pressed.
+ */
+struct button_adc_priv {
+ struct udevice *adc;
+ int channel;
+ int min;
+ int max;
+};
+
+static enum button_state_t button_adc_get_state(struct udevice *dev)
+{
+ struct button_adc_priv *priv = dev_get_priv(dev);
+ unsigned int val;
+ int ret, uV;
+
+ ret = adc_start_channel(priv->adc, priv->channel);
+ if (ret)
+ return ret;
+
+ ret = adc_channel_data(priv->adc, priv->channel, &val);
+ if (ret)
+ return ret;
+
+ ret = adc_raw_to_uV(priv->adc, val, &uV);
+ if (ret)
+ return ret;
+
+ return (uV >= priv->min && uV < priv->max) ? BUTTON_ON : BUTTON_OFF;
+}
+
+static int button_adc_of_to_plat(struct udevice *dev)
+{
+ struct button_uc_plat *uc_plat = dev_get_uclass_plat(dev);
+ struct button_adc_priv *priv = dev_get_priv(dev);
+ struct ofnode_phandle_args args;
+ u32 threshold, up_threshold, t;
+ ofnode node;
+ int ret;
+
+ /* Ignore the top-level button node */
+ if (!uc_plat->label)
+ return 0;
+
+ ret = dev_read_phandle_with_args(dev->parent, "io-channels",
+ "#io-channel-cells", 0, 0, &args);
+ if (ret)
+ return ret;
+
+ ret = uclass_get_device_by_ofnode(UCLASS_ADC, args.node, &priv->adc);
+ if (ret)
+ return ret;
+
+ ret = ofnode_read_u32(dev_ofnode(dev->parent),
+ "keyup-threshold-microvolt", &up_threshold);
+ if (ret)
+ return ret;
+
+ ret = ofnode_read_u32(dev_ofnode(dev), "press-threshold-microvolt",
+ &threshold);
+ if (ret)
+ return ret;
+
+ dev_for_each_subnode(node, dev->parent) {
+ ret = ofnode_read_u32(node, "press-threshold-microvolt", &t);
+ if (ret)
+ return ret;
+
+ if (t > threshold)
+ up_threshold = t;
+ }
+
+ priv->channel = args.args[0];
+ priv->min = threshold;
+ priv->max = up_threshold;
+
+ return ret;
+}
+
+static int button_adc_bind(struct udevice *parent)
+{
+ struct udevice *dev;
+ ofnode node;
+ int ret;
+
+ dev_for_each_subnode(node, parent) {
+ struct button_uc_plat *uc_plat;
+ const char *label;
+
+ label = ofnode_read_string(node, "label");
+ if (!label) {
+ debug("%s: node %s has no label\n", __func__,
+ ofnode_get_name(node));
+ return -EINVAL;
+ }
+ ret = device_bind_driver_to_node(parent, "button_adc",
+ ofnode_get_name(node),
+ node, &dev);
+ if (ret)
+ return ret;
+ uc_plat = dev_get_uclass_plat(dev);
+ uc_plat->label = label;
+ }
+
+ return 0;
+}
+
+static const struct button_ops button_adc_ops = {
+ .get_state = button_adc_get_state,
+};
+
+static const struct udevice_id button_adc_ids[] = {
+ { .compatible = "adc-keys" },
+ { }
+};
+
+U_BOOT_DRIVER(button_adc) = {
+ .name = "button_adc",
+ .id = UCLASS_BUTTON,
+ .of_match = button_adc_ids,
+ .ops = &button_adc_ops,
+ .priv_auto = sizeof(struct button_adc_priv),
+ .bind = button_adc_bind,
+ .of_to_plat = button_adc_of_to_plat,
+};
diff --git a/drivers/clk/clk_stm32mp1.c b/drivers/clk/clk_stm32mp1.c
index 848e33f..0c0ef36 100644
--- a/drivers/clk/clk_stm32mp1.c
+++ b/drivers/clk/clk_stm32mp1.c
@@ -250,7 +250,7 @@
enum stm32mp1_parent_id {
/*
* _HSI, _HSE, _CSI, _LSI, _LSE should not be moved
- * they are used as index in osc[] as entry point
+ * they are used as index in osc_clk[] as clock reference
*/
_HSI,
_HSE,
@@ -430,8 +430,7 @@
struct stm32mp1_clk_priv {
fdt_addr_t base;
const struct stm32mp1_clk_data *data;
- ulong osc[NB_OSC];
- struct udevice *osc_dev[NB_OSC];
+ struct clk osc_clk[NB_OSC];
};
#define STM32MP1_CLK(off, b, idx, s) \
@@ -790,7 +789,7 @@
return 0;
}
- return priv->osc[idx];
+ return clk_get_rate(&priv->osc_clk[idx]);
}
static int stm32mp1_clk_get_id(struct stm32mp1_clk_priv *priv, unsigned long id)
@@ -1545,7 +1544,7 @@
break;
if (hsidiv == 4) {
- log_err("clk-hsi frequency invalid");
+ log_err("hsi frequency invalid");
return -1;
}
@@ -1952,13 +1951,13 @@
* switch ON oscillator found in device-tree,
* HSI already ON after bootrom
*/
- if (priv->osc[_LSI])
+ if (clk_valid(&priv->osc_clk[_LSI]))
stm32mp1_lsi_set(rcc, 1);
- if (priv->osc[_LSE]) {
+ if (clk_valid(&priv->osc_clk[_LSE])) {
int bypass, digbyp;
u32 lsedrv;
- struct udevice *dev = priv->osc_dev[_LSE];
+ struct udevice *dev = priv->osc_clk[_LSE].dev;
bypass = dev_read_bool(dev, "st,bypass");
digbyp = dev_read_bool(dev, "st,digbypass");
@@ -1969,9 +1968,9 @@
stm32mp1_lse_enable(rcc, bypass, digbyp, lsedrv);
}
- if (priv->osc[_HSE]) {
+ if (clk_valid(&priv->osc_clk[_HSE])) {
int bypass, digbyp, css;
- struct udevice *dev = priv->osc_dev[_HSE];
+ struct udevice *dev = priv->osc_clk[_HSE].dev;
bypass = dev_read_bool(dev, "st,bypass");
digbyp = dev_read_bool(dev, "st,digbypass");
@@ -1996,8 +1995,8 @@
/* configure HSIDIV */
dev_dbg(dev, "configure HSIDIV\n");
- if (priv->osc[_HSI]) {
- stm32mp1_hsidiv(rcc, priv->osc[_HSI]);
+ if (clk_valid(&priv->osc_clk[_HSI])) {
+ stm32mp1_hsidiv(rcc, clk_get_rate(&priv->osc_clk[_HSI]));
stgen_config(priv);
}
@@ -2043,7 +2042,7 @@
}
/* wait LSE ready before to use it */
- if (priv->osc[_LSE])
+ if (clk_valid(&priv->osc_clk[_LSE]))
stm32mp1_lse_wait(rcc);
/* configure with expected clock source */
@@ -2082,7 +2081,7 @@
dev_dbg(dev, "oscillator off\n");
/* switch OFF HSI if not found in device-tree */
- if (!priv->osc[_HSI])
+ if (!clk_valid(&priv->osc_clk[_HSI]))
stm32mp1_hsi_set(rcc, 0);
/* Software Self-Refresh mode (SSR) during DDR initilialization */
@@ -2178,40 +2177,25 @@
return -EINVAL;
}
-static void stm32mp1_osc_clk_init(const char *name,
- struct stm32mp1_clk_priv *priv,
- int index)
-{
- struct clk clk;
- struct udevice *dev = NULL;
-
- priv->osc[index] = 0;
- clk.id = 0;
- if (!uclass_get_device_by_name(UCLASS_CLK, name, &dev)) {
- if (clk_request(dev, &clk))
- log_err("%s request", name);
- else
- priv->osc[index] = clk_get_rate(&clk);
- }
- priv->osc_dev[index] = dev;
-}
-
static void stm32mp1_osc_init(struct udevice *dev)
{
struct stm32mp1_clk_priv *priv = dev_get_priv(dev);
int i;
const char *name[NB_OSC] = {
- [_LSI] = "clk-lsi",
- [_LSE] = "clk-lse",
- [_HSI] = "clk-hsi",
- [_HSE] = "clk-hse",
- [_CSI] = "clk-csi",
+ [_LSI] = "lsi",
+ [_LSE] = "lse",
+ [_HSI] = "hsi",
+ [_HSE] = "hse",
+ [_CSI] = "csi",
[_I2S_CKIN] = "i2s_ckin",
};
for (i = 0; i < NB_OSC; i++) {
- stm32mp1_osc_clk_init(name[i], priv, i);
- dev_dbg(dev, "%d: %s => %x\n", i, name[i], (u32)priv->osc[i]);
+ if (clk_get_by_name(dev, name[i], &priv->osc_clk[i]))
+ dev_dbg(dev, "No source clock \"%s\"", name[i]);
+ else
+ dev_dbg(dev, "%s clock rate: %luHz\n",
+ name[i], clk_get_rate(&priv->osc_clk[i]));
}
}
diff --git a/drivers/clk/clk_versal.c b/drivers/clk/clk_versal.c
index 908bc75..62523d2 100644
--- a/drivers/clk/clk_versal.c
+++ b/drivers/clk/clk_versal.c
@@ -718,9 +718,20 @@
return clk_rate;
}
+static int versal_clk_enable(struct clk *clk)
+{
+ struct versal_clk_priv *priv = dev_get_priv(clk->dev);
+ u32 clk_id;
+
+ clk_id = priv->clk[clk->id].clk_id;
+
+ return xilinx_pm_request(PM_CLOCK_ENABLE, clk_id, 0, 0, 0, NULL);
+}
+
static struct clk_ops versal_clk_ops = {
.set_rate = versal_clk_set_rate,
.get_rate = versal_clk_get_rate,
+ .enable = versal_clk_enable,
};
static const struct udevice_id versal_clk_ids[] = {
diff --git a/drivers/clk/clk_zynq.c b/drivers/clk/clk_zynq.c
index 3e33209..18915c3 100644
--- a/drivers/clk/clk_zynq.c
+++ b/drivers/clk/clk_zynq.c
@@ -445,11 +445,21 @@
}
#endif
+static int dummy_enable(struct clk *clk)
+{
+ /*
+ * Add implementation but by default all clocks are enabled
+ * after power up which is only one supported case now.
+ */
+ return 0;
+}
+
static struct clk_ops zynq_clk_ops = {
.get_rate = zynq_clk_get_rate,
#ifndef CONFIG_SPL_BUILD
.set_rate = zynq_clk_set_rate,
#endif
+ .enable = dummy_enable,
};
static int zynq_clk_probe(struct udevice *dev)
diff --git a/drivers/clk/clk_zynqmp.c b/drivers/clk/clk_zynqmp.c
index e8acca0..609d8e3 100644
--- a/drivers/clk/clk_zynqmp.c
+++ b/drivers/clk/clk_zynqmp.c
@@ -199,6 +199,8 @@
return CRF_APB_DDR_CTRL;
case qspi_ref:
return CRL_APB_QSPI_REF_CTRL;
+ case usb3_dual_ref:
+ return CRL_APB_USB3_DUAL_REF_CTRL;
case gem0_ref:
return CRL_APB_GEM0_REF_CTRL;
case gem1_ref:
@@ -207,6 +209,10 @@
return CRL_APB_GEM2_REF_CTRL;
case gem3_ref:
return CRL_APB_GEM3_REF_CTRL;
+ case usb0_bus_ref:
+ return CRL_APB_USB0_BUS_REF_CTRL;
+ case usb1_bus_ref:
+ return CRL_APB_USB1_BUS_REF_CTRL;
case uart0_ref:
return CRL_APB_UART0_REF_CTRL;
case uart1_ref:
@@ -699,9 +705,52 @@
return 0;
}
+static int zynqmp_clk_enable(struct clk *clk)
+{
+ enum zynqmp_clk id = clk->id;
+ u32 reg, clk_ctrl, clkact_shift, mask;
+ int ret;
+
+ reg = zynqmp_clk_get_register(id);
+ debug("%s, clk_id:%x, clk_base:0x%x\n", __func__, id, reg);
+
+ switch (id) {
+ case usb0_bus_ref ... usb1:
+ clkact_shift = 25;
+ mask = 0x1;
+ break;
+ case gem0_ref ... gem3_ref:
+ clkact_shift = 25;
+ mask = 0x3;
+ break;
+ case qspi_ref ... can1_ref:
+ clkact_shift = 24;
+ mask = 0x1;
+ break;
+ default:
+ return -ENXIO;
+ }
+
+ ret = zynqmp_mmio_read(reg, &clk_ctrl);
+ if (ret) {
+ printf("%s mio read fail\n", __func__);
+ return -EIO;
+ }
+
+ clk_ctrl |= (mask << clkact_shift);
+ ret = zynqmp_mmio_write(reg, mask << clkact_shift, clk_ctrl);
+ if (ret) {
+ printf("%s mio write fail\n", __func__);
+ return -EIO;
+ }
+
+ return ret;
+}
+
static struct clk_ops zynqmp_clk_ops = {
.set_rate = zynqmp_clk_set_rate,
.get_rate = zynqmp_clk_get_rate,
+ .enable = zynqmp_clk_enable,
};
static const struct udevice_id zynqmp_clk_ids[] = {
diff --git a/drivers/core/Kconfig b/drivers/core/Kconfig
index 00554af..1eccac2 100644
--- a/drivers/core/Kconfig
+++ b/drivers/core/Kconfig
@@ -329,15 +329,6 @@
things like generating device-specific tables and returning the ACPI
name of a device.
-config INTEL_ACPIGEN
- bool "Support ACPI table generation for Intel SoCs"
- depends on ACPIGEN
- help
- This option adds some functions used for programatic generation of
- ACPI tables on Intel SoCs. This provides features for writing CPU
- information such as P states and T stages. Also included is a way
- to create a GNVS table and set it up.
-
config BOUNCE_BUFFER
bool "Include bounce buffer API"
help
diff --git a/drivers/core/device.c b/drivers/core/device.c
index 6251349..81f6880 100644
--- a/drivers/core/device.c
+++ b/drivers/core/device.c
@@ -92,15 +92,19 @@
if (auto_seq && !(uc->uc_drv->flags & DM_UC_FLAG_NO_AUTO_SEQ))
dev->seq_ = uclass_find_next_free_seq(uc);
+ /* Check if we need to allocate plat */
if (drv->plat_auto) {
bool alloc = !plat;
+ /*
+ * For of-platdata, we try use the existing data, but if
+ * plat_auto is larger, we must allocate a new space
+ */
if (CONFIG_IS_ENABLED(OF_PLATDATA)) {
- if (of_plat_size) {
+ if (of_plat_size)
dev_or_flags(dev, DM_FLAG_OF_PLATDATA);
- if (of_plat_size < drv->plat_auto)
- alloc = true;
- }
+ if (of_plat_size < drv->plat_auto)
+ alloc = true;
}
if (alloc) {
dev_or_flags(dev, DM_FLAG_ALLOC_PDATA);
@@ -109,6 +113,11 @@
ret = -ENOMEM;
goto fail_alloc1;
}
+
+ /*
+ * For of-platdata, copy the old plat into the new
+ * space
+ */
if (CONFIG_IS_ENABLED(OF_PLATDATA) && plat)
memcpy(ptr, plat, of_plat_size);
dev_set_plat(dev, ptr);
@@ -128,9 +137,8 @@
if (parent) {
size = parent->driver->per_child_plat_auto;
- if (!size) {
+ if (!size)
size = parent->uclass->uc_drv->per_child_plat_auto;
- }
if (size) {
dev_or_flags(dev, DM_FLAG_ALLOC_PARENT_PDATA);
ptr = calloc(1, size);
@@ -200,14 +208,18 @@
}
}
fail_alloc3:
- if (dev_get_flags(dev) & DM_FLAG_ALLOC_UCLASS_PDATA) {
- free(dev_get_uclass_plat(dev));
- dev_set_uclass_plat(dev, NULL);
+ if (CONFIG_IS_ENABLED(DM_DEVICE_REMOVE)) {
+ if (dev_get_flags(dev) & DM_FLAG_ALLOC_UCLASS_PDATA) {
+ free(dev_get_uclass_plat(dev));
+ dev_set_uclass_plat(dev, NULL);
+ }
}
fail_alloc2:
- if (dev_get_flags(dev) & DM_FLAG_ALLOC_PDATA) {
- free(dev_get_plat(dev));
- dev_set_plat(dev, NULL);
+ if (CONFIG_IS_ENABLED(DM_DEVICE_REMOVE)) {
+ if (dev_get_flags(dev) & DM_FLAG_ALLOC_PDATA) {
+ free(dev_get_plat(dev));
+ dev_set_plat(dev, NULL);
+ }
}
fail_alloc1:
devres_release_all(dev);
diff --git a/drivers/ddr/altera/Kconfig b/drivers/ddr/altera/Kconfig
index 8f590dc..4660d20 100644
--- a/drivers/ddr/altera/Kconfig
+++ b/drivers/ddr/altera/Kconfig
@@ -1,8 +1,8 @@
config SPL_ALTERA_SDRAM
bool "SoCFPGA DDR SDRAM driver in SPL"
depends on SPL
- depends on TARGET_SOCFPGA_GEN5 || TARGET_SOCFPGA_ARRIA10 || TARGET_SOCFPGA_STRATIX10 || TARGET_SOCFPGA_AGILEX
- select RAM if TARGET_SOCFPGA_GEN5 || TARGET_SOCFPGA_STRATIX10 || TARGET_SOCFPGA_AGILEX
- select SPL_RAM if TARGET_SOCFPGA_GEN5 || TARGET_SOCFPGA_STRATIX10 || TARGET_SOCFPGA_AGILEX
+ depends on TARGET_SOCFPGA_GEN5 || TARGET_SOCFPGA_ARRIA10 || TARGET_SOCFPGA_SOC64
+ select RAM if TARGET_SOCFPGA_GEN5 || TARGET_SOCFPGA_SOC64
+ select SPL_RAM if TARGET_SOCFPGA_GEN5 || TARGET_SOCFPGA_SOC64
help
Enable DDR SDRAM controller for the SoCFPGA devices.
diff --git a/drivers/ddr/altera/sequencer.c b/drivers/ddr/altera/sequencer.c
index 2dbde49..6b9b2e9 100644
--- a/drivers/ddr/altera/sequencer.c
+++ b/drivers/ddr/altera/sequencer.c
@@ -3202,13 +3202,6 @@
/* Centre DM */
debug_cond(DLEVEL >= 2, "%s:%d write_center: DM\n", __func__, __LINE__);
- /*
- * Set the left and right edge of each bit to an illegal value.
- * Use (seq->iocfg->io_out1_delay_max + 1) as an illegal value.
- */
- left_edge[0] = seq->iocfg->io_out1_delay_max + 1;
- right_edge[0] = seq->iocfg->io_out1_delay_max + 1;
-
/* Search for the/part of the window with DM shift. */
search_window(seq, 1, rank_bgn, write_group, &bgn_curr, &end_curr,
&bgn_best, &end_best, &win_best, 0);
diff --git a/drivers/ddr/marvell/a38x/ddr3_debug.c b/drivers/ddr/marvell/a38x/ddr3_debug.c
index 22e0cc4..f5fc964 100644
--- a/drivers/ddr/marvell/a38x/ddr3_debug.c
+++ b/drivers/ddr/marvell/a38x/ddr3_debug.c
@@ -6,7 +6,6 @@
#include "ddr3_init.h"
#include "mv_ddr_training_db.h"
#include "mv_ddr_regs.h"
-#include <log.h>
u8 is_reg_dump = 0;
u8 debug_pbs = DEBUG_LEVEL_ERROR;
diff --git a/drivers/ddr/marvell/a38x/ddr3_init.c b/drivers/ddr/marvell/a38x/ddr3_init.c
index a971cc1..f878b45 100644
--- a/drivers/ddr/marvell/a38x/ddr3_init.c
+++ b/drivers/ddr/marvell/a38x/ddr3_init.c
@@ -77,9 +77,6 @@
return status;
}
-#if defined(CONFIG_PHY_STATIC_PRINT)
- mv_ddr_phy_static_print();
-#endif
/* Post MC/PHY initializations */
mv_ddr_post_training_soc_config(ddr_type);
@@ -104,6 +101,7 @@
static int mv_ddr_training_params_set(u8 dev_num)
{
struct tune_train_params params;
+ struct mv_ddr_topology_map *tm = mv_ddr_topology_map_get();
int status;
u32 cs_num;
int ck_delay;
@@ -136,6 +134,10 @@
if (ck_delay > 0)
params.ck_delay = ck_delay;
+ /* Use platform specific override ODT value */
+ if (tm->odt_config)
+ params.g_odt_config = tm->odt_config;
+
status = ddr3_tip_tune_training_params(dev_num, ¶ms);
if (MV_OK != status) {
printf("%s Training Sequence - FAILED\n", ddr_type);
diff --git a/drivers/ddr/marvell/a38x/ddr3_training.c b/drivers/ddr/marvell/a38x/ddr3_training.c
index 34cc170..2512b58 100644
--- a/drivers/ddr/marvell/a38x/ddr3_training.c
+++ b/drivers/ddr/marvell/a38x/ddr3_training.c
@@ -7,8 +7,6 @@
#include "mv_ddr_common.h"
#include "mv_ddr_training_db.h"
#include "mv_ddr_regs.h"
-#include <log.h>
-#include <linux/delay.h>
#define GET_CS_FROM_MASK(mask) (cs_mask2_num[mask])
#define CS_CBE_VALUE(cs_num) (cs_cbe_reg[cs_num])
@@ -143,6 +141,7 @@
{0x15a4, 0x0, MASK_ALL_BITS},
{0x15a8, 0x0, MASK_ALL_BITS},
{0x15ac, 0x0, MASK_ALL_BITS},
+ {0x1600, 0x0, MASK_ALL_BITS},
{0x1604, 0x0, MASK_ALL_BITS},
{0x1608, 0x0, MASK_ALL_BITS},
{0x160c, 0x0, MASK_ALL_BITS},
@@ -206,7 +205,6 @@
if (tm->interface_params[0].as_bus_params[sphy].
is_ck_swap == 1 && sphy == 0) {
/* TODO: move this code to per platform one */
-#if defined(CONFIG_ARMADA_38X) || defined(CONFIG_ARMADA_39X)
/* clock swap for both cs0 and cs1 */
data = (INVERT_PAD << INV_PAD2_OFFS |
INVERT_PAD << INV_PAD6_OFFS |
@@ -218,9 +216,6 @@
DDR_PHY_CONTROL,
PHY_CTRL_PHY_REG,
data, data);
-#else /* !CONFIG_ARMADA_38X && !CONFIG_ARMADA_39X && !A70X0 && !A80X0 && !A3900 */
-#pragma message "unknown platform to configure ddr clock swap"
-#endif
}
}
@@ -1569,6 +1564,8 @@
val = ((cl_mask_table[cl_value] & 0x1) << 2) |
((cl_mask_table[cl_value] & 0xe) << 3);
+ cs_mask[0] = 0xc;
+
CHECK_STATUS(ddr3_tip_write_mrs_cmd(dev_num, cs_mask, MR_CMD0,
val, (0x7 << 4) | (0x1 << 2)));
@@ -2011,9 +2008,7 @@
static int ddr3_tip_ddr3_training_main_flow(u32 dev_num)
{
/* TODO: enable this functionality for other platforms */
-#if defined(CONFIG_ARMADA_38X) || defined(CONFIG_ARMADA_39X)
struct init_cntr_param init_cntr_prm;
-#endif
int ret = MV_OK;
int adll_bypass_flag = 0;
u32 if_id;
@@ -2047,7 +2042,6 @@
}
/* TODO: enable this functionality for other platforms */
-#if defined(CONFIG_ARMADA_38X) || defined(CONFIG_ARMADA_39X)
if (is_adll_calib_before_init != 0) {
DEBUG_TRAINING_IP(DEBUG_LEVEL_INFO,
("with adll calib before init\n"));
@@ -2078,7 +2072,6 @@
return MV_FAIL;
}
}
-#endif
ret = adll_calibration(dev_num, ACCESS_TYPE_MULTICAST, 0, freq);
if (ret != MV_OK) {
@@ -2902,3 +2895,4 @@
return odt_n;
}
+
diff --git a/drivers/ddr/marvell/a38x/ddr3_training_db.c b/drivers/ddr/marvell/a38x/ddr3_training_db.c
index b2f11a8..6aa7b60 100644
--- a/drivers/ddr/marvell/a38x/ddr3_training_db.c
+++ b/drivers/ddr/marvell/a38x/ddr3_training_db.c
@@ -833,6 +833,9 @@
pattern = pattern_table_get_isi_word16(index);
break;
default:
+ if (((int)type == 29) || ((int)type == 30))
+ break;
+
printf("error: %s: unsupported pattern type [%d] found\n",
__func__, (int)type);
pattern = 0;
diff --git a/drivers/ddr/marvell/a38x/ddr3_training_ip_def.h b/drivers/ddr/marvell/a38x/ddr3_training_ip_def.h
index 2a68669..8765df7c 100644
--- a/drivers/ddr/marvell/a38x/ddr3_training_ip_def.h
+++ b/drivers/ddr/marvell/a38x/ddr3_training_ip_def.h
@@ -80,6 +80,8 @@
#define ADDR_SIZE_2GB 0x10000000
#define ADDR_SIZE_4GB 0x20000000
#define ADDR_SIZE_8GB 0x40000000
+#define ADDR_SIZE_16GB 0x80000000
+
enum hws_edge_compare {
EDGE_PF,
diff --git a/drivers/ddr/marvell/a38x/ddr3_training_ip_engine.c b/drivers/ddr/marvell/a38x/ddr3_training_ip_engine.c
index 979f353..102f9bd 100644
--- a/drivers/ddr/marvell/a38x/ddr3_training_ip_engine.c
+++ b/drivers/ddr/marvell/a38x/ddr3_training_ip_engine.c
@@ -6,8 +6,6 @@
#include "ddr3_init.h"
#include "mv_ddr_regs.h"
#include "ddr_training_ip_db.h"
-#include <image.h>
-#include <linux/delay.h>
#define PATTERN_1 0x55555555
#define PATTERN_2 0xaaaaaaaa
@@ -614,9 +612,9 @@
MASK_ALL_BITS));
}
- CHECK_STATUS(ddr3_tip_if_write(dev_num, access_type, if_id,
- ODPG_DATA_BUFFER_OFFS_REG,
- load_addr, MASK_ALL_BITS));
+ CHECK_STATUS(ddr3_tip_if_write
+ (dev_num, access_type, if_id,
+ ODPG_DATA_BUFFER_OFFS_REG, load_addr, MASK_ALL_BITS));
return MV_OK;
}
@@ -864,8 +862,11 @@
DUAL_DUNIT_CFG_REG, (1 << 3), (1 << 3)));
}
- for (pattern = 0; pattern < PATTERN_LAST; pattern++)
+ for (pattern = 0; pattern < PATTERN_LAST; pattern++) {
+ if (pattern == PATTERN_TEST)
+ continue;
ddr3_tip_load_pattern_to_mem(dev_num, pattern);
+ }
return MV_OK;
}
diff --git a/drivers/ddr/marvell/a38x/ddr3_training_leveling.c b/drivers/ddr/marvell/a38x/ddr3_training_leveling.c
index dadb06b..6523281 100644
--- a/drivers/ddr/marvell/a38x/ddr3_training_leveling.c
+++ b/drivers/ddr/marvell/a38x/ddr3_training_leveling.c
@@ -7,7 +7,6 @@
#include "mv_ddr_training_db.h"
#include "ddr_training_ip_db.h"
#include "mv_ddr_regs.h"
-#include <linux/delay.h>
#define WL_ITERATION_NUM 10
@@ -916,10 +915,8 @@
DEBUG_LEVELING(DEBUG_LEVEL_ERROR, ("training done failed\n"));
} else { /* check for training pass */
reg_data = data_read[0];
-#if defined(CONFIG_ARMADA_38X) /* JIRA #1498 for 16 bit with ECC */
if (tm->bus_act_mask == 0xb) /* set to data to 0 to skip the check */
reg_data = 0;
-#endif
if (reg_data != PASS)
DEBUG_LEVELING(DEBUG_LEVEL_INFO, ("training result failed\n"));
diff --git a/drivers/ddr/marvell/a38x/ddr_ml_wrapper.h b/drivers/ddr/marvell/a38x/ddr_ml_wrapper.h
index ac9250f..7357311 100644
--- a/drivers/ddr/marvell/a38x/ddr_ml_wrapper.h
+++ b/drivers/ddr/marvell/a38x/ddr_ml_wrapper.h
@@ -13,9 +13,7 @@
#include <asm/arch/cpu.h>
#include <asm/arch/soc.h>
-#if defined(CONFIG_ARMADA_38X) || defined(CONFIG_ARMADA_39X)
#define INTER_REGS_BASE SOC_REGS_PHY_BASE
-#endif
/*
* MV_DEBUG_INIT need to be defines, otherwise the output of the
diff --git a/drivers/ddr/marvell/a38x/ddr_topology_def.h b/drivers/ddr/marvell/a38x/ddr_topology_def.h
index 34196b1..7f2317e 100644
--- a/drivers/ddr/marvell/a38x/ddr_topology_def.h
+++ b/drivers/ddr/marvell/a38x/ddr_topology_def.h
@@ -14,6 +14,11 @@
#define MV_DDR_MAX_BUS_NUM 9
#define MV_DDR_MAX_IFACE_NUM 1
+enum mv_ddr_twin_die {
+ NOT_COMBINED,
+ COMBINED,
+};
+
struct bus_params {
/* Chip Select (CS) bitmask (bits 0-CS0, bit 1- CS1 ...) */
u8 cs_bitmask;
@@ -113,6 +118,9 @@
/* source of ddr configuration data */
enum mv_ddr_cfg_src cfg_src;
+ /* ddr twin-die */
+ enum mv_ddr_twin_die twin_die_combined;
+
/* raw spd data */
union mv_ddr_spd_data spd_data;
@@ -125,6 +133,9 @@
/* electrical parameters */
unsigned int electrical_data[MV_DDR_EDATA_LAST];
+ /* ODT configuration */
+ u32 odt_config;
+
/* Clock enable mask */
u32 clk_enable;
@@ -148,9 +159,15 @@
MV_DDR_VAL_DIS,
MV_DDR_VAL_RX,
MV_DDR_VAL_TX,
- MV_DDR_VAL_RX_TX
+ MV_DDR_VAL_RX_TX,
+ MV_DDR_MEMORY_CHECK
};
+enum mv_ddr_sscg {
+ SSCG_EN,
+ SSCG_DIS,
+};
+
struct mv_ddr_iface {
/* base addr of ap ddr interface belongs to */
unsigned int ap_base;
@@ -179,8 +196,12 @@
/* ddr interface validation mode */
enum mv_ddr_validation validation;
+ /* ddr interface validation mode */
+ enum mv_ddr_sscg sscg;
+
/* ddr interface topology map */
struct mv_ddr_topology_map tm;
+
};
struct mv_ddr_iface *mv_ddr_iface_get(void);
diff --git a/drivers/ddr/marvell/a38x/mv_ddr_build_message.c b/drivers/ddr/marvell/a38x/mv_ddr_build_message.c
index cc6234f..a2bb8a9 100644
--- a/drivers/ddr/marvell/a38x/mv_ddr_build_message.c
+++ b/drivers/ddr/marvell/a38x/mv_ddr_build_message.c
@@ -1,3 +1,3 @@
// SPDX-License-Identifier: GPL-2.0
const char mv_ddr_build_message[] = "";
-const char mv_ddr_version_string[] = "mv_ddr: mv_ddr-armada-18.09.2";
+const char mv_ddr_version_string[] = "mv_ddr: 14.0.0";
diff --git a/drivers/ddr/marvell/a38x/mv_ddr_plat.c b/drivers/ddr/marvell/a38x/mv_ddr_plat.c
index 72f0dfb..faafc86 100644
--- a/drivers/ddr/marvell/a38x/mv_ddr_plat.c
+++ b/drivers/ddr/marvell/a38x/mv_ddr_plat.c
@@ -4,10 +4,10 @@
*/
#include "ddr3_init.h"
+#include "mv_ddr_common.h"
#include "mv_ddr_training_db.h"
#include "mv_ddr_regs.h"
#include "mv_ddr_sys_env_lib.h"
-#include <linux/delay.h>
#define DDR_INTERFACES_NUM 1
#define DDR_INTERFACE_OCTETS_NUM 5
@@ -559,11 +559,7 @@
static int ddr3_tip_a38x_get_device_info(u8 dev_num, struct ddr3_device_info *info_ptr)
{
-#if defined(CONFIG_ARMADA_39X)
- info_ptr->device_id = 0x6900;
-#else
info_ptr->device_id = 0x6800;
-#endif
info_ptr->ck_delay = ck_delay;
return MV_OK;
@@ -666,11 +662,7 @@
ddr3_tip_dev_attr_set(dev_num, MV_ATTR_TIP_REV, MV_TIP_REV_4);
ddr3_tip_dev_attr_set(dev_num, MV_ATTR_PHY_EDGE, MV_DDR_PHY_EDGE_POSITIVE);
ddr3_tip_dev_attr_set(dev_num, MV_ATTR_OCTET_PER_INTERFACE, DDR_INTERFACE_OCTETS_NUM);
-#ifdef CONFIG_ARMADA_39X
- ddr3_tip_dev_attr_set(dev_num, MV_ATTR_INTERLEAVE_WA, 1);
-#else
ddr3_tip_dev_attr_set(dev_num, MV_ATTR_INTERLEAVE_WA, 0);
-#endif
ca_delay = 0;
delay_enable = 1;
@@ -1016,7 +1008,7 @@
return MV_BAD_VALUE;
}
- *cs_size = cs_mem_size << 20; /* write cs size in bytes */
+ *cs_size = cs_mem_size;
return MV_OK;
}
@@ -1025,9 +1017,11 @@
{
u32 reg, cs;
uint64_t mem_total_size = 0;
+ uint64_t cs_mem_size_mb = 0;
uint64_t cs_mem_size = 0;
uint64_t mem_total_size_c, cs_mem_size_c;
+
#ifdef DEVICE_MAX_DRAM_ADDRESS_SIZE
u32 physical_mem_size;
u32 max_mem_size = DEVICE_MAX_DRAM_ADDRESS_SIZE;
@@ -1038,8 +1032,9 @@
for (cs = 0; cs < MAX_CS_NUM; cs++) {
if (cs_ena & (1 << cs)) {
/* get CS size */
- if (ddr3_calc_mem_cs_size(cs, &cs_mem_size) != MV_OK)
+ if (ddr3_calc_mem_cs_size(cs, &cs_mem_size_mb) != MV_OK)
return MV_FAIL;
+ cs_mem_size = cs_mem_size_mb * _1M;
#ifdef DEVICE_MAX_DRAM_ADDRESS_SIZE
/*
@@ -1088,6 +1083,7 @@
*/
mem_total_size_c = (mem_total_size >> 16) & 0xffffffffffff;
cs_mem_size_c = (cs_mem_size >> 16) & 0xffffffffffff;
+
/* if the sum less than 2 G - calculate the value */
if (mem_total_size_c + cs_mem_size_c < 0x10000)
mem_total_size += cs_mem_size;
diff --git a/drivers/ddr/marvell/a38x/mv_ddr_plat.h b/drivers/ddr/marvell/a38x/mv_ddr_plat.h
index 281d4c2..4499884 100644
--- a/drivers/ddr/marvell/a38x/mv_ddr_plat.h
+++ b/drivers/ddr/marvell/a38x/mv_ddr_plat.h
@@ -6,6 +6,8 @@
#ifndef _MV_DDR_PLAT_H
#define _MV_DDR_PLAT_H
+#include <linux/delay.h>
+
#define MAX_DEVICE_NUM 1
#define MAX_INTERFACE_NUM 1
#define MAX_BUS_NUM 5
diff --git a/drivers/ddr/marvell/a38x/mv_ddr_spd.h b/drivers/ddr/marvell/a38x/mv_ddr_spd.h
index b4bfef3..6043f11 100644
--- a/drivers/ddr/marvell/a38x/mv_ddr_spd.h
+++ b/drivers/ddr/marvell/a38x/mv_ddr_spd.h
@@ -40,7 +40,10 @@
*/
union mv_ddr_spd_data {
unsigned char all_bytes[MV_DDR_SPD_DATA_BLOCK0_SIZE +
- MV_DDR_SPD_DATA_BLOCK1M_SIZE];
+ MV_DDR_SPD_DATA_BLOCK1M_SIZE +
+ MV_DDR_SPD_DATA_BLOCK1H_SIZE +
+ MV_DDR_SPD_DATA_BLOCK2E_SIZE +
+ MV_DDR_SPD_DATA_BLOCK2M_SIZE];
struct {
/* block 0 */
union { /* num of bytes used/num of bytes in spd device/crc coverage */
@@ -271,6 +274,9 @@
} bit_fields;
} byte_131;
unsigned char bytes_132_191[60]; /* reserved; all 0s */
+ unsigned char bytes_192_255[MV_DDR_SPD_DATA_BLOCK1H_SIZE];
+ unsigned char bytes_256_319[MV_DDR_SPD_DATA_BLOCK2E_SIZE];
+ unsigned char bytes_320_383[MV_DDR_SPD_DATA_BLOCK2M_SIZE];
} byte_fields;
};
diff --git a/drivers/ddr/marvell/a38x/mv_ddr_sys_env_lib.h b/drivers/ddr/marvell/a38x/mv_ddr_sys_env_lib.h
index dc6977c..10b0d45 100644
--- a/drivers/ddr/marvell/a38x/mv_ddr_sys_env_lib.h
+++ b/drivers/ddr/marvell/a38x/mv_ddr_sys_env_lib.h
@@ -78,22 +78,7 @@
* set '-2'
* If suspend to RAM is not supported set '-1'
*/
-#ifdef CONFIG_CUSTOMER_BOARD_SUPPORT
-#ifdef CONFIG_ARMADA_38X
-#define MV_BOARD_WAKEUP_GPIO_INFO { \
- {A38X_CUSTOMER_BOARD_ID0, -1 }, \
- {A38X_CUSTOMER_BOARD_ID0, -1 }, \
-};
-#else
-#define MV_BOARD_WAKEUP_GPIO_INFO { \
- {A39X_CUSTOMER_BOARD_ID0, -1 }, \
- {A39X_CUSTOMER_BOARD_ID0, -1 }, \
-};
-#endif /* CONFIG_ARMADA_38X */
-
-#else
-#ifdef CONFIG_ARMADA_38X
#define MV_BOARD_WAKEUP_GPIO_INFO { \
{RD_NAS_68XX_ID, -2 }, \
{DB_68XX_ID, -1 }, \
@@ -103,13 +88,6 @@
{DB_BP_6821_ID, -2 }, \
{DB_AMC_6820_ID, -2 }, \
};
-#else
-#define MV_BOARD_WAKEUP_GPIO_INFO { \
- {A39X_RD_69XX_ID, -1 }, \
- {A39X_DB_69XX_ID, -1 }, \
-};
-#endif /* CONFIG_ARMADA_38X */
-#endif /* CONFIG_CUSTOMER_BOARD_SUPPORT */
enum suspend_wakeup_status mv_ddr_sys_env_suspend_wakeup_check(void);
u32 mv_ddr_sys_env_get_cs_ena_from_reg(void);
diff --git a/drivers/ddr/marvell/a38x/mv_ddr_topology.c b/drivers/ddr/marvell/a38x/mv_ddr_topology.c
index 09840b1..2db6283 100644
--- a/drivers/ddr/marvell/a38x/mv_ddr_topology.c
+++ b/drivers/ddr/marvell/a38x/mv_ddr_topology.c
@@ -127,6 +127,11 @@
speed_bin_index = iface_params->speed_bin_index;
freq = iface_params->memory_freq;
+ if (tm->twin_die_combined == COMBINED) {
+ iface_params->bus_width = MV_DDR_DEV_WIDTH_8BIT;
+ iface_params->memory_size -= 1;
+ }
+
if (iface_params->cas_l == 0)
iface_params->cas_l = mv_ddr_cl_val_get(speed_bin_index, freq);
@@ -144,6 +149,9 @@
unsigned int octets_per_if_num = ddr3_tip_dev_attr_get(0, MV_ATTR_OCTET_PER_INTERFACE);
if (tm->cfg_src == MV_DDR_CFG_SPD) {
+ if (tm->bus_act_mask == MV_DDR_32BIT_ECC_PUP8_BUS_MASK)
+ tm->spd_data.byte_fields.byte_13.bit_fields.primary_bus_width = MV_DDR_PRI_BUS_WIDTH_32;
+
enum mv_ddr_pri_bus_width pri_bus_width = mv_ddr_spd_pri_bus_width_get(&tm->spd_data);
enum mv_ddr_bus_width_ext bus_width_ext = mv_ddr_spd_bus_width_ext_get(&tm->spd_data);
@@ -151,7 +159,7 @@
case MV_DDR_PRI_BUS_WIDTH_16:
pri_and_ext_bus_width = BUS_MASK_16BIT;
break;
- case MV_DDR_PRI_BUS_WIDTH_32:
+ case MV_DDR_PRI_BUS_WIDTH_32: /*each bit represents byte, so 0xf-is means 4 bytes-32 bit*/
pri_and_ext_bus_width = BUS_MASK_32BIT;
break;
case MV_DDR_PRI_BUS_WIDTH_64:
@@ -245,7 +253,8 @@
ADDR_SIZE_1GB,
ADDR_SIZE_2GB,
ADDR_SIZE_4GB,
- ADDR_SIZE_8GB
+ ADDR_SIZE_8GB,
+ ADDR_SIZE_16GB
/* TODO: add capacity up to 256GB */
};
@@ -277,7 +286,6 @@
mem_sz_per_cs = (unsigned long long)mem_size[iface_params->memory_size] *
(unsigned long long)sphys /
(unsigned long long)sphys_per_dunit;
-
return mem_sz_per_cs;
}
diff --git a/drivers/ddr/marvell/a38x/mv_ddr_topology.h b/drivers/ddr/marvell/a38x/mv_ddr_topology.h
index 4fca476..1cb69ad 100644
--- a/drivers/ddr/marvell/a38x/mv_ddr_topology.h
+++ b/drivers/ddr/marvell/a38x/mv_ddr_topology.h
@@ -179,7 +179,9 @@
/* phy electrical configuration values */
enum mv_ddr_ohm_evalue {
+ MV_DDR_OHM_20 = 20,/*relevant for Synopsys C/A Drive strength only*/
MV_DDR_OHM_30 = 30,
+ MV_DDR_OHM_40 = 40,/*relevant for Synopsys C/A Drive strength only*/
MV_DDR_OHM_48 = 48,
MV_DDR_OHM_60 = 60,
MV_DDR_OHM_80 = 80,
diff --git a/drivers/ddr/marvell/a38x/xor.c b/drivers/ddr/marvell/a38x/xor.c
index 5fb9e21..7bc6268 100644
--- a/drivers/ddr/marvell/a38x/xor.c
+++ b/drivers/ddr/marvell/a38x/xor.c
@@ -340,18 +340,16 @@
{
u32 cs_c, max_cs;
u32 cs_ena = 0;
- uint64_t total_mem_size, cs_mem_size = 0;
+ uint64_t total_mem_size, cs_mem_size_mb = 0, cs_mem_size = 0;
printf("DDR Training Sequence - Start scrubbing\n");
max_cs = mv_ddr_cs_num_get();
for (cs_c = 0; cs_c < max_cs; cs_c++)
cs_ena |= 1 << cs_c;
-#if defined(CONFIG_ARMADA_38X) || defined(CONFIG_ARMADA_39X)
/* all chip-selects are of same size */
- ddr3_calc_mem_cs_size(0, &cs_mem_size);
-#endif
-
+ ddr3_calc_mem_cs_size(0, &cs_mem_size_mb);
+ cs_mem_size = cs_mem_size_mb * _1M;
mv_sys_xor_init(max_cs, cs_ena, cs_mem_size, 0);
total_mem_size = max_cs * cs_mem_size;
mv_xor_mem_init(0, 0, total_mem_size, 0xdeadbeef, 0xdeadbeef);
diff --git a/drivers/ddr/marvell/axp/ddr3_dfs.c b/drivers/ddr/marvell/axp/ddr3_dfs.c
index b58c0fe..2a45966 100644
--- a/drivers/ddr/marvell/axp/ddr3_dfs.c
+++ b/drivers/ddr/marvell/axp/ddr3_dfs.c
@@ -42,8 +42,8 @@
extern void get_target_freq(u32 freq_mode, u32 *ddr_freq, u32 *hclk_ps);
#else
extern u16 odt_dynamic[ODT_OPT][MAX_CS];
-extern u8 div_ratio1to1[CLK_CPU][CLK_DDR];
-extern u8 div_ratio2to1[CLK_CPU][CLK_DDR];
+extern u8 div_ratio1to1[CLK_VCO][CLK_DDR];
+extern u8 div_ratio2to1[CLK_VCO][CLK_DDR];
#endif
extern u16 odt_static[ODT_OPT][MAX_CS];
diff --git a/drivers/ddr/marvell/axp/ddr3_sdram.c b/drivers/ddr/marvell/axp/ddr3_sdram.c
index 3a266c6..0b150b2 100644
--- a/drivers/ddr/marvell/axp/ddr3_sdram.c
+++ b/drivers/ddr/marvell/axp/ddr3_sdram.c
@@ -21,7 +21,7 @@
#if defined(MV88F78X60)
extern u32 pbs_pattern_64b[2][LEN_PBS_PATTERN];
#endif
-extern u32 pbs_dq_mapping[PUP_NUM_64BIT][DQ_NUM];
+extern u32 pbs_dq_mapping[PUP_NUM_64BIT + 1][DQ_NUM];
#if defined(MV88F78X60) || defined(MV88F672X)
/* PBS locked dq (per pup) */
diff --git a/drivers/ddr/marvell/axp/xor.c b/drivers/ddr/marvell/axp/xor.c
index 17bfe6a..76aea96 100644
--- a/drivers/ddr/marvell/axp/xor.c
+++ b/drivers/ddr/marvell/axp/xor.c
@@ -152,8 +152,8 @@
return MV_OK;
}
-int mv_xor_mem_init(u32 chan, u32 start_ptr, u32 block_size, u32 init_val_high,
- u32 init_val_low)
+int mv_xor_mem_init(u32 chan, u32 start_ptr, unsigned long long block_size,
+ u32 init_val_high, u32 init_val_low)
{
u32 tmp;
diff --git a/drivers/ddr/marvell/axp/xor.h b/drivers/ddr/marvell/axp/xor.h
index 97d1056..a7c6ae8 100644
--- a/drivers/ddr/marvell/axp/xor.h
+++ b/drivers/ddr/marvell/axp/xor.h
@@ -64,7 +64,7 @@
void mv_sys_xor_init(MV_DRAM_INFO *dram_info);
void mv_sys_xor_finish(void);
int mv_xor_transfer(u32 chan, int xor_type, u32 xor_chain_ptr);
-int mv_xor_mem_init(u32 chan, u32 start_ptr, u32 block_size, u32 init_val_high,
- u32 init_val_low);
+int mv_xor_mem_init(u32 chan, u32 start_ptr, unsigned long long block_size,
+ u32 init_val_high, u32 init_val_low);
#endif /* __XOR_H */
diff --git a/drivers/fastboot/Kconfig b/drivers/fastboot/Kconfig
index a17e488..2d1836a 100644
--- a/drivers/fastboot/Kconfig
+++ b/drivers/fastboot/Kconfig
@@ -72,6 +72,15 @@
the downloaded image to a non-volatile storage device. Define
this to enable the "fastboot flash" command.
+config FASTBOOT_UUU_SUPPORT
+ bool "Enable FASTBOOT i.MX UUU special command"
+ default n
+ help
+ The fastboot protocol includes "UCmd" and "ACmd" command.
+ Be aware that you provide full access to any U-Boot command,
+ including working with memory and may open a huge backdoor,
+ when enabling this option.
+
choice
prompt "Flash provider for FASTBOOT"
depends on FASTBOOT_FLASH
diff --git a/drivers/fastboot/fb_command.c b/drivers/fastboot/fb_command.c
index 41fc8d7..3a5db5b 100644
--- a/drivers/fastboot/fb_command.c
+++ b/drivers/fastboot/fb_command.c
@@ -49,6 +49,11 @@
static void oem_bootbus(char *, char *);
#endif
+#if CONFIG_IS_ENABLED(FASTBOOT_UUU_SUPPORT)
+static void run_ucmd(char *, char *);
+static void run_acmd(char *, char *);
+#endif
+
static const struct {
const char *command;
void (*dispatch)(char *cmd_parameter, char *response);
@@ -117,6 +122,16 @@
.dispatch = oem_bootbus,
},
#endif
+#if CONFIG_IS_ENABLED(FASTBOOT_UUU_SUPPORT)
+ [FASTBOOT_COMMAND_UCMD] = {
+ .command = "UCmd",
+ .dispatch = run_ucmd,
+ },
+ [FASTBOOT_COMMAND_ACMD] = {
+ .command = "ACmd",
+ .dispatch = run_acmd,
+ },
+#endif
};
/**
@@ -327,6 +342,59 @@
}
#endif
+#if CONFIG_IS_ENABLED(FASTBOOT_UUU_SUPPORT)
+/**
+ * run_ucmd() - Execute the UCmd command
+ *
+ * @cmd_parameter: Pointer to command parameter
+ * @response: Pointer to fastboot response buffer
+ */
+static void run_ucmd(char *cmd_parameter, char *response)
+{
+ if (!cmd_parameter) {
+ pr_err("missing slot suffix\n");
+ fastboot_fail("missing command", response);
+ return;
+ }
+
+ if (run_command(cmd_parameter, 0))
+ fastboot_fail("", response);
+ else
+ fastboot_okay(NULL, response);
+}
+
+static char g_a_cmd_buff[64];
+
+void fastboot_acmd_complete(void)
+{
+ run_command(g_a_cmd_buff, 0);
+}
+
+/**
+ * run_acmd() - Execute the ACmd command
+ *
+ * @cmd_parameter: Pointer to command parameter
+ * @response: Pointer to fastboot response buffer
+ */
+static void run_acmd(char *cmd_parameter, char *response)
+{
+ if (!cmd_parameter) {
+ pr_err("missing slot suffix\n");
+ fastboot_fail("missing command", response);
+ return;
+ }
+
+ if (strlen(cmd_parameter) > sizeof(g_a_cmd_buff)) {
+ pr_err("too long command\n");
+ fastboot_fail("too long command", response);
+ return;
+ }
+
+ strcpy(g_a_cmd_buff, cmd_parameter);
+ fastboot_okay(NULL, response);
+}
+#endif
+
/**
* reboot_bootloader() - Sets reboot bootloader flag.
*
diff --git a/drivers/fastboot/fb_mmc.c b/drivers/fastboot/fb_mmc.c
index 50532ac..8e74e50 100644
--- a/drivers/fastboot/fb_mmc.c
+++ b/drivers/fastboot/fb_mmc.c
@@ -28,30 +28,9 @@
struct blk_desc *dev_desc;
};
-static int part_get_info_by_name_or_alias(struct blk_desc *dev_desc,
- const char *name, struct disk_partition *info)
-{
- int ret;
-
- ret = part_get_info_by_name(dev_desc, name, info);
- if (ret < 0) {
- /* strlen("fastboot_partition_alias_") + PART_NAME_LEN + 1 */
- char env_alias_name[25 + PART_NAME_LEN + 1];
- char *aliased_part_name;
-
- /* check for alias */
- strcpy(env_alias_name, "fastboot_partition_alias_");
- strncat(env_alias_name, name, PART_NAME_LEN);
- aliased_part_name = env_get(env_alias_name);
- if (aliased_part_name != NULL)
- ret = part_get_info_by_name(dev_desc,
- aliased_part_name, info);
- }
- return ret;
-}
-
static int raw_part_get_info_by_name(struct blk_desc *dev_desc,
- const char *name, struct disk_partition *info, int *mmcpart)
+ const char *name,
+ struct disk_partition *info)
{
/* strlen("fastboot_raw_partition_") + PART_NAME_LEN + 1 */
char env_desc_name[23 + PART_NAME_LEN + 1];
@@ -85,13 +64,65 @@
strncpy((char *)info->name, name, PART_NAME_LEN);
if (raw_part_desc) {
- if (strcmp(strsep(&raw_part_desc, " "), "mmcpart") == 0)
- *mmcpart = simple_strtoul(raw_part_desc, NULL, 0);
+ if (strcmp(strsep(&raw_part_desc, " "), "mmcpart") == 0) {
+ ulong mmcpart = simple_strtoul(raw_part_desc, NULL, 0);
+ int ret = blk_dselect_hwpart(dev_desc, mmcpart);
+
+ if (ret)
+ return ret;
+ }
}
return 0;
}
+static int do_get_part_info(struct blk_desc **dev_desc, const char *name,
+ struct disk_partition *info)
+{
+ int ret;
+
+ /* First try partition names on the default device */
+ *dev_desc = blk_get_dev("mmc", CONFIG_FASTBOOT_FLASH_MMC_DEV);
+ if (*dev_desc) {
+ ret = part_get_info_by_name(*dev_desc, name, info);
+ if (ret >= 0)
+ return ret;
+
+ /* Then try raw partitions */
+ ret = raw_part_get_info_by_name(*dev_desc, name, info);
+ if (ret >= 0)
+ return ret;
+ }
+
+ /* Then try dev.hwpart:part */
+ ret = part_get_info_by_dev_and_name_or_num("mmc", name, dev_desc,
+ info, true);
+ return ret;
+}
+
+static int part_get_info_by_name_or_alias(struct blk_desc **dev_desc,
+ const char *name,
+ struct disk_partition *info)
+{
+ int ret;
+
+ ret = do_get_part_info(dev_desc, name, info);
+ if (ret < 0) {
+ /* strlen("fastboot_partition_alias_") + PART_NAME_LEN + 1 */
+ char env_alias_name[25 + PART_NAME_LEN + 1];
+ char *aliased_part_name;
+
+ /* check for alias */
+ strcpy(env_alias_name, "fastboot_partition_alias_");
+ strncat(env_alias_name, name, PART_NAME_LEN);
+ aliased_part_name = env_get(env_alias_name);
+ if (aliased_part_name != NULL)
+ ret = do_get_part_info(dev_desc, aliased_part_name,
+ info);
+ }
+ return ret;
+}
+
/**
* fb_mmc_blk_write() - Write/erase MMC in chunks of FASTBOOT_MAX_BLK_WRITE
*
@@ -424,28 +455,49 @@
struct blk_desc **dev_desc,
struct disk_partition *part_info, char *response)
{
- int r = 0;
- int mmcpart;
+ int ret;
- *dev_desc = blk_get_dev("mmc", CONFIG_FASTBOOT_FLASH_MMC_DEV);
- if (!*dev_desc) {
- fastboot_fail("block device not found", response);
- return -ENOENT;
- }
if (!part_name || !strcmp(part_name, "")) {
fastboot_fail("partition not given", response);
return -ENOENT;
}
- if (raw_part_get_info_by_name(*dev_desc, part_name, part_info, &mmcpart) < 0) {
- r = part_get_info_by_name_or_alias(*dev_desc, part_name, part_info);
- if (r < 0) {
- fastboot_fail("partition not found", response);
- return r;
+ ret = part_get_info_by_name_or_alias(dev_desc, part_name, part_info);
+ if (ret < 0) {
+ switch (ret) {
+ case -ENOSYS:
+ case -EINVAL:
+ fastboot_fail("invalid partition or device", response);
+ break;
+ case -ENODEV:
+ fastboot_fail("no such device", response);
+ break;
+ case -ENOENT:
+ fastboot_fail("no such partition", response);
+ break;
+ case -EPROTONOSUPPORT:
+ fastboot_fail("unknown partition table type", response);
+ break;
+ default:
+ fastboot_fail("unanticipated error", response);
+ break;
}
}
+ return ret;
+}
+
+static struct blk_desc *fastboot_mmc_get_dev(char *response)
+{
+ struct blk_desc *ret = blk_get_dev("mmc",
+ CONFIG_FASTBOOT_FLASH_MMC_DEV);
+
- return r;
+ if (!ret || ret->type == DEV_TYPE_UNKNOWN) {
+ pr_err("invalid mmc device\n");
+ fastboot_fail("invalid mmc device", response);
+ return NULL;
+ }
+ return ret;
}
/**
@@ -461,24 +513,20 @@
{
struct blk_desc *dev_desc;
struct disk_partition info;
- int mmcpart = 0;
-
- dev_desc = blk_get_dev("mmc", CONFIG_FASTBOOT_FLASH_MMC_DEV);
- if (!dev_desc || dev_desc->type == DEV_TYPE_UNKNOWN) {
- pr_err("invalid mmc device\n");
- fastboot_fail("invalid mmc device", response);
- return;
- }
#ifdef CONFIG_FASTBOOT_MMC_BOOT_SUPPORT
if (strcmp(cmd, CONFIG_FASTBOOT_MMC_BOOT1_NAME) == 0) {
- fb_mmc_boot_ops(dev_desc, download_buffer, 1,
- download_bytes, response);
+ dev_desc = fastboot_mmc_get_dev(response);
+ if (dev_desc)
+ fb_mmc_boot_ops(dev_desc, download_buffer, 1,
+ download_bytes, response);
return;
}
if (strcmp(cmd, CONFIG_FASTBOOT_MMC_BOOT2_NAME) == 0) {
- fb_mmc_boot_ops(dev_desc, download_buffer, 2,
- download_bytes, response);
+ dev_desc = fastboot_mmc_get_dev(response);
+ if (dev_desc)
+ fb_mmc_boot_ops(dev_desc, download_buffer, 1,
+ download_bytes, response);
return;
}
#endif
@@ -490,6 +538,10 @@
if (strcmp(cmd, CONFIG_FASTBOOT_GPT_NAME) == 0 ||
strcmp(cmd, CONFIG_FASTBOOT_MMC_USER_NAME) == 0) {
#endif
+ dev_desc = fastboot_mmc_get_dev(response);
+ if (!dev_desc)
+ return;
+
printf("%s: updating MBR, Primary and Backup GPT(s)\n",
__func__);
if (is_valid_gpt_buf(dev_desc, download_buffer)) {
@@ -513,6 +565,10 @@
#if CONFIG_IS_ENABLED(DOS_PARTITION)
if (strcmp(cmd, CONFIG_FASTBOOT_MBR_NAME) == 0) {
+ dev_desc = fastboot_mmc_get_dev(response);
+ if (!dev_desc)
+ return;
+
printf("%s: updating MBR\n", __func__);
if (is_valid_dos_buf(download_buffer)) {
printf("%s: invalid MBR - refusing to write to flash\n",
@@ -535,23 +591,16 @@
#ifdef CONFIG_ANDROID_BOOT_IMAGE
if (strncasecmp(cmd, "zimage", 6) == 0) {
- fb_mmc_update_zimage(dev_desc, download_buffer,
- download_bytes, response);
+ dev_desc = fastboot_mmc_get_dev(response);
+ if (dev_desc)
+ fb_mmc_update_zimage(dev_desc, download_buffer,
+ download_bytes, response);
return;
}
#endif
- if (raw_part_get_info_by_name(dev_desc, cmd, &info, &mmcpart) == 0) {
- if (blk_dselect_hwpart(dev_desc, mmcpart)) {
- pr_err("Failed to select hwpart\n");
- fastboot_fail("Failed to select hwpart", response);
- return;
- }
- } else if (part_get_info_by_name_or_alias(dev_desc, cmd, &info) < 0) {
- pr_err("cannot find partition: '%s'\n", cmd);
- fastboot_fail("cannot find partition", response);
+ if (fastboot_mmc_get_part_info(cmd, &dev_desc, &info, response) < 0)
return;
- }
if (is_sparse_image(download_buffer)) {
struct fb_mmc_sparse sparse_priv;
@@ -593,30 +642,20 @@
struct disk_partition info;
lbaint_t blks, blks_start, blks_size, grp_size;
struct mmc *mmc = find_mmc_device(CONFIG_FASTBOOT_FLASH_MMC_DEV);
- int mmcpart = 0;
-
- if (mmc == NULL) {
- pr_err("invalid mmc device\n");
- fastboot_fail("invalid mmc device", response);
- return;
- }
-
- dev_desc = blk_get_dev("mmc", CONFIG_FASTBOOT_FLASH_MMC_DEV);
- if (!dev_desc || dev_desc->type == DEV_TYPE_UNKNOWN) {
- pr_err("invalid mmc device\n");
- fastboot_fail("invalid mmc device", response);
- return;
- }
#ifdef CONFIG_FASTBOOT_MMC_BOOT_SUPPORT
if (strcmp(cmd, CONFIG_FASTBOOT_MMC_BOOT1_NAME) == 0) {
/* erase EMMC boot1 */
- fb_mmc_boot_ops(dev_desc, NULL, 1, 0, response);
+ dev_desc = fastboot_mmc_get_dev(response);
+ if (dev_desc)
+ fb_mmc_boot_ops(dev_desc, NULL, 1, 0, response);
return;
}
if (strcmp(cmd, CONFIG_FASTBOOT_MMC_BOOT2_NAME) == 0) {
/* erase EMMC boot2 */
- fb_mmc_boot_ops(dev_desc, NULL, 2, 0, response);
+ dev_desc = fastboot_mmc_get_dev(response);
+ if (dev_desc)
+ fb_mmc_boot_ops(dev_desc, NULL, 1, 0, response);
return;
}
#endif
@@ -624,6 +663,10 @@
#ifdef CONFIG_FASTBOOT_MMC_USER_SUPPORT
if (strcmp(cmd, CONFIG_FASTBOOT_MMC_USER_NAME) == 0) {
/* erase EMMC userdata */
+ dev_desc = fastboot_mmc_get_dev(response);
+ if (!dev_desc)
+ return;
+
if (fb_mmc_erase_mmc_hwpart(dev_desc))
fastboot_fail("Failed to erase EMMC_USER", response);
else
@@ -632,17 +675,8 @@
}
#endif
- if (raw_part_get_info_by_name(dev_desc, cmd, &info, &mmcpart) == 0) {
- if (blk_dselect_hwpart(dev_desc, mmcpart)) {
- pr_err("Failed to select hwpart\n");
- fastboot_fail("Failed to select hwpart", response);
- return;
- }
- } else if (part_get_info_by_name_or_alias(dev_desc, cmd, &info) < 0) {
- pr_err("cannot find partition: '%s'\n", cmd);
- fastboot_fail("cannot find partition", response);
+ if (fastboot_mmc_get_part_info(cmd, &dev_desc, &info, response) < 0)
return;
- }
/* Align blocks to erase group size to avoid erasing other partitions */
grp_size = mmc->erase_grp_size;
diff --git a/drivers/firmware/scmi/mailbox_agent.c b/drivers/firmware/scmi/mailbox_agent.c
index 3f4b04a..ea35e7e 100644
--- a/drivers/firmware/scmi/mailbox_agent.c
+++ b/drivers/firmware/scmi/mailbox_agent.c
@@ -3,13 +3,15 @@
* Copyright (C) 2020 Linaro Limited.
*/
+#define LOG_CATEGORY UCLASS_SCMI_AGENT
+
#include <common.h>
#include <dm.h>
-#include <dm/device_compat.h>
#include <errno.h>
#include <mailbox.h>
#include <scmi_agent.h>
#include <scmi_agent-uclass.h>
+#include <dm/device_compat.h>
#include <dm/devres.h>
#include <linux/compat.h>
diff --git a/drivers/firmware/scmi/sandbox-scmi_agent.c b/drivers/firmware/scmi/sandbox-scmi_agent.c
index 35de68c..97a5dac 100644
--- a/drivers/firmware/scmi/sandbox-scmi_agent.c
+++ b/drivers/firmware/scmi/sandbox-scmi_agent.c
@@ -3,6 +3,8 @@
* Copyright (C) 2020, Linaro Limited
*/
+#define LOG_CATEGORY UCLASS_SCMI_AGENT
+
#include <common.h>
#include <dm.h>
#include <malloc.h>
diff --git a/drivers/firmware/scmi/sandbox-scmi_devices.c b/drivers/firmware/scmi/sandbox-scmi_devices.c
index 1a6fafb..69239a1 100644
--- a/drivers/firmware/scmi/sandbox-scmi_devices.c
+++ b/drivers/firmware/scmi/sandbox-scmi_devices.c
@@ -3,6 +3,8 @@
* Copyright (C) 2020, Linaro Limited
*/
+#define LOG_CATEGORY UCLASS_MISC
+
#include <common.h>
#include <clk.h>
#include <dm.h>
diff --git a/drivers/firmware/scmi/scmi_agent-uclass.c b/drivers/firmware/scmi/scmi_agent-uclass.c
index 516e690..527163b 100644
--- a/drivers/firmware/scmi/scmi_agent-uclass.c
+++ b/drivers/firmware/scmi/scmi_agent-uclass.c
@@ -3,13 +3,14 @@
* Copyright (C) 2020 Linaro Limited.
*/
+#define LOG_CATEGORY UCLASS_SCMI_AGENT
+
#include <common.h>
#include <dm.h>
-#include <dm/device_compat.h>
#include <errno.h>
#include <scmi_agent-uclass.h>
#include <scmi_protocols.h>
-
+#include <dm/device_compat.h>
#include <dm/device-internal.h>
#include <linux/compat.h>
diff --git a/drivers/firmware/scmi/smccc_agent.c b/drivers/firmware/scmi/smccc_agent.c
index 64d0929..f185891 100644
--- a/drivers/firmware/scmi/smccc_agent.c
+++ b/drivers/firmware/scmi/smccc_agent.c
@@ -3,12 +3,15 @@
* Copyright (C) 2020 Linaro Limited.
*/
+#define LOG_CATEGORY UCLASS_SCMI_AGENT
+
#include <common.h>
#include <dm.h>
#include <errno.h>
#include <scmi_agent.h>
#include <scmi_agent-uclass.h>
#include <dm/devres.h>
+#include <dm/device_compat.h>
#include <dm/device-internal.h>
#include <linux/arm-smccc.h>
#include <linux/compat.h>
diff --git a/drivers/firmware/scmi/smt.c b/drivers/firmware/scmi/smt.c
index d254787..60b9d49 100644
--- a/drivers/firmware/scmi/smt.c
+++ b/drivers/firmware/scmi/smt.c
@@ -4,6 +4,8 @@
* Copyright (C) 2019-2020 Linaro Limited.
*/
+#define LOG_CATEGORY UCLASS_SCMI_AGENT
+
#include <common.h>
#include <cpu_func.h>
#include <dm.h>
diff --git a/drivers/fpga/Kconfig b/drivers/fpga/Kconfig
index 425b52a..dc0b3dd 100644
--- a/drivers/fpga/Kconfig
+++ b/drivers/fpga/Kconfig
@@ -33,7 +33,7 @@
config FPGA_INTEL_SDM_MAILBOX
bool "Enable Intel FPGA Full Reconfiguration SDM Mailbox driver"
- depends on TARGET_SOCFPGA_STRATIX10 || TARGET_SOCFPGA_AGILEX
+ depends on TARGET_SOCFPGA_SOC64
select FPGA_ALTERA
help
Say Y here to enable the Intel FPGA Full Reconfig SDM Mailbox driver
diff --git a/drivers/fpga/zynqpl.c b/drivers/fpga/zynqpl.c
index a11e485..2de4010 100644
--- a/drivers/fpga/zynqpl.c
+++ b/drivers/fpga/zynqpl.c
@@ -315,7 +315,7 @@
if (new_buf > buf) {
debug("%s: Aligned buffer is after buffer start\n",
__func__);
- new_buf -= ARCH_DMA_MINALIGN;
+ new_buf = (u32 *)((u32)new_buf - ARCH_DMA_MINALIGN);
}
printf("%s: Align buffer at %x to %x(swap %d)\n", __func__,
(u32)buf, (u32)new_buf, swap);
diff --git a/drivers/gpio/mpc8xxx_gpio.c b/drivers/gpio/mpc8xxx_gpio.c
index c733603..f7ffd89 100644
--- a/drivers/gpio/mpc8xxx_gpio.c
+++ b/drivers/gpio/mpc8xxx_gpio.c
@@ -20,7 +20,7 @@
/* The bank's register base in memory */
struct ccsr_gpio __iomem *base;
/* The address of the registers; used to identify the bank */
- ulong addr;
+ phys_addr_t addr;
/* The GPIO count of the bank */
uint gpio_count;
/* The GPDAT register cannot be used to determine the value of output
@@ -181,7 +181,7 @@
if (dev_read_bool(dev, "little-endian"))
data->little_endian = true;
- plat->addr = (ulong)dev_read_addr_size_index(dev, 0, (fdt_size_t *)&plat->size);
+ plat->addr = dev_read_addr_size_index(dev, 0, (fdt_size_t *)&plat->size);
plat->ngpios = dev_read_u32_default(dev, "ngpios", 32);
return 0;
@@ -220,7 +220,8 @@
mpc8xxx_gpio_plat_to_priv(dev);
- snprintf(name, sizeof(name), "MPC@%lx_", data->addr);
+ snprintf(name, sizeof(name), "MPC@%.8llx",
+ (unsigned long long)data->addr);
str = strdup(name);
if (!str)
diff --git a/drivers/i2c/i2c-cdns.c b/drivers/i2c/i2c-cdns.c
index db3c04f..a650dd6 100644
--- a/drivers/i2c/i2c-cdns.c
+++ b/drivers/i2c/i2c-cdns.c
@@ -15,6 +15,7 @@
#include <linux/types.h>
#include <linux/io.h>
#include <linux/errno.h>
+#include <dm/device_compat.h>
#include <dm/root.h>
#include <i2c.h>
#include <fdtdec.h>
@@ -481,6 +482,12 @@
i2c_bus->input_freq = clk_get_rate(&clk);
+ ret = clk_enable(&clk);
+ if (ret) {
+ dev_err(dev, "failed to enable clock\n");
+ return ret;
+ }
+
return 0;
}
diff --git a/drivers/mmc/fsl_esdhc_imx.c b/drivers/mmc/fsl_esdhc_imx.c
index e0e1326..6a9403d 100644
--- a/drivers/mmc/fsl_esdhc_imx.c
+++ b/drivers/mmc/fsl_esdhc_imx.c
@@ -43,6 +43,12 @@
#include "mmc_private.h"
#endif
+#ifndef ESDHCI_QUIRK_BROKEN_TIMEOUT_VALUE
+#ifdef CONFIG_FSL_USDHC
+#define ESDHCI_QUIRK_BROKEN_TIMEOUT_VALUE 1
+#endif
+#endif
+
DECLARE_GLOBAL_DATA_PTR;
#define SDHCI_IRQ_EN_BITS (IRQSTATEN_CC | IRQSTATEN_TC | \
@@ -1706,6 +1712,7 @@
};
static const struct udevice_id fsl_esdhc_ids[] = {
+ { .compatible = "fsl,imx51-esdhc", },
{ .compatible = "fsl,imx53-esdhc", },
{ .compatible = "fsl,imx6ul-usdhc", },
{ .compatible = "fsl,imx6sx-usdhc", },
diff --git a/drivers/mmc/iproc_sdhci.c b/drivers/mmc/iproc_sdhci.c
index 6e4f527..11d86ad 100644
--- a/drivers/mmc/iproc_sdhci.c
+++ b/drivers/mmc/iproc_sdhci.c
@@ -10,8 +10,11 @@
#include <malloc.h>
#include <sdhci.h>
#include <asm/global_data.h>
+#include "mmc_private.h"
#include <linux/delay.h>
+#define MAX_TUNING_LOOP 40
+
DECLARE_GLOBAL_DATA_PTR;
struct sdhci_iproc_host {
@@ -140,17 +143,89 @@
static int sdhci_iproc_set_ios_post(struct sdhci_host *host)
{
- u32 ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2);
+ struct mmc *mmc = (struct mmc *)host->mmc;
+ u32 ctrl;
- /* Reset UHS mode bits */
- ctrl &= ~SDHCI_CTRL_UHS_MASK;
+ if (mmc->signal_voltage == MMC_SIGNAL_VOLTAGE_180) {
+ ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2);
+ ctrl |= SDHCI_CTRL_VDD_180;
+ sdhci_writew(host, ctrl, SDHCI_HOST_CONTROL2);
+ }
- if (host->mmc->ddr_mode)
- ctrl |= UHS_DDR50_BUS_SPEED;
+ sdhci_set_uhs_timing(host);
+ return 0;
+}
+static void sdhci_start_tuning(struct sdhci_host *host)
+{
+ u32 ctrl;
+
+ ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2);
+ ctrl |= SDHCI_CTRL_EXEC_TUNING;
sdhci_writew(host, ctrl, SDHCI_HOST_CONTROL2);
- return 0;
+ sdhci_writel(host, SDHCI_INT_DATA_AVAIL, SDHCI_INT_ENABLE);
+ sdhci_writel(host, SDHCI_INT_DATA_AVAIL, SDHCI_SIGNAL_ENABLE);
+}
+
+static void sdhci_end_tuning(struct sdhci_host *host)
+{
+ /* Enable only interrupts served by the SD controller */
+ sdhci_writel(host, SDHCI_INT_DATA_MASK | SDHCI_INT_CMD_MASK,
+ SDHCI_INT_ENABLE);
+ /* Mask all sdhci interrupt sources */
+ sdhci_writel(host, 0x0, SDHCI_SIGNAL_ENABLE);
+}
+
+static int sdhci_iproc_execute_tuning(struct mmc *mmc, u8 opcode)
+{
+ struct mmc_cmd cmd;
+ u32 ctrl;
+ u32 blocksize = SDHCI_MAKE_BLKSZ(SDHCI_DEFAULT_BOUNDARY_ARG, 64);
+ struct sdhci_host *host = dev_get_priv(mmc->dev);
+ char tuning_loop_counter = MAX_TUNING_LOOP;
+ int ret = 0;
+
+ sdhci_start_tuning(host);
+
+ cmd.cmdidx = opcode;
+ cmd.resp_type = MMC_RSP_R1;
+ cmd.cmdarg = 0;
+
+ if (opcode == MMC_CMD_SEND_TUNING_BLOCK_HS200 && mmc->bus_width == 8)
+ blocksize = SDHCI_MAKE_BLKSZ(SDHCI_DEFAULT_BOUNDARY_ARG, 128);
+
+ sdhci_writew(host, blocksize, SDHCI_BLOCK_SIZE);
+ sdhci_writew(host, 1, SDHCI_BLOCK_COUNT);
+ sdhci_writew(host, SDHCI_TRNS_READ, SDHCI_TRANSFER_MODE);
+
+ do {
+ mmc_send_cmd(mmc, &cmd, NULL);
+ if (opcode == MMC_CMD_SEND_TUNING_BLOCK)
+ /*
+ * For tuning command, do not do busy loop. As tuning
+ * is happening (CLK-DATA latching for setup/hold time
+ * requirements), give time to complete
+ */
+ udelay(1);
+
+ ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2);
+
+ if (tuning_loop_counter-- == 0)
+ break;
+
+ } while (ctrl & SDHCI_CTRL_EXEC_TUNING);
+
+ if (tuning_loop_counter < 0 || (!(ctrl & SDHCI_CTRL_TUNED_CLK))) {
+ ctrl &= ~(SDHCI_CTRL_TUNED_CLK | SDHCI_CTRL_EXEC_TUNING);
+ sdhci_writel(host, ctrl, SDHCI_HOST_CONTROL2);
+ printf("%s:Tuning failed, opcode = 0x%02x\n", __func__, opcode);
+ ret = -EIO;
+ }
+
+ sdhci_end_tuning(host);
+
+ return ret;
}
static struct sdhci_ops sdhci_platform_ops = {
@@ -163,6 +238,7 @@
.write_b = sdhci_iproc_writeb,
#endif
.set_ios_post = sdhci_iproc_set_ios_post,
+ .platform_execute_tuning = sdhci_iproc_execute_tuning,
};
struct iproc_sdhci_plat {
@@ -190,9 +266,7 @@
host->name = dev->name;
host->ioaddr = dev_read_addr_ptr(dev);
- host->voltages = MMC_VDD_165_195 |
- MMC_VDD_32_33 | MMC_VDD_33_34;
- host->quirks = SDHCI_QUIRK_BROKEN_VOLTAGE | SDHCI_QUIRK_BROKEN_R1B;
+ host->quirks = SDHCI_QUIRK_BROKEN_R1B;
host->host_caps = MMC_MODE_DDR_52MHz;
host->index = fdtdec_get_uint(gd->fdt_blob, node, "index", 0);
host->ops = &sdhci_platform_ops;
diff --git a/drivers/mmc/mtk-sd.c b/drivers/mmc/mtk-sd.c
index 3b9c122..48a764b 100644
--- a/drivers/mmc/mtk-sd.c
+++ b/drivers/mmc/mtk-sd.c
@@ -1639,7 +1639,8 @@
else
cfg->f_min = host->src_clk_freq / (4 * 4095);
- cfg->f_max = host->src_clk_freq;
+ if (cfg->f_max < cfg->f_min || cfg->f_max > host->src_clk_freq)
+ cfg->f_max = host->src_clk_freq;
cfg->b_max = 1024;
cfg->voltages = MMC_VDD_32_33 | MMC_VDD_33_34;
diff --git a/drivers/mmc/sandbox_mmc.c b/drivers/mmc/sandbox_mmc.c
index 8a2391d..18ba020 100644
--- a/drivers/mmc/sandbox_mmc.c
+++ b/drivers/mmc/sandbox_mmc.c
@@ -17,6 +17,17 @@
struct mmc mmc;
};
+#define MMC_CSIZE 0
+#define MMC_CMULT 8 /* 8 because the card is high-capacity */
+#define MMC_BL_LEN_SHIFT 10
+#define MMC_BL_LEN BIT(MMC_BL_LEN_SHIFT)
+#define MMC_CAPACITY (((MMC_CSIZE + 1) << (MMC_CMULT + 2)) \
+ * MMC_BL_LEN) /* 1 MiB */
+
+struct sandbox_mmc_priv {
+ u8 buf[MMC_CAPACITY];
+};
+
/**
* sandbox_mmc_send_cmd() - Emulate SD commands
*
@@ -26,6 +37,10 @@
static int sandbox_mmc_send_cmd(struct udevice *dev, struct mmc_cmd *cmd,
struct mmc_data *data)
{
+ struct sandbox_mmc_priv *priv = dev_get_priv(dev);
+ struct mmc *mmc = mmc_get_mmc_dev(dev);
+ static ulong erase_start, erase_end;
+
switch (cmd->cmdidx) {
case MMC_CMD_ALL_SEND_CID:
memset(cmd->response, '\0', sizeof(cmd->response));
@@ -44,8 +59,9 @@
break;
case MMC_CMD_SEND_CSD:
cmd->response[0] = 0;
- cmd->response[1] = 10 << 16; /* 1 << block_len */
- cmd->response[2] = 0;
+ cmd->response[1] = (MMC_BL_LEN_SHIFT << 16) |
+ ((MMC_CSIZE >> 16) & 0x3f);
+ cmd->response[2] = (MMC_CSIZE & 0xffff) << 16;
cmd->response[3] = 0;
break;
case SD_CMD_SWITCH_FUNC: {
@@ -59,13 +75,27 @@
break;
}
case MMC_CMD_READ_SINGLE_BLOCK:
- memset(data->dest, '\0', data->blocksize);
- break;
case MMC_CMD_READ_MULTIPLE_BLOCK:
- strcpy(data->dest, "this is a test");
+ memcpy(data->dest, &priv->buf[cmd->cmdarg * data->blocksize],
+ data->blocks * data->blocksize);
+ break;
+ case MMC_CMD_WRITE_SINGLE_BLOCK:
+ case MMC_CMD_WRITE_MULTIPLE_BLOCK:
+ memcpy(&priv->buf[cmd->cmdarg * data->blocksize], data->src,
+ data->blocks * data->blocksize);
break;
case MMC_CMD_STOP_TRANSMISSION:
break;
+ case SD_CMD_ERASE_WR_BLK_START:
+ erase_start = cmd->cmdarg;
+ break;
+ case SD_CMD_ERASE_WR_BLK_END:
+ erase_end = cmd->cmdarg;
+ break;
+ case MMC_CMD_ERASE:
+ memset(&priv->buf[erase_start * mmc->write_bl_len], '\0',
+ (erase_end - erase_start + 1) * mmc->write_bl_len);
+ break;
case SD_CMD_APP_SEND_OP_COND:
cmd->response[0] = OCR_BUSY | OCR_HCS;
cmd->response[1] = 0;
@@ -148,5 +178,6 @@
.bind = sandbox_mmc_bind,
.unbind = sandbox_mmc_unbind,
.probe = sandbox_mmc_probe,
- .plat_auto = sizeof(struct sandbox_mmc_plat),
+ .priv_auto = sizeof(struct sandbox_mmc_priv),
+ .plat_auto = sizeof(struct sandbox_mmc_plat),
};
diff --git a/drivers/mmc/zynq_sdhci.c b/drivers/mmc/zynq_sdhci.c
index d9ad0ff..b79c402 100644
--- a/drivers/mmc/zynq_sdhci.c
+++ b/drivers/mmc/zynq_sdhci.c
@@ -577,7 +577,7 @@
debug("%s: CLK %ld\n", __func__, clock);
ret = clk_enable(&clk);
- if (ret && ret != -ENOSYS) {
+ if (ret) {
dev_err(dev, "failed to enable clock\n");
return ret;
}
diff --git a/drivers/mtd/nand/core.c b/drivers/mtd/nand/core.c
index 219efdc..090834a 100644
--- a/drivers/mtd/nand/core.c
+++ b/drivers/mtd/nand/core.c
@@ -10,6 +10,7 @@
#define pr_fmt(fmt) "nand: " fmt
#include <common.h>
+#include <watchdog.h>
#ifndef __UBOOT__
#include <linux/compat.h>
#include <linux/module.h>
@@ -172,6 +173,7 @@
nanddev_offs_to_pos(nand, einfo->addr, &pos);
nanddev_offs_to_pos(nand, einfo->addr + einfo->len - 1, &last);
while (nanddev_pos_cmp(&pos, &last) <= 0) {
+ WATCHDOG_RESET();
ret = nanddev_erase(nand, &pos);
if (ret) {
einfo->fail_addr = nanddev_pos_to_offs(nand, &pos);
diff --git a/drivers/mtd/nand/raw/cortina_nand.c b/drivers/mtd/nand/raw/cortina_nand.c
index 12bd1de..81fa878 100644
--- a/drivers/mtd/nand/raw/cortina_nand.c
+++ b/drivers/mtd/nand/raw/cortina_nand.c
@@ -546,7 +546,7 @@
struct nand_drv *info =
(struct nand_drv *)nand_get_controller_data(chip);
unsigned int reg_v, err_loc0, err_loc1;
- int k, max_bitflips;
+ int k, max_bitflips = 0;
for (k = 0; k < (err_num + 1) / 2; k++) {
reg_v = readl(&info->reg->flash_nf_bch_error_loc01 + k);
diff --git a/drivers/mtd/nand/spi/core.c b/drivers/mtd/nand/spi/core.c
index 68ef5d1..e533095 100644
--- a/drivers/mtd/nand/spi/core.c
+++ b/drivers/mtd/nand/spi/core.c
@@ -22,6 +22,7 @@
#else
#include <common.h>
#include <errno.h>
+#include <watchdog.h>
#include <spi.h>
#include <spi-mem.h>
#include <dm/device_compat.h>
@@ -578,6 +579,7 @@
#endif
nanddev_io_for_each_page(nand, from, ops, &iter) {
+ WATCHDOG_RESET();
ret = spinand_select_target(spinand, iter.req.pos.target);
if (ret)
break;
@@ -629,6 +631,7 @@
#endif
nanddev_io_for_each_page(nand, to, ops, &iter) {
+ WATCHDOG_RESET();
ret = spinand_select_target(spinand, iter.req.pos.target);
if (ret)
break;
diff --git a/drivers/mtd/nand/spi/gigadevice.c b/drivers/mtd/nand/spi/gigadevice.c
index 0b228dc..a2c9348 100644
--- a/drivers/mtd/nand/spi/gigadevice.c
+++ b/drivers/mtd/nand/spi/gigadevice.c
@@ -17,9 +17,22 @@
#define GD5FXGQ4XA_STATUS_ECC_1_7_BITFLIPS (1 << 4)
#define GD5FXGQ4XA_STATUS_ECC_8_BITFLIPS (3 << 4)
-#define GD5FXGQ4XEXXG_REG_STATUS2 0xf0
+#define GD5FXGQ5XE_STATUS_ECC_1_4_BITFLIPS (1 << 4)
+#define GD5FXGQ5XE_STATUS_ECC_4_BITFLIPS (3 << 4)
-static SPINAND_OP_VARIANTS(read_cache_variants,
+#define GD5FXGQXXEXXG_REG_STATUS2 0xf0
+
+/* Q4 devices, QUADIO: Dummy bytes valid for 1 and 2 GBit variants */
+static SPINAND_OP_VARIANTS(gd5fxgq4_read_cache_variants,
+ SPINAND_PAGE_READ_FROM_CACHE_QUADIO_OP(0, 1, NULL, 0),
+ SPINAND_PAGE_READ_FROM_CACHE_X4_OP(0, 1, NULL, 0),
+ SPINAND_PAGE_READ_FROM_CACHE_DUALIO_OP(0, 1, NULL, 0),
+ SPINAND_PAGE_READ_FROM_CACHE_X2_OP(0, 1, NULL, 0),
+ SPINAND_PAGE_READ_FROM_CACHE_OP(true, 0, 1, NULL, 0),
+ SPINAND_PAGE_READ_FROM_CACHE_OP(false, 0, 1, NULL, 0));
+
+/* Q5 devices, QUADIO: Dummy bytes only valid for 1 GBit variants */
+static SPINAND_OP_VARIANTS(gd5f1gq5_read_cache_variants,
SPINAND_PAGE_READ_FROM_CACHE_QUADIO_OP(0, 2, NULL, 0),
SPINAND_PAGE_READ_FROM_CACHE_X4_OP(0, 1, NULL, 0),
SPINAND_PAGE_READ_FROM_CACHE_DUALIO_OP(0, 1, NULL, 0),
@@ -35,7 +48,7 @@
SPINAND_PROG_LOAD_X4(false, 0, NULL, 0),
SPINAND_PROG_LOAD(false, 0, NULL, 0));
-static int gd5fxgq4xexxg_ooblayout_ecc(struct mtd_info *mtd, int section,
+static int gd5fxgqxxexxg_ooblayout_ecc(struct mtd_info *mtd, int section,
struct mtd_oob_region *region)
{
if (section)
@@ -47,7 +60,7 @@
return 0;
}
-static int gd5fxgq4xexxg_ooblayout_free(struct mtd_info *mtd, int section,
+static int gd5fxgqxxexxg_ooblayout_free(struct mtd_info *mtd, int section,
struct mtd_oob_region *region)
{
if (section)
@@ -64,7 +77,7 @@
u8 status)
{
u8 status2;
- struct spi_mem_op op = SPINAND_GET_FEATURE_OP(GD5FXGQ4XEXXG_REG_STATUS2,
+ struct spi_mem_op op = SPINAND_GET_FEATURE_OP(GD5FXGQXXEXXG_REG_STATUS2,
&status2);
int ret;
@@ -102,21 +115,67 @@
return -EINVAL;
}
+static int gd5fxgq5xexxg_ecc_get_status(struct spinand_device *spinand,
+ u8 status)
+{
+ u8 status2;
+ struct spi_mem_op op = SPINAND_GET_FEATURE_OP(GD5FXGQXXEXXG_REG_STATUS2,
+ &status2);
+ int ret;
+
+ switch (status & STATUS_ECC_MASK) {
+ case STATUS_ECC_NO_BITFLIPS:
+ return 0;
+
+ case GD5FXGQ5XE_STATUS_ECC_1_4_BITFLIPS:
+ /*
+ * Read status2 register to determine a more fine grained
+ * bit error status
+ */
+ ret = spi_mem_exec_op(spinand->slave, &op);
+ if (ret)
+ return ret;
+
+ /*
+ * 1 ... 4 bits are flipped (and corrected)
+ */
+ /* bits sorted this way (1...0): ECCSE1, ECCSE0 */
+ return ((status2 & STATUS_ECC_MASK) >> 4) + 1;
+
+ case STATUS_ECC_UNCOR_ERROR:
+ return -EBADMSG;
+
+ default:
+ break;
+ }
+
+ return -EINVAL;
+}
+
-static const struct mtd_ooblayout_ops gd5fxgq4xexxg_ooblayout = {
- .ecc = gd5fxgq4xexxg_ooblayout_ecc,
- .rfree = gd5fxgq4xexxg_ooblayout_free,
+static const struct mtd_ooblayout_ops gd5fxgqxxexxg_ooblayout = {
+ .ecc = gd5fxgqxxexxg_ooblayout_ecc,
+ .rfree = gd5fxgqxxexxg_ooblayout_free,
};
static const struct spinand_info gigadevice_spinand_table[] = {
SPINAND_INFO("GD5F1GQ4UExxG", 0xd1,
NAND_MEMORG(1, 2048, 128, 64, 1024, 1, 1, 1),
NAND_ECCREQ(8, 512),
- SPINAND_INFO_OP_VARIANTS(&read_cache_variants,
+ SPINAND_INFO_OP_VARIANTS(&gd5fxgq4_read_cache_variants,
&write_cache_variants,
&update_cache_variants),
0,
- SPINAND_ECCINFO(&gd5fxgq4xexxg_ooblayout,
+ SPINAND_ECCINFO(&gd5fxgqxxexxg_ooblayout,
gd5fxgq4xexxg_ecc_get_status)),
+ SPINAND_INFO("GD5F1GQ5UExxG", 0x51,
+ NAND_MEMORG(1, 2048, 128, 64, 1024, 1, 1, 1),
+ NAND_ECCREQ(4, 512),
+ SPINAND_INFO_OP_VARIANTS(&gd5f1gq5_read_cache_variants,
+ &write_cache_variants,
+ &update_cache_variants),
+ 0,
+ SPINAND_ECCINFO(&gd5fxgqxxexxg_ooblayout,
+ gd5fxgq5xexxg_ecc_get_status)),
};
static int gigadevice_spinand_detect(struct spinand_device *spinand)
diff --git a/drivers/mtd/spi/spi-nor-core.c b/drivers/mtd/spi/spi-nor-core.c
index ef426da..e0efebc 100644
--- a/drivers/mtd/spi/spi-nor-core.c
+++ b/drivers/mtd/spi/spi-nor-core.c
@@ -11,6 +11,7 @@
#include <common.h>
#include <log.h>
+#include <watchdog.h>
#include <dm.h>
#include <dm/device_compat.h>
#include <dm/devres.h>
@@ -566,6 +567,7 @@
len = instr->len;
while (len) {
+ WATCHDOG_RESET();
#ifdef CONFIG_SPI_FLASH_BAR
ret = write_bar(nor, addr);
if (ret < 0)
@@ -1250,6 +1252,7 @@
for (i = 0; i < len; ) {
ssize_t written;
loff_t addr = to + i;
+ WATCHDOG_RESET();
/*
* If page_size is a power of two, the offset can be quickly
diff --git a/drivers/mtd/spi/spi-nor-ids.c b/drivers/mtd/spi/spi-nor-ids.c
index 5bd5dd3..2b57797 100644
--- a/drivers/mtd/spi/spi-nor-ids.c
+++ b/drivers/mtd/spi/spi-nor-ids.c
@@ -108,6 +108,11 @@
SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB)
},
{
+ INFO("gd25lq64c", 0xc86017, 0, 64 * 1024, 128,
+ SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ |
+ SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB)
+ },
+ {
INFO("gd25q128", 0xc84018, 0, 64 * 1024, 256,
SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ |
SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB)
@@ -319,7 +324,10 @@
{ INFO("w25q80bl", 0xef4014, 0, 64 * 1024, 16, SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) },
{ INFO("w25q16cl", 0xef4015, 0, 64 * 1024, 32, SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) },
{ INFO("w25q64cv", 0xef4017, 0, 64 * 1024, 128, SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) },
- { INFO("w25q128", 0xef4018, 0, 64 * 1024, 256, SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) },
+ { INFO("w25q128", 0xef4018, 0, 64 * 1024, 256,
+ SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ |
+ SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB)
+ },
{ INFO("w25q256", 0xef4019, 0, 64 * 1024, 512, SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) },
{ INFO("w25m512jw", 0xef6119, 0, 64 * 1024, 1024, SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) },
{ INFO("w25m512jv", 0xef7119, 0, 64 * 1024, 1024, SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) },
diff --git a/drivers/net/cortina_ni.c b/drivers/net/cortina_ni.c
index ee424d9..ef6ecd8 100644
--- a/drivers/net/cortina_ni.c
+++ b/drivers/net/cortina_ni.c
@@ -713,7 +713,7 @@
priv->rx_xram_end_adr);
memcpy(&packet_status, rx_xram_ptr,
- sizeof(rx_xram_ptr));
+ sizeof(*rx_xram_ptr));
if (packet_status.valid == 0) {
debug("%s: Invalid Packet !!, ", __func__);
debug("next_link=%d\n", next_link);
diff --git a/drivers/net/zynq_gem.c b/drivers/net/zynq_gem.c
index 5cb02bb..baf06a2 100644
--- a/drivers/net/zynq_gem.c
+++ b/drivers/net/zynq_gem.c
@@ -129,6 +129,8 @@
#define ZYNQ_GEM_FREQUENCY_100 25000000UL
#define ZYNQ_GEM_FREQUENCY_1000 125000000UL
+#define RXCLK_EN BIT(0)
+
/* Device registers */
struct zynq_gem_regs {
u32 nwctrl; /* 0x0 - Network Control reg */
@@ -205,10 +207,12 @@
struct phy_device *phydev;
ofnode phy_of_node;
struct mii_dev *bus;
- struct clk clk;
+ struct clk rx_clk;
+ struct clk tx_clk;
u32 max_speed;
bool int_pcs;
bool dma_64bit;
+ u32 clk_en_info;
};
static int phy_setup_op(struct zynq_gem_priv *priv, u32 phy_addr, u32 regnum,
@@ -476,18 +480,25 @@
break;
}
- ret = clk_set_rate(&priv->clk, clk_rate);
- if (IS_ERR_VALUE(ret) && ret != (unsigned long)-ENOSYS) {
+ ret = clk_set_rate(&priv->tx_clk, clk_rate);
+ if (IS_ERR_VALUE(ret)) {
dev_err(dev, "failed to set tx clock rate\n");
return ret;
}
- ret = clk_enable(&priv->clk);
- if (ret && ret != -ENOSYS) {
+ ret = clk_enable(&priv->tx_clk);
+ if (ret) {
dev_err(dev, "failed to enable tx clock\n");
return ret;
}
+ if (priv->clk_en_info & RXCLK_EN) {
+ ret = clk_enable(&priv->rx_clk);
+ if (ret) {
+ dev_err(dev, "failed to enable rx clock\n");
+ return ret;
+ }
+ }
setbits_le32(®s->nwctrl, ZYNQ_GEM_NWCTRL_RXEN_MASK |
ZYNQ_GEM_NWCTRL_TXEN_MASK);
@@ -694,10 +705,18 @@
priv->tx_bd = (struct emac_bd *)bd_space;
priv->rx_bd = (struct emac_bd *)((ulong)bd_space + BD_SEPRN_SPACE);
- ret = clk_get_by_name(dev, "tx_clk", &priv->clk);
+ ret = clk_get_by_name(dev, "tx_clk", &priv->tx_clk);
if (ret < 0) {
- dev_err(dev, "failed to get clock\n");
- goto err1;
+ dev_err(dev, "failed to get tx_clock\n");
+ goto err2;
+ }
+
+ if (priv->clk_en_info & RXCLK_EN) {
+ ret = clk_get_by_name(dev, "rx_clk", &priv->rx_clk);
+ if (ret < 0) {
+ dev_err(dev, "failed to get rx_clock\n");
+ goto err2;
+ }
}
priv->bus = mdio_alloc();
@@ -711,14 +730,16 @@
ret = zynq_phy_init(dev);
if (ret)
- goto err2;
+ goto err3;
return ret;
+err3:
+ mdio_unregister(priv->bus);
err2:
- free(priv->rxbuffers);
-err1:
free(priv->tx_bd);
+err1:
+ free(priv->rxbuffers);
return ret;
}
@@ -792,11 +813,13 @@
(ulong)priv->iobase, (ulong)priv->mdiobase, priv->phyaddr,
phy_string_for_interface(priv->interface));
+ priv->clk_en_info = dev_get_driver_data(dev);
+
return 0;
}
static const struct udevice_id zynq_gem_ids[] = {
- { .compatible = "cdns,versal-gem" },
+ { .compatible = "cdns,versal-gem", .data = RXCLK_EN },
{ .compatible = "cdns,zynqmp-gem" },
{ .compatible = "cdns,zynq-gem" },
{ .compatible = "cdns,gem" },
diff --git a/drivers/pci/fsl_pci_init.c b/drivers/pci/fsl_pci_init.c
index e72a60c..fc3327e 100644
--- a/drivers/pci/fsl_pci_init.c
+++ b/drivers/pci/fsl_pci_init.c
@@ -32,6 +32,8 @@
#include <asm/io.h>
#include <asm/fsl_pci.h>
+#define MAX_PCI_REGIONS 7
+
#ifndef CONFIG_SYS_PCI_MEMORY_BUS
#define CONFIG_SYS_PCI_MEMORY_BUS 0
#endif
@@ -80,6 +82,9 @@
/* Reset hose to make sure its in a clean state */
memset(hose, 0, sizeof(struct pci_controller));
+ hose->regions = (struct pci_region *)
+ calloc(1, MAX_PCI_REGIONS * sizeof(struct pci_region));
+
pci_setup_indirect(hose, (u32)&pci->cfg_addr, (u32)&pci->cfg_data);
return fsl_is_pci_agent(hose);
diff --git a/drivers/pci/pci-aardvark.c b/drivers/pci/pci-aardvark.c
index 8713b88..3b9309f 100644
--- a/drivers/pci/pci-aardvark.c
+++ b/drivers/pci/pci-aardvark.c
@@ -42,6 +42,10 @@
#define PCIE_CORE_DEV_CTRL_STATS_REG 0xc8
#define PCIE_CORE_DEV_CTRL_STATS_RELAX_ORDER_DISABLE (0 << 4)
#define PCIE_CORE_DEV_CTRL_STATS_SNOOP_DISABLE (0 << 11)
+#define PCIE_CORE_DEV_CTRL_STATS_MAX_PAYLOAD_SIZE 0x2
+#define PCIE_CORE_DEV_CTRL_STATS_MAX_PAYLOAD_SIZE_SHIFT 5
+#define PCIE_CORE_DEV_CTRL_STATS_MAX_RD_REQ_SIZE 0x2
+#define PCIE_CORE_DEV_CTRL_STATS_MAX_RD_REQ_SIZE_SHIFT 12
#define PCIE_CORE_LINK_CTRL_STAT_REG 0xd0
#define PCIE_CORE_LINK_TRAINING BIT(5)
#define PCIE_CORE_ERR_CAPCTL_REG 0x118
@@ -101,6 +105,7 @@
#define LTSSM_SHIFT 24
#define LTSSM_MASK 0x3f
#define LTSSM_L0 0x10
+#define VENDOR_ID_REG (LMI_BASE_ADDR + 0x44)
/* PCIe core controller registers */
#define CTRL_CORE_BASE_ADDR 0x18000
@@ -525,6 +530,15 @@
reg |= (IS_RC_MSK << IS_RC_SHIFT);
advk_writel(pcie, reg, PCIE_CORE_CTRL0_REG);
+ /*
+ * Replace incorrect PCI vendor id value 0x1b4b by correct value 0x11ab.
+ * VENDOR_ID_REG contains vendor id in low 16 bits and subsystem vendor
+ * id in high 16 bits. Updating this register changes readback value of
+ * read-only vendor id bits in PCIE_CORE_DEV_ID_REG register. Workaround
+ * for erratum 4.1: "The value of device and vendor ID is incorrect".
+ */
+ advk_writel(pcie, 0x11ab11ab, VENDOR_ID_REG);
+
/* Set Advanced Error Capabilities and Control PF0 register */
reg = PCIE_CORE_ERR_CAPCTL_ECRC_CHK_TX |
PCIE_CORE_ERR_CAPCTL_ECRC_CHK_TX_EN |
@@ -534,6 +548,10 @@
/* Set PCIe Device Control and Status 1 PF0 register */
reg = PCIE_CORE_DEV_CTRL_STATS_RELAX_ORDER_DISABLE |
+ (PCIE_CORE_DEV_CTRL_STATS_MAX_PAYLOAD_SIZE <<
+ PCIE_CORE_DEV_CTRL_STATS_MAX_PAYLOAD_SIZE_SHIFT) |
+ (PCIE_CORE_DEV_CTRL_STATS_MAX_RD_REQ_SIZE <<
+ PCIE_CORE_DEV_CTRL_STATS_MAX_RD_REQ_SIZE_SHIFT) |
PCIE_CORE_DEV_CTRL_STATS_SNOOP_DISABLE;
advk_writel(pcie, reg, PCIE_CORE_DEV_CTRL_STATS_REG);
diff --git a/drivers/pci/pci_mpc85xx.c b/drivers/pci/pci_mpc85xx.c
index ab6ff45..574cb78 100644
--- a/drivers/pci/pci_mpc85xx.c
+++ b/drivers/pci/pci_mpc85xx.c
@@ -46,6 +46,7 @@
return 0;
}
+#ifdef CONFIG_FSL_LAW
static int
mpc85xx_pci_dm_setup_laws(struct pci_region *io, struct pci_region *mem,
struct pci_region *pre)
@@ -68,6 +69,7 @@
return 0;
}
+#endif
static int mpc85xx_pci_dm_probe(struct udevice *dev)
{
@@ -85,22 +87,24 @@
return -EINVAL;
}
+#ifdef CONFIG_FSL_LAW
mpc85xx_pci_dm_setup_laws(io, mem, pre);
+#endif
pcix = priv->cfg_addr;
/* BAR 1: memory */
- out_be32(&pcix->potar1, (mem->bus_start >> 12) & 0x000fffff);
- out_be32(&pcix->potear1, 0);
- out_be32(&pcix->powbar1, (mem->phys_start >> 12) & 0x000fffff);
- out_be32(&pcix->powbear1, 0);
+ out_be32(&pcix->potar1, mem->bus_start >> 12);
+ out_be32(&pcix->potear1, (u64)mem->bus_start >> 44);
+ out_be32(&pcix->powbar1, mem->phys_start >> 12);
+ out_be32(&pcix->powbear1, (u64)mem->phys_start >> 44);
out_be32(&pcix->powar1, (POWAR_EN | POWAR_MEM_READ |
POWAR_MEM_WRITE | (__ilog2(mem->size) - 1)));
/* BAR 1: IO */
- out_be32(&pcix->potar2, (io->bus_start >> 12) & 0x000fffff);
- out_be32(&pcix->potear2, 0);
- out_be32(&pcix->powbar2, (io->phys_start >> 12) & 0x000fffff);
- out_be32(&pcix->powbear2, 0);
+ out_be32(&pcix->potar2, io->bus_start >> 12);
+ out_be32(&pcix->potear2, (u64)io->bus_start >> 44);
+ out_be32(&pcix->powbar2, io->phys_start >> 12);
+ out_be32(&pcix->powbear2, (u64)io->phys_start >> 44);
out_be32(&pcix->powar2, (POWAR_EN | POWAR_IO_READ |
POWAR_IO_WRITE | (__ilog2(io->size) - 1)));
@@ -130,9 +134,8 @@
addr = devfdt_get_addr_index(dev, 0);
if (addr == FDT_ADDR_T_NONE)
return -EINVAL;
- priv->cfg_addr = (void __iomem *)addr;
- addr += 4;
- priv->cfg_data = (void __iomem *)addr;
+ priv->cfg_addr = (void __iomem *)map_physmem(addr, 0, MAP_NOCACHE);
+ priv->cfg_data = (void __iomem *)((ulong)priv->cfg_addr + 4);
return 0;
}
diff --git a/drivers/pci/pci_mvebu.c b/drivers/pci/pci_mvebu.c
index 235d9bb..0c1d7cd 100644
--- a/drivers/pci/pci_mvebu.c
+++ b/drivers/pci/pci_mvebu.c
@@ -79,7 +79,8 @@
u32 lane;
int devfn;
u32 lane_mask;
- pci_dev_t dev;
+ int first_busno;
+ int local_dev;
char name[16];
unsigned int mem_target;
unsigned int mem_attr;
@@ -144,38 +145,47 @@
return container_of(hose, struct mvebu_pcie, hose);
}
+static int mvebu_pcie_valid_addr(struct mvebu_pcie *pcie, pci_dev_t bdf)
+{
+ /*
+ * There are two devices visible on local bus:
+ * * on slot configured by function mvebu_pcie_set_local_dev_nr()
+ * (by default this register is set to 0) there is a
+ * "Marvell Memory controller", which isn't useful in root complex
+ * mode,
+ * * on all other slots the real PCIe card connected to the PCIe slot.
+ *
+ * We therefore allow access only to the real PCIe card.
+ */
+ if (PCI_BUS(bdf) == pcie->first_busno &&
+ PCI_DEV(bdf) != !pcie->local_dev)
+ return 0;
+
+ return 1;
+}
+
static int mvebu_pcie_read_config(const struct udevice *bus, pci_dev_t bdf,
uint offset, ulong *valuep,
enum pci_size_t size)
{
struct mvebu_pcie *pcie = dev_get_plat(bus);
- int local_bus = PCI_BUS(pcie->dev);
- int local_dev = PCI_DEV(pcie->dev);
- u32 reg;
u32 data;
- debug("PCIE CFG read: loc_bus=%d loc_dev=%d (b,d,f)=(%2d,%2d,%2d) ",
- local_bus, local_dev, PCI_BUS(bdf), PCI_DEV(bdf), PCI_FUNC(bdf));
-
- /* Don't access the local host controller via this API */
- if (PCI_BUS(bdf) == local_bus && PCI_DEV(bdf) == local_dev) {
- debug("- skipping host controller\n");
- *valuep = pci_get_ff(size);
- return 0;
- }
+ debug("PCIE CFG read: (b,d,f)=(%2d,%2d,%2d) ",
+ PCI_BUS(bdf), PCI_DEV(bdf), PCI_FUNC(bdf));
- /* If local dev is 0, the first other dev can only be 1 */
- if (PCI_BUS(bdf) == local_bus && local_dev == 0 && PCI_DEV(bdf) != 1) {
+ if (!mvebu_pcie_valid_addr(pcie, bdf)) {
debug("- out of range\n");
*valuep = pci_get_ff(size);
return 0;
}
/* write address */
- reg = PCIE_CONF_ADDR(bdf, offset);
- writel(reg, pcie->base + PCIE_CONF_ADDR_OFF);
+ writel(PCIE_CONF_ADDR(bdf, offset), pcie->base + PCIE_CONF_ADDR_OFF);
+
+ /* read data */
data = readl(pcie->base + PCIE_CONF_DATA_OFF);
- debug("(addr,val)=(0x%04x, 0x%08x)\n", offset, data);
+ debug("(addr,size,val)=(0x%04x, %d, 0x%08x)\n", offset, size, data);
*valuep = pci_conv_32_to_size(data, offset, size);
return 0;
@@ -186,27 +196,21 @@
enum pci_size_t size)
{
struct mvebu_pcie *pcie = dev_get_plat(bus);
- int local_bus = PCI_BUS(pcie->dev);
- int local_dev = PCI_DEV(pcie->dev);
u32 data;
- debug("PCIE CFG write: loc_bus=%d loc_dev=%d (b,d,f)=(%2d,%2d,%2d) ",
- local_bus, local_dev, PCI_BUS(bdf), PCI_DEV(bdf), PCI_FUNC(bdf));
- debug("(addr,val)=(0x%04x, 0x%08lx)\n", offset, value);
-
- /* Don't access the local host controller via this API */
- if (PCI_BUS(bdf) == local_bus && PCI_DEV(bdf) == local_dev) {
- debug("- skipping host controller\n");
- return 0;
- }
+ debug("PCIE CFG write: (b,d,f)=(%2d,%2d,%2d) ",
+ PCI_BUS(bdf), PCI_DEV(bdf), PCI_FUNC(bdf));
+ debug("(addr,size,val)=(0x%04x, %d, 0x%08lx)\n", offset, size, value);
- /* If local dev is 0, the first other dev can only be 1 */
- if (PCI_BUS(bdf) == local_bus && local_dev == 0 && PCI_DEV(bdf) != 1) {
+ if (!mvebu_pcie_valid_addr(pcie, bdf)) {
debug("- out of range\n");
return 0;
}
+ /* write address */
writel(PCIE_CONF_ADDR(bdf, offset), pcie->base + PCIE_CONF_ADDR_OFF);
+
+ /* write data */
data = pci_conv_size_to_32(0, value, offset, size);
writel(data, pcie->base + PCIE_CONF_DATA_OFF);
@@ -273,7 +277,7 @@
struct mvebu_pcie *pcie = dev_get_plat(dev);
struct udevice *ctlr = pci_get_controller(dev);
struct pci_controller *hose = dev_get_uclass_priv(ctlr);
- static int bus;
+ int bus = dev_seq(dev);
u32 reg;
debug("%s: PCIe %d.%d - up, base %08x\n", __func__,
@@ -284,9 +288,11 @@
readl(pcie->base), mvebu_pcie_get_local_bus_nr(pcie),
mvebu_pcie_get_local_dev_nr(pcie));
+ pcie->first_busno = bus;
+ pcie->local_dev = 1;
+
mvebu_pcie_set_local_bus_nr(pcie, bus);
- mvebu_pcie_set_local_dev_nr(pcie, 0);
- pcie->dev = PCI_BDF(bus, 0, 0);
+ mvebu_pcie_set_local_dev_nr(pcie, pcie->local_dev);
pcie->mem.start = (u32)mvebu_pcie_membase;
pcie->mem.end = pcie->mem.start + PCIE_MEM_SIZE - 1;
@@ -336,8 +342,6 @@
writel(SOC_REGS_PHY_BASE, pcie->base + PCIE_BAR_LO_OFF(0));
writel(0, pcie->base + PCIE_BAR_HI_OFF(0));
- bus++;
-
return 0;
}
diff --git a/drivers/power/pmic/Makefile b/drivers/power/pmic/Makefile
index 2b2a6dd..7b4c0f0 100644
--- a/drivers/power/pmic/Makefile
+++ b/drivers/power/pmic/Makefile
@@ -31,8 +31,6 @@
obj-$(CONFIG_POWER_LTC3676) += pmic_ltc3676.o
obj-$(CONFIG_POWER_MAX77696) += pmic_max77696.o
-obj-$(CONFIG_POWER_MAX8998) += pmic_max8998.o
-obj-$(CONFIG_POWER_MAX8997) += pmic_max8997.o
obj-$(CONFIG_POWER_MUIC_MAX8997) += muic_max8997.o
obj-$(CONFIG_POWER_PCA9450) += pmic_pca9450.o
obj-$(CONFIG_POWER_PFUZE100) += pmic_pfuze100.o
diff --git a/drivers/power/pmic/pmic_max8997.c b/drivers/power/pmic/pmic_max8997.c
deleted file mode 100644
index 1d834ff7..0000000
--- a/drivers/power/pmic/pmic_max8997.c
+++ /dev/null
@@ -1,107 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * Copyright (C) 2012 Samsung Electronics
- * Lukasz Majewski <l.majewski@samsung.com>
- */
-
-#include <common.h>
-#include <log.h>
-#include <power/pmic.h>
-#include <power/max8997_pmic.h>
-#include <i2c.h>
-#include <errno.h>
-
-unsigned char max8997_reg_ldo(int uV)
-{
- unsigned char ret;
- if (uV <= 800000)
- return 0;
- if (uV >= 3950000)
- return MAX8997_LDO_MAX_VAL;
- ret = (uV - 800000) / 50000;
- if (ret > MAX8997_LDO_MAX_VAL) {
- printf("MAX8997 LDO SETTING ERROR (%duV) -> %u\n", uV, ret);
- ret = MAX8997_LDO_MAX_VAL;
- }
-
- return ret;
-}
-
-static int pmic_charger_state(struct pmic *p, int state, int current)
-{
- unsigned char fc;
- u32 val = 0;
-
- if (pmic_probe(p))
- return -ENODEV;
-
- if (state == PMIC_CHARGER_DISABLE) {
- puts("Disable the charger.\n");
- pmic_reg_read(p, MAX8997_REG_MBCCTRL2, &val);
- val &= ~(MBCHOSTEN | VCHGR_FC);
- pmic_reg_write(p, MAX8997_REG_MBCCTRL2, val);
-
- return -ENOTSUPP;
- }
-
- if (current < CHARGER_MIN_CURRENT || current > CHARGER_MAX_CURRENT) {
- printf("%s: Wrong charge current: %d [mA]\n",
- __func__, current);
- return -EINVAL;
- }
-
- fc = (current - CHARGER_MIN_CURRENT) / CHARGER_CURRENT_RESOLUTION;
- fc = fc & 0xf; /* up to 950 mA */
-
- printf("Enable the charger @ %d [mA]\n", fc * CHARGER_CURRENT_RESOLUTION
- + CHARGER_MIN_CURRENT);
-
- val = fc | MBCICHFCSET;
- pmic_reg_write(p, MAX8997_REG_MBCCTRL4, val);
-
- pmic_reg_read(p, MAX8997_REG_MBCCTRL2, &val);
- val = MBCHOSTEN | VCHGR_FC; /* enable charger & fast charge */
- pmic_reg_write(p, MAX8997_REG_MBCCTRL2, val);
-
- return 0;
-}
-
-static int pmic_charger_bat_present(struct pmic *p)
-{
- u32 val;
-
- if (pmic_probe(p))
- return -ENODEV;
-
- pmic_reg_read(p, MAX8997_REG_STATUS4, &val);
-
- return !(val & DETBAT);
-}
-
-static struct power_chrg power_chrg_pmic_ops = {
- .chrg_bat_present = pmic_charger_bat_present,
- .chrg_state = pmic_charger_state,
-};
-
-int pmic_init(unsigned char bus)
-{
- static const char name[] = "MAX8997_PMIC";
- struct pmic *p = pmic_alloc();
-
- if (!p) {
- printf("%s: POWER allocation error!\n", __func__);
- return -ENOMEM;
- }
-
- debug("Board PMIC init\n");
-
- p->name = name;
- p->interface = PMIC_I2C;
- p->number_of_regs = PMIC_NUM_OF_REGS;
- p->hw.i2c.addr = MAX8997_I2C_ADDR;
- p->hw.i2c.tx_num = 1;
- p->bus = bus;
-
- p->chrg = &power_chrg_pmic_ops;
- return 0;
-}
diff --git a/drivers/power/pmic/pmic_max8998.c b/drivers/power/pmic/pmic_max8998.c
deleted file mode 100644
index f058238..0000000
--- a/drivers/power/pmic/pmic_max8998.c
+++ /dev/null
@@ -1,32 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * Copyright (C) 2011 Samsung Electronics
- * Lukasz Majewski <l.majewski@samsung.com>
- */
-
-#include <common.h>
-#include <power/pmic.h>
-#include <power/max8998_pmic.h>
-#include <errno.h>
-
-int pmic_init(unsigned char bus)
-{
- static const char name[] = "MAX8998_PMIC";
- struct pmic *p = pmic_alloc();
-
- if (!p) {
- printf("%s: POWER allocation error!\n", __func__);
- return -ENOMEM;
- }
-
- puts("Board PMIC init\n");
-
- p->name = name;
- p->interface = PMIC_I2C;
- p->number_of_regs = PMIC_NUM_OF_REGS;
- p->hw.i2c.addr = MAX8998_I2C_ADDR;
- p->hw.i2c.tx_num = 1;
- p->bus = bus;
-
- return 0;
-}
diff --git a/drivers/rng/iproc_rng200.c b/drivers/rng/iproc_rng200.c
index f71f285..85ac15b 100644
--- a/drivers/rng/iproc_rng200.c
+++ b/drivers/rng/iproc_rng200.c
@@ -33,13 +33,13 @@
#define RNG_FIFO_COUNT_OFFSET 0x24
#define RNG_FIFO_COUNT_RNG_FIFO_COUNT_MASK 0x000000FF
-struct iproc_rng200_platdata {
- fdt_addr_t base;
+struct iproc_rng200_plat {
+ void __iomem *base;
};
-static void iproc_rng200_enable(struct iproc_rng200_platdata *pdata, bool enable)
+static void iproc_rng200_enable(struct iproc_rng200_plat *pdata, bool enable)
{
- fdt_addr_t rng_base = pdata->base;
+ void __iomem *rng_base = pdata->base;
u32 val;
val = readl(rng_base + RNG_CTRL_OFFSET);
@@ -52,9 +52,9 @@
writel(val, rng_base + RNG_CTRL_OFFSET);
}
-static void iproc_rng200_restart(struct iproc_rng200_platdata *pdata)
+static void iproc_rng200_restart(struct iproc_rng200_plat *pdata)
{
- fdt_addr_t rng_base = pdata->base;
+ void __iomem *rng_base = pdata->base;
u32 val;
iproc_rng200_enable(pdata, false);
@@ -84,7 +84,7 @@
static int iproc_rng200_read(struct udevice *dev, void *data, size_t len)
{
- struct iproc_rng200_platdata *priv = dev_get_plat(dev);
+ struct iproc_rng200_plat *priv = dev_get_plat(dev);
char *buf = (char *)data;
u32 num_remaining = len;
u32 status;
@@ -136,7 +136,7 @@
static int iproc_rng200_probe(struct udevice *dev)
{
- struct iproc_rng200_platdata *priv = dev_get_plat(dev);
+ struct iproc_rng200_plat *priv = dev_get_plat(dev);
iproc_rng200_enable(priv, true);
@@ -145,18 +145,18 @@
static int iproc_rng200_remove(struct udevice *dev)
{
- struct iproc_rng200_platdata *priv = dev_get_plat(dev);
+ struct iproc_rng200_plat *priv = dev_get_plat(dev);
iproc_rng200_enable(priv, false);
return 0;
}
-static int iproc_rng200_ofdata_to_platdata(struct udevice *dev)
+static int iproc_rng200_of_to_plat(struct udevice *dev)
{
- struct iproc_rng200_platdata *pdata = dev_get_plat(dev);
+ struct iproc_rng200_plat *pdata = dev_get_plat(dev);
- pdata->base = dev_read_addr(dev);
+ pdata->base = devfdt_map_physmem(dev, sizeof(void *));
if (!pdata->base)
return -ENODEV;
@@ -180,6 +180,6 @@
.ops = &iproc_rng200_ops,
.probe = iproc_rng200_probe,
.remove = iproc_rng200_remove,
- .plat_auto = sizeof(struct iproc_rng200_platdata),
- .of_to_plat = iproc_rng200_ofdata_to_platdata,
+ .priv_auto = sizeof(struct iproc_rng200_plat),
+ .of_to_plat = iproc_rng200_of_to_plat,
};
diff --git a/drivers/serial/Kconfig b/drivers/serial/Kconfig
index 79ad0a1..24413d1 100644
--- a/drivers/serial/Kconfig
+++ b/drivers/serial/Kconfig
@@ -722,6 +722,13 @@
This uses the ns16550 driver, converting the platdata from of-platdata
to the ns16550 format.
+config S5P_SERIAL
+ bool "Support for Samsung S5P UART"
+ depends on ARCH_EXYNOS || ARCH_S5PC1XX
+ default y
+ help
+ Select this to enable Samsung S5P UART support.
+
config SANDBOX_SERIAL
bool "Sandbox UART support"
depends on SANDBOX
diff --git a/drivers/serial/Makefile b/drivers/serial/Makefile
index 0c3810f..92bcb30 100644
--- a/drivers/serial/Makefile
+++ b/drivers/serial/Makefile
@@ -41,7 +41,7 @@
obj-$(CONFIG_LPC32XX_HSUART) += lpc32xx_hsuart.o
obj-$(CONFIG_MCFUART) += serial_mcf.o
obj-$(CONFIG_SYS_NS16550) += ns16550.o
-obj-$(CONFIG_S5P) += serial_s5p.o
+obj-$(CONFIG_S5P_SERIAL) += serial_s5p.o
obj-$(CONFIG_MXC_UART) += serial_mxc.o
obj-$(CONFIG_PXA_SERIAL) += serial_pxa.o
obj-$(CONFIG_MESON_SERIAL) += serial_meson.o
diff --git a/drivers/serial/ns16550.c b/drivers/serial/ns16550.c
index b9e99ba..cc121ee 100644
--- a/drivers/serial/ns16550.c
+++ b/drivers/serial/ns16550.c
@@ -483,7 +483,7 @@
return 0;
}
-static int ns16550_serial_assign_base(struct ns16550_plat *plat, ulong base)
+static int ns16550_serial_assign_base(struct ns16550_plat *plat, fdt_addr_t base)
{
if (base == FDT_ADDR_T_NONE)
return -EINVAL;
@@ -564,6 +564,8 @@
if (!plat->clock)
plat->clock = dev_read_u32_default(dev, "clock-frequency",
CONFIG_SYS_NS16550_CLK);
+ if (!plat->clock)
+ plat->clock = CONFIG_SYS_NS16550_CLK;
if (!plat->clock) {
debug("ns16550 clock not defined\n");
return -EINVAL;
diff --git a/drivers/serial/serial_zynq.c b/drivers/serial/serial_zynq.c
index 2883e24..799d524 100644
--- a/drivers/serial/serial_zynq.c
+++ b/drivers/serial/serial_zynq.c
@@ -127,7 +127,7 @@
debug("%s: CLK %ld\n", __func__, clock);
ret = clk_enable(&clk);
- if (ret && ret != -ENOSYS) {
+ if (ret) {
dev_err(dev, "failed to enable clock\n");
return ret;
}
diff --git a/drivers/serial/usbtty.c b/drivers/serial/usbtty.c
index f1c1a26..4f4eb02 100644
--- a/drivers/serial/usbtty.c
+++ b/drivers/serial/usbtty.c
@@ -500,8 +500,8 @@
n = next_nl_pos (str);
if (str[n] == '\n') {
- __usbtty_puts("\r", 1);
- __usbtty_puts(str, n + 1);
+ __usbtty_puts(str, n);
+ __usbtty_puts("\r\n", 2);
str += (n + 1);
len -= (n + 1);
} else {
@@ -849,17 +849,9 @@
&endpoint_instance[tx_endpoint];
struct urb *current_urb = NULL;
- current_urb = next_urb (device_instance, endpoint);
-
- if (!current_urb) {
- TTYERR ("current_urb is NULL, buf->size %d\n",
- buf->size);
- return 0;
- }
-
/* TX data still exists - send it now
*/
- if(endpoint->sent < current_urb->actual_length){
+ if(endpoint->sent < endpoint->tx_urb->actual_length){
if(udc_endpoint_write (endpoint)){
/* Write pre-empted by RX */
return -1;
@@ -878,6 +870,8 @@
*/
while (buf->size > 0) {
+ current_urb = next_urb (device_instance, endpoint);
+
dest = (char*)current_urb->buffer +
current_urb->actual_length;
diff --git a/drivers/spi/mxc_spi.c b/drivers/spi/mxc_spi.c
index bb68eb9..f3dddbd 100644
--- a/drivers/spi/mxc_spi.c
+++ b/drivers/spi/mxc_spi.c
@@ -662,7 +662,10 @@
static int mxc_spi_set_speed(struct udevice *bus, uint speed)
{
- /* Nothing to do */
+ struct mxc_spi_slave *mxcs = dev_get_plat(bus);
+
+ mxcs->max_hz = speed;
+
return 0;
}
diff --git a/drivers/spi/nxp_fspi.c b/drivers/spi/nxp_fspi.c
index 012f304..6c5bad4 100644
--- a/drivers/spi/nxp_fspi.c
+++ b/drivers/spi/nxp_fspi.c
@@ -823,7 +823,7 @@
/* the default frequency, we will change it later if necessary. */
ret = clk_set_rate(&f->clk, 20000000);
- if (ret)
+ if (ret < 0)
return ret;
ret = nxp_fspi_clk_prep_enable(f);
@@ -914,7 +914,7 @@
nxp_fspi_clk_disable_unprep(f);
ret = clk_set_rate(&f->clk, speed);
- if (ret)
+ if (ret < 0)
return ret;
ret = nxp_fspi_clk_prep_enable(f);
diff --git a/drivers/spi/stm32_qspi.c b/drivers/spi/stm32_qspi.c
index 75e5e84..4acc904 100644
--- a/drivers/spi/stm32_qspi.c
+++ b/drivers/spi/stm32_qspi.c
@@ -16,6 +16,7 @@
#include <reset.h>
#include <spi.h>
#include <spi-mem.h>
+#include <watchdog.h>
#include <dm/device_compat.h>
#include <linux/bitops.h>
#include <linux/delay.h>
@@ -171,6 +172,7 @@
static void _stm32_qspi_read_fifo(u8 *val, void __iomem *addr)
{
*val = readb(addr);
+ WATCHDOG_RESET();
}
static void _stm32_qspi_write_fifo(u8 *val, void __iomem *addr)
diff --git a/drivers/spi/zynq_qspi.c b/drivers/spi/zynq_qspi.c
index 3d829bc..cf6da53 100644
--- a/drivers/spi/zynq_qspi.c
+++ b/drivers/spi/zynq_qspi.c
@@ -194,7 +194,7 @@
}
ret = clk_enable(&clk);
- if (ret && ret != -ENOSYS) {
+ if (ret) {
dev_err(bus, "failed to enable clock\n");
return ret;
}
diff --git a/drivers/spi/zynq_spi.c b/drivers/spi/zynq_spi.c
index 52b8fbc..b3e0858 100644
--- a/drivers/spi/zynq_spi.c
+++ b/drivers/spi/zynq_spi.c
@@ -144,7 +144,7 @@
}
ret = clk_enable(&clk);
- if (ret && ret != -ENOSYS) {
+ if (ret) {
dev_err(bus, "failed to enable clock\n");
return ret;
}
diff --git a/drivers/spi/zynqmp_gqspi.c b/drivers/spi/zynqmp_gqspi.c
index f669974..f8d13d1 100644
--- a/drivers/spi/zynqmp_gqspi.c
+++ b/drivers/spi/zynqmp_gqspi.c
@@ -17,6 +17,7 @@
#include <malloc.h>
#include <memalign.h>
#include <spi.h>
+#include <spi-mem.h>
#include <ubi_uboot.h>
#include <wait_bit.h>
#include <dm/device_compat.h>
@@ -172,8 +173,7 @@
unsigned int len;
int bytes_to_transfer;
int bytes_to_receive;
- unsigned int is_inst;
- unsigned int cs_change:1;
+ const struct spi_mem_op *op;
};
static int zynqmp_qspi_of_to_plat(struct udevice *bus)
@@ -222,6 +222,21 @@
return gqspi_fifo_reg;
}
+static u32 zynqmp_qspi_genfifo_mode(u8 buswidth)
+{
+ switch (buswidth) {
+ case 1:
+ return GQSPI_SPI_MODE_SPI;
+ case 2:
+ return GQSPI_SPI_MODE_DUAL_SPI;
+ case 4:
+ return GQSPI_SPI_MODE_QSPI;
+ default:
+ debug("Unsupported bus width %u\n", buswidth);
+ return GQSPI_SPI_MODE_SPI;
+ }
+}
+
static void zynqmp_qspi_fill_gen_fifo(struct zynqmp_qspi_priv *priv,
u32 gqspi_fifo_reg)
{
@@ -306,12 +321,9 @@
if (speed > plat->frequency)
speed = plat->frequency;
- /* Set the clock frequency */
- confr = readl(®s->confr);
- if (speed == 0) {
- /* Set baudrate x8, if the freq is 0 */
- baud_rate_val = GQSPI_DFLT_BAUD_RATE_VAL;
- } else if (plat->speed_hz != speed) {
+ if (plat->speed_hz != speed) {
+ /* Set the clock frequency */
+ /* If speed == 0, default to lowest speed */
while ((baud_rate_val < 8) &&
((plat->frequency /
(2 << baud_rate_val)) > speed))
@@ -321,13 +333,15 @@
baud_rate_val = GQSPI_DFLT_BAUD_RATE_VAL;
plat->speed_hz = plat->frequency / (2 << baud_rate_val);
- }
- confr &= ~GQSPI_BAUD_DIV_MASK;
- confr |= (baud_rate_val << 3);
- writel(confr, ®s->confr);
- zynqmp_qspi_set_tapdelay(bus, baud_rate_val);
- debug("regs=%p, speed=%d\n", priv->regs, plat->speed_hz);
+ confr = readl(®s->confr);
+ confr &= ~GQSPI_BAUD_DIV_MASK;
+ confr |= (baud_rate_val << 3);
+ writel(confr, ®s->confr);
+ zynqmp_qspi_set_tapdelay(bus, baud_rate_val);
+
+ debug("regs=%p, speed=%d\n", priv->regs, plat->speed_hz);
+ }
return 0;
}
@@ -359,7 +373,7 @@
debug("%s: CLK %ld\n", __func__, clock);
ret = clk_enable(&clk);
- if (ret && ret != -ENOSYS) {
+ if (ret) {
dev_err(bus, "failed to enable clock\n");
return ret;
}
@@ -446,21 +460,42 @@
static void zynqmp_qspi_genfifo_cmd(struct zynqmp_qspi_priv *priv)
{
+ const struct spi_mem_op *op = priv->op;
u32 gen_fifo_cmd;
- u32 bytecount = 0;
+ u8 i, dummy_cycles, addr;
- while (priv->len) {
+ /* Send opcode */
+ gen_fifo_cmd = zynqmp_qspi_bus_select(priv);
+ gen_fifo_cmd |= zynqmp_qspi_genfifo_mode(op->cmd.buswidth);
+ gen_fifo_cmd |= GQSPI_GFIFO_TX;
+ gen_fifo_cmd |= op->cmd.opcode;
+ zynqmp_qspi_fill_gen_fifo(priv, gen_fifo_cmd);
+
+ /* Send address */
+ for (i = 0; i < op->addr.nbytes; i++) {
+ addr = op->addr.val >> (8 * (op->addr.nbytes - i - 1));
+
gen_fifo_cmd = zynqmp_qspi_bus_select(priv);
- gen_fifo_cmd |= GQSPI_GFIFO_TX | GQSPI_SPI_MODE_SPI;
- gen_fifo_cmd |= *(u8 *)priv->tx_buf;
- bytecount++;
- priv->len--;
- priv->tx_buf = (u8 *)priv->tx_buf + 1;
+ gen_fifo_cmd |= zynqmp_qspi_genfifo_mode(op->addr.buswidth);
+ gen_fifo_cmd |= GQSPI_GFIFO_TX;
+ gen_fifo_cmd |= addr;
debug("GFIFO_CMD_Cmd = 0x%x\n", gen_fifo_cmd);
zynqmp_qspi_fill_gen_fifo(priv, gen_fifo_cmd);
}
+
+ /* Send dummy */
+ if (op->dummy.nbytes) {
+ dummy_cycles = op->dummy.nbytes * 8 / op->dummy.buswidth;
+
+ gen_fifo_cmd = zynqmp_qspi_bus_select(priv);
+ gen_fifo_cmd |= zynqmp_qspi_genfifo_mode(op->dummy.buswidth);
+ gen_fifo_cmd &= ~(GQSPI_GFIFO_TX | GQSPI_GFIFO_RX);
+ gen_fifo_cmd |= GQSPI_GFIFO_DATA_XFR_MASK;
+ gen_fifo_cmd |= dummy_cycles;
+ zynqmp_qspi_fill_gen_fifo(priv, gen_fifo_cmd);
+ }
}
static u32 zynqmp_qspi_calc_exp(struct zynqmp_qspi_priv *priv,
@@ -497,11 +532,10 @@
int ret = 0;
gen_fifo_cmd = zynqmp_qspi_bus_select(priv);
+ gen_fifo_cmd |= zynqmp_qspi_genfifo_mode(priv->op->data.buswidth);
gen_fifo_cmd |= GQSPI_GFIFO_TX |
GQSPI_GFIFO_DATA_XFR_MASK;
- gen_fifo_cmd |= GQSPI_SPI_MODE_SPI;
-
while (priv->len) {
len = zynqmp_qspi_calc_exp(priv, &gen_fifo_cmd);
zynqmp_qspi_fill_gen_fifo(priv, gen_fifo_cmd);
@@ -575,11 +609,10 @@
u32 actuallen = priv->len;
gen_fifo_cmd = zynqmp_qspi_bus_select(priv);
+ gen_fifo_cmd |= zynqmp_qspi_genfifo_mode(priv->op->data.buswidth);
gen_fifo_cmd |= GQSPI_GFIFO_RX |
GQSPI_GFIFO_DATA_XFR_MASK;
- gen_fifo_cmd |= GQSPI_SPI_MODE_SPI;
-
/*
* Check if receive buffer is aligned to 4 byte and length
* is multiples of four byte as we are using dma to receive.
@@ -596,62 +629,6 @@
return zynqmp_qspi_start_dma(priv, gen_fifo_cmd, buf);
}
-static int zynqmp_qspi_start_transfer(struct zynqmp_qspi_priv *priv)
-{
- int ret = 0;
-
- if (priv->is_inst) {
- if (priv->tx_buf)
- zynqmp_qspi_genfifo_cmd(priv);
- else
- return -EINVAL;
- } else {
- if (priv->tx_buf)
- ret = zynqmp_qspi_genfifo_fill_tx(priv);
- else if (priv->rx_buf)
- ret = zynqmp_qspi_genfifo_fill_rx(priv);
- else
- return -EINVAL;
- }
- return ret;
-}
-
-static int zynqmp_qspi_transfer(struct zynqmp_qspi_priv *priv)
-{
- static unsigned int cs_change = 1;
- int status = 0;
-
- debug("%s\n", __func__);
-
- while (1) {
- /* Select the chip if required */
- if (cs_change)
- zynqmp_qspi_chipselect(priv, 1);
-
- cs_change = priv->cs_change;
-
- if (!priv->tx_buf && !priv->rx_buf && priv->len) {
- status = -EINVAL;
- break;
- }
-
- /* Request the transfer */
- if (priv->len) {
- status = zynqmp_qspi_start_transfer(priv);
- priv->is_inst = 0;
- if (status < 0)
- break;
- }
-
- if (cs_change)
- /* Deselect the chip */
- zynqmp_qspi_chipselect(priv, 0);
- break;
- }
-
- return status;
-}
-
static int zynqmp_qspi_claim_bus(struct udevice *dev)
{
struct udevice *bus = dev->parent;
@@ -674,45 +651,43 @@
return 0;
}
-int zynqmp_qspi_xfer(struct udevice *dev, unsigned int bitlen, const void *dout,
- void *din, unsigned long flags)
+static int zynqmp_qspi_exec_op(struct spi_slave *slave,
+ const struct spi_mem_op *op)
{
- struct udevice *bus = dev->parent;
- struct zynqmp_qspi_priv *priv = dev_get_priv(bus);
+ struct zynqmp_qspi_priv *priv = dev_get_priv(slave->dev->parent);
+ int ret = 0;
- debug("%s: priv: 0x%08lx bitlen: %d dout: 0x%08lx ", __func__,
- (unsigned long)priv, bitlen, (unsigned long)dout);
- debug("din: 0x%08lx flags: 0x%lx\n", (unsigned long)din, flags);
+ priv->op = op;
+ priv->tx_buf = op->data.buf.out;
+ priv->rx_buf = op->data.buf.in;
+ priv->len = op->data.nbytes;
- priv->tx_buf = dout;
- priv->rx_buf = din;
- priv->len = bitlen / 8;
+ zynqmp_qspi_chipselect(priv, 1);
- /*
- * Assume that the beginning of a transfer with bits to
- * transmit must contain a device command.
- */
- if (dout && flags & SPI_XFER_BEGIN)
- priv->is_inst = 1;
- else
- priv->is_inst = 0;
+ /* Send opcode, addr, dummy */
+ zynqmp_qspi_genfifo_cmd(priv);
- if (flags & SPI_XFER_END)
- priv->cs_change = 1;
- else
- priv->cs_change = 0;
+ /* Request the transfer */
+ if (op->data.dir == SPI_MEM_DATA_IN)
+ ret = zynqmp_qspi_genfifo_fill_rx(priv);
+ else if (op->data.dir == SPI_MEM_DATA_OUT)
+ ret = zynqmp_qspi_genfifo_fill_tx(priv);
- zynqmp_qspi_transfer(priv);
+ zynqmp_qspi_chipselect(priv, 0);
- return 0;
+ return ret;
}
+static const struct spi_controller_mem_ops zynqmp_qspi_mem_ops = {
+ .exec_op = zynqmp_qspi_exec_op,
+};
+
static const struct dm_spi_ops zynqmp_qspi_ops = {
.claim_bus = zynqmp_qspi_claim_bus,
.release_bus = zynqmp_qspi_release_bus,
- .xfer = zynqmp_qspi_xfer,
.set_speed = zynqmp_qspi_set_speed,
.set_mode = zynqmp_qspi_set_mode,
+ .mem_ops = &zynqmp_qspi_mem_ops,
};
static const struct udevice_id zynqmp_qspi_ids[] = {
diff --git a/drivers/sysreset/Kconfig b/drivers/sysreset/Kconfig
index 0e5c7c9..ac77ffb 100644
--- a/drivers/sysreset/Kconfig
+++ b/drivers/sysreset/Kconfig
@@ -33,6 +33,12 @@
if SYSRESET
+config SYSRESET_CMD_RESET
+ bool "sysreset implementation of the reset command"
+ default y
+ help
+ Enable sysreset implementation of the reset command.
+
if CMD_POWEROFF
config SYSRESET_CMD_POWEROFF
@@ -88,7 +94,7 @@
config SYSRESET_SOCFPGA_SOC64
bool "Enable support for Intel SOCFPGA SoC64 family (Stratix10/Agilex)"
- depends on ARCH_SOCFPGA && (TARGET_SOCFPGA_STRATIX10 || TARGET_SOCFPGA_AGILEX)
+ depends on ARCH_SOCFPGA && TARGET_SOCFPGA_SOC64
help
This enables the system reset driver support for Intel SOCFPGA
SoC64 SoCs.
diff --git a/drivers/sysreset/sysreset-uclass.c b/drivers/sysreset/sysreset-uclass.c
index a9908eb..6c9dc7a 100644
--- a/drivers/sysreset/sysreset-uclass.c
+++ b/drivers/sysreset/sysreset-uclass.c
@@ -119,6 +119,7 @@
}
+#if IS_ENABLED(CONFIG_SYSRESET_CMD_RESET)
int do_reset(struct cmd_tbl *cmdtp, int flag, int argc, char *const argv[])
{
printf("resetting ...\n");
@@ -128,6 +129,7 @@
return 0;
}
+#endif
#if IS_ENABLED(CONFIG_SYSRESET_CMD_POWEROFF)
int do_poweroff(struct cmd_tbl *cmdtp, int flag, int argc, char *const argv[])
diff --git a/drivers/thermal/imx_tmu.c b/drivers/thermal/imx_tmu.c
index 02cefec..07766ba 100644
--- a/drivers/thermal/imx_tmu.c
+++ b/drivers/thermal/imx_tmu.c
@@ -344,6 +344,7 @@
ofnode node, offset;
const char *name;
const void *prop;
+ int minc, maxc;
debug("%s dev name %s\n", __func__, dev->name);
@@ -352,6 +353,10 @@
return 0;
pdata->zone_node = 1;
+ /* default alert/crit temps based on temp grade */
+ get_cpu_temp_grade(&minc, &maxc);
+ pdata->critical = maxc * 1000;
+ pdata->alert = (maxc - 10) * 1000;
node = ofnode_path("/thermal-zones");
ofnode_for_each_subnode(offset, node) {
@@ -443,6 +448,7 @@
if (pdata->zone_node) {
imx_tmu_init(dev);
imx_tmu_calibration(dev);
+ imx_tmu_enable_msite(dev);
} else {
imx_tmu_enable_msite(dev);
}
diff --git a/drivers/usb/Kconfig b/drivers/usb/Kconfig
index 6e29119..f697573 100644
--- a/drivers/usb/Kconfig
+++ b/drivers/usb/Kconfig
@@ -95,6 +95,7 @@
config USB_KEYBOARD
bool "USB Keyboard support"
+ select DM_KEYBOARD if DM_USB
select SYS_STDIO_DEREGISTER
---help---
Say Y here if you want to use a USB keyboard for U-Boot command line
diff --git a/drivers/usb/gadget/dwc2_udc_otg.c b/drivers/usb/gadget/dwc2_udc_otg.c
index ecac80f..2f31814 100644
--- a/drivers/usb/gadget/dwc2_udc_otg.c
+++ b/drivers/usb/gadget/dwc2_udc_otg.c
@@ -248,9 +248,7 @@
debug_cond(DEBUG_SETUP != 0, "%s: %s\n", __func__, "no name");
- if (!driver
- || (driver->speed != USB_SPEED_FULL
- && driver->speed != USB_SPEED_HIGH)
+ if (!driver || driver->speed < USB_SPEED_FULL
|| !driver->bind || !driver->disconnect || !driver->setup)
return -EINVAL;
if (!dev)
@@ -320,9 +318,7 @@
debug_cond(DEBUG_SETUP != 0, "%s: %s\n", __func__, "no name");
- if (!driver ||
- (driver->speed != USB_SPEED_FULL &&
- driver->speed != USB_SPEED_HIGH) ||
+ if (!driver || driver->speed < USB_SPEED_FULL ||
!driver->bind || !driver->disconnect || !driver->setup)
return -EINVAL;
diff --git a/drivers/usb/gadget/ep0.c b/drivers/usb/gadget/ep0.c
index 457679f..6624f61 100644
--- a/drivers/usb/gadget/ep0.c
+++ b/drivers/usb/gadget/ep0.c
@@ -294,7 +294,7 @@
{
struct usb_string_descriptor *string_descriptor;
if (!(string_descriptor = usbd_get_string (index))) {
- serial_printf("Invalid string index %d\n", index);
+ dbg_ep0(0, "Invalid string index %d\n", index);
return -1;
}
dbg_ep0(3, "string_descriptor: %p length %d", string_descriptor, string_descriptor->bLength);
@@ -302,14 +302,14 @@
}
break;
case USB_DESCRIPTOR_TYPE_INTERFACE:
- serial_printf("USB_DESCRIPTOR_TYPE_INTERFACE - error not implemented\n");
+ dbg_ep0(2, "USB_DESCRIPTOR_TYPE_INTERFACE - error not implemented\n");
return -1;
case USB_DESCRIPTOR_TYPE_ENDPOINT:
- serial_printf("USB_DESCRIPTOR_TYPE_ENDPOINT - error not implemented\n");
+ dbg_ep0(2, "USB_DESCRIPTOR_TYPE_ENDPOINT - error not implemented\n");
return -1;
case USB_DESCRIPTOR_TYPE_HID:
{
- serial_printf("USB_DESCRIPTOR_TYPE_HID - error not implemented\n");
+ dbg_ep0(2, "USB_DESCRIPTOR_TYPE_HID - error not implemented\n");
return -1; /* unsupported at this time */
#if 0
int bNumInterface =
@@ -338,7 +338,7 @@
break;
case USB_DESCRIPTOR_TYPE_REPORT:
{
- serial_printf("USB_DESCRIPTOR_TYPE_REPORT - error not implemented\n");
+ dbg_ep0(2, "USB_DESCRIPTOR_TYPE_REPORT - error not implemented\n");
return -1; /* unsupported at this time */
#if 0
int bNumInterface =
@@ -531,7 +531,7 @@
le16_to_cpu (request->wValue) & 0xff);
case USB_REQ_GET_CONFIGURATION:
- serial_printf("get config %d\n", device->configuration);
+ dbg_ep0(2, "get config %d\n", device->configuration);
return ep0_get_one (device, urb,
device->configuration);
@@ -621,14 +621,14 @@
device->interface = device->alternate = 0;
/*dbg_ep0(2, "set configuration: %d", device->configuration); */
- /*serial_printf("DEVICE_CONFIGURED.. event?\n"); */
+ /*dbg_ep0(2, "DEVICE_CONFIGURED.. event?\n"); */
return 0;
case USB_REQ_SET_INTERFACE:
device->interface = le16_to_cpu (request->wIndex);
device->alternate = le16_to_cpu (request->wValue);
/*dbg_ep0(2, "set interface: %d alternate: %d", device->interface, device->alternate); */
- serial_printf("DEVICE_SET_INTERFACE.. event?\n");
+ dbg_ep0(2, "DEVICE_SET_INTERFACE.. event?\n");
return 0;
case USB_REQ_GET_STATUS:
diff --git a/drivers/usb/gadget/f_fastboot.c b/drivers/usb/gadget/f_fastboot.c
index 950cc11..8ba55aa 100644
--- a/drivers/usb/gadget/f_fastboot.c
+++ b/drivers/usb/gadget/f_fastboot.c
@@ -494,6 +494,18 @@
do_exit_on_complete(ep, req);
}
+#if CONFIG_IS_ENABLED(FASTBOOT_UUU_SUPPORT)
+static void do_acmd_complete(struct usb_ep *ep, struct usb_request *req)
+{
+ /* When usb dequeue complete will be called
+ * Need status value before call run_command.
+ * otherwise, host can't get last message.
+ */
+ if (req->status == 0)
+ fastboot_acmd_complete();
+}
+#endif
+
static void rx_handler_command(struct usb_ep *ep, struct usb_request *req)
{
char *cmdbuf = req->buf;
@@ -532,6 +544,11 @@
case FASTBOOT_COMMAND_REBOOT_RECOVERY:
fastboot_func->in_req->complete = compl_do_reset;
break;
+#if CONFIG_IS_ENABLED(FASTBOOT_UUU_SUPPORT)
+ case FASTBOOT_COMMAND_ACMD:
+ fastboot_func->in_req->complete = do_acmd_complete;
+ break;
+#endif
}
}
diff --git a/drivers/usb/mtu3/mtu3_qmu.c b/drivers/usb/mtu3/mtu3_qmu.c
index 801c2bc..95eaf6d 100644
--- a/drivers/usb/mtu3/mtu3_qmu.c
+++ b/drivers/usb/mtu3/mtu3_qmu.c
@@ -198,6 +198,7 @@
enq->flag &= ~GPD_FLAGS_HWO;
gpd->next_gpd = cpu_to_le32((u32)gpd_virt_to_dma(ring, enq));
+ mtu3_flush_cache((uintptr_t)enq, sizeof(*gpd));
if (req->zero)
gpd->ext_flag |= GPD_EXT_FLAG_ZLP;
@@ -234,6 +235,8 @@
enq->flag &= ~GPD_FLAGS_HWO;
gpd->next_gpd = cpu_to_le32((u32)gpd_virt_to_dma(ring, enq));
+ mtu3_flush_cache((uintptr_t)enq, sizeof(*gpd));
+
gpd->flag |= GPD_FLAGS_IOC | GPD_FLAGS_HWO;
mreq->gpd = gpd;
diff --git a/drivers/usb/musb/musb_core.c b/drivers/usb/musb/musb_core.c
index 147b2eb..9651f07 100644
--- a/drivers/usb/musb/musb_core.c
+++ b/drivers/usb/musb/musb_core.c
@@ -50,7 +50,7 @@
# define config_fifo(dir, idx, addr) \
do { \
writeb(idx, &musbr->dir##fifosz); \
- writew(fifoaddr >> 3, &musbr->dir##fifoadd); \
+ writew(addr, &musbr->dir##fifoadd); \
} while (0)
#endif
@@ -66,14 +66,14 @@
void musb_configure_ep(const struct musb_epinfo *epinfo, u8 cnt)
{
u16 csr;
- u16 fifoaddr = 64; /* First 64 bytes of FIFO reserved for EP0 */
+ u16 fifoaddr = 64 >> 3; /* First 64 bytes of FIFO reserved for EP0 */
u32 fifosize;
u8 idx;
while (cnt--) {
/* prepare fifosize to write to register */
fifosize = epinfo->epsize >> 3;
- idx = ffs(fifosize) - 1;
+ idx = fifosize ? ((ffs(fifosize) - 1) & 0xF) : 0;
writeb(epinfo->epnum, &musbr->index);
if (epinfo->epdir) {
@@ -81,10 +81,8 @@
config_fifo(tx, idx, fifoaddr);
csr = readw(&musbr->txcsr);
-#if defined(CONFIG_USB_MUSB_HCD)
/* clear the data toggle bit */
writew(csr | MUSB_TXCSR_CLRDATATOG, &musbr->txcsr);
-#endif
/* Flush fifo if required */
if (csr & MUSB_TXCSR_TXPKTRDY)
writew(csr | MUSB_TXCSR_FLUSHFIFO,
@@ -94,16 +92,14 @@
config_fifo(rx, idx, fifoaddr);
csr = readw(&musbr->rxcsr);
-#if defined(CONFIG_USB_MUSB_HCD)
/* clear the data toggle bit */
writew(csr | MUSB_RXCSR_CLRDATATOG, &musbr->rxcsr);
-#endif
/* Flush fifo if required */
if (csr & MUSB_RXCSR_RXPKTRDY)
writew(csr | MUSB_RXCSR_FLUSHFIFO,
&musbr->rxcsr);
}
- fifoaddr += epinfo->epsize;
+ fifoaddr += 1 << idx;
epinfo++;
}
}
diff --git a/drivers/usb/musb/musb_udc.c b/drivers/usb/musb/musb_udc.c
index d901f87..b9510e3 100644
--- a/drivers/usb/musb/musb_udc.c
+++ b/drivers/usb/musb/musb_udc.c
@@ -104,6 +104,8 @@
static struct usb_device_instance *udc_device;
static int enabled;
+static u16 pending_intrrx;
+
#ifdef MUSB_DEBUG
static void musb_db_regs(void)
{
@@ -629,7 +631,7 @@
static void musb_peri_rx_ep(unsigned int ep)
{
u16 peri_rxcount;
- u8 peri_rxcsr = readw(&musbr->ep[ep].epN.rxcsr);
+ u16 peri_rxcsr = readw(&musbr->ep[ep].epN.rxcsr);
if (!(peri_rxcsr & MUSB_RXCSR_RXPKTRDY)) {
if (debug_level > 0)
@@ -664,7 +666,10 @@
/* The common musb fifo reader */
read_fifo(ep, length, data);
- musb_peri_rx_ack(ep);
+ if (length == peri_rxcount)
+ musb_peri_rx_ack(ep);
+ else
+ pending_intrrx |= (1 << ep);
/*
* urb's actual_length is updated in
@@ -677,18 +682,24 @@
serial_printf("ERROR : %s %d no space "
"in rcv buffer\n",
__PRETTY_FUNCTION__, ep);
+
+ pending_intrrx |= (1 << ep);
}
} else {
if (debug_level > 0)
serial_printf("ERROR : %s %d problem with "
"endpoint\n",
__PRETTY_FUNCTION__, ep);
+
+ pending_intrrx |= (1 << ep);
}
} else {
if (debug_level > 0)
serial_printf("ERROR : %s %d with nothing to do\n",
__PRETTY_FUNCTION__, ep);
+
+ musb_peri_rx_ack(ep);
}
}
@@ -696,9 +707,7 @@
{
unsigned int ep;
- /* Check for EP0 */
- if (0x01 & intr)
- musb_peri_ep0();
+ /* First bit is reserved and does not indicate interrupt for EP0 */
for (ep = 1; ep < 16; ep++) {
if ((1 << ep) & intr)
@@ -708,21 +717,16 @@
static void musb_peri_tx(u16 intr)
{
- /* Check for EP0 */
+ unsigned int ep;
+
+ /* Check for EP0: first bit indicates interrupt for both RX and TX */
if (0x01 & intr)
- musb_peri_ep0_tx();
+ musb_peri_ep0();
- /*
- * Use this in the future when handling epN tx
- *
- * u8 ep;
- *
- * for (ep = 1; ep < 16; ep++) {
- * if ((1 << ep) & intr) {
- * / * handle tx for this endpoint * /
- * }
- * }
- */
+ for (ep = 1; ep < 16; ep++) {
+ if ((1 << ep) & intr)
+ udc_endpoint_write(GET_ENDPOINT(udc_device, ep));
+ }
}
void udc_irq(void)
@@ -744,8 +748,6 @@
musb_peri_resume();
}
- musb_peri_ep0();
-
if (MUSB_INTR_RESET & intrusb) {
usbd_device_event_irq(udc_device, DEVICE_RESET, 0);
musb_peri_reset();
@@ -775,13 +777,16 @@
intrrx = readw(&musbr->intrrx);
intrtx = readw(&musbr->intrtx);
+ intrrx |= pending_intrrx;
+ pending_intrrx = 0;
+
if (intrrx)
musb_peri_rx(intrrx);
if (intrtx)
musb_peri_tx(intrtx);
} else {
- if (MUSB_INTR_SOF & intrusb) {
+ if (readw(&musbr->intrtx) & 0x1) {
u8 faddr;
faddr = readb(&musbr->faddr);
/*
@@ -870,18 +875,8 @@
ep0_endpoint->endpoint_address = 0xff;
ep0_urb = usbd_alloc_urb(device, endpoint);
} else if (MAX_ENDPOINT >= id) {
- int ep_addr;
-
- /* Check the direction */
- ep_addr = endpoint->endpoint_address;
- if (USB_DIR_IN == (ep_addr & USB_ENDPOINT_DIR_MASK)) {
- /* IN */
- epinfo[(id * 2) + 1].epsize = endpoint->tx_packetSize;
- } else {
- /* OUT */
- epinfo[id * 2].epsize = endpoint->rcv_packetSize;
- }
-
+ epinfo[(id * 2) + 0].epsize = endpoint->rcv_packetSize;
+ epinfo[(id * 2) + 1].epsize = endpoint->tx_packetSize;
musb_configure_ep(&epinfo[0], ARRAY_SIZE(epinfo));
} else {
if (debug_level > 0)
diff --git a/drivers/video/dw_mipi_dsi.c b/drivers/video/dw_mipi_dsi.c
index 4dde648..9ae09ee 100644
--- a/drivers/video/dw_mipi_dsi.c
+++ b/drivers/video/dw_mipi_dsi.c
@@ -721,15 +721,15 @@
ret = readl_poll_timeout(dsi->base + DSI_PHY_STATUS, val,
val & PHY_LOCK, PHY_STATUS_TIMEOUT_US);
if (ret)
- dev_warn(dsi->dsi_host.dev,
- "failed to wait phy lock state\n");
+ dev_dbg(dsi->dsi_host.dev,
+ "failed to wait phy lock state\n");
ret = readl_poll_timeout(dsi->base + DSI_PHY_STATUS,
val, val & PHY_STOP_STATE_CLK_LANE,
PHY_STATUS_TIMEOUT_US);
if (ret)
- dev_warn(dsi->dsi_host.dev,
- "failed to wait phy clk lane stop state\n");
+ dev_dbg(dsi->dsi_host.dev,
+ "failed to wait phy clk lane stop state\n");
}
static void dw_mipi_dsi_clear_err(struct dw_mipi_dsi *dsi)
@@ -797,6 +797,7 @@
dsi->phy_ops = phy_ops;
dsi->max_data_lanes = max_data_lanes;
dsi->device = device;
+ dsi->dsi_host.dev = (struct device *)dev;
dsi->dsi_host.ops = &dw_mipi_dsi_host_ops;
device->host = &dsi->dsi_host;
diff --git a/drivers/video/stm32/stm32_dsi.c b/drivers/video/stm32/stm32_dsi.c
index 8891ca4..4027e97 100644
--- a/drivers/video/stm32/stm32_dsi.c
+++ b/drivers/video/stm32/stm32_dsi.c
@@ -483,6 +483,9 @@
if (priv->hw_version != HWVER_130 &&
priv->hw_version != HWVER_131) {
dev_err(dev, "DSI version 0x%x not supported\n", priv->hw_version);
+ dev_dbg(dev, "remove and unbind all DSI child\n");
+ device_chld_remove(dev, NULL, DM_REMOVE_NORMAL);
+ device_chld_unbind(dev, NULL);
ret = -ENODEV;
goto err_clk;
}
diff --git a/drivers/virtio/Kconfig b/drivers/virtio/Kconfig
index e800720..1835607 100644
--- a/drivers/virtio/Kconfig
+++ b/drivers/virtio/Kconfig
@@ -55,6 +55,7 @@
config VIRTIO_BLK
bool "virtio block driver"
depends on VIRTIO
+ depends on BLK
help
This is the virtual block driver for virtio. It can be used with
QEMU based targets.
diff --git a/drivers/virtio/virtio-uclass.c b/drivers/virtio/virtio-uclass.c
index cf2cfae..0379536 100644
--- a/drivers/virtio/virtio-uclass.c
+++ b/drivers/virtio/virtio-uclass.c
@@ -227,7 +227,7 @@
struct udevice *vdev;
int ret;
- if (uc_priv->device > VIRTIO_ID_MAX_NUM) {
+ if (uc_priv->device >= VIRTIO_ID_MAX_NUM) {
debug("(%s): virtio device ID %d exceeds maximum num\n",
udev->name, uc_priv->device);
return 0;
diff --git a/drivers/watchdog/xilinx_wwdt.c b/drivers/watchdog/xilinx_wwdt.c
index 9137d87..11b30ae 100644
--- a/drivers/watchdog/xilinx_wwdt.c
+++ b/drivers/watchdog/xilinx_wwdt.c
@@ -90,9 +90,8 @@
/* Calculate timeout count */
count = timeout * clock_f;
- /* clk_enable will return -ENOSYS when it is not implemented */
ret = clk_enable(&wdt->clk);
- if (ret && ret != -ENOSYS) {
+ if (ret) {
dev_err(dev, "failed to enable clock\n");
return ret;
}
diff --git a/dts/Kconfig b/dts/Kconfig
index 71f5055..00ac29a 100644
--- a/dts/Kconfig
+++ b/dts/Kconfig
@@ -60,7 +60,7 @@
config OF_LIVE
bool "Enable use of a live tree"
- depends on OF_CONTROL
+ depends on DM && OF_CONTROL
help
Normally U-Boot uses a flat device tree which saves space and
avoids the need to unpack the tree before use. However a flat
diff --git a/fs/btrfs/btrfs.c b/fs/btrfs/btrfs.c
index 346b2c4..52a243a 100644
--- a/fs/btrfs/btrfs.c
+++ b/fs/btrfs/btrfs.c
@@ -22,14 +22,13 @@
struct btrfs_inode_item ii;
struct btrfs_key key;
static const char* dir_item_str[] = {
- [BTRFS_FT_REG_FILE] = "FILE",
+ [BTRFS_FT_REG_FILE] = " ",
[BTRFS_FT_DIR] = "DIR",
- [BTRFS_FT_CHRDEV] = "CHRDEV",
- [BTRFS_FT_BLKDEV] = "BLKDEV",
- [BTRFS_FT_FIFO] = "FIFO",
- [BTRFS_FT_SOCK] = "SOCK",
- [BTRFS_FT_SYMLINK] = "SYMLINK",
- [BTRFS_FT_XATTR] = "XATTR"
+ [BTRFS_FT_CHRDEV] = "CHR",
+ [BTRFS_FT_BLKDEV] = "BLK",
+ [BTRFS_FT_FIFO] = "FIF",
+ [BTRFS_FT_SOCK] = "SCK",
+ [BTRFS_FT_SYMLINK] = "SYM",
};
u8 type = btrfs_dir_type(eb, di);
char namebuf[BTRFS_NAME_LEN];
@@ -38,6 +37,10 @@
time_t mtime;
int ret = 0;
+ /* skip XATTRs in directory listing */
+ if (type == BTRFS_FT_XATTR)
+ return 0;
+
btrfs_dir_item_key_to_cpu(eb, di, &key);
if (key.type == BTRFS_ROOT_ITEM_KEY) {
@@ -90,7 +93,7 @@
if (type < ARRAY_SIZE(dir_item_str) && dir_item_str[type])
printf("<%s> ", dir_item_str[type]);
else
- printf("DIR_ITEM.%u", type);
+ printf("?%3u? ", type);
if (type == BTRFS_FT_CHRDEV || type == BTRFS_FT_BLKDEV) {
ASSERT(key.type == BTRFS_INODE_ITEM_KEY);
printf("%4llu,%5llu ", btrfs_stack_inode_rdev(&ii) >> 20,
diff --git a/fs/btrfs/disk-io.c b/fs/btrfs/disk-io.c
index b332ecb..c6fdec9 100644
--- a/fs/btrfs/disk-io.c
+++ b/fs/btrfs/disk-io.c
@@ -732,8 +732,7 @@
return fs_info->chunk_root;
if (location->objectid == BTRFS_CSUM_TREE_OBJECTID)
return fs_info->csum_root;
- BUG_ON(location->objectid == BTRFS_TREE_RELOC_OBJECTID ||
- location->offset != (u64)-1);
+ BUG_ON(location->objectid == BTRFS_TREE_RELOC_OBJECTID);
node = rb_search(&fs_info->fs_root_tree, (void *)&objectid,
btrfs_fs_roots_compare_objectids, NULL);
diff --git a/fs/squashfs/sqfs.c b/fs/squashfs/sqfs.c
index dca13bd..29805c3 100644
--- a/fs/squashfs/sqfs.c
+++ b/fs/squashfs/sqfs.c
@@ -1716,6 +1716,9 @@
{
struct squashfs_dir_stream *sqfs_dirs;
+ if (!dirs)
+ return;
+
sqfs_dirs = (struct squashfs_dir_stream *)dirs;
free(sqfs_dirs->inode_table);
free(sqfs_dirs->dir_table);
diff --git a/fs/squashfs/sqfs_inode.c b/fs/squashfs/sqfs_inode.c
index e76ec7c..d25cfb5 100644
--- a/fs/squashfs/sqfs_inode.c
+++ b/fs/squashfs/sqfs_inode.c
@@ -6,6 +6,7 @@
*/
#include <asm/unaligned.h>
+#include <compiler.h>
#include <errno.h>
#include <stdint.h>
#include <stdio.h>
diff --git a/include/addr_map.h b/include/addr_map.h
index d322dd2..55d3a6a 100644
--- a/include/addr_map.h
+++ b/include/addr_map.h
@@ -8,9 +8,17 @@
#include <asm/types.h>
-extern phys_addr_t addrmap_virt_to_phys(void *vaddr);
-extern void *addrmap_phys_to_virt(phys_addr_t paddr);
-extern void addrmap_set_entry(unsigned long vaddr, phys_addr_t paddr,
- phys_size_t size, int idx);
+struct addrmap {
+ phys_addr_t paddr;
+ phys_size_t size;
+ unsigned long vaddr;
+};
+
+extern struct addrmap address_map[CONFIG_SYS_NUM_ADDR_MAP];
+
+phys_addr_t addrmap_virt_to_phys(void *vaddr);
+void *addrmap_phys_to_virt(phys_addr_t paddr);
+void addrmap_set_entry(unsigned long vaddr, phys_addr_t paddr,
+ phys_size_t size, int idx);
#endif
diff --git a/include/button.h b/include/button.h
index 688b63b..ee14fad 100644
--- a/include/button.h
+++ b/include/button.h
@@ -6,6 +6,8 @@
#ifndef __BUTTON_H
#define __BUTTON_H
+struct udevice;
+
/**
* struct button_uc_plat - Platform data the uclass stores about each device
*
diff --git a/include/charset.h b/include/charset.h
index cc650a2..a911160 100644
--- a/include/charset.h
+++ b/include/charset.h
@@ -14,6 +14,11 @@
#define MAX_UTF8_PER_UTF16 3
/**
+ * codepage_437 - Unicode to codepage 437 translation table
+ */
+extern const u16 codepage_437[128];
+
+/**
* console_read_unicode() - read Unicode code point from console
*
* @code: pointer to store Unicode code point
@@ -270,4 +275,33 @@
*/
uint8_t *utf16_to_utf8(uint8_t *dest, const uint16_t *src, size_t size);
+/**
+ * utf_to_cp() - translate Unicode code point to 8bit codepage
+ *
+ * Codepoints that do not exist in the codepage are rendered as question mark.
+ *
+ * @c: pointer to Unicode code point to be translated
+ * @codepage: Unicode to codepage translation table
+ * Return: 0 on success, -ENOENT if codepoint cannot be translated
+ */
+int utf_to_cp(s32 *c, const u16 *codepage);
+
+/**
+ * utf8_to_cp437_stream() - convert UTF-8 stream to codepage 437
+ *
+ * @c: next UTF-8 character to convert
+ * @buffer: buffer, at least 5 characters
+ * Return: next codepage 437 character or 0
+ */
+int utf8_to_cp437_stream(u8 c, char *buffer);
+
+/**
+ * utf8_to_utf32_stream() - convert UTF-8 stream to UTF-32
+ *
+ * @c: next UTF-8 character to convert
+ * @buffer: buffer, at least 5 characters
+ * Return: next codepage 437 character or 0
+ */
+int utf8_to_utf32_stream(u8 c, char *buffer);
+
#endif /* __CHARSET_H_ */
diff --git a/include/configs/MPC8541CDS.h b/include/configs/MPC8541CDS.h
index b1c8917..ea4da6a 100644
--- a/include/configs/MPC8541CDS.h
+++ b/include/configs/MPC8541CDS.h
@@ -18,8 +18,6 @@
#define CONFIG_PCI_INDIRECT_BRIDGE
#define CONFIG_SYS_PCI_64BIT 1 /* enable 64-bit PCI resources */
-#define CONFIG_FSL_VIA
-
#ifndef __ASSEMBLY__
extern unsigned long get_clock_freq(void);
#endif
diff --git a/include/configs/MPC8548CDS.h b/include/configs/MPC8548CDS.h
index 0605f70..9f83931 100644
--- a/include/configs/MPC8548CDS.h
+++ b/include/configs/MPC8548CDS.h
@@ -23,8 +23,6 @@
#define CONFIG_INTERRUPTS /* enable pci, srio, ddr interrupts */
-#define CONFIG_FSL_VIA
-
#ifndef __ASSEMBLY__
#include <linux/stringify.h>
extern unsigned long get_clock_freq(void);
diff --git a/include/configs/MPC8555CDS.h b/include/configs/MPC8555CDS.h
index 88999ef..79e309c 100644
--- a/include/configs/MPC8555CDS.h
+++ b/include/configs/MPC8555CDS.h
@@ -18,8 +18,6 @@
#define CONFIG_PCI_INDIRECT_BRIDGE
#define CONFIG_SYS_PCI_64BIT 1 /* enable 64-bit PCI resources */
-#define CONFIG_FSL_VIA
-
#ifndef __ASSEMBLY__
extern unsigned long get_clock_freq(void);
#endif
diff --git a/include/configs/MPC8569MDS.h b/include/configs/MPC8569MDS.h
deleted file mode 100644
index f50f53e..0000000
--- a/include/configs/MPC8569MDS.h
+++ /dev/null
@@ -1,489 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0+ */
-/*
- * Copyright 2009-2011 Freescale Semiconductor, Inc.
- */
-
-/*
- * mpc8569mds board configuration file
- */
-#ifndef __CONFIG_H
-#define __CONFIG_H
-
-#define CONFIG_SYS_SRIO
-#define CONFIG_SRIO1 /* SRIO port 1 */
-
-#define CONFIG_PCIE1 1 /* PCIE controller */
-#define CONFIG_FSL_PCI_INIT 1 /* use common fsl pci init code */
-#define CONFIG_PCI_INDIRECT_BRIDGE 1 /* indirect PCI bridge support */
-#define CONFIG_SYS_PCI_64BIT 1 /* enable 64-bit PCI resources */
-
-#ifndef __ASSEMBLY__
-extern unsigned long get_clock_freq(void);
-#endif
-/* Replace a call to get_clock_freq (after it is implemented)*/
-#define CONFIG_SYS_CLK_FREQ 66666666
-#define CONFIG_DDR_CLK_FREQ CONFIG_SYS_CLK_FREQ
-
-#ifdef CONFIG_ATM
-#define CONFIG_PQ_MDS_PIB
-#define CONFIG_PQ_MDS_PIB_ATM
-#endif
-
-/*
- * These can be toggled for performance analysis, otherwise use default.
- */
-#define CONFIG_L2_CACHE /* toggle L2 cache */
-#define CONFIG_BTB /* toggle branch predition */
-
-#ifndef CONFIG_SYS_MONITOR_BASE
-#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */
-#endif
-
-/*
- * Only possible on E500 Version 2 or newer cores.
- */
-#define CONFIG_ENABLE_36BIT_PHYS 1
-
-#define CONFIG_HWCONFIG
-
-/*
- * Config the L2 Cache as L2 SRAM
- */
-#define CONFIG_SYS_INIT_L2_ADDR 0xf8f80000
-#define CONFIG_SYS_INIT_L2_ADDR_PHYS CONFIG_SYS_INIT_L2_ADDR
-#define CONFIG_SYS_L2_SIZE (512 << 10)
-#define CONFIG_SYS_INIT_L2_END (CONFIG_SYS_INIT_L2_ADDR + CONFIG_SYS_L2_SIZE)
-
-#define CONFIG_SYS_CCSRBAR 0xe0000000
-#define CONFIG_SYS_CCSRBAR_PHYS_LOW CONFIG_SYS_CCSRBAR
-
-#if defined(CONFIG_NAND_SPL)
-#define CONFIG_SYS_CCSR_DO_NOT_RELOCATE
-#endif
-
-/* DDR Setup */
-#define CONFIG_SPD_EEPROM /* Use SPD EEPROM for DDR setup*/
-#define CONFIG_DDR_SPD
-#define CONFIG_ECC_INIT_VIA_DDRCONTROLLER /* DDR controller or DMA? */
-
-#define CONFIG_MEM_INIT_VALUE 0xDeadBeef
-
-#define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000
- /* DDR is system memory*/
-#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
-
-#define CONFIG_DIMM_SLOTS_PER_CTLR 1
-#define CONFIG_CHIP_SELECTS_PER_CTRL (2 * CONFIG_DIMM_SLOTS_PER_CTLR)
-
-/* I2C addresses of SPD EEPROMs */
-#define SPD_EEPROM_ADDRESS 0x51 /* CTLR 0 DIMM 0 */
-
-/* These are used when DDR doesn't use SPD. */
-#define CONFIG_SYS_SDRAM_SIZE 1024 /* DDR is 1024MB */
-#define CONFIG_SYS_DDR_CS0_BNDS 0x0000003F
-#define CONFIG_SYS_DDR_CS0_CONFIG 0x80014202
-#define CONFIG_SYS_DDR_TIMING_3 0x00020000
-#define CONFIG_SYS_DDR_TIMING_0 0x00330004
-#define CONFIG_SYS_DDR_TIMING_1 0x6F6B4644
-#define CONFIG_SYS_DDR_TIMING_2 0x002888D0
-#define CONFIG_SYS_DDR_SDRAM_CFG 0x47000000
-#define CONFIG_SYS_DDR_SDRAM_CFG_2 0x04401040
-#define CONFIG_SYS_DDR_SDRAM_MODE 0x40401521
-#define CONFIG_SYS_DDR_SDRAM_MODE_2 0x8000C000
-#define CONFIG_SYS_DDR_SDRAM_INTERVAL 0x03E00000
-#define CONFIG_SYS_DDR_DATA_INIT 0xdeadbeef
-#define CONFIG_SYS_DDR_SDRAM_CLK_CNTL 0x01000000
-#define CONFIG_SYS_DDR_TIMING_4 0x00220001
-#define CONFIG_SYS_DDR_TIMING_5 0x03402400
-#define CONFIG_SYS_DDR_ZQ_CNTL 0x89080600
-#define CONFIG_SYS_DDR_WRLVL_CNTL 0x0655A604
-#define CONFIG_SYS_DDR_CDR_1 0x80040000
-#define CONFIG_SYS_DDR_CDR_2 0x00000000
-#define CONFIG_SYS_DDR_OCD_CTRL 0x00000000
-#define CONFIG_SYS_DDR_OCD_STATUS 0x00000000
-#define CONFIG_SYS_DDR_CONTROL 0xc7000000 /* Type = DDR3 */
-#define CONFIG_SYS_DDR_CONTROL2 0x24400000
-
-#define CONFIG_SYS_DDR_ERR_INT_EN 0x0000000d
-#define CONFIG_SYS_DDR_ERR_DIS 0x00000000
-#define CONFIG_SYS_DDR_SBE 0x00010000
-
-/*
- * Local Bus Definitions
- */
-
-#define CONFIG_SYS_FLASH_BASE 0xfe000000 /* start of FLASH 32M */
-#define CONFIG_SYS_FLASH_BASE_PHYS CONFIG_SYS_FLASH_BASE
-
-#define CONFIG_SYS_BCSR_BASE 0xf8000000
-#define CONFIG_SYS_BCSR_BASE_PHYS CONFIG_SYS_BCSR_BASE
-
-/*Chip select 0 - Flash*/
-#define CONFIG_FLASH_BR_PRELIM 0xfe000801
-#define CONFIG_FLASH_OR_PRELIM 0xfe000ff7
-
-/*Chip select 1 - BCSR*/
-#define CONFIG_SYS_BR1_PRELIM 0xf8000801
-#define CONFIG_SYS_OR1_PRELIM 0xffffe9f7
-
-/*Chip select 4 - PIB*/
-#define CONFIG_SYS_BR4_PRELIM 0xf8008801
-#define CONFIG_SYS_OR4_PRELIM 0xffffe9f7
-
-/*Chip select 5 - PIB*/
-#define CONFIG_SYS_BR5_PRELIM 0xf8010801
-#define CONFIG_SYS_OR5_PRELIM 0xffffe9f7
-
-#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */
-#define CONFIG_SYS_MAX_FLASH_SECT 512 /* sectors per device */
-#undef CONFIG_SYS_FLASH_CHECKSUM
-#define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */
-#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */
-
-#undef CONFIG_SYS_RAMBOOT
-
-#define CONFIG_SYS_FLASH_EMPTY_INFO
-
-/* Chip select 3 - NAND */
-#ifndef CONFIG_NAND_SPL
-#define CONFIG_SYS_NAND_BASE 0xFC000000
-#else
-#define CONFIG_SYS_NAND_BASE 0xFFF00000
-#endif
-
-/* NAND boot: 4K NAND loader config */
-#define CONFIG_SYS_NAND_SPL_SIZE 0x1000
-#define CONFIG_SYS_NAND_U_BOOT_SIZE ((512 << 10) - 0x2000)
-#define CONFIG_SYS_NAND_U_BOOT_DST (CONFIG_SYS_INIT_L2_ADDR)
-#define CONFIG_SYS_NAND_U_BOOT_START \
- (CONFIG_SYS_INIT_L2_ADDR + CONFIG_SYS_NAND_SPL_SIZE)
-#define CONFIG_SYS_NAND_U_BOOT_OFFS (0)
-#define CONFIG_SYS_NAND_U_BOOT_RELOC (CONFIG_SYS_INIT_L2_END - 0x2000)
-#define CONFIG_SYS_NAND_U_BOOT_RELOC_SP ((CONFIG_SYS_INIT_L2_END - 1) & ~0xF)
-
-#define CONFIG_SYS_NAND_BASE_PHYS CONFIG_SYS_NAND_BASE
-#define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE, }
-#define CONFIG_SYS_MAX_NAND_DEVICE 1
-#define CONFIG_NAND_FSL_ELBC 1
-#define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024)
-#define CONFIG_SYS_NAND_BR_PRELIM (CONFIG_SYS_NAND_BASE_PHYS \
- | (2<<BR_DECC_SHIFT) /* Use HW ECC */ \
- | BR_PS_8 /* Port Size = 8 bit */ \
- | BR_MS_FCM /* MSEL = FCM */ \
- | BR_V) /* valid */
-#define CONFIG_SYS_NAND_OR_PRELIM (0xFFFC0000 /* length 256K */ \
- | OR_FCM_CSCT \
- | OR_FCM_CST \
- | OR_FCM_CHT \
- | OR_FCM_SCY_1 \
- | OR_FCM_TRLX \
- | OR_FCM_EHTR)
-
-#define CONFIG_SYS_BR0_PRELIM CONFIG_FLASH_BR_PRELIM /* NOR Base Address */
-#define CONFIG_SYS_OR0_PRELIM CONFIG_FLASH_OR_PRELIM /* NOR Options */
-#define CONFIG_SYS_BR3_PRELIM CONFIG_SYS_NAND_BR_PRELIM /* NAND Base Address */
-#define CONFIG_SYS_OR3_PRELIM CONFIG_SYS_NAND_OR_PRELIM /* NAND Options */
-
-#define CONFIG_SYS_LBC_LCRR 0x00000004 /* LB clock ratio reg */
-#define CONFIG_SYS_LBC_LBCR 0x00040000 /* LB config reg */
-#define CONFIG_SYS_LBC_LSRT 0x20000000 /* LB sdram refresh timer */
-#define CONFIG_SYS_LBC_MRTPR 0x00000000 /* LB refresh timer prescal*/
-
-#define CONFIG_SYS_INIT_RAM_LOCK 1
-#define CONFIG_SYS_INIT_RAM_ADDR 0xe4010000 /* Initial RAM address */
-#define CONFIG_SYS_INIT_RAM_SIZE 0x4000 /* Size of used area in RAM */
-
-#define CONFIG_SYS_GBL_DATA_OFFSET \
- (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
-#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
-
-#define CONFIG_SYS_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Mon */
-#define CONFIG_SYS_MALLOC_LEN (512 * 1024) /* Reserved for malloc */
-
-/* Serial Port */
-#define CONFIG_SYS_NS16550_SERIAL
-#define CONFIG_SYS_NS16550_REG_SIZE 1
-#define CONFIG_SYS_NS16550_CLK get_bus_freq(0)
-#ifdef CONFIG_NAND_SPL
-#define CONFIG_NS16550_MIN_FUNCTIONS
-#endif
-
-#define CONFIG_SYS_BAUDRATE_TABLE \
- {300, 600, 1200, 2400, 4800, 9600, 19200, 38400,115200}
-
-#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x4500)
-#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x4600)
-
-/*
- * I2C
- */
-#define CONFIG_SYS_I2C
-#define CONFIG_SYS_I2C_FSL
-#define CONFIG_SYS_FSL_I2C_SPEED 400000
-#define CONFIG_SYS_FSL_I2C_SLAVE 0x7F
-#define CONFIG_SYS_FSL_I2C2_SPEED 400000
-#define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F
-#define CONFIG_SYS_FSL_I2C_OFFSET 0x3000
-#define CONFIG_SYS_FSL_I2C2_OFFSET 0x3100
-#define CONFIG_SYS_I2C_NOPROBES { {0, 0x69} }
-
-/*
- * I2C2 EEPROM
- */
-#define CONFIG_ID_EEPROM
-#ifdef CONFIG_ID_EEPROM
-#define CONFIG_SYS_I2C_EEPROM_NXID
-#endif
-#define CONFIG_SYS_I2C_EEPROM_ADDR 0x52
-#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
-#define CONFIG_SYS_EEPROM_BUS_NUM 1
-
-#define PLPPAR1_I2C_BIT_MASK 0x0000000F
-#define PLPPAR1_I2C2_VAL 0x00000000
-#define PLPPAR1_ESDHC_VAL 0x0000000A
-#define PLPDIR1_I2C_BIT_MASK 0x0000000F
-#define PLPDIR1_I2C2_VAL 0x0000000F
-#define PLPDIR1_ESDHC_VAL 0x00000006
-#define PLPPAR1_UART0_BIT_MASK 0x00000fc0
-#define PLPPAR1_ESDHC_4BITS_VAL 0x00000a80
-#define PLPDIR1_UART0_BIT_MASK 0x00000fc0
-#define PLPDIR1_ESDHC_4BITS_VAL 0x00000a80
-
-/*
- * General PCI
- * Memory Addresses are mapped 1-1. I/O is mapped from 0
- */
-#define CONFIG_SYS_PCIE1_NAME "Slot"
-#define CONFIG_SYS_PCIE1_MEM_VIRT 0xa0000000
-#define CONFIG_SYS_PCIE1_MEM_BUS 0xa0000000
-#define CONFIG_SYS_PCIE1_MEM_PHYS 0xa0000000
-#define CONFIG_SYS_PCIE1_MEM_SIZE 0x20000000 /* 512M */
-#define CONFIG_SYS_PCIE1_IO_VIRT 0xe2800000
-#define CONFIG_SYS_PCIE1_IO_BUS 0x00000000
-#define CONFIG_SYS_PCIE1_IO_PHYS 0xe2800000
-#define CONFIG_SYS_PCIE1_IO_SIZE 0x00800000 /* 8M */
-
-#define CONFIG_SYS_SRIO1_MEM_VIRT 0xC0000000
-#define CONFIG_SYS_SRIO1_MEM_BUS 0xC0000000
-#define CONFIG_SYS_SRIO1_MEM_PHYS CONFIG_SYS_SRIO1_MEM_BUS
-#define CONFIG_SYS_SRIO1_MEM_SIZE 0x20000000 /* 512M */
-
-#ifdef CONFIG_QE
-/*
- * QE UEC ethernet configuration
- */
-#define CONFIG_SYS_UCC_RGMII_MODE /* Set UCC work at RGMII by default */
-#undef CONFIG_SYS_UCC_RMII_MODE /* Set UCC work at RMII mode */
-
-#define CONFIG_MIIM_ADDRESS (CONFIG_SYS_CCSRBAR + 0x82120)
-#define CONFIG_UEC_ETH
-#define CONFIG_ETHPRIME "UEC0"
-#define CONFIG_PHY_MODE_NEED_CHANGE
-
-#define CONFIG_UEC_ETH1 /* GETH1 */
-#define CONFIG_HAS_ETH0
-
-#ifdef CONFIG_UEC_ETH1
-#define CONFIG_SYS_UEC1_UCC_NUM 0 /* UCC1 */
-#define CONFIG_SYS_UEC1_RX_CLK QE_CLK_NONE
-#if defined(CONFIG_SYS_UCC_RGMII_MODE)
-#define CONFIG_SYS_UEC1_TX_CLK QE_CLK12
-#define CONFIG_SYS_UEC1_ETH_TYPE GIGA_ETH
-#define CONFIG_SYS_UEC1_PHY_ADDR 7
-#define CONFIG_SYS_UEC1_INTERFACE_TYPE PHY_INTERFACE_MODE_RGMII_ID
-#define CONFIG_SYS_UEC1_INTERFACE_SPEED 1000
-#elif defined(CONFIG_SYS_UCC_RMII_MODE)
-#define CONFIG_SYS_UEC1_TX_CLK QE_CLK16 /* CLK16 for RMII */
-#define CONFIG_SYS_UEC1_ETH_TYPE FAST_ETH
-#define CONFIG_SYS_UEC1_PHY_ADDR 8 /* 0x8 for RMII */
-#define CONFIG_SYS_UEC1_INTERFACE_TYPE PHY_INTERFACE_MODE_RMII
-#define CONFIG_SYS_UEC1_INTERFACE_SPEED 100
-#endif /* CONFIG_SYS_UCC_RGMII_MODE */
-#endif /* CONFIG_UEC_ETH1 */
-
-#define CONFIG_UEC_ETH2 /* GETH2 */
-#define CONFIG_HAS_ETH1
-
-#ifdef CONFIG_UEC_ETH2
-#define CONFIG_SYS_UEC2_UCC_NUM 1 /* UCC2 */
-#define CONFIG_SYS_UEC2_RX_CLK QE_CLK_NONE
-#if defined(CONFIG_SYS_UCC_RGMII_MODE)
-#define CONFIG_SYS_UEC2_TX_CLK QE_CLK17
-#define CONFIG_SYS_UEC2_ETH_TYPE GIGA_ETH
-#define CONFIG_SYS_UEC2_PHY_ADDR 1
-#define CONFIG_SYS_UEC2_INTERFACE_TYPE PHY_INTERFACE_MODE_RGMII_ID
-#define CONFIG_SYS_UEC2_INTERFACE_SPEED 1000
-#elif defined(CONFIG_SYS_UCC_RMII_MODE)
-#define CONFIG_SYS_UEC2_TX_CLK QE_CLK16 /* CLK 16 for RMII */
-#define CONFIG_SYS_UEC2_ETH_TYPE FAST_ETH
-#define CONFIG_SYS_UEC2_PHY_ADDR 0x9 /* 0x9 for RMII */
-#define CONFIG_SYS_UEC2_INTERFACE_TYPE PHY_INTERFACE_MODE_RMII
-#define CONFIG_SYS_UEC2_INTERFACE_SPEED 100
-#endif /* CONFIG_SYS_UCC_RGMII_MODE */
-#endif /* CONFIG_UEC_ETH2 */
-
-#define CONFIG_UEC_ETH3 /* GETH3 */
-#define CONFIG_HAS_ETH2
-
-#ifdef CONFIG_UEC_ETH3
-#define CONFIG_SYS_UEC3_UCC_NUM 2 /* UCC3 */
-#define CONFIG_SYS_UEC3_RX_CLK QE_CLK_NONE
-#if defined(CONFIG_SYS_UCC_RGMII_MODE)
-#define CONFIG_SYS_UEC3_TX_CLK QE_CLK12
-#define CONFIG_SYS_UEC3_ETH_TYPE GIGA_ETH
-#define CONFIG_SYS_UEC3_PHY_ADDR 2
-#define CONFIG_SYS_UEC3_INTERFACE_TYPE PHY_INTERFACE_MODE_RGMII_ID
-#define CONFIG_SYS_UEC3_INTERFACE_SPEED 1000
-#elif defined(CONFIG_SYS_UCC_RMII_MODE)
-#define CONFIG_SYS_UEC3_TX_CLK QE_CLK16 /* CLK_16 for RMII */
-#define CONFIG_SYS_UEC3_ETH_TYPE FAST_ETH
-#define CONFIG_SYS_UEC3_PHY_ADDR 0xA /* 0xA for RMII */
-#define CONFIG_SYS_UEC3_INTERFACE_TYPE PHY_INTERFACE_MODE_RMII
-#define CONFIG_SYS_UEC3_INTERFACE_SPEED 100
-#endif /* CONFIG_SYS_UCC_RGMII_MODE */
-#endif /* CONFIG_UEC_ETH3 */
-
-#define CONFIG_UEC_ETH4 /* GETH4 */
-#define CONFIG_HAS_ETH3
-
-#ifdef CONFIG_UEC_ETH4
-#define CONFIG_SYS_UEC4_UCC_NUM 3 /* UCC4 */
-#define CONFIG_SYS_UEC4_RX_CLK QE_CLK_NONE
-#if defined(CONFIG_SYS_UCC_RGMII_MODE)
-#define CONFIG_SYS_UEC4_TX_CLK QE_CLK17
-#define CONFIG_SYS_UEC4_ETH_TYPE GIGA_ETH
-#define CONFIG_SYS_UEC4_PHY_ADDR 3
-#define CONFIG_SYS_UEC4_INTERFACE_TYPE PHY_INTERFACE_MODE_RGMII_ID
-#define CONFIG_SYS_UEC4_INTERFACE_SPEED 1000
-#elif defined(CONFIG_SYS_UCC_RMII_MODE)
-#define CONFIG_SYS_UEC4_TX_CLK QE_CLK16 /* CLK16 for RMII */
-#define CONFIG_SYS_UEC4_ETH_TYPE FAST_ETH
-#define CONFIG_SYS_UEC4_PHY_ADDR 0xB /* 0xB for RMII */
-#define CONFIG_SYS_UEC4_INTERFACE_TYPE PHY_INTERFACE_MODE_RMII
-#define CONFIG_SYS_UEC4_INTERFACE_SPEED 100
-#endif /* CONFIG_SYS_UCC_RGMII_MODE */
-#endif /* CONFIG_UEC_ETH4 */
-
-#undef CONFIG_UEC_ETH6 /* GETH6 */
-#define CONFIG_HAS_ETH5
-
-#ifdef CONFIG_UEC_ETH6
-#define CONFIG_SYS_UEC6_UCC_NUM 5 /* UCC6 */
-#define CONFIG_SYS_UEC6_RX_CLK QE_CLK_NONE
-#define CONFIG_SYS_UEC6_TX_CLK QE_CLK_NONE
-#define CONFIG_SYS_UEC6_ETH_TYPE GIGA_ETH
-#define CONFIG_SYS_UEC6_PHY_ADDR 4
-#define CONFIG_SYS_UEC6_INTERFACE_TYPE PHY_INTERFACE_MODE_SGMII
-#define CONFIG_SYS_UEC6_INTERFACE_SPEED 1000
-#endif /* CONFIG_UEC_ETH6 */
-
-#undef CONFIG_UEC_ETH8 /* GETH8 */
-#define CONFIG_HAS_ETH7
-
-#ifdef CONFIG_UEC_ETH8
-#define CONFIG_SYS_UEC8_UCC_NUM 7 /* UCC8 */
-#define CONFIG_SYS_UEC8_RX_CLK QE_CLK_NONE
-#define CONFIG_SYS_UEC8_TX_CLK QE_CLK_NONE
-#define CONFIG_SYS_UEC8_ETH_TYPE GIGA_ETH
-#define CONFIG_SYS_UEC8_PHY_ADDR 6
-#define CONFIG_SYS_UEC8_INTERFACE_TYPE PHY_INTERFACE_MODE_SGMII
-#define CONFIG_SYS_UEC8_INTERFACE_SPEED 1000
-#endif /* CONFIG_UEC_ETH8 */
-
-#endif /* CONFIG_QE */
-
-#if defined(CONFIG_PCI)
-
-#undef CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
-
-#endif /* CONFIG_PCI */
-
-/*
- * Environment
- */
-
-#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
-#define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
-
-/* QE microcode/firmware address */
-#define CONFIG_SYS_QE_FW_ADDR 0xfff00000
-
-/*
- * BOOTP options
- */
-#define CONFIG_BOOTP_BOOTFILESIZE
-
-#undef CONFIG_WATCHDOG /* watchdog disabled */
-
-#ifdef CONFIG_MMC
-#define CONFIG_FSL_ESDHC_PIN_MUX
-#define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC85xx_ESDHC_ADDR
-#endif
-
-/*
- * Miscellaneous configurable options
- */
-#define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */
-#if defined(CONFIG_CMD_KGDB)
-#define CONFIG_SYS_CBSIZE 2048 /* Console I/O Buffer Size */
-#else
-#define CONFIG_SYS_CBSIZE 512 /* Console I/O Buffer Size */
-#endif
-#define CONFIG_SYS_MAXARGS 32 /* max number of command args */
-#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
- /* Boot Argument Buffer Size */
-
-/*
- * For booting Linux, the board info and command line data
- * have to be in the first 64 MB of memory, since this is
- * the maximum mapped by the Linux kernel during initialization.
- */
-#define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial Memory map for Linux*/
-#define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */
-
-#if defined(CONFIG_CMD_KGDB)
-#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */
-#endif
-
-/*
- * Environment Configuration
- */
-#define CONFIG_HOSTNAME "mpc8569mds"
-#define CONFIG_ROOTPATH "/nfsroot"
-#define CONFIG_BOOTFILE "your.uImage"
-
-#define CONFIG_SERVERIP 192.168.1.1
-#define CONFIG_GATEWAYIP 192.168.1.1
-#define CONFIG_NETMASK 255.255.255.0
-
-#define CONFIG_LOADADDR 200000 /*default location for tftp and bootm*/
-
-#define CONFIG_EXTRA_ENV_SETTINGS \
- "netdev=eth0\0" \
- "consoledev=ttyS0\0" \
- "ramdiskaddr=600000\0" \
- "ramdiskfile=your.ramdisk.u-boot\0" \
- "fdtaddr=400000\0" \
- "fdtfile=your.fdt.dtb\0" \
- "nfsargs=setenv bootargs root=/dev/nfs rw " \
- "nfsroot=$serverip:$rootpath " \
- "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
- "console=$consoledev,$baudrate $othbootargs\0" \
- "ramargs=setenv bootargs root=/dev/ram rw " \
- "console=$consoledev,$baudrate $othbootargs\0" \
-
-#define CONFIG_NFSBOOTCOMMAND \
- "run nfsargs;" \
- "tftp $loadaddr $bootfile;" \
- "tftp $fdtaddr $fdtfile;" \
- "bootm $loadaddr - $fdtaddr"
-
-#define CONFIG_RAMBOOTCOMMAND \
- "run ramargs;" \
- "tftp $ramdiskaddr $ramdiskfile;" \
- "tftp $loadaddr $bootfile;" \
- "bootm $loadaddr $ramdiskaddr"
-
-#define CONFIG_BOOTCOMMAND CONFIG_NFSBOOTCOMMAND
-
-#endif /* __CONFIG_H */
diff --git a/include/configs/am65x_evm.h b/include/configs/am65x_evm.h
index b39a5b4..76d7308 100644
--- a/include/configs/am65x_evm.h
+++ b/include/configs/am65x_evm.h
@@ -30,7 +30,7 @@
* our memory footprint. The less we use for BSS the more we have available
* for everything else.
*/
-#define CONFIG_SPL_BSS_MAX_SIZE 0x5000
+#define CONFIG_SPL_BSS_MAX_SIZE 0xc00
/*
* Link BSS to be within SPL in a dedicated region located near the top of
* the MCU SRAM, this way making it available also before relocation. Note
diff --git a/include/configs/apalis-imx8.h b/include/configs/apalis-imx8.h
index b474b2f..8fe3226 100644
--- a/include/configs/apalis-imx8.h
+++ b/include/configs/apalis-imx8.h
@@ -21,9 +21,6 @@
#define CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG
/* Networking */
-#define FEC_QUIRK_ENET_MAC
-#define FEC_ENET_ENABLE_TXC_DELAY
-
#define CONFIG_TFTP_TSIZE
#define CONFIG_IPADDR 192.168.10.2
diff --git a/include/configs/apalis-imx8x.h b/include/configs/apalis-imx8x.h
index db31c21..fdb0da3 100644
--- a/include/configs/apalis-imx8x.h
+++ b/include/configs/apalis-imx8x.h
@@ -25,9 +25,6 @@
#define CONFIG_NETMASK 255.255.255.0
#define CONFIG_SERVERIP 192.168.10.1
-#define FEC_ENET_ENABLE_TXC_DELAY
-#define FEC_ENET_ENABLE_RXC_DELAY
-
#define MEM_LAYOUT_ENV_SETTINGS \
"kernel_addr_r=0x80280000\0" \
"fdt_addr_r=0x83100000\0" \
@@ -143,7 +140,6 @@
#define CONFIG_FEC_MXC_PHYADDR 0x4
#define CONFIG_ETHPRIME "eth0"
#define CONFIG_FEC_XCV_TYPE RGMII
-#define FEC_QUIRK_ENET_MAC
#define PHY_ANEG_TIMEOUT 20000
#endif /* __APALIS_IMX8X_H */
diff --git a/include/configs/capricorn-common.h b/include/configs/capricorn-common.h
index 7c168f1..b310e6c 100644
--- a/include/configs/capricorn-common.h
+++ b/include/configs/capricorn-common.h
@@ -43,7 +43,6 @@
/* ENET Config */
#define CONFIG_FEC_XCV_TYPE RMII
-#define FEC_QUIRK_ENET_MAC
/* ENET1 connects to base board and MUX with ESAI */
#define CONFIG_FEC_ENET_DEV 1
diff --git a/include/configs/colibri-imx8x.h b/include/configs/colibri-imx8x.h
index fc2c191..59593f6 100644
--- a/include/configs/colibri-imx8x.h
+++ b/include/configs/colibri-imx8x.h
@@ -22,8 +22,6 @@
#define CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG
/* Networking */
-#define FEC_QUIRK_ENET_MAC
-
#define CONFIG_TFTP_TSIZE
#define CONFIG_IPADDR 192.168.10.2
diff --git a/include/configs/da850evm.h b/include/configs/da850evm.h
index 0f41748..883cbc9 100644
--- a/include/configs/da850evm.h
+++ b/include/configs/da850evm.h
@@ -215,6 +215,10 @@
#define CONFIG_USB_OHCI_NEW
#define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS 15
+#ifndef CONFIG_MTD_NOR_FLASH
+#define CONFIG_SPL_PAD_TO 32768
+#endif
+
#ifdef CONFIG_SPL_BUILD
/* defines for SPL */
#define CONFIG_SYS_SPL_MALLOC_START (CONFIG_SYS_TEXT_BASE - \
@@ -222,7 +226,7 @@
#define CONFIG_SYS_SPL_MALLOC_SIZE CONFIG_SYS_MALLOC_LEN
#define CONFIG_SPL_STACK 0x8001ff00
#define CONFIG_SPL_MAX_FOOTPRINT 32768
-#define CONFIG_SPL_PAD_TO 32768
+
#endif
/* Load U-Boot Image From MMC */
diff --git a/include/configs/hikey.h b/include/configs/hikey.h
index a323a0b..659fbee 100644
--- a/include/configs/hikey.h
+++ b/include/configs/hikey.h
@@ -47,9 +47,7 @@
/* Size of malloc() pool */
#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + SZ_8M)
-#ifdef CONFIG_CMD_USB
-#define CONFIG_USB_DWC2_REG_ADDR 0xF72C0000
-/*#define CONFIG_DWC2_DFLT_SPEED_FULL*/
+#ifdef CONFIG_USB_DWC2
#define CONFIG_DWC2_ENABLE_DYNAMIC_FIFO
#endif
diff --git a/include/configs/imx8mm_venice.h b/include/configs/imx8mm_venice.h
new file mode 100644
index 0000000..a406e91
--- /dev/null
+++ b/include/configs/imx8mm_venice.h
@@ -0,0 +1,125 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright 2021 Gateworks Corporation
+ */
+
+#ifndef __IMX8MM_VENICE_H
+#define __IMX8MM_VENICE_H
+
+#include <asm/arch/imx-regs.h>
+#include <linux/sizes.h>
+
+#define CONFIG_SPL_MAX_SIZE (148 * 1024)
+#define CONFIG_SYS_MONITOR_LEN SZ_512K
+#define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR
+#define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR 0x300
+#define CONFIG_SYS_UBOOT_BASE \
+ (QSPI0_AMBA_BASE + CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR * 512)
+
+#ifdef CONFIG_SPL_BUILD
+#define CONFIG_SPL_STACK 0x920000
+#define CONFIG_SPL_BSS_START_ADDR 0x910000
+#define CONFIG_SPL_BSS_MAX_SIZE SZ_8K /* 8 KB */
+#define CONFIG_SYS_SPL_MALLOC_START 0x42200000
+#define CONFIG_SYS_SPL_MALLOC_SIZE SZ_512K /* 512 KB */
+
+/* malloc f used before GD_FLG_FULL_MALLOC_INIT set */
+#define CONFIG_MALLOC_F_ADDR 0x930000
+/* For RAW image gives a error info not panic */
+#define CONFIG_SPL_ABORT_ON_RAW_IMAGE
+
+#endif
+
+#define MEM_LAYOUT_ENV_SETTINGS \
+ "fdt_addr_r=0x44000000\0" \
+ "kernel_addr_r=0x42000000\0" \
+ "ramdisk_addr_r=0x46400000\0" \
+ "scriptaddr=0x46000000\0"
+
+/* Link Definitions */
+#define CONFIG_LOADADDR 0x40480000
+#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR
+
+/* Enable Distro Boot */
+#ifndef CONFIG_SPL_BUILD
+#define BOOT_TARGET_DEVICES(func) \
+ func(MMC, mmc, 1) \
+ func(MMC, mmc, 2) \
+ func(DHCP, dhcp, na)
+#include <config_distro_bootcmd.h>
+#undef CONFIG_ISO_PARTITION
+#else
+#define BOOTENV
+#endif
+
+/* Initial environment variables */
+#define CONFIG_EXTRA_ENV_SETTINGS \
+ BOOTENV \
+ MEM_LAYOUT_ENV_SETTINGS \
+ "script=boot.scr\0" \
+ "bootm_size=0x10000000\0" \
+ "ipaddr=192.168.1.22\0" \
+ "serverip=192.168.1.146\0" \
+ "dev=2\0" \
+ "preboot=gsc wd-disable\0" \
+ "console=ttymxc1,115200\0" \
+ "update_firmware=" \
+ "tftpboot $loadaddr $image && " \
+ "setexpr blkcnt $filesize + 0x1ff && " \
+ "setexpr blkcnt $blkcnt / 0x200 && " \
+ "mmc dev $dev && " \
+ "mmc write $loadaddr 0x42 $blkcnt\0" \
+ "boot_net=" \
+ "tftpboot $kernel_addr_r $image && " \
+ "booti $kernel_addr_r - $fdtcontroladdr\0" \
+ "update_rootfs=" \
+ "tftpboot $loadaddr $image && " \
+ "gzwrite mmc $dev $loadaddr $filesize 100000 1000000\0" \
+ "update_all=" \
+ "tftpboot $loadaddr $image && " \
+ "gzwrite mmc $dev $loadaddr $filesize\0" \
+ "erase_env=mmc dev $dev; mmc erase 0x7f08 0x40\0"
+
+#define CONFIG_SYS_INIT_RAM_ADDR 0x40000000
+#define CONFIG_SYS_INIT_RAM_SIZE SZ_2M
+#define CONFIG_SYS_INIT_SP_OFFSET \
+ (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
+#define CONFIG_SYS_INIT_SP_ADDR \
+ (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET)
+
+/* Size of malloc() pool */
+#define CONFIG_SYS_MALLOC_LEN SZ_32M
+#define CONFIG_SYS_SDRAM_BASE 0x40000000
+
+/* SDRAM configuration */
+#define PHYS_SDRAM 0x40000000
+#define PHYS_SDRAM_SIZE SZ_1G /* 1GB DDR */
+#define CONFIG_SYS_BOOTM_LEN SZ_256M
+
+/* UART */
+#define CONFIG_MXC_UART_BASE UART2_BASE_ADDR
+
+/* Monitor Command Prompt */
+#define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
+#define CONFIG_SYS_CBSIZE SZ_2K
+#define CONFIG_SYS_MAXARGS 64
+#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
+#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \
+ sizeof(CONFIG_SYS_PROMPT) + 16)
+
+/* USDHC */
+#define CONFIG_SYS_FSL_USDHC_NUM 2
+#define CONFIG_SYS_FSL_ESDHC_ADDR 0
+#define CONFIG_SYS_MMC_IMG_LOAD_PART 1
+
+/* I2C */
+#define CONFIG_SYS_I2C_SPEED 100000
+
+/* FEC */
+#define CONFIG_ETHPRIME "eth0"
+#define CONFIG_FEC_XCV_TYPE RGMII
+#define CONFIG_FEC_MXC_PHYADDR 0
+#define FEC_QUIRK_ENET_MAC
+#define IMX_FEC_BASE 0x30BE0000
+
+#endif
diff --git a/include/configs/imx8mn_beacon.h b/include/configs/imx8mn_beacon.h
index 7a247cc..9ce60fd 100644
--- a/include/configs/imx8mn_beacon.h
+++ b/include/configs/imx8mn_beacon.h
@@ -126,7 +126,11 @@
#define CONFIG_SYS_SDRAM_BASE 0x40000000
#define PHYS_SDRAM 0x40000000
+#if CONFIG_IS_ENABLED(IMX8MN_BEACON_2GB_LPDDR)
+#define PHYS_SDRAM_SIZE 0x80000000 /* 2GB DDR */
+#else
#define PHYS_SDRAM_SIZE 0x40000000 /* 1GB DDR */
+#endif
#define CONFIG_MXC_UART_BASE UART2_BASE_ADDR
diff --git a/include/configs/imx8qm_mek.h b/include/configs/imx8qm_mek.h
index ff281d3..99e73a9 100644
--- a/include/configs/imx8qm_mek.h
+++ b/include/configs/imx8qm_mek.h
@@ -173,6 +173,5 @@
/* Networking */
#define CONFIG_FEC_XCV_TYPE RGMII
-#define FEC_QUIRK_ENET_MAC
#endif /* __IMX8QM_MEK_H */
diff --git a/include/configs/imx8qm_rom7720.h b/include/configs/imx8qm_rom7720.h
index e5989eb..fcbf8ee 100644
--- a/include/configs/imx8qm_rom7720.h
+++ b/include/configs/imx8qm_rom7720.h
@@ -161,7 +161,6 @@
/* Networking */
#define CONFIG_FEC_XCV_TYPE RGMII
-#define FEC_QUIRK_ENET_MAC
#include <linux/stringify.h>
#endif /* __IMX8QM_ROM7720_H */
diff --git a/include/configs/imx8qxp_mek.h b/include/configs/imx8qxp_mek.h
index 51a8eb6..a7d623a 100644
--- a/include/configs/imx8qxp_mek.h
+++ b/include/configs/imx8qxp_mek.h
@@ -177,7 +177,6 @@
/* Networking */
#define CONFIG_FEC_XCV_TYPE RGMII
-#define FEC_QUIRK_ENET_MAC
/* Misc configuration */
#define CONFIG_SYS_CBSIZE 2048
diff --git a/include/configs/ls1088aqds.h b/include/configs/ls1088aqds.h
index 0dcf844..4d04833 100644
--- a/include/configs/ls1088aqds.h
+++ b/include/configs/ls1088aqds.h
@@ -326,12 +326,6 @@
#define CONFIG_VOL_MONITOR_LTC3882_SET
#define CONFIG_VOL_MONITOR_LTC3882_READ
-/* PM Bus commands code for LTC3882*/
-#define PMBUS_CMD_PAGE 0x0
-#define PMBUS_CMD_READ_VOUT 0x8B
-#define PMBUS_CMD_PAGE_PLUS_WRITE 0x05
-#define PMBUS_CMD_VOUT_COMMAND 0x21
-
#define PWM_CHANNEL0 0x0
/*
diff --git a/include/configs/ls1088ardb.h b/include/configs/ls1088ardb.h
index f59a9f5..6f36dd4 100644
--- a/include/configs/ls1088ardb.h
+++ b/include/configs/ls1088ardb.h
@@ -203,7 +203,7 @@
#define CONFIG_SYS_LS_MC_BOOT_TIMEOUT_MS 5000
-#define I2C_MUX_CH_VOL_MONITOR 0xA
+#define I2C_MUX_CH_VOL_MONITOR 0xA
/* Voltage monitor on channel 2*/
#define I2C_VOL_MONITOR_ADDR 0x63
#define I2C_VOL_MONITOR_BUS_V_OFFSET 0x2
@@ -221,12 +221,6 @@
#define CONFIG_VOL_MONITOR_LTC3882_SET
#define CONFIG_VOL_MONITOR_LTC3882_READ
-/* PM Bus commands code for LTC3882*/
-#define PMBUS_CMD_PAGE 0x0
-#define PMBUS_CMD_READ_VOUT 0x8B
-#define PMBUS_CMD_PAGE_PLUS_WRITE 0x05
-#define PMBUS_CMD_VOUT_COMMAND 0x21
-
#define PWM_CHANNEL0 0x0
/*
diff --git a/include/configs/meson64.h b/include/configs/meson64.h
index 52cc01f..7e97f89 100644
--- a/include/configs/meson64.h
+++ b/include/configs/meson64.h
@@ -80,6 +80,7 @@
"scriptaddr=0x08000000\0" \
"kernel_addr_r=0x08080000\0" \
"pxefile_addr_r=0x01080000\0" \
+ "fdtoverlay_addr_r=0x01000000\0" \
"ramdisk_addr_r=0x13000000\0" \
"fdtfile=amlogic/" CONFIG_DEFAULT_DEVICE_TREE ".dtb\0" \
BOOTENV
diff --git a/include/configs/mx25pdk.h b/include/configs/mx25pdk.h
deleted file mode 100644
index 27d0c25..0000000
--- a/include/configs/mx25pdk.h
+++ /dev/null
@@ -1,178 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0+ */
-/*
- * (C) Copyright 2011 Freescale Semiconductor, Inc.
- */
-
-#ifndef __CONFIG_H
-#define __CONFIG_H
-
-#include <asm/arch/imx-regs.h>
-
-/* High Level Configuration Options */
-
-#define CONFIG_SYS_TEXT_BASE 0x81200000
-#define CONFIG_SYS_FSL_CLK
-
-#define CONFIG_SYS_TIMER_RATE 32768
-#define CONFIG_SYS_TIMER_COUNTER \
- (&((struct gpt_regs *)IMX_GPT1_BASE)->counter)
-
-#define CONFIG_CMDLINE_TAG /* enable passing of ATAGs */
-#define CONFIG_SETUP_MEMORY_TAGS
-#define CONFIG_INITRD_TAG
-
-#define CONFIG_MACH_TYPE MACH_TYPE_MX25_3DS
-
-/* Size of malloc() pool */
-#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 2 * 1024 * 1024)
-
-/* Physical Memory Map */
-
-#define PHYS_SDRAM_1 0x80000000
-#define PHYS_SDRAM_1_SIZE (64 * 1024 * 1024)
-
-#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1
-#define CONFIG_SYS_INIT_RAM_ADDR IMX_RAM_BASE
-#define CONFIG_SYS_INIT_RAM_SIZE IMX_RAM_SIZE
-
-#define CONFIG_SYS_INIT_SP_OFFSET \
- (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
-#define CONFIG_SYS_INIT_SP_ADDR \
- (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET)
-
-/* Memory Test */
-
-/* Serial Info */
-#define CONFIG_MXC_UART_BASE UART1_BASE
-
-/* No NOR flash present */
-
-/* U-Boot general configuration */
-#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
-/* Boot Argument Buffer Size */
-#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
-
-/* Ethernet */
-#define CONFIG_FEC_MXC
-#define CONFIG_FEC_MXC_PHYADDR 0x1f
-
-/* ESDHC driver */
-#define CONFIG_SYS_FSL_ESDHC_ADDR IMX_MMC_SDHC1_BASE
-#define CONFIG_SYS_FSL_ESDHC_NUM 1
-
-/* PMIC Configs */
-#define CONFIG_POWER
-#define CONFIG_POWER_I2C
-#define CONFIG_POWER_FSL
-#define CONFIG_POWER_FSL_MC34704
-#define CONFIG_SYS_FSL_PMIC_I2C_ADDR 0x54
-
-/* I2C Configs */
-#define CONFIG_SYS_I2C
-#define CONFIG_SYS_I2C_MXC
-#define CONFIG_SYS_I2C_MXC_I2C1 /* enable I2C bus 1 */
-#define CONFIG_SYS_I2C_MXC_I2C2 /* enable I2C bus 2 */
-
-/* RTC */
-#define CONFIG_RTC_IMXDI
-
-/* Fuse API support */
-#define CONFIG_FSL_IIM
-
-/* Ethernet Configs */
-
-
-#define CONFIG_LOADADDR 0x81000000 /* loadaddr env var */
-#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR
-
-#define CONFIG_EXTRA_ENV_SETTINGS \
- "script=boot.scr\0" \
- "image=zImage\0" \
- "console=ttymxc0\0" \
- "splashpos=m,m\0" \
- "fdt_high=0xffffffff\0" \
- "initrd_high=0xffffffff\0" \
- "fdt_file=" CONFIG_DEFAULT_FDT_FILE "\0" \
- "fdt_addr=0x82000000\0" \
- "boot_fdt=try\0" \
- "ip_dyn=yes\0" \
- "mmcdev=" __stringify(CONFIG_SYS_MMC_ENV_DEV) "\0" \
- "mmcpart=1\0" \
- "mmcroot=/dev/mmcblk0p2 rootwait rw\0" \
- "update_sd_firmware_filename=u-boot.imx\0" \
- "update_sd_firmware=" \
- "if test ${ip_dyn} = yes; then " \
- "setenv get_cmd dhcp; " \
- "else " \
- "setenv get_cmd tftp; " \
- "fi; " \
- "if mmc dev ${mmcdev}; then " \
- "if ${get_cmd} ${update_sd_firmware_filename}; then " \
- "setexpr fw_sz ${filesize} / 0x200; " \
- "setexpr fw_sz ${fw_sz} + 1; " \
- "mmc write ${loadaddr} 0x2 ${fw_sz}; " \
- "fi; " \
- "fi\0" \
- "mmcargs=setenv bootargs console=${console},${baudrate} " \
- "root=${mmcroot}\0" \
- "loadbootscript=" \
- "load mmc ${mmcdev}:${mmcpart} ${loadaddr} ${script};\0" \
- "bootscript=echo Running bootscript from mmc ...; " \
- "source\0" \
- "loadimage=load mmc ${mmcdev}:${mmcpart} ${loadaddr} ${image}\0" \
- "loadfdt=load mmc ${mmcdev}:${mmcpart} ${fdt_addr} ${fdt_file}\0" \
- "mmcboot=echo Booting from mmc ...; " \
- "run mmcargs; " \
- "if test ${boot_fdt} = yes || test ${boot_fdt} = try; then " \
- "if run loadfdt; then " \
- "bootz ${loadaddr} - ${fdt_addr}; " \
- "else " \
- "if test ${boot_fdt} = try; then " \
- "bootz; " \
- "else " \
- "echo WARN: Cannot load the DT; " \
- "fi; " \
- "fi; " \
- "else " \
- "bootz; " \
- "fi;\0" \
- "netargs=setenv bootargs console=${console},${baudrate} " \
- "root=/dev/nfs " \
- "ip=dhcp nfsroot=${serverip}:${nfsroot},v3,tcp\0" \
- "netboot=echo Booting from net ...; " \
- "run netargs; " \
- "if test ${ip_dyn} = yes; then " \
- "setenv get_cmd dhcp; " \
- "else " \
- "setenv get_cmd tftp; " \
- "fi; " \
- "${get_cmd} ${image}; " \
- "if test ${boot_fdt} = yes || test ${boot_fdt} = try; then " \
- "if ${get_cmd} ${fdt_addr} ${fdt_file}; then " \
- "bootz ${loadaddr} - ${fdt_addr}; " \
- "else " \
- "if test ${boot_fdt} = try; then " \
- "bootz; " \
- "else " \
- "echo WARN: Cannot load the DT; " \
- "fi; " \
- "fi; " \
- "else " \
- "bootz; " \
- "fi;\0"
-
-#define CONFIG_BOOTCOMMAND \
- "mmc dev ${mmcdev}; if mmc rescan; then " \
- "if run loadbootscript; then " \
- "run bootscript; " \
- "else " \
- "if run loadimage; then " \
- "run mmcboot; " \
- "else run netboot; " \
- "fi; " \
- "fi; " \
- "else run netboot; fi"
-
-/* Miscellaneous configurable options */
-
-#endif /* __CONFIG_H */
diff --git a/include/configs/mx51evk.h b/include/configs/mx51evk.h
index 49f88c2..3574d65 100644
--- a/include/configs/mx51evk.h
+++ b/include/configs/mx51evk.h
@@ -51,14 +51,6 @@
#define CONFIG_SYS_FSL_ESDHC_ADDR MMC_SDHC1_BASE_ADDR
#define CONFIG_SYS_FSL_ESDHC_NUM 2
-/*
- * Eth Configs
- */
-
-#define CONFIG_FEC_MXC
-#define IMX_FEC_BASE FEC_BASE_ADDR
-#define CONFIG_FEC_MXC_PHYADDR 0x1F
-
/* USB Configs */
#define CONFIG_MXC_USB_PORT 1
#define CONFIG_MXC_USB_PORTSC PORT_PTS_ULPI
diff --git a/include/configs/mx53ard.h b/include/configs/mx53ard.h
deleted file mode 100644
index b613e98..0000000
--- a/include/configs/mx53ard.h
+++ /dev/null
@@ -1,170 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0+ */
-/*
- * Copyright (C) 2011 Freescale Semiconductor, Inc.
- *
- * Configuration settings for the MX53ARD Freescale board.
- */
-
-#ifndef __CONFIG_H
-#define __CONFIG_H
-
-#define CONFIG_MACH_TYPE MACH_TYPE_MX53_ARD
-
-#include <asm/arch/imx-regs.h>
-
-#define CONFIG_CMDLINE_TAG /* enable passing of ATAGs */
-#define CONFIG_SETUP_MEMORY_TAGS
-#define CONFIG_INITRD_TAG
-#define CONFIG_REVISION_TAG
-
-#define CONFIG_SYS_FSL_CLK
-
-/* Size of malloc() pool */
-#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 2 * 1024 * 1024)
-
-#define CONFIG_SYS_MAX_NAND_DEVICE 1
-#define CONFIG_SYS_NAND_BASE NFC_BASE_ADDR_AXI
-#define CONFIG_MXC_NAND_REGS_BASE NFC_BASE_ADDR_AXI
-#define CONFIG_MXC_NAND_IP_REGS_BASE NFC_BASE_ADDR
-#define CONFIG_SYS_NAND_LARGEPAGE
-#define CONFIG_MXC_NAND_HWECC
-
-#define CONFIG_MXC_UART_BASE UART1_BASE
-
-/* I2C Configs */
-#define CONFIG_SYS_I2C
-#define CONFIG_SYS_I2C_MXC
-#define CONFIG_SYS_I2C_MXC_I2C1 /* enable I2C bus 1 */
-#define CONFIG_SYS_I2C_MXC_I2C2 /* enable I2C bus 2 */
-#define CONFIG_SYS_I2C_MXC_I2C3 /* enable I2C bus 3 */
-
-/* MMC Configs */
-#define CONFIG_SYS_FSL_ESDHC_ADDR 0
-#define CONFIG_SYS_FSL_ESDHC_NUM 2
-
-/* Eth Configs */
-#define CONFIG_HAS_ETH1
-
-/* Command definition */
-
-#define CONFIG_ETHPRIME "smc911x"
-
-#define CONFIG_LOADADDR 0x72000000 /* loadaddr env var */
-
-#define CONFIG_EXTRA_ENV_SETTINGS \
- "script=boot.scr\0" \
- "uimage=zImage\0" \
- "console=ttymxc0\0" \
- "fdt_high=0xffffffff\0" \
- "initrd_high=0xffffffff\0" \
- "fdt_file=" CONFIG_DEFAULT_FDT_FILE "\0" \
- "fdt_addr=0x78000000\0" \
- "boot_fdt=try\0" \
- "ip_dyn=yes\0" \
- "mmcdev=" __stringify(CONFIG_SYS_MMC_ENV_DEV) "\0" \
- "mmcpart=1\0" \
- "mmcroot=/dev/mmcblk0p2 rootwait rw\0" \
- "update_sd_firmware_filename=u-boot.imx\0" \
- "update_sd_firmware=" \
- "if test ${ip_dyn} = yes; then " \
- "setenv get_cmd dhcp; " \
- "else " \
- "setenv get_cmd tftp; " \
- "fi; " \
- "if mmc dev ${mmcdev}; then " \
- "if ${get_cmd} ${update_sd_firmware_filename}; then " \
- "setexpr fw_sz ${filesize} / 0x200; " \
- "setexpr fw_sz ${fw_sz} + 1; " \
- "mmc write ${loadaddr} 0x2 ${fw_sz}; " \
- "fi; " \
- "fi\0" \
- "mmcargs=setenv bootargs console=${console},${baudrate} " \
- "root=${mmcroot}\0" \
- "loadbootscript=" \
- "fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${script};\0" \
- "bootscript=echo Running bootscript from mmc ...; " \
- "source\0" \
- "loaduimage=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${uimage}\0" \
- "loadfdt=fatload mmc ${mmcdev}:${mmcpart} ${fdt_addr} ${fdt_file}\0" \
- "mmcboot=echo Booting from mmc ...; " \
- "run mmcargs; " \
- "if test ${boot_fdt} = yes || test ${boot_fdt} = try; then " \
- "if run loadfdt; then " \
- "bootz ${loadaddr} - ${fdt_addr}; " \
- "else " \
- "if test ${boot_fdt} = try; then " \
- "bootz; " \
- "else " \
- "echo WARN: Cannot load the DT; " \
- "fi; " \
- "fi; " \
- "else " \
- "bootz; " \
- "fi;\0" \
- "netargs=setenv bootargs console=${console},${baudrate} " \
- "root=/dev/nfs " \
- "ip=dhcp nfsroot=${serverip}:${nfsroot},v3,tcp\0" \
- "netboot=echo Booting from net ...; " \
- "run netargs; " \
- "if test ${ip_dyn} = yes; then " \
- "setenv get_cmd dhcp; " \
- "else " \
- "setenv get_cmd tftp; " \
- "fi; " \
- "${get_cmd} ${uimage}; " \
- "if test ${boot_fdt} = yes || test ${boot_fdt} = try; then " \
- "if ${get_cmd} ${fdt_addr} ${fdt_file}; then " \
- "bootz ${loadaddr} - ${fdt_addr}; " \
- "else " \
- "if test ${boot_fdt} = try; then " \
- "bootz; " \
- "else " \
- "echo WARN: Cannot load the DT; " \
- "fi; " \
- "fi; " \
- "else " \
- "bootz; " \
- "fi;\0"
-
-#define CONFIG_BOOTCOMMAND \
- "mmc dev ${mmcdev}; if mmc rescan; then " \
- "if run loadbootscript; then " \
- "run bootscript; " \
- "else " \
- "if run loaduimage; then " \
- "run mmcboot; " \
- "else run netboot; " \
- "fi; " \
- "fi; " \
- "else run netboot; fi"
-
-#define CONFIG_ARP_TIMEOUT 200UL
-
-/* Miscellaneous configurable options */
-
-#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR
-
-/* Physical Memory Map */
-#define PHYS_SDRAM_1 CSD0_BASE_ADDR
-#define PHYS_SDRAM_1_SIZE (512 * 1024 * 1024)
-#define PHYS_SDRAM_2 CSD1_BASE_ADDR
-#define PHYS_SDRAM_2_SIZE (512 * 1024 * 1024)
-#define PHYS_SDRAM_SIZE (PHYS_SDRAM_1_SIZE + PHYS_SDRAM_2_SIZE)
-
-#define CONFIG_SYS_SDRAM_BASE (PHYS_SDRAM_1)
-#define CONFIG_SYS_INIT_RAM_ADDR (IRAM_BASE_ADDR)
-#define CONFIG_SYS_INIT_RAM_SIZE (IRAM_SIZE)
-
-#define CONFIG_SYS_INIT_SP_OFFSET \
- (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
-#define CONFIG_SYS_INIT_SP_ADDR \
- (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET)
-
-/* environment organization */
-
-#define MX53ARD_CS1GCR1 (CSEN | DSZ(2))
-#define MX53ARD_CS1RCR1 (RCSN(2) | OEN (1) | RWSC(22))
-#define MX53ARD_CS1RCR2 RBEN(2)
-#define MX53ARD_CS1WCR1 (WCSN(2) | WEN(2) | WBEN(2) | WWSC(22))
-
-#endif /* __CONFIG_H */
diff --git a/include/configs/mx53loco.h b/include/configs/mx53loco.h
index a0dd33a..e5dc9ac 100644
--- a/include/configs/mx53loco.h
+++ b/include/configs/mx53loco.h
@@ -30,12 +30,6 @@
#define CONFIG_SYS_FSL_ESDHC_ADDR 0
#define CONFIG_SYS_FSL_ESDHC_NUM 2
-/* Eth Configs */
-
-#define CONFIG_FEC_MXC
-#define IMX_FEC_BASE FEC_BASE_ADDR
-#define CONFIG_FEC_MXC_PHYADDR 0x1F
-
/* USB Configs */
#define CONFIG_MXC_USB_PORT 1
#define CONFIG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW)
diff --git a/include/configs/mx53smd.h b/include/configs/mx53smd.h
deleted file mode 100644
index 79c8672..0000000
--- a/include/configs/mx53smd.h
+++ /dev/null
@@ -1,111 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0+ */
-/*
- * Copyright (C) 2011 Freescale Semiconductor, Inc.
- *
- * Configuration settings for the MX53SMD Freescale board.
- */
-
-#ifndef __CONFIG_H
-#define __CONFIG_H
-
-#define CONFIG_MACH_TYPE MACH_TYPE_MX53_SMD
-
-#include <asm/arch/imx-regs.h>
-
-#define CONFIG_CMDLINE_TAG /* enable passing of ATAGs */
-#define CONFIG_SETUP_MEMORY_TAGS
-#define CONFIG_INITRD_TAG
-#define CONFIG_REVISION_TAG
-
-#define CONFIG_SYS_FSL_CLK
-
-/* Size of malloc() pool */
-#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 2 * 1024 * 1024)
-
-#define CONFIG_MXC_UART_BASE UART1_BASE
-
-/* I2C Configs */
-#define CONFIG_SYS_I2C
-#define CONFIG_SYS_I2C_MXC
-#define CONFIG_SYS_I2C_MXC_I2C1 /* enable I2C bus 1 */
-#define CONFIG_SYS_I2C_MXC_I2C2 /* enable I2C bus 2 */
-#define CONFIG_SYS_I2C_MXC_I2C3 /* enable I2C bus 3 */
-
-/* MMC Configs */
-#define CONFIG_SYS_FSL_ESDHC_ADDR 0
-#define CONFIG_SYS_FSL_ESDHC_NUM 1
-
-/* Eth Configs */
-#define CONFIG_HAS_ETH1
-
-#define CONFIG_FEC_MXC
-#define IMX_FEC_BASE FEC_BASE_ADDR
-#define CONFIG_FEC_MXC_PHYADDR 0x1F
-
-/* Command definition */
-
-#define CONFIG_ETHPRIME "FEC0"
-
-#define CONFIG_LOADADDR 0x70800000 /* loadaddr env var */
-
-#define CONFIG_EXTRA_ENV_SETTINGS \
- "script=boot.scr\0" \
- "uimage=uImage\0" \
- "mmcdev=0\0" \
- "mmcpart=2\0" \
- "mmcroot=/dev/mmcblk0p3 rw\0" \
- "mmcrootfstype=ext3 rootwait\0" \
- "mmcargs=setenv bootargs console=ttymxc0,${baudrate} " \
- "root=${mmcroot} " \
- "rootfstype=${mmcrootfstype}\0" \
- "loadbootscript=" \
- "fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${script};\0" \
- "bootscript=echo Running bootscript from mmc ...; " \
- "source\0" \
- "loaduimage=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${uimage}\0" \
- "mmcboot=echo Booting from mmc ...; " \
- "run mmcargs; " \
- "bootm\0" \
- "netargs=setenv bootargs console=ttymxc0,${baudrate} " \
- "root=/dev/nfs " \
- "ip=dhcp nfsroot=${serverip}:${nfsroot},v3,tcp\0" \
- "netboot=echo Booting from net ...; " \
- "run netargs; " \
- "dhcp ${uimage}; bootm\0" \
-
-#define CONFIG_BOOTCOMMAND \
- "mmc dev ${mmcdev}; if mmc rescan; then " \
- "if run loadbootscript; then " \
- "run bootscript; " \
- "else " \
- "if run loaduimage; then " \
- "run mmcboot; " \
- "else run netboot; " \
- "fi; " \
- "fi; " \
- "else run netboot; fi"
-#define CONFIG_ARP_TIMEOUT 200UL
-
-/* Miscellaneous configurable options */
-
-#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR
-
-/* Physical Memory Map */
-#define PHYS_SDRAM_1 CSD0_BASE_ADDR
-#define PHYS_SDRAM_1_SIZE (512 * 1024 * 1024)
-#define PHYS_SDRAM_2 CSD1_BASE_ADDR
-#define PHYS_SDRAM_2_SIZE (512 * 1024 * 1024)
-#define PHYS_SDRAM_SIZE (PHYS_SDRAM_1_SIZE + PHYS_SDRAM_2_SIZE)
-
-#define CONFIG_SYS_SDRAM_BASE (PHYS_SDRAM_1)
-#define CONFIG_SYS_INIT_RAM_ADDR (IRAM_BASE_ADDR)
-#define CONFIG_SYS_INIT_RAM_SIZE (IRAM_SIZE)
-
-#define CONFIG_SYS_INIT_SP_OFFSET \
- (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
-#define CONFIG_SYS_INIT_SP_ADDR \
- (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET)
-
-/* environment organization */
-
-#endif /* __CONFIG_H */
diff --git a/include/configs/mx6sabre_common.h b/include/configs/mx6sabre_common.h
index 93d00a4..ac579f3 100644
--- a/include/configs/mx6sabre_common.h
+++ b/include/configs/mx6sabre_common.h
@@ -73,11 +73,14 @@
"mmcargs=setenv bootargs console=${console},${baudrate} " \
"root=PARTUUID=${uuid} rootwait rw\0" \
"loadbootscript=" \
- "fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${script};\0" \
+ "load mmc ${mmcdev}:${mmcpart} ${loadaddr} ${script} || " \
+ "load mmc ${mmcdev}:${mmcpart} ${loadaddr} boot/${script};\0" \
"bootscript=echo Running bootscript from mmc ...; " \
"source\0" \
- "loadimage=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${image}\0" \
- "loadfdt=fatload mmc ${mmcdev}:${mmcpart} ${fdt_addr} ${fdtfile}\0" \
+ "loadimage=load mmc ${mmcdev}:${mmcpart} ${loadaddr} ${image} || " \
+ "load mmc ${mmcdev}:${mmcpart} ${loadaddr} boot/${image}\0" \
+ "loadfdt=load mmc ${mmcdev}:${mmcpart} ${fdt_addr} ${fdtfile} || " \
+ "load mmc ${mmcdev}:${mmcpart} ${fdt_addr} boot/${fdtfile}\0" \
"mmcboot=echo Booting from mmc ...; " \
"run finduuid; " \
"run mmcargs; " \
diff --git a/include/configs/nokia_rx51.h b/include/configs/nokia_rx51.h
index 3f2700d..23368de 100644
--- a/include/configs/nokia_rx51.h
+++ b/include/configs/nokia_rx51.h
@@ -70,10 +70,12 @@
/* USB device configuration */
#define CONFIG_USB_DEVICE
+#define CONFIG_USB_TTY
#define CONFIG_USBD_VENDORID 0x0421
-#define CONFIG_USBD_PRODUCTID 0x01c8
+#define CONFIG_USBD_PRODUCTID_CDCACM 0x01c8
+#define CONFIG_USBD_PRODUCTID_GSERIAL 0x01c8
#define CONFIG_USBD_MANUFACTURER "Nokia"
-#define CONFIG_USBD_PRODUCT_NAME "N900"
+#define CONFIG_USBD_PRODUCT_NAME "N900 (U-Boot)"
#define GPIO_SLIDE 71
@@ -108,15 +110,9 @@
/* Environment information */
#define CONFIG_EXTRA_ENV_SETTINGS \
"usbtty=cdc_acm\0" \
- "stdin=serial,vga\0" \
- "stdout=serial,vga\0" \
- "stderr=serial,vga\0" \
- "setcon=setenv stdin ${con};" \
- "setenv stdout ${con};" \
- "setenv stderr ${con}\0" \
- "sercon=setenv con serial; run setcon\0" \
- "usbcon=setenv con usbtty; run setcon\0" \
- "vgacon=setenv con vga; run setcon\0" \
+ "stdin=usbtty,serial,vga\0" \
+ "stdout=usbtty,serial,vga\0" \
+ "stderr=usbtty,serial,vga\0" \
"slide=gpio input " __stringify(GPIO_SLIDE) "\0" \
"switchmmc=mmc dev ${mmcnum}\0" \
"kernaddr=0x82008000\0" \
@@ -198,9 +194,6 @@
#define CONFIG_POSTBOOTMENU \
"echo;" \
"echo Extra commands:;" \
- "echo run sercon - Use serial port for control.;" \
- "echo run usbcon - Use usbtty for control.;" \
- "echo run vgacon - Use framebuffer/keyboard.;" \
"echo run sdboot - Boot from SD card slot.;" \
"echo run emmcboot - Boot internal eMMC memory.;" \
"echo run attachboot - Boot attached kernel image.;" \
diff --git a/include/configs/qemu-ppce500.h b/include/configs/qemu-ppce500.h
index ee6ef18..b2e1204 100644
--- a/include/configs/qemu-ppce500.h
+++ b/include/configs/qemu-ppce500.h
@@ -13,8 +13,6 @@
#define CONFIG_SYS_RAMBOOT
-#define CONFIG_PCI1 1 /* PCI controller 1 */
-#define CONFIG_FSL_PCI_INIT /* Use common FSL init code */
#define CONFIG_SYS_PCI_64BIT /* enable 64-bit PCI resources */
#define CONFIG_ENABLE_36BIT_PHYS
@@ -35,7 +33,7 @@
/* Virtual address range for PCI region maps */
#define CONFIG_SYS_PCI_MAP_START 0x80000000
-#define CONFIG_SYS_PCI_MAP_END 0xe8000000
+#define CONFIG_SYS_PCI_MAP_END 0xe0000000
/* Virtual address to a temporary map if we need it (max 128MB) */
#define CONFIG_SYS_TMPVIRT 0xe8000000
@@ -73,29 +71,11 @@
#define CONFIG_SYS_MONITOR_LEN (512 * 1024)
#define CONFIG_SYS_MALLOC_LEN (4 * 1024 * 1024)
-#define CONFIG_SYS_NS16550_SERIAL
-#define CONFIG_SYS_NS16550_REG_SIZE 1
-#define CONFIG_SYS_NS16550_CLK (get_bus_freq(0))
-
-#define CONFIG_SYS_BAUDRATE_TABLE \
- {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
-
-#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x4500)
-#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x4600)
-
-/*
- * General PCI
- * Memory space is mapped 1-1, but I/O space must start from 0.
- */
-
-#ifdef CONFIG_PCI
-#define CONFIG_PCI_INDIRECT_BRIDGE
-
-#define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
-#endif /* CONFIG_PCI */
-
#define CONFIG_LBA48
+/* RTC */
+#define CONFIG_RTC_PT7C4338
+
/*
* Environment
*/
@@ -126,6 +106,6 @@
#define CONFIG_LOADADDR 1000000
#define CONFIG_BOOTCOMMAND \
- "test -n \"$qemu_kernel_addr\" && bootm $qemu_kernel_addr - $fdt_addr_r\0"
+ "test -n \"$qemu_kernel_addr\" && bootm $qemu_kernel_addr - $fdtcontroladdr\0"
#endif /* __QEMU_PPCE500_H */
diff --git a/include/configs/sksimx6.h b/include/configs/sksimx6.h
deleted file mode 100644
index 7052d80..0000000
--- a/include/configs/sksimx6.h
+++ /dev/null
@@ -1,85 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0+ */
-/*
- * Copyright (C) Stefano Babic <sbabic@denx.de>
- */
-
-
-#ifndef __SKSIMX6_CONFIG_H
-#define __SKSIMX6_CONFIG_H
-
-#include "mx6_common.h"
-#include "imx6_spl.h"
-
-/* Serial */
-#define CONFIG_MXC_UART_BASE UART1_BASE
-
-/* Size of malloc() pool */
-#define CONFIG_SYS_MALLOC_LEN (8 * SZ_1M)
-
-/* Ethernet */
-#define IMX_FEC_BASE ENET_BASE_ADDR
-#define CONFIG_FEC_XCV_TYPE RGMII
-#define CONFIG_ETHPRIME "FEC"
-#define CONFIG_FEC_MXC_PHYADDR 0x01
-
-#define CONFIG_PHY_MICREL_KSZ9021
-
-/* I2C Configs */
-#define CONFIG_SYS_I2C
-#define CONFIG_SYS_I2C_MXC
-#define CONFIG_SYS_I2C_MXC_I2C2
-#define CONFIG_SYS_I2C_SPEED 100000
-
-/* Filesystem support */
-
-/* Physical Memory Map */
-#define PHYS_SDRAM MMDC0_ARB_BASE_ADDR
-
-#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM
-#define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR
-#define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE
-
-#define CONFIG_SYS_INIT_SP_OFFSET \
- (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
-#define CONFIG_SYS_INIT_SP_ADDR \
- (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET)
-
-/* MMC Configs */
-#define CONFIG_SYS_FSL_ESDHC_ADDR 0
-#define CONFIG_SYS_FSL_USDHC_NUM 1
-
-/* Environment organization */
-
-/* Default environment */
-#define CONFIG_EXTRA_ENV_SETTINGS \
- "addcons=setenv bootargs ${bootargs} " \
- "console=${console},${baudrate}\0" \
- "addip=setenv bootargs ${bootargs} " \
- "ip=${ipaddr}:${serverip}:${gatewayip}:" \
- "${netmask}:${hostname}:${netdev}:off\0" \
- "addmisc=setenv bootargs ${bootargs} ${miscargs}\0" \
- "bootcmd=run mmcboot\0" \
- "bootfile=uImage\0" \
- "bootimage=uImage\0" \
- "console=ttymxc0\0" \
- "fdt_addr_r=0x18000000\0" \
- "fdt_file=imx6dl-sks-cts.dtb\0" \
- "fdt_high=0xffffffff\0" \
- "kernel_addr_r=" __stringify(CONFIG_LOADADDR) "\0" \
- "miscargs=quiet\0" \
- "mmcargs=setenv bootargs root=${mmcroot} rw rootwait\0" \
- "mmcboot=if run mmcload;then " \
- "run mmcargs addcons addmisc;" \
- "bootm;fi\0" \
- "mmcload=mmc rescan;" \
- "load mmc 0:${mmcpart} ${kernel_addr_r} boot/fitImage\0"\
- "mmcpart=1\0" \
- "mmcroot=/dev/mmcblk0p1\0" \
- "net_nfs=tftp ${kernel_addr_r} ${board_name}/${bootfile};" \
- "tftp ${fdt_addr_r} ${board_name}/${fdt_file};" \
- "run nfsargs addip addcons addmisc;" \
- "bootm ${kernel_addr_r} - ${fdt_addr_r}\0" \
- "nfsargs=setenv bootargs root=/dev/nfs " \
- "nfsroot=${serverip}:${nfsroot},v3 panic=1\0"
-
-#endif
diff --git a/include/configs/socfpga_soc64_common.h b/include/configs/socfpga_soc64_common.h
index fdcd7d3..1cfa190 100644
--- a/include/configs/socfpga_soc64_common.h
+++ b/include/configs/socfpga_soc64_common.h
@@ -79,19 +79,13 @@
#endif /* CONFIG_CADENCE_QSPI */
/*
- * Boot arguments passed to the boot command. The value of
- * CONFIG_BOOTARGS goes into the environment value "bootargs".
- * Do note the value will override also the chosen node in FDT blob.
+ * Environment variable
*/
#ifdef CONFIG_FIT
#define CONFIG_BOOTFILE "kernel.itb"
-#define CONFIG_BOOTCOMMAND "run fatscript; run mmcfitload;run linux_qspi_enable;" \
- "run mmcfitboot"
#else
#define CONFIG_BOOTFILE "Image"
-#define CONFIG_BOOTCOMMAND "run fatscript; run mmcload;run linux_qspi_enable;" \
- "run mmcboot"
#endif
#define CONFIG_EXTRA_ENV_SETTINGS \
@@ -200,7 +194,7 @@
* 0x8000_0000 ...... End of SDRAM_1 (assume 2GB)
*
*/
-#define CONFIG_SPL_TARGET "spl/u-boot-spl.hex"
+#define CONFIG_SPL_TARGET "spl/u-boot-spl-dtb.hex"
#define CONFIG_SPL_MAX_SIZE CONFIG_SYS_INIT_RAM_SIZE
#define CONFIG_SPL_STACK CONFIG_SYS_INIT_SP_ADDR
#define CONFIG_SPL_BSS_MAX_SIZE 0x100000 /* 1 MB */
diff --git a/include/configs/stm32mp1.h b/include/configs/stm32mp1.h
index c553928..db2117a 100644
--- a/include/configs/stm32mp1.h
+++ b/include/configs/stm32mp1.h
@@ -102,11 +102,18 @@
#define BOOT_TARGET_UBIFS(func)
#endif
+#ifdef CONFIG_USB
+#define BOOT_TARGET_USB(func) func(USB, usb, 0)
+#else
+#define BOOT_TARGET_USB(func)
+#endif
+
#define BOOT_TARGET_DEVICES(func) \
BOOT_TARGET_MMC1(func) \
BOOT_TARGET_UBIFS(func) \
BOOT_TARGET_MMC0(func) \
BOOT_TARGET_MMC2(func) \
+ BOOT_TARGET_USB(func) \
BOOT_TARGET_PXE(func)
/*
@@ -153,7 +160,6 @@
* and the ramdisk at the end.
*/
#define CONFIG_EXTRA_ENV_SETTINGS \
- "bootdelay=1\0" \
"kernel_addr_r=0xc2000000\0" \
"fdt_addr_r=0xc4000000\0" \
"scriptaddr=0xc4100000\0" \
diff --git a/include/configs/vexpress_aemv8a.h b/include/configs/vexpress_aemv8a.h
index 566bee5..7318fb6 100644
--- a/include/configs/vexpress_aemv8a.h
+++ b/include/configs/vexpress_aemv8a.h
@@ -117,6 +117,9 @@
#ifdef CONFIG_TARGET_VEXPRESS64_JUNO
#define PHYS_SDRAM_2 (0x880000000)
#define PHYS_SDRAM_2_SIZE 0x180000000
+#elif CONFIG_TARGET_VEXPRESS64_BASE_FVP && CONFIG_NR_DRAM_BANKS == 2
+#define PHYS_SDRAM_2 (0x880000000)
+#define PHYS_SDRAM_2_SIZE 0x80000000
#endif
/* Enable memtest */
diff --git a/include/efi_loader.h b/include/efi_loader.h
index f470bbd..68daa1a 100644
--- a/include/efi_loader.h
+++ b/include/efi_loader.h
@@ -242,7 +242,7 @@
* @link: link to the list of protocols of a handle
* @guid: GUID of the protocol
* @protocol_interface: protocol interface
- * @open_infos link to the list of open protocol info items
+ * @open_infos: link to the list of open protocol info items
*/
struct efi_handler {
struct list_head link;
@@ -258,9 +258,13 @@
* started image.
*/
enum efi_object_type {
+ /** @EFI_OBJECT_TYPE_UNDEFINED: undefined image type */
EFI_OBJECT_TYPE_UNDEFINED = 0,
+ /** @EFI_OBJECT_TYPE_U_BOOT_FIRMWARE: U-Boot firmware */
EFI_OBJECT_TYPE_U_BOOT_FIRMWARE,
+ /** @EFI_OBJECT_TYPE_LOADED_IMAGE: loaded image (not started) */
EFI_OBJECT_TYPE_LOADED_IMAGE,
+ /** @EFI_OBJECT_TYPE_STARTED_IMAGE: started image */
EFI_OBJECT_TYPE_STARTED_IMAGE,
};
@@ -270,6 +274,7 @@
* @link: pointers to put the handle into a linked list
* @protocols: linked list with the protocol interfaces installed on this
* handle
+ * @type: image type if the handle relates to an image
*
* UEFI offers a flexible and expandable object model. The objects in the UEFI
* API are devices, drivers, and loaded images. struct efi_object is our storage
@@ -325,7 +330,7 @@
* @queue_link: Link to the list of queued events
* @type: Type of event, see efi_create_event
* @notify_tpl: Task priority level of notifications
- * @nofify_function: Function to call when the event is triggered
+ * @notify_function: Function to call when the event is triggered
* @notify_context: Data to be passed to the notify function
* @group: Event group
* @trigger_time: Period of the timer
@@ -368,7 +373,8 @@
};
/**
- * efi_register_notify_event - event registered by RegisterProtocolNotify()
+ * struct efi_register_notify_event - event registered by
+ * RegisterProtocolNotify()
*
* The address of this structure serves as registration value.
*
@@ -747,7 +753,7 @@
efi_status_t efi_bootmgr_load(efi_handle_t *handle, void **load_options);
/**
- * efi_image_regions - A list of memory regions
+ * struct efi_image_regions - A list of memory regions
*
* @max: Maximum number of regions
* @num: Number of regions
@@ -760,13 +766,13 @@
};
/**
- * efi_sig_data - A decoded data of struct efi_signature_data
+ * struct efi_sig_data - A decoded data of struct efi_signature_data
*
* This structure represents an internal form of signature in
* signature database. A listed list may represent a signature list.
*
* @next: Pointer to next entry
- * @onwer: Signature owner
+ * @owner: Signature owner
* @data: Pointer to signature data
* @size: Size of signature data
*/
@@ -778,7 +784,7 @@
};
/**
- * efi_signature_store - A decoded data of signature database
+ * struct efi_signature_store - A decoded data of signature database
*
* This structure represents an internal form of signature database.
*
diff --git a/include/fastboot.h b/include/fastboot.h
index 797d7df..57daaf1 100644
--- a/include/fastboot.h
+++ b/include/fastboot.h
@@ -44,6 +44,10 @@
#if CONFIG_IS_ENABLED(FASTBOOT_CMD_OEM_BOOTBUS)
FASTBOOT_COMMAND_OEM_BOOTBUS,
#endif
+#if CONFIG_IS_ENABLED(FASTBOOT_UUU_SUPPORT)
+ FASTBOOT_COMMAND_ACMD,
+ FASTBOOT_COMMAND_UCMD,
+#endif
FASTBOOT_COMMAND_COUNT
};
@@ -169,4 +173,7 @@
*/
void fastboot_data_complete(char *response);
+#if CONFIG_IS_ENABLED(FASTBOOT_UUU_SUPPORT)
+void fastboot_acmd_complete(void);
+#endif
#endif /* _FASTBOOT_H_ */
diff --git a/include/image.h b/include/image.h
index 138c83d..b4b284d 100644
--- a/include/image.h
+++ b/include/image.h
@@ -1158,7 +1158,7 @@
* @fit: pointer to the FIT format image header
* @return 0 if OK, -ENOEXEC if not an FDT file, -EINVAL if the full FDT check
* failed (e.g. due to bad structure), -ENOMSG if the description is
- * missing, -ENODATA if the timestamp is missing, -ENOENT if the /images
+ * missing, -EBADMSG if the timestamp is missing, -ENOENT if the /images
* path is missing
*/
int fit_check_format(const void *fit, ulong size);
diff --git a/include/linux/bitops.h b/include/linux/bitops.h
index 16f2899..d2e5ca0 100644
--- a/include/linux/bitops.h
+++ b/include/linux/bitops.h
@@ -6,7 +6,6 @@
#include <asm/types.h>
#include <asm-generic/bitsperlong.h>
#include <linux/compiler.h>
-#include <linux/kernel.h>
#ifdef __KERNEL__
#define BIT(nr) (1UL << (nr))
@@ -19,6 +18,9 @@
#define BITS_TO_LONGS(nr) DIV_ROUND_UP(nr, BITS_PER_BYTE * sizeof(long))
#endif
+/* kernel.h includes log.h which include bitops.h */
+#include <linux/kernel.h>
+
/*
* Create a contiguous bitmask starting at bit position @l and ending at
* position @h. For example
diff --git a/include/linux/mtd/spi-nor.h b/include/linux/mtd/spi-nor.h
index 4a8e19e..c3e38e4 100644
--- a/include/linux/mtd/spi-nor.h
+++ b/include/linux/mtd/spi-nor.h
@@ -48,13 +48,13 @@
#define SPINOR_OP_READ_1_2_2 0xbb /* Read data bytes (Dual I/O SPI) */
#define SPINOR_OP_READ_1_1_4 0x6b /* Read data bytes (Quad Output SPI) */
#define SPINOR_OP_READ_1_4_4 0xeb /* Read data bytes (Quad I/O SPI) */
-#define SPINOR_OP_READ_1_1_8 0x8b /* Read data bytes (Octal Output SPI) */
-#define SPINOR_OP_READ_1_8_8 0xcb /* Read data bytes (Octal I/O SPI) */
+#define SPINOR_OP_READ_1_1_8 0x8b /* Read data bytes (Octal Output SPI) */
+#define SPINOR_OP_READ_1_8_8 0xcb /* Read data bytes (Octal I/O SPI) */
#define SPINOR_OP_PP 0x02 /* Page program (up to 256 bytes) */
#define SPINOR_OP_PP_1_1_4 0x32 /* Quad page program */
#define SPINOR_OP_PP_1_4_4 0x38 /* Quad page program */
-#define SPINOR_OP_PP_1_1_8 0x82 /* Octal page program */
-#define SPINOR_OP_PP_1_8_8 0xc2 /* Octal page program */
+#define SPINOR_OP_PP_1_1_8 0x82 /* Octal page program */
+#define SPINOR_OP_PP_1_8_8 0xc2 /* Octal page program */
#define SPINOR_OP_BE_4K 0x20 /* Erase 4KiB block */
#define SPINOR_OP_BE_4K_PMC 0xd7 /* Erase 4KiB block on PMC chips */
#define SPINOR_OP_BE_32K 0x52 /* Erase 32KiB block */
@@ -75,13 +75,13 @@
#define SPINOR_OP_READ_1_2_2_4B 0xbc /* Read data bytes (Dual I/O SPI) */
#define SPINOR_OP_READ_1_1_4_4B 0x6c /* Read data bytes (Quad Output SPI) */
#define SPINOR_OP_READ_1_4_4_4B 0xec /* Read data bytes (Quad I/O SPI) */
-#define SPINOR_OP_READ_1_1_8_4B 0x7c /* Read data bytes (Octal Output SPI) */
-#define SPINOR_OP_READ_1_8_8_4B 0xcc /* Read data bytes (Octal I/O SPI) */
+#define SPINOR_OP_READ_1_1_8_4B 0x7c /* Read data bytes (Octal Output SPI) */
+#define SPINOR_OP_READ_1_8_8_4B 0xcc /* Read data bytes (Octal I/O SPI) */
#define SPINOR_OP_PP_4B 0x12 /* Page program (up to 256 bytes) */
#define SPINOR_OP_PP_1_1_4_4B 0x34 /* Quad page program */
#define SPINOR_OP_PP_1_4_4_4B 0x3e /* Quad page program */
-#define SPINOR_OP_PP_1_1_8_4B 0x84 /* Octal page program */
-#define SPINOR_OP_PP_1_8_8_4B 0x8e /* Octal page program */
+#define SPINOR_OP_PP_1_1_8_4B 0x84 /* Octal page program */
+#define SPINOR_OP_PP_1_8_8_4B 0x8e /* Octal page program */
#define SPINOR_OP_BE_4K_4B 0x21 /* Erase 4KiB block */
#define SPINOR_OP_BE_32K_4B 0x5c /* Erase 32KiB block */
#define SPINOR_OP_SE_4B 0xdc /* Sector erase (usually 64KiB) */
@@ -122,8 +122,8 @@
#define SPINOR_OP_CLSR 0x30 /* Clear status register 1 */
/* Used for Micron flashes only. */
-#define SPINOR_OP_RD_EVCR 0x65 /* Read EVCR register */
-#define SPINOR_OP_WD_EVCR 0x61 /* Write EVCR register */
+#define SPINOR_OP_RD_EVCR 0x65 /* Read EVCR register */
+#define SPINOR_OP_WD_EVCR 0x61 /* Write EVCR register */
/* Status Register bits. */
#define SR_WIP BIT(0) /* Write in progress */
@@ -302,8 +302,8 @@
* @flash_lock: [FLASH-SPECIFIC] lock a region of the SPI NOR
* @flash_unlock: [FLASH-SPECIFIC] unlock a region of the SPI NOR
* @flash_is_locked: [FLASH-SPECIFIC] check if a region of the SPI NOR is
- * @quad_enable: [FLASH-SPECIFIC] enables SPI NOR quad mode
* completely locked
+ * @quad_enable: [FLASH-SPECIFIC] enables SPI NOR quad mode
* @priv: the private data
*/
struct spi_nor {
diff --git a/include/linux/printk.h b/include/linux/printk.h
index 088513a..5e85513 100644
--- a/include/linux/printk.h
+++ b/include/linux/printk.h
@@ -1,6 +1,7 @@
#ifndef __KERNEL_PRINTK__
#define __KERNEL_PRINTK__
+#include <log.h>
#include <stdio.h>
#include <linux/compiler.h>
@@ -28,49 +29,56 @@
0; \
})
-#define __printk(level, fmt, ...) \
-({ \
- level < CONFIG_LOGLEVEL ? printk(fmt, ##__VA_ARGS__) : 0; \
-})
-
#ifndef pr_fmt
#define pr_fmt(fmt) fmt
#endif
-#define pr_emerg(fmt, ...) \
- __printk(0, pr_fmt(fmt), ##__VA_ARGS__)
-#define pr_alert(fmt, ...) \
- __printk(1, pr_fmt(fmt), ##__VA_ARGS__)
-#define pr_crit(fmt, ...) \
- __printk(2, pr_fmt(fmt), ##__VA_ARGS__)
-#define pr_err(fmt, ...) \
- __printk(3, pr_fmt(fmt), ##__VA_ARGS__)
-#define pr_warning(fmt, ...) \
- __printk(4, pr_fmt(fmt), ##__VA_ARGS__)
-#define pr_warn pr_warning
-#define pr_notice(fmt, ...) \
- __printk(5, pr_fmt(fmt), ##__VA_ARGS__)
-#define pr_info(fmt, ...) \
- __printk(6, pr_fmt(fmt), ##__VA_ARGS__)
-
-#define pr_cont(fmt, ...) \
- printk(fmt, ##__VA_ARGS__)
-
-/* pr_devel() should produce zero code unless DEBUG is defined */
-#ifdef DEBUG
-#define pr_devel(fmt, ...) \
- __printk(7, pr_fmt(fmt), ##__VA_ARGS__)
-#else
-#define pr_devel(fmt, ...) \
- no_printk(pr_fmt(fmt), ##__VA_ARGS__)
-#endif
+#define pr_emerg(fmt, ...) \
+({ \
+ CONFIG_LOGLEVEL > 0 ? log_emerg(fmt, ##__VA_ARGS__) : 0; \
+})
+#define pr_alert(fmt, ...) \
+({ \
+ CONFIG_LOGLEVEL > 1 ? log_alert(fmt, ##__VA_ARGS__) : 0; \
+})
+#define pr_crit(fmt, ...) \
+({ \
+ CONFIG_LOGLEVEL > 2 ? log_crit(fmt, ##__VA_ARGS__) : 0; \
+})
+#define pr_err(fmt, ...) \
+({ \
+ CONFIG_LOGLEVEL > 3 ? log_err(fmt, ##__VA_ARGS__) : 0; \
+})
+#define pr_warn(fmt, ...) \
+({ \
+ CONFIG_LOGLEVEL > 4 ? log_warning(fmt, ##__VA_ARGS__) : 0; \
+})
+#define pr_notice(fmt, ...) \
+({ \
+ CONFIG_LOGLEVEL > 5 ? log_notice(fmt, ##__VA_ARGS__) : 0; \
+})
+#define pr_info(fmt, ...) \
+({ \
+ CONFIG_LOGLEVEL > 6 ? log_info(fmt, ##__VA_ARGS__) : 0; \
+})
+#define pr_debug(fmt, ...) \
+({ \
+ CONFIG_LOGLEVEL > 7 ? log_debug(fmt, ##__VA_ARGS__) : 0; \
+})
+#define pr_devel(fmt, ...) \
+({ \
+ CONFIG_LOGLEVEL > 7 ? log_debug(fmt, ##__VA_ARGS__) : 0; \
+})
-#ifdef DEBUG
-#define pr_debug(fmt, ...) \
- __printk(7, pr_fmt(fmt), ##__VA_ARGS__)
+#ifdef CONFIG_LOG
+#define pr_cont(fmt, ...) \
+({ \
+ gd->logl_prev < CONFIG_LOGLEVEL ? \
+ log_cont(fmt, ##__VA_ARGS__) : 0; \
+})
#else
-#define pr_debug(fmt, ...) \
- no_printk(pr_fmt(fmt), ##__VA_ARGS__)
+#define pr_cont(fmt, ...) \
+ printk(fmt, ##__VA_ARGS__)
#endif
#define printk_once(fmt, ...) \
diff --git a/include/malloc.h b/include/malloc.h
index f66c2e8..e15e528 100644
--- a/include/malloc.h
+++ b/include/malloc.h
@@ -361,8 +361,11 @@
#if (__STD_C || defined(HAVE_MEMCPY))
#if __STD_C
+/* U-Boot defines memset() and memcpy in /include/linux/string.h
void* memset(void*, int, size_t);
void* memcpy(void*, const void*, size_t);
+*/
+#include <linux/string.h>
#else
#ifdef WIN32
/* On Win32 platforms, 'memset()' and 'memcpy()' are already declared in */
diff --git a/include/part.h b/include/part.h
index 815515a..7f78271 100644
--- a/include/part.h
+++ b/include/part.h
@@ -227,12 +227,16 @@
* @param[in] dev_part_str Input partition description, like "0#misc" or "0:1"
* @param[out] dev_desc Place to store the device description pointer
* @param[out] part_info Place to store the partition information
+ * @param[in] allow_whole_dev true to allow the user to select partition 0
+ * (which means the whole device), false to require a valid
+ * partition number >= 1
* @return 0 on success, or a negative on error
*/
int part_get_info_by_dev_and_name_or_num(const char *dev_iface,
const char *dev_part_str,
struct blk_desc **dev_desc,
- struct disk_partition *part_info);
+ struct disk_partition *part_info,
+ int allow_whole_dev);
/**
* part_set_generic_name() - create generic partition like hda1 or sdb2
diff --git a/include/test/suites.h b/include/test/suites.h
index 52e8fc8..f5d8e13 100644
--- a/include/test/suites.h
+++ b/include/test/suites.h
@@ -26,6 +26,8 @@
struct unit_test *tests, int n_ents,
int argc, char *const argv[]);
+int do_ut_addrmap(struct cmd_tbl *cmdtp, int flag, int argc,
+ char *const argv[]);
int do_ut_bootm(struct cmd_tbl *cmdtp, int flag, int argc, char *const argv[]);
int do_ut_bloblist(struct cmd_tbl *cmdtp, int flag, int argc,
char *const argv[]);
diff --git a/include/u-boot/rsa-mod-exp.h b/include/u-boot/rsa-mod-exp.h
index 7b7c291..fc9557c 100644
--- a/include/u-boot/rsa-mod-exp.h
+++ b/include/u-boot/rsa-mod-exp.h
@@ -9,6 +9,8 @@
#include <errno.h>
#include <image.h>
+struct udevice;
+
/**
* struct key_prop - holder for a public key properties
*
diff --git a/lib/Kconfig b/lib/Kconfig
index b35a71a..7288340 100644
--- a/lib/Kconfig
+++ b/lib/Kconfig
@@ -6,6 +6,8 @@
Enables helper code for implementing non-identity virtual-physical
memory mappings for 32bit CPUs.
+ This library only works in the post-relocation phase.
+
config SYS_NUM_ADDR_MAP
int "Size of the address-map table"
depends on ADDR_MAP
@@ -22,7 +24,7 @@
config BINMAN_FDT
bool "Allow access to binman information in the device tree"
- depends on BINMAN && OF_CONTROL
+ depends on BINMAN && DM && OF_CONTROL
default y
help
This enables U-Boot to access information about binman entries,
diff --git a/lib/addr_map.c b/lib/addr_map.c
index 09771f3..fb2ef40 100644
--- a/lib/addr_map.c
+++ b/lib/addr_map.c
@@ -6,11 +6,7 @@
#include <common.h>
#include <addr_map.h>
-static struct {
- phys_addr_t paddr;
- phys_size_t size;
- unsigned long vaddr;
-} address_map[CONFIG_SYS_NUM_ADDR_MAP];
+struct addrmap address_map[CONFIG_SYS_NUM_ADDR_MAP];
phys_addr_t addrmap_virt_to_phys(void * vaddr)
{
diff --git a/lib/charset.c b/lib/charset.c
index 2177014..f44c58d 100644
--- a/lib/charset.c
+++ b/lib/charset.c
@@ -8,9 +8,16 @@
#include <common.h>
#include <charset.h>
#include <capitalization.h>
+#include <cp437.h>
#include <efi_loader.h>
+#include <errno.h>
#include <malloc.h>
+/**
+ * codepage_437 - Unicode to codepage 437 translation table
+ */
+const u16 codepage_437[128] = CP437;
+
static struct capitalization_table capitalization_table[] =
#ifdef CONFIG_EFI_UNICODE_CAPITALIZATION
UNICODE_CAPITALIZATION_TABLE;
@@ -25,7 +32,7 @@
*
* @read_u8: - stream reader
* @src: - string buffer passed to stream reader, optional
- * Return: - Unicode code point
+ * Return: - Unicode code point, or -1
*/
static int get_code(u8 (*read_u8)(void *data), void *data)
{
@@ -71,7 +78,7 @@
}
return ch;
error:
- return '?';
+ return -1;
}
/**
@@ -113,14 +120,21 @@
int console_read_unicode(s32 *code)
{
- if (!tstc()) {
- /* No input available */
- return 1;
- }
+ for (;;) {
+ s32 c;
- /* Read Unicode code */
- *code = get_code(read_console, NULL);
- return 0;
+ if (!tstc()) {
+ /* No input available */
+ return 1;
+ }
+
+ /* Read Unicode code */
+ c = get_code(read_console, NULL);
+ if (c > 0) {
+ *code = c;
+ return 0;
+ }
+ }
}
s32 utf8_get(const char **src)
@@ -466,3 +480,67 @@
return dest;
}
+
+int utf_to_cp(s32 *c, const u16 *codepage)
+{
+ if (*c >= 0x80) {
+ int j;
+
+ /* Look up codepage translation */
+ for (j = 0; j < 0x80; ++j) {
+ if (*c == codepage[j]) {
+ *c = j + 0x80;
+ return 0;
+ }
+ }
+ *c = '?';
+ return -ENOENT;
+ }
+ return 0;
+}
+
+int utf8_to_cp437_stream(u8 c, char *buffer)
+{
+ char *end;
+ const char *pos;
+ s32 s;
+ int ret;
+
+ for (;;) {
+ pos = buffer;
+ end = buffer + strlen(buffer);
+ *end++ = c;
+ *end = 0;
+ s = utf8_get(&pos);
+ if (s > 0) {
+ *buffer = 0;
+ ret = utf_to_cp(&s, codepage_437);
+ return s;
+ }
+ if (pos == end)
+ return 0;
+ *buffer = 0;
+ }
+}
+
+int utf8_to_utf32_stream(u8 c, char *buffer)
+{
+ char *end;
+ const char *pos;
+ s32 s;
+
+ for (;;) {
+ pos = buffer;
+ end = buffer + strlen(buffer);
+ *end++ = c;
+ *end = 0;
+ s = utf8_get(&pos);
+ if (s > 0) {
+ *buffer = 0;
+ return s;
+ }
+ if (pos == end)
+ return 0;
+ *buffer = 0;
+ }
+}
diff --git a/lib/efi_loader/Kconfig b/lib/efi_loader/Kconfig
index e729f72..634d3b1 100644
--- a/lib/efi_loader/Kconfig
+++ b/lib/efi_loader/Kconfig
@@ -281,7 +281,7 @@
config EFI_GRUB_ARM32_WORKAROUND
bool "Workaround for GRUB on 32bit ARM"
- default n if ARCH_QEMU
+ default n if ARCH_BCM283X || ARCH_SUNXI || ARCH_QEMU
default y
depends on ARM && !ARM64
help
diff --git a/lib/efi_loader/efi_acpi.c b/lib/efi_loader/efi_acpi.c
index 585b2d2..a62c340 100644
--- a/lib/efi_loader/efi_acpi.c
+++ b/lib/efi_loader/efi_acpi.c
@@ -25,7 +25,7 @@
/* Reserve 64kiB page for ACPI */
ret = efi_allocate_pages(EFI_ALLOCATE_MAX_ADDRESS,
- EFI_RUNTIME_SERVICES_DATA, 16, &acpi);
+ EFI_ACPI_RECLAIM_MEMORY, 16, &acpi);
if (ret != EFI_SUCCESS)
return ret;
@@ -34,7 +34,6 @@
* a 4k-aligned address, so it is safe to assume that
* write_acpi_tables() will write the table at that address.
*/
- assert(!(acpi & 0xf));
write_acpi_tables(acpi);
/* And expose them to our EFI payload */
diff --git a/lib/efi_loader/efi_capsule.c b/lib/efi_loader/efi_capsule.c
index b57f030..7ba1ced 100644
--- a/lib/efi_loader/efi_capsule.c
+++ b/lib/efi_loader/efi_capsule.c
@@ -449,7 +449,7 @@
unsigned int i;
efi_status_t ret;
- EFI_ENTRY("%p, %lu, %llu\n", capsule_header_array, capsule_count,
+ EFI_ENTRY("%p, %zu, %llu\n", capsule_header_array, capsule_count,
scatter_gather_list);
if (!capsule_count) {
@@ -509,7 +509,7 @@
unsigned int i;
efi_status_t ret;
- EFI_ENTRY("%p, %lu, %p, %p\n", capsule_header_array, capsule_count,
+ EFI_ENTRY("%p, %zu, %p, %p\n", capsule_header_array, capsule_count,
maximum_capsule_size, reset_type);
if (!maximum_capsule_size) {
diff --git a/lib/efi_loader/efi_console.c b/lib/efi_loader/efi_console.c
index edcfce7..c400355 100644
--- a/lib/efi_loader/efi_console.c
+++ b/lib/efi_loader/efi_console.c
@@ -311,7 +311,7 @@
const char *stdout_name = env_get("stdout");
int rows = 25, cols = 80;
- if (stdout_name && !strcmp(stdout_name, "vidconsole") &&
+ if (stdout_name && !strncmp(stdout_name, "vidconsole", 10) &&
IS_ENABLED(CONFIG_DM_VIDEO)) {
struct stdio_dev *stdout_dev =
stdio_get_by_name("vidconsole");
diff --git a/lib/efi_loader/efi_device_path_to_text.c b/lib/efi_loader/efi_device_path_to_text.c
index 81b8ac2..edc9fdc 100644
--- a/lib/efi_loader/efi_device_path_to_text.c
+++ b/lib/efi_loader/efi_device_path_to_text.c
@@ -67,7 +67,8 @@
s += sprintf(s, "VenHw(%pUl", &vdp->guid);
n = (int)vdp->dp.length - sizeof(struct efi_device_path_vendor);
- if (n > 0) {
+ /* Node must fit into MAX_NODE_LEN) */
+ if (n > 0 && n < MAX_NODE_LEN / 2 - 22) {
s += sprintf(s, ",");
for (i = 0; i < n; ++i)
s += sprintf(s, "%02x", vdp->vendor_data[i]);
@@ -251,7 +252,8 @@
s += sprintf(s, "VenMedia(%pUl", &vdp->guid);
n = (int)vdp->dp.length - sizeof(struct efi_device_path_vendor);
- if (n > 0) {
+ /* Node must fit into MAX_NODE_LEN) */
+ if (n > 0 && n < MAX_NODE_LEN / 2 - 24) {
s += sprintf(s, ",");
for (i = 0; i < n; ++i)
s += sprintf(s, "%02x", vdp->vendor_data[i]);
diff --git a/lib/efi_loader/efi_dt_fixup.c b/lib/efi_loader/efi_dt_fixup.c
index a4529ee..b6fe5d2 100644
--- a/lib/efi_loader/efi_dt_fixup.c
+++ b/lib/efi_loader/efi_dt_fixup.c
@@ -61,7 +61,7 @@
for (i = 0; i < nr_rsv; i++) {
if (fdt_get_mem_rsv(fdt, i, &addr, &size) != 0)
continue;
- efi_reserve_memory(addr, size, false);
+ efi_reserve_memory(addr, size, true);
}
/* process reserved-memory */
diff --git a/lib/efi_loader/efi_firmware.c b/lib/efi_loader/efi_firmware.c
index 5e401bb..7a3cca2 100644
--- a/lib/efi_loader/efi_firmware.c
+++ b/lib/efi_loader/efi_firmware.c
@@ -299,7 +299,7 @@
efi_status_t (*progress)(efi_uintn_t completion),
u16 **abort_reason)
{
- EFI_ENTRY("%p %d %p %ld %p %p %p\n", this, image_index, image,
+ EFI_ENTRY("%p %d %p %zd %p %p %p\n", this, image_index, image,
image_size, vendor_code, progress, abort_reason);
if (!image || image_index != 1)
@@ -414,7 +414,7 @@
efi_status_t status;
efi_uintn_t capsule_payload_size;
- EFI_ENTRY("%p %d %p %ld %p %p %p\n", this, image_index, image,
+ EFI_ENTRY("%p %d %p %zd %p %p %p\n", this, image_index, image,
image_size, vendor_code, progress, abort_reason);
if (!image)
diff --git a/lib/efi_loader/efi_unicode_collation.c b/lib/efi_loader/efi_unicode_collation.c
index f6c875b..36be798 100644
--- a/lib/efi_loader/efi_unicode_collation.c
+++ b/lib/efi_loader/efi_unicode_collation.c
@@ -23,7 +23,7 @@
static const u16 codepage[] = CP1250;
#else
/* Unicode code points for code page 437 characters 0x80 - 0xff */
-static const u16 codepage[] = CP437;
+static const u16 *codepage = codepage_437;
#endif
/* GUID of the EFI_UNICODE_COLLATION_PROTOCOL2 */
@@ -300,23 +300,10 @@
break;
}
c = utf_to_upper(c);
- if (c >= 0x80) {
- int j;
-
- /* Look for codepage translation */
- for (j = 0; j < 0x80; ++j) {
- if (c == codepage[j]) {
- c = j + 0x80;
- break;
- }
- }
- if (j >= 0x80) {
- c = '_';
- ret = true;
- }
- } else if (c && (c < 0x20 || strchr(illegal, c))) {
- c = '_';
+ if (utf_to_cp(&c, codepage) ||
+ (c && (c < 0x20 || strchr(illegal, c)))) {
ret = true;
+ c = '_';
}
fat[i] = c;
diff --git a/lib/efi_selftest/Makefile b/lib/efi_selftest/Makefile
index b02fd56..50de581 100644
--- a/lib/efi_selftest/Makefile
+++ b/lib/efi_selftest/Makefile
@@ -61,7 +61,6 @@
obj-$(CONFIG_EFI_LOADER_HII) += efi_selftest_hii.o
obj-$(CONFIG_EFI_RNG_PROTOCOL) += efi_selftest_rng.o
obj-$(CONFIG_EFI_GET_TIME) += efi_selftest_rtc.o
-obj-$(CONFIG_EFI_LOAD_FILE2_INITRD) += efi_selftest_load_initrd.o
obj-$(CONFIG_EFI_TCG2_PROTOCOL) += efi_selftest_tcg2.o
ifeq ($(CONFIG_GENERATE_ACPI_TABLE),)
diff --git a/lib/efi_selftest/efi_selftest_load_initrd.c b/lib/efi_selftest/efi_selftest_load_initrd.c
deleted file mode 100644
index f591dcd..0000000
--- a/lib/efi_selftest/efi_selftest_load_initrd.c
+++ /dev/null
@@ -1,221 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * efi_selftest_load_initrd
- *
- * Copyright (c) 2020 Ilias Apalodimas <ilias.apalodimas@linaro.org>
- *
- * This test checks the FileLoad2 protocol.
- * A known file is read from the file system and verified.
- *
- * An example usage - given a file image with a file system in partition 1
- * holding file initrd - is:
- *
- * * Configure the sandbox with
- *
- * CONFIG_EFI_SELFTEST=y
- * CONFIG_EFI_LOAD_FILE2_INITRD=y
- * CONFIG_EFI_INITRD_FILESPEC="host 0:1 initrd"
- *
- * * Run ./u-boot and execute
- *
- * host bind 0 image
- * setenv efi_selftest load initrd
- * bootefi selftest
- *
- * This would provide a test output like:
- *
- * Testing EFI API implementation
- *
- * Selected test: 'load initrd'
- *
- * Setting up 'load initrd'
- * Setting up 'load initrd' succeeded
- *
- * Executing 'load initrd'
- * Loaded 12378613 bytes
- * CRC32 2997478465
- *
- * Now the size and CRC32 can be compared to the provided file.
- */
-
-#include <efi_selftest.h>
-#include <efi_loader.h>
-#include <efi_load_initrd.h>
-
-static struct efi_boot_services *boottime;
-
-static struct efi_initrd_dp dp = {
- .vendor = {
- {
- DEVICE_PATH_TYPE_MEDIA_DEVICE,
- DEVICE_PATH_SUB_TYPE_VENDOR_PATH,
- sizeof(dp.vendor),
- },
- EFI_INITRD_MEDIA_GUID,
- },
- .end = {
- DEVICE_PATH_TYPE_END,
- DEVICE_PATH_SUB_TYPE_END,
- sizeof(dp.end),
- }
-};
-
-static struct efi_initrd_dp dp_invalid = {
- .vendor = {
- {
- DEVICE_PATH_TYPE_MEDIA_DEVICE,
- DEVICE_PATH_SUB_TYPE_VENDOR_PATH,
- sizeof(dp.vendor),
- },
- EFI_INITRD_MEDIA_GUID,
- },
- .end = {
- 0x8f, /* invalid */
- 0xfe, /* invalid */
- sizeof(dp.end),
- }
-};
-
-static int setup(const efi_handle_t handle,
- const struct efi_system_table *systable)
-{
- boottime = systable->boottime;
-
- return EFI_ST_SUCCESS;
-}
-
-static int execute(void)
-{
- struct efi_load_file_protocol *lf2;
- struct efi_device_path *dp2, *dp2_invalid;
- efi_status_t status;
- efi_handle_t handle;
- char buffer[64];
- efi_uintn_t buffer_size;
- void *buf;
- u32 crc32;
-
- memset(buffer, 0, sizeof(buffer));
-
- dp2 = (struct efi_device_path *)&dp;
- status = boottime->locate_device_path(&efi_guid_load_file2_protocol,
- &dp2, &handle);
- if (status != EFI_SUCCESS) {
- efi_st_error("Unable to locate device path\n");
- return EFI_ST_FAILURE;
- }
-
- status = boottime->handle_protocol(handle,
- &efi_guid_load_file2_protocol,
- (void **)&lf2);
- if (status != EFI_SUCCESS) {
- efi_st_error("Unable to locate protocol\n");
- return EFI_ST_FAILURE;
- }
-
- /* Case 1:
- * buffer_size can't be NULL
- * protocol can't be NULL
- */
- status = lf2->load_file(lf2, dp2, false, NULL, &buffer);
- if (status != EFI_INVALID_PARAMETER) {
- efi_st_error("Buffer size can't be NULL\n");
- return EFI_ST_FAILURE;
- }
- buffer_size = sizeof(buffer);
- status = lf2->load_file(NULL, dp2, false, &buffer_size, &buffer);
- if (status != EFI_INVALID_PARAMETER) {
- efi_st_error("Protocol can't be NULL\n");
- return EFI_ST_FAILURE;
- }
-
- /*
- * Case 2: Match end node type/sub-type on device path
- */
- dp2_invalid = (struct efi_device_path *)&dp_invalid;
- buffer_size = sizeof(buffer);
- status = lf2->load_file(lf2, dp2_invalid, false, &buffer_size, &buffer);
- if (status != EFI_INVALID_PARAMETER) {
- efi_st_error("Invalid device path type must return EFI_INVALID_PARAMETER\n");
- return EFI_ST_FAILURE;
- }
-
- status = lf2->load_file(lf2, dp2_invalid, false, &buffer_size, &buffer);
- if (status != EFI_INVALID_PARAMETER) {
- efi_st_error("Invalid device path sub-type must return EFI_INVALID_PARAMETER\n");
- return EFI_ST_FAILURE;
- }
-
- /*
- * Case 3:
- * BootPolicy 'true' must return EFI_UNSUPPORTED
- */
- buffer_size = sizeof(buffer);
- status = lf2->load_file(lf2, dp2, true, &buffer_size, &buffer);
- if (status != EFI_UNSUPPORTED) {
- efi_st_error("BootPolicy true must return EFI_UNSUPPORTED\n");
- return EFI_ST_FAILURE;
- }
-
- /*
- * Case: Pass buffer size as zero, firmware must return
- * EFI_BUFFER_TOO_SMALL and an appropriate size
- */
- buffer_size = 0;
- status = lf2->load_file(lf2, dp2, false, &buffer_size, NULL);
- if (status != EFI_BUFFER_TOO_SMALL || !buffer_size) {
- efi_st_printf("buffer_size: %u\n", (unsigned int)buffer_size);
- efi_st_printf("status: %x\n", (unsigned int)status);
- efi_st_error("Buffer size not updated\n");
- return EFI_ST_FAILURE;
- }
-
- /*
- * Case: Pass buffer size as smaller than the file_size,
- * firmware must return * EFI_BUFFER_TOO_SMALL and an appropriate size
- */
- buffer_size = 1;
- status = lf2->load_file(lf2, dp2, false, &buffer_size, &buffer);
- if (status != EFI_BUFFER_TOO_SMALL || buffer_size <= 1) {
- efi_st_error("Buffer size not updated\n");
- return EFI_ST_FAILURE;
- }
-
- status = boottime->allocate_pool(EFI_BOOT_SERVICES_DATA, buffer_size,
- &buf);
- if (status != EFI_SUCCESS) {
- efi_st_error("Cannot allocate buffer\n");
- return EFI_ST_FAILURE;
- }
-
- /* Case: Pass correct buffer, load the file and verify checksum*/
- status = lf2->load_file(lf2, dp2, false, &buffer_size, buf);
- if (status != EFI_SUCCESS) {
- efi_st_error("Loading initrd failed\n");
- return EFI_ST_FAILURE;
- }
-
- efi_st_printf("Loaded %u bytes\n", (unsigned int)buffer_size);
- status = boottime->calculate_crc32(buf, buffer_size, &crc32);
- if (status != EFI_SUCCESS) {
- efi_st_error("Could not determine CRC32\n");
- return EFI_ST_FAILURE;
- }
- efi_st_printf("CRC32 %.8x\n", (unsigned int)crc32);
-
- status = boottime->free_pool(buf);
- if (status != EFI_SUCCESS) {
- efi_st_error("Cannot free buffer\n");
- return EFI_ST_FAILURE;
- }
-
- return EFI_ST_SUCCESS;
-}
-
-EFI_UNIT_TEST(load_initrd) = {
- .name = "load initrd",
- .phase = EFI_EXECUTE_BEFORE_BOOTTIME_EXIT,
- .setup = setup,
- .execute = execute,
- .on_request = true,
-};
diff --git a/lib/efi_selftest/initrddump.c b/lib/efi_selftest/initrddump.c
index c23a05c..325951b 100644
--- a/lib/efi_selftest/initrddump.c
+++ b/lib/efi_selftest/initrddump.c
@@ -272,7 +272,7 @@
error(L"Out of memory\r\n");
return ret;
}
- *initrd = (void *)buffer;
+ *initrd = (void *)(uintptr_t)buffer;
ret = load_file2_prot->load_file(load_file2_prot, dp, false,
initrd_size, *initrd);
if (ret != EFI_SUCCESS) {
diff --git a/lib/rsa/rsa-verify.c b/lib/rsa/rsa-verify.c
index e34d329..aee76f4 100644
--- a/lib/rsa/rsa-verify.c
+++ b/lib/rsa/rsa-verify.c
@@ -447,8 +447,11 @@
}
algo = fdt_getprop(blob, node, "algo", NULL);
- if (strcmp(info->name, algo))
+ if (strcmp(info->name, algo)) {
+ debug("%s: Wrong algo: have %s, expected %s", __func__,
+ info->name, algo);
return -EFAULT;
+ }
prop.num_bits = fdtdec_get_int(blob, node, "rsa,num-bits", 0);
diff --git a/lib/sha512.c b/lib/sha512.c
index f1e2acf..35f31e3 100644
--- a/lib/sha512.c
+++ b/lib/sha512.c
@@ -16,6 +16,7 @@
#else
#include <string.h>
#endif /* USE_HOSTCC */
+#include <compiler.h>
#include <watchdog.h>
#include <u-boot/sha512.h>
diff --git a/net/dsa-uclass.c b/net/dsa-uclass.c
index 2ce9ddb..7ea1cb6 100644
--- a/net/dsa-uclass.c
+++ b/net/dsa-uclass.c
@@ -28,8 +28,8 @@
{
struct dsa_priv *priv;
- if (!dev || !dev_get_uclass_priv(dev))
- return -ENODEV;
+ if (!dev)
+ return -EINVAL;
if (headroom + tailroom > DSA_MAX_OVR)
return -EINVAL;
@@ -47,11 +47,13 @@
/* returns the DSA master Ethernet device */
struct udevice *dsa_get_master(struct udevice *dev)
{
- struct dsa_priv *priv = dev_get_uclass_priv(dev);
+ struct dsa_priv *priv;
- if (!priv)
+ if (!dev)
return NULL;
+ priv = dev_get_uclass_priv(dev);
+
return priv->master_dev;
}
@@ -67,14 +69,6 @@
struct dsa_ops *ops = dsa_get_ops(dev);
int err;
- if (!priv)
- return -ENODEV;
-
- if (!master) {
- dev_err(pdev, "DSA master Ethernet device not found!\n");
- return -EINVAL;
- }
-
if (ops->port_enable) {
struct dsa_port_pdata *port_pdata;
@@ -101,9 +95,6 @@
struct udevice *master = dsa_get_master(dev);
struct dsa_ops *ops = dsa_get_ops(dev);
- if (!priv)
- return;
-
if (ops->port_disable) {
struct dsa_port_pdata *port_pdata;
@@ -112,13 +103,7 @@
ops->port_disable(dev, priv->cpu_port, NULL);
}
- /*
- * stop master only if it's active, don't probe it otherwise.
- * Under normal usage it would be active because we're using it, but
- * during tear-down it may have been removed ahead of us.
- */
- if (master && device_active(master))
- eth_get_ops(master)->stop(master);
+ eth_get_ops(master)->stop(master);
}
/*
@@ -137,9 +122,6 @@
struct dsa_port_pdata *port_pdata;
int err;
- if (!master)
- return -EINVAL;
-
if (length + head + tail > PKTSIZE_ALIGN)
return -EINVAL;
@@ -169,9 +151,6 @@
struct dsa_port_pdata *port_pdata;
int length, port_index, err;
- if (!master)
- return -EINVAL;
-
length = eth_get_ops(master)->recv(master, flags, packetp);
if (length <= 0)
return length;
@@ -205,9 +184,6 @@
struct udevice *master = dsa_get_master(dev);
struct dsa_priv *priv;
- if (!master)
- return -EINVAL;
-
priv = dev_get_uclass_priv(dev);
if (eth_get_ops(master)->free_pkt) {
/* return the original pointer and length to master Eth */
@@ -272,6 +248,7 @@
struct dsa_port_pdata *port_pdata;
struct dsa_priv *dsa_priv;
struct udevice *master;
+ int ret;
port_pdata = dev_get_parent_plat(pdev);
dsa_priv = dev_get_uclass_priv(dev);
@@ -280,6 +257,21 @@
if (!port_pdata->phy)
return -ENODEV;
+ master = dsa_get_master(dev);
+ if (!master)
+ return -ENODEV;
+
+ /*
+ * Probe the master device. We depend on the master device for proper
+ * operation and we also need it for MAC inheritance below.
+ *
+ * TODO: we assume the master device is always there and doesn't get
+ * removed during runtime.
+ */
+ ret = device_probe(master);
+ if (ret)
+ return ret;
+
/*
* Inherit port's hwaddr from the DSA master, unless the port already
* has a unique MAC address specified in the environment.
@@ -288,10 +280,6 @@
if (!is_zero_ethaddr(env_enetaddr))
return 0;
- master = dsa_get_master(dev);
- if (!master)
- return 0;
-
master_pdata = dev_get_plat(master);
eth_pdata = dev_get_plat(pdev);
memcpy(eth_pdata->enetaddr, master_pdata->enetaddr, ARP_HLEN);
@@ -338,7 +326,7 @@
ofnode node = dev_ofnode(dev), pnode;
int i, err, first_err = 0;
- if (!pdata || !ofnode_valid(node))
+ if (!ofnode_valid(node))
return -ENODEV;
pdata->master_node = ofnode_null();
@@ -450,9 +438,6 @@
struct dsa_pdata *pdata = dev_get_uclass_plat(dev);
struct dsa_priv *priv = dev_get_uclass_priv(dev);
- if (!pdata || !priv)
- return -ENODEV;
-
priv->num_ports = pdata->num_ports;
priv->cpu_port = pdata->cpu_port;
priv->cpu_port_fixed_phy = fixed_phy_create(pdata->cpu_port_node);
diff --git a/scripts/Makefile.lib b/scripts/Makefile.lib
index 56e9d54..78543c6 100644
--- a/scripts/Makefile.lib
+++ b/scripts/Makefile.lib
@@ -326,8 +326,7 @@
-d $(depfile).dtc.tmp $(dtc-tmp) || \
(echo "Check $(shell pwd)/$(pre-tmp) for errors" && false) \
; \
- cat $(depfile).pre.tmp $(depfile).dtc.tmp > $(depfile) ; \
- sed -i "s:$(pre-tmp):$(<):" $(depfile)
+ sed "s:$(pre-tmp):$(<):" $(depfile).pre.tmp $(depfile).dtc.tmp > $(depfile)
$(obj)/%.dtb: $(src)/%.dts FORCE
$(call if_changed_dep,dtc)
diff --git a/scripts/Makefile.spl b/scripts/Makefile.spl
index ea4e045..1fd63ef 100644
--- a/scripts/Makefile.spl
+++ b/scripts/Makefile.spl
@@ -229,6 +229,8 @@
INPUTS-y += $(obj)/$(SPL_BIN).sfp
endif
+INPUTS-$(CONFIG_TARGET_SOCFPGA_SOC64) += $(obj)/u-boot-spl-dtb.hex
+
ifdef CONFIG_ARCH_SUNXI
INPUTS-y += $(obj)/sunxi-spl.bin
@@ -389,6 +391,11 @@
MKIMAGEFLAGS_sunxi-spl.bin = -T sunxi_egon \
-n $(CONFIG_DEFAULT_DEVICE_TREE)
+OBJCOPYFLAGS_u-boot-spl-dtb.hex := -I binary -O ihex --change-address=$(CONFIG_SPL_TEXT_BASE)
+
+$(obj)/u-boot-spl-dtb.hex: $(obj)/u-boot-spl-dtb.bin FORCE
+ $(call if_changed,objcopy)
+
$(obj)/sunxi-spl.bin: $(obj)/$(SPL_BIN).bin FORCE
$(call if_changed,mkimage)
diff --git a/scripts/check-config.sh b/scripts/check-config.sh
index 583f7d0..cc1c9a5 100755
--- a/scripts/check-config.sh
+++ b/scripts/check-config.sh
@@ -39,14 +39,14 @@
export LC_ALL=C
export LC_COLLATE=C
-cat ${path} |sed -n 's/^#define \(CONFIG_[A-Za-z0-9_]*\).*/\1/p' |sort |uniq \
+cat ${path} |sed -nr 's/^#define (CONFIG_[A-Za-z0-9_]*).*/\1/p' |sort |uniq \
>${configs}
comm -23 ${configs} ${whitelist} > ${suspects}
-cat `find ${srctree} -name "Kconfig*"` |sed -n \
- -e 's/^\s*config *\([A-Za-z0-9_]*\).*$/CONFIG_\1/p' \
- -e 's/^\s*menuconfig \([A-Za-z0-9_]*\).*$/CONFIG_\1/p' \
+cat `find ${srctree} -name "Kconfig*"` |sed -nr \
+ -e 's/^[[:blank:]]*config *([A-Za-z0-9_]*).*$/CONFIG_\1/p' \
+ -e 's/^[[:blank:]]*menuconfig ([A-Za-z0-9_]*).*$/CONFIG_\1/p' \
|sort |uniq > ${ok}
comm -23 ${suspects} ${ok} >${new_adhoc}
if [ -s ${new_adhoc} ]; then
diff --git a/scripts/checkpatch.pl b/scripts/checkpatch.pl
index 01ab570..755f480 100755
--- a/scripts/checkpatch.pl
+++ b/scripts/checkpatch.pl
@@ -2383,6 +2383,12 @@
"fdt or initrd relocation disabled at boot time\n" . $herecurr);
}
+ # make sure 'skip_board_fixup' is not
+ if ($rawline =~ /.*skip_board_fixup.*/) {
+ ERROR("SKIP_BOARD_FIXUP",
+ "Avoid setting skip_board_fixup env variable\n" . $herecurr);
+ }
+
# Do not use CONFIG_ prefix in CONFIG_IS_ENABLED() calls
if ($line =~ /^\+.*CONFIG_IS_ENABLED\(CONFIG_\w*\).*/) {
ERROR("CONFIG_IS_ENABLED_CONFIG",
diff --git a/scripts/config_whitelist.txt b/scripts/config_whitelist.txt
index c8c8790..43295ee 100644
--- a/scripts/config_whitelist.txt
+++ b/scripts/config_whitelist.txt
@@ -43,7 +43,6 @@
CONFIG_ARMADA100
CONFIG_ARMADA100_FEC
CONFIG_ARMADA168
-CONFIG_ARMADA_39X
CONFIG_ARMV7_SECURE_BASE
CONFIG_ARMV7_SECURE_MAX_SIZE
CONFIG_ARMV7_SECURE_RESERVE_SIZE
@@ -78,7 +77,6 @@
CONFIG_AT91_LED
CONFIG_AT91_WANTS_COMMON_PHY
CONFIG_ATAPI
-CONFIG_ATM
CONFIG_ATMEL_LCD
CONFIG_ATMEL_LCD_BGR555
CONFIG_ATMEL_LCD_RGB565
@@ -552,7 +550,6 @@
CONFIG_FSL_SGMII_RISER
CONFIG_FSL_TBCLK_EXTRA_DIV
CONFIG_FSL_TRUST_ARCH_v1
-CONFIG_FSL_VIA
CONFIG_FSMC_NAND_BASE
CONFIG_FSMTDBLK
CONFIG_FSNOTIFY
@@ -615,8 +612,6 @@
CONFIG_HAS_ETH1
CONFIG_HAS_ETH2
CONFIG_HAS_ETH3
-CONFIG_HAS_ETH5
-CONFIG_HAS_ETH7
CONFIG_HAS_FEC
CONFIG_HAS_FSL_DR_USB
CONFIG_HAS_FSL_MPH_USB
@@ -1276,7 +1271,6 @@
CONFIG_POWER
CONFIG_POWER_FSL
CONFIG_POWER_FSL_MC13892
-CONFIG_POWER_FSL_MC34704
CONFIG_POWER_HI6553
CONFIG_POWER_I2C
CONFIG_POWER_LTC3676
@@ -1387,7 +1381,6 @@
CONFIG_RTC_DS1388_TCR_VAL
CONFIG_RTC_DS3231
CONFIG_RTC_FTRTC010
-CONFIG_RTC_IMXDI
CONFIG_RTC_M41T11
CONFIG_RTC_MC13XXX
CONFIG_RTC_MCFRRTC
@@ -1696,7 +1689,6 @@
CONFIG_SYS_BCSR
CONFIG_SYS_BCSR_ADDR
CONFIG_SYS_BCSR_BASE
-CONFIG_SYS_BCSR_BASE_PHYS
CONFIG_SYS_BCSR_SIZE
CONFIG_SYS_BD_REV
CONFIG_SYS_BFTIC3_BASE
@@ -1968,8 +1960,6 @@
CONFIG_SYS_DDRUA
CONFIG_SYS_DDR_BLOCK1_SIZE
CONFIG_SYS_DDR_BLOCK2_BASE
-CONFIG_SYS_DDR_CDR_1
-CONFIG_SYS_DDR_CDR_2
CONFIG_SYS_DDR_CFG_1A
CONFIG_SYS_DDR_CFG_1B
CONFIG_SYS_DDR_CFG_2
@@ -1986,7 +1976,6 @@
CONFIG_SYS_DDR_CONFIG_2
CONFIG_SYS_DDR_CONFIG_256
CONFIG_SYS_DDR_CONTROL
-CONFIG_SYS_DDR_CONTROL2
CONFIG_SYS_DDR_CONTROL_2
CONFIG_SYS_DDR_CPO
CONFIG_SYS_DDR_CS0_BNDS
@@ -2000,8 +1989,6 @@
CONFIG_SYS_DDR_CS3_BNDS
CONFIG_SYS_DDR_CS3_CONFIG
CONFIG_SYS_DDR_DATA_INIT
-CONFIG_SYS_DDR_ERR_DIS
-CONFIG_SYS_DDR_ERR_INT_EN
CONFIG_SYS_DDR_INIT_ADDR
CONFIG_SYS_DDR_INIT_EXT_ADDR
CONFIG_SYS_DDR_INTERVAL
@@ -2027,21 +2014,14 @@
CONFIG_SYS_DDR_MODE_CONTROL
CONFIG_SYS_DDR_MODE_CTL
CONFIG_SYS_DDR_MODE_WEAK
-CONFIG_SYS_DDR_OCD_CTRL
-CONFIG_SYS_DDR_OCD_STATUS
CONFIG_SYS_DDR_RAW_TIMING
CONFIG_SYS_DDR_RCW_1
CONFIG_SYS_DDR_RCW_2
-CONFIG_SYS_DDR_SBE
CONFIG_SYS_DDR_SDRAM_BASE
CONFIG_SYS_DDR_SDRAM_BASE2
CONFIG_SYS_DDR_SDRAM_CFG
CONFIG_SYS_DDR_SDRAM_CFG2
-CONFIG_SYS_DDR_SDRAM_CFG_2
CONFIG_SYS_DDR_SDRAM_CLK_CNTL
-CONFIG_SYS_DDR_SDRAM_INTERVAL
-CONFIG_SYS_DDR_SDRAM_MODE
-CONFIG_SYS_DDR_SDRAM_MODE_2
CONFIG_SYS_DDR_SIZE
CONFIG_SYS_DDR_SR_CNTR
CONFIG_SYS_DDR_TIMING_0
@@ -2269,8 +2249,6 @@
CONFIG_SYS_FSL_B4860QDS_XFI_ERR
CONFIG_SYS_FSL_BMAN_ADDR
CONFIG_SYS_FSL_BMAN_OFFSET
-CONFIG_SYS_FSL_BOOTROM_BASE
-CONFIG_SYS_FSL_BOOTROM_SIZE
CONFIG_SYS_FSL_CCSR_BASE
CONFIG_SYS_FSL_CCSR_GUR_BE
CONFIG_SYS_FSL_CCSR_GUR_LE
@@ -2818,7 +2796,6 @@
CONFIG_SYS_LBC0_BASE_PHYS
CONFIG_SYS_LBC1_BASE
CONFIG_SYS_LBC1_BASE_PHYS
-CONFIG_SYS_LBCR_ADDR
CONFIG_SYS_LBC_ADDR
CONFIG_SYS_LBC_CACHE_BASE
CONFIG_SYS_LBC_FLASH_BASE
@@ -2894,8 +2871,6 @@
CONFIG_SYS_MAX_NAND_CHIPS
CONFIG_SYS_MAX_NAND_DEVICE
CONFIG_SYS_MAX_PCI_EPS
-CONFIG_SYS_MB862xx_CCF
-CONFIG_SYS_MB862xx_MMR
CONFIG_SYS_MBAR
CONFIG_SYS_MBAR2
CONFIG_SYS_MCATT0_VAL
@@ -3099,7 +3074,6 @@
CONFIG_SYS_NAND_SELECT_DEVICE
CONFIG_SYS_NAND_SIZE
CONFIG_SYS_NAND_SPL_KERNEL_OFFS
-CONFIG_SYS_NAND_SPL_SIZE
CONFIG_SYS_NAND_U_BOOT_DST
CONFIG_SYS_NAND_U_BOOT_RELOC
CONFIG_SYS_NAND_U_BOOT_RELOC_SP
@@ -3700,8 +3674,6 @@
CONFIG_SYS_UBOOT_BASE
CONFIG_SYS_UBOOT_END
CONFIG_SYS_UBOOT_START
-CONFIG_SYS_UCC_RGMII_MODE
-CONFIG_SYS_UCC_RMII_MODE
CONFIG_SYS_UDELAY_BASE
CONFIG_SYS_UEC
CONFIG_SYS_UEC1_ETH_TYPE
@@ -3718,34 +3690,8 @@
CONFIG_SYS_UEC2_RX_CLK
CONFIG_SYS_UEC2_TX_CLK
CONFIG_SYS_UEC2_UCC_NUM
-CONFIG_SYS_UEC3_ETH_TYPE
-CONFIG_SYS_UEC3_INTERFACE_SPEED
-CONFIG_SYS_UEC3_INTERFACE_TYPE
CONFIG_SYS_UEC3_PHY_ADDR
-CONFIG_SYS_UEC3_RX_CLK
-CONFIG_SYS_UEC3_TX_CLK
-CONFIG_SYS_UEC3_UCC_NUM
-CONFIG_SYS_UEC4_ETH_TYPE
-CONFIG_SYS_UEC4_INTERFACE_SPEED
-CONFIG_SYS_UEC4_INTERFACE_TYPE
CONFIG_SYS_UEC4_PHY_ADDR
-CONFIG_SYS_UEC4_RX_CLK
-CONFIG_SYS_UEC4_TX_CLK
-CONFIG_SYS_UEC4_UCC_NUM
-CONFIG_SYS_UEC6_ETH_TYPE
-CONFIG_SYS_UEC6_INTERFACE_SPEED
-CONFIG_SYS_UEC6_INTERFACE_TYPE
-CONFIG_SYS_UEC6_PHY_ADDR
-CONFIG_SYS_UEC6_RX_CLK
-CONFIG_SYS_UEC6_TX_CLK
-CONFIG_SYS_UEC6_UCC_NUM
-CONFIG_SYS_UEC8_ETH_TYPE
-CONFIG_SYS_UEC8_INTERFACE_SPEED
-CONFIG_SYS_UEC8_INTERFACE_TYPE
-CONFIG_SYS_UEC8_PHY_ADDR
-CONFIG_SYS_UEC8_RX_CLK
-CONFIG_SYS_UEC8_TX_CLK
-CONFIG_SYS_UEC8_UCC_NUM
CONFIG_SYS_UECx_PHY_ADDR
CONFIG_SYS_UHC0_EHCI_BASE
CONFIG_SYS_UHC1_EHCI_BASE
@@ -3931,7 +3877,6 @@
CONFIG_USB_DEVICE
CONFIG_USB_DEV_BASE
CONFIG_USB_DEV_PULLUP_GPIO
-CONFIG_USB_DWC2_REG_ADDR
CONFIG_USB_EHCI_ARMADA100
CONFIG_USB_EHCI_BASE
CONFIG_USB_EHCI_BASE_LIST
@@ -3996,7 +3941,6 @@
CONFIG_VERY_BIG_RAM
CONFIG_VEXPRESS_EXTENDED_MEMORY_MAP
CONFIG_VEXPRESS_ORIGINAL_MEMORY_MAP
-CONFIG_VID
CONFIG_VIDEO_BCM2835
CONFIG_VIDEO_BMP_LOGO
CONFIG_VIDEO_CORALP
diff --git a/test/cmd/Makefile b/test/cmd/Makefile
index 5451e9e..2cfe43a 100644
--- a/test/cmd/Makefile
+++ b/test/cmd/Makefile
@@ -6,6 +6,7 @@
obj-$(CONFIG_CONSOLE_RECORD) += test_echo.o
endif
obj-y += mem.o
+obj-$(CONFIG_CMD_ADDRMAP) += addrmap.o
obj-$(CONFIG_CMD_MEM_SEARCH) += mem_search.o
obj-$(CONFIG_CMD_PWM) += pwm.o
-obj-y += setexpr.o
+obj-$(CONFIG_CMD_SETEXPR) += setexpr.o
diff --git a/test/cmd/addrmap.c b/test/cmd/addrmap.c
new file mode 100644
index 0000000..fb74448
--- /dev/null
+++ b/test/cmd/addrmap.c
@@ -0,0 +1,38 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Tests for addrmap command
+ *
+ * Copyright (C) 2021, Bin Meng <bmeng.cn@gmail.com>
+ */
+
+#include <common.h>
+#include <console.h>
+#include <test/suites.h>
+#include <test/ut.h>
+
+/* Declare a new addrmap test */
+#define ADDRMAP_TEST(_name, _flags) UNIT_TEST(_name, _flags, addrmap_test)
+
+/* Test 'addrmap' command output */
+static int addrmap_test_basic(struct unit_test_state *uts)
+{
+ ut_assertok(console_record_reset_enable());
+ ut_assertok(run_command("addrmap", 0));
+ ut_assert_nextline(" vaddr paddr size");
+ ut_assert_nextline("================ ================ ================");
+ /* There should be at least one entry */
+ ut_assertok(!ut_check_console_end(uts));
+
+ return 0;
+}
+ADDRMAP_TEST(addrmap_test_basic, UT_TESTF_CONSOLE_REC);
+
+int do_ut_addrmap(struct cmd_tbl *cmdtp, int flag, int argc, char *const argv[])
+{
+ struct unit_test *tests = ll_entry_start(struct unit_test,
+ addrmap_test);
+ const int n_ents = ll_entry_count(struct unit_test, addrmap_test);
+
+ return cmd_ut_category("cmd_addrmap", "cmd_addrmap_", tests, n_ents,
+ argc, argv);
+}
diff --git a/test/cmd_ut.c b/test/cmd_ut.c
index 90674d5..8728cc8 100644
--- a/test/cmd_ut.c
+++ b/test/cmd_ut.c
@@ -75,8 +75,10 @@
U_BOOT_CMD_MKENT(log, CONFIG_SYS_MAXARGS, 1, do_ut_log, "", ""),
#endif
U_BOOT_CMD_MKENT(mem, CONFIG_SYS_MAXARGS, 1, do_ut_mem, "", ""),
+#ifdef CONFIG_CMD_SETEXPR
U_BOOT_CMD_MKENT(setexpr, CONFIG_SYS_MAXARGS, 1, do_ut_setexpr, "",
""),
+#endif
#ifdef CONFIG_UT_TIME
U_BOOT_CMD_MKENT(time, CONFIG_SYS_MAXARGS, 1, do_ut_time, "", ""),
#endif
@@ -91,6 +93,9 @@
U_BOOT_CMD_MKENT(bootm, CONFIG_SYS_MAXARGS, 1, do_ut_bootm, "", ""),
#endif
U_BOOT_CMD_MKENT(str, CONFIG_SYS_MAXARGS, 1, do_ut_str, "", ""),
+#ifdef CONFIG_CMD_ADDRMAP
+ U_BOOT_CMD_MKENT(addrmap, CONFIG_SYS_MAXARGS, 1, do_ut_addrmap, "", ""),
+#endif
};
static int do_ut_all(struct cmd_tbl *cmdtp, int flag, int argc,
@@ -166,6 +171,9 @@
!defined(CONFIG_SPL_BUILD) && !defined(API_BUILD)
"ut unicode [test-name] - test Unicode functions\n"
#endif
+#ifdef CONFIG_CMD_ADDRMAP
+ "ut addrmap - Very basic test of addrmap command\n"
+#endif
;
#endif /* CONFIG_SYS_LONGHELP */
diff --git a/test/dm/Makefile b/test/dm/Makefile
index 6275ec5..fd14551 100644
--- a/test/dm/Makefile
+++ b/test/dm/Makefile
@@ -95,5 +95,8 @@
ifneq ($(CONFIG_PINMUX),)
obj-$(CONFIG_PINCONF) += pinmux.o
endif
+ifneq ($(CONFIG_EFI_PARTITION),)
+obj-$(CONFIG_FASTBOOT_FLASH_MMC) += fastboot.o
+endif
endif
endif # !SPL
diff --git a/test/dm/button.c b/test/dm/button.c
index ecaa47c..f8a7fab 100644
--- a/test/dm/button.c
+++ b/test/dm/button.c
@@ -7,7 +7,10 @@
#include <common.h>
#include <dm.h>
+#include <adc.h>
#include <button.h>
+#include <power/regulator.h>
+#include <power/sandbox_pmic.h>
#include <asm/gpio.h>
#include <dm/test.h>
#include <test/ut.h>
@@ -17,11 +20,20 @@
{
struct udevice *dev;
- /* Get the top-level device */
+ /* Get the top-level gpio buttons device */
ut_assertok(uclass_get_device(UCLASS_BUTTON, 0, &dev));
+ /* Get the 2 gpio buttons */
ut_assertok(uclass_get_device(UCLASS_BUTTON, 1, &dev));
ut_assertok(uclass_get_device(UCLASS_BUTTON, 2, &dev));
- ut_asserteq(-ENODEV, uclass_get_device(UCLASS_BUTTON, 3, &dev));
+
+ /* Get the top-level adc buttons device */
+ ut_assertok(uclass_get_device(UCLASS_BUTTON, 3, &dev));
+ /* Get the 3 adc buttons */
+ ut_assertok(uclass_get_device(UCLASS_BUTTON, 4, &dev));
+ ut_assertok(uclass_get_device(UCLASS_BUTTON, 5, &dev));
+ ut_assertok(uclass_get_device(UCLASS_BUTTON, 6, &dev));
+
+ ut_asserteq(-ENODEV, uclass_get_device(UCLASS_BUTTON, 7, &dev));
return 0;
}
@@ -72,3 +84,37 @@
return 0;
}
DM_TEST(dm_test_button_label, UT_TESTF_SCAN_PDATA | UT_TESTF_SCAN_FDT);
+
+/* Test adc-keys driver */
+static int dm_test_button_keys_adc(struct unit_test_state *uts)
+{
+ struct udevice *supply;
+ struct udevice *dev;
+ int uV;
+
+ ut_assertok(uclass_get_device_by_name(UCLASS_ADC, "adc@0", &dev));
+
+ ut_assertok(regulator_get_by_devname(SANDBOX_BUCK2_DEVNAME, &supply));
+ ut_assertok(regulator_set_value(supply, SANDBOX_BUCK2_SET_UV));
+ ut_asserteq(SANDBOX_BUCK2_SET_UV, regulator_get_value(supply));
+ /* Update ADC plat and get new Vdd value */
+ ut_assertok(adc_vdd_value(dev, &uV));
+ ut_asserteq(SANDBOX_BUCK2_SET_UV, uV);
+
+ /*
+ * sandbox-adc returns constant value on channel 3, is used by adc-keys:
+ * SANDBOX_ADC_CHANNEL3_DATA * SANDBOX_BUCK2_SET_UV / SANDBOX_ADC_DATA_MASK =
+ * 0x3000 * 3300000 / 0xffff = 618759uV
+ * This means that button3 and button4 are released and button5
+ * is pressed.
+ */
+ ut_assertok(button_get_by_label("button3", &dev));
+ ut_asserteq(BUTTON_OFF, button_get_state(dev));
+ ut_assertok(button_get_by_label("button4", &dev));
+ ut_asserteq(BUTTON_OFF, button_get_state(dev));
+ ut_assertok(button_get_by_label("button5", &dev));
+ ut_asserteq(BUTTON_ON, button_get_state(dev));
+
+ return 0;
+}
+DM_TEST(dm_test_button_keys_adc, UT_TESTF_SCAN_PDATA | UT_TESTF_SCAN_FDT);
diff --git a/test/dm/fastboot.c b/test/dm/fastboot.c
new file mode 100644
index 0000000..e7f8c36
--- /dev/null
+++ b/test/dm/fastboot.c
@@ -0,0 +1,95 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2015 Google, Inc
+ */
+
+#include <common.h>
+#include <dm.h>
+#include <fastboot.h>
+#include <fb_mmc.h>
+#include <mmc.h>
+#include <part.h>
+#include <part_efi.h>
+#include <dm/test.h>
+#include <test/ut.h>
+#include <linux/stringify.h>
+
+#define FB_ALIAS_PREFIX "fastboot_partition_alias_"
+
+static int dm_test_fastboot_mmc_part(struct unit_test_state *uts)
+{
+ char response[FASTBOOT_RESPONSE_LEN] = {0};
+ char str_disk_guid[UUID_STR_LEN + 1];
+ struct blk_desc *mmc_dev_desc, *fb_dev_desc;
+ struct disk_partition part_info;
+ struct disk_partition parts[2] = {
+ {
+ .start = 48, /* GPT data takes up the first 34 blocks or so */
+ .size = 1,
+ .name = "test1",
+ },
+ {
+ .start = 49,
+ .size = 1,
+ .name = "test2",
+ },
+ };
+
+ /*
+ * There are a lot of literal 0s I don't want to have to construct from
+ * MMC_DEV.
+ */
+ ut_asserteq(0, CONFIG_FASTBOOT_FLASH_MMC_DEV);
+ ut_assertok(blk_get_device_by_str("mmc", "0", &mmc_dev_desc));
+ if (CONFIG_IS_ENABLED(RANDOM_UUID)) {
+ gen_rand_uuid_str(parts[0].uuid, UUID_STR_FORMAT_STD);
+ gen_rand_uuid_str(parts[1].uuid, UUID_STR_FORMAT_STD);
+ gen_rand_uuid_str(str_disk_guid, UUID_STR_FORMAT_STD);
+ }
+ ut_assertok(gpt_restore(mmc_dev_desc, str_disk_guid, parts,
+ ARRAY_SIZE(parts)));
+
+ /* "Classic" partition labels */
+ ut_asserteq(1, fastboot_mmc_get_part_info("test1", &fb_dev_desc,
+ &part_info, response));
+ ut_asserteq(2, fastboot_mmc_get_part_info("test2", &fb_dev_desc,
+ &part_info, response));
+
+ /* Test aliases */
+ ut_assertnull(env_get(FB_ALIAS_PREFIX "test3"));
+ ut_assertok(env_set(FB_ALIAS_PREFIX "test3", "test1"));
+ ut_asserteq(1, fastboot_mmc_get_part_info("test3", &fb_dev_desc,
+ &part_info, response));
+ ut_assertok(env_set(FB_ALIAS_PREFIX "test3", NULL));
+
+ /* "New" partition labels */
+ ut_asserteq(1, fastboot_mmc_get_part_info("#test1", &fb_dev_desc,
+ &part_info, response));
+ ut_asserteq(1, fastboot_mmc_get_part_info("0#test1", &fb_dev_desc,
+ &part_info, response));
+ ut_asserteq(1, fastboot_mmc_get_part_info("0.0#test1", &fb_dev_desc,
+ &part_info, response));
+ ut_asserteq(1, fastboot_mmc_get_part_info("0:1", &fb_dev_desc,
+ &part_info, response));
+ ut_asserteq(1, fastboot_mmc_get_part_info("0.0:1", &fb_dev_desc,
+ &part_info, response));
+ ut_asserteq(1, fastboot_mmc_get_part_info("0", &fb_dev_desc,
+ &part_info, response));
+ ut_asserteq(1, fastboot_mmc_get_part_info("0.0", &fb_dev_desc,
+ &part_info, response));
+ ut_asserteq(0, fastboot_mmc_get_part_info("0:0", &fb_dev_desc,
+ &part_info, response));
+ ut_asserteq(0, fastboot_mmc_get_part_info("0.0:0", &fb_dev_desc,
+ &part_info, response));
+ ut_asserteq(0, fastboot_mmc_get_part_info("1", &fb_dev_desc,
+ &part_info, response));
+ ut_asserteq(0, fastboot_mmc_get_part_info("1.0", &fb_dev_desc,
+ &part_info, response));
+ ut_asserteq(1, fastboot_mmc_get_part_info(":1", &fb_dev_desc,
+ &part_info, response));
+ ut_asserteq(0, fastboot_mmc_get_part_info(":0", &fb_dev_desc,
+ &part_info, response));
+
+ return 0;
+}
+DM_TEST(dm_test_fastboot_mmc_part, UT_TESTF_SCAN_PDATA | UT_TESTF_SCAN_FDT);
diff --git a/test/dm/mmc.c b/test/dm/mmc.c
index 4e5136c..f744452 100644
--- a/test/dm/mmc.c
+++ b/test/dm/mmc.c
@@ -29,16 +29,25 @@
{
struct udevice *dev;
struct blk_desc *dev_desc;
- char cmp[1024];
+ int i;
+ char write[1024], read[1024];
ut_assertok(uclass_get_device(UCLASS_MMC, 0, &dev));
ut_assertok(blk_get_device_by_str("mmc", "0", &dev_desc));
- /* Read a few blocks and look for the string we expect */
+ /* Write a few blocks and verify that we get the same data back */
ut_asserteq(512, dev_desc->blksz);
- memset(cmp, '\0', sizeof(cmp));
- ut_asserteq(2, blk_dread(dev_desc, 0, 2, cmp));
- ut_assertok(strcmp(cmp, "this is a test"));
+ for (i = 0; i < sizeof(write); i++)
+ write[i] = i;
+ ut_asserteq(2, blk_dwrite(dev_desc, 0, 2, write));
+ ut_asserteq(2, blk_dread(dev_desc, 0, 2, read));
+ ut_asserteq_mem(write, read, sizeof(write));
+
+ /* Now erase them */
+ memset(write, '\0', sizeof(write));
+ ut_asserteq(2, blk_derase(dev_desc, 0, 2));
+ ut_asserteq(2, blk_dread(dev_desc, 0, 2, read));
+ ut_asserteq_mem(write, read, sizeof(write));
return 0;
}
diff --git a/test/py/tests/test_efi_capsule/uboot_bin_env.its b/test/py/tests/test_efi_capsule/uboot_bin_env.its
index 31e2f80..fc65907 100644
--- a/test/py/tests/test_efi_capsule/uboot_bin_env.its
+++ b/test/py/tests/test_efi_capsule/uboot_bin_env.its
@@ -10,7 +10,7 @@
#address-cells = <2>;
images {
- u-boot-bin@100000 {
+ u-boot-bin {
description = "U-Boot binary on SPI Flash";
data = /incbin/("BINFILE1");
compression = "none";
@@ -21,7 +21,7 @@
algo = "sha1";
};
};
- u-boot-env@150000 {
+ u-boot-env {
description = "U-Boot environment on SPI Flash";
data = /incbin/("BINFILE2");
compression = "none";
diff --git a/test/py/tests/test_env.py b/test/py/tests/test_env.py
index 9402796..9bed2f4 100644
--- a/test/py/tests/test_env.py
+++ b/test/py/tests/test_env.py
@@ -414,6 +414,8 @@
if os.path.exists(persistent):
c.log.action('Disk image file ' + persistent + ' already exists')
else:
+ # Some distributions do not add /sbin to the default PATH, where mkfs.ext4 lives
+ os.environ["PATH"] += os.pathsep + '/sbin'
try:
u_boot_utils.run_and_log(c, 'dd if=/dev/zero of=%s bs=1M count=16' % persistent)
u_boot_utils.run_and_log(c, 'mkfs.ext4 %s' % persistent)
diff --git a/test/unicode_ut.c b/test/unicode_ut.c
index 6130ef0..6f6aea5 100644
--- a/test/unicode_ut.c
+++ b/test/unicode_ut.c
@@ -47,11 +47,15 @@
/* Three letters translating to two utf-16 word each */
static const char d4[] = {0xf0, 0x90, 0x92, 0x8d, 0xf0, 0x90, 0x92, 0x96,
0xf0, 0x90, 0x92, 0x87, 0x00};
+/* Letter not in code page 437 */
+static const char d5[] = {0xCE, 0x92, 0x20, 0x69, 0x73, 0x20, 0x6E, 0x6F,
+ 0x74, 0x20, 0x42, 0x00};
/* Illegal utf-8 strings */
static const char j1[] = {0x6a, 0x31, 0xa1, 0x6c, 0x00};
static const char j2[] = {0x6a, 0x32, 0xc3, 0xc3, 0x6c, 0x00};
static const char j3[] = {0x6a, 0x33, 0xf0, 0x90, 0xf0, 0x00};
+static const char j4[] = {0xa1, 0x00};
static int unicode_test_u16_strlen(struct unit_test_state *uts)
{
@@ -165,6 +169,12 @@
ut_asserteq(0x0001048d, code);
ut_asserteq_ptr(s, d4 + 4);
+ /* Check illegal character */
+ s = j4;
+ code = utf8_get((const char **)&s);
+ ut_asserteq(-1, code);
+ ut_asserteq_ptr(j4 + 1, s);
+
return 0;
}
UNICODE_TEST(unicode_test_utf8_get);
@@ -595,6 +605,110 @@
}
UNICODE_TEST(unicode_test_u16_strsize);
+static int unicode_test_utf_to_cp(struct unit_test_state *uts)
+{
+ int ret;
+ s32 c;
+
+ c = '\n';
+ ret = utf_to_cp(&c, codepage_437);
+ ut_asserteq(0, ret);
+ ut_asserteq('\n', c);
+
+ c = 'a';
+ ret = utf_to_cp(&c, codepage_437);
+ ut_asserteq(0, ret);
+ ut_asserteq('a', c);
+
+ c = 0x03c4; /* Greek small letter tau */
+ ret = utf_to_cp(&c, codepage_437);
+ ut_asserteq(0, ret);
+ ut_asserteq(0xe7, c);
+
+ c = 0x03a4; /* Greek capital letter tau */
+ ret = utf_to_cp(&c, codepage_437);
+ ut_asserteq(-ENOENT, ret);
+ ut_asserteq('?', c);
+
+ return 0;
+}
+UNICODE_TEST(unicode_test_utf_to_cp);
+
+static void utf8_to_cp437_stream_helper(const char *in, char *out)
+{
+ char buffer[5];
+ int ret;
+
+ *buffer = 0;
+ for (; *in; ++in) {
+ ret = utf8_to_cp437_stream(*in, buffer);
+ if (ret)
+ *out++ = ret;
+ }
+ *out = 0;
+}
+
+static int unicode_test_utf8_to_cp437_stream(struct unit_test_state *uts)
+{
+ char buf[16];
+
+ utf8_to_cp437_stream_helper(d1, buf);
+ ut_asserteq_str("U-Boot", buf);
+ utf8_to_cp437_stream_helper(d2, buf);
+ ut_asserteq_str("kafb\xa0tur", buf);
+ utf8_to_cp437_stream_helper(d5, buf);
+ ut_asserteq_str("? is not B", buf);
+ utf8_to_cp437_stream_helper(j2, buf);
+ ut_asserteq_str("j2l", buf);
+
+ return 0;
+}
+UNICODE_TEST(unicode_test_utf8_to_cp437_stream);
+
+static void utf8_to_utf32_stream_helper(const char *in, s32 *out)
+{
+ char buffer[5];
+ int ret;
+
+ *buffer = 0;
+ for (; *in; ++in) {
+ ret = utf8_to_utf32_stream(*in, buffer);
+ if (ret)
+ *out++ = ret;
+ }
+ *out = 0;
+}
+
+static int unicode_test_utf8_to_utf32_stream(struct unit_test_state *uts)
+{
+ s32 buf[16];
+
+ const u32 u1[] = {0x55, 0x2D, 0x42, 0x6F, 0x6F, 0x74, 0x0000};
+ const u32 u2[] = {0x6B, 0x61, 0x66, 0x62, 0xE1, 0x74, 0x75, 0x72, 0x00};
+ const u32 u3[] = {0x0392, 0x20, 0x69, 0x73, 0x20, 0x6E, 0x6F, 0x74,
+ 0x20, 0x42, 0x00};
+ const u32 u4[] = {0x6A, 0x32, 0x6C, 0x00};
+
+ memset(buf, 0, sizeof(buf));
+ utf8_to_utf32_stream_helper(d1, buf);
+ ut_asserteq_mem(u1, buf, sizeof(u1));
+
+ memset(buf, 0, sizeof(buf));
+ utf8_to_utf32_stream_helper(d2, buf);
+ ut_asserteq_mem(u2, buf, sizeof(u2));
+
+ memset(buf, 0, sizeof(buf));
+ utf8_to_utf32_stream_helper(d5, buf);
+ ut_asserteq_mem(u3, buf, sizeof(u3));
+
+ memset(buf, 0, sizeof(buf));
+ utf8_to_utf32_stream_helper(j2, buf);
+ ut_asserteq_mem(u4, buf, sizeof(u4));
+
+ return 0;
+}
+UNICODE_TEST(unicode_test_utf8_to_utf32_stream);
+
#ifdef CONFIG_EFI_LOADER
static int unicode_test_efi_create_indexed_name(struct unit_test_state *uts)
{
diff --git a/tools/Makefile b/tools/Makefile
index 2d55043..62de7e6 100644
--- a/tools/Makefile
+++ b/tools/Makefile
@@ -150,12 +150,12 @@
HOSTCFLAGS_kwbimage.o += -DCONFIG_SYS_U_BOOT_OFFS=$(CONFIG_SYS_U_BOOT_OFFS)
endif
-ifneq ($(CONFIG_ARMADA_38X)$(CONFIG_ARMADA_39X),)
+ifneq ($(CONFIG_ARMADA_38X),)
HOSTCFLAGS_kwbimage.o += -DCONFIG_KWB_SECURE
endif
# MXSImage needs LibSSL
-ifneq ($(CONFIG_MX23)$(CONFIG_MX28)$(CONFIG_ARMADA_38X)$(CONFIG_ARMADA_39X)$(CONFIG_FIT_SIGNATURE)$(CONFIG_FIT_CIPHER),)
+ifneq ($(CONFIG_MX23)$(CONFIG_MX28)$(CONFIG_ARMADA_38X)$(CONFIG_FIT_SIGNATURE)$(CONFIG_FIT_CIPHER),)
HOSTCFLAGS_kwbimage.o += \
$(shell pkg-config --cflags libssl libcrypto 2> /dev/null || echo "")
HOSTLDLIBS_mkimage += \
diff --git a/tools/buildman/README b/tools/buildman/README
index b7442a9..6007947 100644
--- a/tools/buildman/README
+++ b/tools/buildman/README
@@ -1128,6 +1128,11 @@
The -y option is provided (for use with -s) to ignore the bountiful device-tree
warnings. Similarly, -Y tells buildman to ignore the migration warnings.
+Sometimes you might get an error in a thread that is not handled by buildman,
+perhaps due to a failure of a tool that it calls. You might see the output, but
+then buildman hangs. Failing to handle any eventuality is a bug in buildman and
+should be reported. But you can use -T0 to disable threading and hopefully
+figure out the root cause of the build failure.
Build summary
=============
diff --git a/tools/buildman/builder.py b/tools/buildman/builder.py
index 6f6d759..be8a8fa 100644
--- a/tools/buildman/builder.py
+++ b/tools/buildman/builder.py
@@ -197,6 +197,8 @@
last _timestamp_count builds. Each is a datetime object.
_timestamp_count: Number of timestamps to keep in our list.
_working_dir: Base working directory containing all threads
+ _single_builder: BuilderThread object for the singer builder, if
+ threading is not being used
"""
class Outcome:
"""Records a build outcome for a single make invocation
@@ -309,19 +311,24 @@
self._re_migration_warning = re.compile(r'^={21} WARNING ={22}\n.*\n=+\n',
re.MULTILINE | re.DOTALL)
- self.queue = queue.Queue()
- self.out_queue = queue.Queue()
- for i in range(self.num_threads):
- t = builderthread.BuilderThread(self, i, mrproper,
- per_board_out_dir)
+ if self.num_threads:
+ self._single_builder = None
+ self.queue = queue.Queue()
+ self.out_queue = queue.Queue()
+ for i in range(self.num_threads):
+ t = builderthread.BuilderThread(self, i, mrproper,
+ per_board_out_dir)
+ t.setDaemon(True)
+ t.start()
+ self.threads.append(t)
+
+ t = builderthread.ResultThread(self)
t.setDaemon(True)
t.start()
self.threads.append(t)
-
- t = builderthread.ResultThread(self)
- t.setDaemon(True)
- t.start()
- self.threads.append(t)
+ else:
+ self._single_builder = builderthread.BuilderThread(
+ self, -1, mrproper, per_board_out_dir)
ignore_lines = ['(make.*Waiting for unfinished)', '(Segmentation fault)']
self.re_make_err = re.compile('|'.join(ignore_lines))
@@ -1531,11 +1538,12 @@
"""Get the directory path to the working dir for a thread.
Args:
- thread_num: Number of thread to check.
+ thread_num: Number of thread to check (-1 for main process, which
+ is treated as 0)
"""
if self.work_in_output:
return self._working_dir
- return os.path.join(self._working_dir, '%02d' % thread_num)
+ return os.path.join(self._working_dir, '%02d' % max(thread_num, 0))
def _PrepareThread(self, thread_num, setup_git):
"""Prepare the working directory for a thread.
@@ -1594,7 +1602,9 @@
if git-worktree is available, or clones the repo if it isn't.
Args:
- max_threads: Maximum number of threads we expect to need.
+ max_threads: Maximum number of threads we expect to need. If 0 then
+ 1 is set up, since the main process still needs somewhere to
+ work
setup_git: True to set up a git worktree or a git clone
"""
builderthread.Mkdir(self._working_dir)
@@ -1608,7 +1618,9 @@
gitutil.PruneWorktrees(src_dir)
else:
setup_git = 'clone'
- for thread in range(max_threads):
+
+ # Always do at least one thread
+ for thread in range(max(max_threads, 1)):
self._PrepareThread(thread, setup_git)
def _GetOutputSpaceRemovals(self):
@@ -1686,16 +1698,20 @@
job.keep_outputs = keep_outputs
job.work_in_output = self.work_in_output
job.step = self._step
- self.queue.put(job)
+ if self.num_threads:
+ self.queue.put(job)
+ else:
+ results = self._single_builder.RunJob(job)
- term = threading.Thread(target=self.queue.join)
- term.setDaemon(True)
- term.start()
- while term.is_alive():
- term.join(100)
+ if self.num_threads:
+ term = threading.Thread(target=self.queue.join)
+ term.setDaemon(True)
+ term.start()
+ while term.is_alive():
+ term.join(100)
- # Wait until we have processed all output
- self.out_queue.join()
+ # Wait until we have processed all output
+ self.out_queue.join()
Print()
msg = 'Completed: %d total built' % self.count
diff --git a/tools/buildman/builderthread.py b/tools/buildman/builderthread.py
index d664868..6c6dbd7 100644
--- a/tools/buildman/builderthread.py
+++ b/tools/buildman/builderthread.py
@@ -89,7 +89,8 @@
Members:
builder: The builder which contains information we might need
thread_num: Our thread number (0-n-1), used to decide on a
- temporary directory
+ temporary directory. If this is -1 then there are no threads
+ and we are the (only) main process
"""
def __init__(self, builder, thread_num, mrproper, per_board_out_dir):
"""Set up a new builder thread"""
@@ -445,6 +446,9 @@
Args:
job: Job to build
+
+ Returns:
+ List of Result objects
"""
brd = job.board
work_dir = self.builder.GetThreadDir(self.thread_num)
@@ -508,7 +512,10 @@
# We have the build results, so output the result
self._WriteResult(result, job.keep_outputs, job.work_in_output)
- self.builder.out_queue.put(result)
+ if self.thread_num != -1:
+ self.builder.out_queue.put(result)
+ else:
+ self.builder.ProcessResult(result)
else:
# Just build the currently checked-out build
result, request_config = self.RunCommit(None, brd, work_dir, True,
@@ -517,7 +524,10 @@
work_in_output=job.work_in_output)
result.commit_upto = 0
self._WriteResult(result, job.keep_outputs, job.work_in_output)
- self.builder.out_queue.put(result)
+ if self.thread_num != -1:
+ self.builder.out_queue.put(result)
+ else:
+ self.builder.ProcessResult(result)
def run(self):
"""Our thread's run function
diff --git a/tools/buildman/cmdline.py b/tools/buildman/cmdline.py
index 680c072..274b5ac 100644
--- a/tools/buildman/cmdline.py
+++ b/tools/buildman/cmdline.py
@@ -97,7 +97,8 @@
parser.add_option('-t', '--test', action='store_true', dest='test',
default=False, help='run tests')
parser.add_option('-T', '--threads', type='int',
- default=None, help='Number of builder threads to use')
+ default=None,
+ help='Number of builder threads to use (0=single-thread)')
parser.add_option('-u', '--show_unknown', action='store_true',
default=False, help='Show boards with unknown build result')
parser.add_option('-U', '--show-environment', action='store_true',
diff --git a/tools/buildman/control.py b/tools/buildman/control.py
index fe874b8..a767570 100644
--- a/tools/buildman/control.py
+++ b/tools/buildman/control.py
@@ -294,7 +294,7 @@
# By default we have one thread per CPU. But if there are not enough jobs
# we can have fewer threads and use a high '-j' value for make.
- if not options.threads:
+ if options.threads is None:
options.threads = min(multiprocessing.cpu_count(), len(selected))
if not options.jobs:
options.jobs = max(1, (multiprocessing.cpu_count() +
diff --git a/tools/buildman/test.py b/tools/buildman/test.py
index 1a259d5..b9c65c0 100644
--- a/tools/buildman/test.py
+++ b/tools/buildman/test.py
@@ -187,7 +187,7 @@
expect += col.Color(expected_colour, ' %s' % board)
self.assertEqual(text, expect)
- def _SetupTest(self, echo_lines=False, **kwdisplay_args):
+ def _SetupTest(self, echo_lines=False, threads=1, **kwdisplay_args):
"""Set up the test by running a build and summary
Args:
@@ -199,8 +199,8 @@
Returns:
Iterator containing the output lines, each a PrintLine() object
"""
- build = builder.Builder(self.toolchains, self.base_dir, None, 1, 2,
- checkout=False, show_unknown=False)
+ build = builder.Builder(self.toolchains, self.base_dir, None, threads,
+ 2, checkout=False, show_unknown=False)
build.do_make = self.Make
board_selected = self.boards.GetSelectedDict()
@@ -438,6 +438,12 @@
filter_migration_warnings=True)
self._CheckOutput(lines, filter_migration_warnings=True)
+ def testSingleThread(self):
+ """Test operation without threading"""
+ lines = self._SetupTest(show_errors=True, threads=0)
+ self._CheckOutput(lines, list_error_boards=False,
+ filter_dtb_warnings=False)
+
def _testGit(self):
"""Test basic builder operation by building a branch"""
options = Options()
diff --git a/tools/imx8mimage.c b/tools/imx8mimage.c
index bc4ee79..9985b95 100644
--- a/tools/imx8mimage.c
+++ b/tools/imx8mimage.c
@@ -32,6 +32,8 @@
#define HDMI_FW_SIZE 0x17000 /* Use Last 0x1000 for IVT and CSF */
#define ALIGN_SIZE 0x1000
+#define ALIGN_IMX(x, a) __ALIGN_MASK_IMX((x), (__typeof__(x))(a) - 1, a)
+#define __ALIGN_MASK_IMX(x, mask, mask2) (((x) + (mask)) / (mask2) * (mask2))
static uint32_t get_cfg_value(char *token, char *name, int linenr)
{
@@ -342,7 +344,7 @@
fit_size = fdt_totalsize(&image_header);
- fit_size = ALIGN(fit_size, ALIGN_SIZE);
+ fit_size = ALIGN_IMX(fit_size, ALIGN_SIZE);
ret = lseek(fd, fit_offset + fit_size, SEEK_SET);
if (ret < 0) {
@@ -446,7 +448,7 @@
* Aligned to 104KB = 92KB FW image + 0x8000
* (IVT and alignment) + 0x4000 (second IVT + CSF)
*/
- file_off += ALIGN(sbuf.st_size,
+ file_off += ALIGN_IMX(sbuf.st_size,
HDMI_FW_SIZE + 0x2000 + 0x1000);
}
@@ -479,7 +481,7 @@
imx_header[IMAGE_IVT_ID].boot_data.start =
imx_header[IMAGE_IVT_ID].fhdr.self - ivt_offset;
imx_header[IMAGE_IVT_ID].boot_data.size =
- ALIGN(sbuf.st_size + sizeof(imx_header_v3_t) + ivt_offset,
+ ALIGN_IMX(sbuf.st_size + sizeof(imx_header_v3_t) + ivt_offset,
sector_size);
image_off = header_image_off + sizeof(imx_header_v3_t);
diff --git a/tools/mkeficapsule.c b/tools/mkeficapsule.c
index 1624949..f272512 100644
--- a/tools/mkeficapsule.c
+++ b/tools/mkeficapsule.c
@@ -263,7 +263,7 @@
#ifdef DEBUG
printf("For output: %s\n", path);
- printf("\tbin: %s\n\ttype: %pUl\n" bin, guid);
+ printf("\tbin: %s\n\ttype: %pUl\n", bin, guid);
printf("\tindex: %ld\n\tinstance: %ld\n", index, instance);
#endif
@@ -278,7 +278,7 @@
}
data = malloc(bin_stat.st_size);
if (!data) {
- printf("cannot allocate memory: %lx\n", bin_stat.st_size);
+ printf("cannot allocate memory: %zx\n", (size_t)bin_stat.st_size);
goto err_1;
}
f = fopen(path, "w");
@@ -297,7 +297,7 @@
size = fwrite(&header, 1, sizeof(header), f);
if (size < sizeof(header)) {
- printf("write failed (%lx)\n", size);
+ printf("write failed (%zx)\n", size);
goto err_3;
}
@@ -306,13 +306,13 @@
capsule.payload_item_count = 1;
size = fwrite(&capsule, 1, sizeof(capsule), f);
if (size < (sizeof(capsule))) {
- printf("write failed (%lx)\n", size);
+ printf("write failed (%zx)\n", size);
goto err_3;
}
offset = sizeof(capsule) + sizeof(u64);
size = fwrite(&offset, 1, sizeof(offset), f);
if (size < sizeof(offset)) {
- printf("write failed (%lx)\n", size);
+ printf("write failed (%zx)\n", size);
goto err_3;
}
@@ -329,17 +329,17 @@
size = fwrite(&image, 1, sizeof(image), f);
if (size < sizeof(image)) {
- printf("write failed (%lx)\n", size);
+ printf("write failed (%zx)\n", size);
goto err_3;
}
size = fread(data, 1, bin_stat.st_size, g);
if (size < bin_stat.st_size) {
- printf("read failed (%lx)\n", size);
+ printf("read failed (%zx)\n", size);
goto err_3;
}
size = fwrite(data, 1, bin_stat.st_size, f);
if (size < bin_stat.st_size) {
- printf("write failed (%lx)\n", size);
+ printf("write failed (%zx)\n", size);
goto err_3;
}
diff --git a/tools/patman/series.py b/tools/patman/series.py
index a6746e8..41a1173 100644
--- a/tools/patman/series.py
+++ b/tools/patman/series.py
@@ -271,7 +271,7 @@
cc += get_maintainer.GetMaintainer(dir_list, commit.patch)
for x in set(cc) & set(settings.bounces):
print(col.Color(col.YELLOW, 'Skipping "%s"' % x))
- cc = set(cc) - set(settings.bounces)
+ cc = list(set(cc) - set(settings.bounces))
if limit is not None:
cc = cc[:limit]
all_ccs += cc