tree 0fe5d9dd4d0bb149f3f6fd30347d4a930b71aaea
parent 5b6b3dc7bc924bc54c02d0968455e80242dedd1f
author Swapnil Jakhade <sjakhade@cadence.com> 1643357504 +0530
committer Tom Rini <trini@konsulko.com> 1644336003 -0500

phy: cadence: Sierra: Add PHY PCS common register configurations

Add PHY PCS common register configuration sequences for single link.
Update single link PCIe register sequence accordingly.

Signed-off-by: Swapnil Jakhade <sjakhade@cadence.com>
Signed-off-by: Aswath Govindraju <a-govindraju@ti.com>