commit aa12d515e50d944ed856cdba00513e9de956b74e
author T Karthik Reddy <t.karthik.reddy@xilinx.com> Wed Apr 08 21:34:54 2020 -0600
committer Michal Simek <michal.simek@xilinx.com> Mon Apr 27 13:57:17 2020 +0200
tree 498ac555035d59437cb95c80cbf70399f3dc7e5e
parent 6b31a5b370dec4d66e6b6fd12ec4c71eb6916a15

clk: versal: Fix watchdog clock issue

Enable mux based clocks to populate LPD_LSBUS clock to xilinx_wwdt
driver. Skip reading clock rate for the mux based clocks with
parent clock id is zero.

Signed-off-by: T Karthik Reddy <t.karthik.reddy@xilinx.com>
Signed-off-by: Ashok Reddy Soma <ashok.reddy.soma@xilinx.com>

drivers/clk/clk_versal.c

diff --git a/drivers/clk/clk_versal.c b/drivers/clk/clk_versal.c
index d3673a5..075a083 100644
--- a/drivers/clk/clk_versal.c
+++ b/drivers/clk/clk_versal.c
@@ -503,6 +503,9 @@
 	     NODE_CLASS_MASK) == NODE_SUBCLASS_CLOCK_REF)
 		return versal_clock_ref(clk_id);
 
+	if (!parent_id)
+		return 0;
+
 	clk_rate = versal_clock_calc(parent_id);
 
 	if (versal_clock_div(clk_id)) {
@@ -526,7 +529,7 @@
 	     NODE_CLASS_MASK) == NODE_SUBCLASS_CLOCK_OUT &&
 	    ((clk_id >> NODE_CLASS_SHIFT) &
 	     NODE_CLASS_MASK) == NODE_CLASS_CLOCK) {
-		if (!versal_clock_gate(clk_id))
+		if (!versal_clock_gate(clk_id) && !versal_clock_mux(clk_id))
 			return -EINVAL;
 		*clk_rate = versal_clock_calc(clk_id);
 		return 0;