Merge tag 'ti-v2021.10-rc1' of https://source.denx.de/u-boot/custodians/u-boot-ti
- Enabled distro boot for all TI platforms.
- Cleanup for AM335x Guardian Board
- PRUSS rproc on AM65 platform.
- Add PMIC support for J7200
- Misc fixes for Nokia RX-51
# Conflicts:
# arch/arm/mach-omap2/am33xx/Kconfig
diff --git a/Makefile b/Makefile
index bc404c8..ca2432c 100644
--- a/Makefile
+++ b/Makefile
@@ -1125,13 +1125,6 @@
@echo >&2 "See doc/driver-model/migration.rst for more info."
@echo >&2 "===================================================="
endif
- $(call deprecated,CONFIG_DM_USB CONFIG_OF_CONTROL CONFIG_BLK,\
- USB,v2019.07,$(CONFIG_USB))
- $(call deprecated,CONFIG_DM_PCI,PCI,v2019.07,$(CONFIG_PCI))
- $(call deprecated,CONFIG_DM_VIDEO,video,v2019.07,\
- $(CONFIG_LCD)$(CONFIG_VIDEO))
- $(call deprecated,CONFIG_DM_SPI_FLASH,SPI flash,v2019.07,\
- $(CONFIG_SPI_FLASH))
$(call deprecated,CONFIG_WDT,DM watchdog,v2019.10,\
$(CONFIG_WATCHDOG)$(CONFIG_HW_WATCHDOG))
$(call deprecated,CONFIG_DM_ETH,Ethernet drivers,v2020.07,$(CONFIG_NET))
diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
index 7f493a8..9de97cc 100644
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@ -984,7 +984,7 @@
select BINMAN
select CMD_GPIO
select CMD_MMC if MMC
- select CMD_USB if DISTRO_DEFAULTS
+ select CMD_USB if DISTRO_DEFAULTS && USB_HOST
select CLK
select DM
select DM_ETH
@@ -993,7 +993,6 @@
select DM_MMC if MMC
select DM_SCSI if SCSI
select DM_SERIAL
- select DM_USB if DISTRO_DEFAULTS
select GPIO_EXTRA_HEADER
select OF_BOARD_SETUP
select OF_CONTROL
@@ -1006,8 +1005,8 @@
select SYS_NS16550
select SYS_THUMB_BUILD if !ARM64
select USB if DISTRO_DEFAULTS
- select USB_KEYBOARD if DISTRO_DEFAULTS
- select USB_STORAGE if DISTRO_DEFAULTS
+ select USB_KEYBOARD if DISTRO_DEFAULTS && USB_HOST
+ select USB_STORAGE if DISTRO_DEFAULTS && USB_HOST
select SPL_USE_TINY_PRINTF
select USE_PREBOOT
select SYS_RELOC_GD_ENV_ADDR
@@ -1035,7 +1034,6 @@
select DM_GPIO
select DM_MMC if MMC
select DM_SERIAL
- select DM_USB if USB
select OF_CONTROL
select SYSRESET
select TIMER
@@ -1078,7 +1076,6 @@
select DM_SERIAL
select DM_SPI
select DM_SPI_FLASH
- select DM_USB if USB
select GPIO_EXTRA_HEADER
select OF_CONTROL
select SPI
@@ -1122,7 +1119,6 @@
select DM_SERIAL
select DM_SPI if SPI
select DM_SPI_FLASH if DM_SPI
- select DM_USB if USB
select FIRMWARE
select GPIO_EXTRA_HEADER
select OF_CONTROL
@@ -1177,7 +1173,6 @@
select DM_ETH
select BLK
select USB
- select DM_USB
config TARGET_TOTAL_COMPUTE
bool "Support Total Compute Platform"
@@ -1343,7 +1338,6 @@
select ARM64
select DM
select DM_SERIAL
- select DM_USB
select GPIO_EXTRA_HEADER
select OF_CONTROL
select PL01X_SERIAL
@@ -1681,7 +1675,6 @@
select DM_SCSI
select DM_SERIAL
select DM_SPI
- select DM_USB
select GPIO_EXTRA_HEADER
select SPL_DM if SPL
select SPL_DM_SPI if SPL
@@ -1708,7 +1701,6 @@
select DM_MTD
select DM_RESET
select DM_SERIAL
- select DM_USB
select OF_BOARD_SETUP
select OF_CONTROL
select OF_LIBFDT
@@ -1809,7 +1801,6 @@
select DM_SERIAL
select DM_SPI
select DM_SPI_FLASH
- select DM_USB if USB
select ENABLE_ARM_SOC_BOOT0_HOOK
select OF_CONTROL
select SPI
diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile
index 708ce2d..90e3004 100644
--- a/arch/arm/dts/Makefile
+++ b/arch/arm/dts/Makefile
@@ -867,6 +867,7 @@
imx8mm-venice-gw71xx-0x.dtb \
imx8mm-venice-gw72xx-0x.dtb \
imx8mm-venice-gw73xx-0x.dtb \
+ imx8mm-venice-gw7901.dtb \
imx8mm-verdin.dtb \
phycore-imx8mm.dtb \
imx8mn-ddr4-evk.dtb \
diff --git a/arch/arm/dts/imx8mm-venice-gw7901-u-boot.dtsi b/arch/arm/dts/imx8mm-venice-gw7901-u-boot.dtsi
new file mode 100644
index 0000000..6992d91
--- /dev/null
+++ b/arch/arm/dts/imx8mm-venice-gw7901-u-boot.dtsi
@@ -0,0 +1,117 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright 2020 Gateworks Corporation
+ */
+
+&{/soc@0} {
+ u-boot,dm-pre-reloc;
+ u-boot,dm-spl;
+};
+
+&clk {
+ u-boot,dm-spl;
+ u-boot,dm-pre-reloc;
+ /delete-property/ assigned-clocks;
+ /delete-property/ assigned-clock-parents;
+ /delete-property/ assigned-clock-rates;
+};
+
+&osc_24m {
+ u-boot,dm-spl;
+ u-boot,dm-pre-reloc;
+};
+
+&aips1 {
+ u-boot,dm-spl;
+ u-boot,dm-pre-reloc;
+};
+
+&aips2 {
+ u-boot,dm-spl;
+};
+
+&aips3 {
+ u-boot,dm-spl;
+};
+
+&iomuxc {
+ u-boot,dm-spl;
+};
+
+&gpio1 {
+ u-boot,dm-spl;
+};
+
+&gpio2 {
+ u-boot,dm-spl;
+};
+
+&gpio3 {
+ u-boot,dm-spl;
+};
+
+&gpio4 {
+ u-boot,dm-spl;
+};
+
+&gpio5 {
+ u-boot,dm-spl;
+};
+
+&uart2 {
+ u-boot,dm-spl;
+};
+
+&pinctrl_uart2 {
+ u-boot,dm-spl;
+};
+
+&usdhc2 {
+ u-boot,dm-spl;
+};
+
+&pinctrl_usdhc2 {
+ u-boot,dm-spl;
+};
+
+&usdhc3 {
+ u-boot,dm-spl;
+};
+
+&pinctrl_usdhc3 {
+ u-boot,dm-spl;
+};
+
+&i2c1 {
+ u-boot,dm-spl;
+};
+
+&pinctrl_i2c1 {
+ u-boot,dm-spl;
+};
+
+&i2c2 {
+ u-boot,dm-spl;
+};
+
+&pinctrl_i2c2 {
+ u-boot,dm-spl;
+};
+
+&fec1 {
+ phy-reset-gpios = <&gpio4 19 GPIO_ACTIVE_LOW>;
+ phy-reset-duration = <1>;
+ phy-reset-post-delay = <1>;
+};
+
+&{/soc@0/bus@30800000/i2c@30a30000/pmic@4b} {
+ u-boot,dm-spl;
+};
+
+&{/soc@0/bus@30800000/i2c@30a30000/pmic@4b/regulators} {
+ u-boot,dm-spl;
+};
+
+&pinctrl_pmic {
+ u-boot,dm-spl;
+};
diff --git a/arch/arm/dts/imx8mm-venice-gw7901.dts b/arch/arm/dts/imx8mm-venice-gw7901.dts
new file mode 100644
index 0000000..124e1e4
--- /dev/null
+++ b/arch/arm/dts/imx8mm-venice-gw7901.dts
@@ -0,0 +1,1055 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright 2020 Gateworks Corporation
+ */
+
+/dts-v1/;
+
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/input/linux-event-codes.h>
+#include <dt-bindings/leds/common.h>
+
+#include "imx8mm.dtsi"
+
+/ {
+ model = "Gateworks Venice GW7901 i.MX8MM board";
+ compatible = "gw,imx8mm-gw7901", "fsl,imx8mm";
+
+ aliases {
+ ethernet0 = &fec1;
+ ethernet1 = &lan1;
+ ethernet2 = &lan2;
+ ethernet3 = &lan3;
+ ethernet4 = &lan4;
+ usb0 = &usbotg1;
+ usb1 = &usbotg2;
+ };
+
+ chosen {
+ stdout-path = &uart2;
+ };
+
+ memory@40000000 {
+ device_type = "memory";
+ reg = <0x0 0x40000000 0 0x80000000>;
+ };
+
+ gpio-keys {
+ compatible = "gpio-keys";
+
+ user-pb {
+ label = "user_pb";
+ gpios = <&gpio 2 GPIO_ACTIVE_LOW>;
+ linux,code = <BTN_0>;
+ };
+
+ user-pb1x {
+ label = "user_pb1x";
+ linux,code = <BTN_1>;
+ interrupt-parent = <&gsc>;
+ interrupts = <0>;
+ };
+
+ key-erased {
+ label = "key_erased";
+ linux,code = <BTN_2>;
+ interrupt-parent = <&gsc>;
+ interrupts = <1>;
+ };
+
+ eeprom-wp {
+ label = "eeprom_wp";
+ linux,code = <BTN_3>;
+ interrupt-parent = <&gsc>;
+ interrupts = <2>;
+ };
+
+ tamper {
+ label = "tamper";
+ linux,code = <BTN_4>;
+ interrupt-parent = <&gsc>;
+ interrupts = <5>;
+ };
+
+ switch-hold {
+ label = "switch_hold";
+ linux,code = <BTN_5>;
+ interrupt-parent = <&gsc>;
+ interrupts = <7>;
+ };
+ };
+
+ led-controller {
+ compatible = "gpio-leds";
+
+ led-0 {
+ function = LED_FUNCTION_STATUS;
+ color = <LED_COLOR_ID_RED>;
+ label = "led01_red";
+ gpios = <&leds_gpio 0 GPIO_ACTIVE_HIGH>;
+ default-state = "off";
+ };
+
+ led-1 {
+ function = LED_FUNCTION_STATUS;
+ color = <LED_COLOR_ID_GREEN>;
+ label = "led01_grn";
+ gpios = <&leds_gpio 1 GPIO_ACTIVE_HIGH>;
+ default-state = "off";
+ };
+
+ led-2 {
+ function = LED_FUNCTION_STATUS;
+ color = <LED_COLOR_ID_RED>;
+ label = "led02_red";
+ gpios = <&leds_gpio 2 GPIO_ACTIVE_HIGH>;
+ default-state = "off";
+ };
+
+ led-3 {
+ function = LED_FUNCTION_STATUS;
+ color = <LED_COLOR_ID_GREEN>;
+ label = "led02_grn";
+ gpios = <&leds_gpio 3 GPIO_ACTIVE_HIGH>;
+ default-state = "off";
+ };
+
+ led-4 {
+ function = LED_FUNCTION_STATUS;
+ color = <LED_COLOR_ID_RED>;
+ label = "led03_red";
+ gpios = <&leds_gpio 4 GPIO_ACTIVE_HIGH>;
+ default-state = "off";
+ };
+
+ led-5 {
+ function = LED_FUNCTION_STATUS;
+ color = <LED_COLOR_ID_GREEN>;
+ label = "led03_grn";
+ gpios = <&leds_gpio 5 GPIO_ACTIVE_HIGH>;
+ default-state = "off";
+ };
+
+ led-6 {
+ function = LED_FUNCTION_STATUS;
+ color = <LED_COLOR_ID_RED>;
+ label = "led04_red";
+ gpios = <&leds_gpio 8 GPIO_ACTIVE_HIGH>;
+ default-state = "off";
+ };
+
+ led-7 {
+ function = LED_FUNCTION_STATUS;
+ color = <LED_COLOR_ID_GREEN>;
+ label = "led04_grn";
+ gpios = <&leds_gpio 9 GPIO_ACTIVE_HIGH>;
+ default-state = "off";
+ };
+
+ led-8 {
+ function = LED_FUNCTION_STATUS;
+ color = <LED_COLOR_ID_RED>;
+ label = "led05_red";
+ gpios = <&leds_gpio 10 GPIO_ACTIVE_HIGH>;
+ default-state = "off";
+ };
+
+ led-9 {
+ function = LED_FUNCTION_STATUS;
+ color = <LED_COLOR_ID_GREEN>;
+ label = "led05_grn";
+ gpios = <&leds_gpio 11 GPIO_ACTIVE_HIGH>;
+ default-state = "off";
+ };
+
+ led-a {
+ function = LED_FUNCTION_STATUS;
+ color = <LED_COLOR_ID_RED>;
+ label = "led06_red";
+ gpios = <&leds_gpio 12 GPIO_ACTIVE_HIGH>;
+ default-state = "off";
+ };
+
+ led-b {
+ function = LED_FUNCTION_STATUS;
+ color = <LED_COLOR_ID_GREEN>;
+ label = "led06_grn";
+ gpios = <&leds_gpio 13 GPIO_ACTIVE_HIGH>;
+ default-state = "off";
+ };
+ };
+
+ reg_3p3v: regulator-3p3v {
+ compatible = "regulator-fixed";
+ regulator-name = "3P3V";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ };
+
+ regulator-ioexp {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_reg_ioexp>;
+ compatible = "regulator-fixed";
+ regulator-name = "ioexp";
+ gpio = <&gpio4 21 GPIO_ACTIVE_HIGH>;
+ enable-active-high;
+ startup-delay-us = <100>;
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-always-on;
+ };
+
+ regulator-isouart {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_reg_isouart>;
+ compatible = "regulator-fixed";
+ regulator-name = "iso_uart";
+ gpio = <&gpio1 13 GPIO_ACTIVE_LOW>;
+ startup-delay-us = <100>;
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-always-on;
+ };
+
+ reg_usb2_vbus: regulator-usb2 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_reg_usb2>;
+ compatible = "regulator-fixed";
+ regulator-name = "usb_usb2_vbus";
+ gpio = <&gpio4 2 GPIO_ACTIVE_HIGH>;
+ enable-active-high;
+ regulator-min-microvolt = <5000000>;
+ regulator-max-microvolt = <5000000>;
+ };
+
+ reg_wifi: regulator-wifi {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_reg_wl>;
+ compatible = "regulator-fixed";
+ regulator-name = "wifi";
+ gpio = <&gpio3 25 GPIO_ACTIVE_HIGH>;
+ enable-active-high;
+ startup-delay-us = <100>;
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ };
+};
+
+&ddrc {
+ operating-points-v2 = <&ddrc_opp_table>;
+
+ ddrc_opp_table: opp-table {
+ compatible = "operating-points-v2";
+
+ opp-25M {
+ opp-hz = /bits/ 64 <25000000>;
+ };
+
+ opp-100M {
+ opp-hz = /bits/ 64 <100000000>;
+ };
+
+ opp-750M {
+ opp-hz = /bits/ 64 <750000000>;
+ };
+ };
+};
+
+&ecspi1 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_spi1>;
+ cs-gpios = <&gpio5 9 GPIO_ACTIVE_LOW>;
+ status = "okay";
+
+ flash@0 {
+ compatible = "jedec,spi-nor";
+ reg = <0>;
+ spi-max-frequency = <40000000>;
+ status = "okay";
+ };
+};
+
+&fec1 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_fec1>;
+ phy-mode = "rgmii-id";
+ local-mac-address = [00 00 00 00 00 00];
+ status = "okay";
+
+ fixed-link {
+ speed = <1000>;
+ full-duplex;
+ };
+};
+
+&i2c1 {
+ clock-frequency = <100000>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_i2c1>;
+ status = "okay";
+
+ gsc: gsc@20 {
+ compatible = "gw,gsc";
+ reg = <0x20>;
+ pinctrl-0 = <&pinctrl_gsc>;
+ interrupt-parent = <&gpio4>;
+ interrupts = <16 IRQ_TYPE_EDGE_FALLING>;
+ interrupt-controller;
+ #interrupt-cells = <1>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ adc {
+ compatible = "gw,gsc-adc";
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ channel@6 {
+ gw,mode = <0>;
+ reg = <0x06>;
+ label = "temp";
+ };
+
+ channel@8 {
+ gw,mode = <1>;
+ reg = <0x08>;
+ label = "vdd_bat";
+ };
+
+ channel@82 {
+ gw,mode = <2>;
+ reg = <0x82>;
+ label = "vin_aux1";
+ gw,voltage-divider-ohms = <22100 1000>;
+ };
+
+ channel@84 {
+ gw,mode = <2>;
+ reg = <0x84>;
+ label = "vin_aux2";
+ gw,voltage-divider-ohms = <22100 1000>;
+ };
+
+ channel@86 {
+ gw,mode = <2>;
+ reg = <0x86>;
+ label = "vdd_vin";
+ gw,voltage-divider-ohms = <22100 1000>;
+ };
+
+ channel@88 {
+ gw,mode = <2>;
+ reg = <0x88>;
+ label = "vdd_3p3";
+ gw,voltage-divider-ohms = <10000 10000>;
+ };
+
+ channel@8c {
+ gw,mode = <2>;
+ reg = <0x8c>;
+ label = "vdd_2p5";
+ gw,voltage-divider-ohms = <10000 10000>;
+ };
+
+ channel@8e {
+ gw,mode = <2>;
+ reg = <0x8e>;
+ label = "vdd_0p95";
+ };
+
+ channel@90 {
+ gw,mode = <2>;
+ reg = <0x90>;
+ label = "vdd_soc";
+ };
+
+ channel@92 {
+ gw,mode = <2>;
+ reg = <0x92>;
+ label = "vdd_arm";
+ };
+
+ channel@98 {
+ gw,mode = <2>;
+ reg = <0x98>;
+ label = "vdd_1p8";
+ };
+
+ channel@9a {
+ gw,mode = <2>;
+ reg = <0x9a>;
+ label = "vdd_1p2";
+ };
+
+ channel@9c {
+ gw,mode = <2>;
+ reg = <0x9c>;
+ label = "vdd_dram";
+ };
+
+ channel@a2 {
+ gw,mode = <2>;
+ reg = <0xa2>;
+ label = "vdd_gsc";
+ gw,voltage-divider-ohms = <10000 10000>;
+ };
+ };
+ };
+
+ gpio: gpio@23 {
+ compatible = "nxp,pca9555";
+ reg = <0x23>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ interrupt-parent = <&gsc>;
+ interrupts = <4>;
+ };
+
+ eeprom@50 {
+ compatible = "atmel,24c02";
+ reg = <0x50>;
+ pagesize = <16>;
+ };
+
+ eeprom@51 {
+ compatible = "atmel,24c02";
+ reg = <0x51>;
+ pagesize = <16>;
+ };
+
+ eeprom@52 {
+ compatible = "atmel,24c02";
+ reg = <0x52>;
+ pagesize = <16>;
+ };
+
+ eeprom@53 {
+ compatible = "atmel,24c02";
+ reg = <0x53>;
+ pagesize = <16>;
+ };
+
+ rtc@68 {
+ compatible = "dallas,ds1672";
+ reg = <0x68>;
+ };
+};
+
+&i2c2 {
+ clock-frequency = <400000>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_i2c2>;
+ status = "okay";
+
+ pmic@4b {
+ compatible = "rohm,bd71847";
+ reg = <0x4b>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_pmic>;
+ interrupt-parent = <&gpio3>;
+ interrupts = <20 IRQ_TYPE_LEVEL_LOW>;
+ rohm,reset-snvs-powered;
+ #clock-cells = <0>;
+ clocks = <&osc_32k 0>;
+ clock-output-names = "clk-32k-out";
+
+ regulators {
+ /* vdd_soc: 0.805-0.900V (typ=0.8V) */
+ BUCK1 {
+ regulator-name = "buck1";
+ regulator-min-microvolt = <700000>;
+ regulator-max-microvolt = <1300000>;
+ regulator-boot-on;
+ regulator-always-on;
+ regulator-ramp-delay = <1250>;
+ };
+
+ /* vdd_arm: 0.805-1.0V (typ=0.9V) */
+ BUCK2 {
+ regulator-name = "buck2";
+ regulator-min-microvolt = <700000>;
+ regulator-max-microvolt = <1300000>;
+ regulator-boot-on;
+ regulator-always-on;
+ regulator-ramp-delay = <1250>;
+ rohm,dvs-run-voltage = <1000000>;
+ rohm,dvs-idle-voltage = <900000>;
+ };
+
+ /* vdd_0p9: 0.805-1.0V (typ=0.9V) */
+ BUCK3 {
+ regulator-name = "buck3";
+ regulator-min-microvolt = <700000>;
+ regulator-max-microvolt = <1350000>;
+ regulator-boot-on;
+ regulator-always-on;
+ };
+
+ /* vdd_3p3 */
+ BUCK4 {
+ regulator-name = "buck4";
+ regulator-min-microvolt = <3000000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-boot-on;
+ regulator-always-on;
+ };
+
+ /* vdd_1p8 */
+ BUCK5 {
+ regulator-name = "buck5";
+ regulator-min-microvolt = <1605000>;
+ regulator-max-microvolt = <1995000>;
+ regulator-boot-on;
+ regulator-always-on;
+ };
+
+ /* vdd_dram */
+ BUCK6 {
+ regulator-name = "buck6";
+ regulator-min-microvolt = <800000>;
+ regulator-max-microvolt = <1400000>;
+ regulator-boot-on;
+ regulator-always-on;
+ };
+
+ /* nvcc_snvs_1p8 */
+ LDO1 {
+ regulator-name = "ldo1";
+ regulator-min-microvolt = <1600000>;
+ regulator-max-microvolt = <1900000>;
+ regulator-boot-on;
+ regulator-always-on;
+ };
+
+ /* vdd_snvs_0p8 */
+ LDO2 {
+ regulator-name = "ldo2";
+ regulator-min-microvolt = <800000>;
+ regulator-max-microvolt = <900000>;
+ regulator-boot-on;
+ regulator-always-on;
+ };
+
+ /* vdda_1p8 */
+ LDO3 {
+ regulator-name = "ldo3";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-boot-on;
+ regulator-always-on;
+ };
+
+ LDO4 {
+ regulator-name = "ldo4";
+ regulator-min-microvolt = <900000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-boot-on;
+ regulator-always-on;
+ };
+
+ LDO6 {
+ regulator-name = "ldo6";
+ regulator-min-microvolt = <900000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-boot-on;
+ regulator-always-on;
+ };
+ };
+ };
+};
+
+&i2c3 {
+ clock-frequency = <400000>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_i2c3>;
+ status = "okay";
+
+ leds_gpio: gpio@20 {
+ compatible = "nxp,pca9555";
+ reg = <0x20>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ };
+
+ switch: switch@5f {
+ compatible = "microchip,ksz9897";
+ reg = <0x5f>;
+ pinctrl-0 = <&pinctrl_ksz>;
+ interrupt-parent = <&gpio4>;
+ interrupts = <18 IRQ_TYPE_EDGE_FALLING>;
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ lan1: port@0 {
+ reg = <0>;
+ label = "lan1";
+ local-mac-address = [00 00 00 00 00 00];
+ phy-handle = <&sw_phy0>;
+ phy-mode = "internal";
+ };
+
+ lan2: port@1 {
+ reg = <1>;
+ label = "lan2";
+ local-mac-address = [00 00 00 00 00 00];
+ phy-handle = <&sw_phy1>;
+ phy-mode = "internal";
+ };
+
+ lan3: port@2 {
+ reg = <2>;
+ label = "lan3";
+ local-mac-address = [00 00 00 00 00 00];
+ phy-handle = <&sw_phy2>;
+ phy-mode = "internal";
+ };
+
+ lan4: port@3 {
+ reg = <3>;
+ label = "lan4";
+ local-mac-address = [00 00 00 00 00 00];
+ phy-handle = <&sw_phy3>;
+ phy-mode = "internal";
+ };
+
+ port@5 {
+ reg = <5>;
+ label = "cpu";
+ ethernet = <&fec1>;
+ phy-mode = "rgmii-id";
+
+ fixed-link {
+ speed = <1000>;
+ full-duplex;
+ };
+ };
+ };
+
+ mdios {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ mdio@0 {
+ reg = <0>;
+ compatible = "microchip,ksz-mdio";
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ sw_phy0: ethernet-phy@0 {
+ reg = <0x0>;
+ };
+
+ sw_phy1: ethernet-phy@1 {
+ reg = <0x1>;
+ };
+
+ sw_phy2: ethernet-phy@2 {
+ reg = <0x2>;
+ };
+
+ sw_phy3: ethernet-phy@3 {
+ reg = <0x3>;
+ };
+ };
+ };
+ };
+
+ crypto@60 {
+ compatible = "atmel,atecc508a";
+ reg = <0x60>;
+ };
+};
+
+&i2c4 {
+ clock-frequency = <400000>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_i2c4>;
+ status = "okay";
+};
+
+&uart1 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_uart1>, <&pinctrl_uart1_gpio>;
+ rts-gpios = <&gpio1 10 GPIO_ACTIVE_LOW>;
+ cts-gpios = <&gpio1 12 GPIO_ACTIVE_LOW>;
+ dtr-gpios = <&gpio1 14 GPIO_ACTIVE_LOW>;
+ dsr-gpios = <&gpio1 1 GPIO_ACTIVE_LOW>;
+ dcd-gpios = <&gpio1 11 GPIO_ACTIVE_LOW>;
+ status = "okay";
+};
+
+/* console */
+&uart2 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_uart2>;
+ status = "okay";
+};
+
+&uart3 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_uart3>, <&pinctrl_uart3_gpio>;
+ cts-gpios = <&gpio4 10 GPIO_ACTIVE_LOW>;
+ rts-gpios = <&gpio4 9 GPIO_ACTIVE_LOW>;
+ status = "okay";
+};
+
+&uart4 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_uart4>, <&pinctrl_uart4_gpio>;
+ cts-gpios = <&gpio5 11 GPIO_ACTIVE_LOW>;
+ rts-gpios = <&gpio5 12 GPIO_ACTIVE_LOW>;
+ status = "okay";
+};
+
+&usbotg1 {
+ dr_mode = "host";
+ disable-over-current;
+ status = "okay";
+};
+
+&usbotg2 {
+ dr_mode = "host";
+ vbus-supply = <®_usb2_vbus>;
+ status = "okay";
+};
+
+/* SDIO WiFi */
+&usdhc1 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_usdhc1>;
+ bus-width = <4>;
+ non-removable;
+ vmmc-supply = <®_wifi>;
+ status = "okay";
+};
+
+/* microSD */
+&usdhc2 {
+ pinctrl-names = "default", "state_100mhz", "state_200mhz";
+ pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>;
+ pinctrl-1 = <&pinctrl_usdhc2_100mhz>, <&pinctrl_usdhc2_gpio>;
+ pinctrl-2 = <&pinctrl_usdhc2_200mhz>, <&pinctrl_usdhc2_gpio>;
+ cd-gpios = <&gpio2 12 GPIO_ACTIVE_LOW>;
+ bus-width = <4>;
+ vmmc-supply = <®_3p3v>;
+ status = "okay";
+};
+
+/* eMMC */
+&usdhc3 {
+ pinctrl-names = "default", "state_100mhz", "state_200mhz";
+ pinctrl-0 = <&pinctrl_usdhc3>;
+ pinctrl-1 = <&pinctrl_usdhc3_100mhz>;
+ pinctrl-2 = <&pinctrl_usdhc3_200mhz>;
+ bus-width = <8>;
+ non-removable;
+ status = "okay";
+};
+
+&wdog1 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_wdog>;
+ fsl,ext-reset-output;
+ status = "okay";
+};
+
+&iomuxc {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_hog>;
+
+ pinctrl_hog: hoggrp {
+ fsl,pins = <
+ MX8MM_IOMUXC_SPDIF_TX_GPIO5_IO3 0x40000041 /* DIG2_OUT */
+ MX8MM_IOMUXC_SPDIF_RX_GPIO5_IO4 0x40000041 /* DIG2_IN */
+ MX8MM_IOMUXC_GPIO1_IO06_GPIO1_IO6 0x40000041 /* DIG1_IN */
+ MX8MM_IOMUXC_GPIO1_IO07_GPIO1_IO7 0x40000041 /* DIG1_OUT */
+ MX8MM_IOMUXC_SAI3_RXD_GPIO4_IO30 0x40000041 /* SIM2DET# */
+ MX8MM_IOMUXC_SAI3_RXC_GPIO4_IO29 0x40000041 /* SIM1DET# */
+ MX8MM_IOMUXC_SPDIF_EXT_CLK_GPIO5_IO5 0x40000041 /* SIM2SEL */
+ >;
+ };
+
+ pinctrl_fec1: fec1grp {
+ fsl,pins = <
+ MX8MM_IOMUXC_ENET_MDC_ENET1_MDC 0x3
+ MX8MM_IOMUXC_ENET_MDIO_ENET1_MDIO 0x3
+ MX8MM_IOMUXC_ENET_TD3_ENET1_RGMII_TD3 0x1f
+ MX8MM_IOMUXC_ENET_TD2_ENET1_RGMII_TD2 0x1f
+ MX8MM_IOMUXC_ENET_TD1_ENET1_RGMII_TD1 0x1f
+ MX8MM_IOMUXC_ENET_TD0_ENET1_RGMII_TD0 0x1f
+ MX8MM_IOMUXC_ENET_RD3_ENET1_RGMII_RD3 0x91
+ MX8MM_IOMUXC_ENET_RD2_ENET1_RGMII_RD2 0x91
+ MX8MM_IOMUXC_ENET_RD1_ENET1_RGMII_RD1 0x91
+ MX8MM_IOMUXC_ENET_RD0_ENET1_RGMII_RD0 0x91
+ MX8MM_IOMUXC_ENET_TXC_ENET1_RGMII_TXC 0x1f
+ MX8MM_IOMUXC_ENET_RXC_ENET1_RGMII_RXC 0x91
+ MX8MM_IOMUXC_ENET_RX_CTL_ENET1_RGMII_RX_CTL 0x91
+ MX8MM_IOMUXC_ENET_TX_CTL_ENET1_RGMII_TX_CTL 0x1f
+ MX8MM_IOMUXC_SAI1_TXD6_GPIO4_IO18 0x19 /* IRQ# */
+ MX8MM_IOMUXC_SAI1_TXD7_GPIO4_IO19 0x19 /* RST# */
+ >;
+ };
+
+ pinctrl_gsc: gscgrp {
+ fsl,pins = <
+ MX8MM_IOMUXC_SAI1_TXD4_GPIO4_IO16 0x159
+ >;
+ };
+
+ pinctrl_i2c1: i2c1grp {
+ fsl,pins = <
+ MX8MM_IOMUXC_I2C1_SCL_I2C1_SCL 0x400001c3
+ MX8MM_IOMUXC_I2C1_SDA_I2C1_SDA 0x400001c3
+ >;
+ };
+
+ pinctrl_i2c2: i2c2grp {
+ fsl,pins = <
+ MX8MM_IOMUXC_I2C2_SCL_I2C2_SCL 0x400001c3
+ MX8MM_IOMUXC_I2C2_SDA_I2C2_SDA 0x400001c3
+ >;
+ };
+
+ pinctrl_i2c3: i2c3grp {
+ fsl,pins = <
+ MX8MM_IOMUXC_I2C3_SCL_I2C3_SCL 0x400001c3
+ MX8MM_IOMUXC_I2C3_SDA_I2C3_SDA 0x400001c3
+ >;
+ };
+
+ pinctrl_i2c4: i2c4grp {
+ fsl,pins = <
+ MX8MM_IOMUXC_I2C4_SCL_I2C4_SCL 0x400001c3
+ MX8MM_IOMUXC_I2C4_SDA_I2C4_SDA 0x400001c3
+ >;
+ };
+
+ pinctrl_ksz: kszgrp {
+ fsl,pins = <
+ MX8MM_IOMUXC_SAI1_TXD6_GPIO4_IO18 0x41
+ MX8MM_IOMUXC_SAI1_TXD7_GPIO4_IO19 0x41 /* RST# */
+ >;
+ };
+
+ pinctrl_pmic: pmicgrp {
+ fsl,pins = <
+ MX8MM_IOMUXC_SAI5_RXC_GPIO3_IO20 0x41
+ >;
+ };
+
+ pinctrl_reg_isouart: regisouartgrp {
+ fsl,pins = <
+ MX8MM_IOMUXC_GPIO1_IO13_GPIO1_IO13 0x40000041
+ >;
+ };
+
+ pinctrl_reg_ioexp: regioexpgrp {
+ fsl,pins = <
+ MX8MM_IOMUXC_SAI2_RXFS_GPIO4_IO21 0x40000041
+ >;
+ };
+
+ pinctrl_reg_wl: regwlgrp {
+ fsl,pins = <
+ MX8MM_IOMUXC_SAI5_MCLK_GPIO3_IO25 0x40000041
+ >;
+ };
+
+ pinctrl_reg_usb2: regusb1grp {
+ fsl,pins = <
+ MX8MM_IOMUXC_SAI1_RXD0_GPIO4_IO2 0x41
+ MX8MM_IOMUXC_SAI1_TXD5_GPIO4_IO17 0x140
+ MX8MM_IOMUXC_GPIO1_IO15_USB2_OTG_OC 0x140
+ >;
+ };
+
+ pinctrl_spi1: spi1grp {
+ fsl,pins = <
+ MX8MM_IOMUXC_ECSPI1_SCLK_ECSPI1_SCLK 0x82
+ MX8MM_IOMUXC_ECSPI1_MOSI_ECSPI1_MOSI 0x82
+ MX8MM_IOMUXC_ECSPI1_MISO_ECSPI1_MISO 0x82
+ MX8MM_IOMUXC_ECSPI1_SS0_GPIO5_IO9 0x140
+ >;
+ };
+
+ pinctrl_uart1: uart1grp {
+ fsl,pins = <
+ MX8MM_IOMUXC_UART1_RXD_UART1_DCE_RX 0x140
+ MX8MM_IOMUXC_UART1_TXD_UART1_DCE_TX 0x140
+ MX8MM_IOMUXC_GPIO1_IO01_GPIO1_IO1 0x140
+ MX8MM_IOMUXC_GPIO1_IO10_GPIO1_IO10 0x140
+ MX8MM_IOMUXC_GPIO1_IO11_GPIO1_IO11 0x140
+ MX8MM_IOMUXC_GPIO1_IO12_GPIO1_IO12 0x140
+ MX8MM_IOMUXC_GPIO1_IO14_GPIO1_IO14 0x140
+ >;
+ };
+
+ pinctrl_uart1_gpio: uart1gpiogrp {
+ fsl,pins = <
+ MX8MM_IOMUXC_GPIO1_IO00_GPIO1_IO0 0x40000041 /* RS422# */
+ MX8MM_IOMUXC_GPIO1_IO03_GPIO1_IO3 0x40000041 /* RS485# */
+ MX8MM_IOMUXC_GPIO1_IO05_GPIO1_IO5 0x40000041 /* RS232# */
+ >;
+ };
+
+ pinctrl_uart2: uart2grp {
+ fsl,pins = <
+ MX8MM_IOMUXC_UART2_RXD_UART2_DCE_RX 0x140
+ MX8MM_IOMUXC_UART2_TXD_UART2_DCE_TX 0x140
+ >;
+ };
+
+ pinctrl_uart3: uart3grp {
+ fsl,pins = <
+ MX8MM_IOMUXC_UART3_RXD_UART3_DCE_RX 0x140
+ MX8MM_IOMUXC_UART3_TXD_UART3_DCE_TX 0x140
+ MX8MM_IOMUXC_SAI1_RXD7_GPIO4_IO9 0x140
+ MX8MM_IOMUXC_SAI1_TXFS_GPIO4_IO10 0x140
+ >;
+ };
+
+ pinctrl_uart3_gpio: uart3gpiogrp {
+ fsl,pins = <
+ MX8MM_IOMUXC_SAI1_RXD4_GPIO4_IO6 0x40000110 /* RS232# */
+ MX8MM_IOMUXC_SAI1_RXD5_GPIO4_IO7 0x40000110 /* RS422# */
+ MX8MM_IOMUXC_SAI1_RXD6_GPIO4_IO8 0x40000110 /* RS485# */
+ >;
+ };
+
+ pinctrl_uart4: uart4grp {
+ fsl,pins = <
+ MX8MM_IOMUXC_UART4_RXD_UART4_DCE_RX 0x140
+ MX8MM_IOMUXC_UART4_TXD_UART4_DCE_TX 0x140
+ MX8MM_IOMUXC_ECSPI2_MOSI_GPIO5_IO11 0x140
+ MX8MM_IOMUXC_ECSPI2_MISO_GPIO5_IO12 0x140
+ >;
+ };
+
+ pinctrl_uart4_gpio: uart4gpiogrp {
+ fsl,pins = <
+
+ MX8MM_IOMUXC_ECSPI2_SCLK_GPIO5_IO10 0x40000041 /* RS232# */
+ MX8MM_IOMUXC_ECSPI2_SS0_GPIO5_IO13 0x40000041 /* RS422# */
+ MX8MM_IOMUXC_SAI2_MCLK_GPIO4_IO27 0x40000041 /* RS485# */
+ >;
+ };
+
+ pinctrl_usdhc1: usdhc1grp {
+ fsl,pins = <
+ MX8MM_IOMUXC_SD1_CLK_USDHC1_CLK 0x190
+ MX8MM_IOMUXC_SD1_CMD_USDHC1_CMD 0x1d0
+ MX8MM_IOMUXC_SD1_DATA0_USDHC1_DATA0 0x1d0
+ MX8MM_IOMUXC_SD1_DATA1_USDHC1_DATA1 0x1d0
+ MX8MM_IOMUXC_SD1_DATA2_USDHC1_DATA2 0x1d0
+ MX8MM_IOMUXC_SD1_DATA3_USDHC1_DATA3 0x1d0
+ >;
+ };
+
+ pinctrl_usdhc2: usdhc2grp {
+ fsl,pins = <
+ MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK 0x190
+ MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d0
+ MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d0
+ MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d0
+ MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d0
+ MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d0
+ >;
+ };
+
+ pinctrl_usdhc2_100mhz: usdhc2-100mhzgrp {
+ fsl,pins = <
+ MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK 0x194
+ MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d4
+ MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d4
+ MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d4
+ MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d4
+ MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d4
+ >;
+ };
+
+ pinctrl_usdhc2_200mhz: usdhc2-200mhzgrp {
+ fsl,pins = <
+ MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK 0x196
+ MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d6
+ MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d6
+ MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d6
+ MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d6
+ MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d6
+ >;
+ };
+
+ pinctrl_usdhc2_gpio: usdhc2-gpiogrp {
+ fsl,pins = <
+ MX8MM_IOMUXC_SD2_CD_B_GPIO2_IO12 0x1c4
+ MX8MM_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0x1d0
+ >;
+ };
+
+ pinctrl_usdhc3: usdhc3grp {
+ fsl,pins = <
+ MX8MM_IOMUXC_NAND_WE_B_USDHC3_CLK 0x190
+ MX8MM_IOMUXC_NAND_WP_B_USDHC3_CMD 0x1d0
+ MX8MM_IOMUXC_NAND_DATA04_USDHC3_DATA0 0x1d0
+ MX8MM_IOMUXC_NAND_DATA05_USDHC3_DATA1 0x1d0
+ MX8MM_IOMUXC_NAND_DATA06_USDHC3_DATA2 0x1d0
+ MX8MM_IOMUXC_NAND_DATA07_USDHC3_DATA3 0x1d0
+ MX8MM_IOMUXC_NAND_RE_B_USDHC3_DATA4 0x1d0
+ MX8MM_IOMUXC_NAND_CE2_B_USDHC3_DATA5 0x1d0
+ MX8MM_IOMUXC_NAND_CE3_B_USDHC3_DATA6 0x1d0
+ MX8MM_IOMUXC_NAND_CLE_USDHC3_DATA7 0x1d0
+ MX8MM_IOMUXC_NAND_CE1_B_USDHC3_STROBE 0x190
+ >;
+ };
+
+ pinctrl_usdhc3_100mhz: usdhc3-100mhzgrp {
+ fsl,pins = <
+ MX8MM_IOMUXC_NAND_WE_B_USDHC3_CLK 0x194
+ MX8MM_IOMUXC_NAND_WP_B_USDHC3_CMD 0x1d4
+ MX8MM_IOMUXC_NAND_DATA04_USDHC3_DATA0 0x1d4
+ MX8MM_IOMUXC_NAND_DATA05_USDHC3_DATA1 0x1d4
+ MX8MM_IOMUXC_NAND_DATA06_USDHC3_DATA2 0x1d4
+ MX8MM_IOMUXC_NAND_DATA07_USDHC3_DATA3 0x1d4
+ MX8MM_IOMUXC_NAND_RE_B_USDHC3_DATA4 0x1d4
+ MX8MM_IOMUXC_NAND_CE2_B_USDHC3_DATA5 0x1d4
+ MX8MM_IOMUXC_NAND_CE3_B_USDHC3_DATA6 0x1d4
+ MX8MM_IOMUXC_NAND_CLE_USDHC3_DATA7 0x1d4
+ MX8MM_IOMUXC_NAND_CE1_B_USDHC3_STROBE 0x194
+ >;
+ };
+
+ pinctrl_usdhc3_200mhz: usdhc3-200mhzgrp {
+ fsl,pins = <
+ MX8MM_IOMUXC_NAND_WE_B_USDHC3_CLK 0x196
+ MX8MM_IOMUXC_NAND_WP_B_USDHC3_CMD 0x1d6
+ MX8MM_IOMUXC_NAND_DATA04_USDHC3_DATA0 0x1d6
+ MX8MM_IOMUXC_NAND_DATA05_USDHC3_DATA1 0x1d6
+ MX8MM_IOMUXC_NAND_DATA06_USDHC3_DATA2 0x1d6
+ MX8MM_IOMUXC_NAND_DATA07_USDHC3_DATA3 0x1d6
+ MX8MM_IOMUXC_NAND_RE_B_USDHC3_DATA4 0x1d6
+ MX8MM_IOMUXC_NAND_CE2_B_USDHC3_DATA5 0x1d6
+ MX8MM_IOMUXC_NAND_CE3_B_USDHC3_DATA6 0x1d6
+ MX8MM_IOMUXC_NAND_CLE_USDHC3_DATA7 0x1d6
+ MX8MM_IOMUXC_NAND_CE1_B_USDHC3_STROBE 0x196
+ >;
+ };
+
+ pinctrl_wdog: wdoggrp {
+ fsl,pins = <
+ MX8MM_IOMUXC_GPIO1_IO02_WDOG1_WDOG_B 0xc6
+ >;
+ };
+};
+
+&cpu_alert0 {
+ temperature = <95000>;
+ hysteresis = <2000>;
+ type = "passive";
+};
+
+&cpu_crit0 {
+ temperature = <105000>;
+ hysteresis = <2000>;
+ type = "critical";
+};
diff --git a/arch/arm/dts/imx8mp-evk-u-boot.dtsi b/arch/arm/dts/imx8mp-evk-u-boot.dtsi
index 4162f41..2abcf1f 100644
--- a/arch/arm/dts/imx8mp-evk-u-boot.dtsi
+++ b/arch/arm/dts/imx8mp-evk-u-boot.dtsi
@@ -3,11 +3,9 @@
* Copyright 2019 NXP
*/
-/ {
- binman: binman {
- multiple-images;
- };
+#include "imx8mp-u-boot.dtsi"
+/ {
wdt-reboot {
compatible = "wdt-reboot";
wdt = <&wdog1>;
@@ -21,43 +19,6 @@
};
};
-&{/soc@0} {
- u-boot,dm-pre-reloc;
- u-boot,dm-spl;
-};
-
-&clk {
- u-boot,dm-spl;
- u-boot,dm-pre-reloc;
-};
-
-&osc_32k {
- u-boot,dm-spl;
- u-boot,dm-pre-reloc;
-};
-
-&osc_24m {
- u-boot,dm-spl;
- u-boot,dm-pre-reloc;
-};
-
-&aips1 {
- u-boot,dm-spl;
- u-boot,dm-pre-reloc;
-};
-
-&aips2 {
- u-boot,dm-spl;
-};
-
-&aips3 {
- u-boot,dm-spl;
-};
-
-&iomuxc {
- u-boot,dm-spl;
-};
-
®_usdhc2_vmmc {
u-boot,off-on-delay-us = <20000>;
};
@@ -156,104 +117,4 @@
phy-reset-post-delay = <100>;
};
-&binman {
- u-boot-spl-ddr {
- filename = "u-boot-spl-ddr.bin";
- pad-byte = <0xff>;
- align-size = <4>;
- align = <4>;
- u-boot-spl {
- align-end = <4>;
- };
-
- blob_1: blob-ext@1 {
- filename = "lpddr4_pmu_train_1d_imem_202006.bin";
- size = <0x8000>;
- };
-
- blob_2: blob-ext@2 {
- filename = "lpddr4_pmu_train_1d_dmem_202006.bin";
- size = <0x4000>;
- };
-
- blob_3: blob-ext@3 {
- filename = "lpddr4_pmu_train_2d_imem_202006.bin";
- size = <0x8000>;
- };
-
- blob_4: blob-ext@4 {
- filename = "lpddr4_pmu_train_2d_dmem_202006.bin";
- size = <0x4000>;
- };
- };
-
-
- flash {
- mkimage {
- args = "-n spl/u-boot-spl.cfgout -T imx8mimage -e 0x920000";
-
- blob {
- filename = "u-boot-spl-ddr.bin";
- };
- };
- };
-
- itb {
- filename = "u-boot.itb";
-
- fit {
- description = "Configuration to load ATF before U-Boot";
- #address-cells = <1>;
- fit,external-offset = <CONFIG_FIT_EXTERNAL_OFFSET>;
-
- images {
- uboot {
- description = "U-Boot (64-bit)";
- type = "standalone";
- arch = "arm64";
- compression = "none";
- load = <CONFIG_SYS_TEXT_BASE>;
-
- uboot_blob: blob-ext {
- filename = "u-boot-nodtb.bin";
- };
- };
-
- atf {
- description = "ARM Trusted Firmware";
- type = "firmware";
- arch = "arm64";
- compression = "none";
- load = <0x970000>;
- entry = <0x970000>;
-
- atf_blob: blob-ext {
- filename = "bl31.bin";
- };
- };
-
- fdt {
- description = "NAME";
- type = "flat_dt";
- compression = "none";
-
- uboot_fdt_blob: blob-ext {
- filename = "u-boot.dtb";
- };
- };
- };
-
- configurations {
- default = "conf";
-
- conf {
- description = "NAME";
- firmware = "uboot";
- loadables = "atf";
- fdt = "fdt";
- };
- };
- };
- };
-};
diff --git a/arch/arm/dts/imx8mp-phyboard-pollux-rdk-u-boot.dtsi b/arch/arm/dts/imx8mp-phyboard-pollux-rdk-u-boot.dtsi
index 20e7f63..dbc48df 100644
--- a/arch/arm/dts/imx8mp-phyboard-pollux-rdk-u-boot.dtsi
+++ b/arch/arm/dts/imx8mp-phyboard-pollux-rdk-u-boot.dtsi
@@ -4,6 +4,8 @@
* Author: Teresa Remmet <t.remmet@phytec.de>
*/
+#include "imx8mp-u-boot.dtsi"
+
/ {
wdt-reboot {
compatible = "wdt-reboot";
@@ -12,48 +14,11 @@
};
};
-&{/soc@0} {
- u-boot,dm-pre-reloc;
- u-boot,dm-spl;
-};
-
-&clk {
- u-boot,dm-spl;
- u-boot,dm-pre-reloc;
-};
-
-&osc_32k {
- u-boot,dm-spl;
- u-boot,dm-pre-reloc;
-};
-
-&osc_24m {
- u-boot,dm-spl;
- u-boot,dm-pre-reloc;
-};
-
-&aips1 {
- u-boot,dm-spl;
- u-boot,dm-pre-reloc;
-};
-
-&aips2 {
- u-boot,dm-spl;
-};
-
-&aips3 {
- u-boot,dm-spl;
-};
-
-&iomuxc {
- u-boot,dm-spl;
-};
-
®_usdhc2_vmmc {
u-boot,dm-spl;
};
-&pinctrl_uart2 {
+&pinctrl_uart1 {
u-boot,dm-spl;
};
@@ -69,6 +34,10 @@
u-boot,dm-spl;
};
+&pinctrl_wdog {
+ u-boot,dm-spl;
+};
+
&gpio1 {
u-boot,dm-spl;
};
@@ -89,7 +58,7 @@
u-boot,dm-spl;
};
-&uart2 {
+&uart1 {
u-boot,dm-spl;
};
diff --git a/arch/arm/dts/imx8mp-phyboard-pollux-rdk.dts b/arch/arm/dts/imx8mp-phyboard-pollux-rdk.dts
index 0e1a6d9..984a6b9 100644
--- a/arch/arm/dts/imx8mp-phyboard-pollux-rdk.dts
+++ b/arch/arm/dts/imx8mp-phyboard-pollux-rdk.dts
@@ -16,7 +16,7 @@
"phytec,imx8mp-phycore-som", "fsl,imx8mp";
chosen {
- stdout-path = &uart2;
+ stdout-path = &uart1;
};
reg_usdhc2_vmmc: regulator-usdhc2 {
@@ -33,9 +33,33 @@
};
};
+&eqos {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_eqos>;
+ phy-mode = "rgmii-id";
+ phy-handle = <ðphy0>;
+ status = "okay";
+
+ mdio {
+ compatible = "snps,dwmac-mdio";
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ ethphy0: ethernet-phy@1 {
+ compatible = "ethernet-phy-ieee802.3-c22";
+ reg = <0x1>;
+ ti,rx-internal-delay = <DP83867_RGMIIDCTL_1_50_NS>;
+ ti,tx-internal-delay = <DP83867_RGMIIDCTL_1_50_NS>;
+ ti,fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>;
+ ti,clk-output-sel = <DP83867_CLK_O_SEL_OFF>;
+ enet-phy-lane-no-swap;
+ };
+ };
+};
+
&i2c2 {
clock-frequency = <400000>;
- pinctrl-names = "default";
+ pinctrl-names = "default", "gpio";
pinctrl-0 = <&pinctrl_i2c2>;
pinctrl-1 = <&pinctrl_i2c2_gpio>;
sda-gpios = <&gpio5 17 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
@@ -71,9 +95,9 @@
};
/* debug console */
-&uart2 {
+&uart1 {
pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_uart2>;
+ pinctrl-0 = <&pinctrl_uart1>;
status = "okay";
};
@@ -90,6 +114,26 @@
};
&iomuxc {
+ pinctrl_eqos: eqosgrp {
+ fsl,pins = <
+ MX8MP_IOMUXC_ENET_MDC__ENET_QOS_MDC 0x3
+ MX8MP_IOMUXC_ENET_MDIO__ENET_QOS_MDIO 0x3
+ MX8MP_IOMUXC_ENET_RD0__ENET_QOS_RGMII_RD0 0x91
+ MX8MP_IOMUXC_ENET_RD1__ENET_QOS_RGMII_RD1 0x91
+ MX8MP_IOMUXC_ENET_RD2__ENET_QOS_RGMII_RD2 0x91
+ MX8MP_IOMUXC_ENET_RD3__ENET_QOS_RGMII_RD3 0x91
+ MX8MP_IOMUXC_ENET_RXC__CCM_ENET_QOS_CLOCK_GENERATE_RX_CLK 0x91
+ MX8MP_IOMUXC_ENET_RX_CTL__ENET_QOS_RGMII_RX_CTL 0x91
+ MX8MP_IOMUXC_ENET_TD0__ENET_QOS_RGMII_TD0 0x1f
+ MX8MP_IOMUXC_ENET_TD1__ENET_QOS_RGMII_TD1 0x1f
+ MX8MP_IOMUXC_ENET_TD2__ENET_QOS_RGMII_TD2 0x1f
+ MX8MP_IOMUXC_ENET_TD3__ENET_QOS_RGMII_TD3 0x1f
+ MX8MP_IOMUXC_ENET_TX_CTL__ENET_QOS_RGMII_TX_CTL 0x1f
+ MX8MP_IOMUXC_ENET_TXC__CCM_ENET_QOS_CLOCK_GENERATE_TX_CLK 0x1f
+ MX8MP_IOMUXC_SAI1_MCLK__GPIO4_IO20 0x10
+ >;
+ };
+
pinctrl_i2c2: i2c2grp {
fsl,pins = <
MX8MP_IOMUXC_I2C2_SCL__I2C2_SCL 0x400001c3
@@ -110,10 +154,10 @@
>;
};
- pinctrl_uart2: uart2grp {
+ pinctrl_uart1: uart1grp {
fsl,pins = <
- MX8MP_IOMUXC_UART2_RXD__UART2_DCE_RX 0x49
- MX8MP_IOMUXC_UART2_TXD__UART2_DCE_TX 0x49
+ MX8MP_IOMUXC_UART1_RXD__UART1_DCE_RX 0x49
+ MX8MP_IOMUXC_UART1_TXD__UART1_DCE_TX 0x49
>;
};
diff --git a/arch/arm/dts/imx8mp-phycore-som.dtsi b/arch/arm/dts/imx8mp-phycore-som.dtsi
index 44a8c23..f3965ec 100644
--- a/arch/arm/dts/imx8mp-phycore-som.dtsi
+++ b/arch/arm/dts/imx8mp-phycore-som.dtsi
@@ -67,7 +67,7 @@
&i2c1 {
clock-frequency = <400000>;
- pinctrl-names = "default";
+ pinctrl-names = "default", "gpio";
pinctrl-0 = <&pinctrl_i2c1>;
pinctrl-1 = <&pinctrl_i2c1_gpio>;
sda-gpios = <&gpio5 15 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
diff --git a/arch/arm/dts/imx8mp-u-boot.dtsi b/arch/arm/dts/imx8mp-u-boot.dtsi
new file mode 100644
index 0000000..d61346d
--- /dev/null
+++ b/arch/arm/dts/imx8mp-u-boot.dtsi
@@ -0,0 +1,149 @@
+// SPDX-License-Identifier: GPL-2.0-or-later
+/*
+ * Copyright (C) 2021 PHYTEC Messtechnik GmbH
+ * Author: Teresa Remmet <t.remmet@phytec.de>
+ */
+
+/ {
+ binman: binman {
+ multiple-images;
+ };
+};
+
+&{/soc@0} {
+ u-boot,dm-pre-reloc;
+ u-boot,dm-spl;
+};
+
+&clk {
+ u-boot,dm-spl;
+ u-boot,dm-pre-reloc;
+};
+
+&osc_32k {
+ u-boot,dm-spl;
+ u-boot,dm-pre-reloc;
+};
+
+&osc_24m {
+ u-boot,dm-spl;
+ u-boot,dm-pre-reloc;
+};
+
+&aips1 {
+ u-boot,dm-spl;
+ u-boot,dm-pre-reloc;
+};
+
+&aips2 {
+ u-boot,dm-spl;
+};
+
+&aips3 {
+ u-boot,dm-spl;
+};
+
+&iomuxc {
+ u-boot,dm-spl;
+};
+
+&binman {
+ u-boot-spl-ddr {
+ filename = "u-boot-spl-ddr.bin";
+ pad-byte = <0xff>;
+ align-size = <4>;
+ align = <4>;
+
+ u-boot-spl {
+ align-end = <4>;
+ };
+
+ blob_1: blob-ext@1 {
+ filename = "lpddr4_pmu_train_1d_imem_202006.bin";
+ size = <0x8000>;
+ };
+
+ blob_2: blob-ext@2 {
+ filename = "lpddr4_pmu_train_1d_dmem_202006.bin";
+ size = <0x4000>;
+ };
+
+ blob_3: blob-ext@3 {
+ filename = "lpddr4_pmu_train_2d_imem_202006.bin";
+ size = <0x8000>;
+ };
+
+ blob_4: blob-ext@4 {
+ filename = "lpddr4_pmu_train_2d_dmem_202006.bin";
+ size = <0x4000>;
+ };
+ };
+
+ flash {
+ mkimage {
+ args = "-n spl/u-boot-spl.cfgout -T imx8mimage -e 0x920000";
+
+ blob {
+ filename = "u-boot-spl-ddr.bin";
+ };
+ };
+ };
+
+ itb {
+ filename = "u-boot.itb";
+
+ fit {
+ description = "Configuration to load ATF before U-Boot";
+ #address-cells = <1>;
+ fit,external-offset = <CONFIG_FIT_EXTERNAL_OFFSET>;
+
+ images {
+ uboot {
+ description = "U-Boot (64-bit)";
+ type = "standalone";
+ arch = "arm64";
+ compression = "none";
+ load = <CONFIG_SYS_TEXT_BASE>;
+
+ uboot_blob: blob-ext {
+ filename = "u-boot-nodtb.bin";
+ };
+ };
+
+ atf {
+ description = "ARM Trusted Firmware";
+ type = "firmware";
+ arch = "arm64";
+ compression = "none";
+ load = <0x970000>;
+ entry = <0x970000>;
+
+ atf_blob: blob-ext {
+ filename = "bl31.bin";
+ };
+ };
+
+ fdt {
+ description = "NAME";
+ type = "flat_dt";
+ compression = "none";
+
+ uboot_fdt_blob: blob-ext {
+ filename = "u-boot.dtb";
+ };
+ };
+ };
+
+ configurations {
+ default = "conf";
+
+ conf {
+ description = "NAME";
+ firmware = "uboot";
+ loadables = "atf";
+ fdt = "fdt";
+ };
+ };
+ };
+ };
+};
diff --git a/arch/arm/dts/imx8mp.dtsi b/arch/arm/dts/imx8mp.dtsi
index ecccfbb..c2d51a4 100644
--- a/arch/arm/dts/imx8mp.dtsi
+++ b/arch/arm/dts/imx8mp.dtsi
@@ -18,6 +18,7 @@
aliases {
ethernet0 = &fec;
+ ethernet1 = &eqos;
gpio0 = &gpio1;
gpio1 = &gpio2;
gpio2 = &gpio3;
@@ -218,10 +219,12 @@
};
soc@0 {
- compatible = "simple-bus";
+ compatible = "fsl,imx8mp-soc", "simple-bus";
#address-cells = <1>;
#size-cells = <1>;
ranges = <0x0 0x0 0x0 0x3e000000>;
+ nvmem-cells = <&imx8mp_uid>;
+ nvmem-cell-names = "soc_unique_id";
aips1: bus@30000000 {
compatible = "fsl,aips-bus", "simple-bus";
@@ -266,7 +269,7 @@
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
- gpio-ranges = <&iomuxc 0 56 26>, <&iomuxc 0 144 4>;
+ gpio-ranges = <&iomuxc 0 56 26>, <&iomuxc 26 144 4>;
};
gpio4: gpio@30230000 {
@@ -310,6 +313,22 @@
status = "disabled";
};
+ wdog2: watchdog@30290000 {
+ compatible = "fsl,imx8mp-wdt", "fsl,imx21-wdt";
+ reg = <0x30290000 0x10000>;
+ interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&clk IMX8MP_CLK_WDOG2_ROOT>;
+ status = "disabled";
+ };
+
+ wdog3: watchdog@302a0000 {
+ compatible = "fsl,imx8mp-wdt", "fsl,imx21-wdt";
+ reg = <0x302a0000 0x10000>;
+ interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&clk IMX8MP_CLK_WDOG3_ROOT>;
+ status = "disabled";
+ };
+
iomuxc: pinctrl@30330000 {
compatible = "fsl,imx8mp-iomuxc";
reg = <0x30330000 0x10000>;
@@ -328,9 +347,17 @@
#address-cells = <1>;
#size-cells = <1>;
+ imx8mp_uid: unique-id@420 {
+ reg = <0x8 0x8>;
+ };
+
cpu_speed_grade: speed-grade@10 {
reg = <0x10 4>;
};
+
+ eth_mac1: mac-address@90 {
+ reg = <0x90 6>;
+ };
};
anatop: anatop@30360000 {
@@ -762,13 +789,40 @@
assigned-clocks = <&clk IMX8MP_CLK_ENET_AXI>,
<&clk IMX8MP_CLK_ENET_TIMER>,
<&clk IMX8MP_CLK_ENET_REF>,
- <&clk IMX8MP_CLK_ENET_TIMER>;
+ <&clk IMX8MP_CLK_ENET_PHY_REF>;
assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_266M>,
<&clk IMX8MP_SYS_PLL2_100M>,
- <&clk IMX8MP_SYS_PLL2_125M>;
- assigned-clock-rates = <0>, <0>, <125000000>, <100000000>;
+ <&clk IMX8MP_SYS_PLL2_125M>,
+ <&clk IMX8MP_SYS_PLL2_50M>;
+ assigned-clock-rates = <0>, <100000000>, <125000000>, <0>;
fsl,num-tx-queues = <3>;
fsl,num-rx-queues = <3>;
+ nvmem-cells = <ð_mac1>;
+ nvmem-cell-names = "mac-address";
+ fsl,stop-mode = <&gpr 0x10 3>;
+ nvmem_macaddr_swap;
+ status = "disabled";
+ };
+
+ eqos: ethernet@30bf0000 {
+ compatible = "nxp,imx8mp-dwmac-eqos", "snps,dwmac-5.10a";
+ reg = <0x30bf0000 0x10000>;
+ interrupts = <GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "eth_wake_irq", "macirq";
+ clocks = <&clk IMX8MP_CLK_ENET_QOS_ROOT>,
+ <&clk IMX8MP_CLK_QOS_ENET_ROOT>,
+ <&clk IMX8MP_CLK_ENET_QOS_TIMER>,
+ <&clk IMX8MP_CLK_ENET_QOS>;
+ clock-names = "stmmaceth", "pclk", "ptp_ref", "tx";
+ assigned-clocks = <&clk IMX8MP_CLK_ENET_AXI>,
+ <&clk IMX8MP_CLK_ENET_QOS_TIMER>,
+ <&clk IMX8MP_CLK_ENET_QOS>;
+ assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_266M>,
+ <&clk IMX8MP_SYS_PLL2_100M>,
+ <&clk IMX8MP_SYS_PLL2_125M>;
+ assigned-clock-rates = <0>, <100000000>, <125000000>;
+ intf_mode = <&gpr 0x4>;
status = "disabled";
};
};
@@ -788,5 +842,87 @@
reg = <0x3d800000 0x400000>;
interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
};
+
+ usb3_phy0: usb-phy@381f0040 {
+ compatible = "fsl,imx8mp-usb-phy";
+ reg = <0x381f0040 0x40>;
+ clocks = <&clk IMX8MP_CLK_USB_PHY_ROOT>;
+ clock-names = "phy";
+ assigned-clocks = <&clk IMX8MP_CLK_USB_PHY_REF>;
+ assigned-clock-parents = <&clk IMX8MP_CLK_24M>;
+ #phy-cells = <0>;
+ status = "disabled";
+ };
+
+ usb3_0: usb@32f10100 {
+ compatible = "fsl,imx8mp-dwc3";
+ reg = <0x32f10100 0x8>;
+ clocks = <&clk IMX8MP_CLK_HSIO_ROOT>,
+ <&clk IMX8MP_CLK_USB_ROOT>;
+ clock-names = "hsio", "suspend";
+ interrupts = <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ dma-ranges = <0x40000000 0x40000000 0xc0000000>;
+ ranges;
+ status = "disabled";
+
+ usb_dwc3_0: usb@38100000 {
+ compatible = "snps,dwc3";
+ reg = <0x38100000 0x10000>;
+ clocks = <&clk IMX8MP_CLK_HSIO_AXI>,
+ <&clk IMX8MP_CLK_USB_CORE_REF>,
+ <&clk IMX8MP_CLK_USB_ROOT>;
+ clock-names = "bus_early", "ref", "suspend";
+ assigned-clocks = <&clk IMX8MP_CLK_HSIO_AXI>;
+ assigned-clock-parents = <&clk IMX8MP_SYS_PLL2_500M>;
+ assigned-clock-rates = <500000000>;
+ interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>;
+ phys = <&usb3_phy0>, <&usb3_phy0>;
+ phy-names = "usb2-phy", "usb3-phy";
+ snps,dis-u2-freeclk-exists-quirk;
+ };
+
+ };
+
+ usb3_phy1: usb-phy@382f0040 {
+ compatible = "fsl,imx8mp-usb-phy";
+ reg = <0x382f0040 0x40>;
+ clocks = <&clk IMX8MP_CLK_USB_PHY_ROOT>;
+ clock-names = "phy";
+ assigned-clocks = <&clk IMX8MP_CLK_USB_PHY_REF>;
+ assigned-clock-parents = <&clk IMX8MP_CLK_24M>;
+ #phy-cells = <0>;
+ };
+
+ usb3_1: usb@32f10108 {
+ compatible = "fsl,imx8mp-dwc3";
+ reg = <0x32f10108 0x8>;
+ clocks = <&clk IMX8MP_CLK_HSIO_ROOT>,
+ <&clk IMX8MP_CLK_USB_ROOT>;
+ clock-names = "hsio", "suspend";
+ interrupts = <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ dma-ranges = <0x40000000 0x40000000 0xc0000000>;
+ ranges;
+ status = "disabled";
+
+ usb_dwc3_1: usb@38200000 {
+ compatible = "snps,dwc3";
+ reg = <0x38200000 0x10000>;
+ clocks = <&clk IMX8MP_CLK_HSIO_AXI>,
+ <&clk IMX8MP_CLK_USB_CORE_REF>,
+ <&clk IMX8MP_CLK_USB_ROOT>;
+ clock-names = "bus_early", "ref", "suspend";
+ assigned-clocks = <&clk IMX8MP_CLK_HSIO_AXI>;
+ assigned-clock-parents = <&clk IMX8MP_SYS_PLL2_500M>;
+ assigned-clock-rates = <500000000>;
+ interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>;
+ phys = <&usb3_phy1>, <&usb3_phy1>;
+ phy-names = "usb2-phy", "usb3-phy";
+ snps,dis-u2-freeclk-exists-quirk;
+ };
+ };
};
};
diff --git a/arch/arm/dts/imx8mq.dtsi b/arch/arm/dts/imx8mq.dtsi
index a841a02..a44f729 100644
--- a/arch/arm/dts/imx8mq.dtsi
+++ b/arch/arm/dts/imx8mq.dtsi
@@ -39,6 +39,8 @@
spi0 = &ecspi1;
spi1 = &ecspi2;
spi2 = &ecspi3;
+ usb0 = &usb_dwc3_0;
+ usb1 = &usb_dwc3_1;
};
ckil: clock-ckil {
diff --git a/arch/arm/dts/stm32mp15-pinctrl.dtsi b/arch/arm/dts/stm32mp15-pinctrl.dtsi
index 20a59e8..060baa8 100644
--- a/arch/arm/dts/stm32mp15-pinctrl.dtsi
+++ b/arch/arm/dts/stm32mp15-pinctrl.dtsi
@@ -1273,6 +1273,18 @@
};
};
+ sdmmc1_b4_init_pins_a: sdmmc1-b4-init-0 {
+ pins1 {
+ pinmux = <STM32_PINMUX('C', 8, AF12)>, /* SDMMC1_D0 */
+ <STM32_PINMUX('C', 9, AF12)>, /* SDMMC1_D1 */
+ <STM32_PINMUX('C', 10, AF12)>, /* SDMMC1_D2 */
+ <STM32_PINMUX('C', 11, AF12)>; /* SDMMC1_D3 */
+ slew-rate = <1>;
+ drive-push-pull;
+ bias-disable;
+ };
+ };
+
sdmmc1_b4_sleep_pins_a: sdmmc1-b4-sleep-0 {
pins {
pinmux = <STM32_PINMUX('C', 8, ANALOG)>, /* SDMMC1_D0 */
@@ -1299,6 +1311,17 @@
};
};
+ sdmmc1_dir_init_pins_a: sdmmc1-dir-init-0 {
+ pins1 {
+ pinmux = <STM32_PINMUX('F', 2, AF11)>, /* SDMMC1_D0DIR */
+ <STM32_PINMUX('C', 7, AF8)>, /* SDMMC1_D123DIR */
+ <STM32_PINMUX('B', 9, AF11)>; /* SDMMC1_CDIR */
+ slew-rate = <1>;
+ drive-push-pull;
+ bias-pull-up;
+ };
+ };
+
sdmmc1_dir_sleep_pins_a: sdmmc1-dir-sleep-0 {
pins {
pinmux = <STM32_PINMUX('F', 2, ANALOG)>, /* SDMMC1_D0DIR */
@@ -1868,10 +1891,15 @@
usart2_idle_pins_c: usart2-idle-2 {
pins1 {
pinmux = <STM32_PINMUX('D', 5, ANALOG)>, /* USART2_TX */
- <STM32_PINMUX('D', 4, ANALOG)>, /* USART2_RTS */
<STM32_PINMUX('D', 3, ANALOG)>; /* USART2_CTS_NSS */
};
pins2 {
+ pinmux = <STM32_PINMUX('D', 4, AF7)>; /* USART2_RTS */
+ bias-disable;
+ drive-push-pull;
+ slew-rate = <3>;
+ };
+ pins3 {
pinmux = <STM32_PINMUX('D', 6, AF7)>; /* USART2_RX */
bias-disable;
};
@@ -1917,10 +1945,15 @@
usart3_idle_pins_b: usart3-idle-1 {
pins1 {
pinmux = <STM32_PINMUX('B', 10, ANALOG)>, /* USART3_TX */
- <STM32_PINMUX('G', 8, ANALOG)>, /* USART3_RTS */
<STM32_PINMUX('I', 10, ANALOG)>; /* USART3_CTS_NSS */
};
pins2 {
+ pinmux = <STM32_PINMUX('G', 8, AF8)>; /* USART3_RTS */
+ bias-disable;
+ drive-push-pull;
+ slew-rate = <0>;
+ };
+ pins3 {
pinmux = <STM32_PINMUX('B', 12, AF8)>; /* USART3_RX */
bias-disable;
};
@@ -1953,10 +1986,15 @@
usart3_idle_pins_c: usart3-idle-2 {
pins1 {
pinmux = <STM32_PINMUX('B', 10, ANALOG)>, /* USART3_TX */
- <STM32_PINMUX('G', 8, ANALOG)>, /* USART3_RTS */
<STM32_PINMUX('B', 13, ANALOG)>; /* USART3_CTS_NSS */
};
pins2 {
+ pinmux = <STM32_PINMUX('G', 8, AF8)>; /* USART3_RTS */
+ bias-disable;
+ drive-push-pull;
+ slew-rate = <0>;
+ };
+ pins3 {
pinmux = <STM32_PINMUX('B', 12, AF8)>; /* USART3_RX */
bias-disable;
};
@@ -2018,6 +2056,23 @@
};
};
+ i2c6_pins_a: i2c6-0 {
+ pins {
+ pinmux = <STM32_PINMUX('Z', 6, AF2)>, /* I2C6_SCL */
+ <STM32_PINMUX('Z', 7, AF2)>; /* I2C6_SDA */
+ bias-disable;
+ drive-open-drain;
+ slew-rate = <0>;
+ };
+ };
+
+ i2c6_sleep_pins_a: i2c6-sleep-0 {
+ pins {
+ pinmux = <STM32_PINMUX('Z', 6, ANALOG)>, /* I2C6_SCL */
+ <STM32_PINMUX('Z', 7, ANALOG)>; /* I2C6_SDA */
+ };
+ };
+
spi1_pins_a: spi1-0 {
pins1 {
pinmux = <STM32_PINMUX('Z', 0, AF5)>, /* SPI1_SCK */
diff --git a/arch/arm/dts/stm32mp151.dtsi b/arch/arm/dts/stm32mp151.dtsi
index b564fc6..177927d 100644
--- a/arch/arm/dts/stm32mp151.dtsi
+++ b/arch/arm/dts/stm32mp151.dtsi
@@ -470,32 +470,36 @@
usart2: serial@4000e000 {
compatible = "st,stm32h7-uart";
reg = <0x4000e000 0x400>;
- interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
+ interrupts-extended = <&exti 27 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&rcc USART2_K>;
+ wakeup-source;
status = "disabled";
};
usart3: serial@4000f000 {
compatible = "st,stm32h7-uart";
reg = <0x4000f000 0x400>;
- interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>;
+ interrupts-extended = <&exti 28 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&rcc USART3_K>;
+ wakeup-source;
status = "disabled";
};
uart4: serial@40010000 {
compatible = "st,stm32h7-uart";
reg = <0x40010000 0x400>;
- interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>;
+ interrupts-extended = <&exti 30 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&rcc UART4_K>;
+ wakeup-source;
status = "disabled";
};
uart5: serial@40011000 {
compatible = "st,stm32h7-uart";
reg = <0x40011000 0x400>;
- interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>;
+ interrupts-extended = <&exti 31 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&rcc UART5_K>;
+ wakeup-source;
status = "disabled";
};
@@ -511,6 +515,7 @@
#size-cells = <0>;
st,syscfg-fmp = <&syscfg 0x4 0x1>;
wakeup-source;
+ i2c-analog-filter;
status = "disabled";
};
@@ -526,6 +531,7 @@
#size-cells = <0>;
st,syscfg-fmp = <&syscfg 0x4 0x2>;
wakeup-source;
+ i2c-analog-filter;
status = "disabled";
};
@@ -541,6 +547,7 @@
#size-cells = <0>;
st,syscfg-fmp = <&syscfg 0x4 0x4>;
wakeup-source;
+ i2c-analog-filter;
status = "disabled";
};
@@ -556,6 +563,7 @@
#size-cells = <0>;
st,syscfg-fmp = <&syscfg 0x4 0x10>;
wakeup-source;
+ i2c-analog-filter;
status = "disabled";
};
@@ -595,16 +603,18 @@
uart7: serial@40018000 {
compatible = "st,stm32h7-uart";
reg = <0x40018000 0x400>;
- interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
+ interrupts-extended = <&exti 32 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&rcc UART7_K>;
+ wakeup-source;
status = "disabled";
};
uart8: serial@40019000 {
compatible = "st,stm32h7-uart";
reg = <0x40019000 0x400>;
- interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
+ interrupts-extended = <&exti 33 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&rcc UART8_K>;
+ wakeup-source;
status = "disabled";
};
@@ -683,8 +693,9 @@
usart6: serial@44003000 {
compatible = "st,stm32h7-uart";
reg = <0x44003000 0x400>;
- interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
+ interrupts-extended = <&exti 29 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&rcc USART6_K>;
+ wakeup-source;
status = "disabled";
};
@@ -1065,7 +1076,7 @@
};
};
- sdmmc3: sdmmc@48004000 {
+ sdmmc3: mmc@48004000 {
compatible = "arm,pl18x", "arm,primecell";
arm,primecell-periphid = <0x00253180>;
reg = <0x48004000 0x400>;
@@ -1398,7 +1409,7 @@
status = "disabled";
};
- sdmmc1: sdmmc@58005000 {
+ sdmmc1: mmc@58005000 {
compatible = "arm,pl18x", "arm,primecell";
arm,primecell-periphid = <0x00253180>;
reg = <0x58005000 0x1000>;
@@ -1413,7 +1424,7 @@
status = "disabled";
};
- sdmmc2: sdmmc@58007000 {
+ sdmmc2: mmc@58007000 {
compatible = "arm,pl18x", "arm,primecell";
arm,primecell-periphid = <0x00253180>;
reg = <0x58007000 0x1000>;
@@ -1451,11 +1462,13 @@
"mac-clk-tx",
"mac-clk-rx",
"eth-ck",
+ "ptp_ref",
"ethstp";
clocks = <&rcc ETHMAC>,
<&rcc ETHTX>,
<&rcc ETHRX>,
<&rcc ETHCK_K>,
+ <&rcc ETHPTP_K>,
<&rcc ETHSTP>;
st,syscon = <&syscfg 0x4>;
snps,mixed-burst;
@@ -1512,6 +1525,7 @@
usbphyc: usbphyc@5a006000 {
#address-cells = <1>;
#size-cells = <0>;
+ #clock-cells = <0>;
compatible = "st,stm32mp1-usbphyc";
reg = <0x5a006000 0x1000>;
clocks = <&rcc USBPHY_K>;
@@ -1534,8 +1548,9 @@
usart1: serial@5c000000 {
compatible = "st,stm32h7-uart";
reg = <0x5c000000 0x400>;
- interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
+ interrupts-extended = <&exti 26 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&rcc USART1_K>;
+ wakeup-source;
status = "disabled";
};
@@ -1565,6 +1580,7 @@
#size-cells = <0>;
st,syscfg-fmp = <&syscfg 0x4 0x8>;
wakeup-source;
+ i2c-analog-filter;
status = "disabled";
};
@@ -1605,6 +1621,7 @@
#size-cells = <0>;
st,syscfg-fmp = <&syscfg 0x4 0x20>;
wakeup-source;
+ i2c-analog-filter;
status = "disabled";
};
diff --git a/arch/arm/dts/stm32mp157a-dk1-u-boot.dtsi b/arch/arm/dts/stm32mp157a-dk1-u-boot.dtsi
index 6787619..7dcc96c 100644
--- a/arch/arm/dts/stm32mp157a-dk1-u-boot.dtsi
+++ b/arch/arm/dts/stm32mp157a-dk1-u-boot.dtsi
@@ -10,7 +10,6 @@
/ {
aliases {
i2c3 = &i2c4;
- mmc0 = &sdmmc1;
usb0 = &usbotg_hs;
};
config {
diff --git a/arch/arm/dts/stm32mp157c-ed1-u-boot.dtsi b/arch/arm/dts/stm32mp157c-ed1-u-boot.dtsi
index f3002e9..46a4337 100644
--- a/arch/arm/dts/stm32mp157c-ed1-u-boot.dtsi
+++ b/arch/arm/dts/stm32mp157c-ed1-u-boot.dtsi
@@ -10,8 +10,6 @@
/ {
aliases {
i2c3 = &i2c4;
- mmc0 = &sdmmc1;
- mmc1 = &sdmmc2;
};
config {
diff --git a/arch/arm/include/asm/arch-imx8m/clock.h b/arch/arm/include/asm/arch-imx8m/clock.h
index 77d9428..c705dfd 100644
--- a/arch/arm/include/asm/arch-imx8m/clock.h
+++ b/arch/arm/include/asm/arch-imx8m/clock.h
@@ -257,6 +257,7 @@
int clock_init(void);
void init_clk_usdhc(u32 index);
void init_uart_clk(u32 index);
+void init_usb_clk(void);
void init_wdog_clk(void);
unsigned int mxc_get_clock(enum mxc_clock clk);
int clock_enable(enum clk_ccgr_index index, bool enable);
diff --git a/arch/arm/include/asm/arch-mx6/sys_proto.h b/arch/arm/include/asm/arch-mx6/sys_proto.h
index 1e5fa1a..c49759a 100644
--- a/arch/arm/include/asm/arch-mx6/sys_proto.h
+++ b/arch/arm/include/asm/arch-mx6/sys_proto.h
@@ -7,6 +7,7 @@
#ifndef __SYS_PROTO_IMX6_
#define __SYS_PROTO_IMX6_
+#include <asm/gpio.h>
#include <asm/mach-imx/sys_proto.h>
#include <asm/arch/iomux.h>
@@ -18,7 +19,7 @@
USBPHY_PWD_RXPWDRX))
int imx6_pcie_toggle_power(void);
-int imx6_pcie_toggle_reset(void);
+int imx6_pcie_toggle_reset(struct gpio_desc *gpio, bool active_high);
enum ldo_reg {
LDO_ARM,
diff --git a/arch/arm/mach-imx/imx8m/Kconfig b/arch/arm/mach-imx/imx8m/Kconfig
index 0669363..ccaf106 100644
--- a/arch/arm/mach-imx/imx8m/Kconfig
+++ b/arch/arm/mach-imx/imx8m/Kconfig
@@ -127,6 +127,7 @@
config TARGET_PHYCORE_IMX8MP
bool "PHYTEC PHYCORE i.MX8MP"
+ select BINMAN
select IMX8MP
select SUPPORT_SPL
select IMX8M_LPDDR4
diff --git a/arch/arm/mach-imx/imx8m/clock_imx8mq.c b/arch/arm/mach-imx/imx8m/clock_imx8mq.c
index 8fecc60..60e2218 100644
--- a/arch/arm/mach-imx/imx8m/clock_imx8mq.c
+++ b/arch/arm/mach-imx/imx8m/clock_imx8mq.c
@@ -400,6 +400,28 @@
clock_enable(CCGR_WDOG3, 1);
}
+void init_usb_clk(void)
+{
+ if (!is_usb_boot()) {
+ clock_enable(CCGR_USB_CTRL1, 0);
+ clock_enable(CCGR_USB_CTRL2, 0);
+ clock_enable(CCGR_USB_PHY1, 0);
+ clock_enable(CCGR_USB_PHY2, 0);
+ /* 500MHz */
+ clock_set_target_val(USB_BUS_CLK_ROOT, CLK_ROOT_ON |
+ CLK_ROOT_SOURCE_SEL(1));
+ /* 100MHz */
+ clock_set_target_val(USB_CORE_REF_CLK_ROOT, CLK_ROOT_ON |
+ CLK_ROOT_SOURCE_SEL(1));
+ /* 100MHz */
+ clock_set_target_val(USB_PHY_REF_CLK_ROOT, CLK_ROOT_ON |
+ CLK_ROOT_SOURCE_SEL(1));
+ clock_enable(CCGR_USB_CTRL1, 1);
+ clock_enable(CCGR_USB_CTRL2, 1);
+ clock_enable(CCGR_USB_PHY1, 1);
+ clock_enable(CCGR_USB_PHY2, 1);
+ }
+}
void init_nand_clk(void)
{
diff --git a/arch/arm/mach-imx/imx8m/soc.c b/arch/arm/mach-imx/imx8m/soc.c
index 0c44022..f2ddc83 100644
--- a/arch/arm/mach-imx/imx8m/soc.c
+++ b/arch/arm/mach-imx/imx8m/soc.c
@@ -296,6 +296,20 @@
#endif
}
+ulong board_get_usable_ram_top(ulong total_size)
+{
+ /*
+ * Some IPs have their accessible address space restricted by
+ * the interconnect. Let's make sure U-Boot only ever uses the
+ * space below the 4G address boundary (which is 3GiB big),
+ * even when the effective available memory is bigger.
+ */
+ if (PHYS_SDRAM + gd->ram_size > 0x80000000)
+ return 0x80000000;
+
+ return PHYS_SDRAM + gd->ram_size;
+}
+
static u32 get_cpu_variant_type(u32 type)
{
struct ocotp_regs *ocotp = (struct ocotp_regs *)OCOTP_BASE_ADDR;
@@ -571,6 +585,67 @@
}
#endif
+#if defined(CONFIG_IMX8M)
+#include <spl.h>
+int spl_mmc_emmc_boot_partition(struct mmc *mmc)
+{
+ u32 *rom_log_addr = (u32 *)0x9e0;
+ u32 *rom_log;
+ u8 event_id;
+ int i, part;
+
+ part = default_spl_mmc_emmc_boot_partition(mmc);
+
+ /* If the ROM event log pointer is not valid. */
+ if (*rom_log_addr < 0x900000 || *rom_log_addr >= 0xb00000 ||
+ *rom_log_addr & 0x3)
+ return part;
+
+ /* Parse the ROM event ID version 2 log */
+ rom_log = (u32 *)(uintptr_t)(*rom_log_addr);
+ for (i = 0; i < 128; i++) {
+ event_id = rom_log[i] >> 24;
+ switch (event_id) {
+ case 0x00: /* End of list */
+ return part;
+ /* Log entries with 1 parameter, skip 1 */
+ case 0x80: /* Start to perform the device initialization */
+ case 0x81: /* The boot device initialization completes */
+ case 0x8f: /* The boot device initialization fails */
+ case 0x90: /* Start to read data from boot device */
+ case 0x91: /* Reading data from boot device completes */
+ case 0x9f: /* Reading data from boot device fails */
+ i += 1;
+ continue;
+ /* Log entries with 2 parameters, skip 2 */
+ case 0xa0: /* Image authentication result */
+ case 0xc0: /* Jump to the boot image soon */
+ i += 2;
+ continue;
+ /* Boot from the secondary boot image */
+ case 0x51:
+ /*
+ * Swap the eMMC boot partitions in case there was a
+ * fallback event (i.e. primary image was corrupted
+ * and that corruption was recognized by the BootROM),
+ * so the SPL loads the rest of the U-Boot from the
+ * correct eMMC boot partition, since the BootROM
+ * leaves the boot partition set to the corrupted one.
+ */
+ if (part == 1)
+ part = 2;
+ else if (part == 2)
+ part = 1;
+ continue;
+ default:
+ continue;
+ }
+ }
+
+ return part;
+}
+#endif
+
bool is_usb_boot(void)
{
return get_boot_device() == USB_BOOT;
diff --git a/arch/arm/mach-imx/mmdc_size.c b/arch/arm/mach-imx/mmdc_size.c
index 1a09472..41a5af6 100644
--- a/arch/arm/mach-imx/mmdc_size.c
+++ b/arch/arm/mach-imx/mmdc_size.c
@@ -24,11 +24,11 @@
u32 misc;
};
-#define ESD_MMDC_CTL_GET_ROW(mdctl) ((ctl >> 24) & 7)
-#define ESD_MMDC_CTL_GET_COLUMN(mdctl) ((ctl >> 20) & 7)
-#define ESD_MMDC_CTL_GET_WIDTH(mdctl) ((ctl >> 16) & 3)
-#define ESD_MMDC_CTL_GET_CS1(mdctl) ((ctl >> 30) & 1)
-#define ESD_MMDC_MISC_GET_BANK(mdmisc) ((misc >> 5) & 1)
+#define ESD_MMDC_CTL_GET_ROW(mdctl) ((mdctl >> 24) & 7)
+#define ESD_MMDC_CTL_GET_COLUMN(mdctl) ((mdctl >> 20) & 7)
+#define ESD_MMDC_CTL_GET_WIDTH(mdctl) ((mdctl >> 16) & 3)
+#define ESD_MMDC_CTL_GET_CS1(mdctl) ((mdctl >> 30) & 1)
+#define ESD_MMDC_MISC_GET_BANK(mdmisc) ((mdmisc >> 5) & 1)
/*
* imx_ddr_size - return size in bytes of DRAM according MMDC config
diff --git a/arch/arm/mach-imx/mx5/Kconfig b/arch/arm/mach-imx/mx5/Kconfig
index 580b458..494e213 100644
--- a/arch/arm/mach-imx/mx5/Kconfig
+++ b/arch/arm/mach-imx/mx5/Kconfig
@@ -29,7 +29,6 @@
select DM_SERIAL
select DM_MMC
select BLK
- select DM_USB
select DM_REGULATOR
select MX53
imply CMD_DM
diff --git a/arch/arm/mach-imx/mx6/Kconfig b/arch/arm/mach-imx/mx6/Kconfig
index 23cab39..a03eca8 100644
--- a/arch/arm/mach-imx/mx6/Kconfig
+++ b/arch/arm/mach-imx/mx6/Kconfig
@@ -239,7 +239,6 @@
select DM_MMC
select DM_PCI
select DM_SCSI
- select DM_USB
select DM_VIDEO
select OF_CONTROL
select SUPPORT_SPL
@@ -556,7 +555,6 @@
select DM_SERIAL
select DM_I2C
select DM_GPIO
- select DM_USB
select SUPPORT_SPL
select SPL_SEPARATE_BSS if SPL
imply CMD_DM
diff --git a/arch/arm/mach-mvebu/armada3700/cpu.c b/arch/arm/mach-mvebu/armada3700/cpu.c
index 9aec0ce..7702028 100644
--- a/arch/arm/mach-mvebu/armada3700/cpu.c
+++ b/arch/arm/mach-mvebu/armada3700/cpu.c
@@ -331,6 +331,10 @@
/* Calculate fixup offset from first child address (in last cell) */
fix_offset = base - fdt32_to_cpu(ranges[2]);
+ /* If fixup offset is zero then there is nothing to fix */
+ if (!fix_offset)
+ return 0;
+
/*
* Fix address (last cell) of each child address and each parent
* address
diff --git a/arch/arm/mach-omap2/am33xx/Kconfig b/arch/arm/mach-omap2/am33xx/Kconfig
index 65f4394..88cb957 100644
--- a/arch/arm/mach-omap2/am33xx/Kconfig
+++ b/arch/arm/mach-omap2/am33xx/Kconfig
@@ -94,7 +94,6 @@
select DM
select DM_SERIAL
select DM_GPIO
- select DM_USB
select DM_VIDEO
select DM_PANEL_HX8238D
diff --git a/arch/arm/mach-stm32mp/Kconfig b/arch/arm/mach-stm32mp/Kconfig
index 7c25266..0e59931 100644
--- a/arch/arm/mach-stm32mp/Kconfig
+++ b/arch/arm/mach-stm32mp/Kconfig
@@ -174,10 +174,12 @@
config CMD_STM32KEY
bool "command stm32key to fuse public key hash"
- default y
+ default n
help
fuse public key hash in corresponding fuse used to authenticate
binary.
+ This command is used to evaluate the secure boot on stm32mp SOC,
+ it is deactivated by default in real products.
config PRE_CON_BUF_ADDR
default 0xC02FF000
diff --git a/arch/arm/mach-stm32mp/cmd_stm32key.c b/arch/arm/mach-stm32mp/cmd_stm32key.c
index 42fdc11..50840b0 100644
--- a/arch/arm/mach-stm32mp/cmd_stm32key.c
+++ b/arch/arm/mach-stm32mp/cmd_stm32key.c
@@ -11,13 +11,30 @@
#include <dm/device.h>
#include <dm/uclass.h>
-#define STM32_OTP_HASH_KEY_START 24
-#define STM32_OTP_HASH_KEY_SIZE 8
+/* Closed device : bit 6 of OPT0*/
+#define STM32_OTP_CLOSE_ID 0
+#define STM32_OTP_CLOSE_MASK BIT(6)
+
+/* HASH of key: 8 OTPs, starting with OTP24) */
+#define STM32_OTP_HASH_KEY_START 24
+#define STM32_OTP_HASH_KEY_SIZE 8
+
+static int get_misc_dev(struct udevice **dev)
+{
+ int ret;
+
+ ret = uclass_get_device_by_driver(UCLASS_MISC, DM_DRIVER_GET(stm32mp_bsec), dev);
+ if (ret)
+ log_err("Can't find stm32mp_bsec driver\n");
+
+ return ret;
+}
static void read_hash_value(u32 addr)
{
int i;
+ printf("Read KEY at 0x%x\n", addr);
for (i = 0; i < STM32_OTP_HASH_KEY_SIZE; i++) {
printf("OTP value %i: %x\n", STM32_OTP_HASH_KEY_START + i,
__be32_to_cpu(*(u32 *)addr));
@@ -25,32 +42,101 @@
}
}
-static void fuse_hash_value(u32 addr, bool print)
+static int read_hash_otp(bool print, bool *locked, bool *closed)
{
struct udevice *dev;
- u32 word, val;
- int i, ret;
+ int i, word, ret;
+ int nb_invalid = 0, nb_zero = 0, nb_lock = 0;
+ u32 val, lock;
+ bool status;
- ret = uclass_get_device_by_driver(UCLASS_MISC,
- DM_DRIVER_GET(stm32mp_bsec),
- &dev);
- if (ret) {
- log_err("Can't find stm32mp_bsec driver\n");
- return;
+ ret = get_misc_dev(&dev);
+ if (ret)
+ return ret;
+
+ for (i = 0, word = STM32_OTP_HASH_KEY_START; i < STM32_OTP_HASH_KEY_SIZE; i++, word++) {
+ ret = misc_read(dev, STM32_BSEC_OTP(word), &val, 4);
+ if (ret != 4)
+ val = ~0x0;
+ ret = misc_read(dev, STM32_BSEC_LOCK(word), &lock, 4);
+ if (ret != 4)
+ lock = -1;
+ if (print)
+ printf("OTP HASH %i: %x lock : %d\n", word, val, lock);
+ if (val == ~0x0)
+ nb_invalid++;
+ else if (val == 0x0)
+ nb_zero++;
+ if (lock == 1)
+ nb_lock++;
}
- for (i = 0; i < STM32_OTP_HASH_KEY_SIZE; i++) {
+ word = STM32_OTP_CLOSE_ID;
+ ret = misc_read(dev, STM32_BSEC_OTP(word), &val, 4);
+ if (ret != 4)
+ val = 0x0;
+ ret = misc_read(dev, STM32_BSEC_LOCK(word), &lock, 4);
+ if (ret != 4)
+ lock = -1;
+
+ status = (val & STM32_OTP_CLOSE_MASK) == STM32_OTP_CLOSE_MASK;
+ if (closed)
+ *closed = status;
+ if (print)
+ printf("OTP %d: closed status: %d lock : %d\n", word, status, lock);
+
+ status = (nb_lock == STM32_OTP_HASH_KEY_SIZE);
+ if (locked)
+ *locked = status;
+ if (!status && print)
+ printf("Hash of key is not locked!\n");
+
+ if (nb_invalid == STM32_OTP_HASH_KEY_SIZE) {
if (print)
- printf("Fuse OTP %i : %x\n",
- STM32_OTP_HASH_KEY_START + i,
- __be32_to_cpu(*(u32 *)addr));
+ printf("Hash of key is invalid!\n");
+ return -EINVAL;
+ }
+ if (nb_zero == STM32_OTP_HASH_KEY_SIZE) {
+ if (print)
+ printf("Hash of key is free!\n");
+ return -ENOENT;
+ }
+
+ return 0;
+}
- word = STM32_OTP_HASH_KEY_START + i;
+static int fuse_hash_value(u32 addr, bool print)
+{
+ struct udevice *dev;
+ u32 word, val;
+ int i, ret;
+
+ ret = get_misc_dev(&dev);
+ if (ret)
+ return ret;
+
+ for (i = 0, word = STM32_OTP_HASH_KEY_START;
+ i < STM32_OTP_HASH_KEY_SIZE;
+ i++, word++, addr += 4) {
val = __be32_to_cpu(*(u32 *)addr);
- misc_write(dev, STM32_BSEC_OTP(word), &val, 4);
+ if (print)
+ printf("Fuse OTP %i : %x\n", word, val);
- addr += 4;
+ ret = misc_write(dev, STM32_BSEC_OTP(word), &val, 4);
+ if (ret != 4) {
+ log_err("Fuse OTP %i failed\n", word);
+ return ret;
+ }
+ /* on success, lock the OTP for HASH key */
+ val = 1;
+ ret = misc_write(dev, STM32_BSEC_LOCK(word), &val, 4);
+ if (ret != 4) {
+ log_err("Lock OTP %i failed\n", word);
+ return ret;
+ }
}
+
+ return 0;
}
static int confirm_prog(void)
@@ -67,36 +153,117 @@
return 0;
}
-static int do_stm32key(struct cmd_tbl *cmdtp, int flag, int argc,
- char *const argv[])
+static int do_stm32key_read(struct cmd_tbl *cmdtp, int flag, int argc, char *const argv[])
{
u32 addr;
- const char *op = argc >= 2 ? argv[1] : NULL;
- int confirmed = argc > 3 && !strcmp(argv[2], "-y");
+
+ if (argc == 1) {
+ read_hash_otp(true, NULL, NULL);
+ return CMD_RET_SUCCESS;
+ }
- argc -= 2 + confirmed;
- argv += 2 + confirmed;
+ addr = simple_strtoul(argv[1], NULL, 16);
+ if (!addr)
+ return CMD_RET_USAGE;
+
+ read_hash_value(addr);
+
+ return CMD_RET_SUCCESS;
+}
+
+static int do_stm32key_fuse(struct cmd_tbl *cmdtp, int flag, int argc, char *const argv[])
+{
+ u32 addr;
+ bool yes = false, lock, closed;
- if (argc < 1)
+ if (argc < 2)
return CMD_RET_USAGE;
- addr = simple_strtoul(argv[0], NULL, 16);
+ if (argc == 3) {
+ if (strcmp(argv[1], "-y"))
+ return CMD_RET_USAGE;
+ yes = true;
+ }
+
+ addr = simple_strtoul(argv[argc - 1], NULL, 16);
if (!addr)
return CMD_RET_USAGE;
- if (!strcmp(op, "read"))
- read_hash_value(addr);
+ if (read_hash_otp(!yes, &lock, &closed) != -ENOENT) {
+ printf("Error: can't fuse again the OTP\n");
+ return CMD_RET_FAILURE;
+ }
- if (!strcmp(op, "fuse")) {
- if (!confirmed && !confirm_prog())
- return CMD_RET_FAILURE;
- fuse_hash_value(addr, !confirmed);
+ if (lock || closed) {
+ printf("Error: invalid OTP configuration (lock=%d, closed=%d)\n", lock, closed);
+ return CMD_RET_FAILURE;
}
+ if (!yes && !confirm_prog())
+ return CMD_RET_FAILURE;
+
+ if (fuse_hash_value(addr, !yes))
+ return CMD_RET_FAILURE;
+
+ printf("Hash key updated !\n");
+
return CMD_RET_SUCCESS;
}
+static int do_stm32key_close(struct cmd_tbl *cmdtp, int flag, int argc, char *const argv[])
+{
+ bool yes, lock, closed;
+ struct udevice *dev;
+ u32 val;
+ int ret;
+
+ yes = false;
+ if (argc == 2) {
+ if (strcmp(argv[1], "-y"))
+ return CMD_RET_USAGE;
+ yes = true;
+ }
+
+ ret = read_hash_otp(!yes, &lock, &closed);
+ if (ret) {
+ if (ret == -ENOENT)
+ printf("Error: OTP not programmed!\n");
+ return CMD_RET_FAILURE;
+ }
+
+ if (closed) {
+ printf("Error: already closed!\n");
+ return CMD_RET_FAILURE;
+ }
+
+ if (!lock)
+ printf("Warning: OTP not locked!\n");
+
+ if (!yes && !confirm_prog())
+ return CMD_RET_FAILURE;
+
+ ret = get_misc_dev(&dev);
+ if (ret)
+ return CMD_RET_FAILURE;
+
+ val = STM32_OTP_CLOSE_MASK;
+ ret = misc_write(dev, STM32_BSEC_OTP(STM32_OTP_CLOSE_ID), &val, 4);
+ if (ret != 4) {
+ printf("Error: can't update OTP\n");
+ return CMD_RET_FAILURE;
+ }
+
+ printf("Device is closed !\n");
+
+ return CMD_RET_SUCCESS;
+}
+
+static char stm32key_help_text[] =
+ "read [<addr>]: Read the hash stored at addr in memory or in OTP\n"
+ "stm32key fuse [-y] <addr> : Fuse hash stored at addr in OTP\n"
+ "stm32key close [-y] : Close the device, the hash stored in OTP\n";
+
-U_BOOT_CMD(stm32key, 4, 1, do_stm32key,
- "Fuse ST Hash key",
- "read <addr>: Read the hash store at addr in memory\n"
- "stm32key fuse [-y] <addr> : Fuse hash store at addr in otp\n");
+U_BOOT_CMD_WITH_SUBCMDS(stm32key, "Fuse ST Hash key", stm32key_help_text,
+ U_BOOT_SUBCMD_MKENT(read, 2, 0, do_stm32key_read),
+ U_BOOT_SUBCMD_MKENT(fuse, 3, 0, do_stm32key_fuse),
+ U_BOOT_SUBCMD_MKENT(close, 2, 0, do_stm32key_close));
diff --git a/arch/arm/mach-stm32mp/cmd_stm32prog/cmd_stm32prog.c b/arch/arm/mach-stm32mp/cmd_stm32prog/cmd_stm32prog.c
index feff73c..064f51b 100644
--- a/arch/arm/mach-stm32mp/cmd_stm32prog/cmd_stm32prog.c
+++ b/arch/arm/mach-stm32mp/cmd_stm32prog/cmd_stm32prog.c
@@ -177,12 +177,12 @@
}
U_BOOT_CMD(stm32prog, 5, 0, do_stm32prog,
+ "start communication with tools STM32Cubeprogrammer",
"<link> <dev> [<addr>] [<size>]\n"
- "start communication with tools STM32Cubeprogrammer on <link> with Flashlayout at <addr>",
- "<link> = serial|usb\n"
- "<dev> = device instance\n"
- "<addr> = address of flashlayout\n"
- "<size> = size of flashlayout\n"
+ " <link> = serial|usb\n"
+ " <dev> = device instance\n"
+ " <addr> = address of flashlayout\n"
+ " <size> = size of flashlayout (optional for image with STM32 header)\n"
);
bool stm32prog_get_tee_partitions(void)
diff --git a/arch/arm/mach-stm32mp/cmd_stm32prog/stm32prog.c b/arch/arm/mach-stm32mp/cmd_stm32prog/stm32prog.c
index f7c93a1..96ebc6d 100644
--- a/arch/arm/mach-stm32mp/cmd_stm32prog/stm32prog.c
+++ b/arch/arm/mach-stm32mp/cmd_stm32prog/stm32prog.c
@@ -1199,13 +1199,13 @@
}
if (!ret)
- ret = stm32prog_alt_add_virt(dfu, "virtual", PHASE_CMD, 512);
+ ret = stm32prog_alt_add_virt(dfu, "virtual", PHASE_CMD, CMD_SIZE);
if (!ret)
- ret = stm32prog_alt_add_virt(dfu, "OTP", PHASE_OTP, 512);
+ ret = stm32prog_alt_add_virt(dfu, "OTP", PHASE_OTP, OTP_SIZE);
if (!ret && CONFIG_IS_ENABLED(DM_PMIC))
- ret = stm32prog_alt_add_virt(dfu, "PMIC", PHASE_PMIC, 8);
+ ret = stm32prog_alt_add_virt(dfu, "PMIC", PHASE_PMIC, PMIC_SIZE);
if (ret)
stm32prog_err("dfu init failed: %d", ret);
diff --git a/arch/arm/mach-stm32mp/cmd_stm32prog/stm32prog.h b/arch/arm/mach-stm32mp/cmd_stm32prog/stm32prog.h
index efb51a3..9d58cf0 100644
--- a/arch/arm/mach-stm32mp/cmd_stm32prog/stm32prog.h
+++ b/arch/arm/mach-stm32mp/cmd_stm32prog/stm32prog.h
@@ -19,6 +19,7 @@
#define DEFAULT_ADDRESS 0xFFFFFFFF
+#define CMD_SIZE 512
#define OTP_SIZE 1024
#define PMIC_SIZE 8
diff --git a/arch/arm/mach-stm32mp/cmd_stm32prog/stm32prog_usb.c b/arch/arm/mach-stm32mp/cmd_stm32prog/stm32prog_usb.c
index d4a3f7e..e8acc30 100644
--- a/arch/arm/mach-stm32mp/cmd_stm32prog/stm32prog_usb.c
+++ b/arch/arm/mach-stm32mp/cmd_stm32prog/stm32prog_usb.c
@@ -178,7 +178,7 @@
switch (dfu->data.virt.dev_num) {
case PHASE_CMD:
- *size = 512;
+ *size = CMD_SIZE;
break;
case PHASE_OTP:
*size = OTP_SIZE;
diff --git a/arch/arm/mach-stm32mp/cpu.c b/arch/arm/mach-stm32mp/cpu.c
index 592bfd4..f6ed2ce 100644
--- a/arch/arm/mach-stm32mp/cpu.c
+++ b/arch/arm/mach-stm32mp/cpu.c
@@ -483,6 +483,11 @@
STM32_UART7_BASE,
STM32_UART8_BASE
};
+ const u32 sdmmc_addr[] = {
+ STM32_SDMMC1_BASE,
+ STM32_SDMMC2_BASE,
+ STM32_SDMMC3_BASE
+ };
char cmd[60];
u32 boot_ctx = readl(TAMP_BOOT_CONTEXT);
u32 boot_mode =
@@ -525,7 +530,16 @@
break;
case BOOT_FLASH_SD:
case BOOT_FLASH_EMMC:
- sprintf(cmd, "%d", instance);
+ if (instance > ARRAY_SIZE(sdmmc_addr))
+ break;
+ /* search associated sdmmc node in devicetree */
+ sprintf(cmd, "mmc@%x", sdmmc_addr[instance]);
+ if (uclass_get_device_by_name(UCLASS_MMC, cmd, &dev)) {
+ printf("mmc%d = %s not found in device tree!\n",
+ instance, cmd);
+ break;
+ }
+ sprintf(cmd, "%d", dev_seq(dev));
env_set("boot_device", "mmc");
env_set("boot_instance", cmd);
break;
diff --git a/arch/arm/mach-stm32mp/include/mach/stm32.h b/arch/arm/mach-stm32mp/include/mach/stm32.h
index 5fdb893..c11a990 100644
--- a/arch/arm/mach-stm32mp/include/mach/stm32.h
+++ b/arch/arm/mach-stm32mp/include/mach/stm32.h
@@ -32,6 +32,10 @@
#define STM32_UART7_BASE 0x40018000
#define STM32_UART8_BASE 0x40019000
+#define STM32_SDMMC1_BASE 0x58005000
+#define STM32_SDMMC2_BASE 0x58007000
+#define STM32_SDMMC3_BASE 0x48004000
+
#define STM32_SYSRAM_BASE 0x2FFC0000
#define STM32_SYSRAM_SIZE SZ_256K
diff --git a/arch/arm/mach-stm32mp/syscon.c b/arch/arm/mach-stm32mp/syscon.c
index 3e61ce4..a0e8e1d 100644
--- a/arch/arm/mach-stm32mp/syscon.c
+++ b/arch/arm/mach-stm32mp/syscon.c
@@ -4,6 +4,7 @@
*/
#include <common.h>
+#include <clk.h>
#include <dm.h>
#include <syscon.h>
#include <asm/arch/stm32.h>
@@ -14,9 +15,22 @@
{ }
};
+static int stm32mp_syscon_probe(struct udevice *dev)
+{
+ struct clk_bulk clk_bulk;
+ int ret;
+
+ ret = clk_get_bulk(dev, &clk_bulk);
+ if (!ret)
+ clk_enable_bulk(&clk_bulk);
+
+ return 0;
+}
+
U_BOOT_DRIVER(syscon_stm32mp) = {
.name = "stmp32mp_syscon",
.id = UCLASS_SYSCON,
.of_match = stm32mp_syscon_ids,
.bind = dm_scan_fdt_dev,
+ .probe = stm32mp_syscon_probe,
};
diff --git a/arch/m68k/Kconfig b/arch/m68k/Kconfig
index cf45d78..1ab37cc 100644
--- a/arch/m68k/Kconfig
+++ b/arch/m68k/Kconfig
@@ -53,12 +53,6 @@
select DM_SERIAL
bool
-config MCF5445x
- select OF_CONTROL
- select DM
- select DM_SERIAL
- bool
-
config MCF5227x
select OF_CONTROL
select DM
@@ -119,26 +113,10 @@
bool
select MCF5441x
-config M54451
- bool
- select MCF5445x
-
-config M54455
- bool
- select MCF5445x
-
-config M52277
- bool
- select MCF5227x
-
choice
prompt "Target select"
optional
-config TARGET_M52277EVB
- bool "Support M52277EVB"
- select M52277
-
config TARGET_M5235EVB
bool "Support M5235EVB"
select M5235
@@ -191,18 +169,6 @@
bool "Support M5373EVB"
select M5373
-config TARGET_M54418TWR
- bool "Support M54418TWR"
- select M54418
-
-config TARGET_M54451EVB
- bool "Support M54451EVB"
- select M54451
-
-config TARGET_M54455EVB
- bool "Support M54455EVB"
- select M54455
-
config TARGET_AMCORE
bool "Support AMCORE"
select M5307
@@ -217,7 +183,6 @@
source "board/astro/mcf5373l/Kconfig"
source "board/cobra5272/Kconfig"
source "board/freescale/m5208evbe/Kconfig"
-source "board/freescale/m52277evb/Kconfig"
source "board/freescale/m5235evb/Kconfig"
source "board/freescale/m5249evb/Kconfig"
source "board/freescale/m5253demo/Kconfig"
@@ -227,9 +192,6 @@
source "board/freescale/m53017evb/Kconfig"
source "board/freescale/m5329evb/Kconfig"
source "board/freescale/m5373evb/Kconfig"
-source "board/freescale/m54418twr/Kconfig"
-source "board/freescale/m54451evb/Kconfig"
-source "board/freescale/m54455evb/Kconfig"
source "board/sysam/amcore/Kconfig"
source "board/sysam/stmark2/Kconfig"
diff --git a/arch/m68k/Makefile b/arch/m68k/Makefile
index 86b36e1..63f1810 100644
--- a/arch/m68k/Makefile
+++ b/arch/m68k/Makefile
@@ -18,13 +18,11 @@
cpuflags-$(CONFIG_MCF5301x) := -mcpu=53015 -fPIC
cpuflags-$(CONFIG_MCF532x) := -mcpu=5329 -fPIC
cpuflags-$(CONFIG_MCF5441x) := -mcpu=54418 -fPIC
-cpuflags-$(CONFIG_MCF5445x) := -mcpu=54455 -fPIC
PLATFORM_CPPFLAGS += $(cpuflags-y)
ldflags-$(CONFIG_MCF5441x) := --got=single
-ldflags-$(CONFIG_MCF5445x) := --got=single
ifneq (,$(findstring -linux-,$(shell $(CC) --version)))
ifneq (,$(findstring GOT,$(shell $(LD) --help)))
diff --git a/arch/m68k/cpu/mcf5445x/cpu_init.c b/arch/m68k/cpu/mcf5445x/cpu_init.c
index 9deab51..9b3f9f0 100644
--- a/arch/m68k/cpu/mcf5445x/cpu_init.c
+++ b/arch/m68k/cpu/mcf5445x/cpu_init.c
@@ -73,13 +73,6 @@
{
gpio_t *gpio = (gpio_t *)MMAP_GPIO;
-#ifdef CONFIG_MCF5445x
- out_8(&gpio->par_dspi,
- GPIO_PAR_DSPI_SIN_SIN |
- GPIO_PAR_DSPI_SOUT_SOUT |
- GPIO_PAR_DSPI_SCK_SCK);
-#endif
-
#ifdef CONFIG_MCF5441x
pm_t *pm = (pm_t *)MMAP_PM;
@@ -212,36 +205,6 @@
#endif
#endif /* CONFIG_MCF5441x */
-#ifdef CONFIG_MCF5445x
- scm1_t *scm1 = (scm1_t *) MMAP_SCM1;
-
- out_be32(&scm1->mpr, 0x77777777);
- out_be32(&scm1->pacra, 0);
- out_be32(&scm1->pacrb, 0);
- out_be32(&scm1->pacrc, 0);
- out_be32(&scm1->pacrd, 0);
- out_be32(&scm1->pacre, 0);
- out_be32(&scm1->pacrf, 0);
- out_be32(&scm1->pacrg, 0);
-
- /* FlexBus */
- out_8(&gpio->par_be,
- GPIO_PAR_BE_BE3_BE3 | GPIO_PAR_BE_BE2_BE2 |
- GPIO_PAR_BE_BE1_BE1 | GPIO_PAR_BE_BE0_BE0);
- out_8(&gpio->par_fbctl,
- GPIO_PAR_FBCTL_OE | GPIO_PAR_FBCTL_TA_TA |
- GPIO_PAR_FBCTL_RW_RW | GPIO_PAR_FBCTL_TS_TS);
-
-#ifdef CONFIG_CF_SPI
- cfspi_port_conf();
-#endif
-
-#ifdef CONFIG_SYS_FSL_I2C
- out_be16(&gpio->par_feci2c,
- GPIO_PAR_FECI2C_SCL_SCL | GPIO_PAR_FECI2C_SDA_SDA);
-#endif
-#endif /* CONFIG_MCF5445x */
-
/* FlexBus Chipselect */
init_fbcs();
@@ -364,41 +327,7 @@
setbits_8(&gpio->par_cani2c,
GPIO_PAR_CANI2C_CAN1TX_U9TXD | GPIO_PAR_CANI2C_CAN1RX_U9RXD);
break;
-#endif
-#ifdef CONFIG_MCF5445x
- case 0:
- clrbits_8(&gpio->par_uart,
- GPIO_PAR_UART_U0TXD_U0TXD | GPIO_PAR_UART_U0RXD_U0RXD);
- setbits_8(&gpio->par_uart,
- GPIO_PAR_UART_U0TXD_U0TXD | GPIO_PAR_UART_U0RXD_U0RXD);
- break;
- case 1:
-#ifdef CONFIG_SYS_UART1_PRI_GPIO
- clrbits_8(&gpio->par_uart,
- GPIO_PAR_UART_U1TXD_U1TXD | GPIO_PAR_UART_U1RXD_U1RXD);
- setbits_8(&gpio->par_uart,
- GPIO_PAR_UART_U1TXD_U1TXD | GPIO_PAR_UART_U1RXD_U1RXD);
-#elif defined(CONFIG_SYS_UART1_ALT1_GPIO)
- clrbits_be16(&gpio->par_ssi,
- ~(GPIO_PAR_SSI_SRXD_UNMASK | GPIO_PAR_SSI_STXD_UNMASK));
- setbits_be16(&gpio->par_ssi,
- GPIO_PAR_SSI_SRXD_U1RXD | GPIO_PAR_SSI_STXD_U1TXD);
#endif
- break;
- case 2:
-#if defined(CONFIG_SYS_UART2_ALT1_GPIO)
- clrbits_8(&gpio->par_timer,
- ~(GPIO_PAR_TIMER_T3IN_UNMASK | GPIO_PAR_TIMER_T2IN_UNMASK));
- setbits_8(&gpio->par_timer,
- GPIO_PAR_TIMER_T3IN_U2RXD | GPIO_PAR_TIMER_T2IN_U2TXD);
-#elif defined(CONFIG_SYS_UART2_ALT2_GPIO)
- clrbits_8(&gpio->par_timer,
- ~(GPIO_PAR_FECI2C_SCL_UNMASK | GPIO_PAR_FECI2C_SDA_UNMASK));
- setbits_8(&gpio->par_timer,
- GPIO_PAR_FECI2C_SCL_U2TXD | GPIO_PAR_FECI2C_SDA_U2RXD);
-#endif
- break;
-#endif /* CONFIG_MCF5445x */
}
}
@@ -411,46 +340,6 @@
if (fec_get_base_addr(0, &fec0_base))
return -1;
-#ifdef CONFIG_MCF5445x
- if (setclear) {
-#ifdef CONFIG_SYS_FEC_NO_SHARED_PHY
- if (info->iobase == fec0_base)
- setbits_be16(&gpio->par_feci2c,
- GPIO_PAR_FECI2C_MDC0_MDC0 |
- GPIO_PAR_FECI2C_MDIO0_MDIO0);
- else
- setbits_be16(&gpio->par_feci2c,
- GPIO_PAR_FECI2C_MDC1_MDC1 |
- GPIO_PAR_FECI2C_MDIO1_MDIO1);
-#else
- setbits_be16(&gpio->par_feci2c,
- GPIO_PAR_FECI2C_MDC0_MDC0 | GPIO_PAR_FECI2C_MDIO0_MDIO0);
-#endif
-
- if (info->iobase == fec0_base)
- setbits_8(&gpio->par_fec, GPIO_PAR_FEC_FEC0_RMII_GPIO);
- else
- setbits_8(&gpio->par_fec, GPIO_PAR_FEC_FEC1_RMII_ATA);
- } else {
- clrbits_be16(&gpio->par_feci2c,
- GPIO_PAR_FECI2C_MDC0_MDC0 | GPIO_PAR_FECI2C_MDIO0_MDIO0);
-
- if (info->iobase == fec0_base) {
-#ifdef CONFIG_SYS_FEC_FULL_MII
- setbits_8(&gpio->par_fec, GPIO_PAR_FEC_FEC0_MII);
-#else
- clrbits_8(&gpio->par_fec, ~GPIO_PAR_FEC_FEC0_UNMASK);
-#endif
- } else {
-#ifdef CONFIG_SYS_FEC_FULL_MII
- setbits_8(&gpio->par_fec, GPIO_PAR_FEC_FEC1_MII);
-#else
- clrbits_8(&gpio->par_fec, ~GPIO_PAR_FEC_FEC1_UNMASK);
-#endif
- }
- }
-#endif /* CONFIG_MCF5445x */
-
#ifdef CONFIG_MCF5441x
if (setclear) {
out_8(&gpio->par_fec, 0x03);
diff --git a/arch/m68k/cpu/mcf5445x/dspi.c b/arch/m68k/cpu/mcf5445x/dspi.c
index b0e2f2c..456af17 100644
--- a/arch/m68k/cpu/mcf5445x/dspi.c
+++ b/arch/m68k/cpu/mcf5445x/dspi.c
@@ -15,30 +15,6 @@
{
struct gpio *gpio = (struct gpio *)MMAP_GPIO;
-#ifdef CONFIG_MCF5445x
- switch (cs) {
- case 0:
- clrbits_8(&gpio->par_dspi, GPIO_PAR_DSPI_PCS0_PCS0);
- setbits_8(&gpio->par_dspi, GPIO_PAR_DSPI_PCS0_PCS0);
- break;
- case 1:
- clrbits_8(&gpio->par_dspi, GPIO_PAR_DSPI_PCS1_PCS1);
- setbits_8(&gpio->par_dspi, GPIO_PAR_DSPI_PCS1_PCS1);
- break;
- case 2:
- clrbits_8(&gpio->par_dspi, GPIO_PAR_DSPI_PCS2_PCS2);
- setbits_8(&gpio->par_dspi, GPIO_PAR_DSPI_PCS2_PCS2);
- break;
- case 3:
- clrbits_8(&gpio->par_dma, ~GPIO_PAR_DMA_DACK0_UNMASK);
- setbits_8(&gpio->par_dma, GPIO_PAR_DMA_DACK0_PCS3);
- break;
- case 5:
- clrbits_8(&gpio->par_dspi, GPIO_PAR_DSPI_PCS5_PCS5);
- setbits_8(&gpio->par_dspi, GPIO_PAR_DSPI_PCS5_PCS5);
- break;
- }
-#endif
#ifdef CONFIG_MCF5441x
switch (cs) {
case 0:
@@ -61,25 +37,6 @@
{
struct gpio *gpio = (struct gpio *)MMAP_GPIO;
-#ifdef CONFIG_MCF5445x
- switch (cs) {
- case 0:
- clrbits_8(&gpio->par_dspi, GPIO_PAR_DSPI_PCS0_PCS0);
- break;
- case 1:
- clrbits_8(&gpio->par_dspi, GPIO_PAR_DSPI_PCS1_PCS1);
- break;
- case 2:
- clrbits_8(&gpio->par_dspi, GPIO_PAR_DSPI_PCS2_PCS2);
- break;
- case 3:
- clrbits_8(&gpio->par_dma, ~GPIO_PAR_DMA_DACK0_UNMASK);
- break;
- case 5:
- clrbits_8(&gpio->par_dspi, GPIO_PAR_DSPI_PCS5_PCS5);
- break;
- }
-#endif
#ifdef CONFIG_MCF5441x
if (cs == 1)
clrbits_8(&gpio->par_dspiow, GPIO_PAR_DSPIOW_DSPI0PSC1);
diff --git a/arch/m68k/cpu/mcf5445x/speed.c b/arch/m68k/cpu/mcf5445x/speed.c
index a0b9af8..eb73da6 100644
--- a/arch/m68k/cpu/mcf5445x/speed.c
+++ b/arch/m68k/cpu/mcf5445x/speed.c
@@ -42,11 +42,6 @@
/* Round divider down to nearest power of two */
for (i = 0, j = lpdiv; j != 1; j >>= 1, i++) ;
-#ifdef CONFIG_MCF5445x
- /* Apply the divider to the system clock */
- clrsetbits_be16(&ccm->cdr, 0x0f00, CCM_CDR_LPDIV(i));
-#endif
-
/* Enable Limp Mode */
setbits_be16(&ccm->misccr, CCM_MISCCR_LIMP);
}
@@ -127,154 +122,12 @@
}
#endif
-#ifdef CONFIG_MCF5445x
-void setup_5445x_clocks(void)
-{
- ccm_t *ccm = (ccm_t *)MMAP_CCM;
- pll_t *pll = (pll_t *)MMAP_PLL;
- int pllmult_nopci[] = { 20, 10, 24, 18, 12, 6, 16, 8 };
- int pllmult_pci[] = { 12, 6, 16, 8 };
- int vco = 0, temp, fbtemp, pcrvalue;
- int *pPllmult = NULL;
- u16 fbpll_mask;
-#ifdef CONFIG_PCI
- int bPci;
-#endif
-
-#ifdef CONFIG_M54455EVB
- u8 *cpld = (u8 *)(CONFIG_SYS_CS2_BASE + 3);
-#endif
- u8 bootmode;
-
- /* To determine PCI is present or not */
- if (((in_be16(&ccm->ccr) & CCM_CCR_360_FBCONFIG_MASK) == 0x00e0) ||
- ((in_be16(&ccm->ccr) & CCM_CCR_360_FBCONFIG_MASK) == 0x0060)) {
- pPllmult = &pllmult_pci[0];
- fbpll_mask = 3; /* 11b */
-#ifdef CONFIG_PCI
- bPci = 1;
-#endif
- } else {
- pPllmult = &pllmult_nopci[0];
- fbpll_mask = 7; /* 111b */
-#ifdef CONFIG_PCI
- gd->pci_clk = 0;
- bPci = 0;
-#endif
- }
-
-#ifdef CONFIG_M54455EVB
- bootmode = (in_8(cpld) & 0x03);
-
- if (bootmode != 3) {
- /* Temporary read from CCR- fixed fb issue, must be the same clock
- as pci or input clock, causing cpld/fpga read inconsistancy */
- fbtemp = pPllmult[ccm->ccr & fbpll_mask];
-
- /* Break down into small pieces, code still in flex bus */
- pcrvalue = in_be32(&pll->pcr) & 0xFFFFF0FF;
- temp = fbtemp - 1;
- pcrvalue |= PLL_PCR_OUTDIV3(temp);
-
- out_be32(&pll->pcr, pcrvalue);
- }
-#endif
-#ifdef CONFIG_M54451EVB
- /* No external logic to read the bootmode, hard coded from built */
-#ifdef CONFIG_CF_SBF
- bootmode = 3;
-#else
- bootmode = 2;
-
- /* default value is 16 mul, set to 20 mul */
- pcrvalue = (in_be32(&pll->pcr) & 0x00FFFFFF) | 0x14000000;
- out_be32(&pll->pcr, pcrvalue);
- while ((in_be32(&pll->psr) & PLL_PSR_LOCK) != PLL_PSR_LOCK)
- ;
-#endif
-#endif
-
- if (bootmode == 0) {
- /* RCON mode */
- vco = pPllmult[ccm->rcon & fbpll_mask] * CONFIG_SYS_INPUT_CLKSRC;
-
- if ((vco < CLOCK_PLL_FVCO_MIN) || (vco > CLOCK_PLL_FVCO_MAX)) {
- /* invaild range, re-set in PCR */
- int temp = ((in_be32(&pll->pcr) & PLL_PCR_OUTDIV2_MASK) >> 4) + 1;
- int i, j, bus;
-
- j = (in_be32(&pll->pcr) & 0xFF000000) >> 24;
- for (i = j; i < 0xFF; i++) {
- vco = i * CONFIG_SYS_INPUT_CLKSRC;
- if (vco >= CLOCK_PLL_FVCO_MIN) {
- bus = vco / temp;
- if (bus <= CLOCK_PLL_FSYS_MIN - MHZ)
- continue;
- else
- break;
- }
- }
- pcrvalue = in_be32(&pll->pcr) & 0x00FF00FF;
- fbtemp = ((i - 1) << 8) | ((i - 1) << 12);
- pcrvalue |= ((i << 24) | fbtemp);
-
- out_be32(&pll->pcr, pcrvalue);
- }
- gd->arch.vco_clk = vco; /* Vco clock */
- } else if (bootmode == 2) {
- /* Normal mode */
- vco = ((in_be32(&pll->pcr) & 0xFF000000) >> 24) * CONFIG_SYS_INPUT_CLKSRC;
- if ((vco < CLOCK_PLL_FVCO_MIN) || (vco > CLOCK_PLL_FVCO_MAX)) {
- /* Default value */
- pcrvalue = (in_be32(&pll->pcr) & 0x00FFFFFF);
- pcrvalue |= pPllmult[in_be16(&ccm->ccr) & fbpll_mask] << 24;
- out_be32(&pll->pcr, pcrvalue);
- vco = ((in_be32(&pll->pcr) & 0xFF000000) >> 24) * CONFIG_SYS_INPUT_CLKSRC;
- }
- gd->arch.vco_clk = vco; /* Vco clock */
- } else if (bootmode == 3) {
- /* serial mode */
- vco = ((in_be32(&pll->pcr) & 0xFF000000) >> 24) * CONFIG_SYS_INPUT_CLKSRC;
- gd->arch.vco_clk = vco; /* Vco clock */
- }
-
- if ((in_be16(&ccm->ccr) & CCM_MISCCR_LIMP) == CCM_MISCCR_LIMP) {
- /* Limp mode */
- } else {
- gd->arch.inp_clk = CONFIG_SYS_INPUT_CLKSRC; /* Input clock */
-
- temp = (in_be32(&pll->pcr) & PLL_PCR_OUTDIV1_MASK) + 1;
- gd->cpu_clk = vco / temp; /* cpu clock */
-
- temp = ((in_be32(&pll->pcr) & PLL_PCR_OUTDIV2_MASK) >> 4) + 1;
- gd->bus_clk = vco / temp; /* bus clock */
-
- temp = ((in_be32(&pll->pcr) & PLL_PCR_OUTDIV3_MASK) >> 8) + 1;
- gd->arch.flb_clk = vco / temp; /* FlexBus clock */
-
-#ifdef CONFIG_PCI
- if (bPci) {
- temp = ((in_be32(&pll->pcr) & PLL_PCR_OUTDIV4_MASK) >> 12) + 1;
- gd->pci_clk = vco / temp; /* PCI clock */
- }
-#endif
- }
-
-#ifdef CONFIG_SYS_I2C_FSL
- gd->arch.i2c1_clk = gd->bus_clk;
-#endif
-}
-#endif
-
/* get_clocks() fills in gd->cpu_clock and gd->bus_clk */
int get_clocks(void)
{
#ifdef CONFIG_MCF5441x
setup_5441x_clocks();
#endif
-#ifdef CONFIG_MCF5445x
- setup_5445x_clocks();
-#endif
#ifdef CONFIG_SYS_FSL_I2C
gd->arch.i2c1_clk = gd->bus_clk;
diff --git a/arch/m68k/cpu/mcf5445x/start.S b/arch/m68k/cpu/mcf5445x/start.S
index 80eb287..7007d78 100644
--- a/arch/m68k/cpu/mcf5445x/start.S
+++ b/arch/m68k/cpu/mcf5445x/start.S
@@ -202,10 +202,6 @@
move.b #0x80, (%a2)
#endif
-#ifdef CONFIG_MCF5445x
- move.l #0xFC0A4063, %a0
- move.b #0x7F, (%a0)
-#endif
/* Configure DSPI module */
move.l #0xFC05C000, %a0
move.l #0x80FF0C00, (%a0) /* Master, clear TX/RX FIFO */
@@ -214,9 +210,6 @@
#ifdef CONFIG_MCF5441x
move.l #0x3E000016, (%a0)
#endif
-#ifdef CONFIG_MCF5445x
- move.l #0x3E000011, (%a0)
-#endif
move.l #0xFC05C034, %a2 /* dtfr */
move.l #0xFC05C03B, %a3 /* drfr */
diff --git a/arch/m68k/dts/M52277EVB.dts b/arch/m68k/dts/M52277EVB.dts
deleted file mode 100644
index a2210c8..0000000
--- a/arch/m68k/dts/M52277EVB.dts
+++ /dev/null
@@ -1,25 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * Copyright (C) 2018 Angelo Dureghello <angelo@sysam.it>
- */
-
-/dts-v1/;
-/include/ "mcf5227x.dtsi"
-
-/ {
- model = "Freescale M52277EVB";
- compatible = "fsl,M52277EVB";
-
- chosen {
- stdout-path = "serial0:115200n8";
- };
-};
-
-&uart0 {
- u-boot,dm-pre-reloc;
- status = "okay";
-};
-
-&dspi0 {
- status = "okay";
-};
diff --git a/arch/m68k/dts/M52277EVB_stmicro.dts b/arch/m68k/dts/M52277EVB_stmicro.dts
deleted file mode 100644
index 5fd3ca5..0000000
--- a/arch/m68k/dts/M52277EVB_stmicro.dts
+++ /dev/null
@@ -1,22 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * Copyright (C) 2018 Angelo Dureghello <angelo@sysam.it>
- */
-
-/dts-v1/;
-/include/ "mcf5227x.dtsi"
-
-/ {
- model = "Freescale M52277_stmicro";
- compatible = "fsl,M52277_stmicro";
-
- chosen {
- stdout-path = "serial0:115200n8";
- };
-};
-
-&uart0 {
- u-boot,dm-pre-reloc;
- status = "okay";
-};
-
diff --git a/arch/m68k/dts/M54418TWR.dts b/arch/m68k/dts/M54418TWR.dts
deleted file mode 100644
index 058707f..0000000
--- a/arch/m68k/dts/M54418TWR.dts
+++ /dev/null
@@ -1,34 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * Copyright (C) 2018 Angelo Dureghello <angelo@sysam.it>
- */
-
-/dts-v1/;
-/include/ "mcf5441x.dtsi"
-
-/ {
- model = "Freescale M54418TWR";
- compatible = "fsl,M54418TWR";
-
- chosen {
- stdout-path = "serial0:115200n8";
- };
-};
-
-&uart0 {
- u-boot,dm-pre-reloc;
- status = "okay";
-};
-
-&dspi0 {
- status = "okay";
-};
-
-&fec0 {
- status = "okay";
-};
-
-&fec1 {
- status = "okay";
- mii-base = <0>;
-};
diff --git a/arch/m68k/dts/M54418TWR_nand_mii.dts b/arch/m68k/dts/M54418TWR_nand_mii.dts
deleted file mode 100644
index 8afcb0f..0000000
--- a/arch/m68k/dts/M54418TWR_nand_mii.dts
+++ /dev/null
@@ -1,34 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * Copyright (C) 2018 Angelo Dureghello <angelo@sysam.it>
- */
-
-/dts-v1/;
-/include/ "mcf5441x.dtsi"
-
-/ {
- model = "Freescale M54418TWR_nand_mii";
- compatible = "fsl,M54418TWR_nand_mii";
-
- chosen {
- stdout-path = "serial0:115200n8";
- };
-};
-
-&uart0 {
- u-boot,dm-pre-reloc;
- status = "okay";
-};
-
-&dspi0 {
- status = "okay";
-};
-
-&fec0 {
- status = "okay";
-};
-
-&fec1 {
- status = "okay";
- mii-base = <0>;
-};
diff --git a/arch/m68k/dts/M54418TWR_nand_rmii.dts b/arch/m68k/dts/M54418TWR_nand_rmii.dts
deleted file mode 100644
index fc2eb5b..0000000
--- a/arch/m68k/dts/M54418TWR_nand_rmii.dts
+++ /dev/null
@@ -1,34 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * Copyright (C) 2018 Angelo Dureghello <angelo@sysam.it>
- */
-
-/dts-v1/;
-/include/ "mcf5441x.dtsi"
-
-/ {
- model = "Freescale M54418TWR_nand_rmii";
- compatible = "fsl,M54418TWR_nand_rmii";
-
- chosen {
- stdout-path = "serial0:115200n8";
- };
-};
-
-&uart0 {
- u-boot,dm-pre-reloc;
- status = "okay";
-};
-
-&dspi0 {
- status = "okay";
-};
-
-&fec0 {
- status = "okay";
-};
-
-&fec1 {
- status = "okay";
- mii-base = <0>;
-};
diff --git a/arch/m68k/dts/M54418TWR_nand_rmii_lowfreq.dts b/arch/m68k/dts/M54418TWR_nand_rmii_lowfreq.dts
deleted file mode 100644
index a39d102..0000000
--- a/arch/m68k/dts/M54418TWR_nand_rmii_lowfreq.dts
+++ /dev/null
@@ -1,34 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * Copyright (C) 2018 Angelo Dureghello <angelo@sysam.it>
- */
-
-/dts-v1/;
-/include/ "mcf5441x.dtsi"
-
-/ {
- model = "Freescale M54418TWR_nand_rmii_lowfreq";
- compatible = "fsl,M54418TWR_nand_rmii_lowfreq";
-
- chosen {
- stdout-path = "serial0:115200n8";
- };
-};
-
-&uart0 {
- u-boot,dm-pre-reloc;
- status = "okay";
-};
-
-&dspi0 {
- status = "okay";
-};
-
-&fec0 {
- status = "okay";
-};
-
-&fec1 {
- status = "okay";
- mii-base = <0>;
-};
diff --git a/arch/m68k/dts/M54418TWR_serial_mii.dts b/arch/m68k/dts/M54418TWR_serial_mii.dts
deleted file mode 100644
index edf98db..0000000
--- a/arch/m68k/dts/M54418TWR_serial_mii.dts
+++ /dev/null
@@ -1,34 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * Copyright (C) 2018 Angelo Dureghello <angelo@sysam.it>
- */
-
-/dts-v1/;
-/include/ "mcf5441x.dtsi"
-
-/ {
- model = "Freescale M54418TWR_serial_mii";
- compatible = "fsl,M54418TWR_serial_mii";
-
- chosen {
- stdout-path = "serial0:115200n8";
- };
-};
-
-&uart0 {
- u-boot,dm-pre-reloc;
- status = "okay";
-};
-
-&dspi0 {
- status = "okay";
-};
-
-&fec0 {
- status = "okay";
-};
-
-&fec1 {
- status = "okay";
- mii-base = <0>;
-};
diff --git a/arch/m68k/dts/M54418TWR_serial_rmii.dts b/arch/m68k/dts/M54418TWR_serial_rmii.dts
deleted file mode 100644
index e4639fe..0000000
--- a/arch/m68k/dts/M54418TWR_serial_rmii.dts
+++ /dev/null
@@ -1,34 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * Copyright (C) 2018 Angelo Dureghello <angelo@sysam.it>
- */
-
-/dts-v1/;
-/include/ "mcf5441x.dtsi"
-
-/ {
- model = "Freescale M54418TWR_serial_rmii";
- compatible = "fsl,M54418TWR_serial_rmii";
-
- chosen {
- stdout-path = "serial0:115200n8";
- };
-};
-
-&uart0 {
- u-boot,dm-pre-reloc;
- status = "okay";
-};
-
-&dspi0 {
- status = "okay";
-};
-
-&fec0 {
- status = "okay";
-};
-
-&fec1 {
- status = "okay";
- mii-base = <0>;
-};
diff --git a/arch/m68k/dts/M54451EVB.dts b/arch/m68k/dts/M54451EVB.dts
deleted file mode 100644
index b81d37a..0000000
--- a/arch/m68k/dts/M54451EVB.dts
+++ /dev/null
@@ -1,33 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * Copyright (C) 2018 Angelo Dureghello <angelo@sysam.it>
- */
-
-/dts-v1/;
-/include/ "mcf5445x.dtsi"
-
-/ {
- model = "Freescale M54451EVB";
- compatible = "fsl,M54451EVB";
-
- chosen {
- stdout-path = "serial0:115200n8";
- };
-};
-
-&uart0 {
- u-boot,dm-pre-reloc;
- status = "okay";
-};
-
-&dspi0 {
- status = "okay";
-};
-
-&fec0 {
- status = "okay";
-};
-
-&fec1 {
- status = "okay";
-};
diff --git a/arch/m68k/dts/M54451EVB_stmicro.dts b/arch/m68k/dts/M54451EVB_stmicro.dts
deleted file mode 100644
index 6645b58..0000000
--- a/arch/m68k/dts/M54451EVB_stmicro.dts
+++ /dev/null
@@ -1,33 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * Copyright (C) 2018 Angelo Dureghello <angelo@sysam.it>
- */
-
-/dts-v1/;
-/include/ "mcf5445x.dtsi"
-
-/ {
- model = "Freescale M54451EVB_stmicro";
- compatible = "fsl,M54451EVB";
-
- chosen {
- stdout-path = "serial0:115200n8";
- };
-};
-
-&uart0 {
- u-boot,dm-pre-reloc;
- status = "okay";
-};
-
-&dspi0 {
- status = "okay";
-};
-
-&fec0 {
- status = "okay";
-};
-
-&fec1 {
- status = "okay";
-};
diff --git a/arch/m68k/dts/M54455EVB.dts b/arch/m68k/dts/M54455EVB.dts
deleted file mode 100644
index b0ffb51..0000000
--- a/arch/m68k/dts/M54455EVB.dts
+++ /dev/null
@@ -1,34 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * Copyright (C) 2018 Angelo Dureghello <angelo@sysam.it>
- */
-
-/dts-v1/;
-/include/ "mcf5445x.dtsi"
-
-/ {
- model = "Freescale M54455EVB";
- compatible = "fsl,M54455EVB";
-
- chosen {
- stdout-path = "serial0:115200n8";
- };
-};
-
-&uart0 {
- u-boot,dm-pre-reloc;
- status = "okay";
-};
-
-&dspi0 {
- status = "okay";
-};
-
-&fec0 {
- status = "okay";
-};
-
-&fec1 {
- status = "okay";
- mii-base = <0>;
-};
diff --git a/arch/m68k/dts/M54455EVB_a66.dts b/arch/m68k/dts/M54455EVB_a66.dts
deleted file mode 100644
index c2557bd..0000000
--- a/arch/m68k/dts/M54455EVB_a66.dts
+++ /dev/null
@@ -1,34 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * Copyright (C) 2018 Angelo Dureghello <angelo@sysam.it>
- */
-
-/dts-v1/;
-/include/ "mcf5445x.dtsi"
-
-/ {
- model = "Freescale M54455EVB_a66";
- compatible = "fsl,M54455EVB_a66";
-
- chosen {
- stdout-path = "serial0:115200n8";
- };
-};
-
-&uart0 {
- u-boot,dm-pre-reloc;
- status = "okay";
-};
-
-&dspi0 {
- status = "okay";
-};
-
-&fec0 {
- status = "okay";
-};
-
-&fec1 {
- status = "okay";
- mii-base = <0>;
-};
diff --git a/arch/m68k/dts/M54455EVB_i66.dts b/arch/m68k/dts/M54455EVB_i66.dts
deleted file mode 100644
index 3c9161b..0000000
--- a/arch/m68k/dts/M54455EVB_i66.dts
+++ /dev/null
@@ -1,34 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * Copyright (C) 2018 Angelo Dureghello <angelo@sysam.it>
- */
-
-/dts-v1/;
-/include/ "mcf5445x.dtsi"
-
-/ {
- model = "Freescale M54455EVB_i66";
- compatible = "fsl,M54455EVB_i66";
-
- chosen {
- stdout-path = "serial0:115200n8";
- };
-};
-
-&uart0 {
- u-boot,dm-pre-reloc;
- status = "okay";
-};
-
-&dspi0 {
- status = "okay";
-};
-
-&fec0 {
- status = "okay";
-};
-
-&fec1 {
- status = "okay";
- mii-base = <0>;
-};
diff --git a/arch/m68k/dts/M54455EVB_intel.dts b/arch/m68k/dts/M54455EVB_intel.dts
deleted file mode 100644
index 54209d2..0000000
--- a/arch/m68k/dts/M54455EVB_intel.dts
+++ /dev/null
@@ -1,34 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * Copyright (C) 2018 Angelo Dureghello <angelo@sysam.it>
- */
-
-/dts-v1/;
-/include/ "mcf5445x.dtsi"
-
-/ {
- model = "Freescale M54455EVB_intel";
- compatible = "fsl,M5275EVB_intel";
-
- chosen {
- stdout-path = "serial0:115200n8";
- };
-};
-
-&uart0 {
- u-boot,dm-pre-reloc;
- status = "okay";
-};
-
-&dspi0 {
- status = "okay";
-};
-
-&fec0 {
- status = "okay";
-};
-
-&fec1 {
- status = "okay";
- mii-base = <0>;
-};
diff --git a/arch/m68k/dts/M54455EVB_stm33.dts b/arch/m68k/dts/M54455EVB_stm33.dts
deleted file mode 100644
index 701b9a7..0000000
--- a/arch/m68k/dts/M54455EVB_stm33.dts
+++ /dev/null
@@ -1,34 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * Copyright (C) 2018 Angelo Dureghello <angelo@sysam.it>
- */
-
-/dts-v1/;
-/include/ "mcf5445x.dtsi"
-
-/ {
- model = "Freescale M54455EVB_stm33";
- compatible = "fsl,M5275EVB_stm33";
-
- chosen {
- stdout-path = "serial0:115200n8";
- };
-};
-
-&uart0 {
- u-boot,dm-pre-reloc;
- status = "okay";
-};
-
-&dspi0 {
- status = "okay";
-};
-
-&fec0 {
- status = "okay";
-};
-
-&fec1 {
- status = "okay";
- mii-base = <0>;
-};
diff --git a/arch/m68k/dts/Makefile b/arch/m68k/dts/Makefile
index 47260a1..fdd435b 100644
--- a/arch/m68k/dts/Makefile
+++ b/arch/m68k/dts/Makefile
@@ -1,7 +1,5 @@
# SPDX-License-Identifier: GPL-2.0+
-dtb-$(CONFIG_TARGET_M52277EVB) += M52277EVB.dtb \
- M52277EVB_stmicro.dtb
dtb-$(CONFIG_TARGET_M5235EVB) += M5235EVB.dtb \
M5235EVB_Flash32.dtb
dtb-$(CONFIG_TARGET_COBRA5272) += cobra5272.dtb
@@ -17,19 +15,6 @@
dtb-$(CONFIG_TARGET_M53017EVB) += M53017EVB.dtb
dtb-$(CONFIG_TARGET_M5329EVB) += M5329AFEE.dtb M5329BFEE.dtb
dtb-$(CONFIG_TARGET_M5373EVB) += M5373EVB.dtb
-dtb-$(CONFIG_TARGET_M54418TWR) += M54418TWR.dtb \
- M54418TWR_nand_mii.dtb \
- M54418TWR_nand_rmii.dtb \
- M54418TWR_serial_mii.dtb \
- M54418TWR_serial_rmii.dtb \
- M54418TWR_nand_rmii_lowfreq.dtb
-dtb-$(CONFIG_TARGET_M54451EVB) += M54451EVB.dtb \
- M54451EVB_stmicro.dtb
-dtb-$(CONFIG_TARGET_M54455EVB) += M54455EVB.dtb \
- M54455EVB_intel.dtb \
- M54455EVB_stm33.dtb \
- M54455EVB_a66.dtb \
- M54455EVB_i66.dtb
dtb-$(CONFIG_TARGET_AMCORE) += amcore.dtb
dtb-$(CONFIG_TARGET_STMARK2) += stmark2.dtb
diff --git a/arch/m68k/dts/mcf5227x.dtsi b/arch/m68k/dts/mcf5227x.dtsi
deleted file mode 100644
index 8c95edd..0000000
--- a/arch/m68k/dts/mcf5227x.dtsi
+++ /dev/null
@@ -1,48 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * Copyright (C) 2018 Angelo Dureghello <angelo@sysam.it>
- */
-
-/ {
- compatible = "fsl,mcf5227x";
-
- aliases {
- serial0 = &uart0;
- spi0 = &dspi0;
- };
-
- soc {
- compatible = "simple-bus";
- #address-cells = <1>;
- #size-cells = <1>;
-
- uart0: uart@fc060000 {
- compatible = "fsl,mcf-uart";
- reg = <0xfc060000 0x40>;
- status = "disabled";
- };
-
- uart1: uart@fc064000 {
- compatible = "fsl,mcf-uart";
- reg = <0xfc064000 0x40>;
- status = "disabled";
- };
-
- uart2: uart@fc068000 {
- compatible = "fsl,mcf-uart";
- reg = <0xfc068000 0x40>;
- status = "disabled";
- };
-
- dspi0: dspi@fc05c000 {
- compatible = "fsl,mcf-dspi";
- #address-cells = <1>;
- #size-cells = <0>;
- reg = <0xfc05c000 0x100>;
- spi-max-frequency = <50000000>;
- num-cs = <4>;
- spi-mode = <0>;
- status = "disabled";
- };
- };
-};
diff --git a/arch/m68k/dts/mcf5445x.dtsi b/arch/m68k/dts/mcf5445x.dtsi
deleted file mode 100644
index b7ecc99..0000000
--- a/arch/m68k/dts/mcf5445x.dtsi
+++ /dev/null
@@ -1,68 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * Copyright (C) 2018 Angelo Dureghello <angelo@sysam.it>
- */
-
-/ {
- compatible = "fsl,mcf5445x";
-
- aliases {
- serial0 = &uart0;
- spi0 = &dspi0;
- fec0 = &fec0;
- fec1 = &fec1;
- };
-
- soc {
- compatible = "simple-bus";
- #address-cells = <1>;
- #size-cells = <1>;
-
- uart0: uart@fc060000 {
- compatible = "fsl,mcf-uart";
- reg = <0xfc060000 0x40>;
- status = "disabled";
- };
-
- uart1: uart@fc064000 {
- compatible = "fsl,mcf-uart";
- reg = <0xfc064000 0x40>;
- status = "disabled";
- };
-
- uart2: uart@fc068000 {
- compatible = "fsl,mcf-uart";
- reg = <0xfc068000 0x40>;
- status = "disabled";
- };
-
- dspi0: dspi@fc05c000 {
- compatible = "fsl,mcf-dspi";
- #address-cells = <1>;
- #size-cells = <0>;
- reg = <0xfc05c000 0x100>;
- spi-max-frequency = <50000000>;
- num-cs = <4>;
- spi-mode = <0>;
- status = "disabled";
- };
-
- fec0: ethernet@fc030000 {
- compatible = "fsl,mcf-fec";
- reg = <0xfc030000 0x4000>;
- mii-base = <0>;
- max-speed = <100>;
- timeout-loop = <50000>;
- status = "disabled";
- };
-
- fec1: ethernet@fc034000 {
- compatible = "fsl,mcf-fec";
- reg = <0xfc034000 0x4000>;
- mii-base = <1>;
- max-speed = <100>;
- timeout-loop = <50000>;
- status = "disabled";
- };
- };
-};
diff --git a/arch/m68k/include/asm/cache.h b/arch/m68k/include/asm/cache.h
index fabec0a..ceb462f 100644
--- a/arch/m68k/include/asm/cache.h
+++ b/arch/m68k/include/asm/cache.h
@@ -10,7 +10,7 @@
#define __CACHE_H
#if defined(CONFIG_MCF520x) || defined(CONFIG_MCF523x) || \
- defined(CONFIG_MCF52x2) || defined(CONFIG_MCF5227x)
+ defined(CONFIG_MCF52x2)
#define CONFIG_CF_V2
#endif
@@ -19,9 +19,7 @@
#define CONFIG_CF_V3
#endif
-#if defined(CONFIG_MCF5445x)
-#define CONFIG_CF_V4
-#elif defined(CONFIG_MCF5441x)
+#if defined(CONFIG_MCF5441x)
#define CONFIG_CF_V4E /* Four Extra ACRn */
#endif
diff --git a/arch/m68k/include/asm/immap.h b/arch/m68k/include/asm/immap.h
index cabdb0f..02aa95a 100644
--- a/arch/m68k/include/asm/immap.h
+++ b/arch/m68k/include/asm/immap.h
@@ -32,34 +32,6 @@
#define CONFIG_SYS_NUM_IRQS (128)
#endif /* CONFIG_M520x */
-#ifdef CONFIG_M52277
-#include <asm/immap_5227x.h>
-#include <asm/m5227x.h>
-
-#define CONFIG_SYS_UART_BASE (MMAP_UART0 + (CONFIG_SYS_UART_PORT * 0x4000))
-
-#define CONFIG_SYS_MCFRTC_BASE (MMAP_RTC)
-
-#ifdef CONFIG_LCD
-#define CONFIG_SYS_LCD_BASE (MMAP_LCD)
-#endif
-
-/* Timer */
-#ifdef CONFIG_MCFTMR
-#define CONFIG_SYS_UDELAY_BASE (MMAP_DTMR0)
-#define CONFIG_SYS_TMR_BASE (MMAP_DTMR1)
-#define CONFIG_SYS_TMRPND_REG (((volatile int0_t *)(CONFIG_SYS_INTR_BASE))->iprh0)
-#define CONFIG_SYS_TMRINTR_NO (INT0_HI_DTMR1)
-#define CONFIG_SYS_TMRINTR_MASK (INTC_IPRH_INT33)
-#define CONFIG_SYS_TMRINTR_PEND (CONFIG_SYS_TMRINTR_MASK)
-#define CONFIG_SYS_TMRINTR_PRI (6)
-#define CONFIG_SYS_TIMER_PRESCALER (((gd->bus_clk / 1000000) - 1) << 8)
-#endif
-
-#define CONFIG_SYS_INTR_BASE (MMAP_INTC0)
-#define CONFIG_SYS_NUM_IRQS (128)
-#endif /* CONFIG_M52277 */
-
#ifdef CONFIG_M5235
#include <asm/immap_5235.h>
#include <asm/m5235.h>
@@ -330,42 +302,6 @@
#endif /* CONFIG_M54418 */
-#if defined(CONFIG_M54451) || defined(CONFIG_M54455)
-#include <asm/immap_5445x.h>
-#include <asm/m5445x.h>
-
-#define CONFIG_SYS_FEC0_IOBASE (MMAP_FEC0)
-#if defined(CONFIG_M54455EVB)
-#define CONFIG_SYS_FEC1_IOBASE (MMAP_FEC1)
-#endif
-
-#define CONFIG_SYS_UART_BASE (MMAP_UART0 + (CONFIG_SYS_UART_PORT * 0x4000))
-
-#define CONFIG_SYS_MCFRTC_BASE (MMAP_RTC)
-
-/* Timer */
-#ifdef CONFIG_MCFTMR
-#define CONFIG_SYS_UDELAY_BASE (MMAP_DTMR0)
-#define CONFIG_SYS_TMR_BASE (MMAP_DTMR1)
-#define CONFIG_SYS_TMRPND_REG (((volatile int0_t *)(CONFIG_SYS_INTR_BASE))->iprh0)
-#define CONFIG_SYS_TMRINTR_NO (INT0_HI_DTMR1)
-#define CONFIG_SYS_TMRINTR_MASK (INTC_IPRH_INT33)
-#define CONFIG_SYS_TMRINTR_PEND (CONFIG_SYS_TMRINTR_MASK)
-#define CONFIG_SYS_TMRINTR_PRI (6)
-#define CONFIG_SYS_TIMER_PRESCALER (((gd->bus_clk / 1000000) - 1) << 8)
-#endif
-
-#define CONFIG_SYS_INTR_BASE (MMAP_INTC0)
-#define CONFIG_SYS_NUM_IRQS (128)
-
-#ifdef CONFIG_PCI
-#define CONFIG_SYS_PCI_BAR0 (CONFIG_SYS_MBAR)
-#define CONFIG_SYS_PCI_BAR5 (CONFIG_SYS_SDRAM_BASE)
-#define CONFIG_SYS_PCI_TBATR0 (CONFIG_SYS_MBAR)
-#define CONFIG_SYS_PCI_TBATR5 (CONFIG_SYS_SDRAM_BASE)
-#endif
-#endif /* CONFIG_M54451 || CONFIG_M54455 */
-
#ifdef CONFIG_M547x
#include <asm/immap_547x_8x.h>
#include <asm/m547x_8x.h>
diff --git a/arch/m68k/include/asm/immap_5227x.h b/arch/m68k/include/asm/immap_5227x.h
deleted file mode 100644
index 710d6f5..0000000
--- a/arch/m68k/include/asm/immap_5227x.h
+++ /dev/null
@@ -1,237 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0+ */
-/*
- * MCF5227x Internal Memory Map
- *
- * Copyright (C) 2004-2007 Freescale Semiconductor, Inc.
- * TsiChung Liew (Tsi-Chung.Liew@freescale.com)
- */
-
-#ifndef __IMMAP_5227X__
-#define __IMMAP_5227X__
-
-/* Module Base Addresses */
-#define MMAP_SCM1 (CONFIG_SYS_MBAR + 0x00000000)
-#define MMAP_XBS (CONFIG_SYS_MBAR + 0x00004000)
-#define MMAP_FBCS (CONFIG_SYS_MBAR + 0x00008000)
-#define MMAP_CAN (CONFIG_SYS_MBAR + 0x00020000)
-#define MMAP_RTC (CONFIG_SYS_MBAR + 0x0003C000)
-#define MMAP_SCM2 (CONFIG_SYS_MBAR + 0x00040010)
-#define MMAP_SCM3 (CONFIG_SYS_MBAR + 0x00040070)
-#define MMAP_EDMA (CONFIG_SYS_MBAR + 0x00044000)
-#define MMAP_INTC0 (CONFIG_SYS_MBAR + 0x00048000)
-#define MMAP_INTC1 (CONFIG_SYS_MBAR + 0x0004C000)
-#define MMAP_IACK (CONFIG_SYS_MBAR + 0x00054000)
-#define MMAP_I2C (CONFIG_SYS_MBAR + 0x00058000)
-#define MMAP_DSPI (CONFIG_SYS_MBAR + 0x0005C000)
-#define MMAP_UART0 (CONFIG_SYS_MBAR + 0x00060000)
-#define MMAP_UART1 (CONFIG_SYS_MBAR + 0x00064000)
-#define MMAP_UART2 (CONFIG_SYS_MBAR + 0x00068000)
-#define MMAP_DTMR0 (CONFIG_SYS_MBAR + 0x00070000)
-#define MMAP_DTMR1 (CONFIG_SYS_MBAR + 0x00074000)
-#define MMAP_DTMR2 (CONFIG_SYS_MBAR + 0x00078000)
-#define MMAP_DTMR3 (CONFIG_SYS_MBAR + 0x0007C000)
-#define MMAP_PIT0 (CONFIG_SYS_MBAR + 0x00080000)
-#define MMAP_PIT1 (CONFIG_SYS_MBAR + 0x00084000)
-#define MMAP_PWM (CONFIG_SYS_MBAR + 0x00090000)
-#define MMAP_EPORT (CONFIG_SYS_MBAR + 0x00094000)
-#define MMAP_RCM (CONFIG_SYS_MBAR + 0x000A0000)
-#define MMAP_CCM (CONFIG_SYS_MBAR + 0x000A0004)
-#define MMAP_GPIO (CONFIG_SYS_MBAR + 0x000A4000)
-#define MMAP_ADC (CONFIG_SYS_MBAR + 0x000A8000)
-#define MMAP_LCD (CONFIG_SYS_MBAR + 0x000AC000)
-#define MMAP_LCD_BGLUT (CONFIG_SYS_MBAR + 0x000AC800)
-#define MMAP_LCD_GWLUT (CONFIG_SYS_MBAR + 0x000ACC00)
-#define MMAP_USBHW (CONFIG_SYS_MBAR + 0x000B0000)
-#define MMAP_USBCAPS (CONFIG_SYS_MBAR + 0x000B0100)
-#define MMAP_USBEHCI (CONFIG_SYS_MBAR + 0x000B0140)
-#define MMAP_USBOTG (CONFIG_SYS_MBAR + 0x000B01A0)
-#define MMAP_SDRAM (CONFIG_SYS_MBAR + 0x000B8000)
-#define MMAP_SSI (CONFIG_SYS_MBAR + 0x000BC000)
-#define MMAP_PLL (CONFIG_SYS_MBAR + 0x000C0000)
-
-#include <asm/coldfire/crossbar.h>
-#include <asm/coldfire/dspi.h>
-#include <asm/coldfire/edma.h>
-#include <asm/coldfire/eport.h>
-#include <asm/coldfire/flexbus.h>
-#include <asm/coldfire/flexcan.h>
-#include <asm/coldfire/intctrl.h>
-#include <asm/coldfire/lcd.h>
-#include <asm/coldfire/pwm.h>
-#include <asm/coldfire/ssi.h>
-
-/* Reset Controller Module (RCM) */
-typedef struct rcm {
- u8 rcr;
- u8 rsr;
-} rcm_t;
-
-/* Chip Configuration Module (CCM) */
-typedef struct ccm {
- u16 ccr; /* Chip Configuration (Rd-only) */
- u16 resv1;
- u16 rcon; /* Reset Configuration (Rd-only) */
- u16 cir; /* Chip Identification (Rd-only) */
- u32 resv2;
- u16 misccr; /* Miscellaneous Control */
- u16 cdr; /* Clock Divider */
- u16 uocsr; /* USB On-the-Go Controller Status */
- u16 resv4;
- u16 sbfsr; /* Serial Boot Status */
- u16 sbfcr; /* Serial Boot Control */
-} ccm_t;
-
-typedef struct canex_ctrl {
- can_msg_t msg[16]; /* 0x00 Message Buffer 0-15 */
- u32 res0[0x700]; /* 0x100 */
- can_msg_t rxim[16]; /* 0x800 Rx Individual Mask 0-15 */
-} canex_t;
-
-/* General Purpose I/O Module (GPIO) */
-typedef struct gpio {
- /* Port Output Data Registers */
- u8 podr_be; /* 0x00 */
- u8 podr_cs; /* 0x01 */
- u8 podr_fbctl; /* 0x02 */
- u8 podr_i2c; /* 0x03 */
- u8 rsvd1; /* 0x04 */
- u8 podr_uart; /* 0x05 */
- u8 podr_dspi; /* 0x06 */
- u8 podr_timer; /* 0x07 */
- u8 podr_lcdctl; /* 0x08 */
- u8 podr_lcddatah; /* 0x09 */
- u8 podr_lcddatam; /* 0x0A */
- u8 podr_lcddatal; /* 0x0B */
-
- /* Port Data Direction Registers */
- u8 pddr_be; /* 0x0C */
- u8 pddr_cs; /* 0x0D */
- u8 pddr_fbctl; /* 0x0E */
- u8 pddr_i2c; /* 0x0F */
- u8 rsvd2; /* 0x10 */
- u8 pddr_uart; /* 0x11 */
- u8 pddr_dspi; /* 0x12 */
- u8 pddr_timer; /* 0x13 */
- u8 pddr_lcdctl; /* 0x14 */
- u8 pddr_lcddatah; /* 0x15 */
- u8 pddr_lcddatam; /* 0x16 */
- u8 pddr_lcddatal; /* 0x17 */
-
- /* Port Pin Data/Set Data Registers */
- u8 ppdsdr_be; /* 0x18 */
- u8 ppdsdr_cs; /* 0x19 */
- u8 ppdsdr_fbctl; /* 0x1A */
- u8 ppdsdr_i2c; /* 0x1B */
- u8 rsvd3; /* 0x1C */
- u8 ppdsdr_uart; /* 0x1D */
- u8 ppdsdr_dspi; /* 0x1E */
- u8 ppdsdr_timer; /* 0x1F */
- u8 ppdsdr_lcdctl; /* 0x20 */
- u8 ppdsdr_lcddatah; /* 0x21 */
- u8 ppdsdr_lcddatam; /* 0x22 */
- u8 ppdsdr_lcddatal; /* 0x23 */
-
- /* Port Clear Output Data Registers */
- u8 pclrr_be; /* 0x24 */
- u8 pclrr_cs; /* 0x25 */
- u8 pclrr_fbctl; /* 0x26 */
- u8 pclrr_i2c; /* 0x27 */
- u8 rsvd4; /* 0x28 */
- u8 pclrr_uart; /* 0x29 */
- u8 pclrr_dspi; /* 0x2A */
- u8 pclrr_timer; /* 0x2B */
- u8 pclrr_lcdctl; /* 0x2C */
- u8 pclrr_lcddatah; /* 0x2D */
- u8 pclrr_lcddatam; /* 0x2E */
- u8 pclrr_lcddatal; /* 0x2F */
-
- /* Pin Assignment Registers */
- u8 par_be; /* 0x30 */
- u8 par_cs; /* 0x31 */
- u8 par_fbctl; /* 0x32 */
- u8 par_i2c; /* 0x33 */
- u16 par_uart; /* 0x34 */
- u8 par_dspi; /* 0x36 */
- u8 par_timer; /* 0x37 */
- u8 par_lcdctl; /* 0x38 */
- u8 par_irq; /* 0x39 */
- u16 rsvd6; /* 0x3A - 0x3B */
- u32 par_lcdh; /* 0x3C */
- u32 par_lcdl; /* 0x40 */
-
- /* Mode select control registers */
- u8 mscr_fb; /* 0x44 */
- u8 mscr_sdram; /* 0x45 */
-
- u16 rsvd7; /* 0x46 - 0x47 */
- u8 dscr_dspi; /* 0x48 */
- u8 dscr_timer; /* 0x49 */
- u8 dscr_i2c; /* 0x4A */
- u8 dscr_lcd; /* 0x4B */
- u8 dscr_debug; /* 0x4C */
- u8 dscr_clkrst; /* 0x4D */
- u8 dscr_irq; /* 0x4E */
- u8 dscr_uart; /* 0x4F */
-} gpio_t;
-
-/* SDRAM Controller (SDRAMC) */
-typedef struct sdramc {
- u32 sdmr; /* Mode/Extended Mode */
- u32 sdcr; /* Control */
- u32 sdcfg1; /* Configuration 1 */
- u32 sdcfg2; /* Chip Select */
- u8 resv0[0x100];
- u32 sdcs0; /* Mode/Extended Mode */
- u32 sdcs1; /* Mode/Extended Mode */
-} sdramc_t;
-
-/* Phase Locked Loop (PLL) */
-typedef struct pll {
- u32 pcr; /* PLL Control */
- u32 psr; /* PLL Status */
-} pll_t;
-
-/* System Control Module register */
-typedef struct scm1 {
- u32 mpr; /* 0x00 Master Privilege */
- u32 rsvd1[7];
- u32 pacra; /* 0x20 */
- u32 pacrb; /* 0x24 */
- u32 pacrc; /* 0x28 */
- u32 pacrd; /* 0x2C */
- u32 rsvd2[4];
- u32 pacre; /* 0x40 */
- u32 pacrf; /* 0x44 */
- u32 pacrg; /* 0x48 */
- u32 rsvd3;
- u32 pacri; /* 0x50 */
-} scm1_t;
-
-typedef struct scm2_ctrl {
- u8 res1[3]; /* 0x00 - 0x02 */
- u8 wcr; /* 0x03 wakeup control */
- u16 res2; /* 0x04 - 0x05 */
- u16 cwcr; /* 0x06 Core Watchdog Control */
- u8 res3[3]; /* 0x08 - 0x0A */
- u8 cwsr; /* 0x0B Core Watchdog Service */
- u8 res4[2]; /* 0x0C - 0x0D */
- u8 scmisr; /* 0x0F Interrupt Status */
- u32 res5; /* 0x20 */
- u32 bcr; /* 0x24 Burst Configuration */
-} scm2_t;
-
-typedef struct scm3_ctrl {
- u32 cfadr; /* 0x00 Core Fault Address */
- u8 res7; /* 0x04 */
- u8 cfier; /* 0x05 Core Fault Interrupt Enable */
- u8 cfloc; /* 0x06 Core Fault Location */
- u8 cfatr; /* 0x07 Core Fault Attributes */
- u32 cfdtr; /* 0x08 Core Fault Data */
-} scm3_t;
-
-typedef struct rtcex {
- u32 rsvd1[3];
- u32 gocu;
- u32 gocl;
-} rtcex_t;
-#endif /* __IMMAP_5227X__ */
diff --git a/arch/m68k/include/asm/immap_5445x.h b/arch/m68k/include/asm/immap_5445x.h
deleted file mode 100644
index 3111d00..0000000
--- a/arch/m68k/include/asm/immap_5445x.h
+++ /dev/null
@@ -1,335 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0+ */
-/*
- * MCF5445x Internal Memory Map
- *
- * Copyright (C) 2004-2007 Freescale Semiconductor, Inc.
- * TsiChung Liew (Tsi-Chung.Liew@freescale.com)
- */
-
-#ifndef __IMMAP_5445X__
-#define __IMMAP_5445X__
-
-/* Module Base Addresses */
-#define MMAP_SCM1 0xFC000000
-#define MMAP_XBS 0xFC004000
-#define MMAP_FBCS 0xFC008000
-#define MMAP_FEC0 0xFC030000
-#define MMAP_FEC1 0xFC034000
-#define MMAP_RTC 0xFC03C000
-#define MMAP_SCM2 0xFC040000
-#define MMAP_EDMA 0xFC044000
-#define MMAP_INTC0 0xFC048000
-#define MMAP_INTC1 0xFC04C000
-#define MMAP_IACK 0xFC054000
-#define MMAP_I2C 0xFC058000
-#define MMAP_DSPI 0xFC05C000
-#define MMAP_UART0 0xFC060000
-#define MMAP_UART1 0xFC064000
-#define MMAP_UART2 0xFC068000
-#define MMAP_DTMR0 0xFC070000
-#define MMAP_DTMR1 0xFC074000
-#define MMAP_DTMR2 0xFC078000
-#define MMAP_DTMR3 0xFC07C000
-#define MMAP_PIT0 0xFC080000
-#define MMAP_PIT1 0xFC084000
-#define MMAP_PIT2 0xFC088000
-#define MMAP_PIT3 0xFC08C000
-#define MMAP_EPORT 0xFC094000
-#define MMAP_WTM 0xFC098000
-#define MMAP_SBF 0xFC0A0000
-#define MMAP_RCM 0xFC0A0000
-#define MMAP_CCM 0xFC0A0000
-#define MMAP_GPIO 0xFC0A4000
-#define MMAP_PCI 0xFC0A8000
-#define MMAP_PCIARB 0xFC0AC000
-#define MMAP_RNG 0xFC0B4000
-#define MMAP_SDRAM 0xFC0B8000
-#define MMAP_SSI 0xFC0BC000
-#define MMAP_PLL 0xFC0C4000
-#define MMAP_ATA 0x90000000
-#define MMAP_USBHW 0xFC0B0000
-#define MMAP_USBCAPS 0xFC0B0100
-#define MMAP_USBEHCI 0xFC0B0140
-#define MMAP_USBOTG 0xFC0B01A0
-
-#include <asm/coldfire/ata.h>
-#include <asm/coldfire/crossbar.h>
-#include <asm/coldfire/dspi.h>
-#include <asm/coldfire/edma.h>
-#include <asm/coldfire/eport.h>
-#include <asm/coldfire/flexbus.h>
-#include <asm/coldfire/intctrl.h>
-#include <asm/coldfire/ssi.h>
-
-/* Watchdog Timer Modules (WTM) */
-typedef struct wtm {
- u16 wcr;
- u16 wmr;
- u16 wcntr;
- u16 wsr;
-} wtm_t;
-
-/* Serial Boot Facility (SBF) */
-typedef struct sbf {
- u8 resv0[0x18];
- u16 sbfsr; /* Serial Boot Facility Status Register */
- u8 resv1[0x6];
- u16 sbfcr; /* Serial Boot Facility Control Register */
-} sbf_t;
-
-/* Reset Controller Module (RCM) */
-typedef struct rcm {
- u8 rcr;
- u8 rsr;
-} rcm_t;
-
-/* Chip Configuration Module (CCM) */
-typedef struct ccm {
- u8 ccm_resv0[0x4];
- u16 ccr; /* Chip Configuration Register (256 TEPBGA, Read-only) */
- u8 resv1[0x2];
- u16 rcon; /* Reset Configuration (256 TEPBGA, Read-only) */
- u16 cir; /* Chip Identification Register (Read-only) */
- u8 resv2[0x4];
- u16 misccr; /* Miscellaneous Control Register */
- u16 cdr; /* Clock Divider Register */
- u16 uocsr; /* USB On-the-Go Controller Status Register */
-} ccm_t;
-
-/* General Purpose I/O Module (GPIO) */
-typedef struct gpio {
- u8 podr_fec0h; /* FEC0 High Port Output Data Register */
- u8 podr_fec0l; /* FEC0 Low Port Output Data Register */
- u8 podr_ssi; /* SSI Port Output Data Register */
- u8 podr_fbctl; /* Flexbus Control Port Output Data Register */
- u8 podr_be; /* Flexbus Byte Enable Port Output Data Register */
- u8 podr_cs; /* Flexbus Chip-Select Port Output Data Register */
- u8 podr_dma; /* DMA Port Output Data Register */
- u8 podr_feci2c; /* FEC1 / I2C Port Output Data Register */
- u8 resv0[0x1];
- u8 podr_uart; /* UART Port Output Data Register */
- u8 podr_dspi; /* DSPI Port Output Data Register */
- u8 podr_timer; /* Timer Port Output Data Register */
- u8 podr_pci; /* PCI Port Output Data Register */
- u8 podr_usb; /* USB Port Output Data Register */
- u8 podr_atah; /* ATA High Port Output Data Register */
- u8 podr_atal; /* ATA Low Port Output Data Register */
- u8 podr_fec1h; /* FEC1 High Port Output Data Register */
- u8 podr_fec1l; /* FEC1 Low Port Output Data Register */
- u8 resv1[0x2];
- u8 podr_fbadh; /* Flexbus AD High Port Output Data Register */
- u8 podr_fbadmh; /* Flexbus AD Med-High Port Output Data Register */
- u8 podr_fbadml; /* Flexbus AD Med-Low Port Output Data Register */
- u8 podr_fbadl; /* Flexbus AD Low Port Output Data Register */
- u8 pddr_fec0h; /* FEC0 High Port Data Direction Register */
- u8 pddr_fec0l; /* FEC0 Low Port Data Direction Register */
- u8 pddr_ssi; /* SSI Port Data Direction Register */
- u8 pddr_fbctl; /* Flexbus Control Port Data Direction Register */
- u8 pddr_be; /* Flexbus Byte Enable Port Data Direction Register */
- u8 pddr_cs; /* Flexbus Chip-Select Port Data Direction Register */
- u8 pddr_dma; /* DMA Port Data Direction Register */
- u8 pddr_feci2c; /* FEC1 / I2C Port Data Direction Register */
- u8 resv2[0x1];
- u8 pddr_uart; /* UART Port Data Direction Register */
- u8 pddr_dspi; /* DSPI Port Data Direction Register */
- u8 pddr_timer; /* Timer Port Data Direction Register */
- u8 pddr_pci; /* PCI Port Data Direction Register */
- u8 pddr_usb; /* USB Port Data Direction Register */
- u8 pddr_atah; /* ATA High Port Data Direction Register */
- u8 pddr_atal; /* ATA Low Port Data Direction Register */
- u8 pddr_fec1h; /* FEC1 High Port Data Direction Register */
- u8 pddr_fec1l; /* FEC1 Low Port Data Direction Register */
- u8 resv3[0x2];
- u8 pddr_fbadh; /* Flexbus AD High Port Data Direction Register */
- u8 pddr_fbadmh; /* Flexbus AD Med-High Port Data Direction Register */
- u8 pddr_fbadml; /* Flexbus AD Med-Low Port Data Direction Register */
- u8 pddr_fbadl; /* Flexbus AD Low Port Data Direction Register */
- u8 ppdsdr_fec0h; /* FEC0 High Port Pin Data/Set Data Register */
- u8 ppdsdr_fec0l; /* FEC0 Low Port Clear Output Data Register */
- u8 ppdsdr_ssi; /* SSI Port Pin Data/Set Data Register */
- u8 ppdsdr_fbctl; /* Flexbus Control Port Pin Data/Set Data Register */
- u8 ppdsdr_be; /* Flexbus Byte Enable Port Pin Data/Set Data Register */
- u8 ppdsdr_cs; /* Flexbus Chip-Select Port Pin Data/Set Data Register */
- u8 ppdsdr_dma; /* DMA Port Pin Data/Set Data Register */
- u8 ppdsdr_feci2c; /* FEC1 / I2C Port Pin Data/Set Data Register */
- u8 resv4[0x1];
- u8 ppdsdr_uart; /* UART Port Pin Data/Set Data Register */
- u8 ppdsdr_dspi; /* DSPI Port Pin Data/Set Data Register */
- u8 ppdsdr_timer; /* FTimer Port Pin Data/Set Data Register */
- u8 ppdsdr_pci; /* PCI Port Pin Data/Set Data Register */
- u8 ppdsdr_usb; /* USB Port Pin Data/Set Data Register */
- u8 ppdsdr_atah; /* ATA High Port Pin Data/Set Data Register */
- u8 ppdsdr_atal; /* ATA Low Port Pin Data/Set Data Register */
- u8 ppdsdr_fec1h; /* FEC1 High Port Pin Data/Set Data Register */
- u8 ppdsdr_fec1l; /* FEC1 Low Port Pin Data/Set Data Register */
- u8 resv5[0x2];
- u8 ppdsdr_fbadh; /* Flexbus AD High Port Pin Data/Set Data Register */
- u8 ppdsdr_fbadmh; /* Flexbus AD Med-High Port Pin Data/Set Data Register */
- u8 ppdsdr_fbadml; /* Flexbus AD Med-Low Port Pin Data/Set Data Register */
- u8 ppdsdr_fbadl; /* Flexbus AD Low Port Pin Data/Set Data Register */
- u8 pclrr_fec0h; /* FEC0 High Port Clear Output Data Register */
- u8 pclrr_fec0l; /* FEC0 Low Port Pin Data/Set Data Register */
- u8 pclrr_ssi; /* SSI Port Clear Output Data Register */
- u8 pclrr_fbctl; /* Flexbus Control Port Clear Output Data Register */
- u8 pclrr_be; /* Flexbus Byte Enable Port Clear Output Data Register */
- u8 pclrr_cs; /* Flexbus Chip-Select Port Clear Output Data Register */
- u8 pclrr_dma; /* DMA Port Clear Output Data Register */
- u8 pclrr_feci2c; /* FEC1 / I2C Port Clear Output Data Register */
- u8 resv6[0x1];
- u8 pclrr_uart; /* UART Port Clear Output Data Register */
- u8 pclrr_dspi; /* DSPI Port Clear Output Data Register */
- u8 pclrr_timer; /* Timer Port Clear Output Data Register */
- u8 pclrr_pci; /* PCI Port Clear Output Data Register */
- u8 pclrr_usb; /* USB Port Clear Output Data Register */
- u8 pclrr_atah; /* ATA High Port Clear Output Data Register */
- u8 pclrr_atal; /* ATA Low Port Clear Output Data Register */
- u8 pclrr_fec1h; /* FEC1 High Port Clear Output Data Register */
- u8 pclrr_fec1l; /* FEC1 Low Port Clear Output Data Register */
- u8 resv7[0x2];
- u8 pclrr_fbadh; /* Flexbus AD High Port Clear Output Data Register */
- u8 pclrr_fbadmh; /* Flexbus AD Med-High Port Clear Output Data Register */
- u8 pclrr_fbadml; /* Flexbus AD Med-Low Port Clear Output Data Register */
- u8 pclrr_fbadl; /* Flexbus AD Low Port Clear Output Data Register */
- u8 par_fec; /* FEC Pin Assignment Register */
- u8 par_dma; /* DMA Pin Assignment Register */
- u8 par_fbctl; /* Flexbus Control Pin Assignment Register */
- u8 par_dspi; /* DSPI Pin Assignment Register */
- u8 par_be; /* Flexbus Byte-Enable Pin Assignment Register */
- u8 par_cs; /* Flexbus Chip-Select Pin Assignment Register */
- u8 par_timer; /* Time Pin Assignment Register */
- u8 par_usb; /* USB Pin Assignment Register */
- u8 resv8[0x1];
- u8 par_uart; /* UART Pin Assignment Register */
- u16 par_feci2c; /* FEC / I2C Pin Assignment Register */
- u16 par_ssi; /* SSI Pin Assignment Register */
- u16 par_ata; /* ATA Pin Assignment Register */
- u8 par_irq; /* IRQ Pin Assignment Register */
- u8 resv9[0x1];
- u16 par_pci; /* PCI Pin Assignment Register */
- u8 mscr_sdram; /* SDRAM Mode Select Control Register */
- u8 mscr_pci; /* PCI Mode Select Control Register */
- u8 resv10[0x2];
- u8 dscr_i2c; /* I2C Drive Strength Control Register */
- u8 dscr_flexbus; /* FLEXBUS Drive Strength Control Register */
- u8 dscr_fec; /* FEC Drive Strength Control Register */
- u8 dscr_uart; /* UART Drive Strength Control Register */
- u8 dscr_dspi; /* DSPI Drive Strength Control Register */
- u8 dscr_timer; /* TIMER Drive Strength Control Register */
- u8 dscr_ssi; /* SSI Drive Strength Control Register */
- u8 dscr_dma; /* DMA Drive Strength Control Register */
- u8 dscr_debug; /* DEBUG Drive Strength Control Register */
- u8 dscr_reset; /* RESET Drive Strength Control Register */
- u8 dscr_irq; /* IRQ Drive Strength Control Register */
- u8 dscr_usb; /* USB Drive Strength Control Register */
- u8 dscr_ata; /* ATA Drive Strength Control Register */
-} gpio_t;
-
-/* SDRAM Controller (SDRAMC) */
-typedef struct sdramc {
- u32 sdmr; /* SDRAM Mode/Extended Mode Register */
- u32 sdcr; /* SDRAM Control Register */
- u32 sdcfg1; /* SDRAM Configuration Register 1 */
- u32 sdcfg2; /* SDRAM Chip Select Register */
- u8 resv0[0x100];
- u32 sdcs0; /* SDRAM Mode/Extended Mode Register */
- u32 sdcs1; /* SDRAM Mode/Extended Mode Register */
-} sdramc_t;
-
-/* Phase Locked Loop (PLL) */
-typedef struct pll {
- u32 pcr; /* PLL Control Register */
- u32 psr; /* PLL Status Register */
-} pll_t;
-
-typedef struct pci {
- u32 idr; /* 0x00 Device Id / Vendor Id Register */
- u32 scr; /* 0x04 Status / command Register */
- u32 ccrir; /* 0x08 Class Code / Revision Id Register */
- u32 cr1; /* 0x0c Configuration 1 Register */
- u32 bar0; /* 0x10 Base address register 0 Register */
- u32 bar1; /* 0x14 Base address register 1 Register */
- u32 bar2; /* 0x18 Base address register 2 Register */
- u32 bar3; /* 0x1c Base address register 3 Register */
- u32 bar4; /* 0x20 Base address register 4 Register */
- u32 bar5; /* 0x24 Base address register 5 Register */
- u32 ccpr; /* 0x28 Cardbus CIS Pointer Register */
- u32 sid; /* 0x2c Subsystem ID / Subsystem Vendor ID Register */
- u32 erbar; /* 0x30 Expansion ROM Base Address Register */
- u32 cpr; /* 0x34 Capabilities Pointer Register */
- u32 rsvd1; /* 0x38 */
- u32 cr2; /* 0x3c Configuration Register 2 */
- u32 rsvd2[8]; /* 0x40 - 0x5f */
-
- /* General control / status registers */
- u32 gscr; /* 0x60 Global Status / Control Register */
- u32 tbatr0a; /* 0x64 Target Base Address Translation Register 0 */
- u32 tbatr1a; /* 0x68 Target Base Address Translation Register 1 */
- u32 tcr1; /* 0x6c Target Control 1 Register */
- u32 iw0btar; /* 0x70 Initiator Window 0 Base/Translation addr */
- u32 iw1btar; /* 0x74 Initiator Window 1 Base/Translation addr */
- u32 iw2btar; /* 0x78 Initiator Window 2 Base/Translation addr */
- u32 rsvd3; /* 0x7c */
- u32 iwcr; /* 0x80 Initiator Window Configuration Register */
- u32 icr; /* 0x84 Initiator Control Register */
- u32 isr; /* 0x88 Initiator Status Register */
- u32 tcr2; /* 0x8c Target Control 2 Register */
- u32 tbatr0; /* 0x90 Target Base Address Translation Register 0 */
- u32 tbatr1; /* 0x94 Target Base Address Translation Register 1 */
- u32 tbatr2; /* 0x98 Target Base Address Translation Register 2 */
- u32 tbatr3; /* 0x9c Target Base Address Translation Register 3 */
- u32 tbatr4; /* 0xa0 Target Base Address Translation Register 4 */
- u32 tbatr5; /* 0xa4 Target Base Address Translation Register 5 */
- u32 intr; /* 0xa8 Interrupt Register */
- u32 rsvd4[19]; /* 0xac - 0xf7 */
- u32 car; /* 0xf8 Configuration Address Register */
-} pci_t;
-
-typedef struct pci_arbiter {
- /* Pci Arbiter Registers */
- union {
- u32 acr; /* Arbiter Control Register */
- u32 asr; /* Arbiter Status Register */
- };
-} pciarb_t;
-
-/* Register read/write struct */
-typedef struct scm1 {
- u32 mpr; /* 0x00 Master Privilege Register */
- u32 rsvd1[7];
- u32 pacra; /* 0x20 Peripheral Access Control Register A */
- u32 pacrb; /* 0x24 Peripheral Access Control Register B */
- u32 pacrc; /* 0x28 Peripheral Access Control Register C */
- u32 pacrd; /* 0x2C Peripheral Access Control Register D */
- u32 rsvd2[4];
- u32 pacre; /* 0x40 Peripheral Access Control Register E */
- u32 pacrf; /* 0x44 Peripheral Access Control Register F */
- u32 pacrg; /* 0x48 Peripheral Access Control Register G */
-} scm1_t;
-
-typedef struct scm2 {
- u8 rsvd1[19]; /* 0x00 - 0x12 */
- u8 wcr; /* 0x13 */
- u16 rsvd2; /* 0x14 - 0x15 */
- u16 cwcr; /* 0x16 */
- u8 rsvd3[3]; /* 0x18 - 0x1A */
- u8 cwsr; /* 0x1B */
- u8 rsvd4[3]; /* 0x1C - 0x1E */
- u8 scmisr; /* 0x1F */
- u32 rsvd5; /* 0x20 - 0x23 */
- u8 bcr; /* 0x24 */
- u8 rsvd6[74]; /* 0x25 - 0x6F */
- u32 cfadr; /* 0x70 */
- u8 rsvd7; /* 0x74 */
- u8 cfier; /* 0x75 */
- u8 cfloc; /* 0x76 */
- u8 cfatr; /* 0x77 */
- u32 rsvd8; /* 0x78 - 0x7B */
- u32 cfdtr; /* 0x7C */
-} scm2_t;
-
-typedef struct rtcex {
- u32 rsvd1[3];
- u32 gocu;
- u32 gocl;
-} rtcex_t;
-#endif /* __IMMAP_5445X__ */
diff --git a/arch/m68k/include/asm/m5227x.h b/arch/m68k/include/asm/m5227x.h
deleted file mode 100644
index 67c16e0..0000000
--- a/arch/m68k/include/asm/m5227x.h
+++ /dev/null
@@ -1,546 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0+ */
-/*
- * MCF5227x Internal Memory Map
- *
- * Copyright (C) 2004-2007 Freescale Semiconductor, Inc.
- * TsiChung Liew (Tsi-Chung.Liew@freescale.com)
- */
-
-#ifndef __MCF5227X__
-#define __MCF5227X__
-
-/* Interrupt Controller (INTC) */
-#define INT0_LO_RSVD0 (0)
-#define INT0_LO_EPORT1 (1)
-#define INT0_LO_EPORT4 (4)
-#define INT0_LO_EPORT7 (7)
-#define INT0_LO_EDMA_00 (8)
-#define INT0_LO_EDMA_01 (9)
-#define INT0_LO_EDMA_02 (10)
-#define INT0_LO_EDMA_03 (11)
-#define INT0_LO_EDMA_04 (12)
-#define INT0_LO_EDMA_05 (13)
-#define INT0_LO_EDMA_06 (14)
-#define INT0_LO_EDMA_07 (15)
-#define INT0_LO_EDMA_08 (16)
-#define INT0_LO_EDMA_09 (17)
-#define INT0_LO_EDMA_10 (18)
-#define INT0_LO_EDMA_11 (19)
-#define INT0_LO_EDMA_12 (20)
-#define INT0_LO_EDMA_13 (21)
-#define INT0_LO_EDMA_14 (22)
-#define INT0_LO_EDMA_15 (23)
-#define INT0_LO_EDMA_ERR (24)
-#define INT0_LO_SCM_CWIC (25)
-#define INT0_LO_UART0 (26)
-#define INT0_LO_UART1 (27)
-#define INT0_LO_UART2 (28)
-#define INT0_LO_I2C (30)
-#define INT0_LO_DSPI (31)
-#define INT0_HI_DTMR0 (32)
-#define INT0_HI_DTMR1 (33)
-#define INT0_HI_DTMR2 (34)
-#define INT0_HI_DTMR3 (35)
-#define INT0_HI_SCMIR (62)
-#define INT0_HI_RTC_ISR (63)
-
-#define INT1_HI_CAN_BOFFINT (1)
-#define INT1_HI_CAN_ERRINT (3)
-#define INT1_HI_CAN_BUF0I (4)
-#define INT1_HI_CAN_BUF1I (5)
-#define INT1_HI_CAN_BUF2I (6)
-#define INT1_HI_CAN_BUF3I (7)
-#define INT1_HI_CAN_BUF4I (8)
-#define INT1_HI_CAN_BUF5I (9)
-#define INT1_HI_CAN_BUF6I (10)
-#define INT1_HI_CAN_BUF7I (11)
-#define INT1_HI_CAN_BUF8I (12)
-#define INT1_HI_CAN_BUF9I (13)
-#define INT1_HI_CAN_BUF10I (14)
-#define INT1_HI_CAN_BUF11I (15)
-#define INT1_HI_CAN_BUF12I (16)
-#define INT1_HI_CAN_BUF13I (17)
-#define INT1_HI_CAN_BUF14I (18)
-#define INT1_HI_CAN_BUF15I (19)
-#define INT1_HI_PIT0_PIF (43)
-#define INT1_HI_PIT1_PIF (44)
-#define INT1_HI_USBOTG_STS (47)
-#define INT1_HI_SSI_ISR (49)
-#define INT1_HI_PWM_INT (50)
-#define INT1_HI_LCDC_ISR (51)
-#define INT1_HI_CCM_UOCSR (53)
-#define INT1_HI_DSPI_EOQF (54)
-#define INT1_HI_DSPI_TFFF (55)
-#define INT1_HI_DSPI_TCF (56)
-#define INT1_HI_DSPI_TFUF (57)
-#define INT1_HI_DSPI_RFDF (58)
-#define INT1_HI_DSPI_RFOF (59)
-#define INT1_HI_DSPI_RFOF_TFUF (60)
-#define INT1_HI_TOUCH_ADC (61)
-#define INT1_HI_PLL_LOCKS (62)
-
-/*********************************************************************
-* Reset Controller Module (RCM)
-*********************************************************************/
-
-/* Bit definitions and macros for RCR */
-#define RCM_RCR_FRCRSTOUT (0x40)
-#define RCM_RCR_SOFTRST (0x80)
-
-/* Bit definitions and macros for RSR */
-#define RCM_RSR_LOL (0x01)
-#define RCM_RSR_WDR_CORE (0x02)
-#define RCM_RSR_EXT (0x04)
-#define RCM_RSR_POR (0x08)
-#define RCM_RSR_SOFT (0x20)
-
-/*********************************************************************
-* Chip Configuration Module (CCM)
-*********************************************************************/
-
-/* Bit definitions and macros for CCR */
-#define CCM_CCR_DRAMSEL (0x0100)
-#define CCM_CCR_CSC_UNMASK (0xFF3F)
-#define CCM_CCR_CSC_FBCS5_CS4 (0x00C0)
-#define CCM_CCR_CSC_FBCS5_A22 (0x0080)
-#define CCM_CCR_CSC_FB_A23_A22 (0x0040)
-#define CCM_CCR_LIMP (0x0020)
-#define CCM_CCR_LOAD (0x0010)
-#define CCM_CCR_BOOTPS_UNMASK (0xFFF3)
-#define CCM_CCR_BOOTPS_PS16 (0x0008)
-#define CCM_CCR_BOOTPS_PS8 (0x0004)
-#define CCM_CCR_BOOTPS_PS32 (0x0000)
-#define CCM_CCR_OSCMODE_OSCBYPASS (0x0002)
-
-/* Bit definitions and macros for RCON */
-#define CCM_RCON_CSC_UNMASK (0xFF3F)
-#define CCM_RCON_CSC_FBCS5_CS4 (0x00C0)
-#define CCM_RCON_CSC_FBCS5_A22 (0x0080)
-#define CCM_RCON_CSC_FB_A23_A22 (0x0040)
-#define CCM_RCON_LIMP (0x0020)
-#define CCM_RCON_LOAD (0x0010)
-#define CCM_RCON_BOOTPS_UNMASK (0xFFF3)
-#define CCM_RCON_BOOTPS_PS16 (0x0008)
-#define CCM_RCON_BOOTPS_PS8 (0x0004)
-#define CCM_RCON_BOOTPS_PS32 (0x0000)
-#define CCM_RCON_OSCMODE_OSCBYPASS (0x0002)
-
-/* Bit definitions and macros for CIR */
-#define CCM_CIR_PIN(x) (((x) & 0xFFC0) >> 6)
-#define CCM_CIR_PRN(x) ((x) & 0x003F)
-#define CCM_CIR_PIN_MCF52277 (0x0000)
-
-/* Bit definitions and macros for MISCCR */
-#define CCM_MISCCR_RTCSRC (0x4000)
-#define CCM_MISCCR_USBPUE (0x2000) /* USB transceiver pull-up */
-#define CCM_MISCCR_LIMP (0x1000) /* Limp mode enable */
-
-#define CCM_MISCCR_BME (0x0800) /* Bus monitor ext en bit */
-#define CCM_MISCCR_BMT_65536 (0)
-#define CCM_MISCCR_BMT_32768 (1)
-#define CCM_MISCCR_BMT_16384 (2)
-#define CCM_MISCCR_BMT_8192 (3)
-#define CCM_MISCCR_BMT_4096 (4)
-#define CCM_MISCCR_BMT_2048 (5)
-#define CCM_MISCCR_BMT_1024 (6)
-#define CCM_MISCCR_BMT_512 (7)
-
-#define CCM_MISCCR_SSIPUE (0x0080) /* SSI RXD/TXD pull enable */
-#define CCM_MISCCR_SSIPUS (0x0040) /* SSI RXD/TXD pull select */
-#define CCM_MISCCR_TIMDMA (0x0020) /* Timer DMA mux selection */
-#define CCM_MISCCR_SSISRC (0x0010) /* SSI clock source */
-#define CCM_MISCCR_LCDCHEN (0x0004) /* LCD Int CLK en */
-#define CCM_MISCCR_USBOC (0x0002) /* USB VBUS over-current sense pol */
-#define CCM_MISCCR_USBSRC (0x0001) /* USB clock source */
-
-/* Bit definitions and macros for CDR */
-#define CCM_CDR_USBDIV(x) (((x)&0x0003)<<12)
-#define CCM_CDR_LPDIV(x) (((x)&0x000F)<<8) /* Low power clk div */
-#define CCM_CDR_SSIDIV(x) (((x)&0x00FF)) /* SSI oversampling clk div */
-
-/* Bit definitions and macros for UOCSR */
-#define CCM_UOCSR_DPPD (0x2000) /* D+ 15Kohm pull-down (rd-only) */
-#define CCM_UOCSR_DMPD (0x1000) /* D- 15Kohm pull-down (rd-only) */
-#define CCM_UOCSR_CRG_VBUS (0x0400) /* VBUS charge resistor enabled (rd-only) */
-#define CCM_UOCSR_DCR_VBUS (0x0200) /* VBUS discharge resistor en (rd-only) */
-#define CCM_UOCSR_DPPU (0x0100) /* D+ pull-up for FS enabled (rd-only) */
-#define CCM_UOCSR_AVLD (0x0080) /* A-peripheral valid indicator */
-#define CCM_UOCSR_BVLD (0x0040) /* B-peripheral valid indicator */
-#define CCM_UOCSR_VVLD (0x0020) /* VBUS valid indicator */
-#define CCM_UOCSR_SEND (0x0010) /* Session end */
-#define CCM_UOCSR_WKUP (0x0004) /* USB OTG controller wake-up event */
-#define CCM_UOCSR_UOMIE (0x0002) /* USB OTG misc interrupt en */
-#define CCM_UOCSR_XPDE (0x0001) /* On-chip transceiver pull-down en */
-
-/*********************************************************************
-* General Purpose I/O Module (GPIO)
-*********************************************************************/
-/* Bit definitions and macros for PAR_BE */
-#define GPIO_PAR_BE_UNMASK (0x0F)
-#define GPIO_PAR_BE_BE3_BE3 (0x08)
-#define GPIO_PAR_BE_BE3_GPIO (0x00)
-#define GPIO_PAR_BE_BE2_BE2 (0x04)
-#define GPIO_PAR_BE_BE2_GPIO (0x00)
-#define GPIO_PAR_BE_BE1_BE1 (0x02)
-#define GPIO_PAR_BE_BE1_GPIO (0x00)
-#define GPIO_PAR_BE_BE0_BE0 (0x01)
-#define GPIO_PAR_BE_BE0_GPIO (0x00)
-
-/* Bit definitions and macros for PAR_CS */
-#define GPIO_PAR_CS_CS3 (0x10)
-#define GPIO_PAR_CS_CS2 (0x08)
-#define GPIO_PAR_CS_CS1_FBCS1 (0x06)
-#define GPIO_PAR_CS_CS1_SDCS1 (0x04)
-#define GPIO_PAR_CS_CS1_GPIO (0x00)
-#define GPIO_PAR_CS_CS0 (0x01)
-
-/* Bit definitions and macros for PAR_FBCTL */
-#define GPIO_PAR_FBCTL_OE (0x80)
-#define GPIO_PAR_FBCTL_TA (0x40)
-#define GPIO_PAR_FBCTL_RW (0x20)
-#define GPIO_PAR_FBCTL_TS_UNMASK (0xE7)
-#define GPIO_PAR_FBCTL_TS_FBTS (0x18)
-#define GPIO_PAR_FBCTL_TS_DMAACK (0x10)
-#define GPIO_PAR_FBCTL_TS_GPIO (0x00)
-
-/* Bit definitions and macros for PAR_FECI2C */
-#define GPIO_PAR_I2C_SCL_UNMASK (0xF3)
-#define GPIO_PAR_I2C_SCL_SCL (0x0C)
-#define GPIO_PAR_I2C_SCL_CANTXD (0x08)
-#define GPIO_PAR_I2C_SCL_U2TXD (0x04)
-#define GPIO_PAR_I2C_SCL_GPIO (0x00)
-
-#define GPIO_PAR_I2C_SDA_UNMASK (0xFC)
-#define GPIO_PAR_I2C_SDA_SDA (0x03)
-#define GPIO_PAR_I2C_SDA_CANRXD (0x02)
-#define GPIO_PAR_I2C_SDA_U2RXD (0x01)
-#define GPIO_PAR_I2C_SDA_GPIO (0x00)
-
-/* Bit definitions and macros for PAR_UART */
-#define GPIO_PAR_UART_U1CTS_UNMASK (0x3FFF)
-#define GPIO_PAR_UART_U1CTS_U1CTS (0xC000)
-#define GPIO_PAR_UART_U1CTS_SSIBCLK (0x8000)
-#define GPIO_PAR_UART_U1CTS_LCDCLS (0x4000)
-#define GPIO_PAR_UART_U1CTS_GPIO (0x0000)
-
-#define GPIO_PAR_UART_U1RTS_UNMASK (0xCFFF)
-#define GPIO_PAR_UART_U1RTS_U1RTS (0x3000)
-#define GPIO_PAR_UART_U1RTS_SSIFS (0x2000)
-#define GPIO_PAR_UART_U1RTS_LCDPS (0x1000)
-#define GPIO_PAR_UART_U1RTS_GPIO (0x0000)
-
-#define GPIO_PAR_UART_U1RXD_UNMASK (0xF3FF)
-#define GPIO_PAR_UART_U1RXD_U1RXD (0x0C00)
-#define GPIO_PAR_UART_U1RXD_SSIRXD (0x0800)
-#define GPIO_PAR_UART_U1RXD_GPIO (0x0000)
-
-#define GPIO_PAR_UART_U1TXD_UNMASK (0xFCFF)
-#define GPIO_PAR_UART_U1TXD_U1TXD (0x0300)
-#define GPIO_PAR_UART_U1TXD_SSITXD (0x0200)
-#define GPIO_PAR_UART_U1TXD_GPIO (0x0000)
-
-#define GPIO_PAR_UART_U0CTS_UNMASK (0xFF3F)
-#define GPIO_PAR_UART_U0CTS_U0CTS (0x00C0)
-#define GPIO_PAR_UART_U0CTS_T1OUT (0x0080)
-#define GPIO_PAR_UART_U0CTS_USBVBUSEN (0x0040)
-#define GPIO_PAR_UART_U0CTS_GPIO (0x0000)
-
-#define GPIO_PAR_UART_U0RTS_UNMASK (0xFFCF)
-#define GPIO_PAR_UART_U0RTS_U0RTS (0x0030)
-#define GPIO_PAR_UART_U0RTS_T1IN (0x0020)
-#define GPIO_PAR_UART_U0RTS_USBVBUSOC (0x0010)
-#define GPIO_PAR_UART_U0RTS_GPIO (0x0000)
-
-#define GPIO_PAR_UART_U0RXD_UNMASK (0xFFF3)
-#define GPIO_PAR_UART_U0RXD_U0RXD (0x000C)
-#define GPIO_PAR_UART_U0RXD_CANRX (0x0008)
-#define GPIO_PAR_UART_U0RXD_GPIO (0x0000)
-
-#define GPIO_PAR_UART_U0TXD_UNMASK (0xFFFC)
-#define GPIO_PAR_UART_U0TXD_U0TXD (0x0003)
-#define GPIO_PAR_UART_U0TXD_CANTX (0x0002)
-#define GPIO_PAR_UART_U0TXD_GPIO (0x0000)
-
-/* Bit definitions and macros for PAR_DSPI */
-#define GPIO_PAR_DSPI_PCS0_UNMASK (0x3F)
-#define GPIO_PAR_DSPI_PCS0_PCS0 (0xC0)
-#define GPIO_PAR_DSPI_PCS0_U2RTS (0x80)
-#define GPIO_PAR_DSPI_PCS0_GPIO (0x00)
-#define GPIO_PAR_DSPI_SIN_UNMASK (0xCF)
-#define GPIO_PAR_DSPI_SIN_SIN (0x30)
-#define GPIO_PAR_DSPI_SIN_U2RXD (0x20)
-#define GPIO_PAR_DSPI_SIN_GPIO (0x00)
-#define GPIO_PAR_DSPI_SOUT_UNMASK (0xF3)
-#define GPIO_PAR_DSPI_SOUT_SOUT (0x0C)
-#define GPIO_PAR_DSPI_SOUT_U2TXD (0x08)
-#define GPIO_PAR_DSPI_SOUT_GPIO (0x00)
-#define GPIO_PAR_DSPI_SCK_UNMASK (0xFC)
-#define GPIO_PAR_DSPI_SCK_SCK (0x03)
-#define GPIO_PAR_DSPI_SCK_U2CTS (0x02)
-#define GPIO_PAR_DSPI_SCK_GPIO (0x00)
-
-/* Bit definitions and macros for PAR_TIMER */
-#define GPIO_PAR_TIMER_T3IN_UNMASK (0x3F)
-#define GPIO_PAR_TIMER_T3IN_T3IN (0xC0)
-#define GPIO_PAR_TIMER_T3IN_T3OUT (0x80)
-#define GPIO_PAR_TIMER_T3IN_SSIMCLK (0x40)
-#define GPIO_PAR_TIMER_T3IN_GPIO (0x00)
-#define GPIO_PAR_TIMER_T2IN_UNMASK (0xCF)
-#define GPIO_PAR_TIMER_T2IN_T2IN (0x30)
-#define GPIO_PAR_TIMER_T2IN_T2OUT (0x20)
-#define GPIO_PAR_TIMER_T2IN_DSPIPCS2 (0x10)
-#define GPIO_PAR_TIMER_T2IN_GPIO (0x00)
-#define GPIO_PAR_TIMER_T1IN_UNMASK (0xF3)
-#define GPIO_PAR_TIMER_T1IN_T1IN (0x0C)
-#define GPIO_PAR_TIMER_T1IN_T1OUT (0x08)
-#define GPIO_PAR_TIMER_T1IN_LCDCONTRAST (0x04)
-#define GPIO_PAR_TIMER_T1IN_GPIO (0x00)
-#define GPIO_PAR_TIMER_T0IN_UNMASK (0xFC)
-#define GPIO_PAR_TIMER_T0IN_T0IN (0x03)
-#define GPIO_PAR_TIMER_T0IN_T0OUT (0x02)
-#define GPIO_PAR_TIMER_T0IN_LCDREV (0x01)
-#define GPIO_PAR_TIMER_T0IN_GPIO (0x00)
-
-/* Bit definitions and macros for GPIO_PAR_LCDCTL */
-#define GPIO_PAR_LCDCTL_ACDOE_UNMASK (0xE7)
-#define GPIO_PAR_LCDCTL_ACDOE_ACDOE (0x18)
-#define GPIO_PAR_LCDCTL_ACDOE_SPLSPR (0x10)
-#define GPIO_PAR_LCDCTL_ACDOE_GPIO (0x00)
-#define GPIO_PAR_LCDCTL_FLM_VSYNC (0x04)
-#define GPIO_PAR_LCDCTL_LP_HSYNC (0x02)
-#define GPIO_PAR_LCDCTL_LSCLK (0x01)
-
-/* Bit definitions and macros for PAR_IRQ */
-#define GPIO_PAR_IRQ_IRQ4_UNMASK (0xF3)
-#define GPIO_PAR_IRQ_IRQ4_SSIINPCLK (0x0C)
-#define GPIO_PAR_IRQ_IRQ4_DMAREQ0 (0x08)
-#define GPIO_PAR_IRQ_IRQ4_GPIO (0x00)
-#define GPIO_PAR_IRQ_IRQ1_UNMASK (0xFC)
-#define GPIO_PAR_IRQ_IRQ1_PCIINT (0x03)
-#define GPIO_PAR_IRQ_IRQ1_USBCLKIN (0x02)
-#define GPIO_PAR_IRQ_IRQ1_SSICLKIN (0x01)
-#define GPIO_PAR_IRQ_IRQ1_GPIO (0x00)
-
-/* Bit definitions and macros for GPIO_PAR_LCDH */
-#define GPIO_PAR_LCDH_LD17_UNMASK (0xFFFFF3FF)
-#define GPIO_PAR_LCDH_LD17_LD17 (0x00000C00)
-#define GPIO_PAR_LCDH_LD17_LD11 (0x00000800)
-#define GPIO_PAR_LCDH_LD17_GPIO (0x00000000)
-
-#define GPIO_PAR_LCDH_LD16_UNMASK (0xFFFFFCFF)
-#define GPIO_PAR_LCDH_LD16_LD16 (0x00000300)
-#define GPIO_PAR_LCDH_LD16_LD10 (0x00000200)
-#define GPIO_PAR_LCDH_LD16_GPIO (0x00000000)
-
-#define GPIO_PAR_LCDH_LD15_UNMASK (0xFFFFFF3F)
-#define GPIO_PAR_LCDH_LD15_LD15 (0x000000C0)
-#define GPIO_PAR_LCDH_LD15_LD9 (0x00000080)
-#define GPIO_PAR_LCDH_LD15_GPIO (0x00000000)
-
-#define GPIO_PAR_LCDH_LD14_UNMASK (0xFFFFFFCF)
-#define GPIO_PAR_LCDH_LD14_LD14 (0x00000030)
-#define GPIO_PAR_LCDH_LD14_LD8 (0x00000020)
-#define GPIO_PAR_LCDH_LD14_GPIO (0x00000000)
-
-#define GPIO_PAR_LCDH_LD13_UNMASK (0xFFFFFFF3)
-#define GPIO_PAR_LCDH_LD13_LD13 (0x0000000C)
-#define GPIO_PAR_LCDH_LD13_CANTX (0x00000008)
-#define GPIO_PAR_LCDH_LD13_GPIO (0x00000000)
-
-#define GPIO_PAR_LCDH_LD12_UNMASK (0xFFFFFFFC)
-#define GPIO_PAR_LCDH_LD12_LD12 (0x00000003)
-#define GPIO_PAR_LCDH_LD12_CANRX (0x00000002)
-#define GPIO_PAR_LCDH_LD12_GPIO (0x00000000)
-
-/* Bit definitions and macros for GPIO_PAR_LCDL */
-#define GPIO_PAR_LCDL_LD11_UNMASK (0x3FFFFFFF)
-#define GPIO_PAR_LCDL_LD11_LD11 (0xC0000000)
-#define GPIO_PAR_LCDL_LD11_LD7 (0x80000000)
-#define GPIO_PAR_LCDL_LD11_GPIO (0x00000000)
-
-#define GPIO_PAR_LCDL_LD10_UNMASK (0xCFFFFFFF)
-#define GPIO_PAR_LCDL_LD10_LD10 (0x30000000)
-#define GPIO_PAR_LCDL_LD10_LD6 (0x20000000)
-#define GPIO_PAR_LCDL_LD10_GPIO (0x00000000)
-
-#define GPIO_PAR_LCDL_LD9_UNMASK (0xF3FFFFFF)
-#define GPIO_PAR_LCDL_LD9_LD9 (0x0C000000)
-#define GPIO_PAR_LCDL_LD9_LD5 (0x08000000)
-#define GPIO_PAR_LCDL_LD9_GPIO (0x00000000)
-
-#define GPIO_PAR_LCDL_LD8_UNMASK (0xFCFFFFFF)
-#define GPIO_PAR_LCDL_LD8_LD8 (0x03000000)
-#define GPIO_PAR_LCDL_LD8_LD4 (0x02000000)
-#define GPIO_PAR_LCDL_LD8_GPIO (0x00000000)
-
-#define GPIO_PAR_LCDL_LD7_UNMASK (0xFF3FFFFF)
-#define GPIO_PAR_LCDL_LD7_LD7 (0x00C00000)
-#define GPIO_PAR_LCDL_LD7_PWM7 (0x00800000)
-#define GPIO_PAR_LCDL_LD7_GPIO (0x00000000)
-
-#define GPIO_PAR_LCDL_LD6_UNMASK (0xFFCFFFFF)
-#define GPIO_PAR_LCDL_LD6_LD6 (0x00300000)
-#define GPIO_PAR_LCDL_LD6_PWM5 (0x00200000)
-#define GPIO_PAR_LCDL_LD6_GPIO (0x00000000)
-
-#define GPIO_PAR_LCDL_LD5_UNMASK (0xFFF3FFFF)
-#define GPIO_PAR_LCDL_LD5_LD5 (0x000C0000)
-#define GPIO_PAR_LCDL_LD5_LD3 (0x00080000)
-#define GPIO_PAR_LCDL_LD5_GPIO (0x00000000)
-
-#define GPIO_PAR_LCDL_LD4_UNMASK (0xFFFCFFFF)
-#define GPIO_PAR_LCDL_LD4_LD4 (0x00030000)
-#define GPIO_PAR_LCDL_LD4_LD2 (0x00020000)
-#define GPIO_PAR_LCDL_LD4_GPIO (0x00000000)
-
-#define GPIO_PAR_LCDL_LD3_UNMASK (0xFFFF3FFF)
-#define GPIO_PAR_LCDL_LD3_LD3 (0x0000C000)
-#define GPIO_PAR_LCDL_LD3_LD1 (0x00008000)
-#define GPIO_PAR_LCDL_LD3_GPIO (0x00000000)
-
-#define GPIO_PAR_LCDL_LD2_UNMASK (0xFFFFCFFF)
-#define GPIO_PAR_LCDL_LD2_LD2 (0x00003000)
-#define GPIO_PAR_LCDL_LD2_LD0 (0x00002000)
-#define GPIO_PAR_LCDL_LD2_GPIO (0x00000000)
-
-#define GPIO_PAR_LCDL_LD1_UNMASK (0xFFFFF3FF)
-#define GPIO_PAR_LCDL_LD1_LD1 (0x00000C00)
-#define GPIO_PAR_LCDL_LD1_PWM3 (0x00000800)
-#define GPIO_PAR_LCDL_LD1_GPIO (0x00000000)
-
-#define GPIO_PAR_LCDL_LD0_UNMASK (0xFFFFFCFF)
-#define GPIO_PAR_LCDL_LD0_LD0 (0x00000300)
-#define GPIO_PAR_LCDL_LD0_PWM1 (0x00000200)
-#define GPIO_PAR_LCDL_LD0_GPIO (0x00000000)
-
-/* Bit definitions and macros for MSCR_FB */
-#define GPIO_MSCR_FB_DUPPER_UNMASK (0xCF)
-#define GPIO_MSCR_FB_DUPPER_25V_33V (0x30)
-#define GPIO_MSCR_FB_DUPPER_FULL_18V (0x20)
-#define GPIO_MSCR_FB_DUPPER_OD (0x10)
-#define GPIO_MSCR_FB_DUPPER_HALF_18V (0x00)
-
-#define GPIO_MSCR_FB_DLOWER_UNMASK (0xF3)
-#define GPIO_MSCR_FB_DLOWER_25V_33V (0x0C)
-#define GPIO_MSCR_FB_DLOWER_FULL_18V (0x08)
-#define GPIO_MSCR_FB_DLOWER_OD (0x04)
-#define GPIO_MSCR_FB_DLOWER_HALF_18V (0x00)
-
-#define GPIO_MSCR_FB_ADDRCTL_UNMASK (0xFC)
-#define GPIO_MSCR_FB_ADDRCTL_25V_33V (0x03)
-#define GPIO_MSCR_FB_ADDRCTL_FULL_18V (0x02)
-#define GPIO_MSCR_FB_ADDRCTL_OD (0x01)
-#define GPIO_MSCR_FB_ADDRCTL_HALF_18V (0x00)
-
-/* Bit definitions and macros for MSCR_SDRAM */
-#define GPIO_MSCR_SDRAM_SDCLKB_UNMASK (0xCF)
-#define GPIO_MSCR_SDRAM_SDCLKB_25V_33V (0x30)
-#define GPIO_MSCR_SDRAM_SDCLKB_FULL_18V (0x20)
-#define GPIO_MSCR_SDRAM_SDCLKB_OD (0x10)
-#define GPIO_MSCR_SDRAM_SDCLKB_HALF_18V (0x00)
-
-#define GPIO_MSCR_SDRAM_SDCLK_UNMASK (0xF3)
-#define GPIO_MSCR_SDRAM_SDCLK_25V_33V (0x0C)
-#define GPIO_MSCR_SDRAM_SDCLK_FULL_18V (0x08)
-#define GPIO_MSCR_SDRAM_SDCLK_OPD (0x04)
-#define GPIO_MSCR_SDRAM_SDCLK_HALF_18V (0x00)
-
-#define GPIO_MSCR_SDRAM_SDCTL_UNMASK (0xFC)
-#define GPIO_MSCR_SDRAM_SDCTL_25V_33V (0x03)
-#define GPIO_MSCR_SDRAM_SDCTL_FULL_18V (0x02)
-#define GPIO_MSCR_SDRAM_SDCTL_OPD (0x01)
-#define GPIO_MSCR_SDRAM_SDCTL_HALF_18V (0x00)
-
-/* Bit definitions and macros for Drive Strength Control */
-#define DSCR_LOAD_50PF (0x03)
-#define DSCR_LOAD_30PF (0x02)
-#define DSCR_LOAD_20PF (0x01)
-#define DSCR_LOAD_10PF (0x00)
-
-/*********************************************************************
-* SDRAM Controller (SDRAMC)
-*********************************************************************/
-
-/* Bit definitions and macros for SDMR */
-#define SDRAMC_SDMR_DDR2_AD(x) (((x)&0x00003FFF)) /* Address for DDR2 */
-#define SDRAMC_SDMR_CMD (0x00010000) /* Command */
-#define SDRAMC_SDMR_AD(x) (((x)&0x00000FFF)<<18) /* Address */
-#define SDRAMC_SDMR_BK(x) (((x)&0x00000003)<<30) /* Bank Address */
-#define SDRAMC_SDMR_BK_LMR (0x00000000)
-#define SDRAMC_SDMR_BK_LEMR (0x40000000)
-
-/* Bit definitions and macros for SDCR */
-#define SDRAMC_SDCR_DPD (0x00000001) /* Deep Power-Down Mode */
-#define SDRAMC_SDCR_IPALL (0x00000002) /* Initiate Precharge All */
-#define SDRAMC_SDCR_IREF (0x00000004) /* Initiate Refresh */
-#define SDRAMC_SDCR_DQS_OE(x) (((x)&0x00000003)<<10) /* DQS Output Enable */
-#define SDRAMC_SDCR_MEM_PS (0x00002000) /* Data Port Size */
-#define SDRAMC_SDCR_REF_CNT(x) (((x)&0x0000003F)<<16) /* Periodic Refresh Counter */
-#define SDRAMC_SDCR_OE_RULE (0x00400000) /* Drive Rule Selection */
-#define SDRAMC_SDCR_ADDR_MUX(x) (((x)&0x00000003)<<24) /* Internal Address Mux Select */
-#define SDRAMC_SDCR_DDR2_MODE (0x08000000) /* DDR2 Mode Select */
-#define SDRAMC_SDCR_REF_EN (0x10000000) /* Refresh Enable */
-#define SDRAMC_SDCR_DDR_MODE (0x20000000) /* DDR Mode Select */
-#define SDRAMC_SDCR_CKE (0x40000000) /* Clock Enable */
-#define SDRAMC_SDCR_MODE_EN (0x80000000) /* SDRAM Mode Register Programming Enable */
-#define SDRAMC_SDCR_DQS_OE_BOTH (0x00000C000)
-
-/* Bit definitions and macros for SDCFG1 */
-#define SDRAMC_SDCFG1_WT_LAT(x) (((x)&0x00000007)<<4) /* Write Latency */
-#define SDRAMC_SDCFG1_REF2ACT(x) (((x)&0x0000000F)<<8) /* Refresh to active delay */
-#define SDRAMC_SDCFG1_PRE2ACT(x) (((x)&0x00000007)<<12) /* Precharge to active delay */
-#define SDRAMC_SDCFG1_ACT2RW(x) (((x)&0x00000007)<<16) /* Active to read/write delay */
-#define SDRAMC_SDCFG1_RD_LAT(x) (((x)&0x0000000F)<<20) /* Read CAS Latency */
-#define SDRAMC_SDCFG1_SWT2RWP(x) (((x)&0x00000007)<<24) /* Single write to read/write/precharge delay */
-#define SDRAMC_SDCFG1_SRD2RWP(x) (((x)&0x0000000F)<<28) /* Single read to read/write/precharge delay */
-
-/* Bit definitions and macros for SDCFG2 */
-#define SDRAMC_SDCFG2_BL(x) (((x)&0x0000000F)<<16) /* Burst Length */
-#define SDRAMC_SDCFG2_BRD2W(x) (((x)&0x0000000F)<<20) /* Burst read to write delay */
-#define SDRAMC_SDCFG2_BWT2RWP(x) (((x)&0x0000000F)<<24) /* Burst write to read/write/precharge delay */
-#define SDRAMC_SDCFG2_BRD2RP(x) (((x)&0x0000000F)<<28) /* Burst read to read/precharge delay */
-
-/* Bit definitions and macros for SDCS group */
-#define SDRAMC_SDCS_CSSZ(x) (((x)&0x0000001F)) /* Chip-Select Size */
-#define SDRAMC_SDCS_CSBA(x) (((x)&0x00000FFF)<<20) /* Chip-Select Base Address */
-#define SDRAMC_SDCS_BA(x) ((x)&0xFFF00000)
-#define SDRAMC_SDCS_CSSZ_DISABLE (0x00000000)
-#define SDRAMC_SDCS_CSSZ_1MBYTE (0x00000013)
-#define SDRAMC_SDCS_CSSZ_2MBYTE (0x00000014)
-#define SDRAMC_SDCS_CSSZ_4MBYTE (0x00000015)
-#define SDRAMC_SDCS_CSSZ_8MBYTE (0x00000016)
-#define SDRAMC_SDCS_CSSZ_16MBYTE (0x00000017)
-#define SDRAMC_SDCS_CSSZ_32MBYTE (0x00000018)
-#define SDRAMC_SDCS_CSSZ_64MBYTE (0x00000019)
-#define SDRAMC_SDCS_CSSZ_128MBYTE (0x0000001A)
-#define SDRAMC_SDCS_CSSZ_256MBYTE (0x0000001B)
-#define SDRAMC_SDCS_CSSZ_512MBYTE (0x0000001C)
-#define SDRAMC_SDCS_CSSZ_1GBYTE (0x0000001D)
-#define SDRAMC_SDCS_CSSZ_2GBYTE (0x0000001E)
-#define SDRAMC_SDCS_CSSZ_4GBYTE (0x0000001F)
-
-/*********************************************************************
-* Phase Locked Loop (PLL)
-*********************************************************************/
-
-/* Bit definitions and macros for PCR */
-#define PLL_PCR_OUTDIV1(x) (((x)&0x0000000F)) /* Output divider for CPU clock frequency */
-#define PLL_PCR_OUTDIV2(x) (((x)&0x0000000F)<<4) /* Output divider for bus/flexbus clock frequency */
-#define PLL_PCR_OUTDIV3(x) (((x)&0x0000000F)<<8) /* Output divider for SDRAM clock frequency */
-#define PLL_PCR_OUTDIV5(x) (((x)&0x0000000F)<<16) /* Output divider for USB clock frequency */
-#define PLL_PCR_PFDR(x) (((x)&0x000000FF)<<24) /* Feedback divider for VCO frequency */
-#define PLL_PCR_PFDR_MASK (0x000F0000)
-#define PLL_PCR_OUTDIV5_MASK (0x000F0000)
-#define PLL_PCR_OUTDIV3_MASK (0x00000F00)
-#define PLL_PCR_OUTDIV2_MASK (0x000000F0)
-#define PLL_PCR_OUTDIV1_MASK (0x0000000F)
-
-/* Bit definitions and macros for PSR */
-#define PLL_PSR_LOCKS (0x00000001) /* PLL lost lock - sticky */
-#define PLL_PSR_LOCK (0x00000002) /* PLL lock status */
-#define PLL_PSR_LOLIRQ (0x00000004) /* PLL loss-of-lock interrupt enable */
-#define PLL_PSR_LOLRE (0x00000008) /* PLL loss-of-lock reset enable */
-
-/********************************************************************/
-
-#endif /* __MCF5227X__ */
diff --git a/arch/m68k/include/asm/m5445x.h b/arch/m68k/include/asm/m5445x.h
deleted file mode 100644
index 498c225..0000000
--- a/arch/m68k/include/asm/m5445x.h
+++ /dev/null
@@ -1,888 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0+ */
-/*
- * MCF5445x Internal Memory Map
- *
- * Copyright (C) 2004-2007 Freescale Semiconductor, Inc.
- * TsiChung Liew (Tsi-Chung.Liew@freescale.com)
- */
-
-#ifndef __MCF5445X__
-#define __MCF5445X__
-
-/*********************************************************************
-* Interrupt Controller (INTC)
-*********************************************************************/
-#define INT0_LO_RSVD0 (0)
-#define INT0_LO_EPORT1 (1)
-#define INT0_LO_EPORT2 (2)
-#define INT0_LO_EPORT3 (3)
-#define INT0_LO_EPORT4 (4)
-#define INT0_LO_EPORT5 (5)
-#define INT0_LO_EPORT6 (6)
-#define INT0_LO_EPORT7 (7)
-#define INT0_LO_EDMA_00 (8)
-#define INT0_LO_EDMA_01 (9)
-#define INT0_LO_EDMA_02 (10)
-#define INT0_LO_EDMA_03 (11)
-#define INT0_LO_EDMA_04 (12)
-#define INT0_LO_EDMA_05 (13)
-#define INT0_LO_EDMA_06 (14)
-#define INT0_LO_EDMA_07 (15)
-#define INT0_LO_EDMA_08 (16)
-#define INT0_LO_EDMA_09 (17)
-#define INT0_LO_EDMA_10 (18)
-#define INT0_LO_EDMA_11 (19)
-#define INT0_LO_EDMA_12 (20)
-#define INT0_LO_EDMA_13 (21)
-#define INT0_LO_EDMA_14 (22)
-#define INT0_LO_EDMA_15 (23)
-#define INT0_LO_EDMA_ERR (24)
-#define INT0_LO_SCM (25)
-#define INT0_LO_UART0 (26)
-#define INT0_LO_UART1 (27)
-#define INT0_LO_UART2 (28)
-#define INT0_LO_RSVD1 (29)
-#define INT0_LO_I2C (30)
-#define INT0_LO_QSPI (31)
-#define INT0_HI_DTMR0 (32)
-#define INT0_HI_DTMR1 (33)
-#define INT0_HI_DTMR2 (34)
-#define INT0_HI_DTMR3 (35)
-#define INT0_HI_FEC0_TXF (36)
-#define INT0_HI_FEC0_TXB (37)
-#define INT0_HI_FEC0_UN (38)
-#define INT0_HI_FEC0_RL (39)
-#define INT0_HI_FEC0_RXF (40)
-#define INT0_HI_FEC0_RXB (41)
-#define INT0_HI_FEC0_MII (42)
-#define INT0_HI_FEC0_LC (43)
-#define INT0_HI_FEC0_HBERR (44)
-#define INT0_HI_FEC0_GRA (45)
-#define INT0_HI_FEC0_EBERR (46)
-#define INT0_HI_FEC0_BABT (47)
-#define INT0_HI_FEC0_BABR (48)
-#define INT0_HI_FEC1_TXF (49)
-#define INT0_HI_FEC1_TXB (50)
-#define INT0_HI_FEC1_UN (51)
-#define INT0_HI_FEC1_RL (52)
-#define INT0_HI_FEC1_RXF (53)
-#define INT0_HI_FEC1_RXB (54)
-#define INT0_HI_FEC1_MII (55)
-#define INT0_HI_FEC1_LC (56)
-#define INT0_HI_FEC1_HBERR (57)
-#define INT0_HI_FEC1_GRA (58)
-#define INT0_HI_FEC1_EBERR (59)
-#define INT0_HI_FEC1_BABT (60)
-#define INT0_HI_FEC1_BABR (61)
-#define INT0_HI_SCMIR (62)
-#define INT0_HI_RTC_ISR (63)
-
-#define INT1_HI_DSPI_EOQF (33)
-#define INT1_HI_DSPI_TFFF (34)
-#define INT1_HI_DSPI_TCF (35)
-#define INT1_HI_DSPI_TFUF (36)
-#define INT1_HI_DSPI_RFDF (37)
-#define INT1_HI_DSPI_RFOF (38)
-#define INT1_HI_DSPI_RFOF_TFUF (39)
-#define INT1_HI_RNG_EI (40)
-#define INT1_HI_PIT0_PIF (43)
-#define INT1_HI_PIT1_PIF (44)
-#define INT1_HI_PIT2_PIF (45)
-#define INT1_HI_PIT3_PIF (46)
-#define INT1_HI_USBOTG_USBSTS (47)
-#define INT1_HI_SSI_ISR (49)
-#define INT1_HI_CCM_UOCSR (53)
-#define INT1_HI_ATA_ISR (54)
-#define INT1_HI_PCI_SCR (55)
-#define INT1_HI_PCI_ASR (56)
-#define INT1_HI_PLL_LOCKS (57)
-
-/*********************************************************************
-* Watchdog Timer Modules (WTM)
-*********************************************************************/
-
-/* Bit definitions and macros for WCR */
-#define WTM_WCR_EN (0x0001)
-#define WTM_WCR_HALTED (0x0002)
-#define WTM_WCR_DOZE (0x0004)
-#define WTM_WCR_WAIT (0x0008)
-
-/*********************************************************************
-* Serial Boot Facility (SBF)
-*********************************************************************/
-
-/* Bit definitions and macros for SBFCR */
-#define SBF_SBFCR_BLDIV(x) (((x)&0x000F)) /* Boot loader clock divider */
-#define SBF_SBFCR_FR (0x0010) /* Fast read */
-
-/*********************************************************************
-* Reset Controller Module (RCM)
-*********************************************************************/
-
-/* Bit definitions and macros for RCR */
-#define RCM_RCR_FRCRSTOUT (0x40)
-#define RCM_RCR_SOFTRST (0x80)
-
-/* Bit definitions and macros for RSR */
-#define RCM_RSR_LOL (0x01)
-#define RCM_RSR_WDR_CORE (0x02)
-#define RCM_RSR_EXT (0x04)
-#define RCM_RSR_POR (0x08)
-#define RCM_RSR_SOFT (0x20)
-
-/*********************************************************************
-* Chip Configuration Module (CCM)
-*********************************************************************/
-
-/* Bit definitions and macros for CCR_360 */
-#define CCM_CCR_360_PLLMULT2(x) (((x)&0x0003)) /* 2-Bit PLL clock mode */
-#define CCM_CCR_360_PCISLEW (0x0004) /* PCI pad slew rate mode */
-#define CCM_CCR_360_PCIMODE (0x0008) /* PCI host/agent mode */
-#define CCM_CCR_360_PLLMODE (0x0010) /* PLL Mode */
-#define CCM_CCR_360_FBCONFIG(x) (((x)&0x0007)<<5) /* Flexbus/PCI port size configuration */
-#define CCM_CCR_360_PLLMULT3(x) (((x)&0x0007)) /* 3-Bit PLL Clock Mode */
-#define CCM_CCR_360_OSCMODE (0x0008) /* Oscillator Clock Mode */
-#define CCM_CCR_360_FBCONFIG_MASK (0x00E0)
-#define CCM_CCR_360_PLLMULT2_MASK (0x0003)
-#define CCM_CCR_360_PLLMULT3_MASK (0x0007)
-#define CCM_CCR_360_FBCONFIG_NM_NP_32 (0x0000)
-#define CCM_CCR_360_FBCONFIG_NM_NP_8 (0x0020)
-#define CCM_CCR_360_FBCONFIG_NM_NP_16 (0x0040)
-#define CCM_CCR_360_FBCONFIG_M_P_16 (0x0060)
-#define CCM_CCR_360_FBCONFIG_M_NP_32 (0x0080)
-#define CCM_CCR_360_FBCONFIG_M_NP_8 (0x00A0)
-#define CCM_CCR_360_FBCONFIG_M_NP_16 (0x00C0)
-#define CCM_CCR_360_FBCONFIG_M_P_8 (0x00E0)
-#define CCM_CCR_360_PLLMULT2_12X (0x0000)
-#define CCM_CCR_360_PLLMULT2_6X (0x0001)
-#define CCM_CCR_360_PLLMULT2_16X (0x0002)
-#define CCM_CCR_360_PLLMULT2_8X (0x0003)
-#define CCM_CCR_360_PLLMULT3_20X (0x0000)
-#define CCM_CCR_360_PLLMULT3_10X (0x0001)
-#define CCM_CCR_360_PLLMULT3_24X (0x0002)
-#define CCM_CCR_360_PLLMULT3_18X (0x0003)
-#define CCM_CCR_360_PLLMULT3_12X (0x0004)
-#define CCM_CCR_360_PLLMULT3_6X (0x0005)
-#define CCM_CCR_360_PLLMULT3_16X (0x0006)
-#define CCM_CCR_360_PLLMULT3_8X (0x0007)
-
-/* Bit definitions and macros for CCR_256 */
-#define CCM_CCR_256_PLLMULT3(x) (((x)&0x0007)) /* 3-Bit PLL clock mode */
-#define CCM_CCR_256_OSCMODE (0x0008) /* Oscillator clock mode */
-#define CCM_CCR_256_PLLMODE (0x0010) /* PLL Mode */
-#define CCM_CCR_256_FBCONFIG(x) (((x)&0x0007)<<5) /* Flexbus/PCI port size configuration */
-#define CCM_CCR_256_FBCONFIG_MASK (0x00E0)
-#define CCM_CCR_256_FBCONFIG_NM_32 (0x0000)
-#define CCM_CCR_256_FBCONFIG_NM_8 (0x0020)
-#define CCM_CCR_256_FBCONFIG_NM_16 (0x0040)
-#define CCM_CCR_256_FBCONFIG_M_32 (0x0080)
-#define CCM_CCR_256_FBCONFIG_M_8 (0x00A0)
-#define CCM_CCR_256_FBCONFIG_M_16 (0x00C0)
-#define CCM_CCR_256_PLLMULT3_MASK (0x0007)
-#define CCM_CCR_256_PLLMULT3_20X (0x0000)
-#define CCM_CCR_256_PLLMULT3_10X (0x0001)
-#define CCM_CCR_256_PLLMULT3_24X (0x0002)
-#define CCM_CCR_256_PLLMULT3_18X (0x0003)
-#define CCM_CCR_256_PLLMULT3_12X (0x0004)
-#define CCM_CCR_256_PLLMULT3_6X (0x0005)
-#define CCM_CCR_256_PLLMULT3_16X (0x0006)
-#define CCM_CCR_256_PLLMULT3_8X (0x0007)
-
-/* Bit definitions and macros for RCON_360 */
-#define CCM_RCON_360_PLLMULT(x) (((x)&0x0003)) /* PLL clock mode */
-#define CCM_RCON_360_PCISLEW (0x0004) /* PCI pad slew rate mode */
-#define CCM_RCON_360_PCIMODE (0x0008) /* PCI host/agent mode */
-#define CCM_RCON_360_PLLMODE (0x0010) /* PLL Mode */
-#define CCM_RCON_360_FBCONFIG(x) (((x)&0x0007)<<5) /* Flexbus/PCI port size configuration */
-
-/* Bit definitions and macros for RCON_256 */
-#define CCM_RCON_256_PLLMULT(x) (((x)&0x0007)) /* PLL clock mode */
-#define CCM_RCON_256_OSCMODE (0x0008) /* Oscillator clock mode */
-#define CCM_RCON_256_PLLMODE (0x0010) /* PLL Mode */
-#define CCM_RCON_256_FBCONFIG(x) (((x)&0x0007)<<5) /* Flexbus/PCI port size configuration */
-
-/* Bit definitions and macros for CIR */
-#define CCM_CIR_PRN(x) (((x)&0x003F)) /* Part revision number */
-#define CCM_CIR_PIN(x) (((x)&0x03FF)<<6) /* Part identification number */
-#define CCM_CIR_PIN_MASK (0xFFC0)
-#define CCM_CIR_PRN_MASK (0x003F)
-#define CCM_CIR_PIN_MCF54450 (0x4F<<6)
-#define CCM_CIR_PIN_MCF54451 (0x4D<<6)
-#define CCM_CIR_PIN_MCF54452 (0x4B<<6)
-#define CCM_CIR_PIN_MCF54453 (0x49<<6)
-#define CCM_CIR_PIN_MCF54454 (0x4A<<6)
-#define CCM_CIR_PIN_MCF54455 (0x48<<6)
-
-/* Bit definitions and macros for MISCCR */
-#define CCM_MISCCR_USBSRC (0x0001) /* USB clock source */
-#define CCM_MISCCR_USBOC (0x0002) /* USB VBUS over-current sense polarity */
-#define CCM_MISCCR_USBPUE (0x0004) /* USB transceiver pull-up enable */
-#define CCM_MISCCR_SSISRC (0x0010) /* SSI clock source */
-#define CCM_MISCCR_TIMDMA (0x0020) /* Timer DMA mux selection */
-#define CCM_MISCCR_SSIPUS (0x0040) /* SSI RXD/TXD pull select */
-#define CCM_MISCCR_SSIPUE (0x0080) /* SSI RXD/TXD pull enable */
-#define CCM_MISCCR_BMT(x) (((x)&0x0007)<<8) /* Bus monitor timing field */
-#define CCM_MISCCR_BME (0x0800) /* Bus monitor external enable bit */
-#define CCM_MISCCR_LIMP (0x1000) /* Limp mode enable */
-#define CCM_MISCCR_BMT_65536 (0)
-#define CCM_MISCCR_BMT_32768 (1)
-#define CCM_MISCCR_BMT_16384 (2)
-#define CCM_MISCCR_BMT_8192 (3)
-#define CCM_MISCCR_BMT_4096 (4)
-#define CCM_MISCCR_BMT_2048 (5)
-#define CCM_MISCCR_BMT_1024 (6)
-#define CCM_MISCCR_BMT_512 (7)
-#define CCM_MISCCR_SSIPUS_UP (1)
-#define CCM_MISCCR_SSIPUS_DOWN (0)
-#define CCM_MISCCR_TIMDMA_TIM (1)
-#define CCM_MISCCR_TIMDMA_SSI (0)
-#define CCM_MISCCR_SSISRC_CLKIN (0)
-#define CCM_MISCCR_SSISRC_PLL (1)
-#define CCM_MISCCR_USBOC_ACTHI (0)
-#define CCM_MISCCR_USBOV_ACTLO (1)
-#define CCM_MISCCR_USBSRC_CLKIN (0)
-#define CCM_MISCCR_USBSRC_PLL (1)
-
-/* Bit definitions and macros for CDR */
-#define CCM_CDR_SSIDIV(x) (((x)&0x00FF)) /* SSI oversampling clock divider */
-#define CCM_CDR_LPDIV(x) (((x)&0x000F)<<8) /* Low power clock divider */
-
-/* Bit definitions and macros for UOCSR */
-#define CCM_UOCSR_XPDE (0x0001) /* On-chip transceiver pull-down enable */
-#define CCM_UOCSR_UOMIE (0x0002) /* USB OTG misc interrupt enable */
-#define CCM_UOCSR_WKUP (0x0004) /* USB OTG controller wake-up event */
-#define CCM_UOCSR_PWRFLT (0x0008) /* VBUS power fault */
-#define CCM_UOCSR_SEND (0x0010) /* Session end */
-#define CCM_UOCSR_VVLD (0x0020) /* VBUS valid indicator */
-#define CCM_UOCSR_BVLD (0x0040) /* B-peripheral valid indicator */
-#define CCM_UOCSR_AVLD (0x0080) /* A-peripheral valid indicator */
-#define CCM_UOCSR_DPPU (0x0100) /* D+ pull-up for FS enabled (read-only) */
-#define CCM_UOCSR_DCR_VBUS (0x0200) /* VBUS discharge resistor enabled (read-only) */
-#define CCM_UOCSR_CRG_VBUS (0x0400) /* VBUS charge resistor enabled (read-only) */
-#define CCM_UOCSR_DMPD (0x1000) /* D- 15Kohm pull-down (read-only) */
-#define CCM_UOCSR_DPPD (0x2000) /* D+ 15Kohm pull-down (read-only) */
-
-/*********************************************************************
-* General Purpose I/O Module (GPIO)
-*********************************************************************/
-
-/* Bit definitions and macros for PAR_FEC */
-#define GPIO_PAR_FEC_FEC0(x) (((x)&0x07))
-#define GPIO_PAR_FEC_FEC1(x) (((x)&0x07)<<4)
-#define GPIO_PAR_FEC_FEC1_UNMASK (0x8F)
-#define GPIO_PAR_FEC_FEC1_MII (0x70)
-#define GPIO_PAR_FEC_FEC1_RMII_GPIO (0x30)
-#define GPIO_PAR_FEC_FEC1_RMII_ATA (0x20)
-#define GPIO_PAR_FEC_FEC1_ATA (0x10)
-#define GPIO_PAR_FEC_FEC1_GPIO (0x00)
-#define GPIO_PAR_FEC_FEC0_UNMASK (0xF8)
-#define GPIO_PAR_FEC_FEC0_MII (0x07)
-#define GPIO_PAR_FEC_FEC0_RMII_GPIO (0x03)
-#define GPIO_PAR_FEC_FEC0_RMII_ULPI (0x02)
-#define GPIO_PAR_FEC_FEC0_ULPI (0x01)
-#define GPIO_PAR_FEC_FEC0_GPIO (0x00)
-
-/* Bit definitions and macros for PAR_DMA */
-#define GPIO_PAR_DMA_DREQ0 (0x01)
-#define GPIO_PAR_DMA_DACK0(x) (((x)&0x03)<<2)
-#define GPIO_PAR_DMA_DREQ1(x) (((x)&0x03)<<4)
-#define GPIO_PAR_DMA_DACK1(x) (((x)&0x03)<<6)
-#define GPIO_PAR_DMA_DACK1_UNMASK (0x3F)
-#define GPIO_PAR_DMA_DACK1_DACK1 (0xC0)
-#define GPIO_PAR_DMA_DACK1_ULPI_DIR (0x40)
-#define GPIO_PAR_DMA_DACK1_GPIO (0x00)
-#define GPIO_PAR_DMA_DREQ1_UNMASK (0xCF)
-#define GPIO_PAR_DMA_DREQ1_DREQ1 (0x30)
-#define GPIO_PAR_DMA_DREQ1_USB_CLKIN (0x10)
-#define GPIO_PAR_DMA_DREQ1_GPIO (0x00)
-#define GPIO_PAR_DMA_DACK0_UNMASK (0xF3)
-#define GPIO_PAR_DMA_DACK0_DACK1 (0x0C)
-#define GPIO_PAR_DMA_DACK0_PCS3 (0x08)
-#define GPIO_PAR_DMA_DACK0_ULPI_DIR (0x04)
-#define GPIO_PAR_DMA_DACK0_GPIO (0x00)
-#define GPIO_PAR_DMA_DREQ0_DREQ0 (0x01)
-#define GPIO_PAR_DMA_DREQ0_GPIO (0x00)
-
-/* Bit definitions and macros for PAR_FBCTL */
-#define GPIO_PAR_FBCTL_TS(x) (((x)&0x03)<<3)
-#define GPIO_PAR_FBCTL_RW (0x20)
-#define GPIO_PAR_FBCTL_TA (0x40)
-#define GPIO_PAR_FBCTL_OE (0x80)
-#define GPIO_PAR_FBCTL_OE_OE (0x80)
-#define GPIO_PAR_FBCTL_OE_GPIO (0x00)
-#define GPIO_PAR_FBCTL_TA_TA (0x40)
-#define GPIO_PAR_FBCTL_TA_GPIO (0x00)
-#define GPIO_PAR_FBCTL_RW_RW (0x20)
-#define GPIO_PAR_FBCTL_RW_GPIO (0x00)
-#define GPIO_PAR_FBCTL_TS_UNMASK (0xE7)
-#define GPIO_PAR_FBCTL_TS_TS (0x18)
-#define GPIO_PAR_FBCTL_TS_ALE (0x10)
-#define GPIO_PAR_FBCTL_TS_TBST (0x08)
-#define GPIO_PAR_FBCTL_TS_GPIO (0x80)
-
-/* Bit definitions and macros for PAR_DSPI */
-#define GPIO_PAR_DSPI_SCK (0x01)
-#define GPIO_PAR_DSPI_SOUT (0x02)
-#define GPIO_PAR_DSPI_SIN (0x04)
-#define GPIO_PAR_DSPI_PCS0 (0x08)
-#define GPIO_PAR_DSPI_PCS1 (0x10)
-#define GPIO_PAR_DSPI_PCS2 (0x20)
-#define GPIO_PAR_DSPI_PCS5 (0x40)
-#define GPIO_PAR_DSPI_PCS5_PCS5 (0x40)
-#define GPIO_PAR_DSPI_PCS5_GPIO (0x00)
-#define GPIO_PAR_DSPI_PCS2_PCS2 (0x20)
-#define GPIO_PAR_DSPI_PCS2_GPIO (0x00)
-#define GPIO_PAR_DSPI_PCS1_PCS1 (0x10)
-#define GPIO_PAR_DSPI_PCS1_GPIO (0x00)
-#define GPIO_PAR_DSPI_PCS0_PCS0 (0x08)
-#define GPIO_PAR_DSPI_PCS0_GPIO (0x00)
-#define GPIO_PAR_DSPI_SIN_SIN (0x04)
-#define GPIO_PAR_DSPI_SIN_GPIO (0x00)
-#define GPIO_PAR_DSPI_SOUT_SOUT (0x02)
-#define GPIO_PAR_DSPI_SOUT_GPIO (0x00)
-#define GPIO_PAR_DSPI_SCK_SCK (0x01)
-#define GPIO_PAR_DSPI_SCK_GPIO (0x00)
-
-/* Bit definitions and macros for PAR_BE */
-#define GPIO_PAR_BE_BS0 (0x01)
-#define GPIO_PAR_BE_BS1 (0x04)
-#define GPIO_PAR_BE_BS2(x) (((x)&0x03)<<4)
-#define GPIO_PAR_BE_BS3(x) (((x)&0x03)<<6)
-#define GPIO_PAR_BE_BE3_UNMASK (0x3F)
-#define GPIO_PAR_BE_BE3_BE3 (0xC0)
-#define GPIO_PAR_BE_BE3_TSIZ1 (0x80)
-#define GPIO_PAR_BE_BE3_GPIO (0x00)
-#define GPIO_PAR_BE_BE2_UNMASK (0xCF)
-#define GPIO_PAR_BE_BE2_BE2 (0x30)
-#define GPIO_PAR_BE_BE2_TSIZ0 (0x20)
-#define GPIO_PAR_BE_BE2_GPIO (0x00)
-#define GPIO_PAR_BE_BE1_BE1 (0x04)
-#define GPIO_PAR_BE_BE1_GPIO (0x00)
-#define GPIO_PAR_BE_BE0_BE0 (0x01)
-#define GPIO_PAR_BE_BE0_GPIO (0x00)
-
-/* Bit definitions and macros for PAR_CS */
-#define GPIO_PAR_CS_CS1 (0x02)
-#define GPIO_PAR_CS_CS2 (0x04)
-#define GPIO_PAR_CS_CS3 (0x08)
-#define GPIO_PAR_CS_CS3_CS3 (0x08)
-#define GPIO_PAR_CS_CS3_GPIO (0x00)
-#define GPIO_PAR_CS_CS2_CS2 (0x04)
-#define GPIO_PAR_CS_CS2_GPIO (0x00)
-#define GPIO_PAR_CS_CS1_CS1 (0x02)
-#define GPIO_PAR_CS_CS1_GPIO (0x00)
-
-/* Bit definitions and macros for PAR_TIMER */
-#define GPIO_PAR_TIMER_T0IN(x) (((x)&0x03))
-#define GPIO_PAR_TIMER_T1IN(x) (((x)&0x03)<<2)
-#define GPIO_PAR_TIMER_T2IN(x) (((x)&0x03)<<4)
-#define GPIO_PAR_TIMER_T3IN(x) (((x)&0x03)<<6)
-#define GPIO_PAR_TIMER_T3IN_UNMASK (0x3F)
-#define GPIO_PAR_TIMER_T3IN_T3IN (0xC0)
-#define GPIO_PAR_TIMER_T3IN_T3OUT (0x80)
-#define GPIO_PAR_TIMER_T3IN_U2RXD (0x40)
-#define GPIO_PAR_TIMER_T3IN_GPIO (0x00)
-#define GPIO_PAR_TIMER_T2IN_UNMASK (0xCF)
-#define GPIO_PAR_TIMER_T2IN_T2IN (0x30)
-#define GPIO_PAR_TIMER_T2IN_T2OUT (0x20)
-#define GPIO_PAR_TIMER_T2IN_U2TXD (0x10)
-#define GPIO_PAR_TIMER_T2IN_GPIO (0x00)
-#define GPIO_PAR_TIMER_T1IN_UNMASK (0xF3)
-#define GPIO_PAR_TIMER_T1IN_T1IN (0x0C)
-#define GPIO_PAR_TIMER_T1IN_T1OUT (0x08)
-#define GPIO_PAR_TIMER_T1IN_U2CTS (0x04)
-#define GPIO_PAR_TIMER_T1IN_GPIO (0x00)
-#define GPIO_PAR_TIMER_T0IN_UNMASK (0xFC)
-#define GPIO_PAR_TIMER_T0IN_T0IN (0x03)
-#define GPIO_PAR_TIMER_T0IN_T0OUT (0x02)
-#define GPIO_PAR_TIMER_T0IN_U2RTS (0x01)
-#define GPIO_PAR_TIMER_T0IN_GPIO (0x00)
-
-/* Bit definitions and macros for PAR_USB */
-#define GPIO_PAR_USB_VBUSOC(x) (((x)&0x03))
-#define GPIO_PAR_USB_VBUSEN(x) (((x)&0x03)<<2)
-#define GPIO_PAR_USB_VBUSEN_UNMASK (0xF3)
-#define GPIO_PAR_USB_VBUSEN_VBUSEN (0x0C)
-#define GPIO_PAR_USB_VBUSEN_USBPULLUP (0x08)
-#define GPIO_PAR_USB_VBUSEN_ULPI_NXT (0x04)
-#define GPIO_PAR_USB_VBUSEN_GPIO (0x00)
-#define GPIO_PAR_USB_VBUSOC_UNMASK (0xFC)
-#define GPIO_PAR_USB_VBUSOC_VBUSOC (0x03)
-#define GPIO_PAR_USB_VBUSOC_ULPI_STP (0x01)
-#define GPIO_PAR_USB_VBUSOC_GPIO (0x00)
-
-/* Bit definitions and macros for PAR_UART */
-#define GPIO_PAR_UART_U0TXD (0x01)
-#define GPIO_PAR_UART_U0RXD (0x02)
-#define GPIO_PAR_UART_U0RTS (0x04)
-#define GPIO_PAR_UART_U0CTS (0x08)
-#define GPIO_PAR_UART_U1TXD (0x10)
-#define GPIO_PAR_UART_U1RXD (0x20)
-#define GPIO_PAR_UART_U1RTS (0x40)
-#define GPIO_PAR_UART_U1CTS (0x80)
-#define GPIO_PAR_UART_U1CTS_U1CTS (0x80)
-#define GPIO_PAR_UART_U1CTS_GPIO (0x00)
-#define GPIO_PAR_UART_U1RTS_U1RTS (0x40)
-#define GPIO_PAR_UART_U1RTS_GPIO (0x00)
-#define GPIO_PAR_UART_U1RXD_U1RXD (0x20)
-#define GPIO_PAR_UART_U1RXD_GPIO (0x00)
-#define GPIO_PAR_UART_U1TXD_U1TXD (0x10)
-#define GPIO_PAR_UART_U1TXD_GPIO (0x00)
-#define GPIO_PAR_UART_U0CTS_U0CTS (0x08)
-#define GPIO_PAR_UART_U0CTS_GPIO (0x00)
-#define GPIO_PAR_UART_U0RTS_U0RTS (0x04)
-#define GPIO_PAR_UART_U0RTS_GPIO (0x00)
-#define GPIO_PAR_UART_U0RXD_U0RXD (0x02)
-#define GPIO_PAR_UART_U0RXD_GPIO (0x00)
-#define GPIO_PAR_UART_U0TXD_U0TXD (0x01)
-#define GPIO_PAR_UART_U0TXD_GPIO (0x00)
-
-/* Bit definitions and macros for PAR_FECI2C */
-#define GPIO_PAR_FECI2C_SDA(x) (((x)&0x0003))
-#define GPIO_PAR_FECI2C_SCL(x) (((x)&0x0003)<<2)
-#define GPIO_PAR_FECI2C_MDIO0 (0x0010)
-#define GPIO_PAR_FECI2C_MDC0 (0x0040)
-#define GPIO_PAR_FECI2C_MDIO1(x) (((x)&0x0003)<<8)
-#define GPIO_PAR_FECI2C_MDC1(x) (((x)&0x0003)<<10)
-#define GPIO_PAR_FECI2C_MDC1_UNMASK (0xF3FF)
-#define GPIO_PAR_FECI2C_MDC1_MDC1 (0x0C00)
-#define GPIO_PAR_FECI2C_MDC1_ATA_DIOR (0x0800)
-#define GPIO_PAR_FECI2C_MDC1_GPIO (0x0000)
-#define GPIO_PAR_FECI2C_MDIO1_UNMASK (0xFCFF)
-#define GPIO_PAR_FECI2C_MDIO1_MDIO1 (0x0300)
-#define GPIO_PAR_FECI2C_MDIO1_ATA_DIOW (0x0200)
-#define GPIO_PAR_FECI2C_MDIO1_GPIO (0x0000)
-#define GPIO_PAR_FECI2C_MDC0_MDC0 (0x0040)
-#define GPIO_PAR_FECI2C_MDC0_GPIO (0x0000)
-#define GPIO_PAR_FECI2C_MDIO0_MDIO0 (0x0010)
-#define GPIO_PAR_FECI2C_MDIO0_GPIO (0x0000)
-#define GPIO_PAR_FECI2C_SCL_UNMASK (0xFFF3)
-#define GPIO_PAR_FECI2C_SCL_SCL (0x000C)
-#define GPIO_PAR_FECI2C_SCL_U2TXD (0x0004)
-#define GPIO_PAR_FECI2C_SCL_GPIO (0x0000)
-#define GPIO_PAR_FECI2C_SDA_UNMASK (0xFFFC)
-#define GPIO_PAR_FECI2C_SDA_SDA (0x0003)
-#define GPIO_PAR_FECI2C_SDA_U2RXD (0x0001)
-#define GPIO_PAR_FECI2C_SDA_GPIO (0x0000)
-
-/* Bit definitions and macros for PAR_SSI */
-#define GPIO_PAR_SSI_MCLK (0x0001)
-#define GPIO_PAR_SSI_STXD(x) (((x)&0x0003)<<2)
-#define GPIO_PAR_SSI_SRXD(x) (((x)&0x0003)<<4)
-#define GPIO_PAR_SSI_FS(x) (((x)&0x0003)<<6)
-#define GPIO_PAR_SSI_BCLK(x) (((x)&0x0003)<<8)
-#define GPIO_PAR_SSI_BCLK_UNMASK (0xFCFF)
-#define GPIO_PAR_SSI_BCLK_BCLK (0x0300)
-#define GPIO_PAR_SSI_BCLK_U1CTS (0x0200)
-#define GPIO_PAR_SSI_BCLK_GPIO (0x0000)
-#define GPIO_PAR_SSI_FS_UNMASK (0xFF3F)
-#define GPIO_PAR_SSI_FS_FS (0x00C0)
-#define GPIO_PAR_SSI_FS_U1RTS (0x0080)
-#define GPIO_PAR_SSI_FS_GPIO (0x0000)
-#define GPIO_PAR_SSI_SRXD_UNMASK (0xFFCF)
-#define GPIO_PAR_SSI_SRXD_SRXD (0x0030)
-#define GPIO_PAR_SSI_SRXD_U1RXD (0x0020)
-#define GPIO_PAR_SSI_SRXD_GPIO (0x0000)
-#define GPIO_PAR_SSI_STXD_UNMASK (0xFFF3)
-#define GPIO_PAR_SSI_STXD_STXD (0x000C)
-#define GPIO_PAR_SSI_STXD_U1TXD (0x0008)
-#define GPIO_PAR_SSI_STXD_GPIO (0x0000)
-#define GPIO_PAR_SSI_MCLK_MCLK (0x0001)
-#define GPIO_PAR_SSI_MCLK_GPIO (0x0000)
-
-/* Bit definitions and macros for PAR_ATA */
-#define GPIO_PAR_ATA_IORDY (0x0001)
-#define GPIO_PAR_ATA_DMARQ (0x0002)
-#define GPIO_PAR_ATA_RESET (0x0004)
-#define GPIO_PAR_ATA_DA0 (0x0020)
-#define GPIO_PAR_ATA_DA1 (0x0040)
-#define GPIO_PAR_ATA_DA2 (0x0080)
-#define GPIO_PAR_ATA_CS0 (0x0100)
-#define GPIO_PAR_ATA_CS1 (0x0200)
-#define GPIO_PAR_ATA_BUFEN (0x0400)
-#define GPIO_PAR_ATA_BUFEN_BUFEN (0x0400)
-#define GPIO_PAR_ATA_BUFEN_GPIO (0x0000)
-#define GPIO_PAR_ATA_CS1_CS1 (0x0200)
-#define GPIO_PAR_ATA_CS1_GPIO (0x0000)
-#define GPIO_PAR_ATA_CS0_CS0 (0x0100)
-#define GPIO_PAR_ATA_CS0_GPIO (0x0000)
-#define GPIO_PAR_ATA_DA2_DA2 (0x0080)
-#define GPIO_PAR_ATA_DA2_GPIO (0x0000)
-#define GPIO_PAR_ATA_DA1_DA1 (0x0040)
-#define GPIO_PAR_ATA_DA1_GPIO (0x0000)
-#define GPIO_PAR_ATA_DA0_DA0 (0x0020)
-#define GPIO_PAR_ATA_DA0_GPIO (0x0000)
-#define GPIO_PAR_ATA_RESET_RESET (0x0004)
-#define GPIO_PAR_ATA_RESET_GPIO (0x0000)
-#define GPIO_PAR_ATA_DMARQ_DMARQ (0x0002)
-#define GPIO_PAR_ATA_DMARQ_GPIO (0x0000)
-#define GPIO_PAR_ATA_IORDY_IORDY (0x0001)
-#define GPIO_PAR_ATA_IORDY_GPIO (0x0000)
-
-/* Bit definitions and macros for PAR_IRQ */
-#define GPIO_PAR_IRQ_IRQ1 (0x02)
-#define GPIO_PAR_IRQ_IRQ4 (0x10)
-#define GPIO_PAR_IRQ_IRQ4_IRQ4 (0x10)
-#define GPIO_PAR_IRQ_IRQ4_GPIO (0x00)
-#define GPIO_PAR_IRQ_IRQ1_IRQ1 (0x02)
-#define GPIO_PAR_IRQ_IRQ1_GPIO (0x00)
-
-/* Bit definitions and macros for PAR_PCI */
-#define GPIO_PAR_PCI_REQ0 (0x0001)
-#define GPIO_PAR_PCI_REQ1 (0x0004)
-#define GPIO_PAR_PCI_REQ2 (0x0010)
-#define GPIO_PAR_PCI_REQ3(x) (((x)&0x0003)<<6)
-#define GPIO_PAR_PCI_GNT0 (0x0100)
-#define GPIO_PAR_PCI_GNT1 (0x0400)
-#define GPIO_PAR_PCI_GNT2 (0x1000)
-#define GPIO_PAR_PCI_GNT3(x) (((x)&0x0003)<<14)
-#define GPIO_PAR_PCI_GNT3_UNMASK (0x3FFF)
-#define GPIO_PAR_PCI_GNT3_GNT3 (0xC000)
-#define GPIO_PAR_PCI_GNT3_ATA_DMACK (0x8000)
-#define GPIO_PAR_PCI_GNT3_GPIO (0x0000)
-#define GPIO_PAR_PCI_GNT2_GNT2 (0x1000)
-#define GPIO_PAR_PCI_GNT2_GPIO (0x0000)
-#define GPIO_PAR_PCI_GNT1_GNT1 (0x0400)
-#define GPIO_PAR_PCI_GNT1_GPIO (0x0000)
-#define GPIO_PAR_PCI_GNT0_GNT0 (0x0100)
-#define GPIO_PAR_PCI_GNT0_GPIO (0x0000)
-#define GPIO_PAR_PCI_REQ3_UNMASK (0xFF3F)
-#define GPIO_PAR_PCI_REQ3_REQ3 (0x00C0)
-#define GPIO_PAR_PCI_REQ3_ATA_INTRQ (0x0080)
-#define GPIO_PAR_PCI_REQ3_GPIO (0x0000)
-#define GPIO_PAR_PCI_REQ2_REQ2 (0x0010)
-#define GPIO_PAR_PCI_REQ2_GPIO (0x0000)
-#define GPIO_PAR_PCI_REQ1_REQ1 (0x0040)
-#define GPIO_PAR_PCI_REQ1_GPIO (0x0000)
-#define GPIO_PAR_PCI_REQ0_REQ0 (0x0001)
-#define GPIO_PAR_PCI_REQ0_GPIO (0x0000)
-
-/* Bit definitions and macros for MSCR_SDRAM */
-#define GPIO_MSCR_SDRAM_SDCTL(x) (((x)&0x03))
-#define GPIO_MSCR_SDRAM_SDCLK(x) (((x)&0x03)<<2)
-#define GPIO_MSCR_SDRAM_SDDQS(x) (((x)&0x03)<<4)
-#define GPIO_MSCR_SDRAM_SDDATA(x) (((x)&0x03)<<6)
-#define GPIO_MSCR_SDRAM_SDDATA_UNMASK (0x3F)
-#define GPIO_MSCR_SDRAM_SDDATA_DDR1 (0xC0)
-#define GPIO_MSCR_SDRAM_SDDATA_DDR2 (0x80)
-#define GPIO_MSCR_SDRAM_SDDATA_FS_LPDDR (0x40)
-#define GPIO_MSCR_SDRAM_SDDATA_HS_LPDDR (0x00)
-#define GPIO_MSCR_SDRAM_SDDQS_UNMASK (0xCF)
-#define GPIO_MSCR_SDRAM_SDDQS_DDR1 (0x30)
-#define GPIO_MSCR_SDRAM_SDDQS_DDR2 (0x20)
-#define GPIO_MSCR_SDRAM_SDDQS_FS_LPDDR (0x10)
-#define GPIO_MSCR_SDRAM_SDDQS_HS_LPDDR (0x00)
-#define GPIO_MSCR_SDRAM_SDCLK_UNMASK (0xF3)
-#define GPIO_MSCR_SDRAM_SDCLK_DDR1 (0x0C)
-#define GPIO_MSCR_SDRAM_SDCLK_DDR2 (0x08)
-#define GPIO_MSCR_SDRAM_SDCLK_FS_LPDDR (0x04)
-#define GPIO_MSCR_SDRAM_SDCLK_HS_LPDDR (0x00)
-#define GPIO_MSCR_SDRAM_SDCTL_UNMASK (0xFC)
-#define GPIO_MSCR_SDRAM_SDCTL_DDR1 (0x03)
-#define GPIO_MSCR_SDRAM_SDCTL_DDR2 (0x02)
-#define GPIO_MSCR_SDRAM_SDCTL_FS_LPDDR (0x01)
-#define GPIO_MSCR_SDRAM_SDCTL_HS_LPDDR (0x00)
-
-/* Bit definitions and macros for MSCR_PCI */
-#define GPIO_MSCR_PCI_PCI (0x01)
-#define GPIO_MSCR_PCI_PCI_HI_66MHZ (0x01)
-#define GPIO_MSCR_PCI_PCI_LO_33MHZ (0x00)
-
-/* Bit definitions and macros for DSCR_I2C */
-#define GPIO_DSCR_I2C_I2C(x) (((x)&0x03))
-#define GPIO_DSCR_I2C_I2C_LOAD_50PF (0x03)
-#define GPIO_DSCR_I2C_I2C_LOAD_30PF (0x02)
-#define GPIO_DSCR_I2C_I2C_LOAD_20PF (0x01)
-#define GPIO_DSCR_I2C_I2C_LOAD_10PF (0x00)
-
-/* Bit definitions and macros for DSCR_FLEXBUS */
-#define GPIO_DSCR_FLEXBUS_FBADL(x) (((x)&0x03))
-#define GPIO_DSCR_FLEXBUS_FBADH(x) (((x)&0x03)<<2)
-#define GPIO_DSCR_FLEXBUS_FBCTL(x) (((x)&0x03)<<4)
-#define GPIO_DSCR_FLEXBUS_FBCLK(x) (((x)&0x03)<<6)
-#define GPIO_DSCR_FLEXBUS_FBCLK_LOAD_50PF (0xC0)
-#define GPIO_DSCR_FLEXBUS_FBCLK_LOAD_30PF (0x80)
-#define GPIO_DSCR_FLEXBUS_FBCLK_LOAD_20PF (0x40)
-#define GPIO_DSCR_FLEXBUS_FBCLK_LOAD_10PF (0x00)
-#define GPIO_DSCR_FLEXBUS_FBCTL_LOAD_50PF (0x30)
-#define GPIO_DSCR_FLEXBUS_FBCTL_LOAD_30PF (0x20)
-#define GPIO_DSCR_FLEXBUS_FBCTL_LOAD_20PF (0x10)
-#define GPIO_DSCR_FLEXBUS_FBCTL_LOAD_10PF (0x00)
-#define GPIO_DSCR_FLEXBUS_FBADH_LOAD_50PF (0x0C)
-#define GPIO_DSCR_FLEXBUS_FBADH_LOAD_30PF (0x08)
-#define GPIO_DSCR_FLEXBUS_FBADH_LOAD_20PF (0x04)
-#define GPIO_DSCR_FLEXBUS_FBADH_LOAD_10PF (0x00)
-#define GPIO_DSCR_FLEXBUS_FBADL_LOAD_50PF (0x03)
-#define GPIO_DSCR_FLEXBUS_FBADL_LOAD_30PF (0x02)
-#define GPIO_DSCR_FLEXBUS_FBADL_LOAD_20PF (0x01)
-#define GPIO_DSCR_FLEXBUS_FBADL_LOAD_10PF (0x00)
-
-/* Bit definitions and macros for DSCR_FEC */
-#define GPIO_DSCR_FEC_FEC0(x) (((x)&0x03))
-#define GPIO_DSCR_FEC_FEC1(x) (((x)&0x03)<<2)
-#define GPIO_DSCR_FEC_FEC1_LOAD_50PF (0x0C)
-#define GPIO_DSCR_FEC_FEC1_LOAD_30PF (0x08)
-#define GPIO_DSCR_FEC_FEC1_LOAD_20PF (0x04)
-#define GPIO_DSCR_FEC_FEC1_LOAD_10PF (0x00)
-#define GPIO_DSCR_FEC_FEC0_LOAD_50PF (0x03)
-#define GPIO_DSCR_FEC_FEC0_LOAD_30PF (0x02)
-#define GPIO_DSCR_FEC_FEC0_LOAD_20PF (0x01)
-#define GPIO_DSCR_FEC_FEC0_LOAD_10PF (0x00)
-
-/* Bit definitions and macros for DSCR_UART */
-#define GPIO_DSCR_UART_UART0(x) (((x)&0x03))
-#define GPIO_DSCR_UART_UART1(x) (((x)&0x03)<<2)
-#define GPIO_DSCR_UART_UART1_LOAD_50PF (0x0C)
-#define GPIO_DSCR_UART_UART1_LOAD_30PF (0x08)
-#define GPIO_DSCR_UART_UART1_LOAD_20PF (0x04)
-#define GPIO_DSCR_UART_UART1_LOAD_10PF (0x00)
-#define GPIO_DSCR_UART_UART0_LOAD_50PF (0x03)
-#define GPIO_DSCR_UART_UART0_LOAD_30PF (0x02)
-#define GPIO_DSCR_UART_UART0_LOAD_20PF (0x01)
-#define GPIO_DSCR_UART_UART0_LOAD_10PF (0x00)
-
-/* Bit definitions and macros for DSCR_DSPI */
-#define GPIO_DSCR_DSPI_DSPI(x) (((x)&0x03))
-#define GPIO_DSCR_DSPI_DSPI_LOAD_50PF (0x03)
-#define GPIO_DSCR_DSPI_DSPI_LOAD_30PF (0x02)
-#define GPIO_DSCR_DSPI_DSPI_LOAD_20PF (0x01)
-#define GPIO_DSCR_DSPI_DSPI_LOAD_10PF (0x00)
-
-/* Bit definitions and macros for DSCR_TIMER */
-#define GPIO_DSCR_TIMER_TIMER(x) (((x)&0x03))
-#define GPIO_DSCR_TIMER_TIMER_LOAD_50PF (0x03)
-#define GPIO_DSCR_TIMER_TIMER_LOAD_30PF (0x02)
-#define GPIO_DSCR_TIMER_TIMER_LOAD_20PF (0x01)
-#define GPIO_DSCR_TIMER_TIMER_LOAD_10PF (0x00)
-
-/* Bit definitions and macros for DSCR_SSI */
-#define GPIO_DSCR_SSI_SSI(x) (((x)&0x03))
-#define GPIO_DSCR_SSI_SSI_LOAD_50PF (0x03)
-#define GPIO_DSCR_SSI_SSI_LOAD_30PF (0x02)
-#define GPIO_DSCR_SSI_SSI_LOAD_20PF (0x01)
-#define GPIO_DSCR_SSI_SSI_LOAD_10PF (0x00)
-
-/* Bit definitions and macros for DSCR_DMA */
-#define GPIO_DSCR_DMA_DMA(x) (((x)&0x03))
-#define GPIO_DSCR_DMA_DMA_LOAD_50PF (0x03)
-#define GPIO_DSCR_DMA_DMA_LOAD_30PF (0x02)
-#define GPIO_DSCR_DMA_DMA_LOAD_20PF (0x01)
-#define GPIO_DSCR_DMA_DMA_LOAD_10PF (0x00)
-
-/* Bit definitions and macros for DSCR_DEBUG */
-#define GPIO_DSCR_DEBUG_DEBUG(x) (((x)&0x03))
-#define GPIO_DSCR_DEBUG_DEBUG_LOAD_50PF (0x03)
-#define GPIO_DSCR_DEBUG_DEBUG_LOAD_30PF (0x02)
-#define GPIO_DSCR_DEBUG_DEBUG_LOAD_20PF (0x01)
-#define GPIO_DSCR_DEBUG_DEBUG_LOAD_10PF (0x00)
-
-/* Bit definitions and macros for DSCR_RESET */
-#define GPIO_DSCR_RESET_RESET(x) (((x)&0x03))
-#define GPIO_DSCR_RESET_RESET_LOAD_50PF (0x03)
-#define GPIO_DSCR_RESET_RESET_LOAD_30PF (0x02)
-#define GPIO_DSCR_RESET_RESET_LOAD_20PF (0x01)
-#define GPIO_DSCR_RESET_RESET_LOAD_10PF (0x00)
-
-/* Bit definitions and macros for DSCR_IRQ */
-#define GPIO_DSCR_IRQ_IRQ(x) (((x)&0x03))
-#define GPIO_DSCR_IRQ_IRQ_LOAD_50PF (0x03)
-#define GPIO_DSCR_IRQ_IRQ_LOAD_30PF (0x02)
-#define GPIO_DSCR_IRQ_IRQ_LOAD_20PF (0x01)
-#define GPIO_DSCR_IRQ_IRQ_LOAD_10PF (0x00)
-
-/* Bit definitions and macros for DSCR_USB */
-#define GPIO_DSCR_USB_USB(x) (((x)&0x03))
-#define GPIO_DSCR_USB_USB_LOAD_50PF (0x03)
-#define GPIO_DSCR_USB_USB_LOAD_30PF (0x02)
-#define GPIO_DSCR_USB_USB_LOAD_20PF (0x01)
-#define GPIO_DSCR_USB_USB_LOAD_10PF (0x00)
-
-/* Bit definitions and macros for DSCR_ATA */
-#define GPIO_DSCR_ATA_ATA(x) (((x)&0x03))
-#define GPIO_DSCR_ATA_ATA_LOAD_50PF (0x03)
-#define GPIO_DSCR_ATA_ATA_LOAD_30PF (0x02)
-#define GPIO_DSCR_ATA_ATA_LOAD_20PF (0x01)
-#define GPIO_DSCR_ATA_ATA_LOAD_10PF (0x00)
-
-/*********************************************************************
-* SDRAM Controller (SDRAMC)
-*********************************************************************/
-
-/* Bit definitions and macros for SDMR */
-#define SDRAMC_SDMR_DDR2_AD(x) (((x)&0x00003FFF)) /* Address for DDR2 */
-#define SDRAMC_SDMR_CMD (0x00010000) /* Command */
-#define SDRAMC_SDMR_AD(x) (((x)&0x00000FFF)<<18) /* Address */
-#define SDRAMC_SDMR_BK(x) (((x)&0x00000003)<<30) /* Bank Address */
-#define SDRAMC_SDMR_BK_LMR (0x00000000)
-#define SDRAMC_SDMR_BK_LEMR (0x40000000)
-
-/* Bit definitions and macros for SDCR */
-#define SDRAMC_SDCR_DPD (0x00000001) /* Deep Power-Down Mode */
-#define SDRAMC_SDCR_IPALL (0x00000002) /* Initiate Precharge All */
-#define SDRAMC_SDCR_IREF (0x00000004) /* Initiate Refresh */
-#define SDRAMC_SDCR_DQS_OE(x) (((x)&0x00000003)<<10) /* DQS Output Enable */
-#define SDRAMC_SDCR_MEM_PS (0x00002000) /* Data Port Size */
-#define SDRAMC_SDCR_REF_CNT(x) (((x)&0x0000003F)<<16) /* Periodic Refresh Counter */
-#define SDRAMC_SDCR_OE_RULE (0x00400000) /* Drive Rule Selection */
-#define SDRAMC_SDCR_ADDR_MUX(x) (((x)&0x00000003)<<24) /* Internal Address Mux Select */
-#define SDRAMC_SDCR_DDR2_MODE (0x08000000) /* DDR2 Mode Select */
-#define SDRAMC_SDCR_REF_EN (0x10000000) /* Refresh Enable */
-#define SDRAMC_SDCR_DDR_MODE (0x20000000) /* DDR Mode Select */
-#define SDRAMC_SDCR_CKE (0x40000000) /* Clock Enable */
-#define SDRAMC_SDCR_MODE_EN (0x80000000) /* SDRAM Mode Register Programming Enable */
-#define SDRAMC_SDCR_DQS_OE_BOTH (0x00000C000)
-
-/* Bit definitions and macros for SDCFG1 */
-#define SDRAMC_SDCFG1_WT_LAT(x) (((x)&0x00000007)<<4) /* Write Latency */
-#define SDRAMC_SDCFG1_REF2ACT(x) (((x)&0x0000000F)<<8) /* Refresh to active delay */
-#define SDRAMC_SDCFG1_PRE2ACT(x) (((x)&0x00000007)<<12) /* Precharge to active delay */
-#define SDRAMC_SDCFG1_ACT2RW(x) (((x)&0x00000007)<<16) /* Active to read/write delay */
-#define SDRAMC_SDCFG1_RD_LAT(x) (((x)&0x0000000F)<<20) /* Read CAS Latency */
-#define SDRAMC_SDCFG1_SWT2RWP(x) (((x)&0x00000007)<<24) /* Single write to read/write/precharge delay */
-#define SDRAMC_SDCFG1_SRD2RWP(x) (((x)&0x0000000F)<<28) /* Single read to read/write/precharge delay */
-
-/* Bit definitions and macros for SDCFG2 */
-#define SDRAMC_SDCFG2_BL(x) (((x)&0x0000000F)<<16) /* Burst Length */
-#define SDRAMC_SDCFG2_BRD2W(x) (((x)&0x0000000F)<<20) /* Burst read to write delay */
-#define SDRAMC_SDCFG2_BWT2RWP(x) (((x)&0x0000000F)<<24) /* Burst write to read/write/precharge delay */
-#define SDRAMC_SDCFG2_BRD2RP(x) (((x)&0x0000000F)<<28) /* Burst read to read/precharge delay */
-
-/* Bit definitions and macros for SDCS group */
-#define SDRAMC_SDCS_CSSZ(x) (((x)&0x0000001F)) /* Chip-Select Size */
-#define SDRAMC_SDCS_CSBA(x) (((x)&0x00000FFF)<<20) /* Chip-Select Base Address */
-#define SDRAMC_SDCS_BA(x) ((x)&0xFFF00000)
-#define SDRAMC_SDCS_CSSZ_DISABLE (0x00000000)
-#define SDRAMC_SDCS_CSSZ_1MBYTE (0x00000013)
-#define SDRAMC_SDCS_CSSZ_2MBYTE (0x00000014)
-#define SDRAMC_SDCS_CSSZ_4MBYTE (0x00000015)
-#define SDRAMC_SDCS_CSSZ_8MBYTE (0x00000016)
-#define SDRAMC_SDCS_CSSZ_16MBYTE (0x00000017)
-#define SDRAMC_SDCS_CSSZ_32MBYTE (0x00000018)
-#define SDRAMC_SDCS_CSSZ_64MBYTE (0x00000019)
-#define SDRAMC_SDCS_CSSZ_128MBYTE (0x0000001A)
-#define SDRAMC_SDCS_CSSZ_256MBYTE (0x0000001B)
-#define SDRAMC_SDCS_CSSZ_512MBYTE (0x0000001C)
-#define SDRAMC_SDCS_CSSZ_1GBYTE (0x0000001D)
-#define SDRAMC_SDCS_CSSZ_2GBYTE (0x0000001E)
-#define SDRAMC_SDCS_CSSZ_4GBYTE (0x0000001F)
-
-/*********************************************************************
-* Phase Locked Loop (PLL)
-*********************************************************************/
-
-/* Bit definitions and macros for PCR */
-#define PLL_PCR_OUTDIV1(x) (((x)&0x0000000F)) /* Output divider for CPU clock frequency */
-#define PLL_PCR_OUTDIV2(x) (((x)&0x0000000F)<<4) /* Output divider for internal bus clock frequency */
-#define PLL_PCR_OUTDIV3(x) (((x)&0x0000000F)<<8) /* Output divider for Flexbus clock frequency */
-#define PLL_PCR_OUTDIV4(x) (((x)&0x0000000F)<<12) /* Output divider for PCI clock frequency */
-#define PLL_PCR_OUTDIV5(x) (((x)&0x0000000F)<<16) /* Output divider for USB clock frequency */
-#define PLL_PCR_PFDR(x) (((x)&0x000000FF)<<24) /* Feedback divider for VCO frequency */
-#define PLL_PCR_PFDR_MASK (0x000F0000)
-#define PLL_PCR_OUTDIV5_MASK (0x000F0000)
-#define PLL_PCR_OUTDIV4_MASK (0x0000F000)
-#define PLL_PCR_OUTDIV3_MASK (0x00000F00)
-#define PLL_PCR_OUTDIV2_MASK (0x000000F0)
-#define PLL_PCR_OUTDIV1_MASK (0x0000000F)
-
-/* Bit definitions and macros for PSR */
-#define PLL_PSR_LOCKS (0x00000001) /* PLL lost lock - sticky */
-#define PLL_PSR_LOCK (0x00000002) /* PLL lock status */
-#define PLL_PSR_LOLIRQ (0x00000004) /* PLL loss-of-lock interrupt enable */
-#define PLL_PSR_LOLRE (0x00000008) /* PLL loss-of-lock reset enable */
-
-/*********************************************************************
-* PCI
-*********************************************************************/
-
-/* Bit definitions and macros for SCR */
-#define PCI_SCR_PE (0x80000000) /* Parity Error detected */
-#define PCI_SCR_SE (0x40000000) /* System error signalled */
-#define PCI_SCR_MA (0x20000000) /* Master aboart received */
-#define PCI_SCR_TR (0x10000000) /* Target abort received */
-#define PCI_SCR_TS (0x08000000) /* Target abort signalled */
-#define PCI_SCR_DT (0x06000000) /* PCI_DEVSEL timing */
-#define PCI_SCR_DP (0x01000000) /* Master data parity err */
-#define PCI_SCR_FC (0x00800000) /* Fast back-to-back */
-#define PCI_SCR_R (0x00400000) /* Reserved */
-#define PCI_SCR_66M (0x00200000) /* 66Mhz */
-#define PCI_SCR_C (0x00100000) /* Capabilities list */
-#define PCI_SCR_F (0x00000200) /* Fast back-to-back enable */
-#define PCI_SCR_S (0x00000100) /* SERR enable */
-#define PCI_SCR_ST (0x00000080) /* Addr and Data stepping */
-#define PCI_SCR_PER (0x00000040) /* Parity error response */
-#define PCI_SCR_V (0x00000020) /* VGA palette snoop enable */
-#define PCI_SCR_MW (0x00000010) /* Memory write and invalidate enable */
-#define PCI_SCR_SP (0x00000008) /* Special cycle monitor or ignore */
-#define PCI_SCR_B (0x00000004) /* Bus master enable */
-#define PCI_SCR_M (0x00000002) /* Memory access control */
-#define PCI_SCR_IO (0x00000001) /* I/O access control */
-
-#define PCI_CR1_BIST(x) ((x & 0xFF) << 24) /* Built in self test */
-#define PCI_CR1_HDR(x) ((x & 0xFF) << 16) /* Header type */
-#define PCI_CR1_LTMR(x) ((x & 0xF8) << 8) /* Latency timer */
-#define PCI_CR1_CLS(x) (x & 0x0F) /* Cache line size */
-
-#define PCI_BAR_BAR0(x) (x & 0xFFFC0000)
-#define PCI_BAR_BAR1(x) (x & 0xFFF00000)
-#define PCI_BAR_BAR2(x) (x & 0xFFC00000)
-#define PCI_BAR_BAR3(x) (x & 0xFF000000)
-#define PCI_BAR_BAR4(x) (x & 0xF8000000)
-#define PCI_BAR_BAR5(x) (x & 0xE0000000)
-#define PCI_BAR_PREF (0x00000004) /* Prefetchable access */
-#define PCI_BAR_RANGE (0x00000002) /* Fixed to 00 */
-#define PCI_BAR_IO_M (0x00000001) /* IO / memory space */
-
-#define PCI_CR2_MAXLAT(x) ((x & 0xFF) << 24) /* Maximum latency */
-#define PCI_CR2_MINGNT(x) ((x & 0xFF) << 16) /* Minimum grant */
-#define PCI_CR2_INTPIN(x) ((x & 0xFF) << 8) /* Interrupt Pin */
-#define PCI_CR2_INTLIN(x) (x & 0xFF) /* Interrupt Line */
-
-#define PCI_GSCR_DRD (0x80000000) /* Delayed read discarded */
-#define PCI_GSCR_PE (0x20000000) /* PCI_PERR detected */
-#define PCI_GSCR_SE (0x10000000) /* SERR detected */
-#define PCI_GSCR_ER (0x08000000) /* Error response detected */
-#define PCI_GSCR_DRDE (0x00008000) /* Delayed read discarded enable */
-#define PCI_GSCR_PEE (0x00002000) /* PERR detected interrupt enable */
-#define PCI_GSCR_SEE (0x00001000) /* SERR detected interrupt enable */
-#define PCI_GSCR_PR (0x00000001) /* PCI reset */
-
-#define PCI_TCR1_LD (0x01000000) /* Latency rule disable */
-#define PCI_TCR1_PID (0x00020000) /* Prefetch invalidate and disable */
-#define PCI_TCR1_P (0x00010000) /* Prefetch reads */
-#define PCI_TCR1_WCD (0x00000100) /* Write combine disable */
-
-#define PCI_TCR2_B5E (0x00002000) /* */
-#define PCI_TCR2_B4E (0x00001000) /* */
-#define PCI_TCR2_B3E (0x00000800) /* */
-#define PCI_TCR2_B2E (0x00000400) /* */
-#define PCI_TCR2_B1E (0x00000200) /* */
-#define PCI_TCR2_B0E (0x00000100) /* */
-#define PCI_TCR2_CR (0x00000001) /* */
-
-#define PCI_TBATR_BAT(x) ((x & 0xFFF) << 20)
-#define PCI_TBATR_EN (0x00000001) /* Enable */
-
-#define PCI_IWCR_W0C_IO (0x08000000) /* Windows Maps to PCI I/O */
-#define PCI_IWCR_W0C_PRC_RDMUL (0x04000000) /* PCI Memory Read multiple */
-#define PCI_IWCR_W0C_PRC_RDLN (0x02000000) /* PCI Memory Read line */
-#define PCI_IWCR_W0C_PRC_RD (0x00000000) /* PCI Memory Read */
-#define PCI_IWCR_W0C_EN (0x01000000) /* Enable - Register initialize */
-#define PCI_IWCR_W1C_IO (0x00080000) /* Windows Maps to PCI I/O */
-#define PCI_IWCR_W1C_PRC_RDMUL (0x00040000) /* PCI Memory Read multiple */
-#define PCI_IWCR_W1C_PRC_RDLN (0x00020000) /* PCI Memory Read line */
-#define PCI_IWCR_W1C_PRC_RD (0x00000000) /* PCI Memory Read */
-#define PCI_IWCR_W1C_EN (0x00010000) /* Enable - Register initialize */
-#define PCI_IWCR_W2C_IO (0x00000800) /* Windows Maps to PCI I/O */
-#define PCI_IWCR_W2C_PRC_RDMUL (0x00000400) /* PCI Memory Read multiple */
-#define PCI_IWCR_W2C_PRC_RDLN (0x00000200) /* PCI Memory Read line */
-#define PCI_IWCR_W2C_PRC_RD (0x00000000) /* PCI Memory Read */
-#define PCI_IWCR_W2C_EN (0x00000100) /* Enable - Register initialize */
-
-#define PCI_ICR_REE (0x04000000) /* Retry error enable */
-#define PCI_ICR_IAE (0x02000000) /* Initiator abort enable */
-#define PCI_ICR_TAE (0x01000000) /* Target abort enable */
-#define PCI_ICR_MAXRETRY(x) ((x) & 0x000000FF)
-
-/********************************************************************/
-
-#endif /* __MCF5445X__ */
diff --git a/arch/mips/Kconfig b/arch/mips/Kconfig
index e548016..6b1f10d 100644
--- a/arch/mips/Kconfig
+++ b/arch/mips/Kconfig
@@ -14,8 +14,11 @@
config TARGET_MALTA
bool "Support malta"
+ select BOARD_EARLY_INIT_R
select DM
select DM_SERIAL
+ select DM_PCI
+ select DM_ETH
select DYNAMIC_IO_PORT_BASE
select MIPS_CM
select MIPS_INSERT_BOOT_CONFIG
@@ -23,6 +26,7 @@
select MIPS_L2_CACHE
select OF_CONTROL
select OF_ISA_BUS
+ select PCI_MAP_SYSTEM_MEMORY
select ROM_EXCEPTION_VECTORS
select SUPPORTS_BIG_ENDIAN
select SUPPORTS_CPU_MIPS32_R1
diff --git a/arch/mips/dts/mti,malta.dts b/arch/mips/dts/mti,malta.dts
index d339229..ef47a34 100644
--- a/arch/mips/dts/mti,malta.dts
+++ b/arch/mips/dts/mti,malta.dts
@@ -29,4 +29,32 @@
u-boot,dm-pre-reloc;
};
};
+
+ pci0@1bd00000 {
+ compatible = "mips,pci-msc01";
+ device_type = "pci";
+ reg = <0x1bd00000 0x2000>;
+
+ #address-cells = <3>;
+ #size-cells = <2>;
+ bus-range = <0x0 0x0>;
+ ranges = <0x01000000 0 0x00000000 0x00000000 0 0x800000 /* I/O */
+ 0x02000000 0 0x10000000 0xb0000000 0 0x10000000 /* MEM */>;
+
+ status = "disabled";
+ };
+
+ pci0@1be00000 {
+ compatible = "marvell,pci-gt64120";
+ device_type = "pci";
+ reg = <0x1be00000 0x2000>;
+
+ #address-cells = <3>;
+ #size-cells = <2>;
+ bus-range = <0x0 0x0>;
+ ranges = <0x01000000 0 0x00000000 0x00000000 0 0x20000 /* I/O */
+ 0x02000000 0 0x10000000 0x10000000 0 0x8000000 /* MEM */>;
+
+ status = "okay";
+ };
};
diff --git a/arch/sandbox/cpu/state.c b/arch/sandbox/cpu/state.c
index f63cfd3..a4d99ba 100644
--- a/arch/sandbox/cpu/state.c
+++ b/arch/sandbox/cpu/state.c
@@ -78,6 +78,10 @@
err_read:
os_close(fd);
err_open:
+ /*
+ * tainted scalar, since size is obtained from the file. But we can rely
+ * on os_malloc() to handle invalid values.
+ */
os_free(state->state_fdt);
state->state_fdt = NULL;
diff --git a/arch/x86/cpu/coreboot/Kconfig b/arch/x86/cpu/coreboot/Kconfig
index 497d628..b97c277 100644
--- a/arch/x86/cpu/coreboot/Kconfig
+++ b/arch/x86/cpu/coreboot/Kconfig
@@ -1,4 +1,4 @@
-if TARGET_COREBOOT
+if VENDOR_COREBOOT
config SYS_COREBOOT
bool
diff --git a/arch/x86/cpu/i386/cpu.c b/arch/x86/cpu/i386/cpu.c
index e59215c..c7f6c5a 100644
--- a/arch/x86/cpu/i386/cpu.c
+++ b/arch/x86/cpu/i386/cpu.c
@@ -423,7 +423,7 @@
u64 mtrr_cap;
/* Configure fixed range MTRRs for some legacy regions */
- if (!gd->arch.has_mtrr)
+ if (!gd->arch.has_mtrr || !ll_boot_init())
return;
mtrr_cap = native_read_msr(MTRR_CAP_MSR);
diff --git a/arch/x86/dts/chromebook_coral.dts b/arch/x86/dts/chromebook_coral.dts
index c8cb4e2..66c31ef 100644
--- a/arch/x86/dts/chromebook_coral.dts
+++ b/arch/x86/dts/chromebook_coral.dts
@@ -10,7 +10,7 @@
/include/ "rtc.dtsi"
/include/ "tsc_timer.dtsi"
-#ifdef CONFIG_CHROMEOS_VBOOT
+#if defined(CONFIG_CHROMEOS_VBOOT) && defined(CONFIG_ROM_SIZE)
#include "chromeos-x86.dtsi"
#include "flashmap-x86-ro.dtsi"
#include "flashmap-16mb-rw.dtsi"
diff --git a/arch/x86/dts/chromebook_samus.dts b/arch/x86/dts/chromebook_samus.dts
index adaeb1e..ad35ab2 100644
--- a/arch/x86/dts/chromebook_samus.dts
+++ b/arch/x86/dts/chromebook_samus.dts
@@ -11,7 +11,7 @@
#include "smbios.dtsi"
-#ifdef CONFIG_CHROMEOS_VBOOT
+#if defined(CONFIG_CHROMEOS_VBOOT) && defined(CONFIG_ROM_SIZE)
#include "chromeos-x86.dtsi"
#include "flashmap-x86-ro.dtsi"
#include "flashmap-8mb-rw.dtsi"
diff --git a/arch/x86/include/asm/cb_sysinfo.h b/arch/x86/include/asm/cb_sysinfo.h
index 675eef6..7590135 100644
--- a/arch/x86/include/asm/cb_sysinfo.h
+++ b/arch/x86/include/asm/cb_sysinfo.h
@@ -215,6 +215,22 @@
extern struct sysinfo_t lib_sysinfo;
+/**
+ * get_coreboot_info() - parse the coreboot sysinfo table
+ *
+ * Parses the coreboot table if found, setting the GD_FLG_SKIP_LL_INIT flag if
+ * so.
+ *
+ * @info: Place to put the parsed information
+ * @return 0 if OK, -ENOENT if no table found
+ */
int get_coreboot_info(struct sysinfo_t *info);
+/**
+ * cb_get_sysinfo() - get a pointer to the parsed coreboot sysinfo
+ *
+ * @return pointer to sysinfo, or NULL if not available
+ */
+const struct sysinfo_t *cb_get_sysinfo(void);
+
#endif
diff --git a/arch/x86/include/asm/mp.h b/arch/x86/include/asm/mp.h
index 1a3ae8e..e48ba05 100644
--- a/arch/x86/include/asm/mp.h
+++ b/arch/x86/include/asm/mp.h
@@ -10,18 +10,22 @@
#include <asm/atomic.h>
#include <asm/cache.h>
+#include <linux/bitops.h>
struct udevice;
enum {
- /* Indicates that the function should run on all CPUs */
- MP_SELECT_ALL = -1,
+ /*
+ * Indicates that the function should run on all CPUs. We use a large
+ * number, above the number of real CPUs we expect to find.
+ */
+ MP_SELECT_ALL = BIT(16),
/* Run on boot CPUs */
- MP_SELECT_BSP = -2,
+ MP_SELECT_BSP,
/* Run on non-boot CPUs */
- MP_SELECT_APS = -3,
+ MP_SELECT_APS,
};
typedef int (*mp_callback_t)(struct udevice *cpu, void *arg);
diff --git a/arch/x86/lib/init_helpers.c b/arch/x86/lib/init_helpers.c
index 67401b9..f331940 100644
--- a/arch/x86/lib/init_helpers.c
+++ b/arch/x86/lib/init_helpers.c
@@ -18,10 +18,20 @@
IS_ENABLED(CONFIG_FSP_VERSION2);
int ret;
- if (!ll_boot_init())
- return 0;
-
- do_mtrr &= !IS_ENABLED(CONFIG_FSP_VERSION1) &&
+ /*
+ * Supported configurations:
+ *
+ * booting from slimbootloader - in that case the MTRRs are already set
+ * up
+ * booting with FSPv1 - MTRRs are already set up
+ * booting with FSPv2 - MTRRs must be set here
+ * booting from coreboot - in this case there is no SPL, so we set up
+ * the MTRRs here
+ * Note: if there is an SPL, then it has already set up MTRRs so we
+ * don't need to do that here
+ */
+ do_mtrr &= !IS_ENABLED(CONFIG_SPL) &&
+ !IS_ENABLED(CONFIG_FSP_VERSION1) &&
!IS_ENABLED(CONFIG_SYS_SLIMBOOTLOADER);
if (do_mtrr) {
diff --git a/arch/x86/lib/zimage.c b/arch/x86/lib/zimage.c
index 90fc8a4..cf4210c 100644
--- a/arch/x86/lib/zimage.c
+++ b/arch/x86/lib/zimage.c
@@ -313,12 +313,12 @@
int bootproto = get_boot_protocol(hdr, false);
log_debug("Setup E820 entries\n");
- if (ll_boot_init()) {
- setup_base->e820_entries = install_e820_map(
- ARRAY_SIZE(setup_base->e820_map), setup_base->e820_map);
- } else if (IS_ENABLED(CONFIG_COREBOOT_SYSINFO)) {
+ if (IS_ENABLED(CONFIG_COREBOOT_SYSINFO)) {
setup_base->e820_entries = cb_install_e820_map(
ARRAY_SIZE(setup_base->e820_map), setup_base->e820_map);
+ } else {
+ setup_base->e820_entries = install_e820_map(
+ ARRAY_SIZE(setup_base->e820_map), setup_base->e820_map);
}
if (bootproto == 0x0100) {
diff --git a/board/Marvell/mvebu_armada-37xx/board.c b/board/Marvell/mvebu_armada-37xx/board.c
index c630437..2de9c2a 100644
--- a/board/Marvell/mvebu_armada-37xx/board.c
+++ b/board/Marvell/mvebu_armada-37xx/board.c
@@ -124,7 +124,7 @@
/* eMMC is mmc dev num 1 */
mmc_dev = find_mmc_device(1);
- emmc = (mmc_dev && mmc_init(mmc_dev) == 0);
+ emmc = (mmc_dev && mmc_get_op_cond(mmc_dev, true) == 0);
/* if eMMC is not present then remove it from DM */
if (!emmc && mmc_dev) {
@@ -133,9 +133,6 @@
device_unbind(dev);
}
- if (env_get("fdtfile"))
- return 0;
-
/* Ensure that 'env default -a' set correct value to $fdtfile */
if (ddr4 && emmc)
strcpy(ptr, "fdtfile=marvell/armada-3720-espressobin-v7-emmc.dtb");
@@ -146,10 +143,6 @@
else
strcpy(ptr, "fdtfile=marvell/armada-3720-espressobin.dtb");
- /* If $fdtfile was not set explicitly by user then set default value */
- if (!env_get("fdtfile"))
- env_set("fdtfile", ptr + sizeof("fdtfile="));
-
return 0;
}
#endif
diff --git a/board/coreboot/coreboot/Kconfig b/board/coreboot/coreboot/Kconfig
index 5bd6465..05e9b3b 100644
--- a/board/coreboot/coreboot/Kconfig
+++ b/board/coreboot/coreboot/Kconfig
@@ -1,4 +1,4 @@
-if TARGET_COREBOOT
+if VENDOR_COREBOOT
config SYS_BOARD
default "coreboot"
@@ -9,9 +9,6 @@
config SYS_SOC
default "coreboot"
-config SYS_CONFIG_NAME
- default "coreboot"
-
config SYS_TEXT_BASE
default 0x01110000
@@ -31,4 +28,11 @@
help
This option specifies the board specific Cache-As-RAM (CAR) size.
+endif # CONFIG_VENDOR_COREBOOT
+
+if TARGET_COREBOOT
+
+config SYS_CONFIG_NAME
+ default "coreboot"
+
endif
diff --git a/board/coreboot/coreboot/coreboot.c b/board/coreboot/coreboot/coreboot.c
index 175d3ce..11294d6 100644
--- a/board/coreboot/coreboot/coreboot.c
+++ b/board/coreboot/coreboot/coreboot.c
@@ -37,6 +37,7 @@
goto fallback;
const char *bios_ver = smbios_string(bios, t0->bios_ver);
+ const char *bios_date = smbios_string(bios, t0->bios_release_date);
const char *model = smbios_string(system, t1->product_name);
const char *manufacturer = smbios_string(system, t1->manufacturer);
@@ -46,6 +47,8 @@
printf("Vendor: %s\n", manufacturer);
printf("Model: %s\n", model);
printf("BIOS Version: %s\n", bios_ver);
+ if (bios_date)
+ printf("BIOS date: %s\n", bios_date);
return 0;
diff --git a/board/dhelectronics/dh_imx6/MAINTAINERS b/board/dhelectronics/dh_imx6/MAINTAINERS
index ab4e16b..8f9b5ff 100644
--- a/board/dhelectronics/dh_imx6/MAINTAINERS
+++ b/board/dhelectronics/dh_imx6/MAINTAINERS
@@ -1,6 +1,7 @@
DH_IMX6 BOARD
M: Andreas Geisreiter <ageisreiter@dh-electronics.de>
-M: Ludwig Zenz <lzenz@dh-electronics.de>
+M: Christoph Niedermaier <cniedermaier@dh-electronics.com>
+L: u-boot@dh-electronics.com
S: Maintained
F: board/dhelectronics/dh_imx6/
F: include/configs/dh_imx6.h
diff --git a/board/emulation/common/Makefile b/board/emulation/common/Makefile
index 7ed447a..c5b452e 100644
--- a/board/emulation/common/Makefile
+++ b/board/emulation/common/Makefile
@@ -2,4 +2,3 @@
obj-$(CONFIG_SYS_MTDPARTS_RUNTIME) += qemu_mtdparts.o
obj-$(CONFIG_SET_DFU_ALT_INFO) += qemu_dfu.o
-obj-$(CONFIG_EFI_CAPSULE_FIRMWARE_MANAGEMENT) += qemu_capsule.o
diff --git a/board/emulation/common/qemu_capsule.c b/board/emulation/common/qemu_capsule.c
deleted file mode 100644
index 6b8a870..0000000
--- a/board/emulation/common/qemu_capsule.c
+++ /dev/null
@@ -1,43 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * Copyright (c) 2020 Linaro Limited
- */
-
-#include <common.h>
-#include <efi_api.h>
-#include <efi_loader.h>
-#include <env.h>
-#include <fdtdec.h>
-#include <asm/global_data.h>
-
-DECLARE_GLOBAL_DATA_PTR;
-
-int efi_get_public_key_data(void **pkey, efi_uintn_t *pkey_len)
-{
- const void *fdt_blob = gd->fdt_blob;
- const void *blob;
- const char *cnode_name = "capsule-key";
- const char *snode_name = "signature";
- int sig_node;
- int len;
-
- sig_node = fdt_subnode_offset(fdt_blob, 0, snode_name);
- if (sig_node < 0) {
- EFI_PRINT("Unable to get signature node offset\n");
- return -FDT_ERR_NOTFOUND;
- }
-
- blob = fdt_getprop(fdt_blob, sig_node, cnode_name, &len);
-
- if (!blob || len < 0) {
- EFI_PRINT("Unable to get capsule-key value\n");
- *pkey = NULL;
- *pkey_len = 0;
- return -FDT_ERR_NOTFOUND;
- }
-
- *pkey = (void *)blob;
- *pkey_len = len;
-
- return 0;
-}
diff --git a/board/freescale/imx8mq_evk/imx8mq_evk.c b/board/freescale/imx8mq_evk/imx8mq_evk.c
index 93da67d..e394805 100644
--- a/board/freescale/imx8mq_evk/imx8mq_evk.c
+++ b/board/freescale/imx8mq_evk/imx8mq_evk.c
@@ -86,6 +86,10 @@
setup_fec();
#endif
+#if defined(CONFIG_USB_DWC3) || defined(CONFIG_USB_XHCI_DWC3)
+ init_usb_clk();
+#endif
+
return 0;
}
diff --git a/board/freescale/lx2160a/lx2160a.c b/board/freescale/lx2160a/lx2160a.c
index 47a7024..891bc00 100644
--- a/board/freescale/lx2160a/lx2160a.c
+++ b/board/freescale/lx2160a/lx2160a.c
@@ -781,7 +781,7 @@
fdt_fixup_memory_banks(blob, base, size, total_memory_banks);
-#ifdef CONFIG_USB
+#ifdef CONFIG_USB_HOST
fsl_fdt_fixup_dr_usb(blob, bd);
#endif
diff --git a/board/freescale/m52277evb/Kconfig b/board/freescale/m52277evb/Kconfig
deleted file mode 100644
index c427892..0000000
--- a/board/freescale/m52277evb/Kconfig
+++ /dev/null
@@ -1,15 +0,0 @@
-if TARGET_M52277EVB
-
-config SYS_CPU
- default "mcf5227x"
-
-config SYS_BOARD
- default "m52277evb"
-
-config SYS_VENDOR
- default "freescale"
-
-config SYS_CONFIG_NAME
- default "M52277EVB"
-
-endif
diff --git a/board/freescale/m52277evb/MAINTAINERS b/board/freescale/m52277evb/MAINTAINERS
deleted file mode 100644
index a2a2176..0000000
--- a/board/freescale/m52277evb/MAINTAINERS
+++ /dev/null
@@ -1,7 +0,0 @@
-M52277EVB BOARD
-M: TsiChung Liew <Tsi-Chung.Liew@nxp.com>
-S: Maintained
-F: board/freescale/m52277evb/
-F: include/configs/M52277EVB.h
-F: configs/M52277EVB_defconfig
-F: configs/M52277EVB_stmicro_defconfig
diff --git a/board/freescale/m52277evb/Makefile b/board/freescale/m52277evb/Makefile
deleted file mode 100644
index f98b0c9..0000000
--- a/board/freescale/m52277evb/Makefile
+++ /dev/null
@@ -1,6 +0,0 @@
-# SPDX-License-Identifier: GPL-2.0+
-#
-# (C) Copyright 2000-2003
-# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
-
-obj-y = m52277evb.o
diff --git a/board/freescale/m52277evb/README b/board/freescale/m52277evb/README
deleted file mode 100644
index 8bfd812..0000000
--- a/board/freescale/m52277evb/README
+++ /dev/null
@@ -1,228 +0,0 @@
-Freescale MCF52277EVB ColdFire Development Board
-================================================
-
-TsiChung Liew(Tsi-Chung.Liew@freescale.com)
-Created Jan 8, 2008
-===========================================
-
-
-Changed files:
-==============
-
-- board/freescale/m52277evb/m52277evb.c Dram setup
-- board/freescale/m52277evb/Makefile Makefile
-- board/freescale/m52277evb/config.mk config make
-- board/freescale/m52277evb/u-boot.lds Linker description
-
-- arch/m68k/cpu/mcf5227x/cpu.c cpu specific code
-- arch/m68k/cpu/mcf5227x/cpu_init.c FBCS, Mux pins, icache and RTC extra regs
-- arch/m68k/cpu/mcf5227x/interrupts.c cpu specific interrupt support
-- arch/m68k/cpu/mcf5227x/speed.c system, flexbus, and cpu clock
-- arch/m68k/cpu/mcf5227x/Makefile Makefile
-- arch/m68k/cpu/mcf5227x/config.mk config make
-- arch/m68k/cpu/mcf5227x/start.S start up assembly code
-
-- board/freescale/m52277evb/README This readme file
-
-- drivers/serial/mcfuart.c ColdFire common UART driver
-- drivers/rtc/mcfrtc.c Realtime clock Driver
-
-- include/asm-m68k/bitops.h Bit operation function export
-- include/asm-m68k/byteorder.h Byte order functions
-- include/asm-m68k/crossbar.h CrossBar structure and definition
-- include/asm-m68k/dspi.h DSPI structure and definition
-- include/asm-m68k/edma.h eDMA structure and definition
-- include/asm-m68k/flexbus.h FlexBus structure and definition
-- include/asm-m68k/fsl_i2c.h I2C structure and definition
-- include/asm-m68k/global_data.h Global data structure
-- include/asm-m68k/immap.h ColdFire specific header file and driver macros
-- include/asm-m68k/immap_5227x.h mcf5227x specific header file
-- include/asm-m68k/io.h io functions
-- include/asm-m68k/lcd.h LCD structure and definition
-- include/asm-m68k/m5227x.h mcf5227x specific header file
-- include/asm-m68k/posix_types.h Posix
-- include/asm-m68k/processor.h header file
-- include/asm-m68k/ptrace.h Exception structure
-- include/asm-m68k/rtc.h Realtime clock header file
-- include/asm-m68k/ssi.h SSI structure and definition
-- include/asm-m68k/string.h String function export
-- include/asm-m68k/timer.h Timer structure and definition
-- include/asm-m68k/types.h Data types definition
-- include/asm-m68k/uart.h Uart structure and definition
-- include/asm-m68k/u-boot.h U-Boot structure
-
-- include/configs/M52277EVB.h Board specific configuration file
-
-- arch/m68k/lib/board.c board init function
-- arch/m68k/lib/cache.c
-- arch/m68k/lib/interrupts Coldfire common interrupt functions
-- arch/m68k/lib/m68k_linux.c
-- arch/m68k/lib/time.c Timer functions (Dma timer and PIT)
-- arch/m68k/lib/traps.c Exception init code
-
-1 MCF52277 specific Options/Settings
-====================================
-1.1 pre-loader is no longer suppoer in this coldfire family
-
-1.2 Configuration settings for M52277EVB Development Board
-CONFIG_MCF5227x -- define for all MCF5227x CPUs
-CONFIG_M52277 -- define for all Freescale MCF52277 CPUs
-
-CONFIG_MCFUART -- define to use common CF Uart driver
-CONFIG_SYS_UART_PORT -- define UART port number, start with 0, 1 and 2
-CONFIG_BAUDRATE -- define UART baudrate
-
-CONFIG_MCFRTC -- define to use common CF RTC driver
-CONFIG_SYS_MCFRTC_BASE -- provide base address for RTC in immap.h
-CONFIG_SYS_RTC_OSCILLATOR -- define RTC clock frequency
-RTC_DEBUG -- define to show RTC debug message
-CONFIG_CMD_DATE -- enable to use date feature in U-Boot
-
-CONFIG_MCFTMR -- define to use DMA timer
-
-CONFIG_SYS_I2C_FSL -- define to use FSL common I2C driver
-CONFIG_SYS_I2C_SOFT -- define for I2C bit-banged
-CONFIG_SYS_I2C_SPEED -- define for I2C speed
-CONFIG_SYS_I2C_SLAVE -- define for I2C slave address
-CONFIG_SYS_I2C_OFFSET -- define for I2C base address offset
-CONFIG_SYS_IMMR -- define for MBAR offset
-
-CONFIG_SYS_MBAR -- define MBAR offset
-
-CONFIG_MONITOR_IS_IN_RAM -- Not support
-
-CONFIG_SYS_INIT_RAM_ADDR -- defines the base address of the MCF52277 internal SRAM
-
-CONFIG_SYS_CSn_BASE -- defines the Chip Select Base register
-CONFIG_SYS_CSn_MASK -- defines the Chip Select Mask register
-CONFIG_SYS_CSn_CTRL -- defines the Chip Select Control register
-
-CONFIG_SYS_SDRAM_BASE -- defines the DRAM Base
-
-CONFIG_LCD and CONFIG_CMD_USB are not supported in this current U-Boot,
-update will be provided at later time
-
-2. MEMORY MAP UNDER U-BOOT AND LINUX KERNEL
-===========================================
-2.1. System memory map:
- Flash: 0x00000000-0x3FFFFFFF (1024MB)
- DDR: 0x40000000-0x7FFFFFFF (1024MB)
- SRAM: 0x80000000-0x8FFFFFFF (256MB)
- IP: 0xF0000000-0xFFFFFFFF (256MB)
-
-2.2. For the initial bringup, we adopted a consistent memory scheme between U-Boot and
- linux kernel, you can customize it based on your system requirements:
- Flash0: 0x00000000-0x00FFFFFF (16MB)
-
- DDR: 0x40000000-0x4FFFFFFF (64MB)
- SRAM: 0x80000000-0x80007FFF (32KB)
- IP: 0xFC000000-0xFC0FFFFF (64KB)
-
-3. COMPILATION
-==============
-3.1 To create U-Boot the gcc-4.1-xx compiler set (ColdFire ELF or
-uClinux version) from codesourcery.com was used. Download it from:
-http://www.codesourcery.com/gnu_toolchains/coldfire/download.html
-
-3.2 Compilation
- export CROSS_COMPILE=cross-compile-prefix
- cd u-boot-1.x.x
- make distclean
- make M52277EVB_config
- make
-
-4. SCREEN DUMP
-==============
-4.1 M52277EVB Development board
- (NOTE: May not show exactly the same)
-
-U-Boot 1.3.1 (Jan 8 2008 - 12:44:08)
-
-CPU: Freescale MCF52277 (Mask:6c Version:0)
- CPU CLK 160 Mhz BUS CLK 80 Mhz FLB CLK 80 MHZ
- INP CLK 16 Mhz VCO CLK 480 Mhz
-Board: Freescale 52277 EVB
-I2C: ready
-DRAM: 64 MB
-FLASH: 16 MB
-In: serial
-Out: serial
-Err: serial
--> print
-baudrate=115200
-hostname=M52277EVB
-inpclk=16000000
-loadaddr=(0x40000000 + 0x10000)
-load=tftp ${loadaddr) ${u-boot}
-upd=run load; run prog
-prog=prot off 0 3ffff;era 0 3ffff;cp.b ${loadaddr} 0 ${filesize};save
-u-boot=u-boot.bin
-stdin=serial
-stdout=serial
-stderr=serial
-mem=65024k
-
-Environment size: 280/32764 bytes
--> bdinfo
-memstart = 0x40000000
-memsize = 0x04000000
-flashstart = 0x00000000
-flashsize = 0x01000000
-flashoffset = 0x00000000
-sramstart = 0x80000000
-sramsize = 0x00008000
-mbar = 0xFC000000
-busfreq = 80 MHz
-flbfreq = 80 Mhz
-inpfreq = 16 Mhz
-vcofreq = 480 Mhz
-
-baudrate = 115200 bps
-->
--> help
-? - alias for 'help'
-base - print or set address offset
-bdinfo - print Board Info structure
-boot - boot default, i.e., run 'bootcmd'
-bootd - boot default, i.e., run 'bootcmd'
-bootelf - Boot from an ELF image in memory
-bootm - boot application image from memory
-bootp - boot image via network using BootP/TFTP protocol
-bootvx - Boot vxWorks from an ELF image
-cmp - memory compare
-coninfo - print console devices and information
-cp - memory copy
-crc32 - checksum calculation
-date - get/set/reset date & time
-dcache - enable or disable data cache
-echo - echo args to console
-erase - erase FLASH memory
-flinfo - print FLASH memory information
-go - start application at address 'addr'
-help - print online help
-i2c - I2C sub-system
-icache - enable or disable instruction cache
-iminfo - print header information for application image
-imls - list all images found in flash
-itest - return true/false on integer compare
-loadb - load binary file over serial line (kermit mode)
-loads - load S-Record file over serial line
-loady - load binary file over serial line (ymodem mode)
-loop - infinite loop on address range
-ls - list files in a directory (default /)
-md - memory display
-mm - memory modify (auto-incrementing)
-mtest - simple RAM test
-mw - memory write (fill)
-nm - memory modify (constant address)
-ping - send ICMP ECHO_REQUEST to network host
-printenv- print environment variables
-protect - enable or disable FLASH write protection
-reset - Perform RESET of the CPU
-run - run commands in an environment variable
-saveenv - save environment variables to persistent storage
-setenv - set environment variables
-sleep - delay execution for some time
-source - run script from memory
-version - print monitor version
-->
diff --git a/board/freescale/m52277evb/m52277evb.c b/board/freescale/m52277evb/m52277evb.c
deleted file mode 100644
index 510af33..0000000
--- a/board/freescale/m52277evb/m52277evb.c
+++ /dev/null
@@ -1,94 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * (C) Copyright 2000-2003
- * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
- *
- * Copyright (C) 2004-2007, 2012 Freescale Semiconductor, Inc.
- * TsiChung Liew (Tsi-Chung.Liew@freescale.com)
- */
-
-#include <common.h>
-#include <init.h>
-#include <asm/global_data.h>
-#include <asm/immap.h>
-#include <asm/io.h>
-#include <linux/delay.h>
-
-DECLARE_GLOBAL_DATA_PTR;
-
-int checkboard(void)
-{
- puts("Board: ");
- puts("Freescale M52277 EVB\n");
- return 0;
-};
-
-int dram_init(void)
-{
- u32 dramsize;
-
-#ifdef CONFIG_CF_SBF
- /*
- * Serial Boot: The dram is already initialized in start.S
- * only require to return DRAM size
- */
- dramsize = CONFIG_SYS_SDRAM_SIZE * 0x100000;
-#else
- sdramc_t *sdram = (sdramc_t *)(MMAP_SDRAM);
- gpio_t *gpio = (gpio_t *)(MMAP_GPIO);
- u32 i;
-
- dramsize = CONFIG_SYS_SDRAM_SIZE * 0x100000;
-
- for (i = 0x13; i < 0x20; i++) {
- if (dramsize == (1 << i))
- break;
- }
- i--;
-
- out_8(&gpio->mscr_sdram, CONFIG_SYS_SDRAM_DRV_STRENGTH);
-
- out_be32(&sdram->sdcs0, CONFIG_SYS_SDRAM_BASE | i);
-
- out_be32(&sdram->sdcfg1, CONFIG_SYS_SDRAM_CFG1);
- out_be32(&sdram->sdcfg2, CONFIG_SYS_SDRAM_CFG2);
-
- /* Issue PALL */
- out_be32(&sdram->sdcr, CONFIG_SYS_SDRAM_CTRL | 2);
- __asm__("nop");
-
- /* Issue LEMR */
- out_be32(&sdram->sdmr, CONFIG_SYS_SDRAM_MODE);
- __asm__("nop");
- out_be32(&sdram->sdmr, CONFIG_SYS_SDRAM_EMOD);
- __asm__("nop");
-
- udelay(1000);
-
- /* Issue PALL */
- out_be32(&sdram->sdcr, CONFIG_SYS_SDRAM_CTRL | 2);
- __asm__("nop");
-
- /* Perform two refresh cycles */
- out_be32(&sdram->sdcr, CONFIG_SYS_SDRAM_CTRL | 4);
- __asm__("nop");
- out_be32(&sdram->sdcr, CONFIG_SYS_SDRAM_CTRL | 4);
- __asm__("nop");
-
- out_be32(&sdram->sdcr,
- (CONFIG_SYS_SDRAM_CTRL & ~0x80000000) | 0x10000c00);
-
- udelay(100);
-#endif
- gd->ram_size = dramsize;
-
- return 0;
-};
-
-int testdram(void)
-{
- /* TODO: XXX XXX XXX */
- printf("DRAM test not implemented!\n");
-
- return (0);
-}
diff --git a/board/freescale/m54418twr/Kconfig b/board/freescale/m54418twr/Kconfig
deleted file mode 100644
index 4199a3f..0000000
--- a/board/freescale/m54418twr/Kconfig
+++ /dev/null
@@ -1,15 +0,0 @@
-if TARGET_M54418TWR
-
-config SYS_CPU
- default "mcf5445x"
-
-config SYS_BOARD
- default "m54418twr"
-
-config SYS_VENDOR
- default "freescale"
-
-config SYS_CONFIG_NAME
- default "M54418TWR"
-
-endif
diff --git a/board/freescale/m54418twr/MAINTAINERS b/board/freescale/m54418twr/MAINTAINERS
deleted file mode 100644
index f88aed9..0000000
--- a/board/freescale/m54418twr/MAINTAINERS
+++ /dev/null
@@ -1,11 +0,0 @@
-M54418TWR BOARD
-#M: -
-S: Maintained
-F: board/freescale/m54418twr/
-F: include/configs/M54418TWR.h
-F: configs/M54418TWR_defconfig
-F: configs/M54418TWR_nand_mii_defconfig
-F: configs/M54418TWR_nand_rmii_defconfig
-F: configs/M54418TWR_nand_rmii_lowfreq_defconfig
-F: configs/M54418TWR_serial_mii_defconfig
-F: configs/M54418TWR_serial_rmii_defconfig
diff --git a/board/freescale/m54418twr/Makefile b/board/freescale/m54418twr/Makefile
deleted file mode 100644
index aa53874..0000000
--- a/board/freescale/m54418twr/Makefile
+++ /dev/null
@@ -1,7 +0,0 @@
-# SPDX-License-Identifier: GPL-2.0+
-# Copyright 2010-2012 Freescale Semiconductor, Inc.
-# TsiChung Liew (Tsi-Chung.Liew@freescale.com)
-
-obj-y = m54418twr.o
-extra-y += sbf_dram_init.o
-
diff --git a/board/freescale/m54418twr/m54418twr.c b/board/freescale/m54418twr/m54418twr.c
deleted file mode 100644
index ca89931..0000000
--- a/board/freescale/m54418twr/m54418twr.c
+++ /dev/null
@@ -1,117 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * Copyright 2010-2012 Freescale Semiconductor, Inc.
- * TsiChung Liew (Tsi-Chung.Liew@freescale.com)
- */
-
-#include <common.h>
-#include <init.h>
-#include <spi.h>
-#include <asm/global_data.h>
-#include <asm/io.h>
-#include <asm/immap.h>
-#include <mmc.h>
-#include <fsl_esdhc_imx.h>
-#include <linux/delay.h>
-
-DECLARE_GLOBAL_DATA_PTR;
-
-int checkboard(void)
-{
- /*
- * need to to:
- * Check serial flash size. if 2mb evb, else 8mb demo
- */
- puts("Board: ");
- puts("Freescale MCF54418 Tower System\n");
- return 0;
-};
-
-int dram_init(void)
-{
- u32 dramsize;
-
-#if defined(CONFIG_SERIAL_BOOT)
- /*
- * Serial Boot: The dram is already initialized in start.S
- * only require to return DRAM size
- */
- dramsize = CONFIG_SYS_SDRAM_SIZE * 0x100000;
-#else
- sdramc_t *sdram = (sdramc_t *)(MMAP_SDRAM);
- ccm_t *ccm = (ccm_t *)MMAP_CCM;
- gpio_t *gpio = (gpio_t *) MMAP_GPIO;
- pm_t *pm = (pm_t *) MMAP_PM;
- u32 i;
-
- dramsize = CONFIG_SYS_SDRAM_SIZE * 0x100000;
-
- for (i = 0x13; i < 0x20; i++) {
- if (dramsize == (1 << i))
- break;
- }
-
- out_8(&pm->pmcr0, 0x2E);
- out_8(&gpio->mscr_sdram, 1);
-
- clrbits_be16(&ccm->misccr2, CCM_MISCCR2_FBHALF);
- setbits_be16(&ccm->misccr2, CCM_MISCCR2_DDR2CLK);
-
- out_be32(&sdram->rcrcr, 0x40000000);
- out_be32(&sdram->padcr, 0x01030203);
-
- out_be32(&sdram->cr00, 0x01010101);
- out_be32(&sdram->cr01, 0x00000101);
- out_be32(&sdram->cr02, 0x01010100);
- out_be32(&sdram->cr03, 0x01010000);
- out_be32(&sdram->cr04, 0x00010101);
- out_be32(&sdram->cr06, 0x00010100);
- out_be32(&sdram->cr07, 0x00000001);
- out_be32(&sdram->cr08, 0x01000001);
- out_be32(&sdram->cr09, 0x00000100);
- out_be32(&sdram->cr10, 0x00010001);
- out_be32(&sdram->cr11, 0x00000200);
- out_be32(&sdram->cr12, 0x01000002);
- out_be32(&sdram->cr13, 0x00000000);
- out_be32(&sdram->cr14, 0x00000100);
- out_be32(&sdram->cr15, 0x02000100);
- out_be32(&sdram->cr16, 0x02000407);
- out_be32(&sdram->cr17, 0x02030007);
- out_be32(&sdram->cr18, 0x02000100);
- out_be32(&sdram->cr19, 0x0A030203);
- out_be32(&sdram->cr20, 0x00020708);
- out_be32(&sdram->cr21, 0x00050008);
- out_be32(&sdram->cr22, 0x04030002);
- out_be32(&sdram->cr23, 0x00000004);
- out_be32(&sdram->cr24, 0x020A0000);
- out_be32(&sdram->cr25, 0x0C00000E);
- out_be32(&sdram->cr26, 0x00002004);
- out_be32(&sdram->cr28, 0x00100010);
- out_be32(&sdram->cr29, 0x00100010);
- out_be32(&sdram->cr31, 0x07990000);
- out_be32(&sdram->cr40, 0x00000000);
- out_be32(&sdram->cr41, 0x00C80064);
- out_be32(&sdram->cr42, 0x44520002);
- out_be32(&sdram->cr43, 0x00C80023);
- out_be32(&sdram->cr45, 0x0000C350);
- out_be32(&sdram->cr56, 0x04000000);
- out_be32(&sdram->cr57, 0x03000304);
- out_be32(&sdram->cr58, 0x40040000);
- out_be32(&sdram->cr59, 0xC0004004);
- out_be32(&sdram->cr60, 0x0642C000);
- out_be32(&sdram->cr61, 0x00000642);
- asm("tpf");
-
- out_be32(&sdram->cr09, 0x01000100);
-
- udelay(100);
-#endif
- gd->ram_size = dramsize;
-
- return 0;
-};
-
-int testdram(void)
-{
- return 0;
-}
diff --git a/board/freescale/m54418twr/sbf_dram_init.S b/board/freescale/m54418twr/sbf_dram_init.S
deleted file mode 100644
index 5a70fb9..0000000
--- a/board/freescale/m54418twr/sbf_dram_init.S
+++ /dev/null
@@ -1,85 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0+ */
-/*
- * Board-specific sbf ddr/sdram init.
- *
- * (C) Copyright 2017 Angelo Dureghello <angelo@sysam.it>
- */
-
-.global sbf_dram_init
-.text
-
-sbf_dram_init:
- move.l #0xFC04002D, %a1
- move.b #46, (%a1) /* DDR */
-
- /* slew settings */
- move.l #0xEC094060, %a1
- move.b #0, (%a1)
-
- /* use vco instead of cpu*2 clock for ddr clock */
- move.l #0xEC09001A, %a1
- move.w #0xE01D, (%a1)
-
- /* DDR settings */
- move.l #0xFC0B8180, %a1
- move.l #0x00000000, (%a1)
- move.l #0x40000000, (%a1)
-
- move.l #0xFC0B81AC, %a1
- move.l #0x01030203, (%a1)
-
- move.l #0xFC0B8000, %a1
- move.l #0x01010101, (%a1)+ /* 0x00 */
- move.l #0x00000101, (%a1)+ /* 0x04 */
- move.l #0x01010100, (%a1)+ /* 0x08 */
- move.l #0x01010000, (%a1)+ /* 0x0C */
- move.l #0x00010101, (%a1)+ /* 0x10 */
- move.l #0xFC0B8018, %a1
- move.l #0x00010100, (%a1)+ /* 0x18 */
- move.l #0x00000001, (%a1)+ /* 0x1C */
- move.l #0x01000001, (%a1)+ /* 0x20 */
- move.l #0x00000100, (%a1)+ /* 0x24 */
- move.l #0x00010001, (%a1)+ /* 0x28 */
- move.l #0x00000200, (%a1)+ /* 0x2C */
- move.l #0x01000002, (%a1)+ /* 0x30 */
- move.l #0x00000000, (%a1)+ /* 0x34 */
- move.l #0x00000100, (%a1)+ /* 0x38 */
- move.l #0x02000100, (%a1)+ /* 0x3C */
- move.l #0x02000407, (%a1)+ /* 0x40 */
- move.l #0x02030007, (%a1)+ /* 0x44 */
- move.l #0x02000100, (%a1)+ /* 0x48 */
- move.l #0x0A030203, (%a1)+ /* 0x4C */
- move.l #0x00020708, (%a1)+ /* 0x50 */
- move.l #0x00050008, (%a1)+ /* 0x54 */
- move.l #0x04030002, (%a1)+ /* 0x58 */
- move.l #0x00000004, (%a1)+ /* 0x5C */
- move.l #0x020A0000, (%a1)+ /* 0x60 */
- move.l #0x0C00000E, (%a1)+ /* 0x64 */
- move.l #0x00002004, (%a1)+ /* 0x68 */
- move.l #0x00000000, (%a1)+ /* 0x6C */
- move.l #0x00100010, (%a1)+ /* 0x70 */
- move.l #0x00100010, (%a1)+ /* 0x74 */
- move.l #0x00000000, (%a1)+ /* 0x78 */
- move.l #0x07990000, (%a1)+ /* 0x7C */
- move.l #0xFC0B80A0, %a1
- move.l #0x00000000, (%a1)+ /* 0xA0 */
- move.l #0x00C80064, (%a1)+ /* 0xA4 */
- move.l #0x44520002, (%a1)+ /* 0xA8 */
- move.l #0x00C80023, (%a1)+ /* 0xAC */
- move.l #0xFC0B80B4, %a1
- move.l #0x0000C350, (%a1) /* 0xB4 */
- move.l #0xFC0B80E0, %a1
- move.l #0x04000000, (%a1)+ /* 0xE0 */
- move.l #0x03000304, (%a1)+ /* 0xE4 */
- move.l #0x40040000, (%a1)+ /* 0xE8 */
- move.l #0xC0004004, (%a1)+ /* 0xEC */
- move.l #0x0642C000, (%a1)+ /* 0xF0 */
- move.l #0x00000642, (%a1)+ /* 0xF4 */
- move.l #0xFC0B8024, %a1
- tpf
- move.l #0x01000100, (%a1) /* 0x24 */
-
- move.l #0x2000, %d1
- bsr asm_delay
-
- rts
diff --git a/board/freescale/m54451evb/Kconfig b/board/freescale/m54451evb/Kconfig
deleted file mode 100644
index f460e51..0000000
--- a/board/freescale/m54451evb/Kconfig
+++ /dev/null
@@ -1,15 +0,0 @@
-if TARGET_M54451EVB
-
-config SYS_CPU
- default "mcf5445x"
-
-config SYS_BOARD
- default "m54451evb"
-
-config SYS_VENDOR
- default "freescale"
-
-config SYS_CONFIG_NAME
- default "M54451EVB"
-
-endif
diff --git a/board/freescale/m54451evb/MAINTAINERS b/board/freescale/m54451evb/MAINTAINERS
deleted file mode 100644
index 52a2681..0000000
--- a/board/freescale/m54451evb/MAINTAINERS
+++ /dev/null
@@ -1,7 +0,0 @@
-M54451EVB BOARD
-#M: -
-S: Maintained
-F: board/freescale/m54451evb/
-F: include/configs/M54451EVB.h
-F: configs/M54451EVB_defconfig
-F: configs/M54451EVB_stmicro_defconfig
diff --git a/board/freescale/m54451evb/Makefile b/board/freescale/m54451evb/Makefile
deleted file mode 100644
index 8c2c6a9..0000000
--- a/board/freescale/m54451evb/Makefile
+++ /dev/null
@@ -1,7 +0,0 @@
-# SPDX-License-Identifier: GPL-2.0+
-#
-# (C) Copyright 2000-2003
-# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
-
-obj-y = m54451evb.o
-extra-y += sbf_dram_init.o
diff --git a/board/freescale/m54451evb/m54451evb.c b/board/freescale/m54451evb/m54451evb.c
deleted file mode 100644
index a4ddc69..0000000
--- a/board/freescale/m54451evb/m54451evb.c
+++ /dev/null
@@ -1,98 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * (C) Copyright 2000-2003
- * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
- *
- * Copyright (C) 2004-2008, 2012 Freescale Semiconductor, Inc.
- * TsiChung Liew (Tsi-Chung.Liew@freescale.com)
- */
-
-#include <common.h>
-#include <init.h>
-#include <spi.h>
-#include <asm/global_data.h>
-#include <asm/immap.h>
-#include <asm/io.h>
-#include <linux/delay.h>
-
-DECLARE_GLOBAL_DATA_PTR;
-
-int checkboard(void)
-{
- /*
- * need to to:
- * Check serial flash size. if 2mb evb, else 8mb demo
- */
- puts("Board: ");
- puts("Freescale M54451 EVB\n");
- return 0;
-};
-
-int dram_init(void)
-{
- u32 dramsize;
-#ifdef CONFIG_CF_SBF
- /*
- * Serial Boot: The dram is already initialized in start.S
- * only require to return DRAM size
- */
- dramsize = CONFIG_SYS_SDRAM_SIZE * 0x100000;
-#else
- sdramc_t *sdram = (sdramc_t *)(MMAP_SDRAM);
- gpio_t *gpio = (gpio_t *)(MMAP_GPIO);
- u32 i;
-
- dramsize = CONFIG_SYS_SDRAM_SIZE * 0x100000;
-
- if ((in_be32(&sdram->sdcfg1) == CONFIG_SYS_SDRAM_CFG1) &&
- (in_be32(&sdram->sdcfg2) == CONFIG_SYS_SDRAM_CFG2))
- return dramsize;
-
- for (i = 0x13; i < 0x20; i++) {
- if (dramsize == (1 << i))
- break;
- }
- i--;
-
- out_8(&gpio->mscr_sdram, CONFIG_SYS_SDRAM_DRV_STRENGTH);
-
- out_be32(&sdram->sdcs0, CONFIG_SYS_SDRAM_BASE | i);
-
- out_be32(&sdram->sdcfg1, CONFIG_SYS_SDRAM_CFG1);
- out_be32(&sdram->sdcfg2, CONFIG_SYS_SDRAM_CFG2);
-
- udelay(200);
-
- /* Issue PALL */
- out_be32(&sdram->sdcr, CONFIG_SYS_SDRAM_CTRL | 2);
- __asm__("nop");
-
- /* Perform two refresh cycles */
- out_be32(&sdram->sdcr, CONFIG_SYS_SDRAM_CTRL | 4);
- __asm__("nop");
- out_be32(&sdram->sdcr, CONFIG_SYS_SDRAM_CTRL | 4);
- __asm__("nop");
-
- /* Issue LEMR */
- out_be32(&sdram->sdmr, CONFIG_SYS_SDRAM_MODE);
- __asm__("nop");
- out_be32(&sdram->sdmr, CONFIG_SYS_SDRAM_MODE);
- __asm__("nop");
-
- out_be32(&sdram->sdcr,
- (CONFIG_SYS_SDRAM_CTRL & ~0x80000000) | 0x10000000);
-
- udelay(100);
-#endif
- gd->ram_size = dramsize;
-
- return 0;
-};
-
-int testdram(void)
-{
- /* TODO: XXX XXX XXX */
- printf("DRAM test not implemented!\n");
-
- return (0);
-}
diff --git a/board/freescale/m54451evb/sbf_dram_init.S b/board/freescale/m54451evb/sbf_dram_init.S
deleted file mode 100644
index ee08cd1..0000000
--- a/board/freescale/m54451evb/sbf_dram_init.S
+++ /dev/null
@@ -1,96 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0+ */
-/*
- * Board-specific sbf ddr/sdram init.
- *
- * (C) Copyright 2017 Angelo Dureghello <angelo@sysam.it>
- */
-
- #include <config.h>
-
-.global sbf_dram_init
-.text
-
-sbf_dram_init:
- /* Dram Initialization a1, a2, and d0 */
- /* mscr sdram */
- move.l #0xFC0A4074, %a1
- move.b #(CONFIG_SYS_SDRAM_DRV_STRENGTH), (%a1)
- nop
-
- /* SDRAM Chip 0 and 1 */
- move.l #0xFC0B8110, %a1
- move.l #0xFC0B8114, %a2
-
- /* calculate the size */
- move.l #0x13, %d1
- move.l #(CONFIG_SYS_SDRAM_SIZE), %d2
-#ifdef CONFIG_SYS_SDRAM_BASE1
- lsr.l #1, %d2
-#endif
-
-dramsz_loop:
- lsr.l #1, %d2
- add.l #1, %d1
- cmp.l #1, %d2
- bne dramsz_loop
-#ifdef CONFIG_SYS_NAND_BOOT
- beq asm_nand_chk_status
-#endif
- /* SDRAM Chip 0 and 1 */
- move.l #(CONFIG_SYS_SDRAM_BASE), (%a1)
- or.l %d1, (%a1)
-#ifdef CONFIG_SYS_SDRAM_BASE1
- move.l #(CONFIG_SYS_SDRAM_BASE1), (%a2)
- or.l %d1, (%a2)
-#endif
- nop
-
- /* dram cfg1 and cfg2 */
- move.l #0xFC0B8008, %a1
- move.l #(CONFIG_SYS_SDRAM_CFG1), (%a1)
- nop
- move.l #0xFC0B800C, %a2
- move.l #(CONFIG_SYS_SDRAM_CFG2), (%a2)
- nop
-
- move.l #0xFC0B8000, %a1 /* Mode */
- move.l #0xFC0B8004, %a2 /* Ctrl */
-
- /* Issue PALL */
- move.l #(CONFIG_SYS_SDRAM_CTRL + 2), (%a2)
- nop
-
- move.l #1000, %d1
- bsr asm_delay
-
- /* Issue PALL */
- move.l #(CONFIG_SYS_SDRAM_CTRL + 2), (%a2)
- nop
-
- /* Perform two refresh cycles */
- move.l #(CONFIG_SYS_SDRAM_CTRL + 4), %d0
- nop
- move.l %d0, (%a2)
- move.l %d0, (%a2)
- nop
-
- /* Issue LEMR */
- move.l #(CONFIG_SYS_SDRAM_MODE), (%a1)
- nop
- move.l #(CONFIG_SYS_SDRAM_EMOD), (%a1)
-
- move.l #500, %d1
- bsr asm_delay
-
- move.l #(CONFIG_SYS_SDRAM_CTRL), %d1
- and.l #0x7FFFFFFF, %d1
-
- or.l #0x10000C00, %d1
-
- move.l %d1, (%a2)
- nop
-
- move.l #2000, %d1
- bsr asm_delay
-
- rts
diff --git a/board/freescale/m54455evb/Kconfig b/board/freescale/m54455evb/Kconfig
deleted file mode 100644
index 096bce8..0000000
--- a/board/freescale/m54455evb/Kconfig
+++ /dev/null
@@ -1,15 +0,0 @@
-if TARGET_M54455EVB
-
-config SYS_CPU
- default "mcf5445x"
-
-config SYS_BOARD
- default "m54455evb"
-
-config SYS_VENDOR
- default "freescale"
-
-config SYS_CONFIG_NAME
- default "M54455EVB"
-
-endif
diff --git a/board/freescale/m54455evb/MAINTAINERS b/board/freescale/m54455evb/MAINTAINERS
deleted file mode 100644
index 27ced3c..0000000
--- a/board/freescale/m54455evb/MAINTAINERS
+++ /dev/null
@@ -1,10 +0,0 @@
-M54455EVB BOARD
-M: TsiChung Liew <Tsi-Chung.Liew@nxp.com>
-S: Maintained
-F: board/freescale/m54455evb/
-F: include/configs/M54455EVB.h
-F: configs/M54455EVB_defconfig
-F: configs/M54455EVB_a66_defconfig
-F: configs/M54455EVB_i66_defconfig
-F: configs/M54455EVB_intel_defconfig
-F: configs/M54455EVB_stm33_defconfig
diff --git a/board/freescale/m54455evb/Makefile b/board/freescale/m54455evb/Makefile
deleted file mode 100644
index eff8ab0..0000000
--- a/board/freescale/m54455evb/Makefile
+++ /dev/null
@@ -1,7 +0,0 @@
-# SPDX-License-Identifier: GPL-2.0+
-#
-# (C) Copyright 2000-2003
-# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
-
-obj-y = m54455evb.o
-extra-y += sbf_dram_init.o
diff --git a/board/freescale/m54455evb/README b/board/freescale/m54455evb/README
deleted file mode 100644
index 26d3cc8..0000000
--- a/board/freescale/m54455evb/README
+++ /dev/null
@@ -1,407 +0,0 @@
-Freescale MCF54455EVB ColdFire Development Board
-================================================
-
-TsiChung Liew(Tsi-Chung.Liew@freescale.com)
-Created 4/08/07
-===========================================
-
-
-Changed files:
-==============
-
-- board/freescale/m54455evb/m54455evb.c Dram setup, IDE pre init, and PCI init
-- board/freescale/m54455evb/flash.c Atmel and INTEL flash support
-- board/freescale/m54455evb/Makefile Makefile
-- board/freescale/m54455evb/config.mk config make
-- board/freescale/m54455evb/u-boot.lds Linker description
-
-- common/cmd_bdinfo.c Clock frequencies output
-- common/cmd_mii.c mii support
-
-- arch/m68k/cpu/mcf5445x/cpu.c cpu specific code
-- arch/m68k/cpu/mcf5445x/cpu_init.c Flexbus ChipSelect, Mux pins setup, icache and RTC extra regs
-- arch/m68k/cpu/mcf5445x/interrupts.c cpu specific interrupt support
-- arch/m68k/cpu/mcf5445x/speed.c system, pci, flexbus, and cpu clock
-- arch/m68k/cpu/mcf5445x/Makefile Makefile
-- arch/m68k/cpu/mcf5445x/config.mk config make
-- arch/m68k/cpu/mcf5445x/start.S start up assembly code
-
-- board/freescale/m54455evb/README This readme file
-
-- drivers/net/mcffec.c ColdFire common FEC driver
-- drivers/serial/mcfuart.c ColdFire common UART driver
-
-- include/asm-m68k/bitops.h Bit operation function export
-- include/asm-m68k/byteorder.h Byte order functions
-- include/asm-m68k/fec.h FEC structure and definition
-- include/asm-m68k/fsl_i2c.h I2C structure and definition
-- include/asm-m68k/global_data.h Global data structure
-- include/asm-m68k/immap.h ColdFire specific header file and driver macros
-- include/asm-m68k/immap_5445x.h mcf5445x specific header file
-- include/asm-m68k/io.h io functions
-- include/asm-m68k/m5445x.h mcf5445x specific header file
-- include/asm-m68k/posix_types.h Posix
-- include/asm-m68k/processor.h header file
-- include/asm-m68k/ptrace.h Exception structure
-- include/asm-m68k/rtc.h Realtime clock header file
-- include/asm-m68k/string.h String function export
-- include/asm-m68k/timer.h Timer structure and definition
-- include/asm-m68k/types.h Data types definition
-- include/asm-m68k/uart.h Uart structure and definition
-- include/asm-m68k/u-boot.h U-Boot structure
-
-- include/configs/M54455EVB.h Board specific configuration file
-
-- arch/m68k/lib/board.c board init function
-- arch/m68k/lib/cache.c
-- arch/m68k/lib/interrupts Coldfire common interrupt functions
-- arch/m68k/lib/m68k_linux.c
-- arch/m68k/lib/time.c Timer functions (Dma timer and PIT)
-- arch/m68k/lib/traps.c Exception init code
-
-- rtc/mcfrtc.c Realtime clock Driver
-
-1 MCF5445x specific Options/Settings
-====================================
-1.1 pre-loader is no longer suppoer in thie coldfire family
-
-1.2 Configuration settings for M54455EVB Development Board
-CONFIG_MCF5445x -- define for all MCF5445x CPUs
-CONFIG_M54455 -- define for all Freescale MCF54455 CPUs
-CONFIG_M54455EVB -- define for M54455EVB board
-
-CONFIG_MCFUART -- define to use common CF Uart driver
-CONFIG_SYS_UART_PORT -- define UART port number, start with 0, 1 and 2
-CONFIG_BAUDRATE -- define UART baudrate
-
-CONFIG_MCFRTC -- define to use common CF RTC driver
-CONFIG_SYS_MCFRTC_BASE -- provide base address for RTC in immap.h
-CONFIG_SYS_RTC_OSCILLATOR -- define RTC clock frequency
-RTC_DEBUG -- define to show RTC debug message
-CONFIG_CMD_DATE -- enable to use date feature in U-Boot
-
-CONFIG_MCFFEC -- define to use common CF FEC driver
-CONFIG_MII -- enable to use MII driver
-CONFIG_CF_DOMII -- enable to use MII feature in cmd_mii.c
-CONFIG_SYS_DISCOVER_PHY -- enable PHY discovery
-CONFIG_SYS_RX_ETH_BUFFER -- Set FEC Receive buffer
-CONFIG_SYS_FAULT_ECHO_LINK_DOWN--
-CONFIG_SYS_FEC0_PINMUX -- Set FEC0 Pin configuration
-CONFIG_SYS_FEC1_PINMUX -- Set FEC1 Pin configuration
-CONFIG_SYS_FEC0_MIIBASE -- Set FEC0 MII base register
-CONFIG_SYS_FEC1_MIIBASE -- Set FEC0 MII base register
-MCFFEC_TOUT_LOOP -- set FEC timeout loop
-CONFIG_HAS_ETH1 -- define to enable second FEC in U-Boot
-
-CONFIG_ISO_PARTITION -- enable ISO read/write
-CONFIG_DOS_PARTITION -- enable DOS read/write
-CONFIG_IDE_RESET -- define ide_reset()
-CONFIG_IDE_PREINIT -- define ide_preinit()
-CONFIG_ATAPI -- define ATAPI support
-CONFIG_LBA48 -- define LBA48 (larger than 120GB) support
-CONFIG_SYS_IDE_MAXBUS -- define max channel
-CONFIG_SYS_IDE_MAXDEVICE -- define max devices per channel
-CONFIG_SYS_ATA_BASE_ADDR -- define ATA base address
-CONFIG_SYS_ATA_IDE0_OFFSET -- define ATA IDE0 offset
-CONFIG_SYS_ATA_DATA_OFFSET -- define ATA data IO
-CONFIG_SYS_ATA_REG_OFFSET -- define for normal register accesses
-CONFIG_SYS_ATA_ALT_OFFSET -- define for alternate registers
-CONFIG_SYS_ATA_STRIDE -- define for Interval between registers
-_IO_BASE -- define for IO base address
-
-CONFIG_MCFTMR -- define to use DMA timer
-
-CONFIG_SYS_FSL_I2C -- define to use FSL common I2C driver
-CONFIG_SYS_I2C_SOFT -- define for I2C bit-banged
-CONFIG_SYS_I2C_SPEED -- define for I2C speed
-CONFIG_SYS_I2C_SLAVE -- define for I2C slave address
-CONFIG_SYS_I2C_OFFSET -- define for I2C base address offset
-CONFIG_SYS_IMMR -- define for MBAR offset
-
-CONFIG_PCI -- define for PCI support
-CONFIG_PCI_PNP -- define for Plug n play support
-CONFIG_SYS_PCI_MEM_BUS -- PCI memory logical offset
-CONFIG_SYS_PCI_MEM_PHYS -- PCI memory physical offset
-CONFIG_SYS_PCI_MEM_SIZE -- PCI memory size
-CONFIG_SYS_PCI_IO_BUS -- PCI IO logical offset
-CONFIG_SYS_PCI_IO_PHYS -- PCI IO physical offset
-CONFIG_SYS_PCI_IO_SIZE -- PCI IO size
-CONFIG_SYS_PCI_CFG_BUS -- PCI Configuration logical offset
-CONFIG_SYS_PCI_CFG_PHYS -- PCI Configuration physical offset
-CONFIG_SYS_PCI_CFG_SIZE -- PCI Configuration size
-
-CONFIG_EXTRA_CLOCK -- Enable extra clock such as vco, flexbus, pci, etc
-
-CONFIG_SYS_MBAR -- define MBAR offset
-
-CONFIG_SYS_ATMEL_BOOT -- To determine the U-Boot is booted from Atmel or Intel
-
-CONFIG_MONITOR_IS_IN_RAM -- Not support
-
-CONFIG_SYS_INIT_RAM_ADDR -- defines the base address of the MCF54455 internal SRAM
-
-CONFIG_SYS_CSn_BASE -- defines the Chip Select Base register
-CONFIG_SYS_CSn_MASK -- defines the Chip Select Mask register
-CONFIG_SYS_CSn_CTRL -- defines the Chip Select Control register
-
-CONFIG_SYS_ATMEL_BASE -- defines the Atmel Flash base
-CONFIG_SYS_INTEL_BASE -- defines the Intel Flash base
-
-CONFIG_SYS_SDRAM_BASE -- defines the DRAM Base
-CONFIG_SYS_SDRAM_BASE1 -- defines the DRAM Base 1
-
-2. MEMORY MAP UNDER U-BOOT AND LINUX KERNEL
-===========================================
-2.1. System memory map:
- Flash: 0x00000000-0x3FFFFFFF (1024MB)
- DDR: 0x40000000-0x7FFFFFFF (1024MB)
- SRAM: 0x80000000-0x8FFFFFFF (256MB)
- ATA: 0x90000000-0x9FFFFFFF (256MB)
- PCI: 0xA0000000-0xBFFFFFFF (512MB)
- FlexBus: 0xC0000000-0xDFFFFFFF (512MB)
- IP: 0xF0000000-0xFFFFFFFF (256MB)
-
-2.2. For the initial bringup, we adopted a consistent memory scheme between U-Boot and
- linux kernel, you can customize it based on your system requirements:
- Atmel boot:
- Flash0: 0x00000000-0x0007FFFF (512KB)
- Flash1: 0x04000000-0x05FFFFFF (32MB)
- Intel boot:
- Flash0: 0x00000000-0x01FFFFFF (32MB)
- Flash1: 0x04000000-0x0407FFFF (512KB)
-
- CPLD: 0x08000000-0x08FFFFFF (16MB)
- FPGA: 0x09000000-0x09FFFFFF (16MB)
- DDR: 0x40000000-0x4FFFFFFF (256MB)
- SRAM: 0x80000000-0x80007FFF (32KB)
- IP: 0xFC000000-0xFC0FFFFF (64KB)
-
-3. SWITCH SETTINGS
-==================
-3.1 SW1 Pin3: 0 - Boot from Atmel or 1 - INTEL
- SW1 Pin4: 0 - ULPI chip not in reset state or 1 - ULPI chip in reset state
- SW1 Pin5: 0 - Full ATA Bus enabled, FEC Phy1 powered down
- 1 - Upper 8 bits ATA data bus disabled, FEC PHY1 active
- SW1 Pin6: 0 - FEC Phy0 active or 1 - FEC Phy0 powered down
- SW1 Pin3: 0 - Boot from Atmel or 1 - INTEL
-
-4. COMPILATION
-==============
-4.1 To create U-Boot the gcc-4.1-32 compiler set (ColdFire ELF version)
-from codesourcery.com was used. Download it from:
-http://www.codesourcery.com/gnu_toolchains/coldfire/download.html
-
-4.2 Compilation
- export CROSS_COMPILE=cross-compile-prefix
- cd u-boot-1.x.x
- make distclean
- make M54455EVB_config, or - default to atmel 33Mhz input clock
- make M54455EVB_atmel_config, or - default to atmel 33Mhz input clock
- make M54455EVB_a33_config, or - default to atmel 33Mhz input clock
- make M54455EVB_a66_config, or - default to atmel 66Mhz input clock
- make M54455EVB_intel_config, or - default to intel 33Mhz input clock
- make M54455EVB_i33_config, or - default to intel 33Mhz input clock
- make M54455EVB_i66_config, or - default to intel 66Mhz input clock
- make
-
-5. SCREEN DUMP
-==============
-5.1 M54455EVB Development board
- Boot from Atmel (NOTE: May not show exactly the same)
-
-U-Boot 1.2.0-g98c80b46-dirty (Jul 26 2007 - 12:44:08)
-
-CPU: Freescale MCF54455 (Mask:48 Version:1)
- CPU CLK 266 Mhz BUS CLK 133 Mhz FLB CLK 66 Mhz
- PCI CLK 33 Mhz INP CLK 33 Mhz VCO CLK 533 Mhz
-Board: Freescale M54455 EVB
-I2C: ready
-DRAM: 256 MB
-FLASH: 16.5 MB
-In: serial
-Out: serial
-Err: serial
-Net: FEC0, FEC1
-IDE: Bus 0: not available
--> print
-bootargs=root=/dev/ram rw
-bootdelay=1
-baudrate=115200
-ethaddr=00:e0:0c:bc:e5:60
-eth1addr=00:e0:0c:bc:e5:61
-hostname=M54455EVB
-netdev=eth0
-inpclk=33333333
-loadaddr=40010000
-load=tftp ${loadaddr) ${u-boot}
-upd=run load; run prog
-prog=prot off 0 2ffff;era 0 2ffff;cp.b ${loadaddr} 0 ${filesize};save
-ethact=FEC0
-mtdids=nor0=M54455EVB-1
-mtdparts=M54455EVB-1:16m(user)
-u-boot=u-boot54455.bin
-filesize=292b4
-fileaddr=40010000
-gatewayip=192.168.1.1
-netmask=255.255.255.0
-ipaddr=192.168.1.3
-serverip=192.168.1.2
-stdin=serial
-stdout=serial
-stderr=serial
-mem=261632k
-
-Environment size: 563/8188 bytes
--> bdinfo
-memstart = 0x40000000
-memsize = 0x10000000
-flashstart = 0x00000000
-flashsize = 0x01080000
-flashoffset = 0x00000000
-sramstart = 0x80000000
-sramsize = 0x00008000
-mbar = 0xFC000000
-busfreq = 133.333 MHz
-pcifreq = 33.333 MHz
-flbfreq = 66.666 MHz
-inpfreq = 33.333 MHz
-vcofreq = 533.333 MHz
-ethaddr = 00:E0:0C:BC:E5:60
-eth1addr = 00:E0:0C:BC:E5:61
-ip_addr = 192.168.1.3
-baudrate = 115200 bps
-->
--> help
-? - alias for 'help'
-base - print or set address offset
-bdinfo - print Board Info structure
-boot - boot default, i.e., run 'bootcmd'
-bootd - boot default, i.e., run 'bootcmd'
-bootelf - Boot from an ELF image in memory
-bootm - boot application image from memory
-bootp - boot image via network using BootP/TFTP protocol
-bootvx - Boot vxWorks from an ELF image
-cmp - memory compare
-coninfo - print console devices and information
-cp - memory copy
-crc32 - checksum calculation
-date - get/set/reset date & time
-dcache - enable or disable data cache
-diskboot- boot from IDE device
-echo - echo args to console
-erase - erase FLASH memory
-ext2load- load binary file from a Ext2 filesystem
-ext2ls - list files in a directory (default /)
-fatinfo - print information about filesystem
-fatload - load binary file from a dos filesystem
-fatls - list files in a directory (default /)
-flinfo - print FLASH memory information
-fsinfo - print information about filesystems
-fsload - load binary file from a filesystem image
-go - start application at address 'addr'
-help - print online help
-i2c - I2C sub-system
-icache - enable or disable instruction cache
-ide - IDE sub-system
-iminfo - print header information for application image
-imls - list all images found in flash
-itest - return true/false on integer compare
-loadb - load binary file over serial line (kermit mode)
-loads - load S-Record file over serial line
-loady - load binary file over serial line (ymodem mode)
-loop - infinite loop on address range
-ls - list files in a directory (default /)
-md - memory display
-mii - MII utility commands
-mm - memory modify (auto-incrementing)
-mtest - simple RAM test
-mw - memory write (fill)
-nfs - boot image via network using NFS protocol
-nm - memory modify (constant address)
-pci - list and access PCI Configuration Space
-ping - send ICMP ECHO_REQUEST to network host
-printenv- print environment variables
-protect - enable or disable FLASH write protection
-rarpboot- boot image via network using RARP/TFTP protocol
-reset - Perform RESET of the CPU
-run - run commands in an environment variable
-saveenv - save environment variables to persistent storage
-setenv - set environment variables
-sleep - delay execution for some time
-source - run script from memory
-tftpboot- boot image via network using TFTP protocol
-version - print monitor version
-->bootm 4000000
-
-## Booting image at 04000000 ...
- Image Name: Linux Kernel Image
- Created: 2007-08-14 15:13:00 UTC
- Image Type: M68K Linux Kernel Image (uncompressed)
- Data Size: 2301952 Bytes = 2.2 MB
- Load Address: 40020000
- Entry Point: 40020000
- Verifying Checksum ... OK
-OK
-Linux version 2.6.20-gfe5136d6-dirty (mattw@kea) (gcc version 4.2.0 20070318 (pr
-erelease) (Sourcery G++ Lite 4.2-20)) #108 Mon Aug 13 13:00:13 MDT 2007
-starting up linux startmem 0xc0254000, endmem 0xcfffffff, size 253MB
-Built 1 zonelists. Total pages: 32624
-Kernel command line: root=/dev/mtdblock1 rw rootfstype=jffs2 ip=none mtdparts=ph
-ysmap-flash.0:5M(kernel)ro,-(jffs2)
-PID hash table entries: 1024 (order: 10, 4096 bytes)
-Console: colour dummy device 80x25
-Dentry cache hash table entries: 32768 (order: 4, 131072 bytes)
-Inode-cache hash table entries: 16384 (order: 3, 65536 bytes)
-Memory: 257496k/262136k available (1864k kernel code, 2440k data, 88k init)
-Mount-cache hash table entries: 1024
-NET: Registered protocol family 16
-SCSI subsystem initialized
-NET: Registered protocol family 2
-IP route cache hash table entries: 2048 (order: 0, 8192 bytes)
-TCP established hash table entries: 8192 (order: 2, 32768 bytes)
-TCP bind hash table entries: 4096 (order: 1, 16384 bytes)
-TCP: Hash tables configured (established 8192 bind 4096)
-TCP reno registered
-JFFS2 version 2.2. (NAND) (C) 2001-2006 Red Hat, Inc.
-io scheduler noop registered
-io scheduler anticipatory registered
-io scheduler deadline registered
-io scheduler cfq registered (default)
-ColdFire internal UART serial driver version 1.00
-ttyS0 at 0xfc060000 (irq = 90) is a builtin ColdFire UART
-ttyS1 at 0xfc064000 (irq = 91) is a builtin ColdFire UART
-ttyS2 at 0xfc068000 (irq = 92) is a builtin ColdFire UART
-RAMDISK driver initialized: 16 RAM disks of 64000K size 1024 blocksize
-loop: loaded (max 8 devices)
-FEC ENET Version 0.2
-fec: PHY @ 0x0, ID 0x20005ca2 -- DP83849
-eth0: ethernet 00:08:ee:00:e4:19
-physmap platform flash device: 01000000 at 04000000
-physmap-flash.0: Found 1 x16 devices at 0x0 in 8-bit bank
- Intel/Sharp Extended Query Table at 0x0031
-Using buffer write method
-cfi_cmdset_0001: Erase suspend on write enabled
-2 cmdlinepart partitions found on MTD device physmap-flash.0
-Creating 2 MTD partitions on "physmap-flash.0":
-0x00000000-0x00500000 : "kernel"
-mtd: Giving out device 0 to kernel
-0x00500000-0x01000000 : "jffs2"
-mtd: Giving out device 1 to jffs2
-mice: PS/2 mouse device common for all mice
-i2c /dev entries driver
-TCP cubic registered
-NET: Registered protocol family 1
-NET: Registered protocol family 17
-NET: Registered protocol family 15
-VFS: Mounted root (jffs2 filesystem).
-Setting the hostname to freescale
-Mounting filesystems
-mount: Mounting usbfs on /proc/bus/usb failed: No such file or directory
-Starting syslogd and klogd
-Setting up networking on loopback device:
-Setting up networking on eth0:
-eth0: config: auto-negotiation on, 100FDX, 100HDX, 10FDX, 10HDX.
-Adding static route for default gateway to 172.27.255.254:
-Setting nameserver to 172.27.0.1 in /etc/resolv.conf:
-Starting inetd:
-/ #
diff --git a/board/freescale/m54455evb/m54455evb.c b/board/freescale/m54455evb/m54455evb.c
deleted file mode 100644
index c749ee4..0000000
--- a/board/freescale/m54455evb/m54455evb.c
+++ /dev/null
@@ -1,217 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * (C) Copyright 2000-2003
- * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
- *
- * Copyright (C) 2004-2007, 2012 Freescale Semiconductor, Inc.
- * TsiChung Liew (Tsi-Chung.Liew@freescale.com)
- */
-
-#include <common.h>
-#include <init.h>
-#include <pci.h>
-#include <asm/global_data.h>
-#include <asm/immap.h>
-#include <asm/io.h>
-#include <linux/delay.h>
-
-DECLARE_GLOBAL_DATA_PTR;
-
-int checkboard(void)
-{
- puts("Board: ");
- puts("Freescale M54455 EVB\n");
- return 0;
-};
-
-int dram_init(void)
-{
- u32 dramsize;
-#ifdef CONFIG_CF_SBF
- /*
- * Serial Boot: The dram is already initialized in start.S
- * only require to return DRAM size
- */
- dramsize = CONFIG_SYS_SDRAM_SIZE * 0x100000 >> 1;
-#else
- sdramc_t *sdram = (sdramc_t *)(MMAP_SDRAM);
- gpio_t *gpio = (gpio_t *)(MMAP_GPIO);
- u32 i;
-
- dramsize = CONFIG_SYS_SDRAM_SIZE * 0x100000 >> 1;
-
- for (i = 0x13; i < 0x20; i++) {
- if (dramsize == (1 << i))
- break;
- }
- i--;
-
- out_8(&gpio->mscr_sdram, CONFIG_SYS_SDRAM_DRV_STRENGTH);
-
- out_be32(&sdram->sdcs0, CONFIG_SYS_SDRAM_BASE | i);
- out_be32(&sdram->sdcs1, CONFIG_SYS_SDRAM_BASE1 | i);
-
- out_be32(&sdram->sdcfg1, CONFIG_SYS_SDRAM_CFG1);
- out_be32(&sdram->sdcfg2, CONFIG_SYS_SDRAM_CFG2);
-
- /* Issue PALL */
- out_be32(&sdram->sdcr, CONFIG_SYS_SDRAM_CTRL | 2);
-
- /* Issue LEMR */
- out_be32(&sdram->sdmr, CONFIG_SYS_SDRAM_EMOD | 0x408);
- out_be32(&sdram->sdmr, CONFIG_SYS_SDRAM_MODE | 0x300);
-
- udelay(500);
-
- /* Issue PALL */
- out_be32(&sdram->sdcr, CONFIG_SYS_SDRAM_CTRL | 2);
-
- /* Perform two refresh cycles */
- out_be32(&sdram->sdcr, CONFIG_SYS_SDRAM_CTRL | 4);
- out_be32(&sdram->sdcr, CONFIG_SYS_SDRAM_CTRL | 4);
-
- out_be32(&sdram->sdmr, CONFIG_SYS_SDRAM_MODE | 0x200);
-
- out_be32(&sdram->sdcr,
- (CONFIG_SYS_SDRAM_CTRL & ~0x80000000) | 0x10000c00);
-
- udelay(100);
-#endif
- gd->ram_size = dramsize << 1;
-
- return 0;
-};
-
-int testdram(void)
-{
- /* TODO: XXX XXX XXX */
- printf("DRAM test not implemented!\n");
-
- return (0);
-}
-
-#if defined(CONFIG_IDE)
-#include <ata.h>
-
-int ide_preinit(void)
-{
- gpio_t *gpio = (gpio_t *) MMAP_GPIO;
- u32 tmp;
-
- tmp = (in_8(&gpio->par_fec) & GPIO_PAR_FEC_FEC1_UNMASK) | 0x10;
- setbits_8(&gpio->par_fec, tmp);
- tmp = ((in_be16(&gpio->par_feci2c) & 0xf0ff) |
- (GPIO_PAR_FECI2C_MDC1_ATA_DIOR | GPIO_PAR_FECI2C_MDIO1_ATA_DIOW));
- setbits_be16(&gpio->par_feci2c, tmp);
-
- setbits_be16(&gpio->par_ata,
- GPIO_PAR_ATA_BUFEN | GPIO_PAR_ATA_CS1 | GPIO_PAR_ATA_CS0 |
- GPIO_PAR_ATA_DA2 | GPIO_PAR_ATA_DA1 | GPIO_PAR_ATA_DA0 |
- GPIO_PAR_ATA_RESET_RESET | GPIO_PAR_ATA_DMARQ_DMARQ |
- GPIO_PAR_ATA_IORDY_IORDY);
- setbits_be16(&gpio->par_pci,
- GPIO_PAR_PCI_GNT3_ATA_DMACK | GPIO_PAR_PCI_REQ3_ATA_INTRQ);
-
- return (0);
-}
-
-void ide_set_reset(int idereset)
-{
- atac_t *ata = (atac_t *) MMAP_ATA;
- long period;
- /* t1, t2, t3, t4, t5, t6, t9, tRD, tA */
- int piotms[5][9] = {
- {70, 165, 60, 30, 50, 5, 20, 0, 35}, /* PIO 0 */
- {50, 125, 45, 20, 35, 5, 15, 0, 35}, /* PIO 1 */
- {30, 100, 30, 15, 20, 5, 10, 0, 35}, /* PIO 2 */
- {30, 80, 30, 10, 20, 5, 10, 0, 35}, /* PIO 3 */
- {25, 70, 20, 10, 20, 5, 10, 0, 35}
- }; /* PIO 4 */
-
- if (idereset) {
- /* control reset */
- out_8(&ata->cr, 0);
- udelay(10000);
- } else {
-#define CALC_TIMING(t) (t + period - 1) / period
- period = 1000000000 / gd->bus_clk; /* period in ns */
-
- /*ata->ton = CALC_TIMING (180); */
- out_8(&ata->t1, CALC_TIMING(piotms[2][0]));
- out_8(&ata->t2w, CALC_TIMING(piotms[2][1]));
- out_8(&ata->t2r, CALC_TIMING(piotms[2][1]));
- out_8(&ata->ta, CALC_TIMING(piotms[2][8]));
- out_8(&ata->trd, CALC_TIMING(piotms[2][7]));
- out_8(&ata->t4, CALC_TIMING(piotms[2][3]));
- out_8(&ata->t9, CALC_TIMING(piotms[2][6]));
-
- /* IORDY enable */
- out_8(&ata->cr, 0x40);
- udelay(200000);
- /* IORDY enable */
- setbits_8(&ata->cr, 0x01);
- }
-}
-#endif
-
-#if defined(CONFIG_PCI)
-/*
- * Initialize PCI devices, report devices found.
- */
-static struct pci_controller hose;
-extern void pci_mcf5445x_init(struct pci_controller *hose);
-
-void pci_init_board(void)
-{
- pci_mcf5445x_init(&hose);
-}
-#endif /* CONFIG_PCI */
-
-#if defined(CONFIG_FLASH_CFI_LEGACY)
-#include <flash.h>
-ulong board_flash_get_legacy (ulong base, int banknum, flash_info_t * info)
-{
- int sect[] = CONFIG_SYS_ATMEL_SECT;
- int sectsz[] = CONFIG_SYS_ATMEL_SECTSZ;
- int i, j, k;
-
- if (base != CONFIG_SYS_ATMEL_BASE)
- return 0;
-
- info->flash_id = 0x01000000;
- info->portwidth = 1;
- info->chipwidth = 1;
- info->buffer_size = 1;
- info->erase_blk_tout = 16384;
- info->write_tout = 2;
- info->buffer_write_tout = 5;
- info->vendor = 0xFFF0; /* CFI_CMDSET_AMD_LEGACY */
- info->cmd_reset = 0x00F0;
- info->interface = FLASH_CFI_X8;
- info->legacy_unlock = 0;
- info->manufacturer_id = (u16) ATM_MANUFACT;
- info->device_id = ATM_ID_LV040;
- info->device_id2 = 0;
-
- info->ext_addr = 0;
- info->cfi_version = 0x3133;
- info->cfi_offset = 0x0000;
- info->addr_unlock1 = 0x00000555;
- info->addr_unlock2 = 0x000002AA;
- info->name = "CFI conformant";
-
- info->size = 0;
- info->sector_count = CONFIG_SYS_ATMEL_TOTALSECT;
- info->start[0] = base;
- for (k = 0, i = 0; i < CONFIG_SYS_ATMEL_REGION; i++) {
- info->size += sect[i] * sectsz[i];
-
- for (j = 0; j < sect[i]; j++, k++) {
- info->start[k + 1] = info->start[k] + sectsz[i];
- info->protect[k] = 0;
- }
- }
-
- return 1;
-}
-#endif /* CONFIG_SYS_FLASH_CFI */
diff --git a/board/freescale/m54455evb/sbf_dram_init.S b/board/freescale/m54455evb/sbf_dram_init.S
deleted file mode 100644
index fe5bb05..0000000
--- a/board/freescale/m54455evb/sbf_dram_init.S
+++ /dev/null
@@ -1,100 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0+ */
-/*
- * Board-specific sbf ddr/sdram init.
- *
- * (C) Copyright 2017 Angelo Dureghello <angelo@sysam.it>
- */
-
- #include <config.h>
-
-.global sbf_dram_init
-.text
-
-sbf_dram_init:
- /* Dram Initialization a1, a2, and d0 */
- /* mscr sdram */
- move.l #0xFC0A4074, %a1
- move.b #(CONFIG_SYS_SDRAM_DRV_STRENGTH), (%a1)
- nop
-
- /* SDRAM Chip 0 and 1 */
- move.l #0xFC0B8110, %a1
- move.l #0xFC0B8114, %a2
-
- /* calculate the size */
- move.l #0x13, %d1
- move.l #(CONFIG_SYS_SDRAM_SIZE), %d2
-#ifdef CONFIG_SYS_SDRAM_BASE1
- lsr.l #1, %d2
-#endif
-
-dramsz_loop:
- lsr.l #1, %d2
- add.l #1, %d1
- cmp.l #1, %d2
- bne dramsz_loop
-#ifdef CONFIG_SYS_NAND_BOOT
- beq asm_nand_chk_status
-#endif
- /* SDRAM Chip 0 and 1 */
- move.l #(CONFIG_SYS_SDRAM_BASE), (%a1)
- or.l %d1, (%a1)
-#ifdef CONFIG_SYS_SDRAM_BASE1
- move.l #(CONFIG_SYS_SDRAM_BASE1), (%a2)
- or.l %d1, (%a2)
-#endif
- nop
-
- /* dram cfg1 and cfg2 */
- move.l #0xFC0B8008, %a1
- move.l #(CONFIG_SYS_SDRAM_CFG1), (%a1)
- nop
- move.l #0xFC0B800C, %a2
- move.l #(CONFIG_SYS_SDRAM_CFG2), (%a2)
- nop
-
- move.l #0xFC0B8000, %a1 /* Mode */
- move.l #0xFC0B8004, %a2 /* Ctrl */
-
- /* Issue PALL */
- move.l #(CONFIG_SYS_SDRAM_CTRL + 2), (%a2)
- nop
-
- /* Issue LEMR */
- move.l #(CONFIG_SYS_SDRAM_EMOD + 0x408), (%a1)
- nop
- move.l #(CONFIG_SYS_SDRAM_MODE + 0x300), (%a1)
- nop
-
- move.l #1000, %d1
- bsr asm_delay
-
- /* Issue PALL */
- move.l #(CONFIG_SYS_SDRAM_CTRL + 2), (%a2)
- nop
-
- /* Perform two refresh cycles */
- move.l #(CONFIG_SYS_SDRAM_CTRL + 4), %d0
- nop
- move.l %d0, (%a2)
- move.l %d0, (%a2)
- nop
-
- move.l #(CONFIG_SYS_SDRAM_MODE + 0x200), (%a1)
- nop
-
- move.l #500, %d1
- bsr asm_delay
-
- move.l #(CONFIG_SYS_SDRAM_CTRL), %d1
- and.l #0x7FFFFFFF, %d1
-
- or.l #0x10000C00, %d1
-
- move.l %d1, (%a2)
- nop
-
- move.l #2000, %d1
- bsr asm_delay
-
- rts
diff --git a/board/freescale/mpc837xerdb/mpc837xerdb.c b/board/freescale/mpc837xerdb/mpc837xerdb.c
index 66b3d9a..84671f6 100644
--- a/board/freescale/mpc837xerdb/mpc837xerdb.c
+++ b/board/freescale/mpc837xerdb/mpc837xerdb.c
@@ -220,7 +220,7 @@
int board_late_init(void)
{
volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR;
-#ifdef CONFIG_USB
+#ifdef CONFIG_USB_HOST
clrsetbits_be32(&immap->sysconf.sicrl, SICRL_USB_A, 0x40000000);
#endif
return 0;
diff --git a/board/freescale/mx6sxsabresd/mx6sxsabresd.c b/board/freescale/mx6sxsabresd/mx6sxsabresd.c
index 57fab23..e7958df 100644
--- a/board/freescale/mx6sxsabresd/mx6sxsabresd.c
+++ b/board/freescale/mx6sxsabresd/mx6sxsabresd.c
@@ -320,7 +320,10 @@
int checkboard(void)
{
+#ifdef CONFIG_NXP_BOARD_REVISION
printf("Board: MX6SX SABRE SDB rev%c\n", nxp_board_rev_string());
-
+#else
+ puts("Board: MX6SX SABRE SDB");
+#endif
return 0;
}
diff --git a/board/gateworks/gw_ventana/common.c b/board/gateworks/gw_ventana/common.c
index 4627a15..c07eb62 100644
--- a/board/gateworks/gw_ventana/common.c
+++ b/board/gateworks/gw_ventana/common.c
@@ -1550,6 +1550,17 @@
int board = read_eeprom(CONFIG_I2C_GSC, &ventana_info);
const int i2c_pmic = 1;
u32 reg;
+ char rev;
+ int i;
+
+ /* determine board revision */
+ rev = 'A';
+ for (i = sizeof(ventana_info.model) - 1; i > 0; i--) {
+ if (ventana_info.model[i] >= 'A') {
+ rev = ventana_info.model[i];
+ break;
+ }
+ }
i2c_set_bus_num(i2c_pmic);
@@ -1573,7 +1584,44 @@
reg &= ~(SWBST_MODE_MASK | SWBST_VOL_MASK);
reg |= (SWBST_5_00V | (SWBST_MODE_AUTO << SWBST_MODE_SHIFT));
pmic_reg_write(p, PFUZE100_SWBSTCON1, reg);
+
+ if (board == GW54xx && (rev == 'G')) {
+ /* Disable VGEN5 */
+ pmic_reg_write(p, PFUZE100_VGEN5VOL, 0);
+
+ /* Set VGEN6 to 2.5V and enable */
+ pmic_reg_read(p, PFUZE100_VGEN6VOL, ®);
+ reg &= ~(LDO_VOL_MASK);
+ reg |= (LDOB_2_50V | LDO_EN);
+ pmic_reg_write(p, PFUZE100_VGEN6VOL, reg);
+ }
}
+
+ /* put all switchers in continuous mode */
+ pmic_reg_read(p, PFUZE100_SW1ABMODE, ®);
+ reg &= ~(SW_MODE_MASK);
+ reg |= PWM_PWM;
+ pmic_reg_write(p, PFUZE100_SW1ABMODE, reg);
+
+ pmic_reg_read(p, PFUZE100_SW2MODE, ®);
+ reg &= ~(SW_MODE_MASK);
+ reg |= PWM_PWM;
+ pmic_reg_write(p, PFUZE100_SW2MODE, reg);
+
+ pmic_reg_read(p, PFUZE100_SW3AMODE, ®);
+ reg &= ~(SW_MODE_MASK);
+ reg |= PWM_PWM;
+ pmic_reg_write(p, PFUZE100_SW3AMODE, reg);
+
+ pmic_reg_read(p, PFUZE100_SW3BMODE, ®);
+ reg &= ~(SW_MODE_MASK);
+ reg |= PWM_PWM;
+ pmic_reg_write(p, PFUZE100_SW3BMODE, reg);
+
+ pmic_reg_read(p, PFUZE100_SW4MODE, ®);
+ reg &= ~(SW_MODE_MASK);
+ reg |= PWM_PWM;
+ pmic_reg_write(p, PFUZE100_SW4MODE, reg);
}
/* configure LTC3676 PMIC */
@@ -1640,6 +1688,12 @@
/* set SW3 (VDD_ARM) */
pmic_reg_write(p, LTC3676_DVB3A, 0x1f);
}
+
+ /* put all switchers in continuous mode */
+ pmic_reg_write(p, LTC3676_BUCK1, 0xc0);
+ pmic_reg_write(p, LTC3676_BUCK2, 0xc0);
+ pmic_reg_write(p, LTC3676_BUCK3, 0xc0);
+ pmic_reg_write(p, LTC3676_BUCK4, 0xc0);
}
}
@@ -1704,6 +1758,7 @@
return fsl_esdhc_initialize(bis, &usdhc_cfg[0]);
default:
/* doesn't have MMC */
+ printf("None");
return -1;
}
}
diff --git a/board/gateworks/gw_ventana/gw_ventana.c b/board/gateworks/gw_ventana/gw_ventana.c
index 1ed9c1a..468fb09 100644
--- a/board/gateworks/gw_ventana/gw_ventana.c
+++ b/board/gateworks/gw_ventana/gw_ventana.c
@@ -6,37 +6,23 @@
*/
#include <common.h>
-#include <init.h>
-#include <log.h>
-#include <net.h>
#include <asm/arch/clock.h>
#include <asm/arch/crm_regs.h>
-#include <asm/arch/iomux.h>
#include <asm/arch/mx6-pins.h>
#include <asm/arch/mxc_hdmi.h>
#include <asm/arch/sys_proto.h>
#include <asm/global_data.h>
#include <asm/gpio.h>
#include <asm/mach-imx/boot_mode.h>
-#include <asm/mach-imx/sata.h>
#include <asm/mach-imx/video.h>
-#include <asm/io.h>
#include <asm/setup.h>
-#include <dm.h>
#include <env.h>
#include <hwconfig.h>
-#include <i2c.h>
-#include <fdt_support.h>
-#include <jffs2/load_kernel.h>
#include <linux/ctype.h>
#include <miiphy.h>
#include <mtd_node.h>
-#include <pci.h>
#include <linux/delay.h>
-#include <linux/libfdt.h>
#include <power/pmic.h>
-#include <power/ltc3676_pmic.h>
-#include <power/pfuze100_pmic.h>
#include <fdt_support.h>
#include <jffs2/load_kernel.h>
@@ -95,6 +81,7 @@
/* Marvel 88E1510 */
if (phydev->phy_id == 0x1410dd1) {
+ puts("MV88E1510");
/*
* Page 3, Register 16: LED[2:0] Function Control Register
* LED[0] (SPD:Amber) R16_3.3:0 to 0111: on-GbE link
@@ -110,6 +97,13 @@
/* TI DP83867 */
else if (phydev->phy_id == 0x2000a231) {
+ puts("TIDP83867 ");
+ /* LED configuration */
+ val = 0;
+ val |= 0x5 << 4; /* LED1(Amber;Speed) : 1000BT link */
+ val |= 0xb << 8; /* LED2(Green;Link/Act): blink for TX/RX act */
+ phy_write(phydev, MDIO_DEVAD_NONE, 24, val);
+
/* configure register 0x170 for ref CLKOUT */
phy_write(phydev, MDIO_DEVAD_NONE, 13, 0x001f);
phy_write(phydev, MDIO_DEVAD_NONE, 14, 0x0170);
@@ -252,6 +246,27 @@
.sync = FB_SYNC_EXT,
.vmode = FB_VMODE_NONINTERLACED
} }, {
+ /* DLC0700XDP21LF-C-1 */
+ .bus = 0,
+ .addr = 0,
+ .detect = NULL,
+ .enable = enable_lvds,
+ .pixfmt = IPU_PIX_FMT_LVDS666,
+ .mode = {
+ .name = "DLC0700XDP21LF",
+ .refresh = 60,
+ .xres = 1024, /* 1024x600active pixels */
+ .yres = 600,
+ .pixclock = 15385, /* 64MHz */
+ .left_margin = 220,
+ .right_margin = 40,
+ .upper_margin = 21,
+ .lower_margin = 7,
+ .hsync_len = 60,
+ .vsync_len = 10,
+ .sync = FB_SYNC_EXT,
+ .vmode = FB_VMODE_NONINTERLACED
+} }, {
/* DLC800FIG-T-3 */
.bus = 2,
.addr = 0x14,
@@ -357,7 +372,7 @@
return 0;
}
-int imx6_pcie_toggle_reset(void)
+int imx6_pcie_toggle_reset(struct gpio_desc *gpio, bool active_high)
{
if (board_type < GW_UNKNOWN) {
uint pin = gpio_cfg[board_type].pcie_rst;
diff --git a/board/gateworks/venice/gsc.c b/board/gateworks/venice/gsc.c
index d2490e6..c75bc6f 100644
--- a/board/gateworks/venice/gsc.c
+++ b/board/gateworks/venice/gsc.c
@@ -176,7 +176,7 @@
chksum += buf[i];
if ((info->chksum[0] != chksum >> 8) ||
(info->chksum[1] != (chksum & 0xff))) {
- printf("EEPROM: I2C%d@0x%02x: Invalid Model in EEPROM\n", bus, slave);
+ printf("EEPROM: I2C%d@0x%02x: Invalid Checksum\n", bus, slave);
print_hex_dump_bytes("", DUMP_PREFIX_NONE, buf, sizeof(*info));
memset(info, 0, sizeof(*info));
return -EINVAL;
@@ -221,9 +221,11 @@
/* thermal protection */
if (!dm_i2c_read(dev, GSC_SC_THERM_PROTECT, ®, 1)) {
- reg |= 1;
- dm_i2c_write(dev, GSC_SC_THERM_PROTECT, ®, 1);
- strcat(str, " Thermal Protection Enabled");
+ strcat(str, " Thermal Protection ");
+ if (reg & BIT(0))
+ strcat(str, "Enabled");
+ else
+ strcat(str, "Disabled");
}
return str;
@@ -298,7 +300,7 @@
}
/* adjust by offset */
- val += offset;
+ val += (offset / 1000);
printf("%-8s: %d.%03dV\n", label, val / 1000, val % 1000);
break;
diff --git a/board/gateworks/venice/imx8mm_venice.c b/board/gateworks/venice/imx8mm_venice.c
index 1d51b6e..2657bd6 100644
--- a/board/gateworks/venice/imx8mm_venice.c
+++ b/board/gateworks/venice/imx8mm_venice.c
@@ -42,12 +42,16 @@
{
int i = 0;
const char *dtb;
+ static char init;
char buf[32];
do {
dtb = gsc_get_dtb_name(i++, buf, sizeof(buf));
- if (!strcmp(dtb, name))
+ if (!strcmp(dtb, name)) {
+ if (!init++)
+ printf("DTB : %s\n", name);
return 0;
+ }
} while (dtb);
return -1;
@@ -101,13 +105,26 @@
int board_late_init(void)
{
- const char *ethmac;
+ const char *str;
char env[32];
int ret, i;
u8 enetaddr[6];
+ char fdt[64];
led_default_state();
+ /* Set fdt_file vars */
+ i = 0;
+ do {
+ str = gsc_get_dtb_name(i, fdt, sizeof(fdt));
+ if (str) {
+ sprintf(env, "fdt_file%d", i + 1);
+ strcat(fdt, ".dtb");
+ env_set(env, fdt);
+ }
+ i++;
+ } while (str);
+
/* Set mac addrs */
i = 0;
do {
@@ -115,8 +132,8 @@
sprintf(env, "eth%daddr", i);
else
sprintf(env, "ethaddr");
- ethmac = env_get(env);
- if (!ethmac) {
+ str = env_get(env);
+ if (!str) {
ret = gsc_getmac(i, enetaddr);
if (!ret)
eth_env_set_enetaddr(env, enetaddr);
diff --git a/board/gateworks/venice/spl.c b/board/gateworks/venice/spl.c
index ea500d4..8c35775 100644
--- a/board/gateworks/venice/spl.c
+++ b/board/gateworks/venice/spl.c
@@ -26,6 +26,7 @@
#include <dm/uclass-internal.h>
#include <dm/device-internal.h>
+#include <power/bd71837.h>
#include <power/mp5416.h>
#include "gsc.h"
@@ -88,8 +89,23 @@
* Note that we can not use pmic dm drivers here as we have a generic
* venice dt that does not have board-specific pmic's defined.
*
- * Instead we must use dm_i2c.
+ * Instead we must use dm_i2c so we a helpers to give us
+ * clrsetbit functions we would otherwise have if we could use PMIC dm
+ * drivers.
*/
+static int dm_i2c_clrsetbits(struct udevice *dev, uint reg, uint clr, uint set)
+{
+ int ret;
+ u8 val;
+
+ ret = dm_i2c_read(dev, reg, &val, 1);
+ if (ret)
+ return ret;
+ val = (val & ~clr) | set;
+
+ return dm_i2c_write(dev, reg, &val, 1);
+}
+
static int power_init_board(void)
{
const char *model = gsc_get_model();
@@ -117,6 +133,43 @@
BIT(7) | MP5416_VSET_SW3_SVAL(920000));
}
+ else if (!strncmp(model, "GW7901", 6)) {
+ ret = uclass_get_device_by_name(UCLASS_I2C, "i2c@30a30000", &bus);
+ if (ret) {
+ printf("PMIC : failed I2C2 probe: %d\n", ret);
+ return ret;
+ }
+ ret = dm_i2c_probe(bus, 0x4b, 0, &dev);
+ if (ret) {
+ printf("PMIC : failed probe: %d\n", ret);
+ return ret;
+ }
+ puts("PMIC : BD71847\n");
+
+ /* unlock the PMIC regs */
+ dm_i2c_reg_write(dev, BD718XX_REGLOCK, 0x1);
+
+ /* set switchers to forced PWM mode */
+ dm_i2c_clrsetbits(dev, BD718XX_BUCK1_CTRL, 0, 0x8);
+ dm_i2c_clrsetbits(dev, BD718XX_BUCK2_CTRL, 0, 0x8);
+ dm_i2c_clrsetbits(dev, BD718XX_1ST_NODVS_BUCK_CTRL, 0, 0x8);
+ dm_i2c_clrsetbits(dev, BD718XX_2ND_NODVS_BUCK_CTRL, 0, 0x8);
+ dm_i2c_clrsetbits(dev, BD718XX_3RD_NODVS_BUCK_CTRL, 0, 0x8);
+ dm_i2c_clrsetbits(dev, BD718XX_4TH_NODVS_BUCK_CTRL, 0, 0x8);
+
+ /* increase VDD_0P95 (VDD_GPU/VPU/DRAM) to 0.975v for 1.5Ghz DDR */
+ dm_i2c_reg_write(dev, BD718XX_1ST_NODVS_BUCK_VOLT, 0x83);
+
+ /* increase VDD_SOC to 0.85v before first DRAM access */
+ dm_i2c_reg_write(dev, BD718XX_BUCK1_VOLT_RUN, 0x0f);
+
+ /* increase VDD_ARM to 0.92v for 800 and 1600Mhz */
+ dm_i2c_reg_write(dev, BD718XX_BUCK2_VOLT_RUN, 0x16);
+
+ /* Lock the PMIC regs */
+ dm_i2c_reg_write(dev, BD718XX_REGLOCK, 0x11);
+ }
+
return 0;
}
diff --git a/board/google/chromebook_coral/coral.c b/board/google/chromebook_coral/coral.c
index 3f9235c..85cba50 100644
--- a/board/google/chromebook_coral/coral.c
+++ b/board/google/chromebook_coral/coral.c
@@ -10,17 +10,21 @@
#include <command.h>
#include <cros_ec.h>
#include <dm.h>
+#include <init.h>
#include <log.h>
#include <sysinfo.h>
#include <acpi/acpigen.h>
#include <asm-generic/gpio.h>
#include <asm/acpi_nhlt.h>
+#include <asm/cb_sysinfo.h>
#include <asm/intel_gnvs.h>
#include <asm/intel_pinctrl.h>
#include <dm/acpi.h>
#include <linux/delay.h>
#include "variant_gpio.h"
+DECLARE_GLOBAL_DATA_PTR;
+
struct cros_gpio_info {
const char *linux_name;
enum cros_gpio_t type;
@@ -28,6 +32,30 @@
int flags;
};
+int misc_init_f(void)
+{
+ if (!ll_boot_init()) {
+ printf("Running as secondary loader");
+ if (gd->arch.coreboot_table) {
+ int ret;
+
+ printf(" (found coreboot table at %lx)",
+ gd->arch.coreboot_table);
+
+ ret = get_coreboot_info(&lib_sysinfo);
+ if (ret) {
+ printf("\nFailed to parse coreboot tables (err=%d)\n",
+ ret);
+ return ret;
+ }
+ }
+
+ printf("\n");
+ }
+
+ return 0;
+}
+
int arch_misc_init(void)
{
return 0;
diff --git a/board/imgtec/malta/malta.c b/board/imgtec/malta/malta.c
index c04f727..9af1f92 100644
--- a/board/imgtec/malta/malta.c
+++ b/board/imgtec/malta/malta.c
@@ -4,7 +4,8 @@
* Copyright (C) 2013 Imagination Technologies
*/
-#include <common.h>
+#include <config.h>
+#include <fdt_support.h>
#include <ide.h>
#include <init.h>
#include <net.h>
@@ -24,6 +25,9 @@
DECLARE_GLOBAL_DATA_PTR;
+#define MALTA_GT_PATH "/pci0@1be00000"
+#define MALTA_MSC_PATH "/pci0@1bd00000"
+
enum core_card {
CORE_UNKNOWN,
CORE_LV,
@@ -120,10 +124,12 @@
return 0;
}
+#if !IS_ENABLED(CONFIG_DM_ETH)
int board_eth_init(struct bd_info *bis)
{
return pci_eth_init(bis);
}
+#endif
void _machine_restart(void)
{
@@ -167,6 +173,77 @@
return 0;
}
+#if IS_ENABLED(CONFIG_OF_BOARD_FIXUP)
+/*
+ * TODO: currently doesn't work because rw_fdt_blob points to a
+ * NOR flash address. This needs some changes in board_init_f.
+ */
+int board_fix_fdt(void *rw_fdt_blob)
+{
+ int node = -1;
+
+ switch (malta_sys_con()) {
+ case SYSCON_GT64120:
+ node = fdt_path_offset(rw_fdt_blob, MALTA_GT_PATH);
+ break;
+ default:
+ case SYSCON_MSC01:
+ node = fdt_path_offset(rw_fdt_blob, MALTA_MSC_PATH);
+ break;
+ }
+
+ return fdt_status_okay(rw_fdt_blob, node);
+}
+#endif
+
+#if IS_ENABLED(CONFIG_DM_PCI)
+int board_early_init_r(void)
+{
+ struct udevice *dev;
+ int ret;
+
+ pci_init();
+
+ ret = dm_pci_find_device(PCI_VENDOR_ID_INTEL,
+ PCI_DEVICE_ID_INTEL_82371AB_0, 0, &dev);
+ if (ret)
+ panic("Failed to find PIIX4 PCI bridge\n");
+
+ /* setup PCI interrupt routing */
+ dm_pci_write_config8(dev, PCI_CFG_PIIX4_PIRQRCA, 10);
+ dm_pci_write_config8(dev, PCI_CFG_PIIX4_PIRQRCB, 10);
+ dm_pci_write_config8(dev, PCI_CFG_PIIX4_PIRQRCC, 11);
+ dm_pci_write_config8(dev, PCI_CFG_PIIX4_PIRQRCD, 11);
+
+ /* mux SERIRQ onto SERIRQ pin */
+ dm_pci_clrset_config32(dev, PCI_CFG_PIIX4_GENCFG, 0,
+ PCI_CFG_PIIX4_GENCFG_SERIRQ);
+
+ /* enable SERIRQ - Linux currently depends upon this */
+ dm_pci_clrset_config8(dev, PCI_CFG_PIIX4_SERIRQC, 0,
+ PCI_CFG_PIIX4_SERIRQC_EN | PCI_CFG_PIIX4_SERIRQC_CONT);
+
+ ret = dm_pci_find_device(PCI_VENDOR_ID_INTEL,
+ PCI_DEVICE_ID_INTEL_82371AB, 0, &dev);
+ if (ret)
+ panic("Failed to find PIIX4 IDE controller\n");
+
+ /* enable bus master & IO access */
+ dm_pci_clrset_config32(dev, PCI_COMMAND, 0,
+ PCI_COMMAND_MASTER | PCI_COMMAND_IO);
+
+ /* set latency */
+ dm_pci_write_config8(dev, PCI_LATENCY_TIMER, 0x40);
+
+ /* enable IDE/ATA */
+ dm_pci_write_config32(dev, PCI_CFG_PIIX4_IDETIM_PRI,
+ PCI_CFG_PIIX4_IDETIM_IDE);
+ dm_pci_write_config32(dev, PCI_CFG_PIIX4_IDETIM_SEC,
+ PCI_CFG_PIIX4_IDETIM_IDE);
+
+ return 0;
+}
+#else
void pci_init_board(void)
{
pci_dev_t bdf;
@@ -231,3 +308,4 @@
pci_write_config_dword(bdf, PCI_CFG_PIIX4_IDETIM_SEC,
PCI_CFG_PIIX4_IDETIM_IDE);
}
+#endif
diff --git a/board/phytec/phycore_imx8mp/imximage-8mp-sd.cfg b/board/phytec/phycore_imx8mp/imximage-8mp-sd.cfg
new file mode 100644
index 0000000..b2920b4
--- /dev/null
+++ b/board/phytec/phycore_imx8mp/imximage-8mp-sd.cfg
@@ -0,0 +1,10 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright 2021 NXP
+ */
+
+#define __ASSEMBLY__
+
+ROM_VERSION v2
+BOOT_FROM sd
+LOADER mkimage.flash.mkimage 0x920000
diff --git a/board/phytec/phycore_imx8mp/phycore-imx8mp.c b/board/phytec/phycore_imx8mp/phycore-imx8mp.c
index 6764907..a8f0821 100644
--- a/board/phytec/phycore_imx8mp/phycore-imx8mp.c
+++ b/board/phytec/phycore_imx8mp/phycore-imx8mp.c
@@ -10,11 +10,25 @@
#include <asm/io.h>
#include <asm/mach-imx/boot_mode.h>
#include <env.h>
+#include <miiphy.h>
DECLARE_GLOBAL_DATA_PTR;
+static int setup_fec(void)
+{
+ struct iomuxc_gpr_base_regs *gpr =
+ (struct iomuxc_gpr_base_regs *)IOMUXC_GPR_BASE_ADDR;
+
+ /* Use 125M anatop REF_CLK1 for ENET1, not from external */
+ clrsetbits_le32(&gpr->gpr[1], 0x2000, 0);
+
+ return 0;
+}
+
int board_init(void)
{
+ setup_fec();
+
return 0;
}
diff --git a/board/phytec/phycore_imx8mp/spl.c b/board/phytec/phycore_imx8mp/spl.c
index f9fa8d1..19c486e 100644
--- a/board/phytec/phycore_imx8mp/spl.c
+++ b/board/phytec/phycore_imx8mp/spl.c
@@ -62,15 +62,28 @@
/* BUCKxOUT_DVS0/1 control BUCK123 output */
pmic_reg_write(p, PCA9450_BUCK123_DVS, 0x29);
- /* increase VDD_SOC to typical value 0.95V */
+ /* Increase VDD_SOC and VDD_ARM to OD voltage 0.95V */
+ pmic_reg_write(p, PCA9450_BUCK1OUT_DVS0, 0x1C);
pmic_reg_write(p, PCA9450_BUCK2OUT_DVS0, 0x1C);
- /* set WDOG_B_CFG to cold reset */
+ /* Set BUCK1 DVS1 to suspend controlled through PMIC_STBY_REQ */
+ pmic_reg_write(p, PCA9450_BUCK1OUT_DVS1, 0x14);
+ pmic_reg_write(p, PCA9450_BUCK1CTRL, 0x59);
+
+ /* Set WDOG_B_CFG to cold reset */
pmic_reg_write(p, PCA9450_RESET_CTRL, 0xA1);
return 0;
}
+void spl_board_init(void)
+{
+ /* Set GIC clock to 500Mhz for OD VDD_SOC. */
+ clock_enable(CCGR_GIC, 0);
+ clock_set_target_val(GIC_CLK_ROOT, CLK_ROOT_ON | CLK_ROOT_SOURCE_SEL(5));
+ clock_enable(CCGR_GIC, 1);
+}
+
int board_fit_config_name_match(const char *name)
{
return 0;
@@ -80,8 +93,8 @@
#define WDOG_PAD_CTRL (PAD_CTL_DSE6 | PAD_CTL_ODE | PAD_CTL_PUE | PAD_CTL_PE)
static iomux_v3_cfg_t const uart_pads[] = {
- MX8MP_PAD_UART2_RXD__UART2_DCE_RX | MUX_PAD_CTRL(UART_PAD_CTRL),
- MX8MP_PAD_UART2_TXD__UART2_DCE_TX | MUX_PAD_CTRL(UART_PAD_CTRL),
+ MX8MP_PAD_UART1_RXD__UART1_DCE_RX | MUX_PAD_CTRL(UART_PAD_CTRL),
+ MX8MP_PAD_UART1_TXD__UART1_DCE_TX | MUX_PAD_CTRL(UART_PAD_CTRL),
};
static iomux_v3_cfg_t const wdog_pads[] = {
@@ -107,7 +120,7 @@
arch_cpu_init();
- init_uart_clk(1);
+ init_uart_clk(0);
board_early_init_f();
diff --git a/board/solidrun/mx6cuboxi/mx6cuboxi.c b/board/solidrun/mx6cuboxi/mx6cuboxi.c
index 3eadc38..6207bf8 100644
--- a/board/solidrun/mx6cuboxi/mx6cuboxi.c
+++ b/board/solidrun/mx6cuboxi/mx6cuboxi.c
@@ -374,7 +374,7 @@
mmc = find_mmc_device(2);
if (!mmc)
return 0;
- return (mmc_get_op_cond(mmc) < 0) ? 0 : 1;
+ return (mmc_get_op_cond(mmc, true) < 0) ? 0 : 1;
}
int checkboard(void)
diff --git a/board/st/stm32mp1/stm32mp1.c b/board/st/stm32mp1/stm32mp1.c
index 18b8870..2faf5c8 100644
--- a/board/st/stm32mp1/stm32mp1.c
+++ b/board/st/stm32mp1/stm32mp1.c
@@ -841,6 +841,31 @@
}
}
+int mmc_get_boot(void)
+{
+ struct udevice *dev;
+ u32 boot_mode = get_bootmode();
+ unsigned int instance = (boot_mode & TAMP_BOOT_INSTANCE_MASK) - 1;
+ char cmd[20];
+ const u32 sdmmc_addr[] = {
+ STM32_SDMMC1_BASE,
+ STM32_SDMMC2_BASE,
+ STM32_SDMMC3_BASE
+ };
+
+ if (instance > ARRAY_SIZE(sdmmc_addr))
+ return 0;
+
+ /* search associated sdmmc node in devicetree */
+ snprintf(cmd, sizeof(cmd), "mmc@%x", sdmmc_addr[instance]);
+ if (uclass_get_device_by_name(UCLASS_MMC, cmd, &dev)) {
+ log_err("mmc%d = %s not found in device tree!\n", instance, cmd);
+ return 0;
+ }
+
+ return dev_seq(dev);
+};
+
const char *env_ext4_get_dev_part(void)
{
static char *const env_dev_part =
@@ -854,22 +879,16 @@
if (strlen(env_dev_part) > 0)
return env_dev_part;
- u32 bootmode = get_bootmode();
-
- return dev_part[(bootmode & TAMP_BOOT_INSTANCE_MASK) - 1];
+ return dev_part[mmc_get_boot()];
}
int mmc_get_env_dev(void)
{
- u32 bootmode;
-
if (CONFIG_SYS_MMC_ENV_DEV >= 0)
return CONFIG_SYS_MMC_ENV_DEV;
- bootmode = get_bootmode();
-
/* use boot instance to select the correct mmc device identifier */
- return (bootmode & TAMP_BOOT_INSTANCE_MASK) - 1;
+ return mmc_get_boot();
}
#if defined(CONFIG_OF_BOARD_SETUP)
diff --git a/board/tplink/wdr4300/wdr4300.c b/board/tplink/wdr4300/wdr4300.c
index 9134d6b..f2b9210 100644
--- a/board/tplink/wdr4300/wdr4300.c
+++ b/board/tplink/wdr4300/wdr4300.c
@@ -15,7 +15,7 @@
#include <mach/ddr.h>
#include <debug_uart.h>
-#ifdef CONFIG_USB
+#ifdef CONFIG_USB_HOST
static void wdr4300_usb_start(void)
{
void __iomem *gpio_regs = map_physmem(AR71XX_GPIO_BASE,
diff --git a/board/tqc/tqma6/Kconfig b/board/tqc/tqma6/Kconfig
index 0cf6d83..a2a5905 100644
--- a/board/tqc/tqma6/Kconfig
+++ b/board/tqc/tqma6/Kconfig
@@ -65,7 +65,6 @@
bool "TQMa6 on MBa6 Starterkit"
select DM_ETH
select USB
- select DM_USB
select CMD_USB
select USB_STORAGE
select USB_HOST_ETHER
diff --git a/cmd/Kconfig b/cmd/Kconfig
index f196e6c..e40d390 100644
--- a/cmd/Kconfig
+++ b/cmd/Kconfig
@@ -1322,7 +1322,7 @@
config CMD_USB
bool "usb"
- depends on USB
+ depends on USB_HOST
select HAVE_BLOCK_DEVICE
help
USB support.
diff --git a/common/Kconfig.boot b/common/Kconfig.boot
index 89a3161..ae3f2b6 100644
--- a/common/Kconfig.boot
+++ b/common/Kconfig.boot
@@ -35,7 +35,7 @@
could be put in the hole between data payload and fit image
header, such as CSF data on i.MX platform.
-config FIT_ENABLE_SHA256_SUPPORT
+config FIT_SHA256
bool "Support SHA256 checksum of FIT image contents"
default y
select SHA256
@@ -44,7 +44,7 @@
SHA256 checksum is a 256-bit (32-byte) hash value used to check that
the image contents have not been corrupted.
-config FIT_ENABLE_SHA384_SUPPORT
+config FIT_SHA384
bool "Support SHA384 checksum of FIT image contents"
default n
select SHA384
@@ -54,7 +54,7 @@
the image contents have not been corrupted. Use this for the highest
security.
-config FIT_ENABLE_SHA512_SUPPORT
+config FIT_SHA512
bool "Support SHA512 checksum of FIT image contents"
default n
select SHA512
@@ -103,7 +103,7 @@
device memory. Assure this size does not extend past expected storage
space.
-config FIT_ENABLE_RSASSA_PSS_SUPPORT
+config FIT_RSASSA_PSS
bool "Support rsassa-pss signature scheme of FIT image contents"
depends on FIT_SIGNATURE
default n
diff --git a/common/image-android.c b/common/image-android.c
index d07b0e0..1fbbbba 100644
--- a/common/image-android.c
+++ b/common/image-android.c
@@ -164,7 +164,7 @@
else if (get_unaligned_le32(p) == LZ4F_MAGIC)
return IH_COMP_LZ4;
else
- return IH_COMP_NONE;
+ return image_decomp_type(p, sizeof(u32));
}
int android_image_get_ramdisk(const struct andr_img_hdr *hdr,
diff --git a/common/image-fit.c b/common/image-fit.c
index 0c5a059..8e23d51 100644
--- a/common/image-fit.c
+++ b/common/image-fit.c
@@ -17,6 +17,7 @@
#include <u-boot/crc.h>
#else
#include <linux/compiler.h>
+#include <linux/sizes.h>
#include <common.h>
#include <errno.h>
#include <log.h>
@@ -1218,19 +1219,19 @@
CHUNKSZ_CRC32);
*((uint32_t *)value) = cpu_to_uimage(*((uint32_t *)value));
*value_len = 4;
- } else if (IMAGE_ENABLE_SHA1 && strcmp(algo, "sha1") == 0) {
+ } else if (CONFIG_IS_ENABLED(SHA1) && strcmp(algo, "sha1") == 0) {
sha1_csum_wd((unsigned char *)data, data_len,
(unsigned char *)value, CHUNKSZ_SHA1);
*value_len = 20;
- } else if (IMAGE_ENABLE_SHA256 && strcmp(algo, "sha256") == 0) {
+ } else if (CONFIG_IS_ENABLED(SHA256) && strcmp(algo, "sha256") == 0) {
sha256_csum_wd((unsigned char *)data, data_len,
(unsigned char *)value, CHUNKSZ_SHA256);
*value_len = SHA256_SUM_LEN;
- } else if (IMAGE_ENABLE_SHA384 && strcmp(algo, "sha384") == 0) {
+ } else if (CONFIG_IS_ENABLED(SHA384) && strcmp(algo, "sha384") == 0) {
sha384_csum_wd((unsigned char *)data, data_len,
(unsigned char *)value, CHUNKSZ_SHA384);
*value_len = SHA384_SUM_LEN;
- } else if (IMAGE_ENABLE_SHA512 && strcmp(algo, "sha512") == 0) {
+ } else if (CONFIG_IS_ENABLED(SHA512) && strcmp(algo, "sha512") == 0) {
sha512_csum_wd((unsigned char *)data, data_len,
(unsigned char *)value, CHUNKSZ_SHA512);
*value_len = SHA512_SUM_LEN;
@@ -2026,7 +2027,7 @@
* fit_conf_get_node() will try to find default config node
*/
bootstage_mark(bootstage_id + BOOTSTAGE_SUB_NO_UNIT_NAME);
- if (IMAGE_ENABLE_BEST_MATCH && !fit_uname_config) {
+ if (IS_ENABLED(CONFIG_FIT_BEST_MATCH) && !fit_uname_config) {
cfg_noffset = fit_conf_find_compat(fit, gd_fdt_blob());
} else {
cfg_noffset = fit_conf_get_node(fit,
@@ -2267,10 +2268,10 @@
ulong load, len;
#ifdef CONFIG_OF_LIBFDT_OVERLAY
ulong image_start, image_end;
- ulong ovload, ovlen;
+ ulong ovload, ovlen, ovcopylen;
const char *uconfig;
const char *uname;
- void *base, *ov;
+ void *base, *ov, *ovcopy = NULL;
int i, err, noffset, ov_noffset;
#endif
@@ -2360,7 +2361,7 @@
addr, &uname, &uconfig,
arch, IH_TYPE_FLATDT,
BOOTSTAGE_ID_FIT_FDT_START,
- FIT_LOAD_REQUIRED, &ovload, &ovlen);
+ FIT_LOAD_IGNORED, &ovload, &ovlen);
if (ov_noffset < 0) {
printf("load of %s failed\n", uname);
continue;
@@ -2369,6 +2370,21 @@
uname, ovload, ovlen);
ov = map_sysmem(ovload, ovlen);
+ ovcopylen = ALIGN(fdt_totalsize(ov), SZ_4K);
+ ovcopy = malloc(ovcopylen);
+ if (!ovcopy) {
+ printf("failed to duplicate DTO before application\n");
+ fdt_noffset = -ENOMEM;
+ goto out;
+ }
+
+ err = fdt_open_into(ov, ovcopy, ovcopylen);
+ if (err < 0) {
+ printf("failed on fdt_open_into for DTO\n");
+ fdt_noffset = err;
+ goto out;
+ }
+
base = map_sysmem(load, len + ovlen);
err = fdt_open_into(base, base, len + ovlen);
if (err < 0) {
@@ -2376,14 +2392,18 @@
fdt_noffset = err;
goto out;
}
+
/* the verbose method prints out messages on error */
- err = fdt_overlay_apply_verbose(base, ov);
+ err = fdt_overlay_apply_verbose(base, ovcopy);
if (err < 0) {
fdt_noffset = err;
goto out;
}
fdt_pack(base);
len = fdt_totalsize(base);
+
+ free(ovcopy);
+ ovcopy = NULL;
}
#else
printf("config with overlays but CONFIG_OF_LIBFDT_OVERLAY not set\n");
@@ -2400,6 +2420,10 @@
if (fit_uname_configp)
*fit_uname_configp = fit_uname_config;
+#ifdef CONFIG_OF_LIBFDT_OVERLAY
+ if (ovcopy)
+ free(ovcopy);
+#endif
if (fit_uname_config_copy)
free(fit_uname_config_copy);
return fdt_noffset;
diff --git a/common/image-sig.c b/common/image-sig.c
index 0f8e592..fb00355 100644
--- a/common/image-sig.c
+++ b/common/image-sig.c
@@ -3,18 +3,11 @@
* Copyright (c) 2013, Google Inc.
*/
-#ifdef USE_HOSTCC
-#include "mkimage.h"
-#include <fdt_support.h>
-#include <time.h>
-#include <linux/libfdt.h>
-#else
#include <common.h>
#include <log.h>
#include <malloc.h>
#include <asm/global_data.h>
DECLARE_GLOBAL_DATA_PTR;
-#endif /* !USE_HOSTCC*/
#include <image.h>
#include <u-boot/ecdsa.h>
#include <u-boot/rsa.h>
@@ -28,9 +21,6 @@
.checksum_len = SHA1_SUM_LEN,
.der_len = SHA1_DER_LEN,
.der_prefix = sha1_der_prefix,
-#if IMAGE_ENABLE_SIGN
- .calculate_sign = EVP_sha1,
-#endif
.calculate = hash_calculate,
},
{
@@ -38,9 +28,6 @@
.checksum_len = SHA256_SUM_LEN,
.der_len = SHA256_DER_LEN,
.der_prefix = sha256_der_prefix,
-#if IMAGE_ENABLE_SIGN
- .calculate_sign = EVP_sha256,
-#endif
.calculate = hash_calculate,
},
#ifdef CONFIG_SHA384
@@ -49,9 +36,6 @@
.checksum_len = SHA384_SUM_LEN,
.der_len = SHA384_DER_LEN,
.der_prefix = sha384_der_prefix,
-#if IMAGE_ENABLE_SIGN
- .calculate_sign = EVP_sha384,
-#endif
.calculate = hash_calculate,
},
#endif
@@ -61,50 +45,23 @@
.checksum_len = SHA512_SUM_LEN,
.der_len = SHA512_DER_LEN,
.der_prefix = sha512_der_prefix,
-#if IMAGE_ENABLE_SIGN
- .calculate_sign = EVP_sha512,
-#endif
.calculate = hash_calculate,
},
#endif
};
-struct crypto_algo crypto_algos[] = {
- {
- .name = "rsa2048",
- .key_len = RSA2048_BYTES,
- .sign = rsa_sign,
- .add_verify_data = rsa_add_verify_data,
- .verify = rsa_verify,
- },
- {
- .name = "rsa4096",
- .key_len = RSA4096_BYTES,
- .sign = rsa_sign,
- .add_verify_data = rsa_add_verify_data,
- .verify = rsa_verify,
- },
- {
- .name = "ecdsa256",
- .key_len = ECDSA256_BYTES,
- .sign = ecdsa_sign,
- .add_verify_data = ecdsa_add_verify_data,
- .verify = ecdsa_verify,
- },
-};
-
struct padding_algo padding_algos[] = {
{
.name = "pkcs-1.5",
.verify = padding_pkcs_15_verify,
},
-#ifdef CONFIG_FIT_ENABLE_RSASSA_PSS_SUPPORT
+#ifdef CONFIG_FIT_RSASSA_PSS
{
.name = "pss",
.verify = padding_pss_verify,
}
-#endif /* CONFIG_FIT_ENABLE_RSASSA_PSS_SUPPORT */
+#endif /* CONFIG_FIT_RSASSA_PSS */
};
struct checksum_algo *image_get_checksum_algo(const char *full_name)
@@ -112,16 +69,13 @@
int i;
const char *name;
-#if !defined(USE_HOSTCC) && defined(CONFIG_NEEDS_MANUAL_RELOC)
+#if defined(CONFIG_NEEDS_MANUAL_RELOC)
static bool done;
if (!done) {
done = true;
for (i = 0; i < ARRAY_SIZE(checksum_algos); i++) {
checksum_algos[i].name += gd->reloc_off;
-#if IMAGE_ENABLE_SIGN
- checksum_algos[i].calculate_sign += gd->reloc_off;
-#endif
checksum_algos[i].calculate += gd->reloc_off;
}
}
@@ -140,19 +94,18 @@
struct crypto_algo *image_get_crypto_algo(const char *full_name)
{
- int i;
+ struct crypto_algo *crypto, *end;
const char *name;
-#if !defined(USE_HOSTCC) && defined(CONFIG_NEEDS_MANUAL_RELOC)
+#if defined(CONFIG_NEEDS_MANUAL_RELOC)
static bool done;
if (!done) {
- done = true;
- for (i = 0; i < ARRAY_SIZE(crypto_algos); i++) {
- crypto_algos[i].name += gd->reloc_off;
- crypto_algos[i].sign += gd->reloc_off;
- crypto_algos[i].add_verify_data += gd->reloc_off;
- crypto_algos[i].verify += gd->reloc_off;
+ crypto = ll_entry_start(struct crypto_algo, cryptos);
+ end = ll_entry_end(struct crypto_algo, cryptos);
+ for (; crypto < end; crypto++) {
+ crypto->name += gd->reloc_off;
+ crypto->verify += gd->reloc_off;
}
}
#endif
@@ -163,11 +116,14 @@
return NULL;
name += 1;
- for (i = 0; i < ARRAY_SIZE(crypto_algos); i++) {
- if (!strcmp(crypto_algos[i].name, name))
- return &crypto_algos[i];
+ crypto = ll_entry_start(struct crypto_algo, cryptos);
+ end = ll_entry_end(struct crypto_algo, cryptos);
+ for (; crypto < end; crypto++) {
+ if (!strcmp(crypto->name, name))
+ return crypto;
}
+ /* Not found */
return NULL;
}
diff --git a/common/spl/Kconfig b/common/spl/Kconfig
index fa80524..2df3e5d 100644
--- a/common/spl/Kconfig
+++ b/common/spl/Kconfig
@@ -204,7 +204,7 @@
config SPL_LEGACY_IMAGE_CRC_CHECK
bool "Check CRC of Legacy images"
depends on SPL_LEGACY_IMAGE_SUPPORT
- select SPL_CRC32_SUPPORT
+ select SPL_CRC32
help
Enable this to check the CRC of Legacy images. While this increases
reliability, it affects both code size and boot duration.
@@ -407,7 +407,7 @@
the eMMC EXT_CSC_PART_CONFIG selection should be overridden in SPL
by user defined partition number.
-config SPL_CRC32_SUPPORT
+config SPL_CRC32
bool "Support CRC32"
default y if SPL_LEGACY_IMAGE_SUPPORT
help
@@ -417,7 +417,7 @@
for detected accidental image corruption. For secure applications you
should consider SHA1 or SHA256.
-config SPL_MD5_SUPPORT
+config SPL_MD5
bool "Support MD5"
depends on SPL_FIT
help
@@ -429,7 +429,7 @@
applications where images may be changed maliciously, you should
consider SHA256 or SHA384.
-config SPL_SHA1_SUPPORT
+config SPL_FIT_SHA1
bool "Support SHA1"
depends on SPL_FIT
select SHA1
@@ -441,7 +441,7 @@
due to the expanding computing power available to brute-force
attacks. For more security, consider SHA256 or SHA384.
-config SPL_SHA256_SUPPORT
+config SPL_FIT_SHA256
bool "Support SHA256"
depends on SPL_FIT
select SHA256
@@ -450,7 +450,7 @@
checksum is a 256-bit (32-byte) hash value used to check that the
image contents have not been corrupted.
-config SPL_SHA384_SUPPORT
+config SPL_FIT_SHA384
bool "Support SHA384"
depends on SPL_FIT
select SHA384
@@ -461,7 +461,7 @@
image contents have not been corrupted. Use this for the highest
security.
-config SPL_SHA512_SUPPORT
+config SPL_FIT_SHA512
bool "Support SHA512"
depends on SPL_FIT
select SHA512
diff --git a/common/spl/spl_mmc.c b/common/spl/spl_mmc.c
index add2785..2377d09 100644
--- a/common/spl/spl_mmc.c
+++ b/common/spl/spl_mmc.c
@@ -324,6 +324,29 @@
return raw_sect;
}
+int default_spl_mmc_emmc_boot_partition(struct mmc *mmc)
+{
+ int part;
+#ifdef CONFIG_SYS_MMCSD_RAW_MODE_EMMC_BOOT_PARTITION
+ part = CONFIG_SYS_MMCSD_RAW_MODE_EMMC_BOOT_PARTITION;
+#else
+ /*
+ * We need to check what the partition is configured to.
+ * 1 and 2 match up to boot0 / boot1 and 7 is user data
+ * which is the first physical partition (0).
+ */
+ part = (mmc->part_config >> 3) & PART_ACCESS_MASK;
+ if (part == 7)
+ part = 0;
+#endif
+ return part;
+}
+
+int __weak spl_mmc_emmc_boot_partition(struct mmc *mmc)
+{
+ return default_spl_mmc_emmc_boot_partition(mmc);
+}
+
int spl_mmc_load(struct spl_image_info *spl_image,
struct spl_boot_device *bootdev,
const char *filename,
@@ -355,19 +378,7 @@
err = -EINVAL;
switch (boot_mode) {
case MMCSD_MODE_EMMCBOOT:
-#ifdef CONFIG_SYS_MMCSD_RAW_MODE_EMMC_BOOT_PARTITION
- part = CONFIG_SYS_MMCSD_RAW_MODE_EMMC_BOOT_PARTITION;
-#else
- /*
- * We need to check what the partition is configured to.
- * 1 and 2 match up to boot0 / boot1 and 7 is user data
- * which is the first physical partition (0).
- */
- part = (mmc->part_config >> 3) & PART_ACCESS_MASK;
-
- if (part == 7)
- part = 0;
-#endif
+ part = spl_mmc_emmc_boot_partition(mmc);
if (CONFIG_IS_ENABLED(MMC_TINY))
err = mmc_switch_part(mmc, part);
diff --git a/configs/M52277EVB_defconfig b/configs/M52277EVB_defconfig
deleted file mode 100644
index bab8ac4..0000000
--- a/configs/M52277EVB_defconfig
+++ /dev/null
@@ -1,34 +0,0 @@
-CONFIG_M68K=y
-CONFIG_SYS_TEXT_BASE=0x0
-CONFIG_ENV_SIZE=0x1000
-CONFIG_ENV_SECT_SIZE=0x8000
-CONFIG_DEFAULT_DEVICE_TREE="M52277EVB"
-CONFIG_TARGET_M52277EVB=y
-CONFIG_SYS_EXTRA_OPTIONS="SYS_SPANSION_BOOT"
-CONFIG_BOOTDELAY=3
-# CONFIG_DISPLAY_BOARDINFO is not set
-# CONFIG_CMDLINE_EDITING is not set
-# CONFIG_AUTO_COMPLETE is not set
-CONFIG_SYS_PROMPT="-> "
-CONFIG_CMD_IMLS=y
-CONFIG_CMD_I2C=y
-CONFIG_CMD_SF=y
-CONFIG_CMD_SPI=y
-# CONFIG_CMD_SETEXPR is not set
-CONFIG_CMD_CACHE=y
-CONFIG_CMD_DATE=y
-CONFIG_CMD_JFFS2=y
-CONFIG_ENV_OVERWRITE=y
-CONFIG_ENV_IS_IN_FLASH=y
-CONFIG_ENV_ADDR=0x40000
-# CONFIG_NET is not set
-CONFIG_MTD_NOR_FLASH=y
-CONFIG_FLASH_CFI_DRIVER=y
-CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y
-CONFIG_SYS_FLASH_PROTECTION=y
-CONFIG_SYS_FLASH_CFI=y
-CONFIG_SPI_FLASH=y
-CONFIG_SPI_FLASH_STMICRO=y
-CONFIG_SPI=y
-CONFIG_DM_SPI=y
-CONFIG_CF_SPI=y
diff --git a/configs/M52277EVB_stmicro_defconfig b/configs/M52277EVB_stmicro_defconfig
deleted file mode 100644
index 98c64ff..0000000
--- a/configs/M52277EVB_stmicro_defconfig
+++ /dev/null
@@ -1,36 +0,0 @@
-CONFIG_M68K=y
-CONFIG_SYS_TEXT_BASE=0x43E00000
-CONFIG_ENV_SIZE=0x1000
-CONFIG_ENV_OFFSET=0x30000
-CONFIG_ENV_SECT_SIZE=0x10000
-CONFIG_DEFAULT_DEVICE_TREE="M52277EVB_stmicro"
-CONFIG_TARGET_M52277EVB=y
-CONFIG_SYS_EXTRA_OPTIONS="CF_SBF,SYS_STMICRO_BOOT"
-CONFIG_BOOTDELAY=3
-# CONFIG_DISPLAY_BOARDINFO is not set
-# CONFIG_CMDLINE_EDITING is not set
-# CONFIG_AUTO_COMPLETE is not set
-CONFIG_CMD_IMLS=y
-CONFIG_CMD_I2C=y
-CONFIG_CMD_SF=y
-CONFIG_CMD_SPI=y
-# CONFIG_CMD_SETEXPR is not set
-CONFIG_CMD_CACHE=y
-CONFIG_CMD_DATE=y
-CONFIG_CMD_JFFS2=y
-CONFIG_ENV_OVERWRITE=y
-CONFIG_ENV_IS_IN_SPI_FLASH=y
-CONFIG_USE_ENV_SPI_CS=y
-CONFIG_ENV_SPI_CS=2
-CONFIG_SYS_RELOC_GD_ENV_ADDR=y
-# CONFIG_NET is not set
-CONFIG_MTD_NOR_FLASH=y
-CONFIG_FLASH_CFI_DRIVER=y
-CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y
-CONFIG_SYS_FLASH_PROTECTION=y
-CONFIG_SYS_FLASH_CFI=y
-CONFIG_SPI_FLASH=y
-CONFIG_SPI_FLASH_STMICRO=y
-CONFIG_SPI=y
-CONFIG_DM_SPI=y
-CONFIG_CF_SPI=y
diff --git a/configs/M54418TWR_defconfig b/configs/M54418TWR_defconfig
deleted file mode 100644
index 6aa4c2f..0000000
--- a/configs/M54418TWR_defconfig
+++ /dev/null
@@ -1,36 +0,0 @@
-CONFIG_M68K=y
-CONFIG_SYS_TEXT_BASE=0x47E00000
-CONFIG_ENV_SIZE=0x2000
-CONFIG_ENV_OFFSET=0x40000
-CONFIG_ENV_SECT_SIZE=0x10000
-CONFIG_DEFAULT_DEVICE_TREE="M54418TWR"
-CONFIG_TARGET_M54418TWR=y
-CONFIG_SYS_EXTRA_OPTIONS="CF_SBF,SYS_SERIAL_BOOT,SYS_INPUT_CLKSRC=50000000"
-CONFIG_USE_BOOTARGS=y
-CONFIG_BOOTARGS="root=/dev/nfs rw nfsroot=192.168.1.1:/tftpboot/192.168.1.2 ip=192.168.1.2:192.168.1.1:192.168.1.1: 255.255.255.0::eth0:off:rw console=ttyS0,115200"
-# CONFIG_DISPLAY_BOARDINFO is not set
-CONFIG_HUSH_PARSER=y
-# CONFIG_CMDLINE_EDITING is not set
-# CONFIG_AUTO_COMPLETE is not set
-CONFIG_SYS_PROMPT="-> "
-# CONFIG_CMD_LOADB is not set
-# CONFIG_CMD_LOADS is not set
-CONFIG_CMD_SF=y
-CONFIG_CMD_SPI=y
-# CONFIG_CMD_SETEXPR is not set
-CONFIG_CMD_DHCP=y
-CONFIG_CMD_MII=y
-CONFIG_CMD_PING=y
-CONFIG_CMD_CACHE=y
-CONFIG_ENV_IS_IN_SPI_FLASH=y
-CONFIG_USE_ENV_SPI_CS=y
-CONFIG_ENV_SPI_CS=1
-CONFIG_SYS_RELOC_GD_ENV_ADDR=y
-CONFIG_SPI_FLASH=y
-CONFIG_SPI_FLASH_ATMEL=y
-CONFIG_DM_ETH=y
-CONFIG_MCFFEC=y
-CONFIG_MII=y
-CONFIG_SPI=y
-CONFIG_DM_SPI=y
-CONFIG_CF_SPI=y
diff --git a/configs/M54418TWR_nand_mii_defconfig b/configs/M54418TWR_nand_mii_defconfig
deleted file mode 100644
index 7273ee0..0000000
--- a/configs/M54418TWR_nand_mii_defconfig
+++ /dev/null
@@ -1,33 +0,0 @@
-CONFIG_M68K=y
-CONFIG_SYS_TEXT_BASE=0x47E00000
-CONFIG_ENV_SIZE=0x20000
-CONFIG_DEFAULT_DEVICE_TREE="M54418TWR_nand_mii"
-CONFIG_TARGET_M54418TWR=y
-CONFIG_SYS_EXTRA_OPTIONS="SYS_NAND_BOOT,SYS_INPUT_CLKSRC=25000000"
-CONFIG_USE_BOOTARGS=y
-CONFIG_BOOTARGS="root=/dev/mtdblock2 rw rootfstype=jffs2 mtdparts=NAND:1M(u-boot)ro,7M(kernel)ro,-(jffs2) console=ttyS0,115200"
-# CONFIG_DISPLAY_BOARDINFO is not set
-CONFIG_HUSH_PARSER=y
-# CONFIG_CMDLINE_EDITING is not set
-# CONFIG_AUTO_COMPLETE is not set
-CONFIG_SYS_PROMPT="-> "
-# CONFIG_CMD_FLASH is not set
-# CONFIG_CMD_LOADB is not set
-# CONFIG_CMD_LOADS is not set
-CONFIG_CMD_SF=y
-CONFIG_CMD_SPI=y
-# CONFIG_CMD_SETEXPR is not set
-CONFIG_CMD_DHCP=y
-CONFIG_CMD_MII=y
-CONFIG_CMD_PING=y
-CONFIG_CMD_CACHE=y
-CONFIG_SYS_RELOC_GD_ENV_ADDR=y
-CONFIG_MTD=y
-CONFIG_SPI_FLASH=y
-CONFIG_SPI_FLASH_ATMEL=y
-CONFIG_DM_ETH=y
-CONFIG_MCFFEC=y
-CONFIG_MII=y
-CONFIG_SPI=y
-CONFIG_DM_SPI=y
-CONFIG_CF_SPI=y
diff --git a/configs/M54418TWR_nand_rmii_defconfig b/configs/M54418TWR_nand_rmii_defconfig
deleted file mode 100644
index 90df8f4..0000000
--- a/configs/M54418TWR_nand_rmii_defconfig
+++ /dev/null
@@ -1,33 +0,0 @@
-CONFIG_M68K=y
-CONFIG_SYS_TEXT_BASE=0x47E00000
-CONFIG_ENV_SIZE=0x20000
-CONFIG_DEFAULT_DEVICE_TREE="M54418TWR_nand_rmii"
-CONFIG_TARGET_M54418TWR=y
-CONFIG_SYS_EXTRA_OPTIONS="SYS_NAND_BOOT,SYS_INPUT_CLKSRC=50000000"
-CONFIG_USE_BOOTARGS=y
-CONFIG_BOOTARGS="root=/dev/mtdblock2 rw rootfstype=jffs2 mtdparts=NAND:1M(u-boot)ro,7M(kernel)ro,-(jffs2) console=ttyS0,115200"
-# CONFIG_DISPLAY_BOARDINFO is not set
-CONFIG_HUSH_PARSER=y
-# CONFIG_CMDLINE_EDITING is not set
-# CONFIG_AUTO_COMPLETE is not set
-CONFIG_SYS_PROMPT="-> "
-# CONFIG_CMD_FLASH is not set
-# CONFIG_CMD_LOADB is not set
-# CONFIG_CMD_LOADS is not set
-CONFIG_CMD_SF=y
-CONFIG_CMD_SPI=y
-# CONFIG_CMD_SETEXPR is not set
-CONFIG_CMD_DHCP=y
-CONFIG_CMD_MII=y
-CONFIG_CMD_PING=y
-CONFIG_CMD_CACHE=y
-CONFIG_SYS_RELOC_GD_ENV_ADDR=y
-CONFIG_MTD=y
-CONFIG_SPI_FLASH=y
-CONFIG_SPI_FLASH_ATMEL=y
-CONFIG_DM_ETH=y
-CONFIG_MCFFEC=y
-CONFIG_MII=y
-CONFIG_SPI=y
-CONFIG_DM_SPI=y
-CONFIG_CF_SPI=y
diff --git a/configs/M54418TWR_nand_rmii_lowfreq_defconfig b/configs/M54418TWR_nand_rmii_lowfreq_defconfig
deleted file mode 100644
index d7b0f2d..0000000
--- a/configs/M54418TWR_nand_rmii_lowfreq_defconfig
+++ /dev/null
@@ -1,33 +0,0 @@
-CONFIG_M68K=y
-CONFIG_SYS_TEXT_BASE=0x47E00000
-CONFIG_ENV_SIZE=0x20000
-CONFIG_DEFAULT_DEVICE_TREE="M54418TWR_nand_rmii_lowfreq"
-CONFIG_TARGET_M54418TWR=y
-CONFIG_SYS_EXTRA_OPTIONS="SYS_NAND_BOOT,LOW_MCFCLK,SYS_INPUT_CLKSRC=50000000"
-CONFIG_USE_BOOTARGS=y
-CONFIG_BOOTARGS="root=/dev/mtdblock2 rw rootfstype=jffs2 mtdparts=NAND:1M(u-boot)ro,7M(kernel)ro,-(jffs2) console=ttyS0,115200"
-# CONFIG_DISPLAY_BOARDINFO is not set
-CONFIG_HUSH_PARSER=y
-# CONFIG_CMDLINE_EDITING is not set
-# CONFIG_AUTO_COMPLETE is not set
-CONFIG_SYS_PROMPT="-> "
-# CONFIG_CMD_FLASH is not set
-# CONFIG_CMD_LOADB is not set
-# CONFIG_CMD_LOADS is not set
-CONFIG_CMD_SF=y
-CONFIG_CMD_SPI=y
-# CONFIG_CMD_SETEXPR is not set
-CONFIG_CMD_DHCP=y
-CONFIG_CMD_MII=y
-CONFIG_CMD_PING=y
-CONFIG_CMD_CACHE=y
-CONFIG_SYS_RELOC_GD_ENV_ADDR=y
-CONFIG_MTD=y
-CONFIG_SPI_FLASH=y
-CONFIG_SPI_FLASH_ATMEL=y
-CONFIG_DM_ETH=y
-CONFIG_MCFFEC=y
-CONFIG_MII=y
-CONFIG_SPI=y
-CONFIG_DM_SPI=y
-CONFIG_CF_SPI=y
diff --git a/configs/M54418TWR_serial_mii_defconfig b/configs/M54418TWR_serial_mii_defconfig
deleted file mode 100644
index 556bbef..0000000
--- a/configs/M54418TWR_serial_mii_defconfig
+++ /dev/null
@@ -1,36 +0,0 @@
-CONFIG_M68K=y
-CONFIG_SYS_TEXT_BASE=0x47E00000
-CONFIG_ENV_SIZE=0x2000
-CONFIG_ENV_OFFSET=0x40000
-CONFIG_ENV_SECT_SIZE=0x10000
-CONFIG_DEFAULT_DEVICE_TREE="M54418TWR_serial_mii"
-CONFIG_TARGET_M54418TWR=y
-CONFIG_SYS_EXTRA_OPTIONS="CF_SBF,SYS_SERIAL_BOOT,SYS_INPUT_CLKSRC=25000000"
-CONFIG_USE_BOOTARGS=y
-CONFIG_BOOTARGS="root=/dev/nfs rw nfsroot=192.168.1.1:/tftpboot/192.168.1.2 ip=192.168.1.2:192.168.1.1:192.168.1.1: 255.255.255.0::eth0:off:rw console=ttyS0,115200"
-# CONFIG_DISPLAY_BOARDINFO is not set
-CONFIG_HUSH_PARSER=y
-# CONFIG_CMDLINE_EDITING is not set
-# CONFIG_AUTO_COMPLETE is not set
-CONFIG_SYS_PROMPT="-> "
-# CONFIG_CMD_LOADB is not set
-# CONFIG_CMD_LOADS is not set
-CONFIG_CMD_SF=y
-CONFIG_CMD_SPI=y
-# CONFIG_CMD_SETEXPR is not set
-CONFIG_CMD_DHCP=y
-CONFIG_CMD_MII=y
-CONFIG_CMD_PING=y
-CONFIG_CMD_CACHE=y
-CONFIG_ENV_IS_IN_SPI_FLASH=y
-CONFIG_USE_ENV_SPI_CS=y
-CONFIG_ENV_SPI_CS=1
-CONFIG_SYS_RELOC_GD_ENV_ADDR=y
-CONFIG_SPI_FLASH=y
-CONFIG_SPI_FLASH_ATMEL=y
-CONFIG_DM_ETH=y
-CONFIG_MCFFEC=y
-CONFIG_MII=y
-CONFIG_SPI=y
-CONFIG_DM_SPI=y
-CONFIG_CF_SPI=y
diff --git a/configs/M54418TWR_serial_rmii_defconfig b/configs/M54418TWR_serial_rmii_defconfig
deleted file mode 100644
index 19b1aa6..0000000
--- a/configs/M54418TWR_serial_rmii_defconfig
+++ /dev/null
@@ -1,36 +0,0 @@
-CONFIG_M68K=y
-CONFIG_SYS_TEXT_BASE=0x47E00000
-CONFIG_ENV_SIZE=0x2000
-CONFIG_ENV_OFFSET=0x40000
-CONFIG_ENV_SECT_SIZE=0x10000
-CONFIG_DEFAULT_DEVICE_TREE="M54418TWR_serial_rmii"
-CONFIG_TARGET_M54418TWR=y
-CONFIG_SYS_EXTRA_OPTIONS="CF_SBF,SYS_SERIAL_BOOT,SYS_INPUT_CLKSRC=50000000"
-CONFIG_USE_BOOTARGS=y
-CONFIG_BOOTARGS="root=/dev/nfs rw nfsroot=192.168.1.1:/tftpboot/192.168.1.2 ip=192.168.1.2:192.168.1.1:192.168.1.1: 255.255.255.0::eth0:off:rw console=ttyS0,115200"
-# CONFIG_DISPLAY_BOARDINFO is not set
-CONFIG_HUSH_PARSER=y
-# CONFIG_CMDLINE_EDITING is not set
-# CONFIG_AUTO_COMPLETE is not set
-CONFIG_SYS_PROMPT="-> "
-# CONFIG_CMD_LOADB is not set
-# CONFIG_CMD_LOADS is not set
-CONFIG_CMD_SF=y
-CONFIG_CMD_SPI=y
-# CONFIG_CMD_SETEXPR is not set
-CONFIG_CMD_DHCP=y
-CONFIG_CMD_MII=y
-CONFIG_CMD_PING=y
-CONFIG_CMD_CACHE=y
-CONFIG_ENV_IS_IN_SPI_FLASH=y
-CONFIG_USE_ENV_SPI_CS=y
-CONFIG_ENV_SPI_CS=1
-CONFIG_SYS_RELOC_GD_ENV_ADDR=y
-CONFIG_SPI_FLASH=y
-CONFIG_SPI_FLASH_ATMEL=y
-CONFIG_DM_ETH=y
-CONFIG_MCFFEC=y
-CONFIG_MII=y
-CONFIG_SPI=y
-CONFIG_DM_SPI=y
-CONFIG_CF_SPI=y
diff --git a/configs/M54451EVB_defconfig b/configs/M54451EVB_defconfig
deleted file mode 100644
index a3583e5..0000000
--- a/configs/M54451EVB_defconfig
+++ /dev/null
@@ -1,40 +0,0 @@
-CONFIG_M68K=y
-CONFIG_SYS_TEXT_BASE=0x0
-CONFIG_ENV_SIZE=0x2000
-CONFIG_ENV_SECT_SIZE=0x20000
-CONFIG_DEFAULT_DEVICE_TREE="M54451EVB"
-CONFIG_TARGET_M54451EVB=y
-CONFIG_SYS_EXTRA_OPTIONS="SYS_INPUT_CLKSRC=24000000"
-CONFIG_BOOTDELAY=1
-CONFIG_USE_BOOTARGS=y
-CONFIG_BOOTARGS="root=/dev/mtdblock1 rw rootfstype=jffs2 ip=none mtdparts=physmap-flash.0:2M(kernel)ro,-(jffs2)"
-# CONFIG_CMDLINE_EDITING is not set
-# CONFIG_AUTO_COMPLETE is not set
-CONFIG_SYS_PROMPT="-> "
-CONFIG_CMD_IMLS=y
-CONFIG_CMD_I2C=y
-# CONFIG_CMD_LOADB is not set
-# CONFIG_CMD_LOADS is not set
-CONFIG_CMD_SF=y
-CONFIG_CMD_SPI=y
-# CONFIG_CMD_SETEXPR is not set
-CONFIG_CMD_DHCP=y
-CONFIG_CMD_MII=y
-CONFIG_CMD_PING=y
-CONFIG_CMD_CACHE=y
-CONFIG_CMD_DATE=y
-CONFIG_ENV_IS_IN_FLASH=y
-CONFIG_ENV_ADDR=0x40000
-CONFIG_MTD_NOR_FLASH=y
-CONFIG_FLASH_CFI_DRIVER=y
-CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y
-CONFIG_SYS_FLASH_PROTECTION=y
-CONFIG_SYS_FLASH_CFI=y
-CONFIG_SPI_FLASH=y
-CONFIG_SPI_FLASH_STMICRO=y
-CONFIG_DM_ETH=y
-CONFIG_MCFFEC=y
-CONFIG_MII=y
-CONFIG_SPI=y
-CONFIG_DM_SPI=y
-CONFIG_CF_SPI=y
diff --git a/configs/M54451EVB_stmicro_defconfig b/configs/M54451EVB_stmicro_defconfig
deleted file mode 100644
index 5f5e6a5..0000000
--- a/configs/M54451EVB_stmicro_defconfig
+++ /dev/null
@@ -1,42 +0,0 @@
-CONFIG_M68K=y
-CONFIG_SYS_TEXT_BASE=0x47E00000
-CONFIG_ENV_SIZE=0x2000
-CONFIG_ENV_OFFSET=0x20000
-CONFIG_ENV_SECT_SIZE=0x10000
-CONFIG_DEFAULT_DEVICE_TREE="M54451EVB_stmicro"
-CONFIG_TARGET_M54451EVB=y
-CONFIG_SYS_EXTRA_OPTIONS="CF_SBF,SYS_STMICRO_BOOT,SYS_INPUT_CLKSRC=24000000"
-CONFIG_BOOTDELAY=1
-CONFIG_USE_BOOTARGS=y
-CONFIG_BOOTARGS="root=/dev/mtdblock1 rw rootfstype=jffs2 ip=none mtdparts=physmap-flash.0:2M(kernel)ro,-(jffs2)"
-# CONFIG_CMDLINE_EDITING is not set
-# CONFIG_AUTO_COMPLETE is not set
-CONFIG_CMD_IMLS=y
-CONFIG_CMD_I2C=y
-# CONFIG_CMD_LOADB is not set
-# CONFIG_CMD_LOADS is not set
-CONFIG_CMD_SF=y
-CONFIG_CMD_SPI=y
-# CONFIG_CMD_SETEXPR is not set
-CONFIG_CMD_DHCP=y
-CONFIG_CMD_MII=y
-CONFIG_CMD_PING=y
-CONFIG_CMD_CACHE=y
-CONFIG_CMD_DATE=y
-CONFIG_ENV_IS_IN_SPI_FLASH=y
-CONFIG_USE_ENV_SPI_CS=y
-CONFIG_ENV_SPI_CS=1
-CONFIG_SYS_RELOC_GD_ENV_ADDR=y
-CONFIG_MTD_NOR_FLASH=y
-CONFIG_FLASH_CFI_DRIVER=y
-CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y
-CONFIG_SYS_FLASH_PROTECTION=y
-CONFIG_SYS_FLASH_CFI=y
-CONFIG_SPI_FLASH=y
-CONFIG_SPI_FLASH_STMICRO=y
-CONFIG_DM_ETH=y
-CONFIG_MCFFEC=y
-CONFIG_MII=y
-CONFIG_SPI=y
-CONFIG_DM_SPI=y
-CONFIG_CF_SPI=y
diff --git a/configs/M54455EVB_a66_defconfig b/configs/M54455EVB_a66_defconfig
deleted file mode 100644
index 50bdb2c..0000000
--- a/configs/M54455EVB_a66_defconfig
+++ /dev/null
@@ -1,44 +0,0 @@
-CONFIG_M68K=y
-CONFIG_SYS_TEXT_BASE=0x4000000
-CONFIG_ENV_SIZE=0x2000
-CONFIG_ENV_SECT_SIZE=0x10000
-CONFIG_DEFAULT_DEVICE_TREE="M54455EVB_a66"
-CONFIG_TARGET_M54455EVB=y
-CONFIG_SYS_EXTRA_OPTIONS="SYS_ATMEL_BOOT,SYS_INPUT_CLKSRC=66666666"
-CONFIG_BOOTDELAY=1
-CONFIG_USE_BOOTARGS=y
-CONFIG_BOOTARGS="root=/dev/mtdblock1 rw rootfstype=jffs2 ip=none mtdparts=physmap-flash.0:5M(kernel)ro,-(jffs2)"
-# CONFIG_CMDLINE_EDITING is not set
-# CONFIG_AUTO_COMPLETE is not set
-CONFIG_CMD_IMLS=y
-CONFIG_CMD_IDE=y
-CONFIG_CMD_I2C=y
-# CONFIG_CMD_LOADB is not set
-# CONFIG_CMD_LOADS is not set
-CONFIG_CMD_SF=y
-CONFIG_CMD_SPI=y
-# CONFIG_CMD_SETEXPR is not set
-CONFIG_CMD_DHCP=y
-CONFIG_CMD_MII=y
-CONFIG_CMD_PING=y
-CONFIG_CMD_CACHE=y
-CONFIG_CMD_DATE=y
-CONFIG_CMD_EXT2=y
-CONFIG_CMD_FAT=y
-CONFIG_CMD_JFFS2=y
-CONFIG_ISO_PARTITION=y
-CONFIG_ENV_IS_IN_FLASH=y
-CONFIG_ENV_ADDR=0x4040000
-CONFIG_MTD_NOR_FLASH=y
-CONFIG_FLASH_CFI_DRIVER=y
-CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y
-CONFIG_SYS_FLASH_PROTECTION=y
-CONFIG_SYS_FLASH_CFI=y
-CONFIG_SPI_FLASH=y
-CONFIG_SPI_FLASH_STMICRO=y
-CONFIG_DM_ETH=y
-CONFIG_MCFFEC=y
-CONFIG_MII=y
-CONFIG_SPI=y
-CONFIG_DM_SPI=y
-CONFIG_CF_SPI=y
diff --git a/configs/M54455EVB_defconfig b/configs/M54455EVB_defconfig
deleted file mode 100644
index 40d025f..0000000
--- a/configs/M54455EVB_defconfig
+++ /dev/null
@@ -1,45 +0,0 @@
-CONFIG_M68K=y
-CONFIG_SYS_TEXT_BASE=0x4000000
-CONFIG_ENV_SIZE=0x2000
-CONFIG_ENV_SECT_SIZE=0x10000
-CONFIG_DEFAULT_DEVICE_TREE="M54455EVB"
-CONFIG_TARGET_M54455EVB=y
-CONFIG_SYS_EXTRA_OPTIONS="SYS_ATMEL_BOOT,SYS_INPUT_CLKSRC=33333333"
-CONFIG_BOOTDELAY=1
-CONFIG_USE_BOOTARGS=y
-CONFIG_BOOTARGS="root=/dev/mtdblock1 rw rootfstype=jffs2 ip=none mtdparts=physmap-flash.0:5M(kernel)ro,-(jffs2)"
-# CONFIG_CMDLINE_EDITING is not set
-# CONFIG_AUTO_COMPLETE is not set
-CONFIG_SYS_PROMPT="-> "
-CONFIG_CMD_IMLS=y
-CONFIG_CMD_IDE=y
-CONFIG_CMD_I2C=y
-# CONFIG_CMD_LOADB is not set
-# CONFIG_CMD_LOADS is not set
-CONFIG_CMD_SF=y
-CONFIG_CMD_SPI=y
-# CONFIG_CMD_SETEXPR is not set
-CONFIG_CMD_DHCP=y
-CONFIG_CMD_MII=y
-CONFIG_CMD_PING=y
-CONFIG_CMD_CACHE=y
-CONFIG_CMD_DATE=y
-CONFIG_CMD_EXT2=y
-CONFIG_CMD_FAT=y
-CONFIG_CMD_JFFS2=y
-CONFIG_ISO_PARTITION=y
-CONFIG_ENV_IS_IN_FLASH=y
-CONFIG_ENV_ADDR=0x4040000
-CONFIG_MTD_NOR_FLASH=y
-CONFIG_FLASH_CFI_DRIVER=y
-CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y
-CONFIG_SYS_FLASH_PROTECTION=y
-CONFIG_SYS_FLASH_CFI=y
-CONFIG_SPI_FLASH=y
-CONFIG_SPI_FLASH_STMICRO=y
-CONFIG_DM_ETH=y
-CONFIG_MCFFEC=y
-CONFIG_MII=y
-CONFIG_SPI=y
-CONFIG_DM_SPI=y
-CONFIG_CF_SPI=y
diff --git a/configs/M54455EVB_i66_defconfig b/configs/M54455EVB_i66_defconfig
deleted file mode 100644
index 97d5d15..0000000
--- a/configs/M54455EVB_i66_defconfig
+++ /dev/null
@@ -1,44 +0,0 @@
-CONFIG_M68K=y
-CONFIG_SYS_TEXT_BASE=0x0
-CONFIG_ENV_SIZE=0x2000
-CONFIG_ENV_SECT_SIZE=0x20000
-CONFIG_DEFAULT_DEVICE_TREE="M54455EVB_i66"
-CONFIG_TARGET_M54455EVB=y
-CONFIG_SYS_EXTRA_OPTIONS="SYS_INTEL_BOOT,SYS_INPUT_CLKSRC=66666666"
-CONFIG_BOOTDELAY=1
-CONFIG_USE_BOOTARGS=y
-CONFIG_BOOTARGS="root=/dev/mtdblock1 rw rootfstype=jffs2 ip=none mtdparts=physmap-flash.0:5M(kernel)ro,-(jffs2)"
-# CONFIG_CMDLINE_EDITING is not set
-# CONFIG_AUTO_COMPLETE is not set
-CONFIG_CMD_IMLS=y
-CONFIG_CMD_IDE=y
-CONFIG_CMD_I2C=y
-# CONFIG_CMD_LOADB is not set
-# CONFIG_CMD_LOADS is not set
-CONFIG_CMD_SF=y
-CONFIG_CMD_SPI=y
-# CONFIG_CMD_SETEXPR is not set
-CONFIG_CMD_DHCP=y
-CONFIG_CMD_MII=y
-CONFIG_CMD_PING=y
-CONFIG_CMD_CACHE=y
-CONFIG_CMD_DATE=y
-CONFIG_CMD_EXT2=y
-CONFIG_CMD_FAT=y
-CONFIG_CMD_JFFS2=y
-CONFIG_ISO_PARTITION=y
-CONFIG_ENV_IS_IN_FLASH=y
-CONFIG_ENV_ADDR=0x40000
-CONFIG_MTD_NOR_FLASH=y
-CONFIG_FLASH_CFI_DRIVER=y
-CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y
-CONFIG_SYS_FLASH_PROTECTION=y
-CONFIG_SYS_FLASH_CFI=y
-CONFIG_SPI_FLASH=y
-CONFIG_SPI_FLASH_STMICRO=y
-CONFIG_DM_ETH=y
-CONFIG_MCFFEC=y
-CONFIG_MII=y
-CONFIG_SPI=y
-CONFIG_DM_SPI=y
-CONFIG_CF_SPI=y
diff --git a/configs/M54455EVB_intel_defconfig b/configs/M54455EVB_intel_defconfig
deleted file mode 100644
index d82f091..0000000
--- a/configs/M54455EVB_intel_defconfig
+++ /dev/null
@@ -1,44 +0,0 @@
-CONFIG_M68K=y
-CONFIG_SYS_TEXT_BASE=0x0
-CONFIG_ENV_SIZE=0x2000
-CONFIG_ENV_SECT_SIZE=0x20000
-CONFIG_DEFAULT_DEVICE_TREE="M54455EVB_intel"
-CONFIG_TARGET_M54455EVB=y
-CONFIG_SYS_EXTRA_OPTIONS="SYS_INTEL_BOOT,SYS_INPUT_CLKSRC=33333333"
-CONFIG_BOOTDELAY=1
-CONFIG_USE_BOOTARGS=y
-CONFIG_BOOTARGS="root=/dev/mtdblock1 rw rootfstype=jffs2 ip=none mtdparts=physmap-flash.0:5M(kernel)ro,-(jffs2)"
-# CONFIG_CMDLINE_EDITING is not set
-# CONFIG_AUTO_COMPLETE is not set
-CONFIG_CMD_IMLS=y
-CONFIG_CMD_IDE=y
-CONFIG_CMD_I2C=y
-# CONFIG_CMD_LOADB is not set
-# CONFIG_CMD_LOADS is not set
-CONFIG_CMD_SF=y
-CONFIG_CMD_SPI=y
-# CONFIG_CMD_SETEXPR is not set
-CONFIG_CMD_DHCP=y
-CONFIG_CMD_MII=y
-CONFIG_CMD_PING=y
-CONFIG_CMD_CACHE=y
-CONFIG_CMD_DATE=y
-CONFIG_CMD_EXT2=y
-CONFIG_CMD_FAT=y
-CONFIG_CMD_JFFS2=y
-CONFIG_ISO_PARTITION=y
-CONFIG_ENV_IS_IN_FLASH=y
-CONFIG_ENV_ADDR=0x40000
-CONFIG_MTD_NOR_FLASH=y
-CONFIG_FLASH_CFI_DRIVER=y
-CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y
-CONFIG_SYS_FLASH_PROTECTION=y
-CONFIG_SYS_FLASH_CFI=y
-CONFIG_SPI_FLASH=y
-CONFIG_SPI_FLASH_STMICRO=y
-CONFIG_DM_ETH=y
-CONFIG_MCFFEC=y
-CONFIG_MII=y
-CONFIG_SPI=y
-CONFIG_DM_SPI=y
-CONFIG_CF_SPI=y
diff --git a/configs/M54455EVB_stm33_defconfig b/configs/M54455EVB_stm33_defconfig
deleted file mode 100644
index 147d87e..0000000
--- a/configs/M54455EVB_stm33_defconfig
+++ /dev/null
@@ -1,47 +0,0 @@
-CONFIG_M68K=y
-CONFIG_SYS_TEXT_BASE=0x4FE00000
-CONFIG_ENV_SIZE=0x2000
-CONFIG_ENV_OFFSET=0x30000
-CONFIG_ENV_SECT_SIZE=0x10000
-CONFIG_DEFAULT_DEVICE_TREE="M54455EVB_stm33"
-CONFIG_TARGET_M54455EVB=y
-CONFIG_SYS_EXTRA_OPTIONS="SYS_STMICRO_BOOT,CF_SBF,SYS_INPUT_CLKSRC=33333333"
-CONFIG_BOOTDELAY=1
-CONFIG_USE_BOOTARGS=y
-CONFIG_BOOTARGS="root=/dev/mtdblock1 rw rootfstype=jffs2 ip=none mtdparts=physmap-flash.0:5M(kernel)ro,-(jffs2)"
-# CONFIG_CMDLINE_EDITING is not set
-# CONFIG_AUTO_COMPLETE is not set
-CONFIG_CMD_IMLS=y
-CONFIG_CMD_IDE=y
-CONFIG_CMD_I2C=y
-# CONFIG_CMD_LOADB is not set
-# CONFIG_CMD_LOADS is not set
-CONFIG_CMD_SF=y
-CONFIG_CMD_SPI=y
-# CONFIG_CMD_SETEXPR is not set
-CONFIG_CMD_DHCP=y
-CONFIG_CMD_MII=y
-CONFIG_CMD_PING=y
-CONFIG_CMD_CACHE=y
-CONFIG_CMD_DATE=y
-CONFIG_CMD_EXT2=y
-CONFIG_CMD_FAT=y
-CONFIG_CMD_JFFS2=y
-CONFIG_ISO_PARTITION=y
-CONFIG_ENV_IS_IN_SPI_FLASH=y
-CONFIG_USE_ENV_SPI_CS=y
-CONFIG_ENV_SPI_CS=1
-CONFIG_SYS_RELOC_GD_ENV_ADDR=y
-CONFIG_MTD_NOR_FLASH=y
-CONFIG_FLASH_CFI_DRIVER=y
-CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y
-CONFIG_SYS_FLASH_PROTECTION=y
-CONFIG_SYS_FLASH_CFI=y
-CONFIG_SPI_FLASH=y
-CONFIG_SPI_FLASH_STMICRO=y
-CONFIG_DM_ETH=y
-CONFIG_MCFFEC=y
-CONFIG_MII=y
-CONFIG_SPI=y
-CONFIG_DM_SPI=y
-CONFIG_CF_SPI=y
diff --git a/configs/axm_defconfig b/configs/axm_defconfig
index b613c5f..cb64296 100644
--- a/configs/axm_defconfig
+++ b/configs/axm_defconfig
@@ -32,7 +32,7 @@
CONFIG_BOARD_EARLY_INIT_F=y
# CONFIG_SPL_LEGACY_IMAGE_SUPPORT is not set
CONFIG_SPL_SYS_MALLOC_SIMPLE=y
-CONFIG_SPL_CRC32_SUPPORT=y
+CONFIG_SPL_CRC32=y
CONFIG_SPL_NAND_SUPPORT=y
CONFIG_SPL_NAND_DRIVERS=y
CONFIG_SPL_NAND_ECC=y
diff --git a/configs/bcm963158_ram_defconfig b/configs/bcm963158_ram_defconfig
index 4eb3986..f7f1b35 100644
--- a/configs/bcm963158_ram_defconfig
+++ b/configs/bcm963158_ram_defconfig
@@ -11,7 +11,7 @@
CONFIG_ENV_VARS_UBOOT_CONFIG=y
CONFIG_FIT=y
CONFIG_FIT_SIGNATURE=y
-CONFIG_FIT_ENABLE_RSASSA_PSS_SUPPORT=y
+CONFIG_FIT_RSASSA_PSS=y
CONFIG_FIT_VERBOSE=y
CONFIG_LEGACY_IMAGE_FORMAT=y
CONFIG_SUPPORT_RAW_INITRD=y
diff --git a/configs/chromebit_mickey_defconfig b/configs/chromebit_mickey_defconfig
index d652ab8..0e63424 100644
--- a/configs/chromebit_mickey_defconfig
+++ b/configs/chromebit_mickey_defconfig
@@ -25,7 +25,7 @@
CONFIG_SPL_STACK_R=y
CONFIG_SPL_STACK_R_MALLOC_SIMPLE_LEN=0x2000
# CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR is not set
-# CONFIG_SPL_CRC32_SUPPORT is not set
+# CONFIG_SPL_CRC32 is not set
CONFIG_SPL_SPI_LOAD=y
CONFIG_CMD_GPIO=y
CONFIG_CMD_GPT=y
diff --git a/configs/chromebook_jerry_defconfig b/configs/chromebook_jerry_defconfig
index 5bb2735..dc5d06d 100644
--- a/configs/chromebook_jerry_defconfig
+++ b/configs/chromebook_jerry_defconfig
@@ -26,7 +26,7 @@
CONFIG_SPL_STACK_R=y
CONFIG_SPL_STACK_R_MALLOC_SIMPLE_LEN=0x2000
# CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR is not set
-# CONFIG_SPL_CRC32_SUPPORT is not set
+# CONFIG_SPL_CRC32 is not set
CONFIG_SPL_SPI_LOAD=y
CONFIG_CMD_GPIO=y
CONFIG_CMD_GPT=y
diff --git a/configs/chromebook_minnie_defconfig b/configs/chromebook_minnie_defconfig
index 2549c49..0a1d593 100644
--- a/configs/chromebook_minnie_defconfig
+++ b/configs/chromebook_minnie_defconfig
@@ -26,7 +26,7 @@
CONFIG_SPL_STACK_R=y
CONFIG_SPL_STACK_R_MALLOC_SIMPLE_LEN=0x2000
# CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR is not set
-# CONFIG_SPL_CRC32_SUPPORT is not set
+# CONFIG_SPL_CRC32 is not set
CONFIG_SPL_SPI_LOAD=y
CONFIG_CMD_GPIO=y
CONFIG_CMD_GPT=y
diff --git a/configs/chromebook_speedy_defconfig b/configs/chromebook_speedy_defconfig
index 8f7c70a..709af4c 100644
--- a/configs/chromebook_speedy_defconfig
+++ b/configs/chromebook_speedy_defconfig
@@ -26,7 +26,7 @@
CONFIG_SPL_STACK_R=y
CONFIG_SPL_STACK_R_MALLOC_SIMPLE_LEN=0x2000
# CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR is not set
-# CONFIG_SPL_CRC32_SUPPORT is not set
+# CONFIG_SPL_CRC32 is not set
CONFIG_SPL_SPI_LOAD=y
CONFIG_CMD_GPIO=y
CONFIG_CMD_GPT=y
diff --git a/configs/devkit3250_defconfig b/configs/devkit3250_defconfig
index c0354bc..2034cd1 100644
--- a/configs/devkit3250_defconfig
+++ b/configs/devkit3250_defconfig
@@ -57,5 +57,6 @@
CONFIG_SYS_NS16550=y
CONFIG_SPI=y
CONFIG_USB=y
+# CONFIG_SPL_DM_USB is not set
CONFIG_USB_STORAGE=y
CONFIG_OF_LIBFDT=y
diff --git a/configs/draco_defconfig b/configs/draco_defconfig
index 5ee0449..5d9a6aa 100644
--- a/configs/draco_defconfig
+++ b/configs/draco_defconfig
@@ -90,6 +90,7 @@
CONFIG_DM_SPI=y
CONFIG_OMAP3_SPI=y
CONFIG_USB=y
+# CONFIG_SPL_DM_USB is not set
CONFIG_USB_MUSB_HOST=y
CONFIG_USB_MUSB_GADGET=y
CONFIG_USB_MUSB_DSPS=y
diff --git a/configs/etamin_defconfig b/configs/etamin_defconfig
index ee4e6cc..36d96e5 100644
--- a/configs/etamin_defconfig
+++ b/configs/etamin_defconfig
@@ -91,6 +91,7 @@
CONFIG_DM_SPI=y
CONFIG_OMAP3_SPI=y
CONFIG_USB=y
+# CONFIG_SPL_DM_USB is not set
CONFIG_USB_MUSB_HOST=y
CONFIG_USB_MUSB_GADGET=y
CONFIG_USB_MUSB_DSPS=y
diff --git a/configs/evb-px30_defconfig b/configs/evb-px30_defconfig
index 8bcf8ed..d3b52c1 100644
--- a/configs/evb-px30_defconfig
+++ b/configs/evb-px30_defconfig
@@ -29,7 +29,7 @@
# CONFIG_SPL_RAW_IMAGE_SUPPORT is not set
CONFIG_SPL_STACK_R=y
# CONFIG_TPL_BANNER_PRINT is not set
-CONFIG_SPL_CRC32_SUPPORT=y
+CONFIG_SPL_CRC32=y
CONFIG_SPL_ATF=y
# CONFIG_TPL_FRAMEWORK is not set
# CONFIG_CMD_BOOTD is not set
diff --git a/configs/firefly-px30_defconfig b/configs/firefly-px30_defconfig
index d902ab7..1f24f92 100644
--- a/configs/firefly-px30_defconfig
+++ b/configs/firefly-px30_defconfig
@@ -30,7 +30,7 @@
# CONFIG_SPL_RAW_IMAGE_SUPPORT is not set
CONFIG_SPL_STACK_R=y
# CONFIG_TPL_BANNER_PRINT is not set
-CONFIG_SPL_CRC32_SUPPORT=y
+CONFIG_SPL_CRC32=y
CONFIG_SPL_ATF=y
# CONFIG_TPL_FRAMEWORK is not set
# CONFIG_CMD_BOOTD is not set
diff --git a/configs/gardena-smart-gateway-mt7688_defconfig b/configs/gardena-smart-gateway-mt7688_defconfig
index c0795b5..46b9849 100644
--- a/configs/gardena-smart-gateway-mt7688_defconfig
+++ b/configs/gardena-smart-gateway-mt7688_defconfig
@@ -2,13 +2,14 @@
CONFIG_SPL_LIBCOMMON_SUPPORT=y
CONFIG_SPL_LIBGENERIC_SUPPORT=y
CONFIG_NR_DRAM_BANKS=1
+CONFIG_SYS_MEMTEST_START=0x0
CONFIG_ENV_SIZE=0x10000
CONFIG_ENV_OFFSET=0xA0000
CONFIG_ENV_SECT_SIZE=0x10000
CONFIG_DEFAULT_DEVICE_TREE="gardena-smart-gateway-mt7688"
CONFIG_SPL_SERIAL_SUPPORT=y
CONFIG_SYS_BOOTCOUNT_ADDR=0xb000006c
-CONFIG_SPL_SYS_MALLOC_F_LEN=0x40000
+CONFIG_SPL_SYS_MALLOC_F_LEN=0x80000
CONFIG_SPL=y
CONFIG_SYS_BOOTCOUNT_SINGLEWORD=y
CONFIG_ENV_OFFSET_REDUND=0xB0000
@@ -22,6 +23,8 @@
CONFIG_FIT_SIGNATURE=y
CONFIG_LEGACY_IMAGE_FORMAT=y
CONFIG_OF_STDOUT_VIA_ALIAS=y
+CONFIG_AUTOBOOT_KEYED=y
+CONFIG_AUTOBOOT_STOP_STR="x"
CONFIG_USE_BOOTCOMMAND=y
CONFIG_BOOTCOMMAND="cp.b 83000000 84000000 10000 && dhcp uEnv.txt && env import -t ${fileaddr} ${filesize} && run do_u_boot_init; reset"
CONFIG_USE_PREBOOT=y
@@ -34,6 +37,8 @@
# CONFIG_CMD_ELF is not set
# CONFIG_CMD_XIMG is not set
CONFIG_CMD_MEMINFO=y
+CONFIG_CMD_MEMTEST=y
+CONFIG_SYS_ALT_MEMTEST=y
# CONFIG_CMD_FLASH is not set
CONFIG_CMD_GPIO=y
# CONFIG_CMD_LOADS is not set
@@ -45,14 +50,17 @@
CONFIG_CMD_PING=y
CONFIG_CMD_BOOTCOUNT=y
CONFIG_CMD_TIME=y
+CONFIG_CMD_GETTIME=y
CONFIG_CMD_UUID=y
CONFIG_CMD_MTDPARTS=y
+CONFIG_CMD_MTDPARTS_SHOW_NET_SIZES=y
CONFIG_MTDIDS_DEFAULT="spi-nand0=spi0.1,nor0=spi0.0"
CONFIG_MTDPARTS_DEFAULT="spi0.0:640k(uboot),64k(uboot_env0),64k(uboot_env1),64k(factory),-(unused);spi0.1:-(nand)"
CONFIG_CMD_UBI=y
CONFIG_ENV_IS_IN_SPI_FLASH=y
CONFIG_SYS_REDUNDAND_ENVIRONMENT=y
CONFIG_SYS_RELOC_GD_ENV_ADDR=y
+CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y
CONFIG_VERSION_VARIABLE=y
CONFIG_NET_RANDOM_ETHADDR=y
CONFIG_SPL_DM=y
@@ -73,6 +81,7 @@
CONFIG_SPI_FLASH_XMC=y
CONFIG_SPI_FLASH_MTD=y
CONFIG_MTD_UBI_BEB_LIMIT=22
+CONFIG_MTD_UBI_FASTMAP=y
CONFIG_MT7628_ETH=y
CONFIG_PHY=y
CONFIG_SPECIFY_CONSOLE_INDEX=y
diff --git a/configs/gwventana_emmc_defconfig b/configs/gwventana_emmc_defconfig
index 68f4fe8..2fa30d4 100644
--- a/configs/gwventana_emmc_defconfig
+++ b/configs/gwventana_emmc_defconfig
@@ -24,7 +24,6 @@
CONFIG_FIT_VERBOSE=y
CONFIG_SPL_LOAD_FIT=y
# CONFIG_USE_SPL_FIT_GENERATOR is not set
-# CONFIG_LEGACY_IMAGE_FORMAT is not set
CONFIG_SUPPORT_RAW_INITRD=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=arch/arm/mach-imx/spl_sd.cfg"
@@ -108,7 +107,6 @@
CONFIG_USB=y
CONFIG_DM_USB=y
CONFIG_USB_STORAGE=y
-CONFIG_USB_KEYBOARD=y
CONFIG_SYS_USB_EVENT_POLL_VIA_CONTROL_EP=y
CONFIG_USB_GADGET=y
CONFIG_USB_GADGET_MANUFACTURER="Gateworks"
diff --git a/configs/gwventana_gw5904_defconfig b/configs/gwventana_gw5904_defconfig
index b6e4cba..5b75fca 100644
--- a/configs/gwventana_gw5904_defconfig
+++ b/configs/gwventana_gw5904_defconfig
@@ -24,7 +24,6 @@
CONFIG_FIT_VERBOSE=y
CONFIG_SPL_LOAD_FIT=y
# CONFIG_USE_SPL_FIT_GENERATOR is not set
-# CONFIG_LEGACY_IMAGE_FORMAT is not set
CONFIG_SUPPORT_RAW_INITRD=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=arch/arm/mach-imx/spl_sd.cfg"
@@ -112,7 +111,6 @@
CONFIG_USB=y
CONFIG_DM_USB=y
CONFIG_USB_STORAGE=y
-CONFIG_USB_KEYBOARD=y
CONFIG_SYS_USB_EVENT_POLL_VIA_CONTROL_EP=y
CONFIG_USB_GADGET=y
CONFIG_USB_GADGET_MANUFACTURER="Gateworks"
diff --git a/configs/gwventana_nand_defconfig b/configs/gwventana_nand_defconfig
index 5d022b6..16c0374 100644
--- a/configs/gwventana_nand_defconfig
+++ b/configs/gwventana_nand_defconfig
@@ -24,7 +24,6 @@
CONFIG_FIT_VERBOSE=y
CONFIG_SPL_LOAD_FIT=y
# CONFIG_USE_SPL_FIT_GENERATOR is not set
-# CONFIG_LEGACY_IMAGE_FORMAT is not set
CONFIG_SUPPORT_RAW_INITRD=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=arch/arm/mach-imx/spl_sd.cfg"
@@ -114,7 +113,6 @@
CONFIG_USB=y
CONFIG_DM_USB=y
CONFIG_USB_STORAGE=y
-CONFIG_USB_KEYBOARD=y
CONFIG_SYS_USB_EVENT_POLL_VIA_CONTROL_EP=y
CONFIG_USB_GADGET=y
CONFIG_USB_GADGET_MANUFACTURER="Gateworks"
diff --git a/configs/imx6dl_mamoj_defconfig b/configs/imx6dl_mamoj_defconfig
index a163f42..48f0c03 100644
--- a/configs/imx6dl_mamoj_defconfig
+++ b/configs/imx6dl_mamoj_defconfig
@@ -52,6 +52,7 @@
CONFIG_MXC_UART=y
CONFIG_IMX_THERMAL=y
CONFIG_USB=y
+# CONFIG_SPL_DM_USB is not set
CONFIG_USB_GADGET=y
CONFIG_USB_GADGET_MANUFACTURER="FSL"
CONFIG_USB_GADGET_VENDOR_NUM=0x0525
diff --git a/configs/imx8mm_venice_defconfig b/configs/imx8mm_venice_defconfig
index daffcc4..49affcc 100644
--- a/configs/imx8mm_venice_defconfig
+++ b/configs/imx8mm_venice_defconfig
@@ -58,7 +58,7 @@
# CONFIG_SPL_EFI_PARTITION is not set
CONFIG_OF_CONTROL=y
CONFIG_SPL_OF_CONTROL=y
-CONFIG_OF_LIST="imx8mm-venice-gw71xx-0x imx8mm-venice-gw72xx-0x imx8mm-venice-gw73xx-0x"
+CONFIG_OF_LIST="imx8mm-venice-gw71xx-0x imx8mm-venice-gw72xx-0x imx8mm-venice-gw73xx-0x imx8mm-venice-gw7901"
CONFIG_ENV_IS_IN_MMC=y
CONFIG_SYS_REDUNDAND_ENVIRONMENT=y
CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y
@@ -87,9 +87,13 @@
CONFIG_FSL_USDHC=y
CONFIG_PHYLIB=y
CONFIG_PHY_TI_DP83867=y
+CONFIG_PHY_FIXED=y
CONFIG_DM_ETH=y
+CONFIG_DM_MDIO=y
+CONFIG_DM_DSA=y
CONFIG_PHY_GIGE=y
CONFIG_FEC_MXC=y
+CONFIG_KSZ9477=y
CONFIG_MII=y
CONFIG_PINCTRL=y
CONFIG_SPL_PINCTRL=y
diff --git a/configs/imx8mq_evk_defconfig b/configs/imx8mq_evk_defconfig
index 1df4192..f4d5397 100644
--- a/configs/imx8mq_evk_defconfig
+++ b/configs/imx8mq_evk_defconfig
@@ -53,3 +53,12 @@
CONFIG_DM_RESET=y
CONFIG_MXC_UART=y
CONFIG_DM_THERMAL=y
+CONFIG_CMD_USB=y
+CONFIG_USB=y
+CONFIG_USB_STORAGE=y
+CONFIG_DM_USB=y
+CONFIG_USB_XHCI_HCD=y
+CONFIG_USB_XHCI_DWC3=y
+CONFIG_USB_DWC3=y
+CONFIG_PHY=y
+CONFIG_PHY_IMX8MQ_USB=y
diff --git a/configs/imxrt1020-evk_defconfig b/configs/imxrt1020-evk_defconfig
index 0dc3743..79b25be 100644
--- a/configs/imxrt1020-evk_defconfig
+++ b/configs/imxrt1020-evk_defconfig
@@ -24,7 +24,7 @@
CONFIG_SPL_SYS_MALLOC_SIMPLE=y
CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR=y
CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x100
-# CONFIG_SPL_CRC32_SUPPORT is not set
+# CONFIG_SPL_CRC32 is not set
# CONFIG_BOOTM_NETBSD is not set
# CONFIG_BOOTM_PLAN9 is not set
# CONFIG_BOOTM_RTEMS is not set
diff --git a/configs/imxrt1050-evk_defconfig b/configs/imxrt1050-evk_defconfig
index 0e426ce..ca72f8c 100644
--- a/configs/imxrt1050-evk_defconfig
+++ b/configs/imxrt1050-evk_defconfig
@@ -27,7 +27,7 @@
CONFIG_SPL_SYS_MALLOC_SIMPLE=y
CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR=y
CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x100
-# CONFIG_SPL_CRC32_SUPPORT is not set
+# CONFIG_SPL_CRC32 is not set
# CONFIG_BOOTM_NETBSD is not set
# CONFIG_BOOTM_PLAN9 is not set
# CONFIG_BOOTM_RTEMS is not set
diff --git a/configs/k2e_evm_defconfig b/configs/k2e_evm_defconfig
index 2798d56..44cba29 100644
--- a/configs/k2e_evm_defconfig
+++ b/configs/k2e_evm_defconfig
@@ -76,6 +76,7 @@
CONFIG_DAVINCI_SPI=y
CONFIG_USB=y
CONFIG_DM_USB=y
+# CONFIG_SPL_DM_USB is not set
CONFIG_USB_XHCI_HCD=y
CONFIG_USB_XHCI_DWC3=y
CONFIG_USB_DWC3=y
diff --git a/configs/k2hk_evm_defconfig b/configs/k2hk_evm_defconfig
index 6745da1..2392aec 100644
--- a/configs/k2hk_evm_defconfig
+++ b/configs/k2hk_evm_defconfig
@@ -76,6 +76,7 @@
CONFIG_DAVINCI_SPI=y
CONFIG_USB=y
CONFIG_DM_USB=y
+# CONFIG_SPL_DM_USB is not set
CONFIG_USB_XHCI_HCD=y
CONFIG_USB_XHCI_DWC3=y
CONFIG_USB_DWC3=y
diff --git a/configs/k2l_evm_defconfig b/configs/k2l_evm_defconfig
index f23bdbf..021129b 100644
--- a/configs/k2l_evm_defconfig
+++ b/configs/k2l_evm_defconfig
@@ -76,6 +76,7 @@
CONFIG_DAVINCI_SPI=y
CONFIG_USB=y
CONFIG_DM_USB=y
+# CONFIG_SPL_DM_USB is not set
CONFIG_USB_XHCI_HCD=y
CONFIG_USB_XHCI_DWC3=y
CONFIG_USB_DWC3=y
diff --git a/configs/mt8516_pumpkin_defconfig b/configs/mt8516_pumpkin_defconfig
index 945643a..cafad0e 100644
--- a/configs/mt8516_pumpkin_defconfig
+++ b/configs/mt8516_pumpkin_defconfig
@@ -13,7 +13,7 @@
# CONFIG_PSCI_RESET is not set
CONFIG_DEBUG_UART=y
CONFIG_FIT=y
-# CONFIG_FIT_ENABLE_SHA256_SUPPORT is not set
+# CONFIG_FIT_SHA256 is not set
# CONFIG_ARCH_FIXUP_FDT_MEMORY is not set
CONFIG_DEFAULT_FDT_FILE="mt8516-pumpkin"
# CONFIG_DISPLAY_BOARDINFO is not set
diff --git a/configs/mvebu_db-88f3720_defconfig b/configs/mvebu_db-88f3720_defconfig
index c9935da..ff4668e 100644
--- a/configs/mvebu_db-88f3720_defconfig
+++ b/configs/mvebu_db-88f3720_defconfig
@@ -11,7 +11,6 @@
CONFIG_DM_GPIO=y
CONFIG_DEFAULT_DEVICE_TREE="armada-3720-db"
CONFIG_DEBUG_UART_BASE=0xd0012000
-CONFIG_DEBUG_UART_CLOCK=25804800
CONFIG_DEBUG_UART=y
CONFIG_AHCI=y
CONFIG_DISTRO_DEFAULTS=y
diff --git a/configs/mvebu_espressobin-88f3720_defconfig b/configs/mvebu_espressobin-88f3720_defconfig
index 157a4b7..dc199cf 100644
--- a/configs/mvebu_espressobin-88f3720_defconfig
+++ b/configs/mvebu_espressobin-88f3720_defconfig
@@ -11,7 +11,6 @@
CONFIG_DM_GPIO=y
CONFIG_DEFAULT_DEVICE_TREE="armada-3720-espressobin"
CONFIG_DEBUG_UART_BASE=0xd0012000
-CONFIG_DEBUG_UART_CLOCK=25804800
CONFIG_DEBUG_UART=y
CONFIG_AHCI=y
CONFIG_DISTRO_DEFAULTS=y
diff --git a/configs/odroid-go2_defconfig b/configs/odroid-go2_defconfig
index f5b03a3..7cb32f1 100644
--- a/configs/odroid-go2_defconfig
+++ b/configs/odroid-go2_defconfig
@@ -33,7 +33,7 @@
# CONFIG_SPL_RAW_IMAGE_SUPPORT is not set
CONFIG_SPL_STACK_R=y
# CONFIG_TPL_BANNER_PRINT is not set
-CONFIG_SPL_CRC32_SUPPORT=y
+CONFIG_SPL_CRC32=y
CONFIG_SPL_I2C_SUPPORT=y
CONFIG_SPL_POWER_SUPPORT=y
CONFIG_SPL_ATF=y
diff --git a/configs/phycore-imx8mp_defconfig b/configs/phycore-imx8mp_defconfig
index 7f21e88..32d538c 100644
--- a/configs/phycore-imx8mp_defconfig
+++ b/configs/phycore-imx8mp_defconfig
@@ -20,11 +20,12 @@
CONFIG_FIT=y
CONFIG_FIT_EXTERNAL_OFFSET=0x3000
CONFIG_SPL_LOAD_FIT=y
-CONFIG_SPL_FIT_GENERATOR="arch/arm/mach-imx/mkimage_fit_atf.sh"
+# CONFIG_USE_SPL_FIT_GENERATOR is not set
CONFIG_OF_SYSTEM_SETUP=y
-CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=arch/arm/mach-imx/imx8m/imximage-8mp-lpddr4.cfg"
+CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/phytec/phycore_imx8mp/imximage-8mp-sd.cfg"
CONFIG_DEFAULT_FDT_FILE="oftree"
CONFIG_BOARD_LATE_INIT=y
+CONFIG_SPL_BOARD_INIT=y
CONFIG_SPL_BOOTROM_SUPPORT=y
CONFIG_SPL_SYS_MALLOC_SIMPLE=y
CONFIG_SPL_SEPARATE_BSS=y
@@ -58,6 +59,7 @@
CONFIG_SYS_RELOC_GD_ENV_ADDR=y
CONFIG_SYS_MMC_ENV_DEV=2
CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y
+CONFIG_NET_RANDOM_ETHADDR=y
CONFIG_SPL_DM=y
CONFIG_CLK_COMPOSITE_CCF=y
CONFIG_CLK_IMX8MP=y
@@ -79,7 +81,13 @@
CONFIG_MMC_HS400_ES_SUPPORT=y
CONFIG_MMC_HS400_SUPPORT=y
CONFIG_FSL_ESDHC_IMX=y
+CONFIG_PHYLIB=y
+CONFIG_PHY_TI_DP83867=y
CONFIG_DM_ETH=y
+CONFIG_DM_ETH_PHY=y
+CONFIG_FEC_MXC=y
+CONFIG_RGMII=y
+CONFIG_MII=y
CONFIG_PINCTRL=y
CONFIG_SPL_PINCTRL=y
CONFIG_PINCTRL_IMX8M=y
diff --git a/configs/px30-core-ctouch2-px30_defconfig b/configs/px30-core-ctouch2-px30_defconfig
index 3e50d87..0b30ef6 100644
--- a/configs/px30-core-ctouch2-px30_defconfig
+++ b/configs/px30-core-ctouch2-px30_defconfig
@@ -30,7 +30,7 @@
# CONFIG_SPL_RAW_IMAGE_SUPPORT is not set
CONFIG_SPL_STACK_R=y
# CONFIG_TPL_BANNER_PRINT is not set
-CONFIG_SPL_CRC32_SUPPORT=y
+CONFIG_SPL_CRC32=y
CONFIG_SPL_ATF=y
# CONFIG_TPL_FRAMEWORK is not set
# CONFIG_CMD_BOOTD is not set
diff --git a/configs/px30-core-edimm2.2-px30_defconfig b/configs/px30-core-edimm2.2-px30_defconfig
index 01e0b5a..46a4fb9 100644
--- a/configs/px30-core-edimm2.2-px30_defconfig
+++ b/configs/px30-core-edimm2.2-px30_defconfig
@@ -30,7 +30,7 @@
# CONFIG_SPL_RAW_IMAGE_SUPPORT is not set
CONFIG_SPL_STACK_R=y
# CONFIG_TPL_BANNER_PRINT is not set
-CONFIG_SPL_CRC32_SUPPORT=y
+CONFIG_SPL_CRC32=y
CONFIG_SPL_ATF=y
# CONFIG_TPL_FRAMEWORK is not set
# CONFIG_CMD_BOOTD is not set
diff --git a/configs/pxm2_defconfig b/configs/pxm2_defconfig
index 7de4cdb..44e9dc7 100644
--- a/configs/pxm2_defconfig
+++ b/configs/pxm2_defconfig
@@ -90,6 +90,7 @@
CONFIG_DM_SPI=y
CONFIG_OMAP3_SPI=y
CONFIG_USB=y
+# CONFIG_SPL_DM_USB is not set
CONFIG_USB_MUSB_HOST=y
CONFIG_USB_MUSB_GADGET=y
CONFIG_USB_MUSB_DSPS=y
diff --git a/configs/rastaban_defconfig b/configs/rastaban_defconfig
index 5448386..5401892 100644
--- a/configs/rastaban_defconfig
+++ b/configs/rastaban_defconfig
@@ -90,6 +90,7 @@
CONFIG_DM_SPI=y
CONFIG_OMAP3_SPI=y
CONFIG_USB=y
+# CONFIG_SPL_DM_USB is not set
CONFIG_USB_MUSB_HOST=y
CONFIG_USB_MUSB_GADGET=y
CONFIG_USB_MUSB_DSPS=y
diff --git a/configs/rut_defconfig b/configs/rut_defconfig
index fa5250e..91da734 100644
--- a/configs/rut_defconfig
+++ b/configs/rut_defconfig
@@ -90,6 +90,7 @@
CONFIG_DM_SPI=y
CONFIG_OMAP3_SPI=y
CONFIG_USB=y
+# CONFIG_SPL_DM_USB is not set
CONFIG_USB_MUSB_HOST=y
CONFIG_USB_MUSB_GADGET=y
CONFIG_USB_MUSB_DSPS=y
diff --git a/configs/sandbox_defconfig b/configs/sandbox_defconfig
index fc687e3..1655bb1 100644
--- a/configs/sandbox_defconfig
+++ b/configs/sandbox_defconfig
@@ -10,7 +10,7 @@
CONFIG_DISTRO_DEFAULTS=y
CONFIG_FIT=y
CONFIG_FIT_SIGNATURE=y
-CONFIG_FIT_ENABLE_RSASSA_PSS_SUPPORT=y
+CONFIG_FIT_RSASSA_PSS=y
CONFIG_FIT_CIPHER=y
CONFIG_FIT_VERBOSE=y
CONFIG_BOOTSTAGE=y
diff --git a/configs/smegw01_defconfig b/configs/smegw01_defconfig
index 9bfaa01..75fd5bc 100644
--- a/configs/smegw01_defconfig
+++ b/configs/smegw01_defconfig
@@ -21,6 +21,7 @@
# CONFIG_CMD_IMI is not set
# CONFIG_CMD_XIMG is not set
CONFIG_CMD_MEMTEST=y
+CONFIG_CMD_UNZIP=y
CONFIG_CMD_DFU=y
CONFIG_CMD_GPIO=y
CONFIG_CMD_MMC=y
diff --git a/configs/sniper_defconfig b/configs/sniper_defconfig
index b64f7bb..c52e7cb 100644
--- a/configs/sniper_defconfig
+++ b/configs/sniper_defconfig
@@ -31,7 +31,6 @@
CONFIG_TWL4030_INPUT=y
CONFIG_MMC_OMAP_HS=y
CONFIG_CONS_INDEX=3
-CONFIG_USB=y
CONFIG_USB_MUSB_GADGET=y
CONFIG_USB_MUSB_OMAP2PLUS=y
CONFIG_TWL4030_USB=y
diff --git a/configs/socfpga_agilex_atf_defconfig b/configs/socfpga_agilex_atf_defconfig
index 6921575..1a57a6e 100644
--- a/configs/socfpga_agilex_atf_defconfig
+++ b/configs/socfpga_agilex_atf_defconfig
@@ -23,7 +23,7 @@
CONFIG_BOOTARGS="earlycon"
CONFIG_USE_BOOTCOMMAND=y
CONFIG_BOOTCOMMAND="run fatscript; run mmcfitload; run linux_qspi_enable; run mmcfitboot"
-CONFIG_SPL_CRC32_SUPPORT=y
+CONFIG_SPL_CRC32=y
CONFIG_SPL_CACHE=y
CONFIG_SPL_SPI_LOAD=y
CONFIG_SPL_ATF=y
diff --git a/configs/socfpga_agilex_vab_defconfig b/configs/socfpga_agilex_vab_defconfig
index 97eb7b4..3135b61 100644
--- a/configs/socfpga_agilex_vab_defconfig
+++ b/configs/socfpga_agilex_vab_defconfig
@@ -24,7 +24,7 @@
CONFIG_BOOTARGS="earlycon"
CONFIG_USE_BOOTCOMMAND=y
CONFIG_BOOTCOMMAND="run fatscript; run mmcfitload; run mmcfitboot"
-CONFIG_SPL_CRC32_SUPPORT=y
+CONFIG_SPL_CRC32=y
CONFIG_SPL_CACHE=y
CONFIG_SPL_SPI_LOAD=y
CONFIG_SPL_ATF=y
diff --git a/configs/socfpga_stratix10_atf_defconfig b/configs/socfpga_stratix10_atf_defconfig
index cd1b6f9..4eed547 100644
--- a/configs/socfpga_stratix10_atf_defconfig
+++ b/configs/socfpga_stratix10_atf_defconfig
@@ -23,7 +23,7 @@
CONFIG_BOOTARGS="earlycon"
CONFIG_USE_BOOTCOMMAND=y
CONFIG_BOOTCOMMAND="run fatscript; run mmcfitload; run linux_qspi_enable; run mmcfitboot"
-CONFIG_SPL_CRC32_SUPPORT=y
+CONFIG_SPL_CRC32=y
CONFIG_SPL_SPI_LOAD=y
CONFIG_SPL_ATF=y
CONFIG_SPL_ATF_NO_PLATFORM_PARAM=y
diff --git a/configs/socfpga_stratix10_defconfig b/configs/socfpga_stratix10_defconfig
index bbbae14..f83a90c 100644
--- a/configs/socfpga_stratix10_defconfig
+++ b/configs/socfpga_stratix10_defconfig
@@ -39,6 +39,7 @@
CONFIG_CMD_EXT4=y
CONFIG_CMD_FAT=y
CONFIG_CMD_FS_GENERIC=y
+CONFIG_CMD_WDT=y
CONFIG_ENV_IS_IN_MMC=y
CONFIG_SYS_RELOC_GD_ENV_ADDR=y
CONFIG_NET_RANDOM_ETHADDR=y
diff --git a/configs/socrates_defconfig b/configs/socrates_defconfig
index cdf8630..1631b4f 100644
--- a/configs/socrates_defconfig
+++ b/configs/socrates_defconfig
@@ -73,5 +73,6 @@
CONFIG_USB=y
CONFIG_DM_USB=y
# CONFIG_USB_EHCI_HCD is not set
+CONFIG_USB_OHCI_HCD=y
CONFIG_USB_OHCI_PCI=y
CONFIG_USB_STORAGE=y
diff --git a/configs/stm32mp15_basic_defconfig b/configs/stm32mp15_basic_defconfig
index e199f2b..ab02c35 100644
--- a/configs/stm32mp15_basic_defconfig
+++ b/configs/stm32mp15_basic_defconfig
@@ -12,6 +12,7 @@
CONFIG_SPL_MMC_SUPPORT=y
CONFIG_SPL=y
CONFIG_TARGET_ST_STM32MP15x=y
+CONFIG_CMD_STM32KEY=y
CONFIG_CMD_STM32PROG=y
CONFIG_ENV_OFFSET_REDUND=0x2C0000
CONFIG_TYPEC_STUSB160X=y
@@ -54,6 +55,7 @@
CONFIG_CMD_CACHE=y
CONFIG_CMD_EFIDEBUG=y
CONFIG_CMD_TIME=y
+CONFIG_CMD_RNG=y
CONFIG_CMD_TIMER=y
CONFIG_CMD_PMIC=y
CONFIG_CMD_REGULATOR=y
@@ -168,7 +170,6 @@
CONFIG_WDT=y
CONFIG_WDT_STM32MP=y
CONFIG_ERRNO_STR=y
-# CONFIG_HEXDUMP is not set
CONFIG_FDT_FIXUP_PARTITIONS=y
# CONFIG_LMB_USE_MAX_REGIONS is not set
CONFIG_LMB_MEMORY_REGIONS=2
diff --git a/configs/stm32mp15_trusted_defconfig b/configs/stm32mp15_trusted_defconfig
index 5bc5e79..a58ea91 100644
--- a/configs/stm32mp15_trusted_defconfig
+++ b/configs/stm32mp15_trusted_defconfig
@@ -8,6 +8,7 @@
CONFIG_ENV_SECT_SIZE=0x40000
CONFIG_DEFAULT_DEVICE_TREE="stm32mp157c-ev1"
CONFIG_TARGET_ST_STM32MP15x=y
+CONFIG_CMD_STM32KEY=y
CONFIG_CMD_STM32PROG=y
CONFIG_ENV_OFFSET_REDUND=0x2C0000
CONFIG_TYPEC_STUSB160X=y
@@ -37,6 +38,7 @@
CONFIG_CMD_CACHE=y
CONFIG_CMD_EFIDEBUG=y
CONFIG_CMD_TIME=y
+CONFIG_CMD_RNG=y
CONFIG_CMD_TIMER=y
CONFIG_CMD_PMIC=y
CONFIG_CMD_REGULATOR=y
@@ -150,7 +152,6 @@
CONFIG_WDT=y
CONFIG_WDT_STM32MP=y
CONFIG_ERRNO_STR=y
-# CONFIG_HEXDUMP is not set
CONFIG_FDT_FIXUP_PARTITIONS=y
# CONFIG_LMB_USE_MAX_REGIONS is not set
CONFIG_LMB_MEMORY_REGIONS=2
diff --git a/configs/taurus_defconfig b/configs/taurus_defconfig
index ce09450..4c47d7b 100644
--- a/configs/taurus_defconfig
+++ b/configs/taurus_defconfig
@@ -36,7 +36,7 @@
CONFIG_BOARD_EARLY_INIT_F=y
# CONFIG_SPL_LEGACY_IMAGE_SUPPORT is not set
CONFIG_SPL_SYS_MALLOC_SIMPLE=y
-CONFIG_SPL_CRC32_SUPPORT=y
+CONFIG_SPL_CRC32=y
CONFIG_SPL_NAND_SUPPORT=y
CONFIG_SPL_NAND_DRIVERS=y
CONFIG_SPL_NAND_ECC=y
diff --git a/configs/thuban_defconfig b/configs/thuban_defconfig
index 67e1e68..c9a99ca 100644
--- a/configs/thuban_defconfig
+++ b/configs/thuban_defconfig
@@ -90,6 +90,7 @@
CONFIG_DM_SPI=y
CONFIG_OMAP3_SPI=y
CONFIG_USB=y
+# CONFIG_SPL_DM_USB is not set
CONFIG_USB_MUSB_HOST=y
CONFIG_USB_MUSB_GADGET=y
CONFIG_USB_MUSB_DSPS=y
diff --git a/configs/turris_mox_defconfig b/configs/turris_mox_defconfig
index 2c6f493..fd5b6f3 100644
--- a/configs/turris_mox_defconfig
+++ b/configs/turris_mox_defconfig
@@ -11,7 +11,6 @@
CONFIG_DM_GPIO=y
CONFIG_DEFAULT_DEVICE_TREE="armada-3720-turris-mox"
CONFIG_DEBUG_UART_BASE=0xd0012000
-CONFIG_DEBUG_UART_CLOCK=25804800
CONFIG_DEBUG_UART=y
CONFIG_OF_BOARD_FIXUP=y
CONFIG_DISTRO_DEFAULTS=y
@@ -31,6 +30,7 @@
CONFIG_CMD_GPIO=y
CONFIG_CMD_I2C=y
CONFIG_CMD_MMC=y
+CONFIG_CMD_MTD=y
CONFIG_CMD_PCI=y
CONFIG_CMD_SPI=y
CONFIG_CMD_USB=y
@@ -60,12 +60,14 @@
CONFIG_MMC_SDHCI_SDMA=y
CONFIG_MMC_SDHCI_XENON=y
CONFIG_MTD=y
+CONFIG_DM_MTD=y
CONFIG_SF_DEFAULT_MODE=0
CONFIG_SF_DEFAULT_SPEED=20000000
CONFIG_SPI_FLASH_MACRONIX=y
CONFIG_SPI_FLASH_SPANSION=y
CONFIG_SPI_FLASH_STMICRO=y
CONFIG_SPI_FLASH_WINBOND=y
+CONFIG_SPI_FLASH_MTD=y
CONFIG_PHY_MARVELL=y
CONFIG_PHY_GIGE=y
CONFIG_MVNETA=y
diff --git a/configs/turris_omnia_defconfig b/configs/turris_omnia_defconfig
index 57ab384..f860cf5 100644
--- a/configs/turris_omnia_defconfig
+++ b/configs/turris_omnia_defconfig
@@ -41,6 +41,7 @@
CONFIG_CMD_GPIO=y
CONFIG_CMD_I2C=y
CONFIG_CMD_MMC=y
+CONFIG_CMD_MTD=y
CONFIG_CMD_PCI=y
CONFIG_CMD_SATA=y
CONFIG_CMD_SPI=y
@@ -56,7 +57,7 @@
# CONFIG_SPL_PARTITION_UUIDS is not set
CONFIG_ENV_OVERWRITE=y
CONFIG_USE_ENV_SPI_MAX_HZ=y
-CONFIG_ENV_SPI_MAX_HZ=50000000
+CONFIG_ENV_SPI_MAX_HZ=40000000
CONFIG_SYS_RELOC_GD_ENV_ADDR=y
CONFIG_SPL_OF_TRANSLATE=y
CONFIG_AHCI_PCI=y
@@ -65,8 +66,13 @@
CONFIG_DM_PCA953X=y
CONFIG_MMC_SDHCI=y
CONFIG_MMC_SDHCI_MV=y
+CONFIG_MTD=y
+CONFIG_DM_MTD=y
CONFIG_SPI_FLASH_MACRONIX=y
CONFIG_SPI_FLASH_SPANSION=y
+CONFIG_SPI_FLASH_MTD=y
+CONFIG_SF_DEFAULT_MODE=0x0
+CONFIG_SF_DEFAULT_SPEED=40000000
CONFIG_PHY_MARVELL=y
CONFIG_PHY_GIGE=y
CONFIG_MVNETA=y
diff --git a/configs/uDPU_defconfig b/configs/uDPU_defconfig
index cdf6b22..649248d 100644
--- a/configs/uDPU_defconfig
+++ b/configs/uDPU_defconfig
@@ -10,7 +10,6 @@
CONFIG_DM_GPIO=y
CONFIG_DEFAULT_DEVICE_TREE="armada-3720-uDPU"
CONFIG_DEBUG_UART_BASE=0xd0012000
-CONFIG_DEBUG_UART_CLOCK=25804800
CONFIG_DEBUG_UART=y
CONFIG_AHCI=y
CONFIG_DISTRO_DEFAULTS=y
diff --git a/configs/vinco_defconfig b/configs/vinco_defconfig
index be7aaa9..434d90c 100644
--- a/configs/vinco_defconfig
+++ b/configs/vinco_defconfig
@@ -33,13 +33,14 @@
CONFIG_SYS_RELOC_GD_ENV_ADDR=y
CONFIG_AT91_GPIO=y
CONFIG_SUPPORT_EMMC_BOOT=y
-CONFIG_SPI_FLASH=y
+CONFIG_DM_SPI_FLASH=y
CONFIG_SF_DEFAULT_MODE=0
CONFIG_SF_DEFAULT_SPEED=50000000
CONFIG_PHY_SMSC=y
CONFIG_ETH_DESIGNWARE=y
CONFIG_ATMEL_USART=y
CONFIG_USB=y
+CONFIG_DM_USB=y
CONFIG_USB_EHCI_HCD=y
CONFIG_USB_GADGET=y
CONFIG_USB_GADGET_MANUFACTURER="L+G VInCo"
diff --git a/doc/README.m54418twr b/doc/README.m54418twr
deleted file mode 100644
index 0ca74aa..0000000
--- a/doc/README.m54418twr
+++ /dev/null
@@ -1,245 +0,0 @@
-Freescale MCF54418TWR ColdFire Development Board
-================================================
-
-TsiChung Liew(Tsi-Chung.Liew@freescale.com)
-Created Mar 22, 2012
-===========================================
-
-
-Changed files:
-==============
-
-- board/freescale/m54418twr/m54418twr.c Dram setup
-- board/freescale/m54418twr/Makefile Makefile
-- board/freescale/m54418twr/config.mk config make
-- board/freescale/m54418twr/u-boot.lds Linker description
-- board/freescale/m54418twr/sbf_dram_init.S
- DDR/SDRAM initialization
-
-- arch/m68k/cpu/mcf5445x/cpu.c cpu specific code
-- arch/m68k/cpu/mcf5445x/cpu_init.c Flexbus ChipSelect, Mux pins setup, icache and RTC extra regs
-- arch/m68k/cpu/mcf5445x/interrupts.c cpu specific interrupt support
-- arch/m68k/cpu/mcf5445x/speed.c system, pci, flexbus, and cpu clock
-- arch/m68k/cpu/mcf5445x/Makefile Makefile
-- arch/m68k/cpu/mcf5445x/config.mk config make
-- arch/m68k/cpu/mcf5445x/start.S start up assembly code
-
-- doc/README.m54418twr This readme file
-
-- drivers/net/mcffec.c ColdFire common FEC driver
-- drivers/net/mcfmii.c ColdFire common MII driver
-- drivers/serial/mcfuart.c ColdFire common UART driver
-
-- arch/m68k/include/asm/bitops.h Bit operation function export
-- arch/m68k/include/asm/byteorder.h Byte order functions
-- arch/m68k/include/asm/fec.h FEC structure and definition
-- arch/m68k/include/asm/global_data.h Global data structure
-- arch/m68k/include/asm/immap.h ColdFire specific header file and driver macros
-- arch/m68k/include/asm/immap_5441x.h mcf5441x specific header file
-- arch/m68k/include/asm/io.h io functions
-- arch/m68k/include/asm/m5441x.h mcf5441x specific header file
-- arch/m68k/include/asm/posix_types.h Posix
-- arch/m68k/include/asm/processor.h header file
-- arch/m68k/include/asm/ptrace.h Exception structure
-- arch/m68k/include/asm/rtc.h Realtime clock header file
-- arch/m68k/include/asm/string.h String function export
-- arch/m68k/include/asm/timer.h Timer structure and definition
-- arch/m68k/include/asm/types.h Data types definition
-- arch/m68k/include/asm/uart.h Uart structure and definition
-- arch/m68k/include/asm/u-boot.h u-boot structure
-
-- include/configs/M54418TWR.h Board specific configuration file
-
-- arch/m68k/lib/board.c board init function
-- arch/m68k/lib/cache.c
-- arch/m68k/lib/interrupts.c Coldfire common interrupt functions
-- arch/m68k/lib/time.c Timer functions (Dma timer and PIT)
-- arch/m68k/lib/traps.c Exception init code
-
-1 MCF5441x specific Options/Settings
-====================================
-1.1 pre-loader is no longer suppoer in thie coldfire family
-
-1.2 Configuration settings for M54418TWR Development Board
-CONFIG_MCF5441x -- define for all MCF5441x CPUs
-CONFIG_M54418 -- define for all Freescale MCF54418 CPUs
-
-CONFIG_MCFUART -- define to use common CF Uart driver
-CONFIG_SYS_UART_PORT -- define UART port number, start with 0, 1 and 2
-CONFIG_BAUDRATE -- define UART baudrate
-
-CONFIG_MCFFEC -- define to use common CF FEC driver
-CONFIG_MII -- enable to use MII driver
-CONFIG_SYS_DISCOVER_PHY -- enable PHY discovery
-CONFIG_SYS_RX_ETH_BUFFER -- Set FEC Receive buffer
-CONFIG_SYS_FAULT_ECHO_LINK_DOWN --
-CONFIG_SYS_FEC0_PINMUX -- Set FEC0 Pin configuration
-CONFIG_SYS_FEC1_PINMUX -- Set FEC1 Pin configuration
-CONFIG_SYS_FEC0_MIIBASE -- Set FEC0 MII base register
-CONFIG_SYS_FEC1_MIIBASE -- Set FEC0 MII base register
-MCFFEC_TOUT_LOOP -- set FEC timeout loop
-CONFIG_HAS_ETH1 -- define to enable second FEC in u-boot
-
-CONFIG_MCFTMR -- define to use DMA timer
-
-CONFIG_SYS_IMMR -- define for MBAR offset
-
-CONFIG_EXTRA_CLOCK -- Enable extra clock such as vco, flexbus, pci, etc
-
-CONFIG_SYS_MBAR -- define MBAR offset
-
-CONFIG_MONITOR_IS_IN_RAM -- Not support
-
-CONFIG_SYS_INIT_RAM_ADDR -- defines the base address of the MCF54455 internal SRAM
-
-CONFIG_SYS_CSn_BASE -- defines the Chip Select Base register
-CONFIG_SYS_CSn_MASK -- defines the Chip Select Mask register
-CONFIG_SYS_CSn_CTRL -- defines the Chip Select Control register
-
-CONFIG_SYS_SDRAM_BASE -- defines the DRAM Base
-
-2. MEMORY MAP UNDER U-BOOT AND LINUX KERNEL
-===========================================
-2.1. System memory map:
- MRAM: 0x00000000-0x0003FFFF (256KB)
- DDR: 0x40000000-0x47FFFFFF (128MB)
- SRAM: 0x80000000-0x8000FFFF (64KB)
- IP: 0xE0000000-0xFFFFFFFF (512MB)
-
-3. COMPILATION
-==============
-3.1 To create U-Boot the gcc-4.x compiler set (ColdFire ELF version)
-from codesourcery.com was used. Download it from:
-http://www.codesourcery.com/gnu_toolchains/coldfire/download.html
-
-3.2 Compilation
- export CROSS_COMPILE=cross-compile-prefix
- cd u-boot
- make distclean
- make M54418TWR_config, or - default to spi serial flash boot, 50Mhz input clock
- make M54418TWR_nand_mii_config, or - default to nand flash boot, mii mode, 25Mhz input clock
- make M54418TWR_nand_rmii_config, or - default to nand flash boot, rmii mode, 50Mhz input clock
- make M54418TWR_nand_rmii_lowfreq_config, or - default to nand flash boot, rmii mode, 50Mhz input clock
- make M54418TWR_serial_mii_config, or - default to spi serial flash boot, 25Mhz input clock
- make M54418TWR_serial_rmii_config, or - default to spi serial flash boot, 50Mhz input clock
- make
-
-4. SCREEN DUMP
-==============
-4.1 M54418TWR Development board
- Boot from NAND flash (NOTE: May not show exactly the same)
-
-U-Boot 2012.10-00209-g12ae1d8-dirty (Oct 18 2012 - 15:54:54)
-
-CPU: Freescale MCF54418 (Mask:a3 Version:1)
- CPU CLK 250 MHz BUS CLK 125 MHz FLB CLK 125 MHz
- INP CLK 50 MHz VCO CLK 500 MHz
-Board: Freescale MCF54418 Tower System
-SPI: ready
-DRAM: 128 MiB
-NAND: 256 MiB
-In: serial
-Out: serial
-Err: serial
-Net: FEC0, FEC1
--> pri
-baudrate=115200
-bootargs=root=/dev/mtdblock2 rw rootfstype=jffs2 mtdparts=NAND:1M(u-boot)ro,7M(k
-ernel)ro,-(jffs2) console=ttyS0,115200
-bootdelay=2
-eth1addr=00:e0:0c:bc:e5:61
-ethact=FEC0
-ethaddr=00:e0:0c:bc:e5:60
-fileaddr=40010000
-filesize=27354
-gatewayip=192.168.1.1
-hostname=M54418TWR
-inpclk=50000000
-ipaddr=192.168.1.2
-load=tftp ${loadaddr} ${u-boot};
-loadaddr=0x40010000
-mem=129024k
-netdev=eth0
-netmask=255.255.255.0
-prog=nand device 0;nand erase 0 40000;nb_update ${loadaddr} ${filesize};save
-serverip=192.168.1.1
-stderr=serial
-stdin=serial
-stdout=serial
-u-boot=u-boot.bin
-upd=run load; run prog
-
-Environment size: 653/131068 bytes
--> bdinfo
-memstart = 0x40000000
-memsize = 0x08000000
-flashstart = 0x00000000
-flashsize = 0x00000000
-flashoffset = 0x00000000
-sramstart = 0x80000000
-sramsize = 0x00010000
-mbar = 0xFC000000
-cpufreq = 250 MHz
-busfreq = 125 MHz
-flbfreq = 125 MHz
-inpfreq = 50 MHz
-vcofreq = 500 MHz
-ethaddr = 00:e0:0c:bc:e5:60
-eth1addr = 00:e0:0c:bc:e5:61
-ip_addr = 192.168.1.2
-baudrate = 115200 bps
--> help
-? - alias for 'help'
-base - print or set address offset
-bdinfo - print Board Info structure
-boot - boot default, i.e., run 'bootcmd'
-bootd - boot default, i.e., run 'bootcmd'
-bootelf - Boot from an ELF image in memory
-bootm - boot application image from memory
-bootp - boot image via network using BOOTP/TFTP protocol
-bootvx - Boot vxWorks from an ELF image
-cmp - memory compare
-coninfo - print console devices and information
-cp - memory copy
-crc32 - checksum calculation
-dcache - enable or disable data cache
-dhcp - boot image via network using DHCP/TFTP protocol
-echo - echo args to console
-editenv - edit environment variable
-env - environment handling commands
-exit - exit script
-false - do nothing, unsuccessfully
-go - start application at address 'addr'
-help - print command description/usage
-icache - enable or disable instruction cache
-iminfo - print header information for application image
-imxtract- extract a part of a multi-image
-itest - return true/false on integer compare
-loop - infinite loop on address range
-md - memory display
-mdio - MDIO utility commands
-mii - MII utility commands
-mm - memory modify (auto-incrementing address)
-mtest - simple RAM read/write test
-mw - memory write (fill)
-nand - NAND sub-system
-nb_update- Nand boot update program
-nboot - boot from NAND device
-nfs - boot image via network using NFS protocol
-nm - memory modify (constant address)
-ping - send ICMP ECHO_REQUEST to network host
-printenv- print environment variables
-reginfo - print register information
-reset - Perform RESET of the CPU
-run - run commands in an environment variable
-saveenv - save environment variables to persistent storage
-setenv - set environment variables
-sf - SPI flash sub-system
-showvar - print local hushshell variables
-sleep - delay execution for some time
-source - run script from memory
-sspi - SPI utility command
-test - minimal test like /bin/sh
-tftpboot- boot image via network using TFTP protocol
-true - do nothing, successfully
-version - print monitor, compiler and linker version
diff --git a/doc/board/coreboot/coreboot.rst b/doc/board/coreboot/coreboot.rst
index 9c44c02..3792f9e 100644
--- a/doc/board/coreboot/coreboot.rst
+++ b/doc/board/coreboot/coreboot.rst
@@ -50,3 +50,24 @@
can be useful for running UEFI applications, for example.
This has only been lightly tested.
+
+
+Memory map
+----------
+
+ ========== ==================================================================
+ Address Region at that address
+ ========== ==================================================================
+ ffffffff Top of ROM (and last byte of 32-bit address space)
+ 7a9fd000 Typical top of memory available to U-Boot
+ (use cbsysinfo to see where memory range 'table' starts)
+ 10000000 Memory reserved by coreboot for mapping PCI devices
+ (typical size 2151000, includes framebuffer)
+ 1920000 CONFIG_SYS_CAR_ADDR, fake Cache-as-RAM memory, used during startup
+ 1110000 CONFIG_SYS_TEXT_BASE (start address of U-Boot code, before reloc)
+ 110000 CONFIG_BLOBLIST_ADDR (before being relocated)
+ 100000 CONFIG_PRE_CON_BUF_ADDR
+ f0000 ACPI tables set up by U-Boot
+ (typically redirects to 7ab10030 or similar)
+ 500 Location of coreboot sysinfo table, used during startup
+ ========== ==================================================================
diff --git a/doc/board/emulation/qemu_capsule_update.rst b/doc/board/emulation/qemu_capsule_update.rst
deleted file mode 100644
index 0a2286d..0000000
--- a/doc/board/emulation/qemu_capsule_update.rst
+++ /dev/null
@@ -1,203 +0,0 @@
-.. SPDX-License-Identifier: GPL-2.0+
-.. Copyright (C) 2020, Linaro Limited
-
-Enabling UEFI Capsule Update feature
-------------------------------------
-
-Support has been added for the UEFI capsule update feature which
-enables updating the U-Boot image using the UEFI firmware management
-protocol (fmp). The capsules are not passed to the firmware through
-the UpdateCapsule runtime service. Instead, capsule-on-disk
-functionality is used for fetching the capsule from the EFI System
-Partition (ESP) by placing the capsule file under the
-\EFI\UpdateCapsule directory.
-
-Currently, support has been added on the QEMU ARM64 virt platform for
-updating the U-Boot binary as a raw image when the platform is booted
-in non-secure mode, i.e. with CONFIG_TFABOOT disabled. For this
-configuration, the QEMU platform needs to be booted with
-'secure=off'. The U-Boot binary placed on the first bank of the NOR
-flash at offset 0x0. The U-Boot environment is placed on the second
-NOR flash bank at offset 0x4000000.
-
-The capsule update feature is enabled with the following configuration
-settings::
-
- CONFIG_MTD=y
- CONFIG_FLASH_CFI_MTD=y
- CONFIG_CMD_MTDPARTS=y
- CONFIG_CMD_DFU=y
- CONFIG_DFU_MTD=y
- CONFIG_PCI_INIT_R=y
- CONFIG_EFI_CAPSULE_ON_DISK=y
- CONFIG_EFI_CAPSULE_FIRMWARE_MANAGEMENT=y
- CONFIG_EFI_CAPSULE_FIRMWARE=y
- CONFIG_EFI_CAPSULE_FIRMWARE_RAW=y
- CONFIG_EFI_CAPSULE_FMP_HEADER=y
-
-In addition, the following config needs to be disabled(QEMU ARM specific)::
-
- CONFIG_TFABOOT
-
-The capsule file can be generated by using the tools/mkeficapsule::
-
- $ mkeficapsule --raw <u-boot.bin> --index 1 <capsule_file_name>
-
-As per the UEFI specification, the capsule file needs to be placed on
-the EFI System Partition, under the \EFI\UpdateCapsule directory. The
-EFI System Partition can be a virtio-blk-device.
-
-Before initiating the firmware update, the efi variables BootNext,
-BootXXXX and OsIndications need to be set. The BootXXXX variable needs
-to be pointing to the EFI System Partition which contains the capsule
-file. The BootNext, BootXXXX and OsIndications variables can be set
-using the following commands::
-
- => efidebug boot add -b 0 Boot0000 virtio 0:1 <capsule_file_name>
- => efidebug boot next 0
- => setenv -e -nv -bs -rt -v OsIndications =0x04
- => saveenv
-
-Finally, the capsule update can be initiated with the following
-command::
-
- => efidebug capsule disk-update
-
-The updated U-Boot image will be booted on subsequent boot.
-
-Enabling Capsule Authentication
-^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
-
-The UEFI specification defines a way of authenticating the capsule to
-be updated by verifying the capsule signature. The capsule signature
-is computed and prepended to the capsule payload at the time of
-capsule generation. This signature is then verified by using the
-public key stored as part of the X509 certificate. This certificate is
-in the form of an efi signature list (esl) file, which is embedded as
-part of the platform's device tree blob using the mkeficapsule
-utility.
-
-On the QEMU virt platforms, the device-tree is generated on the fly
-based on the devices configured. This device tree is then passed on to
-the various software components booting on the platform, including
-U-Boot. Therefore, on the QEMU virt platform, the signatute is
-embedded on an overlay. This overlay is then applied at runtime to the
-base platform device-tree. Steps needed for embedding the esl file in
-the overlay are highlighted below.
-
-The capsule authentication feature can be enabled through the
-following config, in addition to the configs listed above for capsule
-update::
-
- CONFIG_EFI_CAPSULE_AUTHENTICATE=y
-
-The public and private keys used for the signing process are generated
-and used by the steps highlighted below::
-
- 1. Install utility commands on your host
- * OPENSSL
- * efitools
-
- 2. Create signing keys and certificate files on your host
-
- $ openssl req -x509 -sha256 -newkey rsa:2048 -subj /CN=CRT/ \
- -keyout CRT.key -out CRT.crt -nodes -days 365
- $ cert-to-efi-sig-list CRT.crt CRT.esl
-
- $ openssl x509 -in CRT.crt -out CRT.cer -outform DER
- $ openssl x509 -inform DER -in CRT.cer -outform PEM -out CRT.pub.pem
-
- $ openssl pkcs12 -export -out CRT.pfx -inkey CRT.key -in CRT.crt
- $ openssl pkcs12 -in CRT.pfx -nodes -out CRT.pem
-
-The capsule file can be generated by using the GenerateCapsule.py
-script in EDKII::
-
- $ ./BaseTools/BinWrappers/PosixLike/GenerateCapsule -e -o \
- <capsule_file_name> --monotonic-count <val> --fw-version \
- <val> --lsv <val> --guid \
- e2bb9c06-70e9-4b14-97a3-5a7913176e3f --verbose \
- --update-image-index <val> --signer-private-cert \
- /path/to/CRT.pem --trusted-public-cert \
- /path/to/CRT.pub.pem --other-public-cert /path/to/CRT.pub.pem \
- <u-boot.bin>
-
-Place the capsule generated in the above step on the EFI System
-Partition under the EFI/UpdateCapsule directory
-
-For embedding the public key certificate, the following steps need to
-be followed::
-
- 1. Generate a skeleton overlay dts file, with a single fragment
- node and an empty __overlay__ node
-
- A typical skeleton overlay file will look like this
-
- /dts-v1/;
- /plugin/;
-
- / {
- fragment@0 {
- target-path = "/";
- __overlay__ {
- };
- };
- };
-
-
- 2. Convert the dts to a corresponding dtb with the following
- command
- ./scripts/dtc/dtc -@ -I dts -O dtb -o <ov_dtb_file_name> \
- <dts_file>
-
- 3. Run the dtb file generated above through the mkeficapsule tool
- in U-Boot
- ./tools/mkeficapsule -O <pub_key.esl> -D <ov_dtb>
-
-Running the above command results in the creation of a 'signature'
-node in the dtb, under which the public key is stored as a
-'capsule-key' property. The '-O' option is to be used since the
-public key certificate(esl) file is being embedded in an overlay.
-
-The dtb file embedded with the certificate is now to be placed on an
-EFI System Partition. This would then be loaded and "merged" with the
-base platform flattened device-tree(dtb) at runtime.
-
-Build U-Boot with the following steps(QEMU ARM64)::
-
- $ make qemu_arm64_defconfig
- $ make menuconfig
- Disable CONFIG_TFABOOT
- Enable CONFIG_EFI_CAPSULE_AUTHENTICATE
- Enable all configs needed for capsule update(listed above)
- $ make all
-
-Boot the platform and perform the following steps on the U-Boot
-command line::
-
- 1. Enable capsule authentication by setting the following env
- variable
-
- => setenv capsule_authentication_enabled 1
- => saveenv
-
- 2. Load the overlay dtb to memory and merge it with the base fdt
-
- => fatload virtio 0:1 <$fdtovaddr> EFI/<ov_dtb_file>
- => fdt addr $fdtcontroladdr
- => fdt resize <size_of_ov_dtb_file>
- => fdt apply <$fdtovaddr>
-
- 3. Set the following environment and UEFI boot variables
-
- => setenv -e -nv -bs -rt -v OsIndications =0x04
- => efidebug boot add -b 0 Boot0000 virtio 0:1 <capsule_file_name>
- => efidebug boot next 0
- => saveenv
-
- 4. Finally, the capsule update can be initiated with the following
- command
-
- => efidebug capsule disk-update
-
-On subsequent reboot, the platform should boot the updated U-Boot binary.
diff --git a/doc/chromium/run_vboot.rst b/doc/chromium/run_vboot.rst
index 41b4f63..a9e4408 100644
--- a/doc/chromium/run_vboot.rst
+++ b/doc/chromium/run_vboot.rst
@@ -6,11 +6,15 @@
Running U-Boot with Chromium OS verified boot
=============================================
+Note: Once you use the source below you can obtain extra documentation with
+'make htmldocs'. See the 'Internal Documentation' link, under
+'Chromium OS-specific doc'.
+
To obtain::
git clone https://github.com/sjg20/u-boot.git
cd u-boot
- git checkout cros-master
+ git checkout cros-2021.04
cd ..
git clone https://chromium.googlesource.com/chromiumos/platform/vboot_reference
@@ -169,7 +173,8 @@
U-Boot without Chromium OS verified boot
----------------------------------------
-The following script can be used to boot a Chrome OS image on coral::
+The following script can be used to boot a Chrome OS image on coral. It is
+defined as the boot command in mainline::
# Read the image header and obtain the address of the kernel
# The offset 4f0 is defined by verified boot and may change for other
@@ -195,10 +200,4 @@
zboot go
-TO DO
------
-
-Get the full ACPI tables working with Coral
-
-
7 October 2018
diff --git a/doc/develop/uefi/uefi.rst b/doc/develop/uefi/uefi.rst
index 4f2b8b0..64fe934 100644
--- a/doc/develop/uefi/uefi.rst
+++ b/doc/develop/uefi/uefi.rst
@@ -277,6 +277,131 @@
[1] https://optee.readthedocs.io/en/latest/building/efi_vars/stmm.html
+Enabling UEFI Capsule Update feature
+~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
+
+Support has been added for the UEFI capsule update feature which
+enables updating the U-Boot image using the UEFI firmware management
+protocol (FMP). The capsules are not passed to the firmware through
+the UpdateCapsule runtime service. Instead, capsule-on-disk
+functionality is used for fetching the capsule from the EFI System
+Partition (ESP) by placing the capsule file under the
+\EFI\UpdateCapsule directory.
+
+The directory \EFI\UpdateCapsule is checked for capsules only within the
+EFI system partition on the device specified in the active boot option
+determined by reference to BootNext variable or BootOrder variable processing.
+The active Boot Variable is the variable with highest priority BootNext or
+within BootOrder that refers to a device found to be present. Boot variables
+in BootOrder but referring to devices not present are ignored when determining
+active boot variable.
+Before starting a capsule update make sure your capsules are installed in the
+correct ESP partition or set BootNext.
+
+Performing the update
+*********************
+
+Since U-boot doesn't currently support SetVariable at runtime there's a Kconfig
+option (CONFIG_EFI_IGNORE_OSINDICATIONS) to disable the OsIndications variable
+check. If that option is enabled just copy your capsule to \EFI\UpdateCapsule.
+
+If that option is disabled, you'll need to set the OsIndications variable with::
+
+ => setenv -e -nv -bs -rt -v OsIndications =0x04
+
+Finally, the capsule update can be initiated either by rebooting the board,
+which is the preferred method, or by issuing the following command::
+
+ => efidebug capsule disk-update
+
+**The efidebug command is should only be used during debugging/development.**
+
+Enabling Capsule Authentication
+*******************************
+
+The UEFI specification defines a way of authenticating the capsule to
+be updated by verifying the capsule signature. The capsule signature
+is computed and prepended to the capsule payload at the time of
+capsule generation. This signature is then verified by using the
+public key stored as part of the X509 certificate. This certificate is
+in the form of an efi signature list (esl) file, which is embedded as
+part of U-Boot.
+
+The capsule authentication feature can be enabled through the
+following config, in addition to the configs listed above for capsule
+update::
+
+ CONFIG_EFI_CAPSULE_AUTHENTICATE=y
+ CONFIG_EFI_CAPSULE_KEY_PATH=<path to .esl cert>
+
+The public and private keys used for the signing process are generated
+and used by the steps highlighted below::
+
+ 1. Install utility commands on your host
+ * OPENSSL
+ * efitools
+
+ 2. Create signing keys and certificate files on your host
+
+ $ openssl req -x509 -sha256 -newkey rsa:2048 -subj /CN=CRT/ \
+ -keyout CRT.key -out CRT.crt -nodes -days 365
+ $ cert-to-efi-sig-list CRT.crt CRT.esl
+
+ $ openssl x509 -in CRT.crt -out CRT.cer -outform DER
+ $ openssl x509 -inform DER -in CRT.cer -outform PEM -out CRT.pub.pem
+
+ $ openssl pkcs12 -export -out CRT.pfx -inkey CRT.key -in CRT.crt
+ $ openssl pkcs12 -in CRT.pfx -nodes -out CRT.pem
+
+The capsule file can be generated by using the GenerateCapsule.py
+script in EDKII::
+
+ $ ./BaseTools/BinWrappers/PosixLike/GenerateCapsule -e -o \
+ <capsule_file_name> --monotonic-count <val> --fw-version \
+ <val> --lsv <val> --guid \
+ e2bb9c06-70e9-4b14-97a3-5a7913176e3f --verbose \
+ --update-image-index <val> --signer-private-cert \
+ /path/to/CRT.pem --trusted-public-cert \
+ /path/to/CRT.pub.pem --other-public-cert /path/to/CRT.pub.pem \
+ <u-boot.bin>
+
+Place the capsule generated in the above step on the EFI System
+Partition under the EFI/UpdateCapsule directory
+
+Testing on QEMU
+***************
+
+Currently, support has been added on the QEMU ARM64 virt platform for
+updating the U-Boot binary as a raw image when the platform is booted
+in non-secure mode, i.e. with CONFIG_TFABOOT disabled. For this
+configuration, the QEMU platform needs to be booted with
+'secure=off'. The U-Boot binary placed on the first bank of the NOR
+flash at offset 0x0. The U-Boot environment is placed on the second
+NOR flash bank at offset 0x4000000.
+
+The capsule update feature is enabled with the following configuration
+settings::
+
+ CONFIG_MTD=y
+ CONFIG_FLASH_CFI_MTD=y
+ CONFIG_CMD_MTDPARTS=y
+ CONFIG_CMD_DFU=y
+ CONFIG_DFU_MTD=y
+ CONFIG_PCI_INIT_R=y
+ CONFIG_EFI_CAPSULE_ON_DISK=y
+ CONFIG_EFI_CAPSULE_FIRMWARE_MANAGEMENT=y
+ CONFIG_EFI_CAPSULE_FIRMWARE=y
+ CONFIG_EFI_CAPSULE_FIRMWARE_RAW=y
+ CONFIG_EFI_CAPSULE_FMP_HEADER=y
+
+In addition, the following config needs to be disabled(QEMU ARM specific)::
+
+ CONFIG_TFABOOT
+
+The capsule file can be generated by using the tools/mkeficapsule::
+
+ $ mkeficapsule --raw <u-boot.bin> --index 1 <capsule_file_name>
+
Executing the boot manager
~~~~~~~~~~~~~~~~~~~~~~~~~~
diff --git a/doc/device-tree-bindings/pci/x86-pci.txt b/doc/device-tree-bindings/pci/x86-pci.txt
index 95e370b..cf4e5ed 100644
--- a/doc/device-tree-bindings/pci/x86-pci.txt
+++ b/doc/device-tree-bindings/pci/x86-pci.txt
@@ -20,6 +20,10 @@
output to be lost. This should not generally be used in production code,
although it is often harmless.
+- u-boot,pci-pre-reloc : List of vendor/device IDs to bind before relocation, even
+ if they are not bridges. This is useful if the device is needed (e.g. a
+ UART). The format is 0xvvvvdddd where d is the device ID and v is the
+ vendor ID.
Example:
@@ -32,7 +36,8 @@
0x42000000 0x0 0xb0000000 0xb0000000 0 0x10000000
0x01000000 0x0 0x1000 0x1000 0 0xefff>;
u-boot,skip-auto-config-until-reloc;
-
+ u-boot,pci-pre-reloc = <
+ PCI_VENDEV(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_APL_UART2)>;
serial: serial@18,2 {
reg = <0x0200c210 0 0 0 0>;
diff --git a/drivers/block/Kconfig b/drivers/block/Kconfig
index 1e6dad8..4023332 100644
--- a/drivers/block/Kconfig
+++ b/drivers/block/Kconfig
@@ -1,7 +1,7 @@
config BLK
bool "Support block devices"
depends on DM
- default y if DM_MMC
+ default y if DM_MMC || DM_USB
help
Enable support for block devices, such as SCSI, MMC and USB
flash sticks. These provide a block-level interface which permits
diff --git a/drivers/clk/clk-uclass.c b/drivers/clk/clk-uclass.c
index f049e36..cea38a4 100644
--- a/drivers/clk/clk-uclass.c
+++ b/drivers/clk/clk-uclass.c
@@ -847,13 +847,17 @@
int clk_uclass_post_probe(struct udevice *dev)
{
+ int ret;
+
/*
* when a clock provider is probed. Call clk_set_defaults()
* also after the device is probed. This takes care of cases
* where the DT is used to setup default parents and rates
* using assigned-clocks
*/
- clk_set_defaults(dev, CLK_DEFAULTS_POST);
+ ret = clk_set_defaults(dev, CLK_DEFAULTS_POST);
+ if (ret)
+ return log_ret(ret);
return 0;
}
diff --git a/drivers/clk/clk_stm32mp1.c b/drivers/clk/clk_stm32mp1.c
index 0c0ef36..48c9514 100644
--- a/drivers/clk/clk_stm32mp1.c
+++ b/drivers/clk/clk_stm32mp1.c
@@ -540,6 +540,7 @@
STM32MP1_CLK_SET_CLR(RCC_MP_APB2ENSETR, 13, USART6_K, _UART6_SEL),
STM32MP1_CLK_SET_CLR_F(RCC_MP_APB3ENSETR, 13, VREF, _PCLK3),
+ STM32MP1_CLK_SET_CLR_F(RCC_MP_APB3ENSETR, 11, SYSCFG, _UNKNOWN_SEL),
STM32MP1_CLK_SET_CLR_F(RCC_MP_APB4ENSETR, 0, LTDC_PX, _PLL4_Q),
STM32MP1_CLK_SET_CLR_F(RCC_MP_APB4ENSETR, 4, DSI_PX, _PLL4_Q),
diff --git a/drivers/clk/imx/clk-imx8mm.c b/drivers/clk/imx/clk-imx8mm.c
index d32ff84..3aa8c64 100644
--- a/drivers/clk/imx/clk-imx8mm.c
+++ b/drivers/clk/imx/clk-imx8mm.c
@@ -131,6 +131,15 @@
static const char *imx8mm_usb_phy_sels[] = {"clock-osc-24m", "sys_pll1_100m", "sys_pll1_40m", "sys_pll2_100m",
"sys_pll2_200m", "clk_ext2", "clk_ext3", "audio_pll2_out", };
+static const char *imx8mm_ecspi1_sels[] = {"clock-osc-24m", "sys_pll2_200m", "sys_pll1_40m", "sys_pll1_160m",
+ "sys_pll1_800m", "sys_pll3_out", "sys_pll2_250m", "audio_pll2_out", };
+
+static const char *imx8mm_ecspi2_sels[] = {"clock-osc-24m", "sys_pll2_200m", "sys_pll1_40m", "sys_pll1_160m",
+ "sys_pll1_800m", "sys_pll3_out", "sys_pll2_250m", "audio_pll2_out", };
+
+static const char *imx8mm_ecspi3_sels[] = {"clock-osc-24m", "sys_pll2_200m", "sys_pll1_40m", "sys_pll1_160m",
+ "sys_pll1_800m", "sys_pll3_out", "sys_pll2_250m", "audio_pll2_out", };
+
static ulong imx8mm_clk_get_rate(struct clk *clk)
{
struct clk *c;
@@ -393,7 +402,19 @@
imx8m_clk_composite("usb_core_ref", imx8mm_usb_core_sels, base + 0xb100));
clk_dm(IMX8MM_CLK_USB_PHY_REF,
imx8m_clk_composite("usb_phy_ref", imx8mm_usb_phy_sels, base + 0xb180));
+ clk_dm(IMX8MM_CLK_ECSPI1,
+ imx8m_clk_composite("ecspi1", imx8mm_ecspi1_sels, base + 0xb280));
+ clk_dm(IMX8MM_CLK_ECSPI2,
+ imx8m_clk_composite("ecspi2", imx8mm_ecspi2_sels, base + 0xb300));
+ clk_dm(IMX8MM_CLK_ECSPI3,
+ imx8m_clk_composite("ecspi3", imx8mm_ecspi3_sels, base + 0xc180));
+ clk_dm(IMX8MM_CLK_ECSPI1_ROOT,
+ imx_clk_gate4("ecspi1_root_clk", "ecspi1", base + 0x4070, 0));
+ clk_dm(IMX8MM_CLK_ECSPI2_ROOT,
+ imx_clk_gate4("ecspi2_root_clk", "ecspi2", base + 0x4080, 0));
+ clk_dm(IMX8MM_CLK_ECSPI3_ROOT,
+ imx_clk_gate4("ecspi3_root_clk", "ecspi3", base + 0x4090, 0));
clk_dm(IMX8MM_CLK_I2C1_ROOT,
imx_clk_gate4("i2c1_root_clk", "i2c1", base + 0x4170, 0));
clk_dm(IMX8MM_CLK_I2C2_ROOT,
diff --git a/drivers/core/dump.c b/drivers/core/dump.c
index f8afea3..f2f9cac 100644
--- a/drivers/core/dump.c
+++ b/drivers/core/dump.c
@@ -130,18 +130,19 @@
struct driver *entry;
struct udevice *udev;
struct uclass *uc;
+ int ret;
int i;
puts("Driver uid uclass Devices\n");
puts("----------------------------------------------------------\n");
for (entry = d; entry < d + n_ents; entry++) {
- uclass_get(entry->id, &uc);
+ ret = uclass_get(entry->id, &uc);
printf("%-25.25s %-3.3d %-20.20s ", entry->name, entry->id,
- uc ? uc->uc_drv->name : "<no uclass>");
+ !ret ? uc->uc_drv->name : "<no uclass>");
- if (!uc) {
+ if (ret) {
puts("\n");
continue;
}
diff --git a/drivers/core/regmap.c b/drivers/core/regmap.c
index 3206f3d..5f98f85 100644
--- a/drivers/core/regmap.c
+++ b/drivers/core/regmap.c
@@ -293,6 +293,7 @@
int rc;
struct regmap **mapp, *map;
+ /* this looks like a leak, but devres takes care of it */
mapp = devres_alloc(devm_regmap_release, sizeof(struct regmap *),
__GFP_ZERO);
if (unlikely(!mapp))
diff --git a/drivers/misc/cros_ec_sandbox.c b/drivers/misc/cros_ec_sandbox.c
index db5e3b0..beea47c 100644
--- a/drivers/misc/cros_ec_sandbox.c
+++ b/drivers/misc/cros_ec_sandbox.c
@@ -5,6 +5,8 @@
* Copyright (c) 2013 The Chromium OS Authors.
*/
+#define LOG_CATEGORY UCLASS_CROS_EC
+
#include <common.h>
#include <cros_ec.h>
#include <dm.h>
@@ -221,11 +223,12 @@
int len;
cell = ofnode_get_property(node, "linux,keymap", &len);
+ if (!cell)
+ return log_msg_ret("prop", -EINVAL);
ec->matrix_count = len / 4;
ec->matrix = calloc(ec->matrix_count, sizeof(*ec->matrix));
if (!ec->matrix) {
- debug("%s: Out of memory for key matrix\n", __func__);
- return -1;
+ return log_msg_ret("mem", -ENOMEM);
}
/* Now read the data */
@@ -243,13 +246,12 @@
matrix->col >= KEYBOARD_COLS) {
debug("%s: Matrix pos out of range (%d,%d)\n",
__func__, matrix->row, matrix->col);
- return -1;
+ return log_msg_ret("matrix", -ERANGE);
}
}
if (upto != ec->matrix_count) {
- debug("%s: Read mismatch from key matrix\n", __func__);
- return -1;
+ return log_msg_ret("matrix", -E2BIG);
}
return 0;
diff --git a/drivers/mmc/mmc.c b/drivers/mmc/mmc.c
index 1e83007..8078a89 100644
--- a/drivers/mmc/mmc.c
+++ b/drivers/mmc/mmc.c
@@ -2766,7 +2766,7 @@
return mmc_power_on(mmc);
}
-int mmc_get_op_cond(struct mmc *mmc)
+int mmc_get_op_cond(struct mmc *mmc, bool quiet)
{
bool uhs_en = supports_uhs(mmc->cfg->host_caps);
int err;
@@ -2842,7 +2842,8 @@
if (err) {
#if !defined(CONFIG_SPL_BUILD) || defined(CONFIG_SPL_LIBCOMMON_SUPPORT)
- pr_err("Card did not respond to voltage select! : %d\n", err);
+ if (!quiet)
+ pr_err("Card did not respond to voltage select! : %d\n", err);
#endif
return -EOPNOTSUPP;
}
@@ -2882,7 +2883,7 @@
return -ENOMEDIUM;
}
- err = mmc_get_op_cond(mmc);
+ err = mmc_get_op_cond(mmc, false);
if (!err)
mmc->init_in_progress = 1;
diff --git a/drivers/mtd/spi/spi-nor-ids.c b/drivers/mtd/spi/spi-nor-ids.c
index 1af1c86..6f84c54 100644
--- a/drivers/mtd/spi/spi-nor-ids.c
+++ b/drivers/mtd/spi/spi-nor-ids.c
@@ -160,6 +160,8 @@
{ INFO("mx25l12855e", 0xc22618, 0, 64 * 1024, 256, 0) },
{ INFO("mx25l25635e", 0xc22019, 0, 64 * 1024, 512, SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) },
{ INFO("mx25u25635f", 0xc22539, 0, 64 * 1024, 512, SECT_4K | SPI_NOR_4B_OPCODES) },
+ { INFO("mx25v8035f", 0xc22314, 0, 64 * 1024, 16, SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) },
+ { INFO("mx25r1635f", 0xc22815, 0, 64 * 1024, 32, SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) },
{ INFO("mx25l25655e", 0xc22619, 0, 64 * 1024, 512, 0) },
{ INFO("mx66l51235l", 0xc2201a, 0, 64 * 1024, 1024, SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | SPI_NOR_4B_OPCODES) },
{ INFO("mx66u51235f", 0xc2253a, 0, 64 * 1024, 1024, SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | SPI_NOR_4B_OPCODES) },
diff --git a/drivers/net/Kconfig b/drivers/net/Kconfig
index 4834016..726ad36 100644
--- a/drivers/net/Kconfig
+++ b/drivers/net/Kconfig
@@ -402,6 +402,13 @@
endif #DM_ETH
endif #KS8851_MLL
+config KSZ9477
+ bool "Microchip KSZ9477 I2C controller driver"
+ depends on DM_DSA && DM_I2C
+ help
+ This driver implements a DSA switch driver for the KSZ9477 family
+ of GbE switches using the I2C interface.
+
config MVGBE
bool "Marvell Orion5x/Kirkwood network interface support"
depends on ARCH_KIRKWOOD || ARCH_ORION5X
diff --git a/drivers/net/Makefile b/drivers/net/Makefile
index d56baa6..03900ff 100644
--- a/drivers/net/Makefile
+++ b/drivers/net/Makefile
@@ -39,6 +39,7 @@
obj-$(CONFIG_FTMAC100) += ftmac100.o
obj-$(CONFIG_GMAC_ROCKCHIP) += gmac_rockchip.o
obj-$(CONFIG_KS8851_MLL) += ks8851_mll.o
+obj-$(CONFIG_KSZ9477) += ksz9477.o
obj-$(CONFIG_LAN91C96) += lan91c96.o
obj-$(CONFIG_LPC32XX_ETH) += lpc32xx_eth.o
obj-$(CONFIG_MACB) += macb.o
diff --git a/drivers/net/fec_mxc.c b/drivers/net/fec_mxc.c
index 4fd5c01..db2cdaf 100644
--- a/drivers/net/fec_mxc.c
+++ b/drivers/net/fec_mxc.c
@@ -146,7 +146,7 @@
CONFIG_IS_ENABLED(CLK_CCF)) {
dev = udev;
if (!dev) {
- ret = uclass_get_device(UCLASS_ETH, idx, &dev);
+ ret = uclass_get_device_by_seq(UCLASS_ETH, idx, &dev);
if (ret < 0) {
debug("Can't get FEC udev: %d\n", ret);
return ret;
@@ -458,6 +458,9 @@
else if (fec->xcv_type == RMII)
rcntrl |= FEC_RCNTRL_RMII;
+ if (fec->promisc)
+ rcntrl |= 0x8;
+
writel(rcntrl, &fec->eth->r_cntrl);
}
@@ -1278,6 +1281,15 @@
return fec_get_hwaddr(priv->dev_id, pdata->enetaddr);
}
+static int fecmxc_set_promisc(struct udevice *dev, bool enable)
+{
+ struct fec_priv *priv = dev_get_priv(dev);
+
+ priv->promisc = enable;
+
+ return 0;
+}
+
static int fecmxc_free_pkt(struct udevice *dev, uchar *packet, int length)
{
if (packet)
@@ -1294,6 +1306,7 @@
.stop = fecmxc_halt,
.write_hwaddr = fecmxc_set_hwaddr,
.read_rom_hwaddr = fecmxc_read_rom_hwaddr,
+ .set_promisc = fecmxc_set_promisc,
};
static int device_get_phy_addr(struct fec_priv *priv, struct udevice *dev)
@@ -1304,7 +1317,11 @@
ret = dev_read_phandle_with_args(dev, "phy-handle", NULL, 0, 0,
&phandle_args);
if (ret) {
- debug("Failed to find phy-handle (err = %d\n)", ret);
+ priv->phy_of_node = ofnode_find_subnode(dev_ofnode(dev),
+ "fixed-link");
+ if (ofnode_valid(priv->phy_of_node))
+ return 0;
+ debug("Failed to find phy-handle (err = %d)\n", ret);
return ret;
}
diff --git a/drivers/net/fec_mxc.h b/drivers/net/fec_mxc.h
index 5ccde91..62b55ef 100644
--- a/drivers/net/fec_mxc.h
+++ b/drivers/net/fec_mxc.h
@@ -272,6 +272,7 @@
struct clk clk_ref;
struct clk clk_ptp;
u32 clk_rate;
+ char promisc;
};
/**
diff --git a/drivers/net/ksz9477.c b/drivers/net/ksz9477.c
new file mode 100644
index 0000000..ed8f189
--- /dev/null
+++ b/drivers/net/ksz9477.c
@@ -0,0 +1,546 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * (C) Copyright 2020
+ * Tim Harvey, Gateworks Corporation
+ */
+
+#include <dm.h>
+#include <dm/device_compat.h>
+#include <dm/device-internal.h>
+#include <dm/lists.h>
+#include <eth_phy.h>
+#include <linux/delay.h>
+#include <miiphy.h>
+#include <i2c.h>
+#include <net/dsa.h>
+
+#include <asm-generic/gpio.h>
+
+/* Global registers */
+
+/* Chip ID */
+#define REG_CHIP_ID0__1 0x0000
+
+/* Operation control */
+#define REG_SW_OPERATION 0x0300
+#define SW_RESET BIT(1)
+#define SW_START BIT(0)
+
+/* Port Specific Registers */
+#define PORT_CTRL_ADDR(port, addr) ((addr) | (((port) + 1) << 12))
+
+/* Port Control */
+#define REG_PORT_XMII_CTRL_1 0x0301
+#define PORT_MII_NOT_1GBIT BIT(6)
+#define PORT_MII_SEL_EDGE BIT(5)
+#define PORT_RGMII_ID_IG_ENABLE BIT(4)
+#define PORT_RGMII_ID_EG_ENABLE BIT(3)
+#define PORT_MII_MAC_MODE BIT(2)
+#define PORT_MII_SEL_M 0x3
+#define PORT_RGMII_SEL 0x0
+#define PORT_RMII_SEL 0x1
+#define PORT_GMII_SEL 0x2
+#define PORT_MII_SEL 0x3
+
+/* Port MSTP State Register */
+#define REG_PORT_MSTP_STATE 0x0b04
+#define PORT_TX_ENABLE BIT(2)
+#define PORT_RX_ENABLE BIT(1)
+#define PORT_LEARN_DISABLE BIT(0)
+
+/* MMD */
+#define REG_PORT_PHY_MMD_SETUP 0x011A
+#define PORT_MMD_OP_MODE_M 0x3
+#define PORT_MMD_OP_MODE_S 14
+#define PORT_MMD_OP_INDEX 0
+#define PORT_MMD_OP_DATA_NO_INCR 1
+#define PORT_MMD_OP_DATA_INCR_RW 2
+#define PORT_MMD_OP_DATA_INCR_W 3
+#define PORT_MMD_DEVICE_ID_M 0x1F
+#define MMD_SETUP(mode, dev) (((u16)(mode) << PORT_MMD_OP_MODE_S) | (dev))
+#define REG_PORT_PHY_MMD_INDEX_DATA 0x011C
+
+struct ksz_dsa_priv {
+ struct udevice *dev;
+ int active_port;
+};
+
+static inline int ksz_read8(struct udevice *dev, u32 reg, u8 *val)
+{
+ int ret = dm_i2c_read(dev, reg, val, 1);
+
+ dev_dbg(dev, "%s 0x%04x<<0x%02x\n", __func__, reg, *val);
+
+ return ret;
+}
+
+static inline int ksz_pread8(struct udevice *dev, int port, int reg, u8 *val)
+{
+ return ksz_read8(dev, PORT_CTRL_ADDR(port, reg), val);
+}
+
+static inline int ksz_write8(struct udevice *dev, u32 reg, u8 val)
+{
+ dev_dbg(dev, "%s 0x%04x>>0x%02x\n", __func__, reg, val);
+ return dm_i2c_write(dev, reg, &val, 1);
+}
+
+static inline int ksz_pwrite8(struct udevice *dev, int port, int reg, u8 val)
+{
+ return ksz_write8(dev, PORT_CTRL_ADDR(port, reg), val);
+}
+
+static inline int ksz_write16(struct udevice *dev, u32 reg, u16 val)
+{
+ u8 buf[2];
+
+ buf[1] = val & 0xff;
+ buf[0] = val >> 8;
+ dev_dbg(dev, "%s 0x%04x>>0x%04x\n", __func__, reg, val);
+
+ return dm_i2c_write(dev, reg, buf, 2);
+}
+
+static inline int ksz_pwrite16(struct udevice *dev, int port, int reg, u16 val)
+{
+ return ksz_write16(dev, PORT_CTRL_ADDR(port, reg), val);
+}
+
+static inline int ksz_read16(struct udevice *dev, u32 reg, u16 *val)
+{
+ u8 buf[2];
+ int ret;
+
+ ret = dm_i2c_read(dev, reg, buf, 2);
+ *val = (buf[0] << 8) | buf[1];
+ dev_dbg(dev, "%s 0x%04x<<0x%04x\n", __func__, reg, *val);
+
+ return ret;
+}
+
+static inline int ksz_pread16(struct udevice *dev, int port, int reg, u16 *val)
+{
+ return ksz_read16(dev, PORT_CTRL_ADDR(port, reg), val);
+}
+
+static inline int ksz_read32(struct udevice *dev, u32 reg, u32 *val)
+{
+ return dm_i2c_read(dev, reg, (u8 *)val, 4);
+}
+
+static inline int ksz_pread32(struct udevice *dev, int port, int reg, u32 *val)
+{
+ return ksz_read32(dev, PORT_CTRL_ADDR(port, reg), val);
+}
+
+static inline int ksz_write32(struct udevice *dev, u32 reg, u32 val)
+{
+ u8 buf[4];
+
+ buf[3] = val & 0xff;
+ buf[2] = (val >> 24) & 0xff;
+ buf[1] = (val >> 16) & 0xff;
+ buf[0] = (val >> 8) & 0xff;
+ dev_dbg(dev, "%s 0x%04x>>0x%04x\n", __func__, reg, val);
+
+ return dm_i2c_write(dev, reg, buf, 4);
+}
+
+static inline int ksz_pwrite32(struct udevice *dev, int port, int reg, u32 val)
+{
+ return ksz_write32(dev, PORT_CTRL_ADDR(port, reg), val);
+}
+
+static __maybe_unused void ksz_port_mmd_read(struct udevice *dev, int port,
+ u8 addr, u16 reg, u16 *val)
+{
+ ksz_pwrite16(dev, port, REG_PORT_PHY_MMD_SETUP, MMD_SETUP(PORT_MMD_OP_INDEX, addr));
+ ksz_pwrite16(dev, port, REG_PORT_PHY_MMD_INDEX_DATA, reg);
+ ksz_pwrite16(dev, port, REG_PORT_PHY_MMD_SETUP, MMD_SETUP(PORT_MMD_OP_DATA_NO_INCR, addr));
+ ksz_pread16(dev, port, REG_PORT_PHY_MMD_INDEX_DATA, val);
+ dev_dbg(dev, "%s P%d 0x%02x:0x%04x<<0x%04x\n", __func__, port + 1, addr, reg, *val);
+}
+
+static void ksz_port_mmd_write(struct udevice *dev, int port, u8 addr, u16 reg, u16 val)
+{
+ dev_dbg(dev, "%s P%d 0x%02x:0x%04x>>0x%04x\n", __func__, port + 1, addr, addr, val);
+ ksz_pwrite16(dev, port, REG_PORT_PHY_MMD_SETUP, MMD_SETUP(PORT_MMD_OP_INDEX, addr));
+ ksz_pwrite16(dev, port, REG_PORT_PHY_MMD_INDEX_DATA, addr);
+ ksz_pwrite16(dev, port, REG_PORT_PHY_MMD_SETUP, MMD_SETUP(PORT_MMD_OP_DATA_NO_INCR, addr));
+ ksz_pwrite16(dev, port, REG_PORT_PHY_MMD_INDEX_DATA, val);
+}
+
+/* Apply PHY settings to address errata listed in KSZ9477, KSZ9897, KSZ9896, KSZ9567
+ * Silicon Errata and Data Sheet Clarification documents
+ */
+static void ksz_phy_errata_setup(struct udevice *dev, int port)
+{
+ dev_dbg(dev, "%s P%d\n", __func__, port + 1);
+
+ /* Register settings are needed to improve PHY receive performance */
+ ksz_port_mmd_write(dev, port, 0x01, 0x6f, 0xdd0b);
+ ksz_port_mmd_write(dev, port, 0x01, 0x8f, 0x6032);
+ ksz_port_mmd_write(dev, port, 0x01, 0x9d, 0x248c);
+ ksz_port_mmd_write(dev, port, 0x01, 0x75, 0x0060);
+ ksz_port_mmd_write(dev, port, 0x01, 0xd3, 0x7777);
+ ksz_port_mmd_write(dev, port, 0x1c, 0x06, 0x3008);
+ ksz_port_mmd_write(dev, port, 0x1c, 0x08, 0x2001);
+
+ /* Transmit waveform amplitude can be improved (1000BASE-T, 100BASE-TX, 10BASE-Te) */
+ ksz_port_mmd_write(dev, port, 0x1c, 0x04, 0x00d0);
+
+ /* Energy Efficient Ethernet (EEE) feature select must be manually disabled */
+ ksz_port_mmd_write(dev, port, 0x07, 0x3c, 0x0000);
+
+ /* Register settings are required to meet data sheet supply current specifications */
+ ksz_port_mmd_write(dev, port, 0x1c, 0x13, 0x6eff);
+ ksz_port_mmd_write(dev, port, 0x1c, 0x14, 0xe6ff);
+ ksz_port_mmd_write(dev, port, 0x1c, 0x15, 0x6eff);
+ ksz_port_mmd_write(dev, port, 0x1c, 0x16, 0xe6ff);
+ ksz_port_mmd_write(dev, port, 0x1c, 0x17, 0x00ff);
+ ksz_port_mmd_write(dev, port, 0x1c, 0x18, 0x43ff);
+ ksz_port_mmd_write(dev, port, 0x1c, 0x19, 0xc3ff);
+ ksz_port_mmd_write(dev, port, 0x1c, 0x1a, 0x6fff);
+ ksz_port_mmd_write(dev, port, 0x1c, 0x1b, 0x07ff);
+ ksz_port_mmd_write(dev, port, 0x1c, 0x1c, 0x0fff);
+ ksz_port_mmd_write(dev, port, 0x1c, 0x1d, 0xe7ff);
+ ksz_port_mmd_write(dev, port, 0x1c, 0x1e, 0xefff);
+ ksz_port_mmd_write(dev, port, 0x1c, 0x20, 0xeeee);
+}
+
+/*
+ * mii bus driver
+ */
+#define KSZ_MDIO_CHILD_DRV_NAME "ksz_mdio"
+
+struct ksz_mdio_priv {
+ struct ksz_dsa_priv *ksz;
+};
+
+static int dm_ksz_mdio_read(struct udevice *dev, int addr, int devad, int reg)
+{
+ struct ksz_mdio_priv *priv = dev_get_priv(dev);
+ struct ksz_dsa_priv *ksz = priv->ksz;
+ u16 val = 0xffff;
+
+ ksz_pread16(ksz->dev, addr, 0x100 + (reg << 1), &val);
+ dev_dbg(ksz->dev, "%s P%d reg=0x%04x:0x%04x<<0x%04x\n", __func__,
+ addr + 1, reg, 0x100 + (reg << 1), val);
+
+ return val;
+};
+
+static int dm_ksz_mdio_write(struct udevice *dev, int addr, int devad, int reg, u16 val)
+{
+ struct ksz_mdio_priv *priv = dev_get_priv(dev);
+ struct ksz_dsa_priv *ksz = priv->ksz;
+
+ dev_dbg(ksz->dev, "%s P%d reg=0x%04x:%04x>>0x%04x\n",
+ __func__, addr + 1, reg, 0x100 + (reg << 1), val);
+ ksz_pwrite16(ksz->dev, addr, 0x100 + (reg << 1), val);
+
+ return 0;
+}
+
+static const struct mdio_ops ksz_mdio_ops = {
+ .read = dm_ksz_mdio_read,
+ .write = dm_ksz_mdio_write,
+};
+
+static int ksz_mdio_bind(struct udevice *dev)
+{
+ char name[16];
+ static int num_devices;
+
+ dev_dbg(dev, "%s\n", __func__);
+ sprintf(name, "ksz-mdio-%d", num_devices++);
+ device_set_name(dev, name);
+
+ return 0;
+}
+
+static int ksz_mdio_probe(struct udevice *dev)
+{
+ struct ksz_mdio_priv *priv = dev_get_priv(dev);
+
+ dev_dbg(dev, "%s\n", __func__);
+ priv->ksz = dev_get_parent_priv(dev->parent);
+
+ return 0;
+}
+
+static const struct udevice_id ksz_mdio_ids[] = {
+ { .compatible = "microchip,ksz-mdio" },
+ { }
+};
+
+U_BOOT_DRIVER(ksz_mdio) = {
+ .name = KSZ_MDIO_CHILD_DRV_NAME,
+ .id = UCLASS_MDIO,
+ .of_match = ksz_mdio_ids,
+ .bind = ksz_mdio_bind,
+ .probe = ksz_mdio_probe,
+ .ops = &ksz_mdio_ops,
+ .priv_auto = sizeof(struct ksz_mdio_priv),
+ .plat_auto = sizeof(struct mdio_perdev_priv),
+};
+
+static int ksz_port_setup(struct udevice *dev, int port,
+ phy_interface_t interface)
+{
+ struct dsa_pdata *pdata = dev_get_uclass_plat(dev);
+ u8 data8;
+
+ dev_dbg(dev, "%s P%d %s\n", __func__, port + 1,
+ (port == pdata->cpu_port) ? "cpu" : "");
+
+ if (port != pdata->cpu_port) {
+ /* phy port: config errata and leds */
+ ksz_phy_errata_setup(dev, port);
+ } else {
+ /* cpu port: configure MAC interface mode */
+ ksz_pread8(dev, port, REG_PORT_XMII_CTRL_1, &data8);
+ dev_dbg(dev, "%s P%d cpu interface %s\n", __func__, port + 1,
+ phy_string_for_interface(interface));
+ switch (interface) {
+ case PHY_INTERFACE_MODE_MII:
+ data8 &= ~PORT_MII_SEL_M;
+ data8 |= PORT_MII_SEL;
+ data8 |= PORT_MII_NOT_1GBIT;
+ break;
+ case PHY_INTERFACE_MODE_RMII:
+ data8 &= ~PORT_MII_SEL_M;
+ data8 |= PORT_RMII_SEL;
+ data8 |= PORT_MII_NOT_1GBIT;
+ break;
+ case PHY_INTERFACE_MODE_GMII:
+ data8 &= ~PORT_MII_SEL_M;
+ data8 |= PORT_GMII_SEL;
+ data8 &= ~PORT_MII_NOT_1GBIT;
+ break;
+ default:
+ data8 &= ~PORT_MII_SEL_M;
+ data8 |= PORT_RGMII_SEL;
+ data8 &= ~PORT_MII_NOT_1GBIT;
+ data8 &= ~PORT_RGMII_ID_IG_ENABLE;
+ data8 &= ~PORT_RGMII_ID_EG_ENABLE;
+ if (interface == PHY_INTERFACE_MODE_RGMII_ID ||
+ interface == PHY_INTERFACE_MODE_RGMII_RXID)
+ data8 |= PORT_RGMII_ID_IG_ENABLE;
+ if (interface == PHY_INTERFACE_MODE_RGMII_ID ||
+ interface == PHY_INTERFACE_MODE_RGMII_TXID)
+ data8 |= PORT_RGMII_ID_EG_ENABLE;
+ break;
+ }
+ ksz_write8(dev, PORT_CTRL_ADDR(port, REG_PORT_XMII_CTRL_1), data8);
+ }
+
+ return 0;
+}
+
+static int ksz_port_enable(struct udevice *dev, int port, struct phy_device *phy)
+{
+ struct dsa_pdata *pdata = dev_get_uclass_plat(dev);
+ struct ksz_dsa_priv *priv = dev_get_priv(dev);
+ int supported = PHY_GBIT_FEATURES;
+ u8 data8;
+ int ret;
+
+ dev_dbg(dev, "%s P%d 0x%x %s\n", __func__, port + 1, phy->phy_id,
+ phy_string_for_interface(phy->interface));
+
+ /* setup this port */
+ ret = ksz_port_setup(dev, port, phy->interface);
+ if (ret) {
+ dev_err(dev, "port setup failed: %d\n", ret);
+ return ret;
+ }
+
+ /* enable port forwarding for this port */
+ ksz_pread8(priv->dev, port, REG_PORT_MSTP_STATE, &data8);
+ data8 &= ~(PORT_TX_ENABLE | PORT_RX_ENABLE | PORT_LEARN_DISABLE);
+ data8 |= (PORT_TX_ENABLE | PORT_RX_ENABLE);
+ ksz_pwrite8(priv->dev, port, REG_PORT_MSTP_STATE, data8);
+
+ /* if cpu master we are done */
+ if (port == pdata->cpu_port)
+ return 0;
+
+ /* configure phy */
+ phy->supported &= supported;
+ phy->advertising &= supported;
+ ret = phy_config(phy);
+ if (ret)
+ return ret;
+
+ ret = phy_startup(phy);
+ if (ret)
+ return ret;
+
+ /* start switch */
+ ksz_read8(priv->dev, REG_SW_OPERATION, &data8);
+ data8 |= SW_START;
+ ksz_write8(priv->dev, REG_SW_OPERATION, data8);
+
+ /* keep track of current enabled non-cpu port */
+ priv->active_port = port;
+
+ return 0;
+}
+
+static void ksz_port_disable(struct udevice *dev, int port, struct phy_device *phy)
+{
+ struct dsa_pdata *pdata = dev_get_uclass_plat(dev);
+ struct ksz_dsa_priv *priv = dev_get_priv(dev);
+ u8 data8;
+
+ dev_dbg(dev, "%s P%d 0x%x\n", __func__, port + 1, phy->phy_id);
+
+ /* can't disable CPU port without re-configuring/re-starting switch */
+ if (port == pdata->cpu_port)
+ return;
+
+ /* disable port */
+ ksz_pread8(priv->dev, port, REG_PORT_MSTP_STATE, &data8);
+ data8 &= ~(PORT_TX_ENABLE | PORT_RX_ENABLE | PORT_LEARN_DISABLE);
+ data8 |= PORT_LEARN_DISABLE;
+ ksz_pwrite8(priv->dev, port, REG_PORT_MSTP_STATE, data8);
+
+ /*
+ * we don't call phy_shutdown here to avoid waiting next time we use
+ * the port, but the downside is that remote side will think we're
+ * actively processing traffic although we are not.
+ */
+}
+
+static int ksz_xmit(struct udevice *dev, int port, void *packet, int length)
+{
+ dev_dbg(dev, "%s P%d %d\n", __func__, port + 1, length);
+
+ return 0;
+}
+
+static int ksz_recv(struct udevice *dev, int *port, void *packet, int length)
+{
+ struct ksz_dsa_priv *priv = dev_get_priv(dev);
+
+ dev_dbg(dev, "%s P%d %d\n", __func__, priv->active_port + 1, length);
+ *port = priv->active_port;
+
+ return 0;
+};
+
+static const struct dsa_ops ksz_dsa_ops = {
+ .port_enable = ksz_port_enable,
+ .port_disable = ksz_port_disable,
+ .xmit = ksz_xmit,
+ .rcv = ksz_recv,
+};
+
+static int ksz_probe_mdio(struct udevice *dev)
+{
+ ofnode node, mdios;
+ int ret;
+
+ mdios = dev_read_subnode(dev, "mdios");
+ if (ofnode_valid(mdios)) {
+ ofnode_for_each_subnode(node, mdios) {
+ const char *name = ofnode_get_name(node);
+ struct udevice *pdev;
+
+ ret = device_bind_driver_to_node(dev,
+ KSZ_MDIO_CHILD_DRV_NAME,
+ name, node, &pdev);
+ if (ret)
+ dev_err(dev, "failed to probe %s: %d\n", name, ret);
+ }
+ }
+
+ return 0;
+}
+
+/*
+ * I2C driver
+ */
+static int ksz_i2c_probe(struct udevice *dev)
+{
+ struct dsa_pdata *pdata = dev_get_uclass_plat(dev);
+ struct ksz_dsa_priv *priv = dev_get_priv(dev);
+ struct udevice *master = dsa_get_master(dev);
+ int i, ret;
+ u8 data8;
+ u32 id;
+
+ if (!master)
+ return -ENODEV;
+
+ dev_dbg(dev, "%s %s master:%s\n", __func__, dev->name, master->name);
+ dev_set_parent_priv(dev, priv);
+
+ ret = i2c_set_chip_offset_len(dev, 2);
+ if (ret) {
+ printf("i2c_set_chip_offset_len failed: %d\n", ret);
+ return ret;
+ }
+
+ /* default config */
+ priv->dev = dev;
+
+ /* chip level reset */
+ ksz_read8(priv->dev, REG_SW_OPERATION, &data8);
+ data8 |= SW_RESET;
+ ksz_write8(priv->dev, REG_SW_OPERATION, data8);
+
+ /* read chip id */
+ ret = ksz_read32(dev, REG_CHIP_ID0__1, &id);
+ if (ret)
+ return ret;
+ id = __swab32(id);
+ dev_dbg(dev, "%s id=0x%08x\n", __func__, id);
+ switch (id & 0xffffff00) {
+ case 0x00947700:
+ puts("KSZ9477S: ");
+ break;
+ case 0x00956700:
+ puts("KSZ9567R: ");
+ break;
+ case 0x00989700:
+ puts("KSZ9897S: ");
+ break;
+ default:
+ dev_err(dev, "invalid chip id: 0x%08x\n", id);
+ return -EINVAL;
+ }
+
+ /* probe mdio bus */
+ ret = ksz_probe_mdio(dev);
+ if (ret)
+ return ret;
+
+ /* disable ports by default */
+ for (i = 0; i < pdata->num_ports; i++) {
+ ksz_pread8(priv->dev, i, REG_PORT_MSTP_STATE, &data8);
+ data8 &= ~(PORT_TX_ENABLE | PORT_RX_ENABLE | PORT_LEARN_DISABLE);
+ ksz_pwrite8(priv->dev, i, REG_PORT_MSTP_STATE, data8);
+ }
+
+ dsa_set_tagging(dev, 0, 0);
+
+ return 0;
+};
+
+static const struct udevice_id ksz_i2c_ids[] = {
+ { .compatible = "microchip,ksz9897" },
+ { .compatible = "microchip,ksz9477" },
+ { .compatible = "microchip,ksz9567" },
+ { }
+};
+
+U_BOOT_DRIVER(ksz) = {
+ .name = "ksz-switch",
+ .id = UCLASS_DSA,
+ .of_match = ksz_i2c_ids,
+ .probe = ksz_i2c_probe,
+ .ops = &ksz_dsa_ops,
+ .priv_auto = sizeof(struct ksz_dsa_priv),
+};
diff --git a/drivers/net/mcffec.c b/drivers/net/mcffec.c
index 43bb761..cef9eec 100644
--- a/drivers/net/mcffec.c
+++ b/drivers/net/mcffec.c
@@ -105,17 +105,11 @@
}
if ((dup_spd & 0xFFFF) == _100BASET) {
-#ifdef CONFIG_MCF5445x
- fecp->rcr &= ~0x200; /* disabled 10T base */
-#endif
#ifdef MII_DEBUG
printf("100Mbps\n");
#endif
bd->bi_ethspeed = 100;
} else {
-#ifdef CONFIG_MCF5445x
- fecp->rcr |= 0x200; /* enabled 10T base */
-#endif
#ifdef MII_DEBUG
printf("10Mbps\n");
#endif
diff --git a/drivers/net/sandbox-raw.c b/drivers/net/sandbox-raw.c
index ce66ff7..99eb7a3 100644
--- a/drivers/net/sandbox-raw.c
+++ b/drivers/net/sandbox-raw.c
@@ -161,7 +161,7 @@
ifname = dev_read_string(dev, "host-raw-interface");
if (ifname) {
- strncpy(priv->host_ifname, ifname, IFNAMSIZ);
+ strlcpy(priv->host_ifname, ifname, IFNAMSIZ);
printf(": Using %s from DT\n", priv->host_ifname);
}
if (dev_read_u32(dev, "host-raw-interface-idx",
diff --git a/drivers/pci/Kconfig b/drivers/pci/Kconfig
index 517cf95..2ef4d46 100644
--- a/drivers/pci/Kconfig
+++ b/drivers/pci/Kconfig
@@ -1,22 +1,23 @@
menuconfig PCI
bool "PCI support"
+ depends on DM
default y if PPC
+ select DM_PCI
help
Enable support for PCI (Peripheral Interconnect Bus), a type of bus
used on some devices to allow the CPU to communicate with its
peripherals.
-if PCI
-
config DM_PCI
- bool "Enable driver model for PCI"
- depends on DM
+ bool
help
Use driver model for PCI. Driver model is the new method for
orgnising devices in U-Boot. For PCI, driver model keeps track of
available PCI devices, allows scanning of PCI buses and provides
device configuration support.
+if PCI
+
config DM_PCI_COMPAT
bool "Enable compatible functions for PCI"
depends on DM_PCI
@@ -54,6 +55,19 @@
region type. This helps to add support for SoC's like OcteonTX/TX2
where every peripheral is on the PCI bus.
+config PCI_MAP_SYSTEM_MEMORY
+ bool "Map local system memory from a virtual base address"
+ depends on PCI || DM_PCI
+ depends on MIPS
+ default n
+ help
+ Say Y if base address of system memory is being used as a virtual address
+ instead of a physical address (e.g. on MIPS). The PCI core will then remap
+ the virtual memory base address to a physical address when adding the PCI
+ region of type PCI_REGION_SYS_MEMORY.
+ This should only be required on MIPS where CONFIG_SYS_SDRAM_BASE is still
+ being used as virtual address.
+
config PCI_SRIOV
bool "Enable Single Root I/O Virtualization support for PCI"
depends on PCI || DM_PCI
diff --git a/drivers/pci/Makefile b/drivers/pci/Makefile
index ec8ee9d..83d7a4e 100644
--- a/drivers/pci/Makefile
+++ b/drivers/pci/Makefile
@@ -3,16 +3,12 @@
# (C) Copyright 2000-2007
# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
-ifneq ($(CONFIG_DM_PCI),)
obj-$(CONFIG_DM_VIDEO) += pci_rom.o
obj-$(CONFIG_PCI) += pci-uclass.o pci_auto.o
obj-$(CONFIG_DM_PCI_COMPAT) += pci_compat.o
obj-$(CONFIG_PCI_SANDBOX) += pci_sandbox.o
obj-$(CONFIG_SANDBOX) += pci-emul-uclass.o
obj-$(CONFIG_X86) += pci_x86.o pci_rom.o
-else
-obj-$(CONFIG_PCI) += pci.o pci_auto_old.o
-endif
obj-$(CONFIG_PCI) += pci_auto_common.o pci_common.o
obj-$(CONFIG_PCIE_ECAM_GENERIC) += pcie_ecam_generic.o
diff --git a/drivers/pci/pci-aardvark.c b/drivers/pci/pci-aardvark.c
index 96aa039..1b9bae7 100644
--- a/drivers/pci/pci-aardvark.c
+++ b/drivers/pci/pci-aardvark.c
@@ -605,25 +605,26 @@
/*
* The n-th PCIe window is configured by tuple (match, remap, mask)
- * and an access to address A uses this window it if A matches the
+ * and an access to address A uses this window if A matches the
* match with given mask.
* So every PCIe window size must be a power of two and every start
* address must be aligned to window size. Minimal size is 64 KiB
- * because lower 16 bits of mask must be zero.
+ * because lower 16 bits of mask must be zero. Remapped address
+ * may have set only bits from the mask.
*/
while (*wins < OB_WIN_COUNT && size > 0) {
/* Calculate the largest aligned window size */
win_size = (1ULL << (fls64(size) - 1)) |
(phys_start ? (1ULL << __ffs64(phys_start)) : 0);
win_size = 1ULL << __ffs64(win_size);
- if (win_size < 0x10000)
+ win_mask = ~(win_size - 1);
+ if (win_size < 0x10000 || (bus_start & ~win_mask))
break;
dev_dbg(pcie->dev,
"Configuring PCIe window %d: [0x%llx-0x%llx] as 0x%x\n",
*wins, (u64)phys_start, (u64)phys_start + win_size,
actions);
- win_mask = ~(win_size - 1) & ~0xffff;
pcie_advk_set_ob_win(pcie, *wins, phys_start, bus_start,
win_mask, actions);
diff --git a/drivers/pci/pci-uclass.c b/drivers/pci/pci-uclass.c
index cb9aa81..ce2eb5d 100644
--- a/drivers/pci/pci-uclass.c
+++ b/drivers/pci/pci-uclass.c
@@ -21,6 +21,7 @@
#if defined(CONFIG_X86) && defined(CONFIG_HAVE_FSP)
#include <asm/fsp/fsp_support.h>
#endif
+#include <dt-bindings/pci/pci.h>
#include <linux/delay.h>
#include "pci_internal.h"
@@ -164,7 +165,7 @@
}
static int pci_device_matches_ids(struct udevice *dev,
- struct pci_device_id *ids)
+ const struct pci_device_id *ids)
{
struct pci_child_plat *pplat;
int i;
@@ -181,7 +182,7 @@
return -EINVAL;
}
-int pci_bus_find_devices(struct udevice *bus, struct pci_device_id *ids,
+int pci_bus_find_devices(struct udevice *bus, const struct pci_device_id *ids,
int *indexp, struct udevice **devp)
{
struct udevice *dev;
@@ -201,7 +202,7 @@
return -ENODEV;
}
-int pci_find_device_id(struct pci_device_id *ids, int index,
+int pci_find_device_id(const struct pci_device_id *ids, int index,
struct udevice **devp)
{
struct udevice *bus;
@@ -682,6 +683,34 @@
}
/**
+ * pci_need_device_pre_reloc() - Check if a device should be bound
+ *
+ * This checks a list of vendor/device-ID values indicating devices that should
+ * be bound before relocation.
+ *
+ * @bus: Bus to check
+ * @vendor: Vendor ID to check
+ * @device: Device ID to check
+ * @return true if the vendor/device is in the list, false if not
+ */
+static bool pci_need_device_pre_reloc(struct udevice *bus, uint vendor,
+ uint device)
+{
+ u32 vendev;
+ int index;
+
+ for (index = 0;
+ !dev_read_u32_index(bus, "u-boot,pci-pre-reloc", index,
+ &vendev);
+ index++) {
+ if (vendev == PCI_VENDEV(vendor, device))
+ return true;
+ }
+
+ return false;
+}
+
+/**
* pci_find_and_bind_driver() - Find and bind the right PCI driver
*
* This only looks at certain fields in the descriptor.
@@ -769,7 +798,9 @@
* precious memory space as on some platforms as that space is pretty
* limited (ie: using Cache As RAM).
*/
- if (!(gd->flags & GD_FLG_RELOC) && !bridge)
+ if (!(gd->flags & GD_FLG_RELOC) && !bridge &&
+ !pci_need_device_pre_reloc(parent, find_id->vendor,
+ find_id->device))
return log_msg_ret("notbr", -EPERM);
/* Bind a generic driver so that the device can be used */
@@ -1003,10 +1034,13 @@
for (i = 0; i < CONFIG_NR_DRAM_BANKS; ++i) {
if (bd->bi_dram[i].size) {
+ phys_addr_t start = bd->bi_dram[i].start;
+
+ if (IS_ENABLED(CONFIG_PCI_MAP_SYSTEM_MEMORY))
+ start = virt_to_phys((void *)(uintptr_t)bd->bi_dram[i].start);
+
pci_set_region(hose->regions + hose->region_count++,
- bd->bi_dram[i].start,
- bd->bi_dram[i].start,
- bd->bi_dram[i].size,
+ start, start, bd->bi_dram[i].size,
PCI_REGION_MEM | PCI_REGION_SYS_MEMORY);
}
}
diff --git a/drivers/pci/pci.c b/drivers/pci/pci.c
deleted file mode 100644
index d8f9239..0000000
--- a/drivers/pci/pci.c
+++ /dev/null
@@ -1,588 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * (C) Copyright 2001 Sysgo Real-Time Solutions, GmbH <www.elinos.com>
- * Andreas Heppel <aheppel@sysgo.de>
- *
- * (C) Copyright 2002, 2003
- * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
- */
-
-/*
- * Old PCI routines
- *
- * Do not change this file. Instead, convert your board to use CONFIG_DM_PCI
- * and change pci-uclass.c.
- */
-
-#include <common.h>
-#include <init.h>
-#include <log.h>
-#include <asm/global_data.h>
-#include <linux/delay.h>
-
-#include <command.h>
-#include <env.h>
-#include <errno.h>
-#include <asm/processor.h>
-#include <asm/io.h>
-#include <pci.h>
-
-DECLARE_GLOBAL_DATA_PTR;
-
-#define PCI_HOSE_OP(rw, size, type) \
-int pci_hose_##rw##_config_##size(struct pci_controller *hose, \
- pci_dev_t dev, \
- int offset, type value) \
-{ \
- return hose->rw##_##size(hose, dev, offset, value); \
-}
-
-PCI_HOSE_OP(read, byte, u8 *)
-PCI_HOSE_OP(read, word, u16 *)
-PCI_HOSE_OP(read, dword, u32 *)
-PCI_HOSE_OP(write, byte, u8)
-PCI_HOSE_OP(write, word, u16)
-PCI_HOSE_OP(write, dword, u32)
-
-#define PCI_OP(rw, size, type, error_code) \
-int pci_##rw##_config_##size(pci_dev_t dev, int offset, type value) \
-{ \
- struct pci_controller *hose = pci_bus_to_hose(PCI_BUS(dev)); \
- \
- if (!hose) \
- { \
- error_code; \
- return -1; \
- } \
- \
- return pci_hose_##rw##_config_##size(hose, dev, offset, value); \
-}
-
-PCI_OP(read, byte, u8 *, *value = 0xff)
-PCI_OP(read, word, u16 *, *value = 0xffff)
-PCI_OP(read, dword, u32 *, *value = 0xffffffff)
-PCI_OP(write, byte, u8, )
-PCI_OP(write, word, u16, )
-PCI_OP(write, dword, u32, )
-
-#define PCI_READ_VIA_DWORD_OP(size, type, off_mask) \
-int pci_hose_read_config_##size##_via_dword(struct pci_controller *hose,\
- pci_dev_t dev, \
- int offset, type val) \
-{ \
- u32 val32; \
- \
- if (pci_hose_read_config_dword(hose, dev, offset & 0xfc, &val32) < 0) { \
- *val = -1; \
- return -1; \
- } \
- \
- *val = (val32 >> ((offset & (int)off_mask) * 8)); \
- \
- return 0; \
-}
-
-#define PCI_WRITE_VIA_DWORD_OP(size, type, off_mask, val_mask) \
-int pci_hose_write_config_##size##_via_dword(struct pci_controller *hose,\
- pci_dev_t dev, \
- int offset, type val) \
-{ \
- u32 val32, mask, ldata, shift; \
- \
- if (pci_hose_read_config_dword(hose, dev, offset & 0xfc, &val32) < 0)\
- return -1; \
- \
- shift = ((offset & (int)off_mask) * 8); \
- ldata = (((unsigned long)val) & val_mask) << shift; \
- mask = val_mask << shift; \
- val32 = (val32 & ~mask) | ldata; \
- \
- if (pci_hose_write_config_dword(hose, dev, offset & 0xfc, val32) < 0)\
- return -1; \
- \
- return 0; \
-}
-
-PCI_READ_VIA_DWORD_OP(byte, u8 *, 0x03)
-PCI_READ_VIA_DWORD_OP(word, u16 *, 0x02)
-PCI_WRITE_VIA_DWORD_OP(byte, u8, 0x03, 0x000000ff)
-PCI_WRITE_VIA_DWORD_OP(word, u16, 0x02, 0x0000ffff)
-
-/*
- *
- */
-
-static struct pci_controller* hose_head;
-
-struct pci_controller *pci_get_hose_head(void)
-{
- if (gd->hose)
- return gd->hose;
-
- return hose_head;
-}
-
-void pci_register_hose(struct pci_controller* hose)
-{
- struct pci_controller **phose = &hose_head;
-
- while(*phose)
- phose = &(*phose)->next;
-
- hose->next = NULL;
-
- *phose = hose;
-}
-
-struct pci_controller *pci_bus_to_hose(int bus)
-{
- struct pci_controller *hose;
-
- for (hose = pci_get_hose_head(); hose; hose = hose->next) {
- if (bus >= hose->first_busno && bus <= hose->last_busno)
- return hose;
- }
-
- printf("pci_bus_to_hose() failed\n");
- return NULL;
-}
-
-struct pci_controller *find_hose_by_cfg_addr(void *cfg_addr)
-{
- struct pci_controller *hose;
-
- for (hose = pci_get_hose_head(); hose; hose = hose->next) {
- if (hose->cfg_addr == cfg_addr)
- return hose;
- }
-
- return NULL;
-}
-
-int pci_last_busno(void)
-{
- struct pci_controller *hose = pci_get_hose_head();
-
- if (!hose)
- return -1;
-
- while (hose->next)
- hose = hose->next;
-
- return hose->last_busno;
-}
-
-pci_dev_t pci_find_devices(struct pci_device_id *ids, int index)
-{
- struct pci_controller * hose;
- pci_dev_t bdf;
- int bus;
-
- for (hose = pci_get_hose_head(); hose; hose = hose->next) {
- for (bus = hose->first_busno; bus <= hose->last_busno; bus++) {
- bdf = pci_hose_find_devices(hose, bus, ids, &index);
- if (bdf != -1)
- return bdf;
- }
- }
-
- return -1;
-}
-
-static int pci_hose_config_device(struct pci_controller *hose, pci_dev_t dev,
- ulong io, pci_addr_t mem, ulong command)
-{
- u32 bar_response;
- unsigned int old_command;
- pci_addr_t bar_value;
- pci_size_t bar_size;
- unsigned char pin;
- int bar, found_mem64;
-
- debug("PCI Config: I/O=0x%lx, Memory=0x%llx, Command=0x%lx\n", io,
- (u64)mem, command);
-
- pci_hose_write_config_dword(hose, dev, PCI_COMMAND, 0);
-
- for (bar = PCI_BASE_ADDRESS_0; bar <= PCI_BASE_ADDRESS_5; bar += 4) {
- pci_hose_write_config_dword(hose, dev, bar, 0xffffffff);
- pci_hose_read_config_dword(hose, dev, bar, &bar_response);
-
- if (!bar_response)
- continue;
-
- found_mem64 = 0;
-
- /* Check the BAR type and set our address mask */
- if (bar_response & PCI_BASE_ADDRESS_SPACE) {
- bar_size = ~(bar_response & PCI_BASE_ADDRESS_IO_MASK) + 1;
- /* round up region base address to a multiple of size */
- io = ((io - 1) | (bar_size - 1)) + 1;
- bar_value = io;
- /* compute new region base address */
- io = io + bar_size;
- } else {
- if ((bar_response & PCI_BASE_ADDRESS_MEM_TYPE_MASK) ==
- PCI_BASE_ADDRESS_MEM_TYPE_64) {
- u32 bar_response_upper;
- u64 bar64;
- pci_hose_write_config_dword(hose, dev, bar + 4,
- 0xffffffff);
- pci_hose_read_config_dword(hose, dev, bar + 4,
- &bar_response_upper);
-
- bar64 = ((u64)bar_response_upper << 32) | bar_response;
-
- bar_size = ~(bar64 & PCI_BASE_ADDRESS_MEM_MASK) + 1;
- found_mem64 = 1;
- } else {
- bar_size = (u32)(~(bar_response & PCI_BASE_ADDRESS_MEM_MASK) + 1);
- }
-
- /* round up region base address to multiple of size */
- mem = ((mem - 1) | (bar_size - 1)) + 1;
- bar_value = mem;
- /* compute new region base address */
- mem = mem + bar_size;
- }
-
- /* Write it out and update our limit */
- pci_hose_write_config_dword (hose, dev, bar, (u32)bar_value);
-
- if (found_mem64) {
- bar += 4;
-#ifdef CONFIG_SYS_PCI_64BIT
- pci_hose_write_config_dword(hose, dev, bar,
- (u32)(bar_value >> 32));
-#else
- pci_hose_write_config_dword(hose, dev, bar, 0x00000000);
-#endif
- }
- }
-
- /* Configure Cache Line Size Register */
- pci_hose_write_config_byte(hose, dev, PCI_CACHE_LINE_SIZE, 0x08);
-
- /* Configure Latency Timer */
- pci_hose_write_config_byte(hose, dev, PCI_LATENCY_TIMER, 0x80);
-
- /* Disable interrupt line, if device says it wants to use interrupts */
- pci_hose_read_config_byte(hose, dev, PCI_INTERRUPT_PIN, &pin);
- if (pin != 0) {
- pci_hose_write_config_byte(hose, dev, PCI_INTERRUPT_LINE,
- PCI_INTERRUPT_LINE_DISABLE);
- }
-
- pci_hose_read_config_dword(hose, dev, PCI_COMMAND, &old_command);
- pci_hose_write_config_dword(hose, dev, PCI_COMMAND,
- (old_command & 0xffff0000) | command);
-
- return 0;
-}
-
-/*
- *
- */
-
-struct pci_config_table *pci_find_config(struct pci_controller *hose,
- unsigned short class,
- unsigned int vendor,
- unsigned int device,
- unsigned int bus,
- unsigned int dev,
- unsigned int func)
-{
- struct pci_config_table *table;
-
- for (table = hose->config_table; table && table->vendor; table++) {
- if ((table->vendor == PCI_ANY_ID || table->vendor == vendor) &&
- (table->device == PCI_ANY_ID || table->device == device) &&
- (table->class == PCI_ANY_ID || table->class == class) &&
- (table->bus == PCI_ANY_ID || table->bus == bus) &&
- (table->dev == PCI_ANY_ID || table->dev == dev) &&
- (table->func == PCI_ANY_ID || table->func == func)) {
- return table;
- }
- }
-
- return NULL;
-}
-
-void pci_cfgfunc_config_device(struct pci_controller *hose,
- pci_dev_t dev,
- struct pci_config_table *entry)
-{
- pci_hose_config_device(hose, dev, entry->priv[0], entry->priv[1],
- entry->priv[2]);
-}
-
-void pci_cfgfunc_do_nothing(struct pci_controller *hose,
- pci_dev_t dev, struct pci_config_table *entry)
-{
-}
-
-/*
- * HJF: Changed this to return int. I think this is required
- * to get the correct result when scanning bridges
- */
-extern int pciauto_config_device(struct pci_controller *hose, pci_dev_t dev);
-
-#ifdef CONFIG_PCI_SCAN_SHOW
-__weak int pci_print_dev(struct pci_controller *hose, pci_dev_t dev)
-{
- if (dev == PCI_BDF(hose->first_busno, 0, 0))
- return 0;
-
- return 1;
-}
-#endif /* CONFIG_PCI_SCAN_SHOW */
-
-int pci_hose_scan_bus(struct pci_controller *hose, int bus)
-{
- unsigned int sub_bus, found_multi = 0;
- unsigned short vendor, device, class;
- unsigned char header_type;
-#ifndef CONFIG_PCI_PNP
- struct pci_config_table *cfg;
-#endif
- pci_dev_t dev;
-#ifdef CONFIG_PCI_SCAN_SHOW
- static int indent = 0;
-#endif
-
- sub_bus = bus;
-
- for (dev = PCI_BDF(bus,0,0);
- dev < PCI_BDF(bus, PCI_MAX_PCI_DEVICES - 1,
- PCI_MAX_PCI_FUNCTIONS - 1);
- dev += PCI_BDF(0, 0, 1)) {
-
- if (pci_skip_dev(hose, dev))
- continue;
-
- if (PCI_FUNC(dev) && !found_multi)
- continue;
-
- pci_hose_read_config_byte(hose, dev, PCI_HEADER_TYPE, &header_type);
-
- pci_hose_read_config_word(hose, dev, PCI_VENDOR_ID, &vendor);
-
- if (vendor == 0xffff || vendor == 0x0000)
- continue;
-
- if (!PCI_FUNC(dev))
- found_multi = header_type & 0x80;
-
- debug("PCI Scan: Found Bus %d, Device %d, Function %d\n",
- PCI_BUS(dev), PCI_DEV(dev), PCI_FUNC(dev));
-
- pci_hose_read_config_word(hose, dev, PCI_DEVICE_ID, &device);
- pci_hose_read_config_word(hose, dev, PCI_CLASS_DEVICE, &class);
-
-#ifdef CONFIG_PCI_FIXUP_DEV
- board_pci_fixup_dev(hose, dev, vendor, device, class);
-#endif
-
-#ifdef CONFIG_PCI_SCAN_SHOW
- indent++;
-
- /* Print leading space, including bus indentation */
- printf("%*c", indent + 1, ' ');
-
- if (pci_print_dev(hose, dev)) {
- printf("%02x:%02x.%-*x - %04x:%04x - %s\n",
- PCI_BUS(dev), PCI_DEV(dev), 6 - indent, PCI_FUNC(dev),
- vendor, device, pci_class_str(class >> 8));
- }
-#endif
-
-#ifdef CONFIG_PCI_PNP
- sub_bus = max((unsigned int)pciauto_config_device(hose, dev),
- sub_bus);
-#else
- cfg = pci_find_config(hose, class, vendor, device,
- PCI_BUS(dev), PCI_DEV(dev), PCI_FUNC(dev));
- if (cfg) {
- cfg->config_device(hose, dev, cfg);
- sub_bus = max(sub_bus,
- (unsigned int)hose->current_busno);
- }
-#endif
-
-#ifdef CONFIG_PCI_SCAN_SHOW
- indent--;
-#endif
-
- if (hose->fixup_irq)
- hose->fixup_irq(hose, dev);
- }
-
- return sub_bus;
-}
-
-int pci_hose_scan(struct pci_controller *hose)
-{
-#if defined(CONFIG_PCI_BOOTDELAY)
- char *s;
- int i;
-
- if (!gd->pcidelay_done) {
- /* wait "pcidelay" ms (if defined)... */
- s = env_get("pcidelay");
- if (s) {
- int val = simple_strtoul(s, NULL, 10);
- for (i = 0; i < val; i++)
- udelay(1000);
- }
- gd->pcidelay_done = 1;
- }
-#endif /* CONFIG_PCI_BOOTDELAY */
-
-#ifdef CONFIG_PCI_SCAN_SHOW
- puts("PCI:\n");
-#endif
-
- /*
- * Start scan at current_busno.
- * PCIe will start scan at first_busno+1.
- */
- /* For legacy support, ensure current >= first */
- if (hose->first_busno > hose->current_busno)
- hose->current_busno = hose->first_busno;
-#ifdef CONFIG_PCI_PNP
- pciauto_config_init(hose);
-#endif
- return pci_hose_scan_bus(hose, hose->current_busno);
-}
-
-int pci_init(void)
-{
- hose_head = NULL;
-
- /* allow env to disable pci init/enum */
- if (env_get("pcidisable") != NULL)
- return 0;
-
- /* now call board specific pci_init()... */
- pci_init_board();
-
- return 0;
-}
-
-/* Returns the address of the requested capability structure within the
- * device's PCI configuration space or 0 in case the device does not
- * support it.
- * */
-int pci_hose_find_capability(struct pci_controller *hose, pci_dev_t dev,
- int cap)
-{
- int pos;
- u8 hdr_type;
-
- pci_hose_read_config_byte(hose, dev, PCI_HEADER_TYPE, &hdr_type);
-
- pos = pci_hose_find_cap_start(hose, dev, hdr_type & 0x7F);
-
- if (pos)
- pos = pci_find_cap(hose, dev, pos, cap);
-
- return pos;
-}
-
-/* Find the header pointer to the Capabilities*/
-int pci_hose_find_cap_start(struct pci_controller *hose, pci_dev_t dev,
- u8 hdr_type)
-{
- u16 status;
-
- pci_hose_read_config_word(hose, dev, PCI_STATUS, &status);
-
- if (!(status & PCI_STATUS_CAP_LIST))
- return 0;
-
- switch (hdr_type) {
- case PCI_HEADER_TYPE_NORMAL:
- case PCI_HEADER_TYPE_BRIDGE:
- return PCI_CAPABILITY_LIST;
- case PCI_HEADER_TYPE_CARDBUS:
- return PCI_CB_CAPABILITY_LIST;
- default:
- return 0;
- }
-}
-
-int pci_find_cap(struct pci_controller *hose, pci_dev_t dev, int pos, int cap)
-{
- int ttl = PCI_FIND_CAP_TTL;
- u8 id;
- u8 next_pos;
-
- while (ttl--) {
- pci_hose_read_config_byte(hose, dev, pos, &next_pos);
- if (next_pos < CAP_START_POS)
- break;
- next_pos &= ~3;
- pos = (int) next_pos;
- pci_hose_read_config_byte(hose, dev,
- pos + PCI_CAP_LIST_ID, &id);
- if (id == 0xff)
- break;
- if (id == cap)
- return pos;
- pos += PCI_CAP_LIST_NEXT;
- }
- return 0;
-}
-
-/**
- * pci_find_next_ext_capability - Find an extended capability
- *
- * Returns the address of the next matching extended capability structure
- * within the device's PCI configuration space or 0 if the device does
- * not support it. Some capabilities can occur several times, e.g., the
- * vendor-specific capability, and this provides a way to find them all.
- */
-int pci_find_next_ext_capability(struct pci_controller *hose, pci_dev_t dev,
- int start, int cap)
-{
- u32 header;
- int ttl, pos = PCI_CFG_SPACE_SIZE;
-
- /* minimum 8 bytes per capability */
- ttl = (PCI_CFG_SPACE_EXP_SIZE - PCI_CFG_SPACE_SIZE) / 8;
-
- if (start)
- pos = start;
-
- pci_hose_read_config_dword(hose, dev, pos, &header);
- if (header == 0xffffffff || header == 0)
- return 0;
-
- while (ttl-- > 0) {
- if (PCI_EXT_CAP_ID(header) == cap && pos != start)
- return pos;
-
- pos = PCI_EXT_CAP_NEXT(header);
- if (pos < PCI_CFG_SPACE_SIZE)
- break;
-
- pci_hose_read_config_dword(hose, dev, pos, &header);
- if (header == 0xffffffff || header == 0)
- break;
- }
-
- return 0;
-}
-
-/**
- * pci_hose_find_ext_capability - Find an extended capability
- *
- * Returns the address of the requested extended capability structure
- * within the device's PCI configuration space or 0 if the device does
- * not support it.
- */
-int pci_hose_find_ext_capability(struct pci_controller *hose, pci_dev_t dev,
- int cap)
-{
- return pci_find_next_ext_capability(hose, dev, 0, cap);
-}
diff --git a/drivers/pci/pci_auto_old.c b/drivers/pci/pci_auto_old.c
deleted file mode 100644
index c56ff53..0000000
--- a/drivers/pci/pci_auto_old.c
+++ /dev/null
@@ -1,387 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * PCI autoconfiguration library (legacy version, do not change)
- *
- * Author: Matt Porter <mporter@mvista.com>
- *
- * Copyright 2000 MontaVista Software Inc.
- */
-
-#include <common.h>
-#include <errno.h>
-#include <log.h>
-#include <pci.h>
-
-/*
- * Do not change this file. Instead, convert your board to use CONFIG_DM_PCI
- * and change pci_auto.c.
- */
-
-/* the user can define CONFIG_SYS_PCI_CACHE_LINE_SIZE to avoid problems */
-#ifndef CONFIG_SYS_PCI_CACHE_LINE_SIZE
-#define CONFIG_SYS_PCI_CACHE_LINE_SIZE 8
-#endif
-
-/*
- *
- */
-
-void pciauto_setup_device(struct pci_controller *hose,
- pci_dev_t dev, int bars_num,
- struct pci_region *mem,
- struct pci_region *prefetch,
- struct pci_region *io)
-{
- u32 bar_response;
- pci_size_t bar_size;
- u16 cmdstat = 0;
- int bar, bar_nr = 0;
- u8 header_type;
- int rom_addr;
- pci_addr_t bar_value;
- struct pci_region *bar_res;
- int found_mem64 = 0;
- u16 class;
-
- pci_hose_read_config_word(hose, dev, PCI_COMMAND, &cmdstat);
- cmdstat = (cmdstat & ~(PCI_COMMAND_IO | PCI_COMMAND_MEMORY)) | PCI_COMMAND_MASTER;
-
- for (bar = PCI_BASE_ADDRESS_0;
- bar < PCI_BASE_ADDRESS_0 + (bars_num * 4); bar += 4) {
- /* Tickle the BAR and get the response */
- pci_hose_write_config_dword(hose, dev, bar, 0xffffffff);
- pci_hose_read_config_dword(hose, dev, bar, &bar_response);
-
- /* If BAR is not implemented go to the next BAR */
- if (!bar_response)
- continue;
-
- found_mem64 = 0;
-
- /* Check the BAR type and set our address mask */
- if (bar_response & PCI_BASE_ADDRESS_SPACE) {
- bar_size = ((~(bar_response & PCI_BASE_ADDRESS_IO_MASK))
- & 0xffff) + 1;
- bar_res = io;
-
- debug("PCI Autoconfig: BAR %d, I/O, size=0x%llx, ",
- bar_nr, (unsigned long long)bar_size);
- } else {
- if ((bar_response & PCI_BASE_ADDRESS_MEM_TYPE_MASK) ==
- PCI_BASE_ADDRESS_MEM_TYPE_64) {
- u32 bar_response_upper;
- u64 bar64;
-
- pci_hose_write_config_dword(hose, dev, bar + 4,
- 0xffffffff);
- pci_hose_read_config_dword(hose, dev, bar + 4,
- &bar_response_upper);
-
- bar64 = ((u64)bar_response_upper << 32) | bar_response;
-
- bar_size = ~(bar64 & PCI_BASE_ADDRESS_MEM_MASK) + 1;
- found_mem64 = 1;
- } else {
- bar_size = (u32)(~(bar_response & PCI_BASE_ADDRESS_MEM_MASK) + 1);
- }
- if (prefetch && (bar_response & PCI_BASE_ADDRESS_MEM_PREFETCH))
- bar_res = prefetch;
- else
- bar_res = mem;
-
- debug("PCI Autoconfig: BAR %d, %s, size=0x%llx, ",
- bar_nr, bar_res == prefetch ? "Prf" : "Mem",
- (unsigned long long)bar_size);
- }
-
- if (pciauto_region_allocate(bar_res, bar_size,
- &bar_value, found_mem64) == 0) {
- /* Write it out and update our limit */
- pci_hose_write_config_dword(hose, dev, bar, (u32)bar_value);
-
- if (found_mem64) {
- bar += 4;
-#ifdef CONFIG_SYS_PCI_64BIT
- pci_hose_write_config_dword(hose, dev, bar, (u32)(bar_value>>32));
-#else
- /*
- * If we are a 64-bit decoder then increment to the
- * upper 32 bits of the bar and force it to locate
- * in the lower 4GB of memory.
- */
- pci_hose_write_config_dword(hose, dev, bar, 0x00000000);
-#endif
- }
-
- }
- cmdstat |= (bar_response & PCI_BASE_ADDRESS_SPACE) ?
- PCI_COMMAND_IO : PCI_COMMAND_MEMORY;
-
- debug("\n");
-
- bar_nr++;
- }
-
- /* Configure the expansion ROM address */
- pci_hose_read_config_byte(hose, dev, PCI_HEADER_TYPE, &header_type);
- header_type &= 0x7f;
- if (header_type != PCI_HEADER_TYPE_CARDBUS) {
- rom_addr = (header_type == PCI_HEADER_TYPE_NORMAL) ?
- PCI_ROM_ADDRESS : PCI_ROM_ADDRESS1;
- pci_hose_write_config_dword(hose, dev, rom_addr, 0xfffffffe);
- pci_hose_read_config_dword(hose, dev, rom_addr, &bar_response);
- if (bar_response) {
- bar_size = -(bar_response & ~1);
- debug("PCI Autoconfig: ROM, size=%#x, ",
- (unsigned int)bar_size);
- if (pciauto_region_allocate(mem, bar_size,
- &bar_value, false) == 0) {
- pci_hose_write_config_dword(hose, dev, rom_addr,
- bar_value);
- }
- cmdstat |= PCI_COMMAND_MEMORY;
- debug("\n");
- }
- }
-
- /* PCI_COMMAND_IO must be set for VGA device */
- pci_hose_read_config_word(hose, dev, PCI_CLASS_DEVICE, &class);
- if (class == PCI_CLASS_DISPLAY_VGA)
- cmdstat |= PCI_COMMAND_IO;
-
- pci_hose_write_config_word(hose, dev, PCI_COMMAND, cmdstat);
- pci_hose_write_config_byte(hose, dev, PCI_CACHE_LINE_SIZE,
- CONFIG_SYS_PCI_CACHE_LINE_SIZE);
- pci_hose_write_config_byte(hose, dev, PCI_LATENCY_TIMER, 0x80);
-}
-
-void pciauto_prescan_setup_bridge(struct pci_controller *hose,
- pci_dev_t dev, int sub_bus)
-{
- struct pci_region *pci_mem;
- struct pci_region *pci_prefetch;
- struct pci_region *pci_io;
- u16 cmdstat, prefechable_64;
-
- pci_mem = hose->pci_mem;
- pci_prefetch = hose->pci_prefetch;
- pci_io = hose->pci_io;
-
- pci_hose_read_config_word(hose, dev, PCI_COMMAND, &cmdstat);
- pci_hose_read_config_word(hose, dev, PCI_PREF_MEMORY_BASE,
- &prefechable_64);
- prefechable_64 &= PCI_PREF_RANGE_TYPE_MASK;
-
- /* Configure bus number registers */
- pci_hose_write_config_byte(hose, dev, PCI_PRIMARY_BUS,
- PCI_BUS(dev) - hose->first_busno);
- pci_hose_write_config_byte(hose, dev, PCI_SECONDARY_BUS,
- sub_bus - hose->first_busno);
- pci_hose_write_config_byte(hose, dev, PCI_SUBORDINATE_BUS, 0xff);
-
- if (pci_mem) {
- /* Round memory allocator to 1MB boundary */
- pciauto_region_align(pci_mem, 0x100000);
-
- /* Set up memory and I/O filter limits, assume 32-bit I/O space */
- pci_hose_write_config_word(hose, dev, PCI_MEMORY_BASE,
- (pci_mem->bus_lower & 0xfff00000) >> 16);
-
- cmdstat |= PCI_COMMAND_MEMORY;
- }
-
- if (pci_prefetch) {
- /* Round memory allocator to 1MB boundary */
- pciauto_region_align(pci_prefetch, 0x100000);
-
- /* Set up memory and I/O filter limits, assume 32-bit I/O space */
- pci_hose_write_config_word(hose, dev, PCI_PREF_MEMORY_BASE,
- (pci_prefetch->bus_lower & 0xfff00000) >> 16);
- if (prefechable_64 == PCI_PREF_RANGE_TYPE_64)
-#ifdef CONFIG_SYS_PCI_64BIT
- pci_hose_write_config_dword(hose, dev,
- PCI_PREF_BASE_UPPER32,
- pci_prefetch->bus_lower >> 32);
-#else
- pci_hose_write_config_dword(hose, dev,
- PCI_PREF_BASE_UPPER32,
- 0x0);
-#endif
-
- cmdstat |= PCI_COMMAND_MEMORY;
- } else {
- /* We don't support prefetchable memory for now, so disable */
- pci_hose_write_config_word(hose, dev, PCI_PREF_MEMORY_BASE, 0x1000);
- pci_hose_write_config_word(hose, dev, PCI_PREF_MEMORY_LIMIT, 0x0);
- if (prefechable_64 == PCI_PREF_RANGE_TYPE_64) {
- pci_hose_write_config_word(hose, dev, PCI_PREF_BASE_UPPER32, 0x0);
- pci_hose_write_config_word(hose, dev, PCI_PREF_LIMIT_UPPER32, 0x0);
- }
- }
-
- if (pci_io) {
- /* Round I/O allocator to 4KB boundary */
- pciauto_region_align(pci_io, 0x1000);
-
- pci_hose_write_config_byte(hose, dev, PCI_IO_BASE,
- (pci_io->bus_lower & 0x0000f000) >> 8);
- pci_hose_write_config_word(hose, dev, PCI_IO_BASE_UPPER16,
- (pci_io->bus_lower & 0xffff0000) >> 16);
-
- cmdstat |= PCI_COMMAND_IO;
- }
-
- /* Enable memory and I/O accesses, enable bus master */
- pci_hose_write_config_word(hose, dev, PCI_COMMAND,
- cmdstat | PCI_COMMAND_MASTER);
-}
-
-void pciauto_postscan_setup_bridge(struct pci_controller *hose,
- pci_dev_t dev, int sub_bus)
-{
- struct pci_region *pci_mem;
- struct pci_region *pci_prefetch;
- struct pci_region *pci_io;
-
- pci_mem = hose->pci_mem;
- pci_prefetch = hose->pci_prefetch;
- pci_io = hose->pci_io;
-
- /* Configure bus number registers */
- pci_hose_write_config_byte(hose, dev, PCI_SUBORDINATE_BUS,
- sub_bus - hose->first_busno);
-
- if (pci_mem) {
- /* Round memory allocator to 1MB boundary */
- pciauto_region_align(pci_mem, 0x100000);
-
- pci_hose_write_config_word(hose, dev, PCI_MEMORY_LIMIT,
- (pci_mem->bus_lower - 1) >> 16);
- }
-
- if (pci_prefetch) {
- u16 prefechable_64;
-
- pci_hose_read_config_word(hose, dev,
- PCI_PREF_MEMORY_LIMIT,
- &prefechable_64);
- prefechable_64 &= PCI_PREF_RANGE_TYPE_MASK;
-
- /* Round memory allocator to 1MB boundary */
- pciauto_region_align(pci_prefetch, 0x100000);
-
- pci_hose_write_config_word(hose, dev, PCI_PREF_MEMORY_LIMIT,
- (pci_prefetch->bus_lower - 1) >> 16);
- if (prefechable_64 == PCI_PREF_RANGE_TYPE_64)
-#ifdef CONFIG_SYS_PCI_64BIT
- pci_hose_write_config_dword(hose, dev,
- PCI_PREF_LIMIT_UPPER32,
- (pci_prefetch->bus_lower - 1) >> 32);
-#else
- pci_hose_write_config_dword(hose, dev,
- PCI_PREF_LIMIT_UPPER32,
- 0x0);
-#endif
- }
-
- if (pci_io) {
- /* Round I/O allocator to 4KB boundary */
- pciauto_region_align(pci_io, 0x1000);
-
- pci_hose_write_config_byte(hose, dev, PCI_IO_LIMIT,
- ((pci_io->bus_lower - 1) & 0x0000f000) >> 8);
- pci_hose_write_config_word(hose, dev, PCI_IO_LIMIT_UPPER16,
- ((pci_io->bus_lower - 1) & 0xffff0000) >> 16);
- }
-}
-
-
-/*
- * HJF: Changed this to return int. I think this is required
- * to get the correct result when scanning bridges
- */
-int pciauto_config_device(struct pci_controller *hose, pci_dev_t dev)
-{
- struct pci_region *pci_mem;
- struct pci_region *pci_prefetch;
- struct pci_region *pci_io;
- unsigned int sub_bus = PCI_BUS(dev);
- unsigned short class;
- int n;
-
- pci_mem = hose->pci_mem;
- pci_prefetch = hose->pci_prefetch;
- pci_io = hose->pci_io;
-
- pci_hose_read_config_word(hose, dev, PCI_CLASS_DEVICE, &class);
-
- switch (class) {
- case PCI_CLASS_BRIDGE_PCI:
- debug("PCI Autoconfig: Found P2P bridge, device %d\n",
- PCI_DEV(dev));
-
- pciauto_setup_device(hose, dev, 2, pci_mem,
- pci_prefetch, pci_io);
-
- /* Passing in current_busno allows for sibling P2P bridges */
- hose->current_busno++;
- pciauto_prescan_setup_bridge(hose, dev, hose->current_busno);
- /*
- * need to figure out if this is a subordinate bridge on the bus
- * to be able to properly set the pri/sec/sub bridge registers.
- */
- n = pci_hose_scan_bus(hose, hose->current_busno);
-
- /* figure out the deepest we've gone for this leg */
- sub_bus = max((unsigned int)n, sub_bus);
- pciauto_postscan_setup_bridge(hose, dev, sub_bus);
-
- sub_bus = hose->current_busno;
- break;
-
- case PCI_CLASS_BRIDGE_CARDBUS:
- /*
- * just do a minimal setup of the bridge,
- * let the OS take care of the rest
- */
- pciauto_setup_device(hose, dev, 0, pci_mem,
- pci_prefetch, pci_io);
-
- debug("PCI Autoconfig: Found P2CardBus bridge, device %d\n",
- PCI_DEV(dev));
-
- hose->current_busno++;
- break;
-
-#if defined(CONFIG_PCIAUTO_SKIP_HOST_BRIDGE)
- case PCI_CLASS_BRIDGE_OTHER:
- debug("PCI Autoconfig: Skipping bridge device %d\n",
- PCI_DEV(dev));
- break;
-#endif
-#if defined(CONFIG_ARCH_MPC834X) && !defined(CONFIG_TARGET_VME8349) && \
- !defined(CONFIG_TARGET_CADDY2)
- case PCI_CLASS_BRIDGE_OTHER:
- /*
- * The host/PCI bridge 1 seems broken in 8349 - it presents
- * itself as 'PCI_CLASS_BRIDGE_OTHER' and appears as an _agent_
- * device claiming resources io/mem/irq.. we only allow for
- * the PIMMR window to be allocated (BAR0 - 1MB size)
- */
- debug("PCI Autoconfig: Broken bridge found, only minimal config\n");
- pciauto_setup_device(hose, dev, 0, hose->pci_mem,
- hose->pci_prefetch, hose->pci_io);
- break;
-#endif
-
- case PCI_CLASS_PROCESSOR_POWERPC: /* an agent or end-point */
- debug("PCI AutoConfig: Found PowerPC device\n");
-
- default:
- pciauto_setup_device(hose, dev, 6, pci_mem,
- pci_prefetch, pci_io);
- break;
- }
-
- return sub_bus;
-}
diff --git a/drivers/pci/pci_gt64120.c b/drivers/pci/pci_gt64120.c
index 80f11fe..e57fedf 100644
--- a/drivers/pci/pci_gt64120.c
+++ b/drivers/pci/pci_gt64120.c
@@ -8,7 +8,7 @@
* Maciej W. Rozycki <macro@mips.com>
*/
-#include <common.h>
+#include <dm.h>
#include <gt64120.h>
#include <init.h>
#include <log.h>
@@ -114,6 +114,7 @@
return 0;
}
+#if !IS_ENABLED(CONFIG_DM_PCI)
static int gt_read_config_dword(struct pci_controller *hose, pci_dev_t dev,
int where, u32 *value)
{
@@ -175,3 +176,74 @@
pci_register_hose(hose);
hose->last_busno = pci_hose_scan(hose);
}
+#else
+static int gt64120_pci_read_config(const struct udevice *dev, pci_dev_t bdf,
+ uint where, ulong *val,
+ enum pci_size_t size)
+{
+ struct gt64120_pci_controller *gt = dev_get_priv(dev);
+ u32 data = 0;
+
+ if (gt_config_access(gt, PCI_ACCESS_READ, bdf, where, &data)) {
+ *val = pci_get_ff(size);
+ return 0;
+ }
+
+ *val = pci_conv_32_to_size(data, where, size);
+
+ return 0;
+}
+
+static int gt64120_pci_write_config(struct udevice *dev, pci_dev_t bdf,
+ uint where, ulong val,
+ enum pci_size_t size)
+{
+ struct gt64120_pci_controller *gt = dev_get_priv(dev);
+ u32 data = 0;
+
+ if (size == PCI_SIZE_32) {
+ data = val;
+ } else {
+ u32 old;
+
+ if (gt_config_access(gt, PCI_ACCESS_READ, bdf, where, &old))
+ return 0;
+
+ data = pci_conv_size_to_32(old, val, where, size);
+ }
+
+ gt_config_access(gt, PCI_ACCESS_WRITE, bdf, where, &data);
+
+ return 0;
+}
+
+static int gt64120_pci_probe(struct udevice *dev)
+{
+ struct gt64120_pci_controller *gt = dev_get_priv(dev);
+
+ gt->regs = dev_remap_addr(dev);
+ if (!gt->regs)
+ return -EINVAL;
+
+ return 0;
+}
+
+static const struct dm_pci_ops gt64120_pci_ops = {
+ .read_config = gt64120_pci_read_config,
+ .write_config = gt64120_pci_write_config,
+};
+
+static const struct udevice_id gt64120_pci_ids[] = {
+ { .compatible = "marvell,pci-gt64120" },
+ { }
+};
+
+U_BOOT_DRIVER(gt64120_pci) = {
+ .name = "gt64120_pci",
+ .id = UCLASS_PCI,
+ .of_match = gt64120_pci_ids,
+ .ops = >64120_pci_ops,
+ .probe = gt64120_pci_probe,
+ .priv_auto = sizeof(struct gt64120_pci_controller),
+};
+#endif
diff --git a/drivers/pci/pci_msc01.c b/drivers/pci/pci_msc01.c
index 0483820..c17da47 100644
--- a/drivers/pci/pci_msc01.c
+++ b/drivers/pci/pci_msc01.c
@@ -4,7 +4,7 @@
* Author: Paul Burton <paul.burton@mips.com>
*/
-#include <common.h>
+#include <dm.h>
#include <init.h>
#include <msc01.h>
#include <pci.h>
@@ -62,6 +62,7 @@
return 0;
}
+#if !IS_ENABLED(CONFIG_DM_PCI)
static int msc01_read_config_dword(struct pci_controller *hose, pci_dev_t dev,
int where, u32 *value)
{
@@ -123,3 +124,72 @@
pci_register_hose(hose);
hose->last_busno = pci_hose_scan(hose);
}
+#else
+static int msc01_pci_read_config(const struct udevice *dev, pci_dev_t bdf,
+ uint where, ulong *val, enum pci_size_t size)
+{
+ struct msc01_pci_controller *msc01 = dev_get_priv(dev);
+ u32 data = 0;
+
+ if (msc01_config_access(msc01, PCI_ACCESS_READ, bdf, where, &data)) {
+ *val = pci_get_ff(size);
+ return 0;
+ }
+
+ *val = pci_conv_32_to_size(data, where, size);
+
+ return 0;
+}
+
+static int msc01_pci_write_config(struct udevice *dev, pci_dev_t bdf,
+ uint where, ulong val, enum pci_size_t size)
+{
+ struct msc01_pci_controller *msc01 = dev_get_priv(dev);
+ u32 data = 0;
+
+ if (size == PCI_SIZE_32) {
+ data = val;
+ } else {
+ u32 old;
+
+ if (msc01_config_access(msc01, PCI_ACCESS_READ, bdf, where, &old))
+ return 0;
+
+ data = pci_conv_size_to_32(old, val, where, size);
+ }
+
+ msc01_config_access(msc01, PCI_ACCESS_WRITE, bdf, where, &data);
+
+ return 0;
+}
+
+static int msc01_pci_probe(struct udevice *dev)
+{
+ struct msc01_pci_controller *msc01 = dev_get_priv(dev);
+
+ msc01->base = dev_remap_addr(dev);
+ if (!msc01->base)
+ return -EINVAL;
+
+ return 0;
+}
+
+static const struct dm_pci_ops msc01_pci_ops = {
+ .read_config = msc01_pci_read_config,
+ .write_config = msc01_pci_write_config,
+};
+
+static const struct udevice_id msc01_pci_ids[] = {
+ { .compatible = "mips,pci-msc01" },
+ { }
+};
+
+U_BOOT_DRIVER(msc01_pci) = {
+ .name = "msc01_pci",
+ .id = UCLASS_PCI,
+ .of_match = msc01_pci_ids,
+ .ops = &msc01_pci_ops,
+ .probe = msc01_pci_probe,
+ .priv_auto = sizeof(struct msc01_pci_controller),
+};
+#endif
diff --git a/drivers/pci/pcie_imx.c b/drivers/pci/pcie_imx.c
index 73875e0..7b46fdb 100644
--- a/drivers/pci/pcie_imx.c
+++ b/drivers/pci/pcie_imx.c
@@ -100,6 +100,8 @@
struct imx_pcie_priv {
void __iomem *dbi_base;
void __iomem *cfg_base;
+ struct gpio_desc reset_gpio;
+ bool reset_active_high;
};
/*
@@ -541,7 +543,7 @@
return 0;
}
-__weak int imx6_pcie_toggle_reset(void)
+__weak int imx6_pcie_toggle_reset(struct gpio_desc *gpio, bool active_high)
{
/*
* See 'PCI EXPRESS BASE SPECIFICATION, REV 3.0, SECTION 6.6.1'
@@ -579,12 +581,20 @@
mdelay(20);
gpio_free(CONFIG_PCIE_IMX_PERST_GPIO);
#else
- puts("WARNING: Make sure the PCIe #PERST line is connected!\n");
+ if (dm_gpio_is_valid(gpio)) {
+ /* Assert PERST# for 20ms then de-assert */
+ dm_gpio_set_value(gpio, active_high ? 0 : 1);
+ mdelay(20);
+ dm_gpio_set_value(gpio, active_high ? 1 : 0);
+ mdelay(20);
+ } else {
+ puts("WARNING: Make sure the PCIe #PERST line is connected!\n");
+ }
#endif
return 0;
}
-static int imx6_pcie_deassert_core_reset(void)
+static int imx6_pcie_deassert_core_reset(struct imx_pcie_priv *priv)
{
struct iomuxc *iomuxc_regs = (struct iomuxc *)IOMUXC_BASE_ADDR;
@@ -612,7 +622,7 @@
setbits_le32(&iomuxc_regs->gpr[1], IOMUXC_GPR1_REF_SSP_EN);
#endif
- imx6_pcie_toggle_reset();
+ imx6_pcie_toggle_reset(&priv->reset_gpio, priv->reset_active_high);
return 0;
}
@@ -625,7 +635,7 @@
imx6_pcie_assert_core_reset(priv, false);
imx6_pcie_init_phy();
- imx6_pcie_deassert_core_reset();
+ imx6_pcie_deassert_core_reset(priv);
imx_pcie_regions_setup(priv);
@@ -787,6 +797,15 @@
{
struct imx_pcie_priv *priv = dev_get_priv(dev);
+ /* if PERST# valid from dt then assert it */
+ gpio_request_by_name(dev, "reset-gpio", 0, &priv->reset_gpio,
+ GPIOD_IS_OUT);
+ priv->reset_active_high = dev_read_bool(dev, "reset-gpio-active-high");
+ if (dm_gpio_is_valid(&priv->reset_gpio)) {
+ dm_gpio_set_value(&priv->reset_gpio,
+ priv->reset_active_high ? 0 : 1);
+ }
+
return imx_pcie_link_up(priv);
}
diff --git a/drivers/phy/Kconfig b/drivers/phy/Kconfig
index 92c74b9..80ae1af 100644
--- a/drivers/phy/Kconfig
+++ b/drivers/phy/Kconfig
@@ -274,5 +274,12 @@
multi-ports is first version, otherwise is second veriosn,
so you can easily distinguish them by banks layout.
+config PHY_IMX8MQ_USB
+ bool "NXP i.MX8MQ USB PHY Driver"
+ depends on PHY
+ depends on IMX8MQ
+ help
+ Support the USB3.0 PHY in NXP i.MX8MQ SoC
+
source "drivers/phy/rockchip/Kconfig"
endmenu
diff --git a/drivers/phy/Makefile b/drivers/phy/Makefile
index bf03d05..0f2b63a 100644
--- a/drivers/phy/Makefile
+++ b/drivers/phy/Makefile
@@ -32,3 +32,4 @@
obj-$(CONFIG_MT76X8_USB_PHY) += mt76x8-usb-phy.o
obj-$(CONFIG_PHY_DA8XX_USB) += phy-da8xx-usb.o
obj-$(CONFIG_PHY_MTK_TPHY) += phy-mtk-tphy.o
+obj-$(CONFIG_PHY_IMX8MQ_USB) += phy-imx8mq-usb.o
diff --git a/drivers/phy/phy-imx8mq-usb.c b/drivers/phy/phy-imx8mq-usb.c
new file mode 100644
index 0000000..afbc7ad
--- /dev/null
+++ b/drivers/phy/phy-imx8mq-usb.c
@@ -0,0 +1,197 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright 2021 NXP
+ *
+ */
+
+#include <common.h>
+#include <asm/io.h>
+#include <dm.h>
+#include <errno.h>
+#include <generic-phy.h>
+#include <linux/bitops.h>
+#include <linux/err.h>
+#include <clk.h>
+
+#define PHY_CTRL0 0x0
+#define PHY_CTRL0_REF_SSP_EN BIT(2)
+#define PHY_CTRL0_FSEL_MASK GENMASK(10, 5)
+#define PHY_CTRL0_FSEL_24M 0x2a
+#define PHY_CTRL0_FSEL_100M 0x27
+#define PHY_CTRL0_SSC_RANGE_MASK GENMASK(23, 21)
+#define PHY_CTRL0_SSC_RANGE_4003PPM (0x2 << 21)
+
+#define PHY_CTRL1 0x4
+#define PHY_CTRL1_RESET BIT(0)
+#define PHY_CTRL1_COMMONONN BIT(1)
+#define PHY_CTRL1_ATERESET BIT(3)
+#define PHY_CTRL1_DCDENB BIT(17)
+#define PHY_CTRL1_CHRGSEL BIT(18)
+#define PHY_CTRL1_VDATSRCENB0 BIT(19)
+#define PHY_CTRL1_VDATDETENB0 BIT(20)
+
+#define PHY_CTRL2 0x8
+#define PHY_CTRL2_TXENABLEN0 BIT(8)
+#define PHY_CTRL2_OTG_DISABLE BIT(9)
+
+#define PHY_CTRL3 0xc
+#define PHY_CTRL3_COMPDISTUNE_MASK GENMASK(2, 0)
+#define PHY_CTRL3_TXPREEMP_TUNE_MASK GENMASK(16, 15)
+#define PHY_CTRL3_TXPREEMP_TUNE_SHIFT 15
+#define PHY_CTRL3_TXRISE_TUNE_MASK GENMASK(21, 20)
+#define PHY_CTRL3_TXRISE_TUNE_SHIFT 20
+/* 1111: +24% ... 0000: -6% step: 2% */
+#define PHY_CTRL3_TXVREF_TUNE_MASK GENMASK(25, 22)
+#define PHY_CTRL3_TXVREF_TUNE_SHIFT 22
+#define PHY_CTRL3_TX_VBOOST_LEVEL_MASK GENMASK(31, 29)
+#define PHY_CTRL3_TX_VBOOST_LEVEL_SHIFT 29
+
+#define PHY_CTRL4 0x10
+#define PHY_CTRL4_PCS_TX_DEEMPH_3P5DB_MASK GENMASK(20, 15)
+#define PHY_CTRL4_PCS_TX_DEEMPH_3P5DB_SHIFT 15
+
+#define PHY_CTRL5 0x14
+#define PHY_CTRL5_DMPWD_OVERRIDE_SEL BIT(23)
+#define PHY_CTRL5_DMPWD_OVERRIDE BIT(22)
+#define PHY_CTRL5_DPPWD_OVERRIDE_SEL BIT(21)
+#define PHY_CTRL5_DPPWD_OVERRIDE BIT(20)
+#define PHY_CTRL5_PCS_TX_SWING_FULL_MASK GENMASK(6, 0)
+
+#define PHY_CTRL6 0x18
+#define PHY_CTRL6_RXTERM_OVERRIDE_SEL BIT(29)
+#define PHY_CTRL6_ALT_CLK_EN BIT(1)
+#define PHY_CTRL6_ALT_CLK_SEL BIT(0)
+
+#define PHY_STS0 0x40
+#define PHY_STS0_OTGSESSVLD BIT(7)
+#define PHY_STS0_CHGDET BIT(4)
+#define PHY_STS0_FSVPLUS BIT(3)
+#define PHY_STS0_FSVMINUS BIT(2)
+
+struct imx8mq_usb_phy {
+#if CONFIG_IS_ENABLED(CLK)
+ struct clk phy_clk;
+#endif
+ void __iomem *base;
+};
+
+static const struct udevice_id imx8mq_usb_phy_of_match[] = {
+ {
+ .compatible = "fsl,imx8mq-usb-phy",
+ },
+ {},
+};
+
+static int imx8mq_usb_phy_init(struct phy *usb_phy)
+{
+ struct udevice *dev = usb_phy->dev;
+ struct imx8mq_usb_phy *imx_phy = dev_get_priv(dev);
+ u32 value;
+
+ value = readl(imx_phy->base + PHY_CTRL1);
+ value &= ~(PHY_CTRL1_VDATSRCENB0 | PHY_CTRL1_VDATDETENB0 |
+ PHY_CTRL1_COMMONONN);
+ value |= PHY_CTRL1_RESET | PHY_CTRL1_ATERESET;
+ writel(value, imx_phy->base + PHY_CTRL1);
+
+ value = readl(imx_phy->base + PHY_CTRL0);
+ value |= PHY_CTRL0_REF_SSP_EN;
+ value &= ~PHY_CTRL0_SSC_RANGE_MASK;
+ value |= PHY_CTRL0_SSC_RANGE_4003PPM;
+ writel(value, imx_phy->base + PHY_CTRL0);
+
+ value = readl(imx_phy->base + PHY_CTRL2);
+ value |= PHY_CTRL2_TXENABLEN0;
+ writel(value, imx_phy->base + PHY_CTRL2);
+
+ value = readl(imx_phy->base + PHY_CTRL1);
+ value &= ~(PHY_CTRL1_RESET | PHY_CTRL1_ATERESET);
+ writel(value, imx_phy->base + PHY_CTRL1);
+
+ return 0;
+}
+
+static int imx8mq_usb_phy_power_on(struct phy *usb_phy)
+{
+ struct udevice *dev = usb_phy->dev;
+ struct imx8mq_usb_phy *imx_phy = dev_get_priv(dev);
+ u32 value;
+
+#if CONFIG_IS_ENABLED(CLK)
+ int ret;
+ ret = clk_enable(&imx_phy->phy_clk);
+ if (ret) {
+ printf("Failed to enable usb phy clock\n");
+ return ret;
+ }
+#endif
+
+ /* Disable rx term override */
+ value = readl(imx_phy->base + PHY_CTRL6);
+ value &= ~PHY_CTRL6_RXTERM_OVERRIDE_SEL;
+ writel(value, imx_phy->base + PHY_CTRL6);
+
+ return 0;
+}
+
+static int imx8mq_usb_phy_power_off(struct phy *usb_phy)
+{
+ struct udevice *dev = usb_phy->dev;
+ struct imx8mq_usb_phy *imx_phy = dev_get_priv(dev);
+ u32 value;
+
+ /* Override rx term to be 0 */
+ value = readl(imx_phy->base + PHY_CTRL6);
+ value |= PHY_CTRL6_RXTERM_OVERRIDE_SEL;
+ writel(value, imx_phy->base + PHY_CTRL6);
+
+#if CONFIG_IS_ENABLED(CLK)
+ clk_disable(&imx_phy->phy_clk);
+#endif
+
+ return 0;
+}
+
+static int imx8mq_usb_phy_exit(struct phy *usb_phy)
+{
+ return imx8mq_usb_phy_power_off(usb_phy);
+}
+
+struct phy_ops imx8mq_usb_phy_ops = {
+ .init = imx8mq_usb_phy_init,
+ .power_on = imx8mq_usb_phy_power_on,
+ .power_off = imx8mq_usb_phy_power_off,
+ .exit = imx8mq_usb_phy_exit,
+};
+
+int imx8mq_usb_phy_probe(struct udevice *dev)
+{
+ struct imx8mq_usb_phy *priv = dev_get_priv(dev);
+
+ priv->base = dev_read_addr_ptr(dev);
+
+ if (!priv->base)
+ return -EINVAL;
+
+#if CONFIG_IS_ENABLED(CLK)
+ int ret;
+
+ /* Assigned clock already set clock */
+ ret = clk_get_by_name(dev, "phy", &priv->phy_clk);
+ if (ret) {
+ printf("Failed to get usb phy clock\n");
+ return ret;
+ }
+#endif
+
+ return 0;
+}
+
+U_BOOT_DRIVER(nxp_imx8mq_usb_phy) = {
+ .name = "nxp_imx8mq_usb_phy",
+ .id = UCLASS_PHY,
+ .of_match = imx8mq_usb_phy_of_match,
+ .probe = imx8mq_usb_phy_probe,
+ .ops = &imx8mq_usb_phy_ops,
+ .priv_auto = sizeof(struct imx8mq_usb_phy),
+};
diff --git a/drivers/pinctrl/pinctrl-single.c b/drivers/pinctrl/pinctrl-single.c
index 7af6c5f..cf9ad36 100644
--- a/drivers/pinctrl/pinctrl-single.c
+++ b/drivers/pinctrl/pinctrl-single.c
@@ -471,6 +471,7 @@
return -ENOMEM;
#endif
+ /* looks like a possible divide by 0, but data->width avoids this */
priv->npins = size / (pdata->width / BITS_PER_BYTE);
if (pdata->bits_per_mux) {
if (!pdata->mask) {
diff --git a/drivers/reset/reset-uclass.c b/drivers/reset/reset-uclass.c
index 8caa616..c09c009 100644
--- a/drivers/reset/reset-uclass.c
+++ b/drivers/reset/reset-uclass.c
@@ -325,6 +325,8 @@
bulk = devres_alloc(devm_reset_bulk_release,
sizeof(struct reset_ctl_bulk),
__GFP_ZERO);
+
+ /* this looks like a leak, but devres takes care of it */
if (unlikely(!bulk))
return ERR_PTR(-ENOMEM);
diff --git a/drivers/rtc/m41t62.c b/drivers/rtc/m41t62.c
index 0a4e12d..8be532c 100644
--- a/drivers/rtc/m41t62.c
+++ b/drivers/rtc/m41t62.c
@@ -213,13 +213,13 @@
/* 1. Set stop bit */
val |= M41T62_SEC_ST;
- ret = dm_i2c_write(dev, M41T62_REG_ALARM_HOUR, &val, sizeof(val));
+ ret = dm_i2c_write(dev, M41T62_REG_SEC, &val, sizeof(val));
if (ret)
return ret;
/* 2. Clear stop bit */
val &= ~M41T62_SEC_ST;
- ret = dm_i2c_write(dev, M41T62_REG_ALARM_HOUR, &val, sizeof(val));
+ ret = dm_i2c_write(dev, M41T62_REG_SEC, &val, sizeof(val));
if (ret)
return ret;
diff --git a/drivers/serial/Kconfig b/drivers/serial/Kconfig
index 961e3fb..93348c0 100644
--- a/drivers/serial/Kconfig
+++ b/drivers/serial/Kconfig
@@ -443,6 +443,7 @@
int "UART input clock"
depends on DEBUG_UART
default 0 if DEBUG_UART_SANDBOX
+ default 0 if DEBUG_MVEBU_A3700_UART
help
The UART input clock determines the speed of the internal UART
circuitry. The baud rate is derived from this by dividing the input
diff --git a/drivers/spi/Makefile b/drivers/spi/Makefile
index f70851e..216e72c 100644
--- a/drivers/spi/Makefile
+++ b/drivers/spi/Makefile
@@ -11,6 +11,7 @@
obj-$(CONFIG_SOFT_SPI) += soft_spi.o
obj-$(CONFIG_SPI_MEM) += spi-mem.o
obj-$(CONFIG_TI_QSPI) += ti_qspi.o
+obj-$(CONFIG_FSL_QSPI) += fsl_qspi.o
else
obj-y += spi.o
obj-$(CONFIG_SPI_MEM) += spi-mem-nodm.o
@@ -30,7 +31,6 @@
obj-$(CONFIG_EXYNOS_SPI) += exynos_spi.o
obj-$(CONFIG_FSL_DSPI) += fsl_dspi.o
obj-$(CONFIG_FSL_ESPI) += fsl_espi.o
-obj-$(CONFIG_FSL_QSPI) += fsl_qspi.o
obj-$(CONFIG_SYNQUACER_SPI) += spi-synquacer.o
obj-$(CONFIG_ICH_SPI) += ich.o
obj-$(CONFIG_KIRKWOOD_SPI) += kirkwood_spi.o
diff --git a/drivers/spi/ich.c b/drivers/spi/ich.c
index 1cd4104..3d49c22 100644
--- a/drivers/spi/ich.c
+++ b/drivers/spi/ich.c
@@ -114,7 +114,7 @@
struct ich_spi_priv *priv = dev_get_priv(dev);
u32 fdod, speed;
- if (!CONFIG_IS_ENABLED(PCI))
+ if (!CONFIG_IS_ENABLED(PCI) || !priv->pch)
return false;
/* Observe SPI Descriptor Component Section 0 */
dm_pci_write_config32(priv->pch, 0xb0, 0x1000);
@@ -632,7 +632,7 @@
if (device_get_uclass_id(pch) != UCLASS_PCH) {
uclass_first_device(UCLASS_PCH, &pch);
if (!pch)
- return log_msg_ret("uclass", -EPROTOTYPE);
+ ; /* ignore this error since we don't need it */
}
}
diff --git a/drivers/spi/mxc_spi.c b/drivers/spi/mxc_spi.c
index f3dddbd..a80c3e7 100644
--- a/drivers/spi/mxc_spi.c
+++ b/drivers/spi/mxc_spi.c
@@ -591,8 +591,6 @@
static int mxc_spi_probe(struct udevice *bus)
{
struct mxc_spi_slave *mxcs = dev_get_plat(bus);
- int node = dev_of_offset(bus);
- const void *blob = gd->fdt_blob;
int ret;
int i;
@@ -629,6 +627,8 @@
mxcs->max_hz = clk_get_rate(&clk);
#else
+ int node = dev_of_offset(bus);
+ const void *blob = gd->fdt_blob;
mxcs->max_hz = fdtdec_get_int(blob, node, "spi-max-frequency",
20000000);
#endif
diff --git a/drivers/tpm/cr50_i2c.c b/drivers/tpm/cr50_i2c.c
index 76432bd..7a2b5a4 100644
--- a/drivers/tpm/cr50_i2c.c
+++ b/drivers/tpm/cr50_i2c.c
@@ -18,8 +18,6 @@
#include <acpi/acpi_device.h>
#include <asm/gpio.h>
#include <asm/io.h>
-#include <asm/arch/iomap.h>
-#include <asm/arch/pm.h>
#include <linux/delay.h>
#include <dm/acpi.h>
diff --git a/drivers/usb/Kconfig b/drivers/usb/Kconfig
index f697573..ab1d061 100644
--- a/drivers/usb/Kconfig
+++ b/drivers/usb/Kconfig
@@ -34,8 +34,8 @@
if USB
config DM_USB
- bool "Enable driver model for USB"
- depends on USB && DM
+ bool
+ depends on DM && OF_CONTROL
help
Enable driver model for USB. The USB interface is then implemented
by the USB uclass. Multiple USB controllers of different types
@@ -48,7 +48,7 @@
automatically probed when found on the bus.
config SPL_DM_USB
- bool "Enable driver model for USB in SPL"
+ bool "Enable driver model for USB host most in SPL"
depends on SPL_DM && DM_USB
default y
@@ -84,6 +84,8 @@
source "drivers/usb/ulpi/Kconfig"
+if USB_HOST
+
comment "USB peripherals"
config USB_STORAGE
@@ -129,8 +131,10 @@
endif
-source "drivers/usb/gadget/Kconfig"
-
source "drivers/usb/eth/Kconfig"
endif
+
+source "drivers/usb/gadget/Kconfig"
+
+endif
diff --git a/drivers/usb/cdns3/Kconfig b/drivers/usb/cdns3/Kconfig
index 4cf59c7..05785fc 100644
--- a/drivers/usb/cdns3/Kconfig
+++ b/drivers/usb/cdns3/Kconfig
@@ -1,6 +1,6 @@
config USB_CDNS3
tristate "Cadence USB3 Dual-Role Controller"
- depends on USB_HOST || USB_GADGET
+ depends on USB_XHCI_HCD || USB_GADGET
help
Say Y here if your system has a Cadence USB3 dual-role controller.
It supports: Host-only, and Peripheral-only.
diff --git a/drivers/usb/dwc3/Kconfig b/drivers/usb/dwc3/Kconfig
index 802ee50..93707e0 100644
--- a/drivers/usb/dwc3/Kconfig
+++ b/drivers/usb/dwc3/Kconfig
@@ -1,6 +1,6 @@
config USB_DWC3
bool "DesignWare USB3 DRD Core Support"
- depends on USB_HOST || USB_GADGET
+ depends on USB_XHCI_HCD || USB_GADGET
help
Say Y here if your system has a Dual Role SuperSpeed
USB controller based on the DesignWare USB3 IP Core.
diff --git a/drivers/usb/emul/Kconfig b/drivers/usb/emul/Kconfig
index ae1ab23..279f6c6 100644
--- a/drivers/usb/emul/Kconfig
+++ b/drivers/usb/emul/Kconfig
@@ -1,6 +1,8 @@
config USB_EMUL
bool "Support for USB device emulation"
- depends on DM_USB && SANDBOX
+ depends on SANDBOX
+ select DM_USB
+ select USB_HOST
help
Since sandbox does not have access to a real USB bus, it is possible
to use device emulators instead. This allows testing of the USB
diff --git a/drivers/usb/gadget/Kconfig b/drivers/usb/gadget/Kconfig
index 4a3b22e..327ea86 100644
--- a/drivers/usb/gadget/Kconfig
+++ b/drivers/usb/gadget/Kconfig
@@ -15,6 +15,8 @@
menuconfig USB_GADGET
bool "USB Gadget Support"
+ depends on DM
+ select DM_USB
help
USB is a master/slave protocol, organized with one master
host (such as a PC) controlling up to 127 peripheral devices.
diff --git a/drivers/usb/host/Kconfig b/drivers/usb/host/Kconfig
index f34cba2..427b360 100644
--- a/drivers/usb/host/Kconfig
+++ b/drivers/usb/host/Kconfig
@@ -5,9 +5,11 @@
config USB_HOST
bool
+ select DM_USB
config USB_XHCI_HCD
bool "xHCI HCD (USB 3.0) support"
+ depends on DM && OF_CONTROL
select USB_HOST
---help---
The eXtensible Host Controller Interface (xHCI) is standard for USB 3.0
@@ -107,6 +109,7 @@
config USB_EHCI_HCD
bool "EHCI HCD (USB 2.0) support"
default y if ARCH_MX5 || ARCH_MX6
+ depends on DM && OF_CONTROL
select USB_HOST
---help---
The Enhanced Host Controller Interface (EHCI) is standard for USB 2.0
@@ -217,7 +220,6 @@
config USB_EHCI_GENERIC
bool "Support for generic EHCI USB controller"
- depends on OF_CONTROL
depends on DM_USB
default ARCH_SUNXI
default n
@@ -234,6 +236,8 @@
config USB_OHCI_HCD
bool "OHCI HCD (USB 1.1) support"
+ depends on DM && OF_CONTROL
+ select USB_HOST
---help---
The Open Host Controller Interface (OHCI) is a standard for accessing
USB 1.1 host controller hardware. It does more in hardware than Intel's
@@ -244,21 +248,17 @@
based system where you're not sure, the "lspci -v" entry will list the
right "prog-if" for your USB controller(s): EHCI, OHCI, or UHCI.
+if USB_OHCI_HCD
+
config USB_OHCI_PCI
bool "Support for PCI-based OHCI USB controller"
- depends on DM_USB
- default n
+ depends on PCI
help
Enables support for the PCI-based OHCI controller.
-if USB_OHCI_HCD
-
config USB_OHCI_GENERIC
bool "Support for generic OHCI USB controller"
- depends on OF_CONTROL
- depends on DM_USB
default ARCH_SUNXI
- select USB_HOST
---help---
Enables support for generic OHCI controller.
@@ -289,6 +289,7 @@
config USB_DWC2
bool "DesignWare USB2 Core support"
+ depends on DM && OF_CONTROL
select USB_HOST
---help---
The DesignWare USB 2.0 controller is compliant with the
@@ -311,8 +312,7 @@
config USB_R8A66597_HCD
bool "Renesas R8A66597 USB Core support"
- depends on OF_CONTROL
- depends on DM_USB
+ depends on DM && OF_CONTROL
select USB_HOST
---help---
This enables support for the on-chip Renesas R8A66597 USB 2.0
diff --git a/drivers/usb/mtu3/Kconfig b/drivers/usb/mtu3/Kconfig
index a2a5991..5ec498e 100644
--- a/drivers/usb/mtu3/Kconfig
+++ b/drivers/usb/mtu3/Kconfig
@@ -4,7 +4,7 @@
config USB_MTU3
bool "MediaTek USB3 Dual Role controller"
- depends on USB_HOST || USB_GADGET
+ depends on USB_XHCI_HCD || USB_GADGET
depends on ARCH_MEDIATEK
help
Say Y here if your system runs on MediaTek SoCs with
diff --git a/drivers/usb/musb-new/Kconfig b/drivers/usb/musb-new/Kconfig
index 81ceea9..a9a7c26 100644
--- a/drivers/usb/musb-new/Kconfig
+++ b/drivers/usb/musb-new/Kconfig
@@ -5,22 +5,26 @@
config USB_MUSB_HOST
bool "MUSB host mode support"
+ depends on DM && OF_CONTROL
select SPL_SPRINTF if SPL
select TPL_SPRINTF if TPL
+ select USB_HOST
help
Enables the MUSB USB dual-role controller in host mode.
config USB_MUSB_GADGET
bool "MUSB gadget mode support"
+ depends on USB_GADGET
select USB_GADGET_DUALSPEED
select SPL_SPRINTF if SPL
select TPL_SPRINTF if TPL
help
Enables the MUSB USB dual-role controller in gadget mode.
+if USB_MUSB_HOST || USB_MUSB_GADGET
config USB_MUSB_DA8XX
bool "Enable DA8xx MUSB Controller"
- depends on DM_USB
+ depends on ARCH_DAVINCI
help
Say y here to enable support for the dual role high
speed USB controller based on the Mentor Graphics
@@ -28,7 +32,7 @@
config USB_MUSB_TI
bool "Enable TI OTG USB controller"
- depends on DM_USB
+ depends on AM33XX
select USB_MUSB_DSPS
default n
help
@@ -46,10 +50,9 @@
config USB_MUSB_DSPS
bool "TI DSPS platforms"
-if USB_MUSB_HOST || USB_MUSB_GADGET
config USB_MUSB_MT85XX
bool "Enable Mediatek MT85XX DRC USB controller"
- depends on DM_USB && ARCH_MEDIATEK
+ depends on ARCH_MEDIATEK
default n
help
Say y to enable Mediatek MT85XX USB DRC controller support
@@ -59,7 +62,7 @@
config USB_MUSB_PIC32
bool "Enable Microchip PIC32 DRC USB controller"
- depends on DM_USB && MACH_PIC32
+ depends on MACH_PIC32
help
Say y to enable PIC32 USB DRC controller support
if it is available on your Microchip PIC32 platform.
diff --git a/drivers/video/pwm_backlight.c b/drivers/video/pwm_backlight.c
index 4c86215..d7c0969 100644
--- a/drivers/video/pwm_backlight.c
+++ b/drivers/video/pwm_backlight.c
@@ -235,8 +235,10 @@
priv->levels = malloc(len);
if (!priv->levels)
return log_ret(-ENOMEM);
- dev_read_u32_array(dev, "brightness-levels", priv->levels,
- count);
+ ret = dev_read_u32_array(dev, "brightness-levels", priv->levels,
+ count);
+ if (ret)
+ return log_msg_ret("levels", ret);
priv->num_levels = count;
priv->default_level = priv->levels[index];
priv->max_level = priv->levels[count - 1];
diff --git a/drivers/watchdog/designware_wdt.c b/drivers/watchdog/designware_wdt.c
index 9e54871..afed81e 100644
--- a/drivers/watchdog/designware_wdt.c
+++ b/drivers/watchdog/designware_wdt.c
@@ -22,6 +22,7 @@
struct designware_wdt_priv {
void __iomem *base;
unsigned int clk_khz;
+ struct reset_ctl_bulk *resets;
};
/*
@@ -95,6 +96,18 @@
designware_wdt_reset(dev);
writel(0, priv->base + DW_WDT_CR);
+ if (CONFIG_IS_ENABLED(DM_RESET)) {
+ int ret;
+
+ ret = reset_assert_bulk(priv->resets);
+ if (ret)
+ return ret;
+
+ ret = reset_deassert_bulk(priv->resets);
+ if (ret)
+ return ret;
+ }
+
return 0;
}
@@ -143,13 +156,11 @@
#endif
if (CONFIG_IS_ENABLED(DM_RESET)) {
- struct reset_ctl_bulk resets;
-
- ret = reset_get_bulk(dev, &resets);
+ ret = reset_get_bulk(dev, priv->resets);
if (ret)
goto err;
- ret = reset_deassert_bulk(&resets);
+ ret = reset_deassert_bulk(priv->resets);
if (ret)
goto err;
}
diff --git a/drivers/watchdog/ulp_wdog.c b/drivers/watchdog/ulp_wdog.c
index 6f63b11..ecd35ef 100644
--- a/drivers/watchdog/ulp_wdog.c
+++ b/drivers/watchdog/ulp_wdog.c
@@ -12,9 +12,7 @@
* MX7ULP WDOG Register Map
*/
struct wdog_regs {
- u8 cs1;
- u8 cs2;
- u16 reserve0;
+ u32 cs;
u32 cnt;
u32 toval;
u32 win;
@@ -30,10 +28,12 @@
#define UNLOCK_WORD0 0xC520 /* 1st unlock word */
#define UNLOCK_WORD1 0xD928 /* 2nd unlock word */
-#define WDGCS1_WDGE (1<<7)
-#define WDGCS1_WDGUPDATE (1<<5)
+#define WDGCS_WDGE BIT(7)
+#define WDGCS_WDGUPDATE BIT(5)
-#define WDGCS2_FLG (1<<6)
+#define WDGCS_RCS BIT(10)
+#define WDGCS_ULK BIT(11)
+#define WDGCS_FLG BIT(14)
#define WDG_BUS_CLK (0x0)
#define WDG_LPO_CLK (0x1)
@@ -52,27 +52,34 @@
{
struct wdog_regs *wdog = (struct wdog_regs *)WDOG_BASE_ADDR;
- writel(REFRESH_WORD0, &wdog->cnt);
- writel(REFRESH_WORD1, &wdog->cnt);
+ dmb();
+ __raw_writel(REFRESH_WORD0, &wdog->cnt);
+ __raw_writel(REFRESH_WORD1, &wdog->cnt);
+ dmb();
}
void hw_watchdog_init(void)
{
- u8 val;
struct wdog_regs *wdog = (struct wdog_regs *)WDOG_BASE_ADDR;
- writel(UNLOCK_WORD0, &wdog->cnt);
- writel(UNLOCK_WORD1, &wdog->cnt);
+ dmb();
+ __raw_writel(UNLOCK_WORD0, &wdog->cnt);
+ __raw_writel(UNLOCK_WORD1, &wdog->cnt);
+ dmb();
- val = readb(&wdog->cs2);
- val |= WDGCS2_FLG;
- writeb(val, &wdog->cs2);
+ /* Wait WDOG Unlock */
+ while (!(readl(&wdog->cs) & WDGCS_ULK))
+ ;
hw_watchdog_set_timeout(CONFIG_WATCHDOG_TIMEOUT_MSECS);
writel(0, &wdog->win);
- writeb(WDG_LPO_CLK, &wdog->cs2);/* setting 1-kHz clock source */
- writeb((WDGCS1_WDGE | WDGCS1_WDGUPDATE), &wdog->cs1);/* enable counter running */
+ /* setting 1-kHz clock source, enable counter running, and clear interrupt */
+ writel((WDGCS_WDGE | WDGCS_WDGUPDATE |(WDG_LPO_CLK << 8) | WDGCS_FLG), &wdog->cs);
+
+ /* Wait WDOG reconfiguration */
+ while (!(readl(&wdog->cs) & WDGCS_RCS))
+ ;
hw_watchdog_reset();
}
@@ -81,14 +88,24 @@
{
struct wdog_regs *wdog = (struct wdog_regs *)WDOG_BASE_ADDR;
- writel(UNLOCK_WORD0, &wdog->cnt);
- writel(UNLOCK_WORD1, &wdog->cnt);
+ dmb();
+ __raw_writel(UNLOCK_WORD0, &wdog->cnt);
+ __raw_writel(UNLOCK_WORD1, &wdog->cnt);
+ dmb();
+
+ /* Wait WDOG Unlock */
+ while (!(readl(&wdog->cs) & WDGCS_ULK))
+ ;
hw_watchdog_set_timeout(5); /* 5ms timeout */
writel(0, &wdog->win);
- writeb(WDG_LPO_CLK, &wdog->cs2);/* setting 1-kHz clock source */
- writeb(WDGCS1_WDGE, &wdog->cs1);/* enable counter running */
+ /* enable counter running */
+ writel((WDGCS_WDGE | (WDG_LPO_CLK << 8)), &wdog->cs);
+
+ /* Wait WDOG reconfiguration */
+ while (!(readl(&wdog->cs) & WDGCS_RCS))
+ ;
hw_watchdog_reset();
diff --git a/drivers/watchdog/wdt-uclass.c b/drivers/watchdog/wdt-uclass.c
index a0c2429..17334db 100644
--- a/drivers/watchdog/wdt-uclass.c
+++ b/drivers/watchdog/wdt-uclass.c
@@ -53,7 +53,7 @@
4 * reset_period) / 4;
}
- if (!CONFIG_IS_ENABLED(WATCHDOG_AUTOSTART)) {
+ if (!IS_ENABLED(CONFIG_WATCHDOG_AUTOSTART)) {
printf("WDT: Not starting\n");
return 0;
}
diff --git a/fs/cbfs/cbfs.c b/fs/cbfs/cbfs.c
index 415ea28..3e905c7 100644
--- a/fs/cbfs/cbfs.c
+++ b/fs/cbfs/cbfs.c
@@ -167,6 +167,8 @@
}
swap_file_header(&header, file_header);
+ if (header.offset >= size)
+ return log_msg_ret("range", -E2BIG);
ret = fill_node(node, start, &header);
if (ret) {
priv->result = CBFS_BAD_FILE;
diff --git a/include/asm-generic/sections.h b/include/asm-generic/sections.h
index 267f1db..ec992b0 100644
--- a/include/asm-generic/sections.h
+++ b/include/asm-generic/sections.h
@@ -27,6 +27,8 @@
extern char __efi_helloworld_end[];
extern char __efi_var_file_begin[];
extern char __efi_var_file_end[];
+extern char __efi_capsule_sig_begin[];
+extern char __efi_capsule_sig_end[];
/* Private data used by of-platdata devices/uclasses */
extern char __priv_data_start[], __priv_data_end[];
diff --git a/include/configs/M52277EVB.h b/include/configs/M52277EVB.h
deleted file mode 100644
index 0428be7..0000000
--- a/include/configs/M52277EVB.h
+++ /dev/null
@@ -1,243 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0+ */
-/*
- * Configuation settings for the Freescale MCF52277 EVB board.
- *
- * Copyright (C) 2004-2007 Freescale Semiconductor, Inc.
- * TsiChung Liew (Tsi-Chung.Liew@freescale.com)
- */
-
-/*
- * board/config.h - configuration options, board specific
- */
-
-#ifndef _M52277EVB_H
-#define _M52277EVB_H
-
-#include <linux/stringify.h>
-
-/*
- * High Level Configuration Options
- * (easy to change)
- */
-
-#define CONFIG_MCFUART
-#define CONFIG_SYS_UART_PORT (0)
-
-#undef CONFIG_WATCHDOG
-
-#define CONFIG_TIMESTAMP /* Print image info with timestamp */
-
-/*
- * BOOTP options
- */
-#define CONFIG_BOOTP_BOOTFILESIZE
-
-#define CONFIG_HOSTNAME "M52277EVB"
-#define CONFIG_SYS_UBOOT_END 0x3FFFF
-#define CONFIG_SYS_LOAD_ADDR2 0x40010007
-#ifdef CONFIG_SYS_STMICRO_BOOT
-/* ST Micro serial flash */
-#define CONFIG_EXTRA_ENV_SETTINGS \
- "inpclk=" __stringify(CONFIG_SYS_INPUT_CLKSRC) "\0" \
- "loadaddr=0x40010000\0" \
- "uboot=u-boot.bin\0" \
- "load=loadb ${loadaddr} ${baudrate};" \
- "loadb " __stringify(CONFIG_SYS_LOAD_ADDR2) " ${baudrate} \0" \
- "upd=run load; run prog\0" \
- "prog=sf probe 0:2 10000 1;" \
- "sf erase 0 30000;" \
- "sf write ${loadaddr} 0 30000;" \
- "save\0" \
- ""
-#endif
-#ifdef CONFIG_SYS_SPANSION_BOOT
-#define CONFIG_EXTRA_ENV_SETTINGS \
- "inpclk=" __stringify(CONFIG_SYS_INPUT_CLKSRC) "\0" \
- "loadaddr=0x40010000\0" \
- "uboot=u-boot.bin\0" \
- "load=loadb ${loadaddr} ${baudrate}\0" \
- "upd=run load; run prog\0" \
- "prog=prot off " __stringify(CONFIG_SYS_FLASH_BASE) \
- " " __stringify(CONFIG_SYS_UBOOT_END) ";" \
- "era " __stringify(CONFIG_SYS_FLASH_BASE) " " \
- __stringify(CONFIG_SYS_UBOOT_END) ";" \
- "cp.b ${loadaddr} " __stringify(CONFIG_SYS_FLASH_BASE) \
- " ${filesize}; save\0" \
- "updsbf=run loadsbf; run progsbf\0" \
- "loadsbf=loadb ${loadaddr} ${baudrate};" \
- "loadb " __stringify(CONFIG_SYS_LOAD_ADDR2) " ${baudrate} \0" \
- "progsbf=sf probe 0:2 10000 1;" \
- "sf erase 0 30000;" \
- "sf write ${loadaddr} 0 30000;" \
- ""
-#endif
-
-/* LCD */
-#ifdef CONFIG_CMD_BMP
-#define CONFIG_LCD_LOGO
-#define CONFIG_SHARP_LQ035Q7DH06
-#endif
-
-/* USB */
-#ifdef CONFIG_CMD_USB
-#define CONFIG_SYS_USB_EHCI_REGS_BASE 0xFC0B0000
-#define CONFIG_SYS_USB_EHCI_CPU_INIT
-#endif
-
-/* Realtime clock */
-#define CONFIG_MCFRTC
-#undef RTC_DEBUG
-#define CONFIG_SYS_RTC_OSCILLATOR (32 * CONFIG_SYS_HZ)
-
-/* Timer */
-#define CONFIG_MCFTMR
-
-/* I2c */
-#define CONFIG_SYS_I2C
-#define CONFIG_SYS_I2C_FSL
-#define CONFIG_SYS_FSL_I2C_SPEED 80000
-#define CONFIG_SYS_FSL_I2C_SLAVE 0x7F
-#define CONFIG_SYS_FSL_I2C_OFFSET 0x58000
-#define CONFIG_SYS_IMMR CONFIG_SYS_MBAR
-
-/* DSPI and Serial Flash */
-#define CONFIG_CF_DSPI
-#define CONFIG_SYS_SBFHDR_SIZE 0x7
-
-/* Input, PCI, Flexbus, and VCO */
-#define CONFIG_EXTRA_CLOCK
-
-#define CONFIG_SYS_INPUT_CLKSRC 16000000
-
-#define CONFIG_PRAM 2048 /* 2048 KB */
-
-#define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_SDRAM_BASE + 0x10000)
-
-#define CONFIG_SYS_MBAR 0xFC000000
-
-/*
- * Low Level Configuration Settings
- * (address mappings, register initial values, etc.)
- * You should know what you are doing if you make changes here.
- */
-
-/*
- * Definitions for initial stack pointer and data area (in DPRAM)
- */
-#define CONFIG_SYS_INIT_RAM_ADDR 0x80000000
-#define CONFIG_SYS_INIT_RAM_SIZE 0x8000 /* Size of used area in internal SRAM */
-#define CONFIG_SYS_INIT_RAM_CTRL 0x221
-#define CONFIG_SYS_GBL_DATA_OFFSET ((CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) - 32)
-#define CONFIG_SYS_INIT_SP_OFFSET (CONFIG_SYS_GBL_DATA_OFFSET - 32)
-#define CONFIG_SYS_SBFHDR_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - 32)
-
-/*
- * Start addresses for the final memory configuration
- * (Set up by the startup code)
- * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
- */
-#define CONFIG_SYS_SDRAM_BASE 0x40000000
-#define CONFIG_SYS_SDRAM_SIZE 64 /* SDRAM size in MB */
-#define CONFIG_SYS_SDRAM_CFG1 0x43711630
-#define CONFIG_SYS_SDRAM_CFG2 0x56670000
-#define CONFIG_SYS_SDRAM_CTRL 0xE1092000
-#define CONFIG_SYS_SDRAM_EMOD 0x81810000
-#define CONFIG_SYS_SDRAM_MODE 0x00CD0000
-#define CONFIG_SYS_SDRAM_DRV_STRENGTH 0x00
-
-#ifdef CONFIG_CF_SBF
-# define CONFIG_SYS_MONITOR_BASE (CONFIG_SYS_TEXT_BASE + 0x400)
-#else
-# define CONFIG_SYS_MONITOR_BASE (CONFIG_SYS_FLASH_BASE + 0x400)
-#endif
-#define CONFIG_SYS_BOOTPARAMS_LEN 64*1024
-#define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */
-#define CONFIG_SYS_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */
-
-/* Initial Memory map for Linux */
-#define CONFIG_SYS_BOOTMAPSZ (CONFIG_SYS_SDRAM_BASE + (CONFIG_SYS_SDRAM_SIZE << 20))
-#define CONFIG_SYS_BOOTM_LEN (CONFIG_SYS_SDRAM_SIZE << 20)
-
-/*
- * Configuration for environment
- * Environment is not embedded in u-boot. First time runing may have env
- * crc error warning if there is no correct environment on the flash.
- */
-
-/*-----------------------------------------------------------------------
- * FLASH organization
- */
-#ifdef CONFIG_SYS_STMICRO_BOOT
-# define CONFIG_SYS_FLASH_BASE CONFIG_SYS_CS0_BASE
-# define CONFIG_SYS_FLASH0_BASE CONFIG_SYS_CS0_BASE
-#endif
-#ifdef CONFIG_SYS_SPANSION_BOOT
-# define CONFIG_SYS_FLASH_BASE CONFIG_SYS_CS0_BASE
-# define CONFIG_SYS_FLASH0_BASE CONFIG_SYS_CS0_BASE
-#endif
-
-#ifdef CONFIG_SYS_FLASH_CFI
-# define CONFIG_FLASH_SPANSION_S29WS_N 1
-# define CONFIG_SYS_FLASH_SIZE 0x1000000 /* Max size that the board might have */
-# define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_16BIT
-# define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */
-# define CONFIG_SYS_MAX_FLASH_SECT 137 /* max number of sectors on one chip */
-# define CONFIG_SYS_FLASH_CHECKSUM
-# define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_CS0_BASE }
-#endif
-
-#define LDS_BOARD_TEXT \
- arch/m68k/cpu/mcf5227x/built-in.o (.text*) \
- arch/m68k/lib/built-in.o (.text*)
-
-/*
- * This is setting for JFFS2 support in u-boot.
- * NOTE: Enable CONFIG_CMD_JFFS2 for JFFS2 support.
- */
-#ifdef CONFIG_CMD_JFFS2
-# define CONFIG_JFFS2_DEV "nor0"
-# define CONFIG_JFFS2_PART_SIZE (0x01000000 - 0x40000)
-# define CONFIG_JFFS2_PART_OFFSET (CONFIG_SYS_FLASH0_BASE + 0x40000)
-#endif
-
-/*-----------------------------------------------------------------------
- * Cache Configuration
- */
-#define CONFIG_SYS_CACHELINE_SIZE 16
-
-#define ICACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \
- CONFIG_SYS_INIT_RAM_SIZE - 8)
-#define DCACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \
- CONFIG_SYS_INIT_RAM_SIZE - 4)
-#define CONFIG_SYS_ICACHE_INV (CF_CACR_CINV | CF_CACR_INVI)
-#define CONFIG_SYS_CACHE_ACR0 (CONFIG_SYS_SDRAM_BASE | \
- CF_ADDRMASK(CONFIG_SYS_SDRAM_SIZE) | \
- CF_ACR_EN | CF_ACR_SM_ALL)
-#define CONFIG_SYS_CACHE_ICACR (CF_CACR_CENB | CF_CACR_CINV | \
- CF_CACR_DISD | CF_CACR_INVI | \
- CF_CACR_CEIB | CF_CACR_DCM | \
- CF_CACR_EUSP)
-
-/*-----------------------------------------------------------------------
- * Memory bank definitions
- */
-/*
- * CS0 - NOR Flash
- * CS1 - Available
- * CS2 - Available
- * CS3 - Available
- * CS4 - Available
- * CS5 - Available
- */
-
-#ifdef CONFIG_CF_SBF
-#define CONFIG_SYS_CS0_BASE 0x04000000
-#define CONFIG_SYS_CS0_MASK 0x00FF0001
-#define CONFIG_SYS_CS0_CTRL 0x00001FA0
-#else
-#define CONFIG_SYS_CS0_BASE 0x00000000
-#define CONFIG_SYS_CS0_MASK 0x00FF0001
-#define CONFIG_SYS_CS0_CTRL 0x00001FA0
-#endif
-
-#endif /* _M52277EVB_H */
diff --git a/include/configs/M54418TWR.h b/include/configs/M54418TWR.h
deleted file mode 100644
index 5447f84..0000000
--- a/include/configs/M54418TWR.h
+++ /dev/null
@@ -1,283 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0+ */
-/*
- * Configuation settings for the Freescale MCF54418 TWR board.
- *
- * Copyright 2010-2012 Freescale Semiconductor, Inc.
- * TsiChung Liew (Tsi-Chung.Liew@freescale.com)
- */
-
-/*
- * board/config.h - configuration options, board specific
- */
-
-#ifndef _M54418TWR_H
-#define _M54418TWR_H
-
-#include <linux/stringify.h>
-
-/*
- * High Level Configuration Options
- * (easy to change)
- */
-
-#define CONFIG_MCFUART
-#define CONFIG_SYS_UART_PORT (0)
-#define CONFIG_SYS_BAUDRATE_TABLE { 9600 , 19200 , 38400 , 57600, 115200 }
-
-#define LDS_BOARD_TEXT board/freescale/m54418twr/sbf_dram_init.o (.text*)
-
-#undef CONFIG_WATCHDOG
-
-#define CONFIG_TIMESTAMP /* Print image info with timestamp */
-
-/*
- * BOOTP options
- */
-#define CONFIG_BOOTP_BOOTFILESIZE
-
-/*
- * NAND FLASH
- */
-#ifdef CONFIG_CMD_NAND
-#define CONFIG_JFFS2_NAND
-#define CONFIG_NAND_FSL_NFC
-#define CONFIG_SYS_NAND_BASE 0xFC0FC000
-#define CONFIG_SYS_MAX_NAND_DEVICE 1
-#define NAND_MAX_CHIPS CONFIG_SYS_MAX_NAND_DEVICE
-#define CONFIG_SYS_NAND_SELECT_DEVICE
-#endif
-
-/* Network configuration */
-#ifdef CONFIG_MCFFEC
-#define CONFIG_MII_INIT 1
-#define CONFIG_SYS_DISCOVER_PHY
-#define CONFIG_SYS_RX_ETH_BUFFER 2
-#define CONFIG_SYS_FAULT_ECHO_LINK_DOWN
-#define CONFIG_SYS_TX_ETH_BUFFER 2
-#define CONFIG_HAS_ETH1
-
-#define CONFIG_ETHPRIME "FEC0"
-#define CONFIG_IPADDR 192.168.1.2
-#define CONFIG_NETMASK 255.255.255.0
-#define CONFIG_SERVERIP 192.168.1.1
-#define CONFIG_GATEWAYIP 192.168.1.1
-
-#define CONFIG_SYS_FEC_BUF_USE_SRAM
-/* If CONFIG_SYS_DISCOVER_PHY is not defined - hardcoded */
-#ifndef CONFIG_SYS_DISCOVER_PHY
-#define FECDUPLEX FULL
-#define FECSPEED _100BASET
-#define LINKSTATUS 1
-#else
-#define LINKSTATUS 0
-#ifndef CONFIG_SYS_FAULT_ECHO_LINK_DOWN
-#define CONFIG_SYS_FAULT_ECHO_LINK_DOWN
-#endif
-#endif /* CONFIG_SYS_DISCOVER_PHY */
-#endif
-
-#define CONFIG_HOSTNAME "M54418TWR"
-
-#if defined(CONFIG_CF_SBF)
-/* ST Micro serial flash */
-#define CONFIG_SYS_LOAD_ADDR2 0x40010007
-#define CONFIG_EXTRA_ENV_SETTINGS \
- "netdev=eth0\0" \
- "inpclk=" __stringify(CONFIG_SYS_INPUT_CLKSRC) "\0" \
- "loadaddr=0x40010000\0" \
- "sbfhdr=sbfhdr.bin\0" \
- "uboot=u-boot.bin\0" \
- "load=tftp ${loadaddr} ${sbfhdr};" \
- "tftp " __stringify(CONFIG_SYS_LOAD_ADDR2) " ${uboot} \0" \
- "upd=run load; run prog\0" \
- "prog=sf probe 0:1 1000000 3;" \
- "sf erase 0 40000;" \
- "sf write ${loadaddr} 0 40000;" \
- "save\0" \
- ""
-#elif defined(CONFIG_SYS_NAND_BOOT)
-#define CONFIG_EXTRA_ENV_SETTINGS \
- "netdev=eth0\0" \
- "inpclk=" __stringify(CONFIG_SYS_INPUT_CLKSRC) "\0" \
- "loadaddr=0x40010000\0" \
- "u-boot=u-boot.bin\0" \
- "load=tftp ${loadaddr} ${u-boot};\0" \
- "upd=run load; run prog\0" \
- "prog=nand device 0;" \
- "nand erase 0 40000;" \
- "nb_update ${loadaddr} ${filesize};" \
- "save\0" \
- ""
-#else
-#define CONFIG_SYS_UBOOT_END 0x3FFFF
-#define CONFIG_EXTRA_ENV_SETTINGS \
- "netdev=eth0\0" \
- "inpclk=" __stringify(CONFIG_SYS_INPUT_CLKSRC) "\0" \
- "loadaddr=40010000\0" \
- "u-boot=u-boot.bin\0" \
- "load=tftp ${loadaddr) ${u-boot}\0" \
- "upd=run load; run prog\0" \
- "prog=prot off mram" " ;" \
- "cp.b ${loadaddr} 0 ${filesize};" \
- "save\0" \
- ""
-#endif
-
-/* Realtime clock */
-#undef CONFIG_MCFRTC
-#define CONFIG_RTC_MCFRRTC
-#define CONFIG_SYS_MCFRRTC_BASE 0xFC0A8000
-
-/* Timer */
-#define CONFIG_MCFTMR
-
-/* I2c */
-#undef CONFIG_SYS_FSL_I2C
-#undef CONFIG_SYS_I2C_SOFT /* I2C bit-banged */
-/* I2C speed and slave address */
-#define CONFIG_SYS_I2C_SPEED 80000
-#define CONFIG_SYS_I2C_SLAVE 0x7F
-#define CONFIG_SYS_I2C_OFFSET 0x58000
-#define CONFIG_SYS_IMMR CONFIG_SYS_MBAR
-
-/* DSPI and Serial Flash */
-#define CONFIG_CF_DSPI
-#define CONFIG_SERIAL_FLASH
-#define CONFIG_SYS_SBFHDR_SIZE 0x7
-
-/* Input, PCI, Flexbus, and VCO */
-#define CONFIG_EXTRA_CLOCK
-
-#define CONFIG_PRAM 2048 /* 2048 KB */
-
-#define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_SDRAM_BASE + 0x10000)
-
-#define CONFIG_SYS_MBAR 0xFC000000
-
-/*
- * Low Level Configuration Settings
- * (address mappings, register initial values, etc.)
- * You should know what you are doing if you make changes here.
- */
-
-/*-----------------------------------------------------------------------
- * Definitions for initial stack pointer and data area (in DPRAM)
- */
-#define CONFIG_SYS_INIT_RAM_ADDR 0x80000000
-/* End of used area in internal SRAM */
-#define CONFIG_SYS_INIT_RAM_SIZE 0x10000
-#define CONFIG_SYS_INIT_RAM_CTRL 0x221
-#define CONFIG_SYS_GBL_DATA_OFFSET ((CONFIG_SYS_INIT_RAM_SIZE - \
- GENERATED_GBL_DATA_SIZE) - 32)
-#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
-#define CONFIG_SYS_SBFHDR_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - 32)
-
-/*-----------------------------------------------------------------------
- * Start addresses for the final memory configuration
- * (Set up by the startup code)
- * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
- */
-#define CONFIG_SYS_SDRAM_BASE 0x40000000
-#define CONFIG_SYS_SDRAM_SIZE 128 /* SDRAM size in MB */
-
-#define CONFIG_SYS_DRAM_TEST
-
-#if defined(CONFIG_CF_SBF) || defined(CONFIG_SYS_NAND_BOOT)
-#define CONFIG_SERIAL_BOOT
-#endif
-
-#if defined(CONFIG_SERIAL_BOOT)
-#define CONFIG_SYS_MONITOR_BASE (CONFIG_SYS_TEXT_BASE + 0x400)
-#else
-#define CONFIG_SYS_MONITOR_BASE (CONFIG_SYS_FLASH_BASE + 0x400)
-#endif
-
-#define CONFIG_SYS_BOOTPARAMS_LEN (64 * 1024)
-/* Reserve 256 kB for Monitor */
-#define CONFIG_SYS_MONITOR_LEN (256 << 10)
-/* Reserve 256 kB for malloc() */
-#define CONFIG_SYS_MALLOC_LEN (256 << 10)
-
-/*
- * For booting Linux, the board info and command line data
- * have to be in the first 8 MB of memory, since this is
- * the maximum mapped by the Linux kernel during initialization ??
- */
-/* Initial Memory map for Linux */
-#define CONFIG_SYS_BOOTMAPSZ (CONFIG_SYS_SDRAM_BASE + \
- (CONFIG_SYS_SDRAM_SIZE << 20))
-
-/* Configuration for environment
- * Environment is embedded in u-boot in the second sector of the flash
- */
-
-/* FLASH organization */
-#define CONFIG_SYS_FLASH_BASE CONFIG_SYS_CS0_BASE
-
-#ifdef CONFIG_SYS_FLASH_CFI
-
-/* Max size that the board might have */
-#define CONFIG_SYS_FLASH_SIZE 0x1000000
-#define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_16BIT
-/* max number of memory banks */
-#define CONFIG_SYS_MAX_FLASH_BANKS 1
-/* max number of sectors on one chip */
-#define CONFIG_SYS_MAX_FLASH_SECT 270
-/* "Real" (hardware) sectors protection */
-#define CONFIG_SYS_FLASH_CHECKSUM
-#define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_CS0_BASE }
-#else
-/* max number of sectors on one chip */
-#define CONFIG_SYS_MAX_FLASH_SECT 270
-/* max number of sectors on one chip */
-#define CONFIG_SYS_MAX_FLASH_BANKS 0
-#endif
-
-/*
- * This is setting for JFFS2 support in u-boot.
- * NOTE: Enable CONFIG_CMD_JFFS2 for JFFS2 support.
- */
-#ifdef CONFIG_CMD_JFFS2
-#define CONFIG_JFFS2_DEV "nand0"
-#define CONFIG_JFFS2_PART_OFFSET (0x800000)
-
-#endif
-
-/* Cache Configuration */
-#define CONFIG_SYS_CACHELINE_SIZE 16
-#define ICACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \
- CONFIG_SYS_INIT_RAM_SIZE - 8)
-#define DCACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \
- CONFIG_SYS_INIT_RAM_SIZE - 4)
-#define CONFIG_SYS_ICACHE_INV (CF_CACR_BCINVA + CF_CACR_ICINVA)
-#define CONFIG_SYS_DCACHE_INV (CF_CACR_DCINVA)
-#define CONFIG_SYS_CACHE_ACR2 (CONFIG_SYS_SDRAM_BASE | \
- CF_ADDRMASK(CONFIG_SYS_SDRAM_SIZE) | \
- CF_ACR_EN | CF_ACR_SM_ALL)
-#define CONFIG_SYS_CACHE_ICACR (CF_CACR_BEC | CF_CACR_IEC | \
- CF_CACR_ICINVA | CF_CACR_EUSP)
-#define CONFIG_SYS_CACHE_DCACR ((CONFIG_SYS_CACHE_ICACR | \
- CF_CACR_DEC | CF_CACR_DDCM_P | \
- CF_CACR_DCINVA) & ~CF_CACR_ICINVA)
-
-#define CACR_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \
- CONFIG_SYS_INIT_RAM_SIZE - 12)
-
-/*-----------------------------------------------------------------------
- * Memory bank definitions
- */
-/*
- * CS0 - NOR Flash 16MB
- * CS1 - Available
- * CS2 - Available
- * CS3 - Available
- * CS4 - Available
- * CS5 - Available
- */
-
- /* Flash */
-#define CONFIG_SYS_CS0_BASE 0x00000000
-#define CONFIG_SYS_CS0_MASK 0x000F0101
-#define CONFIG_SYS_CS0_CTRL 0x00001D60
-
-#endif /* _M54418TWR_H */
diff --git a/include/configs/M54451EVB.h b/include/configs/M54451EVB.h
deleted file mode 100644
index f5bafb7..0000000
--- a/include/configs/M54451EVB.h
+++ /dev/null
@@ -1,242 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0+ */
-/*
- * Configuation settings for the Freescale MCF54451 EVB board.
- *
- * Copyright (C) 2004-2008 Freescale Semiconductor, Inc.
- * TsiChung Liew (Tsi-Chung.Liew@freescale.com)
- */
-
-/*
- * board/config.h - configuration options, board specific
- */
-
-#ifndef _M54451EVB_H
-#define _M54451EVB_H
-
-#include <linux/stringify.h>
-
-/*
- * High Level Configuration Options
- * (easy to change)
- */
-#define CONFIG_M54451EVB /* M54451EVB board */
-
-#define CONFIG_MCFUART
-#define CONFIG_SYS_UART_PORT (0)
-
-#define LDS_BOARD_TEXT board/freescale/m54451evb/sbf_dram_init.o (.text*)
-
-#undef CONFIG_WATCHDOG
-
-#define CONFIG_TIMESTAMP /* Print image info with timestamp */
-
-/*
- * BOOTP options
- */
-#define CONFIG_BOOTP_BOOTFILESIZE
-
-/* Network configuration */
-#ifdef CONFIG_MCFFEC
-# define CONFIG_MII_INIT 1
-# define CONFIG_SYS_DISCOVER_PHY
-# define CONFIG_SYS_RX_ETH_BUFFER 8
-# define CONFIG_SYS_FAULT_ECHO_LINK_DOWN
-# define CONFIG_ETHPRIME "FEC0"
-# define CONFIG_IPADDR 192.162.1.2
-# define CONFIG_NETMASK 255.255.255.0
-# define CONFIG_SERVERIP 192.162.1.1
-# define CONFIG_GATEWAYIP 192.162.1.1
-
-/* If CONFIG_SYS_DISCOVER_PHY is not defined - hardcoded */
-# ifndef CONFIG_SYS_DISCOVER_PHY
-# define FECDUPLEX FULL
-# define FECSPEED _100BASET
-# else
-# ifndef CONFIG_SYS_FAULT_ECHO_LINK_DOWN
-# define CONFIG_SYS_FAULT_ECHO_LINK_DOWN
-# endif
-# endif /* CONFIG_SYS_DISCOVER_PHY */
-#endif
-
-#define CONFIG_HOSTNAME "M54451EVB"
-#ifdef CONFIG_SYS_STMICRO_BOOT
-/* ST Micro serial flash */
-#define CONFIG_SYS_LOAD_ADDR2 0x40010007
-#define CONFIG_EXTRA_ENV_SETTINGS \
- "netdev=eth0\0" \
- "inpclk=" __stringify(CONFIG_SYS_INPUT_CLKSRC) "\0" \
- "loadaddr=0x40010000\0" \
- "sbfhdr=sbfhdr.bin\0" \
- "uboot=u-boot.bin\0" \
- "load=tftp ${loadaddr} ${sbfhdr};" \
- "tftp " __stringify(CONFIG_SYS_LOAD_ADDR2) " ${uboot} \0" \
- "upd=run load; run prog\0" \
- "prog=sf probe 0:1 1000000 3;" \
- "sf erase 0 30000;" \
- "sf write ${loadaddr} 0 30000;" \
- "save\0" \
- ""
-#else
-#define CONFIG_SYS_UBOOT_END 0x3FFFF
-#define CONFIG_EXTRA_ENV_SETTINGS \
- "netdev=eth0\0" \
- "inpclk=" __stringify(CONFIG_SYS_INPUT_CLKSRC) "\0" \
- "loadaddr=40010000\0" \
- "u-boot=u-boot.bin\0" \
- "load=tftp ${loadaddr) ${u-boot}\0" \
- "upd=run load; run prog\0" \
- "prog=prot off 0 " __stringify(CONFIG_SYS_UBOOT_END) \
- "; era 0 " __stringify(CONFIG_SYS_UBOOT_END) " ;" \
- "cp.b ${loadaddr} 0 ${filesize};" \
- "save\0" \
- ""
-#endif
-
-/* Realtime clock */
-#define CONFIG_MCFRTC
-#undef RTC_DEBUG
-#define CONFIG_SYS_RTC_OSCILLATOR (32 * CONFIG_SYS_HZ)
-
-/* Timer */
-#define CONFIG_MCFTMR
-
-/* I2c */
-#define CONFIG_SYS_I2C
-#define CONFIG_SYS_I2C_FSL
-#define CONFIG_SYS_FSL_I2C_SPEED 80000
-#define CONFIG_SYS_FSL_I2C_SLAVE 0x7F
-#define CONFIG_SYS_FSL_I2C_OFFSET 0x58000
-#define CONFIG_SYS_IMMR CONFIG_SYS_MBAR
-
-/* DSPI and Serial Flash */
-#define CONFIG_CF_DSPI
-#define CONFIG_SERIAL_FLASH
-#define CONFIG_SYS_SBFHDR_SIZE 0x7
-
-/* Input, PCI, Flexbus, and VCO */
-#define CONFIG_EXTRA_CLOCK
-
-#define CONFIG_PRAM 2048 /* 2048 KB */
-
-#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
-
-#define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_SDRAM_BASE + 0x10000)
-
-#define CONFIG_SYS_MBAR 0xFC000000
-
-/*
- * Low Level Configuration Settings
- * (address mappings, register initial values, etc.)
- * You should know what you are doing if you make changes here.
- */
-
-/*-----------------------------------------------------------------------
- * Definitions for initial stack pointer and data area (in DPRAM)
- */
-#define CONFIG_SYS_INIT_RAM_ADDR 0x80000000
-#define CONFIG_SYS_INIT_RAM_SIZE 0x8000 /* Size of used area in internal SRAM */
-#define CONFIG_SYS_INIT_RAM_CTRL 0x221
-#define CONFIG_SYS_GBL_DATA_OFFSET ((CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) - 32)
-#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
-#define CONFIG_SYS_SBFHDR_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - 32)
-
-/*-----------------------------------------------------------------------
- * Start addresses for the final memory configuration
- * (Set up by the startup code)
- * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
- */
-#define CONFIG_SYS_SDRAM_BASE 0x40000000
-#define CONFIG_SYS_SDRAM_SIZE 128 /* SDRAM size in MB */
-#define CONFIG_SYS_SDRAM_CFG1 0x33633F30
-#define CONFIG_SYS_SDRAM_CFG2 0x57670000
-#define CONFIG_SYS_SDRAM_CTRL 0xE20D2C00
-#define CONFIG_SYS_SDRAM_EMOD 0x80810000
-#define CONFIG_SYS_SDRAM_MODE 0x008D0000
-#define CONFIG_SYS_SDRAM_DRV_STRENGTH 0x44
-
-#ifdef CONFIG_CF_SBF
-# define CONFIG_SERIAL_BOOT
-# define CONFIG_SYS_MONITOR_BASE (CONFIG_SYS_TEXT_BASE + 0x400)
-#else
-# define CONFIG_SYS_MONITOR_BASE (CONFIG_SYS_FLASH_BASE + 0x400)
-#endif
-#define CONFIG_SYS_BOOTPARAMS_LEN 64*1024
-#define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */
-
-/* Reserve 256 kB for malloc() */
-#define CONFIG_SYS_MALLOC_LEN (256 << 10)
-/*
- * For booting Linux, the board info and command line data
- * have to be in the first 8 MB of memory, since this is
- * the maximum mapped by the Linux kernel during initialization ??
- */
-/* Initial Memory map for Linux */
-#define CONFIG_SYS_BOOTMAPSZ (CONFIG_SYS_SDRAM_BASE + (CONFIG_SYS_SDRAM_SIZE << 20))
-
-/* Configuration for environment
- * Environment is not embedded in u-boot. First time runing may have env
- * crc error warning if there is no correct environment on the flash.
- */
-
-/* FLASH organization */
-#define CONFIG_SYS_FLASH_BASE CONFIG_SYS_CS0_BASE
-
-#ifdef CONFIG_SYS_FLASH_CFI
-
-# define CONFIG_SYS_FLASH_SIZE 0x1000000 /* Max size that the board might have */
-# define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_16BIT
-# define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */
-# define CONFIG_SYS_MAX_FLASH_SECT 137 /* max number of sectors on one chip */
-# define CONFIG_SYS_FLASH_CHECKSUM
-# define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_CS0_BASE }
-
-#endif
-
-/*
- * This is setting for JFFS2 support in u-boot.
- * NOTE: Enable CONFIG_CMD_JFFS2 for JFFS2 support.
- */
-#ifdef CONFIG_CMD_JFFS2
-# define CONFIG_JFFS2_DEV "nor0"
-# define CONFIG_JFFS2_PART_SIZE 0x01000000
-# define CONFIG_JFFS2_PART_OFFSET (CONFIG_SYS_FLASH0_BASE + 0x500000)
-#endif
-
-/* Cache Configuration */
-#define CONFIG_SYS_CACHELINE_SIZE 16
-
-#define ICACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \
- CONFIG_SYS_INIT_RAM_SIZE - 8)
-#define DCACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \
- CONFIG_SYS_INIT_RAM_SIZE - 4)
-#define CONFIG_SYS_ICACHE_INV (CF_CACR_BCINVA + CF_CACR_ICINVA)
-#define CONFIG_SYS_DCACHE_INV (CF_CACR_DCINVA)
-#define CONFIG_SYS_CACHE_ACR2 (CONFIG_SYS_SDRAM_BASE | \
- CF_ADDRMASK(CONFIG_SYS_SDRAM_SIZE) | \
- CF_ACR_EN | CF_ACR_SM_ALL)
-#define CONFIG_SYS_CACHE_ICACR (CF_CACR_BEC | CF_CACR_IEC | \
- CF_CACR_ICINVA | CF_CACR_EUSP)
-#define CONFIG_SYS_CACHE_DCACR ((CONFIG_SYS_CACHE_ICACR | \
- CF_CACR_DEC | CF_CACR_DDCM_P | \
- CF_CACR_DCINVA) & ~CF_CACR_ICINVA)
-
-/*-----------------------------------------------------------------------
- * Memory bank definitions
- */
-/*
- * CS0 - NOR Flash 16MB
- * CS1 - Available
- * CS2 - Available
- * CS3 - Available
- * CS4 - Available
- * CS5 - Available
- */
-
- /* Flash */
-#define CONFIG_SYS_CS0_BASE 0x00000000
-#define CONFIG_SYS_CS0_MASK 0x00FF0001
-#define CONFIG_SYS_CS0_CTRL 0x00004D80
-
-#define CONFIG_SYS_SPANSION_BASE CONFIG_SYS_CS0_BASE
-
-#endif /* _M54451EVB_H */
diff --git a/include/configs/M54455EVB.h b/include/configs/M54455EVB.h
deleted file mode 100644
index f3621d6..0000000
--- a/include/configs/M54455EVB.h
+++ /dev/null
@@ -1,356 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0+ */
-/*
- * Configuation settings for the Freescale MCF54455 EVB board.
- *
- * Copyright (C) 2004-2007 Freescale Semiconductor, Inc.
- * TsiChung Liew (Tsi-Chung.Liew@freescale.com)
- */
-
-/*
- * board/config.h - configuration options, board specific
- */
-
-#ifndef _M54455EVB_H
-#define _M54455EVB_H
-
-#include <linux/stringify.h>
-
-/*
- * High Level Configuration Options
- * (easy to change)
- */
-#define CONFIG_M54455EVB /* M54455EVB board */
-
-#define CONFIG_MCFUART
-#define CONFIG_SYS_UART_PORT (0)
-
-#define LDS_BOARD_TEXT board/freescale/m54455evb/sbf_dram_init.o (.text*)
-
-#undef CONFIG_WATCHDOG
-
-#define CONFIG_TIMESTAMP /* Print image info with timestamp */
-
-/*
- * BOOTP options
- */
-#define CONFIG_BOOTP_BOOTFILESIZE
-
-/* Network configuration */
-#ifdef CONFIG_MCFFEC
-# define CONFIG_MII_INIT 1
-# define CONFIG_SYS_DISCOVER_PHY
-# define CONFIG_SYS_RX_ETH_BUFFER 8
-# define CONFIG_SYS_FAULT_ECHO_LINK_DOWN
-# define CONFIG_HAS_ETH1
-# define CONFIG_ETHPRIME "FEC0"
-# define CONFIG_IPADDR 192.162.1.2
-# define CONFIG_NETMASK 255.255.255.0
-# define CONFIG_SERVERIP 192.162.1.1
-# define CONFIG_GATEWAYIP 192.162.1.1
-
-/* If CONFIG_SYS_DISCOVER_PHY is not defined - hardcoded */
-# ifndef CONFIG_SYS_DISCOVER_PHY
-# define FECDUPLEX FULL
-# define FECSPEED _100BASET
-# else
-# ifndef CONFIG_SYS_FAULT_ECHO_LINK_DOWN
-# define CONFIG_SYS_FAULT_ECHO_LINK_DOWN
-# endif
-# endif /* CONFIG_SYS_DISCOVER_PHY */
-#endif
-
-#define CONFIG_HOSTNAME "M54455EVB"
-#ifdef CONFIG_SYS_STMICRO_BOOT
-/* ST Micro serial flash */
-#define CONFIG_SYS_LOAD_ADDR2 0x40010013
-#define CONFIG_EXTRA_ENV_SETTINGS \
- "netdev=eth0\0" \
- "inpclk=" __stringify(CONFIG_SYS_INPUT_CLKSRC) "\0" \
- "loadaddr=0x40010000\0" \
- "sbfhdr=sbfhdr.bin\0" \
- "uboot=u-boot.bin\0" \
- "load=tftp ${loadaddr} ${sbfhdr};" \
- "tftp " __stringify(CONFIG_SYS_LOAD_ADDR2) " ${uboot} \0" \
- "upd=run load; run prog\0" \
- "prog=sf probe 0:1 1000000 3;" \
- "sf erase 0 30000;" \
- "sf write ${loadaddr} 0 0x30000;" \
- "save\0" \
- ""
-#else
-/* Atmel and Intel */
-#ifdef CONFIG_SYS_ATMEL_BOOT
-# define CONFIG_SYS_UBOOT_END 0x0403FFFF
-#elif defined(CONFIG_SYS_INTEL_BOOT)
-# define CONFIG_SYS_UBOOT_END 0x3FFFF
-#endif
-#define CONFIG_EXTRA_ENV_SETTINGS \
- "netdev=eth0\0" \
- "inpclk=" __stringify(CONFIG_SYS_INPUT_CLKSRC) "\0" \
- "loadaddr=0x40010000\0" \
- "uboot=u-boot.bin\0" \
- "load=tftp ${loadaddr} ${uboot}\0" \
- "upd=run load; run prog\0" \
- "prog=prot off " __stringify(CONFIG_SYS_FLASH_BASE) \
- " " __stringify(CONFIG_SYS_UBOOT_END) ";" \
- "era " __stringify(CONFIG_SYS_FLASH_BASE) " " \
- __stringify(CONFIG_SYS_UBOOT_END) ";" \
- "cp.b ${loadaddr} " __stringify(CONFIG_SYS_FLASH_BASE) \
- " ${filesize}; save\0" \
- ""
-#endif
-
-/* ATA configuration */
-#define CONFIG_IDE_RESET 1
-#define CONFIG_IDE_PREINIT 1
-#define CONFIG_ATAPI
-#undef CONFIG_LBA48
-
-#define CONFIG_SYS_IDE_MAXBUS 1
-#define CONFIG_SYS_IDE_MAXDEVICE 2
-
-#define CONFIG_SYS_ATA_BASE_ADDR 0x90000000
-#define CONFIG_SYS_ATA_IDE0_OFFSET 0
-
-#define CONFIG_SYS_ATA_DATA_OFFSET 0xA0 /* Offset for data I/O */
-#define CONFIG_SYS_ATA_REG_OFFSET 0xA0 /* Offset for normal register accesses */
-#define CONFIG_SYS_ATA_ALT_OFFSET 0xC0 /* Offset for alternate registers */
-#define CONFIG_SYS_ATA_STRIDE 4 /* Interval between registers */
-
-/* Realtime clock */
-#define CONFIG_MCFRTC
-#undef RTC_DEBUG
-#define CONFIG_SYS_RTC_OSCILLATOR (32 * CONFIG_SYS_HZ)
-
-/* Timer */
-#define CONFIG_MCFTMR
-
-/* I2c */
-#define CONFIG_SYS_I2C
-#define CONFIG_SYS_I2C_FSL
-#define CONFIG_SYS_FSL_I2C_SPEED 80000
-#define CONFIG_SYS_FSL_I2C_SLAVE 0x7F
-#define CONFIG_SYS_FSL_I2C_OFFSET 0x58000
-#define CONFIG_SYS_IMMR CONFIG_SYS_MBAR
-
-/* DSPI and Serial Flash */
-#define CONFIG_CF_DSPI
-#define CONFIG_SYS_SBFHDR_SIZE 0x13
-
-/* PCI */
-#ifdef CONFIG_CMD_PCI
-#define CONFIG_PCIAUTO_SKIP_HOST_BRIDGE 1
-
-#define CONFIG_SYS_PCI_CACHE_LINE_SIZE 4
-
-#define CONFIG_SYS_PCI_MEM_BUS 0xA0000000
-#define CONFIG_SYS_PCI_MEM_PHYS CONFIG_SYS_PCI_MEM_BUS
-#define CONFIG_SYS_PCI_MEM_SIZE 0x10000000
-
-#define CONFIG_SYS_PCI_IO_BUS 0xB1000000
-#define CONFIG_SYS_PCI_IO_PHYS CONFIG_SYS_PCI_IO_BUS
-#define CONFIG_SYS_PCI_IO_SIZE 0x01000000
-
-#define CONFIG_SYS_PCI_CFG_BUS 0xB0000000
-#define CONFIG_SYS_PCI_CFG_PHYS CONFIG_SYS_PCI_CFG_BUS
-#define CONFIG_SYS_PCI_CFG_SIZE 0x01000000
-#endif
-
-/* FPGA - Spartan 2 */
-/* experiment
-#define CONFIG_FPGA_COUNT 1
-#define CONFIG_SYS_FPGA_PROG_FEEDBACK
-#define CONFIG_SYS_FPGA_CHECK_CTRLC
-*/
-
-/* Input, PCI, Flexbus, and VCO */
-#define CONFIG_EXTRA_CLOCK
-
-#define CONFIG_PRAM 2048 /* 2048 KB */
-
-#define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_SDRAM_BASE + 0x10000)
-
-#define CONFIG_SYS_MBAR 0xFC000000
-
-/*
- * Low Level Configuration Settings
- * (address mappings, register initial values, etc.)
- * You should know what you are doing if you make changes here.
- */
-
-/*-----------------------------------------------------------------------
- * Definitions for initial stack pointer and data area (in DPRAM)
- */
-#define CONFIG_SYS_INIT_RAM_ADDR 0x80000000
-#define CONFIG_SYS_INIT_RAM_SIZE 0x8000 /* Size of used area in internal SRAM */
-#define CONFIG_SYS_INIT_RAM_CTRL 0x221
-#define CONFIG_SYS_GBL_DATA_OFFSET ((CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) - 32)
-#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
-#define CONFIG_SYS_SBFHDR_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - 32)
-
-/*-----------------------------------------------------------------------
- * Start addresses for the final memory configuration
- * (Set up by the startup code)
- * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
- */
-#define CONFIG_SYS_SDRAM_BASE 0x40000000
-#define CONFIG_SYS_SDRAM_BASE1 0x48000000
-#define CONFIG_SYS_SDRAM_SIZE 256 /* SDRAM size in MB */
-#define CONFIG_SYS_SDRAM_CFG1 0x65311610
-#define CONFIG_SYS_SDRAM_CFG2 0x59670000
-#define CONFIG_SYS_SDRAM_CTRL 0xEA0B2000
-#define CONFIG_SYS_SDRAM_EMOD 0x40010000
-#define CONFIG_SYS_SDRAM_MODE 0x00010033
-#define CONFIG_SYS_SDRAM_DRV_STRENGTH 0xAA
-
-#ifdef CONFIG_CF_SBF
-# define CONFIG_SERIAL_BOOT
-# define CONFIG_SYS_MONITOR_BASE (CONFIG_SYS_TEXT_BASE + 0x400)
-#else
-# define CONFIG_SYS_MONITOR_BASE (CONFIG_SYS_FLASH_BASE + 0x400)
-#endif
-#define CONFIG_SYS_BOOTPARAMS_LEN 64*1024
-#define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */
-
-/* Reserve 256 kB for malloc() */
-#define CONFIG_SYS_MALLOC_LEN (256 << 10)
-
-/*
- * For booting Linux, the board info and command line data
- * have to be in the first 8 MB of memory, since this is
- * the maximum mapped by the Linux kernel during initialization ??
- */
-/* Initial Memory map for Linux */
-#define CONFIG_SYS_BOOTMAPSZ (CONFIG_SYS_SDRAM_BASE + (CONFIG_SYS_SDRAM_SIZE << 20))
-
-/*
- * Configuration for environment
- * Environment is not embedded in u-boot. First time runing may have env
- * crc error warning if there is no correct environment on the flash.
- */
-
-/*-----------------------------------------------------------------------
- * FLASH organization
- */
-#ifdef CONFIG_SYS_STMICRO_BOOT
-# define CONFIG_SYS_FLASH_BASE CONFIG_SYS_CS0_BASE
-# define CONFIG_SYS_FLASH0_BASE CONFIG_SYS_CS1_BASE
-#endif
-#ifdef CONFIG_SYS_ATMEL_BOOT
-# define CONFIG_SYS_FLASH_BASE CONFIG_SYS_CS0_BASE
-# define CONFIG_SYS_FLASH0_BASE CONFIG_SYS_CS0_BASE
-# define CONFIG_SYS_FLASH1_BASE CONFIG_SYS_CS1_BASE
-#endif
-#ifdef CONFIG_SYS_INTEL_BOOT
-# define CONFIG_SYS_FLASH_BASE CONFIG_SYS_CS0_BASE
-# define CONFIG_SYS_FLASH0_BASE CONFIG_SYS_CS0_BASE
-# define CONFIG_SYS_FLASH1_BASE CONFIG_SYS_CS1_BASE
-#endif
-
-#ifdef CONFIG_SYS_FLASH_CFI
-
-# define CONFIG_SYS_FLASH_SIZE 0x1000000 /* Max size that the board might have */
-# define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_8BIT
-# define CONFIG_SYS_MAX_FLASH_BANKS 2 /* max number of memory banks */
-# define CONFIG_SYS_MAX_FLASH_SECT 137 /* max number of sectors on one chip */
-# define CONFIG_SYS_FLASH_CHECKSUM
-# define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_CS0_BASE, CONFIG_SYS_CS1_BASE }
-# define CONFIG_FLASH_CFI_LEGACY
-
-#ifdef CONFIG_FLASH_CFI_LEGACY
-# define CONFIG_SYS_ATMEL_REGION 4
-# define CONFIG_SYS_ATMEL_TOTALSECT 11
-# define CONFIG_SYS_ATMEL_SECT {1, 2, 1, 7}
-# define CONFIG_SYS_ATMEL_SECTSZ {0x4000, 0x2000, 0x8000, 0x10000}
-#endif
-#endif
-
-/*
- * This is setting for JFFS2 support in u-boot.
- * NOTE: Enable CONFIG_CMD_JFFS2 for JFFS2 support.
- */
-#ifdef CONFIG_CMD_JFFS2
-#ifdef CF_STMICRO_BOOT
-# define CONFIG_JFFS2_DEV "nor1"
-# define CONFIG_JFFS2_PART_SIZE 0x01000000
-# define CONFIG_JFFS2_PART_OFFSET (CONFIG_SYS_FLASH2_BASE + 0x500000)
-#endif
-#ifdef CONFIG_SYS_ATMEL_BOOT
-# define CONFIG_JFFS2_DEV "nor1"
-# define CONFIG_JFFS2_PART_SIZE 0x01000000
-# define CONFIG_JFFS2_PART_OFFSET (CONFIG_SYS_FLASH1_BASE + 0x500000)
-#endif
-#ifdef CONFIG_SYS_INTEL_BOOT
-# define CONFIG_JFFS2_DEV "nor0"
-# define CONFIG_JFFS2_PART_SIZE (0x01000000 - 0x500000)
-# define CONFIG_JFFS2_PART_OFFSET (CONFIG_SYS_FLASH0_BASE + 0x500000)
-#endif
-#endif
-
-/*-----------------------------------------------------------------------
- * Cache Configuration
- */
-#define CONFIG_SYS_CACHELINE_SIZE 16
-
-#define ICACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \
- CONFIG_SYS_INIT_RAM_SIZE - 8)
-#define DCACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \
- CONFIG_SYS_INIT_RAM_SIZE - 4)
-#define CONFIG_SYS_ICACHE_INV (CF_CACR_BCINVA + CF_CACR_ICINVA)
-#define CONFIG_SYS_DCACHE_INV (CF_CACR_DCINVA)
-#define CONFIG_SYS_CACHE_ACR2 (CONFIG_SYS_SDRAM_BASE | \
- CF_ADDRMASK(CONFIG_SYS_SDRAM_SIZE) | \
- CF_ACR_EN | CF_ACR_SM_ALL)
-#define CONFIG_SYS_CACHE_ICACR (CF_CACR_BEC | CF_CACR_IEC | \
- CF_CACR_ICINVA | CF_CACR_EUSP)
-#define CONFIG_SYS_CACHE_DCACR ((CONFIG_SYS_CACHE_ICACR | \
- CF_CACR_DEC | CF_CACR_DDCM_P | \
- CF_CACR_DCINVA) & ~CF_CACR_ICINVA)
-
-/*-----------------------------------------------------------------------
- * Memory bank definitions
- */
-/*
- * CS0 - NOR Flash 1, 2, 4, or 8MB
- * CS1 - CompactFlash and registers
- * CS2 - CPLD
- * CS3 - FPGA
- * CS4 - Available
- * CS5 - Available
- */
-
-#if defined(CONFIG_SYS_ATMEL_BOOT) || defined(CONFIG_SYS_STMICRO_BOOT)
- /* Atmel Flash */
-#define CONFIG_SYS_CS0_BASE 0x04000000
-#define CONFIG_SYS_CS0_MASK 0x00070001
-#define CONFIG_SYS_CS0_CTRL 0x00001140
-/* Intel Flash */
-#define CONFIG_SYS_CS1_BASE 0x00000000
-#define CONFIG_SYS_CS1_MASK 0x01FF0001
-#define CONFIG_SYS_CS1_CTRL 0x00000D60
-
-#define CONFIG_SYS_ATMEL_BASE CONFIG_SYS_CS0_BASE
-#else
-/* Intel Flash */
-#define CONFIG_SYS_CS0_BASE 0x00000000
-#define CONFIG_SYS_CS0_MASK 0x01FF0001
-#define CONFIG_SYS_CS0_CTRL 0x00000D60
- /* Atmel Flash */
-#define CONFIG_SYS_CS1_BASE 0x04000000
-#define CONFIG_SYS_CS1_MASK 0x00070001
-#define CONFIG_SYS_CS1_CTRL 0x00001140
-
-#define CONFIG_SYS_ATMEL_BASE CONFIG_SYS_CS1_BASE
-#endif
-
-/* CPLD */
-#define CONFIG_SYS_CS2_BASE 0x08000000
-#define CONFIG_SYS_CS2_MASK 0x00070001
-#define CONFIG_SYS_CS2_CTRL 0x003f1140
-
-/* FPGA */
-#define CONFIG_SYS_CS3_BASE 0x09000000
-#define CONFIG_SYS_CS3_MASK 0x00070001
-#define CONFIG_SYS_CS3_CTRL 0x00000020
-
-#endif /* _M54455EVB_H */
diff --git a/include/configs/ge_bx50v3.h b/include/configs/ge_bx50v3.h
index c8e9d3b..2b61172 100644
--- a/include/configs/ge_bx50v3.h
+++ b/include/configs/ge_bx50v3.h
@@ -33,17 +33,6 @@
#define CONFIG_LBA48
#endif
-/* USB Configs */
-#ifdef CONFIG_USB
-#define CONFIG_USB_MAX_CONTROLLER_COUNT 2
-#define CONFIG_EHCI_HCD_INIT_AFTER_RESET
-#define CONFIG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW)
-#define CONFIG_MXC_USB_FLAGS 0
-
-#define CONFIG_USBD_HS
-#define CONFIG_USB_GADGET_MASS_STORAGE
-#endif
-
/* Serial Flash */
#define CONFIG_LOADADDR 0x12000000
diff --git a/include/configs/gw_ventana.h b/include/configs/gw_ventana.h
index 4f2f323..f80a309 100644
--- a/include/configs/gw_ventana.h
+++ b/include/configs/gw_ventana.h
@@ -38,6 +38,9 @@
/* NAND */
#define CONFIG_SYS_MAX_NAND_DEVICE 1
+#undef CONFIG_SYS_BOOTM_LEN
+#define CONFIG_SYS_BOOTM_LEN (64 << 20)
+
/* I2C Configs */
#define CONFIG_SYS_I2C
#define CONFIG_SYS_I2C_MXC
diff --git a/include/configs/lx2160a_common.h b/include/configs/lx2160a_common.h
index 15ea0e4..1338ee3 100644
--- a/include/configs/lx2160a_common.h
+++ b/include/configs/lx2160a_common.h
@@ -142,7 +142,7 @@
#endif
/* USB */
-#ifdef CONFIG_USB
+#ifdef CONFIG_USB_HOST
#define CONFIG_HAS_FSL_XHCI_USB
#ifndef CONFIG_TARGET_LX2162AQDS
#define CONFIG_USB_MAX_CONTROLLER_COUNT 2
diff --git a/include/configs/phycore_imx8mp.h b/include/configs/phycore_imx8mp.h
index 0490049..75f84e6 100644
--- a/include/configs/phycore_imx8mp.h
+++ b/include/configs/phycore_imx8mp.h
@@ -39,9 +39,10 @@
#define CONFIG_EXTRA_ENV_SETTINGS \
"image=Image\0" \
- "console=ttymxc1,115200\0" \
+ "console=ttymxc0,115200\0" \
"fdt_addr=0x48000000\0" \
"fdt_file=" CONFIG_DEFAULT_FDT_FILE "\0" \
+ "ip_dyn=yes\0" \
"mmcdev=" __stringify(CONFIG_SYS_MMC_ENV_DEV) "\0" \
"mmcpart=" __stringify(CONFIG_SYS_MMC_IMG_LOAD_PART) "\0" \
"mmcroot=2\0" \
@@ -57,6 +58,22 @@
"else " \
"echo WARN: Cannot load the DT; " \
"fi;\0 " \
+ "nfsroot=/nfs\0" \
+ "netargs=setenv bootargs console=${console} root=/dev/nfs ip=dhcp " \
+ "nfsroot=${serverip}:${nfsroot},v3,tcp\0" \
+ "netboot=echo Booting from net ...; " \
+ "run netargs; " \
+ "if test ${ip_dyn} = yes; then " \
+ "setenv get_cmd dhcp; " \
+ "else " \
+ "setenv get_cmd tftp; " \
+ "fi; " \
+ "${get_cmd} ${loadaddr} ${image}; " \
+ "if ${get_cmd} ${fdt_addr} ${fdt_file}; then " \
+ "booti ${loadaddr} - ${fdt_addr}; " \
+ "else " \
+ "echo WARN: Cannot load the DT; " \
+ "fi;\0" \
#define CONFIG_BOOTCOMMAND \
"mmc dev ${mmcdev}; if mmc rescan; then " \
@@ -87,7 +104,7 @@
#define PHYS_SDRAM_SIZE 0x80000000
/* UART */
-#define CONFIG_MXC_UART_BASE UART2_BASE_ADDR
+#define CONFIG_MXC_UART_BASE UART1_BASE_ADDR
/* Monitor Command Prompt */
#define CONFIG_SYS_CBSIZE SZ_2K
diff --git a/include/configs/smegw01.h b/include/configs/smegw01.h
index 50f0013..6f7b46e 100644
--- a/include/configs/smegw01.h
+++ b/include/configs/smegw01.h
@@ -29,11 +29,11 @@
"bootm_size=0x10000000\0" \
"mmcdev=0\0" \
"mmcpart=1\0" \
- "mmcroot=/dev/mmcblk0p2 rootwait rw\0" \
+ "mmcroot=/dev/mmcblk0p1 rootwait rw\0" \
"mmcargs=setenv bootargs console=${console},${baudrate} " \
"root=${mmcroot}\0" \
- "loadimage=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${image}\0" \
- "loadfdt=fatload mmc ${mmcdev}:${mmcpart} ${fdt_addr} ${fdtfile}\0" \
+ "loadimage=load mmc ${mmcdev}:${mmcpart} ${loadaddr} boot/${image}\0" \
+ "loadfdt=load mmc ${mmcdev}:${mmcpart} ${fdt_addr} boot/${fdtfile}\0" \
"mmcboot=echo Booting from mmc ...; " \
"run mmcargs; " \
"if run loadfdt; then " \
diff --git a/include/configs/stm32mp1.h b/include/configs/stm32mp1.h
index 440efa1..b372838 100644
--- a/include/configs/stm32mp1.h
+++ b/include/configs/stm32mp1.h
@@ -101,7 +101,7 @@
#define BOOT_TARGET_UBIFS(func)
#endif
-#ifdef CONFIG_USB
+#ifdef CONFIG_CMD_USB
#define BOOT_TARGET_USB(func) func(USB, usb, 0)
#else
#define BOOT_TARGET_USB(func)
@@ -155,7 +155,7 @@
/*
* memory layout for 32M uncompressed/compressed kernel,
- * 1M fdt, 1M script, 1M pxe and 1M for splashimage
+ * 1M fdt, 1M script, 1M pxe and 1M for overlay
* and the ramdisk at the end.
*/
#define CONFIG_EXTRA_ENV_SETTINGS \
@@ -163,7 +163,7 @@
"fdt_addr_r=0xc4000000\0" \
"scriptaddr=0xc4100000\0" \
"pxefile_addr_r=0xc4200000\0" \
- "splashimage=0xc4300000\0" \
+ "fdtoverlay_addr_r=0xc4300000\0" \
"ramdisk_addr_r=0xc4400000\0" \
"altbootcmd=run bootcmd\0" \
"env_check=if env info -p -d -q; then env save; fi\0" \
diff --git a/include/configs/tegra-common-post.h b/include/configs/tegra-common-post.h
index fae0e76..dd7a75a 100644
--- a/include/configs/tegra-common-post.h
+++ b/include/configs/tegra-common-post.h
@@ -21,11 +21,18 @@
#define CONFIG_SYS_NONCACHED_MEMORY (1 << 20) /* 1 MiB */
#ifndef CONFIG_SPL_BUILD
+
+#if CONFIG_IS_ENABLED(CMD_USB)
+# define BOOT_TARGET_USB(func) func(USB, usb, 0)
+#else
+# define BOOT_TARGET_USB(func)
+#endif
+
#ifndef BOOT_TARGET_DEVICES
#define BOOT_TARGET_DEVICES(func) \
func(MMC, mmc, 1) \
func(MMC, mmc, 0) \
- func(USB, usb, 0) \
+ BOOT_TARGET_USB(func) \
func(PXE, pxe, na) \
func(DHCP, dhcp, na)
#endif
diff --git a/include/configs/topic_miami.h b/include/configs/topic_miami.h
index c12cd7c..b668817 100644
--- a/include/configs/topic_miami.h
+++ b/include/configs/topic_miami.h
@@ -34,7 +34,7 @@
/* Setup proper boot sequences for Miami boards */
-#if defined(CONFIG_USB)
+#if defined(CONFIG_USB_HOST)
# define EXTRA_ENV_USB \
"usbreset=i2c dev 1 && i2c mw 41 1 ff && i2c mw 41 3 fe && "\
"i2c mw 41 1 fe && i2c mw 41 1 ff\0" \
diff --git a/include/dt-bindings/pci/pci.h b/include/dt-bindings/pci/pci.h
new file mode 100644
index 0000000..e729027
--- /dev/null
+++ b/include/dt-bindings/pci/pci.h
@@ -0,0 +1,12 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * This header provides common constants for PCI bindings.
+ */
+
+#ifndef _DT_BINDINGS_PCI_PCI_H
+#define _DT_BINDINGS_PCI_PCI_H
+
+/* Encode a vendor and device ID into a single cell */
+#define PCI_VENDEV(v, d) (((v) << 16) | (d))
+
+#endif /* _DT_BINDINGS_PCI_PCI_H */
diff --git a/include/image.h b/include/image.h
index 0c24bf6..e20f0b6 100644
--- a/include/image.h
+++ b/include/image.h
@@ -30,10 +30,10 @@
#define IMAGE_ENABLE_FIT 1
#define IMAGE_ENABLE_OF_LIBFDT 1
#define CONFIG_FIT_VERBOSE 1 /* enable fit_format_{error,warning}() */
-#define CONFIG_FIT_ENABLE_RSASSA_PSS_SUPPORT 1
-#define CONFIG_FIT_ENABLE_SHA256_SUPPORT
-#define CONFIG_FIT_ENABLE_SHA384_SUPPORT
-#define CONFIG_FIT_ENABLE_SHA512_SUPPORT
+#define CONFIG_FIT_RSASSA_PSS 1
+#define CONFIG_FIT_SHA256
+#define CONFIG_FIT_SHA384
+#define CONFIG_FIT_SHA512
#define CONFIG_SHA1
#define CONFIG_SHA256
#define CONFIG_SHA384
@@ -47,6 +47,7 @@
#include <lmb.h>
#include <asm/u-boot.h>
#include <command.h>
+#include <linker_lists.h>
/* Take notice of the 'ignore' property for hashes */
#define IMAGE_ENABLE_IGNORE 1
@@ -62,19 +63,15 @@
#include <linux/libfdt.h>
#include <fdt_support.h>
# ifdef CONFIG_SPL_BUILD
-# ifdef CONFIG_SPL_CRC32_SUPPORT
+# ifdef CONFIG_SPL_CRC32
# define IMAGE_ENABLE_CRC32 1
# endif
-# ifdef CONFIG_SPL_MD5_SUPPORT
+# ifdef CONFIG_SPL_MD5
# define IMAGE_ENABLE_MD5 1
# endif
-# ifdef CONFIG_SPL_SHA1_SUPPORT
-# define IMAGE_ENABLE_SHA1 1
-# endif
# else
# define IMAGE_ENABLE_CRC32 1
# define IMAGE_ENABLE_MD5 1
-# define IMAGE_ENABLE_SHA1 1
# endif
#ifndef IMAGE_ENABLE_CRC32
@@ -85,31 +82,6 @@
#define IMAGE_ENABLE_MD5 0
#endif
-#ifndef IMAGE_ENABLE_SHA1
-#define IMAGE_ENABLE_SHA1 0
-#endif
-
-#if defined(CONFIG_FIT_ENABLE_SHA256_SUPPORT) || \
- defined(CONFIG_SPL_SHA256_SUPPORT)
-#define IMAGE_ENABLE_SHA256 1
-#else
-#define IMAGE_ENABLE_SHA256 0
-#endif
-
-#if defined(CONFIG_FIT_ENABLE_SHA384_SUPPORT) || \
- defined(CONFIG_SPL_SHA384_SUPPORT)
-#define IMAGE_ENABLE_SHA384 1
-#else
-#define IMAGE_ENABLE_SHA384 0
-#endif
-
-#if defined(CONFIG_FIT_ENABLE_SHA512_SUPPORT) || \
- defined(CONFIG_SPL_SHA512_SUPPORT)
-#define IMAGE_ENABLE_SHA512 1
-#else
-#define IMAGE_ENABLE_SHA512 0
-#endif
-
#endif /* IMAGE_ENABLE_FIT */
#ifdef CONFIG_SYS_BOOT_GET_CMDLINE
@@ -1224,20 +1196,14 @@
#if defined(USE_HOSTCC)
# if defined(CONFIG_FIT_SIGNATURE)
# define IMAGE_ENABLE_SIGN 1
-# define IMAGE_ENABLE_VERIFY 1
-# define IMAGE_ENABLE_VERIFY_ECDSA 1
# define FIT_IMAGE_ENABLE_VERIFY 1
# include <openssl/evp.h>
# else
# define IMAGE_ENABLE_SIGN 0
-# define IMAGE_ENABLE_VERIFY 0
-# define IMAGE_ENABLE_VERIFY_ECDSA 0
# define FIT_IMAGE_ENABLE_VERIFY 0
# endif
#else
# define IMAGE_ENABLE_SIGN 0
-# define IMAGE_ENABLE_VERIFY CONFIG_IS_ENABLED(RSA_VERIFY)
-# define IMAGE_ENABLE_VERIFY_ECDSA 0
# define FIT_IMAGE_ENABLE_VERIFY CONFIG_IS_ENABLED(FIT_SIGNATURE)
#endif
@@ -1250,11 +1216,6 @@
# define gd_fdt_blob() (gd->fdt_blob)
#endif
-#ifdef CONFIG_FIT_BEST_MATCH
-#define IMAGE_ENABLE_BEST_MATCH 1
-#else
-#define IMAGE_ENABLE_BEST_MATCH 0
-#endif
#endif /* IMAGE_ENABLE_FIT */
/*
@@ -1293,7 +1254,7 @@
int size;
};
-#if IMAGE_ENABLE_VERIFY
+#if FIT_IMAGE_ENABLE_VERIFY
# include <u-boot/hash-checksum.h>
#endif
struct checksum_algo {
@@ -1362,6 +1323,10 @@
uint8_t *sig, uint sig_len);
};
+/* Declare a new U-Boot crypto algorithm handler */
+#define U_BOOT_CRYPTO_ALGO(__name) \
+ll_entry_declare(struct crypto_algo, __name, cryptos)
+
struct padding_algo {
const char *name;
int (*verify)(struct image_sign_info *info,
diff --git a/include/mmc.h b/include/mmc.h
index 6f943e7..0bf19de 100644
--- a/include/mmc.h
+++ b/include/mmc.h
@@ -900,9 +900,10 @@
* the presence of SD/eMMC when no card detect logic is available.
*
* @param mmc Pointer to a MMC device struct
+ * @param quiet Be quiet, do not print error messages when card is not detected.
* @return 0 on success, <0 on error.
*/
-int mmc_get_op_cond(struct mmc *mmc);
+int mmc_get_op_cond(struct mmc *mmc, bool quiet);
/**
* Start device initialization and return immediately; it does not block on
diff --git a/include/net.h b/include/net.h
index b95d6a6..cec8c98 100644
--- a/include/net.h
+++ b/include/net.h
@@ -158,6 +158,7 @@
* ROM on the board. This is how the driver should expose it
* to the network stack. This function should fill in the
* eth_pdata::enetaddr field - optional
+ * set_promisc: Enable or Disable promiscuous mode
*/
struct eth_ops {
int (*start)(struct udevice *dev);
@@ -168,6 +169,7 @@
int (*mcast)(struct udevice *dev, const u8 *enetaddr, int join);
int (*write_hwaddr)(struct udevice *dev);
int (*read_rom_hwaddr)(struct udevice *dev);
+ int (*set_promisc)(struct udevice *dev, bool enable);
};
#define eth_get_ops(dev) ((struct eth_ops *)(dev)->driver->ops)
diff --git a/include/pci.h b/include/pci.h
index 8e62235..258c8f8 100644
--- a/include/pci.h
+++ b/include/pci.h
@@ -578,7 +578,6 @@
#define PCI_MASK_BUS(bdf) ((bdf) & 0xffff)
#define PCI_ADD_BUS(bus, devfn) (((bus) << 16) | (devfn))
#define PCI_BDF(b, d, f) ((b) << 16 | PCI_DEVFN(d, f))
-#define PCI_VENDEV(v, d) (((v) << 16) | (d))
#define PCI_ANY_ID (~0)
/* Convert from Linux format to U-Boot format */
@@ -1064,7 +1063,7 @@
* @devp: Returns matching device if found
* @return 0 if found, -ENODEV if not
*/
-int pci_bus_find_devices(struct udevice *bus, struct pci_device_id *ids,
+int pci_bus_find_devices(struct udevice *bus, const struct pci_device_id *ids,
int *indexp, struct udevice **devp);
/**
@@ -1076,7 +1075,7 @@
* @devp: Returns matching device if found
* @return 0 if found, -ENODEV if not
*/
-int pci_find_device_id(struct pci_device_id *ids, int index,
+int pci_find_device_id(const struct pci_device_id *ids, int index,
struct udevice **devp);
/**
diff --git a/include/spl.h b/include/spl.h
index cee9a42..c643943 100644
--- a/include/spl.h
+++ b/include/spl.h
@@ -357,6 +357,29 @@
* If not overridden, it is weakly defined in common/spl/spl_mmc.c.
*/
int spl_mmc_boot_partition(const u32 boot_device);
+
+struct mmc;
+/**
+ * default_spl_mmc_emmc_boot_partition() - eMMC boot partition to load U-Boot from.
+ * mmc: Pointer for the mmc device structure
+ *
+ * This function should return the eMMC boot partition number which
+ * the SPL should load U-Boot from (on the given boot_device).
+ */
+int default_spl_mmc_emmc_boot_partition(struct mmc *mmc);
+
+/**
+ * spl_mmc_emmc_boot_partition() - eMMC boot partition to load U-Boot from.
+ * mmc: Pointer for the mmc device structure
+ *
+ * This function should return the eMMC boot partition number which
+ * the SPL should load U-Boot from (on the given boot_device).
+ *
+ * If not overridden, it is weakly defined in common/spl/spl_mmc.c
+ * and calls default_spl_mmc_emmc_boot_partition();
+ */
+int spl_mmc_emmc_boot_partition(struct mmc *mmc);
+
void spl_set_bd(void);
/**
diff --git a/include/u-boot/ecdsa.h b/include/u-boot/ecdsa.h
index 979690d..f6951c7 100644
--- a/include/u-boot/ecdsa.h
+++ b/include/u-boot/ecdsa.h
@@ -15,7 +15,6 @@
* @see "struct crypto_algo"
* @{
*/
-#if IMAGE_ENABLE_SIGN
/**
* sign() - calculate and return signature for given input data
*
@@ -49,22 +48,7 @@
* other -ve value on error
*/
int ecdsa_add_verify_data(struct image_sign_info *info, void *keydest);
-#else
-static inline
-int ecdsa_sign(struct image_sign_info *info, const struct image_region region[],
- int region_count, uint8_t **sigp, uint *sig_len)
-{
- return -ENXIO;
-}
-
-static inline
-int ecdsa_add_verify_data(struct image_sign_info *info, void *keydest)
-{
- return -ENXIO;
-}
-#endif
-#if IMAGE_ENABLE_VERIFY_ECDSA
/**
* verify() - Verify a signature against some data
*
@@ -78,15 +62,6 @@
int ecdsa_verify(struct image_sign_info *info,
const struct image_region region[], int region_count,
uint8_t *sig, uint sig_len);
-#else
-static inline
-int ecdsa_verify(struct image_sign_info *info,
- const struct image_region region[], int region_count,
- uint8_t *sig, uint sig_len)
-{
- return -ENXIO;
-}
-#endif
/** @} */
#define ECDSA256_BYTES (256 / 8)
diff --git a/include/u-boot/rsa.h b/include/u-boot/rsa.h
index bed1c09..89a9c4c 100644
--- a/include/u-boot/rsa.h
+++ b/include/u-boot/rsa.h
@@ -31,7 +31,6 @@
struct image_sign_info;
-#if IMAGE_ENABLE_SIGN
/**
* sign() - calculate and return signature for given input data
*
@@ -66,22 +65,7 @@
other -ve value on error
*/
int rsa_add_verify_data(struct image_sign_info *info, void *keydest);
-#else
-static inline int rsa_sign(struct image_sign_info *info,
- const struct image_region region[], int region_count,
- uint8_t **sigp, uint *sig_len)
-{
- return -ENXIO;
-}
-static inline int rsa_add_verify_data(struct image_sign_info *info,
- void *keydest)
-{
- return -ENXIO;
-}
-#endif
-
-#if IMAGE_ENABLE_VERIFY
/**
* rsa_verify_hash() - Verify a signature against a hash
*
@@ -119,42 +103,11 @@
uint8_t *msg, int msg_len,
const uint8_t *hash, int hash_len);
-#ifdef CONFIG_FIT_ENABLE_RSASSA_PSS_SUPPORT
+#ifdef CONFIG_FIT_RSASSA_PSS
int padding_pss_verify(struct image_sign_info *info,
uint8_t *msg, int msg_len,
const uint8_t *hash, int hash_len);
-#endif /* CONFIG_FIT_ENABLE_RSASSA_PSS_SUPPORT */
-#else
-static inline int rsa_verify_hash(struct image_sign_info *info,
- const uint8_t *hash,
- uint8_t *sig, uint sig_len)
-{
- return -ENXIO;
-}
-
-static inline int rsa_verify(struct image_sign_info *info,
- const struct image_region region[], int region_count,
- uint8_t *sig, uint sig_len)
-{
- return -ENXIO;
-}
-
-static inline int padding_pkcs_15_verify(struct image_sign_info *info,
- uint8_t *msg, int msg_len,
- const uint8_t *hash, int hash_len)
-{
- return -ENXIO;
-}
-
-#ifdef CONFIG_FIT_ENABLE_RSASSA_PSS_SUPPORT
-static inline int padding_pss_verify(struct image_sign_info *info,
- uint8_t *msg, int msg_len,
- const uint8_t *hash, int hash_len)
-{
- return -ENXIO;
-}
-#endif /* CONFIG_FIT_ENABLE_RSASSA_PSS_SUPPORT */
-#endif
+#endif /* CONFIG_FIT_RSASSA_PSS */
#define RSA_DEFAULT_PADDING_NAME "pkcs-1.5"
diff --git a/lib/efi_loader/Kconfig b/lib/efi_loader/Kconfig
index 156b391..dacc3b5 100644
--- a/lib/efi_loader/Kconfig
+++ b/lib/efi_loader/Kconfig
@@ -12,6 +12,7 @@
depends on !EFI_STUB || !X86 || X86_64 || EFI_STUB_32BIT
default y if !ARM || SYS_CPU = armv7 || SYS_CPU = armv8
select LIB_UUID
+ select PARTITION_UUIDS
select HAVE_BLOCK_DEVICE
select REGEX
imply CFB_CONSOLE_ANSI
@@ -213,6 +214,13 @@
Select this option if you want to enable capsule
authentication
+config EFI_CAPSULE_KEY_PATH
+ string "Path to .esl cert for capsule authentication"
+ depends on EFI_CAPSULE_AUTHENTICATE
+ help
+ Provide the EFI signature list (esl) certificate used for capsule
+ authentication
+
config EFI_DEVICE_PATH_TO_TEXT
bool "Device path to text protocol"
default y
@@ -326,7 +334,7 @@
config EFI_TCG2_PROTOCOL_EVENTLOG_SIZE
int "EFI_TCG2_PROTOCOL EventLog size"
depends on EFI_TCG2_PROTOCOL
- default 4096
+ default 65536
help
Define the size of the EventLog for EFI_TCG2_PROTOCOL. Note that
this is going to be allocated twice. One for the eventlog it self
diff --git a/lib/efi_loader/Makefile b/lib/efi_loader/Makefile
index fd344ce..9b36943 100644
--- a/lib/efi_loader/Makefile
+++ b/lib/efi_loader/Makefile
@@ -20,11 +20,19 @@
targets += helloworld.o
endif
+ifeq ($(CONFIG_EFI_CAPSULE_AUTHENTICATE),y)
+EFI_CAPSULE_KEY_PATH := $(subst $\",,$(CONFIG_EFI_CAPSULE_KEY_PATH))
+ifeq ("$(wildcard $(EFI_CAPSULE_KEY_PATH))","")
+$(error .esl cerificate not found. Configure your CONFIG_EFI_CAPSULE_KEY_PATH)
+endif
+endif
+
obj-$(CONFIG_CMD_BOOTEFI_HELLO) += helloworld_efi.o
obj-$(CONFIG_CMD_BOOTEFI_BOOTMGR) += efi_bootmgr.o
obj-y += efi_boottime.o
obj-y += efi_helper.o
obj-$(CONFIG_EFI_HAVE_CAPSULE_SUPPORT) += efi_capsule.o
+obj-$(CONFIG_EFI_CAPSULE_AUTHENTICATE) += efi_capsule_key.o
obj-$(CONFIG_EFI_CAPSULE_FIRMWARE) += efi_firmware.o
obj-y += efi_console.o
obj-y += efi_device_path.o
diff --git a/lib/efi_loader/efi_capsule.c b/lib/efi_loader/efi_capsule.c
index b878e71..f9b0ef5 100644
--- a/lib/efi_loader/efi_capsule.c
+++ b/lib/efi_loader/efi_capsule.c
@@ -16,6 +16,7 @@
#include <mapmem.h>
#include <sort.h>
+#include <asm/sections.h>
#include <crypto/pkcs7.h>
#include <crypto/pkcs7_parser.h>
#include <linux/err.h>
@@ -222,12 +223,23 @@
const efi_guid_t efi_guid_capsule_root_cert_guid =
EFI_FIRMWARE_MANAGEMENT_CAPSULE_ID_GUID;
+static int efi_get_public_key_data(void **pkey, efi_uintn_t *pkey_len)
+{
+ const void *blob = __efi_capsule_sig_begin;
+ const int len = __efi_capsule_sig_end - __efi_capsule_sig_begin;
+
+ *pkey = (void *)blob;
+ *pkey_len = len;
+
+ return 0;
+}
+
efi_status_t efi_capsule_authenticate(const void *capsule, efi_uintn_t capsule_size,
void **image, efi_uintn_t *image_size)
{
u8 *buf;
int ret;
- void *fdt_pkey, *pkey;
+ void *stored_pkey, *pkey;
efi_uintn_t pkey_len;
uint64_t monotonic_count;
struct efi_signature_store *truststore;
@@ -286,7 +298,7 @@
goto out;
}
- ret = efi_get_public_key_data(&fdt_pkey, &pkey_len);
+ ret = efi_get_public_key_data(&stored_pkey, &pkey_len);
if (ret < 0)
goto out;
@@ -294,7 +306,7 @@
if (!pkey)
goto out;
- memcpy(pkey, fdt_pkey, pkey_len);
+ memcpy(pkey, stored_pkey, pkey_len);
truststore = efi_build_signature_store(pkey, pkey_len);
if (!truststore)
goto out;
@@ -691,11 +703,7 @@
}
found:
if (boot_dev) {
- u16 *path_str;
-
- path_str = efi_dp_str(boot_dev);
- log_debug("Boot device %ls\n", path_str);
- efi_free_pool(path_str);
+ log_debug("Boot device %pD\n", boot_dev);
volume = efi_fs_from_path(boot_dev);
if (!volume)
diff --git a/lib/efi_loader/efi_capsule_key.S b/lib/efi_loader/efi_capsule_key.S
new file mode 100644
index 0000000..58f00b8
--- /dev/null
+++ b/lib/efi_loader/efi_capsule_key.S
@@ -0,0 +1,17 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * .esl cert for capsule authentication
+ *
+ * Copyright (c) 2021, Ilias Apalodimas <ilias.apalodimas@linaro.org>
+ */
+
+#include <config.h>
+
+.section .rodata.capsule_key.init,"a"
+.balign 16
+.global __efi_capsule_sig_begin
+__efi_capsule_sig_begin:
+.incbin CONFIG_EFI_CAPSULE_KEY_PATH
+__efi_capsule_sig_end:
+.global __efi_capsule_sig_end
+.balign 16
diff --git a/lib/efi_loader/efi_device_path.c b/lib/efi_loader/efi_device_path.c
index 76c2f82..9c3ac71 100644
--- a/lib/efi_loader/efi_device_path.c
+++ b/lib/efi_loader/efi_device_path.c
@@ -5,6 +5,8 @@
* (C) Copyright 2017 Rob Clark
*/
+#define LOG_CATEGORY LOGC_EFI
+
#include <common.h>
#include <blk.h>
#include <dm.h>
@@ -16,6 +18,7 @@
#include <efi_loader.h>
#include <part.h>
#include <sandboxblockdev.h>
+#include <uuid.h>
#include <asm-generic/unaligned.h>
#include <linux/compat.h> /* U16_MAX */
@@ -851,8 +854,11 @@
break;
case SIG_TYPE_GUID:
hddp->signature_type = 2;
- memcpy(hddp->partition_signature, &desc->guid_sig,
- sizeof(hddp->partition_signature));
+ if (uuid_str_to_bin(info.uuid,
+ hddp->partition_signature, 1))
+ log_warning(
+ "Partition no. %d: invalid guid: %s\n",
+ part, info.uuid);
break;
}
diff --git a/lib/rsa/rsa-sign.c b/lib/rsa/rsa-sign.c
index 5a1583b..f4ed11e 100644
--- a/lib/rsa/rsa-sign.c
+++ b/lib/rsa/rsa-sign.c
@@ -442,7 +442,7 @@
goto err_sign;
}
-#ifdef CONFIG_FIT_ENABLE_RSASSA_PSS_SUPPORT
+#ifdef CONFIG_FIT_RSASSA_PSS
if (padding_algo && !strcmp(padding_algo->name, "pss")) {
if (EVP_PKEY_CTX_set_rsa_padding(ckey,
RSA_PKCS1_PSS_PADDING) <= 0) {
@@ -450,7 +450,7 @@
goto err_sign;
}
}
-#endif /* CONFIG_FIT_ENABLE_RSASSA_PSS_SUPPORT */
+#endif /* CONFIG_FIT_RSASSA_PSS */
for (i = 0; i < region_count; i++) {
if (!EVP_DigestSignUpdate(context, region[i].data,
diff --git a/lib/rsa/rsa-verify.c b/lib/rsa/rsa-verify.c
index aee76f4..bb8cc61 100644
--- a/lib/rsa/rsa-verify.c
+++ b/lib/rsa/rsa-verify.c
@@ -95,7 +95,7 @@
return 0;
}
-#ifdef CONFIG_FIT_ENABLE_RSASSA_PSS_SUPPORT
+#ifdef CONFIG_FIT_RSASSA_PSS
static void u32_i2osp(uint32_t val, uint8_t *buf)
{
buf[0] = (uint8_t)((val >> 24) & 0xff);
@@ -571,3 +571,19 @@
return rsa_verify_hash(info, hash, sig, sig_len);
}
+
+#ifndef USE_HOSTCC
+
+U_BOOT_CRYPTO_ALGO(rsa2048) = {
+ .name = "rsa2048",
+ .key_len = RSA2048_BYTES,
+ .verify = rsa_verify,
+};
+
+U_BOOT_CRYPTO_ALGO(rsa4096) = {
+ .name = "rsa4096",
+ .key_len = RSA4096_BYTES,
+ .verify = rsa_verify,
+};
+
+#endif
diff --git a/lib/tpm-common.c b/lib/tpm-common.c
index 4277846..82ffdc5 100644
--- a/lib/tpm-common.c
+++ b/lib/tpm-common.c
@@ -176,6 +176,11 @@
}
size = tpm_command_size(command);
+
+ /* sanity check, which also helps coverity */
+ if (size > COMMAND_BUFFER_SIZE)
+ return log_msg_ret("size", -E2BIG);
+
log_debug("TPM request [size:%d]: ", size);
for (i = 0; i < size; i++)
log_debug("%02x ", ((u8 *)command)[i]);
diff --git a/lib/vsprintf.c b/lib/vsprintf.c
index 9dc96c8..c14176dd 100644
--- a/lib/vsprintf.c
+++ b/lib/vsprintf.c
@@ -434,9 +434,9 @@
* - 'i' [46] for 'raw' IPv4/IPv6 addresses, IPv6 omits the colons, IPv4 is
* currently the same
*
- * Note: The difference between 'S' and 'F' is that on ia64 and ppc64
- * function pointers are really function descriptors, which contain a
- * pointer to the real address.
+ * Note: IPv6 support is currently if(0)'ed out. If you ever need
+ * %pI6, please add an IPV6 Kconfig knob, make your code select or
+ * depend on that, and change the 0 below to CONFIG_IS_ENABLED(IPV6).
*/
static char *pointer(const char *fmt, char *buf, char *end, void *ptr,
int field_width, int precision, int flags)
@@ -481,7 +481,8 @@
flags |= SPECIAL;
/* Fallthrough */
case 'I':
- if (fmt[1] == '6')
+ /* %pI6 currently unused */
+ if (0 && fmt[1] == '6')
return ip6_addr_string(buf, end, ptr, field_width,
precision, flags);
if (fmt[1] == '4')
@@ -787,22 +788,11 @@
{
va_list args;
uint i;
- char printbuffer[CONFIG_SYS_PBSIZE];
va_start(args, fmt);
-
- /*
- * For this to work, printbuffer must be larger than
- * anything we ever want to print.
- */
- i = vscnprintf(printbuffer, sizeof(printbuffer), fmt, args);
+ i = vprintf(fmt, args);
va_end(args);
- /* Handle error */
- if (i <= 0)
- return i;
- /* Print the string */
- puts(printbuffer);
return i;
}
diff --git a/net/dsa-uclass.c b/net/dsa-uclass.c
index 7ea1cb6..694664d 100644
--- a/net/dsa-uclass.c
+++ b/net/dsa-uclass.c
@@ -277,8 +277,15 @@
* has a unique MAC address specified in the environment.
*/
eth_env_get_enetaddr_by_index("eth", dev_seq(pdev), env_enetaddr);
- if (!is_zero_ethaddr(env_enetaddr))
+ if (!is_zero_ethaddr(env_enetaddr)) {
+ /* individual port mac addrs require master to be promisc */
+ struct eth_ops *eth_ops = eth_get_ops(master);
+
+ if (eth_ops->set_promisc)
+ eth_ops->set_promisc(master, 1);
+
return 0;
+ }
master_pdata = dev_get_plat(master);
eth_pdata = dev_get_plat(pdev);
diff --git a/test/cmd/setexpr.c b/test/cmd/setexpr.c
index c537e89..08b6e6e 100644
--- a/test/cmd/setexpr.c
+++ b/test/cmd/setexpr.c
@@ -270,8 +270,6 @@
ut_asserteq_str("us this is surely! a test is it? yes us this is indeed! a test",
buf);
- /* The following checks fail at present due to a bug in setexpr */
- return 0;
for (i = BUF_SIZE; i < 0x1000; i++) {
ut_assertf(buf[i] == (char)i,
"buf byte at %x should be %02x, got %02x)\n",
diff --git a/tools/Kconfig b/tools/Kconfig
index b2f5012..d6f82cd 100644
--- a/tools/Kconfig
+++ b/tools/Kconfig
@@ -9,4 +9,15 @@
some cases the system dtc may not support all required features
and the path to a different version should be given here.
+config TOOLS_LIBCRYPTO
+ bool "Use OpenSSL's libcrypto library for host tools"
+ default y
+ help
+ Cryptographic signature, verification, and encryption of images is
+ provided by host tools using OpenSSL's libcrypto. Select 'n' here if
+ you wish to build host tools without OpenSSL. mkimage will not have
+ the ability to sign images.
+ This selection does not affect target features, such as runtime FIT
+ signature verification.
+
endmenu
diff --git a/tools/Makefile b/tools/Makefile
index d020c55..bae3f95 100644
--- a/tools/Makefile
+++ b/tools/Makefile
@@ -3,6 +3,25 @@
# (C) Copyright 2000-2006
# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+# A note on target vs host configuration:
+#
+# Host tools can be used across multiple targets, or different configurations
+# of the same target. Thus, host tools must be able to handle any combination
+# of target configurations. To prevent having different variations of the same
+# tool, the tool build options may not depend on target configuration.
+#
+# Some linux distributions package these utilities as u-boot-tools, and it
+# would be unmaintainable to have a different tool variation for each
+# arch or configuration.
+#
+# A couple of simple rules:
+#
+# 1) Do not use target CONFIG_* options to enable or disable features in host
+# tools. Only use the configs from tools/Kconfig
+# 2) It's okay to use target configs to disable building specific tools.
+# That's as long as the features of those tools aren't modified.
+#
+
# Enable all the config-independent tools
ifneq ($(HOST_TOOLS_ALL),)
CONFIG_ARCH_KIRKWOOD = y
@@ -53,30 +72,30 @@
mkenvimage-objs := mkenvimage.o os_support.o lib/crc32.o
hostprogs-y += dumpimage mkimage
-hostprogs-$(CONFIG_FIT_SIGNATURE) += fit_info fit_check_sign
+hostprogs-$(CONFIG_TOOLS_LIBCRYPTO) += fit_info fit_check_sign
hostprogs-$(CONFIG_CMD_BOOTEFI_SELFTEST) += file2include
-FIT_OBJS-$(CONFIG_FIT) := fit_common.o fit_image.o image-host.o common/image-fit.o
-FIT_SIG_OBJS-$(CONFIG_FIT_SIGNATURE) := common/image-sig.o common/image-fit-sig.o
-FIT_CIPHER_OBJS-$(CONFIG_FIT_CIPHER) := common/image-cipher.o
+FIT_OBJS-y := fit_common.o fit_image.o image-host.o common/image-fit.o
+FIT_SIG_OBJS-$(CONFIG_TOOLS_LIBCRYPTO) := image-sig-host.o common/image-fit-sig.o
+FIT_CIPHER_OBJS-$(CONFIG_TOOLS_LIBCRYPTO) := common/image-cipher.o
# The following files are synced with upstream DTC.
# Use synced versions from scripts/dtc/libfdt/.
LIBFDT_OBJS := $(addprefix libfdt/, fdt.o fdt_ro.o fdt_wip.o fdt_sw.o fdt_rw.o \
fdt_strerror.o fdt_empty_tree.o fdt_addresses.o fdt_overlay.o)
-RSA_OBJS-$(CONFIG_FIT_SIGNATURE) := $(addprefix lib/rsa/, \
+RSA_OBJS-$(CONFIG_TOOLS_LIBCRYPTO) := $(addprefix lib/rsa/, \
rsa-sign.o rsa-verify.o \
rsa-mod-exp.o)
-ECDSA_OBJS-$(CONFIG_FIT_SIGNATURE) := $(addprefix lib/ecdsa/, ecdsa-libcrypto.o)
+ECDSA_OBJS-$(CONFIG_TOOLS_LIBCRYPTO) := $(addprefix lib/ecdsa/, ecdsa-libcrypto.o)
-AES_OBJS-$(CONFIG_FIT_CIPHER) := $(addprefix lib/aes/, \
+AES_OBJS-$(CONFIG_TOOLS_LIBCRYPTO) := $(addprefix lib/aes/, \
aes-encrypt.o aes-decrypt.o)
# Cryptographic helpers that depend on openssl/libcrypto
-LIBCRYPTO_OBJS-$(CONFIG_FIT_SIGNATURE) := $(addprefix lib/, \
+LIBCRYPTO_OBJS-$(CONFIG_TOOLS_LIBCRYPTO) := $(addprefix lib/, \
fdt-libcrypto.o)
ROCKCHIP_OBS = lib/rc4.o rkcommon.o rkimage.o rksd.o rkspi.o
@@ -136,22 +155,17 @@
fit_check_sign-objs := $(dumpimage-mkimage-objs) fit_check_sign.o
file2include-objs := file2include.o
-ifneq ($(CONFIG_MX23)$(CONFIG_MX28)$(CONFIG_FIT_SIGNATURE),)
+ifneq ($(CONFIG_MX23)$(CONFIG_MX28)$(CONFIG_TOOLS_LIBCRYPTO),)
# Add CONFIG_MXS into host CFLAGS, so we can check whether or not register
# the mxsimage support within tools/mxsimage.c .
HOSTCFLAGS_mxsimage.o += -DCONFIG_MXS
endif
-ifdef CONFIG_FIT_SIGNATURE
+ifdef CONFIG_TOOLS_LIBCRYPTO
# This affects include/image.h, but including the board config file
# is tricky, so manually define this options here.
HOST_EXTRACFLAGS += -DCONFIG_FIT_SIGNATURE
-HOST_EXTRACFLAGS += -DCONFIG_FIT_SIGNATURE_MAX_SIZE=$(CONFIG_FIT_SIGNATURE_MAX_SIZE)
-endif
-
-ifdef CONFIG_FIT_CIPHER
-# This affects include/image.h, but including the board config file
-# is tricky, so manually define this options here.
+HOST_EXTRACFLAGS += -DCONFIG_FIT_SIGNATURE_MAX_SIZE=0xffffffff
HOST_EXTRACFLAGS += -DCONFIG_FIT_CIPHER
endif
@@ -164,7 +178,7 @@
endif
# MXSImage needs LibSSL
-ifneq ($(CONFIG_MX23)$(CONFIG_MX28)$(CONFIG_ARMADA_38X)$(CONFIG_FIT_SIGNATURE)$(CONFIG_FIT_CIPHER),)
+ifneq ($(CONFIG_MX23)$(CONFIG_MX28)$(CONFIG_ARMADA_38X)$(CONFIG_TOOLS_LIBCRYPTO),)
HOSTCFLAGS_kwbimage.o += \
$(shell pkg-config --cflags libssl libcrypto 2> /dev/null || echo "")
HOSTLDLIBS_mkimage += \
diff --git a/tools/dtoc/dtb_platdata.py b/tools/dtoc/dtb_platdata.py
index 2d42480..869c92b 100644
--- a/tools/dtoc/dtb_platdata.py
+++ b/tools/dtoc/dtb_platdata.py
@@ -749,6 +749,15 @@
break
if node.parent and node.parent.parent:
+ if node.parent not in self._valid_nodes:
+ # This might indicate that the parent node is not in the
+ # SPL/TPL devicetree but the child is. For example if we are
+ # dealing with of-platdata in TPL, the parent has a
+ # u-boot,dm-tpl tag but the child has u-boot,dm-pre-reloc. In
+ # this case the child node exists in TPL but the parent does
+ # not.
+ raise ValueError("Node '%s' requires parent node '%s' but it is not in the valid list" %
+ (node.path, node.parent.path))
self.buf('\t.parent\t\t= DM_DEVICE_REF(%s),\n' %
node.parent.var_name)
if priv_name:
diff --git a/tools/dtoc/test/dtoc_test_noparent.dts b/tools/dtoc/test/dtoc_test_noparent.dts
new file mode 100644
index 0000000..e976dd2
--- /dev/null
+++ b/tools/dtoc/test/dtoc_test_noparent.dts
@@ -0,0 +1,32 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Test device tree file for dtoc
+ *
+ * Copyright 2017 Google, Inc
+ */
+
+/dts-v1/;
+
+/ {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ i2c@0 {
+ compatible = "sandbox,i2c";
+ u-boot,dm-tpl;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ spl-test {
+ u-boot,dm-pre-reloc;
+ compatible = "sandbox,spl-test";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+ pmic@9 {
+ compatible = "sandbox,pmic";
+ u-boot,dm-pre-reloc;
+ reg = <9>;
+ low-power;
+ };
+ };
+ };
+};
diff --git a/tools/dtoc/test_dtoc.py b/tools/dtoc/test_dtoc.py
index 0b2805f..863ede9 100755
--- a/tools/dtoc/test_dtoc.py
+++ b/tools/dtoc/test_dtoc.py
@@ -1830,3 +1830,13 @@
dtb_file = get_dtb_file('dtoc_test_single_reg.dts')
output = tools.GetOutputFilename('output')
self.run_test(['struct'], dtb_file, output)
+
+ def test_missing_parent(self):
+ """Test detection of a parent node with no properties"""
+ dtb_file = get_dtb_file('dtoc_test_noparent.dts', capture_stderr=True)
+ output = tools.GetOutputFilename('output')
+ with self.assertRaises(ValueError) as exc:
+ self.run_test(['device'], dtb_file, output, instantiate=True)
+ self.assertIn("Node '/i2c@0/spl-test/pmic@9' requires parent node "
+ "'/i2c@0/spl-test' but it is not in the valid list",
+ str(exc.exception))
diff --git a/tools/image-host.c b/tools/image-host.c
index 7309546..d3a882e 100644
--- a/tools/image-host.c
+++ b/tools/image-host.c
@@ -329,7 +329,7 @@
{
unsigned char *tmp = data;
struct timespec date;
- int i, ret = 0;
+ int i, ret;
if (!tmp) {
printf("%s: pointer data is NULL\n", __func__);
@@ -338,9 +338,9 @@
}
ret = clock_gettime(CLOCK_MONOTONIC, &date);
- if (ret < 0) {
- printf("%s: clock_gettime has failed (err=%d, str=%s)\n",
- __func__, ret, strerror(errno));
+ if (ret) {
+ printf("%s: clock_gettime has failed (%s)\n", __func__,
+ strerror(errno));
goto out;
}
diff --git a/tools/image-sig-host.c b/tools/image-sig-host.c
new file mode 100644
index 0000000..8ed6998
--- /dev/null
+++ b/tools/image-sig-host.c
@@ -0,0 +1,133 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (c) 2013, Google Inc.
+ */
+
+#include "mkimage.h"
+#include <fdt_support.h>
+#include <time.h>
+#include <linux/libfdt.h>
+#include <image.h>
+#include <u-boot/ecdsa.h>
+#include <u-boot/rsa.h>
+#include <u-boot/hash-checksum.h>
+
+struct checksum_algo checksum_algos[] = {
+ {
+ .name = "sha1",
+ .checksum_len = SHA1_SUM_LEN,
+ .der_len = SHA1_DER_LEN,
+ .der_prefix = sha1_der_prefix,
+ .calculate_sign = EVP_sha1,
+ .calculate = hash_calculate,
+ },
+ {
+ .name = "sha256",
+ .checksum_len = SHA256_SUM_LEN,
+ .der_len = SHA256_DER_LEN,
+ .der_prefix = sha256_der_prefix,
+ .calculate_sign = EVP_sha256,
+ .calculate = hash_calculate,
+ },
+ {
+ .name = "sha384",
+ .checksum_len = SHA384_SUM_LEN,
+ .der_len = SHA384_DER_LEN,
+ .der_prefix = sha384_der_prefix,
+ .calculate_sign = EVP_sha384,
+ .calculate = hash_calculate,
+ },
+ {
+ .name = "sha512",
+ .checksum_len = SHA512_SUM_LEN,
+ .der_len = SHA512_DER_LEN,
+ .der_prefix = sha512_der_prefix,
+ .calculate_sign = EVP_sha512,
+ .calculate = hash_calculate,
+ },
+};
+
+struct crypto_algo crypto_algos[] = {
+ {
+ .name = "rsa2048",
+ .key_len = RSA2048_BYTES,
+ .sign = rsa_sign,
+ .add_verify_data = rsa_add_verify_data,
+ .verify = rsa_verify,
+ },
+ {
+ .name = "rsa4096",
+ .key_len = RSA4096_BYTES,
+ .sign = rsa_sign,
+ .add_verify_data = rsa_add_verify_data,
+ .verify = rsa_verify,
+ },
+ {
+ .name = "ecdsa256",
+ .key_len = ECDSA256_BYTES,
+ .sign = ecdsa_sign,
+ .add_verify_data = ecdsa_add_verify_data,
+ .verify = ecdsa_verify,
+ },
+};
+
+struct padding_algo padding_algos[] = {
+ {
+ .name = "pkcs-1.5",
+ .verify = padding_pkcs_15_verify,
+ },
+ {
+ .name = "pss",
+ .verify = padding_pss_verify,
+ }
+};
+
+struct checksum_algo *image_get_checksum_algo(const char *full_name)
+{
+ int i;
+ const char *name;
+
+ for (i = 0; i < ARRAY_SIZE(checksum_algos); i++) {
+ name = checksum_algos[i].name;
+ /* Make sure names match and next char is a comma */
+ if (!strncmp(name, full_name, strlen(name)) &&
+ full_name[strlen(name)] == ',')
+ return &checksum_algos[i];
+ }
+
+ return NULL;
+}
+
+struct crypto_algo *image_get_crypto_algo(const char *full_name)
+{
+ int i;
+ const char *name;
+
+ /* Move name to after the comma */
+ name = strchr(full_name, ',');
+ if (!name)
+ return NULL;
+ name += 1;
+
+ for (i = 0; i < ARRAY_SIZE(crypto_algos); i++) {
+ if (!strcmp(crypto_algos[i].name, name))
+ return &crypto_algos[i];
+ }
+
+ return NULL;
+}
+
+struct padding_algo *image_get_padding_algo(const char *name)
+{
+ int i;
+
+ if (!name)
+ return NULL;
+
+ for (i = 0; i < ARRAY_SIZE(padding_algos); i++) {
+ if (!strcmp(padding_algos[i].name, name))
+ return &padding_algos[i];
+ }
+
+ return NULL;
+}
diff --git a/tools/mkeficapsule.c b/tools/mkeficapsule.c
index de0a628..4995ba4 100644
--- a/tools/mkeficapsule.c
+++ b/tools/mkeficapsule.c
@@ -4,22 +4,17 @@
* Author: AKASHI Takahiro
*/
-#include <errno.h>
#include <getopt.h>
#include <malloc.h>
#include <stdbool.h>
#include <stdio.h>
#include <stdlib.h>
#include <string.h>
-#include <unistd.h>
#include <linux/types.h>
-#include <sys/mman.h>
#include <sys/stat.h>
#include <sys/types.h>
-#include "fdt_host.h"
-
typedef __u8 u8;
typedef __u16 u16;
typedef __u32 u32;
@@ -29,9 +24,6 @@
#define aligned_u64 __aligned_u64
-#define SIGNATURE_NODENAME "signature"
-#define OVERLAY_NODENAME "__overlay__"
-
#ifndef __packed
#define __packed __attribute__((packed))
#endif
@@ -52,9 +44,6 @@
{"raw", required_argument, NULL, 'r'},
{"index", required_argument, NULL, 'i'},
{"instance", required_argument, NULL, 'I'},
- {"dtb", required_argument, NULL, 'D'},
- {"public key", required_argument, NULL, 'K'},
- {"overlay", no_argument, NULL, 'O'},
{"help", no_argument, NULL, 'h'},
{NULL, 0, NULL, 0},
};
@@ -68,187 +57,10 @@
"\t-r, --raw <raw image> new raw image file\n"
"\t-i, --index <index> update image index\n"
"\t-I, --instance <instance> update hardware instance\n"
- "\t-K, --public-key <key file> public key esl file\n"
- "\t-D, --dtb <dtb file> dtb file\n"
- "\t-O, --overlay the dtb file is an overlay\n"
"\t-h, --help print a help message\n",
tool_name);
}
-static int fdt_add_pub_key_data(void *sptr, void *dptr, size_t key_size,
- bool overlay)
-{
- int parent;
- int ov_node;
- int frag_node;
- int ret = 0;
-
- if (overlay) {
- /*
- * The signature would be stored in the
- * first fragment node of the overlay
- */
- frag_node = fdt_first_subnode(dptr, 0);
- if (frag_node == -FDT_ERR_NOTFOUND) {
- fprintf(stderr,
- "Couldn't find the fragment node: %s\n",
- fdt_strerror(frag_node));
- goto done;
- }
-
- ov_node = fdt_subnode_offset(dptr, frag_node, OVERLAY_NODENAME);
- if (ov_node == -FDT_ERR_NOTFOUND) {
- fprintf(stderr,
- "Couldn't find the __overlay__ node: %s\n",
- fdt_strerror(ov_node));
- goto done;
- }
- } else {
- ov_node = 0;
- }
-
- parent = fdt_subnode_offset(dptr, ov_node, SIGNATURE_NODENAME);
- if (parent == -FDT_ERR_NOTFOUND) {
- parent = fdt_add_subnode(dptr, ov_node, SIGNATURE_NODENAME);
- if (parent < 0) {
- ret = parent;
- if (ret != -FDT_ERR_NOSPACE) {
- fprintf(stderr,
- "Couldn't create signature node: %s\n",
- fdt_strerror(parent));
- }
- }
- }
- if (ret)
- goto done;
-
- /* Write the key to the FDT node */
- ret = fdt_setprop(dptr, parent, "capsule-key",
- sptr, key_size);
-
-done:
- if (ret)
- ret = ret == -FDT_ERR_NOSPACE ? -ENOSPC : -EIO;
-
- return ret;
-}
-
-static int add_public_key(const char *pkey_file, const char *dtb_file,
- bool overlay)
-{
- int ret;
- int srcfd = -1;
- int destfd = -1;
- void *sptr = NULL;
- void *dptr = NULL;
- off_t src_size;
- struct stat pub_key;
- struct stat dtb;
-
- /* Find out the size of the public key */
- srcfd = open(pkey_file, O_RDONLY);
- if (srcfd == -1) {
- fprintf(stderr, "%s: Can't open %s: %s\n",
- __func__, pkey_file, strerror(errno));
- ret = -1;
- goto err;
- }
-
- ret = fstat(srcfd, &pub_key);
- if (ret == -1) {
- fprintf(stderr, "%s: Can't stat %s: %s\n",
- __func__, pkey_file, strerror(errno));
- ret = -1;
- goto err;
- }
-
- src_size = pub_key.st_size;
-
- /* mmap the public key esl file */
- sptr = mmap(0, src_size, PROT_READ, MAP_SHARED, srcfd, 0);
- if (sptr == MAP_FAILED) {
- fprintf(stderr, "%s: Failed to mmap %s:%s\n",
- __func__, pkey_file, strerror(errno));
- ret = -1;
- goto err;
- }
-
- /* Open the dest FDT */
- destfd = open(dtb_file, O_RDWR);
- if (destfd == -1) {
- fprintf(stderr, "%s: Can't open %s: %s\n",
- __func__, dtb_file, strerror(errno));
- ret = -1;
- goto err;
- }
-
- ret = fstat(destfd, &dtb);
- if (ret == -1) {
- fprintf(stderr, "%s: Can't stat %s: %s\n",
- __func__, dtb_file, strerror(errno));
- goto err;
- }
-
- dtb.st_size += src_size + 0x30;
- if (ftruncate(destfd, dtb.st_size)) {
- fprintf(stderr, "%s: Can't expand %s: %s\n",
- __func__, dtb_file, strerror(errno));
- ret = -1;
- goto err;
- }
-
- errno = 0;
- /* mmap the dtb file */
- dptr = mmap(0, dtb.st_size, PROT_READ | PROT_WRITE, MAP_SHARED,
- destfd, 0);
- if (dptr == MAP_FAILED) {
- fprintf(stderr, "%s: Failed to mmap %s:%s\n",
- __func__, dtb_file, strerror(errno));
- ret = -1;
- goto err;
- }
-
- if (fdt_check_header(dptr)) {
- fprintf(stderr, "%s: Invalid FDT header\n", __func__);
- ret = -1;
- goto err;
- }
-
- ret = fdt_open_into(dptr, dptr, dtb.st_size);
- if (ret) {
- fprintf(stderr, "%s: Cannot expand FDT: %s\n",
- __func__, fdt_strerror(ret));
- ret = -1;
- goto err;
- }
-
- /* Copy the esl file to the expanded FDT */
- ret = fdt_add_pub_key_data(sptr, dptr, src_size, overlay);
- if (ret < 0) {
- fprintf(stderr, "%s: Unable to add public key to the FDT\n",
- __func__);
- ret = -1;
- goto err;
- }
-
- ret = 0;
-
-err:
- if (sptr)
- munmap(sptr, src_size);
-
- if (dptr)
- munmap(dptr, dtb.st_size);
-
- if (srcfd != -1)
- close(srcfd);
-
- if (destfd != -1)
- close(destfd);
-
- return ret;
-}
-
static int create_fwbin(char *path, char *bin, efi_guid_t *guid,
unsigned long index, unsigned long instance)
{
@@ -366,22 +178,16 @@
int main(int argc, char **argv)
{
char *file;
- char *pkey_file;
- char *dtb_file;
efi_guid_t *guid;
unsigned long index, instance;
int c, idx;
- int ret;
- bool overlay = false;
file = NULL;
- pkey_file = NULL;
- dtb_file = NULL;
guid = NULL;
index = 0;
instance = 0;
for (;;) {
- c = getopt_long(argc, argv, "f:r:i:I:v:D:K:Oh", options, &idx);
+ c = getopt_long(argc, argv, "f:r:i:I:v:h", options, &idx);
if (c == -1)
break;
@@ -408,43 +214,22 @@
case 'I':
instance = strtoul(optarg, NULL, 0);
break;
- case 'K':
- if (pkey_file) {
- printf("Public Key already specified\n");
- return -1;
- }
- pkey_file = optarg;
- break;
- case 'D':
- if (dtb_file) {
- printf("DTB file already specified\n");
- return -1;
- }
- dtb_file = optarg;
- break;
- case 'O':
- overlay = true;
- break;
case 'h':
print_usage();
return 0;
}
}
- /* need a fit image file or raw image file */
- if (!file && !pkey_file && !dtb_file) {
+ /* need an output file */
+ if (argc != optind + 1) {
print_usage();
exit(EXIT_FAILURE);
}
- if (pkey_file && dtb_file) {
- ret = add_public_key(pkey_file, dtb_file, overlay);
- if (ret == -1) {
- printf("Adding public key to the dtb failed\n");
- exit(EXIT_FAILURE);
- } else {
- exit(EXIT_SUCCESS);
- }
+ /* need a fit image file or raw image file */
+ if (!file) {
+ print_usage();
+ exit(EXIT_SUCCESS);
}
if (create_fwbin(argv[optind], file, guid, index, instance)