tree b6981028f79b40cc7a85b8bb615704edcb23d66f
parent cc1c4623cdd6fb9b45af9cbf03aa2a532ba39f3f
author Nikhil M Jain <n-jain1@ti.com> 1689670655 +0530
committer Tom Rini <trini@konsulko.com> 1689967932 -0400

doc: board: ti: am62x_sk: Add A53 SPL DDR layout

To understand usage of DDR in A53 SPL stage, add a table showing region
and space used by major components of SPL.

Signed-off-by: Nikhil M Jain <n-jain1@ti.com>
Reviewed-by: Tom Rini <trini@konsulko.com>