diff --git a/include/4xx_i2c.h b/include/4xx_i2c.h
index f0e772c..070657f 100644
--- a/include/4xx_i2c.h
+++ b/include/4xx_i2c.h
@@ -63,7 +63,7 @@
 #define IIC_EXTSTS	(I2C_REGISTERS_BASE_ADDRESS+IICEXTSTS)
 #define IIC_LSADR	(I2C_REGISTERS_BASE_ADDRESS+IICLSADR)
 #define IIC_HSADR	(I2C_REGISTERS_BASE_ADDRESS+IICHSADR)
-#define IIC_CLKDIV	(I2C_REGISTERS_BASE_ADDRESS+IICCLKDIV)
+#define IIC_CLKDIV	(I2C_REGISTERS_BASE_ADDRESS+IIC0_CLKDIV)
 #define IIC_INTRMSK	(I2C_REGISTERS_BASE_ADDRESS+IICINTRMSK)
 #define IIC_XFRCNT	(I2C_REGISTERS_BASE_ADDRESS+IICXFRCNT)
 #define IIC_XTCNTLSS	(I2C_REGISTERS_BASE_ADDRESS+IICXTCNTLSS)
diff --git a/include/ppc405.h b/include/ppc405.h
index 5e56897..4c62249 100644
--- a/include/ppc405.h
+++ b/include/ppc405.h
@@ -578,7 +578,7 @@
 #define    IICEXTSTS	    0x09
 #define    IICLSADR	    0x0A
 #define    IICHSADR	    0x0B
-#define    IICCLKDIV	    0x0C
+#define    IIC0_CLKDIV	    0x0C
 #define    IICINTRMSK	    0x0D
 #define    IICXFRCNT	    0x0E
 #define    IICXTCNTLSS	    0x0F
@@ -760,7 +760,7 @@
 #define CPR0_PLLD	0x060
 #define CPR0_CPUD	0x080
 #define CPR0_PLBD	0x0a0
-#define CPR0_OPBD	0x0c0
+#define CPR0_OPBD0	0x0c0
 #define CPR0_PERD	0x0e0
 
 #define SDR0_PINSTP	0x0040
diff --git a/include/ppc440.h b/include/ppc440.h
index 378a9de..9299a71 100644
--- a/include/ppc440.h
+++ b/include/ppc440.h
@@ -60,9 +60,9 @@
 /* values for clkcfga register - indirect addressing of these regs */
 #define CPR0_PLLC	0x0040
 #define CPR0_PLLD	0x0060
-#define CPR0_PRIMAD	0x0080
-#define CPR0_PRIMBD	0x00a0
-#define CPR0_OPBD	0x00c0
+#define CPR0_PRIMAD0	0x0080
+#define CPR0_PRIMBD0	0x00a0
+#define CPR0_OPBD0	0x00c0
 #define CPR0_PERD	0x00e0
 #define CPR0_MALD	0x0100
 #define CPR0_SPCID	0x0120
@@ -100,7 +100,7 @@
 #define SDR0_PFC1	0x4101	/* Pin Function 1 */
 #define SDR0_MFR	0x4300	/* SDR0_MFR reg */
 
-#ifdef CONFIG_440GX
+#if defined(CONFIG_440GX)
 #define SD0_AMP		0x0240
 #define SDR0_XPLLC	0x01c1
 #define SDR0_XPLLD	0x01c2
@@ -1319,6 +1319,19 @@
 #define SDR0_MFR_PKT_REJ_POL         0x00080000   /* Packet Reject Polarity      */
 #endif
 
+
+#if defined(CONFIG_440EPX)
+#define CPM0_ER			0x000000B0
+#define CPM1_ER			0x000000F0
+#define PLB4A0_ACR		0x00000081
+#define PLB4A1_ACR		0x00000089
+#define PLB3A0_ACR		0x00000077
+#define OPB2PLB40_BCTRL		0x00000350
+#define P4P3BO0_CFG		0x00000026
+#define SPI0_MODE               0xEF600090 /* SPI Mode Regsgiter */
+
+#endif
+
 #if defined(CONFIG_440EPX) || defined(CONFIG_440GRX)
 #define SDR0_PFC1_EPS_ENCODE(n)		((((unsigned long)(n))&0x07)<<22)
 #define SDR0_PFC1_EPS_DECODE(n)		((((unsigned long)(n))>>22)&0x07)
@@ -1385,6 +1398,12 @@
 #define SDR0_SRST1_FPU          0x00004000 /* Floating Point Unit */
 #define SDR0_SRST1_KASU0        0x00002000 /* Kasumi Engine */
 
+#define SDR0_EMAC0RXST 		0x00004301 /* */
+#define SDR0_EMAC0TXST		0x00004302 /* */
+#define SDR0_CRYP0		0x00004500
+#define SDR0_EBC0		0x00000100
+#define SDR0_SDSTP2		0x00004001
+#define SDR0_SDSTP3		0x00004001
 #elif defined(CONFIG_460EX) || defined(CONFIG_460GT)
 
 #define SDR0_SRST0		SDR0_SRST  /* for compatability reasons */
@@ -1586,7 +1605,7 @@
 #define IICEXTSTS		0x09
 #define IICLSADR		0x0A
 #define IICHSADR		0x0B
-#define IICCLKDIV		0x0C
+#define IIC0_CLKDIV		0x0C
 #define IICINTRMSK		0x0D
 #define IICXFRCNT		0x0E
 #define IICXTCNTLSS		0x0F
@@ -1595,10 +1614,10 @@
 /*-----------------------------------------------------------------------------
 | PCI Internal Registers et. al. (accessed via plb)
 +----------------------------------------------------------------------------*/
-#define PCIX0_CFGADR		(CONFIG_SYS_PCI_BASE + 0x0ec00000)
-#define PCIX0_CFGDATA		(CONFIG_SYS_PCI_BASE + 0x0ec00004)
-#define PCIX0_CFGBASE		(CONFIG_SYS_PCI_BASE + 0x0ec80000)
-#define PCIX0_IOBASE		(CONFIG_SYS_PCI_BASE + 0x08000000)
+#define PCIL0_CFGADR		(CONFIG_SYS_PCI_BASE + 0x0ec00000)
+#define PCIL0_CFGDATA		(CONFIG_SYS_PCI_BASE + 0x0ec00004)
+#define PCIL0_CFGBASE		(CONFIG_SYS_PCI_BASE + 0x0ec80000)
+#define PCIL0_IOBASE		(CONFIG_SYS_PCI_BASE + 0x08000000)
 
 #if defined(CONFIG_440EP) || defined(CONFIG_440GR) || \
     defined(CONFIG_440EPX) || defined(CONFIG_440GRX)
@@ -1608,82 +1627,82 @@
 #define PCI_MMIO_LCR_BASE (CONFIG_SYS_PCI_BASE + 0x0f400000)    /* Real => 0x0EF400000 */
 
 /* PCI Master Local Configuration Registers */
-#define PCIX0_PMM0LA         (PCI_MMIO_LCR_BASE + 0x00) /* PMM0 Local Address */
-#define PCIX0_PMM0MA         (PCI_MMIO_LCR_BASE + 0x04) /* PMM0 Mask/Attribute */
-#define PCIX0_PMM0PCILA      (PCI_MMIO_LCR_BASE + 0x08) /* PMM0 PCI Low Address */
-#define PCIX0_PMM0PCIHA      (PCI_MMIO_LCR_BASE + 0x0C) /* PMM0 PCI High Address */
-#define PCIX0_PMM1LA         (PCI_MMIO_LCR_BASE + 0x10) /* PMM1 Local Address */
-#define PCIX0_PMM1MA         (PCI_MMIO_LCR_BASE + 0x14) /* PMM1 Mask/Attribute */
-#define PCIX0_PMM1PCILA      (PCI_MMIO_LCR_BASE + 0x18) /* PMM1 PCI Low Address */
-#define PCIX0_PMM1PCIHA      (PCI_MMIO_LCR_BASE + 0x1C) /* PMM1 PCI High Address */
-#define PCIX0_PMM2LA         (PCI_MMIO_LCR_BASE + 0x20) /* PMM2 Local Address */
-#define PCIX0_PMM2MA         (PCI_MMIO_LCR_BASE + 0x24) /* PMM2 Mask/Attribute */
-#define PCIX0_PMM2PCILA      (PCI_MMIO_LCR_BASE + 0x28) /* PMM2 PCI Low Address */
-#define PCIX0_PMM2PCIHA      (PCI_MMIO_LCR_BASE + 0x2C) /* PMM2 PCI High Address */
+#define PCIL0_PMM0LA         (PCI_MMIO_LCR_BASE + 0x00) /* PMM0 Local Address */
+#define PCIL0_PMM0MA         (PCI_MMIO_LCR_BASE + 0x04) /* PMM0 Mask/Attribute */
+#define PCIL0_PMM0PCILA      (PCI_MMIO_LCR_BASE + 0x08) /* PMM0 PCI Low Address */
+#define PCIL0_PMM0PCIHA      (PCI_MMIO_LCR_BASE + 0x0C) /* PMM0 PCI High Address */
+#define PCIL0_PMM1LA         (PCI_MMIO_LCR_BASE + 0x10) /* PMM1 Local Address */
+#define PCIL0_PMM1MA         (PCI_MMIO_LCR_BASE + 0x14) /* PMM1 Mask/Attribute */
+#define PCIL0_PMM1PCILA      (PCI_MMIO_LCR_BASE + 0x18) /* PMM1 PCI Low Address */
+#define PCIL0_PMM1PCIHA      (PCI_MMIO_LCR_BASE + 0x1C) /* PMM1 PCI High Address */
+#define PCIL0_PMM2LA         (PCI_MMIO_LCR_BASE + 0x20) /* PMM2 Local Address */
+#define PCIL0_PMM2MA         (PCI_MMIO_LCR_BASE + 0x24) /* PMM2 Mask/Attribute */
+#define PCIL0_PMM2PCILA      (PCI_MMIO_LCR_BASE + 0x28) /* PMM2 PCI Low Address */
+#define PCIL0_PMM2PCIHA      (PCI_MMIO_LCR_BASE + 0x2C) /* PMM2 PCI High Address */
 
 /* PCI Target Local Configuration Registers */
-#define PCIX0_PTM1MS         (PCI_MMIO_LCR_BASE + 0x30) /* PTM1 Memory Size/Attribute */
-#define PCIX0_PTM1LA         (PCI_MMIO_LCR_BASE + 0x34) /* PTM1 Local Addr. Reg */
-#define PCIX0_PTM2MS         (PCI_MMIO_LCR_BASE + 0x38) /* PTM2 Memory Size/Attribute */
-#define PCIX0_PTM2LA         (PCI_MMIO_LCR_BASE + 0x3C) /* PTM2 Local Addr. Reg */
+#define PCIL0_PTM1MS         (PCI_MMIO_LCR_BASE + 0x30) /* PTM1 Memory Size/Attribute */
+#define PCIL0_PTM1LA         (PCI_MMIO_LCR_BASE + 0x34) /* PTM1 Local Addr. Reg */
+#define PCIL0_PTM2MS         (PCI_MMIO_LCR_BASE + 0x38) /* PTM2 Memory Size/Attribute */
+#define PCIL0_PTM2LA         (PCI_MMIO_LCR_BASE + 0x3C) /* PTM2 Local Addr. Reg */
 
 #else
 
-#define PCIX0_VENDID		(PCIX0_CFGBASE + PCI_VENDOR_ID )
-#define PCIX0_DEVID		(PCIX0_CFGBASE + PCI_DEVICE_ID )
-#define PCIX0_CMD		(PCIX0_CFGBASE + PCI_COMMAND )
-#define PCIX0_STATUS		(PCIX0_CFGBASE + PCI_STATUS )
-#define PCIX0_REVID		(PCIX0_CFGBASE + PCI_REVISION_ID )
-#define PCIX0_CLS		(PCIX0_CFGBASE + PCI_CLASS_CODE)
-#define PCIX0_CACHELS		(PCIX0_CFGBASE + PCI_CACHE_LINE_SIZE )
-#define PCIX0_LATTIM		(PCIX0_CFGBASE + PCI_LATENCY_TIMER )
-#define PCIX0_HDTYPE		(PCIX0_CFGBASE + PCI_HEADER_TYPE )
-#define PCIX0_BIST		(PCIX0_CFGBASE + PCI_BIST )
-#define PCIX0_BAR0		(PCIX0_CFGBASE + PCI_BASE_ADDRESS_0 )
-#define PCIX0_BAR1		(PCIX0_CFGBASE + PCI_BASE_ADDRESS_1 )
-#define PCIX0_BAR2		(PCIX0_CFGBASE + PCI_BASE_ADDRESS_2 )
-#define PCIX0_BAR3		(PCIX0_CFGBASE + PCI_BASE_ADDRESS_3 )
-#define PCIX0_BAR4		(PCIX0_CFGBASE + PCI_BASE_ADDRESS_4 )
-#define PCIX0_BAR5		(PCIX0_CFGBASE + PCI_BASE_ADDRESS_5 )
-#define PCIX0_CISPTR		(PCIX0_CFGBASE + PCI_CARDBUS_CIS )
-#define PCIX0_SBSYSVID		(PCIX0_CFGBASE + PCI_SUBSYSTEM_VENDOR_ID )
-#define PCIX0_SBSYSID		(PCIX0_CFGBASE + PCI_SUBSYSTEM_ID )
-#define PCIX0_EROMBA		(PCIX0_CFGBASE + PCI_ROM_ADDRESS )
-#define PCIX0_CAP		(PCIX0_CFGBASE + PCI_CAPABILITY_LIST )
-#define PCIX0_RES0		(PCIX0_CFGBASE + 0x0035 )
-#define PCIX0_RES1		(PCIX0_CFGBASE + 0x0036 )
-#define PCIX0_RES2		(PCIX0_CFGBASE + 0x0038 )
-#define PCIX0_INTLN		(PCIX0_CFGBASE + PCI_INTERRUPT_LINE )
-#define PCIX0_INTPN		(PCIX0_CFGBASE + PCI_INTERRUPT_PIN )
-#define PCIX0_MINGNT		(PCIX0_CFGBASE + PCI_MIN_GNT )
-#define PCIX0_MAXLTNCY		(PCIX0_CFGBASE + PCI_MAX_LAT )
+#define PCIL0_VENDID		(PCIL0_CFGBASE + PCI_VENDOR_ID )
+#define PCIL0_DEVID		(PCIL0_CFGBASE + PCI_DEVICE_ID )
+#define PCIL0_CMD		(PCIL0_CFGBASE + PCI_COMMAND )
+#define PCIL0_STATUS		(PCIL0_CFGBASE + PCI_STATUS )
+#define PCIL0_REVID		(PCIL0_CFGBASE + PCI_REVISION_ID )
+#define PCIL0_CLS		(PCIL0_CFGBASE + PCI_CLASS_CODE)
+#define PCIL0_CACHELS		(PCIL0_CFGBASE + PCI_CACHE_LINE_SIZE )
+#define PCIL0_LATTIM		(PCIL0_CFGBASE + PCI_LATENCY_TIMER )
+#define PCIL0_HDTYPE		(PCIL0_CFGBASE + PCI_HEADER_TYPE )
+#define PCIL0_BIST		(PCIL0_CFGBASE + PCI_BIST )
+#define PCIL0_BAR0		(PCIL0_CFGBASE + PCI_BASE_ADDRESS_0 )
+#define PCIL0_BAR1		(PCIL0_CFGBASE + PCI_BASE_ADDRESS_1 )
+#define PCIL0_BAR2		(PCIL0_CFGBASE + PCI_BASE_ADDRESS_2 )
+#define PCIL0_BAR3		(PCIL0_CFGBASE + PCI_BASE_ADDRESS_3 )
+#define PCIL0_BAR4		(PCIL0_CFGBASE + PCI_BASE_ADDRESS_4 )
+#define PCIL0_BAR5		(PCIL0_CFGBASE + PCI_BASE_ADDRESS_5 )
+#define PCIL0_CISPTR		(PCIL0_CFGBASE + PCI_CARDBUS_CIS )
+#define PCIL0_SBSYSVID		(PCIL0_CFGBASE + PCI_SUBSYSTEM_VENDOR_ID )
+#define PCIL0_SBSYSID		(PCIL0_CFGBASE + PCI_SUBSYSTEM_ID )
+#define PCIL0_EROMBA		(PCIL0_CFGBASE + PCI_ROM_ADDRESS )
+#define PCIL0_CAP		(PCIL0_CFGBASE + PCI_CAPABILITY_LIST )
+#define PCIL0_RES0		(PCIL0_CFGBASE + 0x0035 )
+#define PCIL0_RES1		(PCIL0_CFGBASE + 0x0036 )
+#define PCIL0_RES2		(PCIL0_CFGBASE + 0x0038 )
+#define PCIL0_INTLN		(PCIL0_CFGBASE + PCI_INTERRUPT_LINE )
+#define PCIL0_INTPN		(PCIL0_CFGBASE + PCI_INTERRUPT_PIN )
+#define PCIL0_MINGNT		(PCIL0_CFGBASE + PCI_MIN_GNT )
+#define PCIL0_MAXLTNCY		(PCIL0_CFGBASE + PCI_MAX_LAT )
 
-#define PCIX0_BRDGOPT1		(PCIX0_CFGBASE + 0x0040)
-#define PCIX0_BRDGOPT2		(PCIX0_CFGBASE + 0x0044)
+#define PCIL0_BRDGOPT1		(PCIL0_CFGBASE + 0x0040)
+#define PCIL0_BRDGOPT2		(PCIL0_CFGBASE + 0x0044)
 
-#define PCIX0_POM0LAL		(PCIX0_CFGBASE + 0x0068)
-#define PCIX0_POM0LAH		(PCIX0_CFGBASE + 0x006c)
-#define PCIX0_POM0SA		(PCIX0_CFGBASE + 0x0070)
-#define PCIX0_POM0PCIAL		(PCIX0_CFGBASE + 0x0074)
-#define PCIX0_POM0PCIAH		(PCIX0_CFGBASE + 0x0078)
-#define PCIX0_POM1LAL		(PCIX0_CFGBASE + 0x007c)
-#define PCIX0_POM1LAH		(PCIX0_CFGBASE + 0x0080)
-#define PCIX0_POM1SA		(PCIX0_CFGBASE + 0x0084)
-#define PCIX0_POM1PCIAL		(PCIX0_CFGBASE + 0x0088)
-#define PCIX0_POM1PCIAH		(PCIX0_CFGBASE + 0x008c)
-#define PCIX0_POM2SA		(PCIX0_CFGBASE + 0x0090)
+#define PCIL0_POM0LAL		(PCIL0_CFGBASE + 0x0068)
+#define PCIL0_POM0LAH		(PCIL0_CFGBASE + 0x006c)
+#define PCIL0_POM0SA		(PCIL0_CFGBASE + 0x0070)
+#define PCIL0_POM0PCIAL		(PCIL0_CFGBASE + 0x0074)
+#define PCIL0_POM0PCIAH		(PCIL0_CFGBASE + 0x0078)
+#define PCIL0_POM1LAL		(PCIL0_CFGBASE + 0x007c)
+#define PCIL0_POM1LAH		(PCIL0_CFGBASE + 0x0080)
+#define PCIL0_POM1SA		(PCIL0_CFGBASE + 0x0084)
+#define PCIL0_POM1PCIAL		(PCIL0_CFGBASE + 0x0088)
+#define PCIL0_POM1PCIAH		(PCIL0_CFGBASE + 0x008c)
+#define PCIL0_POM2SA		(PCIL0_CFGBASE + 0x0090)
 
-#define PCIX0_PIM0SA		(PCIX0_CFGBASE + 0x0098)
-#define PCIX0_PIM0LAL		(PCIX0_CFGBASE + 0x009c)
-#define PCIX0_PIM0LAH		(PCIX0_CFGBASE + 0x00a0)
-#define PCIX0_PIM1SA		(PCIX0_CFGBASE + 0x00a4)
-#define PCIX0_PIM1LAL		(PCIX0_CFGBASE + 0x00a8)
-#define PCIX0_PIM1LAH		(PCIX0_CFGBASE + 0x00ac)
-#define PCIX0_PIM2SA		(PCIX0_CFGBASE + 0x00b0)
-#define PCIX0_PIM2LAL		(PCIX0_CFGBASE + 0x00b4)
-#define PCIX0_PIM2LAH		(PCIX0_CFGBASE + 0x00b8)
+#define PCIL0_PIM0SA		(PCIL0_CFGBASE + 0x0098)
+#define PCIL0_PIM0LAL		(PCIL0_CFGBASE + 0x009c)
+#define PCIL0_PIM0LAH		(PCIL0_CFGBASE + 0x00a0)
+#define PCIL0_PIM1SA		(PCIL0_CFGBASE + 0x00a4)
+#define PCIL0_PIM1LAL		(PCIL0_CFGBASE + 0x00a8)
+#define PCIL0_PIM1LAH		(PCIL0_CFGBASE + 0x00ac)
+#define PCIL0_PIM2SA		(PCIL0_CFGBASE + 0x00b0)
+#define PCIL0_PIM2LAL		(PCIL0_CFGBASE + 0x00b4)
+#define PCIL0_PIM2LAH		(PCIL0_CFGBASE + 0x00b8)
 
-#define PCIX0_STS		(PCIX0_CFGBASE + 0x00e0)
+#define PCIL0_STS		(PCIL0_CFGBASE + 0x00e0)
 
 #endif /* !defined(CONFIG_440EP) !defined(CONFIG_440GR) */
 
diff --git a/include/ppc4xx_enet.h b/include/ppc4xx_enet.h
index 7588e93..9be22e7 100644
--- a/include/ppc4xx_enet.h
+++ b/include/ppc4xx_enet.h
@@ -173,13 +173,13 @@
 #if defined(CONFIG_440EP) || defined(CONFIG_440GR) || \
     defined(CONFIG_440EPX) || defined(CONFIG_440GRX) || \
     defined(CONFIG_460EX) || defined(CONFIG_460GT)
-#define ZMII_BASE		(CONFIG_SYS_PERIPHERAL_BASE + 0x0D00)
+#define ZMII0_BASE		(CONFIG_SYS_PERIPHERAL_BASE + 0x0D00)
 #else
-#define ZMII_BASE		(CONFIG_SYS_PERIPHERAL_BASE + 0x0780)
+#define ZMII0_BASE		(CONFIG_SYS_PERIPHERAL_BASE + 0x0780)
 #endif
-#define ZMII_FER		(ZMII_BASE)
-#define ZMII_SSR		(ZMII_BASE + 4)
-#define ZMII_SMIISR		(ZMII_BASE + 8)
+#define ZMII0_FER		(ZMII0_BASE)
+#define ZMII0_SSR		(ZMII0_BASE + 4)
+#define ZMII0_SMIISR		(ZMII0_BASE + 8)
 
 /* ZMII FER Register Bit Definitions */
 #define ZMII_FER_DIS		(0x0)
@@ -196,25 +196,25 @@
 
 
 /* ZMII Speed Selection Register Bit Definitions */
-#define ZMII_SSR_SCI		(0x4)
-#define ZMII_SSR_FSS		(0x2)
-#define ZMII_SSR_SP		(0x1)
-#define ZMII_SSR_RSVD16_31	(0x0000FFFF)
+#define ZMII0_SSR_SCI		(0x4)
+#define ZMII0_SSR_FSS		(0x2)
+#define ZMII0_SSR_SP		(0x1)
+#define ZMII0_SSR_RSVD16_31	(0x0000FFFF)
 
-#define ZMII_SSR_V(__x)		(((3 - __x) * 4) + 16)
+#define ZMII0_SSR_V(__x)		(((3 - __x) * 4) + 16)
 
 
 /* ZMII SMII Status Register Bit Definitions */
-#define ZMII_SMIISR_E1		(0x80)
-#define ZMII_SMIISR_EC		(0x40)
-#define ZMII_SMIISR_EN		(0x20)
-#define ZMII_SMIISR_EJ		(0x10)
-#define ZMII_SMIISR_EL		(0x08)
-#define ZMII_SMIISR_ED		(0x04)
-#define ZMII_SMIISR_ES		(0x02)
-#define ZMII_SMIISR_EF		(0x01)
+#define ZMII0_SMIISR_E1		(0x80)
+#define ZMII0_SMIISR_EC		(0x40)
+#define ZMII0_SMIISR_EN		(0x20)
+#define ZMII0_SMIISR_EJ		(0x10)
+#define ZMII0_SMIISR_EL		(0x08)
+#define ZMII0_SMIISR_ED		(0x04)
+#define ZMII0_SMIISR_ES		(0x02)
+#define ZMII0_SMIISR_EF		(0x01)
 
-#define ZMII_SMIISR_V(__x)	((3 - __x) * 8)
+#define ZMII0_SMIISR_V(__x)	((3 - __x) * 8)
 
 /* RGMII Register Addresses */
 #if defined(CONFIG_440EPX) || defined(CONFIG_440GRX)
@@ -328,41 +328,49 @@
 #if defined(CONFIG_440EP) || defined(CONFIG_440GR) || \
     defined(CONFIG_440EPX) || defined(CONFIG_440GRX) || \
     defined(CONFIG_460EX) || defined(CONFIG_460GT)
-#define EMAC_BASE		(CONFIG_SYS_PERIPHERAL_BASE + 0x0E00)
+#define EMAC0_BASE		(CONFIG_SYS_PERIPHERAL_BASE + 0x0E00)
 #else
-#define EMAC_BASE		(CONFIG_SYS_PERIPHERAL_BASE + 0x0800)
+#define EMAC0_BASE		(CONFIG_SYS_PERIPHERAL_BASE + 0x0800)
 #endif
 #else
 #if defined(CONFIG_405EZ) || defined(CONFIG_405EX)
-#define EMAC_BASE		0xEF600900
+#define EMAC0_BASE		0xEF600900
 #else
-#define EMAC_BASE		0xEF600800
+#define EMAC0_BASE		0xEF600800
 #endif
 #endif
 
-#define EMAC_M0			(EMAC_BASE)
-#define EMAC_M1			(EMAC_BASE + 4)
-#define EMAC_TXM0		(EMAC_BASE + 8)
-#define EMAC_TXM1		(EMAC_BASE + 12)
-#define EMAC_RXM		(EMAC_BASE + 16)
-#define EMAC_ISR		(EMAC_BASE + 20)
-#define EMAC_IER		(EMAC_BASE + 24)
-#define EMAC_IAH		(EMAC_BASE + 28)
-#define EMAC_IAL		(EMAC_BASE + 32)
-#define EMAC_PAUSE_TIME_REG	(EMAC_BASE + 44)
-#define EMAC_I_FRAME_GAP_REG	(EMAC_BASE + 88)
-#define EMAC_STACR		(EMAC_BASE + 92)
-#define EMAC_TRTR		(EMAC_BASE + 96)
-#define EMAC_RX_HI_LO_WMARK	(EMAC_BASE + 100)
+#if defined(CONFIG_440EPX)
+#define EMAC1_BASE		0xEF600F00
+#define EMAC1_MR1		(EMAC1_BASE + 0x04)
+#endif
+
+#define EMAC0_MR0		(EMAC0_BASE)
+#define EMAC0_MR1		(EMAC0_BASE + 0x04)
+#define EMAC0_TMR0		(EMAC0_BASE + 0x08)
+#define EMAC0_TMR1		(EMAC0_BASE + 0x0c)
+#define EMAC0_RXM		(EMAC0_BASE + 0x10)
+#define EMAC0_ISR		(EMAC0_BASE + 0x14)
+#define EMAC0_IER		(EMAC0_BASE + 0x18)
+#define EMAC0_IAH		(EMAC0_BASE + 0x1c)
+#define EMAC0_IAL		(EMAC0_BASE + 0x20)
+#define EMAC0_PTR		(EMAC0_BASE + 0x2c)
+#define EMAC0_PAUSE_TIME_REG	EMAC0_PTR
+#define EMAC0_IPGVR		(EMAC0_BASE + 0x58)
+#define EMAC0_I_FRAME_GAP_REG	EMAC0_IPGVR
+#define EMAC0_STACR		(EMAC0_BASE + 0x5c)
+#define EMAC0_TRTR		(EMAC0_BASE + 0x60)
+#define EMAC0_RWMR		(EMAC0_BASE + 0x64)
+#define EMAC0_RX_HI_LO_WMARK	EMAC0_RWMR
 
 /* bit definitions */
 /* MODE REG 0 */
-#define EMAC_M0_RXI		(0x80000000)
-#define EMAC_M0_TXI		(0x40000000)
-#define EMAC_M0_SRST		(0x20000000)
-#define EMAC_M0_TXE		(0x10000000)
-#define EMAC_M0_RXE		(0x08000000)
-#define EMAC_M0_WKE		(0x04000000)
+#define EMAC_MR0_RXI		(0x80000000)
+#define EMAC_MR0_TXI		(0x40000000)
+#define EMAC_MR0_SRST		(0x20000000)
+#define EMAC_MR0_TXE		(0x10000000)
+#define EMAC_MR0_RXE		(0x08000000)
+#define EMAC_MR0_WKE		(0x04000000)
 
 /* on 440GX EMAC_MR1 has a different layout! */
 #if defined(CONFIG_440GX) || \
@@ -371,82 +379,82 @@
     defined(CONFIG_460EX) || defined(CONFIG_460GT) || \
     defined(CONFIG_405EX)
 /* MODE Reg 1 */
-#define EMAC_M1_FDE		(0x80000000)
-#define EMAC_M1_ILE		(0x40000000)
-#define EMAC_M1_VLE		(0x20000000)
-#define EMAC_M1_EIFC		(0x10000000)
-#define EMAC_M1_APP		(0x08000000)
-#define EMAC_M1_RSVD		(0x06000000)
-#define EMAC_M1_IST		(0x01000000)
-#define EMAC_M1_MF_1000GPCS	(0x00C00000)
-#define EMAC_M1_MF_1000MBPS	(0x00800000)	/* 0's for 10MBPS */
-#define EMAC_M1_MF_100MBPS	(0x00400000)
-#define EMAC_M1_RFS_MASK	(0x00380000)
-#define EMAC_M1_RFS_16K		(0x00280000)
-#define EMAC_M1_RFS_8K		(0x00200000)
-#define EMAC_M1_RFS_4K		(0x00180000)
-#define EMAC_M1_RFS_2K		(0x00100000)
-#define EMAC_M1_RFS_1K		(0x00080000)
-#define EMAC_M1_TX_FIFO_MASK	(0x00070000)
-#define EMAC_M1_TX_FIFO_16K	(0x00050000)
-#define EMAC_M1_TX_FIFO_8K	(0x00040000)
-#define EMAC_M1_TX_FIFO_4K	(0x00030000)
-#define EMAC_M1_TX_FIFO_2K	(0x00020000)
-#define EMAC_M1_TX_FIFO_1K	(0x00010000)
-#define EMAC_M1_TR_MULTI	(0x00008000)	/* 0'x for single packet */
-#define EMAC_M1_MWSW		(0x00007000)
-#define EMAC_M1_JUMBO_ENABLE	(0x00000800)
-#define EMAC_M1_IPPA		(0x000007c0)
-#define EMAC_M1_IPPA_SET(id)	(((id) & 0x1f) << 6)
-#define EMAC_M1_IPPA_GET(id)	(((id) >> 6) & 0x1f)
-#define EMAC_M1_OBCI_GT100	(0x00000020)
-#define EMAC_M1_OBCI_100	(0x00000018)
-#define EMAC_M1_OBCI_83		(0x00000010)
-#define EMAC_M1_OBCI_66		(0x00000008)
-#define EMAC_M1_RSVD1		(0x00000007)
+#define EMAC_MR1_FDE		(0x80000000)
+#define EMAC_MR1_ILE		(0x40000000)
+#define EMAC_MR1_VLE		(0x20000000)
+#define EMAC_MR1_EIFC		(0x10000000)
+#define EMAC_MR1_APP		(0x08000000)
+#define EMAC_MR1_RSVD		(0x06000000)
+#define EMAC_MR1_IST		(0x01000000)
+#define EMAC_MR1_MF_1000GPCS	(0x00C00000)
+#define EMAC_MR1_MF_1000MBPS	(0x00800000)	/* 0's for 10MBPS */
+#define EMAC_MR1_MF_100MBPS	(0x00400000)
+#define EMAC_MR1_RFS_MASK	(0x00380000)
+#define EMAC_MR1_RFS_16K		(0x00280000)
+#define EMAC_MR1_RFS_8K		(0x00200000)
+#define EMAC_MR1_RFS_4K		(0x00180000)
+#define EMAC_MR1_RFS_2K		(0x00100000)
+#define EMAC_MR1_RFS_1K		(0x00080000)
+#define EMAC_MR1_TX_FIFO_MASK	(0x00070000)
+#define EMAC_MR1_TX_FIFO_16K	(0x00050000)
+#define EMAC_MR1_TX_FIFO_8K	(0x00040000)
+#define EMAC_MR1_TX_FIFO_4K	(0x00030000)
+#define EMAC_MR1_TX_FIFO_2K	(0x00020000)
+#define EMAC_MR1_TX_FIFO_1K	(0x00010000)
+#define EMAC_MR1_TR_MULTI	(0x00008000)	/* 0'x for single packet */
+#define EMAC_MR1_MWSW		(0x00007000)
+#define EMAC_MR1_JUMBO_ENABLE	(0x00000800)
+#define EMAC_MR1_IPPA		(0x000007c0)
+#define EMAC_MR1_IPPA_SET(id)	(((id) & 0x1f) << 6)
+#define EMAC_MR1_IPPA_GET(id)	(((id) >> 6) & 0x1f)
+#define EMAC_MR1_OBCI_GT100	(0x00000020)
+#define EMAC_MR1_OBCI_100	(0x00000018)
+#define EMAC_MR1_OBCI_83		(0x00000010)
+#define EMAC_MR1_OBCI_66		(0x00000008)
+#define EMAC_MR1_RSVD1		(0x00000007)
 #else /* defined(CONFIG_440GX) */
 /* EMAC_MR1 is the same on 405GP, 405GPr, 405EP, 440GP, 440EP */
-#define EMAC_M1_FDE		0x80000000
-#define EMAC_M1_ILE		0x40000000
-#define EMAC_M1_VLE		0x20000000
-#define EMAC_M1_EIFC		0x10000000
-#define EMAC_M1_APP		0x08000000
-#define EMAC_M1_AEMI		0x02000000
-#define EMAC_M1_IST		0x01000000
-#define EMAC_M1_MF_1000MBPS	0x00800000	/* 0's for 10MBPS */
-#define EMAC_M1_MF_100MBPS	0x00400000
-#define EMAC_M1_RFS_MASK	0x00300000
-#define EMAC_M1_RFS_4K		0x00300000
-#define EMAC_M1_RFS_2K		0x00200000
-#define EMAC_M1_RFS_1K		0x00100000
-#define EMAC_M1_RFS_512		0x00000000
-#define EMAC_M1_TX_FIFO_MASK	0x000c0000
-#define EMAC_M1_TX_FIFO_2K	0x00080000
-#define EMAC_M1_TX_FIFO_1K	0x00040000
-#define EMAC_M1_TX_FIFO_512	0x00000000
-#define EMAC_M1_TR0_DEPEND	0x00010000	/* 0'x for single packet */
-#define EMAC_M1_TR0_MULTI	0x00008000
-#define EMAC_M1_TR1_DEPEND	0x00004000
-#define EMAC_M1_TR1_MULTI	0x00002000
+#define EMAC_MR1_FDE		0x80000000
+#define EMAC_MR1_ILE		0x40000000
+#define EMAC_MR1_VLE		0x20000000
+#define EMAC_MR1_EIFC		0x10000000
+#define EMAC_MR1_APP		0x08000000
+#define EMAC_MR1_AEMI		0x02000000
+#define EMAC_MR1_IST		0x01000000
+#define EMAC_MR1_MF_1000MBPS	0x00800000	/* 0's for 10MBPS */
+#define EMAC_MR1_MF_100MBPS	0x00400000
+#define EMAC_MR1_RFS_MASK	0x00300000
+#define EMAC_MR1_RFS_4K		0x00300000
+#define EMAC_MR1_RFS_2K		0x00200000
+#define EMAC_MR1_RFS_1K		0x00100000
+#define EMAC_MR1_RFS_512		0x00000000
+#define EMAC_MR1_TX_FIFO_MASK	0x000c0000
+#define EMAC_MR1_TX_FIFO_2K	0x00080000
+#define EMAC_MR1_TX_FIFO_1K	0x00040000
+#define EMAC_MR1_TX_FIFO_512	0x00000000
+#define EMAC_MR1_TR0_DEPEND	0x00010000	/* 0'x for single packet */
+#define EMAC_MR1_TR0_MULTI	0x00008000
+#define EMAC_MR1_TR1_DEPEND	0x00004000
+#define EMAC_MR1_TR1_MULTI	0x00002000
 #if defined(CONFIG_440EP) || defined(CONFIG_440GR)
-#define EMAC_M1_JUMBO_ENABLE	0x00001000
+#define EMAC_MR1_JUMBO_ENABLE	0x00001000
 #endif /* defined(CONFIG_440EP) || defined(CONFIG_440GR) */
 #endif /* defined(CONFIG_440GX) */
 
-#define EMAC_MR1_FIFO_MASK	(EMAC_M1_RFS_MASK | EMAC_M1_TX_FIFO_MASK)
+#define EMAC_MR1_FIFO_MASK	(EMAC_MR1_RFS_MASK | EMAC_MR1_TX_FIFO_MASK)
 #if defined(CONFIG_405EZ)
 /* 405EZ only supports 512 bytes fifos */
-#define EMAC_MR1_FIFO_SIZE	(EMAC_M1_RFS_512 | EMAC_M1_TX_FIFO_512)
+#define EMAC_MR1_FIFO_SIZE	(EMAC_MR1_RFS_512 | EMAC_MR1_TX_FIFO_512)
 #else
 /* Set receive fifo to 4k and tx fifo to 2k */
-#define EMAC_MR1_FIFO_SIZE	(EMAC_M1_RFS_4K | EMAC_M1_TX_FIFO_2K)
+#define EMAC_MR1_FIFO_SIZE	(EMAC_MR1_RFS_4K | EMAC_MR1_TX_FIFO_2K)
 #endif
 
 /* Transmit Mode Register 0 */
-#define EMAC_TXM0_GNP0		(0x80000000)
-#define EMAC_TXM0_GNP1		(0x40000000)
-#define EMAC_TXM0_GNPD		(0x20000000)
-#define EMAC_TXM0_FC		(0x10000000)
+#define EMAC_TMR0_GNP0		(0x80000000)
+#define EMAC_TMR0_GNP1		(0x40000000)
+#define EMAC_TMR0_GNPD		(0x20000000)
+#define EMAC_TMR0_FC		(0x10000000)
 
 /* Receive Mode Register */
 #define EMAC_RMR_SP		(0x80000000)