Merge tag 'v2024.07-rc4' into next

Prepare v2024.070-rc4
diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile
index cd7fcb3..624dadf 100644
--- a/arch/arm/dts/Makefile
+++ b/arch/arm/dts/Makefile
@@ -31,7 +31,6 @@
 dtb-$(CONFIG_TARGET_A5Y17LTE) += exynos78x0-axy17lte.dtb
 dtb-$(CONFIG_TARGET_A3Y17LTE) += exynos78x0-axy17lte.dtb
 dtb-$(CONFIG_TARGET_A7Y17LTE) += exynos78x0-axy17lte.dtb
-dtb-$(CONFIG_TARGET_E850_96) += exynos850-e850-96.dtb
 
 dtb-$(CONFIG_ARCH_APPLE) += \
 	t8103-j274.dtb \
@@ -97,9 +96,6 @@
 	rk3368-geekbox.dtb \
 	rk3368-px5-evb.dtb \
 
-dtb-$(CONFIG_ROCKCHIP_RV1126) += \
-	rv1126-edgeble-neu2-io.dtb
-
 dtb-$(CONFIG_ARCH_S5P4418) += \
 	s5p4418-nanopi2.dtb
 
@@ -1024,9 +1020,6 @@
 
 dtb-$(CONFIG_TARGET_DEVKIT8000) += omap3-devkit8000.dtb
 
-dtb-$(CONFIG_TARGET_OMAP3_IGEP00X0) += \
-	omap3-igep0020.dtb
-
 dtb-$(CONFIG_TARGET_OMAP4_PANDA) += \
 	omap4-panda.dtb \
 	omap4-panda-es.dtb
diff --git a/arch/arm/dts/exynos850-e850-96-u-boot.dtsi b/arch/arm/dts/exynos850-e850-96-u-boot.dtsi
index 7ad11e9..6d7148f 100644
--- a/arch/arm/dts/exynos850-e850-96-u-boot.dtsi
+++ b/arch/arm/dts/exynos850-e850-96-u-boot.dtsi
@@ -3,35 +3,7 @@
  * Copyright (c) 2023 Linaro Ltd.
  */
 
-&cmu_top {
-	bootph-all;
-};
-
-&cmu_peri {
-	bootph-all;
-};
-
-&oscclk {
-	bootph-all;
-};
-
-&pinctrl_alive {
-	bootph-all;
-};
-
 &pmu_system_controller {
 	bootph-all;
 	samsung,uart-debug-1;
 };
-
-&serial_0 {
-	bootph-all;
-};
-
-&uart1_pins {
-	bootph-all;
-};
-
-&usi_uart {
-	bootph-all;
-};
diff --git a/arch/arm/dts/exynos850-e850-96.dts b/arch/arm/dts/exynos850-e850-96.dts
deleted file mode 100644
index f074df8..0000000
--- a/arch/arm/dts/exynos850-e850-96.dts
+++ /dev/null
@@ -1,273 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0
-/*
- * WinLink E850-96 board device tree source
- *
- * Copyright (C) 2018 Samsung Electronics Co., Ltd.
- * Copyright (C) 2021 Linaro Ltd.
- *
- * Device tree source file for WinLink's E850-96 board which is based on
- * Samsung Exynos850 SoC.
- */
-
-/dts-v1/;
-
-#include "exynos850.dtsi"
-#include <dt-bindings/gpio/gpio.h>
-#include <dt-bindings/input/input.h>
-#include <dt-bindings/leds/common.h>
-
-/ {
-	model = "WinLink E850-96 board";
-	compatible = "winlink,e850-96", "samsung,exynos850";
-
-	aliases {
-		mmc0 = &mmc_0;
-		serial0 = &serial_0;
-	};
-
-	chosen {
-		stdout-path = &serial_0;
-	};
-
-	connector {
-		compatible = "gpio-usb-b-connector", "usb-b-connector";
-		label = "micro-USB";
-		type = "micro";
-		vbus-supply = <&reg_usb_host_vbus>;
-		id-gpios = <&gpa0 0 GPIO_ACTIVE_LOW>;
-		pinctrl-names = "default";
-		pinctrl-0 = <&micro_usb_det_pins>;
-
-		port {
-			usb_dr_connector: endpoint {
-				remote-endpoint = <&usb1_drd_sw>;
-			};
-		};
-	};
-
-	/*
-	 * RAM: 4 GiB (eMCP):
-	 *   - 2 GiB at 0x80000000
-	 *   - 2 GiB at 0x880000000
-	 *
-	 * 0xbab00000..0xbfffffff: secure memory (85 MiB).
-	 */
-	memory@80000000 {
-		device_type = "memory";
-		reg = <0x0 0x80000000 0x3ab00000>,
-		      <0x0 0xc0000000 0x40000000>,
-		      <0x8 0x80000000 0x80000000>;
-	};
-
-	gpio-keys {
-		compatible = "gpio-keys";
-		pinctrl-names = "default";
-		pinctrl-0 = <&key_voldown_pins &key_volup_pins>;
-
-		volume-down-key {
-			label = "Volume Down";
-			linux,code = <KEY_VOLUMEDOWN>;
-			gpios = <&gpa1 0 GPIO_ACTIVE_LOW>;
-		};
-
-		volume-up-key {
-			label = "Volume Up";
-			linux,code = <KEY_VOLUMEUP>;
-			gpios = <&gpa0 7 GPIO_ACTIVE_LOW>;
-		};
-	};
-
-	leds {
-		compatible = "gpio-leds";
-
-		/* HEART_BEAT_LED */
-		user_led1: led-1 {
-			label = "yellow:user1";
-			gpios = <&gpg2 2 GPIO_ACTIVE_HIGH>;
-			color = <LED_COLOR_ID_YELLOW>;
-			function = LED_FUNCTION_HEARTBEAT;
-			linux,default-trigger = "heartbeat";
-		};
-
-		/* eMMC_LED */
-		user_led2: led-2 {
-			label = "yellow:user2";
-			gpios = <&gpg2 3 GPIO_ACTIVE_HIGH>;
-			color = <LED_COLOR_ID_YELLOW>;
-			linux,default-trigger = "mmc0";
-		};
-
-		/* SD_LED */
-		user_led3: led-3 {
-			label = "white:user3";
-			gpios = <&gpg2 4 GPIO_ACTIVE_HIGH>;
-			color = <LED_COLOR_ID_WHITE>;
-			function = LED_FUNCTION_SD;
-			linux,default-trigger = "mmc2";
-		};
-
-		/* WIFI_LED */
-		wlan_active_led: led-4 {
-			label = "yellow:wlan";
-			gpios = <&gpg2 6 GPIO_ACTIVE_HIGH>;
-			color = <LED_COLOR_ID_YELLOW>;
-			function = LED_FUNCTION_WLAN;
-			linux,default-trigger = "phy0tx";
-			default-state = "off";
-		};
-
-		/* BLUETOOTH_LED */
-		bt_active_led: led-5 {
-			label = "blue:bt";
-			gpios = <&gpg2 7 GPIO_ACTIVE_HIGH>;
-			color = <LED_COLOR_ID_BLUE>;
-			function = LED_FUNCTION_BLUETOOTH;
-			linux,default-trigger = "hci0-power";
-			default-state = "off";
-		};
-	};
-
-	/* TODO: Remove this once PMIC is implemented  */
-	reg_dummy: regulator-0 {
-		compatible = "regulator-fixed";
-		regulator-name = "dummy_reg";
-	};
-
-	reg_usb_host_vbus: regulator-1 {
-		compatible = "regulator-fixed";
-		regulator-name = "usb_host_vbus";
-		regulator-min-microvolt = <5000000>;
-		regulator-max-microvolt = <5000000>;
-		gpio = <&gpa3 5 GPIO_ACTIVE_LOW>;
-	};
-
-	reserved-memory {
-		#address-cells = <2>;
-		#size-cells = <1>;
-		ranges;
-
-		ramoops@f0000000 {
-			compatible = "ramoops";
-			reg = <0x0 0xf0000000 0x200000>;
-			record-size = <0x20000>;
-			console-size = <0x20000>;
-			ftrace-size = <0x100000>;
-			pmsg-size = <0x20000>;
-		};
-	};
-
-	/*
-	 * RTC clock (XrtcXTI); external, must be 32.768 kHz.
-	 *
-	 * TODO: Remove this once RTC clock is implemented properly as part of
-	 *       PMIC driver.
-	 */
-	rtcclk: clock-rtcclk {
-		compatible = "fixed-clock";
-		clock-output-names = "rtcclk";
-		#clock-cells = <0>;
-		clock-frequency = <32768>;
-	};
-};
-
-&cmu_hsi {
-	clocks = <&oscclk>, <&rtcclk>,
-		 <&cmu_top CLK_DOUT_HSI_BUS>,
-		 <&cmu_top CLK_DOUT_HSI_MMC_CARD>,
-		 <&cmu_top CLK_DOUT_HSI_USB20DRD>;
-	clock-names = "oscclk", "rtcclk", "dout_hsi_bus",
-		      "dout_hsi_mmc_card", "dout_hsi_usb20drd";
-};
-
-&mmc_0 {
-	status = "okay";
-	mmc-hs200-1_8v;
-	mmc-hs400-1_8v;
-	cap-mmc-highspeed;
-	non-removable;
-	mmc-hs400-enhanced-strobe;
-	card-detect-delay = <200>;
-	clock-frequency = <800000000>;
-	bus-width = <8>;
-	samsung,dw-mshc-ciu-div = <3>;
-	samsung,dw-mshc-sdr-timing = <0 4>;
-	samsung,dw-mshc-ddr-timing = <2 4>;
-	samsung,dw-mshc-hs400-timing = <0 2>;
-
-	pinctrl-names = "default";
-	pinctrl-0 = <&sd0_clk_pins &sd0_cmd_pins &sd0_rdqs_pins &sd0_nreset_pins
-		     &sd0_bus1_pins &sd0_bus4_pins &sd0_bus8_pins>;
-};
-
-&oscclk {
-	clock-frequency = <26000000>;
-};
-
-&pinctrl_alive {
-	key_voldown_pins: key-voldown-pins {
-		samsung,pins = "gpa1-0";
-		samsung,pin-function = <EXYNOS_PIN_FUNC_EINT>;
-		samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
-		samsung,pin-drv = <EXYNOS5420_PIN_DRV_LV1>;
-	};
-
-	key_volup_pins: key-volup-pins {
-		samsung,pins = "gpa0-7";
-		samsung,pin-function = <EXYNOS_PIN_FUNC_EINT>;
-		samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
-		samsung,pin-drv = <EXYNOS5420_PIN_DRV_LV1>;
-	};
-
-	micro_usb_det_pins: micro-usb-det-pins {
-		samsung,pins = "gpa0-0";
-		samsung,pin-function = <EXYNOS_PIN_FUNC_INPUT>;
-		samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
-	};
-};
-
-&rtc {
-	status = "okay";
-	clocks = <&cmu_apm CLK_GOUT_RTC_PCLK>, <&rtcclk>;
-	clock-names = "rtc", "rtc_src";
-};
-
-&serial_0 {
-	status = "okay";
-	pinctrl-names = "default";
-	pinctrl-0 = <&uart1_pins>;
-};
-
-&usbdrd {
-	status = "okay";
-	vdd10-supply = <&reg_dummy>;
-	vdd33-supply = <&reg_dummy>;
-};
-
-&usbdrd_dwc3 {
-	dr_mode = "otg";
-	usb-role-switch;
-	role-switch-default-mode = "host";
-
-	port {
-		usb1_drd_sw: endpoint {
-			remote-endpoint = <&usb_dr_connector>;
-		};
-	};
-};
-
-&usbdrd_phy {
-	status = "okay";
-};
-
-&usi_uart {
-	samsung,clkreq-on; /* needed for UART mode */
-	status = "okay";
-};
-
-&watchdog_cl0 {
-	status = "okay";
-};
-
-&watchdog_cl1 {
-	status = "okay";
-};
diff --git a/arch/arm/dts/exynos850-pinctrl.dtsi b/arch/arm/dts/exynos850-pinctrl.dtsi
deleted file mode 100644
index 424bc80..0000000
--- a/arch/arm/dts/exynos850-pinctrl.dtsi
+++ /dev/null
@@ -1,663 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0
-/*
- * Samsung's Exynos850 SoC pin-mux and pin-config device tree source
- *
- * Copyright (C) 2017 Samsung Electronics Co., Ltd.
- * Copyright (C) 2021 Linaro Ltd.
- *
- * Samsung's Exynos850 SoC pin-mux and pin-config options are listed as device
- * tree nodes in this file.
- */
-
-#include <dt-bindings/interrupt-controller/arm-gic.h>
-#include "exynos-pinctrl.h"
-
-&pinctrl_alive {
-	gpa0: gpa0-gpio-bank {
-		gpio-controller;
-		#gpio-cells = <2>;
-
-		interrupt-controller;
-		#interrupt-cells = <2>;
-		interrupt-parent = <&gic>;
-		interrupts = <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>,
-			     <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>,
-			     <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>,
-			     <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>,
-			     <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>,
-			     <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>,
-			     <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>,
-			     <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
-	};
-
-	gpa1: gpa1-gpio-bank {
-		gpio-controller;
-		#gpio-cells = <2>;
-
-		interrupt-controller;
-		#interrupt-cells = <2>;
-		interrupt-parent = <&gic>;
-		interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>,
-			     <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>,
-			     <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>,
-			     <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>,
-			     <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>,
-			     <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>,
-			     <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>,
-			     <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
-	};
-
-	gpa2: gpa2-gpio-bank {
-		gpio-controller;
-		#gpio-cells = <2>;
-
-		interrupt-controller;
-		#interrupt-cells = <2>;
-		interrupt-parent = <&gic>;
-		interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>,
-			     <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>,
-			     <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>,
-			     <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>,
-			     <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>,
-			     <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>,
-			     <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>,
-			     <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
-	};
-
-	gpa3: gpa3-gpio-bank {
-		gpio-controller;
-		#gpio-cells = <2>;
-
-		interrupt-controller;
-		#interrupt-cells = <2>;
-		interrupt-parent = <&gic>;
-		interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>,
-			     <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>,
-			     <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>,
-			     <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>,
-			     <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>,
-			     <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>,
-			     <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>,
-			     <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
-	};
-
-	gpa4: gpa4-gpio-bank {
-		gpio-controller;
-		#gpio-cells = <2>;
-
-		interrupt-controller;
-		#interrupt-cells = <2>;
-		interrupt-parent = <&gic>;
-		interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>,
-			     <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>,
-			     <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>,
-			     <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
-	};
-
-	gpq0: gpq0-gpio-bank {
-		gpio-controller;
-		#gpio-cells = <2>;
-
-		interrupt-controller;
-		#interrupt-cells = <2>;
-	};
-
-	/* I2C5 (also called CAM_PMIC_I2C in TRM) */
-	i2c5_pins: i2c5-pins {
-		samsung,pins = "gpa3-5", "gpa3-6";
-		samsung,pin-function = <EXYNOS_PIN_FUNC_3>;
-		samsung,pin-pud = <EXYNOS_PIN_PULL_UP>;
-		samsung,pin-drv = <EXYNOS5420_PIN_DRV_LV1>;
-	};
-
-	/* I2C6 (also called MOTOR_I2C in TRM) */
-	i2c6_pins: i2c6-pins {
-		samsung,pins = "gpa3-7", "gpa4-0";
-		samsung,pin-function = <EXYNOS_PIN_FUNC_3>;
-		samsung,pin-pud = <EXYNOS_PIN_PULL_UP>;
-		samsung,pin-drv = <EXYNOS5420_PIN_DRV_LV1>;
-	};
-
-	/* USI: UART_DEBUG_0 pins */
-	uart0_pins: uart0-pins {
-		samsung,pins = "gpq0-0", "gpq0-1";
-		samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
-		samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
-	};
-
-	/* USI: UART_DEBUG_1 pins */
-	uart1_pins: uart1-pins {
-		samsung,pins = "gpa3-7", "gpa4-0";
-		samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
-		samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
-	};
-};
-
-&pinctrl_cmgp {
-	gpm0: gpm0-gpio-bank {
-		gpio-controller;
-		#gpio-cells = <2>;
-
-		interrupt-controller;
-		#interrupt-cells = <2>;
-		interrupt-parent = <&gic>;
-		interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>;
-	};
-
-	gpm1: gpm1-gpio-bank {
-		gpio-controller;
-		#gpio-cells = <2>;
-
-		interrupt-controller;
-		#interrupt-cells = <2>;
-		interrupt-parent = <&gic>;
-		interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>;
-	};
-
-	gpm2: gpm2-gpio-bank {
-		gpio-controller;
-		#gpio-cells = <2>;
-
-		interrupt-controller;
-		#interrupt-cells = <2>;
-		interrupt-parent = <&gic>;
-		interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>;
-	};
-
-	gpm3: gpm3-gpio-bank {
-		gpio-controller;
-		#gpio-cells = <2>;
-
-		interrupt-controller;
-		#interrupt-cells = <2>;
-		interrupt-parent = <&gic>;
-		interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>;
-	};
-
-	gpm4: gpm4-gpio-bank {
-		gpio-controller;
-		#gpio-cells = <2>;
-
-		interrupt-controller;
-		#interrupt-cells = <2>;
-		interrupt-parent = <&gic>;
-		interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>;
-	};
-
-	gpm5: gpm5-gpio-bank {
-		gpio-controller;
-		#gpio-cells = <2>;
-
-		interrupt-controller;
-		#interrupt-cells = <2>;
-		interrupt-parent = <&gic>;
-		interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>;
-	};
-
-	gpm6: gpm6-gpio-bank {
-		gpio-controller;
-		#gpio-cells = <2>;
-
-		interrupt-controller;
-		#interrupt-cells = <2>;
-		interrupt-parent = <&gic>;
-		interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
-	};
-
-	gpm7: gpm7-gpio-bank {
-		gpio-controller;
-		#gpio-cells = <2>;
-
-		interrupt-controller;
-		#interrupt-cells = <2>;
-		interrupt-parent = <&gic>;
-		interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>;
-	};
-
-	/* USI_CMGP0: HSI2C function */
-	hsi2c3_pins: hsi2c3-pins {
-		samsung,pins = "gpm0-0", "gpm1-0";
-		samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
-		samsung,pin-pud = <EXYNOS_PIN_PULL_UP>;
-		samsung,pin-drv = <EXYNOS5420_PIN_DRV_LV1>;
-	};
-
-	/* USI_CMGP0: UART function (4 pins, Auto Flow Control) */
-	uart1_single_pins: uart1-single-pins {
-		samsung,pins = "gpm0-0", "gpm1-0", "gpm2-0", "gpm3-0";
-		samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
-		samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
-	};
-
-	/* USI_CMGP0: UART function (2 pins, Non-Auto Flow Control) */
-	uart1_dual_pins: uart1-dual-pins {
-		samsung,pins = "gpm0-0", "gpm1-0";
-		samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
-		samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
-	};
-
-	/* USI_CMGP0: SPI function */
-	spi1_pins: spi1-pins {
-		samsung,pins = "gpm0-0", "gpm1-0", "gpm2-0", "gpm3-0";
-		samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
-		samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
-		samsung,pin-drv = <EXYNOS5420_PIN_DRV_LV1>;
-	};
-
-	/* USI_CMGP1: HSI2C function */
-	hsi2c4_pins: hsi2c4-pins {
-		samsung,pins = "gpm4-0", "gpm5-0";
-		samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
-		samsung,pin-pud = <EXYNOS_PIN_PULL_UP>;
-		samsung,pin-drv = <EXYNOS5420_PIN_DRV_LV1>;
-	};
-
-	/* USI_CMGP1: UART function (4 pins, Auto Flow Control) */
-	uart2_single_pins: uart2-single-pins {
-		samsung,pins = "gpm4-0", "gpm5-0", "gpm6-0", "gpm7-0";
-		samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
-		samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
-	};
-
-	/* USI_CMGP1: UART function (2 pins, Non-Auto Flow Control) */
-	uart2_dual_pins: uart2-dual-pins {
-		samsung,pins = "gpm4-0", "gpm5-0";
-		samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
-		samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
-	};
-
-	/* USI_CMGP1: SPI function */
-	spi2_pins: spi2-pins {
-		samsung,pins = "gpm4-0", "gpm5-0", "gpm6-0", "gpm7-0";
-		samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
-		samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
-		samsung,pin-drv = <EXYNOS5420_PIN_DRV_LV1>;
-	};
-};
-
-&pinctrl_aud {
-	gpb0: gpb0-gpio-bank {
-		gpio-controller;
-		#gpio-cells = <2>;
-
-		interrupt-controller;
-		#interrupt-cells = <2>;
-	};
-
-	gpb1: gpb1-gpio-bank {
-		gpio-controller;
-		#gpio-cells = <2>;
-
-		interrupt-controller;
-		#interrupt-cells = <2>;
-	};
-
-	aud_codec_mclk_pins: aud-codec-mclk-pins {
-		samsung,pins = "gpb0-0";
-		samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
-		samsung,pin-pud = <EXYNOS_PIN_PULL_DOWN>;
-	};
-
-	aud_codec_mclk_idle_pins: aud-codec-mclk-idle-pins {
-		samsung,pins = "gpb0-0";
-		samsung,pin-function = <EXYNOS_PIN_FUNC_INPUT>;
-		samsung,pin-pud = <EXYNOS_PIN_PULL_DOWN>;
-	};
-
-	aud_i2s0_pins: aud-i2s0-pins {
-		samsung,pins = "gpb0-1", "gpb0-2", "gpb0-3", "gpb0-4";
-		samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
-		samsung,pin-pud = <EXYNOS_PIN_PULL_DOWN>;
-	};
-
-	aud_i2s0_idle_pins: aud-i2s0-idle-pins {
-		samsung,pins = "gpb0-1", "gpb0-2", "gpb0-3", "gpb0-4";
-		samsung,pin-function = <EXYNOS_PIN_FUNC_INPUT>;
-		samsung,pin-pud = <EXYNOS_PIN_PULL_DOWN>;
-	};
-
-	aud_i2s1_pins: aud-i2s1-pins {
-		samsung,pins = "gpb1-0", "gpb1-1", "gpb1-2", "gpb1-3";
-		samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
-		samsung,pin-pud = <EXYNOS_PIN_PULL_DOWN>;
-	};
-
-	aud_i2s1_idle_pins: aud-i2s1-idle-pins {
-		samsung,pins = "gpb1-0", "gpb1-1", "gpb1-2", "gpb1-3";
-		samsung,pin-function = <EXYNOS_PIN_FUNC_INPUT>;
-		samsung,pin-pud = <EXYNOS_PIN_PULL_DOWN>;
-	};
-
-	aud_fm_pins: aud-fm-pins {
-		samsung,pins = "gpb1-4";
-		samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
-		samsung,pin-pud = <EXYNOS_PIN_PULL_DOWN>;
-	};
-
-	aud_fm_idle_pins: aud-fm-idle-pins {
-		samsung,pins = "gpb1-4";
-		samsung,pin-function = <EXYNOS_PIN_FUNC_INPUT>;
-		samsung,pin-pud = <EXYNOS_PIN_PULL_DOWN>;
-	};
-};
-
-&pinctrl_hsi {
-	gpf2: gpf2-gpio-bank {
-		gpio-controller;
-		#gpio-cells = <2>;
-
-		interrupt-controller;
-		#interrupt-cells = <2>;
-	};
-
-	sd2_clk_pins: sd2-clk-pins {
-		samsung,pins = "gpf2-0";
-		samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
-		samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
-		samsung,pin-drv = <EXYNOS850_HSI_PIN_DRV_LV2>;
-	};
-
-	sd2_cmd_pins: sd2-cmd-pins {
-		samsung,pins = "gpf2-1";
-		samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
-		samsung,pin-pud = <EXYNOS_PIN_PULL_UP>;
-		samsung,pin-drv = <EXYNOS850_HSI_PIN_DRV_LV2>;
-	 };
-
-	sd2_bus1_pins: sd2-bus1-pins {
-		samsung,pins = "gpf2-2";
-		samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
-		samsung,pin-pud = <EXYNOS_PIN_PULL_UP>;
-		samsung,pin-drv = <EXYNOS850_HSI_PIN_DRV_LV2>;
-	};
-
-	sd2_bus4_pins: sd2-bus4-pins {
-		samsung,pins = "gpf2-3", "gpf2-4", "gpf2-5";
-		samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
-		samsung,pin-pud = <EXYNOS_PIN_PULL_UP>;
-		samsung,pin-drv = <EXYNOS850_HSI_PIN_DRV_LV2>;
-	};
-
-	sd2_pdn_pins: sd2-pdn-pins {
-		samsung,pins = "gpf2-0", "gpf2-1", "gpf2-2", "gpf2-3",
-			       "gpf2-4", "gpf2-5";
-		samsung,pin-function = <EXYNOS_PIN_FUNC_INPUT>;
-		samsung,pin-pud = <EXYNOS_PIN_PULL_DOWN>;
-	};
-};
-
-&pinctrl_core {
-	gpf0: gpf0-gpio-bank {
-		gpio-controller;
-		#gpio-cells = <2>;
-
-		interrupt-controller;
-		#interrupt-cells = <2>;
-	};
-
-	gpf1: gpf1-gpio-bank {
-		gpio-controller;
-		#gpio-cells = <2>;
-
-		interrupt-controller;
-		#interrupt-cells = <2>;
-	};
-
-	sd0_clk_pins: sd0-clk-pins {
-		samsung,pins = "gpf0-0";
-		samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
-		samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
-		samsung,pin-drv = <EXYNOS5420_PIN_DRV_LV4>;
-	};
-
-	sd0_cmd_pins: sd0-cmd-pins {
-		samsung,pins = "gpf0-1";
-		samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
-		samsung,pin-pud = <EXYNOS_PIN_PULL_UP>;
-		samsung,pin-drv = <EXYNOS5420_PIN_DRV_LV4>;
-	};
-
-	sd0_rdqs_pins: sd0-rdqs-pins {
-		samsung,pins = "gpf0-2";
-		samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
-		samsung,pin-pud = <EXYNOS_PIN_PULL_DOWN>;
-		samsung,pin-drv = <EXYNOS5420_PIN_DRV_LV4>;
-	};
-
-	sd0_nreset_pins: sd0-nreset-pins {
-		samsung,pins = "gpf0-3";
-		samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
-		samsung,pin-pud = <EXYNOS_PIN_PULL_UP>;
-		samsung,pin-drv = <EXYNOS5420_PIN_DRV_LV4>;
-	};
-
-	sd0_bus1_pins: sd0-bus1-pins {
-		samsung,pins = "gpf1-0";
-		samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
-		samsung,pin-pud = <EXYNOS_PIN_PULL_UP>;
-		samsung,pin-drv = <EXYNOS5420_PIN_DRV_LV4>;
-	};
-
-	sd0_bus4_pins: sd0-bus4-pins {
-		samsung,pins = "gpf1-1", "gpf1-2", "gpf1-3";
-		samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
-		samsung,pin-pud = <EXYNOS_PIN_PULL_UP>;
-		samsung,pin-drv = <EXYNOS5420_PIN_DRV_LV4>;
-	};
-
-	sd0_bus8_pins: sd0-bus8-pins {
-		samsung,pins = "gpf1-4", "gpf1-5", "gpf1-6", "gpf1-7";
-		samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
-		samsung,pin-pud = <EXYNOS_PIN_PULL_UP>;
-		samsung,pin-drv = <EXYNOS5420_PIN_DRV_LV4>;
-	};
-};
-
-&pinctrl_peri {
-	gpc0: gpc0-gpio-bank {
-		gpio-controller;
-		#gpio-cells = <2>;
-
-		interrupt-controller;
-		#interrupt-cells = <2>;
-	};
-
-	gpc1: gpc1-gpio-bank {
-		gpio-controller;
-		#gpio-cells = <2>;
-
-		interrupt-controller;
-		#interrupt-cells = <2>;
-	};
-
-	gpg0: gpg0-gpio-bank {
-		gpio-controller;
-		#gpio-cells = <2>;
-
-		interrupt-controller;
-		#interrupt-cells = <2>;
-	};
-
-	gpg1: gpg1-gpio-bank {
-		gpio-controller;
-		#gpio-cells = <2>;
-
-		interrupt-controller;
-		#interrupt-cells = <2>;
-	};
-
-	gpg2: gpg2-gpio-bank {
-		gpio-controller;
-		#gpio-cells = <2>;
-
-		interrupt-controller;
-		#interrupt-cells = <2>;
-	};
-
-	gpg3: gpg3-gpio-bank {
-		gpio-controller;
-		#gpio-cells = <2>;
-
-		interrupt-controller;
-		#interrupt-cells = <2>;
-	};
-
-	gpp0: gpp0-gpio-bank {
-		gpio-controller;
-		#gpio-cells = <2>;
-
-		interrupt-controller;
-		#interrupt-cells = <2>;
-	};
-	gpp1: gpp1-gpio-bank {
-		gpio-controller;
-		#gpio-cells = <2>;
-
-		interrupt-controller;
-		#interrupt-cells = <2>;
-	};
-
-	gpp2: gpp2-gpio-bank {
-		gpio-controller;
-		#gpio-cells = <2>;
-
-		interrupt-controller;
-		#interrupt-cells = <2>;
-	};
-
-	sensor_mclk0_in_pins: sensor-mclk0-in-pins {
-		samsung,pins = "gpc0-0";
-		samsung,pin-function = <EXYNOS_PIN_FUNC_INPUT>;
-		samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
-		samsung,pin-drv = <EXYNOS5420_PIN_DRV_LV3>;
-	};
-
-	sensor_mclk0_out_pins: sensor-mclk0-out-pins {
-		samsung,pins = "gpc0-0";
-		samsung,pin-function = <EXYNOS_PIN_FUNC_OUTPUT>;
-		samsung,pin-pud = <EXYNOS_PIN_PULL_DOWN>;
-		samsung,pin-drv = <EXYNOS5420_PIN_DRV_LV3>;
-	};
-
-	sensor_mclk0_fn_pins: sensor-mclk0-fn-pins {
-		samsung,pins = "gpc0-0";
-		samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
-		samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
-		samsung,pin-drv = <EXYNOS5420_PIN_DRV_LV3>;
-	};
-
-	sensor_mclk1_in_pins: sensor-mclk1-in-pins {
-		samsung,pins = "gpc0-1";
-		samsung,pin-function = <EXYNOS_PIN_FUNC_INPUT>;
-		samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
-		samsung,pin-drv = <EXYNOS5420_PIN_DRV_LV3>;
-	};
-
-	sensor_mclk1_out_pins: sensor-mclk1-out-pins {
-		samsung,pins = "gpc0-1";
-		samsung,pin-function = <EXYNOS_PIN_FUNC_OUTPUT>;
-		samsung,pin-pud = <EXYNOS_PIN_PULL_DOWN>;
-		samsung,pin-drv = <EXYNOS5420_PIN_DRV_LV3>;
-	};
-
-	sensor_mclk1_fn_pins: sensor-mclk1-fn-pins {
-		samsung,pins = "gpc0-1";
-		samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
-		samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
-		samsung,pin-drv = <EXYNOS5420_PIN_DRV_LV3>;
-	};
-
-	sensor_mclk2_in_pins: sensor-mclk2-in-pins {
-		samsung,pins = "gpc0-2";
-		samsung,pin-function = <EXYNOS_PIN_FUNC_INPUT>;
-		samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
-		samsung,pin-drv = <EXYNOS5420_PIN_DRV_LV3>;
-	};
-
-	sensor_mclk2_out_pins: sensor-mclk2-out-pins {
-		samsung,pins = "gpc0-2";
-		samsung,pin-function = <EXYNOS_PIN_FUNC_OUTPUT>;
-		samsung,pin-pud = <EXYNOS_PIN_PULL_DOWN>;
-		samsung,pin-drv = <EXYNOS5420_PIN_DRV_LV3>;
-	};
-
-	sensor_mclk2_fn_pins: sensor-mclk2-fn-pins {
-		samsung,pins = "gpc0-2";
-		samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
-		samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
-		samsung,pin-drv = <EXYNOS5420_PIN_DRV_LV3>;
-	};
-
-	/* USI: HSI2C0 */
-	hsi2c0_pins: hsi2c0-pins {
-		samsung,pins = "gpc1-0", "gpc1-1";
-		samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
-		samsung,pin-pud = <EXYNOS_PIN_PULL_UP>;
-		samsung,pin-drv = <EXYNOS5420_PIN_DRV_LV1>;
-	};
-
-	/* USI: HSI2C1 */
-	hsi2c1_pins: hsi2c1-pins {
-		samsung,pins = "gpc1-2", "gpc1-3";
-		samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
-		samsung,pin-pud = <EXYNOS_PIN_PULL_UP>;
-		samsung,pin-drv = <EXYNOS5420_PIN_DRV_LV1>;
-	};
-
-	/* USI: HSI2C2 */
-	hsi2c2_pins: hsi2c2-pins {
-		samsung,pins = "gpc1-4", "gpc1-5";
-		samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
-		samsung,pin-pud = <EXYNOS_PIN_PULL_UP>;
-		samsung,pin-drv = <EXYNOS5420_PIN_DRV_LV1>;
-	};
-
-	/* USI: SPI */
-	spi0_pins: spi0-pins {
-		samsung,pins = "gpp2-0", "gpp2-1", "gpp2-2", "gpp2-3";
-		samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
-		samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
-		samsung,pin-drv = <EXYNOS5420_PIN_DRV_LV1>;
-	};
-
-	i2c0_pins: i2c0-pins {
-		samsung,pins = "gpp0-0", "gpp0-1";
-		samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
-		samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
-		samsung,pin-drv = <EXYNOS5420_PIN_DRV_LV1>;
-	};
-
-	i2c1_pins: i2c1-pins {
-		samsung,pins = "gpp0-2", "gpp0-3";
-		samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
-		samsung,pin-pud = <EXYNOS_PIN_PULL_UP>;
-		samsung,pin-drv = <EXYNOS5420_PIN_DRV_LV1>;
-	};
-
-	i2c2_pins: i2c2-pins {
-		samsung,pins = "gpp0-4", "gpp0-5";
-		samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
-		samsung,pin-pud = <EXYNOS_PIN_PULL_UP>;
-		samsung,pin-drv = <EXYNOS5420_PIN_DRV_LV1>;
-	};
-
-	i2c3_pins: i2c3-pins {
-		samsung,pins = "gpp1-0", "gpp1-1";
-		samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
-		samsung,pin-pud = <EXYNOS_PIN_PULL_UP>;
-		samsung,pin-drv = <EXYNOS5420_PIN_DRV_LV1>;
-	};
-
-	i2c4_pins: i2c4-pins {
-		samsung,pins = "gpp1-2", "gpp1-3";
-		samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
-		samsung,pin-pud = <EXYNOS_PIN_PULL_UP>;
-		samsung,pin-drv = <EXYNOS5420_PIN_DRV_LV1>;
-	};
-
-	xclkout_pins: xclkout-pins {
-		samsung,pins = "gpq0-2";
-		samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
-		samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
-	};
-};
diff --git a/arch/arm/dts/exynos850.dtsi b/arch/arm/dts/exynos850.dtsi
deleted file mode 100644
index 53104e6..0000000
--- a/arch/arm/dts/exynos850.dtsi
+++ /dev/null
@@ -1,809 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0
-/*
- * Samsung Exynos850 SoC device tree source
- *
- * Copyright (C) 2018 Samsung Electronics Co., Ltd.
- * Copyright (C) 2021 Linaro Ltd.
- *
- * Samsung Exynos850 SoC device nodes are listed in this file.
- * Exynos850 based board files can include this file and provide
- * values for board specific bindings.
- */
-
-#include <dt-bindings/clock/exynos850.h>
-#include <dt-bindings/interrupt-controller/arm-gic.h>
-#include <dt-bindings/soc/samsung,exynos-usi.h>
-
-/ {
-	/* Also known under engineering name Exynos3830 */
-	compatible = "samsung,exynos850";
-	#address-cells = <2>;
-	#size-cells = <1>;
-
-	interrupt-parent = <&gic>;
-
-	aliases {
-		pinctrl0 = &pinctrl_alive;
-		pinctrl1 = &pinctrl_cmgp;
-		pinctrl2 = &pinctrl_aud;
-		pinctrl3 = &pinctrl_hsi;
-		pinctrl4 = &pinctrl_core;
-		pinctrl5 = &pinctrl_peri;
-	};
-
-	arm-pmu {
-		compatible = "arm,cortex-a55-pmu";
-		interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>,
-			     <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>,
-			     <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>,
-			     <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>,
-			     <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>,
-			     <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>,
-			     <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>,
-			     <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>;
-		interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>,
-				     <&cpu4>, <&cpu5>, <&cpu6>, <&cpu7>;
-	};
-
-	/* Main system clock (XTCXO); external, must be 26 MHz */
-	oscclk: clock-oscclk {
-		compatible = "fixed-clock";
-		clock-output-names = "oscclk";
-		#clock-cells = <0>;
-	};
-
-	cpus {
-		#address-cells = <1>;
-		#size-cells = <0>;
-
-		cpu-map {
-			cluster0 {
-				core0 {
-					cpu = <&cpu0>;
-				};
-				core1 {
-					cpu = <&cpu1>;
-				};
-				core2 {
-					cpu = <&cpu2>;
-				};
-				core3 {
-					cpu = <&cpu3>;
-				};
-			};
-
-			cluster1 {
-				core0 {
-					cpu = <&cpu4>;
-				};
-				core1 {
-					cpu = <&cpu5>;
-				};
-				core2 {
-					cpu = <&cpu6>;
-				};
-				core3 {
-					cpu = <&cpu7>;
-				};
-			};
-		};
-
-		cpu0: cpu@0 {
-			device_type = "cpu";
-			compatible = "arm,cortex-a55";
-			reg = <0x0>;
-			enable-method = "psci";
-		};
-		cpu1: cpu@1 {
-			device_type = "cpu";
-			compatible = "arm,cortex-a55";
-			reg = <0x1>;
-			enable-method = "psci";
-		};
-		cpu2: cpu@2 {
-			device_type = "cpu";
-			compatible = "arm,cortex-a55";
-			reg = <0x2>;
-			enable-method = "psci";
-		};
-		cpu3: cpu@3 {
-			device_type = "cpu";
-			compatible = "arm,cortex-a55";
-			reg = <0x3>;
-			enable-method = "psci";
-		};
-		cpu4: cpu@100 {
-			device_type = "cpu";
-			compatible = "arm,cortex-a55";
-			reg = <0x100>;
-			enable-method = "psci";
-		};
-		cpu5: cpu@101 {
-			device_type = "cpu";
-			compatible = "arm,cortex-a55";
-			reg = <0x101>;
-			enable-method = "psci";
-		};
-		cpu6: cpu@102 {
-			device_type = "cpu";
-			compatible = "arm,cortex-a55";
-			reg = <0x102>;
-			enable-method = "psci";
-		};
-		cpu7: cpu@103 {
-			device_type = "cpu";
-			compatible = "arm,cortex-a55";
-			reg = <0x103>;
-			enable-method = "psci";
-		};
-	};
-
-	psci {
-		compatible = "arm,psci-1.0";
-		method = "smc";
-	};
-
-	timer {
-		compatible = "arm,armv8-timer";
-		/* Hypervisor Virtual Timer interrupt is not wired to GIC */
-		interrupts =
-		     <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
-		     <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
-		     <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
-		     <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>;
-	};
-
-	soc: soc@0 {
-		compatible = "simple-bus";
-		#address-cells = <1>;
-		#size-cells = <1>;
-		ranges = <0x0 0x0 0x0 0x20000000>;
-
-		chipid@10000000 {
-			compatible = "samsung,exynos850-chipid";
-			reg = <0x10000000 0x100>;
-		};
-
-		timer@10040000 {
-			compatible = "samsung,exynos850-mct",
-				     "samsung,exynos4210-mct";
-			reg = <0x10040000 0x800>;
-			interrupts = <GIC_SPI 203 IRQ_TYPE_LEVEL_HIGH>,
-				     <GIC_SPI 204 IRQ_TYPE_LEVEL_HIGH>,
-				     <GIC_SPI 205 IRQ_TYPE_LEVEL_HIGH>,
-				     <GIC_SPI 206 IRQ_TYPE_LEVEL_HIGH>,
-				     <GIC_SPI 207 IRQ_TYPE_LEVEL_HIGH>,
-				     <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>,
-				     <GIC_SPI 209 IRQ_TYPE_LEVEL_HIGH>,
-				     <GIC_SPI 210 IRQ_TYPE_LEVEL_HIGH>,
-				     <GIC_SPI 211 IRQ_TYPE_LEVEL_HIGH>,
-				     <GIC_SPI 212 IRQ_TYPE_LEVEL_HIGH>,
-				     <GIC_SPI 213 IRQ_TYPE_LEVEL_HIGH>,
-				     <GIC_SPI 214 IRQ_TYPE_LEVEL_HIGH>;
-			clocks = <&oscclk>, <&cmu_peri CLK_GOUT_MCT_PCLK>;
-			clock-names = "fin_pll", "mct";
-		};
-
-		gic: interrupt-controller@12a01000 {
-			compatible = "arm,gic-400";
-			#interrupt-cells = <3>;
-			#address-cells = <0>;
-			reg = <0x12a01000 0x1000>,
-			      <0x12a02000 0x2000>,
-			      <0x12a04000 0x2000>,
-			      <0x12a06000 0x2000>;
-			interrupt-controller;
-			interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(8) |
-						 IRQ_TYPE_LEVEL_HIGH)>;
-		};
-
-		pmu_system_controller: system-controller@11860000 {
-			compatible = "samsung,exynos850-pmu", "syscon";
-			reg = <0x11860000 0x10000>;
-
-			reboot: syscon-reboot {
-				compatible = "syscon-reboot";
-				regmap = <&pmu_system_controller>;
-				offset = <0x3a00>; /* SYSTEM_CONFIGURATION */
-				mask = <0x2>; /* SWRESET_SYSTEM */
-				value = <0x2>; /* reset value */
-			};
-		};
-
-		watchdog_cl0: watchdog@10050000 {
-			compatible = "samsung,exynos850-wdt";
-			reg = <0x10050000 0x100>;
-			interrupts = <GIC_SPI 228 IRQ_TYPE_LEVEL_HIGH>;
-			clocks = <&cmu_peri CLK_GOUT_WDT0_PCLK>, <&oscclk>;
-			clock-names = "watchdog", "watchdog_src";
-			samsung,syscon-phandle = <&pmu_system_controller>;
-			samsung,cluster-index = <0>;
-			status = "disabled";
-		};
-
-		watchdog_cl1: watchdog@10060000 {
-			compatible = "samsung,exynos850-wdt";
-			reg = <0x10060000 0x100>;
-			interrupts = <GIC_SPI 229 IRQ_TYPE_LEVEL_HIGH>;
-			clocks = <&cmu_peri CLK_GOUT_WDT1_PCLK>, <&oscclk>;
-			clock-names = "watchdog", "watchdog_src";
-			samsung,syscon-phandle = <&pmu_system_controller>;
-			samsung,cluster-index = <1>;
-			status = "disabled";
-		};
-
-		cmu_peri: clock-controller@10030000 {
-			compatible = "samsung,exynos850-cmu-peri";
-			reg = <0x10030000 0x8000>;
-			#clock-cells = <1>;
-
-			clocks = <&oscclk>, <&cmu_top CLK_DOUT_PERI_BUS>,
-				 <&cmu_top CLK_DOUT_PERI_UART>,
-				 <&cmu_top CLK_DOUT_PERI_IP>;
-			clock-names = "oscclk", "dout_peri_bus",
-				      "dout_peri_uart", "dout_peri_ip";
-		};
-
-		cmu_g3d: clock-controller@11400000 {
-			compatible = "samsung,exynos850-cmu-g3d";
-			reg = <0x11400000 0x8000>;
-			#clock-cells = <1>;
-
-			clocks = <&oscclk>, <&cmu_top CLK_DOUT_G3D_SWITCH>;
-			clock-names = "oscclk", "dout_g3d_switch";
-		};
-
-		cmu_apm: clock-controller@11800000 {
-			compatible = "samsung,exynos850-cmu-apm";
-			reg = <0x11800000 0x8000>;
-			#clock-cells = <1>;
-
-			clocks = <&oscclk>, <&cmu_top CLK_DOUT_CLKCMU_APM_BUS>;
-			clock-names = "oscclk", "dout_clkcmu_apm_bus";
-		};
-
-		cmu_cmgp: clock-controller@11c00000 {
-			compatible = "samsung,exynos850-cmu-cmgp";
-			reg = <0x11c00000 0x8000>;
-			#clock-cells = <1>;
-
-			clocks = <&oscclk>, <&cmu_apm CLK_GOUT_CLKCMU_CMGP_BUS>;
-			clock-names = "oscclk", "gout_clkcmu_cmgp_bus";
-		};
-
-		cmu_core: clock-controller@12000000 {
-			compatible = "samsung,exynos850-cmu-core";
-			reg = <0x12000000 0x8000>;
-			#clock-cells = <1>;
-
-			clocks = <&oscclk>, <&cmu_top CLK_DOUT_CORE_BUS>,
-				 <&cmu_top CLK_DOUT_CORE_CCI>,
-				 <&cmu_top CLK_DOUT_CORE_MMC_EMBD>,
-				 <&cmu_top CLK_DOUT_CORE_SSS>;
-			clock-names = "oscclk", "dout_core_bus",
-				      "dout_core_cci", "dout_core_mmc_embd",
-				      "dout_core_sss";
-		};
-
-		cmu_top: clock-controller@120e0000 {
-			compatible = "samsung,exynos850-cmu-top";
-			reg = <0x120e0000 0x8000>;
-			#clock-cells = <1>;
-
-			clocks = <&oscclk>;
-			clock-names = "oscclk";
-		};
-
-		cmu_mfcmscl: clock-controller@12c00000 {
-			compatible = "samsung,exynos850-cmu-mfcmscl";
-			reg = <0x12c00000 0x8000>;
-			#clock-cells = <1>;
-
-			clocks = <&oscclk>,
-				 <&cmu_top CLK_DOUT_MFCMSCL_MFC>,
-				 <&cmu_top CLK_DOUT_MFCMSCL_M2M>,
-				 <&cmu_top CLK_DOUT_MFCMSCL_MCSC>,
-				 <&cmu_top CLK_DOUT_MFCMSCL_JPEG>;
-			clock-names = "oscclk", "dout_mfcmscl_mfc",
-				      "dout_mfcmscl_m2m", "dout_mfcmscl_mcsc",
-				      "dout_mfcmscl_jpeg";
-		};
-
-		cmu_dpu: clock-controller@13000000 {
-			compatible = "samsung,exynos850-cmu-dpu";
-			reg = <0x13000000 0x8000>;
-			#clock-cells = <1>;
-
-			clocks = <&oscclk>, <&cmu_top CLK_DOUT_DPU>;
-			clock-names = "oscclk", "dout_dpu";
-		};
-
-		cmu_hsi: clock-controller@13400000 {
-			compatible = "samsung,exynos850-cmu-hsi";
-			reg = <0x13400000 0x8000>;
-			#clock-cells = <1>;
-
-			clocks = <&oscclk>,
-				 <&cmu_top CLK_DOUT_HSI_BUS>,
-				 <&cmu_top CLK_DOUT_HSI_MMC_CARD>,
-				 <&cmu_top CLK_DOUT_HSI_USB20DRD>;
-			clock-names = "oscclk", "dout_hsi_bus",
-				      "dout_hsi_mmc_card", "dout_hsi_usb20drd";
-		};
-
-		cmu_is: clock-controller@14500000 {
-			compatible = "samsung,exynos850-cmu-is";
-			reg = <0x14500000 0x8000>;
-			#clock-cells = <1>;
-
-			clocks = <&oscclk>,
-				 <&cmu_top CLK_DOUT_IS_BUS>,
-				 <&cmu_top CLK_DOUT_IS_ITP>,
-				 <&cmu_top CLK_DOUT_IS_VRA>,
-				 <&cmu_top CLK_DOUT_IS_GDC>;
-			clock-names = "oscclk", "dout_is_bus", "dout_is_itp",
-				      "dout_is_vra", "dout_is_gdc";
-		};
-
-		cmu_aud: clock-controller@14a00000 {
-			compatible = "samsung,exynos850-cmu-aud";
-			reg = <0x14a00000 0x8000>;
-			#clock-cells = <1>;
-
-			clocks = <&oscclk>, <&cmu_top CLK_DOUT_AUD>;
-			clock-names = "oscclk", "dout_aud";
-		};
-
-		pinctrl_alive: pinctrl@11850000 {
-			compatible = "samsung,exynos850-pinctrl";
-			reg = <0x11850000 0x1000>;
-
-			wakeup-interrupt-controller {
-				compatible = "samsung,exynos850-wakeup-eint";
-			};
-		};
-
-		pinctrl_cmgp: pinctrl@11c30000 {
-			compatible = "samsung,exynos850-pinctrl";
-			reg = <0x11c30000 0x1000>;
-
-			wakeup-interrupt-controller {
-				compatible = "samsung,exynos850-wakeup-eint";
-			};
-		};
-
-		pinctrl_core: pinctrl@12070000 {
-			compatible = "samsung,exynos850-pinctrl";
-			reg = <0x12070000 0x1000>;
-			interrupts = <GIC_SPI 451 IRQ_TYPE_LEVEL_HIGH>;
-		};
-
-		pinctrl_hsi: pinctrl@13430000 {
-			compatible = "samsung,exynos850-pinctrl";
-			reg = <0x13430000 0x1000>;
-			interrupts = <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>;
-		};
-
-		pinctrl_peri: pinctrl@139b0000 {
-			compatible = "samsung,exynos850-pinctrl";
-			reg = <0x139b0000 0x1000>;
-			interrupts = <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>;
-		};
-
-		pinctrl_aud: pinctrl@14a60000 {
-			compatible = "samsung,exynos850-pinctrl";
-			reg = <0x14a60000 0x1000>;
-		};
-
-		rtc: rtc@11a30000 {
-			compatible = "samsung,s3c6410-rtc";
-			reg = <0x11a30000 0x100>;
-			interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>,
-				     <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>;
-			clocks = <&cmu_apm CLK_GOUT_RTC_PCLK>;
-			clock-names = "rtc";
-			status = "disabled";
-		};
-
-		mmc_0: mmc@12100000 {
-			compatible = "samsung,exynos7-dw-mshc-smu";
-			reg = <0x12100000 0x2000>;
-			interrupts = <GIC_SPI 452 IRQ_TYPE_LEVEL_HIGH>;
-			#address-cells = <1>;
-			#size-cells = <0>;
-			clocks = <&cmu_core CLK_GOUT_MMC_EMBD_ACLK>,
-				 <&cmu_core CLK_GOUT_MMC_EMBD_SDCLKIN>;
-			clock-names = "biu", "ciu";
-			fifo-depth = <0x40>;
-			status = "disabled";
-		};
-
-		i2c_0: i2c@13830000 {
-			compatible = "samsung,s3c2440-i2c";
-			reg = <0x13830000 0x100>;
-			interrupts = <GIC_SPI 196 IRQ_TYPE_LEVEL_HIGH>;
-			#address-cells = <1>;
-			#size-cells = <0>;
-			pinctrl-names = "default";
-			pinctrl-0 = <&i2c0_pins>;
-			clocks = <&cmu_peri CLK_GOUT_I2C0_PCLK>;
-			clock-names = "i2c";
-			status = "disabled";
-		};
-
-		i2c_1: i2c@13840000 {
-			compatible = "samsung,s3c2440-i2c";
-			reg = <0x13840000 0x100>;
-			interrupts = <GIC_SPI 197 IRQ_TYPE_LEVEL_HIGH>;
-			#address-cells = <1>;
-			#size-cells = <0>;
-			pinctrl-names = "default";
-			pinctrl-0 = <&i2c1_pins>;
-			clocks = <&cmu_peri CLK_GOUT_I2C1_PCLK>;
-			clock-names = "i2c";
-			status = "disabled";
-		};
-
-		i2c_2: i2c@13850000 {
-			compatible = "samsung,s3c2440-i2c";
-			reg = <0x13850000 0x100>;
-			interrupts = <GIC_SPI 198 IRQ_TYPE_LEVEL_HIGH>;
-			#address-cells = <1>;
-			#size-cells = <0>;
-			pinctrl-names = "default";
-			pinctrl-0 = <&i2c2_pins>;
-			clocks = <&cmu_peri CLK_GOUT_I2C2_PCLK>;
-			clock-names = "i2c";
-			status = "disabled";
-		};
-
-		i2c_3: i2c@13860000 {
-			compatible = "samsung,s3c2440-i2c";
-			reg = <0x13860000 0x100>;
-			interrupts = <GIC_SPI 199 IRQ_TYPE_LEVEL_HIGH>;
-			#address-cells = <1>;
-			#size-cells = <0>;
-			pinctrl-names = "default";
-			pinctrl-0 = <&i2c3_pins>;
-			clocks = <&cmu_peri CLK_GOUT_I2C3_PCLK>;
-			clock-names = "i2c";
-			status = "disabled";
-		};
-
-		i2c_4: i2c@13870000 {
-			compatible = "samsung,s3c2440-i2c";
-			reg = <0x13870000 0x100>;
-			interrupts = <GIC_SPI 200 IRQ_TYPE_LEVEL_HIGH>;
-			#address-cells = <1>;
-			#size-cells = <0>;
-			pinctrl-names = "default";
-			pinctrl-0 = <&i2c4_pins>;
-			clocks = <&cmu_peri CLK_GOUT_I2C4_PCLK>;
-			clock-names = "i2c";
-			status = "disabled";
-		};
-
-		/* I2C_5 (also called CAM_PMIC_I2C in TRM) */
-		i2c_5: i2c@13880000 {
-			compatible = "samsung,s3c2440-i2c";
-			reg = <0x13880000 0x100>;
-			interrupts = <GIC_SPI 201 IRQ_TYPE_LEVEL_HIGH>;
-			#address-cells = <1>;
-			#size-cells = <0>;
-			pinctrl-names = "default";
-			pinctrl-0 = <&i2c5_pins>;
-			clocks = <&cmu_peri CLK_GOUT_I2C5_PCLK>;
-			clock-names = "i2c";
-			status = "disabled";
-		};
-
-		/* I2C_6 (also called MOTOR_I2C in TRM) */
-		i2c_6: i2c@13890000 {
-			compatible = "samsung,s3c2440-i2c";
-			reg = <0x13890000 0x100>;
-			interrupts = <GIC_SPI 202 IRQ_TYPE_LEVEL_HIGH>;
-			#address-cells = <1>;
-			#size-cells = <0>;
-			pinctrl-names = "default";
-			pinctrl-0 = <&i2c6_pins>;
-			clocks = <&cmu_peri CLK_GOUT_I2C6_PCLK>;
-			clock-names = "i2c";
-			status = "disabled";
-		};
-
-		sysmmu_mfcmscl: sysmmu@12c50000 {
-			compatible = "samsung,exynos-sysmmu";
-			reg = <0x12c50000 0x9000>;
-			interrupts = <GIC_SPI 174 IRQ_TYPE_LEVEL_HIGH>;
-			clock-names = "sysmmu";
-			clocks = <&cmu_mfcmscl CLK_GOUT_MFCMSCL_SYSMMU_CLK>;
-			#iommu-cells = <0>;
-		};
-
-		sysmmu_dpu: sysmmu@130c0000 {
-			compatible = "samsung,exynos-sysmmu";
-			reg = <0x130c0000 0x9000>;
-			interrupts = <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>;
-			clock-names = "sysmmu";
-			clocks = <&cmu_dpu CLK_GOUT_DPU_SMMU_CLK>;
-			#iommu-cells = <0>;
-		};
-
-		sysmmu_is0: sysmmu@14550000 {
-			compatible = "samsung,exynos-sysmmu";
-			reg = <0x14550000 0x9000>;
-			interrupts = <GIC_SPI 164 IRQ_TYPE_LEVEL_HIGH>;
-			clock-names = "sysmmu";
-			clocks = <&cmu_is CLK_GOUT_IS_SYSMMU_IS0_CLK>;
-			#iommu-cells = <0>;
-		};
-
-		sysmmu_is1: sysmmu@14570000 {
-			compatible = "samsung,exynos-sysmmu";
-			reg = <0x14570000 0x9000>;
-			interrupts = <GIC_SPI 166 IRQ_TYPE_LEVEL_HIGH>;
-			clock-names = "sysmmu";
-			clocks = <&cmu_is CLK_GOUT_IS_SYSMMU_IS1_CLK>;
-			#iommu-cells = <0>;
-		};
-
-		sysmmu_aud: sysmmu@14850000 {
-			compatible = "samsung,exynos-sysmmu";
-			reg = <0x14850000 0x9000>;
-			interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>;
-			clock-names = "sysmmu";
-			clocks = <&cmu_aud CLK_GOUT_AUD_SYSMMU_CLK>;
-			#iommu-cells = <0>;
-		};
-
-		sysreg_peri: syscon@10020000 {
-			compatible = "samsung,exynos850-peri-sysreg",
-				     "samsung,exynos850-sysreg", "syscon";
-			reg = <0x10020000 0x10000>;
-			clocks = <&cmu_peri CLK_GOUT_SYSREG_PERI_PCLK>;
-		};
-
-		sysreg_cmgp: syscon@11c20000 {
-			compatible = "samsung,exynos850-cmgp-sysreg",
-				     "samsung,exynos850-sysreg", "syscon";
-			reg = <0x11c20000 0x10000>;
-			clocks = <&cmu_cmgp CLK_GOUT_SYSREG_CMGP_PCLK>;
-		};
-
-		usbdrd: usb@13600000 {
-			compatible = "samsung,exynos850-dwusb3";
-			ranges = <0x0 0x13600000 0x10000>;
-			clocks = <&cmu_hsi CLK_GOUT_USB_BUS_EARLY_CLK>,
-				 <&cmu_hsi CLK_GOUT_USB_REF_CLK>;
-			clock-names = "bus_early", "ref";
-			#address-cells = <1>;
-			#size-cells = <1>;
-			status = "disabled";
-
-			usbdrd_dwc3: usb@0 {
-				compatible = "snps,dwc3";
-				reg = <0x0 0x10000>;
-				interrupts = <GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>;
-				phys = <&usbdrd_phy 0>;
-				phy-names = "usb2-phy";
-			};
-		};
-
-		usbdrd_phy: phy@135d0000 {
-			compatible = "samsung,exynos850-usbdrd-phy";
-			reg = <0x135d0000 0x100>;
-			clocks = <&cmu_hsi CLK_GOUT_USB_PHY_ACLK>,
-				 <&cmu_hsi CLK_GOUT_USB_PHY_REF_CLK>;
-			clock-names = "phy", "ref";
-			samsung,pmu-syscon = <&pmu_system_controller>;
-			#phy-cells = <1>;
-			status = "disabled";
-		};
-
-		usi_uart: usi@138200c0 {
-			compatible = "samsung,exynos850-usi";
-			reg = <0x138200c0 0x20>;
-			samsung,sysreg = <&sysreg_peri 0x1010>;
-			samsung,mode = <USI_V2_UART>;
-			#address-cells = <1>;
-			#size-cells = <1>;
-			ranges;
-			clocks = <&cmu_peri CLK_GOUT_UART_PCLK>,
-				 <&cmu_peri CLK_GOUT_UART_IPCLK>;
-			clock-names = "pclk", "ipclk";
-			status = "disabled";
-
-			serial_0: serial@13820000 {
-				compatible = "samsung,exynos850-uart";
-				reg = <0x13820000 0xc0>;
-				interrupts = <GIC_SPI 227 IRQ_TYPE_LEVEL_HIGH>;
-				pinctrl-names = "default";
-				pinctrl-0 = <&uart0_pins>;
-				clocks = <&cmu_peri CLK_GOUT_UART_PCLK>,
-					 <&cmu_peri CLK_GOUT_UART_IPCLK>;
-				clock-names = "uart", "clk_uart_baud0";
-				status = "disabled";
-			};
-		};
-
-		usi_hsi2c_0: usi@138a00c0 {
-			compatible = "samsung,exynos850-usi";
-			reg = <0x138a00c0 0x20>;
-			samsung,sysreg = <&sysreg_peri 0x1020>;
-			samsung,mode = <USI_V2_I2C>;
-			#address-cells = <1>;
-			#size-cells = <1>;
-			ranges;
-			clocks = <&cmu_peri CLK_GOUT_HSI2C0_PCLK>,
-				 <&cmu_peri CLK_GOUT_HSI2C0_IPCLK>;
-			clock-names = "pclk", "ipclk";
-			status = "disabled";
-
-			hsi2c_0: i2c@138a0000 {
-				compatible = "samsung,exynosautov9-hsi2c";
-				reg = <0x138a0000 0xc0>;
-				interrupts = <GIC_SPI 193 IRQ_TYPE_LEVEL_HIGH>;
-				#address-cells = <1>;
-				#size-cells = <0>;
-				pinctrl-names = "default";
-				pinctrl-0 = <&hsi2c0_pins>;
-				clocks = <&cmu_peri CLK_GOUT_HSI2C0_IPCLK>,
-					 <&cmu_peri CLK_GOUT_HSI2C0_PCLK>;
-				clock-names = "hsi2c", "hsi2c_pclk";
-				status = "disabled";
-			};
-		};
-
-		usi_hsi2c_1: usi@138b00c0 {
-			compatible = "samsung,exynos850-usi";
-			reg = <0x138b00c0 0x20>;
-			samsung,sysreg = <&sysreg_peri 0x1030>;
-			samsung,mode = <USI_V2_I2C>;
-			#address-cells = <1>;
-			#size-cells = <1>;
-			ranges;
-			clocks = <&cmu_peri CLK_GOUT_HSI2C1_PCLK>,
-				 <&cmu_peri CLK_GOUT_HSI2C1_IPCLK>;
-			clock-names = "pclk", "ipclk";
-			status = "disabled";
-
-			hsi2c_1: i2c@138b0000 {
-				compatible = "samsung,exynosautov9-hsi2c";
-				reg = <0x138b0000 0xc0>;
-				interrupts = <GIC_SPI 194 IRQ_TYPE_LEVEL_HIGH>;
-				#address-cells = <1>;
-				#size-cells = <0>;
-				pinctrl-names = "default";
-				pinctrl-0 = <&hsi2c1_pins>;
-				clocks = <&cmu_peri CLK_GOUT_HSI2C1_IPCLK>,
-					 <&cmu_peri CLK_GOUT_HSI2C1_PCLK>;
-				clock-names = "hsi2c", "hsi2c_pclk";
-				status = "disabled";
-			};
-		};
-
-		usi_hsi2c_2: usi@138c00c0 {
-			compatible = "samsung,exynos850-usi";
-			reg = <0x138c00c0 0x20>;
-			samsung,sysreg = <&sysreg_peri 0x1040>;
-			samsung,mode = <USI_V2_I2C>;
-			#address-cells = <1>;
-			#size-cells = <1>;
-			ranges;
-			clocks = <&cmu_peri CLK_GOUT_HSI2C2_PCLK>,
-				 <&cmu_peri CLK_GOUT_HSI2C2_IPCLK>;
-			clock-names = "pclk", "ipclk";
-			status = "disabled";
-
-			hsi2c_2: i2c@138c0000 {
-				compatible = "samsung,exynosautov9-hsi2c";
-				reg = <0x138c0000 0xc0>;
-				interrupts = <GIC_SPI 195 IRQ_TYPE_LEVEL_HIGH>;
-				#address-cells = <1>;
-				#size-cells = <0>;
-				pinctrl-names = "default";
-				pinctrl-0 = <&hsi2c2_pins>;
-				clocks = <&cmu_peri CLK_GOUT_HSI2C2_IPCLK>,
-					 <&cmu_peri CLK_GOUT_HSI2C2_PCLK>;
-				clock-names = "hsi2c", "hsi2c_pclk";
-				status = "disabled";
-			};
-		};
-
-		usi_spi_0: usi@139400c0 {
-			compatible = "samsung,exynos850-usi";
-			reg = <0x139400c0 0x20>;
-			samsung,sysreg = <&sysreg_peri 0x1050>;
-			samsung,mode = <USI_V2_SPI>;
-			#address-cells = <1>;
-			#size-cells = <1>;
-			ranges;
-			clocks = <&cmu_peri CLK_GOUT_SPI0_PCLK>,
-				 <&cmu_peri CLK_GOUT_SPI0_IPCLK>;
-			clock-names = "pclk", "ipclk";
-			status = "disabled";
-		};
-
-		usi_cmgp0: usi@11d000c0 {
-			compatible = "samsung,exynos850-usi";
-			reg = <0x11d000c0 0x20>;
-			samsung,sysreg = <&sysreg_cmgp 0x2000>;
-			samsung,mode = <USI_V2_I2C>;
-			#address-cells = <1>;
-			#size-cells = <1>;
-			ranges;
-			clocks = <&cmu_cmgp CLK_GOUT_CMGP_USI0_PCLK>,
-				 <&cmu_cmgp CLK_GOUT_CMGP_USI0_IPCLK>;
-			clock-names = "pclk", "ipclk";
-			status = "disabled";
-
-			hsi2c_3: i2c@11d00000 {
-				compatible = "samsung,exynosautov9-hsi2c";
-				reg = <0x11d00000 0xc0>;
-				interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
-				#address-cells = <1>;
-				#size-cells = <0>;
-				pinctrl-names = "default";
-				pinctrl-0 = <&hsi2c3_pins>;
-				clocks = <&cmu_cmgp CLK_GOUT_CMGP_USI0_IPCLK>,
-					 <&cmu_cmgp CLK_GOUT_CMGP_USI0_PCLK>;
-				clock-names = "hsi2c", "hsi2c_pclk";
-				status = "disabled";
-			};
-
-			serial_1: serial@11d00000 {
-				compatible = "samsung,exynos850-uart";
-				reg = <0x11d00000 0xc0>;
-				interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
-				pinctrl-names = "default";
-				pinctrl-0 = <&uart1_single_pins>;
-				clocks = <&cmu_cmgp CLK_GOUT_CMGP_USI0_PCLK>,
-					 <&cmu_cmgp CLK_GOUT_CMGP_USI0_IPCLK>;
-				clock-names = "uart", "clk_uart_baud0";
-				status = "disabled";
-			};
-		};
-
-		usi_cmgp1: usi@11d200c0 {
-			compatible = "samsung,exynos850-usi";
-			reg = <0x11d200c0 0x20>;
-			samsung,sysreg = <&sysreg_cmgp 0x2010>;
-			samsung,mode = <USI_V2_I2C>;
-			#address-cells = <1>;
-			#size-cells = <1>;
-			ranges;
-			clocks = <&cmu_cmgp CLK_GOUT_CMGP_USI1_PCLK>,
-				 <&cmu_cmgp CLK_GOUT_CMGP_USI1_IPCLK>;
-			clock-names = "pclk", "ipclk";
-			status = "disabled";
-
-			hsi2c_4: i2c@11d20000 {
-				compatible = "samsung,exynosautov9-hsi2c";
-				reg = <0x11d20000 0xc0>;
-				interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>;
-				#address-cells = <1>;
-				#size-cells = <0>;
-				pinctrl-names = "default";
-				pinctrl-0 = <&hsi2c4_pins>;
-				clocks = <&cmu_cmgp CLK_GOUT_CMGP_USI1_IPCLK>,
-					 <&cmu_cmgp CLK_GOUT_CMGP_USI1_PCLK>;
-				clock-names = "hsi2c", "hsi2c_pclk";
-				status = "disabled";
-			};
-
-			serial_2: serial@11d20000 {
-				compatible = "samsung,exynos850-uart";
-				reg = <0x11d20000 0xc0>;
-				interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>;
-				pinctrl-names = "default";
-				pinctrl-0 = <&uart2_single_pins>;
-				clocks = <&cmu_cmgp CLK_GOUT_CMGP_USI1_PCLK>,
-					 <&cmu_cmgp CLK_GOUT_CMGP_USI1_IPCLK>;
-				clock-names = "uart", "clk_uart_baud0";
-				status = "disabled";
-			};
-		};
-	};
-};
-
-#include "exynos850-pinctrl.dtsi"
diff --git a/arch/arm/dts/omap3-igep.dtsi b/arch/arm/dts/omap3-igep.dtsi
deleted file mode 100644
index 2192026..0000000
--- a/arch/arm/dts/omap3-igep.dtsi
+++ /dev/null
@@ -1,247 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0-only
-/*
- * Common device tree for IGEP boards based on AM/DM37x
- *
- * Copyright (C) 2012 Javier Martinez Canillas <javier@dowhile0.org>
- * Copyright (C) 2012 Enric Balletbo i Serra <eballetbo@gmail.com>
- */
-/dts-v1/;
-
-#include "omap36xx.dtsi"
-
-/ {
-	memory@80000000 {
-		device_type = "memory";
-		reg = <0x80000000 0x20000000>; /* 512 MB */
-	};
-
-	chosen {
-		stdout-path = &uart3;
-	};
-
-	sound {
-		compatible = "ti,omap-twl4030";
-		ti,model = "igep2";
-		ti,mcbsp = <&mcbsp2>;
-	};
-
-	vdd33: regulator-vdd33 {
-		compatible = "regulator-fixed";
-		regulator-name = "vdd33";
-		regulator-always-on;
-	};
-
-};
-
-&omap3_pmx_core {
-	gpmc_pins: pinmux_gpmc_pins {
-		pinctrl-single,pins = <
-			/* OneNAND seems to require PIN_INPUT on clock. */
-                        OMAP3_CORE1_IOPAD(0x20be, PIN_INPUT | MUX_MODE0)        /* gpmc_clk.gpmc_clk */
-		>;
-	};
-
-	uart1_pins: pinmux_uart1_pins {
-		pinctrl-single,pins = <
-			OMAP3_CORE1_IOPAD(0x2182, PIN_INPUT | MUX_MODE0)	/* uart1_rx.uart1_rx */
-			OMAP3_CORE1_IOPAD(0x217c, PIN_OUTPUT | MUX_MODE0)	/* uart1_tx.uart1_tx */
-		>;
-	};
-
-	uart3_pins: pinmux_uart3_pins {
-		pinctrl-single,pins = <
-			OMAP3_CORE1_IOPAD(0x219e, PIN_INPUT | MUX_MODE0)	/* uart3_rx.uart3_rx */
-			OMAP3_CORE1_IOPAD(0x21a0, PIN_OUTPUT | MUX_MODE0)	/* uart3_tx.uart3_tx */
-		>;
-	};
-
-	mcbsp2_pins: pinmux_mcbsp2_pins {
-		pinctrl-single,pins = <
-			OMAP3_CORE1_IOPAD(0x213c, PIN_INPUT | MUX_MODE0)	/* mcbsp2_fsx.mcbsp2_fsx */
-			OMAP3_CORE1_IOPAD(0x213e, PIN_INPUT | MUX_MODE0)	/* mcbsp2_clkx.mcbsp2_clkx */
-			OMAP3_CORE1_IOPAD(0x2140, PIN_INPUT | MUX_MODE0)	/* mcbsp2_dr.mcbsp2.dr */
-			OMAP3_CORE1_IOPAD(0x2142, PIN_OUTPUT | MUX_MODE0)	/* mcbsp2_dx.mcbsp2_dx */
-		>;
-	};
-
-	mmc1_pins: pinmux_mmc1_pins {
-		pinctrl-single,pins = <
-			OMAP3_CORE1_IOPAD(0x2144, PIN_INPUT_PULLUP | MUX_MODE0)	/* sdmmc1_clk.sdmmc1_clk */
-			OMAP3_CORE1_IOPAD(0x2146, PIN_INPUT_PULLUP | MUX_MODE0)	/* sdmmc1_cmd.sdmmc1_cmd */
-			OMAP3_CORE1_IOPAD(0x2148, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc1_dat0.sdmmc1_dat0 */
-			OMAP3_CORE1_IOPAD(0x214a, PIN_INPUT_PULLUP | MUX_MODE0)	/* sdmmc1_dat1.sdmmc1_dat1 */
-			OMAP3_CORE1_IOPAD(0x214c, PIN_INPUT_PULLUP | MUX_MODE0)	/* sdmmc1_dat2.sdmmc1_dat2 */
-			OMAP3_CORE1_IOPAD(0x214e, PIN_INPUT_PULLUP | MUX_MODE0)	/* sdmmc1_dat3.sdmmc1_dat3 */
-		>;
-	};
-
-	mmc2_pins: pinmux_mmc2_pins {
-		pinctrl-single,pins = <
-			OMAP3_CORE1_IOPAD(0x2158, PIN_INPUT_PULLUP | MUX_MODE0)	/* sdmmc2_clk.sdmmc2_clk */
-			OMAP3_CORE1_IOPAD(0x215a, PIN_INPUT_PULLUP | MUX_MODE0)	/* sdmmc2_cmd.sdmmc2_cmd */
-			OMAP3_CORE1_IOPAD(0x215c, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc2_dat0.sdmmc2_dat0 */
-			OMAP3_CORE1_IOPAD(0x215e, PIN_INPUT_PULLUP | MUX_MODE0)	/* sdmmc2_dat1.sdmmc2_dat1 */
-			OMAP3_CORE1_IOPAD(0x2160, PIN_INPUT_PULLUP | MUX_MODE0)	/* sdmmc2_dat2.sdmmc2_dat2 */
-			OMAP3_CORE1_IOPAD(0x2162, PIN_INPUT_PULLUP | MUX_MODE0)	/* sdmmc2_dat3.sdmmc2_dat3 */
-		>;
-	};
-
-	i2c1_pins: pinmux_i2c1_pins {
-		pinctrl-single,pins = <
-			OMAP3_CORE1_IOPAD(0x21ba, PIN_INPUT | MUX_MODE0)	/* i2c1_scl.i2c1_scl */
-			OMAP3_CORE1_IOPAD(0x21bc, PIN_INPUT | MUX_MODE0)	/* i2c1_sda.i2c1_sda */
-		>;
-	};
-
-	i2c3_pins: pinmux_i2c3_pins {
-		pinctrl-single,pins = <
-			OMAP3_CORE1_IOPAD(0x21c2, PIN_INPUT | MUX_MODE0)	/* i2c3_scl.i2c3_scl */
-			OMAP3_CORE1_IOPAD(0x21c4, PIN_INPUT | MUX_MODE0)	/* i2c3_sda.i2c3_sda */
-		>;
-	};
-};
-
-&gpmc {
-	pinctrl-names = "default";
-	pinctrl-0 = <&gpmc_pins>;
-
-	nand@0,0 {
-		compatible = "ti,omap2-nand";
-		reg = <0 0 4>; /* CS0, offset 0, IO size 4 */
-		interrupt-parent = <&gpmc>;
-		interrupts = <0 IRQ_TYPE_NONE>, /* fifoevent */
-			     <1 IRQ_TYPE_NONE>;	/* termcount */
-		linux,mtd-name = "micron,mt29c4g96maz";
-		nand-bus-width = <16>;
-		gpmc,device-width = <2>;
-		ti,nand-ecc-opt = "bch8";
-
-		gpmc,sync-clk-ps = <0>;
-		gpmc,cs-on-ns = <0>;
-		gpmc,cs-rd-off-ns = <44>;
-		gpmc,cs-wr-off-ns = <44>;
-		gpmc,adv-on-ns = <6>;
-		gpmc,adv-rd-off-ns = <34>;
-		gpmc,adv-wr-off-ns = <44>;
-		gpmc,we-off-ns = <40>;
-		gpmc,oe-off-ns = <54>;
-		gpmc,access-ns = <64>;
-		gpmc,rd-cycle-ns = <82>;
-		gpmc,wr-cycle-ns = <82>;
-		gpmc,wr-access-ns = <40>;
-		gpmc,wr-data-mux-bus-ns = <0>;
-
-		#address-cells = <1>;
-		#size-cells = <1>;
-
-		status = "okay";
-	};
-
-	onenand@0,0 {
-		compatible = "ti,omap2-onenand";
-		reg = <0 0 0x20000>;	/* CS0, offset 0, IO size 128K */
-
-		gpmc,sync-read;
-		gpmc,sync-write;
-		gpmc,burst-length = <16>;
-		gpmc,burst-wrap;
-		gpmc,burst-read;
-		gpmc,burst-write;
-		gpmc,device-width = <2>; /* GPMC_DEVWIDTH_16BIT */
-		gpmc,mux-add-data = <2>; /* GPMC_MUX_AD */
-		gpmc,cs-on-ns = <0>;
-		gpmc,cs-rd-off-ns = <96>;
-		gpmc,cs-wr-off-ns = <96>;
-		gpmc,adv-on-ns = <0>;
-		gpmc,adv-rd-off-ns = <12>;
-		gpmc,adv-wr-off-ns = <12>;
-		gpmc,oe-on-ns = <18>;
-		gpmc,oe-off-ns = <96>;
-		gpmc,we-on-ns = <0>;
-		gpmc,we-off-ns = <96>;
-		gpmc,rd-cycle-ns = <114>;
-		gpmc,wr-cycle-ns = <114>;
-		gpmc,access-ns = <90>;
-		gpmc,page-burst-access-ns = <12>;
-		gpmc,bus-turnaround-ns = <0>;
-		gpmc,cycle2cycle-delay-ns = <0>;
-		gpmc,wait-monitoring-ns = <0>;
-		gpmc,clk-activation-ns = <6>;
-		gpmc,wr-data-mux-bus-ns = <30>;
-		gpmc,wr-access-ns = <90>;
-		gpmc,sync-clk-ps = <12000>;
-
-		#address-cells = <1>;
-		#size-cells = <1>;
-
-		status = "disabled";
-	};
-};
-
-&i2c1 {
-	pinctrl-names = "default";
-	pinctrl-0 = <&i2c1_pins>;
-	clock-frequency = <2600000>;
-
-	twl: twl@48 {
-		reg = <0x48>;
-		interrupts = <7>; /* SYS_NIRQ cascaded to intc */
-		interrupt-parent = <&intc>;
-
-		twl_audio: audio {
-			compatible = "ti,twl4030-audio";
-			codec {
-			};
-		};
-	};
-};
-
-#include "twl4030.dtsi"
-#include "twl4030_omap3.dtsi"
-
-&i2c3 {
-	pinctrl-names = "default";
-	pinctrl-0 = <&i2c3_pins>;
-};
-
-&mcbsp2 {
-	pinctrl-names = "default";
-	pinctrl-0 = <&mcbsp2_pins>;
-	status = "okay";
-};
-
-&mmc1 {
-	pinctrl-names = "default";
-	pinctrl-0 = <&mmc1_pins>;
-	vmmc-supply = <&vmmc1>;
-	vmmc_aux-supply = <&vsim>;
-	bus-width = <4>;
-	cd-gpios = <&twl_gpio 0 GPIO_ACTIVE_LOW>;
-};
-
-&mmc3 {
-	status = "disabled";
-};
-
-&uart1 {
-	pinctrl-names = "default";
-	pinctrl-0 = <&uart1_pins>;
-};
-
-&uart3 {
-	pinctrl-names = "default";
-	pinctrl-0 = <&uart3_pins>;
-};
-
-&twl_gpio {
-	ti,use-leds;
-};
-
-&usb_otg_hs {
-	interface-type = <0>;
-	usb-phy = <&usb2_phy>;
-	phys = <&usb2_phy>;
-	phy-names = "usb2-phy";
-	mode = <3>;
-	power = <50>;
-};
diff --git a/arch/arm/dts/omap3-igep0020-common.dtsi b/arch/arm/dts/omap3-igep0020-common.dtsi
deleted file mode 100644
index 73d8f47..0000000
--- a/arch/arm/dts/omap3-igep0020-common.dtsi
+++ /dev/null
@@ -1,261 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0-only
-/*
- * Common Device Tree Source for IGEPv2
- *
- * Copyright (C) 2014 Javier Martinez Canillas <javier@dowhile0.org>
- * Copyright (C) 2014 Enric Balletbo i Serra <eballetbo@gmail.com>
- */
-
-#include "omap3-igep.dtsi"
-#include "omap-gpmc-smsc9221.dtsi"
-
-/ {
-
-	leds {
-		pinctrl-names = "default";
-		pinctrl-0 = <&leds_pins>;
-		compatible = "gpio-leds";
-
-		boot {
-			 label = "omap3:green:boot";
-			 gpios = <&gpio1 26 GPIO_ACTIVE_HIGH>;
-			 default-state = "on";
-		};
-
-		user0 {
-			 label = "omap3:red:user0";
-			 gpios = <&gpio1 27 GPIO_ACTIVE_HIGH>;
-			 default-state = "off";
-		};
-
-		user1 {
-			 label = "omap3:red:user1";
-			 gpios = <&gpio1 28 GPIO_ACTIVE_HIGH>;
-			 default-state = "off";
-		};
-
-		user2 {
-			label = "omap3:green:user1";
-			gpios = <&twl_gpio 19 GPIO_ACTIVE_LOW>;
-		};
-	};
-
-	/* HS USB Port 1 Power */
-	hsusb1_power: hsusb1_power_reg {
-		compatible = "regulator-fixed";
-		regulator-name = "hsusb1_vbus";
-		regulator-min-microvolt = <3300000>;
-		regulator-max-microvolt = <3300000>;
-		gpio = <&twl_gpio 18 GPIO_ACTIVE_LOW>;	/* GPIO LEDA */
-		startup-delay-us = <70000>;
-	};
-
-	/* HS USB Host PHY on PORT 1 */
-	hsusb1_phy: hsusb1_phy {
-		compatible = "usb-nop-xceiv";
-		reset-gpios = <&gpio1 24 GPIO_ACTIVE_LOW>; /* gpio_24 */
-		vcc-supply = <&hsusb1_power>;
-		#phy-cells = <0>;
-	};
-
-	tfp410: encoder {
-		compatible = "ti,tfp410";
-		powerdown-gpios = <&gpio6 10 GPIO_ACTIVE_LOW>; /* gpio_170 */
-
-		ports {
-			#address-cells = <1>;
-			#size-cells = <0>;
-
-			port@0 {
-				reg = <0>;
-
-				tfp410_in: endpoint {
-					remote-endpoint = <&dpi_out>;
-				};
-			};
-
-			port@1 {
-				reg = <1>;
-
-				tfp410_out: endpoint {
-					remote-endpoint = <&dvi_connector_in>;
-				};
-			};
-		};
-	};
-
-	dvi0: connector {
-		compatible = "dvi-connector";
-		label = "dvi";
-
-		digital;
-
-		ddc-i2c-bus = <&i2c3>;
-
-		port {
-			dvi_connector_in: endpoint {
-				remote-endpoint = <&tfp410_out>;
-			};
-		};
-	};
-};
-
-&omap3_pmx_core {
-	pinctrl-names = "default";
-	pinctrl-0 = <
-		&tfp410_pins
-		&dss_dpi_pins
-	>;
-
-	tfp410_pins: pinmux_tfp410_pins {
-		pinctrl-single,pins = <
-			OMAP3_CORE1_IOPAD(0x21c6, PIN_OUTPUT | MUX_MODE4)   /* hdq_sio.gpio_170 */
-		>;
-	};
-
-	dss_dpi_pins: pinmux_dss_dpi_pins {
-		pinctrl-single,pins = <
-			OMAP3_CORE1_IOPAD(0x20d4, PIN_OUTPUT | MUX_MODE0)   /* dss_pclk.dss_pclk */
-			OMAP3_CORE1_IOPAD(0x20d6, PIN_OUTPUT | MUX_MODE0)   /* dss_hsync.dss_hsync */
-			OMAP3_CORE1_IOPAD(0x20d8, PIN_OUTPUT | MUX_MODE0)   /* dss_vsync.dss_vsync */
-			OMAP3_CORE1_IOPAD(0x20da, PIN_OUTPUT | MUX_MODE0)   /* dss_acbias.dss_acbias */
-			OMAP3_CORE1_IOPAD(0x20dc, PIN_OUTPUT | MUX_MODE0)   /* dss_data0.dss_data0 */
-			OMAP3_CORE1_IOPAD(0x20de, PIN_OUTPUT | MUX_MODE0)   /* dss_data1.dss_data1 */
-			OMAP3_CORE1_IOPAD(0x20e0, PIN_OUTPUT | MUX_MODE0)   /* dss_data2.dss_data2 */
-			OMAP3_CORE1_IOPAD(0x20e2, PIN_OUTPUT | MUX_MODE0)   /* dss_data3.dss_data3 */
-			OMAP3_CORE1_IOPAD(0x20e4, PIN_OUTPUT | MUX_MODE0)   /* dss_data4.dss_data4 */
-			OMAP3_CORE1_IOPAD(0x20e6, PIN_OUTPUT | MUX_MODE0)   /* dss_data5.dss_data5 */
-			OMAP3_CORE1_IOPAD(0x20e8, PIN_OUTPUT | MUX_MODE0)   /* dss_data6.dss_data6 */
-			OMAP3_CORE1_IOPAD(0x20ea, PIN_OUTPUT | MUX_MODE0)   /* dss_data7.dss_data7 */
-			OMAP3_CORE1_IOPAD(0x20ec, PIN_OUTPUT | MUX_MODE0)   /* dss_data8.dss_data8 */
-			OMAP3_CORE1_IOPAD(0x20ee, PIN_OUTPUT | MUX_MODE0)   /* dss_data9.dss_data9 */
-			OMAP3_CORE1_IOPAD(0x20f0, PIN_OUTPUT | MUX_MODE0)   /* dss_data10.dss_data10 */
-			OMAP3_CORE1_IOPAD(0x20f2, PIN_OUTPUT | MUX_MODE0)   /* dss_data11.dss_data11 */
-			OMAP3_CORE1_IOPAD(0x20f4, PIN_OUTPUT | MUX_MODE0)   /* dss_data12.dss_data12 */
-			OMAP3_CORE1_IOPAD(0x20f6, PIN_OUTPUT | MUX_MODE0)   /* dss_data13.dss_data13 */
-			OMAP3_CORE1_IOPAD(0x20f8, PIN_OUTPUT | MUX_MODE0)   /* dss_data14.dss_data14 */
-			OMAP3_CORE1_IOPAD(0x20fa, PIN_OUTPUT | MUX_MODE0)   /* dss_data15.dss_data15 */
-			OMAP3_CORE1_IOPAD(0x20fc, PIN_OUTPUT | MUX_MODE0)   /* dss_data16.dss_data16 */
-			OMAP3_CORE1_IOPAD(0x20fe, PIN_OUTPUT | MUX_MODE0)   /* dss_data17.dss_data17 */
-			OMAP3_CORE1_IOPAD(0x2100, PIN_OUTPUT | MUX_MODE0)   /* dss_data18.dss_data18 */
-			OMAP3_CORE1_IOPAD(0x2102, PIN_OUTPUT | MUX_MODE0)   /* dss_data19.dss_data19 */
-			OMAP3_CORE1_IOPAD(0x2104, PIN_OUTPUT | MUX_MODE0)   /* dss_data20.dss_data20 */
-			OMAP3_CORE1_IOPAD(0x2106, PIN_OUTPUT | MUX_MODE0)   /* dss_data21.dss_data21 */
-			OMAP3_CORE1_IOPAD(0x2108, PIN_OUTPUT | MUX_MODE0)   /* dss_data22.dss_data22 */
-			OMAP3_CORE1_IOPAD(0x210a, PIN_OUTPUT | MUX_MODE0)   /* dss_data23.dss_data23 */
-		>;
-	};
-
-	uart2_pins: pinmux_uart2_pins {
-		pinctrl-single,pins = <
-			OMAP3_CORE1_IOPAD(0x2174, PIN_INPUT | MUX_MODE0)	/* uart2_cts.uart2_cts */
-			OMAP3_CORE1_IOPAD(0x2176, PIN_OUTPUT | MUX_MODE0)	/* uart2_rts .uart2_rts*/
-			OMAP3_CORE1_IOPAD(0x2178, PIN_OUTPUT | MUX_MODE0)	/* uart2_tx.uart2_tx */
-			OMAP3_CORE1_IOPAD(0x217a, PIN_INPUT | MUX_MODE0)	/* uart2_rx.uart2_rx */
-		>;
-	};
-
-	smsc9221_pins: pinmux_smsc9221_pins {
-		pinctrl-single,pins = <
-			OMAP3_CORE1_IOPAD(0x21d2, PIN_INPUT | MUX_MODE4)	/* mcspi1_cs2.gpio_176 */
-		>;
-	};
-};
-
-&omap3_pmx_core2 {
-	pinctrl-names = "default";
-	pinctrl-0 = <
-		&hsusbb1_pins
-	>;
-
-	hsusbb1_pins: pinmux_hsusbb1_pins {
-		pinctrl-single,pins = <
-			OMAP3630_CORE2_IOPAD(0x25da, PIN_OUTPUT | MUX_MODE3)		/* etk_ctl.hsusb1_clk */
-			OMAP3630_CORE2_IOPAD(0x25d8, PIN_OUTPUT | MUX_MODE3)		/* etk_clk.hsusb1_stp */
-			OMAP3630_CORE2_IOPAD(0x25ec, PIN_INPUT_PULLDOWN | MUX_MODE3)	/* etk_d8.hsusb1_dir */
-			OMAP3630_CORE2_IOPAD(0x25ee, PIN_INPUT_PULLDOWN | MUX_MODE3)	/* etk_d9.hsusb1_nxt */
-			OMAP3630_CORE2_IOPAD(0x25dc, PIN_INPUT_PULLDOWN | MUX_MODE3)	/* etk_d0.hsusb1_data0 */
-			OMAP3630_CORE2_IOPAD(0x25de, PIN_INPUT_PULLDOWN | MUX_MODE3)	/* etk_d1.hsusb1_data1 */
-			OMAP3630_CORE2_IOPAD(0x25e0, PIN_INPUT_PULLDOWN | MUX_MODE3)	/* etk_d2.hsusb1_data2 */
-			OMAP3630_CORE2_IOPAD(0x25e2, PIN_INPUT_PULLDOWN | MUX_MODE3)	/* etk_d3.hsusb1_data7 */
-			OMAP3630_CORE2_IOPAD(0x25e4, PIN_INPUT_PULLDOWN | MUX_MODE3)	/* etk_d4.hsusb1_data4 */
-			OMAP3630_CORE2_IOPAD(0x25e6, PIN_INPUT_PULLDOWN | MUX_MODE3)	/* etk_d5.hsusb1_data5 */
-			OMAP3630_CORE2_IOPAD(0x25e8, PIN_INPUT_PULLDOWN | MUX_MODE3)	/* etk_d6.hsusb1_data6 */
-			OMAP3630_CORE2_IOPAD(0x25ea, PIN_INPUT_PULLDOWN | MUX_MODE3)	/* etk_d7.hsusb1_data3 */
-		>;
-	};
-
-	leds_pins: pinmux_leds_pins {
-		pinctrl-single,pins = <
-			OMAP3630_CORE2_IOPAD(0x25f4, PIN_OUTPUT | MUX_MODE4) /* etk_d12.gpio_26 */
-			OMAP3630_CORE2_IOPAD(0x25f6, PIN_OUTPUT | MUX_MODE4) /* etk_d13.gpio_27 */
-			OMAP3630_CORE2_IOPAD(0x25f8, PIN_OUTPUT | MUX_MODE4) /* etk_d14.gpio_28 */
-		>;
-	};
-
-	mmc1_wp_pins: pinmux_mmc1_cd_pins {
-		pinctrl-single,pins = <
-			OMAP3630_CORE2_IOPAD(0x25fa, PIN_INPUT | MUX_MODE4)   /* etk_d15.gpio_29 */
-		>;
-	};
-};
-
-&i2c3 {
-	clock-frequency = <100000>;
-
-	/*
-	 * Display monitor features are burnt in the EEPROM
-	 * as EDID data.
-	 */
-	eeprom@50 {
-		compatible = "ti,eeprom";
-		reg = <0x50>;
-	};
-};
-
-&gpmc {
-	ranges = <0 0 0x30000000 0x01000000>,	/* CS0: 16MB for NAND */
-		 <5 0 0x2c000000 0x01000000>;	/* CS5: 16MB for ethernet */
-
-	ethernet@gpmc {
-		pinctrl-names = "default";
-		pinctrl-0 = <&smsc9221_pins>;
-		reg = <5 0 0xff>;
-		interrupt-parent = <&gpio6>;
-		interrupts = <16 IRQ_TYPE_LEVEL_LOW>;
-	};
-};
-
-&uart2 {
-	pinctrl-names = "default";
-	pinctrl-0 = <&uart2_pins>;
-};
-
-&usbhshost {
-	port1-mode = "ehci-phy";
-};
-
-&usbhsehci {
-	phys = <&hsusb1_phy>;
-};
-
-&vpll2 {
-	/* Needed for DSS */
-	regulator-name = "vdds_dsi";
-};
-
-&dss {
-	status = "okay";
-
-	port {
-		dpi_out: endpoint {
-			remote-endpoint = <&tfp410_in>;
-			data-lines = <24>;
-		};
-	};
-};
-
-&mmc1 {
-	pinctrl-0 = <&mmc1_pins &mmc1_wp_pins>;
-	wp-gpios = <&gpio1 29 GPIO_ACTIVE_LOW>;	/* gpio_29 */
-};
diff --git a/arch/arm/dts/omap3-igep0020-u-boot.dtsi b/arch/arm/dts/omap3-igep0020-u-boot.dtsi
index 41beaf0..2c03701 100644
--- a/arch/arm/dts/omap3-igep0020-u-boot.dtsi
+++ b/arch/arm/dts/omap3-igep0020-u-boot.dtsi
@@ -5,20 +5,10 @@
  * (C) Copyright 2017 Derald D. Woods <woods.technical@gmail.com>
  */
 
+#include "omap3-u-boot.dtsi"
+
 / {
 	chosen {
 		stdout-path = &uart3;
 	};
 };
-
-&uart1 {
-	reg-shift = <2>;
-};
-
-&uart2 {
-	reg-shift = <2>;
-};
-
-&uart3 {
-	reg-shift = <2>;
-};
diff --git a/arch/arm/dts/omap3-igep0020.dts b/arch/arm/dts/omap3-igep0020.dts
deleted file mode 100644
index cf3ac84..0000000
--- a/arch/arm/dts/omap3-igep0020.dts
+++ /dev/null
@@ -1,47 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0-only
-/*
- * Device Tree Source for IGEPv2 Rev. C (TI OMAP AM/DM37x)
- *
- * Copyright (C) 2012 Javier Martinez Canillas <javier@dowhile0.org>
- * Copyright (C) 2012 Enric Balletbo i Serra <eballetbo@gmail.com>
- */
-
-#include "omap3-igep0020-common.dtsi"
-
-/ {
-	model = "IGEPv2 Rev. C (TI OMAP AM/DM37x)";
-	compatible = "isee,omap3-igep0020", "ti,omap36xx", "ti,omap3";
-
-	vmmcsdio_fixed: fixedregulator-mmcsdio {
-		compatible = "regulator-fixed";
-		regulator-name = "vmmcsdio_fixed";
-		regulator-min-microvolt = <3300000>;
-		regulator-max-microvolt = <3300000>;
-	};
-
-	mmc2_pwrseq: mmc2_pwrseq {
-		compatible = "mmc-pwrseq-simple";
-		reset-gpios = <&gpio5 11 GPIO_ACTIVE_LOW>,	/* gpio_139 - RESET_N_W */
-			      <&gpio5 10 GPIO_ACTIVE_LOW>;	/* gpio_138 - WIFI_PDN */
-	};
-};
-
-&omap3_pmx_core {
-	lbee1usjyc_pins: pinmux_lbee1usjyc_pins {
-		pinctrl-single,pins = <
-			OMAP3_CORE1_IOPAD(0x2166, PIN_OUTPUT | MUX_MODE4)	/* sdmmc2_dat5.gpio_137 - RESET_N_W */
-			OMAP3_CORE1_IOPAD(0x2168, PIN_OUTPUT | MUX_MODE4)	/* sdmmc2_dat6.gpio_138 - WIFI_PDN */
-			OMAP3_CORE1_IOPAD(0x216a, PIN_OUTPUT | MUX_MODE4)	/* sdmmc2_dat7.gpio_139 - RST_N_B */
-		>;
-	};
-};
-
-/* On board Wifi module */
-&mmc2 {
-	pinctrl-names = "default";
-	pinctrl-0 = <&mmc2_pins &lbee1usjyc_pins>;
-	vmmc-supply = <&vmmcsdio_fixed>;
-	mmc-pwrseq = <&mmc2_pwrseq>;
-	bus-width = <4>;
-	non-removable;
-};
diff --git a/arch/arm/dts/rk3566-powkiddy-x55-u-boot.dtsi b/arch/arm/dts/rk3566-powkiddy-x55-u-boot.dtsi
new file mode 100644
index 0000000..eadd351
--- /dev/null
+++ b/arch/arm/dts/rk3566-powkiddy-x55-u-boot.dtsi
@@ -0,0 +1,9 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+
+#include "rk356x-u-boot.dtsi"
+
+/ {
+	chosen {
+		u-boot,spl-boot-order = &sdmmc0, &sdhci;
+	};
+};
diff --git a/arch/arm/dts/rv1126-edgeble-neu2-io.dts b/arch/arm/dts/rv1126-edgeble-neu2-io.dts
deleted file mode 100644
index 0c2396b..0000000
--- a/arch/arm/dts/rv1126-edgeble-neu2-io.dts
+++ /dev/null
@@ -1,112 +0,0 @@
-// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
-/*
- * Copyright (c) 2020 Rockchip Electronics Co., Ltd.
- * Copyright (c) 2022 Edgeble AI Technologies Pvt. Ltd.
- */
-
-/dts-v1/;
-#include "rv1126.dtsi"
-#include "rv1126-edgeble-neu2.dtsi"
-
-/ {
-	model = "Edgeble Neu2 IO Board";
-	compatible = "edgeble,neural-compute-module-2-io",
-		     "edgeble,neural-compute-module-2", "rockchip,rv1126";
-
-	aliases {
-		serial2 = &uart2;
-	};
-
-	chosen {
-		stdout-path = "serial2:1500000n8";
-	};
-
-	vcc12v_dcin: vcc12v-dcin-regulator {
-		compatible = "regulator-fixed";
-		regulator-name = "vcc12v_dcin";
-		regulator-always-on;
-		regulator-boot-on;
-		regulator-min-microvolt = <12000000>;
-		regulator-max-microvolt = <12000000>;
-	};
-
-	vcc5v0_sys: vcc5v0-sys-regulator {
-		compatible = "regulator-fixed";
-		regulator-name = "vcc5v0_sys";
-		regulator-always-on;
-		regulator-boot-on;
-		regulator-min-microvolt = <5000000>;
-		regulator-max-microvolt = <5000000>;
-		vin-supply = <&vcc12v_dcin>;
-	};
-
-	v3v3_sys: v3v3-sys-regulator {
-		compatible = "regulator-fixed";
-		regulator-name = "v3v3_sys";
-		regulator-always-on;
-		regulator-boot-on;
-		regulator-min-microvolt = <3300000>;
-		regulator-max-microvolt = <3300000>;
-		vin-supply = <&vcc5v0_sys>;
-	};
-};
-
-&gmac {
-	assigned-clocks = <&cru CLK_GMAC_SRC>, <&cru CLK_GMAC_TX_RX>,
-			  <&cru CLK_GMAC_ETHERNET_OUT>;
-	assigned-clock-parents = <&cru CLK_GMAC_SRC_M1>, <&cru RGMII_MODE_CLK>;
-	assigned-clock-rates = <125000000>, <0>, <25000000>;
-	clock_in_out = "input";
-	phy-handle = <&phy>;
-	phy-mode = "rgmii";
-	phy-supply = <&vcc_3v3>;
-	pinctrl-names = "default";
-	pinctrl-0 = <&rgmiim1_miim &rgmiim1_bus2 &rgmiim1_bus4 &clk_out_ethernetm1_pins>;
-	tx_delay = <0x2a>;
-	rx_delay = <0x1a>;
-	status = "okay";
-};
-
-&mdio {
-	phy: ethernet-phy@0 {
-		compatible = "ethernet-phy-id001c.c916",
-			     "ethernet-phy-ieee802.3-c22";
-		reg = <0x0>;
-		pinctrl-names = "default";
-		pinctrl-0 = <&eth_phy_rst>;
-		reset-assert-us = <20000>;
-		reset-deassert-us = <100000>;
-		reset-gpios = <&gpio0 RK_PB6 GPIO_ACTIVE_LOW>;
-	};
-};
-
-&pinctrl {
-	ethernet {
-		eth_phy_rst: eth-phy-rst {
-			rockchip,pins = <0 RK_PB6 RK_FUNC_GPIO &pcfg_pull_down>;
-		};
-	};
-};
-
-&pwm11 {
-	status = "okay";
-};
-
-&sdmmc {
-	bus-width = <4>;
-	cap-mmc-highspeed;
-	cap-sd-highspeed;
-	card-detect-delay = <200>;
-	pinctrl-names = "default";
-	pinctrl-0 = <&sdmmc0_clk &sdmmc0_cmd &sdmmc0_bus4 &sdmmc0_det>;
-	rockchip,default-sample-phase = <90>;
-	sd-uhs-sdr12;
-	sd-uhs-sdr25;
-	sd-uhs-sdr104;
-	vqmmc-supply = <&vccio_sd>;
-	status = "okay";
-};
-
-&uart2 {
-	status = "okay";
-};
diff --git a/arch/arm/dts/rv1126-edgeble-neu2.dtsi b/arch/arm/dts/rv1126-edgeble-neu2.dtsi
deleted file mode 100644
index 7ea8d7d..0000000
--- a/arch/arm/dts/rv1126-edgeble-neu2.dtsi
+++ /dev/null
@@ -1,345 +0,0 @@
-// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
-/*
- * Copyright (c) 2020 Rockchip Electronics Co., Ltd.
- * Copyright (c) 2022 Edgeble AI Technologies Pvt. Ltd.
- */
-
-/ {
-	compatible = "edgeble,neural-compute-module-2", "rockchip,rv1126";
-
-	aliases {
-		mmc0 = &emmc;
-	};
-
-	vccio_flash: vccio-flash-regulator {
-		compatible = "regulator-fixed";
-		enable-active-high;
-		gpio = <&gpio0 RK_PB3 GPIO_ACTIVE_HIGH>;
-		pinctrl-names = "default";
-		pinctrl-0 = <&flash_vol_sel>;
-		regulator-name = "vccio_flash";
-		regulator-always-on;
-		regulator-boot-on;
-		regulator-min-microvolt = <1800000>;
-		regulator-max-microvolt = <1800000>;
-		vin-supply = <&vcc_3v3>;
-	};
-
-	sdio_pwrseq: pwrseq-sdio {
-		compatible = "mmc-pwrseq-simple";
-		clocks = <&rk809 1>;
-		clock-names = "ext_clock";
-		pinctrl-names = "default";
-		pinctrl-0 = <&wifi_enable_h>;
-		reset-gpios = <&gpio1 RK_PD0 GPIO_ACTIVE_LOW>;
-	};
-};
-
-&cpu0 {
-	cpu-supply = <&vdd_arm>;
-};
-
-&emmc {
-	bus-width = <8>;
-	non-removable;
-	pinctrl-names = "default";
-	pinctrl-0 = <&emmc_bus8 &emmc_cmd &emmc_clk>;
-	rockchip,default-sample-phase = <90>;
-	vmmc-supply = <&vcc_3v3>;
-	vqmmc-supply = <&vccio_flash>;
-	status = "okay";
-};
-
-&i2c0 {
-	clock-frequency = <400000>;
-	status = "okay";
-
-	rk809: pmic@20 {
-		compatible = "rockchip,rk809";
-		reg = <0x20>;
-		interrupt-parent = <&gpio0>;
-		interrupts = <RK_PB1 IRQ_TYPE_LEVEL_LOW>;
-		#clock-cells = <1>;
-		clock-output-names = "rk808-clkout1", "rk808-clkout2";
-		pinctrl-names = "default";
-		pinctrl-0 = <&pmic_int_l>;
-		rockchip,system-power-controller;
-		wakeup-source;
-
-		vcc1-supply = <&vcc5v0_sys>;
-		vcc2-supply = <&vcc5v0_sys>;
-		vcc3-supply = <&vcc5v0_sys>;
-		vcc4-supply = <&vcc5v0_sys>;
-		vcc5-supply = <&vcc_buck5>;
-		vcc6-supply = <&vcc_buck5>;
-		vcc7-supply = <&vcc5v0_sys>;
-		vcc8-supply = <&vcc3v3_sys>;
-		vcc9-supply = <&vcc5v0_sys>;
-
-		regulators {
-			vdd_npu_vepu: DCDC_REG1 {
-				regulator-name = "vdd_npu_vepu";
-				regulator-always-on;
-				regulator-boot-on;
-				regulator-initial-mode = <0x2>;
-				regulator-min-microvolt = <650000>;
-				regulator-max-microvolt = <950000>;
-				regulator-ramp-delay = <6001>;
-				regulator-state-mem {
-					regulator-off-in-suspend;
-				};
-			};
-
-			vdd_arm: DCDC_REG2 {
-				regulator-name = "vdd_arm";
-				regulator-always-on;
-				regulator-boot-on;
-				regulator-initial-mode = <0x2>;
-				regulator-min-microvolt = <725000>;
-				regulator-max-microvolt = <1350000>;
-				regulator-ramp-delay = <6001>;
-				regulator-state-mem {
-					regulator-off-in-suspend;
-				};
-			};
-
-			vcc_ddr: DCDC_REG3 {
-				regulator-name = "vcc_ddr";
-				regulator-always-on;
-				regulator-boot-on;
-				regulator-initial-mode = <0x2>;
-				regulator-state-mem {
-					regulator-on-in-suspend;
-				};
-			};
-
-			vcc3v3_sys: DCDC_REG4 {
-				regulator-name = "vcc3v3_sys";
-				regulator-always-on;
-				regulator-boot-on;
-				regulator-initial-mode = <0x2>;
-				regulator-min-microvolt = <3300000>;
-				regulator-max-microvolt = <3300000>;
-				regulator-state-mem {
-					regulator-on-in-suspend;
-					regulator-suspend-microvolt = <3300000>;
-				};
-			};
-
-			vcc_buck5: DCDC_REG5 {
-				regulator-name = "vcc_buck5";
-				regulator-always-on;
-				regulator-boot-on;
-				regulator-min-microvolt = <2200000>;
-				regulator-max-microvolt = <2200000>;
-				regulator-state-mem {
-					regulator-on-in-suspend;
-					regulator-suspend-microvolt = <2200000>;
-				};
-			};
-
-			vcc_0v8: LDO_REG1 {
-				regulator-name = "vcc_0v8";
-				regulator-always-on;
-				regulator-boot-on;
-				regulator-min-microvolt = <800000>;
-				regulator-max-microvolt = <800000>;
-				regulator-state-mem {
-					regulator-off-in-suspend;
-				};
-			};
-
-			vcc1v8_pmu: LDO_REG2 {
-				regulator-name = "vcc1v8_pmu";
-				regulator-always-on;
-				regulator-boot-on;
-				regulator-min-microvolt = <1800000>;
-				regulator-max-microvolt = <1800000>;
-				regulator-state-mem {
-					regulator-on-in-suspend;
-					regulator-suspend-microvolt = <1800000>;
-				};
-			};
-
-			vdd0v8_pmu: LDO_REG3 {
-				regulator-name = "vcc0v8_pmu";
-				regulator-always-on;
-				regulator-boot-on;
-				regulator-min-microvolt = <800000>;
-				regulator-max-microvolt = <800000>;
-				regulator-state-mem {
-					regulator-on-in-suspend;
-					regulator-suspend-microvolt = <800000>;
-				};
-			};
-
-			vcc_1v8: LDO_REG4 {
-				regulator-name = "vcc_1v8";
-				regulator-always-on;
-				regulator-boot-on;
-				regulator-min-microvolt = <1800000>;
-				regulator-max-microvolt = <1800000>;
-				regulator-state-mem {
-					regulator-on-in-suspend;
-					regulator-suspend-microvolt = <1800000>;
-				};
-			};
-
-			vcc_dovdd: LDO_REG5 {
-				regulator-name = "vcc_dovdd";
-				regulator-boot-on;
-				regulator-min-microvolt = <1800000>;
-				regulator-max-microvolt = <1800000>;
-				regulator-state-mem {
-					regulator-off-in-suspend;
-				};
-			};
-
-			vcc_dvdd: LDO_REG6 {
-				regulator-name = "vcc_dvdd";
-				regulator-min-microvolt = <1200000>;
-				regulator-max-microvolt = <1200000>;
-				regulator-state-mem {
-					regulator-off-in-suspend;
-				};
-			};
-
-			vcc_avdd: LDO_REG7 {
-				regulator-name = "vcc_avdd";
-				regulator-min-microvolt = <2800000>;
-				regulator-max-microvolt = <2800000>;
-				regulator-state-mem {
-					regulator-off-in-suspend;
-				};
-			};
-
-			vccio_sd: LDO_REG8 {
-				regulator-name = "vccio_sd";
-				regulator-always-on;
-				regulator-boot-on;
-				regulator-min-microvolt = <1800000>;
-				regulator-max-microvolt = <3300000>;
-				regulator-state-mem {
-					regulator-off-in-suspend;
-				};
-			};
-
-			vcc3v3_sd: LDO_REG9 {
-				regulator-name = "vcc3v3_sd";
-				regulator-always-on;
-				regulator-boot-on;
-				regulator-min-microvolt = <3300000>;
-				regulator-max-microvolt = <3300000>;
-				regulator-state-mem {
-					regulator-off-in-suspend;
-				};
-			};
-
-			vcc_5v0: SWITCH_REG1 {
-				regulator-name = "vcc_5v0";
-			};
-
-			vcc_3v3: SWITCH_REG2 {
-				regulator-name = "vcc_3v3";
-				regulator-always-on;
-				regulator-boot-on;
-			};
-		};
-	};
-};
-
-&pinctrl {
-	bt {
-		bt_enable: bt-enable {
-			rockchip,pins = <3 RK_PA5 RK_FUNC_GPIO &pcfg_pull_none>;
-		};
-	};
-
-	flash {
-		flash_vol_sel: flash-vol-sel {
-			rockchip,pins = <0 RK_PB3 RK_FUNC_GPIO &pcfg_pull_none>;
-		};
-	};
-
-	pmic {
-		pmic_int_l: pmic-int-l {
-			rockchip,pins = <0 RK_PB1 RK_FUNC_GPIO &pcfg_pull_up>;
-		};
-	};
-
-	wifi {
-		wifi_enable_h: wifi-enable-h {
-			rockchip,pins = <1 RK_PD0 RK_FUNC_GPIO &pcfg_pull_none>;
-		};
-	};
-};
-
-&pmu_io_domains {
-	pmuio0-supply = <&vcc1v8_pmu>;
-	pmuio1-supply = <&vcc3v3_sys>;
-	vccio1-supply = <&vccio_flash>;
-	vccio2-supply = <&vccio_sd>;
-	vccio3-supply = <&vcc_1v8>;
-	vccio4-supply = <&vcc_dovdd>;
-	vccio5-supply = <&vcc_1v8>;
-	vccio6-supply = <&vcc_1v8>;
-	vccio7-supply = <&vcc_dovdd>;
-	status = "okay";
-};
-
-&saradc {
-	vref-supply = <&vcc_1v8>;
-	status = "okay";
-};
-
-&sfc {
-	pinctrl-names = "default";
-	pinctrl-0 = <&fspi_pins>;
-	#address-cells = <1>;
-	#size-cells = <0>;
-	status = "okay";
-
-	flash@0 {
-		compatible = "jedec,spi-nor";
-		reg = <0>;
-		spi-max-frequency = <50000000>;
-		spi-rx-bus-width = <4>;
-		spi-tx-bus-width = <1>;
-	};
-};
-
-&sdio {
-	bus-width = <4>;
-	cap-sd-highspeed;
-	cap-sdio-irq;
-	keep-power-in-suspend;
-	max-frequency = <100000000>;
-	mmc-pwrseq = <&sdio_pwrseq>;
-	non-removable;
-	pinctrl-names = "default";
-	pinctrl-0 = <&sdmmc1_clk &sdmmc1_cmd &sdmmc1_bus4>;
-	rockchip,default-sample-phase = <90>;
-	sd-uhs-sdr104;
-	vmmc-supply = <&vcc3v3_sys>;
-	vqmmc-supply = <&vcc_1v8>;
-	status = "okay";
-	#address-cells = <1>;
-	#size-cells = <0>;
-};
-
-&uart0 {
-	pinctrl-names = "default";
-	pinctrl-0 = <&uart0_xfer &uart0_ctsn &uart0_rtsn>;
-	status = "okay";
-
-	bluetooth {
-		compatible = "qcom,qca9377-bt";
-		clocks = <&rk809 1>;
-		enable-gpios = <&gpio3 RK_PA5 GPIO_ACTIVE_HIGH>; /* BT_RST */
-		max-speed = <2000000>;
-		pinctrl-names = "default";
-		pinctrl-0 = <&bt_enable>;
-		vddxo-supply = <&vcc3v3_sys>;
-		vddio-supply = <&vcc_1v8>;
-	};
-};
diff --git a/arch/arm/dts/rv1126-pinctrl.dtsi b/arch/arm/dts/rv1126-pinctrl.dtsi
deleted file mode 100644
index f84f5f2..0000000
--- a/arch/arm/dts/rv1126-pinctrl.dtsi
+++ /dev/null
@@ -1,341 +0,0 @@
-// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
-/*
- * Copyright (c) 2020 Fuzhou Rockchip Electronics Co., Ltd
- */
-
-#include <dt-bindings/pinctrl/rockchip.h>
-#include "rockchip-pinconf.dtsi"
-
-/*
- * This file is auto generated by pin2dts tool, please keep these code
- * by adding changes at end of this file.
- */
-&pinctrl {
-	clk_out_ethernet {
-		/omit-if-no-ref/
-		clk_out_ethernetm1_pins: clk-out-ethernetm1-pins {
-			rockchip,pins =
-				/* clk_out_ethernet_m1 */
-				<2 RK_PC5 2 &pcfg_pull_none>;
-		};
-	};
-	emmc {
-		/omit-if-no-ref/
-		emmc_rstnout: emmc-rstnout {
-			rockchip,pins =
-				/* emmc_rstn */
-				<1 RK_PA3 2 &pcfg_pull_none>;
-		};
-		/omit-if-no-ref/
-		emmc_bus8: emmc-bus8 {
-			rockchip,pins =
-				/* emmc_d0 */
-				<0 RK_PC4 2 &pcfg_pull_up_drv_level_2>,
-				/* emmc_d1 */
-				<0 RK_PC5 2 &pcfg_pull_up_drv_level_2>,
-				/* emmc_d2 */
-				<0 RK_PC6 2 &pcfg_pull_up_drv_level_2>,
-				/* emmc_d3 */
-				<0 RK_PC7 2 &pcfg_pull_up_drv_level_2>,
-				/* emmc_d4 */
-				<0 RK_PD0 2 &pcfg_pull_up_drv_level_2>,
-				/* emmc_d5 */
-				<0 RK_PD1 2 &pcfg_pull_up_drv_level_2>,
-				/* emmc_d6 */
-				<0 RK_PD2 2 &pcfg_pull_up_drv_level_2>,
-				/* emmc_d7 */
-				<0 RK_PD3 2 &pcfg_pull_up_drv_level_2>;
-		};
-		/omit-if-no-ref/
-		emmc_clk: emmc-clk {
-			rockchip,pins =
-				/* emmc_clko */
-				<0 RK_PD7 2 &pcfg_pull_up_drv_level_2>;
-		};
-		/omit-if-no-ref/
-		emmc_cmd: emmc-cmd {
-			rockchip,pins =
-				/* emmc_cmd */
-				<0 RK_PD5 2 &pcfg_pull_up_drv_level_2>;
-		};
-	};
-	fspi {
-		/omit-if-no-ref/
-		fspi_pins: fspi-pins {
-			rockchip,pins =
-				/* fspi_clk */
-				<1 RK_PA3 3 &pcfg_pull_down>,
-				/* fspi_cs0n */
-				<0 RK_PD4 3 &pcfg_pull_up>,
-				/* fspi_d0 */
-				<1 RK_PA0 3 &pcfg_pull_up>,
-				/* fspi_d1 */
-				<1 RK_PA1 3 &pcfg_pull_up>,
-				/* fspi_d2 */
-				<0 RK_PD6 3 &pcfg_pull_up>,
-				/* fspi_d3 */
-				<1 RK_PA2 3 &pcfg_pull_up>;
-		};
-	};
-	i2c0 {
-		/omit-if-no-ref/
-		i2c0_xfer: i2c0-xfer {
-			rockchip,pins =
-				/* i2c0_scl */
-				<0 RK_PB4 1 &pcfg_pull_none_drv_level_0_smt>,
-				/* i2c0_sda */
-				<0 RK_PB5 1 &pcfg_pull_none_drv_level_0_smt>;
-		};
-	};
-	i2c2 {
-		/omit-if-no-ref/
-		i2c2_xfer: i2c2-xfer {
-			rockchip,pins =
-				/* i2c2_scl */
-				<0 RK_PC2 1 &pcfg_pull_none_drv_level_0_smt>,
-				/* i2c2_sda */
-				<0 RK_PC3 1 &pcfg_pull_none_drv_level_0_smt>;
-		};
-	};
-	pwm2 {
-		/omit-if-no-ref/
-		pwm2m0_pins: pwm2m0-pins {
-			rockchip,pins =
-				/* pwm2_pin_m0 */
-				<0 RK_PC0 3 &pcfg_pull_none>;
-		};
-	};
-	pwm11 {
-		/omit-if-no-ref/
-		pwm11m0_pins: pwm11m0-pins {
-			rockchip,pins =
-				/* pwm11_pin_m0 */
-				<3 RK_PA7 6 &pcfg_pull_none>;
-		};
-	};
-	rgmii {
-		/omit-if-no-ref/
-		rgmiim1_miim: rgmiim1-miim {
-			rockchip,pins =
-				/* rgmii_mdc_m1 */
-				<2 RK_PC2 2 &pcfg_pull_none>,
-				/* rgmii_mdio_m1 */
-				<2 RK_PC1 2 &pcfg_pull_none>;
-		};
-		/omit-if-no-ref/
-		rgmiim1_rxer: rgmiim1-rxer {
-			rockchip,pins =
-				/* rgmii_rxer_m1 */
-				<2 RK_PC0 2 &pcfg_pull_none>;
-		};
-		/omit-if-no-ref/
-		rgmiim1_bus2: rgmiim1-bus2 {
-			rockchip,pins =
-				/* rgmii_rxd0_m1 */
-				<2 RK_PB5 2 &pcfg_pull_none>,
-				/* rgmii_rxd1_m1 */
-				<2 RK_PB6 2 &pcfg_pull_none>,
-				/* rgmii_rxdv_m1 */
-				<2 RK_PB4 2 &pcfg_pull_none>,
-				/* rgmii_txd0_m1 */
-				<2 RK_PC3 2 &pcfg_pull_none_drv_level_3>,
-				/* rgmii_txd1_m1 */
-				<2 RK_PC4 2 &pcfg_pull_none_drv_level_3>,
-				/* rgmii_txen_m1 */
-				<2 RK_PC6 2 &pcfg_pull_none_drv_level_3>;
-		};
-		/omit-if-no-ref/
-		rgmiim1_bus4: rgmiim1-bus4 {
-			rockchip,pins =
-				/* rgmii_rxclk_m1 */
-				<2 RK_PD3 2 &pcfg_pull_none>,
-				/* rgmii_rxd2_m1 */
-				<2 RK_PC7 2 &pcfg_pull_none>,
-				/* rgmii_rxd3_m1 */
-				<2 RK_PD0 2 &pcfg_pull_none>,
-				/* rgmii_txclk_m1 */
-				<2 RK_PD2 2 &pcfg_pull_none_drv_level_3>,
-				/* rgmii_txd2_m1 */
-				<2 RK_PD1 2 &pcfg_pull_none_drv_level_3>,
-				/* rgmii_txd3_m1 */
-				<2 RK_PA4 2 &pcfg_pull_none_drv_level_3>;
-		};
-		/omit-if-no-ref/
-		rgmiim1_mclkinout: rgmiim1-mclkinout {
-			rockchip,pins =
-				/* rgmii_clk_m1 */
-				<2 RK_PB7 2 &pcfg_pull_none>;
-		};
-	};
-	sdmmc0 {
-		/omit-if-no-ref/
-		sdmmc0_bus4: sdmmc0-bus4 {
-			rockchip,pins =
-				/* sdmmc0_d0 */
-				<1 RK_PA4 1 &pcfg_pull_up_drv_level_2>,
-				/* sdmmc0_d1 */
-				<1 RK_PA5 1 &pcfg_pull_up_drv_level_2>,
-				/* sdmmc0_d2 */
-				<1 RK_PA6 1 &pcfg_pull_up_drv_level_2>,
-				/* sdmmc0_d3 */
-				<1 RK_PA7 1 &pcfg_pull_up_drv_level_2>;
-		};
-		/omit-if-no-ref/
-		sdmmc0_clk: sdmmc0-clk {
-			rockchip,pins =
-				/* sdmmc0_clk */
-				<1 RK_PB0 1 &pcfg_pull_up_drv_level_2>;
-		};
-		/omit-if-no-ref/
-		sdmmc0_cmd: sdmmc0-cmd {
-			rockchip,pins =
-				/* sdmmc0_cmd */
-				<1 RK_PB1 1 &pcfg_pull_up_drv_level_2>;
-		};
-		/omit-if-no-ref/
-		sdmmc0_det: sdmmc0-det {
-			rockchip,pins =
-				<0 RK_PA3 1 &pcfg_pull_none>;
-		};
-		/omit-if-no-ref/
-		sdmmc0_pwr: sdmmc0-pwr {
-			rockchip,pins =
-				<0 RK_PC0 1 &pcfg_pull_none>;
-		};
-	};
-	sdmmc1 {
-		/omit-if-no-ref/
-		sdmmc1_bus4: sdmmc1-bus4 {
-			rockchip,pins =
-				/* sdmmc1_d0 */
-				<1 RK_PB4 1 &pcfg_pull_up_drv_level_2>,
-				/* sdmmc1_d1 */
-				<1 RK_PB5 1 &pcfg_pull_up_drv_level_2>,
-				/* sdmmc1_d2 */
-				<1 RK_PB6 1 &pcfg_pull_up_drv_level_2>,
-				/* sdmmc1_d3 */
-				<1 RK_PB7 1 &pcfg_pull_up_drv_level_2>;
-		};
-		/omit-if-no-ref/
-		sdmmc1_clk: sdmmc1-clk {
-			rockchip,pins =
-				/* sdmmc1_clk */
-				<1 RK_PB2 1 &pcfg_pull_up_drv_level_2>;
-		};
-		/omit-if-no-ref/
-		sdmmc1_cmd: sdmmc1-cmd {
-			rockchip,pins =
-				/* sdmmc1_cmd */
-				<1 RK_PB3 1 &pcfg_pull_up_drv_level_2>;
-		};
-		/omit-if-no-ref/
-		sdmmc1_det: sdmmc1-det {
-			rockchip,pins =
-				<1 RK_PD0 2 &pcfg_pull_none>;
-		};
-		/omit-if-no-ref/
-		sdmmc1_pwr: sdmmc1-pwr {
-			rockchip,pins =
-				<1 RK_PD1 2 &pcfg_pull_none>;
-		};
-	};
-	uart0 {
-		/omit-if-no-ref/
-		uart0_xfer: uart0-xfer {
-			rockchip,pins =
-				/* uart0_rx */
-				<1 RK_PC2 1 &pcfg_pull_up>,
-				/* uart0_tx */
-				<1 RK_PC3 1 &pcfg_pull_up>;
-		};
-		/omit-if-no-ref/
-		uart0_ctsn: uart0-ctsn {
-			rockchip,pins =
-				<1 RK_PC1 1 &pcfg_pull_none>;
-		};
-		/omit-if-no-ref/
-		uart0_rtsn: uart0-rtsn {
-			rockchip,pins =
-				<1 RK_PC0 1 &pcfg_pull_none>;
-		};
-		/omit-if-no-ref/
-		uart0_rtsn_gpio: uart0-rts-pin {
-			rockchip,pins =
-				<1 RK_PC0 RK_FUNC_GPIO &pcfg_pull_none>;
-		};
-	};
-	uart1 {
-		/omit-if-no-ref/
-		uart1m0_xfer: uart1m0-xfer {
-			rockchip,pins =
-				/* uart1_rx_m0 */
-				<0 RK_PB7 2 &pcfg_pull_up>,
-				/* uart1_tx_m0 */
-				<0 RK_PB6 2 &pcfg_pull_up>;
-		};
-	};
-	uart2 {
-		/omit-if-no-ref/
-		uart2m1_xfer: uart2m1-xfer {
-			rockchip,pins =
-				/* uart2_rx_m1 */
-				<3 RK_PA3 1 &pcfg_pull_up>,
-				/* uart2_tx_m1 */
-				<3 RK_PA2 1 &pcfg_pull_up>;
-		};
-	};
-	uart3 {
-		/omit-if-no-ref/
-		uart3m0_xfer: uart3m0-xfer {
-			rockchip,pins =
-				/* uart3_rx_m0 */
-				<3 RK_PC7 4 &pcfg_pull_up>,
-				/* uart3_tx_m0 */
-				<3 RK_PC6 4 &pcfg_pull_up>;
-		};
-		/omit-if-no-ref/
-		uart3m2_xfer: uart3m2-xfer {
-			rockchip,pins =
-				/* uart3_rx_m2 */
-				<3 RK_PA1 4 &pcfg_pull_up>,
-				/* uart3_tx_m2 */
-				<3 RK_PA0 4 &pcfg_pull_up>;
-		};
-	};
-	uart4 {
-		/omit-if-no-ref/
-		uart4m0_xfer: uart4m0-xfer {
-			rockchip,pins =
-				/* uart4_rx_m0 */
-				<3 RK_PA5 4 &pcfg_pull_up>,
-				/* uart4_tx_m0 */
-				<3 RK_PA4 4 &pcfg_pull_up>;
-		};
-		/omit-if-no-ref/
-		uart4m2_xfer: uart4m2-xfer {
-			rockchip,pins =
-				/* uart4_rx_m2 */
-				<1 RK_PD4 3 &pcfg_pull_up>,
-				/* uart4_tx_m2 */
-				<1 RK_PD5 3 &pcfg_pull_up>;
-		};
-	};
-	uart5 {
-		/omit-if-no-ref/
-		uart5m0_xfer: uart5m0-xfer {
-			rockchip,pins =
-				/* uart5_rx_m0 */
-				<3 RK_PA7 4 &pcfg_pull_up>,
-				/* uart5_tx_m0 */
-				<3 RK_PA6 4 &pcfg_pull_up>;
-		};
-		/omit-if-no-ref/
-		uart5m2_xfer: uart5m2-xfer {
-			rockchip,pins =
-				/* uart5_rx_m2 */
-				<2 RK_PA1 3 &pcfg_pull_up>,
-				/* uart5_tx_m2 */
-				<2 RK_PA0 3 &pcfg_pull_up>;
-		};
-	};
-};
diff --git a/arch/arm/dts/rv1126-sonoff-ihost.dts b/arch/arm/dts/rv1126-sonoff-ihost.dts
deleted file mode 100644
index 77386a4..0000000
--- a/arch/arm/dts/rv1126-sonoff-ihost.dts
+++ /dev/null
@@ -1,29 +0,0 @@
-// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
-/*
- * Copyright (c) 2020 Rockchip Electronics Co., Ltd.
- */
-
-/dts-v1/;
-#include "rv1126.dtsi"
-#include "rv1126-sonoff-ihost.dtsi"
-
-/ {
-	model = "Sonoff iHost 4G";
-	compatible = "itead,sonoff-ihost", "rockchip,rv1126";
-};
-
-&cpu0 {
-	cpu-supply = <&vdd_arm>;
-};
-
-&cpu1 {
-	cpu-supply = <&vdd_arm>;
-};
-
-&cpu2 {
-	cpu-supply = <&vdd_arm>;
-};
-
-&cpu3 {
-	cpu-supply = <&vdd_arm>;
-};
diff --git a/arch/arm/dts/rv1126-sonoff-ihost.dtsi b/arch/arm/dts/rv1126-sonoff-ihost.dtsi
deleted file mode 100644
index 32b329e..0000000
--- a/arch/arm/dts/rv1126-sonoff-ihost.dtsi
+++ /dev/null
@@ -1,404 +0,0 @@
-// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
-/*
- * Copyright (c) 2020 Rockchip Electronics Co., Ltd.
- * Copyright (c) 2022 Edgeble AI Technologies Pvt. Ltd.
- */
-
-/ {
-	aliases {
-		ethernet0 = &gmac;
-		mmc0 = &emmc;
-	};
-
-	chosen {
-		stdout-path = "serial2:1500000n8";
-	};
-
-	vcc5v0_sys: regulator-vcc5v0-sys {
-		compatible = "regulator-fixed";
-		regulator-name = "vcc5v0_sys";
-		regulator-always-on;
-		regulator-boot-on;
-		regulator-min-microvolt = <5000000>;
-		regulator-max-microvolt = <5000000>;
-	};
-
-	sdio_pwrseq: pwrseq-sdio {
-		compatible = "mmc-pwrseq-simple";
-		clocks = <&rk809 1>;
-		clock-names = "ext_clock";
-		pinctrl-names = "default";
-		pinctrl-0 = <&wifi_enable_h>;
-		reset-gpios = <&gpio1 RK_PD0 GPIO_ACTIVE_LOW>;
-	};
-};
-
-&emmc {
-	bus-width = <8>;
-	cap-mmc-highspeed;
-	mmc-hs200-1_8v;
-	non-removable;
-	pinctrl-names = "default";
-	pinctrl-0 = <&emmc_bus8 &emmc_cmd &emmc_clk &emmc_rstnout>;
-	rockchip,default-sample-phase = <90>;
-	vmmc-supply = <&vcc_3v3>;
-	vqmmc-supply = <&vcc_1v8>;
-	status = "okay";
-};
-
-&i2c0 {
-	clock-frequency = <400000>;
-	status = "okay";
-
-	rk809: pmic@20 {
-		compatible = "rockchip,rk809";
-		reg = <0x20>;
-		interrupt-parent = <&gpio0>;
-		interrupts = <RK_PB1 IRQ_TYPE_LEVEL_LOW>;
-		#clock-cells = <1>;
-		clock-output-names = "rk808-clkout1", "rk808-clkout2";
-		pinctrl-names = "default";
-		pinctrl-0 = <&pmic_int_l>;
-		rockchip,system-power-controller;
-		wakeup-source;
-
-		vcc1-supply = <&vcc5v0_sys>;
-		vcc2-supply = <&vcc5v0_sys>;
-		vcc3-supply = <&vcc5v0_sys>;
-		vcc4-supply = <&vcc5v0_sys>;
-		vcc5-supply = <&vcc_buck5>;
-		vcc6-supply = <&vcc_buck5>;
-		vcc7-supply = <&vcc5v0_sys>;
-		vcc8-supply = <&vcc3v3_sys>;
-		vcc9-supply = <&vcc5v0_sys>;
-
-		regulators {
-			vdd_npu_vepu: DCDC_REG1 {
-				regulator-name = "vdd_npu_vepu";
-				regulator-always-on;
-				regulator-boot-on;
-				regulator-initial-mode = <0x2>;
-				regulator-min-microvolt = <650000>;
-				regulator-max-microvolt = <950000>;
-				regulator-ramp-delay = <6001>;
-				regulator-state-mem {
-					regulator-off-in-suspend;
-				};
-			};
-
-			vdd_arm: DCDC_REG2 {
-				regulator-name = "vdd_arm";
-				regulator-always-on;
-				regulator-boot-on;
-				regulator-initial-mode = <0x2>;
-				regulator-min-microvolt = <725000>;
-				regulator-max-microvolt = <1350000>;
-				regulator-ramp-delay = <6001>;
-				regulator-state-mem {
-					regulator-off-in-suspend;
-				};
-			};
-
-			vcc_ddr: DCDC_REG3 {
-				regulator-name = "vcc_ddr";
-				regulator-always-on;
-				regulator-boot-on;
-				regulator-initial-mode = <0x2>;
-				regulator-state-mem {
-					regulator-on-in-suspend;
-				};
-			};
-
-			vcc3v3_sys: DCDC_REG4 {
-				regulator-name = "vcc3v3_sys";
-				regulator-always-on;
-				regulator-boot-on;
-				regulator-initial-mode = <0x2>;
-				regulator-min-microvolt = <3300000>;
-				regulator-max-microvolt = <3300000>;
-				regulator-state-mem {
-					regulator-on-in-suspend;
-					regulator-suspend-microvolt = <3300000>;
-				};
-			};
-
-			vcc_buck5: DCDC_REG5 {
-				regulator-name = "vcc_buck5";
-				regulator-always-on;
-				regulator-boot-on;
-				regulator-min-microvolt = <2200000>;
-				regulator-max-microvolt = <2200000>;
-				regulator-state-mem {
-					regulator-on-in-suspend;
-					regulator-suspend-microvolt = <2200000>;
-				};
-			};
-
-			vcc_0v8: LDO_REG1 {
-				regulator-name = "vcc_0v8";
-				regulator-always-on;
-				regulator-boot-on;
-				regulator-min-microvolt = <800000>;
-				regulator-max-microvolt = <800000>;
-				regulator-state-mem {
-					regulator-off-in-suspend;
-				};
-			};
-
-			vcc1v8_pmu: LDO_REG2 {
-				regulator-name = "vcc1v8_pmu";
-				regulator-always-on;
-				regulator-boot-on;
-				regulator-min-microvolt = <1800000>;
-				regulator-max-microvolt = <1800000>;
-				regulator-state-mem {
-					regulator-on-in-suspend;
-					regulator-suspend-microvolt = <1800000>;
-				};
-			};
-
-			vdd0v8_pmu: LDO_REG3 {
-				regulator-name = "vcc0v8_pmu";
-				regulator-always-on;
-				regulator-boot-on;
-				regulator-min-microvolt = <800000>;
-				regulator-max-microvolt = <800000>;
-				regulator-state-mem {
-					regulator-on-in-suspend;
-					regulator-suspend-microvolt = <800000>;
-				};
-			};
-
-			vcc_1v8: LDO_REG4 {
-				regulator-name = "vcc_1v8";
-				regulator-always-on;
-				regulator-boot-on;
-				regulator-min-microvolt = <1800000>;
-				regulator-max-microvolt = <1800000>;
-				regulator-state-mem {
-					regulator-on-in-suspend;
-					regulator-suspend-microvolt = <1800000>;
-				};
-			};
-
-			vcc_dovdd: LDO_REG5 {
-				regulator-name = "vcc_dovdd";
-				regulator-always-on;
-				regulator-boot-on;
-				regulator-min-microvolt = <1800000>;
-				regulator-max-microvolt = <1800000>;
-				regulator-state-mem {
-					regulator-off-in-suspend;
-				};
-			};
-
-			vcc_dvdd: LDO_REG6 {
-				regulator-name = "vcc_dvdd";
-				regulator-min-microvolt = <1200000>;
-				regulator-max-microvolt = <1200000>;
-				regulator-state-mem {
-					regulator-off-in-suspend;
-				};
-			};
-
-			vcc_avdd: LDO_REG7 {
-				regulator-name = "vcc_avdd";
-				regulator-min-microvolt = <2800000>;
-				regulator-max-microvolt = <2800000>;
-				regulator-state-mem {
-					regulator-off-in-suspend;
-				};
-			};
-
-			vccio_sd: LDO_REG8 {
-				regulator-name = "vccio_sd";
-				regulator-always-on;
-				regulator-boot-on;
-				regulator-min-microvolt = <1800000>;
-				regulator-max-microvolt = <3300000>;
-				regulator-state-mem {
-					regulator-off-in-suspend;
-				};
-			};
-
-			vcc3v3_sd: LDO_REG9 {
-				regulator-name = "vcc3v3_sd";
-				regulator-always-on;
-				regulator-boot-on;
-				regulator-min-microvolt = <3300000>;
-				regulator-max-microvolt = <3300000>;
-				regulator-state-mem {
-					regulator-off-in-suspend;
-				};
-			};
-
-			vcc_5v0: SWITCH_REG1 {
-				regulator-name = "vcc_5v0";
-			};
-
-			vcc_3v3: SWITCH_REG2 {
-				regulator-name = "vcc_3v3";
-				regulator-always-on;
-				regulator-boot-on;
-			};
-		};
-	};
-};
-
-&i2c2 {
-	status = "okay";
-	clock-frequency = <400000>;
-
-	pcf8563: rtc@51 {
-		compatible = "nxp,pcf8563";
-		reg = <0x51>;
-		#clock-cells = <0>;
-		interrupt-parent = <&gpio0>;
-		interrupts = <RK_PA2 IRQ_TYPE_LEVEL_LOW>;
-		clock-output-names = "xin32k";
-	};
-};
-
-&gmac {
-	assigned-clocks = <&cru CLK_GMAC_SRC_M1>, <&cru CLK_GMAC_SRC>,
-			  <&cru CLK_GMAC_TX_RX>;
-	assigned-clock-parents = <&cru CLK_GMAC_RGMII_M1>, <&cru CLK_GMAC_SRC_M1>,
-				 <&cru RMII_MODE_CLK>;
-	assigned-clock-rates = <0>, <50000000>;
-	clock_in_out = "output";
-	phy-handle = <&phy>;
-	phy-mode = "rmii";
-	phy-supply = <&vcc_3v3>;
-	pinctrl-names = "default";
-	pinctrl-0 = <&rgmiim1_miim &rgmiim1_rxer &rgmiim1_bus2 &rgmiim1_mclkinout>;
-	status = "okay";
-};
-
-&mdio {
-	phy: ethernet-phy@0 {
-		compatible = "ethernet-phy-ieee802.3-c22";
-		reg = <0x0>;
-		pinctrl-names = "default";
-		pinctrl-0 = <&eth_phy_rst>;
-		reset-active-low;
-		reset-assert-us = <50000>;
-		reset-deassert-us = <10000>;
-		reset-gpios = <&gpio2 RK_PA6 GPIO_ACTIVE_LOW>;
-	};
-};
-
-&pinctrl {
-	ethernet {
-		eth_phy_rst: eth-phy-rst {
-			rockchip,pins = <2 RK_PA6 RK_FUNC_GPIO &pcfg_pull_down>;
-		};
-	};
-	bt {
-		bt_enable: bt-enable {
-			rockchip,pins = <1 RK_PC6 RK_FUNC_GPIO &pcfg_pull_none>;
-		};
-
-		bt_wake_dev: bt-wake-dev {
-			rockchip,pins = <1 RK_PC7 RK_FUNC_GPIO &pcfg_pull_none>;
-		};
-
-		bt_wake_host: bt-wake-host {
-			rockchip,pins = <1 RK_PC5 RK_FUNC_GPIO &pcfg_pull_none>;
-		};
-	};
-
-	pmic {
-		pmic_int_l: pmic-int-l {
-			rockchip,pins = <0 RK_PB1 RK_FUNC_GPIO &pcfg_pull_up>;
-		};
-	};
-
-	wifi {
-		wifi_enable_h: wifi-enable-h {
-			rockchip,pins = <1 RK_PD0 RK_FUNC_GPIO &pcfg_pull_none>;
-		};
-	};
-};
-
-&pmu_io_domains {
-	pmuio0-supply = <&vcc1v8_pmu>;
-	pmuio1-supply = <&vcc3v3_sys>;
-	vccio1-supply = <&vcc_1v8>;
-	vccio2-supply = <&vccio_sd>;
-	vccio3-supply = <&vcc_1v8>;
-	vccio4-supply = <&vcc_dovdd>;
-	vccio5-supply = <&vcc_1v8>;
-	vccio6-supply = <&vcc_1v8>;
-	vccio7-supply = <&vcc_dovdd>;
-	status = "okay";
-};
-
-&saradc {
-	vref-supply = <&vcc_1v8>;
-	status = "okay";
-};
-
-&sdio {
-	bus-width = <4>;
-	cap-sd-highspeed;
-	cap-sdio-irq;
-	keep-power-in-suspend;
-	max-frequency = <100000000>;
-	mmc-pwrseq = <&sdio_pwrseq>;
-	non-removable;
-	pinctrl-names = "default";
-	pinctrl-0 = <&sdmmc1_clk &sdmmc1_cmd &sdmmc1_bus4>;
-	rockchip,default-sample-phase = <90>;
-	sd-uhs-sdr104;
-	vmmc-supply = <&vcc3v3_sys>;
-	vqmmc-supply = <&vcc_1v8>;
-	status = "okay";
-};
-
-&sdmmc {
-	bus-width = <4>;
-	cap-mmc-highspeed;
-	cap-sd-highspeed;
-	card-detect-delay = <200>;
-	pinctrl-names = "default";
-	pinctrl-0 = <&sdmmc0_clk &sdmmc0_cmd &sdmmc0_bus4 &sdmmc0_det>;
-	rockchip,default-sample-phase = <90>;
-	sd-uhs-sdr12;
-	sd-uhs-sdr25;
-	sd-uhs-sdr104;
-	vqmmc-supply = <&vccio_sd>;
-	status = "okay";
-};
-
-&uart0 {
-	pinctrl-names = "default";
-	pinctrl-0 = <&uart0_xfer &uart0_ctsn &uart0_rtsn>;
-	uart-has-rtscts;
-	status = "okay";
-
-	bluetooth {
-		compatible = "realtek,rtl8723ds-bt";
-		device-wake-gpios = <&gpio1 RK_PC7 GPIO_ACTIVE_HIGH>; /* BT_WAKE */
-		enable-gpios = <&gpio1 RK_PC6 GPIO_ACTIVE_HIGH>; /* BT_RST */
-		host-wake-gpios = <&gpio1 RK_PC5 GPIO_ACTIVE_HIGH>; /* BT_WAKE_HOST */
-		max-speed = <2000000>;
-		pinctrl-names = "default";
-		pinctrl-0 = <&bt_enable>, <&bt_wake_dev>, <&bt_wake_host>;
-	};
-};
-
-&uart2 {
-	status = "okay";
-};
-
-&uart3 {
-	pinctrl-names = "default";
-	pinctrl-0 = <&uart3m2_xfer>;
-	status = "okay";
-};
-
-&uart4 {
-	pinctrl-names = "default";
-	pinctrl-0 = <&uart4m2_xfer>;
-	status = "okay";
-};
diff --git a/arch/arm/dts/rv1126.dtsi b/arch/arm/dts/rv1126.dtsi
deleted file mode 100644
index bb603ca..0000000
--- a/arch/arm/dts/rv1126.dtsi
+++ /dev/null
@@ -1,623 +0,0 @@
-// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
-/*
- * Copyright (c) 2019 Fuzhou Rockchip Electronics Co., Ltd.
- */
-
-#include <dt-bindings/clock/rockchip,rv1126-cru.h>
-#include <dt-bindings/gpio/gpio.h>
-#include <dt-bindings/interrupt-controller/arm-gic.h>
-#include <dt-bindings/interrupt-controller/irq.h>
-#include <dt-bindings/pinctrl/rockchip.h>
-#include <dt-bindings/power/rockchip,rv1126-power.h>
-#include <dt-bindings/soc/rockchip,boot-mode.h>
-
-/ {
-	#address-cells = <1>;
-	#size-cells = <1>;
-
-	compatible = "rockchip,rv1126";
-
-	interrupt-parent = <&gic>;
-
-	aliases {
-		i2c0 = &i2c0;
-		i2c2 = &i2c2;
-		serial0 = &uart0;
-		serial1 = &uart1;
-		serial2 = &uart2;
-		serial3 = &uart3;
-		serial4 = &uart4;
-		serial5 = &uart5;
-	};
-
-	cpus {
-		#address-cells = <1>;
-		#size-cells = <0>;
-
-		cpu0: cpu@f00 {
-			device_type = "cpu";
-			compatible = "arm,cortex-a7";
-			reg = <0xf00>;
-			enable-method = "psci";
-			clocks = <&cru ARMCLK>;
-		};
-
-		cpu1: cpu@f01 {
-			device_type = "cpu";
-			compatible = "arm,cortex-a7";
-			reg = <0xf01>;
-			enable-method = "psci";
-			clocks = <&cru ARMCLK>;
-		};
-
-		cpu2: cpu@f02 {
-			device_type = "cpu";
-			compatible = "arm,cortex-a7";
-			reg = <0xf02>;
-			enable-method = "psci";
-			clocks = <&cru ARMCLK>;
-		};
-
-		cpu3: cpu@f03 {
-			device_type = "cpu";
-			compatible = "arm,cortex-a7";
-			reg = <0xf03>;
-			enable-method = "psci";
-			clocks = <&cru ARMCLK>;
-		};
-	};
-
-	arm-pmu {
-		compatible = "arm,cortex-a7-pmu";
-		interrupts = <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>,
-			     <GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>,
-			     <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>,
-			     <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>;
-		interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>;
-	};
-
-	psci {
-		compatible = "arm,psci-1.0";
-		method = "smc";
-	};
-
-	timer {
-		compatible = "arm,armv7-timer";
-		interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
-			     <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
-			     <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
-			     <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
-		clock-frequency = <24000000>;
-	};
-
-	display_subsystem {
-		compatible = "rockchip,display-subsystem";
-		ports = <&vop_out>;
-	};
-
-	xin24m: oscillator {
-		compatible = "fixed-clock";
-		clock-frequency = <24000000>;
-		clock-output-names = "xin24m";
-		#clock-cells = <0>;
-	};
-
-	grf: syscon@fe000000 {
-		compatible = "rockchip,rv1126-grf", "syscon", "simple-mfd";
-		reg = <0xfe000000 0x20000>;
-	};
-
-	pmugrf: syscon@fe020000 {
-		compatible = "rockchip,rv1126-pmugrf", "syscon", "simple-mfd";
-		reg = <0xfe020000 0x1000>;
-
-		pmu_io_domains: io-domains {
-			compatible = "rockchip,rv1126-pmu-io-voltage-domain";
-			status = "disabled";
-		};
-	};
-
-	qos_emmc: qos@fe860000 {
-		compatible = "rockchip,rv1126-qos", "syscon";
-		reg = <0xfe860000 0x20>;
-	};
-
-	qos_nandc: qos@fe860080 {
-		compatible = "rockchip,rv1126-qos", "syscon";
-		reg = <0xfe860080 0x20>;
-	};
-
-	qos_sfc: qos@fe860200 {
-		compatible = "rockchip,rv1126-qos", "syscon";
-		reg = <0xfe860200 0x20>;
-	};
-
-	qos_sdio: qos@fe86c000 {
-		compatible = "rockchip,rv1126-qos", "syscon";
-		reg = <0xfe86c000 0x20>;
-	};
-
-	qos_iep: qos@fe8a0000 {
-		compatible = "rockchip,rv1126-qos", "syscon";
-		reg = <0xfe8a0000 0x20>;
-	};
-
-	qos_rga_rd: qos@fe8a0080 {
-		compatible = "rockchip,rv1126-qos", "syscon";
-		reg = <0xfe8a0080 0x20>;
-	};
-
-	qos_rga_wr: qos@fe8a0100 {
-		compatible = "rockchip,rv1126-qos", "syscon";
-		reg = <0xfe8a0100 0x20>;
-	};
-
-	qos_vop: qos@fe8a0180 {
-		compatible = "rockchip,rv1126-qos", "syscon";
-		reg = <0xfe8a0180 0x20>;
-	};
-
-	gic: interrupt-controller@feff0000 {
-		compatible = "arm,gic-400";
-		interrupt-controller;
-		#interrupt-cells = <3>;
-		#address-cells = <0>;
-
-		reg = <0xfeff1000 0x1000>,
-		      <0xfeff2000 0x2000>,
-		      <0xfeff4000 0x2000>,
-		      <0xfeff6000 0x2000>;
-		interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
-	};
-
-	pmu: power-management@ff3e0000 {
-		compatible = "rockchip,rv1126-pmu", "syscon", "simple-mfd";
-		reg = <0xff3e0000 0x1000>;
-
-		power: power-controller {
-			compatible = "rockchip,rv1126-power-controller";
-			#power-domain-cells = <1>;
-			#address-cells = <1>;
-			#size-cells = <0>;
-
-			power-domain@RV1126_PD_NVM {
-				reg = <RV1126_PD_NVM>;
-				clocks = <&cru HCLK_EMMC>,
-					 <&cru CLK_EMMC>,
-					 <&cru HCLK_NANDC>,
-					 <&cru CLK_NANDC>,
-					 <&cru HCLK_SFC>,
-					 <&cru HCLK_SFCXIP>,
-					 <&cru SCLK_SFC>;
-				pm_qos = <&qos_emmc>,
-					 <&qos_nandc>,
-					 <&qos_sfc>;
-				#power-domain-cells = <0>;
-			};
-
-			power-domain@RV1126_PD_SDIO {
-				reg = <RV1126_PD_SDIO>;
-				clocks = <&cru HCLK_SDIO>,
-					 <&cru CLK_SDIO>;
-				pm_qos = <&qos_sdio>;
-				#power-domain-cells = <0>;
-			};
-
-			power-domain@RV1126_PD_VO {
-				reg = <RV1126_PD_VO>;
-				clocks = <&cru ACLK_RGA>,
-					 <&cru HCLK_RGA>,
-					 <&cru CLK_RGA_CORE>,
-					 <&cru ACLK_VOP>,
-					 <&cru HCLK_VOP>,
-					 <&cru DCLK_VOP>,
-					 <&cru PCLK_DSIHOST>,
-					 <&cru ACLK_IEP>,
-					 <&cru HCLK_IEP>,
-					 <&cru CLK_IEP_CORE>;
-				pm_qos = <&qos_rga_rd>,
-					 <&qos_rga_wr>,
-					 <&qos_vop>,
-					 <&qos_iep>;
-				#power-domain-cells = <0>;
-			};
-		};
-	};
-
-	i2c0: i2c@ff3f0000 {
-		compatible = "rockchip,rv1126-i2c", "rockchip,rk3399-i2c";
-		reg = <0xff3f0000 0x1000>;
-		interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
-		rockchip,grf = <&pmugrf>;
-		clocks = <&pmucru CLK_I2C0>, <&pmucru PCLK_I2C0>;
-		clock-names = "i2c", "pclk";
-		pinctrl-names = "default";
-		pinctrl-0 = <&i2c0_xfer>;
-		#address-cells = <1>;
-		#size-cells = <0>;
-		status = "disabled";
-	};
-
-	i2c2: i2c@ff400000 {
-		compatible = "rockchip,rv1126-i2c", "rockchip,rk3399-i2c";
-		reg = <0xff400000 0x1000>;
-		interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
-		rockchip,grf = <&pmugrf>;
-		clocks = <&pmucru CLK_I2C2>, <&pmucru PCLK_I2C2>;
-		clock-names = "i2c", "pclk";
-		pinctrl-names = "default";
-		pinctrl-0 = <&i2c2_xfer>;
-		#address-cells = <1>;
-		#size-cells = <0>;
-		status = "disabled";
-	};
-
-	uart1: serial@ff410000 {
-		compatible = "rockchip,rv1126-uart", "snps,dw-apb-uart";
-		reg = <0xff410000 0x100>;
-		interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
-		clock-frequency = <24000000>;
-		clocks = <&pmucru SCLK_UART1>, <&pmucru PCLK_UART1>;
-		clock-names = "baudclk", "apb_pclk";
-		dmas = <&dmac 7>, <&dmac 6>;
-		dma-names = "tx", "rx";
-		pinctrl-names = "default";
-		pinctrl-0 = <&uart1m0_xfer>;
-		reg-shift = <2>;
-		reg-io-width = <4>;
-		status = "disabled";
-	};
-
-	pwm2: pwm@ff430020 {
-		compatible = "rockchip,rv1126-pwm", "rockchip,rk3328-pwm";
-		reg = <0xff430020 0x10>;
-		clock-names = "pwm", "pclk";
-		clocks = <&pmucru CLK_PWM0>, <&pmucru PCLK_PWM0>;
-		pinctrl-names = "default";
-		pinctrl-0 = <&pwm2m0_pins>;
-		#pwm-cells = <3>;
-		status = "disabled";
-	};
-
-	pmucru: clock-controller@ff480000 {
-		compatible = "rockchip,rv1126-pmucru";
-		reg = <0xff480000 0x1000>;
-		rockchip,grf = <&grf>;
-		#clock-cells = <1>;
-		#reset-cells = <1>;
-	};
-
-	cru: clock-controller@ff490000 {
-		compatible = "rockchip,rv1126-cru";
-		reg = <0xff490000 0x1000>;
-		clocks = <&xin24m>;
-		clock-names = "xin24m";
-		rockchip,grf = <&grf>;
-		#clock-cells = <1>;
-		#reset-cells = <1>;
-	};
-
-	dmac: dma-controller@ff4e0000 {
-		compatible = "arm,pl330", "arm,primecell";
-		reg = <0xff4e0000 0x4000>;
-		interrupts = <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>,
-			     <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>;
-		#dma-cells = <1>;
-		arm,pl330-periph-burst;
-		clocks = <&cru ACLK_DMAC>;
-		clock-names = "apb_pclk";
-	};
-
-	pwm11: pwm@ff550030 {
-		compatible = "rockchip,rv1126-pwm", "rockchip,rk3328-pwm";
-		reg = <0xff550030 0x10>;
-		clock-names = "pwm", "pclk";
-		clocks = <&cru CLK_PWM2>, <&cru PCLK_PWM2>;
-		pinctrl-0 = <&pwm11m0_pins>;
-		pinctrl-names = "default";
-		#pwm-cells = <3>;
-		status = "disabled";
-	};
-
-	uart0: serial@ff560000 {
-		compatible = "rockchip,rv1126-uart", "snps,dw-apb-uart";
-		reg = <0xff560000 0x100>;
-		interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
-		clock-frequency = <24000000>;
-		clocks = <&cru SCLK_UART0>, <&cru PCLK_UART0>;
-		clock-names = "baudclk", "apb_pclk";
-		dmas = <&dmac 5>, <&dmac 4>;
-		dma-names = "tx", "rx";
-		pinctrl-names = "default";
-		pinctrl-0 = <&uart0_xfer>;
-		reg-shift = <2>;
-		reg-io-width = <4>;
-		status = "disabled";
-	};
-
-	uart2: serial@ff570000 {
-		compatible = "rockchip,rv1126-uart", "snps,dw-apb-uart";
-		reg = <0xff570000 0x100>;
-		interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
-		clock-frequency = <24000000>;
-		clocks = <&cru SCLK_UART2>, <&cru PCLK_UART2>;
-		clock-names = "baudclk", "apb_pclk";
-		dmas = <&dmac 9>, <&dmac 8>;
-		dma-names = "tx", "rx";
-		pinctrl-names = "default";
-		pinctrl-0 = <&uart2m1_xfer>;
-		reg-shift = <2>;
-		reg-io-width = <4>;
-		status = "disabled";
-	};
-
-	uart3: serial@ff580000 {
-		compatible = "rockchip,rv1126-uart", "snps,dw-apb-uart";
-		reg = <0xff580000 0x100>;
-		interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
-		clock-frequency = <24000000>;
-		clocks = <&cru SCLK_UART3>, <&cru PCLK_UART3>;
-		clock-names = "baudclk", "apb_pclk";
-		dmas = <&dmac 11>, <&dmac 10>;
-		dma-names = "tx", "rx";
-		pinctrl-names = "default";
-		pinctrl-0 = <&uart3m0_xfer>;
-		reg-shift = <2>;
-		reg-io-width = <4>;
-		status = "disabled";
-	};
-
-	uart4: serial@ff590000 {
-		compatible = "rockchip,rv1126-uart", "snps,dw-apb-uart";
-		reg = <0xff590000 0x100>;
-		interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
-		clock-frequency = <24000000>;
-		clocks = <&cru SCLK_UART4>, <&cru PCLK_UART4>;
-		clock-names = "baudclk", "apb_pclk";
-		dmas = <&dmac 13>, <&dmac 12>;
-		dma-names = "tx", "rx";
-		pinctrl-names = "default";
-		pinctrl-0 = <&uart4m0_xfer>;
-		reg-shift = <2>;
-		reg-io-width = <4>;
-		status = "disabled";
-	};
-
-	uart5: serial@ff5a0000 {
-		compatible = "rockchip,rv1126-uart", "snps,dw-apb-uart";
-		reg = <0xff5a0000 0x100>;
-		interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
-		clock-frequency = <24000000>;
-		clocks = <&cru SCLK_UART5>, <&cru PCLK_UART5>;
-		clock-names = "baudclk", "apb_pclk";
-		dmas = <&dmac 15>, <&dmac 14>;
-		dma-names = "tx", "rx";
-		pinctrl-names = "default";
-		pinctrl-0 = <&uart5m0_xfer>;
-		reg-shift = <2>;
-		reg-io-width = <4>;
-		status = "disabled";
-	};
-
-	saradc: adc@ff5e0000 {
-		compatible = "rockchip,rv1126-saradc", "rockchip,rk3399-saradc";
-		reg = <0xff5e0000 0x100>;
-		interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>;
-		#io-channel-cells = <1>;
-		clocks = <&cru CLK_SARADC>, <&cru PCLK_SARADC>;
-		clock-names = "saradc", "apb_pclk";
-		resets = <&cru SRST_SARADC_P>;
-		reset-names = "saradc-apb";
-		status = "disabled";
-	};
-
-	timer0: timer@ff660000 {
-		compatible = "rockchip,rv1126-timer", "rockchip,rk3288-timer";
-		reg = <0xff660000 0x20>;
-		interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
-		clocks = <&cru PCLK_TIMER>, <&cru CLK_TIMER0>;
-		clock-names = "pclk", "timer";
-	};
-
-	vop: vop@ffb00000 {
-		compatible = "rockchip,rv1126-vop";
-		reg = <0xffb00000 0x200>, <0xffb00a00 0x400>;
-		interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>;
-		clock-names = "aclk_vop", "dclk_vop", "hclk_vop";
-		clocks = <&cru ACLK_VOP>, <&cru DCLK_VOP>, <&cru HCLK_VOP>;
-		reset-names = "axi", "ahb", "dclk";
-		resets = <&cru SRST_VOP_A>, <&cru SRST_VOP_H>, <&cru SRST_VOP_D>;
-		iommus = <&vop_mmu>;
-		power-domains = <&power RV1126_PD_VO>;
-		status = "disabled";
-
-		vop_out: port {
-			#address-cells = <1>;
-			#size-cells = <0>;
-
-			vop_out_rgb: endpoint@0 {
-				reg = <0>;
-			};
-
-			vop_out_dsi: endpoint@1 {
-				reg = <1>;
-			};
-		};
-	};
-
-	vop_mmu: iommu@ffb00f00 {
-		compatible = "rockchip,iommu";
-		reg = <0xffb00f00 0x100>;
-		interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>;
-		clock-names = "aclk", "iface";
-		clocks = <&cru ACLK_VOP>, <&cru HCLK_VOP>;
-		#iommu-cells = <0>;
-		power-domains = <&power RV1126_PD_VO>;
-		status = "disabled";
-	};
-
-	gmac: ethernet@ffc40000 {
-		compatible = "rockchip,rv1126-gmac", "snps,dwmac-4.20a";
-		reg = <0xffc40000 0x4000>;
-		interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>,
-			     <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
-		interrupt-names = "macirq", "eth_wake_irq";
-		rockchip,grf = <&grf>;
-		clocks = <&cru CLK_GMAC_SRC>, <&cru CLK_GMAC_TX_RX>,
-			 <&cru CLK_GMAC_TX_RX>, <&cru CLK_GMAC_REF>,
-			 <&cru ACLK_GMAC>, <&cru PCLK_GMAC>,
-			 <&cru CLK_GMAC_TX_RX>, <&cru CLK_GMAC_PTPREF>;
-		clock-names = "stmmaceth", "mac_clk_rx",
-			      "mac_clk_tx", "clk_mac_ref",
-			      "aclk_mac", "pclk_mac",
-			      "clk_mac_speed", "ptp_ref";
-		resets = <&cru SRST_GMAC_A>;
-		reset-names = "stmmaceth";
-
-		snps,mixed-burst;
-		snps,tso;
-
-		snps,axi-config = <&stmmac_axi_setup>;
-		snps,mtl-rx-config = <&mtl_rx_setup>;
-		snps,mtl-tx-config = <&mtl_tx_setup>;
-		status = "disabled";
-
-		mdio: mdio {
-			compatible = "snps,dwmac-mdio";
-			#address-cells = <0x1>;
-			#size-cells = <0x0>;
-		};
-
-		stmmac_axi_setup: stmmac-axi-config {
-			snps,wr_osr_lmt = <4>;
-			snps,rd_osr_lmt = <8>;
-			snps,blen = <0 0 0 0 16 8 4>;
-		};
-
-		mtl_rx_setup: rx-queues-config {
-			snps,rx-queues-to-use = <1>;
-			queue0 {};
-		};
-
-		mtl_tx_setup: tx-queues-config {
-			snps,tx-queues-to-use = <1>;
-			queue0 {};
-		};
-	};
-
-	emmc: mmc@ffc50000 {
-		compatible = "rockchip,rv1126-dw-mshc", "rockchip,rk3288-dw-mshc";
-		reg = <0xffc50000 0x4000>;
-		interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>;
-		clocks = <&cru HCLK_EMMC>, <&cru CLK_EMMC>,
-			 <&cru SCLK_EMMC_DRV>, <&cru SCLK_EMMC_SAMPLE>;
-		clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
-		fifo-depth = <0x100>;
-		max-frequency = <200000000>;
-		power-domains = <&power RV1126_PD_NVM>;
-		status = "disabled";
-	};
-
-	sdmmc: mmc@ffc60000 {
-		compatible = "rockchip,rv1126-dw-mshc", "rockchip,rk3288-dw-mshc";
-		reg = <0xffc60000 0x4000>;
-		interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>;
-		clocks = <&cru HCLK_SDMMC>, <&cru CLK_SDMMC>,
-			 <&cru SCLK_SDMMC_DRV>, <&cru SCLK_SDMMC_SAMPLE>;
-		clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
-		fifo-depth = <0x100>;
-		max-frequency = <200000000>;
-		status = "disabled";
-	};
-
-	sdio: mmc@ffc70000 {
-		compatible = "rockchip,rv1126-dw-mshc", "rockchip,rk3288-dw-mshc";
-		reg = <0xffc70000 0x4000>;
-		interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>;
-		clocks = <&cru HCLK_SDIO>, <&cru CLK_SDIO>,
-			 <&cru SCLK_SDIO_DRV>, <&cru SCLK_SDIO_SAMPLE>;
-		clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
-		fifo-depth = <0x100>;
-		max-frequency = <200000000>;
-		power-domains = <&power RV1126_PD_SDIO>;
-		status = "disabled";
-	};
-
-	sfc: spi@ffc90000  {
-		compatible = "rockchip,sfc";
-		reg = <0xffc90000 0x4000>;
-		interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>;
-		assigned-clocks = <&cru SCLK_SFC>;
-		assigned-clock-rates = <80000000>;
-		clock-names = "clk_sfc", "hclk_sfc";
-		clocks = <&cru SCLK_SFC>, <&cru HCLK_SFC>;
-		power-domains = <&power RV1126_PD_NVM>;
-		status = "disabled";
-	};
-
-	pinctrl: pinctrl {
-		compatible = "rockchip,rv1126-pinctrl";
-		rockchip,grf = <&grf>;
-		rockchip,pmu = <&pmugrf>;
-		#address-cells = <1>;
-		#size-cells = <1>;
-		ranges;
-
-		gpio0: gpio@ff460000 {
-			compatible = "rockchip,gpio-bank";
-			reg = <0xff460000 0x100>;
-			interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
-			clocks = <&pmucru PCLK_GPIO0>, <&pmucru DBCLK_GPIO0>;
-			gpio-controller;
-			#gpio-cells = <2>;
-			interrupt-controller;
-			#interrupt-cells = <2>;
-		};
-
-		gpio1: gpio@ff620000 {
-			compatible = "rockchip,gpio-bank";
-			reg = <0xff620000 0x100>;
-			interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
-			clocks = <&cru PCLK_GPIO1>, <&cru DBCLK_GPIO1>;
-			gpio-controller;
-			#gpio-cells = <2>;
-			interrupt-controller;
-			#interrupt-cells = <2>;
-		};
-
-		gpio2: gpio@ff630000 {
-			compatible = "rockchip,gpio-bank";
-			reg = <0xff630000 0x100>;
-			interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
-			clocks = <&cru PCLK_GPIO2>, <&cru DBCLK_GPIO2>;
-			gpio-controller;
-			#gpio-cells = <2>;
-			interrupt-controller;
-			#interrupt-cells = <2>;
-		};
-
-		gpio3: gpio@ff640000 {
-			compatible = "rockchip,gpio-bank";
-			reg = <0xff640000 0x100>;
-			interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
-			clocks = <&cru PCLK_GPIO3>, <&cru DBCLK_GPIO3>;
-			gpio-controller;
-			#gpio-cells = <2>;
-			interrupt-controller;
-			#interrupt-cells = <2>;
-		};
-
-		gpio4: gpio@ff650000 {
-			compatible = "rockchip,gpio-bank";
-			reg = <0xff650000 0x100>;
-			interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
-			clocks = <&cru PCLK_GPIO4>, <&cru DBCLK_GPIO4>;
-			gpio-controller;
-			#gpio-cells = <2>;
-			interrupt-controller;
-			#interrupt-cells = <2>;
-		};
-	};
-};
-
-#include "rv1126-pinctrl.dtsi"
diff --git a/arch/arm/dts/salvator-common.dtsi b/arch/arm/dts/salvator-common.dtsi
deleted file mode 100644
index 4a3d503..0000000
--- a/arch/arm/dts/salvator-common.dtsi
+++ /dev/null
@@ -1,1104 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0
-/*
- * Device Tree Source for common parts of Salvator-X board variants
- *
- * Copyright (C) 2015-2016 Renesas Electronics Corp.
- */
-
-/*
- * SSI-AK4613
- *
- * This command is required when Playback/Capture
- *
- *	amixer set "DVC Out" 100%
- *	amixer set "DVC In" 100%
- *
- * You can use Mute
- *
- *	amixer set "DVC Out Mute" on
- *	amixer set "DVC In Mute" on
- *
- * You can use Volume Ramp
- *
- *	amixer set "DVC Out Ramp Up Rate"   "0.125 dB/64 steps"
- *	amixer set "DVC Out Ramp Down Rate" "0.125 dB/512 steps"
- *	amixer set "DVC Out Ramp" on
- *	aplay xxx.wav &
- *	amixer set "DVC Out"  80%  // Volume Down
- *	amixer set "DVC Out" 100%  // Volume Up
- */
-
-#include <dt-bindings/gpio/gpio.h>
-#include <dt-bindings/input/input.h>
-
-/ {
-	aliases {
-		i2c0 = &i2c0;
-		i2c1 = &i2c1;
-		i2c2 = &i2c2;
-		i2c3 = &i2c3;
-		i2c4 = &i2c4;
-		i2c5 = &i2c5;
-		i2c6 = &i2c6;
-		i2c7 = &i2c_dvfs;
-		serial0 = &scif2;
-		serial1 = &hscif1;
-		ethernet0 = &avb;
-		mmc0 = &sdhi2;
-		mmc1 = &sdhi0;
-		mmc2 = &sdhi3;
-	};
-
-	chosen {
-		bootargs = "ignore_loglevel rw root=/dev/nfs ip=on";
-		stdout-path = "serial0:115200n8";
-	};
-
-	audio_clkout: audio-clkout {
-		/*
-		 * This is same as <&rcar_sound 0>
-		 * but needed to avoid cs2000/rcar_sound probe dead-lock
-		 */
-		compatible = "fixed-clock";
-		#clock-cells = <0>;
-		clock-frequency = <12288000>;
-	};
-
-	backlight: backlight {
-		compatible = "pwm-backlight";
-		pwms = <&pwm1 0 50000>;
-
-		brightness-levels = <256 128 64 16 8 4 0>;
-		default-brightness-level = <6>;
-
-		power-supply = <&reg_12v>;
-		enable-gpios = <&gpio6 7 GPIO_ACTIVE_HIGH>;
-	};
-
-	cvbs-in {
-		compatible = "composite-video-connector";
-		label = "CVBS IN";
-
-		port {
-			cvbs_con: endpoint {
-				remote-endpoint = <&adv7482_ain7>;
-			};
-		};
-	};
-
-	hdmi-in {
-		compatible = "hdmi-connector";
-		label = "HDMI IN";
-		type = "a";
-
-		port {
-			hdmi_in_con: endpoint {
-				remote-endpoint = <&adv7482_hdmi>;
-			};
-		};
-	};
-
-	hdmi0-out {
-		compatible = "hdmi-connector";
-		label = "HDMI0 OUT";
-		type = "a";
-
-		port {
-			hdmi0_con: endpoint {
-				remote-endpoint = <&rcar_dw_hdmi0_out>;
-			};
-		};
-	};
-
-	hdmi1-out {
-		compatible = "hdmi-connector";
-		label = "HDMI1 OUT";
-		type = "a";
-
-		port {
-			hdmi1_con: endpoint {
-			};
-		};
-	};
-
-	keys {
-		compatible = "gpio-keys";
-
-		pinctrl-0 = <&keys_pins>;
-		pinctrl-names = "default";
-
-		key-1 {
-			gpios = <&gpio5 17 GPIO_ACTIVE_LOW>;
-			linux,code = <KEY_1>;
-			label = "SW4-1";
-			wakeup-source;
-			debounce-interval = <20>;
-		};
-		key-2 {
-			gpios = <&gpio5 20 GPIO_ACTIVE_LOW>;
-			linux,code = <KEY_2>;
-			label = "SW4-2";
-			wakeup-source;
-			debounce-interval = <20>;
-		};
-		key-3 {
-			gpios = <&gpio5 22 GPIO_ACTIVE_LOW>;
-			linux,code = <KEY_3>;
-			label = "SW4-3";
-			wakeup-source;
-			debounce-interval = <20>;
-		};
-		key-4 {
-			gpios = <&gpio5 23 GPIO_ACTIVE_LOW>;
-			linux,code = <KEY_4>;
-			label = "SW4-4";
-			wakeup-source;
-			debounce-interval = <20>;
-		};
-		key-a {
-			gpios = <&gpio6 11 GPIO_ACTIVE_LOW>;
-			linux,code = <KEY_A>;
-			label = "TSW0";
-			wakeup-source;
-			debounce-interval = <20>;
-		};
-		key-b {
-			gpios = <&gpio6 12 GPIO_ACTIVE_LOW>;
-			linux,code = <KEY_B>;
-			label = "TSW1";
-			wakeup-source;
-			debounce-interval = <20>;
-		};
-		key-c {
-			gpios = <&gpio6 13 GPIO_ACTIVE_LOW>;
-			linux,code = <KEY_C>;
-			label = "TSW2";
-			wakeup-source;
-			debounce-interval = <20>;
-		};
-	};
-
-	reg_1p8v: regulator-1p8v {
-		compatible = "regulator-fixed";
-		regulator-name = "fixed-1.8V";
-		regulator-min-microvolt = <1800000>;
-		regulator-max-microvolt = <1800000>;
-		regulator-boot-on;
-		regulator-always-on;
-	};
-
-	reg_3p3v: regulator-3p3v {
-		compatible = "regulator-fixed";
-		regulator-name = "fixed-3.3V";
-		regulator-min-microvolt = <3300000>;
-		regulator-max-microvolt = <3300000>;
-		regulator-boot-on;
-		regulator-always-on;
-	};
-
-	reg_12v: regulator-12v {
-		compatible = "regulator-fixed";
-		regulator-name = "fixed-12V";
-		regulator-min-microvolt = <12000000>;
-		regulator-max-microvolt = <12000000>;
-		regulator-boot-on;
-		regulator-always-on;
-	};
-
-	sound_card: sound {
-		compatible = "audio-graph-card";
-
-		label = "rcar-sound";
-
-		dais = <&rsnd_port0	/* ak4613 */
-			&rsnd_port1	/* HDMI0  */
-#ifdef SOC_HAS_HDMI1
-			&rsnd_port2	/* HDMI1  */
-#endif
-			>;
-	};
-
-	vbus0_usb2: regulator-vbus0-usb2 {
-		compatible = "regulator-fixed";
-
-		regulator-name = "USB20_VBUS0";
-		regulator-min-microvolt = <5000000>;
-		regulator-max-microvolt = <5000000>;
-
-		gpio = <&gpio6 16 GPIO_ACTIVE_HIGH>;
-		enable-active-high;
-	};
-
-	vcc_sdhi0: regulator-vcc-sdhi0 {
-		compatible = "regulator-fixed";
-
-		regulator-name = "SDHI0 Vcc";
-		regulator-min-microvolt = <3300000>;
-		regulator-max-microvolt = <3300000>;
-
-		gpio = <&gpio5 2 GPIO_ACTIVE_HIGH>;
-		enable-active-high;
-	};
-
-	vccq_sdhi0: regulator-vccq-sdhi0 {
-		compatible = "regulator-gpio";
-
-		regulator-name = "SDHI0 VccQ";
-		regulator-min-microvolt = <1800000>;
-		regulator-max-microvolt = <3300000>;
-
-		gpios = <&gpio5 1 GPIO_ACTIVE_HIGH>;
-		gpios-states = <1>;
-		states = <3300000 1>, <1800000 0>;
-	};
-
-	vcc_sdhi3: regulator-vcc-sdhi3 {
-		compatible = "regulator-fixed";
-
-		regulator-name = "SDHI3 Vcc";
-		regulator-min-microvolt = <3300000>;
-		regulator-max-microvolt = <3300000>;
-
-		gpio = <&gpio3 15 GPIO_ACTIVE_HIGH>;
-		enable-active-high;
-	};
-
-	vccq_sdhi3: regulator-vccq-sdhi3 {
-		compatible = "regulator-gpio";
-
-		regulator-name = "SDHI3 VccQ";
-		regulator-min-microvolt = <1800000>;
-		regulator-max-microvolt = <3300000>;
-
-		gpios = <&gpio3 14 GPIO_ACTIVE_HIGH>;
-		gpios-states = <1>;
-		states = <3300000 1>, <1800000 0>;
-	};
-
-	vga {
-		compatible = "vga-connector";
-
-		port {
-			vga_in: endpoint {
-				remote-endpoint = <&adv7123_out>;
-			};
-		};
-	};
-
-	vga-encoder {
-		compatible = "adi,adv7123";
-
-		ports {
-			#address-cells = <1>;
-			#size-cells = <0>;
-
-			port@0 {
-				reg = <0>;
-				adv7123_in: endpoint {
-					remote-endpoint = <&du_out_rgb>;
-				};
-			};
-			port@1 {
-				reg = <1>;
-				adv7123_out: endpoint {
-					remote-endpoint = <&vga_in>;
-				};
-			};
-		};
-	};
-
-	x12_clk: x12 {
-		compatible = "fixed-clock";
-		#clock-cells = <0>;
-		clock-frequency = <24576000>;
-	};
-
-	/* External DU dot clocks */
-	x21_clk: x21-clock {
-		compatible = "fixed-clock";
-		#clock-cells = <0>;
-		clock-frequency = <33000000>;
-	};
-
-	x22_clk: x22-clock {
-		compatible = "fixed-clock";
-		#clock-cells = <0>;
-		clock-frequency = <33000000>;
-	};
-
-	x23_clk: x23-clock {
-		compatible = "fixed-clock";
-		#clock-cells = <0>;
-		clock-frequency = <25000000>;
-	};
-};
-
-&a57_0 {
-	cpu-supply = <&dvfs>;
-};
-
-&audio_clk_a {
-	clock-frequency = <22579200>;
-};
-
-&avb {
-	pinctrl-0 = <&avb_pins>;
-	pinctrl-names = "default";
-	phy-handle = <&phy0>;
-	tx-internal-delay-ps = <2000>;
-	status = "okay";
-
-	phy0: ethernet-phy@0 {
-		compatible = "ethernet-phy-id0022.1622",
-			     "ethernet-phy-ieee802.3-c22";
-		rxc-skew-ps = <1500>;
-		reg = <0>;
-		interrupt-parent = <&gpio2>;
-		interrupts = <11 IRQ_TYPE_LEVEL_LOW>;
-		reset-gpios = <&gpio2 10 GPIO_ACTIVE_LOW>;
-	};
-};
-
-&csi20 {
-	status = "okay";
-
-	ports {
-		port@0 {
-			csi20_in: endpoint {
-				clock-lanes = <0>;
-				data-lanes = <1>;
-				remote-endpoint = <&adv7482_txb>;
-			};
-		};
-	};
-};
-
-&csi40 {
-	status = "okay";
-
-	ports {
-		port@0 {
-			csi40_in: endpoint {
-				clock-lanes = <0>;
-				data-lanes = <1 2 3 4>;
-				remote-endpoint = <&adv7482_txa>;
-			};
-		};
-	};
-};
-
-&du {
-	pinctrl-0 = <&du_pins>;
-	pinctrl-names = "default";
-	status = "okay";
-
-	ports {
-		port@0 {
-			du_out_rgb: endpoint {
-				remote-endpoint = <&adv7123_in>;
-			};
-		};
-	};
-};
-
-&ehci0 {
-	dr_mode = "otg";
-	status = "okay";
-};
-
-&ehci1 {
-	status = "okay";
-};
-
-&extalr_clk {
-	clock-frequency = <32768>;
-};
-
-&hdmi0 {
-	status = "okay";
-
-	ports {
-		port@1 {
-			reg = <1>;
-			rcar_dw_hdmi0_out: endpoint {
-				remote-endpoint = <&hdmi0_con>;
-			};
-		};
-		port@2 {
-			reg = <2>;
-			dw_hdmi0_snd_in: endpoint {
-				remote-endpoint = <&rsnd_endpoint1>;
-			};
-		};
-	};
-};
-
-#ifdef SOC_HAS_HDMI1
-&hdmi1 {
-	status = "okay";
-
-	ports {
-		port@1 {
-			reg = <1>;
-			rcar_dw_hdmi1_out: endpoint {
-				remote-endpoint = <&hdmi1_con>;
-			};
-		};
-		port@2 {
-			reg = <2>;
-			dw_hdmi1_snd_in: endpoint {
-				remote-endpoint = <&rsnd_endpoint2>;
-			};
-		};
-	};
-};
-
-&hdmi1_con {
-	remote-endpoint = <&rcar_dw_hdmi1_out>;
-};
-#endif /* SOC_HAS_HDMI1 */
-
-&hscif1 {
-	pinctrl-0 = <&hscif1_pins>;
-	pinctrl-names = "default";
-
-	uart-has-rtscts;
-	/* Please only enable hscif1 or scif1 */
-	status = "okay";
-};
-
-&hsusb {
-	dr_mode = "otg";
-	status = "okay";
-};
-
-&i2c2 {
-	pinctrl-0 = <&i2c2_pins>;
-	pinctrl-names = "default";
-
-	status = "okay";
-
-	clock-frequency = <100000>;
-
-	ak4613: codec@10 {
-		compatible = "asahi-kasei,ak4613";
-		#sound-dai-cells = <0>;
-		reg = <0x10>;
-		clocks = <&rcar_sound 3>;
-
-		asahi-kasei,in1-single-end;
-		asahi-kasei,in2-single-end;
-		asahi-kasei,out1-single-end;
-		asahi-kasei,out2-single-end;
-		asahi-kasei,out3-single-end;
-		asahi-kasei,out4-single-end;
-		asahi-kasei,out5-single-end;
-		asahi-kasei,out6-single-end;
-
-		port {
-			ak4613_endpoint: endpoint {
-				remote-endpoint = <&rsnd_endpoint0>;
-			};
-		};
-	};
-
-	cs2000: clk_multiplier@4f {
-		#clock-cells = <0>;
-		compatible = "cirrus,cs2000-cp";
-		reg = <0x4f>;
-		clocks = <&audio_clkout>, <&x12_clk>;
-		clock-names = "clk_in", "ref_clk";
-
-		assigned-clocks = <&cs2000>;
-		assigned-clock-rates = <24576000>; /* 1/1 divide */
-	};
-};
-
-&i2c4 {
-	status = "okay";
-
-	pca9654: gpio@20 {
-		compatible = "onnn,pca9654";
-		reg = <0x20>;
-		gpio-controller;
-		#gpio-cells = <2>;
-	};
-
-	video-receiver@70 {
-		compatible = "adi,adv7482";
-		reg = <0x70 0x71 0x72 0x73 0x74 0x75
-		       0x60 0x61 0x62 0x63 0x64 0x65>;
-		reg-names = "main", "dpll", "cp", "hdmi", "edid", "repeater",
-			    "infoframe", "cbus", "cec", "sdp", "txa", "txb" ;
-
-		interrupt-parent = <&gpio6>;
-		interrupt-names = "intrq1", "intrq2";
-		interrupts = <30 IRQ_TYPE_LEVEL_LOW>,
-			     <31 IRQ_TYPE_LEVEL_LOW>;
-
-		ports {
-			#address-cells = <1>;
-			#size-cells = <0>;
-
-			port@7 {
-				reg = <7>;
-
-				adv7482_ain7: endpoint {
-					remote-endpoint = <&cvbs_con>;
-				};
-			};
-
-			port@8 {
-				reg = <8>;
-
-				adv7482_hdmi: endpoint {
-					remote-endpoint = <&hdmi_in_con>;
-				};
-			};
-
-			port@a {
-				reg = <10>;
-
-				adv7482_txa: endpoint {
-					clock-lanes = <0>;
-					data-lanes = <1 2 3 4>;
-					remote-endpoint = <&csi40_in>;
-				};
-			};
-
-			port@b {
-				reg = <11>;
-
-				adv7482_txb: endpoint {
-					clock-lanes = <0>;
-					data-lanes = <1>;
-					remote-endpoint = <&csi20_in>;
-				};
-			};
-		};
-	};
-
-	csa_vdd: adc@7c {
-		compatible = "maxim,max9611";
-		reg = <0x7c>;
-
-		shunt-resistor-micro-ohms = <5000>;
-	};
-
-	csa_dvfs: adc@7f {
-		compatible = "maxim,max9611";
-		reg = <0x7f>;
-
-		shunt-resistor-micro-ohms = <5000>;
-	};
-};
-
-&i2c_dvfs {
-	status = "okay";
-
-	clock-frequency = <400000>;
-
-	pmic: pmic@30 {
-		pinctrl-0 = <&irq0_pins>;
-		pinctrl-names = "default";
-
-		compatible = "rohm,bd9571mwv";
-		reg = <0x30>;
-		interrupt-parent = <&intc_ex>;
-		interrupts = <0 IRQ_TYPE_LEVEL_LOW>;
-		interrupt-controller;
-		#interrupt-cells = <2>;
-		gpio-controller;
-		#gpio-cells = <2>;
-		rohm,ddr-backup-power = <0xf>;
-		rohm,rstbmode-level;
-
-		regulators {
-			dvfs: dvfs {
-				regulator-name = "dvfs";
-				regulator-min-microvolt = <750000>;
-				regulator-max-microvolt = <1030000>;
-				regulator-boot-on;
-				regulator-always-on;
-			};
-		};
-	};
-
-	eeprom@50 {
-		compatible = "rohm,br24t01", "atmel,24c01";
-		reg = <0x50>;
-		pagesize = <8>;
-	};
-};
-
-&ohci0 {
-	dr_mode = "otg";
-	status = "okay";
-};
-
-&ohci1 {
-	status = "okay";
-};
-
-&pcie_bus_clk {
-	clock-frequency = <100000000>;
-};
-
-&pciec0 {
-	status = "okay";
-};
-
-&pciec1 {
-	status = "okay";
-};
-
-&pfc {
-	pinctrl-0 = <&scif_clk_pins>;
-	pinctrl-names = "default";
-
-	avb_pins: avb {
-		mux {
-			groups = "avb_link", "avb_mdio", "avb_mii";
-			function = "avb";
-		};
-
-		pins_mdio {
-			groups = "avb_mdio";
-			drive-strength = <24>;
-		};
-
-		pins_mii_tx {
-			pins = "PIN_AVB_TX_CTL", "PIN_AVB_TXC", "PIN_AVB_TD0",
-			       "PIN_AVB_TD1", "PIN_AVB_TD2", "PIN_AVB_TD3";
-			drive-strength = <12>;
-		};
-	};
-
-	du_pins: du {
-		groups = "du_rgb888", "du_sync", "du_oddf", "du_clk_out_0";
-		function = "du";
-	};
-
-	hscif1_pins: hscif1 {
-		groups = "hscif1_data_a", "hscif1_ctrl_a";
-		function = "hscif1";
-	};
-
-	i2c2_pins: i2c2 {
-		groups = "i2c2_a";
-		function = "i2c2";
-	};
-
-	irq0_pins: irq0 {
-		groups = "intc_ex_irq0";
-		function = "intc_ex";
-	};
-
-	keys_pins: keys {
-		pins = "GP_5_17", "GP_5_20", "GP_5_22";
-		bias-pull-up;
-	};
-
-	pwm1_pins: pwm1 {
-		groups = "pwm1_a";
-		function = "pwm1";
-	};
-
-	scif1_pins: scif1 {
-		groups = "scif1_data_a", "scif1_ctrl";
-		function = "scif1";
-	};
-
-	scif2_pins: scif2 {
-		groups = "scif2_data_a";
-		function = "scif2";
-	};
-
-	scif_clk_pins: scif_clk {
-		groups = "scif_clk_a";
-		function = "scif_clk";
-	};
-
-	sdhi0_pins: sd0 {
-		groups = "sdhi0_data4", "sdhi0_ctrl";
-		function = "sdhi0";
-		power-source = <3300>;
-	};
-
-	sdhi0_pins_uhs: sd0_uhs {
-		groups = "sdhi0_data4", "sdhi0_ctrl";
-		function = "sdhi0";
-		power-source = <1800>;
-	};
-
-	sdhi2_pins: sd2 {
-		groups = "sdhi2_data8", "sdhi2_ctrl", "sdhi2_ds";
-		function = "sdhi2";
-		power-source = <1800>;
-	};
-
-	sdhi3_pins: sd3 {
-		groups = "sdhi3_data4", "sdhi3_ctrl";
-		function = "sdhi3";
-		power-source = <3300>;
-	};
-
-	sdhi3_pins_uhs: sd3_uhs {
-		groups = "sdhi3_data4", "sdhi3_ctrl";
-		function = "sdhi3";
-		power-source = <1800>;
-	};
-
-	sound_pins: sound {
-		groups = "ssi01239_ctrl", "ssi0_data", "ssi1_data_a";
-		function = "ssi";
-	};
-
-	sound_clk_pins: sound_clk {
-		groups = "audio_clk_a_a", "audio_clk_b_a", "audio_clk_c_a",
-			 "audio_clkout_a", "audio_clkout3_a";
-		function = "audio_clk";
-	};
-
-	usb0_pins: usb0 {
-		groups = "usb0";
-		function = "usb0";
-	};
-
-	usb1_pins: usb1 {
-		mux {
-			groups = "usb1";
-			function = "usb1";
-		};
-
-		ovc {
-			pins = "GP_6_27";
-			bias-pull-up;
-		};
-
-		pwen {
-			pins = "GP_6_26";
-			bias-pull-down;
-		};
-	};
-
-	usb30_pins: usb30 {
-		groups = "usb30";
-		function = "usb30";
-	};
-};
-
-&pwm1 {
-	pinctrl-0 = <&pwm1_pins>;
-	pinctrl-names = "default";
-
-	status = "okay";
-};
-
-&rcar_sound {
-	pinctrl-0 = <&sound_pins>, <&sound_clk_pins>;
-	pinctrl-names = "default";
-
-	/* audio_clkout0/1/2/3 */
-	#clock-cells = <1>;
-	clock-frequency = <12288000 11289600>;
-
-	status = "okay";
-
-	/* update <audio_clk_b> to <cs2000> */
-	clocks = <&cpg CPG_MOD 1005>,
-		 <&cpg CPG_MOD 1006>, <&cpg CPG_MOD 1007>,
-		 <&cpg CPG_MOD 1008>, <&cpg CPG_MOD 1009>,
-		 <&cpg CPG_MOD 1010>, <&cpg CPG_MOD 1011>,
-		 <&cpg CPG_MOD 1012>, <&cpg CPG_MOD 1013>,
-		 <&cpg CPG_MOD 1014>, <&cpg CPG_MOD 1015>,
-		 <&cpg CPG_MOD 1022>, <&cpg CPG_MOD 1023>,
-		 <&cpg CPG_MOD 1024>, <&cpg CPG_MOD 1025>,
-		 <&cpg CPG_MOD 1026>, <&cpg CPG_MOD 1027>,
-		 <&cpg CPG_MOD 1028>, <&cpg CPG_MOD 1029>,
-		 <&cpg CPG_MOD 1030>, <&cpg CPG_MOD 1031>,
-		 <&cpg CPG_MOD 1020>, <&cpg CPG_MOD 1021>,
-		 <&cpg CPG_MOD 1020>, <&cpg CPG_MOD 1021>,
-		 <&cpg CPG_MOD 1019>, <&cpg CPG_MOD 1018>,
-		 <&audio_clk_a>, <&cs2000>,
-		 <&audio_clk_c>,
-		 <&cpg CPG_CORE CPG_AUDIO_CLK_I>;
-
-	ports {
-		#address-cells = <1>;
-		#size-cells = <0>;
-		rsnd_port0: port@0 {
-			reg = <0>;
-			rsnd_endpoint0: endpoint {
-				remote-endpoint = <&ak4613_endpoint>;
-
-				dai-format = "left_j";
-				bitclock-master = <&rsnd_endpoint0>;
-				frame-master = <&rsnd_endpoint0>;
-
-				playback = <&ssi0>, <&src0>, <&dvc0>;
-				capture = <&ssi1>, <&src1>, <&dvc1>;
-			};
-		};
-
-		rsnd_port1: port@1 {
-			reg = <1>;
-			rsnd_endpoint1: endpoint {
-				remote-endpoint = <&dw_hdmi0_snd_in>;
-
-				dai-format = "i2s";
-				bitclock-master = <&rsnd_endpoint1>;
-				frame-master = <&rsnd_endpoint1>;
-
-				playback = <&ssi2>;
-			};
-		};
-
-#ifdef SOC_HAS_HDMI1
-		rsnd_port2: port@2 {
-			reg = <2>;
-			rsnd_endpoint2: endpoint {
-				remote-endpoint = <&dw_hdmi1_snd_in>;
-
-				dai-format = "i2s";
-				bitclock-master = <&rsnd_endpoint2>;
-				frame-master = <&rsnd_endpoint2>;
-
-				playback = <&ssi3>;
-			};
-		};
-#endif /* SOC_HAS_HDMI1 */
-	};
-};
-
-&rpc {
-	/* Left disabled.  To be enabled by firmware when unlocked. */
-
-	flash@0 {
-		compatible = "cypress,hyperflash", "cfi-flash";
-		reg = <0>;
-
-		partitions {
-			compatible = "fixed-partitions";
-			#address-cells = <1>;
-			#size-cells = <1>;
-
-			bootparam@0 {
-				reg = <0x00000000 0x040000>;
-				read-only;
-			};
-			bl2@40000 {
-				reg = <0x00040000 0x140000>;
-				read-only;
-			};
-			cert_header_sa6@180000 {
-				reg = <0x00180000 0x040000>;
-				read-only;
-			};
-			bl31@1c0000 {
-				reg = <0x001c0000 0x040000>;
-				read-only;
-			};
-			tee@200000 {
-				reg = <0x00200000 0x440000>;
-				read-only;
-			};
-			uboot@640000 {
-				reg = <0x00640000 0x100000>;
-				read-only;
-			};
-			dtb@740000 {
-				reg = <0x00740000 0x080000>;
-			};
-			kernel@7c0000 {
-				reg = <0x007c0000 0x1400000>;
-			};
-			user@1bc0000 {
-				reg = <0x01bc0000 0x2440000>;
-			};
-		};
-	};
-};
-
-&rwdt {
-	timeout-sec = <60>;
-	status = "okay";
-};
-
-#ifdef SOC_HAS_SATA
-&sata {
-	status = "okay";
-};
-#endif /* SOC_HAS_SATA */
-
-&scif1 {
-	pinctrl-0 = <&scif1_pins>;
-	pinctrl-names = "default";
-
-	uart-has-rtscts;
-	/* Please only enable hscif1 or scif1 */
-	/* status = "okay"; */
-};
-
-&scif2 {
-	pinctrl-0 = <&scif2_pins>;
-	pinctrl-names = "default";
-
-	status = "okay";
-};
-
-&scif_clk {
-	clock-frequency = <14745600>;
-};
-
-&sdhi0 {
-	pinctrl-0 = <&sdhi0_pins>;
-	pinctrl-1 = <&sdhi0_pins_uhs>;
-	pinctrl-names = "default", "state_uhs";
-
-	vmmc-supply = <&vcc_sdhi0>;
-	vqmmc-supply = <&vccq_sdhi0>;
-	cd-gpios = <&gpio3 12 GPIO_ACTIVE_LOW>;
-	wp-gpios = <&gpio3 13 GPIO_ACTIVE_HIGH>;
-	bus-width = <4>;
-	sd-uhs-sdr50;
-	sd-uhs-sdr104;
-	status = "okay";
-};
-
-&sdhi2 {
-	/* used for on-board 8bit eMMC */
-	pinctrl-0 = <&sdhi2_pins>;
-	pinctrl-1 = <&sdhi2_pins>;
-	pinctrl-names = "default", "state_uhs";
-
-	vmmc-supply = <&reg_3p3v>;
-	vqmmc-supply = <&reg_1p8v>;
-	bus-width = <8>;
-	mmc-hs200-1_8v;
-	mmc-hs400-1_8v;
-	no-sd;
-	no-sdio;
-	non-removable;
-	fixed-emmc-driver-type = <1>;
-	full-pwr-cycle-in-suspend;
-	status = "okay";
-};
-
-&sdhi3 {
-	pinctrl-0 = <&sdhi3_pins>;
-	pinctrl-1 = <&sdhi3_pins_uhs>;
-	pinctrl-names = "default", "state_uhs";
-
-	vmmc-supply = <&vcc_sdhi3>;
-	vqmmc-supply = <&vccq_sdhi3>;
-	cd-gpios = <&gpio4 15 GPIO_ACTIVE_LOW>;
-	wp-gpios = <&gpio4 16 GPIO_ACTIVE_HIGH>;
-	bus-width = <4>;
-	sd-uhs-sdr50;
-	sd-uhs-sdr104;
-	status = "okay";
-};
-
-&ssi1 {
-	shared-pin;
-};
-
-&usb_extal_clk {
-	clock-frequency = <50000000>;
-};
-
-&usb2_phy0 {
-	pinctrl-0 = <&usb0_pins>;
-	pinctrl-names = "default";
-
-	vbus-supply = <&vbus0_usb2>;
-	status = "okay";
-};
-
-&usb2_phy1 {
-	pinctrl-0 = <&usb1_pins>;
-	pinctrl-names = "default";
-
-	status = "okay";
-};
-
-&usb3_peri0 {
-	phys = <&usb3_phy0>;
-	phy-names = "usb";
-
-	companion = <&xhci0>;
-
-	status = "okay";
-};
-
-&usb3_phy0 {
-	status = "okay";
-};
-
-&usb3s0_clk {
-	clock-frequency = <100000000>;
-};
-
-&vin0 {
-	status = "okay";
-};
-
-&vin1 {
-	status = "okay";
-};
-
-&vin2 {
-	status = "okay";
-};
-
-&vin3 {
-	status = "okay";
-};
-
-&vin4 {
-	status = "okay";
-};
-
-&vin5 {
-	status = "okay";
-};
-
-&vin6 {
-	status = "okay";
-};
-
-&vin7 {
-	status = "okay";
-};
-
-&xhci0 {
-	pinctrl-0 = <&usb30_pins>;
-	pinctrl-names = "default";
-
-	status = "okay";
-};
-
-#ifdef SOC_HAS_USB2_CH2
-&ehci2 {
-	status = "okay";
-};
-
-&ohci2 {
-	status = "okay";
-};
-
-&pfc {
-	usb2_pins: usb2 {
-		groups = "usb2";
-		function = "usb2";
-	};
-};
-
-&usb2_phy2 {
-	pinctrl-0 = <&usb2_pins>;
-	pinctrl-names = "default";
-
-	status = "okay";
-};
-#endif /* SOC_HAS_USB2_CH2 */
diff --git a/arch/arm/dts/salvator-x.dtsi b/arch/arm/dts/salvator-x.dtsi
deleted file mode 100644
index ddee50e..0000000
--- a/arch/arm/dts/salvator-x.dtsi
+++ /dev/null
@@ -1,29 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0
-/*
- * Device Tree Source for the Salvator-X board
- *
- * Copyright (C) 2015-2016 Renesas Electronics Corp.
- */
-
-#include "salvator-common.dtsi"
-
-/ {
-	model = "Renesas Salvator-X board";
-	compatible = "renesas,salvator-x";
-};
-
-&extal_clk {
-	clock-frequency = <16666666>;
-};
-
-&i2c4 {
-	clock-frequency = <400000>;
-
-	versaclock5: clock-generator@6a {
-		compatible = "idt,5p49v5923";
-		reg = <0x6a>;
-		#clock-cells = <1>;
-		clocks = <&x23_clk>;
-		clock-names = "xin";
-	};
-};
diff --git a/arch/arm/dts/salvator-xs.dtsi b/arch/arm/dts/salvator-xs.dtsi
deleted file mode 100644
index 08b9256..0000000
--- a/arch/arm/dts/salvator-xs.dtsi
+++ /dev/null
@@ -1,85 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0
-/*
- * Device Tree Source for the Salvator-X 2nd version board
- *
- * Copyright (C) 2015-2017 Renesas Electronics Corp.
- */
-
-#include "salvator-common.dtsi"
-
-/ {
-	model = "Renesas Salvator-X 2nd version board";
-	compatible = "renesas,salvator-xs";
-};
-
-&extal_clk {
-	clock-frequency = <16640000>;
-};
-
-&i2c4 {
-	clock-frequency = <400000>;
-
-	versaclock6: clock-generator@6a {
-		compatible = "idt,5p49v6901";
-		reg = <0x6a>;
-		#clock-cells = <1>;
-		clocks = <&x23_clk>;
-		clock-names = "xin";
-	};
-};
-
-#ifdef SOC_HAS_SATA
-&pca9654 {
-	pcie-sata-switch-hog {
-		gpio-hog;
-		gpios = <7 GPIO_ACTIVE_HIGH>;
-		output-low; /* enable SATA by default */
-		line-name = "PCIE/SATA switch";
-	};
-};
-
-/* SW12-7 must be set 'Off' (MD12 set to 1) which is not the default! */
-#endif /* SOC_HAS_SATA */
-
-#ifdef SOC_HAS_USB2_CH3
-&ehci3 {
-	dr_mode = "otg";
-	status = "okay";
-};
-
-&hsusb3 {
-	dr_mode = "otg";
-	status = "okay";
-};
-
-&ohci3 {
-	dr_mode = "otg";
-	status = "okay";
-};
-
-&pfc {
-	/*
-	 * - On Salvator-X[S], GP6_3[01] are connected to ADV7482 as irq pins
-	 *   (when SW31 is the default setting on Salvator-XS).
-	 * - If SW31 is the default setting, you cannot use USB2.0 ch3 on
-	 *   r8a77951 with Salvator-XS.
-	 *   Hence the SW31 setting must be changed like 2) below.
-	 *   1) Default setting of SW31: ON-ON-OFF-OFF-OFF-OFF:
-	 *	- Connect GP6_3[01] to ADV7842.
-	 *   2) Changed setting of SW31: OFF-OFF-ON-ON-ON-ON:
-	 *	- Connect GP6_3[01] to BD082065 (USB2.0 ch3's host power).
-	 *	- Connect GP6_{04,21} to ADV7842.
-	 */
-	usb2_ch3_pins: usb2_ch3 {
-		groups = "usb2_ch3";
-		function = "usb2_ch3";
-	};
-};
-
-&usb2_phy3 {
-	pinctrl-0 = <&usb2_ch3_pins>;
-	pinctrl-names = "default";
-
-	status = "okay";
-};
-#endif /* SOC_HAS_USB2_CH3 */
diff --git a/arch/arm/dts/ulcb-audio-graph-card.dtsi b/arch/arm/dts/ulcb-audio-graph-card.dtsi
deleted file mode 100644
index 3be54df..0000000
--- a/arch/arm/dts/ulcb-audio-graph-card.dtsi
+++ /dev/null
@@ -1,85 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0
-/*
- * Device Tree for ULCB + Audio Graph Card
- *
- * Copyright (C) 2022 Renesas Electronics Corp.
- */
-
-/*
- *	(A) CPU0 <-----> ak4613
- *	(B) CPU1  -----> HDMI
- *
- *	(A) aplay   -D plughw:0,0 xxx.wav
- *	(B) aplay   -D plughw:0,1 xxx.wav
- *
- *	(A) arecord -D plughw:0,0 xxx.wav
- */
-
-/ {
-	sound_card: sound {
-		compatible = "audio-graph-card";
-		label = "rcar-sound";
-
-		dais = <&rsnd_port0 /* (A) CPU0 <-> ak4613 */
-			&rsnd_port1 /* (B) CPU1  -> HDMI   */
-		>;
-	};
-};
-
-&ak4613 {
-	#sound-dai-cells = <0>;
-
-	port {
-		/*
-		 * (A) CPU0 <-> ak4613
-		 */
-		ak4613_endpoint: endpoint {
-			remote-endpoint = <&rsnd_for_ak4613>;
-		};
-	};
-};
-
-&hdmi0 {
-	ports {
-		port@2 {
-			/*
-			 * (B) CPU1 -> HDMI
-			 */
-			dw_hdmi0_snd_in: endpoint {
-				remote-endpoint = <&rsnd_for_hdmi>;
-			};
-		};
-	};
-};
-
-&rcar_sound {
-	ports {
-		#address-cells = <1>;
-		#size-cells = <0>;
-		rsnd_port0: port@0 {
-			/*
-			 * (A) CPU0 <-> ak4613
-			 */
-			reg = <0>;
-			rsnd_for_ak4613: endpoint {
-				remote-endpoint = <&ak4613_endpoint>;
-				bitclock-master;
-				frame-master;
-				playback = <&ssi0>, <&src0>, <&dvc0>;
-				capture  = <&ssi1>, <&src1>, <&dvc1>;
-			};
-		};
-		rsnd_port1: port@1 {
-			/*
-			 * (B) CPU1 -> HDMI
-			 */
-			reg = <1>;
-			rsnd_for_hdmi: endpoint {
-				remote-endpoint = <&dw_hdmi0_snd_in>;
-				bitclock-master;
-				frame-master;
-				playback = <&ssi2>;
-			};
-		};
-	};
-};
diff --git a/arch/arm/dts/ulcb-audio-graph-card2.dtsi b/arch/arm/dts/ulcb-audio-graph-card2.dtsi
deleted file mode 100644
index 5ebec12..0000000
--- a/arch/arm/dts/ulcb-audio-graph-card2.dtsi
+++ /dev/null
@@ -1,26 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0
-/*
- * Device Tree for ULCB + Audio Graph Card2
- *
- * Copyright (C) 2022 Renesas Electronics Corp.
- */
-
-/*
- *	(A) CPU0 <----> ak4613
- *	(B) CPU1  ----> HDMI
- *
- *	(A) aplay   -D plughw:0,0 xxx.wav
- *	(B) aplay   -D plughw:0,1 xxx.wav
- *
- *	(A) arecord -D plughw:0,0 xxx.wav
- */
-#include "ulcb-audio-graph-card.dtsi"
-
-&sound_card {
-	compatible = "audio-graph-card2";
-
-	/delete-property/ dais;
-	links = <&rsnd_port0	/* (A) CPU0 <-> ak4613 */
-		 &rsnd_port1	/* (B) CPU1  -> HDMI   */
-		>;
-};
diff --git a/arch/arm/dts/ulcb.dtsi b/arch/arm/dts/ulcb.dtsi
deleted file mode 100644
index 0be2716..0000000
--- a/arch/arm/dts/ulcb.dtsi
+++ /dev/null
@@ -1,509 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0
-/*
- * Device Tree Source for the R-Car Gen3 ULCB board
- *
- * Copyright (C) 2016 Renesas Electronics Corp.
- * Copyright (C) 2016 Cogent Embedded, Inc.
- */
-
-#include <dt-bindings/gpio/gpio.h>
-#include <dt-bindings/input/input.h>
-
-/ {
-	model = "Renesas R-Car Gen3 ULCB board";
-
-	aliases {
-		i2c0 = &i2c0;
-		i2c1 = &i2c1;
-		i2c2 = &i2c2;
-		i2c3 = &i2c3;
-		i2c4 = &i2c4;
-		i2c5 = &i2c5;
-		i2c6 = &i2c6;
-		i2c7 = &i2c_dvfs;
-		serial0 = &scif2;
-		ethernet0 = &avb;
-		mmc0 = &sdhi2;
-		mmc1 = &sdhi0;
-	};
-
-	chosen {
-		bootargs = "ignore_loglevel rw root=/dev/nfs ip=on";
-		stdout-path = "serial0:115200n8";
-	};
-
-	audio_clkout: audio-clkout {
-		/*
-		 * This is same as <&rcar_sound 0>
-		 * but needed to avoid cs2000/rcar_sound probe dead-lock
-		 */
-		compatible = "fixed-clock";
-		#clock-cells = <0>;
-		clock-frequency = <12288000>;
-	};
-
-	hdmi0-out {
-		compatible = "hdmi-connector";
-		type = "a";
-
-		port {
-			hdmi0_con: endpoint {
-				remote-endpoint = <&rcar_dw_hdmi0_out>;
-			};
-		};
-	};
-
-	keyboard {
-		compatible = "gpio-keys";
-
-		key-1 {
-			linux,code = <KEY_1>;
-			label = "SW3";
-			wakeup-source;
-			debounce-interval = <20>;
-			gpios = <&gpio6 11 GPIO_ACTIVE_LOW>;
-		};
-	};
-
-	leds {
-		compatible = "gpio-leds";
-
-		led5 {
-			gpios = <&gpio6 12 GPIO_ACTIVE_HIGH>;
-		};
-		led6 {
-			gpios = <&gpio6 13 GPIO_ACTIVE_HIGH>;
-		};
-	};
-
-	reg_1p8v: regulator-1p8v {
-		compatible = "regulator-fixed";
-		regulator-name = "fixed-1.8V";
-		regulator-min-microvolt = <1800000>;
-		regulator-max-microvolt = <1800000>;
-		regulator-boot-on;
-		regulator-always-on;
-	};
-
-	reg_3p3v: regulator-3p3v {
-		compatible = "regulator-fixed";
-		regulator-name = "fixed-3.3V";
-		regulator-min-microvolt = <3300000>;
-		regulator-max-microvolt = <3300000>;
-		regulator-boot-on;
-		regulator-always-on;
-	};
-
-	vcc_sdhi0: regulator-vcc-sdhi0 {
-		compatible = "regulator-fixed";
-
-		regulator-name = "SDHI0 Vcc";
-		regulator-min-microvolt = <3300000>;
-		regulator-max-microvolt = <3300000>;
-
-		gpio = <&gpio5 2 GPIO_ACTIVE_HIGH>;
-		enable-active-high;
-	};
-
-	vccq_sdhi0: regulator-vccq-sdhi0 {
-		compatible = "regulator-gpio";
-
-		regulator-name = "SDHI0 VccQ";
-		regulator-min-microvolt = <1800000>;
-		regulator-max-microvolt = <3300000>;
-
-		gpios = <&gpio5 1 GPIO_ACTIVE_HIGH>;
-		gpios-states = <1>;
-		states = <3300000 1>, <1800000 0>;
-	};
-
-	x12_clk: x12 {
-		compatible = "fixed-clock";
-		#clock-cells = <0>;
-		clock-frequency = <24576000>;
-	};
-
-	x23_clk: x23-clock {
-		compatible = "fixed-clock";
-		#clock-cells = <0>;
-		clock-frequency = <25000000>;
-	};
-};
-
-&a57_0 {
-	cpu-supply = <&dvfs>;
-};
-
-&audio_clk_a {
-	clock-frequency = <22579200>;
-};
-
-&avb {
-	pinctrl-0 = <&avb_pins>;
-	pinctrl-names = "default";
-	phy-handle = <&phy0>;
-	tx-internal-delay-ps = <2000>;
-	status = "okay";
-
-	phy0: ethernet-phy@0 {
-		compatible = "ethernet-phy-id0022.1622",
-			     "ethernet-phy-ieee802.3-c22";
-		rxc-skew-ps = <1500>;
-		reg = <0>;
-		interrupt-parent = <&gpio2>;
-		interrupts = <11 IRQ_TYPE_LEVEL_LOW>;
-		reset-gpios = <&gpio2 10 GPIO_ACTIVE_LOW>;
-	};
-};
-
-&du {
-	status = "okay";
-};
-
-&ehci1 {
-	status = "okay";
-};
-
-&extal_clk {
-	clock-frequency = <16666666>;
-};
-
-&extalr_clk {
-	clock-frequency = <32768>;
-};
-
-&hdmi0 {
-	status = "okay";
-
-	ports {
-		port@1 {
-			reg = <1>;
-			rcar_dw_hdmi0_out: endpoint {
-				remote-endpoint = <&hdmi0_con>;
-			};
-		};
-		port@2 {
-			reg = <2>;
-		};
-	};
-};
-
-&i2c2 {
-	pinctrl-0 = <&i2c2_pins>;
-	pinctrl-names = "default";
-
-	status = "okay";
-
-	clock-frequency = <100000>;
-
-	ak4613: codec@10 {
-		compatible = "asahi-kasei,ak4613";
-		reg = <0x10>;
-		clocks = <&rcar_sound 3>;
-
-		asahi-kasei,in1-single-end;
-		asahi-kasei,in2-single-end;
-		asahi-kasei,out1-single-end;
-		asahi-kasei,out2-single-end;
-		asahi-kasei,out3-single-end;
-		asahi-kasei,out4-single-end;
-		asahi-kasei,out5-single-end;
-		asahi-kasei,out6-single-end;
-	};
-
-	cs2000: clk-multiplier@4f {
-		#clock-cells = <0>;
-		compatible = "cirrus,cs2000-cp";
-		reg = <0x4f>;
-		clocks = <&audio_clkout>, <&x12_clk>;
-		clock-names = "clk_in", "ref_clk";
-
-		assigned-clocks = <&cs2000>;
-		assigned-clock-rates = <24576000>; /* 1/1 divide */
-	};
-};
-
-&i2c4 {
-	status = "okay";
-
-	clock-frequency = <400000>;
-
-	versaclock5: clock-generator@6a {
-		compatible = "idt,5p49v5925";
-		reg = <0x6a>;
-		#clock-cells = <1>;
-		clocks = <&x23_clk>;
-		clock-names = "xin";
-	};
-};
-
-&i2c_dvfs {
-	status = "okay";
-
-	clock-frequency = <400000>;
-
-	pmic: pmic@30 {
-		pinctrl-0 = <&irq0_pins>;
-		pinctrl-names = "default";
-
-		compatible = "rohm,bd9571mwv";
-		reg = <0x30>;
-		interrupt-parent = <&intc_ex>;
-		interrupts = <0 IRQ_TYPE_LEVEL_LOW>;
-		interrupt-controller;
-		#interrupt-cells = <2>;
-		gpio-controller;
-		#gpio-cells = <2>;
-		rohm,ddr-backup-power = <0xf>;
-		rohm,rstbmode-pulse;
-
-		regulators {
-			dvfs: dvfs {
-				regulator-name = "dvfs";
-				regulator-min-microvolt = <750000>;
-				regulator-max-microvolt = <1030000>;
-				regulator-boot-on;
-				regulator-always-on;
-			};
-		};
-	};
-
-	eeprom@50 {
-		compatible = "rohm,br24t01", "atmel,24c01";
-		reg = <0x50>;
-		pagesize = <8>;
-	};
-};
-
-&ohci1 {
-	status = "okay";
-};
-
-&pfc {
-	pinctrl-0 = <&scif_clk_pins>;
-	pinctrl-names = "default";
-
-	avb_pins: avb {
-		mux {
-			groups = "avb_link", "avb_mdio", "avb_mii";
-			function = "avb";
-		};
-
-		pins_mdio {
-			groups = "avb_mdio";
-			drive-strength = <24>;
-		};
-
-		pins_mii_tx {
-			pins = "PIN_AVB_TX_CTL", "PIN_AVB_TXC", "PIN_AVB_TD0",
-			       "PIN_AVB_TD1", "PIN_AVB_TD2", "PIN_AVB_TD3";
-			drive-strength = <12>;
-		};
-	};
-
-	i2c2_pins: i2c2 {
-		groups = "i2c2_a";
-		function = "i2c2";
-	};
-
-	irq0_pins: irq0 {
-		groups = "intc_ex_irq0";
-		function = "intc_ex";
-	};
-
-	scif2_pins: scif2 {
-		groups = "scif2_data_a";
-		function = "scif2";
-	};
-
-	scif_clk_pins: scif_clk {
-		groups = "scif_clk_a";
-		function = "scif_clk";
-	};
-
-	sdhi0_pins: sd0 {
-		groups = "sdhi0_data4", "sdhi0_ctrl";
-		function = "sdhi0";
-		power-source = <3300>;
-	};
-
-	sdhi0_pins_uhs: sd0_uhs {
-		groups = "sdhi0_data4", "sdhi0_ctrl";
-		function = "sdhi0";
-		power-source = <1800>;
-	};
-
-	sdhi2_pins: sd2 {
-		groups = "sdhi2_data8", "sdhi2_ctrl", "sdhi2_ds";
-		function = "sdhi2";
-		power-source = <1800>;
-	};
-
-	sound_pins: sound {
-		groups = "ssi01239_ctrl", "ssi0_data", "ssi1_data_a";
-		function = "ssi";
-	};
-
-	sound_clk_pins: sound-clk {
-		groups = "audio_clk_a_a", "audio_clk_b_a", "audio_clk_c_a",
-			 "audio_clkout_a", "audio_clkout3_a";
-		function = "audio_clk";
-	};
-
-	usb1_pins: usb1 {
-		groups = "usb1";
-		function = "usb1";
-	};
-};
-
-&rcar_sound {
-	pinctrl-0 = <&sound_pins>, <&sound_clk_pins>;
-	pinctrl-names = "default";
-
-	/* audio_clkout0/1/2/3 */
-	#clock-cells = <1>;
-	clock-frequency = <12288000 11289600>;
-
-	status = "okay";
-
-	/* update <audio_clk_b> to <cs2000> */
-	clocks = <&cpg CPG_MOD 1005>,
-		 <&cpg CPG_MOD 1006>, <&cpg CPG_MOD 1007>,
-		 <&cpg CPG_MOD 1008>, <&cpg CPG_MOD 1009>,
-		 <&cpg CPG_MOD 1010>, <&cpg CPG_MOD 1011>,
-		 <&cpg CPG_MOD 1012>, <&cpg CPG_MOD 1013>,
-		 <&cpg CPG_MOD 1014>, <&cpg CPG_MOD 1015>,
-		 <&cpg CPG_MOD 1022>, <&cpg CPG_MOD 1023>,
-		 <&cpg CPG_MOD 1024>, <&cpg CPG_MOD 1025>,
-		 <&cpg CPG_MOD 1026>, <&cpg CPG_MOD 1027>,
-		 <&cpg CPG_MOD 1028>, <&cpg CPG_MOD 1029>,
-		 <&cpg CPG_MOD 1030>, <&cpg CPG_MOD 1031>,
-		 <&cpg CPG_MOD 1020>, <&cpg CPG_MOD 1021>,
-		 <&cpg CPG_MOD 1020>, <&cpg CPG_MOD 1021>,
-		 <&cpg CPG_MOD 1019>, <&cpg CPG_MOD 1018>,
-		 <&audio_clk_a>, <&cs2000>,
-		 <&audio_clk_c>,
-		 <&cpg CPG_CORE CPG_AUDIO_CLK_I>;
-};
-
-&rpc {
-	/* Left disabled.  To be enabled by firmware when unlocked. */
-
-	flash@0 {
-		compatible = "cypress,hyperflash", "cfi-flash";
-		reg = <0>;
-
-		partitions {
-			compatible = "fixed-partitions";
-			#address-cells = <1>;
-			#size-cells = <1>;
-
-			bootparam@0 {
-				reg = <0x00000000 0x040000>;
-				read-only;
-			};
-			bl2@40000 {
-				reg = <0x00040000 0x140000>;
-				read-only;
-			};
-			cert_header_sa6@180000 {
-				reg = <0x00180000 0x040000>;
-				read-only;
-			};
-			bl31@1c0000 {
-				reg = <0x001c0000 0x040000>;
-				read-only;
-			};
-			tee@200000 {
-				reg = <0x00200000 0x440000>;
-				read-only;
-			};
-			uboot@640000 {
-				reg = <0x00640000 0x100000>;
-				read-only;
-			};
-			dtb@740000 {
-				reg = <0x00740000 0x080000>;
-			};
-			kernel@7c0000 {
-				reg = <0x007c0000 0x1400000>;
-			};
-			user@1bc0000 {
-				reg = <0x01bc0000 0x2440000>;
-			};
-		};
-	};
-};
-
-&rwdt {
-	timeout-sec = <60>;
-	status = "okay";
-};
-
-&scif2 {
-	pinctrl-0 = <&scif2_pins>;
-	pinctrl-names = "default";
-
-	status = "okay";
-};
-
-&scif_clk {
-	clock-frequency = <14745600>;
-};
-
-&sdhi0 {
-	pinctrl-0 = <&sdhi0_pins>;
-	pinctrl-1 = <&sdhi0_pins_uhs>;
-	pinctrl-names = "default", "state_uhs";
-
-	vmmc-supply = <&vcc_sdhi0>;
-	vqmmc-supply = <&vccq_sdhi0>;
-	cd-gpios = <&gpio3 12 GPIO_ACTIVE_LOW>;
-	bus-width = <4>;
-	sd-uhs-sdr50;
-	sd-uhs-sdr104;
-	status = "okay";
-};
-
-&sdhi2 {
-	/* used for on-board 8bit eMMC */
-	pinctrl-0 = <&sdhi2_pins>;
-	pinctrl-1 = <&sdhi2_pins>;
-	pinctrl-names = "default", "state_uhs";
-
-	vmmc-supply = <&reg_3p3v>;
-	vqmmc-supply = <&reg_1p8v>;
-	bus-width = <8>;
-	mmc-hs200-1_8v;
-	mmc-hs400-1_8v;
-	no-sd;
-	no-sdio;
-	non-removable;
-	full-pwr-cycle-in-suspend;
-	status = "okay";
-};
-
-&ssi1 {
-	shared-pin;
-};
-
-&usb2_phy1 {
-	pinctrl-0 = <&usb1_pins>;
-	pinctrl-names = "default";
-
-	status = "okay";
-};
-
-
-/*
- * For sound-test.
- *
- * We can switch Audio Card for testing
- *
- * #include "ulcb-simple-audio-card.dtsi"
- * #include "ulcb-simple-audio-card-mix+split.dtsi"
- * #include "ulcb-audio-graph-card.dtsi"
- * #include "ulcb-audio-graph-card-mix+split.dtsi"
- * #include "ulcb-audio-graph-card2-mix+split.dtsi"
- */
-#include "ulcb-audio-graph-card2.dtsi"
diff --git a/arch/arm/include/asm/arch-rockchip/cru_rk3588.h b/arch/arm/include/asm/arch-rockchip/cru_rk3588.h
index a4507e5..a0e54d3 100644
--- a/arch/arm/include/asm/arch-rockchip/cru_rk3588.h
+++ b/arch/arm/include/asm/arch-rockchip/cru_rk3588.h
@@ -29,6 +29,7 @@
 	V0PLL,
 	AUPLL,
 	PPLL,
+	SPLL,
 	PLL_COUNT,
 };
 
@@ -150,6 +151,9 @@
 #define RK3588_DSU_CLKGATE_CON(x)	((x) * 0x4 + RK3588_DSU_CRU_BASE + 0x800)
 #define RK3588_DSU_SOFTRST_CON(x)	((x) * 0x4 + RK3588_DSU_CRU_BASE + 0xa00)
 
+#define RK3588_SBUSCRU_SPLL_CON(x)	((x) * 0x4 + 0x220)
+#define RK3588_SBUSCRU_MODE_CON0	0x280
+
 enum {
 	/* CRU_CLK_SEL8_CON */
 	ACLK_LOW_TOP_ROOT_SRC_SEL_SHIFT		= 14,
diff --git a/arch/arm/mach-exynos/Kconfig b/arch/arm/mach-exynos/Kconfig
index af00ee1..cad8bb0 100644
--- a/arch/arm/mach-exynos/Kconfig
+++ b/arch/arm/mach-exynos/Kconfig
@@ -249,6 +249,7 @@
 	select OF_CONTROL
 	select PINCTRL
 	select PINCTRL_EXYNOS850
+	imply OF_UPSTREAM
 
 endchoice
 endif
diff --git a/arch/arm/mach-exynos/mmu-arm64.c b/arch/arm/mach-exynos/mmu-arm64.c
index e2f3254..fdaacc70 100644
--- a/arch/arm/mach-exynos/mmu-arm64.c
+++ b/arch/arm/mach-exynos/mmu-arm64.c
@@ -100,6 +100,14 @@
 
 static struct mm_region exynos850_mem_map[] = {
 	{
+		/* iRAM */
+		.virt = 0x02000000UL,
+		.phys = 0x02000000UL,
+		.size = SZ_2M,
+		.attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRE) |
+			 PTE_BLOCK_NON_SHARE |
+			 PTE_BLOCK_PXN | PTE_BLOCK_UXN
+	}, {
 		/* Peripheral block */
 		.virt = 0x10000000UL,
 		.phys = 0x10000000UL,
diff --git a/arch/arm/mach-k3/am62px/Kconfig b/arch/arm/mach-k3/am62px/Kconfig
index 38a9e68..76ae86b 100644
--- a/arch/arm/mach-k3/am62px/Kconfig
+++ b/arch/arm/mach-k3/am62px/Kconfig
@@ -13,6 +13,7 @@
 	bool "TI K3 based AM62P5 EVM running on A53"
 	select ARM64
 	select BINMAN
+	select OF_SYSTEM_SETUP
 
 config TARGET_AM62P5_R5_EVM
 	bool "TI K3 based AM62P5 EVM running on R5"
diff --git a/arch/arm/mach-k3/am62px/Makefile b/arch/arm/mach-k3/am62px/Makefile
index 5902862..eed91a0 100644
--- a/arch/arm/mach-k3/am62px/Makefile
+++ b/arch/arm/mach-k3/am62px/Makefile
@@ -3,4 +3,5 @@
 # Copyright (C) 2024 Texas Instruments Incorporated - https://www.ti.com/
 #	Andrew Davis <afd@ti.com>
 
+obj-$(CONFIG_OF_SYSTEM_SETUP) += am62p5_fdt.o
 obj-$(CONFIG_SPL_BUILD) += am62p5_init.o
diff --git a/arch/arm/mach-k3/am62px/am62p5_fdt.c b/arch/arm/mach-k3/am62px/am62p5_fdt.c
new file mode 100644
index 0000000..29c832d
--- /dev/null
+++ b/arch/arm/mach-k3/am62px/am62p5_fdt.c
@@ -0,0 +1,16 @@
+// SPDX-License-Identifier: GPL-2.0-or-later
+/*
+ * Copyright (C) 2024 Texas Instruments Incorporated - https://www.ti.com/
+ */
+
+#include <asm/hardware.h>
+#include "../common_fdt.h"
+#include <fdt_support.h>
+
+int ft_system_setup(void *blob, struct bd_info *bd)
+{
+	fdt_fixup_reserved(blob, "tfa", CONFIG_K3_ATF_LOAD_ADDR, 0x80000);
+	fdt_fixup_reserved(blob, "optee", CONFIG_K3_OPTEE_LOAD_ADDR, 0x1800000);
+
+	return 0;
+}
diff --git a/arch/arm/mach-rockchip/Kconfig b/arch/arm/mach-rockchip/Kconfig
index ec3697f..661e7fd 100644
--- a/arch/arm/mach-rockchip/Kconfig
+++ b/arch/arm/mach-rockchip/Kconfig
@@ -427,6 +427,7 @@
 	imply SPL_ROCKCHIP_COMMON_BOARD
 	imply SPL_SERIAL
 	imply SPL_SYSCON
+	imply OF_UPSTREAM
 
 config ROCKCHIP_USB_UART
 	bool "Route uart output to usb pins"
diff --git a/arch/arm/mach-rockchip/px30/Kconfig b/arch/arm/mach-rockchip/px30/Kconfig
index 23f8f43..dcf9eb8 100644
--- a/arch/arm/mach-rockchip/px30/Kconfig
+++ b/arch/arm/mach-rockchip/px30/Kconfig
@@ -68,8 +68,11 @@
 config SYS_SOC
 	default "px30"
 
+config ROCKCHIP_COMMON_STACK_ADDR
+	default y
+
 config SYS_MALLOC_F_LEN
-	default 0x400
+	default 0x400 if !SPL_SHARES_INIT_SP_ADDR
 
 config SPL_SERIAL
 	default y
@@ -83,6 +86,9 @@
 config TPL_STACK
 	default 0xff0e4fff
 
+config TPL_SYS_MALLOC_F_LEN
+	default 0x600
+
 config DEBUG_UART_CHANNEL
 	int "Mux channel to use for debug UART2/UART3"
 	depends on DEBUG_UART_BOARD_INIT
diff --git a/arch/arm/mach-rockchip/rk3568/Kconfig b/arch/arm/mach-rockchip/rk3568/Kconfig
index af537d9..014ebf9 100644
--- a/arch/arm/mach-rockchip/rk3568/Kconfig
+++ b/arch/arm/mach-rockchip/rk3568/Kconfig
@@ -22,6 +22,11 @@
 	help
 	  Hardkernel ODROID-M1 single board computer with a RK3568B2 SoC.
 
+config TARGET_POWKIDDY_X55_RK3566
+	bool "Powkiddy X55"
+	help
+	  Powkiddy X55 handheld gaming console with an RK3566 SoC.
+
 config TARGET_QUARTZ64_RK3566
 	bool "Pine64 Quartz64"
 	help
@@ -48,5 +53,6 @@
 source "board/anbernic/rgxx3_rk3566/Kconfig"
 source "board/hardkernel/odroid_m1/Kconfig"
 source "board/pine64/quartz64_rk3566/Kconfig"
+source "board/powkiddy/x55/Kconfig"
 
 endif
diff --git a/arch/arm/mach-rockchip/rk3588/Kconfig b/arch/arm/mach-rockchip/rk3588/Kconfig
index 39049ab..820e979 100644
--- a/arch/arm/mach-rockchip/rk3588/Kconfig
+++ b/arch/arm/mach-rockchip/rk3588/Kconfig
@@ -78,6 +78,15 @@
 	  Power: 5.5*2.1mm DC Jack, 12VDC input
 	  Dimensions: 110x80x1.6mm (without case) / 86x114.5x30mm (with case)
 
+config TARGET_NOVA_RK3588
+	bool "Indiedroid Nova RK3588"
+	select BOARD_LATE_INIT
+	help
+	  Indiedroid Nova is a Rockchip RK3588s based SBC by Indiedroid.
+	  It comes in configurations from 4GB of RAM to 16GB of RAM,
+	  includes socket for eMMC storage, an SDMMC slot, and a 40-pin
+	  GPIO header for expansion.
+
 config TARGET_RK3588_NEU6
 	bool "Edgeble Neural Compute Module 6(Neu6) SoM"
 	select BOARD_LATE_INIT
@@ -223,6 +232,7 @@
 
 source "board/edgeble/neural-compute-module-6/Kconfig"
 source "board/friendlyelec/nanopc-t6-rk3588/Kconfig"
+source "board/indiedroid/nova/Kconfig"
 source "board/pine64/quartzpro64-rk3588/Kconfig"
 source "board/turing/turing-rk1-rk3588/Kconfig"
 source "board/radxa/rock5a-rk3588s/Kconfig"
diff --git a/arch/riscv/cpu/andes/cache.c b/arch/riscv/cpu/andes/cache.c
index 7d3df87..bb57498 100644
--- a/arch/riscv/cpu/andes/cache.c
+++ b/arch/riscv/cpu/andes/cache.c
@@ -43,9 +43,7 @@
 
 void flush_dcache_all(void)
 {
-#if CONFIG_IS_ENABLED(RISCV_MMODE)
-	csr_write(CSR_MCCTLCOMMAND, CCTL_L1D_WBINVAL_ALL);
-#endif
+	csr_write(CSR_UCCTLCOMMAND, CCTL_L1D_WBINVAL_ALL);
 }
 
 void flush_dcache_range(unsigned long start, unsigned long end)
diff --git a/arch/riscv/cpu/start.S b/arch/riscv/cpu/start.S
index a9e1935..8e58f64 100644
--- a/arch/riscv/cpu/start.S
+++ b/arch/riscv/cpu/start.S
@@ -210,10 +210,6 @@
 	bnez	s2, secondary_hart_loop
 #endif
 
-	/* Enable cache */
-	jal	icache_enable
-	jal	dcache_enable
-
 #ifdef CONFIG_DEBUG_UART
 	jal	debug_uart_init
 #endif
diff --git a/arch/riscv/include/asm/arch-andes/csr.h b/arch/riscv/include/asm/arch-andes/csr.h
index 028fd01..7d6104a 100644
--- a/arch/riscv/include/asm/arch-andes/csr.h
+++ b/arch/riscv/include/asm/arch-andes/csr.h
@@ -12,7 +12,7 @@
 
 #define CSR_MCACHE_CTL 0x7ca
 #define CSR_MMISC_CTL 0x7d0
-#define CSR_MCCTLCOMMAND 0x7cc
+#define CSR_UCCTLCOMMAND 0x80c
 
 /* mcache_ctl register */