diff --git a/arch/arm/cpu/armv7/omap3/sdrc.c b/arch/arm/cpu/armv7/omap3/sdrc.c
index 96fd990c..8905224 100644
--- a/arch/arm/cpu/armv7/omap3/sdrc.c
+++ b/arch/arm/cpu/armv7/omap3/sdrc.c
@@ -107,18 +107,12 @@
 /*
  * do_sdrc_init -
  *  - Initialize the SDRAM for use.
- *  - Sets up SDRC timings for CS0
  *  - code called once in C-Stack only context for CS0 and a possible 2nd
  *    time depending on memory configuration from stack+global context
  */
 void do_sdrc_init(u32 cs, u32 early)
 {
-	struct sdrc_actim *sdrc_actim_base;
-
-	if (cs)
-		sdrc_actim_base = (struct sdrc_actim *)SDRC_ACTIM_CTRL1_BASE;
-	else
-		sdrc_actim_base = (struct sdrc_actim *)SDRC_ACTIM_CTRL0_BASE;
+	struct sdrc_actim *sdrc_actim_base0, *sdrc_actim_base1;
 
 	if (early) {
 		/* reset sdrc controller */
@@ -138,24 +132,29 @@
 		sdelay(0x20000);
 	}
 
-	writel(RASWIDTH_13BITS | CASWIDTH_10BITS | ADDRMUXLEGACY |
-			RAMSIZE_128 | BANKALLOCATION | B32NOT16 | B32NOT16 |
-			DEEPPD | DDR_SDRAM, &sdrc_base->cs[cs].mcfg);
-	writel(ARCV | ARE_ARCV_1, &sdrc_base->cs[cs].rfr_ctrl);
-	writel(V_ACTIMA_165, &sdrc_actim_base->ctrla);
-	writel(V_ACTIMB_165, &sdrc_actim_base->ctrlb);
-
-	writel(CMD_NOP, &sdrc_base->cs[cs].manual);
-	writel(CMD_PRECHARGE, &sdrc_base->cs[cs].manual);
-	writel(CMD_AUTOREFRESH, &sdrc_base->cs[cs].manual);
-	writel(CMD_AUTOREFRESH, &sdrc_base->cs[cs].manual);
-
 	/*
-	 * CAS latency 3, Write Burst = Read Burst, Serial Mode,
-	 * Burst length = 4
+	 * SDRC timings are set up by x-load or config header
+	 * We don't need to redo them here.
+	 * Older x-loads configure only CS0
+	 * configure CS1 to handle this ommission
 	 */
-	writel(CASL3 | BURSTLENGTH4, &sdrc_base->cs[cs].mr);
+	if (cs) {
+		sdrc_actim_base0 = (struct sdrc_actim *)SDRC_ACTIM_CTRL0_BASE;
+		sdrc_actim_base1 = (struct sdrc_actim *)SDRC_ACTIM_CTRL1_BASE;
+		writel(readl(&sdrc_base->cs[CS0].mcfg),
+			&sdrc_base->cs[CS1].mcfg);
+		writel(readl(&sdrc_base->cs[CS0].rfr_ctrl),
+			&sdrc_base->cs[CS1].rfr_ctrl);
+		writel(readl(&sdrc_actim_base0->ctrla),
+			&sdrc_actim_base1->ctrla);
+		writel(readl(&sdrc_actim_base0->ctrlb),
+			&sdrc_actim_base1->ctrlb);
+	}
 
+	/*
+	 * Test ram in this bank
+	 * Disable if bad or not present
+	 */
 	if (!mem_ok(cs))
 		writel(0, &sdrc_base->cs[cs].mcfg);
 }