commit a6f493651eaa1578b0a6e8e6d9c09ba199c800a3
author developer <developer@mediatek.com> Fri Jan 17 17:18:55 2025 +0800
committer Tom Rini <trini@konsulko.com> Thu Jan 23 12:11:49 2025 -0600
tree 9e2c97f56535ee30f56425918c8b06b8a696cc07
parent 2602d53d940fbd43c25f857c8e241267edd1d39a

arm: dts: mediatek: update mt7981 mmc node

1. Fix mmc clock order of mt7981 to match the clock name
2. Limit the max clock of SD to 50MHz to meet SD Card Spec 2.0
3. Increase the CLK pin driving strength to 8mA

arch/arm/dts/mt7981-sd-rfb.dts

diff --git a/arch/arm/dts/mt7981-sd-rfb.dts b/arch/arm/dts/mt7981-sd-rfb.dts
index 50ded1e..2adbc37 100644
--- a/arch/arm/dts/mt7981-sd-rfb.dts
+++ b/arch/arm/dts/mt7981-sd-rfb.dts
@@ -118,7 +118,7 @@
 		};
 		conf-clk {
 			pins = "SPI1_CS";
-			drive-strength = <MTK_DRIVE_6mA>;
+			drive-strength = <MTK_DRIVE_8mA>;
 			bias-pull-down = <MTK_PUPD_SET_R1R0_10>;
 		};
 		conf-rst {
@@ -140,10 +140,12 @@
 };
 
 &mmc0 {
+	assigned-clock-parents = <&topckgen CLK_TOP_CB_NET2_D4>,
+				 <&topckgen CLK_TOP_CB_NET2_D2>;
 	pinctrl-names = "default";
 	pinctrl-0 = <&mmc0_pins_default>;
 	bus-width = <4>;
-	max-frequency = <52000000>;
+	max-frequency = <50000000>;
 	cap-sd-highspeed;
 	r_smpl = <0>;
 	vmmc-supply = <&reg_3p3v>;

arch/arm/dts/mt7981.dtsi

diff --git a/arch/arm/dts/mt7981.dtsi b/arch/arm/dts/mt7981.dtsi
index 43e5058..2844ab0 100644
--- a/arch/arm/dts/mt7981.dtsi
+++ b/arch/arm/dts/mt7981.dtsi
@@ -306,13 +306,13 @@
 		reg = <0x11230000 0x1000>,
 		      <0x11C20000 0x1000>;
 		interrupts = <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>;
-		clocks = <&topckgen CLK_TOP_EMMC_400M>,
-			 <&topckgen CLK_TOP_EMMC_208M>,
+		clocks = <&topckgen CLK_TOP_EMMC_208M>,
+			 <&topckgen CLK_TOP_EMMC_400M>,
 			 <&infracfg CLK_INFRA_MSDC_CK>;
-		assigned-clocks = <&topckgen CLK_TOP_EMMC_400M_SEL>,
-				  <&topckgen CLK_TOP_EMMC_208M_SEL>;
-		assigned-clock-parents = <&topckgen CLK_TOP_CB_NET2_D2>,
-					 <&topckgen CLK_TOP_CB_M_D2>;
+		assigned-clocks = <&topckgen CLK_TOP_EMMC_208M_SEL>,
+				  <&topckgen CLK_TOP_EMMC_400M_SEL>;
+		assigned-clock-parents = <&topckgen CLK_TOP_CB_M_D2>,
+					 <&topckgen CLK_TOP_CB_NET2_D2>;
 		clock-names = "source", "hclk", "source_cg";
 		status = "disabled";
 	};