video: dw-mipi-dsi: driver-specific configuration of phy timings
The timing values for dw-dsi are often dependent on the used display and
according to Philippe Cornu will most likely also depend on the used phy
technology in the soc-specific implementation.
To solve this and allow specific implementations to define them as needed
add a new get_timing callback to phy_ops and call this from the dphy_timing
function to retrieve the necessary values for the specific mode.
This is based on the Linux commit [1] and adapted to the U-Boot driver.
[1] 25ed8aeb9c39 ("drm/bridge/synopsys: dsi: driver-specific configuration of phy timings")
Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
diff --git a/drivers/video/dw_mipi_dsi.c b/drivers/video/dw_mipi_dsi.c
index 2743836..44a60ac 100644
--- a/drivers/video/dw_mipi_dsi.c
+++ b/drivers/video/dw_mipi_dsi.c
@@ -645,8 +645,13 @@
static void dw_mipi_dsi_dphy_timing_config(struct dw_mipi_dsi *dsi)
{
+ const struct mipi_dsi_phy_ops *phy_ops = dsi->phy_ops;
+ struct mipi_dsi_phy_timing timing = {0x40, 0x40, 0x40, 0x40};
u32 hw_version;
+ if (phy_ops->get_timing)
+ phy_ops->get_timing(dsi->device, dsi->lane_mbps, &timing);
+
/*
* TODO dw drv improvements
* data & clock lane timers should be computed according to panel
@@ -658,16 +663,16 @@
hw_version = dsi_read(dsi, DSI_VERSION) & VERSION;
if (hw_version >= HWVER_131) {
- dsi_write(dsi, DSI_PHY_TMR_CFG, PHY_HS2LP_TIME_V131(0x40) |
- PHY_LP2HS_TIME_V131(0x40));
+ dsi_write(dsi, DSI_PHY_TMR_CFG, PHY_HS2LP_TIME_V131(timing.data_hs2lp) |
+ PHY_LP2HS_TIME_V131(timing.data_lp2hs));
dsi_write(dsi, DSI_PHY_TMR_RD_CFG, MAX_RD_TIME_V131(10000));
} else {
- dsi_write(dsi, DSI_PHY_TMR_CFG, PHY_HS2LP_TIME(0x40) |
- PHY_LP2HS_TIME(0x40) | MAX_RD_TIME(10000));
+ dsi_write(dsi, DSI_PHY_TMR_CFG, PHY_HS2LP_TIME(timing.data_hs2lp) |
+ PHY_LP2HS_TIME(timing.data_lp2hs) | MAX_RD_TIME(10000));
}
- dsi_write(dsi, DSI_PHY_TMR_LPCLK_CFG, PHY_CLKHS2LP_TIME(0x40)
- | PHY_CLKLP2HS_TIME(0x40));
+ dsi_write(dsi, DSI_PHY_TMR_LPCLK_CFG, PHY_CLKHS2LP_TIME(timing.clk_hs2lp)
+ | PHY_CLKLP2HS_TIME(timing.clk_lp2hs));
}
static void dw_mipi_dsi_dphy_interface_config(struct dw_mipi_dsi *dsi)
diff --git a/include/mipi_dsi.h b/include/mipi_dsi.h
index c8a7d3d..55c7ab3 100644
--- a/include/mipi_dsi.h
+++ b/include/mipi_dsi.h
@@ -97,6 +97,20 @@
};
/**
+ * struct mipi_dsi_phy_timing - DSI host phy timings
+ * @data_hs2lp: High Speed to Low Speed Data Transition Time
+ * @data_lp2hs: Low Speed to High Speed Data Transition Time
+ * @clk_hs2lp: High Speed to Low Speed Clock Transition Time
+ * @clk_lp2hs: Low Speed to High Speed Clock Transition Time
+ */
+struct mipi_dsi_phy_timing {
+ u16 data_hs2lp;
+ u16 data_lp2hs;
+ u16 clk_hs2lp;
+ u16 clk_lp2hs;
+};
+
+/**
* struct mipi_dsi_phy_ops - DSI host physical operations
* @init: initialized host physical part
* @get_lane_mbps: get lane bitrate per lane (mbps)
@@ -107,6 +121,8 @@
int (*get_lane_mbps)(void *priv_data, struct display_timing *timings,
u32 lanes, u32 format, unsigned int *lane_mbps);
void (*post_set_mode)(void *priv_data, unsigned long mode_flags);
+ int (*get_timing)(void *priv_data, unsigned int lane_mbps,
+ struct mipi_dsi_phy_timing *timing);
};
/**