spi: synquacer: simplify tx completion checking
There is a TX-FIFO and Shift Register empty(TFES) status
bit in spi controller. This commit checks the TFES bit
to wait the TX transfer completes.
Signed-off-by: Masahisa Kojima <masahisa.kojima@linaro.org>
Signed-off-by: Satoru Okamoto <okamoto.satoru@socionext.com>
Acked-by: Jassi Brar <jaswinder.singh@linaro.org>
diff --git a/drivers/spi/spi-synquacer.c b/drivers/spi/spi-synquacer.c
index 5e1b3ae..0cae3df 100644
--- a/drivers/spi/spi-synquacer.c
+++ b/drivers/spi/spi-synquacer.c
@@ -45,6 +45,7 @@
#define RXF 0x20
#define RXE 0x24
#define RXC 0x28
+#define TFES 1
#define TFLETE 4
#define TSSRS 6
#define RFMTE 5
@@ -345,13 +346,10 @@
if (priv->tx_words) {
write_fifo(priv);
} else {
- u32 len;
-
- do { /* wait for shifter to empty out */
+ /* wait for shifter to empty out */
+ while (!(readl(priv->base + TXF) & BIT(TFES)))
cpu_relax();
- len = readl(priv->base + DMSTATUS);
- len = (len >> TX_DATA_SHIFT) & TX_DATA_MASK;
- } while (tx_buf && len);
+
busy &= ~BIT(TXBIT);
}
}