arm: socfpga: Add the terasic de10-standard board
Use the de10-nano files as templates for the de10-standard board.
The files in qts directory are generated by quartus from the GHRD
design.
Signed-off-by: Humberto Naves <hsnaves@gmail.com>
Reviewed-by: Marek Vasut <marex@denx.de>
diff --git a/arch/arm/dts/socfpga_cyclone5_de10_standard.dts b/arch/arm/dts/socfpga_cyclone5_de10_standard.dts
new file mode 100644
index 0000000..39bce3b
--- /dev/null
+++ b/arch/arm/dts/socfpga_cyclone5_de10_standard.dts
@@ -0,0 +1,86 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2017, Intel Corporation
+ *
+ * Adapted from socfpga_cyclone5_de10_nano.dts
+ */
+
+#include "socfpga_cyclone5.dtsi"
+#include "socfpga-common-u-boot.dtsi"
+
+/ {
+ model = "Terasic DE10-Standard";
+ compatible = "altr,socfpga-cyclone5", "altr,socfpga";
+
+ chosen {
+ bootargs = "console=ttyS0,115200";
+ stdout-path = "serial0:115200n8";
+ };
+
+ aliases {
+ ethernet0 = &gmac1;
+ udc0 = &usb1;
+ };
+
+ memory {
+ name = "memory";
+ device_type = "memory";
+ reg = <0x0 0x40000000>; /* 1GB */
+ };
+};
+
+&gmac1 {
+ status = "okay";
+ phy-mode = "rgmii";
+
+ rxd0-skew-ps = <420>;
+ rxd1-skew-ps = <420>;
+ rxd2-skew-ps = <420>;
+ rxd3-skew-ps = <420>;
+ txen-skew-ps = <0>;
+ txc-skew-ps = <1860>;
+ rxdv-skew-ps = <420>;
+ rxc-skew-ps = <1680>;
+};
+
+&gpio0 {
+ status = "okay";
+};
+
+&gpio1 {
+ status = "okay";
+};
+
+&gpio2 {
+ status = "okay";
+};
+
+&porta {
+ bank-name = "porta";
+};
+
+&portb {
+ bank-name = "portb";
+};
+
+&portc {
+ bank-name = "portc";
+};
+
+&mmc0 {
+ status = "okay";
+ u-boot,dm-pre-reloc;
+};
+
+&usb1 {
+ status = "okay";
+};
+
+&uart0 {
+ clock-frequency = <100000000>;
+ u-boot,dm-pre-reloc;
+};
+
+&watchdog0 {
+ status = "disabled";
+};
diff --git a/arch/arm/mach-socfpga/Kconfig b/arch/arm/mach-socfpga/Kconfig
index 78a7549..547e47e 100644
--- a/arch/arm/mach-socfpga/Kconfig
+++ b/arch/arm/mach-socfpga/Kconfig
@@ -180,6 +180,10 @@
bool "Terasic DE10-Nano (Cyclone V)"
select TARGET_SOCFPGA_CYCLONE5
+config TARGET_SOCFPGA_TERASIC_DE10_STANDARD
+ bool "Terasic DE10-Standard (Cyclone V)"
+ select TARGET_SOCFPGA_CYCLONE5
+
config TARGET_SOCFPGA_TERASIC_DE1_SOC
bool "Terasic DE1-SoC (Cyclone V)"
select TARGET_SOCFPGA_CYCLONE5
@@ -199,6 +203,7 @@
default "de0-nano-soc" if TARGET_SOCFPGA_TERASIC_DE0_NANO
default "de1-soc" if TARGET_SOCFPGA_TERASIC_DE1_SOC
default "de10-nano" if TARGET_SOCFPGA_TERASIC_DE10_NANO
+ default "de10-standard" if TARGET_SOCFPGA_TERASIC_DE10_STANDARD
default "is1" if TARGET_SOCFPGA_IS1
default "mcvevk" if TARGET_SOCFPGA_ARIES_MCVEVK
default "n5x-socdk" if TARGET_SOCFPGA_N5X_SOCDK
@@ -224,6 +229,7 @@
default "terasic" if TARGET_SOCFPGA_TERASIC_DE0_NANO
default "terasic" if TARGET_SOCFPGA_TERASIC_DE1_SOC
default "terasic" if TARGET_SOCFPGA_TERASIC_DE10_NANO
+ default "terasic" if TARGET_SOCFPGA_TERASIC_DE10_STANDARD
default "terasic" if TARGET_SOCFPGA_TERASIC_SOCKIT
config SYS_SOC
@@ -239,6 +245,7 @@
default "socfpga_de0_nano_soc" if TARGET_SOCFPGA_TERASIC_DE0_NANO
default "socfpga_de1_soc" if TARGET_SOCFPGA_TERASIC_DE1_SOC
default "socfpga_de10_nano" if TARGET_SOCFPGA_TERASIC_DE10_NANO
+ default "socfpga_de10_standard" if TARGET_SOCFPGA_TERASIC_DE10_STANDARD
default "socfpga_is1" if TARGET_SOCFPGA_IS1
default "socfpga_mcvevk" if TARGET_SOCFPGA_ARIES_MCVEVK
default "socfpga_n5x_socdk" if TARGET_SOCFPGA_N5X_SOCDK