Merge patch series "boot: fdt: Change type of env_get_bootm_low() to phys_addr_t"
diff --git a/.azure-pipelines.yml b/.azure-pipelines.yml
index 0a8f49b..27f6958 100644
--- a/.azure-pipelines.yml
+++ b/.azure-pipelines.yml
@@ -2,7 +2,7 @@
windows_vm: windows-2019
ubuntu_vm: ubuntu-22.04
macos_vm: macOS-12
- ci_runner_image: trini/u-boot-gitlab-ci-runner:jammy-20240125-12Feb2024
+ ci_runner_image: trini/u-boot-gitlab-ci-runner:jammy-20240227-14Mar2024
# Add '-u 0' options for Azure pipelines, otherwise we get "permission
# denied" error when it tries to "useradd -m -u 1001 vsts_azpcontainer",
# since our $(ci_runner_image) user is not root.
@@ -277,16 +277,16 @@
TEST_PY_TEST_SPEC: "version"
sandbox_clang:
TEST_PY_BD: "sandbox"
- OVERRIDE: "-O clang-16"
+ OVERRIDE: "-O clang-17"
sandbox_clang_asan:
TEST_PY_BD: "sandbox"
- OVERRIDE: "-O clang-16 -a ASAN"
+ OVERRIDE: "-O clang-17 -a ASAN"
TEST_PY_TEST_SPEC: "version"
sandbox64:
TEST_PY_BD: "sandbox64"
sandbox64_clang:
TEST_PY_BD: "sandbox64"
- OVERRIDE: "-O clang-16"
+ OVERRIDE: "-O clang-17"
sandbox_spl:
TEST_PY_BD: "sandbox_spl"
TEST_PY_TEST_SPEC: "test_ofplatdata or test_handoff or test_spl"
diff --git a/.gitignore b/.gitignore
index 3301481..be13704 100644
--- a/.gitignore
+++ b/.gitignore
@@ -63,6 +63,10 @@
/spl/
/tpl/
/defconfig
+/generated_defconfig
+/Test*
+/capsule.*.efi-capsule
+/capsule*.map
#
# Generated include files
diff --git a/.gitlab-ci.yml b/.gitlab-ci.yml
index b23ece3..165f765 100644
--- a/.gitlab-ci.yml
+++ b/.gitlab-ci.yml
@@ -10,7 +10,7 @@
# Grab our configured image. The source for this is found
# in the u-boot tree at tools/docker/Dockerfile
-image: ${MIRROR_DOCKER}/trini/u-boot-gitlab-ci-runner:jammy-20240125-12Feb2024
+image: ${MIRROR_DOCKER}/trini/u-boot-gitlab-ci-runner:jammy-20240227-14Mar2024
# We run some tests in different order, to catch some failures quicker.
stages:
@@ -251,7 +251,7 @@
sandbox with clang test.py:
variables:
TEST_PY_BD: "sandbox"
- OVERRIDE: "-O clang-16"
+ OVERRIDE: "-O clang-17"
<<: *buildman_and_testpy_dfn
sandbox64 test.py:
@@ -262,7 +262,7 @@
sandbox64 with clang test.py:
variables:
TEST_PY_BD: "sandbox64"
- OVERRIDE: "-O clang-16"
+ OVERRIDE: "-O clang-17"
<<: *buildman_and_testpy_dfn
sandbox_spl test.py:
diff --git a/.mailmap b/.mailmap
index d1f08f3..932bd4d 100644
--- a/.mailmap
+++ b/.mailmap
@@ -30,6 +30,7 @@
Bharat Kumar Gogada <bharat.kumar.gogada@amd.com> <bharat.kumar.gogada@xilinx.com>
Bharat Kumar Gogada <bharat.kumar.gogada@amd.com> <bharatku@xilinx.com>
Bhargava Sreekantappa Gayathri <bhargava.sreekantappa-gayathri@amd.com> <bhargava.sreekantappa-gayathri@xilinx.com>
+Bhupesh Sharma <bhupesh.linux@gmail.com> <bhupesh.sharma@linaro.org>
Bin Meng <bmeng.cn@gmail.com> <bin.meng@windriver.com>
Boris Brezillon <bbrezillon@kernel.org> <boris.brezillon@bootlin.com>
Boris Brezillon <bbrezillon@kernel.org> <boris.brezillon@free-electrons.com>
@@ -57,6 +58,7 @@
Jyotheeswar Reddy Mutthareddyvari <jyotheeswar.reddy.mutthareddyvari@amd.com> <jyothee@xilinx.com>
Jyotheeswar Reddy Mutthareddyvari <jyotheeswar.reddy.mutthareddyvari@amd.com> <jyotheeswar.reddy.mutthareddyvari@xilinx.com>
Kalyani Akula <kalyani.akula@amd.com> <kalyani.akula@xilinx.com>
+Masahisa Kojima <kojima.masahisa@socionext.com> <masahisa.kojima@linaro.org>
Love Kumar <love.kumar@amd.com> <love.kumar@xilinx.com>
Lukasz Majewski <lukma@denx.de>
Marek Behún <kabel@kernel.org> <marek.behun@nic.cz>
diff --git a/Kconfig b/Kconfig
index 5710934..82df59f 100644
--- a/Kconfig
+++ b/Kconfig
@@ -265,7 +265,7 @@
hex "Size of malloc() pool before relocation"
depends on SYS_MALLOC_F
default 0x400 if M68K || PPC || ROCKCHIP_PX30 || ROCKCHIP_RK3036 || \
- ROCKCHIP_RK3308 || ROCKCHIP_RV1108
+ ROCKCHIP_RV1108
default 0x600 if ARCH_ZYNQMP_R5 || ARCH_ZYNQMP
default 0x800 if ARCH_ZYNQ || ROCKCHIP_RK3128 || ROCKCHIP_RK3188 || \
ROCKCHIP_RK322X || X86
@@ -715,6 +715,20 @@
A static value for the CPU frequency. Note that if not required
for a given SoC, this can be left at 0.
+config HAS_LDR
+ bool
+ help
+ Enables building .ldr targets for U-Boot and SPL. This does not
+ automatically build any additional targets with make or buildman.
+
+config LDR_CPU
+ string "CPU name to be passed to LDR utility."
+ depends on HAS_LDR
+ help
+ Set the CPU name for the -T parameter in the LDR utility. This is
+ generally used on processors from Analog Devices, but may be also
+ be useful for other vendors.
+
source "api/Kconfig"
endmenu # General setup
diff --git a/MAINTAINERS b/MAINTAINERS
index b1c5a9a..0462ade 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -55,6 +55,7 @@
S: Maintained
F: board/emulation/configs/acpi.config
F: cmd/acpi.c
+F: include/acpi/
F: lib/acpi/
ANDROID AB
@@ -683,13 +684,6 @@
N: stm
N: stm32
-
-ARM STM STV0991
-M: Vikas Manocha <vikas.manocha@st.com>
-S: Maintained
-F: arch/arm/cpu/armv7/stv0991/
-F: arch/arm/include/asm/arch-stv0991/
-
ARM SUNXI
M: Jagan Teki <jagan@amarulasolutions.com>
M: Andre Przywara <andre.przywara@arm.com>
@@ -1378,6 +1372,12 @@
S: Maintained
F: tools/patman/
+PCIe DWC IMX
+M: Sumit Garg <sumit.garg@linaro.org>
+S: Maintained
+F: drivers/pci/pcie_dw_imx.c
+F: drivers/phy/phy-imx8m-pcie.c
+
PCI Endpoint
M: Ramon Fried <rfried.dev@gmail.com>
S: Maintained
diff --git a/Makefile b/Makefile
index 28a2a1d..7321fe1 100644
--- a/Makefile
+++ b/Makefile
@@ -3,7 +3,7 @@
VERSION = 2024
PATCHLEVEL = 04
SUBLEVEL =
-EXTRAVERSION = -rc4
+EXTRAVERSION =
NAME =
# *DOCUMENTATION*
@@ -1300,12 +1300,17 @@
$(if $(CONFIG_MPC85XX_HAVE_RESET_VECTOR),$(if $(CONFIG_OF_SEPARATE),-R .bootpg -R .resetvec))
binary_size_check: u-boot-nodtb.bin FORCE
- @file_size=$(shell wc -c u-boot-nodtb.bin | awk '{print $$1}') ; \
+ @file_size=$(shell wc -c u-boot-nodtb.bin | awk '{ print $$1 }') ; \
map_size=$(shell cat u-boot.map | \
- awk '/_image_copy_start/ {start = $$1} /_image_binary_end/ {end = $$1} END {if (start != "" && end != "") print "ibase=16; " toupper(end) " - " toupper(start)}' \
- | sed 's/0X//g' \
- | bc); \
- if [ "" != "$$map_size" ]; then \
+ awk ' \
+ /_image_copy_start/ { start = $$1 } \
+ /_image_binary_end/ { end = $$1 } \
+ END { \
+ if (start != "" && end != "") \
+ print end " " start; \
+ }' \
+ | sh -c 'read end start && echo $$((end - start))'); \
+ if [ -n "$$map_size" ]; then \
if test $$map_size -ne $$file_size; then \
echo "u-boot.map shows a binary size of $$map_size" >&2 ; \
echo " but u-boot-nodtb.bin shows $$file_size" >&2 ; \
@@ -1355,7 +1360,7 @@
u-boot.ldr: u-boot
$(CREATE_LDR_ENV)
- $(LDR) -T $(CONFIG_CPU) -c $@ $< $(LDR_FLAGS)
+ $(LDR) -T $(CONFIG_LDR_CPU) -c $@ $< $(LDR_FLAGS)
$(BOARD_SIZE_CHECK)
# binman
@@ -1958,6 +1963,7 @@
echo \#define U_BOOT_VERSION_NUM $(VERSION); \
echo \#define U_BOOT_VERSION_NUM_PATCH $$(echo $(PATCHLEVEL) | \
sed -e "s/^0*//"); \
+ echo \#define HOST_ARCH $(HOST_ARCH); \
echo \#define CC_VERSION_STRING \"$$(LC_ALL=C $(CC) --version | head -n 1)\"; \
echo \#define LD_VERSION_STRING \"$$(LC_ALL=C $(LD) --version | head -n 1)\"; )
endef
@@ -2194,7 +2200,8 @@
mkimage-out.spl.mkimage mkimage.spl.mkimage imx-boot.map \
itb.fit.fit itb.fit.itb itb.map spl.map mkimage-out.rom.mkimage \
mkimage.rom.mkimage mkimage-in-simple-bin* rom.map simple-bin* \
- idbloader-spi.img lib/efi_loader/helloworld_efi.S *.itb
+ idbloader-spi.img lib/efi_loader/helloworld_efi.S *.itb \
+ Test* capsule.*.efi-capsule capsule*.map
# Directories & files removed with 'make mrproper'
MRPROPER_DIRS += include/config include/generated spl tpl vpl \
@@ -2233,6 +2240,7 @@
-o -name modules.builtin -o -name '.tmp_*.o.*' \
-o -name 'dsdt_generated.aml' -o -name 'dsdt_generated.asl.tmp' \
-o -name 'dsdt_generated.c' \
+ -o -name 'generated_defconfig' \
-o -name '*.efi' -o -name '*.gcno' -o -name '*.so' \) \
-type f -print | xargs rm -f
diff --git a/arch/Kconfig b/arch/Kconfig
index 0d3cce9..abd406d 100644
--- a/arch/Kconfig
+++ b/arch/Kconfig
@@ -20,6 +20,12 @@
config SYS_CACHE_SHIFT_7
bool
+config 32BIT
+ bool
+
+config 64BIT
+ bool
+
config SYS_CACHELINE_SIZE
int
default 128 if SYS_CACHE_SHIFT_7
@@ -248,7 +254,6 @@
imply CMD_PCI
imply CMD_SF
imply CMD_SF_TEST
- imply CMD_ZBOOT
imply DM_GPIO
imply DM_KEYBOARD
imply DM_MMC
diff --git a/arch/arc/lib/Makefile b/arch/arc/lib/Makefile
index 0eb44bc..bde1c3d 100644
--- a/arch/arc/lib/Makefile
+++ b/arch/arc/lib/Makefile
@@ -12,6 +12,6 @@
obj-y += ints_low.o
obj-y += init_helpers.o
-obj-$(CONFIG_CMD_BOOTM) += bootm.o
+obj-$(CONFIG_BOOTM) += bootm.o
lib-$(CONFIG_USE_PRIVATE_LIBGCC) += _millicodethunk.o libgcc2.o
diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
index 85f0111..23ee252 100644
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@ -6,6 +6,7 @@
config ARM64
bool
+ select 64BIT
select PHYS_64BIT
select SYS_CACHE_SHIFT_6
imply SPL_SEPARATE_BSS
@@ -28,6 +29,7 @@
ROCKCHIP_RK3288 || ROCKCHIP_RK322X || ROCKCHIP_RK3036
default 25000000 if ARCH_LX2160A || ARCH_LX2162A || ARCH_LS1088A
default 100000000 if ARCH_ZYNQMP
+ default 200000000 if ARCH_SOCFPGA && ARM64 && TARGET_SOCFPGA_AGILEX5
default 0
help
For platforms with ARMv8-A and ARMv7-A which features a system
@@ -122,6 +124,15 @@
ARM GICV3 has limitation, once the LPI table is enabled, LPI
configuration table can not be re-programmed, unless GICV3 reset.
+config GICV3_SUPPORT_GIC600
+ bool "ARM GICV3 GIC600 SUPPORT"
+ help
+ ARM GIC-600 IP complies with ARM GICv3 architecture, but among others,
+ implements a power control register in the Redistributor frame.This
+ register must be programmed to mark the frame as powered on, before
+ accessing other registers in the frame. Rest of initialization sequence
+ remains the same.
+
config STATIC_RELA
bool
default y if ARM64
@@ -631,20 +642,6 @@
select SPL_SEPARATE_BSS if SPL
select TIMER
-config TARGET_STV0991
- bool "Support stv0991"
- select CPU_V7A
- select DM
- select DM_SERIAL
- select DM_SPI
- select DM_SPI_FLASH
- select GPIO_EXTRA_HEADER
- select PL01X_SERIAL
- select MTD
- select SPI
- select SPI_FLASH
- imply CMD_DM
-
config ARCH_BCM283X
bool "Broadcom BCM283X family"
select DM
@@ -1081,6 +1078,7 @@
select DM_GPIO
select DM_SERIAL
select DM_RESET
+ select POWER_DOMAIN
select GPIO_EXTRA_HEADER
select MSM_SMEM
select OF_CONTROL
@@ -1111,6 +1109,8 @@
select SPL_LIBGENERIC_SUPPORT
select SPL_OF_CONTROL
select SPL_SEPARATE_BSS if TARGET_SOCFPGA_SOC64
+ select SPL_DRIVERS_MISC if TARGET_SOCFPGA_SOC64
+ select SPL_SOCFPGA_DT_REG if TARGET_SOCFPGA_SOC64
select SPL_SERIAL
select SPL_SYSRESET
select SPL_WATCHDOG
@@ -1119,7 +1119,8 @@
select SYS_THUMB_BUILD if TARGET_SOCFPGA_GEN5 || TARGET_SOCFPGA_ARRIA10
select SYSRESET
select SYSRESET_SOCFPGA if TARGET_SOCFPGA_GEN5 || TARGET_SOCFPGA_ARRIA10
- select SYSRESET_SOCFPGA_SOC64 if TARGET_SOCFPGA_SOC64
+ select SYSRESET_SOCFPGA_SOC64 if !TARGET_SOCFPGA_AGILEX5 && \
+ TARGET_SOCFPGA_SOC64
imply CMD_DM
imply CMD_MTDPARTS
imply CRC32_VERIFY
@@ -1320,6 +1321,14 @@
select SPL_DM_SPI_FLASH if SPL_DM_SPI
select SPL_DM_MAILBOX if SPL
imply SPL_FIRMWARE if SPL
+ imply SPL_FS_FAT if SPL
+ imply SPL_LIBCOMMON_SUPPORT if SPL
+ imply SPL_LIBDISK_SUPPORT if SPL
+ imply SPL_LIBGENERIC_SUPPORT if SPL
+ imply SPL_MMC if SPL && MMC_SDHCI_ZYNQ
+ imply SPL_SERIAL if SPL
+ imply SPL_SPI if SPL && ZYNQ_QSPI
+ imply SPL_SPI_FLASH_SUPPORT if SPL && ZYNQ_QSPI
select SPL_SEPARATE_BSS if SPL
select SUPPORT_SPL
imply ZYNQMP_IPI if DM_MAILBOX
@@ -2358,7 +2367,6 @@
source "board/siemens/common/Kconfig"
source "board/seeed/npi_imx6ull/Kconfig"
source "board/socionext/developerbox/Kconfig"
-source "board/st/stv0991/Kconfig"
source "board/tcl/sl50/Kconfig"
source "board/traverse/ten64/Kconfig"
source "board/variscite/dart_6ul/Kconfig"
diff --git a/arch/arm/cpu/armv7/Makefile b/arch/arm/cpu/armv7/Makefile
index 653eef8..99cf9eb 100644
--- a/arch/arm/cpu/armv7/Makefile
+++ b/arch/arm/cpu/armv7/Makefile
@@ -37,7 +37,6 @@
obj-$(if $(filter bcmcygnus,$(SOC)),y) += bcmcygnus/
obj-$(if $(filter bcmnsp,$(SOC)),y) += bcmnsp/
obj-$(if $(filter ls102xa,$(SOC)),y) += ls102xa/
-obj-$(if $(filter stv0991,$(SOC)),y) += stv0991/
obj-$(CONFIG_ARCH_SUNXI) += sunxi/
obj-$(CONFIG_VF610) += vf610/
obj-$(CONFIG_ARCH_S5P4418) += s5p4418/
diff --git a/arch/arm/cpu/armv7/stv0991/Makefile b/arch/arm/cpu/armv7/stv0991/Makefile
deleted file mode 100644
index 3be5eba..0000000
--- a/arch/arm/cpu/armv7/stv0991/Makefile
+++ /dev/null
@@ -1,7 +0,0 @@
-# SPDX-License-Identifier: GPL-2.0+
-#
-# Copyright (C) 2014, STMicroelectronics - All Rights Reserved
-# Author(s): Vikas Manocha, <vikas.manocha@st.com> for STMicroelectronics.
-
-obj-y := timer.o clock.o pinmux.o reset.o
-obj-y += lowlevel.o
diff --git a/arch/arm/cpu/armv7/stv0991/clock.c b/arch/arm/cpu/armv7/stv0991/clock.c
deleted file mode 100644
index 1e35dee..0000000
--- a/arch/arm/cpu/armv7/stv0991/clock.c
+++ /dev/null
@@ -1,42 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * Copyright (C) 2014, STMicroelectronics - All Rights Reserved
- * Author(s): Vikas Manocha, <vikas.manocha@st.com> for STMicroelectronics.
- */
-
-#include <asm/io.h>
-#include <asm/arch/hardware.h>
-#include <asm/arch/stv0991_cgu.h>
-#include<asm/arch/stv0991_periph.h>
-
-static struct stv0991_cgu_regs *const stv0991_cgu_regs = \
- (struct stv0991_cgu_regs *) (CGU_BASE_ADDR);
-
-void enable_pll1(void)
-{
- /* pll1 already configured for 1000Mhz, just need to enable it */
- writel(readl(&stv0991_cgu_regs->pll1_ctrl) & ~(0x01),
- &stv0991_cgu_regs->pll1_ctrl);
-}
-
-void clock_setup(int peripheral)
-{
- switch (peripheral) {
- case UART_CLOCK_CFG:
- writel(UART_CLK_CFG, &stv0991_cgu_regs->uart_freq);
- break;
- case ETH_CLOCK_CFG:
- enable_pll1();
- writel(ETH_CLK_CFG, &stv0991_cgu_regs->eth_freq);
-
- /* Clock selection for ethernet tx_clk & rx_clk*/
- writel((readl(&stv0991_cgu_regs->eth_ctrl) & ETH_CLK_MASK)
- | ETH_CLK_CTRL, &stv0991_cgu_regs->eth_ctrl);
- break;
- case QSPI_CLOCK_CFG:
- writel(QSPI_CLK_CTRL, &stv0991_cgu_regs->qspi_freq);
- break;
- default:
- break;
- }
-}
diff --git a/arch/arm/cpu/armv7/stv0991/lowlevel.S b/arch/arm/cpu/armv7/stv0991/lowlevel.S
deleted file mode 100644
index 5733eaa1..0000000
--- a/arch/arm/cpu/armv7/stv0991/lowlevel.S
+++ /dev/null
@@ -1,11 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0+ */
-/*
- * (C) Copyright 2014 STMicroelectronics
- */
-
-#include <config.h>
-#include <linux/linkage.h>
-
-ENTRY(lowlevel_init)
- mov pc, lr
-ENDPROC(lowlevel_init)
diff --git a/arch/arm/cpu/armv7/stv0991/pinmux.c b/arch/arm/cpu/armv7/stv0991/pinmux.c
deleted file mode 100644
index 6c44ffe..0000000
--- a/arch/arm/cpu/armv7/stv0991/pinmux.c
+++ /dev/null
@@ -1,66 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * Copyright (C) 2014, STMicroelectronics - All Rights Reserved
- * Author(s): Vikas Manocha, <vikas.manocha@st.com> for STMicroelectronics.
- */
-
-#include <asm/io.h>
-#include <asm/arch/stv0991_creg.h>
-#include <asm/arch/stv0991_periph.h>
-#include <asm/arch/hardware.h>
-
-static struct stv0991_creg *const stv0991_creg = \
- (struct stv0991_creg *)CREG_BASE_ADDR;
-
-int stv0991_pinmux_config(int peripheral)
-{
- switch (peripheral) {
- case UART_GPIOC_30_31:
- /* SSDA/SSCL pad muxing to UART Rx/Dx */
- writel((readl(&stv0991_creg->mux12) & GPIOC_31_MUX_MASK) |
- CFG_GPIOC_31_UART_RX,
- &stv0991_creg->mux12);
- writel((readl(&stv0991_creg->mux12) & GPIOC_30_MUX_MASK) |
- CFG_GPIOC_30_UART_TX,
- &stv0991_creg->mux12);
- /* SSDA/SSCL pad config to push pull*/
- writel((readl(&stv0991_creg->cfg_pad6) & GPIOC_31_MODE_MASK) |
- CFG_GPIOC_31_MODE_PP,
- &stv0991_creg->cfg_pad6);
- writel((readl(&stv0991_creg->cfg_pad6) & GPIOC_30_MODE_MASK) |
- CFG_GPIOC_30_MODE_HIGH,
- &stv0991_creg->cfg_pad6);
- break;
- case UART_GPIOB_16_17:
- /* ethernet rx_6/7 to UART Rx/Dx */
- writel((readl(&stv0991_creg->mux7) & GPIOB_17_MUX_MASK) |
- CFG_GPIOB_17_UART_RX,
- &stv0991_creg->mux7);
- writel((readl(&stv0991_creg->mux7) & GPIOB_16_MUX_MASK) |
- CFG_GPIOB_16_UART_TX,
- &stv0991_creg->mux7);
- break;
- case ETH_GPIOB_10_31_C_0_4:
- writel(readl(&stv0991_creg->mux6) & 0x000000FF,
- &stv0991_creg->mux6);
- writel(0x00000000, &stv0991_creg->mux7);
- writel(0x00000000, &stv0991_creg->mux8);
- writel(readl(&stv0991_creg->mux9) & 0xFFF00000,
- &stv0991_creg->mux9);
- /* Ethernet Voltage configuration to 1.8V*/
- writel((readl(&stv0991_creg->vdd_pad1) & VDD_ETH_PS_MASK) |
- ETH_VDD_CFG, &stv0991_creg->vdd_pad1);
- writel((readl(&stv0991_creg->vdd_pad1) & VDD_ETH_PS_MASK) |
- ETH_M_VDD_CFG, &stv0991_creg->vdd_pad1);
-
- break;
- case QSPI_CS_CLK_PAD:
- writel((readl(&stv0991_creg->mux13) & FLASH_CS_NC_MASK) |
- CFG_FLASH_CS_NC, &stv0991_creg->mux13);
- writel((readl(&stv0991_creg->mux13) & FLASH_CLK_MASK) |
- CFG_FLASH_CLK, &stv0991_creg->mux13);
- default:
- break;
- }
- return 0;
-}
diff --git a/arch/arm/cpu/armv7/stv0991/reset.c b/arch/arm/cpu/armv7/stv0991/reset.c
deleted file mode 100644
index 77d4477..0000000
--- a/arch/arm/cpu/armv7/stv0991/reset.c
+++ /dev/null
@@ -1,27 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * Copyright (C) 2014, STMicroelectronics - All Rights Reserved
- * Author(s): Vikas Manocha, <vikas.manocha@st.com> for STMicroelectronics.
- */
-
-#include <common.h>
-#include <cpu_func.h>
-#include <asm/io.h>
-#include <asm/arch/stv0991_wdru.h>
-#include <linux/delay.h>
-void reset_cpu(void)
-{
- puts("System is going to reboot ...\n");
- /*
- * This 1 second delay will allow the above message
- * to be printed before reset
- */
- udelay((1000 * 1000));
-
- /* Setting bit 1 of the WDRU unit will reset the SoC */
- writel(WDRU_RST_SYS, &stv0991_wd_ru_ptr->wdru_ctrl1);
-
- /* system will restart */
- while (1)
- ;
-}
diff --git a/arch/arm/cpu/armv7/stv0991/timer.c b/arch/arm/cpu/armv7/stv0991/timer.c
deleted file mode 100644
index f7cc457..0000000
--- a/arch/arm/cpu/armv7/stv0991/timer.c
+++ /dev/null
@@ -1,114 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * Copyright (C) 2014, STMicroelectronics - All Rights Reserved
- * Author(s): Vikas Manocha, <vikas.manocha@st.com> for STMicroelectronics.
- */
-
-#include <common.h>
-#include <init.h>
-#include <time.h>
-#include <asm/global_data.h>
-#include <asm/io.h>
-#include <asm/arch-stv0991/hardware.h>
-#include <asm/arch-stv0991/stv0991_cgu.h>
-#include <asm/arch-stv0991/stv0991_gpt.h>
-#include <linux/delay.h>
-
-static struct stv0991_cgu_regs *const stv0991_cgu_regs = \
- (struct stv0991_cgu_regs *) (CGU_BASE_ADDR);
-
-#define READ_TIMER() (readl(&gpt1_regs_ptr->cnt) & GPT_FREE_RUNNING)
-#define GPT_RESOLUTION (CFG_SYS_HZ_CLOCK / CONFIG_SYS_HZ)
-
-DECLARE_GLOBAL_DATA_PTR;
-
-#define timestamp gd->arch.tbl
-#define lastdec gd->arch.lastinc
-
-static ulong get_timer_masked(void);
-
-int timer_init(void)
-{
- /* Timer1 clock configuration */
- writel(TIMER1_CLK_CFG, &stv0991_cgu_regs->tim_freq);
- writel(readl(&stv0991_cgu_regs->cgu_enable_2) |
- TIMER1_CLK_EN, &stv0991_cgu_regs->cgu_enable_2);
-
- /* Stop the timer */
- writel(readl(&gpt1_regs_ptr->cr1) & ~GPT_CR1_CEN, &gpt1_regs_ptr->cr1);
- writel(GPT_PRESCALER_128, &gpt1_regs_ptr->psc);
- /* Configure timer for auto-reload */
- writel(readl(&gpt1_regs_ptr->cr1) | GPT_MODE_AUTO_RELOAD,
- &gpt1_regs_ptr->cr1);
-
- /* load value for free running */
- writel(GPT_FREE_RUNNING, &gpt1_regs_ptr->arr);
-
- /* start timer */
- writel(readl(&gpt1_regs_ptr->cr1) | GPT_CR1_CEN,
- &gpt1_regs_ptr->cr1);
-
- /* Reset the timer */
- lastdec = READ_TIMER();
- timestamp = 0;
-
- return 0;
-}
-
-/*
- * timer without interrupts
- */
-ulong get_timer(ulong base)
-{
- return (get_timer_masked() / GPT_RESOLUTION) - base;
-}
-
-void __udelay(unsigned long usec)
-{
- ulong tmo;
- ulong start = get_timer_masked();
- ulong tenudelcnt = CFG_SYS_HZ_CLOCK / (1000 * 100);
- ulong rndoff;
-
- rndoff = (usec % 10) ? 1 : 0;
-
- /* tenudelcnt timer tick gives 10 microsecconds delay */
- tmo = ((usec / 10) + rndoff) * tenudelcnt;
-
- while ((ulong) (get_timer_masked() - start) < tmo)
- ;
-}
-
-static ulong get_timer_masked(void)
-{
- ulong now = READ_TIMER();
-
- if (now >= lastdec) {
- /* normal mode */
- timestamp += now - lastdec;
- } else {
- /* we have an overflow ... */
- timestamp += now + GPT_FREE_RUNNING - lastdec;
- }
- lastdec = now;
-
- return timestamp;
-}
-
-/*
- * This function is derived from PowerPC code (read timebase as long long).
- * On ARM it just returns the timer value.
- */
-unsigned long long get_ticks(void)
-{
- return get_timer(0);
-}
-
-/*
- * This function is derived from PowerPC code (timebase clock frequency).
- * On ARM it returns the number of timer ticks per second.
- */
-ulong get_tbclk(void)
-{
- return CONFIG_SYS_HZ;
-}
diff --git a/arch/arm/cpu/armv8/cache.S b/arch/arm/cpu/armv8/cache.S
index 3fe935c..c9e4685 100644
--- a/arch/arm/cpu/armv8/cache.S
+++ b/arch/arm/cpu/armv8/cache.S
@@ -20,6 +20,7 @@
*
* x0: cache level
* x1: 0 clean & invalidate, 1 invalidate only
+ * x16: FEAT_CCIDX
* x2~x9: clobbered
*/
.pushsection .text.__asm_dcache_level, "ax"
@@ -29,8 +30,14 @@
isb /* sync change of cssidr_el1 */
mrs x6, ccsidr_el1 /* read the new cssidr_el1 */
ubfx x2, x6, #0, #3 /* x2 <- log2(cache line size)-4 */
+ cbz x16, 3f /* check for FEAT_CCIDX */
+ ubfx x3, x6, #3, #21 /* x3 <- number of cache ways - 1 */
+ ubfx x4, x6, #32, #24 /* x4 <- number of cache sets - 1 */
+ b 4f
+3:
ubfx x3, x6, #3, #10 /* x3 <- number of cache ways - 1 */
ubfx x4, x6, #13, #15 /* x4 <- number of cache sets - 1 */
+4:
add x2, x2, #4 /* x2 <- log2(cache line size) */
clz w5, w3 /* bit position of #ways */
/* x12 <- cache level << 1 */
@@ -74,6 +81,8 @@
ubfx x11, x10, #24, #3 /* x11 <- loc */
cbz x11, finished /* if loc is 0, exit */
mov x15, lr
+ mrs x16, s3_0_c0_c7_2 /* read value of id_aa64mmfr2_el1*/
+ ubfx x16, x16, #20, #4 /* save FEAT_CCIDX identifier in x16 */
mov x0, #0 /* start flush at cache level 0 */
/* x0 <- cache level */
/* x10 <- clidr_el1 */
diff --git a/arch/arm/cpu/armv8/cache_v8.c b/arch/arm/cpu/armv8/cache_v8.c
index 6973340..57d06f0 100644
--- a/arch/arm/cpu/armv8/cache_v8.c
+++ b/arch/arm/cpu/armv8/cache_v8.c
@@ -326,6 +326,8 @@
/* Going one level down */
if (pte_type(&table[i]) == PTE_TYPE_FAULT)
set_pte_table(&table[i], create_table());
+ else if (pte_type(&table[i]) != PTE_TYPE_TABLE)
+ split_block(&table[i], level);
next_table = (u64 *)(table[i] & GENMASK_ULL(47, PAGE_SHIFT));
next_size = min(map_size - (virt & (map_size - 1)), size);
diff --git a/arch/arm/cpu/armv8/u-boot-spl.lds b/arch/arm/cpu/armv8/u-boot-spl.lds
index 7cb9d73..ef8af67 100644
--- a/arch/arm/cpu/armv8/u-boot-spl.lds
+++ b/arch/arm/cpu/armv8/u-boot-spl.lds
@@ -21,9 +21,9 @@
ENTRY(_start)
SECTIONS
{
+ __image_copy_start = ADDR(.text);
.text : {
. = ALIGN(8);
- __image_copy_start = .;
CPUDIR/start.o (.text*)
*(.text*)
} >.sram
@@ -51,10 +51,8 @@
KEEP(*(SORT(__u_boot_list*)));
} >.sram
- .image_copy_end : {
- . = ALIGN(8);
- *(.__image_copy_end)
- } >.sram
+ . = ALIGN(8);
+ __image_copy_end = .;
.end : {
. = ALIGN(8);
@@ -63,18 +61,11 @@
_image_binary_end = .;
- .bss_start (NOLOAD) : {
- . = ALIGN(8);
- KEEP(*(.__bss_start));
- } >.sdram
-
- .bss (NOLOAD) : {
+ .bss : {
+ __bss_start = .;
*(.bss*)
- . = ALIGN(8);
- } >.sdram
-
- .bss_end (NOLOAD) : {
- KEEP(*(.__bss_end));
+ . = ALIGN(8);
+ __bss_end = .;
} >.sdram
/DISCARD/ : { *(.rela*) }
@@ -89,3 +80,6 @@
#include "linux-kernel-image-header-vars.h"
#endif
}
+
+ASSERT(ADDR(.bss) % 8 == 0, \
+ ".bss must be 8-byte aligned");
diff --git a/arch/arm/cpu/armv8/u-boot.lds b/arch/arm/cpu/armv8/u-boot.lds
index fb6a30c..857f444 100644
--- a/arch/arm/cpu/armv8/u-boot.lds
+++ b/arch/arm/cpu/armv8/u-boot.lds
@@ -21,9 +21,9 @@
. = 0x00000000;
. = ALIGN(8);
+ __image_copy_start = ADDR(.text);
.text :
{
- *(.__image_copy_start)
CPUDIR/start.o (.text*)
}
@@ -115,8 +115,6 @@
KEEP(*(SORT(__u_boot_list*)));
}
- . = ALIGN(8);
-
.efi_runtime_rel : {
__efi_runtime_rel_start = .;
*(.rel*.efi_runtime)
@@ -125,43 +123,24 @@
}
. = ALIGN(8);
-
- .image_copy_end :
- {
- *(.__image_copy_end)
- }
-
- . = ALIGN(8);
-
- .rel_dyn_start :
- {
- *(.__rel_dyn_start)
- }
+ __image_copy_end = .;
.rela.dyn : {
+ __rel_dyn_start = .;
*(.rela*)
+ __rel_dyn_end = .;
}
- .rel_dyn_end :
- {
- *(.__rel_dyn_end)
- }
-
_end = .;
- . = ALIGN(8);
-
- .bss_start : {
- KEEP(*(.__bss_start));
- }
-
- .bss : {
+ /*
+ * arch/arm/lib/crt0_64.S assumes __bss_start - __bss_end % 8 == 0
+ */
+ .bss ALIGN(8) : {
+ __bss_start = .;
*(.bss*)
- . = ALIGN(8);
- }
-
- .bss_end : {
- KEEP(*(.__bss_end));
+ . = ALIGN(8);
+ __bss_end = .;
}
/DISCARD/ : { *(.dynsym) }
diff --git a/arch/arm/cpu/u-boot-spl.lds b/arch/arm/cpu/u-boot-spl.lds
index fb2189d..9ed6239 100644
--- a/arch/arm/cpu/u-boot-spl.lds
+++ b/arch/arm/cpu/u-boot-spl.lds
@@ -14,9 +14,9 @@
. = 0x00000000;
. = ALIGN(4);
+ __image_copy_start = ADDR(.text);
.text :
{
- __image_copy_start = .;
*(.vectors)
CPUDIR/start.o (.text*)
*(.text*)
diff --git a/arch/arm/cpu/u-boot.lds b/arch/arm/cpu/u-boot.lds
index 7724c93..707b197 100644
--- a/arch/arm/cpu/u-boot.lds
+++ b/arch/arm/cpu/u-boot.lds
@@ -35,28 +35,22 @@
. = 0x00000000;
. = ALIGN(4);
+ __image_copy_start = ADDR(.text);
.text :
{
- *(.__image_copy_start)
*(.vectors)
CPUDIR/start.o (.text*)
}
/* This needs to come before *(.text*) */
- .__efi_runtime_start : {
- *(.__efi_runtime_start)
- }
-
.efi_runtime : {
+ __efi_runtime_start = .;
*(.text.efi_runtime*)
*(.rodata.efi_runtime*)
*(.data.efi_runtime*)
+ __efi_runtime_stop = .;
}
- .__efi_runtime_stop : {
- *(.__efi_runtime_stop)
- }
-
.text_rest :
{
*(.text*)
@@ -152,42 +146,24 @@
KEEP(*(SORT(__u_boot_list*)));
}
- . = ALIGN(4);
-
- .efi_runtime_rel_start :
- {
- *(.__efi_runtime_rel_start)
- }
-
.efi_runtime_rel : {
+ __efi_runtime_rel_start = .;
*(.rel*.efi_runtime)
*(.rel*.efi_runtime.*)
+ __efi_runtime_rel_stop = .;
}
- .efi_runtime_rel_stop :
- {
- *(.__efi_runtime_rel_stop)
- }
-
. = ALIGN(4);
-
- .image_copy_end :
- {
- *(.__image_copy_end)
- }
-
- .rel_dyn_start :
- {
- *(.__rel_dyn_start)
- }
+ __image_copy_end = .;
- .rel.dyn : {
+ /*
+ * if CONFIG_USE_ARCH_MEMSET is not selected __bss_end - __bss_start
+ * needs to be a multiple of 4 and we overlay .bss with .rel.dyn
+ */
+ .rel.dyn ALIGN(4) : {
+ __rel_dyn_start = .;
*(.rel*)
- }
-
- .rel_dyn_end :
- {
- *(.__rel_dyn_end)
+ __rel_dyn_end = .;
}
.end :
@@ -207,23 +183,15 @@
}
/*
- * Compiler-generated __bss_start and __bss_end, see arch/arm/lib/bss.c
- * __bss_base and __bss_limit are for linker only (overlay ordering)
+ * These sections occupy the same memory, but their lifetimes do
+ * not overlap: U-Boot initializes .bss only after applying dynamic
+ * relocations and therefore after it doesn't need .rel.dyn any more.
*/
-
- .bss_start __rel_dyn_start (OVERLAY) : {
- KEEP(*(.__bss_start));
- __bss_base = .;
- }
-
- .bss __bss_base (OVERLAY) : {
+ .bss ADDR(.rel.dyn) (OVERLAY): {
+ __bss_start = .;
*(.bss*)
- . = ALIGN(4);
- __bss_limit = .;
- }
-
- .bss_end __bss_limit (OVERLAY) : {
- KEEP(*(.__bss_end));
+ . = ALIGN(4);
+ __bss_end = .;
}
.dynsym _image_binary_end : { *(.dynsym) }
diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile
index a965a70..2634bb4 100644
--- a/arch/arm/dts/Makefile
+++ b/arch/arm/dts/Makefile
@@ -47,33 +47,7 @@
dtb-$(CONFIG_ARCH_KIRKWOOD) += \
kirkwood-atl-sbx81lifkw.dtb \
- kirkwood-atl-sbx81lifxcat.dtb \
- kirkwood-blackarmor-nas220.dtb \
- kirkwood-d2net.dtb \
- kirkwood-dns325.dtb \
- kirkwood-dockstar.dtb \
- kirkwood-dreamplug.dtb \
- kirkwood-ds109.dtb \
- kirkwood-goflexnet.dtb \
- kirkwood-guruplug-server-plus.dtb \
- kirkwood-ib62x0.dtb \
- kirkwood-iconnect.dtb \
- kirkwood-is2.dtb \
- kirkwood-lsxhl.dtb \
- kirkwood-lschlv2.dtb \
- kirkwood-net2big.dtb \
- kirkwood-ns2.dtb \
- kirkwood-ns2lite.dtb \
- kirkwood-ns2max.dtb \
- kirkwood-ns2mini.dtb \
- kirkwood-nsa310s.dtb \
- kirkwood-nsa325.dtb \
- kirkwood-openrd-base.dtb \
- kirkwood-openrd-client.dtb \
- kirkwood-openrd-ultimate.dtb \
- kirkwood-pogo_e02.dtb \
- kirkwood-pogoplug-series-4.dtb \
- kirkwood-sheevaplug.dtb
+ kirkwood-atl-sbx81lifxcat.dtb
dtb-$(CONFIG_MACH_S900) += \
bubblegum_96.dtb
@@ -174,6 +148,8 @@
dtb-$(CONFIG_ROCKCHIP_RK3568) += \
rk3566-anbernic-rgxx3.dtb \
+ rk3566-pinetab2-v0.1.dtb \
+ rk3566-pinetab2-v2.0.dtb \
rk3566-quartz64-a.dtb \
rk3566-quartz64-b.dtb \
rk3566-radxa-cm3-io.dtb \
@@ -191,16 +167,20 @@
rk3568-rock-3a.dtb
dtb-$(CONFIG_ROCKCHIP_RK3588) += \
+ rk3588s-coolpi-4b.dts \
+ rk3588-coolpi-cm5-evb.dts \
rk3588-edgeble-neu6a-io.dtb \
rk3588-edgeble-neu6b-io.dtb \
rk3588-evb1-v10.dtb \
+ rk3588-generic.dtb \
+ rk3588-jaguar.dtb \
rk3588-nanopc-t6.dtb \
rk3588s-orangepi-5.dtb \
rk3588-orangepi-5-plus.dtb \
rk3588-quartzpro64.dtb \
- rk3588-turing-rk1.dtb \
rk3588s-rock-5a.dtb \
- rk3588-rock-5b.dtb
+ rk3588-rock-5b.dtb \
+ rk3588-turing-rk1.dtb
dtb-$(CONFIG_ROCKCHIP_RV1108) += \
rv1108-elgin-r1.dtb \
@@ -213,40 +193,8 @@
s5p4418-nanopi2.dtb
dtb-$(CONFIG_ARCH_MESON) += \
- meson-a1-ad401.dtb \
- meson-axg-s400.dtb \
- meson-axg-jethome-jethub-j100.dtb \
- meson-gxl-s805x-libretech-ac.dtb \
- meson-gxl-s905d-libretech-pc.dtb \
- meson-gxl-s905w-jethome-jethub-j80.dtb \
- meson-gxl-s905x-khadas-vim.dtb \
- meson-gxl-s905x-libretech-cc.dtb \
- meson-gxl-s905x-libretech-cc-v2.dtb \
- meson-gxl-s905x-p212.dtb \
- meson-gxm-gt1-ultimate.dtb \
- meson-gxm-khadas-vim2.dtb \
- meson-gxm-s912-libretech-pc.dtb \
- meson-gxm-wetek-core2.dtb \
- meson-g12a-radxa-zero.dtb \
- meson-g12a-sei510.dtb \
- meson-g12a-u200.dtb \
- meson-g12b-a311d-bananapi-m2s.dtb \
- meson-g12b-a311d-khadas-vim3.dtb \
- meson-g12b-bananapi-cm4-cm4io.dtb \
- meson-g12b-gsking-x.dtb \
- meson-g12b-gtking.dtb \
- meson-g12b-gtking-pro.dtb \
- meson-g12b-odroid-go-ultra.dtb \
- meson-g12b-odroid-n2.dtb \
- meson-g12b-odroid-n2l.dtb \
- meson-g12b-odroid-n2-plus.dtb \
- meson-g12b-radxa-zero2.dtb \
- meson-sm1-bananapi-m2-pro.dtb \
- meson-sm1-bananapi-m5.dtb \
- meson-sm1-khadas-vim3l.dtb \
- meson-sm1-odroid-c4.dtb \
- meson-sm1-odroid-hc4.dtb \
- meson-sm1-sei610.dtb
+ meson-a1-ad401.dtb
+
dtb-$(CONFIG_ARCH_TEGRA) += tegra20-harmony.dtb \
tegra20-medcom-wide.dtb \
tegra20-paz00.dtb \
@@ -540,6 +488,7 @@
dtb-$(CONFIG_ARCH_SOCFPGA) += \
socfpga_agilex_socdk.dtb \
+ socfpga_agilex5_socdk.dtb \
socfpga_arria5_secu1.dtb \
socfpga_arria5_socdk.dtb \
socfpga_arria10_chameleonv3_270_2.dtb \
@@ -569,7 +518,6 @@
am574x-idk.dtb \
am572x-idk.dtb \
am571x-idk.dtb
-dtb-$(CONFIG_TARGET_STV0991) += stv0991.dtb
dtb-$(CONFIG_ARCH_LS1021A) += ls1021a-qds-duart.dtb \
ls1021a-qds-lpuart.dtb \
@@ -1068,7 +1016,6 @@
dtb-$(CONFIG_ARCH_IMX8M) += \
imx8mm-data-modul-edm-sbc.dtb \
- imx8mm-evk.dtb \
imx8mm-icore-mx8mm-ctouch2.dtb \
imx8mm-icore-mx8mm-edimm2.2.dtb \
imx8mm-kontron-bl.dtb \
@@ -1077,30 +1024,12 @@
imx8mm-phg.dtb \
imx8mm-phyboard-polis-rdk.dtb \
imx8mm-phygate-tauri-l.dtb \
- imx8mm-venice.dtb \
- imx8mm-venice-gw71xx-0x.dtb \
- imx8mm-venice-gw72xx-0x.dtb \
- imx8mm-venice-gw73xx-0x.dtb \
- imx8mm-venice-gw7901.dtb \
- imx8mm-venice-gw7902.dtb \
- imx8mm-venice-gw7903.dtb \
- imx8mm-venice-gw7904.dtb \
- imx8mm-venice-gw7905-0x.dtb \
- imx8mm-verdin-wifi-dev.dtb \
imx8mn-bsh-smm-s2.dtb \
imx8mn-bsh-smm-s2pro.dtb \
- imx8mn-ddr4-evk.dtb \
imx8mq-cm.dtb \
- imx8mn-evk.dtb \
imx8mn-var-som-symphony.dtb \
- imx8mn-venice.dtb \
- imx8mn-venice-gw7902.dtb \
- imx8mq-evk.dtb \
- imx8mm-beacon-kit.dtb \
- imx8mn-beacon-kit.dtb \
imx8mq-mnt-reform2.dtb \
imx8mq-phanbell.dtb \
- imx8mp-beacon-kit.dtb \
imx8mp-data-modul-edm-sbc.dtb \
imx8mp-dhcom-som-overlay-rev100.dtbo \
imx8mp-dhcom-som-overlay-eth1xfast.dtbo \
@@ -1110,17 +1039,9 @@
imx8mp-dhcom-pdk2.dtb \
imx8mp-dhcom-pdk3.dtb \
imx8mp-dhcom-pdk3-overlay-rev100.dtbo \
- imx8mp-evk.dtb \
imx8mp-icore-mx8mp-edimm2.2.dtb \
imx8mp-msc-sm2s.dtb \
imx8mp-phyboard-pollux-rdk.dtb \
- imx8mp-venice.dtb \
- imx8mp-venice-gw71xx-2x.dtb \
- imx8mp-venice-gw72xx-2x.dtb \
- imx8mp-venice-gw73xx-2x.dtb \
- imx8mp-venice-gw74xx.dtb \
- imx8mp-venice-gw7905-2x.dtb \
- imx8mp-verdin-wifi-dev.dtb \
imx8mq-pico-pi.dtb \
imx8mq-kontron-pitx-imx8m.dtb \
imx8mq-librem5-r4.dtb
@@ -1260,6 +1181,9 @@
dtb-$(CONFIG_TARGET_SAMA7G5EK) += \
at91-sama7g5ek.dtb
+dtb-$(CONFIG_TARGET_SAMA7G54_CURIOSITY) += \
+ at91-sama7g54_curiosity.dtb
+
dtb-$(CONFIG_TARGET_SAMA5D2_PTC_EK) += \
at91-sama5d2_ptc_ek.dtb
@@ -1359,7 +1283,9 @@
bcm96878.dtb
dtb-$(CONFIG_ASPEED_AST2500) += ast2500-evb.dtb
-dtb-$(CONFIG_ASPEED_AST2600) += ast2600-evb.dtb
+dtb-$(CONFIG_ASPEED_AST2600) += \
+ ast2600-evb.dtb \
+ ast2600-x4tf.dtb
dtb-$(CONFIG_ARCH_STI) += stih410-b2260.dtb
@@ -1418,9 +1344,7 @@
dtb-$(CONFIG_SOC_K3_J784S4) += k3-am69-r5-sk.dtb \
k3-j784s4-r5-evm.dtb
-dtb-$(CONFIG_SOC_K3_AM642) += k3-am642-evm.dtb \
- k3-am642-r5-evm.dtb \
- k3-am642-sk.dtb \
+dtb-$(CONFIG_SOC_K3_AM642) += k3-am642-r5-evm.dtb \
k3-am642-r5-sk.dtb \
k3-am642-phyboard-electra-rdk.dtb \
k3-am642-r5-phycore-som-2gb.dtb
diff --git a/arch/arm/dts/ast2600-x4tf.dts b/arch/arm/dts/ast2600-x4tf.dts
new file mode 100644
index 0000000..4bf4b66
--- /dev/null
+++ b/arch/arm/dts/ast2600-x4tf.dts
@@ -0,0 +1,161 @@
+// SPDX-License-Identifier: GPL-2.0+
+// Copyright 2024 ASUS Corp.
+/dts-v1/;
+
+#include "ast2600-u-boot.dtsi"
+
+/ {
+ model = "AST2600 ASUS X4TF";
+ compatible = "aspeed,ast2600-asus", "aspeed,ast2600";
+
+ memory {
+ device_type = "memory";
+ reg = <0x80000000 0x20000000>;
+ };
+
+ chosen {
+ stdout-path = &uart5;
+ };
+
+ aliases {
+ spi0 = &fmc;
+ ethernet0 = &mac2;
+ ethernet1 = &mac3;
+ };
+
+ cpus {
+ cpu@0 {
+ clock-frequency = <800000000>;
+ };
+
+ cpu@1 {
+ clock-frequency = <800000000>;
+ };
+ };
+};
+
+&uart5 {
+ status = "okay";
+};
+
+&sdrammc {
+ clock-frequency = <400000000>;
+};
+
+&wdt1 {
+ status = "okay";
+};
+
+&wdt2 {
+ status = "okay";
+};
+
+&wdt3 {
+ status = "okay";
+};
+
+&mac2 {
+ status = "okay";
+ phy-mode = "rmii";
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_rmii3_default>;
+};
+
+&mac3 {
+ status = "okay";
+ phy-mode = "rmii";
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_rmii4_default>;
+};
+
+&fmc {
+ status = "okay";
+
+ flash@0 {
+ compatible = "jedec,spi-nor", "macronix,mx66l2g45g";
+ status = "okay";
+ spi-max-frequency = <25000000>;
+ spi-tx-bus-width = <2>;
+ spi-rx-bus-width = <2>;
+ };
+
+ flash@1 {
+ compatible = "spi-flash", "sst,w25q256";
+ status = "okay";
+ spi-max-frequency = <25000000>;
+ spi-tx-bus-width = <4>;
+ spi-rx-bus-width = <4>;
+ };
+};
+
+&hace {
+ status = "okay";
+};
+
+&i2c0 {
+ status = "okay";
+};
+
+&i2c1 {
+ status = "okay";
+};
+
+&i2c2 {
+ status = "okay";
+};
+
+&i2c3 {
+ status = "okay";
+};
+
+&i2c4 {
+ status = "okay";
+};
+
+&i2c5 {
+ status = "okay";
+};
+
+&i2c6 {
+ status = "okay";
+};
+
+&i2c7 {
+ status = "okay";
+};
+
+&i2c8 {
+ status = "okay";
+};
+
+&i2c9 {
+ status = "okay";
+};
+
+&i2c10 {
+ status = "okay";
+};
+
+&i2c11 {
+ status = "okay";
+};
+
+&i2c12 {
+ status = "disabled";
+};
+
+&i2c13 {
+ status = "disabled";
+};
+
+&i2c14 {
+ status = "okay";
+};
+
+&i2c15 {
+ status = "okay";
+};
+
+&display_port {
+ status = "okay";
+};
diff --git a/arch/arm/dts/at91-sama7g54_curiosity-u-boot.dtsi b/arch/arm/dts/at91-sama7g54_curiosity-u-boot.dtsi
new file mode 100644
index 0000000..04d7d9e
--- /dev/null
+++ b/arch/arm/dts/at91-sama7g54_curiosity-u-boot.dtsi
@@ -0,0 +1,59 @@
+// SPDX-License-Identifier: GPL-2.0+ OR MIT
+/*
+ * at91-sama7g54_curiosity-u-boot.dtsi - Device Tree file for SAMA7G5 SoC u-boot properties.
+ *
+ * Copyright (C) 2024 Microchip Technology Inc. and its subsidiaries
+ *
+ * Author: Mihai Sain <mihai.sain@microchip.com>
+ *
+ */
+
+/ {
+ chosen {
+ bootph-all;
+ };
+};
+
+&main_rc {
+ bootph-all;
+};
+
+&main_xtal {
+ bootph-all;
+};
+
+&pioA {
+ bootph-all;
+};
+
+&pinctrl_flx3_default {
+ bootph-all;
+};
+
+&pinctrl_sdmmc1_default {
+ bootph-all;
+};
+
+&pit64b0 {
+ bootph-all;
+};
+
+&pmc {
+ bootph-all;
+};
+
+&sdmmc1 {
+ bootph-all;
+};
+
+&slow_rc_osc {
+ bootph-all;
+};
+
+&slow_xtal {
+ bootph-all;
+};
+
+&uart3 {
+ bootph-all;
+};
diff --git a/arch/arm/dts/at91-sama7g54_curiosity.dts b/arch/arm/dts/at91-sama7g54_curiosity.dts
new file mode 100644
index 0000000..93c230b
--- /dev/null
+++ b/arch/arm/dts/at91-sama7g54_curiosity.dts
@@ -0,0 +1,242 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * at91-sama7g54_curiosity.dts - Device Tree file for SAMA7G54 CURIOSITY board
+ *
+ * Copyright (C) 2024 Microchip Technology Inc. and its subsidiaries
+ *
+ * Author: Mihai Sain <mihai.sain@microchip.com>
+ *
+ */
+/dts-v1/;
+#include "sama7g5-pinfunc.h"
+#include "sama7g5.dtsi"
+#include <dt-bindings/input/input.h>
+#include <dt-bindings/mfd/atmel-flexcom.h>
+#include <dt-bindings/pinctrl/at91.h>
+
+/ {
+ model = "Microchip SAMA7G54 Curiosity";
+ compatible = "microchip,sama7g54-curiosity", "microchip,sama7g5", "microchip,sama7";
+
+ aliases {
+ serial0 = &uart3;
+ i2c0 = &i2c10;
+ };
+
+ chosen {
+ bootargs = "console=ttyS0,115200 root=/dev/mmcblk1p2 rw rootwait";
+ stdout-path = "serial0:115200n8";
+ };
+
+ clocks {
+ slow_xtal {
+ clock-frequency = <32768>;
+ };
+
+ main_xtal {
+ clock-frequency = <24000000>;
+ };
+ };
+
+ leds {
+ compatible = "gpio-leds";
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_led_gpio_default>;
+
+ led-red {
+ label = "red";
+ gpios = <&pioA PIN_PD13 GPIO_ACTIVE_HIGH>;
+ default-state = "off";
+ };
+
+ led-green {
+ label = "green";
+ gpios = <&pioA PIN_PD14 GPIO_ACTIVE_HIGH>;
+ default-state = "off";
+ };
+
+ led-blue {
+ label = "blue";
+ gpios = <&pioA PIN_PB15 GPIO_ACTIVE_HIGH>;
+ default-state = "on";
+ };
+ };
+
+ memory {
+ device_type = "memory";
+ reg = <0x60000000 0x10000000>; // 256 MiB DDR3L-1066 16-bit
+ };
+};
+
+&ebi {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_nand_default>;
+ status = "okay";
+
+ nand_controller: nand-controller {
+ status = "okay";
+
+ nand@3 {
+ reg = <0x3 0x0 0x800000>;
+ atmel,rb = <0>;
+ nand-bus-width = <8>;
+ nand-ecc-mode = "hw";
+ nand-ecc-strength = <8>;
+ nand-ecc-step-size = <512>;
+ nand-on-flash-bbt;
+ };
+ };
+};
+
+&flx3 {
+ atmel,flexcom-mode = <ATMEL_FLEXCOM_MODE_USART>;
+ status = "okay";
+
+ uart3: serial@200 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_flx3_default>;
+ status = "okay";
+ };
+};
+
+&flx10 {
+ atmel,flexcom-mode = <ATMEL_FLEXCOM_MODE_TWI>;
+ status = "okay";
+
+ i2c10: i2c@600 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_flx10_default>;
+ i2c-analog-filter;
+ i2c-digital-filter;
+ i2c-digital-filter-width-ns = <35>;
+ status = "okay";
+
+ adc@1f {
+ compatible = "microchip,pac1934";
+ reg = <0x1f>;
+ };
+
+ eeprom@51 {
+ compatible = "atmel,24c02";
+ reg = <0x51>;
+ pagesize = <16>;
+ size = <256>;
+ };
+
+ pmic@5b {
+ compatible = "microchip,mcp16502";
+ reg = <0x5b>;
+ };
+ };
+};
+
+&pioA {
+ pinctrl_flx3_default: flx3-default {
+ pinmux = <PIN_PD16__FLEXCOM3_IO0>,
+ <PIN_PD17__FLEXCOM3_IO1>;
+ bias-pull-up;
+ };
+
+ pinctrl_flx10_default: flx10-default {
+ pinmux = <PIN_PC30__FLEXCOM10_IO0>,
+ <PIN_PC31__FLEXCOM10_IO1>;
+ bias-pull-up;
+ };
+
+ pinctrl_led_gpio_default: led-gpio-default {
+ pinmux = <PIN_PD13__GPIO>,
+ <PIN_PD14__GPIO>,
+ <PIN_PB15__GPIO>;
+ bias-pull-up;
+ };
+
+ pinctrl_nand_default: nand-default {
+ pinmux = <PIN_PD9__D0>,
+ <PIN_PD10__D1>,
+ <PIN_PD11__D2>,
+ <PIN_PC21__D3>,
+ <PIN_PC22__D4>,
+ <PIN_PC23__D5>,
+ <PIN_PC24__D6>,
+ <PIN_PD2__D7>,
+ <PIN_PD3__NANDRDY>,
+ <PIN_PD4__NCS3_NANDCS>,
+ <PIN_PD5__NWE_NWR0_NANDWE>,
+ <PIN_PD6__NRD_NANDOE>,
+ <PIN_PD7__A21_NANDALE>,
+ <PIN_PD8__A22_NANDCLE>;
+ bias-disable;
+ slew-rate = <0>;
+ };
+
+ pinctrl_qspi1_default: qspi1-default {
+ pinmux = <PIN_PB22__QSPI1_IO3>,
+ <PIN_PB23__QSPI1_IO2>,
+ <PIN_PB24__QSPI1_IO1>,
+ <PIN_PB25__QSPI1_IO0>,
+ <PIN_PB26__QSPI1_CS>,
+ <PIN_PB27__QSPI1_SCK>;
+ bias-pull-up;
+ slew-rate = <0>;
+ };
+
+ pinctrl_sdmmc0_default: sdmmc0-default {
+ pinmux = <PIN_PA0__SDMMC0_CK>,
+ <PIN_PA1__SDMMC0_CMD>,
+ <PIN_PA2__SDMMC0_RSTN>,
+ <PIN_PA3__SDMMC0_DAT0>,
+ <PIN_PA4__SDMMC0_DAT1>,
+ <PIN_PA5__SDMMC0_DAT2>,
+ <PIN_PA6__SDMMC0_DAT3>;
+ bias-pull-up;
+ slew-rate = <0>;
+ };
+
+ pinctrl_sdmmc1_default: sdmmc1-default {
+ pinmux = <PIN_PB29__SDMMC1_CMD>,
+ <PIN_PB30__SDMMC1_CK>,
+ <PIN_PB31__SDMMC1_DAT0>,
+ <PIN_PC0__SDMMC1_DAT1>,
+ <PIN_PC1__SDMMC1_DAT2>,
+ <PIN_PC2__SDMMC1_DAT3>,
+ <PIN_PC4__SDMMC1_CD>;
+ bias-pull-up;
+ slew-rate = <0>;
+ };
+};
+
+&qspi1 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_qspi1_default>;
+ status = "okay";
+
+ flash@0 {
+ compatible = "jedec,spi-nor";
+ reg = <0x0>;
+ spi-max-frequency = <100000000>;
+ spi-tx-bus-width = <4>;
+ spi-rx-bus-width = <4>;
+ m25p,fast-read;
+ };
+};
+
+// M.2 slot for wireless card
+&sdmmc0 {
+ bus-width = <4>;
+ cd-gpios = <&pioA 31 GPIO_ACTIVE_LOW>;
+ disable-wp;
+ max-frequency = <50000000>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_sdmmc0_default>;
+ status = "okay";
+};
+
+// micro SD socket
+&sdmmc1 {
+ bus-width = <4>;
+ disable-wp;
+ max-frequency = <50000000>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_sdmmc1_default>;
+ status = "okay";
+};
diff --git a/arch/arm/dts/imx6qdl-hummingboard2-emmc-som-v15-u-boot.dtsi b/arch/arm/dts/imx6qdl-hummingboard2-emmc-som-v15-u-boot.dtsi
index 23a0577..358cf8a 100644
--- a/arch/arm/dts/imx6qdl-hummingboard2-emmc-som-v15-u-boot.dtsi
+++ b/arch/arm/dts/imx6qdl-hummingboard2-emmc-som-v15-u-boot.dtsi
@@ -1,6 +1,7 @@
// SPDX-License-Identifier: GPL-2.0+
#include "imx6qdl-u-boot.dtsi"
+#include "imx6qdl-sr-som-u-boot.dtsi"
/ {
board-detect {
@@ -13,6 +14,12 @@
&gpio6 4 0
>;
};
+
+ wdt-reboot {
+ compatible = "wdt-reboot";
+ wdt = <&wdog1>;
+ bootph-pre-ram;
+ };
};
&soc {
@@ -58,3 +65,7 @@
&usdhc3 {
bootph-all;
};
+
+&wdog1 {
+ bootph-pre-ram;
+};
diff --git a/arch/arm/dts/imx6qdl-sr-som-u-boot.dtsi b/arch/arm/dts/imx6qdl-sr-som-u-boot.dtsi
new file mode 100644
index 0000000..0bd7df0
--- /dev/null
+++ b/arch/arm/dts/imx6qdl-sr-som-u-boot.dtsi
@@ -0,0 +1,49 @@
+// SPDX-License-Identifier: (GPL-2.0 OR MIT)
+
+#include <dt-bindings/gpio/gpio.h>
+
+&fec {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_microsom_enet_ar8035>;
+ phy-handle = <&phy>;
+ phy-mode = "rgmii-id";
+
+ /*
+ * The PHY seems to require a long-enough reset duration to avoid
+ * some rare issues where the PHY gets stuck in an inconsistent and
+ * non-functional state at boot-up. 10ms proved to be fine .
+ */
+ phy-reset-duration = <10>;
+ phy-reset-gpios = <&gpio4 15 GPIO_ACTIVE_LOW>;
+ status = "okay";
+
+ mdio {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ ethernet-phy@0 {
+ status = "disabled";
+ };
+
+ ethernet-phy@1 {
+ status = "disabled";
+ };
+
+ ethernet-phy@4 {
+ status = "disabled";
+ };
+
+ phy: ethernet-phy@ffffffff {
+ /*
+ * The PHY can appear either:
+ * - AR8035: at address 0 or 4
+ * - ADIN1300: at address 1
+ * Actual address being detected at runtime.
+ */
+ reg = <0xffffffff>;
+ qca,clk-out-frequency = <125000000>;
+ qca,smarteee-tw-us-1g = <24>;
+ adi,phy-output-clock = "125mhz-free-running";
+ };
+ };
+};
diff --git a/arch/arm/dts/imx7d-colibri-eval-v3-u-boot.dtsi b/arch/arm/dts/imx7d-colibri-eval-v3-u-boot.dtsi
index 6814276..854bf27 100644
--- a/arch/arm/dts/imx7d-colibri-eval-v3-u-boot.dtsi
+++ b/arch/arm/dts/imx7d-colibri-eval-v3-u-boot.dtsi
@@ -51,3 +51,7 @@
};
};
};
+
+&wdog1 {
+ bootph-pre-ram;
+};
diff --git a/arch/arm/dts/imx7s-warp-u-boot.dtsi b/arch/arm/dts/imx7s-warp-u-boot.dtsi
index 4f44598..98784fd 100644
--- a/arch/arm/dts/imx7s-warp-u-boot.dtsi
+++ b/arch/arm/dts/imx7s-warp-u-boot.dtsi
@@ -7,6 +7,12 @@
chosen {
stdout-path = &uart1;
};
+
+ wdt-reboot {
+ compatible = "wdt-reboot";
+ wdt = <&wdog1>;
+ bootph-pre-ram;
+ };
};
&aips3 {
@@ -24,3 +30,7 @@
&uart1 {
bootph-all;
};
+
+&wdog1 {
+ bootph-pre-ram;
+};
diff --git a/arch/arm/dts/imx8mm-beacon-kit.dts b/arch/arm/dts/imx8mm-beacon-kit.dts
deleted file mode 100644
index 74a7b0c..0000000
--- a/arch/arm/dts/imx8mm-beacon-kit.dts
+++ /dev/null
@@ -1,19 +0,0 @@
-// SPDX-License-Identifier: (GPL-2.0 OR MIT)
-/*
- * Copyright 2020 Compass Electronics Group, LLC
- */
-
-/dts-v1/;
-
-#include "imx8mm.dtsi"
-#include "imx8mm-beacon-som.dtsi"
-#include "imx8mm-beacon-baseboard.dtsi"
-
-/ {
- model = "Beacon EmbeddedWorks i.MX8M Mini Development Kit";
- compatible = "beacon,imx8mm-beacon-kit", "fsl,imx8mm";
-
- chosen {
- stdout-path = &uart2;
- };
-};
diff --git a/arch/arm/dts/imx8mm-beacon-som.dtsi b/arch/arm/dts/imx8mm-beacon-som.dtsi
deleted file mode 100644
index cf07987..0000000
--- a/arch/arm/dts/imx8mm-beacon-som.dtsi
+++ /dev/null
@@ -1,461 +0,0 @@
-// SPDX-License-Identifier: (GPL-2.0 OR MIT)
-/*
- * Copyright 2020 Compass Electronics Group, LLC
- */
-
-/ {
- aliases {
- rtc0 = &rtc;
- rtc1 = &snvs_rtc;
- };
-
- usdhc1_pwrseq: usdhc1_pwrseq {
- compatible = "mmc-pwrseq-simple";
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_usdhc1_gpio>;
- reset-gpios = <&gpio2 10 GPIO_ACTIVE_LOW>;
- clocks = <&osc_32k>;
- clock-names = "ext_clock";
- post-power-on-delay-ms = <80>;
- };
-
- memory@40000000 {
- device_type = "memory";
- reg = <0x0 0x40000000 0 0x80000000>;
- };
-};
-
-&A53_0 {
- cpu-supply = <&buck2_reg>;
-};
-
-&A53_1 {
- cpu-supply = <&buck2_reg>;
-};
-
-&A53_2 {
- cpu-supply = <&buck2_reg>;
-};
-
-&A53_3 {
- cpu-supply = <&buck2_reg>;
-};
-
-&ddrc {
- operating-points-v2 = <&ddrc_opp_table>;
-
- ddrc_opp_table: opp-table {
- compatible = "operating-points-v2";
-
- opp-25M {
- opp-hz = /bits/ 64 <25000000>;
- };
-
- opp-100M {
- opp-hz = /bits/ 64 <100000000>;
- };
-
- opp-750M {
- opp-hz = /bits/ 64 <750000000>;
- };
- };
-};
-
-&fec1 {
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_fec1>;
- phy-mode = "rgmii-id";
- phy-handle = <ðphy0>;
- fsl,magic-packet;
- status = "okay";
-
- mdio {
- #address-cells = <1>;
- #size-cells = <0>;
-
- ethphy0: ethernet-phy@0 {
- compatible = "ethernet-phy-ieee802.3-c22";
- reg = <0>;
- };
- };
-};
-
-&flexspi {
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_flexspi>;
- status = "okay";
-
- flash@0 {
- reg = <0>;
- #address-cells = <1>;
- #size-cells = <1>;
- compatible = "jedec,spi-nor";
- spi-max-frequency = <80000000>;
- spi-tx-bus-width = <1>;
- spi-rx-bus-width = <4>;
- };
-};
-
-&i2c1 {
- clock-frequency = <400000>;
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_i2c1>;
- status = "okay";
-
- pmic@4b {
- compatible = "rohm,bd71847";
- reg = <0x4b>;
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_pmic>;
- interrupt-parent = <&gpio1>;
- interrupts = <3 IRQ_TYPE_LEVEL_LOW>;
- rohm,reset-snvs-powered;
-
- #clock-cells = <0>;
- clocks = <&osc_32k 0>;
- clock-output-names = "clk-32k-out";
-
- regulators {
- buck1_reg: BUCK1 {
- regulator-name = "buck1";
- regulator-min-microvolt = <700000>;
- regulator-max-microvolt = <1300000>;
- regulator-boot-on;
- regulator-always-on;
- regulator-ramp-delay = <1250>;
- };
-
- buck2_reg: BUCK2 {
- regulator-name = "buck2";
- regulator-min-microvolt = <700000>;
- regulator-max-microvolt = <1300000>;
- regulator-boot-on;
- regulator-always-on;
- regulator-ramp-delay = <1250>;
- rohm,dvs-run-voltage = <1000000>;
- rohm,dvs-idle-voltage = <900000>;
- };
-
- buck3_reg: BUCK3 {
- // BUCK5 in datasheet
- regulator-name = "buck3";
- regulator-min-microvolt = <700000>;
- regulator-max-microvolt = <1350000>;
- regulator-boot-on;
- regulator-always-on;
- };
-
- buck4_reg: BUCK4 {
- // BUCK6 in datasheet
- regulator-name = "buck4";
- regulator-min-microvolt = <3000000>;
- regulator-max-microvolt = <3300000>;
- regulator-boot-on;
- regulator-always-on;
- };
-
- buck5_reg: BUCK5 {
- // BUCK7 in datasheet
- regulator-name = "buck5";
- regulator-min-microvolt = <1605000>;
- regulator-max-microvolt = <1995000>;
- regulator-boot-on;
- regulator-always-on;
- };
-
- buck6_reg: BUCK6 {
- // BUCK8 in datasheet
- regulator-name = "buck6";
- regulator-min-microvolt = <800000>;
- regulator-max-microvolt = <1400000>;
- regulator-boot-on;
- regulator-always-on;
- };
-
- ldo1_reg: LDO1 {
- regulator-name = "ldo1";
- regulator-min-microvolt = <1600000>;
- regulator-max-microvolt = <3300000>;
- regulator-boot-on;
- regulator-always-on;
- };
-
- ldo2_reg: LDO2 {
- regulator-name = "ldo2";
- regulator-min-microvolt = <800000>;
- regulator-max-microvolt = <900000>;
- regulator-boot-on;
- regulator-always-on;
- };
-
- ldo3_reg: LDO3 {
- regulator-name = "ldo3";
- regulator-min-microvolt = <1800000>;
- regulator-max-microvolt = <3300000>;
- regulator-boot-on;
- regulator-always-on;
- };
-
- ldo4_reg: LDO4 {
- regulator-name = "ldo4";
- regulator-min-microvolt = <900000>;
- regulator-max-microvolt = <1800000>;
- regulator-boot-on;
- regulator-always-on;
- };
-
- ldo6_reg: LDO6 {
- regulator-name = "ldo6";
- regulator-min-microvolt = <900000>;
- regulator-max-microvolt = <1800000>;
- regulator-boot-on;
- regulator-always-on;
- };
- };
- };
-};
-
-&i2c3 {
- clock-frequency = <400000>;
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_i2c3>;
- status = "okay";
-
- eeprom@50 {
- compatible = "microchip,24c64", "atmel,24c64";
- pagesize = <32>;
- read-only; /* Manufacturing EEPROM programmed at factory */
- reg = <0x50>;
- };
-
- rtc: rtc@51 {
- compatible = "nxp,pcf85263";
- reg = <0x51>;
- };
-};
-
-&uart1 {
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_uart1>;
- assigned-clocks = <&clk IMX8MM_CLK_UART1>;
- assigned-clock-parents = <&clk IMX8MM_SYS_PLL1_80M>;
- uart-has-rtscts;
- status = "okay";
-
- bluetooth {
- compatible = "brcm,bcm43438-bt";
- shutdown-gpios = <&gpio2 6 GPIO_ACTIVE_HIGH>;
- host-wakeup-gpios = <&gpio2 8 GPIO_ACTIVE_HIGH>;
- device-wakeup-gpios = <&gpio2 7 GPIO_ACTIVE_HIGH>;
- clocks = <&osc_32k>;
- max-speed = <4000000>;
- clock-names = "extclk";
- };
-};
-
-&usdhc1 {
- #address-cells = <1>;
- #size-cells = <0>;
- pinctrl-names = "default", "state_100mhz", "state_200mhz";
- pinctrl-0 = <&pinctrl_usdhc1>;
- pinctrl-1 = <&pinctrl_usdhc1_100mhz>;
- pinctrl-2 = <&pinctrl_usdhc1_200mhz>;
- bus-width = <4>;
- non-removable;
- cap-power-off-card;
- keep-power-in-suspend;
- mmc-pwrseq = <&usdhc1_pwrseq>;
- status = "okay";
-
- brcmf: bcrmf@1 {
- reg = <1>;
- compatible = "brcm,bcm4329-fmac";
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_wlan>;
- interrupt-parent = <&gpio2>;
- interrupts = <9 IRQ_TYPE_LEVEL_HIGH>;
- interrupt-names = "host-wake";
- };
-};
-
-&usdhc3 {
- pinctrl-names = "default", "state_100mhz", "state_200mhz";
- pinctrl-0 = <&pinctrl_usdhc3>;
- pinctrl-1 = <&pinctrl_usdhc3_100mhz>;
- pinctrl-2 = <&pinctrl_usdhc3_200mhz>;
- bus-width = <8>;
- non-removable;
- status = "okay";
-};
-
-&wdog1 {
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_wdog>;
- fsl,ext-reset-output;
- status = "okay";
-};
-
-&iomuxc {
- pinctrl_fec1: fec1grp {
- fsl,pins = <
- MX8MM_IOMUXC_ENET_MDC_ENET1_MDC 0x3
- MX8MM_IOMUXC_ENET_MDIO_ENET1_MDIO 0x3
- MX8MM_IOMUXC_ENET_TD3_ENET1_RGMII_TD3 0x1f
- MX8MM_IOMUXC_ENET_TD2_ENET1_RGMII_TD2 0x1f
- MX8MM_IOMUXC_ENET_TD1_ENET1_RGMII_TD1 0x1f
- MX8MM_IOMUXC_ENET_TD0_ENET1_RGMII_TD0 0x1f
- MX8MM_IOMUXC_ENET_RD3_ENET1_RGMII_RD3 0x91
- MX8MM_IOMUXC_ENET_RD2_ENET1_RGMII_RD2 0x91
- MX8MM_IOMUXC_ENET_RD1_ENET1_RGMII_RD1 0x91
- MX8MM_IOMUXC_ENET_RD0_ENET1_RGMII_RD0 0x91
- MX8MM_IOMUXC_ENET_TXC_ENET1_RGMII_TXC 0x1f
- MX8MM_IOMUXC_ENET_RXC_ENET1_RGMII_RXC 0x91
- MX8MM_IOMUXC_ENET_RX_CTL_ENET1_RGMII_RX_CTL 0x91
- MX8MM_IOMUXC_ENET_TX_CTL_ENET1_RGMII_TX_CTL 0x1f
- MX8MM_IOMUXC_SAI2_RXC_GPIO4_IO22 0x19
- >;
- };
-
- pinctrl_i2c1: i2c1grp {
- fsl,pins = <
- MX8MM_IOMUXC_I2C1_SCL_I2C1_SCL 0x400001c3
- MX8MM_IOMUXC_I2C1_SDA_I2C1_SDA 0x400001c3
- >;
- };
-
- pinctrl_i2c3: i2c3grp {
- fsl,pins = <
- MX8MM_IOMUXC_I2C3_SCL_I2C3_SCL 0x400001c3
- MX8MM_IOMUXC_I2C3_SDA_I2C3_SDA 0x400001c3
- >;
- };
-
- pinctrl_flexspi: flexspigrp {
- fsl,pins = <
- MX8MM_IOMUXC_NAND_ALE_QSPI_A_SCLK 0x1c2
- MX8MM_IOMUXC_NAND_CE0_B_QSPI_A_SS0_B 0x82
- MX8MM_IOMUXC_NAND_DATA00_QSPI_A_DATA0 0x82
- MX8MM_IOMUXC_NAND_DATA01_QSPI_A_DATA1 0x82
- MX8MM_IOMUXC_NAND_DATA02_QSPI_A_DATA2 0x82
- MX8MM_IOMUXC_NAND_DATA03_QSPI_A_DATA3 0x82
- >;
- };
-
- pinctrl_pmic: pmicirqgrp {
- fsl,pins = <
- MX8MM_IOMUXC_GPIO1_IO03_GPIO1_IO3 0x141
- >;
- };
-
- pinctrl_uart1: uart1grp {
- fsl,pins = <
- MX8MM_IOMUXC_UART1_RXD_UART1_DCE_RX 0x140
- MX8MM_IOMUXC_UART1_TXD_UART1_DCE_TX 0x140
- MX8MM_IOMUXC_UART3_RXD_UART1_DCE_CTS_B 0x140
- MX8MM_IOMUXC_UART3_TXD_UART1_DCE_RTS_B 0x140
- MX8MM_IOMUXC_SD1_DATA4_GPIO2_IO6 0x19
- MX8MM_IOMUXC_SD1_DATA5_GPIO2_IO7 0x19
- MX8MM_IOMUXC_SD1_DATA6_GPIO2_IO8 0x19
- MX8MM_IOMUXC_GPIO1_IO00_ANAMIX_REF_CLK_32K 0x141
- >;
- };
-
- pinctrl_usdhc1_gpio: usdhc1gpiogrp {
- fsl,pins = <
- MX8MM_IOMUXC_SD1_RESET_B_GPIO2_IO10 0x41
- >;
- };
-
- pinctrl_usdhc1: usdhc1grp {
- fsl,pins = <
- MX8MM_IOMUXC_SD1_CLK_USDHC1_CLK 0x190
- MX8MM_IOMUXC_SD1_CMD_USDHC1_CMD 0x1d0
- MX8MM_IOMUXC_SD1_DATA0_USDHC1_DATA0 0x1d0
- MX8MM_IOMUXC_SD1_DATA1_USDHC1_DATA1 0x1d0
- MX8MM_IOMUXC_SD1_DATA2_USDHC1_DATA2 0x1d0
- MX8MM_IOMUXC_SD1_DATA3_USDHC1_DATA3 0x1d0
- >;
- };
-
- pinctrl_usdhc1_100mhz: usdhc1-100mhzgrp {
- fsl,pins = <
- MX8MM_IOMUXC_SD1_CLK_USDHC1_CLK 0x194
- MX8MM_IOMUXC_SD1_CMD_USDHC1_CMD 0x1d4
- MX8MM_IOMUXC_SD1_DATA0_USDHC1_DATA0 0x1d4
- MX8MM_IOMUXC_SD1_DATA1_USDHC1_DATA1 0x1d4
- MX8MM_IOMUXC_SD1_DATA2_USDHC1_DATA2 0x1d4
- MX8MM_IOMUXC_SD1_DATA3_USDHC1_DATA3 0x1d4
- >;
- };
-
- pinctrl_usdhc1_200mhz: usdhc1-200mhzgrp {
- fsl,pins = <
- MX8MM_IOMUXC_SD1_CLK_USDHC1_CLK 0x196
- MX8MM_IOMUXC_SD1_CMD_USDHC1_CMD 0x1d6
- MX8MM_IOMUXC_SD1_DATA0_USDHC1_DATA0 0x1d6
- MX8MM_IOMUXC_SD1_DATA1_USDHC1_DATA1 0x1d6
- MX8MM_IOMUXC_SD1_DATA2_USDHC1_DATA2 0x1d6
- MX8MM_IOMUXC_SD1_DATA3_USDHC1_DATA3 0x1d6
- >;
- };
-
- pinctrl_usdhc3: usdhc3grp {
- fsl,pins = <
- MX8MM_IOMUXC_NAND_WE_B_USDHC3_CLK 0x190
- MX8MM_IOMUXC_NAND_WP_B_USDHC3_CMD 0x1d0
- MX8MM_IOMUXC_NAND_DATA04_USDHC3_DATA0 0x1d0
- MX8MM_IOMUXC_NAND_DATA05_USDHC3_DATA1 0x1d0
- MX8MM_IOMUXC_NAND_DATA06_USDHC3_DATA2 0x1d0
- MX8MM_IOMUXC_NAND_DATA07_USDHC3_DATA3 0x1d0
- MX8MM_IOMUXC_NAND_RE_B_USDHC3_DATA4 0x1d0
- MX8MM_IOMUXC_NAND_CE2_B_USDHC3_DATA5 0x1d0
- MX8MM_IOMUXC_NAND_CE3_B_USDHC3_DATA6 0x1d0
- MX8MM_IOMUXC_NAND_CLE_USDHC3_DATA7 0x1d0
- MX8MM_IOMUXC_NAND_CE1_B_USDHC3_STROBE 0x190
- >;
- };
-
- pinctrl_usdhc3_100mhz: usdhc3-100mhzgrp {
- fsl,pins = <
- MX8MM_IOMUXC_NAND_WE_B_USDHC3_CLK 0x194
- MX8MM_IOMUXC_NAND_WP_B_USDHC3_CMD 0x1d4
- MX8MM_IOMUXC_NAND_DATA04_USDHC3_DATA0 0x1d4
- MX8MM_IOMUXC_NAND_DATA05_USDHC3_DATA1 0x1d4
- MX8MM_IOMUXC_NAND_DATA06_USDHC3_DATA2 0x1d4
- MX8MM_IOMUXC_NAND_DATA07_USDHC3_DATA3 0x1d4
- MX8MM_IOMUXC_NAND_RE_B_USDHC3_DATA4 0x1d4
- MX8MM_IOMUXC_NAND_CE2_B_USDHC3_DATA5 0x1d4
- MX8MM_IOMUXC_NAND_CE3_B_USDHC3_DATA6 0x1d4
- MX8MM_IOMUXC_NAND_CLE_USDHC3_DATA7 0x1d4
- MX8MM_IOMUXC_NAND_CE1_B_USDHC3_STROBE 0x194
- >;
- };
-
- pinctrl_usdhc3_200mhz: usdhc3-200mhzgrp {
- fsl,pins = <
- MX8MM_IOMUXC_NAND_WE_B_USDHC3_CLK 0x196
- MX8MM_IOMUXC_NAND_WP_B_USDHC3_CMD 0x1d6
- MX8MM_IOMUXC_NAND_DATA04_USDHC3_DATA0 0x1d6
- MX8MM_IOMUXC_NAND_DATA05_USDHC3_DATA1 0x1d6
- MX8MM_IOMUXC_NAND_DATA06_USDHC3_DATA2 0x1d6
- MX8MM_IOMUXC_NAND_DATA07_USDHC3_DATA3 0x1d6
- MX8MM_IOMUXC_NAND_RE_B_USDHC3_DATA4 0x1d6
- MX8MM_IOMUXC_NAND_CE2_B_USDHC3_DATA5 0x1d6
- MX8MM_IOMUXC_NAND_CE3_B_USDHC3_DATA6 0x1d6
- MX8MM_IOMUXC_NAND_CLE_USDHC3_DATA7 0x1d6
- MX8MM_IOMUXC_NAND_CE1_B_USDHC3_STROBE 0x196
- >;
- };
-
- pinctrl_wdog: wdoggrp {
- fsl,pins = <
- MX8MM_IOMUXC_GPIO1_IO02_WDOG1_WDOG_B 0x166
- >;
- };
-
- pinctrl_wlan: wlangrp {
- fsl,pins = <
- MX8MM_IOMUXC_SD1_DATA7_GPIO2_IO9 0x111
- >;
- };
-};
diff --git a/arch/arm/dts/imx8mm-evk.dts b/arch/arm/dts/imx8mm-evk.dts
deleted file mode 100644
index a2b24d4..0000000
--- a/arch/arm/dts/imx8mm-evk.dts
+++ /dev/null
@@ -1,128 +0,0 @@
-// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
-/*
- * Copyright 2019-2020 NXP
- */
-
-/dts-v1/;
-
-#include <dt-bindings/usb/pd.h>
-#include "imx8mm-evk.dtsi"
-
-/ {
- model = "FSL i.MX8MM EVK board";
- compatible = "fsl,imx8mm-evk", "fsl,imx8mm";
-
- aliases {
- spi0 = &flexspi;
- };
-};
-
-&ddrc {
- operating-points-v2 = <&ddrc_opp_table>;
-
- ddrc_opp_table: opp-table {
- compatible = "operating-points-v2";
-
- opp-25M {
- opp-hz = /bits/ 64 <25000000>;
- };
-
- opp-100M {
- opp-hz = /bits/ 64 <100000000>;
- };
-
- opp-750M {
- opp-hz = /bits/ 64 <750000000>;
- };
- };
-};
-
-&flexspi {
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_flexspi>;
- status = "okay";
-
- flash@0 {
- reg = <0>;
- #address-cells = <1>;
- #size-cells = <1>;
- compatible = "jedec,spi-nor";
- spi-max-frequency = <80000000>;
- spi-tx-bus-width = <1>;
- spi-rx-bus-width = <4>;
- };
-};
-
-&usdhc3 {
- assigned-clocks = <&clk IMX8MM_CLK_USDHC3_ROOT>;
- assigned-clock-rates = <400000000>;
- pinctrl-names = "default", "state_100mhz", "state_200mhz";
- pinctrl-0 = <&pinctrl_usdhc3>;
- pinctrl-1 = <&pinctrl_usdhc3_100mhz>;
- pinctrl-2 = <&pinctrl_usdhc3_200mhz>;
- bus-width = <8>;
- non-removable;
- status = "okay";
-};
-
-&iomuxc {
- pinctrl_flexspi: flexspigrp {
- fsl,pins = <
- MX8MM_IOMUXC_NAND_ALE_QSPI_A_SCLK 0x1c2
- MX8MM_IOMUXC_NAND_CE0_B_QSPI_A_SS0_B 0x82
- MX8MM_IOMUXC_NAND_DATA00_QSPI_A_DATA0 0x82
- MX8MM_IOMUXC_NAND_DATA01_QSPI_A_DATA1 0x82
- MX8MM_IOMUXC_NAND_DATA02_QSPI_A_DATA2 0x82
- MX8MM_IOMUXC_NAND_DATA03_QSPI_A_DATA3 0x82
- >;
- };
-
- pinctrl_usdhc3: usdhc3grp {
- fsl,pins = <
- MX8MM_IOMUXC_NAND_WE_B_USDHC3_CLK 0x190
- MX8MM_IOMUXC_NAND_WP_B_USDHC3_CMD 0x1d0
- MX8MM_IOMUXC_NAND_DATA04_USDHC3_DATA0 0x1d0
- MX8MM_IOMUXC_NAND_DATA05_USDHC3_DATA1 0x1d0
- MX8MM_IOMUXC_NAND_DATA06_USDHC3_DATA2 0x1d0
- MX8MM_IOMUXC_NAND_DATA06_USDHC3_DATA2 0x1d0
- MX8MM_IOMUXC_NAND_DATA07_USDHC3_DATA3 0x1d0
- MX8MM_IOMUXC_NAND_RE_B_USDHC3_DATA4 0x1d0
- MX8MM_IOMUXC_NAND_CE2_B_USDHC3_DATA5 0x1d0
- MX8MM_IOMUXC_NAND_CE3_B_USDHC3_DATA6 0x1d0
- MX8MM_IOMUXC_NAND_CLE_USDHC3_DATA7 0x1d0
- MX8MM_IOMUXC_NAND_CE1_B_USDHC3_STROBE 0x190
- >;
- };
-
- pinctrl_usdhc3_100mhz: usdhc3-100mhzgrp {
- fsl,pins = <
- MX8MM_IOMUXC_NAND_WE_B_USDHC3_CLK 0x194
- MX8MM_IOMUXC_NAND_WP_B_USDHC3_CMD 0x1d4
- MX8MM_IOMUXC_NAND_DATA04_USDHC3_DATA0 0x1d4
- MX8MM_IOMUXC_NAND_DATA05_USDHC3_DATA1 0x1d4
- MX8MM_IOMUXC_NAND_DATA06_USDHC3_DATA2 0x1d4
- MX8MM_IOMUXC_NAND_DATA07_USDHC3_DATA3 0x1d4
- MX8MM_IOMUXC_NAND_RE_B_USDHC3_DATA4 0x1d4
- MX8MM_IOMUXC_NAND_CE2_B_USDHC3_DATA5 0x1d4
- MX8MM_IOMUXC_NAND_CE3_B_USDHC3_DATA6 0x1d4
- MX8MM_IOMUXC_NAND_CLE_USDHC3_DATA7 0x1d4
- MX8MM_IOMUXC_NAND_CE1_B_USDHC3_STROBE 0x194
- >;
- };
-
- pinctrl_usdhc3_200mhz: usdhc3-200mhzgrp {
- fsl,pins = <
- MX8MM_IOMUXC_NAND_WE_B_USDHC3_CLK 0x196
- MX8MM_IOMUXC_NAND_WP_B_USDHC3_CMD 0x1d6
- MX8MM_IOMUXC_NAND_DATA04_USDHC3_DATA0 0x1d6
- MX8MM_IOMUXC_NAND_DATA05_USDHC3_DATA1 0x1d6
- MX8MM_IOMUXC_NAND_DATA06_USDHC3_DATA2 0x1d6
- MX8MM_IOMUXC_NAND_DATA07_USDHC3_DATA3 0x1d6
- MX8MM_IOMUXC_NAND_RE_B_USDHC3_DATA4 0x1d6
- MX8MM_IOMUXC_NAND_CE2_B_USDHC3_DATA5 0x1d6
- MX8MM_IOMUXC_NAND_CE3_B_USDHC3_DATA6 0x1d6
- MX8MM_IOMUXC_NAND_CLE_USDHC3_DATA7 0x1d6
- MX8MM_IOMUXC_NAND_CE1_B_USDHC3_STROBE 0x196
- >;
- };
-};
diff --git a/arch/arm/dts/imx8mm-evk.dtsi b/arch/arm/dts/imx8mm-evk.dtsi
deleted file mode 100644
index 7d6317d..0000000
--- a/arch/arm/dts/imx8mm-evk.dtsi
+++ /dev/null
@@ -1,615 +0,0 @@
-// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
-/*
- * Copyright 2020 NXP
- */
-
-/dts-v1/;
-
-#include <dt-bindings/phy/phy-imx8-pcie.h>
-#include <dt-bindings/usb/pd.h>
-#include "imx8mm.dtsi"
-
-/ {
- chosen {
- stdout-path = &uart2;
- };
-
- memory@40000000 {
- device_type = "memory";
- reg = <0x0 0x40000000 0 0x80000000>;
- };
-
- leds {
- compatible = "gpio-leds";
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_gpio_led>;
-
- status {
- label = "status";
- gpios = <&gpio3 16 GPIO_ACTIVE_HIGH>;
- default-state = "on";
- };
- };
-
- pcie0_refclk: pcie0-refclk {
- compatible = "fixed-clock";
- #clock-cells = <0>;
- clock-frequency = <100000000>;
- };
-
- reg_pcie0: regulator-pcie {
- compatible = "regulator-fixed";
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_pcie0_reg>;
- regulator-name = "MPCIE_3V3";
- regulator-min-microvolt = <3300000>;
- regulator-max-microvolt = <3300000>;
- gpio = <&gpio1 5 GPIO_ACTIVE_HIGH>;
- enable-active-high;
- };
-
- reg_usdhc2_vmmc: regulator-usdhc2 {
- compatible = "regulator-fixed";
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_reg_usdhc2_vmmc>;
- regulator-name = "VSD_3V3";
- regulator-min-microvolt = <3300000>;
- regulator-max-microvolt = <3300000>;
- gpio = <&gpio2 19 GPIO_ACTIVE_HIGH>;
- enable-active-high;
- };
-
- backlight: backlight {
- compatible = "pwm-backlight";
- pwms = <&pwm1 0 5000000 0>;
- brightness-levels = <0 255>;
- num-interpolated-steps = <255>;
- default-brightness-level = <250>;
- };
-
- ir-receiver {
- compatible = "gpio-ir-receiver";
- gpios = <&gpio1 13 GPIO_ACTIVE_LOW>;
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_ir>;
- linux,autosuspend-period = <125>;
- };
-
- audio_codec_bt_sco: audio-codec-bt-sco {
- compatible = "linux,bt-sco";
- #sound-dai-cells = <1>;
- };
-
- wm8524: audio-codec {
- #sound-dai-cells = <0>;
- compatible = "wlf,wm8524";
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_gpio_wlf>;
- wlf,mute-gpios = <&gpio5 21 GPIO_ACTIVE_LOW>;
- };
-
- sound-bt-sco {
- compatible = "simple-audio-card";
- simple-audio-card,name = "bt-sco-audio";
- simple-audio-card,format = "dsp_a";
- simple-audio-card,bitclock-inversion;
- simple-audio-card,frame-master = <&btcpu>;
- simple-audio-card,bitclock-master = <&btcpu>;
-
- btcpu: simple-audio-card,cpu {
- sound-dai = <&sai2>;
- dai-tdm-slot-num = <2>;
- dai-tdm-slot-width = <16>;
- };
-
- simple-audio-card,codec {
- sound-dai = <&audio_codec_bt_sco 1>;
- };
- };
-
- sound-wm8524 {
- compatible = "simple-audio-card";
- simple-audio-card,name = "wm8524-audio";
- simple-audio-card,format = "i2s";
- simple-audio-card,frame-master = <&cpudai>;
- simple-audio-card,bitclock-master = <&cpudai>;
- simple-audio-card,widgets =
- "Line", "Left Line Out Jack",
- "Line", "Right Line Out Jack";
- simple-audio-card,routing =
- "Left Line Out Jack", "LINEVOUTL",
- "Right Line Out Jack", "LINEVOUTR";
-
- cpudai: simple-audio-card,cpu {
- sound-dai = <&sai3>;
- dai-tdm-slot-num = <2>;
- dai-tdm-slot-width = <32>;
- };
-
- simple-audio-card,codec {
- sound-dai = <&wm8524>;
- clocks = <&clk IMX8MM_CLK_SAI3_ROOT>;
- };
- };
-};
-
-&A53_0 {
- cpu-supply = <&buck2_reg>;
-};
-
-&A53_1 {
- cpu-supply = <&buck2_reg>;
-};
-
-&A53_2 {
- cpu-supply = <&buck2_reg>;
-};
-
-&A53_3 {
- cpu-supply = <&buck2_reg>;
-};
-
-&fec1 {
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_fec1>;
- phy-mode = "rgmii-id";
- phy-handle = <ðphy0>;
- fsl,magic-packet;
- status = "okay";
-
- mdio {
- #address-cells = <1>;
- #size-cells = <0>;
-
- ethphy0: ethernet-phy@0 {
- compatible = "ethernet-phy-ieee802.3-c22";
- reg = <0>;
- reset-gpios = <&gpio4 22 GPIO_ACTIVE_LOW>;
- reset-assert-us = <10000>;
- qca,disable-smarteee;
- vddio-supply = <&vddio>;
-
- vddio: vddio-regulator {
- regulator-min-microvolt = <1800000>;
- regulator-max-microvolt = <1800000>;
- };
- };
- };
-};
-
-&i2c1 {
- clock-frequency = <400000>;
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_i2c1>;
- status = "okay";
-
- pmic@4b {
- compatible = "rohm,bd71847";
- reg = <0x4b>;
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_pmic>;
- interrupt-parent = <&gpio1>;
- interrupts = <3 IRQ_TYPE_LEVEL_LOW>;
- rohm,reset-snvs-powered;
-
- #clock-cells = <0>;
- clocks = <&osc_32k 0>;
- clock-output-names = "clk-32k-out";
-
- regulators {
- buck1_reg: BUCK1 {
- regulator-name = "buck1";
- regulator-min-microvolt = <700000>;
- regulator-max-microvolt = <1300000>;
- regulator-boot-on;
- regulator-always-on;
- regulator-ramp-delay = <1250>;
- };
-
- buck2_reg: BUCK2 {
- regulator-name = "buck2";
- regulator-min-microvolt = <700000>;
- regulator-max-microvolt = <1300000>;
- regulator-boot-on;
- regulator-always-on;
- regulator-ramp-delay = <1250>;
- rohm,dvs-run-voltage = <1000000>;
- rohm,dvs-idle-voltage = <900000>;
- };
-
- buck3_reg: BUCK3 {
- // BUCK5 in datasheet
- regulator-name = "buck3";
- regulator-min-microvolt = <700000>;
- regulator-max-microvolt = <1350000>;
- regulator-boot-on;
- regulator-always-on;
- };
-
- buck4_reg: BUCK4 {
- // BUCK6 in datasheet
- regulator-name = "buck4";
- regulator-min-microvolt = <3000000>;
- regulator-max-microvolt = <3300000>;
- regulator-boot-on;
- regulator-always-on;
- };
-
- buck5_reg: BUCK5 {
- // BUCK7 in datasheet
- regulator-name = "buck5";
- regulator-min-microvolt = <1605000>;
- regulator-max-microvolt = <1995000>;
- regulator-boot-on;
- regulator-always-on;
- };
-
- buck6_reg: BUCK6 {
- // BUCK8 in datasheet
- regulator-name = "buck6";
- regulator-min-microvolt = <800000>;
- regulator-max-microvolt = <1400000>;
- regulator-boot-on;
- regulator-always-on;
- };
-
- ldo1_reg: LDO1 {
- regulator-name = "ldo1";
- regulator-min-microvolt = <1600000>;
- regulator-max-microvolt = <3300000>;
- regulator-boot-on;
- regulator-always-on;
- };
-
- ldo2_reg: LDO2 {
- regulator-name = "ldo2";
- regulator-min-microvolt = <800000>;
- regulator-max-microvolt = <900000>;
- regulator-boot-on;
- regulator-always-on;
- };
-
- ldo3_reg: LDO3 {
- regulator-name = "ldo3";
- regulator-min-microvolt = <1800000>;
- regulator-max-microvolt = <3300000>;
- regulator-boot-on;
- regulator-always-on;
- };
-
- ldo4_reg: LDO4 {
- regulator-name = "ldo4";
- regulator-min-microvolt = <900000>;
- regulator-max-microvolt = <1800000>;
- regulator-boot-on;
- regulator-always-on;
- };
-
- ldo6_reg: LDO6 {
- regulator-name = "ldo6";
- regulator-min-microvolt = <900000>;
- regulator-max-microvolt = <1800000>;
- regulator-boot-on;
- regulator-always-on;
- };
- };
- };
-};
-
-&i2c2 {
- clock-frequency = <400000>;
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_i2c2>;
- status = "okay";
-
- ptn5110: tcpc@50 {
- compatible = "nxp,ptn5110";
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_typec1>;
- reg = <0x50>;
- interrupt-parent = <&gpio2>;
- interrupts = <11 8>;
- status = "okay";
-
- port {
- typec1_dr_sw: endpoint {
- remote-endpoint = <&usb1_drd_sw>;
- };
- };
-
- typec1_con: connector {
- compatible = "usb-c-connector";
- label = "USB-C";
- power-role = "dual";
- data-role = "dual";
- try-power-role = "sink";
- source-pdos = <PDO_FIXED(5000, 3000, PDO_FIXED_USB_COMM)>;
- sink-pdos = <PDO_FIXED(5000, 3000, PDO_FIXED_USB_COMM)
- PDO_VAR(5000, 20000, 3000)>;
- op-sink-microwatt = <15000000>;
- self-powered;
- };
- };
-};
-
-&i2c3 {
- clock-frequency = <400000>;
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_i2c3>;
- status = "okay";
-
- pca6416: gpio@20 {
- compatible = "ti,tca6416";
- reg = <0x20>;
- gpio-controller;
- #gpio-cells = <2>;
- };
-};
-
-&pcie_phy {
- fsl,refclk-pad-mode = <IMX8_PCIE_REFCLK_PAD_INPUT>;
- fsl,tx-deemph-gen1 = <0x2d>;
- fsl,tx-deemph-gen2 = <0xf>;
- clocks = <&pcie0_refclk>;
- status = "okay";
-};
-
-&pcie0 {
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_pcie0>;
- reset-gpio = <&gpio4 21 GPIO_ACTIVE_LOW>;
- clocks = <&clk IMX8MM_CLK_PCIE1_ROOT>, <&clk IMX8MM_CLK_PCIE1_AUX>,
- <&pcie0_refclk>;
- clock-names = "pcie", "pcie_aux", "pcie_bus";
- assigned-clocks = <&clk IMX8MM_CLK_PCIE1_AUX>,
- <&clk IMX8MM_CLK_PCIE1_CTRL>;
- assigned-clock-rates = <10000000>, <250000000>;
- assigned-clock-parents = <&clk IMX8MM_SYS_PLL2_50M>,
- <&clk IMX8MM_SYS_PLL2_250M>;
- vpcie-supply = <®_pcie0>;
- status = "okay";
-};
-
-&sai2 {
- #sound-dai-cells = <0>;
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_sai2>;
- assigned-clocks = <&clk IMX8MM_CLK_SAI2>;
- assigned-clock-parents = <&clk IMX8MM_AUDIO_PLL1_OUT>;
- assigned-clock-rates = <24576000>;
- status = "okay";
-};
-
-&sai3 {
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_sai3>;
- assigned-clocks = <&clk IMX8MM_CLK_SAI3>;
- assigned-clock-parents = <&clk IMX8MM_AUDIO_PLL1_OUT>;
- assigned-clock-rates = <24576000>;
- status = "okay";
-};
-
-&snvs_pwrkey {
- status = "okay";
-};
-
-&uart2 { /* console */
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_uart2>;
- status = "okay";
-};
-
-&usbotg1 {
- dr_mode = "otg";
- hnp-disable;
- srp-disable;
- adp-disable;
- usb-role-switch;
- disable-over-current;
- samsung,picophy-pre-emp-curr-control = <3>;
- samsung,picophy-dc-vol-level-adjust = <7>;
- status = "okay";
-
- port {
- usb1_drd_sw: endpoint {
- remote-endpoint = <&typec1_dr_sw>;
- };
- };
-};
-
-&usdhc2 {
- assigned-clocks = <&clk IMX8MM_CLK_USDHC2>;
- assigned-clock-rates = <200000000>;
- pinctrl-names = "default", "state_100mhz", "state_200mhz";
- pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>;
- pinctrl-1 = <&pinctrl_usdhc2_100mhz>, <&pinctrl_usdhc2_gpio>;
- pinctrl-2 = <&pinctrl_usdhc2_200mhz>, <&pinctrl_usdhc2_gpio>;
- cd-gpios = <&gpio1 15 GPIO_ACTIVE_LOW>;
- bus-width = <4>;
- vmmc-supply = <®_usdhc2_vmmc>;
- status = "okay";
-};
-
-&wdog1 {
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_wdog>;
- fsl,ext-reset-output;
- status = "okay";
-};
-
-&pwm1 {
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_backlight>;
- status = "okay";
-};
-
-&iomuxc {
- pinctrl_fec1: fec1grp {
- fsl,pins = <
- MX8MM_IOMUXC_ENET_MDC_ENET1_MDC 0x3
- MX8MM_IOMUXC_ENET_MDIO_ENET1_MDIO 0x3
- MX8MM_IOMUXC_ENET_TD3_ENET1_RGMII_TD3 0x1f
- MX8MM_IOMUXC_ENET_TD2_ENET1_RGMII_TD2 0x1f
- MX8MM_IOMUXC_ENET_TD1_ENET1_RGMII_TD1 0x1f
- MX8MM_IOMUXC_ENET_TD0_ENET1_RGMII_TD0 0x1f
- MX8MM_IOMUXC_ENET_RD3_ENET1_RGMII_RD3 0x91
- MX8MM_IOMUXC_ENET_RD2_ENET1_RGMII_RD2 0x91
- MX8MM_IOMUXC_ENET_RD1_ENET1_RGMII_RD1 0x91
- MX8MM_IOMUXC_ENET_RD0_ENET1_RGMII_RD0 0x91
- MX8MM_IOMUXC_ENET_TXC_ENET1_RGMII_TXC 0x1f
- MX8MM_IOMUXC_ENET_RXC_ENET1_RGMII_RXC 0x91
- MX8MM_IOMUXC_ENET_RX_CTL_ENET1_RGMII_RX_CTL 0x91
- MX8MM_IOMUXC_ENET_TX_CTL_ENET1_RGMII_TX_CTL 0x1f
- MX8MM_IOMUXC_SAI2_RXC_GPIO4_IO22 0x19
- >;
- };
-
- pinctrl_gpio_led: gpioledgrp {
- fsl,pins = <
- MX8MM_IOMUXC_NAND_READY_B_GPIO3_IO16 0x19
- >;
- };
-
- pinctrl_ir: irgrp {
- fsl,pins = <
- MX8MM_IOMUXC_GPIO1_IO13_GPIO1_IO13 0x4f
- >;
- };
-
- pinctrl_gpio_wlf: gpiowlfgrp {
- fsl,pins = <
- MX8MM_IOMUXC_I2C4_SDA_GPIO5_IO21 0xd6
- >;
- };
-
- pinctrl_i2c1: i2c1grp {
- fsl,pins = <
- MX8MM_IOMUXC_I2C1_SCL_I2C1_SCL 0x400001c3
- MX8MM_IOMUXC_I2C1_SDA_I2C1_SDA 0x400001c3
- >;
- };
-
- pinctrl_i2c2: i2c2grp {
- fsl,pins = <
- MX8MM_IOMUXC_I2C2_SCL_I2C2_SCL 0x400001c3
- MX8MM_IOMUXC_I2C2_SDA_I2C2_SDA 0x400001c3
- >;
- };
-
- pinctrl_i2c3: i2c3grp {
- fsl,pins = <
- MX8MM_IOMUXC_I2C3_SCL_I2C3_SCL 0x400001c3
- MX8MM_IOMUXC_I2C3_SDA_I2C3_SDA 0x400001c3
- >;
- };
-
- pinctrl_pcie0: pcie0grp {
- fsl,pins = <
- MX8MM_IOMUXC_I2C4_SCL_PCIE1_CLKREQ_B 0x61
- MX8MM_IOMUXC_SAI2_RXFS_GPIO4_IO21 0x41
- >;
- };
-
- pinctrl_pcie0_reg: pcie0reggrp {
- fsl,pins = <
- MX8MM_IOMUXC_GPIO1_IO05_GPIO1_IO5 0x41
- >;
- };
-
- pinctrl_pmic: pmicirqgrp {
- fsl,pins = <
- MX8MM_IOMUXC_GPIO1_IO03_GPIO1_IO3 0x141
- >;
- };
-
- pinctrl_reg_usdhc2_vmmc: regusdhc2vmmcgrp {
- fsl,pins = <
- MX8MM_IOMUXC_SD2_RESET_B_GPIO2_IO19 0x41
- >;
- };
-
- pinctrl_sai2: sai2grp {
- fsl,pins = <
- MX8MM_IOMUXC_SAI2_TXC_SAI2_TX_BCLK 0xd6
- MX8MM_IOMUXC_SAI2_TXFS_SAI2_TX_SYNC 0xd6
- MX8MM_IOMUXC_SAI2_TXD0_SAI2_TX_DATA0 0xd6
- MX8MM_IOMUXC_SAI2_RXD0_SAI2_RX_DATA0 0xd6
- >;
- };
-
- pinctrl_sai3: sai3grp {
- fsl,pins = <
- MX8MM_IOMUXC_SAI3_TXFS_SAI3_TX_SYNC 0xd6
- MX8MM_IOMUXC_SAI3_TXC_SAI3_TX_BCLK 0xd6
- MX8MM_IOMUXC_SAI3_MCLK_SAI3_MCLK 0xd6
- MX8MM_IOMUXC_SAI3_TXD_SAI3_TX_DATA0 0xd6
- >;
- };
-
- pinctrl_typec1: typec1grp {
- fsl,pins = <
- MX8MM_IOMUXC_SD1_STROBE_GPIO2_IO11 0x159
- >;
- };
-
- pinctrl_uart2: uart2grp {
- fsl,pins = <
- MX8MM_IOMUXC_UART2_RXD_UART2_DCE_RX 0x140
- MX8MM_IOMUXC_UART2_TXD_UART2_DCE_TX 0x140
- >;
- };
-
- pinctrl_usdhc2_gpio: usdhc2grpgpiogrp {
- fsl,pins = <
- MX8MM_IOMUXC_GPIO1_IO15_GPIO1_IO15 0x1c4
- >;
- };
-
- pinctrl_usdhc2: usdhc2grp {
- fsl,pins = <
- MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK 0x190
- MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d0
- MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d0
- MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d0
- MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d0
- MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d0
- MX8MM_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0x1d0
- >;
- };
-
- pinctrl_usdhc2_100mhz: usdhc2-100mhzgrp {
- fsl,pins = <
- MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK 0x194
- MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d4
- MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d4
- MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d4
- MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d4
- MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d4
- MX8MM_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0x1d0
- >;
- };
-
- pinctrl_usdhc2_200mhz: usdhc2-200mhzgrp {
- fsl,pins = <
- MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK 0x196
- MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d6
- MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d6
- MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d6
- MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d6
- MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d6
- MX8MM_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0x1d0
- >;
- };
-
- pinctrl_wdog: wdoggrp {
- fsl,pins = <
- MX8MM_IOMUXC_GPIO1_IO02_WDOG1_WDOG_B 0x166
- >;
- };
-
- pinctrl_backlight: backlightgrp {
- fsl,pins = <
- MX8MM_IOMUXC_GPIO1_IO01_PWM1_OUT 0x06
- >;
- };
-};
diff --git a/arch/arm/dts/imx8mm-venice-gw700x.dtsi b/arch/arm/dts/imx8mm-venice-gw700x.dtsi
deleted file mode 100644
index c305e32..0000000
--- a/arch/arm/dts/imx8mm-venice-gw700x.dtsi
+++ /dev/null
@@ -1,525 +0,0 @@
-// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
-/*
- * Copyright 2020 Gateworks Corporation
- */
-
-#include <dt-bindings/gpio/gpio.h>
-#include <dt-bindings/input/linux-event-codes.h>
-#include <dt-bindings/net/ti-dp83867.h>
-
-/ {
- memory@40000000 {
- device_type = "memory";
- reg = <0x0 0x40000000 0 0x80000000>;
- };
-
- gpio-keys {
- compatible = "gpio-keys";
-
- key-user-pb {
- label = "user_pb";
- gpios = <&gpio 2 GPIO_ACTIVE_LOW>;
- linux,code = <BTN_0>;
- };
-
- key-user-pb1x {
- label = "user_pb1x";
- linux,code = <BTN_1>;
- interrupt-parent = <&gsc>;
- interrupts = <0>;
- };
-
- key-erased {
- label = "key_erased";
- linux,code = <BTN_2>;
- interrupt-parent = <&gsc>;
- interrupts = <1>;
- };
-
- key-eeprom-wp {
- label = "eeprom_wp";
- linux,code = <BTN_3>;
- interrupt-parent = <&gsc>;
- interrupts = <2>;
- };
-
- key-tamper {
- label = "tamper";
- linux,code = <BTN_4>;
- interrupt-parent = <&gsc>;
- interrupts = <5>;
- };
-
- switch-hold {
- label = "switch_hold";
- linux,code = <BTN_5>;
- interrupt-parent = <&gsc>;
- interrupts = <7>;
- };
- };
-};
-
-&A53_0 {
- cpu-supply = <&buck3_reg>;
-};
-
-&A53_1 {
- cpu-supply = <&buck3_reg>;
-};
-
-&A53_2 {
- cpu-supply = <&buck3_reg>;
-};
-
-&A53_3 {
- cpu-supply = <&buck3_reg>;
-};
-
-&ddrc {
- operating-points-v2 = <&ddrc_opp_table>;
-
- ddrc_opp_table: opp-table {
- compatible = "operating-points-v2";
-
- opp-25M {
- opp-hz = /bits/ 64 <25000000>;
- };
-
- opp-100M {
- opp-hz = /bits/ 64 <100000000>;
- };
-
- opp-750M {
- opp-hz = /bits/ 64 <750000000>;
- };
- };
-};
-
-&fec1 {
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_fec1>;
- phy-mode = "rgmii-id";
- phy-handle = <ðphy0>;
- status = "okay";
-
- mdio {
- #address-cells = <1>;
- #size-cells = <0>;
-
- ethphy0: ethernet-phy@0 {
- compatible = "ethernet-phy-ieee802.3-c22";
- reg = <0>;
- ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_00_NS>;
- ti,tx-internal-delay = <DP83867_RGMIIDCTL_2_00_NS>;
- tx-fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>;
- rx-fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>;
- };
- };
-};
-
-&i2c1 {
- clock-frequency = <100000>;
- pinctrl-names = "default", "gpio";
- pinctrl-0 = <&pinctrl_i2c1>;
- pinctrl-1 = <&pinctrl_i2c1_gpio>;
- scl-gpios = <&gpio5 14 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
- sda-gpios = <&gpio5 15 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
- status = "okay";
-
- gsc: gsc@20 {
- compatible = "gw,gsc";
- reg = <0x20>;
- pinctrl-0 = <&pinctrl_gsc>;
- interrupt-parent = <&gpio2>;
- interrupts = <6 IRQ_TYPE_EDGE_FALLING>;
- interrupt-controller;
- #interrupt-cells = <1>;
- #address-cells = <1>;
- #size-cells = <0>;
-
- adc {
- compatible = "gw,gsc-adc";
- #address-cells = <1>;
- #size-cells = <0>;
-
- channel@6 {
- gw,mode = <0>;
- reg = <0x06>;
- label = "temp";
- };
-
- channel@8 {
- gw,mode = <1>;
- reg = <0x08>;
- label = "vdd_bat";
- };
-
- channel@16 {
- gw,mode = <4>;
- reg = <0x16>;
- label = "fan_tach";
- };
-
- channel@82 {
- gw,mode = <2>;
- reg = <0x82>;
- label = "vdd_vin";
- gw,voltage-divider-ohms = <22100 1000>;
- };
-
- channel@84 {
- gw,mode = <2>;
- reg = <0x84>;
- label = "vdd_adc1";
- gw,voltage-divider-ohms = <10000 10000>;
- };
-
- channel@86 {
- gw,mode = <2>;
- reg = <0x86>;
- label = "vdd_adc2";
- gw,voltage-divider-ohms = <10000 10000>;
- };
-
- channel@88 {
- gw,mode = <2>;
- reg = <0x88>;
- label = "vdd_dram";
- };
-
- channel@8c {
- gw,mode = <2>;
- reg = <0x8c>;
- label = "vdd_1p2";
- };
-
- channel@8e {
- gw,mode = <2>;
- reg = <0x8e>;
- label = "vdd_1p0";
- };
-
- channel@90 {
- gw,mode = <2>;
- reg = <0x90>;
- label = "vdd_2p5";
- gw,voltage-divider-ohms = <10000 10000>;
- };
-
- channel@92 {
- gw,mode = <2>;
- reg = <0x92>;
- label = "vdd_3p3";
- gw,voltage-divider-ohms = <10000 10000>;
- };
-
- channel@98 {
- gw,mode = <2>;
- reg = <0x98>;
- label = "vdd_0p95";
- };
-
- channel@9a {
- gw,mode = <2>;
- reg = <0x9a>;
- label = "vdd_1p8";
- };
-
- channel@a2 {
- gw,mode = <2>;
- reg = <0xa2>;
- label = "vdd_gsc";
- gw,voltage-divider-ohms = <10000 10000>;
- };
- };
-
- fan-controller@0 {
- #address-cells = <1>;
- #size-cells = <0>;
- compatible = "gw,gsc-fan";
- reg = <0x0a>;
- };
- };
-
- gpio: gpio@23 {
- compatible = "nxp,pca9555";
- reg = <0x23>;
- gpio-controller;
- #gpio-cells = <2>;
- interrupt-parent = <&gsc>;
- interrupts = <4>;
- };
-
- eeprom@50 {
- compatible = "atmel,24c02";
- reg = <0x50>;
- pagesize = <16>;
- };
-
- eeprom@51 {
- compatible = "atmel,24c02";
- reg = <0x51>;
- pagesize = <16>;
- };
-
- eeprom@52 {
- compatible = "atmel,24c02";
- reg = <0x52>;
- pagesize = <16>;
- };
-
- eeprom@53 {
- compatible = "atmel,24c02";
- reg = <0x53>;
- pagesize = <16>;
- };
-
- rtc@68 {
- compatible = "dallas,ds1672";
- reg = <0x68>;
- };
-
- pmic@69 {
- compatible = "mps,mp5416";
- reg = <0x69>;
-
- regulators {
- /* vdd_0p95: DRAM/GPU/VPU */
- buck1 {
- regulator-name = "buck1";
- regulator-min-microvolt = <800000>;
- regulator-max-microvolt = <1000000>;
- regulator-min-microamp = <3800000>;
- regulator-max-microamp = <6800000>;
- regulator-boot-on;
- regulator-always-on;
- };
-
- /* vdd_soc */
- buck2 {
- regulator-name = "buck2";
- regulator-min-microvolt = <800000>;
- regulator-max-microvolt = <900000>;
- regulator-min-microamp = <2200000>;
- regulator-max-microamp = <5200000>;
- regulator-boot-on;
- regulator-always-on;
- };
-
- /* vdd_arm */
- buck3_reg: buck3 {
- regulator-name = "buck3";
- regulator-min-microvolt = <800000>;
- regulator-max-microvolt = <1000000>;
- regulator-min-microamp = <3800000>;
- regulator-max-microamp = <6800000>;
- regulator-always-on;
- };
-
- /* vdd_1p8 */
- buck4 {
- regulator-name = "buck4";
- regulator-min-microvolt = <1800000>;
- regulator-max-microvolt = <1800000>;
- regulator-min-microamp = <2200000>;
- regulator-max-microamp = <5200000>;
- regulator-boot-on;
- regulator-always-on;
- };
-
- /* nvcc_snvs_1p8 */
- ldo1 {
- regulator-name = "ldo1";
- regulator-min-microvolt = <1800000>;
- regulator-max-microvolt = <1800000>;
- regulator-boot-on;
- regulator-always-on;
- };
-
- /* vdd_snvs_0p8 */
- ldo2 {
- regulator-name = "ldo2";
- regulator-min-microvolt = <800000>;
- regulator-max-microvolt = <800000>;
- regulator-boot-on;
- regulator-always-on;
- };
-
- /* vdd_0p9 */
- ldo3 {
- regulator-name = "ldo3";
- regulator-min-microvolt = <900000>;
- regulator-max-microvolt = <900000>;
- regulator-boot-on;
- regulator-always-on;
- };
-
- /* vdd_1p8 */
- ldo4 {
- regulator-name = "ldo4";
- regulator-min-microvolt = <1800000>;
- regulator-max-microvolt = <1800000>;
- regulator-boot-on;
- regulator-always-on;
- };
- };
- };
-};
-
-&i2c2 {
- clock-frequency = <400000>;
- pinctrl-names = "default", "gpio";
- pinctrl-0 = <&pinctrl_i2c2>;
- pinctrl-1 = <&pinctrl_i2c2_gpio>;
- scl-gpios = <&gpio5 16 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
- sda-gpios = <&gpio5 17 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
- status = "okay";
-
- eeprom@52 {
- compatible = "atmel,24c32";
- reg = <0x52>;
- pagesize = <32>;
- };
-};
-
-/* console */
-&uart2 {
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_uart2>;
- status = "okay";
-};
-
-/* eMMC */
-&usdhc3 {
- pinctrl-names = "default", "state_100mhz", "state_200mhz";
- pinctrl-0 = <&pinctrl_usdhc3>;
- pinctrl-1 = <&pinctrl_usdhc3_100mhz>;
- pinctrl-2 = <&pinctrl_usdhc3_200mhz>;
- bus-width = <8>;
- non-removable;
- status = "okay";
-};
-
-&wdog1 {
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_wdog>;
- fsl,ext-reset-output;
- status = "okay";
-};
-
-&iomuxc {
- pinctrl_fec1: fec1grp {
- fsl,pins = <
- MX8MM_IOMUXC_ENET_MDC_ENET1_MDC 0x3
- MX8MM_IOMUXC_ENET_MDIO_ENET1_MDIO 0x3
- MX8MM_IOMUXC_ENET_TD3_ENET1_RGMII_TD3 0x1f
- MX8MM_IOMUXC_ENET_TD2_ENET1_RGMII_TD2 0x1f
- MX8MM_IOMUXC_ENET_TD1_ENET1_RGMII_TD1 0x1f
- MX8MM_IOMUXC_ENET_TD0_ENET1_RGMII_TD0 0x1f
- MX8MM_IOMUXC_ENET_RD3_ENET1_RGMII_RD3 0x91
- MX8MM_IOMUXC_ENET_RD2_ENET1_RGMII_RD2 0x91
- MX8MM_IOMUXC_ENET_RD1_ENET1_RGMII_RD1 0x91
- MX8MM_IOMUXC_ENET_RD0_ENET1_RGMII_RD0 0x91
- MX8MM_IOMUXC_ENET_TXC_ENET1_RGMII_TXC 0x1f
- MX8MM_IOMUXC_ENET_RXC_ENET1_RGMII_RXC 0x91
- MX8MM_IOMUXC_ENET_RX_CTL_ENET1_RGMII_RX_CTL 0x91
- MX8MM_IOMUXC_ENET_TX_CTL_ENET1_RGMII_TX_CTL 0x1f
- MX8MM_IOMUXC_NAND_ALE_GPIO3_IO0 0x19
- >;
- };
-
- pinctrl_gsc: gscgrp {
- fsl,pins = <
- MX8MM_IOMUXC_SD1_DATA4_GPIO2_IO6 0x159
- >;
- };
-
- pinctrl_i2c1: i2c1grp {
- fsl,pins = <
- MX8MM_IOMUXC_I2C1_SCL_I2C1_SCL 0x400001c3
- MX8MM_IOMUXC_I2C1_SDA_I2C1_SDA 0x400001c3
- >;
- };
-
- pinctrl_i2c1_gpio: i2c1gpiogrp {
- fsl,pins = <
- MX8MM_IOMUXC_I2C1_SCL_GPIO5_IO14 0x400001c3
- MX8MM_IOMUXC_I2C1_SDA_GPIO5_IO15 0x400001c3
- >;
- };
-
- pinctrl_i2c2: i2c2grp {
- fsl,pins = <
- MX8MM_IOMUXC_I2C2_SCL_I2C2_SCL 0x400001c3
- MX8MM_IOMUXC_I2C2_SDA_I2C2_SDA 0x400001c3
- >;
- };
-
- pinctrl_i2c2_gpio: i2c2gpiogrp {
- fsl,pins = <
- MX8MM_IOMUXC_I2C2_SCL_GPIO5_IO16 0x400001c3
- MX8MM_IOMUXC_I2C2_SDA_GPIO5_IO17 0x400001c3
- >;
- };
-
- pinctrl_uart2: uart2grp {
- fsl,pins = <
- MX8MM_IOMUXC_UART2_RXD_UART2_DCE_RX 0x140
- MX8MM_IOMUXC_UART2_TXD_UART2_DCE_TX 0x140
- >;
- };
-
- pinctrl_usdhc3: usdhc3grp {
- fsl,pins = <
- MX8MM_IOMUXC_NAND_WE_B_USDHC3_CLK 0x190
- MX8MM_IOMUXC_NAND_WP_B_USDHC3_CMD 0x1d0
- MX8MM_IOMUXC_NAND_DATA04_USDHC3_DATA0 0x1d0
- MX8MM_IOMUXC_NAND_DATA05_USDHC3_DATA1 0x1d0
- MX8MM_IOMUXC_NAND_DATA06_USDHC3_DATA2 0x1d0
- MX8MM_IOMUXC_NAND_DATA07_USDHC3_DATA3 0x1d0
- MX8MM_IOMUXC_NAND_RE_B_USDHC3_DATA4 0x1d0
- MX8MM_IOMUXC_NAND_CE2_B_USDHC3_DATA5 0x1d0
- MX8MM_IOMUXC_NAND_CE3_B_USDHC3_DATA6 0x1d0
- MX8MM_IOMUXC_NAND_CLE_USDHC3_DATA7 0x1d0
- MX8MM_IOMUXC_NAND_CE1_B_USDHC3_STROBE 0x190
- >;
- };
-
- pinctrl_usdhc3_100mhz: usdhc3-100mhzgrp {
- fsl,pins = <
- MX8MM_IOMUXC_NAND_WE_B_USDHC3_CLK 0x194
- MX8MM_IOMUXC_NAND_WP_B_USDHC3_CMD 0x1d4
- MX8MM_IOMUXC_NAND_DATA04_USDHC3_DATA0 0x1d4
- MX8MM_IOMUXC_NAND_DATA05_USDHC3_DATA1 0x1d4
- MX8MM_IOMUXC_NAND_DATA06_USDHC3_DATA2 0x1d4
- MX8MM_IOMUXC_NAND_DATA07_USDHC3_DATA3 0x1d4
- MX8MM_IOMUXC_NAND_RE_B_USDHC3_DATA4 0x1d4
- MX8MM_IOMUXC_NAND_CE2_B_USDHC3_DATA5 0x1d4
- MX8MM_IOMUXC_NAND_CE3_B_USDHC3_DATA6 0x1d4
- MX8MM_IOMUXC_NAND_CLE_USDHC3_DATA7 0x1d4
- MX8MM_IOMUXC_NAND_CE1_B_USDHC3_STROBE 0x194
- >;
- };
-
- pinctrl_usdhc3_200mhz: usdhc3-200mhzgrp {
- fsl,pins = <
- MX8MM_IOMUXC_NAND_WE_B_USDHC3_CLK 0x196
- MX8MM_IOMUXC_NAND_WP_B_USDHC3_CMD 0x1d6
- MX8MM_IOMUXC_NAND_DATA04_USDHC3_DATA0 0x1d6
- MX8MM_IOMUXC_NAND_DATA05_USDHC3_DATA1 0x1d6
- MX8MM_IOMUXC_NAND_DATA06_USDHC3_DATA2 0x1d6
- MX8MM_IOMUXC_NAND_DATA07_USDHC3_DATA3 0x1d6
- MX8MM_IOMUXC_NAND_RE_B_USDHC3_DATA4 0x1d6
- MX8MM_IOMUXC_NAND_CE2_B_USDHC3_DATA5 0x1d6
- MX8MM_IOMUXC_NAND_CE3_B_USDHC3_DATA6 0x1d6
- MX8MM_IOMUXC_NAND_CLE_USDHC3_DATA7 0x1d6
- MX8MM_IOMUXC_NAND_CE1_B_USDHC3_STROBE 0x196
- >;
- };
-
- pinctrl_wdog: wdoggrp {
- fsl,pins = <
- MX8MM_IOMUXC_GPIO1_IO02_WDOG1_WDOG_B 0xc6
- >;
- };
-};
diff --git a/arch/arm/dts/imx8mm-venice-gw71xx-0x-u-boot.dtsi b/arch/arm/dts/imx8mm-venice-gw71xx-0x-u-boot.dtsi
index b359233..07789c8 100644
--- a/arch/arm/dts/imx8mm-venice-gw71xx-0x-u-boot.dtsi
+++ b/arch/arm/dts/imx8mm-venice-gw71xx-0x-u-boot.dtsi
@@ -25,6 +25,13 @@
gpios = <9 GPIO_ACTIVE_HIGH>;
line-name = "dio1";
};
+
+ tpm_rst {
+ gpio-hog;
+ output-high;
+ gpios = <11 GPIO_ACTIVE_HIGH>;
+ line-name = "tpm_rst#";
+ };
};
&gpio4 {
diff --git a/arch/arm/dts/imx8mm-venice-gw71xx-0x.dts b/arch/arm/dts/imx8mm-venice-gw71xx-0x.dts
deleted file mode 100644
index 3f88c4a..0000000
--- a/arch/arm/dts/imx8mm-venice-gw71xx-0x.dts
+++ /dev/null
@@ -1,19 +0,0 @@
-// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
-/*
- * Copyright 2020 Gateworks Corporation
- */
-
-/dts-v1/;
-
-#include "imx8mm.dtsi"
-#include "imx8mm-venice-gw700x.dtsi"
-#include "imx8mm-venice-gw71xx.dtsi"
-
-/ {
- model = "Gateworks Venice GW71xx-0x i.MX8MM Development Kit";
- compatible = "gw,imx8mm-gw71xx-0x", "fsl,imx8mm";
-
- chosen {
- stdout-path = &uart2;
- };
-};
diff --git a/arch/arm/dts/imx8mm-venice-gw71xx.dtsi b/arch/arm/dts/imx8mm-venice-gw71xx.dtsi
deleted file mode 100644
index c557dbf..0000000
--- a/arch/arm/dts/imx8mm-venice-gw71xx.dtsi
+++ /dev/null
@@ -1,239 +0,0 @@
-// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
-/*
- * Copyright 2020 Gateworks Corporation
- */
-
-#include <dt-bindings/gpio/gpio.h>
-#include <dt-bindings/leds/common.h>
-#include <dt-bindings/phy/phy-imx8-pcie.h>
-
-/ {
- aliases {
- usb0 = &usbotg1;
- usb1 = &usbotg2;
- };
-
- led-controller {
- compatible = "gpio-leds";
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_gpio_leds>;
-
- led-0 {
- function = LED_FUNCTION_STATUS;
- color = <LED_COLOR_ID_GREEN>;
- gpios = <&gpio5 5 GPIO_ACTIVE_HIGH>;
- default-state = "on";
- linux,default-trigger = "heartbeat";
- };
-
- led-1 {
- function = LED_FUNCTION_STATUS;
- color = <LED_COLOR_ID_RED>;
- gpios = <&gpio5 4 GPIO_ACTIVE_HIGH>;
- default-state = "off";
- };
- };
-
- pcie0_refclk: pcie0-refclk {
- compatible = "fixed-clock";
- #clock-cells = <0>;
- clock-frequency = <100000000>;
- };
-
- pps {
- compatible = "pps-gpio";
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_pps>;
- gpios = <&gpio1 15 GPIO_ACTIVE_HIGH>;
- status = "okay";
- };
-
- reg_usb_otg1_vbus: regulator-usb-otg1 {
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_reg_usb1_en>;
- compatible = "regulator-fixed";
- regulator-name = "usb_otg1_vbus";
- gpio = <&gpio1 10 GPIO_ACTIVE_HIGH>;
- enable-active-high;
- regulator-min-microvolt = <5000000>;
- regulator-max-microvolt = <5000000>;
- };
-};
-
-/* off-board header */
-&ecspi2 {
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_spi2>;
- cs-gpios = <&gpio5 13 GPIO_ACTIVE_LOW>;
- status = "okay";
-};
-
-&gpio1 {
- gpio-line-names = "", "", "", "", "", "", "pci_usb_sel", "dio0",
- "", "dio1", "", "", "", "", "", "",
- "", "", "", "", "", "", "", "",
- "", "", "", "", "", "", "", "";
-};
-
-&gpio4 {
- gpio-line-names = "", "", "", "dio2", "dio3", "", "", "pci_wdis#",
- "", "", "", "", "", "", "", "",
- "", "", "", "", "", "", "", "",
- "", "", "", "", "", "", "", "";
-};
-
-&i2c2 {
- clock-frequency = <400000>;
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_i2c2>;
- status = "okay";
-
- accelerometer@19 {
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_accel>;
- compatible = "st,lis2de12";
- reg = <0x19>;
- st,drdy-int-pin = <1>;
- interrupt-parent = <&gpio4>;
- interrupts = <5 IRQ_TYPE_LEVEL_LOW>;
- interrupt-names = "INT1";
- };
-};
-
-/* off-board header */
-&i2c3 {
- clock-frequency = <400000>;
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_i2c3>;
- status = "okay";
-};
-
-&pcie_phy {
- fsl,refclk-pad-mode = <IMX8_PCIE_REFCLK_PAD_INPUT>;
- fsl,clkreq-unsupported;
- clocks = <&pcie0_refclk>;
- clock-names = "ref";
- status = "okay";
-};
-
-&pcie0 {
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_pcie0>;
- reset-gpio = <&gpio4 6 GPIO_ACTIVE_LOW>;
- clocks = <&clk IMX8MM_CLK_PCIE1_ROOT>, <&clk IMX8MM_CLK_PCIE1_AUX>,
- <&pcie0_refclk>;
- clock-names = "pcie", "pcie_aux", "pcie_bus";
- assigned-clocks = <&clk IMX8MM_CLK_PCIE1_AUX>,
- <&clk IMX8MM_CLK_PCIE1_CTRL>;
- assigned-clock-rates = <10000000>, <250000000>;
- assigned-clock-parents = <&clk IMX8MM_SYS_PLL2_50M>,
- <&clk IMX8MM_SYS_PLL2_250M>;
- status = "okay";
-};
-
-/* GPS */
-&uart1 {
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_uart1>;
- status = "okay";
-};
-
-/* off-board header */
-&uart3 {
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_uart3>;
- status = "okay";
-};
-
-&usbotg1 {
- dr_mode = "otg";
- over-current-active-low;
- vbus-supply = <®_usb_otg1_vbus>;
- status = "okay";
-};
-
-&usbotg2 {
- dr_mode = "host";
- disable-over-current;
- status = "okay";
-};
-
-&iomuxc {
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_hog>;
-
- pinctrl_hog: hoggrp {
- fsl,pins = <
- MX8MM_IOMUXC_SPDIF_TX_GPIO5_IO3 0x40000041 /* PLUG_TEST */
- MX8MM_IOMUXC_GPIO1_IO06_GPIO1_IO6 0x40000041 /* PCI_USBSEL */
- MX8MM_IOMUXC_SAI1_RXD5_GPIO4_IO7 0x40000041 /* PCIE_WDIS# */
- MX8MM_IOMUXC_GPIO1_IO07_GPIO1_IO7 0x40000041 /* DIO0 */
- MX8MM_IOMUXC_GPIO1_IO09_GPIO1_IO9 0x40000041 /* DIO1 */
- MX8MM_IOMUXC_SAI1_RXD1_GPIO4_IO3 0x40000041 /* DIO2 */
- MX8MM_IOMUXC_SAI1_RXD2_GPIO4_IO4 0x40000041 /* DIO2 */
- >;
- };
-
- pinctrl_accel: accelgrp {
- fsl,pins = <
- MX8MM_IOMUXC_SAI1_RXD3_GPIO4_IO5 0x159
- >;
- };
-
- pinctrl_gpio_leds: gpioledgrp {
- fsl,pins = <
- MX8MM_IOMUXC_SPDIF_EXT_CLK_GPIO5_IO5 0x19
- MX8MM_IOMUXC_SPDIF_RX_GPIO5_IO4 0x19
- >;
- };
-
- pinctrl_i2c3: i2c3grp {
- fsl,pins = <
- MX8MM_IOMUXC_I2C3_SCL_I2C3_SCL 0x400001c3
- MX8MM_IOMUXC_I2C3_SDA_I2C3_SDA 0x400001c3
- >;
- };
-
- pinctrl_pcie0: pcie0grp {
- fsl,pins = <
- MX8MM_IOMUXC_SAI1_RXD4_GPIO4_IO6 0x41
- >;
- };
-
- pinctrl_pps: ppsgrp {
- fsl,pins = <
- MX8MM_IOMUXC_GPIO1_IO15_GPIO1_IO15 0x41
- >;
- };
-
- pinctrl_reg_usb1_en: regusb1grp {
- fsl,pins = <
- MX8MM_IOMUXC_GPIO1_IO10_GPIO1_IO10 0x41
- MX8MM_IOMUXC_GPIO1_IO12_GPIO1_IO12 0x141
- MX8MM_IOMUXC_GPIO1_IO13_USB1_OTG_OC 0x41
- >;
- };
-
- pinctrl_spi2: spi2grp {
- fsl,pins = <
- MX8MM_IOMUXC_ECSPI2_SCLK_ECSPI2_SCLK 0xd6
- MX8MM_IOMUXC_ECSPI2_MOSI_ECSPI2_MOSI 0xd6
- MX8MM_IOMUXC_ECSPI2_MISO_ECSPI2_MISO 0xd6
- MX8MM_IOMUXC_ECSPI2_SS0_GPIO5_IO13 0xd6
- >;
- };
-
- pinctrl_uart1: uart1grp {
- fsl,pins = <
- MX8MM_IOMUXC_UART1_RXD_UART1_DCE_RX 0x140
- MX8MM_IOMUXC_UART1_TXD_UART1_DCE_TX 0x140
- >;
- };
-
- pinctrl_uart3: uart3grp {
- fsl,pins = <
- MX8MM_IOMUXC_UART3_RXD_UART3_DCE_RX 0x140
- MX8MM_IOMUXC_UART3_TXD_UART3_DCE_TX 0x140
- >;
- };
-};
diff --git a/arch/arm/dts/imx8mm-venice-gw72xx-0x.dts b/arch/arm/dts/imx8mm-venice-gw72xx-0x.dts
deleted file mode 100644
index 641be3a..0000000
--- a/arch/arm/dts/imx8mm-venice-gw72xx-0x.dts
+++ /dev/null
@@ -1,19 +0,0 @@
-// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
-/*
- * Copyright 2020 Gateworks Corporation
- */
-
-/dts-v1/;
-
-#include "imx8mm.dtsi"
-#include "imx8mm-venice-gw700x.dtsi"
-#include "imx8mm-venice-gw72xx.dtsi"
-
-/ {
- model = "Gateworks Venice GW72xx-0x i.MX8MM Development Kit";
- compatible = "gw,imx8mm-gw72xx-0x", "fsl,imx8mm";
-
- chosen {
- stdout-path = &uart2;
- };
-};
diff --git a/arch/arm/dts/imx8mm-venice-gw72xx.dtsi b/arch/arm/dts/imx8mm-venice-gw72xx.dtsi
deleted file mode 100644
index 97ed34a..0000000
--- a/arch/arm/dts/imx8mm-venice-gw72xx.dtsi
+++ /dev/null
@@ -1,400 +0,0 @@
-// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
-/*
- * Copyright 2020 Gateworks Corporation
- */
-
-#include <dt-bindings/gpio/gpio.h>
-#include <dt-bindings/leds/common.h>
-#include <dt-bindings/phy/phy-imx8-pcie.h>
-
-/ {
- aliases {
- ethernet1 = ð1;
- usb0 = &usbotg1;
- usb1 = &usbotg2;
- };
-
- led-controller {
- compatible = "gpio-leds";
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_gpio_leds>;
-
- led-0 {
- function = LED_FUNCTION_STATUS;
- color = <LED_COLOR_ID_GREEN>;
- gpios = <&gpio5 5 GPIO_ACTIVE_HIGH>;
- default-state = "on";
- linux,default-trigger = "heartbeat";
- };
-
- led-1 {
- function = LED_FUNCTION_STATUS;
- color = <LED_COLOR_ID_RED>;
- gpios = <&gpio5 4 GPIO_ACTIVE_HIGH>;
- default-state = "off";
- };
- };
-
- pcie0_refclk: pcie0-refclk {
- compatible = "fixed-clock";
- #clock-cells = <0>;
- clock-frequency = <100000000>;
- };
-
- pps {
- compatible = "pps-gpio";
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_pps>;
- gpios = <&gpio1 15 GPIO_ACTIVE_HIGH>;
- status = "okay";
- };
-
- reg_3p3v: regulator-3p3v {
- compatible = "regulator-fixed";
- regulator-name = "3P3V";
- regulator-min-microvolt = <3300000>;
- regulator-max-microvolt = <3300000>;
- regulator-always-on;
- };
-
- reg_usb_otg1_vbus: regulator-usb-otg1 {
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_reg_usb1_en>;
- compatible = "regulator-fixed";
- regulator-name = "usb_otg1_vbus";
- gpio = <&gpio1 12 GPIO_ACTIVE_HIGH>;
- enable-active-high;
- regulator-min-microvolt = <5000000>;
- regulator-max-microvolt = <5000000>;
- };
-
- reg_usb_otg2_vbus: regulator-usb-otg2 {
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_reg_usb2_en>;
- compatible = "regulator-fixed";
- regulator-name = "usb_otg2_vbus";
- gpio = <&gpio1 8 GPIO_ACTIVE_HIGH>;
- enable-active-high;
- regulator-min-microvolt = <5000000>;
- regulator-max-microvolt = <5000000>;
- };
-};
-
-/* off-board header */
-&ecspi2 {
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_spi2>;
- cs-gpios = <&gpio5 13 GPIO_ACTIVE_LOW>,
- <&gpio1 10 GPIO_ACTIVE_LOW>;
- status = "okay";
-
- tpm@1 {
- compatible = "tcg,tpm_tis-spi";
- reg = <0x1>;
- spi-max-frequency = <36000000>;
- };
-};
-
-&gpio1 {
- gpio-line-names = "rs485_term", "mipi_gpio4", "", "",
- "", "", "pci_usb_sel", "dio0",
- "", "dio1", "", "", "", "", "", "",
- "", "", "", "", "", "", "", "",
- "", "", "", "", "", "", "", "";
-};
-
-&gpio4 {
- gpio-line-names = "rs485_en", "mipi_gpio3", "rs485_hd", "mipi_gpio2",
- "mipi_gpio1", "", "", "pci_wdis#",
- "", "", "", "", "", "", "", "",
- "", "", "", "", "", "", "", "",
- "", "", "", "", "", "", "", "";
-};
-
-&i2c2 {
- clock-frequency = <400000>;
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_i2c2>;
- status = "okay";
-
- accelerometer@19 {
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_accel>;
- compatible = "st,lis2de12";
- reg = <0x19>;
- st,drdy-int-pin = <1>;
- interrupt-parent = <&gpio4>;
- interrupts = <5 IRQ_TYPE_LEVEL_LOW>;
- interrupt-names = "INT1";
- };
-};
-
-/* off-board header */
-&i2c3 {
- clock-frequency = <400000>;
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_i2c3>;
- status = "okay";
-};
-
-&pcie_phy {
- fsl,refclk-pad-mode = <IMX8_PCIE_REFCLK_PAD_INPUT>;
- fsl,clkreq-unsupported;
- clocks = <&pcie0_refclk>;
- clock-names = "ref";
- status = "okay";
-};
-
-&pcie0 {
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_pcie0>;
- reset-gpio = <&gpio4 6 GPIO_ACTIVE_LOW>;
- clocks = <&clk IMX8MM_CLK_PCIE1_ROOT>, <&clk IMX8MM_CLK_PCIE1_AUX>,
- <&pcie0_refclk>;
- clock-names = "pcie", "pcie_aux", "pcie_bus";
- assigned-clocks = <&clk IMX8MM_CLK_PCIE1_AUX>,
- <&clk IMX8MM_CLK_PCIE1_CTRL>;
- assigned-clock-rates = <10000000>, <250000000>;
- assigned-clock-parents = <&clk IMX8MM_SYS_PLL2_50M>,
- <&clk IMX8MM_SYS_PLL2_250M>;
- status = "okay";
-
- pcie@0,0 {
- reg = <0x0000 0 0 0 0>;
- #address-cells = <1>;
- #size-cells = <0>;
-
- pcie@1,0 {
- reg = <0x0000 0 0 0 0>;
- #address-cells = <1>;
- #size-cells = <0>;
-
- pcie@2,3 {
- reg = <0x1800 0 0 0 0>;
- #address-cells = <1>;
- #size-cells = <0>;
-
- eth1: pcie@5,0 {
- reg = <0x0000 0 0 0 0>;
- #address-cells = <1>;
- #size-cells = <0>;
-
- local-mac-address = [00 00 00 00 00 00];
- };
- };
- };
- };
-};
-
-/* off-board header */
-&sai3 {
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_sai3>;
- assigned-clocks = <&clk IMX8MM_CLK_SAI3>;
- assigned-clock-parents = <&clk IMX8MM_AUDIO_PLL1_OUT>;
- assigned-clock-rates = <24576000>;
- status = "okay";
-};
-
-/* GPS */
-&uart1 {
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_uart1>;
- status = "okay";
-};
-
-/* off-board header */
-&uart3 {
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_uart3>;
- status = "okay";
-};
-
-/* RS232 */
-&uart4 {
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_uart4>;
- status = "okay";
-};
-
-&usbotg1 {
- dr_mode = "otg";
- over-current-active-low;
- vbus-supply = <®_usb_otg1_vbus>;
- status = "okay";
-};
-
-&usbotg2 {
- dr_mode = "host";
- disable-over-current;
- vbus-supply = <®_usb_otg2_vbus>;
- status = "okay";
-};
-
-/* microSD */
-&usdhc2 {
- pinctrl-names = "default", "state_100mhz", "state_200mhz";
- pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>;
- pinctrl-1 = <&pinctrl_usdhc2_100mhz>, <&pinctrl_usdhc2_gpio>;
- pinctrl-2 = <&pinctrl_usdhc2_200mhz>, <&pinctrl_usdhc2_gpio>;
- cd-gpios = <&gpio2 12 GPIO_ACTIVE_LOW>;
- bus-width = <4>;
- vmmc-supply = <®_3p3v>;
- status = "okay";
-};
-
-&iomuxc {
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_hog>;
-
- pinctrl_hog: hoggrp {
- fsl,pins = <
- MX8MM_IOMUXC_SPDIF_TX_GPIO5_IO3 0x40000041 /* PLUG_TEST */
- MX8MM_IOMUXC_GPIO1_IO06_GPIO1_IO6 0x40000041 /* PCI_USBSEL */
- MX8MM_IOMUXC_SAI1_RXD5_GPIO4_IO7 0x40000041 /* PCIE_WDIS# */
- MX8MM_IOMUXC_GPIO1_IO07_GPIO1_IO7 0x40000041 /* DIO0 */
- MX8MM_IOMUXC_GPIO1_IO09_GPIO1_IO9 0x40000041 /* DIO1 */
- MX8MM_IOMUXC_GPIO1_IO00_GPIO1_IO0 0x40000104 /* RS485_TERM */
- MX8MM_IOMUXC_SAI1_RXFS_GPIO4_IO0 0x40000104 /* RS485 */
- MX8MM_IOMUXC_SAI1_RXD0_GPIO4_IO2 0x40000104 /* RS485_HALF */
- >;
- };
-
- pinctrl_accel: accelgrp {
- fsl,pins = <
- MX8MM_IOMUXC_SAI1_RXD3_GPIO4_IO5 0x159
- >;
- };
-
- pinctrl_gpio_leds: gpioledgrp {
- fsl,pins = <
- MX8MM_IOMUXC_SPDIF_EXT_CLK_GPIO5_IO5 0x19
- MX8MM_IOMUXC_SPDIF_RX_GPIO5_IO4 0x19
- >;
- };
-
- pinctrl_i2c3: i2c3grp {
- fsl,pins = <
- MX8MM_IOMUXC_I2C3_SCL_I2C3_SCL 0x400001c3
- MX8MM_IOMUXC_I2C3_SDA_I2C3_SDA 0x400001c3
- >;
- };
-
- pinctrl_pcie0: pcie0grp {
- fsl,pins = <
- MX8MM_IOMUXC_SAI1_RXD4_GPIO4_IO6 0x41
- >;
- };
-
- pinctrl_pps: ppsgrp {
- fsl,pins = <
- MX8MM_IOMUXC_GPIO1_IO15_GPIO1_IO15 0x41
- >;
- };
-
- pinctrl_reg_usb1_en: regusb1grp {
- fsl,pins = <
- MX8MM_IOMUXC_GPIO1_IO12_GPIO1_IO12 0x41
- MX8MM_IOMUXC_GPIO1_IO13_USB1_OTG_OC 0x41
- >;
- };
-
- pinctrl_reg_usb2_en: regusb2grp {
- fsl,pins = <
- MX8MM_IOMUXC_GPIO1_IO08_GPIO1_IO8 0x41
- >;
- };
-
- pinctrl_sai3: sai3grp {
- fsl,pins = <
- MX8MM_IOMUXC_SAI3_TXFS_SAI3_TX_SYNC 0xd6
- MX8MM_IOMUXC_SAI3_TXC_SAI3_TX_BCLK 0xd6
- MX8MM_IOMUXC_SAI3_MCLK_SAI3_MCLK 0xd6
- MX8MM_IOMUXC_SAI3_TXD_SAI3_TX_DATA0 0xd6
- MX8MM_IOMUXC_SAI3_RXD_SAI3_RX_DATA0 0xd6
- >;
- };
-
- pinctrl_spi2: spi2grp {
- fsl,pins = <
- MX8MM_IOMUXC_ECSPI2_SCLK_ECSPI2_SCLK 0xd6
- MX8MM_IOMUXC_ECSPI2_MOSI_ECSPI2_MOSI 0xd6
- MX8MM_IOMUXC_ECSPI2_MISO_ECSPI2_MISO 0xd6
- MX8MM_IOMUXC_ECSPI2_SS0_GPIO5_IO13 0xd6
- MX8MM_IOMUXC_GPIO1_IO10_GPIO1_IO10 0xd6
- >;
- };
-
- pinctrl_uart1: uart1grp {
- fsl,pins = <
- MX8MM_IOMUXC_UART1_RXD_UART1_DCE_RX 0x140
- MX8MM_IOMUXC_UART1_TXD_UART1_DCE_TX 0x140
- >;
- };
-
- pinctrl_uart3: uart3grp {
- fsl,pins = <
- MX8MM_IOMUXC_UART3_RXD_UART3_DCE_RX 0x140
- MX8MM_IOMUXC_UART3_TXD_UART3_DCE_TX 0x140
- >;
- };
-
- pinctrl_uart4: uart4grp {
- fsl,pins = <
- MX8MM_IOMUXC_UART4_RXD_UART4_DCE_RX 0x140
- MX8MM_IOMUXC_UART4_TXD_UART4_DCE_TX 0x140
- >;
- };
-
- pinctrl_usdhc1: usdhc1grp {
- fsl,pins = <
- MX8MM_IOMUXC_SD1_CLK_USDHC1_CLK 0x190
- MX8MM_IOMUXC_SD1_CMD_USDHC1_CMD 0x1d0
- MX8MM_IOMUXC_SD1_DATA0_USDHC1_DATA0 0x1d0
- MX8MM_IOMUXC_SD1_DATA1_USDHC1_DATA1 0x1d0
- MX8MM_IOMUXC_SD1_DATA2_USDHC1_DATA2 0x1d0
- MX8MM_IOMUXC_SD1_DATA3_USDHC1_DATA3 0x1d0
- >;
- };
-
- pinctrl_usdhc2: usdhc2grp {
- fsl,pins = <
- MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK 0x190
- MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d0
- MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d0
- MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d0
- MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d0
- MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d0
- >;
- };
-
- pinctrl_usdhc2_100mhz: usdhc2-100mhzgrp {
- fsl,pins = <
- MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK 0x194
- MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d4
- MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d4
- MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d4
- MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d4
- MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d4
- >;
- };
-
- pinctrl_usdhc2_200mhz: usdhc2-200mhzgrp {
- fsl,pins = <
- MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK 0x196
- MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d6
- MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d6
- MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d6
- MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d6
- MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d6
- >;
- };
-
- pinctrl_usdhc2_gpio: usdhc2gpiogrp {
- fsl,pins = <
- MX8MM_IOMUXC_SD2_CD_B_GPIO2_IO12 0x1c4
- MX8MM_IOMUXC_SD2_RESET_B_USDHC2_RESET_B 0x1d0
- MX8MM_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0x1d0
- >;
- };
-};
diff --git a/arch/arm/dts/imx8mm-venice-gw73xx-0x.dts b/arch/arm/dts/imx8mm-venice-gw73xx-0x.dts
deleted file mode 100644
index 6905437..0000000
--- a/arch/arm/dts/imx8mm-venice-gw73xx-0x.dts
+++ /dev/null
@@ -1,19 +0,0 @@
-// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
-/*
- * Copyright 2020 Gateworks Corporation
- */
-
-/dts-v1/;
-
-#include "imx8mm.dtsi"
-#include "imx8mm-venice-gw700x.dtsi"
-#include "imx8mm-venice-gw73xx.dtsi"
-
-/ {
- model = "Gateworks Venice GW73xx-0x i.MX8MM Development Kit";
- compatible = "gw,imx8mm-gw73xx-0x", "fsl,imx8mm";
-
- chosen {
- stdout-path = &uart2;
- };
-};
diff --git a/arch/arm/dts/imx8mm-venice-gw73xx.dtsi b/arch/arm/dts/imx8mm-venice-gw73xx.dtsi
deleted file mode 100644
index 7b2130d..0000000
--- a/arch/arm/dts/imx8mm-venice-gw73xx.dtsi
+++ /dev/null
@@ -1,452 +0,0 @@
-// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
-/*
- * Copyright 2020 Gateworks Corporation
- */
-
-#include <dt-bindings/gpio/gpio.h>
-#include <dt-bindings/leds/common.h>
-#include <dt-bindings/phy/phy-imx8-pcie.h>
-
-/ {
- aliases {
- ethernet1 = ð1;
- usb0 = &usbotg1;
- usb1 = &usbotg2;
- };
-
- led-controller {
- compatible = "gpio-leds";
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_gpio_leds>;
-
- led-0 {
- function = LED_FUNCTION_STATUS;
- color = <LED_COLOR_ID_GREEN>;
- gpios = <&gpio5 5 GPIO_ACTIVE_HIGH>;
- default-state = "on";
- linux,default-trigger = "heartbeat";
- };
-
- led-1 {
- function = LED_FUNCTION_STATUS;
- color = <LED_COLOR_ID_RED>;
- gpios = <&gpio5 4 GPIO_ACTIVE_HIGH>;
- default-state = "off";
- };
- };
-
- pcie0_refclk: pcie0-refclk {
- compatible = "fixed-clock";
- #clock-cells = <0>;
- clock-frequency = <100000000>;
- };
-
- pps {
- compatible = "pps-gpio";
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_pps>;
- gpios = <&gpio1 15 GPIO_ACTIVE_HIGH>;
- status = "okay";
- };
-
- reg_1p8v: regulator-1p8v {
- compatible = "regulator-fixed";
- regulator-name = "1P8V";
- regulator-min-microvolt = <1800000>;
- regulator-max-microvolt = <1800000>;
- regulator-always-on;
- };
-
- reg_3p3v: regulator-3p3v {
- compatible = "regulator-fixed";
- regulator-name = "3P3V";
- regulator-min-microvolt = <3300000>;
- regulator-max-microvolt = <3300000>;
- regulator-always-on;
- };
-
- reg_usb_otg1_vbus: regulator-usb-otg1 {
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_reg_usb1_en>;
- compatible = "regulator-fixed";
- regulator-name = "usb_otg1_vbus";
- gpio = <&gpio1 12 GPIO_ACTIVE_HIGH>;
- enable-active-high;
- regulator-min-microvolt = <5000000>;
- regulator-max-microvolt = <5000000>;
- };
-
- reg_usb_otg2_vbus: regulator-usb-otg2 {
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_reg_usb2_en>;
- compatible = "regulator-fixed";
- regulator-name = "usb_otg2_vbus";
- gpio = <&gpio1 8 GPIO_ACTIVE_HIGH>;
- enable-active-high;
- regulator-min-microvolt = <5000000>;
- regulator-max-microvolt = <5000000>;
- };
-
- reg_wifi_en: regulator-wifi-en {
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_reg_wl>;
- compatible = "regulator-fixed";
- regulator-name = "wl";
- gpio = <&gpio1 5 GPIO_ACTIVE_HIGH>;
- startup-delay-us = <100>;
- enable-active-high;
- regulator-min-microvolt = <3300000>;
- regulator-max-microvolt = <3300000>;
- };
-};
-
-/* off-board header */
-&ecspi2 {
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_spi2>;
- cs-gpios = <&gpio5 13 GPIO_ACTIVE_LOW>,
- <&gpio1 10 GPIO_ACTIVE_LOW>;
- status = "okay";
-
- tpm@1 {
- compatible = "tcg,tpm_tis-spi";
- reg = <0x1>;
- spi-max-frequency = <36000000>;
- };
-};
-
-&gpio1 {
- gpio-line-names = "rs485_term", "mipi_gpio4", "", "",
- "", "", "pci_usb_sel", "dio0",
- "", "dio1", "", "", "", "", "", "",
- "", "", "", "", "", "", "", "",
- "", "", "", "", "", "", "", "";
-};
-
-&gpio4 {
- gpio-line-names = "rs485_en", "mipi_gpio3", "rs485_hd", "mipi_gpio2",
- "mipi_gpio1", "", "", "pci_wdis#",
- "", "", "", "", "", "", "", "",
- "", "", "", "", "", "", "", "",
- "", "", "", "", "", "", "", "";
-};
-
-&i2c2 {
- clock-frequency = <400000>;
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_i2c2>;
- status = "okay";
-
- accelerometer@19 {
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_accel>;
- compatible = "st,lis2de12";
- reg = <0x19>;
- st,drdy-int-pin = <1>;
- interrupt-parent = <&gpio4>;
- interrupts = <5 IRQ_TYPE_LEVEL_LOW>;
- interrupt-names = "INT1";
- };
-};
-
-/* off-board header */
-&i2c3 {
- clock-frequency = <400000>;
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_i2c3>;
- status = "okay";
-};
-
-&pcie_phy {
- fsl,refclk-pad-mode = <IMX8_PCIE_REFCLK_PAD_INPUT>;
- fsl,clkreq-unsupported;
- clocks = <&pcie0_refclk>;
- clock-names = "ref";
- status = "okay";
-};
-
-&pcie0 {
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_pcie0>;
- reset-gpio = <&gpio4 6 GPIO_ACTIVE_LOW>;
- clocks = <&clk IMX8MM_CLK_PCIE1_ROOT>, <&clk IMX8MM_CLK_PCIE1_AUX>,
- <&pcie0_refclk>;
- clock-names = "pcie", "pcie_aux", "pcie_bus";
- assigned-clocks = <&clk IMX8MM_CLK_PCIE1_AUX>,
- <&clk IMX8MM_CLK_PCIE1_CTRL>;
- assigned-clock-rates = <10000000>, <250000000>;
- assigned-clock-parents = <&clk IMX8MM_SYS_PLL2_50M>,
- <&clk IMX8MM_SYS_PLL2_250M>;
- status = "okay";
-
- pcie@0,0 {
- reg = <0x0000 0 0 0 0>;
- #address-cells = <1>;
- #size-cells = <0>;
-
- pcie@1,0 {
- reg = <0x0000 0 0 0 0>;
- #address-cells = <1>;
- #size-cells = <0>;
-
- pcie@2,4 {
- reg = <0x2000 0 0 0 0>;
- #address-cells = <1>;
- #size-cells = <0>;
-
- eth1: pcie@6,0 {
- reg = <0x0000 0 0 0 0>;
- #address-cells = <1>;
- #size-cells = <0>;
-
- local-mac-address = [00 00 00 00 00 00];
- };
- };
- };
- };
-};
-
-/* off-board header */
-&sai3 {
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_sai3>;
- assigned-clocks = <&clk IMX8MM_CLK_SAI3>;
- assigned-clock-parents = <&clk IMX8MM_AUDIO_PLL1_OUT>;
- assigned-clock-rates = <24576000>;
- status = "okay";
-};
-
-/* GPS */
-&uart1 {
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_uart1>;
- status = "okay";
-};
-
-/* bluetooth HCI */
-&uart3 {
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_uart3>, <&pinctrl_bten>;
- cts-gpios = <&gpio5 8 GPIO_ACTIVE_LOW>;
- rts-gpios = <&gpio5 9 GPIO_ACTIVE_LOW>;
- uart-has-rtscts;
- status = "okay";
-
- bluetooth {
- compatible = "brcm,bcm4330-bt";
- shutdown-gpios = <&gpio1 3 GPIO_ACTIVE_HIGH>;
- };
-};
-
-/* RS232 */
-&uart4 {
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_uart4>;
- status = "okay";
-};
-
-&usbotg1 {
- dr_mode = "otg";
- over-current-active-low;
- vbus-supply = <®_usb_otg1_vbus>;
- status = "okay";
-};
-
-&usbotg2 {
- dr_mode = "host";
- disable-over-current;
- vbus-supply = <®_usb_otg2_vbus>;
- status = "okay";
-};
-
-/* SDIO WiFi */
-&usdhc1 {
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_usdhc1>;
- bus-width = <4>;
- non-removable;
- vmmc-supply = <®_wifi_en>;
- status = "okay";
-};
-
-/* microSD */
-&usdhc2 {
- pinctrl-names = "default", "state_100mhz", "state_200mhz";
- pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>;
- pinctrl-1 = <&pinctrl_usdhc2_100mhz>, <&pinctrl_usdhc2_gpio>;
- pinctrl-2 = <&pinctrl_usdhc2_200mhz>, <&pinctrl_usdhc2_gpio>;
- cd-gpios = <&gpio2 12 GPIO_ACTIVE_LOW>;
- bus-width = <4>;
- vmmc-supply = <®_3p3v>;
- status = "okay";
-};
-
-&iomuxc {
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_hog>;
-
- pinctrl_hog: hoggrp {
- fsl,pins = <
- MX8MM_IOMUXC_SPDIF_TX_GPIO5_IO3 0x40000041 /* PLUG_TEST */
- MX8MM_IOMUXC_GPIO1_IO06_GPIO1_IO6 0x40000041 /* PCI_USBSEL */
- MX8MM_IOMUXC_SAI1_RXD5_GPIO4_IO7 0x40000041 /* PCIE_WDIS# */
- MX8MM_IOMUXC_GPIO1_IO07_GPIO1_IO7 0x40000041 /* DIO0 */
- MX8MM_IOMUXC_GPIO1_IO09_GPIO1_IO9 0x40000041 /* DIO1 */
- MX8MM_IOMUXC_GPIO1_IO00_GPIO1_IO0 0x40000104 /* RS485_TERM */
- MX8MM_IOMUXC_SAI1_RXFS_GPIO4_IO0 0x40000104 /* RS485 */
- MX8MM_IOMUXC_SAI1_RXD0_GPIO4_IO2 0x40000104 /* RS485_HALF */
- >;
- };
-
- pinctrl_accel: accelgrp {
- fsl,pins = <
- MX8MM_IOMUXC_SAI1_RXD3_GPIO4_IO5 0x159
- >;
- };
-
- pinctrl_bten: btengrp {
- fsl,pins = <
- MX8MM_IOMUXC_GPIO1_IO03_GPIO1_IO3 0x41
- >;
- };
-
- pinctrl_gpio_leds: gpioledgrp {
- fsl,pins = <
- MX8MM_IOMUXC_SPDIF_EXT_CLK_GPIO5_IO5 0x19
- MX8MM_IOMUXC_SPDIF_RX_GPIO5_IO4 0x19
- >;
- };
-
- pinctrl_i2c3: i2c3grp {
- fsl,pins = <
- MX8MM_IOMUXC_I2C3_SCL_I2C3_SCL 0x400001c3
- MX8MM_IOMUXC_I2C3_SDA_I2C3_SDA 0x400001c3
- >;
- };
-
- pinctrl_pcie0: pcie0grp {
- fsl,pins = <
- MX8MM_IOMUXC_SAI1_RXD4_GPIO4_IO6 0x41
- >;
- };
-
- pinctrl_pps: ppsgrp {
- fsl,pins = <
- MX8MM_IOMUXC_GPIO1_IO15_GPIO1_IO15 0x41
- >;
- };
-
- pinctrl_reg_wl: regwlgrp {
- fsl,pins = <
- MX8MM_IOMUXC_GPIO1_IO05_GPIO1_IO5 0x41
- >;
- };
-
- pinctrl_reg_usb1_en: regusb1grp {
- fsl,pins = <
- MX8MM_IOMUXC_GPIO1_IO12_GPIO1_IO12 0x41
- MX8MM_IOMUXC_GPIO1_IO13_USB1_OTG_OC 0x41
- >;
- };
-
- pinctrl_reg_usb2_en: regusb2grp {
- fsl,pins = <
- MX8MM_IOMUXC_GPIO1_IO08_GPIO1_IO8 0x41
- >;
- };
-
- pinctrl_sai3: sai3grp {
- fsl,pins = <
- MX8MM_IOMUXC_SAI3_TXFS_SAI3_TX_SYNC 0xd6
- MX8MM_IOMUXC_SAI3_TXC_SAI3_TX_BCLK 0xd6
- MX8MM_IOMUXC_SAI3_MCLK_SAI3_MCLK 0xd6
- MX8MM_IOMUXC_SAI3_TXD_SAI3_TX_DATA0 0xd6
- MX8MM_IOMUXC_SAI3_RXD_SAI3_RX_DATA0 0xd6
- >;
- };
-
- pinctrl_spi2: spi2grp {
- fsl,pins = <
- MX8MM_IOMUXC_ECSPI2_SCLK_ECSPI2_SCLK 0xd6
- MX8MM_IOMUXC_ECSPI2_MOSI_ECSPI2_MOSI 0xd6
- MX8MM_IOMUXC_ECSPI2_MISO_ECSPI2_MISO 0xd6
- MX8MM_IOMUXC_ECSPI2_SS0_GPIO5_IO13 0xd6
- MX8MM_IOMUXC_GPIO1_IO10_GPIO1_IO10 0xd6
- >;
- };
-
- pinctrl_uart1: uart1grp {
- fsl,pins = <
- MX8MM_IOMUXC_UART1_RXD_UART1_DCE_RX 0x140
- MX8MM_IOMUXC_UART1_TXD_UART1_DCE_TX 0x140
- >;
- };
-
- pinctrl_uart3: uart3grp {
- fsl,pins = <
- MX8MM_IOMUXC_UART3_RXD_UART3_DCE_RX 0x140
- MX8MM_IOMUXC_UART3_TXD_UART3_DCE_TX 0x140
- MX8MM_IOMUXC_ECSPI1_MISO_GPIO5_IO8 0x140
- MX8MM_IOMUXC_ECSPI1_SS0_GPIO5_IO9 0x140
- >;
- };
-
- pinctrl_uart4: uart4grp {
- fsl,pins = <
- MX8MM_IOMUXC_UART4_RXD_UART4_DCE_RX 0x140
- MX8MM_IOMUXC_UART4_TXD_UART4_DCE_TX 0x140
- >;
- };
-
- pinctrl_usdhc1: usdhc1grp {
- fsl,pins = <
- MX8MM_IOMUXC_SD1_CLK_USDHC1_CLK 0x190
- MX8MM_IOMUXC_SD1_CMD_USDHC1_CMD 0x1d0
- MX8MM_IOMUXC_SD1_DATA0_USDHC1_DATA0 0x1d0
- MX8MM_IOMUXC_SD1_DATA1_USDHC1_DATA1 0x1d0
- MX8MM_IOMUXC_SD1_DATA2_USDHC1_DATA2 0x1d0
- MX8MM_IOMUXC_SD1_DATA3_USDHC1_DATA3 0x1d0
- >;
- };
-
- pinctrl_usdhc2: usdhc2grp {
- fsl,pins = <
- MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK 0x190
- MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d0
- MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d0
- MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d0
- MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d0
- MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d0
- >;
- };
-
- pinctrl_usdhc2_100mhz: usdhc2-100mhzgrp {
- fsl,pins = <
- MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK 0x194
- MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d4
- MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d4
- MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d4
- MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d4
- MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d4
- >;
- };
-
- pinctrl_usdhc2_200mhz: usdhc2-200mhzgrp {
- fsl,pins = <
- MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK 0x196
- MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d6
- MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d6
- MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d6
- MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d6
- MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d6
- >;
- };
-
- pinctrl_usdhc2_gpio: usdhc2gpiogrp {
- fsl,pins = <
- MX8MM_IOMUXC_SD2_CD_B_GPIO2_IO12 0x1c4
- MX8MM_IOMUXC_SD2_RESET_B_USDHC2_RESET_B 0x1d0
- MX8MM_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0x1d0
- >;
- };
-};
diff --git a/arch/arm/dts/imx8mm-venice-gw7901-u-boot.dtsi b/arch/arm/dts/imx8mm-venice-gw7901-u-boot.dtsi
index e68030e..9fa2194 100644
--- a/arch/arm/dts/imx8mm-venice-gw7901-u-boot.dtsi
+++ b/arch/arm/dts/imx8mm-venice-gw7901-u-boot.dtsi
@@ -43,6 +43,20 @@
};
&gpio4 {
+ dig1ctl {
+ gpio-hog;
+ output-low;
+ gpios = <4 GPIO_ACTIVE_HIGH>;
+ line-name = "dig1_ctl";
+ };
+
+ dig2ctl {
+ gpio-hog;
+ output-low;
+ gpios = <5 GPIO_ACTIVE_HIGH>;
+ line-name = "dig2_ctl";
+ };
+
uart3_rs232 {
gpio-hog;
output-high;
diff --git a/arch/arm/dts/imx8mm-venice-gw7901.dts b/arch/arm/dts/imx8mm-venice-gw7901.dts
deleted file mode 100644
index 826627b..0000000
--- a/arch/arm/dts/imx8mm-venice-gw7901.dts
+++ /dev/null
@@ -1,1137 +0,0 @@
-// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
-/*
- * Copyright 2020 Gateworks Corporation
- */
-
-/dts-v1/;
-
-#include <dt-bindings/gpio/gpio.h>
-#include <dt-bindings/input/linux-event-codes.h>
-#include <dt-bindings/leds/common.h>
-#include <dt-bindings/phy/phy-imx8-pcie.h>
-
-#include "imx8mm.dtsi"
-
-/ {
- model = "Gateworks Venice GW7901 i.MX8MM board";
- compatible = "gw,imx8mm-gw7901", "fsl,imx8mm";
-
- aliases {
- ethernet0 = &fec1;
- ethernet1 = &lan1;
- ethernet2 = &lan2;
- ethernet3 = &lan3;
- ethernet4 = &lan4;
- usb0 = &usbotg1;
- usb1 = &usbotg2;
- };
-
- chosen {
- stdout-path = &uart2;
- };
-
- memory@40000000 {
- device_type = "memory";
- reg = <0x0 0x40000000 0 0x80000000>;
- };
-
- gpio-keys {
- compatible = "gpio-keys";
-
- key-user-pb {
- label = "user_pb";
- gpios = <&gpio 2 GPIO_ACTIVE_LOW>;
- linux,code = <BTN_0>;
- };
-
- key-user-pb1x {
- label = "user_pb1x";
- linux,code = <BTN_1>;
- interrupt-parent = <&gsc>;
- interrupts = <0>;
- };
-
- key-erased {
- label = "key_erased";
- linux,code = <BTN_2>;
- interrupt-parent = <&gsc>;
- interrupts = <1>;
- };
-
- key-eeprom-wp {
- label = "eeprom_wp";
- linux,code = <BTN_3>;
- interrupt-parent = <&gsc>;
- interrupts = <2>;
- };
-
- key-tamper {
- label = "tamper";
- linux,code = <BTN_4>;
- interrupt-parent = <&gsc>;
- interrupts = <5>;
- };
-
- switch-hold {
- label = "switch_hold";
- linux,code = <BTN_5>;
- interrupt-parent = <&gsc>;
- interrupts = <7>;
- };
- };
-
- led-controller {
- compatible = "gpio-leds";
-
- led-0 {
- function = LED_FUNCTION_STATUS;
- color = <LED_COLOR_ID_RED>;
- label = "led01_red";
- gpios = <&leds_gpio 0 GPIO_ACTIVE_HIGH>;
- default-state = "off";
- };
-
- led-1 {
- function = LED_FUNCTION_STATUS;
- color = <LED_COLOR_ID_GREEN>;
- label = "led01_grn";
- gpios = <&leds_gpio 1 GPIO_ACTIVE_HIGH>;
- default-state = "off";
- };
-
- led-2 {
- function = LED_FUNCTION_STATUS;
- color = <LED_COLOR_ID_RED>;
- label = "led02_red";
- gpios = <&leds_gpio 2 GPIO_ACTIVE_HIGH>;
- default-state = "off";
- };
-
- led-3 {
- function = LED_FUNCTION_STATUS;
- color = <LED_COLOR_ID_GREEN>;
- label = "led02_grn";
- gpios = <&leds_gpio 3 GPIO_ACTIVE_HIGH>;
- default-state = "off";
- };
-
- led-4 {
- function = LED_FUNCTION_STATUS;
- color = <LED_COLOR_ID_RED>;
- label = "led03_red";
- gpios = <&leds_gpio 4 GPIO_ACTIVE_HIGH>;
- default-state = "off";
- };
-
- led-5 {
- function = LED_FUNCTION_STATUS;
- color = <LED_COLOR_ID_GREEN>;
- label = "led03_grn";
- gpios = <&leds_gpio 5 GPIO_ACTIVE_HIGH>;
- default-state = "off";
- };
-
- led-6 {
- function = LED_FUNCTION_STATUS;
- color = <LED_COLOR_ID_RED>;
- label = "led04_red";
- gpios = <&leds_gpio 8 GPIO_ACTIVE_HIGH>;
- default-state = "off";
- };
-
- led-7 {
- function = LED_FUNCTION_STATUS;
- color = <LED_COLOR_ID_GREEN>;
- label = "led04_grn";
- gpios = <&leds_gpio 9 GPIO_ACTIVE_HIGH>;
- default-state = "off";
- };
-
- led-8 {
- function = LED_FUNCTION_STATUS;
- color = <LED_COLOR_ID_RED>;
- label = "led05_red";
- gpios = <&leds_gpio 10 GPIO_ACTIVE_HIGH>;
- default-state = "off";
- };
-
- led-9 {
- function = LED_FUNCTION_STATUS;
- color = <LED_COLOR_ID_GREEN>;
- label = "led05_grn";
- gpios = <&leds_gpio 11 GPIO_ACTIVE_HIGH>;
- default-state = "off";
- };
-
- led-a {
- function = LED_FUNCTION_STATUS;
- color = <LED_COLOR_ID_RED>;
- label = "led06_red";
- gpios = <&leds_gpio 12 GPIO_ACTIVE_HIGH>;
- default-state = "off";
- };
-
- led-b {
- function = LED_FUNCTION_STATUS;
- color = <LED_COLOR_ID_GREEN>;
- label = "led06_grn";
- gpios = <&leds_gpio 13 GPIO_ACTIVE_HIGH>;
- default-state = "off";
- };
- };
-
- pcie0_refclk: pcie0-refclk {
- compatible = "fixed-clock";
- #clock-cells = <0>;
- clock-frequency = <100000000>;
- };
-
- reg_3p3v: regulator-3p3v {
- compatible = "regulator-fixed";
- regulator-name = "3P3V";
- regulator-min-microvolt = <3300000>;
- regulator-max-microvolt = <3300000>;
- };
-
- regulator-ioexp {
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_reg_ioexp>;
- compatible = "regulator-fixed";
- regulator-name = "ioexp";
- gpio = <&gpio4 21 GPIO_ACTIVE_HIGH>;
- enable-active-high;
- startup-delay-us = <100>;
- regulator-min-microvolt = <3300000>;
- regulator-max-microvolt = <3300000>;
- regulator-always-on;
- };
-
- regulator-isouart {
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_reg_isouart>;
- compatible = "regulator-fixed";
- regulator-name = "iso_uart";
- gpio = <&gpio1 13 GPIO_ACTIVE_LOW>;
- startup-delay-us = <100>;
- regulator-min-microvolt = <3300000>;
- regulator-max-microvolt = <3300000>;
- regulator-always-on;
- };
-
- reg_usb2_vbus: regulator-usb2 {
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_reg_usb2>;
- compatible = "regulator-fixed";
- regulator-name = "usb_usb2_vbus";
- gpio = <&gpio4 2 GPIO_ACTIVE_HIGH>;
- enable-active-high;
- regulator-min-microvolt = <5000000>;
- regulator-max-microvolt = <5000000>;
- };
-
- reg_wifi: regulator-wifi {
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_reg_wl>;
- compatible = "regulator-fixed";
- regulator-name = "wifi";
- gpio = <&gpio3 25 GPIO_ACTIVE_HIGH>;
- enable-active-high;
- startup-delay-us = <100>;
- regulator-min-microvolt = <3300000>;
- regulator-max-microvolt = <3300000>;
- };
-};
-
-&ddrc {
- operating-points-v2 = <&ddrc_opp_table>;
-
- ddrc_opp_table: opp-table {
- compatible = "operating-points-v2";
-
- opp-25M {
- opp-hz = /bits/ 64 <25000000>;
- };
-
- opp-100M {
- opp-hz = /bits/ 64 <100000000>;
- };
-
- opp-750M {
- opp-hz = /bits/ 64 <750000000>;
- };
- };
-};
-
-&disp_blk_ctrl {
- status = "disabled";
-};
-
-&ecspi1 {
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_spi1>;
- cs-gpios = <&gpio5 9 GPIO_ACTIVE_LOW>;
- status = "okay";
-
- flash@0 {
- compatible = "jedec,spi-nor";
- reg = <0>;
- spi-max-frequency = <40000000>;
- status = "okay";
- };
-};
-
-&fec1 {
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_fec1>;
- phy-mode = "rgmii-id";
- local-mac-address = [00 00 00 00 00 00];
- status = "okay";
-
- fixed-link {
- speed = <1000>;
- full-duplex;
- };
-};
-
-&gpio1 {
- gpio-line-names = "uart1_rs422#", "", "", "uart1_rs485#",
- "", "uart1_rs232#", "dig1_in", "dig1_out",
- "", "", "", "", "", "", "", "",
- "", "", "", "", "", "", "", "",
- "", "", "", "", "", "", "", "";
-};
-
-&gpio4 {
- gpio-line-names = "", "", "", "",
- "", "", "uart3_rs232#", "uart3_rs422#",
- "uart3_rs485#", "", "", "", "", "", "", "",
- "", "", "", "", "", "", "", "",
- "", "", "", "uart4_rs485#", "", "sim1det#", "sim2det#", "";
-};
-
-&gpio5 {
- gpio-line-names = "", "", "", "dig2_out", "dig2_in", "sim2sel", "", "",
- "", "", "uart4_rs232#", "", "", "uart4_rs422#", "", "",
- "", "", "", "", "", "", "", "",
- "", "", "", "", "", "", "", "";
-};
-
-&gpu_2d {
- status = "disabled";
-};
-
-&gpu_3d {
- status = "disabled";
-};
-
-&i2c1 {
- clock-frequency = <100000>;
- pinctrl-names = "default", "gpio";
- pinctrl-0 = <&pinctrl_i2c1>;
- pinctrl-1 = <&pinctrl_i2c1_gpio>;
- scl-gpios = <&gpio5 14 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
- sda-gpios = <&gpio5 15 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
- status = "okay";
-
- gsc: gsc@20 {
- compatible = "gw,gsc";
- reg = <0x20>;
- pinctrl-0 = <&pinctrl_gsc>;
- interrupt-parent = <&gpio4>;
- interrupts = <16 IRQ_TYPE_EDGE_FALLING>;
- interrupt-controller;
- #interrupt-cells = <1>;
-
- adc {
- compatible = "gw,gsc-adc";
- #address-cells = <1>;
- #size-cells = <0>;
-
- channel@6 {
- gw,mode = <0>;
- reg = <0x06>;
- label = "temp";
- };
-
- channel@8 {
- gw,mode = <1>;
- reg = <0x08>;
- label = "vdd_bat";
- };
-
- channel@82 {
- gw,mode = <2>;
- reg = <0x82>;
- label = "vin_aux1";
- gw,voltage-divider-ohms = <22100 1000>;
- };
-
- channel@84 {
- gw,mode = <2>;
- reg = <0x84>;
- label = "vin_aux2";
- gw,voltage-divider-ohms = <22100 1000>;
- };
-
- channel@86 {
- gw,mode = <2>;
- reg = <0x86>;
- label = "vdd_vin";
- gw,voltage-divider-ohms = <22100 1000>;
- };
-
- channel@88 {
- gw,mode = <2>;
- reg = <0x88>;
- label = "vdd_3p3";
- gw,voltage-divider-ohms = <10000 10000>;
- };
-
- channel@8c {
- gw,mode = <2>;
- reg = <0x8c>;
- label = "vdd_2p5";
- gw,voltage-divider-ohms = <10000 10000>;
- };
-
- channel@8e {
- gw,mode = <2>;
- reg = <0x8e>;
- label = "vdd_0p95";
- };
-
- channel@90 {
- gw,mode = <2>;
- reg = <0x90>;
- label = "vdd_soc";
- };
-
- channel@92 {
- gw,mode = <2>;
- reg = <0x92>;
- label = "vdd_arm";
- };
-
- channel@98 {
- gw,mode = <2>;
- reg = <0x98>;
- label = "vdd_1p8";
- };
-
- channel@9a {
- gw,mode = <2>;
- reg = <0x9a>;
- label = "vdd_1p2";
- };
-
- channel@9c {
- gw,mode = <2>;
- reg = <0x9c>;
- label = "vdd_dram";
- };
-
- channel@a2 {
- gw,mode = <2>;
- reg = <0xa2>;
- label = "vdd_gsc";
- gw,voltage-divider-ohms = <10000 10000>;
- };
- };
- };
-
- gpio: gpio@23 {
- compatible = "nxp,pca9555";
- reg = <0x23>;
- gpio-controller;
- #gpio-cells = <2>;
- interrupt-parent = <&gsc>;
- interrupts = <4>;
- };
-
- eeprom@50 {
- compatible = "atmel,24c02";
- reg = <0x50>;
- pagesize = <16>;
- };
-
- eeprom@51 {
- compatible = "atmel,24c02";
- reg = <0x51>;
- pagesize = <16>;
- };
-
- eeprom@52 {
- compatible = "atmel,24c02";
- reg = <0x52>;
- pagesize = <16>;
- };
-
- eeprom@53 {
- compatible = "atmel,24c02";
- reg = <0x53>;
- pagesize = <16>;
- };
-
- rtc@68 {
- compatible = "dallas,ds1672";
- reg = <0x68>;
- };
-};
-
-&i2c2 {
- clock-frequency = <400000>;
- pinctrl-names = "default", "gpio";
- pinctrl-0 = <&pinctrl_i2c2>;
- pinctrl-1 = <&pinctrl_i2c2_gpio>;
- scl-gpios = <&gpio5 16 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
- sda-gpios = <&gpio5 17 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
- status = "okay";
-
- pmic@4b {
- compatible = "rohm,bd71847";
- reg = <0x4b>;
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_pmic>;
- interrupt-parent = <&gpio3>;
- interrupts = <20 IRQ_TYPE_LEVEL_LOW>;
- rohm,reset-snvs-powered;
- #clock-cells = <0>;
- clocks = <&osc_32k 0>;
- clock-output-names = "clk-32k-out";
-
- regulators {
- /* vdd_soc: 0.805-0.900V (typ=0.8V) */
- BUCK1 {
- regulator-name = "buck1";
- regulator-min-microvolt = <700000>;
- regulator-max-microvolt = <1300000>;
- regulator-boot-on;
- regulator-always-on;
- regulator-ramp-delay = <1250>;
- };
-
- /* vdd_arm: 0.805-1.0V (typ=0.9V) */
- BUCK2 {
- regulator-name = "buck2";
- regulator-min-microvolt = <700000>;
- regulator-max-microvolt = <1300000>;
- regulator-boot-on;
- regulator-always-on;
- regulator-ramp-delay = <1250>;
- rohm,dvs-run-voltage = <1000000>;
- rohm,dvs-idle-voltage = <900000>;
- };
-
- /* vdd_0p9: 0.805-1.0V (typ=0.9V) */
- BUCK3 {
- regulator-name = "buck3";
- regulator-min-microvolt = <700000>;
- regulator-max-microvolt = <1350000>;
- regulator-boot-on;
- regulator-always-on;
- };
-
- /* vdd_3p3 */
- BUCK4 {
- regulator-name = "buck4";
- regulator-min-microvolt = <3000000>;
- regulator-max-microvolt = <3300000>;
- regulator-boot-on;
- regulator-always-on;
- };
-
- /* vdd_1p8 */
- BUCK5 {
- regulator-name = "buck5";
- regulator-min-microvolt = <1605000>;
- regulator-max-microvolt = <1995000>;
- regulator-boot-on;
- regulator-always-on;
- };
-
- /* vdd_dram */
- BUCK6 {
- regulator-name = "buck6";
- regulator-min-microvolt = <800000>;
- regulator-max-microvolt = <1400000>;
- regulator-boot-on;
- regulator-always-on;
- };
-
- /* nvcc_snvs_1p8 */
- LDO1 {
- regulator-name = "ldo1";
- regulator-min-microvolt = <1600000>;
- regulator-max-microvolt = <1900000>;
- regulator-boot-on;
- regulator-always-on;
- };
-
- /* vdd_snvs_0p8 */
- LDO2 {
- regulator-name = "ldo2";
- regulator-min-microvolt = <800000>;
- regulator-max-microvolt = <900000>;
- regulator-boot-on;
- regulator-always-on;
- };
-
- /* vdda_1p8 */
- LDO3 {
- regulator-name = "ldo3";
- regulator-min-microvolt = <1800000>;
- regulator-max-microvolt = <3300000>;
- regulator-boot-on;
- regulator-always-on;
- };
-
- LDO4 {
- regulator-name = "ldo4";
- regulator-min-microvolt = <900000>;
- regulator-max-microvolt = <1800000>;
- regulator-boot-on;
- regulator-always-on;
- };
-
- LDO6 {
- regulator-name = "ldo6";
- regulator-min-microvolt = <900000>;
- regulator-max-microvolt = <1800000>;
- regulator-boot-on;
- regulator-always-on;
- };
- };
- };
-};
-
-&i2c3 {
- clock-frequency = <400000>;
- pinctrl-names = "default", "gpio";
- pinctrl-0 = <&pinctrl_i2c3>;
- pinctrl-1 = <&pinctrl_i2c3_gpio>;
- scl-gpios = <&gpio5 18 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
- sda-gpios = <&gpio5 19 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
- status = "okay";
-
- leds_gpio: gpio@20 {
- compatible = "nxp,pca9555";
- reg = <0x20>;
- gpio-controller;
- #gpio-cells = <2>;
- };
-
- switch: switch@5f {
- compatible = "microchip,ksz9897";
- reg = <0x5f>;
- pinctrl-0 = <&pinctrl_ksz>;
- interrupt-parent = <&gpio4>;
- interrupts = <18 IRQ_TYPE_EDGE_FALLING>;
- phy-mode = "rgmii-id";
-
- ports {
- #address-cells = <1>;
- #size-cells = <0>;
-
- lan1: port@0 {
- reg = <0>;
- label = "lan1";
- phy-mode = "internal";
- local-mac-address = [00 00 00 00 00 00];
- };
-
- lan2: port@1 {
- reg = <1>;
- label = "lan2";
- phy-mode = "internal";
- local-mac-address = [00 00 00 00 00 00];
- };
-
- lan3: port@2 {
- reg = <2>;
- label = "lan3";
- phy-mode = "internal";
- local-mac-address = [00 00 00 00 00 00];
- };
-
- lan4: port@3 {
- reg = <3>;
- label = "lan4";
- phy-mode = "internal";
- local-mac-address = [00 00 00 00 00 00];
- };
-
- port@5 {
- reg = <5>;
- label = "cpu";
- ethernet = <&fec1>;
- phy-mode = "rgmii-id";
-
- fixed-link {
- speed = <1000>;
- full-duplex;
- };
- };
- };
- };
-
- crypto@60 {
- compatible = "atmel,atecc508a";
- reg = <0x60>;
- };
-};
-
-&i2c4 {
- clock-frequency = <400000>;
- pinctrl-names = "default", "gpio";
- pinctrl-0 = <&pinctrl_i2c4>;
- pinctrl-1 = <&pinctrl_i2c4_gpio>;
- scl-gpios = <&gpio5 20 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
- sda-gpios = <&gpio5 21 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
- status = "okay";
-};
-
-&pcie_phy {
- fsl,refclk-pad-mode = <IMX8_PCIE_REFCLK_PAD_INPUT>;
- fsl,clkreq-unsupported;
- clocks = <&pcie0_refclk>;
- clock-names = "ref";
- status = "okay";
-};
-
-&pcie0 {
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_pcie0>;
- reset-gpio = <&gpio5 2 GPIO_ACTIVE_LOW>;
- clocks = <&clk IMX8MM_CLK_PCIE1_ROOT>, <&clk IMX8MM_CLK_PCIE1_AUX>,
- <&pcie0_refclk>;
- clock-names = "pcie", "pcie_aux", "pcie_bus";
- assigned-clocks = <&clk IMX8MM_CLK_PCIE1_AUX>,
- <&clk IMX8MM_CLK_PCIE1_CTRL>;
- assigned-clock-rates = <10000000>, <250000000>;
- assigned-clock-parents = <&clk IMX8MM_SYS_PLL2_50M>,
- <&clk IMX8MM_SYS_PLL2_250M>;
- status = "okay";
-};
-
-&pgc_gpu {
- status = "disabled";
-};
-
-&pgc_gpumix {
- status = "disabled";
-};
-
-&pgc_mipi {
- status = "disabled";
-};
-
-&uart1 {
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_uart1>, <&pinctrl_uart1_gpio>;
- rts-gpios = <&gpio1 10 GPIO_ACTIVE_LOW>;
- cts-gpios = <&gpio1 12 GPIO_ACTIVE_LOW>;
- dtr-gpios = <&gpio1 14 GPIO_ACTIVE_LOW>;
- dsr-gpios = <&gpio1 1 GPIO_ACTIVE_LOW>;
- dcd-gpios = <&gpio1 11 GPIO_ACTIVE_LOW>;
- uart-has-rtscts;
- status = "okay";
-};
-
-/* console */
-&uart2 {
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_uart2>;
- status = "okay";
-};
-
-&uart3 {
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_uart3>, <&pinctrl_uart3_gpio>;
- cts-gpios = <&gpio4 10 GPIO_ACTIVE_LOW>;
- rts-gpios = <&gpio4 9 GPIO_ACTIVE_LOW>;
- uart-has-rtscts;
- status = "okay";
-};
-
-&uart4 {
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_uart4>, <&pinctrl_uart4_gpio>;
- cts-gpios = <&gpio5 11 GPIO_ACTIVE_LOW>;
- rts-gpios = <&gpio5 12 GPIO_ACTIVE_LOW>;
- uart-has-rtscts;
- status = "okay";
-};
-
-&usbotg1 {
- dr_mode = "host";
- disable-over-current;
- status = "okay";
-};
-
-&usbotg2 {
- dr_mode = "host";
- vbus-supply = <®_usb2_vbus>;
- status = "okay";
-};
-
-/* SDIO WiFi */
-&usdhc1 {
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_usdhc1>;
- bus-width = <4>;
- non-removable;
- vmmc-supply = <®_wifi>;
- status = "okay";
-};
-
-/* microSD */
-&usdhc2 {
- pinctrl-names = "default", "state_100mhz", "state_200mhz";
- pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>;
- pinctrl-1 = <&pinctrl_usdhc2_100mhz>, <&pinctrl_usdhc2_gpio>;
- pinctrl-2 = <&pinctrl_usdhc2_200mhz>, <&pinctrl_usdhc2_gpio>;
- cd-gpios = <&gpio2 12 GPIO_ACTIVE_LOW>;
- bus-width = <4>;
- vmmc-supply = <®_3p3v>;
- status = "okay";
-};
-
-/* eMMC */
-&usdhc3 {
- pinctrl-names = "default", "state_100mhz", "state_200mhz";
- pinctrl-0 = <&pinctrl_usdhc3>;
- pinctrl-1 = <&pinctrl_usdhc3_100mhz>;
- pinctrl-2 = <&pinctrl_usdhc3_200mhz>;
- bus-width = <8>;
- non-removable;
- status = "okay";
-};
-
-&wdog1 {
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_wdog>;
- fsl,ext-reset-output;
- status = "okay";
-};
-
-&iomuxc {
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_hog>;
-
- pinctrl_hog: hoggrp {
- fsl,pins = <
- MX8MM_IOMUXC_SPDIF_TX_GPIO5_IO3 0x40000041 /* DIG2_OUT */
- MX8MM_IOMUXC_SPDIF_RX_GPIO5_IO4 0x40000041 /* DIG2_IN */
- MX8MM_IOMUXC_GPIO1_IO06_GPIO1_IO6 0x40000041 /* DIG1_IN */
- MX8MM_IOMUXC_GPIO1_IO07_GPIO1_IO7 0x40000041 /* DIG1_OUT */
- MX8MM_IOMUXC_SAI3_RXD_GPIO4_IO30 0x40000041 /* SIM2DET# */
- MX8MM_IOMUXC_SAI3_RXC_GPIO4_IO29 0x40000041 /* SIM1DET# */
- MX8MM_IOMUXC_SPDIF_EXT_CLK_GPIO5_IO5 0x40000041 /* SIM2SEL */
- >;
- };
-
- pinctrl_fec1: fec1grp {
- fsl,pins = <
- MX8MM_IOMUXC_ENET_MDC_ENET1_MDC 0x3
- MX8MM_IOMUXC_ENET_MDIO_ENET1_MDIO 0x3
- MX8MM_IOMUXC_ENET_TD3_ENET1_RGMII_TD3 0x1f
- MX8MM_IOMUXC_ENET_TD2_ENET1_RGMII_TD2 0x1f
- MX8MM_IOMUXC_ENET_TD1_ENET1_RGMII_TD1 0x1f
- MX8MM_IOMUXC_ENET_TD0_ENET1_RGMII_TD0 0x1f
- MX8MM_IOMUXC_ENET_RD3_ENET1_RGMII_RD3 0x91
- MX8MM_IOMUXC_ENET_RD2_ENET1_RGMII_RD2 0x91
- MX8MM_IOMUXC_ENET_RD1_ENET1_RGMII_RD1 0x91
- MX8MM_IOMUXC_ENET_RD0_ENET1_RGMII_RD0 0x91
- MX8MM_IOMUXC_ENET_TXC_ENET1_RGMII_TXC 0x1f
- MX8MM_IOMUXC_ENET_RXC_ENET1_RGMII_RXC 0x91
- MX8MM_IOMUXC_ENET_RX_CTL_ENET1_RGMII_RX_CTL 0x91
- MX8MM_IOMUXC_ENET_TX_CTL_ENET1_RGMII_TX_CTL 0x1f
- MX8MM_IOMUXC_SAI1_TXD6_GPIO4_IO18 0x19 /* IRQ# */
- MX8MM_IOMUXC_SAI1_TXD7_GPIO4_IO19 0x19 /* RST# */
- >;
- };
-
- pinctrl_gsc: gscgrp {
- fsl,pins = <
- MX8MM_IOMUXC_SAI1_TXD4_GPIO4_IO16 0x159
- >;
- };
-
- pinctrl_i2c1: i2c1grp {
- fsl,pins = <
- MX8MM_IOMUXC_I2C1_SCL_I2C1_SCL 0x400001c3
- MX8MM_IOMUXC_I2C1_SDA_I2C1_SDA 0x400001c3
- >;
- };
-
- pinctrl_i2c1_gpio: i2c1gpiogrp {
- fsl,pins = <
- MX8MM_IOMUXC_I2C1_SCL_GPIO5_IO14 0x400001c3
- MX8MM_IOMUXC_I2C1_SDA_GPIO5_IO15 0x400001c3
- >;
- };
-
- pinctrl_i2c2: i2c2grp {
- fsl,pins = <
- MX8MM_IOMUXC_I2C2_SCL_I2C2_SCL 0x400001c3
- MX8MM_IOMUXC_I2C2_SDA_I2C2_SDA 0x400001c3
- >;
- };
-
- pinctrl_i2c2_gpio: i2c2gpiogrp {
- fsl,pins = <
- MX8MM_IOMUXC_I2C2_SCL_GPIO5_IO16 0x400001c3
- MX8MM_IOMUXC_I2C2_SDA_GPIO5_IO17 0x400001c3
- >;
- };
-
- pinctrl_i2c3: i2c3grp {
- fsl,pins = <
- MX8MM_IOMUXC_I2C3_SCL_I2C3_SCL 0x400001c3
- MX8MM_IOMUXC_I2C3_SDA_I2C3_SDA 0x400001c3
- >;
- };
-
- pinctrl_i2c3_gpio: i2c3gpiogrp {
- fsl,pins = <
- MX8MM_IOMUXC_I2C3_SCL_GPIO5_IO18 0x400001c3
- MX8MM_IOMUXC_I2C3_SDA_GPIO5_IO19 0x400001c3
- >;
- };
-
- pinctrl_i2c4: i2c4grp {
- fsl,pins = <
- MX8MM_IOMUXC_I2C4_SCL_I2C4_SCL 0x400001c3
- MX8MM_IOMUXC_I2C4_SDA_I2C4_SDA 0x400001c3
- >;
- };
-
- pinctrl_i2c4_gpio: i2c4gpiogrp {
- fsl,pins = <
- MX8MM_IOMUXC_I2C4_SCL_GPIO5_IO20 0x400001c3
- MX8MM_IOMUXC_I2C4_SDA_GPIO5_IO21 0x400001c3
- >;
- };
-
- pinctrl_ksz: kszgrp {
- fsl,pins = <
- MX8MM_IOMUXC_SAI1_TXD6_GPIO4_IO18 0x41
- MX8MM_IOMUXC_SAI1_TXD7_GPIO4_IO19 0x41 /* RST# */
- >;
- };
-
- pinctrl_pcie0: pciegrp {
- fsl,pins = <
- MX8MM_IOMUXC_SAI3_TXFS_GPIO4_IO31 0x40000041 /* WDIS# */
- MX8MM_IOMUXC_SAI3_MCLK_GPIO5_IO2 0x41
- >;
- };
-
- pinctrl_pmic: pmicgrp {
- fsl,pins = <
- MX8MM_IOMUXC_SAI5_RXC_GPIO3_IO20 0x41
- >;
- };
-
- pinctrl_reg_isouart: regisouartgrp {
- fsl,pins = <
- MX8MM_IOMUXC_GPIO1_IO13_GPIO1_IO13 0x40000041
- >;
- };
-
- pinctrl_reg_ioexp: regioexpgrp {
- fsl,pins = <
- MX8MM_IOMUXC_SAI2_RXFS_GPIO4_IO21 0x40000041
- >;
- };
-
- pinctrl_reg_wl: regwlgrp {
- fsl,pins = <
- MX8MM_IOMUXC_SAI5_MCLK_GPIO3_IO25 0x40000041
- >;
- };
-
- pinctrl_reg_usb2: regusb1grp {
- fsl,pins = <
- MX8MM_IOMUXC_SAI1_RXD0_GPIO4_IO2 0x41
- MX8MM_IOMUXC_SAI1_TXD5_GPIO4_IO17 0x140
- MX8MM_IOMUXC_GPIO1_IO15_USB2_OTG_OC 0x140
- >;
- };
-
- pinctrl_spi1: spi1grp {
- fsl,pins = <
- MX8MM_IOMUXC_ECSPI1_SCLK_ECSPI1_SCLK 0x82
- MX8MM_IOMUXC_ECSPI1_MOSI_ECSPI1_MOSI 0x82
- MX8MM_IOMUXC_ECSPI1_MISO_ECSPI1_MISO 0x82
- MX8MM_IOMUXC_ECSPI1_SS0_GPIO5_IO9 0x140
- >;
- };
-
- pinctrl_uart1: uart1grp {
- fsl,pins = <
- MX8MM_IOMUXC_UART1_RXD_UART1_DCE_RX 0x140
- MX8MM_IOMUXC_UART1_TXD_UART1_DCE_TX 0x140
- MX8MM_IOMUXC_GPIO1_IO01_GPIO1_IO1 0x140
- MX8MM_IOMUXC_GPIO1_IO10_GPIO1_IO10 0x140
- MX8MM_IOMUXC_GPIO1_IO11_GPIO1_IO11 0x140
- MX8MM_IOMUXC_GPIO1_IO12_GPIO1_IO12 0x140
- MX8MM_IOMUXC_GPIO1_IO14_GPIO1_IO14 0x140
- >;
- };
-
- pinctrl_uart1_gpio: uart1gpiogrp {
- fsl,pins = <
- MX8MM_IOMUXC_GPIO1_IO00_GPIO1_IO0 0x40000041 /* RS422# */
- MX8MM_IOMUXC_GPIO1_IO03_GPIO1_IO3 0x40000041 /* RS485# */
- MX8MM_IOMUXC_GPIO1_IO05_GPIO1_IO5 0x40000041 /* RS232# */
- >;
- };
-
- pinctrl_uart2: uart2grp {
- fsl,pins = <
- MX8MM_IOMUXC_UART2_RXD_UART2_DCE_RX 0x140
- MX8MM_IOMUXC_UART2_TXD_UART2_DCE_TX 0x140
- >;
- };
-
- pinctrl_uart3: uart3grp {
- fsl,pins = <
- MX8MM_IOMUXC_UART3_RXD_UART3_DCE_RX 0x140
- MX8MM_IOMUXC_UART3_TXD_UART3_DCE_TX 0x140
- MX8MM_IOMUXC_SAI1_RXD7_GPIO4_IO9 0x140
- MX8MM_IOMUXC_SAI1_TXFS_GPIO4_IO10 0x140
- >;
- };
-
- pinctrl_uart3_gpio: uart3gpiogrp {
- fsl,pins = <
- MX8MM_IOMUXC_SAI1_RXD4_GPIO4_IO6 0x40000110 /* RS232# */
- MX8MM_IOMUXC_SAI1_RXD5_GPIO4_IO7 0x40000110 /* RS422# */
- MX8MM_IOMUXC_SAI1_RXD6_GPIO4_IO8 0x40000110 /* RS485# */
- >;
- };
-
- pinctrl_uart4: uart4grp {
- fsl,pins = <
- MX8MM_IOMUXC_UART4_RXD_UART4_DCE_RX 0x140
- MX8MM_IOMUXC_UART4_TXD_UART4_DCE_TX 0x140
- MX8MM_IOMUXC_ECSPI2_MOSI_GPIO5_IO11 0x140
- MX8MM_IOMUXC_ECSPI2_MISO_GPIO5_IO12 0x140
- >;
- };
-
- pinctrl_uart4_gpio: uart4gpiogrp {
- fsl,pins = <
-
- MX8MM_IOMUXC_ECSPI2_SCLK_GPIO5_IO10 0x40000041 /* RS232# */
- MX8MM_IOMUXC_ECSPI2_SS0_GPIO5_IO13 0x40000041 /* RS422# */
- MX8MM_IOMUXC_SAI2_MCLK_GPIO4_IO27 0x40000041 /* RS485# */
- >;
- };
-
- pinctrl_usdhc1: usdhc1grp {
- fsl,pins = <
- MX8MM_IOMUXC_SD1_CLK_USDHC1_CLK 0x190
- MX8MM_IOMUXC_SD1_CMD_USDHC1_CMD 0x1d0
- MX8MM_IOMUXC_SD1_DATA0_USDHC1_DATA0 0x1d0
- MX8MM_IOMUXC_SD1_DATA1_USDHC1_DATA1 0x1d0
- MX8MM_IOMUXC_SD1_DATA2_USDHC1_DATA2 0x1d0
- MX8MM_IOMUXC_SD1_DATA3_USDHC1_DATA3 0x1d0
- >;
- };
-
- pinctrl_usdhc2: usdhc2grp {
- fsl,pins = <
- MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK 0x190
- MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d0
- MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d0
- MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d0
- MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d0
- MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d0
- >;
- };
-
- pinctrl_usdhc2_100mhz: usdhc2-100mhzgrp {
- fsl,pins = <
- MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK 0x194
- MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d4
- MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d4
- MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d4
- MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d4
- MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d4
- >;
- };
-
- pinctrl_usdhc2_200mhz: usdhc2-200mhzgrp {
- fsl,pins = <
- MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK 0x196
- MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d6
- MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d6
- MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d6
- MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d6
- MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d6
- >;
- };
-
- pinctrl_usdhc2_gpio: usdhc2-gpiogrp {
- fsl,pins = <
- MX8MM_IOMUXC_SD2_CD_B_GPIO2_IO12 0x1c4
- MX8MM_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0x1d0
- >;
- };
-
- pinctrl_usdhc3: usdhc3grp {
- fsl,pins = <
- MX8MM_IOMUXC_NAND_WE_B_USDHC3_CLK 0x190
- MX8MM_IOMUXC_NAND_WP_B_USDHC3_CMD 0x1d0
- MX8MM_IOMUXC_NAND_DATA04_USDHC3_DATA0 0x1d0
- MX8MM_IOMUXC_NAND_DATA05_USDHC3_DATA1 0x1d0
- MX8MM_IOMUXC_NAND_DATA06_USDHC3_DATA2 0x1d0
- MX8MM_IOMUXC_NAND_DATA07_USDHC3_DATA3 0x1d0
- MX8MM_IOMUXC_NAND_RE_B_USDHC3_DATA4 0x1d0
- MX8MM_IOMUXC_NAND_CE2_B_USDHC3_DATA5 0x1d0
- MX8MM_IOMUXC_NAND_CE3_B_USDHC3_DATA6 0x1d0
- MX8MM_IOMUXC_NAND_CLE_USDHC3_DATA7 0x1d0
- MX8MM_IOMUXC_NAND_CE1_B_USDHC3_STROBE 0x190
- >;
- };
-
- pinctrl_usdhc3_100mhz: usdhc3-100mhzgrp {
- fsl,pins = <
- MX8MM_IOMUXC_NAND_WE_B_USDHC3_CLK 0x194
- MX8MM_IOMUXC_NAND_WP_B_USDHC3_CMD 0x1d4
- MX8MM_IOMUXC_NAND_DATA04_USDHC3_DATA0 0x1d4
- MX8MM_IOMUXC_NAND_DATA05_USDHC3_DATA1 0x1d4
- MX8MM_IOMUXC_NAND_DATA06_USDHC3_DATA2 0x1d4
- MX8MM_IOMUXC_NAND_DATA07_USDHC3_DATA3 0x1d4
- MX8MM_IOMUXC_NAND_RE_B_USDHC3_DATA4 0x1d4
- MX8MM_IOMUXC_NAND_CE2_B_USDHC3_DATA5 0x1d4
- MX8MM_IOMUXC_NAND_CE3_B_USDHC3_DATA6 0x1d4
- MX8MM_IOMUXC_NAND_CLE_USDHC3_DATA7 0x1d4
- MX8MM_IOMUXC_NAND_CE1_B_USDHC3_STROBE 0x194
- >;
- };
-
- pinctrl_usdhc3_200mhz: usdhc3-200mhzgrp {
- fsl,pins = <
- MX8MM_IOMUXC_NAND_WE_B_USDHC3_CLK 0x196
- MX8MM_IOMUXC_NAND_WP_B_USDHC3_CMD 0x1d6
- MX8MM_IOMUXC_NAND_DATA04_USDHC3_DATA0 0x1d6
- MX8MM_IOMUXC_NAND_DATA05_USDHC3_DATA1 0x1d6
- MX8MM_IOMUXC_NAND_DATA06_USDHC3_DATA2 0x1d6
- MX8MM_IOMUXC_NAND_DATA07_USDHC3_DATA3 0x1d6
- MX8MM_IOMUXC_NAND_RE_B_USDHC3_DATA4 0x1d6
- MX8MM_IOMUXC_NAND_CE2_B_USDHC3_DATA5 0x1d6
- MX8MM_IOMUXC_NAND_CE3_B_USDHC3_DATA6 0x1d6
- MX8MM_IOMUXC_NAND_CLE_USDHC3_DATA7 0x1d6
- MX8MM_IOMUXC_NAND_CE1_B_USDHC3_STROBE 0x196
- >;
- };
-
- pinctrl_wdog: wdoggrp {
- fsl,pins = <
- MX8MM_IOMUXC_GPIO1_IO02_WDOG1_WDOG_B 0xc6
- >;
- };
-};
diff --git a/arch/arm/dts/imx8mm-venice-gw7902.dts b/arch/arm/dts/imx8mm-venice-gw7902.dts
deleted file mode 100644
index 11481e0..0000000
--- a/arch/arm/dts/imx8mm-venice-gw7902.dts
+++ /dev/null
@@ -1,1052 +0,0 @@
-// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
-/*
- * Copyright 2021 Gateworks Corporation
- */
-
-/dts-v1/;
-
-#include <dt-bindings/gpio/gpio.h>
-#include <dt-bindings/input/linux-event-codes.h>
-#include <dt-bindings/leds/common.h>
-#include <dt-bindings/net/ti-dp83867.h>
-#include <dt-bindings/phy/phy-imx8-pcie.h>
-
-#include "imx8mm.dtsi"
-
-/ {
- model = "Gateworks Venice GW7902 i.MX8MM board";
- compatible = "gw,imx8mm-gw7902", "fsl,imx8mm";
-
- aliases {
- ethernet1 = ð1;
- usb0 = &usbotg1;
- usb1 = &usbotg2;
- };
-
- chosen {
- stdout-path = &uart2;
- };
-
- memory@40000000 {
- device_type = "memory";
- reg = <0x0 0x40000000 0 0x80000000>;
- };
-
- can20m: can20m {
- compatible = "fixed-clock";
- #clock-cells = <0>;
- clock-frequency = <20000000>;
- clock-output-names = "can20m";
- };
-
- gpio-keys {
- compatible = "gpio-keys";
-
- key-user-pb {
- label = "user_pb";
- gpios = <&gpio 2 GPIO_ACTIVE_LOW>;
- linux,code = <BTN_0>;
- };
-
- key-user-pb1x {
- label = "user_pb1x";
- linux,code = <BTN_1>;
- interrupt-parent = <&gsc>;
- interrupts = <0>;
- };
-
- key-erased {
- label = "key_erased";
- linux,code = <BTN_2>;
- interrupt-parent = <&gsc>;
- interrupts = <1>;
- };
-
- key-eeprom-wp {
- label = "eeprom_wp";
- linux,code = <BTN_3>;
- interrupt-parent = <&gsc>;
- interrupts = <2>;
- };
-
- key-tamper {
- label = "tamper";
- linux,code = <BTN_4>;
- interrupt-parent = <&gsc>;
- interrupts = <5>;
- };
-
- switch-hold {
- label = "switch_hold";
- linux,code = <BTN_5>;
- interrupt-parent = <&gsc>;
- interrupts = <7>;
- };
- };
-
- led-controller {
- compatible = "gpio-leds";
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_gpio_leds>;
-
- led-0 {
- function = LED_FUNCTION_STATUS;
- color = <LED_COLOR_ID_GREEN>;
- label = "panel1";
- gpios = <&gpio3 21 GPIO_ACTIVE_LOW>;
- default-state = "off";
- };
-
- led-1 {
- function = LED_FUNCTION_STATUS;
- color = <LED_COLOR_ID_GREEN>;
- label = "panel2";
- gpios = <&gpio3 23 GPIO_ACTIVE_LOW>;
- default-state = "off";
- };
-
- led-2 {
- function = LED_FUNCTION_STATUS;
- color = <LED_COLOR_ID_GREEN>;
- label = "panel3";
- gpios = <&gpio3 22 GPIO_ACTIVE_LOW>;
- default-state = "off";
- };
-
- led-3 {
- function = LED_FUNCTION_STATUS;
- color = <LED_COLOR_ID_GREEN>;
- label = "panel4";
- gpios = <&gpio3 20 GPIO_ACTIVE_LOW>;
- default-state = "off";
- };
-
- led-4 {
- function = LED_FUNCTION_STATUS;
- color = <LED_COLOR_ID_GREEN>;
- label = "panel5";
- gpios = <&gpio3 25 GPIO_ACTIVE_LOW>;
- default-state = "off";
- };
- };
-
- pcie0_refclk: pcie0-refclk {
- compatible = "fixed-clock";
- #clock-cells = <0>;
- clock-frequency = <100000000>;
- };
-
- pps {
- compatible = "pps-gpio";
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_pps>;
- gpios = <&gpio3 24 GPIO_ACTIVE_HIGH>;
- status = "okay";
- };
-
- reg_3p3v: regulator-3p3v {
- compatible = "regulator-fixed";
- regulator-name = "3P3V";
- regulator-min-microvolt = <3300000>;
- regulator-max-microvolt = <3300000>;
- regulator-always-on;
- };
-
- reg_usb1_vbus: regulator-usb1 {
- compatible = "regulator-fixed";
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_reg_usb1>;
- regulator-name = "usb_usb1_vbus";
- gpio = <&gpio2 7 GPIO_ACTIVE_HIGH>;
- enable-active-high;
- regulator-min-microvolt = <5000000>;
- regulator-max-microvolt = <5000000>;
- };
-
- reg_wifi: regulator-wifi {
- compatible = "regulator-fixed";
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_reg_wl>;
- regulator-name = "wifi";
- gpio = <&gpio2 19 GPIO_ACTIVE_HIGH>;
- enable-active-high;
- startup-delay-us = <100>;
- regulator-min-microvolt = <3300000>;
- regulator-max-microvolt = <3300000>;
- };
-};
-
-&A53_0 {
- cpu-supply = <&buck2>;
-};
-
-&A53_1 {
- cpu-supply = <&buck2>;
-};
-
-&A53_2 {
- cpu-supply = <&buck2>;
-};
-
-&A53_3 {
- cpu-supply = <&buck2>;
-};
-
-&ddrc {
- operating-points-v2 = <&ddrc_opp_table>;
-
- ddrc_opp_table: opp-table {
- compatible = "operating-points-v2";
-
- opp-25M {
- opp-hz = /bits/ 64 <25000000>;
- };
-
- opp-100M {
- opp-hz = /bits/ 64 <100000000>;
- };
-
- opp-750M {
- opp-hz = /bits/ 64 <750000000>;
- };
- };
-};
-
-&ecspi1 {
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_spi1>;
- cs-gpios = <&gpio5 9 GPIO_ACTIVE_LOW>;
- status = "okay";
-
- can@0 {
- compatible = "microchip,mcp2515";
- reg = <0>;
- clocks = <&can20m>;
- interrupt-parent = <&gpio2>;
- interrupts = <3 IRQ_TYPE_LEVEL_LOW>;
- spi-max-frequency = <10000000>;
- };
-};
-
-/* off-board header */
-&ecspi2 {
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_spi2>;
- cs-gpios = <&gpio5 13 GPIO_ACTIVE_LOW>;
- status = "okay";
-};
-
-&fec1 {
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_fec1>;
- phy-mode = "rgmii-id";
- phy-handle = <ðphy0>;
- local-mac-address = [00 00 00 00 00 00];
- status = "okay";
-
- mdio {
- #address-cells = <1>;
- #size-cells = <0>;
-
- ethphy0: ethernet-phy@0 {
- compatible = "ethernet-phy-ieee802.3-c22";
- reg = <0>;
- ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_00_NS>;
- ti,tx-internal-delay = <DP83867_RGMIIDCTL_2_00_NS>;
- tx-fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>;
- rx-fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>;
- };
- };
-};
-
-&gpio1 {
- gpio-line-names = "", "", "", "", "", "", "", "",
- "m2_pwr_en", "", "", "", "", "m2_reset", "", "m2_wdis#",
- "", "", "", "", "", "", "", "",
- "", "", "", "", "", "", "", "";
-};
-
-&gpio2 {
- gpio-line-names = "", "", "", "", "", "", "", "",
- "uart2_en#", "", "", "", "", "", "", "",
- "", "", "", "", "", "", "", "",
- "", "", "", "", "", "", "", "";
-};
-
-&gpio3 {
- gpio-line-names = "", "m2_gdis#", "", "", "", "", "", "m2_off#",
- "", "", "", "", "", "", "", "",
- "", "", "", "", "", "", "", "",
- "", "", "", "", "", "", "", "";
-};
-
-&gpio4 {
- gpio-line-names = "", "", "", "", "", "", "", "",
- "", "", "", "amp_gpio3", "amp_gpio2", "", "amp_gpio1", "",
- "lte_pwr#", "lte_rst", "lte_int", "",
- "amp_gpio4", "app_gpio1", "vdd_4p0_en", "uart1_rs485",
- "", "uart1_term", "uart1_half", "app_gpio2",
- "mipi_gpio1", "", "", "";
-};
-
-&gpio5 {
- gpio-line-names = "", "", "", "mipi_gpio4",
- "mipi_gpio3", "mipi_gpio2", "", "",
- "", "", "", "", "", "", "", "",
- "", "", "", "", "", "", "", "",
- "", "", "", "", "", "", "", "";
-};
-
-&i2c1 {
- clock-frequency = <100000>;
- pinctrl-names = "default", "gpio";
- pinctrl-0 = <&pinctrl_i2c1>;
- pinctrl-1 = <&pinctrl_i2c1_gpio>;
- scl-gpios = <&gpio5 14 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
- sda-gpios = <&gpio5 15 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
- status = "okay";
-
- gsc: gsc@20 {
- compatible = "gw,gsc";
- reg = <0x20>;
- pinctrl-0 = <&pinctrl_gsc>;
- interrupt-parent = <&gpio2>;
- interrupts = <6 IRQ_TYPE_EDGE_FALLING>;
- interrupt-controller;
- #interrupt-cells = <1>;
-
- adc {
- compatible = "gw,gsc-adc";
- #address-cells = <1>;
- #size-cells = <0>;
-
- channel@6 {
- gw,mode = <0>;
- reg = <0x06>;
- label = "temp";
- };
-
- channel@8 {
- gw,mode = <1>;
- reg = <0x08>;
- label = "vdd_bat";
- };
-
- channel@82 {
- gw,mode = <2>;
- reg = <0x82>;
- label = "vin";
- gw,voltage-divider-ohms = <22100 1000>;
- gw,voltage-offset-microvolt = <700000>;
- };
-
- channel@84 {
- gw,mode = <2>;
- reg = <0x84>;
- label = "vin_4p0";
- gw,voltage-divider-ohms = <10000 10000>;
- };
-
- channel@86 {
- gw,mode = <2>;
- reg = <0x86>;
- label = "vdd_3p3";
- gw,voltage-divider-ohms = <10000 10000>;
- };
-
- channel@88 {
- gw,mode = <2>;
- reg = <0x88>;
- label = "vdd_0p9";
- };
-
- channel@8c {
- gw,mode = <2>;
- reg = <0x8c>;
- label = "vdd_soc";
- };
-
- channel@8e {
- gw,mode = <2>;
- reg = <0x8e>;
- label = "vdd_arm";
- };
-
- channel@90 {
- gw,mode = <2>;
- reg = <0x90>;
- label = "vdd_1p8";
- };
-
- channel@92 {
- gw,mode = <2>;
- reg = <0x92>;
- label = "vdd_dram";
- };
-
- channel@98 {
- gw,mode = <2>;
- reg = <0x98>;
- label = "vdd_1p0";
- };
-
- channel@9a {
- gw,mode = <2>;
- reg = <0x9a>;
- label = "vdd_2p5";
- gw,voltage-divider-ohms = <10000 10000>;
- };
-
- channel@9c {
- gw,mode = <2>;
- reg = <0x9c>;
- label = "vdd_5p0";
- gw,voltage-divider-ohms = <10000 10000>;
- };
-
- channel@a2 {
- gw,mode = <2>;
- reg = <0xa2>;
- label = "vdd_gsc";
- gw,voltage-divider-ohms = <10000 10000>;
- };
- };
- };
-
- gpio: gpio@23 {
- compatible = "nxp,pca9555";
- reg = <0x23>;
- gpio-controller;
- #gpio-cells = <2>;
- interrupt-parent = <&gsc>;
- interrupts = <4>;
- };
-
- pmic@4b {
- compatible = "rohm,bd71847";
- reg = <0x4b>;
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_pmic>;
- interrupt-parent = <&gpio3>;
- interrupts = <8 IRQ_TYPE_LEVEL_LOW>;
- rohm,reset-snvs-powered;
- #clock-cells = <0>;
- clocks = <&osc_32k 0>;
- clock-output-names = "clk-32k-out";
-
- regulators {
- /* vdd_soc: 0.805-0.900V (typ=0.8V) */
- BUCK1 {
- regulator-name = "buck1";
- regulator-min-microvolt = <700000>;
- regulator-max-microvolt = <1300000>;
- regulator-boot-on;
- regulator-always-on;
- regulator-ramp-delay = <1250>;
- };
-
- /* vdd_arm: 0.805-1.0V (typ=0.9V) */
- buck2: BUCK2 {
- regulator-name = "buck2";
- regulator-min-microvolt = <700000>;
- regulator-max-microvolt = <1300000>;
- regulator-boot-on;
- regulator-always-on;
- regulator-ramp-delay = <1250>;
- rohm,dvs-run-voltage = <1000000>;
- rohm,dvs-idle-voltage = <900000>;
- };
-
- /* vdd_0p9: 0.805-1.0V (typ=0.9V) */
- BUCK3 {
- regulator-name = "buck3";
- regulator-min-microvolt = <700000>;
- regulator-max-microvolt = <1350000>;
- regulator-boot-on;
- regulator-always-on;
- };
-
- /* vdd_3p3 */
- BUCK4 {
- regulator-name = "buck4";
- regulator-min-microvolt = <3000000>;
- regulator-max-microvolt = <3300000>;
- regulator-boot-on;
- regulator-always-on;
- };
-
- /* vdd_1p8 */
- BUCK5 {
- regulator-name = "buck5";
- regulator-min-microvolt = <1605000>;
- regulator-max-microvolt = <1995000>;
- regulator-boot-on;
- regulator-always-on;
- };
-
- /* vdd_dram */
- BUCK6 {
- regulator-name = "buck6";
- regulator-min-microvolt = <800000>;
- regulator-max-microvolt = <1400000>;
- regulator-boot-on;
- regulator-always-on;
- };
-
- /* nvcc_snvs_1p8 */
- LDO1 {
- regulator-name = "ldo1";
- regulator-min-microvolt = <1600000>;
- regulator-max-microvolt = <1900000>;
- regulator-boot-on;
- regulator-always-on;
- };
-
- /* vdd_snvs_0p8 */
- LDO2 {
- regulator-name = "ldo2";
- regulator-min-microvolt = <800000>;
- regulator-max-microvolt = <900000>;
- regulator-boot-on;
- regulator-always-on;
- };
-
- /* vdda_1p8 */
- LDO3 {
- regulator-name = "ldo3";
- regulator-min-microvolt = <1800000>;
- regulator-max-microvolt = <3300000>;
- regulator-boot-on;
- regulator-always-on;
- };
-
- LDO4 {
- regulator-name = "ldo4";
- regulator-min-microvolt = <900000>;
- regulator-max-microvolt = <1800000>;
- regulator-boot-on;
- regulator-always-on;
- };
-
- LDO6 {
- regulator-name = "ldo6";
- regulator-min-microvolt = <900000>;
- regulator-max-microvolt = <1800000>;
- regulator-boot-on;
- regulator-always-on;
- };
- };
- };
-
- eeprom@50 {
- compatible = "atmel,24c02";
- reg = <0x50>;
- pagesize = <16>;
- };
-
- eeprom@51 {
- compatible = "atmel,24c02";
- reg = <0x51>;
- pagesize = <16>;
- };
-
- eeprom@52 {
- compatible = "atmel,24c02";
- reg = <0x52>;
- pagesize = <16>;
- };
-
- eeprom@53 {
- compatible = "atmel,24c02";
- reg = <0x53>;
- pagesize = <16>;
- };
-
- rtc@68 {
- compatible = "dallas,ds1672";
- reg = <0x68>;
- };
-};
-
-&i2c2 {
- clock-frequency = <400000>;
- pinctrl-names = "default", "gpio";
- pinctrl-0 = <&pinctrl_i2c2>;
- pinctrl-1 = <&pinctrl_i2c2_gpio>;
- scl-gpios = <&gpio5 16 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
- sda-gpios = <&gpio5 17 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
- status = "okay";
-
- accelerometer@19 {
- compatible = "st,lis2de12";
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_accel>;
- reg = <0x19>;
- st,drdy-int-pin = <1>;
- interrupt-parent = <&gpio1>;
- interrupts = <12 IRQ_TYPE_LEVEL_LOW>;
- interrupt-names = "INT1";
- };
-};
-
-/* off-board header */
-&i2c3 {
- clock-frequency = <400000>;
- pinctrl-names = "default", "gpio";
- pinctrl-0 = <&pinctrl_i2c3>;
- pinctrl-1 = <&pinctrl_i2c3_gpio>;
- scl-gpios = <&gpio5 18 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
- sda-gpios = <&gpio5 19 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
- status = "okay";
-};
-
-/* off-board header */
-&i2c4 {
- clock-frequency = <400000>;
- pinctrl-names = "default", "gpio";
- pinctrl-0 = <&pinctrl_i2c4>;
- pinctrl-1 = <&pinctrl_i2c4_gpio>;
- scl-gpios = <&gpio5 20 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
- sda-gpios = <&gpio5 21 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
- status = "okay";
-};
-
-&pcie_phy {
- fsl,refclk-pad-mode = <IMX8_PCIE_REFCLK_PAD_INPUT>;
- fsl,clkreq-unsupported;
- clocks = <&pcie0_refclk>;
- clock-names = "ref";
- status = "okay";
-};
-
-&pcie0 {
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_pcie0>;
- reset-gpio = <&gpio4 5 GPIO_ACTIVE_LOW>;
- clocks = <&clk IMX8MM_CLK_PCIE1_ROOT>, <&clk IMX8MM_CLK_PCIE1_AUX>,
- <&pcie0_refclk>;
- clock-names = "pcie", "pcie_aux", "pcie_bus";
- assigned-clocks = <&clk IMX8MM_CLK_PCIE1_AUX>,
- <&clk IMX8MM_CLK_PCIE1_CTRL>;
- assigned-clock-rates = <10000000>, <250000000>;
- assigned-clock-parents = <&clk IMX8MM_SYS_PLL2_50M>,
- <&clk IMX8MM_SYS_PLL2_250M>;
- status = "okay";
-
- pcie@0,0 {
- reg = <0x0000 0 0 0 0>;
- #address-cells = <1>;
- #size-cells = <0>;
-
- eth1: pcie@1,0 {
- reg = <0x0000 0 0 0 0>;
- #address-cells = <1>;
- #size-cells = <0>;
-
- local-mac-address = [00 00 00 00 00 00];
- };
- };
-};
-
-/* off-board header */
-&sai3 {
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_sai3>;
- assigned-clocks = <&clk IMX8MM_CLK_SAI3>;
- assigned-clock-parents = <&clk IMX8MM_AUDIO_PLL1_OUT>;
- assigned-clock-rates = <24576000>;
- status = "okay";
-};
-
-/* RS232/RS485/RS422 selectable */
-&uart1 {
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_uart1>, <&pinctrl_uart1_gpio>;
- rts-gpios = <&gpio4 10 GPIO_ACTIVE_LOW>;
- cts-gpios = <&gpio4 24 GPIO_ACTIVE_LOW>;
- uart-has-rtscts;
- status = "okay";
-};
-
-/* RS232 console */
-&uart2 {
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_uart2>;
- status = "okay";
-};
-
-/* bluetooth HCI */
-&uart3 {
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_uart3>, <&pinctrl_uart3_gpio>;
- rts-gpios = <&gpio2 1 GPIO_ACTIVE_LOW>;
- cts-gpios = <&gpio2 0 GPIO_ACTIVE_LOW>;
- uart-has-rtscts;
- status = "okay";
-
- bluetooth {
- compatible = "brcm,bcm4330-bt";
- shutdown-gpios = <&gpio2 12 GPIO_ACTIVE_HIGH>;
- };
-};
-
-/* LTE Cat M1/NB1/EGPRS modem or GPS (loading option) */
-&uart4 {
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_uart4>;
- rts-gpios = <&gpio4 2 GPIO_ACTIVE_LOW>;
- cts-gpios = <&gpio4 1 GPIO_ACTIVE_LOW>;
- dtr-gpios = <&gpio4 3 GPIO_ACTIVE_LOW>;
- dsr-gpios = <&gpio4 4 GPIO_ACTIVE_LOW>;
- dcd-gpios = <&gpio4 6 GPIO_ACTIVE_LOW>;
- uart-has-rtscts;
- status = "okay";
-};
-
-&usbotg1 {
- dr_mode = "host";
- vbus-supply = <®_usb1_vbus>;
- disable-over-current;
- status = "okay";
-};
-
-&usbotg2 {
- dr_mode = "host";
- disable-over-current;
- status = "okay";
-};
-
-/* SDIO WiFi */
-&usdhc2 {
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_usdhc2>;
- bus-width = <4>;
- non-removable;
- vmmc-supply = <®_wifi>;
- status = "okay";
-};
-
-/* eMMC */
-&usdhc3 {
- pinctrl-names = "default", "state_100mhz", "state_200mhz";
- pinctrl-0 = <&pinctrl_usdhc3>;
- pinctrl-1 = <&pinctrl_usdhc3_100mhz>;
- pinctrl-2 = <&pinctrl_usdhc3_200mhz>;
- bus-width = <8>;
- non-removable;
- status = "okay";
-};
-
-&wdog1 {
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_wdog>;
- fsl,ext-reset-output;
- status = "okay";
-};
-
-&iomuxc {
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_hog>;
-
- pinctrl_hog: hoggrp {
- fsl,pins = <
- MX8MM_IOMUXC_NAND_CE0_B_GPIO3_IO1 0x40000159 /* M2_GDIS# */
- MX8MM_IOMUXC_GPIO1_IO08_GPIO1_IO8 0x40000041 /* M2_PWR_EN */
- MX8MM_IOMUXC_GPIO1_IO13_GPIO1_IO13 0x40000041 /* M2_RESET */
- MX8MM_IOMUXC_NAND_DATA01_GPIO3_IO7 0x40000119 /* M2_OFF# */
- MX8MM_IOMUXC_GPIO1_IO15_GPIO1_IO15 0x40000159 /* M2_WDIS# */
- MX8MM_IOMUXC_SAI1_TXD6_GPIO4_IO18 0x40000041 /* LTE_INT */
- MX8MM_IOMUXC_SAI1_TXD5_GPIO4_IO17 0x40000041 /* LTE_RST# */
- MX8MM_IOMUXC_SAI1_TXD4_GPIO4_IO16 0x40000041 /* LTE_PWR */
- MX8MM_IOMUXC_SAI1_TXD2_GPIO4_IO14 0x40000041 /* AMP GPIO1 */
- MX8MM_IOMUXC_SAI1_TXD0_GPIO4_IO12 0x40000041 /* AMP GPIO2 */
- MX8MM_IOMUXC_SAI1_TXC_GPIO4_IO11 0x40000041 /* AMP GPIO3 */
- MX8MM_IOMUXC_SAI1_MCLK_GPIO4_IO20 0x40000041 /* AMP_GPIO4 */
- MX8MM_IOMUXC_SAI2_RXFS_GPIO4_IO21 0x40000041 /* APP GPIO1 */
- MX8MM_IOMUXC_SAI2_RXC_GPIO4_IO22 0x40000041 /* VDD_4P0_EN */
- MX8MM_IOMUXC_SAI2_MCLK_GPIO4_IO27 0x40000041 /* APP GPIO2 */
- MX8MM_IOMUXC_SD1_DATA6_GPIO2_IO8 0x40000041 /* UART2_EN# */
- MX8MM_IOMUXC_SAI3_RXFS_GPIO4_IO28 0x40000041 /* MIPI_GPIO1 */
- MX8MM_IOMUXC_SPDIF_EXT_CLK_GPIO5_IO5 0x40000041 /* MIPI_GPIO2 */
- MX8MM_IOMUXC_SPDIF_RX_GPIO5_IO4 0x40000041 /* MIPI_GPIO3/PWM2 */
- MX8MM_IOMUXC_SPDIF_TX_GPIO5_IO3 0x40000041 /* MIPI_GPIO4/PWM3 */
- >;
- };
-
- pinctrl_accel: accelgrp {
- fsl,pins = <
- MX8MM_IOMUXC_GPIO1_IO12_GPIO1_IO12 0x159
- >;
- };
-
- pinctrl_fec1: fec1grp {
- fsl,pins = <
- MX8MM_IOMUXC_ENET_MDC_ENET1_MDC 0x3
- MX8MM_IOMUXC_ENET_MDIO_ENET1_MDIO 0x3
- MX8MM_IOMUXC_ENET_TD3_ENET1_RGMII_TD3 0x1f
- MX8MM_IOMUXC_ENET_TD2_ENET1_RGMII_TD2 0x1f
- MX8MM_IOMUXC_ENET_TD1_ENET1_RGMII_TD1 0x1f
- MX8MM_IOMUXC_ENET_TD0_ENET1_RGMII_TD0 0x1f
- MX8MM_IOMUXC_ENET_RD3_ENET1_RGMII_RD3 0x91
- MX8MM_IOMUXC_ENET_RD2_ENET1_RGMII_RD2 0x91
- MX8MM_IOMUXC_ENET_RD1_ENET1_RGMII_RD1 0x91
- MX8MM_IOMUXC_ENET_RD0_ENET1_RGMII_RD0 0x91
- MX8MM_IOMUXC_ENET_TXC_ENET1_RGMII_TXC 0x1f
- MX8MM_IOMUXC_ENET_RXC_ENET1_RGMII_RXC 0x91
- MX8MM_IOMUXC_ENET_RX_CTL_ENET1_RGMII_RX_CTL 0x91
- MX8MM_IOMUXC_ENET_TX_CTL_ENET1_RGMII_TX_CTL 0x1f
- MX8MM_IOMUXC_GPIO1_IO10_GPIO1_IO10 0x19 /* RST# */
- MX8MM_IOMUXC_GPIO1_IO11_GPIO1_IO11 0x19 /* IRQ# */
- >;
- };
-
- pinctrl_gsc: gscgrp {
- fsl,pins = <
- MX8MM_IOMUXC_SD1_DATA4_GPIO2_IO6 0x40
- >;
- };
-
- pinctrl_i2c1: i2c1grp {
- fsl,pins = <
- MX8MM_IOMUXC_I2C1_SCL_I2C1_SCL 0x400001c3
- MX8MM_IOMUXC_I2C1_SDA_I2C1_SDA 0x400001c3
- >;
- };
-
- pinctrl_i2c1_gpio: i2c1gpiogrp {
- fsl,pins = <
- MX8MM_IOMUXC_I2C1_SCL_GPIO5_IO14 0x400001c3
- MX8MM_IOMUXC_I2C1_SDA_GPIO5_IO15 0x400001c3
- >;
- };
-
- pinctrl_i2c2: i2c2grp {
- fsl,pins = <
- MX8MM_IOMUXC_I2C2_SCL_I2C2_SCL 0x400001c3
- MX8MM_IOMUXC_I2C2_SDA_I2C2_SDA 0x400001c3
- >;
- };
-
- pinctrl_i2c2_gpio: i2c2gpiogrp {
- fsl,pins = <
- MX8MM_IOMUXC_I2C2_SCL_GPIO5_IO16 0x400001c3
- MX8MM_IOMUXC_I2C2_SDA_GPIO5_IO17 0x400001c3
- >;
- };
-
- pinctrl_i2c3: i2c3grp {
- fsl,pins = <
- MX8MM_IOMUXC_I2C3_SCL_I2C3_SCL 0x400001c3
- MX8MM_IOMUXC_I2C3_SDA_I2C3_SDA 0x400001c3
- >;
- };
-
- pinctrl_i2c3_gpio: i2c3gpiogrp {
- fsl,pins = <
- MX8MM_IOMUXC_I2C3_SCL_GPIO5_IO18 0x400001c3
- MX8MM_IOMUXC_I2C3_SDA_GPIO5_IO19 0x400001c3
- >;
- };
-
- pinctrl_i2c4: i2c4grp {
- fsl,pins = <
- MX8MM_IOMUXC_I2C4_SCL_I2C4_SCL 0x400001c3
- MX8MM_IOMUXC_I2C4_SDA_I2C4_SDA 0x400001c3
- >;
- };
-
- pinctrl_i2c4_gpio: i2c4gpiogrp {
- fsl,pins = <
- MX8MM_IOMUXC_I2C4_SCL_GPIO5_IO20 0x400001c3
- MX8MM_IOMUXC_I2C4_SDA_GPIO5_IO21 0x400001c3
- >;
- };
-
- pinctrl_gpio_leds: gpioledgrp {
- fsl,pins = <
- MX8MM_IOMUXC_SAI5_RXD0_GPIO3_IO21 0x19
- MX8MM_IOMUXC_SAI5_RXD2_GPIO3_IO23 0x19
- MX8MM_IOMUXC_SAI5_RXD1_GPIO3_IO22 0x19
- MX8MM_IOMUXC_SAI5_RXC_GPIO3_IO20 0x19
- MX8MM_IOMUXC_SAI5_MCLK_GPIO3_IO25 0x19
- >;
- };
-
- pinctrl_pcie0: pciegrp {
- fsl,pins = <
- MX8MM_IOMUXC_SAI1_RXD3_GPIO4_IO5 0x41
- >;
- };
-
- pinctrl_pmic: pmicgrp {
- fsl,pins = <
- MX8MM_IOMUXC_NAND_DATA02_GPIO3_IO8 0x41
- >;
- };
-
- pinctrl_pps: ppsgrp {
- fsl,pins = <
- MX8MM_IOMUXC_SAI5_RXD3_GPIO3_IO24 0x141 /* PPS */
- >;
- };
-
- pinctrl_reg_wl: regwlgrp {
- fsl,pins = <
- MX8MM_IOMUXC_SD2_RESET_B_GPIO2_IO19 0x41 /* WLAN_WLON */
- >;
- };
-
- pinctrl_reg_usb1: regusb1grp {
- fsl,pins = <
- MX8MM_IOMUXC_SD1_DATA5_GPIO2_IO7 0x41
- >;
- };
-
- pinctrl_sai3: sai3grp {
- fsl,pins = <
- MX8MM_IOMUXC_SAI3_MCLK_SAI3_MCLK 0xd6
- MX8MM_IOMUXC_SAI3_RXD_SAI3_RX_DATA0 0xd6
- MX8MM_IOMUXC_SAI3_TXC_SAI3_TX_BCLK 0xd6
- MX8MM_IOMUXC_SAI3_TXD_SAI3_TX_DATA0 0xd6
- MX8MM_IOMUXC_SAI3_TXFS_SAI3_TX_SYNC 0xd6
- >;
- };
-
- pinctrl_spi1: spi1grp {
- fsl,pins = <
- MX8MM_IOMUXC_ECSPI1_SCLK_ECSPI1_SCLK 0x82
- MX8MM_IOMUXC_ECSPI1_MOSI_ECSPI1_MOSI 0x82
- MX8MM_IOMUXC_ECSPI1_MISO_ECSPI1_MISO 0x82
- MX8MM_IOMUXC_ECSPI1_SS0_GPIO5_IO9 0x40
- MX8MM_IOMUXC_SD1_DATA1_GPIO2_IO3 0x140 /* CAN_IRQ# */
- >;
- };
-
- pinctrl_spi2: spi2grp {
- fsl,pins = <
- MX8MM_IOMUXC_ECSPI2_SCLK_ECSPI2_SCLK 0x82
- MX8MM_IOMUXC_ECSPI2_MOSI_ECSPI2_MOSI 0x82
- MX8MM_IOMUXC_ECSPI2_MISO_ECSPI2_MISO 0x82
- MX8MM_IOMUXC_ECSPI2_SS0_GPIO5_IO13 0x40 /* SS0 */
- >;
- };
-
- pinctrl_uart1: uart1grp {
- fsl,pins = <
- MX8MM_IOMUXC_UART1_RXD_UART1_DCE_RX 0x140
- MX8MM_IOMUXC_UART1_TXD_UART1_DCE_TX 0x140
- MX8MM_IOMUXC_SAI1_TXFS_GPIO4_IO10 0x140 /* RTS */
- MX8MM_IOMUXC_SAI2_TXFS_GPIO4_IO24 0x140 /* CTS */
- >;
- };
-
- pinctrl_uart1_gpio: uart1gpiogrp {
- fsl,pins = <
- MX8MM_IOMUXC_SAI2_TXD0_GPIO4_IO26 0x40000110 /* HALF */
- MX8MM_IOMUXC_SAI2_TXC_GPIO4_IO25 0x40000110 /* TERM */
- MX8MM_IOMUXC_SAI2_RXD0_GPIO4_IO23 0x40000110 /* RS485 */
- >;
- };
-
- pinctrl_uart2: uart2grp {
- fsl,pins = <
- MX8MM_IOMUXC_UART2_RXD_UART2_DCE_RX 0x140
- MX8MM_IOMUXC_UART2_TXD_UART2_DCE_TX 0x140
- >;
- };
-
- pinctrl_uart3_gpio: uart3_gpiogrp {
- fsl,pins = <
- MX8MM_IOMUXC_SD2_CD_B_GPIO2_IO12 0x41 /* BT_EN# */
- >;
- };
-
- pinctrl_uart3: uart3grp {
- fsl,pins = <
- MX8MM_IOMUXC_UART3_RXD_UART3_DCE_RX 0x140
- MX8MM_IOMUXC_UART3_TXD_UART3_DCE_TX 0x140
- MX8MM_IOMUXC_SD1_CLK_GPIO2_IO0 0x140 /* CTS */
- MX8MM_IOMUXC_SD1_CMD_GPIO2_IO1 0x140 /* RTS */
- >;
- };
-
- pinctrl_uart4: uart4grp {
- fsl,pins = <
- MX8MM_IOMUXC_UART4_RXD_UART4_DCE_RX 0x140
- MX8MM_IOMUXC_UART4_TXD_UART4_DCE_TX 0x140
- MX8MM_IOMUXC_SAI1_RXC_GPIO4_IO1 0x140 /* CTS */
- MX8MM_IOMUXC_SAI1_RXD0_GPIO4_IO2 0x140 /* RTS */
- MX8MM_IOMUXC_SAI1_RXD1_GPIO4_IO3 0x140 /* DTR */
- MX8MM_IOMUXC_SAI1_RXD2_GPIO4_IO4 0x140 /* DSR */
- MX8MM_IOMUXC_SAI1_RXD4_GPIO4_IO6 0x140 /* DCD */
- MX8MM_IOMUXC_SAI1_RXD5_GPIO4_IO7 0x140 /* RI */
- MX8MM_IOMUXC_SAI1_RXFS_GPIO4_IO0 0x140 /* GNSS_PPS */
- MX8MM_IOMUXC_GPIO1_IO06_GPIO1_IO6 0x141 /* GNSS_GASP */
- >;
- };
-
- pinctrl_usdhc2: usdhc2grp {
- fsl,pins = <
- MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK 0x190
- MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d0
- MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d0
- MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d0
- MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d0
- MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d0
- >;
- };
-
- pinctrl_usdhc3: usdhc3grp {
- fsl,pins = <
- MX8MM_IOMUXC_NAND_WE_B_USDHC3_CLK 0x190
- MX8MM_IOMUXC_NAND_WP_B_USDHC3_CMD 0x1d0
- MX8MM_IOMUXC_NAND_DATA04_USDHC3_DATA0 0x1d0
- MX8MM_IOMUXC_NAND_DATA05_USDHC3_DATA1 0x1d0
- MX8MM_IOMUXC_NAND_DATA06_USDHC3_DATA2 0x1d0
- MX8MM_IOMUXC_NAND_DATA07_USDHC3_DATA3 0x1d0
- MX8MM_IOMUXC_NAND_RE_B_USDHC3_DATA4 0x1d0
- MX8MM_IOMUXC_NAND_CE2_B_USDHC3_DATA5 0x1d0
- MX8MM_IOMUXC_NAND_CE3_B_USDHC3_DATA6 0x1d0
- MX8MM_IOMUXC_NAND_CLE_USDHC3_DATA7 0x1d0
- MX8MM_IOMUXC_NAND_CE1_B_USDHC3_STROBE 0x190
- >;
- };
-
- pinctrl_usdhc3_100mhz: usdhc3-100mhzgrp {
- fsl,pins = <
- MX8MM_IOMUXC_NAND_WE_B_USDHC3_CLK 0x194
- MX8MM_IOMUXC_NAND_WP_B_USDHC3_CMD 0x1d4
- MX8MM_IOMUXC_NAND_DATA04_USDHC3_DATA0 0x1d4
- MX8MM_IOMUXC_NAND_DATA05_USDHC3_DATA1 0x1d4
- MX8MM_IOMUXC_NAND_DATA06_USDHC3_DATA2 0x1d4
- MX8MM_IOMUXC_NAND_DATA07_USDHC3_DATA3 0x1d4
- MX8MM_IOMUXC_NAND_RE_B_USDHC3_DATA4 0x1d4
- MX8MM_IOMUXC_NAND_CE2_B_USDHC3_DATA5 0x1d4
- MX8MM_IOMUXC_NAND_CE3_B_USDHC3_DATA6 0x1d4
- MX8MM_IOMUXC_NAND_CLE_USDHC3_DATA7 0x1d4
- MX8MM_IOMUXC_NAND_CE1_B_USDHC3_STROBE 0x194
- >;
- };
-
- pinctrl_usdhc3_200mhz: usdhc3-200mhzgrp {
- fsl,pins = <
- MX8MM_IOMUXC_NAND_WE_B_USDHC3_CLK 0x196
- MX8MM_IOMUXC_NAND_WP_B_USDHC3_CMD 0x1d6
- MX8MM_IOMUXC_NAND_DATA04_USDHC3_DATA0 0x1d6
- MX8MM_IOMUXC_NAND_DATA05_USDHC3_DATA1 0x1d6
- MX8MM_IOMUXC_NAND_DATA06_USDHC3_DATA2 0x1d6
- MX8MM_IOMUXC_NAND_DATA07_USDHC3_DATA3 0x1d6
- MX8MM_IOMUXC_NAND_RE_B_USDHC3_DATA4 0x1d6
- MX8MM_IOMUXC_NAND_CE2_B_USDHC3_DATA5 0x1d6
- MX8MM_IOMUXC_NAND_CE3_B_USDHC3_DATA6 0x1d6
- MX8MM_IOMUXC_NAND_CLE_USDHC3_DATA7 0x1d6
- MX8MM_IOMUXC_NAND_CE1_B_USDHC3_STROBE 0x196
- >;
- };
-
- pinctrl_wdog: wdoggrp {
- fsl,pins = <
- MX8MM_IOMUXC_GPIO1_IO02_WDOG1_WDOG_B 0xc6
- >;
- };
-};
diff --git a/arch/arm/dts/imx8mm-venice-gw7903.dts b/arch/arm/dts/imx8mm-venice-gw7903.dts
deleted file mode 100644
index 1ec91c5..0000000
--- a/arch/arm/dts/imx8mm-venice-gw7903.dts
+++ /dev/null
@@ -1,869 +0,0 @@
-// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
-/*
- * Copyright 2022 Gateworks Corporation
- */
-
-/dts-v1/;
-
-#include <dt-bindings/gpio/gpio.h>
-#include <dt-bindings/input/linux-event-codes.h>
-#include <dt-bindings/leds/common.h>
-#include <dt-bindings/phy/phy-imx8-pcie.h>
-
-#include "imx8mm.dtsi"
-
-/ {
- model = "Gateworks Venice GW7903 i.MX8MM board";
- compatible = "gw,imx8mm-gw7903", "fsl,imx8mm";
-
- aliases {
- ethernet0 = &fec1;
- usb0 = &usbotg1;
- };
-
- chosen {
- stdout-path = &uart2;
- };
-
- memory@40000000 {
- device_type = "memory";
- reg = <0x0 0x40000000 0 0x80000000>;
- };
-
- gpio-keys {
- compatible = "gpio-keys";
-
- key-user-pb {
- label = "user_pb";
- gpios = <&gpio 2 GPIO_ACTIVE_LOW>;
- linux,code = <BTN_0>;
- };
-
- key-user-pb1x {
- label = "user_pb1x";
- linux,code = <BTN_1>;
- interrupt-parent = <&gsc>;
- interrupts = <0>;
- };
-
- key-erased {
- label = "key_erased";
- linux,code = <BTN_2>;
- interrupt-parent = <&gsc>;
- interrupts = <1>;
- };
-
- key-eeprom-wp {
- label = "eeprom_wp";
- linux,code = <BTN_3>;
- interrupt-parent = <&gsc>;
- interrupts = <2>;
- };
-
- switch-hold {
- label = "switch_hold";
- linux,code = <BTN_5>;
- interrupt-parent = <&gsc>;
- interrupts = <7>;
- };
- };
-
- led-controller {
- compatible = "gpio-leds";
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_gpio_leds>;
-
- led-0 {
- function = LED_FUNCTION_STATUS;
- color = <LED_COLOR_ID_RED>;
- label = "led01_red";
- gpios = <&gpio5 5 GPIO_ACTIVE_HIGH>;
- default-state = "off";
- };
-
- led-1 {
- function = LED_FUNCTION_STATUS;
- color = <LED_COLOR_ID_GREEN>;
- label = "led01_grn";
- gpios = <&gpio4 30 GPIO_ACTIVE_HIGH>;
- default-state = "off";
- };
-
- led-2 {
- function = LED_FUNCTION_STATUS;
- color = <LED_COLOR_ID_RED>;
- label = "led02_red";
- gpios = <&gpio5 2 GPIO_ACTIVE_HIGH>;
- default-state = "off";
- };
-
- led-3 {
- function = LED_FUNCTION_STATUS;
- color = <LED_COLOR_ID_GREEN>;
- label = "led02_grn";
- gpios = <&gpio1 14 GPIO_ACTIVE_HIGH>;
- default-state = "off";
- };
-
- led-4 {
- function = LED_FUNCTION_STATUS;
- color = <LED_COLOR_ID_RED>;
- label = "led03_red";
- gpios = <&gpio1 9 GPIO_ACTIVE_HIGH>;
- default-state = "off";
- };
-
- led-5 {
- function = LED_FUNCTION_STATUS;
- color = <LED_COLOR_ID_GREEN>;
- label = "led03_grn";
- gpios = <&gpio5 3 GPIO_ACTIVE_HIGH>;
- default-state = "off";
- };
-
- led-6 {
- function = LED_FUNCTION_STATUS;
- color = <LED_COLOR_ID_RED>;
- label = "led04_red";
- gpios = <&gpio4 29 GPIO_ACTIVE_HIGH>;
- default-state = "off";
- };
-
- led-7 {
- function = LED_FUNCTION_STATUS;
- color = <LED_COLOR_ID_GREEN>;
- label = "led04_grn";
- gpios = <&gpio4 28 GPIO_ACTIVE_HIGH>;
- default-state = "off";
- };
-
- led-8 {
- function = LED_FUNCTION_STATUS;
- color = <LED_COLOR_ID_RED>;
- label = "led05_red";
- gpios = <&gpio1 13 GPIO_ACTIVE_HIGH>;
- default-state = "off";
- };
-
- led-9 {
- function = LED_FUNCTION_STATUS;
- color = <LED_COLOR_ID_GREEN>;
- label = "led05_grn";
- gpios = <&gpio4 31 GPIO_ACTIVE_HIGH>;
- default-state = "off";
- };
-
- led-a {
- function = LED_FUNCTION_STATUS;
- color = <LED_COLOR_ID_RED>;
- label = "led06_red";
- gpios = <&gpio5 4 GPIO_ACTIVE_HIGH>;
- default-state = "off";
- };
-
- led-b {
- function = LED_FUNCTION_STATUS;
- color = <LED_COLOR_ID_GREEN>;
- label = "led06_grn";
- gpios = <&gpio1 8 GPIO_ACTIVE_HIGH>;
- default-state = "off";
- };
- };
-
- pcie0_refclk: pcie0-refclk {
- compatible = "fixed-clock";
- #clock-cells = <0>;
- clock-frequency = <100000000>;
- };
-
- reg_3p3v: regulator-3p3v {
- compatible = "regulator-fixed";
- regulator-name = "3P3V";
- regulator-min-microvolt = <3300000>;
- regulator-max-microvolt = <3300000>;
- regulator-always-on;
- };
-};
-
-&A53_0 {
- cpu-supply = <&buck2>;
-};
-
-&A53_1 {
- cpu-supply = <&buck2>;
-};
-
-&A53_2 {
- cpu-supply = <&buck2>;
-};
-
-&A53_3 {
- cpu-supply = <&buck2>;
-};
-
-&ddrc {
- operating-points-v2 = <&ddrc_opp_table>;
-
- ddrc_opp_table: opp-table {
- compatible = "operating-points-v2";
-
- opp-25M {
- opp-hz = /bits/ 64 <25000000>;
- };
-
- opp-100M {
- opp-hz = /bits/ 64 <100000000>;
- };
-
- opp-750M {
- opp-hz = /bits/ 64 <750000000>;
- };
- };
-};
-
-&fec1 {
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_fec1>;
- phy-mode = "rgmii-id";
- phy-handle = <ðphy0>;
- local-mac-address = [00 00 00 00 00 00];
- status = "okay";
-
- mdio {
- #address-cells = <1>;
- #size-cells = <0>;
-
- ethphy0: ethernet-phy@0 {
- compatible = "ethernet-phy-ieee802.3-c22";
- reg = <0>;
- rx-internal-delay-ps = <2000>;
- tx-internal-delay-ps = <2500>;
- };
- };
-};
-
-&gpio1 {
- gpio-line-names = "", "", "", "", "", "", "", "",
- "", "", "rs422_en#", "rs485_en#", "rs232_en#", "", "", "",
- "", "", "", "", "", "", "", "",
- "", "", "", "", "", "", "", "";
-};
-
-&gpio2 {
- gpio-line-names = "dig2_in", "dig2_out#", "dig2_ctl", "", "", "", "dig1_ctl", "",
- "dig1_out#", "dig1_in", "", "", "", "", "", "",
- "", "", "", "", "", "", "", "",
- "", "", "", "", "", "", "", "";
-};
-
-&gpio5 {
- gpio-line-names = "", "", "", "", "", "", "", "sim1_det#",
- "sim2_det#", "sim2_sel", "", "", "pci_wdis#", "", "", "",
- "", "", "", "", "", "", "", "",
- "", "", "", "", "", "", "", "";
-};
-
-&i2c1 {
- clock-frequency = <100000>;
- pinctrl-names = "default", "gpio";
- pinctrl-0 = <&pinctrl_i2c1>;
- pinctrl-1 = <&pinctrl_i2c1_gpio>;
- scl-gpios = <&gpio5 14 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
- sda-gpios = <&gpio5 15 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
- status = "okay";
-
- gsc: gsc@20 {
- compatible = "gw,gsc";
- reg = <0x20>;
- pinctrl-0 = <&pinctrl_gsc>;
- interrupt-parent = <&gpio4>;
- interrupts = <26 IRQ_TYPE_EDGE_FALLING>;
- interrupt-controller;
- #interrupt-cells = <1>;
-
- adc {
- compatible = "gw,gsc-adc";
- #address-cells = <1>;
- #size-cells = <0>;
-
- channel@6 {
- gw,mode = <0>;
- reg = <0x06>;
- label = "temp";
- };
-
- channel@8 {
- gw,mode = <1>;
- reg = <0x08>;
- label = "vdd_bat";
- };
-
- channel@82 {
- gw,mode = <2>;
- reg = <0x82>;
- label = "vin";
- gw,voltage-divider-ohms = <22100 1000>;
- gw,voltage-offset-microvolt = <700000>;
- };
-
- channel@84 {
- gw,mode = <2>;
- reg = <0x84>;
- label = "vdd_5p0";
- gw,voltage-divider-ohms = <10000 10000>;
- };
-
- channel@86 {
- gw,mode = <2>;
- reg = <0x86>;
- label = "vdd_3p3";
- gw,voltage-divider-ohms = <10000 10000>;
- };
-
- channel@88 {
- gw,mode = <2>;
- reg = <0x88>;
- label = "vdd_0p9";
- };
-
- channel@8c {
- gw,mode = <2>;
- reg = <0x8c>;
- label = "vdd_soc";
- };
-
- channel@8e {
- gw,mode = <2>;
- reg = <0x8e>;
- label = "vdd_arm";
- };
-
- channel@90 {
- gw,mode = <2>;
- reg = <0x90>;
- label = "vdd_1p8";
- };
-
- channel@92 {
- gw,mode = <2>;
- reg = <0x92>;
- label = "vdd_dram";
- };
-
- channel@a2 {
- gw,mode = <2>;
- reg = <0xa2>;
- label = "vdd_gsc";
- gw,voltage-divider-ohms = <10000 10000>;
- };
- };
- };
-
- gpio: gpio@23 {
- compatible = "nxp,pca9555";
- reg = <0x23>;
- gpio-controller;
- #gpio-cells = <2>;
- interrupt-parent = <&gsc>;
- interrupts = <4>;
- };
-
- eeprom@50 {
- compatible = "atmel,24c02";
- reg = <0x50>;
- pagesize = <16>;
- };
-
- eeprom@51 {
- compatible = "atmel,24c02";
- reg = <0x51>;
- pagesize = <16>;
- };
-
- eeprom@52 {
- compatible = "atmel,24c02";
- reg = <0x52>;
- pagesize = <16>;
- };
-
- eeprom@53 {
- compatible = "atmel,24c02";
- reg = <0x53>;
- pagesize = <16>;
- };
-
- rtc@68 {
- compatible = "dallas,ds1672";
- reg = <0x68>;
- };
-};
-
-&i2c2 {
- clock-frequency = <400000>;
- pinctrl-names = "default", "gpio";
- pinctrl-0 = <&pinctrl_i2c2>;
- pinctrl-1 = <&pinctrl_i2c2_gpio>;
- scl-gpios = <&gpio5 16 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
- sda-gpios = <&gpio5 17 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
- status = "okay";
-
- pmic@4b {
- compatible = "rohm,bd71847";
- reg = <0x4b>;
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_pmic>;
- interrupt-parent = <&gpio3>;
- interrupts = <8 IRQ_TYPE_LEVEL_LOW>;
- rohm,reset-snvs-powered;
- #clock-cells = <0>;
- clocks = <&osc_32k 0>;
- clock-output-names = "clk-32k-out";
-
- regulators {
- /* vdd_soc: 0.805-0.900V (typ=0.8V) */
- BUCK1 {
- regulator-name = "buck1";
- regulator-min-microvolt = <700000>;
- regulator-max-microvolt = <1300000>;
- regulator-boot-on;
- regulator-always-on;
- regulator-ramp-delay = <1250>;
- };
-
- /* vdd_arm: 0.805-1.0V (typ=0.9V) */
- buck2: BUCK2 {
- regulator-name = "buck2";
- regulator-min-microvolt = <700000>;
- regulator-max-microvolt = <1300000>;
- regulator-boot-on;
- regulator-always-on;
- regulator-ramp-delay = <1250>;
- rohm,dvs-run-voltage = <1000000>;
- rohm,dvs-idle-voltage = <900000>;
- };
-
- /* vdd_0p9: 0.805-1.0V (typ=0.9V) */
- BUCK3 {
- regulator-name = "buck3";
- regulator-min-microvolt = <700000>;
- regulator-max-microvolt = <1350000>;
- regulator-boot-on;
- regulator-always-on;
- };
-
- /* vdd_3p3 */
- BUCK4 {
- regulator-name = "buck4";
- regulator-min-microvolt = <3000000>;
- regulator-max-microvolt = <3300000>;
- regulator-boot-on;
- regulator-always-on;
- };
-
- /* vdd_1p8 */
- BUCK5 {
- regulator-name = "buck5";
- regulator-min-microvolt = <1605000>;
- regulator-max-microvolt = <1995000>;
- regulator-boot-on;
- regulator-always-on;
- };
-
- /* vdd_dram */
- BUCK6 {
- regulator-name = "buck6";
- regulator-min-microvolt = <800000>;
- regulator-max-microvolt = <1400000>;
- regulator-boot-on;
- regulator-always-on;
- };
-
- /* nvcc_snvs_1p8 */
- LDO1 {
- regulator-name = "ldo1";
- regulator-min-microvolt = <1600000>;
- regulator-max-microvolt = <1900000>;
- regulator-boot-on;
- regulator-always-on;
- };
-
- /* vdd_snvs_0p8 */
- LDO2 {
- regulator-name = "ldo2";
- regulator-min-microvolt = <800000>;
- regulator-max-microvolt = <900000>;
- regulator-boot-on;
- regulator-always-on;
- };
-
- /* vdda_1p8 */
- LDO3 {
- regulator-name = "ldo3";
- regulator-min-microvolt = <1800000>;
- regulator-max-microvolt = <3300000>;
- regulator-boot-on;
- regulator-always-on;
- };
-
- LDO4 {
- regulator-name = "ldo4";
- regulator-min-microvolt = <900000>;
- regulator-max-microvolt = <1800000>;
- regulator-boot-on;
- regulator-always-on;
- };
-
- LDO6 {
- regulator-name = "ldo6";
- regulator-min-microvolt = <900000>;
- regulator-max-microvolt = <1800000>;
- regulator-boot-on;
- regulator-always-on;
- };
- };
- };
-};
-
-&i2c3 {
- clock-frequency = <400000>;
- pinctrl-names = "default", "gpio";
- pinctrl-0 = <&pinctrl_i2c3>;
- pinctrl-1 = <&pinctrl_i2c3_gpio>;
- scl-gpios = <&gpio5 18 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
- sda-gpios = <&gpio5 19 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
- status = "okay";
-
- accelerometer@19 {
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_accel>;
- compatible = "st,lis2de12";
- reg = <0x19>;
- st,drdy-int-pin = <1>;
- interrupt-parent = <&gpio1>;
- interrupts = <15 IRQ_TYPE_LEVEL_LOW>;
- interrupt-names = "INT1";
- };
-};
-
-&pcie_phy {
- fsl,refclk-pad-mode = <IMX8_PCIE_REFCLK_PAD_INPUT>;
- fsl,clkreq-unsupported;
- clocks = <&pcie0_refclk>;
- clock-names = "ref";
- status = "okay";
-};
-
-&pcie0 {
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_pcie0>;
- reset-gpio = <&gpio5 11 GPIO_ACTIVE_LOW>;
- clocks = <&clk IMX8MM_CLK_PCIE1_ROOT>, <&clk IMX8MM_CLK_PCIE1_AUX>,
- <&pcie0_refclk>;
- clock-names = "pcie", "pcie_aux", "pcie_bus";
- assigned-clocks = <&clk IMX8MM_CLK_PCIE1_AUX>,
- <&clk IMX8MM_CLK_PCIE1_CTRL>;
- assigned-clock-rates = <10000000>, <250000000>;
- assigned-clock-parents = <&clk IMX8MM_SYS_PLL2_50M>,
- <&clk IMX8MM_SYS_PLL2_250M>;
- status = "okay";
-};
-
-&pgc_mipi {
- status = "disabled";
-};
-
-/* off-board RS232/RS485/RS422 */
-&uart1 {
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_uart1>;
- cts-gpios = <&gpio1 3 GPIO_ACTIVE_LOW>;
- rts-gpios = <&gpio1 5 GPIO_ACTIVE_LOW>;
- dtr-gpios = <&gpio1 0 GPIO_ACTIVE_LOW>;
- dsr-gpios = <&gpio1 1 GPIO_ACTIVE_LOW>;
- dcd-gpios = <&gpio3 24 GPIO_ACTIVE_LOW>;
- uart-has-rtscts;
- status = "okay";
-};
-
-/* console */
-&uart2 {
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_uart2>;
- status = "okay";
-};
-
-&usbotg1 {
- dr_mode = "host";
- disable-over-current;
- status = "okay";
-};
-
-/* microSD */
-&usdhc2 {
- pinctrl-names = "default", "state_100mhz", "state_200mhz";
- pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>;
- pinctrl-1 = <&pinctrl_usdhc2_100mhz>, <&pinctrl_usdhc2_gpio>;
- pinctrl-2 = <&pinctrl_usdhc2_200mhz>, <&pinctrl_usdhc2_gpio>;
- cd-gpios = <&gpio2 12 GPIO_ACTIVE_LOW>;
- bus-width = <4>;
- vmmc-supply = <®_3p3v>;
- status = "okay";
-};
-
-/* eMMC */
-&usdhc3 {
- pinctrl-names = "default", "state_100mhz", "state_200mhz";
- pinctrl-0 = <&pinctrl_usdhc3>;
- pinctrl-1 = <&pinctrl_usdhc3_100mhz>;
- pinctrl-2 = <&pinctrl_usdhc3_200mhz>;
- bus-width = <8>;
- non-removable;
- status = "okay";
-};
-
-&wdog1 {
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_wdog>;
- fsl,ext-reset-output;
- status = "okay";
-};
-
-&iomuxc {
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_hog>;
-
- pinctrl_hog: hoggrp {
- fsl,pins = <
- MX8MM_IOMUXC_GPIO1_IO10_GPIO1_IO10 0x40000041 /* RS422# */
- MX8MM_IOMUXC_GPIO1_IO11_GPIO1_IO11 0x40000041 /* RS485# */
- MX8MM_IOMUXC_GPIO1_IO12_GPIO1_IO12 0x40000041 /* RS232# */
- MX8MM_IOMUXC_SD1_DATA7_GPIO2_IO9 0x40000041 /* DIG1_IN */
- MX8MM_IOMUXC_SD1_DATA6_GPIO2_IO8 0x40000041 /* DIG1_OUT */
- MX8MM_IOMUXC_SD1_DATA4_GPIO2_IO6 0x40000041 /* DIG1_CTL */
- MX8MM_IOMUXC_SD1_DATA0_GPIO2_IO2 0x40000041 /* DIG2_CTL */
- MX8MM_IOMUXC_SD1_CLK_GPIO2_IO0 0x40000041 /* DIG2_IN */
- MX8MM_IOMUXC_SD1_CMD_GPIO2_IO1 0x40000041 /* DIG2_OUT */
- MX8MM_IOMUXC_ECSPI1_MOSI_GPIO5_IO7 0x40000041 /* SIM1DET# */
- MX8MM_IOMUXC_ECSPI1_MISO_GPIO5_IO8 0x40000041 /* SIM2DET# */
- MX8MM_IOMUXC_ECSPI1_SS0_GPIO5_IO9 0x40000041 /* SIM2SEL */
- MX8MM_IOMUXC_ECSPI2_MISO_GPIO5_IO12 0x40000041 /* PCI_WDIS# */
- >;
- };
-
- pinctrl_accel: accelgrp {
- fsl,pins = <
- MX8MM_IOMUXC_GPIO1_IO15_GPIO1_IO15 0x159
- >;
- };
-
- pinctrl_fec1: fec1grp {
- fsl,pins = <
- MX8MM_IOMUXC_ENET_MDC_ENET1_MDC 0x3
- MX8MM_IOMUXC_ENET_MDIO_ENET1_MDIO 0x3
- MX8MM_IOMUXC_ENET_TD3_ENET1_RGMII_TD3 0x1f
- MX8MM_IOMUXC_ENET_TD2_ENET1_RGMII_TD2 0x1f
- MX8MM_IOMUXC_ENET_TD1_ENET1_RGMII_TD1 0x1f
- MX8MM_IOMUXC_ENET_TD0_ENET1_RGMII_TD0 0x1f
- MX8MM_IOMUXC_ENET_RD3_ENET1_RGMII_RD3 0x91
- MX8MM_IOMUXC_ENET_RD2_ENET1_RGMII_RD2 0x91
- MX8MM_IOMUXC_ENET_RD1_ENET1_RGMII_RD1 0x91
- MX8MM_IOMUXC_ENET_RD0_ENET1_RGMII_RD0 0x91
- MX8MM_IOMUXC_ENET_TXC_ENET1_RGMII_TXC 0x1f
- MX8MM_IOMUXC_ENET_RXC_ENET1_RGMII_RXC 0x91
- MX8MM_IOMUXC_ENET_RX_CTL_ENET1_RGMII_RX_CTL 0x91
- MX8MM_IOMUXC_ENET_TX_CTL_ENET1_RGMII_TX_CTL 0x1f
- MX8MM_IOMUXC_SAI2_TXFS_GPIO4_IO24 0x19 /* IRQ# */
- MX8MM_IOMUXC_SAI2_TXC_GPIO4_IO25 0x19 /* RST# */
- >;
- };
-
- pinctrl_gsc: gscgrp {
- fsl,pins = <
- MX8MM_IOMUXC_SAI2_TXD0_GPIO4_IO26 0x159
- >;
- };
-
- pinctrl_i2c1: i2c1grp {
- fsl,pins = <
- MX8MM_IOMUXC_I2C1_SCL_I2C1_SCL 0x400001c3
- MX8MM_IOMUXC_I2C1_SDA_I2C1_SDA 0x400001c3
- >;
- };
-
- pinctrl_i2c1_gpio: i2c1gpiogrp {
- fsl,pins = <
- MX8MM_IOMUXC_I2C1_SCL_GPIO5_IO14 0x400001c3
- MX8MM_IOMUXC_I2C1_SDA_GPIO5_IO15 0x400001c3
- >;
- };
-
- pinctrl_i2c2: i2c2grp {
- fsl,pins = <
- MX8MM_IOMUXC_I2C2_SCL_I2C2_SCL 0x400001c3
- MX8MM_IOMUXC_I2C2_SDA_I2C2_SDA 0x400001c3
- >;
- };
-
- pinctrl_i2c2_gpio: i2c2gpiogrp {
- fsl,pins = <
- MX8MM_IOMUXC_I2C2_SCL_GPIO5_IO16 0x400001c3
- MX8MM_IOMUXC_I2C2_SDA_GPIO5_IO17 0x400001c3
- >;
- };
-
- pinctrl_i2c3: i2c3grp {
- fsl,pins = <
- MX8MM_IOMUXC_I2C3_SCL_I2C3_SCL 0x400001c3
- MX8MM_IOMUXC_I2C3_SDA_I2C3_SDA 0x400001c3
- >;
- };
-
- pinctrl_i2c3_gpio: i2c3gpiogrp {
- fsl,pins = <
- MX8MM_IOMUXC_I2C3_SCL_GPIO5_IO18 0x400001c3
- MX8MM_IOMUXC_I2C3_SDA_GPIO5_IO19 0x400001c3
- >;
- };
-
- pinctrl_gpio_leds: gpioledgrp {
- fsl,pins = <
- MX8MM_IOMUXC_SPDIF_EXT_CLK_GPIO5_IO5 0x19
- MX8MM_IOMUXC_SAI3_RXD_GPIO4_IO30 0x19
- MX8MM_IOMUXC_SAI3_MCLK_GPIO5_IO2 0x19
- MX8MM_IOMUXC_GPIO1_IO14_GPIO1_IO14 0x19
- MX8MM_IOMUXC_GPIO1_IO09_GPIO1_IO9 0x19
- MX8MM_IOMUXC_SPDIF_TX_GPIO5_IO3 0x19
- MX8MM_IOMUXC_SAI3_RXC_GPIO4_IO29 0x19
- MX8MM_IOMUXC_SAI3_RXFS_GPIO4_IO28 0x19
- MX8MM_IOMUXC_GPIO1_IO13_GPIO1_IO13 0x19
- MX8MM_IOMUXC_SAI3_TXFS_GPIO4_IO31 0x19
- MX8MM_IOMUXC_SPDIF_RX_GPIO5_IO4 0x19
- MX8MM_IOMUXC_GPIO1_IO08_GPIO1_IO8 0x19
- >;
- };
-
- pinctrl_pcie0: pciegrp {
- fsl,pins = <
- MX8MM_IOMUXC_ECSPI2_MOSI_GPIO5_IO11 0x41
- >;
- };
-
- pinctrl_pmic: pmicgrp {
- fsl,pins = <
- MX8MM_IOMUXC_NAND_DATA02_GPIO3_IO8 0x41
- >;
- };
-
- pinctrl_uart1: uart1grp {
- fsl,pins = <
- MX8MM_IOMUXC_UART1_RXD_UART1_DCE_RX 0x140
- MX8MM_IOMUXC_UART1_TXD_UART1_DCE_TX 0x140
- MX8MM_IOMUXC_GPIO1_IO00_GPIO1_IO0 0x140
- MX8MM_IOMUXC_GPIO1_IO01_GPIO1_IO1 0x140
- MX8MM_IOMUXC_GPIO1_IO03_GPIO1_IO3 0x140
- MX8MM_IOMUXC_GPIO1_IO05_GPIO1_IO5 0x140
- MX8MM_IOMUXC_SAI5_RXD3_GPIO3_IO24 0x140
- >;
- };
-
- pinctrl_uart2: uart2grp {
- fsl,pins = <
- MX8MM_IOMUXC_UART2_RXD_UART2_DCE_RX 0x140
- MX8MM_IOMUXC_UART2_TXD_UART2_DCE_TX 0x140
- >;
- };
-
- pinctrl_usdhc2: usdhc2grp {
- fsl,pins = <
- MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK 0x190
- MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d0
- MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d0
- MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d0
- MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d0
- MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d0
- >;
- };
-
- pinctrl_usdhc2_100mhz: usdhc2-100mhzgrp {
- fsl,pins = <
- MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK 0x194
- MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d4
- MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d4
- MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d4
- MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d4
- MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d4
- >;
- };
-
- pinctrl_usdhc2_200mhz: usdhc2-200mhzgrp {
- fsl,pins = <
- MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK 0x196
- MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d6
- MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d6
- MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d6
- MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d6
- MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d6
- >;
- };
-
- pinctrl_usdhc2_gpio: usdhc2-gpiogrp {
- fsl,pins = <
- MX8MM_IOMUXC_SD2_CD_B_GPIO2_IO12 0x1c4
- MX8MM_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0x1d0
- >;
- };
-
- pinctrl_usdhc3: usdhc3grp {
- fsl,pins = <
- MX8MM_IOMUXC_NAND_WE_B_USDHC3_CLK 0x190
- MX8MM_IOMUXC_NAND_WP_B_USDHC3_CMD 0x1d0
- MX8MM_IOMUXC_NAND_DATA04_USDHC3_DATA0 0x1d0
- MX8MM_IOMUXC_NAND_DATA05_USDHC3_DATA1 0x1d0
- MX8MM_IOMUXC_NAND_DATA06_USDHC3_DATA2 0x1d0
- MX8MM_IOMUXC_NAND_DATA07_USDHC3_DATA3 0x1d0
- MX8MM_IOMUXC_NAND_RE_B_USDHC3_DATA4 0x1d0
- MX8MM_IOMUXC_NAND_CE2_B_USDHC3_DATA5 0x1d0
- MX8MM_IOMUXC_NAND_CE3_B_USDHC3_DATA6 0x1d0
- MX8MM_IOMUXC_NAND_CLE_USDHC3_DATA7 0x1d0
- MX8MM_IOMUXC_NAND_CE1_B_USDHC3_STROBE 0x190
- >;
- };
-
- pinctrl_usdhc3_100mhz: usdhc3-100mhzgrp {
- fsl,pins = <
- MX8MM_IOMUXC_NAND_WE_B_USDHC3_CLK 0x194
- MX8MM_IOMUXC_NAND_WP_B_USDHC3_CMD 0x1d4
- MX8MM_IOMUXC_NAND_DATA04_USDHC3_DATA0 0x1d4
- MX8MM_IOMUXC_NAND_DATA05_USDHC3_DATA1 0x1d4
- MX8MM_IOMUXC_NAND_DATA06_USDHC3_DATA2 0x1d4
- MX8MM_IOMUXC_NAND_DATA07_USDHC3_DATA3 0x1d4
- MX8MM_IOMUXC_NAND_RE_B_USDHC3_DATA4 0x1d4
- MX8MM_IOMUXC_NAND_CE2_B_USDHC3_DATA5 0x1d4
- MX8MM_IOMUXC_NAND_CE3_B_USDHC3_DATA6 0x1d4
- MX8MM_IOMUXC_NAND_CLE_USDHC3_DATA7 0x1d4
- MX8MM_IOMUXC_NAND_CE1_B_USDHC3_STROBE 0x194
- >;
- };
-
- pinctrl_usdhc3_200mhz: usdhc3-200mhzgrp {
- fsl,pins = <
- MX8MM_IOMUXC_NAND_WE_B_USDHC3_CLK 0x196
- MX8MM_IOMUXC_NAND_WP_B_USDHC3_CMD 0x1d6
- MX8MM_IOMUXC_NAND_DATA04_USDHC3_DATA0 0x1d6
- MX8MM_IOMUXC_NAND_DATA05_USDHC3_DATA1 0x1d6
- MX8MM_IOMUXC_NAND_DATA06_USDHC3_DATA2 0x1d6
- MX8MM_IOMUXC_NAND_DATA07_USDHC3_DATA3 0x1d6
- MX8MM_IOMUXC_NAND_RE_B_USDHC3_DATA4 0x1d6
- MX8MM_IOMUXC_NAND_CE2_B_USDHC3_DATA5 0x1d6
- MX8MM_IOMUXC_NAND_CE3_B_USDHC3_DATA6 0x1d6
- MX8MM_IOMUXC_NAND_CLE_USDHC3_DATA7 0x1d6
- MX8MM_IOMUXC_NAND_CE1_B_USDHC3_STROBE 0x196
- >;
- };
-
- pinctrl_wdog: wdoggrp {
- fsl,pins = <
- MX8MM_IOMUXC_GPIO1_IO02_WDOG1_WDOG_B 0xc6
- >;
- };
-};
diff --git a/arch/arm/dts/imx8mm-venice-gw7904.dts b/arch/arm/dts/imx8mm-venice-gw7904.dts
deleted file mode 100644
index 93c9651..0000000
--- a/arch/arm/dts/imx8mm-venice-gw7904.dts
+++ /dev/null
@@ -1,928 +0,0 @@
-// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
-/*
- * Copyright 2022 Gateworks Corporation
- */
-
-/dts-v1/;
-
-#include <dt-bindings/gpio/gpio.h>
-#include <dt-bindings/input/linux-event-codes.h>
-#include <dt-bindings/leds/common.h>
-#include <dt-bindings/phy/phy-imx8-pcie.h>
-
-#include "imx8mm.dtsi"
-
-/ {
- model = "Gateworks Venice GW7904 i.MX8MM board";
- compatible = "gateworks,imx8mm-gw7904", "fsl,imx8mm";
-
- chosen {
- stdout-path = &uart2;
- };
-
- memory@40000000 {
- device_type = "memory";
- reg = <0x0 0x40000000 0 0x80000000>;
- };
-
- gpio-keys {
- compatible = "gpio-keys";
-
- key-0 {
- label = "user_pb";
- gpios = <&gpio 2 GPIO_ACTIVE_LOW>;
- linux,code = <BTN_0>;
- };
-
- key-1 {
- label = "user_pb1x";
- linux,code = <BTN_1>;
- interrupt-parent = <&gsc>;
- interrupts = <0>;
- };
-
- key-2 {
- label = "key_erased";
- linux,code = <BTN_2>;
- interrupt-parent = <&gsc>;
- interrupts = <1>;
- };
-
- key-3 {
- label = "eeprom_wp";
- linux,code = <BTN_3>;
- interrupt-parent = <&gsc>;
- interrupts = <2>;
- };
-
- key-4 {
- label = "switch_hold";
- linux,code = <BTN_5>;
- interrupt-parent = <&gsc>;
- interrupts = <7>;
- };
- };
-
- led-controller {
- compatible = "gpio-leds";
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_gpio_leds>;
-
- led-0 {
- function = LED_FUNCTION_STATUS;
- color = <LED_COLOR_ID_GREEN>;
- label = "led01_grn";
- gpios = <&gpioled 0 GPIO_ACTIVE_LOW>;
- default-state = "off";
- };
-
- led-1 {
- function = LED_FUNCTION_STATUS;
- color = <LED_COLOR_ID_YELLOW>;
- label = "led01_yel";
- gpios = <&gpioled 1 GPIO_ACTIVE_LOW>;
- default-state = "off";
- };
-
- led-2 {
- function = LED_FUNCTION_STATUS;
- color = <LED_COLOR_ID_GREEN>;
- label = "led02_grn";
- gpios = <&gpioled 2 GPIO_ACTIVE_LOW>;
- default-state = "off";
- };
-
- led-3 {
- function = LED_FUNCTION_STATUS;
- color = <LED_COLOR_ID_YELLOW>;
- label = "led02_yel";
- gpios = <&gpioled 3 GPIO_ACTIVE_LOW>;
- default-state = "off";
- };
-
- led-4 {
- function = LED_FUNCTION_STATUS;
- color = <LED_COLOR_ID_GREEN>;
- label = "led03_grn";
- gpios = <&gpioled 4 GPIO_ACTIVE_LOW>;
- default-state = "off";
- };
-
- led-5 {
- function = LED_FUNCTION_STATUS;
- color = <LED_COLOR_ID_YELLOW>;
- label = "led03_yel";
- gpios = <&gpioled 5 GPIO_ACTIVE_LOW>;
- default-state = "off";
- };
-
- led-6 {
- function = LED_FUNCTION_STATUS;
- color = <LED_COLOR_ID_GREEN>;
- label = "led04_grn";
- gpios = <&gpioled 6 GPIO_ACTIVE_LOW>;
- default-state = "off";
- };
-
- led-7 {
- function = LED_FUNCTION_STATUS;
- color = <LED_COLOR_ID_YELLOW>;
- label = "led04_yel";
- gpios = <&gpioled 7 GPIO_ACTIVE_LOW>;
- default-state = "off";
- };
-
- led-8 {
- function = LED_FUNCTION_STATUS;
- color = <LED_COLOR_ID_GREEN>;
- label = "led05_grn";
- gpios = <&gpioled 8 GPIO_ACTIVE_LOW>;
- default-state = "off";
- };
-
- led-9 {
- function = LED_FUNCTION_STATUS;
- color = <LED_COLOR_ID_YELLOW>;
- label = "led05_yel";
- gpios = <&gpioled 9 GPIO_ACTIVE_LOW>;
- default-state = "off";
- };
-
- led-10 {
- function = LED_FUNCTION_STATUS;
- color = <LED_COLOR_ID_GREEN>;
- label = "led06_grn";
- gpios = <&gpio1 8 GPIO_ACTIVE_LOW>;
- default-state = "off";
- };
-
- led-11 {
- function = LED_FUNCTION_STATUS;
- color = <LED_COLOR_ID_RED>;
- label = "led06_red";
- gpios = <&gpio1 9 GPIO_ACTIVE_LOW>;
- default-state = "off";
- };
-
- led-12 {
- function = LED_FUNCTION_STATUS;
- color = <LED_COLOR_ID_GREEN>;
- label = "led07_grn";
- gpios = <&gpio1 10 GPIO_ACTIVE_LOW>;
- default-state = "off";
- };
-
- led-13 {
- function = LED_FUNCTION_STATUS;
- color = <LED_COLOR_ID_RED>;
- label = "led07_red";
- gpios = <&gpio1 11 GPIO_ACTIVE_LOW>;
- default-state = "off";
- };
-
- led-14 {
- function = LED_FUNCTION_STATUS;
- color = <LED_COLOR_ID_GREEN>;
- label = "led08_grn";
- gpios = <&gpioled 10 GPIO_ACTIVE_LOW>;
- default-state = "off";
- };
-
- led-15 {
- function = LED_FUNCTION_STATUS;
- color = <LED_COLOR_ID_YELLOW>;
- label = "led08_yel";
- gpios = <&gpioled 11 GPIO_ACTIVE_LOW>;
- default-state = "off";
- };
-
- led-16 {
- function = LED_FUNCTION_STATUS;
- color = <LED_COLOR_ID_GREEN>;
- label = "led09_grn";
- gpios = <&gpioled 12 GPIO_ACTIVE_LOW>;
- default-state = "off";
- };
-
- led-17 {
- function = LED_FUNCTION_STATUS;
- color = <LED_COLOR_ID_YELLOW>;
- label = "led09_yel";
- gpios = <&gpioled 13 GPIO_ACTIVE_LOW>;
- default-state = "off";
- };
-
- led-18 {
- function = LED_FUNCTION_STATUS;
- color = <LED_COLOR_ID_GREEN>;
- label = "led10_grn";
- gpios = <&gpioled 14 GPIO_ACTIVE_LOW>;
- default-state = "off";
- };
-
- led-19 {
- function = LED_FUNCTION_STATUS;
- color = <LED_COLOR_ID_YELLOW>;
- label = "led10_yel";
- gpios = <&gpioled 15 GPIO_ACTIVE_LOW>;
- default-state = "off";
- };
- };
-
- pcie0_refclk: pcie0-refclk {
- compatible = "fixed-clock";
- #clock-cells = <0>;
- clock-frequency = <100000000>;
- };
-
- reg_3p3v: regulator-3p3v {
- compatible = "regulator-fixed";
- regulator-name = "3P3V";
- regulator-min-microvolt = <3300000>;
- regulator-max-microvolt = <3300000>;
- regulator-always-on;
- };
-};
-
-&A53_0 {
- cpu-supply = <&buck2>;
-};
-
-&A53_1 {
- cpu-supply = <&buck2>;
-};
-
-&A53_2 {
- cpu-supply = <&buck2>;
-};
-
-&A53_3 {
- cpu-supply = <&buck2>;
-};
-
-&ddrc {
- operating-points-v2 = <&ddrc_opp_table>;
-
- ddrc_opp_table: opp-table {
- compatible = "operating-points-v2";
-
- opp-25M {
- opp-hz = /bits/ 64 <25000000>;
- };
-
- opp-100M {
- opp-hz = /bits/ 64 <100000000>;
- };
-
- opp-750M {
- opp-hz = /bits/ 64 <750000000>;
- };
- };
-};
-
-&fec1 {
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_fec1>;
- phy-mode = "rgmii-id";
- phy-handle = <ðphy0>;
- local-mac-address = [00 00 00 00 00 00];
- status = "okay";
-
- mdio {
- #address-cells = <1>;
- #size-cells = <0>;
-
- ethphy0: ethernet-phy@0 {
- compatible = "ethernet-phy-ieee802.3-c22";
- reg = <0>;
- };
- };
-};
-
-&gpio1 {
- gpio-line-names = "", "", "", "", "", "", "", "",
- "", "", "", "", "rs232_en#", "", "", "",
- "", "", "", "", "", "", "", "",
- "", "", "", "", "", "", "", "";
-};
-
-&gpio5 {
- gpio-line-names = "", "", "", "", "", "", "", "",
- "", "", "", "", "pci_wdis#", "", "", "",
- "", "", "", "", "", "", "", "",
- "", "", "", "", "", "", "", "";
-};
-
-&i2c1 {
- clock-frequency = <100000>;
- pinctrl-names = "default", "gpio";
- pinctrl-0 = <&pinctrl_i2c1>;
- pinctrl-1 = <&pinctrl_i2c1_gpio>;
- scl-gpios = <&gpio5 14 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
- sda-gpios = <&gpio5 15 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
- status = "okay";
-
- gsc: gsc@20 {
- compatible = "gw,gsc";
- reg = <0x20>;
- pinctrl-0 = <&pinctrl_gsc>;
- interrupt-parent = <&gpio4>;
- interrupts = <26 IRQ_TYPE_EDGE_FALLING>;
- interrupt-controller;
- #interrupt-cells = <1>;
-
- adc {
- compatible = "gw,gsc-adc";
- #address-cells = <1>;
- #size-cells = <0>;
-
- channel@6 {
- gw,mode = <0>;
- reg = <0x06>;
- label = "temp";
- };
-
- channel@82 {
- gw,mode = <2>;
- reg = <0x82>;
- label = "vin";
- gw,voltage-divider-ohms = <22100 1000>;
- gw,voltage-offset-microvolt = <700000>;
- };
-
- channel@84 {
- gw,mode = <2>;
- reg = <0x84>;
- label = "vdd_5p0";
- gw,voltage-divider-ohms = <10000 10000>;
- };
-
- channel@86 {
- gw,mode = <2>;
- reg = <0x86>;
- label = "vdd_3p3";
- gw,voltage-divider-ohms = <10000 10000>;
- };
-
- channel@88 {
- gw,mode = <2>;
- reg = <0x88>;
- label = "vdd_0p9";
- };
-
- channel@8c {
- gw,mode = <2>;
- reg = <0x8c>;
- label = "vdd_soc";
- };
-
- channel@8e {
- gw,mode = <2>;
- reg = <0x8e>;
- label = "vdd_arm";
- };
-
- channel@90 {
- gw,mode = <2>;
- reg = <0x90>;
- label = "vdd_1p8";
- };
-
- channel@92 {
- gw,mode = <2>;
- reg = <0x92>;
- label = "vdd_dram";
- };
-
- channel@a2 {
- gw,mode = <2>;
- reg = <0xa2>;
- label = "vdd_gsc";
- gw,voltage-divider-ohms = <10000 10000>;
- };
- };
- };
-
- gpio: gpio@23 {
- compatible = "nxp,pca9555";
- reg = <0x23>;
- gpio-controller;
- #gpio-cells = <2>;
- interrupt-parent = <&gsc>;
- interrupts = <4>;
- };
-
- eeprom@50 {
- compatible = "atmel,24c02";
- reg = <0x50>;
- pagesize = <16>;
- };
-
- eeprom@51 {
- compatible = "atmel,24c02";
- reg = <0x51>;
- pagesize = <16>;
- };
-
- eeprom@52 {
- compatible = "atmel,24c02";
- reg = <0x52>;
- pagesize = <16>;
- };
-
- eeprom@53 {
- compatible = "atmel,24c02";
- reg = <0x53>;
- pagesize = <16>;
- };
-
- rtc@68 {
- compatible = "dallas,ds1672";
- reg = <0x68>;
- };
-};
-
-&i2c2 {
- clock-frequency = <400000>;
- pinctrl-names = "default", "gpio";
- pinctrl-0 = <&pinctrl_i2c2>;
- pinctrl-1 = <&pinctrl_i2c2_gpio>;
- scl-gpios = <&gpio5 16 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
- sda-gpios = <&gpio5 17 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
- status = "okay";
-
- pmic@4b {
- compatible = "rohm,bd71847";
- reg = <0x4b>;
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_pmic>;
- interrupt-parent = <&gpio3>;
- interrupts = <8 IRQ_TYPE_LEVEL_LOW>;
- rohm,reset-snvs-powered;
- #clock-cells = <0>;
- clocks = <&osc_32k 0>;
- clock-output-names = "clk-32k-out";
-
- regulators {
- /* vdd_soc: 0.805-0.900V (typ=0.8V) */
- BUCK1 {
- regulator-name = "buck1";
- regulator-min-microvolt = <700000>;
- regulator-max-microvolt = <1300000>;
- regulator-boot-on;
- regulator-always-on;
- regulator-ramp-delay = <1250>;
- };
-
- /* vdd_arm: 0.805-1.0V (typ=0.9V) */
- buck2: BUCK2 {
- regulator-name = "buck2";
- regulator-min-microvolt = <700000>;
- regulator-max-microvolt = <1300000>;
- regulator-boot-on;
- regulator-always-on;
- regulator-ramp-delay = <1250>;
- rohm,dvs-run-voltage = <1000000>;
- rohm,dvs-idle-voltage = <900000>;
- };
-
- /* vdd_0p9: 0.805-1.0V (typ=0.9V) */
- BUCK3 {
- regulator-name = "buck3";
- regulator-min-microvolt = <700000>;
- regulator-max-microvolt = <1350000>;
- regulator-boot-on;
- regulator-always-on;
- };
-
- /* vdd_3p3 */
- BUCK4 {
- regulator-name = "buck4";
- regulator-min-microvolt = <3000000>;
- regulator-max-microvolt = <3300000>;
- regulator-boot-on;
- regulator-always-on;
- };
-
- /* vdd_1p8 */
- BUCK5 {
- regulator-name = "buck5";
- regulator-min-microvolt = <1605000>;
- regulator-max-microvolt = <1995000>;
- regulator-boot-on;
- regulator-always-on;
- };
-
- /* vdd_dram */
- BUCK6 {
- regulator-name = "buck6";
- regulator-min-microvolt = <800000>;
- regulator-max-microvolt = <1400000>;
- regulator-boot-on;
- regulator-always-on;
- };
-
- /* nvcc_snvs_1p8 */
- LDO1 {
- regulator-name = "ldo1";
- regulator-min-microvolt = <1600000>;
- regulator-max-microvolt = <1900000>;
- regulator-boot-on;
- regulator-always-on;
- };
-
- /* vdd_snvs_0p8 */
- LDO2 {
- regulator-name = "ldo2";
- regulator-min-microvolt = <800000>;
- regulator-max-microvolt = <900000>;
- regulator-boot-on;
- regulator-always-on;
- };
-
- /* vdda_1p8 */
- LDO3 {
- regulator-name = "ldo3";
- regulator-min-microvolt = <1800000>;
- regulator-max-microvolt = <3300000>;
- regulator-boot-on;
- regulator-always-on;
- };
-
- LDO4 {
- regulator-name = "ldo4";
- regulator-min-microvolt = <900000>;
- regulator-max-microvolt = <1800000>;
- regulator-boot-on;
- regulator-always-on;
- };
-
- LDO6 {
- regulator-name = "ldo6";
- regulator-min-microvolt = <900000>;
- regulator-max-microvolt = <1800000>;
- regulator-boot-on;
- regulator-always-on;
- };
- };
- };
-};
-
-&i2c3 {
- clock-frequency = <400000>;
- pinctrl-names = "default", "gpio";
- pinctrl-0 = <&pinctrl_i2c3>;
- pinctrl-1 = <&pinctrl_i2c3_gpio>;
- scl-gpios = <&gpio5 18 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
- sda-gpios = <&gpio5 19 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
- status = "okay";
-
- accelerometer@19 {
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_accel>;
- compatible = "st,lis2de12";
- reg = <0x19>;
- st,drdy-int-pin = <1>;
- interrupt-parent = <&gpio1>;
- interrupts = <15 IRQ_TYPE_LEVEL_LOW>;
- interrupt-names = "INT1";
- };
-};
-
-&i2c4 {
- clock-frequency = <400000>;
- pinctrl-names = "default", "gpio";
- pinctrl-0 = <&pinctrl_i2c4>;
- pinctrl-1 = <&pinctrl_i2c4_gpio>;
- scl-gpios = <&gpio5 20 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
- sda-gpios = <&gpio5 21 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
- status = "okay";
-
- gpioled: gpio@27 {
- compatible = "nxp,pca9555";
- reg = <0x27>;
- gpio-controller;
- #gpio-cells = <2>;
- };
-};
-
-&pcie_phy {
- fsl,refclk-pad-mode = <IMX8_PCIE_REFCLK_PAD_INPUT>;
- fsl,clkreq-unsupported;
- clocks = <&pcie0_refclk>;
- clock-names = "ref";
- status = "okay";
-};
-
-&pcie0 {
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_pcie0>;
- reset-gpio = <&gpio5 11 GPIO_ACTIVE_LOW>;
- clocks = <&clk IMX8MM_CLK_PCIE1_ROOT>, <&clk IMX8MM_CLK_PCIE1_AUX>,
- <&pcie0_refclk>;
- clock-names = "pcie", "pcie_aux", "pcie_bus";
- assigned-clocks = <&clk IMX8MM_CLK_PCIE1_AUX>,
- <&clk IMX8MM_CLK_PCIE1_CTRL>;
- assigned-clock-rates = <10000000>, <250000000>;
- assigned-clock-parents = <&clk IMX8MM_SYS_PLL2_50M>,
- <&clk IMX8MM_SYS_PLL2_250M>;
- status = "okay";
-};
-
-&pgc_mipi {
- status = "disabled";
-};
-
-/* off-board RS232 */
-&uart1 {
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_uart1>;
- status = "okay";
-};
-
-/* console */
-&uart2 {
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_uart2>;
- status = "okay";
-};
-
-/* off-board RS232 */
-&uart3 {
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_uart3>;
- status = "okay";
-};
-
-&usbotg1 {
- dr_mode = "host";
- disable-over-current;
- status = "okay";
-};
-
-/* microSD */
-&usdhc2 {
- pinctrl-names = "default", "state_100mhz", "state_200mhz";
- pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>;
- pinctrl-1 = <&pinctrl_usdhc2_100mhz>, <&pinctrl_usdhc2_gpio>;
- pinctrl-2 = <&pinctrl_usdhc2_200mhz>, <&pinctrl_usdhc2_gpio>;
- cd-gpios = <&gpio2 12 GPIO_ACTIVE_LOW>;
- bus-width = <4>;
- vmmc-supply = <®_3p3v>;
- status = "okay";
-};
-
-/* eMMC */
-&usdhc3 {
- pinctrl-names = "default", "state_100mhz", "state_200mhz";
- pinctrl-0 = <&pinctrl_usdhc3>;
- pinctrl-1 = <&pinctrl_usdhc3_100mhz>;
- pinctrl-2 = <&pinctrl_usdhc3_200mhz>;
- bus-width = <8>;
- non-removable;
- status = "okay";
-};
-
-&wdog1 {
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_wdog>;
- fsl,ext-reset-output;
- status = "okay";
-};
-
-&iomuxc {
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_hog>;
-
- pinctrl_hog: hoggrp {
- fsl,pins = <
- MX8MM_IOMUXC_GPIO1_IO12_GPIO1_IO12 0x40000041 /* RS232# */
- MX8MM_IOMUXC_ECSPI2_MISO_GPIO5_IO12 0x40000041 /* PCI_WDIS# */
- >;
- };
-
- pinctrl_accel: accelgrp {
- fsl,pins = <
- MX8MM_IOMUXC_GPIO1_IO15_GPIO1_IO15 0x159
- >;
- };
-
- pinctrl_fec1: fec1grp {
- fsl,pins = <
- MX8MM_IOMUXC_ENET_MDC_ENET1_MDC 0x3
- MX8MM_IOMUXC_ENET_MDIO_ENET1_MDIO 0x3
- MX8MM_IOMUXC_ENET_TD3_ENET1_RGMII_TD3 0x1f
- MX8MM_IOMUXC_ENET_TD2_ENET1_RGMII_TD2 0x1f
- MX8MM_IOMUXC_ENET_TD1_ENET1_RGMII_TD1 0x1f
- MX8MM_IOMUXC_ENET_TD0_ENET1_RGMII_TD0 0x1f
- MX8MM_IOMUXC_ENET_RD3_ENET1_RGMII_RD3 0x91
- MX8MM_IOMUXC_ENET_RD2_ENET1_RGMII_RD2 0x91
- MX8MM_IOMUXC_ENET_RD1_ENET1_RGMII_RD1 0x91
- MX8MM_IOMUXC_ENET_RD0_ENET1_RGMII_RD0 0x91
- MX8MM_IOMUXC_ENET_TXC_ENET1_RGMII_TXC 0x1f
- MX8MM_IOMUXC_ENET_RXC_ENET1_RGMII_RXC 0x91
- MX8MM_IOMUXC_ENET_RX_CTL_ENET1_RGMII_RX_CTL 0x91
- MX8MM_IOMUXC_ENET_TX_CTL_ENET1_RGMII_TX_CTL 0x1f
- MX8MM_IOMUXC_SAI2_TXFS_GPIO4_IO24 0x19 /* IRQ# */
- MX8MM_IOMUXC_SAI2_TXC_GPIO4_IO25 0x19 /* RST# */
- >;
- };
-
- pinctrl_gpio_leds: gpioledsgrp {
- fsl,pins = <
- MX8MM_IOMUXC_GPIO1_IO08_GPIO1_IO8 0x40000019
- MX8MM_IOMUXC_GPIO1_IO09_GPIO1_IO9 0x40000019
- MX8MM_IOMUXC_GPIO1_IO10_GPIO1_IO10 0x40000019
- MX8MM_IOMUXC_GPIO1_IO11_GPIO1_IO11 0x40000019
- >;
- };
-
- pinctrl_gsc: gscgrp {
- fsl,pins = <
- MX8MM_IOMUXC_SAI2_TXD0_GPIO4_IO26 0x159
- >;
- };
-
- pinctrl_i2c1: i2c1grp {
- fsl,pins = <
- MX8MM_IOMUXC_I2C1_SCL_I2C1_SCL 0x400001c3
- MX8MM_IOMUXC_I2C1_SDA_I2C1_SDA 0x400001c3
- >;
- };
-
- pinctrl_i2c1_gpio: i2c1gpiogrp {
- fsl,pins = <
- MX8MM_IOMUXC_I2C1_SCL_GPIO5_IO14 0x400001c3
- MX8MM_IOMUXC_I2C1_SDA_GPIO5_IO15 0x400001c3
- >;
- };
-
- pinctrl_i2c2: i2c2grp {
- fsl,pins = <
- MX8MM_IOMUXC_I2C2_SCL_I2C2_SCL 0x400001c3
- MX8MM_IOMUXC_I2C2_SDA_I2C2_SDA 0x400001c3
- >;
- };
-
- pinctrl_i2c2_gpio: i2c2gpiogrp {
- fsl,pins = <
- MX8MM_IOMUXC_I2C2_SCL_GPIO5_IO16 0x400001c3
- MX8MM_IOMUXC_I2C2_SDA_GPIO5_IO17 0x400001c3
- >;
- };
-
- pinctrl_i2c3: i2c3grp {
- fsl,pins = <
- MX8MM_IOMUXC_I2C3_SCL_I2C3_SCL 0x400001c3
- MX8MM_IOMUXC_I2C3_SDA_I2C3_SDA 0x400001c3
- >;
- };
-
- pinctrl_i2c3_gpio: i2c3gpiogrp {
- fsl,pins = <
- MX8MM_IOMUXC_I2C3_SCL_GPIO5_IO18 0x400001c3
- MX8MM_IOMUXC_I2C3_SDA_GPIO5_IO19 0x400001c3
- >;
- };
-
- pinctrl_i2c4: i2c4grp {
- fsl,pins = <
- MX8MM_IOMUXC_I2C4_SCL_I2C4_SCL 0x400001c3
- MX8MM_IOMUXC_I2C4_SDA_I2C4_SDA 0x400001c3
- >;
- };
-
- pinctrl_i2c4_gpio: i2c4gpiogrp {
- fsl,pins = <
- MX8MM_IOMUXC_I2C4_SCL_GPIO5_IO20 0x400001c3
- MX8MM_IOMUXC_I2C4_SDA_GPIO5_IO21 0x400001c3
- >;
- };
-
- pinctrl_pcie0: pciegrp {
- fsl,pins = <
- MX8MM_IOMUXC_ECSPI2_MOSI_GPIO5_IO11 0x41
- >;
- };
-
- pinctrl_pmic: pmicgrp {
- fsl,pins = <
- MX8MM_IOMUXC_NAND_DATA02_GPIO3_IO8 0x41
- >;
- };
-
- pinctrl_uart1: uart1grp {
- fsl,pins = <
- MX8MM_IOMUXC_UART1_RXD_UART1_DCE_RX 0x140
- MX8MM_IOMUXC_UART1_TXD_UART1_DCE_TX 0x140
- >;
- };
-
- pinctrl_uart2: uart2grp {
- fsl,pins = <
- MX8MM_IOMUXC_UART2_RXD_UART2_DCE_RX 0x140
- MX8MM_IOMUXC_UART2_TXD_UART2_DCE_TX 0x140
- >;
- };
-
- pinctrl_uart3: uart3grp {
- fsl,pins = <
- MX8MM_IOMUXC_UART3_RXD_UART3_DCE_RX 0x140
- MX8MM_IOMUXC_UART3_TXD_UART3_DCE_TX 0x140
- >;
- };
-
- pinctrl_usdhc2: usdhc2grp {
- fsl,pins = <
- MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK 0x190
- MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d0
- MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d0
- MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d0
- MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d0
- MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d0
- >;
- };
-
- pinctrl_usdhc2_100mhz: usdhc2-100mhzgrp {
- fsl,pins = <
- MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK 0x194
- MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d4
- MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d4
- MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d4
- MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d4
- MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d4
- >;
- };
-
- pinctrl_usdhc2_200mhz: usdhc2-200mhzgrp {
- fsl,pins = <
- MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK 0x196
- MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d6
- MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d6
- MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d6
- MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d6
- MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d6
- >;
- };
-
- pinctrl_usdhc2_gpio: usdhc2-gpiogrp {
- fsl,pins = <
- MX8MM_IOMUXC_SD2_CD_B_GPIO2_IO12 0x1c4
- MX8MM_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0x1d0
- >;
- };
-
- pinctrl_usdhc3: usdhc3grp {
- fsl,pins = <
- MX8MM_IOMUXC_NAND_WE_B_USDHC3_CLK 0x190
- MX8MM_IOMUXC_NAND_WP_B_USDHC3_CMD 0x1d0
- MX8MM_IOMUXC_NAND_DATA04_USDHC3_DATA0 0x1d0
- MX8MM_IOMUXC_NAND_DATA05_USDHC3_DATA1 0x1d0
- MX8MM_IOMUXC_NAND_DATA06_USDHC3_DATA2 0x1d0
- MX8MM_IOMUXC_NAND_DATA07_USDHC3_DATA3 0x1d0
- MX8MM_IOMUXC_NAND_RE_B_USDHC3_DATA4 0x1d0
- MX8MM_IOMUXC_NAND_CE2_B_USDHC3_DATA5 0x1d0
- MX8MM_IOMUXC_NAND_CE3_B_USDHC3_DATA6 0x1d0
- MX8MM_IOMUXC_NAND_CLE_USDHC3_DATA7 0x1d0
- MX8MM_IOMUXC_NAND_CE1_B_USDHC3_STROBE 0x190
- >;
- };
-
- pinctrl_usdhc3_100mhz: usdhc3-100mhzgrp {
- fsl,pins = <
- MX8MM_IOMUXC_NAND_WE_B_USDHC3_CLK 0x194
- MX8MM_IOMUXC_NAND_WP_B_USDHC3_CMD 0x1d4
- MX8MM_IOMUXC_NAND_DATA04_USDHC3_DATA0 0x1d4
- MX8MM_IOMUXC_NAND_DATA05_USDHC3_DATA1 0x1d4
- MX8MM_IOMUXC_NAND_DATA06_USDHC3_DATA2 0x1d4
- MX8MM_IOMUXC_NAND_DATA07_USDHC3_DATA3 0x1d4
- MX8MM_IOMUXC_NAND_RE_B_USDHC3_DATA4 0x1d4
- MX8MM_IOMUXC_NAND_CE2_B_USDHC3_DATA5 0x1d4
- MX8MM_IOMUXC_NAND_CE3_B_USDHC3_DATA6 0x1d4
- MX8MM_IOMUXC_NAND_CLE_USDHC3_DATA7 0x1d4
- MX8MM_IOMUXC_NAND_CE1_B_USDHC3_STROBE 0x194
- >;
- };
-
- pinctrl_usdhc3_200mhz: usdhc3-200mhzgrp {
- fsl,pins = <
- MX8MM_IOMUXC_NAND_WE_B_USDHC3_CLK 0x196
- MX8MM_IOMUXC_NAND_WP_B_USDHC3_CMD 0x1d6
- MX8MM_IOMUXC_NAND_DATA04_USDHC3_DATA0 0x1d6
- MX8MM_IOMUXC_NAND_DATA05_USDHC3_DATA1 0x1d6
- MX8MM_IOMUXC_NAND_DATA06_USDHC3_DATA2 0x1d6
- MX8MM_IOMUXC_NAND_DATA07_USDHC3_DATA3 0x1d6
- MX8MM_IOMUXC_NAND_RE_B_USDHC3_DATA4 0x1d6
- MX8MM_IOMUXC_NAND_CE2_B_USDHC3_DATA5 0x1d6
- MX8MM_IOMUXC_NAND_CE3_B_USDHC3_DATA6 0x1d6
- MX8MM_IOMUXC_NAND_CLE_USDHC3_DATA7 0x1d6
- MX8MM_IOMUXC_NAND_CE1_B_USDHC3_STROBE 0x196
- >;
- };
-
- pinctrl_wdog: wdoggrp {
- fsl,pins = <
- MX8MM_IOMUXC_GPIO1_IO02_WDOG1_WDOG_B 0xc6
- >;
- };
-};
diff --git a/arch/arm/dts/imx8mm-venice-gw7905-0x.dts b/arch/arm/dts/imx8mm-venice-gw7905-0x.dts
deleted file mode 100644
index 914753f..0000000
--- a/arch/arm/dts/imx8mm-venice-gw7905-0x.dts
+++ /dev/null
@@ -1,28 +0,0 @@
-// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
-/*
- * Copyright 2023 Gateworks Corporation
- */
-
-/dts-v1/;
-
-#include "imx8mm.dtsi"
-#include "imx8mm-venice-gw700x.dtsi"
-#include "imx8mm-venice-gw7905.dtsi"
-
-/ {
- model = "Gateworks Venice GW7905-0x i.MX8MM Development Kit";
- compatible = "gateworks,imx8mm-gw7905-0x", "fsl,imx8mm";
-
- chosen {
- stdout-path = &uart2;
- };
-};
-
-/* Disable SOM interfaces not used on baseboard */
-&fec1 {
- status = "disabled";
-};
-
-&usdhc1 {
- status = "disabled";
-};
diff --git a/arch/arm/dts/imx8mm-venice-gw7905.dtsi b/arch/arm/dts/imx8mm-venice-gw7905.dtsi
deleted file mode 100644
index 9646eb9..0000000
--- a/arch/arm/dts/imx8mm-venice-gw7905.dtsi
+++ /dev/null
@@ -1,303 +0,0 @@
-// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
-/*
- * Copyright 2023 Gateworks Corporation
- */
-
-#include <dt-bindings/gpio/gpio.h>
-#include <dt-bindings/leds/common.h>
-#include <dt-bindings/phy/phy-imx8-pcie.h>
-
-/ {
- led-controller {
- compatible = "gpio-leds";
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_gpio_leds>;
-
- led-0 {
- function = LED_FUNCTION_STATUS;
- color = <LED_COLOR_ID_GREEN>;
- gpios = <&gpio4 0 GPIO_ACTIVE_HIGH>;
- default-state = "on";
- linux,default-trigger = "heartbeat";
- };
-
- led-1 {
- function = LED_FUNCTION_STATUS;
- color = <LED_COLOR_ID_RED>;
- gpios = <&gpio4 2 GPIO_ACTIVE_HIGH>;
- default-state = "off";
- };
- };
-
- pcie0_refclk: pcie0-refclk {
- compatible = "fixed-clock";
- #clock-cells = <0>;
- clock-frequency = <100000000>;
- };
-
- pps {
- compatible = "pps-gpio";
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_pps>;
- gpios = <&gpio4 5 GPIO_ACTIVE_HIGH>;
- status = "okay";
- };
-
- reg_usb2_vbus: regulator-usb2-vbus {
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_reg_usb2_en>;
- compatible = "regulator-fixed";
- regulator-name = "usb2_vbus";
- gpio = <&gpio1 8 GPIO_ACTIVE_HIGH>;
- enable-active-high;
- regulator-min-microvolt = <5000000>;
- regulator-max-microvolt = <5000000>;
- };
-
- reg_usdhc2_vmmc: regulator-usdhc2 {
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_reg_usdhc2_vmmc>;
- compatible = "regulator-fixed";
- regulator-name = "SD2_3P3V";
- regulator-min-microvolt = <3300000>;
- regulator-max-microvolt = <3300000>;
- gpio = <&gpio2 19 GPIO_ACTIVE_HIGH>;
- enable-active-high;
- };
-};
-
-/* off-board header */
-&ecspi2 {
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_spi2>;
- cs-gpios = <&gpio5 13 GPIO_ACTIVE_LOW>;
- status = "okay";
-};
-
-&gpio1 {
- gpio-line-names =
- "", "", "", "",
- "", "", "", "",
- "", "", "", "",
- "", "gpioa", "gpiob", "",
- "", "", "", "",
- "", "", "", "",
- "", "", "", "",
- "", "", "", "";
-};
-
-&gpio4 {
- gpio-line-names =
- "", "", "", "pci_usb_sel",
- "", "", "", "pci_wdis#",
- "", "", "", "",
- "", "", "", "",
- "", "", "", "",
- "", "", "", "",
- "", "", "", "",
- "", "", "", "";
-};
-
-&gpio5 {
- gpio-line-names =
- "", "", "", "",
- "gpioc", "gpiod", "", "",
- "", "", "", "",
- "", "", "", "",
- "", "", "", "",
- "", "", "", "",
- "", "", "", "",
- "", "", "", "";
-};
-
-&i2c2 {
- clock-frequency = <400000>;
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_i2c2>;
- status = "okay";
-
- eeprom@52 {
- compatible = "atmel,24c32";
- reg = <0x52>;
- pagesize = <32>;
- };
-};
-
-/* off-board header */
-&i2c3 {
- clock-frequency = <400000>;
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_i2c3>;
- status = "okay";
-};
-
-&pcie_phy {
- fsl,refclk-pad-mode = <IMX8_PCIE_REFCLK_PAD_INPUT>;
- fsl,clkreq-unsupported;
- clocks = <&pcie0_refclk>;
- clock-names = "ref";
- status = "okay";
-};
-
-&pcie0 {
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_pcie0>;
- reset-gpio = <&gpio4 6 GPIO_ACTIVE_LOW>;
- status = "okay";
-};
-
-/* GPS */
-&uart1 {
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_uart1>;
- status = "okay";
-};
-
-/* USB1 - Type C front panel SINK port J14 */
-&usbotg1 {
- dr_mode = "peripheral";
- status = "okay";
-};
-
-/* USB2 4-port USB3.0 HUB:
- * P1 - USBC connector (host only)
- * P2 - USB2 test connector
- * P3 - miniPCIe full card
- * P4 - miniPCIe half card
- */
-&usbotg2 {
- dr_mode = "host";
- vbus-supply = <®_usb2_vbus>;
- status = "okay";
-};
-
-/* microSD */
-&usdhc2 {
- pinctrl-names = "default", "state_100mhz", "state_200mhz";
- pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>;
- pinctrl-1 = <&pinctrl_usdhc2_100mhz>, <&pinctrl_usdhc2_gpio>;
- pinctrl-2 = <&pinctrl_usdhc2_200mhz>, <&pinctrl_usdhc2_gpio>;
- cd-gpios = <&gpio2 12 GPIO_ACTIVE_LOW>;
- vmmc-supply = <®_usdhc2_vmmc>;
- bus-width = <4>;
- status = "okay";
-};
-
-&iomuxc {
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_hog>;
-
- pinctrl_hog: hoggrp {
- fsl,pins = <
- MX8MM_IOMUXC_GPIO1_IO13_GPIO1_IO13 0x40000040 /* GPIOA */
- MX8MM_IOMUXC_GPIO1_IO14_GPIO1_IO14 0x40000040 /* GPIOB */
- MX8MM_IOMUXC_SAI1_RXD1_GPIO4_IO3 0x40000106 /* PCI_USBSEL */
- MX8MM_IOMUXC_SAI1_RXD5_GPIO4_IO7 0x40000106 /* PCIE_WDIS# */
- MX8MM_IOMUXC_SPDIF_EXT_CLK_GPIO5_IO5 0x40000040 /* GPIOD */
- MX8MM_IOMUXC_SPDIF_RX_GPIO5_IO4 0x40000040 /* GPIOC */
- >;
- };
-
- pinctrl_gpio_leds: gpioledgrp {
- fsl,pins = <
- MX8MM_IOMUXC_SAI1_RXFS_GPIO4_IO0 0x6 /* LEDG */
- MX8MM_IOMUXC_SAI1_RXD0_GPIO4_IO2 0x6 /* LEDR */
- >;
- };
-
- pinctrl_i2c2: i2c2grp {
- fsl,pins = <
- MX8MM_IOMUXC_I2C2_SCL_I2C2_SCL 0x400001c2
- MX8MM_IOMUXC_I2C2_SDA_I2C2_SDA 0x400001c2
- >;
- };
-
- pinctrl_i2c3: i2c3grp {
- fsl,pins = <
- MX8MM_IOMUXC_I2C3_SCL_I2C3_SCL 0x400001c2
- MX8MM_IOMUXC_I2C3_SDA_I2C3_SDA 0x400001c2
- >;
- };
-
- pinctrl_pcie0: pciegrp {
- fsl,pins = <
- MX8MM_IOMUXC_SAI1_RXD4_GPIO4_IO6 0x106
- >;
- };
-
- pinctrl_pps: ppsgrp {
- fsl,pins = <
- MX8MM_IOMUXC_SAI1_RXD3_GPIO4_IO5 0x106
- >;
- };
-
- pinctrl_reg_usb2_en: regusb2grp {
- fsl,pins = <
- MX8MM_IOMUXC_GPIO1_IO08_GPIO1_IO8 0x6 /* USBHUB_RST# (ext p/u) */
- >;
- };
-
- pinctrl_reg_usdhc2_vmmc: regusdhc2vmmcgrp {
- fsl,pins = <
- MX8MM_IOMUXC_SD2_RESET_B_GPIO2_IO19 0x40
- >;
- };
-
- pinctrl_spi2: spi2grp {
- fsl,pins = <
- MX8MM_IOMUXC_ECSPI2_SCLK_ECSPI2_SCLK 0x140
- MX8MM_IOMUXC_ECSPI2_MOSI_ECSPI2_MOSI 0x140
- MX8MM_IOMUXC_ECSPI2_MISO_ECSPI2_MISO 0x140
- MX8MM_IOMUXC_ECSPI2_SS0_GPIO5_IO13 0x140
- >;
- };
-
- pinctrl_uart1: uart1grp {
- fsl,pins = <
- MX8MM_IOMUXC_UART1_RXD_UART1_DCE_RX 0x140
- MX8MM_IOMUXC_UART1_TXD_UART1_DCE_TX 0x140
- >;
- };
-
- pinctrl_usdhc2: usdhc2grp {
- fsl,pins = <
- MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK 0x190
- MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d0
- MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d0
- MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d0
- MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d0
- MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d0
- MX8MM_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0xc0
- >;
- };
-
- pinctrl_usdhc2_100mhz: usdhc2-100mhzgrp {
- fsl,pins = <
- MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK 0x194
- MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d4
- MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d4
- MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d4
- MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d4
- MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d4
- MX8MM_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0xc0
- >;
- };
-
- pinctrl_usdhc2_200mhz: usdhc2-200mhzgrp {
- fsl,pins = <
- MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK 0x196
- MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d6
- MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d6
- MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d6
- MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d6
- MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d6
- MX8MM_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0xc0
- >;
- };
-
- pinctrl_usdhc2_gpio: usdhc2gpiogrp {
- fsl,pins = <
- MX8MM_IOMUXC_SD2_CD_B_GPIO2_IO12 0x1c4
- >;
- };
-};
diff --git a/arch/arm/dts/imx8mm-venice.dts b/arch/arm/dts/imx8mm-venice.dts
deleted file mode 100644
index d092990..0000000
--- a/arch/arm/dts/imx8mm-venice.dts
+++ /dev/null
@@ -1,169 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * Copyright 2021 Gateworks Corporation
- */
-
-/dts-v1/;
-
-#include "imx8mm.dtsi"
-
-/ {
- model = "Gateworks Venice i.MX8MM board";
- compatible = "gw,imx8mm-venice", "fsl,imx8mm";
-
- chosen {
- stdout-path = &uart2;
- };
-
- memory@40000000 {
- device_type = "memory";
- reg = <0x0 0x40000000 0 0x80000000>;
- };
-};
-
-&i2c1 {
- clock-frequency = <100000>;
- pinctrl-names = "default", "gpio";
- pinctrl-0 = <&pinctrl_i2c1>;
- pinctrl-1 = <&pinctrl_i2c1_gpio>;
- scl-gpios = <&gpio5 14 GPIO_ACTIVE_HIGH>;
- sda-gpios = <&gpio5 15 GPIO_ACTIVE_HIGH>;
- status = "okay";
-
- gsc: gsc@20 {
- compatible = "gw,gsc";
- reg = <0x20>;
- #address-cells = <1>;
- #size-cells = <0>;
- };
-
- eeprom@51 {
- compatible = "atmel,24c02";
- reg = <0x51>;
- pagesize = <16>;
- };
-};
-
-&i2c2 {
- clock-frequency = <400000>;
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_i2c2>;
- status = "okay";
-
- eeprom@52 {
- compatible = "atmel,24c32";
- reg = <0x52>;
- pagesize = <32>;
- };
-};
-
-/* console */
-&uart2 {
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_uart2>;
- status = "okay";
-};
-
-/* eMMC */
-&usdhc3 {
- assigned-clocks = <&clk IMX8MM_CLK_USDHC3_ROOT>;
- assigned-clock-rates = <400000000>;
- pinctrl-names = "default", "state_100mhz", "state_200mhz";
- pinctrl-0 = <&pinctrl_usdhc3>;
- pinctrl-1 = <&pinctrl_usdhc3_100mhz>;
- pinctrl-2 = <&pinctrl_usdhc3_200mhz>;
- bus-width = <8>;
- non-removable;
- status = "okay";
-};
-
-&wdog1 {
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_wdog>;
- fsl,ext-reset-output;
- status = "okay";
-};
-
-&iomuxc {
- pinctrl_i2c1: i2c1grp {
- fsl,pins = <
- MX8MM_IOMUXC_I2C1_SCL_I2C1_SCL 0x400001c3
- MX8MM_IOMUXC_I2C1_SDA_I2C1_SDA 0x400001c3
- >;
- };
-
- pinctrl_i2c1_gpio: i2c1grp-gpio-grp {
- fsl,pins = <
- MX8MM_IOMUXC_I2C1_SCL_GPIO5_IO14 0x400001c3
- MX8MM_IOMUXC_I2C1_SDA_GPIO5_IO15 0x400001c3
- >;
- };
-
- pinctrl_i2c2: i2c2grp {
- fsl,pins = <
- MX8MM_IOMUXC_I2C2_SCL_I2C2_SCL 0x400001c3
- MX8MM_IOMUXC_I2C2_SDA_I2C2_SDA 0x400001c3
- >;
- };
-
- pinctrl_uart2: uart2grp {
- fsl,pins = <
- MX8MM_IOMUXC_UART2_RXD_UART2_DCE_RX 0x140
- MX8MM_IOMUXC_UART2_TXD_UART2_DCE_TX 0x140
- >;
- };
-
- pinctrl_usdhc3: usdhc3grp {
- fsl,pins = <
- MX8MM_IOMUXC_NAND_WE_B_USDHC3_CLK 0x190
- MX8MM_IOMUXC_NAND_WP_B_USDHC3_CMD 0x1d0
- MX8MM_IOMUXC_NAND_DATA04_USDHC3_DATA0 0x1d0
- MX8MM_IOMUXC_NAND_DATA05_USDHC3_DATA1 0x1d0
- MX8MM_IOMUXC_NAND_DATA06_USDHC3_DATA2 0x1d0
- MX8MM_IOMUXC_NAND_DATA07_USDHC3_DATA3 0x1d0
- MX8MM_IOMUXC_NAND_RE_B_USDHC3_DATA4 0x1d0
- MX8MM_IOMUXC_NAND_CE2_B_USDHC3_DATA5 0x1d0
- MX8MM_IOMUXC_NAND_CE3_B_USDHC3_DATA6 0x1d0
- MX8MM_IOMUXC_NAND_CLE_USDHC3_DATA7 0x1d0
- MX8MM_IOMUXC_NAND_CE1_B_USDHC3_STROBE 0x190
- >;
- };
-
- pinctrl_usdhc3_100mhz: usdhc3grp100mhz {
- fsl,pins = <
- MX8MM_IOMUXC_NAND_WE_B_USDHC3_CLK 0x194
- MX8MM_IOMUXC_NAND_WP_B_USDHC3_CMD 0x1d4
- MX8MM_IOMUXC_NAND_DATA04_USDHC3_DATA0 0x1d4
- MX8MM_IOMUXC_NAND_DATA05_USDHC3_DATA1 0x1d4
- MX8MM_IOMUXC_NAND_DATA06_USDHC3_DATA2 0x1d4
- MX8MM_IOMUXC_NAND_DATA07_USDHC3_DATA3 0x1d4
- MX8MM_IOMUXC_NAND_RE_B_USDHC3_DATA4 0x1d4
- MX8MM_IOMUXC_NAND_CE2_B_USDHC3_DATA5 0x1d4
- MX8MM_IOMUXC_NAND_CE3_B_USDHC3_DATA6 0x1d4
- MX8MM_IOMUXC_NAND_CLE_USDHC3_DATA7 0x1d4
- MX8MM_IOMUXC_NAND_CE1_B_USDHC3_STROBE 0x194
- >;
- };
-
- pinctrl_usdhc3_200mhz: usdhc3grp200mhz {
- fsl,pins = <
- MX8MM_IOMUXC_NAND_WE_B_USDHC3_CLK 0x196
- MX8MM_IOMUXC_NAND_WP_B_USDHC3_CMD 0x1d6
- MX8MM_IOMUXC_NAND_DATA04_USDHC3_DATA0 0x1d6
- MX8MM_IOMUXC_NAND_DATA05_USDHC3_DATA1 0x1d6
- MX8MM_IOMUXC_NAND_DATA06_USDHC3_DATA2 0x1d6
- MX8MM_IOMUXC_NAND_DATA07_USDHC3_DATA3 0x1d6
- MX8MM_IOMUXC_NAND_RE_B_USDHC3_DATA4 0x1d6
- MX8MM_IOMUXC_NAND_CE2_B_USDHC3_DATA5 0x1d6
- MX8MM_IOMUXC_NAND_CE3_B_USDHC3_DATA6 0x1d6
- MX8MM_IOMUXC_NAND_CLE_USDHC3_DATA7 0x1d6
- MX8MM_IOMUXC_NAND_CE1_B_USDHC3_STROBE 0x196
- >;
- };
-
- pinctrl_wdog: wdoggrp {
- fsl,pins = <
- MX8MM_IOMUXC_GPIO1_IO02_WDOG1_WDOG_B 0xc6
- >;
- };
-};
diff --git a/arch/arm/dts/imx8mm-verdin-dev.dtsi b/arch/arm/dts/imx8mm-verdin-dev.dtsi
deleted file mode 100644
index 3c4b8ca..0000000
--- a/arch/arm/dts/imx8mm-verdin-dev.dtsi
+++ /dev/null
@@ -1,160 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
-/*
- * Copyright 2022 Toradex
- */
-
-/ {
- sound_card: sound-card {
- compatible = "simple-audio-card";
- simple-audio-card,bitclock-master = <&dailink_master>;
- simple-audio-card,format = "i2s";
- simple-audio-card,frame-master = <&dailink_master>;
- simple-audio-card,mclk-fs = <256>;
- simple-audio-card,name = "imx8mm-nau8822";
- simple-audio-card,routing =
- "Headphones", "LHP",
- "Headphones", "RHP",
- "Speaker", "LSPK",
- "Speaker", "RSPK",
- "Line Out", "AUXOUT1",
- "Line Out", "AUXOUT2",
- "LAUX", "Line In",
- "RAUX", "Line In",
- "LMICP", "Mic In",
- "RMICP", "Mic In";
- simple-audio-card,widgets =
- "Headphones", "Headphones",
- "Line Out", "Line Out",
- "Speaker", "Speaker",
- "Microphone", "Mic In",
- "Line", "Line In";
-
- dailink_master: simple-audio-card,codec {
- clocks = <&clk IMX8MM_CLK_SAI2_ROOT>;
- sound-dai = <&nau8822_1a>;
- };
-
- simple-audio-card,cpu {
- sound-dai = <&sai2>;
- };
- };
-};
-
-/* Verdin SPI_1 */
-&ecspi2 {
- status = "okay";
-};
-
-/* EEPROM on display adapter boards */
-&eeprom_display_adapter {
- status = "okay";
-};
-
-/* EEPROM on Verdin Development board */
-&eeprom_carrier_board {
- status = "okay";
-};
-
-&fec1 {
- status = "okay";
-};
-
-/* Verdin QSPI_1 */
-&flexspi {
- status = "okay";
-};
-
-/* Current measurement into module VCC */
-&hwmon {
- status = "okay";
-};
-
-&hwmon_temp {
- vs-supply = <®_1p8v>;
- status = "okay";
-};
-
-&i2c3 {
- status = "okay";
-};
-
-&gpio_expander_21 {
- status = "okay";
-};
-
-/* Verdin I2C_1 */
-&i2c4 {
- status = "okay";
-
- /* Audio Codec */
- nau8822_1a: audio-codec@1a {
- compatible = "nuvoton,nau8822";
- reg = <0x1a>;
- #sound-dai-cells = <0>;
- };
-};
-
-/* Verdin PCIE_1 */
-&pcie0 {
- status = "okay";
-};
-
-&pcie_phy {
- status = "okay";
-};
-
-/* Verdin PWM_3_DSI */
-&pwm1 {
- status = "okay";
-};
-
-/* Verdin PWM_1 */
-&pwm2 {
- status = "okay";
-};
-
-/* Verdin PWM_2 */
-&pwm3 {
- status = "okay";
-};
-
-/* Verdin I2S_1 */
-&sai2 {
- status = "okay";
-};
-
-/* Verdin UART_3 */
-&uart1 {
- status = "okay";
-};
-
-/* Verdin UART_1, connector X50 through RS485 transceiver */
-&uart2 {
- linux,rs485-enabled-at-boot-time;
- rs485-rts-active-low;
- rs485-rx-during-tx;
- status = "okay";
-};
-
-/* Verdin UART_2 */
-&uart3 {
- status = "okay";
-};
-
-/* Verdin USB_1 */
-&usbotg1 {
- disable-over-current;
- status = "okay";
-};
-
-/* Verdin USB_2 */
-&usbotg2 {
- disable-over-current;
- status = "okay";
-};
-
-/* Limit frequency on dev board due to long traces and bad signal integrity */
-&usdhc2 {
- max-frequency = <100000000>;
- status = "okay";
-};
diff --git a/arch/arm/dts/imx8mm-verdin-wifi-dev.dts b/arch/arm/dts/imx8mm-verdin-wifi-dev.dts
deleted file mode 100644
index ef95202..0000000
--- a/arch/arm/dts/imx8mm-verdin-wifi-dev.dts
+++ /dev/null
@@ -1,18 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
-/*
- * Copyright 2022 Toradex
- */
-
-/dts-v1/;
-
-#include "imx8mm-verdin.dtsi"
-#include "imx8mm-verdin-wifi.dtsi"
-#include "imx8mm-verdin-dev.dtsi"
-
-/ {
- model = "Toradex Verdin iMX8M Mini WB on Verdin Development Board";
- compatible = "toradex,verdin-imx8mm-wifi-dev",
- "toradex,verdin-imx8mm-wifi",
- "toradex,verdin-imx8mm",
- "fsl,imx8mm";
-};
diff --git a/arch/arm/dts/imx8mm-verdin-wifi.dtsi b/arch/arm/dts/imx8mm-verdin-wifi.dtsi
deleted file mode 100644
index 017db9e..0000000
--- a/arch/arm/dts/imx8mm-verdin-wifi.dtsi
+++ /dev/null
@@ -1,94 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
-/*
- * Copyright 2022 Toradex
- */
-
-/ {
- reg_wifi_en: regulator-wifi-en {
- compatible = "regulator-fixed";
- enable-active-high;
- gpio = <&gpio3 25 GPIO_ACTIVE_HIGH>;
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_wifi_pwr_en>;
- regulator-max-microvolt = <3300000>;
- regulator-min-microvolt = <3300000>;
- regulator-name = "PDn_AW-CM276NF";
- startup-delay-us = <2000>;
- };
-};
-
-&gpio3 {
- gpio-line-names = "SODIMM_52",
- "SODIMM_54",
- "SODIMM_64",
- "SODIMM_21",
- "SODIMM_206",
- "SODIMM_76",
- "SODIMM_56",
- "SODIMM_58",
- "SODIMM_60",
- "SODIMM_62",
- "",
- "",
- "",
- "",
- "SODIMM_66",
- "SODIMM_17",
- "",
- "",
- "",
- "SODIMM_244",
- "",
- "SODIMM_48",
- "SODIMM_44",
- "SODIMM_42",
- "SODIMM_46";
-};
-
-&gpio4 {
- gpio-line-names = "SODIMM_102",
- "SODIMM_90",
- "SODIMM_92",
- "SODIMM_94",
- "SODIMM_96",
- "SODIMM_100",
- "",
- "",
- "",
- "",
- "SODIMM_120",
- "SODIMM_104",
- "SODIMM_106",
- "SODIMM_108",
- "SODIMM_112",
- "SODIMM_114",
- "SODIMM_116",
- "",
- "SODIMM_118",
- "",
- "SODIMM_88",
- "SODIMM_149",
- "SODIMM_147",
- "SODIMM_36",
- "SODIMM_32",
- "SODIMM_30",
- "SODIMM_34",
- "SODIMM_38",
- "SODIMM_252",
- "SODIMM_133",
- "SODIMM_135",
- "SODIMM_129";
-};
-
-/* On-module Wi-Fi */
-&usdhc3 {
- bus-width = <4>;
- keep-power-in-suspend;
- non-removable;
- pinctrl-names = "default", "state_100mhz", "state_200mhz";
- pinctrl-0 = <&pinctrl_usdhc3>, <&pinctrl_wifi_ctrl>;
- pinctrl-1 = <&pinctrl_usdhc3_100mhz>, <&pinctrl_wifi_ctrl>;
- pinctrl-2 = <&pinctrl_usdhc3_200mhz>, <&pinctrl_wifi_ctrl>;
- vmmc-supply = <®_wifi_en>;
- status = "okay";
-};
diff --git a/arch/arm/dts/imx8mm-verdin.dtsi b/arch/arm/dts/imx8mm-verdin.dtsi
deleted file mode 100644
index 6f08115..0000000
--- a/arch/arm/dts/imx8mm-verdin.dtsi
+++ /dev/null
@@ -1,1319 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
-/*
- * Copyright 2022 Toradex
- */
-
-#include <dt-bindings/phy/phy-imx8-pcie.h>
-#include <dt-bindings/pwm/pwm.h>
-#include "imx8mm.dtsi"
-
-/ {
- chosen {
- stdout-path = &uart1;
- };
-
- aliases {
- rtc0 = &rtc_i2c;
- rtc1 = &snvs_rtc;
- };
-
- backlight: backlight {
- compatible = "pwm-backlight";
- brightness-levels = <0 45 63 88 119 158 203 255>;
- default-brightness-level = <4>;
- /* Verdin I2S_2_D_OUT (DSI_1_BKL_EN/DSI_1_BKL_EN_LVDS, SODIMM 46) */
- enable-gpios = <&gpio3 24 GPIO_ACTIVE_HIGH>;
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_i2s_2_d_out_dsi_1_bkl_en>;
- power-supply = <®_3p3v>;
- /* Verdin PWM_3_DSI/PWM_3_DSI_LVDS (SODIMM 19) */
- pwms = <&pwm1 0 6666667 PWM_POLARITY_INVERTED>;
- status = "disabled";
- };
-
- /* Fixed clock dedicated to SPI CAN controller */
- clk40m: oscillator {
- compatible = "fixed-clock";
- #clock-cells = <0>;
- clock-frequency = <40000000>;
- };
-
- gpio-keys {
- compatible = "gpio-keys";
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_gpio_keys>;
-
- key-wakeup {
- debounce-interval = <10>;
- /* Verdin CTRL_WAKE1_MICO# (SODIMM 252) */
- gpios = <&gpio4 28 GPIO_ACTIVE_LOW>;
- label = "Wake-Up";
- linux,code = <KEY_WAKEUP>;
- wakeup-source;
- };
- };
-
- hdmi_connector: hdmi-connector {
- compatible = "hdmi-connector";
- ddc-i2c-bus = <&i2c2>;
- /* Verdin PWM_3_DSI (SODIMM 19) */
- hpd-gpios = <&gpio1 1 GPIO_ACTIVE_HIGH>;
- label = "hdmi";
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_pwm_3_dsi_hpd_gpio>;
- type = "a";
- status = "disabled";
- };
-
- panel_lvds: panel-lvds {
- compatible = "panel-lvds";
- backlight = <&backlight>;
- data-mapping = "vesa-24";
- status = "disabled";
- };
-
- /* Carrier Board Supplies */
- reg_1p8v: regulator-1p8v {
- compatible = "regulator-fixed";
- regulator-max-microvolt = <1800000>;
- regulator-min-microvolt = <1800000>;
- regulator-name = "+V1.8_SW";
- };
-
- reg_3p3v: regulator-3p3v {
- compatible = "regulator-fixed";
- regulator-max-microvolt = <3300000>;
- regulator-min-microvolt = <3300000>;
- regulator-name = "+V3.3_SW";
- };
-
- reg_5p0v: regulator-5p0v {
- compatible = "regulator-fixed";
- regulator-max-microvolt = <5000000>;
- regulator-min-microvolt = <5000000>;
- regulator-name = "+V5_SW";
- };
-
- /* Non PMIC On-module Supplies */
- reg_ethphy: regulator-ethphy {
- compatible = "regulator-fixed";
- enable-active-high;
- gpio = <&gpio2 20 GPIO_ACTIVE_HIGH>; /* PMIC_EN_ETH */
- off-on-delay-us = <500000>;
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_reg_eth>;
- regulator-always-on;
- regulator-boot-on;
- regulator-max-microvolt = <3300000>;
- regulator-min-microvolt = <3300000>;
- regulator-name = "On-module +V3.3_ETH";
- startup-delay-us = <200000>;
- };
-
- reg_usb_otg1_vbus: regulator-usb-otg1 {
- compatible = "regulator-fixed";
- enable-active-high;
- /* Verdin USB_1_EN (SODIMM 155) */
- gpio = <&gpio1 12 GPIO_ACTIVE_HIGH>;
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_reg_usb1_en>;
- regulator-max-microvolt = <5000000>;
- regulator-min-microvolt = <5000000>;
- regulator-name = "USB_1_EN";
- };
-
- reg_usb_otg2_vbus: regulator-usb-otg2 {
- compatible = "regulator-fixed";
- enable-active-high;
- /* Verdin USB_2_EN (SODIMM 185) */
- gpio = <&gpio1 14 GPIO_ACTIVE_HIGH>;
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_reg_usb2_en>;
- regulator-max-microvolt = <5000000>;
- regulator-min-microvolt = <5000000>;
- regulator-name = "USB_2_EN";
- };
-
- reg_usdhc2_vmmc: regulator-usdhc2 {
- compatible = "regulator-fixed";
- enable-active-high;
- /* Verdin SD_1_PWR_EN (SODIMM 76) */
- gpio = <&gpio3 5 GPIO_ACTIVE_HIGH>;
- off-on-delay-us = <100000>;
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_usdhc2_pwr_en>;
- regulator-max-microvolt = <3300000>;
- regulator-min-microvolt = <3300000>;
- regulator-name = "+V3.3_SD";
- startup-delay-us = <2000>;
- };
-
- reserved-memory {
- #address-cells = <2>;
- #size-cells = <2>;
- ranges;
-
- /* Use the kernel configuration settings instead */
- /delete-node/ linux,cma;
- };
-};
-
-&A53_0 {
- cpu-supply = <®_vdd_arm>;
-};
-
-&A53_1 {
- cpu-supply = <®_vdd_arm>;
-};
-
-&A53_2 {
- cpu-supply = <®_vdd_arm>;
-};
-
-&A53_3 {
- cpu-supply = <®_vdd_arm>;
-};
-
-&cpu_alert0 {
- temperature = <95000>;
-};
-
-&cpu_crit0 {
- temperature = <105000>;
-};
-
-&ddrc {
- operating-points-v2 = <&ddrc_opp_table>;
-
- ddrc_opp_table: opp-table {
- compatible = "operating-points-v2";
-
- opp-25000000 {
- opp-hz = /bits/ 64 <25000000>;
- };
-
- opp-100000000 {
- opp-hz = /bits/ 64 <100000000>;
- };
-
- opp-750000000 {
- opp-hz = /bits/ 64 <750000000>;
- };
- };
-};
-
-/* Verdin SPI_1 */
-&ecspi2 {
- #address-cells = <1>;
- #size-cells = <0>;
- cs-gpios = <&gpio5 13 GPIO_ACTIVE_LOW>;
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_ecspi2>;
-};
-
-/* Verdin CAN_1 (On-module) */
-&ecspi3 {
- #address-cells = <1>;
- #size-cells = <0>;
- cs-gpios = <&gpio5 25 GPIO_ACTIVE_LOW>;
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_ecspi3>;
- status = "okay";
-
- can1: can@0 {
- compatible = "microchip,mcp251xfd";
- clocks = <&clk40m>;
- interrupts-extended = <&gpio1 6 IRQ_TYPE_LEVEL_LOW>;
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_can1_int>;
- reg = <0>;
- spi-max-frequency = <8500000>;
- };
-};
-
-/* Verdin ETH_1 (On-module PHY) */
-&fec1 {
- fsl,magic-packet;
- phy-handle = <ðphy0>;
- phy-mode = "rgmii-id";
- phy-supply = <®_ethphy>;
- pinctrl-names = "default", "sleep";
- pinctrl-0 = <&pinctrl_fec1>;
- pinctrl-1 = <&pinctrl_fec1_sleep>;
-
- mdio {
- #address-cells = <1>;
- #size-cells = <0>;
-
- ethphy0: ethernet-phy@7 {
- compatible = "ethernet-phy-ieee802.3-c22";
- interrupt-parent = <&gpio1>;
- interrupts = <10 IRQ_TYPE_LEVEL_LOW>;
- micrel,led-mode = <0>;
- reg = <7>;
- };
- };
-};
-
-/* Verdin QSPI_1 */
-&flexspi {
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_flexspi0>;
-};
-
-&gpio1 {
- gpio-line-names = "SODIMM_216",
- "SODIMM_19",
- "",
- "",
- "",
- "",
- "",
- "",
- "SODIMM_220",
- "SODIMM_222",
- "",
- "SODIMM_218",
- "SODIMM_155",
- "SODIMM_157",
- "SODIMM_185",
- "SODIMM_187";
-};
-
-&gpio2 {
- gpio-line-names = "",
- "",
- "",
- "",
- "",
- "",
- "",
- "",
- "",
- "",
- "",
- "",
- "SODIMM_84",
- "SODIMM_78",
- "SODIMM_74",
- "SODIMM_80",
- "SODIMM_82",
- "SODIMM_70",
- "SODIMM_72";
-};
-
-&gpio5 {
- gpio-line-names = "SODIMM_131",
- "",
- "SODIMM_91",
- "SODIMM_16",
- "SODIMM_15",
- "SODIMM_208",
- "SODIMM_137",
- "SODIMM_139",
- "SODIMM_141",
- "SODIMM_143",
- "SODIMM_196",
- "SODIMM_200",
- "SODIMM_198",
- "SODIMM_202",
- "",
- "",
- "SODIMM_55",
- "SODIMM_53",
- "SODIMM_95",
- "SODIMM_93",
- "SODIMM_14",
- "SODIMM_12",
- "",
- "",
- "",
- "",
- "SODIMM_210",
- "SODIMM_212",
- "SODIMM_151",
- "SODIMM_153";
-
- ctrl-sleep-moci-hog {
- gpio-hog;
- /* Verdin CTRL_SLEEP_MOCI# (SODIMM 256) */
- gpios = <1 GPIO_ACTIVE_HIGH>;
- line-name = "CTRL_SLEEP_MOCI#";
- output-high;
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_ctrl_sleep_moci>;
- };
-};
-
-/* On-module I2C */
-&i2c1 {
- clock-frequency = <400000>;
- pinctrl-names = "default", "gpio";
- pinctrl-0 = <&pinctrl_i2c1>;
- pinctrl-1 = <&pinctrl_i2c1_gpio>;
- scl-gpios = <&gpio5 14 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
- sda-gpios = <&gpio5 15 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
- status = "okay";
-
- pca9450: pmic@25 {
- compatible = "nxp,pca9450a";
- interrupt-parent = <&gpio1>;
- /* PMIC PCA9450 PMIC_nINT GPIO1_IO3 */
- interrupts = <3 IRQ_TYPE_LEVEL_LOW>;
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_pmic>;
- reg = <0x25>;
-
- /*
- * The bootloader is expected to switch on the I2C level shifter for the TLA2024 ADC
- * behind this PMIC.
- */
-
- regulators {
- reg_vdd_soc: BUCK1 {
- nxp,dvs-run-voltage = <850000>;
- nxp,dvs-standby-voltage = <800000>;
- regulator-always-on;
- regulator-boot-on;
- regulator-max-microvolt = <850000>;
- regulator-min-microvolt = <800000>;
- regulator-name = "On-module +VDD_SOC (BUCK1)";
- regulator-ramp-delay = <3125>;
- };
-
- reg_vdd_arm: BUCK2 {
- nxp,dvs-run-voltage = <950000>;
- nxp,dvs-standby-voltage = <850000>;
- regulator-always-on;
- regulator-boot-on;
- regulator-max-microvolt = <1050000>;
- regulator-min-microvolt = <805000>;
- regulator-name = "On-module +VDD_ARM (BUCK2)";
- regulator-ramp-delay = <3125>;
- };
-
- reg_vdd_dram: BUCK3 {
- regulator-always-on;
- regulator-boot-on;
- regulator-max-microvolt = <1000000>;
- regulator-min-microvolt = <805000>;
- regulator-name = "On-module +VDD_GPU_VPU_DDR (BUCK3)";
- };
-
- reg_vdd_3v3: BUCK4 {
- regulator-always-on;
- regulator-boot-on;
- regulator-max-microvolt = <3300000>;
- regulator-min-microvolt = <3300000>;
- regulator-name = "On-module +V3.3 (BUCK4)";
- };
-
- reg_vdd_1v8: BUCK5 {
- regulator-always-on;
- regulator-boot-on;
- regulator-max-microvolt = <1800000>;
- regulator-min-microvolt = <1800000>;
- regulator-name = "PWR_1V8_MOCI (BUCK5)";
- };
-
- reg_nvcc_dram: BUCK6 {
- regulator-always-on;
- regulator-boot-on;
- regulator-max-microvolt = <1100000>;
- regulator-min-microvolt = <1100000>;
- regulator-name = "On-module +VDD_DDR (BUCK6)";
- };
-
- reg_nvcc_snvs: LDO1 {
- regulator-always-on;
- regulator-boot-on;
- regulator-max-microvolt = <1800000>;
- regulator-min-microvolt = <1800000>;
- regulator-name = "On-module +V1.8_SNVS (LDO1)";
- };
-
- reg_vdd_snvs: LDO2 {
- regulator-always-on;
- regulator-boot-on;
- regulator-max-microvolt = <800000>;
- regulator-min-microvolt = <800000>;
- regulator-name = "On-module +V0.8_SNVS (LDO2)";
- };
-
- reg_vdda: LDO3 {
- regulator-always-on;
- regulator-boot-on;
- regulator-max-microvolt = <1800000>;
- regulator-min-microvolt = <1800000>;
- regulator-name = "On-module +V1.8A (LDO3)";
- };
-
- reg_vdd_phy: LDO4 {
- regulator-always-on;
- regulator-boot-on;
- regulator-max-microvolt = <900000>;
- regulator-min-microvolt = <900000>;
- regulator-name = "On-module +V0.9_MIPI (LDO4)";
- };
-
- reg_nvcc_sd: LDO5 {
- regulator-max-microvolt = <3300000>;
- regulator-min-microvolt = <1800000>;
- regulator-name = "On-module +V3.3_1.8_SD (LDO5)";
- };
- };
- };
-
- rtc_i2c: rtc@32 {
- compatible = "epson,rx8130";
- reg = <0x32>;
- };
-
- adc@49 {
- compatible = "ti,ads1015";
- reg = <0x49>;
- #address-cells = <1>;
- #size-cells = <0>;
-
- /* Verdin I2C_1 (ADC_4 - ADC_3) */
- channel@0 {
- reg = <0>;
- ti,datarate = <4>;
- ti,gain = <2>;
- };
-
- /* Verdin I2C_1 (ADC_4 - ADC_1) */
- channel@1 {
- reg = <1>;
- ti,datarate = <4>;
- ti,gain = <2>;
- };
-
- /* Verdin I2C_1 (ADC_3 - ADC_1) */
- channel@2 {
- reg = <2>;
- ti,datarate = <4>;
- ti,gain = <2>;
- };
-
- /* Verdin I2C_1 (ADC_2 - ADC_1) */
- channel@3 {
- reg = <3>;
- ti,datarate = <4>;
- ti,gain = <2>;
- };
-
- /* Verdin I2C_1 ADC_4 */
- channel@4 {
- reg = <4>;
- ti,datarate = <4>;
- ti,gain = <2>;
- };
-
- /* Verdin I2C_1 ADC_3 */
- channel@5 {
- reg = <5>;
- ti,datarate = <4>;
- ti,gain = <2>;
- };
-
- /* Verdin I2C_1 ADC_2 */
- channel@6 {
- reg = <6>;
- ti,datarate = <4>;
- ti,gain = <2>;
- };
-
- /* Verdin I2C_1 ADC_1 */
- channel@7 {
- reg = <7>;
- ti,datarate = <4>;
- ti,gain = <2>;
- };
- };
-
- eeprom@50 {
- compatible = "st,24c02";
- pagesize = <16>;
- reg = <0x50>;
- };
-};
-
-/* Verdin I2C_2_DSI */
-&i2c2 {
- clock-frequency = <10000>;
- pinctrl-names = "default", "gpio";
- pinctrl-0 = <&pinctrl_i2c2>;
- pinctrl-1 = <&pinctrl_i2c2_gpio>;
- scl-gpios = <&gpio5 16 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
- sda-gpios = <&gpio5 17 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
- status = "disabled";
-};
-
-/* Verdin I2C_3_HDMI N/A */
-
-/* Verdin I2C_4_CSI */
-&i2c3 {
- clock-frequency = <400000>;
- pinctrl-names = "default", "gpio";
- pinctrl-0 = <&pinctrl_i2c3>;
- pinctrl-1 = <&pinctrl_i2c3_gpio>;
- scl-gpios = <&gpio5 18 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
- sda-gpios = <&gpio5 19 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
-};
-
-/* Verdin I2C_1 */
-&i2c4 {
- clock-frequency = <400000>;
- pinctrl-names = "default", "gpio";
- pinctrl-0 = <&pinctrl_i2c4>;
- pinctrl-1 = <&pinctrl_i2c4_gpio>;
- scl-gpios = <&gpio5 20 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
- sda-gpios = <&gpio5 21 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
-
- gpio_expander_21: gpio-expander@21 {
- compatible = "nxp,pcal6416";
- #gpio-cells = <2>;
- gpio-controller;
- reg = <0x21>;
- vcc-supply = <®_3p3v>;
- status = "disabled";
- };
-
- lvds_ti_sn65dsi84: bridge@2c {
- compatible = "ti,sn65dsi84";
- /* Verdin GPIO_9_DSI (SN65DSI84 IRQ, SODIMM 17, unused) */
- /* Verdin GPIO_10_DSI (SODIMM 21) */
- enable-gpios = <&gpio3 3 GPIO_ACTIVE_HIGH>;
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_gpio_10_dsi>;
- reg = <0x2c>;
- status = "disabled";
- };
-
- /* Current measurement into module VCC */
- hwmon: hwmon@40 {
- compatible = "ti,ina219";
- reg = <0x40>;
- shunt-resistor = <10000>;
- status = "disabled";
- };
-
- hdmi_lontium_lt8912: hdmi@48 {
- compatible = "lontium,lt8912b";
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_gpio_10_dsi>;
- reg = <0x48>;
- /* Verdin GPIO_9_DSI (LT8912 INT, SODIMM 17, unused) */
- /* Verdin GPIO_10_DSI (SODIMM 21) */
- reset-gpios = <&gpio3 3 GPIO_ACTIVE_LOW>;
- status = "disabled";
- };
-
- atmel_mxt_ts: touch@4a {
- compatible = "atmel,maxtouch";
- /*
- * Verdin GPIO_9_DSI
- * (TOUCH_INT#, SODIMM 17, also routed to SN65DSI84 IRQ albeit currently unused)
- */
- interrupt-parent = <&gpio3>;
- interrupts = <15 IRQ_TYPE_EDGE_FALLING>;
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_gpio_9_dsi>, <&pinctrl_i2s_2_bclk_touch_reset>;
- reg = <0x4a>;
- /* Verdin I2S_2_BCLK (TOUCH_RESET#, SODIMM 42) */
- reset-gpios = <&gpio3 23 GPIO_ACTIVE_LOW>;
- status = "disabled";
- };
-
- /* Temperature sensor on carrier board */
- hwmon_temp: sensor@4f {
- compatible = "ti,tmp75c";
- reg = <0x4f>;
- status = "disabled";
- };
-
- /* EEPROM on display adapter (MIPI DSI Display Adapter) */
- eeprom_display_adapter: eeprom@50 {
- compatible = "st,24c02";
- pagesize = <16>;
- reg = <0x50>;
- status = "disabled";
- };
-
- /* EEPROM on carrier board */
- eeprom_carrier_board: eeprom@57 {
- compatible = "st,24c02";
- pagesize = <16>;
- reg = <0x57>;
- status = "disabled";
- };
-};
-
-/* Verdin PCIE_1 */
-&pcie0 {
- assigned-clocks = <&clk IMX8MM_CLK_PCIE1_AUX>,
- <&clk IMX8MM_CLK_PCIE1_CTRL>;
- assigned-clock-parents = <&clk IMX8MM_SYS_PLL2_50M>,
- <&clk IMX8MM_SYS_PLL2_250M>;
- assigned-clock-rates = <10000000>, <250000000>;
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_pcie0>;
- /* PCIE_1_RESET# (SODIMM 244) */
- reset-gpio = <&gpio3 19 GPIO_ACTIVE_LOW>;
-};
-
-&pcie_phy {
- clocks = <&clk IMX8MM_CLK_PCIE1_PHY>;
- clock-names = "ref";
- fsl,clkreq-unsupported;
- fsl,refclk-pad-mode = <IMX8_PCIE_REFCLK_PAD_OUTPUT>;
- fsl,tx-deemph-gen1 = <0x2d>;
- fsl,tx-deemph-gen2 = <0xf>;
-};
-
-/* Verdin PWM_3_DSI */
-&pwm1 {
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_pwm_1>;
- #pwm-cells = <3>;
-};
-
-/* Verdin PWM_1 */
-&pwm2 {
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_pwm_2>;
- #pwm-cells = <3>;
-};
-
-/* Verdin PWM_2 */
-&pwm3 {
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_pwm_3>;
- #pwm-cells = <3>;
-};
-
-/* Verdin I2S_1 */
-&sai2 {
- #sound-dai-cells = <0>;
- assigned-clock-parents = <&clk IMX8MM_AUDIO_PLL1_OUT>;
- assigned-clock-rates = <24576000>;
- assigned-clocks = <&clk IMX8MM_CLK_SAI2>;
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_sai2>;
-};
-
-&snvs_pwrkey {
- status = "okay";
-};
-
-/* Verdin UART_3, used as the Linux console */
-&uart1 {
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_uart1>;
-};
-
-/* Verdin UART_1 */
-&uart2 {
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_uart2>;
- uart-has-rtscts;
-};
-
-/* Verdin UART_2 */
-&uart3 {
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_uart3>;
- uart-has-rtscts;
-};
-
-/*
- * Verdin UART_4
- * Resource allocated to M4 by default, must not be accessed from Cortex-A35 or you get an OOPS
- */
-&uart4 {
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_uart4>;
-};
-
-/* Verdin USB_1 */
-&usbotg1 {
- adp-disable;
- dr_mode = "otg";
- hnp-disable;
- samsung,picophy-dc-vol-level-adjust = <7>;
- samsung,picophy-pre-emp-curr-control = <3>;
- srp-disable;
- vbus-supply = <®_usb_otg1_vbus>;
-};
-
-/* Verdin USB_2 */
-&usbotg2 {
- dr_mode = "host";
- samsung,picophy-dc-vol-level-adjust = <7>;
- samsung,picophy-pre-emp-curr-control = <3>;
- vbus-supply = <®_usb_otg2_vbus>;
-};
-
-&usbphynop1 {
- vcc-supply = <®_vdd_3v3>;
-};
-
-&usbphynop2 {
- power-domains = <&pgc_otg2>;
- vcc-supply = <®_vdd_3v3>;
-};
-
-/* On-module eMMC */
-&usdhc1 {
- bus-width = <8>;
- keep-power-in-suspend;
- non-removable;
- pinctrl-names = "default", "state_100mhz", "state_200mhz";
- pinctrl-0 = <&pinctrl_usdhc1>;
- pinctrl-1 = <&pinctrl_usdhc1_100mhz>;
- pinctrl-2 = <&pinctrl_usdhc1_200mhz>;
- status = "okay";
-};
-
-/* Verdin SD_1 */
-&usdhc2 {
- bus-width = <4>;
- cd-gpios = <&gpio2 12 GPIO_ACTIVE_LOW>;
- disable-wp;
- pinctrl-names = "default", "state_100mhz", "state_200mhz", "sleep";
- pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_cd>;
- pinctrl-1 = <&pinctrl_usdhc2_100mhz>, <&pinctrl_usdhc2_cd>;
- pinctrl-2 = <&pinctrl_usdhc2_200mhz>, <&pinctrl_usdhc2_cd>;
- pinctrl-3 = <&pinctrl_usdhc2_sleep>, <&pinctrl_usdhc2_cd_sleep>;
- vmmc-supply = <®_usdhc2_vmmc>;
-};
-
-&wdog1 {
- fsl,ext-reset-output;
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_wdog>;
- status = "okay";
-};
-
-&iomuxc {
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_gpio1>, <&pinctrl_gpio2>,
- <&pinctrl_gpio3>, <&pinctrl_gpio4>,
- <&pinctrl_gpio7>, <&pinctrl_gpio8>,
- <&pinctrl_gpio_hog1>, <&pinctrl_gpio_hog2>, <&pinctrl_gpio_hog3>,
- <&pinctrl_pmic_tpm_ena>;
-
- pinctrl_can1_int: can1intgrp {
- fsl,pins =
- <MX8MM_IOMUXC_GPIO1_IO06_GPIO1_IO6 0x146>; /* CAN_1_SPI_INT#_1.8V */
- };
-
- pinctrl_can2_int: can2intgrp {
- fsl,pins =
- <MX8MM_IOMUXC_GPIO1_IO07_GPIO1_IO7 0x106>; /* CAN_2_SPI_INT#_1.8V, unused */
- };
-
- pinctrl_ctrl_sleep_moci: ctrlsleepmocigrp {
- fsl,pins =
- <MX8MM_IOMUXC_SAI3_TXD_GPIO5_IO1 0x106>; /* SODIMM 256 */
- };
-
- pinctrl_ecspi2: ecspi2grp {
- fsl,pins =
- <MX8MM_IOMUXC_ECSPI2_MISO_ECSPI2_MISO 0x6>, /* SODIMM 198 */
- <MX8MM_IOMUXC_ECSPI2_MOSI_ECSPI2_MOSI 0x6>, /* SODIMM 200 */
- <MX8MM_IOMUXC_ECSPI2_SCLK_ECSPI2_SCLK 0x6>, /* SODIMM 196 */
- <MX8MM_IOMUXC_ECSPI2_SS0_GPIO5_IO13 0x6>; /* SODIMM 202 */
- };
-
- pinctrl_ecspi3: ecspi3grp {
- fsl,pins =
- <MX8MM_IOMUXC_GPIO1_IO05_GPIO1_IO5 0x146>, /* CAN_2_SPI_CS#_1.8V */
- <MX8MM_IOMUXC_UART1_RXD_ECSPI3_SCLK 0x6>, /* CAN_SPI_SCK_1.8V */
- <MX8MM_IOMUXC_UART1_TXD_ECSPI3_MOSI 0x6>, /* CAN_SPI_MOSI_1.8V */
- <MX8MM_IOMUXC_UART2_RXD_ECSPI3_MISO 0x6>, /* CAN_SPI_MISO_1.8V */
- <MX8MM_IOMUXC_UART2_TXD_GPIO5_IO25 0x6>; /* CAN_1_SPI_CS_1.8V# */
- };
-
- pinctrl_fec1: fec1grp {
- fsl,pins =
- <MX8MM_IOMUXC_ENET_MDC_ENET1_MDC 0x3>,
- <MX8MM_IOMUXC_ENET_MDIO_ENET1_MDIO 0x3>,
- <MX8MM_IOMUXC_ENET_RD0_ENET1_RGMII_RD0 0x91>,
- <MX8MM_IOMUXC_ENET_RD1_ENET1_RGMII_RD1 0x91>,
- <MX8MM_IOMUXC_ENET_RD2_ENET1_RGMII_RD2 0x91>,
- <MX8MM_IOMUXC_ENET_RD3_ENET1_RGMII_RD3 0x91>,
- <MX8MM_IOMUXC_ENET_RXC_ENET1_RGMII_RXC 0x91>,
- <MX8MM_IOMUXC_ENET_RX_CTL_ENET1_RGMII_RX_CTL 0x91>,
- <MX8MM_IOMUXC_ENET_TD0_ENET1_RGMII_TD0 0x1f>,
- <MX8MM_IOMUXC_ENET_TD1_ENET1_RGMII_TD1 0x1f>,
- <MX8MM_IOMUXC_ENET_TD2_ENET1_RGMII_TD2 0x1f>,
- <MX8MM_IOMUXC_ENET_TD3_ENET1_RGMII_TD3 0x1f>,
- <MX8MM_IOMUXC_ENET_TXC_ENET1_RGMII_TXC 0x1f>,
- <MX8MM_IOMUXC_ENET_TX_CTL_ENET1_RGMII_TX_CTL 0x1f>,
- <MX8MM_IOMUXC_GPIO1_IO10_GPIO1_IO10 0x146>;
- };
-
- pinctrl_fec1_sleep: fec1-sleepgrp {
- fsl,pins =
- <MX8MM_IOMUXC_ENET_MDC_ENET1_MDC 0x3>,
- <MX8MM_IOMUXC_ENET_MDIO_ENET1_MDIO 0x3>,
- <MX8MM_IOMUXC_ENET_RD0_ENET1_RGMII_RD0 0x91>,
- <MX8MM_IOMUXC_ENET_RD1_ENET1_RGMII_RD1 0x91>,
- <MX8MM_IOMUXC_ENET_RD2_ENET1_RGMII_RD2 0x91>,
- <MX8MM_IOMUXC_ENET_RD3_ENET1_RGMII_RD3 0x91>,
- <MX8MM_IOMUXC_ENET_RXC_ENET1_RGMII_RXC 0x91>,
- <MX8MM_IOMUXC_ENET_RX_CTL_ENET1_RGMII_RX_CTL 0x91>,
- <MX8MM_IOMUXC_ENET_TD0_GPIO1_IO21 0x1f>,
- <MX8MM_IOMUXC_ENET_TD1_GPIO1_IO20 0x1f>,
- <MX8MM_IOMUXC_ENET_TD2_GPIO1_IO19 0x1f>,
- <MX8MM_IOMUXC_ENET_TD3_GPIO1_IO18 0x1f>,
- <MX8MM_IOMUXC_ENET_TXC_GPIO1_IO23 0x1f>,
- <MX8MM_IOMUXC_ENET_TX_CTL_GPIO1_IO22 0x1f>,
- <MX8MM_IOMUXC_GPIO1_IO10_GPIO1_IO10 0x106>;
- };
-
- pinctrl_flexspi0: flexspi0grp {
- fsl,pins =
- <MX8MM_IOMUXC_NAND_ALE_QSPI_A_SCLK 0x106>, /* SODIMM 52 */
- <MX8MM_IOMUXC_NAND_CE0_B_QSPI_A_SS0_B 0x106>, /* SODIMM 54 */
- <MX8MM_IOMUXC_NAND_CE1_B_QSPI_A_SS1_B 0x106>, /* SODIMM 64 */
- <MX8MM_IOMUXC_NAND_DATA00_QSPI_A_DATA0 0x106>, /* SODIMM 56 */
- <MX8MM_IOMUXC_NAND_DATA01_QSPI_A_DATA1 0x106>, /* SODIMM 58 */
- <MX8MM_IOMUXC_NAND_DATA02_QSPI_A_DATA2 0x106>, /* SODIMM 60 */
- <MX8MM_IOMUXC_NAND_DATA03_QSPI_A_DATA3 0x106>, /* SODIMM 62 */
- <MX8MM_IOMUXC_NAND_DQS_QSPI_A_DQS 0x106>; /* SODIMM 66 */
- };
-
- pinctrl_gpio1: gpio1grp {
- fsl,pins =
- <MX8MM_IOMUXC_NAND_CE3_B_GPIO3_IO4 0x106>; /* SODIMM 206 */
- };
-
- pinctrl_gpio2: gpio2grp {
- fsl,pins =
- <MX8MM_IOMUXC_SPDIF_EXT_CLK_GPIO5_IO5 0x106>; /* SODIMM 208 */
- };
-
- pinctrl_gpio3: gpio3grp {
- fsl,pins =
- <MX8MM_IOMUXC_UART3_RXD_GPIO5_IO26 0x106>; /* SODIMM 210 */
- };
-
- pinctrl_gpio4: gpio4grp {
- fsl,pins =
- <MX8MM_IOMUXC_UART3_TXD_GPIO5_IO27 0x106>; /* SODIMM 212 */
- };
-
- pinctrl_gpio5: gpio5grp {
- fsl,pins =
- <MX8MM_IOMUXC_GPIO1_IO00_GPIO1_IO0 0x106>; /* SODIMM 216 */
- };
-
- pinctrl_gpio6: gpio6grp {
- fsl,pins =
- <MX8MM_IOMUXC_GPIO1_IO11_GPIO1_IO11 0x106>; /* SODIMM 218 */
- };
-
- pinctrl_gpio7: gpio7grp {
- fsl,pins =
- <MX8MM_IOMUXC_GPIO1_IO08_GPIO1_IO8 0x106>; /* SODIMM 220 */
- };
-
- pinctrl_gpio8: gpio8grp {
- fsl,pins =
- <MX8MM_IOMUXC_GPIO1_IO09_GPIO1_IO9 0x106>; /* SODIMM 222 */
- };
-
- /* Verdin GPIO_9_DSI (pulled-up as active-low) */
- pinctrl_gpio_9_dsi: gpio9dsigrp {
- fsl,pins =
- <MX8MM_IOMUXC_NAND_RE_B_GPIO3_IO15 0x146>; /* SODIMM 17 */
- };
-
- /* Verdin GPIO_10_DSI (pulled-up as active-low) */
- pinctrl_gpio_10_dsi: gpio10dsigrp {
- fsl,pins =
- <MX8MM_IOMUXC_NAND_CE2_B_GPIO3_IO3 0x146>; /* SODIMM 21 */
- };
-
- pinctrl_gpio_hog1: gpiohog1grp {
- fsl,pins =
- <MX8MM_IOMUXC_SAI1_MCLK_GPIO4_IO20 0x106>, /* SODIMM 88 */
- <MX8MM_IOMUXC_SAI1_RXC_GPIO4_IO1 0x106>, /* SODIMM 90 */
- <MX8MM_IOMUXC_SAI1_RXD0_GPIO4_IO2 0x106>, /* SODIMM 92 */
- <MX8MM_IOMUXC_SAI1_RXD1_GPIO4_IO3 0x106>, /* SODIMM 94 */
- <MX8MM_IOMUXC_SAI1_RXD2_GPIO4_IO4 0x106>, /* SODIMM 96 */
- <MX8MM_IOMUXC_SAI1_RXD3_GPIO4_IO5 0x106>, /* SODIMM 100 */
- <MX8MM_IOMUXC_SAI1_RXFS_GPIO4_IO0 0x106>, /* SODIMM 102 */
- <MX8MM_IOMUXC_SAI1_TXC_GPIO4_IO11 0x106>, /* SODIMM 104 */
- <MX8MM_IOMUXC_SAI1_TXD0_GPIO4_IO12 0x106>, /* SODIMM 106 */
- <MX8MM_IOMUXC_SAI1_TXD1_GPIO4_IO13 0x106>, /* SODIMM 108 */
- <MX8MM_IOMUXC_SAI1_TXD2_GPIO4_IO14 0x106>, /* SODIMM 112 */
- <MX8MM_IOMUXC_SAI1_TXD3_GPIO4_IO15 0x106>, /* SODIMM 114 */
- <MX8MM_IOMUXC_SAI1_TXD4_GPIO4_IO16 0x106>, /* SODIMM 116 */
- <MX8MM_IOMUXC_SAI1_TXD6_GPIO4_IO18 0x106>, /* SODIMM 118 */
- <MX8MM_IOMUXC_SAI1_TXFS_GPIO4_IO10 0x106>; /* SODIMM 120 */
- };
-
- pinctrl_gpio_hog2: gpiohog2grp {
- fsl,pins =
- <MX8MM_IOMUXC_SAI3_MCLK_GPIO5_IO2 0x106>; /* SODIMM 91 */
- };
-
- pinctrl_gpio_hog3: gpiohog3grp {
- fsl,pins =
- <MX8MM_IOMUXC_GPIO1_IO13_GPIO1_IO13 0x146>, /* SODIMM 157 */
- <MX8MM_IOMUXC_GPIO1_IO15_GPIO1_IO15 0x146>; /* SODIMM 187 */
- };
-
- pinctrl_gpio_keys: gpiokeysgrp {
- fsl,pins =
- <MX8MM_IOMUXC_SAI3_RXFS_GPIO4_IO28 0x146>; /* SODIMM 252 */
- };
-
- /* On-module I2C */
- pinctrl_i2c1: i2c1grp {
- fsl,pins =
- <MX8MM_IOMUXC_I2C1_SCL_I2C1_SCL 0x40000146>, /* PMIC_I2C_SCL */
- <MX8MM_IOMUXC_I2C1_SDA_I2C1_SDA 0x40000146>; /* PMIC_I2C_SDA */
- };
-
- pinctrl_i2c1_gpio: i2c1gpiogrp {
- fsl,pins =
- <MX8MM_IOMUXC_I2C1_SCL_GPIO5_IO14 0x146>, /* PMIC_I2C_SCL */
- <MX8MM_IOMUXC_I2C1_SDA_GPIO5_IO15 0x146>; /* PMIC_I2C_SDA */
- };
-
- /* Verdin I2C_4_CSI */
- pinctrl_i2c2: i2c2grp {
- fsl,pins =
- <MX8MM_IOMUXC_I2C2_SCL_I2C2_SCL 0x40000146>, /* SODIMM 55 */
- <MX8MM_IOMUXC_I2C2_SDA_I2C2_SDA 0x40000146>; /* SODIMM 53 */
- };
-
- pinctrl_i2c2_gpio: i2c2gpiogrp {
- fsl,pins =
- <MX8MM_IOMUXC_I2C2_SCL_GPIO5_IO16 0x146>, /* SODIMM 55 */
- <MX8MM_IOMUXC_I2C2_SDA_GPIO5_IO17 0x146>; /* SODIMM 53 */
- };
-
- /* Verdin I2C_2_DSI */
- pinctrl_i2c3: i2c3grp {
- fsl,pins =
- <MX8MM_IOMUXC_I2C3_SCL_I2C3_SCL 0x40000146>, /* SODIMM 95 */
- <MX8MM_IOMUXC_I2C3_SDA_I2C3_SDA 0x40000146>; /* SODIMM 93 */
- };
-
- pinctrl_i2c3_gpio: i2c3gpiogrp {
- fsl,pins =
- <MX8MM_IOMUXC_I2C3_SCL_GPIO5_IO18 0x146>, /* SODIMM 95 */
- <MX8MM_IOMUXC_I2C3_SDA_GPIO5_IO19 0x146>; /* SODIMM 93 */
- };
-
- /* Verdin I2C_1 */
- pinctrl_i2c4: i2c4grp {
- fsl,pins =
- <MX8MM_IOMUXC_I2C4_SCL_I2C4_SCL 0x40000146>, /* SODIMM 14 */
- <MX8MM_IOMUXC_I2C4_SDA_I2C4_SDA 0x40000146>; /* SODIMM 12 */
- };
-
- pinctrl_i2c4_gpio: i2c4gpiogrp {
- fsl,pins =
- <MX8MM_IOMUXC_I2C4_SCL_GPIO5_IO20 0x146>, /* SODIMM 14 */
- <MX8MM_IOMUXC_I2C4_SDA_GPIO5_IO21 0x146>; /* SODIMM 12 */
- };
-
- /* Verdin I2S_2_BCLK (TOUCH_RESET#) */
- pinctrl_i2s_2_bclk_touch_reset: i2s2bclktouchresetgrp {
- fsl,pins =
- <MX8MM_IOMUXC_SAI5_RXD2_GPIO3_IO23 0x6>; /* SODIMM 42 */
- };
-
- /* Verdin I2S_2_D_OUT shared with SAI5 */
- pinctrl_i2s_2_d_out_dsi_1_bkl_en: i2s2doutdsi1bklengrp {
- fsl,pins =
- <MX8MM_IOMUXC_SAI5_RXD3_GPIO3_IO24 0x6>; /* SODIMM 46 */
- };
-
- pinctrl_pcie0: pcie0grp {
- fsl,pins =
- <MX8MM_IOMUXC_SAI5_RXFS_GPIO3_IO19 0x6>, /* SODIMM 244 */
- /* PMIC_EN_PCIe_CLK, unused */
- <MX8MM_IOMUXC_SD2_RESET_B_GPIO2_IO19 0x6>;
- };
-
- pinctrl_pmic: pmicirqgrp {
- fsl,pins =
- <MX8MM_IOMUXC_GPIO1_IO03_GPIO1_IO3 0x141>; /* PMIC_INT# */
- };
-
- /* Verdin PWM_3_DSI shared with GPIO1_IO1 */
- pinctrl_pwm_1: pwm1grp {
- fsl,pins =
- <MX8MM_IOMUXC_GPIO1_IO01_PWM1_OUT 0x6>; /* SODIMM 19 */
- };
-
- pinctrl_pwm_2: pwm2grp {
- fsl,pins =
- <MX8MM_IOMUXC_SPDIF_RX_PWM2_OUT 0x6>; /* SODIMM 15 */
- };
-
- pinctrl_pwm_3: pwm3grp {
- fsl,pins =
- <MX8MM_IOMUXC_SPDIF_TX_PWM3_OUT 0x6>; /* SODIMM 16 */
- };
-
- /* Verdin PWM_3_DSI (pulled-down as active-high) shared with PWM1_OUT */
- pinctrl_pwm_3_dsi_hpd_gpio: pwm3dsihpdgpiogrp {
- fsl,pins =
- <MX8MM_IOMUXC_GPIO1_IO01_GPIO1_IO1 0x106>; /* SODIMM 19 */
- };
-
- pinctrl_reg_eth: regethgrp {
- fsl,pins =
- <MX8MM_IOMUXC_SD2_WP_GPIO2_IO20 0x146>; /* PMIC_EN_ETH */
- };
-
- pinctrl_reg_usb1_en: regusb1engrp {
- fsl,pins =
- <MX8MM_IOMUXC_GPIO1_IO12_GPIO1_IO12 0x106>; /* SODIMM 155 */
- };
-
- pinctrl_reg_usb2_en: regusb2engrp {
- fsl,pins =
- <MX8MM_IOMUXC_GPIO1_IO14_GPIO1_IO14 0x106>; /* SODIMM 185 */
- };
-
- pinctrl_sai2: sai2grp {
- fsl,pins =
- <MX8MM_IOMUXC_SAI2_MCLK_SAI2_MCLK 0x6>, /* SODIMM 38 */
- <MX8MM_IOMUXC_SAI2_TXC_SAI2_TX_BCLK 0x6>, /* SODIMM 30 */
- <MX8MM_IOMUXC_SAI2_TXFS_SAI2_TX_SYNC 0x6>, /* SODIMM 32 */
- <MX8MM_IOMUXC_SAI2_RXD0_SAI2_RX_DATA0 0x6>, /* SODIMM 36 */
- <MX8MM_IOMUXC_SAI2_TXD0_SAI2_TX_DATA0 0x6>; /* SODIMM 34 */
- };
-
- pinctrl_sai5: sai5grp {
- fsl,pins =
- <MX8MM_IOMUXC_SAI5_RXD0_SAI5_RX_DATA0 0x6>, /* SODIMM 48 */
- <MX8MM_IOMUXC_SAI5_RXD1_SAI5_TX_SYNC 0x6>, /* SODIMM 44 */
- <MX8MM_IOMUXC_SAI5_RXD2_SAI5_TX_BCLK 0x6>, /* SODIMM 42 */
- <MX8MM_IOMUXC_SAI5_RXD3_SAI5_TX_DATA0 0x6>; /* SODIMM 46 */
- };
-
- /* control signal for optional ATTPM20P or SE050 */
- pinctrl_pmic_tpm_ena: pmictpmenagrp {
- fsl,pins =
- <MX8MM_IOMUXC_SAI1_TXD7_GPIO4_IO19 0x106>; /* PMIC_TPM_ENA */
- };
-
- pinctrl_tsp: tspgrp {
- fsl,pins =
- <MX8MM_IOMUXC_SAI1_RXD4_GPIO4_IO6 0x6>, /* SODIMM 148 */
- <MX8MM_IOMUXC_SAI1_RXD5_GPIO4_IO7 0x6>, /* SODIMM 152 */
- <MX8MM_IOMUXC_SAI1_RXD6_GPIO4_IO8 0x6>, /* SODIMM 154 */
- <MX8MM_IOMUXC_SAI1_RXD7_GPIO4_IO9 0x146>, /* SODIMM 174 */
- <MX8MM_IOMUXC_SAI1_TXD5_GPIO4_IO17 0x6>; /* SODIMM 150 */
- };
-
- pinctrl_uart1: uart1grp {
- fsl,pins =
- <MX8MM_IOMUXC_SAI2_RXC_UART1_DCE_RX 0x146>, /* SODIMM 147 */
- <MX8MM_IOMUXC_SAI2_RXFS_UART1_DCE_TX 0x146>; /* SODIMM 149 */
- };
-
- pinctrl_uart2: uart2grp {
- fsl,pins =
- <MX8MM_IOMUXC_SAI3_RXC_UART2_DCE_CTS_B 0x146>, /* SODIMM 133 */
- <MX8MM_IOMUXC_SAI3_RXD_UART2_DCE_RTS_B 0x146>, /* SODIMM 135 */
- <MX8MM_IOMUXC_SAI3_TXC_UART2_DCE_TX 0x146>, /* SODIMM 131 */
- <MX8MM_IOMUXC_SAI3_TXFS_UART2_DCE_RX 0x146>; /* SODIMM 129 */
- };
-
- pinctrl_uart3: uart3grp {
- fsl,pins =
- <MX8MM_IOMUXC_ECSPI1_MISO_UART3_DCE_CTS_B 0x146>, /* SODIMM 141 */
- <MX8MM_IOMUXC_ECSPI1_MOSI_UART3_DCE_TX 0x146>, /* SODIMM 139 */
- <MX8MM_IOMUXC_ECSPI1_SCLK_UART3_DCE_RX 0x146>, /* SODIMM 137 */
- <MX8MM_IOMUXC_ECSPI1_SS0_UART3_DCE_RTS_B 0x146>; /* SODIMM 143 */
- };
-
- pinctrl_uart4: uart4grp {
- fsl,pins =
- <MX8MM_IOMUXC_UART4_RXD_UART4_DCE_RX 0x146>, /* SODIMM 151 */
- <MX8MM_IOMUXC_UART4_TXD_UART4_DCE_TX 0x146>; /* SODIMM 153 */
- };
-
- pinctrl_usdhc1: usdhc1grp {
- fsl,pins =
- <MX8MM_IOMUXC_SD1_CLK_USDHC1_CLK 0x190>,
- <MX8MM_IOMUXC_SD1_CMD_USDHC1_CMD 0x1d0>,
- <MX8MM_IOMUXC_SD1_DATA0_USDHC1_DATA0 0x1d0>,
- <MX8MM_IOMUXC_SD1_DATA1_USDHC1_DATA1 0x1d0>,
- <MX8MM_IOMUXC_SD1_DATA2_USDHC1_DATA2 0x1d0>,
- <MX8MM_IOMUXC_SD1_DATA3_USDHC1_DATA3 0x1d0>,
- <MX8MM_IOMUXC_SD1_DATA4_USDHC1_DATA4 0x1d0>,
- <MX8MM_IOMUXC_SD1_DATA5_USDHC1_DATA5 0x1d0>,
- <MX8MM_IOMUXC_SD1_DATA6_USDHC1_DATA6 0x1d0>,
- <MX8MM_IOMUXC_SD1_DATA7_USDHC1_DATA7 0x1d0>,
- <MX8MM_IOMUXC_SD1_RESET_B_USDHC1_RESET_B 0x1d1>,
- <MX8MM_IOMUXC_SD1_STROBE_USDHC1_STROBE 0x190>;
- };
-
- pinctrl_usdhc1_100mhz: usdhc1-100mhzgrp {
- fsl,pins =
- <MX8MM_IOMUXC_SD1_CLK_USDHC1_CLK 0x194>,
- <MX8MM_IOMUXC_SD1_CMD_USDHC1_CMD 0x1d4>,
- <MX8MM_IOMUXC_SD1_DATA0_USDHC1_DATA0 0x1d4>,
- <MX8MM_IOMUXC_SD1_DATA1_USDHC1_DATA1 0x1d4>,
- <MX8MM_IOMUXC_SD1_DATA2_USDHC1_DATA2 0x1d4>,
- <MX8MM_IOMUXC_SD1_DATA3_USDHC1_DATA3 0x1d4>,
- <MX8MM_IOMUXC_SD1_DATA4_USDHC1_DATA4 0x1d4>,
- <MX8MM_IOMUXC_SD1_DATA5_USDHC1_DATA5 0x1d4>,
- <MX8MM_IOMUXC_SD1_DATA6_USDHC1_DATA6 0x1d4>,
- <MX8MM_IOMUXC_SD1_DATA7_USDHC1_DATA7 0x1d4>,
- <MX8MM_IOMUXC_SD1_RESET_B_USDHC1_RESET_B 0x1d1>,
- <MX8MM_IOMUXC_SD1_STROBE_USDHC1_STROBE 0x194>;
- };
-
- pinctrl_usdhc1_200mhz: usdhc1-200mhzgrp {
- fsl,pins =
- <MX8MM_IOMUXC_SD1_CLK_USDHC1_CLK 0x196>,
- <MX8MM_IOMUXC_SD1_CMD_USDHC1_CMD 0x1d6>,
- <MX8MM_IOMUXC_SD1_DATA0_USDHC1_DATA0 0x1d6>,
- <MX8MM_IOMUXC_SD1_DATA1_USDHC1_DATA1 0x1d6>,
- <MX8MM_IOMUXC_SD1_DATA2_USDHC1_DATA2 0x1d6>,
- <MX8MM_IOMUXC_SD1_DATA3_USDHC1_DATA3 0x1d6>,
- <MX8MM_IOMUXC_SD1_DATA4_USDHC1_DATA4 0x1d6>,
- <MX8MM_IOMUXC_SD1_DATA5_USDHC1_DATA5 0x1d6>,
- <MX8MM_IOMUXC_SD1_DATA6_USDHC1_DATA6 0x1d6>,
- <MX8MM_IOMUXC_SD1_DATA7_USDHC1_DATA7 0x1d6>,
- <MX8MM_IOMUXC_SD1_RESET_B_USDHC1_RESET_B 0x1d1>,
- <MX8MM_IOMUXC_SD1_STROBE_USDHC1_STROBE 0x196>;
- };
-
- pinctrl_usdhc2_cd: usdhc2cdgrp {
- fsl,pins =
- <MX8MM_IOMUXC_SD2_CD_B_GPIO2_IO12 0x6>; /* SODIMM 84 */
- };
-
- pinctrl_usdhc2_cd_sleep: usdhc2cdslpgrp {
- fsl,pins =
- <MX8MM_IOMUXC_SD2_CD_B_GPIO2_IO12 0x0>; /* SODIMM 84 */
- };
-
- pinctrl_usdhc2_pwr_en: usdhc2pwrengrp {
- fsl,pins =
- <MX8MM_IOMUXC_NAND_CLE_GPIO3_IO5 0x6>; /* SODIMM 76 */
- };
-
- /*
- * Note: Due to ERR050080 we use discrete external on-module resistors pulling-up to the
- * on-module +V3.3_1.8_SD (LDO5) rail and explicitly disable the internal pull-ups here.
- */
- pinctrl_usdhc2: usdhc2grp {
- fsl,pins =
- <MX8MM_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0x10>,
- <MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK 0x90>, /* SODIMM 78 */
- <MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD 0x90>, /* SODIMM 74 */
- <MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x90>, /* SODIMM 80 */
- <MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x90>, /* SODIMM 82 */
- <MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x90>, /* SODIMM 70 */
- <MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x90>; /* SODIMM 72 */
- };
-
- pinctrl_usdhc2_100mhz: usdhc2-100mhzgrp {
- fsl,pins =
- <MX8MM_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0x10>,
- <MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK 0x94>,
- <MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD 0x94>,
- <MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x94>,
- <MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x94>,
- <MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x94>,
- <MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x94>;
- };
-
- pinctrl_usdhc2_200mhz: usdhc2-200mhzgrp {
- fsl,pins =
- <MX8MM_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0x10>,
- <MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK 0x96>,
- <MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD 0x96>,
- <MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x96>,
- <MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x96>,
- <MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x96>,
- <MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x96>;
- };
-
- /* Avoid backfeeding with removed card power */
- pinctrl_usdhc2_sleep: usdhc2slpgrp {
- fsl,pins =
- <MX8MM_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0x0>,
- <MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK 0x0>,
- <MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD 0x0>,
- <MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x0>,
- <MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x0>,
- <MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x0>,
- <MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x0>;
- };
-
- /*
- * On-module Wi-Fi/BT or type specific SDHC interface
- * (e.g. on X52 extension slot of Verdin Development Board)
- */
- pinctrl_usdhc3: usdhc3grp {
- fsl,pins =
- <MX8MM_IOMUXC_NAND_DATA04_USDHC3_DATA0 0x150>,
- <MX8MM_IOMUXC_NAND_DATA05_USDHC3_DATA1 0x150>,
- <MX8MM_IOMUXC_NAND_DATA06_USDHC3_DATA2 0x150>,
- <MX8MM_IOMUXC_NAND_DATA07_USDHC3_DATA3 0x150>,
- <MX8MM_IOMUXC_NAND_WE_B_USDHC3_CLK 0x150>,
- <MX8MM_IOMUXC_NAND_WP_B_USDHC3_CMD 0x150>;
- };
-
- pinctrl_usdhc3_100mhz: usdhc3-100mhzgrp {
- fsl,pins =
- <MX8MM_IOMUXC_NAND_DATA04_USDHC3_DATA0 0x154>,
- <MX8MM_IOMUXC_NAND_DATA05_USDHC3_DATA1 0x154>,
- <MX8MM_IOMUXC_NAND_DATA06_USDHC3_DATA2 0x154>,
- <MX8MM_IOMUXC_NAND_DATA07_USDHC3_DATA3 0x154>,
- <MX8MM_IOMUXC_NAND_WE_B_USDHC3_CLK 0x154>,
- <MX8MM_IOMUXC_NAND_WP_B_USDHC3_CMD 0x154>;
- };
-
- pinctrl_usdhc3_200mhz: usdhc3-200mhzgrp {
- fsl,pins =
- <MX8MM_IOMUXC_NAND_DATA04_USDHC3_DATA0 0x156>,
- <MX8MM_IOMUXC_NAND_DATA05_USDHC3_DATA1 0x156>,
- <MX8MM_IOMUXC_NAND_DATA06_USDHC3_DATA2 0x156>,
- <MX8MM_IOMUXC_NAND_DATA07_USDHC3_DATA3 0x156>,
- <MX8MM_IOMUXC_NAND_WE_B_USDHC3_CLK 0x156>,
- <MX8MM_IOMUXC_NAND_WP_B_USDHC3_CMD 0x156>;
- };
-
- pinctrl_wdog: wdoggrp {
- fsl,pins =
- <MX8MM_IOMUXC_GPIO1_IO02_WDOG1_WDOG_B 0x166>; /* PMIC_WDI */
- };
-
- pinctrl_wifi_ctrl: wifictrlgrp {
- fsl,pins =
- <MX8MM_IOMUXC_NAND_READY_B_GPIO3_IO16 0x46>, /* WIFI_WKUP_BT */
- <MX8MM_IOMUXC_SAI1_RXD7_GPIO4_IO9 0x146>, /* WIFI_W_WKUP_HOST */
- <MX8MM_IOMUXC_SAI5_RXC_GPIO3_IO20 0x46>; /* WIFI_WKUP_WLAN */
- };
-
- pinctrl_wifi_i2s: bti2sgrp {
- fsl,pins =
- <MX8MM_IOMUXC_SAI1_RXD4_SAI6_TX_BCLK 0x6>, /* WIFI_TX_BCLK */
- <MX8MM_IOMUXC_SAI1_RXD5_SAI6_TX_DATA0 0x6>, /* WIFI_TX_DATA0 */
- <MX8MM_IOMUXC_SAI1_RXD6_SAI6_TX_SYNC 0x6>, /* WIFI_TX_SYNC */
- <MX8MM_IOMUXC_SAI1_TXD5_SAI6_RX_DATA0 0x6>; /* WIFI_RX_DATA0 */
- };
-
- pinctrl_wifi_pwr_en: wifipwrengrp {
- fsl,pins =
- <MX8MM_IOMUXC_SAI5_MCLK_GPIO3_IO25 0x6>; /* PMIC_EN_WIFI */
- };
-};
diff --git a/arch/arm/dts/imx8mn-beacon-kit.dts b/arch/arm/dts/imx8mn-beacon-kit.dts
deleted file mode 100644
index 1392ce0..0000000
--- a/arch/arm/dts/imx8mn-beacon-kit.dts
+++ /dev/null
@@ -1,19 +0,0 @@
-// SPDX-License-Identifier: (GPL-2.0 OR MIT)
-/*
- * Copyright 2020 Compass Electronics Group, LLC
- */
-
-/dts-v1/;
-
-#include "imx8mn.dtsi"
-#include "imx8mn-beacon-som.dtsi"
-#include "imx8mn-beacon-baseboard.dtsi"
-
-/ {
- model = "Beacon EmbeddedWorks i.MX8M Nano Development Kit";
- compatible = "beacon,imx8mn-beacon-kit", "fsl,imx8mn";
-
- chosen {
- stdout-path = &uart2;
- };
-};
diff --git a/arch/arm/dts/imx8mn-beacon-som.dtsi b/arch/arm/dts/imx8mn-beacon-som.dtsi
deleted file mode 100644
index 1133cde..0000000
--- a/arch/arm/dts/imx8mn-beacon-som.dtsi
+++ /dev/null
@@ -1,472 +0,0 @@
-// SPDX-License-Identifier: (GPL-2.0 OR MIT)
-/*
- * Copyright 2020 Compass Electronics Group, LLC
- */
-
-/ {
- aliases {
- rtc0 = &rtc;
- rtc1 = &snvs_rtc;
- spi0 = &flexspi;
- };
-
- usdhc1_pwrseq: usdhc1_pwrseq {
- compatible = "mmc-pwrseq-simple";
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_usdhc1_gpio>;
- reset-gpios = <&gpio2 10 GPIO_ACTIVE_LOW>;
- clocks = <&osc_32k>;
- clock-names = "ext_clock";
- post-power-on-delay-ms = <80>;
- };
-
- memory@40000000 {
- device_type = "memory";
- reg = <0x0 0x40000000 0 0x80000000>;
- };
-};
-
-&A53_0 {
- cpu-supply = <&buck2_reg>;
-};
-
-&A53_1 {
- cpu-supply = <&buck2_reg>;
-};
-
-&A53_2 {
- cpu-supply = <&buck2_reg>;
-};
-
-&A53_3 {
- cpu-supply = <&buck2_reg>;
-};
-
-/* DDR controller is running LPDDR at 800MHz which requires 0.95V */
-&a53_opp_table {
- opp-1200000000 {
- opp-microvolt = <950000>;
- };
-};
-
-&ddrc {
- operating-points-v2 = <&ddrc_opp_table>;
-
- ddrc_opp_table: opp-table {
- compatible = "operating-points-v2";
-
- opp-25M {
- opp-hz = /bits/ 64 <25000000>;
- };
-
- opp-100M {
- opp-hz = /bits/ 64 <100000000>;
- };
-
- opp-800M {
- opp-hz = /bits/ 64 <800000000>;
- };
- };
-};
-
-&fec1 {
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_fec1>;
- phy-mode = "rgmii-id";
- phy-handle = <ðphy0>;
- phy-supply = <&buck6_reg>;
- phy-reset-gpios = <&gpio4 22 GPIO_ACTIVE_LOW>;
- fsl,magic-packet;
- status = "okay";
-
- mdio {
- #address-cells = <1>;
- #size-cells = <0>;
-
- ethphy0: ethernet-phy@0 {
- compatible = "ethernet-phy-ieee802.3-c22";
- reg = <0>;
- };
- };
-};
-
-&flexspi {
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_flexspi>;
- status = "okay";
-
- flash@0 {
- reg = <0>;
- #address-cells = <1>;
- #size-cells = <1>;
- compatible = "jedec,spi-nor";
- spi-max-frequency = <80000000>;
- spi-tx-bus-width = <1>;
- spi-rx-bus-width = <4>;
- };
-};
-
-&i2c1 {
- clock-frequency = <400000>;
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_i2c1>;
- status = "okay";
-
- pmic@4b {
- compatible = "rohm,bd71847";
- reg = <0x4b>;
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_pmic>;
- interrupt-parent = <&gpio1>;
- interrupts = <3 IRQ_TYPE_LEVEL_LOW>;
- rohm,reset-snvs-powered;
- #clock-cells = <0>;
- clocks = <&osc_32k 0>;
- clock-output-names = "clk-32k-out";
-
- regulators {
- buck1_reg: BUCK1 {
- regulator-name = "buck1";
- regulator-min-microvolt = <700000>;
- regulator-max-microvolt = <1300000>;
- regulator-boot-on;
- regulator-always-on;
- regulator-ramp-delay = <1250>;
- };
-
- buck2_reg: BUCK2 {
- regulator-name = "buck2";
- regulator-min-microvolt = <700000>;
- regulator-max-microvolt = <1300000>;
- regulator-boot-on;
- regulator-always-on;
- regulator-ramp-delay = <1250>;
- rohm,dvs-run-voltage = <1000000>;
- rohm,dvs-idle-voltage = <900000>;
- };
-
- buck3_reg: BUCK3 {
- // BUCK5 in datasheet
- regulator-name = "buck3";
- regulator-min-microvolt = <700000>;
- regulator-max-microvolt = <1350000>;
- regulator-boot-on;
- regulator-always-on;
- };
-
- buck4_reg: BUCK4 {
- // BUCK6 in datasheet
- regulator-name = "buck4";
- regulator-min-microvolt = <3000000>;
- regulator-max-microvolt = <3300000>;
- regulator-boot-on;
- regulator-always-on;
- };
-
- buck5_reg: BUCK5 {
- // BUCK7 in datasheet
- regulator-name = "buck5";
- regulator-min-microvolt = <1605000>;
- regulator-max-microvolt = <1995000>;
- regulator-boot-on;
- regulator-always-on;
- };
-
- buck6_reg: BUCK6 {
- // BUCK8 in datasheet
- regulator-name = "buck6";
- regulator-min-microvolt = <800000>;
- regulator-max-microvolt = <1400000>;
- regulator-boot-on;
- regulator-always-on;
- };
-
- ldo1_reg: LDO1 {
- regulator-name = "ldo1";
- regulator-min-microvolt = <1600000>;
- regulator-max-microvolt = <3300000>;
- regulator-boot-on;
- regulator-always-on;
- };
-
- ldo2_reg: LDO2 {
- regulator-name = "ldo2";
- regulator-min-microvolt = <800000>;
- regulator-max-microvolt = <900000>;
- regulator-boot-on;
- regulator-always-on;
- };
-
- ldo3_reg: LDO3 {
- regulator-name = "ldo3";
- regulator-min-microvolt = <1800000>;
- regulator-max-microvolt = <3300000>;
- regulator-boot-on;
- regulator-always-on;
- };
-
- ldo4_reg: LDO4 {
- regulator-name = "ldo4";
- regulator-min-microvolt = <900000>;
- regulator-max-microvolt = <1800000>;
- regulator-boot-on;
- regulator-always-on;
- };
-
- ldo6_reg: LDO6 {
- regulator-name = "ldo6";
- regulator-min-microvolt = <900000>;
- regulator-max-microvolt = <1800000>;
- regulator-boot-on;
- regulator-always-on;
- };
- };
- };
-};
-
-&i2c3 {
- clock-frequency = <400000>;
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_i2c3>;
- status = "okay";
-
- eeprom@50 {
- compatible = "microchip,24c64", "atmel,24c64";
- pagesize = <32>;
- read-only; /* Manufacturing EEPROM programmed at factory */
- reg = <0x50>;
- };
-
- rtc: rtc@51 {
- compatible = "nxp,pcf85263";
- reg = <0x51>;
- };
-};
-
-&uart1 {
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_uart1>;
- assigned-clocks = <&clk IMX8MN_CLK_UART1>;
- assigned-clock-parents = <&clk IMX8MN_SYS_PLL1_80M>;
- uart-has-rtscts;
- status = "okay";
-
- bluetooth {
- compatible = "brcm,bcm43438-bt";
- shutdown-gpios = <&gpio2 6 GPIO_ACTIVE_HIGH>;
- host-wakeup-gpios = <&gpio2 8 GPIO_ACTIVE_HIGH>;
- device-wakeup-gpios = <&gpio2 7 GPIO_ACTIVE_HIGH>;
- clocks = <&osc_32k>;
- max-speed = <4000000>;
- clock-names = "extclk";
- };
-};
-
-&usdhc1 {
- #address-cells = <1>;
- #size-cells = <0>;
- pinctrl-names = "default", "state_100mhz", "state_200mhz";
- pinctrl-0 = <&pinctrl_usdhc1>;
- pinctrl-1 = <&pinctrl_usdhc1_100mhz>;
- pinctrl-2 = <&pinctrl_usdhc1_200mhz>;
- vmmc-supply = <&buck4_reg>;
- vqmmc-supply = <&buck5_reg>;
- bus-width = <4>;
- non-removable;
- cap-power-off-card;
- keep-power-in-suspend;
- mmc-pwrseq = <&usdhc1_pwrseq>;
- status = "okay";
-
- brcmf: bcrmf@1 {
- reg = <1>;
- compatible = "brcm,bcm4329-fmac";
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_wlan>;
- interrupt-parent = <&gpio2>;
- interrupts = <9 IRQ_TYPE_LEVEL_HIGH>;
- interrupt-names = "host-wake";
- };
-};
-
-&usdhc3 {
- pinctrl-names = "default", "state_100mhz", "state_200mhz";
- pinctrl-0 = <&pinctrl_usdhc3>;
- pinctrl-1 = <&pinctrl_usdhc3_100mhz>;
- pinctrl-2 = <&pinctrl_usdhc3_200mhz>;
- bus-width = <8>;
- non-removable;
- status = "okay";
-};
-
-&wdog1 {
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_wdog>;
- fsl,ext-reset-output;
- status = "okay";
-};
-
-&iomuxc {
- pinctrl_fec1: fec1grp {
- fsl,pins = <
- MX8MN_IOMUXC_ENET_MDC_ENET1_MDC 0x3
- MX8MN_IOMUXC_ENET_MDIO_ENET1_MDIO 0x3
- MX8MN_IOMUXC_ENET_TD3_ENET1_RGMII_TD3 0x1f
- MX8MN_IOMUXC_ENET_TD2_ENET1_RGMII_TD2 0x1f
- MX8MN_IOMUXC_ENET_TD1_ENET1_RGMII_TD1 0x1f
- MX8MN_IOMUXC_ENET_TD0_ENET1_RGMII_TD0 0x1f
- MX8MN_IOMUXC_ENET_RD3_ENET1_RGMII_RD3 0x91
- MX8MN_IOMUXC_ENET_RD2_ENET1_RGMII_RD2 0x91
- MX8MN_IOMUXC_ENET_RD1_ENET1_RGMII_RD1 0x91
- MX8MN_IOMUXC_ENET_RD0_ENET1_RGMII_RD0 0x91
- MX8MN_IOMUXC_ENET_TXC_ENET1_RGMII_TXC 0x1f
- MX8MN_IOMUXC_ENET_RXC_ENET1_RGMII_RXC 0x91
- MX8MN_IOMUXC_ENET_RX_CTL_ENET1_RGMII_RX_CTL 0x91
- MX8MN_IOMUXC_ENET_TX_CTL_ENET1_RGMII_TX_CTL 0x1f
- MX8MN_IOMUXC_SAI2_RXC_GPIO4_IO22 0x19
- >;
- };
-
- pinctrl_i2c1: i2c1grp {
- fsl,pins = <
- MX8MN_IOMUXC_I2C1_SCL_I2C1_SCL 0x400001c3
- MX8MN_IOMUXC_I2C1_SDA_I2C1_SDA 0x400001c3
- >;
- };
-
- pinctrl_i2c3: i2c3grp {
- fsl,pins = <
- MX8MN_IOMUXC_I2C3_SCL_I2C3_SCL 0x400001c3
- MX8MN_IOMUXC_I2C3_SDA_I2C3_SDA 0x400001c3
- >;
- };
-
- pinctrl_flexspi: flexspigrp {
- fsl,pins = <
- MX8MN_IOMUXC_NAND_ALE_QSPI_A_SCLK 0x1c2
- MX8MN_IOMUXC_NAND_CE0_B_QSPI_A_SS0_B 0x82
- MX8MN_IOMUXC_NAND_DATA00_QSPI_A_DATA0 0x82
- MX8MN_IOMUXC_NAND_DATA01_QSPI_A_DATA1 0x82
- MX8MN_IOMUXC_NAND_DATA02_QSPI_A_DATA2 0x82
- MX8MN_IOMUXC_NAND_DATA03_QSPI_A_DATA3 0x82
- >;
- };
-
- pinctrl_pmic: pmicirqgrp {
- fsl,pins = <
- MX8MN_IOMUXC_GPIO1_IO03_GPIO1_IO3 0x141
- >;
- };
-
- pinctrl_uart1: uart1grp {
- fsl,pins = <
- MX8MN_IOMUXC_UART1_RXD_UART1_DCE_RX 0x140
- MX8MN_IOMUXC_UART1_TXD_UART1_DCE_TX 0x140
- MX8MN_IOMUXC_UART3_RXD_UART1_DCE_CTS_B 0x140
- MX8MN_IOMUXC_UART3_TXD_UART1_DCE_RTS_B 0x140
- MX8MN_IOMUXC_SD1_DATA4_GPIO2_IO6 0x19
- MX8MN_IOMUXC_SD1_DATA5_GPIO2_IO7 0x19
- MX8MN_IOMUXC_SD1_DATA6_GPIO2_IO8 0x19
- MX8MN_IOMUXC_GPIO1_IO00_ANAMIX_REF_CLK_32K 0x141
- >;
- };
-
- pinctrl_usdhc1_gpio: usdhc1gpiogrp {
- fsl,pins = <
- MX8MN_IOMUXC_SD1_RESET_B_GPIO2_IO10 0x41
- >;
- };
-
- pinctrl_usdhc1: usdhc1grp {
- fsl,pins = <
- MX8MN_IOMUXC_SD1_CLK_USDHC1_CLK 0x190
- MX8MN_IOMUXC_SD1_CMD_USDHC1_CMD 0x1d0
- MX8MN_IOMUXC_SD1_DATA0_USDHC1_DATA0 0x1d0
- MX8MN_IOMUXC_SD1_DATA1_USDHC1_DATA1 0x1d0
- MX8MN_IOMUXC_SD1_DATA2_USDHC1_DATA2 0x1d0
- MX8MN_IOMUXC_SD1_DATA3_USDHC1_DATA3 0x1d0
- >;
- };
-
- pinctrl_usdhc1_100mhz: usdhc1-100mhzgrp {
- fsl,pins = <
- MX8MN_IOMUXC_SD1_CLK_USDHC1_CLK 0x194
- MX8MN_IOMUXC_SD1_CMD_USDHC1_CMD 0x1d4
- MX8MN_IOMUXC_SD1_DATA0_USDHC1_DATA0 0x1d4
- MX8MN_IOMUXC_SD1_DATA1_USDHC1_DATA1 0x1d4
- MX8MN_IOMUXC_SD1_DATA2_USDHC1_DATA2 0x1d4
- MX8MN_IOMUXC_SD1_DATA3_USDHC1_DATA3 0x1d4
- >;
- };
-
- pinctrl_usdhc1_200mhz: usdhc1-200mhzgrp {
- fsl,pins = <
- MX8MN_IOMUXC_SD1_CLK_USDHC1_CLK 0x196
- MX8MN_IOMUXC_SD1_CMD_USDHC1_CMD 0x1d6
- MX8MN_IOMUXC_SD1_DATA0_USDHC1_DATA0 0x1d6
- MX8MN_IOMUXC_SD1_DATA1_USDHC1_DATA1 0x1d6
- MX8MN_IOMUXC_SD1_DATA2_USDHC1_DATA2 0x1d6
- MX8MN_IOMUXC_SD1_DATA3_USDHC1_DATA3 0x1d6
- >;
- };
-
- pinctrl_usdhc3: usdhc3grp {
- fsl,pins = <
- MX8MN_IOMUXC_NAND_WE_B_USDHC3_CLK 0x190
- MX8MN_IOMUXC_NAND_WP_B_USDHC3_CMD 0x1d0
- MX8MN_IOMUXC_NAND_DATA04_USDHC3_DATA0 0x1d0
- MX8MN_IOMUXC_NAND_DATA05_USDHC3_DATA1 0x1d0
- MX8MN_IOMUXC_NAND_DATA06_USDHC3_DATA2 0x1d0
- MX8MN_IOMUXC_NAND_DATA07_USDHC3_DATA3 0x1d0
- MX8MN_IOMUXC_NAND_RE_B_USDHC3_DATA4 0x1d0
- MX8MN_IOMUXC_NAND_CE2_B_USDHC3_DATA5 0x1d0
- MX8MN_IOMUXC_NAND_CE3_B_USDHC3_DATA6 0x1d0
- MX8MN_IOMUXC_NAND_CLE_USDHC3_DATA7 0x1d0
- MX8MN_IOMUXC_NAND_CE1_B_USDHC3_STROBE 0x190
- >;
- };
-
- pinctrl_usdhc3_100mhz: usdhc3-100mhzgrp {
- fsl,pins = <
- MX8MN_IOMUXC_NAND_WE_B_USDHC3_CLK 0x194
- MX8MN_IOMUXC_NAND_WP_B_USDHC3_CMD 0x1d4
- MX8MN_IOMUXC_NAND_DATA04_USDHC3_DATA0 0x1d4
- MX8MN_IOMUXC_NAND_DATA05_USDHC3_DATA1 0x1d4
- MX8MN_IOMUXC_NAND_DATA06_USDHC3_DATA2 0x1d4
- MX8MN_IOMUXC_NAND_DATA07_USDHC3_DATA3 0x1d4
- MX8MN_IOMUXC_NAND_RE_B_USDHC3_DATA4 0x1d4
- MX8MN_IOMUXC_NAND_CE2_B_USDHC3_DATA5 0x1d4
- MX8MN_IOMUXC_NAND_CE3_B_USDHC3_DATA6 0x1d4
- MX8MN_IOMUXC_NAND_CLE_USDHC3_DATA7 0x1d4
- MX8MN_IOMUXC_NAND_CE1_B_USDHC3_STROBE 0x194
- >;
- };
-
- pinctrl_usdhc3_200mhz: usdhc3-200mhzgrp {
- fsl,pins = <
- MX8MN_IOMUXC_NAND_WE_B_USDHC3_CLK 0x196
- MX8MN_IOMUXC_NAND_WP_B_USDHC3_CMD 0x1d6
- MX8MN_IOMUXC_NAND_DATA04_USDHC3_DATA0 0x1d6
- MX8MN_IOMUXC_NAND_DATA05_USDHC3_DATA1 0x1d6
- MX8MN_IOMUXC_NAND_DATA06_USDHC3_DATA2 0x1d6
- MX8MN_IOMUXC_NAND_DATA07_USDHC3_DATA3 0x1d6
- MX8MN_IOMUXC_NAND_RE_B_USDHC3_DATA4 0x1d6
- MX8MN_IOMUXC_NAND_CE2_B_USDHC3_DATA5 0x1d6
- MX8MN_IOMUXC_NAND_CE3_B_USDHC3_DATA6 0x1d6
- MX8MN_IOMUXC_NAND_CLE_USDHC3_DATA7 0x1d6
- MX8MN_IOMUXC_NAND_CE1_B_USDHC3_STROBE 0x196
- >;
- };
-
- pinctrl_wdog: wdoggrp {
- fsl,pins = <
- MX8MN_IOMUXC_GPIO1_IO02_WDOG1_WDOG_B 0xc6
- >;
- };
-
- pinctrl_wlan: wlangrp {
- fsl,pins = <
- MX8MN_IOMUXC_SD1_DATA7_GPIO2_IO9 0x111
- >;
- };
-};
diff --git a/arch/arm/dts/imx8mn-ddr4-evk.dts b/arch/arm/dts/imx8mn-ddr4-evk.dts
deleted file mode 100644
index d8ce217..0000000
--- a/arch/arm/dts/imx8mn-ddr4-evk.dts
+++ /dev/null
@@ -1,160 +0,0 @@
-// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
-/*
- * Copyright 2019 NXP
- */
-
-/dts-v1/;
-
-#include "imx8mn.dtsi"
-#include "imx8mn-evk.dtsi"
-
-/ {
- model = "NXP i.MX8MNano DDR4 EVK board";
- compatible = "fsl,imx8mn-ddr4-evk", "fsl,imx8mn";
-};
-
-&A53_0 {
- cpu-supply = <&buck2_reg>;
-};
-
-&A53_1 {
- cpu-supply = <&buck2_reg>;
-};
-
-&A53_2 {
- cpu-supply = <&buck2_reg>;
-};
-
-&A53_3 {
- cpu-supply = <&buck2_reg>;
-};
-
-&ddrc {
- operating-points-v2 = <&ddrc_opp_table>;
-
- ddrc_opp_table: opp-table {
- compatible = "operating-points-v2";
-
- opp-25M {
- opp-hz = /bits/ 64 <25000000>;
- };
-
- opp-100M {
- opp-hz = /bits/ 64 <100000000>;
- };
-
- opp-600M {
- opp-hz = /bits/ 64 <600000000>;
- };
- };
-};
-
-&i2c1 {
- pmic@4b {
- compatible = "rohm,bd71847";
- reg = <0x4b>;
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_pmic>;
- interrupt-parent = <&gpio1>;
- interrupts = <3 IRQ_TYPE_LEVEL_LOW>;
- rohm,reset-snvs-powered;
-
- #clock-cells = <0>;
- clocks = <&osc_32k 0>;
- clock-output-names = "clk-32k-out";
-
- regulators {
- buck1_reg: BUCK1 {
- regulator-name = "buck1";
- regulator-min-microvolt = <700000>;
- regulator-max-microvolt = <1300000>;
- regulator-boot-on;
- regulator-always-on;
- regulator-ramp-delay = <1250>;
- };
-
- buck2_reg: BUCK2 {
- regulator-name = "buck2";
- regulator-min-microvolt = <700000>;
- regulator-max-microvolt = <1300000>;
- regulator-boot-on;
- regulator-always-on;
- regulator-ramp-delay = <1250>;
- };
-
- buck3_reg: BUCK3 {
- // BUCK5 in datasheet
- regulator-name = "buck3";
- regulator-min-microvolt = <700000>;
- regulator-max-microvolt = <1350000>;
- };
-
- buck4_reg: BUCK4 {
- // BUCK6 in datasheet
- regulator-name = "buck4";
- regulator-min-microvolt = <3000000>;
- regulator-max-microvolt = <3300000>;
- regulator-boot-on;
- regulator-always-on;
- };
-
- buck5_reg: BUCK5 {
- // BUCK7 in datasheet
- regulator-name = "buck5";
- regulator-min-microvolt = <1605000>;
- regulator-max-microvolt = <1995000>;
- regulator-boot-on;
- regulator-always-on;
- };
-
- buck6_reg: BUCK6 {
- // BUCK8 in datasheet
- regulator-name = "buck6";
- regulator-min-microvolt = <800000>;
- regulator-max-microvolt = <1400000>;
- regulator-boot-on;
- regulator-always-on;
- };
-
- ldo1_reg: LDO1 {
- regulator-name = "ldo1";
- regulator-min-microvolt = <1600000>;
- regulator-max-microvolt = <3300000>;
- regulator-boot-on;
- regulator-always-on;
- };
-
- ldo2_reg: LDO2 {
- regulator-name = "ldo2";
- regulator-min-microvolt = <800000>;
- regulator-max-microvolt = <900000>;
- regulator-boot-on;
- regulator-always-on;
- };
-
- ldo3_reg: LDO3 {
- regulator-name = "ldo3";
- regulator-min-microvolt = <1800000>;
- regulator-max-microvolt = <3300000>;
- regulator-boot-on;
- regulator-always-on;
- };
-
- ldo4_reg: LDO4 {
- regulator-name = "ldo4";
- regulator-min-microvolt = <900000>;
- regulator-max-microvolt = <1800000>;
- regulator-boot-on;
- regulator-always-on;
- };
-
- ldo6_reg: LDO6 {
- regulator-name = "ldo6";
- regulator-min-microvolt = <900000>;
- regulator-max-microvolt = <1800000>;
- regulator-boot-on;
- regulator-always-on;
- };
- };
- };
-};
diff --git a/arch/arm/dts/imx8mn-evk.dts b/arch/arm/dts/imx8mn-evk.dts
deleted file mode 100644
index 4eb467d..0000000
--- a/arch/arm/dts/imx8mn-evk.dts
+++ /dev/null
@@ -1,128 +0,0 @@
-// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
-/*
- * Copyright 2019 NXP
- */
-
-/dts-v1/;
-
-#include "imx8mn.dtsi"
-#include "imx8mn-evk.dtsi"
-#include <dt-bindings/interrupt-controller/irq.h>
-
-/ {
- model = "NXP i.MX8MNano EVK board";
- compatible = "fsl,imx8mn-evk", "fsl,imx8mn";
-};
-
-&A53_0 {
- cpu-supply = <&buck2>;
-};
-
-&A53_1 {
- cpu-supply = <&buck2>;
-};
-
-&A53_2 {
- cpu-supply = <&buck2>;
-};
-
-&A53_3 {
- cpu-supply = <&buck2>;
-};
-
-&i2c1 {
- pmic: pmic@25 {
- compatible = "nxp,pca9450b";
- reg = <0x25>;
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_pmic>;
- interrupt-parent = <&gpio1>;
- interrupts = <3 IRQ_TYPE_LEVEL_LOW>;
-
- regulators {
- buck1: BUCK1{
- regulator-name = "VDD_SOC";
- regulator-min-microvolt = <850000>;
- regulator-max-microvolt = <950000>;
- regulator-boot-on;
- regulator-always-on;
- regulator-ramp-delay = <3125>;
- };
-
- buck2: BUCK2 {
- regulator-name = "VDD_ARM_0V9";
- regulator-min-microvolt = <850000>;
- regulator-max-microvolt = <1000000>;
- regulator-boot-on;
- regulator-always-on;
- regulator-ramp-delay = <3125>;
- nxp,dvs-run-voltage = <950000>;
- nxp,dvs-standby-voltage = <850000>;
- };
-
- buck4: BUCK4{
- regulator-name = "VDD_3V3";
- regulator-min-microvolt = <3300000>;
- regulator-max-microvolt = <3300000>;
- regulator-boot-on;
- regulator-always-on;
- };
-
- buck5: BUCK5{
- regulator-name = "VDD_1V8";
- regulator-min-microvolt = <1800000>;
- regulator-max-microvolt = <1800000>;
- regulator-boot-on;
- regulator-always-on;
- };
-
- buck6: BUCK6 {
- regulator-name = "NVCC_DRAM_1V1";
- regulator-min-microvolt = <1100000>;
- regulator-max-microvolt = <1100000>;
- regulator-boot-on;
- regulator-always-on;
- };
-
- ldo1: LDO1 {
- regulator-name = "NVCC_SNVS_1V8";
- regulator-min-microvolt = <1800000>;
- regulator-max-microvolt = <1800000>;
- regulator-boot-on;
- regulator-always-on;
- };
-
- ldo2: LDO2 {
- regulator-name = "VDD_SNVS_0V8";
- regulator-min-microvolt = <800000>;
- regulator-max-microvolt = <800000>;
- regulator-boot-on;
- regulator-always-on;
- };
-
- ldo3: LDO3 {
- regulator-name = "VDDA_1V8";
- regulator-min-microvolt = <1800000>;
- regulator-max-microvolt = <1800000>;
- regulator-boot-on;
- regulator-always-on;
- };
-
- ldo4: LDO4 {
- regulator-name = "VDD_PHY_1V2";
- regulator-min-microvolt = <1200000>;
- regulator-max-microvolt = <1200000>;
- regulator-boot-on;
- regulator-always-on;
- };
-
- ldo5: LDO5 {
- regulator-name = "NVCC_SD2";
- regulator-min-microvolt = <1800000>;
- regulator-max-microvolt = <3300000>;
- regulator-boot-on;
- regulator-always-on;
- };
- };
- };
-};
diff --git a/arch/arm/dts/imx8mn-venice-gw7902.dts b/arch/arm/dts/imx8mn-venice-gw7902.dts
deleted file mode 100644
index 97582db..0000000
--- a/arch/arm/dts/imx8mn-venice-gw7902.dts
+++ /dev/null
@@ -1,980 +0,0 @@
-// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
-/*
- * Copyright 2021 Gateworks Corporation
- */
-
-/dts-v1/;
-
-#include <dt-bindings/gpio/gpio.h>
-#include <dt-bindings/input/linux-event-codes.h>
-#include <dt-bindings/leds/common.h>
-#include <dt-bindings/net/ti-dp83867.h>
-
-#include "imx8mn.dtsi"
-
-/ {
- model = "Gateworks Venice GW7902 i.MX8MN board";
- compatible = "gw,imx8mn-gw7902", "fsl,imx8mn";
-
- aliases {
- usb0 = &usbotg1;
- };
-
- chosen {
- stdout-path = &uart2;
- };
-
- memory@40000000 {
- device_type = "memory";
- reg = <0x0 0x40000000 0 0x80000000>;
- };
-
- can20m: can20m {
- compatible = "fixed-clock";
- #clock-cells = <0>;
- clock-frequency = <20000000>;
- clock-output-names = "can20m";
- };
-
- gpio-keys {
- compatible = "gpio-keys";
-
- key-user-pb {
- label = "user_pb";
- gpios = <&gpio 2 GPIO_ACTIVE_LOW>;
- linux,code = <BTN_0>;
- };
-
- key-user-pb1x {
- label = "user_pb1x";
- linux,code = <BTN_1>;
- interrupt-parent = <&gsc>;
- interrupts = <0>;
- };
-
- key-erased {
- label = "key_erased";
- linux,code = <BTN_2>;
- interrupt-parent = <&gsc>;
- interrupts = <1>;
- };
-
- key-eeprom-wp {
- label = "eeprom_wp";
- linux,code = <BTN_3>;
- interrupt-parent = <&gsc>;
- interrupts = <2>;
- };
-
- key-tamper {
- label = "tamper";
- linux,code = <BTN_4>;
- interrupt-parent = <&gsc>;
- interrupts = <5>;
- };
-
- switch-hold {
- label = "switch_hold";
- linux,code = <BTN_5>;
- interrupt-parent = <&gsc>;
- interrupts = <7>;
- };
- };
-
- led-controller {
- compatible = "gpio-leds";
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_gpio_leds>;
-
- led-0 {
- function = LED_FUNCTION_STATUS;
- color = <LED_COLOR_ID_GREEN>;
- label = "panel1";
- gpios = <&gpio3 21 GPIO_ACTIVE_LOW>;
- default-state = "off";
- };
-
- led-1 {
- function = LED_FUNCTION_STATUS;
- color = <LED_COLOR_ID_GREEN>;
- label = "panel2";
- gpios = <&gpio3 23 GPIO_ACTIVE_LOW>;
- default-state = "off";
- };
-
- led-2 {
- function = LED_FUNCTION_STATUS;
- color = <LED_COLOR_ID_GREEN>;
- label = "panel3";
- gpios = <&gpio3 22 GPIO_ACTIVE_LOW>;
- default-state = "off";
- };
-
- led-3 {
- function = LED_FUNCTION_STATUS;
- color = <LED_COLOR_ID_GREEN>;
- label = "panel4";
- gpios = <&gpio3 20 GPIO_ACTIVE_LOW>;
- default-state = "off";
- };
-
- led-4 {
- function = LED_FUNCTION_STATUS;
- color = <LED_COLOR_ID_GREEN>;
- label = "panel5";
- gpios = <&gpio3 25 GPIO_ACTIVE_LOW>;
- default-state = "off";
- };
- };
-
- pps {
- compatible = "pps-gpio";
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_pps>;
- gpios = <&gpio3 24 GPIO_ACTIVE_HIGH>;
- status = "okay";
- };
-
- reg_3p3v: regulator-3p3v {
- compatible = "regulator-fixed";
- regulator-name = "3P3V";
- regulator-min-microvolt = <3300000>;
- regulator-max-microvolt = <3300000>;
- regulator-always-on;
- };
-
- reg_usb1_vbus: regulator-usb1 {
- compatible = "regulator-fixed";
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_reg_usb1>;
- regulator-name = "usb_usb1_vbus";
- gpio = <&gpio2 7 GPIO_ACTIVE_HIGH>;
- enable-active-high;
- regulator-min-microvolt = <5000000>;
- regulator-max-microvolt = <5000000>;
- };
-
- reg_wifi: regulator-wifi {
- compatible = "regulator-fixed";
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_reg_wl>;
- regulator-name = "wifi";
- gpio = <&gpio2 19 GPIO_ACTIVE_HIGH>;
- enable-active-high;
- startup-delay-us = <100>;
- regulator-min-microvolt = <3300000>;
- regulator-max-microvolt = <3300000>;
- };
-};
-
-&A53_0 {
- cpu-supply = <&buck2>;
-};
-
-&A53_1 {
- cpu-supply = <&buck2>;
-};
-
-&A53_2 {
- cpu-supply = <&buck2>;
-};
-
-&A53_3 {
- cpu-supply = <&buck2>;
-};
-
-&ddrc {
- operating-points-v2 = <&ddrc_opp_table>;
-
- ddrc_opp_table: opp-table {
- compatible = "operating-points-v2";
-
- opp-25M {
- opp-hz = /bits/ 64 <25000000>;
- };
-
- opp-100M {
- opp-hz = /bits/ 64 <100000000>;
- };
-
- opp-750M {
- opp-hz = /bits/ 64 <750000000>;
- };
- };
-};
-
-&ecspi1 {
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_spi1>;
- cs-gpios = <&gpio5 9 GPIO_ACTIVE_LOW>;
- status = "okay";
-
- can@0 {
- compatible = "microchip,mcp2515";
- reg = <0>;
- clocks = <&can20m>;
- interrupt-parent = <&gpio2>;
- interrupts = <3 IRQ_TYPE_LEVEL_LOW>;
- spi-max-frequency = <10000000>;
- };
-};
-
-&disp_blk_ctrl {
- status = "disabled";
-};
-
-/* off-board header */
-&ecspi2 {
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_spi2>;
- cs-gpios = <&gpio5 13 GPIO_ACTIVE_LOW>;
- status = "okay";
-};
-
-&fec1 {
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_fec1>;
- phy-mode = "rgmii-id";
- phy-handle = <ðphy0>;
- local-mac-address = [00 00 00 00 00 00];
- status = "okay";
-
- mdio {
- #address-cells = <1>;
- #size-cells = <0>;
-
- ethphy0: ethernet-phy@0 {
- compatible = "ethernet-phy-ieee802.3-c22";
- reg = <0>;
- ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_00_NS>;
- ti,tx-internal-delay = <DP83867_RGMIIDCTL_2_00_NS>;
- tx-fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>;
- rx-fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>;
- };
- };
-};
-
-&gpio1 {
- gpio-line-names = "", "", "", "", "", "", "", "",
- "m2_pwr_en", "", "", "", "", "m2_reset", "", "m2_wdis#",
- "", "", "", "", "", "", "", "",
- "", "", "", "", "", "", "", "";
-};
-
-&gpio2 {
- gpio-line-names = "", "", "", "", "", "", "", "",
- "uart2_en#", "", "", "", "", "", "", "",
- "", "", "", "", "", "", "", "",
- "", "", "", "", "", "", "", "";
-};
-
-&gpio3 {
- gpio-line-names = "", "m2_gdis#", "", "", "", "", "", "m2_off#",
- "", "", "", "", "", "", "", "",
- "", "", "", "", "", "", "", "",
- "", "", "", "", "", "", "", "";
-};
-
-&gpio4 {
- gpio-line-names = "", "", "", "", "", "", "", "",
- "", "", "", "", "", "", "", "",
- "", "", "", "", "", "app_gpio1", "vdd_4p0_en", "uart1_rs485",
- "", "uart1_term", "uart1_half", "app_gpio2",
- "mipi_gpio1", "", "", "";
-};
-
-&gpio5 {
- gpio-line-names = "", "", "", "mipi_gpio4",
- "mipi_gpio3", "mipi_gpio2", "", "",
- "", "", "", "", "", "", "", "",
- "", "", "", "", "", "", "", "",
- "", "", "", "", "", "", "", "";
-};
-
-&gpu {
- status = "disabled";
-};
-
-&i2c1 {
- clock-frequency = <100000>;
- pinctrl-names = "default", "gpio";
- pinctrl-0 = <&pinctrl_i2c1>;
- pinctrl-1 = <&pinctrl_i2c1_gpio>;
- scl-gpios = <&gpio5 14 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
- sda-gpios = <&gpio5 15 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
- status = "okay";
-
- gsc: gsc@20 {
- compatible = "gw,gsc";
- reg = <0x20>;
- pinctrl-0 = <&pinctrl_gsc>;
- interrupt-parent = <&gpio2>;
- interrupts = <6 IRQ_TYPE_EDGE_FALLING>;
- interrupt-controller;
- #interrupt-cells = <1>;
-
- adc {
- compatible = "gw,gsc-adc";
- #address-cells = <1>;
- #size-cells = <0>;
-
- channel@6 {
- gw,mode = <0>;
- reg = <0x06>;
- label = "temp";
- };
-
- channel@8 {
- gw,mode = <1>;
- reg = <0x08>;
- label = "vdd_bat";
- };
-
- channel@82 {
- gw,mode = <2>;
- reg = <0x82>;
- label = "vin";
- gw,voltage-divider-ohms = <22100 1000>;
- gw,voltage-offset-microvolt = <700000>;
- };
-
- channel@84 {
- gw,mode = <2>;
- reg = <0x84>;
- label = "vin_4p0";
- gw,voltage-divider-ohms = <10000 10000>;
- };
-
- channel@86 {
- gw,mode = <2>;
- reg = <0x86>;
- label = "vdd_3p3";
- gw,voltage-divider-ohms = <10000 10000>;
- };
-
- channel@88 {
- gw,mode = <2>;
- reg = <0x88>;
- label = "vdd_0p9";
- };
-
- channel@8c {
- gw,mode = <2>;
- reg = <0x8c>;
- label = "vdd_soc";
- };
-
- channel@8e {
- gw,mode = <2>;
- reg = <0x8e>;
- label = "vdd_arm";
- };
-
- channel@90 {
- gw,mode = <2>;
- reg = <0x90>;
- label = "vdd_1p8";
- };
-
- channel@92 {
- gw,mode = <2>;
- reg = <0x92>;
- label = "vdd_dram";
- };
-
- channel@98 {
- gw,mode = <2>;
- reg = <0x98>;
- label = "vdd_1p0";
- };
-
- channel@9a {
- gw,mode = <2>;
- reg = <0x9a>;
- label = "vdd_2p5";
- gw,voltage-divider-ohms = <10000 10000>;
- };
-
- channel@9c {
- gw,mode = <2>;
- reg = <0x9c>;
- label = "vdd_5p0";
- gw,voltage-divider-ohms = <10000 10000>;
- };
-
- channel@a2 {
- gw,mode = <2>;
- reg = <0xa2>;
- label = "vdd_gsc";
- gw,voltage-divider-ohms = <10000 10000>;
- };
- };
- };
-
- gpio: gpio@23 {
- compatible = "nxp,pca9555";
- reg = <0x23>;
- gpio-controller;
- #gpio-cells = <2>;
- interrupt-parent = <&gsc>;
- interrupts = <4>;
- };
-
- pmic@4b {
- compatible = "rohm,bd71847";
- reg = <0x4b>;
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_pmic>;
- interrupt-parent = <&gpio3>;
- interrupts = <8 IRQ_TYPE_LEVEL_LOW>;
- rohm,reset-snvs-powered;
- #clock-cells = <0>;
- clocks = <&osc_32k 0>;
- clock-output-names = "clk-32k-out";
-
- regulators {
- /* vdd_soc: 0.805-0.900V (typ=0.8V) */
- BUCK1 {
- regulator-name = "buck1";
- regulator-min-microvolt = <700000>;
- regulator-max-microvolt = <1300000>;
- regulator-boot-on;
- regulator-always-on;
- regulator-ramp-delay = <1250>;
- };
-
- /* vdd_arm: 0.805-1.0V (typ=0.9V) */
- buck2: BUCK2 {
- regulator-name = "buck2";
- regulator-min-microvolt = <700000>;
- regulator-max-microvolt = <1300000>;
- regulator-boot-on;
- regulator-always-on;
- regulator-ramp-delay = <1250>;
- rohm,dvs-run-voltage = <1000000>;
- rohm,dvs-idle-voltage = <900000>;
- };
-
- /* vdd_0p9: 0.805-1.0V (typ=0.9V) */
- BUCK3 {
- regulator-name = "buck3";
- regulator-min-microvolt = <700000>;
- regulator-max-microvolt = <1350000>;
- regulator-boot-on;
- regulator-always-on;
- };
-
- /* vdd_3p3 */
- BUCK4 {
- regulator-name = "buck4";
- regulator-min-microvolt = <3000000>;
- regulator-max-microvolt = <3300000>;
- regulator-boot-on;
- regulator-always-on;
- };
-
- /* vdd_1p8 */
- BUCK5 {
- regulator-name = "buck5";
- regulator-min-microvolt = <1605000>;
- regulator-max-microvolt = <1995000>;
- regulator-boot-on;
- regulator-always-on;
- };
-
- /* vdd_dram */
- BUCK6 {
- regulator-name = "buck6";
- regulator-min-microvolt = <800000>;
- regulator-max-microvolt = <1400000>;
- regulator-boot-on;
- regulator-always-on;
- };
-
- /* nvcc_snvs_1p8 */
- LDO1 {
- regulator-name = "ldo1";
- regulator-min-microvolt = <1600000>;
- regulator-max-microvolt = <1900000>;
- regulator-boot-on;
- regulator-always-on;
- };
-
- /* vdd_snvs_0p8 */
- LDO2 {
- regulator-name = "ldo2";
- regulator-min-microvolt = <800000>;
- regulator-max-microvolt = <900000>;
- regulator-boot-on;
- regulator-always-on;
- };
-
- /* vdda_1p8 */
- LDO3 {
- regulator-name = "ldo3";
- regulator-min-microvolt = <1800000>;
- regulator-max-microvolt = <3300000>;
- regulator-boot-on;
- regulator-always-on;
- };
-
- LDO4 {
- regulator-name = "ldo4";
- regulator-min-microvolt = <900000>;
- regulator-max-microvolt = <1800000>;
- regulator-boot-on;
- regulator-always-on;
- };
-
- LDO6 {
- regulator-name = "ldo6";
- regulator-min-microvolt = <900000>;
- regulator-max-microvolt = <1800000>;
- regulator-boot-on;
- regulator-always-on;
- };
- };
- };
-
- eeprom@50 {
- compatible = "atmel,24c02";
- reg = <0x50>;
- pagesize = <16>;
- };
-
- eeprom@51 {
- compatible = "atmel,24c02";
- reg = <0x51>;
- pagesize = <16>;
- };
-
- eeprom@52 {
- compatible = "atmel,24c02";
- reg = <0x52>;
- pagesize = <16>;
- };
-
- eeprom@53 {
- compatible = "atmel,24c02";
- reg = <0x53>;
- pagesize = <16>;
- };
-
- rtc@68 {
- compatible = "dallas,ds1672";
- reg = <0x68>;
- };
-};
-
-&i2c2 {
- clock-frequency = <400000>;
- pinctrl-names = "default", "gpio";
- pinctrl-0 = <&pinctrl_i2c2>;
- pinctrl-1 = <&pinctrl_i2c2_gpio>;
- scl-gpios = <&gpio5 16 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
- sda-gpios = <&gpio5 17 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
- status = "okay";
-
- accelerometer@19 {
- compatible = "st,lis2de12";
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_accel>;
- reg = <0x19>;
- st,drdy-int-pin = <1>;
- interrupt-parent = <&gpio1>;
- interrupts = <12 IRQ_TYPE_LEVEL_LOW>;
- interrupt-names = "INT1";
- };
-};
-
-/* off-board header */
-&i2c3 {
- clock-frequency = <400000>;
- pinctrl-names = "default", "gpio";
- pinctrl-0 = <&pinctrl_i2c3>;
- pinctrl-1 = <&pinctrl_i2c3_gpio>;
- scl-gpios = <&gpio5 18 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
- sda-gpios = <&gpio5 19 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
- status = "okay";
-};
-
-/* off-board header */
-&i2c4 {
- clock-frequency = <400000>;
- pinctrl-names = "default", "gpio";
- pinctrl-0 = <&pinctrl_i2c4>;
- pinctrl-1 = <&pinctrl_i2c4_gpio>;
- scl-gpios = <&gpio5 20 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
- sda-gpios = <&gpio5 21 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
- status = "okay";
-};
-
-&pgc_gpumix {
- status = "disabled";
-};
-
-/* off-board header */
-&sai3 {
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_sai3>;
- assigned-clocks = <&clk IMX8MN_CLK_SAI3>;
- assigned-clock-parents = <&clk IMX8MN_AUDIO_PLL1_OUT>;
- assigned-clock-rates = <24576000>;
- status = "okay";
-};
-
-/* RS232/RS485/RS422 selectable */
-&uart1 {
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_uart1>, <&pinctrl_uart1_gpio>;
- status = "okay";
-};
-
-/* RS232 console */
-&uart2 {
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_uart2>;
- status = "okay";
-};
-
-/* bluetooth HCI */
-&uart3 {
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_uart3>, <&pinctrl_uart3_gpio>;
- rts-gpios = <&gpio2 1 GPIO_ACTIVE_LOW>;
- cts-gpios = <&gpio2 0 GPIO_ACTIVE_LOW>;
- uart-has-rtscts;
- status = "okay";
-
- bluetooth {
- compatible = "brcm,bcm4330-bt";
- shutdown-gpios = <&gpio2 12 GPIO_ACTIVE_HIGH>;
- };
-};
-
-/* LTE Cat M1/NB1/EGPRS modem or GPS (loading option) */
-&uart4 {
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_uart4>;
- status = "okay";
-};
-
-&usbotg1 {
- dr_mode = "host";
- vbus-supply = <®_usb1_vbus>;
- disable-over-current;
- status = "okay";
-};
-
-/* SDIO WiFi */
-&usdhc2 {
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_usdhc2>;
- bus-width = <4>;
- non-removable;
- vmmc-supply = <®_wifi>;
- status = "okay";
-};
-
-/* eMMC */
-&usdhc3 {
- pinctrl-names = "default", "state_100mhz", "state_200mhz";
- pinctrl-0 = <&pinctrl_usdhc3>;
- pinctrl-1 = <&pinctrl_usdhc3_100mhz>;
- pinctrl-2 = <&pinctrl_usdhc3_200mhz>;
- bus-width = <8>;
- non-removable;
- status = "okay";
-};
-
-&wdog1 {
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_wdog>;
- fsl,ext-reset-output;
- status = "okay";
-};
-
-&iomuxc {
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_hog>;
-
- pinctrl_hog: hoggrp {
- fsl,pins = <
- MX8MN_IOMUXC_NAND_CE0_B_GPIO3_IO1 0x40000159 /* M2_GDIS# */
- MX8MN_IOMUXC_GPIO1_IO08_GPIO1_IO8 0x40000041 /* M2_PWR_EN */
- MX8MN_IOMUXC_GPIO1_IO13_GPIO1_IO13 0x40000041 /* M2_RESET */
- MX8MN_IOMUXC_NAND_DATA01_GPIO3_IO7 0x40000119 /* M2_OFF# */
- MX8MN_IOMUXC_GPIO1_IO15_GPIO1_IO15 0x40000159 /* M2_WDIS# */
- MX8MN_IOMUXC_SAI2_RXFS_GPIO4_IO21 0x40000041 /* APP GPIO1 */
- MX8MN_IOMUXC_SAI2_RXC_GPIO4_IO22 0x40000041 /* VDD_4P0_EN */
- MX8MN_IOMUXC_SAI2_MCLK_GPIO4_IO27 0x40000041 /* APP GPIO2 */
- MX8MN_IOMUXC_SD1_DATA6_GPIO2_IO8 0x40000041 /* UART2_EN# */
- MX8MN_IOMUXC_SAI3_RXFS_GPIO4_IO28 0x40000041 /* MIPI_GPIO1 */
- MX8MN_IOMUXC_SPDIF_EXT_CLK_GPIO5_IO5 0x40000041 /* MIPI_GPIO2 */
- MX8MN_IOMUXC_SPDIF_RX_GPIO5_IO4 0x40000041 /* MIPI_GPIO3/PWM2 */
- MX8MN_IOMUXC_SPDIF_TX_GPIO5_IO3 0x40000041 /* MIPI_GPIO4/PWM3 */
- >;
- };
-
- pinctrl_accel: accelgrp {
- fsl,pins = <
- MX8MN_IOMUXC_GPIO1_IO12_GPIO1_IO12 0x159
- >;
- };
-
- pinctrl_fec1: fec1grp {
- fsl,pins = <
- MX8MN_IOMUXC_ENET_MDC_ENET1_MDC 0x3
- MX8MN_IOMUXC_ENET_MDIO_ENET1_MDIO 0x3
- MX8MN_IOMUXC_ENET_TD3_ENET1_RGMII_TD3 0x1f
- MX8MN_IOMUXC_ENET_TD2_ENET1_RGMII_TD2 0x1f
- MX8MN_IOMUXC_ENET_TD1_ENET1_RGMII_TD1 0x1f
- MX8MN_IOMUXC_ENET_TD0_ENET1_RGMII_TD0 0x1f
- MX8MN_IOMUXC_ENET_RD3_ENET1_RGMII_RD3 0x91
- MX8MN_IOMUXC_ENET_RD2_ENET1_RGMII_RD2 0x91
- MX8MN_IOMUXC_ENET_RD1_ENET1_RGMII_RD1 0x91
- MX8MN_IOMUXC_ENET_RD0_ENET1_RGMII_RD0 0x91
- MX8MN_IOMUXC_ENET_TXC_ENET1_RGMII_TXC 0x1f
- MX8MN_IOMUXC_ENET_RXC_ENET1_RGMII_RXC 0x91
- MX8MN_IOMUXC_ENET_RX_CTL_ENET1_RGMII_RX_CTL 0x91
- MX8MN_IOMUXC_ENET_TX_CTL_ENET1_RGMII_TX_CTL 0x1f
- MX8MN_IOMUXC_GPIO1_IO10_GPIO1_IO10 0x19 /* RST# */
- MX8MN_IOMUXC_GPIO1_IO11_GPIO1_IO11 0x19 /* IRQ# */
- >;
- };
-
- pinctrl_gsc: gscgrp {
- fsl,pins = <
- MX8MN_IOMUXC_SD1_DATA4_GPIO2_IO6 0x40
- >;
- };
-
- pinctrl_i2c1: i2c1grp {
- fsl,pins = <
- MX8MN_IOMUXC_I2C1_SCL_I2C1_SCL 0x400001c3
- MX8MN_IOMUXC_I2C1_SDA_I2C1_SDA 0x400001c3
- >;
- };
-
- pinctrl_i2c1_gpio: i2c1gpiogrp {
- fsl,pins = <
- MX8MN_IOMUXC_I2C1_SCL_GPIO5_IO14 0x400001c3
- MX8MN_IOMUXC_I2C1_SDA_GPIO5_IO15 0x400001c3
- >;
- };
-
- pinctrl_i2c2: i2c2grp {
- fsl,pins = <
- MX8MN_IOMUXC_I2C2_SCL_I2C2_SCL 0x400001c3
- MX8MN_IOMUXC_I2C2_SDA_I2C2_SDA 0x400001c3
- >;
- };
-
- pinctrl_i2c2_gpio: i2c2gpiogrp {
- fsl,pins = <
- MX8MN_IOMUXC_I2C2_SCL_GPIO5_IO16 0x400001c3
- MX8MN_IOMUXC_I2C2_SDA_GPIO5_IO17 0x400001c3
- >;
- };
-
- pinctrl_i2c3: i2c3grp {
- fsl,pins = <
- MX8MN_IOMUXC_I2C3_SCL_I2C3_SCL 0x400001c3
- MX8MN_IOMUXC_I2C3_SDA_I2C3_SDA 0x400001c3
- >;
- };
-
- pinctrl_i2c3_gpio: i2c3gpiogrp {
- fsl,pins = <
- MX8MN_IOMUXC_I2C3_SCL_GPIO5_IO18 0x400001c3
- MX8MN_IOMUXC_I2C3_SDA_GPIO5_IO19 0x400001c3
- >;
- };
-
- pinctrl_i2c4: i2c4grp {
- fsl,pins = <
- MX8MN_IOMUXC_I2C4_SCL_I2C4_SCL 0x400001c3
- MX8MN_IOMUXC_I2C4_SDA_I2C4_SDA 0x400001c3
- >;
- };
-
- pinctrl_i2c4_gpio: i2c4gpiogrp {
- fsl,pins = <
- MX8MN_IOMUXC_I2C4_SCL_GPIO5_IO20 0x400001c3
- MX8MN_IOMUXC_I2C4_SDA_GPIO5_IO21 0x400001c3
- >;
- };
-
- pinctrl_gpio_leds: gpioledgrp {
- fsl,pins = <
- MX8MN_IOMUXC_SAI5_RXD0_GPIO3_IO21 0x19
- MX8MN_IOMUXC_SAI5_RXD2_GPIO3_IO23 0x19
- MX8MN_IOMUXC_SAI5_RXD1_GPIO3_IO22 0x19
- MX8MN_IOMUXC_SAI5_RXC_GPIO3_IO20 0x19
- MX8MN_IOMUXC_SAI5_MCLK_GPIO3_IO25 0x19
- >;
- };
-
- pinctrl_pmic: pmicgrp {
- fsl,pins = <
- MX8MN_IOMUXC_NAND_DATA02_GPIO3_IO8 0x41
- >;
- };
-
- pinctrl_pps: ppsgrp {
- fsl,pins = <
- MX8MN_IOMUXC_SAI5_RXD3_GPIO3_IO24 0x141 /* PPS */
- >;
- };
-
- pinctrl_reg_wl: regwlgrp {
- fsl,pins = <
- MX8MN_IOMUXC_SD2_RESET_B_GPIO2_IO19 0x41 /* WLAN_WLON */
- >;
- };
-
- pinctrl_reg_usb1: regusb1grp {
- fsl,pins = <
- MX8MN_IOMUXC_SD1_DATA5_GPIO2_IO7 0x41
- >;
- };
-
- pinctrl_sai3: sai3grp {
- fsl,pins = <
- MX8MN_IOMUXC_SAI3_MCLK_SAI3_MCLK 0xd6
- MX8MN_IOMUXC_SAI3_RXD_SAI3_RX_DATA0 0xd6
- MX8MN_IOMUXC_SAI3_TXC_SAI3_TX_BCLK 0xd6
- MX8MN_IOMUXC_SAI3_TXD_SAI3_TX_DATA0 0xd6
- MX8MN_IOMUXC_SAI3_TXFS_SAI3_TX_SYNC 0xd6
- >;
- };
-
- pinctrl_spi1: spi1grp {
- fsl,pins = <
- MX8MN_IOMUXC_ECSPI1_SCLK_ECSPI1_SCLK 0x82
- MX8MN_IOMUXC_ECSPI1_MOSI_ECSPI1_MOSI 0x82
- MX8MN_IOMUXC_ECSPI1_MISO_ECSPI1_MISO 0x82
- MX8MN_IOMUXC_ECSPI1_SS0_GPIO5_IO9 0x40
- MX8MN_IOMUXC_SD1_DATA1_GPIO2_IO3 0x140 /* CAN_IRQ# */
- >;
- };
-
- pinctrl_spi2: spi2grp {
- fsl,pins = <
- MX8MN_IOMUXC_ECSPI2_SCLK_ECSPI2_SCLK 0x82
- MX8MN_IOMUXC_ECSPI2_MOSI_ECSPI2_MOSI 0x82
- MX8MN_IOMUXC_ECSPI2_MISO_ECSPI2_MISO 0x82
- MX8MN_IOMUXC_ECSPI2_SS0_GPIO5_IO13 0x40 /* SS0 */
- >;
- };
-
- pinctrl_uart1: uart1grp {
- fsl,pins = <
- MX8MN_IOMUXC_UART1_RXD_UART1_DCE_RX 0x140
- MX8MN_IOMUXC_UART1_TXD_UART1_DCE_TX 0x140
- >;
- };
-
- pinctrl_uart1_gpio: uart1gpiogrp {
- fsl,pins = <
- MX8MN_IOMUXC_SAI2_TXD0_GPIO4_IO26 0x40000110 /* HALF */
- MX8MN_IOMUXC_SAI2_TXC_GPIO4_IO25 0x40000110 /* TERM */
- MX8MN_IOMUXC_SAI2_RXD0_GPIO4_IO23 0x40000110 /* RS485 */
- >;
- };
-
- pinctrl_uart2: uart2grp {
- fsl,pins = <
- MX8MN_IOMUXC_UART2_RXD_UART2_DCE_RX 0x140
- MX8MN_IOMUXC_UART2_TXD_UART2_DCE_TX 0x140
- >;
- };
-
- pinctrl_uart3_gpio: uart3_gpiogrp {
- fsl,pins = <
- MX8MN_IOMUXC_SD2_CD_B_GPIO2_IO12 0x41 /* BT_EN# */
- >;
- };
-
- pinctrl_uart3: uart3grp {
- fsl,pins = <
- MX8MN_IOMUXC_UART3_RXD_UART3_DCE_RX 0x140
- MX8MN_IOMUXC_UART3_TXD_UART3_DCE_TX 0x140
- MX8MN_IOMUXC_SD1_CLK_GPIO2_IO0 0x140 /* CTS */
- MX8MN_IOMUXC_SD1_CMD_GPIO2_IO1 0x140 /* RTS */
- >;
- };
-
- pinctrl_uart4: uart4grp {
- fsl,pins = <
- MX8MN_IOMUXC_UART4_RXD_UART4_DCE_RX 0x140
- MX8MN_IOMUXC_UART4_TXD_UART4_DCE_TX 0x140
- MX8MN_IOMUXC_GPIO1_IO06_GPIO1_IO6 0x141 /* GNSS_GASP */
- >;
- };
-
- pinctrl_usdhc2: usdhc2grp {
- fsl,pins = <
- MX8MN_IOMUXC_SD2_CLK_USDHC2_CLK 0x190
- MX8MN_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d0
- MX8MN_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d0
- MX8MN_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d0
- MX8MN_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d0
- MX8MN_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d0
- >;
- };
-
- pinctrl_usdhc3: usdhc3grp {
- fsl,pins = <
- MX8MN_IOMUXC_NAND_WE_B_USDHC3_CLK 0x190
- MX8MN_IOMUXC_NAND_WP_B_USDHC3_CMD 0x1d0
- MX8MN_IOMUXC_NAND_DATA04_USDHC3_DATA0 0x1d0
- MX8MN_IOMUXC_NAND_DATA05_USDHC3_DATA1 0x1d0
- MX8MN_IOMUXC_NAND_DATA06_USDHC3_DATA2 0x1d0
- MX8MN_IOMUXC_NAND_DATA07_USDHC3_DATA3 0x1d0
- MX8MN_IOMUXC_NAND_RE_B_USDHC3_DATA4 0x1d0
- MX8MN_IOMUXC_NAND_CE2_B_USDHC3_DATA5 0x1d0
- MX8MN_IOMUXC_NAND_CE3_B_USDHC3_DATA6 0x1d0
- MX8MN_IOMUXC_NAND_CLE_USDHC3_DATA7 0x1d0
- MX8MN_IOMUXC_NAND_CE1_B_USDHC3_STROBE 0x190
- >;
- };
-
- pinctrl_usdhc3_100mhz: usdhc3-100mhzgrp {
- fsl,pins = <
- MX8MN_IOMUXC_NAND_WE_B_USDHC3_CLK 0x194
- MX8MN_IOMUXC_NAND_WP_B_USDHC3_CMD 0x1d4
- MX8MN_IOMUXC_NAND_DATA04_USDHC3_DATA0 0x1d4
- MX8MN_IOMUXC_NAND_DATA05_USDHC3_DATA1 0x1d4
- MX8MN_IOMUXC_NAND_DATA06_USDHC3_DATA2 0x1d4
- MX8MN_IOMUXC_NAND_DATA07_USDHC3_DATA3 0x1d4
- MX8MN_IOMUXC_NAND_RE_B_USDHC3_DATA4 0x1d4
- MX8MN_IOMUXC_NAND_CE2_B_USDHC3_DATA5 0x1d4
- MX8MN_IOMUXC_NAND_CE3_B_USDHC3_DATA6 0x1d4
- MX8MN_IOMUXC_NAND_CLE_USDHC3_DATA7 0x1d4
- MX8MN_IOMUXC_NAND_CE1_B_USDHC3_STROBE 0x194
- >;
- };
-
- pinctrl_usdhc3_200mhz: usdhc3-200mhzgrp {
- fsl,pins = <
- MX8MN_IOMUXC_NAND_WE_B_USDHC3_CLK 0x196
- MX8MN_IOMUXC_NAND_WP_B_USDHC3_CMD 0x1d6
- MX8MN_IOMUXC_NAND_DATA04_USDHC3_DATA0 0x1d6
- MX8MN_IOMUXC_NAND_DATA05_USDHC3_DATA1 0x1d6
- MX8MN_IOMUXC_NAND_DATA06_USDHC3_DATA2 0x1d6
- MX8MN_IOMUXC_NAND_DATA07_USDHC3_DATA3 0x1d6
- MX8MN_IOMUXC_NAND_RE_B_USDHC3_DATA4 0x1d6
- MX8MN_IOMUXC_NAND_CE2_B_USDHC3_DATA5 0x1d6
- MX8MN_IOMUXC_NAND_CE3_B_USDHC3_DATA6 0x1d6
- MX8MN_IOMUXC_NAND_CLE_USDHC3_DATA7 0x1d6
- MX8MN_IOMUXC_NAND_CE1_B_USDHC3_STROBE 0x196
- >;
- };
-
- pinctrl_wdog: wdoggrp {
- fsl,pins = <
- MX8MN_IOMUXC_GPIO1_IO02_WDOG1_WDOG_B 0xc6
- >;
- };
-};
diff --git a/arch/arm/dts/imx8mn-venice.dts b/arch/arm/dts/imx8mn-venice.dts
deleted file mode 100644
index 9e31b37..0000000
--- a/arch/arm/dts/imx8mn-venice.dts
+++ /dev/null
@@ -1,169 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * Copyright 2022 Gateworks Corporation
- */
-
-/dts-v1/;
-
-#include "imx8mn.dtsi"
-
-/ {
- model = "Gateworks Venice i.MX8MM board";
- compatible = "gw,imx8mn-venice", "fsl,imx8mn";
-
- chosen {
- stdout-path = &uart2;
- };
-
- memory@40000000 {
- device_type = "memory";
- reg = <0x0 0x40000000 0 0x80000000>;
- };
-};
-
-&i2c1 {
- clock-frequency = <100000>;
- pinctrl-names = "default", "gpio";
- pinctrl-0 = <&pinctrl_i2c1>;
- pinctrl-1 = <&pinctrl_i2c1_gpio>;
- scl-gpios = <&gpio5 14 GPIO_ACTIVE_HIGH>;
- sda-gpios = <&gpio5 15 GPIO_ACTIVE_HIGH>;
- status = "okay";
-
- gsc: gsc@20 {
- compatible = "gw,gsc";
- reg = <0x20>;
- #address-cells = <1>;
- #size-cells = <0>;
- };
-
- eeprom@51 {
- compatible = "atmel,24c02";
- reg = <0x51>;
- pagesize = <16>;
- };
-};
-
-&i2c2 {
- clock-frequency = <400000>;
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_i2c2>;
- status = "okay";
-
- eeprom@52 {
- compatible = "atmel,24c32";
- reg = <0x52>;
- pagesize = <32>;
- };
-};
-
-/* console */
-&uart2 {
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_uart2>;
- status = "okay";
-};
-
-/* eMMC */
-&usdhc3 {
- assigned-clocks = <&clk IMX8MN_CLK_USDHC3_ROOT>;
- assigned-clock-rates = <400000000>;
- pinctrl-names = "default", "state_100mhz", "state_200mhz";
- pinctrl-0 = <&pinctrl_usdhc3>;
- pinctrl-1 = <&pinctrl_usdhc3_100mhz>;
- pinctrl-2 = <&pinctrl_usdhc3_200mhz>;
- bus-width = <8>;
- non-removable;
- status = "okay";
-};
-
-&wdog1 {
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_wdog>;
- fsl,ext-reset-output;
- status = "okay";
-};
-
-&iomuxc {
- pinctrl_i2c1: i2c1grp {
- fsl,pins = <
- MX8MN_IOMUXC_I2C1_SCL_I2C1_SCL 0x400001c3
- MX8MN_IOMUXC_I2C1_SDA_I2C1_SDA 0x400001c3
- >;
- };
-
- pinctrl_i2c1_gpio: i2c1grp-gpio-grp {
- fsl,pins = <
- MX8MN_IOMUXC_I2C1_SCL_GPIO5_IO14 0x400001c3
- MX8MN_IOMUXC_I2C1_SDA_GPIO5_IO15 0x400001c3
- >;
- };
-
- pinctrl_i2c2: i2c2grp {
- fsl,pins = <
- MX8MN_IOMUXC_I2C2_SCL_I2C2_SCL 0x400001c3
- MX8MN_IOMUXC_I2C2_SDA_I2C2_SDA 0x400001c3
- >;
- };
-
- pinctrl_uart2: uart2grp {
- fsl,pins = <
- MX8MN_IOMUXC_UART2_RXD_UART2_DCE_RX 0x140
- MX8MN_IOMUXC_UART2_TXD_UART2_DCE_TX 0x140
- >;
- };
-
- pinctrl_usdhc3: usdhc3grp {
- fsl,pins = <
- MX8MN_IOMUXC_NAND_WE_B_USDHC3_CLK 0x190
- MX8MN_IOMUXC_NAND_WP_B_USDHC3_CMD 0x1d0
- MX8MN_IOMUXC_NAND_DATA04_USDHC3_DATA0 0x1d0
- MX8MN_IOMUXC_NAND_DATA05_USDHC3_DATA1 0x1d0
- MX8MN_IOMUXC_NAND_DATA06_USDHC3_DATA2 0x1d0
- MX8MN_IOMUXC_NAND_DATA07_USDHC3_DATA3 0x1d0
- MX8MN_IOMUXC_NAND_RE_B_USDHC3_DATA4 0x1d0
- MX8MN_IOMUXC_NAND_CE2_B_USDHC3_DATA5 0x1d0
- MX8MN_IOMUXC_NAND_CE3_B_USDHC3_DATA6 0x1d0
- MX8MN_IOMUXC_NAND_CLE_USDHC3_DATA7 0x1d0
- MX8MN_IOMUXC_NAND_CE1_B_USDHC3_STROBE 0x190
- >;
- };
-
- pinctrl_usdhc3_100mhz: usdhc3grp100mhz {
- fsl,pins = <
- MX8MN_IOMUXC_NAND_WE_B_USDHC3_CLK 0x194
- MX8MN_IOMUXC_NAND_WP_B_USDHC3_CMD 0x1d4
- MX8MN_IOMUXC_NAND_DATA04_USDHC3_DATA0 0x1d4
- MX8MN_IOMUXC_NAND_DATA05_USDHC3_DATA1 0x1d4
- MX8MN_IOMUXC_NAND_DATA06_USDHC3_DATA2 0x1d4
- MX8MN_IOMUXC_NAND_DATA07_USDHC3_DATA3 0x1d4
- MX8MN_IOMUXC_NAND_RE_B_USDHC3_DATA4 0x1d4
- MX8MN_IOMUXC_NAND_CE2_B_USDHC3_DATA5 0x1d4
- MX8MN_IOMUXC_NAND_CE3_B_USDHC3_DATA6 0x1d4
- MX8MN_IOMUXC_NAND_CLE_USDHC3_DATA7 0x1d4
- MX8MN_IOMUXC_NAND_CE1_B_USDHC3_STROBE 0x194
- >;
- };
-
- pinctrl_usdhc3_200mhz: usdhc3grp200mhz {
- fsl,pins = <
- MX8MN_IOMUXC_NAND_WE_B_USDHC3_CLK 0x196
- MX8MN_IOMUXC_NAND_WP_B_USDHC3_CMD 0x1d6
- MX8MN_IOMUXC_NAND_DATA04_USDHC3_DATA0 0x1d6
- MX8MN_IOMUXC_NAND_DATA05_USDHC3_DATA1 0x1d6
- MX8MN_IOMUXC_NAND_DATA06_USDHC3_DATA2 0x1d6
- MX8MN_IOMUXC_NAND_DATA07_USDHC3_DATA3 0x1d6
- MX8MN_IOMUXC_NAND_RE_B_USDHC3_DATA4 0x1d6
- MX8MN_IOMUXC_NAND_CE2_B_USDHC3_DATA5 0x1d6
- MX8MN_IOMUXC_NAND_CE3_B_USDHC3_DATA6 0x1d6
- MX8MN_IOMUXC_NAND_CLE_USDHC3_DATA7 0x1d6
- MX8MN_IOMUXC_NAND_CE1_B_USDHC3_STROBE 0x196
- >;
- };
-
- pinctrl_wdog: wdoggrp {
- fsl,pins = <
- MX8MN_IOMUXC_GPIO1_IO02_WDOG1_WDOG_B 0xc6
- >;
- };
-};
diff --git a/arch/arm/dts/imx8mp-beacon-kit.dts b/arch/arm/dts/imx8mp-beacon-kit.dts
deleted file mode 100644
index a080574..0000000
--- a/arch/arm/dts/imx8mp-beacon-kit.dts
+++ /dev/null
@@ -1,783 +0,0 @@
-// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
-/*
- * Copyright 2023 Logic PD, Inc dba Beacon EmbeddedWorks
- */
-
-/dts-v1/;
-
-#include <dt-bindings/usb/pd.h>
-#include <dt-bindings/phy/phy-imx8-pcie.h>
-#include "imx8mp.dtsi"
-#include "imx8mp-beacon-som.dtsi"
-
-/ {
- model = "Beacon EmbeddedWorks i.MX8MPlus Development kit";
- compatible = "beacon,imx8mp-beacon-kit", "fsl,imx8mp";
-
- aliases {
- ethernet0 = &eqos;
- ethernet1 = &fec;
- };
-
- chosen {
- stdout-path = &uart2;
- };
-
- clk_xtal25: clock-xtal25 {
- compatible = "fixed-clock";
- #clock-cells = <0>;
- clock-frequency = <25000000>;
- };
-
- connector {
- compatible = "usb-c-connector";
- label = "USB-C";
- data-role = "dual";
-
- ports {
- #address-cells = <1>;
- #size-cells = <0>;
-
- port@0 {
- reg = <0>;
-
- hs_ep: endpoint {
- remote-endpoint = <&usb3_hs_ep>;
- };
- };
- port@1 {
- reg = <1>;
-
- ss_ep: endpoint {
- remote-endpoint = <&hd3ss3220_in_ep>;
- };
- };
- };
- };
-
- dmic_codec: dmic-codec {
- compatible = "dmic-codec";
- num-channels = <1>;
- #sound-dai-cells = <0>;
- };
-
- gpio-keys {
- compatible = "gpio-keys";
- autorepeat;
-
- button-0 {
- label = "btn0";
- linux,code = <BTN_0>;
- gpios = <&pca6416_1 12 (GPIO_ACTIVE_LOW | GPIO_PULL_UP)>;
- wakeup-source;
- };
-
- button-1 {
- label = "btn1";
- linux,code = <BTN_1>;
- gpios = <&pca6416_1 13 (GPIO_ACTIVE_LOW | GPIO_PULL_UP)>;
- wakeup-source;
- };
-
- button-2 {
- label = "btn2";
- linux,code = <BTN_2>;
- gpios = <&pca6416_1 14 (GPIO_ACTIVE_LOW | GPIO_PULL_UP)>;
- wakeup-source;
- };
-
- button-3 {
- label = "btn3";
- linux,code = <BTN_3>;
- gpios = <&pca6416_1 15 (GPIO_ACTIVE_LOW | GPIO_PULL_UP)>;
- wakeup-source;
- };
- };
-
- bridge-connector {
- compatible = "hdmi-connector";
- type = "a";
-
- port {
- hdmi_con: endpoint {
- remote-endpoint = <&adv7535_out>;
- };
- };
- };
-
- leds {
- compatible = "gpio-leds";
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_led3>;
-
- led-0 {
- label = "gen_led0";
- gpios = <&pca6416_1 4 GPIO_ACTIVE_HIGH>;
- default-state = "off";
- };
-
- led-1 {
- label = "gen_led1";
- gpios = <&pca6416_1 5 GPIO_ACTIVE_HIGH>;
- default-state = "off";
- };
-
- led-2 {
- label = "gen_led2";
- gpios = <&pca6416_1 6 GPIO_ACTIVE_HIGH>;
- default-state = "off";
- };
-
- led-3 {
- label = "heartbeat";
- gpios = <&gpio4 28 GPIO_ACTIVE_HIGH>;
- linux,default-trigger = "heartbeat";
- };
- };
-
- reg_audio: regulator-wm8962 {
- compatible = "regulator-fixed";
- regulator-name = "3v3_aud";
- regulator-min-microvolt = <3300000>;
- regulator-max-microvolt = <3300000>;
- gpio = <&pca6416_1 11 GPIO_ACTIVE_HIGH>;
- enable-active-high;
- };
-
- reg_usdhc2_vmmc: regulator-usdhc2 {
- compatible = "regulator-fixed";
- regulator-name = "VSD_3V3";
- regulator-min-microvolt = <3300000>;
- regulator-max-microvolt = <3300000>;
- gpio = <&gpio2 19 GPIO_ACTIVE_HIGH>;
- enable-active-high;
- startup-delay-us = <100>;
- off-on-delay-us = <20000>;
- };
-
- reg_usb1_host_vbus: regulator-usb1-vbus {
- compatible = "regulator-fixed";
- regulator-name = "usb1_host_vbus";
- regulator-max-microvolt = <5000000>;
- regulator-min-microvolt = <5000000>;
- gpio = <&pca6416_1 0 GPIO_ACTIVE_HIGH>;
- enable-active-high;
- };
-
- sound-adv7535 {
- compatible = "simple-audio-card";
- simple-audio-card,name = "sound-adv7535";
- simple-audio-card,format = "i2s";
-
- simple-audio-card,cpu {
- sound-dai = <&sai5>;
- system-clock-direction-out;
- };
-
- simple-audio-card,codec {
- sound-dai = <&adv_bridge>;
- };
- };
-
- sound-dmic {
- compatible = "simple-audio-card";
- simple-audio-card,name = "sound-pdm";
- simple-audio-card,format = "i2s";
- simple-audio-card,bitclock-master = <&dailink_master>;
- simple-audio-card,frame-master = <&dailink_master>;
-
- dailink_master: simple-audio-card,cpu {
- sound-dai = <&micfil>;
- };
-
- simple-audio-card,codec {
- sound-dai = <&dmic_codec>;
- };
- };
-
- sound-wm8962 {
- compatible = "simple-audio-card";
- simple-audio-card,name = "wm8962";
- simple-audio-card,format = "i2s";
- simple-audio-card,widgets = "Headphone", "Headphones",
- "Microphone", "Headset Mic",
- "Speaker", "Speaker";
- simple-audio-card,routing = "Headphones", "HPOUTL",
- "Headphones", "HPOUTR",
- "Speaker", "SPKOUTL",
- "Speaker", "SPKOUTR",
- "Headset Mic", "MICBIAS",
- "IN3R", "Headset Mic";
-
- simple-audio-card,cpu {
- sound-dai = <&sai3>;
- };
-
- simple-audio-card,codec {
- sound-dai = <&wm8962>;
- clocks = <&clk IMX8MP_CLK_IPP_DO_CLKO1>;
- frame-master;
- bitclock-master;
- };
- };
-};
-
-&audio_blk_ctrl {
- assigned-clocks = <&clk IMX8MP_AUDIO_PLL1>, <&clk IMX8MP_AUDIO_PLL2>;
- assigned-clock-rates = <393216000>, <135475200>;
-};
-
-&ecspi2 {
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_ecspi2>;
- cs-gpios = <&gpio5 13 GPIO_ACTIVE_LOW>;
- status = "okay";
-
- tpm: tpm@0 {
- compatible = "infineon,slb9670", "tcg,tpm_tis-spi";
- reg = <0>;
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_tpm>;
- reset-gpios = <&gpio4 0 GPIO_ACTIVE_LOW>;
- spi-max-frequency = <18500000>;
- };
-};
-
-&fec {
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_fec>;
- phy-mode = "rgmii-id";
- phy-handle = <ðphy1>;
- fsl,magic-packet;
- status = "okay";
-
- mdio {
- #address-cells = <1>;
- #size-cells = <0>;
-
- ethphy1: ethernet-phy@3 {
- compatible = "ethernet-phy-id0022.1640",
- "ethernet-phy-ieee802.3-c22";
- reg = <3>;
- reset-gpios = <&gpio4 18 GPIO_ACTIVE_LOW>;
- reset-assert-us = <10000>;
- reset-deassert-us = <150000>;
- interrupt-parent = <&gpio4>;
- interrupts = <2 IRQ_TYPE_LEVEL_LOW>;
- };
- };
-};
-
-&flexcan1 {
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_flexcan1>;
- status = "okay";
-};
-
-&gpio2 {
- usb-mux-hog {
- gpio-hog;
- gpios = <20 0>;
- output-low;
- line-name = "USB-C Mux En";
- };
-};
-
-&i2c2 {
- clock-frequency = <384000>;
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_i2c2>;
- status = "okay";
-
- pca6416_3: gpio@20 {
- compatible = "nxp,pcal6416";
- reg = <0x20>;
- gpio-controller;
- #gpio-cells = <2>;
- interrupt-parent = <&gpio4>;
- interrupts = <27 IRQ_TYPE_EDGE_FALLING>;
- interrupt-controller;
- #interrupt-cells = <2>;
- };
-
- adv_bridge: hdmi@3d {
- compatible = "adi,adv7535";
- reg = <0x3d>, <0x3c>, <0x3e>, <0x3f>;
- reg-names = "main", "cec", "edid", "packet";
- adi,dsi-lanes = <4>;
- #sound-dai-cells = <0>;
-
- ports {
- #address-cells = <1>;
- #size-cells = <0>;
-
- port@0 {
- reg = <0>;
-
- adv7535_in: endpoint {
- remote-endpoint = <&dsi_out>;
- };
- };
-
- port@1 {
- reg = <1>;
-
- adv7535_out: endpoint {
- remote-endpoint = <&hdmi_con>;
- };
- };
- };
- };
-
- pcieclk: clock-generator@68 {
- compatible = "renesas,9fgv0241";
- reg = <0x68>;
- clocks = <&clk_xtal25>;
- #clock-cells = <1>;
- };
-};
-
-&i2c3 {
- /* Connected to USB Hub */
- usb-typec@52 {
- compatible = "nxp,ptn5110";
- reg = <0x52>;
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_typec>;
- interrupt-parent = <&gpio4>;
- interrupts = <1 IRQ_TYPE_LEVEL_LOW>;
-
- connector {
- compatible = "usb-c-connector";
- label = "USB-C";
- power-role = "source";
- data-role = "host";
- source-pdos = <PDO_FIXED(5000, 3000, PDO_FIXED_USB_COMM)>;
- };
- };
-};
-
-&i2c4 {
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_i2c4>;
- clock-frequency = <384000>;
- status = "okay";
-
- wm8962: audio-codec@1a {
- compatible = "wlf,wm8962";
- reg = <0x1a>;
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_wm8962>;
- clocks = <&clk IMX8MP_CLK_IPP_DO_CLKO1>;
- assigned-clocks = <&clk IMX8MP_CLK_IPP_DO_CLKO1>;
- assigned-clock-parents = <&clk IMX8MP_AUDIO_PLL2_OUT>;
- assigned-clock-rates = <22576000>;
- DCVDD-supply = <®_audio>;
- DBVDD-supply = <®_audio>;
- AVDD-supply = <®_audio>;
- CPVDD-supply = <®_audio>;
- MICVDD-supply = <®_audio>;
- PLLVDD-supply = <®_audio>;
- SPKVDD1-supply = <®_audio>;
- SPKVDD2-supply = <®_audio>;
- gpio-cfg = <
- 0x0000 /* 0:Default */
- 0x0000 /* 1:Default */
- 0x0000 /* 2:FN_DMICCLK */
- 0x0000 /* 3:Default */
- 0x0000 /* 4:FN_DMICCDAT */
- 0x0000 /* 5:Default */
- >;
- #sound-dai-cells = <0>;
- };
-
- pca6416: gpio@20 {
- compatible = "nxp,pcal6416";
- reg = <0x20>;
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_pcal6414>;
- gpio-controller;
- #gpio-cells = <2>;
- interrupt-parent = <&gpio4>;
- interrupts = <27 IRQ_TYPE_EDGE_FALLING>;
- interrupt-controller;
- #interrupt-cells = <2>;
- };
-
- pca6416_1: gpio@21 {
- compatible = "nxp,pcal6416";
- reg = <0x21>;
- gpio-controller;
- #gpio-cells = <2>;
- interrupt-parent = <&gpio4>;
- interrupts = <27 IRQ_TYPE_EDGE_FALLING>;
- interrupt-controller;
- #interrupt-cells = <2>;
-
- usb-hub-hog {
- gpio-hog;
- gpios = <7 0>;
- output-low;
- line-name = "USB Hub Enable";
- };
- };
-
- usb-typec@47 {
- compatible = "ti,hd3ss3220";
- reg = <0x47>;
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_hd3ss3220>;
- interrupt-parent = <&gpio4>;
- interrupts = <19 IRQ_TYPE_LEVEL_LOW>;
-
- ports {
- #address-cells = <1>;
- #size-cells = <0>;
-
- port@0 {
- reg = <0>;
-
- hd3ss3220_in_ep: endpoint {
- remote-endpoint = <&ss_ep>;
- };
- };
-
- port@1 {
- reg = <1>;
-
- hd3ss3220_out_ep: endpoint {
- remote-endpoint = <&usb3_role_switch>;
- };
- };
- };
- };
-};
-
-&lcdif1 {
- status = "okay";
-};
-
-&micfil {
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_pdm>;
- assigned-clocks = <&clk IMX8MP_CLK_PDM>;
- assigned-clock-parents = <&clk IMX8MP_AUDIO_PLL1_OUT>;
- assigned-clock-rates = <49152000>;
- status = "okay";
-};
-
-&mipi_dsi {
- samsung,esc-clock-frequency = <10000000>;
- status = "okay";
-
- ports {
- port@1 {
- reg = <1>;
-
- dsi_out: endpoint {
- remote-endpoint = <&adv7535_in>;
- };
- };
- };
-};
-
-&pcie {
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_pcie>;
- reset-gpio = <&gpio4 21 GPIO_ACTIVE_LOW>;
- status = "okay";
-};
-
-&pcie_phy {
- fsl,clkreq-unsupported;
- fsl,refclk-pad-mode = <IMX8_PCIE_REFCLK_PAD_INPUT>;
- clocks = <&pcieclk 1>;
- clock-names = "ref";
- status = "okay";
-};
-
-&sai3 {
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_sai3>;
- assigned-clocks = <&clk IMX8MP_CLK_SAI3>,
- <&clk IMX8MP_AUDIO_PLL2> ;
- assigned-clock-parents = <&clk IMX8MP_AUDIO_PLL2_OUT>;
- assigned-clock-rates = <12288000>, <361267200>;
- fsl,sai-mclk-direction-output;
- status = "okay";
-};
-
-&sai5 {
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_sai5>;
- assigned-clocks = <&clk IMX8MP_CLK_SAI5>;
- assigned-clock-parents = <&clk IMX8MP_AUDIO_PLL1_OUT>;
- assigned-clock-rates = <12288000>;
- fsl,sai-mclk-direction-output;
- status = "okay";
-};
-
-&snvs_pwrkey {
- status = "okay";
-};
-
-&uart2 {
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_uart2>;
- status = "okay";
-};
-
-&uart3 {
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_uart3>;
- assigned-clocks = <&clk IMX8MP_CLK_UART3>;
- assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_80M>;
- uart-has-rtscts;
- status = "okay";
-};
-
-&usb3_0 {
- status = "okay";
-};
-
-&usb_dwc3_0 {
- dr_mode = "otg";
- hnp-disable;
- srp-disable;
- adp-disable;
- usb-role-switch;
- status = "okay";
-
- ports {
- #address-cells = <1>;
- #size-cells = <0>;
-
- port@0 {
- reg = <0>;
- usb3_hs_ep: endpoint {
- remote-endpoint = <&hs_ep>;
- };
- };
- port@1 {
- reg = <1>;
- usb3_role_switch: endpoint {
- remote-endpoint = <&hd3ss3220_out_ep>;
- };
- };
- };
-};
-
-&usb3_phy0 {
- vbus-supply = <®_usb1_host_vbus>;
- status = "okay";
-};
-
-&usb3_1 {
- status = "okay";
-};
-
-&usb_dwc3_1 {
- dr_mode = "host";
- status = "okay";
-};
-
-&usb3_phy1 {
- status = "okay";
-};
-
-&usdhc2 {
- pinctrl-names = "default", "state_100mhz", "state_200mhz";
- pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>;
- pinctrl-1 = <&pinctrl_usdhc2_100mhz>, <&pinctrl_usdhc2_gpio>;
- pinctrl-2 = <&pinctrl_usdhc2_200mhz>, <&pinctrl_usdhc2_gpio>;
- cd-gpios = <&gpio2 12 GPIO_ACTIVE_LOW>;
- vmmc-supply = <®_usdhc2_vmmc>;
- bus-width = <4>;
- status = "okay";
-};
-
-&iomuxc {
- pinctrl_ecspi2: ecspi2grp {
- fsl,pins = <
- MX8MP_IOMUXC_ECSPI2_SCLK__ECSPI2_SCLK 0x82
- MX8MP_IOMUXC_ECSPI2_MOSI__ECSPI2_MOSI 0x82
- MX8MP_IOMUXC_ECSPI2_MISO__ECSPI2_MISO 0x82
- MX8MP_IOMUXC_ECSPI2_SS0__GPIO5_IO13 0x40000
- >;
- };
-
- pinctrl_fec: fecgrp {
- fsl,pins = <
- MX8MP_IOMUXC_SAI1_RXD2__ENET1_MDC 0x2
- MX8MP_IOMUXC_SAI1_RXD3__ENET1_MDIO 0x2
- MX8MP_IOMUXC_SAI1_RXD4__ENET1_RGMII_RD0 0x90
- MX8MP_IOMUXC_SAI1_RXD5__ENET1_RGMII_RD1 0x90
- MX8MP_IOMUXC_SAI1_RXD6__ENET1_RGMII_RD2 0x90
- MX8MP_IOMUXC_SAI1_RXD7__ENET1_RGMII_RD3 0x90
- MX8MP_IOMUXC_SAI1_TXC__ENET1_RGMII_RXC 0x90
- MX8MP_IOMUXC_SAI1_TXFS__ENET1_RGMII_RX_CTL 0x90
- MX8MP_IOMUXC_SAI1_TXD0__ENET1_RGMII_TD0 0x16
- MX8MP_IOMUXC_SAI1_TXD1__ENET1_RGMII_TD1 0x16
- MX8MP_IOMUXC_SAI1_TXD2__ENET1_RGMII_TD2 0x16
- MX8MP_IOMUXC_SAI1_TXD3__ENET1_RGMII_TD3 0x16
- MX8MP_IOMUXC_SAI1_TXD4__ENET1_RGMII_TX_CTL 0x16
- MX8MP_IOMUXC_SAI1_TXD5__ENET1_RGMII_TXC 0x16
- MX8MP_IOMUXC_SAI1_RXD0__GPIO4_IO02 0x140
- MX8MP_IOMUXC_SAI1_TXD6__GPIO4_IO18 0x10
- >;
- };
-
- pinctrl_flexcan1: flexcan1grp {
- fsl,pins = <
- MX8MP_IOMUXC_SPDIF_RX__CAN1_RX 0x154
- MX8MP_IOMUXC_SPDIF_TX__CAN1_TX 0x154
- >;
- };
-
- pinctrl_hd3ss3220: hd3ss3220grp {
- fsl,pins = <
- MX8MP_IOMUXC_SAI1_TXD7__GPIO4_IO19 0x140
- >;
- };
-
- pinctrl_i2c2: i2c2grp {
- fsl,pins = <
- MX8MP_IOMUXC_I2C2_SCL__I2C2_SCL 0x400001c2
- MX8MP_IOMUXC_I2C2_SDA__I2C2_SDA 0x400001c2
- >;
- };
-
- pinctrl_i2c4: i2c4grp {
- fsl,pins = <
- MX8MP_IOMUXC_I2C4_SCL__I2C4_SCL 0x400001c2
- MX8MP_IOMUXC_I2C4_SDA__I2C4_SDA 0x400001c2
- >;
- };
-
- pinctrl_led3: led3grp {
- fsl,pins = <
- MX8MP_IOMUXC_SAI3_RXFS__GPIO4_IO28 0x41
- >;
- };
-
- pinctrl_pcal6414: pcal6414-gpiogrp {
- fsl,pins = <
- MX8MP_IOMUXC_SAI2_MCLK__GPIO4_IO27 0x10
- >;
- };
-
- pinctrl_pcie: pciegrp {
- fsl,pins = <
- MX8MP_IOMUXC_GPIO1_IO05__GPIO1_IO05 0x10 /* PCIe_nDIS */
- MX8MP_IOMUXC_SAI2_RXFS__GPIO4_IO21 0x10 /* PCIe_nRST */
- >;
- };
-
- pinctrl_pdm: pdmgrp {
- fsl,pins = <
- MX8MP_IOMUXC_SAI5_RXC__AUDIOMIX_PDM_CLK 0xd6
- MX8MP_IOMUXC_SAI5_RXD0__AUDIOMIX_PDM_BIT_STREAM00 0xd6
- >;
- };
-
- pinctrl_reg_usdhc2_vmmc: regusdhc2vmmcgrp {
- fsl,pins = <
- MX8MP_IOMUXC_SD2_RESET_B__GPIO2_IO19 0x40
- >;
- };
-
- pinctrl_sai3: sai3grp {
- fsl,pins = <
- MX8MP_IOMUXC_SAI3_TXFS__AUDIOMIX_SAI3_TX_SYNC 0xd6
- MX8MP_IOMUXC_SAI3_TXC__AUDIOMIX_SAI3_TX_BCLK 0xd6
- MX8MP_IOMUXC_SAI3_RXD__AUDIOMIX_SAI3_RX_DATA00 0xd6
- MX8MP_IOMUXC_SAI3_TXD__AUDIOMIX_SAI3_TX_DATA00 0xd6
- MX8MP_IOMUXC_SAI3_MCLK__AUDIOMIX_SAI3_MCLK 0xd6
- >;
- };
-
- pinctrl_sai5: sai5grp {
- fsl,pins = <
- MX8MP_IOMUXC_SAI5_RXD3__AUDIOMIX_SAI5_TX_DATA00 0xd6
- MX8MP_IOMUXC_SAI5_RXD2__AUDIOMIX_SAI5_TX_BCLK 0xd6
- MX8MP_IOMUXC_SAI5_RXD1__AUDIOMIX_SAI5_TX_SYNC 0xd6
- >;
- };
-
- pinctrl_tpm: tpmgrp {
- fsl,pins = <
- MX8MP_IOMUXC_SAI1_RXFS__GPIO4_IO00 0x19 /* Reset */
- MX8MP_IOMUXC_SAI3_RXC__GPIO4_IO29 0x1d6 /* IRQ */
- >;
- };
-
- pinctrl_typec: typec1grp {
- fsl,pins = <
- MX8MP_IOMUXC_SAI1_RXC__GPIO4_IO01 0xc4
- >;
- };
-
- pinctrl_uart2: uart2grp {
- fsl,pins = <
- MX8MP_IOMUXC_UART2_RXD__UART2_DCE_RX 0x140
- MX8MP_IOMUXC_UART2_TXD__UART2_DCE_TX 0x140
- >;
- };
-
- pinctrl_uart3: uart3grp {
- fsl,pins = <
- MX8MP_IOMUXC_ECSPI1_SCLK__UART3_DCE_RX 0x140
- MX8MP_IOMUXC_ECSPI1_MOSI__UART3_DCE_TX 0x140
- MX8MP_IOMUXC_ECSPI1_SS0__UART3_DCE_RTS 0x140
- MX8MP_IOMUXC_ECSPI1_MISO__UART3_DCE_CTS 0x140
- >;
- };
-
- pinctrl_usdhc2: usdhc2grp {
- fsl,pins = <
- MX8MP_IOMUXC_SD2_CLK__USDHC2_CLK 0x190
- MX8MP_IOMUXC_SD2_CMD__USDHC2_CMD 0x1d0
- MX8MP_IOMUXC_SD2_DATA0__USDHC2_DATA0 0x1d0
- MX8MP_IOMUXC_SD2_DATA1__USDHC2_DATA1 0x1d0
- MX8MP_IOMUXC_SD2_DATA2__USDHC2_DATA2 0x1d0
- MX8MP_IOMUXC_SD2_DATA3__USDHC2_DATA3 0x1d0
- MX8MP_IOMUXC_GPIO1_IO04__USDHC2_VSELECT 0xc0
- >;
- };
-
- pinctrl_usdhc2_100mhz: usdhc2-100mhzgrp {
- fsl,pins = <
- MX8MP_IOMUXC_SD2_CLK__USDHC2_CLK 0x194
- MX8MP_IOMUXC_SD2_CMD__USDHC2_CMD 0x1d4
- MX8MP_IOMUXC_SD2_DATA0__USDHC2_DATA0 0x1d4
- MX8MP_IOMUXC_SD2_DATA1__USDHC2_DATA1 0x1d4
- MX8MP_IOMUXC_SD2_DATA2__USDHC2_DATA2 0x1d4
- MX8MP_IOMUXC_SD2_DATA3__USDHC2_DATA3 0x1d4
- MX8MP_IOMUXC_GPIO1_IO04__USDHC2_VSELECT 0xc0
- >;
- };
-
- pinctrl_usdhc2_200mhz: usdhc2-200mhzgrp {
- fsl,pins = <
- MX8MP_IOMUXC_SD2_CLK__USDHC2_CLK 0x196
- MX8MP_IOMUXC_SD2_CMD__USDHC2_CMD 0x1d6
- MX8MP_IOMUXC_SD2_DATA0__USDHC2_DATA0 0x1d6
- MX8MP_IOMUXC_SD2_DATA1__USDHC2_DATA1 0x1d6
- MX8MP_IOMUXC_SD2_DATA2__USDHC2_DATA2 0x1d6
- MX8MP_IOMUXC_SD2_DATA3__USDHC2_DATA3 0x1d6
- MX8MP_IOMUXC_GPIO1_IO04__USDHC2_VSELECT 0xc0
- >;
- };
-
- pinctrl_usdhc2_gpio: usdhc2gpiogrp {
- fsl,pins = <
- MX8MP_IOMUXC_SD2_CD_B__GPIO2_IO12 0x1c4
- >;
- };
-
- pinctrl_wm8962: wm8962grp {
- fsl,pins = <
- MX8MP_IOMUXC_GPIO1_IO14__CCM_CLKO1 0x59
- >;
- };
-};
diff --git a/arch/arm/dts/imx8mp-beacon-som.dtsi b/arch/arm/dts/imx8mp-beacon-som.dtsi
deleted file mode 100644
index 8be251b..0000000
--- a/arch/arm/dts/imx8mp-beacon-som.dtsi
+++ /dev/null
@@ -1,487 +0,0 @@
-// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
-/*
- * Copyright 2023 LogicPD, Inc. dba Beacon EmbeddedWorks
- */
-
-/ {
- aliases {
- rtc0 = &rtc;
- rtc1 = &snvs_rtc;
- };
-
- memory@40000000 {
- device_type = "memory";
- reg = <0x0 0x40000000 0 0xc0000000>,
- <0x1 0x00000000 0 0xc0000000>;
- };
-
- reg_wl_bt: regulator-wifi-bt {
- compatible = "regulator-fixed";
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_reg_wl_bt>;
- regulator-name = "wl-bt-pow-dwn";
- regulator-min-microvolt = <3300000>;
- regulator-max-microvolt = <3300000>;
- gpio = <&gpio2 6 GPIO_ACTIVE_LOW>;
- startup-delay-us = <70000>;
- regulator-always-on;
- };
-};
-
-&A53_0 {
- cpu-supply = <&buck2>;
-};
-
-&A53_1 {
- cpu-supply = <&buck2>;
-};
-
-&A53_2 {
- cpu-supply = <&buck2>;
-};
-
-&A53_3 {
- cpu-supply = <&buck2>;
-};
-
-&eqos {
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_eqos>;
- phy-mode = "rgmii-id";
- phy-handle = <ðphy0>;
- snps,force_thresh_dma_mode;
- snps,mtl-rx-config = <&mtl_rx_setup>;
- snps,mtl-tx-config = <&mtl_tx_setup>;
- status = "okay";
-
- mdio {
- compatible = "snps,dwmac-mdio";
- #address-cells = <1>;
- #size-cells = <0>;
-
- ethphy0: ethernet-phy@3 {
- compatible = "ethernet-phy-id0022.1640",
- "ethernet-phy-ieee802.3-c22";
- reg = <3>;
- reset-gpios = <&gpio4 10 GPIO_ACTIVE_LOW>;
- interrupt-parent = <&gpio1>;
- interrupts = <10 IRQ_TYPE_LEVEL_LOW>;
- };
- };
-
- mtl_rx_setup: rx-queues-config {
- snps,rx-queues-to-use = <5>;
- snps,rx-sched-sp;
-
- queue0 {
- snps,dcb-algorithm;
- snps,priority = <0x1>;
- snps,map-to-dma-channel = <0>;
- };
-
- queue1 {
- snps,dcb-algorithm;
- snps,priority = <0x2>;
- snps,map-to-dma-channel = <1>;
- };
-
- queue2 {
- snps,dcb-algorithm;
- snps,priority = <0x4>;
- snps,map-to-dma-channel = <2>;
- };
-
- queue3 {
- snps,dcb-algorithm;
- snps,priority = <0x8>;
- snps,map-to-dma-channel = <3>;
- };
-
- queue4 {
- snps,dcb-algorithm;
- snps,priority = <0xf0>;
- snps,map-to-dma-channel = <4>;
- };
- };
-
- mtl_tx_setup: tx-queues-config {
- snps,tx-queues-to-use = <5>;
- snps,tx-sched-sp;
-
- queue0 {
- snps,dcb-algorithm;
- snps,priority = <0x1>;
- };
-
- queue1 {
- snps,dcb-algorithm;
- snps,priority = <0x2>;
- };
-
- queue2 {
- snps,dcb-algorithm;
- snps,priority = <0x4>;
- };
-
- queue3 {
- snps,dcb-algorithm;
- snps,priority = <0x8>;
- };
-
- queue4 {
- snps,dcb-algorithm;
- snps,priority = <0xf0>;
- };
- };
-};
-
-&flexspi {
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_flexspi0>;
- status = "okay";
-
- flash0: flash@0 {
- compatible = "jedec,spi-nor";
- reg = <0>;
- spi-max-frequency = <80000000>;
- spi-tx-bus-width = <1>;
- spi-rx-bus-width = <4>;
- };
-};
-
-&i2c1 {
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_i2c1>;
- clock-frequency = <384000>;
- status = "okay";
-
- pmic@25 {
- compatible = "nxp,pca9450c";
- reg = <0x25>;
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_pmic>;
- interrupt-parent = <&gpio1>;
- interrupts = <3 IRQ_TYPE_LEVEL_LOW>;
-
- regulators {
- buck1: BUCK1 {
- regulator-name = "BUCK1";
- regulator-min-microvolt = <600000>;
- regulator-max-microvolt = <2187500>;
- regulator-boot-on;
- regulator-always-on;
- regulator-ramp-delay = <3125>;
- };
-
- buck2: BUCK2 {
- regulator-name = "BUCK2";
- regulator-min-microvolt = <600000>;
- regulator-max-microvolt = <2187500>;
- regulator-boot-on;
- regulator-always-on;
- regulator-ramp-delay = <3125>;
- nxp,dvs-run-voltage = <950000>;
- nxp,dvs-standby-voltage = <850000>;
- };
-
- buck4: BUCK4 {
- regulator-name = "BUCK4";
- regulator-min-microvolt = <3300000>;
- regulator-max-microvolt = <3300000>;
- regulator-boot-on;
- regulator-always-on;
- };
-
- buck5: BUCK5 {
- regulator-name = "BUCK5";
- regulator-min-microvolt = <1800000>;
- regulator-max-microvolt = <1800000>;
- regulator-boot-on;
- regulator-always-on;
- };
-
- buck6: BUCK6 {
- regulator-name = "BUCK6";
- regulator-min-microvolt = <600000>;
- regulator-max-microvolt = <3400000>;
- regulator-boot-on;
- regulator-always-on;
- };
-
- ldo1: LDO1 {
- regulator-name = "LDO1";
- regulator-min-microvolt = <1600000>;
- regulator-max-microvolt = <1800000>;
- regulator-boot-on;
- regulator-always-on;
- };
-
- ldo3: LDO3 {
- regulator-name = "LDO3";
- regulator-min-microvolt = <800000>;
- regulator-max-microvolt = <1800000>;
- regulator-boot-on;
- regulator-always-on;
- };
-
- ldo4: LDO4 {
- regulator-name = "LDO4";
- regulator-min-microvolt = <800000>;
- regulator-max-microvolt = <3300000>;
- regulator-boot-on;
- regulator-always-on;
- };
-
- ldo5: LDO5 {
- regulator-name = "LDO5";
- regulator-min-microvolt = <1800000>;
- regulator-max-microvolt = <3300000>;
- regulator-boot-on;
- regulator-always-on;
- };
- };
- };
-};
-
-&i2c3 {
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_i2c3>;
- clock-frequency = <384000>;
- status = "okay";
-
- eeprom@50 {
- compatible = "atmel,24c64";
- reg = <0x50>;
- pagesize = <32>;
- read-only; /* Manufacturing EEPROM programmed at factory */
- };
-
- rtc: rtc@51 {
- compatible = "nxp,pcf85263";
- reg = <0x51>;
- };
-};
-
-&snvs_pwrkey {
- status = "okay";
-};
-
-&uart1 {
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_uart1>;
- assigned-clocks = <&clk IMX8MP_CLK_UART1>;
- assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_80M>;
- uart-has-rtscts;
- status = "okay";
-
- bluetooth {
- compatible = "nxp,88w8997-bt";
- };
-};
-
-&usdhc1 {
- pinctrl-names = "default", "state_100mhz", "state_200mhz";
- pinctrl-0 = <&pinctrl_usdhc1>;
- pinctrl-1 = <&pinctrl_usdhc1_100mhz>;
- pinctrl-2 = <&pinctrl_usdhc1_200mhz>;
- bus-width = <4>;
- vmmc-supply = <®_wl_bt>;
- cap-sd-highspeed;
- sd-uhs-sdr50;
- sd-uhs-sdr104;
- keep-power-in-suspend;
- wakeup-source;
- non-removable;
- cap-power-off-card;
- #address-cells = <1>;
- #size-cells = <0>;
- status = "okay";
-
- mwifiex: wifi@1 {
- compatible = "marvell,sd8997";
- reg = <1>;
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_wlan>;
- interrupt-parent = <&gpio2>;
- interrupts = <9 IRQ_TYPE_LEVEL_LOW>;
- };
-};
-
-&usdhc3 {
- pinctrl-names = "default", "state_100mhz", "state_200mhz";
- pinctrl-0 = <&pinctrl_usdhc3>;
- pinctrl-1 = <&pinctrl_usdhc3_100mhz>;
- pinctrl-2 = <&pinctrl_usdhc3_200mhz>;
- bus-width = <8>;
- non-removable;
- status = "okay";
-};
-
-&wdog1 {
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_wdog>;
- fsl,ext-reset-output;
- status = "okay";
-};
-
-&iomuxc {
- pinctrl_eqos: eqosgrp {
- fsl,pins = <
- MX8MP_IOMUXC_ENET_MDC__ENET_QOS_MDC 0x2
- MX8MP_IOMUXC_ENET_MDIO__ENET_QOS_MDIO 0x2
- MX8MP_IOMUXC_ENET_RD0__ENET_QOS_RGMII_RD0 0x90
- MX8MP_IOMUXC_ENET_RD1__ENET_QOS_RGMII_RD1 0x90
- MX8MP_IOMUXC_ENET_RD2__ENET_QOS_RGMII_RD2 0x90
- MX8MP_IOMUXC_ENET_RD3__ENET_QOS_RGMII_RD3 0x90
- MX8MP_IOMUXC_ENET_RXC__CCM_ENET_QOS_CLOCK_GENERATE_RX_CLK 0x90
- MX8MP_IOMUXC_ENET_RX_CTL__ENET_QOS_RGMII_RX_CTL 0x90
- MX8MP_IOMUXC_ENET_TD0__ENET_QOS_RGMII_TD0 0x16
- MX8MP_IOMUXC_ENET_TD1__ENET_QOS_RGMII_TD1 0x16
- MX8MP_IOMUXC_ENET_TD2__ENET_QOS_RGMII_TD2 0x16
- MX8MP_IOMUXC_ENET_TD3__ENET_QOS_RGMII_TD3 0x16
- MX8MP_IOMUXC_ENET_TX_CTL__ENET_QOS_RGMII_TX_CTL 0x16
- MX8MP_IOMUXC_ENET_TXC__CCM_ENET_QOS_CLOCK_GENERATE_TX_CLK 0x16
- MX8MP_IOMUXC_SAI2_RXC__GPIO4_IO22 0x10
- MX8MP_IOMUXC_GPIO1_IO10__GPIO1_IO10 0x10
- >;
- };
-
- pinctrl_flexspi0: flexspi0grp {
- fsl,pins = <
- MX8MP_IOMUXC_NAND_ALE__FLEXSPI_A_SCLK 0x1c2
- MX8MP_IOMUXC_NAND_CE0_B__FLEXSPI_A_SS0_B 0x82
- MX8MP_IOMUXC_NAND_DATA00__FLEXSPI_A_DATA00 0x82
- MX8MP_IOMUXC_NAND_DATA01__FLEXSPI_A_DATA01 0x82
- MX8MP_IOMUXC_NAND_DATA02__FLEXSPI_A_DATA02 0x82
- MX8MP_IOMUXC_NAND_DATA03__FLEXSPI_A_DATA03 0x82
- >;
- };
-
- pinctrl_i2c1: i2c1grp {
- fsl,pins = <
- MX8MP_IOMUXC_I2C1_SCL__I2C1_SCL 0x400001c2
- MX8MP_IOMUXC_I2C1_SDA__I2C1_SDA 0x400001c2
- >;
- };
-
- pinctrl_i2c3: i2c3grp {
- fsl,pins = <
- MX8MP_IOMUXC_I2C3_SCL__I2C3_SCL 0x400001c2
- MX8MP_IOMUXC_I2C3_SDA__I2C3_SDA 0x400001c2
- >;
- };
-
- pinctrl_pmic: pmicgrp {
- fsl,pins = <
- MX8MP_IOMUXC_GPIO1_IO03__GPIO1_IO03 0x1c0
- >;
- };
-
- pinctrl_reg_wl_bt: reg-wl-btgrp {
- fsl,pins = <
- MX8MP_IOMUXC_SD1_DATA4__GPIO2_IO06 0x40
- >;
- };
-
- pinctrl_uart1: uart1grp {
- fsl,pins = <
- MX8MP_IOMUXC_UART1_RXD__UART1_DCE_RX 0x140
- MX8MP_IOMUXC_UART1_TXD__UART1_DCE_TX 0x140
- MX8MP_IOMUXC_UART3_RXD__UART1_DCE_CTS 0x140
- MX8MP_IOMUXC_UART3_TXD__UART1_DCE_RTS 0x140
- >;
- };
-
- pinctrl_usdhc1: usdhc1grp {
- fsl,pins = <
- MX8MP_IOMUXC_SD1_CLK__USDHC1_CLK 0x190
- MX8MP_IOMUXC_SD1_CMD__USDHC1_CMD 0x1d0
- MX8MP_IOMUXC_SD1_DATA0__USDHC1_DATA0 0x1d0
- MX8MP_IOMUXC_SD1_DATA1__USDHC1_DATA1 0x1d0
- MX8MP_IOMUXC_SD1_DATA2__USDHC1_DATA2 0x1d0
- MX8MP_IOMUXC_SD1_DATA3__USDHC1_DATA3 0x1d0
- >;
- };
-
- pinctrl_usdhc1_100mhz: usdhc1-100mhzgrp {
- fsl,pins = <
- MX8MP_IOMUXC_SD1_CLK__USDHC1_CLK 0x194
- MX8MP_IOMUXC_SD1_CMD__USDHC1_CMD 0x1d4
- MX8MP_IOMUXC_SD1_DATA0__USDHC1_DATA0 0x1d4
- MX8MP_IOMUXC_SD1_DATA1__USDHC1_DATA1 0x1d4
- MX8MP_IOMUXC_SD1_DATA2__USDHC1_DATA2 0x1d4
- MX8MP_IOMUXC_SD1_DATA3__USDHC1_DATA3 0x1d4
- >;
- };
-
- pinctrl_usdhc1_200mhz: usdhc1-200mhzgrp {
- fsl,pins = <
- MX8MP_IOMUXC_SD1_CLK__USDHC1_CLK 0x196
- MX8MP_IOMUXC_SD1_CMD__USDHC1_CMD 0x1d6
- MX8MP_IOMUXC_SD1_DATA0__USDHC1_DATA0 0x1d6
- MX8MP_IOMUXC_SD1_DATA1__USDHC1_DATA1 0x1d6
- MX8MP_IOMUXC_SD1_DATA2__USDHC1_DATA2 0x1d6
- MX8MP_IOMUXC_SD1_DATA3__USDHC1_DATA3 0x1d6
- >;
- };
-
- pinctrl_usdhc3: usdhc3grp {
- fsl,pins = <
- MX8MP_IOMUXC_NAND_WE_B__USDHC3_CLK 0x190
- MX8MP_IOMUXC_NAND_WP_B__USDHC3_CMD 0x1d0
- MX8MP_IOMUXC_NAND_DATA04__USDHC3_DATA0 0x1d0
- MX8MP_IOMUXC_NAND_DATA05__USDHC3_DATA1 0x1d0
- MX8MP_IOMUXC_NAND_DATA06__USDHC3_DATA2 0x1d0
- MX8MP_IOMUXC_NAND_DATA07__USDHC3_DATA3 0x1d0
- MX8MP_IOMUXC_NAND_RE_B__USDHC3_DATA4 0x1d0
- MX8MP_IOMUXC_NAND_CE2_B__USDHC3_DATA5 0x1d0
- MX8MP_IOMUXC_NAND_CE3_B__USDHC3_DATA6 0x1d0
- MX8MP_IOMUXC_NAND_CLE__USDHC3_DATA7 0x1d0
- MX8MP_IOMUXC_NAND_CE1_B__USDHC3_STROBE 0x190
- >;
- };
-
- pinctrl_usdhc3_100mhz: usdhc3-100mhzgrp {
- fsl,pins = <
- MX8MP_IOMUXC_NAND_WE_B__USDHC3_CLK 0x194
- MX8MP_IOMUXC_NAND_WP_B__USDHC3_CMD 0x1d4
- MX8MP_IOMUXC_NAND_DATA04__USDHC3_DATA0 0x1d4
- MX8MP_IOMUXC_NAND_DATA05__USDHC3_DATA1 0x1d4
- MX8MP_IOMUXC_NAND_DATA06__USDHC3_DATA2 0x1d4
- MX8MP_IOMUXC_NAND_DATA07__USDHC3_DATA3 0x1d4
- MX8MP_IOMUXC_NAND_RE_B__USDHC3_DATA4 0x1d4
- MX8MP_IOMUXC_NAND_CE2_B__USDHC3_DATA5 0x1d4
- MX8MP_IOMUXC_NAND_CE3_B__USDHC3_DATA6 0x1d4
- MX8MP_IOMUXC_NAND_CLE__USDHC3_DATA7 0x1d4
- MX8MP_IOMUXC_NAND_CE1_B__USDHC3_STROBE 0x194
- >;
- };
-
- pinctrl_usdhc3_200mhz: usdhc3-200mhzgrp {
- fsl,pins = <
- MX8MP_IOMUXC_NAND_WE_B__USDHC3_CLK 0x196
- MX8MP_IOMUXC_NAND_WP_B__USDHC3_CMD 0x1d6
- MX8MP_IOMUXC_NAND_DATA04__USDHC3_DATA0 0x1d6
- MX8MP_IOMUXC_NAND_DATA05__USDHC3_DATA1 0x1d6
- MX8MP_IOMUXC_NAND_DATA06__USDHC3_DATA2 0x1d6
- MX8MP_IOMUXC_NAND_DATA07__USDHC3_DATA3 0x1d6
- MX8MP_IOMUXC_NAND_RE_B__USDHC3_DATA4 0x1d6
- MX8MP_IOMUXC_NAND_CE2_B__USDHC3_DATA5 0x1d6
- MX8MP_IOMUXC_NAND_CE3_B__USDHC3_DATA6 0x1d6
- MX8MP_IOMUXC_NAND_CLE__USDHC3_DATA7 0x1d6
- MX8MP_IOMUXC_NAND_CE1_B__USDHC3_STROBE 0x196
- >;
- };
-
- pinctrl_wdog: wdoggrp {
- fsl,pins = <
- MX8MP_IOMUXC_GPIO1_IO02__WDOG1_WDOG_B 0x166
- >;
- };
-
- pinctrl_wlan: wlangrp {
- fsl,pins = <
- MX8MP_IOMUXC_SD1_DATA7__GPIO2_IO09 0x140
- >;
- };
-};
diff --git a/arch/arm/dts/imx8mp-evk.dts b/arch/arm/dts/imx8mp-evk.dts
deleted file mode 100644
index 9f1469d..0000000
--- a/arch/arm/dts/imx8mp-evk.dts
+++ /dev/null
@@ -1,684 +0,0 @@
-// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
-/*
- * Copyright 2019 NXP
- */
-
-/dts-v1/;
-
-#include <dt-bindings/phy/phy-imx8-pcie.h>
-#include "imx8mp.dtsi"
-
-/ {
- model = "NXP i.MX8MPlus EVK board";
- compatible = "fsl,imx8mp-evk", "fsl,imx8mp";
-
- chosen {
- stdout-path = &uart2;
- };
-
- gpio-leds {
- compatible = "gpio-leds";
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_gpio_led>;
-
- status {
- label = "yellow:status";
- gpios = <&gpio3 16 GPIO_ACTIVE_HIGH>;
- default-state = "on";
- };
- };
-
- memory@40000000 {
- device_type = "memory";
- reg = <0x0 0x40000000 0 0xc0000000>,
- <0x1 0x00000000 0 0xc0000000>;
- };
-
- pcie0_refclk: pcie0-refclk {
- compatible = "fixed-clock";
- #clock-cells = <0>;
- clock-frequency = <100000000>;
- };
-
- reg_can1_stby: regulator-can1-stby {
- compatible = "regulator-fixed";
- regulator-name = "can1-stby";
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_flexcan1_reg>;
- regulator-min-microvolt = <3300000>;
- regulator-max-microvolt = <3300000>;
- gpio = <&gpio5 5 GPIO_ACTIVE_HIGH>;
- enable-active-high;
- };
-
- reg_can2_stby: regulator-can2-stby {
- compatible = "regulator-fixed";
- regulator-name = "can2-stby";
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_flexcan2_reg>;
- regulator-min-microvolt = <3300000>;
- regulator-max-microvolt = <3300000>;
- gpio = <&gpio4 27 GPIO_ACTIVE_HIGH>;
- enable-active-high;
- };
-
- reg_pcie0: regulator-pcie {
- compatible = "regulator-fixed";
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_pcie0_reg>;
- regulator-name = "MPCIE_3V3";
- regulator-min-microvolt = <3300000>;
- regulator-max-microvolt = <3300000>;
- gpio = <&gpio2 6 GPIO_ACTIVE_HIGH>;
- enable-active-high;
- };
-
- reg_usdhc2_vmmc: regulator-usdhc2 {
- compatible = "regulator-fixed";
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_reg_usdhc2_vmmc>;
- regulator-name = "VSD_3V3";
- regulator-min-microvolt = <3300000>;
- regulator-max-microvolt = <3300000>;
- gpio = <&gpio2 19 GPIO_ACTIVE_HIGH>;
- enable-active-high;
- };
-};
-
-&A53_0 {
- cpu-supply = <®_arm>;
-};
-
-&A53_1 {
- cpu-supply = <®_arm>;
-};
-
-&A53_2 {
- cpu-supply = <®_arm>;
-};
-
-&A53_3 {
- cpu-supply = <®_arm>;
-};
-
-&eqos {
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_eqos>;
- phy-mode = "rgmii-id";
- phy-handle = <ðphy0>;
- snps,force_thresh_dma_mode;
- snps,mtl-tx-config = <&mtl_tx_setup>;
- snps,mtl-rx-config = <&mtl_rx_setup>;
- status = "okay";
-
- mdio {
- compatible = "snps,dwmac-mdio";
- #address-cells = <1>;
- #size-cells = <0>;
-
- ethphy0: ethernet-phy@1 {
- compatible = "ethernet-phy-ieee802.3-c22";
- reg = <1>;
- eee-broken-1000t;
- reset-gpios = <&gpio4 22 GPIO_ACTIVE_LOW>;
- reset-assert-us = <10000>;
- reset-deassert-us = <80000>;
- realtek,clkout-disable;
- };
- };
-
- mtl_tx_setup: tx-queues-config {
- snps,tx-queues-to-use = <5>;
- snps,tx-sched-sp;
-
- queue0 {
- snps,dcb-algorithm;
- snps,priority = <0x1>;
- };
-
- queue1 {
- snps,dcb-algorithm;
- snps,priority = <0x2>;
- };
-
- queue2 {
- snps,dcb-algorithm;
- snps,priority = <0x4>;
- };
-
- queue3 {
- snps,dcb-algorithm;
- snps,priority = <0x8>;
- };
-
- queue4 {
- snps,dcb-algorithm;
- snps,priority = <0xf0>;
- };
- };
-
- mtl_rx_setup: rx-queues-config {
- snps,rx-queues-to-use = <5>;
- snps,rx-sched-sp;
-
- queue0 {
- snps,dcb-algorithm;
- snps,priority = <0x1>;
- snps,map-to-dma-channel = <0>;
- };
-
- queue1 {
- snps,dcb-algorithm;
- snps,priority = <0x2>;
- snps,map-to-dma-channel = <1>;
- };
-
- queue2 {
- snps,dcb-algorithm;
- snps,priority = <0x4>;
- snps,map-to-dma-channel = <2>;
- };
-
- queue3 {
- snps,dcb-algorithm;
- snps,priority = <0x8>;
- snps,map-to-dma-channel = <3>;
- };
-
- queue4 {
- snps,dcb-algorithm;
- snps,priority = <0xf0>;
- snps,map-to-dma-channel = <4>;
- };
- };
-};
-
-&fec {
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_fec>;
- phy-mode = "rgmii-id";
- phy-handle = <ðphy1>;
- fsl,magic-packet;
- status = "okay";
-
- mdio {
- #address-cells = <1>;
- #size-cells = <0>;
-
- ethphy1: ethernet-phy@1 {
- compatible = "ethernet-phy-ieee802.3-c22";
- reg = <1>;
- eee-broken-1000t;
- reset-gpios = <&gpio4 2 GPIO_ACTIVE_LOW>;
- reset-assert-us = <10000>;
- reset-deassert-us = <80000>;
- realtek,clkout-disable;
- };
- };
-};
-
-&flexcan1 {
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_flexcan1>;
- xceiver-supply = <®_can1_stby>;
- status = "okay";
-};
-
-&flexcan2 {
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_flexcan2>;
- xceiver-supply = <®_can2_stby>;
- status = "disabled";/* can2 pin conflict with pdm */
-};
-
-&i2c1 {
- clock-frequency = <400000>;
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_i2c1>;
- status = "okay";
-
- pmic@25 {
- compatible = "nxp,pca9450c";
- reg = <0x25>;
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_pmic>;
- interrupt-parent = <&gpio1>;
- interrupts = <3 IRQ_TYPE_LEVEL_LOW>;
-
- regulators {
- BUCK1 {
- regulator-name = "BUCK1";
- regulator-min-microvolt = <720000>;
- regulator-max-microvolt = <1000000>;
- regulator-boot-on;
- regulator-always-on;
- regulator-ramp-delay = <3125>;
- };
-
- reg_arm: BUCK2 {
- regulator-name = "BUCK2";
- regulator-min-microvolt = <720000>;
- regulator-max-microvolt = <1025000>;
- regulator-boot-on;
- regulator-always-on;
- regulator-ramp-delay = <3125>;
- nxp,dvs-run-voltage = <950000>;
- nxp,dvs-standby-voltage = <850000>;
- };
-
- BUCK4 {
- regulator-name = "BUCK4";
- regulator-min-microvolt = <3000000>;
- regulator-max-microvolt = <3600000>;
- regulator-boot-on;
- regulator-always-on;
- };
-
- BUCK5 {
- regulator-name = "BUCK5";
- regulator-min-microvolt = <1650000>;
- regulator-max-microvolt = <1950000>;
- regulator-boot-on;
- regulator-always-on;
- };
-
- BUCK6 {
- regulator-name = "BUCK6";
- regulator-min-microvolt = <1045000>;
- regulator-max-microvolt = <1155000>;
- regulator-boot-on;
- regulator-always-on;
- };
-
- LDO1 {
- regulator-name = "LDO1";
- regulator-min-microvolt = <1650000>;
- regulator-max-microvolt = <1950000>;
- regulator-boot-on;
- regulator-always-on;
- };
-
- LDO3 {
- regulator-name = "LDO3";
- regulator-min-microvolt = <1710000>;
- regulator-max-microvolt = <1890000>;
- regulator-boot-on;
- regulator-always-on;
- };
-
- LDO5 {
- regulator-name = "LDO5";
- regulator-min-microvolt = <1800000>;
- regulator-max-microvolt = <3300000>;
- regulator-boot-on;
- regulator-always-on;
- };
- };
- };
-};
-
-&i2c3 {
- clock-frequency = <400000>;
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_i2c3>;
- status = "okay";
-
- pca6416: gpio@20 {
- compatible = "ti,tca6416";
- reg = <0x20>;
- gpio-controller;
- #gpio-cells = <2>;
- interrupt-controller;
- #interrupt-cells = <2>;
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_pca6416_int>;
- interrupt-parent = <&gpio1>;
- interrupts = <12 IRQ_TYPE_LEVEL_LOW>;
- gpio-line-names = "EXT_PWREN1",
- "EXT_PWREN2",
- "CAN1/I2C5_SEL",
- "PDM/CAN2_SEL",
- "FAN_EN",
- "PWR_MEAS_IO1",
- "PWR_MEAS_IO2",
- "EXP_P0_7",
- "EXP_P1_0",
- "EXP_P1_1",
- "EXP_P1_2",
- "EXP_P1_3",
- "EXP_P1_4",
- "EXP_P1_5",
- "EXP_P1_6",
- "EXP_P1_7";
- };
-};
-
-/* I2C on expansion connector J22. */
-&i2c5 {
- clock-frequency = <100000>; /* Lower clock speed for external bus. */
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_i2c5>;
- status = "disabled"; /* can1 pins conflict with i2c5 */
-
- /* GPIO 2 of PCA6416 is used to switch between CAN1 and I2C5 functions:
- * LOW: CAN1 (default, pull-down)
- * HIGH: I2C5
- * You need to set it to high to enable I2C5 (for example, add gpio-hog
- * in pca6416 node).
- */
-};
-
-&pcie_phy {
- fsl,refclk-pad-mode = <IMX8_PCIE_REFCLK_PAD_INPUT>;
- clocks = <&pcie0_refclk>;
- clock-names = "ref";
- status = "okay";
-};
-
-&pcie {
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_pcie0>;
- reset-gpio = <&gpio2 7 GPIO_ACTIVE_LOW>;
- clocks = <&clk IMX8MP_CLK_HSIO_ROOT>,
- <&clk IMX8MP_CLK_PCIE_ROOT>,
- <&clk IMX8MP_CLK_HSIO_AXI>;
- clock-names = "pcie", "pcie_aux", "pcie_bus";
- assigned-clocks = <&clk IMX8MP_CLK_PCIE_AUX>;
- assigned-clock-rates = <10000000>;
- assigned-clock-parents = <&clk IMX8MP_SYS_PLL2_50M>;
- vpcie-supply = <®_pcie0>;
- status = "okay";
-};
-
-&snvs_pwrkey {
- status = "okay";
-};
-
-&uart2 {
- /* console */
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_uart2>;
- status = "okay";
-};
-
-&usb3_phy1 {
- status = "okay";
-};
-
-&usb3_1 {
- status = "okay";
-};
-
-&usb_dwc3_1 {
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_usb1_vbus>;
- dr_mode = "host";
- status = "okay";
-};
-
-&usdhc2 {
- assigned-clocks = <&clk IMX8MP_CLK_USDHC2>;
- assigned-clock-rates = <400000000>;
- pinctrl-names = "default", "state_100mhz", "state_200mhz";
- pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>;
- pinctrl-1 = <&pinctrl_usdhc2_100mhz>, <&pinctrl_usdhc2_gpio>;
- pinctrl-2 = <&pinctrl_usdhc2_200mhz>, <&pinctrl_usdhc2_gpio>;
- cd-gpios = <&gpio2 12 GPIO_ACTIVE_LOW>;
- vmmc-supply = <®_usdhc2_vmmc>;
- bus-width = <4>;
- status = "okay";
-};
-
-&usdhc3 {
- assigned-clocks = <&clk IMX8MP_CLK_USDHC3>;
- assigned-clock-rates = <400000000>;
- pinctrl-names = "default", "state_100mhz", "state_200mhz";
- pinctrl-0 = <&pinctrl_usdhc3>;
- pinctrl-1 = <&pinctrl_usdhc3_100mhz>;
- pinctrl-2 = <&pinctrl_usdhc3_200mhz>;
- bus-width = <8>;
- non-removable;
- status = "okay";
-};
-
-&wdog1 {
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_wdog>;
- fsl,ext-reset-output;
- status = "okay";
-};
-
-&iomuxc {
- pinctrl_eqos: eqosgrp {
- fsl,pins = <
- MX8MP_IOMUXC_ENET_MDC__ENET_QOS_MDC 0x2
- MX8MP_IOMUXC_ENET_MDIO__ENET_QOS_MDIO 0x2
- MX8MP_IOMUXC_ENET_RD0__ENET_QOS_RGMII_RD0 0x90
- MX8MP_IOMUXC_ENET_RD1__ENET_QOS_RGMII_RD1 0x90
- MX8MP_IOMUXC_ENET_RD2__ENET_QOS_RGMII_RD2 0x90
- MX8MP_IOMUXC_ENET_RD3__ENET_QOS_RGMII_RD3 0x90
- MX8MP_IOMUXC_ENET_RXC__CCM_ENET_QOS_CLOCK_GENERATE_RX_CLK 0x90
- MX8MP_IOMUXC_ENET_RX_CTL__ENET_QOS_RGMII_RX_CTL 0x90
- MX8MP_IOMUXC_ENET_TD0__ENET_QOS_RGMII_TD0 0x16
- MX8MP_IOMUXC_ENET_TD1__ENET_QOS_RGMII_TD1 0x16
- MX8MP_IOMUXC_ENET_TD2__ENET_QOS_RGMII_TD2 0x16
- MX8MP_IOMUXC_ENET_TD3__ENET_QOS_RGMII_TD3 0x16
- MX8MP_IOMUXC_ENET_TX_CTL__ENET_QOS_RGMII_TX_CTL 0x16
- MX8MP_IOMUXC_ENET_TXC__CCM_ENET_QOS_CLOCK_GENERATE_TX_CLK 0x16
- MX8MP_IOMUXC_SAI2_RXC__GPIO4_IO22 0x10
- >;
- };
-
- pinctrl_fec: fecgrp {
- fsl,pins = <
- MX8MP_IOMUXC_SAI1_RXD2__ENET1_MDC 0x2
- MX8MP_IOMUXC_SAI1_RXD3__ENET1_MDIO 0x2
- MX8MP_IOMUXC_SAI1_RXD4__ENET1_RGMII_RD0 0x90
- MX8MP_IOMUXC_SAI1_RXD5__ENET1_RGMII_RD1 0x90
- MX8MP_IOMUXC_SAI1_RXD6__ENET1_RGMII_RD2 0x90
- MX8MP_IOMUXC_SAI1_RXD7__ENET1_RGMII_RD3 0x90
- MX8MP_IOMUXC_SAI1_TXC__ENET1_RGMII_RXC 0x90
- MX8MP_IOMUXC_SAI1_TXFS__ENET1_RGMII_RX_CTL 0x90
- MX8MP_IOMUXC_SAI1_TXD0__ENET1_RGMII_TD0 0x16
- MX8MP_IOMUXC_SAI1_TXD1__ENET1_RGMII_TD1 0x16
- MX8MP_IOMUXC_SAI1_TXD2__ENET1_RGMII_TD2 0x16
- MX8MP_IOMUXC_SAI1_TXD3__ENET1_RGMII_TD3 0x16
- MX8MP_IOMUXC_SAI1_TXD4__ENET1_RGMII_TX_CTL 0x16
- MX8MP_IOMUXC_SAI1_TXD5__ENET1_RGMII_TXC 0x16
- MX8MP_IOMUXC_SAI1_RXD0__GPIO4_IO02 0x10
- >;
- };
-
- pinctrl_flexcan1: flexcan1grp {
- fsl,pins = <
- MX8MP_IOMUXC_SPDIF_RX__CAN1_RX 0x154
- MX8MP_IOMUXC_SPDIF_TX__CAN1_TX 0x154
- >;
- };
-
- pinctrl_flexcan2: flexcan2grp {
- fsl,pins = <
- MX8MP_IOMUXC_SAI5_MCLK__CAN2_RX 0x154
- MX8MP_IOMUXC_SAI5_RXD3__CAN2_TX 0x154
- >;
- };
-
- pinctrl_flexcan1_reg: flexcan1reggrp {
- fsl,pins = <
- MX8MP_IOMUXC_SPDIF_EXT_CLK__GPIO5_IO05 0x154 /* CAN1_STBY */
- >;
- };
-
- pinctrl_flexcan2_reg: flexcan2reggrp {
- fsl,pins = <
- MX8MP_IOMUXC_SAI2_MCLK__GPIO4_IO27 0x154 /* CAN2_STBY */
- >;
- };
-
- pinctrl_gpio_led: gpioledgrp {
- fsl,pins = <
- MX8MP_IOMUXC_NAND_READY_B__GPIO3_IO16 0x140
- >;
- };
-
- pinctrl_i2c1: i2c1grp {
- fsl,pins = <
- MX8MP_IOMUXC_I2C1_SCL__I2C1_SCL 0x400001c2
- MX8MP_IOMUXC_I2C1_SDA__I2C1_SDA 0x400001c2
- >;
- };
-
- pinctrl_i2c3: i2c3grp {
- fsl,pins = <
- MX8MP_IOMUXC_I2C3_SCL__I2C3_SCL 0x400001c2
- MX8MP_IOMUXC_I2C3_SDA__I2C3_SDA 0x400001c2
- >;
- };
-
- pinctrl_i2c5: i2c5grp {
- fsl,pins = <
- MX8MP_IOMUXC_SPDIF_RX__I2C5_SDA 0x400001c2
- MX8MP_IOMUXC_SPDIF_TX__I2C5_SCL 0x400001c2
- >;
- };
-
- pinctrl_pcie0: pcie0grp {
- fsl,pins = <
- MX8MP_IOMUXC_I2C4_SCL__PCIE_CLKREQ_B 0x61 /* open drain, pull up */
- MX8MP_IOMUXC_SD1_DATA5__GPIO2_IO07 0x41
- >;
- };
-
- pinctrl_pcie0_reg: pcie0reggrp {
- fsl,pins = <
- MX8MP_IOMUXC_SD1_DATA4__GPIO2_IO06 0x41
- >;
- };
-
- pinctrl_pmic: pmicgrp {
- fsl,pins = <
- MX8MP_IOMUXC_GPIO1_IO03__GPIO1_IO03 0x000001c0
- >;
- };
-
- pinctrl_pca6416_int: pca6416_int_grp {
- fsl,pins = <
- MX8MP_IOMUXC_GPIO1_IO12__GPIO1_IO12 0x146 /* Input pull-up. */
- >;
- };
-
- pinctrl_reg_usdhc2_vmmc: regusdhc2vmmcgrp {
- fsl,pins = <
- MX8MP_IOMUXC_SD2_RESET_B__GPIO2_IO19 0x40
- >;
- };
-
- pinctrl_uart2: uart2grp {
- fsl,pins = <
- MX8MP_IOMUXC_UART2_RXD__UART2_DCE_RX 0x140
- MX8MP_IOMUXC_UART2_TXD__UART2_DCE_TX 0x140
- >;
- };
-
- pinctrl_usb1_vbus: usb1grp {
- fsl,pins = <
- MX8MP_IOMUXC_GPIO1_IO14__USB2_OTG_PWR 0x10
- >;
- };
-
- pinctrl_usdhc2: usdhc2grp {
- fsl,pins = <
- MX8MP_IOMUXC_SD2_CLK__USDHC2_CLK 0x190
- MX8MP_IOMUXC_SD2_CMD__USDHC2_CMD 0x1d0
- MX8MP_IOMUXC_SD2_DATA0__USDHC2_DATA0 0x1d0
- MX8MP_IOMUXC_SD2_DATA1__USDHC2_DATA1 0x1d0
- MX8MP_IOMUXC_SD2_DATA2__USDHC2_DATA2 0x1d0
- MX8MP_IOMUXC_SD2_DATA3__USDHC2_DATA3 0x1d0
- MX8MP_IOMUXC_GPIO1_IO04__USDHC2_VSELECT 0xc0
- >;
- };
-
- pinctrl_usdhc2_100mhz: usdhc2-100mhzgrp {
- fsl,pins = <
- MX8MP_IOMUXC_SD2_CLK__USDHC2_CLK 0x194
- MX8MP_IOMUXC_SD2_CMD__USDHC2_CMD 0x1d4
- MX8MP_IOMUXC_SD2_DATA0__USDHC2_DATA0 0x1d4
- MX8MP_IOMUXC_SD2_DATA1__USDHC2_DATA1 0x1d4
- MX8MP_IOMUXC_SD2_DATA2__USDHC2_DATA2 0x1d4
- MX8MP_IOMUXC_SD2_DATA3__USDHC2_DATA3 0x1d4
- MX8MP_IOMUXC_GPIO1_IO04__USDHC2_VSELECT 0xc0
- >;
- };
-
- pinctrl_usdhc2_200mhz: usdhc2-200mhzgrp {
- fsl,pins = <
- MX8MP_IOMUXC_SD2_CLK__USDHC2_CLK 0x196
- MX8MP_IOMUXC_SD2_CMD__USDHC2_CMD 0x1d6
- MX8MP_IOMUXC_SD2_DATA0__USDHC2_DATA0 0x1d6
- MX8MP_IOMUXC_SD2_DATA1__USDHC2_DATA1 0x1d6
- MX8MP_IOMUXC_SD2_DATA2__USDHC2_DATA2 0x1d6
- MX8MP_IOMUXC_SD2_DATA3__USDHC2_DATA3 0x1d6
- MX8MP_IOMUXC_GPIO1_IO04__USDHC2_VSELECT 0xc0
- >;
- };
-
- pinctrl_usdhc2_gpio: usdhc2gpiogrp {
- fsl,pins = <
- MX8MP_IOMUXC_SD2_CD_B__GPIO2_IO12 0x1c4
- >;
- };
-
- pinctrl_usdhc3: usdhc3grp {
- fsl,pins = <
- MX8MP_IOMUXC_NAND_WE_B__USDHC3_CLK 0x190
- MX8MP_IOMUXC_NAND_WP_B__USDHC3_CMD 0x1d0
- MX8MP_IOMUXC_NAND_DATA04__USDHC3_DATA0 0x1d0
- MX8MP_IOMUXC_NAND_DATA05__USDHC3_DATA1 0x1d0
- MX8MP_IOMUXC_NAND_DATA06__USDHC3_DATA2 0x1d0
- MX8MP_IOMUXC_NAND_DATA07__USDHC3_DATA3 0x1d0
- MX8MP_IOMUXC_NAND_RE_B__USDHC3_DATA4 0x1d0
- MX8MP_IOMUXC_NAND_CE2_B__USDHC3_DATA5 0x1d0
- MX8MP_IOMUXC_NAND_CE3_B__USDHC3_DATA6 0x1d0
- MX8MP_IOMUXC_NAND_CLE__USDHC3_DATA7 0x1d0
- MX8MP_IOMUXC_NAND_CE1_B__USDHC3_STROBE 0x190
- >;
- };
-
- pinctrl_usdhc3_100mhz: usdhc3-100mhzgrp {
- fsl,pins = <
- MX8MP_IOMUXC_NAND_WE_B__USDHC3_CLK 0x194
- MX8MP_IOMUXC_NAND_WP_B__USDHC3_CMD 0x1d4
- MX8MP_IOMUXC_NAND_DATA04__USDHC3_DATA0 0x1d4
- MX8MP_IOMUXC_NAND_DATA05__USDHC3_DATA1 0x1d4
- MX8MP_IOMUXC_NAND_DATA06__USDHC3_DATA2 0x1d4
- MX8MP_IOMUXC_NAND_DATA07__USDHC3_DATA3 0x1d4
- MX8MP_IOMUXC_NAND_RE_B__USDHC3_DATA4 0x1d4
- MX8MP_IOMUXC_NAND_CE2_B__USDHC3_DATA5 0x1d4
- MX8MP_IOMUXC_NAND_CE3_B__USDHC3_DATA6 0x1d4
- MX8MP_IOMUXC_NAND_CLE__USDHC3_DATA7 0x1d4
- MX8MP_IOMUXC_NAND_CE1_B__USDHC3_STROBE 0x194
- >;
- };
-
- pinctrl_usdhc3_200mhz: usdhc3-200mhzgrp {
- fsl,pins = <
- MX8MP_IOMUXC_NAND_WE_B__USDHC3_CLK 0x196
- MX8MP_IOMUXC_NAND_WP_B__USDHC3_CMD 0x1d6
- MX8MP_IOMUXC_NAND_DATA04__USDHC3_DATA0 0x1d6
- MX8MP_IOMUXC_NAND_DATA05__USDHC3_DATA1 0x1d6
- MX8MP_IOMUXC_NAND_DATA06__USDHC3_DATA2 0x1d6
- MX8MP_IOMUXC_NAND_DATA07__USDHC3_DATA3 0x1d6
- MX8MP_IOMUXC_NAND_RE_B__USDHC3_DATA4 0x1d6
- MX8MP_IOMUXC_NAND_CE2_B__USDHC3_DATA5 0x1d6
- MX8MP_IOMUXC_NAND_CE3_B__USDHC3_DATA6 0x1d6
- MX8MP_IOMUXC_NAND_CLE__USDHC3_DATA7 0x1d6
- MX8MP_IOMUXC_NAND_CE1_B__USDHC3_STROBE 0x196
- >;
- };
-
- pinctrl_wdog: wdoggrp {
- fsl,pins = <
- MX8MP_IOMUXC_GPIO1_IO02__WDOG1_WDOG_B 0x166
- >;
- };
-};
diff --git a/arch/arm/dts/imx8mp-venice-gw702x.dtsi b/arch/arm/dts/imx8mp-venice-gw702x.dtsi
deleted file mode 100644
index 560c68e..0000000
--- a/arch/arm/dts/imx8mp-venice-gw702x.dtsi
+++ /dev/null
@@ -1,587 +0,0 @@
-// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
-/*
- * Copyright 2023 Gateworks Corporation
- */
-
-#include <dt-bindings/gpio/gpio.h>
-#include <dt-bindings/input/linux-event-codes.h>
-#include <dt-bindings/net/ti-dp83867.h>
-
-/ {
- aliases {
- ethernet0 = &eqos;
- };
-
- memory@40000000 {
- device_type = "memory";
- reg = <0x0 0x40000000 0 0x80000000>;
- };
-
- gpio-keys {
- compatible = "gpio-keys";
-
- key-user-pb {
- label = "user_pb";
- gpios = <&gpio 2 GPIO_ACTIVE_LOW>;
- linux,code = <BTN_0>;
- };
-
- key-user-pb1x {
- label = "user_pb1x";
- linux,code = <BTN_1>;
- interrupt-parent = <&gsc>;
- interrupts = <0>;
- };
-
- key-erased {
- label = "key_erased";
- linux,code = <BTN_2>;
- interrupt-parent = <&gsc>;
- interrupts = <1>;
- };
-
- key-eeprom-wp {
- label = "eeprom_wp";
- linux,code = <BTN_3>;
- interrupt-parent = <&gsc>;
- interrupts = <2>;
- };
-
- key-tamper {
- label = "tamper";
- linux,code = <BTN_4>;
- interrupt-parent = <&gsc>;
- interrupts = <5>;
- };
-
- switch-hold {
- label = "switch_hold";
- linux,code = <BTN_5>;
- interrupt-parent = <&gsc>;
- interrupts = <7>;
- };
- };
-};
-
-&A53_0 {
- cpu-supply = <&buck3_reg>;
-};
-
-&A53_1 {
- cpu-supply = <&buck3_reg>;
-};
-
-&A53_2 {
- cpu-supply = <&buck3_reg>;
-};
-
-&A53_3 {
- cpu-supply = <&buck3_reg>;
-};
-
-&eqos {
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_eqos>;
- phy-mode = "rgmii-id";
- phy-handle = <ðphy0>;
- status = "okay";
-
- mdio {
- compatible = "snps,dwmac-mdio";
- #address-cells = <1>;
- #size-cells = <0>;
-
- ethphy0: ethernet-phy@0 {
- compatible = "ethernet-phy-ieee802.3-c22";
- pinctrl-0 = <&pinctrl_ethphy0>;
- pinctrl-names = "default";
- reg = <0x0>;
- interrupt-parent = <&gpio3>;
- interrupts = <16 IRQ_TYPE_EDGE_FALLING>;
- ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_00_NS>;
- ti,tx-internal-delay = <DP83867_RGMIIDCTL_2_00_NS>;
- tx-fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>;
- rx-fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>;
- };
- };
-};
-
-&i2c1 {
- clock-frequency = <100000>;
- pinctrl-names = "default", "gpio";
- pinctrl-0 = <&pinctrl_i2c1>;
- pinctrl-1 = <&pinctrl_i2c1_gpio>;
- scl-gpios = <&gpio5 14 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
- sda-gpios = <&gpio5 15 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
- status = "okay";
-
- gsc: gsc@20 {
- compatible = "gw,gsc";
- reg = <0x20>;
- pinctrl-0 = <&pinctrl_gsc>;
- interrupt-parent = <&gpio2>;
- interrupts = <6 IRQ_TYPE_EDGE_FALLING>;
- interrupt-controller;
- #interrupt-cells = <1>;
- #address-cells = <1>;
- #size-cells = <0>;
-
- adc {
- compatible = "gw,gsc-adc";
- #address-cells = <1>;
- #size-cells = <0>;
-
- channel@6 {
- gw,mode = <0>;
- reg = <0x06>;
- label = "temp";
- };
-
- channel@8 {
- gw,mode = <3>;
- reg = <0x08>;
- label = "vdd_bat";
- };
-
- channel@16 {
- gw,mode = <4>;
- reg = <0x16>;
- label = "fan_tach";
- };
-
- channel@82 {
- gw,mode = <2>;
- reg = <0x82>;
- label = "vdd_vin";
- gw,voltage-divider-ohms = <22100 1000>;
- };
-
- channel@84 {
- gw,mode = <2>;
- reg = <0x84>;
- label = "vdd_adc1";
- gw,voltage-divider-ohms = <10000 10000>;
- };
-
- channel@86 {
- gw,mode = <2>;
- reg = <0x86>;
- label = "vdd_adc2";
- gw,voltage-divider-ohms = <10000 10000>;
- };
-
- channel@88 {
- gw,mode = <2>;
- reg = <0x88>;
- label = "vdd_1p0";
- };
-
- channel@8c {
- gw,mode = <2>;
- reg = <0x8c>;
- label = "vdd_1p8";
- };
-
- channel@8e {
- gw,mode = <2>;
- reg = <0x8e>;
- label = "vdd_2p5";
- };
-
- channel@90 {
- gw,mode = <2>;
- reg = <0x90>;
- label = "vdd_3p3";
- gw,voltage-divider-ohms = <10000 10000>;
- };
-
- channel@92 {
- gw,mode = <2>;
- reg = <0x92>;
- label = "vdd_dram";
- };
-
- channel@98 {
- gw,mode = <2>;
- reg = <0x98>;
- label = "vdd_soc";
- };
-
- channel@9a {
- gw,mode = <2>;
- reg = <0x9a>;
- label = "vdd_arm";
- };
-
- channel@a2 {
- gw,mode = <2>;
- reg = <0xa2>;
- label = "vdd_gsc";
- gw,voltage-divider-ohms = <10000 10000>;
- };
- };
-
- fan-controller@0 {
- compatible = "gw,gsc-fan";
- reg = <0x0a>;
- };
- };
-
- gpio: gpio@23 {
- compatible = "nxp,pca9555";
- reg = <0x23>;
- gpio-controller;
- #gpio-cells = <2>;
- interrupt-parent = <&gsc>;
- interrupts = <4>;
- };
-
- eeprom@50 {
- compatible = "atmel,24c02";
- reg = <0x50>;
- pagesize = <16>;
- };
-
- eeprom@51 {
- compatible = "atmel,24c02";
- reg = <0x51>;
- pagesize = <16>;
- };
-
- eeprom@52 {
- compatible = "atmel,24c02";
- reg = <0x52>;
- pagesize = <16>;
- };
-
- eeprom@53 {
- compatible = "atmel,24c02";
- reg = <0x53>;
- pagesize = <16>;
- };
-
- rtc@68 {
- compatible = "dallas,ds1672";
- reg = <0x68>;
- };
-
- pmic@69 {
- compatible = "mps,mp5416";
- reg = <0x69>;
-
- regulators {
- /* vdd_soc */
- buck1 {
- regulator-name = "buck1";
- regulator-min-microvolt = <850000>;
- regulator-max-microvolt = <1000000>;
- regulator-always-on;
- regulator-boot-on;
- };
-
- /* vdd_dram */
- buck2 {
- regulator-name = "buck2";
- regulator-min-microvolt = <1100000>;
- regulator-max-microvolt = <1100000>;
- regulator-always-on;
- regulator-boot-on;
- };
-
- /* vdd_arm */
- buck3_reg: buck3 {
- regulator-name = "buck3";
- regulator-min-microvolt = <850000>;
- regulator-max-microvolt = <1000000>;
- regulator-always-on;
- regulator-boot-on;
- };
-
- /* vdd_1p8 */
- buck4 {
- regulator-name = "buck4";
- regulator-min-microvolt = <1800000>;
- regulator-max-microvolt = <1800000>;
- regulator-always-on;
- regulator-boot-on;
- };
-
- /* OUT2: nvcc_snvs_1p8 */
- ldo1 {
- regulator-name = "ldo1";
- regulator-min-microvolt = <1800000>;
- regulator-max-microvolt = <1800000>;
- regulator-always-on;
- regulator-boot-on;
- };
-
- /* OUT3: vdd_1p0 */
- ldo2 {
- regulator-name = "ldo2";
- regulator-min-microvolt = <1000000>;
- regulator-max-microvolt = <1000000>;
- regulator-always-on;
- regulator-boot-on;
- };
-
- /* OUT4: vdd_2p5 */
- ldo3 {
- regulator-name = "ldo3";
- regulator-min-microvolt = <2500000>;
- regulator-max-microvolt = <2500000>;
- regulator-always-on;
- regulator-boot-on;
- };
-
- /* OUT5: vdd_3p3 */
- ldo4 {
- regulator-name = "ldo4";
- regulator-min-microvolt = <3300000>;
- regulator-max-microvolt = <3300000>;
- regulator-always-on;
- regulator-boot-on;
- };
- };
- };
-};
-
-/* off-board header */
-&i2c2 {
- clock-frequency = <400000>;
- pinctrl-names = "default", "gpio";
- pinctrl-0 = <&pinctrl_i2c2>;
- pinctrl-1 = <&pinctrl_i2c2_gpio>;
- scl-gpios = <&gpio5 16 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
- sda-gpios = <&gpio5 17 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
- status = "okay";
-
- eeprom@52 {
- compatible = "atmel,24c32";
- reg = <0x52>;
- pagesize = <32>;
- };
-};
-
-/* off-board header */
-&i2c3 {
- clock-frequency = <400000>;
- pinctrl-names = "default", "gpio";
- pinctrl-0 = <&pinctrl_i2c3>;
- pinctrl-1 = <&pinctrl_i2c3_gpio>;
- scl-gpios = <&gpio5 18 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
- sda-gpios = <&gpio5 19 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
- status = "okay";
-};
-
-/* off-board header */
-&uart1 {
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_uart1>;
- status = "okay";
-};
-
-/* console */
-&uart2 {
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_uart2>;
- status = "okay";
-};
-
-/* off-board header */
-&uart3 {
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_uart3>;
- status = "okay";
-};
-
-/* off-board */
-&usdhc1 {
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_usdhc1>;
- bus-width = <4>;
- non-removable;
- status = "okay";
- bus-width = <4>;
- non-removable;
- status = "okay";
-};
-
-/* eMMC */
-&usdhc3 {
- pinctrl-names = "default", "state_100mhz", "state_200mhz";
- pinctrl-0 = <&pinctrl_usdhc3>;
- pinctrl-1 = <&pinctrl_usdhc3_100mhz>;
- pinctrl-2 = <&pinctrl_usdhc3_200mhz>;
- bus-width = <8>;
- non-removable;
- status = "okay";
-};
-
-&wdog1 {
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_wdog>;
- fsl,ext-reset-output;
- status = "okay";
-};
-
-&iomuxc {
- pinctrl_eqos: eqosgrp {
- fsl,pins = <
- MX8MP_IOMUXC_ENET_MDC__ENET_QOS_MDC 0x2
- MX8MP_IOMUXC_ENET_MDIO__ENET_QOS_MDIO 0x2
- MX8MP_IOMUXC_ENET_RD0__ENET_QOS_RGMII_RD0 0x90
- MX8MP_IOMUXC_ENET_RD1__ENET_QOS_RGMII_RD1 0x90
- MX8MP_IOMUXC_ENET_RD2__ENET_QOS_RGMII_RD2 0x90
- MX8MP_IOMUXC_ENET_RD3__ENET_QOS_RGMII_RD3 0x90
- MX8MP_IOMUXC_ENET_RXC__CCM_ENET_QOS_CLOCK_GENERATE_RX_CLK 0x90
- MX8MP_IOMUXC_ENET_RX_CTL__ENET_QOS_RGMII_RX_CTL 0x90
- MX8MP_IOMUXC_ENET_TD0__ENET_QOS_RGMII_TD0 0x16
- MX8MP_IOMUXC_ENET_TD1__ENET_QOS_RGMII_TD1 0x16
- MX8MP_IOMUXC_ENET_TD2__ENET_QOS_RGMII_TD2 0x16
- MX8MP_IOMUXC_ENET_TD3__ENET_QOS_RGMII_TD3 0x16
- MX8MP_IOMUXC_ENET_TX_CTL__ENET_QOS_RGMII_TX_CTL 0x16
- MX8MP_IOMUXC_ENET_TXC__CCM_ENET_QOS_CLOCK_GENERATE_TX_CLK 0x16
- >;
- };
-
- pinctrl_ethphy0: ethphy0grp {
- fsl,pins = <
- MX8MP_IOMUXC_NAND_DQS__GPIO3_IO14 0x140 /* RST# */
- MX8MP_IOMUXC_NAND_READY_B__GPIO3_IO16 0x150 /* IRQ# */
- >;
- };
-
- pinctrl_gsc: gscgrp {
- fsl,pins = <
- MX8MP_IOMUXC_SD1_DATA4__GPIO2_IO06 0x150 /* IRQ# */
- >;
- };
-
- pinctrl_i2c1: i2c1grp {
- fsl,pins = <
- MX8MP_IOMUXC_I2C1_SCL__I2C1_SCL 0x400001c2
- MX8MP_IOMUXC_I2C1_SDA__I2C1_SDA 0x400001c2
- >;
- };
-
- pinctrl_i2c1_gpio: i2c1gpiogrp {
- fsl,pins = <
- MX8MP_IOMUXC_I2C1_SCL__GPIO5_IO14 0x400001c2
- MX8MP_IOMUXC_I2C1_SDA__GPIO5_IO15 0x400001c2
- >;
- };
-
- pinctrl_i2c2: i2c2grp {
- fsl,pins = <
- MX8MP_IOMUXC_I2C2_SCL__I2C2_SCL 0x400001c2
- MX8MP_IOMUXC_I2C2_SDA__I2C2_SDA 0x400001c2
- >;
- };
-
- pinctrl_i2c2_gpio: i2c2gpiogrp {
- fsl,pins = <
- MX8MP_IOMUXC_I2C2_SCL__GPIO5_IO16 0x400001c2
- MX8MP_IOMUXC_I2C2_SDA__GPIO5_IO17 0x400001c2
- >;
- };
-
- pinctrl_i2c3: i2c3grp {
- fsl,pins = <
- MX8MP_IOMUXC_I2C3_SCL__I2C3_SCL 0x400001c2
- MX8MP_IOMUXC_I2C3_SDA__I2C3_SDA 0x400001c2
- >;
- };
-
- pinctrl_i2c3_gpio: i2c3gpiogrp {
- fsl,pins = <
- MX8MP_IOMUXC_I2C3_SCL__GPIO5_IO18 0x400001c2
- MX8MP_IOMUXC_I2C3_SDA__GPIO5_IO19 0x400001c2
- >;
- };
-
- pinctrl_uart1: uart1grp {
- fsl,pins = <
- MX8MP_IOMUXC_UART1_RXD__UART1_DCE_RX 0x140
- MX8MP_IOMUXC_UART1_TXD__UART1_DCE_TX 0x140
- >;
- };
-
- pinctrl_uart2: uart2grp {
- fsl,pins = <
- MX8MP_IOMUXC_UART2_RXD__UART2_DCE_RX 0x140
- MX8MP_IOMUXC_UART2_TXD__UART2_DCE_TX 0x140
- >;
- };
-
- pinctrl_uart3: uart3grp {
- fsl,pins = <
- MX8MP_IOMUXC_UART3_RXD__UART3_DCE_RX 0x140
- MX8MP_IOMUXC_UART3_TXD__UART3_DCE_TX 0x140
- >;
- };
-
- pinctrl_usdhc1: usdhc1grp {
- fsl,pins = <
- MX8MP_IOMUXC_SD1_CLK__USDHC1_CLK 0x190
- MX8MP_IOMUXC_SD1_CMD__USDHC1_CMD 0x1d0
- MX8MP_IOMUXC_SD1_DATA0__USDHC1_DATA0 0x1d0
- MX8MP_IOMUXC_SD1_DATA1__USDHC1_DATA1 0x1d0
- MX8MP_IOMUXC_SD1_DATA2__USDHC1_DATA2 0x1d0
- MX8MP_IOMUXC_SD1_DATA3__USDHC1_DATA3 0x1d0
- >;
- };
-
- pinctrl_usdhc3: usdhc3grp {
- fsl,pins = <
- MX8MP_IOMUXC_NAND_WE_B__USDHC3_CLK 0x190
- MX8MP_IOMUXC_NAND_WP_B__USDHC3_CMD 0x1d0
- MX8MP_IOMUXC_NAND_DATA04__USDHC3_DATA0 0x1d0
- MX8MP_IOMUXC_NAND_DATA05__USDHC3_DATA1 0x1d0
- MX8MP_IOMUXC_NAND_DATA06__USDHC3_DATA2 0x1d0
- MX8MP_IOMUXC_NAND_DATA07__USDHC3_DATA3 0x1d0
- MX8MP_IOMUXC_NAND_RE_B__USDHC3_DATA4 0x1d0
- MX8MP_IOMUXC_NAND_CE2_B__USDHC3_DATA5 0x1d0
- MX8MP_IOMUXC_NAND_CE3_B__USDHC3_DATA6 0x1d0
- MX8MP_IOMUXC_NAND_CLE__USDHC3_DATA7 0x1d0
- MX8MP_IOMUXC_NAND_CE1_B__USDHC3_STROBE 0x190
- >;
- };
-
- pinctrl_usdhc3_100mhz: usdhc3-100mhzgrp {
- fsl,pins = <
- MX8MP_IOMUXC_NAND_WE_B__USDHC3_CLK 0x194
- MX8MP_IOMUXC_NAND_WP_B__USDHC3_CMD 0x1d4
- MX8MP_IOMUXC_NAND_DATA04__USDHC3_DATA0 0x1d4
- MX8MP_IOMUXC_NAND_DATA05__USDHC3_DATA1 0x1d4
- MX8MP_IOMUXC_NAND_DATA06__USDHC3_DATA2 0x1d4
- MX8MP_IOMUXC_NAND_DATA07__USDHC3_DATA3 0x1d4
- MX8MP_IOMUXC_NAND_RE_B__USDHC3_DATA4 0x1d4
- MX8MP_IOMUXC_NAND_CE2_B__USDHC3_DATA5 0x1d4
- MX8MP_IOMUXC_NAND_CE3_B__USDHC3_DATA6 0x1d4
- MX8MP_IOMUXC_NAND_CLE__USDHC3_DATA7 0x1d4
- MX8MP_IOMUXC_NAND_CE1_B__USDHC3_STROBE 0x194
- >;
- };
-
- pinctrl_usdhc3_200mhz: usdhc3-200mhzgrp {
- fsl,pins = <
- MX8MP_IOMUXC_NAND_WE_B__USDHC3_CLK 0x196
- MX8MP_IOMUXC_NAND_WP_B__USDHC3_CMD 0x1d6
- MX8MP_IOMUXC_NAND_DATA04__USDHC3_DATA0 0x1d6
- MX8MP_IOMUXC_NAND_DATA05__USDHC3_DATA1 0x1d6
- MX8MP_IOMUXC_NAND_DATA06__USDHC3_DATA2 0x1d6
- MX8MP_IOMUXC_NAND_DATA07__USDHC3_DATA3 0x1d6
- MX8MP_IOMUXC_NAND_RE_B__USDHC3_DATA4 0x1d6
- MX8MP_IOMUXC_NAND_CE2_B__USDHC3_DATA5 0x1d6
- MX8MP_IOMUXC_NAND_CE3_B__USDHC3_DATA6 0x1d6
- MX8MP_IOMUXC_NAND_CLE__USDHC3_DATA7 0x1d6
- MX8MP_IOMUXC_NAND_CE1_B__USDHC3_STROBE 0x196
- >;
- };
-
- pinctrl_wdog: wdoggrp {
- fsl,pins = <
- MX8MP_IOMUXC_GPIO1_IO02__WDOG1_WDOG_B 0x166
- >;
- };
-};
diff --git a/arch/arm/dts/imx8mp-venice-gw71xx-2x-u-boot.dtsi b/arch/arm/dts/imx8mp-venice-gw71xx-2x-u-boot.dtsi
index 5c33f8c..216a7a0 100644
--- a/arch/arm/dts/imx8mp-venice-gw71xx-2x-u-boot.dtsi
+++ b/arch/arm/dts/imx8mp-venice-gw71xx-2x-u-boot.dtsi
@@ -4,6 +4,15 @@
*/
#include "imx8mp-venice-gw702x-u-boot.dtsi"
+&gpio1 {
+ tpm_rst {
+ gpio-hog;
+ output-high;
+ gpios = <11 GPIO_ACTIVE_HIGH>;
+ line-name = "tpm_rst#";
+ };
+};
+
&gpio4 {
dio_1 {
gpio-hog;
diff --git a/arch/arm/dts/imx8mp-venice-gw71xx-2x.dts b/arch/arm/dts/imx8mp-venice-gw71xx-2x.dts
deleted file mode 100644
index 53120fc..0000000
--- a/arch/arm/dts/imx8mp-venice-gw71xx-2x.dts
+++ /dev/null
@@ -1,19 +0,0 @@
-// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
-/*
- * Copyright 2023 Gateworks Corporation
- */
-
-/dts-v1/;
-
-#include "imx8mp.dtsi"
-#include "imx8mp-venice-gw702x.dtsi"
-#include "imx8mp-venice-gw71xx.dtsi"
-
-/ {
- model = "Gateworks Venice GW71xx-2x i.MX8MP Development Kit";
- compatible = "gateworks,imx8mp-gw71xx-2x", "fsl,imx8mp";
-
- chosen {
- stdout-path = &uart2;
- };
-};
diff --git a/arch/arm/dts/imx8mp-venice-gw71xx.dtsi b/arch/arm/dts/imx8mp-venice-gw71xx.dtsi
deleted file mode 100644
index 86999f5..0000000
--- a/arch/arm/dts/imx8mp-venice-gw71xx.dtsi
+++ /dev/null
@@ -1,236 +0,0 @@
-// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
-/*
- * Copyright 2023 Gateworks Corporation
- */
-
-#include <dt-bindings/gpio/gpio.h>
-#include <dt-bindings/leds/common.h>
-#include <dt-bindings/phy/phy-imx8-pcie.h>
-
-/ {
- led-controller {
- compatible = "gpio-leds";
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_gpio_leds>;
-
- led-0 {
- function = LED_FUNCTION_STATUS;
- color = <LED_COLOR_ID_GREEN>;
- gpios = <&gpio4 1 GPIO_ACTIVE_HIGH>;
- default-state = "on";
- linux,default-trigger = "heartbeat";
- };
-
- led-1 {
- function = LED_FUNCTION_STATUS;
- color = <LED_COLOR_ID_RED>;
- gpios = <&gpio4 5 GPIO_ACTIVE_HIGH>;
- default-state = "off";
- };
- };
-
- pcie0_refclk: pcie0-refclk {
- compatible = "fixed-clock";
- #clock-cells = <0>;
- clock-frequency = <100000000>;
- };
-
- pps {
- compatible = "pps-gpio";
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_pps>;
- gpios = <&gpio4 3 GPIO_ACTIVE_HIGH>;
- status = "okay";
- };
-};
-
-/* off-board header */
-&ecspi2 {
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_spi2>;
- cs-gpios = <&gpio5 13 GPIO_ACTIVE_LOW>;
- status = "okay";
-};
-
-&gpio4 {
- gpio-line-names =
- "", "", "", "",
- "", "", "", "",
- "dio1", "", "", "dio0",
- "", "", "pci_usb_sel", "",
- "", "", "", "",
- "", "", "", "",
- "dio3", "", "dio2", "",
- "pci_wdis#", "", "", "";
-};
-
-&i2c2 {
- clock-frequency = <400000>;
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_i2c2>;
- status = "okay";
-
- accelerometer@19 {
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_accel>;
- compatible = "st,lis2de12";
- reg = <0x19>;
- st,drdy-int-pin = <1>;
- interrupt-parent = <&gpio4>;
- interrupts = <21 IRQ_TYPE_LEVEL_LOW>;
- interrupt-names = "INT1";
- };
-};
-
-&pcie_phy {
- fsl,refclk-pad-mode = <IMX8_PCIE_REFCLK_PAD_INPUT>;
- fsl,clkreq-unsupported;
- clocks = <&pcie0_refclk>;
- clock-names = "ref";
- status = "okay";
-};
-
-&pcie {
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_pcie0>;
- reset-gpio = <&gpio4 29 GPIO_ACTIVE_LOW>;
- status = "okay";
-};
-
-/* GPS */
-&uart1 {
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_uart1>;
- status = "okay";
-};
-
-/* off-board header */
-&uart3 {
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_uart3>;
- status = "okay";
-};
-
-/* USB1 Type-C front panel */
-&usb3_0 {
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_usb1>;
- fsl,over-current-active-low;
- status = "okay";
-};
-
-&usb3_phy0 {
- status = "okay";
-};
-
-&usb_dwc3_0 {
- /* dual role is implemented but not a full featured OTG */
- adp-disable;
- hnp-disable;
- srp-disable;
- dr_mode = "otg";
- usb-role-switch;
- role-switch-default-mode = "peripheral";
- status = "okay";
-
- connector {
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_usbcon1>;
- compatible = "gpio-usb-b-connector", "usb-b-connector";
- type = "micro";
- label = "Type-C";
- id-gpios = <&gpio3 21 GPIO_ACTIVE_HIGH>;
- };
-};
-
-/* USB2 - MiniPCIe socket */
-&usb3_1 {
- fsl,permanently-attached;
- fsl,disable-port-power-control;
- status = "okay";
-};
-
-&usb3_phy1 {
- status = "okay";
-};
-
-&usb_dwc3_1 {
- dr_mode = "host";
- status = "okay";
-};
-
-&iomuxc {
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_hog>;
-
- pinctrl_hog: hoggrp {
- fsl,pins = <
- MX8MP_IOMUXC_SAI1_RXD6__GPIO4_IO08 0x40000146 /* DIO1 */
- MX8MP_IOMUXC_SAI1_TXC__GPIO4_IO11 0x40000146 /* DIO0 */
- MX8MP_IOMUXC_SAI1_TXD2__GPIO4_IO14 0x40000106 /* PCIE_USBSEL */
- MX8MP_IOMUXC_SAI2_TXD0__GPIO4_IO26 0x40000146 /* DIO2 */
- MX8MP_IOMUXC_SAI2_TXFS__GPIO4_IO24 0x40000146 /* DIO3 */
- MX8MP_IOMUXC_SAI3_RXFS__GPIO4_IO28 0x40000106 /* PCIE_WDIS# */
- >;
- };
-
- pinctrl_accel: accelgrp {
- fsl,pins = <
- MX8MP_IOMUXC_SAI2_RXFS__GPIO4_IO21 0x150 /* IRQ */
- >;
- };
-
- pinctrl_gpio_leds: gpioledgrp {
- fsl,pins = <
- MX8MP_IOMUXC_SAI1_RXC__GPIO4_IO01 0x6 /* LEDG */
- MX8MP_IOMUXC_SAI1_RXD3__GPIO4_IO05 0x6 /* LEDR */
- >;
- };
-
- pinctrl_pcie0: pcie0grp {
- fsl,pins = <
- MX8MP_IOMUXC_SAI3_RXC__GPIO4_IO29 0x106
- >;
- };
-
- pinctrl_pps: ppsgrp {
- fsl,pins = <
- MX8MP_IOMUXC_SAI1_RXD1__GPIO4_IO03 0x146
- >;
- };
-
- pinctrl_usb1: usb1grp {
- fsl,pins = <
- MX8MP_IOMUXC_GPIO1_IO13__USB1_OTG_OC 0x140 /* USB1_FLT# */
- >;
- };
-
- pinctrl_usbcon1: usbcon1grp {
- fsl,pins = <
- MX8MP_IOMUXC_SAI5_RXD0__GPIO3_IO21 0x140 /* USB1_ID */
- >;
- };
-
- pinctrl_spi2: spi2grp {
- fsl,pins = <
- MX8MP_IOMUXC_ECSPI2_SCLK__ECSPI2_SCLK 0x140
- MX8MP_IOMUXC_ECSPI2_MOSI__ECSPI2_MOSI 0x140
- MX8MP_IOMUXC_ECSPI2_MISO__ECSPI2_MISO 0x140
- MX8MP_IOMUXC_ECSPI2_SS0__GPIO5_IO13 0x140
- >;
- };
-
- pinctrl_uart1: uart1grp {
- fsl,pins = <
- MX8MP_IOMUXC_UART1_RXD__UART1_DCE_RX 0x140
- MX8MP_IOMUXC_UART1_TXD__UART1_DCE_TX 0x140
- >;
- };
-
- pinctrl_uart3: uart3grp {
- fsl,pins = <
- MX8MP_IOMUXC_UART3_RXD__UART3_DCE_RX 0x140
- MX8MP_IOMUXC_UART3_TXD__UART3_DCE_TX 0x140
- >;
- };
-};
diff --git a/arch/arm/dts/imx8mp-venice-gw72xx-2x.dts b/arch/arm/dts/imx8mp-venice-gw72xx-2x.dts
deleted file mode 100644
index 255e36f..0000000
--- a/arch/arm/dts/imx8mp-venice-gw72xx-2x.dts
+++ /dev/null
@@ -1,19 +0,0 @@
-// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
-/*
- * Copyright 2023 Gateworks Corporation
- */
-
-/dts-v1/;
-
-#include "imx8mp.dtsi"
-#include "imx8mp-venice-gw702x.dtsi"
-#include "imx8mp-venice-gw72xx.dtsi"
-
-/ {
- model = "Gateworks Venice GW72xx-2x i.MX8MP Development Kit";
- compatible = "gateworks,imx8mp-gw72xx-2x", "fsl,imx8mp";
-
- chosen {
- stdout-path = &uart2;
- };
-};
diff --git a/arch/arm/dts/imx8mp-venice-gw72xx.dtsi b/arch/arm/dts/imx8mp-venice-gw72xx.dtsi
deleted file mode 100644
index 4e72612..0000000
--- a/arch/arm/dts/imx8mp-venice-gw72xx.dtsi
+++ /dev/null
@@ -1,378 +0,0 @@
-// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
-/*
- * Copyright 2023 Gateworks Corporation
- */
-
-#include <dt-bindings/gpio/gpio.h>
-#include <dt-bindings/leds/common.h>
-#include <dt-bindings/phy/phy-imx8-pcie.h>
-
-/ {
- led-controller {
- compatible = "gpio-leds";
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_gpio_leds>;
-
- led-0 {
- function = LED_FUNCTION_STATUS;
- color = <LED_COLOR_ID_GREEN>;
- gpios = <&gpio4 1 GPIO_ACTIVE_HIGH>;
- default-state = "on";
- linux,default-trigger = "heartbeat";
- };
-
- led-1 {
- function = LED_FUNCTION_STATUS;
- color = <LED_COLOR_ID_RED>;
- gpios = <&gpio4 5 GPIO_ACTIVE_HIGH>;
- default-state = "off";
- };
- };
-
- pcie0_refclk: pcie0-refclk {
- compatible = "fixed-clock";
- #clock-cells = <0>;
- clock-frequency = <100000000>;
- };
-
- pps {
- compatible = "pps-gpio";
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_pps>;
- gpios = <&gpio4 3 GPIO_ACTIVE_HIGH>;
- status = "okay";
- };
-
- reg_usb1_vbus: regulator-usb1 {
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_reg_usb1_en>;
- compatible = "regulator-fixed";
- regulator-name = "usb1_vbus";
- gpio = <&gpio1 12 GPIO_ACTIVE_HIGH>;
- enable-active-high;
- regulator-min-microvolt = <5000000>;
- regulator-max-microvolt = <5000000>;
- };
-
- reg_usb2_vbus: regulator-usb2 {
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_reg_usb2_en>;
- compatible = "regulator-fixed";
- regulator-name = "usb2_vbus";
- gpio = <&gpio4 12 GPIO_ACTIVE_HIGH>;
- enable-active-high;
- regulator-min-microvolt = <5000000>;
- regulator-max-microvolt = <5000000>;
- };
-
- reg_usdhc2_vmmc: regulator-usdhc2-vmmc {
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_usdhc2_vmmc>;
- compatible = "regulator-fixed";
- regulator-name = "VDD_3V3_SD";
- enable-active-high;
- gpio = <&gpio2 19 0>; /* SD2_RESET */
- off-on-delay-us = <12000>;
- regulator-max-microvolt = <3300000>;
- regulator-min-microvolt = <3300000>;
- startup-delay-us = <100>;
- };
-};
-
-/* off-board header */
-&ecspi2 {
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_spi2>;
- cs-gpios = <&gpio5 13 GPIO_ACTIVE_LOW>,
- <&gpio1 10 GPIO_ACTIVE_LOW>;
- status = "okay";
- tpm@1 {
- compatible = "tcg,tpm_tis-spi";
- reg = <0x1>;
- spi-max-frequency = <36000000>;
- };
-};
-
-&gpio4 {
- gpio-line-names =
- "", "", "", "",
- "", "", "", "",
- "dio1", "", "", "dio0",
- "", "", "pci_usb_sel", "",
- "", "", "", "",
- "", "", "rs485_en", "rs485_term",
- "", "", "", "rs485_half",
- "pci_wdis#", "", "", "";
-};
-
-&i2c2 {
- clock-frequency = <400000>;
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_i2c2>;
- status = "okay";
-
- accelerometer@19 {
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_accel>;
- compatible = "st,lis2de12";
- reg = <0x19>;
- st,drdy-int-pin = <1>;
- interrupt-parent = <&gpio4>;
- interrupts = <21 IRQ_TYPE_LEVEL_LOW>;
- interrupt-names = "INT1";
- };
-};
-
-&pcie_phy {
- fsl,refclk-pad-mode = <IMX8_PCIE_REFCLK_PAD_INPUT>;
- fsl,clkreq-unsupported;
- clocks = <&pcie0_refclk>;
- clock-names = "ref";
- status = "okay";
-};
-
-&pcie {
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_pcie0>;
- reset-gpio = <&gpio4 29 GPIO_ACTIVE_LOW>;
- status = "okay";
-};
-
-/* GPS */
-&uart1 {
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_uart1>;
- status = "okay";
-};
-
-/* off-board header */
-&uart3 {
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_uart3>;
- status = "okay";
-};
-
-/* RS232 */
-&uart4 {
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_uart4>;
- status = "okay";
-};
-
-/* USB1 - OTG */
-&usb3_0 {
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_usb1>;
- fsl,over-current-active-low;
- status = "okay";
-};
-
-&usb3_phy0 {
- vbus-supply = <®_usb1_vbus>;
- status = "okay";
-};
-
-&usb_dwc3_0 {
- /* dual role is implemented but not a full featured OTG */
- adp-disable;
- hnp-disable;
- srp-disable;
- dr_mode = "otg";
- usb-role-switch;
- role-switch-default-mode = "peripheral";
- status = "okay";
-
- connector {
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_usbcon1>;
- compatible = "gpio-usb-b-connector", "usb-b-connector";
- type = "micro";
- label = "otg";
- id-gpios = <&gpio3 21 GPIO_ACTIVE_HIGH>;
- };
-};
-
-/* USB2 - USB3.0 Hub */
-&usb3_1 {
- fsl,permanently-attached;
- fsl,disable-port-power-control;
- status = "okay";
-};
-
-&usb3_phy1 {
- vbus-supply = <®_usb2_vbus>;
- status = "okay";
-};
-
-&usb_dwc3_1 {
- dr_mode = "host";
- status = "okay";
-};
-
-/* microSD */
-&usdhc2 {
- pinctrl-names = "default", "state_100mhz", "state_200mhz";
- pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>;
- pinctrl-1 = <&pinctrl_usdhc2_100mhz>, <&pinctrl_usdhc2_gpio>;
- pinctrl-2 = <&pinctrl_usdhc2_200mhz>, <&pinctrl_usdhc2_gpio>;
- cd-gpios = <&gpio2 12 GPIO_ACTIVE_LOW>;
- bus-width = <4>;
- vmmc-supply = <®_usdhc2_vmmc>;
- status = "okay";
-};
-
-&iomuxc {
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_hog>;
-
- pinctrl_hog: hoggrp {
- fsl,pins = <
- MX8MP_IOMUXC_SAI1_RXD6__GPIO4_IO08 0x40000146 /* DIO1 */
- MX8MP_IOMUXC_SAI1_TXC__GPIO4_IO11 0x40000146 /* DIO0 */
- MX8MP_IOMUXC_SAI1_TXD2__GPIO4_IO14 0x40000106 /* PCIE_USBSEL */
- MX8MP_IOMUXC_SAI2_MCLK__GPIO4_IO27 0x40000106 /* RS485_HALF */
- MX8MP_IOMUXC_SAI2_RXC__GPIO4_IO22 0x40000106 /* RS485_EN */
- MX8MP_IOMUXC_SAI2_RXD0__GPIO4_IO23 0x40000106 /* RS485_TERM */
- MX8MP_IOMUXC_SAI3_RXFS__GPIO4_IO28 0x40000106 /* PCIE_WDIS# */
- >;
- };
-
- pinctrl_accel: accelgrp {
- fsl,pins = <
- MX8MP_IOMUXC_SAI2_RXFS__GPIO4_IO21 0x150 /* IRQ */
- >;
- };
-
- pinctrl_gpio_leds: gpioledgrp {
- fsl,pins = <
- MX8MP_IOMUXC_SAI1_RXC__GPIO4_IO01 0x6 /* LEDG */
- MX8MP_IOMUXC_SAI1_RXD3__GPIO4_IO05 0x6 /* LEDR */
- >;
- };
-
- pinctrl_pcie0: pcie0grp {
- fsl,pins = <
- MX8MP_IOMUXC_SAI3_RXC__GPIO4_IO29 0x106
- >;
- };
-
- pinctrl_pps: ppsgrp {
- fsl,pins = <
- MX8MP_IOMUXC_SAI1_RXD1__GPIO4_IO03 0x146
- >;
- };
-
- pinctrl_reg_usb1_en: regusb1grp {
- fsl,pins = <
- MX8MP_IOMUXC_GPIO1_IO12__GPIO1_IO12 0x146 /* USB1_EN */
- >;
- };
-
- pinctrl_usb1: usb1grp {
- fsl,pins = <
- MX8MP_IOMUXC_GPIO1_IO13__USB1_OTG_OC 0x140 /* USB1_FLT# */
- >;
- };
-
- pinctrl_usbcon1: usbcon1grp {
- fsl,pins = <
- MX8MP_IOMUXC_SAI5_RXD0__GPIO3_IO21 0x140 /* USB1_ID */
- >;
- };
-
- pinctrl_reg_usb2_en: regusb2grp {
- fsl,pins = <
- MX8MP_IOMUXC_SAI1_TXD0__GPIO4_IO12 0x146 /* USBHUB_RST# */
- >;
- };
-
- pinctrl_spi2: spi2grp {
- fsl,pins = <
- MX8MP_IOMUXC_ECSPI2_SCLK__ECSPI2_SCLK 0x140
- MX8MP_IOMUXC_ECSPI2_MOSI__ECSPI2_MOSI 0x140
- MX8MP_IOMUXC_ECSPI2_MISO__ECSPI2_MISO 0x140
- MX8MP_IOMUXC_ECSPI2_SS0__GPIO5_IO13 0x140
- MX8MP_IOMUXC_GPIO1_IO10__GPIO1_IO10 0x140
- >;
- };
-
- pinctrl_uart1: uart1grp {
- fsl,pins = <
- MX8MP_IOMUXC_UART1_RXD__UART1_DCE_RX 0x140
- MX8MP_IOMUXC_UART1_TXD__UART1_DCE_TX 0x140
- >;
- };
-
- pinctrl_uart3: uart3grp {
- fsl,pins = <
- MX8MP_IOMUXC_UART3_RXD__UART3_DCE_RX 0x140
- MX8MP_IOMUXC_UART3_TXD__UART3_DCE_TX 0x140
- >;
- };
-
- pinctrl_uart4: uart4grp {
- fsl,pins = <
- MX8MP_IOMUXC_UART4_RXD__UART4_DCE_RX 0x140
- MX8MP_IOMUXC_UART4_TXD__UART4_DCE_TX 0x140
- >;
- };
-
- pinctrl_usdhc1: usdhc1grp {
- fsl,pins = <
- MX8MP_IOMUXC_SD1_CLK__USDHC1_CLK 0x190
- MX8MP_IOMUXC_SD1_CMD__USDHC1_CMD 0x1d0
- MX8MP_IOMUXC_SD1_DATA0__USDHC1_DATA0 0x1d0
- MX8MP_IOMUXC_SD1_DATA1__USDHC1_DATA1 0x1d0
- MX8MP_IOMUXC_SD1_DATA2__USDHC1_DATA2 0x1d0
- MX8MP_IOMUXC_SD1_DATA3__USDHC1_DATA3 0x1d0
- >;
- };
-
- pinctrl_usdhc2: usdhc2grp {
- fsl,pins = <
- MX8MP_IOMUXC_SD2_CLK__USDHC2_CLK 0x190
- MX8MP_IOMUXC_SD2_CMD__USDHC2_CMD 0x1d0
- MX8MP_IOMUXC_SD2_DATA0__USDHC2_DATA0 0x1d0
- MX8MP_IOMUXC_SD2_DATA1__USDHC2_DATA1 0x1d0
- MX8MP_IOMUXC_SD2_DATA2__USDHC2_DATA2 0x1d0
- MX8MP_IOMUXC_SD2_DATA3__USDHC2_DATA3 0x1d0
- MX8MP_IOMUXC_GPIO1_IO04__USDHC2_VSELECT 0xc1
- >;
- };
-
- pinctrl_usdhc2_100mhz: usdhc2-100mhzgrp {
- fsl,pins = <
- MX8MP_IOMUXC_SD2_CLK__USDHC2_CLK 0x194
- MX8MP_IOMUXC_SD2_CMD__USDHC2_CMD 0x1d4
- MX8MP_IOMUXC_SD2_DATA0__USDHC2_DATA0 0x1d4
- MX8MP_IOMUXC_SD2_DATA1__USDHC2_DATA1 0x1d4
- MX8MP_IOMUXC_SD2_DATA2__USDHC2_DATA2 0x1d4
- MX8MP_IOMUXC_SD2_DATA3__USDHC2_DATA3 0x1d4
- MX8MP_IOMUXC_GPIO1_IO04__USDHC2_VSELECT 0xc1
- >;
- };
-
- pinctrl_usdhc2_200mhz: usdhc2-200mhzgrp {
- fsl,pins = <
- MX8MP_IOMUXC_SD2_CLK__USDHC2_CLK 0x196
- MX8MP_IOMUXC_SD2_CMD__USDHC2_CMD 0x1d6
- MX8MP_IOMUXC_SD2_DATA0__USDHC2_DATA0 0x1d6
- MX8MP_IOMUXC_SD2_DATA1__USDHC2_DATA1 0x1d6
- MX8MP_IOMUXC_SD2_DATA2__USDHC2_DATA2 0x1d6
- MX8MP_IOMUXC_SD2_DATA3__USDHC2_DATA3 0x1d6
- MX8MP_IOMUXC_GPIO1_IO04__USDHC2_VSELECT 0xc1
- >;
- };
-
- pinctrl_usdhc2_vmmc: usdhc2-vmmc-grp {
- fsl,pins = <
- MX8MP_IOMUXC_SD2_RESET_B__USDHC2_RESET_B 0x1d0
- >;
- };
-
- pinctrl_usdhc2_gpio: usdhc2gpiogrp {
- fsl,pins = <
- MX8MP_IOMUXC_SD2_CD_B__GPIO2_IO12 0x1c4
- >;
- };
-};
diff --git a/arch/arm/dts/imx8mp-venice-gw73xx-2x.dts b/arch/arm/dts/imx8mp-venice-gw73xx-2x.dts
deleted file mode 100644
index 000fd15..0000000
--- a/arch/arm/dts/imx8mp-venice-gw73xx-2x.dts
+++ /dev/null
@@ -1,19 +0,0 @@
-// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
-/*
- * Copyright 2023 Gateworks Corporation
- */
-
-/dts-v1/;
-
-#include "imx8mp.dtsi"
-#include "imx8mp-venice-gw702x.dtsi"
-#include "imx8mp-venice-gw73xx.dtsi"
-
-/ {
- model = "Gateworks Venice GW73xx-2x i.MX8MP Development Kit";
- compatible = "gateworks,imx8mp-gw73xx-2x", "fsl,imx8mp";
-
- chosen {
- stdout-path = &uart2;
- };
-};
diff --git a/arch/arm/dts/imx8mp-venice-gw73xx.dtsi b/arch/arm/dts/imx8mp-venice-gw73xx.dtsi
deleted file mode 100644
index 88c3c00..0000000
--- a/arch/arm/dts/imx8mp-venice-gw73xx.dtsi
+++ /dev/null
@@ -1,421 +0,0 @@
-// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
-/*
- * Copyright 2023 Gateworks Corporation
- */
-
-#include <dt-bindings/gpio/gpio.h>
-#include <dt-bindings/leds/common.h>
-#include <dt-bindings/phy/phy-imx8-pcie.h>
-
-/ {
- led-controller {
- compatible = "gpio-leds";
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_gpio_leds>;
-
- led-0 {
- function = LED_FUNCTION_STATUS;
- color = <LED_COLOR_ID_GREEN>;
- gpios = <&gpio4 1 GPIO_ACTIVE_HIGH>;
- default-state = "on";
- linux,default-trigger = "heartbeat";
- };
-
- led-1 {
- function = LED_FUNCTION_STATUS;
- color = <LED_COLOR_ID_RED>;
- gpios = <&gpio4 5 GPIO_ACTIVE_HIGH>;
- default-state = "off";
- };
- };
-
- pcie0_refclk: pcie0-refclk {
- compatible = "fixed-clock";
- #clock-cells = <0>;
- clock-frequency = <100000000>;
- };
-
- pps {
- compatible = "pps-gpio";
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_pps>;
- gpios = <&gpio4 3 GPIO_ACTIVE_HIGH>;
- status = "okay";
- };
-
- reg_usb1_vbus: regulator-usb1 {
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_reg_usb1_en>;
- compatible = "regulator-fixed";
- regulator-name = "usb1_vbus";
- gpio = <&gpio1 12 GPIO_ACTIVE_HIGH>;
- enable-active-high;
- regulator-min-microvolt = <5000000>;
- regulator-max-microvolt = <5000000>;
- };
-
- reg_usb2_vbus: regulator-usb2 {
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_reg_usb2_en>;
- compatible = "regulator-fixed";
- regulator-name = "usb2_vbus";
- gpio = <&gpio4 12 GPIO_ACTIVE_HIGH>;
- enable-active-high;
- regulator-min-microvolt = <5000000>;
- regulator-max-microvolt = <5000000>;
- };
-
- reg_wifi_en: regulator-wifi-en {
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_reg_wl>;
- compatible = "regulator-fixed";
- regulator-name = "wl";
- gpio = <&gpio4 19 GPIO_ACTIVE_HIGH>;
- startup-delay-us = <100>;
- enable-active-high;
- regulator-min-microvolt = <3300000>;
- regulator-max-microvolt = <3300000>;
- };
-
- reg_usdhc2_vmmc: regulator-usdhc2-vmmc {
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_usdhc2_vmmc>;
- compatible = "regulator-fixed";
- regulator-name = "VDD_3V3_SD";
- enable-active-high;
- gpio = <&gpio2 19 0>; /* SD2_RESET */
- off-on-delay-us = <12000>;
- regulator-max-microvolt = <3300000>;
- regulator-min-microvolt = <3300000>;
- startup-delay-us = <100>;
- };
-};
-
-/* off-board header */
-&ecspi2 {
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_spi2>;
- cs-gpios = <&gpio5 13 GPIO_ACTIVE_LOW>,
- <&gpio1 10 GPIO_ACTIVE_LOW>;
- status = "okay";
- tpm@1 {
- compatible = "tcg,tpm_tis-spi";
- reg = <0x1>;
- spi-max-frequency = <36000000>;
- };
-};
-
-&gpio4 {
- gpio-line-names =
- "", "", "", "",
- "", "", "", "",
- "dio1", "", "", "dio0",
- "", "", "pci_usb_sel", "",
- "", "", "", "",
- "", "", "rs485_en", "rs485_term",
- "", "", "", "rs485_half",
- "pci_wdis#", "", "", "";
-};
-
-&i2c2 {
- clock-frequency = <400000>;
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_i2c2>;
- status = "okay";
-
- accelerometer@19 {
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_accel>;
- compatible = "st,lis2de12";
- reg = <0x19>;
- st,drdy-int-pin = <1>;
- interrupt-parent = <&gpio4>;
- interrupts = <21 IRQ_TYPE_LEVEL_LOW>;
- interrupt-names = "INT1";
- };
-};
-
-&pcie_phy {
- fsl,refclk-pad-mode = <IMX8_PCIE_REFCLK_PAD_INPUT>;
- fsl,clkreq-unsupported;
- clocks = <&pcie0_refclk>;
- clock-names = "ref";
- status = "okay";
-};
-
-&pcie {
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_pcie0>;
- reset-gpio = <&gpio4 29 GPIO_ACTIVE_LOW>;
- status = "okay";
-};
-
-/* GPS */
-&uart1 {
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_uart1>;
- status = "okay";
-};
-
-/* bluetooth HCI */
-&uart3 {
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_uart3>, <&pinctrl_bten>;
- cts-gpios = <&gpio5 8 GPIO_ACTIVE_LOW>;
- rts-gpios = <&gpio5 9 GPIO_ACTIVE_LOW>;
- status = "okay";
-
- bluetooth {
- compatible = "brcm,bcm4330-bt";
- shutdown-gpios = <&gpio4 16 GPIO_ACTIVE_HIGH>;
- };
-};
-
-/* RS232 */
-&uart4 {
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_uart4>;
- status = "okay";
-};
-
-/* USB1 - OTG */
-&usb3_0 {
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_usb1>;
- fsl,over-current-active-low;
- status = "okay";
-};
-
-&usb3_phy0 {
- vbus-supply = <®_usb1_vbus>;
- status = "okay";
-};
-
-&usb_dwc3_0 {
- /* dual role is implemented but not a full featured OTG */
- adp-disable;
- hnp-disable;
- srp-disable;
- dr_mode = "otg";
- usb-role-switch;
- role-switch-default-mode = "peripheral";
- status = "okay";
-
- connector {
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_usbcon1>;
- compatible = "gpio-usb-b-connector", "usb-b-connector";
- type = "micro";
- label = "otg";
- id-gpios = <&gpio3 21 GPIO_ACTIVE_HIGH>;
- };
-};
-
-/* USB2 - USB3.0 Hub */
-&usb3_1 {
- fsl,permanently-attached;
- fsl,disable-port-power-control;
- status = "okay";
-};
-
-&usb3_phy1 {
- vbus-supply = <®_usb2_vbus>;
- status = "okay";
-};
-
-&usb_dwc3_1 {
- dr_mode = "host";
- status = "okay";
-};
-
-/* SDIO WiFi */
-&usdhc1 {
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_usdhc1>;
- bus-width = <4>;
- non-removable;
- vmmc-supply = <®_wifi_en>;
- status = "okay";
-};
-
-/* microSD */
-&usdhc2 {
- pinctrl-names = "default", "state_100mhz", "state_200mhz";
- pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>;
- pinctrl-1 = <&pinctrl_usdhc2_100mhz>, <&pinctrl_usdhc2_gpio>;
- pinctrl-2 = <&pinctrl_usdhc2_200mhz>, <&pinctrl_usdhc2_gpio>;
- cd-gpios = <&gpio2 12 GPIO_ACTIVE_LOW>;
- bus-width = <4>;
- vmmc-supply = <®_usdhc2_vmmc>;
- status = "okay";
-};
-
-&iomuxc {
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_hog>;
-
- pinctrl_hog: hoggrp {
- fsl,pins = <
- MX8MP_IOMUXC_SAI1_RXD6__GPIO4_IO08 0x40000146 /* DIO1 */
- MX8MP_IOMUXC_SAI1_TXC__GPIO4_IO11 0x40000146 /* DIO0 */
- MX8MP_IOMUXC_SAI1_TXD2__GPIO4_IO14 0x40000106 /* PCIE_USBSEL */
- MX8MP_IOMUXC_SAI2_MCLK__GPIO4_IO27 0x40000106 /* RS485_HALF */
- MX8MP_IOMUXC_SAI2_RXC__GPIO4_IO22 0x40000106 /* RS485_EN */
- MX8MP_IOMUXC_SAI2_RXD0__GPIO4_IO23 0x40000106 /* RS485_TERM */
- MX8MP_IOMUXC_SAI3_RXFS__GPIO4_IO28 0x40000106 /* PCIE_WDIS# */
- >;
- };
-
- pinctrl_accel: accelgrp {
- fsl,pins = <
- MX8MP_IOMUXC_SAI2_RXFS__GPIO4_IO21 0x150 /* IRQ */
- >;
- };
-
- pinctrl_bten: btengrp {
- fsl,pins = <
- MX8MP_IOMUXC_SAI1_TXD4__GPIO4_IO16 0x146
- >;
- };
-
- pinctrl_gpio_leds: gpioledgrp {
- fsl,pins = <
- MX8MP_IOMUXC_SAI1_RXC__GPIO4_IO01 0x6 /* LEDG */
- MX8MP_IOMUXC_SAI1_RXD3__GPIO4_IO05 0x6 /* LEDR */
- >;
- };
-
- pinctrl_pcie0: pcie0grp {
- fsl,pins = <
- MX8MP_IOMUXC_SAI3_RXC__GPIO4_IO29 0x106
- >;
- };
-
- pinctrl_pps: ppsgrp {
- fsl,pins = <
- MX8MP_IOMUXC_SAI1_RXD1__GPIO4_IO03 0x146
- >;
- };
-
- pinctrl_reg_wl: regwlgrp {
- fsl,pins = <
- MX8MP_IOMUXC_SAI1_TXD7__GPIO4_IO19 0x146
- >;
- };
-
- pinctrl_reg_usb1_en: regusb1grp {
- fsl,pins = <
- MX8MP_IOMUXC_GPIO1_IO12__GPIO1_IO12 0x146 /* USB1_EN */
- >;
- };
-
- pinctrl_usb1: usb1grp {
- fsl,pins = <
- MX8MP_IOMUXC_GPIO1_IO13__USB1_OTG_OC 0x140 /* USB1_FLT# */
- >;
- };
-
- pinctrl_usbcon1: usbcon1grp {
- fsl,pins = <
- MX8MP_IOMUXC_SAI5_RXD0__GPIO3_IO21 0x140 /* USB1_ID */
- >;
- };
-
- pinctrl_reg_usb2_en: regusb2grp {
- fsl,pins = <
- MX8MP_IOMUXC_SAI1_TXD0__GPIO4_IO12 0x146 /* USBHUB_RST# */
- >;
- };
-
- pinctrl_spi2: spi2grp {
- fsl,pins = <
- MX8MP_IOMUXC_ECSPI2_SCLK__ECSPI2_SCLK 0x140
- MX8MP_IOMUXC_ECSPI2_MOSI__ECSPI2_MOSI 0x140
- MX8MP_IOMUXC_ECSPI2_MISO__ECSPI2_MISO 0x140
- MX8MP_IOMUXC_ECSPI2_SS0__GPIO5_IO13 0x140
- MX8MP_IOMUXC_GPIO1_IO10__GPIO1_IO10 0x140
- >;
- };
-
- pinctrl_uart1: uart1grp {
- fsl,pins = <
- MX8MP_IOMUXC_UART1_RXD__UART1_DCE_RX 0x140
- MX8MP_IOMUXC_UART1_TXD__UART1_DCE_TX 0x140
- >;
- };
-
- pinctrl_uart3: uart3grp {
- fsl,pins = <
- MX8MP_IOMUXC_UART3_RXD__UART3_DCE_RX 0x140
- MX8MP_IOMUXC_UART3_TXD__UART3_DCE_TX 0x140
- MX8MP_IOMUXC_ECSPI1_MISO__GPIO5_IO08 0x140
- MX8MP_IOMUXC_ECSPI1_SS0__GPIO5_IO09 0x140
- >;
- };
-
- pinctrl_uart4: uart4grp {
- fsl,pins = <
- MX8MP_IOMUXC_UART4_RXD__UART4_DCE_RX 0x140
- MX8MP_IOMUXC_UART4_TXD__UART4_DCE_TX 0x140
- >;
- };
-
- pinctrl_usdhc1: usdhc1grp {
- fsl,pins = <
- MX8MP_IOMUXC_SD1_CLK__USDHC1_CLK 0x190
- MX8MP_IOMUXC_SD1_CMD__USDHC1_CMD 0x1d0
- MX8MP_IOMUXC_SD1_DATA0__USDHC1_DATA0 0x1d0
- MX8MP_IOMUXC_SD1_DATA1__USDHC1_DATA1 0x1d0
- MX8MP_IOMUXC_SD1_DATA2__USDHC1_DATA2 0x1d0
- MX8MP_IOMUXC_SD1_DATA3__USDHC1_DATA3 0x1d0
- >;
- };
-
- pinctrl_usdhc2: usdhc2grp {
- fsl,pins = <
- MX8MP_IOMUXC_SD2_CLK__USDHC2_CLK 0x190
- MX8MP_IOMUXC_SD2_CMD__USDHC2_CMD 0x1d0
- MX8MP_IOMUXC_SD2_DATA0__USDHC2_DATA0 0x1d0
- MX8MP_IOMUXC_SD2_DATA1__USDHC2_DATA1 0x1d0
- MX8MP_IOMUXC_SD2_DATA2__USDHC2_DATA2 0x1d0
- MX8MP_IOMUXC_SD2_DATA3__USDHC2_DATA3 0x1d0
- MX8MP_IOMUXC_GPIO1_IO04__USDHC2_VSELECT 0xc1
- >;
- };
-
- pinctrl_usdhc2_100mhz: usdhc2-100mhzgrp {
- fsl,pins = <
- MX8MP_IOMUXC_SD2_CLK__USDHC2_CLK 0x194
- MX8MP_IOMUXC_SD2_CMD__USDHC2_CMD 0x1d4
- MX8MP_IOMUXC_SD2_DATA0__USDHC2_DATA0 0x1d4
- MX8MP_IOMUXC_SD2_DATA1__USDHC2_DATA1 0x1d4
- MX8MP_IOMUXC_SD2_DATA2__USDHC2_DATA2 0x1d4
- MX8MP_IOMUXC_SD2_DATA3__USDHC2_DATA3 0x1d4
- MX8MP_IOMUXC_GPIO1_IO04__USDHC2_VSELECT 0xc1
- >;
- };
-
- pinctrl_usdhc2_200mhz: usdhc2-200mhzgrp {
- fsl,pins = <
- MX8MP_IOMUXC_SD2_CLK__USDHC2_CLK 0x196
- MX8MP_IOMUXC_SD2_CMD__USDHC2_CMD 0x1d6
- MX8MP_IOMUXC_SD2_DATA0__USDHC2_DATA0 0x1d6
- MX8MP_IOMUXC_SD2_DATA1__USDHC2_DATA1 0x1d6
- MX8MP_IOMUXC_SD2_DATA2__USDHC2_DATA2 0x1d6
- MX8MP_IOMUXC_SD2_DATA3__USDHC2_DATA3 0x1d6
- MX8MP_IOMUXC_GPIO1_IO04__USDHC2_VSELECT 0xc1
- >;
- };
-
- pinctrl_usdhc2_vmmc: usdhc2-vmmc-grp {
- fsl,pins = <
- MX8MP_IOMUXC_SD2_RESET_B__USDHC2_RESET_B 0x1d0
- >;
- };
-
- pinctrl_usdhc2_gpio: usdhc2gpiogrp {
- fsl,pins = <
- MX8MP_IOMUXC_SD2_CD_B__GPIO2_IO12 0x1c4
- >;
- };
-};
diff --git a/arch/arm/dts/imx8mp-venice-gw74xx.dts b/arch/arm/dts/imx8mp-venice-gw74xx.dts
deleted file mode 100644
index 7eb2853..0000000
--- a/arch/arm/dts/imx8mp-venice-gw74xx.dts
+++ /dev/null
@@ -1,1125 +0,0 @@
-// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
-/*
- * Copyright 2021 Gateworks Corporation
- */
-
-/dts-v1/;
-
-#include <dt-bindings/gpio/gpio.h>
-#include <dt-bindings/input/linux-event-codes.h>
-#include <dt-bindings/leds/common.h>
-#include <dt-bindings/phy/phy-imx8-pcie.h>
-
-#include "imx8mp.dtsi"
-
-/ {
- model = "Gateworks Venice GW74xx i.MX8MP board";
- compatible = "gateworks,imx8mp-gw74xx", "fsl,imx8mp";
-
- aliases {
- ethernet0 = &eqos;
- ethernet1 = &fec;
- ethernet2 = &lan1;
- ethernet3 = &lan2;
- ethernet4 = &lan3;
- ethernet5 = &lan4;
- ethernet6 = &lan5;
- };
-
- chosen {
- stdout-path = &uart2;
- };
-
- memory@40000000 {
- device_type = "memory";
- reg = <0x0 0x40000000 0 0x80000000>;
- };
-
- gpio-keys {
- compatible = "gpio-keys";
-
- key-0 {
- label = "user_pb";
- gpios = <&gpio 2 GPIO_ACTIVE_LOW>;
- linux,code = <BTN_0>;
- };
-
- key-1 {
- label = "user_pb1x";
- linux,code = <BTN_1>;
- interrupt-parent = <&gsc>;
- interrupts = <0>;
- };
-
- key-2 {
- label = "key_erased";
- linux,code = <BTN_2>;
- interrupt-parent = <&gsc>;
- interrupts = <1>;
- };
-
- key-3 {
- label = "eeprom_wp";
- linux,code = <BTN_3>;
- interrupt-parent = <&gsc>;
- interrupts = <2>;
- };
-
- key-4 {
- label = "tamper";
- linux,code = <BTN_4>;
- interrupt-parent = <&gsc>;
- interrupts = <5>;
- };
-
- key-5 {
- label = "switch_hold";
- linux,code = <BTN_5>;
- interrupt-parent = <&gsc>;
- interrupts = <7>;
- };
- };
-
- led-controller {
- compatible = "gpio-leds";
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_gpio_leds>;
-
- led-0 {
- function = LED_FUNCTION_HEARTBEAT;
- color = <LED_COLOR_ID_GREEN>;
- gpios = <&gpio2 15 GPIO_ACTIVE_HIGH>;
- default-state = "on";
- linux,default-trigger = "heartbeat";
- };
-
- led-1 {
- function = LED_FUNCTION_STATUS;
- color = <LED_COLOR_ID_RED>;
- gpios = <&gpio2 16 GPIO_ACTIVE_HIGH>;
- default-state = "off";
- };
- };
-
- pcie0_refclk: pcie0-refclk {
- compatible = "fixed-clock";
- #clock-cells = <0>;
- clock-frequency = <100000000>;
- };
-
- pps {
- compatible = "pps-gpio";
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_pps>;
- gpios = <&gpio1 12 GPIO_ACTIVE_HIGH>;
- };
-
- reg_usb2_vbus: regulator-usb2 {
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_reg_usb2>;
- compatible = "regulator-fixed";
- regulator-name = "usb_usb2_vbus";
- gpio = <&gpio1 6 GPIO_ACTIVE_HIGH>;
- enable-active-high;
- regulator-min-microvolt = <5000000>;
- regulator-max-microvolt = <5000000>;
- };
-
- reg_can1_stby: regulator-can1-stby {
- compatible = "regulator-fixed";
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_reg_can1>;
- regulator-name = "can1_stby";
- gpio = <&gpio3 19 GPIO_ACTIVE_LOW>;
- regulator-min-microvolt = <3300000>;
- regulator-max-microvolt = <3300000>;
- };
-
- reg_can2_stby: regulator-can2-stby {
- compatible = "regulator-fixed";
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_reg_can2>;
- regulator-name = "can2_stby";
- gpio = <&gpio5 5 GPIO_ACTIVE_LOW>;
- regulator-min-microvolt = <3300000>;
- regulator-max-microvolt = <3300000>;
- };
-
- reg_wifi_en: regulator-wifi-en {
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_reg_wifi>;
- compatible = "regulator-fixed";
- regulator-name = "wl";
- gpio = <&gpio3 9 GPIO_ACTIVE_HIGH>;
- startup-delay-us = <70000>;
- enable-active-high;
- regulator-min-microvolt = <3300000>;
- regulator-max-microvolt = <3300000>;
- };
-};
-
-&A53_0 {
- cpu-supply = <®_arm>;
-};
-
-&A53_1 {
- cpu-supply = <®_arm>;
-};
-
-&A53_2 {
- cpu-supply = <®_arm>;
-};
-
-&A53_3 {
- cpu-supply = <®_arm>;
-};
-
-&ecspi1 {
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_spi1>;
- cs-gpios = <&gpio5 9 GPIO_ACTIVE_LOW>;
- status = "okay";
-
- tpm@0 {
- compatible = "tcg,tpm_tis-spi";
- #address-cells = <0x1>;
- #size-cells = <0x1>;
- reg = <0x0>;
- spi-max-frequency = <36000000>;
- };
-};
-
-/* off-board header */
-&ecspi2 {
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_spi2>;
- cs-gpios = <&gpio5 13 GPIO_ACTIVE_LOW>;
- status = "okay";
-};
-
-&eqos {
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_eqos>;
- phy-mode = "rgmii-id";
- phy-handle = <ðphy0>;
- status = "okay";
-
- mdio {
- compatible = "snps,dwmac-mdio";
- #address-cells = <1>;
- #size-cells = <0>;
-
- ethphy0: ethernet-phy@0 {
- compatible = "ethernet-phy-ieee802.3-c22";
- reg = <0x0>;
- };
- };
-};
-
-&fec {
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_fec>;
- phy-mode = "rgmii-id";
- local-mac-address = [00 00 00 00 00 00];
- status = "okay";
-
- fixed-link {
- speed = <1000>;
- full-duplex;
- };
-};
-
-&flexcan1 {
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_flexcan1>;
- xceiver-supply = <®_can1_stby>;
- status = "okay";
-};
-
-&flexcan2 {
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_flexcan2>;
- xceiver-supply = <®_can2_stby>;
- status = "okay";
-};
-
-&gpio1 {
- gpio-line-names =
- "", "", "", "", "", "", "", "",
- "", "dio0", "", "dio1", "", "", "", "",
- "", "", "", "", "", "", "", "",
- "", "", "", "", "", "", "", "";
-};
-
-&gpio2 {
- gpio-line-names =
- "", "", "", "", "", "", "m2_pin20", "",
- "", "", "", "", "", "pcie1_wdis#", "pcie3_wdis#", "",
- "", "", "pcie2_wdis#", "", "", "", "", "",
- "", "", "", "", "", "", "", "";
-};
-
-&gpio3 {
- gpio-line-names =
- "", "", "", "", "", "", "m2_rst", "",
- "", "", "", "", "", "", "", "",
- "", "", "", "", "", "", "", "",
- "", "", "", "", "", "", "", "";
-};
-
-&gpio4 {
- gpio-line-names =
- "", "", "m2_off#", "", "", "", "", "",
- "", "", "", "", "", "", "", "",
- "", "", "m2_wdis#", "", "", "", "", "",
- "", "", "", "", "", "", "", "rs485_en";
-};
-
-&gpio5 {
- gpio-line-names =
- "rs485_hd", "rs485_term", "", "", "", "", "", "",
- "", "", "", "", "", "", "", "",
- "", "", "", "", "", "", "", "",
- "", "", "", "", "", "", "", "";
-};
-
-&i2c1 {
- clock-frequency = <100000>;
- pinctrl-names = "default", "gpio";
- pinctrl-0 = <&pinctrl_i2c1>;
- pinctrl-1 = <&pinctrl_i2c1_gpio>;
- scl-gpios = <&gpio5 14 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
- sda-gpios = <&gpio5 15 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
- status = "okay";
-
- gsc: gsc@20 {
- compatible = "gw,gsc";
- reg = <0x20>;
- pinctrl-0 = <&pinctrl_gsc>;
- interrupt-parent = <&gpio4>;
- interrupts = <20 IRQ_TYPE_EDGE_FALLING>;
- interrupt-controller;
- #interrupt-cells = <1>;
- #address-cells = <1>;
- #size-cells = <0>;
-
- adc {
- compatible = "gw,gsc-adc";
- #address-cells = <1>;
- #size-cells = <0>;
-
- channel@6 {
- gw,mode = <0>;
- reg = <0x06>;
- label = "temp";
- };
-
- channel@8 {
- gw,mode = <1>;
- reg = <0x08>;
- label = "vdd_bat";
- };
-
- channel@16 {
- gw,mode = <4>;
- reg = <0x16>;
- label = "fan_tach";
- };
-
- channel@82 {
- gw,mode = <2>;
- reg = <0x82>;
- label = "vdd_adc1";
- gw,voltage-divider-ohms = <10000 10000>;
- };
-
- channel@84 {
- gw,mode = <2>;
- reg = <0x84>;
- label = "vdd_adc2";
- gw,voltage-divider-ohms = <10000 10000>;
- };
-
- channel@86 {
- gw,mode = <2>;
- reg = <0x86>;
- label = "vdd_vin";
- gw,voltage-divider-ohms = <22100 1000>;
- };
-
- channel@88 {
- gw,mode = <2>;
- reg = <0x88>;
- label = "vdd_3p3";
- gw,voltage-divider-ohms = <10000 10000>;
- };
-
- channel@8c {
- gw,mode = <2>;
- reg = <0x8c>;
- label = "vdd_2p5";
- gw,voltage-divider-ohms = <10000 10000>;
- };
-
- channel@90 {
- gw,mode = <2>;
- reg = <0x90>;
- label = "vdd_soc";
- };
-
- channel@92 {
- gw,mode = <2>;
- reg = <0x92>;
- label = "vdd_arm";
- };
-
- channel@98 {
- gw,mode = <2>;
- reg = <0x98>;
- label = "vdd_1p8";
- };
-
- channel@9a {
- gw,mode = <2>;
- reg = <0x9a>;
- label = "vdd_1p2";
- };
-
- channel@9c {
- gw,mode = <2>;
- reg = <0x9c>;
- label = "vdd_dram";
- };
-
- channel@a2 {
- gw,mode = <2>;
- reg = <0xa2>;
- label = "vdd_gsc";
- gw,voltage-divider-ohms = <10000 10000>;
- };
- };
-
- fan-controller@a {
- compatible = "gw,gsc-fan";
- reg = <0x0a>;
- };
- };
-
- gpio: gpio@23 {
- compatible = "nxp,pca9555";
- reg = <0x23>;
- gpio-controller;
- #gpio-cells = <2>;
- interrupt-parent = <&gsc>;
- interrupts = <4>;
- };
-
- eeprom@50 {
- compatible = "atmel,24c02";
- reg = <0x50>;
- pagesize = <16>;
- };
-
- eeprom@51 {
- compatible = "atmel,24c02";
- reg = <0x51>;
- pagesize = <16>;
- };
-
- eeprom@52 {
- compatible = "atmel,24c02";
- reg = <0x52>;
- pagesize = <16>;
- };
-
- eeprom@53 {
- compatible = "atmel,24c02";
- reg = <0x53>;
- pagesize = <16>;
- };
-
- rtc@68 {
- compatible = "dallas,ds1672";
- reg = <0x68>;
- };
-};
-
-&i2c2 {
- clock-frequency = <400000>;
- pinctrl-names = "default", "gpio";
- pinctrl-0 = <&pinctrl_i2c2>;
- pinctrl-1 = <&pinctrl_i2c2_gpio>;
- scl-gpios = <&gpio5 16 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
- sda-gpios = <&gpio5 17 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
- status = "okay";
-
- accelerometer@19 {
- compatible = "st,lis2de12";
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_accel>;
- reg = <0x19>;
- st,drdy-int-pin = <1>;
- interrupt-parent = <&gpio1>;
- interrupts = <7 IRQ_TYPE_LEVEL_LOW>;
- interrupt-names = "INT1";
- };
-
- switch: switch@5f {
- compatible = "microchip,ksz9897";
- reg = <0x5f>;
- pinctrl-0 = <&pinctrl_ksz>;
- interrupt-parent = <&gpio4>;
- interrupts = <29 IRQ_TYPE_EDGE_FALLING>;
-
- ports {
- #address-cells = <1>;
- #size-cells = <0>;
-
- lan1: port@0 {
- reg = <0>;
- label = "lan1";
- phy-mode = "internal";
- local-mac-address = [00 00 00 00 00 00];
- };
-
- lan2: port@1 {
- reg = <1>;
- label = "lan2";
- phy-mode = "internal";
- local-mac-address = [00 00 00 00 00 00];
- };
-
- lan3: port@2 {
- reg = <2>;
- label = "lan3";
- phy-mode = "internal";
- local-mac-address = [00 00 00 00 00 00];
- };
-
- lan4: port@3 {
- reg = <3>;
- label = "lan4";
- phy-mode = "internal";
- local-mac-address = [00 00 00 00 00 00];
- };
-
- lan5: port@4 {
- reg = <4>;
- label = "lan5";
- phy-mode = "internal";
- local-mac-address = [00 00 00 00 00 00];
- };
-
- port@5 {
- reg = <5>;
- label = "cpu";
- ethernet = <&fec>;
- phy-mode = "rgmii-id";
-
- fixed-link {
- speed = <1000>;
- full-duplex;
- };
- };
- };
- };
-};
-
-&i2c3 {
- clock-frequency = <400000>;
- pinctrl-names = "default", "gpio";
- pinctrl-0 = <&pinctrl_i2c3>;
- pinctrl-1 = <&pinctrl_i2c3_gpio>;
- scl-gpios = <&gpio5 18 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
- sda-gpios = <&gpio5 19 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
- status = "okay";
-
- pmic@25 {
- compatible = "nxp,pca9450c";
- reg = <0x25>;
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_pmic>;
- interrupt-parent = <&gpio3>;
- interrupts = <7 IRQ_TYPE_LEVEL_LOW>;
-
- regulators {
- BUCK1 {
- regulator-name = "BUCK1";
- regulator-min-microvolt = <720000>;
- regulator-max-microvolt = <1000000>;
- regulator-boot-on;
- regulator-always-on;
- regulator-ramp-delay = <3125>;
- };
-
- reg_arm: BUCK2 {
- regulator-name = "BUCK2";
- regulator-min-microvolt = <720000>;
- regulator-max-microvolt = <1025000>;
- regulator-boot-on;
- regulator-always-on;
- regulator-ramp-delay = <3125>;
- nxp,dvs-run-voltage = <950000>;
- nxp,dvs-standby-voltage = <850000>;
- };
-
- BUCK4 {
- regulator-name = "BUCK4";
- regulator-min-microvolt = <3000000>;
- regulator-max-microvolt = <3600000>;
- regulator-boot-on;
- regulator-always-on;
- };
-
- BUCK5 {
- regulator-name = "BUCK5";
- regulator-min-microvolt = <1650000>;
- regulator-max-microvolt = <1950000>;
- regulator-boot-on;
- regulator-always-on;
- };
-
- BUCK6 {
- regulator-name = "BUCK6";
- regulator-min-microvolt = <1045000>;
- regulator-max-microvolt = <1155000>;
- regulator-boot-on;
- regulator-always-on;
- };
-
- LDO1 {
- regulator-name = "LDO1";
- regulator-min-microvolt = <1650000>;
- regulator-max-microvolt = <1950000>;
- regulator-boot-on;
- regulator-always-on;
- };
-
- LDO3 {
- regulator-name = "LDO3";
- regulator-min-microvolt = <1710000>;
- regulator-max-microvolt = <1890000>;
- regulator-boot-on;
- regulator-always-on;
- };
-
- LDO5 {
- regulator-name = "LDO5";
- regulator-min-microvolt = <1800000>;
- regulator-max-microvolt = <3300000>;
- regulator-boot-on;
- regulator-always-on;
- };
- };
- };
-};
-
-/* off-board header */
-&i2c4 {
- clock-frequency = <400000>;
- pinctrl-names = "default", "gpio";
- pinctrl-0 = <&pinctrl_i2c4>;
- pinctrl-1 = <&pinctrl_i2c4_gpio>;
- scl-gpios = <&gpio5 20 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
- sda-gpios = <&gpio5 21 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
- status = "okay";
-};
-
-&pcie_phy {
- fsl,refclk-pad-mode = <IMX8_PCIE_REFCLK_PAD_INPUT>;
- fsl,clkreq-unsupported;
- clocks = <&pcie0_refclk>;
- clock-names = "ref";
- status = "okay";
-};
-
-&pcie {
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_pcie0>;
- reset-gpio = <&gpio2 17 GPIO_ACTIVE_LOW>;
- clocks = <&clk IMX8MP_CLK_HSIO_ROOT>,
- <&clk IMX8MP_CLK_PCIE_ROOT>,
- <&clk IMX8MP_CLK_HSIO_AXI>;
- clock-names = "pcie", "pcie_aux", "pcie_bus";
- assigned-clocks = <&clk IMX8MP_CLK_PCIE_AUX>;
- assigned-clock-rates = <10000000>;
- assigned-clock-parents = <&clk IMX8MP_SYS_PLL2_50M>;
- status = "okay";
-};
-
-/* GPS / off-board header */
-&uart1 {
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_uart1>;
- status = "okay";
-};
-
-/* RS232 console */
-&uart2 {
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_uart2>;
- status = "okay";
-};
-
-/* bluetooth HCI */
-&uart3 {
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_uart3>, <&pinctrl_uart3_gpio>;
- cts-gpios = <&gpio3 21 GPIO_ACTIVE_LOW>;
- rts-gpios = <&gpio3 22 GPIO_ACTIVE_LOW>;
- uart-has-rtscts;
- status = "okay";
-
- bluetooth {
- compatible = "brcm,bcm4330-bt";
- shutdown-gpios = <&gpio3 8 GPIO_ACTIVE_HIGH>;
- };
-};
-
-&uart4 {
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_uart4>;
- status = "okay";
-};
-
-/* USB1 - Type C front panel */
-&usb3_0 {
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_usb1>;
- fsl,over-current-active-low;
- status = "okay";
-};
-
-&usb3_phy0 {
- status = "okay";
-};
-
-&usb_dwc3_0 {
- /* dual role is implemented but not a full featured OTG */
- adp-disable;
- hnp-disable;
- srp-disable;
- dr_mode = "otg";
- usb-role-switch;
- role-switch-default-mode = "peripheral";
- status = "okay";
-
- connector {
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_usbcon1>;
- compatible = "gpio-usb-b-connector", "usb-b-connector";
- type = "micro";
- label = "Type-C";
- id-gpios = <&gpio1 10 GPIO_ACTIVE_HIGH>;
- };
-};
-
-/* USB2 - USB3.0 Hub */
-&usb3_phy1 {
- vbus-supply = <®_usb2_vbus>;
- status = "okay";
-};
-
-&usb3_1 {
- fsl,permanently-attached;
- fsl,disable-port-power-control;
- status = "okay";
-};
-
-&usb_dwc3_1 {
- dr_mode = "host";
- status = "okay";
-};
-
-/* SDIO WiFi */
-&usdhc1 {
- pinctrl-names = "default", "state_100mhz", "state_200mhz";
- pinctrl-0 = <&pinctrl_usdhc1>;
- pinctrl-1 = <&pinctrl_usdhc1_100mhz>;
- pinctrl-2 = <&pinctrl_usdhc1_200mhz>;
- bus-width = <4>;
- non-removable;
- vmmc-supply = <®_wifi_en>;
- #address-cells = <1>;
- #size-cells = <0>;
- status = "okay";
-
- wifi@0 {
- compatible = "cypress,cyw4373-fmac";
- reg = <0>;
- };
-};
-
-/* eMMC */
-&usdhc3 {
- assigned-clocks = <&clk IMX8MP_CLK_USDHC3>;
- assigned-clock-rates = <400000000>;
- pinctrl-names = "default", "state_100mhz", "state_200mhz";
- pinctrl-0 = <&pinctrl_usdhc3>;
- pinctrl-1 = <&pinctrl_usdhc3_100mhz>;
- pinctrl-2 = <&pinctrl_usdhc3_200mhz>;
- bus-width = <8>;
- non-removable;
- status = "okay";
-};
-
-&wdog1 {
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_wdog>;
- fsl,ext-reset-output;
- status = "okay";
-};
-
-&iomuxc {
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_hog>;
-
- pinctrl_hog: hoggrp {
- fsl,pins = <
- MX8MP_IOMUXC_GPIO1_IO09__GPIO1_IO09 0x40000040 /* DIO0 */
- MX8MP_IOMUXC_GPIO1_IO11__GPIO1_IO11 0x40000040 /* DIO1 */
- MX8MP_IOMUXC_SAI1_RXD0__GPIO4_IO02 0x40000040 /* M2SKT_OFF# */
- MX8MP_IOMUXC_SAI1_TXD6__GPIO4_IO18 0x40000150 /* M2SKT_WDIS# */
- MX8MP_IOMUXC_SD1_DATA4__GPIO2_IO06 0x40000040 /* M2SKT_PIN20 */
- MX8MP_IOMUXC_SD1_STROBE__GPIO2_IO11 0x40000040 /* M2SKT_PIN22 */
- MX8MP_IOMUXC_SD2_CLK__GPIO2_IO13 0x40000150 /* PCIE1_WDIS# */
- MX8MP_IOMUXC_SD2_CMD__GPIO2_IO14 0x40000150 /* PCIE3_WDIS# */
- MX8MP_IOMUXC_SD2_DATA3__GPIO2_IO18 0x40000150 /* PCIE2_WDIS# */
- MX8MP_IOMUXC_NAND_DATA00__GPIO3_IO06 0x40000040 /* M2SKT_RST# */
- MX8MP_IOMUXC_SAI3_TXD__GPIO5_IO01 0x40000104 /* UART_TERM */
- MX8MP_IOMUXC_SAI3_TXFS__GPIO4_IO31 0x40000104 /* UART_RS485 */
- MX8MP_IOMUXC_SAI3_TXC__GPIO5_IO00 0x40000104 /* UART_HALF */
- >;
- };
-
- pinctrl_accel: accelgrp {
- fsl,pins = <
- MX8MP_IOMUXC_GPIO1_IO07__GPIO1_IO07 0x150
- >;
- };
-
- pinctrl_eqos: eqosgrp {
- fsl,pins = <
- MX8MP_IOMUXC_ENET_MDC__ENET_QOS_MDC 0x2
- MX8MP_IOMUXC_ENET_MDIO__ENET_QOS_MDIO 0x2
- MX8MP_IOMUXC_ENET_RD0__ENET_QOS_RGMII_RD0 0x90
- MX8MP_IOMUXC_ENET_RD1__ENET_QOS_RGMII_RD1 0x90
- MX8MP_IOMUXC_ENET_RD2__ENET_QOS_RGMII_RD2 0x90
- MX8MP_IOMUXC_ENET_RD3__ENET_QOS_RGMII_RD3 0x90
- MX8MP_IOMUXC_ENET_RXC__CCM_ENET_QOS_CLOCK_GENERATE_RX_CLK 0x90
- MX8MP_IOMUXC_ENET_RX_CTL__ENET_QOS_RGMII_RX_CTL 0x90
- MX8MP_IOMUXC_ENET_TD0__ENET_QOS_RGMII_TD0 0x16
- MX8MP_IOMUXC_ENET_TD1__ENET_QOS_RGMII_TD1 0x16
- MX8MP_IOMUXC_ENET_TD2__ENET_QOS_RGMII_TD2 0x16
- MX8MP_IOMUXC_ENET_TD3__ENET_QOS_RGMII_TD3 0x16
- MX8MP_IOMUXC_ENET_TX_CTL__ENET_QOS_RGMII_TX_CTL 0x16
- MX8MP_IOMUXC_ENET_TXC__CCM_ENET_QOS_CLOCK_GENERATE_TX_CLK 0x16
- MX8MP_IOMUXC_SAI3_RXD__GPIO4_IO30 0x140 /* RST# */
- MX8MP_IOMUXC_SAI3_RXFS__GPIO4_IO28 0x150 /* IRQ# */
- >;
- };
-
- pinctrl_fec: fecgrp {
- fsl,pins = <
- MX8MP_IOMUXC_SAI1_RXD4__ENET1_RGMII_RD0 0x90
- MX8MP_IOMUXC_SAI1_RXD5__ENET1_RGMII_RD1 0x90
- MX8MP_IOMUXC_SAI1_RXD6__ENET1_RGMII_RD2 0x90
- MX8MP_IOMUXC_SAI1_RXD7__ENET1_RGMII_RD3 0x90
- MX8MP_IOMUXC_SAI1_TXC__ENET1_RGMII_RXC 0x90
- MX8MP_IOMUXC_SAI1_TXFS__ENET1_RGMII_RX_CTL 0x90
- MX8MP_IOMUXC_SAI1_TXD0__ENET1_RGMII_TD0 0x16
- MX8MP_IOMUXC_SAI1_TXD1__ENET1_RGMII_TD1 0x16
- MX8MP_IOMUXC_SAI1_TXD2__ENET1_RGMII_TD2 0x16
- MX8MP_IOMUXC_SAI1_TXD3__ENET1_RGMII_TD3 0x16
- MX8MP_IOMUXC_SAI1_TXD4__ENET1_RGMII_TX_CTL 0x16
- MX8MP_IOMUXC_SAI1_TXD5__ENET1_RGMII_TXC 0x16
- MX8MP_IOMUXC_SAI1_RXFS__ENET1_1588_EVENT0_IN 0x140
- MX8MP_IOMUXC_SAI1_RXC__ENET1_1588_EVENT0_OUT 0x140
- >;
- };
-
- pinctrl_flexcan1: flexcan1grp {
- fsl,pins = <
- MX8MP_IOMUXC_SPDIF_RX__CAN1_RX 0x154
- MX8MP_IOMUXC_SPDIF_TX__CAN1_TX 0x154
- >;
- };
-
- pinctrl_flexcan2: flexcan2grp {
- fsl,pins = <
- MX8MP_IOMUXC_SAI5_RXD3__CAN2_TX 0x154
- MX8MP_IOMUXC_SAI5_MCLK__CAN2_RX 0x154
- >;
- };
-
- pinctrl_gsc: gscgrp {
- fsl,pins = <
- MX8MP_IOMUXC_SAI1_MCLK__GPIO4_IO20 0x150
- >;
- };
-
- pinctrl_i2c1: i2c1grp {
- fsl,pins = <
- MX8MP_IOMUXC_I2C1_SCL__I2C1_SCL 0x400001c2
- MX8MP_IOMUXC_I2C1_SDA__I2C1_SDA 0x400001c2
- >;
- };
-
- pinctrl_i2c1_gpio: i2c1gpiogrp {
- fsl,pins = <
- MX8MP_IOMUXC_I2C1_SCL__GPIO5_IO14 0x400001c2
- MX8MP_IOMUXC_I2C1_SDA__GPIO5_IO15 0x400001c2
- >;
- };
-
- pinctrl_i2c2: i2c2grp {
- fsl,pins = <
- MX8MP_IOMUXC_I2C2_SCL__I2C2_SCL 0x400001c2
- MX8MP_IOMUXC_I2C2_SDA__I2C2_SDA 0x400001c2
- >;
- };
-
- pinctrl_i2c2_gpio: i2c2gpiogrp {
- fsl,pins = <
- MX8MP_IOMUXC_I2C2_SCL__GPIO5_IO16 0x400001c3
- MX8MP_IOMUXC_I2C2_SDA__GPIO5_IO17 0x400001c3
- >;
- };
-
- pinctrl_i2c3: i2c3grp {
- fsl,pins = <
- MX8MP_IOMUXC_I2C3_SCL__I2C3_SCL 0x400001c2
- MX8MP_IOMUXC_I2C3_SDA__I2C3_SDA 0x400001c2
- >;
- };
-
- pinctrl_i2c3_gpio: i2c3gpiogrp {
- fsl,pins = <
- MX8MP_IOMUXC_I2C3_SCL__GPIO5_IO18 0x400001c3
- MX8MP_IOMUXC_I2C3_SDA__GPIO5_IO19 0x400001c3
- >;
- };
-
- pinctrl_i2c4: i2c4grp {
- fsl,pins = <
- MX8MP_IOMUXC_I2C4_SCL__I2C4_SCL 0x400001c2
- MX8MP_IOMUXC_I2C4_SDA__I2C4_SDA 0x400001c2
- >;
- };
-
- pinctrl_i2c4_gpio: i2c4gpiogrp {
- fsl,pins = <
- MX8MP_IOMUXC_I2C4_SCL__GPIO5_IO20 0x400001c3
- MX8MP_IOMUXC_I2C4_SDA__GPIO5_IO21 0x400001c3
- >;
- };
-
- pinctrl_ksz: kszgrp {
- fsl,pins = <
- MX8MP_IOMUXC_SAI3_RXC__GPIO4_IO29 0x150 /* IRQ# */
- MX8MP_IOMUXC_SAI3_MCLK__GPIO5_IO02 0x140 /* RST# */
- >;
- };
-
- pinctrl_gpio_leds: ledgrp {
- fsl,pins = <
- MX8MP_IOMUXC_SD2_DATA0__GPIO2_IO15 0x10
- MX8MP_IOMUXC_SD2_DATA1__GPIO2_IO16 0x10
- >;
- };
-
- pinctrl_pcie0: pciegrp {
- fsl,pins = <
- MX8MP_IOMUXC_SD2_DATA2__GPIO2_IO17 0x106
- >;
- };
-
- pinctrl_pmic: pmicgrp {
- fsl,pins = <
- MX8MP_IOMUXC_NAND_DATA01__GPIO3_IO07 0x140
- >;
- };
-
- pinctrl_pps: ppsgrp {
- fsl,pins = <
- MX8MP_IOMUXC_GPIO1_IO12__GPIO1_IO12 0x140
- >;
- };
-
- pinctrl_reg_can1: regcan1grp {
- fsl,pins = <
- MX8MP_IOMUXC_SAI5_RXFS__GPIO3_IO19 0x154
- >;
- };
-
- pinctrl_reg_can2: regcan2grp {
- fsl,pins = <
- MX8MP_IOMUXC_SPDIF_EXT_CLK__GPIO5_IO05 0x154
- >;
- };
-
- pinctrl_reg_usb2: regusb2grp {
- fsl,pins = <
- MX8MP_IOMUXC_GPIO1_IO06__GPIO1_IO06 0x140
- >;
- };
-
- pinctrl_reg_wifi: regwifigrp {
- fsl,pins = <
- MX8MP_IOMUXC_NAND_DATA03__GPIO3_IO09 0x110
- >;
- };
-
- pinctrl_spi1: spi1grp {
- fsl,pins = <
- MX8MP_IOMUXC_ECSPI1_SCLK__ECSPI1_SCLK 0x82
- MX8MP_IOMUXC_ECSPI1_MOSI__ECSPI1_MOSI 0x82
- MX8MP_IOMUXC_ECSPI1_MISO__ECSPI1_MISO 0x82
- MX8MP_IOMUXC_ECSPI1_SS0__GPIO5_IO09 0x140
- >;
- };
-
- pinctrl_spi2: spi2grp {
- fsl,pins = <
- MX8MP_IOMUXC_ECSPI2_SCLK__ECSPI2_SCLK 0x82
- MX8MP_IOMUXC_ECSPI2_MOSI__ECSPI2_MOSI 0x82
- MX8MP_IOMUXC_ECSPI2_MISO__ECSPI2_MISO 0x82
- MX8MP_IOMUXC_ECSPI2_SS0__GPIO5_IO13 0x140
- >;
- };
-
- pinctrl_uart1: uart1grp {
- fsl,pins = <
- MX8MP_IOMUXC_UART1_RXD__UART1_DCE_RX 0x140
- MX8MP_IOMUXC_UART1_TXD__UART1_DCE_TX 0x140
- >;
- };
-
- pinctrl_uart2: uart2grp {
- fsl,pins = <
- MX8MP_IOMUXC_UART2_RXD__UART2_DCE_RX 0x140
- MX8MP_IOMUXC_UART2_TXD__UART2_DCE_TX 0x140
- >;
- };
-
- pinctrl_uart3: uart3grp {
- fsl,pins = <
- MX8MP_IOMUXC_UART3_RXD__UART3_DCE_RX 0x140
- MX8MP_IOMUXC_UART3_TXD__UART3_DCE_TX 0x140
- MX8MP_IOMUXC_SAI5_RXD0__GPIO3_IO21 0x140
- MX8MP_IOMUXC_SAI5_RXD1__GPIO3_IO22 0x140
- >;
- };
-
- pinctrl_uart3_gpio: uart3gpiogrp {
- fsl,pins = <
- MX8MP_IOMUXC_NAND_DATA02__GPIO3_IO08 0x110
- >;
- };
-
- pinctrl_uart4: uart4grp {
- fsl,pins = <
- MX8MP_IOMUXC_UART4_RXD__UART4_DCE_RX 0x140
- MX8MP_IOMUXC_UART4_TXD__UART4_DCE_TX 0x140
- >;
- };
-
- pinctrl_usb1: usb1grp {
- fsl,pins = <
- MX8MP_IOMUXC_GPIO1_IO13__USB1_OTG_OC 0x140
- >;
- };
-
- pinctrl_usbcon1: usb1congrp {
- fsl,pins = <
- MX8MP_IOMUXC_GPIO1_IO10__GPIO1_IO10 0x140
- >;
- };
-
- pinctrl_usdhc1: usdhc1grp {
- fsl,pins = <
- MX8MP_IOMUXC_SD1_CLK__USDHC1_CLK 0x190
- MX8MP_IOMUXC_SD1_CMD__USDHC1_CMD 0x1d0
- MX8MP_IOMUXC_SD1_DATA0__USDHC1_DATA0 0x1d0
- MX8MP_IOMUXC_SD1_DATA1__USDHC1_DATA1 0x1d0
- MX8MP_IOMUXC_SD1_DATA2__USDHC1_DATA2 0x1d0
- MX8MP_IOMUXC_SD1_DATA3__USDHC1_DATA3 0x1d0
- >;
- };
-
- pinctrl_usdhc1_100mhz: usdhc1-100mhzgrp {
- fsl,pins = <
- MX8MP_IOMUXC_SD1_CLK__USDHC1_CLK 0x194
- MX8MP_IOMUXC_SD1_CMD__USDHC1_CMD 0x1d4
- MX8MP_IOMUXC_SD1_DATA0__USDHC1_DATA0 0x1d4
- MX8MP_IOMUXC_SD1_DATA1__USDHC1_DATA1 0x1d4
- MX8MP_IOMUXC_SD1_DATA2__USDHC1_DATA2 0x1d4
- MX8MP_IOMUXC_SD1_DATA3__USDHC1_DATA3 0x1d4
- >;
- };
-
- pinctrl_usdhc1_200mhz: usdhc1-200mhzgrp {
- fsl,pins = <
- MX8MP_IOMUXC_SD1_CLK__USDHC1_CLK 0x196
- MX8MP_IOMUXC_SD1_CMD__USDHC1_CMD 0x1d6
- MX8MP_IOMUXC_SD1_DATA0__USDHC1_DATA0 0x1d6
- MX8MP_IOMUXC_SD1_DATA1__USDHC1_DATA1 0x1d6
- MX8MP_IOMUXC_SD1_DATA2__USDHC1_DATA2 0x1d6
- MX8MP_IOMUXC_SD1_DATA3__USDHC1_DATA3 0x1d6
- >;
- };
-
- pinctrl_usdhc3: usdhc3grp {
- fsl,pins = <
- MX8MP_IOMUXC_NAND_WE_B__USDHC3_CLK 0x190
- MX8MP_IOMUXC_NAND_WP_B__USDHC3_CMD 0x1d0
- MX8MP_IOMUXC_NAND_DATA04__USDHC3_DATA0 0x1d0
- MX8MP_IOMUXC_NAND_DATA05__USDHC3_DATA1 0x1d0
- MX8MP_IOMUXC_NAND_DATA06__USDHC3_DATA2 0x1d0
- MX8MP_IOMUXC_NAND_DATA07__USDHC3_DATA3 0x1d0
- MX8MP_IOMUXC_NAND_RE_B__USDHC3_DATA4 0x1d0
- MX8MP_IOMUXC_NAND_CE2_B__USDHC3_DATA5 0x1d0
- MX8MP_IOMUXC_NAND_CE3_B__USDHC3_DATA6 0x1d0
- MX8MP_IOMUXC_NAND_CLE__USDHC3_DATA7 0x1d0
- MX8MP_IOMUXC_NAND_CE1_B__USDHC3_STROBE 0x190
- >;
- };
-
- pinctrl_usdhc3_100mhz: usdhc3-100mhzgrp {
- fsl,pins = <
- MX8MP_IOMUXC_NAND_WE_B__USDHC3_CLK 0x194
- MX8MP_IOMUXC_NAND_WP_B__USDHC3_CMD 0x1d4
- MX8MP_IOMUXC_NAND_DATA04__USDHC3_DATA0 0x1d4
- MX8MP_IOMUXC_NAND_DATA05__USDHC3_DATA1 0x1d4
- MX8MP_IOMUXC_NAND_DATA06__USDHC3_DATA2 0x1d4
- MX8MP_IOMUXC_NAND_DATA07__USDHC3_DATA3 0x1d4
- MX8MP_IOMUXC_NAND_RE_B__USDHC3_DATA4 0x1d4
- MX8MP_IOMUXC_NAND_CE2_B__USDHC3_DATA5 0x1d4
- MX8MP_IOMUXC_NAND_CE3_B__USDHC3_DATA6 0x1d4
- MX8MP_IOMUXC_NAND_CLE__USDHC3_DATA7 0x1d4
- MX8MP_IOMUXC_NAND_CE1_B__USDHC3_STROBE 0x194
- >;
- };
-
- pinctrl_usdhc3_200mhz: usdhc3-200mhzgrp {
- fsl,pins = <
- MX8MP_IOMUXC_NAND_WE_B__USDHC3_CLK 0x196
- MX8MP_IOMUXC_NAND_WP_B__USDHC3_CMD 0x1d6
- MX8MP_IOMUXC_NAND_DATA04__USDHC3_DATA0 0x1d6
- MX8MP_IOMUXC_NAND_DATA05__USDHC3_DATA1 0x1d6
- MX8MP_IOMUXC_NAND_DATA06__USDHC3_DATA2 0x1d6
- MX8MP_IOMUXC_NAND_DATA07__USDHC3_DATA3 0x1d6
- MX8MP_IOMUXC_NAND_RE_B__USDHC3_DATA4 0x1d6
- MX8MP_IOMUXC_NAND_CE2_B__USDHC3_DATA5 0x1d6
- MX8MP_IOMUXC_NAND_CE3_B__USDHC3_DATA6 0x1d6
- MX8MP_IOMUXC_NAND_CLE__USDHC3_DATA7 0x1d6
- MX8MP_IOMUXC_NAND_CE1_B__USDHC3_STROBE 0x196
- >;
- };
-
- pinctrl_wdog: wdoggrp {
- fsl,pins = <
- MX8MP_IOMUXC_GPIO1_IO02__WDOG1_WDOG_B 0x166
- >;
- };
-};
diff --git a/arch/arm/dts/imx8mp-venice-gw7905-2x.dts b/arch/arm/dts/imx8mp-venice-gw7905-2x.dts
deleted file mode 100644
index 4a1bbbb..0000000
--- a/arch/arm/dts/imx8mp-venice-gw7905-2x.dts
+++ /dev/null
@@ -1,28 +0,0 @@
-// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
-/*
- * Copyright 2023 Gateworks Corporation
- */
-
-/dts-v1/;
-
-#include "imx8mp.dtsi"
-#include "imx8mp-venice-gw702x.dtsi"
-#include "imx8mp-venice-gw7905.dtsi"
-
-/ {
- model = "Gateworks Venice GW7905-2x i.MX8MP Development Kit";
- compatible = "gateworks,imx8mp-gw7905-2x", "fsl,imx8mp";
-
- chosen {
- stdout-path = &uart2;
- };
-};
-
-/* Disable SOM interfaces not used on baseboard */
-&eqos {
- status = "disabled";
-};
-
-&usdhc1 {
- status = "disabled";
-};
diff --git a/arch/arm/dts/imx8mp-venice-gw7905.dtsi b/arch/arm/dts/imx8mp-venice-gw7905.dtsi
deleted file mode 100644
index 0d40cb0..0000000
--- a/arch/arm/dts/imx8mp-venice-gw7905.dtsi
+++ /dev/null
@@ -1,309 +0,0 @@
-// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
-/*
- * Copyright 2023 Gateworks Corporation
- */
-
-#include <dt-bindings/gpio/gpio.h>
-#include <dt-bindings/leds/common.h>
-#include <dt-bindings/phy/phy-imx8-pcie.h>
-
-/ {
- led-controller {
- compatible = "gpio-leds";
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_gpio_leds>;
-
- led-0 {
- function = LED_FUNCTION_STATUS;
- color = <LED_COLOR_ID_GREEN>;
- gpios = <&gpio4 22 GPIO_ACTIVE_HIGH>;
- default-state = "on";
- linux,default-trigger = "heartbeat";
- };
-
- led-1 {
- function = LED_FUNCTION_STATUS;
- color = <LED_COLOR_ID_RED>;
- gpios = <&gpio4 27 GPIO_ACTIVE_HIGH>;
- default-state = "off";
- };
- };
-
- pcie0_refclk: pcie0-refclk {
- compatible = "fixed-clock";
- #clock-cells = <0>;
- clock-frequency = <100000000>;
- };
-
- pps {
- compatible = "pps-gpio";
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_pps>;
- gpios = <&gpio4 21 GPIO_ACTIVE_HIGH>;
- status = "okay";
- };
-
- reg_usb2_vbus: regulator-usb2-vbus {
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_reg_usb2_en>;
- compatible = "regulator-fixed";
- regulator-name = "usb2_vbus";
- gpio = <&gpio4 12 GPIO_ACTIVE_HIGH>;
- enable-active-high;
- regulator-min-microvolt = <5000000>;
- regulator-max-microvolt = <5000000>;
- };
-
- reg_usdhc2_vmmc: regulator-usdhc2 {
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_reg_usdhc2_vmmc>;
- compatible = "regulator-fixed";
- regulator-name = "SD2_3P3V";
- regulator-min-microvolt = <3300000>;
- regulator-max-microvolt = <3300000>;
- gpio = <&gpio2 19 GPIO_ACTIVE_HIGH>;
- enable-active-high;
- };
-};
-
-/* off-board header */
-&ecspi2 {
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_spi2>;
- cs-gpios = <&gpio5 13 GPIO_ACTIVE_LOW>;
- status = "okay";
-};
-
-&gpio4 {
- gpio-line-names =
- "", "", "", "",
- "", "", "", "",
- "", "", "", "",
- "", "gpioa", "", "",
- "", "", "", "",
- "", "", "", "",
- "", "", "", "",
- "", "", "", "";
-};
-
-&gpio4 {
- gpio-line-names =
- "", "gpiod", "", "",
- "gpiob", "gpioc", "", "",
- "", "", "", "",
- "", "", "", "",
- "", "", "", "",
- "", "", "", "",
- "", "", "pci_usb_sel", "",
- "pci_wdis#", "", "", "";
-};
-
-&i2c2 {
- clock-frequency = <400000>;
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_i2c2>;
- status = "okay";
-
- eeprom@52 {
- compatible = "atmel,24c32";
- reg = <0x52>;
- pagesize = <32>;
- };
-};
-
-/* off-board header */
-&i2c3 {
- clock-frequency = <400000>;
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_i2c3>;
- status = "okay";
-};
-
-&pcie_phy {
- fsl,refclk-pad-mode = <IMX8_PCIE_REFCLK_PAD_INPUT>;
- fsl,clkreq-unsupported;
- clocks = <&pcie0_refclk>;
- clock-names = "ref";
- status = "okay";
-};
-
-&pcie {
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_pcie0>;
- reset-gpio = <&gpio4 29 GPIO_ACTIVE_LOW>;
- status = "okay";
-};
-
-/* GPS */
-&uart1 {
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_uart1>;
- status = "okay";
-};
-
-/* USB1 - Type C front panel SINK port J14 */
-&usb3_0 {
- status = "okay";
-};
-
-&usb3_phy0 {
- status = "okay";
-};
-
-&usb_dwc3_0 {
- dr_mode = "peripheral";
- status = "okay";
-};
-
-/* USB2 4-port USB3.0 HUB:
- * P1 - USBC connector (host only)
- * P2 - USB2 test connector
- * P3 - miniPCIe full card
- * P4 - miniPCIe half card
- */
-&usb3_phy1 {
- vbus-supply = <®_usb2_vbus>;
- status = "okay";
-};
-
-&usb3_1 {
- fsl,permanently-attached;
- fsl,disable-port-power-control;
- status = "okay";
-};
-
-&usb_dwc3_1 {
- dr_mode = "host";
- status = "okay";
-};
-
-/* microSD */
-&usdhc2 {
- pinctrl-names = "default", "state_100mhz", "state_200mhz";
- pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>;
- pinctrl-1 = <&pinctrl_usdhc2_100mhz>, <&pinctrl_usdhc2_gpio>;
- pinctrl-2 = <&pinctrl_usdhc2_200mhz>, <&pinctrl_usdhc2_gpio>;
- cd-gpios = <&gpio2 12 GPIO_ACTIVE_LOW>;
- vmmc-supply = <®_usdhc2_vmmc>;
- bus-width = <4>;
- status = "okay";
-};
-
-&iomuxc {
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_hog>;
-
- pinctrl_hog: hoggrp {
- fsl,pins = <
- MX8MP_IOMUXC_GPIO1_IO13__GPIO1_IO13 0x40000040 /* GPIOA */
- MX8MP_IOMUXC_SAI1_RXC__GPIO4_IO01 0x40000040 /* GPIOD */
- MX8MP_IOMUXC_SAI1_RXD2__GPIO4_IO04 0x40000040 /* GPIOB */
- MX8MP_IOMUXC_SAI1_RXD3__GPIO4_IO05 0x40000040 /* GPIOC */
- MX8MP_IOMUXC_SAI2_TXD0__GPIO4_IO26 0x40000106 /* PCI_USBSEL */
- MX8MP_IOMUXC_SAI3_RXFS__GPIO4_IO28 0x40000106 /* PCI_WDIS# */
- >;
- };
-
- pinctrl_gpio_leds: gpioledgrp {
- fsl,pins = <
- MX8MP_IOMUXC_SAI2_RXC__GPIO4_IO22 0x6 /* LEDG */
- MX8MP_IOMUXC_SAI2_MCLK__GPIO4_IO27 0x6 /* LEDR */
- >;
- };
-
- pinctrl_i2c2: i2c2grp {
- fsl,pins = <
- MX8MP_IOMUXC_I2C2_SCL__I2C2_SCL 0x400001c2
- MX8MP_IOMUXC_I2C2_SDA__I2C2_SDA 0x400001c2
- >;
- };
-
- pinctrl_i2c3: i2c3grp {
- fsl,pins = <
- MX8MP_IOMUXC_I2C3_SCL__I2C3_SCL 0x400001c2
- MX8MP_IOMUXC_I2C3_SDA__I2C3_SDA 0x400001c2
- >;
- };
-
- pinctrl_pcie0: pciegrp {
- fsl,pins = <
- MX8MP_IOMUXC_SAI3_RXC__GPIO4_IO29 0x106
- >;
- };
-
- pinctrl_pps: ppsgrp {
- fsl,pins = <
- MX8MP_IOMUXC_SAI2_RXFS__GPIO4_IO21 0x106
- >;
- };
-
- pinctrl_reg_usb2_en: regusb2grp {
- fsl,pins = <
- MX8MP_IOMUXC_SAI1_TXD0__GPIO4_IO12 0x6 /* USBHUB_RST# (ext p/u) */
- >;
- };
-
- pinctrl_reg_usdhc2_vmmc: regusdhc2vmmcgrp {
- fsl,pins = <
- MX8MP_IOMUXC_SD2_RESET_B__GPIO2_IO19 0x40
- >;
- };
-
- pinctrl_spi2: spi2grp {
- fsl,pins = <
- MX8MP_IOMUXC_ECSPI2_SCLK__ECSPI2_SCLK 0x140
- MX8MP_IOMUXC_ECSPI2_MOSI__ECSPI2_MOSI 0x140
- MX8MP_IOMUXC_ECSPI2_MISO__ECSPI2_MISO 0x140
- MX8MP_IOMUXC_ECSPI2_SS0__GPIO5_IO13 0x140
- >;
- };
-
- pinctrl_uart1: uart1grp {
- fsl,pins = <
- MX8MP_IOMUXC_UART1_RXD__UART1_DCE_RX 0x140
- MX8MP_IOMUXC_UART1_TXD__UART1_DCE_TX 0x140
- >;
- };
-
- pinctrl_usdhc2: usdhc2grp {
- fsl,pins = <
- MX8MP_IOMUXC_SD2_CLK__USDHC2_CLK 0x190
- MX8MP_IOMUXC_SD2_CMD__USDHC2_CMD 0x1d0
- MX8MP_IOMUXC_SD2_DATA0__USDHC2_DATA0 0x1d0
- MX8MP_IOMUXC_SD2_DATA1__USDHC2_DATA1 0x1d0
- MX8MP_IOMUXC_SD2_DATA2__USDHC2_DATA2 0x1d0
- MX8MP_IOMUXC_SD2_DATA3__USDHC2_DATA3 0x1d0
- MX8MP_IOMUXC_GPIO1_IO04__USDHC2_VSELECT 0xc0
- >;
- };
-
- pinctrl_usdhc2_100mhz: usdhc2-100mhzgrp {
- fsl,pins = <
- MX8MP_IOMUXC_SD2_CLK__USDHC2_CLK 0x194
- MX8MP_IOMUXC_SD2_CMD__USDHC2_CMD 0x1d4
- MX8MP_IOMUXC_SD2_DATA0__USDHC2_DATA0 0x1d4
- MX8MP_IOMUXC_SD2_DATA1__USDHC2_DATA1 0x1d4
- MX8MP_IOMUXC_SD2_DATA2__USDHC2_DATA2 0x1d4
- MX8MP_IOMUXC_SD2_DATA3__USDHC2_DATA3 0x1d4
- MX8MP_IOMUXC_GPIO1_IO04__USDHC2_VSELECT 0xc0
- >;
- };
-
- pinctrl_usdhc2_200mhz: usdhc2-200mhzgrp {
- fsl,pins = <
- MX8MP_IOMUXC_SD2_CLK__USDHC2_CLK 0x196
- MX8MP_IOMUXC_SD2_CMD__USDHC2_CMD 0x1d6
- MX8MP_IOMUXC_SD2_DATA0__USDHC2_DATA0 0x1d6
- MX8MP_IOMUXC_SD2_DATA1__USDHC2_DATA1 0x1d6
- MX8MP_IOMUXC_SD2_DATA2__USDHC2_DATA2 0x1d6
- MX8MP_IOMUXC_SD2_DATA3__USDHC2_DATA3 0x1d6
- MX8MP_IOMUXC_GPIO1_IO04__USDHC2_VSELECT 0xc0
- >;
- };
-
- pinctrl_usdhc2_gpio: usdhc2gpiogrp {
- fsl,pins = <
- MX8MP_IOMUXC_SD2_CD_B__GPIO2_IO12 0x1c4
- >;
- };
-};
diff --git a/arch/arm/dts/imx8mp-venice.dts b/arch/arm/dts/imx8mp-venice.dts
deleted file mode 100644
index 372db26..0000000
--- a/arch/arm/dts/imx8mp-venice.dts
+++ /dev/null
@@ -1,183 +0,0 @@
-// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
-/*
- * Copyright 2022 Gateworks Corporation
- */
-
-/dts-v1/;
-
-#include "imx8mp.dtsi"
-
-/ {
- model = "Gateworks Venice i.MX8MP board";
- compatible = "gateworks,imx8mp-venice", "fsl,imx8mp";
-
- chosen {
- stdout-path = &uart2;
- };
-
- memory@40000000 {
- device_type = "memory";
- reg = <0x0 0x40000000 0 0x80000000>;
- };
-};
-
-&i2c1 {
- clock-frequency = <100000>;
- pinctrl-names = "default", "gpio";
- pinctrl-0 = <&pinctrl_i2c1>;
- pinctrl-1 = <&pinctrl_i2c1_gpio>;
- scl-gpios = <&gpio5 14 GPIO_ACTIVE_HIGH>;
- sda-gpios = <&gpio5 15 GPIO_ACTIVE_HIGH>;
- status = "okay";
-
- gsc: gsc@20 {
- compatible = "gw,gsc";
- reg = <0x20>;
- #address-cells = <1>;
- #size-cells = <0>;
- };
-
- eeprom@51 {
- compatible = "atmel,24c02";
- reg = <0x51>;
- pagesize = <16>;
- };
-};
-
-&i2c2 {
- clock-frequency = <400000>;
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_i2c2>;
- status = "okay";
-
- eeprom@52 {
- compatible = "atmel,24c32";
- reg = <0x52>;
- pagesize = <32>;
- };
-};
-
-&i2c3 {
- clock-frequency = <400000>;
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_i2c3>;
- status = "okay";
-};
-
-/* console */
-&uart2 {
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_uart2>;
- status = "okay";
-};
-
-/* eMMC */
-&usdhc3 {
- assigned-clocks = <&clk IMX8MP_CLK_USDHC3>;
- assigned-clock-rates = <400000000>;
- pinctrl-names = "default", "state_100mhz", "state_200mhz";
- pinctrl-0 = <&pinctrl_usdhc3>;
- pinctrl-1 = <&pinctrl_usdhc3_100mhz>;
- pinctrl-2 = <&pinctrl_usdhc3_200mhz>;
- bus-width = <8>;
- non-removable;
- status = "okay";
-};
-
-&wdog1 {
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_wdog>;
- fsl,ext-reset-output;
- status = "okay";
-};
-
-&iomuxc {
- pinctrl_i2c1: i2c1grp {
- fsl,pins = <
- MX8MP_IOMUXC_I2C1_SCL__I2C1_SCL 0x400001c3
- MX8MP_IOMUXC_I2C1_SDA__I2C1_SDA 0x400001c3
- >;
- };
-
- pinctrl_i2c1_gpio: i2c1grp-gpio-grp {
- fsl,pins = <
- MX8MP_IOMUXC_I2C1_SCL__GPIO5_IO14 0x400001c3
- MX8MP_IOMUXC_I2C1_SDA__GPIO5_IO15 0x400001c3
- >;
- };
-
- pinctrl_i2c2: i2c2grp {
- fsl,pins = <
- MX8MP_IOMUXC_I2C2_SCL__I2C2_SCL 0x400001c3
- MX8MP_IOMUXC_I2C2_SDA__I2C2_SDA 0x400001c3
- >;
- };
-
- pinctrl_i2c3: i2c3grp {
- fsl,pins = <
- MX8MP_IOMUXC_I2C3_SCL__I2C3_SCL 0x400001c3
- MX8MP_IOMUXC_I2C3_SDA__I2C3_SDA 0x400001c3
- >;
- };
-
- pinctrl_uart2: uart2grp {
- fsl,pins = <
- MX8MP_IOMUXC_UART2_RXD__UART2_DCE_RX 0x49
- MX8MP_IOMUXC_UART2_TXD__UART2_DCE_TX 0x49
- >;
- };
-
- pinctrl_usdhc3: usdhc3grp {
- fsl,pins = <
- MX8MP_IOMUXC_NAND_WE_B__USDHC3_CLK 0x190
- MX8MP_IOMUXC_NAND_WP_B__USDHC3_CMD 0x1d0
- MX8MP_IOMUXC_NAND_DATA04__USDHC3_DATA0 0x1d0
- MX8MP_IOMUXC_NAND_DATA05__USDHC3_DATA1 0x1d0
- MX8MP_IOMUXC_NAND_DATA06__USDHC3_DATA2 0x1d0
- MX8MP_IOMUXC_NAND_DATA07__USDHC3_DATA3 0x1d0
- MX8MP_IOMUXC_NAND_RE_B__USDHC3_DATA4 0x1d0
- MX8MP_IOMUXC_NAND_CE2_B__USDHC3_DATA5 0x1d0
- MX8MP_IOMUXC_NAND_CE3_B__USDHC3_DATA6 0x1d0
- MX8MP_IOMUXC_NAND_CLE__USDHC3_DATA7 0x1d0
- MX8MP_IOMUXC_NAND_CE1_B__USDHC3_STROBE 0x190
- >;
- };
-
- pinctrl_usdhc3_100mhz: usdhc3-100mhzgrp {
- fsl,pins = <
- MX8MP_IOMUXC_NAND_WE_B__USDHC3_CLK 0x194
- MX8MP_IOMUXC_NAND_WP_B__USDHC3_CMD 0x1d4
- MX8MP_IOMUXC_NAND_DATA04__USDHC3_DATA0 0x1d4
- MX8MP_IOMUXC_NAND_DATA05__USDHC3_DATA1 0x1d4
- MX8MP_IOMUXC_NAND_DATA06__USDHC3_DATA2 0x1d4
- MX8MP_IOMUXC_NAND_DATA07__USDHC3_DATA3 0x1d4
- MX8MP_IOMUXC_NAND_RE_B__USDHC3_DATA4 0x1d4
- MX8MP_IOMUXC_NAND_CE2_B__USDHC3_DATA5 0x1d4
- MX8MP_IOMUXC_NAND_CE3_B__USDHC3_DATA6 0x1d4
- MX8MP_IOMUXC_NAND_CLE__USDHC3_DATA7 0x1d4
- MX8MP_IOMUXC_NAND_CE1_B__USDHC3_STROBE 0x194
- >;
- };
-
- pinctrl_usdhc3_200mhz: usdhc3-200mhzgrp {
- fsl,pins = <
- MX8MP_IOMUXC_NAND_WE_B__USDHC3_CLK 0x196
- MX8MP_IOMUXC_NAND_WP_B__USDHC3_CMD 0x1d6
- MX8MP_IOMUXC_NAND_DATA04__USDHC3_DATA0 0x1d6
- MX8MP_IOMUXC_NAND_DATA05__USDHC3_DATA1 0x1d6
- MX8MP_IOMUXC_NAND_DATA06__USDHC3_DATA2 0x1d6
- MX8MP_IOMUXC_NAND_DATA07__USDHC3_DATA3 0x1d6
- MX8MP_IOMUXC_NAND_RE_B__USDHC3_DATA4 0x1d6
- MX8MP_IOMUXC_NAND_CE2_B__USDHC3_DATA5 0x1d6
- MX8MP_IOMUXC_NAND_CE3_B__USDHC3_DATA6 0x1d6
- MX8MP_IOMUXC_NAND_CLE__USDHC3_DATA7 0x1d6
- MX8MP_IOMUXC_NAND_CE1_B__USDHC3_STROBE 0x196
- >;
- };
-
- pinctrl_wdog: wdoggrp {
- fsl,pins = <
- MX8MP_IOMUXC_GPIO1_IO02__WDOG1_WDOG_B 0x166
- >;
- };
-};
diff --git a/arch/arm/dts/imx8mp-verdin-dev.dtsi b/arch/arm/dts/imx8mp-verdin-dev.dtsi
deleted file mode 100644
index bdfdd4c..0000000
--- a/arch/arm/dts/imx8mp-verdin-dev.dtsi
+++ /dev/null
@@ -1,165 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
-/*
- * Copyright 2022 Toradex
- */
-
-/ {
- /* TODO: Audio Codec */
-
- reg_eth2phy: regulator-eth2phy {
- compatible = "regulator-fixed";
- enable-active-high;
- gpio = <&gpio_expander_21 4 GPIO_ACTIVE_HIGH>; /* ETH_PWR_EN */
- off-on-delay-us = <500000>;
- regulator-max-microvolt = <3300000>;
- regulator-min-microvolt = <3300000>;
- regulator-name = "+V3.3_ETH";
- startup-delay-us = <200000>;
- vin-supply = <®_3p3v>;
- };
-};
-
-&backlight {
- power-supply = <®_3p3v>;
-};
-
-/* Verdin SPI_1 */
-&ecspi1 {
- status = "okay";
-};
-
-/* EEPROM on display adapter boards */
-&eeprom_display_adapter {
- status = "okay";
-};
-
-/* EEPROM on Verdin Development board */
-&eeprom_carrier_board {
- status = "okay";
-};
-
-&eqos {
- status = "okay";
-};
-
-&fec {
- phy-supply = <®_eth2phy>;
- status = "okay";
-};
-
-&flexcan1 {
- status = "okay";
-};
-
-&flexcan2 {
- status = "okay";
-};
-
-/* Verdin QSPI_1 */
-&flexspi {
- status = "okay";
-};
-
-&gpio_expander_21 {
- status = "okay";
- vcc-supply = <®_1p8v>;
-};
-
-/* Current measurement into module VCC */
-&hwmon {
- status = "okay";
-};
-
-&hwmon_temp {
- vs-supply = <®_1p8v>;
- status = "okay";
-};
-
-/* Verdin I2C_2_DSI */
-&i2c2 {
- status = "okay";
-};
-
-&i2c3 {
- status = "okay";
-};
-
-/* Verdin I2C_1 */
-&i2c4 {
- status = "okay";
-
- /* TODO: Audio Codec */
-};
-
-/* Verdin PCIE_1 */
-&pcie {
- status = "okay";
-};
-
-&pcie_phy {
- status = "okay";
-};
-
-/* Verdin PWM_1 */
-&pwm1 {
- status = "okay";
-};
-
-/* Verdin PWM_2 */
-&pwm2 {
- status = "okay";
-};
-
-/* Verdin PWM_3_DSI */
-&pwm3 {
- status = "okay";
-};
-
-®_usdhc2_vmmc {
- vin-supply = <®_3p3v>;
-};
-
-/* TODO: Verdin I2C_1 with Audio Codec */
-
-/* Verdin UART_1, connector X50 through RS485 transceiver */
-&uart1 {
- linux,rs485-enabled-at-boot-time;
- rs485-rts-active-low;
- rs485-rx-during-tx;
- status = "okay";
-};
-
-/* Verdin UART_2 */
-&uart2 {
- status = "okay";
-};
-
-/* Verdin UART_3, used as the Linux Console */
-&uart3 {
- status = "okay";
-};
-
-/* Verdin USB_1 */
-&usb3_0 {
- status = "okay";
-};
-
-&usb3_phy0 {
- status = "okay";
-};
-
-/* Verdin USB_2 */
-&usb3_1 {
- fsl,permanently-attached;
- status = "okay";
-};
-
-&usb3_phy1 {
- status = "okay";
-};
-
-/* Limit frequency on dev board due to long traces and bad signal integrity */
-&usdhc2 {
- max-frequency = <100000000>;
- status = "okay";
-};
diff --git a/arch/arm/dts/imx8mp-verdin-wifi-dev.dts b/arch/arm/dts/imx8mp-verdin-wifi-dev.dts
deleted file mode 100644
index c1713c2..0000000
--- a/arch/arm/dts/imx8mp-verdin-wifi-dev.dts
+++ /dev/null
@@ -1,18 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
-/*
- * Copyright 2022 Toradex
- */
-
-/dts-v1/;
-
-#include "imx8mp-verdin.dtsi"
-#include "imx8mp-verdin-wifi.dtsi"
-#include "imx8mp-verdin-dev.dtsi"
-
-/ {
- model = "Toradex Verdin iMX8M Plus WB on Verdin Development Board";
- compatible = "toradex,verdin-imx8mp-wifi-dev",
- "toradex,verdin-imx8mp-wifi",
- "toradex,verdin-imx8mp",
- "fsl,imx8mp";
-};
diff --git a/arch/arm/dts/imx8mp-verdin-wifi.dtsi b/arch/arm/dts/imx8mp-verdin-wifi.dtsi
deleted file mode 100644
index ef94f9a..0000000
--- a/arch/arm/dts/imx8mp-verdin-wifi.dtsi
+++ /dev/null
@@ -1,87 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
-/*
- * Copyright 2022 Toradex
- */
-
-/ {
- reg_wifi_en: regulator-wifi-en {
- compatible = "regulator-fixed";
- enable-active-high;
- gpio = <&gpio2 11 GPIO_ACTIVE_HIGH>;
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_wifi_pwr_en>;
- regulator-max-microvolt = <3300000>;
- regulator-min-microvolt = <3300000>;
- regulator-name = "PDn_AW-CM276NF";
- startup-delay-us = <2000>;
- };
-};
-
-&gpio5 {
- gpio-line-names = "SODIMM_42",
- "SODIMM_46",
- "SODIMM_187",
- "SODIMM_20",
- "SODIMM_22",
- "SODIMM_15",
- "SODIMM_196",
- "SODIMM_200",
- "SODIMM_198",
- "SODIMM_202",
- "",
- "",
- "",
- "",
- "",
- "",
- "SODIMM_55",
- "SODIMM_53",
- "SODIMM_95",
- "SODIMM_93",
- "SODIMM_14",
- "SODIMM_12",
- "SODIMM_129",
- "SODIMM_131",
- "SODIMM_137",
- "SODIMM_139",
- "SODIMM_147",
- "SODIMM_149",
- "SODIMM_151",
- "SODIMM_153";
-};
-
-&iomuxc {
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_gpio1>, <&pinctrl_gpio2>,
- <&pinctrl_gpio3>, <&pinctrl_gpio4>,
- <&pinctrl_gpio7>, <&pinctrl_gpio8>,
- <&pinctrl_gpio_hog2>, <&pinctrl_gpio_hog3>, <&pinctrl_gpio_hog4>,
- <&pinctrl_hdmi_hog>;
-};
-
-/* On-module Bluetooth */
-&uart4 {
- uart-has-rtscts;
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_bt_uart>;
- status = "okay";
-
- bluetooth {
- compatible = "mrvl,88w8997";
- max-speed = <921600>;
- };
-};
-
-/* On-module Wi-Fi */
-&usdhc1 {
- bus-width = <4>;
- keep-power-in-suspend;
- max-frequency = <100000000>;
- non-removable;
- pinctrl-names = "default", "state_100mhz", "state_200mhz";
- pinctrl-0 = <&pinctrl_usdhc1>, <&pinctrl_wifi_ctrl>;
- pinctrl-1 = <&pinctrl_usdhc1_100mhz>, <&pinctrl_wifi_ctrl>;
- pinctrl-2 = <&pinctrl_usdhc1_200mhz>, <&pinctrl_wifi_ctrl>;
- vmmc-supply = <®_wifi_en>;
- status = "okay";
-};
diff --git a/arch/arm/dts/imx8mp-verdin.dtsi b/arch/arm/dts/imx8mp-verdin.dtsi
deleted file mode 100644
index e9e4fcb..0000000
--- a/arch/arm/dts/imx8mp-verdin.dtsi
+++ /dev/null
@@ -1,1438 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
-/*
- * Copyright 2022 Toradex
- */
-
-#include <dt-bindings/phy/phy-imx8-pcie.h>
-#include <dt-bindings/pwm/pwm.h>
-#include "imx8mp.dtsi"
-
-/ {
- chosen {
- stdout-path = &uart3;
- };
-
- aliases {
- /* Ethernet aliases to ensure correct MAC addresses */
- ethernet0 = &eqos;
- ethernet1 = &fec;
- rtc0 = &rtc_i2c;
- rtc1 = &snvs_rtc;
- };
-
- backlight: backlight {
- compatible = "pwm-backlight";
- brightness-levels = <0 45 63 88 119 158 203 255>;
- default-brightness-level = <4>;
- /* Verdin I2S_2_D_OUT (DSI_1_BKL_EN/DSI_1_BKL_EN_LVDS, SODIMM 46) */
- enable-gpios = <&gpio5 1 GPIO_ACTIVE_HIGH>;
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_i2s_2_d_out_dsi_1_bkl_en>;
- power-supply = <®_3p3v>;
- /* Verdin PWM_3_DSI/PWM_3_DSI_LVDS (SODIMM 19) */
- pwms = <&pwm3 0 6666667 PWM_POLARITY_INVERTED>;
- status = "disabled";
- };
-
- backlight_mezzanine: backlight-mezzanine {
- compatible = "pwm-backlight";
- brightness-levels = <0 45 63 88 119 158 203 255>;
- default-brightness-level = <4>;
- /* Verdin GPIO 4 (SODIMM 212) */
- enable-gpios = <&gpio1 6 GPIO_ACTIVE_HIGH>;
- /* Verdin PWM_2 (SODIMM 16) */
- pwms = <&pwm2 0 6666667 PWM_POLARITY_INVERTED>;
- status = "disabled";
- };
-
- gpio-keys {
- compatible = "gpio-keys";
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_gpio_keys>;
-
- key-wakeup {
- debounce-interval = <10>;
- /* Verdin CTRL_WAKE1_MICO# (SODIMM 252) */
- gpios = <&gpio4 0 GPIO_ACTIVE_LOW>;
- label = "Wake-Up";
- linux,code = <KEY_WAKEUP>;
- wakeup-source;
- };
- };
-
- /* Carrier Board Supplies */
- reg_1p8v: regulator-1p8v {
- compatible = "regulator-fixed";
- regulator-max-microvolt = <1800000>;
- regulator-min-microvolt = <1800000>;
- regulator-name = "+V1.8_SW";
- };
-
- reg_3p3v: regulator-3p3v {
- compatible = "regulator-fixed";
- regulator-max-microvolt = <3300000>;
- regulator-min-microvolt = <3300000>;
- regulator-name = "+V3.3_SW";
- };
-
- reg_5p0v: regulator-5p0v {
- compatible = "regulator-fixed";
- regulator-max-microvolt = <5000000>;
- regulator-min-microvolt = <5000000>;
- regulator-name = "+V5_SW";
- };
-
- /* Non PMIC On-module Supplies */
- reg_module_eth1phy: regulator-module-eth1phy {
- compatible = "regulator-fixed";
- enable-active-high;
- gpio = <&gpio2 20 GPIO_ACTIVE_HIGH>; /* PMIC_EN_ETH */
- off-on-delay-us = <500000>;
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_reg_eth>;
- regulator-always-on;
- regulator-boot-on;
- regulator-max-microvolt = <3300000>;
- regulator-min-microvolt = <3300000>;
- regulator-name = "On-module +V3.3_ETH";
- startup-delay-us = <200000>;
- vin-supply = <®_vdd_3v3>;
- };
-
- reg_usb1_vbus: regulator-usb1-vbus {
- compatible = "regulator-fixed";
- enable-active-high;
- /* Verdin USB_1_EN (SODIMM 155) */
- gpio = <&gpio1 12 GPIO_ACTIVE_HIGH>;
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_usb1_vbus>;
- regulator-max-microvolt = <5000000>;
- regulator-min-microvolt = <5000000>;
- regulator-name = "USB_1_EN";
- };
-
- reg_usb2_vbus: regulator-usb2-vbus {
- compatible = "regulator-fixed";
- enable-active-high;
- /* Verdin USB_2_EN (SODIMM 185) */
- gpio = <&gpio1 14 GPIO_ACTIVE_HIGH>;
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_usb2_vbus>;
- regulator-max-microvolt = <5000000>;
- regulator-min-microvolt = <5000000>;
- regulator-name = "USB_2_EN";
- };
-
- reg_usdhc2_vmmc: regulator-usdhc2 {
- compatible = "regulator-fixed";
- enable-active-high;
- /* Verdin SD_1_PWR_EN (SODIMM 76) */
- gpio = <&gpio4 22 GPIO_ACTIVE_HIGH>;
- off-on-delay-us = <100000>;
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_usdhc2_pwr_en>;
- regulator-max-microvolt = <3300000>;
- regulator-min-microvolt = <3300000>;
- regulator-name = "+V3.3_SD";
- startup-delay-us = <2000>;
- };
-
- reserved-memory {
- #address-cells = <2>;
- #size-cells = <2>;
- ranges;
-
- /* Use the kernel configuration settings instead */
- /delete-node/ linux,cma;
- };
-};
-
-&A53_0 {
- cpu-supply = <®_vdd_arm>;
-};
-
-&A53_1 {
- cpu-supply = <®_vdd_arm>;
-};
-
-&A53_2 {
- cpu-supply = <®_vdd_arm>;
-};
-
-&A53_3 {
- cpu-supply = <®_vdd_arm>;
-};
-
-&cpu_alert0 {
- temperature = <95000>;
-};
-
-&cpu_crit0 {
- temperature = <105000>;
-};
-
-/* Verdin SPI_1 */
-&ecspi1 {
- #address-cells = <1>;
- #size-cells = <0>;
- cs-gpios = <&gpio5 9 GPIO_ACTIVE_LOW>;
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_ecspi1>;
-};
-
-/* Verdin ETH_1 (On-module PHY) */
-&eqos {
- phy-handle = <ðphy0>;
- phy-mode = "rgmii-id";
- phy-supply = <®_module_eth1phy>;
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_eqos>;
- snps,force_thresh_dma_mode;
- snps,mtl-rx-config = <&mtl_rx_setup>;
- snps,mtl-tx-config = <&mtl_tx_setup>;
-
- mdio {
- compatible = "snps,dwmac-mdio";
- #address-cells = <1>;
- #size-cells = <0>;
-
- ethphy0: ethernet-phy@7 {
- compatible = "ethernet-phy-ieee802.3-c22";
- eee-broken-100tx;
- eee-broken-1000t;
- interrupt-parent = <&gpio1>;
- interrupts = <10 IRQ_TYPE_LEVEL_LOW>;
- micrel,led-mode = <0>;
- reg = <7>;
- };
- };
-
- mtl_rx_setup: rx-queues-config {
- snps,rx-queues-to-use = <5>;
- snps,rx-sched-sp;
-
- queue0 {
- snps,dcb-algorithm;
- snps,priority = <0x1>;
- snps,map-to-dma-channel = <0>;
- };
-
- queue1 {
- snps,dcb-algorithm;
- snps,priority = <0x2>;
- snps,map-to-dma-channel = <1>;
- };
-
- queue2 {
- snps,dcb-algorithm;
- snps,priority = <0x4>;
- snps,map-to-dma-channel = <2>;
- };
-
- queue3 {
- snps,dcb-algorithm;
- snps,priority = <0x8>;
- snps,map-to-dma-channel = <3>;
- };
-
- queue4 {
- snps,dcb-algorithm;
- snps,priority = <0xf0>;
- snps,map-to-dma-channel = <4>;
- };
- };
-
- mtl_tx_setup: tx-queues-config {
- snps,tx-queues-to-use = <5>;
- snps,tx-sched-sp;
-
- queue0 {
- snps,dcb-algorithm;
- snps,priority = <0x1>;
- };
-
- queue1 {
- snps,dcb-algorithm;
- snps,priority = <0x2>;
- };
-
- queue2 {
- snps,dcb-algorithm;
- snps,priority = <0x4>;
- };
-
- queue3 {
- snps,dcb-algorithm;
- snps,priority = <0x8>;
- };
-
- queue4 {
- snps,dcb-algorithm;
- snps,priority = <0xf0>;
- };
- };
-};
-
-/* Verdin ETH_2_RGMII */
-&fec {
- fsl,magic-packet;
- phy-handle = <ðphy1>;
- phy-mode = "rgmii-id";
- pinctrl-names = "default", "sleep";
- pinctrl-0 = <&pinctrl_fec>;
- pinctrl-1 = <&pinctrl_fec_sleep>;
-
- mdio {
- #address-cells = <1>;
- #size-cells = <0>;
-
- ethphy1: ethernet-phy@7 {
- compatible = "ethernet-phy-ieee802.3-c22";
- interrupt-parent = <&gpio4>;
- interrupts = <18 IRQ_TYPE_LEVEL_LOW>;
- micrel,led-mode = <0>;
- reg = <7>;
- };
- };
-};
-
-/* Verdin CAN_1 */
-&flexcan1 {
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_flexcan1>;
- status = "disabled";
-};
-
-/* Verdin CAN_2 */
-&flexcan2 {
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_flexcan2>;
- status = "disabled";
-};
-
-/* Verdin QSPI_1 */
-&flexspi {
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_flexspi0>;
-};
-
-&gpio1 {
- gpio-line-names = "SODIMM_206",
- "SODIMM_208",
- "",
- "",
- "",
- "SODIMM_210",
- "SODIMM_212",
- "SODIMM_216",
- "SODIMM_218",
- "",
- "",
- "SODIMM_16",
- "SODIMM_155",
- "SODIMM_157",
- "SODIMM_185",
- "SODIMM_91";
-};
-
-&gpio2 {
- gpio-line-names = "",
- "",
- "",
- "",
- "",
- "",
- "SODIMM_143",
- "SODIMM_141",
- "",
- "",
- "SODIMM_161",
- "",
- "SODIMM_84",
- "SODIMM_78",
- "SODIMM_74",
- "SODIMM_80",
- "SODIMM_82",
- "SODIMM_70",
- "SODIMM_72";
-};
-
-&gpio3 {
- gpio-line-names = "SODIMM_52",
- "SODIMM_54",
- "",
- "",
- "",
- "",
- "SODIMM_56",
- "SODIMM_58",
- "SODIMM_60",
- "SODIMM_62",
- "",
- "",
- "",
- "",
- "SODIMM_66",
- "",
- "SODIMM_64",
- "",
- "",
- "SODIMM_34",
- "SODIMM_19",
- "",
- "SODIMM_32",
- "",
- "",
- "SODIMM_30",
- "SODIMM_59",
- "SODIMM_57",
- "SODIMM_63",
- "SODIMM_61";
-};
-
-&gpio4 {
- gpio-line-names = "SODIMM_252",
- "SODIMM_222",
- "SODIMM_36",
- "SODIMM_220",
- "SODIMM_193",
- "SODIMM_191",
- "SODIMM_201",
- "SODIMM_203",
- "SODIMM_205",
- "SODIMM_207",
- "SODIMM_199",
- "SODIMM_197",
- "SODIMM_221",
- "SODIMM_219",
- "SODIMM_217",
- "SODIMM_215",
- "SODIMM_211",
- "SODIMM_213",
- "SODIMM_189",
- "SODIMM_244",
- "SODIMM_38",
- "",
- "SODIMM_76",
- "SODIMM_135",
- "SODIMM_133",
- "SODIMM_17",
- "SODIMM_24",
- "SODIMM_26",
- "SODIMM_21",
- "SODIMM_256",
- "SODIMM_48",
- "SODIMM_44";
-
- ctrl-sleep-moci-hog {
- gpio-hog;
- /* Verdin CTRL_SLEEP_MOCI# (SODIMM 256) */
- gpios = <29 GPIO_ACTIVE_HIGH>;
- line-name = "CTRL_SLEEP_MOCI#";
- output-high;
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_ctrl_sleep_moci>;
- };
-};
-
-/* On-module I2C */
-&i2c1 {
- clock-frequency = <400000>;
- pinctrl-names = "default", "gpio";
- pinctrl-0 = <&pinctrl_i2c1>;
- pinctrl-1 = <&pinctrl_i2c1_gpio>;
- scl-gpios = <&gpio5 14 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
- sda-gpios = <&gpio5 15 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
- status = "okay";
-
- pca9450: pmic@25 {
- compatible = "nxp,pca9450c";
- interrupt-parent = <&gpio1>;
- /* PMIC PCA9450 PMIC_nINT GPIO1_IO3 */
- interrupts = <3 IRQ_TYPE_LEVEL_LOW>;
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_pmic>;
- reg = <0x25>;
-
- /*
- * The bootloader is expected to switch on LDO4 for the on-module +V3.3_ADC and the
- * I2C level shifter for the TLA2024 ADC behind this PMIC.
- */
-
- regulators {
- BUCK1 {
- regulator-always-on;
- regulator-boot-on;
- regulator-max-microvolt = <1000000>;
- regulator-min-microvolt = <720000>;
- regulator-name = "On-module +VDD_SOC (BUCK1)";
- regulator-ramp-delay = <3125>;
- };
-
- reg_vdd_arm: BUCK2 {
- nxp,dvs-run-voltage = <950000>;
- nxp,dvs-standby-voltage = <850000>;
- regulator-always-on;
- regulator-boot-on;
- regulator-max-microvolt = <1025000>;
- regulator-min-microvolt = <720000>;
- regulator-name = "On-module +VDD_ARM (BUCK2)";
- regulator-ramp-delay = <3125>;
- };
-
- reg_vdd_3v3: BUCK4 {
- regulator-always-on;
- regulator-boot-on;
- regulator-max-microvolt = <3300000>;
- regulator-min-microvolt = <3300000>;
- regulator-name = "On-module +V3.3 (BUCK4)";
- };
-
- reg_vdd_1v8: BUCK5 {
- regulator-always-on;
- regulator-boot-on;
- regulator-max-microvolt = <1800000>;
- regulator-min-microvolt = <1800000>;
- regulator-name = "PWR_1V8_MOCI (BUCK5)";
- };
-
- BUCK6 {
- regulator-always-on;
- regulator-boot-on;
- regulator-max-microvolt = <1155000>;
- regulator-min-microvolt = <1045000>;
- regulator-name = "On-module +VDD_DDR (BUCK6)";
- };
-
- LDO1 {
- regulator-always-on;
- regulator-boot-on;
- regulator-max-microvolt = <1950000>;
- regulator-min-microvolt = <1650000>;
- regulator-name = "On-module +V1.8_SNVS (LDO1)";
- };
-
- LDO2 {
- regulator-always-on;
- regulator-boot-on;
- regulator-max-microvolt = <1150000>;
- regulator-min-microvolt = <800000>;
- regulator-name = "On-module +V0.8_SNVS (LDO2)";
- };
-
- LDO3 {
- regulator-always-on;
- regulator-boot-on;
- regulator-max-microvolt = <1800000>;
- regulator-min-microvolt = <1800000>;
- regulator-name = "On-module +V1.8A (LDO3)";
- };
-
- LDO4 {
- regulator-always-on;
- regulator-boot-on;
- regulator-max-microvolt = <3300000>;
- regulator-min-microvolt = <3300000>;
- regulator-name = "On-module +V3.3_ADC (LDO4)";
- };
-
- LDO5 {
- regulator-max-microvolt = <3300000>;
- regulator-min-microvolt = <1800000>;
- regulator-name = "On-module +V3.3_1.8_SD (LDO5)";
- };
- };
- };
-
- rtc_i2c: rtc@32 {
- compatible = "epson,rx8130";
- reg = <0x32>;
- };
-
- /* On-module temperature sensor */
- hwmon_temp_module: sensor@48 {
- compatible = "ti,tmp1075";
- reg = <0x48>;
- vs-supply = <®_vdd_1v8>;
- };
-
- adc@49 {
- compatible = "ti,ads1015";
- reg = <0x49>;
- #address-cells = <1>;
- #size-cells = <0>;
-
- /* Verdin I2C_1 (ADC_4 - ADC_3) */
- channel@0 {
- reg = <0>;
- ti,datarate = <4>;
- ti,gain = <2>;
- };
-
- /* Verdin I2C_1 (ADC_4 - ADC_1) */
- channel@1 {
- reg = <1>;
- ti,datarate = <4>;
- ti,gain = <2>;
- };
-
- /* Verdin I2C_1 (ADC_3 - ADC_1) */
- channel@2 {
- reg = <2>;
- ti,datarate = <4>;
- ti,gain = <2>;
- };
-
- /* Verdin I2C_1 (ADC_2 - ADC_1) */
- channel@3 {
- reg = <3>;
- ti,datarate = <4>;
- ti,gain = <2>;
- };
-
- /* Verdin I2C_1 ADC_4 */
- channel@4 {
- reg = <4>;
- ti,datarate = <4>;
- ti,gain = <2>;
- };
-
- /* Verdin I2C_1 ADC_3 */
- channel@5 {
- reg = <5>;
- ti,datarate = <4>;
- ti,gain = <2>;
- };
-
- /* Verdin I2C_1 ADC_2 */
- channel@6 {
- reg = <6>;
- ti,datarate = <4>;
- ti,gain = <2>;
- };
-
- /* Verdin I2C_1 ADC_1 */
- channel@7 {
- reg = <7>;
- ti,datarate = <4>;
- ti,gain = <2>;
- };
- };
-
- eeprom@50 {
- compatible = "st,24c02";
- pagesize = <16>;
- reg = <0x50>;
- };
-};
-
-/* Verdin I2C_2_DSI */
-&i2c2 {
- /* Lower frequency to avoid DDC/EDID issues with certain displays/screens. */
- clock-frequency = <10000>;
- pinctrl-names = "default", "gpio";
- pinctrl-0 = <&pinctrl_i2c2>;
- pinctrl-1 = <&pinctrl_i2c2_gpio>;
- scl-gpios = <&gpio5 16 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
- sda-gpios = <&gpio5 17 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
-
- atmel_mxt_ts_mezzanine: touch-mezzanine@4a {
- compatible = "atmel,maxtouch";
- /* Verdin GPIO_3 (SODIMM 210) */
- interrupt-parent = <&gpio1>;
- interrupts = <5 IRQ_TYPE_EDGE_FALLING>;
- reg = <0x4a>;
- /* Verdin GPIO_2 (SODIMM 208) */
- reset-gpios = <&gpio1 1 GPIO_ACTIVE_LOW>;
- status = "disabled";
- };
-};
-
-/* TODO: Verdin I2C_3_HDMI */
-
-/* Verdin I2C_4_CSI */
-&i2c3 {
- clock-frequency = <400000>;
- pinctrl-names = "default", "gpio";
- pinctrl-0 = <&pinctrl_i2c3>;
- pinctrl-1 = <&pinctrl_i2c3_gpio>;
- scl-gpios = <&gpio5 18 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
- sda-gpios = <&gpio5 19 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
-};
-
-/* Verdin I2C_1 */
-&i2c4 {
- clock-frequency = <400000>;
- pinctrl-names = "default", "gpio";
- pinctrl-0 = <&pinctrl_i2c4>;
- pinctrl-1 = <&pinctrl_i2c4_gpio>;
- scl-gpios = <&gpio5 20 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
- sda-gpios = <&gpio5 21 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
-
- gpio_expander_21: gpio-expander@21 {
- compatible = "nxp,pcal6416";
- #gpio-cells = <2>;
- gpio-controller;
- reg = <0x21>;
- vcc-supply = <®_3p3v>;
- status = "disabled";
- };
-
- lvds_ti_sn65dsi84: bridge@2c {
- compatible = "ti,sn65dsi84";
- /* Verdin GPIO_9_DSI (SN65DSI84 IRQ, SODIMM 17, unused) */
- /* Verdin GPIO_10_DSI (SODIMM 21) */
- enable-gpios = <&gpio4 28 GPIO_ACTIVE_HIGH>;
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_gpio_10_dsi>;
- reg = <0x2c>;
- status = "disabled";
- };
-
- /* Current measurement into module VCC */
- hwmon: hwmon@40 {
- compatible = "ti,ina219";
- reg = <0x40>;
- shunt-resistor = <10000>;
- status = "disabled";
- };
-
- hdmi_lontium_lt8912: hdmi@48 {
- compatible = "lontium,lt8912b";
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_gpio_10_dsi>, <&pinctrl_pwm_3_dsi_hpd_gpio>;
- reg = <0x48>;
- /* Verdin GPIO_9_DSI (LT8912 INT, SODIMM 17, unused) */
- /* Verdin GPIO_10_DSI (SODIMM 21) */
- reset-gpios = <&gpio4 28 GPIO_ACTIVE_LOW>;
- status = "disabled";
- };
-
- atmel_mxt_ts: touch@4a {
- compatible = "atmel,maxtouch";
- /*
- * Verdin GPIO_9_DSI
- * (TOUCH_INT#, SODIMM 17, also routed to SN65DSI84 IRQ albeit currently unused)
- */
- interrupt-parent = <&gpio4>;
- interrupts = <25 IRQ_TYPE_EDGE_FALLING>;
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_gpio_9_dsi>, <&pinctrl_i2s_2_bclk_touch_reset>;
- reg = <0x4a>;
- /* Verdin I2S_2_BCLK (TOUCH_RESET#, SODIMM 42) */
- reset-gpios = <&gpio5 0 GPIO_ACTIVE_LOW>;
- status = "disabled";
- };
-
- /* Temperature sensor on carrier board */
- hwmon_temp: sensor@4f {
- compatible = "ti,tmp75c";
- reg = <0x4f>;
- status = "disabled";
- };
-
- /* EEPROM on display adapter (MIPI DSI Display Adapter) */
- eeprom_display_adapter: eeprom@50 {
- compatible = "st,24c02";
- pagesize = <16>;
- reg = <0x50>;
- status = "disabled";
- };
-
- /* EEPROM on carrier board */
- eeprom_carrier_board: eeprom@57 {
- compatible = "st,24c02";
- pagesize = <16>;
- reg = <0x57>;
- status = "disabled";
- };
-};
-
-/* Verdin PCIE_1 */
-&pcie {
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_pcie>;
- /* PCIE_1_RESET# (SODIMM 244) */
- reset-gpio = <&gpio4 19 GPIO_ACTIVE_LOW>;
-};
-
-&pcie_phy {
- clocks = <&hsio_blk_ctrl>;
- clock-names = "ref";
- fsl,clkreq-unsupported;
- fsl,refclk-pad-mode = <IMX8_PCIE_REFCLK_PAD_OUTPUT>;
-};
-
-/* Verdin PWM_1 */
-&pwm1 {
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_pwm_1>;
- #pwm-cells = <3>;
-};
-
-/* Verdin PWM_2 */
-&pwm2 {
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_pwm_2>;
- #pwm-cells = <3>;
-};
-
-/* Verdin PWM_3_DSI */
-&pwm3 {
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_pwm_3>;
- #pwm-cells = <3>;
-};
-
-/* TODO: Verdin I2S_1 */
-
-/* TODO: Verdin I2S_2 */
-
-&snvs_pwrkey {
- status = "okay";
-};
-
-/* Verdin UART_1 */
-&uart1 {
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_uart1>;
- uart-has-rtscts;
-};
-
-/* Verdin UART_2 */
-&uart2 {
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_uart2>;
- uart-has-rtscts;
-};
-
-/* Verdin UART_3, used as the Linux Console */
-&uart3 {
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_uart3>;
-};
-
-/* Verdin UART_4, used for Bluetooth on Wi-Fi/Bluetooth SKUs */
-&uart4 {
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_uart4>;
-};
-
-/* Verdin USB_1 */
-&usb3_0 {
- fsl,disable-port-power-control;
- fsl,over-current-active-low;
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_usb_1_oc_n>;
-};
-
-&usb_dwc3_0 {
- /* dual role only, not full featured OTG */
- adp-disable;
- dr_mode = "otg";
- hnp-disable;
- maximum-speed = "high-speed";
- role-switch-default-mode = "peripheral";
- srp-disable;
- usb-role-switch;
-
- connector {
- compatible = "gpio-usb-b-connector", "usb-b-connector";
- id-gpios = <&gpio2 10 GPIO_ACTIVE_HIGH>;
- label = "Type-C";
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_usb_1_id>;
- self-powered;
- type = "micro";
- vbus-supply = <®_usb1_vbus>;
- };
-};
-
-/* Verdin USB_2 */
-&usb3_1 {
- fsl,disable-port-power-control;
-};
-
-&usb3_phy1 {
- vbus-supply = <®_usb2_vbus>;
-};
-
-&usb_dwc3_1 {
- dr_mode = "host";
-};
-
-/* Verdin SD_1 */
-&usdhc2 {
- assigned-clocks = <&clk IMX8MP_CLK_USDHC2>;
- assigned-clock-rates = <400000000>;
- bus-width = <4>;
- cd-gpios = <&gpio2 12 GPIO_ACTIVE_LOW>;
- disable-wp;
- pinctrl-names = "default", "state_100mhz", "state_200mhz", "sleep";
- pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_cd>;
- pinctrl-1 = <&pinctrl_usdhc2_100mhz>, <&pinctrl_usdhc2_cd>;
- pinctrl-2 = <&pinctrl_usdhc2_200mhz>, <&pinctrl_usdhc2_cd>;
- pinctrl-3 = <&pinctrl_usdhc2_sleep>, <&pinctrl_usdhc2_cd_sleep>;
- vmmc-supply = <®_usdhc2_vmmc>;
-};
-
-/* On-module eMMC */
-&usdhc3 {
- assigned-clocks = <&clk IMX8MP_CLK_USDHC3_ROOT>;
- assigned-clock-rates = <400000000>;
- bus-width = <8>;
- non-removable;
- pinctrl-names = "default", "state_100mhz", "state_200mhz";
- pinctrl-0 = <&pinctrl_usdhc3>;
- pinctrl-1 = <&pinctrl_usdhc3_100mhz>;
- pinctrl-2 = <&pinctrl_usdhc3_200mhz>;
- status = "okay";
-};
-
-&wdog1 {
- fsl,ext-reset-output;
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_wdog>;
- status = "okay";
-};
-
-&iomuxc {
- pinctrl_bt_uart: btuartgrp {
- fsl,pins =
- <MX8MP_IOMUXC_ECSPI2_MISO__UART4_DCE_CTS 0x1c4>,
- <MX8MP_IOMUXC_ECSPI2_MOSI__UART4_DCE_TX 0x1c4>,
- <MX8MP_IOMUXC_ECSPI2_SCLK__UART4_DCE_RX 0x1c4>,
- <MX8MP_IOMUXC_ECSPI2_SS0__UART4_DCE_RTS 0x1c4>;
- };
-
- pinctrl_ctrl_sleep_moci: ctrlsleepmocigrp {
- fsl,pins =
- <MX8MP_IOMUXC_SAI3_RXC__GPIO4_IO29 0x1c4>; /* SODIMM 256 */
- };
-
- pinctrl_ecspi1: ecspi1grp {
- fsl,pins =
- <MX8MP_IOMUXC_ECSPI1_MISO__ECSPI1_MISO 0x1c4>, /* SODIMM 198 */
- <MX8MP_IOMUXC_ECSPI1_MOSI__ECSPI1_MOSI 0x4>, /* SODIMM 200 */
- <MX8MP_IOMUXC_ECSPI1_SCLK__ECSPI1_SCLK 0x4>, /* SODIMM 196 */
- <MX8MP_IOMUXC_ECSPI1_SS0__GPIO5_IO09 0x1c4>; /* SODIMM 202 */
- };
-
- /* Connection On Board PHY */
- pinctrl_eqos: eqosgrp {
- fsl,pins =
- <MX8MP_IOMUXC_ENET_MDC__ENET_QOS_MDC 0x3>,
- <MX8MP_IOMUXC_ENET_MDIO__ENET_QOS_MDIO 0x3>,
- <MX8MP_IOMUXC_ENET_RD0__ENET_QOS_RGMII_RD0 0x91>,
- <MX8MP_IOMUXC_ENET_RD1__ENET_QOS_RGMII_RD1 0x91>,
- <MX8MP_IOMUXC_ENET_RD2__ENET_QOS_RGMII_RD2 0x91>,
- <MX8MP_IOMUXC_ENET_RD3__ENET_QOS_RGMII_RD3 0x91>,
- <MX8MP_IOMUXC_ENET_RXC__CCM_ENET_QOS_CLOCK_GENERATE_RX_CLK 0x91>,
- <MX8MP_IOMUXC_ENET_RX_CTL__ENET_QOS_RGMII_RX_CTL 0x91>,
- <MX8MP_IOMUXC_ENET_TD0__ENET_QOS_RGMII_TD0 0x1f>,
- <MX8MP_IOMUXC_ENET_TD1__ENET_QOS_RGMII_TD1 0x1f>,
- <MX8MP_IOMUXC_ENET_TD2__ENET_QOS_RGMII_TD2 0x1f>,
- <MX8MP_IOMUXC_ENET_TD3__ENET_QOS_RGMII_TD3 0x1f>,
- <MX8MP_IOMUXC_ENET_TX_CTL__ENET_QOS_RGMII_TX_CTL 0x1f>,
- <MX8MP_IOMUXC_ENET_TXC__CCM_ENET_QOS_CLOCK_GENERATE_TX_CLK 0x1f>;
- };
-
- /* ETH_INT# shared with TPM_INT# (usually N/A) */
- pinctrl_eth_tpm_int: ethtpmintgrp {
- fsl,pins =
- <MX8MP_IOMUXC_GPIO1_IO10__GPIO1_IO10 0x1c4>;
- };
-
- /* Connection Carrier Board PHY ETH_2 */
- pinctrl_fec: fecgrp {
- fsl,pins =
- <MX8MP_IOMUXC_SAI1_RXD2__ENET1_MDC 0x3>, /* SODIMM 193 */
- <MX8MP_IOMUXC_SAI1_RXD3__ENET1_MDIO 0x3>, /* SODIMM 191 */
- <MX8MP_IOMUXC_SAI1_RXD4__ENET1_RGMII_RD0 0x91>, /* SODIMM 201 */
- <MX8MP_IOMUXC_SAI1_RXD5__ENET1_RGMII_RD1 0x91>, /* SODIMM 203 */
- <MX8MP_IOMUXC_SAI1_RXD6__ENET1_RGMII_RD2 0x91>, /* SODIMM 205 */
- <MX8MP_IOMUXC_SAI1_RXD7__ENET1_RGMII_RD3 0x91>, /* SODIMM 207 */
- <MX8MP_IOMUXC_SAI1_TXC__ENET1_RGMII_RXC 0x91>, /* SODIMM 197 */
- <MX8MP_IOMUXC_SAI1_TXFS__ENET1_RGMII_RX_CTL 0x91>, /* SODIMM 199 */
- <MX8MP_IOMUXC_SAI1_TXD0__ENET1_RGMII_TD0 0x1f>, /* SODIMM 221 */
- <MX8MP_IOMUXC_SAI1_TXD1__ENET1_RGMII_TD1 0x1f>, /* SODIMM 219 */
- <MX8MP_IOMUXC_SAI1_TXD2__ENET1_RGMII_TD2 0x1f>, /* SODIMM 217 */
- <MX8MP_IOMUXC_SAI1_TXD3__ENET1_RGMII_TD3 0x1f>, /* SODIMM 215 */
- <MX8MP_IOMUXC_SAI1_TXD4__ENET1_RGMII_TX_CTL 0x1f>, /* SODIMM 211 */
- <MX8MP_IOMUXC_SAI1_TXD5__ENET1_RGMII_TXC 0x1f>, /* SODIMM 213 */
- <MX8MP_IOMUXC_SAI1_TXD6__GPIO4_IO18 0x1c4>; /* SODIMM 189 */
- };
-
- pinctrl_fec_sleep: fecsleepgrp {
- fsl,pins =
- <MX8MP_IOMUXC_SAI1_RXD2__ENET1_MDC 0x3>, /* SODIMM 193 */
- <MX8MP_IOMUXC_SAI1_RXD3__ENET1_MDIO 0x3>, /* SODIMM 191 */
- <MX8MP_IOMUXC_SAI1_RXD4__ENET1_RGMII_RD0 0x91>, /* SODIMM 201 */
- <MX8MP_IOMUXC_SAI1_RXD5__ENET1_RGMII_RD1 0x91>, /* SODIMM 203 */
- <MX8MP_IOMUXC_SAI1_RXD6__ENET1_RGMII_RD2 0x91>, /* SODIMM 205 */
- <MX8MP_IOMUXC_SAI1_RXD7__ENET1_RGMII_RD3 0x91>, /* SODIMM 207 */
- <MX8MP_IOMUXC_SAI1_TXC__ENET1_RGMII_RXC 0x91>, /* SODIMM 197 */
- <MX8MP_IOMUXC_SAI1_TXFS__ENET1_RGMII_RX_CTL 0x91>, /* SODIMM 199 */
- <MX8MP_IOMUXC_SAI1_TXD0__GPIO4_IO12 0x1f>, /* SODIMM 221 */
- <MX8MP_IOMUXC_SAI1_TXD1__GPIO4_IO13 0x1f>, /* SODIMM 219 */
- <MX8MP_IOMUXC_SAI1_TXD2__GPIO4_IO14 0x1f>, /* SODIMM 217 */
- <MX8MP_IOMUXC_SAI1_TXD3__GPIO4_IO15 0x1f>, /* SODIMM 215 */
- <MX8MP_IOMUXC_SAI1_TXD4__GPIO4_IO16 0x1f>, /* SODIMM 211 */
- <MX8MP_IOMUXC_SAI1_TXD5__GPIO4_IO17 0x1f>, /* SODIMM 213 */
- <MX8MP_IOMUXC_SAI1_TXD6__GPIO4_IO18 0x184>; /* SODIMM 189 */
- };
-
- pinctrl_flexcan1: flexcan1grp {
- fsl,pins =
- <MX8MP_IOMUXC_SPDIF_RX__CAN1_RX 0x154>, /* SODIMM 22 */
- <MX8MP_IOMUXC_SPDIF_TX__CAN1_TX 0x154>; /* SODIMM 20 */
- };
-
- pinctrl_flexcan2: flexcan2grp {
- fsl,pins =
- <MX8MP_IOMUXC_SAI2_MCLK__CAN2_RX 0x154>, /* SODIMM 26 */
- <MX8MP_IOMUXC_SAI2_TXD0__CAN2_TX 0x154>; /* SODIMM 24 */
- };
-
- pinctrl_flexspi0: flexspi0grp {
- fsl,pins =
- <MX8MP_IOMUXC_NAND_ALE__FLEXSPI_A_SCLK 0x1c2>, /* SODIMM 52 */
- <MX8MP_IOMUXC_NAND_CE0_B__FLEXSPI_A_SS0_B 0x82>, /* SODIMM 54 */
- <MX8MP_IOMUXC_NAND_DQS__FLEXSPI_A_DQS 0x82>, /* SODIMM 66 */
- <MX8MP_IOMUXC_NAND_DATA00__FLEXSPI_A_DATA00 0x82>, /* SODIMM 56 */
- <MX8MP_IOMUXC_NAND_DATA01__FLEXSPI_A_DATA01 0x82>, /* SODIMM 58 */
- <MX8MP_IOMUXC_NAND_DATA02__FLEXSPI_A_DATA02 0x82>, /* SODIMM 60 */
- <MX8MP_IOMUXC_NAND_DATA03__FLEXSPI_A_DATA03 0x82>, /* SODIMM 62 */
- <MX8MP_IOMUXC_NAND_READY_B__GPIO3_IO16 0x82>; /* SODIMM 64 */
- };
-
- pinctrl_gpio1: gpio1grp {
- fsl,pins =
- <MX8MP_IOMUXC_GPIO1_IO00__GPIO1_IO00 0x184>; /* SODIMM 206 */
- };
-
- pinctrl_gpio2: gpio2grp {
- fsl,pins =
- <MX8MP_IOMUXC_GPIO1_IO01__GPIO1_IO01 0x1c4>; /* SODIMM 208 */
- };
-
- pinctrl_gpio3: gpio3grp {
- fsl,pins =
- <MX8MP_IOMUXC_GPIO1_IO05__GPIO1_IO05 0x184>; /* SODIMM 210 */
- };
-
- pinctrl_gpio4: gpio4grp {
- fsl,pins =
- <MX8MP_IOMUXC_GPIO1_IO06__GPIO1_IO06 0x184>; /* SODIMM 212 */
- };
-
- pinctrl_gpio5: gpio5grp {
- fsl,pins =
- <MX8MP_IOMUXC_GPIO1_IO07__GPIO1_IO07 0x184>; /* SODIMM 216 */
- };
-
- pinctrl_gpio6: gpio6grp {
- fsl,pins =
- <MX8MP_IOMUXC_GPIO1_IO08__GPIO1_IO08 0x184>; /* SODIMM 218 */
- };
-
- pinctrl_gpio7: gpio7grp {
- fsl,pins =
- <MX8MP_IOMUXC_SAI1_RXD1__GPIO4_IO03 0x184>; /* SODIMM 220 */
- };
-
- pinctrl_gpio8: gpio8grp {
- fsl,pins =
- <MX8MP_IOMUXC_SAI1_RXC__GPIO4_IO01 0x184>; /* SODIMM 222 */
- };
-
- /* Verdin GPIO_9_DSI (pulled-up as active-low) */
- pinctrl_gpio_9_dsi: gpio9dsigrp {
- fsl,pins =
- <MX8MP_IOMUXC_SAI2_TXC__GPIO4_IO25 0x1c4>; /* SODIMM 17 */
- };
-
- /* Verdin GPIO_10_DSI */
- pinctrl_gpio_10_dsi: gpio10dsigrp {
- fsl,pins =
- <MX8MP_IOMUXC_SAI3_RXFS__GPIO4_IO28 0x1c4>; /* SODIMM 21 */
- };
-
- /* Non-wifi MSP usage only */
- pinctrl_gpio_hog1: gpiohog1grp {
- fsl,pins =
- <MX8MP_IOMUXC_ECSPI2_MISO__GPIO5_IO12 0x1c4>, /* SODIMM 116 */
- <MX8MP_IOMUXC_ECSPI2_MOSI__GPIO5_IO11 0x1c4>, /* SODIMM 152 */
- <MX8MP_IOMUXC_ECSPI2_SCLK__GPIO5_IO10 0x1c4>, /* SODIMM 164 */
- <MX8MP_IOMUXC_ECSPI2_SS0__GPIO5_IO13 0x1c4>; /* SODIMM 128 */
- };
-
- /* USB_2_OC# */
- pinctrl_gpio_hog2: gpiohog2grp {
- fsl,pins =
- <MX8MP_IOMUXC_SAI3_MCLK__GPIO5_IO02 0x1c4>; /* SODIMM 187 */
- };
-
- pinctrl_gpio_hog3: gpiohog3grp {
- fsl,pins =
- /* CSI_1_MCLK */
- <MX8MP_IOMUXC_GPIO1_IO15__GPIO1_IO15 0x1c4>; /* SODIMM 91 */
- };
-
- /* Wifi usage only */
- pinctrl_gpio_hog4: gpiohog4grp {
- fsl,pins =
- <MX8MP_IOMUXC_UART4_RXD__GPIO5_IO28 0x1c4>, /* SODIMM 151 */
- <MX8MP_IOMUXC_UART4_TXD__GPIO5_IO29 0x1c4>; /* SODIMM 153 */
- };
-
- pinctrl_gpio_keys: gpiokeysgrp {
- fsl,pins =
- <MX8MP_IOMUXC_SAI1_RXFS__GPIO4_IO00 0x1c4>; /* SODIMM 252 */
- };
-
- pinctrl_hdmi_hog: hdmihoggrp {
- fsl,pins =
- <MX8MP_IOMUXC_HDMI_CEC__HDMIMIX_HDMI_CEC 0x40000019>, /* SODIMM 63 */
- <MX8MP_IOMUXC_HDMI_DDC_SCL__HDMIMIX_HDMI_SCL 0x400001c3>, /* SODIMM 59 */
- <MX8MP_IOMUXC_HDMI_DDC_SDA__HDMIMIX_HDMI_SDA 0x400001c3>, /* SODIMM 57 */
- <MX8MP_IOMUXC_HDMI_HPD__HDMIMIX_HDMI_HPD 0x40000019>; /* SODIMM 61 */
- };
-
- /* On-module I2C */
- pinctrl_i2c1: i2c1grp {
- fsl,pins =
- <MX8MP_IOMUXC_I2C1_SCL__I2C1_SCL 0x400001c6>, /* PMIC_I2C_SCL */
- <MX8MP_IOMUXC_I2C1_SDA__I2C1_SDA 0x400001c6>; /* PMIC_I2C_SDA */
- };
-
- pinctrl_i2c1_gpio: i2c1gpiogrp {
- fsl,pins =
- <MX8MP_IOMUXC_I2C1_SCL__GPIO5_IO14 0x400001c6>, /* PMIC_I2C_SCL */
- <MX8MP_IOMUXC_I2C1_SDA__GPIO5_IO15 0x400001c6>; /* PMIC_I2C_SDA */
- };
-
- /* Verdin I2C_2_DSI */
- pinctrl_i2c2: i2c2grp {
- fsl,pins =
- <MX8MP_IOMUXC_I2C2_SCL__I2C2_SCL 0x400001c6>, /* SODIMM 55 */
- <MX8MP_IOMUXC_I2C2_SDA__I2C2_SDA 0x400001c6>; /* SODIMM 53 */
- };
-
- pinctrl_i2c2_gpio: i2c2gpiogrp {
- fsl,pins =
- <MX8MP_IOMUXC_I2C2_SCL__GPIO5_IO16 0x400001c6>, /* SODIMM 55 */
- <MX8MP_IOMUXC_I2C2_SDA__GPIO5_IO17 0x400001c6>; /* SODIMM 53 */
- };
-
- /* Verdin I2C_4_CSI */
- pinctrl_i2c3: i2c3grp {
- fsl,pins =
- <MX8MP_IOMUXC_I2C3_SCL__I2C3_SCL 0x400001c6>, /* SODIMM 95 */
- <MX8MP_IOMUXC_I2C3_SDA__I2C3_SDA 0x400001c6>; /* SODIMM 93 */
- };
-
- pinctrl_i2c3_gpio: i2c3gpiogrp {
- fsl,pins =
- <MX8MP_IOMUXC_I2C3_SCL__GPIO5_IO18 0x400001c6>, /* SODIMM 95 */
- <MX8MP_IOMUXC_I2C3_SDA__GPIO5_IO19 0x400001c6>; /* SODIMM 93 */
- };
-
- /* Verdin I2C_1 */
- pinctrl_i2c4: i2c4grp {
- fsl,pins =
- <MX8MP_IOMUXC_I2C4_SCL__I2C4_SCL 0x400001c6>, /* SODIMM 14 */
- <MX8MP_IOMUXC_I2C4_SDA__I2C4_SDA 0x400001c6>; /* SODIMM 12 */
- };
-
- pinctrl_i2c4_gpio: i2c4gpiogrp {
- fsl,pins =
- <MX8MP_IOMUXC_I2C4_SCL__GPIO5_IO20 0x400001c6>, /* SODIMM 14 */
- <MX8MP_IOMUXC_I2C4_SDA__GPIO5_IO21 0x400001c6>; /* SODIMM 12 */
- };
-
- /* Verdin I2S_2_BCLK (TOUCH_RESET#) */
- pinctrl_i2s_2_bclk_touch_reset: i2s2bclktouchresetgrp {
- fsl,pins =
- <MX8MP_IOMUXC_SAI3_TXC__GPIO5_IO00 0x184>; /* SODIMM 42 */
- };
-
- /* Verdin I2S_2_D_OUT shared with SAI3 */
- pinctrl_i2s_2_d_out_dsi_1_bkl_en: i2s2doutdsi1bklengrp {
- fsl,pins =
- <MX8MP_IOMUXC_SAI3_TXD__GPIO5_IO01 0x184>; /* SODIMM 46 */
- };
-
- pinctrl_pcie: pciegrp {
- fsl,pins =
- <MX8MP_IOMUXC_SAI1_TXD7__GPIO4_IO19 0x4>, /* SODIMM 244 */
- <MX8MP_IOMUXC_SD2_RESET_B__GPIO2_IO19 0x1c4>; /* PMIC_EN_PCIe_CLK, unused */
- };
-
- pinctrl_pmic: pmicirqgrp {
- fsl,pins =
- <MX8MP_IOMUXC_GPIO1_IO03__GPIO1_IO03 0x1c4>; /* PMIC_INT# */
- };
-
- pinctrl_pwm_1: pwm1grp {
- fsl,pins =
- <MX8MP_IOMUXC_SPDIF_EXT_CLK__PWM1_OUT 0x6>; /* SODIMM 15 */
- };
-
- pinctrl_pwm_2: pwm2grp {
- fsl,pins =
- <MX8MP_IOMUXC_GPIO1_IO11__PWM2_OUT 0x6>; /* SODIMM 16 */
- };
-
- /* Verdin PWM_3_DSI shared with GPIO3_IO20 */
- pinctrl_pwm_3: pwm3grp {
- fsl,pins =
- <MX8MP_IOMUXC_SAI5_RXC__PWM3_OUT 0x6>; /* SODIMM 19 */
- };
-
- /* Verdin PWM_3_DSI (pulled-down as active-high) shared with PWM3_OUT */
- pinctrl_pwm_3_dsi_hpd_gpio: pwm3dsi1hpdgpiogrp {
- fsl,pins =
- <MX8MP_IOMUXC_SAI5_RXC__GPIO3_IO20 0x184>; /* SODIMM 19 */
- };
-
- pinctrl_reg_eth: regethgrp {
- fsl,pins =
- <MX8MP_IOMUXC_SD2_WP__GPIO2_IO20 0x184>; /* PMIC_EN_ETH */
- };
-
- pinctrl_sai1: sai1grp {
- fsl,pins =
- <MX8MP_IOMUXC_SAI1_MCLK__AUDIOMIX_SAI1_MCLK 0x96>, /* SODIMM 38 */
- <MX8MP_IOMUXC_SAI1_RXD0__AUDIOMIX_SAI1_RX_DATA00 0x1d6>, /* SODIMM 36 */
- <MX8MP_IOMUXC_SAI5_MCLK__AUDIOMIX_SAI1_TX_BCLK 0x1d6>, /* SODIMM 30 */
- <MX8MP_IOMUXC_SAI5_RXD1__AUDIOMIX_SAI1_TX_SYNC 0x1d6>, /* SODIMM 32 */
- <MX8MP_IOMUXC_SAI5_RXFS__AUDIOMIX_SAI1_TX_DATA00 0x96>; /* SODIMM 34 */
- };
-
- pinctrl_sai3: sai3grp {
- fsl,pins =
- <MX8MP_IOMUXC_SAI3_RXD__AUDIOMIX_SAI3_RX_DATA00 0x1d6>, /* SODIMM 48 */
- <MX8MP_IOMUXC_SAI3_TXC__AUDIOMIX_SAI3_TX_BCLK 0x1d6>, /* SODIMM 42 */
- <MX8MP_IOMUXC_SAI3_TXD__AUDIOMIX_SAI3_TX_DATA00 0x96>, /* SODIMM 46 */
- <MX8MP_IOMUXC_SAI3_TXFS__AUDIOMIX_SAI3_TX_SYNC 0x1d6>; /* SODIMM 44 */
- };
-
- pinctrl_uart1: uart1grp {
- fsl,pins =
- <MX8MP_IOMUXC_SAI2_RXD0__UART1_DCE_RTS 0x1c4>, /* SODIMM 135 */
- <MX8MP_IOMUXC_SAI2_TXFS__UART1_DCE_CTS 0x1c4>, /* SODIMM 133 */
- <MX8MP_IOMUXC_UART1_RXD__UART1_DCE_RX 0x1c4>, /* SODIMM 129 */
- <MX8MP_IOMUXC_UART1_TXD__UART1_DCE_TX 0x1c4>; /* SODIMM 131 */
- };
-
- pinctrl_uart2: uart2grp {
- fsl,pins =
- <MX8MP_IOMUXC_SD1_DATA4__UART2_DCE_RTS 0x1c4>, /* SODIMM 143 */
- <MX8MP_IOMUXC_SD1_DATA5__UART2_DCE_CTS 0x1c4>, /* SODIMM 141 */
- <MX8MP_IOMUXC_UART2_RXD__UART2_DCE_RX 0x1c4>, /* SODIMM 137 */
- <MX8MP_IOMUXC_UART2_TXD__UART2_DCE_TX 0x1c4>; /* SODIMM 139 */
- };
-
- pinctrl_uart3: uart3grp {
- fsl,pins =
- <MX8MP_IOMUXC_UART3_RXD__UART3_DCE_RX 0x1c4>, /* SODIMM 147 */
- <MX8MP_IOMUXC_UART3_TXD__UART3_DCE_TX 0x1c4>; /* SODIMM 149 */
- };
-
- /* Non-wifi usage only */
- pinctrl_uart4: uart4grp {
- fsl,pins =
- <MX8MP_IOMUXC_UART4_RXD__UART4_DCE_RX 0x1c4>, /* SODIMM 151 */
- <MX8MP_IOMUXC_UART4_TXD__UART4_DCE_TX 0x1c4>; /* SODIMM 153 */
- };
-
- pinctrl_usb1_vbus: usb1vbusgrp {
- fsl,pins =
- <MX8MP_IOMUXC_GPIO1_IO12__GPIO1_IO12 0x106>; /* SODIMM 155 */
- };
-
- /* USB_1_ID */
- pinctrl_usb_1_id: usb1idgrp {
- fsl,pins =
- <MX8MP_IOMUXC_SD1_RESET_B__GPIO2_IO10 0x1c4>; /* SODIMM 161 */
- };
-
- /* USB_1_OC# */
- pinctrl_usb_1_oc_n: usb1ocngrp {
- fsl,pins =
- <MX8MP_IOMUXC_GPIO1_IO13__USB1_OTG_OC 0x1c4>; /* SODIMM 157 */
- };
-
- pinctrl_usb2_vbus: usb2vbusgrp {
- fsl,pins =
- <MX8MP_IOMUXC_GPIO1_IO14__GPIO1_IO14 0x106>; /* SODIMM 185 */
- };
-
- /* On-module Wi-Fi */
- pinctrl_usdhc1: usdhc1grp {
- fsl,pins =
- <MX8MP_IOMUXC_SD1_CLK__USDHC1_CLK 0x190>,
- <MX8MP_IOMUXC_SD1_CMD__USDHC1_CMD 0x1d0>,
- <MX8MP_IOMUXC_SD1_DATA0__USDHC1_DATA0 0x1d0>,
- <MX8MP_IOMUXC_SD1_DATA1__USDHC1_DATA1 0x1d0>,
- <MX8MP_IOMUXC_SD1_DATA2__USDHC1_DATA2 0x1d0>,
- <MX8MP_IOMUXC_SD1_DATA3__USDHC1_DATA3 0x1d0>;
- };
-
- pinctrl_usdhc1_100mhz: usdhc1-100mhzgrp {
- fsl,pins =
- <MX8MP_IOMUXC_SD1_CLK__USDHC1_CLK 0x194>,
- <MX8MP_IOMUXC_SD1_CMD__USDHC1_CMD 0x1d4>,
- <MX8MP_IOMUXC_SD1_DATA0__USDHC1_DATA0 0x1d4>,
- <MX8MP_IOMUXC_SD1_DATA1__USDHC1_DATA1 0x1d4>,
- <MX8MP_IOMUXC_SD1_DATA2__USDHC1_DATA2 0x1d4>,
- <MX8MP_IOMUXC_SD1_DATA3__USDHC1_DATA3 0x1d4>;
- };
-
- pinctrl_usdhc1_200mhz: usdhc1-200mhzgrp {
- fsl,pins =
- <MX8MP_IOMUXC_SD1_CLK__USDHC1_CLK 0x196>,
- <MX8MP_IOMUXC_SD1_CMD__USDHC1_CMD 0x1d6>,
- <MX8MP_IOMUXC_SD1_DATA0__USDHC1_DATA0 0x1d6>,
- <MX8MP_IOMUXC_SD1_DATA1__USDHC1_DATA1 0x1d6>,
- <MX8MP_IOMUXC_SD1_DATA2__USDHC1_DATA2 0x1d6>,
- <MX8MP_IOMUXC_SD1_DATA3__USDHC1_DATA3 0x1d6>;
- };
-
- pinctrl_usdhc2_cd: usdhc2cdgrp {
- fsl,pins =
- <MX8MP_IOMUXC_SD2_CD_B__GPIO2_IO12 0x1c4>; /* SODIMM 84 */
- };
-
- pinctrl_usdhc2_cd_sleep: usdhc2cdslpgrp {
- fsl,pins =
- <MX8MP_IOMUXC_SD2_CD_B__GPIO2_IO12 0x0>; /* SODIMM 84 */
- };
-
- pinctrl_usdhc2_pwr_en: usdhc2pwrengrp {
- fsl,pins =
- <MX8MP_IOMUXC_SAI2_RXC__GPIO4_IO22 0x4>; /* SODIMM 76 */
- };
-
- pinctrl_usdhc2: usdhc2grp {
- fsl,pins =
- <MX8MP_IOMUXC_GPIO1_IO04__USDHC2_VSELECT 0x4>, /* PMIC_USDHC_VSELECT */
- <MX8MP_IOMUXC_SD2_CLK__USDHC2_CLK 0x190>, /* SODIMM 78 */
- <MX8MP_IOMUXC_SD2_CMD__USDHC2_CMD 0x1d0>, /* SODIMM 74 */
- <MX8MP_IOMUXC_SD2_DATA0__USDHC2_DATA0 0x1d0>, /* SODIMM 80 */
- <MX8MP_IOMUXC_SD2_DATA1__USDHC2_DATA1 0x1d0>, /* SODIMM 82 */
- <MX8MP_IOMUXC_SD2_DATA2__USDHC2_DATA2 0x1d0>, /* SODIMM 70 */
- <MX8MP_IOMUXC_SD2_DATA3__USDHC2_DATA3 0x1d0>; /* SODIMM 72 */
- };
-
- pinctrl_usdhc2_100mhz: usdhc2-100mhzgrp {
- fsl,pins =
- <MX8MP_IOMUXC_GPIO1_IO04__USDHC2_VSELECT 0x4>,
- <MX8MP_IOMUXC_SD2_CLK__USDHC2_CLK 0x194>,
- <MX8MP_IOMUXC_SD2_CMD__USDHC2_CMD 0x1d4>,
- <MX8MP_IOMUXC_SD2_DATA0__USDHC2_DATA0 0x1d4>,
- <MX8MP_IOMUXC_SD2_DATA1__USDHC2_DATA1 0x1d4>,
- <MX8MP_IOMUXC_SD2_DATA2__USDHC2_DATA2 0x1d4>,
- <MX8MP_IOMUXC_SD2_DATA3__USDHC2_DATA3 0x1d4>;
- };
-
- pinctrl_usdhc2_200mhz: usdhc2-200mhzgrp {
- fsl,pins =
- <MX8MP_IOMUXC_GPIO1_IO04__USDHC2_VSELECT 0x4>,
- <MX8MP_IOMUXC_SD2_CLK__USDHC2_CLK 0x196>,
- <MX8MP_IOMUXC_SD2_CMD__USDHC2_CMD 0x1d6>,
- <MX8MP_IOMUXC_SD2_DATA0__USDHC2_DATA0 0x1d6>,
- <MX8MP_IOMUXC_SD2_DATA1__USDHC2_DATA1 0x1d6>,
- <MX8MP_IOMUXC_SD2_DATA2__USDHC2_DATA2 0x1d6>,
- <MX8MP_IOMUXC_SD2_DATA3__USDHC2_DATA3 0x1d6>;
- };
-
- /* Avoid backfeeding with removed card power */
- pinctrl_usdhc2_sleep: usdhc2slpgrp {
- fsl,pins =
- <MX8MP_IOMUXC_GPIO1_IO04__USDHC2_VSELECT 0x0>,
- <MX8MP_IOMUXC_SD2_CLK__USDHC2_CLK 0x100>,
- <MX8MP_IOMUXC_SD2_CMD__USDHC2_CMD 0x100>,
- <MX8MP_IOMUXC_SD2_DATA0__USDHC2_DATA0 0x100>,
- <MX8MP_IOMUXC_SD2_DATA1__USDHC2_DATA1 0x100>,
- <MX8MP_IOMUXC_SD2_DATA2__USDHC2_DATA2 0x100>,
- <MX8MP_IOMUXC_SD2_DATA3__USDHC2_DATA3 0x100>;
- };
-
- pinctrl_usdhc3: usdhc3grp {
- fsl,pins =
- <MX8MP_IOMUXC_GPIO1_IO09__USDHC3_RESET_B 0x1d1>,
- <MX8MP_IOMUXC_NAND_CE1_B__USDHC3_STROBE 0x190>,
- <MX8MP_IOMUXC_NAND_CE2_B__USDHC3_DATA5 0x1d0>,
- <MX8MP_IOMUXC_NAND_CE3_B__USDHC3_DATA6 0x1d0>,
- <MX8MP_IOMUXC_NAND_CLE__USDHC3_DATA7 0x1d0>,
- <MX8MP_IOMUXC_NAND_DATA04__USDHC3_DATA0 0x1d0>,
- <MX8MP_IOMUXC_NAND_DATA05__USDHC3_DATA1 0x1d0>,
- <MX8MP_IOMUXC_NAND_DATA06__USDHC3_DATA2 0x1d0>,
- <MX8MP_IOMUXC_NAND_DATA07__USDHC3_DATA3 0x1d0>,
- <MX8MP_IOMUXC_NAND_RE_B__USDHC3_DATA4 0x1d0>,
- <MX8MP_IOMUXC_NAND_WE_B__USDHC3_CLK 0x190>,
- <MX8MP_IOMUXC_NAND_WP_B__USDHC3_CMD 0x1d0>;
- };
-
- pinctrl_usdhc3_100mhz: usdhc3-100mhzgrp {
- fsl,pins =
- <MX8MP_IOMUXC_GPIO1_IO09__USDHC3_RESET_B 0x1d1>,
- <MX8MP_IOMUXC_NAND_CE1_B__USDHC3_STROBE 0x194>,
- <MX8MP_IOMUXC_NAND_CE2_B__USDHC3_DATA5 0x1d4>,
- <MX8MP_IOMUXC_NAND_CE3_B__USDHC3_DATA6 0x1d4>,
- <MX8MP_IOMUXC_NAND_CLE__USDHC3_DATA7 0x1d4>,
- <MX8MP_IOMUXC_NAND_DATA04__USDHC3_DATA0 0x1d4>,
- <MX8MP_IOMUXC_NAND_DATA05__USDHC3_DATA1 0x1d4>,
- <MX8MP_IOMUXC_NAND_DATA06__USDHC3_DATA2 0x1d4>,
- <MX8MP_IOMUXC_NAND_DATA07__USDHC3_DATA3 0x1d4>,
- <MX8MP_IOMUXC_NAND_RE_B__USDHC3_DATA4 0x1d4>,
- <MX8MP_IOMUXC_NAND_WE_B__USDHC3_CLK 0x194>,
- <MX8MP_IOMUXC_NAND_WP_B__USDHC3_CMD 0x1d4>;
- };
-
- pinctrl_usdhc3_200mhz: usdhc3-200mhzgrp {
- fsl,pins =
- <MX8MP_IOMUXC_GPIO1_IO09__USDHC3_RESET_B 0x1d1>,
- <MX8MP_IOMUXC_NAND_CE1_B__USDHC3_STROBE 0x196>,
- <MX8MP_IOMUXC_NAND_CE2_B__USDHC3_DATA5 0x1d2>,
- <MX8MP_IOMUXC_NAND_CE3_B__USDHC3_DATA6 0x1d2>,
- <MX8MP_IOMUXC_NAND_CLE__USDHC3_DATA7 0x1d2>,
- <MX8MP_IOMUXC_NAND_DATA04__USDHC3_DATA0 0x1d2>,
- <MX8MP_IOMUXC_NAND_DATA05__USDHC3_DATA1 0x1d2>,
- <MX8MP_IOMUXC_NAND_DATA06__USDHC3_DATA2 0x1d2>,
- <MX8MP_IOMUXC_NAND_DATA07__USDHC3_DATA3 0x1d2>,
- <MX8MP_IOMUXC_NAND_RE_B__USDHC3_DATA4 0x1d2>,
- <MX8MP_IOMUXC_NAND_WE_B__USDHC3_CLK 0x196>,
- <MX8MP_IOMUXC_NAND_WP_B__USDHC3_CMD 0x1d6>;
- };
-
- pinctrl_wdog: wdoggrp {
- fsl,pins =
- <MX8MP_IOMUXC_GPIO1_IO02__WDOG1_WDOG_B 0xc6>; /* PMIC_WDI */
- };
-
- pinctrl_bluetooth_ctrl: bluetoothctrlgrp {
- fsl,pins =
- <MX8MP_IOMUXC_SD1_DATA6__GPIO2_IO08 0x1c4>; /* WIFI_WKUP_BT */
- };
-
- pinctrl_wifi_ctrl: wifictrlgrp {
- fsl,pins =
- <MX8MP_IOMUXC_SD1_DATA7__GPIO2_IO09 0x1c4>; /* WIFI_WKUP_WLAN */
- };
-
- pinctrl_wifi_i2s: wifii2sgrp {
- fsl,pins =
- <MX8MP_IOMUXC_SAI2_RXFS__GPIO4_IO21 0x1d6>, /* WIFI_TX_SYNC */
- <MX8MP_IOMUXC_SAI5_RXD0__GPIO3_IO21 0x96>, /* WIFI_RX_DATA0 */
- <MX8MP_IOMUXC_SAI5_RXD2__GPIO3_IO23 0x1d6>, /* WIFI_TX_BCLK */
- <MX8MP_IOMUXC_SAI5_RXD3__GPIO3_IO24 0x1d6>; /* WIFI_TX_DATA0 */
- };
-
- pinctrl_wifi_pwr_en: wifipwrengrp {
- fsl,pins =
- <MX8MP_IOMUXC_SD1_STROBE__GPIO2_IO11 0x184>; /* PMIC_EN_WIFI */
- };
-};
diff --git a/arch/arm/dts/imx8mq-evk.dts b/arch/arm/dts/imx8mq-evk.dts
deleted file mode 100644
index 82387b9..0000000
--- a/arch/arm/dts/imx8mq-evk.dts
+++ /dev/null
@@ -1,712 +0,0 @@
-// SPDX-License-Identifier: (GPL-2.0 OR MIT)
-/*
- * Copyright 2017 NXP
- * Copyright (C) 2017-2018 Pengutronix, Lucas Stach <kernel@pengutronix.de>
- */
-
-/dts-v1/;
-
-#include "imx8mq.dtsi"
-
-/ {
- model = "NXP i.MX8MQ EVK";
- compatible = "fsl,imx8mq-evk", "fsl,imx8mq";
-
- chosen {
- stdout-path = &uart1;
- };
-
- memory@40000000 {
- device_type = "memory";
- reg = <0x00000000 0x40000000 0 0xc0000000>;
- };
-
- pcie0_refclk: pcie0-refclk {
- compatible = "fixed-clock";
- #clock-cells = <0>;
- clock-frequency = <100000000>;
- };
-
- reg_pcie1: regulator-pcie {
- compatible = "regulator-fixed";
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_pcie1_reg>;
- regulator-name = "MPCIE_3V3";
- regulator-min-microvolt = <3300000>;
- regulator-max-microvolt = <3300000>;
- gpio = <&gpio5 10 GPIO_ACTIVE_HIGH>;
- enable-active-high;
- };
-
- reg_usdhc2_vmmc: regulator-vsd-3v3 {
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_reg_usdhc2>;
- compatible = "regulator-fixed";
- regulator-name = "VSD_3V3";
- regulator-min-microvolt = <3300000>;
- regulator-max-microvolt = <3300000>;
- gpio = <&gpio2 19 GPIO_ACTIVE_HIGH>;
- enable-active-high;
- };
-
- buck2_reg: regulator-buck2 {
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_buck2>;
- compatible = "regulator-gpio";
- regulator-name = "vdd_arm";
- regulator-min-microvolt = <900000>;
- regulator-max-microvolt = <1000000>;
- gpios = <&gpio1 13 GPIO_ACTIVE_HIGH>;
- states = <1000000 0x0
- 900000 0x1>;
- regulator-boot-on;
- regulator-always-on;
- };
-
- ir-receiver {
- compatible = "gpio-ir-receiver";
- gpios = <&gpio1 12 GPIO_ACTIVE_LOW>;
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_ir>;
- linux,autosuspend-period = <125>;
- };
-
- audio_codec_bt_sco: audio-codec-bt-sco {
- compatible = "linux,bt-sco";
- #sound-dai-cells = <1>;
- };
-
- wm8524: audio-codec {
- #sound-dai-cells = <0>;
- compatible = "wlf,wm8524";
- wlf,mute-gpios = <&gpio1 8 GPIO_ACTIVE_LOW>;
- };
-
- sound-bt-sco {
- compatible = "simple-audio-card";
- simple-audio-card,name = "bt-sco-audio";
- simple-audio-card,format = "dsp_a";
- simple-audio-card,bitclock-inversion;
- simple-audio-card,frame-master = <&btcpu>;
- simple-audio-card,bitclock-master = <&btcpu>;
-
- btcpu: simple-audio-card,cpu {
- sound-dai = <&sai3>;
- dai-tdm-slot-num = <2>;
- dai-tdm-slot-width = <16>;
- };
-
- simple-audio-card,codec {
- sound-dai = <&audio_codec_bt_sco 1>;
- };
- };
-
- sound-wm8524 {
- compatible = "simple-audio-card";
- simple-audio-card,name = "wm8524-audio";
- simple-audio-card,format = "i2s";
- simple-audio-card,frame-master = <&cpudai>;
- simple-audio-card,bitclock-master = <&cpudai>;
- simple-audio-card,widgets =
- "Line", "Left Line Out Jack",
- "Line", "Right Line Out Jack";
- simple-audio-card,routing =
- "Left Line Out Jack", "LINEVOUTL",
- "Right Line Out Jack", "LINEVOUTR";
-
- cpudai: simple-audio-card,cpu {
- sound-dai = <&sai2>;
- };
-
- link_codec: simple-audio-card,codec {
- sound-dai = <&wm8524>;
- clocks = <&clk IMX8MQ_CLK_SAI2_ROOT>;
- };
- };
-
- sound-spdif {
- compatible = "fsl,imx-audio-spdif";
- model = "imx-spdif";
- spdif-controller = <&spdif1>;
- spdif-out;
- spdif-in;
- };
-
- sound-hdmi-arc {
- compatible = "fsl,imx-audio-spdif";
- model = "imx-hdmi-arc";
- spdif-controller = <&spdif2>;
- spdif-in;
- };
-};
-
-&A53_0 {
- cpu-supply = <&buck2_reg>;
-};
-
-&A53_1 {
- cpu-supply = <&buck2_reg>;
-};
-
-&A53_2 {
- cpu-supply = <&buck2_reg>;
-};
-
-&A53_3 {
- cpu-supply = <&buck2_reg>;
-};
-
-&ddrc {
- operating-points-v2 = <&ddrc_opp_table>;
- status = "okay";
-
- ddrc_opp_table: opp-table {
- compatible = "operating-points-v2";
-
- opp-25M {
- opp-hz = /bits/ 64 <25000000>;
- };
-
- opp-100M {
- opp-hz = /bits/ 64 <100000000>;
- };
-
- /*
- * On imx8mq B0 PLL can't be bypassed so low bus is 166M
- */
- opp-166M {
- opp-hz = /bits/ 64 <166935483>;
- };
-
- opp-800M {
- opp-hz = /bits/ 64 <800000000>;
- };
- };
-};
-
-&dphy {
- status = "okay";
-};
-
-&fec1 {
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_fec1>;
- phy-mode = "rgmii-id";
- phy-handle = <ðphy0>;
- fsl,magic-packet;
- status = "okay";
-
- mdio {
- #address-cells = <1>;
- #size-cells = <0>;
-
- ethphy0: ethernet-phy@0 {
- compatible = "ethernet-phy-ieee802.3-c22";
- reg = <0>;
- reset-gpios = <&gpio1 9 GPIO_ACTIVE_LOW>;
- reset-assert-us = <10000>;
- qca,disable-smarteee;
- vddio-supply = <&vddh>;
-
- vddh: vddh-regulator {
- };
- };
- };
-};
-
-&gpio5 {
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_wifi_reset>;
-
- wl-reg-on-hog {
- gpio-hog;
- gpios = <29 GPIO_ACTIVE_HIGH>;
- output-high;
- };
-};
-
-&i2c1 {
- clock-frequency = <100000>;
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_i2c1>;
- status = "okay";
-
- pmic@8 {
- compatible = "fsl,pfuze100";
- reg = <0x8>;
-
- regulators {
- sw1a_reg: sw1ab {
- regulator-min-microvolt = <825000>;
- regulator-max-microvolt = <1100000>;
- };
-
- sw1c_reg: sw1c {
- regulator-min-microvolt = <825000>;
- regulator-max-microvolt = <1100000>;
- };
-
- sw2_reg: sw2 {
- regulator-min-microvolt = <1100000>;
- regulator-max-microvolt = <1100000>;
- regulator-always-on;
- };
-
- sw3a_reg: sw3ab {
- regulator-min-microvolt = <825000>;
- regulator-max-microvolt = <1100000>;
- regulator-always-on;
- };
-
- sw4_reg: sw4 {
- regulator-min-microvolt = <1800000>;
- regulator-max-microvolt = <1800000>;
- regulator-always-on;
- };
-
- swbst_reg: swbst {
- regulator-min-microvolt = <5000000>;
- regulator-max-microvolt = <5150000>;
- };
-
- snvs_reg: vsnvs {
- regulator-min-microvolt = <1000000>;
- regulator-max-microvolt = <3000000>;
- regulator-always-on;
- };
-
- vref_reg: vrefddr {
- regulator-always-on;
- };
-
- vgen1_reg: vgen1 {
- regulator-min-microvolt = <800000>;
- regulator-max-microvolt = <1550000>;
- };
-
- vgen2_reg: vgen2 {
- regulator-min-microvolt = <850000>;
- regulator-max-microvolt = <975000>;
- regulator-always-on;
- };
-
- vgen3_reg: vgen3 {
- regulator-min-microvolt = <1675000>;
- regulator-max-microvolt = <1975000>;
- regulator-always-on;
- };
-
- vgen4_reg: vgen4 {
- regulator-min-microvolt = <1625000>;
- regulator-max-microvolt = <1875000>;
- regulator-always-on;
- };
-
- vgen5_reg: vgen5 {
- regulator-min-microvolt = <3075000>;
- regulator-max-microvolt = <3625000>;
- regulator-always-on;
- };
-
- vgen6_reg: vgen6 {
- regulator-min-microvolt = <1800000>;
- regulator-max-microvolt = <3300000>;
- };
- };
- };
-};
-
-&lcdif {
- status = "okay";
-};
-
-&mipi_dsi {
- #address-cells = <1>;
- #size-cells = <0>;
- status = "okay";
-
- panel@0 {
- pinctrl-0 = <&pinctrl_mipi_dsi>;
- pinctrl-names = "default";
- compatible = "raydium,rm67191";
- reg = <0>;
- reset-gpios = <&gpio5 6 GPIO_ACTIVE_LOW>;
- dsi-lanes = <4>;
-
- port {
- panel_in: endpoint {
- remote-endpoint = <&mipi_dsi_out>;
- };
- };
- };
-
- ports {
- port@1 {
- reg = <1>;
- mipi_dsi_out: endpoint {
- remote-endpoint = <&panel_in>;
- };
- };
- };
-};
-
-&pcie0 {
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_pcie0>;
- reset-gpio = <&gpio5 28 GPIO_ACTIVE_LOW>;
- clocks = <&clk IMX8MQ_CLK_PCIE1_ROOT>,
- <&clk IMX8MQ_CLK_PCIE1_AUX>,
- <&clk IMX8MQ_CLK_PCIE1_PHY>,
- <&pcie0_refclk>;
- clock-names = "pcie", "pcie_aux", "pcie_phy", "pcie_bus";
- vph-supply = <&vgen5_reg>;
- status = "okay";
-};
-
-&pcie1 {
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_pcie1>;
- reset-gpio = <&gpio5 12 GPIO_ACTIVE_LOW>;
- clocks = <&clk IMX8MQ_CLK_PCIE2_ROOT>,
- <&clk IMX8MQ_CLK_PCIE2_AUX>,
- <&clk IMX8MQ_CLK_PCIE2_PHY>,
- <&pcie0_refclk>;
- clock-names = "pcie", "pcie_aux", "pcie_phy", "pcie_bus";
- vpcie-supply = <®_pcie1>;
- vph-supply = <&vgen5_reg>;
- status = "okay";
-};
-
-&pgc_gpu {
- power-supply = <&sw1a_reg>;
-};
-
-&pgc_vpu {
- power-supply = <&sw1c_reg>;
-};
-
-&qspi0 {
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_qspi>;
- status = "okay";
-
- n25q256a: flash@0 {
- reg = <0>;
- #address-cells = <1>;
- #size-cells = <1>;
- compatible = "micron,n25q256a", "jedec,spi-nor";
- spi-max-frequency = <29000000>;
- spi-tx-bus-width = <1>;
- spi-rx-bus-width = <4>;
- };
-};
-
-&sai2 {
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_sai2>;
- assigned-clocks = <&clk IMX8MQ_AUDIO_PLL1_BYPASS>, <&clk IMX8MQ_CLK_SAI2>;
- assigned-clock-parents = <&clk IMX8MQ_AUDIO_PLL1>, <&clk IMX8MQ_AUDIO_PLL1_OUT>;
- assigned-clock-rates = <0>, <24576000>;
- status = "okay";
-};
-
-&sai3 {
- #sound-dai-cells = <0>;
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_sai3>;
- assigned-clocks = <&clk IMX8MQ_CLK_SAI3>;
- assigned-clock-parents = <&clk IMX8MQ_AUDIO_PLL1_OUT>;
- assigned-clock-rates = <24576000>;
- status = "okay";
-};
-
-&snvs_pwrkey {
- status = "okay";
-};
-
-&spdif1 {
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_spdif1>;
- assigned-clocks = <&clk IMX8MQ_CLK_SPDIF1>;
- assigned-clock-parents = <&clk IMX8MQ_AUDIO_PLL1_OUT>;
- assigned-clock-rates = <24576000>;
- status = "okay";
-};
-
-&spdif2 {
- assigned-clocks = <&clk IMX8MQ_CLK_SPDIF2>;
- assigned-clock-parents = <&clk IMX8MQ_AUDIO_PLL1_OUT>;
- assigned-clock-rates = <24576000>;
- status = "okay";
-};
-
-&uart1 {
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_uart1>;
- status = "okay";
-};
-
-&usb3_phy1 {
- status = "okay";
-};
-
-&usb_dwc3_1 {
- dr_mode = "host";
- status = "okay";
-};
-
-&usdhc1 {
- assigned-clocks = <&clk IMX8MQ_CLK_USDHC1>;
- assigned-clock-rates = <400000000>;
- pinctrl-names = "default", "state_100mhz", "state_200mhz";
- pinctrl-0 = <&pinctrl_usdhc1>;
- pinctrl-1 = <&pinctrl_usdhc1_100mhz>;
- pinctrl-2 = <&pinctrl_usdhc1_200mhz>;
- vqmmc-supply = <&sw4_reg>;
- bus-width = <8>;
- non-removable;
- no-sd;
- no-sdio;
- status = "okay";
-};
-
-&usdhc2 {
- assigned-clocks = <&clk IMX8MQ_CLK_USDHC2>;
- assigned-clock-rates = <200000000>;
- pinctrl-names = "default", "state_100mhz", "state_200mhz";
- pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>;
- pinctrl-1 = <&pinctrl_usdhc2_100mhz>, <&pinctrl_usdhc2_gpio>;
- pinctrl-2 = <&pinctrl_usdhc2_200mhz>, <&pinctrl_usdhc2_gpio>;
- cd-gpios = <&gpio2 12 GPIO_ACTIVE_LOW>;
- vmmc-supply = <®_usdhc2_vmmc>;
- status = "okay";
-};
-
-&wdog1 {
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_wdog>;
- fsl,ext-reset-output;
- status = "okay";
-};
-
-&iomuxc {
- pinctrl_buck2: vddarmgrp {
- fsl,pins = <
- MX8MQ_IOMUXC_GPIO1_IO13_GPIO1_IO13 0x19
- >;
- };
-
- pinctrl_fec1: fec1grp {
- fsl,pins = <
- MX8MQ_IOMUXC_ENET_MDC_ENET1_MDC 0x3
- MX8MQ_IOMUXC_ENET_MDIO_ENET1_MDIO 0x23
- MX8MQ_IOMUXC_ENET_TD3_ENET1_RGMII_TD3 0x1f
- MX8MQ_IOMUXC_ENET_TD2_ENET1_RGMII_TD2 0x1f
- MX8MQ_IOMUXC_ENET_TD1_ENET1_RGMII_TD1 0x1f
- MX8MQ_IOMUXC_ENET_TD0_ENET1_RGMII_TD0 0x1f
- MX8MQ_IOMUXC_ENET_RD3_ENET1_RGMII_RD3 0x91
- MX8MQ_IOMUXC_ENET_RD2_ENET1_RGMII_RD2 0x91
- MX8MQ_IOMUXC_ENET_RD1_ENET1_RGMII_RD1 0x91
- MX8MQ_IOMUXC_ENET_RD0_ENET1_RGMII_RD0 0x91
- MX8MQ_IOMUXC_ENET_TXC_ENET1_RGMII_TXC 0x1f
- MX8MQ_IOMUXC_ENET_RXC_ENET1_RGMII_RXC 0x91
- MX8MQ_IOMUXC_ENET_RX_CTL_ENET1_RGMII_RX_CTL 0x91
- MX8MQ_IOMUXC_ENET_TX_CTL_ENET1_RGMII_TX_CTL 0x1f
- MX8MQ_IOMUXC_GPIO1_IO09_GPIO1_IO9 0x19
- >;
- };
-
- pinctrl_i2c1: i2c1grp {
- fsl,pins = <
- MX8MQ_IOMUXC_I2C1_SCL_I2C1_SCL 0x4000007f
- MX8MQ_IOMUXC_I2C1_SDA_I2C1_SDA 0x4000007f
- >;
- };
-
- pinctrl_ir: irgrp {
- fsl,pins = <
- MX8MQ_IOMUXC_GPIO1_IO12_GPIO1_IO12 0x4f
- >;
- };
-
- pinctrl_mipi_dsi: mipidsigrp {
- fsl,pins = <
- MX8MQ_IOMUXC_ECSPI1_SCLK_GPIO5_IO6 0x16
- >;
- };
-
- pinctrl_pcie0: pcie0grp {
- fsl,pins = <
- MX8MQ_IOMUXC_I2C4_SCL_PCIE1_CLKREQ_B 0x76
- MX8MQ_IOMUXC_UART4_RXD_GPIO5_IO28 0x16
- >;
- };
-
- pinctrl_pcie1: pcie1grp {
- fsl,pins = <
- MX8MQ_IOMUXC_I2C4_SDA_PCIE2_CLKREQ_B 0x76
- MX8MQ_IOMUXC_ECSPI2_MISO_GPIO5_IO12 0x16
- >;
- };
-
- pinctrl_pcie1_reg: pcie1reggrp {
- fsl,pins = <
- MX8MQ_IOMUXC_ECSPI2_SCLK_GPIO5_IO10 0x16
- >;
- };
-
- pinctrl_qspi: qspigrp {
- fsl,pins = <
- MX8MQ_IOMUXC_NAND_ALE_QSPI_A_SCLK 0x82
- MX8MQ_IOMUXC_NAND_CE0_B_QSPI_A_SS0_B 0x82
- MX8MQ_IOMUXC_NAND_DATA00_QSPI_A_DATA0 0x82
- MX8MQ_IOMUXC_NAND_DATA01_QSPI_A_DATA1 0x82
- MX8MQ_IOMUXC_NAND_DATA02_QSPI_A_DATA2 0x82
- MX8MQ_IOMUXC_NAND_DATA03_QSPI_A_DATA3 0x82
- >;
- };
-
- pinctrl_reg_usdhc2: regusdhc2gpiogrp {
- fsl,pins = <
- MX8MQ_IOMUXC_SD2_RESET_B_GPIO2_IO19 0x41
- >;
- };
-
- pinctrl_sai2: sai2grp {
- fsl,pins = <
- MX8MQ_IOMUXC_SAI2_TXFS_SAI2_TX_SYNC 0xd6
- MX8MQ_IOMUXC_SAI2_TXC_SAI2_TX_BCLK 0xd6
- MX8MQ_IOMUXC_SAI2_MCLK_SAI2_MCLK 0xd6
- MX8MQ_IOMUXC_SAI2_TXD0_SAI2_TX_DATA0 0xd6
- MX8MQ_IOMUXC_GPIO1_IO08_GPIO1_IO8 0xd6
- >;
- };
-
- pinctrl_sai3: sai3grp {
- fsl,pins = <
- MX8MQ_IOMUXC_SAI3_TXFS_SAI3_TX_SYNC 0xd6
- MX8MQ_IOMUXC_SAI3_TXC_SAI3_TX_BCLK 0xd6
- MX8MQ_IOMUXC_SAI3_TXD_SAI3_TX_DATA0 0xd6
- MX8MQ_IOMUXC_SAI3_RXD_SAI3_RX_DATA0 0xd6
- >;
- };
-
- pinctrl_spdif1: spdif1grp {
- fsl,pins = <
- MX8MQ_IOMUXC_SPDIF_TX_SPDIF1_OUT 0xd6
- MX8MQ_IOMUXC_SPDIF_RX_SPDIF1_IN 0xd6
- >;
- };
-
- pinctrl_uart1: uart1grp {
- fsl,pins = <
- MX8MQ_IOMUXC_UART1_RXD_UART1_DCE_RX 0x49
- MX8MQ_IOMUXC_UART1_TXD_UART1_DCE_TX 0x49
- >;
- };
-
- pinctrl_usdhc1: usdhc1grp {
- fsl,pins = <
- MX8MQ_IOMUXC_SD1_CLK_USDHC1_CLK 0x83
- MX8MQ_IOMUXC_SD1_CMD_USDHC1_CMD 0xc3
- MX8MQ_IOMUXC_SD1_DATA0_USDHC1_DATA0 0xc3
- MX8MQ_IOMUXC_SD1_DATA1_USDHC1_DATA1 0xc3
- MX8MQ_IOMUXC_SD1_DATA2_USDHC1_DATA2 0xc3
- MX8MQ_IOMUXC_SD1_DATA3_USDHC1_DATA3 0xc3
- MX8MQ_IOMUXC_SD1_DATA4_USDHC1_DATA4 0xc3
- MX8MQ_IOMUXC_SD1_DATA5_USDHC1_DATA5 0xc3
- MX8MQ_IOMUXC_SD1_DATA6_USDHC1_DATA6 0xc3
- MX8MQ_IOMUXC_SD1_DATA7_USDHC1_DATA7 0xc3
- MX8MQ_IOMUXC_SD1_STROBE_USDHC1_STROBE 0x83
- MX8MQ_IOMUXC_SD1_RESET_B_USDHC1_RESET_B 0xc1
- >;
- };
-
- pinctrl_usdhc1_100mhz: usdhc1-100grp {
- fsl,pins = <
- MX8MQ_IOMUXC_SD1_CLK_USDHC1_CLK 0x8d
- MX8MQ_IOMUXC_SD1_CMD_USDHC1_CMD 0xcd
- MX8MQ_IOMUXC_SD1_DATA0_USDHC1_DATA0 0xcd
- MX8MQ_IOMUXC_SD1_DATA1_USDHC1_DATA1 0xcd
- MX8MQ_IOMUXC_SD1_DATA2_USDHC1_DATA2 0xcd
- MX8MQ_IOMUXC_SD1_DATA3_USDHC1_DATA3 0xcd
- MX8MQ_IOMUXC_SD1_DATA4_USDHC1_DATA4 0xcd
- MX8MQ_IOMUXC_SD1_DATA5_USDHC1_DATA5 0xcd
- MX8MQ_IOMUXC_SD1_DATA6_USDHC1_DATA6 0xcd
- MX8MQ_IOMUXC_SD1_DATA7_USDHC1_DATA7 0xcd
- MX8MQ_IOMUXC_SD1_STROBE_USDHC1_STROBE 0x8d
- MX8MQ_IOMUXC_SD1_RESET_B_USDHC1_RESET_B 0xc1
- >;
- };
-
- pinctrl_usdhc1_200mhz: usdhc1-200grp {
- fsl,pins = <
- MX8MQ_IOMUXC_SD1_CLK_USDHC1_CLK 0x9f
- MX8MQ_IOMUXC_SD1_CMD_USDHC1_CMD 0xdf
- MX8MQ_IOMUXC_SD1_DATA0_USDHC1_DATA0 0xdf
- MX8MQ_IOMUXC_SD1_DATA1_USDHC1_DATA1 0xdf
- MX8MQ_IOMUXC_SD1_DATA2_USDHC1_DATA2 0xdf
- MX8MQ_IOMUXC_SD1_DATA3_USDHC1_DATA3 0xdf
- MX8MQ_IOMUXC_SD1_DATA4_USDHC1_DATA4 0xdf
- MX8MQ_IOMUXC_SD1_DATA5_USDHC1_DATA5 0xdf
- MX8MQ_IOMUXC_SD1_DATA6_USDHC1_DATA6 0xdf
- MX8MQ_IOMUXC_SD1_DATA7_USDHC1_DATA7 0xdf
- MX8MQ_IOMUXC_SD1_STROBE_USDHC1_STROBE 0x9f
- MX8MQ_IOMUXC_SD1_RESET_B_USDHC1_RESET_B 0xc1
- >;
- };
-
- pinctrl_usdhc2_gpio: usdhc2gpiogrp {
- fsl,pins = <
- MX8MQ_IOMUXC_SD2_CD_B_GPIO2_IO12 0x41
- >;
- };
-
- pinctrl_usdhc2: usdhc2grp {
- fsl,pins = <
- MX8MQ_IOMUXC_SD2_CLK_USDHC2_CLK 0x83
- MX8MQ_IOMUXC_SD2_CMD_USDHC2_CMD 0xc3
- MX8MQ_IOMUXC_SD2_DATA0_USDHC2_DATA0 0xc3
- MX8MQ_IOMUXC_SD2_DATA1_USDHC2_DATA1 0xc3
- MX8MQ_IOMUXC_SD2_DATA2_USDHC2_DATA2 0xc3
- MX8MQ_IOMUXC_SD2_DATA3_USDHC2_DATA3 0xc3
- MX8MQ_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0xc1
- >;
- };
-
- pinctrl_usdhc2_100mhz: usdhc2-100grp {
- fsl,pins = <
- MX8MQ_IOMUXC_SD2_CLK_USDHC2_CLK 0x85
- MX8MQ_IOMUXC_SD2_CMD_USDHC2_CMD 0xc5
- MX8MQ_IOMUXC_SD2_DATA0_USDHC2_DATA0 0xc5
- MX8MQ_IOMUXC_SD2_DATA1_USDHC2_DATA1 0xc5
- MX8MQ_IOMUXC_SD2_DATA2_USDHC2_DATA2 0xc5
- MX8MQ_IOMUXC_SD2_DATA3_USDHC2_DATA3 0xc5
- MX8MQ_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0xc1
- >;
- };
-
- pinctrl_usdhc2_200mhz: usdhc2-200grp {
- fsl,pins = <
- MX8MQ_IOMUXC_SD2_CLK_USDHC2_CLK 0x87
- MX8MQ_IOMUXC_SD2_CMD_USDHC2_CMD 0xc7
- MX8MQ_IOMUXC_SD2_DATA0_USDHC2_DATA0 0xc7
- MX8MQ_IOMUXC_SD2_DATA1_USDHC2_DATA1 0xc7
- MX8MQ_IOMUXC_SD2_DATA2_USDHC2_DATA2 0xc7
- MX8MQ_IOMUXC_SD2_DATA3_USDHC2_DATA3 0xc7
- MX8MQ_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0xc1
- >;
- };
-
- pinctrl_wdog: wdog1grp {
- fsl,pins = <
- MX8MQ_IOMUXC_GPIO1_IO02_WDOG1_WDOG_B 0xc6
- >;
- };
-
- pinctrl_wifi_reset: wifiresetgrp {
- fsl,pins = <
- MX8MQ_IOMUXC_UART4_TXD_GPIO5_IO29 0x16
- >;
- };
-};
diff --git a/arch/arm/dts/imx93-phyboard-segin-u-boot.dtsi b/arch/arm/dts/imx93-phyboard-segin-u-boot.dtsi
index 8bf28c2..6897c91 100644
--- a/arch/arm/dts/imx93-phyboard-segin-u-boot.dtsi
+++ b/arch/arm/dts/imx93-phyboard-segin-u-boot.dtsi
@@ -121,6 +121,21 @@
bootph-some-ram;
};
+/*
+ * Remove once USB support is added to imx93-phyboard-segin.dts upstream.
+ */
+&usbotg1 {
+ disable-over-current;
+ dr_mode = "otg";
+ status = "okay";
+};
+
+&usbotg2 {
+ disable-over-current;
+ dr_mode = "host";
+ status = "okay";
+};
+
&usdhc1 {
bootph-pre-ram;
bootph-some-ram;
diff --git a/arch/arm/dts/k3-am625-verdin-r5.dts b/arch/arm/dts/k3-am625-verdin-r5.dts
index 6b03e74..2b333e7 100644
--- a/arch/arm/dts/k3-am625-verdin-r5.dts
+++ b/arch/arm/dts/k3-am625-verdin-r5.dts
@@ -23,7 +23,7 @@
*/
assigned-clocks = <&k3_clks 61 0>, <&k3_clks 135 0>, <&k3_clks 157 20>;
assigned-clock-parents = <&k3_clks 61 2>, <0>, <&k3_clks 157 22>;
- assigned-clock-rates = <200000000>, <1000000000>, <25000000>;
+ assigned-clock-rates = <200000000>, <800000000>, <25000000>;
clocks = <&k3_clks 61 0>;
power-domains = <&k3_pds 61 TI_SCI_PD_EXCLUSIVE>,
<&k3_pds 135 TI_SCI_PD_EXCLUSIVE>,
diff --git a/arch/arm/dts/k3-am64-main.dtsi b/arch/arm/dts/k3-am64-main.dtsi
deleted file mode 100644
index 0df54a7..0000000
--- a/arch/arm/dts/k3-am64-main.dtsi
+++ /dev/null
@@ -1,1546 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0
-/*
- * Device Tree Source for AM642 SoC Family Main Domain peripherals
- *
- * Copyright (C) 2020-2021 Texas Instruments Incorporated - https://www.ti.com/
- */
-
-#include <dt-bindings/phy/phy-cadence.h>
-#include <dt-bindings/phy/phy-ti.h>
-
-/ {
- serdes_refclk: clock-cmnrefclk {
- #clock-cells = <0>;
- compatible = "fixed-clock";
- clock-frequency = <0>;
- };
-};
-
-&cbass_main {
- oc_sram: sram@70000000 {
- compatible = "mmio-sram";
- reg = <0x00 0x70000000 0x00 0x200000>;
- #address-cells = <1>;
- #size-cells = <1>;
- ranges = <0x0 0x00 0x70000000 0x200000>;
-
- tfa-sram@1c0000 {
- reg = <0x1c0000 0x20000>;
- };
-
- dmsc-sram@1e0000 {
- reg = <0x1e0000 0x1c000>;
- };
-
- sproxy-sram@1fc000 {
- reg = <0x1fc000 0x4000>;
- };
- };
-
- main_conf: syscon@43000000 {
- compatible = "ti,j721e-system-controller", "syscon", "simple-mfd";
- reg = <0x0 0x43000000 0x0 0x20000>;
- #address-cells = <1>;
- #size-cells = <1>;
- ranges = <0x0 0x0 0x43000000 0x20000>;
-
- chipid@14 {
- compatible = "ti,am654-chipid";
- reg = <0x00000014 0x4>;
- };
-
- serdes_ln_ctrl: mux-controller {
- compatible = "mmio-mux";
- #mux-control-cells = <1>;
- mux-reg-masks = <0x4080 0x3>; /* SERDES0 lane0 select */
- };
-
- phy_gmii_sel: phy@4044 {
- compatible = "ti,am654-phy-gmii-sel";
- reg = <0x4044 0x8>;
- #phy-cells = <1>;
- };
-
- epwm_tbclk: clock-controller@4140 {
- compatible = "ti,am64-epwm-tbclk";
- reg = <0x4130 0x4>;
- #clock-cells = <1>;
- };
- };
-
- gic500: interrupt-controller@1800000 {
- compatible = "arm,gic-v3";
- #address-cells = <2>;
- #size-cells = <2>;
- ranges;
- #interrupt-cells = <3>;
- interrupt-controller;
- reg = <0x00 0x01800000 0x00 0x10000>, /* GICD */
- <0x00 0x01840000 0x00 0xC0000>, /* GICR */
- <0x01 0x00000000 0x00 0x2000>, /* GICC */
- <0x01 0x00010000 0x00 0x1000>, /* GICH */
- <0x01 0x00020000 0x00 0x2000>; /* GICV */
- /*
- * vcpumntirq:
- * virtual CPU interface maintenance interrupt
- */
- interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
-
- gic_its: msi-controller@1820000 {
- compatible = "arm,gic-v3-its";
- reg = <0x00 0x01820000 0x00 0x10000>;
- socionext,synquacer-pre-its = <0x1000000 0x400000>;
- msi-controller;
- #msi-cells = <1>;
- };
- };
-
- dmss: bus@48000000 {
- compatible = "simple-mfd";
- #address-cells = <2>;
- #size-cells = <2>;
- dma-ranges;
- ranges = <0x00 0x48000000 0x00 0x48000000 0x00 0x06400000>;
-
- ti,sci-dev-id = <25>;
-
- secure_proxy_main: mailbox@4d000000 {
- compatible = "ti,am654-secure-proxy";
- #mbox-cells = <1>;
- reg-names = "target_data", "rt", "scfg";
- reg = <0x00 0x4d000000 0x00 0x80000>,
- <0x00 0x4a600000 0x00 0x80000>,
- <0x00 0x4a400000 0x00 0x80000>;
- interrupt-names = "rx_012";
- interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
- };
-
- inta_main_dmss: interrupt-controller@48000000 {
- compatible = "ti,sci-inta";
- reg = <0x00 0x48000000 0x00 0x100000>;
- #interrupt-cells = <0>;
- interrupt-controller;
- interrupt-parent = <&gic500>;
- msi-controller;
- ti,sci = <&dmsc>;
- ti,sci-dev-id = <28>;
- ti,interrupt-ranges = <4 68 36>;
- ti,unmapped-event-sources = <&main_bcdma>, <&main_pktdma>;
- };
-
- main_bcdma: dma-controller@485c0100 {
- compatible = "ti,am64-dmss-bcdma";
- reg = <0x00 0x485c0100 0x00 0x100>,
- <0x00 0x4c000000 0x00 0x20000>,
- <0x00 0x4a820000 0x00 0x20000>,
- <0x00 0x4aa40000 0x00 0x20000>,
- <0x00 0x4bc00000 0x00 0x100000>;
- reg-names = "gcfg", "bchanrt", "rchanrt", "tchanrt", "ringrt";
- msi-parent = <&inta_main_dmss>;
- #dma-cells = <3>;
-
- ti,sci = <&dmsc>;
- ti,sci-dev-id = <26>;
- ti,sci-rm-range-bchan = <0x20>; /* BLOCK_COPY_CHAN */
- ti,sci-rm-range-rchan = <0x21>; /* SPLIT_TR_RX_CHAN */
- ti,sci-rm-range-tchan = <0x22>; /* SPLIT_TR_TX_CHAN */
- };
-
- main_pktdma: dma-controller@485c0000 {
- compatible = "ti,am64-dmss-pktdma";
- reg = <0x00 0x485c0000 0x00 0x100>,
- <0x00 0x4a800000 0x00 0x20000>,
- <0x00 0x4aa00000 0x00 0x40000>,
- <0x00 0x4b800000 0x00 0x400000>;
- reg-names = "gcfg", "rchanrt", "tchanrt", "ringrt";
- msi-parent = <&inta_main_dmss>;
- #dma-cells = <2>;
-
- ti,sci = <&dmsc>;
- ti,sci-dev-id = <30>;
- ti,sci-rm-range-tchan = <0x23>, /* UNMAPPED_TX_CHAN */
- <0x24>, /* CPSW_TX_CHAN */
- <0x25>, /* SAUL_TX_0_CHAN */
- <0x26>, /* SAUL_TX_1_CHAN */
- <0x27>, /* ICSSG_0_TX_CHAN */
- <0x28>; /* ICSSG_1_TX_CHAN */
- ti,sci-rm-range-tflow = <0x10>, /* RING_UNMAPPED_TX_CHAN */
- <0x11>, /* RING_CPSW_TX_CHAN */
- <0x12>, /* RING_SAUL_TX_0_CHAN */
- <0x13>, /* RING_SAUL_TX_1_CHAN */
- <0x14>, /* RING_ICSSG_0_TX_CHAN */
- <0x15>; /* RING_ICSSG_1_TX_CHAN */
- ti,sci-rm-range-rchan = <0x29>, /* UNMAPPED_RX_CHAN */
- <0x2b>, /* CPSW_RX_CHAN */
- <0x2d>, /* SAUL_RX_0_CHAN */
- <0x2f>, /* SAUL_RX_1_CHAN */
- <0x31>, /* SAUL_RX_2_CHAN */
- <0x33>, /* SAUL_RX_3_CHAN */
- <0x35>, /* ICSSG_0_RX_CHAN */
- <0x37>; /* ICSSG_1_RX_CHAN */
- ti,sci-rm-range-rflow = <0x2a>, /* FLOW_UNMAPPED_RX_CHAN */
- <0x2c>, /* FLOW_CPSW_RX_CHAN */
- <0x2e>, /* FLOW_SAUL_RX_0/1_CHAN */
- <0x32>, /* FLOW_SAUL_RX_2/3_CHAN */
- <0x36>, /* FLOW_ICSSG_0_RX_CHAN */
- <0x38>; /* FLOW_ICSSG_1_RX_CHAN */
- };
- };
-
- dmsc: system-controller@44043000 {
- compatible = "ti,k2g-sci";
- ti,host-id = <12>;
- mbox-names = "rx", "tx";
- mboxes = <&secure_proxy_main 12>,
- <&secure_proxy_main 13>;
- reg-names = "debug_messages";
- reg = <0x00 0x44043000 0x00 0xfe0>;
-
- k3_pds: power-controller {
- compatible = "ti,sci-pm-domain";
- #power-domain-cells = <2>;
- };
-
- k3_clks: clock-controller {
- compatible = "ti,k2g-sci-clk";
- #clock-cells = <2>;
- };
-
- k3_reset: reset-controller {
- compatible = "ti,sci-reset";
- #reset-cells = <2>;
- };
- };
-
- main_pmx0: pinctrl@f4000 {
- compatible = "pinctrl-single";
- reg = <0x00 0xf4000 0x00 0x2d0>;
- #pinctrl-cells = <1>;
- pinctrl-single,register-width = <32>;
- pinctrl-single,function-mask = <0xffffffff>;
- };
-
- main_timer0: timer@2400000 {
- compatible = "ti,am654-timer";
- reg = <0x00 0x2400000 0x00 0x400>;
- interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&k3_clks 36 1>;
- clock-names = "fck";
- assigned-clocks = <&k3_clks 36 1>;
- assigned-clock-parents = <&k3_clks 36 2>;
- power-domains = <&k3_pds 36 TI_SCI_PD_EXCLUSIVE>;
- ti,timer-pwm;
- };
-
- main_timer1: timer@2410000 {
- compatible = "ti,am654-timer";
- reg = <0x00 0x2410000 0x00 0x400>;
- interrupts = <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&k3_clks 37 1>;
- clock-names = "fck";
- assigned-clocks = <&k3_clks 37 1>;
- assigned-clock-parents = <&k3_clks 37 2>;
- power-domains = <&k3_pds 37 TI_SCI_PD_EXCLUSIVE>;
- ti,timer-pwm;
- };
-
- main_timer2: timer@2420000 {
- compatible = "ti,am654-timer";
- reg = <0x00 0x2420000 0x00 0x400>;
- interrupts = <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&k3_clks 38 1>;
- clock-names = "fck";
- assigned-clocks = <&k3_clks 38 1>;
- assigned-clock-parents = <&k3_clks 38 2>;
- power-domains = <&k3_pds 38 TI_SCI_PD_EXCLUSIVE>;
- ti,timer-pwm;
- };
-
- main_timer3: timer@2430000 {
- compatible = "ti,am654-timer";
- reg = <0x00 0x2430000 0x00 0x400>;
- interrupts = <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&k3_clks 39 1>;
- clock-names = "fck";
- assigned-clocks = <&k3_clks 39 1>;
- assigned-clock-parents = <&k3_clks 39 2>;
- power-domains = <&k3_pds 39 TI_SCI_PD_EXCLUSIVE>;
- ti,timer-pwm;
- };
-
- main_timer4: timer@2440000 {
- compatible = "ti,am654-timer";
- reg = <0x00 0x2440000 0x00 0x400>;
- interrupts = <GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&k3_clks 40 1>;
- clock-names = "fck";
- assigned-clocks = <&k3_clks 40 1>;
- assigned-clock-parents = <&k3_clks 40 2>;
- power-domains = <&k3_pds 40 TI_SCI_PD_EXCLUSIVE>;
- ti,timer-pwm;
- };
-
- main_timer5: timer@2450000 {
- compatible = "ti,am654-timer";
- reg = <0x00 0x2450000 0x00 0x400>;
- interrupts = <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&k3_clks 41 1>;
- clock-names = "fck";
- assigned-clocks = <&k3_clks 41 1>;
- assigned-clock-parents = <&k3_clks 41 2>;
- power-domains = <&k3_pds 41 TI_SCI_PD_EXCLUSIVE>;
- ti,timer-pwm;
- };
-
- main_timer6: timer@2460000 {
- compatible = "ti,am654-timer";
- reg = <0x00 0x2460000 0x00 0x400>;
- interrupts = <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&k3_clks 42 1>;
- clock-names = "fck";
- assigned-clocks = <&k3_clks 42 1>;
- assigned-clock-parents = <&k3_clks 42 2>;
- power-domains = <&k3_pds 42 TI_SCI_PD_EXCLUSIVE>;
- ti,timer-pwm;
- };
-
- main_timer7: timer@2470000 {
- compatible = "ti,am654-timer";
- reg = <0x00 0x2470000 0x00 0x400>;
- interrupts = <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&k3_clks 43 1>;
- clock-names = "fck";
- assigned-clocks = <&k3_clks 43 1>;
- assigned-clock-parents = <&k3_clks 43 2>;
- power-domains = <&k3_pds 43 TI_SCI_PD_EXCLUSIVE>;
- ti,timer-pwm;
- };
-
- main_timer8: timer@2480000 {
- compatible = "ti,am654-timer";
- reg = <0x00 0x2480000 0x00 0x400>;
- interrupts = <GIC_SPI 128 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&k3_clks 44 1>;
- clock-names = "fck";
- assigned-clocks = <&k3_clks 44 1>;
- assigned-clock-parents = <&k3_clks 44 2>;
- power-domains = <&k3_pds 44 TI_SCI_PD_EXCLUSIVE>;
- ti,timer-pwm;
- };
-
- main_timer9: timer@2490000 {
- compatible = "ti,am654-timer";
- reg = <0x00 0x2490000 0x00 0x400>;
- interrupts = <GIC_SPI 129 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&k3_clks 45 1>;
- clock-names = "fck";
- assigned-clocks = <&k3_clks 45 1>;
- assigned-clock-parents = <&k3_clks 45 2>;
- power-domains = <&k3_pds 45 TI_SCI_PD_EXCLUSIVE>;
- ti,timer-pwm;
- };
-
- main_timer10: timer@24a0000 {
- compatible = "ti,am654-timer";
- reg = <0x00 0x24a0000 0x00 0x400>;
- interrupts = <GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&k3_clks 46 1>;
- clock-names = "fck";
- assigned-clocks = <&k3_clks 46 1>;
- assigned-clock-parents = <&k3_clks 46 2>;
- power-domains = <&k3_pds 46 TI_SCI_PD_EXCLUSIVE>;
- ti,timer-pwm;
- };
-
- main_timer11: timer@24b0000 {
- compatible = "ti,am654-timer";
- reg = <0x00 0x24b0000 0x00 0x400>;
- interrupts = <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&k3_clks 47 1>;
- clock-names = "fck";
- assigned-clocks = <&k3_clks 47 1>;
- assigned-clock-parents = <&k3_clks 47 2>;
- power-domains = <&k3_pds 47 TI_SCI_PD_EXCLUSIVE>;
- ti,timer-pwm;
- };
-
- main_esm: esm@420000 {
- compatible = "ti,j721e-esm";
- reg = <0x00 0x420000 0x00 0x1000>;
- ti,esm-pins = <160>, <161>;
- };
-
- main_uart0: serial@2800000 {
- compatible = "ti,am64-uart", "ti,am654-uart";
- reg = <0x00 0x02800000 0x00 0x100>;
- interrupts = <GIC_SPI 178 IRQ_TYPE_LEVEL_HIGH>;
- clock-frequency = <48000000>;
- power-domains = <&k3_pds 146 TI_SCI_PD_EXCLUSIVE>;
- clocks = <&k3_clks 146 0>;
- clock-names = "fclk";
- status = "disabled";
- };
-
- main_uart1: serial@2810000 {
- compatible = "ti,am64-uart", "ti,am654-uart";
- reg = <0x00 0x02810000 0x00 0x100>;
- interrupts = <GIC_SPI 179 IRQ_TYPE_LEVEL_HIGH>;
- clock-frequency = <48000000>;
- power-domains = <&k3_pds 152 TI_SCI_PD_EXCLUSIVE>;
- clocks = <&k3_clks 152 0>;
- clock-names = "fclk";
- status = "disabled";
- };
-
- main_uart2: serial@2820000 {
- compatible = "ti,am64-uart", "ti,am654-uart";
- reg = <0x00 0x02820000 0x00 0x100>;
- interrupts = <GIC_SPI 180 IRQ_TYPE_LEVEL_HIGH>;
- clock-frequency = <48000000>;
- power-domains = <&k3_pds 153 TI_SCI_PD_EXCLUSIVE>;
- clocks = <&k3_clks 153 0>;
- clock-names = "fclk";
- status = "disabled";
- };
-
- main_uart3: serial@2830000 {
- compatible = "ti,am64-uart", "ti,am654-uart";
- reg = <0x00 0x02830000 0x00 0x100>;
- interrupts = <GIC_SPI 181 IRQ_TYPE_LEVEL_HIGH>;
- clock-frequency = <48000000>;
- power-domains = <&k3_pds 154 TI_SCI_PD_EXCLUSIVE>;
- clocks = <&k3_clks 154 0>;
- clock-names = "fclk";
- status = "disabled";
- };
-
- main_uart4: serial@2840000 {
- compatible = "ti,am64-uart", "ti,am654-uart";
- reg = <0x00 0x02840000 0x00 0x100>;
- interrupts = <GIC_SPI 182 IRQ_TYPE_LEVEL_HIGH>;
- clock-frequency = <48000000>;
- power-domains = <&k3_pds 155 TI_SCI_PD_EXCLUSIVE>;
- clocks = <&k3_clks 155 0>;
- clock-names = "fclk";
- status = "disabled";
- };
-
- main_uart5: serial@2850000 {
- compatible = "ti,am64-uart", "ti,am654-uart";
- reg = <0x00 0x02850000 0x00 0x100>;
- interrupts = <GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH>;
- clock-frequency = <48000000>;
- power-domains = <&k3_pds 156 TI_SCI_PD_EXCLUSIVE>;
- clocks = <&k3_clks 156 0>;
- clock-names = "fclk";
- status = "disabled";
- };
-
- main_uart6: serial@2860000 {
- compatible = "ti,am64-uart", "ti,am654-uart";
- reg = <0x00 0x02860000 0x00 0x100>;
- interrupts = <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>;
- clock-frequency = <48000000>;
- power-domains = <&k3_pds 158 TI_SCI_PD_EXCLUSIVE>;
- clocks = <&k3_clks 158 0>;
- clock-names = "fclk";
- status = "disabled";
- };
-
- main_i2c0: i2c@20000000 {
- compatible = "ti,am64-i2c", "ti,omap4-i2c";
- reg = <0x00 0x20000000 0x00 0x100>;
- interrupts = <GIC_SPI 161 IRQ_TYPE_LEVEL_HIGH>;
- #address-cells = <1>;
- #size-cells = <0>;
- power-domains = <&k3_pds 102 TI_SCI_PD_EXCLUSIVE>;
- clocks = <&k3_clks 102 2>;
- clock-names = "fck";
- status = "disabled";
- };
-
- main_i2c1: i2c@20010000 {
- compatible = "ti,am64-i2c", "ti,omap4-i2c";
- reg = <0x00 0x20010000 0x00 0x100>;
- interrupts = <GIC_SPI 162 IRQ_TYPE_LEVEL_HIGH>;
- #address-cells = <1>;
- #size-cells = <0>;
- power-domains = <&k3_pds 103 TI_SCI_PD_EXCLUSIVE>;
- clocks = <&k3_clks 103 2>;
- clock-names = "fck";
- status = "disabled";
- };
-
- main_i2c2: i2c@20020000 {
- compatible = "ti,am64-i2c", "ti,omap4-i2c";
- reg = <0x00 0x20020000 0x00 0x100>;
- interrupts = <GIC_SPI 163 IRQ_TYPE_LEVEL_HIGH>;
- #address-cells = <1>;
- #size-cells = <0>;
- power-domains = <&k3_pds 104 TI_SCI_PD_EXCLUSIVE>;
- clocks = <&k3_clks 104 2>;
- clock-names = "fck";
- status = "disabled";
- };
-
- main_i2c3: i2c@20030000 {
- compatible = "ti,am64-i2c", "ti,omap4-i2c";
- reg = <0x00 0x20030000 0x00 0x100>;
- interrupts = <GIC_SPI 164 IRQ_TYPE_LEVEL_HIGH>;
- #address-cells = <1>;
- #size-cells = <0>;
- power-domains = <&k3_pds 105 TI_SCI_PD_EXCLUSIVE>;
- clocks = <&k3_clks 105 2>;
- clock-names = "fck";
- status = "disabled";
- };
-
- main_spi0: spi@20100000 {
- compatible = "ti,am654-mcspi", "ti,omap4-mcspi";
- reg = <0x00 0x20100000 0x00 0x400>;
- interrupts = <GIC_SPI 172 IRQ_TYPE_LEVEL_HIGH>;
- #address-cells = <1>;
- #size-cells = <0>;
- power-domains = <&k3_pds 141 TI_SCI_PD_EXCLUSIVE>;
- clocks = <&k3_clks 141 0>;
- dmas = <&main_pktdma 0xc300 0>, <&main_pktdma 0x4300 0>;
- dma-names = "tx0", "rx0";
- status = "disabled";
- };
-
- main_spi1: spi@20110000 {
- compatible = "ti,am654-mcspi","ti,omap4-mcspi";
- reg = <0x00 0x20110000 0x00 0x400>;
- interrupts = <GIC_SPI 173 IRQ_TYPE_LEVEL_HIGH>;
- #address-cells = <1>;
- #size-cells = <0>;
- power-domains = <&k3_pds 142 TI_SCI_PD_EXCLUSIVE>;
- clocks = <&k3_clks 142 0>;
- status = "disabled";
- };
-
- main_spi2: spi@20120000 {
- compatible = "ti,am654-mcspi","ti,omap4-mcspi";
- reg = <0x00 0x20120000 0x00 0x400>;
- interrupts = <GIC_SPI 174 IRQ_TYPE_LEVEL_HIGH>;
- #address-cells = <1>;
- #size-cells = <0>;
- power-domains = <&k3_pds 143 TI_SCI_PD_EXCLUSIVE>;
- clocks = <&k3_clks 143 0>;
- status = "disabled";
- };
-
- main_spi3: spi@20130000 {
- compatible = "ti,am654-mcspi","ti,omap4-mcspi";
- reg = <0x00 0x20130000 0x00 0x400>;
- interrupts = <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>;
- #address-cells = <1>;
- #size-cells = <0>;
- power-domains = <&k3_pds 144 TI_SCI_PD_EXCLUSIVE>;
- clocks = <&k3_clks 144 0>;
- status = "disabled";
- };
-
- main_spi4: spi@20140000 {
- compatible = "ti,am654-mcspi","ti,omap4-mcspi";
- reg = <0x00 0x20140000 0x00 0x400>;
- interrupts = <GIC_SPI 175 IRQ_TYPE_LEVEL_HIGH>;
- #address-cells = <1>;
- #size-cells = <0>;
- power-domains = <&k3_pds 145 TI_SCI_PD_EXCLUSIVE>;
- clocks = <&k3_clks 145 0>;
- status = "disabled";
- };
-
- main_gpio_intr: interrupt-controller@a00000 {
- compatible = "ti,sci-intr";
- reg = <0x00 0x00a00000 0x00 0x800>;
- ti,intr-trigger-type = <1>;
- interrupt-controller;
- interrupt-parent = <&gic500>;
- #interrupt-cells = <1>;
- ti,sci = <&dmsc>;
- ti,sci-dev-id = <3>;
- ti,interrupt-ranges = <0 32 16>;
- };
-
- main_gpio0: gpio@600000 {
- compatible = "ti,am64-gpio", "ti,keystone-gpio";
- reg = <0x0 0x00600000 0x0 0x100>;
- gpio-controller;
- #gpio-cells = <2>;
- interrupt-parent = <&main_gpio_intr>;
- interrupts = <190>, <191>, <192>,
- <193>, <194>, <195>;
- interrupt-controller;
- #interrupt-cells = <2>;
- ti,ngpio = <87>;
- ti,davinci-gpio-unbanked = <0>;
- power-domains = <&k3_pds 77 TI_SCI_PD_EXCLUSIVE>;
- clocks = <&k3_clks 77 0>;
- clock-names = "gpio";
- };
-
- main_gpio1: gpio@601000 {
- compatible = "ti,am64-gpio", "ti,keystone-gpio";
- reg = <0x0 0x00601000 0x0 0x100>;
- gpio-controller;
- #gpio-cells = <2>;
- interrupt-parent = <&main_gpio_intr>;
- interrupts = <180>, <181>, <182>,
- <183>, <184>, <185>;
- interrupt-controller;
- #interrupt-cells = <2>;
- ti,ngpio = <88>;
- ti,davinci-gpio-unbanked = <0>;
- power-domains = <&k3_pds 78 TI_SCI_PD_EXCLUSIVE>;
- clocks = <&k3_clks 78 0>;
- clock-names = "gpio";
- };
-
- sdhci0: mmc@fa10000 {
- compatible = "ti,am64-sdhci-8bit";
- reg = <0x00 0xfa10000 0x00 0x260>, <0x00 0xfa18000 0x00 0x134>;
- interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>;
- power-domains = <&k3_pds 57 TI_SCI_PD_EXCLUSIVE>;
- clocks = <&k3_clks 57 0>, <&k3_clks 57 1>;
- clock-names = "clk_ahb", "clk_xin";
- mmc-ddr-1_8v;
- mmc-hs200-1_8v;
- ti,trm-icp = <0x2>;
- ti,otap-del-sel-legacy = <0x0>;
- ti,otap-del-sel-mmc-hs = <0x0>;
- ti,otap-del-sel-ddr52 = <0x6>;
- ti,otap-del-sel-hs200 = <0x7>;
- };
-
- sdhci1: mmc@fa00000 {
- compatible = "ti,am64-sdhci-4bit";
- reg = <0x00 0xfa00000 0x00 0x260>, <0x00 0xfa08000 0x00 0x134>;
- interrupts = <GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>;
- power-domains = <&k3_pds 58 TI_SCI_PD_EXCLUSIVE>;
- clocks = <&k3_clks 58 3>, <&k3_clks 58 4>;
- clock-names = "clk_ahb", "clk_xin";
- ti,trm-icp = <0x2>;
- ti,otap-del-sel-legacy = <0x0>;
- ti,otap-del-sel-sd-hs = <0xf>;
- ti,otap-del-sel-sdr12 = <0xf>;
- ti,otap-del-sel-sdr25 = <0xf>;
- ti,otap-del-sel-sdr50 = <0xc>;
- ti,otap-del-sel-sdr104 = <0x6>;
- ti,otap-del-sel-ddr50 = <0x9>;
- ti,clkbuf-sel = <0x7>;
- };
-
- cpsw3g: ethernet@8000000 {
- compatible = "ti,am642-cpsw-nuss";
- #address-cells = <2>;
- #size-cells = <2>;
- reg = <0x0 0x8000000 0x0 0x200000>;
- reg-names = "cpsw_nuss";
- ranges = <0x0 0x0 0x0 0x8000000 0x0 0x200000>;
- clocks = <&k3_clks 13 0>;
- assigned-clocks = <&k3_clks 13 1>;
- assigned-clock-parents = <&k3_clks 13 9>;
- clock-names = "fck";
- power-domains = <&k3_pds 13 TI_SCI_PD_EXCLUSIVE>;
-
- dmas = <&main_pktdma 0xC500 15>,
- <&main_pktdma 0xC501 15>,
- <&main_pktdma 0xC502 15>,
- <&main_pktdma 0xC503 15>,
- <&main_pktdma 0xC504 15>,
- <&main_pktdma 0xC505 15>,
- <&main_pktdma 0xC506 15>,
- <&main_pktdma 0xC507 15>,
- <&main_pktdma 0x4500 15>;
- dma-names = "tx0", "tx1", "tx2", "tx3", "tx4", "tx5", "tx6",
- "tx7", "rx";
-
- ethernet-ports {
- #address-cells = <1>;
- #size-cells = <0>;
-
- cpsw_port1: port@1 {
- reg = <1>;
- ti,mac-only;
- label = "port1";
- phys = <&phy_gmii_sel 1>;
- mac-address = [00 00 00 00 00 00];
- ti,syscon-efuse = <&main_conf 0x200>;
- };
-
- cpsw_port2: port@2 {
- reg = <2>;
- ti,mac-only;
- label = "port2";
- phys = <&phy_gmii_sel 2>;
- mac-address = [00 00 00 00 00 00];
- };
- };
-
- cpsw3g_mdio: mdio@f00 {
- compatible = "ti,cpsw-mdio","ti,davinci_mdio";
- reg = <0x0 0xf00 0x0 0x100>;
- #address-cells = <1>;
- #size-cells = <0>;
- clocks = <&k3_clks 13 0>;
- clock-names = "fck";
- bus_freq = <1000000>;
- status = "disabled";
- };
-
- cpts@3d000 {
- compatible = "ti,j721e-cpts";
- reg = <0x0 0x3d000 0x0 0x400>;
- clocks = <&k3_clks 13 1>;
- clock-names = "cpts";
- interrupts-extended = <&gic500 GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>;
- interrupt-names = "cpts";
- ti,cpts-ext-ts-inputs = <4>;
- ti,cpts-periodic-outputs = <2>;
- };
- };
-
- main_cpts0: cpts@39000000 {
- compatible = "ti,j721e-cpts";
- reg = <0x0 0x39000000 0x0 0x400>;
- reg-names = "cpts";
- power-domains = <&k3_pds 84 TI_SCI_PD_EXCLUSIVE>;
- clocks = <&k3_clks 84 0>;
- clock-names = "cpts";
- assigned-clocks = <&k3_clks 84 0>;
- assigned-clock-parents = <&k3_clks 84 8>;
- interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>;
- interrupt-names = "cpts";
- ti,cpts-periodic-outputs = <6>;
- ti,cpts-ext-ts-inputs = <8>;
- };
-
- timesync_router: pinctrl@a40000 {
- compatible = "pinctrl-single";
- reg = <0x0 0xa40000 0x0 0x800>;
- #pinctrl-cells = <1>;
- pinctrl-single,register-width = <32>;
- pinctrl-single,function-mask = <0x000107ff>;
- };
-
- usbss0: cdns-usb@f900000 {
- compatible = "ti,am64-usb";
- reg = <0x00 0xf900000 0x00 0x100>;
- power-domains = <&k3_pds 161 TI_SCI_PD_EXCLUSIVE>;
- clocks = <&k3_clks 161 9>, <&k3_clks 161 1>;
- clock-names = "ref", "lpm";
- assigned-clocks = <&k3_clks 161 9>; /* USB2_REFCLK */
- assigned-clock-parents = <&k3_clks 161 10>; /* HF0SC0 */
- #address-cells = <2>;
- #size-cells = <2>;
- ranges;
- usb0: usb@f400000 {
- compatible = "cdns,usb3";
- reg = <0x00 0xf400000 0x00 0x10000>,
- <0x00 0xf410000 0x00 0x10000>,
- <0x00 0xf420000 0x00 0x10000>;
- reg-names = "otg",
- "xhci",
- "dev";
- interrupts = <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>, /* irq.0 */
- <GIC_SPI 194 IRQ_TYPE_LEVEL_HIGH>, /* irq.6 */
- <GIC_SPI 196 IRQ_TYPE_LEVEL_HIGH>; /* otgirq */
- interrupt-names = "host",
- "peripheral",
- "otg";
- maximum-speed = "super-speed";
- dr_mode = "otg";
- };
- };
-
- tscadc0: tscadc@28001000 {
- compatible = "ti,am654-tscadc", "ti,am3359-tscadc";
- reg = <0x00 0x28001000 0x00 0x1000>;
- interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
- power-domains = <&k3_pds 0 TI_SCI_PD_EXCLUSIVE>;
- clocks = <&k3_clks 0 0>;
- assigned-clocks = <&k3_clks 0 0>;
- assigned-clock-parents = <&k3_clks 0 3>;
- assigned-clock-rates = <60000000>;
- clock-names = "fck";
- status = "disabled";
-
- adc {
- #io-channel-cells = <1>;
- compatible = "ti,am654-adc", "ti,am3359-adc";
- };
- };
-
- fss: bus@fc00000 {
- compatible = "simple-bus";
- reg = <0x00 0x0fc00000 0x00 0x70000>;
- #address-cells = <2>;
- #size-cells = <2>;
- ranges;
-
- ospi0: spi@fc40000 {
- compatible = "ti,am654-ospi", "cdns,qspi-nor";
- reg = <0x00 0x0fc40000 0x00 0x100>,
- <0x05 0x00000000 0x01 0x00000000>;
- interrupts = <GIC_SPI 139 IRQ_TYPE_LEVEL_HIGH>;
- cdns,fifo-depth = <256>;
- cdns,fifo-width = <4>;
- cdns,trigger-address = <0x0>;
- #address-cells = <0x1>;
- #size-cells = <0x0>;
- clocks = <&k3_clks 75 6>;
- assigned-clocks = <&k3_clks 75 6>;
- assigned-clock-parents = <&k3_clks 75 7>;
- assigned-clock-rates = <166666666>;
- power-domains = <&k3_pds 75 TI_SCI_PD_EXCLUSIVE>;
- status = "disabled";
- };
- };
-
- hwspinlock: spinlock@2a000000 {
- compatible = "ti,am64-hwspinlock";
- reg = <0x00 0x2a000000 0x00 0x1000>;
- #hwlock-cells = <1>;
- };
-
- mailbox0_cluster2: mailbox@29020000 {
- compatible = "ti,am64-mailbox";
- reg = <0x00 0x29020000 0x00 0x200>;
- interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>;
- #mbox-cells = <1>;
- ti,mbox-num-users = <4>;
- ti,mbox-num-fifos = <16>;
- status = "disabled";
- };
-
- mailbox0_cluster3: mailbox@29030000 {
- compatible = "ti,am64-mailbox";
- reg = <0x00 0x29030000 0x00 0x200>;
- interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
- #mbox-cells = <1>;
- ti,mbox-num-users = <4>;
- ti,mbox-num-fifos = <16>;
- status = "disabled";
- };
-
- mailbox0_cluster4: mailbox@29040000 {
- compatible = "ti,am64-mailbox";
- reg = <0x00 0x29040000 0x00 0x200>;
- interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
- #mbox-cells = <1>;
- ti,mbox-num-users = <4>;
- ti,mbox-num-fifos = <16>;
- status = "disabled";
- };
-
- mailbox0_cluster5: mailbox@29050000 {
- compatible = "ti,am64-mailbox";
- reg = <0x00 0x29050000 0x00 0x200>;
- interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>;
- #mbox-cells = <1>;
- ti,mbox-num-users = <4>;
- ti,mbox-num-fifos = <16>;
- status = "disabled";
- };
-
- mailbox0_cluster6: mailbox@29060000 {
- compatible = "ti,am64-mailbox";
- reg = <0x00 0x29060000 0x00 0x200>;
- interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>;
- #mbox-cells = <1>;
- ti,mbox-num-users = <4>;
- ti,mbox-num-fifos = <16>;
- status = "disabled";
- };
-
- mailbox0_cluster7: mailbox@29070000 {
- compatible = "ti,am64-mailbox";
- reg = <0x00 0x29070000 0x00 0x200>;
- interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>;
- #mbox-cells = <1>;
- ti,mbox-num-users = <4>;
- ti,mbox-num-fifos = <16>;
- status = "disabled";
- };
-
- main_r5fss0: r5fss@78000000 {
- compatible = "ti,am64-r5fss";
- ti,cluster-mode = <0>;
- #address-cells = <1>;
- #size-cells = <1>;
- ranges = <0x78000000 0x00 0x78000000 0x10000>,
- <0x78100000 0x00 0x78100000 0x10000>,
- <0x78200000 0x00 0x78200000 0x08000>,
- <0x78300000 0x00 0x78300000 0x08000>;
- power-domains = <&k3_pds 119 TI_SCI_PD_EXCLUSIVE>;
-
- main_r5fss0_core0: r5f@78000000 {
- compatible = "ti,am64-r5f";
- reg = <0x78000000 0x00010000>,
- <0x78100000 0x00010000>;
- reg-names = "atcm", "btcm";
- ti,sci = <&dmsc>;
- ti,sci-dev-id = <121>;
- ti,sci-proc-ids = <0x01 0xff>;
- resets = <&k3_reset 121 1>;
- firmware-name = "am64-main-r5f0_0-fw";
- ti,atcm-enable = <1>;
- ti,btcm-enable = <1>;
- ti,loczrama = <1>;
- };
-
- main_r5fss0_core1: r5f@78200000 {
- compatible = "ti,am64-r5f";
- reg = <0x78200000 0x00008000>,
- <0x78300000 0x00008000>;
- reg-names = "atcm", "btcm";
- ti,sci = <&dmsc>;
- ti,sci-dev-id = <122>;
- ti,sci-proc-ids = <0x02 0xff>;
- resets = <&k3_reset 122 1>;
- firmware-name = "am64-main-r5f0_1-fw";
- ti,atcm-enable = <1>;
- ti,btcm-enable = <1>;
- ti,loczrama = <1>;
- };
- };
-
- main_r5fss1: r5fss@78400000 {
- compatible = "ti,am64-r5fss";
- ti,cluster-mode = <0>;
- #address-cells = <1>;
- #size-cells = <1>;
- ranges = <0x78400000 0x00 0x78400000 0x10000>,
- <0x78500000 0x00 0x78500000 0x10000>,
- <0x78600000 0x00 0x78600000 0x08000>,
- <0x78700000 0x00 0x78700000 0x08000>;
- power-domains = <&k3_pds 120 TI_SCI_PD_EXCLUSIVE>;
-
- main_r5fss1_core0: r5f@78400000 {
- compatible = "ti,am64-r5f";
- reg = <0x78400000 0x00010000>,
- <0x78500000 0x00010000>;
- reg-names = "atcm", "btcm";
- ti,sci = <&dmsc>;
- ti,sci-dev-id = <123>;
- ti,sci-proc-ids = <0x06 0xff>;
- resets = <&k3_reset 123 1>;
- firmware-name = "am64-main-r5f1_0-fw";
- ti,atcm-enable = <1>;
- ti,btcm-enable = <1>;
- ti,loczrama = <1>;
- };
-
- main_r5fss1_core1: r5f@78600000 {
- compatible = "ti,am64-r5f";
- reg = <0x78600000 0x00008000>,
- <0x78700000 0x00008000>;
- reg-names = "atcm", "btcm";
- ti,sci = <&dmsc>;
- ti,sci-dev-id = <124>;
- ti,sci-proc-ids = <0x07 0xff>;
- resets = <&k3_reset 124 1>;
- firmware-name = "am64-main-r5f1_1-fw";
- ti,atcm-enable = <1>;
- ti,btcm-enable = <1>;
- ti,loczrama = <1>;
- };
- };
-
- serdes_wiz0: wiz@f000000 {
- compatible = "ti,am64-wiz-10g";
- #address-cells = <1>;
- #size-cells = <1>;
- power-domains = <&k3_pds 162 TI_SCI_PD_EXCLUSIVE>;
- clocks = <&k3_clks 162 0>, <&k3_clks 162 1>, <&serdes_refclk>;
- clock-names = "fck", "core_ref_clk", "ext_ref_clk";
- num-lanes = <1>;
- #reset-cells = <1>;
- #clock-cells = <1>;
- ranges = <0x0f000000 0x0 0x0f000000 0x00010000>;
-
- assigned-clocks = <&k3_clks 162 1>;
- assigned-clock-parents = <&k3_clks 162 5>;
-
- serdes0: serdes@f000000 {
- compatible = "ti,j721e-serdes-10g";
- reg = <0x0f000000 0x00010000>;
- reg-names = "torrent_phy";
- resets = <&serdes_wiz0 0>;
- reset-names = "torrent_reset";
- clocks = <&serdes_wiz0 TI_WIZ_PLL0_REFCLK>,
- <&serdes_wiz0 TI_WIZ_PHY_EN_REFCLK>;
- clock-names = "refclk", "phy_en_refclk";
- assigned-clocks = <&serdes_wiz0 TI_WIZ_PLL0_REFCLK>,
- <&serdes_wiz0 TI_WIZ_PLL1_REFCLK>,
- <&serdes_wiz0 TI_WIZ_REFCLK_DIG>;
- assigned-clock-parents = <&k3_clks 162 1>,
- <&k3_clks 162 1>,
- <&k3_clks 162 1>;
- #address-cells = <1>;
- #size-cells = <0>;
- #clock-cells = <1>;
- };
- };
-
- pcie0_rc: pcie@f102000 {
- compatible = "ti,am64-pcie-host", "ti,j721e-pcie-host";
- reg = <0x00 0x0f102000 0x00 0x1000>,
- <0x00 0x0f100000 0x00 0x400>,
- <0x00 0x0d000000 0x00 0x00800000>,
- <0x00 0x68000000 0x00 0x00001000>;
- reg-names = "intd_cfg", "user_cfg", "reg", "cfg";
- interrupt-names = "link_state";
- interrupts = <GIC_SPI 203 IRQ_TYPE_EDGE_RISING>;
- device_type = "pci";
- ti,syscon-pcie-ctrl = <&main_conf 0x4070>;
- max-link-speed = <2>;
- num-lanes = <1>;
- power-domains = <&k3_pds 114 TI_SCI_PD_EXCLUSIVE>;
- clocks = <&k3_clks 114 0>, <&serdes0 CDNS_TORRENT_REFCLK_DRIVER>;
- clock-names = "fck", "pcie_refclk";
- #address-cells = <3>;
- #size-cells = <2>;
- bus-range = <0x0 0xff>;
- cdns,no-bar-match-nbits = <64>;
- vendor-id = <0x104c>;
- device-id = <0xb010>;
- msi-map = <0x0 &gic_its 0x0 0x10000>;
- ranges = <0x01000000 0x00 0x68001000 0x00 0x68001000 0x00 0x0010000>,
- <0x02000000 0x00 0x68011000 0x00 0x68011000 0x00 0x7fef000>;
- dma-ranges = <0x02000000 0x0 0x0 0x0 0x0 0x00000010 0x0>;
- status = "disabled";
- };
-
- pcie0_ep: pcie-ep@f102000 {
- compatible = "ti,am64-pcie-ep", "ti,j721e-pcie-ep";
- reg = <0x00 0x0f102000 0x00 0x1000>,
- <0x00 0x0f100000 0x00 0x400>,
- <0x00 0x0d000000 0x00 0x00800000>,
- <0x00 0x68000000 0x00 0x08000000>;
- reg-names = "intd_cfg", "user_cfg", "reg", "mem";
- interrupt-names = "link_state";
- interrupts = <GIC_SPI 203 IRQ_TYPE_EDGE_RISING>;
- ti,syscon-pcie-ctrl = <&main_conf 0x4070>;
- max-link-speed = <2>;
- num-lanes = <1>;
- power-domains = <&k3_pds 114 TI_SCI_PD_EXCLUSIVE>;
- clocks = <&k3_clks 114 0>;
- clock-names = "fck";
- max-functions = /bits/ 8 <1>;
- status = "disabled";
- };
-
- epwm0: pwm@23000000 {
- compatible = "ti,am64-epwm", "ti,am3352-ehrpwm";
- #pwm-cells = <3>;
- reg = <0x0 0x23000000 0x0 0x100>;
- power-domains = <&k3_pds 86 TI_SCI_PD_EXCLUSIVE>;
- clocks = <&epwm_tbclk 0>, <&k3_clks 86 0>;
- clock-names = "tbclk", "fck";
- status = "disabled";
- };
-
- epwm1: pwm@23010000 {
- compatible = "ti,am64-epwm", "ti,am3352-ehrpwm";
- #pwm-cells = <3>;
- reg = <0x0 0x23010000 0x0 0x100>;
- power-domains = <&k3_pds 87 TI_SCI_PD_EXCLUSIVE>;
- clocks = <&epwm_tbclk 1>, <&k3_clks 87 0>;
- clock-names = "tbclk", "fck";
- status = "disabled";
- };
-
- epwm2: pwm@23020000 {
- compatible = "ti,am64-epwm", "ti,am3352-ehrpwm";
- #pwm-cells = <3>;
- reg = <0x0 0x23020000 0x0 0x100>;
- power-domains = <&k3_pds 88 TI_SCI_PD_EXCLUSIVE>;
- clocks = <&epwm_tbclk 2>, <&k3_clks 88 0>;
- clock-names = "tbclk", "fck";
- status = "disabled";
- };
-
- epwm3: pwm@23030000 {
- compatible = "ti,am64-epwm", "ti,am3352-ehrpwm";
- #pwm-cells = <3>;
- reg = <0x0 0x23030000 0x0 0x100>;
- power-domains = <&k3_pds 89 TI_SCI_PD_EXCLUSIVE>;
- clocks = <&epwm_tbclk 3>, <&k3_clks 89 0>;
- clock-names = "tbclk", "fck";
- status = "disabled";
- };
-
- epwm4: pwm@23040000 {
- compatible = "ti,am64-epwm", "ti,am3352-ehrpwm";
- #pwm-cells = <3>;
- reg = <0x0 0x23040000 0x0 0x100>;
- power-domains = <&k3_pds 90 TI_SCI_PD_EXCLUSIVE>;
- clocks = <&epwm_tbclk 4>, <&k3_clks 90 0>;
- clock-names = "tbclk", "fck";
- status = "disabled";
- };
-
- epwm5: pwm@23050000 {
- compatible = "ti,am64-epwm", "ti,am3352-ehrpwm";
- #pwm-cells = <3>;
- reg = <0x0 0x23050000 0x0 0x100>;
- power-domains = <&k3_pds 91 TI_SCI_PD_EXCLUSIVE>;
- clocks = <&epwm_tbclk 5>, <&k3_clks 91 0>;
- clock-names = "tbclk", "fck";
- status = "disabled";
- };
-
- epwm6: pwm@23060000 {
- compatible = "ti,am64-epwm", "ti,am3352-ehrpwm";
- #pwm-cells = <3>;
- reg = <0x0 0x23060000 0x0 0x100>;
- power-domains = <&k3_pds 92 TI_SCI_PD_EXCLUSIVE>;
- clocks = <&epwm_tbclk 6>, <&k3_clks 92 0>;
- clock-names = "tbclk", "fck";
- status = "disabled";
- };
-
- epwm7: pwm@23070000 {
- compatible = "ti,am64-epwm", "ti,am3352-ehrpwm";
- #pwm-cells = <3>;
- reg = <0x0 0x23070000 0x0 0x100>;
- power-domains = <&k3_pds 93 TI_SCI_PD_EXCLUSIVE>;
- clocks = <&epwm_tbclk 7>, <&k3_clks 93 0>;
- clock-names = "tbclk", "fck";
- status = "disabled";
- };
-
- epwm8: pwm@23080000 {
- compatible = "ti,am64-epwm", "ti,am3352-ehrpwm";
- #pwm-cells = <3>;
- reg = <0x0 0x23080000 0x0 0x100>;
- power-domains = <&k3_pds 94 TI_SCI_PD_EXCLUSIVE>;
- clocks = <&epwm_tbclk 8>, <&k3_clks 94 0>;
- clock-names = "tbclk", "fck";
- status = "disabled";
- };
-
- ecap0: pwm@23100000 {
- compatible = "ti,am64-ecap", "ti,am3352-ecap";
- #pwm-cells = <3>;
- reg = <0x0 0x23100000 0x0 0x60>;
- power-domains = <&k3_pds 51 TI_SCI_PD_EXCLUSIVE>;
- clocks = <&k3_clks 51 0>;
- clock-names = "fck";
- status = "disabled";
- };
-
- ecap1: pwm@23110000 {
- compatible = "ti,am64-ecap", "ti,am3352-ecap";
- #pwm-cells = <3>;
- reg = <0x0 0x23110000 0x0 0x60>;
- power-domains = <&k3_pds 52 TI_SCI_PD_EXCLUSIVE>;
- clocks = <&k3_clks 52 0>;
- clock-names = "fck";
- status = "disabled";
- };
-
- ecap2: pwm@23120000 {
- compatible = "ti,am64-ecap", "ti,am3352-ecap";
- #pwm-cells = <3>;
- reg = <0x0 0x23120000 0x0 0x60>;
- power-domains = <&k3_pds 53 TI_SCI_PD_EXCLUSIVE>;
- clocks = <&k3_clks 53 0>;
- clock-names = "fck";
- status = "disabled";
- };
-
- main_rti0: watchdog@e000000 {
- compatible = "ti,j7-rti-wdt";
- reg = <0x00 0xe000000 0x00 0x100>;
- clocks = <&k3_clks 125 0>;
- power-domains = <&k3_pds 125 TI_SCI_PD_EXCLUSIVE>;
- assigned-clocks = <&k3_clks 125 0>;
- assigned-clock-parents = <&k3_clks 125 2>;
- };
-
- main_rti1: watchdog@e010000 {
- compatible = "ti,j7-rti-wdt";
- reg = <0x00 0xe010000 0x00 0x100>;
- clocks = <&k3_clks 126 0>;
- power-domains = <&k3_pds 126 TI_SCI_PD_EXCLUSIVE>;
- assigned-clocks = <&k3_clks 126 0>;
- assigned-clock-parents = <&k3_clks 126 2>;
- };
-
- icssg0: icssg@30000000 {
- compatible = "ti,am642-icssg";
- reg = <0x00 0x30000000 0x00 0x80000>;
- power-domains = <&k3_pds 81 TI_SCI_PD_EXCLUSIVE>;
- #address-cells = <1>;
- #size-cells = <1>;
- ranges = <0x0 0x00 0x30000000 0x80000>;
-
- icssg0_mem: memories@0 {
- reg = <0x0 0x2000>,
- <0x2000 0x2000>,
- <0x10000 0x10000>;
- reg-names = "dram0", "dram1", "shrdram2";
- };
-
- icssg0_cfg: cfg@26000 {
- compatible = "ti,pruss-cfg", "syscon";
- reg = <0x26000 0x200>;
- #address-cells = <1>;
- #size-cells = <1>;
- ranges = <0x0 0x26000 0x2000>;
-
- clocks {
- #address-cells = <1>;
- #size-cells = <0>;
-
- icssg0_coreclk_mux: coreclk-mux@3c {
- reg = <0x3c>;
- #clock-cells = <0>;
- clocks = <&k3_clks 81 0>, /* icssg0_core_clk */
- <&k3_clks 81 20>; /* icssg0_iclk */
- assigned-clocks = <&icssg0_coreclk_mux>;
- assigned-clock-parents = <&k3_clks 81 20>;
- };
-
- icssg0_iepclk_mux: iepclk-mux@30 {
- reg = <0x30>;
- #clock-cells = <0>;
- clocks = <&k3_clks 81 3>, /* icssg0_iep_clk */
- <&icssg0_coreclk_mux>; /* icssg0_coreclk_mux */
- assigned-clocks = <&icssg0_iepclk_mux>;
- assigned-clock-parents = <&icssg0_coreclk_mux>;
- };
- };
- };
-
- icssg0_mii_rt: mii-rt@32000 {
- compatible = "ti,pruss-mii", "syscon";
- reg = <0x32000 0x100>;
- };
-
- icssg0_mii_g_rt: mii-g-rt@33000 {
- compatible = "ti,pruss-mii-g", "syscon";
- reg = <0x33000 0x1000>;
- };
-
- icssg0_intc: interrupt-controller@20000 {
- compatible = "ti,icssg-intc";
- reg = <0x20000 0x2000>;
- interrupt-controller;
- #interrupt-cells = <3>;
- interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>;
- interrupt-names = "host_intr0", "host_intr1",
- "host_intr2", "host_intr3",
- "host_intr4", "host_intr5",
- "host_intr6", "host_intr7";
- };
-
- pru0_0: pru@34000 {
- compatible = "ti,am642-pru";
- reg = <0x34000 0x3000>,
- <0x22000 0x100>,
- <0x22400 0x100>;
- reg-names = "iram", "control", "debug";
- firmware-name = "am64x-pru0_0-fw";
- };
-
- rtu0_0: rtu@4000 {
- compatible = "ti,am642-rtu";
- reg = <0x4000 0x2000>,
- <0x23000 0x100>,
- <0x23400 0x100>;
- reg-names = "iram", "control", "debug";
- firmware-name = "am64x-rtu0_0-fw";
- };
-
- tx_pru0_0: txpru@a000 {
- compatible = "ti,am642-tx-pru";
- reg = <0xa000 0x1800>,
- <0x25000 0x100>,
- <0x25400 0x100>;
- reg-names = "iram", "control", "debug";
- firmware-name = "am64x-txpru0_0-fw";
- };
-
- pru0_1: pru@38000 {
- compatible = "ti,am642-pru";
- reg = <0x38000 0x3000>,
- <0x24000 0x100>,
- <0x24400 0x100>;
- reg-names = "iram", "control", "debug";
- firmware-name = "am64x-pru0_1-fw";
- };
-
- rtu0_1: rtu@6000 {
- compatible = "ti,am642-rtu";
- reg = <0x6000 0x2000>,
- <0x23800 0x100>,
- <0x23c00 0x100>;
- reg-names = "iram", "control", "debug";
- firmware-name = "am64x-rtu0_1-fw";
- };
-
- tx_pru0_1: txpru@c000 {
- compatible = "ti,am642-tx-pru";
- reg = <0xc000 0x1800>,
- <0x25800 0x100>,
- <0x25c00 0x100>;
- reg-names = "iram", "control", "debug";
- firmware-name = "am64x-txpru0_1-fw";
- };
-
- icssg0_mdio: mdio@32400 {
- compatible = "ti,davinci_mdio";
- reg = <0x32400 0x100>;
- clocks = <&k3_clks 62 3>;
- clock-names = "fck";
- #address-cells = <1>;
- #size-cells = <0>;
- bus_freq = <1000000>;
- status = "disabled";
- };
- };
-
- icssg1: icssg@30080000 {
- compatible = "ti,am642-icssg";
- reg = <0x00 0x30080000 0x00 0x80000>;
- power-domains = <&k3_pds 82 TI_SCI_PD_EXCLUSIVE>;
- #address-cells = <1>;
- #size-cells = <1>;
- ranges = <0x0 0x00 0x30080000 0x80000>;
-
- icssg1_mem: memories@0 {
- reg = <0x0 0x2000>,
- <0x2000 0x2000>,
- <0x10000 0x10000>;
- reg-names = "dram0", "dram1", "shrdram2";
- };
-
- icssg1_cfg: cfg@26000 {
- compatible = "ti,pruss-cfg", "syscon";
- reg = <0x26000 0x200>;
- #address-cells = <1>;
- #size-cells = <1>;
- ranges = <0x0 0x26000 0x2000>;
-
- clocks {
- #address-cells = <1>;
- #size-cells = <0>;
-
- icssg1_coreclk_mux: coreclk-mux@3c {
- reg = <0x3c>;
- #clock-cells = <0>;
- clocks = <&k3_clks 82 0>, /* icssg1_core_clk */
- <&k3_clks 82 20>; /* icssg1_iclk */
- assigned-clocks = <&icssg1_coreclk_mux>;
- assigned-clock-parents = <&k3_clks 82 20>;
- };
-
- icssg1_iepclk_mux: iepclk-mux@30 {
- reg = <0x30>;
- #clock-cells = <0>;
- clocks = <&k3_clks 82 3>, /* icssg1_iep_clk */
- <&icssg1_coreclk_mux>; /* icssg1_coreclk_mux */
- assigned-clocks = <&icssg1_iepclk_mux>;
- assigned-clock-parents = <&icssg1_coreclk_mux>;
- };
- };
- };
-
- icssg1_mii_rt: mii-rt@32000 {
- compatible = "ti,pruss-mii", "syscon";
- reg = <0x32000 0x100>;
- };
-
- icssg1_mii_g_rt: mii-g-rt@33000 {
- compatible = "ti,pruss-mii-g", "syscon";
- reg = <0x33000 0x1000>;
- };
-
- icssg1_intc: interrupt-controller@20000 {
- compatible = "ti,icssg-intc";
- reg = <0x20000 0x2000>;
- interrupt-controller;
- #interrupt-cells = <3>;
- interrupts = <GIC_SPI 216 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 217 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 218 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 219 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 220 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 221 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 222 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 223 IRQ_TYPE_LEVEL_HIGH>;
- interrupt-names = "host_intr0", "host_intr1",
- "host_intr2", "host_intr3",
- "host_intr4", "host_intr5",
- "host_intr6", "host_intr7";
- };
-
- pru1_0: pru@34000 {
- compatible = "ti,am642-pru";
- reg = <0x34000 0x4000>,
- <0x22000 0x100>,
- <0x22400 0x100>;
- reg-names = "iram", "control", "debug";
- firmware-name = "am64x-pru1_0-fw";
- };
-
- rtu1_0: rtu@4000 {
- compatible = "ti,am642-rtu";
- reg = <0x4000 0x2000>,
- <0x23000 0x100>,
- <0x23400 0x100>;
- reg-names = "iram", "control", "debug";
- firmware-name = "am64x-rtu1_0-fw";
- };
-
- tx_pru1_0: txpru@a000 {
- compatible = "ti,am642-tx-pru";
- reg = <0xa000 0x1800>,
- <0x25000 0x100>,
- <0x25400 0x100>;
- reg-names = "iram", "control", "debug";
- firmware-name = "am64x-txpru1_0-fw";
- };
-
- pru1_1: pru@38000 {
- compatible = "ti,am642-pru";
- reg = <0x38000 0x4000>,
- <0x24000 0x100>,
- <0x24400 0x100>;
- reg-names = "iram", "control", "debug";
- firmware-name = "am64x-pru1_1-fw";
- };
-
- rtu1_1: rtu@6000 {
- compatible = "ti,am642-rtu";
- reg = <0x6000 0x2000>,
- <0x23800 0x100>,
- <0x23c00 0x100>;
- reg-names = "iram", "control", "debug";
- firmware-name = "am64x-rtu1_1-fw";
- };
-
- tx_pru1_1: txpru@c000 {
- compatible = "ti,am642-tx-pru";
- reg = <0xc000 0x1800>,
- <0x25800 0x100>,
- <0x25c00 0x100>;
- reg-names = "iram", "control", "debug";
- firmware-name = "am64x-txpru1_1-fw";
- };
-
- icssg1_mdio: mdio@32400 {
- compatible = "ti,davinci_mdio";
- reg = <0x32400 0x100>;
- #address-cells = <1>;
- #size-cells = <0>;
- clocks = <&k3_clks 82 0>;
- clock-names = "fck";
- bus_freq = <1000000>;
- status = "disabled";
- };
- };
-
- main_mcan0: can@20701000 {
- compatible = "bosch,m_can";
- reg = <0x00 0x20701000 0x00 0x200>,
- <0x00 0x20708000 0x00 0x8000>;
- reg-names = "m_can", "message_ram";
- power-domains = <&k3_pds 98 TI_SCI_PD_EXCLUSIVE>;
- clocks = <&k3_clks 98 5>, <&k3_clks 98 0>;
- clock-names = "hclk", "cclk";
- interrupts = <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 156 IRQ_TYPE_LEVEL_HIGH>;
- interrupt-names = "int0", "int1";
- bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>;
- status = "disabled";
- };
-
- main_mcan1: can@20711000 {
- compatible = "bosch,m_can";
- reg = <0x00 0x20711000 0x00 0x200>,
- <0x00 0x20718000 0x00 0x8000>;
- reg-names = "m_can", "message_ram";
- power-domains = <&k3_pds 99 TI_SCI_PD_EXCLUSIVE>;
- clocks = <&k3_clks 99 5>, <&k3_clks 99 0>;
- clock-names = "hclk", "cclk";
- interrupts = <GIC_SPI 158 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 159 IRQ_TYPE_LEVEL_HIGH>;
- interrupt-names = "int0", "int1";
- bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>;
- status = "disabled";
- };
-
- crypto: crypto@40900000 {
- compatible = "ti,am64-sa2ul";
- reg = <0x00 0x40900000 0x00 0x1200>;
- power-domains = <&k3_pds 133 TI_SCI_PD_SHARED>;
- #address-cells = <2>;
- #size-cells = <2>;
- ranges = <0x00 0x40900000 0x00 0x40900000 0x00 0x30000>;
- dmas = <&main_pktdma 0xc001 0>, <&main_pktdma 0x4002 0>,
- <&main_pktdma 0x4003 0>;
- dma-names = "tx", "rx1", "rx2";
-
- rng: rng@40910000 {
- compatible = "inside-secure,safexcel-eip76";
- reg = <0x00 0x40910000 0x00 0x7d>;
- interrupts = <GIC_SPI 168 IRQ_TYPE_LEVEL_HIGH>;
- status = "disabled"; /* Used by OP-TEE */
- };
- };
-
- gpmc0: memory-controller@3b000000 {
- compatible = "ti,am64-gpmc";
- power-domains = <&k3_pds 80 TI_SCI_PD_EXCLUSIVE>;
- clocks = <&k3_clks 80 0>;
- clock-names = "fck";
- reg = <0x00 0x3b000000 0x00 0x400>,
- <0x00 0x50000000 0x00 0x8000000>;
- reg-names = "cfg", "data";
- interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>;
- gpmc,num-cs = <3>;
- gpmc,num-waitpins = <2>;
- #address-cells = <2>;
- #size-cells = <1>;
- interrupt-controller;
- #interrupt-cells = <2>;
- gpio-controller;
- #gpio-cells = <2>;
- status = "disabled";
- };
-
- elm0: ecc@25010000 {
- compatible = "ti,am64-elm";
- reg = <0x00 0x25010000 0x00 0x2000>;
- interrupts = <GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH>;
- power-domains = <&k3_pds 54 TI_SCI_PD_EXCLUSIVE>;
- clocks = <&k3_clks 54 0>;
- clock-names = "fck";
- status = "disabled";
- };
-
- main_vtm0: temperature-sensor@b00000 {
- compatible = "ti,j7200-vtm";
- reg = <0x00 0xb00000 0x00 0x400>,
- <0x00 0xb01000 0x00 0x400>;
- power-domains = <&k3_pds 95 TI_SCI_PD_EXCLUSIVE>;
- #thermal-sensor-cells = <1>;
- };
-};
diff --git a/arch/arm/dts/k3-am64-mcu.dtsi b/arch/arm/dts/k3-am64-mcu.dtsi
deleted file mode 100644
index 686d497..0000000
--- a/arch/arm/dts/k3-am64-mcu.dtsi
+++ /dev/null
@@ -1,161 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0
-/*
- * Device Tree Source for AM64 SoC Family MCU Domain peripherals
- *
- * Copyright (C) 2020-2021 Texas Instruments Incorporated - https://www.ti.com/
- */
-
-&cbass_mcu {
- /*
- * The MCU domain timer interrupts are routed only to the ESM module,
- * and not currently available for Linux. The MCU domain timers are
- * of limited use without interrupts, and likely reserved by the ESM.
- */
- mcu_timer0: timer@4800000 {
- compatible = "ti,am654-timer";
- reg = <0x00 0x4800000 0x00 0x400>;
- clocks = <&k3_clks 35 1>;
- clock-names = "fck";
- power-domains = <&k3_pds 35 TI_SCI_PD_EXCLUSIVE>;
- ti,timer-pwm;
- status = "reserved";
- };
-
- mcu_timer1: timer@4810000 {
- compatible = "ti,am654-timer";
- reg = <0x00 0x4810000 0x00 0x400>;
- clocks = <&k3_clks 48 1>;
- clock-names = "fck";
- power-domains = <&k3_pds 48 TI_SCI_PD_EXCLUSIVE>;
- ti,timer-pwm;
- status = "reserved";
- };
-
- mcu_timer2: timer@4820000 {
- compatible = "ti,am654-timer";
- reg = <0x00 0x4820000 0x00 0x400>;
- clocks = <&k3_clks 49 1>;
- clock-names = "fck";
- power-domains = <&k3_pds 49 TI_SCI_PD_EXCLUSIVE>;
- ti,timer-pwm;
- status = "reserved";
- };
-
- mcu_timer3: timer@4830000 {
- compatible = "ti,am654-timer";
- reg = <0x00 0x4830000 0x00 0x400>;
- clocks = <&k3_clks 50 1>;
- clock-names = "fck";
- power-domains = <&k3_pds 50 TI_SCI_PD_EXCLUSIVE>;
- ti,timer-pwm;
- status = "reserved";
- };
-
- mcu_uart0: serial@4a00000 {
- compatible = "ti,am64-uart", "ti,am654-uart";
- reg = <0x00 0x04a00000 0x00 0x100>;
- interrupts = <GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH>;
- power-domains = <&k3_pds 149 TI_SCI_PD_EXCLUSIVE>;
- clocks = <&k3_clks 149 0>;
- clock-names = "fclk";
- status = "disabled";
- };
-
- mcu_uart1: serial@4a10000 {
- compatible = "ti,am64-uart", "ti,am654-uart";
- reg = <0x00 0x04a10000 0x00 0x100>;
- interrupts = <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>;
- power-domains = <&k3_pds 160 TI_SCI_PD_EXCLUSIVE>;
- clocks = <&k3_clks 160 0>;
- clock-names = "fclk";
- status = "disabled";
- };
-
- mcu_i2c0: i2c@4900000 {
- compatible = "ti,am64-i2c", "ti,omap4-i2c";
- reg = <0x00 0x04900000 0x00 0x100>;
- interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>;
- #address-cells = <1>;
- #size-cells = <0>;
- power-domains = <&k3_pds 106 TI_SCI_PD_EXCLUSIVE>;
- clocks = <&k3_clks 106 2>;
- clock-names = "fck";
- status = "disabled";
- };
-
- mcu_i2c1: i2c@4910000 {
- compatible = "ti,am64-i2c", "ti,omap4-i2c";
- reg = <0x00 0x04910000 0x00 0x100>;
- interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>;
- #address-cells = <1>;
- #size-cells = <0>;
- power-domains = <&k3_pds 107 TI_SCI_PD_EXCLUSIVE>;
- clocks = <&k3_clks 107 2>;
- clock-names = "fck";
- status = "disabled";
- };
-
- mcu_spi0: spi@4b00000 {
- compatible = "ti,am654-mcspi", "ti,omap4-mcspi";
- reg = <0x00 0x04b00000 0x00 0x400>;
- interrupts = <GIC_SPI 176 IRQ_TYPE_LEVEL_HIGH>;
- #address-cells = <1>;
- #size-cells = <0>;
- power-domains = <&k3_pds 147 TI_SCI_PD_EXCLUSIVE>;
- clocks = <&k3_clks 147 0>;
- status = "disabled";
- };
-
- mcu_spi1: spi@4b10000 {
- compatible = "ti,am654-mcspi","ti,omap4-mcspi";
- reg = <0x00 0x04b10000 0x00 0x400>;
- interrupts = <GIC_SPI 177 IRQ_TYPE_LEVEL_HIGH>;
- #address-cells = <1>;
- #size-cells = <0>;
- power-domains = <&k3_pds 148 TI_SCI_PD_EXCLUSIVE>;
- clocks = <&k3_clks 148 0>;
- status = "disabled";
- };
-
- mcu_gpio_intr: interrupt-controller@4210000 {
- compatible = "ti,sci-intr";
- reg = <0x00 0x04210000 0x00 0x200>;
- ti,intr-trigger-type = <1>;
- interrupt-controller;
- interrupt-parent = <&gic500>;
- #interrupt-cells = <1>;
- ti,sci = <&dmsc>;
- ti,sci-dev-id = <5>;
- ti,interrupt-ranges = <0 104 4>;
- };
-
- mcu_gpio0: gpio@4201000 {
- compatible = "ti,am64-gpio", "ti,keystone-gpio";
- reg = <0x0 0x4201000 0x0 0x100>;
- gpio-controller;
- #gpio-cells = <2>;
- interrupt-parent = <&mcu_gpio_intr>;
- interrupts = <30>, <31>;
- interrupt-controller;
- #interrupt-cells = <2>;
- ti,ngpio = <23>;
- ti,davinci-gpio-unbanked = <0>;
- power-domains = <&k3_pds 79 TI_SCI_PD_EXCLUSIVE>;
- clocks = <&k3_clks 79 0>;
- clock-names = "gpio";
- };
-
- mcu_pmx0: pinctrl@4084000 {
- compatible = "pinctrl-single";
- reg = <0x00 0x4084000 0x00 0x84>;
- #pinctrl-cells = <1>;
- pinctrl-single,register-width = <32>;
- pinctrl-single,function-mask = <0xffffffff>;
- };
-
- mcu_esm: esm@4100000 {
- compatible = "ti,j721e-esm";
- reg = <0x00 0x4100000 0x00 0x1000>;
- ti,esm-pins = <0>, <1>;
- };
-};
diff --git a/arch/arm/dts/k3-am64-thermal.dtsi b/arch/arm/dts/k3-am64-thermal.dtsi
deleted file mode 100644
index 036db56..0000000
--- a/arch/arm/dts/k3-am64-thermal.dtsi
+++ /dev/null
@@ -1,33 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0
-
-#include <dt-bindings/thermal/thermal.h>
-
-thermal_zones: thermal-zones {
- main0_thermal: main0-thermal {
- polling-delay-passive = <250>; /* milliSeconds */
- polling-delay = <500>; /* milliSeconds */
- thermal-sensors = <&main_vtm0 0>;
-
- trips {
- main0_crit: main0-crit {
- temperature = <105000>; /* milliCelsius */
- hysteresis = <2000>; /* milliCelsius */
- type = "critical";
- };
- };
- };
-
- main1_thermal: main1-thermal {
- polling-delay-passive = <250>; /* milliSeconds */
- polling-delay = <500>; /* milliSeconds */
- thermal-sensors = <&main_vtm0 1>;
-
- trips {
- main1_crit: main1-crit {
- temperature = <105000>; /* milliCelsius */
- hysteresis = <2000>; /* milliCelsius */
- type = "critical";
- };
- };
- };
-};
diff --git a/arch/arm/dts/k3-am64.dtsi b/arch/arm/dts/k3-am64.dtsi
deleted file mode 100644
index 8e9c2bc..0000000
--- a/arch/arm/dts/k3-am64.dtsi
+++ /dev/null
@@ -1,100 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0
-/*
- * Device Tree Source for AM642 SoC Family
- *
- * Copyright (C) 2020-2021 Texas Instruments Incorporated - https://www.ti.com/
- */
-
-#include <dt-bindings/gpio/gpio.h>
-#include <dt-bindings/interrupt-controller/irq.h>
-#include <dt-bindings/interrupt-controller/arm-gic.h>
-#include <dt-bindings/soc/ti,sci_pm_domain.h>
-
-#include "k3-pinctrl.h"
-
-/ {
- model = "Texas Instruments K3 AM642 SoC";
- compatible = "ti,am642";
- interrupt-parent = <&gic500>;
- #address-cells = <2>;
- #size-cells = <2>;
-
- chosen { };
-
- firmware {
- optee {
- compatible = "linaro,optee-tz";
- method = "smc";
- };
-
- psci: psci {
- compatible = "arm,psci-1.0";
- method = "smc";
- };
- };
-
- a53_timer0: timer-cl0-cpu0 {
- compatible = "arm,armv8-timer";
- interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>, /* cntpsirq */
- <GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>, /* cntpnsirq */
- <GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>, /* cntvirq */
- <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>; /* cnthpirq */
- };
-
- pmu: pmu {
- compatible = "arm,cortex-a53-pmu";
- interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH>;
- };
-
- cbass_main: bus@f4000 {
- compatible = "simple-bus";
- #address-cells = <2>;
- #size-cells = <2>;
- ranges = <0x00 0x000f4000 0x00 0x000f4000 0x00 0x000002d0>, /* PINCTRL */
- <0x00 0x00420000 0x00 0x00420000 0x00 0x00001000>, /* ESM0 */
- <0x00 0x00600000 0x00 0x00600000 0x00 0x00001100>, /* GPIO */
- <0x00 0x00a40000 0x00 0x00a40000 0x00 0x00000800>, /* Timesync router */
- <0x00 0x00b00000 0x00 0x00b00000 0x00 0x00002400>, /* VTM */
- <0x00 0x01000000 0x00 0x01000000 0x00 0x02330400>, /* First peripheral window */
- <0x00 0x08000000 0x00 0x08000000 0x00 0x00200000>, /* Main CPSW */
- <0x00 0x0d000000 0x00 0x0d000000 0x00 0x00800000>, /* PCIE_CORE */
- <0x00 0x0e000000 0x00 0x0e000000 0x00 0x00000100>, /* Main RTI0 */
- <0x00 0x0e010000 0x00 0x0e010000 0x00 0x00000100>, /* Main RTI1 */
- <0x00 0x0f000000 0x00 0x0f000000 0x00 0x00c44200>, /* Second peripheral window */
- <0x00 0x20000000 0x00 0x20000000 0x00 0x0a008000>, /* Third peripheral window */
- <0x00 0x30000000 0x00 0x30000000 0x00 0x000bc100>, /* ICSSG0/1 */
- <0x00 0x37000000 0x00 0x37000000 0x00 0x00040000>, /* TIMERMGR0 TIMERS */
- <0x00 0x39000000 0x00 0x39000000 0x00 0x00000400>, /* CPTS0 */
- <0x00 0x3b000000 0x00 0x3b000000 0x00 0x00000400>, /* GPMC0_CFG */
- <0x00 0x3cd00000 0x00 0x3cd00000 0x00 0x00000200>, /* TIMERMGR0_CONFIG */
- <0x00 0x3f004000 0x00 0x3f004000 0x00 0x00000400>, /* GICSS0_REGS */
- <0x00 0x40900000 0x00 0x40900000 0x00 0x00030000>, /* SA2_UL0 */
- <0x00 0x43000000 0x00 0x43000000 0x00 0x00020000>, /* CTRL_MMR0 */
- <0x00 0x44043000 0x00 0x44043000 0x00 0x00000fe0>, /* TI SCI DEBUG */
- <0x00 0x48000000 0x00 0x48000000 0x00 0x06400000>, /* DMASS */
- <0x00 0x50000000 0x00 0x50000000 0x00 0x08000000>, /* GPMC0 DATA */
- <0x00 0x60000000 0x00 0x60000000 0x00 0x08000000>, /* FSS0 DAT1 */
- <0x00 0x68000000 0x00 0x68000000 0x00 0x08000000>, /* PCIe DAT0 */
- <0x00 0x70000000 0x00 0x70000000 0x00 0x00200000>, /* OC SRAM */
- <0x00 0x78000000 0x00 0x78000000 0x00 0x00800000>, /* Main R5FSS */
- <0x01 0x00000000 0x01 0x00000000 0x00 0x00310000>, /* A53 PERIPHBASE */
- <0x06 0x00000000 0x06 0x00000000 0x01 0x00000000>, /* PCIe DAT1 */
- <0x05 0x00000000 0x05 0x00000000 0x01 0x00000000>, /* FSS0 DAT3 */
-
- /* MCU Domain Range */
- <0x00 0x04000000 0x00 0x04000000 0x00 0x01ff1400>;
-
- cbass_mcu: bus@4000000 {
- compatible = "simple-bus";
- #address-cells = <2>;
- #size-cells = <2>;
- ranges = <0x00 0x04000000 0x00 0x04000000 0x00 0x01ff1400>; /* Peripheral window */
- };
- };
-
- #include "k3-am64-thermal.dtsi"
-};
-
-/* Now include the peripherals for each bus segments */
-#include "k3-am64-main.dtsi"
-#include "k3-am64-mcu.dtsi"
diff --git a/arch/arm/dts/k3-am642-evm-u-boot.dtsi b/arch/arm/dts/k3-am642-evm-u-boot.dtsi
index 60b219c..ee66567 100644
--- a/arch/arm/dts/k3-am642-evm-u-boot.dtsi
+++ b/arch/arm/dts/k3-am642-evm-u-boot.dtsi
@@ -9,97 +9,27 @@
chosen {
tick-timer = &main_timer0;
};
-
- memory@80000000 {
- bootph-all;
- };
-};
-
-&cbass_main {
- bootph-all;
};
&main_timer0 {
- bootph-all;
clock-frequency = <200000000>;
};
-&main_conf {
- bootph-all;
- chipid@14 {
- bootph-all;
- };
-};
-
-&main_pmx0 {
- bootph-all;
-};
-
-&main_i2c0_pins_default {
- bootph-all;
-};
-
-&main_i2c0 {
- bootph-all;
-};
-
-&main_uart0_pins_default {
- bootph-all;
-};
-
-&main_uart0 {
- bootph-all;
-};
-
-&main_usb0_pins_default {
- bootph-all;
-};
-
&usb0 {
dr_mode="peripheral";
- bootph-all;
};
-&usbss0 {
- bootph-all;
-};
-
&main_mmc1_pins_default {
bootph-all;
};
-&main_usb0_pins_default {
- bootph-all;
-};
-
-&dmss {
- bootph-all;
-};
-
-&secure_proxy_main {
- bootph-all;
-};
-
&dmsc {
- bootph-all;
k3_sysreset: sysreset-controller {
compatible = "ti,sci-sysreset";
bootph-all;
};
};
-&k3_pds {
- bootph-all;
-};
-
-&k3_clks {
- bootph-all;
-};
-
-&k3_reset {
- bootph-all;
-};
-
&sdhci0 {
bootph-all;
};
@@ -108,10 +38,6 @@
bootph-all;
};
-&sdhci1 {
- bootph-all;
-};
-
&inta_main_dmss {
bootph-all;
};
@@ -143,42 +69,6 @@
bootph-all;
};
-&mdio1_pins_default {
- bootph-all;
-};
-
-&cpsw3g_mdio {
- bootph-all;
-};
-
-&cpsw3g_phy0 {
- bootph-all;
-};
-
-&rgmii1_pins_default {
- bootph-all;
-};
-
-&rgmii2_pins_default {
- bootph-all;
-};
-
-&cpsw3g {
- bootph-all;
-
- ethernet-ports {
- bootph-all;
- };
-};
-
-&phy_gmii_sel {
- bootph-all;
-};
-
-&cpsw_port1 {
- bootph-all;
-};
-
&cpsw_port2 {
status = "disabled";
};
diff --git a/arch/arm/dts/k3-am642-evm.dts b/arch/arm/dts/k3-am642-evm.dts
deleted file mode 100644
index b4a1f73..0000000
--- a/arch/arm/dts/k3-am642-evm.dts
+++ /dev/null
@@ -1,690 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0
-/*
- * Copyright (C) 2020-2021 Texas Instruments Incorporated - https://www.ti.com/
- */
-
-/dts-v1/;
-
-#include <dt-bindings/phy/phy.h>
-#include <dt-bindings/leds/common.h>
-#include <dt-bindings/gpio/gpio.h>
-#include <dt-bindings/net/ti-dp83867.h>
-#include "k3-am642.dtsi"
-
-#include "k3-serdes.h"
-
-/ {
- compatible = "ti,am642-evm", "ti,am642";
- model = "Texas Instruments AM642 EVM";
-
- chosen {
- stdout-path = &main_uart0;
- };
-
- aliases {
- serial0 = &mcu_uart0;
- serial1 = &main_uart1;
- serial2 = &main_uart0;
- serial3 = &main_uart3;
- i2c0 = &main_i2c0;
- i2c1 = &main_i2c1;
- mmc0 = &sdhci0;
- mmc1 = &sdhci1;
- ethernet0 = &cpsw_port1;
- ethernet1 = &cpsw_port2;
- };
-
- memory@80000000 {
- device_type = "memory";
- /* 2G RAM */
- reg = <0x00000000 0x80000000 0x00000000 0x80000000>;
- };
-
- reserved-memory {
- #address-cells = <2>;
- #size-cells = <2>;
- ranges;
-
- secure_ddr: optee@9e800000 {
- reg = <0x00 0x9e800000 0x00 0x01800000>; /* for OP-TEE */
- alignment = <0x1000>;
- no-map;
- };
-
- main_r5fss0_core0_dma_memory_region: r5f-dma-memory@a0000000 {
- compatible = "shared-dma-pool";
- reg = <0x00 0xa0000000 0x00 0x100000>;
- no-map;
- };
-
- main_r5fss0_core0_memory_region: r5f-memory@a0100000 {
- compatible = "shared-dma-pool";
- reg = <0x00 0xa0100000 0x00 0xf00000>;
- no-map;
- };
-
- main_r5fss0_core1_dma_memory_region: r5f-dma-memory@a1000000 {
- compatible = "shared-dma-pool";
- reg = <0x00 0xa1000000 0x00 0x100000>;
- no-map;
- };
-
- main_r5fss0_core1_memory_region: r5f-memory@a1100000 {
- compatible = "shared-dma-pool";
- reg = <0x00 0xa1100000 0x00 0xf00000>;
- no-map;
- };
-
- main_r5fss1_core0_dma_memory_region: r5f-dma-memory@a2000000 {
- compatible = "shared-dma-pool";
- reg = <0x00 0xa2000000 0x00 0x100000>;
- no-map;
- };
-
- main_r5fss1_core0_memory_region: r5f-memory@a2100000 {
- compatible = "shared-dma-pool";
- reg = <0x00 0xa2100000 0x00 0xf00000>;
- no-map;
- };
-
- main_r5fss1_core1_dma_memory_region: r5f-dma-memory@a3000000 {
- compatible = "shared-dma-pool";
- reg = <0x00 0xa3000000 0x00 0x100000>;
- no-map;
- };
-
- main_r5fss1_core1_memory_region: r5f-memory@a3100000 {
- compatible = "shared-dma-pool";
- reg = <0x00 0xa3100000 0x00 0xf00000>;
- no-map;
- };
-
- rtos_ipc_memory_region: ipc-memories@a5000000 {
- reg = <0x00 0xa5000000 0x00 0x00800000>;
- alignment = <0x1000>;
- no-map;
- };
- };
-
- evm_12v0: regulator-0 {
- /* main DC jack */
- compatible = "regulator-fixed";
- regulator-name = "evm_12v0";
- regulator-min-microvolt = <12000000>;
- regulator-max-microvolt = <12000000>;
- regulator-always-on;
- regulator-boot-on;
- };
-
- vsys_5v0: regulator-1 {
- /* output of LM5140 */
- compatible = "regulator-fixed";
- regulator-name = "vsys_5v0";
- regulator-min-microvolt = <5000000>;
- regulator-max-microvolt = <5000000>;
- vin-supply = <&evm_12v0>;
- regulator-always-on;
- regulator-boot-on;
- };
-
- vsys_3v3: regulator-2 {
- /* output of LM5140 */
- compatible = "regulator-fixed";
- regulator-name = "vsys_3v3";
- regulator-min-microvolt = <3300000>;
- regulator-max-microvolt = <3300000>;
- vin-supply = <&evm_12v0>;
- regulator-always-on;
- regulator-boot-on;
- };
-
- vdd_mmc1: regulator-3 {
- /* TPS2051BD */
- compatible = "regulator-fixed";
- regulator-name = "vdd_mmc1";
- regulator-min-microvolt = <3300000>;
- regulator-max-microvolt = <3300000>;
- regulator-boot-on;
- enable-active-high;
- vin-supply = <&vsys_3v3>;
- gpio = <&exp1 6 GPIO_ACTIVE_HIGH>;
- };
-
- vddb: regulator-4 {
- compatible = "regulator-fixed";
- regulator-name = "vddb_3v3_display";
- regulator-min-microvolt = <3300000>;
- regulator-max-microvolt = <3300000>;
- vin-supply = <&vsys_3v3>;
- regulator-always-on;
- regulator-boot-on;
- };
-
- vtt_supply: regulator-5 {
- compatible = "regulator-fixed";
- regulator-name = "vtt";
- pinctrl-names = "default";
- pinctrl-0 = <&ddr_vtt_pins_default>;
- regulator-min-microvolt = <3300000>;
- regulator-max-microvolt = <3300000>;
- gpio = <&main_gpio0 12 GPIO_ACTIVE_HIGH>;
- vin-supply = <&vsys_3v3>;
- enable-active-high;
- regulator-always-on;
- regulator-boot-on;
- };
-
- leds {
- compatible = "gpio-leds";
-
- led-0 {
- label = "am64-evm:red:heartbeat";
- gpios = <&exp1 16 GPIO_ACTIVE_HIGH>;
- linux,default-trigger = "heartbeat";
- function = LED_FUNCTION_HEARTBEAT;
- default-state = "off";
- };
- };
-
- mdio_mux: mux-controller {
- compatible = "gpio-mux";
- #mux-control-cells = <0>;
-
- mux-gpios = <&exp1 12 GPIO_ACTIVE_HIGH>;
- };
-
- mdio-mux-1 {
- compatible = "mdio-mux-multiplexer";
- mux-controls = <&mdio_mux>;
- mdio-parent-bus = <&cpsw3g_mdio>;
- #address-cells = <1>;
- #size-cells = <0>;
-
- mdio@1 {
- reg = <0x1>;
- #address-cells = <1>;
- #size-cells = <0>;
-
- cpsw3g_phy3: ethernet-phy@3 {
- reg = <3>;
- };
- };
- };
-
- transceiver1: can-phy0 {
- compatible = "ti,tcan1042";
- #phy-cells = <0>;
- max-bitrate = <5000000>;
- standby-gpios = <&exp1 8 GPIO_ACTIVE_HIGH>;
- };
-
- transceiver2: can-phy1 {
- compatible = "ti,tcan1042";
- #phy-cells = <0>;
- max-bitrate = <5000000>;
- standby-gpios = <&exp1 9 GPIO_ACTIVE_HIGH>;
- };
-};
-
-&main_pmx0 {
- main_mmc1_pins_default: main-mmc1-default-pins {
- pinctrl-single,pins = <
- AM64X_IOPAD(0x0294, PIN_INPUT_PULLUP, 0) /* (J19) MMC1_CMD */
- AM64X_IOPAD(0x028c, PIN_INPUT_PULLDOWN, 0) /* (L20) MMC1_CLK */
- AM64X_IOPAD(0x0288, PIN_INPUT_PULLUP, 0) /* (K21) MMC1_DAT0 */
- AM64X_IOPAD(0x0284, PIN_INPUT_PULLUP, 0) /* (L21) MMC1_DAT1 */
- AM64X_IOPAD(0x0280, PIN_INPUT_PULLUP, 0) /* (K19) MMC1_DAT2 */
- AM64X_IOPAD(0x027c, PIN_INPUT_PULLUP, 0) /* (K18) MMC1_DAT3 */
- AM64X_IOPAD(0x0298, PIN_INPUT_PULLUP, 0) /* (D19) MMC1_SDCD */
- AM64X_IOPAD(0x029c, PIN_INPUT, 0) /* (C20) MMC1_SDWP */
- AM64X_IOPAD(0x0290, PIN_INPUT, 0) /* MMC1_CLKLB */
- >;
- };
-
- main_uart1_pins_default: main-uart1-default-pins {
- pinctrl-single,pins = <
- AM64X_IOPAD(0x0248, PIN_INPUT, 0) /* (D16) UART1_CTSn */
- AM64X_IOPAD(0x024c, PIN_OUTPUT, 0) /* (E16) UART1_RTSn */
- AM64X_IOPAD(0x0240, PIN_INPUT, 0) /* (E15) UART1_RXD */
- AM64X_IOPAD(0x0244, PIN_OUTPUT, 0) /* (E14) UART1_TXD */
- >;
- };
-
- main_uart0_pins_default: main-uart0-default-pins {
- pinctrl-single,pins = <
- AM64X_IOPAD(0x0238, PIN_INPUT, 0) /* (B16) UART0_CTSn */
- AM64X_IOPAD(0x023c, PIN_OUTPUT, 0) /* (A16) UART0_RTSn */
- AM64X_IOPAD(0x0230, PIN_INPUT, 0) /* (D15) UART0_RXD */
- AM64X_IOPAD(0x0234, PIN_OUTPUT, 0) /* (C16) UART0_TXD */
- >;
- };
-
- main_spi0_pins_default: main-spi0-default-pins {
- pinctrl-single,pins = <
- AM64X_IOPAD(0x0210, PIN_INPUT, 0) /* (D13) SPI0_CLK */
- AM64X_IOPAD(0x0208, PIN_OUTPUT, 0) /* (D12) SPI0_CS0 */
- AM64X_IOPAD(0x0214, PIN_OUTPUT, 0) /* (A13) SPI0_D0 */
- AM64X_IOPAD(0x0218, PIN_INPUT, 0) /* (A14) SPI0_D1 */
- >;
- };
-
- main_i2c0_pins_default: main-i2c0-default-pins {
- pinctrl-single,pins = <
- AM64X_IOPAD(0x0260, PIN_INPUT_PULLUP, 0) /* (A18) I2C0_SCL */
- AM64X_IOPAD(0x0264, PIN_INPUT_PULLUP, 0) /* (B18) I2C0_SDA */
- >;
- };
-
- main_i2c1_pins_default: main-i2c1-default-pins {
- pinctrl-single,pins = <
- AM64X_IOPAD(0x0268, PIN_INPUT_PULLUP, 0) /* (C18) I2C1_SCL */
- AM64X_IOPAD(0x026c, PIN_INPUT_PULLUP, 0) /* (B19) I2C1_SDA */
- >;
- };
-
- mdio1_pins_default: mdio1-default-pins {
- pinctrl-single,pins = <
- AM64X_IOPAD(0x01fc, PIN_OUTPUT, 4) /* (R2) PRG0_PRU1_GPO19.MDIO0_MDC */
- AM64X_IOPAD(0x01f8, PIN_INPUT, 4) /* (P5) PRG0_PRU1_GPO18.MDIO0_MDIO */
- >;
- };
-
- rgmii1_pins_default: rgmii1-default-pins {
- pinctrl-single,pins = <
- AM64X_IOPAD(0x01cc, PIN_INPUT, 4) /* (W5) PRG0_PRU1_GPO7.RGMII1_RD0 */
- AM64X_IOPAD(0x01d4, PIN_INPUT, 4) /* (Y5) PRG0_PRU1_GPO9.RGMII1_RD1 */
- AM64X_IOPAD(0x01d8, PIN_INPUT, 4) /* (V6) PRG0_PRU1_GPO10.RGMII1_RD2 */
- AM64X_IOPAD(0x01f4, PIN_INPUT, 4) /* (V5) PRG0_PRU1_GPO17.RGMII1_RD3 */
- AM64X_IOPAD(0x0188, PIN_INPUT, 4) /* (AA5) PRG0_PRU0_GPO10.RGMII1_RXC */
- AM64X_IOPAD(0x0184, PIN_INPUT, 4) /* (W6) PRG0_PRU0_GPO9.RGMII1_RX_CTL */
- AM64X_IOPAD(0x0124, PIN_OUTPUT, 4) /* (V15) PRG1_PRU1_GPO7.RGMII1_TD0 */
- AM64X_IOPAD(0x012c, PIN_OUTPUT, 4) /* (V14) PRG1_PRU1_GPO9.RGMII1_TD1 */
- AM64X_IOPAD(0x0130, PIN_OUTPUT, 4) /* (W14) PRG1_PRU1_GPO10.RGMII1_TD2 */
- AM64X_IOPAD(0x014c, PIN_OUTPUT, 4) /* (AA14) PRG1_PRU1_GPO17.RGMII1_TD3 */
- AM64X_IOPAD(0x00e0, PIN_OUTPUT, 4) /* (U14) PRG1_PRU0_GPO10.RGMII1_TXC */
- AM64X_IOPAD(0x00dc, PIN_OUTPUT, 4) /* (U15) PRG1_PRU0_GPO9.RGMII1_TX_CTL */
- >;
- };
-
- rgmii2_pins_default: rgmii2-default-pins {
- pinctrl-single,pins = <
- AM64X_IOPAD(0x0108, PIN_INPUT, 4) /* (W11) PRG1_PRU1_GPO0.RGMII2_RD0 */
- AM64X_IOPAD(0x010c, PIN_INPUT, 4) /* (V11) PRG1_PRU1_GPO1.RGMII2_RD1 */
- AM64X_IOPAD(0x0110, PIN_INPUT, 4) /* (AA12) PRG1_PRU1_GPO2.RGMII2_RD2 */
- AM64X_IOPAD(0x0114, PIN_INPUT, 4) /* (Y12) PRG1_PRU1_GPO3.RGMII2_RD3 */
- AM64X_IOPAD(0x0120, PIN_INPUT, 4) /* (U11) PRG1_PRU1_GPO6.RGMII2_RXC */
- AM64X_IOPAD(0x0118, PIN_INPUT, 4) /* (W12) PRG1_PRU1_GPO4.RGMII2_RX_CTL */
- AM64X_IOPAD(0x0134, PIN_OUTPUT, 4) /* (AA10) PRG1_PRU1_GPO11.RGMII2_TD0 */
- AM64X_IOPAD(0x0138, PIN_OUTPUT, 4) /* (V10) PRG1_PRU1_GPO12.RGMII2_TD1 */
- AM64X_IOPAD(0x013c, PIN_OUTPUT, 4) /* (U10) PRG1_PRU1_GPO13.RGMII2_TD2 */
- AM64X_IOPAD(0x0140, PIN_OUTPUT, 4) /* (AA11) PRG1_PRU1_GPO14.RGMII2_TD3 */
- AM64X_IOPAD(0x0148, PIN_OUTPUT, 4) /* (Y10) PRG1_PRU1_GPO16.RGMII2_TXC */
- AM64X_IOPAD(0x0144, PIN_OUTPUT, 4) /* (Y11) PRG1_PRU1_GPO15.RGMII2_TX_CTL */
- >;
- };
-
- main_usb0_pins_default: main-usb0-default-pins {
- pinctrl-single,pins = <
- AM64X_IOPAD(0x02a8, PIN_OUTPUT, 0) /* (E19) USB0_DRVVBUS */
- >;
- };
-
- ospi0_pins_default: ospi0-default-pins {
- pinctrl-single,pins = <
- AM64X_IOPAD(0x0000, PIN_OUTPUT, 0) /* (N20) OSPI0_CLK */
- AM64X_IOPAD(0x002c, PIN_OUTPUT, 0) /* (L19) OSPI0_CSn0 */
- AM64X_IOPAD(0x000c, PIN_INPUT, 0) /* (M19) OSPI0_D0 */
- AM64X_IOPAD(0x0010, PIN_INPUT, 0) /* (M18) OSPI0_D1 */
- AM64X_IOPAD(0x0014, PIN_INPUT, 0) /* (M20) OSPI0_D2 */
- AM64X_IOPAD(0x0018, PIN_INPUT, 0) /* (M21) OSPI0_D3 */
- AM64X_IOPAD(0x001c, PIN_INPUT, 0) /* (P21) OSPI0_D4 */
- AM64X_IOPAD(0x0020, PIN_INPUT, 0) /* (P20) OSPI0_D5 */
- AM64X_IOPAD(0x0024, PIN_INPUT, 0) /* (N18) OSPI0_D6 */
- AM64X_IOPAD(0x0028, PIN_INPUT, 0) /* (M17) OSPI0_D7 */
- AM64X_IOPAD(0x0008, PIN_INPUT, 0) /* (N19) OSPI0_DQS */
- >;
- };
-
- main_ecap0_pins_default: main-ecap0-default-pins {
- pinctrl-single,pins = <
- AM64X_IOPAD(0x0270, PIN_INPUT, 0) /* (D18) ECAP0_IN_APWM_OUT */
- >;
- };
-
- main_mcan0_pins_default: main-mcan0-default-pins {
- pinctrl-single,pins = <
- AM64X_IOPAD(0x0254, PIN_INPUT, 0) /* (B17) MCAN0_RX */
- AM64X_IOPAD(0x0250, PIN_OUTPUT, 0) /* (A17) MCAN0_TX */
- >;
- };
-
- main_mcan1_pins_default: main-mcan1-default-pins {
- pinctrl-single,pins = <
- AM64X_IOPAD(0x025c, PIN_INPUT, 0) /* (D17) MCAN1_RX */
- AM64X_IOPAD(0x0258, PIN_OUTPUT, 0) /* (C17) MCAN1_TX */
- >;
- };
-
- ddr_vtt_pins_default: ddr-vtt-default-pins {
- pinctrl-single,pins = <
- AM64X_IOPAD(0x0030, PIN_OUTPUT_PULLUP, 7) /* (L18) OSPI0_CSN1.GPIO0_12 */
- >;
- };
-};
-
-&main_uart0 {
- status = "okay";
- pinctrl-names = "default";
- pinctrl-0 = <&main_uart0_pins_default>;
- current-speed = <115200>;
-};
-
-/* main_uart1 is reserved for firmware usage */
-&main_uart1 {
- status = "reserved";
- pinctrl-names = "default";
- pinctrl-0 = <&main_uart1_pins_default>;
-};
-
-&main_i2c0 {
- status = "okay";
- pinctrl-names = "default";
- pinctrl-0 = <&main_i2c0_pins_default>;
- clock-frequency = <400000>;
-
- eeprom@50 {
- /* AT24CM01 */
- compatible = "atmel,24c1024";
- reg = <0x50>;
- };
-};
-
-&main_i2c1 {
- status = "okay";
- pinctrl-names = "default";
- pinctrl-0 = <&main_i2c1_pins_default>;
- clock-frequency = <400000>;
-
- exp1: gpio@22 {
- compatible = "ti,tca6424";
- reg = <0x22>;
- gpio-controller;
- #gpio-cells = <2>;
- gpio-line-names = "GPIO_eMMC_RSTn", "CAN_MUX_SEL",
- "GPIO_CPSW1_RST", "GPIO_RGMII1_RST",
- "GPIO_RGMII2_RST", "GPIO_PCIe_RST_OUT",
- "MMC1_SD_EN", "FSI_FET_SEL",
- "MCAN0_STB_3V3", "MCAN1_STB_3V3",
- "CPSW_FET_SEL", "CPSW_FET2_SEL",
- "PRG1_RGMII2_FET_SEL", "TEST_GPIO2",
- "GPIO_OLED_RESETn", "VPP_LDO_EN",
- "TEST_LED1", "TP92", "TP90", "TP88",
- "TP87", "TP86", "TP89", "TP91";
- };
-
- /* osd9616p0899-10 */
- display@3c {
- compatible = "solomon,ssd1306fb-i2c";
- reg = <0x3c>;
- reset-gpios = <&exp1 14 GPIO_ACTIVE_LOW>;
- vbat-supply = <&vddb>;
- solomon,height = <16>;
- solomon,width = <96>;
- solomon,com-seq;
- solomon,com-invdir;
- solomon,page-offset = <0>;
- solomon,prechargep1 = <2>;
- solomon,prechargep2 = <13>;
- };
-};
-
-/* mcu_gpio0 is reserved for mcu firmware usage */
-&mcu_gpio0 {
- status = "reserved";
-};
-
-&main_spi0 {
- status = "okay";
- pinctrl-names = "default";
- pinctrl-0 = <&main_spi0_pins_default>;
- ti,pindir-d0-out-d1-in;
- eeprom@0 {
- compatible = "microchip,93lc46b";
- reg = <0>;
- spi-max-frequency = <1000000>;
- spi-cs-high;
- data-size = <16>;
- };
-};
-
-&sdhci0 {
- /* emmc */
- bus-width = <8>;
- non-removable;
- ti,driver-strength-ohm = <50>;
- disable-wp;
-};
-
-&sdhci1 {
- /* SD/MMC */
- vmmc-supply = <&vdd_mmc1>;
- pinctrl-names = "default";
- bus-width = <4>;
- pinctrl-0 = <&main_mmc1_pins_default>;
- ti,driver-strength-ohm = <50>;
- disable-wp;
-};
-
-&usbss0 {
- ti,vbus-divider;
- ti,usb2-only;
-};
-
-&usb0 {
- dr_mode = "otg";
- maximum-speed = "high-speed";
- pinctrl-names = "default";
- pinctrl-0 = <&main_usb0_pins_default>;
-};
-
-&cpsw3g {
- pinctrl-names = "default";
- pinctrl-0 = <&rgmii1_pins_default>, <&rgmii2_pins_default>;
-};
-
-&cpsw_port1 {
- phy-mode = "rgmii-rxid";
- phy-handle = <&cpsw3g_phy0>;
-};
-
-&cpsw_port2 {
- phy-mode = "rgmii-rxid";
- phy-handle = <&cpsw3g_phy3>;
-};
-
-&cpsw3g_mdio {
- status = "okay";
- pinctrl-names = "default";
- pinctrl-0 = <&mdio1_pins_default>;
-
- cpsw3g_phy0: ethernet-phy@0 {
- reg = <0>;
- ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_00_NS>;
- ti,fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>;
- };
-};
-
-&tscadc0 {
- /* ADC is reserved for R5 usage */
- status = "reserved";
-};
-
-&ospi0 {
- status = "okay";
- pinctrl-names = "default";
- pinctrl-0 = <&ospi0_pins_default>;
-
- flash@0 {
- compatible = "jedec,spi-nor";
- reg = <0x0>;
- spi-tx-bus-width = <8>;
- spi-rx-bus-width = <8>;
- spi-max-frequency = <25000000>;
- cdns,tshsl-ns = <60>;
- cdns,tsd2d-ns = <60>;
- cdns,tchsh-ns = <60>;
- cdns,tslch-ns = <60>;
- cdns,read-delay = <4>;
-
- partitions {
- compatible = "fixed-partitions";
- #address-cells = <1>;
- #size-cells = <1>;
-
- partition@0 {
- label = "ospi.tiboot3";
- reg = <0x0 0x100000>;
- };
-
- partition@100000 {
- label = "ospi.tispl";
- reg = <0x100000 0x200000>;
- };
-
- partition@300000 {
- label = "ospi.u-boot";
- reg = <0x300000 0x400000>;
- };
-
- partition@700000 {
- label = "ospi.env";
- reg = <0x700000 0x40000>;
- };
-
- partition@740000 {
- label = "ospi.env.backup";
- reg = <0x740000 0x40000>;
- };
-
- partition@800000 {
- label = "ospi.rootfs";
- reg = <0x800000 0x37c0000>;
- };
-
- partition@3fc0000 {
- label = "ospi.phypattern";
- reg = <0x3fc0000 0x40000>;
- };
- };
- };
-};
-
-&mailbox0_cluster2 {
- status = "okay";
-
- mbox_main_r5fss0_core0: mbox-main-r5fss0-core0 {
- ti,mbox-rx = <0 0 2>;
- ti,mbox-tx = <1 0 2>;
- };
-
- mbox_main_r5fss0_core1: mbox-main-r5fss0-core1 {
- ti,mbox-rx = <2 0 2>;
- ti,mbox-tx = <3 0 2>;
- };
-};
-
-&mailbox0_cluster4 {
- status = "okay";
-
- mbox_main_r5fss1_core0: mbox-main-r5fss1-core0 {
- ti,mbox-rx = <0 0 2>;
- ti,mbox-tx = <1 0 2>;
- };
-
- mbox_main_r5fss1_core1: mbox-main-r5fss1-core1 {
- ti,mbox-rx = <2 0 2>;
- ti,mbox-tx = <3 0 2>;
- };
-};
-
-&mailbox0_cluster6 {
- status = "okay";
-
- mbox_m4_0: mbox-m4-0 {
- ti,mbox-rx = <0 0 2>;
- ti,mbox-tx = <1 0 2>;
- };
-};
-
-&main_r5fss0_core0 {
- mboxes = <&mailbox0_cluster2>, <&mbox_main_r5fss0_core0>;
- memory-region = <&main_r5fss0_core0_dma_memory_region>,
- <&main_r5fss0_core0_memory_region>;
-};
-
-&main_r5fss0_core1 {
- mboxes = <&mailbox0_cluster2>, <&mbox_main_r5fss0_core1>;
- memory-region = <&main_r5fss0_core1_dma_memory_region>,
- <&main_r5fss0_core1_memory_region>;
-};
-
-&main_r5fss1_core0 {
- mboxes = <&mailbox0_cluster4>, <&mbox_main_r5fss1_core0>;
- memory-region = <&main_r5fss1_core0_dma_memory_region>,
- <&main_r5fss1_core0_memory_region>;
-};
-
-&main_r5fss1_core1 {
- mboxes = <&mailbox0_cluster4>, <&mbox_main_r5fss1_core1>;
- memory-region = <&main_r5fss1_core1_dma_memory_region>,
- <&main_r5fss1_core1_memory_region>;
-};
-
-&serdes_ln_ctrl {
- idle-states = <AM64_SERDES0_LANE0_PCIE0>;
-};
-
-&serdes0 {
- serdes0_pcie_link: phy@0 {
- reg = <0>;
- cdns,num-lanes = <1>;
- #phy-cells = <0>;
- cdns,phy-type = <PHY_TYPE_PCIE>;
- resets = <&serdes_wiz0 1>;
- };
-};
-
-&pcie0_rc {
- status = "okay";
- reset-gpios = <&exp1 5 GPIO_ACTIVE_HIGH>;
- phys = <&serdes0_pcie_link>;
- phy-names = "pcie-phy";
- num-lanes = <1>;
-};
-
-&pcie0_ep {
- phys = <&serdes0_pcie_link>;
- phy-names = "pcie-phy";
- num-lanes = <1>;
-};
-
-&ecap0 {
- status = "okay";
- /* PWM is available on Pin 1 of header J12 */
- pinctrl-names = "default";
- pinctrl-0 = <&main_ecap0_pins_default>;
-};
-
-&main_mcan0 {
- status = "okay";
- pinctrl-names = "default";
- pinctrl-0 = <&main_mcan0_pins_default>;
- phys = <&transceiver1>;
-};
-
-&main_mcan1 {
- status = "okay";
- pinctrl-names = "default";
- pinctrl-0 = <&main_mcan1_pins_default>;
- phys = <&transceiver2>;
-};
diff --git a/arch/arm/dts/k3-am642-r5-evm.dts b/arch/arm/dts/k3-am642-r5-evm.dts
index 6825c07..be85969 100644
--- a/arch/arm/dts/k3-am642-r5-evm.dts
+++ b/arch/arm/dts/k3-am642-r5-evm.dts
@@ -40,10 +40,6 @@
};
};
-&vtt_supply {
- bootph-pre-ram;
-};
-
&cbass_main {
sysctrler: sysctrler {
compatible = "ti,am654-system-controller";
@@ -53,18 +49,6 @@
};
};
-&main_esm {
- bootph-pre-ram;
-};
-
-&cbass_mcu {
- bootph-pre-ram;
-};
-
-&mcu_esm {
- bootph-pre-ram;
-};
-
&dmsc {
mboxes= <&secure_proxy_main 0>,
<&secure_proxy_main 1>,
@@ -74,10 +58,6 @@
ti,secure-host;
};
-&vtt_supply {
- bootph-pre-ram;
-};
-
&memorycontroller {
vtt-supply = <&vtt_supply>;
};
@@ -92,10 +72,6 @@
clock-names = "clk_xin";
};
-&main_gpio0 {
- bootph-pre-ram;
-};
-
/* UART is initialized before SYSFW is started
* so we can't do any power-domain/clock operations.
* Delete clock/power-domain properties to avoid
diff --git a/arch/arm/dts/k3-am642-r5-sk.dts b/arch/arm/dts/k3-am642-r5-sk.dts
index 60d747d..2186152 100644
--- a/arch/arm/dts/k3-am642-r5-sk.dts
+++ b/arch/arm/dts/k3-am642-r5-sk.dts
@@ -49,18 +49,6 @@
};
};
-&main_esm {
- bootph-pre-ram;
-};
-
-&cbass_mcu {
- bootph-pre-ram;
-};
-
-&mcu_esm {
- bootph-pre-ram;
-};
-
&dmsc {
mboxes= <&secure_proxy_main 0>,
<&secure_proxy_main 1>,
diff --git a/arch/arm/dts/k3-am642-sk-u-boot.dtsi b/arch/arm/dts/k3-am642-sk-u-boot.dtsi
index 2f93eb6..7e6b298 100644
--- a/arch/arm/dts/k3-am642-sk-u-boot.dtsi
+++ b/arch/arm/dts/k3-am642-sk-u-boot.dtsi
@@ -9,87 +9,21 @@
chosen {
tick-timer = &main_timer0;
};
-
- memory@80000000 {
- bootph-all;
- };
};
-&cbass_main{
- bootph-all;
-};
-
&main_timer0 {
- bootph-all;
clock-frequency = <200000000>;
};
-&main_conf {
- bootph-all;
- chipid@14 {
- bootph-all;
- };
-};
-
-&main_pmx0 {
- bootph-all;
-};
-
-&main_i2c0_pins_default {
- bootph-all;
-};
-
-&main_i2c0 {
- bootph-all;
-};
-
-&main_uart0_pins_default {
- bootph-all;
-};
-
-&main_uart0 {
- bootph-all;
-};
-
-&dmss {
- bootph-all;
-};
-
-&secure_proxy_main {
- bootph-all;
-};
-
&dmsc {
- bootph-all;
k3_sysreset: sysreset-controller {
compatible = "ti,sci-sysreset";
bootph-all;
};
};
-&k3_pds {
- bootph-all;
-};
-
-&k3_clks {
- bootph-all;
-};
-
-&k3_reset {
- bootph-all;
-};
-
&sdhci0 {
status = "disabled";
- bootph-all;
-};
-
-&sdhci1 {
- bootph-all;
-};
-
-&main_mmc1_pins_default {
- bootph-all;
};
&inta_main_dmss {
@@ -180,38 +114,10 @@
bootph-all;
};
-&main_usb0_pins_default {
- bootph-all;
-};
-
&serdes_ln_ctrl {
bootph-all;
};
-&usbss0 {
- bootph-all;
-};
-
-&usb0 {
- bootph-all;
-};
-
-&serdes_wiz0 {
- bootph-all;
-};
-
-&serdes0_usb_link {
- bootph-all;
-};
-
-&serdes0 {
- bootph-all;
-};
-
-&serdes_refclk {
- bootph-all;
-};
-
&ospi0_pins_default {
bootph-all;
};
diff --git a/arch/arm/dts/k3-am642-sk.dts b/arch/arm/dts/k3-am642-sk.dts
deleted file mode 100644
index 722fd28..0000000
--- a/arch/arm/dts/k3-am642-sk.dts
+++ /dev/null
@@ -1,642 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0
-/*
- * Copyright (C) 2021 Texas Instruments Incorporated - https://www.ti.com/
- */
-
-/dts-v1/;
-
-#include <dt-bindings/phy/phy.h>
-#include <dt-bindings/gpio/gpio.h>
-#include <dt-bindings/net/ti-dp83867.h>
-#include <dt-bindings/leds/common.h>
-#include "k3-am642.dtsi"
-
-#include "k3-serdes.h"
-
-/ {
- compatible = "ti,am642-sk", "ti,am642";
- model = "Texas Instruments AM642 SK";
-
- chosen {
- stdout-path = &main_uart0;
- };
-
- aliases {
- serial0 = &mcu_uart0;
- serial1 = &main_uart1;
- serial2 = &main_uart0;
- i2c0 = &main_i2c0;
- i2c1 = &main_i2c1;
- mmc0 = &sdhci0;
- mmc1 = &sdhci1;
- ethernet0 = &cpsw_port1;
- ethernet1 = &cpsw_port2;
- };
-
- memory@80000000 {
- device_type = "memory";
- /* 2G RAM */
- reg = <0x00000000 0x80000000 0x00000000 0x80000000>;
- };
-
- reserved-memory {
- #address-cells = <2>;
- #size-cells = <2>;
- ranges;
-
- secure_ddr: optee@9e800000 {
- reg = <0x00 0x9e800000 0x00 0x01800000>; /* for OP-TEE */
- alignment = <0x1000>;
- no-map;
- };
-
- main_r5fss0_core0_dma_memory_region: r5f-dma-memory@a0000000 {
- compatible = "shared-dma-pool";
- reg = <0x00 0xa0000000 0x00 0x100000>;
- no-map;
- };
-
- main_r5fss0_core0_memory_region: r5f-memory@a0100000 {
- compatible = "shared-dma-pool";
- reg = <0x00 0xa0100000 0x00 0xf00000>;
- no-map;
- };
-
- main_r5fss0_core1_dma_memory_region: r5f-dma-memory@a1000000 {
- compatible = "shared-dma-pool";
- reg = <0x00 0xa1000000 0x00 0x100000>;
- no-map;
- };
-
- main_r5fss0_core1_memory_region: r5f-memory@a1100000 {
- compatible = "shared-dma-pool";
- reg = <0x00 0xa1100000 0x00 0xf00000>;
- no-map;
- };
-
- main_r5fss1_core0_dma_memory_region: r5f-dma-memory@a2000000 {
- compatible = "shared-dma-pool";
- reg = <0x00 0xa2000000 0x00 0x100000>;
- no-map;
- };
-
- main_r5fss1_core0_memory_region: r5f-memory@a2100000 {
- compatible = "shared-dma-pool";
- reg = <0x00 0xa2100000 0x00 0xf00000>;
- no-map;
- };
-
- main_r5fss1_core1_dma_memory_region: r5f-dma-memory@a3000000 {
- compatible = "shared-dma-pool";
- reg = <0x00 0xa3000000 0x00 0x100000>;
- no-map;
- };
-
- main_r5fss1_core1_memory_region: r5f-memory@a3100000 {
- compatible = "shared-dma-pool";
- reg = <0x00 0xa3100000 0x00 0xf00000>;
- no-map;
- };
-
- rtos_ipc_memory_region: ipc-memories@a5000000 {
- reg = <0x00 0xa5000000 0x00 0x00800000>;
- alignment = <0x1000>;
- no-map;
- };
- };
-
- vusb_main: regulator-0 {
- /* USB MAIN INPUT 5V DC */
- compatible = "regulator-fixed";
- regulator-name = "vusb_main5v0";
- regulator-min-microvolt = <5000000>;
- regulator-max-microvolt = <5000000>;
- regulator-always-on;
- regulator-boot-on;
- };
-
- vcc_3v3_sys: regulator-1 {
- /* output of LP8733xx */
- compatible = "regulator-fixed";
- regulator-name = "vcc_3v3_sys";
- regulator-min-microvolt = <3300000>;
- regulator-max-microvolt = <3300000>;
- vin-supply = <&vusb_main>;
- regulator-always-on;
- regulator-boot-on;
- };
-
- vdd_mmc1: regulator-2 {
- /* TPS2051BD */
- compatible = "regulator-fixed";
- regulator-name = "vdd_mmc1";
- regulator-min-microvolt = <3300000>;
- regulator-max-microvolt = <3300000>;
- regulator-boot-on;
- enable-active-high;
- vin-supply = <&vcc_3v3_sys>;
- gpio = <&exp1 3 GPIO_ACTIVE_HIGH>;
- };
-
- com8_ls_en: regulator-3 {
- compatible = "regulator-fixed";
- regulator-name = "com8_ls_en";
- regulator-min-microvolt = <3300000>;
- regulator-max-microvolt = <3300000>;
- regulator-always-on;
- regulator-boot-on;
- pinctrl-0 = <&main_com8_ls_en_pins_default>;
- pinctrl-names = "default";
- gpio = <&main_gpio0 62 GPIO_ACTIVE_LOW>;
- };
-
- wlan_en: regulator-4 {
- /* output of SN74AVC4T245RSVR */
- compatible = "regulator-fixed";
- regulator-name = "wlan_en";
- regulator-min-microvolt = <1800000>;
- regulator-max-microvolt = <1800000>;
- enable-active-high;
- pinctrl-0 = <&main_wlan_en_pins_default>;
- pinctrl-names = "default";
- vin-supply = <&com8_ls_en>;
- gpio = <&main_gpio0 48 GPIO_ACTIVE_HIGH>;
- };
-
- led-controller {
- compatible = "gpio-leds";
-
- led-0 {
- color = <LED_COLOR_ID_GREEN>;
- function = LED_FUNCTION_INDICATOR;
- function-enumerator = <1>;
- gpios = <&exp2 0 GPIO_ACTIVE_HIGH>;
- default-state = "off";
- };
-
- led-1 {
- color = <LED_COLOR_ID_RED>;
- function = LED_FUNCTION_INDICATOR;
- function-enumerator = <2>;
- gpios = <&exp2 1 GPIO_ACTIVE_HIGH>;
- default-state = "off";
- };
-
- led-2 {
- color = <LED_COLOR_ID_GREEN>;
- function = LED_FUNCTION_INDICATOR;
- function-enumerator = <3>;
- gpios = <&exp2 2 GPIO_ACTIVE_HIGH>;
- default-state = "off";
- };
-
- led-3 {
- color = <LED_COLOR_ID_AMBER>;
- function = LED_FUNCTION_INDICATOR;
- function-enumerator = <4>;
- gpios = <&exp2 3 GPIO_ACTIVE_HIGH>;
- default-state = "off";
- };
-
- led-4 {
- color = <LED_COLOR_ID_GREEN>;
- function = LED_FUNCTION_INDICATOR;
- function-enumerator = <5>;
- gpios = <&exp2 4 GPIO_ACTIVE_HIGH>;
- default-state = "off";
- };
-
- led-5 {
- color = <LED_COLOR_ID_RED>;
- function = LED_FUNCTION_INDICATOR;
- function-enumerator = <6>;
- gpios = <&exp2 5 GPIO_ACTIVE_HIGH>;
- default-state = "off";
- };
-
- led-6 {
- color = <LED_COLOR_ID_GREEN>;
- function = LED_FUNCTION_INDICATOR;
- function-enumerator = <7>;
- gpios = <&exp2 6 GPIO_ACTIVE_HIGH>;
- default-state = "off";
- };
-
- led-7 {
- color = <LED_COLOR_ID_AMBER>;
- function = LED_FUNCTION_HEARTBEAT;
- function-enumerator = <8>;
- linux,default-trigger = "heartbeat";
- gpios = <&exp2 7 GPIO_ACTIVE_HIGH>;
- };
- };
-};
-
-&main_pmx0 {
- main_mmc1_pins_default: main-mmc1-default-pins {
- pinctrl-single,pins = <
- AM64X_IOPAD(0x029c, PIN_INPUT_PULLUP, 0) /* (C20) MMC1_SDWP */
- AM64X_IOPAD(0x0298, PIN_INPUT_PULLUP, 0) /* (D19) MMC1_SDCD */
- AM64X_IOPAD(0x0294, PIN_INPUT_PULLUP, 0) /* (J19) MMC1_CMD */
- AM64X_IOPAD(0x0290, PIN_INPUT, 0) /* (#N/A) MMC1_CLKLB */
- AM64X_IOPAD(0x028c, PIN_INPUT_PULLDOWN, 0) /* (L20) MMC1_CLK */
- AM64X_IOPAD(0x0288, PIN_INPUT_PULLUP, 0) /* (K21) MMC1_DAT0 */
- AM64X_IOPAD(0x0284, PIN_INPUT_PULLUP, 0) /* (L21) MMC1_DAT1 */
- AM64X_IOPAD(0x0280, PIN_INPUT_PULLUP, 0) /* (K19) MMC1_DAT2 */
- AM64X_IOPAD(0x027c, PIN_INPUT_PULLUP, 0) /* (K18) MMC1_DAT3 */
- >;
- };
-
- main_uart0_pins_default: main-uart0-default-pins {
- pinctrl-single,pins = <
- AM64X_IOPAD(0x0238, PIN_INPUT, 0) /* (B16) UART0_CTSn */
- AM64X_IOPAD(0x023c, PIN_OUTPUT, 0) /* (A16) UART0_RTSn */
- AM64X_IOPAD(0x0230, PIN_INPUT, 0) /* (D15) UART0_RXD */
- AM64X_IOPAD(0x0234, PIN_OUTPUT, 0) /* (C16) UART0_TXD */
- >;
- };
-
- main_uart1_pins_default: main-uart1-default-pins {
- pinctrl-single,pins = <
- AM64X_IOPAD(0x0248, PIN_INPUT, 0) /* (D16) UART1_CTSn */
- AM64X_IOPAD(0x024c, PIN_OUTPUT, 0) /* (E16) UART1_RTSn */
- AM64X_IOPAD(0x0240, PIN_INPUT, 0) /* (E15) UART1_RXD */
- AM64X_IOPAD(0x0244, PIN_OUTPUT, 0) /* (E14) UART1_TXD */
- >;
- };
-
- main_usb0_pins_default: main-usb0-default-pins {
- pinctrl-single,pins = <
- AM64X_IOPAD(0x02a8, PIN_OUTPUT, 0) /* (E19) USB0_DRVVBUS */
- >;
- };
-
- main_i2c0_pins_default: main-i2c0-default-pins {
- pinctrl-single,pins = <
- AM64X_IOPAD(0x0260, PIN_INPUT_PULLUP, 0) /* (A18) I2C0_SCL */
- AM64X_IOPAD(0x0264, PIN_INPUT_PULLUP, 0) /* (B18) I2C0_SDA */
- >;
- };
-
- main_i2c1_pins_default: main-i2c1-default-pins {
- pinctrl-single,pins = <
- AM64X_IOPAD(0x0268, PIN_INPUT_PULLUP, 0) /* (C18) I2C1_SCL */
- AM64X_IOPAD(0x026c, PIN_INPUT_PULLUP, 0) /* (B19) I2C1_SDA */
- >;
- };
-
- mdio1_pins_default: mdio1-default-pins {
- pinctrl-single,pins = <
- AM64X_IOPAD(0x01fc, PIN_OUTPUT, 4) /* (R2) PRG0_PRU1_GPO19.MDIO0_MDC */
- AM64X_IOPAD(0x01f8, PIN_INPUT, 4) /* (P5) PRG0_PRU1_GPO18.MDIO0_MDIO */
- >;
- };
-
- rgmii1_pins_default: rgmii1-default-pins {
- pinctrl-single,pins = <
- AM64X_IOPAD(0x011c, PIN_INPUT, 4) /* (AA13) PRG1_PRU1_GPO5.RGMII1_RD0 */
- AM64X_IOPAD(0x0128, PIN_INPUT, 4) /* (U12) PRG1_PRU1_GPO8.RGMII1_RD1 */
- AM64X_IOPAD(0x0150, PIN_INPUT, 4) /* (Y13) PRG1_PRU1_GPO18.RGMII1_RD2 */
- AM64X_IOPAD(0x0154, PIN_INPUT, 4) /* (V12) PRG1_PRU1_GPO19.RGMII1_RD3 */
- AM64X_IOPAD(0x00d8, PIN_INPUT, 4) /* (W13) PRG1_PRU0_GPO8.RGMII1_RXC */
- AM64X_IOPAD(0x00cc, PIN_INPUT, 4) /* (V13) PRG1_PRU0_GPO5.RGMII1_RX_CTL */
- AM64X_IOPAD(0x0124, PIN_OUTPUT, 4) /* (V15) PRG1_PRU1_GPO7.RGMII1_TD0 */
- AM64X_IOPAD(0x012c, PIN_OUTPUT, 4) /* (V14) PRG1_PRU1_GPO9.RGMII1_TD1 */
- AM64X_IOPAD(0x0130, PIN_OUTPUT, 4) /* (W14) PRG1_PRU1_GPO10.RGMII1_TD2 */
- AM64X_IOPAD(0x014c, PIN_OUTPUT, 4) /* (AA14) PRG1_PRU1_GPO17.RGMII1_TD3 */
- AM64X_IOPAD(0x00e0, PIN_OUTPUT, 4) /* (U14) PRG1_PRU0_GPO10.RGMII1_TXC */
- AM64X_IOPAD(0x00dc, PIN_OUTPUT, 4) /* (U15) PRG1_PRU0_GPO9.RGMII1_TX_CTL */
- >;
- };
-
- rgmii2_pins_default: rgmii2-default-pins {
- pinctrl-single,pins = <
- AM64X_IOPAD(0x0108, PIN_INPUT, 4) /* (W11) PRG1_PRU1_GPO0.RGMII2_RD0 */
- AM64X_IOPAD(0x010c, PIN_INPUT, 4) /* (V11) PRG1_PRU1_GPO1.RGMII2_RD1 */
- AM64X_IOPAD(0x0110, PIN_INPUT, 4) /* (AA12) PRG1_PRU1_GPO2.RGMII2_RD2 */
- AM64X_IOPAD(0x0114, PIN_INPUT, 4) /* (Y12) PRG1_PRU1_GPO3.RGMII2_RD3 */
- AM64X_IOPAD(0x0120, PIN_INPUT, 4) /* (U11) PRG1_PRU1_GPO6.RGMII2_RXC */
- AM64X_IOPAD(0x0118, PIN_INPUT, 4) /* (W12) PRG1_PRU1_GPO4.RGMII2_RX_CTL */
- AM64X_IOPAD(0x0134, PIN_OUTPUT, 4) /* (AA10) PRG1_PRU1_GPO11.RGMII2_TD0 */
- AM64X_IOPAD(0x0138, PIN_OUTPUT, 4) /* (V10) PRG1_PRU1_GPO12.RGMII2_TD1 */
- AM64X_IOPAD(0x013c, PIN_OUTPUT, 4) /* (U10) PRG1_PRU1_GPO13.RGMII2_TD2 */
- AM64X_IOPAD(0x0140, PIN_OUTPUT, 4) /* (AA11) PRG1_PRU1_GPO14.RGMII2_TD3 */
- AM64X_IOPAD(0x0148, PIN_OUTPUT, 4) /* (Y10) PRG1_PRU1_GPO16.RGMII2_TXC */
- AM64X_IOPAD(0x0144, PIN_OUTPUT, 4) /* (Y11) PRG1_PRU1_GPO15.RGMII2_TX_CTL */
- >;
- };
-
- ospi0_pins_default: ospi0-default-pins {
- pinctrl-single,pins = <
- AM64X_IOPAD(0x0000, PIN_OUTPUT, 0) /* (N20) OSPI0_CLK */
- AM64X_IOPAD(0x002c, PIN_OUTPUT, 0) /* (L19) OSPI0_CSn0 */
- AM64X_IOPAD(0x000c, PIN_INPUT, 0) /* (M19) OSPI0_D0 */
- AM64X_IOPAD(0x0010, PIN_INPUT, 0) /* (M18) OSPI0_D1 */
- AM64X_IOPAD(0x0014, PIN_INPUT, 0) /* (M20) OSPI0_D2 */
- AM64X_IOPAD(0x0018, PIN_INPUT, 0) /* (M21) OSPI0_D3 */
- AM64X_IOPAD(0x001c, PIN_INPUT, 0) /* (P21) OSPI0_D4 */
- AM64X_IOPAD(0x0020, PIN_INPUT, 0) /* (P20) OSPI0_D5 */
- AM64X_IOPAD(0x0024, PIN_INPUT, 0) /* (N18) OSPI0_D6 */
- AM64X_IOPAD(0x0028, PIN_INPUT, 0) /* (M17) OSPI0_D7 */
- AM64X_IOPAD(0x0008, PIN_INPUT, 0) /* (N19) OSPI0_DQS */
- >;
- };
-
- main_ecap0_pins_default: main-ecap0-default-pins {
- pinctrl-single,pins = <
- AM64X_IOPAD(0x0270, PIN_INPUT, 0) /* (D18) ECAP0_IN_APWM_OUT */
- >;
- };
- main_wlan_en_pins_default: main-wlan-en-default-pins {
- pinctrl-single,pins = <
- AM64X_IOPAD(0x00c4, PIN_OUTPUT_PULLUP, 7) /* (V8) GPIO0_48 */
- >;
- };
-
- main_com8_ls_en_pins_default: main-com8-ls-en-default-pins {
- pinctrl-single,pins = <
- AM64X_IOPAD(0x00fc, PIN_OUTPUT, 7) /* (U7) PRG1_PRU0_GPO17.GPIO0_62 */
- >;
- };
-
- main_wlan_pins_default: main-wlan-default-pins {
- pinctrl-single,pins = <
- AM64X_IOPAD(0x00bc, PIN_INPUT, 7) /* (U8) GPIO0_46 */
- >;
- };
-};
-
-&main_uart0 {
- status = "okay";
- pinctrl-names = "default";
- pinctrl-0 = <&main_uart0_pins_default>;
- current-speed = <115200>;
-};
-
-&main_uart1 {
- /* main_uart1 is reserved for firmware usage */
- status = "reserved";
- pinctrl-names = "default";
- pinctrl-0 = <&main_uart1_pins_default>;
-};
-
-&main_i2c0 {
- status = "okay";
- pinctrl-names = "default";
- pinctrl-0 = <&main_i2c0_pins_default>;
- clock-frequency = <400000>;
-
- eeprom@51 {
- compatible = "atmel,24c512";
- reg = <0x51>;
- };
-};
-
-&main_i2c1 {
- status = "okay";
- pinctrl-names = "default";
- pinctrl-0 = <&main_i2c1_pins_default>;
- clock-frequency = <400000>;
-
- exp1: gpio@70 {
- compatible = "nxp,pca9538";
- reg = <0x70>;
- gpio-controller;
- #gpio-cells = <2>;
- gpio-line-names = "GPIO_CPSW2_RST", "GPIO_CPSW1_RST",
- "PRU_DETECT", "MMC1_SD_EN",
- "VPP_LDO_EN", "RPI_PS_3V3_En",
- "RPI_PS_5V0_En", "RPI_HAT_DETECT";
- };
-
- exp2: gpio@60 {
- compatible = "ti,tpic2810";
- reg = <0x60>;
- gpio-controller;
- #gpio-cells = <2>;
- gpio-line-names = "LED1","LED2","LED3","LED4","LED5","LED6","LED7","LED8";
- };
-};
-
-/* mcu_gpio0 is reserved for mcu firmware usage */
-&mcu_gpio0 {
- status = "reserved";
-};
-
-&sdhci0 {
- vmmc-supply = <&wlan_en>;
- bus-width = <4>;
- non-removable;
- cap-power-off-card;
- keep-power-in-suspend;
- ti,driver-strength-ohm = <50>;
-
- #address-cells = <1>;
- #size-cells = <0>;
- wlcore: wlcore@2 {
- compatible = "ti,wl1837";
- reg = <2>;
- pinctrl-0 = <&main_wlan_pins_default>;
- pinctrl-names = "default";
- interrupt-parent = <&main_gpio0>;
- interrupts = <46 IRQ_TYPE_EDGE_FALLING>;
- };
-};
-
-&sdhci1 {
- /* SD/MMC */
- vmmc-supply = <&vdd_mmc1>;
- pinctrl-names = "default";
- bus-width = <4>;
- pinctrl-0 = <&main_mmc1_pins_default>;
- ti,driver-strength-ohm = <50>;
- disable-wp;
-};
-
-&serdes_ln_ctrl {
- idle-states = <AM64_SERDES0_LANE0_USB>;
-};
-
-&serdes0 {
- serdes0_usb_link: phy@0 {
- reg = <0>;
- cdns,num-lanes = <1>;
- #phy-cells = <0>;
- cdns,phy-type = <PHY_TYPE_USB3>;
- resets = <&serdes_wiz0 1>;
- };
-};
-
-&usbss0 {
- ti,vbus-divider;
-};
-
-&usb0 {
- dr_mode = "host";
- maximum-speed = "super-speed";
- pinctrl-names = "default";
- pinctrl-0 = <&main_usb0_pins_default>;
- phys = <&serdes0_usb_link>;
- phy-names = "cdns3,usb3-phy";
-};
-
-&cpsw3g {
- pinctrl-names = "default";
- pinctrl-0 = <&rgmii1_pins_default>, <&rgmii2_pins_default>;
-};
-
-&cpsw_port1 {
- phy-mode = "rgmii-rxid";
- phy-handle = <&cpsw3g_phy0>;
-};
-
-&cpsw_port2 {
- phy-mode = "rgmii-rxid";
- phy-handle = <&cpsw3g_phy1>;
-};
-
-&cpsw3g_mdio {
- status = "okay";
- pinctrl-names = "default";
- pinctrl-0 = <&mdio1_pins_default>;
-
- cpsw3g_phy0: ethernet-phy@0 {
- reg = <0>;
- ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_00_NS>;
- ti,fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>;
- };
-
- cpsw3g_phy1: ethernet-phy@1 {
- reg = <1>;
- ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_00_NS>;
- ti,fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>;
- };
-};
-
-&ospi0 {
- status = "okay";
- pinctrl-names = "default";
- pinctrl-0 = <&ospi0_pins_default>;
-
- flash@0 {
- compatible = "jedec,spi-nor";
- reg = <0x0>;
- spi-tx-bus-width = <8>;
- spi-rx-bus-width = <8>;
- spi-max-frequency = <25000000>;
- cdns,tshsl-ns = <60>;
- cdns,tsd2d-ns = <60>;
- cdns,tchsh-ns = <60>;
- cdns,tslch-ns = <60>;
- cdns,read-delay = <4>;
-
- partitions {
- compatible = "fixed-partitions";
- #address-cells = <1>;
- #size-cells = <1>;
-
- partition@0 {
- label = "ospi.tiboot3";
- reg = <0x0 0x100000>;
- };
-
- partition@100000 {
- label = "ospi.tispl";
- reg = <0x100000 0x200000>;
- };
-
- partition@300000 {
- label = "ospi.u-boot";
- reg = <0x300000 0x400000>;
- };
-
- partition@700000 {
- label = "ospi.env";
- reg = <0x700000 0x40000>;
- };
-
- partition@740000 {
- label = "ospi.env.backup";
- reg = <0x740000 0x40000>;
- };
-
- partition@800000 {
- label = "ospi.rootfs";
- reg = <0x800000 0x37c0000>;
- };
-
- partition@3fc0000 {
- label = "ospi.phypattern";
- reg = <0x3fc0000 0x40000>;
- };
- };
- };
-};
-
-&mailbox0_cluster2 {
- status = "okay";
-
- mbox_main_r5fss0_core0: mbox-main-r5fss0-core0 {
- ti,mbox-rx = <0 0 2>;
- ti,mbox-tx = <1 0 2>;
- };
-
- mbox_main_r5fss0_core1: mbox-main-r5fss0-core1 {
- ti,mbox-rx = <2 0 2>;
- ti,mbox-tx = <3 0 2>;
- };
-};
-
-&mailbox0_cluster4 {
- status = "okay";
-
- mbox_main_r5fss1_core0: mbox-main-r5fss1-core0 {
- ti,mbox-rx = <0 0 2>;
- ti,mbox-tx = <1 0 2>;
- };
-
- mbox_main_r5fss1_core1: mbox-main-r5fss1-core1 {
- ti,mbox-rx = <2 0 2>;
- ti,mbox-tx = <3 0 2>;
- };
-};
-
-&mailbox0_cluster6 {
- status = "okay";
-
- mbox_m4_0: mbox-m4-0 {
- ti,mbox-rx = <0 0 2>;
- ti,mbox-tx = <1 0 2>;
- };
-};
-
-&main_r5fss0_core0 {
- mboxes = <&mailbox0_cluster2>, <&mbox_main_r5fss0_core0>;
- memory-region = <&main_r5fss0_core0_dma_memory_region>,
- <&main_r5fss0_core0_memory_region>;
-};
-
-&main_r5fss0_core1 {
- mboxes = <&mailbox0_cluster2>, <&mbox_main_r5fss0_core1>;
- memory-region = <&main_r5fss0_core1_dma_memory_region>,
- <&main_r5fss0_core1_memory_region>;
-};
-
-&main_r5fss1_core0 {
- mboxes = <&mailbox0_cluster4>, <&mbox_main_r5fss1_core0>;
- memory-region = <&main_r5fss1_core0_dma_memory_region>,
- <&main_r5fss1_core0_memory_region>;
-};
-
-&main_r5fss1_core1 {
- mboxes = <&mailbox0_cluster4>, <&mbox_main_r5fss1_core1>;
- memory-region = <&main_r5fss1_core1_dma_memory_region>,
- <&main_r5fss1_core1_memory_region>;
-};
-
-&ecap0 {
- status = "okay";
- /* PWM is available on Pin 1 of header J3 */
- pinctrl-names = "default";
- pinctrl-0 = <&main_ecap0_pins_default>;
-};
diff --git a/arch/arm/dts/k3-am64x-binman.dtsi b/arch/arm/dts/k3-am64x-binman.dtsi
index 88df214..37817ba 100644
--- a/arch/arm/dts/k3-am64x-binman.dtsi
+++ b/arch/arm/dts/k3-am64x-binman.dtsi
@@ -118,11 +118,11 @@
#ifdef CONFIG_TARGET_AM642_A53_EVM
-#define SPL_AM642_EVM_DTB "spl/dts/k3-am642-evm.dtb"
-#define SPL_AM642_SK_DTB "spl/dts/k3-am642-sk.dtb"
+#define SPL_AM642_EVM_DTB "spl/dts/ti/k3-am642-evm.dtb"
+#define SPL_AM642_SK_DTB "spl/dts/ti/k3-am642-sk.dtb"
#define AM642_EVM_DTB "u-boot.dtb"
-#define AM642_SK_DTB "arch/arm/dts/k3-am642-sk.dtb"
+#define AM642_SK_DTB "dts/upstream/src/arm64/ti/k3-am642-sk.dtb"
&binman {
ti-spl {
diff --git a/arch/arm/dts/k3-j7200-common-proc-board-u-boot.dtsi b/arch/arm/dts/k3-j7200-common-proc-board-u-boot.dtsi
index 60ca6d2..c9fee0e 100644
--- a/arch/arm/dts/k3-j7200-common-proc-board-u-boot.dtsi
+++ b/arch/arm/dts/k3-j7200-common-proc-board-u-boot.dtsi
@@ -195,6 +195,10 @@
&ospi0 {
bootph-all;
+
+ flash@0 {
+ bootph-all;
+ };
};
&serdes_ln_ctrl {
diff --git a/arch/arm/dts/k3-j7200-r5-common-proc-board.dts b/arch/arm/dts/k3-j7200-r5-common-proc-board.dts
index 018faaa..fb7e2e5 100644
--- a/arch/arm/dts/k3-j7200-r5-common-proc-board.dts
+++ b/arch/arm/dts/k3-j7200-r5-common-proc-board.dts
@@ -52,7 +52,7 @@
};
&mcu_timer0 {
- clock-frequency = <25000000>;
+ clock-frequency = <250000000>;
bootph-pre-ram;
};
@@ -83,3 +83,16 @@
&wkup_vtm0 {
bootph-pre-ram;
};
+
+&ospi0 {
+ reg = <0x0 0x47040000 0x0 0x100>,
+ <0x0 0x50000000 0x0 0x8000000>;
+};
+
+&mcu_ringacc {
+ ti,sci = <&dm_tifs>;
+};
+
+&mcu_udmap {
+ ti,sci = <&dm_tifs>;
+};
diff --git a/arch/arm/dts/kirkwood-6192.dtsi b/arch/arm/dts/kirkwood-6192.dtsi
deleted file mode 100644
index 396bcba..0000000
--- a/arch/arm/dts/kirkwood-6192.dtsi
+++ /dev/null
@@ -1,88 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0
-/ {
- mbus@f1000000 {
- pciec: pcie@82000000 {
- compatible = "marvell,kirkwood-pcie";
- status = "disabled";
- device_type = "pci";
-
- #address-cells = <3>;
- #size-cells = <2>;
-
- bus-range = <0x00 0xff>;
-
- ranges =
- <0x82000000 0 0x40000 MBUS_ID(0xf0, 0x01) 0x40000 0 0x00002000
- 0x82000000 0x1 0 MBUS_ID(0x04, 0xe8) 0 1 0 /* Port 0.0 MEM */
- 0x81000000 0x1 0 MBUS_ID(0x04, 0xe0) 0 1 0 /* Port 0.0 IO */>;
-
- pcie0: pcie@1,0 {
- device_type = "pci";
- assigned-addresses = <0x82000800 0 0x00040000 0 0x2000>;
- reg = <0x0800 0 0 0 0>;
- #address-cells = <3>;
- #size-cells = <2>;
- #interrupt-cells = <1>;
- ranges = <0x82000000 0 0 0x82000000 0x1 0 1 0
- 0x81000000 0 0 0x81000000 0x1 0 1 0>;
- bus-range = <0x00 0xff>;
- interrupt-map-mask = <0 0 0 0>;
- interrupt-map = <0 0 0 0 &intc 9>;
- marvell,pcie-port = <0>;
- marvell,pcie-lane = <0>;
- clocks = <&gate_clk 2>;
- status = "disabled";
- };
- };
- };
-
- ocp@f1000000 {
- pinctrl: pin-controller@10000 {
- compatible = "marvell,88f6192-pinctrl";
-
- pmx_sata0: pmx-sata0 {
- marvell,pins = "mpp5", "mpp21", "mpp23";
- marvell,function = "sata0";
- };
- pmx_sata1: pmx-sata1 {
- marvell,pins = "mpp4", "mpp20", "mpp22";
- marvell,function = "sata1";
- };
- pmx_sdio: pmx-sdio {
- marvell,pins = "mpp12", "mpp13", "mpp14",
- "mpp15", "mpp16", "mpp17";
- marvell,function = "sdio";
- };
- };
-
- rtc: rtc@10300 {
- compatible = "marvell,kirkwood-rtc", "marvell,orion-rtc";
- reg = <0x10300 0x20>;
- interrupts = <53>;
- clocks = <&gate_clk 7>;
- };
-
- sata: sata@80000 {
- compatible = "marvell,orion-sata";
- reg = <0x80000 0x5000>;
- interrupts = <21>;
- clocks = <&gate_clk 14>, <&gate_clk 15>;
- clock-names = "0", "1";
- phys = <&sata_phy0>, <&sata_phy1>;
- phy-names = "port0", "port1";
- status = "disabled";
- };
-
- sdio: mvsdio@90000 {
- compatible = "marvell,orion-sdio";
- reg = <0x90000 0x200>;
- interrupts = <28>;
- clocks = <&gate_clk 4>;
- bus-width = <4>;
- cap-sdio-irq;
- cap-sd-highspeed;
- cap-mmc-highspeed;
- status = "disabled";
- };
- };
-};
diff --git a/arch/arm/dts/kirkwood-6281.dtsi b/arch/arm/dts/kirkwood-6281.dtsi
deleted file mode 100644
index faa0584..0000000
--- a/arch/arm/dts/kirkwood-6281.dtsi
+++ /dev/null
@@ -1,90 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0
-/ {
- mbus@f1000000 {
- pciec: pcie@82000000 {
- compatible = "marvell,kirkwood-pcie";
- status = "disabled";
- device_type = "pci";
-
- #address-cells = <3>;
- #size-cells = <2>;
-
- bus-range = <0x00 0xff>;
-
- ranges =
- <0x82000000 0 0x40000 MBUS_ID(0xf0, 0x01) 0x40000 0 0x00002000
- 0x82000000 0x1 0 MBUS_ID(0x04, 0xe8) 0 1 0 /* Port 0.0 MEM */
- 0x81000000 0x1 0 MBUS_ID(0x04, 0xe0) 0 1 0 /* Port 0.0 IO */>;
-
- pcie0: pcie@1,0 {
- device_type = "pci";
- assigned-addresses = <0x82000800 0 0x00040000 0 0x2000>;
- reg = <0x0800 0 0 0 0>;
- #address-cells = <3>;
- #size-cells = <2>;
- #interrupt-cells = <1>;
- ranges = <0x82000000 0 0 0x82000000 0x1 0 1 0
- 0x81000000 0 0 0x81000000 0x1 0 1 0>;
- bus-range = <0x00 0xff>;
- interrupt-map-mask = <0 0 0 0>;
- interrupt-map = <0 0 0 0 &intc 9>;
- marvell,pcie-port = <0>;
- marvell,pcie-lane = <0>;
- clocks = <&gate_clk 2>;
- status = "disabled";
- };
- };
- };
-
- ocp@f1000000 {
- pinctrl: pin-controller@10000 {
- compatible = "marvell,88f6281-pinctrl";
-
- pmx_sata0: pmx-sata0 {
- marvell,pins = "mpp5", "mpp21", "mpp23";
- marvell,function = "sata0";
- };
- pmx_sata1: pmx-sata1 {
- marvell,pins = "mpp4", "mpp20", "mpp22";
- marvell,function = "sata1";
- };
- pmx_sdio: pmx-sdio {
- marvell,pins = "mpp12", "mpp13", "mpp14",
- "mpp15", "mpp16", "mpp17";
- marvell,function = "sdio";
- };
- };
-
- rtc: rtc@10300 {
- compatible = "marvell,kirkwood-rtc", "marvell,orion-rtc";
- reg = <0x10300 0x20>;
- interrupts = <53>;
- clocks = <&gate_clk 7>;
- };
-
- sata: sata@80000 {
- compatible = "marvell,orion-sata";
- reg = <0x80000 0x5000>;
- interrupts = <21>;
- clocks = <&gate_clk 14>, <&gate_clk 15>;
- clock-names = "0", "1";
- phys = <&sata_phy0>, <&sata_phy1>;
- phy-names = "port0", "port1";
- status = "disabled";
- };
-
- sdio: mvsdio@90000 {
- compatible = "marvell,orion-sdio";
- reg = <0x90000 0x200>;
- interrupts = <28>;
- clocks = <&gate_clk 4>;
- pinctrl-0 = <&pmx_sdio>;
- pinctrl-names = "default";
- bus-width = <4>;
- cap-sdio-irq;
- cap-sd-highspeed;
- cap-mmc-highspeed;
- status = "disabled";
- };
- };
-};
diff --git a/arch/arm/dts/kirkwood-6282.dtsi b/arch/arm/dts/kirkwood-6282.dtsi
deleted file mode 100644
index e732c50..0000000
--- a/arch/arm/dts/kirkwood-6282.dtsi
+++ /dev/null
@@ -1,161 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0
-/ {
- mbus@f1000000 {
- pciec: pcie@82000000 {
- compatible = "marvell,kirkwood-pcie";
- status = "disabled";
- device_type = "pci";
-
- #address-cells = <3>;
- #size-cells = <2>;
-
- bus-range = <0x00 0xff>;
-
- ranges =
- <0x82000000 0 0x40000 MBUS_ID(0xf0, 0x01) 0x40000 0 0x00002000
- 0x82000000 0 0x44000 MBUS_ID(0xf0, 0x01) 0x44000 0 0x00002000
- 0x82000000 0 0x80000 MBUS_ID(0xf0, 0x01) 0x80000 0 0x00002000
- 0x82000000 0x1 0 MBUS_ID(0x04, 0xe8) 0 1 0 /* Port 0.0 MEM */
- 0x81000000 0x1 0 MBUS_ID(0x04, 0xe0) 0 1 0 /* Port 0.0 IO */
- 0x82000000 0x2 0 MBUS_ID(0x04, 0xd8) 0 1 0 /* Port 1.0 MEM */
- 0x81000000 0x2 0 MBUS_ID(0x04, 0xd0) 0 1 0 /* Port 1.0 IO */>;
-
- pcie0: pcie@1,0 {
- device_type = "pci";
- assigned-addresses = <0x82000800 0 0x00040000 0 0x2000>;
- reg = <0x0800 0 0 0 0>;
- #address-cells = <3>;
- #size-cells = <2>;
- #interrupt-cells = <1>;
- ranges = <0x82000000 0 0 0x82000000 0x1 0 1 0
- 0x81000000 0 0 0x81000000 0x1 0 1 0>;
- bus-range = <0x00 0xff>;
- interrupt-names = "intx", "error";
- interrupts = <9>, <44>;
- interrupt-map-mask = <0 0 0 7>;
- interrupt-map = <0 0 0 1 &pcie0_intc 0>,
- <0 0 0 2 &pcie0_intc 1>,
- <0 0 0 3 &pcie0_intc 2>,
- <0 0 0 4 &pcie0_intc 3>;
- marvell,pcie-port = <0>;
- marvell,pcie-lane = <0>;
- clocks = <&gate_clk 2>;
- status = "disabled";
-
- pcie0_intc: interrupt-controller {
- interrupt-controller;
- #interrupt-cells = <1>;
- };
- };
-
- pcie1: pcie@2,0 {
- device_type = "pci";
- assigned-addresses = <0x82001000 0 0x00044000 0 0x2000>;
- reg = <0x1000 0 0 0 0>;
- #address-cells = <3>;
- #size-cells = <2>;
- #interrupt-cells = <1>;
- ranges = <0x82000000 0 0 0x82000000 0x2 0 1 0
- 0x81000000 0 0 0x81000000 0x2 0 1 0>;
- bus-range = <0x00 0xff>;
- interrupt-names = "intx", "error";
- interrupts = <10>, <45>;
- interrupt-map-mask = <0 0 0 7>;
- interrupt-map = <0 0 0 1 &pcie1_intc 0>,
- <0 0 0 2 &pcie1_intc 1>,
- <0 0 0 3 &pcie1_intc 2>,
- <0 0 0 4 &pcie1_intc 3>;
- marvell,pcie-port = <1>;
- marvell,pcie-lane = <0>;
- clocks = <&gate_clk 18>;
- status = "disabled";
-
- pcie1_intc: interrupt-controller {
- interrupt-controller;
- #interrupt-cells = <1>;
- };
- };
- };
- };
- ocp@f1000000 {
-
- pinctrl: pin-controller@10000 {
- compatible = "marvell,88f6282-pinctrl";
-
- pmx_sata0: pmx-sata0 {
- marvell,pins = "mpp5", "mpp21", "mpp23";
- marvell,function = "sata0";
- };
- pmx_sata1: pmx-sata1 {
- marvell,pins = "mpp4", "mpp20", "mpp22";
- marvell,function = "sata1";
- };
-
- /*
- * Default I2C1 pinctrl setting on mpp36/mpp37,
- * overwrite marvell,pins on board level if required.
- */
- pmx_twsi1: pmx-twsi1 {
- marvell,pins = "mpp36", "mpp37";
- marvell,function = "twsi1";
- };
-
- pmx_sdio: pmx-sdio {
- marvell,pins = "mpp12", "mpp13", "mpp14",
- "mpp15", "mpp16", "mpp17";
- marvell,function = "sdio";
- };
- };
-
- thermal: thermal@10078 {
- compatible = "marvell,kirkwood-thermal";
- reg = <0x10078 0x4>;
- status = "okay";
- };
-
- rtc: rtc@10300 {
- compatible = "marvell,kirkwood-rtc", "marvell,orion-rtc";
- reg = <0x10300 0x20>;
- interrupts = <53>;
- clocks = <&gate_clk 7>;
- };
-
- i2c1: i2c@11100 {
- compatible = "marvell,mv64xxx-i2c";
- reg = <0x11100 0x20>;
- #address-cells = <1>;
- #size-cells = <0>;
- interrupts = <32>;
- clock-frequency = <100000>;
- clocks = <&gate_clk 7>;
- pinctrl-0 = <&pmx_twsi1>;
- pinctrl-names = "default";
- status = "disabled";
- };
-
- sata: sata@80000 {
- compatible = "marvell,orion-sata";
- reg = <0x80000 0x5000>;
- interrupts = <21>;
- clocks = <&gate_clk 14>, <&gate_clk 15>;
- clock-names = "0", "1";
- phys = <&sata_phy0>, <&sata_phy1>;
- phy-names = "port0", "port1";
- status = "disabled";
- };
-
- sdio: mvsdio@90000 {
- compatible = "marvell,orion-sdio";
- reg = <0x90000 0x200>;
- interrupts = <28>;
- clocks = <&gate_clk 4>;
- pinctrl-0 = <&pmx_sdio>;
- pinctrl-names = "default";
- bus-width = <4>;
- cap-sdio-irq;
- cap-sd-highspeed;
- cap-mmc-highspeed;
- status = "disabled";
- };
- };
-};
diff --git a/arch/arm/dts/kirkwood-98dx4122.dtsi b/arch/arm/dts/kirkwood-98dx4122.dtsi
deleted file mode 100644
index 299c147..0000000
--- a/arch/arm/dts/kirkwood-98dx4122.dtsi
+++ /dev/null
@@ -1,53 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0
-/ {
- mbus@f1000000 {
- pciec: pcie@82000000 {
- compatible = "marvell,kirkwood-pcie";
- status = "disabled";
- device_type = "pci";
-
- #address-cells = <3>;
- #size-cells = <2>;
-
- bus-range = <0x00 0xff>;
-
- ranges =
- <0x82000000 0 0x40000 MBUS_ID(0xf0, 0x01) 0x40000 0 0x00002000
- 0x82000000 0x1 0 MBUS_ID(0x04, 0xe8) 0 1 0 /* Port 0.0 MEM */
- 0x81000000 0x1 0 MBUS_ID(0x04, 0xe0) 0 1 0 /* Port 0.0 IO */>;
-
- pcie0: pcie@1,0 {
- device_type = "pci";
- assigned-addresses = <0x82000800 0 0x00040000 0 0x2000>;
- reg = <0x0800 0 0 0 0>;
- #address-cells = <3>;
- #size-cells = <2>;
- #interrupt-cells = <1>;
- ranges = <0x82000000 0 0 0x82000000 0x1 0 1 0
- 0x81000000 0 0 0x81000000 0x1 0 1 0>;
- bus-range = <0x00 0xff>;
- interrupt-map-mask = <0 0 0 0>;
- interrupt-map = <0 0 0 0 &intc 9>;
- marvell,pcie-port = <0>;
- marvell,pcie-lane = <0>;
- clocks = <&gate_clk 2>;
- status = "disabled";
- };
- };
- };
-
- ocp@f1000000 {
- pinctrl: pin-controller@10000 {
- compatible = "marvell,98dx4122-pinctrl";
-
- };
- };
-};
-
-&sata_phy0 {
- status = "disabled";
-};
-
-&sata_phy1 {
- status = "disabled";
-};
diff --git a/arch/arm/dts/kirkwood-blackarmor-nas220.dts b/arch/arm/dts/kirkwood-blackarmor-nas220.dts
deleted file mode 100644
index 07fbfca..0000000
--- a/arch/arm/dts/kirkwood-blackarmor-nas220.dts
+++ /dev/null
@@ -1,172 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * Device Tree file for Seagate Blackarmor NAS220
- *
- * Copyright (C) 2014 Evgeni Dobrev <evgeni@studio-punkt.com>
- */
-
-/dts-v1/;
-
-#include <dt-bindings/gpio/gpio.h>
-#include <dt-bindings/input/input.h>
-#include "kirkwood.dtsi"
-#include "kirkwood-6192.dtsi"
-
-/ {
- model = "Seagate Blackarmor NAS220";
- compatible = "seagate,blackarmor-nas220","marvell,kirkwood-88f6192",
- "marvell,kirkwood";
-
- memory { /* 128 MB */
- device_type = "memory";
- reg = <0x00000000 0x8000000>;
- };
-
- chosen {
- bootargs = "console=ttyS0,115200n8";
- stdout-path = &uart0;
- };
-
- gpio_poweroff {
- compatible = "gpio-poweroff";
- gpios = <&gpio0 14 GPIO_ACTIVE_LOW>;
- };
-
- gpio_keys {
- compatible = "gpio-keys";
-
- reset {
- label = "Reset";
- linux,code = <KEY_POWER>;
- gpios = <&gpio0 29 GPIO_ACTIVE_HIGH>;
- };
-
- button {
- label = "Power";
- linux,code = <KEY_SLEEP>;
- gpios = <&gpio0 26 GPIO_ACTIVE_LOW>;
- };
- };
-
- gpio-leds {
- compatible = "gpio-leds";
-
- blue-power {
- label = "nas220:blue:power";
- gpios = <&gpio0 12 GPIO_ACTIVE_HIGH>;
- linux,default-trigger = "default-on";
- };
- };
-
- regulators {
- compatible = "simple-bus";
- #address-cells = <1>;
- #size-cells = <0>;
- pinctrl-0 = <&pmx_power_sata0 &pmx_power_sata1>;
- pinctrl-names = "default";
-
- sata0_power: regulator@1 {
- compatible = "regulator-fixed";
- reg = <1>;
- regulator-name = "SATA0 Power";
- regulator-min-microvolt = <5000000>;
- regulator-max-microvolt = <5000000>;
- enable-active-high;
- regulator-always-on;
- regulator-boot-on;
- gpio = <&gpio0 24 GPIO_ACTIVE_LOW>;
- };
-
- sata1_power: regulator@2 {
- compatible = "regulator-fixed";
- reg = <2>;
- regulator-name = "SATA1 Power";
- regulator-min-microvolt = <5000000>;
- regulator-max-microvolt = <5000000>;
- enable-active-high;
- regulator-always-on;
- regulator-boot-on;
- gpio = <&gpio0 28 GPIO_ACTIVE_LOW>;
- };
- };
-};
-
-/*
- * Serial port routed to connector CN5
- *
- * pin 1 - TX (CPU's TX)
- * pin 4 - RX (CPU's RX)
- * pin 6 - GND
- */
-&uart0 {
- status = "okay";
-};
-
-&pinctrl {
- pinctrl-0 = <&pmx_button_reset &pmx_button_power>;
- pinctrl-names = "default";
-
- pmx_act_sata0: pmx-act-sata0 {
- marvell,pins = "mpp15";
- marvell,function = "sata0";
- };
-
- pmx_act_sata1: pmx-act-sata1 {
- marvell,pins = "mpp16";
- marvell,function = "sata1";
- };
-
- pmx_power_sata0: pmx-power-sata0 {
- marvell,pins = "mpp24";
- marvell,function = "gpio";
- };
-
- pmx_power_sata1: pmx-power-sata1 {
- marvell,pins = "mpp28";
- marvell,function = "gpio";
- };
-
- pmx_button_reset: pmx-button-reset {
- marvell,pins = "mpp29";
- marvell,function = "gpio";
- };
-
- pmx_button_power: pmx-button-power {
- marvell,pins = "mpp26";
- marvell,function = "gpio";
- };
-};
-
-&sata {
- status = "okay";
- nr-ports = <2>;
-};
-
-&i2c0 {
- status = "okay";
-
- adt7476: thermal@2e {
- compatible = "adi,adt7476";
- reg = <0x2e>;
- };
-};
-
-&nand {
- status = "okay";
-};
-
-&mdio {
- status = "okay";
-
- ethphy0: ethernet-phy@8 {
- reg = <8>;
- };
-};
-
-ð0 {
- status = "okay";
-
- ethernet0-port@0 {
- phy-handle = <ðphy0>;
- };
-};
diff --git a/arch/arm/dts/kirkwood-d2net.dts b/arch/arm/dts/kirkwood-d2net.dts
deleted file mode 100644
index bd3b266..0000000
--- a/arch/arm/dts/kirkwood-d2net.dts
+++ /dev/null
@@ -1,45 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0
-/*
- * Device Tree file for d2 Network v2
- *
- * Copyright (C) 2014 Simon Guinot <simon.guinot@sequanux.org>
- *
-*/
-
-/dts-v1/;
-
-#include <dt-bindings/leds/leds-ns2.h>
-#include "kirkwood-netxbig.dtsi"
-
-/ {
- model = "LaCie d2 Network v2";
- compatible = "lacie,d2net_v2", "lacie,netxbig", "marvell,kirkwood-88f6281", "marvell,kirkwood";
-
- memory {
- device_type = "memory";
- reg = <0x00000000 0x10000000>;
- };
-
- ns2-leds {
- compatible = "lacie,ns2-leds";
-
- blue-sata {
- label = "d2net_v2:blue:sata";
- slow-gpio = <&gpio0 29 GPIO_ACTIVE_HIGH>;
- cmd-gpio = <&gpio0 30 GPIO_ACTIVE_HIGH>;
- modes-map = <NS_V2_LED_OFF 1 0
- NS_V2_LED_ON 0 1
- NS_V2_LED_ON 1 1
- NS_V2_LED_SATA 0 0>;
- };
- };
-
- gpio-leds {
- compatible = "gpio-leds";
-
- red-fail {
- label = "d2net_v2:red:fail";
- gpios = <&gpio0 12 GPIO_ACTIVE_HIGH>;
- };
- };
-};
diff --git a/arch/arm/dts/kirkwood-dns325.dts b/arch/arm/dts/kirkwood-dns325.dts
deleted file mode 100644
index 94d9c06..0000000
--- a/arch/arm/dts/kirkwood-dns325.dts
+++ /dev/null
@@ -1,63 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0
-/dts-v1/;
-
-#include "kirkwood-dnskw.dtsi"
-
-/ {
- model = "D-Link DNS-325 NAS (Rev A1)";
- compatible = "dlink,dns-325-a1", "dlink,dns-325", "dlink,dns-kirkwood", "marvell,kirkwood-88f6281", "marvell,kirkwood";
-
- memory {
- device_type = "memory";
- reg = <0x00000000 0x10000000>;
- };
-
- chosen {
- bootargs = "console=ttyS0,115200n8 earlyprintk";
- stdout-path = &uart0;
- };
-
- gpio-leds {
- compatible = "gpio-leds";
- pinctrl-0 = <&pmx_led_power &pmx_led_red_usb_325
- &pmx_led_red_left_hdd &pmx_led_red_right_hdd
- &pmx_led_white_usb>;
- pinctrl-names = "default";
-
- white-power {
- label = "dns325:white:power";
- gpios = <&gpio0 26 GPIO_ACTIVE_LOW>;
- default-state = "keep";
- };
- white-usb {
- label = "dns325:white:usb";
- gpios = <&gpio1 11 GPIO_ACTIVE_LOW>; /* GPIO 43 */
- };
- red-l_hdd {
- label = "dns325:red:l_hdd";
- gpios = <&gpio0 28 GPIO_ACTIVE_LOW>;
- };
- red-r_hdd {
- label = "dns325:red:r_hdd";
- gpios = <&gpio0 27 GPIO_ACTIVE_LOW>;
- };
- red-usb {
- label = "dns325:red:usb";
- gpios = <&gpio0 29 GPIO_ACTIVE_LOW>;
- };
- };
-
- ocp@f1000000 {
- i2c@11000 {
- status = "okay";
-
- lm75: lm75@48 {
- compatible = "national,lm75";
- reg = <0x48>;
- };
- };
- serial@12000 {
- status = "okay";
- };
- };
-};
diff --git a/arch/arm/dts/kirkwood-dnskw.dtsi b/arch/arm/dts/kirkwood-dnskw.dtsi
deleted file mode 100644
index cbaf06f..0000000
--- a/arch/arm/dts/kirkwood-dnskw.dtsi
+++ /dev/null
@@ -1,235 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0
-#include "kirkwood.dtsi"
-#include "kirkwood-6281.dtsi"
-
-/ {
- model = "D-Link DNS NASes (kirkwood-based)";
- compatible = "dlink,dns-kirkwood", "marvell,kirkwood-88f6281", "marvell,kirkwood";
-
- gpio_keys {
- compatible = "gpio-keys";
- #address-cells = <1>;
- #size-cells = <0>;
- pinctrl-0 = <&pmx_button_power &pmx_button_unmount
- &pmx_button_reset>;
- pinctrl-names = "default";
-
- power {
- label = "Power button";
- linux,code = <KEY_POWER>;
- gpios = <&gpio1 2 GPIO_ACTIVE_LOW>;
- };
- eject {
- label = "USB unmount button";
- linux,code = <KEY_EJECTCD>;
- gpios = <&gpio1 15 GPIO_ACTIVE_LOW>;
- };
- reset {
- label = "Reset button";
- linux,code = <KEY_RESTART>;
- gpios = <&gpio1 16 GPIO_ACTIVE_LOW>;
- };
- };
-
- gpio_fan {
- /* Fan: ADDA AD045HB-G73 40mm 6000rpm@5v */
- compatible = "gpio-fan";
- pinctrl-0 = <&pmx_fan_high_speed &pmx_fan_low_speed>;
- pinctrl-names = "default";
- gpios = <&gpio1 14 GPIO_ACTIVE_LOW
- &gpio1 13 GPIO_ACTIVE_LOW>;
- gpio-fan,speed-map = <0 0
- 3000 1
- 6000 2>;
- };
-
- gpio_poweroff {
- compatible = "gpio-poweroff";
- pinctrl-0 = <&pmx_power_off>;
- pinctrl-names = "default";
- gpios = <&gpio1 4 GPIO_ACTIVE_HIGH>;
- };
-
- ocp@f1000000 {
- pinctrl: pin-controller@10000 {
-
- pinctrl-0 = <&pmx_power_back_on &pmx_present_sata0
- &pmx_present_sata1 &pmx_fan_tacho
- &pmx_temp_alarm>;
- pinctrl-names = "default";
-
- pmx_sata0: pmx-sata0 {
- marvell,pins = "mpp20";
- marvell,function = "sata1";
- };
- pmx_sata1: pmx-sata1 {
- marvell,pins = "mpp21";
- marvell,function = "sata0";
- };
- pmx_led_power: pmx-led-power {
- marvell,pins = "mpp26";
- marvell,function = "gpio";
- };
- pmx_led_red_right_hdd: pmx-led-red-right-hdd {
- marvell,pins = "mpp27";
- marvell,function = "gpio";
- };
- pmx_led_red_left_hdd: pmx-led-red-left-hdd {
- marvell,pins = "mpp28";
- marvell,function = "gpio";
- };
- pmx_led_red_usb_325: pmx-led-red-usb-325 {
- marvell,pins = "mpp29";
- marvell,function = "gpio";
- };
- pmx_button_power: pmx-button-power {
- marvell,pins = "mpp34";
- marvell,function = "gpio";
- };
- pmx_led_red_usb_320: pmx-led-red-usb-320 {
- marvell,pins = "mpp35";
- marvell,function = "gpio";
- };
- pmx_power_off: pmx-power-off {
- marvell,pins = "mpp36";
- marvell,function = "gpio";
- };
- pmx_power_back_on: pmx-power-back-on {
- marvell,pins = "mpp37";
- marvell,function = "gpio";
- };
- pmx_power_sata0: pmx-power-sata0 {
- marvell,pins = "mpp39";
- marvell,function = "gpio";
- };
- pmx_power_sata1: pmx-power-sata1 {
- marvell,pins = "mpp40";
- marvell,function = "gpio";
- };
- pmx_present_sata0: pmx-present-sata0 {
- marvell,pins = "mpp41";
- marvell,function = "gpio";
- };
- pmx_present_sata1: pmx-present-sata1 {
- marvell,pins = "mpp42";
- marvell,function = "gpio";
- };
- pmx_led_white_usb: pmx-led-white-usb {
- marvell,pins = "mpp43";
- marvell,function = "gpio";
- };
- pmx_fan_tacho: pmx-fan-tacho {
- marvell,pins = "mpp44";
- marvell,function = "gpio";
- };
- pmx_fan_high_speed: pmx-fan-high-speed {
- marvell,pins = "mpp45";
- marvell,function = "gpio";
- };
- pmx_fan_low_speed: pmx-fan-low-speed {
- marvell,pins = "mpp46";
- marvell,function = "gpio";
- };
- pmx_button_unmount: pmx-button-unmount {
- marvell,pins = "mpp47";
- marvell,function = "gpio";
- };
- pmx_button_reset: pmx-button-reset {
- marvell,pins = "mpp48";
- marvell,function = "gpio";
- };
- pmx_temp_alarm: pmx-temp-alarm {
- marvell,pins = "mpp49";
- marvell,function = "gpio";
- };
- };
- sata@80000 {
- pinctrl-0 = <&pmx_sata0 &pmx_sata1>;
- pinctrl-names = "default";
- status = "okay";
- nr-ports = <2>;
- };
- };
-
- regulators {
- compatible = "simple-bus";
- #address-cells = <1>;
- #size-cells = <0>;
- pinctrl-0 = <&pmx_power_sata0 &pmx_power_sata1>;
- pinctrl-names = "default";
-
- sata0_power: regulator@1 {
- compatible = "regulator-fixed";
- reg = <1>;
- regulator-name = "SATA0 Power";
- regulator-min-microvolt = <5000000>;
- regulator-max-microvolt = <5000000>;
- enable-active-high;
- regulator-always-on;
- regulator-boot-on;
- gpio = <&gpio1 7 0>;
- };
- sata1_power: regulator@2 {
- compatible = "regulator-fixed";
- reg = <2>;
- regulator-name = "SATA1 Power";
- regulator-min-microvolt = <5000000>;
- regulator-max-microvolt = <5000000>;
- enable-active-high;
- regulator-always-on;
- regulator-boot-on;
- gpio = <&gpio1 8 0>;
- };
- };
-};
-
-&nand {
- status = "okay";
- chip-delay = <35>;
-
- partition@0 {
- label = "u-boot";
- reg = <0x0000000 0x100000>;
- read-only;
- };
-
- partition@100000 {
- label = "uImage";
- reg = <0x0100000 0x500000>;
- };
-
- partition@600000 {
- label = "ramdisk";
- reg = <0x0600000 0x500000>;
- };
-
- partition@b00000 {
- label = "image";
- reg = <0x0b00000 0x6600000>;
- };
-
- partition@7100000 {
- label = "mini firmware";
- reg = <0x7100000 0xa00000>;
- };
-
- partition@7b00000 {
- label = "config";
- reg = <0x7b00000 0x500000>;
- };
-};
-
-&mdio {
- status = "okay";
-
- ethphy0: ethernet-phy@8 {
- reg = <8>;
- };
-};
-
-ð0 {
- status = "okay";
- ethernet0-port@0 {
- phy-handle = <ðphy0>;
- };
-};
diff --git a/arch/arm/dts/kirkwood-dockstar.dts b/arch/arm/dts/kirkwood-dockstar.dts
deleted file mode 100644
index 6a3f1bf..0000000
--- a/arch/arm/dts/kirkwood-dockstar.dts
+++ /dev/null
@@ -1,110 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0
-/dts-v1/;
-
-#include "kirkwood.dtsi"
-#include "kirkwood-6281.dtsi"
-
-/ {
- model = "Seagate FreeAgent Dockstar";
- compatible = "seagate,dockstar", "marvell,kirkwood-88f6281", "marvell,kirkwood";
-
- memory {
- device_type = "memory";
- reg = <0x00000000 0x8000000>;
- };
-
- chosen {
- bootargs = "console=ttyS0,115200n8 earlyprintk root=/dev/sda1 rootdelay=10";
- stdout-path = &uart0;
- };
-
- ocp@f1000000 {
- pinctrl: pin-controller@10000 {
- pmx_usb_power_enable: pmx-usb-power-enable {
- marvell,pins = "mpp29";
- marvell,function = "gpio";
- };
- pmx_led_green: pmx-led-green {
- marvell,pins = "mpp46";
- marvell,function = "gpio";
- };
- pmx_led_orange: pmx-led-orange {
- marvell,pins = "mpp47";
- marvell,function = "gpio";
- };
- };
- serial@12000 {
- status = "ok";
- };
- };
- gpio-leds {
- compatible = "gpio-leds";
- pinctrl-0 = <&pmx_led_green &pmx_led_orange>;
- pinctrl-names = "default";
-
- health {
- label = "status:green:health";
- gpios = <&gpio1 14 GPIO_ACTIVE_LOW>;
- default-state = "keep";
- };
- fault {
- label = "status:orange:fault";
- gpios = <&gpio1 15 GPIO_ACTIVE_LOW>;
- };
- };
- regulators {
- compatible = "simple-bus";
- #address-cells = <1>;
- #size-cells = <0>;
- pinctrl-0 = <&pmx_usb_power_enable>;
- pinctrl-names = "default";
-
- usb_power: regulator@1 {
- compatible = "regulator-fixed";
- reg = <1>;
- regulator-name = "USB Power";
- regulator-min-microvolt = <5000000>;
- regulator-max-microvolt = <5000000>;
- enable-active-high;
- regulator-always-on;
- regulator-boot-on;
- gpio = <&gpio0 29 0>;
- };
- };
-};
-
-&nand {
- status = "okay";
-
- partition@0 {
- label = "u-boot";
- reg = <0x0000000 0x100000>;
- read-only;
- };
-
- partition@100000 {
- label = "uImage";
- reg = <0x0100000 0x400000>;
- };
-
- partition@500000 {
- label = "data";
- reg = <0x0500000 0xfb00000>;
- };
-};
-
-&mdio {
- status = "okay";
-
- ethphy0: ethernet-phy@0 {
- compatible = "marvell,88e1116";
- reg = <0>;
- };
-};
-
-ð0 {
- status = "okay";
- ethernet0-port@0 {
- phy-handle = <ðphy0>;
- };
-};
diff --git a/arch/arm/dts/kirkwood-dreamplug-u-boot.dtsi b/arch/arm/dts/kirkwood-dreamplug-u-boot.dtsi
new file mode 100644
index 0000000..59f19a2
--- /dev/null
+++ b/arch/arm/dts/kirkwood-dreamplug-u-boot.dtsi
@@ -0,0 +1,7 @@
+// SPDX-License-Identifier: GPL-2.0+
+
+/ {
+ aliases {
+ spi0 = &spi0;
+ };
+};
diff --git a/arch/arm/dts/kirkwood-dreamplug.dts b/arch/arm/dts/kirkwood-dreamplug.dts
deleted file mode 100644
index e9eea22..0000000
--- a/arch/arm/dts/kirkwood-dreamplug.dts
+++ /dev/null
@@ -1,131 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0
-/dts-v1/;
-
-#include "kirkwood.dtsi"
-#include "kirkwood-6281.dtsi"
-
-/ {
- model = "Globalscale Technologies Dreamplug";
- compatible = "globalscale,dreamplug-003-ds2001", "globalscale,dreamplug", "marvell,kirkwood-88f6281", "marvell,kirkwood";
-
- memory {
- device_type = "memory";
- reg = <0x00000000 0x20000000>;
- };
-
- chosen {
- bootargs = "console=ttyS0,115200n8 earlyprintk";
- stdout-path = &uart0;
- };
-
- aliases {
- spi0 = &spi0;
- };
-
- ocp@f1000000 {
- pinctrl: pin-controller@10000 {
- pmx_led_bluetooth: pmx-led-bluetooth {
- marvell,pins = "mpp47";
- marvell,function = "gpio";
- };
- pmx_led_wifi: pmx-led-wifi {
- marvell,pins = "mpp48";
- marvell,function = "gpio";
- };
- pmx_led_wifi_ap: pmx-led-wifi-ap {
- marvell,pins = "mpp49";
- marvell,function = "gpio";
- };
- };
- serial@12000 {
- status = "ok";
- };
-
- spi@10600 {
- status = "okay";
-
- m25p40@0 {
- #address-cells = <1>;
- #size-cells = <1>;
- compatible = "mxicy,mx25l1606e", "jedec,spi-nor";
- reg = <0>;
- spi-max-frequency = <50000000>;
- mode = <0>;
-
- partition@0 {
- reg = <0x0 0x80000>;
- label = "u-boot";
- };
-
- partition@100000 {
- reg = <0x100000 0x10000>;
- label = "u-boot env";
- };
-
- partition@180000 {
- reg = <0x180000 0x10000>;
- label = "dtb";
- };
- };
- };
-
- sata@80000 {
- status = "okay";
- nr-ports = <1>;
- };
-
- mvsdio@90000 {
- pinctrl-0 = <&pmx_sdio>;
- pinctrl-names = "default";
- status = "okay";
- /* No CD or WP GPIOs */
- broken-cd;
- };
- };
-
- gpio-leds {
- compatible = "gpio-leds";
- pinctrl-0 = <&pmx_led_bluetooth &pmx_led_wifi
- &pmx_led_wifi_ap >;
- pinctrl-names = "default";
-
- bluetooth {
- label = "dreamplug:blue:bluetooth";
- gpios = <&gpio1 15 GPIO_ACTIVE_LOW>;
- };
- wifi {
- label = "dreamplug:green:wifi";
- gpios = <&gpio1 16 GPIO_ACTIVE_LOW>;
- };
- wifi-ap {
- label = "dreamplug:green:wifi_ap";
- gpios = <&gpio1 17 GPIO_ACTIVE_LOW>;
- };
- };
-};
-
-&mdio {
- status = "okay";
-
- ethphy0: ethernet-phy@0 {
- reg = <0>;
- };
-
- ethphy1: ethernet-phy@1 {
- reg = <1>;
- };
-};
-
-ð0 {
- status = "okay";
- ethernet0-port@0 {
- phy-handle = <ðphy0>;
- };
-};
-
-ð1 {
- status = "okay";
- ethernet1-port@0 {
- phy-handle = <ðphy1>;
- };
-};
diff --git a/arch/arm/dts/kirkwood-ds109.dts b/arch/arm/dts/kirkwood-ds109.dts
deleted file mode 100644
index 29982e7..0000000
--- a/arch/arm/dts/kirkwood-ds109.dts
+++ /dev/null
@@ -1,40 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0
-/*
- * Andrew Lunn <andrew@lunn.ch>
- * Ben Peddell <klightspeed@killerwolves.net>
- *
- */
-
-/dts-v1/;
-
-#include "kirkwood.dtsi"
-#include "kirkwood-6281.dtsi"
-#include "kirkwood-synology.dtsi"
-
-/ {
- model = "Synology DS109, DS110, DS110jv20";
- compatible = "synology,ds109", "synology,ds110jv20",
- "synology,ds110", "marvell,kirkwood";
-
- memory {
- device_type = "memory";
- reg = <0x00000000 0x8000000>;
- };
-
- chosen {
- bootargs = "console=ttyS0,115200n8";
- stdout-path = &uart0;
- };
-
- gpio-fan-150-32-35 {
- status = "okay";
- };
-
- gpio-leds-hdd-21-1 {
- status = "okay";
- };
-};
-
-&rs5c372 {
- status = "okay";
-};
diff --git a/arch/arm/dts/kirkwood-goflexnet.dts b/arch/arm/dts/kirkwood-goflexnet.dts
deleted file mode 100644
index 02d87e0..0000000
--- a/arch/arm/dts/kirkwood-goflexnet.dts
+++ /dev/null
@@ -1,190 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0
-/dts-v1/;
-
-#include "kirkwood.dtsi"
-#include "kirkwood-6281.dtsi"
-
-/ {
- model = "Seagate GoFlex Net";
- compatible = "seagate,goflexnet", "marvell,kirkwood-88f6281", "marvell,kirkwood";
-
- memory {
- device_type = "memory";
- reg = <0x00000000 0x8000000>;
- };
-
- chosen {
- bootargs = "console=ttyS0,115200n8 earlyprintk root=/dev/sda1 rootdelay=10";
- stdout-path = &uart0;
- };
-
- ocp@f1000000 {
- pinctrl: pin-controller@10000 {
- pmx_usb_power_enable: pmx-usb-power-enable {
- marvell,pins = "mpp29";
- marvell,function = "gpio";
- };
- pmx_led_right_cap_0: pmx-led_right_cap_0 {
- marvell,pins = "mpp38";
- marvell,function = "gpio";
- };
- pmx_led_right_cap_1: pmx-led_right_cap_1 {
- marvell,pins = "mpp39";
- marvell,function = "gpio";
- };
- pmx_led_right_cap_2: pmx-led_right_cap_2 {
- marvell,pins = "mpp40";
- marvell,function = "gpio";
- };
- pmx_led_right_cap_3: pmx-led_right_cap_3 {
- marvell,pins = "mpp41";
- marvell,function = "gpio";
- };
- pmx_led_left_cap_0: pmx-led_left_cap_0 {
- marvell,pins = "mpp42";
- marvell,function = "gpio";
- };
- pmx_led_left_cap_1: pmx-led_left_cap_1 {
- marvell,pins = "mpp43";
- marvell,function = "gpio";
- };
- pmx_led_left_cap_2: pmx-led_left_cap_2 {
- marvell,pins = "mpp44";
- marvell,function = "gpio";
- };
- pmx_led_left_cap_3: pmx-led_left_cap_3 {
- marvell,pins = "mpp45";
- marvell,function = "gpio";
- };
- pmx_led_green: pmx-led_green {
- marvell,pins = "mpp46";
- marvell,function = "gpio";
- };
- pmx_led_orange: pmx-led_orange {
- marvell,pins = "mpp47";
- marvell,function = "gpio";
- };
- };
- serial@12000 {
- status = "ok";
- };
-
- sata@80000 {
- status = "okay";
- nr-ports = <2>;
- };
-
- };
- gpio-leds {
- compatible = "gpio-leds";
- pinctrl-0 = < &pmx_led_orange
- &pmx_led_left_cap_0 &pmx_led_left_cap_1
- &pmx_led_left_cap_2 &pmx_led_left_cap_3
- &pmx_led_right_cap_0 &pmx_led_right_cap_1
- &pmx_led_right_cap_2 &pmx_led_right_cap_3
- >;
- pinctrl-names = "default";
-
- health {
- label = "status:green:health";
- gpios = <&gpio1 14 GPIO_ACTIVE_LOW>;
- default-state = "keep";
- };
- fault {
- label = "status:orange:fault";
- gpios = <&gpio1 15 GPIO_ACTIVE_LOW>;
- };
- left0 {
- label = "status:white:left0";
- gpios = <&gpio1 10 GPIO_ACTIVE_HIGH>;
- };
- left1 {
- label = "status:white:left1";
- gpios = <&gpio1 11 GPIO_ACTIVE_HIGH>;
- };
- left2 {
- label = "status:white:left2";
- gpios = <&gpio1 12 GPIO_ACTIVE_HIGH>;
- };
- left3 {
- label = "status:white:left3";
- gpios = <&gpio1 13 GPIO_ACTIVE_HIGH>;
- };
- right0 {
- label = "status:white:right0";
- gpios = <&gpio1 6 GPIO_ACTIVE_HIGH>;
- };
- right1 {
- label = "status:white:right1";
- gpios = <&gpio1 7 GPIO_ACTIVE_HIGH>;
- };
- right2 {
- label = "status:white:right2";
- gpios = <&gpio1 8 GPIO_ACTIVE_HIGH>;
- };
- right3 {
- label = "status:white:right3";
- gpios = <&gpio1 9 GPIO_ACTIVE_HIGH>;
- };
- };
- regulators {
- compatible = "simple-bus";
- #address-cells = <1>;
- #size-cells = <0>;
- pinctrl-0 = <&pmx_usb_power_enable>;
- pinctrl-names = "default";
-
- usb_power: regulator@1 {
- compatible = "regulator-fixed";
- reg = <1>;
- regulator-name = "USB Power";
- regulator-min-microvolt = <5000000>;
- regulator-max-microvolt = <5000000>;
- enable-active-high;
- regulator-always-on;
- regulator-boot-on;
- gpio = <&gpio0 29 GPIO_ACTIVE_HIGH>;
- };
- };
-};
-
-&nand {
- chip-delay = <40>;
- status = "okay";
-
- partition@0 {
- label = "u-boot";
- reg = <0x0000000 0x100000>;
- read-only;
- };
-
- partition@100000 {
- label = "uImage";
- reg = <0x0100000 0x400000>;
- };
-
- partition@500000 {
- label = "pogoplug";
- reg = <0x0500000 0x2000000>;
- };
-
- partition@2500000 {
- label = "root";
- reg = <0x02500000 0xd800000>;
- };
-};
-
-&mdio {
- status = "okay";
-
- ethphy0: ethernet-phy@0 {
- reg = <0>;
- };
-};
-
-ð0 {
- status = "okay";
- ethernet0-port@0 {
- phy-handle = <ðphy0>;
- };
-};
diff --git a/arch/arm/dts/kirkwood-guruplug-server-plus.dts b/arch/arm/dts/kirkwood-guruplug-server-plus.dts
deleted file mode 100644
index ff1260e..0000000
--- a/arch/arm/dts/kirkwood-guruplug-server-plus.dts
+++ /dev/null
@@ -1,133 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0
-/dts-v1/;
-
-#include "kirkwood.dtsi"
-#include "kirkwood-6281.dtsi"
-
-/ {
- model = "Globalscale Technologies Guruplug Server Plus";
- compatible = "globalscale,guruplug-server-plus", "globalscale,guruplug", "marvell,kirkwood-88f6281", "marvell,kirkwood";
-
- memory {
- device_type = "memory";
- reg = <0x00000000 0x20000000>;
- };
-
- chosen {
- bootargs = "console=ttyS0,115200n8 earlyprintk";
- stdout-path = &uart0;
- };
-
- ocp@f1000000 {
- pinctrl: pin-controller@10000 {
- pmx_led_health_r: pmx-led-health-r {
- marvell,pins = "mpp46";
- marvell,function = "gpio";
- };
- pmx_led_health_g: pmx-led-health-g {
- marvell,pins = "mpp47";
- marvell,function = "gpio";
- };
- pmx_led_wmode_r: pmx-led-wmode-r {
- marvell,pins = "mpp48";
- marvell,function = "gpio";
- };
- pmx_led_wmode_g: pmx-led-wmode-g {
- marvell,pins = "mpp49";
- marvell,function = "gpio";
- };
- };
- serial@12000 {
- status = "ok";
- };
-
- sata@80000 {
- status = "okay";
- nr-ports = <1>;
- };
-
- /* AzureWave AW-GH381 WiFi/BT */
- mvsdio@90000 {
- status = "okay";
- non-removable;
- };
- };
-
- gpio-leds {
- compatible = "gpio-leds";
- pinctrl-0 = < &pmx_led_health_r &pmx_led_health_g
- &pmx_led_wmode_r &pmx_led_wmode_g >;
- pinctrl-names = "default";
-
- health-r {
- label = "guruplug:red:health";
- gpios = <&gpio1 14 GPIO_ACTIVE_LOW>;
- };
- health-g {
- label = "guruplug:green:health";
- gpios = <&gpio1 15 GPIO_ACTIVE_LOW>;
- };
- wmode-r {
- label = "guruplug:red:wmode";
- gpios = <&gpio1 16 GPIO_ACTIVE_LOW>;
- };
- wmode-g {
- label = "guruplug:green:wmode";
- gpios = <&gpio1 17 GPIO_ACTIVE_LOW>;
- };
- };
-};
-
-&nand {
- status = "okay";
-
- partition@0 {
- label = "u-boot";
- reg = <0x00000000 0x00100000>;
- read-only;
- };
-
- partition@100000 {
- label = "uImage";
- reg = <0x00100000 0x00400000>;
- };
-
- partition@500000 {
- label = "data";
- reg = <0x00500000 0x1fb00000>;
- };
-};
-
-&mdio {
- status = "okay";
-
- ethphy0: ethernet-phy@0 {
- /* Marvell 88E1121R */
- compatible = "ethernet-phy-id0141.0cb0",
- "ethernet-phy-ieee802.3-c22";
- reg = <0>;
- };
-
- ethphy1: ethernet-phy@1 {
- /* Marvell 88E1121R */
- compatible = "ethernet-phy-id0141.0cb0",
- "ethernet-phy-ieee802.3-c22";
- reg = <1>;
- };
-};
-
-ð0 {
- status = "okay";
- ethernet0-port@0 {
- phy-handle = <ðphy0>;
- phy-connection-type = "rgmii-id";
- };
-};
-
-ð1 {
- status = "okay";
- ethernet1-port@0 {
- phy-handle = <ðphy1>;
- phy-connection-type = "rgmii-id";
- };
-};
diff --git a/arch/arm/dts/kirkwood-ib62x0.dts b/arch/arm/dts/kirkwood-ib62x0.dts
deleted file mode 100644
index 962a910..0000000
--- a/arch/arm/dts/kirkwood-ib62x0.dts
+++ /dev/null
@@ -1,146 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0
-/dts-v1/;
-
-#include "kirkwood.dtsi"
-#include "kirkwood-6281.dtsi"
-
-/ {
- model = "RaidSonic ICY BOX IB-NAS62x0 (Rev B)";
- compatible = "raidsonic,ib-nas6210-b", "raidsonic,ib-nas6220-b", "raidsonic,ib-nas6210", "raidsonic,ib-nas6220", "raidsonic,ib-nas62x0", "marvell,kirkwood-88f6281", "marvell,kirkwood";
-
- memory {
- device_type = "memory";
- reg = <0x00000000 0x10000000>;
- };
-
- chosen {
- bootargs = "console=ttyS0,115200n8 earlyprintk";
- stdout-path = &uart0;
- };
-
- ocp@f1000000 {
- pinctrl: pin-controller@10000 {
- pmx_led_os_red: pmx-led-os-red {
- marvell,pins = "mpp22";
- marvell,function = "gpio";
- };
- pmx_power_off: pmx-power-off {
- marvell,pins = "mpp24";
- marvell,function = "gpio";
- };
- pmx_led_os_green: pmx-led-os-green {
- marvell,pins = "mpp25";
- marvell,function = "gpio";
- };
- pmx_led_usb_transfer: pmx-led-usb-transfer {
- marvell,pins = "mpp27";
- marvell,function = "gpio";
- };
- pmx_button_reset: pmx-button-reset {
- marvell,pins = "mpp28";
- marvell,function = "gpio";
- };
- pmx_button_usb_copy: pmx-button-usb-copy {
- marvell,pins = "mpp29";
- marvell,function = "gpio";
- };
- };
-
- serial@12000 {
- status = "okay";
- };
-
- sata@80000 {
- status = "okay";
- nr-ports = <2>;
- };
- };
-
- gpio_keys {
- compatible = "gpio-keys";
- #address-cells = <1>;
- #size-cells = <0>;
- pinctrl-0 = <&pmx_button_reset &pmx_button_usb_copy>;
- pinctrl-names = "default";
-
- copy {
- label = "USB Copy";
- linux,code = <KEY_COPY>;
- gpios = <&gpio0 29 GPIO_ACTIVE_LOW>;
- };
- reset {
- label = "Reset";
- linux,code = <KEY_RESTART>;
- gpios = <&gpio0 28 GPIO_ACTIVE_LOW>;
- };
- };
-
- gpio-leds {
- compatible = "gpio-leds";
- pinctrl-0 = <&pmx_led_os_red &pmx_led_os_green
- &pmx_led_usb_transfer>;
- pinctrl-names = "default";
-
- green-os {
- label = "ib62x0:green:os";
- gpios = <&gpio0 25 GPIO_ACTIVE_HIGH>;
- default-state = "keep";
- };
- red-os {
- label = "ib62x0:red:os";
- gpios = <&gpio0 22 GPIO_ACTIVE_HIGH>;
- };
- usb-copy {
- label = "ib62x0:red:usb_copy";
- gpios = <&gpio0 27 GPIO_ACTIVE_HIGH>;
- };
- };
-
- gpio_poweroff {
- compatible = "gpio-poweroff";
- pinctrl-0 = <&pmx_power_off>;
- pinctrl-names = "default";
- gpios = <&gpio0 24 GPIO_ACTIVE_HIGH>;
- };
-};
-
-&nand {
- status = "okay";
-
- partition@0 {
- label = "u-boot";
- reg = <0x0000000 0xe0000>;
- };
-
- partition@e0000 {
- label = "u-boot environment";
- reg = <0xe0000 0x20000>;
- };
-
- partition@100000 {
- label = "uImage";
- reg = <0x0100000 0x600000>;
- };
-
- partition@700000 {
- label = "root";
- reg = <0x0700000 0xf900000>;
- };
-
-};
-
-&mdio {
- status = "okay";
-
- ethphy0: ethernet-phy@8 {
- reg = <8>;
- };
-};
-
-ð0 {
- status = "okay";
-
- ethernet0-port@0 {
- phy-handle = <ðphy0>;
- };
-};
diff --git a/arch/arm/dts/kirkwood-iconnect.dts b/arch/arm/dts/kirkwood-iconnect.dts
deleted file mode 100644
index 4a512d8..0000000
--- a/arch/arm/dts/kirkwood-iconnect.dts
+++ /dev/null
@@ -1,195 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0
-/dts-v1/;
-
-#include "kirkwood.dtsi"
-#include "kirkwood-6281.dtsi"
-
-/ {
- model = "Iomega Iconnect";
- compatible = "iom,iconnect-1.1", "iom,iconnect", "marvell,kirkwood-88f6281", "marvell,kirkwood";
-
- memory {
- device_type = "memory";
- reg = <0x00000000 0x10000000>;
- };
-
- chosen {
- bootargs = "console=ttyS0,115200n8 earlyprintk";
- stdout-path = &uart0;
- linux,initrd-start = <0x4500040>;
- linux,initrd-end = <0x4800000>;
- };
-
- ocp@f1000000 {
- pinctrl: pin-controller@10000 {
- pmx_button_reset: pmx-button-reset {
- marvell,pins = "mpp12";
- marvell,function = "gpio";
- };
- pmx_button_otb: pmx-button-otb {
- marvell,pins = "mpp35";
- marvell,function = "gpio";
- };
- pmx_led_level: pmx-led-level {
- marvell,pins = "mpp41";
- marvell,function = "gpio";
- };
- pmx_led_power_blue: pmx-led-power-blue {
- marvell,pins = "mpp42";
- marvell,function = "gpio";
- };
- pmx_led_power_red: pmx-power-red {
- marvell,pins = "mpp43";
- marvell,function = "gpio";
- };
- pmx_led_usb1: pmx-led-usb1 {
- marvell,pins = "mpp44";
- marvell,function = "gpio";
- };
- pmx_led_usb2: pmx-led-usb2 {
- marvell,pins = "mpp45";
- marvell,function = "gpio";
- };
- pmx_led_usb3: pmx-led-usb3 {
- marvell,pins = "mpp46";
- marvell,function = "gpio";
- };
- pmx_led_usb4: pmx-led-usb4 {
- marvell,pins = "mpp47";
- marvell,function = "gpio";
- };
- pmx_led_otb: pmx-led-otb {
- marvell,pins = "mpp48";
- marvell,function = "gpio";
- };
- };
- i2c@11000 {
- status = "okay";
-
- lm63: lm63@4c {
- compatible = "national,lm63";
- reg = <0x4c>;
- };
- };
- serial@12000 {
- status = "ok";
- };
- };
-
- gpio-leds {
- compatible = "gpio-leds";
- pinctrl-0 = < &pmx_led_level &pmx_led_power_blue
- &pmx_led_power_red &pmx_led_usb1
- &pmx_led_usb2 &pmx_led_usb3
- &pmx_led_usb4 &pmx_led_otb >;
- pinctrl-names = "default";
-
- led-level {
- label = "led_level";
- gpios = <&gpio1 9 GPIO_ACTIVE_HIGH>;
- default-state = "on";
- };
- power-blue {
- label = "power:blue";
- gpios = <&gpio1 10 GPIO_ACTIVE_HIGH>;
- default-state = "keep";
- };
- power-red {
- label = "power:red";
- gpios = <&gpio1 11 GPIO_ACTIVE_HIGH>;
- };
- usb1 {
- label = "usb1:blue";
- gpios = <&gpio1 12 GPIO_ACTIVE_HIGH>;
- };
- usb2 {
- label = "usb2:blue";
- gpios = <&gpio1 13 GPIO_ACTIVE_HIGH>;
- };
- usb3 {
- label = "usb3:blue";
- gpios = <&gpio1 14 GPIO_ACTIVE_HIGH>;
- };
- usb4 {
- label = "usb4:blue";
- gpios = <&gpio1 15 GPIO_ACTIVE_HIGH>;
- };
- otb {
- label = "otb:blue";
- gpios = <&gpio1 16 GPIO_ACTIVE_HIGH>;
- };
- };
-
- gpio_keys {
- compatible = "gpio-keys";
- #address-cells = <1>;
- #size-cells = <0>;
- pinctrl-0 = < &pmx_button_reset &pmx_button_otb >;
- pinctrl-names = "default";
-
- otb {
- label = "OTB Button";
- linux,code = <KEY_COPY>;
- gpios = <&gpio1 3 GPIO_ACTIVE_LOW>;
- debounce-interval = <100>;
- };
- reset {
- label = "Reset";
- linux,code = <KEY_RESTART>;
- gpios = <&gpio0 12 GPIO_ACTIVE_LOW>;
- debounce-interval = <100>;
- };
- };
-};
-
-&nand {
- status = "okay";
-
- partition@0 {
- label = "uboot";
- reg = <0x0000000 0xc0000>;
- };
-
- partition@a0000 {
- label = "env";
- reg = <0xa0000 0x20000>;
- };
-
- partition@100000 {
- label = "zImage";
- reg = <0x100000 0x300000>;
- };
-
- partition@540000 {
- label = "initrd";
- reg = <0x540000 0x300000>;
- };
-
- partition@980000 {
- label = "boot";
- reg = <0x980000 0x1f400000>;
- };
-};
-
-&mdio {
- status = "okay";
-
- ethphy0: ethernet-phy@11 {
- reg = <11>;
- };
-};
-
-ð0 {
- status = "okay";
- ethernet0-port@0 {
- phy-handle = <ðphy0>;
- };
-};
-
-&pciec {
- status = "okay";
-};
-
-&pcie0 {
- status = "okay";
-};
diff --git a/arch/arm/dts/kirkwood-is2.dts b/arch/arm/dts/kirkwood-is2.dts
deleted file mode 100644
index 1bc16a5..0000000
--- a/arch/arm/dts/kirkwood-is2.dts
+++ /dev/null
@@ -1,40 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0
-/dts-v1/;
-
-#include <dt-bindings/leds/leds-ns2.h>
-#include "kirkwood-ns2-common.dtsi"
-
-/ {
- model = "LaCie Internet Space v2";
- compatible = "lacie,inetspace_v2", "marvell,kirkwood-88f6281", "marvell,kirkwood";
-
- memory {
- device_type = "memory";
- reg = <0x00000000 0x8000000>;
- };
-
- ocp@f1000000 {
- sata@80000 {
- pinctrl-0 = <&pmx_ns2_sata0>;
- pinctrl-names = "default";
- status = "okay";
- nr-ports = <1>;
- };
- };
-
- ns2-leds {
- compatible = "lacie,ns2-leds";
-
- blue-sata {
- label = "ns2:blue:sata";
- slow-gpio = <&gpio0 29 0>;
- cmd-gpio = <&gpio0 30 0>;
- modes-map = <NS_V2_LED_OFF 1 0
- NS_V2_LED_ON 0 1
- NS_V2_LED_ON 1 1
- NS_V2_LED_SATA 0 0>;
- };
- };
-};
-
-ðphy0 { reg = <8>; };
diff --git a/arch/arm/dts/kirkwood-lschlv2-u-boot.dtsi b/arch/arm/dts/kirkwood-lschlv2-u-boot.dtsi
index 7fc2d7d..cf33ff8 100644
--- a/arch/arm/dts/kirkwood-lschlv2-u-boot.dtsi
+++ b/arch/arm/dts/kirkwood-lschlv2-u-boot.dtsi
@@ -1,7 +1,9 @@
// SPDX-License-Identifier: GPL-2.0+
-ð0 {
- status = "disabled";
+/ {
+ aliases {
+ spi0 = &spi0;
+ };
};
&hdd_power {
diff --git a/arch/arm/dts/kirkwood-lschlv2.dts b/arch/arm/dts/kirkwood-lschlv2.dts
deleted file mode 100644
index 1d737d9..0000000
--- a/arch/arm/dts/kirkwood-lschlv2.dts
+++ /dev/null
@@ -1,20 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0
-/dts-v1/;
-
-#include "kirkwood-lsxl.dtsi"
-
-/ {
- model = "Buffalo Linkstation LS-CHLv2";
- compatible = "buffalo,lschlv2", "buffalo,lsxl", "marvell,kirkwood-88f6281", "marvell,kirkwood";
-
- memory {
- device_type = "memory";
- reg = <0x00000000 0x4000000>;
- };
-
- ocp@f1000000 {
- serial@12000 {
- status = "okay";
- };
- };
-};
diff --git a/arch/arm/dts/kirkwood-lsxhl-u-boot.dtsi b/arch/arm/dts/kirkwood-lsxhl-u-boot.dtsi
index 7fc2d7d..cf33ff8 100644
--- a/arch/arm/dts/kirkwood-lsxhl-u-boot.dtsi
+++ b/arch/arm/dts/kirkwood-lsxhl-u-boot.dtsi
@@ -1,7 +1,9 @@
// SPDX-License-Identifier: GPL-2.0+
-ð0 {
- status = "disabled";
+/ {
+ aliases {
+ spi0 = &spi0;
+ };
};
&hdd_power {
diff --git a/arch/arm/dts/kirkwood-lsxhl.dts b/arch/arm/dts/kirkwood-lsxhl.dts
deleted file mode 100644
index a56e0d7..0000000
--- a/arch/arm/dts/kirkwood-lsxhl.dts
+++ /dev/null
@@ -1,20 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0
-/dts-v1/;
-
-#include "kirkwood-lsxl.dtsi"
-
-/ {
- model = "Buffalo Linkstation LS-XHL";
- compatible = "buffalo,lsxhl", "buffalo,lsxl", "marvell,kirkwood-88f6281", "marvell,kirkwood";
-
- memory {
- device_type = "memory";
- reg = <0x00000000 0x10000000>;
- };
-
- ocp@f1000000 {
- serial@12000 {
- status = "okay";
- };
- };
-};
diff --git a/arch/arm/dts/kirkwood-lsxl.dtsi b/arch/arm/dts/kirkwood-lsxl.dtsi
deleted file mode 100644
index c99c0da..0000000
--- a/arch/arm/dts/kirkwood-lsxl.dtsi
+++ /dev/null
@@ -1,241 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0
-#include "kirkwood.dtsi"
-#include "kirkwood-6281.dtsi"
-
-/ {
- chosen {
- bootargs = "console=ttyS0,115200n8 earlyprintk";
- stdout-path = &uart0;
- };
-
- aliases {
- spi0 = &spi0;
- };
-
- ocp@f1000000 {
- pinctrl: pin-controller@10000 {
- pmx_power_hdd: pmx-power-hdd {
- marvell,pins = "mpp10";
- marvell,function = "gpo";
- };
- pmx_usb_vbus: pmx-usb-vbus {
- marvell,pins = "mpp11";
- marvell,function = "gpio";
- };
- pmx_fan_high: pmx-fan-high {
- marvell,pins = "mpp18";
- marvell,function = "gpo";
- };
- pmx_fan_low: pmx-fan-low {
- marvell,pins = "mpp19";
- marvell,function = "gpo";
- };
- pmx_led_function_blue: pmx-led-function-blue {
- marvell,pins = "mpp36";
- marvell,function = "gpio";
- };
- pmx_led_alarm: pmx-led-alarm {
- marvell,pins = "mpp37";
- marvell,function = "gpio";
- };
- pmx_led_info: pmx-led-info {
- marvell,pins = "mpp38";
- marvell,function = "gpio";
- };
- pmx_led_power: pmx-led-power {
- marvell,pins = "mpp39";
- marvell,function = "gpio";
- };
- pmx_fan_lock: pmx-fan-lock {
- marvell,pins = "mpp40";
- marvell,function = "gpio";
- };
- pmx_button_function: pmx-button-function {
- marvell,pins = "mpp41";
- marvell,function = "gpio";
- };
- pmx_power_switch: pmx-power-switch {
- marvell,pins = "mpp42";
- marvell,function = "gpio";
- };
- pmx_power_auto_switch: pmx-power-auto-switch {
- marvell,pins = "mpp43";
- marvell,function = "gpio";
- };
- pmx_led_function_red: pmx-led-function_red {
- marvell,pins = "mpp48";
- marvell,function = "gpio";
- };
-
- };
- sata@80000 {
- status = "okay";
- nr-ports = <1>;
- };
-
- spi@10600 {
- status = "okay";
-
- m25p40@0 {
- #address-cells = <1>;
- #size-cells = <1>;
- compatible = "m25p40", "jedec,spi-nor";
- reg = <0>;
- spi-max-frequency = <25000000>;
- mode = <0>;
-
- partition@0 {
- reg = <0x0 0x60000>;
- label = "uboot";
- read-only;
- };
-
- partition@60000 {
- reg = <0x60000 0x10000>;
- label = "dtb";
- read-only;
- };
-
- partition@70000 {
- reg = <0x70000 0x10000>;
- label = "uboot_env";
- };
- };
- };
- };
-
- gpio_keys {
- compatible = "gpio-keys";
- #address-cells = <1>;
- #size-cells = <0>;
- pinctrl-0 = <&pmx_button_function &pmx_power_switch
- &pmx_power_auto_switch>;
- pinctrl-names = "default";
-
- option {
- label = "Function Button";
- linux,code = <KEY_OPTION>;
- gpios = <&gpio1 9 GPIO_ACTIVE_LOW>;
- };
- reserved {
- label = "Power-on Switch";
- linux,code = <KEY_RESERVED>;
- linux,input-type = <5>;
- gpios = <&gpio1 10 GPIO_ACTIVE_LOW>;
- };
- power {
- label = "Power-auto Switch";
- linux,code = <KEY_ESC>;
- linux,input-type = <5>;
- gpios = <&gpio1 11 GPIO_ACTIVE_LOW>;
- };
- };
-
- gpio_leds {
- compatible = "gpio-leds";
- pinctrl-0 = <&pmx_led_function_red &pmx_led_alarm
- &pmx_led_info &pmx_led_power
- &pmx_led_function_blue>;
- pinctrl-names = "default";
-
- func_blue {
- label = "lsxl:blue:func";
- gpios = <&gpio1 4 GPIO_ACTIVE_LOW>;
- };
-
- alarm {
- label = "lsxl:red:alarm";
- gpios = <&gpio1 5 GPIO_ACTIVE_LOW>;
- };
-
- info {
- label = "lsxl:amber:info";
- gpios = <&gpio1 6 GPIO_ACTIVE_LOW>;
- };
-
- power {
- label = "lsxl:blue:power";
- gpios = <&gpio1 7 GPIO_ACTIVE_LOW>;
- default-state = "keep";
- };
-
- func_red {
- label = "lsxl:red:func";
- gpios = <&gpio1 16 GPIO_ACTIVE_LOW>;
- };
- };
-
- gpio_fan {
- compatible = "gpio-fan";
- pinctrl-0 = <&pmx_fan_low &pmx_fan_high &pmx_fan_lock>;
- pinctrl-names = "default";
- gpios = <&gpio0 19 GPIO_ACTIVE_LOW
- &gpio0 18 GPIO_ACTIVE_LOW>;
- gpio-fan,speed-map = <0 3
- 1500 2
- 3250 1
- 5000 0>;
- alarm-gpios = <&gpio1 8 GPIO_ACTIVE_HIGH>;
- };
-
- restart_poweroff {
- compatible = "restart-poweroff";
- };
-
- regulators {
- compatible = "simple-bus";
- #address-cells = <1>;
- #size-cells = <0>;
- pinctrl-0 = <&pmx_power_hdd &pmx_usb_vbus>;
- pinctrl-names = "default";
-
- usb_power: regulator@1 {
- compatible = "regulator-fixed";
- reg = <1>;
- regulator-name = "USB Power";
- regulator-min-microvolt = <5000000>;
- regulator-max-microvolt = <5000000>;
- enable-active-high;
- regulator-always-on;
- regulator-boot-on;
- gpio = <&gpio0 11 0>;
- };
- hdd_power: regulator@2 {
- compatible = "regulator-fixed";
- reg = <2>;
- regulator-name = "HDD Power";
- regulator-min-microvolt = <5000000>;
- regulator-max-microvolt = <5000000>;
- enable-active-high;
- regulator-always-on;
- regulator-boot-on;
- gpio = <&gpio0 10 0>;
- };
- };
-};
-
-&mdio {
- status = "okay";
-
- ethphy0: ethernet-phy@0 {
- reg = <0>;
- };
-
- ethphy1: ethernet-phy@8 {
- reg = <8>;
- };
-};
-
-ð0 {
- status = "okay";
- ethernet0-port@0 {
- phy-handle = <ðphy0>;
- };
-};
-
-ð1 {
- status = "okay";
- ethernet1-port@0 {
- phy-handle = <ðphy1>;
- };
-};
diff --git a/arch/arm/dts/kirkwood-net2big.dts b/arch/arm/dts/kirkwood-net2big.dts
deleted file mode 100644
index 3e3ac28..0000000
--- a/arch/arm/dts/kirkwood-net2big.dts
+++ /dev/null
@@ -1,63 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0
-/*
- * Device Tree file for LaCie 2Big Network v2
- *
- * Copyright (C) 2014
- *
- * Andrew Lunn <andrew@lunn.ch>
- *
- * Based on netxbig_v2-setup.c,
- * Copyright (C) 2010 Simon Guinot <sguinot@lacie.com>
- *
-*/
-
-/dts-v1/;
-
-#include "kirkwood.dtsi"
-#include "kirkwood-6281.dtsi"
-#include "kirkwood-netxbig.dtsi"
-
-/ {
- model = "LaCie 2Big Network v2";
- compatible = "lacie,net2big_v2", "lacie,netxbig", "marvell,kirkwood-88f6281", "marvell,kirkwood";
-
- memory {
- device_type = "memory";
- reg = <0x00000000 0x10000000>;
- };
-
- fan {
- compatible = "gpio-fan";
- alarm-gpios = <&gpio0 25 GPIO_ACTIVE_LOW>;
- };
-};
-
-®ulators {
- regulator@2 {
- compatible = "regulator-fixed";
- reg = <2>;
- regulator-name = "hdd1power";
- regulator-min-microvolt = <5000000>;
- regulator-max-microvolt = <5000000>;
- enable-active-high;
- regulator-always-on;
- regulator-boot-on;
- gpio = <&gpio0 17 GPIO_ACTIVE_HIGH>;
- };
-
- clocks {
- g762_clk: g762-oscillator {
- compatible = "fixed-clock";
- #clock-cells = <0>;
- clock-frequency = <32768>;
- };
- };
-};
-
-&i2c0 {
- g762@3e {
- compatible = "gmt,g762";
- reg = <0x3e>;
- clocks = <&g762_clk>;
- };
-};
diff --git a/arch/arm/dts/kirkwood-netxbig.dtsi b/arch/arm/dts/kirkwood-netxbig.dtsi
deleted file mode 100644
index b573702..0000000
--- a/arch/arm/dts/kirkwood-netxbig.dtsi
+++ /dev/null
@@ -1,232 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0
-/*
- * Device Tree common file for LaCie 2Big and 5Big Network v2
- *
- * Copyright (C) 2014
- *
- * Andrew Lunn <andrew@lunn.ch>
- *
- * Based on netxbig_v2-setup.c,
- * Copyright (C) 2010 Simon Guinot <sguinot@lacie.com>
- *
-*/
-
-#include <dt-bindings/leds/leds-netxbig.h>
-#include "kirkwood.dtsi"
-#include "kirkwood-6281.dtsi"
-
-/ {
- chosen {
- bootargs = "console=ttyS0,115200n8";
- stdout-path = &uart0;
- };
-
- ocp@f1000000 {
- serial@12000 {
- status = "okay";
- };
-
- spi@10600 {
- status = "okay";
-
- flash@0 {
- #address-cells = <1>;
- #size-cells = <1>;
- compatible = "mxicy,mx25l4005a", "jedec,spi-nor";
- reg = <0>;
- spi-max-frequency = <20000000>;
- mode = <0>;
-
- partition@0 {
- reg = <0x0 0x80000>;
- label = "u-boot";
- };
- };
- };
-
- sata@80000 {
- status = "okay";
- nr-ports = <2>;
- };
-
- };
-
- gpio-keys {
- compatible = "gpio-keys";
- #address-cells = <1>;
- #size-cells = <0>;
-
- /*
- * esc and power represent a three position rocker
- * switch. Thus the conventional KEY_POWER does not fit
- */
- exc {
- label = "Back power switch (on|auto)";
- linux,code = <KEY_ESC>;
- linux,input-type = <5>;
- gpios = <&gpio0 13 GPIO_ACTIVE_LOW>;
- };
- power {
- label = "Back power switch (auto|off)";
- linux,code = <KEY_1>;
- linux,input-type = <5>;
- gpios = <&gpio0 15 GPIO_ACTIVE_LOW>;
- };
- option {
- label = "Function button";
- linux,code = <KEY_OPTION>;
- gpios = <&gpio1 2 GPIO_ACTIVE_LOW>;
- };
-
- };
-
- gpio-poweroff {
- compatible = "gpio-poweroff";
- gpios = <&gpio0 7 GPIO_ACTIVE_HIGH>;
- };
-
- regulators: regulators {
- status = "okay";
- compatible = "simple-bus";
- #address-cells = <1>;
- #size-cells = <0>;
- pinctrl-names = "default";
-
- regulator@1 {
- compatible = "regulator-fixed";
- reg = <1>;
- regulator-name = "hdd0power";
- regulator-min-microvolt = <5000000>;
- regulator-max-microvolt = <5000000>;
- enable-active-high;
- regulator-always-on;
- regulator-boot-on;
- gpio = <&gpio0 16 GPIO_ACTIVE_HIGH>;
- };
- };
-
- netxbig_gpio_ext: netxbig-gpio-ext {
- compatible = "lacie,netxbig-gpio-ext";
-
- addr-gpios = <&gpio1 15 GPIO_ACTIVE_HIGH
- &gpio1 16 GPIO_ACTIVE_HIGH
- &gpio1 17 GPIO_ACTIVE_HIGH>;
- data-gpios = <&gpio1 12 GPIO_ACTIVE_HIGH
- &gpio1 13 GPIO_ACTIVE_HIGH
- &gpio1 14 GPIO_ACTIVE_HIGH>;
- enable-gpio = <&gpio0 29 GPIO_ACTIVE_HIGH>;
- };
-
- netxbig-leds {
- compatible = "lacie,netxbig-leds";
-
- gpio-ext = <&netxbig_gpio_ext>;
-
- timers = <NETXBIG_LED_TIMER1 500 500
- NETXBIG_LED_TIMER2 500 1000>;
-
- blue-power {
- label = "netxbig:blue:power";
- mode-addr = <0>;
- mode-val = <NETXBIG_LED_OFF 0
- NETXBIG_LED_ON 1
- NETXBIG_LED_TIMER1 3
- NETXBIG_LED_TIMER2 7>;
- bright-addr = <1>;
- max-brightness = <7>;
- };
- red-power {
- label = "netxbig:red:power";
- mode-addr = <0>;
- mode-val = <NETXBIG_LED_OFF 0
- NETXBIG_LED_ON 2
- NETXBIG_LED_TIMER1 4>;
- bright-addr = <1>;
- max-brightness = <7>;
- };
- blue-sata0 {
- label = "netxbig:blue:sata0";
- mode-addr = <3>;
- mode-val = <NETXBIG_LED_OFF 0
- NETXBIG_LED_ON 7
- NETXBIG_LED_SATA 1
- NETXBIG_LED_TIMER1 3>;
- bright-addr = <2>;
- max-brightness = <7>;
- };
- red-sata0 {
- label = "netxbig:red:sata0";
- mode-addr = <3>;
- mode-val = <NETXBIG_LED_OFF 0
- NETXBIG_LED_ON 2
- NETXBIG_LED_TIMER1 4>;
- bright-addr = <2>;
- max-brightness = <7>;
- };
- blue-sata1 {
- label = "netxbig:blue:sata1";
- mode-addr = <4>;
- mode-val = <NETXBIG_LED_OFF 0
- NETXBIG_LED_ON 7
- NETXBIG_LED_SATA 1
- NETXBIG_LED_TIMER1 3>;
- bright-addr = <2>;
- max-brightness = <7>;
- };
- red-sata1 {
- label = "netxbig:red:sata1";
- mode-addr = <4>;
- mode-val = <NETXBIG_LED_OFF 0
- NETXBIG_LED_ON 2
- NETXBIG_LED_TIMER1 4>;
- bright-addr = <2>;
- max-brightness = <7>;
- };
- };
-};
-
-&mdio {
- status = "okay";
-
- ethphy0: ethernet-phy@0 {
- reg = <8>;
- };
-
- ethphy1: ethernet-phy@1 {
- reg = <0>;
- };
-};
-
-ð0 {
- status = "okay";
- ethernet0-port@0 {
- phy-handle = <ðphy0>;
- };
-};
-
-&pinctrl {
- pinctrl-names = "default";
-
- pmx_button_function: pmx-button-function {
- marvell,pins = "mpp34";
- marvell,function = "gpio";
- };
- pmx_button_power_off: pmx-button-power-off {
- marvell,pins = "mpp15";
- marvell,function = "gpio";
- };
- pmx_button_power_on: pmx-button-power-on {
- marvell,pins = "mpp13";
- marvell,function = "gpio";
- };
-};
-
-&i2c0 {
- status = "okay";
-
- eeprom@50 {
- compatible = "atmel,24c04";
- pagesize = <16>;
- reg = <0x50>;
- };
-};
diff --git a/arch/arm/dts/kirkwood-ns2-common.dtsi b/arch/arm/dts/kirkwood-ns2-common.dtsi
deleted file mode 100644
index 51530ea..0000000
--- a/arch/arm/dts/kirkwood-ns2-common.dtsi
+++ /dev/null
@@ -1,97 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0
-#include "kirkwood.dtsi"
-#include "kirkwood-6281.dtsi"
-
-/ {
- chosen {
- bootargs = "console=ttyS0,115200n8";
- stdout-path = &uart0;
- };
-
- ocp@f1000000 {
- pinctrl: pin-controller@10000 {
- pmx_ns2_sata0: pmx-ns2-sata0 {
- marvell,pins = "mpp21";
- marvell,function = "sata0";
- };
- pmx_ns2_sata1: pmx-ns2-sata1 {
- marvell,pins = "mpp20";
- marvell,function = "sata1";
- };
- };
-
- serial@12000 {
- status = "okay";
- };
-
- spi@10600 {
- status = "okay";
-
- flash@0 {
- #address-cells = <1>;
- #size-cells = <1>;
- compatible = "mxicy,mx25l4005a", "jedec,spi-nor";
- reg = <0>;
- spi-max-frequency = <20000000>;
- mode = <0>;
-
- partition@0 {
- reg = <0x0 0x80000>;
- label = "u-boot";
- };
- };
- };
-
- i2c@11000 {
- status = "okay";
-
- eeprom@50 {
- compatible = "atmel,24c04";
- pagesize = <16>;
- reg = <0x50>;
- };
- };
- };
-
- gpio_keys {
- compatible = "gpio-keys";
- #address-cells = <1>;
- #size-cells = <0>;
-
- power {
- label = "Power push button";
- linux,code = <KEY_POWER>;
- gpios = <&gpio1 0 GPIO_ACTIVE_HIGH>;
- };
- };
-
- gpio-leds {
- compatible = "gpio-leds";
-
- red-fail {
- label = "ns2:red:fail";
- gpios = <&gpio0 12 GPIO_ACTIVE_HIGH>;
- };
- };
-
- gpio_poweroff {
- compatible = "gpio-poweroff";
- gpios = <&gpio0 31 GPIO_ACTIVE_HIGH>;
- };
-
-};
-
-&mdio {
- status = "okay";
-
- ethphy0: ethernet-phy@X {
- /* overwrite reg property in board file */
- };
-};
-
-ð0 {
- status = "okay";
- ethernet0-port@0 {
- phy-handle = <ðphy0>;
- };
-};
diff --git a/arch/arm/dts/kirkwood-ns2.dts b/arch/arm/dts/kirkwood-ns2.dts
deleted file mode 100644
index 7b67083..0000000
--- a/arch/arm/dts/kirkwood-ns2.dts
+++ /dev/null
@@ -1,40 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0
-/dts-v1/;
-
-#include <dt-bindings/leds/leds-ns2.h>
-#include "kirkwood-ns2-common.dtsi"
-
-/ {
- model = "LaCie Network Space v2";
- compatible = "lacie,netspace_v2", "marvell,kirkwood-88f6281", "marvell,kirkwood";
-
- memory {
- device_type = "memory";
- reg = <0x00000000 0x10000000>;
- };
-
- ocp@f1000000 {
- sata@80000 {
- pinctrl-0 = <&pmx_ns2_sata0>;
- pinctrl-names = "default";
- status = "okay";
- nr-ports = <1>;
- };
- };
-
- ns2-leds {
- compatible = "lacie,ns2-leds";
-
- blue-sata {
- label = "ns2:blue:sata";
- slow-gpio = <&gpio0 29 0>;
- cmd-gpio = <&gpio0 30 0>;
- modes-map = <NS_V2_LED_OFF 1 0
- NS_V2_LED_ON 0 1
- NS_V2_LED_ON 1 1
- NS_V2_LED_SATA 0 0>;
- };
- };
-};
-
-ðphy0 { reg = <8>; };
diff --git a/arch/arm/dts/kirkwood-ns2lite.dts b/arch/arm/dts/kirkwood-ns2lite.dts
deleted file mode 100644
index b0cb590..0000000
--- a/arch/arm/dts/kirkwood-ns2lite.dts
+++ /dev/null
@@ -1,35 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0
-/dts-v1/;
-
-#include "kirkwood-ns2-common.dtsi"
-
-/ {
- model = "LaCie Network Space Lite v2";
- compatible = "lacie,netspace_lite_v2", "marvell,kirkwood-88f6192", "marvell,kirkwood";
-
- memory {
- device_type = "memory";
- reg = <0x00000000 0x8000000>;
- };
-
- ocp@f1000000 {
- sata@80000 {
- pinctrl-0 = <&pmx_ns2_sata0>;
- pinctrl-names = "default";
- status = "okay";
- nr-ports = <1>;
- };
- };
-
- gpio-leds {
- compatible = "gpio-leds";
-
- blue-sata {
- label = "ns2:blue:sata";
- gpios = <&gpio0 30 GPIO_ACTIVE_LOW>;
- linux,default-trigger = "disk-activity";
- };
- };
-};
-
-ðphy0 { reg = <0>; };
diff --git a/arch/arm/dts/kirkwood-ns2max.dts b/arch/arm/dts/kirkwood-ns2max.dts
deleted file mode 100644
index c0a087e..0000000
--- a/arch/arm/dts/kirkwood-ns2max.dts
+++ /dev/null
@@ -1,59 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0
-/dts-v1/;
-
-#include <dt-bindings/leds/leds-ns2.h>
-#include "kirkwood-ns2-common.dtsi"
-
-/ {
- model = "LaCie Network Space Max v2";
- compatible = "lacie,netspace_max_v2", "marvell,kirkwood-88f6281", "marvell,kirkwood";
-
- memory {
- device_type = "memory";
- reg = <0x00000000 0x10000000>;
- };
-
- ocp@f1000000 {
- sata@80000 {
- pinctrl-0 = <&pmx_ns2_sata0 &pmx_ns2_sata1>;
- pinctrl-names = "default";
- status = "okay";
- nr-ports = <2>;
- };
- };
-
- gpio_fan {
- compatible = "gpio-fan";
- gpios = <&gpio0 22 GPIO_ACTIVE_LOW
- &gpio0 7 GPIO_ACTIVE_LOW
- &gpio1 1 GPIO_ACTIVE_LOW
- &gpio0 23 GPIO_ACTIVE_LOW>;
- gpio-fan,speed-map =
- < 0 0
- 1500 15
- 1700 14
- 1800 13
- 2100 12
- 3100 11
- 3300 10
- 4300 9
- 5500 8>;
- alarm-gpios = <&gpio0 25 GPIO_ACTIVE_LOW>;
- };
-
- ns2-leds {
- compatible = "lacie,ns2-leds";
-
- blue-sata {
- label = "ns2:blue:sata";
- slow-gpio = <&gpio0 29 0>;
- cmd-gpio = <&gpio0 30 0>;
- modes-map = <NS_V2_LED_OFF 1 0
- NS_V2_LED_ON 0 1
- NS_V2_LED_ON 1 1
- NS_V2_LED_SATA 0 0>;
- };
- };
-};
-
-ðphy0 { reg = <8>; };
diff --git a/arch/arm/dts/kirkwood-ns2mini.dts b/arch/arm/dts/kirkwood-ns2mini.dts
deleted file mode 100644
index 5b9fa14..0000000
--- a/arch/arm/dts/kirkwood-ns2mini.dts
+++ /dev/null
@@ -1,60 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0
-/dts-v1/;
-
-#include <dt-bindings/leds/leds-ns2.h>
-#include "kirkwood-ns2-common.dtsi"
-
-/ {
- /* This machine is embedded in the first LaCie CloudBox product. */
- model = "LaCie Network Space Mini v2";
- compatible = "lacie,netspace_mini_v2", "marvell,kirkwood-88f6192", "marvell,kirkwood";
-
- memory {
- device_type = "memory";
- reg = <0x00000000 0x8000000>;
- };
-
- ocp@f1000000 {
- sata@80000 {
- pinctrl-0 = <&pmx_ns2_sata0>;
- pinctrl-names = "default";
- status = "okay";
- nr-ports = <1>;
- };
- };
-
- gpio_fan {
- compatible = "gpio-fan";
- gpios = <&gpio0 22 GPIO_ACTIVE_LOW
- &gpio0 7 GPIO_ACTIVE_LOW
- &gpio1 1 GPIO_ACTIVE_LOW
- &gpio0 23 GPIO_ACTIVE_LOW>;
- gpio-fan,speed-map =
- < 0 0
- 3000 15
- 3180 14
- 4140 13
- 4570 12
- 6760 11
- 7140 10
- 7980 9
- 9200 8>;
- alarm-gpios = <&gpio0 25 GPIO_ACTIVE_LOW>;
- };
-
- ns2-leds {
- compatible = "lacie,ns2-leds";
-
- blue-sata {
- label = "ns2:blue:sata";
- slow-gpio = <&gpio0 29 0>;
- cmd-gpio = <&gpio0 30 0>;
- modes-map = <NS_V2_LED_OFF 1 0
- NS_V2_LED_ON 0 1
- NS_V2_LED_ON 1 1
- NS_V2_LED_SATA 0 0>;
- };
- };
-};
-
-ðphy0 { reg = <0>; };
diff --git a/arch/arm/dts/kirkwood-nsa310s.dts b/arch/arm/dts/kirkwood-nsa310s.dts
deleted file mode 100644
index 09ee76c..0000000
--- a/arch/arm/dts/kirkwood-nsa310s.dts
+++ /dev/null
@@ -1,319 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0
-/*
- * Device tree file for the Zyxel NSA 310S NAS box.
- *
- * Copyright (c) 2015-2021, Tony Dinh <mibodhi@gmail.com>
- *
- * Based on
- * Copyright (c) 2014, Adam Baker <linux@baker-net.org.uk>
- * Based upon the board setup file created by Peter Schildmann
- */
-/dts-v1/;
-
-#include "kirkwood.dtsi"
-#include "kirkwood-6281.dtsi"
-
-/ {
- model = "Zyxel NSA310S";
- compatible = "zyxel,nsa320s", "marvell,kirkwood-88f6702", "marvell,kirkwood";
-
- memory {
- device_type = "memory";
- reg = <0x00000000 0x10000000>;
- };
-
- chosen {
- bootargs = "console=ttyS0,115200";
- stdout-path = &uart0;
- };
-
- ocp@f1000000 {
- pinctrl: pin-controller@10000 {
- pinctrl-names = "default";
-
- pmx_sata0: pmx-sata0 {
- marvell,pins ;
- marvell,function = "sata0";
- };
-
- pmx_sata1: pmx-sata1 {
- marvell,pins ;
- marvell,function = "sata1";
- };
-
- pmx_usb_power: pmx-usb-power {
- marvell,pins = "mpp21";
- marvell,function = "gpio";
- };
-
- pmx_pwr_off: pmx-pwr-off {
- marvell,pins = "mpp27";
- marvell,function = "gpio";
- };
-
- pmx_btn_reset: pmx-btn-reset {
- marvell,pins = "mpp24";
- marvell,function = "gpio";
- };
-
- pmx_btn_copy: pmx-btn-copy {
- marvell,pins = "mpp25";
- marvell,function = "gpio";
- };
-
- pmx_btn_power: pmx-btn-power {
- marvell,pins = "mpp26";
- marvell,function = "gpio";
- };
-
- pmx_led_hdd2_green: pmx-led-hdd2-green {
- marvell,pins = "mpp34";
- marvell,function = "gpio";
- };
-
- pmx_led_hdd2_red: pmx-led-hdd2-red {
- marvell,pins = "mpp12";
- marvell,function = "gpio";
- };
-
- pmx_led_usb_green: pmx-led-usb-green {
- marvell,pins = "mpp15";
- marvell,function = "gpio";
- };
-
- pmx_led_copy_green: pmx-led-copy-green {
- marvell,pins = "mpp22";
- marvell,function = "gpio";
- };
-
- pmx_led_copy_red: pmx-led-copy-red {
- marvell,pins = "mpp23";
- marvell,function = "gpio";
- };
-
- pmx_led_sys_green: pmx-led-sys-green {
- marvell,pins = "mpp28";
- marvell,function = "gpio";
- };
-
- pmx_led_sys_orange: pmx-led-sys-orange {
- marvell,pins = "mpp29";
- marvell,function = "gpio";
- };
-
- pmx_led_hdd1_green: pmx-led-hdd1-green {
- marvell,pins = "mpp16";
- marvell,function = "gpio";
- };
-
- pmx_led_hdd1_red: pmx-led-hdd1-red {
- marvell,pins = "mpp13";
- marvell,function = "gpio";
- };
-
- pmx_pwr_sata1: pmx-pwr-sata1 {
- marvell,pins = "mpp33";
- marvell,function = "gpio";
- };
- };
-
- serial@12000 {
- status = "ok";
- };
-
- sata@80000 {
- status = "okay";
- nr-ports = <1>;
- };
-
- rtc@10300 {
- status = "disabled";
- };
-
- i2c@11000 {
- status = "okay";
- ht1382: rtc@68 {
- compatible = "htk,ht1382";
- reg = <0x68>;
- };
- };
- };
-
- regulators {
- compatible = "simple-bus";
- #address-cells = <1>;
- #size-cells = <0>;
- pinctrl-names = "default";
- pinctrl-0 = <&pmx_usb_power &pmx_pwr_sata1>;
-
- usb0_power: regulator@1 {
- compatible = "regulator-fixed";
- reg = <1>;
- regulator-name = "USB Power";
- regulator-min-microvolt = <5000000>;
- regulator-max-microvolt = <5000000>;
- regulator-always-on;
- regulator-boot-on;
- enable-active-high;
- gpio = <&gpio0 21 GPIO_ACTIVE_HIGH>;
- };
-
- sata1_power: regulator@2 {
- compatible = "regulator-fixed";
- reg = <2>;
- regulator-name = "SATA1 Power";
- regulator-min-microvolt = <5000000>;
- regulator-max-microvolt = <5000000>;
- regulator-always-on;
- regulator-boot-on;
- enable-active-high;
- gpio = <&gpio1 1 GPIO_ACTIVE_HIGH>;
- };
- };
-
- gpio_poweroff {
- compatible = "gpio-poweroff";
- pinctrl-0 = <&pmx_pwr_off>;
- pinctrl-names = "default";
- gpios = <&gpio0 27 GPIO_ACTIVE_HIGH>;
- };
-
- gpio_keys {
- compatible = "gpio-keys";
- #address-cells = <1>;
- #size-cells = <0>;
- pinctrl-0 = <&pmx_btn_reset &pmx_btn_copy &pmx_btn_power>;
- pinctrl-names = "default";
-
- button@1 {
- label = "Power Button";
- linux,code = <KEY_POWER>;
- gpios = <&gpio0 26 GPIO_ACTIVE_HIGH>;
- };
- button@2 {
- label = "Copy Button";
- linux,code = <KEY_COPY>;
- gpios = <&gpio0 25 GPIO_ACTIVE_LOW>;
- };
- button@3 {
- label = "Reset Button";
- linux,code = <KEY_RESTART>;
- gpios = <&gpio0 24 GPIO_ACTIVE_LOW>;
- };
- };
-
- gpio-leds {
- compatible = "gpio-leds";
- pinctrl-0 = <&pmx_led_hdd2_green &pmx_led_hdd2_red
- &pmx_led_usb_green
- &pmx_led_sys_green &pmx_led_sys_orange
- &pmx_led_copy_green &pmx_led_copy_red
- &pmx_led_hdd1_green &pmx_led_hdd1_red>;
- pinctrl-names = "default";
-
- green-sys {
- label = "nsa310s:green:sys";
- gpios = <&gpio0 28 GPIO_ACTIVE_HIGH>;
- linux,default-trigger = "default-on";
- };
- orange-sys {
- label = "nsa310s:orange:sys";
- gpios = <&gpio0 29 GPIO_ACTIVE_HIGH>;
- };
- green-hdd1 {
- label = "nsa310s:green:hdd1";
- gpios = <&gpio0 16 GPIO_ACTIVE_HIGH>;
- };
- red-hdd1 {
- label = "nsa310s:red:hdd1";
- gpios = <&gpio0 13 GPIO_ACTIVE_HIGH>;
- };
- green-hdd2 {
- label = "nsa310s:green:hdd2";
- gpios = <&gpio1 2 GPIO_ACTIVE_HIGH>;
- };
- red-hdd2 {
- label = "nsa310s:red:hdd2";
- gpios = <&gpio0 12 GPIO_ACTIVE_HIGH>;
- };
- green-usb {
- label = "nsa310s:green:usb";
- gpios = <&gpio0 15 GPIO_ACTIVE_HIGH>;
- };
- green-copy {
- label = "nsa310s:green:copy";
- gpios = <&gpio0 22 GPIO_ACTIVE_HIGH>;
- linux,default-trigger = "ide-disk";
- };
- red-copy {
- label = "nsa310s:red:copy";
- gpios = <&gpio0 23 GPIO_ACTIVE_HIGH>;
- };
- };
-};
-
-&nand {
- status = "okay";
- chip-delay = <35>;
-
- partition@0 {
- label = "uboot";
- reg = <0x0000000 0x0100000>;
- };
- partition@100000 {
- label = "stock_uboot_env";
- reg = <0x0100000 0x0080000>;
- };
- partition@180000 {
- label = "key_store";
- reg = <0x0180000 0x0080000>;
- };
- partition@200000 {
- label = "info";
- reg = <0x0200000 0x0080000>;
- };
- partition@280000 {
- label = "etc";
- reg = <0x0280000 0x0a00000>;
- };
- partition@c80000 {
- label = "kernel_1";
- reg = <0x0c80000 0x0a00000>;
- };
- partition@1680000 {
- label = "rootfs1";
- reg = <0x1680000 0x2fc0000>;
- };
- partition@4640000 {
- label = "kernel_2";
- reg = <0x4640000 0x0a00000>;
- };
- partition@5040000 {
- label = "rootfs2";
- reg = <0x5040000 0x2fc0000>;
- };
-};
-
-&mdio {
- status = "okay";
- ethphy0: ethernet-phy@1 {
- compatible = "marvell,88e1510";
- reg = <1>;
- };
-};
-
-ð0 {
- status = "okay";
- ethernet0-port@0 {
- phy-handle = <ðphy0>;
- phy-mode = "rgmii";
- };
-};
-
-&pciec {
- status = "okay";
-};
-
-&pcie0 {
- status = "okay";
-};
diff --git a/arch/arm/dts/kirkwood-nsa325-u-boot.dtsi b/arch/arm/dts/kirkwood-nsa325-u-boot.dtsi
new file mode 100644
index 0000000..dec27b2
--- /dev/null
+++ b/arch/arm/dts/kirkwood-nsa325-u-boot.dtsi
@@ -0,0 +1,7 @@
+// SPDX-License-Identifier: GPL-2.0+
+
+&nand {
+ partition@0 {
+ /delete-property/ read-only;
+ };
+};
diff --git a/arch/arm/dts/kirkwood-nsa325.dts b/arch/arm/dts/kirkwood-nsa325.dts
deleted file mode 100644
index efc57cf..0000000
--- a/arch/arm/dts/kirkwood-nsa325.dts
+++ /dev/null
@@ -1,231 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+
-/* Device tree file for the Zyxel NSA 325 NAS box.
- *
- * Copyright (c) 2015, Hans Ulli Kroll <ulli.kroll@googlemail.com>
- *
- *
- * Based upon the board setup file created by Peter Schildmann
- */
-
-/dts-v1/;
-
-#include "kirkwood-nsa3x0-common.dtsi"
-
-/ {
- model = "ZyXEL NSA325";
- compatible = "zyxel,nsa325", "marvell,kirkwood-88f6282", "marvell,kirkwood";
-
- memory {
- device_type = "memory";
- reg = <0x00000000 0x20000000>;
- };
-
- chosen {
- bootargs = "console=ttyS0,115200";
- stdout-path = &uart0;
- };
-
- ocp@f1000000 {
- pinctrl: pin-controller@10000 {
- pinctrl-names = "default";
-
- pmx_led_hdd2_green: pmx-led-hdd2-green {
- marvell,pins = "mpp12";
- marvell,function = "gpio";
- };
-
- pmx_led_hdd2_red: pmx-led-hdd2-red {
- marvell,pins = "mpp13";
- marvell,function = "gpio";
- };
-
- pmx_mcu_data: pmx-mcu-data {
- marvell,pins = "mpp14";
- marvell,function = "gpio";
- };
-
- pmx_led_usb_green: pmx-led-usb-green {
- marvell,pins = "mpp15";
- marvell,function = "gpio";
- };
-
- pmx_mcu_clk: pmx-mcu-clk {
- marvell,pins = "mpp16";
- marvell,function = "gpio";
- };
-
- pmx_mcu_act: pmx-mcu-act {
- marvell,pins = "mpp17";
- marvell,function = "gpio";
- };
-
- pmx_led_sys_green: pmx-led-sys-green {
- marvell,pins = "mpp28";
- marvell,function = "gpio";
- };
-
- pmx_led_sys_orange: pmx-led-sys-orange {
- marvell,pins = "mpp29";
- marvell,function = "gpio";
- };
-
- pmx_led_hdd1_green: pmx-led-hdd1-green {
- marvell,pins = "mpp41";
- marvell,function = "gpio";
- };
-
- pmx_led_hdd1_red: pmx-led-hdd1-red {
- marvell,pins = "mpp42";
- marvell,function = "gpio";
- };
-
- pmx_htp: pmx-htp {
- marvell,pins = "mpp43";
- marvell,function = "gpio";
- };
-
- /*
- * Buzzer needs to be switched at around 1kHz so is
- * not compatible with the gpio-beeper driver.
- */
- pmx_buzzer: pmx-buzzer {
- marvell,pins = "mpp44";
- marvell,function = "gpio";
- };
-
- pmx_vid_b1: pmx-vid-b1 {
- marvell,pins = "mpp45";
- marvell,function = "gpio";
- };
-
- pmx_power_resume_data: pmx-power-resume-data {
- marvell,pins = "mpp47";
- marvell,function = "gpio";
- };
-
- pmx_power_resume_clk: pmx-power-resume-clk {
- marvell,pins = "mpp49";
- marvell,function = "gpio";
- };
-
- pmx_pwr_sata1: pmx-pwr-sata1 {
- marvell,pins = "mpp47";
- marvell,function = "gpio";
- };
- };
-
- /* This board uses the pcf8563 RTC instead of the SoC RTC */
- rtc@10300 {
- status = "disabled";
- };
-
- i2c@11000 {
- status = "okay";
-
- pcf8563: pcf8563@51 {
- compatible = "nxp,pcf8563";
- reg = <0x51>;
- };
- };
- };
-
- regulators {
- compatible = "simple-bus";
- #address-cells = <1>;
- #size-cells = <0>;
- pinctrl-0 = <&pmx_pwr_sata1>;
- pinctrl-names = "default";
-
- usb0_power: regulator@1 {
- enable-active-high;
- };
-
- sata1_power: regulator@2 {
- compatible = "regulator-fixed";
- reg = <2>;
- regulator-name = "SATA1 Power";
- regulator-min-microvolt = <5000000>;
- regulator-max-microvolt = <5000000>;
- regulator-always-on;
- regulator-boot-on;
- enable-active-high;
- gpio = <&gpio1 15 GPIO_ACTIVE_HIGH>;
- };
- };
-
- gpio-leds {
- compatible = "gpio-leds";
- pinctrl-0 = <&pmx_led_hdd2_green &pmx_led_hdd2_red
- &pmx_led_usb_green
- &pmx_led_sys_green &pmx_led_sys_orange
- &pmx_led_copy_green &pmx_led_copy_red
- &pmx_led_hdd1_green &pmx_led_hdd1_red>;
- pinctrl-names = "default";
-
- green-sys {
- label = "nsa325:green:sys";
- gpios = <&gpio0 28 GPIO_ACTIVE_HIGH>;
- };
- orange-sys {
- label = "nsa325:orange:sys";
- gpios = <&gpio0 29 GPIO_ACTIVE_HIGH>;
- };
- green-hdd1 {
- label = "nsa325:green:hdd1";
- gpios = <&gpio1 9 GPIO_ACTIVE_HIGH>;
- };
- red-hdd1 {
- label = "nsa325:red:hdd1";
- gpios = <&gpio1 10 GPIO_ACTIVE_HIGH>;
- };
- green-hdd2 {
- label = "nsa325:green:hdd2";
- gpios = <&gpio0 12 GPIO_ACTIVE_HIGH>;
- };
- red-hdd2 {
- label = "nsa325:red:hdd2";
- gpios = <&gpio0 13 GPIO_ACTIVE_HIGH>;
- };
- green-usb {
- label = "nsa325:green:usb";
- gpios = <&gpio0 15 GPIO_ACTIVE_HIGH>;
- };
- green-copy {
- label = "nsa325:green:copy";
- gpios = <&gpio1 7 GPIO_ACTIVE_HIGH>;
- };
- red-copy {
- label = "nsa325:red:copy";
- gpios = <&gpio1 8 GPIO_ACTIVE_HIGH>;
- };
-
- /* The following pins are currently not assigned to a driver,
- some of them should be configured as inputs.
- pinctrl-0 = <&pmx_mcu_data &pmx_mcu_clk &pmx_mcu_act
- &pmx_htp &pmx_vid_b1
- &pmx_power_resume_data &pmx_power_resume_clk>; */
- };
-
-};
-
-&mdio {
- status = "okay";
- ethphy0: ethernet-phy@1 {
- reg = <1>;
- };
-};
-
-ð0 {
- status = "okay";
- ethernet0-port@0 {
- phy-handle = <ðphy0>;
- };
-};
-
-&pciec {
- status = "okay";
-};
-
-&pcie0 {
- status = "okay";
-};
diff --git a/arch/arm/dts/kirkwood-nsa3x0-common.dtsi b/arch/arm/dts/kirkwood-nsa3x0-common.dtsi
deleted file mode 100644
index a21c50d..0000000
--- a/arch/arm/dts/kirkwood-nsa3x0-common.dtsi
+++ /dev/null
@@ -1,157 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0
-#include "kirkwood.dtsi"
-#include "kirkwood-6281.dtsi"
-
-/ {
- model = "ZyXEL NSA310";
-
- ocp@f1000000 {
- pinctrl: pin-controller@10000 {
-
- pmx_usb_power: pmx-usb-power {
- marvell,pins = "mpp21";
- marvell,function = "gpio";
- };
-
- pmx_pwr_off: pmx-pwr-off {
- marvell,pins = "mpp48";
- marvell,function = "gpio";
- };
-
- pmx_btn_reset: pmx-btn-reset {
- marvell,pins = "mpp36";
- marvell,function = "gpio";
- };
-
- pmx_btn_copy: pmx-btn-copy {
- marvell,pins = "mpp37";
- marvell,function = "gpio";
- };
-
- pmx_btn_power: pmx-btn-power {
- marvell,pins = "mpp46";
- marvell,function = "gpio";
- };
-
- pmx_led_copy_green: pmx-led-copy-green {
- marvell,pins = "mpp39";
- marvell,function = "gpio";
- };
-
- pmx_led_copy_red: pmx-led-copy-red {
- marvell,pins = "mpp40";
- marvell,function = "gpio";
- };
- };
-
- serial@12000 {
- status = "okay";
- };
-
- sata@80000 {
- status = "okay";
- nr-ports = <2>;
- };
- };
-
- gpio_poweroff {
- compatible = "gpio-poweroff";
- pinctrl-0 = <&pmx_pwr_off>;
- pinctrl-names = "default";
- gpios = <&gpio1 16 GPIO_ACTIVE_HIGH>;
- };
-
- gpio_keys {
- compatible = "gpio-keys";
- #address-cells = <1>;
- #size-cells = <0>;
- pinctrl-0 = <&pmx_btn_reset &pmx_btn_copy &pmx_btn_power>;
- pinctrl-names = "default";
-
- power {
- label = "Power Button";
- linux,code = <KEY_POWER>;
- gpios = <&gpio1 14 GPIO_ACTIVE_HIGH>;
- };
- copy {
- label = "Copy Button";
- linux,code = <KEY_COPY>;
- gpios = <&gpio1 5 GPIO_ACTIVE_LOW>;
- };
- reset {
- label = "Reset Button";
- linux,code = <KEY_RESTART>;
- gpios = <&gpio1 4 GPIO_ACTIVE_LOW>;
- };
- };
-
-
- regulators {
- compatible = "simple-bus";
- #address-cells = <1>;
- #size-cells = <0>;
- pinctrl-0 = <&pmx_usb_power>;
- pinctrl-names = "default";
-
- usb0_power: regulator@1 {
- compatible = "regulator-fixed";
- reg = <1>;
- regulator-name = "USB Power";
- regulator-min-microvolt = <5000000>;
- regulator-max-microvolt = <5000000>;
- regulator-always-on;
- regulator-boot-on;
- gpio = <&gpio0 21 GPIO_ACTIVE_HIGH>;
- };
- };
-};
-
-&nand {
- status = "okay";
- chip-delay = <35>;
-
- partition@0 {
- label = "uboot";
- reg = <0x0000000 0x0100000>;
- };
- partition@100000 {
- label = "uboot_env";
- reg = <0x0100000 0x0080000>;
- };
- partition@180000 {
- label = "key_store";
- reg = <0x0180000 0x0080000>;
- };
- partition@200000 {
- label = "info";
- reg = <0x0200000 0x0080000>;
- };
- partition@280000 {
- label = "etc";
- reg = <0x0280000 0x0a00000>;
- };
- partition@c80000 {
- label = "kernel_1";
- reg = <0x0c80000 0x0a00000>;
- };
- partition@1680000 {
- label = "rootfs1";
- reg = <0x1680000 0x2fc0000>;
- };
- partition@4640000 {
- label = "kernel_2";
- reg = <0x4640000 0x0a00000>;
- };
- partition@5040000 {
- label = "rootfs2";
- reg = <0x5040000 0x2fc0000>;
- };
-};
-
-&pciec {
- status = "okay";
-};
-
-&pcie0 {
- status = "okay";
-};
diff --git a/arch/arm/dts/kirkwood-openrd-base.dts b/arch/arm/dts/kirkwood-openrd-base.dts
deleted file mode 100644
index 094191e..0000000
--- a/arch/arm/dts/kirkwood-openrd-base.dts
+++ /dev/null
@@ -1,39 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0
-/*
- * Marvell OpenRD Base Board Description
- *
- * Andrew Lunn <andrew@lunn.ch>
- *
- * This file contains the definitions that are specific to OpenRD
- * base variant of the Marvell Kirkwood Development Board.
- */
-
-/dts-v1/;
-
-#include "kirkwood-openrd.dtsi"
-
-/ {
- model = "OpenRD Base";
- compatible = "marvell,openrd-base", "marvell,openrd", "marvell,kirkwood-88f6281", "marvell,kirkwood";
-
- ocp@f1000000 {
- serial@12100 {
- status = "okay";
- };
- };
-};
-
-&mdio {
- status = "okay";
-
- ethphy0: ethernet-phy@8 {
- reg = <8>;
- };
-};
-
-ð0 {
- status = "okay";
- ethernet0-port@0 {
- phy-handle = <ðphy0>;
- };
-};
diff --git a/arch/arm/dts/kirkwood-openrd-client.dts b/arch/arm/dts/kirkwood-openrd-client.dts
deleted file mode 100644
index 74dc23d..0000000
--- a/arch/arm/dts/kirkwood-openrd-client.dts
+++ /dev/null
@@ -1,73 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0
-/*
- * Marvell OpenRD Client Board Description
- *
- * Andrew Lunn <andrew@lunn.ch>
- *
- * This file contains the definitions that are specific to OpenRD
- * client variant of the Marvell Kirkwood Development Board.
- */
-
-/dts-v1/;
-
-#include "kirkwood-openrd.dtsi"
-
-/ {
- model = "OpenRD Client";
- compatible = "marvell,openrd-client", "marvell,openrd", "marvell,kirkwood-88f6281", "marvell,kirkwood";
-
- ocp@f1000000 {
- audio-controller@a0000 {
- status = "okay";
- };
- i2c@11000 {
- status = "okay";
- clock-frequency = <400000>;
-
- cs42l51: cs42l51@4a {
- compatible = "cirrus,cs42l51";
- reg = <0x4a>;
- #sound-dai-cells = <0>;
- };
- };
- };
-
- sound {
- compatible = "simple-audio-card";
- simple-audio-card,format = "i2s";
- simple-audio-card,mclk-fs = <256>;
-
- simple-audio-card,cpu {
- sound-dai = <&audio0 0>;
- };
-
- simple-audio-card,codec {
- sound-dai = <&cs42l51>;
- };
- };
-};
-
-&mdio {
- status = "okay";
-
- ethphy0: ethernet-phy@8 {
- reg = <8>;
- };
- ethphy1: ethernet-phy@24 {
- reg = <24>;
- };
-};
-
-ð0 {
- status = "okay";
- ethernet0-port@0 {
- phy-handle = <ðphy0>;
- };
-};
-
-ð1 {
- status = "okay";
- ethernet1-port@0 {
- phy-handle = <ðphy1>;
- };
-};
diff --git a/arch/arm/dts/kirkwood-openrd-ultimate.dts b/arch/arm/dts/kirkwood-openrd-ultimate.dts
deleted file mode 100644
index 888e133..0000000
--- a/arch/arm/dts/kirkwood-openrd-ultimate.dts
+++ /dev/null
@@ -1,55 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0
-/*
- * Marvell OpenRD Ultimate Board Description
- *
- * Andrew Lunn <andrew@lunn.ch>
- *
- * This file contains the definitions that are specific to OpenRD
- * ultimate variant of the Marvell Kirkwood Development Board.
- */
-
-/dts-v1/;
-
-#include "kirkwood-openrd.dtsi"
-
-/ {
- model = "OpenRD Ultimate";
- compatible = "marvell,openrd-ultimate", "marvell,openrd", "marvell,kirkwood-88f6281", "marvell,kirkwood";
-
- ocp@f1000000 {
- i2c@11000 {
- status = "okay";
- clock-frequency = <400000>;
-
- cs42l51: cs42l51@4a {
- compatible = "cirrus,cs42l51";
- reg = <0x4a>;
- };
- };
- };
-};
-
-&mdio {
- status = "okay";
-
- ethphy0: ethernet-phy@0 {
- reg = <0>;
- };
- ethphy1: ethernet-phy@1 {
- reg = <1>;
- };
-};
-
-ð0 {
- status = "okay";
- ethernet0-port@0 {
- phy-handle = <ðphy0>;
- };
-};
-
-ð1 {
- status = "okay";
- ethernet1-port@0 {
- phy-handle = <ðphy1>;
- };
-};
diff --git a/arch/arm/dts/kirkwood-openrd.dtsi b/arch/arm/dts/kirkwood-openrd.dtsi
deleted file mode 100644
index 47f03c6..0000000
--- a/arch/arm/dts/kirkwood-openrd.dtsi
+++ /dev/null
@@ -1,122 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0
-/*
- * Marvell OpenRD (Base|Client|Ultimate) Board Description
- *
- * Andrew Lunn <andrew@lunn.ch>
- *
- * This file contains the definitions that are common between the three
- * variants of the Marvell Kirkwood Development Board.
- */
-
-#include "kirkwood.dtsi"
-#include "kirkwood-6281.dtsi"
-
-/ {
- memory {
- device_type = "memory";
- reg = <0x00000000 0x20000000>;
- };
-
- chosen {
- bootargs = "console=ttyS0,115200n8";
- stdout-path = &uart0;
- };
-
- ocp@f1000000 {
- pinctrl: pin-controller@10000 {
- pinctrl-0 = <&pmx_select28 &pmx_sdio_cd &pmx_select34>;
- pinctrl-names = "default";
-
- pmx_select28: pmx-select-rs232-rs485 {
- marvell,pins = "mpp28";
- marvell,function = "gpio";
- };
- pmx_sdio_cd: pmx-sdio-cd {
- marvell,pins = "mpp29";
- marvell,function = "gpio";
- };
- pmx_select34: pmx-select-uart-sd {
- marvell,pins = "mpp34";
- marvell,function = "gpio";
- };
- };
- serial@12000 {
- status = "okay";
-
- };
- sata@80000 {
- status = "okay";
- nr-ports = <2>;
- };
- mvsdio@90000 {
- status = "okay";
- cd-gpios = <&gpio0 29 9>;
- };
- gpio@10100 {
- p28 {
- gpio-hog;
- gpios = <28 GPIO_ACTIVE_HIGH>;
- /*
- * SelRS232or485 selects between RS-232 or RS-485
- * mode for the second UART.
- *
- * Low: RS-232
- * High: RS-485
- *
- * To use the second UART, you need to change also
- * the SelUARTorSD.
- */
- output-low;
- line-name = "SelRS232or485";
- };
- };
- gpio@10140 {
- p2 {
- gpio-hog;
- gpios = <2 GPIO_ACTIVE_HIGH>;
- /*
- * SelUARTorSD selects between the second UART
- * (serial@12100) and SD (mvsdio@90000).
- *
- * Low: UART
- * High: SD
- *
- * When changing this line make sure the newly
- * selected device node is enabled and the
- * previously selected device node is disabled.
- */
- output-high; /* Select SD by default */
- line-name = "SelUARTorSD";
- };
- };
- };
-};
-
-&nand {
- status = "okay";
- pinctrl-0 = <&pmx_nand>;
- pinctrl-names = "default";
-
- partition@0 {
- label = "u-boot";
- reg = <0x0000000 0x100000>;
- };
-
- partition@100000 {
- label = "uImage";
- reg = <0x0100000 0x400000>;
- };
-
- partition@600000 {
- label = "root";
- reg = <0x0600000 0x1FA00000>;
- };
-};
-
-&pciec {
- status = "okay";
-};
-
-&pcie0 {
- status = "okay";
-};
diff --git a/arch/arm/dts/kirkwood-pogo_e02.dts b/arch/arm/dts/kirkwood-pogo_e02.dts
deleted file mode 100644
index f9e95e5..0000000
--- a/arch/arm/dts/kirkwood-pogo_e02.dts
+++ /dev/null
@@ -1,132 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0
-/*
- * kirkwood-pogo_e02.dts - Device tree file for Pogoplug E02
- *
- * Copyright (C) 2015 Christoph Junghans <ottxor@gentoo.org>
- *
- * based on information of dts files from
- * Arch Linux ARM by Oleg Rakhmanov <moonman.ca@gmail.com>
- * OpenWrt by Felix Kaechele <heffer@fedoraproject.org>
- *
- */
-
-/dts-v1/;
-
-#include "kirkwood.dtsi"
-#include "kirkwood-6281.dtsi"
-
-/ {
- model = "Cloud Engines Pogoplug E02";
- compatible = "cloudengines,pogoe02", "marvell,kirkwood-88f6281",
- "marvell,kirkwood";
-
- memory {
- device_type = "memory";
- reg = <0x00000000 0x10000000>;
- };
-
- chosen {
- bootargs = "console=ttyS0,115200n8";
- stdout-path = &uart0;
- };
-
- gpio-leds {
- compatible = "gpio-leds";
-
- health {
- label = "pogo_e02:green:health";
- gpios = <&gpio1 16 GPIO_ACTIVE_LOW>;
- default-state = "keep";
- };
- fault {
- label = "pogo_e02:orange:fault";
- gpios = <&gpio1 17 GPIO_ACTIVE_LOW>;
- };
- };
-
- regulators {
- compatible = "simple-bus";
- #address-cells = <1>;
- #size-cells = <0>;
- pinctrl-0 = <&pmx_usb_power_enable>;
- pinctrl-names = "default";
-
- usb_power: regulator@1 {
- compatible = "regulator-fixed";
- reg = <1>;
- regulator-name = "USB Power";
- regulator-min-microvolt = <5000000>;
- regulator-max-microvolt = <5000000>;
- enable-active-high;
- regulator-always-on;
- regulator-boot-on;
- gpio = <&gpio0 29 GPIO_ACTIVE_HIGH>;
- };
- };
-};
-
-&pinctrl {
- pinctrl-0 = < &pmx_usb_power_enable &pmx_led_orange
- &pmx_led_green >;
- pinctrl-names = "default";
-
- pmx_usb_power_enable: pmx-usb-power-enable {
- marvell,pins = "mpp29";
- marvell,function = "gpio";
- };
-
- pmx_led_green: pmx-led-green {
- marvell,pins = "mpp48";
- marvell,function = "gpio";
- };
-
- pmx_led_orange: pmx-led-orange {
- marvell,pins = "mpp49";
- marvell,function = "gpio";
- };
-};
-
-&uart0 {
- status = "okay";
-};
-
-&nand {
- chip-delay = <40>;
- status = "okay";
-
- partition@0 {
- label = "u-boot";
- reg = <0x0000000 0x100000>;
- read-only;
- };
-
- partition@100000 {
- label = "uImage";
- reg = <0x0100000 0x400000>;
- };
-
- partition@500000 {
- label = "pogoplug";
- reg = <0x0500000 0x2000000>;
- };
-
- partition@2500000 {
- label = "root";
- reg = <0x02500000 0x5b00000>;
- };
-};
-
-&mdio {
- status = "okay";
-
- ethphy0: ethernet-phy@0 {
- reg = <0>;
- };
-};
-
-ð0 {
- status = "okay";
- ethernet0-port@0 {
- phy-handle = <ðphy0>;
- };
-};
diff --git a/arch/arm/dts/kirkwood-pogoplug-series-4.dts b/arch/arm/dts/kirkwood-pogoplug-series-4.dts
deleted file mode 100644
index 5aa4669..0000000
--- a/arch/arm/dts/kirkwood-pogoplug-series-4.dts
+++ /dev/null
@@ -1,180 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0
-/*
- * kirkwood-pogoplug-series-4.dts - Device tree file for PogoPlug Series 4
- * inspired by the board files made by Kevin Mihelich for ArchLinux,
- * and their DTS file.
- *
- * Copyright (C) 2015 Linus Walleij <linus.walleij@linaro.org>
- */
-
-/dts-v1/;
-
-#include "kirkwood.dtsi"
-#include "kirkwood-6192.dtsi"
-#include <dt-bindings/input/linux-event-codes.h>
-
-/ {
- model = "Cloud Engines PogoPlug Series 4";
- compatible = "cloudengines,pogoplugv4", "marvell,kirkwood-88f6192",
- "marvell,kirkwood";
-
- memory {
- device_type = "memory";
- reg = <0x00000000 0x08000000>;
- };
-
- chosen {
- stdout-path = "uart0:115200n8";
- };
-
- gpio_keys {
- compatible = "gpio-keys";
- #address-cells = <1>;
- #size-cells = <0>;
- pinctrl-0 = <&pmx_button_eject>;
- pinctrl-names = "default";
-
- eject {
- debounce-interval = <50>;
- wakeup-source;
- linux,code = <KEY_EJECTCD>;
- label = "Eject Button";
- gpios = <&gpio0 29 GPIO_ACTIVE_LOW>;
- };
- };
-
- gpio-leds {
- compatible = "gpio-leds";
- pinctrl-0 = <&pmx_led_green &pmx_led_red>;
- pinctrl-names = "default";
-
- health {
- label = "pogoplugv4:green:health";
- gpios = <&gpio0 22 GPIO_ACTIVE_LOW>;
- default-state = "on";
- };
- fault {
- label = "pogoplugv4:red:fault";
- gpios = <&gpio0 24 GPIO_ACTIVE_LOW>;
- };
- };
-};
-
-&pinctrl {
- pmx_sata0: pmx-sata0 {
- marvell,pins = "mpp21";
- marvell,function = "sata0";
- };
-
- pmx_sata1: pmx-sata1 {
- marvell,pins = "mpp20";
- marvell,function = "sata1";
- };
-
- pmx_sdio_cd: pmx-sdio-cd {
- marvell,pins = "mpp27";
- marvell,function = "gpio";
- };
-
- pmx_sdio_wp: pmx-sdio-wp {
- marvell,pins = "mpp28";
- marvell,function = "gpio";
- };
-
- pmx_button_eject: pmx-button-eject {
- marvell,pins = "mpp29";
- marvell,function = "gpio";
- };
-
- pmx_led_green: pmx-led-green {
- marvell,pins = "mpp22";
- marvell,function = "gpio";
- };
-
- pmx_led_red: pmx-led-red {
- marvell,pins = "mpp24";
- marvell,function = "gpio";
- };
-};
-
-&uart0 {
- status = "okay";
-};
-
-/*
- * This PCIE controller has a USB 3.0 XHCI controller at 1,0
- */
-&pciec {
- status = "okay";
-};
-
-&pcie0 {
- status = "okay";
-};
-
-&sata {
- status = "okay";
- pinctrl-0 = <&pmx_sata0 &pmx_sata1>;
- pinctrl-names = "default";
- nr-ports = <1>;
-};
-
-&sdio {
- status = "okay";
- pinctrl-0 = <&pmx_sdio &pmx_sdio_cd &pmx_sdio_wp>;
- pinctrl-names = "default";
- cd-gpios = <&gpio0 27 GPIO_ACTIVE_LOW>;
- wp-gpios = <&gpio0 28 GPIO_ACTIVE_HIGH>;
-};
-
-&nand {
- /* 128 MiB of NAND flash */
- chip-delay = <40>;
- status = "okay";
- partitions {
- compatible = "fixed-partitions";
- #address-cells = <1>;
- #size-cells = <1>;
-
- partition@0 {
- label = "u-boot";
- reg = <0x00000000 0x200000>;
- read-only;
- };
-
- partition@200000 {
- label = "uImage";
- reg = <0x00200000 0x300000>;
- };
-
- partition@500000 {
- label = "uImage2";
- reg = <0x00500000 0x300000>;
- };
-
- partition@800000 {
- label = "failsafe";
- reg = <0x00800000 0x800000>;
- };
-
- partition@1000000 {
- label = "root";
- reg = <0x01000000 0x7000000>;
- };
- };
-};
-
-&mdio {
- status = "okay";
-
- ethphy0: ethernet-phy@0 {
- reg = <0>;
- };
-};
-
-ð0 {
- status = "okay";
- ethernet0-port@0 {
- phy-handle = <ðphy0>;
- };
-};
diff --git a/arch/arm/dts/kirkwood-sheevaplug-common.dtsi b/arch/arm/dts/kirkwood-sheevaplug-common.dtsi
deleted file mode 100644
index 0a698d3..0000000
--- a/arch/arm/dts/kirkwood-sheevaplug-common.dtsi
+++ /dev/null
@@ -1,104 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0
-/*
- * kirkwood-sheevaplug-common.dtsi - Common parts for Sheevaplugs
- *
- * Copyright (C) 2013 Simon Baatz <gmbnomis@gmail.com>
- */
-
-#include "kirkwood.dtsi"
-#include "kirkwood-6281.dtsi"
-
-/ {
- memory {
- device_type = "memory";
- reg = <0x00000000 0x20000000>;
- };
-
- chosen {
- bootargs = "console=ttyS0,115200n8 earlyprintk";
- stdout-path = &uart0;
- };
-
- ocp@f1000000 {
- pinctrl: pin-controller@10000 {
-
- pmx_usb_power_enable: pmx-usb-power-enable {
- marvell,pins = "mpp29";
- marvell,function = "gpio";
- };
- pmx_led_red: pmx-led-red {
- marvell,pins = "mpp46";
- marvell,function = "gpio";
- };
- pmx_led_blue: pmx-led-blue {
- marvell,pins = "mpp49";
- marvell,function = "gpio";
- };
- pmx_sdio_cd: pmx-sdio-cd {
- marvell,pins = "mpp44";
- marvell,function = "gpio";
- };
- pmx_sdio_wp: pmx-sdio-wp {
- marvell,pins = "mpp47";
- marvell,function = "gpio";
- };
- };
- serial@12000 {
- status = "okay";
- };
- };
-
- regulators {
- compatible = "simple-bus";
- #address-cells = <1>;
- #size-cells = <0>;
- pinctrl-0 = <&pmx_usb_power_enable>;
- pinctrl-names = "default";
-
- usb_power: regulator@1 {
- compatible = "regulator-fixed";
- reg = <1>;
- regulator-name = "USB Power";
- regulator-min-microvolt = <5000000>;
- regulator-max-microvolt = <5000000>;
- enable-active-high;
- regulator-always-on;
- regulator-boot-on;
- gpio = <&gpio0 29 0>;
- };
- };
-};
-
-&nand {
- status = "okay";
-
- partition@0 {
- label = "u-boot";
- reg = <0x0000000 0x100000>;
- };
-
- partition@100000 {
- label = "uImage";
- reg = <0x0100000 0x400000>;
- };
-
- partition@500000 {
- label = "root";
- reg = <0x0500000 0x1fb00000>;
- };
-};
-
-&mdio {
- status = "okay";
-
- ethphy0: ethernet-phy@0 {
- reg = <0>;
- };
-};
-
-ð0 {
- status = "okay";
- ethernet0-port@0 {
- phy-handle = <ðphy0>;
- };
-};
diff --git a/arch/arm/dts/kirkwood-sheevaplug.dts b/arch/arm/dts/kirkwood-sheevaplug.dts
deleted file mode 100644
index c73cc90..0000000
--- a/arch/arm/dts/kirkwood-sheevaplug.dts
+++ /dev/null
@@ -1,42 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0
-/*
- * kirkwood-sheevaplug.dts - Device tree file for Sheevaplug
- *
- * Copyright (C) 2013 Simon Baatz <gmbnomis@gmail.com>
- */
-
-/dts-v1/;
-
-#include "kirkwood-sheevaplug-common.dtsi"
-
-/ {
- model = "Globalscale Technologies SheevaPlug";
- compatible = "globalscale,sheevaplug", "marvell,kirkwood-88f6281", "marvell,kirkwood";
-
- ocp@f1000000 {
- mvsdio@90000 {
- pinctrl-0 = <&pmx_sdio>;
- pinctrl-names = "default";
- status = "okay";
- /* No CD or WP GPIOs */
- broken-cd;
- };
- };
-
- gpio-leds {
- compatible = "gpio-leds";
- pinctrl-0 = <&pmx_led_blue &pmx_led_red>;
- pinctrl-names = "default";
-
- health {
- label = "sheevaplug:blue:health";
- gpios = <&gpio1 17 GPIO_ACTIVE_LOW>;
- default-state = "keep";
- };
-
- misc {
- label = "sheevaplug:red:misc";
- gpios = <&gpio1 14 GPIO_ACTIVE_LOW>;
- };
- };
-};
diff --git a/arch/arm/dts/kirkwood-synology.dtsi b/arch/arm/dts/kirkwood-synology.dtsi
deleted file mode 100644
index c97ed29..0000000
--- a/arch/arm/dts/kirkwood-synology.dtsi
+++ /dev/null
@@ -1,855 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0
-/*
- * Nodes for Marvell 628x Synology devices
- *
- * Andrew Lunn <andrew@lunn.ch>
- * Ben Peddell <klightspeed@killerwolves.net>
- *
- */
-
-/ {
- ocp@f1000000 {
- pinctrl: pin-controller@10000 {
- pmx_alarmled_12: pmx-alarmled-12 {
- marvell,pins = "mpp12";
- marvell,function = "gpio";
- };
-
- pmx_fanctrl_15: pmx-fanctrl-15 {
- marvell,pins = "mpp15";
- marvell,function = "gpio";
- };
-
- pmx_fanctrl_16: pmx-fanctrl-16 {
- marvell,pins = "mpp16";
- marvell,function = "gpio";
- };
-
- pmx_fanctrl_17: pmx-fanctrl-17 {
- marvell,pins = "mpp17";
- marvell,function = "gpio";
- };
-
- pmx_fanalarm_18: pmx-fanalarm-18 {
- marvell,pins = "mpp18";
- marvell,function = "gpo";
- };
-
- pmx_hddled_20: pmx-hddled-20 {
- marvell,pins = "mpp20";
- marvell,function = "gpio";
- };
-
- pmx_hddled_21: pmx-hddled-21 {
- marvell,pins = "mpp21";
- marvell,function = "gpio";
- };
-
- pmx_hddled_22: pmx-hddled-22 {
- marvell,pins = "mpp22";
- marvell,function = "gpio";
- };
-
- pmx_hddled_23: pmx-hddled-23 {
- marvell,pins = "mpp23";
- marvell,function = "gpio";
- };
-
- pmx_hddled_24: pmx-hddled-24 {
- marvell,pins = "mpp24";
- marvell,function = "gpio";
- };
-
- pmx_hddled_25: pmx-hddled-25 {
- marvell,pins = "mpp25";
- marvell,function = "gpio";
- };
-
- pmx_hddled_26: pmx-hddled-26 {
- marvell,pins = "mpp26";
- marvell,function = "gpio";
- };
-
- pmx_hddled_27: pmx-hddled-27 {
- marvell,pins = "mpp27";
- marvell,function = "gpio";
- };
-
- pmx_hddled_28: pmx-hddled-28 {
- marvell,pins = "mpp28";
- marvell,function = "gpio";
- };
-
- pmx_hdd1_pwr_29: pmx-hdd1-pwr-29 {
- marvell,pins = "mpp29";
- marvell,function = "gpio";
- };
-
- pmx_hdd1_pwr_30: pmx-hdd-pwr-30 {
- marvell,pins = "mpp30";
- marvell,function = "gpio";
- };
-
- pmx_hdd2_pwr_31: pmx-hdd2-pwr-31 {
- marvell,pins = "mpp31";
- marvell,function = "gpio";
- };
-
- pmx_fanctrl_32: pmx-fanctrl-32 {
- marvell,pins = "mpp32";
- marvell,function = "gpio";
- };
-
- pmx_fanctrl_33: pmx-fanctrl-33 {
- marvell,pins = "mpp33";
- marvell,function = "gpo";
- };
-
- pmx_fanctrl_34: pmx-fanctrl-34 {
- marvell,pins = "mpp34";
- marvell,function = "gpio";
- };
-
- pmx_hdd2_pwr_34: pmx-hdd2-pwr-34 {
- marvell,pins = "mpp34";
- marvell,function = "gpio";
- };
-
- pmx_fanalarm_35: pmx-fanalarm-35 {
- marvell,pins = "mpp35";
- marvell,function = "gpio";
- };
-
- pmx_hddled_36: pmx-hddled-36 {
- marvell,pins = "mpp36";
- marvell,function = "gpio";
- };
-
- pmx_hddled_37: pmx-hddled-37 {
- marvell,pins = "mpp37";
- marvell,function = "gpio";
- };
-
- pmx_hddled_38: pmx-hddled-38 {
- marvell,pins = "mpp38";
- marvell,function = "gpio";
- };
-
- pmx_hddled_39: pmx-hddled-39 {
- marvell,pins = "mpp39";
- marvell,function = "gpio";
- };
-
- pmx_hddled_40: pmx-hddled-40 {
- marvell,pins = "mpp40";
- marvell,function = "gpio";
- };
-
- pmx_hddled_41: pmx-hddled-41 {
- marvell,pins = "mpp41";
- marvell,function = "gpio";
- };
-
- pmx_hddled_42: pmx-hddled-42 {
- marvell,pins = "mpp42";
- marvell,function = "gpio";
- };
-
- pmx_hddled_43: pmx-hddled-43 {
- marvell,pins = "mpp43";
- marvell,function = "gpio";
- };
-
- pmx_hddled_44: pmx-hddled-44 {
- marvell,pins = "mpp44";
- marvell,function = "gpio";
- };
-
- pmx_hddled_45: pmx-hddled-45 {
- marvell,pins = "mpp45";
- marvell,function = "gpio";
- };
-
- pmx_hdd3_pwr_44: pmx-hdd3-pwr-44 {
- marvell,pins = "mpp44";
- marvell,function = "gpio";
- };
-
- pmx_hdd4_pwr_45: pmx-hdd4-pwr-45 {
- marvell,pins = "mpp45";
- marvell,function = "gpio";
- };
-
- pmx_fanalarm_44: pmx-fanalarm-44 {
- marvell,pins = "mpp44";
- marvell,function = "gpio";
- };
-
- pmx_fanalarm_45: pmx-fanalarm-45 {
- marvell,pins = "mpp45";
- marvell,function = "gpio";
- };
- };
-
- rtc@10300 {
- status = "disabled";
- };
-
- spi@10600 {
- status = "okay";
-
- m25p80@0 {
- #address-cells = <1>;
- #size-cells = <1>;
- compatible = "st,m25p80", "jedec,spi-nor";
- reg = <0>;
- spi-max-frequency = <20000000>;
- mode = <0>;
-
- partition@0 {
- reg = <0x00000000 0x00080000>;
- label = "RedBoot";
- };
-
- partition@80000 {
- reg = <0x00080000 0x00200000>;
- label = "zImage";
- };
-
- partition@280000 {
- reg = <0x00280000 0x00140000>;
- label = "rd.gz";
- };
-
- partition@3c0000 {
- reg = <0x003c0000 0x00010000>;
- label = "vendor";
- };
-
- partition@3d0000 {
- reg = <0x003d0000 0x00020000>;
- label = "RedBoot config";
- };
-
- partition@3f0000 {
- reg = <0x003f0000 0x00010000>;
- label = "FIS directory";
- };
- };
- };
-
- i2c@11000 {
- status = "okay";
- clock-frequency = <400000>;
-
- rs5c372: rs5c372@32 {
- status = "disabled";
- compatible = "ricoh,rs5c372";
- reg = <0x32>;
- };
-
- s35390a: s35390a@30 {
- status = "disabled";
- compatible = "sii,s35390a";
- reg = <0x30>;
- };
- };
-
- serial@12000 {
- status = "okay";
- };
-
- serial@12100 {
- status = "okay";
- };
-
- poweroff@12100 {
- compatible = "synology,power-off";
- reg = <0x12100 0x100>;
- clocks = <&gate_clk 7>;
- };
-
- sata@80000 {
- pinctrl-0 = <&pmx_sata0 &pmx_sata1>;
- pinctrl-names = "default";
- status = "okay";
- nr-ports = <2>;
- };
- };
-
- gpio-fan-150-32-35 {
- status = "disabled";
- compatible = "gpio-fan";
- pinctrl-0 = <&pmx_fanctrl_32 &pmx_fanctrl_33 &pmx_fanctrl_34
- &pmx_fanalarm_35>;
- pinctrl-names = "default";
- gpios = <&gpio1 0 GPIO_ACTIVE_HIGH
- &gpio1 1 GPIO_ACTIVE_HIGH
- &gpio1 2 GPIO_ACTIVE_HIGH>;
- gpio-fan,speed-map = < 0 0
- 2200 1
- 2500 2
- 3000 4
- 3300 3
- 3700 5
- 3800 6
- 4200 7 >;
- };
-
- gpio-fan-150-15-18 {
- status = "disabled";
- compatible = "gpio-fan";
- pinctrl-0 = <&pmx_fanctrl_15 &pmx_fanctrl_16 &pmx_fanctrl_17
- &pmx_fanalarm_18>;
- pinctrl-names = "default";
- gpios = <&gpio0 15 GPIO_ACTIVE_HIGH
- &gpio0 16 GPIO_ACTIVE_HIGH
- &gpio0 17 GPIO_ACTIVE_HIGH>;
- alarm-gpios = <&gpio0 18 GPIO_ACTIVE_HIGH>;
- gpio-fan,speed-map = < 0 0
- 2200 1
- 2500 2
- 3000 4
- 3300 3
- 3700 5
- 3800 6
- 4200 7 >;
- };
-
- gpio-fan-100-32-35 {
- status = "disabled";
- compatible = "gpio-fan";
- pinctrl-0 = <&pmx_fanctrl_32 &pmx_fanctrl_33 &pmx_fanctrl_34
- &pmx_fanalarm_35>;
- pinctrl-names = "default";
- gpios = <&gpio1 0 GPIO_ACTIVE_HIGH
- &gpio1 1 GPIO_ACTIVE_HIGH
- &gpio1 2 GPIO_ACTIVE_HIGH>;
- alarm-gpios = <&gpio1 3 GPIO_ACTIVE_HIGH>;
- gpio-fan,speed-map = < 0 0
- 2500 1
- 3100 2
- 3800 3
- 4600 4
- 4800 5
- 4900 6
- 5000 7 >;
- };
-
- gpio-fan-100-15-18 {
- status = "disabled";
- compatible = "gpio-fan";
- pinctrl-0 = <&pmx_fanctrl_15 &pmx_fanctrl_16 &pmx_fanctrl_17
- &pmx_fanalarm_18>;
- pinctrl-names = "default";
- gpios = <&gpio0 15 GPIO_ACTIVE_HIGH
- &gpio0 16 GPIO_ACTIVE_HIGH
- &gpio0 17 GPIO_ACTIVE_HIGH>;
- alarm-gpios = <&gpio0 18 GPIO_ACTIVE_HIGH>;
- gpio-fan,speed-map = < 0 0
- 2500 1
- 3100 2
- 3800 3
- 4600 4
- 4800 5
- 4900 6
- 5000 7 >;
- };
-
- gpio-fan-100-15-35-1 {
- status = "disabled";
- compatible = "gpio-fan";
- pinctrl-0 = <&pmx_fanctrl_15 &pmx_fanctrl_16 &pmx_fanctrl_17
- &pmx_fanalarm_35>;
- pinctrl-names = "default";
- gpios = <&gpio0 15 GPIO_ACTIVE_HIGH
- &gpio0 16 GPIO_ACTIVE_HIGH
- &gpio0 17 GPIO_ACTIVE_HIGH>;
- alarm-gpios = <&gpio1 3 GPIO_ACTIVE_HIGH>;
- gpio-fan,speed-map = < 0 0
- 2500 1
- 3100 2
- 3800 3
- 4600 4
- 4800 5
- 4900 6
- 5000 7 >;
- };
-
- gpio-fan-100-15-35-3 {
- status = "disabled";
- compatible = "gpio-fan";
- pinctrl-0 = <&pmx_fanctrl_15 &pmx_fanctrl_16 &pmx_fanctrl_17
- &pmx_fanalarm_35 &pmx_fanalarm_44 &pmx_fanalarm_45>;
- pinctrl-names = "default";
- gpios = <&gpio0 15 GPIO_ACTIVE_HIGH
- &gpio0 16 GPIO_ACTIVE_HIGH
- &gpio0 17 GPIO_ACTIVE_HIGH>;
- alarm-gpios = <&gpio1 3 GPIO_ACTIVE_HIGH
- &gpio1 12 GPIO_ACTIVE_HIGH
- &gpio1 13 GPIO_ACTIVE_HIGH>;
- gpio-fan,speed-map = < 0 0
- 2500 1
- 3100 2
- 3800 3
- 4600 4
- 4800 5
- 4900 6
- 5000 7 >;
- };
-
- gpio-leds-alarm-12 {
- status = "disabled";
- compatible = "gpio-leds";
- pinctrl-0 = <&pmx_alarmled_12>;
- pinctrl-names = "default";
-
- hdd1-green {
- label = "synology:alarm";
- gpios = <&gpio0 21 GPIO_ACTIVE_LOW>;
- };
- };
-
- gpio-leds-hdd-20 {
- status = "disabled";
- compatible = "gpio-leds";
- pinctrl-0 = <&pmx_hddled_20 &pmx_hddled_21 &pmx_hddled_22
- &pmx_hddled_23 &pmx_hddled_24 &pmx_hddled_25
- &pmx_hddled_26 &pmx_hddled_27>;
- pinctrl-names = "default";
-
- hdd1-green {
- label = "synology:green:hdd1";
- gpios = <&gpio0 20 GPIO_ACTIVE_LOW>;
- };
-
- hdd1-amber {
- label = "synology:amber:hdd1";
- gpios = <&gpio0 21 GPIO_ACTIVE_LOW>;
- };
-
- hdd2-green {
- label = "synology:green:hdd2";
- gpios = <&gpio0 22 GPIO_ACTIVE_LOW>;
- };
-
- hdd2-amber {
- label = "synology:amber:hdd2";
- gpios = <&gpio0 23 GPIO_ACTIVE_LOW>;
- };
-
- hdd3-green {
- label = "synology:green:hdd3";
- gpios = <&gpio0 24 GPIO_ACTIVE_LOW>;
- };
-
- hdd3-amber {
- label = "synology:amber:hdd3";
- gpios = <&gpio0 25 GPIO_ACTIVE_LOW>;
- };
-
- hdd4-green {
- label = "synology:green:hdd4";
- gpios = <&gpio0 26 GPIO_ACTIVE_LOW>;
- };
-
- hdd4-amber {
- label = "synology:amber:hdd4";
- gpios = <&gpio0 27 GPIO_ACTIVE_LOW>;
- };
- };
-
- gpio-leds-hdd-21-1 {
- status = "disabled";
- compatible = "gpio-leds";
- pinctrl-0 = <&pmx_hddled_21 &pmx_hddled_23>;
- pinctrl-names = "default";
-
- hdd1-green {
- label = "synology:green:hdd1";
- gpios = <&gpio0 21 GPIO_ACTIVE_LOW>;
- };
-
- hdd1-amber {
- label = "synology:amber:hdd1";
- gpios = <&gpio0 23 GPIO_ACTIVE_LOW>;
- };
- };
-
- gpio-leds-hdd-21-2 {
- status = "disabled";
- compatible = "gpio-leds";
- pinctrl-0 = <&pmx_hddled_21 &pmx_hddled_23 &pmx_hddled_20 &pmx_hddled_22>;
- pinctrl-names = "default";
-
- hdd1-green {
- label = "synology:green:hdd1";
- gpios = <&gpio0 21 GPIO_ACTIVE_LOW>;
- };
-
- hdd1-amber {
- label = "synology:amber:hdd1";
- gpios = <&gpio0 23 GPIO_ACTIVE_LOW>;
- };
-
- hdd2-green {
- label = "synology:green:hdd2";
- gpios = <&gpio0 20 GPIO_ACTIVE_LOW>;
- };
-
- hdd2-amber {
- label = "synology:amber:hdd2";
- gpios = <&gpio0 22 GPIO_ACTIVE_LOW>;
- };
- };
-
- gpio-leds-hdd-36 {
- status = "disabled";
- compatible = "gpio-leds";
- pinctrl-0 = <&pmx_hddled_36 &pmx_hddled_37 &pmx_hddled_38
- &pmx_hddled_39 &pmx_hddled_40 &pmx_hddled_41
- &pmx_hddled_42 &pmx_hddled_43 &pmx_hddled_44
- &pmx_hddled_45>;
- pinctrl-names = "default";
-
- hdd1-green {
- label = "synology:green:hdd1";
- gpios = <&gpio1 4 GPIO_ACTIVE_LOW>;
- };
-
- hdd1-amber {
- label = "synology:amber:hdd1";
- gpios = <&gpio1 5 GPIO_ACTIVE_LOW>;
- };
-
- hdd2-green {
- label = "synology:green:hdd2";
- gpios = <&gpio1 6 GPIO_ACTIVE_LOW>;
- };
-
- hdd2-amber {
- label = "synology:amber:hdd2";
- gpios = <&gpio1 7 GPIO_ACTIVE_LOW>;
- };
-
- hdd3-green {
- label = "synology:green:hdd3";
- gpios = <&gpio1 8 GPIO_ACTIVE_LOW>;
- };
-
- hdd3-amber {
- label = "synology:amber:hdd3";
- gpios = <&gpio1 9 GPIO_ACTIVE_LOW>;
- };
-
- hdd4-green {
- label = "synology:green:hdd4";
- gpios = <&gpio1 10 GPIO_ACTIVE_LOW>;
- };
-
- hdd4-amber {
- label = "synology:amber:hdd4";
- gpios = <&gpio1 11 GPIO_ACTIVE_LOW>;
- };
-
- hdd5-green {
- label = "synology:green:hdd5";
- gpios = <&gpio1 12 GPIO_ACTIVE_LOW>;
- };
-
- hdd5-amber {
- label = "synology:amber:hdd5";
- gpios = <&gpio1 13 GPIO_ACTIVE_LOW>;
- };
- };
-
- gpio-leds-hdd-38 {
- status = "disabled";
- compatible = "gpio-leds";
- pinctrl-0 = <&pmx_hddled_38 &pmx_hddled_39 &pmx_hddled_36 &pmx_hddled_37>;
- pinctrl-names = "default";
-
- hdd1-green {
- label = "synology:green:hdd1";
- gpios = <&gpio1 6 GPIO_ACTIVE_LOW>;
- };
-
- hdd1-amber {
- label = "synology:amber:hdd1";
- gpios = <&gpio1 7 GPIO_ACTIVE_LOW>;
- };
-
- hdd2-green {
- label = "synology:green:hdd2";
- gpios = <&gpio1 4 GPIO_ACTIVE_LOW>;
- };
-
- hdd2-amber {
- label = "synology:amber:hdd2";
- gpios = <&gpio1 5 GPIO_ACTIVE_LOW>;
- };
- };
-
- regulators-hdd-29 {
- status = "disabled";
- compatible = "simple-bus";
- #address-cells = <1>;
- #size-cells = <0>;
- pinctrl-0 = <&pmx_hdd1_pwr_29 &pmx_hdd2_pwr_31>;
- pinctrl-names = "default";
-
- regulator@1 {
- compatible = "regulator-fixed";
- reg = <1>;
- regulator-name = "hdd1power";
- regulator-min-microvolt = <5000000>;
- regulator-max-microvolt = <5000000>;
- enable-active-high;
- regulator-always-on;
- regulator-boot-on;
- startup-delay-us = <5000000>;
- gpio = <&gpio0 29 GPIO_ACTIVE_HIGH>;
- };
-
- regulator@2 {
- compatible = "regulator-fixed";
- reg = <2>;
- regulator-name = "hdd2power";
- regulator-min-microvolt = <5000000>;
- regulator-max-microvolt = <5000000>;
- enable-active-high;
- regulator-always-on;
- regulator-boot-on;
- startup-delay-us = <5000000>;
- gpio = <&gpio0 31 GPIO_ACTIVE_HIGH>;
- };
- };
-
- regulators-hdd-30-1 {
- status = "disabled";
- compatible = "simple-bus";
- #address-cells = <1>;
- #size-cells = <0>;
- pinctrl-0 = <&pmx_hdd1_pwr_30>;
- pinctrl-names = "default";
-
- regulator@1 {
- compatible = "regulator-fixed";
- reg = <1>;
- regulator-name = "hdd1power";
- regulator-min-microvolt = <5000000>;
- regulator-max-microvolt = <5000000>;
- enable-active-high;
- regulator-always-on;
- regulator-boot-on;
- startup-delay-us = <5000000>;
- gpio = <&gpio0 30 GPIO_ACTIVE_HIGH>;
- };
- };
-
- regulators-hdd-30-2 {
- status = "disabled";
- compatible = "simple-bus";
- #address-cells = <1>;
- #size-cells = <0>;
- pinctrl-0 = <&pmx_hdd1_pwr_30 &pmx_hdd2_pwr_34>;
- pinctrl-names = "default";
-
- regulator@1 {
- compatible = "regulator-fixed";
- reg = <1>;
- regulator-name = "hdd1power";
- regulator-min-microvolt = <5000000>;
- regulator-max-microvolt = <5000000>;
- enable-active-high;
- regulator-always-on;
- regulator-boot-on;
- startup-delay-us = <5000000>;
- gpio = <&gpio0 30 GPIO_ACTIVE_HIGH>;
- };
-
- regulator@2 {
- compatible = "regulator-fixed";
- reg = <2>;
- regulator-name = "hdd2power";
- regulator-min-microvolt = <5000000>;
- regulator-max-microvolt = <5000000>;
- enable-active-high;
- regulator-always-on;
- regulator-boot-on;
- startup-delay-us = <5000000>;
- gpio = <&gpio1 2 GPIO_ACTIVE_HIGH>;
- };
- };
-
- regulators-hdd-30-4 {
- status = "disabled";
- compatible = "simple-bus";
- #address-cells = <1>;
- #size-cells = <0>;
- pinctrl-0 = <&pmx_hdd1_pwr_30 &pmx_hdd2_pwr_34
- &pmx_hdd3_pwr_44 &pmx_hdd4_pwr_45>;
- pinctrl-names = "default";
-
- regulator@1 {
- compatible = "regulator-fixed";
- reg = <1>;
- regulator-name = "hdd1power";
- regulator-min-microvolt = <5000000>;
- regulator-max-microvolt = <5000000>;
- enable-active-high;
- regulator-always-on;
- regulator-boot-on;
- startup-delay-us = <5000000>;
- gpio = <&gpio0 30 GPIO_ACTIVE_HIGH>;
- };
-
- regulator@2 {
- compatible = "regulator-fixed";
- reg = <2>;
- regulator-name = "hdd2power";
- regulator-min-microvolt = <5000000>;
- regulator-max-microvolt = <5000000>;
- enable-active-high;
- regulator-always-on;
- regulator-boot-on;
- startup-delay-us = <5000000>;
- gpio = <&gpio1 2 GPIO_ACTIVE_HIGH>;
- };
-
- regulator@3 {
- compatible = "regulator-fixed";
- reg = <3>;
- regulator-name = "hdd3power";
- regulator-min-microvolt = <5000000>;
- regulator-max-microvolt = <5000000>;
- enable-active-high;
- regulator-always-on;
- regulator-boot-on;
- startup-delay-us = <5000000>;
- gpio = <&gpio1 12 GPIO_ACTIVE_HIGH>;
- };
-
- regulator@4 {
- compatible = "regulator-fixed";
- reg = <4>;
- regulator-name = "hdd4power";
- regulator-min-microvolt = <5000000>;
- regulator-max-microvolt = <5000000>;
- enable-active-high;
- regulator-always-on;
- regulator-boot-on;
- startup-delay-us = <5000000>;
- gpio = <&gpio1 13 GPIO_ACTIVE_HIGH>;
- };
- };
-
- regulators-hdd-31 {
- status = "disabled";
- compatible = "simple-bus";
- #address-cells = <1>;
- #size-cells = <0>;
- pinctrl-0 = <&pmx_hdd2_pwr_31>;
- pinctrl-names = "default";
-
- regulator@1 {
- compatible = "regulator-fixed";
- reg = <1>;
- regulator-name = "hdd2power";
- regulator-min-microvolt = <5000000>;
- regulator-max-microvolt = <5000000>;
- enable-active-high;
- regulator-always-on;
- regulator-boot-on;
- startup-delay-us = <5000000>;
- gpio = <&gpio0 31 GPIO_ACTIVE_HIGH>;
- };
- };
-
- regulators-hdd-34 {
- status = "disabled";
- compatible = "simple-bus";
- #address-cells = <1>;
- #size-cells = <0>;
- pinctrl-0 = <&pmx_hdd2_pwr_34 &pmx_hdd3_pwr_44
- &pmx_hdd4_pwr_45>;
- pinctrl-names = "default";
-
- regulator@2 {
- compatible = "regulator-fixed";
- reg = <2>;
- regulator-name = "hdd2power";
- regulator-min-microvolt = <5000000>;
- regulator-max-microvolt = <5000000>;
- enable-active-high;
- regulator-always-on;
- regulator-boot-on;
- startup-delay-us = <5000000>;
- gpio = <&gpio1 2 GPIO_ACTIVE_HIGH>;
- };
-
- regulator@3 {
- compatible = "regulator-fixed";
- reg = <3>;
- regulator-name = "hdd3power";
- regulator-min-microvolt = <5000000>;
- regulator-max-microvolt = <5000000>;
- enable-active-high;
- regulator-always-on;
- regulator-boot-on;
- startup-delay-us = <5000000>;
- gpio = <&gpio1 12 GPIO_ACTIVE_HIGH>;
- };
-
- regulator@4 {
- compatible = "regulator-fixed";
- reg = <4>;
- regulator-name = "hdd4power";
- regulator-min-microvolt = <5000000>;
- regulator-max-microvolt = <5000000>;
- enable-active-high;
- regulator-always-on;
- regulator-boot-on;
- startup-delay-us = <5000000>;
- gpio = <&gpio1 13 GPIO_ACTIVE_HIGH>;
- };
- };
-};
-
-&mdio {
- status = "okay";
-
- ethphy0: ethernet-phy@0 {
- device_type = "ethernet-phy";
- reg = <8>;
- };
-
- ethphy1: ethernet-phy@1 {
- device_type = "ethernet-phy";
- reg = <9>;
- };
-};
-
-ð0 {
- status = "okay";
-
- ethernet0-port@0 {
- phy-handle = <ðphy0>;
- };
-};
-
-ð1 {
- status = "disabled";
-
- ethernet1-port@0 {
- phy-handle = <ðphy1>;
- };
-};
-
-&pciec {
- status = "okay";
-};
-
-&pcie0 {
- status = "okay";
-};
diff --git a/arch/arm/dts/kirkwood.dtsi b/arch/arm/dts/kirkwood.dtsi
deleted file mode 100644
index 81c7eda..0000000
--- a/arch/arm/dts/kirkwood.dtsi
+++ /dev/null
@@ -1,393 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0
-/include/ "skeleton.dtsi"
-#include <dt-bindings/input/input.h>
-#include <dt-bindings/gpio/gpio.h>
-
-#define MBUS_ID(target,attributes) (((target) << 24) | ((attributes) << 16))
-
-/ {
- compatible = "marvell,kirkwood";
- interrupt-parent = <&intc>;
-
- cpus {
- #address-cells = <1>;
- #size-cells = <0>;
-
- cpu@0 {
- device_type = "cpu";
- compatible = "marvell,feroceon";
- reg = <0>;
- clocks = <&core_clk 1>, <&core_clk 3>, <&gate_clk 11>;
- clock-names = "cpu_clk", "ddrclk", "powersave";
- };
- };
-
- aliases {
- gpio0 = &gpio0;
- gpio1 = &gpio1;
- i2c0 = &i2c0;
- };
-
- mbus@f1000000 {
- compatible = "marvell,kirkwood-mbus", "simple-bus";
- #address-cells = <2>;
- #size-cells = <1>;
- /* If a board file needs to change this ranges it must replace it completely */
- ranges = <MBUS_ID(0xf0, 0x01) 0 0xf1000000 0x100000 /* internal-regs */
- MBUS_ID(0x01, 0x2f) 0 0xf4000000 0x10000 /* nand flash */
- MBUS_ID(0x03, 0x01) 0 0xf5000000 0x10000 /* crypto sram */
- >;
- controller = <&mbusc>;
- pcie-mem-aperture = <0xe0000000 0x10000000>; /* 256 MiB memory space */
- pcie-io-aperture = <0xf2000000 0x100000>; /* 1 MiB I/O space */
-
- nand: nand@12f {
- #address-cells = <1>;
- #size-cells = <1>;
- cle = <0>;
- ale = <1>;
- bank-width = <1>;
- compatible = "marvell,orion-nand";
- reg = <MBUS_ID(0x01, 0x2f) 0 0x400>;
- chip-delay = <25>;
- /* set partition map and/or chip-delay in board dts */
- clocks = <&gate_clk 7>;
- pinctrl-0 = <&pmx_nand>;
- pinctrl-names = "default";
- status = "disabled";
- };
-
- crypto_sram: sa-sram@301 {
- compatible = "mmio-sram";
- reg = <MBUS_ID(0x03, 0x01) 0x0 0x800>;
- clocks = <&gate_clk 17>;
- #address-cells = <1>;
- #size-cells = <1>;
- };
- };
-
- ocp@f1000000 {
- compatible = "simple-bus";
- ranges = <0x00000000 0xf1000000 0x0100000>;
- #address-cells = <1>;
- #size-cells = <1>;
-
- pinctrl: pin-controller@10000 {
- /* set compatible property in SoC file */
- reg = <0x10000 0x20>;
-
- pmx_ge1: pmx-ge1 {
- marvell,pins = "mpp20", "mpp21", "mpp22", "mpp23",
- "mpp24", "mpp25", "mpp26", "mpp27",
- "mpp30", "mpp31", "mpp32", "mpp33";
- marvell,function = "ge1";
- };
-
- pmx_nand: pmx-nand {
- marvell,pins = "mpp0", "mpp1", "mpp2", "mpp3",
- "mpp4", "mpp5", "mpp18", "mpp19";
- marvell,function = "nand";
- };
-
- /*
- * Default SPI0 pinctrl setting with CSn on mpp0,
- * overwrite marvell,pins on board level if required.
- */
- pmx_spi: pmx-spi {
- marvell,pins = "mpp0", "mpp1", "mpp2", "mpp3";
- marvell,function = "spi";
- };
-
- pmx_twsi0: pmx-twsi0 {
- marvell,pins = "mpp8", "mpp9";
- marvell,function = "twsi0";
- };
-
- /*
- * Default UART pinctrl setting without RTS/CTS,
- * overwrite marvell,pins on board level if required.
- */
- pmx_uart0: pmx-uart0 {
- marvell,pins = "mpp10", "mpp11";
- marvell,function = "uart0";
- };
-
- pmx_uart1: pmx-uart1 {
- marvell,pins = "mpp13", "mpp14";
- marvell,function = "uart1";
- };
- };
-
- core_clk: core-clocks@10030 {
- compatible = "marvell,kirkwood-core-clock";
- reg = <0x10030 0x4>;
- #clock-cells = <1>;
- };
-
- spi0: spi@10600 {
- compatible = "marvell,orion-spi";
- #address-cells = <1>;
- #size-cells = <0>;
- cell-index = <0>;
- interrupts = <23>;
- reg = <0x10600 0x28>;
- clocks = <&gate_clk 7>;
- pinctrl-0 = <&pmx_spi>;
- pinctrl-names = "default";
- status = "disabled";
- };
-
- gpio0: gpio@10100 {
- compatible = "marvell,orion-gpio";
- #gpio-cells = <2>;
- gpio-controller;
- reg = <0x10100 0x40>;
- ngpios = <32>;
- interrupt-controller;
- #interrupt-cells = <2>;
- interrupts = <35>, <36>, <37>, <38>;
- clocks = <&gate_clk 7>;
- };
-
- gpio1: gpio@10140 {
- compatible = "marvell,orion-gpio";
- #gpio-cells = <2>;
- gpio-controller;
- reg = <0x10140 0x40>;
- ngpios = <18>;
- interrupt-controller;
- #interrupt-cells = <2>;
- interrupts = <39>, <40>, <41>;
- clocks = <&gate_clk 7>;
- };
-
- i2c0: i2c@11000 {
- compatible = "marvell,mv64xxx-i2c";
- reg = <0x11000 0x20>;
- #address-cells = <1>;
- #size-cells = <0>;
- interrupts = <29>;
- clock-frequency = <100000>;
- clocks = <&gate_clk 7>;
- pinctrl-0 = <&pmx_twsi0>;
- pinctrl-names = "default";
- status = "disabled";
- };
-
- uart0: serial@12000 {
- compatible = "ns16550a";
- reg = <0x12000 0x100>;
- reg-shift = <2>;
- interrupts = <33>;
- clocks = <&gate_clk 7>;
- pinctrl-0 = <&pmx_uart0>;
- pinctrl-names = "default";
- status = "disabled";
- };
-
- uart1: serial@12100 {
- compatible = "ns16550a";
- reg = <0x12100 0x100>;
- reg-shift = <2>;
- interrupts = <34>;
- clocks = <&gate_clk 7>;
- pinctrl-0 = <&pmx_uart1>;
- pinctrl-names = "default";
- status = "disabled";
- };
-
- mbusc: mbus-controller@20000 {
- compatible = "marvell,mbus-controller";
- reg = <0x20000 0x80>, <0x1500 0x20>;
- };
-
- sysc: system-controller@20000 {
- compatible = "marvell,orion-system-controller";
- reg = <0x20000 0x120>;
- };
-
- bridge_intc: bridge-interrupt-ctrl@20110 {
- compatible = "marvell,orion-bridge-intc";
- interrupt-controller;
- #interrupt-cells = <1>;
- reg = <0x20110 0x8>;
- interrupts = <1>;
- marvell,#interrupts = <6>;
- };
-
- gate_clk: clock-gating-control@2011c {
- compatible = "marvell,kirkwood-gating-clock";
- reg = <0x2011c 0x4>;
- clocks = <&core_clk 0>;
- #clock-cells = <1>;
- };
-
- l2: l2-cache@20128 {
- compatible = "marvell,kirkwood-cache";
- reg = <0x20128 0x4>;
- };
-
- intc: main-interrupt-ctrl@20200 {
- compatible = "marvell,orion-intc";
- interrupt-controller;
- #interrupt-cells = <1>;
- reg = <0x20200 0x10>, <0x20210 0x10>;
- };
-
- timer: timer@20300 {
- compatible = "marvell,orion-timer";
- reg = <0x20300 0x20>;
- interrupt-parent = <&bridge_intc>;
- interrupts = <1>, <2>;
- clocks = <&core_clk 0>;
- };
-
- wdt: watchdog-timer@20300 {
- compatible = "marvell,orion-wdt";
- reg = <0x20300 0x28>, <0x20108 0x4>;
- interrupt-parent = <&bridge_intc>;
- interrupts = <3>;
- clocks = <&gate_clk 7>;
- status = "okay";
- };
-
- cesa: crypto@30000 {
- compatible = "marvell,kirkwood-crypto";
- reg = <0x30000 0x10000>;
- reg-names = "regs";
- interrupts = <22>;
- clocks = <&gate_clk 17>;
- marvell,crypto-srams = <&crypto_sram>;
- marvell,crypto-sram-size = <0x800>;
- status = "okay";
- };
-
- usb0: ehci@50000 {
- compatible = "marvell,orion-ehci";
- reg = <0x50000 0x1000>;
- interrupts = <19>;
- clocks = <&gate_clk 3>;
- status = "okay";
- };
-
- dma0: xor@60800 {
- compatible = "marvell,orion-xor";
- reg = <0x60800 0x100
- 0x60A00 0x100>;
- status = "okay";
- clocks = <&gate_clk 8>;
-
- xor00 {
- interrupts = <5>;
- dmacap,memcpy;
- dmacap,xor;
- };
- xor01 {
- interrupts = <6>;
- dmacap,memcpy;
- dmacap,xor;
- dmacap,memset;
- };
- };
-
- dma1: xor@60900 {
- compatible = "marvell,orion-xor";
- reg = <0x60900 0x100
- 0x60B00 0x100>;
- status = "okay";
- clocks = <&gate_clk 16>;
-
- xor00 {
- interrupts = <7>;
- dmacap,memcpy;
- dmacap,xor;
- };
- xor01 {
- interrupts = <8>;
- dmacap,memcpy;
- dmacap,xor;
- dmacap,memset;
- };
- };
-
- eth0: ethernet-controller@72000 {
- compatible = "marvell,kirkwood-eth";
- #address-cells = <1>;
- #size-cells = <0>;
- reg = <0x72000 0x4000>;
- clocks = <&gate_clk 0>;
- marvell,tx-checksum-limit = <1600>;
- status = "disabled";
-
- eth0port: ethernet0-port@0 {
- compatible = "marvell,kirkwood-eth-port";
- reg = <0>;
- interrupts = <11>;
- /* overwrite MAC address in bootloader */
- local-mac-address = [00 00 00 00 00 00];
- /* set phy-handle property in board file */
- };
- };
-
- mdio: mdio-bus@72004 {
- compatible = "marvell,orion-mdio";
- #address-cells = <1>;
- #size-cells = <0>;
- reg = <0x72004 0x84>;
- interrupts = <46>;
- clocks = <&gate_clk 0>;
- status = "disabled";
-
- /* add phy nodes in board file */
- };
-
- eth1: ethernet-controller@76000 {
- compatible = "marvell,kirkwood-eth";
- #address-cells = <1>;
- #size-cells = <0>;
- reg = <0x76000 0x4000>;
- clocks = <&gate_clk 19>;
- marvell,tx-checksum-limit = <1600>;
- pinctrl-0 = <&pmx_ge1>;
- pinctrl-names = "default";
- status = "disabled";
-
- eth1port: ethernet1-port@0 {
- compatible = "marvell,kirkwood-eth-port";
- reg = <0>;
- interrupts = <15>;
- /* overwrite MAC address in bootloader */
- local-mac-address = [00 00 00 00 00 00];
- /* set phy-handle property in board file */
- };
- };
-
- sata_phy0: sata-phy@82000 {
- compatible = "marvell,mvebu-sata-phy";
- reg = <0x82000 0x0334>;
- clocks = <&gate_clk 14>;
- clock-names = "sata";
- #phy-cells = <0>;
- status = "ok";
- };
-
- sata_phy1: sata-phy@84000 {
- compatible = "marvell,mvebu-sata-phy";
- reg = <0x84000 0x0334>;
- clocks = <&gate_clk 15>;
- clock-names = "sata";
- #phy-cells = <0>;
- status = "ok";
- };
-
- audio0: audio-controller@a0000 {
- compatible = "marvell,kirkwood-audio";
- #sound-dai-cells = <0>;
- reg = <0xa0000 0x2210>;
- interrupts = <24>;
- clocks = <&gate_clk 9>;
- clock-names = "internal";
- status = "disabled";
- };
- };
-};
diff --git a/arch/arm/dts/meson-axg-jethome-jethub-j100.dts b/arch/arm/dts/meson-axg-jethome-jethub-j100.dts
deleted file mode 100644
index 5783732..0000000
--- a/arch/arm/dts/meson-axg-jethome-jethub-j100.dts
+++ /dev/null
@@ -1,361 +0,0 @@
-// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
-/*
- * Copyright (c) 2021 Vyacheslav Bocharov <adeep@lexina.in>
- * Copyright (c) 2020 JetHome
- * Author: Aleksandr Kazantsev <ak@tvip.ru>
- * Author: Alexey Shevelkin <ash@tvip.ru>
- * Author: Vyacheslav Bocharov <adeep@lexina.in>
- */
-
-/dts-v1/;
-
-#include "meson-axg.dtsi"
-#include <dt-bindings/input/input.h>
-#include <dt-bindings/thermal/thermal.h>
-
-/ {
- compatible = "jethome,jethub-j100", "amlogic,a113d", "amlogic,meson-axg";
- model = "JetHome JetHub J100";
- aliases {
- serial0 = &uart_AO; /* Console */
- serial1 = &uart_AO_B; /* External UART (Wireless Module) */
- ethernet0 = ðmac;
- };
-
- chosen {
- stdout-path = "serial0:115200n8";
- };
-
- /* 1024MB RAM */
- memory@0 {
- device_type = "memory";
- reg = <0x0 0x0 0x0 0x40000000>;
- };
-
- reserved-memory {
- linux,cma {
- size = <0x0 0x400000>;
- };
- };
-
- emmc_pwrseq: emmc-pwrseq {
- compatible = "mmc-pwrseq-emmc";
- reset-gpios = <&gpio BOOT_9 GPIO_ACTIVE_LOW>;
- };
-
- vcc_3v3: regulator-vcc_3v3 {
- compatible = "regulator-fixed";
- regulator-name = "VCC_3V3";
- regulator-min-microvolt = <3300000>;
- regulator-max-microvolt = <3300000>;
- vin-supply = <&vddao_3v3>;
- regulator-always-on;
- };
-
- vcc_5v: regulator-vcc_5v {
- compatible = "regulator-fixed";
- regulator-name = "VCC5V";
- regulator-min-microvolt = <5000000>;
- regulator-max-microvolt = <5000000>;
- regulator-always-on;
- };
-
- vddao_3v3: regulator-vddao_3v3 {
- compatible = "regulator-fixed";
- regulator-name = "VDDAO_3V3";
- regulator-min-microvolt = <3300000>;
- regulator-max-microvolt = <3300000>;
- vin-supply = <&vcc_5v>;
- regulator-always-on;
- };
-
- vddio_ao18: regulator-vddio_ao18 {
- compatible = "regulator-fixed";
- regulator-name = "VDDIO_AO18";
- regulator-min-microvolt = <1800000>;
- regulator-max-microvolt = <1800000>;
- vin-supply = <&vddao_3v3>;
- regulator-always-on;
- };
-
- vddio_boot: regulator-vddio_boot {
- compatible = "regulator-fixed";
- regulator-name = "VDDIO_BOOT";
- regulator-min-microvolt = <1800000>;
- regulator-max-microvolt = <1800000>;
- vin-supply = <&vddao_3v3>;
- regulator-always-on;
- };
-
- usb_pwr: regulator-usb_pwr {
- compatible = "regulator-fixed";
- regulator-name = "USB_PWR";
- regulator-min-microvolt = <5000000>;
- regulator-max-microvolt = <5000000>;
- vin-supply = <&vcc_5v>;
- regulator-always-on;
- };
-
- sdio_pwrseq: sdio-pwrseq {
- compatible = "mmc-pwrseq-simple";
- reset-gpios = <&gpio GPIOX_7 GPIO_ACTIVE_LOW>;
- clocks = <&wifi32k>;
- clock-names = "ext_clock";
- };
-
- wifi32k: wifi32k {
- compatible = "pwm-clock";
- #clock-cells = <0>;
- clock-frequency = <32768>;
- pwms = <&pwm_ab 0 30518 0>; /* PWM_A at 32.768KHz */
- };
-
- thermal-zones {
- cpu_thermal: cpu-thermal {
- polling-delay-passive = <250>;
- polling-delay = <1000>;
- thermal-sensors = <&scpi_sensors 0>;
- trips {
- cpu_passive: cpu-passive {
- temperature = <70000>; /* millicelsius */
- hysteresis = <2000>; /* millicelsius */
- type = "passive";
- };
-
- cpu_hot: cpu-hot {
- temperature = <80000>; /* millicelsius */
- hysteresis = <2000>; /* millicelsius */
- type = "hot";
- };
-
- cpu_critical: cpu-critical {
- temperature = <100000>; /* millicelsius */
- hysteresis = <2000>; /* millicelsius */
- type = "critical";
- };
- };
- };
-
- cpu_cooling_maps: cooling-maps {
- map0 {
- trip = <&cpu_passive>;
- cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
- <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
- <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
- <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
- };
-
- map1 {
- trip = <&cpu_hot>;
- cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
- <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
- <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
- <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
- };
- };
- };
- onewire {
- compatible = "w1-gpio";
- gpios = <&gpio GPIOA_14 GPIO_ACTIVE_HIGH>;
- #gpio-cells = <1>;
- };
-};
-
-&efuse {
- sn: sn@32 {
- reg = <0x32 0x20>;
- };
-
- eth_mac: eth_mac@0 {
- reg = <0x0 0x6>;
- };
-
- bt_mac: bt_mac@6 {
- reg = <0x6 0x6>;
- };
-
- wifi_mac: wifi_mac@c {
- reg = <0xc 0x6>;
- };
-
- bid: bid@12 {
- reg = <0x12 0x20>;
- };
-};
-
-ðmac {
- status = "okay";
- pinctrl-0 = <ð_rmii_x_pins>;
- pinctrl-names = "default";
- phy-handle = <ð_phy0>;
- phy-mode = "rmii";
-
- mdio {
- compatible = "snps,dwmac-mdio";
- #address-cells = <1>;
- #size-cells = <0>;
-
- /* ICPlus IP101A/G Ethernet PHY (vendor_id=0x0243, model_id=0x0c54) */
- eth_phy0: ethernet-phy@0 {
- /* compatible = "ethernet-phy-id0243.0c54";*/
- max-speed = <100>;
- reg = <0>;
-
- reset-assert-us = <10000>;
- reset-deassert-us = <10000>;
- reset-gpios = <&gpio GPIOZ_5 GPIO_ACTIVE_LOW>;
- };
- };
-};
-
-/* Internal I2C bus (on CPU module) */
-&i2c1 {
- status = "okay";
- pinctrl-0 = <&i2c1_z_pins>;
- pinctrl-names = "default";
-
- /* RTC */
- pcf8563: pcf8563@51 {
- compatible = "nxp,pcf8563";
- reg = <0x51>;
- status = "okay";
- };
-};
-
-/* Peripheral I2C bus (on motherboard) */
-&i2c_AO {
- status = "okay";
- pinctrl-0 = <&i2c_ao_sck_10_pins>, <&i2c_ao_sda_11_pins>;
- pinctrl-names = "default";
-};
-
-&pwm_ab {
- status = "okay";
- pinctrl-0 = <&pwm_a_x20_pins>;
- pinctrl-names = "default";
-};
-
-/* wifi module */
-&sd_emmc_b {
- status = "okay";
- #address-cells = <1>;
- #size-cells = <0>;
-
- pinctrl-0 = <&sdio_pins>;
- pinctrl-1 = <&sdio_clk_gate_pins>;
- pinctrl-names = "default", "clk-gate";
-
- bus-width = <4>;
- cap-sd-highspeed;
- sd-uhs-sdr104;
- max-frequency = <200000000>;
- non-removable;
- disable-wp;
-
- mmc-pwrseq = <&sdio_pwrseq>;
-
- vmmc-supply = <&vddao_3v3>;
- vqmmc-supply = <&vddio_boot>;
-
- brcmf: wifi@1 {
- reg = <1>;
- compatible = "brcm,bcm4329-fmac";
- };
-};
-
-/* emmc storage */
-&sd_emmc_c {
- status = "okay";
- pinctrl-0 = <&emmc_pins>, <&emmc_ds_pins>;
- pinctrl-1 = <&emmc_clk_gate_pins>;
- pinctrl-names = "default", "clk-gate";
-
- bus-width = <8>;
- cap-mmc-highspeed;
- max-frequency = <200000000>;
- non-removable;
- disable-wp;
- mmc-ddr-1_8v;
- mmc-hs200-1_8v;
-
- mmc-pwrseq = <&emmc_pwrseq>;
-
- vmmc-supply = <&vcc_3v3>;
- vqmmc-supply = <&vddio_boot>;
-};
-
-/* UART Bluetooth */
-&uart_B {
- status = "okay";
- pinctrl-0 = <&uart_b_z_pins>, <&uart_b_z_cts_rts_pins>;
- pinctrl-names = "default";
- uart-has-rtscts;
-
- bluetooth {
- compatible = "brcm,bcm43438-bt";
- shutdown-gpios = <&gpio GPIOZ_7 GPIO_ACTIVE_HIGH>;
- };
-};
-
-/* UART Console */
-&uart_AO {
- status = "okay";
- pinctrl-0 = <&uart_ao_a_pins>;
- pinctrl-names = "default";
-};
-
-/* UART Wireless module */
-&uart_AO_B {
- status = "okay";
- pinctrl-0 = <&uart_ao_b_pins>;
- pinctrl-names = "default";
-};
-
-&usb {
- status = "okay";
- phy-supply = <&usb_pwr>;
-};
-
-&spicc1 {
- status = "okay";
- pinctrl-0 = <&spi1_x_pins>, <&spi1_ss0_x_pins>;
- pinctrl-names = "default";
-};
-
-&gpio {
- gpio-line-names =
- "", "", "", "", "", // 0 - 4
- "", "", "", "", "", // 5 - 9
- "UserButton", "", "", "", "", // 10 - 14
- "", "", "", "", "", // 15 - 19
- "", "", "", "", "", // 20 - 24
- "", "LedRed", "LedGreen", "Output3", "Output2", // 25 - 29
- "Output1", "", "", "", "", // 30 - 34
- "", "ZigBeeBOOT", "", "", "", // 35 - 39
- "", "ZigBeeRESET", "", "Input4", "Input3", // 40 - 44
- "Input2", "Input1", "", "", "", // 45 - 49
- "", "", "", "", "", // 50 - 54
- "", "", "", "", "", // 55 - 59
- "", "", "", "", "", // 60 - 64
- "", "", "", "", "", // 65 - 69
- "", "", "", "", "", // 70 - 74
- "", "", "", "", "", // 75 - 79
- "", "", "", "", "", // 80 - 84
- "", ""; // 85-86
-};
-
-&cpu0 {
- #cooling-cells = <2>;
-};
-
-&cpu1 {
- #cooling-cells = <2>;
-};
-
-&cpu2 {
- #cooling-cells = <2>;
-};
-
-&cpu3 {
- #cooling-cells = <2>;
-};
diff --git a/arch/arm/dts/meson-axg-s400.dts b/arch/arm/dts/meson-axg-s400.dts
deleted file mode 100644
index 359589d..0000000
--- a/arch/arm/dts/meson-axg-s400.dts
+++ /dev/null
@@ -1,602 +0,0 @@
-// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
-/*
- * Copyright (c) 2017 Amlogic, Inc. All rights reserved.
- */
-
-/dts-v1/;
-
-#include "meson-axg.dtsi"
-#include <dt-bindings/input/input.h>
-
-/ {
- compatible = "amlogic,s400", "amlogic,a113d", "amlogic,meson-axg";
- model = "Amlogic Meson AXG S400 Development Board";
-
- adc_keys {
- compatible = "adc-keys";
- io-channels = <&saradc 0>;
- io-channel-names = "buttons";
- keyup-threshold-microvolt = <1800000>;
-
- button-next {
- label = "Next";
- linux,code = <KEY_NEXT>;
- press-threshold-microvolt = <1116000>; /* 62% */
- };
-
- button-prev {
- label = "Previous";
- linux,code = <KEY_PREVIOUS>;
- press-threshold-microvolt = <900000>; /* 50% */
- };
-
- button-wifi {
- label = "Wifi";
- linux,code = <KEY_WLAN>;
- press-threshold-microvolt = <684000>; /* 38% */
- };
-
- button-up {
- label = "Volume Up";
- linux,code = <KEY_VOLUMEUP>;
- press-threshold-microvolt = <468000>; /* 26% */
- };
-
- button-down {
- label = "Volume Down";
- linux,code = <KEY_VOLUMEDOWN>;
- press-threshold-microvolt = <252000>; /* 14% */
- };
-
- button-voice {
- label = "Voice";
- linux,code = <KEY_VOICECOMMAND>;
- press-threshold-microvolt = <0>; /* 0% */
- };
- };
-
- aliases {
- serial0 = &uart_AO;
- serial1 = &uart_A;
- };
-
- linein: audio-codec-0 {
- #sound-dai-cells = <0>;
- compatible = "everest,es7241";
- VDDA-supply = <&vcc_3v3>;
- VDDP-supply = <&vcc_3v3>;
- VDDD-supply = <&vcc_3v3>;
- status = "okay";
- sound-name-prefix = "Linein";
- };
-
- lineout: audio-codec-1 {
- #sound-dai-cells = <0>;
- compatible = "everest,es7154";
- VDD-supply = <&vcc_3v3>;
- PVDD-supply = <&vcc_5v>;
- status = "okay";
- sound-name-prefix = "Lineout";
- };
-
- spdif_dit: audio-codec-2 {
- #sound-dai-cells = <0>;
- compatible = "linux,spdif-dit";
- status = "okay";
- sound-name-prefix = "DIT";
- };
-
- dmics: audio-codec-3 {
- #sound-dai-cells = <0>;
- compatible = "dmic-codec";
- num-channels = <7>;
- wakeup-delay-ms = <50>;
- status = "okay";
- sound-name-prefix = "MIC";
- };
-
- spdif_dir: audio-codec-4 {
- #sound-dai-cells = <0>;
- compatible = "linux,spdif-dir";
- status = "okay";
- sound-name-prefix = "DIR";
- };
-
- emmc_pwrseq: emmc-pwrseq {
- compatible = "mmc-pwrseq-emmc";
- reset-gpios = <&gpio BOOT_9 GPIO_ACTIVE_LOW>;
- };
-
- chosen {
- stdout-path = "serial0:115200n8";
- };
-
- memory@0 {
- device_type = "memory";
- reg = <0x0 0x0 0x0 0x40000000>;
- };
-
- main_12v: regulator-main_12v {
- compatible = "regulator-fixed";
- regulator-name = "12V";
- regulator-min-microvolt = <12000000>;
- regulator-max-microvolt = <12000000>;
- regulator-always-on;
- };
-
- vcc_3v3: regulator-vcc_3v3 {
- compatible = "regulator-fixed";
- regulator-name = "VCC_3V3";
- regulator-min-microvolt = <3300000>;
- regulator-max-microvolt = <3300000>;
- vin-supply = <&vddao_3v3>;
- regulator-always-on;
- };
-
- vcc_5v: regulator-vcc_5v {
- compatible = "regulator-fixed";
- regulator-name = "VCC5V";
- regulator-min-microvolt = <5000000>;
- regulator-max-microvolt = <5000000>;
- vin-supply = <&main_12v>;
-
- gpio = <&gpio_ao GPIOAO_13 GPIO_ACTIVE_HIGH>;
- enable-active-high;
- };
-
- vddao_3v3: regulator-vddao_3v3 {
- compatible = "regulator-fixed";
- regulator-name = "VDDAO_3V3";
- regulator-min-microvolt = <3300000>;
- regulator-max-microvolt = <3300000>;
- vin-supply = <&main_12v>;
- regulator-always-on;
- };
-
- vddio_ao18: regulator-vddio_ao18 {
- compatible = "regulator-fixed";
- regulator-name = "VDDIO_AO18";
- regulator-min-microvolt = <1800000>;
- regulator-max-microvolt = <1800000>;
- vin-supply = <&vddao_3v3>;
- regulator-always-on;
- };
-
- vddio_boot: regulator-vddio_boot {
- compatible = "regulator-fixed";
- regulator-name = "VDDIO_BOOT";
- regulator-min-microvolt = <1800000>;
- regulator-max-microvolt = <1800000>;
- vin-supply = <&vddao_3v3>;
- regulator-always-on;
- };
-
- usb_pwr: regulator-usb_pwr {
- compatible = "regulator-fixed";
- regulator-name = "USB_PWR";
- regulator-min-microvolt = <5000000>;
- regulator-max-microvolt = <5000000>;
- vin-supply = <&vcc_5v>;
-
- gpio = <&gpio_ao GPIOAO_5 GPIO_ACTIVE_HIGH>;
- enable-active-high;
- };
-
- sdio_pwrseq: sdio-pwrseq {
- compatible = "mmc-pwrseq-simple";
- reset-gpios = <&gpio GPIOX_7 GPIO_ACTIVE_LOW>;
- clocks = <&wifi32k>;
- clock-names = "ext_clock";
- };
-
- speaker-leds {
- compatible = "gpio-leds";
-
- aled1 {
- label = "speaker:aled1";
- gpios = <&gpio_speaker 7 0>;
- };
-
- aled2 {
- label = "speaker:aled2";
- gpios = <&gpio_speaker 6 0>;
- };
-
- aled3 {
- label = "speaker:aled3";
- gpios = <&gpio_speaker 5 0>;
- };
-
- aled4 {
- label = "speaker:aled4";
- gpios = <&gpio_speaker 4 0>;
- };
-
- aled5 {
- label = "speaker:aled5";
- gpios = <&gpio_speaker 3 0>;
- };
-
- aled6 {
- label = "speaker:aled6";
- gpios = <&gpio_speaker 2 0>;
- };
- };
-
- sound {
- compatible = "amlogic,axg-sound-card";
- model = "AXG-S400";
- audio-aux-devs = <&tdmin_a>, <&tdmin_b>, <&tdmin_c>,
- <&tdmin_lb>, <&tdmout_c>;
- audio-widgets = "Line", "Lineout",
- "Line", "Linein",
- "Speaker", "Speaker1 Left",
- "Speaker", "Speaker1 Right";
- audio-routing = "TDMOUT_C IN 0", "FRDDR_A OUT 2",
- "SPDIFOUT IN 0", "FRDDR_A OUT 3",
- "TDMOUT_C IN 1", "FRDDR_B OUT 2",
- "SPDIFOUT IN 1", "FRDDR_B OUT 3",
- "TDMOUT_C IN 2", "FRDDR_C OUT 2",
- "SPDIFOUT IN 2", "FRDDR_C OUT 3",
- "TDM_C Playback", "TDMOUT_C OUT",
- "TDMIN_A IN 2", "TDM_C Capture",
- "TDMIN_A IN 5", "TDM_C Loopback",
- "TDMIN_B IN 2", "TDM_C Capture",
- "TDMIN_B IN 5", "TDM_C Loopback",
- "TDMIN_C IN 2", "TDM_C Capture",
- "TDMIN_C IN 5", "TDM_C Loopback",
- "TDMIN_LB IN 2", "TDM_C Loopback",
- "TDMIN_LB IN 5", "TDM_C Capture",
- "TODDR_A IN 0", "TDMIN_A OUT",
- "TODDR_B IN 0", "TDMIN_A OUT",
- "TODDR_C IN 0", "TDMIN_A OUT",
- "TODDR_A IN 1", "TDMIN_B OUT",
- "TODDR_B IN 1", "TDMIN_B OUT",
- "TODDR_C IN 1", "TDMIN_B OUT",
- "TODDR_A IN 2", "TDMIN_C OUT",
- "TODDR_B IN 2", "TDMIN_C OUT",
- "TODDR_C IN 2", "TDMIN_C OUT",
- "TODDR_A IN 3", "SPDIFIN Capture",
- "TODDR_B IN 3", "SPDIFIN Capture",
- "TODDR_C IN 3", "SPDIFIN Capture",
- "TODDR_A IN 4", "PDM Capture",
- "TODDR_B IN 4", "PDM Capture",
- "TODDR_C IN 4", "PDM Capture",
- "TODDR_A IN 6", "TDMIN_LB OUT",
- "TODDR_B IN 6", "TDMIN_LB OUT",
- "TODDR_C IN 6", "TDMIN_LB OUT",
- "Lineout", "Lineout AOUTL",
- "Lineout", "Lineout AOUTR",
- "Speaker1 Left", "SPK1 OUT_A",
- "Speaker1 Left", "SPK1 OUT_B",
- "Speaker1 Right", "SPK1 OUT_C",
- "Speaker1 Right", "SPK1 OUT_D",
- "Linein AINL", "Linein",
- "Linein AINR", "Linein";
- assigned-clocks = <&clkc CLKID_HIFI_PLL>,
- <&clkc CLKID_MPLL0>,
- <&clkc CLKID_MPLL1>;
- assigned-clock-parents = <0>, <0>, <0>;
- assigned-clock-rates = <589824000>,
- <270950400>,
- <393216000>;
- status = "okay";
-
- dai-link-0 {
- sound-dai = <&frddr_a>;
- };
-
- dai-link-1 {
- sound-dai = <&frddr_b>;
- };
-
- dai-link-2 {
- sound-dai = <&frddr_c>;
- };
-
- dai-link-3 {
- sound-dai = <&toddr_a>;
- };
-
- dai-link-4 {
- sound-dai = <&toddr_b>;
- };
-
- dai-link-5 {
- sound-dai = <&toddr_c>;
- };
-
- dai-link-6 {
- sound-dai = <&tdmif_c>;
- dai-format = "i2s";
- dai-tdm-slot-tx-mask-2 = <1 1>;
- dai-tdm-slot-rx-mask-1 = <1 1>;
- mclk-fs = <256>;
-
- codec-0 {
- sound-dai = <&lineout>;
- };
-
- codec-1 {
- sound-dai = <&speaker_amp1>;
- };
-
- codec-2 {
- sound-dai = <&linein>;
- };
-
- };
-
- dai-link-7 {
- sound-dai = <&spdifout>;
-
- codec {
- sound-dai = <&spdif_dit>;
- };
- };
-
- dai-link-8 {
- sound-dai = <&spdifin>;
-
- codec {
- sound-dai = <&spdif_dir>;
- };
- };
-
- dai-link-9 {
- sound-dai = <&pdm>;
-
- codec {
- sound-dai = <&dmics>;
- };
- };
- };
-
- wifi32k: wifi32k {
- compatible = "pwm-clock";
- #clock-cells = <0>;
- clock-frequency = <32768>;
- pwms = <&pwm_ab 0 30518 0>; /* PWM_A at 32.768KHz */
- };
-};
-
-ðmac {
- status = "okay";
- pinctrl-0 = <ð_rgmii_y_pins>;
- pinctrl-names = "default";
- phy-handle = <ð_phy0>;
- phy-mode = "rgmii";
-
- mdio {
- compatible = "snps,dwmac-mdio";
- #address-cells = <1>;
- #size-cells = <0>;
-
- eth_phy0: ethernet-phy@0 {
- /* Realtek RTL8211F (0x001cc916) */
- reg = <0>;
- interrupt-parent = <&gpio_intc>;
- interrupts = <98 IRQ_TYPE_LEVEL_LOW>;
- eee-broken-1000t;
- };
- };
-};
-
-&frddr_a {
- status = "okay";
-};
-
-&frddr_b {
- status = "okay";
-};
-
-&frddr_c {
- status = "okay";
-};
-
-&ir {
- status = "okay";
- pinctrl-0 = <&remote_input_ao_pins>;
- pinctrl-names = "default";
-};
-
-&i2c1 {
- status = "okay";
- pinctrl-0 = <&i2c1_z_pins>;
- pinctrl-names = "default";
-
- speaker_amp1: audio-codec@1b {
- compatible = "ti,tas5707";
- reg = <0x1b>;
- reset-gpios = <&gpio_ao GPIOAO_4 GPIO_ACTIVE_LOW>;
- #sound-dai-cells = <0>;
- AVDD-supply = <&vcc_3v3>;
- DVDD-supply = <&vcc_3v3>;
- PVDD_A-supply = <&main_12v>;
- PVDD_B-supply = <&main_12v>;
- PVDD_C-supply = <&main_12v>;
- PVDD_D-supply = <&main_12v>;
- sound-name-prefix = "SPK1";
- };
-};
-
-&i2c_AO {
- status = "okay";
- pinctrl-0 = <&i2c_ao_sck_10_pins>, <&i2c_ao_sda_11_pins>;
- pinctrl-names = "default";
-
- gpio_speaker: gpio-controller@1f {
- compatible = "nxp,pca9557";
- reg = <0x1f>;
- gpio-controller;
- #gpio-cells = <2>;
- vcc-supply = <&vddao_3v3>;
- };
-};
-
-&pdm {
- pinctrl-0 = <&pdm_dclk_a14_pins>, <&pdm_din0_pins>,
- <&pdm_din1_pins>, <&pdm_din2_pins>, <&pdm_din3_pins>;
- pinctrl-names = "default";
- status = "okay";
-};
-
-&pcieA {
- reset-gpios = <&gpio GPIOX_19 GPIO_ACTIVE_LOW>;
- status = "okay";
-};
-
-&pcieB {
- reset-gpios = <&gpio GPIOZ_10 (GPIO_ACTIVE_LOW | GPIO_OPEN_DRAIN)>;
- status = "okay";
-};
-
-&pwm_ab {
- status = "okay";
- pinctrl-0 = <&pwm_a_x20_pins>;
- pinctrl-names = "default";
-};
-
-&saradc {
- status = "okay";
- vref-supply = <&vddio_ao18>;
-};
-
-/* wifi module */
-&sd_emmc_b {
- status = "okay";
- #address-cells = <1>;
- #size-cells = <0>;
-
- pinctrl-0 = <&sdio_pins>;
- pinctrl-1 = <&sdio_clk_gate_pins>;
- pinctrl-names = "default", "clk-gate";
-
- bus-width = <4>;
- cap-sd-highspeed;
- sd-uhs-sdr104;
- max-frequency = <200000000>;
- non-removable;
- disable-wp;
-
- mmc-pwrseq = <&sdio_pwrseq>;
-
- vmmc-supply = <&vddao_3v3>;
- vqmmc-supply = <&vddio_boot>;
-
- brcmf: wifi@1 {
- reg = <1>;
- compatible = "brcm,bcm4329-fmac";
- };
-};
-
-/* emmc storage */
-&sd_emmc_c {
- status = "okay";
- pinctrl-0 = <&emmc_pins>, <&emmc_ds_pins>;
- pinctrl-1 = <&emmc_clk_gate_pins>;
- pinctrl-names = "default", "clk-gate";
-
- bus-width = <8>;
- cap-mmc-highspeed;
- max-frequency = <200000000>;
- non-removable;
- disable-wp;
- mmc-ddr-1_8v;
- mmc-hs200-1_8v;
-
- mmc-pwrseq = <&emmc_pwrseq>;
-
- vmmc-supply = <&vcc_3v3>;
- vqmmc-supply = <&vddio_boot>;
-};
-
-&spdifin {
- pinctrl-0 = <&spdif_in_a19_pins>;
- pinctrl-names = "default";
- status = "okay";
-};
-
-&spdifout {
- pinctrl-0 = <&spdif_out_a20_pins>;
- pinctrl-names = "default";
- status = "okay";
-};
-
-&tdmif_a {
- pinctrl-0 = <&tdma_sclk_pins>, <&tdma_fs_pins>,
- <&tdma_din0_pins>, <&tdma_dout0_x15_pins>;
- pinctrl-names = "default";
- status = "okay";
-};
-
-&tdmif_b {
- pinctrl-0 = <&tdmb_sclk_pins>, <&tdmb_fs_pins>,
- <&tdmb_din3_pins>, <&mclk_b_pins>;
- pinctrl-names = "default";
- status = "okay";
-};
-
-&tdmif_c {
- pinctrl-0 = <&tdmc_sclk_pins>, <&tdmc_fs_pins>,
- <&tdmc_din1_pins>, <&tdmc_dout2_pins>,
- <&mclk_c_pins>;
- pinctrl-names = "default";
- status = "okay";
-};
-
-&tdmin_a {
- status = "okay";
-};
-
-&tdmin_b {
- status = "okay";
-};
-
-&tdmin_c {
- status = "okay";
-};
-
-&tdmin_lb {
- status = "okay";
-};
-
-&tdmout_c {
- status = "okay";
-};
-
-&toddr_a {
- status = "okay";
-};
-
-&toddr_b {
- status = "okay";
-};
-
-&toddr_c {
- status = "okay";
-};
-
-&uart_A {
- status = "okay";
- pinctrl-0 = <&uart_a_pins>, <&uart_a_cts_rts_pins>;
- pinctrl-names = "default";
- uart-has-rtscts;
-
- bluetooth {
- compatible = "brcm,bcm43438-bt";
- shutdown-gpios = <&gpio GPIOX_21 GPIO_ACTIVE_HIGH>;
- };
-};
-
-&uart_AO {
- status = "okay";
- pinctrl-0 = <&uart_ao_a_pins>;
- pinctrl-names = "default";
-};
-
-&usb {
- status = "okay";
- dr_mode = "otg";
- vbus-supply = <&usb_pwr>;
-};
diff --git a/arch/arm/dts/meson-axg.dtsi b/arch/arm/dts/meson-axg.dtsi
deleted file mode 100644
index 3f5254e..0000000
--- a/arch/arm/dts/meson-axg.dtsi
+++ /dev/null
@@ -1,1957 +0,0 @@
-// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
-/*
- * Copyright (c) 2017 Amlogic, Inc. All rights reserved.
- */
-
-#include <dt-bindings/clock/axg-aoclkc.h>
-#include <dt-bindings/clock/axg-audio-clkc.h>
-#include <dt-bindings/clock/axg-clkc.h>
-#include <dt-bindings/gpio/gpio.h>
-#include <dt-bindings/gpio/meson-axg-gpio.h>
-#include <dt-bindings/interrupt-controller/irq.h>
-#include <dt-bindings/interrupt-controller/arm-gic.h>
-#include <dt-bindings/reset/amlogic,meson-axg-audio-arb.h>
-#include <dt-bindings/reset/amlogic,meson-axg-reset.h>
-#include <dt-bindings/power/meson-axg-power.h>
-
-/ {
- compatible = "amlogic,meson-axg";
-
- interrupt-parent = <&gic>;
- #address-cells = <2>;
- #size-cells = <2>;
-
- tdmif_a: audio-controller-0 {
- compatible = "amlogic,axg-tdm-iface";
- #sound-dai-cells = <0>;
- sound-name-prefix = "TDM_A";
- clocks = <&clkc_audio AUD_CLKID_MST_A_MCLK>,
- <&clkc_audio AUD_CLKID_MST_A_SCLK>,
- <&clkc_audio AUD_CLKID_MST_A_LRCLK>;
- clock-names = "mclk", "sclk", "lrclk";
- status = "disabled";
- };
-
- tdmif_b: audio-controller-1 {
- compatible = "amlogic,axg-tdm-iface";
- #sound-dai-cells = <0>;
- sound-name-prefix = "TDM_B";
- clocks = <&clkc_audio AUD_CLKID_MST_B_MCLK>,
- <&clkc_audio AUD_CLKID_MST_B_SCLK>,
- <&clkc_audio AUD_CLKID_MST_B_LRCLK>;
- clock-names = "mclk", "sclk", "lrclk";
- status = "disabled";
- };
-
- tdmif_c: audio-controller-2 {
- compatible = "amlogic,axg-tdm-iface";
- #sound-dai-cells = <0>;
- sound-name-prefix = "TDM_C";
- clocks = <&clkc_audio AUD_CLKID_MST_C_MCLK>,
- <&clkc_audio AUD_CLKID_MST_C_SCLK>,
- <&clkc_audio AUD_CLKID_MST_C_LRCLK>;
- clock-names = "mclk", "sclk", "lrclk";
- status = "disabled";
- };
-
- arm-pmu {
- compatible = "arm,cortex-a53-pmu";
- interrupts = <GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>;
- interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>;
- };
-
- cpus {
- #address-cells = <0x2>;
- #size-cells = <0x0>;
-
- cpu0: cpu@0 {
- device_type = "cpu";
- compatible = "arm,cortex-a53";
- reg = <0x0 0x0>;
- enable-method = "psci";
- next-level-cache = <&l2>;
- clocks = <&scpi_dvfs 0>;
- };
-
- cpu1: cpu@1 {
- device_type = "cpu";
- compatible = "arm,cortex-a53";
- reg = <0x0 0x1>;
- enable-method = "psci";
- next-level-cache = <&l2>;
- clocks = <&scpi_dvfs 0>;
- };
-
- cpu2: cpu@2 {
- device_type = "cpu";
- compatible = "arm,cortex-a53";
- reg = <0x0 0x2>;
- enable-method = "psci";
- next-level-cache = <&l2>;
- clocks = <&scpi_dvfs 0>;
- };
-
- cpu3: cpu@3 {
- device_type = "cpu";
- compatible = "arm,cortex-a53";
- reg = <0x0 0x3>;
- enable-method = "psci";
- next-level-cache = <&l2>;
- clocks = <&scpi_dvfs 0>;
- };
-
- l2: l2-cache0 {
- compatible = "cache";
- };
- };
-
- sm: secure-monitor {
- compatible = "amlogic,meson-gxbb-sm";
- };
-
- efuse: efuse {
- compatible = "amlogic,meson-gxbb-efuse";
- clocks = <&clkc CLKID_EFUSE>;
- #address-cells = <1>;
- #size-cells = <1>;
- read-only;
- secure-monitor = <&sm>;
- };
-
- psci {
- compatible = "arm,psci-1.0";
- method = "smc";
- };
-
- reserved-memory {
- #address-cells = <2>;
- #size-cells = <2>;
- ranges;
-
- /* 16 MiB reserved for Hardware ROM Firmware */
- hwrom_reserved: hwrom@0 {
- reg = <0x0 0x0 0x0 0x1000000>;
- no-map;
- };
-
- /* Alternate 3 MiB reserved for ARM Trusted Firmware (BL31) */
- secmon_reserved: secmon@5000000 {
- reg = <0x0 0x05000000 0x0 0x300000>;
- no-map;
- };
- };
-
- scpi {
- compatible = "arm,scpi-pre-1.0";
- mboxes = <&mailbox 1 &mailbox 2>;
- shmem = <&cpu_scp_lpri &cpu_scp_hpri>;
-
- scpi_clocks: clocks {
- compatible = "arm,scpi-clocks";
-
- scpi_dvfs: clock-controller {
- compatible = "arm,scpi-dvfs-clocks";
- #clock-cells = <1>;
- clock-indices = <0>;
- clock-output-names = "vcpu";
- };
- };
-
- scpi_sensors: sensors {
- compatible = "amlogic,meson-gxbb-scpi-sensors";
- #thermal-sensor-cells = <1>;
- };
- };
-
- soc {
- compatible = "simple-bus";
- #address-cells = <2>;
- #size-cells = <2>;
- ranges;
-
- pcieA: pcie@f9800000 {
- compatible = "amlogic,axg-pcie", "snps,dw-pcie";
- reg = <0x0 0xf9800000 0x0 0x400000>,
- <0x0 0xff646000 0x0 0x2000>,
- <0x0 0xf9f00000 0x0 0x100000>;
- reg-names = "elbi", "cfg", "config";
- interrupts = <GIC_SPI 177 IRQ_TYPE_EDGE_RISING>;
- #interrupt-cells = <1>;
- interrupt-map-mask = <0 0 0 0>;
- interrupt-map = <0 0 0 0 &gic GIC_SPI 179 IRQ_TYPE_EDGE_RISING>;
- bus-range = <0x0 0xff>;
- #address-cells = <3>;
- #size-cells = <2>;
- device_type = "pci";
- ranges = <0x82000000 0 0xf9c00000 0x0 0xf9c00000 0 0x00300000>;
-
- clocks = <&clkc CLKID_USB>, <&clkc CLKID_PCIE_A>, <&clkc CLKID_PCIE_CML_EN0>;
- clock-names = "general", "pclk", "port";
- resets = <&reset RESET_PCIE_A>, <&reset RESET_PCIE_APB>;
- reset-names = "port", "apb";
- num-lanes = <1>;
- phys = <&pcie_phy>;
- phy-names = "pcie";
- status = "disabled";
- };
-
- pcieB: pcie@fa000000 {
- compatible = "amlogic,axg-pcie", "snps,dw-pcie";
- reg = <0x0 0xfa000000 0x0 0x400000>,
- <0x0 0xff648000 0x0 0x2000>,
- <0x0 0xfa400000 0x0 0x100000>;
- reg-names = "elbi", "cfg", "config";
- interrupts = <GIC_SPI 167 IRQ_TYPE_EDGE_RISING>;
- #interrupt-cells = <1>;
- interrupt-map-mask = <0 0 0 0>;
- interrupt-map = <0 0 0 0 &gic GIC_SPI 169 IRQ_TYPE_EDGE_RISING>;
- bus-range = <0x0 0xff>;
- #address-cells = <3>;
- #size-cells = <2>;
- device_type = "pci";
- ranges = <0x82000000 0 0xfa500000 0x0 0xfa500000 0 0x00300000>;
-
- clocks = <&clkc CLKID_USB>, <&clkc CLKID_PCIE_B>, <&clkc CLKID_PCIE_CML_EN1>;
- clock-names = "general", "pclk", "port";
- resets = <&reset RESET_PCIE_B>, <&reset RESET_PCIE_APB>;
- reset-names = "port", "apb";
- num-lanes = <1>;
- phys = <&pcie_phy>;
- phy-names = "pcie";
- status = "disabled";
- };
-
- usb: usb@ffe09080 {
- compatible = "amlogic,meson-axg-usb-ctrl";
- reg = <0x0 0xffe09080 0x0 0x20>;
- interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
- #address-cells = <2>;
- #size-cells = <2>;
- ranges;
-
- clocks = <&clkc CLKID_USB>, <&clkc CLKID_USB1_DDR_BRIDGE>;
- clock-names = "usb_ctrl", "ddr";
- resets = <&reset RESET_USB_OTG>;
-
- dr_mode = "otg";
-
- phys = <&usb2_phy1>;
- phy-names = "usb2-phy1";
-
- dwc2: usb@ff400000 {
- compatible = "amlogic,meson-g12a-usb", "snps,dwc2";
- reg = <0x0 0xff400000 0x0 0x40000>;
- interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&clkc CLKID_USB1>;
- clock-names = "otg";
- phys = <&usb2_phy1>;
- dr_mode = "peripheral";
- g-rx-fifo-size = <192>;
- g-np-tx-fifo-size = <128>;
- g-tx-fifo-size = <128 128 16 16 16>;
- };
-
- dwc3: usb@ff500000 {
- compatible = "snps,dwc3";
- reg = <0x0 0xff500000 0x0 0x100000>;
- interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
- dr_mode = "host";
- maximum-speed = "high-speed";
- snps,dis_u2_susphy_quirk;
- };
- };
-
- ethmac: ethernet@ff3f0000 {
- compatible = "amlogic,meson-axg-dwmac",
- "snps,dwmac-3.70a",
- "snps,dwmac";
- reg = <0x0 0xff3f0000 0x0 0x10000>,
- <0x0 0xff634540 0x0 0x8>;
- interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
- interrupt-names = "macirq";
- clocks = <&clkc CLKID_ETH>,
- <&clkc CLKID_FCLK_DIV2>,
- <&clkc CLKID_MPLL2>,
- <&clkc CLKID_FCLK_DIV2>;
- clock-names = "stmmaceth", "clkin0", "clkin1",
- "timing-adjustment";
- rx-fifo-depth = <4096>;
- tx-fifo-depth = <2048>;
- power-domains = <&pwrc PWRC_AXG_ETHERNET_MEM_ID>;
- status = "disabled";
- };
-
- pcie_phy: phy@ff644000 {
- compatible = "amlogic,axg-pcie-phy";
- reg = <0x0 0xff644000 0x0 0x1c>;
- resets = <&reset RESET_PCIE_PHY>;
- phys = <&mipi_pcie_analog_dphy>;
- phy-names = "analog";
- #phy-cells = <0>;
- };
-
- pdm: audio-controller@ff632000 {
- compatible = "amlogic,axg-pdm";
- reg = <0x0 0xff632000 0x0 0x34>;
- #sound-dai-cells = <0>;
- sound-name-prefix = "PDM";
- clocks = <&clkc_audio AUD_CLKID_PDM>,
- <&clkc_audio AUD_CLKID_PDM_DCLK>,
- <&clkc_audio AUD_CLKID_PDM_SYSCLK>;
- clock-names = "pclk", "dclk", "sysclk";
- status = "disabled";
- };
-
- periphs: bus@ff634000 {
- compatible = "simple-bus";
- reg = <0x0 0xff634000 0x0 0x2000>;
- #address-cells = <2>;
- #size-cells = <2>;
- ranges = <0x0 0x0 0x0 0xff634000 0x0 0x2000>;
-
- hwrng: rng@18 {
- compatible = "amlogic,meson-rng";
- reg = <0x0 0x18 0x0 0x4>;
- clocks = <&clkc CLKID_RNG0>;
- clock-names = "core";
- };
-
- pinctrl_periphs: pinctrl@480 {
- compatible = "amlogic,meson-axg-periphs-pinctrl";
- #address-cells = <2>;
- #size-cells = <2>;
- ranges;
-
- gpio: bank@480 {
- reg = <0x0 0x00480 0x0 0x40>,
- <0x0 0x004e8 0x0 0x14>,
- <0x0 0x00520 0x0 0x14>,
- <0x0 0x00430 0x0 0x3c>;
- reg-names = "mux", "pull", "pull-enable", "gpio";
- gpio-controller;
- #gpio-cells = <2>;
- gpio-ranges = <&pinctrl_periphs 0 0 86>;
- };
-
- i2c0_pins: i2c0 {
- mux {
- groups = "i2c0_sck",
- "i2c0_sda";
- function = "i2c0";
- bias-disable;
- };
- };
-
- i2c1_x_pins: i2c1_x {
- mux {
- groups = "i2c1_sck_x",
- "i2c1_sda_x";
- function = "i2c1";
- bias-disable;
- };
- };
-
- i2c1_z_pins: i2c1_z {
- mux {
- groups = "i2c1_sck_z",
- "i2c1_sda_z";
- function = "i2c1";
- bias-disable;
- };
- };
-
- i2c2_a_pins: i2c2_a {
- mux {
- groups = "i2c2_sck_a",
- "i2c2_sda_a";
- function = "i2c2";
- bias-disable;
- };
- };
-
- i2c2_x_pins: i2c2_x {
- mux {
- groups = "i2c2_sck_x",
- "i2c2_sda_x";
- function = "i2c2";
- bias-disable;
- };
- };
-
- i2c3_a6_pins: i2c3_a6 {
- mux {
- groups = "i2c3_sda_a6",
- "i2c3_sck_a7";
- function = "i2c3";
- bias-disable;
- };
- };
-
- i2c3_a12_pins: i2c3_a12 {
- mux {
- groups = "i2c3_sda_a12",
- "i2c3_sck_a13";
- function = "i2c3";
- bias-disable;
- };
- };
-
- i2c3_a19_pins: i2c3_a19 {
- mux {
- groups = "i2c3_sda_a19",
- "i2c3_sck_a20";
- function = "i2c3";
- bias-disable;
- };
- };
-
- emmc_pins: emmc {
- mux-0 {
- groups = "emmc_nand_d0",
- "emmc_nand_d1",
- "emmc_nand_d2",
- "emmc_nand_d3",
- "emmc_nand_d4",
- "emmc_nand_d5",
- "emmc_nand_d6",
- "emmc_nand_d7",
- "emmc_cmd";
- function = "emmc";
- bias-pull-up;
- };
-
- mux-1 {
- groups = "emmc_clk";
- function = "emmc";
- bias-disable;
- };
- };
-
- emmc_ds_pins: emmc_ds {
- mux {
- groups = "emmc_ds";
- function = "emmc";
- bias-pull-down;
- };
- };
-
- emmc_clk_gate_pins: emmc_clk_gate {
- mux {
- groups = "BOOT_8";
- function = "gpio_periphs";
- bias-pull-down;
- };
- };
-
- eth_rgmii_x_pins: eth-x-rgmii {
- mux {
- groups = "eth_mdio_x",
- "eth_mdc_x",
- "eth_rgmii_rx_clk_x",
- "eth_rx_dv_x",
- "eth_rxd0_x",
- "eth_rxd1_x",
- "eth_rxd2_rgmii",
- "eth_rxd3_rgmii",
- "eth_rgmii_tx_clk",
- "eth_txen_x",
- "eth_txd0_x",
- "eth_txd1_x",
- "eth_txd2_rgmii",
- "eth_txd3_rgmii";
- function = "eth";
- bias-disable;
- };
- };
-
- eth_rgmii_y_pins: eth-y-rgmii {
- mux {
- groups = "eth_mdio_y",
- "eth_mdc_y",
- "eth_rgmii_rx_clk_y",
- "eth_rx_dv_y",
- "eth_rxd0_y",
- "eth_rxd1_y",
- "eth_rxd2_rgmii",
- "eth_rxd3_rgmii",
- "eth_rgmii_tx_clk",
- "eth_txen_y",
- "eth_txd0_y",
- "eth_txd1_y",
- "eth_txd2_rgmii",
- "eth_txd3_rgmii";
- function = "eth";
- bias-disable;
- };
- };
-
- eth_rmii_x_pins: eth-x-rmii {
- mux {
- groups = "eth_mdio_x",
- "eth_mdc_x",
- "eth_rgmii_rx_clk_x",
- "eth_rx_dv_x",
- "eth_rxd0_x",
- "eth_rxd1_x",
- "eth_txen_x",
- "eth_txd0_x",
- "eth_txd1_x";
- function = "eth";
- bias-disable;
- };
- };
-
- eth_rmii_y_pins: eth-y-rmii {
- mux {
- groups = "eth_mdio_y",
- "eth_mdc_y",
- "eth_rgmii_rx_clk_y",
- "eth_rx_dv_y",
- "eth_rxd0_y",
- "eth_rxd1_y",
- "eth_txen_y",
- "eth_txd0_y",
- "eth_txd1_y";
- function = "eth";
- bias-disable;
- };
- };
-
- mclk_b_pins: mclk_b {
- mux {
- groups = "mclk_b";
- function = "mclk_b";
- bias-disable;
- };
- };
-
- mclk_c_pins: mclk_c {
- mux {
- groups = "mclk_c";
- function = "mclk_c";
- bias-disable;
- };
- };
-
- pdm_dclk_a14_pins: pdm_dclk_a14 {
- mux {
- groups = "pdm_dclk_a14";
- function = "pdm";
- bias-disable;
- };
- };
-
- pdm_dclk_a19_pins: pdm_dclk_a19 {
- mux {
- groups = "pdm_dclk_a19";
- function = "pdm";
- bias-disable;
- };
- };
-
- pdm_din0_pins: pdm_din0 {
- mux {
- groups = "pdm_din0";
- function = "pdm";
- bias-disable;
- };
- };
-
- pdm_din1_pins: pdm_din1 {
- mux {
- groups = "pdm_din1";
- function = "pdm";
- bias-disable;
- };
- };
-
- pdm_din2_pins: pdm_din2 {
- mux {
- groups = "pdm_din2";
- function = "pdm";
- bias-disable;
- };
- };
-
- pdm_din3_pins: pdm_din3 {
- mux {
- groups = "pdm_din3";
- function = "pdm";
- bias-disable;
- };
- };
-
- pwm_a_a_pins: pwm_a_a {
- mux {
- groups = "pwm_a_a";
- function = "pwm_a";
- bias-disable;
- };
- };
-
- pwm_a_x18_pins: pwm_a_x18 {
- mux {
- groups = "pwm_a_x18";
- function = "pwm_a";
- bias-disable;
- };
- };
-
- pwm_a_x20_pins: pwm_a_x20 {
- mux {
- groups = "pwm_a_x20";
- function = "pwm_a";
- bias-disable;
- };
- };
-
- pwm_a_z_pins: pwm_a_z {
- mux {
- groups = "pwm_a_z";
- function = "pwm_a";
- bias-disable;
- };
- };
-
- pwm_b_a_pins: pwm_b_a {
- mux {
- groups = "pwm_b_a";
- function = "pwm_b";
- bias-disable;
- };
- };
-
- pwm_b_x_pins: pwm_b_x {
- mux {
- groups = "pwm_b_x";
- function = "pwm_b";
- bias-disable;
- };
- };
-
- pwm_b_z_pins: pwm_b_z {
- mux {
- groups = "pwm_b_z";
- function = "pwm_b";
- bias-disable;
- };
- };
-
- pwm_c_a_pins: pwm_c_a {
- mux {
- groups = "pwm_c_a";
- function = "pwm_c";
- bias-disable;
- };
- };
-
- pwm_c_x10_pins: pwm_c_x10 {
- mux {
- groups = "pwm_c_x10";
- function = "pwm_c";
- bias-disable;
- };
- };
-
- pwm_c_x17_pins: pwm_c_x17 {
- mux {
- groups = "pwm_c_x17";
- function = "pwm_c";
- bias-disable;
- };
- };
-
- pwm_d_x11_pins: pwm_d_x11 {
- mux {
- groups = "pwm_d_x11";
- function = "pwm_d";
- bias-disable;
- };
- };
-
- pwm_d_x16_pins: pwm_d_x16 {
- mux {
- groups = "pwm_d_x16";
- function = "pwm_d";
- bias-disable;
- };
- };
-
- sdio_pins: sdio {
- mux-0 {
- groups = "sdio_d0",
- "sdio_d1",
- "sdio_d2",
- "sdio_d3",
- "sdio_cmd";
- function = "sdio";
- bias-pull-up;
- };
-
- mux-1 {
- groups = "sdio_clk";
- function = "sdio";
- bias-disable;
- };
- };
-
- sdio_clk_gate_pins: sdio_clk_gate {
- mux {
- groups = "GPIOX_4";
- function = "gpio_periphs";
- bias-pull-down;
- };
- };
-
- spdif_in_z_pins: spdif_in_z {
- mux {
- groups = "spdif_in_z";
- function = "spdif_in";
- bias-disable;
- };
- };
-
- spdif_in_a1_pins: spdif_in_a1 {
- mux {
- groups = "spdif_in_a1";
- function = "spdif_in";
- bias-disable;
- };
- };
-
- spdif_in_a7_pins: spdif_in_a7 {
- mux {
- groups = "spdif_in_a7";
- function = "spdif_in";
- bias-disable;
- };
- };
-
- spdif_in_a19_pins: spdif_in_a19 {
- mux {
- groups = "spdif_in_a19";
- function = "spdif_in";
- bias-disable;
- };
- };
-
- spdif_in_a20_pins: spdif_in_a20 {
- mux {
- groups = "spdif_in_a20";
- function = "spdif_in";
- bias-disable;
- };
- };
-
- spdif_out_a1_pins: spdif_out_a1 {
- mux {
- groups = "spdif_out_a1";
- function = "spdif_out";
- bias-disable;
- };
- };
-
- spdif_out_a11_pins: spdif_out_a11 {
- mux {
- groups = "spdif_out_a11";
- function = "spdif_out";
- bias-disable;
- };
- };
-
- spdif_out_a19_pins: spdif_out_a19 {
- mux {
- groups = "spdif_out_a19";
- function = "spdif_out";
- bias-disable;
- };
- };
-
- spdif_out_a20_pins: spdif_out_a20 {
- mux {
- groups = "spdif_out_a20";
- function = "spdif_out";
- bias-disable;
- };
- };
-
- spdif_out_z_pins: spdif_out_z {
- mux {
- groups = "spdif_out_z";
- function = "spdif_out";
- bias-disable;
- };
- };
-
- spi0_pins: spi0 {
- mux {
- groups = "spi0_miso",
- "spi0_mosi",
- "spi0_clk";
- function = "spi0";
- bias-disable;
- };
- };
-
- spi0_ss0_pins: spi0_ss0 {
- mux {
- groups = "spi0_ss0";
- function = "spi0";
- bias-disable;
- };
- };
-
- spi0_ss1_pins: spi0_ss1 {
- mux {
- groups = "spi0_ss1";
- function = "spi0";
- bias-disable;
- };
- };
-
- spi0_ss2_pins: spi0_ss2 {
- mux {
- groups = "spi0_ss2";
- function = "spi0";
- bias-disable;
- };
- };
-
- spi1_a_pins: spi1_a {
- mux {
- groups = "spi1_miso_a",
- "spi1_mosi_a",
- "spi1_clk_a";
- function = "spi1";
- bias-disable;
- };
- };
-
- spi1_ss0_a_pins: spi1_ss0_a {
- mux {
- groups = "spi1_ss0_a";
- function = "spi1";
- bias-disable;
- };
- };
-
- spi1_ss1_pins: spi1_ss1 {
- mux {
- groups = "spi1_ss1";
- function = "spi1";
- bias-disable;
- };
- };
-
- spi1_x_pins: spi1_x {
- mux {
- groups = "spi1_miso_x",
- "spi1_mosi_x",
- "spi1_clk_x";
- function = "spi1";
- bias-disable;
- };
- };
-
- spi1_ss0_x_pins: spi1_ss0_x {
- mux {
- groups = "spi1_ss0_x";
- function = "spi1";
- bias-disable;
- };
- };
-
- tdma_din0_pins: tdma_din0 {
- mux {
- groups = "tdma_din0";
- function = "tdma";
- bias-disable;
- };
- };
-
- tdma_dout0_x14_pins: tdma_dout0_x14 {
- mux {
- groups = "tdma_dout0_x14";
- function = "tdma";
- bias-disable;
- };
- };
-
- tdma_dout0_x15_pins: tdma_dout0_x15 {
- mux {
- groups = "tdma_dout0_x15";
- function = "tdma";
- bias-disable;
- };
- };
-
- tdma_dout1_pins: tdma_dout1 {
- mux {
- groups = "tdma_dout1";
- function = "tdma";
- bias-disable;
- };
- };
-
- tdma_din1_pins: tdma_din1 {
- mux {
- groups = "tdma_din1";
- function = "tdma";
- bias-disable;
- };
- };
-
- tdma_fs_pins: tdma_fs {
- mux {
- groups = "tdma_fs";
- function = "tdma";
- bias-disable;
- };
- };
-
- tdma_fs_slv_pins: tdma_fs_slv {
- mux {
- groups = "tdma_fs_slv";
- function = "tdma";
- bias-disable;
- };
- };
-
- tdma_sclk_pins: tdma_sclk {
- mux {
- groups = "tdma_sclk";
- function = "tdma";
- bias-disable;
- };
- };
-
- tdma_sclk_slv_pins: tdma_sclk_slv {
- mux {
- groups = "tdma_sclk_slv";
- function = "tdma";
- bias-disable;
- };
- };
-
- tdmb_din0_pins: tdmb_din0 {
- mux {
- groups = "tdmb_din0";
- function = "tdmb";
- bias-disable;
- };
- };
-
- tdmb_din1_pins: tdmb_din1 {
- mux {
- groups = "tdmb_din1";
- function = "tdmb";
- bias-disable;
- };
- };
-
- tdmb_din2_pins: tdmb_din2 {
- mux {
- groups = "tdmb_din2";
- function = "tdmb";
- bias-disable;
- };
- };
-
- tdmb_din3_pins: tdmb_din3 {
- mux {
- groups = "tdmb_din3";
- function = "tdmb";
- bias-disable;
- };
- };
-
- tdmb_dout0_pins: tdmb_dout0 {
- mux {
- groups = "tdmb_dout0";
- function = "tdmb";
- bias-disable;
- };
- };
-
- tdmb_dout1_pins: tdmb_dout1 {
- mux {
- groups = "tdmb_dout1";
- function = "tdmb";
- bias-disable;
- };
- };
-
- tdmb_dout2_pins: tdmb_dout2 {
- mux {
- groups = "tdmb_dout2";
- function = "tdmb";
- bias-disable;
- };
- };
-
- tdmb_dout3_pins: tdmb_dout3 {
- mux {
- groups = "tdmb_dout3";
- function = "tdmb";
- bias-disable;
- };
- };
-
- tdmb_fs_pins: tdmb_fs {
- mux {
- groups = "tdmb_fs";
- function = "tdmb";
- bias-disable;
- };
- };
-
- tdmb_fs_slv_pins: tdmb_fs_slv {
- mux {
- groups = "tdmb_fs_slv";
- function = "tdmb";
- bias-disable;
- };
- };
-
- tdmb_sclk_pins: tdmb_sclk {
- mux {
- groups = "tdmb_sclk";
- function = "tdmb";
- bias-disable;
- };
- };
-
- tdmb_sclk_slv_pins: tdmb_sclk_slv {
- mux {
- groups = "tdmb_sclk_slv";
- function = "tdmb";
- bias-disable;
- };
- };
-
- tdmc_fs_pins: tdmc_fs {
- mux {
- groups = "tdmc_fs";
- function = "tdmc";
- bias-disable;
- };
- };
-
- tdmc_fs_slv_pins: tdmc_fs_slv {
- mux {
- groups = "tdmc_fs_slv";
- function = "tdmc";
- bias-disable;
- };
- };
-
- tdmc_sclk_pins: tdmc_sclk {
- mux {
- groups = "tdmc_sclk";
- function = "tdmc";
- bias-disable;
- };
- };
-
- tdmc_sclk_slv_pins: tdmc_sclk_slv {
- mux {
- groups = "tdmc_sclk_slv";
- function = "tdmc";
- bias-disable;
- };
- };
-
- tdmc_din0_pins: tdmc_din0 {
- mux {
- groups = "tdmc_din0";
- function = "tdmc";
- bias-disable;
- };
- };
-
- tdmc_din1_pins: tdmc_din1 {
- mux {
- groups = "tdmc_din1";
- function = "tdmc";
- bias-disable;
- };
- };
-
- tdmc_din2_pins: tdmc_din2 {
- mux {
- groups = "tdmc_din2";
- function = "tdmc";
- bias-disable;
- };
- };
-
- tdmc_din3_pins: tdmc_din3 {
- mux {
- groups = "tdmc_din3";
- function = "tdmc";
- bias-disable;
- };
- };
-
- tdmc_dout0_pins: tdmc_dout0 {
- mux {
- groups = "tdmc_dout0";
- function = "tdmc";
- bias-disable;
- };
- };
-
- tdmc_dout1_pins: tdmc_dout1 {
- mux {
- groups = "tdmc_dout1";
- function = "tdmc";
- bias-disable;
- };
- };
-
- tdmc_dout2_pins: tdmc_dout2 {
- mux {
- groups = "tdmc_dout2";
- function = "tdmc";
- bias-disable;
- };
- };
-
- tdmc_dout3_pins: tdmc_dout3 {
- mux {
- groups = "tdmc_dout3";
- function = "tdmc";
- bias-disable;
- };
- };
-
- uart_a_pins: uart_a {
- mux {
- groups = "uart_tx_a",
- "uart_rx_a";
- function = "uart_a";
- bias-disable;
- };
- };
-
- uart_a_cts_rts_pins: uart_a_cts_rts {
- mux {
- groups = "uart_cts_a",
- "uart_rts_a";
- function = "uart_a";
- bias-disable;
- };
- };
-
- uart_b_x_pins: uart_b_x {
- mux {
- groups = "uart_tx_b_x",
- "uart_rx_b_x";
- function = "uart_b";
- bias-disable;
- };
- };
-
- uart_b_x_cts_rts_pins: uart_b_x_cts_rts {
- mux {
- groups = "uart_cts_b_x",
- "uart_rts_b_x";
- function = "uart_b";
- bias-disable;
- };
- };
-
- uart_b_z_pins: uart_b_z {
- mux {
- groups = "uart_tx_b_z",
- "uart_rx_b_z";
- function = "uart_b";
- bias-disable;
- };
- };
-
- uart_b_z_cts_rts_pins: uart_b_z_cts_rts {
- mux {
- groups = "uart_cts_b_z",
- "uart_rts_b_z";
- function = "uart_b";
- bias-disable;
- };
- };
-
- uart_ao_b_z_pins: uart_ao_b_z {
- mux {
- groups = "uart_ao_tx_b_z",
- "uart_ao_rx_b_z";
- function = "uart_ao_b_z";
- bias-disable;
- };
- };
-
- uart_ao_b_z_cts_rts_pins: uart_ao_b_z_cts_rts {
- mux {
- groups = "uart_ao_cts_b_z",
- "uart_ao_rts_b_z";
- function = "uart_ao_b_z";
- bias-disable;
- };
- };
- };
- };
-
- hiubus: bus@ff63c000 {
- compatible = "simple-bus";
- reg = <0x0 0xff63c000 0x0 0x1c00>;
- #address-cells = <2>;
- #size-cells = <2>;
- ranges = <0x0 0x0 0x0 0xff63c000 0x0 0x1c00>;
-
- sysctrl: system-controller@0 {
- compatible = "amlogic,meson-axg-hhi-sysctrl",
- "simple-mfd", "syscon";
- reg = <0 0 0 0x400>;
-
- clkc: clock-controller {
- compatible = "amlogic,axg-clkc";
- #clock-cells = <1>;
- clocks = <&xtal>;
- clock-names = "xtal";
- };
-
- pwrc: power-controller {
- compatible = "amlogic,meson-axg-pwrc";
- #power-domain-cells = <1>;
- amlogic,ao-sysctrl = <&sysctrl_AO>;
- resets = <&reset RESET_VIU>,
- <&reset RESET_VENC>,
- <&reset RESET_VCBUS>,
- <&reset RESET_VENCL>,
- <&reset RESET_VID_LOCK>;
- reset-names = "viu", "venc", "vcbus",
- "vencl", "vid_lock";
- clocks = <&clkc CLKID_VPU>,
- <&clkc CLKID_VAPB>;
- clock-names = "vpu", "vapb";
- /*
- * VPU clocking is provided by two identical clock paths
- * VPU_0 and VPU_1 muxed to a single clock by a glitch
- * free mux to safely change frequency while running.
- * Same for VAPB but with a final gate after the glitch free mux.
- */
- assigned-clocks = <&clkc CLKID_VPU_0_SEL>,
- <&clkc CLKID_VPU_0>,
- <&clkc CLKID_VPU>, /* Glitch free mux */
- <&clkc CLKID_VAPB_0_SEL>,
- <&clkc CLKID_VAPB_0>,
- <&clkc CLKID_VAPB_SEL>; /* Glitch free mux */
- assigned-clock-parents = <&clkc CLKID_FCLK_DIV4>,
- <0>, /* Do Nothing */
- <&clkc CLKID_VPU_0>,
- <&clkc CLKID_FCLK_DIV4>,
- <0>, /* Do Nothing */
- <&clkc CLKID_VAPB_0>;
- assigned-clock-rates = <0>, /* Do Nothing */
- <250000000>,
- <0>, /* Do Nothing */
- <0>, /* Do Nothing */
- <250000000>,
- <0>; /* Do Nothing */
- };
-
- mipi_pcie_analog_dphy: phy {
- compatible = "amlogic,axg-mipi-pcie-analog-phy";
- #phy-cells = <0>;
- status = "disabled";
- };
- };
- };
-
- mailbox: mailbox@ff63c404 {
- compatible = "amlogic,meson-gxbb-mhu";
- reg = <0 0xff63c404 0 0x4c>;
- interrupts = <GIC_SPI 208 IRQ_TYPE_EDGE_RISING>,
- <GIC_SPI 209 IRQ_TYPE_EDGE_RISING>,
- <GIC_SPI 210 IRQ_TYPE_EDGE_RISING>;
- #mbox-cells = <1>;
- };
-
- mipi_dphy: phy@ff640000 {
- compatible = "amlogic,axg-mipi-dphy";
- reg = <0x0 0xff640000 0x0 0x100>;
- clocks = <&clkc CLKID_MIPI_DSI_PHY>;
- clock-names = "pclk";
- resets = <&reset RESET_MIPI_PHY>;
- reset-names = "phy";
- phys = <&mipi_pcie_analog_dphy>;
- phy-names = "analog";
- #phy-cells = <0>;
- status = "disabled";
- };
-
- audio: bus@ff642000 {
- compatible = "simple-bus";
- reg = <0x0 0xff642000 0x0 0x2000>;
- #address-cells = <2>;
- #size-cells = <2>;
- ranges = <0x0 0x0 0x0 0xff642000 0x0 0x2000>;
-
- clkc_audio: clock-controller@0 {
- compatible = "amlogic,axg-audio-clkc";
- reg = <0x0 0x0 0x0 0xb4>;
- #clock-cells = <1>;
-
- clocks = <&clkc CLKID_AUDIO>,
- <&clkc CLKID_MPLL0>,
- <&clkc CLKID_MPLL1>,
- <&clkc CLKID_MPLL2>,
- <&clkc CLKID_MPLL3>,
- <&clkc CLKID_HIFI_PLL>,
- <&clkc CLKID_FCLK_DIV3>,
- <&clkc CLKID_FCLK_DIV4>,
- <&clkc CLKID_GP0_PLL>;
- clock-names = "pclk",
- "mst_in0",
- "mst_in1",
- "mst_in2",
- "mst_in3",
- "mst_in4",
- "mst_in5",
- "mst_in6",
- "mst_in7";
-
- resets = <&reset RESET_AUDIO>;
- };
-
- toddr_a: audio-controller@100 {
- compatible = "amlogic,axg-toddr";
- reg = <0x0 0x100 0x0 0x2c>;
- #sound-dai-cells = <0>;
- sound-name-prefix = "TODDR_A";
- interrupts = <GIC_SPI 84 IRQ_TYPE_EDGE_RISING>;
- clocks = <&clkc_audio AUD_CLKID_TODDR_A>;
- resets = <&arb AXG_ARB_TODDR_A>;
- amlogic,fifo-depth = <512>;
- status = "disabled";
- };
-
- toddr_b: audio-controller@140 {
- compatible = "amlogic,axg-toddr";
- reg = <0x0 0x140 0x0 0x2c>;
- #sound-dai-cells = <0>;
- sound-name-prefix = "TODDR_B";
- interrupts = <GIC_SPI 85 IRQ_TYPE_EDGE_RISING>;
- clocks = <&clkc_audio AUD_CLKID_TODDR_B>;
- resets = <&arb AXG_ARB_TODDR_B>;
- amlogic,fifo-depth = <256>;
- status = "disabled";
- };
-
- toddr_c: audio-controller@180 {
- compatible = "amlogic,axg-toddr";
- reg = <0x0 0x180 0x0 0x2c>;
- #sound-dai-cells = <0>;
- sound-name-prefix = "TODDR_C";
- interrupts = <GIC_SPI 86 IRQ_TYPE_EDGE_RISING>;
- clocks = <&clkc_audio AUD_CLKID_TODDR_C>;
- resets = <&arb AXG_ARB_TODDR_C>;
- amlogic,fifo-depth = <256>;
- status = "disabled";
- };
-
- frddr_a: audio-controller@1c0 {
- compatible = "amlogic,axg-frddr";
- reg = <0x0 0x1c0 0x0 0x2c>;
- #sound-dai-cells = <0>;
- sound-name-prefix = "FRDDR_A";
- interrupts = <GIC_SPI 88 IRQ_TYPE_EDGE_RISING>;
- clocks = <&clkc_audio AUD_CLKID_FRDDR_A>;
- resets = <&arb AXG_ARB_FRDDR_A>;
- amlogic,fifo-depth = <512>;
- status = "disabled";
- };
-
- frddr_b: audio-controller@200 {
- compatible = "amlogic,axg-frddr";
- reg = <0x0 0x200 0x0 0x2c>;
- #sound-dai-cells = <0>;
- sound-name-prefix = "FRDDR_B";
- interrupts = <GIC_SPI 89 IRQ_TYPE_EDGE_RISING>;
- clocks = <&clkc_audio AUD_CLKID_FRDDR_B>;
- resets = <&arb AXG_ARB_FRDDR_B>;
- amlogic,fifo-depth = <256>;
- status = "disabled";
- };
-
- frddr_c: audio-controller@240 {
- compatible = "amlogic,axg-frddr";
- reg = <0x0 0x240 0x0 0x2c>;
- #sound-dai-cells = <0>;
- sound-name-prefix = "FRDDR_C";
- interrupts = <GIC_SPI 90 IRQ_TYPE_EDGE_RISING>;
- clocks = <&clkc_audio AUD_CLKID_FRDDR_C>;
- resets = <&arb AXG_ARB_FRDDR_C>;
- amlogic,fifo-depth = <256>;
- status = "disabled";
- };
-
- arb: reset-controller@280 {
- compatible = "amlogic,meson-axg-audio-arb";
- reg = <0x0 0x280 0x0 0x4>;
- #reset-cells = <1>;
- clocks = <&clkc_audio AUD_CLKID_DDR_ARB>;
- };
-
- tdmin_a: audio-controller@300 {
- compatible = "amlogic,axg-tdmin";
- reg = <0x0 0x300 0x0 0x40>;
- sound-name-prefix = "TDMIN_A";
- clocks = <&clkc_audio AUD_CLKID_TDMIN_A>,
- <&clkc_audio AUD_CLKID_TDMIN_A_SCLK>,
- <&clkc_audio AUD_CLKID_TDMIN_A_SCLK_SEL>,
- <&clkc_audio AUD_CLKID_TDMIN_A_LRCLK>,
- <&clkc_audio AUD_CLKID_TDMIN_A_LRCLK>;
- clock-names = "pclk", "sclk", "sclk_sel",
- "lrclk", "lrclk_sel";
- status = "disabled";
- };
-
- tdmin_b: audio-controller@340 {
- compatible = "amlogic,axg-tdmin";
- reg = <0x0 0x340 0x0 0x40>;
- sound-name-prefix = "TDMIN_B";
- clocks = <&clkc_audio AUD_CLKID_TDMIN_B>,
- <&clkc_audio AUD_CLKID_TDMIN_B_SCLK>,
- <&clkc_audio AUD_CLKID_TDMIN_B_SCLK_SEL>,
- <&clkc_audio AUD_CLKID_TDMIN_B_LRCLK>,
- <&clkc_audio AUD_CLKID_TDMIN_B_LRCLK>;
- clock-names = "pclk", "sclk", "sclk_sel",
- "lrclk", "lrclk_sel";
- status = "disabled";
- };
-
- tdmin_c: audio-controller@380 {
- compatible = "amlogic,axg-tdmin";
- reg = <0x0 0x380 0x0 0x40>;
- sound-name-prefix = "TDMIN_C";
- clocks = <&clkc_audio AUD_CLKID_TDMIN_C>,
- <&clkc_audio AUD_CLKID_TDMIN_C_SCLK>,
- <&clkc_audio AUD_CLKID_TDMIN_C_SCLK_SEL>,
- <&clkc_audio AUD_CLKID_TDMIN_C_LRCLK>,
- <&clkc_audio AUD_CLKID_TDMIN_C_LRCLK>;
- clock-names = "pclk", "sclk", "sclk_sel",
- "lrclk", "lrclk_sel";
- status = "disabled";
- };
-
- tdmin_lb: audio-controller@3c0 {
- compatible = "amlogic,axg-tdmin";
- reg = <0x0 0x3c0 0x0 0x40>;
- sound-name-prefix = "TDMIN_LB";
- clocks = <&clkc_audio AUD_CLKID_TDMIN_LB>,
- <&clkc_audio AUD_CLKID_TDMIN_LB_SCLK>,
- <&clkc_audio AUD_CLKID_TDMIN_LB_SCLK_SEL>,
- <&clkc_audio AUD_CLKID_TDMIN_LB_LRCLK>,
- <&clkc_audio AUD_CLKID_TDMIN_LB_LRCLK>;
- clock-names = "pclk", "sclk", "sclk_sel",
- "lrclk", "lrclk_sel";
- status = "disabled";
- };
-
- spdifin: audio-controller@400 {
- compatible = "amlogic,axg-spdifin";
- reg = <0x0 0x400 0x0 0x30>;
- #sound-dai-cells = <0>;
- sound-name-prefix = "SPDIFIN";
- interrupts = <GIC_SPI 87 IRQ_TYPE_EDGE_RISING>;
- clocks = <&clkc_audio AUD_CLKID_SPDIFIN>,
- <&clkc_audio AUD_CLKID_SPDIFIN_CLK>;
- clock-names = "pclk", "refclk";
- status = "disabled";
- };
-
- spdifout: audio-controller@480 {
- compatible = "amlogic,axg-spdifout";
- reg = <0x0 0x480 0x0 0x50>;
- #sound-dai-cells = <0>;
- sound-name-prefix = "SPDIFOUT";
- clocks = <&clkc_audio AUD_CLKID_SPDIFOUT>,
- <&clkc_audio AUD_CLKID_SPDIFOUT_CLK>;
- clock-names = "pclk", "mclk";
- status = "disabled";
- };
-
- tdmout_a: audio-controller@500 {
- compatible = "amlogic,axg-tdmout";
- reg = <0x0 0x500 0x0 0x40>;
- sound-name-prefix = "TDMOUT_A";
- clocks = <&clkc_audio AUD_CLKID_TDMOUT_A>,
- <&clkc_audio AUD_CLKID_TDMOUT_A_SCLK>,
- <&clkc_audio AUD_CLKID_TDMOUT_A_SCLK_SEL>,
- <&clkc_audio AUD_CLKID_TDMOUT_A_LRCLK>,
- <&clkc_audio AUD_CLKID_TDMOUT_A_LRCLK>;
- clock-names = "pclk", "sclk", "sclk_sel",
- "lrclk", "lrclk_sel";
- status = "disabled";
- };
-
- tdmout_b: audio-controller@540 {
- compatible = "amlogic,axg-tdmout";
- reg = <0x0 0x540 0x0 0x40>;
- sound-name-prefix = "TDMOUT_B";
- clocks = <&clkc_audio AUD_CLKID_TDMOUT_B>,
- <&clkc_audio AUD_CLKID_TDMOUT_B_SCLK>,
- <&clkc_audio AUD_CLKID_TDMOUT_B_SCLK_SEL>,
- <&clkc_audio AUD_CLKID_TDMOUT_B_LRCLK>,
- <&clkc_audio AUD_CLKID_TDMOUT_B_LRCLK>;
- clock-names = "pclk", "sclk", "sclk_sel",
- "lrclk", "lrclk_sel";
- status = "disabled";
- };
-
- tdmout_c: audio-controller@580 {
- compatible = "amlogic,axg-tdmout";
- reg = <0x0 0x580 0x0 0x40>;
- sound-name-prefix = "TDMOUT_C";
- clocks = <&clkc_audio AUD_CLKID_TDMOUT_C>,
- <&clkc_audio AUD_CLKID_TDMOUT_C_SCLK>,
- <&clkc_audio AUD_CLKID_TDMOUT_C_SCLK_SEL>,
- <&clkc_audio AUD_CLKID_TDMOUT_C_LRCLK>,
- <&clkc_audio AUD_CLKID_TDMOUT_C_LRCLK>;
- clock-names = "pclk", "sclk", "sclk_sel",
- "lrclk", "lrclk_sel";
- status = "disabled";
- };
- };
-
- aobus: bus@ff800000 {
- compatible = "simple-bus";
- reg = <0x0 0xff800000 0x0 0x100000>;
- #address-cells = <2>;
- #size-cells = <2>;
- ranges = <0x0 0x0 0x0 0xff800000 0x0 0x100000>;
-
- sysctrl_AO: sys-ctrl@0 {
- compatible = "amlogic,meson-axg-ao-sysctrl", "simple-mfd", "syscon";
- reg = <0x0 0x0 0x0 0x100>;
-
- clkc_AO: clock-controller {
- compatible = "amlogic,meson-axg-aoclkc";
- #clock-cells = <1>;
- #reset-cells = <1>;
- clocks = <&xtal>, <&clkc CLKID_CLK81>;
- clock-names = "xtal", "mpeg-clk";
- };
- };
-
- pinctrl_aobus: pinctrl@14 {
- compatible = "amlogic,meson-axg-aobus-pinctrl";
- #address-cells = <2>;
- #size-cells = <2>;
- ranges;
-
- gpio_ao: bank@14 {
- reg = <0x0 0x00014 0x0 0x8>,
- <0x0 0x0002c 0x0 0x4>,
- <0x0 0x00024 0x0 0x8>;
- reg-names = "mux", "pull", "gpio";
- gpio-controller;
- #gpio-cells = <2>;
- gpio-ranges = <&pinctrl_aobus 0 0 15>;
- };
-
- i2c_ao_sck_4_pins: i2c_ao_sck_4 {
- mux {
- groups = "i2c_ao_sck_4";
- function = "i2c_ao";
- bias-disable;
- };
- };
-
- i2c_ao_sck_8_pins: i2c_ao_sck_8 {
- mux {
- groups = "i2c_ao_sck_8";
- function = "i2c_ao";
- bias-disable;
- };
- };
-
- i2c_ao_sck_10_pins: i2c_ao_sck_10 {
- mux {
- groups = "i2c_ao_sck_10";
- function = "i2c_ao";
- bias-disable;
- };
- };
-
- i2c_ao_sda_5_pins: i2c_ao_sda_5 {
- mux {
- groups = "i2c_ao_sda_5";
- function = "i2c_ao";
- bias-disable;
- };
- };
-
- i2c_ao_sda_9_pins: i2c_ao_sda_9 {
- mux {
- groups = "i2c_ao_sda_9";
- function = "i2c_ao";
- bias-disable;
- };
- };
-
- i2c_ao_sda_11_pins: i2c_ao_sda_11 {
- mux {
- groups = "i2c_ao_sda_11";
- function = "i2c_ao";
- bias-disable;
- };
- };
-
- remote_input_ao_pins: remote_input_ao {
- mux {
- groups = "remote_input_ao";
- function = "remote_input_ao";
- bias-disable;
- };
- };
-
- uart_ao_a_pins: uart_ao_a {
- mux {
- groups = "uart_ao_tx_a",
- "uart_ao_rx_a";
- function = "uart_ao_a";
- bias-disable;
- };
- };
-
- uart_ao_a_cts_rts_pins: uart_ao_a_cts_rts {
- mux {
- groups = "uart_ao_cts_a",
- "uart_ao_rts_a";
- function = "uart_ao_a";
- bias-disable;
- };
- };
-
- uart_ao_b_pins: uart_ao_b {
- mux {
- groups = "uart_ao_tx_b",
- "uart_ao_rx_b";
- function = "uart_ao_b";
- bias-disable;
- };
- };
-
- uart_ao_b_cts_rts_pins: uart_ao_b_cts_rts {
- mux {
- groups = "uart_ao_cts_b",
- "uart_ao_rts_b";
- function = "uart_ao_b";
- bias-disable;
- };
- };
- };
-
- sec_AO: ao-secure@140 {
- compatible = "amlogic,meson-gx-ao-secure", "syscon";
- reg = <0x0 0x140 0x0 0x140>;
- amlogic,has-chip-id;
- };
-
- pwm_AO_cd: pwm@2000 {
- compatible = "amlogic,meson-axg-ao-pwm";
- reg = <0x0 0x02000 0x0 0x20>;
- #pwm-cells = <3>;
- status = "disabled";
- };
-
- uart_AO: serial@3000 {
- compatible = "amlogic,meson-gx-uart", "amlogic,meson-ao-uart";
- reg = <0x0 0x3000 0x0 0x18>;
- interrupts = <GIC_SPI 193 IRQ_TYPE_EDGE_RISING>;
- clocks = <&xtal>, <&clkc_AO CLKID_AO_UART1>, <&xtal>;
- clock-names = "xtal", "pclk", "baud";
- status = "disabled";
- };
-
- uart_AO_B: serial@4000 {
- compatible = "amlogic,meson-gx-uart", "amlogic,meson-ao-uart";
- reg = <0x0 0x4000 0x0 0x18>;
- interrupts = <GIC_SPI 197 IRQ_TYPE_EDGE_RISING>;
- clocks = <&xtal>, <&clkc_AO CLKID_AO_UART2>, <&xtal>;
- clock-names = "xtal", "pclk", "baud";
- status = "disabled";
- };
-
- i2c_AO: i2c@5000 {
- compatible = "amlogic,meson-axg-i2c";
- reg = <0x0 0x05000 0x0 0x20>;
- interrupts = <GIC_SPI 195 IRQ_TYPE_EDGE_RISING>;
- clocks = <&clkc CLKID_AO_I2C>;
- #address-cells = <1>;
- #size-cells = <0>;
- status = "disabled";
- };
-
- pwm_AO_ab: pwm@7000 {
- compatible = "amlogic,meson-axg-ao-pwm";
- reg = <0x0 0x07000 0x0 0x20>;
- #pwm-cells = <3>;
- status = "disabled";
- };
-
- ir: ir@8000 {
- compatible = "amlogic,meson-gxbb-ir";
- reg = <0x0 0x8000 0x0 0x20>;
- interrupts = <GIC_SPI 196 IRQ_TYPE_EDGE_RISING>;
- status = "disabled";
- };
-
- saradc: adc@9000 {
- compatible = "amlogic,meson-axg-saradc",
- "amlogic,meson-saradc";
- reg = <0x0 0x9000 0x0 0x38>;
- #io-channel-cells = <1>;
- interrupts = <GIC_SPI 73 IRQ_TYPE_EDGE_RISING>;
- clocks = <&xtal>,
- <&clkc_AO CLKID_AO_SAR_ADC>,
- <&clkc_AO CLKID_AO_SAR_ADC_CLK>,
- <&clkc_AO CLKID_AO_SAR_ADC_SEL>;
- clock-names = "clkin", "core", "adc_clk", "adc_sel";
- status = "disabled";
- };
- };
-
- ge2d: ge2d@ff940000 {
- compatible = "amlogic,axg-ge2d";
- reg = <0x0 0xff940000 0x0 0x10000>;
- interrupts = <GIC_SPI 150 IRQ_TYPE_EDGE_RISING>;
- clocks = <&clkc CLKID_VAPB>;
- resets = <&reset RESET_GE2D>;
- };
-
- gic: interrupt-controller@ffc01000 {
- compatible = "arm,gic-400";
- reg = <0x0 0xffc01000 0 0x1000>,
- <0x0 0xffc02000 0 0x2000>,
- <0x0 0xffc04000 0 0x2000>,
- <0x0 0xffc06000 0 0x2000>;
- interrupt-controller;
- interrupts = <GIC_PPI 9
- (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_HIGH)>;
- #interrupt-cells = <3>;
- #address-cells = <0>;
- };
-
- cbus: bus@ffd00000 {
- compatible = "simple-bus";
- reg = <0x0 0xffd00000 0x0 0x25000>;
- #address-cells = <2>;
- #size-cells = <2>;
- ranges = <0x0 0x0 0x0 0xffd00000 0x0 0x25000>;
-
- reset: reset-controller@1004 {
- compatible = "amlogic,meson-axg-reset";
- reg = <0x0 0x01004 0x0 0x9c>;
- #reset-cells = <1>;
- };
-
- gpio_intc: interrupt-controller@f080 {
- compatible = "amlogic,meson-axg-gpio-intc",
- "amlogic,meson-gpio-intc";
- reg = <0x0 0xf080 0x0 0x10>;
- interrupt-controller;
- #interrupt-cells = <2>;
- amlogic,channel-interrupts = <64 65 66 67 68 69 70 71>;
- };
-
- watchdog@f0d0 {
- compatible = "amlogic,meson-gxbb-wdt";
- reg = <0x0 0xf0d0 0x0 0x10>;
- clocks = <&xtal>;
- };
-
- pwm_ab: pwm@1b000 {
- compatible = "amlogic,meson-axg-ee-pwm";
- reg = <0x0 0x1b000 0x0 0x20>;
- #pwm-cells = <3>;
- status = "disabled";
- };
-
- pwm_cd: pwm@1a000 {
- compatible = "amlogic,meson-axg-ee-pwm";
- reg = <0x0 0x1a000 0x0 0x20>;
- #pwm-cells = <3>;
- status = "disabled";
- };
-
- spicc0: spi@13000 {
- compatible = "amlogic,meson-axg-spicc";
- reg = <0x0 0x13000 0x0 0x3c>;
- interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&clkc CLKID_SPICC0>;
- clock-names = "core";
- #address-cells = <1>;
- #size-cells = <0>;
- status = "disabled";
- };
-
- spicc1: spi@15000 {
- compatible = "amlogic,meson-axg-spicc";
- reg = <0x0 0x15000 0x0 0x3c>;
- interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&clkc CLKID_SPICC1>;
- clock-names = "core";
- #address-cells = <1>;
- #size-cells = <0>;
- status = "disabled";
- };
-
- clk_msr: clock-measure@18000 {
- compatible = "amlogic,meson-axg-clk-measure";
- reg = <0x0 0x18000 0x0 0x10>;
- };
-
- i2c3: i2c@1c000 {
- compatible = "amlogic,meson-axg-i2c";
- reg = <0x0 0x1c000 0x0 0x20>;
- interrupts = <GIC_SPI 39 IRQ_TYPE_EDGE_RISING>;
- clocks = <&clkc CLKID_I2C>;
- #address-cells = <1>;
- #size-cells = <0>;
- status = "disabled";
- };
-
- i2c2: i2c@1d000 {
- compatible = "amlogic,meson-axg-i2c";
- reg = <0x0 0x1d000 0x0 0x20>;
- interrupts = <GIC_SPI 215 IRQ_TYPE_EDGE_RISING>;
- clocks = <&clkc CLKID_I2C>;
- #address-cells = <1>;
- #size-cells = <0>;
- status = "disabled";
- };
-
- i2c1: i2c@1e000 {
- compatible = "amlogic,meson-axg-i2c";
- reg = <0x0 0x1e000 0x0 0x20>;
- interrupts = <GIC_SPI 214 IRQ_TYPE_EDGE_RISING>;
- clocks = <&clkc CLKID_I2C>;
- #address-cells = <1>;
- #size-cells = <0>;
- status = "disabled";
- };
-
- i2c0: i2c@1f000 {
- compatible = "amlogic,meson-axg-i2c";
- reg = <0x0 0x1f000 0x0 0x20>;
- interrupts = <GIC_SPI 21 IRQ_TYPE_EDGE_RISING>;
- clocks = <&clkc CLKID_I2C>;
- #address-cells = <1>;
- #size-cells = <0>;
- status = "disabled";
- };
-
- uart_B: serial@23000 {
- compatible = "amlogic,meson-gx-uart";
- reg = <0x0 0x23000 0x0 0x18>;
- interrupts = <GIC_SPI 75 IRQ_TYPE_EDGE_RISING>;
- status = "disabled";
- clocks = <&xtal>, <&clkc CLKID_UART1>, <&xtal>;
- clock-names = "xtal", "pclk", "baud";
- };
-
- uart_A: serial@24000 {
- compatible = "amlogic,meson-gx-uart";
- reg = <0x0 0x24000 0x0 0x18>;
- interrupts = <GIC_SPI 26 IRQ_TYPE_EDGE_RISING>;
- status = "disabled";
- clocks = <&xtal>, <&clkc CLKID_UART0>, <&xtal>;
- clock-names = "xtal", "pclk", "baud";
- fifo-size = <128>;
- };
- };
-
- apb: bus@ffe00000 {
- compatible = "simple-bus";
- reg = <0x0 0xffe00000 0x0 0x200000>;
- #address-cells = <2>;
- #size-cells = <2>;
- ranges = <0x0 0x0 0x0 0xffe00000 0x0 0x200000>;
-
- sd_emmc_b: sd@5000 {
- compatible = "amlogic,meson-axg-mmc";
- reg = <0x0 0x5000 0x0 0x800>;
- interrupts = <GIC_SPI 217 IRQ_TYPE_EDGE_RISING>;
- status = "disabled";
- clocks = <&clkc CLKID_SD_EMMC_B>,
- <&clkc CLKID_SD_EMMC_B_CLK0>,
- <&clkc CLKID_FCLK_DIV2>;
- clock-names = "core", "clkin0", "clkin1";
- resets = <&reset RESET_SD_EMMC_B>;
- };
-
- sd_emmc_c: mmc@7000 {
- compatible = "amlogic,meson-axg-mmc";
- reg = <0x0 0x7000 0x0 0x800>;
- interrupts = <GIC_SPI 218 IRQ_TYPE_EDGE_RISING>;
- status = "disabled";
- clocks = <&clkc CLKID_SD_EMMC_C>,
- <&clkc CLKID_SD_EMMC_C_CLK0>,
- <&clkc CLKID_FCLK_DIV2>;
- clock-names = "core", "clkin0", "clkin1";
- resets = <&reset RESET_SD_EMMC_C>;
- };
-
- usb2_phy1: phy@9020 {
- compatible = "amlogic,meson-gxl-usb2-phy";
- #phy-cells = <0>;
- reg = <0x0 0x9020 0x0 0x20>;
- clocks = <&clkc CLKID_USB>;
- clock-names = "phy";
- resets = <&reset RESET_USB_OTG>;
- reset-names = "phy";
- };
- };
-
- sram: sram@fffc0000 {
- compatible = "mmio-sram";
- reg = <0x0 0xfffc0000 0x0 0x20000>;
- #address-cells = <1>;
- #size-cells = <1>;
- ranges = <0 0x0 0xfffc0000 0x20000>;
-
- cpu_scp_lpri: scp-sram@13000 {
- compatible = "amlogic,meson-axg-scp-shmem";
- reg = <0x13000 0x400>;
- };
-
- cpu_scp_hpri: scp-sram@13400 {
- compatible = "amlogic,meson-axg-scp-shmem";
- reg = <0x13400 0x400>;
- };
- };
- };
-
- timer {
- compatible = "arm,armv8-timer";
- interrupts = <GIC_PPI 13
- (GIC_CPU_MASK_RAW(0xff) | IRQ_TYPE_LEVEL_LOW)>,
- <GIC_PPI 14
- (GIC_CPU_MASK_RAW(0xff) | IRQ_TYPE_LEVEL_LOW)>,
- <GIC_PPI 11
- (GIC_CPU_MASK_RAW(0xff) | IRQ_TYPE_LEVEL_LOW)>,
- <GIC_PPI 10
- (GIC_CPU_MASK_RAW(0xff) | IRQ_TYPE_LEVEL_LOW)>;
- };
-
- xtal: xtal-clk {
- compatible = "fixed-clock";
- clock-frequency = <24000000>;
- clock-output-names = "xtal";
- #clock-cells = <0>;
- };
-};
diff --git a/arch/arm/dts/meson-g12-common.dtsi b/arch/arm/dts/meson-g12-common.dtsi
deleted file mode 100644
index 9dbd508..0000000
--- a/arch/arm/dts/meson-g12-common.dtsi
+++ /dev/null
@@ -1,2493 +0,0 @@
-// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
-/*
- * Copyright (c) 2018 Amlogic, Inc. All rights reserved.
- */
-
-#include <dt-bindings/phy/phy.h>
-#include <dt-bindings/gpio/gpio.h>
-#include <dt-bindings/clock/g12a-clkc.h>
-#include <dt-bindings/clock/g12a-aoclkc.h>
-#include <dt-bindings/interrupt-controller/irq.h>
-#include <dt-bindings/interrupt-controller/arm-gic.h>
-#include <dt-bindings/reset/amlogic,meson-g12a-reset.h>
-#include <dt-bindings/thermal/thermal.h>
-
-/ {
- interrupt-parent = <&gic>;
- #address-cells = <2>;
- #size-cells = <2>;
-
- aliases {
- mmc0 = &sd_emmc_b; /* SD card */
- mmc1 = &sd_emmc_c; /* eMMC */
- mmc2 = &sd_emmc_a; /* SDIO */
- };
-
- chosen {
- #address-cells = <2>;
- #size-cells = <2>;
- ranges;
-
- simplefb_cvbs: framebuffer-cvbs {
- compatible = "amlogic,simple-framebuffer",
- "simple-framebuffer";
- amlogic,pipeline = "vpu-cvbs";
- clocks = <&clkc CLKID_HDMI>,
- <&clkc CLKID_HTX_PCLK>,
- <&clkc CLKID_VPU_INTR>;
- status = "disabled";
- };
-
- simplefb_hdmi: framebuffer-hdmi {
- compatible = "amlogic,simple-framebuffer",
- "simple-framebuffer";
- amlogic,pipeline = "vpu-hdmi";
- clocks = <&clkc CLKID_HDMI>,
- <&clkc CLKID_HTX_PCLK>,
- <&clkc CLKID_VPU_INTR>;
- status = "disabled";
- };
- };
-
- efuse: efuse {
- compatible = "amlogic,meson-gxbb-efuse";
- clocks = <&clkc CLKID_EFUSE>;
- #address-cells = <1>;
- #size-cells = <1>;
- read-only;
- secure-monitor = <&sm>;
- };
-
- gpu_opp_table: opp-table-gpu {
- compatible = "operating-points-v2";
-
- opp-124999998 {
- opp-hz = /bits/ 64 <124999998>;
- opp-microvolt = <800000>;
- };
- opp-249999996 {
- opp-hz = /bits/ 64 <249999996>;
- opp-microvolt = <800000>;
- };
- opp-285714281 {
- opp-hz = /bits/ 64 <285714281>;
- opp-microvolt = <800000>;
- };
- opp-399999994 {
- opp-hz = /bits/ 64 <399999994>;
- opp-microvolt = <800000>;
- };
- opp-499999992 {
- opp-hz = /bits/ 64 <499999992>;
- opp-microvolt = <800000>;
- };
- opp-666666656 {
- opp-hz = /bits/ 64 <666666656>;
- opp-microvolt = <800000>;
- };
- opp-799999987 {
- opp-hz = /bits/ 64 <799999987>;
- opp-microvolt = <800000>;
- };
- };
-
- psci {
- compatible = "arm,psci-1.0";
- method = "smc";
- };
-
- reserved-memory {
- #address-cells = <2>;
- #size-cells = <2>;
- ranges;
-
- /* 3 MiB reserved for ARM Trusted Firmware (BL31) */
- secmon_reserved: secmon@5000000 {
- reg = <0x0 0x05000000 0x0 0x300000>;
- no-map;
- };
-
- /* 32 MiB reserved for ARM Trusted Firmware (BL32) */
- secmon_reserved_bl32: secmon@5300000 {
- reg = <0x0 0x05300000 0x0 0x2000000>;
- no-map;
- };
-
- linux,cma {
- compatible = "shared-dma-pool";
- reusable;
- size = <0x0 0x10000000>;
- alignment = <0x0 0x400000>;
- linux,cma-default;
- };
- };
-
- sm: secure-monitor {
- compatible = "amlogic,meson-gxbb-sm";
- };
-
- soc {
- compatible = "simple-bus";
- #address-cells = <2>;
- #size-cells = <2>;
- ranges;
-
- pcie: pcie@fc000000 {
- compatible = "amlogic,g12a-pcie", "snps,dw-pcie";
- reg = <0x0 0xfc000000 0x0 0x400000>,
- <0x0 0xff648000 0x0 0x2000>,
- <0x0 0xfc400000 0x0 0x200000>;
- reg-names = "elbi", "cfg", "config";
- interrupts = <GIC_SPI 221 IRQ_TYPE_LEVEL_HIGH>;
- #interrupt-cells = <1>;
- interrupt-map-mask = <0 0 0 0>;
- interrupt-map = <0 0 0 0 &gic GIC_SPI 223 IRQ_TYPE_LEVEL_HIGH>;
- bus-range = <0x0 0xff>;
- #address-cells = <3>;
- #size-cells = <2>;
- device_type = "pci";
- ranges = <0x81000000 0 0 0x0 0xfc600000 0 0x00100000>,
- <0x82000000 0 0xfc700000 0x0 0xfc700000 0 0x1900000>;
-
- clocks = <&clkc CLKID_PCIE_PHY
- &clkc CLKID_PCIE_COMB
- &clkc CLKID_PCIE_PLL>;
- clock-names = "general",
- "pclk",
- "port";
- resets = <&reset RESET_PCIE_CTRL_A>,
- <&reset RESET_PCIE_APB>;
- reset-names = "port",
- "apb";
- num-lanes = <1>;
- phys = <&usb3_pcie_phy PHY_TYPE_PCIE>;
- phy-names = "pcie";
- status = "disabled";
- };
-
- ethmac: ethernet@ff3f0000 {
- compatible = "amlogic,meson-g12a-dwmac",
- "snps,dwmac-3.70a",
- "snps,dwmac";
- reg = <0x0 0xff3f0000 0x0 0x10000>,
- <0x0 0xff634540 0x0 0x8>;
- interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
- interrupt-names = "macirq";
- clocks = <&clkc CLKID_ETH>,
- <&clkc CLKID_FCLK_DIV2>,
- <&clkc CLKID_MPLL2>,
- <&clkc CLKID_FCLK_DIV2>;
- clock-names = "stmmaceth", "clkin0", "clkin1",
- "timing-adjustment";
- rx-fifo-depth = <4096>;
- tx-fifo-depth = <2048>;
- status = "disabled";
-
- mdio0: mdio {
- #address-cells = <1>;
- #size-cells = <0>;
- compatible = "snps,dwmac-mdio";
- };
- };
-
- apb: bus@ff600000 {
- compatible = "simple-bus";
- reg = <0x0 0xff600000 0x0 0x200000>;
- #address-cells = <2>;
- #size-cells = <2>;
- ranges = <0x0 0x0 0x0 0xff600000 0x0 0x200000>;
-
- hdmi_tx: hdmi-tx@0 {
- compatible = "amlogic,meson-g12a-dw-hdmi";
- reg = <0x0 0x0 0x0 0x10000>;
- interrupts = <GIC_SPI 57 IRQ_TYPE_EDGE_RISING>;
- resets = <&reset RESET_HDMITX_CAPB3>,
- <&reset RESET_HDMITX_PHY>,
- <&reset RESET_HDMITX>;
- reset-names = "hdmitx_apb", "hdmitx", "hdmitx_phy";
- clocks = <&clkc CLKID_HDMI>,
- <&clkc CLKID_HTX_PCLK>,
- <&clkc CLKID_VPU_INTR>;
- clock-names = "isfr", "iahb", "venci";
- #address-cells = <1>;
- #size-cells = <0>;
- #sound-dai-cells = <0>;
- status = "disabled";
-
- /* VPU VENC Input */
- hdmi_tx_venc_port: port@0 {
- reg = <0>;
-
- hdmi_tx_in: endpoint {
- remote-endpoint = <&hdmi_tx_out>;
- };
- };
-
- /* TMDS Output */
- hdmi_tx_tmds_port: port@1 {
- reg = <1>;
- };
- };
-
- apb_efuse: bus@30000 {
- compatible = "simple-bus";
- reg = <0x0 0x30000 0x0 0x2000>;
- #address-cells = <2>;
- #size-cells = <2>;
- ranges = <0x0 0x0 0x0 0x30000 0x0 0x2000>;
-
- hwrng: rng@218 {
- compatible = "amlogic,meson-rng";
- reg = <0x0 0x218 0x0 0x4>;
- clocks = <&clkc CLKID_RNG0>;
- clock-names = "core";
- };
- };
-
- acodec: audio-controller@32000 {
- compatible = "amlogic,t9015";
- reg = <0x0 0x32000 0x0 0x14>;
- #sound-dai-cells = <0>;
- sound-name-prefix = "ACODEC";
- clocks = <&clkc CLKID_AUDIO_CODEC>;
- clock-names = "pclk";
- resets = <&reset RESET_AUDIO_CODEC>;
- status = "disabled";
- };
-
- periphs: bus@34400 {
- compatible = "simple-bus";
- reg = <0x0 0x34400 0x0 0x400>;
- #address-cells = <2>;
- #size-cells = <2>;
- ranges = <0x0 0x0 0x0 0x34400 0x0 0x400>;
-
- periphs_pinctrl: pinctrl@40 {
- compatible = "amlogic,meson-g12a-periphs-pinctrl";
- #address-cells = <2>;
- #size-cells = <2>;
- ranges;
-
- gpio: bank@40 {
- reg = <0x0 0x40 0x0 0x4c>,
- <0x0 0xe8 0x0 0x18>,
- <0x0 0x120 0x0 0x18>,
- <0x0 0x2c0 0x0 0x40>,
- <0x0 0x340 0x0 0x1c>;
- reg-names = "gpio",
- "pull",
- "pull-enable",
- "mux",
- "ds";
- gpio-controller;
- #gpio-cells = <2>;
- gpio-ranges = <&periphs_pinctrl 0 0 86>;
- };
-
- cec_ao_a_h_pins: cec_ao_a_h {
- mux {
- groups = "cec_ao_a_h";
- function = "cec_ao_a_h";
- bias-disable;
- };
- };
-
- cec_ao_b_h_pins: cec_ao_b_h {
- mux {
- groups = "cec_ao_b_h";
- function = "cec_ao_b_h";
- bias-disable;
- };
- };
-
- emmc_ctrl_pins: emmc-ctrl {
- mux-0 {
- groups = "emmc_cmd";
- function = "emmc";
- bias-pull-up;
- drive-strength-microamp = <4000>;
- };
-
- mux-1 {
- groups = "emmc_clk";
- function = "emmc";
- bias-disable;
- drive-strength-microamp = <4000>;
- };
- };
-
- emmc_data_4b_pins: emmc-data-4b {
- mux-0 {
- groups = "emmc_nand_d0",
- "emmc_nand_d1",
- "emmc_nand_d2",
- "emmc_nand_d3";
- function = "emmc";
- bias-pull-up;
- drive-strength-microamp = <4000>;
- };
- };
-
- emmc_data_8b_pins: emmc-data-8b {
- mux-0 {
- groups = "emmc_nand_d0",
- "emmc_nand_d1",
- "emmc_nand_d2",
- "emmc_nand_d3",
- "emmc_nand_d4",
- "emmc_nand_d5",
- "emmc_nand_d6",
- "emmc_nand_d7";
- function = "emmc";
- bias-pull-up;
- drive-strength-microamp = <4000>;
- };
- };
-
- emmc_ds_pins: emmc-ds {
- mux {
- groups = "emmc_nand_ds";
- function = "emmc";
- bias-pull-down;
- drive-strength-microamp = <4000>;
- };
- };
-
- emmc_clk_gate_pins: emmc_clk_gate {
- mux {
- groups = "BOOT_8";
- function = "gpio_periphs";
- bias-pull-down;
- drive-strength-microamp = <4000>;
- };
- };
-
- hdmitx_ddc_pins: hdmitx_ddc {
- mux {
- groups = "hdmitx_sda",
- "hdmitx_sck";
- function = "hdmitx";
- bias-disable;
- drive-strength-microamp = <4000>;
- };
- };
-
- hdmitx_hpd_pins: hdmitx_hpd {
- mux {
- groups = "hdmitx_hpd_in";
- function = "hdmitx";
- bias-disable;
- };
- };
-
-
- i2c0_sda_c_pins: i2c0-sda-c {
- mux {
- groups = "i2c0_sda_c";
- function = "i2c0";
- bias-disable;
- drive-strength-microamp = <3000>;
-
- };
- };
-
- i2c0_sck_c_pins: i2c0-sck-c {
- mux {
- groups = "i2c0_sck_c";
- function = "i2c0";
- bias-disable;
- drive-strength-microamp = <3000>;
- };
- };
-
- i2c0_sda_z0_pins: i2c0-sda-z0 {
- mux {
- groups = "i2c0_sda_z0";
- function = "i2c0";
- bias-disable;
- drive-strength-microamp = <3000>;
- };
- };
-
- i2c0_sck_z1_pins: i2c0-sck-z1 {
- mux {
- groups = "i2c0_sck_z1";
- function = "i2c0";
- bias-disable;
- drive-strength-microamp = <3000>;
- };
- };
-
- i2c0_sda_z7_pins: i2c0-sda-z7 {
- mux {
- groups = "i2c0_sda_z7";
- function = "i2c0";
- bias-disable;
- drive-strength-microamp = <3000>;
- };
- };
-
- i2c0_sda_z8_pins: i2c0-sda-z8 {
- mux {
- groups = "i2c0_sda_z8";
- function = "i2c0";
- bias-disable;
- drive-strength-microamp = <3000>;
- };
- };
-
- i2c1_sda_x_pins: i2c1-sda-x {
- mux {
- groups = "i2c1_sda_x";
- function = "i2c1";
- bias-disable;
- drive-strength-microamp = <3000>;
- };
- };
-
- i2c1_sck_x_pins: i2c1-sck-x {
- mux {
- groups = "i2c1_sck_x";
- function = "i2c1";
- bias-disable;
- drive-strength-microamp = <3000>;
- };
- };
-
- i2c1_sda_h2_pins: i2c1-sda-h2 {
- mux {
- groups = "i2c1_sda_h2";
- function = "i2c1";
- bias-disable;
- drive-strength-microamp = <3000>;
- };
- };
-
- i2c1_sck_h3_pins: i2c1-sck-h3 {
- mux {
- groups = "i2c1_sck_h3";
- function = "i2c1";
- bias-disable;
- drive-strength-microamp = <3000>;
- };
- };
-
- i2c1_sda_h6_pins: i2c1-sda-h6 {
- mux {
- groups = "i2c1_sda_h6";
- function = "i2c1";
- bias-disable;
- drive-strength-microamp = <3000>;
- };
- };
-
- i2c1_sck_h7_pins: i2c1-sck-h7 {
- mux {
- groups = "i2c1_sck_h7";
- function = "i2c1";
- bias-disable;
- drive-strength-microamp = <3000>;
- };
- };
-
- i2c2_sda_x_pins: i2c2-sda-x {
- mux {
- groups = "i2c2_sda_x";
- function = "i2c2";
- bias-disable;
- drive-strength-microamp = <3000>;
- };
- };
-
- i2c2_sck_x_pins: i2c2-sck-x {
- mux {
- groups = "i2c2_sck_x";
- function = "i2c2";
- bias-disable;
- drive-strength-microamp = <3000>;
- };
- };
-
- i2c2_sda_z_pins: i2c2-sda-z {
- mux {
- groups = "i2c2_sda_z";
- function = "i2c2";
- bias-disable;
- drive-strength-microamp = <3000>;
- };
- };
-
- i2c2_sck_z_pins: i2c2-sck-z {
- mux {
- groups = "i2c2_sck_z";
- function = "i2c2";
- bias-disable;
- drive-strength-microamp = <3000>;
- };
- };
-
- i2c3_sda_h_pins: i2c3-sda-h {
- mux {
- groups = "i2c3_sda_h";
- function = "i2c3";
- bias-disable;
- drive-strength-microamp = <3000>;
- };
- };
-
- i2c3_sck_h_pins: i2c3-sck-h {
- mux {
- groups = "i2c3_sck_h";
- function = "i2c3";
- bias-disable;
- drive-strength-microamp = <3000>;
- };
- };
-
- i2c3_sda_a_pins: i2c3-sda-a {
- mux {
- groups = "i2c3_sda_a";
- function = "i2c3";
- bias-disable;
- drive-strength-microamp = <3000>;
- };
- };
-
- i2c3_sck_a_pins: i2c3-sck-a {
- mux {
- groups = "i2c3_sck_a";
- function = "i2c3";
- bias-disable;
- drive-strength-microamp = <3000>;
- };
- };
-
- mclk0_a_pins: mclk0-a {
- mux {
- groups = "mclk0_a";
- function = "mclk0";
- bias-disable;
- drive-strength-microamp = <3000>;
- };
- };
-
- mclk1_a_pins: mclk1-a {
- mux {
- groups = "mclk1_a";
- function = "mclk1";
- bias-disable;
- drive-strength-microamp = <3000>;
- };
- };
-
- mclk1_x_pins: mclk1-x {
- mux {
- groups = "mclk1_x";
- function = "mclk1";
- bias-disable;
- drive-strength-microamp = <3000>;
- };
- };
-
- mclk1_z_pins: mclk1-z {
- mux {
- groups = "mclk1_z";
- function = "mclk1";
- bias-disable;
- drive-strength-microamp = <3000>;
- };
- };
-
- nor_pins: nor {
- mux {
- groups = "nor_d",
- "nor_q",
- "nor_c",
- "nor_cs";
- function = "nor";
- bias-disable;
- };
- };
-
- pdm_din0_a_pins: pdm-din0-a {
- mux {
- groups = "pdm_din0_a";
- function = "pdm";
- bias-disable;
- };
- };
-
- pdm_din0_c_pins: pdm-din0-c {
- mux {
- groups = "pdm_din0_c";
- function = "pdm";
- bias-disable;
- };
- };
-
- pdm_din0_x_pins: pdm-din0-x {
- mux {
- groups = "pdm_din0_x";
- function = "pdm";
- bias-disable;
- };
- };
-
- pdm_din0_z_pins: pdm-din0-z {
- mux {
- groups = "pdm_din0_z";
- function = "pdm";
- bias-disable;
- };
- };
-
- pdm_din1_a_pins: pdm-din1-a {
- mux {
- groups = "pdm_din1_a";
- function = "pdm";
- bias-disable;
- };
- };
-
- pdm_din1_c_pins: pdm-din1-c {
- mux {
- groups = "pdm_din1_c";
- function = "pdm";
- bias-disable;
- };
- };
-
- pdm_din1_x_pins: pdm-din1-x {
- mux {
- groups = "pdm_din1_x";
- function = "pdm";
- bias-disable;
- };
- };
-
- pdm_din1_z_pins: pdm-din1-z {
- mux {
- groups = "pdm_din1_z";
- function = "pdm";
- bias-disable;
- };
- };
-
- pdm_din2_a_pins: pdm-din2-a {
- mux {
- groups = "pdm_din2_a";
- function = "pdm";
- bias-disable;
- };
- };
-
- pdm_din2_c_pins: pdm-din2-c {
- mux {
- groups = "pdm_din2_c";
- function = "pdm";
- bias-disable;
- };
- };
-
- pdm_din2_x_pins: pdm-din2-x {
- mux {
- groups = "pdm_din2_x";
- function = "pdm";
- bias-disable;
- };
- };
-
- pdm_din2_z_pins: pdm-din2-z {
- mux {
- groups = "pdm_din2_z";
- function = "pdm";
- bias-disable;
- };
- };
-
- pdm_din3_a_pins: pdm-din3-a {
- mux {
- groups = "pdm_din3_a";
- function = "pdm";
- bias-disable;
- };
- };
-
- pdm_din3_c_pins: pdm-din3-c {
- mux {
- groups = "pdm_din3_c";
- function = "pdm";
- bias-disable;
- };
- };
-
- pdm_din3_x_pins: pdm-din3-x {
- mux {
- groups = "pdm_din3_x";
- function = "pdm";
- bias-disable;
- };
- };
-
- pdm_din3_z_pins: pdm-din3-z {
- mux {
- groups = "pdm_din3_z";
- function = "pdm";
- bias-disable;
- };
- };
-
- pdm_dclk_a_pins: pdm-dclk-a {
- mux {
- groups = "pdm_dclk_a";
- function = "pdm";
- bias-disable;
- drive-strength-microamp = <500>;
- };
- };
-
- pdm_dclk_c_pins: pdm-dclk-c {
- mux {
- groups = "pdm_dclk_c";
- function = "pdm";
- bias-disable;
- drive-strength-microamp = <500>;
- };
- };
-
- pdm_dclk_x_pins: pdm-dclk-x {
- mux {
- groups = "pdm_dclk_x";
- function = "pdm";
- bias-disable;
- drive-strength-microamp = <500>;
- };
- };
-
- pdm_dclk_z_pins: pdm-dclk-z {
- mux {
- groups = "pdm_dclk_z";
- function = "pdm";
- bias-disable;
- drive-strength-microamp = <500>;
- };
- };
-
- pwm_a_pins: pwm-a {
- mux {
- groups = "pwm_a";
- function = "pwm_a";
- bias-disable;
- };
- };
-
- pwm_b_x7_pins: pwm-b-x7 {
- mux {
- groups = "pwm_b_x7";
- function = "pwm_b";
- bias-disable;
- };
- };
-
- pwm_b_x19_pins: pwm-b-x19 {
- mux {
- groups = "pwm_b_x19";
- function = "pwm_b";
- bias-disable;
- };
- };
-
- pwm_c_c_pins: pwm-c-c {
- mux {
- groups = "pwm_c_c";
- function = "pwm_c";
- bias-disable;
- };
- };
-
- pwm_c_x5_pins: pwm-c-x5 {
- mux {
- groups = "pwm_c_x5";
- function = "pwm_c";
- bias-disable;
- };
- };
-
- pwm_c_x8_pins: pwm-c-x8 {
- mux {
- groups = "pwm_c_x8";
- function = "pwm_c";
- bias-disable;
- };
- };
-
- pwm_d_x3_pins: pwm-d-x3 {
- mux {
- groups = "pwm_d_x3";
- function = "pwm_d";
- bias-disable;
- };
- };
-
- pwm_d_x6_pins: pwm-d-x6 {
- mux {
- groups = "pwm_d_x6";
- function = "pwm_d";
- bias-disable;
- };
- };
-
- pwm_e_pins: pwm-e {
- mux {
- groups = "pwm_e";
- function = "pwm_e";
- bias-disable;
- };
- };
-
- pwm_f_z_pins: pwm-f-z {
- mux {
- groups = "pwm_f_z";
- function = "pwm_f";
- bias-disable;
- };
- };
-
- pwm_f_a_pins: pwm-f-a {
- mux {
- groups = "pwm_f_a";
- function = "pwm_f";
- bias-disable;
- };
- };
-
- pwm_f_x_pins: pwm-f-x {
- mux {
- groups = "pwm_f_x";
- function = "pwm_f";
- bias-disable;
- };
- };
-
- pwm_f_h_pins: pwm-f-h {
- mux {
- groups = "pwm_f_h";
- function = "pwm_f";
- bias-disable;
- };
- };
-
- sdcard_c_pins: sdcard_c {
- mux-0 {
- groups = "sdcard_d0_c",
- "sdcard_d1_c",
- "sdcard_d2_c",
- "sdcard_d3_c",
- "sdcard_cmd_c";
- function = "sdcard";
- bias-pull-up;
- drive-strength-microamp = <4000>;
- };
-
- mux-1 {
- groups = "sdcard_clk_c";
- function = "sdcard";
- bias-disable;
- drive-strength-microamp = <4000>;
- };
- };
-
- sdcard_clk_gate_c_pins: sdcard_clk_gate_c {
- mux {
- groups = "GPIOC_4";
- function = "gpio_periphs";
- bias-pull-down;
- drive-strength-microamp = <4000>;
- };
- };
-
- sdcard_z_pins: sdcard_z {
- mux-0 {
- groups = "sdcard_d0_z",
- "sdcard_d1_z",
- "sdcard_d2_z",
- "sdcard_d3_z",
- "sdcard_cmd_z";
- function = "sdcard";
- bias-pull-up;
- drive-strength-microamp = <4000>;
- };
-
- mux-1 {
- groups = "sdcard_clk_z";
- function = "sdcard";
- bias-disable;
- drive-strength-microamp = <4000>;
- };
- };
-
- sdcard_clk_gate_z_pins: sdcard_clk_gate_z {
- mux {
- groups = "GPIOZ_6";
- function = "gpio_periphs";
- bias-pull-down;
- drive-strength-microamp = <4000>;
- };
- };
-
- sdio_pins: sdio {
- mux {
- groups = "sdio_d0",
- "sdio_d1",
- "sdio_d2",
- "sdio_d3",
- "sdio_clk",
- "sdio_cmd";
- function = "sdio";
- bias-disable;
- drive-strength-microamp = <4000>;
- };
- };
-
- sdio_clk_gate_pins: sdio_clk_gate {
- mux {
- groups = "GPIOX_4";
- function = "gpio_periphs";
- bias-pull-down;
- drive-strength-microamp = <4000>;
- };
- };
-
- spdif_in_a10_pins: spdif-in-a10 {
- mux {
- groups = "spdif_in_a10";
- function = "spdif_in";
- bias-disable;
- };
- };
-
- spdif_in_a12_pins: spdif-in-a12 {
- mux {
- groups = "spdif_in_a12";
- function = "spdif_in";
- bias-disable;
- };
- };
-
- spdif_in_h_pins: spdif-in-h {
- mux {
- groups = "spdif_in_h";
- function = "spdif_in";
- bias-disable;
- };
- };
-
- spdif_out_h_pins: spdif-out-h {
- mux {
- groups = "spdif_out_h";
- function = "spdif_out";
- drive-strength-microamp = <500>;
- bias-disable;
- };
- };
-
- spdif_out_a11_pins: spdif-out-a11 {
- mux {
- groups = "spdif_out_a11";
- function = "spdif_out";
- drive-strength-microamp = <500>;
- bias-disable;
- };
- };
-
- spdif_out_a13_pins: spdif-out-a13 {
- mux {
- groups = "spdif_out_a13";
- function = "spdif_out";
- drive-strength-microamp = <500>;
- bias-disable;
- };
- };
-
- spicc0_x_pins: spicc0-x {
- mux {
- groups = "spi0_mosi_x",
- "spi0_miso_x",
- "spi0_clk_x";
- function = "spi0";
- drive-strength-microamp = <4000>;
- bias-disable;
- };
- };
-
- spicc0_ss0_x_pins: spicc0-ss0-x {
- mux {
- groups = "spi0_ss0_x";
- function = "spi0";
- drive-strength-microamp = <4000>;
- bias-disable;
- };
- };
-
- spicc0_c_pins: spicc0-c {
- mux {
- groups = "spi0_mosi_c",
- "spi0_miso_c",
- "spi0_ss0_c",
- "spi0_clk_c";
- function = "spi0";
- drive-strength-microamp = <4000>;
- bias-disable;
- };
- };
-
- spicc1_pins: spicc1 {
- mux {
- groups = "spi1_mosi",
- "spi1_miso",
- "spi1_clk";
- function = "spi1";
- drive-strength-microamp = <4000>;
- };
- };
-
- spicc1_ss0_pins: spicc1-ss0 {
- mux {
- groups = "spi1_ss0";
- function = "spi1";
- drive-strength-microamp = <4000>;
- bias-disable;
- };
- };
-
- tdm_a_din0_pins: tdm-a-din0 {
- mux {
- groups = "tdm_a_din0";
- function = "tdm_a";
- bias-disable;
- };
- };
-
-
- tdm_a_din1_pins: tdm-a-din1 {
- mux {
- groups = "tdm_a_din1";
- function = "tdm_a";
- bias-disable;
- };
- };
-
- tdm_a_dout0_pins: tdm-a-dout0 {
- mux {
- groups = "tdm_a_dout0";
- function = "tdm_a";
- bias-disable;
- drive-strength-microamp = <3000>;
- };
- };
-
- tdm_a_dout1_pins: tdm-a-dout1 {
- mux {
- groups = "tdm_a_dout1";
- function = "tdm_a";
- bias-disable;
- drive-strength-microamp = <3000>;
- };
- };
-
- tdm_a_fs_pins: tdm-a-fs {
- mux {
- groups = "tdm_a_fs";
- function = "tdm_a";
- bias-disable;
- drive-strength-microamp = <3000>;
- };
- };
-
- tdm_a_sclk_pins: tdm-a-sclk {
- mux {
- groups = "tdm_a_sclk";
- function = "tdm_a";
- bias-disable;
- drive-strength-microamp = <3000>;
- };
- };
-
- tdm_a_slv_fs_pins: tdm-a-slv-fs {
- mux {
- groups = "tdm_a_slv_fs";
- function = "tdm_a";
- bias-disable;
- };
- };
-
-
- tdm_a_slv_sclk_pins: tdm-a-slv-sclk {
- mux {
- groups = "tdm_a_slv_sclk";
- function = "tdm_a";
- bias-disable;
- };
- };
-
- tdm_b_din0_pins: tdm-b-din0 {
- mux {
- groups = "tdm_b_din0";
- function = "tdm_b";
- bias-disable;
- };
- };
-
- tdm_b_din1_pins: tdm-b-din1 {
- mux {
- groups = "tdm_b_din1";
- function = "tdm_b";
- bias-disable;
- };
- };
-
- tdm_b_din2_pins: tdm-b-din2 {
- mux {
- groups = "tdm_b_din2";
- function = "tdm_b";
- bias-disable;
- };
- };
-
- tdm_b_din3_a_pins: tdm-b-din3-a {
- mux {
- groups = "tdm_b_din3_a";
- function = "tdm_b";
- bias-disable;
- };
- };
-
- tdm_b_din3_h_pins: tdm-b-din3-h {
- mux {
- groups = "tdm_b_din3_h";
- function = "tdm_b";
- bias-disable;
- };
- };
-
- tdm_b_dout0_pins: tdm-b-dout0 {
- mux {
- groups = "tdm_b_dout0";
- function = "tdm_b";
- bias-disable;
- drive-strength-microamp = <3000>;
- };
- };
-
- tdm_b_dout1_pins: tdm-b-dout1 {
- mux {
- groups = "tdm_b_dout1";
- function = "tdm_b";
- bias-disable;
- drive-strength-microamp = <3000>;
- };
- };
-
- tdm_b_dout2_pins: tdm-b-dout2 {
- mux {
- groups = "tdm_b_dout2";
- function = "tdm_b";
- bias-disable;
- drive-strength-microamp = <3000>;
- };
- };
-
- tdm_b_dout3_a_pins: tdm-b-dout3-a {
- mux {
- groups = "tdm_b_dout3_a";
- function = "tdm_b";
- bias-disable;
- drive-strength-microamp = <3000>;
- };
- };
-
- tdm_b_dout3_h_pins: tdm-b-dout3-h {
- mux {
- groups = "tdm_b_dout3_h";
- function = "tdm_b";
- bias-disable;
- drive-strength-microamp = <3000>;
- };
- };
-
- tdm_b_fs_pins: tdm-b-fs {
- mux {
- groups = "tdm_b_fs";
- function = "tdm_b";
- bias-disable;
- drive-strength-microamp = <3000>;
- };
- };
-
- tdm_b_sclk_pins: tdm-b-sclk {
- mux {
- groups = "tdm_b_sclk";
- function = "tdm_b";
- bias-disable;
- drive-strength-microamp = <3000>;
- };
- };
-
- tdm_b_slv_fs_pins: tdm-b-slv-fs {
- mux {
- groups = "tdm_b_slv_fs";
- function = "tdm_b";
- bias-disable;
- };
- };
-
- tdm_b_slv_sclk_pins: tdm-b-slv-sclk {
- mux {
- groups = "tdm_b_slv_sclk";
- function = "tdm_b";
- bias-disable;
- };
- };
-
- tdm_c_din0_a_pins: tdm-c-din0-a {
- mux {
- groups = "tdm_c_din0_a";
- function = "tdm_c";
- bias-disable;
- };
- };
-
- tdm_c_din0_z_pins: tdm-c-din0-z {
- mux {
- groups = "tdm_c_din0_z";
- function = "tdm_c";
- bias-disable;
- };
- };
-
- tdm_c_din1_a_pins: tdm-c-din1-a {
- mux {
- groups = "tdm_c_din1_a";
- function = "tdm_c";
- bias-disable;
- };
- };
-
- tdm_c_din1_z_pins: tdm-c-din1-z {
- mux {
- groups = "tdm_c_din1_z";
- function = "tdm_c";
- bias-disable;
- };
- };
-
- tdm_c_din2_a_pins: tdm-c-din2-a {
- mux {
- groups = "tdm_c_din2_a";
- function = "tdm_c";
- bias-disable;
- };
- };
-
- eth_leds_pins: eth-leds {
- mux {
- groups = "eth_link_led",
- "eth_act_led";
- function = "eth";
- bias-disable;
- };
- };
-
- eth_pins: eth {
- mux {
- groups = "eth_mdio",
- "eth_mdc",
- "eth_rgmii_rx_clk",
- "eth_rx_dv",
- "eth_rxd0",
- "eth_rxd1",
- "eth_txen",
- "eth_txd0",
- "eth_txd1";
- function = "eth";
- drive-strength-microamp = <4000>;
- bias-disable;
- };
- };
-
- eth_rgmii_pins: eth-rgmii {
- mux {
- groups = "eth_rxd2_rgmii",
- "eth_rxd3_rgmii",
- "eth_rgmii_tx_clk",
- "eth_txd2_rgmii",
- "eth_txd3_rgmii";
- function = "eth";
- drive-strength-microamp = <4000>;
- bias-disable;
- };
- };
-
- tdm_c_din2_z_pins: tdm-c-din2-z {
- mux {
- groups = "tdm_c_din2_z";
- function = "tdm_c";
- bias-disable;
- };
- };
-
- tdm_c_din3_a_pins: tdm-c-din3-a {
- mux {
- groups = "tdm_c_din3_a";
- function = "tdm_c";
- bias-disable;
- };
- };
-
- tdm_c_din3_z_pins: tdm-c-din3-z {
- mux {
- groups = "tdm_c_din3_z";
- function = "tdm_c";
- bias-disable;
- };
- };
-
- tdm_c_dout0_a_pins: tdm-c-dout0-a {
- mux {
- groups = "tdm_c_dout0_a";
- function = "tdm_c";
- bias-disable;
- drive-strength-microamp = <3000>;
- };
- };
-
- tdm_c_dout0_z_pins: tdm-c-dout0-z {
- mux {
- groups = "tdm_c_dout0_z";
- function = "tdm_c";
- bias-disable;
- drive-strength-microamp = <3000>;
- };
- };
-
- tdm_c_dout1_a_pins: tdm-c-dout1-a {
- mux {
- groups = "tdm_c_dout1_a";
- function = "tdm_c";
- bias-disable;
- drive-strength-microamp = <3000>;
- };
- };
-
- tdm_c_dout1_z_pins: tdm-c-dout1-z {
- mux {
- groups = "tdm_c_dout1_z";
- function = "tdm_c";
- bias-disable;
- drive-strength-microamp = <3000>;
- };
- };
-
- tdm_c_dout2_a_pins: tdm-c-dout2-a {
- mux {
- groups = "tdm_c_dout2_a";
- function = "tdm_c";
- bias-disable;
- drive-strength-microamp = <3000>;
- };
- };
-
- tdm_c_dout2_z_pins: tdm-c-dout2-z {
- mux {
- groups = "tdm_c_dout2_z";
- function = "tdm_c";
- bias-disable;
- drive-strength-microamp = <3000>;
- };
- };
-
- tdm_c_dout3_a_pins: tdm-c-dout3-a {
- mux {
- groups = "tdm_c_dout3_a";
- function = "tdm_c";
- bias-disable;
- drive-strength-microamp = <3000>;
- };
- };
-
- tdm_c_dout3_z_pins: tdm-c-dout3-z {
- mux {
- groups = "tdm_c_dout3_z";
- function = "tdm_c";
- bias-disable;
- drive-strength-microamp = <3000>;
- };
- };
-
- tdm_c_fs_a_pins: tdm-c-fs-a {
- mux {
- groups = "tdm_c_fs_a";
- function = "tdm_c";
- bias-disable;
- drive-strength-microamp = <3000>;
- };
- };
-
- tdm_c_fs_z_pins: tdm-c-fs-z {
- mux {
- groups = "tdm_c_fs_z";
- function = "tdm_c";
- bias-disable;
- drive-strength-microamp = <3000>;
- };
- };
-
- tdm_c_sclk_a_pins: tdm-c-sclk-a {
- mux {
- groups = "tdm_c_sclk_a";
- function = "tdm_c";
- bias-disable;
- drive-strength-microamp = <3000>;
- };
- };
-
- tdm_c_sclk_z_pins: tdm-c-sclk-z {
- mux {
- groups = "tdm_c_sclk_z";
- function = "tdm_c";
- bias-disable;
- drive-strength-microamp = <3000>;
- };
- };
-
- tdm_c_slv_fs_a_pins: tdm-c-slv-fs-a {
- mux {
- groups = "tdm_c_slv_fs_a";
- function = "tdm_c";
- bias-disable;
- };
- };
-
- tdm_c_slv_fs_z_pins: tdm-c-slv-fs-z {
- mux {
- groups = "tdm_c_slv_fs_z";
- function = "tdm_c";
- bias-disable;
- };
- };
-
- tdm_c_slv_sclk_a_pins: tdm-c-slv-sclk-a {
- mux {
- groups = "tdm_c_slv_sclk_a";
- function = "tdm_c";
- bias-disable;
- };
- };
-
- tdm_c_slv_sclk_z_pins: tdm-c-slv-sclk-z {
- mux {
- groups = "tdm_c_slv_sclk_z";
- function = "tdm_c";
- bias-disable;
- };
- };
-
- uart_a_pins: uart-a {
- mux {
- groups = "uart_a_tx",
- "uart_a_rx";
- function = "uart_a";
- bias-disable;
- };
- };
-
- uart_a_cts_rts_pins: uart-a-cts-rts {
- mux {
- groups = "uart_a_cts",
- "uart_a_rts";
- function = "uart_a";
- bias-disable;
- };
- };
-
- uart_b_pins: uart-b {
- mux {
- groups = "uart_b_tx",
- "uart_b_rx";
- function = "uart_b";
- bias-disable;
- };
- };
-
- uart_c_pins: uart-c {
- mux {
- groups = "uart_c_tx",
- "uart_c_rx";
- function = "uart_c";
- bias-disable;
- };
- };
-
- uart_c_cts_rts_pins: uart-c-cts-rts {
- mux {
- groups = "uart_c_cts",
- "uart_c_rts";
- function = "uart_c";
- bias-disable;
- };
- };
- };
- };
-
- cpu_temp: temperature-sensor@34800 {
- compatible = "amlogic,g12a-cpu-thermal",
- "amlogic,g12a-thermal";
- reg = <0x0 0x34800 0x0 0x50>;
- interrupts = <GIC_SPI 35 IRQ_TYPE_EDGE_RISING>;
- clocks = <&clkc CLKID_TS>;
- #thermal-sensor-cells = <0>;
- amlogic,ao-secure = <&sec_AO>;
- };
-
- ddr_temp: temperature-sensor@34c00 {
- compatible = "amlogic,g12a-ddr-thermal",
- "amlogic,g12a-thermal";
- reg = <0x0 0x34c00 0x0 0x50>;
- interrupts = <GIC_SPI 36 IRQ_TYPE_EDGE_RISING>;
- clocks = <&clkc CLKID_TS>;
- #thermal-sensor-cells = <0>;
- amlogic,ao-secure = <&sec_AO>;
- };
-
- usb2_phy0: phy@36000 {
- compatible = "amlogic,g12a-usb2-phy";
- reg = <0x0 0x36000 0x0 0x2000>;
- clocks = <&xtal>;
- clock-names = "xtal";
- resets = <&reset RESET_USB_PHY20>;
- reset-names = "phy";
- #phy-cells = <0>;
- };
-
- dmc: bus@38000 {
- compatible = "simple-bus";
- reg = <0x0 0x38000 0x0 0x400>;
- #address-cells = <2>;
- #size-cells = <2>;
- ranges = <0x0 0x0 0x0 0x38000 0x0 0x400>;
-
- canvas: video-lut@48 {
- compatible = "amlogic,canvas";
- reg = <0x0 0x48 0x0 0x14>;
- };
- };
-
- usb2_phy1: phy@3a000 {
- compatible = "amlogic,g12a-usb2-phy";
- reg = <0x0 0x3a000 0x0 0x2000>;
- clocks = <&xtal>;
- clock-names = "xtal";
- resets = <&reset RESET_USB_PHY21>;
- reset-names = "phy";
- #phy-cells = <0>;
- };
-
- hiu: bus@3c000 {
- compatible = "simple-bus";
- reg = <0x0 0x3c000 0x0 0x1400>;
- #address-cells = <2>;
- #size-cells = <2>;
- ranges = <0x0 0x0 0x0 0x3c000 0x0 0x1400>;
-
- hhi: system-controller@0 {
- compatible = "amlogic,meson-gx-hhi-sysctrl",
- "simple-mfd", "syscon";
- reg = <0 0 0 0x400>;
-
- clkc: clock-controller {
- compatible = "amlogic,g12a-clkc";
- #clock-cells = <1>;
- clocks = <&xtal>;
- clock-names = "xtal";
- };
-
- pwrc: power-controller {
- compatible = "amlogic,meson-g12a-pwrc";
- #power-domain-cells = <1>;
- amlogic,ao-sysctrl = <&rti>;
- resets = <&reset RESET_VIU>,
- <&reset RESET_VENC>,
- <&reset RESET_VCBUS>,
- <&reset RESET_BT656>,
- <&reset RESET_RDMA>,
- <&reset RESET_VENCI>,
- <&reset RESET_VENCP>,
- <&reset RESET_VDAC>,
- <&reset RESET_VDI6>,
- <&reset RESET_VENCL>,
- <&reset RESET_VID_LOCK>;
- reset-names = "viu", "venc", "vcbus", "bt656",
- "rdma", "venci", "vencp", "vdac",
- "vdi6", "vencl", "vid_lock";
- clocks = <&clkc CLKID_VPU>,
- <&clkc CLKID_VAPB>;
- clock-names = "vpu", "vapb";
- /*
- * VPU clocking is provided by two identical clock paths
- * VPU_0 and VPU_1 muxed to a single clock by a glitch
- * free mux to safely change frequency while running.
- * Same for VAPB but with a final gate after the glitch free mux.
- */
- assigned-clocks = <&clkc CLKID_VPU_0_SEL>,
- <&clkc CLKID_VPU_0>,
- <&clkc CLKID_VPU>, /* Glitch free mux */
- <&clkc CLKID_VAPB_0_SEL>,
- <&clkc CLKID_VAPB_0>,
- <&clkc CLKID_VAPB_SEL>; /* Glitch free mux */
- assigned-clock-parents = <&clkc CLKID_FCLK_DIV3>,
- <0>, /* Do Nothing */
- <&clkc CLKID_VPU_0>,
- <&clkc CLKID_FCLK_DIV4>,
- <0>, /* Do Nothing */
- <&clkc CLKID_VAPB_0>;
- assigned-clock-rates = <0>, /* Do Nothing */
- <666666666>,
- <0>, /* Do Nothing */
- <0>, /* Do Nothing */
- <250000000>,
- <0>; /* Do Nothing */
- };
- };
- };
-
- usb3_pcie_phy: phy@46000 {
- compatible = "amlogic,g12a-usb3-pcie-phy";
- reg = <0x0 0x46000 0x0 0x2000>;
- clocks = <&clkc CLKID_PCIE_PLL>;
- clock-names = "ref_clk";
- resets = <&reset RESET_PCIE_PHY>;
- reset-names = "phy";
- assigned-clocks = <&clkc CLKID_PCIE_PLL>;
- assigned-clock-rates = <100000000>;
- #phy-cells = <1>;
- };
-
- eth_phy: mdio-multiplexer@4c000 {
- compatible = "amlogic,g12a-mdio-mux";
- reg = <0x0 0x4c000 0x0 0xa4>;
- clocks = <&clkc CLKID_ETH_PHY>,
- <&xtal>,
- <&clkc CLKID_MPLL_50M>;
- clock-names = "pclk", "clkin0", "clkin1";
- mdio-parent-bus = <&mdio0>;
- #address-cells = <1>;
- #size-cells = <0>;
-
- ext_mdio: mdio@0 {
- reg = <0>;
- #address-cells = <1>;
- #size-cells = <0>;
- };
-
- int_mdio: mdio@1 {
- reg = <1>;
- #address-cells = <1>;
- #size-cells = <0>;
-
- internal_ephy: ethernet_phy@8 {
- compatible = "ethernet-phy-id0180.3301",
- "ethernet-phy-ieee802.3-c22";
- interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
- reg = <8>;
- max-speed = <100>;
- };
- };
- };
- };
-
- pmu: pmu@ff638000 {
- reg = <0x0 0xff638000 0x0 0x100>,
- <0x0 0xff638c00 0x0 0x100>;
- interrupts = <GIC_SPI 52 IRQ_TYPE_EDGE_RISING>;
- };
-
- aobus: bus@ff800000 {
- compatible = "simple-bus";
- reg = <0x0 0xff800000 0x0 0x100000>;
- #address-cells = <2>;
- #size-cells = <2>;
- ranges = <0x0 0x0 0x0 0xff800000 0x0 0x100000>;
-
- rti: sys-ctrl@0 {
- compatible = "amlogic,meson-gx-ao-sysctrl",
- "simple-mfd", "syscon";
- reg = <0x0 0x0 0x0 0x100>;
- #address-cells = <2>;
- #size-cells = <2>;
- ranges = <0x0 0x0 0x0 0x0 0x0 0x100>;
-
- clkc_AO: clock-controller {
- compatible = "amlogic,meson-g12a-aoclkc";
- #clock-cells = <1>;
- #reset-cells = <1>;
- clocks = <&xtal>, <&clkc CLKID_CLK81>;
- clock-names = "xtal", "mpeg-clk";
- };
-
- ao_pinctrl: pinctrl@14 {
- compatible = "amlogic,meson-g12a-aobus-pinctrl";
- #address-cells = <2>;
- #size-cells = <2>;
- ranges;
-
- gpio_ao: bank@14 {
- reg = <0x0 0x14 0x0 0x8>,
- <0x0 0x1c 0x0 0x8>,
- <0x0 0x24 0x0 0x14>;
- reg-names = "mux",
- "ds",
- "gpio";
- gpio-controller;
- #gpio-cells = <2>;
- gpio-ranges = <&ao_pinctrl 0 0 15>;
- };
-
- i2c_ao_sck_pins: i2c_ao_sck_pins {
- mux {
- groups = "i2c_ao_sck";
- function = "i2c_ao";
- bias-disable;
- drive-strength-microamp = <3000>;
- };
- };
-
- i2c_ao_sda_pins: i2c_ao_sda {
- mux {
- groups = "i2c_ao_sda";
- function = "i2c_ao";
- bias-disable;
- drive-strength-microamp = <3000>;
- };
- };
-
- i2c_ao_sck_e_pins: i2c_ao_sck_e {
- mux {
- groups = "i2c_ao_sck_e";
- function = "i2c_ao";
- bias-disable;
- drive-strength-microamp = <3000>;
- };
- };
-
- i2c_ao_sda_e_pins: i2c_ao_sda_e {
- mux {
- groups = "i2c_ao_sda_e";
- function = "i2c_ao";
- bias-disable;
- drive-strength-microamp = <3000>;
- };
- };
-
- mclk0_ao_pins: mclk0-ao {
- mux {
- groups = "mclk0_ao";
- function = "mclk0_ao";
- bias-disable;
- drive-strength-microamp = <3000>;
- };
- };
-
- tdm_ao_b_din0_pins: tdm-ao-b-din0 {
- mux {
- groups = "tdm_ao_b_din0";
- function = "tdm_ao_b";
- bias-disable;
- };
- };
-
- spdif_ao_out_pins: spdif-ao-out {
- mux {
- groups = "spdif_ao_out";
- function = "spdif_ao_out";
- drive-strength-microamp = <500>;
- bias-disable;
- };
- };
-
- tdm_ao_b_din1_pins: tdm-ao-b-din1 {
- mux {
- groups = "tdm_ao_b_din1";
- function = "tdm_ao_b";
- bias-disable;
- };
- };
-
- tdm_ao_b_din2_pins: tdm-ao-b-din2 {
- mux {
- groups = "tdm_ao_b_din2";
- function = "tdm_ao_b";
- bias-disable;
- };
- };
-
- tdm_ao_b_dout0_pins: tdm-ao-b-dout0 {
- mux {
- groups = "tdm_ao_b_dout0";
- function = "tdm_ao_b";
- bias-disable;
- drive-strength-microamp = <3000>;
- };
- };
-
- tdm_ao_b_dout1_pins: tdm-ao-b-dout1 {
- mux {
- groups = "tdm_ao_b_dout1";
- function = "tdm_ao_b";
- bias-disable;
- drive-strength-microamp = <3000>;
- };
- };
-
- tdm_ao_b_dout2_pins: tdm-ao-b-dout2 {
- mux {
- groups = "tdm_ao_b_dout2";
- function = "tdm_ao_b";
- bias-disable;
- drive-strength-microamp = <3000>;
- };
- };
-
- tdm_ao_b_fs_pins: tdm-ao-b-fs {
- mux {
- groups = "tdm_ao_b_fs";
- function = "tdm_ao_b";
- bias-disable;
- drive-strength-microamp = <3000>;
- };
- };
-
- tdm_ao_b_sclk_pins: tdm-ao-b-sclk {
- mux {
- groups = "tdm_ao_b_sclk";
- function = "tdm_ao_b";
- bias-disable;
- drive-strength-microamp = <3000>;
- };
- };
-
- tdm_ao_b_slv_fs_pins: tdm-ao-b-slv-fs {
- mux {
- groups = "tdm_ao_b_slv_fs";
- function = "tdm_ao_b";
- bias-disable;
- };
- };
-
- tdm_ao_b_slv_sclk_pins: tdm-ao-b-slv-sclk {
- mux {
- groups = "tdm_ao_b_slv_sclk";
- function = "tdm_ao_b";
- bias-disable;
- };
- };
-
- uart_ao_a_pins: uart-a-ao {
- mux {
- groups = "uart_ao_a_tx",
- "uart_ao_a_rx";
- function = "uart_ao_a";
- bias-disable;
- };
- };
-
- uart_ao_a_cts_rts_pins: uart-ao-a-cts-rts {
- mux {
- groups = "uart_ao_a_cts",
- "uart_ao_a_rts";
- function = "uart_ao_a";
- bias-disable;
- };
- };
-
- uart_ao_b_2_3_pins: uart-ao-b-2-3 {
- mux {
- groups = "uart_ao_b_tx_2",
- "uart_ao_b_rx_3";
- function = "uart_ao_b";
- bias-disable;
- };
- };
-
- uart_ao_b_8_9_pins: uart-ao-b-8-9 {
- mux {
- groups = "uart_ao_b_tx_8",
- "uart_ao_b_rx_9";
- function = "uart_ao_b";
- bias-disable;
- };
- };
-
- uart_ao_b_cts_rts_pins: uart-ao-b-cts-rts {
- mux {
- groups = "uart_ao_b_cts",
- "uart_ao_b_rts";
- function = "uart_ao_b";
- bias-disable;
- };
- };
-
- pwm_a_e_pins: pwm-a-e {
- mux {
- groups = "pwm_a_e";
- function = "pwm_a_e";
- bias-disable;
- };
- };
-
- pwm_ao_a_pins: pwm-ao-a {
- mux {
- groups = "pwm_ao_a";
- function = "pwm_ao_a";
- bias-disable;
- };
- };
-
- pwm_ao_b_pins: pwm-ao-b {
- mux {
- groups = "pwm_ao_b";
- function = "pwm_ao_b";
- bias-disable;
- };
- };
-
- pwm_ao_c_4_pins: pwm-ao-c-4 {
- mux {
- groups = "pwm_ao_c_4";
- function = "pwm_ao_c";
- bias-disable;
- };
- };
-
- pwm_ao_c_6_pins: pwm-ao-c-6 {
- mux {
- groups = "pwm_ao_c_6";
- function = "pwm_ao_c";
- bias-disable;
- };
- };
-
- pwm_ao_d_5_pins: pwm-ao-d-5 {
- mux {
- groups = "pwm_ao_d_5";
- function = "pwm_ao_d";
- bias-disable;
- };
- };
-
- pwm_ao_d_10_pins: pwm-ao-d-10 {
- mux {
- groups = "pwm_ao_d_10";
- function = "pwm_ao_d";
- bias-disable;
- };
- };
-
- pwm_ao_d_e_pins: pwm-ao-d-e {
- mux {
- groups = "pwm_ao_d_e";
- function = "pwm_ao_d";
- };
- };
-
- remote_input_ao_pins: remote-input-ao {
- mux {
- groups = "remote_ao_input";
- function = "remote_ao_input";
- bias-disable;
- };
- };
- };
- };
-
- vrtc: rtc@a8 {
- compatible = "amlogic,meson-vrtc";
- reg = <0x0 0x000a8 0x0 0x4>;
- };
-
- cec_AO: cec@100 {
- compatible = "amlogic,meson-gx-ao-cec";
- reg = <0x0 0x00100 0x0 0x14>;
- interrupts = <GIC_SPI 199 IRQ_TYPE_EDGE_RISING>;
- clocks = <&clkc_AO CLKID_AO_CEC>;
- clock-names = "core";
- status = "disabled";
- };
-
- sec_AO: ao-secure@140 {
- compatible = "amlogic,meson-gx-ao-secure", "syscon";
- reg = <0x0 0x140 0x0 0x140>;
- amlogic,has-chip-id;
- };
-
- cecb_AO: cec@280 {
- compatible = "amlogic,meson-g12a-ao-cec";
- reg = <0x0 0x00280 0x0 0x1c>;
- interrupts = <GIC_SPI 203 IRQ_TYPE_EDGE_RISING>;
- clocks = <&clkc_AO CLKID_AO_CTS_OSCIN>;
- clock-names = "oscin";
- status = "disabled";
- };
-
- pwm_AO_cd: pwm@2000 {
- compatible = "amlogic,meson-g12a-ao-pwm-cd";
- reg = <0x0 0x2000 0x0 0x20>;
- #pwm-cells = <3>;
- status = "disabled";
- };
-
- uart_AO: serial@3000 {
- compatible = "amlogic,meson-gx-uart",
- "amlogic,meson-ao-uart";
- reg = <0x0 0x3000 0x0 0x18>;
- interrupts = <GIC_SPI 193 IRQ_TYPE_EDGE_RISING>;
- clocks = <&xtal>, <&clkc_AO CLKID_AO_UART>, <&xtal>;
- clock-names = "xtal", "pclk", "baud";
- status = "disabled";
- };
-
- uart_AO_B: serial@4000 {
- compatible = "amlogic,meson-gx-uart",
- "amlogic,meson-ao-uart";
- reg = <0x0 0x4000 0x0 0x18>;
- interrupts = <GIC_SPI 197 IRQ_TYPE_EDGE_RISING>;
- clocks = <&xtal>, <&clkc_AO CLKID_AO_UART2>, <&xtal>;
- clock-names = "xtal", "pclk", "baud";
- status = "disabled";
- };
-
- i2c_AO: i2c@5000 {
- compatible = "amlogic,meson-axg-i2c";
- status = "disabled";
- reg = <0x0 0x05000 0x0 0x20>;
- interrupts = <GIC_SPI 195 IRQ_TYPE_EDGE_RISING>;
- #address-cells = <1>;
- #size-cells = <0>;
- clocks = <&clkc CLKID_I2C>;
- };
-
- pwm_AO_ab: pwm@7000 {
- compatible = "amlogic,meson-g12a-ao-pwm-ab";
- reg = <0x0 0x7000 0x0 0x20>;
- #pwm-cells = <3>;
- status = "disabled";
- };
-
- ir: ir@8000 {
- compatible = "amlogic,meson-gxbb-ir";
- reg = <0x0 0x8000 0x0 0x20>;
- interrupts = <GIC_SPI 196 IRQ_TYPE_EDGE_RISING>;
- status = "disabled";
- };
-
- saradc: adc@9000 {
- compatible = "amlogic,meson-g12a-saradc",
- "amlogic,meson-saradc";
- reg = <0x0 0x9000 0x0 0x48>;
- #io-channel-cells = <1>;
- interrupts = <GIC_SPI 200 IRQ_TYPE_EDGE_RISING>;
- clocks = <&xtal>,
- <&clkc_AO CLKID_AO_SAR_ADC>,
- <&clkc_AO CLKID_AO_SAR_ADC_CLK>,
- <&clkc_AO CLKID_AO_SAR_ADC_SEL>;
- clock-names = "clkin", "core", "adc_clk", "adc_sel";
- status = "disabled";
- };
- };
-
- vdec: video-decoder@ff620000 {
- compatible = "amlogic,g12a-vdec";
- reg = <0x0 0xff620000 0x0 0x10000>,
- <0x0 0xffd0e180 0x0 0xe4>;
- reg-names = "dos", "esparser";
- interrupts = <GIC_SPI 44 IRQ_TYPE_EDGE_RISING>,
- <GIC_SPI 32 IRQ_TYPE_EDGE_RISING>;
- interrupt-names = "vdec", "esparser";
-
- amlogic,ao-sysctrl = <&rti>;
- amlogic,canvas = <&canvas>;
-
- clocks = <&clkc CLKID_PARSER>,
- <&clkc CLKID_DOS>,
- <&clkc CLKID_VDEC_1>,
- <&clkc CLKID_VDEC_HEVC>,
- <&clkc CLKID_VDEC_HEVCF>;
- clock-names = "dos_parser", "dos", "vdec_1",
- "vdec_hevc", "vdec_hevcf";
- resets = <&reset RESET_PARSER>;
- reset-names = "esparser";
- };
-
- vpu: vpu@ff900000 {
- compatible = "amlogic,meson-g12a-vpu";
- reg = <0x0 0xff900000 0x0 0x100000>,
- <0x0 0xff63c000 0x0 0x1000>;
- reg-names = "vpu", "hhi";
- interrupts = <GIC_SPI 3 IRQ_TYPE_EDGE_RISING>;
- #address-cells = <1>;
- #size-cells = <0>;
- amlogic,canvas = <&canvas>;
-
- /* CVBS VDAC output port */
- cvbs_vdac_port: port@0 {
- reg = <0>;
- };
-
- /* HDMI-TX output port */
- hdmi_tx_port: port@1 {
- reg = <1>;
-
- hdmi_tx_out: endpoint {
- remote-endpoint = <&hdmi_tx_in>;
- };
- };
- };
-
- gic: interrupt-controller@ffc01000 {
- compatible = "arm,gic-400";
- reg = <0x0 0xffc01000 0 0x1000>,
- <0x0 0xffc02000 0 0x2000>,
- <0x0 0xffc04000 0 0x2000>,
- <0x0 0xffc06000 0 0x2000>;
- interrupt-controller;
- interrupts = <GIC_PPI 9
- (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_HIGH)>;
- #interrupt-cells = <3>;
- #address-cells = <0>;
- };
-
- cbus: bus@ffd00000 {
- compatible = "simple-bus";
- reg = <0x0 0xffd00000 0x0 0x100000>;
- #address-cells = <2>;
- #size-cells = <2>;
- ranges = <0x0 0x0 0x0 0xffd00000 0x0 0x100000>;
-
- reset: reset-controller@1004 {
- compatible = "amlogic,meson-axg-reset";
- reg = <0x0 0x1004 0x0 0x9c>;
- #reset-cells = <1>;
- };
-
- gpio_intc: interrupt-controller@f080 {
- compatible = "amlogic,meson-g12a-gpio-intc",
- "amlogic,meson-gpio-intc";
- reg = <0x0 0xf080 0x0 0x10>;
- interrupt-controller;
- #interrupt-cells = <2>;
- amlogic,channel-interrupts = <64 65 66 67 68 69 70 71>;
- };
-
- watchdog: watchdog@f0d0 {
- compatible = "amlogic,meson-gxbb-wdt";
- reg = <0x0 0xf0d0 0x0 0x10>;
- clocks = <&xtal>;
- };
-
- spicc0: spi@13000 {
- compatible = "amlogic,meson-g12a-spicc";
- reg = <0x0 0x13000 0x0 0x44>;
- interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&clkc CLKID_SPICC0>,
- <&clkc CLKID_SPICC0_SCLK>;
- clock-names = "core", "pclk";
- #address-cells = <1>;
- #size-cells = <0>;
- status = "disabled";
- };
-
- spicc1: spi@15000 {
- compatible = "amlogic,meson-g12a-spicc";
- reg = <0x0 0x15000 0x0 0x44>;
- interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&clkc CLKID_SPICC1>,
- <&clkc CLKID_SPICC1_SCLK>;
- clock-names = "core", "pclk";
- #address-cells = <1>;
- #size-cells = <0>;
- status = "disabled";
- };
-
- spifc: spi@14000 {
- compatible = "amlogic,meson-gxbb-spifc";
- status = "disabled";
- reg = <0x0 0x14000 0x0 0x80>;
- #address-cells = <1>;
- #size-cells = <0>;
- clocks = <&clkc CLKID_CLK81>;
- };
-
- pwm_ef: pwm@19000 {
- compatible = "amlogic,meson-g12a-ee-pwm";
- reg = <0x0 0x19000 0x0 0x20>;
- #pwm-cells = <3>;
- status = "disabled";
- };
-
- pwm_cd: pwm@1a000 {
- compatible = "amlogic,meson-g12a-ee-pwm";
- reg = <0x0 0x1a000 0x0 0x20>;
- #pwm-cells = <3>;
- status = "disabled";
- };
-
- pwm_ab: pwm@1b000 {
- compatible = "amlogic,meson-g12a-ee-pwm";
- reg = <0x0 0x1b000 0x0 0x20>;
- #pwm-cells = <3>;
- status = "disabled";
- };
-
- i2c3: i2c@1c000 {
- compatible = "amlogic,meson-axg-i2c";
- status = "disabled";
- reg = <0x0 0x1c000 0x0 0x20>;
- interrupts = <GIC_SPI 39 IRQ_TYPE_EDGE_RISING>;
- #address-cells = <1>;
- #size-cells = <0>;
- clocks = <&clkc CLKID_I2C>;
- };
-
- i2c2: i2c@1d000 {
- compatible = "amlogic,meson-axg-i2c";
- status = "disabled";
- reg = <0x0 0x1d000 0x0 0x20>;
- interrupts = <GIC_SPI 215 IRQ_TYPE_EDGE_RISING>;
- #address-cells = <1>;
- #size-cells = <0>;
- clocks = <&clkc CLKID_I2C>;
- };
-
- i2c1: i2c@1e000 {
- compatible = "amlogic,meson-axg-i2c";
- status = "disabled";
- reg = <0x0 0x1e000 0x0 0x20>;
- interrupts = <GIC_SPI 214 IRQ_TYPE_EDGE_RISING>;
- #address-cells = <1>;
- #size-cells = <0>;
- clocks = <&clkc CLKID_I2C>;
- };
-
- i2c0: i2c@1f000 {
- compatible = "amlogic,meson-axg-i2c";
- status = "disabled";
- reg = <0x0 0x1f000 0x0 0x20>;
- interrupts = <GIC_SPI 21 IRQ_TYPE_EDGE_RISING>;
- #address-cells = <1>;
- #size-cells = <0>;
- clocks = <&clkc CLKID_I2C>;
- };
-
- clk_msr: clock-measure@18000 {
- compatible = "amlogic,meson-g12a-clk-measure";
- reg = <0x0 0x18000 0x0 0x10>;
- };
-
- uart_C: serial@22000 {
- compatible = "amlogic,meson-gx-uart";
- reg = <0x0 0x22000 0x0 0x18>;
- interrupts = <GIC_SPI 93 IRQ_TYPE_EDGE_RISING>;
- clocks = <&xtal>, <&clkc CLKID_UART2>, <&xtal>;
- clock-names = "xtal", "pclk", "baud";
- status = "disabled";
- };
-
- uart_B: serial@23000 {
- compatible = "amlogic,meson-gx-uart";
- reg = <0x0 0x23000 0x0 0x18>;
- interrupts = <GIC_SPI 75 IRQ_TYPE_EDGE_RISING>;
- clocks = <&xtal>, <&clkc CLKID_UART1>, <&xtal>;
- clock-names = "xtal", "pclk", "baud";
- status = "disabled";
- };
-
- uart_A: serial@24000 {
- compatible = "amlogic,meson-gx-uart";
- reg = <0x0 0x24000 0x0 0x18>;
- interrupts = <GIC_SPI 26 IRQ_TYPE_EDGE_RISING>;
- clocks = <&xtal>, <&clkc CLKID_UART0>, <&xtal>;
- clock-names = "xtal", "pclk", "baud";
- status = "disabled";
- fifo-size = <128>;
- };
- };
-
- sd_emmc_a: sd@ffe03000 {
- compatible = "amlogic,meson-axg-mmc";
- reg = <0x0 0xffe03000 0x0 0x800>;
- interrupts = <GIC_SPI 189 IRQ_TYPE_EDGE_RISING>;
- status = "disabled";
- clocks = <&clkc CLKID_SD_EMMC_A>,
- <&clkc CLKID_SD_EMMC_A_CLK0>,
- <&clkc CLKID_FCLK_DIV2>;
- clock-names = "core", "clkin0", "clkin1";
- resets = <&reset RESET_SD_EMMC_A>;
- };
-
- sd_emmc_b: sd@ffe05000 {
- compatible = "amlogic,meson-axg-mmc";
- reg = <0x0 0xffe05000 0x0 0x800>;
- interrupts = <GIC_SPI 190 IRQ_TYPE_EDGE_RISING>;
- status = "disabled";
- clocks = <&clkc CLKID_SD_EMMC_B>,
- <&clkc CLKID_SD_EMMC_B_CLK0>,
- <&clkc CLKID_FCLK_DIV2>;
- clock-names = "core", "clkin0", "clkin1";
- resets = <&reset RESET_SD_EMMC_B>;
- };
-
- sd_emmc_c: mmc@ffe07000 {
- compatible = "amlogic,meson-axg-mmc";
- reg = <0x0 0xffe07000 0x0 0x800>;
- interrupts = <GIC_SPI 191 IRQ_TYPE_EDGE_RISING>;
- status = "disabled";
- clocks = <&clkc CLKID_SD_EMMC_C>,
- <&clkc CLKID_SD_EMMC_C_CLK0>,
- <&clkc CLKID_FCLK_DIV2>;
- clock-names = "core", "clkin0", "clkin1";
- resets = <&reset RESET_SD_EMMC_C>;
- };
-
- usb: usb@ffe09000 {
- status = "disabled";
- compatible = "amlogic,meson-g12a-usb-ctrl";
- reg = <0x0 0xffe09000 0x0 0xa0>;
- interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
- #address-cells = <2>;
- #size-cells = <2>;
- ranges;
-
- clocks = <&clkc CLKID_USB>;
- resets = <&reset RESET_USB>;
-
- dr_mode = "otg";
-
- phys = <&usb2_phy0>, <&usb2_phy1>,
- <&usb3_pcie_phy PHY_TYPE_USB3>;
- phy-names = "usb2-phy0", "usb2-phy1", "usb3-phy0";
-
- dwc2: usb@ff400000 {
- compatible = "amlogic,meson-g12a-usb", "snps,dwc2";
- reg = <0x0 0xff400000 0x0 0x40000>;
- interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&clkc CLKID_USB1_DDR_BRIDGE>;
- clock-names = "otg";
- phys = <&usb2_phy1>;
- phy-names = "usb2-phy";
- dr_mode = "peripheral";
- g-rx-fifo-size = <192>;
- g-np-tx-fifo-size = <128>;
- g-tx-fifo-size = <128 128 16 16 16>;
- };
-
- dwc3: usb@ff500000 {
- compatible = "snps,dwc3";
- reg = <0x0 0xff500000 0x0 0x100000>;
- interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
- dr_mode = "host";
- snps,dis_u2_susphy_quirk;
- snps,quirk-frame-length-adjustment = <0x20>;
- snps,parkmode-disable-ss-quirk;
- };
- };
-
- mali: gpu@ffe40000 {
- compatible = "amlogic,meson-g12a-mali", "arm,mali-bifrost";
- reg = <0x0 0xffe40000 0x0 0x40000>;
- interrupt-parent = <&gic>;
- interrupts = <GIC_SPI 162 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 161 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 160 IRQ_TYPE_LEVEL_HIGH>;
- interrupt-names = "job", "mmu", "gpu";
- clocks = <&clkc CLKID_MALI>;
- resets = <&reset RESET_DVALIN_CAPB3>, <&reset RESET_DVALIN>;
- operating-points-v2 = <&gpu_opp_table>;
- #cooling-cells = <2>;
- };
- };
-
- thermal-zones {
- cpu_thermal: cpu-thermal {
- polling-delay = <1000>;
- polling-delay-passive = <100>;
- thermal-sensors = <&cpu_temp>;
-
- trips {
- cpu_passive: cpu-passive {
- temperature = <85000>; /* millicelsius */
- hysteresis = <2000>; /* millicelsius */
- type = "passive";
- };
-
- cpu_hot: cpu-hot {
- temperature = <95000>; /* millicelsius */
- hysteresis = <2000>; /* millicelsius */
- type = "hot";
- };
-
- cpu_critical: cpu-critical {
- temperature = <110000>; /* millicelsius */
- hysteresis = <2000>; /* millicelsius */
- type = "critical";
- };
- };
- };
-
- ddr_thermal: ddr-thermal {
- polling-delay = <1000>;
- polling-delay-passive = <100>;
- thermal-sensors = <&ddr_temp>;
-
- trips {
- ddr_passive: ddr-passive {
- temperature = <85000>; /* millicelsius */
- hysteresis = <2000>; /* millicelsius */
- type = "passive";
- };
-
- ddr_critical: ddr-critical {
- temperature = <110000>; /* millicelsius */
- hysteresis = <2000>; /* millicelsius */
- type = "critical";
- };
- };
-
- cooling-maps {
- map {
- trip = <&ddr_passive>;
- cooling-device = <&mali THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
- };
- };
- };
- };
-
- timer {
- compatible = "arm,armv8-timer";
- interrupts = <GIC_PPI 13
- (GIC_CPU_MASK_RAW(0xff) | IRQ_TYPE_LEVEL_LOW)>,
- <GIC_PPI 14
- (GIC_CPU_MASK_RAW(0xff) | IRQ_TYPE_LEVEL_LOW)>,
- <GIC_PPI 11
- (GIC_CPU_MASK_RAW(0xff) | IRQ_TYPE_LEVEL_LOW)>,
- <GIC_PPI 10
- (GIC_CPU_MASK_RAW(0xff) | IRQ_TYPE_LEVEL_LOW)>;
- arm,no-tick-in-suspend;
- };
-
- xtal: xtal-clk {
- compatible = "fixed-clock";
- clock-frequency = <24000000>;
- clock-output-names = "xtal";
- #clock-cells = <0>;
- };
-
-};
diff --git a/arch/arm/dts/meson-g12.dtsi b/arch/arm/dts/meson-g12.dtsi
deleted file mode 100644
index 6a1f4dc..0000000
--- a/arch/arm/dts/meson-g12.dtsi
+++ /dev/null
@@ -1,385 +0,0 @@
-// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
-/*
- * Copyright (c) 2019 BayLibre, SAS
- * Author: Jerome Brunet <jbrunet@baylibre.com>
- */
-
-#include "meson-g12-common.dtsi"
-#include <dt-bindings/clock/axg-audio-clkc.h>
-#include <dt-bindings/power/meson-g12a-power.h>
-#include <dt-bindings/reset/amlogic,meson-axg-audio-arb.h>
-#include <dt-bindings/reset/amlogic,meson-g12a-audio-reset.h>
-
-/ {
- tdmif_a: audio-controller-0 {
- compatible = "amlogic,axg-tdm-iface";
- #sound-dai-cells = <0>;
- sound-name-prefix = "TDM_A";
- clocks = <&clkc_audio AUD_CLKID_MST_A_MCLK>,
- <&clkc_audio AUD_CLKID_MST_A_SCLK>,
- <&clkc_audio AUD_CLKID_MST_A_LRCLK>;
- clock-names = "mclk", "sclk", "lrclk";
- status = "disabled";
- };
-
- tdmif_b: audio-controller-1 {
- compatible = "amlogic,axg-tdm-iface";
- #sound-dai-cells = <0>;
- sound-name-prefix = "TDM_B";
- clocks = <&clkc_audio AUD_CLKID_MST_B_MCLK>,
- <&clkc_audio AUD_CLKID_MST_B_SCLK>,
- <&clkc_audio AUD_CLKID_MST_B_LRCLK>;
- clock-names = "mclk", "sclk", "lrclk";
- status = "disabled";
- };
-
- tdmif_c: audio-controller-2 {
- compatible = "amlogic,axg-tdm-iface";
- #sound-dai-cells = <0>;
- sound-name-prefix = "TDM_C";
- clocks = <&clkc_audio AUD_CLKID_MST_C_MCLK>,
- <&clkc_audio AUD_CLKID_MST_C_SCLK>,
- <&clkc_audio AUD_CLKID_MST_C_LRCLK>;
- clock-names = "mclk", "sclk", "lrclk";
- status = "disabled";
- };
-};
-
-&apb {
- pdm: audio-controller@40000 {
- compatible = "amlogic,g12a-pdm",
- "amlogic,axg-pdm";
- reg = <0x0 0x40000 0x0 0x34>;
- #sound-dai-cells = <0>;
- sound-name-prefix = "PDM";
- clocks = <&clkc_audio AUD_CLKID_PDM>,
- <&clkc_audio AUD_CLKID_PDM_DCLK>,
- <&clkc_audio AUD_CLKID_PDM_SYSCLK>;
- clock-names = "pclk", "dclk", "sysclk";
- resets = <&clkc_audio AUD_RESET_PDM>;
- status = "disabled";
- };
-
- audio: bus@42000 {
- compatible = "simple-bus";
- reg = <0x0 0x42000 0x0 0x2000>;
- #address-cells = <2>;
- #size-cells = <2>;
- ranges = <0x0 0x0 0x0 0x42000 0x0 0x2000>;
-
- clkc_audio: clock-controller@0 {
- status = "disabled";
- compatible = "amlogic,g12a-audio-clkc";
- reg = <0x0 0x0 0x0 0xb4>;
- #clock-cells = <1>;
- #reset-cells = <1>;
-
- clocks = <&clkc CLKID_AUDIO>,
- <&clkc CLKID_MPLL0>,
- <&clkc CLKID_MPLL1>,
- <&clkc CLKID_MPLL2>,
- <&clkc CLKID_MPLL3>,
- <&clkc CLKID_HIFI_PLL>,
- <&clkc CLKID_FCLK_DIV3>,
- <&clkc CLKID_FCLK_DIV4>,
- <&clkc CLKID_GP0_PLL>;
- clock-names = "pclk",
- "mst_in0",
- "mst_in1",
- "mst_in2",
- "mst_in3",
- "mst_in4",
- "mst_in5",
- "mst_in6",
- "mst_in7";
-
- resets = <&reset RESET_AUDIO>;
- };
-
- toddr_a: audio-controller@100 {
- compatible = "amlogic,g12a-toddr",
- "amlogic,axg-toddr";
- reg = <0x0 0x100 0x0 0x2c>;
- #sound-dai-cells = <0>;
- sound-name-prefix = "TODDR_A";
- interrupts = <GIC_SPI 148 IRQ_TYPE_EDGE_RISING>;
- clocks = <&clkc_audio AUD_CLKID_TODDR_A>;
- resets = <&arb AXG_ARB_TODDR_A>,
- <&clkc_audio AUD_RESET_TODDR_A>;
- reset-names = "arb", "rst";
- amlogic,fifo-depth = <512>;
- status = "disabled";
- };
-
- toddr_b: audio-controller@140 {
- compatible = "amlogic,g12a-toddr",
- "amlogic,axg-toddr";
- reg = <0x0 0x140 0x0 0x2c>;
- #sound-dai-cells = <0>;
- sound-name-prefix = "TODDR_B";
- interrupts = <GIC_SPI 149 IRQ_TYPE_EDGE_RISING>;
- clocks = <&clkc_audio AUD_CLKID_TODDR_B>;
- resets = <&arb AXG_ARB_TODDR_B>,
- <&clkc_audio AUD_RESET_TODDR_B>;
- reset-names = "arb", "rst";
- amlogic,fifo-depth = <256>;
- status = "disabled";
- };
-
- toddr_c: audio-controller@180 {
- compatible = "amlogic,g12a-toddr",
- "amlogic,axg-toddr";
- reg = <0x0 0x180 0x0 0x2c>;
- #sound-dai-cells = <0>;
- sound-name-prefix = "TODDR_C";
- interrupts = <GIC_SPI 150 IRQ_TYPE_EDGE_RISING>;
- clocks = <&clkc_audio AUD_CLKID_TODDR_C>;
- resets = <&arb AXG_ARB_TODDR_C>,
- <&clkc_audio AUD_RESET_TODDR_C>;
- reset-names = "arb", "rst";
- amlogic,fifo-depth = <256>;
- status = "disabled";
- };
-
- frddr_a: audio-controller@1c0 {
- compatible = "amlogic,g12a-frddr",
- "amlogic,axg-frddr";
- reg = <0x0 0x1c0 0x0 0x2c>;
- #sound-dai-cells = <0>;
- sound-name-prefix = "FRDDR_A";
- interrupts = <GIC_SPI 152 IRQ_TYPE_EDGE_RISING>;
- clocks = <&clkc_audio AUD_CLKID_FRDDR_A>;
- resets = <&arb AXG_ARB_FRDDR_A>,
- <&clkc_audio AUD_RESET_FRDDR_A>;
- reset-names = "arb", "rst";
- amlogic,fifo-depth = <512>;
- status = "disabled";
- };
-
- frddr_b: audio-controller@200 {
- compatible = "amlogic,g12a-frddr",
- "amlogic,axg-frddr";
- reg = <0x0 0x200 0x0 0x2c>;
- #sound-dai-cells = <0>;
- sound-name-prefix = "FRDDR_B";
- interrupts = <GIC_SPI 153 IRQ_TYPE_EDGE_RISING>;
- clocks = <&clkc_audio AUD_CLKID_FRDDR_B>;
- resets = <&arb AXG_ARB_FRDDR_B>,
- <&clkc_audio AUD_RESET_FRDDR_B>;
- reset-names = "arb", "rst";
- amlogic,fifo-depth = <256>;
- status = "disabled";
- };
-
- frddr_c: audio-controller@240 {
- compatible = "amlogic,g12a-frddr",
- "amlogic,axg-frddr";
- reg = <0x0 0x240 0x0 0x2c>;
- #sound-dai-cells = <0>;
- sound-name-prefix = "FRDDR_C";
- interrupts = <GIC_SPI 154 IRQ_TYPE_EDGE_RISING>;
- clocks = <&clkc_audio AUD_CLKID_FRDDR_C>;
- resets = <&arb AXG_ARB_FRDDR_C>,
- <&clkc_audio AUD_RESET_FRDDR_C>;
- reset-names = "arb", "rst";
- amlogic,fifo-depth = <256>;
- status = "disabled";
- };
-
- arb: reset-controller@280 {
- status = "disabled";
- compatible = "amlogic,meson-axg-audio-arb";
- reg = <0x0 0x280 0x0 0x4>;
- #reset-cells = <1>;
- clocks = <&clkc_audio AUD_CLKID_DDR_ARB>;
- };
-
- tdmin_a: audio-controller@300 {
- compatible = "amlogic,g12a-tdmin",
- "amlogic,axg-tdmin";
- reg = <0x0 0x300 0x0 0x40>;
- sound-name-prefix = "TDMIN_A";
- resets = <&clkc_audio AUD_RESET_TDMIN_A>;
- clocks = <&clkc_audio AUD_CLKID_TDMIN_A>,
- <&clkc_audio AUD_CLKID_TDMIN_A_SCLK>,
- <&clkc_audio AUD_CLKID_TDMIN_A_SCLK_SEL>,
- <&clkc_audio AUD_CLKID_TDMIN_A_LRCLK>,
- <&clkc_audio AUD_CLKID_TDMIN_A_LRCLK>;
- clock-names = "pclk", "sclk", "sclk_sel",
- "lrclk", "lrclk_sel";
- status = "disabled";
- };
-
- tdmin_b: audio-controller@340 {
- compatible = "amlogic,g12a-tdmin",
- "amlogic,axg-tdmin";
- reg = <0x0 0x340 0x0 0x40>;
- sound-name-prefix = "TDMIN_B";
- resets = <&clkc_audio AUD_RESET_TDMIN_B>;
- clocks = <&clkc_audio AUD_CLKID_TDMIN_B>,
- <&clkc_audio AUD_CLKID_TDMIN_B_SCLK>,
- <&clkc_audio AUD_CLKID_TDMIN_B_SCLK_SEL>,
- <&clkc_audio AUD_CLKID_TDMIN_B_LRCLK>,
- <&clkc_audio AUD_CLKID_TDMIN_B_LRCLK>;
- clock-names = "pclk", "sclk", "sclk_sel",
- "lrclk", "lrclk_sel";
- status = "disabled";
- };
-
- tdmin_c: audio-controller@380 {
- compatible = "amlogic,g12a-tdmin",
- "amlogic,axg-tdmin";
- reg = <0x0 0x380 0x0 0x40>;
- sound-name-prefix = "TDMIN_C";
- resets = <&clkc_audio AUD_RESET_TDMIN_C>;
- clocks = <&clkc_audio AUD_CLKID_TDMIN_C>,
- <&clkc_audio AUD_CLKID_TDMIN_C_SCLK>,
- <&clkc_audio AUD_CLKID_TDMIN_C_SCLK_SEL>,
- <&clkc_audio AUD_CLKID_TDMIN_C_LRCLK>,
- <&clkc_audio AUD_CLKID_TDMIN_C_LRCLK>;
- clock-names = "pclk", "sclk", "sclk_sel",
- "lrclk", "lrclk_sel";
- status = "disabled";
- };
-
- tdmin_lb: audio-controller@3c0 {
- compatible = "amlogic,g12a-tdmin",
- "amlogic,axg-tdmin";
- reg = <0x0 0x3c0 0x0 0x40>;
- sound-name-prefix = "TDMIN_LB";
- resets = <&clkc_audio AUD_RESET_TDMIN_LB>;
- clocks = <&clkc_audio AUD_CLKID_TDMIN_LB>,
- <&clkc_audio AUD_CLKID_TDMIN_LB_SCLK>,
- <&clkc_audio AUD_CLKID_TDMIN_LB_SCLK_SEL>,
- <&clkc_audio AUD_CLKID_TDMIN_LB_LRCLK>,
- <&clkc_audio AUD_CLKID_TDMIN_LB_LRCLK>;
- clock-names = "pclk", "sclk", "sclk_sel",
- "lrclk", "lrclk_sel";
- status = "disabled";
- };
-
- spdifin: audio-controller@400 {
- compatible = "amlogic,g12a-spdifin",
- "amlogic,axg-spdifin";
- reg = <0x0 0x400 0x0 0x30>;
- #sound-dai-cells = <0>;
- sound-name-prefix = "SPDIFIN";
- interrupts = <GIC_SPI 151 IRQ_TYPE_EDGE_RISING>;
- clocks = <&clkc_audio AUD_CLKID_SPDIFIN>,
- <&clkc_audio AUD_CLKID_SPDIFIN_CLK>;
- clock-names = "pclk", "refclk";
- resets = <&clkc_audio AUD_RESET_SPDIFIN>;
- status = "disabled";
- };
-
- spdifout: audio-controller@480 {
- compatible = "amlogic,g12a-spdifout",
- "amlogic,axg-spdifout";
- reg = <0x0 0x480 0x0 0x50>;
- #sound-dai-cells = <0>;
- sound-name-prefix = "SPDIFOUT";
- clocks = <&clkc_audio AUD_CLKID_SPDIFOUT>,
- <&clkc_audio AUD_CLKID_SPDIFOUT_CLK>;
- clock-names = "pclk", "mclk";
- resets = <&clkc_audio AUD_RESET_SPDIFOUT>;
- status = "disabled";
- };
-
- tdmout_a: audio-controller@500 {
- compatible = "amlogic,g12a-tdmout";
- reg = <0x0 0x500 0x0 0x40>;
- sound-name-prefix = "TDMOUT_A";
- resets = <&clkc_audio AUD_RESET_TDMOUT_A>;
- clocks = <&clkc_audio AUD_CLKID_TDMOUT_A>,
- <&clkc_audio AUD_CLKID_TDMOUT_A_SCLK>,
- <&clkc_audio AUD_CLKID_TDMOUT_A_SCLK_SEL>,
- <&clkc_audio AUD_CLKID_TDMOUT_A_LRCLK>,
- <&clkc_audio AUD_CLKID_TDMOUT_A_LRCLK>;
- clock-names = "pclk", "sclk", "sclk_sel",
- "lrclk", "lrclk_sel";
- status = "disabled";
- };
-
- tdmout_b: audio-controller@540 {
- compatible = "amlogic,g12a-tdmout";
- reg = <0x0 0x540 0x0 0x40>;
- sound-name-prefix = "TDMOUT_B";
- resets = <&clkc_audio AUD_RESET_TDMOUT_B>;
- clocks = <&clkc_audio AUD_CLKID_TDMOUT_B>,
- <&clkc_audio AUD_CLKID_TDMOUT_B_SCLK>,
- <&clkc_audio AUD_CLKID_TDMOUT_B_SCLK_SEL>,
- <&clkc_audio AUD_CLKID_TDMOUT_B_LRCLK>,
- <&clkc_audio AUD_CLKID_TDMOUT_B_LRCLK>;
- clock-names = "pclk", "sclk", "sclk_sel",
- "lrclk", "lrclk_sel";
- status = "disabled";
- };
-
- tdmout_c: audio-controller@580 {
- compatible = "amlogic,g12a-tdmout";
- reg = <0x0 0x580 0x0 0x40>;
- sound-name-prefix = "TDMOUT_C";
- resets = <&clkc_audio AUD_RESET_TDMOUT_C>;
- clocks = <&clkc_audio AUD_CLKID_TDMOUT_C>,
- <&clkc_audio AUD_CLKID_TDMOUT_C_SCLK>,
- <&clkc_audio AUD_CLKID_TDMOUT_C_SCLK_SEL>,
- <&clkc_audio AUD_CLKID_TDMOUT_C_LRCLK>,
- <&clkc_audio AUD_CLKID_TDMOUT_C_LRCLK>;
- clock-names = "pclk", "sclk", "sclk_sel",
- "lrclk", "lrclk_sel";
- status = "disabled";
- };
-
- spdifout_b: audio-controller@680 {
- compatible = "amlogic,g12a-spdifout",
- "amlogic,axg-spdifout";
- reg = <0x0 0x680 0x0 0x50>;
- #sound-dai-cells = <0>;
- sound-name-prefix = "SPDIFOUT_B";
- clocks = <&clkc_audio AUD_CLKID_SPDIFOUT_B>,
- <&clkc_audio AUD_CLKID_SPDIFOUT_B_CLK>;
- clock-names = "pclk", "mclk";
- resets = <&clkc_audio AUD_RESET_SPDIFOUT_B>;
- status = "disabled";
- };
-
- toacodec: audio-controller@740 {
- compatible = "amlogic,g12a-toacodec";
- reg = <0x0 0x740 0x0 0x4>;
- #sound-dai-cells = <1>;
- sound-name-prefix = "TOACODEC";
- resets = <&clkc_audio AUD_RESET_TOACODEC>;
- status = "disabled";
- };
-
- tohdmitx: audio-controller@744 {
- compatible = "amlogic,g12a-tohdmitx";
- reg = <0x0 0x744 0x0 0x4>;
- #sound-dai-cells = <1>;
- sound-name-prefix = "TOHDMITX";
- resets = <&clkc_audio AUD_RESET_TOHDMITX>;
- status = "disabled";
- };
- };
-};
-
-ðmac {
- power-domains = <&pwrc PWRC_G12A_ETH_ID>;
-};
-
-&vpu {
- power-domains = <&pwrc PWRC_G12A_VPU_ID>;
-};
-
-&sd_emmc_a {
- amlogic,dram-access-quirk;
-};
-
-&simplefb_cvbs {
- power-domains = <&pwrc PWRC_G12A_VPU_ID>;
-};
-
-&simplefb_hdmi {
- power-domains = <&pwrc PWRC_G12A_VPU_ID>;
-};
-
diff --git a/arch/arm/dts/meson-g12a-radxa-zero.dts b/arch/arm/dts/meson-g12a-radxa-zero.dts
deleted file mode 100644
index e3bb6df..0000000
--- a/arch/arm/dts/meson-g12a-radxa-zero.dts
+++ /dev/null
@@ -1,405 +0,0 @@
-// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
-/*
- * Copyright (c) 2018 BayLibre SAS. All rights reserved.
- */
-
-/dts-v1/;
-
-#include "meson-g12a.dtsi"
-#include <dt-bindings/gpio/meson-g12a-gpio.h>
-#include <dt-bindings/sound/meson-g12a-tohdmitx.h>
-
-/ {
- compatible = "radxa,zero", "amlogic,g12a";
- model = "Radxa Zero";
-
- aliases {
- serial0 = &uart_AO;
- };
-
- chosen {
- stdout-path = "serial0:115200n8";
- };
-
- memory@0 {
- device_type = "memory";
- reg = <0x0 0x0 0x0 0x40000000>;
- };
-
- cvbs-connector {
- status = "disabled";
- compatible = "composite-video-connector";
-
- port {
- cvbs_connector_in: endpoint {
- remote-endpoint = <&cvbs_vdac_out>;
- };
- };
- };
-
- hdmi-connector {
- compatible = "hdmi-connector";
- type = "a";
-
- port {
- hdmi_connector_in: endpoint {
- remote-endpoint = <&hdmi_tx_tmds_out>;
- };
- };
- };
-
- emmc_pwrseq: emmc-pwrseq {
- compatible = "mmc-pwrseq-emmc";
- reset-gpios = <&gpio BOOT_12 GPIO_ACTIVE_LOW>;
- };
-
- sdio_pwrseq: sdio-pwrseq {
- compatible = "mmc-pwrseq-simple";
- reset-gpios = <&gpio GPIOX_6 GPIO_ACTIVE_LOW>;
- clocks = <&wifi32k>;
- clock-names = "ext_clock";
- };
-
- ao_5v: regulator-ao_5v {
- compatible = "regulator-fixed";
- regulator-name = "AO_5V";
- regulator-min-microvolt = <5000000>;
- regulator-max-microvolt = <5000000>;
- regulator-always-on;
- };
-
- vcc_1v8: regulator-vcc_1v8 {
- compatible = "regulator-fixed";
- regulator-name = "VCC_1V8";
- regulator-min-microvolt = <1800000>;
- regulator-max-microvolt = <1800000>;
- vin-supply = <&vcc_3v3>;
- regulator-always-on;
- };
-
- vcc_3v3: regulator-vcc_3v3 {
- compatible = "regulator-fixed";
- regulator-name = "VCC_3V3";
- regulator-min-microvolt = <3300000>;
- regulator-max-microvolt = <3300000>;
- vin-supply = <&vddao_3v3>;
- regulator-always-on;
- };
-
- hdmi_pw: regulator-hdmi_pw {
- compatible = "regulator-fixed";
- regulator-name = "HDMI_PW";
- regulator-min-microvolt = <5000000>;
- regulator-max-microvolt = <5000000>;
- vin-supply = <&ao_5v>;
- regulator-always-on;
- };
-
- vddao_1v8: regulator-vddao_1v8 {
- compatible = "regulator-fixed";
- regulator-name = "VDDAO_1V8";
- regulator-min-microvolt = <1800000>;
- regulator-max-microvolt = <1800000>;
- vin-supply = <&vddao_3v3>;
- regulator-always-on;
- };
-
- vddao_3v3: regulator-vddao_3v3 {
- compatible = "regulator-fixed";
- regulator-name = "VDDAO_3V3";
- regulator-min-microvolt = <3300000>;
- regulator-max-microvolt = <3300000>;
- vin-supply = <&ao_5v>;
- regulator-always-on;
- };
-
- vddcpu: regulator-vddcpu {
- compatible = "pwm-regulator";
-
- regulator-name = "VDDCPU";
- regulator-min-microvolt = <721000>;
- regulator-max-microvolt = <1022000>;
-
- vin-supply = <&ao_5v>;
-
- pwms = <&pwm_AO_cd 1 1250 0>;
- pwm-dutycycle-range = <100 0>;
-
- regulator-boot-on;
- regulator-always-on;
- };
-
- sound {
- compatible = "amlogic,axg-sound-card";
- model = "RADXA-ZERO";
- audio-aux-devs = <&tdmout_b>;
- audio-routing = "TDMOUT_B IN 0", "FRDDR_A OUT 1",
- "TDMOUT_B IN 1", "FRDDR_B OUT 1",
- "TDMOUT_B IN 2", "FRDDR_C OUT 1",
- "TDM_B Playback", "TDMOUT_B OUT";
-
- assigned-clocks = <&clkc CLKID_MPLL2>,
- <&clkc CLKID_MPLL0>,
- <&clkc CLKID_MPLL1>;
- assigned-clock-parents = <0>, <0>, <0>;
- assigned-clock-rates = <294912000>,
- <270950400>,
- <393216000>;
- status = "okay";
-
- dai-link-0 {
- sound-dai = <&frddr_a>;
- };
-
- dai-link-1 {
- sound-dai = <&frddr_b>;
- };
-
- dai-link-2 {
- sound-dai = <&frddr_c>;
- };
-
- /* 8ch hdmi interface */
- dai-link-3 {
- sound-dai = <&tdmif_b>;
- dai-format = "i2s";
- dai-tdm-slot-tx-mask-0 = <1 1>;
- dai-tdm-slot-tx-mask-1 = <1 1>;
- dai-tdm-slot-tx-mask-2 = <1 1>;
- dai-tdm-slot-tx-mask-3 = <1 1>;
- mclk-fs = <256>;
-
- codec {
- sound-dai = <&tohdmitx TOHDMITX_I2S_IN_B>;
- };
- };
-
- dai-link-4 {
- sound-dai = <&tohdmitx TOHDMITX_I2S_OUT>;
-
- codec {
- sound-dai = <&hdmi_tx>;
- };
- };
- };
-
- wifi32k: wifi32k {
- compatible = "pwm-clock";
- #clock-cells = <0>;
- clock-frequency = <32768>;
- pwms = <&pwm_ef 0 30518 0>; /* PWM_E at 32.768KHz */
- };
-};
-
-&arb {
- status = "okay";
-};
-
-&cec_AO {
- pinctrl-0 = <&cec_ao_a_h_pins>;
- pinctrl-names = "default";
- status = "disabled";
- hdmi-phandle = <&hdmi_tx>;
-};
-
-&cecb_AO {
- pinctrl-0 = <&cec_ao_b_h_pins>;
- pinctrl-names = "default";
- status = "okay";
- hdmi-phandle = <&hdmi_tx>;
-};
-
-&clkc_audio {
- status = "okay";
-};
-
-&cpu0 {
- cpu-supply = <&vddcpu>;
- operating-points-v2 = <&cpu_opp_table>;
- clocks = <&clkc CLKID_CPU_CLK>;
- clock-latency = <50000>;
-};
-
-&cpu1 {
- cpu-supply = <&vddcpu>;
- operating-points-v2 = <&cpu_opp_table>;
- clocks = <&clkc CLKID_CPU_CLK>;
- clock-latency = <50000>;
-};
-
-&cpu2 {
- cpu-supply = <&vddcpu>;
- operating-points-v2 = <&cpu_opp_table>;
- clocks = <&clkc CLKID_CPU_CLK>;
- clock-latency = <50000>;
-};
-
-&cpu3 {
- cpu-supply = <&vddcpu>;
- operating-points-v2 = <&cpu_opp_table>;
- clocks = <&clkc CLKID_CPU_CLK>;
- clock-latency = <50000>;
-};
-
-&cvbs_vdac_port {
- cvbs_vdac_out: endpoint {
- remote-endpoint = <&cvbs_connector_in>;
- };
-};
-
-&frddr_a {
- status = "okay";
-};
-
-&frddr_b {
- status = "okay";
-};
-
-&frddr_c {
- status = "okay";
-};
-
-&hdmi_tx {
- status = "okay";
- pinctrl-0 = <&hdmitx_hpd_pins>, <&hdmitx_ddc_pins>;
- pinctrl-names = "default";
- hdmi-supply = <&hdmi_pw>;
-};
-
-&hdmi_tx_tmds_port {
- hdmi_tx_tmds_out: endpoint {
- remote-endpoint = <&hdmi_connector_in>;
- };
-};
-
-&ir {
- status = "disabled";
- pinctrl-0 = <&remote_input_ao_pins>;
- pinctrl-names = "default";
-};
-
-&pwm_AO_cd {
- pinctrl-0 = <&pwm_ao_d_e_pins>;
- pinctrl-names = "default";
- clocks = <&xtal>;
- clock-names = "clkin1";
- status = "okay";
-};
-
-&pwm_ef {
- status = "okay";
- pinctrl-0 = <&pwm_e_pins>;
- pinctrl-names = "default";
- clocks = <&xtal>;
- clock-names = "clkin0";
-};
-
-&saradc {
- status = "okay";
- vref-supply = <&vddao_1v8>;
-};
-
-/* SDIO */
-&sd_emmc_a {
- status = "okay";
- pinctrl-0 = <&sdio_pins>;
- pinctrl-1 = <&sdio_clk_gate_pins>;
- pinctrl-names = "default", "clk-gate";
- #address-cells = <1>;
- #size-cells = <0>;
-
- bus-width = <4>;
- cap-sd-highspeed;
- sd-uhs-sdr50;
- max-frequency = <100000000>;
-
- non-removable;
- disable-wp;
-
- /* WiFi firmware requires power to be kept while in suspend */
- keep-power-in-suspend;
-
- mmc-pwrseq = <&sdio_pwrseq>;
-
- vmmc-supply = <&vddao_3v3>;
- vqmmc-supply = <&vddao_1v8>;
-
- brcmf: wifi@1 {
- reg = <1>;
- compatible = "brcm,bcm4329-fmac";
- };
-};
-
-/* SD card */
-&sd_emmc_b {
- status = "okay";
- pinctrl-0 = <&sdcard_c_pins>;
- pinctrl-1 = <&sdcard_clk_gate_c_pins>;
- pinctrl-names = "default", "clk-gate";
-
- bus-width = <4>;
- cap-sd-highspeed;
- max-frequency = <100000000>;
- disable-wp;
-
- cd-gpios = <&gpio GPIOC_6 GPIO_ACTIVE_LOW>;
- vmmc-supply = <&vddao_3v3>;
- vqmmc-supply = <&vddao_3v3>;
-};
-
-/* eMMC */
-&sd_emmc_c {
- status = "okay";
- pinctrl-0 = <&emmc_ctrl_pins>, <&emmc_data_8b_pins>, <&emmc_ds_pins>;
- pinctrl-1 = <&emmc_clk_gate_pins>;
- pinctrl-names = "default", "clk-gate";
-
- bus-width = <8>;
- cap-mmc-highspeed;
- mmc-ddr-1_8v;
- mmc-hs200-1_8v;
- max-frequency = <200000000>;
- disable-wp;
-
- mmc-pwrseq = <&emmc_pwrseq>;
- vmmc-supply = <&vcc_3v3>;
- vqmmc-supply = <&vcc_1v8>;
-};
-
-&tdmif_b {
- status = "okay";
-};
-
-&tdmout_b {
- status = "okay";
-};
-
-&tohdmitx {
- status = "okay";
-};
-
-&uart_A {
- status = "okay";
- pinctrl-0 = <&uart_a_pins>, <&uart_a_cts_rts_pins>;
- pinctrl-names = "default";
- uart-has-rtscts;
-
- bluetooth {
- compatible = "brcm,bcm43438-bt";
- shutdown-gpios = <&gpio GPIOX_17 GPIO_ACTIVE_HIGH>;
- max-speed = <2000000>;
- clocks = <&wifi32k>;
- clock-names = "lpo";
- };
-};
-
-&uart_AO {
- status = "okay";
- pinctrl-0 = <&uart_ao_a_pins>;
- pinctrl-names = "default";
-};
-
-&usb {
- status = "okay";
- dr_mode = "host";
-};
diff --git a/arch/arm/dts/meson-g12a-sei510.dts b/arch/arm/dts/meson-g12a-sei510.dts
deleted file mode 100644
index 81269cc..0000000
--- a/arch/arm/dts/meson-g12a-sei510.dts
+++ /dev/null
@@ -1,566 +0,0 @@
-// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
-/*
- * Copyright (c) 2019 BayLibre SAS. All rights reserved.
- */
-
-/dts-v1/;
-
-#include "meson-g12a.dtsi"
-#include <dt-bindings/gpio/gpio.h>
-#include <dt-bindings/input/input.h>
-#include <dt-bindings/gpio/meson-g12a-gpio.h>
-#include <dt-bindings/sound/meson-g12a-tohdmitx.h>
-
-/ {
- compatible = "seirobotics,sei510", "amlogic,g12a";
- model = "SEI Robotics SEI510";
-
- adc_keys {
- compatible = "adc-keys";
- io-channels = <&saradc 0>;
- io-channel-names = "buttons";
- keyup-threshold-microvolt = <1800000>;
-
- button-onoff {
- label = "On/Off";
- linux,code = <KEY_POWER>;
- press-threshold-microvolt = <1700000>;
- };
- };
-
- aliases {
- serial0 = &uart_AO;
- ethernet0 = ðmac;
- };
-
- mono_dac: audio-codec-0 {
- compatible = "maxim,max98357a";
- #sound-dai-cells = <0>;
- sound-name-prefix = "U16";
- sdmode-gpios = <&gpio GPIOX_8 GPIO_ACTIVE_HIGH>;
- };
-
- dmics: audio-codec-1 {
- #sound-dai-cells = <0>;
- compatible = "dmic-codec";
- num-channels = <2>;
- wakeup-delay-ms = <50>;
- status = "okay";
- sound-name-prefix = "MIC";
- };
-
- chosen {
- stdout-path = "serial0:115200n8";
- };
-
- cvbs-connector {
- compatible = "composite-video-connector";
-
- port {
- cvbs_connector_in: endpoint {
- remote-endpoint = <&cvbs_vdac_out>;
- };
- };
- };
-
- emmc_pwrseq: emmc-pwrseq {
- compatible = "mmc-pwrseq-emmc";
- reset-gpios = <&gpio BOOT_12 GPIO_ACTIVE_LOW>;
- };
-
- hdmi-connector {
- compatible = "hdmi-connector";
- type = "a";
-
- port {
- hdmi_connector_in: endpoint {
- remote-endpoint = <&hdmi_tx_tmds_out>;
- };
- };
- };
-
- memory@0 {
- device_type = "memory";
- reg = <0x0 0x0 0x0 0x40000000>;
- };
-
- ao_5v: regulator-ao_5v {
- compatible = "regulator-fixed";
- regulator-name = "AO_5V";
- regulator-min-microvolt = <5000000>;
- regulator-max-microvolt = <5000000>;
- vin-supply = <&dc_in>;
- regulator-always-on;
- };
-
- dc_in: regulator-dc_in {
- compatible = "regulator-fixed";
- regulator-name = "DC_IN";
- regulator-min-microvolt = <5000000>;
- regulator-max-microvolt = <5000000>;
- regulator-always-on;
- };
-
- emmc_1v8: regulator-emmc_1v8 {
- compatible = "regulator-fixed";
- regulator-name = "EMMC_1V8";
- regulator-min-microvolt = <1800000>;
- regulator-max-microvolt = <1800000>;
- vin-supply = <&vddao_3v3>;
- regulator-always-on;
- };
-
- vddao_3v3: regulator-vddao_3v3 {
- compatible = "regulator-fixed";
- regulator-name = "VDDAO_3V3";
- regulator-min-microvolt = <3300000>;
- regulator-max-microvolt = <3300000>;
- vin-supply = <&dc_in>;
- regulator-always-on;
- };
-
- vddao_3v3_t: regultor-vddao_3v3_t {
- compatible = "regulator-fixed";
- regulator-name = "VDDAO_3V3_T";
- regulator-min-microvolt = <3300000>;
- regulator-max-microvolt = <3300000>;
- vin-supply = <&vddao_3v3>;
- gpio = <&gpio GPIOH_8 GPIO_OPEN_DRAIN>;
- enable-active-high;
- };
-
- vddcpu: regulator-vddcpu {
- /*
- * SY8120B1ABC DC/DC Regulator.
- */
- compatible = "pwm-regulator";
-
- regulator-name = "VDDCPU";
- regulator-min-microvolt = <721000>;
- regulator-max-microvolt = <1022000>;
-
- vin-supply = <&dc_in>;
-
- pwms = <&pwm_AO_cd 1 1250 0>;
- pwm-dutycycle-range = <100 0>;
-
- regulator-boot-on;
- regulator-always-on;
- };
-
- vddio_ao1v8: regulator-vddio_ao1v8 {
- compatible = "regulator-fixed";
- regulator-name = "VDDIO_AO1V8";
- regulator-min-microvolt = <1800000>;
- regulator-max-microvolt = <1800000>;
- vin-supply = <&vddao_3v3>;
- regulator-always-on;
- };
-
- reserved-memory {
- /* TEE Reserved Memory */
- bl32_reserved: bl32@5000000 {
- reg = <0x0 0x05300000 0x0 0x2000000>;
- no-map;
- };
- };
-
- sdio_pwrseq: sdio-pwrseq {
- compatible = "mmc-pwrseq-simple";
- reset-gpios = <&gpio GPIOX_6 GPIO_ACTIVE_LOW>;
- clocks = <&wifi32k>;
- clock-names = "ext_clock";
- };
-
- wifi32k: wifi32k {
- compatible = "pwm-clock";
- #clock-cells = <0>;
- clock-frequency = <32768>;
- pwms = <&pwm_ef 0 30518 0>; /* PWM_E at 32.768KHz */
- };
-
- sound {
- compatible = "amlogic,axg-sound-card";
- model = "SEI510";
- audio-aux-devs = <&tdmout_a>, <&tdmout_b>,
- <&tdmin_a>, <&tdmin_b>;
- audio-routing = "TDMOUT_A IN 0", "FRDDR_A OUT 0",
- "TDMOUT_A IN 1", "FRDDR_B OUT 0",
- "TDMOUT_A IN 2", "FRDDR_C OUT 0",
- "TDM_A Playback", "TDMOUT_A OUT",
- "TDMOUT_B IN 0", "FRDDR_A OUT 1",
- "TDMOUT_B IN 1", "FRDDR_B OUT 1",
- "TDMOUT_B IN 2", "FRDDR_C OUT 1",
- "TDM_B Playback", "TDMOUT_B OUT",
- "TODDR_A IN 4", "PDM Capture",
- "TODDR_B IN 4", "PDM Capture",
- "TODDR_C IN 4", "PDM Capture",
- "TDMIN_A IN 0", "TDM_A Capture",
- "TDMIN_A IN 3", "TDM_A Loopback",
- "TDMIN_B IN 0", "TDM_A Capture",
- "TDMIN_B IN 3", "TDM_A Loopback",
- "TDMIN_A IN 1", "TDM_B Capture",
- "TDMIN_A IN 4", "TDM_B Loopback",
- "TDMIN_B IN 1", "TDM_B Capture",
- "TDMIN_B IN 4", "TDM_B Loopback",
- "TODDR_A IN 0", "TDMIN_A OUT",
- "TODDR_B IN 0", "TDMIN_A OUT",
- "TODDR_C IN 0", "TDMIN_A OUT",
- "TODDR_A IN 1", "TDMIN_B OUT",
- "TODDR_B IN 1", "TDMIN_B OUT",
- "TODDR_C IN 1", "TDMIN_B OUT";
-
- assigned-clocks = <&clkc CLKID_MPLL2>,
- <&clkc CLKID_MPLL0>,
- <&clkc CLKID_MPLL1>;
- assigned-clock-parents = <0>, <0>, <0>;
- assigned-clock-rates = <294912000>,
- <270950400>,
- <393216000>;
- status = "okay";
-
- dai-link-0 {
- sound-dai = <&frddr_a>;
- };
-
- dai-link-1 {
- sound-dai = <&frddr_b>;
- };
-
- dai-link-2 {
- sound-dai = <&frddr_c>;
- };
-
- dai-link-3 {
- sound-dai = <&toddr_a>;
- };
-
- dai-link-4 {
- sound-dai = <&toddr_b>;
- };
-
- dai-link-5 {
- sound-dai = <&toddr_c>;
- };
-
- /* internal speaker interface */
- dai-link-6 {
- sound-dai = <&tdmif_a>;
- dai-format = "i2s";
- dai-tdm-slot-tx-mask-0 = <1 1>;
- mclk-fs = <256>;
-
- codec-0 {
- sound-dai = <&mono_dac>;
- };
-
- codec-1 {
- sound-dai = <&tohdmitx TOHDMITX_I2S_IN_A>;
- };
- };
-
- /* 8ch hdmi interface */
- dai-link-7 {
- sound-dai = <&tdmif_b>;
- dai-format = "i2s";
- dai-tdm-slot-tx-mask-0 = <1 1>;
- dai-tdm-slot-tx-mask-1 = <1 1>;
- dai-tdm-slot-tx-mask-2 = <1 1>;
- dai-tdm-slot-tx-mask-3 = <1 1>;
- mclk-fs = <256>;
-
- codec {
- sound-dai = <&tohdmitx TOHDMITX_I2S_IN_B>;
- };
- };
-
- /* internal digital mics */
- dai-link-8 {
- sound-dai = <&pdm>;
-
- codec {
- sound-dai = <&dmics>;
- };
- };
-
- /* hdmi glue */
- dai-link-9 {
- sound-dai = <&tohdmitx TOHDMITX_I2S_OUT>;
-
- codec {
- sound-dai = <&hdmi_tx>;
- };
- };
- };
-};
-
-&arb {
- status = "okay";
-};
-
-&cec_AO {
- pinctrl-0 = <&cec_ao_a_h_pins>;
- pinctrl-names = "default";
- status = "disabled";
- hdmi-phandle = <&hdmi_tx>;
-};
-
-&cecb_AO {
- pinctrl-0 = <&cec_ao_b_h_pins>;
- pinctrl-names = "default";
- status = "okay";
- hdmi-phandle = <&hdmi_tx>;
-};
-
-&clkc_audio {
- status = "okay";
-};
-
-&cpu0 {
- cpu-supply = <&vddcpu>;
- operating-points-v2 = <&cpu_opp_table>;
- clocks = <&clkc CLKID_CPU_CLK>;
- clock-latency = <50000>;
-};
-
-&cpu1 {
- cpu-supply = <&vddcpu>;
- operating-points-v2 = <&cpu_opp_table>;
- clocks = <&clkc CLKID_CPU_CLK>;
- clock-latency = <50000>;
-};
-
-&cpu2 {
- cpu-supply = <&vddcpu>;
- operating-points-v2 = <&cpu_opp_table>;
- clocks = <&clkc CLKID_CPU_CLK>;
- clock-latency = <50000>;
-};
-
-&cpu3 {
- cpu-supply = <&vddcpu>;
- operating-points-v2 = <&cpu_opp_table>;
- clocks = <&clkc CLKID_CPU_CLK>;
- clock-latency = <50000>;
-};
-
-&cvbs_vdac_port {
- cvbs_vdac_out: endpoint {
- remote-endpoint = <&cvbs_connector_in>;
- };
-};
-
-ðmac {
- status = "okay";
- phy-handle = <&internal_ephy>;
- phy-mode = "rmii";
-};
-
-&frddr_a {
- status = "okay";
-};
-
-&frddr_b {
- status = "okay";
-};
-
-&frddr_c {
- status = "okay";
-};
-
-&hdmi_tx {
- status = "okay";
- pinctrl-0 = <&hdmitx_hpd_pins>, <&hdmitx_ddc_pins>;
- pinctrl-names = "default";
-};
-
-&hdmi_tx_tmds_port {
- hdmi_tx_tmds_out: endpoint {
- remote-endpoint = <&hdmi_connector_in>;
- };
-};
-
-&i2c3 {
- status = "okay";
- pinctrl-0 = <&i2c3_sda_a_pins>, <&i2c3_sck_a_pins>;
- pinctrl-names = "default";
-};
-
-&ir {
- status = "okay";
- pinctrl-0 = <&remote_input_ao_pins>;
- pinctrl-names = "default";
-};
-
-&pwm_AO_cd {
- pinctrl-0 = <&pwm_ao_d_e_pins>;
- pinctrl-names = "default";
- clocks = <&xtal>;
- clock-names = "clkin1";
- status = "okay";
-};
-
-&pwm_ef {
- status = "okay";
- pinctrl-0 = <&pwm_e_pins>;
- pinctrl-names = "default";
- clocks = <&xtal>;
- clock-names = "clkin0";
-};
-
-&pdm {
- pinctrl-0 = <&pdm_din0_z_pins>, <&pdm_din1_z_pins>,
- <&pdm_din2_z_pins>, <&pdm_din3_z_pins>,
- <&pdm_dclk_z_pins>;
- pinctrl-names = "default";
- status = "okay";
-};
-
-&saradc {
- status = "okay";
- vref-supply = <&vddio_ao1v8>;
-};
-
-/* SDIO */
-&sd_emmc_a {
- status = "okay";
- pinctrl-0 = <&sdio_pins>;
- pinctrl-1 = <&sdio_clk_gate_pins>;
- pinctrl-names = "default", "clk-gate";
- #address-cells = <1>;
- #size-cells = <0>;
-
- bus-width = <4>;
- cap-sd-highspeed;
- sd-uhs-sdr50;
- max-frequency = <100000000>;
-
- non-removable;
- disable-wp;
-
- /* WiFi firmware requires power to be kept while in suspend */
- keep-power-in-suspend;
-
- mmc-pwrseq = <&sdio_pwrseq>;
-
- vmmc-supply = <&vddao_3v3>;
- vqmmc-supply = <&vddio_ao1v8>;
-
- brcmf: wifi@1 {
- reg = <1>;
- compatible = "brcm,bcm4329-fmac";
- };
-};
-
-/* SD card */
-&sd_emmc_b {
- status = "okay";
- pinctrl-0 = <&sdcard_c_pins>;
- pinctrl-1 = <&sdcard_clk_gate_c_pins>;
- pinctrl-names = "default", "clk-gate";
-
- bus-width = <4>;
- cap-sd-highspeed;
- max-frequency = <50000000>;
- disable-wp;
-
- cd-gpios = <&gpio GPIOC_6 GPIO_ACTIVE_LOW>;
- vmmc-supply = <&vddao_3v3>;
- vqmmc-supply = <&vddao_3v3>;
-};
-
-/* eMMC */
-&sd_emmc_c {
- status = "okay";
- pinctrl-0 = <&emmc_ctrl_pins>, <&emmc_data_8b_pins>, <&emmc_ds_pins>;
- pinctrl-1 = <&emmc_clk_gate_pins>;
- pinctrl-names = "default", "clk-gate";
-
- bus-width = <8>;
- cap-mmc-highspeed;
- mmc-ddr-1_8v;
- mmc-hs200-1_8v;
- max-frequency = <200000000>;
- non-removable;
- disable-wp;
-
- mmc-pwrseq = <&emmc_pwrseq>;
- vmmc-supply = <&vddao_3v3>;
- vqmmc-supply = <&emmc_1v8>;
-};
-
-&tdmif_a {
- pinctrl-0 = <&tdm_a_dout0_pins>, <&tdm_a_fs_pins>, <&tdm_a_sclk_pins>;
- pinctrl-names = "default";
- status = "okay";
-
- assigned-clocks = <&clkc_audio AUD_CLKID_TDM_SCLK_PAD0>,
- <&clkc_audio AUD_CLKID_TDM_LRCLK_PAD0>;
- assigned-clock-parents = <&clkc_audio AUD_CLKID_MST_A_SCLK>,
- <&clkc_audio AUD_CLKID_MST_A_LRCLK>;
- assigned-clock-rates = <0>, <0>;
-};
-
-&tdmif_b {
- status = "okay";
-};
-
-&tdmin_a {
- status = "okay";
-};
-
-&tdmin_b {
- status = "okay";
-};
-
-&tdmout_a {
- status = "okay";
-};
-
-&tdmout_b {
- status = "okay";
-};
-
-&toddr_a {
- status = "okay";
-};
-
-&toddr_b {
- status = "okay";
-};
-
-&toddr_c {
- status = "okay";
-};
-
-&tohdmitx {
- status = "okay";
-};
-
-&uart_A {
- status = "okay";
- pinctrl-0 = <&uart_a_pins>, <&uart_a_cts_rts_pins>;
- pinctrl-names = "default";
- uart-has-rtscts;
-
- bluetooth {
- compatible = "brcm,bcm43438-bt";
- shutdown-gpios = <&gpio GPIOX_17 GPIO_ACTIVE_HIGH>;
- max-speed = <2000000>;
- clocks = <&wifi32k>;
- clock-names = "lpo";
- vbat-supply = <&vddao_3v3>;
- vddio-supply = <&vddio_ao1v8>;
- };
-};
-
-&uart_AO {
- status = "okay";
- pinctrl-0 = <&uart_ao_a_pins>;
- pinctrl-names = "default";
-};
-
-&usb {
- status = "okay";
- dr_mode = "host";
-};
diff --git a/arch/arm/dts/meson-g12a-u200.dts b/arch/arm/dts/meson-g12a-u200.dts
deleted file mode 100644
index a26bfe7..0000000
--- a/arch/arm/dts/meson-g12a-u200.dts
+++ /dev/null
@@ -1,308 +0,0 @@
-// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
-/*
- * Copyright (c) 2018 Amlogic, Inc. All rights reserved.
- */
-
-/dts-v1/;
-
-#include "meson-g12a.dtsi"
-#include <dt-bindings/gpio/gpio.h>
-#include <dt-bindings/gpio/meson-g12a-gpio.h>
-
-/ {
- compatible = "amlogic,u200", "amlogic,g12a";
- model = "Amlogic Meson G12A U200 Development Board";
-
- aliases {
- serial0 = &uart_AO;
- ethernet0 = ðmac;
- };
-
- chosen {
- stdout-path = "serial0:115200n8";
- };
-
- cvbs-connector {
- compatible = "composite-video-connector";
-
- port {
- cvbs_connector_in: endpoint {
- remote-endpoint = <&cvbs_vdac_out>;
- };
- };
- };
-
- emmc_pwrseq: emmc-pwrseq {
- compatible = "mmc-pwrseq-emmc";
- reset-gpios = <&gpio BOOT_12 GPIO_ACTIVE_LOW>;
- };
-
- hdmi-connector {
- compatible = "hdmi-connector";
- type = "a";
-
- port {
- hdmi_connector_in: endpoint {
- remote-endpoint = <&hdmi_tx_tmds_out>;
- };
- };
- };
-
- memory@0 {
- device_type = "memory";
- reg = <0x0 0x0 0x0 0x40000000>;
- };
-
- flash_1v8: regulator-flash_1v8 {
- compatible = "regulator-fixed";
- regulator-name = "FLASH_1V8";
- regulator-min-microvolt = <1800000>;
- regulator-max-microvolt = <1800000>;
- vin-supply = <&vcc_3v3>;
- regulator-always-on;
- };
-
- main_12v: regulator-main_12v {
- compatible = "regulator-fixed";
- regulator-name = "12V";
- regulator-min-microvolt = <12000000>;
- regulator-max-microvolt = <12000000>;
- regulator-always-on;
- };
-
- usb_pwr_en: regulator-usb_pwr_en {
- compatible = "regulator-fixed";
- regulator-name = "USB_PWR_EN";
- regulator-min-microvolt = <5000000>;
- regulator-max-microvolt = <5000000>;
- vin-supply = <&vcc_5v>;
-
- gpio = <&gpio GPIOH_6 GPIO_ACTIVE_HIGH>;
- enable-active-high;
- };
-
- vcc_1v8: regulator-vcc_1v8 {
- compatible = "regulator-fixed";
- regulator-name = "VCC_1V8";
- regulator-min-microvolt = <1800000>;
- regulator-max-microvolt = <1800000>;
- vin-supply = <&vcc_3v3>;
- regulator-always-on;
- };
-
- vcc_3v3: regulator-vcc_3v3 {
- compatible = "regulator-fixed";
- regulator-name = "VCC_3V3";
- regulator-min-microvolt = <3300000>;
- regulator-max-microvolt = <3300000>;
- vin-supply = <&vddao_3v3>;
- regulator-always-on;
- /* FIXME: actually controlled by VDDCPU_B_EN */
- };
-
- vcc_5v: regulator-vcc_5v {
- compatible = "regulator-fixed";
- regulator-name = "VCC_5V";
- regulator-min-microvolt = <5000000>;
- regulator-max-microvolt = <5000000>;
- vin-supply = <&main_12v>;
-
- gpio = <&gpio GPIOH_8 GPIO_OPEN_DRAIN>;
- enable-active-high;
- };
-
- vddao_1v8: regulator-vddao_1v8 {
- compatible = "regulator-fixed";
- regulator-name = "VDDAO_1V8";
- regulator-min-microvolt = <1800000>;
- regulator-max-microvolt = <1800000>;
- vin-supply = <&vddao_3v3>;
- regulator-always-on;
- };
-
- vddao_3v3: regulator-vddao_3v3 {
- compatible = "regulator-fixed";
- regulator-name = "VDDAO_3V3";
- regulator-min-microvolt = <3300000>;
- regulator-max-microvolt = <3300000>;
- vin-supply = <&main_12v>;
- regulator-always-on;
- };
-
- vddcpu: regulator-vddcpu {
- /*
- * MP8756GD Regulator.
- */
- compatible = "pwm-regulator";
-
- regulator-name = "VDDCPU";
- regulator-min-microvolt = <721000>;
- regulator-max-microvolt = <1022000>;
-
- vin-supply = <&main_12v>;
-
- pwms = <&pwm_AO_cd 1 1250 0>;
- pwm-dutycycle-range = <100 0>;
-
- regulator-boot-on;
- regulator-always-on;
- };
-};
-
-&cec_AO {
- pinctrl-0 = <&cec_ao_a_h_pins>;
- pinctrl-names = "default";
- status = "disabled";
- hdmi-phandle = <&hdmi_tx>;
-};
-
-&cecb_AO {
- pinctrl-0 = <&cec_ao_b_h_pins>;
- pinctrl-names = "default";
- status = "okay";
- hdmi-phandle = <&hdmi_tx>;
-};
-
-&cpu0 {
- cpu-supply = <&vddcpu>;
- operating-points-v2 = <&cpu_opp_table>;
- clocks = <&clkc CLKID_CPU_CLK>;
- clock-latency = <50000>;
-};
-
-&cpu1 {
- cpu-supply = <&vddcpu>;
- operating-points-v2 = <&cpu_opp_table>;
- clocks = <&clkc CLKID_CPU_CLK>;
- clock-latency = <50000>;
-};
-
-&cpu2 {
- cpu-supply = <&vddcpu>;
- operating-points-v2 = <&cpu_opp_table>;
- clocks = <&clkc CLKID_CPU_CLK>;
- clock-latency = <50000>;
-};
-
-&cpu3 {
- cpu-supply = <&vddcpu>;
- operating-points-v2 = <&cpu_opp_table>;
- clocks = <&clkc CLKID_CPU_CLK>;
- clock-latency = <50000>;
-};
-
-&cvbs_vdac_port {
- cvbs_vdac_out: endpoint {
- remote-endpoint = <&cvbs_connector_in>;
- };
-};
-
-ðmac {
- status = "okay";
- phy-handle = <&internal_ephy>;
- phy-mode = "rmii";
-};
-
-&hdmi_tx {
- status = "okay";
- pinctrl-0 = <&hdmitx_hpd_pins>, <&hdmitx_ddc_pins>;
- pinctrl-names = "default";
- hdmi-supply = <&vcc_5v>;
-};
-
-&hdmi_tx_tmds_port {
- hdmi_tx_tmds_out: endpoint {
- remote-endpoint = <&hdmi_connector_in>;
- };
-};
-
-&ir {
- status = "okay";
- pinctrl-0 = <&remote_input_ao_pins>;
- pinctrl-names = "default";
-};
-
-/* i2c Touch */
-&i2c0 {
- status = "okay";
- pinctrl-0 = <&i2c0_sda_z0_pins>, <&i2c0_sck_z1_pins>;
- pinctrl-names = "default";
-};
-
-/* i2c CM */
-&i2c2 {
- status = "okay";
- pinctrl-0 = <&i2c2_sda_z_pins>, <&i2c2_sck_z_pins>;
- pinctrl-names = "default";
-};
-
-/* i2c Audio */
-&i2c3 {
- status = "okay";
- pinctrl-0 = <&i2c3_sda_a_pins>, <&i2c3_sck_a_pins>;
- pinctrl-names = "default";
-};
-
-&pwm_AO_cd {
- pinctrl-0 = <&pwm_ao_d_e_pins>;
- pinctrl-names = "default";
- clocks = <&xtal>;
- clock-names = "clkin1";
- status = "okay";
-};
-
-/* SD card */
-&sd_emmc_b {
- status = "okay";
- pinctrl-0 = <&sdcard_c_pins>;
- pinctrl-1 = <&sdcard_clk_gate_c_pins>;
- pinctrl-names = "default", "clk-gate";
-
- bus-width = <4>;
- cap-sd-highspeed;
- max-frequency = <50000000>;
- disable-wp;
-
- cd-gpios = <&gpio GPIOC_6 GPIO_ACTIVE_LOW>;
- vmmc-supply = <&vddao_3v3>;
- vqmmc-supply = <&vddao_3v3>;
-};
-
-/* eMMC */
-&sd_emmc_c {
- status = "okay";
- pinctrl-0 = <&emmc_ctrl_pins>, <&emmc_data_8b_pins>, <&emmc_ds_pins>;
- pinctrl-1 = <&emmc_clk_gate_pins>;
- pinctrl-names = "default", "clk-gate";
-
- bus-width = <8>;
- cap-mmc-highspeed;
- mmc-ddr-1_8v;
- mmc-hs200-1_8v;
- max-frequency = <200000000>;
- non-removable;
- disable-wp;
-
- mmc-pwrseq = <&emmc_pwrseq>;
- vmmc-supply = <&vcc_3v3>;
- vqmmc-supply = <&flash_1v8>;
-};
-
-&uart_AO {
- status = "okay";
- pinctrl-0 = <&uart_ao_a_pins>;
- pinctrl-names = "default";
-};
-
-&usb {
- status = "okay";
- vbus-supply = <&usb_pwr_en>;
-};
-
-&usb2_phy0 {
- phy-supply = <&vcc_5v>;
-};
-
-&usb2_phy1 {
- phy-supply = <&vcc_5v>;
-};
diff --git a/arch/arm/dts/meson-g12a.dtsi b/arch/arm/dts/meson-g12a.dtsi
deleted file mode 100644
index 7677764..0000000
--- a/arch/arm/dts/meson-g12a.dtsi
+++ /dev/null
@@ -1,140 +0,0 @@
-// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
-/*
- * Copyright (c) 2018 Amlogic, Inc. All rights reserved.
- */
-
-#include "meson-g12.dtsi"
-
-/ {
- compatible = "amlogic,g12a";
-
- cpus {
- #address-cells = <0x2>;
- #size-cells = <0x0>;
-
- cpu0: cpu@0 {
- device_type = "cpu";
- compatible = "arm,cortex-a53";
- reg = <0x0 0x0>;
- enable-method = "psci";
- next-level-cache = <&l2>;
- #cooling-cells = <2>;
- };
-
- cpu1: cpu@1 {
- device_type = "cpu";
- compatible = "arm,cortex-a53";
- reg = <0x0 0x1>;
- enable-method = "psci";
- next-level-cache = <&l2>;
- #cooling-cells = <2>;
- };
-
- cpu2: cpu@2 {
- device_type = "cpu";
- compatible = "arm,cortex-a53";
- reg = <0x0 0x2>;
- enable-method = "psci";
- next-level-cache = <&l2>;
- #cooling-cells = <2>;
- };
-
- cpu3: cpu@3 {
- device_type = "cpu";
- compatible = "arm,cortex-a53";
- reg = <0x0 0x3>;
- enable-method = "psci";
- next-level-cache = <&l2>;
- #cooling-cells = <2>;
- };
-
- l2: l2-cache0 {
- compatible = "cache";
- cache-level = <2>;
- };
- };
-
- cpu_opp_table: opp-table {
- compatible = "operating-points-v2";
- opp-shared;
-
- opp-100000000 {
- opp-hz = /bits/ 64 <100000000>;
- opp-microvolt = <731000>;
- };
-
- opp-250000000 {
- opp-hz = /bits/ 64 <250000000>;
- opp-microvolt = <731000>;
- };
-
- opp-500000000 {
- opp-hz = /bits/ 64 <500000000>;
- opp-microvolt = <731000>;
- };
-
- opp-667000000 {
- opp-hz = /bits/ 64 <666666666>;
- opp-microvolt = <731000>;
- };
-
- opp-1000000000 {
- opp-hz = /bits/ 64 <1000000000>;
- opp-microvolt = <731000>;
- };
-
- opp-1200000000 {
- opp-hz = /bits/ 64 <1200000000>;
- opp-microvolt = <731000>;
- };
-
- opp-1398000000 {
- opp-hz = /bits/ 64 <1398000000>;
- opp-microvolt = <761000>;
- };
-
- opp-1512000000 {
- opp-hz = /bits/ 64 <1512000000>;
- opp-microvolt = <791000>;
- };
-
- opp-1608000000 {
- opp-hz = /bits/ 64 <1608000000>;
- opp-microvolt = <831000>;
- };
-
- opp-1704000000 {
- opp-hz = /bits/ 64 <1704000000>;
- opp-microvolt = <861000>;
- };
-
- opp-1800000000 {
- opp-hz = /bits/ 64 <1800000000>;
- opp-microvolt = <981000>;
- };
- };
-};
-
-&cpu_thermal {
- cooling-maps {
- map0 {
- trip = <&cpu_passive>;
- cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
- <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
- <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
- <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
- };
-
- map1 {
- trip = <&cpu_hot>;
- cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
- <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
- <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
- <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
- };
- };
-};
-
-&pmu {
- compatible = "amlogic,g12a-ddr-pmu";
-};
diff --git a/arch/arm/dts/meson-g12b-a311d-bananapi-m2s.dts b/arch/arm/dts/meson-g12b-a311d-bananapi-m2s.dts
deleted file mode 100644
index 3136531..0000000
--- a/arch/arm/dts/meson-g12b-a311d-bananapi-m2s.dts
+++ /dev/null
@@ -1,33 +0,0 @@
-// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
-/*
- * Copyright (c) 2023 Christian Hewitt <christianshewitt@gmail.com>
- */
-
-/dts-v1/;
-
-#include "meson-g12b-a311d.dtsi"
-#include "meson-g12b-bananapi.dtsi"
-
-/ {
- compatible = "bananapi,bpi-m2s", "amlogic,a311d", "amlogic,g12b";
- model = "BananaPi M2S";
-
- aliases {
- i2c0 = &i2c1;
- i2c1 = &i2c3;
- };
-};
-
-/* Camera (CSI) bus */
-&i2c1 {
- status = "okay";
- pinctrl-0 = <&i2c1_sda_h6_pins>, <&i2c1_sck_h7_pins>;
- pinctrl-names = "default";
-};
-
-/* Display (DSI) bus */
-&i2c3 {
- status = "okay";
- pinctrl-0 = <&i2c3_sda_a_pins>, <&i2c3_sck_a_pins>;
- pinctrl-names = "default";
-};
diff --git a/arch/arm/dts/meson-g12b-a311d-khadas-vim3.dts b/arch/arm/dts/meson-g12b-a311d-khadas-vim3.dts
deleted file mode 100644
index 124a809..0000000
--- a/arch/arm/dts/meson-g12b-a311d-khadas-vim3.dts
+++ /dev/null
@@ -1,41 +0,0 @@
-// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
-/*
- * Copyright (c) 2019 BayLibre, SAS
- * Author: Neil Armstrong <narmstrong@baylibre.com>
- * Copyright (c) 2019 Christian Hewitt <christianshewitt@gmail.com>
- */
-
-/dts-v1/;
-
-#include "meson-g12b-a311d.dtsi"
-#include "meson-khadas-vim3.dtsi"
-#include "meson-g12b-khadas-vim3.dtsi"
-
-/ {
- compatible = "khadas,vim3", "amlogic,a311d", "amlogic,g12b";
-};
-
-/*
- * The VIM3 on-board MCU can mux the PCIe/USB3.0 shared differential
- * lines using a FUSB340TMX USB 3.1 SuperSpeed Data Switch between
- * an USB3.0 Type A connector and a M.2 Key M slot.
- * The PHY driving these differential lines is shared between
- * the USB3.0 controller and the PCIe Controller, thus only
- * a single controller can use it.
- * If the MCU is configured to mux the PCIe/USB3.0 differential lines
- * to the M.2 Key M slot, uncomment the following block to disable
- * USB3.0 from the USB Complex and enable the PCIe controller.
- * The End User is not expected to uncomment the following except for
- * testing purposes, but instead rely on the firmware/bootloader to
- * update these nodes accordingly if PCIe mode is selected by the MCU.
- */
-/*
-&pcie {
- status = "okay";
-};
-
-&usb {
- phys = <&usb2_phy0>, <&usb2_phy1>;
- phy-names = "usb2-phy0", "usb2-phy1";
-};
- */
diff --git a/arch/arm/dts/meson-g12b-a311d.dtsi b/arch/arm/dts/meson-g12b-a311d.dtsi
deleted file mode 100644
index d61f430..0000000
--- a/arch/arm/dts/meson-g12b-a311d.dtsi
+++ /dev/null
@@ -1,149 +0,0 @@
-// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
-/*
- * Copyright (c) 2019 BayLibre, SAS
- * Author: Neil Armstrong <narmstrong@baylibre.com>
- */
-
-#include "meson-g12b.dtsi"
-
-/ {
- cpu_opp_table_0: opp-table-0 {
- compatible = "operating-points-v2";
- opp-shared;
-
- opp-100000000 {
- opp-hz = /bits/ 64 <100000000>;
- opp-microvolt = <731000>;
- };
-
- opp-250000000 {
- opp-hz = /bits/ 64 <250000000>;
- opp-microvolt = <731000>;
- };
-
- opp-500000000 {
- opp-hz = /bits/ 64 <500000000>;
- opp-microvolt = <731000>;
- };
-
- opp-667000000 {
- opp-hz = /bits/ 64 <667000000>;
- opp-microvolt = <731000>;
- };
-
- opp-1000000000 {
- opp-hz = /bits/ 64 <1000000000>;
- opp-microvolt = <761000>;
- };
-
- opp-1200000000 {
- opp-hz = /bits/ 64 <1200000000>;
- opp-microvolt = <781000>;
- };
-
- opp-1398000000 {
- opp-hz = /bits/ 64 <1398000000>;
- opp-microvolt = <811000>;
- };
-
- opp-1512000000 {
- opp-hz = /bits/ 64 <1512000000>;
- opp-microvolt = <861000>;
- };
-
- opp-1608000000 {
- opp-hz = /bits/ 64 <1608000000>;
- opp-microvolt = <901000>;
- };
-
- opp-1704000000 {
- opp-hz = /bits/ 64 <1704000000>;
- opp-microvolt = <951000>;
- };
-
- opp-1800000000 {
- opp-hz = /bits/ 64 <1800000000>;
- opp-microvolt = <1001000>;
- };
- };
-
- cpub_opp_table_1: opp-table-1 {
- compatible = "operating-points-v2";
- opp-shared;
-
- opp-100000000 {
- opp-hz = /bits/ 64 <100000000>;
- opp-microvolt = <731000>;
- };
-
- opp-250000000 {
- opp-hz = /bits/ 64 <250000000>;
- opp-microvolt = <731000>;
- };
-
- opp-500000000 {
- opp-hz = /bits/ 64 <500000000>;
- opp-microvolt = <731000>;
- };
-
- opp-667000000 {
- opp-hz = /bits/ 64 <667000000>;
- opp-microvolt = <731000>;
- };
-
- opp-1000000000 {
- opp-hz = /bits/ 64 <1000000000>;
- opp-microvolt = <731000>;
- };
-
- opp-1200000000 {
- opp-hz = /bits/ 64 <1200000000>;
- opp-microvolt = <751000>;
- };
-
- opp-1398000000 {
- opp-hz = /bits/ 64 <1398000000>;
- opp-microvolt = <771000>;
- };
-
- opp-1512000000 {
- opp-hz = /bits/ 64 <1512000000>;
- opp-microvolt = <771000>;
- };
-
- opp-1608000000 {
- opp-hz = /bits/ 64 <1608000000>;
- opp-microvolt = <781000>;
- };
-
- opp-1704000000 {
- opp-hz = /bits/ 64 <1704000000>;
- opp-microvolt = <791000>;
- };
-
- opp-1800000000 {
- opp-hz = /bits/ 64 <1800000000>;
- opp-microvolt = <831000>;
- };
-
- opp-1908000000 {
- opp-hz = /bits/ 64 <1908000000>;
- opp-microvolt = <861000>;
- };
-
- opp-2016000000 {
- opp-hz = /bits/ 64 <2016000000>;
- opp-microvolt = <911000>;
- };
-
- opp-2108000000 {
- opp-hz = /bits/ 64 <2108000000>;
- opp-microvolt = <951000>;
- };
-
- opp-2208000000 {
- opp-hz = /bits/ 64 <2208000000>;
- opp-microvolt = <1011000>;
- };
- };
-};
diff --git a/arch/arm/dts/meson-g12b-bananapi-cm4-cm4io.dts b/arch/arm/dts/meson-g12b-bananapi-cm4-cm4io.dts
deleted file mode 100644
index 1b0c388..0000000
--- a/arch/arm/dts/meson-g12b-bananapi-cm4-cm4io.dts
+++ /dev/null
@@ -1,165 +0,0 @@
-// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
-/*
- * Copyright (c) 2023 Neil Armstrong <neil.armstrong@linaro.org>
- */
-
-/dts-v1/;
-
-#include "meson-g12b-bananapi-cm4.dtsi"
-#include <dt-bindings/input/input.h>
-#include <dt-bindings/leds/common.h>
-#include <dt-bindings/sound/meson-g12a-tohdmitx.h>
-
-/ {
- compatible = "bananapi,bpi-cm4io", "bananapi,bpi-cm4", "amlogic,a311d", "amlogic,g12b";
- model = "BananaPi BPI-CM4IO Baseboard with BPI-CM4 Module";
-
- aliases {
- ethernet0 = ðmac;
- i2c0 = &i2c1;
- i2c1 = &i2c3;
- };
-
- adc-keys {
- compatible = "adc-keys";
- io-channels = <&saradc 2>;
- io-channel-names = "buttons";
- keyup-threshold-microvolt = <1710000>;
-
- button-function {
- label = "Function";
- linux,code = <KEY_FN>;
- press-threshold-microvolt = <10000>;
- };
- };
-
- hdmi_connector: hdmi-connector {
- compatible = "hdmi-connector";
- type = "a";
-
- port {
- hdmi_connector_in: endpoint {
- remote-endpoint = <&hdmi_tx_tmds_out>;
- };
- };
- };
-
- leds {
- compatible = "gpio-leds";
-
- led-blue {
- color = <LED_COLOR_ID_BLUE>;
- function = LED_FUNCTION_STATUS;
- gpios = <&gpio_ao GPIOAO_7 GPIO_ACTIVE_HIGH>;
- linux,default-trigger = "heartbeat";
- };
-
- led-green {
- color = <LED_COLOR_ID_GREEN>;
- function = LED_FUNCTION_STATUS;
- gpios = <&gpio_ao GPIOAO_2 GPIO_ACTIVE_HIGH>;
- };
- };
-
- sound {
- compatible = "amlogic,axg-sound-card";
- model = "BPI-CM4IO";
- audio-aux-devs = <&tdmout_b>;
- audio-routing = "TDMOUT_B IN 0", "FRDDR_A OUT 1",
- "TDMOUT_B IN 1", "FRDDR_B OUT 1",
- "TDMOUT_B IN 2", "FRDDR_C OUT 1",
- "TDM_B Playback", "TDMOUT_B OUT";
-
- assigned-clocks = <&clkc CLKID_MPLL2>,
- <&clkc CLKID_MPLL0>,
- <&clkc CLKID_MPLL1>;
- assigned-clock-parents = <0>, <0>, <0>;
- assigned-clock-rates = <294912000>,
- <270950400>,
- <393216000>;
-
- dai-link-0 {
- sound-dai = <&frddr_a>;
- };
-
- dai-link-1 {
- sound-dai = <&frddr_b>;
- };
-
- dai-link-2 {
- sound-dai = <&frddr_c>;
- };
-
- /* 8ch hdmi interface */
- dai-link-3 {
- sound-dai = <&tdmif_b>;
- dai-format = "i2s";
- dai-tdm-slot-tx-mask-0 = <1 1>;
- dai-tdm-slot-tx-mask-1 = <1 1>;
- dai-tdm-slot-tx-mask-2 = <1 1>;
- dai-tdm-slot-tx-mask-3 = <1 1>;
- mclk-fs = <256>;
-
- codec {
- sound-dai = <&tohdmitx TOHDMITX_I2S_IN_B>;
- };
- };
-
- /* hdmi glue */
- dai-link-4 {
- sound-dai = <&tohdmitx TOHDMITX_I2S_OUT>;
-
- codec {
- sound-dai = <&hdmi_tx>;
- };
- };
- };
-};
-
-&cecb_AO {
- status = "okay";
-};
-
-ðmac {
- status = "okay";
-};
-
-&hdmi_tx {
- status = "okay";
-};
-
-&hdmi_tx_tmds_port {
- hdmi_tx_tmds_out: endpoint {
- remote-endpoint = <&hdmi_connector_in>;
- };
-};
-
-/* CSI port */
-&i2c1 {
- status = "okay";
-};
-
-/* DSI port for touchscreen */
-&i2c3 {
- status = "okay";
-};
-
-/* miniPCIe port with USB + SIM slot */
-&pcie {
- status = "okay";
-};
-
-&sd_emmc_b {
- status = "okay";
-};
-
-&tohdmitx {
- status = "okay";
-};
-
-/* Peripheral Only USB-C port */
-&usb {
- dr_mode = "peripheral";
-
- status = "okay";
-};
diff --git a/arch/arm/dts/meson-g12b-bananapi-cm4.dtsi b/arch/arm/dts/meson-g12b-bananapi-cm4.dtsi
deleted file mode 100644
index 97e5229..0000000
--- a/arch/arm/dts/meson-g12b-bananapi-cm4.dtsi
+++ /dev/null
@@ -1,388 +0,0 @@
-// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
-/*
- * Copyright (c) 2023 Neil Armstrong <neil.armstrong@linaro.org>
- */
-
-#include "meson-g12b-a311d.dtsi"
-#include <dt-bindings/gpio/meson-g12a-gpio.h>
-
-/ {
- aliases {
- serial0 = &uart_AO;
- rtc1 = &vrtc;
- };
-
- chosen {
- stdout-path = "serial0:115200n8";
- };
-
- emmc_pwrseq: emmc-pwrseq {
- compatible = "mmc-pwrseq-emmc";
- reset-gpios = <&gpio BOOT_12 GPIO_ACTIVE_LOW>;
- };
-
- memory@0 {
- device_type = "memory";
- reg = <0x0 0x0 0x0 0x40000000>;
- };
-
- sdio_pwrseq: sdio-pwrseq {
- compatible = "mmc-pwrseq-simple";
- reset-gpios = <&gpio GPIOAO_6 GPIO_ACTIVE_LOW>;
- clocks = <&wifi32k>;
- clock-names = "ext_clock";
- };
-
- emmc_1v8: regulator-emmc-1v8 {
- compatible = "regulator-fixed";
- regulator-name = "EMMC_1V8";
- regulator-min-microvolt = <1800000>;
- regulator-max-microvolt = <1800000>;
- vin-supply = <&vddao_3v3>;
- regulator-always-on;
- };
-
- dc_in: regulator-dc-in {
- compatible = "regulator-fixed";
- regulator-name = "DC_IN";
- regulator-min-microvolt = <5000000>;
- regulator-max-microvolt = <5000000>;
- regulator-always-on;
- };
-
- vddio_c: regulator-vddio-c {
- compatible = "regulator-gpio";
- regulator-name = "VDDIO_C";
- regulator-min-microvolt = <1800000>;
- regulator-max-microvolt = <3300000>;
-
- enable-gpio = <&gpio_ao GPIOAO_3 GPIO_OPEN_DRAIN>;
- enable-active-high;
- regulator-always-on;
-
- gpios = <&gpio_ao GPIOAO_9 GPIO_OPEN_DRAIN>;
- gpios-states = <1>;
-
- states = <1800000 0>,
- <3300000 1>;
- };
-
- vddao_1v8: regulator-vddao-1v8 {
- compatible = "regulator-fixed";
- regulator-name = "VDDAO_1V8";
- regulator-min-microvolt = <1800000>;
- regulator-max-microvolt = <1800000>;
- vin-supply = <&vddao_3v3>;
- regulator-always-on;
- };
-
- vddao_3v3: regulator-vddao-3v3 {
- compatible = "regulator-fixed";
- regulator-name = "VDDAO_3V3";
- regulator-min-microvolt = <3300000>;
- regulator-max-microvolt = <3300000>;
- vin-supply = <&dc_in>;
- regulator-always-on;
- };
-
- vddcpu_a: regulator-vddcpu-a {
- /*
- * MP8756GD DC/DC Regulator.
- */
- compatible = "pwm-regulator";
-
- regulator-name = "VDDCPU_A";
- regulator-min-microvolt = <680000>;
- regulator-max-microvolt = <1040000>;
-
- pwm-supply = <&dc_in>;
-
- pwms = <&pwm_ab 0 1250 0>;
- pwm-dutycycle-range = <100 0>;
-
- regulator-boot-on;
- regulator-always-on;
- };
-
- vddcpu_b: regulator-vddcpu-b {
- /*
- * SY8120B1ABC DC/DC Regulator.
- */
- compatible = "pwm-regulator";
-
- regulator-name = "VDDCPU_B";
- regulator-min-microvolt = <680000>;
- regulator-max-microvolt = <1040000>;
-
- pwm-supply = <&dc_in>;
-
- pwms = <&pwm_AO_cd 1 1250 0>;
- pwm-dutycycle-range = <100 0>;
-
- regulator-boot-on;
- regulator-always-on;
- };
-
- wifi32k: wifi32k {
- compatible = "pwm-clock";
- #clock-cells = <0>;
- clock-frequency = <32768>;
- pwms = <&pwm_ef 0 30518 0>; /* PWM_E at 32.768KHz */
- };
-};
-
-&arb {
- status = "okay";
-};
-
-&clkc_audio {
- status = "okay";
-};
-
-&cec_AO {
- pinctrl-0 = <&cec_ao_a_h_pins>;
- pinctrl-names = "default";
- hdmi-phandle = <&hdmi_tx>;
-};
-
-&cecb_AO {
- pinctrl-0 = <&cec_ao_b_h_pins>;
- pinctrl-names = "default";
- hdmi-phandle = <&hdmi_tx>;
-};
-
-&cpu0 {
- cpu-supply = <&vddcpu_b>;
- operating-points-v2 = <&cpu_opp_table_0>;
- clocks = <&clkc CLKID_CPU_CLK>;
- clock-latency = <50000>;
-};
-
-&cpu1 {
- cpu-supply = <&vddcpu_b>;
- operating-points-v2 = <&cpu_opp_table_0>;
- clocks = <&clkc CLKID_CPU_CLK>;
- clock-latency = <50000>;
-};
-
-&cpu100 {
- cpu-supply = <&vddcpu_a>;
- operating-points-v2 = <&cpub_opp_table_1>;
- clocks = <&clkc CLKID_CPUB_CLK>;
- clock-latency = <50000>;
-};
-
-&cpu101 {
- cpu-supply = <&vddcpu_a>;
- operating-points-v2 = <&cpub_opp_table_1>;
- clocks = <&clkc CLKID_CPUB_CLK>;
- clock-latency = <50000>;
-};
-
-&cpu102 {
- cpu-supply = <&vddcpu_a>;
- operating-points-v2 = <&cpub_opp_table_1>;
- clocks = <&clkc CLKID_CPUB_CLK>;
- clock-latency = <50000>;
-};
-
-&cpu103 {
- cpu-supply = <&vddcpu_a>;
- operating-points-v2 = <&cpub_opp_table_1>;
- clocks = <&clkc CLKID_CPUB_CLK>;
- clock-latency = <50000>;
-};
-
-&ext_mdio {
- external_phy: ethernet-phy@0 {
- /* Realtek RTL8211F (0x001cc916) */
- reg = <0>;
- max-speed = <1000>;
-
- interrupt-parent = <&gpio_intc>;
- /* MAC_INTR on GPIOZ_14 */
- interrupts = <26 IRQ_TYPE_LEVEL_LOW>;
- };
-};
-
-/* Ethernet to be enabled in baseboard DT */
-ðmac {
- pinctrl-0 = <ð_pins>, <ð_rgmii_pins>;
- pinctrl-names = "default";
- phy-mode = "rgmii-txid";
- phy-handle = <&external_phy>;
-};
-
-&frddr_a {
- status = "okay";
-};
-
-&frddr_b {
- status = "okay";
-};
-
-&frddr_c {
- status = "okay";
-};
-
-/* HDMI to be enabled in baseboard DT */
-&hdmi_tx {
- pinctrl-0 = <&hdmitx_hpd_pins>, <&hdmitx_ddc_pins>;
- pinctrl-names = "default";
- hdmi-supply = <&dc_in>;
-};
-
-/* "Camera" I2C bus */
-&i2c1 {
- pinctrl-0 = <&i2c1_sda_h6_pins>, <&i2c1_sck_h7_pins>;
- pinctrl-names = "default";
-};
-
-/* Main I2C bus */
-&i2c2 {
- pinctrl-0 = <&i2c2_sda_x_pins>, <&i2c2_sck_x_pins>;
- pinctrl-names = "default";
-};
-
-/* "ID" I2C bus */
-&i2c3 {
- pinctrl-0 = <&i2c3_sda_a_pins>, <&i2c3_sck_a_pins>;
- pinctrl-names = "default";
-};
-
-&pcie {
- reset-gpios = <&gpio GPIOA_8 GPIO_ACTIVE_LOW>;
-};
-
-&pwm_ab {
- pinctrl-0 = <&pwm_a_e_pins>;
- pinctrl-names = "default";
- clocks = <&xtal>;
- clock-names = "clkin0";
-
- status = "okay";
-};
-
-&pwm_ef {
- pinctrl-0 = <&pwm_e_pins>;
- pinctrl-names = "default";
-
- status = "okay";
-};
-
-&pwm_AO_cd {
- pinctrl-0 = <&pwm_ao_d_e_pins>;
- pinctrl-names = "default";
- clocks = <&xtal>;
- clock-names = "clkin1";
-
- status = "okay";
-};
-
-&saradc {
- vref-supply = <&vddao_1v8>;
-
- status = "okay";
-};
-
-/* on-module SDIO WiFi */
-&sd_emmc_a {
- pinctrl-0 = <&sdio_pins>;
- pinctrl-1 = <&sdio_clk_gate_pins>;
- pinctrl-names = "default", "clk-gate";
- #address-cells = <1>;
- #size-cells = <0>;
-
- bus-width = <4>;
- sd-uhs-sdr104;
- max-frequency = <50000000>;
-
- non-removable;
- disable-wp;
-
- /* WiFi firmware requires power in suspend */
- keep-power-in-suspend;
-
- mmc-pwrseq = <&sdio_pwrseq>;
-
- vmmc-supply = <&vddao_3v3>;
- vqmmc-supply = <&vddao_3v3>;
-
- status = "okay";
-
- rtl8822cs: wifi@1 {
- reg = <1>;
- };
-};
-
-/* SD card to be enabled in baseboard DT */
-&sd_emmc_b {
- pinctrl-0 = <&sdcard_c_pins>;
- pinctrl-1 = <&sdcard_clk_gate_c_pins>;
- pinctrl-names = "default", "clk-gate";
-
- bus-width = <4>;
- cap-sd-highspeed;
- max-frequency = <50000000>;
- disable-wp;
-
- cd-gpios = <&gpio GPIOC_6 GPIO_ACTIVE_LOW>;
- vmmc-supply = <&vddao_3v3>;
- vqmmc-supply = <&vddio_c>;
-};
-
-/* on-module eMMC */
-&sd_emmc_c {
- pinctrl-0 = <&emmc_ctrl_pins>, <&emmc_data_8b_pins>, <&emmc_ds_pins>;
- pinctrl-1 = <&emmc_clk_gate_pins>;
- pinctrl-names = "default", "clk-gate";
-
- bus-width = <8>;
- cap-mmc-highspeed;
- mmc-ddr-1_8v;
- mmc-hs200-1_8v;
- max-frequency = <200000000>;
- disable-wp;
-
- mmc-pwrseq = <&emmc_pwrseq>;
- vmmc-supply = <&vddao_3v3>;
- vqmmc-supply = <&vddao_1v8>;
-
- status = "okay";
-};
-
-&tdmif_b {
- status = "okay";
-};
-
-&tdmout_b {
- status = "okay";
-};
-
-/* on-module UART BT */
-&uart_A {
- pinctrl-0 = <&uart_a_pins>, <&uart_a_cts_rts_pins>;
- pinctrl-names = "default";
- uart-has-rtscts;
-
- status = "okay";
-
- bluetooth {
- compatible = "realtek,rtl8822cs-bt";
- enable-gpios = <&gpio GPIOX_17 GPIO_ACTIVE_HIGH>;
- host-wake-gpios = <&gpio GPIOX_19 GPIO_ACTIVE_HIGH>;
- device-wake-gpios = <&gpio GPIOX_18 GPIO_ACTIVE_HIGH>;
- };
-};
-
-&uart_AO {
- pinctrl-0 = <&uart_ao_a_pins>;
- pinctrl-names = "default";
-
- status = "okay";
-};
-
-&usb {
- phys = <&usb2_phy0>, <&usb2_phy1>;
- phy-names = "usb2-phy0", "usb2-phy1";
-};
diff --git a/arch/arm/dts/meson-g12b-bananapi.dtsi b/arch/arm/dts/meson-g12b-bananapi.dtsi
deleted file mode 100644
index 83709787..0000000
--- a/arch/arm/dts/meson-g12b-bananapi.dtsi
+++ /dev/null
@@ -1,521 +0,0 @@
-// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
-/*
- * Copyright (c) 2019 BayLibre, SAS
- * Author: Neil Armstrong <narmstrong@baylibre.com>
- * Copyright (c) 2023 Christian Hewitt <christianshewitt@gmail.com>
- */
-
-#include <dt-bindings/input/input.h>
-#include <dt-bindings/leds/common.h>
-#include <dt-bindings/gpio/meson-g12a-gpio.h>
-#include <dt-bindings/sound/meson-g12a-tohdmitx.h>
-
-/ {
- aliases {
- serial0 = &uart_AO;
- ethernet0 = ðmac;
- rtc1 = &vrtc;
- };
-
- chosen {
- stdout-path = "serial0:115200n8";
- };
-
- memory@0 {
- device_type = "memory";
- reg = <0x0 0x0 0x0 0x80000000>; /* 2 GiB or 4 GiB */
- };
-
- adc-keys {
- compatible = "adc-keys";
- io-channels = <&saradc 2>;
- io-channel-names = "buttons";
- keyup-threshold-microvolt = <1710000>;
-
- button-function {
- label = "RST";
- linux,code = <KEY_POWER>;
- press-threshold-microvolt = <10000>;
- };
- };
-
- emmc_pwrseq: emmc-pwrseq {
- compatible = "mmc-pwrseq-emmc";
- reset-gpios = <&gpio BOOT_12 GPIO_ACTIVE_LOW>;
- };
-
- fan0: pwm-fan {
- compatible = "pwm-fan";
- #cooling-cells = <2>;
- cooling-min-state = <0>;
- cooling-max-state = <3>;
- cooling-levels = <0 120 170 220>;
- pwms = <&pwm_cd 1 40000 0>;
- };
-
- hdmi-connector {
- compatible = "hdmi-connector";
- type = "a";
-
- port {
- hdmi_connector_in: endpoint {
- remote-endpoint = <&hdmi_tx_tmds_out>;
- };
- };
- };
-
- leds {
- compatible = "gpio-leds";
-
- led-0 {
- color = <LED_COLOR_ID_BLUE>;
- function = LED_FUNCTION_STATUS;
- gpios = <&gpio_ao GPIOAO_7 GPIO_ACTIVE_LOW>;
- linux,default-trigger = "heartbeat";
- };
-
- led-1 {
- color = <LED_COLOR_ID_GREEN>;
- function = LED_FUNCTION_STATUS;
- gpios = <&gpio_ao GPIOAO_2 GPIO_ACTIVE_LOW>;
- };
- };
-
- sdio_pwrseq: sdio-pwrseq {
- compatible = "mmc-pwrseq-simple";
- reset-gpios = <&gpio GPIOX_6 GPIO_ACTIVE_LOW>;
- clocks = <&wifi32k>;
- clock-names = "ext_clock";
- };
-
- wifi32k: wifi32k {
- compatible = "pwm-clock";
- #clock-cells = <0>;
- clock-frequency = <32768>;
- pwms = <&pwm_ef 0 30518 0>; /* PWM_E at 32.768KHz */
- };
-
- dc_in: regulator-dc-in {
- compatible = "regulator-fixed";
- regulator-name = "DC_IN";
- regulator-min-microvolt = <5000000>;
- regulator-max-microvolt = <5000000>;
- regulator-always-on;
- };
-
- vcc_5v: regulator-vcc-5v {
- compatible = "regulator-fixed";
- regulator-name = "VCC_5V";
- regulator-min-microvolt = <5000000>;
- regulator-max-microvolt = <5000000>;
- vin-supply = <&dc_in>;
-
- gpio = <&gpio GPIOH_8 GPIO_OPEN_DRAIN>;
- enable-active-high;
- };
-
- vcc_3v3: regulator-vcc-3v3 {
- compatible = "regulator-fixed";
- regulator-name = "VCC_3V3";
- regulator-min-microvolt = <3300000>;
- regulator-max-microvolt = <3300000>;
- vin-supply = <&vsys_3v3>;
- regulator-always-on;
- };
-
- vcc_1v8: regulator-vcc-1v8 {
- compatible = "regulator-fixed";
- regulator-name = "VCC_1V8";
- regulator-min-microvolt = <1800000>;
- regulator-max-microvolt = <1800000>;
- vin-supply = <&vcc_3v3>;
- regulator-always-on;
- };
-
- vddao_1v8: regulator-vddao-1v8 {
- compatible = "regulator-fixed";
- regulator-name = "VDDIO_AO1V8";
- regulator-min-microvolt = <1800000>;
- regulator-max-microvolt = <1800000>;
- vin-supply = <&vsys_3v3>;
- regulator-always-on;
- };
-
- vddcpu_a: regulator-vddcpu-a {
- compatible = "pwm-regulator";
- regulator-name = "VDDCPU_A";
- regulator-min-microvolt = <690000>;
- regulator-max-microvolt = <1050000>;
- pwm-supply = <&dc_in>;
- pwms = <&pwm_ab 0 1250 0>;
- pwm-dutycycle-range = <100 0>;
- regulator-boot-on;
- regulator-always-on;
- };
-
- vddcpu_b: regulator-vddcpu-b {
- compatible = "pwm-regulator";
- regulator-name = "VDDCPU_B";
- regulator-min-microvolt = <690000>;
- regulator-max-microvolt = <1050000>;
- pwm-supply = <&vsys_3v3>;
- pwms = <&pwm_AO_cd 1 1250 0>;
- pwm-dutycycle-range = <100 0>;
- regulator-boot-on;
- regulator-always-on;
- };
-
- vsys_3v3: regulator-vsys-3v3 {
- compatible = "regulator-fixed";
- regulator-name = "VSYS_3V3";
- regulator-min-microvolt = <3300000>;
- regulator-max-microvolt = <3300000>;
- vin-supply = <&dc_in>;
- regulator-always-on;
- };
-
- emmc_1v8: regulator-emmc-1v8 {
- compatible = "regulator-fixed";
- regulator-name = "EMMC_AO1V8";
- regulator-min-microvolt = <1800000>;
- regulator-max-microvolt = <1800000>;
- vin-supply = <&vcc_3v3>;
- regulator-always-on;
- };
-
- usb_pwr: regulator-usb-pwr {
- compatible = "regulator-fixed";
- regulator-name = "USB_PWR";
- regulator-min-microvolt = <5000000>;
- regulator-max-microvolt = <5000000>;
- vin-supply = <&vcc_5v>;
-
- gpio = <&gpio GPIOA_6 GPIO_ACTIVE_HIGH>;
- enable-active-high;
- };
-
- sound {
- compatible = "amlogic,axg-sound-card";
- model = "BPI-M2S";
- audio-aux-devs = <&tdmout_b>;
- audio-routing = "TDMOUT_B IN 0", "FRDDR_A OUT 1",
- "TDMOUT_B IN 1", "FRDDR_B OUT 1",
- "TDMOUT_B IN 2", "FRDDR_C OUT 1",
- "TDM_B Playback", "TDMOUT_B OUT";
-
- assigned-clocks = <&clkc CLKID_MPLL2>,
- <&clkc CLKID_MPLL0>,
- <&clkc CLKID_MPLL1>;
- assigned-clock-parents = <0>, <0>, <0>;
- assigned-clock-rates = <294912000>,
- <270950400>,
- <393216000>;
-
- dai-link-0 {
- sound-dai = <&frddr_a>;
- };
-
- dai-link-1 {
- sound-dai = <&frddr_b>;
- };
-
- dai-link-2 {
- sound-dai = <&frddr_c>;
- };
-
- /* 8ch hdmi interface */
- dai-link-3 {
- sound-dai = <&tdmif_b>;
- dai-format = "i2s";
- dai-tdm-slot-tx-mask-0 = <1 1>;
- dai-tdm-slot-tx-mask-1 = <1 1>;
- dai-tdm-slot-tx-mask-2 = <1 1>;
- dai-tdm-slot-tx-mask-3 = <1 1>;
- mclk-fs = <256>;
-
- codec {
- sound-dai = <&tohdmitx TOHDMITX_I2S_IN_B>;
- };
- };
-
- /* hdmi glue */
- dai-link-4 {
- sound-dai = <&tohdmitx TOHDMITX_I2S_OUT>;
-
- codec {
- sound-dai = <&hdmi_tx>;
- };
- };
- };
-};
-
-&arb {
- status = "okay";
-};
-
-&clkc_audio {
- status = "okay";
-};
-
-&cecb_AO {
- pinctrl-0 = <&cec_ao_b_h_pins>;
- pinctrl-names = "default";
- status = "okay";
- hdmi-phandle = <&hdmi_tx>;
-};
-
-&cpu0 {
- cpu-supply = <&vddcpu_b>;
- operating-points-v2 = <&cpu_opp_table_0>;
- clocks = <&clkc CLKID_CPU_CLK>;
- clock-latency = <50000>;
-};
-
-&cpu1 {
- cpu-supply = <&vddcpu_b>;
- operating-points-v2 = <&cpu_opp_table_0>;
- clocks = <&clkc CLKID_CPU_CLK>;
- clock-latency = <50000>;
-};
-
-&cpu100 {
- cpu-supply = <&vddcpu_a>;
- operating-points-v2 = <&cpub_opp_table_1>;
- clocks = <&clkc CLKID_CPUB_CLK>;
- clock-latency = <50000>;
-};
-
-&cpu101 {
- cpu-supply = <&vddcpu_a>;
- operating-points-v2 = <&cpub_opp_table_1>;
- clocks = <&clkc CLKID_CPUB_CLK>;
- clock-latency = <50000>;
-};
-
-&cpu102 {
- cpu-supply = <&vddcpu_a>;
- operating-points-v2 = <&cpub_opp_table_1>;
- clocks = <&clkc CLKID_CPUB_CLK>;
- clock-latency = <50000>;
-};
-
-&cpu103 {
- cpu-supply = <&vddcpu_a>;
- operating-points-v2 = <&cpub_opp_table_1>;
- clocks = <&clkc CLKID_CPUB_CLK>;
- clock-latency = <50000>;
-};
-
-ðmac {
- pinctrl-0 = <ð_pins>, <ð_rgmii_pins>;
- pinctrl-names = "default";
- status = "okay";
- phy-mode = "rgmii";
- phy-handle = <&external_phy>;
- amlogic,tx-delay-ns = <2>;
-};
-
-&ext_mdio {
- external_phy: ethernet-phy@0 {
- /* Realtek RTL8211F (0x001cc916) */
- reg = <0>;
- max-speed = <1000>;
-
- reset-assert-us = <10000>;
- reset-deassert-us = <80000>;
- reset-gpios = <&gpio GPIOZ_15 (GPIO_ACTIVE_LOW | GPIO_OPEN_DRAIN)>;
-
- interrupt-parent = <&gpio_intc>;
- /* MAC_INTR on GPIOZ_14 */
- interrupts = <26 IRQ_TYPE_LEVEL_LOW>;
- };
-};
-
-&frddr_a {
- status = "okay";
-};
-
-&frddr_b {
- status = "okay";
-};
-
-&frddr_c {
- status = "okay";
-};
-
-&hdmi_tx {
- status = "okay";
- pinctrl-0 = <&hdmitx_hpd_pins>, <&hdmitx_ddc_pins>;
- pinctrl-names = "default";
- hdmi-supply = <&vcc_5v>;
-};
-
-&hdmi_tx_tmds_port {
- hdmi_tx_tmds_out: endpoint {
- remote-endpoint = <&hdmi_connector_in>;
- };
-};
-
-/* Main i2c bus */
-&i2c2 {
- status = "okay";
- pinctrl-0 = <&i2c2_sda_x_pins>, <&i2c2_sck_x_pins>;
- pinctrl-names = "default";
-};
-
-&pcie {
- status = "okay";
- reset-gpios = <&gpio GPIOA_8 GPIO_ACTIVE_LOW>;
-};
-
-&pwm_ab {
- status = "okay";
- pinctrl-0 = <&pwm_a_e_pins>;
- pinctrl-names = "default";
- clocks = <&xtal>;
- clock-names = "clkin0";
-};
-
-&pwm_cd {
- status = "okay";
- pinctrl-0 = <&pwm_d_x6_pins>;
- pinctrl-names = "default";
- pwm-gpios = <&gpio GPIOAO_10 GPIO_ACTIVE_HIGH>;
-};
-
-&pwm_ef {
- status = "okay";
- pinctrl-0 = <&pwm_e_pins>;
- pinctrl-names = "default";
-};
-
-&pwm_AO_cd {
- pinctrl-0 = <&pwm_ao_d_e_pins>;
- pinctrl-names = "default";
- clocks = <&xtal>;
- clock-names = "clkin1";
- status = "okay";
-};
-
-&saradc {
- status = "okay";
- vref-supply = <&vddao_1v8>;
-};
-
-/* SDIO */
-&sd_emmc_a {
- /* enable if WiFi/BT board connected */
- status = "disabled";
- pinctrl-0 = <&sdio_pins>;
- pinctrl-1 = <&sdio_clk_gate_pins>;
- pinctrl-names = "default", "clk-gate";
- #address-cells = <1>;
- #size-cells = <0>;
-
- bus-width = <4>;
- sd-uhs-sdr104;
- max-frequency = <50000000>;
-
- non-removable;
- disable-wp;
-
- /* WiFi firmware requires power in suspend */
- keep-power-in-suspend;
-
- mmc-pwrseq = <&sdio_pwrseq>;
-
- vmmc-supply = <&vsys_3v3>;
- vqmmc-supply = <&vddao_1v8>;
-
- rtl8822cs: wifi@1 {
- reg = <1>;
- };
-};
-
-/* SD card */
-&sd_emmc_b {
- status = "okay";
- pinctrl-0 = <&sdcard_c_pins>;
- pinctrl-1 = <&sdcard_clk_gate_c_pins>;
- pinctrl-names = "default", "clk-gate";
-
- bus-width = <4>;
- cap-sd-highspeed;
- max-frequency = <50000000>;
- disable-wp;
-
- cd-gpios = <&gpio GPIOC_6 GPIO_ACTIVE_LOW>;
- vmmc-supply = <&vsys_3v3>;
- vqmmc-supply = <&vsys_3v3>;
-};
-
-/* eMMC */
-&sd_emmc_c {
- status = "okay";
- pinctrl-0 = <&emmc_ctrl_pins>, <&emmc_data_8b_pins>, <&emmc_ds_pins>;
- pinctrl-1 = <&emmc_clk_gate_pins>;
- pinctrl-names = "default", "clk-gate";
-
- bus-width = <8>;
- cap-mmc-highspeed;
- mmc-ddr-1_8v;
- mmc-hs200-1_8v;
- max-frequency = <200000000>;
- disable-wp;
-
- mmc-pwrseq = <&emmc_pwrseq>;
- vmmc-supply = <&vcc_3v3>;
- vqmmc-supply = <&emmc_1v8>;
-};
-
-&tdmif_b {
- status = "okay";
-};
-
-&tdmout_b {
- status = "okay";
-};
-
-&tohdmitx {
- status = "okay";
-};
-
-&uart_A {
- /* enable if WiFi/BT board connected */
- status = "disabled";
- pinctrl-0 = <&uart_a_pins>, <&uart_a_cts_rts_pins>;
- pinctrl-names = "default";
- uart-has-rtscts;
-
- bluetooth {
- compatible = "realtek,rtl8822cs-bt";
- enable-gpios = <&gpio GPIOX_17 GPIO_ACTIVE_HIGH>;
- host-wake-gpios = <&gpio GPIOX_19 GPIO_ACTIVE_HIGH>;
- device-wake-gpios = <&gpio GPIOX_18 GPIO_ACTIVE_HIGH>;
- };
-};
-
-&uart_AO {
- status = "okay";
- pinctrl-0 = <&uart_ao_a_pins>;
- pinctrl-names = "default";
-};
-
-&usb2_phy0 {
- phy-supply = <&dc_in>;
-};
-
-&usb2_phy1 {
- phy-supply = <&usb_pwr>;
-};
-
-&usb3_pcie_phy {
- phy-supply = <&usb_pwr>;
-};
-
-&usb {
- status = "okay";
- dr_mode = "peripheral";
- phys = <&usb2_phy0>, <&usb2_phy1>;
- phy-names = "usb2-phy0", "usb2-phy1";
-};
diff --git a/arch/arm/dts/meson-g12b-gsking-x.dts b/arch/arm/dts/meson-g12b-gsking-x.dts
deleted file mode 100644
index 6c7bfac..0000000
--- a/arch/arm/dts/meson-g12b-gsking-x.dts
+++ /dev/null
@@ -1,133 +0,0 @@
-// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
-/*
- * Copyright (c) 2019 BayLibre, SAS
- * Author: Neil Armstrong <narmstrong@baylibre.com>
- * Copyright (c) 2019 Christian Hewitt <christianshewitt@gmail.com>
- */
-
-/dts-v1/;
-
-#include "meson-g12b-w400.dtsi"
-#include <dt-bindings/leds/common.h>
-#include <dt-bindings/sound/meson-g12a-tohdmitx.h>
-
-/ {
- compatible = "azw,gsking-x", "amlogic,s922x", "amlogic,g12b";
- model = "Beelink GS-King X";
-
- aliases {
- rtc0 = &rtc;
- rtc1 = &vrtc;
- };
-
- gpio-keys-polled {
- compatible = "gpio-keys-polled";
- #address-cells = <1>;
- #size-cells = <0>;
- poll-interval = <100>;
-
- power-button {
- label = "power";
- linux,code = <KEY_POWER>;
- gpios = <&gpio_ao GPIOAO_3 GPIO_ACTIVE_HIGH>;
- };
- };
-
- sound {
- compatible = "amlogic,axg-sound-card";
- model = "GSKING-X";
- audio-aux-devs = <&tdmout_a>;
- audio-routing = "TDMOUT_A IN 0", "FRDDR_A OUT 1",
- "TDMOUT_A IN 1", "FRDDR_B OUT 1",
- "TDMOUT_A IN 2", "FRDDR_C OUT 1",
- "TDM_A Playback", "TDMOUT_A OUT";
-
- assigned-clocks = <&clkc CLKID_MPLL2>,
- <&clkc CLKID_MPLL0>,
- <&clkc CLKID_MPLL1>;
- assigned-clock-parents = <0>, <0>, <0>;
- assigned-clock-rates = <294912000>,
- <270950400>,
- <393216000>;
- status = "okay";
-
- dai-link-0 {
- sound-dai = <&frddr_a>;
- };
-
- dai-link-1 {
- sound-dai = <&frddr_b>;
- };
-
- dai-link-2 {
- sound-dai = <&frddr_c>;
- };
-
- /* 8ch hdmi interface */
- dai-link-3 {
- sound-dai = <&tdmif_a>;
- dai-format = "i2s";
- dai-tdm-slot-tx-mask-0 = <1 1>;
- dai-tdm-slot-tx-mask-1 = <1 1>;
- dai-tdm-slot-tx-mask-2 = <1 1>;
- dai-tdm-slot-tx-mask-3 = <1 1>;
- mclk-fs = <256>;
-
- codec {
- sound-dai = <&tohdmitx TOHDMITX_I2S_IN_A>;
- };
- };
-
- dai-link-4 {
- sound-dai = <&tohdmitx TOHDMITX_I2S_OUT>;
-
- codec {
- sound-dai = <&hdmi_tx>;
- };
- };
- };
-};
-
-&arb {
- status = "okay";
-};
-
-&clkc_audio {
- status = "okay";
-};
-
-&frddr_a {
- status = "okay";
-};
-
-&frddr_b {
- status = "okay";
-};
-
-&frddr_c {
- status = "okay";
-};
-
-&i2c3 {
- status = "okay";
- pinctrl-0 = <&i2c3_sda_a_pins>, <&i2c3_sck_a_pins>;
- pinctrl-names = "default";
-
- rtc: rtc@51 {
- compatible = "nxp,pcf8563";
- reg = <0x51>;
- wakeup-source;
- };
-};
-
-&tdmif_a {
- status = "okay";
-};
-
-&tdmout_a {
- status = "okay";
-};
-
-&tohdmitx {
- status = "okay";
-};
diff --git a/arch/arm/dts/meson-g12b-gtking-pro.dts b/arch/arm/dts/meson-g12b-gtking-pro.dts
deleted file mode 100644
index 707daf9..0000000
--- a/arch/arm/dts/meson-g12b-gtking-pro.dts
+++ /dev/null
@@ -1,142 +0,0 @@
-// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
-/*
- * Copyright (c) 2019 BayLibre, SAS
- * Author: Neil Armstrong <narmstrong@baylibre.com>
- * Copyright (c) 2019 Christian Hewitt <christianshewitt@gmail.com>
- */
-
-/dts-v1/;
-
-#include "meson-g12b-w400.dtsi"
-#include <dt-bindings/sound/meson-g12a-tohdmitx.h>
-
-/ {
- compatible = "azw,gtking", "amlogic,s922x", "amlogic,g12b";
- model = "Beelink GT-King Pro";
-
- aliases {
- rtc0 = &rtc;
- rtc1 = &vrtc;
- };
-
- gpio-keys-polled {
- compatible = "gpio-keys-polled";
- #address-cells = <1>;
- #size-cells = <0>;
- poll-interval = <100>;
-
- power-button {
- label = "power";
- linux,code = <KEY_POWER>;
- gpios = <&gpio_ao GPIOAO_3 GPIO_ACTIVE_HIGH>;
- };
- };
-
- leds {
- compatible = "gpio-leds";
-
- led-white {
- label = "power:white";
- gpios = <&gpio_ao GPIOAO_11 GPIO_ACTIVE_HIGH>;
- default-state = "on";
- };
- };
-
- sound {
- compatible = "amlogic,axg-sound-card";
- model = "GTKING-PRO";
- audio-aux-devs = <&tdmout_b>;
- audio-routing = "TDMOUT_B IN 0", "FRDDR_A OUT 1",
- "TDMOUT_B IN 1", "FRDDR_B OUT 1",
- "TDMOUT_B IN 2", "FRDDR_C OUT 1",
- "TDM_B Playback", "TDMOUT_B OUT";
-
- assigned-clocks = <&clkc CLKID_MPLL2>,
- <&clkc CLKID_MPLL0>,
- <&clkc CLKID_MPLL1>;
- assigned-clock-parents = <0>, <0>, <0>;
- assigned-clock-rates = <294912000>,
- <270950400>,
- <393216000>;
- status = "okay";
-
- dai-link-0 {
- sound-dai = <&frddr_a>;
- };
-
- dai-link-1 {
- sound-dai = <&frddr_b>;
- };
-
- dai-link-2 {
- sound-dai = <&frddr_c>;
- };
-
- /* 8ch hdmi interface */
- dai-link-3 {
- sound-dai = <&tdmif_b>;
- dai-format = "i2s";
- dai-tdm-slot-tx-mask-0 = <1 1>;
- dai-tdm-slot-tx-mask-1 = <1 1>;
- dai-tdm-slot-tx-mask-2 = <1 1>;
- dai-tdm-slot-tx-mask-3 = <1 1>;
- mclk-fs = <256>;
-
- codec {
- sound-dai = <&tohdmitx TOHDMITX_I2S_IN_B>;
- };
- };
-
- dai-link-4 {
- sound-dai = <&tohdmitx TOHDMITX_I2S_OUT>;
-
- codec {
- sound-dai = <&hdmi_tx>;
- };
- };
- };
-};
-
-&arb {
- status = "okay";
-};
-
-&clkc_audio {
- status = "okay";
-};
-
-&frddr_a {
- status = "okay";
-};
-
-&frddr_b {
- status = "okay";
-};
-
-&frddr_c {
- status = "okay";
-};
-
-&i2c3 {
- status = "okay";
- pinctrl-0 = <&i2c3_sda_a_pins>, <&i2c3_sck_a_pins>;
- pinctrl-names = "default";
-
- rtc: rtc@51 {
- compatible = "nxp,pcf8563";
- reg = <0x51>;
- wakeup-source;
- };
-};
-
-&tdmif_b {
- status = "okay";
-};
-
-&tdmout_b {
- status = "okay";
-};
-
-&tohdmitx {
- status = "okay";
-};
diff --git a/arch/arm/dts/meson-g12b-gtking.dts b/arch/arm/dts/meson-g12b-gtking.dts
deleted file mode 100644
index 5d96c14..0000000
--- a/arch/arm/dts/meson-g12b-gtking.dts
+++ /dev/null
@@ -1,163 +0,0 @@
-// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
-/*
- * Copyright (c) 2019 BayLibre, SAS
- * Author: Neil Armstrong <narmstrong@baylibre.com>
- * Copyright (c) 2019 Christian Hewitt <christianshewitt@gmail.com>
- */
-
-/dts-v1/;
-
-#include "meson-g12b-w400.dtsi"
-#include <dt-bindings/sound/meson-g12a-tohdmitx.h>
-
-/ {
- compatible = "azw,gtking", "amlogic,s922x", "amlogic,g12b";
- model = "Beelink GT-King";
-
- aliases {
- rtc0 = &rtc;
- rtc1 = &vrtc;
- };
-
- spdif_dit: audio-codec-1 {
- #sound-dai-cells = <0>;
- compatible = "linux,spdif-dit";
- status = "okay";
- sound-name-prefix = "DIT";
- };
-
- sound {
- compatible = "amlogic,axg-sound-card";
- model = "GTKING";
- audio-aux-devs = <&tdmout_b>;
- audio-routing = "TDMOUT_B IN 0", "FRDDR_A OUT 1",
- "TDMOUT_B IN 1", "FRDDR_B OUT 1",
- "TDMOUT_B IN 2", "FRDDR_C OUT 1",
- "TDM_B Playback", "TDMOUT_B OUT",
- "SPDIFOUT IN 0", "FRDDR_A OUT 3",
- "SPDIFOUT IN 1", "FRDDR_B OUT 3",
- "SPDIFOUT IN 2", "FRDDR_C OUT 3";
-
- assigned-clocks = <&clkc CLKID_MPLL2>,
- <&clkc CLKID_MPLL0>,
- <&clkc CLKID_MPLL1>;
- assigned-clock-parents = <0>, <0>, <0>;
- assigned-clock-rates = <294912000>,
- <270950400>,
- <393216000>;
- status = "okay";
-
- dai-link-0 {
- sound-dai = <&frddr_a>;
- };
-
- dai-link-1 {
- sound-dai = <&frddr_b>;
- };
-
- dai-link-2 {
- sound-dai = <&frddr_c>;
- };
-
- /* 8ch hdmi interface */
- dai-link-3 {
- sound-dai = <&tdmif_b>;
- dai-format = "i2s";
- dai-tdm-slot-tx-mask-0 = <1 1>;
- dai-tdm-slot-tx-mask-1 = <1 1>;
- dai-tdm-slot-tx-mask-2 = <1 1>;
- dai-tdm-slot-tx-mask-3 = <1 1>;
- mclk-fs = <256>;
-
- codec {
- sound-dai = <&tohdmitx TOHDMITX_I2S_IN_B>;
- };
- };
-
- /* spdif hdmi or toslink interface */
- dai-link-4 {
- sound-dai = <&spdifout>;
-
- codec-0 {
- sound-dai = <&spdif_dit>;
- };
-
- codec-1 {
- sound-dai = <&tohdmitx TOHDMITX_SPDIF_IN_A>;
- };
- };
-
- /* spdif hdmi interface */
- dai-link-5 {
- sound-dai = <&spdifout_b>;
-
- codec {
- sound-dai = <&tohdmitx TOHDMITX_SPDIF_IN_B>;
- };
- };
-
- /* hdmi glue */
- dai-link-6 {
- sound-dai = <&tohdmitx TOHDMITX_I2S_OUT>;
-
- codec {
- sound-dai = <&hdmi_tx>;
- };
- };
- };
-};
-
-&arb {
- status = "okay";
-};
-
-&clkc_audio {
- status = "okay";
-};
-
-&frddr_a {
- status = "okay";
-};
-
-&frddr_b {
- status = "okay";
-};
-
-&frddr_c {
- status = "okay";
-};
-
-
-&i2c3 {
- status = "okay";
- pinctrl-0 = <&i2c3_sda_a_pins>, <&i2c3_sck_a_pins>;
- pinctrl-names = "default";
-
- rtc: rtc@51 {
- compatible = "nxp,pcf8563";
- reg = <0x51>;
- wakeup-source;
- };
-};
-
-&spdifout {
- pinctrl-0 = <&spdif_out_h_pins>;
- pinctrl-names = "default";
- status = "okay";
-};
-
-&spdifout_b {
- status = "okay";
-};
-
-&tdmif_b {
- status = "okay";
-};
-
-&tdmout_b {
- status = "okay";
-};
-
-&tohdmitx {
- status = "okay";
-};
diff --git a/arch/arm/dts/meson-g12b-khadas-vim3.dtsi b/arch/arm/dts/meson-g12b-khadas-vim3.dtsi
deleted file mode 100644
index f42cf4b..0000000
--- a/arch/arm/dts/meson-g12b-khadas-vim3.dtsi
+++ /dev/null
@@ -1,107 +0,0 @@
-// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
-/*
- * Copyright (c) 2019 BayLibre, SAS
- * Author: Neil Armstrong <narmstrong@baylibre.com>
- * Copyright (c) 2019 Christian Hewitt <christianshewitt@gmail.com>
- */
-
-/ {
- model = "Khadas VIM3";
-
- vddcpu_a: regulator-vddcpu-a {
- /*
- * MP8756GD Regulator.
- */
- compatible = "pwm-regulator";
-
- regulator-name = "VDDCPU_A";
- regulator-min-microvolt = <690000>;
- regulator-max-microvolt = <1050000>;
-
- vin-supply = <&dc_in>;
-
- pwms = <&pwm_ab 0 1250 0>;
- pwm-dutycycle-range = <100 0>;
-
- regulator-boot-on;
- regulator-always-on;
- };
-
- vddcpu_b: regulator-vddcpu-b {
- /*
- * Silergy SY8030DEC Regulator.
- */
- compatible = "pwm-regulator";
-
- regulator-name = "VDDCPU_B";
- regulator-min-microvolt = <690000>;
- regulator-max-microvolt = <1050000>;
-
- vin-supply = <&vsys_3v3>;
-
- pwms = <&pwm_AO_cd 1 1250 0>;
- pwm-dutycycle-range = <100 0>;
-
- regulator-boot-on;
- regulator-always-on;
- };
-};
-
-&cpu0 {
- cpu-supply = <&vddcpu_b>;
- operating-points-v2 = <&cpu_opp_table_0>;
- clocks = <&clkc CLKID_CPU_CLK>;
- clock-latency = <50000>;
-};
-
-&cpu1 {
- cpu-supply = <&vddcpu_b>;
- operating-points-v2 = <&cpu_opp_table_0>;
- clocks = <&clkc CLKID_CPU_CLK>;
- clock-latency = <50000>;
-};
-
-&cpu100 {
- cpu-supply = <&vddcpu_a>;
- operating-points-v2 = <&cpub_opp_table_1>;
- clocks = <&clkc CLKID_CPUB_CLK>;
- clock-latency = <50000>;
-};
-
-&cpu101 {
- cpu-supply = <&vddcpu_a>;
- operating-points-v2 = <&cpub_opp_table_1>;
- clocks = <&clkc CLKID_CPUB_CLK>;
- clock-latency = <50000>;
-};
-
-&cpu102 {
- cpu-supply = <&vddcpu_a>;
- operating-points-v2 = <&cpub_opp_table_1>;
- clocks = <&clkc CLKID_CPUB_CLK>;
- clock-latency = <50000>;
-};
-
-&cpu103 {
- cpu-supply = <&vddcpu_a>;
- operating-points-v2 = <&cpub_opp_table_1>;
- clocks = <&clkc CLKID_CPUB_CLK>;
- clock-latency = <50000>;
-};
-
-&pwm_ab {
- pinctrl-0 = <&pwm_a_e_pins>;
- pinctrl-names = "default";
- clocks = <&xtal>;
- clock-names = "clkin0";
- status = "okay";
-};
-
-&pwm_AO_cd {
- pinctrl-0 = <&pwm_ao_d_e_pins>;
- pinctrl-names = "default";
- clocks = <&xtal>;
- clock-names = "clkin1";
- status = "okay";
-};
-
diff --git a/arch/arm/dts/meson-g12b-odroid-go-ultra.dts b/arch/arm/dts/meson-g12b-odroid-go-ultra.dts
deleted file mode 100644
index 1e40709..0000000
--- a/arch/arm/dts/meson-g12b-odroid-go-ultra.dts
+++ /dev/null
@@ -1,722 +0,0 @@
-// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
-/*
- * Copyright (c) 2022 Neil Armstrong <neil.armstrong@linaro.org>
- */
-
-/dts-v1/;
-
-#include "meson-g12b-s922x.dtsi"
-#include <dt-bindings/input/input.h>
-#include <dt-bindings/leds/common.h>
-#include <dt-bindings/gpio/meson-g12a-gpio.h>
-#include <dt-bindings/sound/meson-g12a-toacodec.h>
-#include <dt-bindings/sound/meson-g12a-tohdmitx.h>
-
-/ {
- compatible = "hardkernel,odroid-go-ultra", "amlogic,s922x", "amlogic,g12b";
- model = "Hardkernel ODROID-GO-Ultra";
-
- aliases {
- serial0 = &uart_AO;
- rtc0 = &vrtc;
- };
-
- adc-joystick-left {
- compatible = "adc-joystick";
- io-channels = <&saradc 2>, <&saradc 3>;
- poll-interval = <10>;
- #address-cells = <1>;
- #size-cells = <0>;
-
- axis@0 {
- reg = <0>;
- linux,code = <ABS_Y>;
- abs-range = <3150 950>;
- abs-fuzz = <32>;
- abs-flat = <64>;
- };
- axis@1 {
- reg = <1>;
- linux,code = <ABS_X>;
- abs-range = <700 2900>;
- abs-fuzz = <32>;
- abs-flat = <64>;
- };
- };
-
- adc-joystick-right {
- compatible = "adc-joystick";
- io-channels = <&saradc 0>, <&saradc 1>;
- poll-interval = <10>;
- #address-cells = <1>;
- #size-cells = <0>;
-
- axis@0 {
- reg = <0>;
- linux,code = <ABS_RY>;
- abs-range = <3150 950>;
- abs-fuzz = <32>;
- abs-flat = <64>;
- };
- axis@1 {
- reg = <1>;
- linux,code = <ABS_RX>;
- abs-range = <800 3000>;
- abs-fuzz = <32>;
- abs-flat = <64>;
- };
- };
-
- chosen {
- stdout-path = "serial0:115200n8";
- };
-
- codec_clk: codec-clk {
- compatible = "fixed-clock";
- clock-frequency = <12288000>;
- clock-output-names = "codec_clk";
- #clock-cells = <0>;
- };
-
- gpio-keys {
- compatible = "gpio-keys-polled";
- poll-interval = <10>;
- pinctrl-0 = <&keypad_gpio_pins>;
- pinctrl-names = "default";
-
- volume-up-button {
- label = "VOLUME-UP";
- linux,code = <KEY_VOLUMEUP>;
- gpios = <&gpio GPIOX_8 GPIO_ACTIVE_LOW>;
- };
- volume-down-button {
- label = "VOLUME-DOWN";
- linux,code = <KEY_VOLUMEDOWN>;
- gpios = <&gpio GPIOX_9 GPIO_ACTIVE_LOW>;
- };
- dpad-up-button {
- label = "DPAD-UP";
- linux,code = <BTN_DPAD_UP>;
- gpios = <&gpio GPIOX_0 GPIO_ACTIVE_LOW>;
- };
- dpad-down-button {
- label = "DPAD-DOWN";
- linux,code = <BTN_DPAD_DOWN>;
- gpios = <&gpio GPIOX_1 GPIO_ACTIVE_LOW>;
- };
- dpad-left-button {
- label = "DPAD-LEFT";
- linux,code = <BTN_DPAD_LEFT>;
- gpios = <&gpio GPIOX_2 GPIO_ACTIVE_LOW>;
- };
- dpad-right-button {
- label = "DPAD-RIGHT";
- linux,code = <BTN_DPAD_RIGHT>;
- gpios = <&gpio GPIOX_3 GPIO_ACTIVE_LOW>;
- };
- a-button {
- label = "A";
- linux,code = <BTN_EAST>;
- gpios = <&gpio GPIOX_4 GPIO_ACTIVE_LOW>;
- };
- b-button {
- label = "B";
- linux,code = <BTN_SOUTH>;
- gpios = <&gpio GPIOX_5 GPIO_ACTIVE_LOW>;
- };
- y-button {
- label = "Y";
- linux,code = <BTN_WEST>;
- gpios = <&gpio GPIOX_6 GPIO_ACTIVE_LOW>;
- };
- x-button {
- label = "X";
- linux,code = <BTN_NORTH>;
- gpios = <&gpio GPIOX_7 GPIO_ACTIVE_LOW>;
- };
- f1-button {
- label = "F1";
- linux,code = <BTN_TRIGGER_HAPPY1>;
- gpios = <&gpio GPIOX_17 GPIO_ACTIVE_LOW>;
- };
- f2-button {
- label = "F2";
- linux,code = <BTN_TRIGGER_HAPPY2>;
- gpios = <&gpio GPIOX_10 GPIO_ACTIVE_LOW>;
- };
- f3-button {
- label = "F3";
- linux,code = <BTN_TRIGGER_HAPPY3>;
- gpios = <&gpio GPIOX_11 GPIO_ACTIVE_LOW>;
- };
- f4-button {
- label = "F4";
- linux,code = <BTN_TRIGGER_HAPPY4>;
- gpios = <&gpio GPIOX_12 GPIO_ACTIVE_LOW>;
- };
- f5-button {
- label = "F5";
- linux,code = <BTN_TRIGGER_HAPPY5>;
- gpios = <&gpio GPIOX_13 GPIO_ACTIVE_LOW>;
- };
- f6-button {
- label = "F6";
- linux,code = <BTN_TRIGGER_HAPPY6>;
- gpios = <&gpio GPIOX_16 GPIO_ACTIVE_LOW>;
- };
- top-left-button {
- label = "TOP Left";
- linux,code = <BTN_TL>;
- gpios = <&gpio GPIOX_14 GPIO_ACTIVE_LOW>;
- };
- top-left2-button {
- label = "TOP Left 2";
- linux,code = <BTN_TL2>;
- gpios = <&gpio GPIOX_19 GPIO_ACTIVE_LOW>;
- };
- top-right-button {
- label = "TOP Right";
- linux,code = <BTN_TR>;
- gpios = <&gpio GPIOX_15 GPIO_ACTIVE_LOW>;
- };
- top-right2-button {
- label = "TOP Right 2";
- linux,code = <BTN_TR2>;
- gpios = <&gpio GPIOX_18 GPIO_ACTIVE_LOW>;
- };
- };
-
- memory@0 {
- device_type = "memory";
- reg = <0x0 0x0 0x0 0x40000000>;
- };
-
- emmc_pwrseq: emmc-pwrseq {
- compatible = "mmc-pwrseq-emmc";
- reset-gpios = <&gpio BOOT_12 GPIO_ACTIVE_LOW>;
- };
-
- leds {
- compatible = "gpio-leds";
-
- led-blue {
- color = <LED_COLOR_ID_BLUE>;
- gpios = <&gpio_ao GPIOAO_11 GPIO_ACTIVE_HIGH>;
- linux,default-trigger = "heartbeat";
- };
- };
-
- vdd_sys: regulator-vdd-sys {
- compatible = "regulator-fixed";
- regulator-name = "VDD_SYS";
- regulator-min-microvolt = <3800000>;
- regulator-max-microvolt = <3800000>;
- regulator-always-on;
- };
-
- sound {
- compatible = "amlogic,axg-sound-card";
- model = "Odroid GO Ultra";
- audio-widgets = "Microphone", "Mic Jack",
- "Headphone", "Headphones",
- "Speaker", "Internal Speakers";
- audio-aux-devs = <&tdmout_b>, <&tdmin_b>, <&speaker_amp>;
- audio-routing = "TDMOUT_B IN 0", "FRDDR_A OUT 1",
- "TDM_B Playback", "TDMOUT_B OUT",
- "TDMIN_B IN 1", "TDM_B Capture",
- "TDMIN_B IN 4", "TDM_B Loopback",
- "TODDR_A IN 1", "TDMIN_B OUT",
- "MICL", "Mic Jack",
- "Headphones", "HPOL",
- "Headphones", "HPOR",
- "Speaker Amplifier INL", "HPOL",
- "Speaker Amplifier INR", "HPOR",
- "Internal Speakers", "Speaker Amplifier OUTL",
- "Internal Speakers", "Speaker Amplifier OUTR";
-
- assigned-clocks = <&clkc CLKID_MPLL2>,
- <&clkc CLKID_MPLL0>,
- <&clkc CLKID_MPLL1>;
- assigned-clock-parents = <0>, <0>, <0>;
- assigned-clock-rates = <294912000>,
- <270950400>,
- <393216000>;
-
- dai-link-0 {
- sound-dai = <&frddr_a>;
- };
-
- dai-link-1 {
- sound-dai = <&toddr_a>;
- };
-
- dai-link-2 {
- sound-dai = <&tdmif_b>;
- dai-format = "i2s";
- dai-tdm-slot-tx-mask-0 = <1 1>;
- mclk-fs = <256>;
-
- codec-0 {
- sound-dai = <&rk817>;
- };
- };
- };
-
- speaker_amp: speaker-amplifier {
- compatible = "simple-audio-amplifier";
- sound-name-prefix = "Speaker Amplifier";
- VCC-supply = <&hp_5v>;
- };
-};
-
-&arb {
- status = "okay";
-};
-
-&cpu0 {
- cpu-supply = <&vddcpu_b>;
- operating-points-v2 = <&cpu_opp_table_0>;
- clocks = <&clkc CLKID_CPU_CLK>;
- clock-latency = <50000>;
-};
-
-&cpu1 {
- cpu-supply = <&vddcpu_b>;
- operating-points-v2 = <&cpu_opp_table_0>;
- clocks = <&clkc CLKID_CPU_CLK>;
- clock-latency = <50000>;
-};
-
-&cpu100 {
- cpu-supply = <&vddcpu_a>;
- operating-points-v2 = <&cpub_opp_table_1>;
- clocks = <&clkc CLKID_CPUB_CLK>;
- clock-latency = <50000>;
-};
-
-&cpu101 {
- cpu-supply = <&vddcpu_a>;
- operating-points-v2 = <&cpub_opp_table_1>;
- clocks = <&clkc CLKID_CPUB_CLK>;
- clock-latency = <50000>;
-};
-
-&cpu102 {
- cpu-supply = <&vddcpu_a>;
- operating-points-v2 = <&cpub_opp_table_1>;
- clocks = <&clkc CLKID_CPUB_CLK>;
- clock-latency = <50000>;
-};
-
-&cpu103 {
- cpu-supply = <&vddcpu_a>;
- operating-points-v2 = <&cpub_opp_table_1>;
- clocks = <&clkc CLKID_CPUB_CLK>;
- clock-latency = <50000>;
-};
-
-/* RK817 only supports 12.5mV steps, round up the values */
-&cpu_opp_table_0 {
- opp-1000000000 {
- opp-microvolt = <737500>;
- };
- opp-1200000000 {
- opp-microvolt = <737500>;
- };
- opp-1398000000 {
- opp-microvolt = <762500>;
- };
- opp-1512000000 {
- opp-microvolt = <800000>;
- };
- opp-1608000000 {
- opp-microvolt = <837500>;
- };
- opp-1704000000 {
- opp-microvolt = <862500>;
- };
- opp-1896000000 {
- opp-microvolt = <987500>;
- };
- opp-1992000000 {
- opp-microvolt = <1012500>;
- };
-};
-
-/* RK818 only supports 12.5mV steps, round up the values */
-&cpub_opp_table_1 {
- opp-1000000000 {
- opp-microvolt = <775000>;
- };
- opp-1200000000 {
- opp-microvolt = <775000>;
- };
- opp-1398000000 {
- opp-microvolt = <800000>;
- };
- opp-1512000000 {
- opp-microvolt = <825000>;
- };
- opp-1608000000 {
- opp-microvolt = <862500>;
- };
- opp-1704000000 {
- opp-microvolt = <900000>;
- };
- opp-1800000000 {
- opp-microvolt = <987500>;
- };
- opp-1908000000 {
- opp-microvolt = <1025000>;
- };
-};
-
-&i2c_AO {
- status = "okay";
- pinctrl-0 = <&i2c_ao_sck_pins>, <&i2c_ao_sda_pins>;
- pinctrl-names = "default";
-
- rk818: pmic@1c {
- compatible = "rockchip,rk818";
- reg = <0x1c>;
- interrupt-parent = <&gpio_intc>;
- interrupts = <7 IRQ_TYPE_LEVEL_LOW>; /* GPIOAO_7 */
-
- vcc1-supply = <&vdd_sys>;
- vcc2-supply = <&vdd_sys>;
- vcc3-supply = <&vdd_sys>;
- vcc4-supply = <&vdd_sys>;
- vcc6-supply = <&vdd_sys>;
- vcc7-supply = <&vcc_2v3>;
- vcc8-supply = <&vcc_2v3>;
- vcc9-supply = <&vddao_3v3>;
- boost-supply = <&vdd_sys>;
- switch-supply = <&vdd_sys>;
-
- regulators {
- vddcpu_a: DCDC_REG1 {
- regulator-name = "vddcpu_a";
- regulator-always-on;
- regulator-boot-on;
- regulator-min-microvolt = <775000>;
- regulator-max-microvolt = <1025000>;
- regulator-ramp-delay = <6001>;
- regulator-state-mem {
- regulator-on-in-suspend;
- regulator-suspend-microvolt = <775000>;
- };
- };
-
- vdd_ee: DCDC_REG2 {
- regulator-name = "vdd_ee";
- regulator-always-on;
- regulator-boot-on;
- regulator-min-microvolt = <875000>;
- regulator-max-microvolt = <1250000>;
- regulator-ramp-delay = <6001>;
- regulator-state-mem {
- regulator-on-in-suspend;
- regulator-suspend-microvolt = <875000>;
- };
- };
-
- vddq_1v1: DCDC_REG3 {
- regulator-name = "vddq_1v1";
- regulator-always-on;
- regulator-boot-on;
- regulator-state-mem {
- regulator-on-in-suspend;
- };
- };
-
- vddao_3v3: DCDC_REG4 {
- regulator-always-on;
- regulator-boot-on;
- regulator-min-microvolt = <3300000>;
- regulator-max-microvolt = <3300000>;
- regulator-name = "vddao_3v3";
- regulator-state-mem {
- regulator-on-in-suspend;
- regulator-suspend-microvolt = <3300000>;
- };
- };
-
- hp_5v: DCDC_BOOST {
- regulator-always-on;
- regulator-boot-on;
- regulator-name = "hp_5v";
- regulator-min-microvolt = <5000000>;
- regulator-max-microvolt = <5000000>;
- regulator-state-mem {
- regulator-off-in-suspend;
- };
- };
-
- vddio_ao1v8: LDO_REG5 {
- regulator-always-on;
- regulator-boot-on;
- regulator-min-microvolt = <1800000>;
- regulator-max-microvolt = <1800000>;
- regulator-name = "vddio_ao1v8";
- regulator-state-mem {
- regulator-on-in-suspend;
- regulator-suspend-microvolt = <1800000>;
- };
- };
-
- vddq_1v8: LDO_REG7 {
- regulator-always-on;
- regulator-boot-on;
- regulator-min-microvolt = <1800000>;
- regulator-max-microvolt = <1800000>;
- regulator-name = "vddq_1v8";
- regulator-state-mem {
- regulator-on-in-suspend;
- regulator-suspend-microvolt = <1800000>;
- };
- };
-
- vddio_c: LDO_REG9 {
- regulator-always-on;
- regulator-boot-on;
- regulator-min-microvolt = <1800000>;
- regulator-max-microvolt = <3300000>;
- regulator-name = "vddio_c";
- regulator-state-mem {
- regulator-on-in-suspend;
- regulator-suspend-microvolt = <3300000>;
- };
- };
-
- vcc_sd: SWITCH_REG {
- regulator-name = "vcc_sd";
- regulator-always-on;
- regulator-boot-on;
- regulator-min-microvolt = <3300000>;
- regulator-max-microvolt = <3300000>;
- regulator-state-mem {
- regulator-on-in-suspend;
- };
- };
-
- OTG_SWITCH {
- regulator-name = "otg_switch";
- regulator-state-mem {
- regulator-off-in-suspend;
- };
- };
- };
- };
-};
-
-&i2c3 {
- status = "okay";
- pinctrl-0 = <&i2c3_sda_a_pins>, <&i2c3_sck_a_pins>;
- pinctrl-names = "default";
-
- rk817: pmic@20 {
- compatible = "rockchip,rk817";
- reg = <0x20>;
- interrupt-parent = <&gpio_intc>;
-
- interrupts = <5 IRQ_TYPE_LEVEL_LOW>; /* GPIOAO_5 */
-
- vcc1-supply = <&vdd_sys>;
- vcc2-supply = <&vdd_sys>;
- vcc3-supply = <&vdd_sys>;
- vcc4-supply = <&vdd_sys>;
- vcc5-supply = <&vdd_sys>;
- vcc6-supply = <&vdd_sys>;
- vcc7-supply = <&vdd_sys>;
- vcc8-supply = <&vdd_sys>;
- vcc9-supply = <&rk817_boost>;
-
- #sound-dai-cells = <0>;
- clocks = <&codec_clk>;
- clock-names = "mclk";
-
- #clock-cells = <1>;
-
- regulators {
- vddcpu_b: DCDC_REG2 {
- regulator-always-on;
- regulator-boot-on;
- regulator-min-microvolt = <737500>;
- regulator-max-microvolt = <1012500>;
- regulator-ramp-delay = <6001>;
- regulator-initial-mode = <0x2>;
- regulator-name = "vddcpu_b";
- regulator-state-mem {
- regulator-on-in-suspend;
- regulator-suspend-microvolt = <1000000>;
- };
- };
-
- vcc_2v3: DCDC_REG3 {
- regulator-always-on;
- regulator-boot-on;
- regulator-min-microvolt = <2300000>;
- regulator-max-microvolt = <2400000>;
- regulator-initial-mode = <0x2>;
- regulator-name = "vcc_2v3";
- regulator-state-mem {
- regulator-on-in-suspend;
- };
- };
-
- LDO_REG4 {
- regulator-always-on;
- regulator-boot-on;
- regulator-min-microvolt = <3300000>;
- regulator-max-microvolt = <3300000>;
- regulator-name = "vdd_codec";
- regulator-state-mem {
- regulator-off-in-suspend;
- };
- };
-
- vcc_lcd: LDO_REG8 {
- regulator-min-microvolt = <3300000>;
- regulator-max-microvolt = <3300000>;
- regulator-name = "vcc_lcd";
- regulator-state-mem {
- regulator-off-in-suspend;
- };
- };
-
- rk817_boost: BOOST {
- regulator-always-on;
- regulator-boot-on;
- regulator-min-microvolt = <5000000>;
- regulator-max-microvolt = <5400000>;
- regulator-name = "rk817_boost";
- regulator-state-mem {
- regulator-off-in-suspend;
- };
- };
-
- usb_host: OTG_SWITCH {
- regulator-name = "usb_host";
- regulator-min-microvolt = <5000000>;
- regulator-max-microvolt = <5000000>;
- regulator-state-mem {
- regulator-off-in-suspend;
- };
- };
- };
- };
-};
-
-&clkc_audio {
- status = "okay";
-};
-
-ð_phy {
- status = "disabled";
-};
-
-&frddr_a {
- status = "okay";
-};
-
-&periphs_pinctrl {
- keypad_gpio_pins: keypad-gpio {
- mux {
- groups = "GPIOX_0", "GPIOX_1", "GPIOX_2", "GPIOX_3",
- "GPIOX_4", "GPIOX_5", "GPIOX_6", "GPIOX_7",
- "GPIOX_8", "GPIOX_9", "GPIOX_10", "GPIOX_11",
- "GPIOX_12", "GPIOX_13", "GPIOX_14", "GPIOX_15",
- "GPIOX_16", "GPIOX_17", "GPIOX_18", "GPIOX_19";
- function = "gpio_periphs";
- bias-pull-up;
- output-disable;
- };
- };
-};
-
-&saradc {
- status = "okay";
- vref-supply = <&vddio_ao1v8>;
-};
-
-/* SD card */
-&sd_emmc_b {
- status = "okay";
- pinctrl-0 = <&sdcard_c_pins>;
- pinctrl-1 = <&sdcard_clk_gate_c_pins>;
- pinctrl-names = "default", "clk-gate";
-
- bus-width = <4>;
- cap-sd-highspeed;
- max-frequency = <50000000>;
- disable-wp;
-
- cd-gpios = <&gpio GPIOC_6 GPIO_ACTIVE_LOW>;
- vmmc-supply = <&vcc_sd>;
- vqmmc-supply = <&vddio_c>;
-
-};
-
-/* eMMC */
-&sd_emmc_c {
- status = "okay";
- pinctrl-0 = <&emmc_ctrl_pins>, <&emmc_data_8b_pins>, <&emmc_ds_pins>;
- pinctrl-1 = <&emmc_clk_gate_pins>;
- pinctrl-names = "default", "clk-gate";
-
- bus-width = <8>;
- cap-mmc-highspeed;
- mmc-ddr-1_8v;
- mmc-hs200-1_8v;
- max-frequency = <200000000>;
- disable-wp;
-
- mmc-pwrseq = <&emmc_pwrseq>;
- vmmc-supply = <&vcc_sd>;
- vqmmc-supply = <&vddio_ao1v8>;
-};
-
-
-&tdmif_b {
- pinctrl-0 = <&tdm_b_dout0_pins>, <&tdm_b_fs_pins>, <&tdm_b_sclk_pins>, <&tdm_b_din1_pins>;
- pinctrl-names = "default";
- status = "okay";
-
- assigned-clocks = <&clkc_audio AUD_CLKID_TDM_SCLK_PAD1>,
- <&clkc_audio AUD_CLKID_TDM_LRCLK_PAD1>;
- assigned-clock-parents = <&clkc_audio AUD_CLKID_MST_B_SCLK>,
- <&clkc_audio AUD_CLKID_MST_B_LRCLK>;
- assigned-clock-rates = <0>, <0>;
-};
-
-&tdmin_b {
- status = "okay";
-};
-
-&tdmout_b {
- status = "okay";
-};
-
-&toddr_a {
- status = "okay";
-};
-
-&uart_AO {
- status = "okay";
- pinctrl-0 = <&uart_ao_a_pins>;
- pinctrl-names = "default";
-};
-
-&usb {
- status = "okay";
- dr_mode = "peripheral";
-};
-
-&usb2_phy0 {
- status = "okay";
-};
-
-&usb2_phy1 {
- status = "okay";
- phy-supply = <&usb_host>;
-};
diff --git a/arch/arm/dts/meson-g12b-odroid-n2-plus.dts b/arch/arm/dts/meson-g12b-odroid-n2-plus.dts
deleted file mode 100644
index ce1198a..0000000
--- a/arch/arm/dts/meson-g12b-odroid-n2-plus.dts
+++ /dev/null
@@ -1,31 +0,0 @@
-// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
-/*
- * Copyright (c) 2019 BayLibre, SAS
- * Author: Neil Armstrong <narmstrong@baylibre.com>
- */
-
-/dts-v1/;
-
-/* The Amlogic S922X Rev. C supports the same OPPs as the A311D variant */
-#include "meson-g12b-a311d.dtsi"
-#include "meson-g12b-odroid-n2.dtsi"
-
-/ {
- compatible = "hardkernel,odroid-n2-plus", "amlogic,s922x", "amlogic,g12b";
- model = "Hardkernel ODROID-N2Plus";
-};
-
-&vddcpu_a {
- regulator-min-microvolt = <680000>;
- regulator-max-microvolt = <1040000>;
-
- pwms = <&pwm_ab 0 1500 0>;
-};
-
-&vddcpu_b {
- regulator-min-microvolt = <680000>;
- regulator-max-microvolt = <1040000>;
-
- pwms = <&pwm_AO_cd 1 1500 0>;
-};
-
diff --git a/arch/arm/dts/meson-g12b-odroid-n2.dts b/arch/arm/dts/meson-g12b-odroid-n2.dts
deleted file mode 100644
index a198a91..0000000
--- a/arch/arm/dts/meson-g12b-odroid-n2.dts
+++ /dev/null
@@ -1,15 +0,0 @@
-// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
-/*
- * Copyright (c) 2019 BayLibre, SAS
- * Author: Neil Armstrong <narmstrong@baylibre.com>
- */
-
-/dts-v1/;
-
-#include "meson-g12b-s922x.dtsi"
-#include "meson-g12b-odroid-n2.dtsi"
-
-/ {
- compatible = "hardkernel,odroid-n2", "amlogic,s922x", "amlogic,g12b";
- model = "Hardkernel ODROID-N2";
-};
diff --git a/arch/arm/dts/meson-g12b-odroid-n2.dtsi b/arch/arm/dts/meson-g12b-odroid-n2.dtsi
deleted file mode 100644
index 24d0442..0000000
--- a/arch/arm/dts/meson-g12b-odroid-n2.dtsi
+++ /dev/null
@@ -1,303 +0,0 @@
-// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
-/*
- * Copyright (c) 2019 BayLibre, SAS
- * Author: Neil Armstrong <narmstrong@baylibre.com>
- */
-
-#include "meson-g12b-odroid.dtsi"
-
-/ {
- aliases {
- rtc0 = &rtc;
- };
-
- dio2133: audio-amplifier-0 {
- compatible = "simple-audio-amplifier";
- enable-gpios = <&gpio_ao GPIOAO_2 GPIO_ACTIVE_HIGH>;
- VCC-supply = <&vcc_5v>;
- sound-name-prefix = "U19";
- status = "okay";
- };
-
- hub_5v: regulator-hub_5v {
- compatible = "regulator-fixed";
- regulator-name = "HUB_5V";
- regulator-min-microvolt = <5000000>;
- regulator-max-microvolt = <5000000>;
- vin-supply = <&vcc_5v>;
-
- /* Connected to the Hub CHIPENABLE, LOW sets low power state */
- gpio = <&gpio GPIOH_5 GPIO_ACTIVE_HIGH>;
- enable-active-high;
- };
-
- sound {
- compatible = "amlogic,axg-sound-card";
- model = "ODROID-N2";
- audio-widgets = "Line", "Lineout";
- audio-aux-devs = <&tdmout_b>, <&tdmout_c>, <&tdmin_a>,
- <&tdmin_b>, <&tdmin_c>, <&tdmin_lb>,
- <&dio2133>;
- audio-routing = "TDMOUT_B IN 0", "FRDDR_A OUT 1",
- "TDMOUT_B IN 1", "FRDDR_B OUT 1",
- "TDMOUT_B IN 2", "FRDDR_C OUT 1",
- "TDM_B Playback", "TDMOUT_B OUT",
- "TDMOUT_C IN 0", "FRDDR_A OUT 2",
- "TDMOUT_C IN 1", "FRDDR_B OUT 2",
- "TDMOUT_C IN 2", "FRDDR_C OUT 2",
- "TDM_C Playback", "TDMOUT_C OUT",
- "TDMIN_A IN 4", "TDM_B Loopback",
- "TDMIN_B IN 4", "TDM_B Loopback",
- "TDMIN_C IN 4", "TDM_B Loopback",
- "TDMIN_LB IN 1", "TDM_B Loopback",
- "TDMIN_A IN 5", "TDM_C Loopback",
- "TDMIN_B IN 5", "TDM_C Loopback",
- "TDMIN_C IN 5", "TDM_C Loopback",
- "TDMIN_LB IN 2", "TDM_C Loopback",
- "TODDR_A IN 0", "TDMIN_A OUT",
- "TODDR_B IN 0", "TDMIN_A OUT",
- "TODDR_C IN 0", "TDMIN_A OUT",
- "TODDR_A IN 1", "TDMIN_B OUT",
- "TODDR_B IN 1", "TDMIN_B OUT",
- "TODDR_C IN 1", "TDMIN_B OUT",
- "TODDR_A IN 2", "TDMIN_C OUT",
- "TODDR_B IN 2", "TDMIN_C OUT",
- "TODDR_C IN 2", "TDMIN_C OUT",
- "TODDR_A IN 6", "TDMIN_LB OUT",
- "TODDR_B IN 6", "TDMIN_LB OUT",
- "TODDR_C IN 6", "TDMIN_LB OUT",
- "U19 INL", "ACODEC LOLP",
- "U19 INR", "ACODEC LORP",
- "Lineout", "U19 OUTL",
- "Lineout", "U19 OUTR";
-
- assigned-clocks = <&clkc CLKID_MPLL2>,
- <&clkc CLKID_MPLL0>,
- <&clkc CLKID_MPLL1>;
- assigned-clock-parents = <0>, <0>, <0>;
- assigned-clock-rates = <294912000>,
- <270950400>,
- <393216000>;
- status = "okay";
-
- dai-link-0 {
- sound-dai = <&frddr_a>;
- };
-
- dai-link-1 {
- sound-dai = <&frddr_b>;
- };
-
- dai-link-2 {
- sound-dai = <&frddr_c>;
- };
-
- dai-link-3 {
- sound-dai = <&toddr_a>;
- };
-
- dai-link-4 {
- sound-dai = <&toddr_b>;
- };
-
- dai-link-5 {
- sound-dai = <&toddr_c>;
- };
-
- /* 8ch hdmi interface */
- dai-link-6 {
- sound-dai = <&tdmif_b>;
- dai-format = "i2s";
- dai-tdm-slot-tx-mask-0 = <1 1>;
- dai-tdm-slot-tx-mask-1 = <1 1>;
- dai-tdm-slot-tx-mask-2 = <1 1>;
- dai-tdm-slot-tx-mask-3 = <1 1>;
- mclk-fs = <256>;
-
- codec-0 {
- sound-dai = <&tohdmitx TOHDMITX_I2S_IN_B>;
- };
-
- codec-1 {
- sound-dai = <&toacodec TOACODEC_IN_B>;
- };
- };
-
- /* i2s jack output interface */
- dai-link-7 {
- sound-dai = <&tdmif_c>;
- dai-format = "i2s";
- dai-tdm-slot-tx-mask-0 = <1 1>;
- mclk-fs = <256>;
-
- codec-0 {
- sound-dai = <&tohdmitx TOHDMITX_I2S_IN_C>;
- };
-
- codec-1 {
- sound-dai = <&toacodec TOACODEC_IN_C>;
- };
- };
-
- /* hdmi glue */
- dai-link-8 {
- sound-dai = <&tohdmitx TOHDMITX_I2S_OUT>;
-
- codec {
- sound-dai = <&hdmi_tx>;
- };
- };
-
- /* acodec glue */
- dai-link-9 {
- sound-dai = <&toacodec TOACODEC_OUT>;
-
- codec {
- sound-dai = <&acodec>;
- };
- };
- };
-};
-
-&acodec {
- AVDD-supply = <&vddao_1v8>;
- status = "okay";
-};
-
-ðmac {
- pinctrl-0 = <ð_pins>, <ð_rgmii_pins>;
- pinctrl-names = "default";
- status = "okay";
- phy-mode = "rgmii";
- phy-handle = <&external_phy>;
- amlogic,tx-delay-ns = <2>;
-};
-
-&ext_mdio {
- external_phy: ethernet-phy@0 {
- /* Realtek RTL8211F (0x001cc916) */
- reg = <0>;
- max-speed = <1000>;
-
- reset-assert-us = <10000>;
- reset-deassert-us = <80000>;
- reset-gpios = <&gpio GPIOZ_15 (GPIO_ACTIVE_LOW | GPIO_OPEN_DRAIN)>;
-
- interrupt-parent = <&gpio_intc>;
- /* MAC_INTR on GPIOZ_14 */
- interrupts = <26 IRQ_TYPE_LEVEL_LOW>;
- };
-};
-
-&gpio {
- gpio-line-names =
- /* GPIOZ */
- "", "", "", "", "", "", "", "",
- "", "", "", "", "", "", "", "",
- /* GPIOH */
- "", "", "", "", "", "", "", "",
- "",
- /* BOOT */
- "", "", "", "", "", "", "", "",
- "", "", "", "", "", "", "", "",
- /* GPIOC */
- "", "", "", "", "", "", "", "",
- /* GPIOA */
- "PIN_44", /* GPIOA_0 */
- "PIN_46", /* GPIOA_1 */
- "PIN_45", /* GPIOA_2 */
- "PIN_47", /* GPIOA_3 */
- "PIN_26", /* GPIOA_4 */
- "", "", "", "", "", "",
- "PIN_42", /* GPIOA_11 */
- "PIN_32", /* GPIOA_12 */
- "PIN_7", /* GPIOA_13 */
- "PIN_27", /* GPIOA_14 */
- "PIN_28", /* GPIOA_15 */
- /* GPIOX */
- "PIN_16", /* GPIOX_0 */
- "PIN_18", /* GPIOX_1 */
- "PIN_22", /* GPIOX_2 */
- "PIN_11", /* GPIOX_3 */
- "PIN_13", /* GPIOX_4 */
- "PIN_33", /* GPIOX_5 */
- "PIN_35", /* GPIOX_6 */
- "PIN_15", /* GPIOX_7 */
- "PIN_19", /* GPIOX_8 */
- "PIN_21", /* GPIOX_9 */
- "PIN_24", /* GPIOX_10 */
- "PIN_23", /* GPIOX_11 */
- "PIN_8", /* GPIOX_12 */
- "PIN_10", /* GPIOX_13 */
- "PIN_29", /* GPIOX_14 */
- "PIN_31", /* GPIOX_15 */
- "PIN_12", /* GPIOX_16 */
- "PIN_3", /* GPIOX_17 */
- "PIN_5", /* GPIOX_18 */
- "PIN_36"; /* GPIOX_19 */
- /*
- * WARNING: The USB Hub on the Odroid-N2 needs a reset signal
- * to be turned high in order to be detected by the USB Controller
- * This signal should be handled by a USB specific power sequence
- * in order to reset the Hub when USB bus is powered down.
- */
- hog-0 {
- gpio-hog;
- gpios = <GPIOH_4 GPIO_ACTIVE_HIGH>;
- output-high;
- line-name = "usb-hub-reset";
- };
-};
-
-&i2c3 {
- status = "okay";
- pinctrl-0 = <&i2c3_sda_a_pins>, <&i2c3_sck_a_pins>;
- pinctrl-names = "default";
-
- rtc: rtc@51 {
- compatible = "nxp,pcf8563";
- reg = <0x51>;
- wakeup-source;
- };
-};
-
-&ir {
- status = "okay";
- pinctrl-0 = <&remote_input_ao_pins>;
- pinctrl-names = "default";
- linux,rc-map-name = "rc-odroid";
-};
-
-/*
- * EMMC_D4, EMMC_D5, EMMC_D6 and EMMC_D7 pins are shared between SPI NOR pins
- * and eMMC Data 4 to 7 pins.
- * Replace emmc_data_8b_pins to emmc_data_4b_pins from sd_emmc_c pinctrl-0,
- * and change bus-width to 4 then spifc can be enabled.
- * The SW1 slide should also be set to the correct position.
- */
-&spifc {
- status = "disabled";
- pinctrl-0 = <&nor_pins>;
- pinctrl-names = "default";
-
- mx25u64: flash@0 {
- #address-cells = <1>;
- #size-cells = <1>;
- compatible = "mxicy,mx25u6435f", "jedec,spi-nor";
- reg = <0>;
- spi-max-frequency = <104000000>;
- };
-};
-
-&toacodec {
- status = "okay";
-};
-
-&usb {
- vbus-supply = <&usb_pwr_en>;
-};
-
-&usb2_phy1 {
- /* Enable the hub which is connected to this port */
- phy-supply = <&hub_5v>;
-};
diff --git a/arch/arm/dts/meson-g12b-odroid-n2l.dts b/arch/arm/dts/meson-g12b-odroid-n2l.dts
deleted file mode 100644
index 70919f4..0000000
--- a/arch/arm/dts/meson-g12b-odroid-n2l.dts
+++ /dev/null
@@ -1,125 +0,0 @@
-// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
-/*
- * Copyright (c) 2022 Dongjin Kim <tobetter@gmail.com>
- */
-
-/dts-v1/;
-
-/* The Amlogic S922X Rev. C supports the same OPPs as the A311D variant */
-#include "meson-g12b-a311d.dtsi"
-#include "meson-g12b-odroid.dtsi"
-
-/ {
- compatible = "hardkernel,odroid-n2l", "amlogic,s922x", "amlogic,g12b";
- model = "Hardkernel ODROID-N2L";
-
- sound {
- compatible = "amlogic,axg-sound-card";
- model = "ODROID-N2L";
- audio-aux-devs = <&tdmout_b>, <&tdmin_a>, <&tdmin_b>,
- <&tdmin_c>, <&tdmin_lb>;
- audio-routing = "TDMOUT_B IN 0", "FRDDR_A OUT 1",
- "TDMOUT_B IN 1", "FRDDR_B OUT 1",
- "TDMOUT_B IN 2", "FRDDR_C OUT 1",
- "TDM_B Playback", "TDMOUT_B OUT",
- "TDMIN_A IN 4", "TDM_B Loopback",
- "TDMIN_B IN 4", "TDM_B Loopback",
- "TDMIN_C IN 4", "TDM_B Loopback",
- "TDMIN_LB IN 1", "TDM_B Loopback",
- "TODDR_A IN 0", "TDMIN_A OUT",
- "TODDR_B IN 0", "TDMIN_A OUT",
- "TODDR_C IN 0", "TDMIN_A OUT",
- "TODDR_A IN 1", "TDMIN_B OUT",
- "TODDR_B IN 1", "TDMIN_B OUT",
- "TODDR_C IN 1", "TDMIN_B OUT",
- "TODDR_A IN 2", "TDMIN_C OUT",
- "TODDR_B IN 2", "TDMIN_C OUT",
- "TODDR_C IN 2", "TDMIN_C OUT",
- "TODDR_A IN 6", "TDMIN_LB OUT",
- "TODDR_B IN 6", "TDMIN_LB OUT",
- "TODDR_C IN 6", "TDMIN_LB OUT";
-
- assigned-clocks = <&clkc CLKID_MPLL2>,
- <&clkc CLKID_MPLL0>,
- <&clkc CLKID_MPLL1>;
- assigned-clock-parents = <0>, <0>, <0>;
- assigned-clock-rates = <294912000>,
- <270950400>,
- <393216000>;
- status = "okay";
-
- dai-link-0 {
- sound-dai = <&frddr_a>;
- };
-
- dai-link-1 {
- sound-dai = <&frddr_b>;
- };
-
- dai-link-2 {
- sound-dai = <&frddr_c>;
- };
-
- dai-link-3 {
- sound-dai = <&toddr_a>;
- };
-
- dai-link-4 {
- sound-dai = <&toddr_b>;
- };
-
- dai-link-5 {
- sound-dai = <&toddr_c>;
- };
-
- /* 8ch hdmi interface */
- dai-link-6 {
- sound-dai = <&tdmif_b>;
- dai-format = "i2s";
- dai-tdm-slot-tx-mask-0 = <1 1>;
- dai-tdm-slot-tx-mask-1 = <1 1>;
- dai-tdm-slot-tx-mask-2 = <1 1>;
- dai-tdm-slot-tx-mask-3 = <1 1>;
- mclk-fs = <256>;
-
- codec {
- sound-dai = <&tohdmitx TOHDMITX_I2S_IN_B>;
- };
- };
-
- /* hdmi glue */
- dai-link-7 {
- sound-dai = <&tohdmitx TOHDMITX_I2S_OUT>;
-
- codec {
- sound-dai = <&hdmi_tx>;
- };
- };
- };
-};
-
-ð_phy {
- status = "disabled";
-};
-
-&vddcpu_a {
- regulator-min-microvolt = <680000>;
- regulator-max-microvolt = <1040000>;
-
- pwms = <&pwm_ab 0 1500 0>;
-};
-
-&vddcpu_b {
- regulator-min-microvolt = <680000>;
- regulator-max-microvolt = <1040000>;
-
- pwms = <&pwm_AO_cd 1 1500 0>;
-};
-
-&usb2_phy0 {
- phy-supply = <&usb_pwr_en>;
-};
-
-&usb2_phy1 {
- phy-supply = <&usb_pwr_en>;
-};
diff --git a/arch/arm/dts/meson-g12b-odroid.dtsi b/arch/arm/dts/meson-g12b-odroid.dtsi
deleted file mode 100644
index 9e12a34..0000000
--- a/arch/arm/dts/meson-g12b-odroid.dtsi
+++ /dev/null
@@ -1,445 +0,0 @@
-// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
-/*
- * Copyright (c) 2019 BayLibre, SAS
- * Author: Neil Armstrong <narmstrong@baylibre.com>
- */
-
-#include <dt-bindings/input/input.h>
-#include <dt-bindings/gpio/meson-g12a-gpio.h>
-#include <dt-bindings/sound/meson-g12a-toacodec.h>
-#include <dt-bindings/sound/meson-g12a-tohdmitx.h>
-
-/ {
- aliases {
- serial0 = &uart_AO;
- ethernet0 = ðmac;
- rtc1 = &vrtc;
- };
-
- chosen {
- stdout-path = "serial0:115200n8";
- };
-
- memory@0 {
- device_type = "memory";
- reg = <0x0 0x0 0x0 0x40000000>;
- };
-
- emmc_pwrseq: emmc-pwrseq {
- compatible = "mmc-pwrseq-emmc";
- reset-gpios = <&gpio BOOT_12 GPIO_ACTIVE_LOW>;
- };
-
- fan: gpio-fan {
- compatible = "gpio-fan";
- gpios = <&gpio_ao GPIOAO_10 GPIO_ACTIVE_HIGH>;
- /* Using Dummy Speed */
- gpio-fan,speed-map = <0 0>, <1 1>;
- #cooling-cells = <2>;
- };
-
- leds {
- compatible = "gpio-leds";
-
- led-blue {
- label = "n2:blue";
- gpios = <&gpio_ao GPIOAO_11 GPIO_ACTIVE_HIGH>;
- linux,default-trigger = "heartbeat";
- };
- };
-
- tflash_vdd: regulator-tflash_vdd {
- compatible = "regulator-fixed";
-
- regulator-name = "TFLASH_VDD";
- regulator-min-microvolt = <3300000>;
- regulator-max-microvolt = <3300000>;
-
- gpio = <&gpio_ao GPIOAO_8 GPIO_ACTIVE_HIGH>;
- enable-active-high;
- regulator-always-on;
- };
-
- tf_io: gpio-regulator-tf_io {
- compatible = "regulator-gpio";
-
- regulator-name = "TF_IO";
- regulator-min-microvolt = <1800000>;
- regulator-max-microvolt = <3300000>;
-
- gpios = <&gpio_ao GPIOAO_9 GPIO_ACTIVE_HIGH>;
- gpios-states = <0>;
-
- states = <3300000 0>,
- <1800000 1>;
- };
-
- flash_1v8: regulator-flash_1v8 {
- compatible = "regulator-fixed";
- regulator-name = "FLASH_1V8";
- regulator-min-microvolt = <1800000>;
- regulator-max-microvolt = <1800000>;
- vin-supply = <&vcc_3v3>;
- regulator-always-on;
- };
-
- main_12v: regulator-main_12v {
- compatible = "regulator-fixed";
- regulator-name = "12V";
- regulator-min-microvolt = <12000000>;
- regulator-max-microvolt = <12000000>;
- regulator-always-on;
- };
-
- usb_pwr_en: regulator-usb_pwr_en {
- compatible = "regulator-fixed";
- regulator-name = "USB_PWR_EN";
- regulator-min-microvolt = <5000000>;
- regulator-max-microvolt = <5000000>;
- vin-supply = <&vcc_5v>;
-
- /* Connected to the microUSB port power enable */
- gpio = <&gpio GPIOH_6 GPIO_ACTIVE_HIGH>;
- enable-active-high;
- };
-
- vcc_5v: regulator-vcc_5v {
- compatible = "regulator-fixed";
- regulator-name = "5V";
- regulator-min-microvolt = <5000000>;
- regulator-max-microvolt = <5000000>;
- regulator-always-on;
- vin-supply = <&main_12v>;
- gpio = <&gpio GPIOH_8 GPIO_OPEN_DRAIN>;
- enable-active-high;
- };
-
- vcc_1v8: regulator-vcc_1v8 {
- compatible = "regulator-fixed";
- regulator-name = "VCC_1V8";
- regulator-min-microvolt = <1800000>;
- regulator-max-microvolt = <1800000>;
- vin-supply = <&vcc_3v3>;
- regulator-always-on;
- };
-
- vcc_3v3: regulator-vcc_3v3 {
- compatible = "regulator-fixed";
- regulator-name = "VCC_3V3";
- regulator-min-microvolt = <3300000>;
- regulator-max-microvolt = <3300000>;
- vin-supply = <&vddao_3v3>;
- regulator-always-on;
- /* FIXME: actually controlled by VDDCPU_B_EN */
- };
-
- vddcpu_a: regulator-vddcpu-a {
- /*
- * MP8756GD Regulator.
- */
- compatible = "pwm-regulator";
-
- regulator-name = "VDDCPU_A";
- regulator-min-microvolt = <721000>;
- regulator-max-microvolt = <1022000>;
-
- pwm-supply = <&main_12v>;
-
- pwms = <&pwm_ab 0 1250 0>;
- pwm-dutycycle-range = <100 0>;
-
- regulator-boot-on;
- regulator-always-on;
- };
-
- vddcpu_b: regulator-vddcpu-b {
- /*
- * Silergy SY8120B1ABC Regulator.
- */
- compatible = "pwm-regulator";
-
- regulator-name = "VDDCPU_B";
- regulator-min-microvolt = <721000>;
- regulator-max-microvolt = <1022000>;
-
- pwm-supply = <&main_12v>;
-
- pwms = <&pwm_AO_cd 1 1250 0>;
- pwm-dutycycle-range = <100 0>;
-
- regulator-boot-on;
- regulator-always-on;
- };
-
- vddao_1v8: regulator-vddao_1v8 {
- compatible = "regulator-fixed";
- regulator-name = "VDDAO_1V8";
- regulator-min-microvolt = <1800000>;
- regulator-max-microvolt = <1800000>;
- vin-supply = <&vddao_3v3>;
- regulator-always-on;
- };
-
- vddao_3v3: regulator-vddao_3v3 {
- compatible = "regulator-fixed";
- regulator-name = "VDDAO_3V3";
- regulator-min-microvolt = <3300000>;
- regulator-max-microvolt = <3300000>;
- vin-supply = <&main_12v>;
- regulator-always-on;
- };
-
- hdmi-connector {
- compatible = "hdmi-connector";
- type = "a";
-
- port {
- hdmi_connector_in: endpoint {
- remote-endpoint = <&hdmi_tx_tmds_out>;
- };
- };
- };
-};
-
-&arb {
- status = "okay";
-};
-
-&cec_AO {
- pinctrl-0 = <&cec_ao_a_h_pins>;
- pinctrl-names = "default";
- status = "disabled";
- hdmi-phandle = <&hdmi_tx>;
-};
-
-&cecb_AO {
- pinctrl-0 = <&cec_ao_b_h_pins>;
- pinctrl-names = "default";
- status = "okay";
- hdmi-phandle = <&hdmi_tx>;
-};
-
-&clkc_audio {
- status = "okay";
-};
-
-&cpu0 {
- cpu-supply = <&vddcpu_b>;
- operating-points-v2 = <&cpu_opp_table_0>;
- clocks = <&clkc CLKID_CPU_CLK>;
- clock-latency = <50000>;
-};
-
-&cpu1 {
- cpu-supply = <&vddcpu_b>;
- operating-points-v2 = <&cpu_opp_table_0>;
- clocks = <&clkc CLKID_CPU_CLK>;
- clock-latency = <50000>;
-};
-
-&cpu100 {
- cpu-supply = <&vddcpu_a>;
- operating-points-v2 = <&cpub_opp_table_1>;
- clocks = <&clkc CLKID_CPUB_CLK>;
- clock-latency = <50000>;
-};
-
-&cpu101 {
- cpu-supply = <&vddcpu_a>;
- operating-points-v2 = <&cpub_opp_table_1>;
- clocks = <&clkc CLKID_CPUB_CLK>;
- clock-latency = <50000>;
-};
-
-&cpu102 {
- cpu-supply = <&vddcpu_a>;
- operating-points-v2 = <&cpub_opp_table_1>;
- clocks = <&clkc CLKID_CPUB_CLK>;
- clock-latency = <50000>;
-};
-
-&cpu103 {
- cpu-supply = <&vddcpu_a>;
- operating-points-v2 = <&cpub_opp_table_1>;
- clocks = <&clkc CLKID_CPUB_CLK>;
- clock-latency = <50000>;
-};
-
-&cpu_thermal {
- trips {
- cpu_active: cpu-active {
- temperature = <60000>; /* millicelsius */
- hysteresis = <2000>; /* millicelsius */
- type = "active";
- };
- };
-
- cooling-maps {
- map {
- trip = <&cpu_active>;
- cooling-device = <&fan THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
- };
- };
-};
-
-&ddr_thermal {
- trips {
- ddr_active: ddr-active {
- temperature = <60000>; /* millicelsius */
- hysteresis = <2000>; /* millicelsius */
- type = "active";
- };
- };
-
- cooling-maps {
- map {
- trip = <&ddr_active>;
- cooling-device = <&fan THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
- };
- };
-};
-
-&frddr_a {
- status = "okay";
-};
-
-&frddr_b {
- status = "okay";
-};
-
-&frddr_c {
- status = "okay";
-};
-
-&hdmi_tx {
- status = "okay";
- pinctrl-0 = <&hdmitx_hpd_pins>, <&hdmitx_ddc_pins>;
- pinctrl-names = "default";
- hdmi-supply = <&vcc_5v>;
-};
-
-&hdmi_tx_tmds_port {
- hdmi_tx_tmds_out: endpoint {
- remote-endpoint = <&hdmi_connector_in>;
- };
-};
-
-&pwm_ab {
- pinctrl-0 = <&pwm_a_e_pins>;
- pinctrl-names = "default";
- clocks = <&xtal>;
- clock-names = "clkin0";
- status = "okay";
-};
-
-&pwm_AO_cd {
- pinctrl-0 = <&pwm_ao_d_e_pins>;
- pinctrl-names = "default";
- clocks = <&xtal>;
- clock-names = "clkin1";
- status = "okay";
-};
-
-&saradc {
- status = "okay";
- vref-supply = <&vddao_1v8>;
-};
-
-/* SD card */
-&sd_emmc_b {
- status = "okay";
- pinctrl-0 = <&sdcard_c_pins>;
- pinctrl-1 = <&sdcard_clk_gate_c_pins>;
- pinctrl-names = "default", "clk-gate";
-
- bus-width = <4>;
- cap-sd-highspeed;
- max-frequency = <50000000>;
- disable-wp;
-
- cd-gpios = <&gpio GPIOC_6 GPIO_ACTIVE_LOW>;
- vmmc-supply = <&tflash_vdd>;
- vqmmc-supply = <&tf_io>;
-
-};
-
-/* eMMC */
-&sd_emmc_c {
- status = "okay";
- pinctrl-0 = <&emmc_ctrl_pins>, <&emmc_data_8b_pins>, <&emmc_ds_pins>;
- pinctrl-1 = <&emmc_clk_gate_pins>;
- pinctrl-names = "default", "clk-gate";
-
- bus-width = <8>;
- cap-mmc-highspeed;
- mmc-ddr-1_8v;
- mmc-hs200-1_8v;
- max-frequency = <200000000>;
- disable-wp;
-
- mmc-pwrseq = <&emmc_pwrseq>;
- vmmc-supply = <&vcc_3v3>;
- vqmmc-supply = <&flash_1v8>;
-};
-
-&tdmif_b {
- status = "okay";
-};
-
-&tdmif_c {
- status = "okay";
-};
-
-&tdmin_a {
- status = "okay";
-};
-
-&tdmin_b {
- status = "okay";
-};
-
-&tdmin_c {
- status = "okay";
-};
-
-&tdmin_lb {
- status = "okay";
-};
-
-&tdmout_b {
- status = "okay";
-};
-
-&tdmout_c {
- status = "okay";
-};
-
-&tohdmitx {
- status = "okay";
-};
-
-&toddr_a {
- status = "okay";
-};
-
-&toddr_b {
- status = "okay";
-};
-
-&toddr_c {
- status = "okay";
-};
-
-&uart_AO {
- status = "okay";
- pinctrl-0 = <&uart_ao_a_pins>;
- pinctrl-names = "default";
-};
-
-&usb {
- status = "okay";
-};
-
-&usb2_phy0 {
- phy-supply = <&vcc_5v>;
-};
diff --git a/arch/arm/dts/meson-g12b-radxa-zero2.dts b/arch/arm/dts/meson-g12b-radxa-zero2.dts
deleted file mode 100644
index 890f5bf..0000000
--- a/arch/arm/dts/meson-g12b-radxa-zero2.dts
+++ /dev/null
@@ -1,489 +0,0 @@
-// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
-/*
- * Copyright (c) 2019 BayLibre, SAS
- * Author: Neil Armstrong <narmstrong@baylibre.com>
- * Copyright (c) 2019 Christian Hewitt <christianshewitt@gmail.com>
- * Copyright (c) 2022 Radxa Limited
- * Author: Yuntian Zhang <yt@radxa.com>
- */
-
-/dts-v1/;
-
-#include "meson-g12b-a311d.dtsi"
-#include <dt-bindings/input/input.h>
-#include <dt-bindings/leds/common.h>
-#include <dt-bindings/gpio/meson-g12a-gpio.h>
-#include <dt-bindings/sound/meson-g12a-tohdmitx.h>
-
-/ {
- compatible = "radxa,zero2", "amlogic,a311d", "amlogic,g12b";
- model = "Radxa Zero2";
-
- aliases {
- serial0 = &uart_AO;
- serial2 = &uart_A;
- };
-
- chosen {
- stdout-path = "serial0:115200n8";
- };
-
- memory@0 {
- device_type = "memory";
- reg = <0x0 0x0 0x0 0x80000000>;
- };
-
- gpio-keys-polled {
- compatible = "gpio-keys-polled";
- poll-interval = <100>;
- power-button {
- label = "power";
- linux,code = <KEY_POWER>;
- gpios = <&gpio_ao GPIOAO_3 (GPIO_ACTIVE_LOW | GPIO_PULL_UP)>;
- };
- };
-
- leds {
- compatible = "gpio-leds";
-
- led-green {
- color = <LED_COLOR_ID_GREEN>;
- function = LED_FUNCTION_STATUS;
- gpios = <&gpio GPIOA_12 GPIO_ACTIVE_HIGH>;
- linux,default-trigger = "heartbeat";
- };
- };
-
- hdmi-connector {
- compatible = "hdmi-connector";
- type = "a";
-
- port {
- hdmi_connector_in: endpoint {
- remote-endpoint = <&hdmi_tx_tmds_out>;
- };
- };
- };
-
- emmc_pwrseq: emmc-pwrseq {
- compatible = "mmc-pwrseq-emmc";
- reset-gpios = <&gpio BOOT_12 GPIO_ACTIVE_LOW>;
- };
-
- sdio_pwrseq: sdio-pwrseq {
- compatible = "mmc-pwrseq-simple";
- reset-gpios = <&gpio GPIOX_6 GPIO_ACTIVE_LOW>;
- clocks = <&wifi32k>;
- clock-names = "ext_clock";
- };
-
- ao_5v: regulator-ao-5v {
- compatible = "regulator-fixed";
- regulator-name = "AO_5V";
- regulator-min-microvolt = <5000000>;
- regulator-max-microvolt = <5000000>;
- regulator-always-on;
- };
-
- vcc_1v8: regulator-vcc-1v8 {
- compatible = "regulator-fixed";
- regulator-name = "VCC_1V8";
- regulator-min-microvolt = <1800000>;
- regulator-max-microvolt = <1800000>;
- vin-supply = <&vcc_3v3>;
- regulator-always-on;
- };
-
- vcc_3v3: regulator-vcc-3v3 {
- compatible = "regulator-fixed";
- regulator-name = "VCC_3V3";
- regulator-min-microvolt = <3300000>;
- regulator-max-microvolt = <3300000>;
- vin-supply = <&vddao_3v3>;
- regulator-always-on;
- /* FIXME: actually controlled by VDDCPU_B_EN */
- };
-
- vddao_1v8: regulator-vddao-1v8 {
- compatible = "regulator-fixed";
- regulator-name = "VDDIO_AO1V8";
- regulator-min-microvolt = <1800000>;
- regulator-max-microvolt = <1800000>;
- vin-supply = <&vddao_3v3>;
- regulator-always-on;
- };
-
- vddao_3v3: regulator-vddao-3v3 {
- compatible = "regulator-fixed";
- regulator-name = "VDDAO_3V3";
- regulator-min-microvolt = <3300000>;
- regulator-max-microvolt = <3300000>;
- vin-supply = <&ao_5v>;
- regulator-always-on;
- };
-
- vddcpu_a: regulator-vddcpu-a {
- /*
- * MP8756GD Regulator.
- */
- compatible = "pwm-regulator";
-
- regulator-name = "VDDCPU_A";
- regulator-min-microvolt = <730000>;
- regulator-max-microvolt = <1022000>;
-
- pwm-supply = <&ao_5v>;
-
- pwms = <&pwm_ab 0 1250 0>;
- pwm-dutycycle-range = <100 0>;
-
- regulator-boot-on;
- regulator-always-on;
- };
-
- vddcpu_b: regulator-vddcpu-b {
- /*
- * Silergy SY8120B1ABC Regulator.
- */
- compatible = "pwm-regulator";
-
- regulator-name = "VDDCPU_B";
- regulator-min-microvolt = <730000>;
- regulator-max-microvolt = <1022000>;
-
- pwm-supply = <&ao_5v>;
-
- pwms = <&pwm_AO_cd 1 1250 0>;
- pwm-dutycycle-range = <100 0>;
-
- regulator-boot-on;
- regulator-always-on;
- };
-
- sound {
- compatible = "amlogic,axg-sound-card";
- model = "RADXA-ZERO2";
- audio-aux-devs = <&tdmout_b>;
- audio-routing = "TDMOUT_B IN 0", "FRDDR_A OUT 1",
- "TDMOUT_B IN 1", "FRDDR_B OUT 1",
- "TDMOUT_B IN 2", "FRDDR_C OUT 1",
- "TDM_B Playback", "TDMOUT_B OUT";
-
- assigned-clocks = <&clkc CLKID_MPLL2>,
- <&clkc CLKID_MPLL0>,
- <&clkc CLKID_MPLL1>;
- assigned-clock-parents = <0>, <0>, <0>;
- assigned-clock-rates = <294912000>,
- <270950400>,
- <393216000>;
-
- dai-link-0 {
- sound-dai = <&frddr_a>;
- };
-
- dai-link-1 {
- sound-dai = <&frddr_b>;
- };
-
- dai-link-2 {
- sound-dai = <&frddr_c>;
- };
-
- /* 8ch hdmi interface */
- dai-link-3 {
- sound-dai = <&tdmif_b>;
- dai-format = "i2s";
- dai-tdm-slot-tx-mask-0 = <1 1>;
- dai-tdm-slot-tx-mask-1 = <1 1>;
- dai-tdm-slot-tx-mask-2 = <1 1>;
- dai-tdm-slot-tx-mask-3 = <1 1>;
- mclk-fs = <256>;
-
- codec {
- sound-dai = <&tohdmitx TOHDMITX_I2S_IN_B>;
- };
- };
-
- /* hdmi glue */
- dai-link-4 {
- sound-dai = <&tohdmitx TOHDMITX_I2S_OUT>;
-
- codec {
- sound-dai = <&hdmi_tx>;
- };
- };
- };
-
- wifi32k: clock-0 {
- compatible = "pwm-clock";
- #clock-cells = <0>;
- clock-frequency = <32768>;
- pwms = <&pwm_ef 0 30518 0>; /* PWM_E at 32.768KHz */
- };
-};
-
-&arb {
- status = "okay";
-};
-
-&cec_AO {
- pinctrl-0 = <&cec_ao_a_h_pins>;
- pinctrl-names = "default";
- status = "disabled";
- hdmi-phandle = <&hdmi_tx>;
-};
-
-&cecb_AO {
- pinctrl-0 = <&cec_ao_b_h_pins>;
- pinctrl-names = "default";
- status = "okay";
- hdmi-phandle = <&hdmi_tx>;
-};
-
-&clkc_audio {
- status = "okay";
-};
-
-&cpu0 {
- cpu-supply = <&vddcpu_b>;
- operating-points-v2 = <&cpu_opp_table_0>;
- clocks = <&clkc CLKID_CPU_CLK>;
- clock-latency = <50000>;
-};
-
-&cpu1 {
- cpu-supply = <&vddcpu_b>;
- operating-points-v2 = <&cpu_opp_table_0>;
- clocks = <&clkc CLKID_CPU_CLK>;
- clock-latency = <50000>;
-};
-
-&cpu100 {
- cpu-supply = <&vddcpu_a>;
- operating-points-v2 = <&cpub_opp_table_1>;
- clocks = <&clkc CLKID_CPUB_CLK>;
- clock-latency = <50000>;
-};
-
-&cpu101 {
- cpu-supply = <&vddcpu_a>;
- operating-points-v2 = <&cpub_opp_table_1>;
- clocks = <&clkc CLKID_CPUB_CLK>;
- clock-latency = <50000>;
-};
-
-&cpu102 {
- cpu-supply = <&vddcpu_a>;
- operating-points-v2 = <&cpub_opp_table_1>;
- clocks = <&clkc CLKID_CPUB_CLK>;
- clock-latency = <50000>;
-};
-
-&cpu103 {
- cpu-supply = <&vddcpu_a>;
- operating-points-v2 = <&cpub_opp_table_1>;
- clocks = <&clkc CLKID_CPUB_CLK>;
- clock-latency = <50000>;
-};
-
-&frddr_a {
- status = "okay";
-};
-
-&frddr_b {
- status = "okay";
-};
-
-&frddr_c {
- status = "okay";
-};
-
-&gpio {
- gpio-line-names =
- /* GPIOZ */
- "PIN_27", "PIN_28", "PIN_7", "PIN_11", "PIN_13", "PIN_15", "PIN_18", "PIN_40",
- "", "", "", "", "", "", "", "",
- /* GPIOH */
- "", "", "", "", "PIN_19", "PIN_21", "PIN_24", "PIN_23",
- "",
- /* BOOT */
- "", "", "", "", "", "", "", "",
- "", "", "", "", "EMMC_PWRSEQ", "", "", "",
- /* GPIOC */
- "", "", "", "", "", "", "SD_CD", "PIN_36",
- /* GPIOA */
- "PIN_32", "PIN_12", "PIN_35", "", "", "PIN_38", "", "",
- "", "", "", "", "LED_GREEN", "PIN_31", "PIN_3", "PIN_5",
- /* GPIOX */
- "", "", "", "", "", "", "SDIO_PWRSEQ", "",
- "", "", "", "", "", "", "", "",
- "", "BT_SHUTDOWN", "", "";
-};
-
-&gpio_ao {
- gpio-line-names =
- /* GPIOAO */
- "PIN_8", "PIN_10", "", "BTN_POWER", "", "", "", "PIN_29",
- "PIN_33", "PIN_37", "FAN", "",
- /* GPIOE */
- "", "", "";
-};
-
-&hdmi_tx {
- status = "okay";
- pinctrl-0 = <&hdmitx_hpd_pins>, <&hdmitx_ddc_pins>;
- pinctrl-names = "default";
- hdmi-supply = <&ao_5v>;
-};
-
-&hdmi_tx_tmds_port {
- hdmi_tx_tmds_out: endpoint {
- remote-endpoint = <&hdmi_connector_in>;
- };
-};
-
-&ir {
- status = "disabled";
- pinctrl-0 = <&remote_input_ao_pins>;
- pinctrl-names = "default";
-};
-
-&pwm_ab {
- pinctrl-0 = <&pwm_a_e_pins>;
- pinctrl-names = "default";
- clocks = <&xtal>;
- clock-names = "clkin0";
- status = "okay";
-};
-
-&pwm_ef {
- pinctrl-0 = <&pwm_e_pins>;
- pinctrl-names = "default";
- clocks = <&xtal>;
- clock-names = "clkin0";
- status = "okay";
-};
-
-&pwm_AO_ab {
- pinctrl-0 = <&pwm_ao_a_pins>;
- pinctrl-names = "default";
- clocks = <&xtal>;
- clock-names = "clkin0";
- status = "okay";
-};
-
-&pwm_AO_cd {
- pinctrl-0 = <&pwm_ao_d_e_pins>;
- pinctrl-names = "default";
- clocks = <&xtal>;
- clock-names = "clkin1";
- status = "okay";
-};
-
-&saradc {
- status = "okay";
- vref-supply = <&vddao_1v8>;
-};
-
-/* SDIO */
-&sd_emmc_a {
- status = "okay";
- pinctrl-0 = <&sdio_pins>;
- pinctrl-1 = <&sdio_clk_gate_pins>;
- pinctrl-names = "default", "clk-gate";
- #address-cells = <1>;
- #size-cells = <0>;
-
- bus-width = <4>;
- cap-sd-highspeed;
- max-frequency = <100000000>;
-
- non-removable;
- disable-wp;
-
- /* WiFi firmware requires power to be kept while in suspend */
- keep-power-in-suspend;
-
- mmc-pwrseq = <&sdio_pwrseq>;
-
- vmmc-supply = <&vddao_3v3>;
- vqmmc-supply = <&vddao_1v8>;
-
- brcmf: wifi@1 {
- reg = <1>;
- compatible = "brcm,bcm4329-fmac";
- };
-};
-
-/* SD card */
-&sd_emmc_b {
- status = "okay";
- pinctrl-0 = <&sdcard_c_pins>;
- pinctrl-1 = <&sdcard_clk_gate_c_pins>;
- pinctrl-names = "default", "clk-gate";
-
- bus-width = <4>;
- cap-sd-highspeed;
- max-frequency = <50000000>;
- disable-wp;
-
- cd-gpios = <&gpio GPIOC_6 GPIO_ACTIVE_LOW>;
- vmmc-supply = <&vddao_3v3>;
- vqmmc-supply = <&vddao_3v3>;
-};
-
-/* eMMC */
-&sd_emmc_c {
- status = "okay";
- pinctrl-0 = <&emmc_ctrl_pins>, <&emmc_data_8b_pins>, <&emmc_ds_pins>;
- pinctrl-1 = <&emmc_clk_gate_pins>;
- pinctrl-names = "default", "clk-gate";
-
- bus-width = <8>;
- cap-mmc-highspeed;
- mmc-ddr-1_8v;
- mmc-hs200-1_8v;
- max-frequency = <200000000>;
- disable-wp;
-
- mmc-pwrseq = <&emmc_pwrseq>;
- vmmc-supply = <&vcc_3v3>;
- vqmmc-supply = <&vcc_1v8>;
-};
-
-&tdmif_b {
- status = "okay";
-};
-
-&tdmout_b {
- status = "okay";
-};
-
-&tohdmitx {
- status = "okay";
-};
-
-&uart_A {
- status = "okay";
- pinctrl-0 = <&uart_a_pins>, <&uart_a_cts_rts_pins>;
- pinctrl-names = "default";
- uart-has-rtscts;
-
- bluetooth {
- compatible = "brcm,bcm43438-bt";
- shutdown-gpios = <&gpio GPIOX_17 GPIO_ACTIVE_HIGH>;
- max-speed = <2000000>;
- clocks = <&wifi32k>;
- clock-names = "lpo";
- };
-};
-
-&uart_AO {
- status = "okay";
- pinctrl-0 = <&uart_ao_a_pins>;
- pinctrl-names = "default";
-};
-
-&usb {
- status = "okay";
-};
diff --git a/arch/arm/dts/meson-g12b-s922x-bananapi-m2s.dts b/arch/arm/dts/meson-g12b-s922x-bananapi-m2s.dts
deleted file mode 100644
index 7f66f26..0000000
--- a/arch/arm/dts/meson-g12b-s922x-bananapi-m2s.dts
+++ /dev/null
@@ -1,14 +0,0 @@
-// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
-/*
- * Copyright (c) 2023 Christian Hewitt <christianshewitt@gmail.com>
- */
-
-/dts-v1/;
-
-#include "meson-g12b-s922x.dtsi"
-#include "meson-g12b-bananapi.dtsi"
-
-/ {
- compatible = "bananapi,bpi-m2s", "amlogic,s922x", "amlogic,g12b";
- model = "BananaPi M2S";
-};
diff --git a/arch/arm/dts/meson-g12b-s922x.dtsi b/arch/arm/dts/meson-g12b-s922x.dtsi
deleted file mode 100644
index 1e5d0ee..0000000
--- a/arch/arm/dts/meson-g12b-s922x.dtsi
+++ /dev/null
@@ -1,139 +0,0 @@
-// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
-/*
- * Copyright (c) 2019 BayLibre, SAS
- * Author: Neil Armstrong <narmstrong@baylibre.com>
- */
-
-#include "meson-g12b.dtsi"
-
-/ {
- cpu_opp_table_0: opp-table-0 {
- compatible = "operating-points-v2";
- opp-shared;
-
- opp-100000000 {
- opp-hz = /bits/ 64 <100000000>;
- opp-microvolt = <731000>;
- };
-
- opp-250000000 {
- opp-hz = /bits/ 64 <250000000>;
- opp-microvolt = <731000>;
- };
-
- opp-500000000 {
- opp-hz = /bits/ 64 <500000000>;
- opp-microvolt = <731000>;
- };
-
- opp-667000000 {
- opp-hz = /bits/ 64 <667000000>;
- opp-microvolt = <731000>;
- };
-
- opp-1000000000 {
- opp-hz = /bits/ 64 <1000000000>;
- opp-microvolt = <731000>;
- };
-
- opp-1200000000 {
- opp-hz = /bits/ 64 <1200000000>;
- opp-microvolt = <731000>;
- };
-
- opp-1398000000 {
- opp-hz = /bits/ 64 <1398000000>;
- opp-microvolt = <761000>;
- };
-
- opp-1512000000 {
- opp-hz = /bits/ 64 <1512000000>;
- opp-microvolt = <791000>;
- };
-
- opp-1608000000 {
- opp-hz = /bits/ 64 <1608000000>;
- opp-microvolt = <831000>;
- };
-
- opp-1704000000 {
- opp-hz = /bits/ 64 <1704000000>;
- opp-microvolt = <861000>;
- };
-
- opp-1896000000 {
- opp-hz = /bits/ 64 <1896000000>;
- opp-microvolt = <981000>;
- };
-
- opp-1992000000 {
- opp-hz = /bits/ 64 <1992000000>;
- opp-microvolt = <1001000>;
- };
- };
-
- cpub_opp_table_1: opp-table-1 {
- compatible = "operating-points-v2";
- opp-shared;
-
- opp-100000000 {
- opp-hz = /bits/ 64 <100000000>;
- opp-microvolt = <751000>;
- };
-
- opp-250000000 {
- opp-hz = /bits/ 64 <250000000>;
- opp-microvolt = <751000>;
- };
-
- opp-500000000 {
- opp-hz = /bits/ 64 <500000000>;
- opp-microvolt = <751000>;
- };
-
- opp-667000000 {
- opp-hz = /bits/ 64 <667000000>;
- opp-microvolt = <751000>;
- };
-
- opp-1000000000 {
- opp-hz = /bits/ 64 <1000000000>;
- opp-microvolt = <771000>;
- };
-
- opp-1200000000 {
- opp-hz = /bits/ 64 <1200000000>;
- opp-microvolt = <771000>;
- };
-
- opp-1398000000 {
- opp-hz = /bits/ 64 <1398000000>;
- opp-microvolt = <791000>;
- };
-
- opp-1512000000 {
- opp-hz = /bits/ 64 <1512000000>;
- opp-microvolt = <821000>;
- };
-
- opp-1608000000 {
- opp-hz = /bits/ 64 <1608000000>;
- opp-microvolt = <861000>;
- };
-
- opp-1704000000 {
- opp-hz = /bits/ 64 <1704000000>;
- opp-microvolt = <891000>;
- };
-
- opp-1800000000 {
- opp-hz = /bits/ 64 <1800000000>;
- opp-microvolt = <981000>;
- };
-
- opp-1908000000 {
- opp-hz = /bits/ 64 <1908000000>;
- opp-microvolt = <1022000>;
- };
- };
-};
diff --git a/arch/arm/dts/meson-g12b-w400.dtsi b/arch/arm/dts/meson-g12b-w400.dtsi
deleted file mode 100644
index feb0885..0000000
--- a/arch/arm/dts/meson-g12b-w400.dtsi
+++ /dev/null
@@ -1,425 +0,0 @@
-// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
-/*
- * Copyright (c) 2019 BayLibre, SAS
- * Author: Neil Armstrong <narmstrong@baylibre.com>
- * Copyright (c) 2019 Christian Hewitt <christianshewitt@gmail.com>
- */
-
-/dts-v1/;
-
-#include "meson-g12b.dtsi"
-#include "meson-g12b-s922x.dtsi"
-#include <dt-bindings/input/input.h>
-#include <dt-bindings/gpio/meson-g12a-gpio.h>
-
-/ {
- aliases {
- serial0 = &uart_AO;
- ethernet0 = ðmac;
- };
-
- chosen {
- stdout-path = "serial0:115200n8";
- };
-
- memory@0 {
- device_type = "memory";
- reg = <0x0 0x0 0x0 0x40000000>;
- };
-
- emmc_pwrseq: emmc-pwrseq {
- compatible = "mmc-pwrseq-emmc";
- reset-gpios = <&gpio BOOT_12 GPIO_ACTIVE_LOW>;
- };
-
- sdio_pwrseq: sdio-pwrseq {
- compatible = "mmc-pwrseq-simple";
- reset-gpios = <&gpio GPIOX_6 GPIO_ACTIVE_LOW>;
- clocks = <&wifi32k>;
- clock-names = "ext_clock";
- };
-
- flash_1v8: regulator-flash_1v8 {
- compatible = "regulator-fixed";
- regulator-name = "FLASH_1V8";
- regulator-min-microvolt = <1800000>;
- regulator-max-microvolt = <1800000>;
- vin-supply = <&vcc_3v3>;
- regulator-always-on;
- };
-
- main_12v: regulator-main_12v {
- compatible = "regulator-fixed";
- regulator-name = "12V";
- regulator-min-microvolt = <12000000>;
- regulator-max-microvolt = <12000000>;
- regulator-always-on;
- };
-
- vcc_5v: regulator-vcc_5v {
- compatible = "regulator-fixed";
- regulator-name = "VCC_5V";
- regulator-min-microvolt = <5000000>;
- regulator-max-microvolt = <5000000>;
- vin-supply = <&main_12v>;
-
- gpio = <&gpio GPIOH_8 GPIO_OPEN_DRAIN>;
- enable-active-high;
- };
-
- vcc_1v8: regulator-vcc_1v8 {
- compatible = "regulator-fixed";
- regulator-name = "VCC_1V8";
- regulator-min-microvolt = <1800000>;
- regulator-max-microvolt = <1800000>;
- vin-supply = <&vcc_3v3>;
- regulator-always-on;
- };
-
- vcc_3v3: regulator-vcc_3v3 {
- compatible = "regulator-fixed";
- regulator-name = "VCC_3V3";
- regulator-min-microvolt = <3300000>;
- regulator-max-microvolt = <3300000>;
- vin-supply = <&vddao_3v3>;
- regulator-always-on;
- /* FIXME: actually controlled by VDDCPU_B_EN */
- };
-
- vddcpu_a: regulator-vddcpu-a {
- /*
- * MP1653 Regulator.
- */
- compatible = "pwm-regulator";
-
- regulator-name = "VDDCPU_A";
- regulator-min-microvolt = <721000>;
- regulator-max-microvolt = <1022000>;
-
- vin-supply = <&main_12v>;
-
- pwms = <&pwm_ab 0 1250 0>;
- pwm-dutycycle-range = <100 0>;
-
- regulator-boot-on;
- regulator-always-on;
- };
-
- vddcpu_b: regulator-vddcpu-b {
- /*
- * MP1652 Regulator.
- */
- compatible = "pwm-regulator";
-
- regulator-name = "VDDCPU_B";
- regulator-min-microvolt = <721000>;
- regulator-max-microvolt = <1022000>;
-
- vin-supply = <&main_12v>;
-
- pwms = <&pwm_AO_cd 1 1250 0>;
- pwm-dutycycle-range = <100 0>;
-
- regulator-boot-on;
- regulator-always-on;
- };
-
- usb1_pow: regulator-usb1-pow {
- compatible = "regulator-fixed";
- regulator-name = "USB1_POW";
- regulator-min-microvolt = <5000000>;
- regulator-max-microvolt = <5000000>;
- vin-supply = <&vcc_5v>;
-
- /* connected to SY6280A Power Switch */
- gpio = <&gpio GPIOA_8 GPIO_ACTIVE_HIGH>;
- enable-active-high;
- };
-
- usb_pwr_en: regulator-usb-pwr-en {
- compatible = "regulator-fixed";
- regulator-name = "USB_PWR_EN";
- regulator-min-microvolt = <5000000>;
- regulator-max-microvolt = <5000000>;
- vin-supply = <&vcc_5v>;
-
- /* Connected to USB3 Type-A Port power enable */
- gpio = <&gpio GPIOAO_7 GPIO_ACTIVE_HIGH>;
- enable-active-high;
- };
-
- vddao_1v8: regulator-vddao-1v8 {
- compatible = "regulator-fixed";
- regulator-name = "VDDAO_1V8";
- regulator-min-microvolt = <1800000>;
- regulator-max-microvolt = <1800000>;
- vin-supply = <&vddao_3v3>;
- regulator-always-on;
- };
-
- vddao_3v3: regulator-vddao-3v3 {
- compatible = "regulator-fixed";
- regulator-name = "VDDAO_3V3";
- regulator-min-microvolt = <3300000>;
- regulator-max-microvolt = <3300000>;
- vin-supply = <&main_12v>;
- regulator-always-on;
- };
-
- cvbs-connector {
- compatible = "composite-video-connector";
-
- port {
- cvbs_connector_in: endpoint {
- remote-endpoint = <&cvbs_vdac_out>;
- };
- };
- };
-
- hdmi-connector {
- compatible = "hdmi-connector";
- type = "a";
-
- port {
- hdmi_connector_in: endpoint {
- remote-endpoint = <&hdmi_tx_tmds_out>;
- };
- };
- };
-
- wifi32k: wifi32k {
- compatible = "pwm-clock";
- #clock-cells = <0>;
- clock-frequency = <32768>;
- pwms = <&pwm_ef 0 30518 0>; /* PWM_E at 32.768KHz */
- };
-};
-
-&cec_AO {
- pinctrl-0 = <&cec_ao_a_h_pins>;
- pinctrl-names = "default";
- status = "disabled";
- hdmi-phandle = <&hdmi_tx>;
-};
-
-&cecb_AO {
- pinctrl-0 = <&cec_ao_b_h_pins>;
- pinctrl-names = "default";
- status = "okay";
- hdmi-phandle = <&hdmi_tx>;
-};
-
-&cpu0 {
- cpu-supply = <&vddcpu_b>;
- operating-points-v2 = <&cpu_opp_table_0>;
- clocks = <&clkc CLKID_CPU_CLK>;
- clock-latency = <50000>;
-};
-
-&cpu1 {
- cpu-supply = <&vddcpu_b>;
- operating-points-v2 = <&cpu_opp_table_0>;
- clocks = <&clkc CLKID_CPU_CLK>;
- clock-latency = <50000>;
-};
-
-&cpu100 {
- cpu-supply = <&vddcpu_a>;
- operating-points-v2 = <&cpub_opp_table_1>;
- clocks = <&clkc CLKID_CPUB_CLK>;
- clock-latency = <50000>;
-};
-
-&cpu101 {
- cpu-supply = <&vddcpu_a>;
- operating-points-v2 = <&cpub_opp_table_1>;
- clocks = <&clkc CLKID_CPUB_CLK>;
- clock-latency = <50000>;
-};
-
-&cpu102 {
- cpu-supply = <&vddcpu_a>;
- operating-points-v2 = <&cpub_opp_table_1>;
- clocks = <&clkc CLKID_CPUB_CLK>;
- clock-latency = <50000>;
-};
-
-&cpu103 {
- cpu-supply = <&vddcpu_a>;
- operating-points-v2 = <&cpub_opp_table_1>;
- clocks = <&clkc CLKID_CPUB_CLK>;
- clock-latency = <50000>;
-};
-
-&cvbs_vdac_port {
- cvbs_vdac_out: endpoint {
- remote-endpoint = <&cvbs_connector_in>;
- };
-};
-
-&ext_mdio {
- external_phy: ethernet-phy@0 {
- /* Realtek RTL8211F (0x001cc916) */
- reg = <0>;
- max-speed = <1000>;
-
- reset-assert-us = <10000>;
- reset-deassert-us = <80000>;
- reset-gpios = <&gpio GPIOZ_15 (GPIO_ACTIVE_LOW | GPIO_OPEN_DRAIN)>;
-
- interrupt-parent = <&gpio_intc>;
- /* MAC_INTR on GPIOZ_14 */
- interrupts = <26 IRQ_TYPE_LEVEL_LOW>;
- };
-};
-
-ðmac {
- pinctrl-0 = <ð_pins>, <ð_rgmii_pins>;
- pinctrl-names = "default";
- status = "okay";
- phy-mode = "rgmii";
- phy-handle = <&external_phy>;
- amlogic,tx-delay-ns = <2>;
-};
-
-&hdmi_tx {
- status = "okay";
- pinctrl-0 = <&hdmitx_hpd_pins>, <&hdmitx_ddc_pins>;
- pinctrl-names = "default";
- hdmi-supply = <&vcc_5v>;
-};
-
-&hdmi_tx_tmds_port {
- hdmi_tx_tmds_out: endpoint {
- remote-endpoint = <&hdmi_connector_in>;
- };
-};
-
-&ir {
- status = "okay";
- pinctrl-0 = <&remote_input_ao_pins>;
- pinctrl-names = "default";
-};
-
-&pwm_ab {
- pinctrl-0 = <&pwm_a_e_pins>;
- pinctrl-names = "default";
- clocks = <&xtal>;
- clock-names = "clkin0";
- status = "okay";
-};
-
-&pwm_AO_cd {
- pinctrl-0 = <&pwm_ao_d_e_pins>;
- pinctrl-names = "default";
- clocks = <&xtal>;
- clock-names = "clkin1";
- status = "okay";
-};
-
-&pwm_ef {
- pinctrl-0 = <&pwm_e_pins>;
- pinctrl-names = "default";
- clocks = <&xtal>;
- clock-names = "clkin0";
- status = "okay";
-};
-
-/* SDIO */
-&sd_emmc_a {
- status = "okay";
- pinctrl-0 = <&sdio_pins>;
- pinctrl-1 = <&sdio_clk_gate_pins>;
- pinctrl-names = "default", "clk-gate";
- #address-cells = <1>;
- #size-cells = <0>;
-
- bus-width = <4>;
- cap-sd-highspeed;
- max-frequency = <100000000>;
-
- /* WiFi firmware requires power to be kept while in suspend */
- keep-power-in-suspend;
-
- non-removable;
- disable-wp;
-
- mmc-pwrseq = <&sdio_pwrseq>;
-
- vmmc-supply = <&vddao_3v3>;
- vqmmc-supply = <&vddao_1v8>;
-
- brcmf: wifi@1 {
- reg = <1>;
- compatible = "brcm,bcm4329-fmac";
- };
-};
-
-/* SD card */
-&sd_emmc_b {
- status = "okay";
- pinctrl-0 = <&sdcard_c_pins>;
- pinctrl-1 = <&sdcard_clk_gate_c_pins>;
- pinctrl-names = "default", "clk-gate";
-
- bus-width = <4>;
- cap-sd-highspeed;
- max-frequency = <50000000>;
- disable-wp;
-
- cd-gpios = <&gpio GPIOC_6 GPIO_ACTIVE_LOW>;
- vmmc-supply = <&vddao_3v3>;
- vqmmc-supply = <&vddao_3v3>;
-};
-
-/* eMMC */
-&sd_emmc_c {
- status = "okay";
- pinctrl-0 = <&emmc_ctrl_pins>, <&emmc_data_8b_pins>, <&emmc_ds_pins>;
- pinctrl-1 = <&emmc_clk_gate_pins>;
- pinctrl-names = "default", "clk-gate";
-
- bus-width = <8>;
- cap-mmc-highspeed;
- max-frequency = <100000000>;
- disable-wp;
-
- mmc-pwrseq = <&emmc_pwrseq>;
- vmmc-supply = <&vcc_3v3>;
- vqmmc-supply = <&flash_1v8>;
-};
-
-&uart_A {
- status = "okay";
- pinctrl-0 = <&uart_a_pins>, <&uart_a_cts_rts_pins>;
- pinctrl-names = "default";
- uart-has-rtscts;
-
- bluetooth {
- compatible = "brcm,bcm43438-bt";
- shutdown-gpios = <&gpio GPIOX_17 GPIO_ACTIVE_HIGH>;
- max-speed = <2000000>;
- clocks = <&wifi32k>;
- clock-names = "lpo";
- };
-};
-
-&uart_AO {
- status = "okay";
- pinctrl-0 = <&uart_ao_a_pins>;
- pinctrl-names = "default";
-};
-
-&usb {
- status = "okay";
- dr_mode = "host";
- vbus-supply = <&usb_pwr_en>;
-};
-
-&usb2_phy0 {
- phy-supply = <&usb1_pow>;
-};
-
-&usb2_phy1 {
- phy-supply = <&usb1_pow>;
-};
diff --git a/arch/arm/dts/meson-g12b.dtsi b/arch/arm/dts/meson-g12b.dtsi
deleted file mode 100644
index 75ff00f..0000000
--- a/arch/arm/dts/meson-g12b.dtsi
+++ /dev/null
@@ -1,146 +0,0 @@
-// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
-/*
- * Copyright (c) 2019 BayLibre, SAS
- * Author: Neil Armstrong <narmstrong@baylibre.com>
- */
-
-#include "meson-g12.dtsi"
-
-/ {
- compatible = "amlogic,g12b";
-
- cpus {
- #address-cells = <0x2>;
- #size-cells = <0x0>;
-
- cpu-map {
- cluster0 {
- core0 {
- cpu = <&cpu0>;
- };
-
- core1 {
- cpu = <&cpu1>;
- };
- };
-
- cluster1 {
- core0 {
- cpu = <&cpu100>;
- };
-
- core1 {
- cpu = <&cpu101>;
- };
-
- core2 {
- cpu = <&cpu102>;
- };
-
- core3 {
- cpu = <&cpu103>;
- };
- };
- };
-
- cpu0: cpu@0 {
- device_type = "cpu";
- compatible = "arm,cortex-a53";
- reg = <0x0 0x0>;
- enable-method = "psci";
- capacity-dmips-mhz = <592>;
- next-level-cache = <&l2>;
- #cooling-cells = <2>;
- };
-
- cpu1: cpu@1 {
- device_type = "cpu";
- compatible = "arm,cortex-a53";
- reg = <0x0 0x1>;
- enable-method = "psci";
- capacity-dmips-mhz = <592>;
- next-level-cache = <&l2>;
- #cooling-cells = <2>;
- };
-
- cpu100: cpu@100 {
- device_type = "cpu";
- compatible = "arm,cortex-a73";
- reg = <0x0 0x100>;
- enable-method = "psci";
- capacity-dmips-mhz = <1024>;
- next-level-cache = <&l2>;
- #cooling-cells = <2>;
- };
-
- cpu101: cpu@101 {
- device_type = "cpu";
- compatible = "arm,cortex-a73";
- reg = <0x0 0x101>;
- enable-method = "psci";
- capacity-dmips-mhz = <1024>;
- next-level-cache = <&l2>;
- #cooling-cells = <2>;
- };
-
- cpu102: cpu@102 {
- device_type = "cpu";
- compatible = "arm,cortex-a73";
- reg = <0x0 0x102>;
- enable-method = "psci";
- capacity-dmips-mhz = <1024>;
- next-level-cache = <&l2>;
- #cooling-cells = <2>;
- };
-
- cpu103: cpu@103 {
- device_type = "cpu";
- compatible = "arm,cortex-a73";
- reg = <0x0 0x103>;
- enable-method = "psci";
- capacity-dmips-mhz = <1024>;
- next-level-cache = <&l2>;
- #cooling-cells = <2>;
- };
-
- l2: l2-cache0 {
- compatible = "cache";
- cache-level = <2>;
- };
- };
-};
-
-&clkc {
- compatible = "amlogic,g12b-clkc";
-};
-
-&cpu_thermal {
- cooling-maps {
- map0 {
- trip = <&cpu_passive>;
- cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
- <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
- <&cpu100 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
- <&cpu101 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
- <&cpu102 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
- <&cpu103 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
- };
- map1 {
- trip = <&cpu_hot>;
- cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
- <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
- <&cpu100 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
- <&cpu101 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
- <&cpu102 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
- <&cpu103 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
- };
- };
-};
-
-&mali {
- dma-coherent;
-};
-
-&pmu {
- compatible = "amlogic,g12b-ddr-pmu";
-};
diff --git a/arch/arm/dts/meson-gx-libretech-pc.dtsi b/arch/arm/dts/meson-gx-libretech-pc.dtsi
deleted file mode 100644
index 4e84ab8..0000000
--- a/arch/arm/dts/meson-gx-libretech-pc.dtsi
+++ /dev/null
@@ -1,447 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0
-/*
- * Copyright (c) 2019 BayLibre SAS.
- * Author: Jerome Brunet <jbrunet@baylibre.com>
- */
-
-/* Libretech Amlogic GX PC form factor - AKA: Tartiflette */
-
-#include <dt-bindings/input/input.h>
-#include <dt-bindings/leds/common.h>
-#include <dt-bindings/sound/meson-aiu.h>
-
-/ {
- adc-keys {
- compatible = "adc-keys";
- io-channels = <&saradc 0>;
- io-channel-names = "buttons";
- keyup-threshold-microvolt = <1800000>;
-
- button-update {
- label = "update";
- linux,code = <KEY_VENDOR>;
- press-threshold-microvolt = <1300000>;
- };
- };
-
- aliases {
- serial0 = &uart_AO;
- ethernet0 = ðmac;
- spi0 = &spifc;
- };
-
- dio2133: analog-amplifier {
- compatible = "simple-audio-amplifier";
- sound-name-prefix = "AU2";
- VCC-supply = <&vcc5v>;
- enable-gpios = <&gpio GPIOH_5 GPIO_ACTIVE_HIGH>;
- };
-
- chosen {
- stdout-path = "serial0:115200n8";
- };
-
- cvbs-connector {
- compatible = "composite-video-connector";
- status = "disabled";
-
- port {
- cvbs_connector_in: endpoint {
- remote-endpoint = <&cvbs_vdac_out>;
- };
- };
- };
-
- emmc_pwrseq: emmc-pwrseq {
- compatible = "mmc-pwrseq-emmc";
- reset-gpios = <&gpio BOOT_9 GPIO_ACTIVE_LOW>;
- };
-
- hdmi-connector {
- compatible = "hdmi-connector";
- type = "a";
-
- port {
- hdmi_connector_in: endpoint {
- remote-endpoint = <&hdmi_tx_tmds_out>;
- };
- };
- };
-
- gpio-keys-polled {
- compatible = "gpio-keys-polled";
- poll-interval = <100>;
-
- power-button {
- label = "power";
- linux,code = <KEY_POWER>;
- gpios = <&gpio_ao GPIOAO_2 GPIO_ACTIVE_LOW>;
- };
- };
-
- memory@0 {
- device_type = "memory";
- reg = <0x0 0x0 0x0 0x80000000>;
- };
-
- ao_5v: regulator-ao_5v {
- compatible = "regulator-fixed";
- regulator-name = "AO_5V";
- regulator-min-microvolt = <5000000>;
- regulator-max-microvolt = <5000000>;
- vin-supply = <&dc_in>;
- regulator-always-on;
- };
-
- dc_in: regulator-dc_in {
- compatible = "regulator-fixed";
- regulator-name = "DC_IN";
- regulator-min-microvolt = <5000000>;
- regulator-max-microvolt = <5000000>;
- regulator-always-on;
- };
-
- leds {
- compatible = "gpio-leds";
-
- led-green {
- color = <LED_COLOR_ID_GREEN>;
- function = LED_FUNCTION_DISK_ACTIVITY;
- gpios = <&gpio_ao GPIOAO_9 GPIO_ACTIVE_HIGH>;
- linux,default-trigger = "disk-activity";
- };
-
- led-blue {
- color = <LED_COLOR_ID_BLUE>;
- function = LED_FUNCTION_STATUS;
- gpios = <&gpio GPIODV_28 GPIO_ACTIVE_HIGH>;
- linux,default-trigger = "heartbeat";
- panic-indicator;
- };
- };
-
- vcc_card: regulator-vcc_card {
- compatible = "regulator-fixed";
- regulator-name = "VCC_CARD";
- regulator-min-microvolt = <3300000>;
- regulator-max-microvolt = <3300000>;
- vin-supply = <&vddio_ao3v3>;
-
- gpio = <&gpio GPIODV_4 GPIO_ACTIVE_HIGH>;
- enable-active-high;
- };
-
- vcc5v: regulator-vcc5v {
- compatible = "regulator-fixed";
- regulator-name = "VCC5V";
- regulator-min-microvolt = <5000000>;
- regulator-max-microvolt = <5000000>;
- vin-supply = <&ao_5v>;
-
- gpio = <&gpio GPIOH_3 GPIO_OPEN_DRAIN>;
- };
-
- vddio_ao18: regulator-vddio_ao18 {
- compatible = "regulator-fixed";
- regulator-name = "VDDIO_AO18";
- regulator-min-microvolt = <1800000>;
- regulator-max-microvolt = <1800000>;
- vin-supply = <&ao_5v>;
- regulator-always-on;
- };
-
- vddio_ao3v3: regulator-vddio_ao3v3 {
- compatible = "regulator-fixed";
- regulator-name = "VDDIO_AO3V3";
- regulator-min-microvolt = <3300000>;
- regulator-max-microvolt = <3300000>;
- vin-supply = <&ao_5v>;
- regulator-always-on;
- };
-
- vddio_boot: regulator-vddio_boot {
- compatible = "regulator-fixed";
- regulator-name = "VDDIO_BOOT";
- regulator-min-microvolt = <1800000>;
- regulator-max-microvolt = <1800000>;
- vin-supply = <&vddio_ao3v3>;
- regulator-always-on;
- };
-
- vddio_card: regulator-vddio-card {
- compatible = "regulator-gpio";
- regulator-name = "VDDIO_CARD";
- regulator-min-microvolt = <1800000>;
- regulator-max-microvolt = <3300000>;
-
- gpios = <&gpio GPIODV_5 GPIO_ACTIVE_HIGH>;
- gpios-states = <0>;
-
- states = <3300000 0>,
- <1800000 1>;
-
- regulator-settling-time-up-us = <200>;
- regulator-settling-time-down-us = <50000>;
- };
-
- sound {
- compatible = "amlogic,gx-sound-card";
- model = "LIBRETECH-PC";
- audio-aux-devs = <&dio2133>;
- audio-widgets = "Speaker", "7J4-14 LEFT",
- "Speaker", "7J4-11 RIGHT";
- audio-routing = "AU2 INL", "ACODEC LOLN",
- "AU2 INR", "ACODEC LORN",
- "7J4-14 LEFT", "AU2 OUTL",
- "7J4-11 RIGHT", "AU2 OUTR";
- assigned-clocks = <&clkc CLKID_MPLL0>,
- <&clkc CLKID_MPLL1>,
- <&clkc CLKID_MPLL2>;
- assigned-clock-parents = <0>, <0>, <0>;
- assigned-clock-rates = <294912000>,
- <270950400>,
- <393216000>;
- status = "okay";
-
- dai-link-0 {
- sound-dai = <&aiu AIU_CPU CPU_I2S_FIFO>;
- };
-
- dai-link-1 {
- sound-dai = <&aiu AIU_CPU CPU_I2S_ENCODER>;
- dai-format = "i2s";
- mclk-fs = <256>;
-
- codec-0 {
- sound-dai = <&aiu AIU_HDMI CTRL_I2S>;
- };
-
- codec-1 {
- sound-dai = <&aiu AIU_ACODEC CTRL_I2S>;
- };
- };
-
- dai-link-2 {
- sound-dai = <&aiu AIU_HDMI CTRL_OUT>;
-
- codec-0 {
- sound-dai = <&hdmi_tx>;
- };
- };
-
- dai-link-3 {
- sound-dai = <&aiu AIU_ACODEC CTRL_OUT>;
-
- codec-0 {
- sound-dai = <&acodec>;
- };
- };
- };
-};
-
-&acodec {
- AVDD-supply = <&vddio_ao18>;
- status = "okay";
-};
-
-&aiu {
- status = "okay";
-};
-
-&cec_AO {
- pinctrl-0 = <&ao_cec_pins>;
- pinctrl-names = "default";
- hdmi-phandle = <&hdmi_tx>;
- status = "okay";
-};
-
-&cvbs_vdac_port {
- cvbs_vdac_out: endpoint {
- remote-endpoint = <&cvbs_connector_in>;
- };
-};
-
-ðmac {
- pinctrl-0 = <ð_pins>, <ð_phy_irq_pins>;
- pinctrl-names = "default";
- phy-handle = <&external_phy>;
- amlogic,tx-delay-ns = <2>;
- phy-mode = "rgmii";
- status = "okay";
-};
-
-&external_mdio {
- external_phy: ethernet-phy@0 {
- reg = <0>;
- max-speed = <1000>;
- reset-assert-us = <10000>;
- reset-deassert-us = <30000>;
- reset-gpios = <&gpio GPIOZ_14 GPIO_ACTIVE_LOW>;
- interrupt-parent = <&gpio_intc>;
- interrupts = <25 IRQ_TYPE_LEVEL_LOW>;
- };
-};
-
-&pinctrl_periphs {
- /*
- * Make sure the reset pin of the usb HUB is driven high to take
- * it out of reset.
- */
- usb1_rst_pins: usb1_rst_irq {
- mux {
- groups = "GPIODV_3";
- function = "gpio_periphs";
- bias-disable;
- output-high;
- };
- };
-
- /* Make sure the phy irq pin is properly configured as input */
- eth_phy_irq_pins: eth_phy_irq {
- mux {
- groups = "GPIOZ_15";
- function = "gpio_periphs";
- bias-disable;
- output-disable;
- };
- };
-};
-
-&hdmi_tx {
- pinctrl-0 = <&hdmi_hpd_pins>, <&hdmi_i2c_pins>;
- pinctrl-names = "default";
- hdmi-supply = <&vcc5v>;
- status = "okay";
-};
-
-&hdmi_tx_tmds_port {
- hdmi_tx_tmds_out: endpoint {
- remote-endpoint = <&hdmi_connector_in>;
- };
-};
-
-&ir {
- pinctrl-0 = <&remote_input_ao_pins>;
- pinctrl-names = "default";
- status = "okay";
-};
-
-&i2c_C {
- pinctrl-0 = <&i2c_c_dv18_pins>;
- pinctrl-names = "default";
- status = "okay";
-
- rtc: rtc@51 {
- reg = <0x51>;
- compatible = "nxp,pcf8563";
- #clock-cells = <0>;
- clock-output-names = "rtc_clkout";
- };
-};
-
-&pwm_AO_ab {
- pinctrl-0 = <&pwm_ao_a_3_pins>;
- pinctrl-names = "default";
- clocks = <&clkc CLKID_FCLK_DIV4>;
- clock-names = "clkin0";
- status = "okay";
-};
-
-&pwm_ab {
- pinctrl-0 = <&pwm_b_pins>;
- pinctrl-names = "default";
- clocks = <&clkc CLKID_FCLK_DIV4>;
- clock-names = "clkin0";
- status = "okay";
-};
-
-&pwm_ef {
- pinctrl-0 = <&pwm_e_pins>, <&pwm_f_clk_pins>;
- pinctrl-names = "default";
- clocks = <&clkc CLKID_FCLK_DIV4>;
- clock-names = "clkin0";
- status = "okay";
-};
-
-&saradc {
- vref-supply = <&vddio_ao18>;
- status = "okay";
-};
-
-/* SD card */
-&sd_emmc_b {
- pinctrl-0 = <&sdcard_pins>;
- pinctrl-1 = <&sdcard_clk_gate_pins>;
- pinctrl-names = "default", "clk-gate";
-
- bus-width = <4>;
- cap-sd-highspeed;
- sd-uhs-sdr12;
- sd-uhs-sdr25;
- sd-uhs-sdr50;
- sd-uhs-ddr50;
- max-frequency = <200000000>;
- disable-wp;
-
- cd-gpios = <&gpio CARD_6 GPIO_ACTIVE_LOW>;
-
- vmmc-supply = <&vcc_card>;
- vqmmc-supply = <&vddio_card>;
-
- status = "okay";
-};
-
-/* eMMC */
-&sd_emmc_c {
- pinctrl-0 = <&emmc_pins>;
- pinctrl-1 = <&emmc_clk_gate_pins>;
- pinctrl-names = "default", "clk-gate";
-
- bus-width = <8>;
- cap-mmc-highspeed;
- mmc-ddr-1_8v;
- mmc-hs200-1_8v;
- max-frequency = <200000000>;
- disable-wp;
-
- mmc-pwrseq = <&emmc_pwrseq>;
- vmmc-supply = <&vddio_ao3v3>;
- vqmmc-supply = <&vddio_boot>;
-
- status = "okay";
-};
-
-&spifc {
- pinctrl-0 = <&nor_pins>;
- pinctrl-names = "default";
- status = "okay";
-
- gd25lq128: flash@0 {
- compatible = "jedec,spi-nor";
- #address-cells = <1>;
- #size-cells = <1>;
- reg = <0>;
- spi-max-frequency = <12000000>;
- };
-};
-
-&uart_AO {
- pinctrl-0 = <&uart_ao_a_pins>;
- pinctrl-names = "default";
- status = "okay";
-};
-
-&usb {
- status = "okay";
- dr_mode = "host";
-};
-
-&usb2_phy0 {
- pinctrl-0 = <&usb1_rst_pins>;
- pinctrl-names = "default";
- phy-supply = <&vcc5v>;
-};
-
-&usb2_phy1 {
- phy-supply = <&vcc5v>;
-};
diff --git a/arch/arm/dts/meson-gx-mali450.dtsi b/arch/arm/dts/meson-gx-mali450.dtsi
deleted file mode 100644
index f9771b5..0000000
--- a/arch/arm/dts/meson-gx-mali450.dtsi
+++ /dev/null
@@ -1,61 +0,0 @@
-// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
-/*
- * Copyright (c) 2017 BayLibre SAS
- * Author: Neil Armstrong <narmstrong@baylibre.com>
- */
-
-/ {
- gpu_opp_table: opp-table {
- compatible = "operating-points-v2";
-
- opp-125000000 {
- opp-hz = /bits/ 64 <125000000>;
- opp-microvolt = <950000>;
- };
- opp-250000000 {
- opp-hz = /bits/ 64 <250000000>;
- opp-microvolt = <950000>;
- };
- opp-285714285 {
- opp-hz = /bits/ 64 <285714285>;
- opp-microvolt = <950000>;
- };
- opp-400000000 {
- opp-hz = /bits/ 64 <400000000>;
- opp-microvolt = <950000>;
- };
- opp-500000000 {
- opp-hz = /bits/ 64 <500000000>;
- opp-microvolt = <950000>;
- };
- opp-666666666 {
- opp-hz = /bits/ 64 <666666666>;
- opp-microvolt = <950000>;
- };
- opp-744000000 {
- opp-hz = /bits/ 64 <744000000>;
- opp-microvolt = <950000>;
- };
- };
-};
-
-&apb {
- mali: gpu@c0000 {
- compatible = "arm,mali-450";
- reg = <0x0 0xc0000 0x0 0x40000>;
- interrupts = <GIC_SPI 160 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 161 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 162 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 163 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 164 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 165 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 166 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 167 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 168 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 169 IRQ_TYPE_LEVEL_HIGH>;
- interrupt-names = "gp", "gpmmu", "pp", "pmu",
- "pp0", "ppmmu0", "pp1", "ppmmu1",
- "pp2", "ppmmu2";
- operating-points-v2 = <&gpu_opp_table>;
- };
-};
diff --git a/arch/arm/dts/meson-gx-p23x-q20x.dtsi b/arch/arm/dts/meson-gx-p23x-q20x.dtsi
deleted file mode 100644
index dafc841..0000000
--- a/arch/arm/dts/meson-gx-p23x-q20x.dtsi
+++ /dev/null
@@ -1,324 +0,0 @@
-// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
-/*
- * Copyright (c) 2016 Endless Computers, Inc.
- * Author: Carlo Caione <carlo@endlessm.com>
- */
-
-/* Common DTSI for same Amlogic Q200/Q201 and P230/P231 boards using either
- * the pin-compatible S912 (GXM) or S905D (GXL) SoCs.
- */
-
-#include <dt-bindings/sound/meson-aiu.h>
-
-/ {
- aliases {
- serial0 = &uart_AO;
- ethernet0 = ðmac;
- };
-
- dio2133: analog-amplifier {
- compatible = "simple-audio-amplifier";
- sound-name-prefix = "AU2";
- VCC-supply = <&hdmi_5v>;
- enable-gpios = <&gpio GPIOH_5 GPIO_ACTIVE_HIGH>;
- };
-
- spdif_dit: audio-codec-0 {
- #sound-dai-cells = <0>;
- compatible = "linux,spdif-dit";
- status = "okay";
- sound-name-prefix = "DIT";
- };
-
- chosen {
- stdout-path = "serial0:115200n8";
- };
-
- memory@0 {
- device_type = "memory";
- reg = <0x0 0x0 0x0 0x80000000>;
- };
-
- hdmi_5v: regulator-hdmi-5v {
- compatible = "regulator-fixed";
-
- regulator-name = "HDMI_5V";
- regulator-min-microvolt = <5000000>;
- regulator-max-microvolt = <5000000>;
-
- gpio = <&gpio GPIOH_3 GPIO_ACTIVE_HIGH>;
- enable-active-high;
- regulator-always-on;
- };
-
- vddio_ao18: regulator-vddio_ao18 {
- compatible = "regulator-fixed";
- regulator-name = "VDDIO_AO18";
- regulator-min-microvolt = <1800000>;
- regulator-max-microvolt = <1800000>;
- };
-
- vddio_boot: regulator-vddio_boot {
- compatible = "regulator-fixed";
- regulator-name = "VDDIO_BOOT";
- regulator-min-microvolt = <1800000>;
- regulator-max-microvolt = <1800000>;
- };
-
- vddao_3v3: regulator-vddao_3v3 {
- compatible = "regulator-fixed";
- regulator-name = "VDDAO_3V3";
- regulator-min-microvolt = <3300000>;
- regulator-max-microvolt = <3300000>;
- };
-
- vcc_3v3: regulator-vcc_3v3 {
- compatible = "regulator-fixed";
- regulator-name = "VCC_3V3";
- regulator-min-microvolt = <3300000>;
- regulator-max-microvolt = <3300000>;
- };
-
- emmc_pwrseq: emmc-pwrseq {
- compatible = "mmc-pwrseq-emmc";
- reset-gpios = <&gpio BOOT_9 GPIO_ACTIVE_LOW>;
- };
-
- wifi32k: wifi32k {
- compatible = "pwm-clock";
- #clock-cells = <0>;
- clock-frequency = <32768>;
- pwms = <&pwm_ef 0 30518 0>; /* PWM_E at 32.768KHz */
- };
-
- sdio_pwrseq: sdio-pwrseq {
- compatible = "mmc-pwrseq-simple";
- reset-gpios = <&gpio GPIOX_6 GPIO_ACTIVE_LOW>;
- clocks = <&wifi32k>;
- clock-names = "ext_clock";
- };
-
- cvbs-connector {
- compatible = "composite-video-connector";
-
- port {
- cvbs_connector_in: endpoint {
- remote-endpoint = <&cvbs_vdac_out>;
- };
- };
- };
-
- hdmi-connector {
- compatible = "hdmi-connector";
- type = "a";
-
- port {
- hdmi_connector_in: endpoint {
- remote-endpoint = <&hdmi_tx_tmds_out>;
- };
- };
- };
-
- sound {
- compatible = "amlogic,gx-sound-card";
- model = "P230-Q200";
- audio-aux-devs = <&dio2133>;
- audio-widgets = "Line", "Lineout";
- audio-routing = "AU2 INL", "ACODEC LOLP",
- "AU2 INR", "ACODEC LORP",
- "AU2 INL", "ACODEC LOLN",
- "AU2 INR", "ACODEC LORN",
- "Lineout", "AU2 OUTL",
- "Lineout", "AU2 OUTR";
- assigned-clocks = <&clkc CLKID_MPLL0>,
- <&clkc CLKID_MPLL1>,
- <&clkc CLKID_MPLL2>;
- assigned-clock-parents = <0>, <0>, <0>;
- assigned-clock-rates = <294912000>,
- <270950400>,
- <393216000>;
- status = "okay";
-
- dai-link-0 {
- sound-dai = <&aiu AIU_CPU CPU_I2S_FIFO>;
- };
-
- dai-link-1 {
- sound-dai = <&aiu AIU_CPU CPU_SPDIF_FIFO>;
- };
-
- dai-link-2 {
- sound-dai = <&aiu AIU_CPU CPU_I2S_ENCODER>;
- dai-format = "i2s";
- mclk-fs = <256>;
-
- codec-0 {
- sound-dai = <&aiu AIU_HDMI CTRL_I2S>;
- };
-
- codec-1 {
- sound-dai = <&aiu AIU_ACODEC CTRL_I2S>;
- };
- };
-
- dai-link-3 {
- sound-dai = <&aiu AIU_CPU CPU_SPDIF_ENCODER>;
-
- codec-0 {
- sound-dai = <&spdif_dit>;
- };
- };
-
- dai-link-4 {
- sound-dai = <&aiu AIU_HDMI CTRL_OUT>;
-
- codec-0 {
- sound-dai = <&hdmi_tx>;
- };
- };
-
- dai-link-5 {
- sound-dai = <&aiu AIU_ACODEC CTRL_OUT>;
-
- codec-0 {
- sound-dai = <&acodec>;
- };
- };
- };
-};
-
-&acodec {
- AVDD-supply = <&vddio_ao18>;
- status = "okay";
-};
-
-&aiu {
- status = "okay";
- pinctrl-0 = <&spdif_out_h_pins>;
- pinctrl-names = "default";
-
-};
-
-&cec_AO {
- status = "okay";
- pinctrl-0 = <&ao_cec_pins>;
- pinctrl-names = "default";
- hdmi-phandle = <&hdmi_tx>;
-};
-
-&cvbs_vdac_port {
- cvbs_vdac_out: endpoint {
- remote-endpoint = <&cvbs_connector_in>;
- };
-};
-
-ðmac {
- status = "okay";
-};
-
-&hdmi_tx {
- status = "okay";
- pinctrl-0 = <&hdmi_hpd_pins>, <&hdmi_i2c_pins>;
- pinctrl-names = "default";
- hdmi-supply = <&hdmi_5v>;
-};
-
-&hdmi_tx_tmds_port {
- hdmi_tx_tmds_out: endpoint {
- remote-endpoint = <&hdmi_connector_in>;
- };
-};
-
-&ir {
- status = "okay";
- pinctrl-0 = <&remote_input_ao_pins>;
- pinctrl-names = "default";
-};
-
-&pwm_ef {
- status = "okay";
- pinctrl-0 = <&pwm_e_pins>;
- pinctrl-names = "default";
- clocks = <&clkc CLKID_FCLK_DIV4>;
- clock-names = "clkin0";
-};
-
-&saradc {
- status = "okay";
- vref-supply = <&vddio_ao18>;
-};
-
-/* Wireless SDIO Module */
-&sd_emmc_a {
- status = "okay";
- pinctrl-0 = <&sdio_pins>;
- pinctrl-1 = <&sdio_clk_gate_pins>;
- pinctrl-names = "default", "clk-gate";
- #address-cells = <1>;
- #size-cells = <0>;
-
- bus-width = <4>;
- cap-sd-highspeed;
- max-frequency = <50000000>;
-
- non-removable;
- disable-wp;
-
- /* WiFi firmware requires power to be kept while in suspend */
- keep-power-in-suspend;
-
- mmc-pwrseq = <&sdio_pwrseq>;
-
- vmmc-supply = <&vddao_3v3>;
- vqmmc-supply = <&vddio_boot>;
-};
-
-/* SD card */
-&sd_emmc_b {
- status = "okay";
- pinctrl-0 = <&sdcard_pins>;
- pinctrl-1 = <&sdcard_clk_gate_pins>;
- pinctrl-names = "default", "clk-gate";
-
- bus-width = <4>;
- cap-sd-highspeed;
- max-frequency = <50000000>;
- disable-wp;
-
- cd-gpios = <&gpio CARD_6 GPIO_ACTIVE_LOW>;
-
- vmmc-supply = <&vddao_3v3>;
- vqmmc-supply = <&vddio_boot>;
-};
-
-/* eMMC */
-&sd_emmc_c {
- status = "okay";
- pinctrl-0 = <&emmc_pins>, <&emmc_ds_pins>;
- pinctrl-1 = <&emmc_clk_gate_pins>;
- pinctrl-names = "default", "clk-gate";
-
- bus-width = <8>;
- cap-mmc-highspeed;
- max-frequency = <200000000>;
- non-removable;
- disable-wp;
- mmc-ddr-1_8v;
- mmc-hs200-1_8v;
-
- mmc-pwrseq = <&emmc_pwrseq>;
- vmmc-supply = <&vcc_3v3>;
- vqmmc-supply = <&vddio_boot>;
-};
-
-/* This UART is brought out to the DB9 connector */
-&uart_AO {
- status = "okay";
- pinctrl-0 = <&uart_ao_a_pins>;
- pinctrl-names = "default";
-};
-
-&usb {
- status = "okay";
- dr_mode = "otg";
-};
diff --git a/arch/arm/dts/meson-gx.dtsi b/arch/arm/dts/meson-gx.dtsi
deleted file mode 100644
index 11f89bf..0000000
--- a/arch/arm/dts/meson-gx.dtsi
+++ /dev/null
@@ -1,675 +0,0 @@
-// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
-/*
- * Copyright (c) 2016 Andreas Färber
- *
- * Copyright (c) 2016 BayLibre, SAS.
- * Author: Neil Armstrong <narmstrong@baylibre.com>
- *
- * Copyright (c) 2016 Endless Computers, Inc.
- * Author: Carlo Caione <carlo@endlessm.com>
- */
-
-#include <dt-bindings/gpio/gpio.h>
-#include <dt-bindings/interrupt-controller/irq.h>
-#include <dt-bindings/interrupt-controller/arm-gic.h>
-#include <dt-bindings/power/meson-gxbb-power.h>
-#include <dt-bindings/thermal/thermal.h>
-
-/ {
- interrupt-parent = <&gic>;
- #address-cells = <2>;
- #size-cells = <2>;
-
- aliases {
- mmc0 = &sd_emmc_b; /* SD card */
- mmc1 = &sd_emmc_c; /* eMMC */
- mmc2 = &sd_emmc_a; /* SDIO */
- };
-
- reserved-memory {
- #address-cells = <2>;
- #size-cells = <2>;
- ranges;
-
- /* 16 MiB reserved for Hardware ROM Firmware */
- hwrom_reserved: hwrom@0 {
- reg = <0x0 0x0 0x0 0x1000000>;
- no-map;
- };
-
- /* 2 MiB reserved for ARM Trusted Firmware (BL31) */
- secmon_reserved: secmon@10000000 {
- reg = <0x0 0x10000000 0x0 0x200000>;
- no-map;
- };
-
- /* Alternate 3 MiB reserved for ARM Trusted Firmware (BL31) */
- secmon_reserved_alt: secmon@5000000 {
- reg = <0x0 0x05000000 0x0 0x300000>;
- no-map;
- };
-
- /* 32 MiB reserved for ARM Trusted Firmware (BL32) */
- secmon_reserved_bl32: secmon@5300000 {
- reg = <0x0 0x05300000 0x0 0x2000000>;
- no-map;
- };
-
- linux,cma {
- compatible = "shared-dma-pool";
- reusable;
- size = <0x0 0x10000000>;
- alignment = <0x0 0x400000>;
- linux,cma-default;
- };
- };
-
- chosen {
- #address-cells = <2>;
- #size-cells = <2>;
- ranges;
-
- simplefb_cvbs: framebuffer-cvbs {
- compatible = "amlogic,simple-framebuffer",
- "simple-framebuffer";
- amlogic,pipeline = "vpu-cvbs";
- power-domains = <&pwrc PWRC_GXBB_VPU_ID>;
- status = "disabled";
- };
-
- simplefb_hdmi: framebuffer-hdmi {
- compatible = "amlogic,simple-framebuffer",
- "simple-framebuffer";
- amlogic,pipeline = "vpu-hdmi";
- power-domains = <&pwrc PWRC_GXBB_VPU_ID>;
- status = "disabled";
- };
- };
-
- cpus {
- #address-cells = <0x2>;
- #size-cells = <0x0>;
-
- cpu0: cpu@0 {
- device_type = "cpu";
- compatible = "arm,cortex-a53";
- reg = <0x0 0x0>;
- enable-method = "psci";
- next-level-cache = <&l2>;
- clocks = <&scpi_dvfs 0>;
- #cooling-cells = <2>;
- };
-
- cpu1: cpu@1 {
- device_type = "cpu";
- compatible = "arm,cortex-a53";
- reg = <0x0 0x1>;
- enable-method = "psci";
- next-level-cache = <&l2>;
- clocks = <&scpi_dvfs 0>;
- #cooling-cells = <2>;
- };
-
- cpu2: cpu@2 {
- device_type = "cpu";
- compatible = "arm,cortex-a53";
- reg = <0x0 0x2>;
- enable-method = "psci";
- next-level-cache = <&l2>;
- clocks = <&scpi_dvfs 0>;
- #cooling-cells = <2>;
- };
-
- cpu3: cpu@3 {
- device_type = "cpu";
- compatible = "arm,cortex-a53";
- reg = <0x0 0x3>;
- enable-method = "psci";
- next-level-cache = <&l2>;
- clocks = <&scpi_dvfs 0>;
- #cooling-cells = <2>;
- };
-
- l2: l2-cache0 {
- compatible = "cache";
- cache-level = <2>;
- };
- };
-
- thermal-zones {
- cpu-thermal {
- polling-delay-passive = <250>; /* milliseconds */
- polling-delay = <1000>; /* milliseconds */
-
- thermal-sensors = <&scpi_sensors 0>;
-
- trips {
- cpu_passive: cpu-passive {
- temperature = <80000>; /* millicelsius */
- hysteresis = <2000>; /* millicelsius */
- type = "passive";
- };
-
- cpu_hot: cpu-hot {
- temperature = <90000>; /* millicelsius */
- hysteresis = <2000>; /* millicelsius */
- type = "hot";
- };
-
- cpu_critical: cpu-critical {
- temperature = <110000>; /* millicelsius */
- hysteresis = <2000>; /* millicelsius */
- type = "critical";
- };
- };
-
- cpu_cooling_maps: cooling-maps {
- map0 {
- trip = <&cpu_passive>;
- cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
- <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
- <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
- <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
- };
-
- map1 {
- trip = <&cpu_hot>;
- cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
- <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
- <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
- <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
- };
- };
- };
- };
-
- arm-pmu {
- compatible = "arm,cortex-a53-pmu";
- interrupts = <GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>;
- interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>;
- };
-
- psci {
- compatible = "arm,psci-0.2";
- method = "smc";
- };
-
- timer {
- compatible = "arm,armv8-timer";
- interrupts = <GIC_PPI 13
- (GIC_CPU_MASK_RAW(0xff) | IRQ_TYPE_LEVEL_LOW)>,
- <GIC_PPI 14
- (GIC_CPU_MASK_RAW(0xff) | IRQ_TYPE_LEVEL_LOW)>,
- <GIC_PPI 11
- (GIC_CPU_MASK_RAW(0xff) | IRQ_TYPE_LEVEL_LOW)>,
- <GIC_PPI 10
- (GIC_CPU_MASK_RAW(0xff) | IRQ_TYPE_LEVEL_LOW)>;
- };
-
- xtal: xtal-clk {
- compatible = "fixed-clock";
- clock-frequency = <24000000>;
- clock-output-names = "xtal";
- #clock-cells = <0>;
- };
-
- firmware {
- sm: secure-monitor {
- compatible = "amlogic,meson-gx-sm", "amlogic,meson-gxbb-sm";
- };
- };
-
- efuse: efuse {
- compatible = "amlogic,meson-gx-efuse", "amlogic,meson-gxbb-efuse";
- #address-cells = <1>;
- #size-cells = <1>;
- read-only;
- secure-monitor = <&sm>;
-
- sn: sn@14 {
- reg = <0x14 0x10>;
- };
-
- eth_mac: eth-mac@34 {
- reg = <0x34 0x10>;
- };
-
- bid: bid@46 {
- reg = <0x46 0x30>;
- };
- };
-
- scpi {
- compatible = "amlogic,meson-gxbb-scpi", "arm,scpi-pre-1.0";
- mboxes = <&mailbox 1 &mailbox 2>;
- shmem = <&cpu_scp_lpri &cpu_scp_hpri>;
-
- scpi_clocks: clocks {
- compatible = "arm,scpi-clocks";
-
- scpi_dvfs: clocks-0 {
- compatible = "arm,scpi-dvfs-clocks";
- #clock-cells = <1>;
- clock-indices = <0>;
- clock-output-names = "vcpu";
- };
- };
-
- scpi_sensors: sensors {
- compatible = "amlogic,meson-gxbb-scpi-sensors", "arm,scpi-sensors";
- #thermal-sensor-cells = <1>;
- };
- };
-
- soc {
- compatible = "simple-bus";
- #address-cells = <2>;
- #size-cells = <2>;
- ranges;
-
- cbus: bus@c1100000 {
- compatible = "simple-bus";
- reg = <0x0 0xc1100000 0x0 0x100000>;
- #address-cells = <2>;
- #size-cells = <2>;
- ranges = <0x0 0x0 0x0 0xc1100000 0x0 0x100000>;
-
- gpio_intc: interrupt-controller@9880 {
- compatible = "amlogic,meson-gpio-intc";
- reg = <0x0 0x9880 0x0 0x10>;
- interrupt-controller;
- #interrupt-cells = <2>;
- amlogic,channel-interrupts = <64 65 66 67 68 69 70 71>;
- status = "disabled";
- };
-
- reset: reset-controller@4404 {
- compatible = "amlogic,meson-gxbb-reset";
- reg = <0x0 0x04404 0x0 0x9c>;
- #reset-cells = <1>;
- };
-
- aiu: audio-controller@5400 {
- compatible = "amlogic,aiu";
- #sound-dai-cells = <2>;
- sound-name-prefix = "AIU";
- reg = <0x0 0x5400 0x0 0x2ac>;
- interrupts = <GIC_SPI 48 IRQ_TYPE_EDGE_RISING>,
- <GIC_SPI 50 IRQ_TYPE_EDGE_RISING>;
- interrupt-names = "i2s", "spdif";
- status = "disabled";
- };
-
- uart_A: serial@84c0 {
- compatible = "amlogic,meson-gx-uart";
- reg = <0x0 0x84c0 0x0 0x18>;
- interrupts = <GIC_SPI 26 IRQ_TYPE_EDGE_RISING>;
- status = "disabled";
- fifo-size = <128>;
- };
-
- uart_B: serial@84dc {
- compatible = "amlogic,meson-gx-uart";
- reg = <0x0 0x84dc 0x0 0x18>;
- interrupts = <GIC_SPI 75 IRQ_TYPE_EDGE_RISING>;
- status = "disabled";
- };
-
- i2c_A: i2c@8500 {
- compatible = "amlogic,meson-gxbb-i2c";
- reg = <0x0 0x08500 0x0 0x20>;
- interrupts = <GIC_SPI 21 IRQ_TYPE_EDGE_RISING>;
- #address-cells = <1>;
- #size-cells = <0>;
- status = "disabled";
- };
-
- pwm_ab: pwm@8550 {
- compatible = "amlogic,meson-gx-pwm", "amlogic,meson-gxbb-pwm";
- reg = <0x0 0x08550 0x0 0x10>;
- #pwm-cells = <3>;
- status = "disabled";
- };
-
- pwm_cd: pwm@8650 {
- compatible = "amlogic,meson-gx-pwm", "amlogic,meson-gxbb-pwm";
- reg = <0x0 0x08650 0x0 0x10>;
- #pwm-cells = <3>;
- status = "disabled";
- };
-
- saradc: adc@8680 {
- compatible = "amlogic,meson-saradc";
- reg = <0x0 0x8680 0x0 0x34>;
- #io-channel-cells = <1>;
- interrupts = <GIC_SPI 73 IRQ_TYPE_EDGE_RISING>;
- status = "disabled";
- };
-
- pwm_ef: pwm@86c0 {
- compatible = "amlogic,meson-gx-pwm", "amlogic,meson-gxbb-pwm";
- reg = <0x0 0x086c0 0x0 0x10>;
- #pwm-cells = <3>;
- status = "disabled";
- };
-
- uart_C: serial@8700 {
- compatible = "amlogic,meson-gx-uart";
- reg = <0x0 0x8700 0x0 0x18>;
- interrupts = <GIC_SPI 93 IRQ_TYPE_EDGE_RISING>;
- status = "disabled";
- };
-
- clock-measure@8758 {
- compatible = "amlogic,meson-gx-clk-measure";
- reg = <0x0 0x8758 0x0 0x10>;
- };
-
- i2c_B: i2c@87c0 {
- compatible = "amlogic,meson-gxbb-i2c";
- reg = <0x0 0x087c0 0x0 0x20>;
- interrupts = <GIC_SPI 214 IRQ_TYPE_EDGE_RISING>;
- #address-cells = <1>;
- #size-cells = <0>;
- status = "disabled";
- };
-
- i2c_C: i2c@87e0 {
- compatible = "amlogic,meson-gxbb-i2c";
- reg = <0x0 0x087e0 0x0 0x20>;
- interrupts = <GIC_SPI 215 IRQ_TYPE_EDGE_RISING>;
- #address-cells = <1>;
- #size-cells = <0>;
- status = "disabled";
- };
-
- spicc: spi@8d80 {
- compatible = "amlogic,meson-gx-spicc";
- reg = <0x0 0x08d80 0x0 0x80>;
- interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>;
- #address-cells = <1>;
- #size-cells = <0>;
- status = "disabled";
- };
-
- spifc: spi@8c80 {
- compatible = "amlogic,meson-gxbb-spifc";
- reg = <0x0 0x08c80 0x0 0x80>;
- #address-cells = <1>;
- #size-cells = <0>;
- status = "disabled";
- };
-
- watchdog@98d0 {
- compatible = "amlogic,meson-gxbb-wdt";
- reg = <0x0 0x098d0 0x0 0x10>;
- clocks = <&xtal>;
- };
- };
-
- gic: interrupt-controller@c4301000 {
- compatible = "arm,gic-400";
- reg = <0x0 0xc4301000 0 0x1000>,
- <0x0 0xc4302000 0 0x2000>,
- <0x0 0xc4304000 0 0x2000>,
- <0x0 0xc4306000 0 0x2000>;
- interrupt-controller;
- interrupts = <GIC_PPI 9
- (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_HIGH)>;
- #interrupt-cells = <3>;
- #address-cells = <0>;
- };
-
- sram: sram@c8000000 {
- compatible = "mmio-sram";
- reg = <0x0 0xc8000000 0x0 0x14000>;
-
- #address-cells = <1>;
- #size-cells = <1>;
- ranges = <0 0x0 0xc8000000 0x14000>;
-
- cpu_scp_lpri: scp-sram@0 {
- compatible = "amlogic,meson-gxbb-scp-shmem";
- reg = <0x13000 0x400>;
- };
-
- cpu_scp_hpri: scp-sram@200 {
- compatible = "amlogic,meson-gxbb-scp-shmem";
- reg = <0x13400 0x400>;
- };
- };
-
- aobus: bus@c8100000 {
- compatible = "simple-bus";
- reg = <0x0 0xc8100000 0x0 0x100000>;
- #address-cells = <2>;
- #size-cells = <2>;
- ranges = <0x0 0x0 0x0 0xc8100000 0x0 0x100000>;
-
- sysctrl_AO: sys-ctrl@0 {
- compatible = "amlogic,meson-gx-ao-sysctrl", "simple-mfd", "syscon";
- reg = <0x0 0x0 0x0 0x100>;
-
- clkc_AO: clock-controller {
- compatible = "amlogic,meson-gx-aoclkc";
- #clock-cells = <1>;
- #reset-cells = <1>;
- };
- };
-
- cec_AO: cec@100 {
- compatible = "amlogic,meson-gx-ao-cec";
- reg = <0x0 0x00100 0x0 0x14>;
- interrupts = <GIC_SPI 199 IRQ_TYPE_EDGE_RISING>;
- status = "disabled";
- };
-
- sec_AO: ao-secure@140 {
- compatible = "amlogic,meson-gx-ao-secure", "syscon";
- reg = <0x0 0x140 0x0 0x140>;
- amlogic,has-chip-id;
- };
-
- uart_AO: serial@4c0 {
- compatible = "amlogic,meson-gx-uart", "amlogic,meson-ao-uart";
- reg = <0x0 0x004c0 0x0 0x18>;
- interrupts = <GIC_SPI 193 IRQ_TYPE_EDGE_RISING>;
- status = "disabled";
- };
-
- uart_AO_B: serial@4e0 {
- compatible = "amlogic,meson-gx-uart", "amlogic,meson-ao-uart";
- reg = <0x0 0x004e0 0x0 0x18>;
- interrupts = <GIC_SPI 197 IRQ_TYPE_EDGE_RISING>;
- status = "disabled";
- };
-
- i2c_AO: i2c@500 {
- compatible = "amlogic,meson-gxbb-i2c";
- reg = <0x0 0x500 0x0 0x20>;
- interrupts = <GIC_SPI 195 IRQ_TYPE_EDGE_RISING>;
- #address-cells = <1>;
- #size-cells = <0>;
- status = "disabled";
- };
-
- pwm_AO_ab: pwm@550 {
- compatible = "amlogic,meson-gx-ao-pwm", "amlogic,meson-gxbb-ao-pwm";
- reg = <0x0 0x00550 0x0 0x10>;
- #pwm-cells = <3>;
- status = "disabled";
- };
-
- ir: ir@580 {
- compatible = "amlogic,meson-gx-ir", "amlogic,meson-gxbb-ir";
- reg = <0x0 0x00580 0x0 0x40>;
- interrupts = <GIC_SPI 196 IRQ_TYPE_EDGE_RISING>;
- status = "disabled";
- };
- };
-
- vdec: video-codec@c8820000 {
- compatible = "amlogic,gx-vdec";
- reg = <0x0 0xc8820000 0x0 0x10000>,
- <0x0 0xc110a580 0x0 0xe4>;
- reg-names = "dos", "esparser";
-
- interrupts = <GIC_SPI 44 IRQ_TYPE_EDGE_RISING>,
- <GIC_SPI 32 IRQ_TYPE_EDGE_RISING>;
- interrupt-names = "vdec", "esparser";
-
- amlogic,ao-sysctrl = <&sysctrl_AO>;
- amlogic,canvas = <&canvas>;
- };
-
- periphs: bus@c8834000 {
- compatible = "simple-bus";
- reg = <0x0 0xc8834000 0x0 0x2000>;
- #address-cells = <2>;
- #size-cells = <2>;
- ranges = <0x0 0x0 0x0 0xc8834000 0x0 0x2000>;
-
- hwrng: rng@0 {
- compatible = "amlogic,meson-rng";
- reg = <0x0 0x0 0x0 0x4>;
- };
- };
-
- dmcbus: bus@c8838000 {
- compatible = "simple-bus";
- reg = <0x0 0xc8838000 0x0 0x400>;
- #address-cells = <2>;
- #size-cells = <2>;
- ranges = <0x0 0x0 0x0 0xc8838000 0x0 0x400>;
-
- canvas: video-lut@48 {
- compatible = "amlogic,canvas";
- reg = <0x0 0x48 0x0 0x14>;
- };
- };
-
- hiubus: bus@c883c000 {
- compatible = "simple-bus";
- reg = <0x0 0xc883c000 0x0 0x2000>;
- #address-cells = <2>;
- #size-cells = <2>;
- ranges = <0x0 0x0 0x0 0xc883c000 0x0 0x2000>;
-
- sysctrl: system-controller@0 {
- compatible = "amlogic,meson-gx-hhi-sysctrl", "simple-mfd", "syscon";
- reg = <0 0 0 0x400>;
-
- pwrc: power-controller {
- compatible = "amlogic,meson-gxbb-pwrc";
- #power-domain-cells = <1>;
- amlogic,ao-sysctrl = <&sysctrl_AO>;
- };
- };
-
- mailbox: mailbox@404 {
- compatible = "amlogic,meson-gxbb-mhu";
- reg = <0 0x404 0 0x4c>;
- interrupts = <GIC_SPI 208 IRQ_TYPE_EDGE_RISING>,
- <GIC_SPI 209 IRQ_TYPE_EDGE_RISING>,
- <GIC_SPI 210 IRQ_TYPE_EDGE_RISING>;
- #mbox-cells = <1>;
- };
- };
-
- ethmac: ethernet@c9410000 {
- compatible = "amlogic,meson-gxbb-dwmac",
- "snps,dwmac-3.70a",
- "snps,dwmac";
- reg = <0x0 0xc9410000 0x0 0x10000>,
- <0x0 0xc8834540 0x0 0x4>;
- interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
- interrupt-names = "macirq";
- rx-fifo-depth = <4096>;
- tx-fifo-depth = <2048>;
- power-domains = <&pwrc PWRC_GXBB_ETHERNET_MEM_ID>;
- status = "disabled";
- };
-
- apb: apb@d0000000 {
- compatible = "simple-bus";
- reg = <0x0 0xd0000000 0x0 0x200000>;
- #address-cells = <2>;
- #size-cells = <2>;
- ranges = <0x0 0x0 0x0 0xd0000000 0x0 0x200000>;
-
- sd_emmc_a: mmc@70000 {
- compatible = "amlogic,meson-gx-mmc", "amlogic,meson-gxbb-mmc";
- reg = <0x0 0x70000 0x0 0x800>;
- interrupts = <GIC_SPI 216 IRQ_TYPE_LEVEL_HIGH>;
- status = "disabled";
- };
-
- sd_emmc_b: mmc@72000 {
- compatible = "amlogic,meson-gx-mmc", "amlogic,meson-gxbb-mmc";
- reg = <0x0 0x72000 0x0 0x800>;
- interrupts = <GIC_SPI 217 IRQ_TYPE_LEVEL_HIGH>;
- status = "disabled";
- };
-
- sd_emmc_c: mmc@74000 {
- compatible = "amlogic,meson-gx-mmc", "amlogic,meson-gxbb-mmc";
- reg = <0x0 0x74000 0x0 0x800>;
- interrupts = <GIC_SPI 218 IRQ_TYPE_LEVEL_HIGH>;
- status = "disabled";
- };
- };
-
- vpu: vpu@d0100000 {
- compatible = "amlogic,meson-gx-vpu";
- reg = <0x0 0xd0100000 0x0 0x100000>,
- <0x0 0xc883c000 0x0 0x1000>;
- reg-names = "vpu", "hhi";
- interrupts = <GIC_SPI 3 IRQ_TYPE_EDGE_RISING>;
- #address-cells = <1>;
- #size-cells = <0>;
- amlogic,canvas = <&canvas>;
-
- /* CVBS VDAC output port */
- cvbs_vdac_port: port@0 {
- reg = <0>;
- };
-
- /* HDMI-TX output port */
- hdmi_tx_port: port@1 {
- reg = <1>;
-
- hdmi_tx_out: endpoint {
- remote-endpoint = <&hdmi_tx_in>;
- };
- };
- };
-
- hdmi_tx: hdmi-tx@c883a000 {
- compatible = "amlogic,meson-gx-dw-hdmi";
- reg = <0x0 0xc883a000 0x0 0x1c>;
- interrupts = <GIC_SPI 57 IRQ_TYPE_EDGE_RISING>;
- #address-cells = <1>;
- #size-cells = <0>;
- #sound-dai-cells = <0>;
- sound-name-prefix = "HDMITX";
- status = "disabled";
-
- /* VPU VENC Input */
- hdmi_tx_venc_port: port@0 {
- reg = <0>;
-
- hdmi_tx_in: endpoint {
- remote-endpoint = <&hdmi_tx_out>;
- };
- };
-
- /* TMDS Output */
- hdmi_tx_tmds_port: port@1 {
- reg = <1>;
- };
- };
- };
-};
diff --git a/arch/arm/dts/meson-gxbb-wetek-u-boot.dtsi b/arch/arm/dts/meson-gxbb-wetek-hub-u-boot.dtsi
similarity index 100%
rename from arch/arm/dts/meson-gxbb-wetek-u-boot.dtsi
rename to arch/arm/dts/meson-gxbb-wetek-hub-u-boot.dtsi
diff --git a/arch/arm/dts/meson-gxbb-wetek-u-boot.dtsi b/arch/arm/dts/meson-gxbb-wetek-play2-u-boot.dtsi
similarity index 100%
copy from arch/arm/dts/meson-gxbb-wetek-u-boot.dtsi
copy to arch/arm/dts/meson-gxbb-wetek-play2-u-boot.dtsi
diff --git a/arch/arm/dts/meson-gxl-mali.dtsi b/arch/arm/dts/meson-gxl-mali.dtsi
deleted file mode 100644
index 478e755..0000000
--- a/arch/arm/dts/meson-gxl-mali.dtsi
+++ /dev/null
@@ -1,17 +0,0 @@
-// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
-/*
- * Copyright (c) 2017 BayLibre SAS
- * Author: Neil Armstrong <narmstrong@baylibre.com>
- */
-
-#include "meson-gx-mali450.dtsi"
-
-&mali {
- compatible = "amlogic,meson-gxl-mali", "arm,mali-450";
-
- clocks = <&clkc CLKID_CLK81>, <&clkc CLKID_MALI>;
- clock-names = "bus", "core";
-
- assigned-clocks = <&clkc CLKID_GP0_PLL>;
- assigned-clock-rates = <744000000>;
-};
diff --git a/arch/arm/dts/meson-gxl-s805x-libretech-ac.dts b/arch/arm/dts/meson-gxl-s805x-libretech-ac.dts
deleted file mode 100644
index 213a070..0000000
--- a/arch/arm/dts/meson-gxl-s805x-libretech-ac.dts
+++ /dev/null
@@ -1,319 +0,0 @@
-// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
-/*
- * Copyright (c) 2018 BayLibre, SAS.
- * Author: Neil Armstrong <narmstrong@baylibre.com>
- * Author: Jerome Brunet <jbrunet@baylibre.com>
- */
-
-/dts-v1/;
-
-#include <dt-bindings/input/input.h>
-#include <dt-bindings/sound/meson-aiu.h>
-
-#include "meson-gxl-s805x.dtsi"
-
-/ {
- compatible = "libretech,aml-s805x-ac", "amlogic,s805x",
- "amlogic,meson-gxl";
- model = "Libre Computer AML-S805X-AC";
-
- aliases {
- serial0 = &uart_AO;
- ethernet0 = ðmac;
- spi0 = &spifc;
- };
-
- chosen {
- stdout-path = "serial0:115200n8";
- };
-
- cvbs-connector {
- /*
- * The pads are present but no connector is soldered on
- * 2J2, so keep this off by default.
- */
- status = "disabled";
- compatible = "composite-video-connector";
-
- port {
- cvbs_connector_in: endpoint {
- remote-endpoint = <&cvbs_vdac_out>;
- };
- };
- };
-
- dc_5v: regulator-dc_5v {
- compatible = "regulator-fixed";
- regulator-name = "DC_5V";
- regulator-min-microvolt = <5000000>;
- regulator-max-microvolt = <5000000>;
- regulator-always-on;
- };
-
- emmc_pwrseq: emmc-pwrseq {
- compatible = "mmc-pwrseq-emmc";
- reset-gpios = <&gpio BOOT_9 GPIO_ACTIVE_LOW>;
- };
-
- hdmi-connector {
- compatible = "hdmi-connector";
- type = "a";
-
- port {
- hdmi_connector_in: endpoint {
- remote-endpoint = <&hdmi_tx_tmds_out>;
- };
- };
- };
-
- memory@0 {
- device_type = "memory";
- reg = <0x0 0x0 0x0 0x20000000>;
- };
-
- vcck: regulator-vcck {
- compatible = "regulator-fixed";
- regulator-name = "VCCK";
- regulator-min-microvolt = <3300000>;
- regulator-max-microvolt = <3300000>;
- vin-supply = <&dc_5v>;
-
- /*
- * This is controlled by GPIOAO_9 we reserve this but
- * claiming it as done below reset the board anyway
- * Need to investigate this
- *
- * gpio = <&gpio_ao GPIOAO_9 GPIO_ACTIVE_HIGH>;
- * enable-active-high;
- */
- regulator-always-on;
- };
-
- vcc_3v3: regulator-vcc_3v3 {
- compatible = "regulator-fixed";
- regulator-name = "VCC_3V3";
- regulator-min-microvolt = <3300000>;
- regulator-max-microvolt = <3300000>;
- vin-supply = <&dc_5v>;
- regulator-always-on;
- };
-
- vddio_ao18: regulator-vddio_ao18 {
- compatible = "regulator-fixed";
- regulator-name = "VDDIO_AO18";
- regulator-min-microvolt = <1800000>;
- regulator-max-microvolt = <1800000>;
- vin-supply = <&vcc_3v3>;
- regulator-always-on;
- };
-
- vddio_boot: regulator-vddio_boot {
- compatible = "regulator-fixed";
- regulator-name = "VDDIO_BOOT";
- regulator-min-microvolt = <1800000>;
- regulator-max-microvolt = <1800000>;
- vin-supply = <&vcc_3v3>;
- regulator-always-on;
- };
-
- sound {
- compatible = "amlogic,gx-sound-card";
- model = "LIBRETECH-AC";
- audio-widgets = "Speaker", "9J5-3 LEFT",
- "Speaker", "9J5-2 RIGHT";
- audio-routing = "9J5-3 LEFT", "ACODEC LOLN",
- "9J5-2 RIGHT", "ACODEC LORN";
- assigned-clocks = <&clkc CLKID_MPLL0>,
- <&clkc CLKID_MPLL1>,
- <&clkc CLKID_MPLL2>;
- assigned-clock-parents = <0>, <0>, <0>;
- assigned-clock-rates = <294912000>,
- <270950400>,
- <393216000>;
- status = "okay";
-
- dai-link-0 {
- sound-dai = <&aiu AIU_CPU CPU_I2S_FIFO>;
- };
-
- dai-link-1 {
- sound-dai = <&aiu AIU_CPU CPU_I2S_ENCODER>;
- dai-format = "i2s";
- mclk-fs = <256>;
-
- codec-0 {
- sound-dai = <&aiu AIU_HDMI CTRL_I2S>;
- };
-
- codec-1 {
- sound-dai = <&aiu AIU_ACODEC CTRL_I2S>;
- };
- };
-
- dai-link-2 {
- sound-dai = <&aiu AIU_HDMI CTRL_OUT>;
-
- codec-0 {
- sound-dai = <&hdmi_tx>;
- };
- };
-
- dai-link-3 {
- sound-dai = <&aiu AIU_ACODEC CTRL_OUT>;
-
- codec-0 {
- sound-dai = <&acodec>;
- };
- };
- };
-};
-
-&acodec {
- AVDD-supply = <&vddio_ao18>;
- status = "okay";
-};
-
-&aiu {
- status = "okay";
-};
-
-&cec_AO {
- status = "okay";
- pinctrl-0 = <&ao_cec_pins>;
- pinctrl-names = "default";
- hdmi-phandle = <&hdmi_tx>;
-};
-
-&cvbs_vdac_port {
- cvbs_vdac_out: endpoint {
- remote-endpoint = <&cvbs_connector_in>;
- };
-};
-
-ðmac {
- status = "okay";
-};
-
-&internal_phy {
- pinctrl-0 = <ð_link_led_pins>, <ð_act_led_pins>;
- pinctrl-names = "default";
-};
-
-&ir {
- status = "okay";
- pinctrl-0 = <&remote_input_ao_pins>;
- pinctrl-names = "default";
-};
-
-&hdmi_tx {
- status = "okay";
- pinctrl-0 = <&hdmi_hpd_pins>, <&hdmi_i2c_pins>;
- pinctrl-names = "default";
-};
-
-&hdmi_tx_tmds_port {
- hdmi_tx_tmds_out: endpoint {
- remote-endpoint = <&hdmi_connector_in>;
- };
-};
-
-&gpio_ao {
- gpio-line-names = "UART TX",
- "UART RX",
- "7J1 Header Pin31",
- "", "", "", "",
- "IR In",
- "HDMI CEC",
- "5V VCCK Regulator",
- /* GPIO_TEST_N */
- "";
-};
-
-&gpio {
- gpio-line-names = /* Bank GPIOZ */
- "", "", "", "", "", "", "",
- "", "", "", "", "", "", "",
- "Eth Link LED", "Eth Activity LED",
- /* Bank GPIOH */
- "HDMI HPD", "HDMI SDA", "HDMI SCL",
- "", "7J1 Header Pin13",
- "7J1 Header Pin15",
- "7J1 Header Pin7",
- "7J1 Header Pin12",
- "7J1 Header Pin16",
- "7J1 Header Pin18",
- /* Bank BOOT */
- "eMMC D0", "eMMC D1", "eMMC D2", "eMMC D3",
- "eMMC D4", "eMMC D5", "eMMC D6", "eMMC D7",
- "eMMC Clk", "eMMC Reset", "eMMC CMD",
- "SPI NOR MOSI", "SPI NOR MISO", "SPI NOR Clk",
- "", "SPI NOR Chip Select",
- /* Bank CARD */
- "", "", "", "", "", "", "",
- /* Bank GPIODV */
- "", "", "", "", "", "", "", "", "", "", "", "",
- "", "", "", "", "", "", "", "", "", "", "", "",
- "7J1 Header Pin27", "7J1 Header Pin28", "",
- "7J1 Header Pin29",
- "VCCK Regulator", "VDDEE Regulator",
- /* Bank GPIOX */
- "7J1 Header Pin22", "7J1 Header Pin26",
- "7J1 Header Pin36", "7J1 Header Pin38",
- "7J1 Header Pin40", "7J1 Header Pin37",
- "7J1 Header Pin33", "7J1 Header Pin35",
- "7J1 Header Pin19", "7J1 Header Pin21",
- "7J1 Header Pin24", "7J1 Header Pin23",
- "7J1 Header Pin8", "7J1 Header Pin10",
- "", "", "7J1 Header Pin32", "", "",
- /* Bank GPIOCLK */
- "", "";
-};
-
-&saradc {
- status = "okay";
- vref-supply = <&vddio_boot>;
-};
-
-/* eMMC */
-&sd_emmc_c {
- status = "okay";
- pinctrl-0 = <&emmc_pins>;
- pinctrl-1 = <&emmc_clk_gate_pins>;
- pinctrl-names = "default", "clk-gate";
-
- bus-width = <8>;
- cap-mmc-highspeed;
- mmc-ddr-1_8v;
- mmc-hs200-1_8v;
- max-frequency = <200000000>;
- disable-wp;
-
- mmc-pwrseq = <&emmc_pwrseq>;
- vmmc-supply = <&vcc_3v3>;
- vqmmc-supply = <&vddio_boot>;
-};
-
-&spifc {
- status = "okay";
- pinctrl-0 = <&nor_pins>;
- pinctrl-names = "default";
-
- w25q32: flash@0 {
- #address-cells = <1>;
- #size-cells = <1>;
- compatible = "jedec,spi-nor";
- reg = <0>;
- spi-max-frequency = <3000000>;
- };
-};
-
-&uart_AO {
- status = "okay";
- pinctrl-0 = <&uart_ao_a_pins>;
- pinctrl-names = "default";
-};
-
-&usb {
- status = "okay";
- dr_mode = "host";
-};
diff --git a/arch/arm/dts/meson-gxl-s805x.dtsi b/arch/arm/dts/meson-gxl-s805x.dtsi
deleted file mode 100644
index 2997584..0000000
--- a/arch/arm/dts/meson-gxl-s805x.dtsi
+++ /dev/null
@@ -1,23 +0,0 @@
-// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
-/*
- * Copyright (c) 2020 BayLibre SAS
- * Author: Neil Armstrong <narmstrong@baylibre.com>
- */
-
-#include "meson-gxl-s905x.dtsi"
-
-/ {
- compatible = "amlogic,s805x", "amlogic,meson-gxl";
-};
-
-/* The S805X Package doesn't seem to handle the 744MHz OPP correctly */
-&gpu_opp_table {
- opp-744000000 {
- status = "disabled";
- };
-};
-
-&mali {
- /delete-property/ assigned-clocks;
- /delete-property/ assigned-clock-rates;
-};
diff --git a/arch/arm/dts/meson-gxl-s905d-libretech-pc.dts b/arch/arm/dts/meson-gxl-s905d-libretech-pc.dts
deleted file mode 100644
index 100a1cf..0000000
--- a/arch/arm/dts/meson-gxl-s905d-libretech-pc.dts
+++ /dev/null
@@ -1,16 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0
-/*
- * Copyright (c) 2019 BayLibre SAS. All rights reserved.
- * Author: Jerome Brunet <jbrunet@baylibre.com>
- */
-
-/dts-v1/;
-
-#include "meson-gxl-s905d.dtsi"
-#include "meson-gx-libretech-pc.dtsi"
-
-/ {
- compatible = "libretech,aml-s905d-pc", "amlogic,s905d",
- "amlogic,meson-gxl";
- model = "Libre Computer AML-S905D-PC";
-};
diff --git a/arch/arm/dts/meson-gxl-s905d.dtsi b/arch/arm/dts/meson-gxl-s905d.dtsi
deleted file mode 100644
index 4332191..0000000
--- a/arch/arm/dts/meson-gxl-s905d.dtsi
+++ /dev/null
@@ -1,12 +0,0 @@
-// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
-/*
- * Copyright (c) 2016 Endless Computers, Inc.
- * Author: Carlo Caione <carlo@endlessm.com>
- */
-
-#include "meson-gxl.dtsi"
-#include "meson-gxl-mali.dtsi"
-
-/ {
- compatible = "amlogic,s905d", "amlogic,meson-gxl";
-};
diff --git a/arch/arm/dts/meson-gxl-s905w-jethome-jethub-j80.dts b/arch/arm/dts/meson-gxl-s905w-jethome-jethub-j80.dts
deleted file mode 100644
index a18d6d2..0000000
--- a/arch/arm/dts/meson-gxl-s905w-jethome-jethub-j80.dts
+++ /dev/null
@@ -1,247 +0,0 @@
-// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
-/*
- * Copyright (c) 2021 Vyacheslav Bocharov <adeep@lexina.in>
- * Copyright (c) 2020 JetHome
- * Author: Aleksandr Kazantsev <ak@tvip.ru>
- * Author: Alexey Shevelkin <ash@tvip.ru>
- * Author: Vyacheslav Bocharov <adeep@lexina.in>
- */
-
-/dts-v1/;
-
-#include "meson-gxl.dtsi"
-
-/ {
- compatible = "jethome,jethub-j80", "amlogic,s905w", "amlogic,meson-gxl";
- model = "JetHome JetHub J80";
- memory@0 {
- device_type = "memory";
- reg = <0x0 0x0 0x0 0x40000000>;
- };
-
- reserved-memory {
- linux,cma {
- size = <0x0 0x1000000>;
- };
- };
-
- aliases {
- serial0 = &uart_AO; /* Console */
- serial1 = &uart_A; /* Bluetooth */
- serial2 = &uart_AO_B; /* Wireless module 1 */
- serial3 = &uart_C; /* Wireless module 2 */
- ethernet0 = ðmac;
- };
-
- chosen {
- stdout-path = "serial0:115200n8";
- };
-
- vddio_ao18: regulator-vddio_ao18 {
- compatible = "regulator-fixed";
- regulator-name = "VDDIO_AO18";
- regulator-min-microvolt = <1800000>;
- regulator-max-microvolt = <1800000>;
- };
-
- vddio_boot: regulator-vddio_boot {
- compatible = "regulator-fixed";
- regulator-name = "VDDIO_BOOT";
- regulator-min-microvolt = <1800000>;
- regulator-max-microvolt = <1800000>;
- };
-
- vddao_3v3: regulator-vddao_3v3 {
- compatible = "regulator-fixed";
- regulator-name = "VDDAO_3V3";
- regulator-min-microvolt = <3300000>;
- regulator-max-microvolt = <3300000>;
- };
-
- vcc_3v3: regulator-vcc_3v3 {
- compatible = "regulator-fixed";
- regulator-name = "VCC_3V3";
- regulator-min-microvolt = <3300000>;
- regulator-max-microvolt = <3300000>;
- };
-
- emmc_pwrseq: emmc-pwrseq {
- compatible = "mmc-pwrseq-emmc";
- reset-gpios = <&gpio BOOT_9 GPIO_ACTIVE_LOW>;
- };
-
- wifi32k: wifi32k {
- compatible = "pwm-clock";
- #clock-cells = <0>;
- clock-frequency = <32768>;
- pwms = <&pwm_ef 0 30518 0>; /* PWM_E at 32.768KHz */
- };
-
- sdio_pwrseq: sdio-pwrseq {
- compatible = "mmc-pwrseq-simple";
- reset-gpios = <&gpio GPIOX_6 GPIO_ACTIVE_LOW>;
- clocks = <&wifi32k>;
- clock-names = "ext_clock";
- };
-};
-
-&efuse {
- bt_mac: bt-mac@6 {
- reg = <0x6 0x6>;
- };
-
- wifi_mac: wifi-mac@c {
- reg = <0xc 0x6>;
- };
-};
-
-&sn {
- reg = <0x32 0x20>;
-};
-
-ð_mac {
- reg = <0x0 0x6>;
-};
-
-&bid {
- reg = <0x12 0x20>;
-};
-
-&usb {
- status = "okay";
- dr_mode = "host";
-};
-
-&pwm_ef {
- status = "okay";
- pinctrl-0 = <&pwm_e_pins>;
- pinctrl-names = "default";
- clocks = <&clkc CLKID_FCLK_DIV4>;
- clock-names = "clkin0";
-};
-
-&saradc {
- status = "okay";
- vref-supply = <&vddio_ao18>;
-};
-
-/* Wireless SDIO Module */
-&sd_emmc_a {
- status = "okay";
- pinctrl-0 = <&sdio_pins>;
- pinctrl-1 = <&sdio_clk_gate_pins>;
- pinctrl-names = "default", "clk-gate";
- #address-cells = <1>;
- #size-cells = <0>;
-
- bus-width = <4>;
- cap-sd-highspeed;
- max-frequency = <50000000>;
-
- non-removable;
- disable-wp;
-
- /* WiFi firmware requires power to be kept while in suspend */
- keep-power-in-suspend;
-
- mmc-pwrseq = <&sdio_pwrseq>;
-
- vmmc-supply = <&vddao_3v3>;
- vqmmc-supply = <&vddio_boot>;
-};
-
-/* SD card */
-&sd_emmc_b {
- status = "okay";
- pinctrl-0 = <&sdcard_pins>;
- pinctrl-1 = <&sdcard_clk_gate_pins>;
- pinctrl-names = "default", "clk-gate";
-
- bus-width = <4>;
- cap-sd-highspeed;
- max-frequency = <50000000>;
- disable-wp;
-
- cd-gpios = <&gpio CARD_6 GPIO_ACTIVE_LOW>;
-
- vmmc-supply = <&vddao_3v3>;
- vqmmc-supply = <&vddio_boot>;
-};
-
-/* eMMC */
-&sd_emmc_c {
- status = "okay";
- pinctrl-0 = <&emmc_pins>, <&emmc_ds_pins>;
- pinctrl-1 = <&emmc_clk_gate_pins>;
- pinctrl-names = "default", "clk-gate";
-
- bus-width = <8>;
- cap-mmc-highspeed;
- max-frequency = <200000000>;
- non-removable;
- disable-wp;
- mmc-ddr-1_8v;
- mmc-hs200-1_8v;
-
- mmc-pwrseq = <&emmc_pwrseq>;
- vmmc-supply = <&vcc_3v3>;
- vqmmc-supply = <&vddio_boot>;
-};
-
-/* Console UART */
-&uart_AO {
- status = "okay";
- pinctrl-0 = <&uart_ao_a_pins>;
- pinctrl-names = "default";
-};
-
-/* S905W only has access to its internal PHY */
-ðmac {
- status = "okay";
- phy-mode = "rmii";
- phy-handle = <&internal_phy>;
-};
-
-&internal_phy {
- status = "okay";
- pinctrl-0 = <ð_link_led_pins>, <ð_act_led_pins>;
- pinctrl-names = "default";
-};
-
-&uart_A {
- status = "okay";
- pinctrl-0 = <&uart_a_pins>, <&uart_a_cts_rts_pins>;
- pinctrl-names = "default";
- uart-has-rtscts;
-
- bluetooth {
- compatible = "realtek,rtl8822cs-bt";
- enable-gpios = <&gpio GPIOX_17 GPIO_ACTIVE_HIGH>;
- host-wake-gpios = <&gpio GPIOX_18 GPIO_ACTIVE_HIGH>;
- };
-};
-
-&uart_C {
- status = "okay";
- pinctrl-0 = <&uart_c_pins>;
- pinctrl-names = "default";
-};
-
-&uart_AO_B {
- status = "okay";
- pinctrl-0 = <&uart_ao_b_pins>, <&uart_ao_b_cts_rts_pins>;
- pinctrl-names = "default";
- uart-has-rtscts;
-};
-
-&i2c_B {
- status = "okay";
- pinctrl-names = "default";
- pinctrl-0 = <&i2c_b_pins>;
-
- pcf8563: rtc@51 {
- compatible = "nxp,pcf8563";
- reg = <0x51>;
- status = "okay";
- };
-};
diff --git a/arch/arm/dts/meson-gxl-s905x-khadas-vim.dts b/arch/arm/dts/meson-gxl-s905x-khadas-vim.dts
deleted file mode 100644
index 02f8183..0000000
--- a/arch/arm/dts/meson-gxl-s905x-khadas-vim.dts
+++ /dev/null
@@ -1,237 +0,0 @@
-// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
-/*
- * Copyright (c) 2017 Martin Blumenstingl <martin.blumenstingl@googlemail.com>.
- */
-
-/dts-v1/;
-
-#include "meson-gxl-s905x-p212.dtsi"
-#include <dt-bindings/input/input.h>
-#include <dt-bindings/sound/meson-aiu.h>
-
-/ {
- compatible = "khadas,vim", "amlogic,s905x", "amlogic,meson-gxl";
- model = "Khadas VIM";
-
- adc-keys {
- compatible = "adc-keys";
- io-channels = <&saradc 0>;
- io-channel-names = "buttons";
- keyup-threshold-microvolt = <1710000>;
-
- button-function {
- label = "Function";
- linux,code = <KEY_FN>;
- press-threshold-microvolt = <10000>;
- };
- };
-
- aliases {
- serial2 = &uart_AO_B;
- ethernet0 = ðmac;
- };
-
- gpio-keys-polled {
- compatible = "gpio-keys-polled";
- poll-interval = <100>;
-
- power-button {
- label = "power";
- linux,code = <KEY_POWER>;
- gpios = <&gpio_ao GPIOAO_2 GPIO_ACTIVE_LOW>;
- };
- };
-
- led-controller {
- compatible = "pwm-leds";
-
- led-1 {
- label = "vim:red:power";
- pwms = <&pwm_AO_ab 1 7812500 0>;
- max-brightness = <255>;
- linux,default-trigger = "default-on";
- };
- };
-
- hdmi-connector {
- compatible = "hdmi-connector";
- type = "a";
-
- port {
- hdmi_connector_in: endpoint {
- remote-endpoint = <&hdmi_tx_tmds_out>;
- };
- };
- };
-
- sound {
- compatible = "amlogic,gx-sound-card";
- model = "KHADAS-VIM";
- assigned-clocks = <&clkc CLKID_MPLL0>,
- <&clkc CLKID_MPLL1>,
- <&clkc CLKID_MPLL2>;
- assigned-clock-parents = <0>, <0>, <0>;
- assigned-clock-rates = <294912000>,
- <270950400>,
- <393216000>;
- status = "okay";
-
- dai-link-0 {
- sound-dai = <&aiu AIU_CPU CPU_I2S_FIFO>;
- };
-
- dai-link-1 {
- sound-dai = <&aiu AIU_CPU CPU_I2S_ENCODER>;
- dai-format = "i2s";
- mclk-fs = <256>;
-
- codec-0 {
- sound-dai = <&aiu AIU_HDMI CTRL_I2S>;
- };
- };
-
- dai-link-2 {
- sound-dai = <&aiu AIU_HDMI CTRL_OUT>;
-
- codec-0 {
- sound-dai = <&hdmi_tx>;
- };
- };
- };
-};
-
-&aiu {
- status = "okay";
-};
-
-&cec_AO {
- status = "okay";
- pinctrl-0 = <&ao_cec_pins>;
- pinctrl-names = "default";
- hdmi-phandle = <&hdmi_tx>;
-};
-
-&hdmi_tx {
- status = "okay";
- pinctrl-0 = <&hdmi_hpd_pins>, <&hdmi_i2c_pins>;
- pinctrl-names = "default";
- hdmi-supply = <&hdmi_5v>;
-};
-
-&hdmi_tx_tmds_port {
- hdmi_tx_tmds_out: endpoint {
- remote-endpoint = <&hdmi_connector_in>;
- };
-};
-
-&i2c_A {
- status = "okay";
- pinctrl-0 = <&i2c_a_pins>;
- pinctrl-names = "default";
-};
-
-&i2c_B {
- status = "okay";
- pinctrl-0 = <&i2c_b_pins>;
- pinctrl-names = "default";
-
- rtc: rtc@51 {
- status = "okay";
- compatible = "haoyu,hym8563";
- reg = <0x51>;
- #clock-cells = <0>;
- clock-output-names = "xin32k";
- };
-};
-
-&ir {
- linux,rc-map-name = "rc-khadas";
-};
-
-&gpio_ao {
- gpio-line-names = "UART TX",
- "UART RX",
- "Power Key In",
- "J9 Header Pin35",
- "J9 Header Pin16",
- "J9 Header Pin15",
- "J9 Header Pin33",
- "IR In",
- "HDMI CEC",
- "SYS LED",
- /* GPIO_TEST_N */
- "";
-};
-
-&gpio {
- gpio-line-names = /* Bank GPIOZ */
- "", "", "", "", "", "", "",
- "", "", "", "", "", "", "",
- "Power OFF",
- "VCCK Enable",
- /* Bank GPIOH */
- "HDMI HPD", "HDMI SDA", "HDMI SCL",
- "HDMI_5V_EN", "SPDIF",
- "J9 Header Pin37",
- "J9 Header Pin30",
- "J9 Header Pin29",
- "J9 Header Pin32",
- "J9 Header Pin31",
- /* Bank BOOT */
- "eMMC D0", "eMMC D1", "eMMC D2", "eMMC D3",
- "eMMC D4", "eMMC D5", "eMMC D6", "eMMC D7",
- "eMMC Clk", "eMMC Reset", "eMMC CMD",
- "", "BOOT_MODE", "", "", "eMMC Data Strobe",
- /* Bank CARD */
- "SDCard D1", "SDCard D0", "SDCard CLK", "SDCard CMD",
- "SDCard D3", "SDCard D2", "SDCard Det",
- /* Bank GPIODV */
- "", "", "", "", "", "", "", "", "", "", "", "",
- "", "", "", "", "", "", "", "", "", "", "", "",
- "I2C A SDA", "I2C A SCK", "I2C B SDA", "I2C B SCK",
- "VCCK Regulator", "VDDEE Regulator",
- /* Bank GPIOX */
- "WIFI SDIO D0", "WIFI SDIO D1", "WIFI SDIO D2",
- "WIFI SDIO D3", "WIFI SDIO CLK", "WIFI SDIO CMD",
- "WIFI Power Enable", "WIFI WAKE HOST",
- "Bluetooth PCM DOUT", "Bluetooth PCM DIN",
- "Bluetooth PCM SYNC", "Bluetooth PCM CLK",
- "Bluetooth UART TX", "Bluetooth UART RX",
- "Bluetooth UART CTS", "Bluetooth UART RTS",
- "WIFI 32K", "Bluetooth Enable",
- "Bluetooth WAKE HOST",
- /* Bank GPIOCLK */
- "", "J9 Header Pin39";
-};
-
-&pwm_AO_ab {
- status = "okay";
- pinctrl-0 = <&pwm_ao_a_3_pins>, <&pwm_ao_b_pins>;
- pinctrl-names = "default";
- clocks = <&xtal> , <&xtal>;
- clock-names = "clkin0", "clkin1" ;
-};
-
-&pwm_ef {
- pinctrl-0 = <&pwm_e_pins>, <&pwm_f_clk_pins>;
-};
-
-&sd_emmc_a {
- max-frequency = <100000000>;
-};
-
-/* This is brought out on the Linux_RX (18) and Linux_TX (19) pins: */
-&uart_AO {
- status = "okay";
-};
-
-/* This is brought out on the UART_RX_AO_B (15) and UART_TX_AO_B (16) pins: */
-&uart_AO_B {
- status = "okay";
- pinctrl-0 = <&uart_ao_b_pins>;
- pinctrl-names = "default";
-};
-
-&usb {
- dr_mode = "peripheral";
-};
diff --git a/arch/arm/dts/meson-gxl-s905x-libretech-cc-v2.dts b/arch/arm/dts/meson-gxl-s905x-libretech-cc-v2.dts
deleted file mode 100644
index 6c4e68e..0000000
--- a/arch/arm/dts/meson-gxl-s905x-libretech-cc-v2.dts
+++ /dev/null
@@ -1,313 +0,0 @@
-// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
-/*
- * Copyright (c) 2020 BayLibre, SAS.
- * Author: Jerome Brunet <jbrunet@baylibre.com>
- */
-
-/dts-v1/;
-
-#include <dt-bindings/input/input.h>
-#include <dt-bindings/leds/common.h>
-#include <dt-bindings/sound/meson-aiu.h>
-
-#include "meson-gxl-s905x.dtsi"
-
-/ {
- compatible = "libretech,aml-s905x-cc-v2", "amlogic,s905x",
- "amlogic,meson-gxl";
- model = "Libre Computer AML-S905X-CC V2";
-
- aliases {
- serial0 = &uart_AO;
- ethernet0 = ðmac;
- spi0 = &spifc;
- };
-
- chosen {
- stdout-path = "serial0:115200n8";
- };
-
- emmc_pwrseq: emmc-pwrseq {
- compatible = "mmc-pwrseq-emmc";
- reset-gpios = <&gpio BOOT_9 GPIO_ACTIVE_LOW>;
- };
-
- hdmi-connector {
- compatible = "hdmi-connector";
- type = "a";
-
- port {
- hdmi_connector_in: endpoint {
- remote-endpoint = <&hdmi_tx_tmds_out>;
- };
- };
- };
-
- leds {
- compatible = "gpio-leds";
-
- led-blue {
- color = <LED_COLOR_ID_BLUE>;
- function = LED_FUNCTION_STATUS;
- gpios = <&gpio GPIODV_24 GPIO_ACTIVE_HIGH>;
- linux,default-trigger = "heartbeat";
- panic-indicator;
- };
-
- led-green {
- color = <LED_COLOR_ID_GREEN>;
- function = LED_FUNCTION_DISK_ACTIVITY;
- gpios = <&gpio_ao GPIOAO_2 GPIO_ACTIVE_HIGH>;
- linux,default-trigger = "disk-activity";
- };
- };
-
- memory@0 {
- device_type = "memory";
- reg = <0x0 0x0 0x0 0x80000000>;
- };
-
- ao_5v: regulator-ao_5v {
- compatible = "regulator-fixed";
- regulator-name = "AO_5V";
- regulator-min-microvolt = <5000000>;
- regulator-max-microvolt = <5000000>;
- vin-supply = <&dc_in>;
- regulator-always-on;
- };
-
- dc_in: regulator-dc_in {
- compatible = "regulator-fixed";
- regulator-name = "DC_IN";
- regulator-min-microvolt = <5000000>;
- regulator-max-microvolt = <5000000>;
- regulator-always-on;
- };
-
- vcck: regulator-vcck {
- compatible = "regulator-fixed";
- regulator-name = "VCCK";
- regulator-min-microvolt = <3300000>;
- regulator-max-microvolt = <3300000>;
- vin-supply = <&ao_5v>;
- regulator-always-on;
- };
-
- vcc_card: regulator-vcc_card {
- compatible = "regulator-fixed";
- regulator-name = "VCC_CARD";
- regulator-min-microvolt = <3300000>;
- regulator-max-microvolt = <3300000>;
- vin-supply = <&vddio_ao3v3>;
-
- gpio = <&gpio GPIOCLK_1 GPIO_ACTIVE_HIGH>;
- enable-active-high;
- };
-
- vcc5v: regulator-vcc5v {
- compatible = "regulator-fixed";
- regulator-name = "VCC5V";
- regulator-min-microvolt = <5000000>;
- regulator-max-microvolt = <5000000>;
- vin-supply = <&ao_5v>;
-
- gpio = <&gpio GPIOH_3 GPIO_OPEN_DRAIN>;
- };
-
- vddio_ao3v3: regulator-vddio_ao3v3 {
- compatible = "regulator-fixed";
- regulator-name = "VDDIO_AO3V3";
- regulator-min-microvolt = <3300000>;
- regulator-max-microvolt = <3300000>;
- vin-supply = <&ao_5v>;
- regulator-always-on;
- };
-
- vddio_card: regulator-vddio-card {
- compatible = "regulator-gpio";
- regulator-name = "VDDIO_CARD";
- regulator-min-microvolt = <1800000>;
- regulator-max-microvolt = <3300000>;
-
- gpios = <&gpio_ao GPIOAO_3 GPIO_ACTIVE_HIGH>;
- gpios-states = <0>;
-
- states = <3300000 0>,
- <1800000 1>;
-
- regulator-settling-time-up-us = <200>;
- regulator-settling-time-down-us = <50000>;
- };
-
- vddio_ao18: regulator-vddio_ao18 {
- compatible = "regulator-fixed";
- regulator-name = "VDDIO_AO18";
- regulator-min-microvolt = <1800000>;
- regulator-max-microvolt = <1800000>;
- vin-supply = <&vddio_ao3v3>;
- regulator-always-on;
- };
-
- vcc_1v8: regulator-vcc_1v8 {
- compatible = "regulator-fixed";
- regulator-name = "VCC 1V8";
- regulator-min-microvolt = <1800000>;
- regulator-max-microvolt = <1800000>;
- vin-supply = <&vddio_ao3v3>;
- regulator-always-on;
- };
-
- sound {
- compatible = "amlogic,gx-sound-card";
- model = "LIBRETECH-CC-V2";
- assigned-clocks = <&clkc CLKID_MPLL0>,
- <&clkc CLKID_MPLL1>,
- <&clkc CLKID_MPLL2>;
- assigned-clock-parents = <0>, <0>, <0>;
- assigned-clock-rates = <294912000>,
- <270950400>,
- <393216000>;
- status = "okay";
-
- dai-link-0 {
- sound-dai = <&aiu AIU_CPU CPU_I2S_FIFO>;
- };
-
- dai-link-1 {
- sound-dai = <&aiu AIU_CPU CPU_I2S_ENCODER>;
- dai-format = "i2s";
- mclk-fs = <256>;
-
- codec-0 {
- sound-dai = <&aiu AIU_HDMI CTRL_I2S>;
- };
- };
-
- dai-link-2 {
- sound-dai = <&aiu AIU_HDMI CTRL_OUT>;
-
- codec-0 {
- sound-dai = <&hdmi_tx>;
- };
- };
- };
-};
-
-&aiu {
- status = "okay";
-};
-
-&cec_AO {
- status = "okay";
- pinctrl-0 = <&ao_cec_pins>;
- pinctrl-names = "default";
- hdmi-phandle = <&hdmi_tx>;
-};
-
-ðmac {
- status = "okay";
-};
-
-&internal_phy {
- pinctrl-0 = <ð_link_led_pins>, <ð_act_led_pins>;
- pinctrl-names = "default";
-};
-
-&ir {
- status = "okay";
- pinctrl-0 = <&remote_input_ao_pins>;
- pinctrl-names = "default";
-};
-
-&hdmi_tx {
- status = "okay";
- pinctrl-0 = <&hdmi_hpd_pins>, <&hdmi_i2c_pins>;
- hdmi-supply = <&vcc5v>;
- pinctrl-names = "default";
-};
-
-&hdmi_tx_tmds_port {
- hdmi_tx_tmds_out: endpoint {
- remote-endpoint = <&hdmi_connector_in>;
- };
-};
-
-&saradc {
- status = "okay";
- vref-supply = <&vddio_ao18>;
-};
-
-/* SD card */
-&sd_emmc_b {
- pinctrl-0 = <&sdcard_pins>;
- pinctrl-1 = <&sdcard_clk_gate_pins>;
- pinctrl-names = "default", "clk-gate";
-
- bus-width = <4>;
- cap-sd-highspeed;
- sd-uhs-sdr12;
- sd-uhs-sdr25;
- sd-uhs-sdr50;
- sd-uhs-ddr50;
- max-frequency = <100000000>;
- disable-wp;
-
- cd-gpios = <&gpio CARD_6 GPIO_ACTIVE_LOW>;
-
- vmmc-supply = <&vcc_card>;
- vqmmc-supply = <&vddio_card>;
-
- status = "okay";
-};
-
-/* eMMC */
-&sd_emmc_c {
- pinctrl-0 = <&emmc_pins>;
- pinctrl-1 = <&emmc_clk_gate_pins>;
- pinctrl-names = "default", "clk-gate";
-
- bus-width = <8>;
- cap-mmc-highspeed;
- mmc-hs200-1_8v;
- max-frequency = <200000000>;
- disable-wp;
-
- mmc-pwrseq = <&emmc_pwrseq>;
- vmmc-supply = <&vddio_ao3v3>;
- vqmmc-supply = <&vcc_1v8>;
-
- status = "okay";
-};
-
-&spifc {
- status = "okay";
- pinctrl-0 = <&nor_pins>;
- pinctrl-names = "default";
-
- nor_4u1: flash@0 {
- #address-cells = <1>;
- #size-cells = <1>;
- compatible = "jedec,spi-nor";
- reg = <0>;
- spi-max-frequency = <3000000>;
- };
-};
-
-&uart_AO {
- status = "okay";
- pinctrl-0 = <&uart_ao_a_pins>;
- pinctrl-names = "default";
-};
-
-&usb {
- status = "okay";
- dr_mode = "host";
-};
-
-&usb2_phy0 {
- phy-supply = <&vcc5v>;
-};
-
-&usb2_phy1 {
- phy-supply = <&vcc5v>;
-};
diff --git a/arch/arm/dts/meson-gxl-s905x-libretech-cc.dts b/arch/arm/dts/meson-gxl-s905x-libretech-cc.dts
deleted file mode 100644
index 82bfabf..0000000
--- a/arch/arm/dts/meson-gxl-s905x-libretech-cc.dts
+++ /dev/null
@@ -1,356 +0,0 @@
-// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
-/*
- * Copyright (c) 2017 BayLibre, SAS.
- * Author: Neil Armstrong <narmstrong@baylibre.com>
- * Author: Jerome Brunet <jbrunet@baylibre.com>
- */
-
-/dts-v1/;
-
-#include <dt-bindings/input/input.h>
-#include <dt-bindings/sound/meson-aiu.h>
-
-#include "meson-gxl-s905x.dtsi"
-
-/ {
- compatible = "libretech,aml-s905x-cc", "amlogic,s905x",
- "amlogic,meson-gxl";
- model = "Libre Computer AML-S905X-CC";
-
- aliases {
- serial0 = &uart_AO;
- ethernet0 = ðmac;
- };
-
- dio2133: analog-amplifier {
- compatible = "simple-audio-amplifier";
- sound-name-prefix = "AU2";
- VCC-supply = <&hdmi_5v>;
- enable-gpios = <&gpio GPIOH_5 GPIO_ACTIVE_HIGH>;
- };
-
- chosen {
- stdout-path = "serial0:115200n8";
- };
-
- cvbs-connector {
- compatible = "composite-video-connector";
-
- port {
- cvbs_connector_in: endpoint {
- remote-endpoint = <&cvbs_vdac_out>;
- };
- };
- };
-
- emmc_pwrseq: emmc-pwrseq {
- compatible = "mmc-pwrseq-emmc";
- reset-gpios = <&gpio BOOT_9 GPIO_ACTIVE_LOW>;
- };
-
- hdmi-connector {
- compatible = "hdmi-connector";
- type = "a";
-
- port {
- hdmi_connector_in: endpoint {
- remote-endpoint = <&hdmi_tx_tmds_out>;
- };
- };
- };
-
- leds {
- compatible = "gpio-leds";
-
- led-system {
- label = "librecomputer:system-status";
- gpios = <&gpio GPIODV_24 GPIO_ACTIVE_HIGH>;
- default-state = "on";
- panic-indicator;
- };
-
- led-blue {
- label = "librecomputer:blue";
- gpios = <&gpio_ao GPIOAO_2 GPIO_ACTIVE_HIGH>;
- linux,default-trigger = "heartbeat";
- };
- };
-
- memory@0 {
- device_type = "memory";
- reg = <0x0 0x0 0x0 0x80000000>;
- };
-
- hdmi_5v: regulator-hdmi-5v {
- compatible = "regulator-fixed";
-
- regulator-name = "HDMI_5V";
- regulator-min-microvolt = <5000000>;
- regulator-max-microvolt = <5000000>;
-
- gpio = <&gpio GPIOH_3 GPIO_ACTIVE_HIGH>;
- enable-active-high;
- regulator-always-on;
- };
-
- vcc_3v3: regulator-vcc_3v3 {
- compatible = "regulator-fixed";
- regulator-name = "VCC_3V3";
- regulator-min-microvolt = <3300000>;
- regulator-max-microvolt = <3300000>;
- };
-
- vcc_card: regulator-vcc-card {
- compatible = "regulator-gpio";
-
- regulator-name = "VCC_CARD";
- regulator-min-microvolt = <1800000>;
- regulator-max-microvolt = <3300000>;
-
- gpios = <&gpio_ao GPIOAO_3 GPIO_ACTIVE_HIGH>;
- gpios-states = <0>;
-
- states = <3300000 0>,
- <1800000 1>;
-
- regulator-settling-time-up-us = <200>;
- regulator-settling-time-down-us = <50000>;
- };
-
- vddio_ao18: regulator-vddio_ao18 {
- compatible = "regulator-fixed";
- regulator-name = "VDDIO_AO18";
- regulator-min-microvolt = <1800000>;
- regulator-max-microvolt = <1800000>;
- };
-
- /* This is provided by LDOs on the eMMC daugther card */
- vddio_boot: regulator-vddio_boot {
- compatible = "regulator-fixed";
- regulator-name = "VDDIO_BOOT";
- regulator-min-microvolt = <1800000>;
- regulator-max-microvolt = <1800000>;
- vin-supply = <&vcc_3v3>;
- };
-
- sound {
- compatible = "amlogic,gx-sound-card";
- model = "LIBRETECH-CC";
- audio-aux-devs = <&dio2133>;
- audio-widgets = "Line", "Lineout";
- audio-routing = "AU2 INL", "ACODEC LOLN",
- "AU2 INR", "ACODEC LORN",
- "Lineout", "AU2 OUTL",
- "Lineout", "AU2 OUTR";
- assigned-clocks = <&clkc CLKID_MPLL0>,
- <&clkc CLKID_MPLL1>,
- <&clkc CLKID_MPLL2>;
- assigned-clock-parents = <0>, <0>, <0>;
- assigned-clock-rates = <294912000>,
- <270950400>,
- <393216000>;
- status = "okay";
-
- dai-link-0 {
- sound-dai = <&aiu AIU_CPU CPU_I2S_FIFO>;
- };
-
- dai-link-1 {
- sound-dai = <&aiu AIU_CPU CPU_I2S_ENCODER>;
- dai-format = "i2s";
- mclk-fs = <256>;
-
- codec-0 {
- sound-dai = <&aiu AIU_HDMI CTRL_I2S>;
- };
-
- codec-1 {
- sound-dai = <&aiu AIU_ACODEC CTRL_I2S>;
- };
- };
-
- dai-link-2 {
- sound-dai = <&aiu AIU_HDMI CTRL_OUT>;
-
- codec-0 {
- sound-dai = <&hdmi_tx>;
- };
- };
-
- dai-link-3 {
- sound-dai = <&aiu AIU_ACODEC CTRL_OUT>;
-
- codec-0 {
- sound-dai = <&acodec>;
- };
- };
- };
-};
-
-&acodec {
- AVDD-supply = <&vddio_ao18>;
- status = "okay";
-};
-
-&aiu {
- status = "okay";
-};
-
-&cec_AO {
- status = "okay";
- pinctrl-0 = <&ao_cec_pins>;
- pinctrl-names = "default";
- hdmi-phandle = <&hdmi_tx>;
-};
-
-&cvbs_vdac_port {
- cvbs_vdac_out: endpoint {
- remote-endpoint = <&cvbs_connector_in>;
- };
-};
-
-ðmac {
- status = "okay";
-};
-
-&internal_phy {
- pinctrl-0 = <ð_link_led_pins>, <ð_act_led_pins>;
- pinctrl-names = "default";
-};
-
-&ir {
- status = "okay";
- pinctrl-0 = <&remote_input_ao_pins>;
- pinctrl-names = "default";
-};
-
-&hdmi_tx {
- status = "okay";
- pinctrl-0 = <&hdmi_hpd_pins>, <&hdmi_i2c_pins>;
- pinctrl-names = "default";
- hdmi-supply = <&hdmi_5v>;
-};
-
-&hdmi_tx_tmds_port {
- hdmi_tx_tmds_out: endpoint {
- remote-endpoint = <&hdmi_connector_in>;
- };
-};
-
-&gpio_ao {
- gpio-line-names = "UART TX",
- "UART RX",
- "Blue LED",
- "SDCard Voltage Switch",
- "7J1 Header Pin5",
- "7J1 Header Pin3",
- "7J1 Header Pin12",
- "IR In",
- "9J3 Switch HDMI CEC/7J1 Header Pin11",
- "7J1 Header Pin13",
- /* GPIO_TEST_N */
- "7J1 Header Pin15";
-};
-
-&gpio {
- gpio-line-names = /* Bank GPIOZ */
- "", "", "", "", "", "", "",
- "", "", "", "", "", "", "",
- "Eth Link LED", "Eth Activity LED",
- /* Bank GPIOH */
- "HDMI HPD", "HDMI SDA", "HDMI SCL",
- "HDMI_5V_EN", "9J1 Header Pin2",
- "Analog Audio Mute",
- "2J3 Header Pin6",
- "2J3 Header Pin5",
- "2J3 Header Pin4",
- "2J3 Header Pin3",
- /* Bank BOOT */
- "eMMC D0", "eMMC D1", "eMMC D2", "eMMC D3",
- "eMMC D4", "eMMC D5", "eMMC D6", "eMMC D7",
- "eMMC Clk", "eMMC Reset", "eMMC CMD",
- "ALT BOOT MODE", "", "", "", "eMMC Data Strobe",
- /* Bank CARD */
- "SDCard D1", "SDCard D0", "SDCard CLK", "SDCard CMD",
- "SDCard D3", "SDCard D2", "SDCard Det",
- /* Bank GPIODV */
- "", "", "", "", "", "", "", "", "", "", "", "",
- "", "", "", "", "", "", "", "", "", "", "", "",
- "Green LED", "VCCK Enable",
- "7J1 Header Pin27", "7J1 Header Pin28",
- "VCCK Regulator", "VDDEE Regulator",
- /* Bank GPIOX */
- "7J1 Header Pin22", "7J1 Header Pin26",
- "7J1 Header Pin36", "7J1 Header Pin38",
- "7J1 Header Pin40", "7J1 Header Pin37",
- "7J1 Header Pin33", "7J1 Header Pin35",
- "7J1 Header Pin19", "7J1 Header Pin21",
- "7J1 Header Pin24", "7J1 Header Pin23",
- "7J1 Header Pin8", "7J1 Header Pin10",
- "7J1 Header Pin16", "7J1 Header Pin18",
- "7J1 Header Pin32", "7J1 Header Pin29",
- "7J1 Header Pin31",
- /* Bank GPIOCLK */
- "7J1 Header Pin7", "";
-};
-
-&saradc {
- status = "okay";
- vref-supply = <&vddio_ao18>;
-};
-
-/* SD card */
-&sd_emmc_b {
- status = "okay";
- pinctrl-0 = <&sdcard_pins>;
- pinctrl-1 = <&sdcard_clk_gate_pins>;
- pinctrl-names = "default", "clk-gate";
-
- bus-width = <4>;
- cap-sd-highspeed;
- max-frequency = <50000000>;
- disable-wp;
-
- cd-gpios = <&gpio CARD_6 GPIO_ACTIVE_LOW>;
-
- vmmc-supply = <&vcc_3v3>;
- vqmmc-supply = <&vcc_card>;
-};
-
-/* eMMC */
-&sd_emmc_c {
- status = "okay";
- pinctrl-0 = <&emmc_pins>, <&emmc_ds_pins>;
- pinctrl-1 = <&emmc_clk_gate_pins>;
- pinctrl-names = "default", "clk-gate";
-
- bus-width = <8>;
- cap-mmc-highspeed;
- mmc-ddr-1_8v;
- mmc-hs200-1_8v;
- max-frequency = <200000000>;
- disable-wp;
-
- mmc-pwrseq = <&emmc_pwrseq>;
- vmmc-supply = <&vcc_3v3>;
- vqmmc-supply = <&vddio_boot>;
-};
-
-&uart_AO {
- status = "okay";
- pinctrl-0 = <&uart_ao_a_pins>;
- pinctrl-names = "default";
-};
-
-&usb {
- status = "okay";
- dr_mode = "host";
-};
-
-&usb2_phy0 {
- /*
- * even though the schematics don't show it:
- * HDMI_5V is also used as supply for the USB VBUS.
- */
- phy-supply = <&hdmi_5v>;
-};
diff --git a/arch/arm/dts/meson-gxl-s905x-p212.dts b/arch/arm/dts/meson-gxl-s905x-p212.dts
deleted file mode 100644
index 9b4ea6a..0000000
--- a/arch/arm/dts/meson-gxl-s905x-p212.dts
+++ /dev/null
@@ -1,134 +0,0 @@
-// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
-/*
- * Copyright (c) 2016 Endless Computers, Inc.
- * Author: Carlo Caione <carlo@endlessm.com>
- */
-
-/dts-v1/;
-
-#include "meson-gxl-s905x-p212.dtsi"
-#include <dt-bindings/sound/meson-aiu.h>
-
-/ {
- compatible = "amlogic,p212", "amlogic,s905x", "amlogic,meson-gxl";
- model = "Amlogic Meson GXL (S905X) P212 Development Board";
-
- dio2133: analog-amplifier {
- compatible = "simple-audio-amplifier";
- sound-name-prefix = "AU2";
- VCC-supply = <&hdmi_5v>;
- enable-gpios = <&gpio GPIOH_5 GPIO_ACTIVE_HIGH>;
- };
-
- cvbs-connector {
- compatible = "composite-video-connector";
-
- port {
- cvbs_connector_in: endpoint {
- remote-endpoint = <&cvbs_vdac_out>;
- };
- };
- };
-
- hdmi-connector {
- compatible = "hdmi-connector";
- type = "a";
-
- port {
- hdmi_connector_in: endpoint {
- remote-endpoint = <&hdmi_tx_tmds_out>;
- };
- };
- };
-
- sound {
- compatible = "amlogic,gx-sound-card";
- model = "S905X-P212";
- audio-aux-devs = <&dio2133>;
- audio-widgets = "Line", "Lineout";
- audio-routing = "AU2 INL", "ACODEC LOLN",
- "AU2 INR", "ACODEC LORN",
- "Lineout", "AU2 OUTL",
- "Lineout", "AU2 OUTR";
- assigned-clocks = <&clkc CLKID_MPLL0>,
- <&clkc CLKID_MPLL1>,
- <&clkc CLKID_MPLL2>;
- assigned-clock-parents = <0>, <0>, <0>;
- assigned-clock-rates = <294912000>,
- <270950400>,
- <393216000>;
- dai-link-0 {
- sound-dai = <&aiu AIU_CPU CPU_I2S_FIFO>;
- };
-
- dai-link-1 {
- sound-dai = <&aiu AIU_CPU CPU_I2S_ENCODER>;
- dai-format = "i2s";
- mclk-fs = <256>;
-
- codec-0 {
- sound-dai = <&aiu AIU_HDMI CTRL_I2S>;
- };
-
- codec-1 {
- sound-dai = <&aiu AIU_ACODEC CTRL_I2S>;
- };
- };
-
- dai-link-2 {
- sound-dai = <&aiu AIU_HDMI CTRL_OUT>;
-
- codec-0 {
- sound-dai = <&hdmi_tx>;
- };
- };
-
- dai-link-3 {
- sound-dai = <&aiu AIU_ACODEC CTRL_OUT>;
-
- codec-0 {
- sound-dai = <&acodec>;
- };
- };
- };
-};
-
-&acodec {
- AVDD-supply = <&vddio_ao18>;
- status = "okay";
-};
-
-&aiu {
- status = "okay";
-};
-
-&cec_AO {
- status = "okay";
- pinctrl-0 = <&ao_cec_pins>;
- pinctrl-names = "default";
- hdmi-phandle = <&hdmi_tx>;
-};
-
-&cvbs_vdac_port {
- cvbs_vdac_out: endpoint {
- remote-endpoint = <&cvbs_connector_in>;
- };
-};
-
-&hdmi_tx {
- status = "okay";
- pinctrl-0 = <&hdmi_hpd_pins>, <&hdmi_i2c_pins>;
- pinctrl-names = "default";
- hdmi-supply = <&hdmi_5v>;
-};
-
-&hdmi_tx_tmds_port {
- hdmi_tx_tmds_out: endpoint {
- remote-endpoint = <&hdmi_connector_in>;
- };
-};
-
-/* This UART is brought out to the DB9 connector */
-&uart_AO {
- status = "okay";
-};
diff --git a/arch/arm/dts/meson-gxl-s905x-p212.dtsi b/arch/arm/dts/meson-gxl-s905x-p212.dtsi
deleted file mode 100644
index a150cc0..0000000
--- a/arch/arm/dts/meson-gxl-s905x-p212.dtsi
+++ /dev/null
@@ -1,213 +0,0 @@
-// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
-/*
- * Copyright (c) 2016 Martin Blumenstingl <martin.blumenstingl@googlemail.com>.
- * Based on meson-gx-p23x-q20x.dtsi:
- * - Copyright (c) 2016 Endless Computers, Inc.
- * Author: Carlo Caione <carlo@endlessm.com>
- * - Copyright (c) 2016 BayLibre, SAS.
- * Author: Neil Armstrong <narmstrong@baylibre.com>
- */
-
-/* Common DTSI for devices which are based on the P212 reference board. */
-
-#include "meson-gxl-s905x.dtsi"
-
-/ {
- aliases {
- serial0 = &uart_AO;
- ethernet0 = ðmac;
- };
-
- chosen {
- stdout-path = "serial0:115200n8";
- };
-
- memory@0 {
- device_type = "memory";
- reg = <0x0 0x0 0x0 0x80000000>;
- };
-
- hdmi_5v: regulator-hdmi-5v {
- compatible = "regulator-fixed";
-
- regulator-name = "HDMI_5V";
- regulator-min-microvolt = <5000000>;
- regulator-max-microvolt = <5000000>;
-
- gpio = <&gpio GPIOH_3 GPIO_ACTIVE_HIGH>;
- enable-active-high;
- regulator-always-on;
- };
-
- vddio_boot: regulator-vddio_boot {
- compatible = "regulator-fixed";
- regulator-name = "VDDIO_BOOT";
- regulator-min-microvolt = <1800000>;
- regulator-max-microvolt = <1800000>;
- };
-
- vddao_3v3: regulator-vddao_3v3 {
- compatible = "regulator-fixed";
- regulator-name = "VDDAO_3V3";
- regulator-min-microvolt = <3300000>;
- regulator-max-microvolt = <3300000>;
- };
-
- vddio_ao18: regulator-vddio_ao18 {
- compatible = "regulator-fixed";
- regulator-name = "VDDIO_AO18";
- regulator-min-microvolt = <1800000>;
- regulator-max-microvolt = <1800000>;
- };
-
- vcc_3v3: regulator-vcc_3v3 {
- compatible = "regulator-fixed";
- regulator-name = "VCC_3V3";
- regulator-min-microvolt = <3300000>;
- regulator-max-microvolt = <3300000>;
- };
-
- emmc_pwrseq: emmc-pwrseq {
- compatible = "mmc-pwrseq-emmc";
- reset-gpios = <&gpio BOOT_9 GPIO_ACTIVE_LOW>;
- };
-
- wifi32k: wifi32k {
- compatible = "pwm-clock";
- #clock-cells = <0>;
- clock-frequency = <32768>;
- pwms = <&pwm_ef 0 30518 0>; /* PWM_E at 32.768KHz */
- };
-
- sdio_pwrseq: sdio-pwrseq {
- compatible = "mmc-pwrseq-simple";
- reset-gpios = <&gpio GPIOX_6 GPIO_ACTIVE_LOW>;
- clocks = <&wifi32k>;
- clock-names = "ext_clock";
- };
-};
-
-ðmac {
- status = "okay";
-};
-
-&ir {
- status = "okay";
- pinctrl-0 = <&remote_input_ao_pins>;
- pinctrl-names = "default";
-};
-
-&pwm_ef {
- status = "okay";
- pinctrl-0 = <&pwm_e_pins>;
- pinctrl-names = "default";
- clocks = <&clkc CLKID_FCLK_DIV4>;
- clock-names = "clkin0";
-};
-
-&saradc {
- status = "okay";
- vref-supply = <&vddio_ao18>;
-};
-
-/* Wireless SDIO Module */
-&sd_emmc_a {
- status = "okay";
- pinctrl-0 = <&sdio_pins>;
- pinctrl-1 = <&sdio_clk_gate_pins>;
- pinctrl-names = "default", "clk-gate";
- #address-cells = <1>;
- #size-cells = <0>;
-
- bus-width = <4>;
- cap-sd-highspeed;
- max-frequency = <50000000>;
-
- non-removable;
- disable-wp;
-
- /* WiFi firmware requires power to be kept while in suspend */
- keep-power-in-suspend;
-
- mmc-pwrseq = <&sdio_pwrseq>;
-
- vmmc-supply = <&vddao_3v3>;
- vqmmc-supply = <&vddio_boot>;
-
- brcmf: wifi@1 {
- reg = <1>;
- compatible = "brcm,bcm4329-fmac";
- };
-};
-
-/* SD card */
-&sd_emmc_b {
- status = "okay";
- pinctrl-0 = <&sdcard_pins>;
- pinctrl-1 = <&sdcard_clk_gate_pins>;
- pinctrl-names = "default", "clk-gate";
-
- bus-width = <4>;
- cap-sd-highspeed;
- max-frequency = <50000000>;
- disable-wp;
-
- cd-gpios = <&gpio CARD_6 GPIO_ACTIVE_LOW>;
-
- vmmc-supply = <&vddao_3v3>;
- vqmmc-supply = <&vddio_boot>;
-};
-
-/* eMMC */
-&sd_emmc_c {
- status = "okay";
- pinctrl-0 = <&emmc_pins>, <&emmc_ds_pins>;
- pinctrl-1 = <&emmc_clk_gate_pins>;
- pinctrl-names = "default", "clk-gate";
-
- bus-width = <8>;
- cap-mmc-highspeed;
- max-frequency = <200000000>;
- non-removable;
- disable-wp;
- mmc-ddr-1_8v;
- mmc-hs200-1_8v;
-
- mmc-pwrseq = <&emmc_pwrseq>;
- vmmc-supply = <&vcc_3v3>;
- vqmmc-supply = <&vddio_boot>;
-};
-
-/* This is connected to the Bluetooth module: */
-&uart_A {
- status = "okay";
- pinctrl-0 = <&uart_a_pins>, <&uart_a_cts_rts_pins>;
- pinctrl-names = "default";
- uart-has-rtscts;
-
- bluetooth {
- compatible = "brcm,bcm43438-bt";
- shutdown-gpios = <&gpio GPIOX_17 GPIO_ACTIVE_HIGH>;
- max-speed = <2000000>;
- clocks = <&wifi32k>;
- clock-names = "lpo";
- };
-};
-
-&uart_AO {
- status = "okay";
- pinctrl-0 = <&uart_ao_a_pins>;
- pinctrl-names = "default";
-};
-
-&usb {
- status = "okay";
- dr_mode = "host";
-};
-
-&usb2_phy0 {
- /*
- * HDMI_5V is also used as supply for the USB VBUS.
- */
- phy-supply = <&hdmi_5v>;
-};
diff --git a/arch/arm/dts/meson-gxl-s905x.dtsi b/arch/arm/dts/meson-gxl-s905x.dtsi
deleted file mode 100644
index 40c19f6..0000000
--- a/arch/arm/dts/meson-gxl-s905x.dtsi
+++ /dev/null
@@ -1,18 +0,0 @@
-// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
-/*
- * Copyright (c) 2016 Endless Computers, Inc.
- * Author: Carlo Caione <carlo@endlessm.com>
- */
-
-#include "meson-gxl.dtsi"
-#include "meson-gxl-mali.dtsi"
-
-/ {
- compatible = "amlogic,s905x", "amlogic,meson-gxl";
-};
-
-/* S905X only has access to its internal PHY */
-ðmac {
- phy-mode = "rmii";
- phy-handle = <&internal_phy>;
-};
diff --git a/arch/arm/dts/meson-gxl.dtsi b/arch/arm/dts/meson-gxl.dtsi
deleted file mode 100644
index 17bcfa4..0000000
--- a/arch/arm/dts/meson-gxl.dtsi
+++ /dev/null
@@ -1,940 +0,0 @@
-// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
-/*
- * Copyright (c) 2016 Endless Computers, Inc.
- * Author: Carlo Caione <carlo@endlessm.com>
- */
-
-#include "meson-gx.dtsi"
-#include <dt-bindings/clock/gxbb-clkc.h>
-#include <dt-bindings/clock/gxbb-aoclkc.h>
-#include <dt-bindings/gpio/meson-gxl-gpio.h>
-#include <dt-bindings/reset/amlogic,meson-gxbb-reset.h>
-
-/ {
- compatible = "amlogic,meson-gxl";
-
- soc {
- usb: usb@d0078080 {
- compatible = "amlogic,meson-gxl-usb-ctrl";
- reg = <0x0 0xd0078080 0x0 0x20>;
- interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
- #address-cells = <2>;
- #size-cells = <2>;
- ranges;
-
- clocks = <&clkc CLKID_USB>, <&clkc CLKID_USB1_DDR_BRIDGE>;
- clock-names = "usb_ctrl", "ddr";
- resets = <&reset RESET_USB_OTG>;
-
- dr_mode = "otg";
-
- phys = <&usb2_phy0>, <&usb2_phy1>;
- phy-names = "usb2-phy0", "usb2-phy1";
-
- dwc2: usb@c9100000 {
- compatible = "amlogic,meson-g12a-usb", "snps,dwc2";
- reg = <0x0 0xc9100000 0x0 0x40000>;
- interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&clkc CLKID_USB1>;
- clock-names = "otg";
- phys = <&usb2_phy1>;
- dr_mode = "peripheral";
- g-rx-fifo-size = <192>;
- g-np-tx-fifo-size = <128>;
- g-tx-fifo-size = <128 128 16 16 16>;
- };
-
- dwc3: usb@c9000000 {
- compatible = "snps,dwc3";
- reg = <0x0 0xc9000000 0x0 0x100000>;
- interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
- dr_mode = "host";
- maximum-speed = "high-speed";
- snps,dis_u2_susphy_quirk;
- };
- };
-
- acodec: audio-controller@c8832000 {
- compatible = "amlogic,t9015";
- reg = <0x0 0xc8832000 0x0 0x14>;
- #sound-dai-cells = <0>;
- sound-name-prefix = "ACODEC";
- clocks = <&clkc CLKID_ACODEC>;
- clock-names = "pclk";
- resets = <&reset RESET_ACODEC>;
- status = "disabled";
- };
-
- crypto: crypto@c883e000 {
- compatible = "amlogic,gxl-crypto";
- reg = <0x0 0xc883e000 0x0 0x36>;
- interrupts = <GIC_SPI 188 IRQ_TYPE_EDGE_RISING>,
- <GIC_SPI 189 IRQ_TYPE_EDGE_RISING>;
- clocks = <&clkc CLKID_BLKMV>;
- clock-names = "blkmv";
- status = "okay";
- };
- };
-};
-
-&aiu {
- compatible = "amlogic,aiu-gxl", "amlogic,aiu";
- clocks = <&clkc CLKID_AIU_GLUE>,
- <&clkc CLKID_I2S_OUT>,
- <&clkc CLKID_AOCLK_GATE>,
- <&clkc CLKID_CTS_AMCLK>,
- <&clkc CLKID_MIXER_IFACE>,
- <&clkc CLKID_IEC958>,
- <&clkc CLKID_IEC958_GATE>,
- <&clkc CLKID_CTS_MCLK_I958>,
- <&clkc CLKID_CTS_I958>;
- clock-names = "pclk",
- "i2s_pclk",
- "i2s_aoclk",
- "i2s_mclk",
- "i2s_mixer",
- "spdif_pclk",
- "spdif_aoclk",
- "spdif_mclk",
- "spdif_mclk_sel";
- resets = <&reset RESET_AIU>;
-};
-
-&apb {
- usb2_phy0: phy@78000 {
- compatible = "amlogic,meson-gxl-usb2-phy";
- #phy-cells = <0>;
- reg = <0x0 0x78000 0x0 0x20>;
- clocks = <&clkc CLKID_USB>;
- clock-names = "phy";
- resets = <&reset RESET_USB_OTG>;
- reset-names = "phy";
- status = "okay";
- };
-
- usb2_phy1: phy@78020 {
- compatible = "amlogic,meson-gxl-usb2-phy";
- #phy-cells = <0>;
- reg = <0x0 0x78020 0x0 0x20>;
- clocks = <&clkc CLKID_USB>;
- clock-names = "phy";
- resets = <&reset RESET_USB_OTG>;
- reset-names = "phy";
- status = "okay";
- };
-};
-
-&efuse {
- clocks = <&clkc CLKID_EFUSE>;
-};
-
-ðmac {
- clocks = <&clkc CLKID_ETH>,
- <&clkc CLKID_FCLK_DIV2>,
- <&clkc CLKID_MPLL2>,
- <&clkc CLKID_FCLK_DIV2>;
- clock-names = "stmmaceth", "clkin0", "clkin1", "timing-adjustment";
-
- mdio0: mdio {
- #address-cells = <1>;
- #size-cells = <0>;
- compatible = "snps,dwmac-mdio";
- };
-};
-
-&aobus {
- pinctrl_aobus: pinctrl@14 {
- compatible = "amlogic,meson-gxl-aobus-pinctrl";
- #address-cells = <2>;
- #size-cells = <2>;
- ranges;
-
- gpio_ao: bank@14 {
- reg = <0x0 0x00014 0x0 0x8>,
- <0x0 0x0002c 0x0 0x4>,
- <0x0 0x00024 0x0 0x8>;
- reg-names = "mux", "pull", "gpio";
- gpio-controller;
- #gpio-cells = <2>;
- gpio-ranges = <&pinctrl_aobus 0 0 14>;
- };
-
- uart_ao_a_pins: uart_ao_a {
- mux {
- groups = "uart_tx_ao_a", "uart_rx_ao_a";
- function = "uart_ao";
- bias-disable;
- };
- };
-
- uart_ao_a_cts_rts_pins: uart_ao_a_cts_rts {
- mux {
- groups = "uart_cts_ao_a",
- "uart_rts_ao_a";
- function = "uart_ao";
- bias-disable;
- };
- };
-
- uart_ao_b_pins: uart_ao_b {
- mux {
- groups = "uart_tx_ao_b", "uart_rx_ao_b";
- function = "uart_ao_b";
- bias-disable;
- };
- };
-
- uart_ao_b_0_1_pins: uart_ao_b_0_1 {
- mux {
- groups = "uart_tx_ao_b_0", "uart_rx_ao_b_1";
- function = "uart_ao_b";
- bias-disable;
- };
- };
-
- uart_ao_b_cts_rts_pins: uart_ao_b_cts_rts {
- mux {
- groups = "uart_cts_ao_b",
- "uart_rts_ao_b";
- function = "uart_ao_b";
- bias-disable;
- };
- };
-
- remote_input_ao_pins: remote_input_ao {
- mux {
- groups = "remote_input_ao";
- function = "remote_input_ao";
- bias-disable;
- };
- };
-
- i2c_ao_pins: i2c_ao {
- mux {
- groups = "i2c_sck_ao",
- "i2c_sda_ao";
- function = "i2c_ao";
- bias-disable;
- };
- };
-
- pwm_ao_a_3_pins: pwm_ao_a_3 {
- mux {
- groups = "pwm_ao_a_3";
- function = "pwm_ao_a";
- bias-disable;
- };
- };
-
- pwm_ao_a_8_pins: pwm_ao_a_8 {
- mux {
- groups = "pwm_ao_a_8";
- function = "pwm_ao_a";
- bias-disable;
- };
- };
-
- pwm_ao_b_pins: pwm_ao_b {
- mux {
- groups = "pwm_ao_b";
- function = "pwm_ao_b";
- bias-disable;
- };
- };
-
- pwm_ao_b_6_pins: pwm_ao_b_6 {
- mux {
- groups = "pwm_ao_b_6";
- function = "pwm_ao_b";
- bias-disable;
- };
- };
-
- i2s_out_ch23_ao_pins: i2s_out_ch23_ao {
- mux {
- groups = "i2s_out_ch23_ao";
- function = "i2s_out_ao";
- bias-disable;
- };
- };
-
- i2s_out_ch45_ao_pins: i2s_out_ch45_ao {
- mux {
- groups = "i2s_out_ch45_ao";
- function = "i2s_out_ao";
- bias-disable;
- };
- };
-
- spdif_out_ao_6_pins: spdif_out_ao_6 {
- mux {
- groups = "spdif_out_ao_6";
- function = "spdif_out_ao";
- bias-disable;
- };
- };
-
- spdif_out_ao_9_pins: spdif_out_ao_9 {
- mux {
- groups = "spdif_out_ao_9";
- function = "spdif_out_ao";
- bias-disable;
- };
- };
-
- ao_cec_pins: ao_cec {
- mux {
- groups = "ao_cec";
- function = "cec_ao";
- bias-disable;
- };
- };
-
- ee_cec_pins: ee_cec {
- mux {
- groups = "ee_cec";
- function = "cec_ao";
- bias-disable;
- };
- };
- };
-};
-
-&cec_AO {
- clocks = <&clkc_AO CLKID_AO_CEC_32K>;
- clock-names = "core";
-};
-
-&clkc_AO {
- compatible = "amlogic,meson-gxl-aoclkc", "amlogic,meson-gx-aoclkc";
- clocks = <&xtal>, <&clkc CLKID_CLK81>;
- clock-names = "xtal", "mpeg-clk";
-};
-
-&gpio_intc {
- compatible = "amlogic,meson-gxl-gpio-intc",
- "amlogic,meson-gpio-intc";
- status = "okay";
-};
-
-&hdmi_tx {
- compatible = "amlogic,meson-gxl-dw-hdmi", "amlogic,meson-gx-dw-hdmi";
- resets = <&reset RESET_HDMITX_CAPB3>,
- <&reset RESET_HDMI_SYSTEM_RESET>,
- <&reset RESET_HDMI_TX>;
- reset-names = "hdmitx_apb", "hdmitx", "hdmitx_phy";
- clocks = <&clkc CLKID_HDMI_PCLK>,
- <&clkc CLKID_CLK81>,
- <&clkc CLKID_GCLK_VENCI_INT0>;
- clock-names = "isfr", "iahb", "venci";
-};
-
-&sysctrl {
- clkc: clock-controller {
- compatible = "amlogic,gxl-clkc";
- #clock-cells = <1>;
- clocks = <&xtal>;
- clock-names = "xtal";
- };
-};
-
-&hwrng {
- clocks = <&clkc CLKID_RNG0>;
- clock-names = "core";
-};
-
-&i2c_A {
- clocks = <&clkc CLKID_I2C>;
-};
-
-&i2c_AO {
- clocks = <&clkc CLKID_AO_I2C>;
-};
-
-&i2c_B {
- clocks = <&clkc CLKID_I2C>;
-};
-
-&i2c_C {
- clocks = <&clkc CLKID_I2C>;
-};
-
-&periphs {
- pinctrl_periphs: pinctrl@4b0 {
- compatible = "amlogic,meson-gxl-periphs-pinctrl";
- #address-cells = <2>;
- #size-cells = <2>;
- ranges;
-
- gpio: bank@4b0 {
- reg = <0x0 0x004b0 0x0 0x28>,
- <0x0 0x004e8 0x0 0x14>,
- <0x0 0x00520 0x0 0x14>,
- <0x0 0x00430 0x0 0x40>;
- reg-names = "mux", "pull", "pull-enable", "gpio";
- gpio-controller;
- #gpio-cells = <2>;
- gpio-ranges = <&pinctrl_periphs 0 0 100>;
- };
-
- emmc_pins: emmc {
- mux-0 {
- groups = "emmc_nand_d07",
- "emmc_cmd";
- function = "emmc";
- bias-pull-up;
- };
-
- mux-1 {
- groups = "emmc_clk";
- function = "emmc";
- bias-disable;
- };
- };
-
- emmc_ds_pins: emmc-ds {
- mux {
- groups = "emmc_ds";
- function = "emmc";
- bias-pull-down;
- };
- };
-
- emmc_clk_gate_pins: emmc_clk_gate {
- mux {
- groups = "BOOT_8";
- function = "gpio_periphs";
- bias-pull-down;
- };
- };
-
- nor_pins: nor {
- mux {
- groups = "nor_d",
- "nor_q",
- "nor_c",
- "nor_cs";
- function = "nor";
- bias-disable;
- };
- };
-
- spi_pins: spi-pins {
- mux {
- groups = "spi_miso",
- "spi_mosi",
- "spi_sclk";
- function = "spi";
- bias-disable;
- };
- };
-
- spi_idle_high_pins: spi-idle-high-pins {
- mux {
- groups = "spi_sclk";
- bias-pull-up;
- };
- };
-
- spi_idle_low_pins: spi-idle-low-pins {
- mux {
- groups = "spi_sclk";
- bias-pull-down;
- };
- };
-
- spi_ss0_pins: spi-ss0 {
- mux {
- groups = "spi_ss0";
- function = "spi";
- bias-disable;
- };
- };
-
- sdcard_pins: sdcard {
- mux-0 {
- groups = "sdcard_d0",
- "sdcard_d1",
- "sdcard_d2",
- "sdcard_d3",
- "sdcard_cmd";
- function = "sdcard";
- bias-pull-up;
- };
-
- mux-1 {
- groups = "sdcard_clk";
- function = "sdcard";
- bias-disable;
- };
- };
-
- sdcard_clk_gate_pins: sdcard_clk_gate {
- mux {
- groups = "CARD_2";
- function = "gpio_periphs";
- bias-pull-down;
- };
- };
-
- sdio_pins: sdio {
- mux-0 {
- groups = "sdio_d0",
- "sdio_d1",
- "sdio_d2",
- "sdio_d3",
- "sdio_cmd";
- function = "sdio";
- bias-pull-up;
- };
-
- mux-1 {
- groups = "sdio_clk";
- function = "sdio";
- bias-disable;
- };
- };
-
- sdio_clk_gate_pins: sdio_clk_gate {
- mux {
- groups = "GPIOX_4";
- function = "gpio_periphs";
- bias-pull-down;
- };
- };
-
- sdio_irq_pins: sdio_irq {
- mux {
- groups = "sdio_irq";
- function = "sdio";
- bias-disable;
- };
- };
-
- uart_a_pins: uart_a {
- mux {
- groups = "uart_tx_a",
- "uart_rx_a";
- function = "uart_a";
- bias-disable;
- };
- };
-
- uart_a_cts_rts_pins: uart_a_cts_rts {
- mux {
- groups = "uart_cts_a",
- "uart_rts_a";
- function = "uart_a";
- bias-disable;
- };
- };
-
- uart_b_pins: uart_b {
- mux {
- groups = "uart_tx_b",
- "uart_rx_b";
- function = "uart_b";
- bias-disable;
- };
- };
-
- uart_b_cts_rts_pins: uart_b_cts_rts {
- mux {
- groups = "uart_cts_b",
- "uart_rts_b";
- function = "uart_b";
- bias-disable;
- };
- };
-
- uart_c_pins: uart_c {
- mux {
- groups = "uart_tx_c",
- "uart_rx_c";
- function = "uart_c";
- bias-disable;
- };
- };
-
- uart_c_cts_rts_pins: uart_c_cts_rts {
- mux {
- groups = "uart_cts_c",
- "uart_rts_c";
- function = "uart_c";
- bias-disable;
- };
- };
-
- i2c_a_pins: i2c_a {
- mux {
- groups = "i2c_sck_a",
- "i2c_sda_a";
- function = "i2c_a";
- bias-disable;
- };
- };
-
- i2c_b_pins: i2c_b {
- mux {
- groups = "i2c_sck_b",
- "i2c_sda_b";
- function = "i2c_b";
- bias-disable;
- };
- };
-
- i2c_c_pins: i2c_c {
- mux {
- groups = "i2c_sck_c",
- "i2c_sda_c";
- function = "i2c_c";
- bias-disable;
- };
- };
-
- i2c_c_dv18_pins: i2c_c_dv18 {
- mux {
- groups = "i2c_sck_c_dv19",
- "i2c_sda_c_dv18";
- function = "i2c_c";
- bias-disable;
- };
- };
-
- eth_pins: eth_c {
- mux {
- groups = "eth_mdio",
- "eth_mdc",
- "eth_clk_rx_clk",
- "eth_rx_dv",
- "eth_rxd0",
- "eth_rxd1",
- "eth_rxd2",
- "eth_rxd3",
- "eth_rgmii_tx_clk",
- "eth_tx_en",
- "eth_txd0",
- "eth_txd1",
- "eth_txd2",
- "eth_txd3";
- function = "eth";
- bias-disable;
- };
- };
-
- eth_link_led_pins: eth_link_led {
- mux {
- groups = "eth_link_led";
- function = "eth_led";
- bias-disable;
- };
- };
-
- eth_act_led_pins: eth_act_led {
- mux {
- groups = "eth_act_led";
- function = "eth_led";
- };
- };
-
- pwm_a_pins: pwm_a {
- mux {
- groups = "pwm_a";
- function = "pwm_a";
- bias-disable;
- };
- };
-
- pwm_b_pins: pwm_b {
- mux {
- groups = "pwm_b";
- function = "pwm_b";
- bias-disable;
- };
- };
-
- pwm_c_pins: pwm_c {
- mux {
- groups = "pwm_c";
- function = "pwm_c";
- bias-disable;
- };
- };
-
- pwm_d_pins: pwm_d {
- mux {
- groups = "pwm_d";
- function = "pwm_d";
- bias-disable;
- };
- };
-
- pwm_e_pins: pwm_e {
- mux {
- groups = "pwm_e";
- function = "pwm_e";
- bias-disable;
- };
- };
-
- pwm_f_clk_pins: pwm_f_clk {
- mux {
- groups = "pwm_f_clk";
- function = "pwm_f";
- bias-disable;
- };
- };
-
- pwm_f_x_pins: pwm_f_x {
- mux {
- groups = "pwm_f_x";
- function = "pwm_f";
- bias-disable;
- };
- };
-
- hdmi_hpd_pins: hdmi_hpd {
- mux {
- groups = "hdmi_hpd";
- function = "hdmi_hpd";
- bias-disable;
- };
- };
-
- hdmi_i2c_pins: hdmi_i2c {
- mux {
- groups = "hdmi_sda", "hdmi_scl";
- function = "hdmi_i2c";
- bias-disable;
- };
- };
-
- i2s_am_clk_pins: i2s_am_clk {
- mux {
- groups = "i2s_am_clk";
- function = "i2s_out";
- bias-disable;
- };
- };
-
- i2s_out_ao_clk_pins: i2s_out_ao_clk {
- mux {
- groups = "i2s_out_ao_clk";
- function = "i2s_out";
- bias-disable;
- };
- };
-
- i2s_out_lr_clk_pins: i2s_out_lr_clk {
- mux {
- groups = "i2s_out_lr_clk";
- function = "i2s_out";
- bias-disable;
- };
- };
-
- i2s_out_ch01_pins: i2s_out_ch01 {
- mux {
- groups = "i2s_out_ch01";
- function = "i2s_out";
- bias-disable;
- };
- };
- i2sout_ch23_z_pins: i2sout_ch23_z {
- mux {
- groups = "i2sout_ch23_z";
- function = "i2s_out";
- bias-disable;
- };
- };
-
- i2sout_ch45_z_pins: i2sout_ch45_z {
- mux {
- groups = "i2sout_ch45_z";
- function = "i2s_out";
- bias-disable;
- };
- };
-
- i2sout_ch67_z_pins: i2sout_ch67_z {
- mux {
- groups = "i2sout_ch67_z";
- function = "i2s_out";
- bias-disable;
- };
- };
-
- spdif_out_h_pins: spdif_out_ao_h {
- mux {
- groups = "spdif_out_h";
- function = "spdif_out";
- bias-disable;
- };
- };
- };
-
- eth_phy_mux: mdio@558 {
- reg = <0x0 0x558 0x0 0xc>;
- compatible = "amlogic,gxl-mdio-mux";
- #address-cells = <1>;
- #size-cells = <0>;
- clocks = <&clkc CLKID_FCLK_DIV4>;
- clock-names = "ref";
- mdio-parent-bus = <&mdio0>;
-
- external_mdio: mdio@0 {
- reg = <0x0>;
- #address-cells = <1>;
- #size-cells = <0>;
- };
-
- internal_mdio: mdio@1 {
- reg = <0x1>;
- #address-cells = <1>;
- #size-cells = <0>;
-
- internal_phy: ethernet-phy@8 {
- compatible = "ethernet-phy-id0181.4400";
- interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
- reg = <8>;
- max-speed = <100>;
- };
- };
- };
-};
-
-&pwrc {
- resets = <&reset RESET_VIU>,
- <&reset RESET_VENC>,
- <&reset RESET_VCBUS>,
- <&reset RESET_BT656>,
- <&reset RESET_DVIN_RESET>,
- <&reset RESET_RDMA>,
- <&reset RESET_VENCI>,
- <&reset RESET_VENCP>,
- <&reset RESET_VDAC>,
- <&reset RESET_VDI6>,
- <&reset RESET_VENCL>,
- <&reset RESET_VID_LOCK>;
- reset-names = "viu", "venc", "vcbus", "bt656",
- "dvin", "rdma", "venci", "vencp",
- "vdac", "vdi6", "vencl", "vid_lock";
- clocks = <&clkc CLKID_VPU>,
- <&clkc CLKID_VAPB>;
- clock-names = "vpu", "vapb";
- /*
- * VPU clocking is provided by two identical clock paths
- * VPU_0 and VPU_1 muxed to a single clock by a glitch
- * free mux to safely change frequency while running.
- * Same for VAPB but with a final gate after the glitch free mux.
- */
- assigned-clocks = <&clkc CLKID_VPU_0_SEL>,
- <&clkc CLKID_VPU_0>,
- <&clkc CLKID_VPU>, /* Glitch free mux */
- <&clkc CLKID_VAPB_0_SEL>,
- <&clkc CLKID_VAPB_0>,
- <&clkc CLKID_VAPB_SEL>; /* Glitch free mux */
- assigned-clock-parents = <&clkc CLKID_FCLK_DIV3>,
- <0>, /* Do Nothing */
- <&clkc CLKID_VPU_0>,
- <&clkc CLKID_FCLK_DIV4>,
- <0>, /* Do Nothing */
- <&clkc CLKID_VAPB_0>;
- assigned-clock-rates = <0>, /* Do Nothing */
- <666666666>,
- <0>, /* Do Nothing */
- <0>, /* Do Nothing */
- <250000000>,
- <0>; /* Do Nothing */
-};
-
-&saradc {
- compatible = "amlogic,meson-gxl-saradc", "amlogic,meson-saradc";
- clocks = <&xtal>,
- <&clkc CLKID_SAR_ADC>,
- <&clkc CLKID_SAR_ADC_CLK>,
- <&clkc CLKID_SAR_ADC_SEL>;
- clock-names = "clkin", "core", "adc_clk", "adc_sel";
-};
-
-&sd_emmc_a {
- clocks = <&clkc CLKID_SD_EMMC_A>,
- <&clkc CLKID_SD_EMMC_A_CLK0>,
- <&clkc CLKID_FCLK_DIV2>;
- clock-names = "core", "clkin0", "clkin1";
- resets = <&reset RESET_SD_EMMC_A>;
-};
-
-&sd_emmc_b {
- clocks = <&clkc CLKID_SD_EMMC_B>,
- <&clkc CLKID_SD_EMMC_B_CLK0>,
- <&clkc CLKID_FCLK_DIV2>;
- clock-names = "core", "clkin0", "clkin1";
- resets = <&reset RESET_SD_EMMC_B>;
-};
-
-&sd_emmc_c {
- clocks = <&clkc CLKID_SD_EMMC_C>,
- <&clkc CLKID_SD_EMMC_C_CLK0>,
- <&clkc CLKID_FCLK_DIV2>;
- clock-names = "core", "clkin0", "clkin1";
- resets = <&reset RESET_SD_EMMC_C>;
-};
-
-&simplefb_hdmi {
- clocks = <&clkc CLKID_HDMI_PCLK>,
- <&clkc CLKID_CLK81>,
- <&clkc CLKID_GCLK_VENCI_INT0>;
-};
-
-&spicc {
- clocks = <&clkc CLKID_SPICC>;
- clock-names = "core";
- resets = <&reset RESET_PERIPHS_SPICC>;
- num-cs = <1>;
-};
-
-&spifc {
- clocks = <&clkc CLKID_SPI>;
-};
-
-&uart_A {
- clocks = <&xtal>, <&clkc CLKID_UART0>, <&xtal>;
- clock-names = "xtal", "pclk", "baud";
-};
-
-&uart_AO {
- clocks = <&xtal>, <&clkc_AO CLKID_AO_UART1>, <&xtal>;
- clock-names = "xtal", "pclk", "baud";
-};
-
-&uart_AO_B {
- clocks = <&xtal>, <&clkc_AO CLKID_AO_UART2>, <&xtal>;
- clock-names = "xtal", "pclk", "baud";
-};
-
-&uart_B {
- clocks = <&xtal>, <&clkc CLKID_UART1>, <&xtal>;
- clock-names = "xtal", "pclk", "baud";
-};
-
-&uart_C {
- clocks = <&xtal>, <&clkc CLKID_UART2>, <&xtal>;
- clock-names = "xtal", "pclk", "baud";
-};
-
-&vpu {
- compatible = "amlogic,meson-gxl-vpu", "amlogic,meson-gx-vpu";
- power-domains = <&pwrc PWRC_GXBB_VPU_ID>;
-};
-
-&vdec {
- compatible = "amlogic,gxl-vdec", "amlogic,gx-vdec";
- clocks = <&clkc CLKID_DOS_PARSER>,
- <&clkc CLKID_DOS>,
- <&clkc CLKID_VDEC_1>,
- <&clkc CLKID_VDEC_HEVC>;
- clock-names = "dos_parser", "dos", "vdec_1", "vdec_hevc";
- resets = <&reset RESET_PARSER>;
- reset-names = "esparser";
-};
diff --git a/arch/arm/dts/meson-gxm-gt1-ultimate.dts b/arch/arm/dts/meson-gxm-gt1-ultimate.dts
deleted file mode 100644
index 2c26788..0000000
--- a/arch/arm/dts/meson-gxm-gt1-ultimate.dts
+++ /dev/null
@@ -1,91 +0,0 @@
-// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
-/*
- * Copyright (c) Christian Hewitt <christianshewitt@gmail.com>
- */
-
-/dts-v1/;
-
-#include "meson-gxm.dtsi"
-#include "meson-gx-p23x-q20x.dtsi"
-#include <dt-bindings/input/input.h>
-#include <dt-bindings/leds/common.h>
-
-/ {
- compatible = "azw,gt1-ultimate", "amlogic,s912", "amlogic,meson-gxm";
- model = "Beelink GT1 Ultimate";
-
- leds {
- compatible = "gpio-leds";
-
- led-white {
- color = <LED_COLOR_ID_WHITE>;
- function = LED_FUNCTION_POWER;
- gpios = <&gpio_ao GPIOAO_9 GPIO_ACTIVE_HIGH>;
- default-state = "on";
- panic-indicator;
- };
- };
-
- adc-keys {
- compatible = "adc-keys";
- io-channels = <&saradc 0>;
- io-channel-names = "buttons";
- keyup-threshold-microvolt = <1710000>;
-
- button-function {
- label = "update";
- linux,code = <KEY_VENDOR>;
- press-threshold-microvolt = <10000>;
- };
- };
-};
-
-ðmac {
- pinctrl-0 = <ð_pins>;
- pinctrl-names = "default";
- phy-handle = <&external_phy>;
- amlogic,tx-delay-ns = <2>;
- phy-mode = "rgmii";
-};
-
-&external_mdio {
- external_phy: ethernet-phy@0 {
- /* Realtek RTL8211F (0x001cc916) */
- reg = <0>;
- max-speed = <1000>;
-
- reset-assert-us = <10000>;
- reset-deassert-us = <80000>;
- reset-gpios = <&gpio GPIOZ_14 GPIO_ACTIVE_LOW>;
-
- interrupt-parent = <&gpio_intc>;
- /* MAC_INTR on GPIOZ_15 */
- interrupts = <25 IRQ_TYPE_LEVEL_LOW>;
- };
-};
-
-&ir {
- linux,rc-map-name = "rc-beelink-gs1";
-};
-
-&sd_emmc_a {
- brcmf: wifi@1 {
- reg = <1>;
- compatible = "brcm,bcm4329-fmac";
- };
-};
-
-&uart_A {
- status = "okay";
- pinctrl-0 = <&uart_a_pins>, <&uart_a_cts_rts_pins>;
- pinctrl-names = "default";
- uart-has-rtscts;
-
- bluetooth {
- compatible = "brcm,bcm43438-bt";
- shutdown-gpios = <&gpio GPIOX_17 GPIO_ACTIVE_HIGH>;
- max-speed = <2000000>;
- clocks = <&wifi32k>;
- clock-names = "lpo";
- };
-};
diff --git a/arch/arm/dts/meson-gxm-khadas-vim2.dts b/arch/arm/dts/meson-gxm-khadas-vim2.dts
deleted file mode 100644
index 74897a1..0000000
--- a/arch/arm/dts/meson-gxm-khadas-vim2.dts
+++ /dev/null
@@ -1,424 +0,0 @@
-// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
-/*
- * Copyright (c) 2017 Martin Blumenstingl <martin.blumenstingl@googlemail.com>.
- * Copyright (c) 2017 BayLibre, SAS
- * Author: Neil Armstrong <narmstrong@baylibre.com>
- */
-
-/dts-v1/;
-
-#include "meson-gxm.dtsi"
-#include <dt-bindings/input/input.h>
-#include <dt-bindings/sound/meson-aiu.h>
-
-/ {
- compatible = "khadas,vim2", "amlogic,s912", "amlogic,meson-gxm";
- model = "Khadas VIM2";
-
- aliases {
- serial0 = &uart_AO;
- serial2 = &uart_AO_B;
- };
-
- chosen {
- stdout-path = "serial0:115200n8";
- };
-
- memory@0 {
- device_type = "memory";
- reg = <0x0 0x0 0x0 0x80000000>;
- };
-
- adc-keys {
- compatible = "adc-keys";
- io-channels = <&saradc 0>;
- io-channel-names = "buttons";
- keyup-threshold-microvolt = <1710000>;
-
- button-function {
- label = "Function";
- linux,code = <KEY_FN>;
- press-threshold-microvolt = <10000>;
- };
- };
-
- emmc_pwrseq: emmc-pwrseq {
- compatible = "mmc-pwrseq-emmc";
- reset-gpios = <&gpio BOOT_9 GPIO_ACTIVE_LOW>;
- };
-
- gpio_fan: gpio-fan {
- compatible = "gpio-fan";
- gpios = <&gpio GPIODV_14 GPIO_ACTIVE_HIGH
- &gpio GPIODV_15 GPIO_ACTIVE_HIGH>;
- /* Dummy RPM values since fan is optional */
- gpio-fan,speed-map =
- <0 0>,
- <1 1>,
- <2 2>,
- <3 3>;
- #cooling-cells = <2>;
- };
-
- gpio-keys-polled {
- compatible = "gpio-keys-polled";
- poll-interval = <100>;
-
- power-button {
- label = "power";
- linux,code = <KEY_POWER>;
- gpios = <&gpio_ao GPIOAO_2 GPIO_ACTIVE_LOW>;
- };
- };
-
- hdmi-connector {
- compatible = "hdmi-connector";
- type = "a";
-
- port {
- hdmi_connector_in: endpoint {
- remote-endpoint = <&hdmi_tx_tmds_out>;
- };
- };
- };
-
- led-controller {
- compatible = "pwm-leds";
-
- led-1 {
- label = "vim:red:power";
- pwms = <&pwm_AO_ab 1 7812500 0>;
- max-brightness = <255>;
- linux,default-trigger = "default-on";
- };
- };
-
- sdio_pwrseq: sdio-pwrseq {
- compatible = "mmc-pwrseq-simple";
- reset-gpios = <&gpio GPIOX_6 GPIO_ACTIVE_LOW>;
- clocks = <&wifi32k>;
- clock-names = "ext_clock";
- };
-
- hdmi_5v: regulator-hdmi-5v {
- compatible = "regulator-fixed";
-
- regulator-name = "HDMI_5V";
- regulator-min-microvolt = <5000000>;
- regulator-max-microvolt = <5000000>;
-
- gpio = <&gpio GPIOH_3 GPIO_ACTIVE_HIGH>;
- enable-active-high;
- regulator-always-on;
- };
-
- vcc_3v3: regulator-vcc_3v3 {
- compatible = "regulator-fixed";
- regulator-name = "VCC_3V3";
- regulator-min-microvolt = <3300000>;
- regulator-max-microvolt = <3300000>;
- };
-
- vddio_ao18: regulator-vddio_ao18 {
- compatible = "regulator-fixed";
- regulator-name = "VDDIO_AO18";
- regulator-min-microvolt = <1800000>;
- regulator-max-microvolt = <1800000>;
- };
-
- vddio_boot: regulator-vddio_boot {
- compatible = "regulator-fixed";
- regulator-name = "VDDIO_BOOT";
- regulator-min-microvolt = <1800000>;
- regulator-max-microvolt = <1800000>;
- };
-
- vddao_3v3: regulator-vddao_3v3 {
- compatible = "regulator-fixed";
- regulator-name = "VDDAO_3V3";
- regulator-min-microvolt = <3300000>;
- regulator-max-microvolt = <3300000>;
- };
-
- wifi32k: wifi32k {
- compatible = "pwm-clock";
- #clock-cells = <0>;
- clock-frequency = <32768>;
- pwms = <&pwm_ef 0 30518 0>; /* PWM_E at 32.768KHz */
- };
-
- sound {
- compatible = "amlogic,gx-sound-card";
- model = "KHADAS-VIM2";
- assigned-clocks = <&clkc CLKID_MPLL0>,
- <&clkc CLKID_MPLL1>,
- <&clkc CLKID_MPLL2>;
- assigned-clock-parents = <0>, <0>, <0>;
- assigned-clock-rates = <294912000>,
- <270950400>,
- <393216000>;
- status = "okay";
-
- dai-link-0 {
- sound-dai = <&aiu AIU_CPU CPU_I2S_FIFO>;
- };
-
- dai-link-1 {
- sound-dai = <&aiu AIU_CPU CPU_I2S_ENCODER>;
- dai-format = "i2s";
- mclk-fs = <256>;
-
- codec-0 {
- sound-dai = <&aiu AIU_HDMI CTRL_I2S>;
- };
- };
-
- dai-link-2 {
- sound-dai = <&aiu AIU_HDMI CTRL_OUT>;
-
- codec-0 {
- sound-dai = <&hdmi_tx>;
- };
- };
- };
-};
-
-&aiu {
- status = "okay";
-};
-
-&cec_AO {
- status = "okay";
- pinctrl-0 = <&ao_cec_pins>;
- pinctrl-names = "default";
- hdmi-phandle = <&hdmi_tx>;
-};
-
-&cpu_cooling_maps {
- map0 {
- cooling-device = <&gpio_fan THERMAL_NO_LIMIT 1>;
- };
-
- map1 {
- cooling-device = <&gpio_fan 2 THERMAL_NO_LIMIT>,
- <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
- <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
- <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
- <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
- <&cpu4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
- <&cpu5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
- <&cpu6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
- <&cpu7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
- };
-};
-
-ðmac {
- pinctrl-0 = <ð_pins>;
- pinctrl-names = "default";
-
- /* Select external PHY by default */
- phy-handle = <&external_phy>;
-
- amlogic,tx-delay-ns = <2>;
-
- /* External PHY is in RGMII */
- phy-mode = "rgmii";
-
- status = "okay";
-};
-
-&external_mdio {
- external_phy: ethernet-phy@0 {
- /* Realtek RTL8211F (0x001cc916) */
- reg = <0>;
-
- reset-assert-us = <10000>;
- reset-deassert-us = <80000>;
- reset-gpios = <&gpio GPIOZ_14 GPIO_ACTIVE_LOW>;
-
- interrupt-parent = <&gpio_intc>;
- /* MAC_INTR on GPIOZ_15 */
- interrupts = <25 IRQ_TYPE_LEVEL_LOW>;
- };
-};
-
-&hdmi_tx {
- status = "okay";
- pinctrl-0 = <&hdmi_hpd_pins>, <&hdmi_i2c_pins>;
- pinctrl-names = "default";
- hdmi-supply = <&hdmi_5v>;
-};
-
-&hdmi_tx_tmds_port {
- hdmi_tx_tmds_out: endpoint {
- remote-endpoint = <&hdmi_connector_in>;
- };
-};
-
-&i2c_A {
- status = "okay";
- pinctrl-0 = <&i2c_a_pins>;
- pinctrl-names = "default";
-};
-
-&i2c_B {
- status = "okay";
- pinctrl-0 = <&i2c_b_pins>;
- pinctrl-names = "default";
-
- rtc: rtc@51 {
- status = "okay";
- compatible = "haoyu,hym8563";
- reg = <0x51>;
- #clock-cells = <0>;
- clock-output-names = "xin32k";
- };
-};
-
-&ir {
- status = "okay";
- pinctrl-0 = <&remote_input_ao_pins>;
- pinctrl-names = "default";
- linux,rc-map-name = "rc-khadas";
-};
-
-&pwm_AO_ab {
- status = "okay";
- pinctrl-0 = <&pwm_ao_a_3_pins>, <&pwm_ao_b_pins>;
- pinctrl-names = "default";
- clocks = <&clkc CLKID_FCLK_DIV4>;
- clock-names = "clkin0";
-};
-
-&pwm_ef {
- status = "okay";
- pinctrl-0 = <&pwm_e_pins>, <&pwm_f_clk_pins>;
- pinctrl-names = "default";
- clocks = <&clkc CLKID_FCLK_DIV4>;
- clock-names = "clkin0";
-};
-
-&sd_emmc_a {
- status = "okay";
- pinctrl-0 = <&sdio_pins>;
- pinctrl-1 = <&sdio_clk_gate_pins>;
- pinctrl-names = "default", "clk-gate";
- #address-cells = <1>;
- #size-cells = <0>;
-
- bus-width = <4>;
- cap-sd-highspeed;
- max-frequency = <100000000>;
-
- non-removable;
- disable-wp;
-
- /* WiFi firmware requires power to be kept while in suspend */
- keep-power-in-suspend;
-
- mmc-pwrseq = <&sdio_pwrseq>;
-
- vmmc-supply = <&vddao_3v3>;
- vqmmc-supply = <&vddio_boot>;
-
- brcmf: wifi@1 {
- reg = <1>;
- compatible = "brcm,bcm4329-fmac";
- };
-};
-
-/* SD card */
-&sd_emmc_b {
- status = "okay";
- pinctrl-0 = <&sdcard_pins>;
- pinctrl-1 = <&sdcard_clk_gate_pins>;
- pinctrl-names = "default", "clk-gate";
-
- bus-width = <4>;
- cap-sd-highspeed;
- max-frequency = <50000000>;
- disable-wp;
-
- cd-gpios = <&gpio CARD_6 GPIO_ACTIVE_LOW>;
-
- vmmc-supply = <&vddao_3v3>;
- vqmmc-supply = <&vddio_boot>;
-};
-
-/* eMMC */
-&sd_emmc_c {
- status = "okay";
- pinctrl-0 = <&emmc_pins>, <&emmc_ds_pins>;
- pinctrl-1 = <&emmc_clk_gate_pins>;
- pinctrl-names = "default", "clk-gate";
-
- bus-width = <8>;
- cap-mmc-highspeed;
- max-frequency = <200000000>;
- non-removable;
- disable-wp;
- mmc-ddr-1_8v;
- mmc-hs200-1_8v;
-
- mmc-pwrseq = <&emmc_pwrseq>;
- vmmc-supply = <&vcc_3v3>;
- vqmmc-supply = <&vddio_boot>;
-};
-
-/*
- * EMMC_DS pin is shared between SPI NOR CS and eMMC Data Strobe
- * Remove emmc_ds_pins from sd_emmc_c pinctrl-0 then spifc can be enabled
- */
-&spifc {
- status = "disabled";
- pinctrl-0 = <&nor_pins>;
- pinctrl-names = "default";
-
- w25q32: flash@0 {
- #address-cells = <1>;
- #size-cells = <1>;
- compatible = "winbond,w25q16", "jedec,spi-nor";
- reg = <0>;
- spi-max-frequency = <104000000>;
- };
-};
-
-/* This one is connected to the Bluetooth module */
-&uart_A {
- status = "okay";
- pinctrl-0 = <&uart_a_pins>, <&uart_a_cts_rts_pins>;
- pinctrl-names = "default";
- uart-has-rtscts;
-
- bluetooth {
- compatible = "brcm,bcm43438-bt";
- shutdown-gpios = <&gpio GPIOX_17 GPIO_ACTIVE_HIGH>;
- max-speed = <2000000>;
- clocks = <&wifi32k>;
- clock-names = "lpo";
- };
-};
-
-/* This is brought out on the Linux_RX (18) and Linux_TX (19) pins: */
-&uart_AO {
- status = "okay";
- pinctrl-0 = <&uart_ao_a_pins>;
- pinctrl-names = "default";
-};
-
-/* This is brought out on the UART_RX_AO_B (15) and UART_TX_AO_B (16) pins: */
-&uart_AO_B {
- status = "okay";
- pinctrl-0 = <&uart_ao_b_pins>;
- pinctrl-names = "default";
-};
-
-&saradc {
- status = "okay";
- vref-supply = <&vddio_ao18>;
-};
-
-&usb {
- status = "okay";
- dr_mode = "peripheral";
-};
diff --git a/arch/arm/dts/meson-gxm-s912-libretech-pc.dts b/arch/arm/dts/meson-gxm-s912-libretech-pc.dts
deleted file mode 100644
index 444c249..0000000
--- a/arch/arm/dts/meson-gxm-s912-libretech-pc.dts
+++ /dev/null
@@ -1,62 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0
-/*
- * Copyright (c) 2019 BayLibre SAS. All rights reserved.
- * Author: Jerome Brunet <jbrunet@baylibre.com>
- */
-
-/dts-v1/;
-
-#include "meson-gxm.dtsi"
-#include "meson-gx-libretech-pc.dtsi"
-
-/ {
- compatible = "libretech,aml-s912-pc", "amlogic,s912",
- "amlogic,meson-gxm";
- model = "Libre Computer AML-S912-PC";
-
- typec2_vbus: regulator-typec2_vbus {
- compatible = "regulator-fixed";
- regulator-name = "TYPEC2_VBUS";
- regulator-min-microvolt = <5000000>;
- regulator-max-microvolt = <5000000>;
- vin-supply = <&vcc5v>;
-
- gpio = <&gpio GPIODV_1 GPIO_ACTIVE_HIGH>;
- enable-active-high;
- };
-};
-
-&pinctrl_periphs {
- /*
- * Make sure the irq pin of the TYPE C controller is not driven
- * by the SoC.
- */
- fusb302_irq_pins: fusb302_irq {
- mux {
- groups = "GPIODV_0";
- function = "gpio_periphs";
- bias-pull-up;
- output-disable;
- };
- };
-};
-
-&i2c_C {
- fusb302@22 {
- compatible = "fcs,fusb302";
- reg = <0x22>;
-
- pinctrl-0 = <&fusb302_irq_pins>;
- pinctrl-names = "default";
- interrupt-parent = <&gpio_intc>;
- interrupts = <59 IRQ_TYPE_LEVEL_LOW>;
-
- vbus-supply = <&typec2_vbus>;
-
- status = "okay";
- };
-};
-
-&usb2_phy2 {
- phy-supply = <&typec2_vbus>;
-};
diff --git a/arch/arm/dts/meson-gxm-wetek-core2.dts b/arch/arm/dts/meson-gxm-wetek-core2.dts
deleted file mode 100644
index f8c4034..0000000
--- a/arch/arm/dts/meson-gxm-wetek-core2.dts
+++ /dev/null
@@ -1,85 +0,0 @@
-// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
-/*
- * Copyright (c) 2020 Christian Hewitt <christianshewitt@gmail.com>
- */
-
-/dts-v1/;
-
-#include "meson-gxm.dtsi"
-#include "meson-gx-p23x-q20x.dtsi"
-#include <dt-bindings/input/input.h>
-#include <dt-bindings/leds/common.h>
-
-/ {
- compatible = "wetek,core2", "amlogic,s912", "amlogic,meson-gxm";
- model = "WeTek Core 2";
-
- memory@0 {
- device_type = "memory";
- reg = <0x0 0x0 0x0 0x80000000>; /* 2 GiB or 3 GiB */
- };
-
- leds {
- compatible = "gpio-leds";
-
- led-blue {
- color = <LED_COLOR_ID_BLUE>;
- function = LED_FUNCTION_STATUS;
- gpios = <&gpio GPIODV_24 GPIO_ACTIVE_HIGH>;
- default-state = "on";
- };
- };
-
- adc-keys {
- compatible = "adc-keys";
- io-channels = <&saradc 0>;
- io-channel-names = "buttons";
- keyup-threshold-microvolt = <1710000>;
-
- button-update {
- label = "update";
- linux,code = <KEY_VENDOR>;
- press-threshold-microvolt = <10000>;
- };
- };
-
- gpio-keys-polled {
- compatible = "gpio-keys-polled";
- poll-interval = <100>;
-
- button-power {
- label = "power";
- linux,code = <KEY_POWER>;
- gpios = <&gpio_ao GPIOAO_2 GPIO_ACTIVE_LOW>;
- };
- };
-};
-
-/* Disabled as Realtek RTL8152 USB provides Ethernet */
-ðmac {
- status = "disabled";
-};
-
-&internal_phy {
- status = "disabled";
-};
-
-&ir {
- linux,rc-map-name = "rc-wetek-play2";
-};
-
-/* This is connected to the Bluetooth module: */
-&uart_A {
- status = "okay";
- pinctrl-0 = <&uart_a_pins>, <&uart_a_cts_rts_pins>;
- pinctrl-names = "default";
- uart-has-rtscts;
-
- bluetooth {
- compatible = "brcm,bcm43438-bt";
- shutdown-gpios = <&gpio GPIOX_17 GPIO_ACTIVE_HIGH>;
- max-speed = <2000000>;
- clocks = <&wifi32k>;
- clock-names = "lpo";
- };
-};
diff --git a/arch/arm/dts/meson-gxm.dtsi b/arch/arm/dts/meson-gxm.dtsi
deleted file mode 100644
index 411cc31..0000000
--- a/arch/arm/dts/meson-gxm.dtsi
+++ /dev/null
@@ -1,216 +0,0 @@
-// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
-/*
- * Copyright (c) 2016 Endless Computers, Inc.
- * Author: Carlo Caione <carlo@endlessm.com>
- */
-
-#include "meson-gxl.dtsi"
-
-/ {
- compatible = "amlogic,meson-gxm";
-
- cpus {
- cpu-map {
- cluster0 {
- core0 {
- cpu = <&cpu0>;
- };
- core1 {
- cpu = <&cpu1>;
- };
- core2 {
- cpu = <&cpu2>;
- };
- core3 {
- cpu = <&cpu3>;
- };
- };
-
- cluster1 {
- core0 {
- cpu = <&cpu4>;
- };
- core1 {
- cpu = <&cpu5>;
- };
- core2 {
- cpu = <&cpu6>;
- };
- core3 {
- cpu = <&cpu7>;
- };
- };
- };
-
- cpu0: cpu@0 {
- capacity-dmips-mhz = <1024>;
- };
-
- cpu1: cpu@1 {
- capacity-dmips-mhz = <1024>;
- };
-
- cpu2: cpu@2 {
- capacity-dmips-mhz = <1024>;
- };
-
- cpu3: cpu@3 {
- capacity-dmips-mhz = <1024>;
- };
-
- cpu4: cpu@100 {
- device_type = "cpu";
- compatible = "arm,cortex-a53";
- reg = <0x0 0x100>;
- enable-method = "psci";
- capacity-dmips-mhz = <1024>;
- next-level-cache = <&l2>;
- clocks = <&scpi_dvfs 1>;
- #cooling-cells = <2>;
- };
-
- cpu5: cpu@101 {
- device_type = "cpu";
- compatible = "arm,cortex-a53";
- reg = <0x0 0x101>;
- enable-method = "psci";
- capacity-dmips-mhz = <1024>;
- next-level-cache = <&l2>;
- clocks = <&scpi_dvfs 1>;
- #cooling-cells = <2>;
- };
-
- cpu6: cpu@102 {
- device_type = "cpu";
- compatible = "arm,cortex-a53";
- reg = <0x0 0x102>;
- enable-method = "psci";
- capacity-dmips-mhz = <1024>;
- next-level-cache = <&l2>;
- clocks = <&scpi_dvfs 1>;
- #cooling-cells = <2>;
- };
-
- cpu7: cpu@103 {
- device_type = "cpu";
- compatible = "arm,cortex-a53";
- reg = <0x0 0x103>;
- enable-method = "psci";
- capacity-dmips-mhz = <1024>;
- next-level-cache = <&l2>;
- clocks = <&scpi_dvfs 1>;
- #cooling-cells = <2>;
- };
- };
-
- gpu_opp_table: opp-table {
- compatible = "operating-points-v2";
-
- opp-125000000 {
- opp-hz = /bits/ 64 <125000000>;
- opp-microvolt = <950000>;
- };
- opp-250000000 {
- opp-hz = /bits/ 64 <250000000>;
- opp-microvolt = <950000>;
- };
- opp-285714285 {
- opp-hz = /bits/ 64 <285714285>;
- opp-microvolt = <950000>;
- };
- opp-400000000 {
- opp-hz = /bits/ 64 <400000000>;
- opp-microvolt = <950000>;
- };
- opp-500000000 {
- opp-hz = /bits/ 64 <500000000>;
- opp-microvolt = <950000>;
- };
- opp-666666666 {
- opp-hz = /bits/ 64 <666666666>;
- opp-microvolt = <950000>;
- };
- };
-};
-
-&apb {
- usb2_phy2: phy@78040 {
- compatible = "amlogic,meson-gxl-usb2-phy";
- #phy-cells = <0>;
- reg = <0x0 0x78040 0x0 0x20>;
- clocks = <&clkc CLKID_USB>;
- clock-names = "phy";
- resets = <&reset RESET_USB_OTG>;
- reset-names = "phy";
- status = "okay";
- };
-
- mali: gpu@c0000 {
- compatible = "amlogic,meson-gxm-mali", "arm,mali-t820";
- reg = <0x0 0xc0000 0x0 0x40000>;
- interrupt-parent = <&gic>;
- interrupts = <GIC_SPI 162 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 161 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 160 IRQ_TYPE_LEVEL_HIGH>;
- interrupt-names = "job", "mmu", "gpu";
- clocks = <&clkc CLKID_MALI>;
- resets = <&reset RESET_MALI_CAPB3>, <&reset RESET_MALI>;
- operating-points-v2 = <&gpu_opp_table>;
- };
-};
-
-&clkc_AO {
- compatible = "amlogic,meson-gxm-aoclkc", "amlogic,meson-gx-aoclkc";
-};
-
-&cpu_cooling_maps {
- map0 {
- cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
- <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
- <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
- <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
- <&cpu4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
- <&cpu5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
- <&cpu6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
- <&cpu7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
- };
-
- map1 {
- cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
- <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
- <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
- <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
- <&cpu4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
- <&cpu5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
- <&cpu6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
- <&cpu7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
- };
-};
-
-&saradc {
- compatible = "amlogic,meson-gxm-saradc", "amlogic,meson-saradc";
-};
-
-&scpi_dvfs {
- clock-indices = <0 1>;
- clock-output-names = "vbig", "vlittle";
-};
-
-&vpu {
- compatible = "amlogic,meson-gxm-vpu", "amlogic,meson-gx-vpu";
-};
-
-&hdmi_tx {
- compatible = "amlogic,meson-gxm-dw-hdmi", "amlogic,meson-gx-dw-hdmi";
-};
-
-&usb {
- compatible = "amlogic,meson-gxm-usb-ctrl";
-
- phy-names = "usb2-phy0", "usb2-phy1", "usb2-phy2";
- phys = <&usb2_phy0>, <&usb2_phy1>, <&usb2_phy2>;
-};
-
-&vdec {
- compatible = "amlogic,gxm-vdec", "amlogic,gx-vdec";
-};
diff --git a/arch/arm/dts/meson-khadas-vim3.dtsi b/arch/arm/dts/meson-khadas-vim3.dtsi
deleted file mode 100644
index 3cf4ecb..0000000
--- a/arch/arm/dts/meson-khadas-vim3.dtsi
+++ /dev/null
@@ -1,534 +0,0 @@
-// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
-/*
- * Copyright (c) 2019 BayLibre, SAS
- * Author: Neil Armstrong <narmstrong@baylibre.com>
- * Copyright (c) 2019 Christian Hewitt <christianshewitt@gmail.com>
- */
-
-#include <dt-bindings/input/input.h>
-#include <dt-bindings/leds/common.h>
-#include <dt-bindings/gpio/meson-g12a-gpio.h>
-#include <dt-bindings/sound/meson-g12a-tohdmitx.h>
-
-/ {
- aliases {
- serial0 = &uart_AO;
- ethernet0 = ðmac;
- rtc0 = &rtc;
- rtc1 = &vrtc;
- };
-
- chosen {
- stdout-path = "serial0:115200n8";
- };
-
- memory@0 {
- device_type = "memory";
- reg = <0x0 0x0 0x0 0x80000000>;
- };
-
- adc-keys {
- compatible = "adc-keys";
- io-channels = <&saradc 2>;
- io-channel-names = "buttons";
- keyup-threshold-microvolt = <1710000>;
-
- button-function {
- label = "Function";
- linux,code = <KEY_FN>;
- press-threshold-microvolt = <10000>;
- };
- };
-
- leds {
- compatible = "gpio-leds";
-
- led-white {
- color = <LED_COLOR_ID_WHITE>;
- function = LED_FUNCTION_STATUS;
- gpios = <&gpio_ao GPIOAO_4 GPIO_ACTIVE_HIGH>;
- linux,default-trigger = "heartbeat";
- };
-
- led-red {
- color = <LED_COLOR_ID_RED>;
- function = LED_FUNCTION_STATUS;
- gpios = <&gpio_expander 5 GPIO_ACTIVE_HIGH>;
- };
- };
-
- emmc_pwrseq: emmc-pwrseq {
- compatible = "mmc-pwrseq-emmc";
- reset-gpios = <&gpio BOOT_12 GPIO_ACTIVE_LOW>;
- };
-
- gpio-keys-polled {
- compatible = "gpio-keys-polled";
- poll-interval = <100>;
-
- power-button {
- label = "power";
- linux,code = <KEY_POWER>;
- gpios = <&gpio_ao GPIOAO_7 GPIO_ACTIVE_LOW>;
- };
- };
-
- sdio_pwrseq: sdio-pwrseq {
- compatible = "mmc-pwrseq-simple";
- reset-gpios = <&gpio GPIOX_6 GPIO_ACTIVE_LOW>;
- clocks = <&wifi32k>;
- clock-names = "ext_clock";
- };
-
- dc_in: regulator-dc_in {
- compatible = "regulator-fixed";
- regulator-name = "DC_IN";
- regulator-min-microvolt = <5000000>;
- regulator-max-microvolt = <5000000>;
- regulator-always-on;
- };
-
- vcc_5v: regulator-vcc_5v {
- compatible = "regulator-fixed";
- regulator-name = "VCC_5V";
- regulator-min-microvolt = <5000000>;
- regulator-max-microvolt = <5000000>;
- vin-supply = <&dc_in>;
-
- gpio = <&gpio GPIOH_8 GPIO_OPEN_DRAIN>;
- enable-active-high;
- };
-
- vcc_1v8: regulator-vcc_1v8 {
- compatible = "regulator-fixed";
- regulator-name = "VCC_1V8";
- regulator-min-microvolt = <1800000>;
- regulator-max-microvolt = <1800000>;
- vin-supply = <&vcc_3v3>;
- regulator-always-on;
- };
-
- vcc_3v3: regulator-vcc_3v3 {
- compatible = "regulator-fixed";
- regulator-name = "VCC_3V3";
- regulator-min-microvolt = <3300000>;
- regulator-max-microvolt = <3300000>;
- vin-supply = <&vsys_3v3>;
- regulator-always-on;
- /* FIXME: actually controlled by VDDCPU_B_EN */
- };
-
- vddao_1v8: regulator-vddao_1v8 {
- compatible = "regulator-fixed";
- regulator-name = "VDDIO_AO1V8";
- regulator-min-microvolt = <1800000>;
- regulator-max-microvolt = <1800000>;
- vin-supply = <&vsys_3v3>;
- regulator-always-on;
- };
-
- emmc_1v8: regulator-emmc_1v8 {
- compatible = "regulator-fixed";
- regulator-name = "EMMC_AO1V8";
- regulator-min-microvolt = <1800000>;
- regulator-max-microvolt = <1800000>;
- vin-supply = <&vcc_3v3>;
- regulator-always-on;
- };
-
- vsys_3v3: regulator-vsys_3v3 {
- compatible = "regulator-fixed";
- regulator-name = "VSYS_3V3";
- regulator-min-microvolt = <3300000>;
- regulator-max-microvolt = <3300000>;
- vin-supply = <&dc_in>;
- regulator-always-on;
- };
-
- usb_pwr: regulator-usb_pwr {
- compatible = "regulator-fixed";
- regulator-name = "USB_PWR";
- regulator-min-microvolt = <5000000>;
- regulator-max-microvolt = <5000000>;
- vin-supply = <&vcc_5v>;
-
- gpio = <&gpio GPIOA_6 GPIO_ACTIVE_HIGH>;
- enable-active-high;
- };
-
- hdmi-connector {
- compatible = "hdmi-connector";
- type = "a";
-
- port {
- hdmi_connector_in: endpoint {
- remote-endpoint = <&hdmi_tx_tmds_out>;
- };
- };
- };
-
-
- sound {
- compatible = "amlogic,axg-sound-card";
- model = "KHADAS-VIM3";
- audio-aux-devs = <&tdmin_a>, <&tdmout_a>;
- audio-routing = "TDMOUT_A IN 0", "FRDDR_A OUT 0",
- "TDMOUT_A IN 1", "FRDDR_B OUT 0",
- "TDMOUT_A IN 2", "FRDDR_C OUT 0",
- "TDM_A Playback", "TDMOUT_A OUT",
- "TDMIN_A IN 0", "TDM_A Capture",
- "TDMIN_A IN 3", "TDM_A Loopback",
- "TODDR_A IN 0", "TDMIN_A OUT",
- "TODDR_B IN 0", "TDMIN_A OUT",
- "TODDR_C IN 0", "TDMIN_A OUT";
-
- assigned-clocks = <&clkc CLKID_MPLL2>,
- <&clkc CLKID_MPLL0>,
- <&clkc CLKID_MPLL1>;
- assigned-clock-parents = <0>, <0>, <0>;
- assigned-clock-rates = <294912000>,
- <270950400>,
- <393216000>;
- status = "okay";
-
- dai-link-0 {
- sound-dai = <&frddr_a>;
- };
-
- dai-link-1 {
- sound-dai = <&frddr_b>;
- };
-
- dai-link-2 {
- sound-dai = <&frddr_c>;
- };
-
- dai-link-3 {
- sound-dai = <&toddr_a>;
- };
-
- dai-link-4 {
- sound-dai = <&toddr_b>;
- };
-
- dai-link-5 {
- sound-dai = <&toddr_c>;
- };
-
- /* 8ch hdmi interface */
- dai-link-6 {
- sound-dai = <&tdmif_a>;
- dai-format = "i2s";
- dai-tdm-slot-tx-mask-0 = <1 1>;
- dai-tdm-slot-tx-mask-1 = <1 1>;
- dai-tdm-slot-tx-mask-2 = <1 1>;
- dai-tdm-slot-tx-mask-3 = <1 1>;
- mclk-fs = <256>;
-
- codec {
- sound-dai = <&tohdmitx TOHDMITX_I2S_IN_A>;
- };
- };
-
- /* hdmi glue */
- dai-link-7 {
- sound-dai = <&tohdmitx TOHDMITX_I2S_OUT>;
-
- codec {
- sound-dai = <&hdmi_tx>;
- };
- };
- };
-
- wifi32k: wifi32k {
- compatible = "pwm-clock";
- #clock-cells = <0>;
- clock-frequency = <32768>;
- pwms = <&pwm_ef 0 30518 0>; /* PWM_E at 32.768KHz */
- };
-};
-
-&arb {
- status = "okay";
-};
-
-&clkc_audio {
- status = "okay";
-};
-
-&cec_AO {
- pinctrl-0 = <&cec_ao_a_h_pins>;
- pinctrl-names = "default";
- status = "disabled";
- hdmi-phandle = <&hdmi_tx>;
-};
-
-&cecb_AO {
- pinctrl-0 = <&cec_ao_b_h_pins>;
- pinctrl-names = "default";
- status = "okay";
- hdmi-phandle = <&hdmi_tx>;
-};
-
-&cpu_thermal {
- trips {
- cpu_active: cpu-active {
- temperature = <80000>; /* millicelsius */
- hysteresis = <2000>; /* millicelsius */
- type = "active";
- };
- };
-
- cooling-maps {
- map {
- trip = <&cpu_active>;
- cooling-device = <&khadas_mcu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
- };
- };
-};
-
-&ext_mdio {
- external_phy: ethernet-phy@0 {
- /* Realtek RTL8211F (0x001cc916) */
- reg = <0>;
- max-speed = <1000>;
-
- interrupt-parent = <&gpio_intc>;
- /* MAC_INTR on GPIOZ_14 */
- interrupts = <26 IRQ_TYPE_LEVEL_LOW>;
- };
-};
-
-ðmac {
- pinctrl-0 = <ð_pins>, <ð_rgmii_pins>;
- pinctrl-names = "default";
- status = "okay";
- phy-mode = "rgmii";
- phy-handle = <&external_phy>;
- amlogic,tx-delay-ns = <2>;
-};
-
-&frddr_a {
- status = "okay";
-};
-
-&frddr_b {
- status = "okay";
-};
-
-&frddr_c {
- status = "okay";
-};
-
-&hdmi_tx {
- status = "okay";
- pinctrl-0 = <&hdmitx_hpd_pins>, <&hdmitx_ddc_pins>;
- pinctrl-names = "default";
- hdmi-supply = <&vcc_5v>;
-};
-
-&hdmi_tx_tmds_port {
- hdmi_tx_tmds_out: endpoint {
- remote-endpoint = <&hdmi_connector_in>;
- };
-};
-
-&i2c_AO {
- status = "okay";
- pinctrl-0 = <&i2c_ao_sck_pins>, <&i2c_ao_sda_pins>;
- pinctrl-names = "default";
-
- khadas_mcu: system-controller@18 {
- compatible = "khadas,mcu";
- reg = <0x18>;
- #cooling-cells = <2>;
- };
-
- gpio_expander: gpio-controller@20 {
- compatible = "ti,tca6408";
- reg = <0x20>;
- vcc-supply = <&vcc_3v3>;
- gpio-controller;
- #gpio-cells = <2>;
- };
-
- rtc: rtc@51 {
- compatible = "haoyu,hym8563";
- reg = <0x51>;
- #clock-cells = <0>;
- };
-};
-
-&ir {
- status = "okay";
- pinctrl-0 = <&remote_input_ao_pins>;
- pinctrl-names = "default";
- linux,rc-map-name = "rc-khadas";
-};
-
-&pcie {
- reset-gpios = <&gpio GPIOA_8 GPIO_ACTIVE_LOW>;
-};
-
-&pwm_ef {
- status = "okay";
- pinctrl-0 = <&pwm_e_pins>;
- pinctrl-names = "default";
-};
-
-&saradc {
- status = "okay";
- vref-supply = <&vddao_1v8>;
-};
-
-/* SDIO */
-&sd_emmc_a {
- status = "okay";
- pinctrl-0 = <&sdio_pins>;
- pinctrl-1 = <&sdio_clk_gate_pins>;
- pinctrl-names = "default", "clk-gate";
- #address-cells = <1>;
- #size-cells = <0>;
-
- bus-width = <4>;
- cap-sd-highspeed;
- max-frequency = <100000000>;
-
- non-removable;
- disable-wp;
-
- /* WiFi firmware requires power to be kept while in suspend */
- keep-power-in-suspend;
-
- mmc-pwrseq = <&sdio_pwrseq>;
-
- vmmc-supply = <&vsys_3v3>;
- vqmmc-supply = <&vddao_1v8>;
-
- brcmf: wifi@1 {
- reg = <1>;
- compatible = "brcm,bcm4329-fmac";
- };
-};
-
-/* SD card */
-&sd_emmc_b {
- status = "okay";
- pinctrl-0 = <&sdcard_c_pins>;
- pinctrl-1 = <&sdcard_clk_gate_c_pins>;
- pinctrl-names = "default", "clk-gate";
-
- bus-width = <4>;
- cap-sd-highspeed;
- max-frequency = <50000000>;
- disable-wp;
-
- cd-gpios = <&gpio GPIOC_6 GPIO_ACTIVE_LOW>;
- vmmc-supply = <&vsys_3v3>;
- vqmmc-supply = <&vsys_3v3>;
-};
-
-/* eMMC */
-&sd_emmc_c {
- status = "okay";
- pinctrl-0 = <&emmc_ctrl_pins>, <&emmc_data_8b_pins>, <&emmc_ds_pins>;
- pinctrl-1 = <&emmc_clk_gate_pins>;
- pinctrl-names = "default", "clk-gate";
-
- bus-width = <8>;
- cap-mmc-highspeed;
- mmc-ddr-1_8v;
- mmc-hs200-1_8v;
- max-frequency = <200000000>;
- disable-wp;
-
- mmc-pwrseq = <&emmc_pwrseq>;
- vmmc-supply = <&vcc_3v3>;
- vqmmc-supply = <&emmc_1v8>;
-};
-
-/*
- * EMMC_D4, EMMC_D5, EMMC_D6 and EMMC_D7 pins are shared between SPI NOR CS
- * and eMMC Data 4 to 7 pins.
- * Replace emmc_data_8b_pins to emmc_data_4b_pins from sd_emmc_c pinctrl-0,
- * and change bus-width to 4 then spifc can be enabled.
- */
-&spifc {
- status = "disabled";
- pinctrl-0 = <&nor_pins>;
- pinctrl-names = "default";
-
- w25q128: spi-flash@0 {
- #address-cells = <1>;
- #size-cells = <1>;
- compatible = "winbond,w25q128fw", "jedec,spi-nor";
- reg = <0>;
- spi-max-frequency = <104000000>;
- };
-};
-
-&tdmif_a {
- status = "okay";
-};
-
-&tdmin_a {
- status = "okay";
-};
-
-&tdmout_a {
- status = "okay";
-};
-
-&toddr_a {
- status = "okay";
-};
-
-&toddr_b {
- status = "okay";
-};
-
-&toddr_c {
- status = "okay";
-};
-
-&tohdmitx {
- status = "okay";
-};
-
-&uart_A {
- status = "okay";
- pinctrl-0 = <&uart_a_pins>, <&uart_a_cts_rts_pins>;
- pinctrl-names = "default";
- uart-has-rtscts;
-
- bluetooth {
- compatible = "brcm,bcm43438-bt";
- shutdown-gpios = <&gpio GPIOX_17 GPIO_ACTIVE_HIGH>;
- max-speed = <2000000>;
- clocks = <&wifi32k>;
- clock-names = "lpo";
- };
-};
-
-&uart_AO {
- status = "okay";
- pinctrl-0 = <&uart_ao_a_pins>;
- pinctrl-names = "default";
-};
-
-&usb2_phy0 {
- phy-supply = <&dc_in>;
-};
-
-&usb2_phy1 {
- phy-supply = <&usb_pwr>;
-};
-
-&usb3_pcie_phy {
- phy-supply = <&usb_pwr>;
-};
-
-&usb {
- status = "okay";
- dr_mode = "peripheral";
-};
diff --git a/arch/arm/dts/meson-sm1-bananapi-m2-pro.dts b/arch/arm/dts/meson-sm1-bananapi-m2-pro.dts
deleted file mode 100644
index 5860343..0000000
--- a/arch/arm/dts/meson-sm1-bananapi-m2-pro.dts
+++ /dev/null
@@ -1,97 +0,0 @@
-// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
-/*
- * Copyright (c) 2021 BayLibre SAS
- * Author: Neil Armstrong <narmstrong@baylibre.com>
- */
-
-/dts-v1/;
-
-#include "meson-sm1-bananapi.dtsi"
-#include <dt-bindings/sound/meson-g12a-tohdmitx.h>
-
-/ {
- compatible = "bananapi,bpi-m2-pro", "amlogic,sm1";
- model = "Banana Pi BPI-M2-PRO";
-
- sound {
- compatible = "amlogic,axg-sound-card";
- model = "BPI-M2-PRO";
- audio-aux-devs = <&tdmout_b>;
- audio-routing = "TDMOUT_B IN 0", "FRDDR_A OUT 1",
- "TDMOUT_B IN 1", "FRDDR_B OUT 1",
- "TDMOUT_B IN 2", "FRDDR_C OUT 1",
- "TDM_B Playback", "TDMOUT_B OUT";
-
- assigned-clocks = <&clkc CLKID_MPLL2>,
- <&clkc CLKID_MPLL0>,
- <&clkc CLKID_MPLL1>;
- assigned-clock-parents = <0>, <0>, <0>;
- assigned-clock-rates = <294912000>,
- <270950400>,
- <393216000>;
-
- dai-link-0 {
- sound-dai = <&frddr_a>;
- };
-
- dai-link-1 {
- sound-dai = <&frddr_b>;
- };
-
- dai-link-2 {
- sound-dai = <&frddr_c>;
- };
-
- /* 8ch hdmi interface */
- dai-link-3 {
- sound-dai = <&tdmif_b>;
- dai-format = "i2s";
- dai-tdm-slot-tx-mask-0 = <1 1>;
- dai-tdm-slot-tx-mask-1 = <1 1>;
- dai-tdm-slot-tx-mask-2 = <1 1>;
- dai-tdm-slot-tx-mask-3 = <1 1>;
- mclk-fs = <256>;
-
- codec {
- sound-dai = <&tohdmitx TOHDMITX_I2S_IN_B>;
- };
- };
-
- /* hdmi glue */
- dai-link-4 {
- sound-dai = <&tohdmitx TOHDMITX_I2S_OUT>;
-
- codec {
- sound-dai = <&hdmi_tx>;
- };
- };
- };
-};
-
-&clkc_audio {
- status = "okay";
-};
-
-&frddr_a {
- status = "okay";
-};
-
-&frddr_b {
- status = "okay";
-};
-
-&frddr_c {
- status = "okay";
-};
-
-&tdmif_b {
- status = "okay";
-};
-
-&tdmout_b {
- status = "okay";
-};
-
-&tohdmitx {
- status = "okay";
-};
diff --git a/arch/arm/dts/meson-sm1-bananapi-m5.dts b/arch/arm/dts/meson-sm1-bananapi-m5.dts
deleted file mode 100644
index f045bf8..0000000
--- a/arch/arm/dts/meson-sm1-bananapi-m5.dts
+++ /dev/null
@@ -1,221 +0,0 @@
-// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
-/*
- * Copyright (c) 2021 BayLibre SAS
- * Author: Neil Armstrong <narmstrong@baylibre.com>
- */
-
-/dts-v1/;
-
-#include "meson-sm1-bananapi.dtsi"
-#include <dt-bindings/sound/meson-g12a-toacodec.h>
-#include <dt-bindings/sound/meson-g12a-tohdmitx.h>
-
-/ {
- compatible = "bananapi,bpi-m5", "amlogic,sm1";
- model = "Banana Pi BPI-M5";
-
- /* TOFIX: handle CVBS_DET on SARADC channel 0 */
- cvbs-connector {
- compatible = "composite-video-connector";
-
- port {
- cvbs_connector_in: endpoint {
- remote-endpoint = <&cvbs_vdac_out>;
- };
- };
- };
-
- sound {
- compatible = "amlogic,axg-sound-card";
- model = "BPI-M5";
- audio-widgets = "Line", "Lineout";
- audio-aux-devs = <&tdmout_b>, <&tdmout_c>,
- <&tdmin_a>, <&tdmin_b>, <&tdmin_c>;
- audio-routing = "TDMOUT_B IN 0", "FRDDR_A OUT 1",
- "TDMOUT_B IN 1", "FRDDR_B OUT 1",
- "TDMOUT_B IN 2", "FRDDR_C OUT 1",
- "TDM_B Playback", "TDMOUT_B OUT",
- "TDMOUT_C IN 0", "FRDDR_A OUT 2",
- "TDMOUT_C IN 1", "FRDDR_B OUT 2",
- "TDMOUT_C IN 2", "FRDDR_C OUT 2",
- "TDM_C Playback", "TDMOUT_C OUT",
- "TDMIN_A IN 4", "TDM_B Loopback",
- "TDMIN_B IN 4", "TDM_B Loopback",
- "TDMIN_C IN 4", "TDM_B Loopback",
- "TDMIN_A IN 5", "TDM_C Loopback",
- "TDMIN_B IN 5", "TDM_C Loopback",
- "TDMIN_C IN 5", "TDM_C Loopback",
- "TODDR_A IN 0", "TDMIN_A OUT",
- "TODDR_B IN 0", "TDMIN_A OUT",
- "TODDR_C IN 0", "TDMIN_A OUT",
- "TODDR_A IN 1", "TDMIN_B OUT",
- "TODDR_B IN 1", "TDMIN_B OUT",
- "TODDR_C IN 1", "TDMIN_B OUT",
- "TODDR_A IN 2", "TDMIN_C OUT",
- "TODDR_B IN 2", "TDMIN_C OUT",
- "TODDR_C IN 2", "TDMIN_C OUT",
- "Lineout", "ACODEC LOLP",
- "Lineout", "ACODEC LORP";
-
- assigned-clocks = <&clkc CLKID_MPLL2>,
- <&clkc CLKID_MPLL0>,
- <&clkc CLKID_MPLL1>;
- assigned-clock-parents = <0>, <0>, <0>;
- assigned-clock-rates = <294912000>,
- <270950400>,
- <393216000>;
-
- dai-link-0 {
- sound-dai = <&frddr_a>;
- };
-
- dai-link-1 {
- sound-dai = <&frddr_b>;
- };
-
- dai-link-2 {
- sound-dai = <&frddr_c>;
- };
-
- dai-link-3 {
- sound-dai = <&toddr_a>;
- };
-
- dai-link-4 {
- sound-dai = <&toddr_b>;
- };
-
- dai-link-5 {
- sound-dai = <&toddr_c>;
- };
-
- /* 8ch hdmi interface */
- dai-link-6 {
- sound-dai = <&tdmif_b>;
- dai-format = "i2s";
- dai-tdm-slot-tx-mask-0 = <1 1>;
- dai-tdm-slot-tx-mask-1 = <1 1>;
- dai-tdm-slot-tx-mask-2 = <1 1>;
- dai-tdm-slot-tx-mask-3 = <1 1>;
- mclk-fs = <256>;
-
- codec-0 {
- sound-dai = <&tohdmitx TOHDMITX_I2S_IN_B>;
- };
-
- codec-1 {
- sound-dai = <&toacodec TOACODEC_IN_B>;
- };
- };
-
- /* i2s jack output interface */
- dai-link-7 {
- sound-dai = <&tdmif_c>;
- dai-format = "i2s";
- dai-tdm-slot-tx-mask-0 = <1 1>;
- mclk-fs = <256>;
-
- codec-0 {
- sound-dai = <&tohdmitx TOHDMITX_I2S_IN_C>;
- };
-
- codec-1 {
- sound-dai = <&toacodec TOACODEC_IN_C>;
- };
- };
-
- /* hdmi glue */
- dai-link-8 {
- sound-dai = <&tohdmitx TOHDMITX_I2S_OUT>;
-
- codec {
- sound-dai = <&hdmi_tx>;
- };
- };
-
- /* acodec glue */
- dai-link-9 {
- sound-dai = <&toacodec TOACODEC_OUT>;
-
- codec {
- sound-dai = <&acodec>;
- };
- };
- };
-};
-
-&acodec {
- AVDD-supply = <&vddao_1v8>;
- status = "okay";
-};
-
-
-&clkc_audio {
- status = "okay";
-};
-
-&cvbs_vdac_port {
- cvbs_vdac_out: endpoint {
- remote-endpoint = <&cvbs_connector_in>;
- };
-};
-
-&frddr_a {
- status = "okay";
-};
-
-&frddr_b {
- status = "okay";
-};
-
-&frddr_c {
- status = "okay";
-};
-
-&tdmif_b {
- status = "okay";
-};
-
-&tdmif_c {
- status = "okay";
-};
-
-&tdmin_a {
- status = "okay";
-};
-
-&tdmin_b {
- status = "okay";
-};
-
-&tdmin_c {
- status = "okay";
-};
-
-&tdmout_b {
- status = "okay";
-};
-
-&tdmout_c {
- status = "okay";
-};
-
-&toacodec {
- status = "okay";
-};
-
-&tohdmitx {
- status = "okay";
-};
-
-&toddr_a {
- status = "okay";
-};
-
-&toddr_b {
- status = "okay";
-};
-
-&toddr_c {
- status = "okay";
-};
diff --git a/arch/arm/dts/meson-sm1-bananapi.dtsi b/arch/arm/dts/meson-sm1-bananapi.dtsi
deleted file mode 100644
index 17045ff..0000000
--- a/arch/arm/dts/meson-sm1-bananapi.dtsi
+++ /dev/null
@@ -1,435 +0,0 @@
-// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
-/*
- * Copyright (c) 2021 BayLibre SAS
- * Author: Neil Armstrong <narmstrong@baylibre.com>
- */
-
-#include "meson-sm1.dtsi"
-#include <dt-bindings/leds/common.h>
-#include <dt-bindings/input/linux-event-codes.h>
-#include <dt-bindings/gpio/meson-g12a-gpio.h>
-
-/ {
- adc-keys {
- compatible = "adc-keys";
- io-channels = <&saradc 2>;
- io-channel-names = "buttons";
- keyup-threshold-microvolt = <1800000>;
-
- button-sw3 {
- label = "SW3";
- linux,code = <BTN_3>;
- press-threshold-microvolt = <1700000>;
- };
- };
-
- aliases {
- serial0 = &uart_AO;
- ethernet0 = ðmac;
- };
-
- chosen {
- stdout-path = "serial0:115200n8";
- };
-
- emmc_pwrseq: emmc-pwrseq {
- compatible = "mmc-pwrseq-emmc";
- reset-gpios = <&gpio BOOT_12 GPIO_ACTIVE_LOW>;
- };
-
- gpio-keys {
- compatible = "gpio-keys";
-
- key {
- label = "SW1";
- linux,code = <BTN_1>;
- gpios = <&gpio_ao GPIOAO_3 GPIO_ACTIVE_LOW>;
- interrupt-parent = <&gpio_intc>;
- interrupts = <3 IRQ_TYPE_EDGE_BOTH>;
- };
- };
-
- hdmi-connector {
- compatible = "hdmi-connector";
- type = "a";
-
- port {
- hdmi_connector_in: endpoint {
- remote-endpoint = <&hdmi_tx_tmds_out>;
- };
- };
- };
-
- leds {
- compatible = "gpio-leds";
-
- led-green {
- color = <LED_COLOR_ID_GREEN>;
- function = LED_FUNCTION_STATUS;
- gpios = <&gpio_ao GPIOAO_2 GPIO_ACTIVE_LOW>;
- };
-
- led-blue {
- color = <LED_COLOR_ID_BLUE>;
- function = LED_FUNCTION_STATUS;
- gpios = <&gpio_ao GPIOAO_11 GPIO_ACTIVE_LOW>;
- linux,default-trigger = "heartbeat";
- };
- };
-
- memory@0 {
- device_type = "memory";
- reg = <0x0 0x0 0x0 0x40000000>;
- };
-
- emmc_1v8: regulator-emmc_1v8 {
- compatible = "regulator-fixed";
- regulator-name = "EMMC_1V8";
- regulator-min-microvolt = <1800000>;
- regulator-max-microvolt = <1800000>;
- vin-supply = <&vddao_3v3>;
- regulator-always-on;
- };
-
- dc_in: regulator-dc_in {
- compatible = "regulator-fixed";
- regulator-name = "DC_IN";
- regulator-min-microvolt = <5000000>;
- regulator-max-microvolt = <5000000>;
- regulator-always-on;
- };
-
- vddio_c: regulator-vddio_c {
- compatible = "regulator-gpio";
- regulator-name = "VDDIO_C";
- regulator-min-microvolt = <1800000>;
- regulator-max-microvolt = <3300000>;
-
- enable-gpios = <&gpio_ao GPIOE_2 GPIO_OPEN_DRAIN>;
- enable-active-high;
- regulator-always-on;
-
- gpios = <&gpio_ao GPIOAO_6 GPIO_OPEN_DRAIN>;
- gpios-states = <1>;
-
- states = <1800000 0>,
- <3300000 1>;
- };
-
- tflash_vdd: regulator-tflash_vdd {
- compatible = "regulator-fixed";
- regulator-name = "TFLASH_VDD";
- regulator-min-microvolt = <3300000>;
- regulator-max-microvolt = <3300000>;
- vin-supply = <&dc_in>;
- gpio = <&gpio GPIOH_8 GPIO_OPEN_DRAIN>;
- enable-active-high;
- regulator-always-on;
- };
-
- vddao_1v8: regulator-vddao_1v8 {
- compatible = "regulator-fixed";
- regulator-name = "VDDAO_1V8";
- regulator-min-microvolt = <1800000>;
- regulator-max-microvolt = <1800000>;
- vin-supply = <&vddao_3v3>;
- regulator-always-on;
- };
-
- vddao_3v3: regulator-vddao_3v3 {
- compatible = "regulator-fixed";
- regulator-name = "VDDAO_3V3";
- regulator-min-microvolt = <3300000>;
- regulator-max-microvolt = <3300000>;
- vin-supply = <&dc_in>;
- regulator-always-on;
- };
-
- vddcpu: regulator-vddcpu {
- /*
- * SY8120B1ABC DC/DC Regulator.
- */
- compatible = "pwm-regulator";
-
- regulator-name = "VDDCPU";
- regulator-min-microvolt = <690000>;
- regulator-max-microvolt = <1050000>;
-
- pwm-supply = <&dc_in>;
-
- pwms = <&pwm_AO_cd 1 1250 0>;
- pwm-dutycycle-range = <100 0>;
-
- regulator-boot-on;
- regulator-always-on;
- };
-
- /* USB Hub Power Enable */
- vl_pwr_en: regulator-vl_pwr_en {
- compatible = "regulator-fixed";
- regulator-name = "VL_PWR_EN";
- regulator-min-microvolt = <5000000>;
- regulator-max-microvolt = <5000000>;
- vin-supply = <&dc_in>;
-
- gpio = <&gpio GPIOH_6 GPIO_ACTIVE_HIGH>;
- enable-active-high;
- };
-};
-
-&arb {
- status = "okay";
-};
-
-&cpu0 {
- cpu-supply = <&vddcpu>;
- operating-points-v2 = <&cpu_opp_table>;
- clocks = <&clkc CLKID_CPU_CLK>;
- clock-latency = <50000>;
-};
-
-&cpu1 {
- cpu-supply = <&vddcpu>;
- operating-points-v2 = <&cpu_opp_table>;
- clocks = <&clkc CLKID_CPU1_CLK>;
- clock-latency = <50000>;
-};
-
-&cpu2 {
- cpu-supply = <&vddcpu>;
- operating-points-v2 = <&cpu_opp_table>;
- clocks = <&clkc CLKID_CPU2_CLK>;
- clock-latency = <50000>;
-};
-
-&cpu3 {
- cpu-supply = <&vddcpu>;
- operating-points-v2 = <&cpu_opp_table>;
- clocks = <&clkc CLKID_CPU3_CLK>;
- clock-latency = <50000>;
-};
-
-&ext_mdio {
- external_phy: ethernet-phy@0 {
- /* Realtek RTL8211F (0x001cc916) */
- reg = <0>;
- max-speed = <1000>;
-
- interrupt-parent = <&gpio_intc>;
- /* MAC_INTR on GPIOZ_14 */
- interrupts = <26 IRQ_TYPE_LEVEL_LOW>;
- };
-};
-
-ðmac {
- pinctrl-0 = <ð_pins>, <ð_rgmii_pins>;
- pinctrl-names = "default";
- status = "okay";
- phy-mode = "rgmii-txid";
- phy-handle = <&external_phy>;
-};
-
-&gpio {
- gpio-line-names =
- /* GPIOZ */
- "ETH_MDIO", /* GPIOZ_0 */
- "ETH_MDC", /* GPIOZ_1 */
- "ETH_RXCLK", /* GPIOZ_2 */
- "ETH_RX_DV", /* GPIOZ_3 */
- "ETH_RXD0", /* GPIOZ_4 */
- "ETH_RXD1", /* GPIOZ_5 */
- "ETH_RXD2", /* GPIOZ_6 */
- "ETH_RXD3", /* GPIOZ_7 */
- "ETH_TXCLK", /* GPIOZ_8 */
- "ETH_TXEN", /* GPIOZ_9 */
- "ETH_TXD0", /* GPIOZ_10 */
- "ETH_TXD1", /* GPIOZ_11 */
- "ETH_TXD2", /* GPIOZ_12 */
- "ETH_TXD3", /* GPIOZ_13 */
- "ETH_INTR", /* GPIOZ_14 */
- "ETH_NRST", /* GPIOZ_15 */
- /* GPIOH */
- "HDMI_SDA", /* GPIOH_0 */
- "HDMI_SCL", /* GPIOH_1 */
- "HDMI_HPD", /* GPIOH_2 */
- "HDMI_CEC", /* GPIOH_3 */
- "VL-RST_N", /* GPIOH_4 */
- "CON1-P36", /* GPIOH_5 */
- "VL-PWREN", /* GPIOH_6 */
- "WiFi_3V3_1V8", /* GPIOH_7 */
- "TFLASH_VDD_EN", /* GPIOH_8 */
- /* BOOT */
- "eMMC_D0", /* BOOT_0 */
- "eMMC_D1", /* BOOT_1 */
- "eMMC_D2", /* BOOT_2 */
- "eMMC_D3", /* BOOT_3 */
- "eMMC_D4", /* BOOT_4 */
- "eMMC_D5", /* BOOT_5 */
- "eMMC_D6", /* BOOT_6 */
- "eMMC_D7", /* BOOT_7 */
- "eMMC_CLK", /* BOOT_8 */
- "",
- "eMMC_CMD", /* BOOT_10 */
- "",
- "eMMC_RST#", /* BOOT_12 */
- "eMMC_DS", /* BOOT_13 */
- "", "",
- /* GPIOC */
- "SD_D0_B", /* GPIOC_0 */
- "SD_D1_B", /* GPIOC_1 */
- "SD_D2_B", /* GPIOC_2 */
- "SD_D3_B", /* GPIOC_3 */
- "SD_CLK_B", /* GPIOC_4 */
- "SD_CMD_B", /* GPIOC_5 */
- "CARD_EN_DET", /* GPIOC_6 */
- "",
- /* GPIOA */
- "", "", "", "", "", "", "", "",
- "", "", "", "", "", "",
- "CON1-P27", /* GPIOA_14 */
- "CON1-P28", /* GPIOA_15 */
- /* GPIOX */
- "CON1-P16", /* GPIOX_0 */
- "CON1-P18", /* GPIOX_1 */
- "CON1-P22", /* GPIOX_2 */
- "CON1-P11", /* GPIOX_3 */
- "CON1-P13", /* GPIOX_4 */
- "CON1-P07", /* GPIOX_5 */
- "CON1-P33", /* GPIOX_6 */
- "CON1-P15", /* GPIOX_7 */
- "CON1-P19", /* GPIOX_8 */
- "CON1-P21", /* GPIOX_9 */
- "CON1-P24", /* GPIOX_10 */
- "CON1-P23", /* GPIOX_11 */
- "CON1-P08", /* GPIOX_12 */
- "CON1-P10", /* GPIOX_13 */
- "CON1-P29", /* GPIOX_14 */
- "CON1-P31", /* GPIOX_15 */
- "CON1-P26", /* GPIOX_16 */
- "CON1-P03", /* GPIOX_17 */
- "CON1-P05", /* GPIOX_18 */
- "CON1-P32"; /* GPIOX_19 */
-
- /*
- * WARNING: The USB Hub needs a reset signal to be turned high in
- * order to be detected by the USB Controller. This signal should
- * be handled by a USB specific power sequence to reset the Hub
- * when the USB bus is powered down.
- */
- usb-hub-hog {
- gpio-hog;
- gpios = <GPIOH_4 GPIO_ACTIVE_HIGH>;
- output-high;
- line-name = "usb-hub-reset";
- };
-};
-
-&gpio_ao {
- gpio-line-names =
- /* GPIOAO */
- "DEBUG TX", /* GPIOAO_0 */
- "DEBUG RX", /* GPIOAO_1 */
- "SYS_LED2", /* GPIOAO_2 */
- "UPDATE_KEY", /* GPIOAO_3 */
- "CON1-P40", /* GPIOAO_4 */
- "IR_IN", /* GPIOAO_5 */
- "TF_3V3N_1V8_EN", /* GPIOAO_6 */
- "CON1-P35", /* GPIOAO_7 */
- "CON1-P12", /* GPIOAO_8 */
- "CON1-P37", /* GPIOAO_9 */
- "CON1-P38", /* GPIOAO_10 */
- "SYS_LED", /* GPIOAO_11 */
- /* GPIOE */
- "VDDEE_PWM", /* GPIOE_0 */
- "VDDCPU_PWM", /* GPIOE_1 */
- "TF_PWR_EN"; /* GPIOE_2 */
-};
-
-&hdmi_tx {
- status = "okay";
- pinctrl-0 = <&hdmitx_hpd_pins>, <&hdmitx_ddc_pins>;
- pinctrl-names = "default";
- hdmi-supply = <&dc_in>;
-};
-
-&hdmi_tx_tmds_port {
- hdmi_tx_tmds_out: endpoint {
- remote-endpoint = <&hdmi_connector_in>;
- };
-};
-
-&ir {
- status = "okay";
- pinctrl-0 = <&remote_input_ao_pins>;
- pinctrl-names = "default";
-};
-
-&pwm_AO_cd {
- pinctrl-0 = <&pwm_ao_d_e_pins>;
- pinctrl-names = "default";
- clocks = <&xtal>;
- clock-names = "clkin1";
- status = "okay";
-};
-
-&saradc {
- status = "okay";
- vref-supply = <&vddao_1v8>;
-};
-
-/* SD card */
-&sd_emmc_b {
- status = "okay";
- pinctrl-0 = <&sdcard_c_pins>;
- pinctrl-1 = <&sdcard_clk_gate_c_pins>;
- pinctrl-names = "default", "clk-gate";
-
- bus-width = <4>;
- cap-sd-highspeed;
- max-frequency = <50000000>;
- disable-wp;
-
- /* TOFIX: SD card is barely usable in SDR modes */
-
- cd-gpios = <&gpio GPIOC_6 GPIO_ACTIVE_LOW>;
- vmmc-supply = <&tflash_vdd>;
- vqmmc-supply = <&vddio_c>;
-};
-
-/* eMMC */
-&sd_emmc_c {
- status = "okay";
- pinctrl-0 = <&emmc_ctrl_pins>, <&emmc_data_8b_pins>, <&emmc_ds_pins>;
- pinctrl-1 = <&emmc_clk_gate_pins>;
- pinctrl-names = "default", "clk-gate";
-
- bus-width = <8>;
- cap-mmc-highspeed;
- mmc-ddr-1_8v;
- mmc-hs200-1_8v;
- max-frequency = <200000000>;
- disable-wp;
-
- mmc-pwrseq = <&emmc_pwrseq>;
- vmmc-supply = <&vddao_3v3>;
- vqmmc-supply = <&emmc_1v8>;
-};
-
-&uart_AO {
- status = "okay";
- pinctrl-0 = <&uart_ao_a_pins>;
- pinctrl-names = "default";
-};
-
-&usb {
- status = "okay";
-};
-
-&usb2_phy0 {
- phy-supply = <&dc_in>;
-};
-
-&usb2_phy1 {
- /* Enable the hub which is connected to this port */
- phy-supply = <&vl_pwr_en>;
-};
diff --git a/arch/arm/dts/meson-sm1-khadas-vim3l.dts b/arch/arm/dts/meson-sm1-khadas-vim3l.dts
deleted file mode 100644
index f2c0981..0000000
--- a/arch/arm/dts/meson-sm1-khadas-vim3l.dts
+++ /dev/null
@@ -1,113 +0,0 @@
-// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
-/*
- * Copyright (c) 2019 BayLibre, SAS
- * Author: Neil Armstrong <narmstrong@baylibre.com>
- */
-
-/dts-v1/;
-
-#include "meson-sm1.dtsi"
-#include "meson-khadas-vim3.dtsi"
-#include <dt-bindings/sound/meson-g12a-tohdmitx.h>
-
-/ {
- compatible = "khadas,vim3l", "amlogic,sm1";
- model = "Khadas VIM3L";
-
- vddcpu: regulator-vddcpu {
- /*
- * Silergy SY8030DEC Regulator.
- */
- compatible = "pwm-regulator";
-
- regulator-name = "VDDCPU";
- regulator-min-microvolt = <690000>;
- regulator-max-microvolt = <1050000>;
-
- vin-supply = <&vsys_3v3>;
-
- pwms = <&pwm_AO_cd 1 1250 0>;
- pwm-dutycycle-range = <100 0>;
-
- regulator-boot-on;
- regulator-always-on;
- };
-
- sound {
- model = "G12B-KHADAS-VIM3L";
- audio-routing = "TDMOUT_A IN 0", "FRDDR_A OUT 0",
- "TDMOUT_A IN 1", "FRDDR_B OUT 0",
- "TDMOUT_A IN 2", "FRDDR_C OUT 0",
- "TDM_A Playback", "TDMOUT_A OUT",
- "TDMIN_A IN 0", "TDM_A Capture",
- "TDMIN_A IN 13", "TDM_A Loopback",
- "TODDR_A IN 0", "TDMIN_A OUT",
- "TODDR_B IN 0", "TDMIN_A OUT",
- "TODDR_C IN 0", "TDMIN_A OUT";
- };
-};
-
-&cpu0 {
- cpu-supply = <&vddcpu>;
- operating-points-v2 = <&cpu_opp_table>;
- clocks = <&clkc CLKID_CPU_CLK>;
- clock-latency = <50000>;
-};
-
-&cpu1 {
- cpu-supply = <&vddcpu>;
- operating-points-v2 = <&cpu_opp_table>;
- clocks = <&clkc CLKID_CPU1_CLK>;
- clock-latency = <50000>;
-};
-
-&cpu2 {
- cpu-supply = <&vddcpu>;
- operating-points-v2 = <&cpu_opp_table>;
- clocks = <&clkc CLKID_CPU2_CLK>;
- clock-latency = <50000>;
-};
-
-&cpu3 {
- cpu-supply = <&vddcpu>;
- operating-points-v2 = <&cpu_opp_table>;
- clocks = <&clkc CLKID_CPU3_CLK>;
- clock-latency = <50000>;
-};
-
-&pwm_AO_cd {
- pinctrl-0 = <&pwm_ao_d_e_pins>;
- pinctrl-names = "default";
- clocks = <&xtal>;
- clock-names = "clkin1";
- status = "okay";
-};
-
-/*
- * The VIM3 on-board MCU can mux the PCIe/USB3.0 shared differential
- * lines using a FUSB340TMX USB 3.1 SuperSpeed Data Switch between
- * an USB3.0 Type A connector and a M.2 Key M slot.
- * The PHY driving these differential lines is shared between
- * the USB3.0 controller and the PCIe Controller, thus only
- * a single controller can use it.
- * If the MCU is configured to mux the PCIe/USB3.0 differential lines
- * to the M.2 Key M slot, uncomment the following block to disable
- * USB3.0 from the USB Complex and enable the PCIe controller.
- * The End User is not expected to uncomment the following except for
- * testing purposes, but instead rely on the firmware/bootloader to
- * update these nodes accordingly if PCIe mode is selected by the MCU.
- */
-/*
-&pcie {
- status = "okay";
-};
-
-&usb {
- phys = <&usb2_phy0>, <&usb2_phy1>;
- phy-names = "usb2-phy0", "usb2-phy1";
-};
- */
-
-&sd_emmc_a {
- sd-uhs-sdr50;
-};
diff --git a/arch/arm/dts/meson-sm1-odroid-c4.dts b/arch/arm/dts/meson-sm1-odroid-c4.dts
deleted file mode 100644
index 8c30ce6..0000000
--- a/arch/arm/dts/meson-sm1-odroid-c4.dts
+++ /dev/null
@@ -1,48 +0,0 @@
-// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
-/*
- * Copyright (c) 2020 Dongjin Kim <tobetter@gmail.com>
- */
-
-/dts-v1/;
-
-#include "meson-sm1-odroid.dtsi"
-
-/ {
- compatible = "hardkernel,odroid-c4", "amlogic,sm1";
- model = "Hardkernel ODROID-C4";
-
- leds {
- compatible = "gpio-leds";
-
- led-blue {
- color = <LED_COLOR_ID_BLUE>;
- function = LED_FUNCTION_STATUS;
- gpios = <&gpio_ao GPIOAO_11 GPIO_ACTIVE_HIGH>;
- linux,default-trigger = "heartbeat";
- panic-indicator;
- };
- };
-
- sound {
- model = "ODROID-C4";
- };
-};
-
-&gpio {
- /*
- * WARNING: The USB Hub on the Odroid-C4 needs a reset signal
- * to be turned high in order to be detected by the USB Controller
- * This signal should be handled by a USB specific power sequence
- * in order to reset the Hub when USB bus is powered down.
- */
- hog-0 {
- gpio-hog;
- gpios = <GPIOH_4 GPIO_ACTIVE_HIGH>;
- output-high;
- line-name = "usb-hub-reset";
- };
-};
-
-&ir {
- linux,rc-map-name = "rc-odroid";
-};
diff --git a/arch/arm/dts/meson-sm1-odroid-hc4.dts b/arch/arm/dts/meson-sm1-odroid-hc4.dts
deleted file mode 100644
index f3f9532..0000000
--- a/arch/arm/dts/meson-sm1-odroid-hc4.dts
+++ /dev/null
@@ -1,140 +0,0 @@
-// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
-/*
- * Copyright (c) 2020 Dongjin Kim <tobetter@gmail.com>
- */
-
-/dts-v1/;
-
-#include "meson-sm1-odroid.dtsi"
-
-/ {
- compatible = "hardkernel,odroid-hc4", "amlogic,sm1";
- model = "Hardkernel ODROID-HC4";
-
- aliases {
- rtc0 = &rtc;
- rtc1 = &vrtc;
- };
-
- fan0: pwm-fan {
- compatible = "pwm-fan";
- #cooling-cells = <2>;
- cooling-min-state = <0>;
- cooling-max-state = <3>;
- cooling-levels = <0 120 170 220>;
- pwms = <&pwm_cd 1 40000 0>;
- };
-
- leds {
- compatible = "gpio-leds";
-
- led-blue {
- color = <LED_COLOR_ID_BLUE>;
- function = LED_FUNCTION_STATUS;
- gpios = <&gpio_ao GPIOAO_11 GPIO_ACTIVE_HIGH>;
- linux,default-trigger = "heartbeat";
- panic-indicator;
- };
-
- led-red {
- color = <LED_COLOR_ID_RED>;
- function = LED_FUNCTION_POWER;
- gpios = <&gpio_ao GPIOAO_7 GPIO_ACTIVE_HIGH>;
- default-state = "on";
- };
- };
-
- /* Powers the SATA Disk 0 regulator, which is enabled when a disk load is detected */
- p12v_0: regulator-p12v_0 {
- compatible = "regulator-fixed";
- regulator-name = "P12V_0";
- regulator-min-microvolt = <12000000>;
- regulator-max-microvolt = <12000000>;
- vin-supply = <&main_12v>;
-
- gpio = <&gpio GPIOH_8 GPIO_OPEN_DRAIN>;
- enable-active-high;
- regulator-always-on;
- };
-
- /* Powers the SATA Disk 1 regulator, which is enabled when a disk load is detected */
- p12v_1: regulator-p12v_1 {
- compatible = "regulator-fixed";
- regulator-name = "P12V_1";
- regulator-min-microvolt = <12000000>;
- regulator-max-microvolt = <12000000>;
- vin-supply = <&main_12v>;
-
- gpio = <&gpio GPIOH_8 GPIO_OPEN_DRAIN>;
- enable-active-high;
- regulator-always-on;
- };
-
- sound {
- model = "ODROID-HC4";
- };
-};
-
-&cpu_thermal {
- cooling-maps {
- map {
- trip = <&cpu_passive>;
- cooling-device = <&fan0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
- };
- };
-};
-
-&ir {
- linux,rc-map-name = "rc-odroid";
-};
-
-&i2c2 {
- status = "okay";
- pinctrl-0 = <&i2c2_sda_x_pins>, <&i2c2_sck_x_pins>;
- pinctrl-names = "default";
-
- rtc: rtc@51 {
- status = "okay";
- compatible = "nxp,pcf8563";
- reg = <0x51>;
- wakeup-source;
- };
-};
-
-&pcie {
- status = "okay";
- reset-gpios = <&gpio GPIOH_4 GPIO_ACTIVE_LOW>;
-};
-
-&pwm_cd {
- status = "okay";
- pinctrl-names = "default";
- pinctrl-0 = <&pwm_d_x6_pins>;
-};
-
-&sd_emmc_c {
- status = "disabled";
-};
-
-&spifc {
- status = "okay";
- pinctrl-0 = <&nor_pins>;
- pinctrl-names = "default";
-
- spi-flash@0 {
- #address-cells = <1>;
- #size-cells = <1>;
- compatible = "jedec,spi-nor";
- reg = <0>;
- spi-max-frequency = <104000000>;
- };
-};
-
-&usb {
- phys = <&usb2_phy1>;
- phy-names = "usb2-phy1";
-};
-
-&usb2_phy0 {
- status = "disabled";
-};
diff --git a/arch/arm/dts/meson-sm1-odroid.dtsi b/arch/arm/dts/meson-sm1-odroid.dtsi
deleted file mode 100644
index fd0ad85..0000000
--- a/arch/arm/dts/meson-sm1-odroid.dtsi
+++ /dev/null
@@ -1,449 +0,0 @@
-// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
-/*
- * Copyright (c) 2020 Dongjin Kim <tobetter@gmail.com>
- */
-
-#include "meson-sm1.dtsi"
-#include <dt-bindings/gpio/meson-g12a-gpio.h>
-#include <dt-bindings/leds/common.h>
-#include <dt-bindings/sound/meson-g12a-tohdmitx.h>
-
-/ {
- aliases {
- serial0 = &uart_AO;
- ethernet0 = ðmac;
- };
-
- chosen {
- stdout-path = "serial0:115200n8";
- };
-
- memory@0 {
- device_type = "memory";
- reg = <0x0 0x0 0x0 0x40000000>;
- };
-
- emmc_pwrseq: emmc-pwrseq {
- compatible = "mmc-pwrseq-emmc";
- reset-gpios = <&gpio BOOT_12 GPIO_ACTIVE_LOW>;
- };
-
- tflash_vdd: regulator-tflash_vdd {
- compatible = "regulator-fixed";
-
- regulator-name = "TFLASH_VDD";
- regulator-min-microvolt = <3300000>;
- regulator-max-microvolt = <3300000>;
-
- gpio = <&gpio_ao GPIOAO_3 GPIO_OPEN_DRAIN>;
- enable-active-high;
- regulator-always-on;
- };
-
- tf_io: gpio-regulator-tf_io {
- compatible = "regulator-gpio";
-
- regulator-name = "TF_IO";
- regulator-min-microvolt = <1800000>;
- regulator-max-microvolt = <3300000>;
- vin-supply = <&vcc_5v>;
-
- enable-gpio = <&gpio GPIOE_2 GPIO_ACTIVE_HIGH>;
- enable-active-high;
- regulator-always-on;
-
- gpios = <&gpio_ao GPIOAO_6 GPIO_OPEN_SOURCE>;
- gpios-states = <0>;
-
- states = <3300000 0>,
- <1800000 1>;
- };
-
- flash_1v8: regulator-flash_1v8 {
- compatible = "regulator-fixed";
- regulator-name = "FLASH_1V8";
- regulator-min-microvolt = <1800000>;
- regulator-max-microvolt = <1800000>;
- vin-supply = <&vcc_3v3>;
- regulator-always-on;
- };
-
- main_12v: regulator-main_12v {
- compatible = "regulator-fixed";
- regulator-name = "12V";
- regulator-min-microvolt = <12000000>;
- regulator-max-microvolt = <12000000>;
- regulator-always-on;
- };
-
- vcc_5v: regulator-vcc_5v {
- compatible = "regulator-fixed";
- regulator-name = "5V";
- regulator-min-microvolt = <5000000>;
- regulator-max-microvolt = <5000000>;
- regulator-always-on;
- vin-supply = <&main_12v>;
- gpio = <&gpio GPIOH_8 GPIO_OPEN_DRAIN>;
- enable-active-high;
- };
-
- vcc_1v8: regulator-vcc_1v8 {
- compatible = "regulator-fixed";
- regulator-name = "VCC_1V8";
- regulator-min-microvolt = <1800000>;
- regulator-max-microvolt = <1800000>;
- vin-supply = <&vcc_3v3>;
- regulator-always-on;
- };
-
- vcc_3v3: regulator-vcc_3v3 {
- compatible = "regulator-fixed";
- regulator-name = "VCC_3V3";
- regulator-min-microvolt = <3300000>;
- regulator-max-microvolt = <3300000>;
- vin-supply = <&vddao_3v3>;
- regulator-always-on;
- /* FIXME: actually controlled by VDDCPU_B_EN */
- };
-
- vddcpu: regulator-vddcpu {
- /*
- * MP8756GD Regulator.
- */
- compatible = "pwm-regulator";
-
- regulator-name = "VDDCPU";
- regulator-min-microvolt = <721000>;
- regulator-max-microvolt = <1022000>;
-
- vin-supply = <&main_12v>;
-
- pwms = <&pwm_AO_cd 1 1250 0>;
- pwm-dutycycle-range = <100 0>;
-
- regulator-boot-on;
- regulator-always-on;
- };
-
- usb_pwr_en: regulator-usb_pwr_en {
- compatible = "regulator-fixed";
- regulator-name = "USB_PWR_EN";
- regulator-min-microvolt = <5000000>;
- regulator-max-microvolt = <5000000>;
- vin-supply = <&vcc_5v>;
-
- /* Connected to the microUSB port power enable */
- gpio = <&gpio_ao GPIOAO_2 GPIO_ACTIVE_HIGH>;
- enable-active-high;
- };
-
- vddao_1v8: regulator-vddao_1v8 {
- compatible = "regulator-fixed";
- regulator-name = "VDDAO_1V8";
- regulator-min-microvolt = <1800000>;
- regulator-max-microvolt = <1800000>;
- vin-supply = <&vddao_3v3>;
- regulator-always-on;
- };
-
- vddao_3v3: regulator-vddao_3v3 {
- compatible = "regulator-fixed";
- regulator-name = "VDDAO_3V3";
- regulator-min-microvolt = <3300000>;
- regulator-max-microvolt = <3300000>;
- vin-supply = <&main_12v>;
- regulator-always-on;
- };
-
- hdmi-connector {
- compatible = "hdmi-connector";
- type = "a";
-
- port {
- hdmi_connector_in: endpoint {
- remote-endpoint = <&hdmi_tx_tmds_out>;
- };
- };
- };
-
- sound {
- compatible = "amlogic,axg-sound-card";
- audio-aux-devs = <&tdmout_b>;
- audio-routing = "TDMOUT_B IN 0", "FRDDR_A OUT 1",
- "TDMOUT_B IN 1", "FRDDR_B OUT 1",
- "TDMOUT_B IN 2", "FRDDR_C OUT 1",
- "TDM_B Playback", "TDMOUT_B OUT";
-
- assigned-clocks = <&clkc CLKID_MPLL2>,
- <&clkc CLKID_MPLL0>,
- <&clkc CLKID_MPLL1>;
- assigned-clock-parents = <0>, <0>, <0>;
- assigned-clock-rates = <294912000>,
- <270950400>,
- <393216000>;
- status = "okay";
-
- dai-link-0 {
- sound-dai = <&frddr_a>;
- };
-
- dai-link-1 {
- sound-dai = <&frddr_b>;
- };
-
- dai-link-2 {
- sound-dai = <&frddr_c>;
- };
-
- /* 8ch hdmi interface */
- dai-link-3 {
- sound-dai = <&tdmif_b>;
- dai-format = "i2s";
- dai-tdm-slot-tx-mask-0 = <1 1>;
- dai-tdm-slot-tx-mask-1 = <1 1>;
- dai-tdm-slot-tx-mask-2 = <1 1>;
- dai-tdm-slot-tx-mask-3 = <1 1>;
- mclk-fs = <256>;
-
- codec {
- sound-dai = <&tohdmitx TOHDMITX_I2S_IN_B>;
- };
- };
-
- /* hdmi glue */
- dai-link-4 {
- sound-dai = <&tohdmitx TOHDMITX_I2S_OUT>;
-
- codec {
- sound-dai = <&hdmi_tx>;
- };
- };
- };
-};
-
-&arb {
- status = "okay";
-};
-
-&clkc_audio {
- status = "okay";
-};
-
-&cpu0 {
- cpu-supply = <&vddcpu>;
- operating-points-v2 = <&cpu_opp_table>;
- clocks = <&clkc CLKID_CPU_CLK>;
- clock-latency = <50000>;
-};
-
-&cpu1 {
- cpu-supply = <&vddcpu>;
- operating-points-v2 = <&cpu_opp_table>;
- clocks = <&clkc CLKID_CPU1_CLK>;
- clock-latency = <50000>;
-};
-
-&cpu2 {
- cpu-supply = <&vddcpu>;
- operating-points-v2 = <&cpu_opp_table>;
- clocks = <&clkc CLKID_CPU2_CLK>;
- clock-latency = <50000>;
-};
-
-&cpu3 {
- cpu-supply = <&vddcpu>;
- operating-points-v2 = <&cpu_opp_table>;
- clocks = <&clkc CLKID_CPU3_CLK>;
- clock-latency = <50000>;
-};
-
-&ext_mdio {
- external_phy: ethernet-phy@0 {
- /* Realtek RTL8211F (0x001cc916) */
- reg = <0>;
- max-speed = <1000>;
-
- interrupt-parent = <&gpio_intc>;
- /* MAC_INTR on GPIOZ_14 */
- interrupts = <26 IRQ_TYPE_LEVEL_LOW>;
- };
-};
-
-ðmac {
- pinctrl-0 = <ð_pins>, <ð_rgmii_pins>;
- pinctrl-names = "default";
- status = "okay";
- phy-mode = "rgmii";
- phy-handle = <&external_phy>;
- amlogic,tx-delay-ns = <2>;
-};
-
-&frddr_a {
- status = "okay";
-};
-
-&frddr_b {
- status = "okay";
-};
-
-&frddr_c {
- status = "okay";
-};
-
-&gpio {
- gpio-line-names =
- /* GPIOZ */
- "", "", "", "", "", "", "", "",
- "", "", "", "", "", "", "", "",
- /* GPIOH */
- "", "", "", "", "",
- "PIN_36", /* GPIOH_5 */
- "PIN_26", /* GPIOH_6 */
- "PIN_32", /* GPIOH_7 */
- "",
- /* BOOT */
- "", "", "", "", "", "", "", "",
- "", "", "", "", "", "", "", "",
- /* GPIOC */
- "", "", "", "", "", "", "", "",
- /* GPIOA */
- "", "", "", "", "", "", "", "",
- "", "", "", "", "", "",
- "PIN_27", /* GPIOA_14 */
- "PIN_28", /* GPIOA_15 */
- /* GPIOX */
- "PIN_16", /* GPIOX_0 */
- "PIN_18", /* GPIOX_1 */
- "PIN_22", /* GPIOX_2 */
- "PIN_11", /* GPIOX_3 */
- "PIN_13", /* GPIOX_4 */
- "PIN_7", /* GPIOX_5 */
- "PIN_33", /* GPIOX_6 */
- "PIN_15", /* GPIOX_7 */
- "PIN_19", /* GPIOX_8 */
- "PIN_21", /* GPIOX_9 */
- "PIN_24", /* GPIOX_10 */
- "PIN_23", /* GPIOX_11 */
- "PIN_8", /* GPIOX_12 */
- "PIN_10", /* GPIOX_13 */
- "PIN_29", /* GPIOX_14 */
- "PIN_31", /* GPIOX_15 */
- "PIN_12", /* GPIOX_16 */
- "PIN_3", /* GPIOX_17 */
- "PIN_5", /* GPIOX_18 */
- "PIN_35"; /* GPIOX_19 */
-};
-
-&gpio_ao {
- gpio-line-names =
- /* GPIOAO */
- "", "", "", "",
- "PIN_47", /* GPIOAO_4 */
- "", "",
- "PIN_45", /* GPIOAO_7 */
- "PIN_46", /* GPIOAO_8 */
- "PIN_44", /* GPIOAO_9 */
- "PIN_42", /* GPIOAO_10 */
- "",
- /* GPIOE */
- "", "", "";
-};
-
-&hdmi_tx {
- status = "okay";
- pinctrl-0 = <&hdmitx_hpd_pins>, <&hdmitx_ddc_pins>;
- pinctrl-names = "default";
- hdmi-supply = <&vcc_5v>;
-};
-
-&hdmi_tx_tmds_port {
- hdmi_tx_tmds_out: endpoint {
- remote-endpoint = <&hdmi_connector_in>;
- };
-};
-
-&ir {
- status = "okay";
- pinctrl-0 = <&remote_input_ao_pins>;
- pinctrl-names = "default";
-};
-
-&pwm_AO_cd {
- pinctrl-0 = <&pwm_ao_d_e_pins>;
- pinctrl-names = "default";
- clocks = <&xtal>;
- clock-names = "clkin1";
- status = "okay";
-};
-
-&saradc {
- status = "okay";
-};
-
-/* SD card */
-&sd_emmc_b {
- status = "okay";
- pinctrl-0 = <&sdcard_c_pins>;
- pinctrl-1 = <&sdcard_clk_gate_c_pins>;
- pinctrl-names = "default", "clk-gate";
-
- bus-width = <4>;
- cap-sd-highspeed;
- max-frequency = <200000000>;
- sd-uhs-sdr12;
- sd-uhs-sdr25;
- sd-uhs-sdr50;
- sd-uhs-sdr104;
- disable-wp;
-
- cd-gpios = <&gpio GPIOC_6 GPIO_ACTIVE_LOW>;
- vmmc-supply = <&tflash_vdd>;
- vqmmc-supply = <&tf_io>;
-};
-
-/* eMMC */
-&sd_emmc_c {
- status = "okay";
- pinctrl-0 = <&emmc_ctrl_pins>, <&emmc_data_8b_pins>, <&emmc_ds_pins>;
- pinctrl-1 = <&emmc_clk_gate_pins>;
- pinctrl-names = "default", "clk-gate";
-
- bus-width = <8>;
- cap-mmc-highspeed;
- mmc-ddr-1_8v;
- mmc-hs200-1_8v;
- max-frequency = <200000000>;
- disable-wp;
-
- mmc-pwrseq = <&emmc_pwrseq>;
- vmmc-supply = <&vcc_3v3>;
- vqmmc-supply = <&flash_1v8>;
-};
-
-&tdmif_b {
- status = "okay";
-};
-
-&tdmout_b {
- status = "okay";
-};
-
-&tohdmitx {
- status = "okay";
-};
-
-&uart_AO {
- status = "okay";
- pinctrl-0 = <&uart_ao_a_pins>;
- pinctrl-names = "default";
-};
-
-&usb {
- status = "okay";
- vbus-supply = <&usb_pwr_en>;
-};
-
-&usb2_phy0 {
- phy-supply = <&vcc_5v>;
-};
-
diff --git a/arch/arm/dts/meson-sm1-sei610.dts b/arch/arm/dts/meson-sm1-sei610.dts
deleted file mode 100644
index 2194a77..0000000
--- a/arch/arm/dts/meson-sm1-sei610.dts
+++ /dev/null
@@ -1,616 +0,0 @@
-// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
-/*
- * Copyright (c) 2019 BayLibre SAS. All rights reserved.
- */
-
-/dts-v1/;
-
-#include "meson-sm1.dtsi"
-#include <dt-bindings/gpio/gpio.h>
-#include <dt-bindings/input/input.h>
-#include <dt-bindings/gpio/meson-g12a-gpio.h>
-#include <dt-bindings/sound/meson-g12a-tohdmitx.h>
-
-/ {
- compatible = "seirobotics,sei610", "amlogic,sm1";
- model = "SEI Robotics SEI610";
-
- aliases {
- serial0 = &uart_AO;
- ethernet0 = ðmac;
- };
-
- mono_dac: audio-codec-0 {
- compatible = "maxim,max98357a";
- #sound-dai-cells = <0>;
- sound-name-prefix = "U16";
- sdmode-gpios = <&gpio GPIOX_8 GPIO_ACTIVE_HIGH>;
- };
-
- dmics: audio-codec-1 {
- #sound-dai-cells = <0>;
- compatible = "dmic-codec";
- num-channels = <2>;
- wakeup-delay-ms = <50>;
- status = "okay";
- sound-name-prefix = "MIC";
- };
-
- chosen {
- stdout-path = "serial0:115200n8";
- };
-
- emmc_pwrseq: emmc-pwrseq {
- compatible = "mmc-pwrseq-emmc";
- reset-gpios = <&gpio BOOT_12 GPIO_ACTIVE_LOW>;
- };
-
- gpio-keys {
- compatible = "gpio-keys";
-
- key1 {
- label = "A";
- linux,code = <BTN_0>;
- gpios = <&gpio GPIOH_6 GPIO_ACTIVE_LOW>;
- interrupt-parent = <&gpio_intc>;
- interrupts = <34 IRQ_TYPE_EDGE_BOTH>;
- };
-
- key2 {
- label = "B";
- linux,code = <BTN_1>;
- gpios = <&gpio GPIOH_7 GPIO_ACTIVE_LOW>;
- interrupt-parent = <&gpio_intc>;
- interrupts = <35 IRQ_TYPE_EDGE_BOTH>;
- };
-
- key3 {
- label = "C";
- linux,code = <BTN_2>;
- gpios = <&gpio_ao GPIOAO_2 GPIO_ACTIVE_LOW>;
- interrupt-parent = <&gpio_intc>;
- interrupts = <2 IRQ_TYPE_EDGE_BOTH>;
- };
-
- mic_mute {
- label = "MicMute";
- linux,code = <SW_MUTE_DEVICE>;
- linux,input-type = <EV_SW>;
- gpios = <&gpio_ao GPIOE_2 GPIO_ACTIVE_LOW>;
- interrupt-parent = <&gpio_intc>;
- interrupts = <99 IRQ_TYPE_EDGE_BOTH>;
- };
-
- power_key {
- label = "PowerKey";
- linux,code = <KEY_POWER>;
- gpios = <&gpio_ao GPIOAO_3 GPIO_ACTIVE_LOW>;
- interrupt-parent = <&gpio_intc>;
- interrupts = <3 IRQ_TYPE_EDGE_BOTH>;
- };
- };
-
- hdmi-connector {
- compatible = "hdmi-connector";
- type = "a";
-
- port {
- hdmi_connector_in: endpoint {
- remote-endpoint = <&hdmi_tx_tmds_out>;
- };
- };
- };
-
- led-controller-1 {
- compatible = "gpio-leds";
-
- led-1 {
- label = "sei610:blue:bt";
- gpios = <&gpio GPIOC_7 (GPIO_ACTIVE_LOW | GPIO_OPEN_DRAIN)>;
- default-state = "off";
- };
- };
-
- led-controller-2 {
- compatible = "pwm-leds";
-
- led-2 {
- label = "sei610:red:power";
- pwms = <&pwm_AO_ab 0 30518 0>;
- max-brightness = <255>;
- linux,default-trigger = "default-on";
- active-low;
- };
- };
-
- memory@0 {
- device_type = "memory";
- reg = <0x0 0x0 0x0 0x40000000>;
- };
-
- ao_5v: regulator-ao_5v {
- compatible = "regulator-fixed";
- regulator-name = "AO_5V";
- regulator-min-microvolt = <5000000>;
- regulator-max-microvolt = <5000000>;
- vin-supply = <&dc_in>;
- regulator-always-on;
- };
-
- dc_in: regulator-dc_in {
- compatible = "regulator-fixed";
- regulator-name = "DC_IN";
- regulator-min-microvolt = <5000000>;
- regulator-max-microvolt = <5000000>;
- regulator-always-on;
- };
-
- emmc_1v8: regulator-emmc_1v8 {
- compatible = "regulator-fixed";
- regulator-name = "EMMC_1V8";
- regulator-min-microvolt = <1800000>;
- regulator-max-microvolt = <1800000>;
- vin-supply = <&vddao_3v3>;
- regulator-always-on;
- };
-
- vddao_3v3: regulator-vddao_3v3 {
- compatible = "regulator-fixed";
- regulator-name = "VDDAO_3V3";
- regulator-min-microvolt = <3300000>;
- regulator-max-microvolt = <3300000>;
- vin-supply = <&dc_in>;
- regulator-always-on;
- };
-
- /* Used by Tuner, RGB Led & IR Emitter LED array */
- vddao_3v3_t: regulator-vddao_3v3_t {
- compatible = "regulator-fixed";
- regulator-name = "VDDAO_3V3_T";
- regulator-min-microvolt = <3300000>;
- regulator-max-microvolt = <3300000>;
- vin-supply = <&vddao_3v3>;
- gpio = <&gpio GPIOH_8 GPIO_OPEN_DRAIN>;
- enable-active-low;
- regulator-always-on;
- };
-
- vddcpu: regulator-vddcpu {
- /*
- * SY8120B1ABC DC/DC Regulator.
- */
- compatible = "pwm-regulator";
-
- regulator-name = "VDDCPU";
- regulator-min-microvolt = <690000>;
- regulator-max-microvolt = <1050000>;
-
- vin-supply = <&dc_in>;
-
- pwms = <&pwm_AO_cd 1 1500 0>;
- pwm-dutycycle-range = <100 0>;
-
- regulator-boot-on;
- regulator-always-on;
- };
-
- vddio_ao1v8: regulator-vddio_ao1v8 {
- compatible = "regulator-fixed";
- regulator-name = "VDDIO_AO1V8";
- regulator-min-microvolt = <1800000>;
- regulator-max-microvolt = <1800000>;
- vin-supply = <&vddao_3v3>;
- regulator-always-on;
- };
-
- reserved-memory {
- /* TEE Reserved Memory */
- bl32_reserved: bl32@5000000 {
- reg = <0x0 0x05300000 0x0 0x2000000>;
- no-map;
- };
- };
-
- sdio_pwrseq: sdio-pwrseq {
- compatible = "mmc-pwrseq-simple";
- reset-gpios = <&gpio GPIOX_6 GPIO_ACTIVE_LOW>;
- clocks = <&wifi32k>;
- clock-names = "ext_clock";
- };
-
- sound {
- compatible = "amlogic,axg-sound-card";
- model = "SEI610";
- audio-aux-devs = <&tdmout_a>, <&tdmout_b>,
- <&tdmin_a>, <&tdmin_b>;
- audio-routing = "TDMOUT_A IN 0", "FRDDR_A OUT 0",
- "TDMOUT_A IN 1", "FRDDR_B OUT 0",
- "TDMOUT_A IN 2", "FRDDR_C OUT 0",
- "TDM_A Playback", "TDMOUT_A OUT",
- "TDMOUT_B IN 0", "FRDDR_A OUT 1",
- "TDMOUT_B IN 1", "FRDDR_B OUT 1",
- "TDMOUT_B IN 2", "FRDDR_C OUT 1",
- "TDM_B Playback", "TDMOUT_B OUT",
- "TODDR_A IN 4", "PDM Capture",
- "TODDR_B IN 4", "PDM Capture",
- "TODDR_C IN 4", "PDM Capture",
- "TDMIN_A IN 0", "TDM_A Capture",
- "TDMIN_A IN 3", "TDM_A Loopback",
- "TDMIN_B IN 0", "TDM_A Capture",
- "TDMIN_B IN 3", "TDM_A Loopback",
- "TDMIN_A IN 1", "TDM_B Capture",
- "TDMIN_A IN 4", "TDM_B Loopback",
- "TDMIN_B IN 1", "TDM_B Capture",
- "TDMIN_B IN 4", "TDM_B Loopback",
- "TODDR_A IN 0", "TDMIN_A OUT",
- "TODDR_B IN 0", "TDMIN_A OUT",
- "TODDR_C IN 0", "TDMIN_A OUT",
- "TODDR_A IN 1", "TDMIN_B OUT",
- "TODDR_B IN 1", "TDMIN_B OUT",
- "TODDR_C IN 1", "TDMIN_B OUT";
-
- assigned-clocks = <&clkc CLKID_MPLL2>,
- <&clkc CLKID_MPLL0>,
- <&clkc CLKID_MPLL1>;
- assigned-clock-parents = <0>, <0>, <0>;
- assigned-clock-rates = <294912000>,
- <270950400>,
- <393216000>;
- status = "okay";
-
- dai-link-0 {
- sound-dai = <&frddr_a>;
- };
-
- dai-link-1 {
- sound-dai = <&frddr_b>;
- };
-
- dai-link-2 {
- sound-dai = <&frddr_c>;
- };
-
- dai-link-3 {
- sound-dai = <&toddr_a>;
- };
-
- dai-link-4 {
- sound-dai = <&toddr_b>;
- };
-
- dai-link-5 {
- sound-dai = <&toddr_c>;
- };
-
- /* internal speaker interface */
- dai-link-6 {
- sound-dai = <&tdmif_a>;
- dai-format = "i2s";
- dai-tdm-slot-tx-mask-0 = <1 1>;
- mclk-fs = <256>;
-
- codec-0 {
- sound-dai = <&mono_dac>;
- };
-
- codec-1 {
- sound-dai = <&tohdmitx TOHDMITX_I2S_IN_A>;
- };
- };
-
- /* 8ch hdmi interface */
- dai-link-7 {
- sound-dai = <&tdmif_b>;
- dai-format = "i2s";
- dai-tdm-slot-tx-mask-0 = <1 1>;
- dai-tdm-slot-tx-mask-1 = <1 1>;
- dai-tdm-slot-tx-mask-2 = <1 1>;
- dai-tdm-slot-tx-mask-3 = <1 1>;
- mclk-fs = <256>;
-
- codec {
- sound-dai = <&tohdmitx TOHDMITX_I2S_IN_B>;
- };
- };
-
- /* internal digital mics */
- dai-link-8 {
- sound-dai = <&pdm>;
-
- codec {
- sound-dai = <&dmics>;
- };
- };
-
- /* hdmi glue */
- dai-link-9 {
- sound-dai = <&tohdmitx TOHDMITX_I2S_OUT>;
-
- codec {
- sound-dai = <&hdmi_tx>;
- };
- };
- };
-
- wifi32k: wifi32k {
- compatible = "pwm-clock";
- #clock-cells = <0>;
- clock-frequency = <32768>;
- pwms = <&pwm_ef 0 30518 0>; /* PWM_E at 32.768KHz */
- };
-};
-
-&arb {
- status = "okay";
-};
-
-&cec_AO {
- pinctrl-0 = <&cec_ao_a_h_pins>;
- pinctrl-names = "default";
- status = "disabled";
- hdmi-phandle = <&hdmi_tx>;
-};
-
-&cecb_AO {
- pinctrl-0 = <&cec_ao_b_h_pins>;
- pinctrl-names = "default";
- status = "okay";
- hdmi-phandle = <&hdmi_tx>;
-};
-
-&clkc_audio {
- status = "okay";
-};
-
-&cpu0 {
- cpu-supply = <&vddcpu>;
- operating-points-v2 = <&cpu_opp_table>;
- clocks = <&clkc CLKID_CPU_CLK>;
- clock-latency = <50000>;
-};
-
-&cpu1 {
- cpu-supply = <&vddcpu>;
- operating-points-v2 = <&cpu_opp_table>;
- clocks = <&clkc CLKID_CPU1_CLK>;
- clock-latency = <50000>;
-};
-
-&cpu2 {
- cpu-supply = <&vddcpu>;
- operating-points-v2 = <&cpu_opp_table>;
- clocks = <&clkc CLKID_CPU2_CLK>;
- clock-latency = <50000>;
-};
-
-&cpu3 {
- cpu-supply = <&vddcpu>;
- operating-points-v2 = <&cpu_opp_table>;
- clocks = <&clkc CLKID_CPU3_CLK>;
- clock-latency = <50000>;
-};
-
-ðmac {
- status = "okay";
- phy-handle = <&internal_ephy>;
- phy-mode = "rmii";
-};
-
-&frddr_a {
- status = "okay";
-};
-
-&frddr_b {
- status = "okay";
-};
-
-&frddr_c {
- status = "okay";
-};
-
-&hdmi_tx {
- status = "okay";
- pinctrl-0 = <&hdmitx_hpd_pins>, <&hdmitx_ddc_pins>;
- pinctrl-names = "default";
-};
-
-&hdmi_tx_tmds_port {
- hdmi_tx_tmds_out: endpoint {
- remote-endpoint = <&hdmi_connector_in>;
- };
-};
-
-&i2c3 {
- status = "okay";
- pinctrl-0 = <&i2c3_sda_a_pins>, <&i2c3_sck_a_pins>;
- pinctrl-names = "default";
-};
-
-&ir {
- status = "okay";
- pinctrl-0 = <&remote_input_ao_pins>;
- pinctrl-names = "default";
-};
-
-&pdm {
- pinctrl-0 = <&pdm_din0_z_pins>, <&pdm_dclk_z_pins>;
- pinctrl-names = "default";
- status = "okay";
-};
-
-&pwm_AO_ab {
- status = "okay";
- pinctrl-0 = <&pwm_ao_a_pins>;
- pinctrl-names = "default";
- clocks = <&xtal>;
- clock-names = "clkin0";
-};
-
-&pwm_AO_cd {
- pinctrl-0 = <&pwm_ao_d_e_pins>;
- pinctrl-names = "default";
- clocks = <&xtal>;
- clock-names = "clkin1";
- status = "okay";
-};
-
-&pwm_ef {
- status = "okay";
- pinctrl-0 = <&pwm_e_pins>;
- pinctrl-names = "default";
- clocks = <&xtal>;
- clock-names = "clkin0";
-};
-
-&saradc {
- status = "okay";
- vref-supply = <&vddio_ao1v8>;
-};
-
-/* SDIO */
-&sd_emmc_a {
- status = "okay";
- pinctrl-0 = <&sdio_pins>;
- pinctrl-1 = <&sdio_clk_gate_pins>;
- pinctrl-names = "default", "clk-gate";
- #address-cells = <1>;
- #size-cells = <0>;
-
- bus-width = <4>;
- cap-sd-highspeed;
- sd-uhs-sdr50;
- max-frequency = <100000000>;
-
- non-removable;
- disable-wp;
-
- /* WiFi firmware requires power to be kept while in suspend */
- keep-power-in-suspend;
-
- mmc-pwrseq = <&sdio_pwrseq>;
-
- vmmc-supply = <&vddao_3v3>;
- vqmmc-supply = <&vddio_ao1v8>;
-
- brcmf: wifi@1 {
- reg = <1>;
- compatible = "brcm,bcm4329-fmac";
- };
-};
-
-/* SD card */
-&sd_emmc_b {
- status = "okay";
- pinctrl-0 = <&sdcard_c_pins>;
- pinctrl-1 = <&sdcard_clk_gate_c_pins>;
- pinctrl-names = "default", "clk-gate";
-
- bus-width = <4>;
- cap-sd-highspeed;
- max-frequency = <50000000>;
- disable-wp;
-
- cd-gpios = <&gpio GPIOC_6 GPIO_ACTIVE_LOW>;
- vmmc-supply = <&vddao_3v3>;
- vqmmc-supply = <&vddao_3v3>;
-};
-
-/* eMMC */
-&sd_emmc_c {
- status = "okay";
- pinctrl-0 = <&emmc_ctrl_pins>, <&emmc_data_8b_pins>, <&emmc_ds_pins>;
- pinctrl-1 = <&emmc_clk_gate_pins>;
- pinctrl-names = "default", "clk-gate";
-
- bus-width = <8>;
- cap-mmc-highspeed;
- mmc-ddr-1_8v;
- mmc-hs200-1_8v;
- max-frequency = <200000000>;
- non-removable;
- disable-wp;
-
- mmc-pwrseq = <&emmc_pwrseq>;
- vmmc-supply = <&vddao_3v3>;
- vqmmc-supply = <&emmc_1v8>;
-};
-
-&tdmif_a {
- pinctrl-0 = <&tdm_a_dout0_pins>, <&tdm_a_fs_pins>, <&tdm_a_sclk_pins>;
- pinctrl-names = "default";
- status = "okay";
-
- assigned-clocks = <&clkc_audio AUD_CLKID_TDM_SCLK_PAD0>,
- <&clkc_audio AUD_CLKID_TDM_LRCLK_PAD0>;
- assigned-clock-parents = <&clkc_audio AUD_CLKID_MST_A_SCLK>,
- <&clkc_audio AUD_CLKID_MST_A_LRCLK>;
- assigned-clock-rates = <0>, <0>;
-};
-
-&tdmif_b {
- status = "okay";
-};
-
-&tdmin_a {
- status = "okay";
-};
-
-&tdmin_b {
- status = "okay";
-};
-
-&tdmout_a {
- status = "okay";
-};
-
-&tdmout_b {
- status = "okay";
-};
-
-&toddr_a {
- status = "okay";
-};
-
-&toddr_b {
- status = "okay";
-};
-
-&toddr_c {
- status = "okay";
-};
-
-&tohdmitx {
- status = "okay";
-};
-
-&uart_A {
- status = "okay";
- pinctrl-0 = <&uart_a_pins>, <&uart_a_cts_rts_pins>;
- pinctrl-names = "default";
- uart-has-rtscts;
-
- bluetooth {
- compatible = "brcm,bcm43438-bt";
- interrupt-parent = <&gpio_intc>;
- interrupts = <95 IRQ_TYPE_LEVEL_HIGH>;
- interrupt-names = "host-wakeup";
- shutdown-gpios = <&gpio GPIOX_17 GPIO_ACTIVE_HIGH>;
- max-speed = <2000000>;
- clocks = <&wifi32k>;
- clock-names = "lpo";
- vbat-supply = <&vddao_3v3>;
- vddio-supply = <&vddio_ao1v8>;
- };
-};
-
-/* Exposed via the on-board USB to Serial FT232RL IC */
-&uart_AO {
- status = "okay";
- pinctrl-0 = <&uart_ao_a_pins>;
- pinctrl-names = "default";
-};
-
-&usb {
- status = "okay";
- dr_mode = "otg";
-};
diff --git a/arch/arm/dts/meson-sm1.dtsi b/arch/arm/dts/meson-sm1.dtsi
deleted file mode 100644
index 56ca0ba..0000000
--- a/arch/arm/dts/meson-sm1.dtsi
+++ /dev/null
@@ -1,550 +0,0 @@
-// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
-/*
- * Copyright (c) 2019 BayLibre, SAS
- * Author: Neil Armstrong <narmstrong@baylibre.com>
- */
-
-#include "meson-g12-common.dtsi"
-#include <dt-bindings/clock/axg-audio-clkc.h>
-#include <dt-bindings/power/meson-sm1-power.h>
-#include <dt-bindings/reset/amlogic,meson-axg-audio-arb.h>
-#include <dt-bindings/reset/amlogic,meson-g12a-audio-reset.h>
-
-/ {
- compatible = "amlogic,sm1";
-
- tdmif_a: audio-controller-0 {
- compatible = "amlogic,axg-tdm-iface";
- #sound-dai-cells = <0>;
- sound-name-prefix = "TDM_A";
- clocks = <&clkc_audio AUD_CLKID_MST_A_MCLK>,
- <&clkc_audio AUD_CLKID_MST_A_SCLK>,
- <&clkc_audio AUD_CLKID_MST_A_LRCLK>;
- clock-names = "mclk", "sclk", "lrclk";
- status = "disabled";
- };
-
- tdmif_b: audio-controller-1 {
- compatible = "amlogic,axg-tdm-iface";
- #sound-dai-cells = <0>;
- sound-name-prefix = "TDM_B";
- clocks = <&clkc_audio AUD_CLKID_MST_B_MCLK>,
- <&clkc_audio AUD_CLKID_MST_B_SCLK>,
- <&clkc_audio AUD_CLKID_MST_B_LRCLK>;
- clock-names = "mclk", "sclk", "lrclk";
- status = "disabled";
- };
-
- tdmif_c: audio-controller-2 {
- compatible = "amlogic,axg-tdm-iface";
- #sound-dai-cells = <0>;
- sound-name-prefix = "TDM_C";
- clocks = <&clkc_audio AUD_CLKID_MST_C_MCLK>,
- <&clkc_audio AUD_CLKID_MST_C_SCLK>,
- <&clkc_audio AUD_CLKID_MST_C_LRCLK>;
- clock-names = "mclk", "sclk", "lrclk";
- status = "disabled";
- };
-
- cpus {
- #address-cells = <0x2>;
- #size-cells = <0x0>;
-
- cpu0: cpu@0 {
- device_type = "cpu";
- compatible = "arm,cortex-a55";
- reg = <0x0 0x0>;
- enable-method = "psci";
- next-level-cache = <&l2>;
- #cooling-cells = <2>;
- };
-
- cpu1: cpu@1 {
- device_type = "cpu";
- compatible = "arm,cortex-a55";
- reg = <0x0 0x1>;
- enable-method = "psci";
- next-level-cache = <&l2>;
- #cooling-cells = <2>;
- };
-
- cpu2: cpu@2 {
- device_type = "cpu";
- compatible = "arm,cortex-a55";
- reg = <0x0 0x2>;
- enable-method = "psci";
- next-level-cache = <&l2>;
- #cooling-cells = <2>;
- };
-
- cpu3: cpu@3 {
- device_type = "cpu";
- compatible = "arm,cortex-a55";
- reg = <0x0 0x3>;
- enable-method = "psci";
- next-level-cache = <&l2>;
- #cooling-cells = <2>;
- };
-
- l2: l2-cache0 {
- compatible = "cache";
- cache-level = <2>;
- };
- };
-
- cpu_opp_table: opp-table {
- compatible = "operating-points-v2";
- opp-shared;
-
- opp-1000000000 {
- opp-hz = /bits/ 64 <1000000000>;
- opp-microvolt = <770000>;
- };
-
- opp-1200000000 {
- opp-hz = /bits/ 64 <1200000000>;
- opp-microvolt = <780000>;
- };
-
- opp-1404000000 {
- opp-hz = /bits/ 64 <1404000000>;
- opp-microvolt = <790000>;
- };
-
- opp-1500000000 {
- opp-hz = /bits/ 64 <1500000000>;
- opp-microvolt = <800000>;
- };
-
- opp-1608000000 {
- opp-hz = /bits/ 64 <1608000000>;
- opp-microvolt = <810000>;
- };
-
- opp-1704000000 {
- opp-hz = /bits/ 64 <1704000000>;
- opp-microvolt = <850000>;
- };
-
- opp-1800000000 {
- opp-hz = /bits/ 64 <1800000000>;
- opp-microvolt = <900000>;
- };
-
- opp-1908000000 {
- opp-hz = /bits/ 64 <1908000000>;
- opp-microvolt = <950000>;
- };
- };
-};
-
-&apb {
- audio: bus@60000 {
- compatible = "simple-bus";
- reg = <0x0 0x60000 0x0 0x1000>;
- #address-cells = <2>;
- #size-cells = <2>;
- ranges = <0x0 0x0 0x0 0x60000 0x0 0x1000>;
-
- clkc_audio: clock-controller@0 {
- status = "disabled";
- compatible = "amlogic,sm1-audio-clkc";
- reg = <0x0 0x0 0x0 0xb4>;
- #clock-cells = <1>;
- #reset-cells = <1>;
-
- clocks = <&clkc CLKID_AUDIO>,
- <&clkc CLKID_MPLL0>,
- <&clkc CLKID_MPLL1>,
- <&clkc CLKID_MPLL2>,
- <&clkc CLKID_MPLL3>,
- <&clkc CLKID_HIFI_PLL>,
- <&clkc CLKID_FCLK_DIV3>,
- <&clkc CLKID_FCLK_DIV4>,
- <&clkc CLKID_FCLK_DIV5>;
- clock-names = "pclk",
- "mst_in0",
- "mst_in1",
- "mst_in2",
- "mst_in3",
- "mst_in4",
- "mst_in5",
- "mst_in6",
- "mst_in7";
-
- resets = <&reset RESET_AUDIO>;
- };
-
- toddr_a: audio-controller@100 {
- compatible = "amlogic,sm1-toddr",
- "amlogic,axg-toddr";
- reg = <0x0 0x100 0x0 0x2c>;
- #sound-dai-cells = <0>;
- sound-name-prefix = "TODDR_A";
- interrupts = <GIC_SPI 148 IRQ_TYPE_EDGE_RISING>;
- clocks = <&clkc_audio AUD_CLKID_TODDR_A>;
- resets = <&arb AXG_ARB_TODDR_A>,
- <&clkc_audio AUD_RESET_TODDR_A>;
- reset-names = "arb", "rst";
- amlogic,fifo-depth = <8192>;
- status = "disabled";
- };
-
- toddr_b: audio-controller@140 {
- compatible = "amlogic,sm1-toddr",
- "amlogic,axg-toddr";
- reg = <0x0 0x140 0x0 0x2c>;
- #sound-dai-cells = <0>;
- sound-name-prefix = "TODDR_B";
- interrupts = <GIC_SPI 149 IRQ_TYPE_EDGE_RISING>;
- clocks = <&clkc_audio AUD_CLKID_TODDR_B>;
- resets = <&arb AXG_ARB_TODDR_B>,
- <&clkc_audio AUD_RESET_TODDR_B>;
- reset-names = "arb", "rst";
- amlogic,fifo-depth = <256>;
- status = "disabled";
- };
-
- toddr_c: audio-controller@180 {
- compatible = "amlogic,sm1-toddr",
- "amlogic,axg-toddr";
- reg = <0x0 0x180 0x0 0x2c>;
- #sound-dai-cells = <0>;
- sound-name-prefix = "TODDR_C";
- interrupts = <GIC_SPI 150 IRQ_TYPE_EDGE_RISING>;
- clocks = <&clkc_audio AUD_CLKID_TODDR_C>;
- resets = <&arb AXG_ARB_TODDR_C>,
- <&clkc_audio AUD_RESET_TODDR_C>;
- reset-names = "arb", "rst";
- amlogic,fifo-depth = <256>;
- status = "disabled";
- };
-
- frddr_a: audio-controller@1c0 {
- compatible = "amlogic,sm1-frddr",
- "amlogic,axg-frddr";
- reg = <0x0 0x1c0 0x0 0x2c>;
- #sound-dai-cells = <0>;
- sound-name-prefix = "FRDDR_A";
- interrupts = <GIC_SPI 152 IRQ_TYPE_EDGE_RISING>;
- clocks = <&clkc_audio AUD_CLKID_FRDDR_A>;
- resets = <&arb AXG_ARB_FRDDR_A>,
- <&clkc_audio AUD_RESET_FRDDR_A>;
- reset-names = "arb", "rst";
- amlogic,fifo-depth = <512>;
- status = "disabled";
- };
-
- frddr_b: audio-controller@200 {
- compatible = "amlogic,sm1-frddr",
- "amlogic,axg-frddr";
- reg = <0x0 0x200 0x0 0x2c>;
- #sound-dai-cells = <0>;
- sound-name-prefix = "FRDDR_B";
- interrupts = <GIC_SPI 153 IRQ_TYPE_EDGE_RISING>;
- clocks = <&clkc_audio AUD_CLKID_FRDDR_B>;
- resets = <&arb AXG_ARB_FRDDR_B>,
- <&clkc_audio AUD_RESET_FRDDR_B>;
- reset-names = "arb", "rst";
- amlogic,fifo-depth = <256>;
- status = "disabled";
- };
-
- frddr_c: audio-controller@240 {
- compatible = "amlogic,sm1-frddr",
- "amlogic,axg-frddr";
- reg = <0x0 0x240 0x0 0x2c>;
- #sound-dai-cells = <0>;
- sound-name-prefix = "FRDDR_C";
- interrupts = <GIC_SPI 154 IRQ_TYPE_EDGE_RISING>;
- clocks = <&clkc_audio AUD_CLKID_FRDDR_C>;
- resets = <&arb AXG_ARB_FRDDR_C>,
- <&clkc_audio AUD_RESET_FRDDR_C>;
- reset-names = "arb", "rst";
- amlogic,fifo-depth = <256>;
- status = "disabled";
- };
-
- arb: reset-controller@280 {
- status = "disabled";
- compatible = "amlogic,meson-sm1-audio-arb";
- reg = <0x0 0x280 0x0 0x4>;
- #reset-cells = <1>;
- clocks = <&clkc_audio AUD_CLKID_DDR_ARB>;
- };
-
- tdmin_a: audio-controller@300 {
- compatible = "amlogic,sm1-tdmin",
- "amlogic,axg-tdmin";
- reg = <0x0 0x300 0x0 0x40>;
- sound-name-prefix = "TDMIN_A";
- resets = <&clkc_audio AUD_RESET_TDMIN_A>;
- clocks = <&clkc_audio AUD_CLKID_TDMIN_A>,
- <&clkc_audio AUD_CLKID_TDMIN_A_SCLK>,
- <&clkc_audio AUD_CLKID_TDMIN_A_SCLK_SEL>,
- <&clkc_audio AUD_CLKID_TDMIN_A_LRCLK>,
- <&clkc_audio AUD_CLKID_TDMIN_A_LRCLK>;
- clock-names = "pclk", "sclk", "sclk_sel",
- "lrclk", "lrclk_sel";
- status = "disabled";
- };
-
- tdmin_b: audio-controller@340 {
- compatible = "amlogic,sm1-tdmin",
- "amlogic,axg-tdmin";
- reg = <0x0 0x340 0x0 0x40>;
- sound-name-prefix = "TDMIN_B";
- resets = <&clkc_audio AUD_RESET_TDMIN_B>;
- clocks = <&clkc_audio AUD_CLKID_TDMIN_B>,
- <&clkc_audio AUD_CLKID_TDMIN_B_SCLK>,
- <&clkc_audio AUD_CLKID_TDMIN_B_SCLK_SEL>,
- <&clkc_audio AUD_CLKID_TDMIN_B_LRCLK>,
- <&clkc_audio AUD_CLKID_TDMIN_B_LRCLK>;
- clock-names = "pclk", "sclk", "sclk_sel",
- "lrclk", "lrclk_sel";
- status = "disabled";
- };
-
- tdmin_c: audio-controller@380 {
- compatible = "amlogic,sm1-tdmin",
- "amlogic,axg-tdmin";
- reg = <0x0 0x380 0x0 0x40>;
- sound-name-prefix = "TDMIN_C";
- resets = <&clkc_audio AUD_RESET_TDMIN_C>;
- clocks = <&clkc_audio AUD_CLKID_TDMIN_C>,
- <&clkc_audio AUD_CLKID_TDMIN_C_SCLK>,
- <&clkc_audio AUD_CLKID_TDMIN_C_SCLK_SEL>,
- <&clkc_audio AUD_CLKID_TDMIN_C_LRCLK>,
- <&clkc_audio AUD_CLKID_TDMIN_C_LRCLK>;
- clock-names = "pclk", "sclk", "sclk_sel",
- "lrclk", "lrclk_sel";
- status = "disabled";
- };
-
- tdmin_lb: audio-controller@3c0 {
- compatible = "amlogic,sm1-tdmin",
- "amlogic,axg-tdmin";
- reg = <0x0 0x3c0 0x0 0x40>;
- sound-name-prefix = "TDMIN_LB";
- resets = <&clkc_audio AUD_RESET_TDMIN_LB>;
- clocks = <&clkc_audio AUD_CLKID_TDMIN_LB>,
- <&clkc_audio AUD_CLKID_TDMIN_LB_SCLK>,
- <&clkc_audio AUD_CLKID_TDMIN_LB_SCLK_SEL>,
- <&clkc_audio AUD_CLKID_TDMIN_LB_LRCLK>,
- <&clkc_audio AUD_CLKID_TDMIN_LB_LRCLK>;
- clock-names = "pclk", "sclk", "sclk_sel",
- "lrclk", "lrclk_sel";
- status = "disabled";
- };
-
- spdifin: audio-controller@400 {
- compatible = "amlogic,g12a-spdifin",
- "amlogic,axg-spdifin";
- reg = <0x0 0x400 0x0 0x30>;
- #sound-dai-cells = <0>;
- sound-name-prefix = "SPDIFIN";
- interrupts = <GIC_SPI 151 IRQ_TYPE_EDGE_RISING>;
- clocks = <&clkc_audio AUD_CLKID_SPDIFIN>,
- <&clkc_audio AUD_CLKID_SPDIFIN_CLK>;
- clock-names = "pclk", "refclk";
- resets = <&clkc_audio AUD_RESET_SPDIFIN>;
- status = "disabled";
- };
-
- spdifout_a: audio-controller@480 {
- compatible = "amlogic,g12a-spdifout",
- "amlogic,axg-spdifout";
- reg = <0x0 0x480 0x0 0x50>;
- #sound-dai-cells = <0>;
- sound-name-prefix = "SPDIFOUT_A";
- clocks = <&clkc_audio AUD_CLKID_SPDIFOUT>,
- <&clkc_audio AUD_CLKID_SPDIFOUT_CLK>;
- clock-names = "pclk", "mclk";
- resets = <&clkc_audio AUD_RESET_SPDIFOUT>;
- status = "disabled";
- };
-
- tdmout_a: audio-controller@500 {
- compatible = "amlogic,sm1-tdmout";
- reg = <0x0 0x500 0x0 0x40>;
- sound-name-prefix = "TDMOUT_A";
- resets = <&clkc_audio AUD_RESET_TDMOUT_A>;
- clocks = <&clkc_audio AUD_CLKID_TDMOUT_A>,
- <&clkc_audio AUD_CLKID_TDMOUT_A_SCLK>,
- <&clkc_audio AUD_CLKID_TDMOUT_A_SCLK_SEL>,
- <&clkc_audio AUD_CLKID_TDMOUT_A_LRCLK>,
- <&clkc_audio AUD_CLKID_TDMOUT_A_LRCLK>;
- clock-names = "pclk", "sclk", "sclk_sel",
- "lrclk", "lrclk_sel";
- status = "disabled";
- };
-
- tdmout_b: audio-controller@540 {
- compatible = "amlogic,sm1-tdmout";
- reg = <0x0 0x540 0x0 0x40>;
- sound-name-prefix = "TDMOUT_B";
- resets = <&clkc_audio AUD_RESET_TDMOUT_B>;
- clocks = <&clkc_audio AUD_CLKID_TDMOUT_B>,
- <&clkc_audio AUD_CLKID_TDMOUT_B_SCLK>,
- <&clkc_audio AUD_CLKID_TDMOUT_B_SCLK_SEL>,
- <&clkc_audio AUD_CLKID_TDMOUT_B_LRCLK>,
- <&clkc_audio AUD_CLKID_TDMOUT_B_LRCLK>;
- clock-names = "pclk", "sclk", "sclk_sel",
- "lrclk", "lrclk_sel";
- status = "disabled";
- };
-
- tdmout_c: audio-controller@580 {
- compatible = "amlogic,sm1-tdmout";
- reg = <0x0 0x580 0x0 0x40>;
- sound-name-prefix = "TDMOUT_C";
- resets = <&clkc_audio AUD_RESET_TDMOUT_C>;
- clocks = <&clkc_audio AUD_CLKID_TDMOUT_C>,
- <&clkc_audio AUD_CLKID_TDMOUT_C_SCLK>,
- <&clkc_audio AUD_CLKID_TDMOUT_C_SCLK_SEL>,
- <&clkc_audio AUD_CLKID_TDMOUT_C_LRCLK>,
- <&clkc_audio AUD_CLKID_TDMOUT_C_LRCLK>;
- clock-names = "pclk", "sclk", "sclk_sel",
- "lrclk", "lrclk_sel";
- status = "disabled";
- };
-
- toacodec: audio-controller@740 {
- compatible = "amlogic,sm1-toacodec",
- "amlogic,g12a-toacodec";
- reg = <0x0 0x740 0x0 0x4>;
- #sound-dai-cells = <1>;
- sound-name-prefix = "TOACODEC";
- resets = <&clkc_audio AUD_RESET_TOACODEC>;
- status = "disabled";
- };
-
- tohdmitx: audio-controller@744 {
- compatible = "amlogic,sm1-tohdmitx",
- "amlogic,g12a-tohdmitx";
- reg = <0x0 0x744 0x0 0x4>;
- #sound-dai-cells = <1>;
- sound-name-prefix = "TOHDMITX";
- resets = <&clkc_audio AUD_RESET_TOHDMITX>;
- status = "disabled";
- };
-
- toddr_d: audio-controller@840 {
- compatible = "amlogic,sm1-toddr",
- "amlogic,axg-toddr";
- reg = <0x0 0x840 0x0 0x2c>;
- #sound-dai-cells = <0>;
- sound-name-prefix = "TODDR_D";
- interrupts = <GIC_SPI 49 IRQ_TYPE_EDGE_RISING>;
- clocks = <&clkc_audio AUD_CLKID_TODDR_D>;
- resets = <&arb AXG_ARB_TODDR_D>,
- <&clkc_audio AUD_RESET_TODDR_D>;
- reset-names = "arb", "rst";
- amlogic,fifo-depth = <256>;
- status = "disabled";
- };
-
- frddr_d: audio-controller@880 {
- compatible = "amlogic,sm1-frddr",
- "amlogic,axg-frddr";
- reg = <0x0 0x880 0x0 0x2c>;
- #sound-dai-cells = <0>;
- sound-name-prefix = "FRDDR_D";
- interrupts = <GIC_SPI 50 IRQ_TYPE_EDGE_RISING>;
- clocks = <&clkc_audio AUD_CLKID_FRDDR_D>;
- resets = <&arb AXG_ARB_FRDDR_D>,
- <&clkc_audio AUD_RESET_FRDDR_D>;
- reset-names = "arb", "rst";
- amlogic,fifo-depth = <256>;
- status = "disabled";
- };
- };
-
- pdm: audio-controller@61000 {
- compatible = "amlogic,sm1-pdm",
- "amlogic,axg-pdm";
- reg = <0x0 0x61000 0x0 0x34>;
- #sound-dai-cells = <0>;
- sound-name-prefix = "PDM";
- clocks = <&clkc_audio AUD_CLKID_PDM>,
- <&clkc_audio AUD_CLKID_PDM_DCLK>,
- <&clkc_audio AUD_CLKID_PDM_SYSCLK>;
- clock-names = "pclk", "dclk", "sysclk";
- resets = <&clkc_audio AUD_RESET_PDM>;
- status = "disabled";
- };
-};
-
-&cecb_AO {
- compatible = "amlogic,meson-sm1-ao-cec";
-};
-
-&clk_msr {
- compatible = "amlogic,meson-sm1-clk-measure";
-};
-
-
-&clkc {
- compatible = "amlogic,sm1-clkc";
-};
-
-&cpu_thermal {
- cooling-maps {
- map0 {
- trip = <&cpu_passive>;
- cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
- <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
- <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
- <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
- };
-
- map1 {
- trip = <&cpu_hot>;
- cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
- <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
- <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
- <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
- };
- };
-};
-
-ðmac {
- power-domains = <&pwrc PWRC_SM1_ETH_ID>;
-};
-
-&gpio_intc {
- compatible = "amlogic,meson-sm1-gpio-intc",
- "amlogic,meson-gpio-intc";
-};
-
-&pcie {
- power-domains = <&pwrc PWRC_SM1_PCIE_ID>;
-};
-
-&pmu {
- compatible = "amlogic,sm1-ddr-pmu";
-};
-
-&pwrc {
- compatible = "amlogic,meson-sm1-pwrc";
-};
-
-&simplefb_cvbs {
- power-domains = <&pwrc PWRC_SM1_VPU_ID>;
-};
-
-&simplefb_hdmi {
- power-domains = <&pwrc PWRC_SM1_VPU_ID>;
-};
-
-&vdec {
- compatible = "amlogic,sm1-vdec";
-};
-
-&vpu {
- power-domains = <&pwrc PWRC_SM1_VPU_ID>;
-};
-
-&usb {
- power-domains = <&pwrc PWRC_SM1_USB_ID>;
-};
diff --git a/arch/arm/dts/rk3328-evb-u-boot.dtsi b/arch/arm/dts/rk3328-evb-u-boot.dtsi
index 12b68df..38ad3cc 100644
--- a/arch/arm/dts/rk3328-evb-u-boot.dtsi
+++ b/arch/arm/dts/rk3328-evb-u-boot.dtsi
@@ -44,3 +44,7 @@
/* Integrated PHY unsupported by U-Boot */
status = "broken";
};
+
+&vcc_sd {
+ bootph-pre-ram;
+};
diff --git a/arch/arm/dts/rk3328-evb.dts b/arch/arm/dts/rk3328-evb.dts
index ff6b466..1eef550 100644
--- a/arch/arm/dts/rk3328-evb.dts
+++ b/arch/arm/dts/rk3328-evb.dts
@@ -11,6 +11,7 @@
compatible = "rockchip,rk3328-evb", "rockchip,rk3328";
aliases {
+ ethernet0 = &gmac2phy;
mmc0 = &sdmmc;
mmc1 = &sdio;
mmc2 = &emmc;
diff --git a/arch/arm/dts/rk3328-nanopi-r2c-plus-u-boot.dtsi b/arch/arm/dts/rk3328-nanopi-r2c-plus-u-boot.dtsi
index f8adb9e..1dc3c02 100644
--- a/arch/arm/dts/rk3328-nanopi-r2c-plus-u-boot.dtsi
+++ b/arch/arm/dts/rk3328-nanopi-r2c-plus-u-boot.dtsi
@@ -1,9 +1,3 @@
// SPDX-License-Identifier: GPL-2.0-or-later
#include "rk3328-nanopi-r2c-u-boot.dtsi"
-
-/ {
- chosen {
- u-boot,spl-boot-order = "same-as-spl", &sdmmc, &emmc;
- };
-};
diff --git a/arch/arm/dts/rk3328-nanopi-r2s-u-boot.dtsi b/arch/arm/dts/rk3328-nanopi-r2s-u-boot.dtsi
index 78d37ab..4fa170e 100644
--- a/arch/arm/dts/rk3328-nanopi-r2s-u-boot.dtsi
+++ b/arch/arm/dts/rk3328-nanopi-r2s-u-boot.dtsi
@@ -6,35 +6,23 @@
#include "rk3328-u-boot.dtsi"
#include "rk3328-sdram-ddr4-666.dtsi"
-/ {
- chosen {
- u-boot,spl-boot-order = "same-as-spl", &sdmmc, &emmc;
- };
-};
-&gpio0 {
+&gpio1 {
bootph-pre-ram;
};
-&pinctrl {
- bootph-pre-ram;
+&sdio_vcc_pin {
+ bootph-all;
};
-&sdmmc0m1_pin {
- bootph-pre-ram;
+&usb20_otg {
+ dr_mode = "peripheral";
};
-&pcfg_pull_up_4ma {
+&vcc_io_sdio {
bootph-pre-ram;
};
-/* Need this and all the pinctrl/gpio stuff above to set pinmux */
&vcc_sd {
bootph-pre-ram;
};
-
-&gmac2io {
- snps,reset-gpio = <&gpio1 RK_PC2 GPIO_ACTIVE_LOW>;
- snps,reset-active-low;
- snps,reset-delays-us = <0 10000 50000>;
-};
diff --git a/arch/arm/dts/rk3328-nanopi-r2s.dts b/arch/arm/dts/rk3328-nanopi-r2s.dts
index 3857d48..a4399da 100644
--- a/arch/arm/dts/rk3328-nanopi-r2s.dts
+++ b/arch/arm/dts/rk3328-nanopi-r2s.dts
@@ -14,6 +14,7 @@
compatible = "friendlyarm,nanopi-r2s", "rockchip,rk3328";
aliases {
+ ethernet0 = &gmac2io;
ethernet1 = &rtl8153;
mmc0 = &sdmmc;
};
@@ -34,7 +35,7 @@
pinctrl-0 = <&reset_button_pin>;
pinctrl-names = "default";
- reset {
+ key-reset {
label = "reset";
gpios = <&gpio0 RK_PA0 GPIO_ACTIVE_LOW>;
linux,code = <KEY_RESTART>;
diff --git a/arch/arm/dts/rk3328-orangepi-r1-plus-lts-u-boot.dtsi b/arch/arm/dts/rk3328-orangepi-r1-plus-lts-u-boot.dtsi
index ebe33e4..0a9423c 100644
--- a/arch/arm/dts/rk3328-orangepi-r1-plus-lts-u-boot.dtsi
+++ b/arch/arm/dts/rk3328-orangepi-r1-plus-lts-u-boot.dtsi
@@ -6,41 +6,37 @@
#include "rk3328-u-boot.dtsi"
#include "rk3328-sdram-lpddr3-666.dtsi"
-/ {
- chosen {
- u-boot,spl-boot-order = "same-as-spl", &sdmmc, &emmc;
- };
-};
-&gpio0 {
+&spi0 {
bootph-pre-ram;
+ bootph-some-ram;
+
+ flash@0 {
+ bootph-pre-ram;
+ bootph-some-ram;
+ };
};
-&pinctrl {
+&spi0m2_clk {
bootph-pre-ram;
};
-&sdmmc0m1_pin {
+&spi0m2_cs0 {
bootph-pre-ram;
};
-&pcfg_pull_up_4ma {
+&spi0m2_rx {
bootph-pre-ram;
};
-/* Need this and all the pinctrl/gpio stuff above to set pinmux */
-&vcc_sd {
+&spi0m2_tx {
bootph-pre-ram;
};
-&gmac2io {
- snps,reset-gpio = <&gpio1 RK_PC2 GPIO_ACTIVE_LOW>;
- snps,reset-active-low;
- snps,reset-delays-us = <0 10000 50000>;
+&usb20_otg {
+ dr_mode = "peripheral";
};
-&spi0 {
- spi_flash: spiflash@0 {
- bootph-all;
- };
+&vcc_sd {
+ bootph-pre-ram;
};
diff --git a/arch/arm/dts/rk3328-orangepi-r1-plus-lts.dts b/arch/arm/dts/rk3328-orangepi-r1-plus-lts.dts
index 5d7d567..4237f2e 100644
--- a/arch/arm/dts/rk3328-orangepi-r1-plus-lts.dts
+++ b/arch/arm/dts/rk3328-orangepi-r1-plus-lts.dts
@@ -26,9 +26,11 @@
compatible = "ethernet-phy-ieee802.3-c22";
reg = <0>;
+ motorcomm,auto-sleep-disabled;
motorcomm,clk-out-frequency-hz = <125000000>;
motorcomm,keep-pll-enabled;
- motorcomm,auto-sleep-disabled;
+ motorcomm,rx-clk-drv-microamp = <5020>;
+ motorcomm,rx-data-drv-microamp = <5020>;
pinctrl-0 = <ð_phy_reset_pin>;
pinctrl-names = "default";
diff --git a/arch/arm/dts/rk3328-orangepi-r1-plus-u-boot.dtsi b/arch/arm/dts/rk3328-orangepi-r1-plus-u-boot.dtsi
index 637c70a..1096821 100644
--- a/arch/arm/dts/rk3328-orangepi-r1-plus-u-boot.dtsi
+++ b/arch/arm/dts/rk3328-orangepi-r1-plus-u-boot.dtsi
@@ -6,41 +6,37 @@
#include "rk3328-u-boot.dtsi"
#include "rk3328-sdram-ddr4-666.dtsi"
-/ {
- chosen {
- u-boot,spl-boot-order = "same-as-spl", &sdmmc, &emmc;
- };
-};
-&gpio0 {
+&spi0 {
bootph-pre-ram;
+ bootph-some-ram;
+
+ flash@0 {
+ bootph-pre-ram;
+ bootph-some-ram;
+ };
};
-&pinctrl {
+&spi0m2_clk {
bootph-pre-ram;
};
-&sdmmc0m1_pin {
+&spi0m2_cs0 {
bootph-pre-ram;
};
-&pcfg_pull_up_4ma {
+&spi0m2_rx {
bootph-pre-ram;
};
-/* Need this and all the pinctrl/gpio stuff above to set pinmux */
-&vcc_sd {
+&spi0m2_tx {
bootph-pre-ram;
};
-&gmac2io {
- snps,reset-gpio = <&gpio1 RK_PC2 GPIO_ACTIVE_LOW>;
- snps,reset-active-low;
- snps,reset-delays-us = <0 10000 50000>;
+&usb20_otg {
+ dr_mode = "peripheral";
};
-&spi0 {
- spi_flash: spiflash@0 {
- bootph-all;
- };
+&vcc_sd {
+ bootph-pre-ram;
};
diff --git a/arch/arm/dts/rk3328-orangepi-r1-plus.dts b/arch/arm/dts/rk3328-orangepi-r1-plus.dts
index dc83d74..f206629 100644
--- a/arch/arm/dts/rk3328-orangepi-r1-plus.dts
+++ b/arch/arm/dts/rk3328-orangepi-r1-plus.dts
@@ -15,6 +15,7 @@
compatible = "xunlong,orangepi-r1-plus", "rockchip,rk3328";
aliases {
+ ethernet0 = &gmac2io;
ethernet1 = &rtl8153;
mmc0 = &sdmmc;
};
diff --git a/arch/arm/dts/rk3328-roc-cc-u-boot.dtsi b/arch/arm/dts/rk3328-roc-cc-u-boot.dtsi
index 2062f34..582d6ba 100644
--- a/arch/arm/dts/rk3328-roc-cc-u-boot.dtsi
+++ b/arch/arm/dts/rk3328-roc-cc-u-boot.dtsi
@@ -5,11 +5,8 @@
#include "rk3328-u-boot.dtsi"
#include "rk3328-sdram-ddr4-666.dtsi"
-/ {
- chosen {
- u-boot,spl-boot-order = "same-as-spl", &sdmmc, &emmc;
- };
+/ {
smbios {
compatible = "u-boot,sysinfo-smbios";
@@ -32,23 +29,10 @@
};
};
-&gpio0 {
- bootph-pre-ram;
-};
-
-&pinctrl {
- bootph-pre-ram;
+&usb20_otg {
+ hnp-srp-disable;
};
-&sdmmc0m1_pin {
- bootph-pre-ram;
-};
-
-&pcfg_pull_up_4ma {
- bootph-pre-ram;
-};
-
-/* Need this and all the pinctrl/gpio stuff above to set pinmux */
&vcc_sd {
bootph-pre-ram;
};
diff --git a/arch/arm/dts/rk3328-roc-cc.dts b/arch/arm/dts/rk3328-roc-cc.dts
index aa22a0c..414897a 100644
--- a/arch/arm/dts/rk3328-roc-cc.dts
+++ b/arch/arm/dts/rk3328-roc-cc.dts
@@ -11,6 +11,7 @@
compatible = "firefly,roc-rk3328-cc", "rockchip,rk3328";
aliases {
+ ethernet0 = &gmac2io;
mmc0 = &sdmmc;
mmc1 = &emmc;
};
@@ -96,7 +97,6 @@
linux,default-trigger = "heartbeat";
gpios = <&rk805 1 GPIO_ACTIVE_LOW>;
default-state = "on";
- mode = <0x23>;
};
user_led: led-1 {
@@ -104,7 +104,6 @@
linux,default-trigger = "mmc1";
gpios = <&rk805 0 GPIO_ACTIVE_LOW>;
default-state = "off";
- mode = <0x05>;
};
};
};
diff --git a/arch/arm/dts/rk3328-rock-pi-e-u-boot.dtsi b/arch/arm/dts/rk3328-rock-pi-e-u-boot.dtsi
index 1f220c6..d314bfa 100644
--- a/arch/arm/dts/rk3328-rock-pi-e-u-boot.dtsi
+++ b/arch/arm/dts/rk3328-rock-pi-e-u-boot.dtsi
@@ -29,23 +29,15 @@
};
};
-&gpio0 {
- bootph-pre-ram;
+&u2phy_host {
+ phy-supply = <&vcc_host_5v>;
};
-&pinctrl {
- bootph-pre-ram;
+&vcc_host_5v {
+ /delete-property/ regulator-always-on;
+ /delete-property/ regulator-boot-on;
};
-&sdmmc0m1_pin {
- bootph-pre-ram;
-};
-
-&pcfg_pull_up_4ma {
- bootph-pre-ram;
-};
-
-/* Need this and all the pinctrl/gpio stuff above to set pinmux */
&vcc_sd {
bootph-pre-ram;
};
diff --git a/arch/arm/dts/rk3328-rock-pi-e.dts b/arch/arm/dts/rk3328-rock-pi-e.dts
index 018a3a5..3cda6c6 100644
--- a/arch/arm/dts/rk3328-rock-pi-e.dts
+++ b/arch/arm/dts/rk3328-rock-pi-e.dts
@@ -21,6 +21,8 @@
compatible = "radxa,rockpi-e", "rockchip,rk3328";
aliases {
+ ethernet0 = &gmac2io;
+ ethernet1 = &gmac2phy;
mmc0 = &sdmmc;
mmc1 = &emmc;
};
@@ -180,6 +182,59 @@
status = "okay";
};
+&gpio0 {
+ gpio-line-names =
+ /* GPIO0_A0 - A7 */
+ "", "", "", "", "", "", "", "",
+ /* GPIO0_B0 - B7 */
+ "", "", "", "", "", "", "", "",
+ /* GPIO0_C0 - C7 */
+ "", "", "", "", "", "", "", "",
+ /* GPIO0_D0 - D7 */
+ "", "", "", "pin-15 [GPIO0_D3]", "", "", "", "";
+};
+
+&gpio1 {
+ gpio-line-names =
+ /* GPIO1_A0 - A7 */
+ "", "", "", "", "", "", "", "",
+ /* GPIO1_B0 - B7 */
+ "", "", "", "", "", "", "", "",
+ /* GPIO1_C0 - C7 */
+ "", "", "", "", "", "", "", "",
+ /* GPIO1_D0 - D7 */
+ "", "", "", "", "pin-07 [GPIO1_D4]", "", "", "";
+};
+
+&gpio2 {
+ gpio-line-names =
+ /* GPIO2_A0 - A7 */
+ "pin-08 [GPIO2_A0]", "pin-10 [GPIO2_A1]", "pin-11 [GPIO2_A2]",
+ "pin-13 [GPIO2-A3]", "pin-27 [GPIO2_A4]", "pin-28 [GPIO2_A5]",
+ "pin-33 [GPIO2_A6]", "",
+ /* GPIO2_B0 - B7 */
+ "", "", "", "", "pin-26 [GPIO2_B4]", "", "", "pin-36 [GPIO2_B7]",
+ /* GPIO2_C0 - C7 */
+ "pin-32 [GPIO2_C0]", "pin-35 [GPIO2_C1]", "pin-12 [GPIO2_C2]",
+ "pin-38 [GPIO2_C3]", "pin-29 [GPIO2_C4]", "pin-31 [GPIO2_C5]",
+ "pin-37 [GPIO2_C6]", "pin-40 [GPIO2_C7]",
+ /* GPIO2_D0 - D7 */
+ "", "", "", "", "", "", "", "";
+};
+
+&gpio3 {
+ gpio-line-names =
+ /* GPIO3_A0 - A7 */
+ "pin-23 [GPIO3_A0]", "pin-19 [GPIO3_A1]", "pin-21 [GPIO3_A2]",
+ "", "pin-03 [GPIO3_A4]", "", "pin-05 [GPIO3_A6]", "",
+ /* GPIO3_B0 - B7 */
+ "pin-24 [GPIO3_B0]", "", "", "", "", "", "", "",
+ /* GPIO3_C0 - C7 */
+ "", "", "", "", "", "", "", "",
+ /* GPIO3_D0 - D7 */
+ "", "", "", "", "", "", "", "";
+};
+
&i2c1 {
status = "okay";
diff --git a/arch/arm/dts/rk3328-rock64-u-boot.dtsi b/arch/arm/dts/rk3328-rock64-u-boot.dtsi
index 6904515..551cff6 100644
--- a/arch/arm/dts/rk3328-rock64-u-boot.dtsi
+++ b/arch/arm/dts/rk3328-rock64-u-boot.dtsi
@@ -5,11 +5,8 @@
#include "rk3328-u-boot.dtsi"
#include "rk3328-sdram-lpddr3-1600.dtsi"
-/ {
- chosen {
- u-boot,spl-boot-order = "same-as-spl", &sdmmc, &emmc;
- };
+/ {
smbios {
compatible = "u-boot,sysinfo-smbios";
@@ -32,29 +29,36 @@
};
};
-&gpio0 {
+&spi0 {
bootph-pre-ram;
+ bootph-some-ram;
+
+ flash@0 {
+ bootph-pre-ram;
+ bootph-some-ram;
+ };
};
-&pinctrl {
+&spi0m2_clk {
bootph-pre-ram;
};
-&sdmmc0m1_pin {
+&spi0m2_cs0 {
bootph-pre-ram;
};
-&pcfg_pull_up_4ma {
+&spi0m2_rx {
bootph-pre-ram;
};
-/* Need this and all the pinctrl/gpio stuff above to set pinmux */
-&vcc_sd {
+&spi0m2_tx {
bootph-pre-ram;
};
-&spi0 {
- spi_flash: flash@0 {
- bootph-all;
- };
+&usb20_otg {
+ hnp-srp-disable;
+};
+
+&vcc_sd {
+ bootph-pre-ram;
};
diff --git a/arch/arm/dts/rk3328-rock64.dts b/arch/arm/dts/rk3328-rock64.dts
index 0a27fa5..229fe9d 100644
--- a/arch/arm/dts/rk3328-rock64.dts
+++ b/arch/arm/dts/rk3328-rock64.dts
@@ -11,6 +11,7 @@
compatible = "pine64,rock64", "rockchip,rk3328";
aliases {
+ ethernet0 = &gmac2io;
mmc0 = &sdmmc;
mmc1 = &emmc;
};
diff --git a/arch/arm/dts/rk3328-u-boot.dtsi b/arch/arm/dts/rk3328-u-boot.dtsi
index a9f2536..e0c6aee 100644
--- a/arch/arm/dts/rk3328-u-boot.dtsi
+++ b/arch/arm/dts/rk3328-u-boot.dtsi
@@ -13,7 +13,7 @@
};
chosen {
- u-boot,spl-boot-order = &emmc, &sdmmc;
+ u-boot,spl-boot-order = "same-as-spl", &sdmmc, &emmc;
};
dmc: dmc {
@@ -26,45 +26,117 @@
0x0 0xff720000 0x0 0x1000
0x0 0xff798000 0x0 0x1000>;
};
-
- rng: rng@ff060000 {
- compatible = "rockchip,cryptov1-rng";
- reg = <0x0 0xff060000 0x0 0x4000>;
- status = "okay";
- };
};
&cru {
bootph-all;
};
+&emmc {
+ bootph-pre-ram;
+ bootph-some-ram;
+
+ /* mmc to sram can't do dma, prevent aborts transferring TF-A parts */
+ u-boot,spl-fifo-mode;
+};
+
+&emmc_bus8 {
+ bootph-pre-ram;
+};
+
+&emmc_clk {
+ bootph-pre-ram;
+};
+
+&emmc_cmd {
+ bootph-pre-ram;
+};
+
+&gpio0 {
+ bootph-pre-ram;
+};
+
&grf {
bootph-all;
};
-&uart2 {
+&pcfg_pull_none {
bootph-all;
- clock-frequency = <24000000>;
};
-&emmc {
+&pcfg_pull_none_8ma {
+ bootph-pre-ram;
+};
+
+&pcfg_pull_none_12ma {
+ bootph-pre-ram;
+};
+
+&pcfg_pull_up {
bootph-all;
+};
- /* mmc to sram can't do dma, prevent aborts transfering TF-A parts */
- u-boot,spl-fifo-mode;
+&pcfg_pull_up_4ma {
+ bootph-pre-ram;
};
+&pcfg_pull_up_8ma {
+ bootph-pre-ram;
+};
+
+&pcfg_pull_up_12ma {
+ bootph-pre-ram;
+};
+
+&pinctrl {
+ bootph-pre-ram;
+ bootph-some-ram;
+};
+
&sdmmc {
- bootph-all;
+ bootph-pre-ram;
+ bootph-some-ram;
- /* mmc to sram can't do dma, prevent aborts transfering TF-A parts */
+ /* mmc to sram can't do dma, prevent aborts transferring TF-A parts */
u-boot,spl-fifo-mode;
};
+&sdmmc0_bus4 {
+ bootph-pre-ram;
+};
+
-&usb20_otg {
- hnp-srp-disable;
+&sdmmc0_clk {
+ bootph-pre-ram;
};
-&spi0 {
+&sdmmc0_cmd {
+ bootph-pre-ram;
+};
+
+&sdmmc0_dectn {
+ bootph-pre-ram;
+};
+
+&sdmmc0m1_pin {
+ bootph-pre-ram;
+};
+
+&uart2 {
bootph-all;
+ clock-frequency = <24000000>;
+};
+
+&uart2m1_xfer {
+ bootph-all;
+};
+
+#ifdef CONFIG_ROCKCHIP_SPI_IMAGE
+&binman {
+ simple-bin-spi {
+ mkimage {
+ args = "-n", CONFIG_SYS_SOC, "-T", "rksd";
+ offset = <0x8000>;
+ };
+ };
};
+#endif
diff --git a/arch/arm/dts/rk3328.dtsi b/arch/arm/dts/rk3328.dtsi
index e8d8f00..fb5dcf6 100644
--- a/arch/arm/dts/rk3328.dtsi
+++ b/arch/arm/dts/rk3328.dtsi
@@ -20,6 +20,10 @@
#size-cells = <2>;
aliases {
+ gpio0 = &gpio0;
+ gpio1 = &gpio1;
+ gpio2 = &gpio2;
+ gpio3 = &gpio3;
serial0 = &uart0;
serial1 = &uart1;
serial2 = &uart2;
@@ -27,8 +31,6 @@
i2c1 = &i2c1;
i2c2 = &i2c2;
i2c3 = &i2c3;
- ethernet0 = &gmac2io;
- ethernet1 = &gmac2phy;
};
cpus {
@@ -102,10 +104,12 @@
l2: l2-cache0 {
compatible = "cache";
+ cache-level = <2>;
+ cache-unified;
};
};
- cpu0_opp_table: opp_table0 {
+ cpu0_opp_table: opp-table-0 {
compatible = "operating-points-v2";
opp-shared;
@@ -306,6 +310,10 @@
};
power-domain@RK3328_PD_VIDEO {
reg = <RK3328_PD_VIDEO>;
+ clocks = <&cru ACLK_RKVDEC>,
+ <&cru HCLK_RKVDEC>,
+ <&cru SCLK_VDEC_CABAC>,
+ <&cru SCLK_VDEC_CORE>;
#power-domain-cells = <0>;
};
power-domain@RK3328_PD_VPU {
@@ -489,7 +497,7 @@
status = "disabled";
};
- dmac: dmac@ff1f0000 {
+ dmac: dma-controller@ff1f0000 {
compatible = "arm,pl330", "arm,primecell";
reg = <0x0 0xff1f0000 0x0 0x4000>;
interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
@@ -599,7 +607,7 @@
gpu: gpu@ff300000 {
compatible = "rockchip,rk3328-mali", "arm,mali-450";
- reg = <0x0 0xff300000 0x0 0x40000>;
+ reg = <0x0 0xff300000 0x0 0x30000>;
interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>,
@@ -623,7 +631,6 @@
compatible = "rockchip,iommu";
reg = <0x0 0xff330200 0 0x100>;
interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
- interrupt-names = "h265e_mmu";
clocks = <&cru ACLK_H265>, <&cru PCLK_H265>;
clock-names = "aclk", "iface";
#iommu-cells = <0>;
@@ -634,7 +641,6 @@
compatible = "rockchip,iommu";
reg = <0x0 0xff340800 0x0 0x40>;
interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
- interrupt-names = "vepu_mmu";
clocks = <&cru ACLK_VPU>, <&cru HCLK_VPU>;
clock-names = "aclk", "iface";
#iommu-cells = <0>;
@@ -656,22 +662,34 @@
compatible = "rockchip,iommu";
reg = <0x0 0xff350800 0x0 0x40>;
interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
- interrupt-names = "vpu_mmu";
clocks = <&cru ACLK_VPU>, <&cru HCLK_VPU>;
clock-names = "aclk", "iface";
#iommu-cells = <0>;
power-domains = <&power RK3328_PD_VPU>;
};
- rkvdec_mmu: iommu@ff360480 {
+ vdec: video-codec@ff360000 {
+ compatible = "rockchip,rk3328-vdec", "rockchip,rk3399-vdec";
+ reg = <0x0 0xff360000 0x0 0x480>;
+ interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cru ACLK_RKVDEC>, <&cru HCLK_RKVDEC>,
+ <&cru SCLK_VDEC_CABAC>, <&cru SCLK_VDEC_CORE>;
+ clock-names = "axi", "ahb", "cabac", "core";
+ assigned-clocks = <&cru ACLK_RKVDEC>, <&cru SCLK_VDEC_CABAC>,
+ <&cru SCLK_VDEC_CORE>;
+ assigned-clock-rates = <400000000>, <400000000>, <300000000>;
+ iommus = <&vdec_mmu>;
+ power-domains = <&power RK3328_PD_VIDEO>;
+ };
+
+ vdec_mmu: iommu@ff360480 {
compatible = "rockchip,iommu";
reg = <0x0 0xff360480 0x0 0x40>, <0x0 0xff3604c0 0x0 0x40>;
interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;
- interrupt-names = "rkvdec_mmu";
clocks = <&cru ACLK_RKVDEC>, <&cru HCLK_RKVDEC>;
clock-names = "aclk", "iface";
#iommu-cells = <0>;
- status = "disabled";
+ power-domains = <&power RK3328_PD_VIDEO>;
};
vop: vop@ff370000 {
@@ -700,7 +718,6 @@
compatible = "rockchip,iommu";
reg = <0x0 0xff373f00 0x0 0x100>;
interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
- interrupt-names = "vop_mmu";
clocks = <&cru ACLK_VOP>, <&cru HCLK_VOP>;
clock-names = "aclk", "iface";
#iommu-cells = <0>;
@@ -901,6 +918,8 @@
resets = <&cru SRST_GMAC2IO_A>;
reset-names = "stmmaceth";
rockchip,grf = <&grf>;
+ tx-fifo-depth = <2048>;
+ rx-fifo-depth = <4096>;
snps,txpbl = <0x4>;
status = "disabled";
};
@@ -923,6 +942,8 @@
reset-names = "stmmaceth";
phy-mode = "rmii";
phy-handle = <&phy>;
+ tx-fifo-depth = <2048>;
+ rx-fifo-depth = <4096>;
snps,txpbl = <0x4>;
clock_in_out = "output";
status = "disabled";
@@ -944,6 +965,22 @@
};
};
+ usb20_otg: usb@ff580000 {
+ compatible = "rockchip,rk3328-usb", "rockchip,rk3066-usb",
+ "snps,dwc2";
+ reg = <0x0 0xff580000 0x0 0x40000>;
+ interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cru HCLK_OTG>;
+ clock-names = "otg";
+ dr_mode = "otg";
+ g-np-tx-fifo-size = <16>;
+ g-rx-fifo-size = <280>;
+ g-tx-fifo-size = <256 128 128 64 32 16>;
+ phys = <&u2phy_otg>;
+ phy-names = "usb2-phy";
+ status = "disabled";
+ };
+
usb_host0_ehci: usb@ff5c0000 {
compatible = "generic-ehci";
reg = <0x0 0xff5c0000 0x0 0x10000>;
@@ -983,31 +1020,6 @@
status = "disabled";
};
- /*
- * U-Boot Specific Change
- *
- * The OTG controller must come after the USB host pair for it
- * to work. This is likely due to lack of support for the USB
- * PHYs. This must be manually changed after each device tree
- * sync. There is no clean way to handle this in -u-boot.dtsi
- * files.
- */
- usb20_otg: usb@ff580000 {
- compatible = "rockchip,rk3328-usb", "rockchip,rk3066-usb",
- "snps,dwc2";
- reg = <0x0 0xff580000 0x0 0x40000>;
- interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cru HCLK_OTG>;
- clock-names = "otg";
- dr_mode = "otg";
- g-np-tx-fifo-size = <16>;
- g-rx-fifo-size = <280>;
- g-tx-fifo-size = <256 128 128 64 32 16>;
- phys = <&u2phy_otg>;
- phy-names = "usb2-phy";
- status = "disabled";
- };
-
gic: interrupt-controller@ff811000 {
compatible = "arm,gic-400";
#interrupt-cells = <3>;
@@ -1021,6 +1033,17 @@
(GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
};
+ crypto: crypto@ff060000 {
+ compatible = "rockchip,rk3328-crypto";
+ reg = <0x0 0xff060000 0x0 0x4000>;
+ interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cru HCLK_CRYPTO_MST>, <&cru HCLK_CRYPTO_SLV>,
+ <&cru SCLK_CRYPTO>;
+ clock-names = "hclk_master", "hclk_slave", "sclk";
+ resets = <&cru SRST_CRYPTO>;
+ reset-names = "crypto-rst";
+ };
+
pinctrl: pinctrl {
compatible = "rockchip,rk3328-pinctrl";
rockchip,grf = <&grf>;
@@ -1028,7 +1051,7 @@
#size-cells = <2>;
ranges;
- gpio0: gpio0@ff210000 {
+ gpio0: gpio@ff210000 {
compatible = "rockchip,gpio-bank";
reg = <0x0 0xff210000 0x0 0x100>;
interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>;
@@ -1041,7 +1064,7 @@
#interrupt-cells = <2>;
};
- gpio1: gpio1@ff220000 {
+ gpio1: gpio@ff220000 {
compatible = "rockchip,gpio-bank";
reg = <0x0 0xff220000 0x0 0x100>;
interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>;
@@ -1054,7 +1077,7 @@
#interrupt-cells = <2>;
};
- gpio2: gpio2@ff230000 {
+ gpio2: gpio@ff230000 {
compatible = "rockchip,gpio-bank";
reg = <0x0 0xff230000 0x0 0x100>;
interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>;
@@ -1067,7 +1090,7 @@
#interrupt-cells = <2>;
};
- gpio3: gpio3@ff240000 {
+ gpio3: gpio@ff240000 {
compatible = "rockchip,gpio-bank";
reg = <0x0 0xff240000 0x0 0x100>;
interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>;
diff --git a/arch/arm/dts/rk3399-u-boot.dtsi b/arch/arm/dts/rk3399-u-boot.dtsi
index 3423b88..87b173e 100644
--- a/arch/arm/dts/rk3399-u-boot.dtsi
+++ b/arch/arm/dts/rk3399-u-boot.dtsi
@@ -30,7 +30,7 @@
};
rng: rng@ff8b8000 {
- compatible = "rockchip,cryptov1-rng";
+ compatible = "rockchip,rk3399-crypto";
reg = <0x0 0xff8b8000 0x0 0x1000>;
status = "okay";
};
diff --git a/arch/arm/dts/rk3566-anbernic-rgxx3-u-boot.dtsi b/arch/arm/dts/rk3566-anbernic-rgxx3-u-boot.dtsi
index fa3df73..791f16b 100644
--- a/arch/arm/dts/rk3566-anbernic-rgxx3-u-boot.dtsi
+++ b/arch/arm/dts/rk3566-anbernic-rgxx3-u-boot.dtsi
@@ -14,37 +14,6 @@
};
};
-&cru {
- assigned-clocks =
- <&pmucru CLK_RTC_32K>,
- <&pmucru PLL_PPLL>,
- <&pmucru PCLK_PMU>, <&cru PLL_CPLL>,
- <&cru PLL_GPLL>,
- <&cru ACLK_BUS>, <&cru PCLK_BUS>,
- <&cru ACLK_TOP_HIGH>, <&cru ACLK_TOP_LOW>,
- <&cru HCLK_TOP>, <&cru PCLK_TOP>,
- <&cru ACLK_PERIMID>, <&cru HCLK_PERIMID>,
- <&cru CPLL_500M>, <&cru CPLL_333M>,
- <&cru CPLL_250M>, <&cru CPLL_125M>,
- <&cru CPLL_100M>, <&cru CPLL_62P5M>,
- <&cru CPLL_50M>, <&cru CPLL_25M>;
- assigned-clock-rates =
- <32768>,
- <200000000>,
- <100000000>, <1000000000>,
- <1188000000>,
- <150000000>, <100000000>,
- <500000000>, <400000000>,
- <150000000>, <100000000>,
- <300000000>, <150000000>,
- <500000000>, <333333333>,
- <250000000>, <125000000>,
- <100000000>, <62500000>,
- <50000000>, <25000000>;
- assigned-clock-parents =
- <&pmucru CLK_RTC32K_FRAC>;
-};
-
&dsi_dphy0 {
status = "okay";
};
diff --git a/arch/arm/dts/rk3566-anbernic-rgxx3.dts b/arch/arm/dts/rk3566-anbernic-rgxx3.dts
index 404dddf..c393c8d 100644
--- a/arch/arm/dts/rk3566-anbernic-rgxx3.dts
+++ b/arch/arm/dts/rk3566-anbernic-rgxx3.dts
@@ -12,7 +12,17 @@
* set the correct dtb name for loading mainline Linux automatically.
*/
model = "RGXX3";
- compatible = "anbernic,rg353m", "anbernic,rg353p",
- "anbernic,rg353v", "anbernic,rg353vs",
- "anbernic,rg503", "rockchip,rk3566";
+ compatible = "anbernic,rg-arc-d", "anbernic,rg-arc-s",
+ "anbernic,rg353m", "anbernic,rg353p",
+ "anbernic,rg353ps", "anbernic,rg353v",
+ "anbernic,rg353vs", "anbernic,rg503",
+ "powkiddy,rgb10max3", "powkiddy,rgb30",
+ "powkiddy,rk2023", "rockchip,rk3566";
+};
+
+&cru {
+ assigned-clocks = <&pmucru CLK_RTC_32K>, <&cru PLL_GPLL>,
+ <&pmucru PLL_PPLL>, <&cru PLL_VPLL>;
+ assigned-clock-rates = <32768>, <1200000000>,
+ <200000000>, <241500000>;
};
diff --git a/arch/arm/dts/rk3566-pinetab2-u-boot.dtsi b/arch/arm/dts/rk3566-pinetab2-u-boot.dtsi
new file mode 100644
index 0000000..4aa6ab1
--- /dev/null
+++ b/arch/arm/dts/rk3566-pinetab2-u-boot.dtsi
@@ -0,0 +1,44 @@
+// SPDX-License-Identifier: GPL-2.0+
+
+#include "rk356x-u-boot.dtsi"
+
+&fspi_dual_io_pins {
+ bootph-all;
+};
+
+&gpio0 {
+ bootph-all;
+};
+
+&i2c0 {
+ bootph-pre-ram;
+};
+
+&rk817 {
+ bootph-pre-ram;
+
+ regulators {
+ bootph-pre-ram;
+ };
+};
+
+&sdhci {
+ cap-mmc-highspeed;
+};
+
+&sdmmc_pwren_l {
+ bootph-all;
+};
+
+&sfc {
+ bootph-pre-ram;
+ u-boot,spl-sfc-no-dma;
+
+ flash@0 {
+ bootph-pre-ram;
+ };
+};
+
+&vcc3v3_sd {
+ bootph-pre-ram;
+};
diff --git a/arch/arm/dts/rk3566-pinetab2-v0.1-u-boot.dtsi b/arch/arm/dts/rk3566-pinetab2-v0.1-u-boot.dtsi
new file mode 100644
index 0000000..061dc3c
--- /dev/null
+++ b/arch/arm/dts/rk3566-pinetab2-v0.1-u-boot.dtsi
@@ -0,0 +1,3 @@
+// SPDX-License-Identifier: GPL-2.0+
+
+#include "rk3566-pinetab2-u-boot.dtsi"
diff --git a/arch/arm/dts/rk3566-pinetab2-v0.1.dts b/arch/arm/dts/rk3566-pinetab2-v0.1.dts
new file mode 100644
index 0000000..5fe6ca5
--- /dev/null
+++ b/arch/arm/dts/rk3566-pinetab2-v0.1.dts
@@ -0,0 +1,28 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+
+/dts-v1/;
+
+#include "rk3566-pinetab2.dtsi"
+
+/ {
+ model = "Pine64 PineTab2 v0.1";
+ compatible = "pine64,pinetab2-v0.1", "pine64,pinetab2", "rockchip,rk3566";
+};
+
+&lcd {
+ reset-gpios = <&gpio0 RK_PA6 GPIO_ACTIVE_LOW>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&lcd_pwren_h &lcd0_rst_l>;
+};
+
+&pinctrl {
+ lcd0 {
+ lcd0_rst_l: lcd0-rst-l {
+ rockchip,pins = <0 RK_PA6 RK_FUNC_GPIO &pcfg_pull_none>;
+ };
+ };
+};
+
+&sdmmc1 {
+ vmmc-supply = <&vcc3v3_sys>;
+};
diff --git a/arch/arm/dts/rk3566-pinetab2-v2.0-u-boot.dtsi b/arch/arm/dts/rk3566-pinetab2-v2.0-u-boot.dtsi
new file mode 100644
index 0000000..061dc3c
--- /dev/null
+++ b/arch/arm/dts/rk3566-pinetab2-v2.0-u-boot.dtsi
@@ -0,0 +1,3 @@
+// SPDX-License-Identifier: GPL-2.0+
+
+#include "rk3566-pinetab2-u-boot.dtsi"
diff --git a/arch/arm/dts/rk3566-pinetab2-v2.0.dts b/arch/arm/dts/rk3566-pinetab2-v2.0.dts
new file mode 100644
index 0000000..9349541
--- /dev/null
+++ b/arch/arm/dts/rk3566-pinetab2-v2.0.dts
@@ -0,0 +1,48 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+
+/dts-v1/;
+
+#include "rk3566-pinetab2.dtsi"
+
+/ {
+ model = "Pine64 PineTab2 v2.0";
+ compatible = "pine64,pinetab2-v2.0", "pine64,pinetab2", "rockchip,rk3566";
+};
+
+&gpio_keys {
+ pinctrl-0 = <&kb_id_det>, <&hall_int_l>;
+
+ event-hall-sensor {
+ debounce-interval = <20>;
+ gpios = <&gpio0 RK_PA6 GPIO_ACTIVE_LOW>;
+ label = "Hall Sensor";
+ linux,code = <SW_LID>;
+ linux,input-type = <EV_SW>;
+ wakeup-event-action = <EV_ACT_DEASSERTED>;
+ wakeup-source;
+ };
+};
+
+&lcd {
+ reset-gpios = <&gpio0 RK_PC6 GPIO_ACTIVE_LOW>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&lcd_pwren_h &lcd0_rst_l>;
+};
+
+&pinctrl {
+ lcd0 {
+ lcd0_rst_l: lcd0-rst-l {
+ rockchip,pins = <0 RK_PC6 RK_FUNC_GPIO &pcfg_pull_none>;
+ };
+ };
+
+ hall {
+ hall_int_l: hall-int-l {
+ rockchip,pins = <0 RK_PA6 RK_FUNC_GPIO &pcfg_pull_none>;
+ };
+ };
+};
+
+&sdmmc1 {
+ vmmc-supply = <&vcc_sys>;
+};
diff --git a/arch/arm/dts/rk3566-pinetab2.dtsi b/arch/arm/dts/rk3566-pinetab2.dtsi
new file mode 100644
index 0000000..db40281
--- /dev/null
+++ b/arch/arm/dts/rk3566-pinetab2.dtsi
@@ -0,0 +1,943 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/input/gpio-keys.h>
+#include <dt-bindings/input/input.h>
+#include <dt-bindings/leds/common.h>
+#include <dt-bindings/pinctrl/rockchip.h>
+#include <dt-bindings/soc/rockchip,vop2.h>
+#include <dt-bindings/usb/pd.h>
+#include "rk3566.dtsi"
+
+/ {
+ chassis-type = "tablet";
+
+ aliases {
+ mmc0 = &sdhci;
+ mmc1 = &sdmmc0;
+ };
+
+ chosen {
+ stdout-path = "serial2:1500000n8";
+ };
+
+ adc-keys {
+ compatible = "adc-keys";
+ io-channels = <&saradc 0>;
+ io-channel-names = "buttons";
+ keyup-threshold-microvolt = <1800000>;
+ poll-interval = <25>;
+
+ button-vol-up {
+ label = "Volume Up";
+ linux,code = <KEY_VOLUMEUP>;
+ press-threshold-microvolt = <297500>;
+ };
+
+ button-vol-down {
+ label = "Volume Down";
+ linux,code = <KEY_VOLUMEDOWN>;
+ press-threshold-microvolt = <1750>;
+ };
+ };
+
+ backlight: backlight {
+ compatible = "pwm-backlight";
+ pwms = <&pwm4 0 25000 0>;
+ brightness-levels = <20 220>;
+ num-interpolated-steps = <200>;
+ default-brightness-level = <100>;
+ power-supply = <&vcc_sys>;
+ };
+
+ battery: battery {
+ compatible = "simple-battery";
+ charge-full-design-microamp-hours = <6000000>;
+ charge-term-current-microamp = <300000>;
+ constant-charge-current-max-microamp = <2000000>;
+ constant-charge-voltage-max-microvolt = <4300000>;
+ voltage-max-design-microvolt = <4350000>;
+ voltage-min-design-microvolt = <3400000>;
+
+ ocv-capacity-celsius = <20>;
+ ocv-capacity-table-0 = <4322000 100>, <4250000 95>, <4192000 90>, <4136000 85>,
+ <4080000 80>, <4022000 75>, <3972000 70>, <3928000 65>,
+ <3885000 60>, <3833000 55>, <3798000 50>, <3780000 45>,
+ <3776000 40>, <3773000 35>, <3755000 30>, <3706000 25>,
+ <3640000 20>, <3589000 15>, <3535000 10>, <3492000 5>,
+ <3400000 0>;
+ };
+
+ gpio_keys: gpio-keys {
+ compatible = "gpio-keys";
+ pinctrl-names = "default";
+ pinctrl-0 = <&kb_id_det>;
+
+ tablet-mode-switch {
+ debounce-interval = <20>;
+ gpios = <&gpio4 RK_PA4 GPIO_ACTIVE_HIGH>;
+ label = "Tablet Mode";
+ linux,input-type = <EV_SW>;
+ linux,code = <SW_TABLET_MODE>;
+ };
+ };
+
+ hdmi-connector {
+ compatible = "hdmi-connector";
+ type = "d";
+
+ port {
+ hdmi_con_in: endpoint {
+ remote-endpoint = <&hdmi_out_con>;
+ };
+ };
+ };
+
+ led-0 {
+ compatible = "regulator-led";
+ vled-supply = <&vcc5v0_flashled>;
+ color = <LED_COLOR_ID_WHITE>;
+ function = LED_FUNCTION_FLASH;
+ };
+
+ rk817-sound {
+ compatible = "simple-audio-card";
+ pinctrl-names = "default";
+ pinctrl-0 = <&hp_det_l>;
+ simple-audio-card,format = "i2s";
+ simple-audio-card,name = "rk817_ext";
+ simple-audio-card,mclk-fs = <256>;
+
+ simple-audio-card,widgets =
+ "Microphone", "Mic Jack",
+ "Headphone", "Headphones",
+ "Speaker", "Internal Speakers";
+
+ simple-audio-card,routing =
+ "MICR", "Mic Jack",
+ "Headphones", "HPOL",
+ "Headphones", "HPOR",
+ "Internal Speakers", "Speaker Amplifier OUTL",
+ "Internal Speakers", "Speaker Amplifier OUTR",
+ "Speaker Amplifier INL", "HPOL",
+ "Speaker Amplifier INR", "HPOR";
+ simple-audio-card,hp-det-gpio = <&gpio4 RK_PC6 GPIO_ACTIVE_LOW>;
+ simple-audio-card,aux-devs = <&speaker_amp>;
+ simple-audio-card,pin-switches = "Internal Speakers";
+
+ simple-audio-card,cpu {
+ sound-dai = <&i2s1_8ch>;
+ };
+
+ simple-audio-card,codec {
+ sound-dai = <&rk817>;
+ };
+ };
+
+ speaker_amp: speaker-amplifier {
+ compatible = "simple-audio-amplifier";
+ pinctrl-names = "default";
+ pinctrl-0 = <&spk_ctl>;
+ enable-gpios = <&gpio4 RK_PC2 GPIO_ACTIVE_HIGH>;
+ sound-name-prefix = "Speaker Amplifier";
+ VCC-supply = <&vcc_bat>;
+ };
+
+ vcc_3v3: vcc-3v3-regulator {
+ compatible = "regulator-fixed";
+ regulator-name = "vcc_3v3";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ vin-supply = <&vcc3v3_sys>;
+ };
+
+ vcc3v3_minipcie: vcc3v3-minipcie-regulator {
+ compatible = "regulator-fixed";
+ enable-active-high;
+ gpio = <&gpio4 RK_PC3 GPIO_ACTIVE_HIGH>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pcie_pwren_h>;
+ regulator-name = "vcc3v3_minipcie";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ vin-supply = <&vcc_sys>;
+ };
+
+ vcc3v3_sd: vcc3v3-sd-regulator {
+ compatible = "regulator-fixed";
+ gpio = <&gpio0 RK_PA5 GPIO_ACTIVE_HIGH>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&sdmmc_pwren_l>;
+ regulator-name = "vcc3v3_sd";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ vin-supply = <&vcc3v3_sys>;
+ };
+
+ vcc5v0_flashled: vcc5v0-flashled-regulator {
+ compatible = "regulator-fixed";
+ enable-active-high;
+ gpio = <&gpio4 RK_PA5 GPIO_ACTIVE_HIGH>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&flash_led_en_h>;
+ regulator-name = "vcc5v0_flashled";
+ regulator-min-microvolt = <5000000>;
+ regulator-max-microvolt = <5000000>;
+ vin-supply = <&vcc5v_midu>;
+ };
+
+ vcc5v0_usb_host0: vcc5v0-usb-host0-regulator {
+ compatible = "regulator-fixed";
+ enable-active-high;
+ gpio = <&gpio4 RK_PC4 GPIO_ACTIVE_HIGH>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&usb_host_pwren1_h>;
+ regulator-name = "vcc5v0_usb_host0";
+ regulator-min-microvolt = <5000000>;
+ regulator-max-microvolt = <5000000>;
+ vin-supply = <&vcc5v_midu>;
+ };
+
+ vcc5v0_usb_host2: vcc5v0-usb-host2-regulator {
+ compatible = "regulator-fixed";
+ enable-active-high;
+ gpio = <&gpio4 RK_PC5 GPIO_ACTIVE_HIGH>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&usb_host_pwren2_h>;
+ regulator-name = "vcc5v0_usb_host2";
+ regulator-min-microvolt = <5000000>;
+ regulator-max-microvolt = <5000000>;
+ vin-supply = <&vcc5v_midu>;
+ };
+
+ vcc_bat: vcc-bat-regulator {
+ compatible = "regulator-fixed";
+ regulator-name = "vcc_bat";
+ regulator-always-on;
+ regulator-boot-on;
+ };
+
+ vcc_sys: vcc-sys-regulator {
+ compatible = "regulator-fixed";
+ regulator-name = "vcc_sys";
+ regulator-always-on;
+ regulator-boot-on;
+ vin-supply = <&vcc_bat>;
+ };
+
+ vdd1v2_dvp: vdd1v2-dvp-regulator {
+ compatible = "regulator-fixed";
+ regulator-name = "vdd1v2_dvp";
+ regulator-min-microvolt = <1200000>;
+ regulator-max-microvolt = <1200000>;
+ vin-supply = <&vcc_3v3>;
+ };
+};
+
+&combphy1 {
+ status = "okay";
+};
+
+&combphy2 {
+ status = "okay";
+};
+
+&cpu0 {
+ cpu-supply = <&vdd_cpu>;
+};
+
+&cpu1 {
+ cpu-supply = <&vdd_cpu>;
+};
+
+&cpu2 {
+ cpu-supply = <&vdd_cpu>;
+};
+
+&cpu3 {
+ cpu-supply = <&vdd_cpu>;
+};
+
+&cru {
+ assigned-clocks = <&pmucru CLK_RTC_32K>, <&cru PLL_GPLL>,
+ <&pmucru PLL_PPLL>, <&cru PLL_VPLL>;
+ assigned-clock-rates = <32768>, <1200000000>, <200000000>, <500000000>;
+ assigned-clock-parents = <&pmucru CLK_RTC32K_FRAC>;
+};
+
+&csi_dphy {
+ status = "okay";
+};
+
+&dsi0 {
+ status = "okay";
+ clock-master;
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ lcd: panel@0 {
+ compatible = "boe,th101mb31ig002-28a";
+ reg = <0>;
+ backlight = <&backlight>;
+ enable-gpios = <&gpio0 RK_PC7 GPIO_ACTIVE_HIGH>;
+ rotation = <90>;
+ power-supply = <&vcc_3v3>;
+
+ port@0 {
+ panel_in_dsi: endpoint@0 {
+ remote-endpoint = <&dsi0_out_con>;
+ };
+ };
+ };
+};
+
+&dsi0_in {
+ dsi0_in_vp1: endpoint {
+ remote-endpoint = <&vp1_out_dsi0>;
+ };
+};
+
+&dsi0_out {
+ dsi0_out_con: endpoint {
+ remote-endpoint = <&panel_in_dsi>;
+ };
+};
+
+&dsi_dphy0 {
+ status = "okay";
+};
+
+&gpu {
+ mali-supply = <&vdd_gpu_npu>;
+ status = "okay";
+};
+
+&hdmi {
+ avdd-0v9-supply = <&vdda_0v9_p>;
+ avdd-1v8-supply = <&vcc_1v8>;
+ status = "okay";
+};
+
+&hdmi_in {
+ hdmi_in_vp0: endpoint {
+ remote-endpoint = <&vp0_out_hdmi>;
+ };
+};
+
+&hdmi_out {
+ hdmi_out_con: endpoint {
+ remote-endpoint = <&hdmi_con_in>;
+ };
+};
+
+&hdmi_sound {
+ status = "okay";
+};
+
+&i2c0 {
+ clock-frequency = <400000>;
+ status = "okay";
+
+ vdd_cpu: regulator@1c {
+ compatible = "tcs,tcs4525";
+ reg = <0x1c>;
+ fcs,suspend-voltage-selector = <1>;
+ regulator-name = "vdd_cpu";
+ regulator-min-microvolt = <800000>;
+ regulator-max-microvolt = <1150000>;
+ regulator-ramp-delay = <2300>;
+ regulator-always-on;
+ regulator-boot-on;
+ vin-supply = <&vcc_sys>;
+
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ };
+ };
+
+ rk817: pmic@20 {
+ compatible = "rockchip,rk817";
+ reg = <0x20>;
+ interrupt-parent = <&gpio0>;
+ interrupts = <RK_PA3 IRQ_TYPE_LEVEL_LOW>;
+ assigned-clocks = <&cru I2S1_MCLKOUT_TX>;
+ assigned-clock-parents = <&cru CLK_I2S1_8CH_TX>;
+ clock-names = "mclk";
+ clocks = <&cru I2S1_MCLKOUT_TX>;
+ clock-output-names = "rk808-clkout1", "rk808-clkout2";
+ #clock-cells = <1>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pmic_int_l>, <&i2s1m0_mclk>;
+ rockchip,system-power-controller;
+ #sound-dai-cells = <0>;
+ wakeup-source;
+
+ vcc1-supply = <&vcc_sys>;
+ vcc2-supply = <&vcc_sys>;
+ vcc3-supply = <&vcc_sys>;
+ vcc4-supply = <&vcc_sys>;
+ vcc5-supply = <&vcc_sys>;
+ vcc6-supply = <&vcc_sys>;
+ vcc7-supply = <&vcc_sys>;
+ vcc8-supply = <&vcc_sys>;
+ vcc9-supply = <&vcc5v_midu>;
+
+ regulators {
+ vdd_logic: DCDC_REG1 {
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <500000>;
+ regulator-max-microvolt = <1350000>;
+ regulator-ramp-delay = <6001>;
+ regulator-initial-mode = <0x2>;
+ regulator-name = "vdd_logic";
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ };
+ };
+
+ vdd_gpu_npu: DCDC_REG2 {
+ regulator-min-microvolt = <500000>;
+ regulator-max-microvolt = <1350000>;
+ regulator-ramp-delay = <6001>;
+ regulator-initial-mode = <0x2>;
+ regulator-name = "vdd_gpu_npu";
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ };
+ };
+
+ vcc_ddr: DCDC_REG3 {
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-initial-mode = <0x2>;
+ regulator-name = "vcc_ddr";
+ regulator-state-mem {
+ regulator-on-in-suspend;
+ };
+ };
+
+ vcc3v3_sys: DCDC_REG4 {
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-initial-mode = <0x2>;
+ regulator-name = "vcc3v3_sys";
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ };
+ };
+
+ vcca1v8_pmu: LDO_REG1 {
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-name = "vcca1v8_pmu";
+ regulator-state-mem {
+ regulator-on-in-suspend;
+ };
+ };
+
+ vdda_0v9_p: LDO_REG2 {
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <900000>;
+ regulator-max-microvolt = <900000>;
+ regulator-name = "vdda_0v9_p";
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ };
+ };
+
+ vdda0v9_pmu: LDO_REG3 {
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <900000>;
+ regulator-max-microvolt = <900000>;
+ regulator-name = "vdda0v9_pmu";
+ regulator-state-mem {
+ regulator-on-in-suspend;
+ };
+ };
+
+ vccio_acodec: LDO_REG4 {
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-name = "vccio_acodec";
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ };
+ };
+
+ vccio_sd: LDO_REG5 {
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-name = "vccio_sd";
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ };
+ };
+
+ vcc3v3_pmu: LDO_REG6 {
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-name = "vcc3v3_pmu";
+ regulator-state-mem {
+ regulator-on-in-suspend;
+ };
+ };
+
+ vcc_1v8: LDO_REG7 {
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-name = "vcc_1v8";
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ };
+ };
+
+ vcc1v8_dvp: LDO_REG8 {
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-name = "vcc1v8_dvp";
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ };
+ };
+
+ vcc2v8_dvp: LDO_REG9 {
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <2800000>;
+ regulator-max-microvolt = <2800000>;
+ regulator-name = "vcc2v8_dvp";
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ };
+ };
+
+ vcc5v_midu: BOOST {
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <5000000>;
+ regulator-max-microvolt = <5000000>;
+ regulator-name = "boost";
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ };
+ };
+
+ vbus: OTG_SWITCH {
+ regulator-min-microvolt = <5000000>;
+ regulator-max-microvolt = <5000000>;
+ regulator-name = "otg_switch";
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ };
+ };
+ };
+
+ charger {
+ monitored-battery = <&battery>;
+ rockchip,resistor-sense-micro-ohms = <10000>;
+ rockchip,sleep-enter-current-microamp = <300000>;
+ rockchip,sleep-filter-current-microamp = <100000>;
+ };
+ };
+};
+
+&i2c1 {
+ clock-frequency = <400000>;
+ status = "okay";
+
+ touchscreen@5d {
+ compatible = "goodix,gt911";
+ reg = <0x5d>;
+ interrupt-parent = <&gpio0>;
+ interrupts = <RK_PB0 IRQ_TYPE_EDGE_FALLING>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&tp_int_l_pmuio2>, <&tp_rst_l_pmuio2>;
+ AVDD28-supply = <&vcc3v3_pmu>;
+ VDDIO-supply = <&vcca1v8_pmu>;
+ irq-gpios = <&gpio0 RK_PB0 GPIO_ACTIVE_HIGH>;
+ reset-gpios = <&gpio0 RK_PC2 GPIO_ACTIVE_HIGH>;
+ };
+};
+
+&i2c2 {
+ clock-frequency = <400000>;
+ pinctrl-0 = <&i2c2m1_xfer>;
+ status = "okay";
+
+ vcm@c {
+ compatible = "dongwoon,dw9714";
+ reg = <0x0c>;
+ vcc-supply = <&vcc1v8_dvp>;
+ };
+
+ camera@36 {
+ compatible = "ovti,ov5648";
+ reg = <0x36>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&camerab_pdn_l &camerab_rst_l>;
+
+ clocks = <&cru CLK_CIF_OUT>;
+ assigned-clocks = <&cru CLK_CIF_OUT>;
+ assigned-clock-rates = <24000000>;
+
+ avdd-supply = <&vcc2v8_dvp>;
+ dvdd-supply = <&vdd1v2_dvp>;
+ dovdd-supply = <&vcc1v8_dvp>;
+ powerdown-gpios = <&gpio4 RK_PB3 GPIO_ACTIVE_LOW>;
+ reset-gpios = <&gpio4 RK_PB1 GPIO_ACTIVE_LOW>;
+
+ port {
+ endpoint {
+ data-lanes = <1 2>;
+ remote-endpoint = <0>;
+ link-frequencies = /bits/ 64 <210000000 168000000>;
+ };
+ };
+ };
+};
+
+&i2c5 {
+ clock-frequency = <400000>;
+ status = "okay";
+
+ accelerometer@18 {
+ compatible = "silan,sc7a20";
+ reg = <0x18>;
+ interrupt-parent = <&gpio3>;
+ interrupts = <RK_PA2 IRQ_TYPE_LEVEL_LOW>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&gsensor_int_l>;
+ st,drdy-int-pin = <1>;
+ vdd-supply = <&vcc_1v8>;
+ vddio-supply = <&vcc_1v8>;
+ mount-matrix = "1", "0", "0",
+ "0", "0", "1",
+ "0", "1", "0";
+ };
+};
+
+&i2s0_8ch {
+ status = "okay";
+};
+
+&i2s1_8ch {
+ pinctrl-names = "default";
+ pinctrl-0 = <&i2s1m0_sclktx
+ &i2s1m0_lrcktx
+ &i2s1m0_sdi0
+ &i2s1m0_sdo0>;
+ rockchip,trcm-sync-tx-only;
+ status = "okay";
+};
+
+&pcie2x1 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pcie_reset_h>;
+ reset-gpios = <&gpio1 RK_PB2 GPIO_ACTIVE_HIGH>;
+ vpcie3v3-supply = <&vcc3v3_minipcie>;
+ status = "okay";
+};
+
+&pinctrl {
+ camerab {
+ camerab_pdn_l: camerab-pdn-l {
+ rockchip,pins = <4 RK_PB3 RK_FUNC_GPIO &pcfg_pull_none>;
+ };
+
+ camerab_rst_l: camerab-rst-l {
+ rockchip,pins = <4 RK_PB1 RK_FUNC_GPIO &pcfg_pull_none>;
+ };
+ };
+
+ cameraf {
+ cameraf_pdn_l: cameraf-pdn-l {
+ rockchip,pins = <4 RK_PB2 RK_FUNC_GPIO &pcfg_pull_none>;
+ };
+
+ cameraf_rst_l: cameraf-rst-l {
+ rockchip,pins = <4 RK_PB0 RK_FUNC_GPIO &pcfg_pull_none>;
+ };
+ };
+
+ flash {
+ flash_led_en_h: flash-led-en-h {
+ rockchip,pins = <4 RK_PA5 RK_FUNC_GPIO &pcfg_pull_none>;
+ };
+ };
+
+ fspi {
+ fspi_dual_io_pins: fspi-dual-io-pins {
+ rockchip,pins =
+ /* fspi_clk */
+ <1 RK_PD0 1 &pcfg_pull_none>,
+ /* fspi_cs0n */
+ <1 RK_PD3 1 &pcfg_pull_none>,
+ /* fspi_d0 */
+ <1 RK_PD1 1 &pcfg_pull_none>,
+ /* fspi_d1 */
+ <1 RK_PD2 1 &pcfg_pull_none>;
+ };
+ };
+
+ gsensor {
+ gsensor_int_l: gsensor-int-l {
+ rockchip,pins = <3 RK_PA2 RK_FUNC_GPIO &pcfg_pull_up>;
+ };
+ };
+
+ kb {
+ kb_id_det: kb-id-det {
+ rockchip,pins = <4 RK_PA4 RK_FUNC_GPIO &pcfg_pull_none>;
+ };
+ };
+
+ lcd {
+ lcd_pwren_h: lcd-pwren-h {
+ rockchip,pins = <0 RK_PC7 RK_FUNC_GPIO &pcfg_pull_none>;
+ };
+ };
+
+ pcie {
+ pcie_pwren_h: pcie-pwren-h {
+ rockchip,pins = <4 RK_PC3 RK_FUNC_GPIO &pcfg_pull_none>;
+ };
+
+ pcie_reset_h: pcie-reset-h {
+ rockchip,pins = <1 RK_PB2 RK_FUNC_GPIO &pcfg_pull_none>;
+ };
+ };
+
+ pmic {
+ pmic_int_l: pmic-int-l {
+ rockchip,pins = <0 RK_PA3 RK_FUNC_GPIO &pcfg_pull_up>;
+ };
+ };
+
+ sdmmc {
+ sdmmc_pwren_l: sdmmc-pwren-l {
+ rockchip,pins = <0 RK_PA5 RK_FUNC_GPIO &pcfg_pull_none>;
+ };
+ };
+
+ sound {
+ hp_det_l: hp-det-l {
+ rockchip,pins = <4 RK_PC6 RK_FUNC_GPIO &pcfg_pull_none>;
+ };
+
+ spk_ctl: spk-ctl {
+ rockchip,pins = <4 RK_PC2 RK_FUNC_GPIO &pcfg_pull_none>;
+ };
+ };
+
+ tp {
+ tp_int_l_pmuio2: tp-int-l-pmuio2 {
+ rockchip,pins = <0 RK_PB0 RK_FUNC_GPIO &pcfg_pull_up>;
+ };
+
+ tp_rst_l_pmuio2: tp-rst-l-pmuio2 {
+ rockchip,pins = <0 RK_PC2 RK_FUNC_GPIO &pcfg_pull_none>;
+ };
+ };
+
+ usb {
+ usbcc_int_l: usbcc-int-l {
+ rockchip,pins = <0 RK_PC5 RK_FUNC_GPIO &pcfg_pull_none>;
+ };
+
+ usb_host_pwren1_h: usb-host-pwren1-h {
+ rockchip,pins = <4 RK_PC4 RK_FUNC_GPIO &pcfg_pull_none>;
+ };
+
+ usb_host_pwren2_h: usb-host-pwren2-h {
+ rockchip,pins = <4 RK_PC5 RK_FUNC_GPIO &pcfg_pull_none>;
+ };
+ };
+
+ wifi {
+ host_wake_wl: host-wake-wl {
+ rockchip,pins = <0 RK_PB7 RK_FUNC_GPIO &pcfg_pull_none>;
+ };
+
+ wifi_wake_host_h: wifi-wake-host-h {
+ rockchip,pins = <0 RK_PC4 RK_FUNC_GPIO &pcfg_pull_down>;
+ };
+ };
+};
+
+&pmu_io_domains {
+ pmuio1-supply = <&vcc3v3_pmu>;
+ pmuio2-supply = <&vcca1v8_pmu>;
+ vccio1-supply = <&vccio_acodec>;
+ vccio2-supply = <&vcc_1v8>;
+ vccio3-supply = <&vccio_sd>;
+ vccio4-supply = <&vcc_1v8>;
+ vccio5-supply = <&vcc_1v8>;
+ vccio6-supply = <&vcc1v8_dvp>;
+ vccio7-supply = <&vcc_3v3>;
+ status = "okay";
+};
+
+&pwm4 {
+ status = "okay";
+};
+
+&saradc {
+ vref-supply = <&vcc_1v8>;
+ status = "okay";
+};
+
+&sdhci {
+ bus-width = <8>;
+ no-sdio;
+ no-sd;
+ non-removable;
+ max-frequency = <200000000>;
+ mmc-hs200-1_8v;
+ pinctrl-names = "default";
+ pinctrl-0 = <&emmc_bus8
+ &emmc_clk
+ &emmc_cmd
+ &emmc_datastrobe
+ &emmc_rstnout>;
+ vmmc-supply = <&vcc_3v3>;
+ vqmmc-supply = <&vcc_1v8>;
+ status = "okay";
+};
+
+&sdmmc0 {
+ bus-width = <4>;
+ cap-sd-highspeed;
+ cd-gpios = <&gpio0 RK_PA4 GPIO_ACTIVE_LOW>;
+ disable-wp;
+ pinctrl-names = "default";
+ pinctrl-0 = <&sdmmc0_bus4
+ &sdmmc0_clk
+ &sdmmc0_cmd
+ &sdmmc0_det>;
+ sd-uhs-sdr104;
+ vmmc-supply = <&vcc3v3_sd>;
+ vqmmc-supply = <&vccio_sd>;
+ status = "okay";
+};
+
+&sdmmc1 {
+ bus-width = <4>;
+ cap-sd-highspeed;
+ cap-sdio-irq;
+ keep-power-in-suspend;
+ non-removable;
+ pinctrl-names = "default";
+ pinctrl-0 = <&sdmmc1_bus4
+ &sdmmc1_cmd
+ &sdmmc1_clk>;
+ sd-uhs-sdr104;
+ vqmmc-supply = <&vcca1v8_pmu>;
+ status = "okay";
+};
+
+&sfc {
+ pinctrl-names = "default";
+ pinctrl-0 = <&fspi_dual_io_pins>;
+ status = "okay";
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ flash@0 {
+ compatible = "jedec,spi-nor";
+ reg = <0>;
+ spi-max-frequency = <100000000>;
+ spi-rx-bus-width = <2>;
+ spi-tx-bus-width = <1>;
+ };
+};
+
+&tsadc {
+ rockchip,hw-tshut-mode = <1>;
+ rockchip,hw-tshut-polarity = <0>;
+ status = "okay";
+};
+
+&uart2 {
+ status = "okay";
+};
+
+&usb_host0_ehci {
+ status = "okay";
+};
+
+&usb_host0_ohci {
+ status = "okay";
+};
+
+&usb_host0_xhci {
+ status = "okay";
+};
+
+&usb_host1_xhci {
+ status = "okay";
+};
+
+&usb2phy0 {
+ status = "okay";
+};
+
+&usb2phy0_host {
+ phy-supply = <&vcc5v0_usb_host0>;
+ status = "okay";
+};
+
+&usb2phy0_otg {
+ status = "okay";
+};
+
+&usb2phy1 {
+ status = "okay";
+};
+
+&usb2phy1_otg {
+ phy-supply = <&vcc5v0_usb_host2>;
+ status = "okay";
+};
+
+&vop {
+ assigned-clocks = <&cru DCLK_VOP0>, <&cru DCLK_VOP1>;
+ assigned-clock-parents = <&pmucru PLL_HPLL>, <&cru PLL_VPLL>;
+ status = "okay";
+};
+
+&vop_mmu {
+ status = "okay";
+};
+
+&vp0 {
+ vp0_out_hdmi: endpoint@ROCKCHIP_VOP2_EP_HDMI0 {
+ reg = <ROCKCHIP_VOP2_EP_HDMI0>;
+ remote-endpoint = <&hdmi_in_vp0>;
+ };
+};
+
+&vp1 {
+ vp1_out_dsi0: endpoint@ROCKCHIP_VOP2_EP_MIPI0 {
+ reg = <ROCKCHIP_VOP2_EP_MIPI0>;
+ remote-endpoint = <&dsi0_in_vp1>;
+ };
+};
diff --git a/arch/arm/dts/rk3588-coolpi-cm5-evb-u-boot.dtsi b/arch/arm/dts/rk3588-coolpi-cm5-evb-u-boot.dtsi
new file mode 100644
index 0000000..ed15b14
--- /dev/null
+++ b/arch/arm/dts/rk3588-coolpi-cm5-evb-u-boot.dtsi
@@ -0,0 +1,29 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+
+#include "rk3588-u-boot.dtsi"
+
+&fspim2_pins {
+ bootph-all;
+};
+
+&sdhci {
+ cap-mmc-highspeed;
+ mmc-hs200-1_8v;
+};
+
+&sfc {
+ bootph-pre-ram;
+ u-boot,spl-sfc-no-dma;
+ pinctrl-names = "default";
+ pinctrl-0 = <&fspim2_pins>;
+ status = "okay";
+
+ flash@0 {
+ bootph-pre-ram;
+ compatible = "jedec,spi-nor";
+ reg = <0>;
+ spi-max-frequency = <24000000>;
+ spi-rx-bus-width = <4>;
+ spi-tx-bus-width = <1>;
+ };
+};
diff --git a/arch/arm/dts/rk3588-coolpi-cm5-evb.dts b/arch/arm/dts/rk3588-coolpi-cm5-evb.dts
new file mode 100644
index 0000000..a4946cd
--- /dev/null
+++ b/arch/arm/dts/rk3588-coolpi-cm5-evb.dts
@@ -0,0 +1,216 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (c) 2023 Rockchip Electronics Co., Ltd.
+ *
+ */
+
+/dts-v1/;
+
+#include <dt-bindings/leds/common.h>
+#include "rk3588-coolpi-cm5.dtsi"
+
+/ {
+ model = "RK3588 CoolPi CM5 EVB";
+ compatible = "coolpi,pi-cm5-evb", "coolpi,pi-cm5", "rockchip,rk3588";
+
+ backlight: backlight {
+ compatible = "pwm-backlight";
+ enable-gpios = <&gpio4 RK_PA3 GPIO_ACTIVE_HIGH>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&bl_en>;
+ power-supply = <&vcc12v_dcin>;
+ pwms = <&pwm2 0 25000 0>;
+ };
+
+ leds: leds {
+ compatible = "gpio-leds";
+
+ green_led: led-0 {
+ color = <LED_COLOR_ID_GREEN>;
+ function = LED_FUNCTION_STATUS;
+ gpios = <&gpio3 RK_PB7 GPIO_ACTIVE_HIGH>;
+ linux,default-trigger = "heartbeat";
+ };
+ };
+
+ vcc12v_dcin: vcc12v-dcin-regulator {
+ compatible = "regulator-fixed";
+ regulator-name = "vcc12v_dcin";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <12000000>;
+ regulator-max-microvolt = <12000000>;
+ };
+
+ vcc5v0_sys: vcc5v0-sys-regulator {
+ compatible = "regulator-fixed";
+ regulator-name = "vcc5v0_sys";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <5000000>;
+ regulator-max-microvolt = <5000000>;
+ vin-supply = <&vcc12v_dcin>;
+ };
+
+ vcc3v3_sys: vcc3v3-sys-regulator {
+ compatible = "regulator-fixed";
+ regulator-name = "vcc3v3_sys";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ vin-supply = <&vcc12v_dcin>;
+ };
+
+ vcc3v3_lcd: vcc3v3-lcd-regulator {
+ compatible = "regulator-fixed";
+ regulator-name = "vcc3v3_lcd";
+ enable-active-high;
+ gpio = <&gpio1 RK_PC4 GPIO_ACTIVE_HIGH>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&lcdpwr_en>;
+ vin-supply = <&vcc3v3_sys>;
+ };
+
+ vcc5v0_usb_host1: vcc5v0_usb_host2: vcc5v0-usb-host-regulator {
+ compatible = "regulator-fixed";
+ regulator-name = "vcc5v0_host";
+ regulator-boot-on;
+ regulator-always-on;
+ enable-active-high;
+ regulator-min-microvolt = <5000000>;
+ regulator-max-microvolt = <5000000>;
+ gpio = <&gpio1 RK_PD5 GPIO_ACTIVE_HIGH>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&usb_host_pwren>;
+ vin-supply = <&vcc5v0_sys>;
+ };
+
+ vcc5v0_usb30_otg: vcc5v0-usb30-otg-regulator {
+ compatible = "regulator-fixed";
+ regulator-name = "vcc5v0_otg";
+ regulator-boot-on;
+ regulator-always-on;
+ enable-active-high;
+ regulator-min-microvolt = <5000000>;
+ regulator-max-microvolt = <5000000>;
+ gpios = <&gpio0 RK_PA0 GPIO_ACTIVE_HIGH>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&usb_otg_pwren>;
+ vin-supply = <&vcc5v0_sys>;
+ };
+};
+
+/* M.2 E-Key */
+&pcie2x1l1 {
+ reset-gpios = <&gpio4 RK_PA2 GPIO_ACTIVE_HIGH>;
+ vpcie3v3-supply = <&vcc3v3_sys>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pcie_clkreq &pcie_wake &pcie_rst &wifi_pwron &bt_pwron>;
+ status = "okay";
+};
+
+&pcie30phy {
+ status = "okay";
+};
+
+/* Standard pcie */
+&pcie3x2 {
+ reset-gpios = <&gpio3 RK_PB0 GPIO_ACTIVE_HIGH>;
+ vpcie3v3-supply = <&vcc3v3_sys>;
+ status = "okay";
+};
+
+/* M.2 M-Key ssd */
+&pcie3x4 {
+ num-lanes = <2>;
+ reset-gpios = <&gpio4 RK_PB6 GPIO_ACTIVE_HIGH>;
+ vpcie3v3-supply = <&vcc3v3_sys>;
+ status = "okay";
+};
+
+&pinctrl {
+ lcd {
+ lcdpwr_en: lcdpwr-en {
+ rockchip,pins = <1 RK_PC4 RK_FUNC_GPIO &pcfg_pull_down>;
+ };
+
+ bl_en: bl-en {
+ rockchip,pins = <4 RK_PA3 RK_FUNC_GPIO &pcfg_pull_none>;
+ };
+ };
+
+ usb {
+ usb_host_pwren: usb-host-pwren {
+ rockchip,pins = <1 RK_PD5 RK_FUNC_GPIO &pcfg_pull_up>;
+ };
+
+ usb_otg_pwren: usb-otg-pwren {
+ rockchip,pins = <0 RK_PA0 RK_FUNC_GPIO &pcfg_pull_up>;
+ };
+ };
+
+ wifi {
+ bt_pwron: bt-pwron {
+ rockchip,pins = <3 RK_PA6 RK_FUNC_GPIO &pcfg_pull_up>;
+ };
+
+ pcie_clkreq: pcie-clkreq {
+ rockchip,pins = <4 RK_PA0 RK_FUNC_GPIO &pcfg_pull_up>;
+ };
+
+ pcie_rst: pcie-rst {
+ rockchip,pins = <4 RK_PA2 RK_FUNC_GPIO &pcfg_pull_up>;
+ };
+
+ wifi_pwron: wifi-pwron {
+ rockchip,pins = <3 RK_PB1 RK_FUNC_GPIO &pcfg_pull_up>;
+ };
+
+ pcie_wake: pcie-wake {
+ rockchip,pins = <4 RK_PA1 RK_FUNC_GPIO &pcfg_pull_up>;
+ };
+ };
+};
+
+&pwm2 {
+ status = "okay";
+};
+
+&sata1 {
+ status = "okay";
+};
+
+&u2phy2 {
+ status = "okay";
+};
+
+&u2phy3 {
+ status = "okay";
+};
+
+&u2phy2_host {
+ phy-supply = <&vcc5v0_usb_host1>;
+ status = "okay";
+};
+
+&u2phy3_host {
+ phy-supply = <&vcc5v0_usb_host2>;
+ status = "okay";
+};
+
+&usb_host0_ehci {
+ status = "okay";
+};
+
+&usb_host0_ohci {
+ status = "okay";
+};
+
+&usb_host1_ehci {
+ status = "okay";
+};
+
+&usb_host1_ohci {
+ status = "okay";
+};
diff --git a/arch/arm/dts/rk3588-coolpi-cm5.dtsi b/arch/arm/dts/rk3588-coolpi-cm5.dtsi
new file mode 100644
index 0000000..9cb6d56
--- /dev/null
+++ b/arch/arm/dts/rk3588-coolpi-cm5.dtsi
@@ -0,0 +1,649 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (c) 2023 Rockchip Electronics Co., Ltd.
+ *
+ */
+
+/dts-v1/;
+
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/pwm/pwm.h>
+#include <dt-bindings/pinctrl/rockchip.h>
+#include "rk3588.dtsi"
+
+/ {
+ compatible = "coolpi,pi-cm5", "rockchip,rk3588";
+
+ aliases {
+ mmc0 = &sdhci;
+ mmc1 = &sdmmc;
+ mmc2 = &sdio;
+ };
+
+ analog-sound {
+ compatible = "audio-graph-card";
+ dais = <&i2s0_8ch_p0>;
+ label = "rk3588-es8316";
+ routing = "MIC2", "Mic Jack",
+ "Headphones", "HPOL",
+ "Headphones", "HPOR";
+ widgets = "Microphone", "Mic Jack",
+ "Headphone", "Headphones";
+ };
+
+ chosen {
+ stdout-path = "serial2:1500000n8";
+ };
+
+ avdd0v85_pcie20: avdd0v85-pcie20-regulator {
+ compatible = "regulator-fixed";
+ regulator-name = "avdd0v85_pcie20";
+ regulator-boot-on;
+ regulator-always-on;
+ regulator-min-microvolt = <850000>;
+ regulator-max-microvolt = <850000>;
+ vin-supply = <&vdd_0v85_s0>;
+ };
+
+ avdd1v8_pcie20: avdd1v8-pcie20-regulator {
+ compatible = "regulator-fixed";
+ regulator-name = "avdd1v8_pcie20";
+ regulator-boot-on;
+ regulator-always-on;
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ vin-supply = <&avcc_1v8_s0>;
+ };
+
+ avdd0v75_pcie30: avdd0v75-pcie30-regulator {
+ compatible = "regulator-fixed";
+ regulator-name = "avdd0v75_pcie30";
+ regulator-boot-on;
+ regulator-always-on;
+ regulator-min-microvolt = <750000>;
+ regulator-max-microvolt = <750000>;
+ vin-supply = <&avdd_0v75_s0>;
+ };
+
+ pcie30_avdd1v8: avdd1v8-pcie30-regulator {
+ compatible = "regulator-fixed";
+ regulator-name = "pcie30_avdd1v8";
+ regulator-boot-on;
+ regulator-always-on;
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ vin-supply = <&avcc_1v8_s0>;
+ };
+};
+
+&combphy0_ps {
+ status = "okay";
+};
+
+&combphy1_ps {
+ status = "okay";
+};
+
+&combphy2_psu {
+ status = "okay";
+};
+
+&cpu_b0 {
+ cpu-supply = <&vdd_cpu_big0_s0>;
+};
+
+&cpu_b1 {
+ cpu-supply = <&vdd_cpu_big0_s0>;
+};
+
+&cpu_b2 {
+ cpu-supply = <&vdd_cpu_big1_s0>;
+};
+
+&cpu_b3 {
+ cpu-supply = <&vdd_cpu_big1_s0>;
+};
+
+&cpu_l0 {
+ cpu-supply = <&vdd_cpu_lit_s0>;
+};
+
+&cpu_l1 {
+ cpu-supply = <&vdd_cpu_lit_s0>;
+};
+
+&cpu_l2 {
+ cpu-supply = <&vdd_cpu_lit_s0>;
+};
+
+&cpu_l3 {
+ cpu-supply = <&vdd_cpu_lit_s0>;
+};
+
+&gmac0 {
+ clock_in_out = "output";
+ phy-handle = <&rgmii_phy>;
+ phy-mode = "rgmii-rxid";
+ pinctrl-0 = <&gmac0_miim
+ &gmac0_tx_bus2
+ &gmac0_rx_bus2
+ &gmac0_rgmii_clk
+ &gmac0_rgmii_bus>;
+ pinctrl-names = "default";
+ rx_delay = <0x00>;
+ tx_delay = <0x43>;
+ status = "okay";
+};
+
+&i2c0 {
+ pinctrl-0 = <&i2c0m2_xfer>;
+ status = "okay";
+
+ vdd_cpu_big0_s0: regulator@42 {
+ compatible = "rockchip,rk8602";
+ reg = <0x42>;
+ fcs,suspend-voltage-selector = <1>;
+ regulator-name = "vdd_cpu_big0_s0";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <550000>;
+ regulator-max-microvolt = <1050000>;
+ regulator-ramp-delay = <2300>;
+ vin-supply = <&vcc5v0_sys>;
+
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ };
+ };
+
+ vdd_cpu_big1_s0: regulator@43 {
+ compatible = "rockchip,rk8603", "rockchip,rk8602";
+ reg = <0x43>;
+ fcs,suspend-voltage-selector = <1>;
+ regulator-name = "vdd_cpu_big1_s0";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <550000>;
+ regulator-max-microvolt = <1050000>;
+ regulator-ramp-delay = <2300>;
+ vin-supply = <&vcc5v0_sys>;
+
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ };
+ };
+};
+
+&i2c2 {
+ status = "okay";
+
+ vdd_npu_s0: regulator@42 {
+ compatible = "rockchip,rk8602";
+ reg = <0x42>;
+ fcs,suspend-voltage-selector = <1>;
+ regulator-name = "vdd_npu_s0";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <550000>;
+ regulator-max-microvolt = <950000>;
+ regulator-ramp-delay = <2300>;
+ vin-supply = <&vcc5v0_sys>;
+
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ };
+ };
+};
+
+&i2c6 {
+ status = "okay";
+
+ hym8563: rtc@51 {
+ compatible = "haoyu,hym8563";
+ reg = <0x51>;
+ interrupt-parent = <&gpio0>;
+ interrupts = <RK_PD4 IRQ_TYPE_LEVEL_LOW>;
+ #clock-cells = <0>;
+ clock-output-names = "hym8563";
+ pinctrl-names = "default";
+ pinctrl-0 = <&hym8563_int>;
+ wakeup-source;
+ };
+};
+
+&i2c7 {
+ pinctrl-0 = <&i2c7m0_xfer>;
+ status = "okay";
+
+ es8316: audio-codec@11 {
+ compatible = "everest,es8316";
+ reg = <0x11>;
+ assigned-clocks = <&cru I2S0_8CH_MCLKOUT>;
+ assigned-clock-rates = <12288000>;
+ clocks = <&cru I2S0_8CH_MCLKOUT>;
+ clock-names = "mclk";
+ #sound-dai-cells = <0>;
+
+ port {
+ es8316_p0_0: endpoint {
+ remote-endpoint = <&i2s0_8ch_p0_0>;
+ };
+ };
+ };
+};
+
+&i2s0_8ch {
+ pinctrl-0 = <&i2s0_lrck
+ &i2s0_mclk
+ &i2s0_sclk
+ &i2s0_sdi0
+ &i2s0_sdo0>;
+ status = "okay";
+
+ i2s0_8ch_p0: port {
+ i2s0_8ch_p0_0: endpoint {
+ dai-format = "i2s";
+ mclk-fs = <256>;
+ remote-endpoint = <&es8316_p0_0>;
+ };
+ };
+};
+
+&mdio0 {
+ rgmii_phy: ethernet-phy@1 {
+ /* YT8531C/H */
+ compatible = "ethernet-phy-ieee802.3-c22";
+ reg = <0x1>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&yt8531_rst>;
+ reset-assert-us = <20000>;
+ reset-deassert-us = <100000>;
+ reset-gpios = <&gpio4 RK_PB3 GPIO_ACTIVE_LOW>;
+ };
+};
+
+/* ethernet */
+&pcie2x1l2 {
+ reset-gpios = <&gpio3 RK_PD1 GPIO_ACTIVE_HIGH>;
+ vpcie3v3-supply = <&vcc3v3_sys>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&yt6801_isolate>;
+ status = "okay";
+};
+
+&pinctrl {
+ hym8563 {
+ hym8563_int: hym8563-int {
+ rockchip,pins = <0 RK_PD4 RK_FUNC_GPIO &pcfg_pull_up>;
+ };
+ };
+
+ yt6801 {
+ yt6801_isolate: yt6801-isolate {
+ rockchip,pins = <1 RK_PA4 RK_FUNC_GPIO &pcfg_pull_up>;
+ };
+ };
+
+ yt8531 {
+ yt8531_rst: yt8531-rst {
+ rockchip,pins = <4 RK_PB3 RK_FUNC_GPIO &pcfg_pull_none>;
+ };
+ };
+};
+
+&saradc {
+ vref-supply = <&vcc_1v8_s0>;
+ status = "okay";
+};
+
+&sdhci {
+ bus-width = <8>;
+ max-frequency = <200000000>;
+ mmc-hs400-1_8v;
+ mmc-hs400-enhanced-strobe;
+ no-sdio;
+ no-sd;
+ non-removable;
+ status = "okay";
+};
+
+&sdmmc {
+ bus-width = <4>;
+ cap-mmc-highspeed;
+ cap-sd-highspeed;
+ disable-wp;
+ max-frequency = <150000000>;
+ no-sdio;
+ no-mmc;
+ sd-uhs-sdr104;
+ vqmmc-supply = <&vccio_sd_s0>;
+ status = "okay";
+};
+
+&spi2 {
+ assigned-clocks = <&cru CLK_SPI2>;
+ assigned-clock-rates = <200000000>;
+ num-cs = <1>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&spi2m2_cs0 &spi2m2_pins>;
+ status = "okay";
+
+ pmic@0 {
+ compatible = "rockchip,rk806";
+ reg = <0x0>;
+ interrupt-parent = <&gpio0>;
+ interrupts = <7 IRQ_TYPE_LEVEL_LOW>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pmic_pins>, <&rk806_dvs1_null>,
+ <&rk806_dvs2_null>, <&rk806_dvs3_null>;
+ spi-max-frequency = <1000000>;
+ vcc1-supply = <&vcc5v0_sys>;
+ vcc2-supply = <&vcc5v0_sys>;
+ vcc3-supply = <&vcc5v0_sys>;
+ vcc4-supply = <&vcc5v0_sys>;
+ vcc5-supply = <&vcc5v0_sys>;
+ vcc6-supply = <&vcc5v0_sys>;
+ vcc7-supply = <&vcc5v0_sys>;
+ vcc8-supply = <&vcc5v0_sys>;
+ vcc9-supply = <&vcc5v0_sys>;
+ vcc10-supply = <&vcc5v0_sys>;
+ vcc11-supply = <&vcc_2v0_pldo_s3>;
+ vcc12-supply = <&vcc5v0_sys>;
+ vcc13-supply = <&vcc_2v0_pldo_s3>;
+ vcc14-supply = <&vcc_2v0_pldo_s3>;
+ vcca-supply = <&vcc5v0_sys>;
+
+ rk806_dvs1_null: dvs1-null-pins {
+ pins = "gpio_pwrctrl2";
+ function = "pin_fun0";
+ };
+
+ rk806_dvs2_null: dvs2-null-pins {
+ pins = "gpio_pwrctrl2";
+ function = "pin_fun0";
+ };
+
+ rk806_dvs3_null: dvs3-null-pins {
+ pins = "gpio_pwrctrl3";
+ function = "pin_fun0";
+ };
+
+ regulators {
+ vdd_gpu_s0: vdd_gpu_mem_s0: dcdc-reg1 {
+ regulator-boot-on;
+ regulator-min-microvolt = <550000>;
+ regulator-max-microvolt = <950000>;
+ regulator-ramp-delay = <12500>;
+ regulator-name = "vdd_gpu_s0";
+ regulator-enable-ramp-delay = <400>;
+
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ };
+ };
+
+ vdd_cpu_lit_s0: vdd_cpu_lit_mem_s0: dcdc-reg2 {
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <550000>;
+ regulator-max-microvolt = <950000>;
+ regulator-ramp-delay = <12500>;
+ regulator-name = "vdd_cpu_lit_s0";
+
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ };
+ };
+
+ vdd_log_s0: dcdc-reg3 {
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <675000>;
+ regulator-max-microvolt = <750000>;
+ regulator-ramp-delay = <12500>;
+ regulator-name = "vdd_log_s0";
+
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ regulator-suspend-microvolt = <750000>;
+ };
+ };
+
+ vdd_vdenc_s0: vdd_vdenc_mem_s0: dcdc-reg4 {
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <550000>;
+ regulator-max-microvolt = <950000>;
+ regulator-ramp-delay = <12500>;
+ regulator-name = "vdd_vdenc_s0";
+
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ };
+ };
+
+ vdd_ddr_s0: dcdc-reg5 {
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <675000>;
+ regulator-max-microvolt = <900000>;
+ regulator-ramp-delay = <12500>;
+ regulator-name = "vdd_ddr_s0";
+
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ regulator-suspend-microvolt = <850000>;
+ };
+ };
+
+ vdd2_ddr_s3: dcdc-reg6 {
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-name = "vdd2_ddr_s3";
+
+ regulator-state-mem {
+ regulator-on-in-suspend;
+ };
+ };
+
+ vcc_2v0_pldo_s3: dcdc-reg7 {
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <2000000>;
+ regulator-max-microvolt = <2000000>;
+ regulator-ramp-delay = <12500>;
+ regulator-name = "vdd_2v0_pldo_s3";
+
+ regulator-state-mem {
+ regulator-on-in-suspend;
+ regulator-suspend-microvolt = <2000000>;
+ };
+ };
+
+ vcc_3v3_s3: dcdc-reg8 {
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-name = "vcc_3v3_s3";
+
+ regulator-state-mem {
+ regulator-on-in-suspend;
+ regulator-suspend-microvolt = <3300000>;
+ };
+ };
+
+ vddq_ddr_s0: dcdc-reg9 {
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-name = "vddq_ddr_s0";
+
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ };
+ };
+
+ vcc_1v8_s3: dcdc-reg10 {
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-name = "vcc_1v8_s3";
+
+ regulator-state-mem {
+ regulator-on-in-suspend;
+ regulator-suspend-microvolt = <1800000>;
+ };
+ };
+
+ avcc_1v8_s0: pldo-reg1 {
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-name = "avcc_1v8_s0";
+
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ };
+ };
+
+ vcc_1v8_s0: pldo-reg2 {
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-name = "vcc_1v8_s0";
+
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ regulator-suspend-microvolt = <1800000>;
+ };
+ };
+
+ avdd_1v2_s0: pldo-reg3 {
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <1200000>;
+ regulator-max-microvolt = <1200000>;
+ regulator-name = "avdd_1v2_s0";
+
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ };
+ };
+
+ vcc_3v3_s0: pldo-reg4 {
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-ramp-delay = <12500>;
+ regulator-name = "vcc_3v3_s0";
+
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ };
+ };
+
+ vccio_sd_s0: pldo-reg5 {
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-ramp-delay = <12500>;
+ regulator-name = "vccio_sd_s0";
+
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ };
+ };
+
+ pldo6_s3: pldo-reg6 {
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-name = "pldo6_s3";
+
+ regulator-state-mem {
+ regulator-on-in-suspend;
+ regulator-suspend-microvolt = <1800000>;
+ };
+ };
+
+ vdd_0v75_s3: nldo-reg1 {
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <750000>;
+ regulator-max-microvolt = <750000>;
+ regulator-name = "vdd_0v75_s3";
+
+ regulator-state-mem {
+ regulator-on-in-suspend;
+ regulator-suspend-microvolt = <750000>;
+ };
+ };
+
+ vdd_ddr_pll_s0: nldo-reg2 {
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <850000>;
+ regulator-max-microvolt = <850000>;
+ regulator-name = "vdd_ddr_pll_s0";
+
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ regulator-suspend-microvolt = <850000>;
+ };
+ };
+
+ avdd_0v75_s0: nldo-reg3 {
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <750000>;
+ regulator-max-microvolt = <750000>;
+ regulator-name = "avdd_0v75_s0";
+
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ };
+ };
+
+ vdd_0v85_s0: nldo-reg4 {
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <850000>;
+ regulator-max-microvolt = <850000>;
+ regulator-name = "vdd_0v85_s0";
+
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ };
+ };
+
+ vdd_0v75_s0: nldo-reg5 {
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <750000>;
+ regulator-max-microvolt = <750000>;
+ regulator-name = "vdd_0v75_s0";
+
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ };
+ };
+ };
+ };
+};
+
+&tsadc {
+ status = "okay";
+};
+
+&uart2 {
+ pinctrl-0 = <&uart2m0_xfer>;
+ status = "okay";
+};
diff --git a/arch/arm/dts/rk3588-generic-u-boot.dtsi b/arch/arm/dts/rk3588-generic-u-boot.dtsi
new file mode 100644
index 0000000..853ed58
--- /dev/null
+++ b/arch/arm/dts/rk3588-generic-u-boot.dtsi
@@ -0,0 +1,3 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+
+#include "rk3588s-u-boot.dtsi"
diff --git a/arch/arm/dts/rk3588-generic.dts b/arch/arm/dts/rk3588-generic.dts
new file mode 100644
index 0000000..e4721d9
--- /dev/null
+++ b/arch/arm/dts/rk3588-generic.dts
@@ -0,0 +1,44 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Minimal generic DT for RK3588S/RK3588 with eMMC and SD-card enabled
+ */
+
+/dts-v1/;
+#include "rk3588s.dtsi"
+
+/ {
+ model = "Generic RK3588S/RK3588";
+ compatible = "rockchip,rk3588";
+
+ aliases {
+ mmc0 = &sdhci;
+ mmc1 = &sdmmc;
+ };
+
+ chosen {
+ stdout-path = "serial2:1500000n8";
+ };
+};
+
+&sdhci {
+ bus-width = <8>;
+ cap-mmc-highspeed;
+ mmc-hs200-1_8v;
+ no-sd;
+ no-sdio;
+ non-removable;
+ status = "okay";
+};
+
+&sdmmc {
+ bus-width = <4>;
+ cap-sd-highspeed;
+ disable-wp;
+ no-mmc;
+ no-sdio;
+ status = "okay";
+};
+
+&uart2 {
+ status = "okay";
+};
diff --git a/arch/arm/dts/rk3588-jaguar-u-boot.dtsi b/arch/arm/dts/rk3588-jaguar-u-boot.dtsi
new file mode 100644
index 0000000..dcda4f9
--- /dev/null
+++ b/arch/arm/dts/rk3588-jaguar-u-boot.dtsi
@@ -0,0 +1,33 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (c) 2023 Theobroma Systems Design und Consulting GmbH
+ */
+
+#include "rk3588-u-boot.dtsi"
+
+/ {
+ chosen {
+ u-boot,spl-boot-order = "same-as-spl", &sdhci, &sdmmc;
+ };
+};
+
+&emmc_pwrseq {
+ bootph-pre-ram;
+ bootph-some-ram;
+};
+
+&emmc_reset {
+ bootph-pre-ram;
+ bootph-some-ram;
+};
+
+&gpio2 {
+ bootph-pre-ram;
+ bootph-some-ram;
+};
+
+&sdhci {
+ /* U-Boot currently cannot handle anything below HS200 for eMMC on RK3588 */
+ /delete-property/ mmc-ddr-1_8v;
+ /delete-property/ cap-mmc-highspeed;
+};
diff --git a/arch/arm/dts/rk3588-jaguar.dts b/arch/arm/dts/rk3588-jaguar.dts
new file mode 100644
index 0000000..4ce70fb
--- /dev/null
+++ b/arch/arm/dts/rk3588-jaguar.dts
@@ -0,0 +1,803 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (c) 2023 Theobroma Systems Design und Consulting GmbH
+ */
+
+/dts-v1/;
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/input/input.h>
+#include <dt-bindings/leds/common.h>
+#include <dt-bindings/pinctrl/rockchip.h>
+#include <dt-bindings/usb/pd.h>
+#include "rk3588.dtsi"
+
+/ {
+ model = "Theobroma Systems RK3588-SBC Jaguar";
+ compatible = "tsd,rk3588-jaguar", "rockchip,rk3588";
+
+ adc-keys {
+ compatible = "adc-keys";
+ io-channels = <&saradc 0>;
+ io-channel-names = "buttons";
+ keyup-threshold-microvolt = <1800000>;
+ poll-interval = <100>;
+
+ /* Can be controlled through SW2 but also GPIO1 on CP2102 on P20 */
+ button-bios-disable {
+ label = "BIOS_DISABLE";
+ linux,code = <KEY_VENDOR>;
+ press-threshold-microvolt = <0>;
+ };
+ };
+
+ aliases {
+ ethernet0 = &gmac0;
+ mmc0 = &sdhci;
+ mmc1 = &sdmmc;
+ rtc0 = &rtc_twi;
+ };
+
+ chosen {
+ stdout-path = "serial2:115200n8";
+ };
+
+ /* DCIN is 12-24V but standard is 12V */
+ dc_12v: dc-12v-regulator {
+ compatible = "regulator-fixed";
+ regulator-name = "dc_12v";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <12000000>;
+ regulator-max-microvolt = <12000000>;
+ };
+
+ emmc_pwrseq: emmc-pwrseq {
+ compatible = "mmc-pwrseq-emmc";
+ pinctrl-0 = <&emmc_reset>;
+ pinctrl-names = "default";
+ reset-gpios = <&gpio2 RK_PA3 GPIO_ACTIVE_HIGH>;
+ };
+
+ leds {
+ compatible = "gpio-leds";
+ pinctrl-names = "default";
+ pinctrl-0 = <&led1_pin>;
+ status = "okay";
+
+ /* LED1 on PCB */
+ led-1 {
+ gpios = <&gpio1 RK_PD4 GPIO_ACTIVE_HIGH>;
+ function = LED_FUNCTION_HEARTBEAT;
+ linux,default-trigger = "heartbeat";
+ color = <LED_COLOR_ID_AMBER>;
+ };
+ };
+
+ pps {
+ compatible = "pps-gpio";
+ gpios = <&gpio0 RK_PD5 GPIO_ACTIVE_HIGH>;
+ };
+
+ vcc_1v1_nldo_s3: vcc-1v1-nldo-s3-regulator {
+ compatible = "regulator-fixed";
+ regulator-name = "vcc_1v1_nldo_s3";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <1100000>;
+ regulator-max-microvolt = <1100000>;
+ vin-supply = <&vcc5v0_sys>;
+ };
+
+ vcc_1v2_s3: vcc-1v2-s3-regulator {
+ compatible = "regulator-fixed";
+ regulator-name = "vcc_1v2_s3";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <1200000>;
+ regulator-max-microvolt = <1200000>;
+ vin-supply = <&vcc5v0_sys>;
+ };
+
+ /* Exposed on P14 and P15 */
+ vcc_2v8_s3: vcc-2v8-s3-regulator {
+ compatible = "regulator-fixed";
+ regulator-name = "vcc_2v8_s3";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <2800000>;
+ regulator-max-microvolt = <2800000>;
+ vin-supply = <&vcc_3v3_s3>;
+ };
+
+ vcc_5v0_usb_a: vcc-5v0-usb-a-regulator {
+ compatible = "regulator-fixed";
+ regulator-name = "usb_a_vcc";
+ regulator-min-microvolt = <5000000>;
+ regulator-max-microvolt = <5000000>;
+ vin-supply = <&vcc5v0_sys>;
+ gpio = <&gpio1 RK_PB4 GPIO_ACTIVE_HIGH>;
+ enable-active-high;
+ };
+
+ vcc_5v0_usb_c1: vcc-5v0-usb-c1-regulator {
+ compatible = "regulator-fixed";
+ regulator-name = "5v_usbc1";
+ regulator-min-microvolt = <5000000>;
+ regulator-max-microvolt = <5000000>;
+ vin-supply = <&vcc5v0_usb>;
+ gpio = <&gpio4 RK_PB5 GPIO_ACTIVE_HIGH>;
+ enable-active-high;
+ };
+
+ vcc_5v0_usb_c2: vcc-5v0-usb-c2-regulator {
+ compatible = "regulator-fixed";
+ regulator-name = "5v_usbc2";
+ regulator-min-microvolt = <5000000>;
+ regulator-max-microvolt = <5000000>;
+ vin-supply = <&vcc5v0_usb>;
+ gpio = <&gpio4 RK_PB6 GPIO_ACTIVE_HIGH>;
+ enable-active-high;
+ };
+
+ vcc3v3_mdot2: vcc3v3-mdot2-regulator {
+ compatible = "regulator-fixed";
+ regulator-name = "vcc3v3_mdot2";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ vin-supply = <&dc_12v>;
+ };
+
+ vcc5v0_sys: vcc5v0-sys-regulator {
+ compatible = "regulator-fixed";
+ regulator-name = "vcc5v0_sys";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <5000000>;
+ regulator-max-microvolt = <5000000>;
+ vin-supply = <&dc_12v>;
+ };
+
+ vcc5v0_usb: vcc5v0-usb-regulator {
+ compatible = "regulator-fixed";
+ regulator-name = "vcc5v0_usb";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <5000000>;
+ regulator-max-microvolt = <5000000>;
+ vin-supply = <&vcc5v0_sys>;
+ };
+};
+
+&combphy1_ps {
+ status = "okay";
+};
+
+&cpu_b0 {
+ cpu-supply = <&vdd_cpu_big0_s0>;
+};
+
+&cpu_b1 {
+ cpu-supply = <&vdd_cpu_big0_s0>;
+};
+
+&cpu_b2 {
+ cpu-supply = <&vdd_cpu_big1_s0>;
+};
+
+&cpu_b3 {
+ cpu-supply = <&vdd_cpu_big1_s0>;
+};
+
+&cpu_l0 {
+ cpu-supply = <&vdd_cpu_lit_s0>;
+};
+
+&cpu_l1 {
+ cpu-supply = <&vdd_cpu_lit_s0>;
+};
+
+&cpu_l2 {
+ cpu-supply = <&vdd_cpu_lit_s0>;
+};
+
+&cpu_l3 {
+ cpu-supply = <&vdd_cpu_lit_s0>;
+};
+
+&gmac0 {
+ clock_in_out = "output";
+ phy-handle = <&rgmii_phy>;
+ phy-mode = "rgmii";
+ phy-supply = <&vcc_1v2_s3>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&gmac0_miim
+ &gmac0_rx_bus2
+ &gmac0_tx_bus2
+ &gmac0_rgmii_clk
+ &gmac0_rgmii_bus
+ ð0_pins
+ ð_reset>;
+ tx_delay = <0x10>;
+ rx_delay = <0x10>;
+ snps,reset-gpio = <&gpio4 RK_PC3 GPIO_ACTIVE_LOW>;
+ snps,reset-active-low;
+ snps,reset-delays-us = <0 10000 100000>;
+
+ status = "okay";
+};
+
+&gpio1 {
+ mdot2e-w-disable1-n-hog {
+ gpios = <RK_PB1 GPIO_ACTIVE_LOW>;
+ output-low;
+ line-name = "m.2 E-key W_DISABLE1#";
+ gpio-hog;
+ };
+};
+
+&gpio4 {
+ mdot2e-w-disable2-n-hog {
+ gpios = <RK_PC1 GPIO_ACTIVE_LOW>;
+ output-low;
+ line-name = "m.2 E-key W_DISABLE2#";
+ gpio-hog;
+ };
+};
+
+&i2c0 {
+ pinctrl-0 = <&i2c0m2_xfer>;
+ status = "okay";
+
+ fan@18 {
+ compatible = "ti,amc6821";
+ reg = <0x18>;
+ };
+
+ vdd_npu_s0: regulator@42 {
+ compatible = "rockchip,rk8602";
+ reg = <0x42>;
+ fcs,suspend-voltage-selector = <1>;
+ regulator-name = "vdd_npu_s0";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <550000>;
+ regulator-max-microvolt = <950000>;
+ regulator-ramp-delay = <2300>;
+ vin-supply = <&vcc5v0_sys>;
+
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ };
+ };
+
+ vdd_cpu_big1_s0: regulator@43 {
+ compatible = "rockchip,rk8603", "rockchip,rk8602";
+ reg = <0x43>;
+ fcs,suspend-voltage-selector = <1>;
+ regulator-name = "vdd_cpu_big1_s0";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <550000>;
+ regulator-max-microvolt = <1050000>;
+ regulator-ramp-delay = <2300>;
+ vin-supply = <&vcc5v0_sys>;
+
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ };
+ };
+
+ rtc_twi: rtc@6f {
+ compatible = "isil,isl1208";
+ reg = <0x6f>;
+ };
+};
+
+&i2c1 {
+ pinctrl-0 = <&i2c1m4_xfer>;
+};
+
+&i2c6 {
+ pinctrl-0 = <&i2c6m4_xfer>;
+};
+
+&i2c7 {
+ status = "okay";
+
+ /* SE050 Secure Element at 0x48; GPIO1_A4 for enable pin */
+
+ /* Also on 0x55 */
+ eeprom@54 {
+ compatible = "st,24c04", "atmel,24c04";
+ reg = <0x54>;
+ pagesize = <16>;
+ vcc-supply = <&vcc_3v3_s3>;
+ };
+};
+
+&i2c8 {
+ pinctrl-0 = <&i2c8m2_xfer>;
+ status = "okay";
+
+ vdd_cpu_big0_s0: regulator@42 {
+ compatible = "rockchip,rk8602";
+ reg = <0x42>;
+ fcs,suspend-voltage-selector = <1>;
+ regulator-name = "vdd_cpu_big0_s0";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <550000>;
+ regulator-max-microvolt = <1050000>;
+ regulator-ramp-delay = <2300>;
+ vin-supply = <&vcc5v0_sys>;
+
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ };
+ };
+};
+
+&mdio0 {
+ rgmii_phy: ethernet-phy@6 {
+ /* KSZ9031 or KSZ9131 */
+ compatible = "ethernet-phy-ieee802.3-c22";
+ reg = <0x6>;
+ clocks = <&cru REFCLKO25M_ETH0_OUT>;
+ };
+};
+
+&pcie2x1l0 {
+ reset-gpios = <&gpio4 RK_PB3 GPIO_ACTIVE_HIGH>; /* WIFI_PERST0# */
+ vpcie3v3-supply = <&vcc3v3_mdot2>;
+ status = "okay";
+};
+
+&pinctrl {
+ emmc {
+ emmc_reset: emmc-reset {
+ rockchip,pins = <2 RK_PA3 RK_FUNC_GPIO &pcfg_pull_none>;
+ };
+ };
+
+ ethernet {
+ eth_reset: eth-reset {
+ rockchip,pins = <4 RK_PC3 RK_FUNC_GPIO &pcfg_pull_none>;
+ };
+ };
+
+ leds {
+ led1_pin: led1-pin {
+ rockchip,pins = <1 RK_PD4 RK_FUNC_GPIO &pcfg_pull_none>;
+ };
+ };
+};
+
+&saradc {
+ vref-supply = <&vcc_1v8_s0>;
+ status = "okay";
+};
+
+&sdhci {
+ bus-width = <8>;
+ cap-mmc-highspeed;
+ mmc-ddr-1_8v;
+ mmc-hs200-1_8v;
+ mmc-hs400-1_8v;
+ mmc-hs400-enhanced-strobe;
+ mmc-pwrseq = <&emmc_pwrseq>;
+ no-sdio;
+ no-sd;
+ non-removable;
+ pinctrl-names = "default";
+ pinctrl-0 = <&emmc_bus8 &emmc_cmd &emmc_clk &emmc_data_strobe>;
+ supports-cqe;
+ vmmc-supply = <&vcc_3v3_s3>;
+ vqmmc-supply = <&vcc_1v8_s3>;
+ status = "okay";
+};
+
+&sdmmc {
+ broken-cd;
+ bus-width = <4>;
+ cap-sd-highspeed;
+ disable-wp;
+ max-frequency = <150000000>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&sdmmc_bus4 &sdmmc_cmd &sdmmc_clk>;
+ sd-uhs-sdr12;
+ sd-uhs-sdr25;
+ sd-uhs-sdr50;
+ sd-uhs-ddr50;
+ sd-uhs-sdr104;
+ vmmc-supply = <&vcc_3v3_s3>;
+ vqmmc-supply = <&vccio_sd_s0>;
+ status = "okay";
+};
+
+&spi2 {
+ assigned-clocks = <&cru CLK_SPI2>;
+ assigned-clock-rates = <200000000>;
+ num-cs = <1>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&spi2m2_cs0 &spi2m2_pins>;
+ status = "okay";
+
+ pmic@0 {
+ compatible = "rockchip,rk806";
+ reg = <0x0>;
+ interrupt-parent = <&gpio0>;
+ interrupts = <7 IRQ_TYPE_LEVEL_LOW>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pmic_pins>, <&rk806_dvs1_null>,
+ <&rk806_dvs2_null>, <&rk806_dvs3_null>;
+ spi-max-frequency = <1000000>;
+ system-power-controller;
+ vcc1-supply = <&vcc5v0_sys>;
+ vcc2-supply = <&vcc5v0_sys>;
+ vcc3-supply = <&vcc5v0_sys>;
+ vcc4-supply = <&vcc5v0_sys>;
+ vcc5-supply = <&vcc5v0_sys>;
+ vcc6-supply = <&vcc5v0_sys>;
+ vcc7-supply = <&vcc5v0_sys>;
+ vcc8-supply = <&vcc5v0_sys>;
+ vcc9-supply = <&vcc5v0_sys>;
+ vcc10-supply = <&vcc5v0_sys>;
+ vcc11-supply = <&vcc_2v0_pldo_s3>;
+ vcc12-supply = <&vcc5v0_sys>;
+ vcc13-supply = <&vcc_1v1_nldo_s3>;
+ vcc14-supply = <&vcc_1v1_nldo_s3>;
+ vcca-supply = <&vcc5v0_sys>;
+
+ rk806_dvs1_null: dvs1-null-pins {
+ pins = "gpio_pwrctrl2";
+ function = "pin_fun0";
+ };
+
+ rk806_dvs2_null: dvs2-null-pins {
+ pins = "gpio_pwrctrl2";
+ function = "pin_fun0";
+ };
+
+ rk806_dvs3_null: dvs3-null-pins {
+ pins = "gpio_pwrctrl3";
+ function = "pin_fun0";
+ };
+
+ regulators {
+ vdd_gpu_s0: dcdc-reg1 {
+ regulator-boot-on;
+ regulator-min-microvolt = <550000>;
+ regulator-max-microvolt = <950000>;
+ regulator-ramp-delay = <12500>;
+ regulator-name = "vdd_gpu_s0";
+ regulator-enable-ramp-delay = <400>;
+
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ };
+ };
+
+ vdd_cpu_lit_s0: dcdc-reg2 {
+ regulator-name = "vdd_cpu_lit_s0";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <550000>;
+ regulator-max-microvolt = <950000>;
+ regulator-ramp-delay = <12500>;
+
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ };
+ };
+
+ vdd_log_s0: dcdc-reg3 {
+ regulator-name = "vdd_log_s0";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <675000>;
+ regulator-max-microvolt = <750000>;
+ regulator-ramp-delay = <12500>;
+
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ regulator-suspend-microvolt = <750000>;
+ };
+ };
+
+ vdd_vdenc_s0: dcdc-reg4 {
+ regulator-name = "vdd_vdenc_s0";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <550000>;
+ regulator-max-microvolt = <950000>;
+ regulator-ramp-delay = <12500>;
+
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ };
+ };
+
+ vdd_ddr_s0: dcdc-reg5 {
+ regulator-name = "vdd_ddr_s0";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <675000>;
+ regulator-max-microvolt = <900000>;
+ regulator-ramp-delay = <12500>;
+
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ regulator-suspend-microvolt = <850000>;
+ };
+ };
+
+ vdd2_ddr_s3: dcdc-reg6 {
+ regulator-name = "vdd2_ddr_s3";
+ regulator-always-on;
+ regulator-boot-on;
+
+ regulator-state-mem {
+ regulator-on-in-suspend;
+ };
+ };
+
+ vcc_2v0_pldo_s3: dcdc-reg7 {
+ regulator-name = "vdd_2v0_pldo_s3";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <2000000>;
+ regulator-max-microvolt = <2000000>;
+ regulator-ramp-delay = <12500>;
+
+ regulator-state-mem {
+ regulator-on-in-suspend;
+ regulator-suspend-microvolt = <2000000>;
+ };
+ };
+
+ vcc_3v3_s3: dcdc-reg8 {
+ regulator-name = "vcc_3v3_s3";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+
+ regulator-state-mem {
+ regulator-on-in-suspend;
+ regulator-suspend-microvolt = <3300000>;
+ };
+ };
+
+ vddq_ddr_s0: dcdc-reg9 {
+ regulator-name = "vddq_ddr_s0";
+ regulator-always-on;
+ regulator-boot-on;
+
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ };
+ };
+
+ vcc_1v8_s3: dcdc-reg10 {
+ regulator-name = "vcc_1v8_s3";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+
+ regulator-state-mem {
+ regulator-on-in-suspend;
+ regulator-suspend-microvolt = <1800000>;
+ };
+ };
+
+ vcca_1v8_s0: pldo-reg1 {
+ regulator-name = "vcca_1v8_s0";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ };
+ };
+
+ vcc_1v8_s0: pldo-reg2 {
+ regulator-name = "vcc_1v8_s0";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ regulator-suspend-microvolt = <1800000>;
+ };
+ };
+
+ vdda_1v2_s0: pldo-reg3 {
+ regulator-name = "vdda_1v2_s0";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <1200000>;
+ regulator-max-microvolt = <1200000>;
+
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ };
+ };
+
+ vcca_3v3_s0: pldo-reg4 {
+ regulator-name = "vcca_3v3_s0";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-ramp-delay = <12500>;
+
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ };
+ };
+
+ vccio_sd_s0: pldo-reg5 {
+ regulator-name = "vccio_sd_s0";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-ramp-delay = <12500>;
+
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ };
+ };
+
+ pldo6_s3: pldo-reg6 {
+ regulator-name = "pldo6_s3";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+
+ regulator-state-mem {
+ regulator-on-in-suspend;
+ regulator-suspend-microvolt = <1800000>;
+ };
+ };
+
+ vdd_0v75_s3: nldo-reg1 {
+ regulator-name = "vdd_0v75_s3";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <750000>;
+ regulator-max-microvolt = <750000>;
+
+ regulator-state-mem {
+ regulator-on-in-suspend;
+ regulator-suspend-microvolt = <750000>;
+ };
+ };
+
+ vdda_ddr_pll_s0: nldo-reg2 {
+ regulator-name = "vdda_ddr_pll_s0";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <850000>;
+ regulator-max-microvolt = <850000>;
+
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ regulator-suspend-microvolt = <850000>;
+ };
+ };
+
+ vdda_0v75_s0: nldo-reg3 {
+ regulator-name = "vdda_0v75_s0";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <750000>;
+ regulator-max-microvolt = <750000>;
+
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ };
+ };
+
+ vdda_0v85_s0: nldo-reg4 {
+ regulator-name = "vdda_0v85_s0";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <850000>;
+ regulator-max-microvolt = <850000>;
+
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ };
+ };
+
+ vdd_0v75_s0: nldo-reg5 {
+ regulator-name = "vdd_0v75_s0";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <750000>;
+ regulator-max-microvolt = <750000>;
+
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ };
+ };
+ };
+ };
+};
+
+&tsadc {
+ status = "okay";
+};
+
+&u2phy2 {
+ status = "okay";
+};
+
+&u2phy2_host {
+ phy-supply = <&vcc_5v0_usb_a>;
+ status = "okay";
+};
+
+&u2phy3 {
+ status = "okay";
+};
+
+&u2phy3_host {
+ status = "okay";
+};
+
+/* Mule-ATtiny debug UART; typically baudrate 9600 */
+&uart0 {
+ pinctrl-0 = <&uart0m0_xfer>;
+ status = "okay";
+};
+
+/* Main debug interface on P20 micro-USB B port and P21 header */
+&uart2 {
+ pinctrl-0 = <&uart2m0_xfer>;
+ status = "okay";
+};
+
+/* RS485 on P19 */
+&uart3 {
+ pinctrl-0 = <&uart3m2_xfer &uart3_rtsn>;
+ linux,rs485-enabled-at-boot-time;
+ status = "okay";
+};
+
+/* Mule-ATtiny UPDI flashing UART */
+&uart7 {
+ pinctrl-0 = <&uart7m0_xfer>;
+ status = "okay";
+};
+
+/* host0 on P10 USB-A */
+&usb_host0_ehci {
+ status = "okay";
+};
+
+/* host0 on P10 USB-A */
+&usb_host0_ohci {
+ status = "okay";
+};
+
+/* host1 on M.2 E-key */
+&usb_host1_ehci {
+ status = "okay";
+};
+
+/* host1 on M.2 E-key */
+&usb_host1_ohci {
+ status = "okay";
+};
diff --git a/arch/arm/dts/rk3588-toybrick-x0-u-boot.dtsi b/arch/arm/dts/rk3588-toybrick-x0-u-boot.dtsi
new file mode 100644
index 0000000..1aeb541
--- /dev/null
+++ b/arch/arm/dts/rk3588-toybrick-x0-u-boot.dtsi
@@ -0,0 +1,12 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (c) 2024 Rockchip Electronics Co., Ltd.
+ */
+
+#include "rk3588-u-boot.dtsi"
+
+/ {
+ chosen {
+ u-boot,spl-boot-order = "same-as-spl", &sdhci;
+ };
+};
diff --git a/arch/arm/dts/rk3588-toybrick-x0.dts b/arch/arm/dts/rk3588-toybrick-x0.dts
new file mode 100644
index 0000000..9090c5c
--- /dev/null
+++ b/arch/arm/dts/rk3588-toybrick-x0.dts
@@ -0,0 +1,688 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (c) 2024 Rockchip Electronics Co., Ltd.
+ *
+ */
+
+/dts-v1/;
+
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/input/input.h>
+#include <dt-bindings/pinctrl/rockchip.h>
+#include "rk3588.dtsi"
+
+/ {
+ model = "Rockchip Toybrick TB-RK3588X Board";
+ compatible = "rockchip,rk3588-toybrick-x0", "rockchip,rk3588";
+
+ aliases {
+ mmc0 = &sdhci;
+ };
+
+ chosen {
+ stdout-path = "serial2:1500000n8";
+ };
+
+ adc-keys {
+ compatible = "adc-keys";
+ io-channels = <&saradc 1>;
+ io-channel-names = "buttons";
+ keyup-threshold-microvolt = <1800000>;
+ poll-interval = <100>;
+
+ button-vol-up {
+ label = "Volume Up";
+ linux,code = <KEY_VOLUMEUP>;
+ press-threshold-microvolt = <17000>;
+ };
+
+ button-vol-down {
+ label = "Volume Down";
+ linux,code = <KEY_VOLUMEDOWN>;
+ press-threshold-microvolt = <417000>;
+ };
+
+ button-menu {
+ label = "Menu";
+ linux,code = <KEY_MENU>;
+ press-threshold-microvolt = <890000>;
+ };
+
+ button-escape {
+ label = "Escape";
+ linux,code = <KEY_ESC>;
+ press-threshold-microvolt = <1235000>;
+ };
+ };
+
+ backlight: backlight {
+ compatible = "pwm-backlight";
+ power-supply = <&vcc12v_dcin>;
+ pwms = <&pwm2 0 25000 0>;
+ };
+
+ pcie20_avdd0v85: pcie20-avdd0v85-regulator {
+ compatible = "regulator-fixed";
+ regulator-name = "pcie20_avdd0v85";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <850000>;
+ regulator-max-microvolt = <850000>;
+ vin-supply = <&vdd_0v85_s0>;
+ };
+
+ pcie20_avdd1v8: pcie20-avdd1v8-regulator {
+ compatible = "regulator-fixed";
+ regulator-name = "pcie20_avdd1v8";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ vin-supply = <&avcc_1v8_s0>;
+ };
+
+ pcie30_avdd0v75: pcie30-avdd0v75-regulator {
+ compatible = "regulator-fixed";
+ regulator-name = "pcie30_avdd0v75";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <750000>;
+ regulator-max-microvolt = <750000>;
+ vin-supply = <&avdd_0v75_s0>;
+ };
+
+ pcie30_avdd1v8: pcie30-avdd1v8-regulator {
+ compatible = "regulator-fixed";
+ regulator-name = "pcie30_avdd1v8";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ vin-supply = <&avcc_1v8_s0>;
+ };
+
+ vcc12v_dcin: vcc12v-dcin-regulator {
+ compatible = "regulator-fixed";
+ regulator-name = "vcc12v_dcin";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <12000000>;
+ regulator-max-microvolt = <12000000>;
+ };
+
+ vcc5v0_host: vcc5v0-host-regulator {
+ compatible = "regulator-fixed";
+ enable-active-high;
+ gpio = <&gpio4 RK_PB0 GPIO_ACTIVE_HIGH>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&vcc5v0_host_en>;
+ regulator-name = "vcc5v0_host";
+ regulator-boot-on;
+ regulator-always-on;
+ regulator-min-microvolt = <5000000>;
+ regulator-max-microvolt = <5000000>;
+ vin-supply = <&vcc5v0_usb>;
+ };
+
+ vcc5v0_sys: vcc5v0-sys-regulator {
+ compatible = "regulator-fixed";
+ regulator-name = "vcc5v0_sys";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <5000000>;
+ regulator-max-microvolt = <5000000>;
+ vin-supply = <&vcc12v_dcin>;
+ };
+
+ vcc5v0_usbdcin: vcc5v0-usbdcin-regulator {
+ compatible = "regulator-fixed";
+ regulator-name = "vcc5v0_usbdcin";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <5000000>;
+ regulator-max-microvolt = <5000000>;
+ vin-supply = <&vcc12v_dcin>;
+ };
+
+ vcc5v0_usb: vcc5v0-usb-regulator {
+ compatible = "regulator-fixed";
+ regulator-name = "vcc5v0_usb";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <5000000>;
+ regulator-max-microvolt = <5000000>;
+ vin-supply = <&vcc5v0_usbdcin>;
+ };
+
+ vcc_1v1_nldo_s3: vcc-1v1-nldo-s3-regulator {
+ compatible = "regulator-fixed";
+ regulator-name = "vcc_1v1_nldo_s3";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <1100000>;
+ regulator-max-microvolt = <1100000>;
+ vin-supply = <&vcc5v0_sys>;
+ };
+};
+
+&combphy0_ps {
+ status = "okay";
+};
+
+&combphy2_psu {
+ status = "okay";
+};
+
+&cpu_b0 {
+ cpu-supply = <&vdd_cpu_big0_s0>;
+};
+
+&cpu_b1 {
+ cpu-supply = <&vdd_cpu_big0_s0>;
+};
+
+&cpu_b2 {
+ cpu-supply = <&vdd_cpu_big1_s0>;
+};
+
+&cpu_b3 {
+ cpu-supply = <&vdd_cpu_big1_s0>;
+};
+
+&cpu_l0 {
+ cpu-supply = <&vdd_cpu_lit_s0>;
+};
+
+&cpu_l1 {
+ cpu-supply = <&vdd_cpu_lit_s0>;
+};
+
+&cpu_l2 {
+ cpu-supply = <&vdd_cpu_lit_s0>;
+};
+
+&cpu_l3 {
+ cpu-supply = <&vdd_cpu_lit_s0>;
+};
+
+&gmac0 {
+ clock_in_out = "output";
+ phy-handle = <&rgmii_phy>;
+ phy-mode = "rgmii-rxid";
+ pinctrl-0 = <&gmac0_miim
+ &gmac0_tx_bus2
+ &gmac0_rx_bus2
+ &gmac0_rgmii_clk
+ &gmac0_rgmii_bus>;
+ pinctrl-names = "default";
+ rx_delay = <0x00>;
+ tx_delay = <0x43>;
+ status = "okay";
+};
+
+&i2c0 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&i2c0m2_xfer>;
+ status = "okay";
+
+ vdd_cpu_big0_s0: regulator@42 {
+ compatible = "rockchip,rk8602";
+ reg = <0x42>;
+ fcs,suspend-voltage-selector = <1>;
+ regulator-name = "vdd_cpu_big0_s0";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <550000>;
+ regulator-max-microvolt = <1050000>;
+ regulator-ramp-delay = <2300>;
+ vin-supply = <&vcc5v0_sys>;
+
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ };
+ };
+
+ vdd_cpu_big1_s0: regulator@43 {
+ compatible = "rockchip,rk8603", "rockchip,rk8602";
+ reg = <0x43>;
+ fcs,suspend-voltage-selector = <1>;
+ regulator-name = "vdd_cpu_big1_s0";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <550000>;
+ regulator-max-microvolt = <1050000>;
+ regulator-ramp-delay = <2300>;
+ vin-supply = <&vcc5v0_sys>;
+
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ };
+ };
+};
+
+&i2c2 {
+ status = "okay";
+
+ hym8563: rtc@51 {
+ compatible = "haoyu,hym8563";
+ reg = <0x51>;
+ #clock-cells = <0>;
+ clock-output-names = "hym8563";
+ interrupt-parent = <&gpio0>;
+ interrupts = <RK_PD4 IRQ_TYPE_LEVEL_LOW>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&hym8563_int>;
+ wakeup-source;
+ };
+};
+
+&mdio0 {
+ rgmii_phy: ethernet-phy@1 {
+ /* RTL8211F */
+ compatible = "ethernet-phy-id001c.c916";
+ reg = <0x1>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&rtl8211f_rst>;
+ reset-assert-us = <20000>;
+ reset-deassert-us = <100000>;
+ reset-gpios = <&gpio4 RK_PB3 GPIO_ACTIVE_LOW>;
+ };
+};
+
+&pinctrl {
+ rtl8211f {
+ rtl8211f_rst: rtl8211f-rst {
+ rockchip,pins = <4 RK_PB3 RK_FUNC_GPIO &pcfg_pull_none>;
+ };
+
+ };
+
+ hym8563 {
+ hym8563_int: hym8563-int {
+ rockchip,pins = <0 RK_PD4 RK_FUNC_GPIO &pcfg_pull_up>;
+ };
+ };
+
+ usb {
+ vcc5v0_host_en: vcc5v0-host-en {
+ rockchip,pins = <4 RK_PB0 RK_FUNC_GPIO &pcfg_pull_none>;
+ };
+ };
+};
+
+&pwm2 {
+ status = "okay";
+};
+
+&saradc {
+ vref-supply = <&vcc_1v8_s0>;
+ status = "okay";
+};
+
+&sdhci {
+ bus-width = <8>;
+ mmc-hs400-1_8v;
+ mmc-hs400-enhanced-strobe;
+ no-sdio;
+ no-sd;
+ non-removable;
+ status = "okay";
+};
+
+&spi2 {
+ assigned-clocks = <&cru CLK_SPI2>;
+ assigned-clock-rates = <200000000>;
+ num-cs = <1>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&spi2m2_cs0 &spi2m2_pins>;
+ status = "okay";
+
+ pmic@0 {
+ compatible = "rockchip,rk806";
+ reg = <0x0>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ interrupt-parent = <&gpio0>;
+ interrupts = <7 IRQ_TYPE_LEVEL_LOW>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pmic_pins>, <&rk806_dvs1_null>,
+ <&rk806_dvs2_null>, <&rk806_dvs3_null>;
+ spi-max-frequency = <1000000>;
+ system-power-controller;
+
+ vcc1-supply = <&vcc5v0_sys>;
+ vcc2-supply = <&vcc5v0_sys>;
+ vcc3-supply = <&vcc5v0_sys>;
+ vcc4-supply = <&vcc5v0_sys>;
+ vcc5-supply = <&vcc5v0_sys>;
+ vcc6-supply = <&vcc5v0_sys>;
+ vcc7-supply = <&vcc5v0_sys>;
+ vcc8-supply = <&vcc5v0_sys>;
+ vcc9-supply = <&vcc5v0_sys>;
+ vcc10-supply = <&vcc5v0_sys>;
+ vcc11-supply = <&vcc_2v0_pldo_s3>;
+ vcc12-supply = <&vcc5v0_sys>;
+ vcc13-supply = <&vcc_1v1_nldo_s3>;
+ vcc14-supply = <&vcc_1v1_nldo_s3>;
+ vcca-supply = <&vcc5v0_sys>;
+
+ rk806_dvs1_null: dvs1-null-pins {
+ pins = "gpio_pwrctrl1";
+ function = "pin_fun0";
+ };
+
+ rk806_dvs2_null: dvs2-null-pins {
+ pins = "gpio_pwrctrl2";
+ function = "pin_fun0";
+ };
+
+ rk806_dvs3_null: dvs3-null-pins {
+ pins = "gpio_pwrctrl3";
+ function = "pin_fun0";
+ };
+
+ regulators {
+ vdd_gpu_s0: vdd_gpu_mem_s0: dcdc-reg1 {
+ regulator-name = "vdd_gpu_s0";
+ regulator-boot-on;
+ regulator-enable-ramp-delay = <400>;
+ regulator-min-microvolt = <550000>;
+ regulator-max-microvolt = <950000>;
+ regulator-ramp-delay = <12500>;
+
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ };
+ };
+
+ vdd_cpu_lit_s0: vdd_cpu_lit_mem_s0: dcdc-reg2 {
+ regulator-name = "vdd_cpu_lit_s0";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <550000>;
+ regulator-max-microvolt = <950000>;
+ regulator-ramp-delay = <12500>;
+
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ };
+ };
+
+ vdd_log_s0: dcdc-reg3 {
+ regulator-name = "vdd_log_s0";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <675000>;
+ regulator-max-microvolt = <750000>;
+ regulator-ramp-delay = <12500>;
+
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ regulator-suspend-microvolt = <750000>;
+ };
+ };
+
+ vdd_vdenc_s0: vdd_vdenc_mem_s0: dcdc-reg4 {
+ regulator-name = "vdd_vdenc_s0";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <550000>;
+ regulator-max-microvolt = <950000>;
+ regulator-init-microvolt = <750000>;
+ regulator-ramp-delay = <12500>;
+
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ };
+ };
+
+ vdd_ddr_s0: dcdc-reg5 {
+ regulator-name = "vdd_ddr_s0";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <675000>;
+ regulator-max-microvolt = <900000>;
+ regulator-ramp-delay = <12500>;
+
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ regulator-suspend-microvolt = <850000>;
+ };
+ };
+
+ vdd2_ddr_s3: dcdc-reg6 {
+ regulator-name = "vdd2_ddr_s3";
+ regulator-always-on;
+ regulator-boot-on;
+
+ regulator-state-mem {
+ regulator-on-in-suspend;
+ };
+ };
+
+ vcc_2v0_pldo_s3: dcdc-reg7 {
+ regulator-name = "vdd_2v0_pldo_s3";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <2000000>;
+ regulator-max-microvolt = <2000000>;
+
+ regulator-state-mem {
+ regulator-on-in-suspend;
+ regulator-suspend-microvolt = <2000000>;
+ };
+ };
+
+ vcc_3v3_s3: dcdc-reg8 {
+ regulator-name = "vcc_3v3_s3";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+
+ regulator-state-mem {
+ regulator-on-in-suspend;
+ regulator-suspend-microvolt = <3300000>;
+ };
+ };
+
+ vddq_ddr_s0: dcdc-reg9 {
+ regulator-name = "vddq_ddr_s0";
+ regulator-always-on;
+ regulator-boot-on;
+
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ };
+ };
+
+ vcc_1v8_s3: dcdc-reg10 {
+ regulator-name = "vcc_1v8_s3";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+
+ regulator-state-mem {
+ regulator-on-in-suspend;
+ regulator-suspend-microvolt = <1800000>;
+ };
+ };
+
+ avcc_1v8_s0: pldo-reg1 {
+ regulator-name = "avcc_1v8_s0";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ };
+ };
+
+ vcc_1v8_s0: pldo-reg2 {
+ regulator-name = "vcc_1v8_s0";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ regulator-suspend-microvolt = <1800000>;
+ };
+ };
+
+ avdd_1v2_s0: pldo-reg3 {
+ regulator-name = "avdd_1v2_s0";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <1200000>;
+ regulator-max-microvolt = <1200000>;
+
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ };
+ };
+
+ vcc_3v3_s0: pldo-reg4 {
+ regulator-name = "vcc_3v3_s0";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ };
+ };
+
+ vccio_sd_s0: pldo-reg5 {
+ regulator-name = "vccio_sd_s0";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <3300000>;
+
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ };
+ };
+
+ pldo6_s3: pldo-reg6 {
+ regulator-name = "pldo6_s3";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+
+ regulator-state-mem {
+ regulator-on-in-suspend;
+ regulator-suspend-microvolt = <1800000>;
+ };
+ };
+
+ vdd_0v75_s3: nldo-reg1 {
+ regulator-name = "vdd_0v75_s3";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <750000>;
+ regulator-max-microvolt = <750000>;
+
+ regulator-state-mem {
+ regulator-on-in-suspend;
+ regulator-suspend-microvolt = <750000>;
+ };
+ };
+
+ vdd_ddr_pll_s0: nldo-reg2 {
+ regulator-name = "vdd_ddr_pll_s0";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <850000>;
+ regulator-max-microvolt = <850000>;
+
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ regulator-suspend-microvolt = <850000>;
+ };
+ };
+
+ avdd_0v75_s0: nldo-reg3 {
+ regulator-name = "avdd_0v75_s0";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <837500>;
+ regulator-max-microvolt = <837500>;
+
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ };
+ };
+
+ vdd_0v85_s0: nldo-reg4 {
+ regulator-name = "vdd_0v85_s0";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <850000>;
+ regulator-max-microvolt = <850000>;
+
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ };
+ };
+
+ vdd_0v75_s0: nldo-reg5 {
+ regulator-name = "vdd_0v75_s0";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <750000>;
+ regulator-max-microvolt = <750000>;
+
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ };
+ };
+ };
+ };
+};
+
+&u2phy2 {
+ status = "okay";
+};
+
+&u2phy2_host {
+ phy-supply = <&vcc5v0_host>;
+ status = "okay";
+};
+
+&u2phy3 {
+ status = "okay";
+};
+
+&u2phy3_host {
+ phy-supply = <&vcc5v0_host>;
+ status = "okay";
+};
+
+&uart2 {
+ pinctrl-0 = <&uart2m0_xfer>;
+ status = "okay";
+};
+
+&usb_host0_ehci {
+ status = "okay";
+};
+
+&usb_host0_ohci {
+ status = "okay";
+};
+
+&usb_host1_ehci {
+ status = "okay";
+};
+
+&usb_host1_ohci {
+ status = "okay";
+};
diff --git a/arch/arm/dts/rk3588s-coolpi-4b-u-boot.dtsi b/arch/arm/dts/rk3588s-coolpi-4b-u-boot.dtsi
new file mode 100644
index 0000000..6e4b970
--- /dev/null
+++ b/arch/arm/dts/rk3588s-coolpi-4b-u-boot.dtsi
@@ -0,0 +1,29 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+
+#include "rk3588s-u-boot.dtsi"
+
+&fspim2_pins {
+ bootph-all;
+};
+
+&sdhci {
+ cap-mmc-highspeed;
+ mmc-hs200-1_8v;
+};
+
+&sfc {
+ bootph-pre-ram;
+ u-boot,spl-sfc-no-dma;
+ pinctrl-names = "default";
+ pinctrl-0 = <&fspim2_pins>;
+ status = "okay";
+
+ flash@0 {
+ bootph-pre-ram;
+ compatible = "jedec,spi-nor";
+ reg = <0>;
+ spi-max-frequency = <24000000>;
+ spi-rx-bus-width = <4>;
+ spi-tx-bus-width = <1>;
+ };
+};
diff --git a/arch/arm/dts/rk3588s-coolpi-4b.dts b/arch/arm/dts/rk3588s-coolpi-4b.dts
new file mode 100644
index 0000000..e037bf9
--- /dev/null
+++ b/arch/arm/dts/rk3588s-coolpi-4b.dts
@@ -0,0 +1,812 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (c) 2023 Rockchip Electronics Co., Ltd.
+ *
+ * https://cool-pi.com/topic/130/coolpi-4b-product-spec-introduction
+ *
+ */
+
+/dts-v1/;
+
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/leds/common.h>
+#include <dt-bindings/pinctrl/rockchip.h>
+#include "rk3588s.dtsi"
+
+/ {
+ model = "RK3588S CoolPi 4 Model B";
+ compatible = "coolpi,pi-4b", "rockchip,rk3588s";
+
+ aliases {
+ mmc0 = &sdhci;
+ mmc1 = &sdmmc;
+ mmc2 = &sdio;
+ };
+
+ analog-sound {
+ compatible = "audio-graph-card";
+ dais = <&i2s0_8ch_p0>;
+ label = "rk3588-es8316";
+ routing = "MIC2", "Mic Jack",
+ "Headphones", "HPOL",
+ "Headphones", "HPOR";
+ widgets = "Microphone", "Mic Jack",
+ "Headphone", "Headphones";
+ };
+
+ chosen {
+ stdout-path = "serial2:1500000n8";
+ };
+
+ leds: leds {
+ compatible = "gpio-leds";
+ pinctrl-names = "default";
+ pinctrl-0 = <&gpio_leds>;
+
+ led0: led-green {
+ color = <LED_COLOR_ID_GREEN>;
+ function = LED_FUNCTION_STATUS;
+ gpios = <&gpio0 RK_PD0 GPIO_ACTIVE_HIGH>;
+ linux,default-trigger = "heartbeat";
+ };
+
+ led1: led-red {
+ color = <LED_COLOR_ID_RED>;
+ default-state = "off";
+ function = LED_FUNCTION_WLAN;
+ gpios = <&gpio0 RK_PC4 GPIO_ACTIVE_HIGH>;
+ linux,default-trigger = "phy0tx";
+ };
+ };
+
+ sdio_pwrseq: sdio-pwrseq {
+ compatible = "mmc-pwrseq-simple";
+ clocks = <&hym8563>;
+ clock-names = "ext_clock";
+ pinctrl-names = "default";
+ pinctrl-0 = <&wifi_enable_h>;
+ /*
+ * On the module itself this is one of these (depending
+ * on the actual card populated):
+ * - SDIO_RESET_L_WL_REG_ON
+ * - PDN (power down when low)
+ */
+ post-power-on-delay-ms = <200>;
+ reset-gpios = <&gpio0 RK_PC7 GPIO_ACTIVE_LOW>;
+ };
+
+ vcc12v_dcin: vcc12v-dcin-regulator {
+ compatible = "regulator-fixed";
+ regulator-name = "vcc12v_dcin";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <12000000>;
+ regulator-max-microvolt = <12000000>;
+ };
+
+ vcc5v0_sys: vcc5v0-sys-regulator {
+ compatible = "regulator-fixed";
+ regulator-name = "vcc5v0_sys";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <5000000>;
+ regulator-max-microvolt = <5000000>;
+ vin-supply = <&vcc12v_dcin>;
+ };
+
+ vcc5v0_usbdcin: vcc5v0-usbdcin-regulator {
+ compatible = "regulator-fixed";
+ regulator-name = "vcc5v0_usbdcin";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <5000000>;
+ regulator-max-microvolt = <5000000>;
+ vin-supply = <&vcc12v_dcin>;
+ };
+
+ vcc5v0_usb: vcc5v0-usb-regulator {
+ compatible = "regulator-fixed";
+ regulator-name = "vcc5v0_usb";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <5000000>;
+ regulator-max-microvolt = <5000000>;
+ vin-supply = <&vcc5v0_usbdcin>;
+ };
+
+ avdd0v85_pcie20: avdd0v85-pcie20-regulator {
+ compatible = "regulator-fixed";
+ regulator-name = "avdd0v85_pcie20";
+ regulator-boot-on;
+ regulator-always-on;
+ regulator-min-microvolt = <850000>;
+ regulator-max-microvolt = <850000>;
+ vin-supply = <&vdd_0v85_s0>;
+ };
+
+ avdd1v8_pcie20: avdd1v8-pcie20-regulator {
+ compatible = "regulator-fixed";
+ regulator-name = "avdd1v8_pcie20";
+ regulator-boot-on;
+ regulator-always-on;
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ vin-supply = <&avcc_1v8_s0>;
+ };
+
+ vcc3v3_mipi: vcc3v3-mipi-regulator {
+ compatible = "regulator-fixed";
+ enable-active-high;
+ gpio = <&gpio3 RK_PC2 GPIO_ACTIVE_HIGH>;
+ regulator-name = "vcc3v3_mipi";
+ regulator-boot-on;
+ regulator-always-on;
+ vin-supply = <&vcc_3v3_s3>;
+ };
+
+ vcc5v0_host: vcc5v0-host-regulator {
+ compatible = "regulator-fixed";
+ enable-active-high;
+ gpio = <&gpio3 RK_PC0 GPIO_ACTIVE_HIGH>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&vcc5v0_host_en>;
+ regulator-name = "vcc5v0_host";
+ regulator-boot-on;
+ regulator-always-on;
+ regulator-min-microvolt = <5000000>;
+ regulator-max-microvolt = <5000000>;
+ vin-supply = <&vcc5v0_sys>;
+ };
+
+ vcc5v0_otg: vcc5v0-otg-regulator {
+ compatible = "regulator-fixed";
+ enable-active-high;
+ gpio = <&gpio3 RK_PC1 GPIO_ACTIVE_HIGH>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&vcc5v0_u3host_en>;
+ regulator-name = "vcc5v0_otg";
+ regulator-boot-on;
+ regulator-always-on;
+ regulator-min-microvolt = <5000000>;
+ regulator-max-microvolt = <5000000>;
+ vin-supply = <&vcc5v0_sys>;
+ };
+
+ vcc_1v1_nldo_s3: vcc-1v1-nldo-s3-regulator {
+ compatible = "regulator-fixed";
+ regulator-name = "vcc_1v1_nldo_s3";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <1100000>;
+ regulator-max-microvolt = <1100000>;
+ vin-supply = <&vcc5v0_sys>;
+ };
+};
+
+&combphy0_ps {
+ status = "okay";
+};
+
+&combphy2_psu {
+ status = "okay";
+};
+
+&cpu_l0 {
+ cpu-supply = <&vdd_cpu_lit_s0>;
+};
+
+&cpu_b0 {
+ cpu-supply = <&vdd_cpu_big0_s0>;
+};
+
+&cpu_b2 {
+ cpu-supply = <&vdd_cpu_big1_s0>;
+};
+
+&i2c0 {
+ pinctrl-0 = <&i2c0m2_xfer>;
+ status = "okay";
+
+ vdd_cpu_big0_s0: regulator@42 {
+ compatible = "rockchip,rk8602";
+ reg = <0x42>;
+ fcs,suspend-voltage-selector = <1>;
+ regulator-name = "vdd_cpu_big0_s0";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <550000>;
+ regulator-max-microvolt = <1050000>;
+ regulator-ramp-delay = <2300>;
+ vin-supply = <&vcc5v0_sys>;
+
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ };
+ };
+
+ vdd_cpu_big1_s0: regulator@43 {
+ compatible = "rockchip,rk8603", "rockchip,rk8602";
+ reg = <0x43>;
+ fcs,suspend-voltage-selector = <1>;
+ regulator-name = "vdd_cpu_big1_s0";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <550000>;
+ regulator-max-microvolt = <1050000>;
+ regulator-ramp-delay = <2300>;
+ vin-supply = <&vcc5v0_sys>;
+
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ };
+ };
+};
+
+&i2c2 {
+ status = "okay";
+
+ vdd_npu_s0: regulator@42 {
+ compatible = "rockchip,rk8602";
+ reg = <0x42>;
+ fcs,suspend-voltage-selector = <1>;
+ regulator-name = "vdd_npu_s0";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <550000>;
+ regulator-max-microvolt = <950000>;
+ regulator-ramp-delay = <2300>;
+ vin-supply = <&vcc5v0_sys>;
+
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ };
+ };
+};
+
+&i2c6 {
+ pinctrl-0 = <&i2c6m3_xfer>;
+ status = "okay";
+
+ hym8563: rtc@51 {
+ compatible = "haoyu,hym8563";
+ reg = <0x51>;
+ interrupt-parent = <&gpio0>;
+ interrupts = <RK_PB0 IRQ_TYPE_LEVEL_LOW>;
+ #clock-cells = <0>;
+ clock-output-names = "hym8563";
+ pinctrl-names = "default";
+ pinctrl-0 = <&hym8563_int>;
+ };
+};
+
+&i2c7 {
+ pinctrl-0 = <&i2c7m0_xfer>;
+ status = "okay";
+
+ es8316: audio-codec@11 {
+ compatible = "everest,es8316";
+ reg = <0x11>;
+ assigned-clocks = <&cru I2S0_8CH_MCLKOUT>;
+ assigned-clock-rates = <12288000>;
+ clocks = <&cru I2S0_8CH_MCLKOUT>;
+ clock-names = "mclk";
+ #sound-dai-cells = <0>;
+
+ port {
+ es8316_p0_0: endpoint {
+ remote-endpoint = <&i2s0_8ch_p0_0>;
+ };
+ };
+ };
+};
+
+&i2s0_8ch {
+ pinctrl-0 = <&i2s0_lrck
+ &i2s0_mclk
+ &i2s0_sclk
+ &i2s0_sdi0
+ &i2s0_sdo0>;
+ status = "okay";
+
+ i2s0_8ch_p0: port {
+ i2s0_8ch_p0_0: endpoint {
+ dai-format = "i2s";
+ mclk-fs = <256>;
+ remote-endpoint = <&es8316_p0_0>;
+ };
+ };
+};
+
+&pcie2x1l2 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&rtl8111_isolate>;
+ reset-gpios = <&gpio3 RK_PD1 GPIO_ACTIVE_HIGH>;
+ status = "okay";
+};
+
+&pinctrl {
+ hym8563 {
+ hym8563_int: hym8563-int {
+ rockchip,pins = <0 RK_PB0 RK_FUNC_GPIO &pcfg_pull_up>;
+ };
+ };
+
+ led {
+ gpio_leds: gpio-leds {
+ rockchip,pins = <0 RK_PC4 RK_FUNC_GPIO &pcfg_pull_down>,
+ <0 RK_PD0 RK_FUNC_GPIO &pcfg_pull_down>;
+ };
+ };
+
+ rtl8111 {
+ rtl8111_isolate: rtl8111-isolate {
+ rockchip,pins = <1 RK_PA4 RK_FUNC_GPIO &pcfg_pull_up>;
+ };
+ };
+
+ sdio-pwrseq {
+ wifi_enable_h: wifi-enable-h {
+ rockchip,pins = <0 RK_PC7 RK_FUNC_GPIO &pcfg_pull_up>;
+ };
+ };
+
+ usb {
+ vcc5v0_host_en: vcc5v0-host-en {
+ rockchip,pins = <3 RK_PC0 RK_FUNC_GPIO &pcfg_pull_none>,
+ <4 RK_PB5 RK_FUNC_GPIO &pcfg_pull_up>;
+ };
+
+ vcc5v0_u3host_en: vcc5v0-u3host-en {
+ rockchip,pins = <3 RK_PC1 RK_FUNC_GPIO &pcfg_pull_none>;
+ };
+ };
+
+ wireless-bluetooth {
+ bt_reset_gpio: bt-reset-pin {
+ rockchip,pins = <0 RK_PD3 RK_FUNC_GPIO &pcfg_pull_none>;
+ };
+
+ bt_wake_gpio: bt-wake-pin {
+ rockchip,pins = <0 RK_PC6 RK_FUNC_GPIO &pcfg_pull_none>;
+ };
+
+ bt_wake_host_irq: bt-wake-host-irq {
+ rockchip,pins = <0 RK_PC5 RK_FUNC_GPIO &pcfg_pull_down>;
+ };
+ };
+
+ wireless-wlan {
+ wifi_host_wake_irq: wifi-host-wake-irq {
+ rockchip,pins = <0 RK_PA0 RK_FUNC_GPIO &pcfg_pull_down>;
+ };
+
+ wifi_poweren_pin: wifi-poweren-pin {
+ rockchip,pins = <1 RK_PD3 RK_FUNC_GPIO &pcfg_pull_up>;
+ };
+ };
+};
+
+&pwm2 {
+ pinctrl-0 = <&pwm2m1_pins>;
+ status = "okay";
+};
+
+&pwm13 {
+ pinctrl-names = "active";
+ pinctrl-0 = <&pwm13m2_pins>;
+ status = "okay";
+};
+
+&saradc {
+ vref-supply = <&vcc_1v8_s0>;
+ status = "okay";
+};
+
+&sdhci {
+ bus-width = <8>;
+ max-frequency = <200000000>;
+ mmc-hs400-1_8v;
+ mmc-hs400-enhanced-strobe;
+ no-sdio;
+ no-sd;
+ non-removable;
+ status = "okay";
+};
+
+&sdio {
+ bus-width = <4>;
+ cap-sd-highspeed;
+ cap-sdio-irq;
+ disable-wp;
+ keep-power-in-suspend;
+ max-frequency = <150000000>;
+ mmc-pwrseq = <&sdio_pwrseq>;
+ no-sd;
+ no-mmc;
+ non-removable;
+ pinctrl-names = "default";
+ pinctrl-0 = <&sdiom1_pins>,<&wifi_poweren_pin>;
+ status = "okay";
+};
+
+&sdmmc {
+ bus-width = <4>;
+ cap-mmc-highspeed;
+ cap-sd-highspeed;
+ disable-wp;
+ max-frequency = <150000000>;
+ no-sdio;
+ no-mmc;
+ sd-uhs-sdr104;
+ vmmc-supply = <&vcc_3v3_s3>;
+ vqmmc-supply = <&vccio_sd_s0>;
+ status = "okay";
+};
+
+&spi2 {
+ assigned-clocks = <&cru CLK_SPI2>;
+ assigned-clock-rates = <200000000>;
+ num-cs = <1>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&spi2m2_cs0 &spi2m2_pins>;
+ status = "okay";
+
+ pmic@0 {
+ compatible = "rockchip,rk806";
+ reg = <0x0>;
+ interrupt-parent = <&gpio0>;
+ interrupts = <7 IRQ_TYPE_LEVEL_LOW>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pmic_pins>, <&rk806_dvs1_null>,
+ <&rk806_dvs2_null>, <&rk806_dvs3_null>;
+ spi-max-frequency = <1000000>;
+ vcc1-supply = <&vcc5v0_sys>;
+ vcc2-supply = <&vcc5v0_sys>;
+ vcc3-supply = <&vcc5v0_sys>;
+ vcc4-supply = <&vcc5v0_sys>;
+ vcc5-supply = <&vcc5v0_sys>;
+ vcc6-supply = <&vcc5v0_sys>;
+ vcc7-supply = <&vcc5v0_sys>;
+ vcc8-supply = <&vcc5v0_sys>;
+ vcc9-supply = <&vcc5v0_sys>;
+ vcc10-supply = <&vcc5v0_sys>;
+ vcc11-supply = <&vcc_2v0_pldo_s3>;
+ vcc12-supply = <&vcc5v0_sys>;
+ vcc13-supply = <&vcc_1v1_nldo_s3>;
+ vcc14-supply = <&vcc_1v1_nldo_s3>;
+ vcca-supply = <&vcc5v0_sys>;
+
+ rk806_dvs1_null: dvs1-null-pins {
+ pins = "gpio_pwrctrl2";
+ function = "pin_fun0";
+ };
+
+ rk806_dvs2_null: dvs2-null-pins {
+ pins = "gpio_pwrctrl2";
+ function = "pin_fun0";
+ };
+
+ rk806_dvs3_null: dvs3-null-pins {
+ pins = "gpio_pwrctrl3";
+ function = "pin_fun0";
+ };
+
+ regulators {
+ vdd_gpu_s0: vdd_gpu_mem_s0: dcdc-reg1 {
+ regulator-name = "vdd_gpu_s0";
+ regulator-boot-on;
+ regulator-min-microvolt = <550000>;
+ regulator-max-microvolt = <950000>;
+ regulator-ramp-delay = <12500>;
+ regulator-enable-ramp-delay = <400>;
+
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ };
+ };
+
+ vdd_cpu_lit_s0: vdd_cpu_lit_mem_s0: dcdc-reg2 {
+ regulator-name = "vdd_cpu_lit_s0";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <550000>;
+ regulator-max-microvolt = <950000>;
+ regulator-ramp-delay = <12500>;
+
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ };
+ };
+
+ vdd_log_s0: dcdc-reg3 {
+ regulator-name = "vdd_log_s0";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <675000>;
+ regulator-max-microvolt = <750000>;
+ regulator-ramp-delay = <12500>;
+
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ regulator-suspend-microvolt = <750000>;
+ };
+ };
+
+ vdd_vdenc_s0: vdd_vdenc_mem_s0: dcdc-reg4 {
+ regulator-name = "vdd_vdenc_s0";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <550000>;
+ regulator-max-microvolt = <950000>;
+ regulator-ramp-delay = <12500>;
+
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ };
+ };
+
+ vdd_ddr_s0: dcdc-reg5 {
+ regulator-name = "vdd_ddr_s0";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <675000>;
+ regulator-max-microvolt = <900000>;
+ regulator-ramp-delay = <12500>;
+
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ regulator-suspend-microvolt = <850000>;
+ };
+ };
+
+ vdd2_ddr_s3: dcdc-reg6 {
+ regulator-name = "vdd2_ddr_s3";
+ regulator-always-on;
+ regulator-boot-on;
+
+ regulator-state-mem {
+ regulator-on-in-suspend;
+ };
+ };
+
+ vcc_2v0_pldo_s3: dcdc-reg7 {
+ regulator-name = "vdd_2v0_pldo_s3";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <2000000>;
+ regulator-max-microvolt = <2000000>;
+ regulator-ramp-delay = <12500>;
+
+ regulator-state-mem {
+ regulator-on-in-suspend;
+ regulator-suspend-microvolt = <2000000>;
+ };
+ };
+
+ vcc_3v3_s3: dcdc-reg8 {
+ regulator-name = "vcc_3v3_s3";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+
+ regulator-state-mem {
+ regulator-on-in-suspend;
+ regulator-suspend-microvolt = <3300000>;
+ };
+ };
+
+ vddq_ddr_s0: dcdc-reg9 {
+ regulator-name = "vddq_ddr_s0";
+ regulator-always-on;
+ regulator-boot-on;
+
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ };
+ };
+
+ vcc_1v8_s3: dcdc-reg10 {
+ regulator-name = "vcc_1v8_s3";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+
+ regulator-state-mem {
+ regulator-on-in-suspend;
+ regulator-suspend-microvolt = <1800000>;
+ };
+ };
+
+ avcc_1v8_s0: pldo-reg1 {
+ regulator-name = "avcc_1v8_s0";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ };
+ };
+
+ vcc_1v8_s0: pldo-reg2 {
+ regulator-name = "vcc_1v8_s0";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ regulator-suspend-microvolt = <1800000>;
+ };
+ };
+
+ avdd_1v2_s0: pldo-reg3 {
+ regulator-name = "avdd_1v2_s0";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <1200000>;
+ regulator-max-microvolt = <1200000>;
+
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ };
+ };
+
+ vcc_3v3_s0: pldo-reg4 {
+ regulator-name = "vcc_3v3_s0";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-ramp-delay = <12500>;
+
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ };
+ };
+
+ vccio_sd_s0: pldo-reg5 {
+ regulator-name = "vccio_sd_s0";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-ramp-delay = <12500>;
+
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ };
+ };
+
+ pldo6_s3: pldo-reg6 {
+ regulator-name = "pldo6_s3";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+
+ regulator-state-mem {
+ regulator-on-in-suspend;
+ regulator-suspend-microvolt = <1800000>;
+ };
+ };
+
+ vdd_0v75_s3: nldo-reg1 {
+ regulator-name = "vdd_0v75_s3";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <750000>;
+ regulator-max-microvolt = <750000>;
+
+ regulator-state-mem {
+ regulator-on-in-suspend;
+ regulator-suspend-microvolt = <750000>;
+ };
+ };
+
+ vdd_ddr_pll_s0: nldo-reg2 {
+ regulator-name = "vdd_ddr_pll_s0";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <850000>;
+ regulator-max-microvolt = <850000>;
+
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ regulator-suspend-microvolt = <850000>;
+ };
+ };
+
+ avdd_0v75_s0: nldo-reg3 {
+ regulator-name = "avdd_0v75_s0";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <750000>;
+ regulator-max-microvolt = <750000>;
+
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ };
+ };
+
+ vdd_0v85_s0: nldo-reg4 {
+ regulator-name = "vdd_0v85_s0";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <850000>;
+ regulator-max-microvolt = <850000>;
+
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ };
+ };
+
+ vdd_0v75_s0: nldo-reg5 {
+ regulator-name = "vdd_0v75_s0";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <750000>;
+ regulator-max-microvolt = <750000>;
+
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ };
+ };
+ };
+ };
+};
+
+&tsadc {
+ status = "okay";
+};
+
+&u2phy2 {
+ status = "okay";
+};
+
+&u2phy3 {
+ status = "okay";
+};
+
+&u2phy2_host {
+ phy-supply = <&vcc5v0_host>;
+ status = "okay";
+};
+
+&u2phy3_host {
+ status = "okay";
+};
+
+&uart2 {
+ pinctrl-0 = <&uart2m0_xfer>;
+ status = "okay";
+};
+
+/* bt */
+&uart9 {
+ status = "okay";
+ pinctrl-names = "default";
+ pinctrl-0 = <&uart9m2_xfer &uart9m2_ctsn>;
+};
+
+&usb_host0_ehci {
+ status = "okay";
+};
+
+&usb_host0_ohci {
+ status = "okay";
+};
+
+&usb_host1_ehci {
+ status = "okay";
+};
+
+&usb_host1_ohci {
+ status = "okay";
+};
diff --git a/arch/arm/dts/rk3588s-u-boot.dtsi b/arch/arm/dts/rk3588s-u-boot.dtsi
index bf3b1ea8..ac67c77 100644
--- a/arch/arm/dts/rk3588s-u-boot.dtsi
+++ b/arch/arm/dts/rk3588s-u-boot.dtsi
@@ -188,11 +188,13 @@
&sdmmc {
bootph-pre-ram;
+ bootph-some-ram;
u-boot,spl-fifo-mode;
};
&sdhci {
bootph-pre-ram;
+ bootph-some-ram;
u-boot,spl-fifo-mode;
};
diff --git a/arch/arm/dts/sama7g5.dtsi b/arch/arm/dts/sama7g5.dtsi
index 746a5ba..a17c58c 100644
--- a/arch/arm/dts/sama7g5.dtsi
+++ b/arch/arm/dts/sama7g5.dtsi
@@ -871,6 +871,30 @@
};
};
+ flx10: flexcom@e2820000 {
+ compatible = "atmel,sama5d2-flexcom";
+ reg = <0xe2820000 0x200>;
+ clocks = <&pmc PMC_TYPE_PERIPHERAL 48>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0x0 0xe2820000 0x800>;
+ status = "disabled";
+
+ i2c10: i2c@600 {
+ compatible = "microchip,sama7g5-i2c", "microchip,sam9x60-i2c";
+ reg = <0x600 0x200>;
+ interrupts = <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ clocks = <&pmc PMC_TYPE_PERIPHERAL 48>;
+ atmel,fifo-size = <32>;
+ dmas = <&dma0 AT91_XDMAC_DT_PERID(26)>,
+ <&dma0 AT91_XDMAC_DT_PERID(25)>;
+ dma-names = "tx", "rx";
+ status = "disabled";
+ };
+ };
+
flx11: flexcom@e2824000 {
compatible = "atmel,sama5d2-flexcom";
reg = <0xe2824000 0x200>;
diff --git a/arch/arm/dts/sdm845-db845c-u-boot.dtsi b/arch/arm/dts/sdm845-db845c-u-boot.dtsi
new file mode 100644
index 0000000..906f9fa
--- /dev/null
+++ b/arch/arm/dts/sdm845-db845c-u-boot.dtsi
@@ -0,0 +1,9 @@
+// SPDX-License-Identifier: GPL-2.0
+
+/* Needed for Linux to boot from USB, otherwise if PCIe driver is not in initramfs
+ * the VBUS supply will never get turned on.
+ * https://lore.kernel.org/linux-arm-msm/20240320122515.3243711-1-caleb.connolly@linaro.org/
+ */
+&pcie0_3p3v_dual {
+ regulator-always-on;
+};
diff --git a/arch/arm/dts/socfpga_agilex5-u-boot.dtsi b/arch/arm/dts/socfpga_agilex5-u-boot.dtsi
new file mode 100644
index 0000000..a8167e5
--- /dev/null
+++ b/arch/arm/dts/socfpga_agilex5-u-boot.dtsi
@@ -0,0 +1,71 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * U-Boot additions
+ *
+ * Copyright (C) 2024 Intel Corporation <www.intel.com>
+ */
+
+#include "socfpga_soc64_fit-u-boot.dtsi"
+
+/{
+ memory {
+ #address-cells = <2>;
+ #size-cells = <2>;
+ bootph-all;
+ };
+};
+
+&clkmgr {
+ bootph-all;
+};
+
+&i2c0 {
+ reset-names = "i2c";
+};
+
+&i2c1 {
+ reset-names = "i2c";
+};
+
+&i2c2 {
+ reset-names = "i2c";
+};
+
+&i2c3 {
+ reset-names = "i2c";
+};
+
+&mmc {
+ resets = <&rst SDMMC_RESET>, <&rst SDMMC_OCP_RESET>;
+};
+
+&porta {
+ bank-name = "porta";
+};
+
+&portb {
+ bank-name = "portb";
+};
+
+&qspi {
+ bootph-all;
+};
+
+&rst {
+ compatible = "altr,rst-mgr";
+ altr,modrst-offset = <0x24>;
+ bootph-all;
+};
+
+&sysmgr {
+ compatible = "altr,sys-mgr", "syscon";
+ bootph-all;
+};
+
+&uart0 {
+ bootph-all;
+};
+
+&watchdog0 {
+ bootph-all;
+};
diff --git a/arch/arm/dts/socfpga_agilex5.dtsi b/arch/arm/dts/socfpga_agilex5.dtsi
new file mode 100644
index 0000000..03b5504
--- /dev/null
+++ b/arch/arm/dts/socfpga_agilex5.dtsi
@@ -0,0 +1,575 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (C) 2024 Intel Corporation <www.intel.com>
+ */
+
+/dts-v1/;
+#include <dt-bindings/reset/altr,rst-mgr-agx5.h>
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/clock/agilex5-clock.h>
+
+/ {
+ compatible = "intel,socfpga-agilex";
+ #address-cells = <2>;
+ #size-cells = <2>;
+
+ reserved-memory {
+ #address-cells = <2>;
+ #size-cells = <2>;
+ ranges;
+
+ service_reserved: svcbuffer@0 {
+ compatible = "shared-dma-pool";
+ reg = <0x0 0x0 0x0 0x1000000>;
+ alignment = <0x1000>;
+ no-map;
+ };
+ };
+
+ cpus {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ cpu0: cpu@0 {
+ compatible = "arm,cortex-a55";
+ device_type = "cpu";
+ enable-method = "psci";
+ reg = <0x0>;
+ };
+
+ cpu1: cpu@1 {
+ compatible = "arm,cortex-a55";
+ device_type = "cpu";
+ enable-method = "psci";
+ reg = <0x1>;
+ };
+
+ cpu2: cpu@2 {
+ compatible = "arm,cortex-a76";
+ device_type = "cpu";
+ enable-method = "psci";
+ reg = <0x2>;
+ };
+
+ cpu3: cpu@3 {
+ compatible = "arm,cortex-a76";
+ device_type = "cpu";
+ enable-method = "psci";
+ reg = <0x3>;
+ };
+ };
+
+ pmu {
+ compatible = "arm,armv8-pmuv3";
+ interrupts = <0 170 4>,
+ <0 171 4>,
+ <0 172 4>,
+ <0 173 4>;
+ interrupt-affinity = <&cpu0>,
+ <&cpu1>,
+ <&cpu2>,
+ <&cpu3>;
+ interrupt-parent = <&intc>;
+ };
+
+ psci {
+ compatible = "arm,psci-0.2";
+ method = "smc";
+ };
+
+ intc: intc@fffc1000 {
+ compatible = "arm,gic-400", "arm,cortex-a15-gic";
+ #interrupt-cells = <3>;
+ interrupt-controller;
+ reg = <0x0 0x1d000000 0x0 0x10000>;
+ };
+
+ soc {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ compatible = "simple-bus";
+ device_type = "soc";
+ interrupt-parent = <&intc>;
+ ranges = <0 0 0 0xffffffff>;
+
+ base_fpga_region {
+ #address-cells = <0x1>;
+ #size-cells = <0x1>;
+ compatible = "fpga-region";
+ fpga-mgr = <&fpga_mgr>;
+ };
+
+ clkmgr: clock-controller@10d10000 {
+ compatible = "intel,agilex5-clkmgr";
+ reg = <0x10d10000 0x1000>;
+ #clock-cells = <1>;
+ };
+
+ clocks {
+ cb_intosc_hs_div2_clk: cb-intosc-hs-div2-clk {
+ #clock-cells = <0>;
+ compatible = "fixed-clock";
+ };
+
+ cb_intosc_ls_clk: cb-intosc-ls-clk {
+ #clock-cells = <0>;
+ compatible = "fixed-clock";
+ };
+
+ f2s_free_clk: f2s-free-clk {
+ #clock-cells = <0>;
+ compatible = "fixed-clock";
+ };
+
+ osc1: osc1 {
+ #clock-cells = <0>;
+ compatible = "fixed-clock";
+ };
+
+ qspi_clk: qspi-clk {
+ #clock-cells = <0>;
+ compatible = "fixed-clock";
+ clock-frequency = <200000000>;
+ };
+ };
+ gmac0: ethernet@10810000 {
+ compatible = "intel,socfpga-dwxgmac", "snps,dwxgmac-2.10", "snps,dwxgmac";
+ reg = <0x10810000 0x3500>;
+ interrupts = <0 190 4>;
+ interrupt-names = "macirq";
+ mac-address = [00 00 00 00 00 00];
+ resets = <&rst EMAC0_RESET>, <&rst EMAC0_OCP_RESET>;
+ reset-names = "stmmaceth", "stmmaceth-ocp";
+ tx-fifo-depth = <32768>;
+ rx-fifo-depth = <16384>;
+ iommus = <&smmu 1>;
+ altr,sysmgr-syscon = <&sysmgr 0x44 0>;
+ clocks = <&clkmgr AGILEX5_EMAC0_CLK>;
+ clock-names = "stmmaceth";
+ status = "disabled";
+ };
+
+ gmac1: ethernet@10820000 {
+ compatible = "intel,socfpga-dwxgmac", "snps,dwxgmac-2.10", "snps,dwxgmac";
+ reg = <0x10820000 0x3500>;
+ interrupts = <0 207 4>;
+ interrupt-names = "macirq";
+ mac-address = [00 00 00 00 00 00];
+ resets = <&rst EMAC1_RESET>, <&rst EMAC1_OCP_RESET>;
+ reset-names = "stmmaceth", "stmmaceth-ocp";
+ tx-fifo-depth = <32768>;
+ rx-fifo-depth = <16384>;
+ iommus = <&smmu 2>;
+ altr,sysmgr-syscon = <&sysmgr 0x48 0>;
+ clocks = <&clkmgr AGILEX5_EMAC1_CLK>;
+ clock-names = "stmmaceth";
+ status = "disabled";
+ };
+
+ gmac2: ethernet@10830000 {
+ compatible = "intel,socfpga-dwxgmac", "snps,dwxgmac-2.10", "snps,dwxgmac";
+ reg = <0x10830000 0x3500>;
+ interrupts = <0 224 4>;
+ interrupt-names = "macirq";
+ mac-address = [00 00 00 00 00 00];
+ resets = <&rst EMAC2_RESET>, <&rst EMAC2_OCP_RESET>;
+ reset-names = "stmmaceth", "stmmaceth-ocp";
+ tx-fifo-depth = <32768>;
+ rx-fifo-depth = <16384>;
+ iommus = <&smmu 3>;
+ altr,sysmgr-syscon = <&sysmgr 0x4c 0>;
+ clocks = <&clkmgr AGILEX5_EMAC2_CLK>;
+ clock-names = "stmmaceth";
+ status = "disabled";
+ };
+
+ gpio0: gpio@10c03200 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ compatible = "snps,dw-apb-gpio";
+ reg = <0x10c03200 0x80>;
+ resets = <&rst GPIO0_RESET>;
+ status = "disabled";
+
+ porta: gpio-controller@0 {
+ compatible = "snps,dw-apb-gpio-port";
+ gpio-controller;
+ #gpio-cells = <2>;
+ snps,nr-gpios = <24>;
+ reg = <0>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ interrupts = <0 110 4>;
+ };
+ };
+
+ gpio1: gpio@10c03300 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ compatible = "snps,dw-apb-gpio";
+ reg = <0x10c03300 0x80>;
+ resets = <&rst GPIO1_RESET>;
+ status = "disabled";
+
+ portb: gpio-controller@0 {
+ compatible = "snps,dw-apb-gpio-port";
+ gpio-controller;
+ #gpio-cells = <2>;
+ snps,nr-gpios = <24>;
+ reg = <0>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ interrupts = <0 111 4>;
+ };
+ };
+
+ i2c0: i2c@10c02800 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ compatible = "snps,designware-i2c";
+ reg = <0x10c02800 0x100>;
+ interrupts = <0 103 4>;
+ resets = <&rst I2C0_RESET>;
+ clocks = <&clkmgr AGILEX5_L4_SP_CLK>;
+ status = "disabled";
+ };
+
+ i2c1: i2c@10c02900 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ compatible = "snps,designware-i2c";
+ reg = <0x10c02900 0x100>;
+ interrupts = <0 104 4>;
+ resets = <&rst I2C1_RESET>;
+ clocks = <&clkmgr AGILEX5_L4_SP_CLK>;
+ status = "disabled";
+ };
+
+ i2c2: i2c@10c02a00 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ compatible = "snps,designware-i2c";
+ reg = <0x10c02a00 0x100>;
+ interrupts = <0 105 4>;
+ resets = <&rst I2C2_RESET>;
+ clocks = <&clkmgr AGILEX5_L4_SP_CLK>;
+ status = "disabled";
+ };
+
+ i2c3: i2c@10c02b00 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ compatible = "snps,designware-i2c";
+ reg = <0x10c02b00 0x100>;
+ interrupts = <0 106 4>;
+ resets = <&rst I2C3_RESET>;
+ clocks = <&clkmgr AGILEX5_L4_SP_CLK>;
+ status = "disabled";
+ };
+
+ i2c4: i2c@10c02c00 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ compatible = "snps,designware-i2c";
+ reg = <0x10c02c00 0x100>;
+ interrupts = <0 107 4>;
+ resets = <&rst I2C4_RESET>;
+ clocks = <&clkmgr AGILEX5_L4_SP_CLK>;
+ status = "disabled";
+ };
+
+ i3c0: i3c@10da0000 {
+ compatible = "snps,dw-i3c-master-1.00a";
+ reg = <0x10da0000 0x1000>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ interrupts = <0 164 4>;
+ resets = <&rst I3C0_RESET>;
+ max_devices = <11>;
+ clocks = <&clkmgr AGILEX5_L4_MP_CLK>;
+ status = "disabled";
+ };
+
+ i3c1: i3c@10da1000 {
+ compatible = "snps,dw-i3c-master-1.00a";
+ reg = <0x10da1000 0x1000>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ interrupts = <0 165 4>;
+ resets = <&rst I3C1_RESET>;
+ clocks = <&clkmgr AGILEX5_L4_MP_CLK>;
+ max_devices = <11>;
+ status = "disabled";
+ };
+
+ combophy0: combophy@0 {
+ #phy-cells = <0>;
+ phy-type = <1>;
+ compatible = "cdns,combophy";
+ reg = <0x10808000 0x1000>;
+ resets = <&rst COMBOPHY_RESET>;
+ reset-names = "reset";
+ status = "disabled";
+ };
+
+ mmc: mmc0@10808000 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ compatible = "cdns,sd4hc";
+ reg = <0x10808000 0x1000>;
+ interrupts = <0 96 4>;
+ phys = <&combophy0>;
+ phy-names = "combo-phy";
+ clocks = <&clkmgr AGILEX5_L4_MP_CLK>,
+ <&clkmgr AGILEX5_SDMMC_CLK>;
+ clock-names = "biu", "ciu";
+ fifo-depth = <0x800>;
+ resets = <&rst SDMMC_RESET>;
+ reset-names = "reset";
+ iommus = <&smmu 5>;
+ status = "disabled";
+ };
+
+ ocram: sram@00000000 {
+ compatible = "mmio-sram";
+ reg = <0x00000000 0x200000>;
+ };
+
+ rst: rstmgr@10d11000 {
+ #reset-cells = <1>;
+ compatible = "altr,stratix10-rst-mgr";
+ reg = <0x10d11000 0x1000>;
+ };
+
+ smmu: iommu@16000000 {
+ compatible = "arm,mmu-500", "arm,smmu-v2";
+ reg = <0x16000000 0x40000>;
+ #global-interrupts = <2>;
+ #iommu-cells = <1>;
+ interrupt-parent = <&intc>;
+ interrupts = <0 128 4>, /* Global Secure Fault */
+ <0 129 4>, /* Global Non-secure Fault */
+ /* Non-secure Context Interrupts (32) */
+ <0 138 4>, <0 139 4>, <0 140 4>, <0 141 4>,
+ <0 142 4>, <0 143 4>, <0 144 4>, <0 145 4>,
+ <0 146 4>, <0 147 4>, <0 148 4>, <0 149 4>,
+ <0 150 4>, <0 151 4>, <0 152 4>, <0 153 4>,
+ <0 154 4>, <0 155 4>, <0 156 4>, <0 157 4>,
+ <0 158 4>, <0 159 4>, <0 160 4>, <0 161 4>,
+ <0 162 4>, <0 163 4>, <0 164 4>, <0 165 4>,
+ <0 166 4>, <0 167 4>, <0 168 4>, <0 169 4>;
+ stream-match-mask = <0x7ff0>;
+ status = "disabled";
+ };
+
+ spi0: spi@10da4000 {
+ compatible = "intel,agilex-spi",
+ "snps,dw-apb-ssi-4.00a", "snps,dw-apb-ssi";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0x10da4000 0x1000>;
+ interrupts = <0 99 4>;
+ resets = <&rst SPIM0_RESET>;
+ reg-io-width = <4>;
+ num-cs = <4>;
+ clocks = <&clkmgr AGILEX5_L4_MAIN_CLK>;
+ status = "disabled";
+ };
+
+ spi1: spi@10da5000 {
+ compatible = "intel,agilex-spi",
+ "snps,dw-apb-ssi-4.00a", "snps,dw-apb-ssi";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0x10da5000 0x1000>;
+ interrupts = <0 100 4>;
+ resets = <&rst SPIM1_RESET>;
+ reg-io-width = <4>;
+ num-cs = <4>;
+ clocks = <&clkmgr AGILEX5_L4_MAIN_CLK>;
+ status = "disabled";
+ };
+
+ sysmgr: sysmgr@10d12000 {
+ compatible = "altr,sys-mgr-s10","altr,sys-mgr";
+ reg = <0x10d12000 0x500>;
+ };
+
+ /* Local timer */
+ timer {
+ compatible = "arm,armv8-timer";
+ interrupts = <1 13 0xf08>,
+ <1 14 0xf08>,
+ <1 11 0xf08>,
+ <1 10 0xf08>;
+ };
+
+ timer0: timer0@10c03000 {
+ compatible = "snps,dw-apb-timer";
+ interrupts = <0 113 4>;
+ reg = <0x10c03000 0x100>;
+ resets = <&rst SPTIMER0_RESET>;
+ clocks = <&clkmgr AGILEX5_L4_SP_CLK>;
+ clock-names = "timer";
+ status = "disabled";
+ };
+
+ timer1: timer1@10c03100 {
+ compatible = "snps,dw-apb-timer";
+ interrupts = <0 114 4>;
+ reg = <0x10c03100 0x100>;
+ resets = <&rst SPTIMER1_RESET>;
+ clocks = <&clkmgr AGILEX5_L4_SP_CLK>;
+ clock-names = "timer";
+ status = "disabled";
+ };
+
+ timer2: timer2@10d00000 {
+ compatible = "snps,dw-apb-timer";
+ interrupts = <0 115 4>;
+ reg = <0x10d00000 0x100>;
+ resets = <&rst L4SYSTIMER0_RESET>;
+ clocks = <&clkmgr AGILEX5_L4_SYS_FREE_CLK>;
+ clock-names = "timer";
+ status = "disabled";
+ };
+
+ timer3: timer3@10d00100 {
+ compatible = "snps,dw-apb-timer";
+ interrupts = <0 116 4>;
+ reg = <0x10d00100 0x100>;
+ resets = <&rst L4SYSTIMER1_RESET>;
+ clocks = <&clkmgr AGILEX5_L4_SYS_FREE_CLK>;
+ clock-names = "timer";
+ status = "disabled";
+ };
+
+ uart0: serial0@10c02000 {
+ compatible = "snps,dw-apb-uart";
+ reg = <0x10c02000 0x100>;
+ interrupts = <0 108 4>;
+ reg-shift = <2>;
+ reg-io-width = <4>;
+ resets = <&rst UART0_RESET>;
+ status = "disabled";
+ clocks = <&clkmgr AGILEX5_L4_SP_CLK>;
+ clock-frequency = <100000000>;
+ };
+
+ uart1: serial1@10c02100 {
+ compatible = "snps,dw-apb-uart";
+ reg = <0x10c02100 0x100>;
+ interrupts = <0 109 4>;
+ reg-shift = <2>;
+ reg-io-width = <4>;
+ resets = <&rst UART1_RESET>;
+ clocks = <&clkmgr AGILEX5_L4_SP_CLK>;
+ status = "disabled";
+ };
+
+ usbphy0: usbphy@0 {
+ #phy-cells = <0>;
+ compatible = "usb-nop-xceiv";
+ clocks = <&clkmgr AGILEX5_USB_CLK>;
+ status = "disabled";
+ };
+
+ usb0: usb@10b00000 {
+ compatible = "snps,dwc2";
+ reg = <0x10b00000 0x40000>;
+ interrupts = <0 93 4>;
+ phys = <&usbphy0>;
+ phy-names = "usb2-phy";
+ resets = <&rst USB0_RESET>, <&rst USB0_OCP_RESET>;
+ reset-names = "dwc2", "dwc2-ecc";
+ clocks = <&clkmgr AGILEX5_USB_CLK>;
+ iommus = <&smmu 6>;
+ status = "disabled";
+ };
+
+ usb31: usb31@11000000 {
+ compatible = "snps,dwc3";
+ reg = <0x11000000 0x100000>;
+ resets = <&rst USB1_RESET>;
+ phys = <&usbphy0>, <&usbphy0>;
+ phy-names = "usb2-phy", "usb3-phy";
+ dr_mode = "host";
+ maximum-speed = "super-speed";
+ snps,dis_u2_susphy_quirk;
+ status = "disabled";
+ };
+
+ watchdog0: watchdog@10d00200 {
+ compatible = "snps,dw-wdt";
+ reg = <0x10d00200 0x100>;
+ interrupts = <0 117 4>;
+ resets = <&rst WATCHDOG0_RESET>;
+ clocks = <&clkmgr AGILEX5_L4_SYS_FREE_CLK>;
+ status = "disabled";
+ };
+
+ watchdog1: watchdog@10d00300 {
+ compatible = "snps,dw-wdt";
+ reg = <0x10d00300 0x100>;
+ interrupts = <0 118 4>;
+ resets = <&rst WATCHDOG1_RESET>;
+ clocks = <&clkmgr AGILEX5_L4_SYS_FREE_CLK>;
+ status = "disabled";
+ };
+
+ watchdog2: watchdog@10d00400 {
+ compatible = "snps,dw-wdt";
+ reg = <0x10d00400 0x100>;
+ interrupts = <0 125 4>;
+ resets = <&rst WATCHDOG2_RESET>;
+ clocks = <&clkmgr AGILEX5_L4_SYS_FREE_CLK>;
+ status = "disabled";
+ };
+
+ watchdog3: watchdog@10d00500 {
+ compatible = "snps,dw-wdt";
+ reg = <0x10d00500 0x100>;
+ interrupts = <0 126 4>;
+ resets = <&rst WATCHDOG3_RESET>;
+ clocks = <&clkmgr AGILEX5_L4_SYS_FREE_CLK>;
+ status = "disabled";
+ };
+
+ watchdog4: watchdog@10d00600 {
+ compatible = "snps,dw-wdt";
+ reg = <0x10d00600 0x100>;
+ interrupts = <0 175 4>;
+ resets = <&rst WATCHDOG4_RESET>;
+ clocks = <&clkmgr AGILEX5_L4_SYS_FREE_CLK>;
+ status = "disabled";
+ };
+
+ /* QSPI address not available yet */
+ qspi: spi@108d2000 {
+ compatible = "cdns,qspi-nor";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0x108d2000 0x100>,
+ <0x10900000 0x100000>;
+ interrupts = <0 3 4>;
+ cdns,fifo-depth = <128>;
+ cdns,fifo-width = <4>;
+ cdns,trigger-address = <0x00000000>;
+ clocks = <&qspi_clk>;
+
+ status = "disabled";
+ };
+
+ firmware {
+ svc {
+ compatible = "intel,stratix10-svc";
+ method = "smc";
+ memory-region = <&service_reserved>;
+
+ fpga_mgr: fpga-mgr {
+ compatible = "intel,stratix10-soc-fpga-mgr";
+ };
+ };
+ };
+ };
+};
diff --git a/arch/arm/dts/socfpga_agilex5_socdk-u-boot.dtsi b/arch/arm/dts/socfpga_agilex5_socdk-u-boot.dtsi
new file mode 100644
index 0000000..9eb21d6
--- /dev/null
+++ b/arch/arm/dts/socfpga_agilex5_socdk-u-boot.dtsi
@@ -0,0 +1,124 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * U-Boot additions
+ *
+ * Copyright (C) 2024 Intel Corporation <www.intel.com>
+ */
+
+#include "socfpga_agilex5-u-boot.dtsi"
+
+/{
+ aliases {
+ spi0 = &qspi;
+ freeze_br0 = &freeze_controller;
+ };
+
+ soc {
+ freeze_controller: freeze_controller@0x20000450 {
+ compatible = "altr,freeze-bridge-controller";
+ reg = <0x20000450 0x00000010>;
+ status = "disabled";
+ };
+ };
+
+ memory {
+ /* 8GB */
+ reg = <0 0x80000000 0 0x80000000>,
+ <8 0x80000000 1 0x80000000>;
+ };
+
+ chosen {
+ stdout-path = "serial0:115200n8";
+ u-boot,spl-boot-order = &mmc,&flash0,"/memory";
+ };
+};
+
+&flash0 {
+ compatible = "jedec,spi-nor";
+ spi-tx-bus-width = <4>;
+ spi-rx-bus-width = <4>;
+ bootph-all;
+ /delete-property/ cdns,read-delay;
+};
+
+&i3c0 {
+ bootph-all;
+};
+
+&i3c1 {
+ bootph-all;
+};
+
+&mmc {
+ status = "okay";
+ bus-width = <4>;
+ sd-uhs-sdr50;
+ cap-mmc-highspeed;
+ bootph-all;
+};
+
+&combophy0 {
+ status = "okay";
+ bootph-all;
+ cdns,phy-use-ext-lpbk-dqs = <1>;
+ cdns,phy-use-lpbk-dqs = <1>;
+ cdns,phy-use-phony-dqs = <1>;
+ cdns,phy-use-phony-dqs-cmd = <1>;
+ cdns,phy-io-mask-always-on = <0>;
+ cdns,phy-io-mask-end = <5>;
+ cdns,phy-io-mask-start = <0>;
+ cdns,phy-data-select-oe-end = <1>;
+ cdns,phy-sync-method = <1>;
+ cdns,phy-sw-half-cycle-shift = <0>;
+ cdns,phy-rd-del-sel = <52>;
+ cdns,phy-underrun-suppress = <1>;
+ cdns,phy-gate-cfg-always-on = <1>;
+ cdns,phy-param-dll-bypass-mode = <1>;
+ cdns,phy-param-phase-detect-sel = <2>;
+ cdns,phy-param-dll-start-point = <254>;
+ cdns,phy-read-dqs-cmd-delay = <0>;
+ cdns,phy-clk-wrdqs-delay = <0>;
+ cdns,phy-clk-wr-delay = <0>;
+ cdns,phy-read-dqs-delay = <0>;
+ cdns,phy-phony-dqs-timing = <0>;
+ cdns,hrs09-rddata-en = <1>;
+ cdns,hrs09-rdcmd-en = <1>;
+ cdns,hrs09-extended-wr-mode = <1>;
+ cdns,hrs09-extended-rd-mode = <1>;
+ cdns,hrs10-hcsdclkadj = <3>;
+ cdns,hrs16-wrdata1-sdclk-dly = <0>;
+ cdns,hrs16-wrdata0-sdclk-dly = <0>;
+ cdns,hrs16-wrcmd1-sdclk-dly = <0>;
+ cdns,hrs16-wrcmd0-sdclk-dly = <0>;
+ cdns,hrs16-wrdata1-dly = <0>;
+ cdns,hrs16-wrdata0-dly = <0>;
+ cdns,hrs16-wrcmd1-dly = <0>;
+ cdns,hrs16-wrcmd0-dly = <0>;
+ cdns,hrs07-rw-compensate = <10>;
+ cdns,hrs07-idelay-val = <0>;
+};
+
+&qspi {
+ status = "okay";
+};
+
+&timer0 {
+ bootph-all;
+};
+
+&timer1 {
+ bootph-all;
+};
+
+&timer2 {
+ bootph-all;
+};
+
+&timer3 {
+ bootph-all;
+};
+
+&watchdog0 {
+ bootph-all;
+};
+
diff --git a/arch/arm/dts/socfpga_agilex5_socdk.dts b/arch/arm/dts/socfpga_agilex5_socdk.dts
new file mode 100644
index 0000000..852e1e5
--- /dev/null
+++ b/arch/arm/dts/socfpga_agilex5_socdk.dts
@@ -0,0 +1,163 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (C) 2024 Intel Corporation <www.intel.com>
+ */
+#include "socfpga_agilex5.dtsi"
+
+/ {
+ model = "SoCFPGA Agilex5 SoCDK";
+
+ aliases {
+ serial0 = &uart0;
+ ethernet0 = &gmac0;
+ ethernet2 = &gmac2;
+ };
+
+ leds {
+ compatible = "gpio-leds";
+ hps0 {
+ label = "hps_led0";
+ gpios = <&portb 20 GPIO_ACTIVE_HIGH>;
+ };
+
+ hps1 {
+ label = "hps_led1";
+ gpios = <&portb 19 GPIO_ACTIVE_HIGH>;
+ };
+
+ hps2 {
+ label = "hps_led2";
+ gpios = <&portb 21 GPIO_ACTIVE_HIGH>;
+ };
+ };
+
+ memory {
+ device_type = "memory";
+ /* We expect the bootloader to fill in the reg */
+ reg = <0 0 0 0>;
+ };
+
+ soc {
+ clocks {
+ osc1 {
+ clock-frequency = <25000000>;
+ };
+ };
+ };
+};
+
+&gpio0 {
+ status = "okay";
+};
+
+&gpio1 {
+ status = "okay";
+};
+
+&i2c0 {
+ status = "okay";
+};
+
+&i2c1 {
+ status = "okay";
+};
+
+&i3c0 {
+ status = "okay";
+};
+
+&i3c1 {
+ status = "okay";
+};
+
+&uart0 {
+ status = "okay";
+};
+
+&usbphy0 {
+ status = "okay";
+};
+
+&usb0 {
+ status = "okay";
+ disable-over-current;
+};
+
+&watchdog0 {
+ status = "okay";
+};
+
+&watchdog1 {
+ status = "okay";
+};
+
+&watchdog2 {
+ status = "okay";
+};
+
+&watchdog3 {
+ status = "okay";
+};
+
+&watchdog4 {
+ status = "okay";
+};
+
+&timer0 {
+ status = "okay";
+};
+
+&timer1 {
+ status = "okay";
+};
+
+&timer2 {
+ status = "okay";
+};
+
+&timer3 {
+ status = "okay";
+};
+
+&spi0 {
+ status = "okay";
+};
+
+&spi1 {
+ status = "okay";
+};
+
+&qspi {
+ flash0: flash@0 {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ compatible = "mt25qu02g";
+ reg = <0>;
+ spi-max-frequency = <100000000>;
+
+ m25p,fast-read;
+ cdns,page-size = <256>;
+ cdns,block-size = <16>;
+ cdns,read-delay = <1>;
+ cdns,tshsl-ns = <50>;
+ cdns,tsd2d-ns = <50>;
+ cdns,tchsh-ns = <4>;
+ cdns,tslch-ns = <4>;
+
+ partitions {
+ compatible = "fixed-partitions";
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ qspi_boot: partition@0 {
+ label = "u-boot";
+ reg = <0x0 0x04200000>;
+ };
+
+ root: partition@4200000 {
+ label = "root";
+ reg = <0x04200000 0x0BE00000>;
+ };
+ };
+ };
+};
diff --git a/arch/arm/dts/socfpga_soc64_fit-u-boot.dtsi b/arch/arm/dts/socfpga_soc64_fit-u-boot.dtsi
index 84b91e8..15306db 100644
--- a/arch/arm/dts/socfpga_soc64_fit-u-boot.dtsi
+++ b/arch/arm/dts/socfpga_soc64_fit-u-boot.dtsi
@@ -2,7 +2,7 @@
/*
* U-Boot additions
*
- * Copyright (C) 2020 Intel Corporation <www.intel.com>
+ * Copyright (C) 2020-2024 Intel Corporation <www.intel.com>
*/
#if defined(CONFIG_FIT)
@@ -21,14 +21,18 @@
description = "FIT with firmware and bootloader";
#address-cells = <1>;
- images {
+ images: images {
uboot {
description = "U-Boot SoC64";
type = "standalone";
os = "U-Boot";
arch = "arm64";
compression = "none";
+ #if IS_ENABLED(CONFIG_TARGET_SOCFPGA_AGILEX5)
+ load = <0x80200000>;
+ #else
load = <0x00200000>;
+ #endif
uboot_blob: blob-ext {
filename = "u-boot-nodtb.bin";
};
@@ -43,8 +47,13 @@
os = "arm-trusted-firmware";
arch = "arm64";
compression = "none";
+ #if IS_ENABLED(CONFIG_TARGET_SOCFPGA_AGILEX5)
+ load = <0x80000000>;
+ entry = <0x80000000>;
+ #else
load = <0x00001000>;
entry = <0x00001000>;
+ #endif
atf_blob: blob-ext {
filename = "bl31.bin";
};
@@ -53,11 +62,11 @@
};
};
- fdt {
- description = "U-Boot SoC64 flat device-tree";
+ fdt-0 {
+ description = "socfpga_socdk";
type = "flat_dt";
compression = "none";
- uboot_fdt_blob: blob-ext {
+ fdt_0_blob: blob-ext {
filename = "u-boot.dtb";
};
hash {
@@ -66,17 +75,18 @@
};
};
- configurations {
- default = "conf";
- conf {
- description = "Intel SoC64 FPGA";
+ board_config: configurations {
+ default = "board-0";
+
+ board-0 {
+ description = "board_0";
firmware = "atf";
loadables = "uboot";
- fdt = "fdt";
+ fdt = "fdt-0";
signature {
algo = "crc32";
key-name-hint = "dev";
- sign-images = "atf", "fdt", "uboot";
+ sign-images = "atf", "uboot", "fdt-0";
};
};
};
@@ -96,8 +106,8 @@
arch = "arm64";
os = "linux";
compression = "none";
- load = <0x4080000>;
- entry = <0x4080000>;
+ load = <0x6000000>;
+ entry = <0x6000000>;
kernel_blob: blob-ext {
filename = "Image";
};
@@ -146,7 +156,7 @@
filename = "signed-bl31.bin";
};
-&uboot_fdt_blob {
+&fdt_0_blob {
filename = "signed-u-boot.dtb";
};
diff --git a/arch/arm/dts/stv0991.dts b/arch/arm/dts/stv0991.dts
deleted file mode 100644
index b04e899..0000000
--- a/arch/arm/dts/stv0991.dts
+++ /dev/null
@@ -1,55 +0,0 @@
-/dts-v1/;
-
-/ {
- model = "ST STV0991 application board";
- compatible = "st,stv0991";
- #address-cells = <1>;
- #size-cells = <1>;
-
- chosen {
- stdout-path = &uart0;
- };
-
- memory {
- device_type="memory";
- reg = <0x0 0x198000>;
- };
-
- uart0: serial@0x80406000 {
- compatible = "arm,pl011", "arm,primecell";
- reg = <0x80406000 0x1000>;
- clock = <2700000>;
- };
-
- aliases {
- spi0 = "/spi@80203000"; /* QSPI */
- };
-
- qspi: spi@80203000 {
- compatible = "cdns,qspi-nor";
- #address-cells = <1>;
- #size-cells = <0>;
- reg = <0x80203000 0x100>,
- <0x40000000 0x1000000>;
- clocks = <3750000>;
- cdns,fifo-depth = <256>;
- cdns,fifo-width = <4>;
- cdns,trigger-address = <0x40000000>;
- status = "okay";
-
- flash0: n25q32@0 {
- #address-cells = <1>;
- #size-cells = <1>;
- compatible = "jedec,spi-nor";
- reg = <0>; /* chip select */
- spi-max-frequency = <50000000>;
- m25p,fast-read;
- page-size = <256>;
- block-size = <16>; /* 2^16, 64KB */
- cdns,tshsl-ns = <50>;
- cdns,tsd2d-ns = <50>;
- cdns,tchsh-ns = <4>;
- cdns,tslch-ns = <4>;
- };
- };
-};
diff --git a/arch/arm/dts/zynqmp-mini-nand.dts b/arch/arm/dts/zynqmp-mini-nand.dts
index e0517cf..5889d43 100644
--- a/arch/arm/dts/zynqmp-mini-nand.dts
+++ b/arch/arm/dts/zynqmp-mini-nand.dts
@@ -50,6 +50,12 @@
#size-cells = <1>;
arasan,has-mdma;
num-cs = <2>;
+ nand@0 {
+ reg = <0>;
+ #address-cells = <2>;
+ #size-cells = <1>;
+ nand-ecc-mode = "hw";
+ };
};
};
};
diff --git a/arch/arm/dts/zynqmp-sc-revB.dts b/arch/arm/dts/zynqmp-sc-revB.dts
index 8517bda..c1d713b 100644
--- a/arch/arm/dts/zynqmp-sc-revB.dts
+++ b/arch/arm/dts/zynqmp-sc-revB.dts
@@ -49,7 +49,7 @@
gpio-keys {
compatible = "gpio-keys";
autorepeat;
- fwuen {
+ key-fwuen {
label = "sw16";
gpios = <&gpio 12 GPIO_ACTIVE_LOW>;
linux,code = <BTN_MISC>;
@@ -192,7 +192,7 @@
status = "okay";
/* QSPI should also have PINCTRL setup */
flash@0 {
- compatible = "mt25qu512a", "m25p80", "jedec,spi-nor"; /* mt25qu512abb8e12 512Mib */
+ compatible = "m25p80", "jedec,spi-nor"; /* mt25qu512abb8e12 512Mib */
#address-cells = <1>;
#size-cells = <1>;
reg = <0>;
diff --git a/arch/arm/dts/zynqmp-sck-kd-g-revA.dtso b/arch/arm/dts/zynqmp-sck-kd-g-revA.dtso
index 5202b7c..1727a1c 100644
--- a/arch/arm/dts/zynqmp-sck-kd-g-revA.dtso
+++ b/arch/arm/dts/zynqmp-sck-kd-g-revA.dtso
@@ -356,6 +356,8 @@
&uart0 {
status = "okay";
+ rts-gpios = <&gpio 72 GPIO_ACTIVE_HIGH>;
+ linux,rs485-enabled-at-boot-time;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_uart0_default>;
assigned-clock-rates = <100000000>;
diff --git a/arch/arm/dts/zynqmp-sck-kr-g-revB.dtso b/arch/arm/dts/zynqmp-sck-kr-g-revB.dtso
index 6c29f65..0a0cbd2 100644
--- a/arch/arm/dts/zynqmp-sck-kr-g-revB.dtso
+++ b/arch/arm/dts/zynqmp-sck-kr-g-revB.dtso
@@ -66,6 +66,18 @@
#clock-cells = <0>;
clock-frequency = <74250000>;
};
+
+ dpcon {
+ compatible = "dp-connector";
+ label = "P11";
+ type = "full-size";
+
+ port {
+ dpcon_in: endpoint {
+ remote-endpoint = <&dpsub_dp_out>;
+ };
+ };
+ };
};
&i2c1 { /* I2C_SCK C26/C27 - MIO from SOM */
@@ -130,6 +142,14 @@
phy-names = "dp-phy0";
phys = <&psgtr 1 PHY_TYPE_DP 0 1>;
assigned-clock-rates = <27000000>, <25000000>, <300000000>;
+
+ ports {
+ port@5 {
+ dpsub_dp_out: endpoint {
+ remote-endpoint = <&dpcon_in>;
+ };
+ };
+ };
};
&zynqmp_dpdma {
diff --git a/arch/arm/dts/zynqmp-sck-kv-g-revA.dtso b/arch/arm/dts/zynqmp-sck-kv-g-revA.dtso
index 6d0d5c4..561b546 100644
--- a/arch/arm/dts/zynqmp-sck-kv-g-revA.dtso
+++ b/arch/arm/dts/zynqmp-sck-kv-g-revA.dtso
@@ -342,6 +342,7 @@
slew-rate = <SLEW_RATE_SLOW>;
power-source = <IO_STANDARD_LVCMOS18>;
bias-disable;
+ output-enable;
};
conf-cd {
diff --git a/arch/arm/dts/zynqmp-sck-kv-g-revB.dtso b/arch/arm/dts/zynqmp-sck-kv-g-revB.dtso
index a4b4465..64683e0 100644
--- a/arch/arm/dts/zynqmp-sck-kv-g-revB.dtso
+++ b/arch/arm/dts/zynqmp-sck-kv-g-revB.dtso
@@ -63,6 +63,18 @@
#clock-cells = <0>;
clock-frequency = <27000000>;
};
+
+ dpcon {
+ compatible = "dp-connector";
+ label = "P11";
+ type = "full-size";
+
+ port {
+ dpcon_in: endpoint {
+ remote-endpoint = <&dpsub_dp_out>;
+ };
+ };
+ };
};
&i2c1 { /* I2C_SCK C23/C24 - MIO from SOM */
@@ -97,6 +109,14 @@
phy-names = "dp-phy0", "dp-phy1";
phys = <&psgtr 1 PHY_TYPE_DP 0 0>, <&psgtr 0 PHY_TYPE_DP 1 0>;
assigned-clock-rates = <27000000>, <25000000>, <300000000>;
+
+ ports {
+ port@5 {
+ dpsub_dp_out: endpoint {
+ remote-endpoint = <&dpcon_in>;
+ };
+ };
+ };
};
&zynqmp_dpdma {
@@ -329,6 +349,7 @@
slew-rate = <SLEW_RATE_SLOW>;
power-source = <IO_STANDARD_LVCMOS18>;
bias-disable;
+ output-enable;
};
conf-cd {
diff --git a/arch/arm/dts/zynqmp-vp-x-a2785-00-revA.dts b/arch/arm/dts/zynqmp-vp-x-a2785-00-revA.dts
index 2a3bbe1..b626d1a 100644
--- a/arch/arm/dts/zynqmp-vp-x-a2785-00-revA.dts
+++ b/arch/arm/dts/zynqmp-vp-x-a2785-00-revA.dts
@@ -47,7 +47,7 @@
gpio-keys {
compatible = "gpio-keys";
autorepeat;
- j383 {
+ key-j383 {
label = "j383";
gpios = <&gpio 10 GPIO_ACTIVE_HIGH>;
linux,code = <BTN_MISC>;
diff --git a/arch/arm/dts/zynqmp-vpk120-revA.dts b/arch/arm/dts/zynqmp-vpk120-revA.dts
index e0e4f1b..e063288 100644
--- a/arch/arm/dts/zynqmp-vpk120-revA.dts
+++ b/arch/arm/dts/zynqmp-vpk120-revA.dts
@@ -47,7 +47,7 @@
gpio-keys {
compatible = "gpio-keys";
autorepeat;
- sw16 {
+ button-16 {
label = "sw16";
gpios = <&gpio 10 GPIO_ACTIVE_HIGH>;
linux,code = <BTN_MISC>;
diff --git a/arch/arm/dts/zynqmp-zc1751-xm017-dc3.dts b/arch/arm/dts/zynqmp-zc1751-xm017-dc3.dts
index b97f7ee..48ab619 100644
--- a/arch/arm/dts/zynqmp-zc1751-xm017-dc3.dts
+++ b/arch/arm/dts/zynqmp-zc1751-xm017-dc3.dts
@@ -136,8 +136,7 @@
reg = <0x0>;
#address-cells = <0x2>;
#size-cells = <0x1>;
- nand-ecc-mode = "soft";
- nand-ecc-algo = "bch";
+ nand-ecc-mode = "hw";
nand-rb = <0>;
label = "main-storage-0";
nand-ecc-step-size = <1024>;
@@ -173,8 +172,7 @@
reg = <0x1>;
#address-cells = <0x2>;
#size-cells = <0x1>;
- nand-ecc-mode = "soft";
- nand-ecc-algo = "bch";
+ nand-ecc-mode = "hw";
nand-rb = <0>;
label = "main-storage-1";
nand-ecc-step-size = <1024>;
diff --git a/arch/arm/dts/zynqmp-zcu208-revA.dts b/arch/arm/dts/zynqmp-zcu208-revA.dts
index b4e2474..a113e47 100644
--- a/arch/arm/dts/zynqmp-zcu208-revA.dts
+++ b/arch/arm/dts/zynqmp-zcu208-revA.dts
@@ -46,7 +46,7 @@
gpio-keys {
compatible = "gpio-keys";
autorepeat;
- sw19 {
+ switch-19 {
label = "sw19";
gpios = <&gpio 22 GPIO_ACTIVE_HIGH>;
linux,code = <KEY_DOWN>;
diff --git a/arch/arm/dts/zynqmp-zcu216-revA.dts b/arch/arm/dts/zynqmp-zcu216-revA.dts
index 6f593e8..4d7d5d2 100644
--- a/arch/arm/dts/zynqmp-zcu216-revA.dts
+++ b/arch/arm/dts/zynqmp-zcu216-revA.dts
@@ -46,7 +46,7 @@
gpio-keys {
compatible = "gpio-keys";
autorepeat;
- sw19 {
+ switch-19 {
label = "sw19";
gpios = <&gpio 22 GPIO_ACTIVE_HIGH>;
linux,code = <KEY_DOWN>;
diff --git a/arch/arm/dts/zynqmp-zcu670-revA.dts b/arch/arm/dts/zynqmp-zcu670-revA.dts
index 7f70904..def3b53 100644
--- a/arch/arm/dts/zynqmp-zcu670-revA.dts
+++ b/arch/arm/dts/zynqmp-zcu670-revA.dts
@@ -49,7 +49,7 @@
gpio-keys {
compatible = "gpio-keys";
autorepeat;
- sw1 {
+ switch-1 {
label = "sw1";
gpios = <&gpio 22 GPIO_ACTIVE_HIGH>;
linux,code = <BTN_MISC>;
diff --git a/arch/arm/dts/zynqmp-zcu670-revB.dts b/arch/arm/dts/zynqmp-zcu670-revB.dts
index 0adb206..41f9a23 100644
--- a/arch/arm/dts/zynqmp-zcu670-revB.dts
+++ b/arch/arm/dts/zynqmp-zcu670-revB.dts
@@ -49,7 +49,7 @@
gpio-keys {
compatible = "gpio-keys";
autorepeat;
- sw1 {
+ switch-1 {
label = "sw1";
gpios = <&gpio 22 GPIO_ACTIVE_HIGH>;
linux,code = <BTN_MISC>;
diff --git a/arch/arm/dts/zynqmp.dtsi b/arch/arm/dts/zynqmp.dtsi
index b50b83b..53a606c 100644
--- a/arch/arm/dts/zynqmp.dtsi
+++ b/arch/arm/dts/zynqmp.dtsi
@@ -168,7 +168,7 @@
bootph-all;
};
- pmu {
+ pmu: pmu {
compatible = "arm,armv8-pmuv3";
interrupt-parent = <&gic>;
interrupts = <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>,
@@ -1001,14 +1001,14 @@
status = "disabled";
reg = <0x0 0xfe200000 0x0 0x40000>;
interrupt-parent = <&gic>;
- interrupt-names = "host", "peripheral", "otg";
+ interrupt-names = "host", "peripheral", "otg", "wakeup";
interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>;
+ <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>;
/* iommus = <&smmu 0x860>; */
snps,quirk-frame-length-adjustment = <0x20>;
clock-names = "ref";
- snps,enable_guctl1_ipd_quirk;
snps,resume-hs-terminations;
/* dma-coherent; */
};
@@ -1033,14 +1033,14 @@
status = "disabled";
reg = <0x0 0xfe300000 0x0 0x40000>;
interrupt-parent = <&gic>;
- interrupt-names = "host", "peripheral", "otg";
+ interrupt-names = "host", "peripheral", "otg", "wakeup";
interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;
+ <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>;
/* iommus = <&smmu 0x861>; */
snps,quirk-frame-length-adjustment = <0x20>;
clock-names = "ref";
- snps,enable_guctl1_ipd_quirk;
snps,resume-hs-terminations;
/* dma-coherent; */
};
diff --git a/arch/arm/include/asm/arch-imx9/mu.h b/arch/arm/include/asm/arch-imx9/mu.h
index b860499..649b8a6 100644
--- a/arch/arm/include/asm/arch-imx9/mu.h
+++ b/arch/arm/include/asm/arch-imx9/mu.h
@@ -8,6 +8,6 @@
#include <event.h>
-int imx9_probe_mu(void *ctx, struct event *event);
+int imx9_probe_mu(void);
#endif
diff --git a/arch/arm/include/asm/arch-rockchip/cru_rk3588.h b/arch/arm/include/asm/arch-rockchip/cru_rk3588.h
index 7f4a908..a4507e5 100644
--- a/arch/arm/include/asm/arch-rockchip/cru_rk3588.h
+++ b/arch/arm/include/asm/arch-rockchip/cru_rk3588.h
@@ -63,6 +63,8 @@
unsigned int reserved0[3];
};
+#define CRU_BASE 0xfd7c0000
+
struct rk3588_cru {
struct rk3588_pll pll[18];
unsigned int reserved0[16];/* Address Offset: 0x0240 */
diff --git a/arch/arm/include/asm/arch-rockchip/grf_rk3588.h b/arch/arm/include/asm/arch-rockchip/grf_rk3588.h
index e069406..f0ecff9 100644
--- a/arch/arm/include/asm/arch-rockchip/grf_rk3588.h
+++ b/arch/arm/include/asm/arch-rockchip/grf_rk3588.h
@@ -32,4 +32,28 @@
check_member(rk3588_pmu1grf, sd_detect_cnt, 0x03b0);
+#define SYS_GRF_BASE 0xfd58c000
+
+struct rk3588_sysgrf {
+ unsigned int wdt_con0;
+ unsigned int reserved0[(0x0010 - 0x0000) / 4 - 1];
+ unsigned int uart_con[2];
+ unsigned int reserved1[(0x00c0 - 0x0014) / 4 - 1];
+ unsigned int gic_con0;
+ unsigned int reserved2[(0x0200 - 0x00c0) / 4 - 1];
+ unsigned int memcfg_con[32];
+ unsigned int reserved3[(0x0300 - 0x027c) / 4 - 1];
+ /* soc_con0 is reserved */
+ unsigned int soc_con[14];
+ unsigned int reserved4[(0x0380 - 0x0334) / 4 - 1];
+ unsigned int soc_status[4];
+ unsigned int reserved5[(0x0500 - 0x038c) / 4 - 1];
+ unsigned int otp_key08;
+ unsigned int otp_key0d;
+ unsigned int otp_key0e;
+ unsigned int reserved6[(0x0600 - 0x0508) / 4 - 1];
+ unsigned int chip_id;
+};
+
+check_member(rk3588_sysgrf, chip_id, 0x0600);
#endif /*__SOC_ROCKCHIP_RK3588_GRF_H__ */
diff --git a/arch/arm/include/asm/arch-rockchip/hardware.h b/arch/arm/include/asm/arch-rockchip/hardware.h
index 62e8bed..e4662a2 100644
--- a/arch/arm/include/asm/arch-rockchip/hardware.h
+++ b/arch/arm/include/asm/arch-rockchip/hardware.h
@@ -6,6 +6,8 @@
#ifndef _ASM_ARCH_HARDWARE_H
#define _ASM_ARCH_HARDWARE_H
+#include <asm/io.h>
+
#define RK_CLRSETBITS(clr, set) ((((clr) | (set)) << 16) | (set))
#define RK_SETBITS(set) RK_CLRSETBITS(0, set)
#define RK_CLRBITS(clr) RK_CLRSETBITS(clr, 0)
diff --git a/arch/arm/include/asm/arch-rockchip/ioc_rk3588.h b/arch/arm/include/asm/arch-rockchip/ioc_rk3588.h
index 5a656f8..7ad9846 100644
--- a/arch/arm/include/asm/arch-rockchip/ioc_rk3588.h
+++ b/arch/arm/include/asm/arch-rockchip/ioc_rk3588.h
@@ -5,6 +5,8 @@
#ifndef _ASM_ARCH_IOC_RK3588_H
#define _ASM_ARCH_IOC_RK3588_H
+#define BUS_IOC_BASE 0xfd5f8000
+
struct rk3588_bus_ioc {
unsigned int reserved0000[3]; /* Address Offset: 0x0000 */
unsigned int gpio0b_iomux_sel_h; /* Address Offset: 0x000C */
@@ -48,6 +50,8 @@
check_member(rk3588_bus_ioc, gpio4d_iomux_sel_h, 0x009C);
+#define PMU1_IOC_BASE 0xfd5f0000
+
struct rk3588_pmu1_ioc {
unsigned int gpio0a_iomux_sel_l; /* Address Offset: 0x0000 */
unsigned int gpio0a_iomux_sel_h; /* Address Offset: 0x0004 */
@@ -70,6 +74,8 @@
check_member(rk3588_pmu1_ioc, xin_con, 0x0040);
+#define PMU2_IOC_BASE 0xfd5f4000
+
struct rk3588_pmu2_ioc {
unsigned int gpio0b_iomux_sel_h; /* Address Offset: 0x0000 */
unsigned int gpio0c_iomux_sel_l; /* Address Offset: 0x0004 */
diff --git a/arch/arm/include/asm/arch-rockchip/misc.h b/arch/arm/include/asm/arch-rockchip/misc.h
deleted file mode 100644
index 4155af8..0000000
--- a/arch/arm/include/asm/arch-rockchip/misc.h
+++ /dev/null
@@ -1,14 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0+ */
-/*
- * RK3399: Architecture common definitions
- *
- * Copyright (C) 2019 Collabora Inc - https://www.collabora.com/
- * Rohan Garg <rohan.garg@collabora.com>
- */
-
-int rockchip_cpuid_from_efuse(const u32 cpuid_offset,
- const u32 cpuid_length,
- u8 *cpuid);
-int rockchip_cpuid_set(const u8 *cpuid, const u32 cpuid_length);
-int rockchip_setup_macaddr(void);
-void rockchip_capsule_update_board_setup(void);
diff --git a/arch/arm/include/asm/arch-stv0991/gpio.h b/arch/arm/include/asm/arch-stv0991/gpio.h
deleted file mode 100644
index b27f407..0000000
--- a/arch/arm/include/asm/arch-stv0991/gpio.h
+++ /dev/null
@@ -1,21 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0+ */
-/*
- * Copyright (C) 2014, STMicroelectronics - All Rights Reserved
- * Author(s): Vikas Manocha, <vikas.manocha@st.com> for STMicroelectronics.
- */
-
-#ifndef __ASM_ARCH_STV0991_GPIO_H
-#define __ASM_ARCH_STV0991_GPIO_H
-
-enum gpio_direction {
- GPIO_DIRECTION_IN,
- GPIO_DIRECTION_OUT,
-};
-
-struct gpio_regs {
- u32 data; /* offset 0x0 */
- u32 reserved[0xff]; /* 0x4--0x3fc */
- u32 dir; /* offset 0x400 */
-};
-
-#endif /* __ASM_ARCH_STV0991_GPIO_H */
diff --git a/arch/arm/include/asm/arch-stv0991/hardware.h b/arch/arm/include/asm/arch-stv0991/hardware.h
deleted file mode 100644
index ea8f820..0000000
--- a/arch/arm/include/asm/arch-stv0991/hardware.h
+++ /dev/null
@@ -1,72 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0+ */
-/*
- * Copyright (C) 2014, STMicroelectronics - All Rights Reserved
- * Author(s): Vikas Manocha, <vikas.manocha@st.com> for STMicroelectronics.
- */
-
-#ifndef _ASM_ARCH_HARDWARE_H
-#define _ASM_ARCH_HARDWARE_H
-
-/* STV0991 */
-#define SRAM0_BASE_ADDR 0x00000000UL
-#define SRAM1_BASE_ADDR 0x00068000UL
-#define SRAM2_BASE_ADDR 0x000D0000UL
-#define SRAM3_BASE_ADDR 0x00138000UL
-#define CFS_SRAM0_BASE_ADDR 0x00198000UL
-#define CFS_SRAM1_BASE_ADDR 0x001B8000UL
-#define FAST_SRAM_BASE_ADDR 0x001D8000UL
-#define FLASH_BASE_ADDR 0x40000000UL
-#define PL310_BASE_ADDR 0x70000000UL
-#define HSAXIM_BASE_ADDR 0x70100000UL
-#define IMGSS_BASE_ADDR 0x70200000UL
-#define ADC_BASE_ADDR 0x80000000UL
-#define GPIOA_BASE_ADDR 0x80001000UL
-#define GPIOB_BASE_ADDR 0x80002000UL
-#define GPIOC_BASE_ADDR 0x80003000UL
-#define HDM_BASE_ADDR 0x80004000UL
-#define THSENS_BASE_ADDR 0x80200000UL
-#define GPTIMER2_BASE_ADDR 0x80201000UL
-#define GPTIMER1_BASE_ADDR 0x80202000UL
-#define QSPI_BASE_ADDR 0x80203000UL
-#define CGU_BASE_ADDR 0x80204000UL
-#define CREG_BASE_ADDR 0x80205000UL
-#define PEC_BASE_ADDR 0x80206000UL
-#define WDRU_BASE_ADDR 0x80207000UL
-#define BSEC_BASE_ADDR 0x80208000UL
-#define DAP_ROM_BASE_ADDR 0x80210000UL
-#define SOC_CTI_BASE_ADDR 0x80211000UL
-#define TPIU_BASE_ADDR 0x80212000UL
-#define TMC_ETF_BASE_ADDR 0x80213000UL
-#define R4_ETM_BASE_ADDR 0x80214000UL
-#define R4_CTI_BASE_ADDR 0x80215000UL
-#define R4_DBG_BASE_ADDR 0x80216000UL
-#define GMAC_BASE_ADDR 0x80300000UL
-#define RNSS_BASE_ADDR 0x80302000UL
-#define CRYP_BASE_ADDR 0x80303000UL
-#define HASH_BASE_ADDR 0x80304000UL
-#define GPDMA_BASE_ADDR 0x80305000UL
-#define ISA_BASE_ADDR 0x8032A000UL
-#define HCI_BASE_ADDR 0x80400000UL
-#define I2C1_BASE_ADDR 0x80401000UL
-#define I2C2_BASE_ADDR 0x80402000UL
-#define SAI_BASE_ADDR 0x80403000UL
-#define USI_BASE_ADDR 0x80404000UL
-#define SPI1_BASE_ADDR 0x80405000UL
-#define UART_BASE_ADDR 0x80406000UL
-#define SPI2_BASE_ADDR 0x80500000UL
-#define CAN_BASE_ADDR 0x80501000UL
-#define USART1_BASE_ADDR 0x80502000UL
-#define USART2_BASE_ADDR 0x80503000UL
-#define USART3_BASE_ADDR 0x80504000UL
-#define USART4_BASE_ADDR 0x80505000UL
-#define USART5_BASE_ADDR 0x80506000UL
-#define USART6_BASE_ADDR 0x80507000UL
-#define SDI2_BASE_ADDR 0x80600000UL
-#define SDI1_BASE_ADDR 0x80601000UL
-#define VICA_BASE_ADDR 0x81000000UL
-#define VICB_BASE_ADDR 0x81001000UL
-#define STM_CHANNELS_BASE_ADDR 0x81100000UL
-#define STM_BASE_ADDR 0x81110000UL
-#define SROM_BASE_ADDR 0xFFFF0000UL
-
-#endif /* _ASM_ARCH_HARDWARE_H */
diff --git a/arch/arm/include/asm/arch-stv0991/stv0991_cgu.h b/arch/arm/include/asm/arch-stv0991/stv0991_cgu.h
deleted file mode 100644
index df9dd54..0000000
--- a/arch/arm/include/asm/arch-stv0991/stv0991_cgu.h
+++ /dev/null
@@ -1,130 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0+ */
-/*
- * Copyright (C) 2014, STMicroelectronics - All Rights Reserved
- * Author(s): Vikas Manocha, <vikas.manocha@st.com> for STMicroelectronics.
- */
-
-#ifndef _STV0991_CGU_H
-#define _STV0991_CGU_H
-
-struct stv0991_cgu_regs {
- u32 cpu_freq; /* offset 0x0 */
- u32 icn2_freq; /* offset 0x4 */
- u32 dma_freq; /* offset 0x8 */
- u32 isp_freq; /* offset 0xc */
- u32 h264_freq; /* offset 0x10 */
- u32 osif_freq; /* offset 0x14 */
- u32 ren_freq; /* offset 0x18 */
- u32 tim_freq; /* offset 0x1c */
- u32 sai_freq; /* offset 0x20 */
- u32 eth_freq; /* offset 0x24 */
- u32 i2c_freq; /* offset 0x28 */
- u32 spi_freq; /* offset 0x2c */
- u32 uart_freq; /* offset 0x30 */
- u32 qspi_freq; /* offset 0x34 */
- u32 sdio_freq; /* offset 0x38 */
- u32 usi_freq; /* offset 0x3c */
- u32 can_line_freq; /* offset 0x40 */
- u32 debug_freq; /* offset 0x44 */
- u32 trace_freq; /* offset 0x48 */
- u32 stm_freq; /* offset 0x4c */
- u32 eth_ctrl; /* offset 0x50 */
- u32 reserved[3]; /* offset 0x54 */
- u32 osc_ctrl; /* offset 0x60 */
- u32 pll1_ctrl; /* offset 0x64 */
- u32 pll1_freq; /* offset 0x68 */
- u32 pll1_fract; /* offset 0x6c */
- u32 pll1_spread; /* offset 0x70 */
- u32 pll1_status; /* offset 0x74 */
- u32 pll2_ctrl; /* offset 0x78 */
- u32 pll2_freq; /* offset 0x7c */
- u32 pll2_fract; /* offset 0x80 */
- u32 pll2_spread; /* offset 0x84 */
- u32 pll2_status; /* offset 0x88 */
- u32 cgu_enable_1; /* offset 0x8c */
- u32 cgu_enable_2; /* offset 0x90 */
- u32 cgu_isp_pulse; /* offset 0x94 */
- u32 cgu_h264_pulse; /* offset 0x98 */
- u32 cgu_osif_pulse; /* offset 0x9c */
- u32 cgu_ren_pulse; /* offset 0xa0 */
-
-};
-
-/* CGU Timer */
-#define CLK_TMR_OSC 0
-#define CLK_TMR_MCLK 1
-#define CLK_TMR_PLL1 2
-#define CLK_TMR_PLL2 3
-#define MDIV_SHIFT_TMR 3
-#define DIV_SHIFT_TMR 6
-
-#define TIMER1_CLK_CFG (0 << DIV_SHIFT_TMR \
- | 0 << MDIV_SHIFT_TMR | CLK_TMR_MCLK)
-
-/* Clock Enable/Disable */
-
-#define TIMER1_CLK_EN (1 << 15)
-
-/* CGU Uart config */
-#define CLK_UART_MCLK 0
-#define CLK_UART_PLL1 1
-#define CLK_UART_PLL2 2
-
-#define MDIV_SHIFT_UART 3
-#define DIV_SHIFT_UART 6
-
-#define UART_CLK_CFG (4 << DIV_SHIFT_UART \
- | 1 << MDIV_SHIFT_UART | CLK_UART_MCLK)
-
-/* CGU Ethernet clock config */
-#define CLK_ETH_MCLK 0
-#define CLK_ETH_PLL1 1
-#define CLK_ETH_PLL2 2
-
-#define MDIV_SHIFT_ETH 3
-#define DIV_SHIFT_ETH 6
-#define DIV_ETH_125 9
-#define DIV_ETH_50 12
-#define DIV_ETH_P2P 15
-
-#define ETH_CLK_CFG (4 << DIV_ETH_P2P | 4 << DIV_ETH_50 \
- | 1 << DIV_ETH_125 \
- | 0 << DIV_SHIFT_ETH \
- | 3 << MDIV_SHIFT_ETH | CLK_ETH_PLL1)
- /* CGU Ethernet control */
-
-#define ETH_CLK_TX_EXT_PHY 0
-#define ETH_CLK_TX_125M 1
-#define ETH_CLK_TX_25M 2
-#define ETH_CLK_TX_2M5 3
-#define ETH_CLK_TX_DIS 7
-
-#define ETH_CLK_RX_EXT_PHY 0
-#define ETH_CLK_RX_25M 1
-#define ETH_CLK_RX_2M5 2
-#define ETH_CLK_RX_DIS 3
-#define RX_CLK_SHIFT 3
-#define ETH_CLK_MASK ~(0x1F)
-
-#define ETH_PHY_MODE_GMII 0
-#define ETH_PHY_MODE_RMII 1
-#define ETH_PHY_CLK_DIS 1
-
-#define ETH_CLK_CTRL (ETH_CLK_RX_EXT_PHY << RX_CLK_SHIFT \
- | ETH_CLK_TX_EXT_PHY)
-/* CGU qspi clock */
-#define DIV_HCLK1_SHIFT 9
-#define DIV_CRYP_SHIFT 6
-#define MDIV_QSPI_SHIFT 3
-
-#define CLK_QSPI_OSC 0
-#define CLK_QSPI_MCLK 1
-#define CLK_QSPI_PLL1 2
-#define CLK_QSPI_PLL2 3
-
-#define QSPI_CLK_CTRL (3 << DIV_HCLK1_SHIFT \
- | 1 << DIV_CRYP_SHIFT \
- | 0 << MDIV_QSPI_SHIFT \
- | CLK_QSPI_OSC)
-
-#endif
diff --git a/arch/arm/include/asm/arch-stv0991/stv0991_creg.h b/arch/arm/include/asm/arch-stv0991/stv0991_creg.h
deleted file mode 100644
index 4d444a6..0000000
--- a/arch/arm/include/asm/arch-stv0991/stv0991_creg.h
+++ /dev/null
@@ -1,103 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0+ */
-/*
- * Copyright (C) 2014, STMicroelectronics - All Rights Reserved
- * Author(s): Vikas Manocha, <vikas.manocha@st.com> for STMicroelectronics.
- */
-
-#ifndef _STV0991_CREG_H
-#define _STV0991_CREG_H
-
-struct stv0991_creg {
- u32 version; /* offset 0x0 */
- u32 hdpctl; /* offset 0x4 */
- u32 hdpval; /* offset 0x8 */
- u32 hdpgposet; /* offset 0xc */
- u32 hdpgpoclr; /* offset 0x10 */
- u32 hdpgpoval; /* offset 0x14 */
- u32 stm_mux; /* offset 0x18 */
- u32 sysctrl_1; /* offset 0x1c */
- u32 sysctrl_2; /* offset 0x20 */
- u32 sysctrl_3; /* offset 0x24 */
- u32 sysctrl_4; /* offset 0x28 */
- u32 reserved_1[0x35]; /* offset 0x2C-0xFC */
- u32 mux1; /* offset 0x100 */
- u32 mux2; /* offset 0x104 */
- u32 mux3; /* offset 0x108 */
- u32 mux4; /* offset 0x10c */
- u32 mux5; /* offset 0x110 */
- u32 mux6; /* offset 0x114 */
- u32 mux7; /* offset 0x118 */
- u32 mux8; /* offset 0x11c */
- u32 mux9; /* offset 0x120 */
- u32 mux10; /* offset 0x124 */
- u32 mux11; /* offset 0x128 */
- u32 mux12; /* offset 0x12c */
- u32 mux13; /* offset 0x130 */
- u32 reserved_2[0x33]; /* offset 0x134-0x1FC */
- u32 cfg_pad1; /* offset 0x200 */
- u32 cfg_pad2; /* offset 0x204 */
- u32 cfg_pad3; /* offset 0x208 */
- u32 cfg_pad4; /* offset 0x20c */
- u32 cfg_pad5; /* offset 0x210 */
- u32 cfg_pad6; /* offset 0x214 */
- u32 cfg_pad7; /* offset 0x218 */
- u32 reserved_3[0x39]; /* offset 0x21C-0x2FC */
- u32 vdd_pad1; /* offset 0x300 */
- u32 vdd_pad2; /* offset 0x304 */
- u32 reserved_4[0x3e]; /* offset 0x308-0x3FC */
- u32 vdd_comp1; /* offset 0x400 */
-};
-
-/* CREG MUX 13 register */
-#define FLASH_CS_NC_SHIFT 4
-#define FLASH_CS_NC_MASK ~(7 << FLASH_CS_NC_SHIFT)
-#define CFG_FLASH_CS_NC (0 << FLASH_CS_NC_SHIFT)
-
-#define FLASH_CLK_SHIFT 0
-#define FLASH_CLK_MASK ~(7 << FLASH_CLK_SHIFT)
-#define CFG_FLASH_CLK (0 << FLASH_CLK_SHIFT)
-
-/* CREG MUX 12 register */
-#define GPIOC_30_MUX_SHIFT 24
-#define GPIOC_30_MUX_MASK ~(1 << GPIOC_30_MUX_SHIFT)
-#define CFG_GPIOC_30_UART_TX (1 << GPIOC_30_MUX_SHIFT)
-
-#define GPIOC_31_MUX_SHIFT 28
-#define GPIOC_31_MUX_MASK ~(1 << GPIOC_31_MUX_SHIFT)
-#define CFG_GPIOC_31_UART_RX (1 << GPIOC_31_MUX_SHIFT)
-
-/* CREG MUX 7 register */
-#define GPIOB_16_MUX_SHIFT 0
-#define GPIOB_16_MUX_MASK ~(1 << GPIOB_16_MUX_SHIFT)
-#define CFG_GPIOB_16_UART_TX (1 << GPIOB_16_MUX_SHIFT)
-
-#define GPIOB_17_MUX_SHIFT 4
-#define GPIOB_17_MUX_MASK ~(1 << GPIOB_17_MUX_SHIFT)
-#define CFG_GPIOB_17_UART_RX (1 << GPIOB_17_MUX_SHIFT)
-
-/* CREG CFG_PAD6 register */
-
-#define GPIOC_31_MODE_SHIFT 30
-#define GPIOC_31_MODE_MASK ~(1 << GPIOC_31_MODE_SHIFT)
-#define CFG_GPIOC_31_MODE_OD (0 << GPIOC_31_MODE_SHIFT)
-#define CFG_GPIOC_31_MODE_PP (1 << GPIOC_31_MODE_SHIFT)
-
-#define GPIOC_30_MODE_SHIFT 28
-#define GPIOC_30_MODE_MASK ~(1 << GPIOC_30_MODE_SHIFT)
-#define CFG_GPIOC_30_MODE_LOW (0 << GPIOC_30_MODE_SHIFT)
-#define CFG_GPIOC_30_MODE_HIGH (1 << GPIOC_30_MODE_SHIFT)
-
-/* CREG Ethernet pad config */
-
-#define VDD_ETH_PS_1V8 0
-#define VDD_ETH_PS_2V5 2
-#define VDD_ETH_PS_3V3 3
-#define VDD_ETH_PS_MASK 0x3
-
-#define VDD_ETH_PS_SHIFT 12
-#define ETH_VDD_CFG (VDD_ETH_PS_1V8 << VDD_ETH_PS_SHIFT)
-
-#define VDD_ETH_M_PS_SHIFT 28
-#define ETH_M_VDD_CFG (VDD_ETH_PS_1V8 << VDD_ETH_M_PS_SHIFT)
-
-#endif
diff --git a/arch/arm/include/asm/arch-stv0991/stv0991_defs.h b/arch/arm/include/asm/arch-stv0991/stv0991_defs.h
deleted file mode 100644
index 98d7cde..0000000
--- a/arch/arm/include/asm/arch-stv0991/stv0991_defs.h
+++ /dev/null
@@ -1,14 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0+ */
-/*
- * Copyright (C) 2014, STMicroelectronics - All Rights Reserved
- * Author(s): Vikas Manocha, <vikas.manocha@st.com> for STMicroelectronics.
- */
-
-#ifndef __STV0991_DEFS_H__
-#define __STV0991_DEFS_H__
-#include <asm/arch/stv0991_periph.h>
-
-extern int stv0991_pinmux_config(enum periph_id);
-extern int clock_setup(enum periph_clock);
-
-#endif
diff --git a/arch/arm/include/asm/arch-stv0991/stv0991_gpt.h b/arch/arm/include/asm/arch-stv0991/stv0991_gpt.h
deleted file mode 100644
index eb1ddca..0000000
--- a/arch/arm/include/asm/arch-stv0991/stv0991_gpt.h
+++ /dev/null
@@ -1,41 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0+ */
-/*
- * Copyright (C) 2014, STMicroelectronics - All Rights Reserved
- * Author(s): Vikas Manocha, <vikas.manocha@st.com> for STMicroelectronics.
- */
-
-#ifndef _STV0991_GPT_H
-#define _STV0991_GPT_H
-
-#include <asm/arch-stv0991/hardware.h>
-
-struct gpt_regs {
- u32 cr1;
- u32 cr2;
- u32 reserved_1;
- u32 dier; /* dma_int_en */
- u32 sr; /* status reg */
- u32 egr; /* event gen */
- u32 reserved_2[3]; /* offset 0x18--0x20*/
- u32 cnt;
- u32 psc;
- u32 arr;
-};
-
-struct gpt_regs *const gpt1_regs_ptr =
- (struct gpt_regs *) GPTIMER1_BASE_ADDR;
-
-/* Timer control1 register */
-#define GPT_CR1_CEN 0x0001
-#define GPT_MODE_AUTO_RELOAD (1 << 7)
-
-/* Timer prescalar reg */
-#define GPT_PRESCALER_128 0x128
-
-/* Auto reload register for free running config */
-#define GPT_FREE_RUNNING 0xFFFF
-
-/* Timer, HZ specific defines */
-#define CFG_SYS_HZ_CLOCK ((27 * 1000 * 1000) / GPT_PRESCALER_128)
-
-#endif
diff --git a/arch/arm/include/asm/arch-stv0991/stv0991_periph.h b/arch/arm/include/asm/arch-stv0991/stv0991_periph.h
deleted file mode 100644
index 7a50be1..0000000
--- a/arch/arm/include/asm/arch-stv0991/stv0991_periph.h
+++ /dev/null
@@ -1,45 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0+ */
-/*
- * Copyright (C) 2014, STMicroelectronics - All Rights Reserved
- * Author(s): Vikas Manocha, <vikas.manocha@st.com> for STMicroelectronics.
- */
-
-#ifndef __ASM_ARM_ARCH_PERIPH_H
-#define __ASM_ARM_ARCH_PERIPH_H
-
-/*
- * Peripherals required for pinmux configuration. List will
- * grow with support for more devices getting added.
- * Numbering based on interrupt table.
- *
- */
-enum periph_id {
- UART_GPIOC_30_31 = 0,
- UART_GPIOB_16_17,
- ETH_GPIOB_10_31_C_0_4,
- QSPI_CS_CLK_PAD,
- PERIPH_ID_I2C0,
- PERIPH_ID_I2C1,
- PERIPH_ID_I2C2,
- PERIPH_ID_I2C3,
- PERIPH_ID_I2C4,
- PERIPH_ID_I2C5,
- PERIPH_ID_I2C6,
- PERIPH_ID_I2C7,
- PERIPH_ID_SPI0,
- PERIPH_ID_SPI1,
- PERIPH_ID_SPI2,
- PERIPH_ID_SDMMC0,
- PERIPH_ID_SDMMC1,
- PERIPH_ID_SDMMC2,
- PERIPH_ID_SDMMC3,
- PERIPH_ID_I2S1,
-};
-
-enum periph_clock {
- UART_CLOCK_CFG = 0,
- ETH_CLOCK_CFG,
- QSPI_CLOCK_CFG,
-};
-
-#endif /* __ASM_ARM_ARCH_PERIPH_H */
diff --git a/arch/arm/include/asm/arch-stv0991/stv0991_wdru.h b/arch/arm/include/asm/arch-stv0991/stv0991_wdru.h
deleted file mode 100644
index 8cb8a8a..0000000
--- a/arch/arm/include/asm/arch-stv0991/stv0991_wdru.h
+++ /dev/null
@@ -1,27 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0+ */
-/*
- * Copyright (C) 2014, STMicroelectronics - All Rights Reserved
- * Author(s): Vikas Manocha, <vikas.manocha@st.com> for STMicroelectronics.
- */
-
-#ifndef _STV0991_WD_RST_H
-#define _STV0991_WD_RST_H
-#include <asm/arch-stv0991/hardware.h>
-
-struct stv0991_wd_ru {
- u32 wdru_config;
- u32 wdru_ctrl1;
- u32 wdru_ctrl2;
- u32 wdru_tim;
- u32 wdru_count;
- u32 wdru_stat;
- u32 wdru_wrlock;
-};
-
-struct stv0991_wd_ru *const stv0991_wd_ru_ptr = \
- (struct stv0991_wd_ru *)WDRU_BASE_ADDR;
-
-/* Watchdog control register */
-#define WDRU_RST_SYS 0x1
-
-#endif
diff --git a/arch/arm/include/asm/gic.h b/arch/arm/include/asm/gic.h
index bd3a80c..fb64ba0 100644
--- a/arch/arm/include/asm/gic.h
+++ b/arch/arm/include/asm/gic.h
@@ -57,6 +57,7 @@
#define GICR_TYPER 0x0008
#define GICR_STATUSR 0x0010
#define GICR_WAKER 0x0014
+#define GICR_PWRR 0x0024
#define GICR_SETLPIR 0x0040
#define GICR_CLRLPIR 0x0048
#define GICR_SEIR 0x0068
diff --git a/arch/arm/include/asm/mach-imx/ele_api.h b/arch/arm/include/asm/mach-imx/ele_api.h
index cfd4ece..a29b849 100644
--- a/arch/arm/include/asm/mach-imx/ele_api.h
+++ b/arch/arm/include/asm/mach-imx/ele_api.h
@@ -24,6 +24,7 @@
#define ELE_GET_FW_VERSION_REQ (0x9D)
#define ELE_RET_LIFECYCLE_UP_REQ (0xA0)
#define ELE_GET_EVENTS_REQ (0xA2)
+#define ELE_COMMIT_REQ (0xA8)
#define ELE_START_RNG (0xA3)
#define ELE_GENERATE_DEK_BLOB (0xAF)
#define ELE_ENABLE_PATCH_REQ (0xC3)
@@ -142,6 +143,7 @@
int ele_release_caam(u32 core_did, u32 *response);
int ele_get_fw_version(u32 *fw_version, u32 *sha1, u32 *response);
int ele_get_events(u32 *events, u32 *events_cnt, u32 *response);
+int ele_commit(u16 fuse_id, u32 *response, u32 *info_type);
int ele_generate_dek_blob(u32 key_id, u32 src_paddr, u32 dst_paddr, u32 max_output_size);
int ele_dump_buffer(u32 *buffer, u32 buffer_length);
int ele_get_info(struct ele_get_info_data *info, u32 *response);
diff --git a/arch/arm/lib/Makefile b/arch/arm/lib/Makefile
index 67275fb..b55167e 100644
--- a/arch/arm/lib/Makefile
+++ b/arch/arm/lib/Makefile
@@ -31,7 +31,7 @@
obj-$(CONFIG_CPU_V7M) += cmd_boot.o
obj-$(CONFIG_OF_LIBFDT) += bootm-fdt.o
obj-$(CONFIG_CMD_BOOTI) += bootm.o image.o
-obj-$(CONFIG_CMD_BOOTM) += bootm.o
+obj-$(CONFIG_BOOTM) += bootm.o
obj-$(CONFIG_CMD_BOOTZ) += bootm.o zimage.o
else
obj-$(CONFIG_$(SPL_TPL_)FRAMEWORK) += spl.o
diff --git a/arch/arm/lib/gic_64.S b/arch/arm/lib/gic_64.S
index 86cd882..7fa4864 100644
--- a/arch/arm/lib/gic_64.S
+++ b/arch/arm/lib/gic_64.S
@@ -92,8 +92,16 @@
add x9, x9, #(2 << 16)
b 1b
+2:
+#if defined(CONFIG_GICV3_SUPPORT_GIC600)
+ mov w10, #0x0 /* Power on redistributor */
+ str w10, [x9, GICR_PWRR]
+5: ldr w10, [x9, GICR_PWRR] /* Wait until the power on state is reflected */
+ tbnz w10, #1, 5b /* If RDPD == 0 then powered on */
+#endif
+
/* x9: ReDistributor Base Address of Current CPU */
-2: mov w10, #~0x2
+ mov w10, #~0x2
ldr w11, [x9, GICR_WAKER]
and w11, w11, w10 /* Clear ProcessorSleep */
str w11, [x9, GICR_WAKER]
diff --git a/arch/arm/lib/sections.c b/arch/arm/lib/sections.c
index 8578797..db5463b 100644
--- a/arch/arm/lib/sections.c
+++ b/arch/arm/lib/sections.c
@@ -19,18 +19,8 @@
* aliasing warnings.
*/
-char __bss_start[0] __section(".__bss_start");
-char __bss_end[0] __section(".__bss_end");
-char __image_copy_start[0] __section(".__image_copy_start");
-char __image_copy_end[0] __section(".__image_copy_end");
-char __rel_dyn_start[0] __section(".__rel_dyn_start");
-char __rel_dyn_end[0] __section(".__rel_dyn_end");
char __secure_start[0] __section(".__secure_start");
char __secure_end[0] __section(".__secure_end");
char __secure_stack_start[0] __section(".__secure_stack_start");
char __secure_stack_end[0] __section(".__secure_stack_end");
-char __efi_runtime_start[0] __section(".__efi_runtime_start");
-char __efi_runtime_stop[0] __section(".__efi_runtime_stop");
-char __efi_runtime_rel_start[0] __section(".__efi_runtime_rel_start");
-char __efi_runtime_rel_stop[0] __section(".__efi_runtime_rel_stop");
char _end[0] __section(".__end");
diff --git a/arch/arm/mach-aspeed/ast2600/u-boot-spl.lds b/arch/arm/mach-aspeed/ast2600/u-boot-spl.lds
index 37f0ccd..ada6570 100644
--- a/arch/arm/mach-aspeed/ast2600/u-boot-spl.lds
+++ b/arch/arm/mach-aspeed/ast2600/u-boot-spl.lds
@@ -22,9 +22,9 @@
. = 0x00000000;
. = ALIGN(4);
+ __image_copy_start = ADDR(.text);
.text :
{
- __image_copy_start = .;
*(.vectors)
CPUDIR/start.o (.text*)
*(.text*)
diff --git a/arch/arm/mach-at91/Kconfig b/arch/arm/mach-at91/Kconfig
index c5fd869..8a8ac53 100644
--- a/arch/arm/mach-at91/Kconfig
+++ b/arch/arm/mach-at91/Kconfig
@@ -286,6 +286,15 @@
select BOARD_EARLY_INIT_F
select BOARD_LATE_INIT
+config TARGET_SAMA7G54_CURIOSITY
+ bool "SAMA7G54 CURIOSITY board"
+ select SAMA7G5
+ select CPU_V7A
+ help
+ The SAMA7G54 Curiosity embeds SAMA7G54D2G SiP (System in Package)
+ with 2Gbit DDR3-SDRAM, 64Mbit QSPI nor-flash with MAC-address,
+ 4Gbit SLC nand-flash, MCP16502 PMIC, 2 x Mikrobus connectors,
+ 1 x SD-Card connector, 1 x M.2 slot, 3 x USB
config TARGET_TAURUS
bool "Support taurus"
@@ -366,6 +375,7 @@
source "board/atmel/sam9x60ek/Kconfig"
source "board/atmel/sam9x60_curiosity/Kconfig"
source "board/atmel/sama7g5ek/Kconfig"
+source "board/atmel/sama7g54_curiosity/Kconfig"
source "board/atmel/sama5d2_ptc_ek/Kconfig"
source "board/atmel/sama5d2_xplained/Kconfig"
source "board/atmel/sama5d27_som1_ek/Kconfig"
diff --git a/arch/arm/mach-imx/ele_ahab.c b/arch/arm/mach-imx/ele_ahab.c
index 295c055..d02316e 100644
--- a/arch/arm/mach-imx/ele_ahab.c
+++ b/arch/arm/mach-imx/ele_ahab.c
@@ -625,6 +625,29 @@
return CMD_RET_SUCCESS;
}
+static int do_ahab_commit(struct cmd_tbl *cmdtp, int flag, int argc,
+ char *const argv[])
+{
+ u32 index;
+ u32 resp;
+ u32 info_type;
+
+ if (argc < 2)
+ return CMD_RET_USAGE;
+
+ index = simple_strtoul(argv[1], NULL, 16);
+ printf("Commit index is 0x%x\n", index);
+
+ if (ele_commit(index, &resp, &info_type)) {
+ printf("Error in AHAB commit\n");
+ return -EIO;
+ }
+
+ printf("Ahab commit succeeded. Information type is 0x%x\n", info_type);
+
+ return 0;
+}
+
U_BOOT_CMD(auth_cntr, CONFIG_SYS_MAXARGS, 1, do_authenticate,
"autenticate OS container via AHAB",
"addr\n"
@@ -657,3 +680,9 @@
"addr\n"
"addr - Return lifecycle message block signed by OEM SRK\n"
);
+
+U_BOOT_CMD(ahab_commit, CONFIG_SYS_MAXARGS, 1, do_ahab_commit,
+ "commit into the fuses any new SRK revocation and FW version information\n"
+ "that have been found into the NXP (ELE FW) and OEM containers",
+ ""
+);
diff --git a/arch/arm/mach-imx/image-container.c b/arch/arm/mach-imx/image-container.c
index c9455fe..35da0ae 100644
--- a/arch/arm/mach-imx/image-container.c
+++ b/arch/arm/mach-imx/image-container.c
@@ -262,7 +262,7 @@
}
#ifdef CONFIG_SPL_SPI_LOAD
-unsigned long spl_spi_get_uboot_offs(struct spi_flash *flash)
+unsigned int spl_spi_get_uboot_offs(struct spi_flash *flash)
{
int end;
diff --git a/arch/arm/mach-imx/imx8/cpu.c b/arch/arm/mach-imx/imx8/cpu.c
index 0b91e44..6e64318 100644
--- a/arch/arm/mach-imx/imx8/cpu.c
+++ b/arch/arm/mach-imx/imx8/cpu.c
@@ -84,6 +84,10 @@
}
}
+__weak void reset_cpu(void)
+{
+}
+
int arch_cpu_init(void)
{
#if defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_RECOVER_DATA_SECTION)
diff --git a/arch/arm/mach-imx/imx8m/Kconfig b/arch/arm/mach-imx/imx8m/Kconfig
index 328c3e3..23d9217 100644
--- a/arch/arm/mach-imx/imx8m/Kconfig
+++ b/arch/arm/mach-imx/imx8m/Kconfig
@@ -53,6 +53,7 @@
select FSL_CAAM
select ARCH_MISC_INIT
select SPL_CRYPTO if SPL
+ imply OF_UPSTREAM
config TARGET_IMX8MQ_PHANBELL
bool "imx8mq_phanbell"
@@ -78,6 +79,7 @@
select FSL_CAAM
select ARCH_MISC_INIT
select SPL_CRYPTO if SPL
+ imply OF_UPSTREAM
config TARGET_IMX8MM_ICORE_MX8MM
bool "Engicam i.Core MX8M Mini SOM"
@@ -119,6 +121,7 @@
select FSL_CAAM
select ARCH_MISC_INIT
select SPL_CRYPTO if SPL
+ imply OF_UPSTREAM
config TARGET_KONTRON_MX8MM
bool "Kontron Electronics N80xx"
@@ -148,6 +151,7 @@
select IMX8M_LPDDR4
select FSL_CAAM
select SPL_CRYPTO if SPL
+ imply OF_UPSTREAM
config TARGET_IMX8MN_DDR4_EVK
bool "imx8mn DDR4 EVK board"
@@ -156,6 +160,7 @@
select IMX8M_DDR4
select FSL_CAAM
select SPL_CRYPTO if SPL
+ imply OF_UPSTREAM
config TARGET_IMX8MN_VENICE
bool "Support Gateworks Venice iMX8M Nano module"
@@ -167,6 +172,7 @@
select FSL_CAAM
select ARCH_MISC_INIT
select SPL_CRYPTO if SPL
+ imply OF_UPSTREAM
config TARGET_IMX8MP_DATA_MODUL_EDM_SBC
bool "Data Modul eDM SBC i.MX8M Plus"
@@ -182,6 +188,7 @@
select FSL_CAAM
select ARCH_MISC_INIT
select SPL_CRYPTO if SPL
+ imply OF_UPSTREAM
config TARGET_IMX8MP_DEBIX_MODEL_A
bool "Polyhex i.MX8M Plus Debix Model A SBC"
@@ -216,6 +223,7 @@
select FSL_CAAM
select ARCH_MISC_INIT
select SPL_CRYPTO if SPL
+ imply OF_UPSTREAM
config TARGET_IMX8MP_VENICE
bool "Support Gateworks Venice iMX8M Plus module"
@@ -227,6 +235,7 @@
select FSL_CAAM
select ARCH_MISC_INIT
select SPL_CRYPTO if SPL
+ imply OF_UPSTREAM
config TARGET_PICO_IMX8MQ
bool "Support Technexion Pico iMX8MQ"
@@ -253,12 +262,14 @@
select IMX8MM
select SUPPORT_SPL
select IMX8M_LPDDR4
+ imply OF_UPSTREAM
config TARGET_VERDIN_IMX8MP
bool "Support Toradex Verdin iMX8M Plus module"
select IMX8MP
select SUPPORT_SPL
select IMX8M_LPDDR4
+ imply OF_UPSTREAM
config TARGET_IMX8MM_BEACON
bool "imx8mm Beacon Embedded devkit"
@@ -268,6 +279,7 @@
select FSL_CAAM
select ARCH_MISC_INIT
select SPL_CRYPTO if SPL
+ imply OF_UPSTREAM
config TARGET_IMX8MN_BEACON
bool "imx8mn Beacon Embedded devkit"
@@ -277,6 +289,7 @@
select FSL_CAAM
select ARCH_MISC_INIT
select SPL_CRYPTO if SPL
+ imply OF_UPSTREAM
config TARGET_PHYCORE_IMX8MM
bool "PHYTEC PHYCORE i.MX8MM"
diff --git a/arch/arm/mach-imx/imx8m/soc.c b/arch/arm/mach-imx/imx8m/soc.c
index 39802d6..0c49fb9 100644
--- a/arch/arm/mach-imx/imx8m/soc.c
+++ b/arch/arm/mach-imx/imx8m/soc.c
@@ -933,19 +933,28 @@
{
static const char * const nodes_path_8mq[] = {
"/vpu@38300000",
- "/soc@0/vpu@38300000"
+ "/soc@0/vpu@38300000",
+ "/soc@0/video-codec@38300000",
+ "/soc@0/video-codec@38310000",
+ "/soc@0/blk-ctrl@38320000",
};
static const char * const nodes_path_8mm[] = {
"/vpu_g1@38300000",
"/vpu_g2@38310000",
- "/vpu_h1@38320000"
+ "/vpu_h1@38320000",
+ "/soc@0/video-codec@38300000",
+ "/soc@0/video-codec@38310000",
+ "/soc@0/blk-ctrl@38330000",
};
static const char * const nodes_path_8mp[] = {
"/vpu_g1@38300000",
"/vpu_g2@38310000",
- "/vpu_vc8000e@38320000"
+ "/vpu_vc8000e@38320000",
+ "/soc@0/video-codec@38300000",
+ "/soc@0/video-codec@38310000",
+ "/soc@0/blk-ctrl@38330000",
};
if (is_imx8mq())
@@ -1100,7 +1109,8 @@
int disable_npu_nodes(void *blob)
{
static const char * const nodes_path_8mp[] = {
- "/vipsi@38500000"
+ "/vipsi@38500000",
+ "/soc@0/npu@38500000",
};
return disable_fdt_nodes(blob, nodes_path_8mp, ARRAY_SIZE(nodes_path_8mp));
diff --git a/arch/arm/mach-imx/imx9/soc.c b/arch/arm/mach-imx/imx9/soc.c
index f06339f..2117489 100644
--- a/arch/arm/mach-imx/imx9/soc.c
+++ b/arch/arm/mach-imx/imx9/soc.c
@@ -262,7 +262,7 @@
/* Flexible Serial Peripheral Interface */
.virt = 0x28000000UL,
.phys = 0x28000000UL,
- .size = 0x30000000UL,
+ .size = 0x08000000UL,
.attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
PTE_BLOCK_NON_SHARE |
PTE_BLOCK_PXN | PTE_BLOCK_UXN
@@ -622,6 +622,7 @@
return 0;
}
EVENT_SPY_SIMPLE(EVT_DM_POST_INIT_F, imx9_probe_mu);
+EVENT_SPY_SIMPLE(EVT_DM_POST_INIT_R, imx9_probe_mu);
int timer_init(void)
{
diff --git a/arch/arm/mach-k3/r5/common.c b/arch/arm/mach-k3/r5/common.c
index 7309573..c02f8d3 100644
--- a/arch/arm/mach-k3/r5/common.c
+++ b/arch/arm/mach-k3/r5/common.c
@@ -70,7 +70,7 @@
char *name = NULL;
int size = 0;
- if (!IS_ENABLED(CONFIG_FS_LOADER))
+ if (!CONFIG_IS_ENABLED(FS_LOADER))
return 0;
*loadaddr = 0;
diff --git a/arch/arm/mach-kirkwood/Kconfig b/arch/arm/mach-kirkwood/Kconfig
index c2fff84..031d4e5 100644
--- a/arch/arm/mach-kirkwood/Kconfig
+++ b/arch/arm/mach-kirkwood/Kconfig
@@ -6,10 +6,12 @@
config KW88F6192
bool
select ARCH_VERY_EARLY_INIT
+ imply OF_UPSTREAM
config KW88F6281
bool
select ARCH_VERY_EARLY_INIT
+ imply OF_UPSTREAM
config SHEEVA_88SV131
bool
diff --git a/arch/arm/mach-meson/Kconfig b/arch/arm/mach-meson/Kconfig
index 95e7b01..7570f48 100644
--- a/arch/arm/mach-meson/Kconfig
+++ b/arch/arm/mach-meson/Kconfig
@@ -32,24 +32,28 @@
config MESON_GXL
bool "GXL"
select MESON_GX
+ imply OF_UPSTREAM
help
Select this if your SoC is an S905X/D or S805X
config MESON_GXM
bool "GXM"
select MESON_GX
+ imply OF_UPSTREAM
help
Select this if your SoC is an S912
config MESON_AXG
bool "AXG"
select MESON64_COMMON
+ imply OF_UPSTREAM
help
Select this if your SoC is an A113X/D
config MESON_G12A
bool "G12A"
select MESON64_COMMON
+ imply OF_UPSTREAM
help
Select this if your SoC is an S905X/D2
diff --git a/arch/arm/mach-mvebu/Kconfig b/arch/arm/mach-mvebu/Kconfig
index 2058c95..f15d3cc 100644
--- a/arch/arm/mach-mvebu/Kconfig
+++ b/arch/arm/mach-mvebu/Kconfig
@@ -18,6 +18,8 @@
select TOOLS_KWBIMAGE if SPL
select SPL_SYS_NO_VECTOR_TABLE if SPL
select ARCH_VERY_EARLY_INIT
+ select ARMADA_32BIT_SYSCON_RESET if DM_RESET && PCI_MVEBU
+ select ARMADA_32BIT_SYSCON_SYSRESET if SYSRESET
# ARMv7 SoCs...
config ARMADA_375
@@ -456,6 +458,29 @@
default 0x0
depends on MVEBU_SPL_BOOT_DEVICE_SPI
+config ARMADA_32BIT_SYSCON
+ bool
+ depends on ARMADA_32BIT
+ select REGMAP
+ select SYSCON
+
+config ARMADA_32BIT_SYSCON_RESET
+ bool "Support Armada XP/375/38x/39x reset controller"
+ depends on ARMADA_32BIT
+ depends on DM_RESET
+ select ARMADA_32BIT_SYSCON
+ help
+ Build support for Armada XP/375/38x/39x reset controller. This is
+ needed for PCIe support.
+
+config ARMADA_32BIT_SYSCON_SYSRESET
+ bool "Support Armada XP/375/38x/39x sysreset via driver model"
+ depends on ARMADA_32BIT
+ depends on SYSRESET
+ select ARMADA_32BIT_SYSCON
+ help
+ Build support for Armada XP/375/38x/39x system reset via driver model.
+
source "board/solidrun/clearfog/Kconfig"
source "board/kobol/helios4/Kconfig"
diff --git a/arch/arm/mach-mvebu/Makefile b/arch/arm/mach-mvebu/Makefile
index 0584ed2..329c2e4 100644
--- a/arch/arm/mach-mvebu/Makefile
+++ b/arch/arm/mach-mvebu/Makefile
@@ -22,13 +22,14 @@
obj-y = cpu.o
obj-y += dram.o
obj-y += lowlevel.o
-obj-$(CONFIG_DM_RESET) += system-controller.o
ifndef CONFIG_SPL_BUILD
obj-$(CONFIG_ARMADA_375) += ../../../drivers/ddr/marvell/axp/xor.o
obj-$(CONFIG_ARMADA_38X) += ../../../drivers/ddr/marvell/a38x/xor.o
obj-$(CONFIG_ARMADA_XP) += ../../../drivers/ddr/marvell/axp/xor.o
obj-$(CONFIG_ARMADA_MSYS) += ../../../drivers/ddr/marvell/axp/xor.o
+obj-$(CONFIG_ARMADA_32BIT_SYSCON) += system-controller.o
+
ifdef CONFIG_ARMADA_38X
obj-$(CONFIG_MVEBU_EFUSE) += efuse.o
endif
diff --git a/arch/arm/mach-mvebu/cpu.c b/arch/arm/mach-mvebu/cpu.c
index 8e0de93..7c62a5d 100644
--- a/arch/arm/mach-mvebu/cpu.c
+++ b/arch/arm/mach-mvebu/cpu.c
@@ -52,6 +52,7 @@
*/
}
+#if defined(CONFIG_SPL_BUILD) || !defined(CONFIG_ARMADA_32BIT_SYSCON_SYSRESET)
void reset_cpu(void)
{
struct mvebu_system_registers *reg =
@@ -62,6 +63,7 @@
while (1)
;
}
+#endif
u32 get_boot_device(void)
{
diff --git a/arch/arm/mach-mvebu/system-controller.c b/arch/arm/mach-mvebu/system-controller.c
index 7cdde11..682431e 100644
--- a/arch/arm/mach-mvebu/system-controller.c
+++ b/arch/arm/mach-mvebu/system-controller.c
@@ -1,18 +1,33 @@
// SPDX-License-Identifier: GPL-2.0+
-// (C) 2021 Pali Rohár <pali@kernel.org>
+/*
+ * Copyright (C) 2021 Pali Rohár <pali@kernel.org>
+ * Copyright (C) 2024 Marek Behún <kabel@kernel.org>
+ */
#include <common.h>
#include <dm.h>
+#include <dm/lists.h>
+#include <regmap.h>
#include <reset-uclass.h>
+#include <syscon.h>
+#include <sysreset.h>
#include <asm/io.h>
-#define MVEBU_SOC_CONTROL_1_REG 0x4
+#define MVEBU_SOC_CONTROL_1_REG 0x4
-#define MVEBU_PCIE_ID 0
+#if defined(CONFIG_ARMADA_375)
+# define MVEBU_RSTOUTN_MASK_REG 0x54
+# define MVEBU_SYS_SOFT_RST_REG 0x58
+#else
+# define MVEBU_RSTOUTN_MASK_REG 0x60
+# define MVEBU_SYS_SOFT_RST_REG 0x64
+#endif
-struct mvebu_reset_data {
- void *base;
-};
+#define MVEBU_GLOBAL_SOFT_RST_BIT BIT(0)
+
+#define MVEBU_PCIE_ID 0
+
+#if IS_ENABLED(CONFIG_ARMADA_32BIT_SYSCON_RESET)
static int mvebu_reset_of_xlate(struct reset_ctl *rst,
struct ofnode_phandle_args *args)
@@ -46,46 +61,33 @@
static int mvebu_reset_assert(struct reset_ctl *rst)
{
- struct mvebu_reset_data *data = dev_get_priv(rst->dev);
+ struct regmap *regmap = syscon_get_regmap(rst->dev->parent);
- clrbits_32(data->base + MVEBU_SOC_CONTROL_1_REG, BIT(rst->data));
- return 0;
+ return regmap_update_bits(regmap, MVEBU_SOC_CONTROL_1_REG,
+ BIT(rst->data), 0);
}
static int mvebu_reset_deassert(struct reset_ctl *rst)
{
- struct mvebu_reset_data *data = dev_get_priv(rst->dev);
+ struct regmap *regmap = syscon_get_regmap(rst->dev->parent);
- setbits_32(data->base + MVEBU_SOC_CONTROL_1_REG, BIT(rst->data));
- return 0;
+ return regmap_update_bits(regmap, MVEBU_SOC_CONTROL_1_REG,
+ BIT(rst->data), BIT(rst->data));
}
static int mvebu_reset_status(struct reset_ctl *rst)
{
- struct mvebu_reset_data *data = dev_get_priv(rst->dev);
+ struct regmap *regmap = syscon_get_regmap(rst->dev->parent);
+ uint val;
+ int ret;
- return !(readl(data->base + MVEBU_SOC_CONTROL_1_REG) & BIT(rst->data));
-}
+ ret = regmap_read(regmap, MVEBU_SOC_CONTROL_1_REG, &val);
+ if (ret < 0)
+ return ret;
-static int mvebu_reset_of_to_plat(struct udevice *dev)
-{
- struct mvebu_reset_data *data = dev_get_priv(dev);
-
- data->base = dev_read_addr_ptr(dev);
- if (!data->base)
- return -EINVAL;
-
- return 0;
+ return !(val & BIT(rst->data));
}
-static const struct udevice_id mvebu_reset_of_match[] = {
- { .compatible = "marvell,armada-370-xp-system-controller" },
- { .compatible = "marvell,armada-375-system-controller" },
- { .compatible = "marvell,armada-380-system-controller" },
- { .compatible = "marvell,armada-390-system-controller" },
- { },
-};
-
static const struct reset_ops mvebu_reset_ops = {
.of_xlate = mvebu_reset_of_xlate,
.request = mvebu_reset_request,
@@ -98,8 +100,81 @@
U_BOOT_DRIVER(mvebu_reset) = {
.name = "mvebu-reset",
.id = UCLASS_RESET,
- .of_match = mvebu_reset_of_match,
- .of_to_plat = mvebu_reset_of_to_plat,
- .priv_auto = sizeof(struct mvebu_reset_data),
.ops = &mvebu_reset_ops,
};
+
+#endif /* IS_ENABLED(CONFIG_ARMADA_32BIT_SYSCON_RESET) */
+
+#if IS_ENABLED(CONFIG_ARMADA_32BIT_SYSCON_SYSRESET)
+
+static int mvebu_sysreset_request(struct udevice *dev, enum sysreset_t type)
+{
+ struct regmap *regmap = syscon_get_regmap(dev->parent);
+ uint bit;
+
+ if (type != SYSRESET_COLD)
+ return -EPROTONOSUPPORT;
+
+ bit = MVEBU_GLOBAL_SOFT_RST_BIT;
+
+ regmap_update_bits(regmap, MVEBU_RSTOUTN_MASK_REG, bit, bit);
+ regmap_update_bits(regmap, MVEBU_SYS_SOFT_RST_REG, bit, bit);
+
+ /* Loop while waiting for the reset */
+ while (1)
+ ;
+
+ return 0;
+}
+
+static struct sysreset_ops mvebu_sysreset_ops = {
+ .request = mvebu_sysreset_request,
+};
+
+U_BOOT_DRIVER(mvebu_sysreset) = {
+ .name = "mvebu-sysreset",
+ .id = UCLASS_SYSRESET,
+ .ops = &mvebu_sysreset_ops,
+};
+
+#endif /* IS_ENABLED(CONFIG_ARMADA_32BIT_SYSCON_SYSRESET) */
+
+static int mvebu_syscon_bind(struct udevice *dev)
+{
+ int ret = 0;
+
+ /* bind also mvebu-reset, with the same ofnode */
+ if (IS_ENABLED(CONFIG_ARMADA_32BIT_SYSCON_RESET)) {
+ ret = device_bind_driver_to_node(dev, "mvebu-reset",
+ "mvebu-reset", dev_ofnode(dev),
+ NULL);
+ if (ret < 0)
+ return ret;
+ }
+
+ /* bind also mvebu-sysreset, with the same ofnode */
+ if (IS_ENABLED(CONFIG_ARMADA_32BIT_SYSCON_SYSRESET)) {
+ ret = device_bind_driver_to_node(dev, "mvebu-sysreset",
+ "mvebu-sysreset",
+ dev_ofnode(dev), NULL);
+ if (ret < 0)
+ return ret;
+ }
+
+ return ret;
+}
+
+static const struct udevice_id mvebu_syscon_of_match[] = {
+ { .compatible = "marvell,armada-370-xp-system-controller" },
+ { .compatible = "marvell,armada-375-system-controller" },
+ { .compatible = "marvell,armada-380-system-controller" },
+ { .compatible = "marvell,armada-390-system-controller" },
+ { },
+};
+
+U_BOOT_DRIVER(mvebu_syscon) = {
+ .name = "mvebu-system-controller",
+ .id = UCLASS_SYSCON,
+ .of_match = mvebu_syscon_of_match,
+ .bind = mvebu_syscon_bind,
+};
diff --git a/arch/arm/mach-omap2/boot-common.c b/arch/arm/mach-omap2/boot-common.c
index 57917da..aa0ab13 100644
--- a/arch/arm/mach-omap2/boot-common.c
+++ b/arch/arm/mach-omap2/boot-common.c
@@ -190,7 +190,7 @@
struct udevice *fsdev;
int size = 0;
- if (!IS_ENABLED(CONFIG_FS_LOADER))
+ if (!CONFIG_IS_ENABLED(FS_LOADER))
return 0;
if (!*loadaddr)
diff --git a/arch/arm/mach-rockchip/Kconfig b/arch/arm/mach-rockchip/Kconfig
index 1bc7ee9..f68a0a4 100644
--- a/arch/arm/mach-rockchip/Kconfig
+++ b/arch/arm/mach-rockchip/Kconfig
@@ -189,6 +189,9 @@
select ENABLE_ARM_SOC_BOOT0_HOOK
select DEBUG_UART_BOARD_INIT
select SYS_NS16550
+ imply MISC
+ imply ROCKCHIP_EFUSE
+ imply MISC_INIT_R
help
The Rockchip RK3328 is a ARM-based SoC with a quad-core Cortex-A53.
including NEON and GPU, 1MB L2 cache, Mali-T7 graphics, two
@@ -267,6 +270,9 @@
imply SYS_BOOTCOUNT_SINGLEWORD if BOOTCOUNT_LIMIT
imply BOOTSTD_FULL
imply CMD_BOOTCOUNT if BOOTCOUNT_LIMIT
+ imply MISC
+ imply ROCKCHIP_EFUSE
+ imply MISC_INIT_R
help
The Rockchip RK3399 is a ARM-based SoC with a dual-core Cortex-A72
and quad-core Cortex-A53.
@@ -501,6 +507,30 @@
This enables support code in the BOOT0 hook for the SPL stage
to allow multiple entries.
+config ROCKCHIP_DISABLE_FORCE_JTAG
+ bool "Disable force_jtag feature"
+ default y
+ depends on SPL
+ help
+ Rockchip SoCs can automatically switch between jtag and sdmmc based
+ on the following rules:
+ - all the SDMMC pins including SDMMC_DET set as SDMMC function in
+ GRF,
+ - force_jtag bit in GRF is 1,
+ - SDMMC_DET is low (no card detected),
+
+ Some HW design may not route the SD card card detect to SDMMC_DET
+ pin, thus breaking the SD card support in some cases because JTAG
+ would be auto-enabled by mistake.
+
+ Also, enabling JTAG at runtime may be an undesired feature, e.g.
+ because it could be a security vulnerability.
+
+ This disables force_jtag feature, which you may want for debugging
+ purposes.
+
+ If unsure, say Y.
+
config TPL_ROCKCHIP_EARLYRETURN_TO_BROM
bool "TPL requires early-return (for RK3188-style BROM) to BROM"
depends on TPL && ENABLE_ARM_SOC_BOOT0_HOOK
@@ -528,6 +558,21 @@
config LNX_KRNL_IMG_TEXT_OFFSET_BASE
default TEXT_BASE
+config ROCKCHIP_COMMON_STACK_ADDR
+ bool
+ depends on SPL_SHARES_INIT_SP_ADDR
+ select HAS_CUSTOM_SYS_INIT_SP_ADDR
+ imply SPL_LIBCOMMON_SUPPORT if SPL
+ imply SPL_LIBGENERIC_SUPPORT if SPL
+ imply SPL_ROCKCHIP_COMMON_BOARD if SPL
+ imply SPL_SYS_MALLOC_F if SPL
+ imply SPL_SYS_MALLOC_SIMPLE if SPL
+ imply TPL_LIBCOMMON_SUPPORT if TPL
+ imply TPL_LIBGENERIC_SUPPORT if TPL
+ imply TPL_ROCKCHIP_COMMON_BOARD if TPL
+ imply TPL_SYS_MALLOC_F if TPL
+ imply TPL_SYS_MALLOC_SIMPLE if TPL
+
source "arch/arm/mach-rockchip/px30/Kconfig"
source "arch/arm/mach-rockchip/rk3036/Kconfig"
source "arch/arm/mach-rockchip/rk3066/Kconfig"
@@ -543,4 +588,44 @@
source "arch/arm/mach-rockchip/rk3588/Kconfig"
source "arch/arm/mach-rockchip/rv1108/Kconfig"
source "arch/arm/mach-rockchip/rv1126/Kconfig"
+
+if ROCKCHIP_COMMON_STACK_ADDR && SPL_SHARES_INIT_SP_ADDR
+
+config CUSTOM_SYS_INIT_SP_ADDR
+ default 0x3f00000
+
+config SYS_MALLOC_F_LEN
+ default 0x10000 if CUSTOM_SYS_INIT_SP_ADDR = 0x3f00000
+
+config SPL_SYS_MALLOC_F_LEN
+ default 0x8000 if CUSTOM_SYS_INIT_SP_ADDR = 0x3f00000
+
+config TPL_SYS_MALLOC_F_LEN
+ default 0x4000 if CUSTOM_SYS_INIT_SP_ADDR = 0x3f00000
+
+config TEXT_BASE
+ default 0x00200000 if ARM64
+
+config SPL_TEXT_BASE
+ default 0x0 if ARM64
+
+config SPL_HAS_BSS_LINKER_SECTION
+ default y if ARM64
+
+config SPL_BSS_START_ADDR
+ default 0x3f80000
+
+config SPL_BSS_MAX_SIZE
+ default 0x8000 if SPL_BSS_START_ADDR = 0x3f80000
+
+config SPL_STACK_R
+ default y if CUSTOM_SYS_INIT_SP_ADDR = 0x3f00000
+
+config SPL_STACK_R_ADDR
+ default 0x3e00000 if CUSTOM_SYS_INIT_SP_ADDR = 0x3f00000
+
+config SPL_STACK_R_MALLOC_SIMPLE_LEN
+ default 0x200000 if SPL_STACK_R_ADDR = 0x3e00000
+
+endif
endif
diff --git a/arch/arm/mach-rockchip/Makefile b/arch/arm/mach-rockchip/Makefile
index 1dc9206..c07bdae 100644
--- a/arch/arm/mach-rockchip/Makefile
+++ b/arch/arm/mach-rockchip/Makefile
@@ -23,7 +23,6 @@
# meaning "turn it off".
obj-y += boot_mode.o
obj-$(CONFIG_ROCKCHIP_COMMON_BOARD) += board.o
-obj-$(CONFIG_MISC_INIT_R) += misc.o
endif
ifeq ($(CONFIG_TPL_BUILD),)
diff --git a/arch/arm/mach-rockchip/board.c b/arch/arm/mach-rockchip/board.c
index 2620530..cd22684 100644
--- a/arch/arm/mach-rockchip/board.c
+++ b/arch/arm/mach-rockchip/board.c
@@ -1,29 +1,41 @@
// SPDX-License-Identifier: GPL-2.0+
/*
* (C) Copyright 2019 Rockchip Electronics Co., Ltd.
+ *
+ * Copyright (C) 2019 Collabora Inc - https://www.collabora.com/
+ * Rohan Garg <rohan.garg@collabora.com>
+ *
+ * Based on puma-rk3399.c:
+ * (C) Copyright 2017 Theobroma Systems Design und Consulting GmbH
*/
#include <common.h>
#include <clk.h>
#include <cpu_func.h>
+#include <env.h>
#include <dm.h>
+#include <dm/uclass-internal.h>
#include <efi_loader.h>
#include <fastboot.h>
+#include <hash.h>
#include <init.h>
#include <log.h>
#include <mmc.h>
+#include <dm/uclass-internal.h>
+#include <misc.h>
#include <part.h>
#include <ram.h>
#include <syscon.h>
#include <uuid.h>
+#include <u-boot/crc.h>
+#include <u-boot/sha256.h>
#include <asm/cache.h>
#include <asm/io.h>
#include <asm/arch-rockchip/boot_mode.h>
#include <asm/arch-rockchip/clock.h>
#include <asm/arch-rockchip/periph.h>
-#include <asm/arch-rockchip/misc.h>
#include <power/regulator.h>
-#if defined(CONFIG_EFI_HAVE_CAPSULE_SUPPORT) && defined(CONFIG_EFI_PARTITION)
+#if IS_ENABLED(CONFIG_EFI_HAVE_CAPSULE_SUPPORT) && IS_ENABLED(CONFIG_EFI_PARTITION)
#define DFU_ALT_BUF_LEN SZ_1K
@@ -136,6 +148,10 @@
env_set("dfu_alt_info", buf);
}
+__weak void rockchip_capsule_update_board_setup(void)
+{
+}
+
static void gpt_capsule_update_setup(void)
{
int p, i, ret;
@@ -170,10 +186,6 @@
__weak int rk_board_late_init(void)
{
-#if defined(CONFIG_EFI_HAVE_CAPSULE_SUPPORT) && defined(CONFIG_EFI_PARTITION)
- gpt_capsule_update_setup();
-#endif
-
return 0;
}
@@ -181,6 +193,10 @@
{
setup_boot_mode();
+#if IS_ENABLED(CONFIG_EFI_HAVE_CAPSULE_SUPPORT) && IS_ENABLED(CONFIG_EFI_PARTITION)
+ gpt_capsule_update_setup();
+#endif
+
return rk_board_late_init();
}
@@ -205,8 +221,24 @@
}
#endif
-#if defined(CONFIG_USB_GADGET) && defined(CONFIG_USB_GADGET_DWC2_OTG)
+#if IS_ENABLED(CONFIG_USB_GADGET)
#include <usb.h>
+
+#if IS_ENABLED(CONFIG_USB_GADGET_DOWNLOAD)
+#define ROCKCHIP_G_DNL_UMS_PRODUCT_NUM 0x0010
+
+int g_dnl_bind_fixup(struct usb_device_descriptor *dev, const char *name)
+{
+ if (!strcmp(name, "usb_dnl_ums"))
+ put_unaligned(ROCKCHIP_G_DNL_UMS_PRODUCT_NUM, &dev->idProduct);
+ else
+ put_unaligned(CONFIG_USB_GADGET_PRODUCT_NUM, &dev->idProduct);
+
+ return 0;
+}
+#endif /* CONFIG_USB_GADGET_DOWNLOAD */
+
+#if IS_ENABLED(CONFIG_USB_GADGET_DWC2_OTG) && !IS_ENABLED(CONFIG_DM_USB_GADGET)
#include <linux/usb/otg.h>
#include <usb/dwc2_udc.h>
@@ -281,6 +313,7 @@
return 0;
}
#endif /* CONFIG_USB_GADGET_DWC2_OTG */
+#endif /* CONFIG_USB_GADGET */
#if IS_ENABLED(CONFIG_FASTBOOT)
int fastboot_set_reboot_flag(enum fastboot_reboot_reason reason)
@@ -297,6 +330,124 @@
#endif
#ifdef CONFIG_MISC_INIT_R
+int rockchip_setup_macaddr(void)
+{
+#if CONFIG_IS_ENABLED(HASH) && CONFIG_IS_ENABLED(SHA256)
+ int ret;
+ const char *cpuid = env_get("cpuid#");
+ u8 hash[SHA256_SUM_LEN];
+ int size = sizeof(hash);
+ u8 mac_addr[6];
+
+ /* Only generate a MAC address, if none is set in the environment */
+ if (env_get("ethaddr"))
+ return 0;
+
+ if (!cpuid) {
+ debug("%s: could not retrieve 'cpuid#'\n", __func__);
+ return -1;
+ }
+
+ ret = hash_block("sha256", (void *)cpuid, strlen(cpuid), hash, &size);
+ if (ret) {
+ debug("%s: failed to calculate SHA256\n", __func__);
+ return -1;
+ }
+
+ /* Copy 6 bytes of the hash to base the MAC address on */
+ memcpy(mac_addr, hash, 6);
+
+ /* Make this a valid MAC address and set it */
+ mac_addr[0] &= 0xfe; /* clear multicast bit */
+ mac_addr[0] |= 0x02; /* set local assignment bit (IEEE802) */
+ eth_env_set_enetaddr("ethaddr", mac_addr);
+
+ /* Make a valid MAC address for ethernet1 */
+ mac_addr[5] ^= 0x01;
+ eth_env_set_enetaddr("eth1addr", mac_addr);
+#endif
+ return 0;
+}
+
+int rockchip_cpuid_from_efuse(const u32 cpuid_offset,
+ const u32 cpuid_length,
+ u8 *cpuid)
+{
+#if IS_ENABLED(CONFIG_ROCKCHIP_EFUSE) || IS_ENABLED(CONFIG_ROCKCHIP_OTP)
+ struct udevice *dev;
+ int ret;
+
+ /* retrieve the device */
+#if IS_ENABLED(CONFIG_ROCKCHIP_EFUSE)
+ ret = uclass_get_device_by_driver(UCLASS_MISC,
+ DM_DRIVER_GET(rockchip_efuse), &dev);
+#elif IS_ENABLED(CONFIG_ROCKCHIP_OTP)
+ ret = uclass_get_device_by_driver(UCLASS_MISC,
+ DM_DRIVER_GET(rockchip_otp), &dev);
+#endif
+ if (ret) {
+ debug("%s: could not find efuse device\n", __func__);
+ return -1;
+ }
+
+ /* read the cpu_id range from the efuses */
+ ret = misc_read(dev, cpuid_offset, cpuid, cpuid_length);
+ if (ret < 0) {
+ debug("%s: reading cpuid from the efuses failed\n",
+ __func__);
+ return -1;
+ }
+#endif
+ return 0;
+}
+
+int rockchip_cpuid_set(const u8 *cpuid, const u32 cpuid_length)
+{
+ u8 low[cpuid_length / 2], high[cpuid_length / 2];
+ char cpuid_str[cpuid_length * 2 + 1];
+ u64 serialno;
+ char serialno_str[17];
+ const char *oldid;
+ int i;
+
+ memset(cpuid_str, 0, sizeof(cpuid_str));
+ for (i = 0; i < cpuid_length; i++)
+ sprintf(&cpuid_str[i * 2], "%02x", cpuid[i]);
+
+ debug("cpuid: %s\n", cpuid_str);
+
+ /*
+ * Mix the cpuid bytes using the same rules as in
+ * ${linux}/drivers/soc/rockchip/rockchip-cpuinfo.c
+ */
+ for (i = 0; i < cpuid_length / 2; i++) {
+ low[i] = cpuid[1 + (i << 1)];
+ high[i] = cpuid[i << 1];
+ }
+
+ serialno = crc32_no_comp(0, low, cpuid_length / 2);
+ serialno |= (u64)crc32_no_comp(serialno, high, cpuid_length / 2) << 32;
+ snprintf(serialno_str, sizeof(serialno_str), "%016llx", serialno);
+
+ oldid = env_get("cpuid#");
+ if (oldid && strcmp(oldid, cpuid_str) != 0)
+ printf("cpuid: value %s present in env does not match hardware %s\n",
+ oldid, cpuid_str);
+
+ env_set("cpuid#", cpuid_str);
+
+ /* Only generate serial# when none is set yet */
+ if (!env_get("serial#"))
+ env_set("serial#", serialno_str);
+
+ return 0;
+}
+
+__weak int rockchip_early_misc_init_r(void)
+{
+ return 0;
+}
+
__weak int misc_init_r(void)
{
const u32 cpuid_offset = CFG_CPUID_OFFSET;
@@ -304,6 +455,10 @@
u8 cpuid[cpuid_length];
int ret;
+ ret = rockchip_early_misc_init_r();
+ if (ret)
+ return ret;
+
ret = rockchip_cpuid_from_efuse(cpuid_offset, cpuid_length, cpuid);
if (ret)
return ret;
@@ -349,3 +504,33 @@
return 0;
}
#endif
+
+int mmc_get_env_dev(void)
+{
+ int devnum;
+ const char *boot_device;
+ struct udevice *dev;
+
+#ifdef CONFIG_SYS_MMC_ENV_DEV
+ devnum = CONFIG_SYS_MMC_ENV_DEV;
+#else
+ devnum = 0;
+#endif
+
+ boot_device = ofnode_read_chosen_string("u-boot,spl-boot-device");
+ if (!boot_device) {
+ debug("%s: /chosen/u-boot,spl-boot-device not set\n", __func__);
+ return devnum;
+ }
+
+ debug("%s: booted from %s\n", __func__, boot_device);
+
+ if (uclass_find_device_by_ofnode(UCLASS_MMC, ofnode_path(boot_device), &dev)) {
+ debug("%s: no U-Boot device found for %s\n", __func__, boot_device);
+ return devnum;
+ }
+
+ devnum = dev->seq_;
+ debug("%s: get MMC env from mmc%d\n", __func__, devnum);
+ return devnum;
+}
diff --git a/arch/arm/mach-rockchip/boot_mode.c b/arch/arm/mach-rockchip/boot_mode.c
index eb8f65a..f9be396 100644
--- a/arch/arm/mach-rockchip/boot_mode.c
+++ b/arch/arm/mach-rockchip/boot_mode.c
@@ -40,6 +40,7 @@
__weak int rockchip_dnl_key_pressed(void)
{
+#if CONFIG_IS_ENABLED(ADC)
unsigned int val;
struct udevice *dev;
struct uclass *uc;
@@ -69,6 +70,9 @@
return true;
else
return false;
+#else
+ return false;
+#endif
}
void rockchip_dnl_mode_check(void)
diff --git a/arch/arm/mach-rockchip/cpu-info.c b/arch/arm/mach-rockchip/cpu-info.c
index dac2491..a62ff53 100644
--- a/arch/arm/mach-rockchip/cpu-info.c
+++ b/arch/arm/mach-rockchip/cpu-info.c
@@ -7,7 +7,6 @@
#include <common.h>
#include <env.h>
#include <init.h>
-#include <asm/io.h>
#include <asm/arch-rockchip/clock.h>
#include <asm/arch-rockchip/cru.h>
#include <asm/arch-rockchip/hardware.h>
diff --git a/arch/arm/mach-rockchip/misc.c b/arch/arm/mach-rockchip/misc.c
deleted file mode 100644
index 7d03f0c..0000000
--- a/arch/arm/mach-rockchip/misc.c
+++ /dev/null
@@ -1,135 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0+ */
-/*
- * RK3399: Architecture common definitions
- *
- * Copyright (C) 2019 Collabora Inc - https://www.collabora.com/
- * Rohan Garg <rohan.garg@collabora.com>
- *
- * Based on puma-rk3399.c:
- * (C) Copyright 2017 Theobroma Systems Design und Consulting GmbH
- */
-
-#include <common.h>
-#include <env.h>
-#include <dm.h>
-#include <hash.h>
-#include <log.h>
-#include <dm/uclass-internal.h>
-#include <misc.h>
-#include <u-boot/crc.h>
-#include <u-boot/sha256.h>
-
-#include <asm/arch-rockchip/misc.h>
-
-int rockchip_setup_macaddr(void)
-{
-#if CONFIG_IS_ENABLED(HASH) && CONFIG_IS_ENABLED(SHA256)
- int ret;
- const char *cpuid = env_get("cpuid#");
- u8 hash[SHA256_SUM_LEN];
- int size = sizeof(hash);
- u8 mac_addr[6];
-
- /* Only generate a MAC address, if none is set in the environment */
- if (env_get("ethaddr"))
- return 0;
-
- if (!cpuid) {
- debug("%s: could not retrieve 'cpuid#'\n", __func__);
- return -1;
- }
-
- ret = hash_block("sha256", (void *)cpuid, strlen(cpuid), hash, &size);
- if (ret) {
- debug("%s: failed to calculate SHA256\n", __func__);
- return -1;
- }
-
- /* Copy 6 bytes of the hash to base the MAC address on */
- memcpy(mac_addr, hash, 6);
-
- /* Make this a valid MAC address and set it */
- mac_addr[0] &= 0xfe; /* clear multicast bit */
- mac_addr[0] |= 0x02; /* set local assignment bit (IEEE802) */
- eth_env_set_enetaddr("ethaddr", mac_addr);
-
- /* Make a valid MAC address for ethernet1 */
- mac_addr[5] ^= 0x01;
- eth_env_set_enetaddr("eth1addr", mac_addr);
-#endif
- return 0;
-}
-
-int rockchip_cpuid_from_efuse(const u32 cpuid_offset,
- const u32 cpuid_length,
- u8 *cpuid)
-{
-#if IS_ENABLED(CONFIG_ROCKCHIP_EFUSE) || IS_ENABLED(CONFIG_ROCKCHIP_OTP)
- struct udevice *dev;
- int ret;
-
- /* retrieve the device */
-#if IS_ENABLED(CONFIG_ROCKCHIP_EFUSE)
- ret = uclass_get_device_by_driver(UCLASS_MISC,
- DM_DRIVER_GET(rockchip_efuse), &dev);
-#elif IS_ENABLED(CONFIG_ROCKCHIP_OTP)
- ret = uclass_get_device_by_driver(UCLASS_MISC,
- DM_DRIVER_GET(rockchip_otp), &dev);
-#endif
- if (ret) {
- debug("%s: could not find efuse device\n", __func__);
- return -1;
- }
-
- /* read the cpu_id range from the efuses */
- ret = misc_read(dev, cpuid_offset, cpuid, cpuid_length);
- if (ret < 0) {
- debug("%s: reading cpuid from the efuses failed\n",
- __func__);
- return -1;
- }
-#endif
- return 0;
-}
-
-int rockchip_cpuid_set(const u8 *cpuid, const u32 cpuid_length)
-{
- u8 low[cpuid_length / 2], high[cpuid_length / 2];
- char cpuid_str[cpuid_length * 2 + 1];
- u64 serialno;
- char serialno_str[17];
- const char *oldid;
- int i;
-
- memset(cpuid_str, 0, sizeof(cpuid_str));
- for (i = 0; i < 16; i++)
- sprintf(&cpuid_str[i * 2], "%02x", cpuid[i]);
-
- debug("cpuid: %s\n", cpuid_str);
-
- /*
- * Mix the cpuid bytes using the same rules as in
- * ${linux}/drivers/soc/rockchip/rockchip-cpuinfo.c
- */
- for (i = 0; i < 8; i++) {
- low[i] = cpuid[1 + (i << 1)];
- high[i] = cpuid[i << 1];
- }
-
- serialno = crc32_no_comp(0, low, 8);
- serialno |= (u64)crc32_no_comp(serialno, high, 8) << 32;
- snprintf(serialno_str, sizeof(serialno_str), "%016llx", serialno);
-
- oldid = env_get("cpuid#");
- if (oldid && strcmp(oldid, cpuid_str) != 0)
- printf("cpuid: value %s present in env does not match hardware %s\n",
- oldid, cpuid_str);
-
- env_set("cpuid#", cpuid_str);
-
- /* Only generate serial# when none is set yet */
- if (!env_get("serial#"))
- env_set("serial#", serialno_str);
-
- return 0;
-}
diff --git a/arch/arm/mach-rockchip/px30/px30.c b/arch/arm/mach-rockchip/px30/px30.c
index fc7456e..b4f655f 100644
--- a/arch/arm/mach-rockchip/px30/px30.c
+++ b/arch/arm/mach-rockchip/px30/px30.c
@@ -9,7 +9,6 @@
#include <init.h>
#include <spl.h>
#include <asm/armv8/mmu.h>
-#include <asm/io.h>
#include <asm/arch-rockchip/bootrom.h>
#include <asm/arch-rockchip/grf_px30.h>
#include <asm/arch-rockchip/hardware.h>
diff --git a/arch/arm/mach-rockchip/rk3036/rk3036.c b/arch/arm/mach-rockchip/rk3036/rk3036.c
index 0a072cf..e8130ab 100644
--- a/arch/arm/mach-rockchip/rk3036/rk3036.c
+++ b/arch/arm/mach-rockchip/rk3036/rk3036.c
@@ -6,7 +6,6 @@
#include <common.h>
#include <init.h>
#include <asm/global_data.h>
-#include <asm/io.h>
#include <asm/arch-rockchip/grf_rk3036.h>
#include <asm/arch-rockchip/hardware.h>
#include <asm/arch-rockchip/sdram_rk3036.h>
diff --git a/arch/arm/mach-rockchip/rk3036/sdram_rk3036.c b/arch/arm/mach-rockchip/rk3036/sdram_rk3036.c
index fcae65b..07cd29a 100644
--- a/arch/arm/mach-rockchip/rk3036/sdram_rk3036.c
+++ b/arch/arm/mach-rockchip/rk3036/sdram_rk3036.c
@@ -4,7 +4,6 @@
*/
#include <common.h>
#include <init.h>
-#include <asm/io.h>
#include <asm/types.h>
#include <asm/arch-rockchip/cru_rk3036.h>
#include <asm/arch-rockchip/grf_rk3036.h>
diff --git a/arch/arm/mach-rockchip/rk3066/rk3066.c b/arch/arm/mach-rockchip/rk3066/rk3066.c
index 78c7d89..9a95ff8 100644
--- a/arch/arm/mach-rockchip/rk3066/rk3066.c
+++ b/arch/arm/mach-rockchip/rk3066/rk3066.c
@@ -4,9 +4,9 @@
*/
#include <common.h>
-#include <asm/io.h>
#include <asm/arch-rockchip/bootrom.h>
#include <asm/arch-rockchip/grf_rk3066.h>
+#include <asm/arch-rockchip/hardware.h>
#define GRF_BASE 0x20008000
diff --git a/arch/arm/mach-rockchip/rk3188/rk3188.c b/arch/arm/mach-rockchip/rk3188/rk3188.c
index c807221..ffdcaa4 100644
--- a/arch/arm/mach-rockchip/rk3188/rk3188.c
+++ b/arch/arm/mach-rockchip/rk3188/rk3188.c
@@ -10,7 +10,6 @@
#include <log.h>
#include <syscon.h>
#include <asm/global_data.h>
-#include <asm/io.h>
#include <asm/arch-rockchip/bootrom.h>
#include <asm/arch-rockchip/clock.h>
#include <asm/arch-rockchip/grf_rk3188.h>
diff --git a/arch/arm/mach-rockchip/rk322x/rk322x.c b/arch/arm/mach-rockchip/rk322x/rk322x.c
index a304795..712c052 100644
--- a/arch/arm/mach-rockchip/rk322x/rk322x.c
+++ b/arch/arm/mach-rockchip/rk322x/rk322x.c
@@ -3,7 +3,6 @@
* (C) Copyright 2019 Rockchip Electronics Co., Ltd
*/
#include <init.h>
-#include <asm/io.h>
#include <asm/arch-rockchip/bootrom.h>
#include <asm/arch-rockchip/grf_rk322x.h>
#include <asm/arch-rockchip/hardware.h>
diff --git a/arch/arm/mach-rockchip/rk3288/rk3288.c b/arch/arm/mach-rockchip/rk3288/rk3288.c
index d9f782e..c77c56c 100644
--- a/arch/arm/mach-rockchip/rk3288/rk3288.c
+++ b/arch/arm/mach-rockchip/rk3288/rk3288.c
@@ -11,7 +11,6 @@
#include <malloc.h>
#include <asm/armv7.h>
#include <asm/global_data.h>
-#include <asm/io.h>
#include <asm/arch-rockchip/bootrom.h>
#include <asm/arch-rockchip/clock.h>
#include <asm/arch-rockchip/cpu_rk3288.h>
diff --git a/arch/arm/mach-rockchip/rk3308/Kconfig b/arch/arm/mach-rockchip/rk3308/Kconfig
index 194353e..749e999 100644
--- a/arch/arm/mach-rockchip/rk3308/Kconfig
+++ b/arch/arm/mach-rockchip/rk3308/Kconfig
@@ -17,8 +17,11 @@
config SYS_SOC
default "rk3308"
-config SYS_MALLOC_F_LEN
- default 0x400
+config ROCKCHIP_COMMON_STACK_ADDR
+ default y
+
+config TEXT_BASE
+ default 0x00600000
config SPL_SERIAL
default y
diff --git a/arch/arm/mach-rockchip/rk3308/rk3308.c b/arch/arm/mach-rockchip/rk3308/rk3308.c
index 6f121bf..27a7483 100644
--- a/arch/arm/mach-rockchip/rk3308/rk3308.c
+++ b/arch/arm/mach-rockchip/rk3308/rk3308.c
@@ -5,7 +5,6 @@
#include <common.h>
#include <init.h>
#include <malloc.h>
-#include <asm/io.h>
#include <asm/arch/grf_rk3308.h>
#include <asm/arch-rockchip/bootrom.h>
#include <asm/arch-rockchip/hardware.h>
diff --git a/arch/arm/mach-rockchip/rk3328/Kconfig b/arch/arm/mach-rockchip/rk3328/Kconfig
index d5cb649..70770da 100644
--- a/arch/arm/mach-rockchip/rk3328/Kconfig
+++ b/arch/arm/mach-rockchip/rk3328/Kconfig
@@ -21,13 +21,7 @@
config SYS_SOC
default "rk3328"
-config SYS_MALLOC_F_LEN
- default 0x2000
-
-config SPL_LIBCOMMON_SUPPORT
- default y
-
-config SPL_LIBGENERIC_SUPPORT
+config ROCKCHIP_COMMON_STACK_ADDR
default y
config TPL_LDSCRIPT
@@ -39,6 +33,9 @@
config TPL_STACK
default 0xff098000
+config TPL_SYS_MALLOC_F_LEN
+ default 0x800
+
source "board/rockchip/evb_rk3328/Kconfig"
endif
diff --git a/arch/arm/mach-rockchip/rk3328/rk3328.c b/arch/arm/mach-rockchip/rk3328/rk3328.c
index b591d38..ca3fa81 100644
--- a/arch/arm/mach-rockchip/rk3328/rk3328.c
+++ b/arch/arm/mach-rockchip/rk3328/rk3328.c
@@ -10,7 +10,6 @@
#include <asm/arch-rockchip/grf_rk3328.h>
#include <asm/arch-rockchip/uart.h>
#include <asm/armv8/mmu.h>
-#include <asm/io.h>
#define CRU_BASE 0xFF440000
#define GRF_BASE 0xFF100000
@@ -36,6 +35,7 @@
const char * const boot_devices[BROM_LAST_BOOTSOURCE + 1] = {
[BROM_BOOTSOURCE_EMMC] = "/mmc@ff520000",
+ [BROM_BOOTSOURCE_SPINOR] = "/spi@ff190000/flash@0",
[BROM_BOOTSOURCE_SD] = "/mmc@ff500000",
};
diff --git a/arch/arm/mach-rockchip/rk3368/rk3368.c b/arch/arm/mach-rockchip/rk3368/rk3368.c
index d009b87..651ba10 100644
--- a/arch/arm/mach-rockchip/rk3368/rk3368.c
+++ b/arch/arm/mach-rockchip/rk3368/rk3368.c
@@ -8,7 +8,6 @@
#include <init.h>
#include <syscon.h>
#include <asm/armv8/mmu.h>
-#include <asm/io.h>
#include <asm/arch-rockchip/bootrom.h>
#include <asm/arch-rockchip/clock.h>
#include <asm/arch-rockchip/cru_rk3368.h>
diff --git a/arch/arm/mach-rockchip/rk3399/Kconfig b/arch/arm/mach-rockchip/rk3399/Kconfig
index d01063a..04a84e2 100644
--- a/arch/arm/mach-rockchip/rk3399/Kconfig
+++ b/arch/arm/mach-rockchip/rk3399/Kconfig
@@ -89,6 +89,11 @@
* 2x USB 3.0 type A, 2x USB 2.0 type A (host mode only),
1x USB 3.0 type C OTG
+config TARGET_ROCKPI4_RK3399
+ bool "Radxa ROCK Pi 4 board"
+ help
+ Support for ROCK Pi 4 board family by Radxa.
+
config TARGET_ROCKPRO64_RK3399
bool "Pine64 Rockpro64 board"
help
@@ -138,8 +143,11 @@
config SYS_SOC
default "rk3399"
+config ROCKCHIP_COMMON_STACK_ADDR
+ default y
+
config SYS_MALLOC_F_LEN
- default 0x4000
+ default 0x4000 if !SPL_SHARES_INIT_SP_ADDR
config SPL_LIBCOMMON_SUPPORT
default y
@@ -157,7 +165,7 @@
default 0xff8c2000
config SPL_STACK_R_ADDR
- default 0x04000000
+ default 0x04000000 if !SPL_SHARES_INIT_SP_ADDR
if BOOTCOUNT_LIMIT
@@ -174,6 +182,7 @@
source "board/pine64/pinebook-pro-rk3399/Kconfig"
source "board/pine64/pinephone-pro-rk3399/Kconfig"
source "board/pine64/rockpro64_rk3399/Kconfig"
+source "board/radxa/rockpi4-rk3399/Kconfig"
source "board/rockchip/evb_rk3399/Kconfig"
source "board/theobroma-systems/puma_rk3399/Kconfig"
source "board/vamrs/rock960_rk3399/Kconfig"
diff --git a/arch/arm/mach-rockchip/rk3399/rk3399.c b/arch/arm/mach-rockchip/rk3399/rk3399.c
index a1aa0e3..7fa1d7c 100644
--- a/arch/arm/mach-rockchip/rk3399/rk3399.c
+++ b/arch/arm/mach-rockchip/rk3399/rk3399.c
@@ -11,7 +11,6 @@
#include <spl_gpio.h>
#include <syscon.h>
#include <asm/armv8/mmu.h>
-#include <asm/io.h>
#include <asm/arch-rockchip/bootrom.h>
#include <asm/arch-rockchip/clock.h>
#include <asm/arch-rockchip/cru.h>
diff --git a/arch/arm/mach-rockchip/rk3568/Kconfig b/arch/arm/mach-rockchip/rk3568/Kconfig
index baa5134..af537d9 100644
--- a/arch/arm/mach-rockchip/rk3568/Kconfig
+++ b/arch/arm/mach-rockchip/rk3568/Kconfig
@@ -38,8 +38,11 @@
config SYS_SOC
default "rk3568"
-config SYS_MALLOC_F_LEN
- default 0x20000
+config ROCKCHIP_COMMON_STACK_ADDR
+ default y
+
+config TEXT_BASE
+ default 0x00a00000
source "board/rockchip/evb_rk3568/Kconfig"
source "board/anbernic/rgxx3_rk3566/Kconfig"
diff --git a/arch/arm/mach-rockchip/rk3568/rk3568.c b/arch/arm/mach-rockchip/rk3568/rk3568.c
index 69ef19c..b30ea04 100644
--- a/arch/arm/mach-rockchip/rk3568/rk3568.c
+++ b/arch/arm/mach-rockchip/rk3568/rk3568.c
@@ -6,7 +6,6 @@
#include <common.h>
#include <dm.h>
#include <asm/armv8/mmu.h>
-#include <asm/io.h>
#include <asm/arch-rockchip/bootrom.h>
#include <asm/arch-rockchip/grf_rk3568.h>
#include <asm/arch-rockchip/hardware.h>
diff --git a/arch/arm/mach-rockchip/rk3588/Kconfig b/arch/arm/mach-rockchip/rk3588/Kconfig
index a2193fb..d7e4af3 100644
--- a/arch/arm/mach-rockchip/rk3588/Kconfig
+++ b/arch/arm/mach-rockchip/rk3588/Kconfig
@@ -6,6 +6,33 @@
help
RK3588 EVB is a evaluation board for Rockchp RK3588.
+config TARGET_JAGUAR_RK3588
+ bool "Theobroma Systems SBC-RK3588-AMR (Jaguar)"
+ select BOARD_LATE_INIT
+ help
+ The SBC-RK3588-AMR is a Single Board Computer designed by
+ Theobroma Systems for autonomous mobile robots.
+
+ It provides the following features:
+ * up to 32GB LDDR4
+ * up to 128GB on-module eMMC (with 8-bit 1.8V interface)
+ * SD card
+ * Gigabit Ethernet
+ * 1x USB-A 2.0 host
+ * PCIe M.2 2230 Key M (Gen 2 1-lane) for WiFi+BT
+ * PCIe M.2 2280 Key M (Gen 3 4-lane) for NVMe
+ * CAN
+ * RS485 UART
+ * 2x USB Type-C 3.1 host/device
+ * HDMI output
+ * 2x camera connectors (MIPI-CSI 2-lane + I2C/SPI for IMUs + GPIOs)
+ * EEPROM
+ * Secure Element
+ * ATtiny companion controller implementing:
+ - low-power RTC functionality (ISL1208 emulation)
+ - fan controller (AMC6821 emulation)
+ * 80-pin Mezzanine connector
+
config TARGET_NANOPCT6_RK3588
bool "FriendlyElec NanoPC-T6 RK3588 board"
select BOARD_LATE_INIT
@@ -155,6 +182,30 @@
Gigabit Ethernet
Size: 69.6mm x 45mm (260-pin SO-DIMM connector)
+config TARGET_TOYBRICK_RK3588
+ bool "Toybrick TB-RK3588X board"
+ select BOARD_LATE_INIT
+ help
+ Rockchip Toybrick TB-RK3588X is a Rockchip RK3588 based development board.
+ TB-RK3588X adopts core board and mainboard design. The core board is connected
+ with the mainboard through the MXM314Pin standard interface, which can form
+ a complete industry development board.
+
+ Specifications:
+
+ Rockchip RK3588 SoC
+ 4x ARM Cortex-A76, 4x ARM Cortex-A55
+ 8/16GB Memory LPDDR4x
+ Mali G610MC4 GPU
+ 2× MIPI-CSI0 Connector
+ 1x 2Lanes PCIe3.0 Connector
+ 1x SATA3.0 Connector
+ 32GB eMMC Module
+ 2x USB2.0, 2x USB3.0
+ 1x HDMI Output, 1x HDMI Input
+ 2x Ethernet Port
+
+
config ROCKCHIP_BOOT_MODE_REG
default 0xfd588080
@@ -164,15 +215,20 @@
config SYS_SOC
default "rk3588"
+config ROCKCHIP_COMMON_STACK_ADDR
+ default y
+
-config SYS_MALLOC_F_LEN
- default 0x80000
+config TEXT_BASE
+ default 0x00a00000
source board/edgeble/neural-compute-module-6/Kconfig
source board/friendlyelec/nanopc-t6-rk3588/Kconfig
source board/pine64/quartzpro64-rk3588/Kconfig
source board/turing/turing-rk1-rk3588/Kconfig
-source board/rockchip/evb_rk3588/Kconfig
source board/radxa/rock5a-rk3588s/Kconfig
source board/radxa/rock5b-rk3588/Kconfig
+source board/rockchip/evb_rk3588/Kconfig
+source board/rockchip/toybrick_rk3588/Kconfig
+source board/theobroma-systems/jaguar_rk3588/Kconfig
endif
diff --git a/arch/arm/mach-rockchip/rk3588/rk3588.c b/arch/arm/mach-rockchip/rk3588/rk3588.c
index 38e95a6..eb65daf 100644
--- a/arch/arm/mach-rockchip/rk3588/rk3588.c
+++ b/arch/arm/mach-rockchip/rk3588/rk3588.c
@@ -7,8 +7,8 @@
#include <common.h>
#include <spl.h>
#include <asm/armv8/mmu.h>
-#include <asm/io.h>
#include <asm/arch-rockchip/bootrom.h>
+#include <asm/arch-rockchip/grf_rk3588.h>
#include <asm/arch-rockchip/hardware.h>
#include <asm/arch-rockchip/ioc_rk3588.h>
@@ -25,16 +25,14 @@
#define FW_SYSM_MST26_REG 0xa8
#define FW_SYSM_MST27_REG 0xac
-#define PMU1_IOC_BASE 0xfd5f0000
-#define PMU2_IOC_BASE 0xfd5f4000
-
-#define BUS_IOC_BASE 0xfd5f8000
#define BUS_IOC_GPIO2A_IOMUX_SEL_L 0x40
#define BUS_IOC_GPIO2B_IOMUX_SEL_L 0x48
#define BUS_IOC_GPIO2D_IOMUX_SEL_L 0x58
#define BUS_IOC_GPIO2D_IOMUX_SEL_H 0x5c
#define BUS_IOC_GPIO3A_IOMUX_SEL_L 0x60
+#define SYS_GRF_FORCE_JTAG BIT(14)
+
/**
* Boot-device identifiers used by the BROM on RK3588 when device is booted
* from SPI flash. IOMUX used for SPI flash affect the value used by the BROM
@@ -134,6 +132,9 @@
int arch_cpu_init(void)
{
#ifdef CONFIG_SPL_BUILD
+#ifdef CONFIG_ROCKCHIP_DISABLE_FORCE_JTAG
+ static struct rk3588_sysgrf * const sys_grf = (void *)SYS_GRF_BASE;
+#endif
int secure_reg;
/* Set the SDMMC eMMC crypto_ns FSPI access secure area */
@@ -168,6 +169,11 @@
secure_reg = readl(FIREWALL_SYSMEM_BASE + FW_SYSM_MST27_REG);
secure_reg &= 0xffff0000;
writel(secure_reg, FIREWALL_SYSMEM_BASE + FW_SYSM_MST27_REG);
+
+#ifdef CONFIG_ROCKCHIP_DISABLE_FORCE_JTAG
+ /* Disable JTAG exposed on SDMMC */
+ rk_clrreg(&sys_grf->soc_con[6], SYS_GRF_FORCE_JTAG);
+#endif
#endif
return 0;
diff --git a/arch/arm/mach-rockchip/rv1126/rv1126.c b/arch/arm/mach-rockchip/rv1126/rv1126.c
index b9b8987..8589c46 100644
--- a/arch/arm/mach-rockchip/rv1126/rv1126.c
+++ b/arch/arm/mach-rockchip/rv1126/rv1126.c
@@ -5,7 +5,6 @@
*/
#include <common.h>
-#include <asm/io.h>
#include <asm/arch-rockchip/bootrom.h>
#include <asm/arch-rockchip/hardware.h>
#include <asm/arch-rockchip/grf_rv1126.h>
diff --git a/arch/arm/mach-rockchip/spl-boot-order.c b/arch/arm/mach-rockchip/spl-boot-order.c
index 2c39a21..79c856d 100644
--- a/arch/arm/mach-rockchip/spl-boot-order.c
+++ b/arch/arm/mach-rockchip/spl-boot-order.c
@@ -65,9 +65,6 @@
default:
return -ENOSYS;
}
- } else if (!uclass_get_device_by_of_offset(UCLASS_SPI_FLASH, node,
- &parent)) {
- return BOOT_DEVICE_SPI;
}
/*
diff --git a/arch/arm/mach-rockchip/spl.c b/arch/arm/mach-rockchip/spl.c
index 87280e2..1586a09 100644
--- a/arch/arm/mach-rockchip/spl.c
+++ b/arch/arm/mach-rockchip/spl.c
@@ -3,7 +3,7 @@
* (C) Copyright 2019 Rockchip Electronics Co., Ltd
*/
-#include <common.h>
+#include <cpu_func.h>
#include <debug_uart.h>
#include <dm.h>
#include <hang.h>
@@ -136,6 +136,20 @@
}
gd->ram_top = gd->ram_base + get_effective_memsize();
gd->ram_top = board_get_usable_ram_top(gd->ram_size);
+
+ if (IS_ENABLED(CONFIG_ARM64) && !CONFIG_IS_ENABLED(SYS_DCACHE_OFF)) {
+ gd->relocaddr = gd->ram_top;
+ arch_reserve_mmu();
+ enable_caches();
+ }
#endif
preloader_console_init();
}
+
+void spl_board_prepare_for_boot(void)
+{
+ if (!IS_ENABLED(CONFIG_ARM64) || CONFIG_IS_ENABLED(SYS_DCACHE_OFF))
+ return;
+
+ cleanup_before_linux();
+}
diff --git a/arch/arm/mach-rockchip/u-boot-tpl-v8.lds b/arch/arm/mach-rockchip/u-boot-tpl-v8.lds
index 74618eb..ad32654 100644
--- a/arch/arm/mach-rockchip/u-boot-tpl-v8.lds
+++ b/arch/arm/mach-rockchip/u-boot-tpl-v8.lds
@@ -22,9 +22,9 @@
{
. = 0x00000000;
+ __image_copy_start = ADDR(.text);
.text : {
. = ALIGN(8);
- *(.__image_copy_start)
CPUDIR/start.o (.text*)
*(.text*)
}
@@ -44,10 +44,8 @@
KEEP(*(SORT(__u_boot_list*)));
}
- .image_copy_end : {
- . = ALIGN(8);
- *(.__image_copy_end)
- }
+ . = ALIGN(8);
+ __image_copy_end = .;
.end : {
. = ALIGN(8);
@@ -56,18 +54,11 @@
_image_binary_end = .;
- .bss_start (NOLOAD) : {
- . = ALIGN(8);
- KEEP(*(.__bss_start));
- }
-
- .bss (NOLOAD) : {
+ .bss ALIGN(8) : {
+ __bss_start = .;
*(.bss*)
- . = ALIGN(8);
- }
-
- .bss_end (NOLOAD) : {
- KEEP(*(.__bss_end));
+ . = ALIGN(8);
+ __bss_end = .;
}
/DISCARD/ : { *(.dynsym) }
diff --git a/arch/arm/mach-snapdragon/Makefile b/arch/arm/mach-snapdragon/Makefile
index 857171e..7a4495c 100644
--- a/arch/arm/mach-snapdragon/Makefile
+++ b/arch/arm/mach-snapdragon/Makefile
@@ -3,3 +3,4 @@
# (C) Copyright 2015 Mateusz Kulikowski <mateusz.kulikowski@gmail.com>
obj-y += board.o
+obj-$(CONFIG_OF_LIVE) += of_fixup.o
diff --git a/arch/arm/mach-snapdragon/board.c b/arch/arm/mach-snapdragon/board.c
index f12f579..3d5994c 100644
--- a/arch/arm/mach-snapdragon/board.c
+++ b/arch/arm/mach-snapdragon/board.c
@@ -16,6 +16,7 @@
#include <dm/pinctrl.h>
#include <dm/uclass-internal.h>
#include <dm/read.h>
+#include <power/regulator.h>
#include <env.h>
#include <init.h>
#include <linux/arm-smccc.h>
@@ -24,9 +25,12 @@
#include <linux/sizes.h>
#include <lmb.h>
#include <malloc.h>
+#include <fdt_support.h>
#include <usb.h>
#include <sort.h>
+#include "qcom-priv.h"
+
DECLARE_GLOBAL_DATA_PTR;
static struct mm_region rbx_mem_map[CONFIG_NR_DRAM_BANKS + 2] = { { 0 } };
@@ -93,7 +97,9 @@
* try and use the FDT built into U-Boot if there is one...
* This avoids having a hard dependency on the previous stage bootloader
*/
- if (IS_ENABLED(CONFIG_OF_SEPARATE) && (!fdt || fdt != ALIGN(fdt, SZ_4K))) {
+
+ if (IS_ENABLED(CONFIG_OF_SEPARATE) && (!fdt || fdt != ALIGN(fdt, SZ_4K) ||
+ fdt_check_header((void *)fdt))) {
debug("%s: Using built in FDT, bootloader gave us %#llx\n", __func__, fdt);
return (void *)gd->fdt_blob;
}
@@ -156,7 +162,9 @@
int board_init(void)
{
+ regulators_enable_boot_on(false);
show_psci_version();
+ qcom_of_fixup_nodes();
qcom_board_init();
return 0;
}
diff --git a/arch/arm/mach-snapdragon/of_fixup.c b/arch/arm/mach-snapdragon/of_fixup.c
new file mode 100644
index 0000000..3f7ac22
--- /dev/null
+++ b/arch/arm/mach-snapdragon/of_fixup.c
@@ -0,0 +1,155 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * OF_LIVE devicetree fixup.
+ *
+ * This file implements runtime fixups for Qualcomm DT to improve
+ * compatibility with U-Boot. This includes adjusting the USB nodes
+ * to only use USB high-speed, as well as remapping volume buttons
+ * to behave as up/down for navigating U-Boot.
+ *
+ * We use OF_LIVE for this rather than early FDT fixup for a couple
+ * of reasons: it has a much nicer API, is most likely more efficient,
+ * and our changes are only applied to U-Boot. This allows us to use a
+ * DT designed for Linux, run U-Boot with a modified version, and then
+ * boot Linux with the original FDT.
+ *
+ * Copyright (c) 2024 Linaro Ltd.
+ * Author: Caleb Connolly <caleb.connolly@linaro.org>
+ */
+
+#include <dt-bindings/input/linux-event-codes.h>
+#include <dm/of_access.h>
+#include <dm/of.h>
+#include <fdt_support.h>
+#include <linux/errno.h>
+#include <stdlib.h>
+#include <time.h>
+
+/* U-Boot only supports USB high-speed mode on Qualcomm platforms with DWC3
+ * USB controllers. Rather than requiring source level DT changes, we fix up
+ * DT here. This improves compatibility with upstream DT and simplifies the
+ * porting process for new devices.
+ */
+static int fixup_qcom_dwc3(struct device_node *glue_np)
+{
+ struct device_node *dwc3;
+ int ret, len, hsphy_idx = 1;
+ const __be32 *phandles;
+ const char *second_phy_name;
+
+ debug("Fixing up %s\n", glue_np->name);
+
+ /* Tell the glue driver to configure the wrapper for high-speed only operation */
+ ret = of_write_prop(glue_np, "qcom,select-utmi-as-pipe-clk", 0, NULL);
+ if (ret) {
+ log_err("Failed to add property 'qcom,select-utmi-as-pipe-clk': %d\n", ret);
+ return ret;
+ }
+
+ /* Find the DWC3 node itself */
+ dwc3 = of_find_compatible_node(glue_np, NULL, "snps,dwc3");
+ if (!dwc3) {
+ log_err("Failed to find dwc3 node\n");
+ return -ENOENT;
+ }
+
+ phandles = of_get_property(dwc3, "phys", &len);
+ len /= sizeof(*phandles);
+ if (len == 1) {
+ log_debug("Only one phy, not a superspeed controller\n");
+ return 0;
+ }
+
+ /* Figure out if the superspeed phy is present and if so then which phy is it? */
+ ret = of_property_read_string_index(dwc3, "phy-names", 1, &second_phy_name);
+ if (ret == -ENODATA) {
+ log_debug("Only one phy, not a super-speed controller\n");
+ return 0;
+ } else if (ret) {
+ log_err("Failed to read second phy name: %d\n", ret);
+ return ret;
+ }
+
+ if (!strncmp("usb3-phy", second_phy_name, strlen("usb3-phy"))) {
+ log_debug("Second phy isn't superspeed (is '%s') assuming first phy is SS\n",
+ second_phy_name);
+ hsphy_idx = 0;
+ }
+
+ /* Overwrite the "phys" property to only contain the high-speed phy */
+ ret = of_write_prop(dwc3, "phys", sizeof(*phandles), phandles + hsphy_idx);
+ if (ret) {
+ log_err("Failed to overwrite 'phys' property: %d\n", ret);
+ return ret;
+ }
+
+ /* Overwrite "phy-names" to only contain a single entry */
+ ret = of_write_prop(dwc3, "phy-names", strlen("usb2-phy"), "usb2-phy");
+ if (ret) {
+ log_err("Failed to overwrite 'phy-names' property: %d\n", ret);
+ return ret;
+ }
+
+ ret = of_write_prop(dwc3, "maximum-speed", strlen("high-speed"), "high-speed");
+ if (ret) {
+ log_err("Failed to set 'maximum-speed' property: %d\n", ret);
+ return ret;
+ }
+
+ return 0;
+}
+
+static void fixup_usb_nodes(void)
+{
+ struct device_node *glue_np = NULL;
+ int ret;
+
+ while ((glue_np = of_find_compatible_node(glue_np, NULL, "qcom,dwc3"))) {
+ ret = fixup_qcom_dwc3(glue_np);
+ if (ret)
+ log_warning("Failed to fixup node %s: %d\n", glue_np->name, ret);
+ }
+}
+
+/* Remove all references to the rpmhpd device */
+static void fixup_power_domains(void)
+{
+ struct device_node *pd = NULL, *np = NULL;
+ struct property *prop;
+ const __be32 *val;
+
+ /* All Qualcomm platforms name the rpm(h)pd "power-controller" */
+ for_each_of_allnodes(pd) {
+ if (pd->name && !strcmp("power-controller", pd->name))
+ break;
+ }
+
+ /* Sanity check that this is indeed a power domain controller */
+ if (!of_find_property(pd, "#power-domain-cells", NULL)) {
+ log_err("Found power-controller but it doesn't have #power-domain-cells\n");
+ return;
+ }
+
+ /* Remove all references to the power domain controller */
+ for_each_of_allnodes(np) {
+ if (!(prop = of_find_property(np, "power-domains", NULL)))
+ continue;
+
+ val = prop->value;
+ if (val[0] == cpu_to_fdt32(pd->phandle))
+ of_remove_property(np, prop);
+ }
+}
+
+#define time_call(func, ...) \
+ do { \
+ u64 start = timer_get_us(); \
+ func(__VA_ARGS__); \
+ debug(#func " took %lluus\n", timer_get_us() - start); \
+ } while (0)
+
+void qcom_of_fixup_nodes(void)
+{
+ time_call(fixup_usb_nodes);
+ time_call(fixup_power_domains);
+}
diff --git a/arch/arm/mach-snapdragon/qcom-priv.h b/arch/arm/mach-snapdragon/qcom-priv.h
new file mode 100644
index 0000000..0a7ed5e
--- /dev/null
+++ b/arch/arm/mach-snapdragon/qcom-priv.h
@@ -0,0 +1,20 @@
+// SPDX-License-Identifier: GPL-2.0
+
+#ifndef __QCOM_PRIV_H__
+#define __QCOM_PRIV_H__
+
+#if CONFIG_IS_ENABLED(OF_LIVE)
+/**
+ * qcom_of_fixup_nodes() - Fixup Qualcomm DT nodes
+ *
+ * Adjusts nodes in the live tree to improve compatibility with U-Boot.
+ */
+void qcom_of_fixup_nodes(void);
+#else
+static inline void qcom_of_fixup_nodes(void)
+{
+ log_debug("Unable to dynamically fixup USB nodes, please enable CONFIG_OF_LIVE\n");
+}
+#endif /* OF_LIVE */
+
+#endif /* __QCOM_PRIV_H__ */
diff --git a/arch/arm/mach-socfpga/Kconfig b/arch/arm/mach-socfpga/Kconfig
index 114d243..1008232 100644
--- a/arch/arm/mach-socfpga/Kconfig
+++ b/arch/arm/mach-socfpga/Kconfig
@@ -8,7 +8,8 @@
config SOCFPGA_SECURE_VAB_AUTH
bool "Enable boot image authentication with Secure Device Manager"
- depends on TARGET_SOCFPGA_AGILEX || TARGET_SOCFPGA_N5X
+ depends on TARGET_SOCFPGA_AGILEX || TARGET_SOCFPGA_N5X || \
+ TARGET_SOCFPGA_AGILEX5
select FIT_IMAGE_POST_PROCESS
select SHA384
select SHA512
@@ -58,6 +59,15 @@
select SPL_CLK if SPL
select TARGET_SOCFPGA_SOC64
+config TARGET_SOCFPGA_AGILEX5
+ bool
+ select BINMAN if SPL_ATF
+ select CLK
+ select FPGA_INTEL_SDM_MAILBOX
+ select GICV3
+ select SPL_CLK if SPL
+ select TARGET_SOCFPGA_SOC64
+
config TARGET_SOCFPGA_ARRIA5
bool
select TARGET_SOCFPGA_GEN5
@@ -129,6 +139,10 @@
bool "Intel SOCFPGA SoCDK (Agilex)"
select TARGET_SOCFPGA_AGILEX
+config TARGET_SOCFPGA_AGILEX5_SOCDK
+ bool "Intel SOCFPGA SoCDK (Agilex5)"
+ select TARGET_SOCFPGA_AGILEX5
+
config TARGET_SOCFPGA_ARIES_MCVEVK
bool "Aries MCVEVK (Cyclone V)"
select TARGET_SOCFPGA_CYCLONE5
@@ -202,6 +216,7 @@
endchoice
config SYS_BOARD
+ default "agilex5-socdk" if TARGET_SOCFPGA_AGILEX5_SOCDK
default "agilex-socdk" if TARGET_SOCFPGA_AGILEX_SOCDK
default "arria5-socdk" if TARGET_SOCFPGA_ARRIA5_SOCDK
default "arria10-socdk" if TARGET_SOCFPGA_ARRIA10_SOCDK
@@ -223,6 +238,7 @@
default "vining_fpga" if TARGET_SOCFPGA_SOFTING_VINING_FPGA
config SYS_VENDOR
+ default "intel" if TARGET_SOCFPGA_AGILEX5_SOCDK
default "intel" if TARGET_SOCFPGA_AGILEX_SOCDK
default "intel" if TARGET_SOCFPGA_N5X_SOCDK
default "altera" if TARGET_SOCFPGA_ARRIA5_SOCDK
@@ -245,6 +261,7 @@
default "socfpga"
config SYS_CONFIG_NAME
+ default "socfpga_agilex5_socdk" if TARGET_SOCFPGA_AGILEX5_SOCDK
default "socfpga_agilex_socdk" if TARGET_SOCFPGA_AGILEX_SOCDK
default "socfpga_arria5_secu1" if TARGET_SOCFPGA_ARRIA5_SECU1
default "socfpga_arria5_socdk" if TARGET_SOCFPGA_ARRIA5_SOCDK
diff --git a/arch/arm/mach-socfpga/Makefile b/arch/arm/mach-socfpga/Makefile
index ec38b64..67c6a8d 100644
--- a/arch/arm/mach-socfpga/Makefile
+++ b/arch/arm/mach-socfpga/Makefile
@@ -4,7 +4,7 @@
# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
#
# Copyright (C) 2012-2017 Altera Corporation <www.altera.com>
-# Copyright (C) 2017-2021 Intel Corporation <www.intel.com>
+# Copyright (C) 2017-2024 Intel Corporation <www.intel.com>
obj-y += board.o
obj-y += clock_manager.o
@@ -56,6 +56,15 @@
obj-y += wrap_pll_config_soc64.o
endif
+ifdef CONFIG_TARGET_SOCFPGA_AGILEX5
+obj-y += clock_manager_agilex5.o
+obj-y += mailbox_s10.o
+obj-y += misc_soc64.o
+obj-y += mmu-arm64_s10.o
+obj-y += reset_manager_s10.o
+obj-y += wrap_pll_config_soc64.o
+endif
+
ifdef CONFIG_TARGET_SOCFPGA_N5X
obj-y += clock_manager_n5x.o
obj-y += lowlevel_init_soc64.o
@@ -95,6 +104,9 @@
ifdef CONFIG_TARGET_SOCFPGA_N5X
obj-y += spl_n5x.o
endif
+ifdef CONFIG_TARGET_SOCFPGA_AGILEX5
+obj-y += spl_soc64.o
+endif
else
obj-$(CONFIG_SPL_ATF) += secure_reg_helper.o
obj-$(CONFIG_SPL_ATF) += smc_api.o
diff --git a/arch/arm/mach-socfpga/board.c b/arch/arm/mach-socfpga/board.c
index 09e0919..616e1af 100644
--- a/arch/arm/mach-socfpga/board.c
+++ b/arch/arm/mach-socfpga/board.c
@@ -7,9 +7,11 @@
#include <common.h>
#include <asm/arch/clock_manager.h>
+#include <asm/arch/mailbox_s10.h>
#include <asm/arch/misc.h>
#include <asm/arch/reset_manager.h>
#include <asm/arch/secure_vab.h>
+#include <asm/arch/smc_api.h>
#include <asm/global_data.h>
#include <asm/io.h>
#include <errno.h>
@@ -23,6 +25,8 @@
DECLARE_GLOBAL_DATA_PTR;
+#define DEFAULT_JTAG_USERCODE 0xFFFFFFFF
+
void s_init(void) {
#ifndef CONFIG_ARM64
/*
@@ -92,13 +96,50 @@
}
#endif
-#ifdef CONFIG_SPL_BUILD
-__weak int board_fit_config_name_match(const char *name)
+u8 socfpga_get_board_id(void)
{
- /* Just empty function now - can't decide what to choose */
- debug("%s: %s\n", __func__, name);
+ u8 board_id = 0;
+ u32 jtag_usercode;
+ int err;
- return 0;
+#if !IS_ENABLED(CONFIG_SPL_BUILD) && IS_ENABLED(CONFIG_SPL_ATF)
+ err = smc_get_usercode(&jtag_usercode);
+#else
+ u32 resp_len = 1;
+
+ err = mbox_send_cmd(MBOX_ID_UBOOT, MBOX_GET_USERCODE, MBOX_CMD_DIRECT, 0,
+ NULL, 0, &resp_len, &jtag_usercode);
+#endif
+
+ if (err) {
+ puts("Fail to read JTAG Usercode. Default Board ID to 0\n");
+ return board_id;
+ }
+
+ debug("Valid JTAG Usercode: %u\n", jtag_usercode);
+
+ if (jtag_usercode == DEFAULT_JTAG_USERCODE) {
+ debug("JTAG Usercode is not set. Default Board ID to 0\n");
+ } else if (jtag_usercode >= 0 && jtag_usercode <= 255) {
+ board_id = jtag_usercode;
+ debug("Valid JTAG Usercode. Set Board ID to %u\n", board_id);
+ } else {
+ puts("Board ID is not in range 0 to 255\n");
+ }
+
+ return board_id;
+}
+
+#if IS_ENABLED(CONFIG_SPL_BUILD) && IS_ENABLED(CONFIG_TARGET_SOCFPGA_SOC64)
+int board_fit_config_name_match(const char *name)
+{
+ char board_name[10];
+
+ sprintf(board_name, "board_%u", socfpga_get_board_id());
+
+ debug("Board name: %s\n", board_name);
+
+ return strcmp(name, board_name);
}
#endif
@@ -116,6 +157,8 @@
#if !IS_ENABLED(CONFIG_SPL_BUILD) && IS_ENABLED(CONFIG_FIT)
void board_prep_linux(struct bootm_headers *images)
{
+ bool use_fit = false;
+
if (!images->fit_uname_cfg) {
if (IS_ENABLED(CONFIG_SOCFPGA_SECURE_VAB_AUTH) &&
!IS_ENABLED(CONFIG_SOCFPGA_SECURE_VAB_AUTH_ALLOW_NON_FIT_IMAGE)) {
@@ -127,12 +170,13 @@
hang();
}
} else {
+ use_fit = true;
/* Update fdt_addr in enviroment variable */
env_set_hex("fdt_addr", (ulong)images->ft_addr);
debug("images->ft_addr = 0x%08lx\n", (ulong)images->ft_addr);
}
- if (IS_ENABLED(CONFIG_CADENCE_QSPI)) {
+ if (use_fit && IS_ENABLED(CONFIG_CADENCE_QSPI)) {
if (env_get("linux_qspi_enable"))
run_command(env_get("linux_qspi_enable"), 0);
}
diff --git a/arch/arm/mach-socfpga/clock_manager_agilex5.c b/arch/arm/mach-socfpga/clock_manager_agilex5.c
new file mode 100644
index 0000000..b92f0b3
--- /dev/null
+++ b/arch/arm/mach-socfpga/clock_manager_agilex5.c
@@ -0,0 +1,89 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (C) 2024 Intel Corporation <www.intel.com>
+ *
+ */
+
+#include <clk.h>
+#include <config.h>
+#include <dm.h>
+#include <errno.h>
+#include <log.h>
+#include <malloc.h>
+#include <stdarg.h>
+#include <stdio.h>
+#include <time.h>
+#include <vsprintf.h>
+#include <asm/global_data.h>
+#include <asm/io.h>
+#include <asm/u-boot.h>
+#include <linux/kernel.h>
+#include <linux/string.h>
+#include <linux/types.h>
+#include <asm/arch/clock_manager.h>
+#include <asm/arch/system_manager.h>
+#include <dt-bindings/clock/agilex5-clock.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+static ulong cm_get_rate_dm(u32 id)
+{
+ struct udevice *dev;
+ struct clk clk;
+ ulong rate;
+ int ret;
+
+ ret = uclass_get_device_by_driver(UCLASS_CLK,
+ DM_DRIVER_GET(socfpga_agilex5_clk),
+ &dev);
+ if (ret)
+ return 0;
+
+ clk.id = id;
+ ret = clk_request(dev, &clk);
+ if (ret < 0)
+ return 0;
+
+ rate = clk_get_rate(&clk);
+
+ if ((rate == (unsigned long)-ENOSYS) ||
+ (rate == (unsigned long)-ENXIO) ||
+ (rate == (unsigned long)-EIO)) {
+ debug("%s id %u: clk_get_rate err: %ld\n",
+ __func__, id, rate);
+ return 0;
+ }
+
+ return rate;
+}
+
+static u32 cm_get_rate_dm_khz(u32 id)
+{
+ return cm_get_rate_dm(id) / 1000;
+}
+
+unsigned long cm_get_mpu_clk_hz(void)
+{
+ return cm_get_rate_dm(AGILEX5_MPU_CLK);
+}
+
+unsigned int cm_get_l4_sys_free_clk_hz(void)
+{
+ return cm_get_rate_dm(AGILEX5_L4_SYS_FREE_CLK);
+}
+
+void cm_print_clock_quick_summary(void)
+{
+ printf("MPU %10d kHz\n",
+ cm_get_rate_dm_khz(AGILEX5_MPU_CLK));
+ printf("L4 Main %8d kHz\n",
+ cm_get_rate_dm_khz(AGILEX5_L4_MAIN_CLK));
+ printf("L4 sys free %8d kHz\n",
+ cm_get_rate_dm_khz(AGILEX5_L4_SYS_FREE_CLK));
+ printf("L4 MP %8d kHz\n",
+ cm_get_rate_dm_khz(AGILEX5_L4_MP_CLK));
+ printf("L4 SP %8d kHz\n",
+ cm_get_rate_dm_khz(AGILEX5_L4_SP_CLK));
+ printf("SDMMC %8d kHz\n",
+ cm_get_rate_dm_khz(AGILEX5_SDMMC_CLK));
+}
diff --git a/arch/arm/mach-socfpga/include/mach/base_addr_soc64.h b/arch/arm/mach-socfpga/include/mach/base_addr_soc64.h
index 3f899fc..6572109 100644
--- a/arch/arm/mach-socfpga/include/mach/base_addr_soc64.h
+++ b/arch/arm/mach-socfpga/include/mach/base_addr_soc64.h
@@ -1,11 +1,46 @@
/* SPDX-License-Identifier: GPL-2.0 */
/*
- * Copyright (C) 2016-2021 Intel Corporation <www.intel.com>
+ * Copyright (C) 2016-2024 Intel Corporation <www.intel.com>
*/
#ifndef _SOCFPGA_SOC64_BASE_HARDWARE_H_
#define _SOCFPGA_SOC64_BASE_HARDWARE_H_
+#if IS_ENABLED(CONFIG_TARGET_SOCFPGA_AGILEX5)
+#define SOCFPGA_CCU_ADDRESS 0x1c000000
+#define SOCFPGA_F2SDRAM_MGR_ADDRESS 0x18001000
+#define SOCFPGA_SMMU_ADDRESS 0x16000000
+#define SOCFPGA_OCRAM_FIREWALL_ADDRESS 0x108cc400
+#define SOCFPGA_MAILBOX_ADDRESS 0x10a30000
+#define SOCFPGA_UART0_ADDRESS 0x10c02000
+#define SOCFPGA_UART1_ADDRESS 0x10c02100
+#define SOCFPGA_SPTIMER0_ADDRESS 0x10c03000
+#define SOCFPGA_SPTIMER1_ADDRESS 0x10c03100
+#define SOCFPGA_SYSTIMER0_ADDRESS 0x10d00000
+#define SOCFPGA_SYSTIMER1_ADDRESS 0x10d00100
+#define SOCFPGA_L4WD0_ADDRESS 0x10d00200
+#define SOCFPGA_L4WD1_ADDRESS 0x10d00300
+#define SOCFPGA_L4WD2_ADDRESS 0x10d00400
+#define SOCFPGA_L4WD3_ADDRESS 0x10d00500
+#define SOCFPGA_L4WD4_ADDRESS 0x10d00600
+#define SOCFPGA_GTIMER_SEC_ADDRESS 0x10d01000
+#define SOCFPGA_GTIMER_NSEC_ADDRESS 0x10d02000
+#define SOCFPGA_CLKMGR_ADDRESS 0x10d10000
+#define SOCFPGA_RSTMGR_ADDRESS 0x10d11000
+#define SOCFPGA_SYSMGR_ADDRESS 0x10d12000
+#define SOCFPGA_OCRAM_ADDRESS 0x00000000
+#define SOCFPGA_FW_DDR_CCU_DMI0_ADDRESS 0x18000800
+#define SOCFPGA_FW_DDR_CCU_DMI1_ADDRESS 0x18000A00
+#define SOCFPGA_FW_TBU2NOC_ADDRESS 0x18000C00
+#define SOCFPGA_FIREWALL_L4_PER 0x10d21000
+#define SOCFPGA_FIREWALL_L4_SYS 0x10d21100
+#define SOCFPGA_FIREWALL_SOC2FPGA 0x10d21200
+#define SOCFPGA_FIREWALL_LWSOC2FPGA 0x10d21300
+#define SOCFPGA_FIREWALL_TCU 0x10d21400
+#define SOCFPGA_FIREWALL_PRIV_MEMORYMAP_PRIV 0x10d24800
+#define GICD_BASE 0x1d000000
+#define GICR_BASE 0x1d060000
+#else
#define SOCFPGA_CCU_ADDRESS 0xf7000000
#define SOCFPGA_SDR_SCHEDULER_ADDRESS 0xf8000400
#define SOCFPGA_HMC_MMR_IO48_ADDRESS 0xf8010000
@@ -44,5 +79,6 @@
#define SOCFPGA_OCRAM_ADDRESS 0xffe00000
#define GICD_BASE 0xfffc1000
#define GICC_BASE 0xfffc2000
+#endif /* IS_ENABLED(CONFIG_TARGET_SOCFPGA_AGILEX5) */
#endif /* _SOCFPGA_SOC64_BASE_HARDWARE_H_ */
diff --git a/arch/arm/mach-socfpga/include/mach/clock_manager.h b/arch/arm/mach-socfpga/include/mach/clock_manager.h
index a8cb07a..6c9d32b 100644
--- a/arch/arm/mach-socfpga/include/mach/clock_manager.h
+++ b/arch/arm/mach-socfpga/include/mach/clock_manager.h
@@ -1,6 +1,6 @@
/* SPDX-License-Identifier: GPL-2.0+ */
/*
- * Copyright (C) 2013-2017 Altera Corporation <www.altera.com>
+ * Copyright (C) 2013-2024 Altera Corporation <www.altera.com>
*/
#ifndef _CLOCK_MANAGER_H_
@@ -28,6 +28,8 @@
#include <asm/arch/clock_manager_s10.h>
#elif defined(CONFIG_TARGET_SOCFPGA_AGILEX)
#include <asm/arch/clock_manager_agilex.h>
+#elif IS_ENABLED(CONFIG_TARGET_SOCFPGA_AGILEX5)
+#include <asm/arch/clock_manager_agilex5.h>
#elif IS_ENABLED(CONFIG_TARGET_SOCFPGA_N5X)
#include <asm/arch/clock_manager_n5x.h>
#endif
diff --git a/arch/arm/mach-socfpga/include/mach/clock_manager_agilex5.h b/arch/arm/mach-socfpga/include/mach/clock_manager_agilex5.h
new file mode 100644
index 0000000..1ae0a92
--- /dev/null
+++ b/arch/arm/mach-socfpga/include/mach/clock_manager_agilex5.h
@@ -0,0 +1,12 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Copyright (C) 2024 Intel Corporation <www.intel.com>
+ */
+
+#ifndef _CLOCK_MANAGER_AGILEX5_
+#define _CLOCK_MANAGER_AGILEX5_
+
+#include <asm/arch/clock_manager_soc64.h>
+#include "../../../../../drivers/clk/altera/clk-agilex5.h"
+
+#endif /* _CLOCK_MANAGER_AGILEX5_ */
diff --git a/arch/arm/mach-socfpga/include/mach/handoff_soc64.h b/arch/arm/mach-socfpga/include/mach/handoff_soc64.h
index 9b85e58..d839f28 100644
--- a/arch/arm/mach-socfpga/include/mach/handoff_soc64.h
+++ b/arch/arm/mach-socfpga/include/mach/handoff_soc64.h
@@ -1,6 +1,6 @@
/* SPDX-License-Identifier: GPL-2.0
*
- * Copyright (C) 2016-2021 Intel Corporation <www.intel.com>
+ * Copyright (C) 2016-2024 Intel Corporation <www.intel.com>
*
*/
@@ -17,7 +17,12 @@
#define SOC64_HANDOFF_MAGIC_FPGA 0x46504741
#define SOC64_HANDOFF_MAGIC_DELAY 0x444C4159
#define SOC64_HANDOFF_MAGIC_CLOCK 0x434C4B53
+#if IS_ENABLED(CONFIG_TARGET_SOCFPGA_AGILEX5)
+#define SOC64_HANDOFF_MAGIC_PERI 0x50455249
+#define SOC64_HANDOFF_MAGIC_SDRAM 0x5344524d
+#else
#define SOC64_HANDOFF_MAGIC_MISC 0x4D495343
+#endif
#define SOC64_HANDOFF_OFFSET_LENGTH 0x4
#define SOC64_HANDOFF_OFFSET_DATA 0x10
@@ -27,6 +32,8 @@
IS_ENABLED(CONFIG_TARGET_SOCFPGA_AGILEX)
#define SOC64_HANDOFF_BASE 0xFFE3F000
#define SOC64_HANDOFF_MISC (SOC64_HANDOFF_BASE + 0x610)
+#elif IS_ENABLED(CONFIG_TARGET_SOCFPGA_AGILEX5)
+#define SOC64_HANDOFF_BASE 0x0007F000
#elif IS_ENABLED(CONFIG_TARGET_SOCFPGA_N5X)
#define SOC64_HANDOFF_BASE 0xFFE5F000
#define SOC64_HANDOFF_MISC (SOC64_HANDOFF_BASE + 0x630)
@@ -58,13 +65,21 @@
#define SOC64_HANDOFF_FPGA (SOC64_HANDOFF_BASE + 0x330)
#define SOC64_HANDOFF_DELAY (SOC64_HANDOFF_BASE + 0x3F0)
#define SOC64_HANDOFF_CLOCK (SOC64_HANDOFF_BASE + 0x580)
+#if IS_ENABLED(CONFIG_TARGET_SOCFPGA_AGILEX5)
+#define SOC64_HANDOFF_PERI (SOC64_HANDOFF_BASE + 0x620)
+#define SOC64_HANDOFF_SDRAM (SOC64_HANDOFF_BASE + 0x634)
+#define SOC64_HANDOFF_SDRAM_LEN 1
+#endif
#if IS_ENABLED(CONFIG_TARGET_SOCFPGA_STRATIX10)
-#define SOC64_HANDOFF_CLOCK_OSC (SOC64_HANDOFF_BASE + 0x608)
-#define SOC64_HANDOFF_CLOCK_FPGA (SOC64_HANDOFF_BASE + 0x60C)
+#define SOC64_HANDOFF_CLOCK_OSC (SOC64_HANDOFF_BASE + 0x608)
+#define SOC64_HANDOFF_CLOCK_FPGA (SOC64_HANDOFF_BASE + 0x60C)
+#elif IS_ENABLED(CONFIG_TARGET_SOCFPGA_AGILEX5)
+#define SOC64_HANDOFF_CLOCK_OSC (SOC64_HANDOFF_BASE + 0x60c)
+#define SOC64_HANDOFF_CLOCK_FPGA (SOC64_HANDOFF_BASE + 0x610)
#else
-#define SOC64_HANDOFF_CLOCK_OSC (SOC64_HANDOFF_BASE + 0x5fc)
-#define SOC64_HANDOFF_CLOCK_FPGA (SOC64_HANDOFF_BASE + 0x600)
+#define SOC64_HANDOFF_CLOCK_OSC (SOC64_HANDOFF_BASE + 0x5fc)
+#define SOC64_HANDOFF_CLOCK_FPGA (SOC64_HANDOFF_BASE + 0x600)
#endif
#define SOC64_HANDOFF_MUX_LEN 96
diff --git a/arch/arm/mach-socfpga/include/mach/mailbox_s10.h b/arch/arm/mach-socfpga/include/mach/mailbox_s10.h
index fbaf115..2cc7c89 100644
--- a/arch/arm/mach-socfpga/include/mach/mailbox_s10.h
+++ b/arch/arm/mach-socfpga/include/mach/mailbox_s10.h
@@ -119,6 +119,7 @@
#define MBOX_RECONFIG_DATA 8
#define MBOX_RECONFIG_STATUS 9
#define MBOX_VAB_SRC_CERT 11
+#define MBOX_GET_USERCODE 19
#define MBOX_QSPI_OPEN 50
#define MBOX_QSPI_CLOSE 51
#define MBOX_QSPI_DIRECT 59
diff --git a/arch/arm/mach-socfpga/mmu-arm64_s10.c b/arch/arm/mach-socfpga/mmu-arm64_s10.c
index a55b7b7..91c6d7c 100644
--- a/arch/arm/mach-socfpga/mmu-arm64_s10.c
+++ b/arch/arm/mach-socfpga/mmu-arm64_s10.c
@@ -1,6 +1,6 @@
// SPDX-License-Identifier: GPL-2.0
/*
- * Copyright (C) 2016-2018 Intel Corporation <www.intel.com>
+ * Copyright (C) 2016-2024 Intel Corporation <www.intel.com>
*
*/
@@ -10,6 +10,62 @@
DECLARE_GLOBAL_DATA_PTR;
+#if IS_ENABLED(CONFIG_TARGET_SOCFPGA_AGILEX5)
+static struct mm_region socfpga_agilex5_mem_map[] = {
+ {
+ /* OCRAM 512KB */
+ .virt = 0x00000000UL,
+ .phys = 0x00000000UL,
+ .size = 0x00080000UL,
+ .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
+ PTE_BLOCK_NON_SHARE,
+ }, {
+ /* DEVICE */
+ .virt = 0x10808000UL,
+ .phys = 0x10808000UL,
+ .size = 0x0F7F8000UL,
+ .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
+ PTE_BLOCK_NON_SHARE |
+ PTE_BLOCK_PXN | PTE_BLOCK_UXN,
+ }, {
+ /* FPGA 1.5GB */
+ .virt = 0x20000000UL,
+ .phys = 0x20000000UL,
+ .size = 0x60000000UL,
+ .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
+ PTE_BLOCK_NON_SHARE |
+ PTE_BLOCK_PXN | PTE_BLOCK_UXN,
+ }, {
+ /* FPGA 15GB */
+ .virt = 0x440000000UL,
+ .phys = 0x440000000UL,
+ .size = 0x3C0000000UL,
+ .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
+ PTE_BLOCK_NON_SHARE |
+ PTE_BLOCK_PXN | PTE_BLOCK_UXN,
+ }, {
+ /* FPGA 240GB */
+ .virt = 0x4400000000UL,
+ .phys = 0x4400000000UL,
+ .size = 0x3C00000000UL,
+ .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
+ PTE_BLOCK_NON_SHARE |
+ PTE_BLOCK_PXN | PTE_BLOCK_UXN,
+ }, {
+ /* MEM 2GB */
+ .virt = 0x80000000UL,
+ .phys = 0x80000000UL,
+ .size = 0x80000000UL,
+ .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
+ PTE_BLOCK_INNER_SHARE,
+ }, {
+ /* List terminator */
+ },
+};
+
+struct mm_region *mem_map = socfpga_agilex5_mem_map;
+
+#else
static struct mm_region socfpga_stratix10_mem_map[] = {
{
/* MEM 2GB*/
@@ -70,3 +126,4 @@
};
struct mm_region *mem_map = socfpga_stratix10_mem_map;
+#endif
diff --git a/arch/arm/mach-socfpga/wrap_handoff_soc64.c b/arch/arm/mach-socfpga/wrap_handoff_soc64.c
index df0701e..6aa9bb2 100644
--- a/arch/arm/mach-socfpga/wrap_handoff_soc64.c
+++ b/arch/arm/mach-socfpga/wrap_handoff_soc64.c
@@ -11,7 +11,6 @@
#include "log.h"
#ifndef __ASSEMBLY__
-#include <asm/types.h>
enum endianness {
LITTLE_ENDIAN = 0,
BIG_ENDIAN,
diff --git a/arch/arm/mach-versal-net/Kconfig b/arch/arm/mach-versal-net/Kconfig
index 1b53399..54fb93a 100644
--- a/arch/arm/mach-versal-net/Kconfig
+++ b/arch/arm/mach-versal-net/Kconfig
@@ -35,6 +35,9 @@
config GICV3
def_bool y
+config GICV3_SUPPORT_GIC600
+ def_bool y
+
config SYS_MALLOC_LEN
default 0x2000000
diff --git a/arch/arm/mach-zynq/u-boot-spl.lds b/arch/arm/mach-zynq/u-boot-spl.lds
index 8c18d3f..d96a577 100644
--- a/arch/arm/mach-zynq/u-boot-spl.lds
+++ b/arch/arm/mach-zynq/u-boot-spl.lds
@@ -18,9 +18,9 @@
SECTIONS
{
. = ALIGN(4);
+ __image_copy_start = ADDR(.text);
.text :
{
- __image_copy_start = .;
*(.vectors)
CPUDIR/start.o (.text*)
*(.text*)
diff --git a/arch/arm/mach-zynq/u-boot.lds b/arch/arm/mach-zynq/u-boot.lds
index 3b7c9d5..3e0c96c 100644
--- a/arch/arm/mach-zynq/u-boot.lds
+++ b/arch/arm/mach-zynq/u-boot.lds
@@ -14,28 +14,22 @@
. = 0x00000000;
. = ALIGN(4);
+ __image_copy_start = ADDR(.text);
.text :
{
- *(.__image_copy_start)
*(.vectors)
CPUDIR/start.o (.text*)
}
/* This needs to come before *(.text*) */
- .__efi_runtime_start : {
- *(.__efi_runtime_start)
- }
-
.efi_runtime : {
+ __efi_runtime_start = .;
*(.text.efi_runtime*)
*(.rodata.efi_runtime*)
*(.data.efi_runtime*)
+ __efi_runtime_stop = .;
}
- .__efi_runtime_stop : {
- *(.__efi_runtime_stop)
- }
-
.text_rest :
{
*(.text*)
@@ -58,41 +52,20 @@
KEEP(*(SORT(__u_boot_list*)));
}
- . = ALIGN(4);
-
- .efi_runtime_rel_start :
- {
- *(.__efi_runtime_rel_start)
- }
-
.efi_runtime_rel : {
+ __efi_runtime_rel_start = .;
*(.rel*.efi_runtime)
*(.rel*.efi_runtime.*)
- }
-
- .efi_runtime_rel_stop :
- {
- *(.__efi_runtime_rel_stop)
+ __efi_runtime_rel_stop = .;
}
. = ALIGN(8);
- .image_copy_end :
- {
- *(.__image_copy_end)
- }
-
- .rel_dyn_start :
- {
- *(.__rel_dyn_start)
- }
+ __image_copy_end = .;
- .rel.dyn : {
+ .rel.dyn ALIGN(8) : {
+ __rel_dyn_start = .;
*(.rel*)
- }
-
- .rel_dyn_end :
- {
- *(.__rel_dyn_end)
+ __rel_dyn_end = .;
}
.end :
@@ -103,23 +76,15 @@
_image_binary_end = .;
/*
- * Compiler-generated __bss_start and __bss_end, see arch/arm/lib/bss.c
- * __bss_base and __bss_limit are for linker only (overlay ordering)
+ * These sections occupy the same memory, but their lifetimes do
+ * not overlap: U-Boot initializes .bss only after applying dynamic
+ * relocations and therefore after it doesn't need .rel.dyn any more.
*/
-
- .bss_start __rel_dyn_start (OVERLAY) : {
- KEEP(*(.__bss_start));
- __bss_base = .;
- }
-
- .bss __bss_base (OVERLAY) : {
+ .bss ADDR(.rel.dyn) (OVERLAY): {
+ __bss_start = .;
*(.bss*)
- . = ALIGN(8);
- __bss_limit = .;
- }
-
- .bss_end __bss_limit (OVERLAY) : {
- KEEP(*(.__bss_end));
+ . = ALIGN(8);
+ __bss_end = .;
}
/*
diff --git a/arch/arm/mach-zynqmp/Kconfig b/arch/arm/mach-zynqmp/Kconfig
index 6a7be0b..0d2238a 100644
--- a/arch/arm/mach-zynqmp/Kconfig
+++ b/arch/arm/mach-zynqmp/Kconfig
@@ -1,29 +1,5 @@
if ARCH_ZYNQMP
-config SPL_FS_FAT
- default y
-
-config SPL_LIBCOMMON_SUPPORT
- default y
-
-config SPL_LIBDISK_SUPPORT
- default y
-
-config SPL_LIBGENERIC_SUPPORT
- default y
-
-config SPL_MMC
- default y if MMC_SDHCI_ZYNQ
-
-config SPL_SERIAL
- default y
-
-config SPL_SPI_FLASH_SUPPORT
- default y if ZYNQ_QSPI
-
-config SPL_SPI
- default y if ZYNQ_QSPI
-
config SYS_BOARD
string "Board name"
default "zynqmp"
@@ -135,7 +111,8 @@
config SPL_ZYNQMP_PSU_INIT_ENABLED
bool "Include psu_init in SPL"
- default y if SPL
+ depends on SPL
+ default y
select BOARD_EARLY_INIT_F
help
Include psu_init by default in SPL.
diff --git a/arch/arm/mach-zynqmp/spl.c b/arch/arm/mach-zynqmp/spl.c
index a0f35f3..979ff3a 100644
--- a/arch/arm/mach-zynqmp/spl.c
+++ b/arch/arm/mach-zynqmp/spl.c
@@ -9,6 +9,7 @@
#include <image.h>
#include <init.h>
#include <log.h>
+#include <semihosting.h>
#include <spl.h>
#include <linux/delay.h>
@@ -66,6 +67,11 @@
}
#endif
+static u32 jtag_boot_device(void)
+{
+ return semihosting_enabled() ? BOOT_DEVICE_SMH : BOOT_DEVICE_RAM;
+}
+
void board_boot_order(u32 *spl_boot_list)
{
spl_boot_list[0] = spl_boot_device();
@@ -75,7 +81,7 @@
if (spl_boot_list[0] == BOOT_DEVICE_MMC2)
spl_boot_list[1] = BOOT_DEVICE_MMC1;
- spl_boot_list[2] = BOOT_DEVICE_RAM;
+ spl_boot_list[2] = jtag_boot_device();
}
u32 spl_boot_device(void)
@@ -85,19 +91,20 @@
#if defined(CONFIG_SPL_ZYNQMP_ALT_BOOTMODE_ENABLED)
/* Change default boot mode at run-time */
+ reg = CONFIG_SPL_ZYNQMP_ALT_BOOTMODE;
writel(CONFIG_SPL_ZYNQMP_ALT_BOOTMODE << BOOT_MODE_ALT_SHIFT,
&crlapb_base->boot_mode);
-#endif
-
+#else
reg = readl(&crlapb_base->boot_mode);
if (reg >> BOOT_MODE_ALT_SHIFT)
reg >>= BOOT_MODE_ALT_SHIFT;
+#endif
bootmode = reg & BOOT_MODES_MASK;
switch (bootmode) {
case JTAG_MODE:
- return BOOT_DEVICE_RAM;
+ return jtag_boot_device();
#ifdef CONFIG_SPL_MMC
case SD_MODE1:
case SD1_LSHFT_MODE: /* not working on silicon v1 */
diff --git a/arch/m68k/lib/Makefile b/arch/m68k/lib/Makefile
index 6e1fd93..5ccd954 100644
--- a/arch/m68k/lib/Makefile
+++ b/arch/m68k/lib/Makefile
@@ -8,7 +8,7 @@
lib-$(CONFIG_USE_PRIVATE_LIBGCC) += lshrdi3.o muldi3.o ashldi3.o ashrdi3.o
obj-y += bdinfo.o
-obj-$(CONFIG_CMD_BOOTM) += bootm.o
+obj-$(CONFIG_BOOTM) += bootm.o
obj-y += cache.o
obj-y += interrupts.o
obj-y += time.o
diff --git a/arch/microblaze/lib/Makefile b/arch/microblaze/lib/Makefile
index dfd8135..2f23482 100644
--- a/arch/microblaze/lib/Makefile
+++ b/arch/microblaze/lib/Makefile
@@ -3,6 +3,6 @@
# (C) Copyright 2003-2006
# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
-obj-$(CONFIG_CMD_BOOTM) += bootm.o
+obj-$(CONFIG_BOOTM) += bootm.o
obj-$(CONFIG_CMD_BDI) += bdinfo.o
obj-y += muldi3.o
diff --git a/arch/mips/Kconfig b/arch/mips/Kconfig
index f0704d9..eb7f3ad 100644
--- a/arch/mips/Kconfig
+++ b/arch/mips/Kconfig
@@ -473,12 +473,6 @@
config MIPS_TUNE_OCTEON3
bool
-config 32BIT
- bool
-
-config 64BIT
- bool
-
config SWAP_IO_SPACE
bool
diff --git a/arch/mips/lib/Makefile b/arch/mips/lib/Makefile
index 9ee1fcb..4386eb4 100644
--- a/arch/mips/lib/Makefile
+++ b/arch/mips/lib/Makefile
@@ -10,8 +10,8 @@
obj-y += stack.o
obj-y += traps.o
-obj-$(CONFIG_CMD_BOOTM) += bootm.o
+obj-$(CONFIG_BOOTM) += bootm.o
obj-$(CONFIG_CMD_GO) += boot.o
obj-$(CONFIG_SPL_BUILD) += spl.o
-lib-$(CONFIG_USE_PRIVATE_LIBGCC) += ashldi3.o ashrdi3.o lshrdi3.o
+lib-$(CONFIG_USE_PRIVATE_LIBGCC) += ashldi3.o ashrdi3.o lshrdi3.o udivdi3.o
diff --git a/arch/mips/lib/cache_init.S b/arch/mips/lib/cache_init.S
index 602741c..d64209d 100644
--- a/arch/mips/lib/cache_init.S
+++ b/arch/mips/lib/cache_init.S
@@ -431,9 +431,9 @@
#else
xor a0, a0, t0
andi a0, a0, CONF_CM_CMASK
- xor a0, a0, t0
+ xor t0, a0, t0
#endif
- mtc0 a0, CP0_CONFIG
+ mtc0 t0, CP0_CONFIG
jr.hb ra
END(change_k0_cca)
diff --git a/arch/mips/lib/udivdi3.c b/arch/mips/lib/udivdi3.c
new file mode 100644
index 0000000..4d78011
--- /dev/null
+++ b/arch/mips/lib/udivdi3.c
@@ -0,0 +1,17 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+
+#include "libgcc.h"
+
+#if BITS_PER_LONG == 32
+
+#include <div64.h>
+
+long long __udivdi3(long long u, word_type b)
+{
+ long long ret = u;
+
+ __div64_32(&ret, b);
+ return ret;
+}
+
+#endif /* BITS_PER_LONG == 32 */
diff --git a/arch/nios2/lib/Makefile b/arch/nios2/lib/Makefile
index a9f3c71..68a5ca0 100644
--- a/arch/nios2/lib/Makefile
+++ b/arch/nios2/lib/Makefile
@@ -4,5 +4,5 @@
# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
obj-y += cache.o
-obj-$(CONFIG_CMD_BOOTM) += bootm.o
+obj-$(CONFIG_BOOTM) += bootm.o
obj-y += libgcc.o
diff --git a/arch/powerpc/lib/Makefile b/arch/powerpc/lib/Makefile
index bb819dc..dcce983 100644
--- a/arch/powerpc/lib/Makefile
+++ b/arch/powerpc/lib/Makefile
@@ -34,7 +34,7 @@
endif
obj-y += reloc.o
-obj-$(CONFIG_CMD_BOOTM) += bootm.o
+obj-$(CONFIG_BOOTM) += bootm.o
obj-y += cache.o
obj-y += extable.o
obj-y += interrupts.o
diff --git a/arch/riscv/Kconfig b/arch/riscv/Kconfig
index ac52c5e..7e20ef6 100644
--- a/arch/riscv/Kconfig
+++ b/arch/riscv/Kconfig
@@ -22,6 +22,7 @@
config TARGET_QEMU_VIRT
bool "Support QEMU Virt Board"
+ select BOARD_LATE_INIT
config TARGET_SIFIVE_UNLEASHED
bool "Support SiFive Unleashed Board"
@@ -93,6 +94,7 @@
# platform-specific options below
source "arch/riscv/cpu/andesv5/Kconfig"
+source "arch/riscv/cpu/cv1800b/Kconfig"
source "arch/riscv/cpu/fu540/Kconfig"
source "arch/riscv/cpu/fu740/Kconfig"
source "arch/riscv/cpu/generic/Kconfig"
@@ -119,6 +121,26 @@
endchoice
+config FRAMEPOINTER
+ bool "Build with frame pointer for stack unwinding"
+ help
+ Choose this option to use the frame pointer so the stack can be
+ unwound if needed. This is useful for tracing where faults came
+ from as the source may be several functions back
+
+ If you say Y here, then the code size will be increased due to
+ having to store the fp.
+
+config SPL_FRAMEPOINTER
+ bool "Build SPL with frame pointer for stack unwinding"
+ help
+ Choose this option to use the frame pointer so the stack can be
+ unwound if needed. This is useful for tracing where faults came
+ from as the source may be several functions back
+
+ If you say Y here, then the code size will be increased due to
+ having to store the fp.
+
choice
prompt "Code Model"
default CMODEL_MEDLOW
@@ -288,12 +310,6 @@
config RISCV_ISA_A
def_bool y
-config 32BIT
- bool
-
-config 64BIT
- bool
-
config DMA_ADDR_T_64BIT
bool
default y if 64BIT
diff --git a/arch/riscv/Makefile b/arch/riscv/Makefile
index b3ef870..c36a853 100644
--- a/arch/riscv/Makefile
+++ b/arch/riscv/Makefile
@@ -48,6 +48,10 @@
ARCH_FLAGS = -march=$(RISCV_MARCH) -mabi=$(ABI) \
-mcmodel=$(CMODEL)
+ifeq ($(CONFIG_$(SPL_)FRAMEPOINTER),y)
+ ARCH_FLAGS += -fno-omit-frame-pointer
+endif
+
PLATFORM_CPPFLAGS += $(ARCH_FLAGS)
CFLAGS_EFI += $(ARCH_FLAGS)
diff --git a/arch/riscv/cpu/cpu.c b/arch/riscv/cpu/cpu.c
index 8445c58..affe700 100644
--- a/arch/riscv/cpu/cpu.c
+++ b/arch/riscv/cpu/cpu.c
@@ -38,24 +38,50 @@
#if CONFIG_IS_ENABLED(RISCV_MMODE)
return csr_read(CSR_MISA) & (1 << (ext - 'a'));
#elif CONFIG_CPU
+ char sext[2] = {ext};
struct udevice *dev;
- char desc[32];
- int i;
+ const char *isa;
+ int ret, i;
uclass_find_first_device(UCLASS_CPU, &dev);
if (!dev) {
debug("unable to find the RISC-V cpu device\n");
return false;
}
- if (!cpu_get_desc(dev, desc, sizeof(desc))) {
- /*
- * skip the first 4 characters (rv32|rv64) and
- * check until underscore
- */
- for (i = 4; i < sizeof(desc); i++) {
- if (desc[i] == '_' || desc[i] == '\0')
- break;
- if (desc[i] == ext)
+
+ ret = dev_read_stringlist_search(dev, "riscv,isa-extensions", sext);
+ if (ret >= 0)
+ return true;
+
+ /*
+ * Only if the property is not found (ENODATA) is the fallback to
+ * riscv,isa used, otherwise the extension is not present in this
+ * CPU.
+ */
+ if (ret != -ENODATA)
+ return false;
+
+ isa = dev_read_string(dev, "riscv,isa");
+ if (!isa)
+ return false;
+
+ /*
+ * Skip the first 4 characters (rv32|rv64).
+ */
+ for (i = 4; i < sizeof(isa); i++) {
+ switch (isa[i]) {
+ case 's':
+ case 'x':
+ case 'z':
+ case '_':
+ case '\0':
+ /*
+ * Any of these characters mean the single
+ * letter extensions have all been consumed.
+ */
+ return false;
+ default:
+ if (isa[i] == ext)
return true;
}
}
diff --git a/arch/riscv/cpu/cv1800b/Kconfig b/arch/riscv/cpu/cv1800b/Kconfig
new file mode 100644
index 0000000..7225b12
--- /dev/null
+++ b/arch/riscv/cpu/cv1800b/Kconfig
@@ -0,0 +1,12 @@
+# SPDX-License-Identifier: GPL-2.0+
+#
+# Copyright (c) 2024, Kongyang Liu <seashell11234455@gmail.com>
+
+config SOPHGO_CV1800B
+ bool
+ select ARCH_EARLY_INIT_R
+ select SYS_CACHE_SHIFT_6
+ imply CPU
+ imply CPU_RISCV
+ imply RISCV_TIMER
+ imply CMD_CPU
diff --git a/arch/riscv/cpu/cv1800b/Makefile b/arch/riscv/cpu/cv1800b/Makefile
new file mode 100644
index 0000000..95beb34
--- /dev/null
+++ b/arch/riscv/cpu/cv1800b/Makefile
@@ -0,0 +1,7 @@
+# SPDX-License-Identifier: GPL-2.0+
+#
+# Copyright (c) 2024, Kongyang Liu <seashell11234455@gmail.com>
+
+obj-y += dram.o
+obj-y += cpu.o
+obj-y += cache.o
diff --git a/arch/riscv/cpu/cv1800b/cache.c b/arch/riscv/cpu/cv1800b/cache.c
new file mode 100644
index 0000000..b8051e2
--- /dev/null
+++ b/arch/riscv/cpu/cv1800b/cache.c
@@ -0,0 +1,45 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (c) 2024, Kongyang Liu <seashell11234455@gmail.com>
+ */
+
+#include <cpu_func.h>
+
+/*
+ * dcache.ipa rs1 (invalidate)
+ * | 31 - 25 | 24 - 20 | 19 - 15 | 14 - 12 | 11 - 7 | 6 - 0 |
+ * 0000001 01010 rs1 000 00000 0001011
+ *
+ * dcache.cpa rs1 (clean)
+ * | 31 - 25 | 24 - 20 | 19 - 15 | 14 - 12 | 11 - 7 | 6 - 0 |
+ * 0000001 01001 rs1 000 00000 0001011
+ *
+ * dcache.cipa rs1 (clean then invalidate)
+ * | 31 - 25 | 24 - 20 | 19 - 15 | 14 - 12 | 11 - 7 | 6 - 0 |
+ * 0000001 01011 rs1 000 00000 0001011
+ *
+ * sync.s
+ * | 31 - 25 | 24 - 20 | 19 - 15 | 14 - 12 | 11 - 7 | 6 - 0 |
+ * 0000000 11001 00000 000 00000 0001011
+ */
+#define DCACHE_IPA_A0 ".long 0x02a5000b"
+#define DCACHE_CPA_A0 ".long 0x0295000b"
+#define DCACHE_CIPA_A0 ".long 0x02b5000b"
+
+#define SYNC_S ".long 0x0190000b"
+
+void invalidate_dcache_range(unsigned long start, unsigned long end)
+{
+ register unsigned long i asm("a0") = start & ~(CONFIG_SYS_CACHELINE_SIZE - 1);
+ for (; i < end; i += CONFIG_SYS_CACHELINE_SIZE)
+ __asm__ __volatile__(DCACHE_IPA_A0);
+ __asm__ __volatile__(SYNC_S);
+}
+
+void flush_dcache_range(unsigned long start, unsigned long end)
+{
+ register unsigned long i asm("a0") = start & ~(CONFIG_SYS_CACHELINE_SIZE - 1);
+ for (; i < end; i += CONFIG_SYS_CACHELINE_SIZE)
+ __asm__ __volatile__(DCACHE_CPA_A0);
+ __asm__ __volatile__(SYNC_S);
+}
diff --git a/arch/riscv/cpu/cv1800b/cpu.c b/arch/riscv/cpu/cv1800b/cpu.c
new file mode 100644
index 0000000..233a6a3
--- /dev/null
+++ b/arch/riscv/cpu/cv1800b/cpu.c
@@ -0,0 +1,9 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (c) 2024, Kongyang Liu <seashell11234455@gmail.com>
+ */
+
+int cleanup_before_linux(void)
+{
+ return 0;
+}
diff --git a/arch/riscv/cpu/cv1800b/dram.c b/arch/riscv/cpu/cv1800b/dram.c
new file mode 100644
index 0000000..91007c0
--- /dev/null
+++ b/arch/riscv/cpu/cv1800b/dram.c
@@ -0,0 +1,21 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2018, Bin Meng <bmeng.cn@gmail.com>
+ */
+
+#include <fdtdec.h>
+#include <init.h>
+#include <asm/global_data.h>
+#include <linux/sizes.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+int dram_init(void)
+{
+ return fdtdec_setup_mem_size_base();
+}
+
+int dram_init_banksize(void)
+{
+ return fdtdec_setup_memory_banksize();
+}
diff --git a/arch/riscv/cpu/start.S b/arch/riscv/cpu/start.S
index 6cecadf..a9e1935 100644
--- a/arch/riscv/cpu/start.S
+++ b/arch/riscv/cpu/start.S
@@ -418,6 +418,7 @@
*/
mv a0, s3 /* gd_t */
mv a1, s4 /* dest_addr */
+ mv s0, zero /* fp == NULL */
/*
* jump to it ...
diff --git a/arch/riscv/dts/cv1800b-milkv-duo.dts b/arch/riscv/dts/cv1800b-milkv-duo.dts
index 3af9e34..94e64dd 100644
--- a/arch/riscv/dts/cv1800b-milkv-duo.dts
+++ b/arch/riscv/dts/cv1800b-milkv-duo.dts
@@ -33,6 +33,14 @@
clock-frequency = <25000000>;
};
+&sdhci0 {
+ status = "okay";
+ bus-width = <4>;
+ no-1-8-v;
+ no-mmc;
+ no-sdio;
+};
+
&uart0 {
status = "okay";
};
diff --git a/arch/riscv/dts/cv1800b.dtsi b/arch/riscv/dts/cv1800b.dtsi
index 165e9e3..baf6418 100644
--- a/arch/riscv/dts/cv1800b.dtsi
+++ b/arch/riscv/dts/cv1800b.dtsi
@@ -16,3 +16,7 @@
&clint {
compatible = "sophgo,cv1800b-clint", "thead,c900-clint";
};
+
+&clk {
+ compatible = "sophgo,cv1800-clk";
+};
diff --git a/arch/riscv/dts/cv18xx.dtsi b/arch/riscv/dts/cv18xx.dtsi
index 2d6f4a4..ec99c4d 100644
--- a/arch/riscv/dts/cv18xx.dtsi
+++ b/arch/riscv/dts/cv18xx.dtsi
@@ -45,6 +45,13 @@
#clock-cells = <0>;
};
+ sdhci_clk: sdhci-clock {
+ compatible = "fixed-clock";
+ clock-frequency = <375000000>;
+ clock-output-names = "sdhci_clk";
+ #clock-cells = <0>;
+ };
+
soc {
compatible = "simple-bus";
interrupt-parent = <&plic>;
@@ -53,6 +60,12 @@
dma-noncoherent;
ranges;
+ clk: clock-controller@3002000 {
+ reg = <0x03002000 0x1000>;
+ clocks = <&osc>;
+ #clock-cells = <1>;
+ };
+
gpio0: gpio@3020000 {
compatible = "snps,dw-apb-gpio";
reg = <0x3020000 0x1000>;
@@ -175,6 +188,15 @@
status = "disabled";
};
+ sdhci0: mmc@4310000 {
+ compatible = "sophgo,cv1800b-dwcmshc";
+ reg = <0x4310000 0x1000>;
+ interrupts = <36 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&sdhci_clk>;
+ clock-names = "core";
+ status = "disabled";
+ };
+
plic: interrupt-controller@70000000 {
reg = <0x70000000 0x4000000>;
interrupts-extended = <&cpu0_intc 11>, <&cpu0_intc 9>;
diff --git a/arch/riscv/dts/fu740-c000-u-boot.dtsi b/arch/riscv/dts/fu740-c000-u-boot.dtsi
index 706224b..956237c 100644
--- a/arch/riscv/dts/fu740-c000-u-boot.dtsi
+++ b/arch/riscv/dts/fu740-c000-u-boot.dtsi
@@ -77,7 +77,7 @@
0x0 0x100b2000 0x0 0x2000
0x0 0x100b8000 0x0 0x1000>;
clocks = <&prci FU740_PRCI_CLK_DDRPLL>;
- clock-frequency = <933333324>;
+ clock-frequency = <800000004>;
bootph-pre-ram;
};
};
diff --git a/arch/riscv/dts/jh7110-starfive-visionfive-2-u-boot.dtsi b/arch/riscv/dts/jh7110-starfive-visionfive-2-u-boot.dtsi
index 5518531..3012466 100644
--- a/arch/riscv/dts/jh7110-starfive-visionfive-2-u-boot.dtsi
+++ b/arch/riscv/dts/jh7110-starfive-visionfive-2-u-boot.dtsi
@@ -112,6 +112,6 @@
u-boot-spl {
};
+ };
};
};
-};
diff --git a/arch/riscv/dts/jh7110-starfive-visionfive-2.dtsi b/arch/riscv/dts/jh7110-starfive-visionfive-2.dtsi
index f2c6bec..e11babc 100644
--- a/arch/riscv/dts/jh7110-starfive-visionfive-2.dtsi
+++ b/arch/riscv/dts/jh7110-starfive-visionfive-2.dtsi
@@ -298,7 +298,7 @@
pinctrl-0 = <&mmc1_pins>;
no-sdio;
no-mmc;
- broken-cd;
+ cd-gpios = <&sysgpio 41 GPIO_ACTIVE_LOW>;
cap-sd-highspeed;
post-power-on-delay-ms = <200>;
status = "okay";
diff --git a/arch/riscv/dts/jh7110-u-boot.dtsi b/arch/riscv/dts/jh7110-u-boot.dtsi
index 2f560e7..c09d5c9 100644
--- a/arch/riscv/dts/jh7110-u-boot.dtsi
+++ b/arch/riscv/dts/jh7110-u-boot.dtsi
@@ -93,6 +93,10 @@
bootph-pre-ram;
};
+&pllclk {
+ bootph-pre-ram;
+};
+
&S7_0 {
status = "okay";
};
diff --git a/arch/riscv/dts/xilinx-mbv32.dts b/arch/riscv/dts/xilinx-mbv32.dts
index 94e42c2..48ee115 100644
--- a/arch/riscv/dts/xilinx-mbv32.dts
+++ b/arch/riscv/dts/xilinx-mbv32.dts
@@ -8,6 +8,9 @@
*/
/dts-v1/;
+
+#include "binman.dtsi"
+
/ {
#address-cells = <1>;
#size-cells = <1>;
diff --git a/arch/riscv/include/asm/arch-jh7110/eeprom.h b/arch/riscv/include/asm/arch-jh7110/eeprom.h
index d2776d5..62d184a 100644
--- a/arch/riscv/include/asm/arch-jh7110/eeprom.h
+++ b/arch/riscv/include/asm/arch-jh7110/eeprom.h
@@ -12,4 +12,13 @@
u8 get_pcb_revision_from_eeprom(void);
u32 get_ddr_size_from_eeprom(void);
+/**
+ * get_product_id_from_eeprom - get product ID string
+ *
+ * A string like "VF7110A1-2228-D008E000-00000001" is returned.
+ *
+ * Return: product ID string
+ */
+const char *get_product_id_from_eeprom(void);
+
#endif /* _ASM_RISCV_EEPROM_H */
diff --git a/arch/riscv/lib/Makefile b/arch/riscv/lib/Makefile
index 9a05b66..0b2c88d 100644
--- a/arch/riscv/lib/Makefile
+++ b/arch/riscv/lib/Makefile
@@ -6,7 +6,7 @@
# Copyright (C) 2017 Andes Technology Corporation
# Rick Chen, Andes Technology Corporation <rick@andestech.com>
-obj-$(CONFIG_CMD_BOOTM) += bootm.o
+obj-$(CONFIG_BOOTM) += bootm.o
obj-$(CONFIG_CMD_BOOTI) += bootm.o image.o
obj-$(CONFIG_CMD_GO) += boot.o
obj-y += cache.o
diff --git a/arch/riscv/lib/interrupts.c b/arch/riscv/lib/interrupts.c
index a26ccc7..7350e2c 100644
--- a/arch/riscv/lib/interrupts.c
+++ b/arch/riscv/lib/interrupts.c
@@ -60,6 +60,40 @@
#endif
}
+#if defined(CONFIG_FRAMEPOINTER) || defined(CONFIG_SPL_FRAMEPOINTER)
+static void show_backtrace(struct pt_regs *regs)
+{
+ uintptr_t *fp = (uintptr_t *)regs->s0;
+ unsigned count = 0;
+ ulong ra;
+
+ printf("backtrace:\n");
+
+ /* there are a few entry points where the s0 register is
+ * set to gd, so to avoid changing those, just abort if
+ * the value is the same */
+ while (fp != NULL && fp != (uintptr_t *)gd) {
+ ra = fp[-1];
+ printf("backtrace %2d: FP: " REG_FMT " RA: " REG_FMT,
+ count, (ulong)fp, ra);
+
+ if (gd && gd->flags & GD_FLG_RELOC)
+ printf(" - RA: " REG_FMT " reloc adjusted\n",
+ ra - gd->reloc_off);
+ else
+ printf("\n");
+
+ fp = (uintptr_t *)fp[-2];
+ count++;
+ }
+}
+#else
+static void show_backtrace(struct pt_regs *regs)
+{
+ printf("No backtrace support enabled\n");
+}
+#endif
+
/**
* instr_len() - get instruction length
*
@@ -131,6 +165,7 @@
epc - gd->reloc_off, regs->ra - gd->reloc_off);
show_regs(regs);
+ show_backtrace(regs);
show_code(epc);
show_efi_loaded_images(epc);
panic("\n");
diff --git a/arch/sandbox/config.mk b/arch/sandbox/config.mk
index 1d50991..4058438 100644
--- a/arch/sandbox/config.mk
+++ b/arch/sandbox/config.mk
@@ -69,5 +69,3 @@
endif
EFI_CRT0 := crt0_sandbox_efi.o
EFI_RELOC := reloc_sandbox_efi.o
-AFLAGS_crt0_sandbox_efi.o += -DHOST_ARCH="$(HOST_ARCH)"
-CFLAGS_reloc_sandbox_efi.o += -DHOST_ARCH="$(HOST_ARCH)"
diff --git a/arch/sandbox/dts/sandbox.dts b/arch/sandbox/dts/sandbox.dts
index 12d3eff..8392206 100644
--- a/arch/sandbox/dts/sandbox.dts
+++ b/arch/sandbox/dts/sandbox.dts
@@ -106,3 +106,7 @@
#if IS_ENABLED(CONFIG_SUPPORT_VPL)
#include "sandbox_vpl.dtsi"
#endif
+
+#if IS_ENABLED(CONFIG_EFI_HAVE_CAPSULE_SUPPORT)
+#include "sandbox_capsule.dtsi"
+#endif
diff --git a/arch/sandbox/dts/sandbox_capsule.dtsi b/arch/sandbox/dts/sandbox_capsule.dtsi
new file mode 100644
index 0000000..34d2991
--- /dev/null
+++ b/arch/sandbox/dts/sandbox_capsule.dtsi
@@ -0,0 +1,169 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Devicetree file with binman nodes needed for generating EFI
+ * capsules.
+ *
+ */
+
+#include <sandbox_efi_capsule.h>
+
+/ {
+ binman: binman {
+ multiple-images;
+ };
+};
+
+&binman {
+ capsule1 {
+ filename = "Test01";
+ efi-capsule {
+ image-index = <0x1>;
+ image-guid = SANDBOX_UBOOT_IMAGE_GUID;
+
+ text {
+ text = "u-boot:New";
+ };
+ };
+ };
+
+ capsule2 {
+ filename = "Test02";
+ efi-capsule {
+ image-index = <0x2>;
+ image-guid = SANDBOX_UBOOT_ENV_IMAGE_GUID;
+
+ text {
+ text = "u-boot-env:New";
+ };
+ };
+ };
+
+ capsule3 {
+ filename = "Test03";
+ efi-capsule {
+ image-index = <0x1>;
+ image-guid = SANDBOX_INCORRECT_GUID;
+
+ text {
+ text = "u-boot:New";
+ };
+ };
+ };
+
+ capsule4 {
+ filename = "Test101";
+ efi-capsule {
+ image-index = <0x1>;
+ fw-version = <0x5>;
+ image-guid = SANDBOX_UBOOT_IMAGE_GUID;
+
+ text {
+ text = "u-boot:New";
+ };
+ };
+ };
+
+ capsule5 {
+ filename = "Test102";
+ efi-capsule {
+ image-index = <0x2>;
+ fw-version = <0xa>;
+ image-guid = SANDBOX_UBOOT_ENV_IMAGE_GUID;
+
+ text {
+ text = "u-boot-env:New";
+ };
+ };
+ };
+
+ capsule6 {
+ filename = "Test103";
+ efi-capsule {
+ image-index = <0x1>;
+ fw-version = <0x2>;
+ image-guid = SANDBOX_UBOOT_IMAGE_GUID;
+
+ text {
+ text = "u-boot:New";
+ };
+ };
+ };
+
+ capsule7 {
+ filename = "Test11";
+ efi-capsule {
+ image-index = <0x1>;
+ image-guid = SANDBOX_UBOOT_IMAGE_GUID;
+ private-key = CAPSULE_PRIV_KEY;
+ public-key-cert = CAPSULE_PUB_KEY;
+ monotonic-count = <0x1>;
+
+ text {
+ text = "u-boot:New";
+ };
+ };
+ };
+
+ capsule8 {
+ filename = "Test12";
+ efi-capsule {
+ image-index = <0x1>;
+ image-guid = SANDBOX_UBOOT_IMAGE_GUID;
+ private-key = CAPSULE_INVAL_KEY;
+ public-key-cert = CAPSULE_INVAL_PUB_KEY;
+ monotonic-count = <0x1>;
+
+ text {
+ text = "u-boot:New";
+ };
+ };
+ };
+
+ capsule9 {
+ filename = "Test111";
+ efi-capsule {
+ image-index = <0x1>;
+ fw-version = <0x5>;
+ image-guid = SANDBOX_UBOOT_IMAGE_GUID;
+ private-key = CAPSULE_PRIV_KEY;
+ public-key-cert = CAPSULE_PUB_KEY;
+ monotonic-count = <0x1>;
+
+ text {
+ text = "u-boot:New";
+ };
+ };
+ };
+
+ capsule10 {
+ filename = "Test112";
+ efi-capsule {
+ image-index = <0x2>;
+ fw-version = <0xa>;
+ image-guid = SANDBOX_UBOOT_ENV_IMAGE_GUID;
+ private-key = CAPSULE_PRIV_KEY;
+ public-key-cert = CAPSULE_PUB_KEY;
+ monotonic-count = <0x1>;
+
+ text {
+ text = "u-boot-env:New";
+ };
+ };
+ };
+
+ capsule11 {
+ filename = "Test113";
+ efi-capsule {
+ image-index = <0x1>;
+ fw-version = <0x2>;
+ image-guid = SANDBOX_UBOOT_IMAGE_GUID;
+ private-key = CAPSULE_PRIV_KEY;
+ public-key-cert = CAPSULE_PUB_KEY;
+ monotonic-count = <0x1>;
+
+ text {
+ text = "u-boot:New";
+ };
+ };
+ };
+};
diff --git a/arch/sandbox/dts/test.dts b/arch/sandbox/dts/test.dts
index e264b29..a012f5c 100644
--- a/arch/sandbox/dts/test.dts
+++ b/arch/sandbox/dts/test.dts
@@ -1990,4 +1990,8 @@
#include "sandbox_vpl.dtsi"
#endif
+#if IS_ENABLED(CONFIG_EFI_HAVE_CAPSULE_SUPPORT)
+#include "sandbox_capsule.dtsi"
+#endif
+
#include "cedit.dtsi"
diff --git a/arch/sandbox/lib/Makefile b/arch/sandbox/lib/Makefile
index a2bc5a7..c4924b2 100644
--- a/arch/sandbox/lib/Makefile
+++ b/arch/sandbox/lib/Makefile
@@ -7,5 +7,5 @@
obj-y += fdt_fixup.o interrupts.o sections.o
obj-$(CONFIG_PCI) += pci_io.o
-obj-$(CONFIG_CMD_BOOTM) += bootm.o
+obj-$(CONFIG_BOOTM) += bootm.o
obj-$(CONFIG_CMD_BOOTZ) += bootm.o
diff --git a/arch/sh/lib/Makefile b/arch/sh/lib/Makefile
index e7520a3..8c3c302 100644
--- a/arch/sh/lib/Makefile
+++ b/arch/sh/lib/Makefile
@@ -6,7 +6,7 @@
extra-y += start.o
obj-y += board.o
-obj-$(CONFIG_CMD_BOOTM) += bootm.o
+obj-$(CONFIG_BOOTM) += bootm.o
obj-y += time.o
obj-$(CONFIG_CMD_SH_ZIMAGEBOOT) += zimageboot.o
diff --git a/arch/x86/Kconfig b/arch/x86/Kconfig
index 99e59d9..23a1e21 100644
--- a/arch/x86/Kconfig
+++ b/arch/x86/Kconfig
@@ -723,6 +723,14 @@
hex
default 0x10000
+config X86_HARDFP
+ bool "Support hardware floating point"
+ help
+ U-Boot generally does not make use of floating point. Where this is
+ needed, it can be enabled using this option. This adjusts the
+ start-up code for 64-bit mode and changes the compiler options for
+ 64-bit to enable SSE.
+
config HAVE_ITSS
bool "Enable ITSS"
help
@@ -1053,4 +1061,12 @@
display, memory and build information. It is stored in
struct sysinfo_t after parsing by get_coreboot_info().
+config ZBOOT
+ bool "Support the zImage format"
+ default y
+ help
+ Enable this to support booting the x86-specific zImage format. This
+ uses a special, binary format containing information about the Linux
+ format to boot.
+
endmenu
diff --git a/arch/x86/config.mk b/arch/x86/config.mk
index 26ec1af..2e3a711 100644
--- a/arch/x86/config.mk
+++ b/arch/x86/config.mk
@@ -27,9 +27,13 @@
PLATFORM_CPPFLAGS += -march=i386 -m32
else
PLATFORM_CPPFLAGS += $(if $(CONFIG_SPL_BUILD),,-fpic) -fno-common -march=core2 -m64
+
+ifndef CONFIG_X86_HARDFP
PLATFORM_CPPFLAGS += -mno-mmx -mno-sse
endif
+endif # IS_32BIT
+
PLATFORM_RELFLAGS += -fdata-sections -ffunction-sections -fvisibility=hidden
KBUILD_LDFLAGS += -Bsymbolic -Bsymbolic-functions
diff --git a/arch/x86/cpu/x86_64/cpu.c b/arch/x86/cpu/x86_64/cpu.c
index 2647bff..5ea746e 100644
--- a/arch/x86/cpu/x86_64/cpu.c
+++ b/arch/x86/cpu/x86_64/cpu.c
@@ -10,6 +10,7 @@
#include <init.h>
#include <asm/cpu.h>
#include <asm/global_data.h>
+#include <asm/processor-flags.h>
DECLARE_GLOBAL_DATA_PTR;
@@ -39,11 +40,22 @@
return 0;
}
+/* enable SSE features for hardware floating point */
+static void setup_sse_features(void)
+{
+ asm ("mov %%cr4, %%rax\n" \
+ "or %0, %%rax\n" \
+ "mov %%rax, %%cr4\n" \
+ : : "i" (X86_CR4_OSFXSR | X86_CR4_OSXMMEXCPT) : "eax");
+}
+
int x86_cpu_reinit_f(void)
{
/* set the vendor to Intel so that native_calibrate_tsc() works */
gd->arch.x86_vendor = X86_VENDOR_INTEL;
gd->arch.has_mtrr = true;
+ if (IS_ENABLED(CONFIG_X86_HARDFP))
+ setup_sse_features();
return 0;
}
diff --git a/arch/x86/dts/coreboot.dts b/arch/x86/dts/coreboot.dts
index dfce7c2..b867468 100644
--- a/arch/x86/dts/coreboot.dts
+++ b/arch/x86/dts/coreboot.dts
@@ -46,6 +46,16 @@
compatible = "coreboot-fb";
};
+ bootstd {
+ compatible = "u-boot,boot-std";
+
+ theme {
+ font-size = <30>;
+ menu-inset = <3>;
+ menuitem-gap-y = <1>;
+ };
+ };
+
sysinfo {
compatible = "coreboot,sysinfo";
};
diff --git a/arch/x86/include/asm/zimage.h b/arch/x86/include/asm/zimage.h
index 655675b..8b54260 100644
--- a/arch/x86/include/asm/zimage.h
+++ b/arch/x86/include/asm/zimage.h
@@ -30,6 +30,78 @@
#define BZIMAGE_LOAD_ADDR 0x100000
#define ZIMAGE_LOAD_ADDR 0x10000
+enum {
+ ZBOOT_STATE_START = BIT(0),
+ ZBOOT_STATE_LOAD = BIT(1),
+ ZBOOT_STATE_SETUP = BIT(2),
+ ZBOOT_STATE_INFO = BIT(3),
+ ZBOOT_STATE_GO = BIT(4),
+
+ /* This one doesn't execute automatically, so stop the count before 5 */
+ ZBOOT_STATE_DUMP = BIT(5),
+ ZBOOT_STATE_COUNT = 5,
+};
+
+/**
+ * struct zboot_state - Current state of the boot
+ *
+ * @bzimage_addr: Address of the bzImage to boot, or 0 if the image has already
+ * been loaded and does not exist (as a cohesive whole) in memory
+ * @bzimage_size: Size of the bzImage, or 0 to detect this
+ * @initrd_addr: Address of the initial ramdisk, or 0 if none
+ * @initrd_size: Size of the initial ramdisk, or 0 if none
+ * @load_address: Address where the bzImage is moved before booting, either
+ * BZIMAGE_LOAD_ADDR or ZIMAGE_LOAD_ADDR
+ * This is set up when loading the zimage
+ * @base_ptr: Pointer to the boot parameters, typically at address
+ * DEFAULT_SETUP_BASE
+ * This is set up when loading the zimage
+ * @cmdline: Environment variable containing the 'override' command line, or
+ * NULL to use the one in the setup block
+ */
+struct zboot_state {
+ ulong bzimage_addr;
+ ulong bzimage_size;
+ ulong initrd_addr;
+ ulong initrd_size;
+ ulong load_address;
+ struct boot_params *base_ptr;
+ const char *cmdline;
+};
+
+extern struct zboot_state state;
+
+/**
+ * zimage_dump() - Dump information about a zimage
+ *
+ * @base_ptr: Pointer to the boot parameters
+ * @show_cmdline: true to show the kernel command line
+ */
+void zimage_dump(struct boot_params *base_ptr, bool show_cmdline);
+
+/**
+ * zboot_load() - Load a zimage
+ *
+ * Load the zimage into the correct place
+ *
+ * Return: 0 if OK, -ve on error
+ */
+int zboot_load(void);
+
+/**
+ * zboot_setup() - Set up the zboot image reeady for booting
+ *
+ * Return: 0 if OK, -ve on error
+ */
+int zboot_setup(void);
+
+/**
+ * zboot_go() - Start the image
+ *
+ * Return: 0 if OK, -ve on error
+ */
+int zboot_go(void);
+
/**
* load_zimage() - Load a zImage or bzImage
*
@@ -62,4 +134,29 @@
int setup_zimage(struct boot_params *setup_base, char *cmd_line, int auto_boot,
ulong initrd_addr, ulong initrd_size, ulong cmdline_force);
+/**
+ * zboot_start() - Prepare to boot a zimage
+ *
+ * Record information about a zimage so it can be booted
+ *
+ * @bzimage_addr: Address of the bzImage to boot
+ * @bzimage_size: Size of the bzImage, or 0 to detect this
+ * @initrd_addr: Address of the initial ramdisk, or 0 if none
+ * @initrd_size: Size of the initial ramdisk, or 0 if none
+ * @base_addr: If non-zero, this indicates that the boot parameters have already
+ * been loaded by the caller to this address, so the load_zimage() call
+ * in zboot_load() will be skipped when booting
+ * @cmdline: Environment variable containing the 'override' command line, or
+ * NULL to use the one in the setup block
+ */
+void zboot_start(ulong bzimage_addr, ulong bzimage_size, ulong initrd_addr,
+ ulong initrd_size, ulong base_addr, const char *cmdline);
+
+/**
+ * zboot_info() - Show simple info about a zimage
+ *
+ * Shows wherer the kernel was loaded and also the setup base
+ */
+void zboot_info(void);
+
#endif
diff --git a/arch/x86/lib/Makefile b/arch/x86/lib/Makefile
index 90a7618..94aa335 100644
--- a/arch/x86/lib/Makefile
+++ b/arch/x86/lib/Makefile
@@ -16,7 +16,7 @@
endif
ifndef CONFIG_SPL_BUILD
-obj-$(CONFIG_CMD_BOOTM) += bootm.o
+obj-$(CONFIG_BOOTM) += bootm.o
endif
obj-y += cmd_boot.o
obj-$(CONFIG_$(SPL_)COREBOOT_SYSINFO) += coreboot/
@@ -48,7 +48,7 @@
endif
obj-y += tables.o
ifndef CONFIG_SPL_BUILD
-obj-$(CONFIG_CMD_ZBOOT) += zimage.o
+obj-$(CONFIG_ZBOOT) += zimage.o
endif
obj-$(CONFIG_USE_HOB) += hob.o
ifndef CONFIG_TPL_BUILD
diff --git a/arch/x86/lib/acpi_nhlt.c b/arch/x86/lib/acpi_nhlt.c
index 6c8cd83..08e13fd 100644
--- a/arch/x86/lib/acpi_nhlt.c
+++ b/arch/x86/lib/acpi_nhlt.c
@@ -409,7 +409,7 @@
memcpy(header->oem_table_id, oem_table_id, oem_table_id_len);
}
header->oem_revision = oem_revision;
- memcpy(header->aslc_id, ASLC_ID, 4);
+ memcpy(header->creator_id, ASLC_ID, 4);
cur.buf = (void *)(header + 1);
cur.start = (void *)header;
diff --git a/arch/x86/lib/acpi_table.c b/arch/x86/lib/acpi_table.c
index 5ecd3d4..a568313 100644
--- a/arch/x86/lib/acpi_table.c
+++ b/arch/x86/lib/acpi_table.c
@@ -253,7 +253,7 @@
/* Fill out header fields. */
acpi_fill_header(header, "TPM2");
- memcpy(header->aslc_id, ASLC_ID, 4);
+ memcpy(header->creator_id, ASLC_ID, 4);
header->length = sizeof(struct acpi_tpm2);
header->revision = acpi_get_table_revision(ACPITAB_TPM2);
@@ -479,7 +479,7 @@
/* Fill out header fields. */
acpi_fill_header(header, "HPET");
- header->aslc_revision = ASL_REVISION;
+ header->creator_revision = ASL_REVISION;
header->length = sizeof(struct acpi_hpet);
header->revision = acpi_get_table_revision(ACPITAB_HPET);
@@ -569,8 +569,8 @@
header->revision = 4;
memcpy(header->oem_id, OEM_ID, 6);
memcpy(header->oem_table_id, OEM_TABLE_ID, 8);
- memcpy(header->aslc_id, ASLC_ID, 4);
- header->aslc_revision = 1;
+ memcpy(header->creator_id, ASLC_ID, 4);
+ header->creator_revision = 1;
fadt->x_firmware_ctrl = map_to_sysmem(facs);
fadt->x_dsdt = map_to_sysmem(dsdt);
diff --git a/arch/x86/lib/spl.c b/arch/x86/lib/spl.c
index c15f11f..4e4cf18 100644
--- a/arch/x86/lib/spl.c
+++ b/arch/x86/lib/spl.c
@@ -283,7 +283,7 @@
{
int ret;
- printf("Jumping to 64-bit U-Boot: Note many features are missing\n");
+ printf("Jumping to 64-bit U-Boot\n");
ret = cpu_jump_to_64bit_uboot(spl_image->entry_point);
debug("ret=%d\n", ret);
hang();
diff --git a/arch/x86/lib/zimage.c b/arch/x86/lib/zimage.c
index a41e1cc..d740387 100644
--- a/arch/x86/lib/zimage.c
+++ b/arch/x86/lib/zimage.c
@@ -56,41 +56,8 @@
#define COMMAND_LINE_SIZE 2048
-/**
- * struct zboot_state - Current state of the boot
- *
- * @bzimage_addr: Address of the bzImage to boot
- * @bzimage_size: Size of the bzImage, or 0 to detect this
- * @initrd_addr: Address of the initial ramdisk, or 0 if none
- * @initrd_size: Size of the initial ramdisk, or 0 if none
- * @load_address: Address where the bzImage is moved before booting, either
- * BZIMAGE_LOAD_ADDR or ZIMAGE_LOAD_ADDR
- * @base_ptr: Pointer to the boot parameters, typically at address
- * DEFAULT_SETUP_BASE
- * @cmdline: Environment variable containing the 'override' command line, or
- * NULL to use the one in the setup block
- */
-struct zboot_state {
- ulong bzimage_addr;
- ulong bzimage_size;
- ulong initrd_addr;
- ulong initrd_size;
- ulong load_address;
- struct boot_params *base_ptr;
- char *cmdline;
-} state;
-
-enum {
- ZBOOT_STATE_START = BIT(0),
- ZBOOT_STATE_LOAD = BIT(1),
- ZBOOT_STATE_SETUP = BIT(2),
- ZBOOT_STATE_INFO = BIT(3),
- ZBOOT_STATE_GO = BIT(4),
-
- /* This one doesn't execute automatically, so stop the count before 5 */
- ZBOOT_STATE_DUMP = BIT(5),
- ZBOOT_STATE_COUNT = 5,
-};
+/* Current state of the boot */
+struct zboot_state state;
static void build_command_line(char *command_line, int auto_boot)
{
@@ -400,56 +367,10 @@
return 0;
}
-static int do_zboot_start(struct cmd_tbl *cmdtp, int flag, int argc,
- char *const argv[])
-{
- const char *s;
-
- memset(&state, '\0', sizeof(state));
- if (argc >= 2) {
- /* argv[1] holds the address of the bzImage */
- s = argv[1];
- } else {
- s = env_get("fileaddr");
- }
-
- if (s)
- state.bzimage_addr = hextoul(s, NULL);
-
- if (argc >= 3) {
- /* argv[2] holds the size of the bzImage */
- state.bzimage_size = hextoul(argv[2], NULL);
- }
-
- if (argc >= 4)
- state.initrd_addr = hextoul(argv[3], NULL);
- if (argc >= 5)
- state.initrd_size = hextoul(argv[4], NULL);
- if (argc >= 6) {
- /*
- * When the base_ptr is passed in, we assume that the image is
- * already loaded at the address given by argv[1] and therefore
- * the original bzImage is somewhere else, or not accessible.
- * In any case, we don't need access to the bzImage since all
- * the processing is assumed to be done.
- *
- * So set the base_ptr to the given address, use this arg as the
- * load address and set bzimage_addr to 0 so we know that it
- * cannot be proceesed (or processed again).
- */
- state.base_ptr = (void *)hextoul(argv[5], NULL);
- state.load_address = state.bzimage_addr;
- state.bzimage_addr = 0;
- }
- if (argc >= 7)
- state.cmdline = env_get(argv[6]);
-
- return 0;
-}
-
-static int zboot_load(void)
+int zboot_load(void)
{
struct boot_params *base_ptr;
+ int ret;
if (state.base_ptr) {
struct boot_params *from = (struct boot_params *)state.base_ptr;
@@ -469,23 +390,16 @@
}
state.base_ptr = base_ptr;
- return 0;
-}
-
-static int do_zboot_load(struct cmd_tbl *cmdtp, int flag, int argc,
- char *const argv[])
-{
- if (zboot_load())
- return CMD_RET_FAILURE;
-
- if (env_set_hex("zbootbase", map_to_sysmem(state.base_ptr)) ||
- env_set_hex("zbootaddr", state.load_address))
- return CMD_RET_FAILURE;
+ ret = env_set_hex("zbootbase", map_to_sysmem(state.base_ptr));
+ if (!ret)
+ ret = env_set_hex("zbootaddr", state.load_address);
+ if (ret)
+ return ret;
return 0;
}
-static int zboot_setup(void)
+int zboot_setup(void)
{
struct boot_params *base_ptr = state.base_ptr;
int ret;
@@ -499,33 +413,7 @@
return 0;
}
-static int do_zboot_setup(struct cmd_tbl *cmdtp, int flag, int argc,
- char *const argv[])
-{
- struct boot_params *base_ptr = state.base_ptr;
-
- if (!base_ptr) {
- printf("base is not set: use 'zboot load' first\n");
- return CMD_RET_FAILURE;
- }
- if (zboot_setup()) {
- puts("Setting up boot parameters failed ...\n");
- return CMD_RET_FAILURE;
- }
-
- return 0;
-}
-
-static int do_zboot_info(struct cmd_tbl *cmdtp, int flag, int argc,
- char *const argv[])
-{
- printf("Kernel loaded at %08lx, setup_base=%p\n",
- state.load_address, state.base_ptr);
-
- return 0;
-}
-
-static int zboot_go(void)
+int zboot_go(void)
{
struct boot_params *params = state.base_ptr;
struct setup_header *hdr = ¶ms->hdr;
@@ -549,35 +437,12 @@
return ret;
}
-static int do_zboot_go(struct cmd_tbl *cmdtp, int flag, int argc,
- char *const argv[])
+int zboot_run(ulong addr, ulong size, ulong initrd, ulong initrd_size,
+ ulong base, char *cmdline)
{
int ret;
- ret = zboot_go();
- printf("Kernel returned! (err=%d)\n", ret);
-
- return CMD_RET_FAILURE;
-}
-
-int zboot_start(ulong addr, ulong size, ulong initrd, ulong initrd_size,
- ulong base, char *cmdline)
-{
- int ret;
-
- memset(&state, '\0', sizeof(state));
-
- if (base) {
- state.base_ptr = map_sysmem(base, 0);
- state.load_address = addr;
- } else {
- state.bzimage_addr = addr;
- }
- state.bzimage_size = size;
- state.initrd_addr = initrd;
- state.initrd_size = initrd_size;
- state.cmdline = cmdline;
-
+ zboot_start(addr, size, initrd, initrd_size, base, cmdline);
ret = zboot_load();
if (ret)
return log_msg_ret("ld", ret);
@@ -586,7 +451,7 @@
return log_msg_ret("set", ret);
ret = zboot_go();
if (ret)
- return log_msg_ret("set", ret);
+ return log_msg_ret("go", ret);
return -EFAULT;
}
@@ -776,97 +641,25 @@
print_num("Kernel info offset", hdr->kernel_info_offset);
}
-static int do_zboot_dump(struct cmd_tbl *cmdtp, int flag, int argc,
- char *const argv[])
+void zboot_start(ulong bzimage_addr, ulong bzimage_size, ulong initrd_addr,
+ ulong initrd_size, ulong base_addr, const char *cmdline)
{
- struct boot_params *base_ptr = state.base_ptr;
-
- if (argc > 1)
- base_ptr = (void *)hextoul(argv[1], NULL);
- if (!base_ptr) {
- printf("No zboot setup_base\n");
- return CMD_RET_FAILURE;
- }
- zimage_dump(base_ptr, true);
-
- return 0;
-}
-
-/* Note: This defines the complete_zboot() function */
-U_BOOT_SUBCMDS(zboot,
- U_BOOT_CMD_MKENT(start, 8, 1, do_zboot_start, "", ""),
- U_BOOT_CMD_MKENT(load, 1, 1, do_zboot_load, "", ""),
- U_BOOT_CMD_MKENT(setup, 1, 1, do_zboot_setup, "", ""),
- U_BOOT_CMD_MKENT(info, 1, 1, do_zboot_info, "", ""),
- U_BOOT_CMD_MKENT(go, 1, 1, do_zboot_go, "", ""),
- U_BOOT_CMD_MKENT(dump, 2, 1, do_zboot_dump, "", ""),
-)
-
-int do_zboot_states(struct cmd_tbl *cmdtp, int flag, int argc,
- char *const argv[], int state_mask)
-{
- int i;
-
- for (i = 0; i < ZBOOT_STATE_COUNT; i++) {
- struct cmd_tbl *cmd = &zboot_subcmds[i];
- int mask = 1 << i;
- int ret;
+ memset(&state, '\0', sizeof(state));
- if (mask & state_mask) {
- ret = cmd->cmd(cmd, flag, argc, argv);
- if (ret)
- return ret;
- }
+ state.bzimage_size = bzimage_size;
+ state.initrd_addr = initrd_addr;
+ state.initrd_size = initrd_size;
+ if (base_addr) {
+ state.base_ptr = map_sysmem(base_addr, 0);
+ state.load_address = bzimage_addr;
+ } else {
+ state.bzimage_addr = bzimage_addr;
}
-
- return 0;
+ state.cmdline = cmdline;
}
-int do_zboot_parent(struct cmd_tbl *cmdtp, int flag, int argc,
- char *const argv[], int *repeatable)
+void zboot_info(void)
{
- /* determine if we have a sub command */
- if (argc > 1) {
- char *endp;
-
- hextoul(argv[1], &endp);
- /*
- * endp pointing to nul means that argv[1] was just a valid
- * number, so pass it along to the normal processing
- */
- if (*endp)
- return do_zboot(cmdtp, flag, argc, argv, repeatable);
- }
-
- do_zboot_states(cmdtp, flag, argc, argv, ZBOOT_STATE_START |
- ZBOOT_STATE_LOAD | ZBOOT_STATE_SETUP |
- ZBOOT_STATE_INFO | ZBOOT_STATE_GO);
-
- return CMD_RET_FAILURE;
+ printf("Kernel loaded at %08lx, setup_base=%p\n",
+ state.load_address, state.base_ptr);
}
-
-U_BOOT_CMDREP_COMPLETE(
- zboot, 8, do_zboot_parent, "Boot bzImage",
- "[addr] [size] [initrd addr] [initrd size] [setup] [cmdline]\n"
- " addr - The optional starting address of the bzimage.\n"
- " If not set it defaults to the environment\n"
- " variable \"fileaddr\".\n"
- " size - The optional size of the bzimage. Defaults to\n"
- " zero.\n"
- " initrd addr - The address of the initrd image to use, if any.\n"
- " initrd size - The size of the initrd image to use, if any.\n"
- " setup - The address of the kernel setup region, if this\n"
- " is not at addr\n"
- " cmdline - Environment variable containing the kernel\n"
- " command line, to override U-Boot's normal\n"
- " cmdline generation\n"
- "\n"
- "Sub-commands to do part of the zboot sequence:\n"
- "\tstart [addr [arg ...]] - specify arguments\n"
- "\tload - load OS image\n"
- "\tsetup - set up table\n"
- "\tinfo - show summary info\n"
- "\tgo - start OS\n"
- "\tdump [addr] - dump info (optional address of boot params)",
- complete_zboot
-);
diff --git a/arch/xtensa/lib/Makefile b/arch/xtensa/lib/Makefile
index ad4fe32..bb9157f 100644
--- a/arch/xtensa/lib/Makefile
+++ b/arch/xtensa/lib/Makefile
@@ -3,6 +3,6 @@
# (C) Copyright 2007 - 2013 Tensilica Inc.
# (C) Copyright 2014 - 2016 Cadence Design Systems Inc.
-obj-$(CONFIG_CMD_BOOTM) += bootm.o
+obj-$(CONFIG_BOOTM) += bootm.o
obj-y += cache.o misc.o relocate.o time.o
diff --git a/board/CZ.NIC/turris_atsha_otp.c b/board/CZ.NIC/turris_atsha_otp.c
index a29fe36..85eebcd 100644
--- a/board/CZ.NIC/turris_atsha_otp.c
+++ b/board/CZ.NIC/turris_atsha_otp.c
@@ -11,6 +11,7 @@
#include <atsha204a-i2c.h>
#include "turris_atsha_otp.h"
+#include "turris_common.h"
#define TURRIS_ATSHA_OTP_VERSION 0
#define TURRIS_ATSHA_OTP_SERIAL 1
@@ -32,26 +33,6 @@
return dev;
}
-static void increment_mac(u8 *mac)
-{
- int i;
-
- for (i = 5; i >= 3; i--) {
- mac[i] += 1;
- if (mac[i])
- break;
- }
-}
-
-static void set_mac_if_invalid(int i, u8 *mac)
-{
- u8 oldmac[6];
-
- if (is_valid_ethaddr(mac) &&
- !eth_env_get_enetaddr_by_index("eth", i, oldmac))
- eth_env_set_enetaddr_by_index("eth", i, mac);
-}
-
int turris_atsha_otp_init_mac_addresses(int first_idx)
{
struct udevice *dev = get_atsha204a_dev();
@@ -84,11 +65,7 @@
mac[4] = mac1[2];
mac[5] = mac1[3];
- set_mac_if_invalid((first_idx + 0) % 3, mac);
- increment_mac(mac);
- set_mac_if_invalid((first_idx + 1) % 3, mac);
- increment_mac(mac);
- set_mac_if_invalid((first_idx + 2) % 3, mac);
+ turris_init_mac_addresses(first_idx, mac);
return 0;
}
diff --git a/board/CZ.NIC/turris_common.c b/board/CZ.NIC/turris_common.c
new file mode 100644
index 0000000..1717dda
--- /dev/null
+++ b/board/CZ.NIC/turris_common.c
@@ -0,0 +1,42 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2017 Marek Behún <kabel@kernel.org>
+ */
+
+#include <env.h>
+#include <net.h>
+
+#include "turris_common.h"
+
+static void increment_mac(u8 *mac)
+{
+ int i;
+
+ for (i = 5; i >= 3; i--) {
+ mac[i] += 1;
+ if (mac[i])
+ break;
+ }
+}
+
+static void set_mac_if_invalid(int i, u8 *mac)
+{
+ u8 oldmac[6];
+
+ if (is_valid_ethaddr(mac) &&
+ !eth_env_get_enetaddr_by_index("eth", i, oldmac))
+ eth_env_set_enetaddr_by_index("eth", i, mac);
+}
+
+void turris_init_mac_addresses(int first_idx, const u8 *first_mac)
+{
+ u8 mac[6];
+
+ memcpy(mac, first_mac, sizeof(mac));
+
+ set_mac_if_invalid((first_idx + 0) % 3, mac);
+ increment_mac(mac);
+ set_mac_if_invalid((first_idx + 1) % 3, mac);
+ increment_mac(mac);
+ set_mac_if_invalid((first_idx + 2) % 3, mac);
+}
diff --git a/board/CZ.NIC/turris_common.h b/board/CZ.NIC/turris_common.h
new file mode 100644
index 0000000..5565ea9
--- /dev/null
+++ b/board/CZ.NIC/turris_common.h
@@ -0,0 +1,10 @@
+// SPDX-License-Identifier: GPL-2.0+
+
+#ifndef TURRIS_COMMON_H
+#define TURRIS_COMMON_H
+
+#include <asm/types.h>
+
+void turris_init_mac_addresses(int first_idx, const u8 *first_mac);
+
+#endif
diff --git a/board/CZ.NIC/turris_mox/turris_mox.c b/board/CZ.NIC/turris_mox/turris_mox.c
index 3489bdd..1a2f60e 100644
--- a/board/CZ.NIC/turris_mox/turris_mox.c
+++ b/board/CZ.NIC/turris_mox/turris_mox.c
@@ -565,13 +565,10 @@
int checkboard(void)
{
int i, ret, board_version, ram_size, is_sd;
- const char *pub_key, *model;
+ const char *pub_key;
const u8 *topology;
u64 serial_number;
- model = fdt_getprop(gd->fdt_blob, 0, "model", NULL);
- printf("Model: %s\n", model);
-
ret = mbox_sp_get_board_info(&serial_number, NULL, NULL, &board_version,
&ram_size, NULL);
if (ret < 0) {
diff --git a/board/CZ.NIC/turris_omnia/Makefile b/board/CZ.NIC/turris_omnia/Makefile
index dc39b44..341378b 100644
--- a/board/CZ.NIC/turris_omnia/Makefile
+++ b/board/CZ.NIC/turris_omnia/Makefile
@@ -2,4 +2,4 @@
#
# Copyright (C) 2017 Marek Behún <kabel@kernel.org>
-obj-y := turris_omnia.o ../turris_atsha_otp.o
+obj-y := turris_omnia.o ../turris_atsha_otp.o ../turris_common.o
diff --git a/board/CZ.NIC/turris_omnia/turris_omnia.c b/board/CZ.NIC/turris_omnia/turris_omnia.c
index adeb69a..3b7a71b 100644
--- a/board/CZ.NIC/turris_omnia/turris_omnia.c
+++ b/board/CZ.NIC/turris_omnia/turris_omnia.c
@@ -18,18 +18,22 @@
#include <asm/io.h>
#include <asm/arch/cpu.h>
#include <asm/arch/soc.h>
+#include <asm/unaligned.h>
#include <dm/uclass.h>
#include <dt-bindings/gpio/gpio.h>
#include <fdt_support.h>
#include <hexdump.h>
#include <time.h>
+#include <turris-omnia-mcu-interface.h>
#include <linux/bitops.h>
+#include <linux/bitrev.h>
#include <linux/delay.h>
#include <u-boot/crc.h>
#include "../drivers/ddr/marvell/a38x/ddr3_init.h"
#include <../serdes/a38x/high_speed_env_spec.h>
#include "../turris_atsha_otp.h"
+#include "../turris_common.h"
DECLARE_GLOBAL_DATA_PTR;
@@ -59,46 +63,6 @@
#define A385_WD_RSTOUT_UNMASK MVEBU_REGISTER(0x20704)
#define A385_WD_RSTOUT_UNMASK_GLOBAL BIT(8)
-enum mcu_commands {
- CMD_GET_STATUS_WORD = 0x01,
- CMD_GET_RESET = 0x09,
- CMD_GET_FW_VERSION_APP = 0x0a,
- CMD_WATCHDOG_STATE = 0x0b,
- CMD_GET_FW_VERSION_BOOT = 0x0e,
-
- /* available if STS_FEATURES_SUPPORTED bit set in status word */
- CMD_GET_FEATURES = 0x10,
-
- /* available if EXT_CMD bit set in features */
- CMD_EXT_CONTROL = 0x12,
-};
-
-enum status_word_bits {
- STS_MCU_TYPE_MASK = GENMASK(1, 0),
- STS_MCU_TYPE_STM32 = 0,
- STS_MCU_TYPE_GD32 = 1,
- STS_MCU_TYPE_MKL = 2,
- STS_MCU_TYPE_UNKN = 3,
- STS_FEATURES_SUPPORTED = BIT(2),
- CARD_DET_STSBIT = 0x0010,
- MSATA_IND_STSBIT = 0x0020,
-};
-
-/* CMD_GET_FEATURES */
-enum features_e {
- FEAT_PERIPH_MCU = BIT(0),
- FEAT_EXT_CMDS = BIT(1),
-};
-
-/* CMD_EXT_CONTROL */
-enum ext_ctl_e {
- EXT_CTL_nRES_LAN = BIT(1),
- EXT_CTL_nRES_PHY = BIT(2),
- EXT_CTL_nPERST0 = BIT(3),
- EXT_CTL_nPERST1 = BIT(4),
- EXT_CTL_nPERST2 = BIT(5),
-};
-
/*
* Those values and defines are taken from the Marvell U-Boot version
* "u-boot-2013.01-2014_T3.0"
@@ -172,6 +136,141 @@
return dm_i2c_write(chip, cmd, buf, len);
}
+static int omnia_mcu_get_sts_and_features(u16 *psts, u32 *pfeatures)
+{
+ u16 sts, feat16;
+ int ret;
+
+ ret = omnia_mcu_read(CMD_GET_STATUS_WORD, &sts, sizeof(sts));
+ if (ret)
+ return ret;
+
+ if (psts)
+ *psts = sts;
+
+ if (!pfeatures)
+ return 0;
+
+ if (sts & STS_FEATURES_SUPPORTED) {
+ /* try read 32-bit features */
+ ret = omnia_mcu_read(CMD_GET_FEATURES, pfeatures,
+ sizeof(*pfeatures));
+ if (ret) {
+ /* try read 16-bit features */
+ ret = omnia_mcu_read(CMD_GET_FEATURES, &feat16,
+ sizeof(&feat16));
+ if (ret)
+ return ret;
+
+ *pfeatures = feat16;
+ } else {
+ if (*pfeatures & FEAT_FROM_BIT_16_INVALID)
+ *pfeatures &= GENMASK(15, 0);
+ }
+ } else {
+ *pfeatures = 0;
+ }
+
+ return 0;
+}
+
+static int omnia_mcu_get_sts(u16 *sts)
+{
+ return omnia_mcu_get_sts_and_features(sts, NULL);
+}
+
+static bool omnia_mcu_has_feature(u32 feature)
+{
+ u32 features;
+
+ if (omnia_mcu_get_sts_and_features(NULL, &features))
+ return false;
+
+ return feature & features;
+}
+
+static u32 omnia_mcu_crc32(const void *p, size_t len)
+{
+ u32 val, crc = 0;
+
+ compiletime_assert(!(len % 4), "length has to be a multiple of 4");
+
+ while (len) {
+ val = bitrev32(get_unaligned_le32(p));
+ crc = crc32(crc, (void *)&val, 4);
+ p += 4;
+ len -= 4;
+ }
+
+ return ~bitrev32(crc);
+}
+
+/* Can only be called after relocation, since it needs cleared BSS */
+static int omnia_mcu_board_info(char *serial, u8 *mac, char *version)
+{
+ static u8 reply[17];
+ static bool cached;
+
+ if (!cached) {
+ u8 csum;
+ int ret;
+
+ ret = omnia_mcu_read(CMD_BOARD_INFO_GET, reply, sizeof(reply));
+ if (ret)
+ return ret;
+
+ if (reply[0] != 16)
+ return -EBADMSG;
+
+ csum = reply[16];
+ reply[16] = 0;
+
+ if ((omnia_mcu_crc32(&reply[1], 16) & 0xff) != csum)
+ return -EBADMSG;
+
+ cached = true;
+ }
+
+ if (serial) {
+ const char *serial_env;
+
+ serial_env = env_get("serial#");
+ if (serial_env && strlen(serial_env) == 16) {
+ strcpy(serial, serial_env);
+ } else {
+ sprintf(serial, "%016llX",
+ get_unaligned_le64(&reply[1]));
+ env_set("serial#", serial);
+ }
+ }
+
+ if (mac)
+ memcpy(mac, &reply[9], ETH_ALEN);
+
+ if (version)
+ sprintf(version, "%u", reply[15]);
+
+ return 0;
+}
+
+static int omnia_mcu_get_board_public_key(char pub_key[static 67])
+{
+ u8 reply[34];
+ int ret;
+
+ ret = omnia_mcu_read(CMD_CRYPTO_GET_PUBLIC_KEY, reply, sizeof(reply));
+ if (ret)
+ return ret;
+
+ if (reply[0] != 33)
+ return -EBADMSG;
+
+ bin2hex(pub_key, &reply[1], 33);
+ pub_key[66] = '\0';
+
+ return 0;
+}
+
static void enable_a385_watchdog(unsigned int timeout_minutes)
{
struct sar_freq_modes sar_freq;
@@ -219,7 +318,7 @@
puts("Disabling MCU watchdog... ");
- ret = omnia_mcu_write(CMD_WATCHDOG_STATE, "\x00", 1);
+ ret = omnia_mcu_write(CMD_SET_WATCHDOG_STATE, "\x00", 1);
if (ret) {
printf("omnia_mcu_write failed: %i\n", ret);
return false;
@@ -233,7 +332,7 @@
static bool omnia_detect_sata(const char *msata_slot)
{
int ret;
- u16 stsword;
+ u16 sts;
puts("MiniPCIe/mSATA card detection... ");
@@ -249,24 +348,24 @@
}
}
- ret = omnia_mcu_read(CMD_GET_STATUS_WORD, &stsword, sizeof(stsword));
+ ret = omnia_mcu_get_sts(&sts);
if (ret) {
printf("omnia_mcu_read failed: %i, defaulting to MiniPCIe card\n",
ret);
return false;
}
- if (!(stsword & CARD_DET_STSBIT)) {
+ if (!(sts & STS_CARD_DET)) {
puts("none\n");
return false;
}
- if (stsword & MSATA_IND_STSBIT)
+ if (sts & STS_MSATA_IND)
puts("mSATA\n");
else
puts("MiniPCIe\n");
- return stsword & MSATA_IND_STSBIT ? true : false;
+ return sts & STS_MSATA_IND;
}
static bool omnia_detect_wwan_usb3(const char *wwan_slot)
@@ -393,32 +492,33 @@
static const char * const omnia_get_mcu_type(void)
{
- static const char * const mcu_types[] = {
- [STS_MCU_TYPE_STM32] = "STM32",
- [STS_MCU_TYPE_GD32] = "GD32",
- [STS_MCU_TYPE_MKL] = "MKL",
- [STS_MCU_TYPE_UNKN] = "unknown",
- };
- static const char * const mcu_types_with_perip_resets[] = {
- [STS_MCU_TYPE_STM32] = "STM32 (with peripheral resets)",
- [STS_MCU_TYPE_GD32] = "GD32 (with peripheral resets)",
- [STS_MCU_TYPE_MKL] = "MKL (with peripheral resets)",
- [STS_MCU_TYPE_UNKN] = "unknown (with peripheral resets)",
- };
- u16 stsword, features;
+ static char result[] = "xxxxxxx (with peripheral resets)";
+ u16 sts;
int ret;
- ret = omnia_mcu_read(CMD_GET_STATUS_WORD, &stsword, sizeof(stsword));
+ ret = omnia_mcu_get_sts(&sts);
if (ret)
return "unknown";
- if (stsword & STS_FEATURES_SUPPORTED) {
- ret = omnia_mcu_read(CMD_GET_FEATURES, &features, sizeof(features));
- if (ret == 0 && (features & FEAT_PERIPH_MCU))
- return mcu_types_with_perip_resets[stsword & STS_MCU_TYPE_MASK];
+ switch (sts & STS_MCU_TYPE_MASK) {
+ case STS_MCU_TYPE_STM32:
+ strcpy(result, "STM32");
+ break;
+ case STS_MCU_TYPE_GD32:
+ strcpy(result, "GD32");
+ break;
+ case STS_MCU_TYPE_MKL:
+ strcpy(result, "MKL");
+ break;
+ default:
+ strcpy(result, "unknown");
+ break;
}
- return mcu_types[stsword & STS_MCU_TYPE_MASK];
+ if (omnia_mcu_has_feature(FEAT_PERIPH_MCU))
+ strcat(result, " (with peripheral resets)");
+
+ return result;
}
static const char * const omnia_get_mcu_version(void)
@@ -695,9 +795,6 @@
void spl_board_init(void)
{
- u16 val;
- int ret;
-
/*
* If booting from UART, disable MCU watchdog in SPL, since uploading
* U-Boot proper can take too much time and trigger it. Instead enable
@@ -714,12 +811,8 @@
* resets then LAN eth switch is initialized automatically by bootstrap
* pins when A385 is released from the reset.
*/
- ret = omnia_mcu_read(CMD_GET_STATUS_WORD, &val, sizeof(val));
- if (ret == 0 && (val & STS_FEATURES_SUPPORTED)) {
- ret = omnia_mcu_read(CMD_GET_FEATURES, &val, sizeof(val));
- if (ret == 0 && (val & FEAT_PERIPH_MCU))
- initialize_switch();
- }
+ if (omnia_mcu_has_feature(FEAT_PERIPH_MCU))
+ initialize_switch();
}
#if IS_ENABLED(CONFIG_OF_BOARD_FIXUP) || IS_ENABLED(CONFIG_OF_BOARD_SETUP)
@@ -914,26 +1007,40 @@
return 0;
}
+static void fixup_atsha_node(void *blob)
+{
+ int node;
+
+ if (!omnia_mcu_has_feature(FEAT_CRYPTO))
+ return;
+
+ node = fdt_node_offset_by_compatible(blob, -1, "atmel,atsha204a");
+ if (node < 0) {
+ printf("Cannot find ATSHA204A node!\n");
+ return;
+ }
+
+ if (fdt_status_disabled(blob, node) < 0)
+ printf("Cannot disable ATSHA204A node!\n");
+ else
+ debug("Disabled ATSHA204A node\n");
+}
+
#endif
#if IS_ENABLED(CONFIG_OF_BOARD_FIXUP)
int board_fix_fdt(void *blob)
{
- u16 val;
- int ret;
-
- ret = omnia_mcu_read(CMD_GET_STATUS_WORD, &val, sizeof(val));
- if (ret == 0 && (val & STS_FEATURES_SUPPORTED)) {
- ret = omnia_mcu_read(CMD_GET_FEATURES, &val, sizeof(val));
- if (ret == 0 && (val & FEAT_PERIPH_MCU)) {
- fixup_mcu_gpio_in_pcie_nodes(blob);
- fixup_mcu_gpio_in_eth_wan_node(blob);
- }
+ if (omnia_mcu_has_feature(FEAT_PERIPH_MCU)) {
+ fixup_mcu_gpio_in_pcie_nodes(blob);
+ fixup_mcu_gpio_in_eth_wan_node(blob);
}
fixup_msata_port_nodes(blob);
fixup_wwan_port_nodes(blob);
+ fixup_atsha_node(blob);
+
return 0;
}
#endif
@@ -964,23 +1071,46 @@
int checkboard(void)
{
- char serial[17];
+ char serial[17], version[4], pub_key[67];
+ bool has_version;
int err;
- err = turris_atsha_otp_get_serial_number(serial);
- printf("Model: Turris Omnia\n");
printf(" MCU type: %s\n", omnia_get_mcu_type());
printf(" MCU version: %s\n", omnia_get_mcu_version());
printf(" RAM size: %i MiB\n", omnia_get_ram_size_gb() * 1024);
+
+ if (omnia_mcu_has_feature(FEAT_BOARD_INFO)) {
+ err = omnia_mcu_board_info(serial, NULL, version);
+ has_version = !err;
+ } else {
+ err = turris_atsha_otp_get_serial_number(serial);
+ has_version = false;
+ }
+
+ printf(" Board version: %s\n", has_version ? version : "unknown");
printf(" Serial Number: %s\n", !err ? serial : "unknown");
+ if (omnia_mcu_has_feature(FEAT_CRYPTO)) {
+ err = omnia_mcu_get_board_public_key(pub_key);
+ printf(" ECDSA Public Key: %s\n", !err ? pub_key : "unknown");
+ }
+
return 0;
}
int misc_init_r(void)
{
- turris_atsha_otp_init_mac_addresses(1);
- turris_atsha_otp_init_serial_number();
+ if (omnia_mcu_has_feature(FEAT_BOARD_INFO)) {
+ char serial[17];
+ u8 first_mac[6];
+
+ if (!omnia_mcu_board_info(serial, first_mac, NULL))
+ turris_init_mac_addresses(1, first_mac);
+ } else {
+ turris_atsha_otp_init_mac_addresses(1);
+ turris_atsha_otp_init_serial_number();
+ }
+
return 0;
}
@@ -1102,6 +1232,8 @@
fixup_msata_port_nodes(blob);
fixup_wwan_port_nodes(blob);
+ fixup_atsha_node(blob);
+
return 0;
}
#endif
diff --git a/board/advantech/imx8qm_dmsse20_a1/imx8qm_dmsse20_a1.c b/board/advantech/imx8qm_dmsse20_a1/imx8qm_dmsse20_a1.c
index 8b4d730..56b7bdb 100644
--- a/board/advantech/imx8qm_dmsse20_a1/imx8qm_dmsse20_a1.c
+++ b/board/advantech/imx8qm_dmsse20_a1/imx8qm_dmsse20_a1.c
@@ -136,17 +136,6 @@
puts("\nDDR ");
}
-/*
- * Board specific reset that is system reset.
- */
-void reset_cpu(void)
-{
- puts("SCI reboot request");
-
- while (1)
- putc('.');
-}
-
#ifdef CONFIG_OF_BOARD_SETUP
int ft_board_setup(void *blob, struct bd_info *bd)
{
diff --git a/board/advantech/imx8qm_rom7720_a1/imx8qm_rom7720_a1.c b/board/advantech/imx8qm_rom7720_a1/imx8qm_rom7720_a1.c
index 206ce7d..7f766a6 100644
--- a/board/advantech/imx8qm_rom7720_a1/imx8qm_rom7720_a1.c
+++ b/board/advantech/imx8qm_rom7720_a1/imx8qm_rom7720_a1.c
@@ -112,14 +112,6 @@
return 0;
}
-/*
- * Board specific reset that is system reset.
- */
-void reset_cpu(void)
-{
- /* TODO */
-}
-
int board_mmc_get_env_dev(int devno)
{
return devno;
diff --git a/board/amlogic/beelink-s922x/beelink-s922x.c b/board/amlogic/beelink-s922x/beelink-s922x.c
index adae27f..c277631 100644
--- a/board/amlogic/beelink-s922x/beelink-s922x.c
+++ b/board/amlogic/beelink-s922x/beelink-s922x.c
@@ -20,7 +20,7 @@
int misc_init_r(void)
{
- u8 mac_addr[MAC_ADDR_LEN];
+ u8 mac_addr[MAC_ADDR_LEN + 1];
char efuse_mac_addr[EFUSE_MAC_SIZE], tmp[3];
ssize_t len;
@@ -41,6 +41,7 @@
tmp[2] = '\0';
mac_addr[i] = hextoul(tmp, NULL);
}
+ mac_addr[MAC_ADDR_LEN] = '\0';
if (is_valid_ethaddr(mac_addr))
eth_env_set_enetaddr("ethaddr", mac_addr);
diff --git a/board/amlogic/jethub-j100/MAINTAINERS b/board/amlogic/jethub-j100/MAINTAINERS
index 43f6a5f..3edc5d8 100644
--- a/board/amlogic/jethub-j100/MAINTAINERS
+++ b/board/amlogic/jethub-j100/MAINTAINERS
@@ -1,5 +1,5 @@
JetHome JetHub
-M: Vyacheslav Bocharov <adeep@lexina.in>
+M: Viacheslav Bocharov <adeep@lexina.in>
S: Maintained
L: u-boot-amlogic@groups.io
F: board/amlogic/jethub-j100/
diff --git a/board/amlogic/jethub-j100/jethub-j100.c b/board/amlogic/jethub-j100/jethub-j100.c
index 6a2c4ad..010fc0d 100644
--- a/board/amlogic/jethub-j100/jethub-j100.c
+++ b/board/amlogic/jethub-j100/jethub-j100.c
@@ -17,7 +17,7 @@
int misc_init_r(void)
{
- u8 mac_addr[ARP_HLEN];
+ u8 mac_addr[ARP_HLEN + 1];
char serial[SM_SERIAL_SIZE];
u32 sid;
@@ -34,6 +34,7 @@
mac_addr[3] = (sid >> 16) & 0xff;
mac_addr[4] = (sid >> 8) & 0xff;
mac_addr[5] = (sid >> 0) & 0xff;
+ mac_addr[ARP_HLEN] = '\0';
eth_env_set_enetaddr("ethaddr", mac_addr);
}
diff --git a/board/amlogic/jethub-j80/jethub-j80.c b/board/amlogic/jethub-j80/jethub-j80.c
index 185880d..0b78166 100644
--- a/board/amlogic/jethub-j80/jethub-j80.c
+++ b/board/amlogic/jethub-j80/jethub-j80.c
@@ -27,9 +27,9 @@
int misc_init_r(void)
{
- u8 mac_addr[EFUSE_MAC_SIZE];
- char serial[EFUSE_SN_SIZE];
- char usid[EFUSE_USID_SIZE];
+ u8 mac_addr[EFUSE_MAC_SIZE + 1];
+ char serial[EFUSE_SN_SIZE + 1];
+ char usid[EFUSE_USID_SIZE + 1];
ssize_t len;
unsigned int adcval;
int ret;
@@ -37,6 +37,7 @@
if (!eth_env_get_enetaddr("ethaddr", mac_addr)) {
len = meson_sm_read_efuse(EFUSE_MAC_OFFSET,
mac_addr, EFUSE_MAC_SIZE);
+ mac_addr[len] = '\0';
if (len == EFUSE_MAC_SIZE && is_valid_ethaddr(mac_addr))
eth_env_set_enetaddr("ethaddr", mac_addr);
else
@@ -46,6 +47,7 @@
if (!env_get("serial")) {
len = meson_sm_read_efuse(EFUSE_SN_OFFSET, serial,
EFUSE_SN_SIZE);
+ serial[len] = '\0';
if (len == EFUSE_SN_SIZE)
env_set("serial", serial);
}
@@ -53,6 +55,7 @@
if (!env_get("usid")) {
len = meson_sm_read_efuse(EFUSE_USID_OFFSET, usid,
EFUSE_USID_SIZE);
+ usid[len] = '\0';
if (len == EFUSE_USID_SIZE)
env_set("usid", usid);
}
diff --git a/board/amlogic/odroid-n2/odroid-n2.c b/board/amlogic/odroid-n2/odroid-n2.c
index 2135457..a4bcc62 100644
--- a/board/amlogic/odroid-n2/odroid-n2.c
+++ b/board/amlogic/odroid-n2/odroid-n2.c
@@ -107,7 +107,7 @@
int misc_init_r(void)
{
- u8 mac_addr[MAC_ADDR_LEN];
+ u8 mac_addr[MAC_ADDR_LEN + 1];
char efuse_mac_addr[EFUSE_MAC_SIZE], tmp[3];
ssize_t len;
@@ -128,6 +128,7 @@
tmp[2] = '\0';
mac_addr[i] = hextoul(tmp, NULL);
}
+ mac_addr[MAC_ADDR_LEN] = '\0';
if (is_valid_ethaddr(mac_addr))
eth_env_set_enetaddr("ethaddr", mac_addr);
diff --git a/board/amlogic/p200/p200.c b/board/amlogic/p200/p200.c
index 7c432f9..754242e 100644
--- a/board/amlogic/p200/p200.c
+++ b/board/amlogic/p200/p200.c
@@ -21,20 +21,24 @@
int misc_init_r(void)
{
- u8 mac_addr[EFUSE_MAC_SIZE];
- char serial[EFUSE_SN_SIZE];
+ u8 mac_addr[EFUSE_MAC_SIZE + 1];
+ char serial[EFUSE_SN_SIZE + 1];
ssize_t len;
if (!eth_env_get_enetaddr("ethaddr", mac_addr)) {
len = meson_sm_read_efuse(EFUSE_MAC_OFFSET,
mac_addr, EFUSE_MAC_SIZE);
+ mac_addr[len] = '\0';
if (len == EFUSE_MAC_SIZE && is_valid_ethaddr(mac_addr))
eth_env_set_enetaddr("ethaddr", mac_addr);
+ else
+ meson_generate_serial_ethaddr();
}
if (!env_get("serial#")) {
len = meson_sm_read_efuse(EFUSE_SN_OFFSET, serial,
EFUSE_SN_SIZE);
+ serial[len] = '\0';
if (len == EFUSE_SN_SIZE)
env_set("serial#", serial);
}
diff --git a/board/amlogic/p201/p201.c b/board/amlogic/p201/p201.c
index 7c432f9..769e273 100644
--- a/board/amlogic/p201/p201.c
+++ b/board/amlogic/p201/p201.c
@@ -21,13 +21,14 @@
int misc_init_r(void)
{
- u8 mac_addr[EFUSE_MAC_SIZE];
- char serial[EFUSE_SN_SIZE];
+ u8 mac_addr[EFUSE_MAC_SIZE + 1];
+ char serial[EFUSE_SN_SIZE + 1];
ssize_t len;
if (!eth_env_get_enetaddr("ethaddr", mac_addr)) {
len = meson_sm_read_efuse(EFUSE_MAC_OFFSET,
mac_addr, EFUSE_MAC_SIZE);
+ mac_addr[len] = '\0';
if (len == EFUSE_MAC_SIZE && is_valid_ethaddr(mac_addr))
eth_env_set_enetaddr("ethaddr", mac_addr);
}
@@ -35,6 +36,7 @@
if (!env_get("serial#")) {
len = meson_sm_read_efuse(EFUSE_SN_OFFSET, serial,
EFUSE_SN_SIZE);
+ serial[len] = '\0';
if (len == EFUSE_SN_SIZE)
env_set("serial#", serial);
}
diff --git a/board/amlogic/p212/p212.c b/board/amlogic/p212/p212.c
index fcef90b..f6e60ae 100644
--- a/board/amlogic/p212/p212.c
+++ b/board/amlogic/p212/p212.c
@@ -22,13 +22,14 @@
int misc_init_r(void)
{
- u8 mac_addr[EFUSE_MAC_SIZE];
- char serial[EFUSE_SN_SIZE];
+ u8 mac_addr[EFUSE_MAC_SIZE + 1];
+ char serial[EFUSE_SN_SIZE + 1];
ssize_t len;
if (!eth_env_get_enetaddr("ethaddr", mac_addr)) {
len = meson_sm_read_efuse(EFUSE_MAC_OFFSET,
mac_addr, EFUSE_MAC_SIZE);
+ mac_addr[len] = '\0';
if (len == EFUSE_MAC_SIZE && is_valid_ethaddr(mac_addr))
eth_env_set_enetaddr("ethaddr", mac_addr);
else
@@ -38,6 +39,7 @@
if (!env_get("serial#")) {
len = meson_sm_read_efuse(EFUSE_SN_OFFSET, serial,
EFUSE_SN_SIZE);
+ serial[len] = '\0';
if (len == EFUSE_SN_SIZE)
env_set("serial#", serial);
}
diff --git a/board/amlogic/q200/q200.c b/board/amlogic/q200/q200.c
index 3aa6d8f..47f1566 100644
--- a/board/amlogic/q200/q200.c
+++ b/board/amlogic/q200/q200.c
@@ -22,13 +22,14 @@
int misc_init_r(void)
{
- u8 mac_addr[EFUSE_MAC_SIZE];
- char serial[EFUSE_SN_SIZE];
+ u8 mac_addr[EFUSE_MAC_SIZE + 1];
+ char serial[EFUSE_SN_SIZE + 1];
ssize_t len;
if (!eth_env_get_enetaddr("ethaddr", mac_addr)) {
len = meson_sm_read_efuse(EFUSE_MAC_OFFSET,
mac_addr, EFUSE_MAC_SIZE);
+ mac_addr[len] = '\0';
if (len == EFUSE_MAC_SIZE && is_valid_ethaddr(mac_addr))
eth_env_set_enetaddr("ethaddr", mac_addr);
else
@@ -38,6 +39,7 @@
if (!env_get("serial#")) {
len = meson_sm_read_efuse(EFUSE_SN_OFFSET, serial,
EFUSE_SN_SIZE);
+ serial[len] = '\0';
if (len == EFUSE_SN_SIZE)
env_set("serial#", serial);
}
diff --git a/board/amlogic/vim3/vim3.c b/board/amlogic/vim3/vim3.c
index 8bdfb30..43d7a8e 100644
--- a/board/amlogic/vim3/vim3.c
+++ b/board/amlogic/vim3/vim3.c
@@ -151,7 +151,7 @@
int misc_init_r(void)
{
- u8 mac_addr[MAC_ADDR_LEN];
+ u8 mac_addr[MAC_ADDR_LEN + 1];
char efuse_mac_addr[EFUSE_MAC_SIZE], tmp[3];
char serial_string[EFUSE_MAC_SIZE + 1];
ssize_t len;
@@ -169,6 +169,7 @@
tmp[2] = '\0';
mac_addr[i] = hextoul(tmp, NULL);
}
+ mac_addr[MAC_ADDR_LEN] = '\0';
if (is_valid_ethaddr(mac_addr))
eth_env_set_enetaddr("ethaddr", mac_addr);
diff --git a/board/anbernic/rgxx3_rk3566/Kconfig b/board/anbernic/rgxx3_rk3566/Kconfig
index 6743a28..b5ee67c 100644
--- a/board/anbernic/rgxx3_rk3566/Kconfig
+++ b/board/anbernic/rgxx3_rk3566/Kconfig
@@ -9,7 +9,4 @@
config SYS_CONFIG_NAME
default "anbernic-rgxx3-rk3566"
-config BOARD_SPECIFIC_OPTIONS
- def_bool y
-
endif
diff --git a/board/anbernic/rgxx3_rk3566/rgxx3-rk3566.c b/board/anbernic/rgxx3_rk3566/rgxx3-rk3566.c
index d05502f..099eea6 100644
--- a/board/anbernic/rgxx3_rk3566/rgxx3-rk3566.c
+++ b/board/anbernic/rgxx3_rk3566/rgxx3-rk3566.c
@@ -6,12 +6,14 @@
#include <abuf.h>
#include <adc.h>
#include <asm/io.h>
+#include <command.h>
#include <display.h>
#include <dm.h>
#include <dm/lists.h>
#include <env.h>
#include <fdt_support.h>
#include <linux/delay.h>
+#include <linux/iopoll.h>
#include <mipi_dsi.h>
#include <mmc.h>
#include <panel.h>
@@ -19,6 +21,8 @@
#include <stdlib.h>
#include <video_bridge.h>
+#define BOOT_BROM_DOWNLOAD 0xef08a53c
+
#define GPIO0_BASE 0xfdd60000
#define GPIO4_BASE 0xfe770000
#define GPIO_SWPORT_DR_L 0x0000
@@ -32,6 +36,14 @@
#define GPIO_WRITEMASK(bits) ((bits) << 16)
+#define SARADC_BASE 0xfe720000
+#define SARADC_DATA 0x0000
+#define SARADC_STAS 0x0004
+#define SARADC_ADC_STATUS BIT(0)
+#define SARADC_CTRL 0x0008
+#define SARADC_INPUT_SRC_MSK 0x7
+#define SARADC_POWER_CTRL BIT(3)
+
#define DTB_DIR "rockchip/"
struct rg3xx_model {
@@ -50,6 +62,7 @@
RGB30,
RK2023,
RGARCD,
+ RGB10MAX3,
/* Devices with duplicate ADC value */
RG353PS,
RG353VS,
@@ -107,6 +120,13 @@
.fdtfile = DTB_DIR "rk3566-anbernic-rg-arc-d.dtb",
.detect_panel = 0,
},
+ [RGB10MAX3] = {
+ .adc_value = 765, /* Observed average from device */
+ .board = "rk3566-powkiddy-rgb10max3",
+ .board_name = "Powkiddy RGB10MAX3",
+ .fdtfile = DTB_DIR "rk3566-powkiddy-rgb10max3.dtb",
+ .detect_panel = 0,
+ },
/* Devices with duplicate ADC value */
[RG353PS] = {
.adc_value = 860, /* Observed average from device */
@@ -150,11 +170,63 @@
};
/*
+ * The device has internal eMMC, and while some devices have an exposed
+ * clk pin you can ground to force a bypass not all devices do. As a
+ * result it may be possible for some devices to become a perma-brick
+ * if a corrupted TPL or SPL stage with a valid header is flashed to
+ * the internal eMMC. Add functionality to read ADC channel 0 (the func
+ * button) as early as possible in the boot process to provide some
+ * protection against this. If we ever get an open TPL stage, we should
+ * consider moving this function there.
+ */
+void read_func_button(void)
+{
+ int ret;
+ u32 reg;
+
+ /* Turn off SARADC to reset it. */
+ writel(0, (SARADC_BASE + SARADC_CTRL));
+
+ /* Enable channel 0 and power on SARADC. */
+ writel(((0 & SARADC_INPUT_SRC_MSK) | SARADC_POWER_CTRL),
+ (SARADC_BASE + SARADC_CTRL));
+
+ /*
+ * Wait for data to be ready. Use timeout of 20000us from
+ * rockchip_saradc driver.
+ */
+ ret = readl_poll_timeout((SARADC_BASE + SARADC_STAS), reg,
+ !(reg & SARADC_ADC_STATUS), 20000);
+ if (ret) {
+ printf("ADC Timeout");
+ return;
+ }
+
+ /* Read the data from the SARADC. */
+ reg = readl((SARADC_BASE + SARADC_DATA));
+
+ /* Turn the SARADC back off so it's ready to be used again. */
+ writel(0, (SARADC_BASE + SARADC_CTRL));
+
+ /*
+ * If the value is less than 30 the button is being pressed.
+ * Reset the device back into Rockchip download mode.
+ */
+ if (reg <= 30) {
+ printf("download key pressed, entering download mode...");
+ writel(BOOT_BROM_DOWNLOAD, CONFIG_ROCKCHIP_BOOT_MODE_REG);
+ do_reset(NULL, 0, 0, NULL);
+ }
+};
+
+/*
* Start LED very early so user knows device is on. Set color
* to red.
*/
void spl_board_init(void)
{
+ read_func_button();
+
/* Set GPIO0_C5, GPIO0_C6, and GPIO0_C7 to output. */
writel(GPIO_WRITEMASK(GPIO_C7 | GPIO_C6 | GPIO_C5) | \
(GPIO_C7 | GPIO_C6 | GPIO_C5),
diff --git a/board/atmel/sama7g54_curiosity/Kconfig b/board/atmel/sama7g54_curiosity/Kconfig
new file mode 100644
index 0000000..3e60d96
--- /dev/null
+++ b/board/atmel/sama7g54_curiosity/Kconfig
@@ -0,0 +1,15 @@
+if TARGET_SAMA7G54_CURIOSITY
+
+config SYS_BOARD
+ default "sama7g54_curiosity"
+
+config SYS_VENDOR
+ default "atmel"
+
+config SYS_SOC
+ default "at91"
+
+config SYS_CONFIG_NAME
+ default "sama7g54_curiosity"
+
+endif
diff --git a/board/atmel/sama7g54_curiosity/MAINTAINERS b/board/atmel/sama7g54_curiosity/MAINTAINERS
new file mode 100644
index 0000000..b9f1a27
--- /dev/null
+++ b/board/atmel/sama7g54_curiosity/MAINTAINERS
@@ -0,0 +1,9 @@
+SAMA7G54 CURIOSITY BOARD
+M: Mihai Sain <mihai.sain@microchip.com>
+S: Maintained
+F: board/atmel/sama7g54_curiosity.c
+F: include/configs/sama7g54_curiosity.h
+F: configs/sama7g54_curiosity_mmc_defconfig
+F: configs/sama7g54_curiosity_nandflash_defconfig
+F: configs/sama7g54_curiosity_qspiflash_defconfig
+F: arch/arm/dts/at91-sama7g54_curiosity*
diff --git a/board/atmel/sama7g54_curiosity/Makefile b/board/atmel/sama7g54_curiosity/Makefile
new file mode 100644
index 0000000..bc77655
--- /dev/null
+++ b/board/atmel/sama7g54_curiosity/Makefile
@@ -0,0 +1,7 @@
+# SPDX-License-Identifier: GPL-2.0+
+#
+# Copyright (C) 2024 Microchip Technology Inc. and its subsidiaries
+#
+# Author: Mihai Sain <mihai.sain@microchip.com>
+
+obj-y += sama7g54_curiosity.o
diff --git a/board/atmel/sama7g54_curiosity/sama7g54_curiosity.c b/board/atmel/sama7g54_curiosity/sama7g54_curiosity.c
new file mode 100644
index 0000000..33cd090
--- /dev/null
+++ b/board/atmel/sama7g54_curiosity/sama7g54_curiosity.c
@@ -0,0 +1,36 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2024 Microchip Technology Inc. and its subsidiaries
+ *
+ * Author: Mihai Sain <mihai.sain@microchip.com>
+ *
+ */
+
+#include <common.h>
+#include <init.h>
+#include <asm/global_data.h>
+#include <asm/io.h>
+#include <asm/arch/at91_common.h>
+#include <asm/arch/atmel_pio4.h>
+#include <asm/arch/gpio.h>
+#include <asm/arch/sama7g5.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+int board_init(void)
+{
+ // Address of boot parameters
+ gd->bd->bi_boot_params = gd->bd->bi_dram[0].start + 0x100;
+
+ return 0;
+}
+
+int dram_init_banksize(void)
+{
+ return fdtdec_setup_memory_banksize();
+}
+
+int dram_init(void)
+{
+ return fdtdec_setup_mem_size_base();
+}
diff --git a/board/chipspark/popmetal_rk3288/Kconfig b/board/chipspark/popmetal_rk3288/Kconfig
index a5f4043..22228ae 100644
--- a/board/chipspark/popmetal_rk3288/Kconfig
+++ b/board/chipspark/popmetal_rk3288/Kconfig
@@ -9,7 +9,4 @@
config SYS_CONFIG_NAME
default "popmetal_rk3288"
-config BOARD_SPECIFIC_OPTIONS # dummy
- def_bool y
-
endif
diff --git a/board/congatec/cgtqmx8/cgtqmx8.c b/board/congatec/cgtqmx8/cgtqmx8.c
index 26189ff..3b01354 100644
--- a/board/congatec/cgtqmx8/cgtqmx8.c
+++ b/board/congatec/cgtqmx8/cgtqmx8.c
@@ -371,13 +371,6 @@
puts("\nDDR ");
}
-/*
- * Board specific reset that is system reset.
- */
-void reset_cpu(void)
-{
- /* TODO */
-}
#ifdef CONFIG_OF_BOARD_SETUP
int ft_board_setup(void *blob, struct bd_info *bd)
diff --git a/board/dhelectronics/common/dh_common.c b/board/dhelectronics/common/dh_common.c
index 67e3d59..34094a0 100644
--- a/board/dhelectronics/common/dh_common.c
+++ b/board/dhelectronics/common/dh_common.c
@@ -18,6 +18,19 @@
return eth_env_get_enetaddr(env, enetaddr);
}
+int dh_get_mac_is_enabled(const char *alias)
+{
+ ofnode node = ofnode_path(alias);
+
+ if (!ofnode_valid(node))
+ return -EINVAL;
+
+ if (!ofnode_is_enabled(node))
+ return -ENODEV;
+
+ return 0;
+}
+
int dh_get_mac_from_eeprom(unsigned char *enetaddr, const char *alias)
{
struct udevice *dev;
@@ -57,6 +70,9 @@
if (dh_mac_is_in_env("ethaddr"))
return 0;
+ if (dh_get_mac_is_enabled("ethernet0"))
+ return 0;
+
if (!dh_get_mac_from_eeprom(enetaddr, "eeprom0"))
return eth_env_set_enetaddr("ethaddr", enetaddr);
diff --git a/board/dhelectronics/common/dh_common.h b/board/dhelectronics/common/dh_common.h
index 2b24637..a2de5b1 100644
--- a/board/dhelectronics/common/dh_common.h
+++ b/board/dhelectronics/common/dh_common.h
@@ -12,6 +12,14 @@
bool dh_mac_is_in_env(const char *env);
/*
+ * dh_get_mac_is_enabled - Test if ethernet MAC is enabled in DT
+ *
+ * @alias: alias for ethernet MAC device tree node
+ * Return: 0 if OK, other value on error
+ */
+int dh_get_mac_is_enabled(const char *alias);
+
+/*
* dh_get_mac_from_eeprom - Get MAC address from eeprom and write it to enetaddr
*
* @enetaddr: buffer where address is to be stored
diff --git a/board/dhelectronics/dh_imx6/dh_imx6.c b/board/dhelectronics/dh_imx6/dh_imx6.c
index 07fc9b1..0676587 100644
--- a/board/dhelectronics/dh_imx6/dh_imx6.c
+++ b/board/dhelectronics/dh_imx6/dh_imx6.c
@@ -92,6 +92,9 @@
if (dh_mac_is_in_env("ethaddr"))
return 0;
+ if (dh_get_mac_is_enabled("ethernet0"))
+ return 0;
+
if (!dh_imx_get_mac_from_fuse(enetaddr))
goto out;
diff --git a/board/dhelectronics/dh_imx8mp/imx8mp_dhcom_pdk2.c b/board/dhelectronics/dh_imx8mp/imx8mp_dhcom_pdk2.c
index 5f12d78..ff2c0e8 100644
--- a/board/dhelectronics/dh_imx8mp/imx8mp_dhcom_pdk2.c
+++ b/board/dhelectronics/dh_imx8mp/imx8mp_dhcom_pdk2.c
@@ -47,6 +47,9 @@
if (dh_mac_is_in_env("ethaddr"))
return 0;
+ if (dh_get_mac_is_enabled("ethernet0"))
+ return 0;
+
if (!dh_imx_get_mac_from_fuse(enetaddr))
goto out;
@@ -66,6 +69,9 @@
if (dh_mac_is_in_env("eth1addr"))
return 0;
+ if (dh_get_mac_is_enabled("ethernet1"))
+ return 0;
+
if (!dh_imx_get_mac_from_fuse(enetaddr))
goto increment_out;
diff --git a/board/dhelectronics/dh_stm32mp1/board.c b/board/dhelectronics/dh_stm32mp1/board.c
index d1f662d..079dfff 100644
--- a/board/dhelectronics/dh_stm32mp1/board.c
+++ b/board/dhelectronics/dh_stm32mp1/board.c
@@ -128,6 +128,9 @@
if (dh_mac_is_in_env("ethaddr"))
return 0;
+ if (dh_get_mac_is_enabled("ethernet0"))
+ return 0;
+
if (!dh_get_mac_from_eeprom(enetaddr, "eeprom0"))
return eth_env_set_enetaddr("ethaddr", enetaddr);
@@ -141,6 +144,9 @@
if (dh_mac_is_in_env("eth1addr"))
return 0;
+ if (dh_get_mac_is_enabled("ethernet1"))
+ return 0;
+
if (dh_stm32_mac_is_in_ks8851())
return 0;
diff --git a/board/edgeble/neural-compute-module-6/Kconfig b/board/edgeble/neural-compute-module-6/Kconfig
index c445454..05de14f 100644
--- a/board/edgeble/neural-compute-module-6/Kconfig
+++ b/board/edgeble/neural-compute-module-6/Kconfig
@@ -9,7 +9,4 @@
config SYS_CONFIG_NAME
default "neural-compute-module-6"
-config BOARD_SPECIFIC_OPTIONS # dummy
- def_bool y
-
endif
diff --git a/board/elgin/elgin_rv1108/Kconfig b/board/elgin/elgin_rv1108/Kconfig
index be92431..e942e13 100644
--- a/board/elgin/elgin_rv1108/Kconfig
+++ b/board/elgin/elgin_rv1108/Kconfig
@@ -9,7 +9,4 @@
config SYS_CONFIG_NAME
default "elgin_rv1108"
-config BOARD_SPECIFIC_OPTIONS # dummy
- def_bool y
-
endif
diff --git a/board/elgin/elgin_rv1108/elgin_rv1108.c b/board/elgin/elgin_rv1108/elgin_rv1108.c
index eb7a322..10398e7 100644
--- a/board/elgin/elgin_rv1108/elgin_rv1108.c
+++ b/board/elgin/elgin_rv1108/elgin_rv1108.c
@@ -8,7 +8,6 @@
#include <init.h>
#include <syscon.h>
#include <asm/global_data.h>
-#include <asm/io.h>
#include <asm/arch-rockchip/clock.h>
#include <asm/arch-rockchip/grf_rv1108.h>
#include <asm/arch-rockchip/hardware.h>
diff --git a/board/emulation/qemu-riscv/qemu-riscv.c b/board/emulation/qemu-riscv/qemu-riscv.c
index 181abbb..173245b 100644
--- a/board/emulation/qemu-riscv/qemu-riscv.c
+++ b/board/emulation/qemu-riscv/qemu-riscv.c
@@ -31,12 +31,6 @@
int board_init(void)
{
- /*
- * Make sure virtio bus is enumerated so that peripherals
- * on the virtio bus can be discovered by their drivers
- */
- virtio_init();
-
return 0;
}
@@ -46,6 +40,12 @@
if (CONFIG_IS_ENABLED(USB_KEYBOARD))
usb_init();
+ /*
+ * Make sure virtio bus is enumerated so that peripherals
+ * on the virtio bus can be discovered by their drivers
+ */
+ virtio_init();
+
return 0;
}
diff --git a/board/emulation/qemu-x86/Kconfig b/board/emulation/qemu-x86/Kconfig
index 9a06118..b2a4e08 100644
--- a/board/emulation/qemu-x86/Kconfig
+++ b/board/emulation/qemu-x86/Kconfig
@@ -18,7 +18,8 @@
select X86_RESET_VECTOR
select QEMU
select QFW_PIO if CMD_QFW
- select BOARD_ROMSIZE_KB_1024
+ select BOARD_ROMSIZE_KB_1024 if TARGET_QEMU_X86
+ select BOARD_ROMSIZE_KB_2048 if TARGET_QEMU_X86_64
imply VIRTIO_PCI
imply VIRTIO_NET
imply VIRTIO_BLK
diff --git a/board/firefly/firefly-rk3288/Kconfig b/board/firefly/firefly-rk3288/Kconfig
index 1c2bca8..ed1c9fc 100644
--- a/board/firefly/firefly-rk3288/Kconfig
+++ b/board/firefly/firefly-rk3288/Kconfig
@@ -9,7 +9,4 @@
config SYS_CONFIG_NAME
default "firefly-rk3288"
-config BOARD_SPECIFIC_OPTIONS # dummy
- def_bool y
-
endif
diff --git a/board/firefly/firefly-rk3308/Kconfig b/board/firefly/firefly-rk3308/Kconfig
index 80b1ad8..fd6b981 100644
--- a/board/firefly/firefly-rk3308/Kconfig
+++ b/board/firefly/firefly-rk3308/Kconfig
@@ -9,7 +9,4 @@
config SYS_CONFIG_NAME
default "firefly_rk3308"
-config BOARD_SPECIFIC_OPTIONS # dummy
- def_bool y
-
endif
diff --git a/board/firefly/firefly-rk3308/roc_cc_rk3308.c b/board/firefly/firefly-rk3308/roc_cc_rk3308.c
index bdf3cc0..99a52a7 100644
--- a/board/firefly/firefly-rk3308/roc_cc_rk3308.c
+++ b/board/firefly/firefly-rk3308/roc_cc_rk3308.c
@@ -5,7 +5,6 @@
#include <common.h>
#include <adc.h>
-#include <asm/io.h>
#include <asm/arch/grf_rk3308.h>
#include <asm/arch-rockchip/hardware.h>
#include <linux/bitops.h>
diff --git a/board/firefly/roc-pc-rk3399/Kconfig b/board/firefly/roc-pc-rk3399/Kconfig
index 720fbbb..c211e9d 100644
--- a/board/firefly/roc-pc-rk3399/Kconfig
+++ b/board/firefly/roc-pc-rk3399/Kconfig
@@ -9,8 +9,5 @@
config SYS_CONFIG_NAME
default "roc-pc-rk3399"
-config BOARD_SPECIFIC_OPTIONS # dummy
- def_bool y
-
endif
diff --git a/board/firefly/roc-pc-rk3399/MAINTAINERS b/board/firefly/roc-pc-rk3399/MAINTAINERS
index 68a5b75..2c0de44 100644
--- a/board/firefly/roc-pc-rk3399/MAINTAINERS
+++ b/board/firefly/roc-pc-rk3399/MAINTAINERS
@@ -6,3 +6,4 @@
F: include/configs/roc-pc-rk3399.h
F: configs/roc-pc-rk3399_defconfig
F: configs/roc-pc-mezzanine-rk3399_defconfig
+F: arch/arm/dts/rk3399-roc-pc*
diff --git a/board/firefly/roc-pc-rk3399/roc-pc-rk3399.c b/board/firefly/roc-pc-rk3399/roc-pc-rk3399.c
index 93e7d77..590519b 100644
--- a/board/firefly/roc-pc-rk3399/roc-pc-rk3399.c
+++ b/board/firefly/roc-pc-rk3399/roc-pc-rk3399.c
@@ -9,32 +9,12 @@
#include <log.h>
#include <spl_gpio.h>
#include <asm/io.h>
-#include <power/regulator.h>
#include <asm/arch-rockchip/cru.h>
#include <asm/arch-rockchip/gpio.h>
#include <asm/arch-rockchip/grf_rk3399.h>
-#ifndef CONFIG_SPL_BUILD
-int board_early_init_f(void)
-{
- struct udevice *regulator;
- int ret;
-
- ret = regulator_get_by_platname("vcc5v0_host", ®ulator);
- if (ret) {
- debug("%s vcc5v0_host init fail! ret %d\n", __func__, ret);
- goto out;
- }
-
- ret = regulator_set_enable(regulator, true);
- if (ret)
- debug("%s vcc5v0-host-en set fail! ret %d\n", __func__, ret);
-out:
- return 0;
-}
-
-#else
+#ifdef CONFIG_SPL_BUILD
#define PMUGRF_BASE 0xff320000
#define GPIO0_BASE 0xff720000
diff --git a/board/freescale/imx8mq_evk/imx8mq_evk.c b/board/freescale/imx8mq_evk/imx8mq_evk.c
index e394805..e577e4d 100644
--- a/board/freescale/imx8mq_evk/imx8mq_evk.c
+++ b/board/freescale/imx8mq_evk/imx8mq_evk.c
@@ -54,38 +54,8 @@
return 0;
}
-#ifdef CONFIG_FEC_MXC
-static int setup_fec(void)
-{
- struct iomuxc_gpr_base_regs *gpr =
- (struct iomuxc_gpr_base_regs *)IOMUXC_GPR_BASE_ADDR;
-
- /* Use 125M anatop REF_CLK1 for ENET1, not from external */
- clrsetbits_le32(&gpr->gpr[1], BIT(13) | BIT(17), 0);
- return set_clk_enet(ENET_125MHZ);
-}
-
-int board_phy_config(struct phy_device *phydev)
-{
- /* enable rgmii rxc skew and phy mode select to RGMII copper */
- phy_write(phydev, MDIO_DEVAD_NONE, 0x1d, 0x1f);
- phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, 0x8);
-
- phy_write(phydev, MDIO_DEVAD_NONE, 0x1d, 0x05);
- phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, 0x100);
-
- if (phydev->drv->config)
- phydev->drv->config(phydev);
- return 0;
-}
-#endif
-
int board_init(void)
{
-#ifdef CONFIG_FEC_MXC
- setup_fec();
-#endif
-
#if defined(CONFIG_USB_DWC3) || defined(CONFIG_USB_XHCI_DWC3)
init_usb_clk();
#endif
diff --git a/board/freescale/imx8qm_mek/imx8qm_mek.c b/board/freescale/imx8qm_mek/imx8qm_mek.c
index d96d1d0..2b209c8 100644
--- a/board/freescale/imx8qm_mek/imx8qm_mek.c
+++ b/board/freescale/imx8qm_mek/imx8qm_mek.c
@@ -102,14 +102,6 @@
return 0;
}
-/*
- * Board specific reset that is system reset.
- */
-void reset_cpu(void)
-{
- /* TODO */
-}
-
#ifdef CONFIG_OF_BOARD_SETUP
int ft_board_setup(void *blob, struct bd_info *bd)
{
diff --git a/board/freescale/imx8qxp_mek/imx8qxp_mek.c b/board/freescale/imx8qxp_mek/imx8qxp_mek.c
index 516cefd..833bee5 100644
--- a/board/freescale/imx8qxp_mek/imx8qxp_mek.c
+++ b/board/freescale/imx8qxp_mek/imx8qxp_mek.c
@@ -126,14 +126,6 @@
return 0;
}
-/*
- * Board specific reset that is system reset.
- */
-void reset_cpu(void)
-{
- /* TODO */
-}
-
#ifdef CONFIG_OF_BOARD_SETUP
int ft_board_setup(void *blob, struct bd_info *bd)
{
diff --git a/board/freescale/imx93_evk/spl.c b/board/freescale/imx93_evk/spl.c
index 2fd5559..7331a20 100644
--- a/board/freescale/imx93_evk/spl.c
+++ b/board/freescale/imx93_evk/spl.c
@@ -116,7 +116,7 @@
preloader_console_init();
- ret = imx9_probe_mu(NULL, NULL);
+ ret = imx9_probe_mu();
if (ret) {
printf("Fail to init Sentinel API\n");
} else {
diff --git a/board/friendlyelec/nanopc-t6-rk3588/Kconfig b/board/friendlyelec/nanopc-t6-rk3588/Kconfig
index 032ef48..e86a94c 100644
--- a/board/friendlyelec/nanopc-t6-rk3588/Kconfig
+++ b/board/friendlyelec/nanopc-t6-rk3588/Kconfig
@@ -9,7 +9,4 @@
config SYS_CONFIG_NAME
default "nanopc-t6-rk3588"
-config BOARD_SPECIFIC_OPTIONS # dummy
- def_bool y
-
endif
diff --git a/board/gateworks/venice/venice.c b/board/gateworks/venice/venice.c
index 0902a1d..f54f118 100644
--- a/board/gateworks/venice/venice.c
+++ b/board/gateworks/venice/venice.c
@@ -25,12 +25,13 @@
return 0;
}
-int board_fit_config_name_match(const char *name)
+int board_fit_config_name_match(const char *path)
{
- int i = 0;
- const char *dtb;
+ const char *name = path + strlen("freescale/");
static char init;
+ const char *dtb;
char buf[32];
+ int i = 0;
do {
dtb = eeprom_get_dtb_name(i++, buf, sizeof(buf));
diff --git a/board/geekbuying/geekbox/Kconfig b/board/geekbuying/geekbox/Kconfig
index 41aa8fb..ac5aedf 100644
--- a/board/geekbuying/geekbox/Kconfig
+++ b/board/geekbuying/geekbox/Kconfig
@@ -9,7 +9,4 @@
config SYS_CONFIG_NAME
default "geekbox"
-config BOARD_SPECIFIC_OPTIONS # dummy
- def_bool y
-
endif
diff --git a/board/google/gru/Kconfig b/board/google/gru/Kconfig
index 1455e14..c84ebaf 100644
--- a/board/google/gru/Kconfig
+++ b/board/google/gru/Kconfig
@@ -9,9 +9,6 @@
config SYS_CONFIG_NAME
default "gru"
-config BOARD_SPECIFIC_OPTIONS # dummy
- def_bool y
-
endif
if TARGET_CHROMEBOOK_KEVIN
@@ -25,7 +22,4 @@
config SYS_CONFIG_NAME
default "gru"
-config BOARD_SPECIFIC_OPTIONS # dummy
- def_bool y
-
endif
diff --git a/board/google/gru/gru.c b/board/google/gru/gru.c
index fbcf845..e08cb42 100644
--- a/board/google/gru/gru.c
+++ b/board/google/gru/gru.c
@@ -3,20 +3,9 @@
* Copyright 2018 Google
*/
-#include <common.h>
#include <dm.h>
#include <init.h>
-#include <syscon.h>
-#include <asm/io.h>
#include <asm/arch-rockchip/clock.h>
-#include <asm/arch-rockchip/grf_rk3399.h>
-#include <asm/arch-rockchip/hardware.h>
-#include <asm/arch-rockchip/misc.h>
-
-#define GRF_IO_VSEL_BT656_SHIFT 0
-#define GRF_IO_VSEL_AUDIO_SHIFT 1
-#define PMUGRF_CON0_VSEL_SHIFT 8
-#define PMUGRF_CON0_VOL_SHIFT 9
#ifdef CONFIG_SPL_BUILD
/* provided to defeat compiler optimisation in board_init_f() */
@@ -65,44 +54,3 @@
return 0;
}
#endif
-
-static void setup_iodomain(void)
-{
- struct rk3399_grf_regs *grf =
- syscon_get_first_range(ROCKCHIP_SYSCON_GRF);
- struct rk3399_pmugrf_regs *pmugrf =
- syscon_get_first_range(ROCKCHIP_SYSCON_PMUGRF);
-
- /* BT656 and audio is in 1.8v domain */
- rk_setreg(&grf->io_vsel, (1 << GRF_IO_VSEL_BT656_SHIFT |
- 1 << GRF_IO_VSEL_AUDIO_SHIFT));
-
- /*
- * Set GPIO1 1.8v/3.0v source select to PMU1830_VOL
- * and explicitly configure that PMU1830_VOL to be 1.8V
- */
- rk_setreg(&pmugrf->soc_con0, (1 << PMUGRF_CON0_VSEL_SHIFT |
- 1 << PMUGRF_CON0_VOL_SHIFT));
-}
-
-int misc_init_r(void)
-{
- const u32 cpuid_offset = 0x7;
- const u32 cpuid_length = 0x10;
- u8 cpuid[cpuid_length];
- int ret;
-
- setup_iodomain();
-
- ret = rockchip_cpuid_from_efuse(cpuid_offset, cpuid_length, cpuid);
- if (ret)
- return ret;
-
- ret = rockchip_cpuid_set(cpuid, cpuid_length);
- if (ret)
- return ret;
-
- ret = rockchip_setup_macaddr();
-
- return ret;
-}
diff --git a/board/google/veyron/Kconfig b/board/google/veyron/Kconfig
index 7f55d78..e24a2ae 100644
--- a/board/google/veyron/Kconfig
+++ b/board/google/veyron/Kconfig
@@ -9,9 +9,6 @@
config SYS_CONFIG_NAME
default "veyron"
-config BOARD_SPECIFIC_OPTIONS # dummy
- def_bool y
-
endif
if TARGET_CHROMEBIT_MICKEY
@@ -25,9 +22,6 @@
config SYS_CONFIG_NAME
default "veyron"
-config BOARD_SPECIFIC_OPTIONS # dummy
- def_bool y
-
endif
if TARGET_CHROMEBOOK_MINNIE
@@ -41,9 +35,6 @@
config SYS_CONFIG_NAME
default "veyron"
-config BOARD_SPECIFIC_OPTIONS # dummy
- def_bool y
-
endif
if TARGET_CHROMEBOOK_SPEEDY
@@ -57,7 +48,4 @@
config SYS_CONFIG_NAME
default "veyron"
-config BOARD_SPECIFIC_OPTIONS # dummy
- def_bool y
-
endif
diff --git a/board/hardkernel/odroid_go2/Kconfig b/board/hardkernel/odroid_go2/Kconfig
index cf3f7c9..82988df 100644
--- a/board/hardkernel/odroid_go2/Kconfig
+++ b/board/hardkernel/odroid_go2/Kconfig
@@ -9,7 +9,4 @@
config SYS_CONFIG_NAME
default "odroid_go2"
-config BOARD_SPECIFIC_OPTIONS # dummy
- def_bool y
-
endif
diff --git a/board/hardkernel/odroid_m1/Kconfig b/board/hardkernel/odroid_m1/Kconfig
index 999c494..0217c91 100644
--- a/board/hardkernel/odroid_m1/Kconfig
+++ b/board/hardkernel/odroid_m1/Kconfig
@@ -9,7 +9,4 @@
config SYS_CONFIG_NAME
default "odroid_m1"
-config BOARD_SPECIFIC_OPTIONS # dummy
- def_bool y
-
endif
diff --git a/board/intel/agilex5-socdk/MAINTAINERS b/board/intel/agilex5-socdk/MAINTAINERS
new file mode 100644
index 0000000..b696f78
--- /dev/null
+++ b/board/intel/agilex5-socdk/MAINTAINERS
@@ -0,0 +1,8 @@
+SOCFPGA BOARD
+M: Tien Fong Chee <tien.fong.chee@intel.com>
+M: Teik Heng Chong <teik.heng.chong@intel.com>
+M: Jit Loon Lim <jit.loon.lim@intel.com>
+S: Maintained
+F: board/intel/agilex5-socdk/
+F: include/configs/socfpga_agilex5_socdk.h
+F: configs/socfpga_agilex5_defconfig
diff --git a/board/liebherr/xea/spl_xea.c b/board/liebherr/xea/spl_xea.c
index df354ca..6cf8f83 100644
--- a/board/liebherr/xea/spl_xea.c
+++ b/board/liebherr/xea/spl_xea.c
@@ -112,13 +112,6 @@
MX28_PAD_I2C0_SCL__I2C0_SCL,
MX28_PAD_I2C0_SDA__I2C0_SDA,
- /* I2S Codec */
- MX28_PAD_SAIF0_BITCLK__SAIF0_BITCLK,
- MX28_PAD_SAIF0_LRCLK__SAIF0_LRCLK,
- MX28_PAD_SAIF0_MCLK__SAIF0_MCLK,
- MX28_PAD_SAIF0_SDATA0__SAIF0_SDATA0,
- MX28_PAD_SAIF1_SDATA0__SAIF1_SDATA0,
-
/* PWR-Hold */
MX28_PAD_SPDIF__GPIO_3_27,
@@ -232,11 +225,23 @@
MX28_PAD_ENET0_TXD0__ENET0_TXD0 | MUX_CONFIG_ENET,
MX28_PAD_ENET0_TXD1__ENET0_TXD1 | MUX_CONFIG_ENET,
MX28_PAD_ENET0_TXD3__ENET1_TXD1 | MUX_CONFIG_ENET,
- MX28_PAD_SSP1_CMD__GPIO_2_13, /* PHY reset */
+ MX28_PAD_SSP1_CMD__GPIO_2_13, /* PHY reset HW Rev. 1*/
+ MX28_PAD_SAIF0_LRCLK__GPIO_3_21, /* PHY reset HW Rev. 2*/
/* TIVA boot control */
MX28_PAD_GPMI_RDY3__GPIO_0_23 | MUX_CONFIG_BOOT, /* TIVA0 */
MX28_PAD_GPMI_WRN__GPIO_0_25 | MUX_CONFIG_BOOT, /* TIVA1 */
+
+ /* HW revision ID Base Board */
+ MX28_PAD_LCD_D12__GPIO_1_12,
+ MX28_PAD_LCD_D13__GPIO_1_13,
+ MX28_PAD_LCD_D14__GPIO_1_14,
+
+ /* HW revision ID (SoM) */
+ MX28_PAD_LCD_D15__GPIO_1_15,
+ MX28_PAD_LCD_D16__GPIO_1_16,
+ MX28_PAD_LCD_D17__GPIO_1_17,
+ MX28_PAD_LCD_D18__GPIO_1_18,
};
u32 mxs_dram_vals[] = {
diff --git a/board/liebherr/xea/xea.c b/board/liebherr/xea/xea.c
index c8ac526..0a6fd7f 100644
--- a/board/liebherr/xea/xea.c
+++ b/board/liebherr/xea/xea.c
@@ -216,6 +216,34 @@
return !boot_tiva0 || !boot_tiva1;
}
#else
+/*
+ * Reading the HW ID number for XEA SoM module
+ *
+ * GPIOs from Port 1 (GPIO1_15, GPIO1_16, GPIO1_17 and GPIO1_18)
+ * are used to store HW revision information.
+ * Reading of GPIOs values is performed before the Device Model is
+ * bring up as the proper DTB needs to be chosen first.
+ *
+ * Moreover, this approach is required as "single binary" configuration
+ * of U-Boot (imx28_xea_sb_defconfig) is NOT using SPL framework, so
+ * only minimal subset of functionality is provided when ID is read.
+ *
+ * Hence, the direct registers' access.
+ */
+#define XEA_SOM_HW_ID_GPIO_PORT (MXS_PINCTRL_BASE + (0x0900 + ((1) * 0x10)))
+#define XEA_SOM_REV_MASK GENMASK(18, 15)
+#define XEA_SOM_REV_SHIFT 15
+
+static u8 get_som_rev(void)
+{
+ struct mxs_register_32 *reg =
+ (struct mxs_register_32 *)XEA_SOM_HW_ID_GPIO_PORT;
+
+ u32 tmp = ~readl(®->reg);
+ u8 id = (tmp & XEA_SOM_REV_MASK) >> XEA_SOM_REV_SHIFT;
+
+ return id;
+}
int board_early_init_f(void)
{
@@ -252,6 +280,27 @@
return 0;
}
+
+#if defined(CONFIG_BOARD_LATE_INIT)
+int board_late_init(void)
+{
+ int ret = env_set_ulong("board_som_rev", get_som_rev());
+
+ if (ret)
+ printf("Cannot set XEA's SoM revision env variable!\n");
+
+ return 0;
+}
+#endif
+
+#if defined(CONFIG_DISPLAY_BOARDINFO)
+int checkboard(void)
+{
+ printf("Board: LWE XEA SoM HW rev %d\n", get_som_rev());
+
+ return 0;
+}
+#endif
int dram_init(void)
{
diff --git a/board/mqmaker/miqi_rk3288/Kconfig b/board/mqmaker/miqi_rk3288/Kconfig
index 232a112..bb687c9 100644
--- a/board/mqmaker/miqi_rk3288/Kconfig
+++ b/board/mqmaker/miqi_rk3288/Kconfig
@@ -9,7 +9,4 @@
config SYS_CONFIG_NAME
default "miqi_rk3288"
-config BOARD_SPECIFIC_OPTIONS # dummy
- def_bool y
-
endif
diff --git a/board/phytec/common/phytec_som_detection.c b/board/phytec/common/phytec_som_detection.c
index f9607b0..a56e0f6 100644
--- a/board/phytec/common/phytec_som_detection.c
+++ b/board/phytec/common/phytec_som_detection.c
@@ -248,4 +248,9 @@
return PHYTEC_EEPROM_INVAL;
}
+u8 __maybe_unused phytec_get_som_type(struct phytec_eeprom_data *data)
+{
+ return PHYTEC_EEPROM_INVAL;
+}
+
#endif /* IS_ENABLED(CONFIG_PHYTEC_SOM_DETECTION) */
diff --git a/board/phytec/phycore_imx8mp/phycore_imx8mp.env b/board/phytec/phycore_imx8mp/phycore_imx8mp.env
new file mode 100644
index 0000000..7f6c5fd
--- /dev/null
+++ b/board/phytec/phycore_imx8mp/phycore_imx8mp.env
@@ -0,0 +1,62 @@
+#include <env/phytec/rauc.env>
+
+bootcmd=
+ if test ${dofastboot} = 1; then
+ fastboot 0;
+ fi;
+ mmc dev ${mmcdev};
+ if mmc rescan; then
+ if test ${doraucboot} = 1; then
+ run raucinit;
+ fi;
+ if run loadimage; then
+ run mmcboot;
+ else
+ run netboot;
+ fi;
+ fi;
+console=ttymxc0,115200
+dofastboot=0
+emmc_dev=2
+fastboot_raw_partition_all=0 4194304
+fastboot_raw_partition_bootloader=64 8128
+fdt_addr=0x48000000
+fdt_file=CONFIG_DEFAULT_FDT_FILE
+image=Image
+ip_dyn=yes
+loadfdt=fatload mmc ${mmcdev}:${mmcpart} ${fdt_addr} ${fdt_file}
+loadimage=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${image}
+mmcargs=
+ setenv bootargs console=${console}
+ root=/dev/mmcblk${mmcdev}p${mmcroot} ${raucargs} rootwait rw
+mmcautodetect=yes
+mmcboot=
+ echo Booting from mmc ...;
+ run mmcargs;
+ if run loadfdt; then
+ booti ${loadaddr} - ${fdt_addr};
+ else
+ echo WARN: Cannot load the DT;
+ fi;
+mmcdev=CONFIG_SYS_MMC_ENV_DEV
+mmcpart=1
+mmcroot=2
+netargs=
+ setenv bootargs console=${console} root=/dev/nfs ip=dhcp
+ nfsroot=${serverip}:${nfsroot},v3,tcp
+netboot=
+ echo Booting from net ...;
+ if test ${ip_dyn} = yes; then
+ setenv get_cmd dhcp;
+ else
+ setenv get_cmd tftp;
+ fi;
+ ${get_cmd} ${loadaddr} ${image};
+ run netargs;
+ if ${get_cmd} ${fdt_addr} ${fdt_file}; then
+ booti ${loadaddr} - ${fdt_addr};
+ else
+ echo WARN: Cannot load the DT;
+ fi;
+nfsroot=/srv/nfs
+sd_dev=1
diff --git a/board/phytec/phycore_imx93/spl.c b/board/phytec/phycore_imx93/spl.c
index 16303fc..f03bfee 100644
--- a/board/phytec/phycore_imx93/spl.c
+++ b/board/phytec/phycore_imx93/spl.c
@@ -122,7 +122,7 @@
preloader_console_init();
- ret = imx9_probe_mu(NULL, NULL);
+ ret = imx9_probe_mu();
if (ret) {
printf("Fail to init ELE API\n");
} else {
diff --git a/board/phytec/phycore_rk3288/Kconfig b/board/phytec/phycore_rk3288/Kconfig
index 57cd8e2..09753ef 100644
--- a/board/phytec/phycore_rk3288/Kconfig
+++ b/board/phytec/phycore_rk3288/Kconfig
@@ -9,7 +9,4 @@
config SYS_CONFIG_NAME
default "phycore_rk3288"
-config BOARD_SPECIFIC_OPTIONS # dummy
- def_bool y
-
endif
diff --git a/board/pine64/pinebook-pro-rk3399/Kconfig b/board/pine64/pinebook-pro-rk3399/Kconfig
index 3bb7ca4..3eedbcd 100644
--- a/board/pine64/pinebook-pro-rk3399/Kconfig
+++ b/board/pine64/pinebook-pro-rk3399/Kconfig
@@ -9,7 +9,4 @@
config SYS_CONFIG_NAME
default "pinebook-pro-rk3399"
-config BOARD_SPECIFIC_OPTIONS
- def_bool y
-
endif
diff --git a/board/pine64/pinebook-pro-rk3399/MAINTAINERS b/board/pine64/pinebook-pro-rk3399/MAINTAINERS
index 7300ca1..2cafd1a 100644
--- a/board/pine64/pinebook-pro-rk3399/MAINTAINERS
+++ b/board/pine64/pinebook-pro-rk3399/MAINTAINERS
@@ -1,8 +1,8 @@
PINEBOOK_PRO
M: Peter Robinson <pbrobinson@gmail.com>
+R: Jonas Karlman <jonas@kwiboo.se>
S: Maintained
F: board/pine64/pinebook-pro-rk3399/
-F: include/configs/rk3399-pinebook-pro.h
-F: arch/arm/dts/rk3399-pinebook-pro.dts
-F: arch/arm/dts/rk3399-pinebook-pro-u-boot.dtsi
+F: include/configs/pinebook-pro-rk3399.h
+F: arch/arm/dts/rk3399-pinebook-pro*
F: configs/pinebook-pro-rk3399_defconfig
diff --git a/board/pine64/pinebook-pro-rk3399/Makefile b/board/pine64/pinebook-pro-rk3399/Makefile
deleted file mode 100644
index 2f692a1..0000000
--- a/board/pine64/pinebook-pro-rk3399/Makefile
+++ /dev/null
@@ -1 +0,0 @@
-obj-y += pinebook-pro-rk3399.o
diff --git a/board/pine64/pinebook-pro-rk3399/pinebook-pro-rk3399.c b/board/pine64/pinebook-pro-rk3399/pinebook-pro-rk3399.c
deleted file mode 100644
index 4ad7807..0000000
--- a/board/pine64/pinebook-pro-rk3399/pinebook-pro-rk3399.c
+++ /dev/null
@@ -1,76 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * (C) Copyright 2016 Rockchip Electronics Co., Ltd
- * (C) Copyright 2020 Peter Robinson <pbrobinson at gmail.com>
- */
-
-#include <common.h>
-#include <dm.h>
-#include <syscon.h>
-#include <asm/io.h>
-#include <asm/arch-rockchip/clock.h>
-#include <asm/arch-rockchip/grf_rk3399.h>
-#include <asm/arch-rockchip/hardware.h>
-#include <asm/arch-rockchip/misc.h>
-#include <linux/printk.h>
-#include <power/regulator.h>
-
-#define GRF_IO_VSEL_BT565_SHIFT 0
-#define PMUGRF_CON0_VSEL_SHIFT 8
-
-#ifndef CONFIG_SPL_BUILD
-int board_early_init_f(void)
-{
- struct udevice *regulator;
- int ret;
-
- ret = regulator_get_by_platname("vcc5v0_usb", ®ulator);
- if (ret) {
- pr_debug("%s vcc5v0_usb init fail! ret %d\n", __func__, ret);
- goto out;
- }
-
- ret = regulator_set_enable(regulator, true);
- if (ret)
- pr_debug("%s vcc5v0-host-en-gpio set fail! ret %d\n", __func__, ret);
-
-out:
- return 0;
-}
-#endif
-
-#ifdef CONFIG_MISC_INIT_R
-static void setup_iodomain(void)
-{
- struct rk3399_grf_regs *grf =
- syscon_get_first_range(ROCKCHIP_SYSCON_GRF);
- struct rk3399_pmugrf_regs *pmugrf =
- syscon_get_first_range(ROCKCHIP_SYSCON_PMUGRF);
-
- /* BT565 is in 1.8v domain */
- rk_setreg(&grf->io_vsel, 1 << GRF_IO_VSEL_BT565_SHIFT);
-
- /* Set GPIO1 1.8v/3.0v source select to PMU1830_VOL */
- rk_setreg(&pmugrf->soc_con0, 1 << PMUGRF_CON0_VSEL_SHIFT);
-}
-
-int misc_init_r(void)
-{
- const u32 cpuid_offset = 0x7;
- const u32 cpuid_length = 0x10;
- u8 cpuid[cpuid_length];
- int ret;
-
- setup_iodomain();
-
- ret = rockchip_cpuid_from_efuse(cpuid_offset, cpuid_length, cpuid);
- if (ret)
- return ret;
-
- ret = rockchip_cpuid_set(cpuid, cpuid_length);
- if (ret)
- return ret;
-
- return ret;
-}
-#endif
diff --git a/board/pine64/pinephone-pro-rk3399/Kconfig b/board/pine64/pinephone-pro-rk3399/Kconfig
index 13d6465..5f207df 100644
--- a/board/pine64/pinephone-pro-rk3399/Kconfig
+++ b/board/pine64/pinephone-pro-rk3399/Kconfig
@@ -9,7 +9,4 @@
config SYS_CONFIG_NAME
default "pinephone-pro-rk3399"
-config BOARD_SPECIFIC_OPTIONS
- def_bool y
-
endif
diff --git a/board/pine64/pinephone-pro-rk3399/MAINTAINERS b/board/pine64/pinephone-pro-rk3399/MAINTAINERS
index bc2dcdd..959566a 100644
--- a/board/pine64/pinephone-pro-rk3399/MAINTAINERS
+++ b/board/pine64/pinephone-pro-rk3399/MAINTAINERS
@@ -2,7 +2,6 @@
M: Peter Robinson <pbrobinson@gmail.com>
S: Maintained
F: board/pine64/pinephone-pro-rk3399/
-F: include/configs/rk3399-pinephone-pro.h
-F: arch/arm/dts/rk3399-pinephone-pro.dts
-F: arch/arm/dts/rk3399-pinephone-pro-u-boot.dtsi
+F: include/configs/pinephone-pro-rk3399.h
+F: arch/arm/dts/rk3399-pinephone-pro*
F: configs/pinephone-pro-rk3399_defconfig
diff --git a/board/pine64/pinephone-pro-rk3399/Makefile b/board/pine64/pinephone-pro-rk3399/Makefile
deleted file mode 100644
index 8d92030..0000000
--- a/board/pine64/pinephone-pro-rk3399/Makefile
+++ /dev/null
@@ -1 +0,0 @@
-obj-y += pinephone-pro-rk3399.o
diff --git a/board/pine64/pinephone-pro-rk3399/pinephone-pro-rk3399.c b/board/pine64/pinephone-pro-rk3399/pinephone-pro-rk3399.c
deleted file mode 100644
index b6ccbb9..0000000
--- a/board/pine64/pinephone-pro-rk3399/pinephone-pro-rk3399.c
+++ /dev/null
@@ -1,78 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * (C) Copyright 2016 Rockchip Electronics Co., Ltd
- * (C) Copyright 2022 Peter Robinson <pbrobinson at gmail.com>
- */
-
-#include <common.h>
-#include <dm.h>
-#include <init.h>
-#include <syscon.h>
-#include <asm/io.h>
-#include <asm/arch-rockchip/clock.h>
-#include <asm/arch-rockchip/grf_rk3399.h>
-#include <asm/arch-rockchip/hardware.h>
-#include <asm/arch-rockchip/misc.h>
-#include <power/regulator.h>
-
-#define GRF_IO_VSEL_BT565_GPIO2AB 1
-#define GRF_IO_VSEL_AUDIO_GPIO3D4A 2
-#define PMUGRF_CON0_VSEL_SHIFT 8
-
-#ifndef CONFIG_SPL_BUILD
-int board_early_init_f(void)
-{
- struct udevice *regulator;
- int ret;
-
- ret = regulator_get_by_platname("vcc5v0_usb", ®ulator);
- if (ret) {
- pr_debug("%s vcc5v0_usb init fail! ret %d\n", __func__, ret);
- goto out;
- }
-
- ret = regulator_set_enable(regulator, true);
- if (ret)
- pr_debug("%s vcc5v0-host-en-gpio set fail! ret %d\n", __func__, ret);
-
-out:
- return 0;
-}
-#endif
-
-#ifdef CONFIG_MISC_INIT_R
-static void setup_iodomain(void)
-{
- struct rk3399_grf_regs *grf =
- syscon_get_first_range(ROCKCHIP_SYSCON_GRF);
- struct rk3399_pmugrf_regs *pmugrf =
- syscon_get_first_range(ROCKCHIP_SYSCON_PMUGRF);
-
- /* BT565 is in 1.8v domain */
- rk_setreg(&grf->io_vsel,
- GRF_IO_VSEL_BT565_GPIO2AB | GRF_IO_VSEL_AUDIO_GPIO3D4A);
-
- /* Set GPIO1 1.8v/3.0v source select to PMU1830_VOL */
- rk_setreg(&pmugrf->soc_con0, 1 << PMUGRF_CON0_VSEL_SHIFT);
-}
-
-int misc_init_r(void)
-{
- const u32 cpuid_offset = 0x7;
- const u32 cpuid_length = 0x10;
- u8 cpuid[cpuid_length];
- int ret;
-
- setup_iodomain();
-
- ret = rockchip_cpuid_from_efuse(cpuid_offset, cpuid_length, cpuid);
- if (ret)
- return ret;
-
- ret = rockchip_cpuid_set(cpuid, cpuid_length);
- if (ret)
- return ret;
-
- return ret;
-}
-#endif
diff --git a/board/pine64/quartz64_rk3566/Kconfig b/board/pine64/quartz64_rk3566/Kconfig
index 3de1d8f..104b7a1 100644
--- a/board/pine64/quartz64_rk3566/Kconfig
+++ b/board/pine64/quartz64_rk3566/Kconfig
@@ -9,7 +9,4 @@
config SYS_CONFIG_NAME
default "quartz64_rk3566"
-config BOARD_SPECIFIC_OPTIONS # dummy
- def_bool y
-
endif
diff --git a/board/pine64/quartz64_rk3566/MAINTAINERS b/board/pine64/quartz64_rk3566/MAINTAINERS
index 6b75b35..37b8c1e 100644
--- a/board/pine64/quartz64_rk3566/MAINTAINERS
+++ b/board/pine64/quartz64_rk3566/MAINTAINERS
@@ -21,3 +21,14 @@
F: arch/arm/dts/rk3566-soquartz-cm4-u-boot.dtsi
F: arch/arm/dts/rk3566-soquartz-model-a.dts
F: arch/arm/dts/rk3566-soquartz-model-a-u-boot.dtsi
+
+PINETAB2-RK3566
+M: Jonas Karlman <jonas@kwiboo.se>
+S: Maintained
+F: configs/pinetab2-rk3566_defconfig
+F: arch/arm/dts/rk3566-pinetab2.dtsi
+F: arch/arm/dts/rk3566-pinetab2-u-boot.dtsi
+F: arch/arm/dts/rk3566-pinetab2-v0.1.dts
+F: arch/arm/dts/rk3566-pinetab2-v0.1-u-boot.dtsi
+F: arch/arm/dts/rk3566-pinetab2-v2.0.dts
+F: arch/arm/dts/rk3566-pinetab2-v2.0-u-boot.dtsi
diff --git a/board/pine64/quartzpro64-rk3588/Kconfig b/board/pine64/quartzpro64-rk3588/Kconfig
index 96aa792..4147240 100644
--- a/board/pine64/quartzpro64-rk3588/Kconfig
+++ b/board/pine64/quartzpro64-rk3588/Kconfig
@@ -9,7 +9,4 @@
config SYS_CONFIG_NAME
default "quartzpro64-rk3588"
-config BOARD_SPECIFIC_OPTIONS # dummy
- def_bool y
-
endif
diff --git a/board/pine64/rockpro64_rk3399/Kconfig b/board/pine64/rockpro64_rk3399/Kconfig
index 3353f1f..93aab57 100644
--- a/board/pine64/rockpro64_rk3399/Kconfig
+++ b/board/pine64/rockpro64_rk3399/Kconfig
@@ -9,7 +9,4 @@
config SYS_CONFIG_NAME
default "rockpro64_rk3399"
-config BOARD_SPECIFIC_OPTIONS # dummy
- def_bool y
-
endif
diff --git a/board/pine64/rockpro64_rk3399/MAINTAINERS b/board/pine64/rockpro64_rk3399/MAINTAINERS
index 220ee21..42084ae 100644
--- a/board/pine64/rockpro64_rk3399/MAINTAINERS
+++ b/board/pine64/rockpro64_rk3399/MAINTAINERS
@@ -1,7 +1,8 @@
ROCKPRO64
M: Jagan Teki <jagan@amarulasolutions.com>
+R: Jonas Karlman <jonas@kwiboo.se>
S: Maintained
F: board/pine64/rockpro64_rk3399
F: include/configs/rockpro64_rk3399.h
-F: arch/arm/dts/rk3399-rockpro64-u-boot.dtsi
+F: arch/arm/dts/rk3399-rockpro64*
F: configs/rockpro64-rk3399_defconfig
diff --git a/board/pine64/rockpro64_rk3399/Makefile b/board/pine64/rockpro64_rk3399/Makefile
deleted file mode 100644
index b015c47..0000000
--- a/board/pine64/rockpro64_rk3399/Makefile
+++ /dev/null
@@ -1,7 +0,0 @@
-#
-# (C) Copyright 2019 Vasily Khoruzhick
-#
-# SPDX-License-Identifier: GPL-2.0+
-#
-
-obj-y += rockpro64-rk3399.o
diff --git a/board/pine64/rockpro64_rk3399/rockpro64-rk3399.c b/board/pine64/rockpro64_rk3399/rockpro64-rk3399.c
deleted file mode 100644
index d790846..0000000
--- a/board/pine64/rockpro64_rk3399/rockpro64-rk3399.c
+++ /dev/null
@@ -1,56 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * (C) Copyright 2019 Vasily Khoruzhick <anarsoul@gmail.com>
- */
-
-#include <common.h>
-#include <dm.h>
-#include <init.h>
-#include <syscon.h>
-#include <asm/io.h>
-#include <asm/arch-rockchip/clock.h>
-#include <asm/arch-rockchip/grf_rk3399.h>
-#include <asm/arch-rockchip/hardware.h>
-#include <asm/arch-rockchip/misc.h>
-
-#define GRF_IO_VSEL_BT565_SHIFT 0
-#define PMUGRF_CON0_VSEL_SHIFT 8
-
-#ifdef CONFIG_MISC_INIT_R
-static void setup_iodomain(void)
-{
- struct rk3399_grf_regs *grf =
- syscon_get_first_range(ROCKCHIP_SYSCON_GRF);
- struct rk3399_pmugrf_regs *pmugrf =
- syscon_get_first_range(ROCKCHIP_SYSCON_PMUGRF);
-
- /* BT565 is in 1.8v domain */
- rk_setreg(&grf->io_vsel, 1 << GRF_IO_VSEL_BT565_SHIFT);
-
- /* Set GPIO1 1.8v/3.0v source select to PMU1830_VOL */
- rk_setreg(&pmugrf->soc_con0, 1 << PMUGRF_CON0_VSEL_SHIFT);
-}
-
-int misc_init_r(void)
-{
- const u32 cpuid_offset = 0x7;
- const u32 cpuid_length = 0x10;
- u8 cpuid[cpuid_length];
- int ret;
-
- setup_iodomain();
-
- ret = rockchip_cpuid_from_efuse(cpuid_offset, cpuid_length, cpuid);
- if (ret)
- return ret;
-
- ret = rockchip_cpuid_set(cpuid, cpuid_length);
- if (ret)
- return ret;
-
- ret = rockchip_setup_macaddr();
-
- return ret;
-}
-
-#endif
diff --git a/board/purism/librem5/spl.c b/board/purism/librem5/spl.c
index 581f092..9aadc55 100644
--- a/board/purism/librem5/spl.c
+++ b/board/purism/librem5/spl.c
@@ -418,12 +418,6 @@
return rv;
}
-int dm_usb_gadget_handle_interrupts(struct udevice *dev)
-{
- dwc3_uboot_handle_interrupt(dev);
- return 0;
-}
-
static void dwc3_nxp_usb_phy_init(struct dwc3_device *dwc3)
{
u32 RegData;
diff --git a/board/radxa/rock/Kconfig b/board/radxa/rock/Kconfig
index 855b9b6..c9c4576 100644
--- a/board/radxa/rock/Kconfig
+++ b/board/radxa/rock/Kconfig
@@ -9,7 +9,4 @@
config SYS_CONFIG_NAME
default "rock"
-config BOARD_SPECIFIC_OPTIONS # dummy
- def_bool y
-
endif
diff --git a/board/radxa/rock2/Kconfig b/board/radxa/rock2/Kconfig
index c2ff9e9..82ecaba 100644
--- a/board/radxa/rock2/Kconfig
+++ b/board/radxa/rock2/Kconfig
@@ -9,7 +9,4 @@
config SYS_CONFIG_NAME
default "rock2"
-config BOARD_SPECIFIC_OPTIONS # dummy
- def_bool y
-
endif
diff --git a/board/radxa/rock5a-rk3588s/Kconfig b/board/radxa/rock5a-rk3588s/Kconfig
index 2d7fc85..82013ad 100644
--- a/board/radxa/rock5a-rk3588s/Kconfig
+++ b/board/radxa/rock5a-rk3588s/Kconfig
@@ -9,7 +9,4 @@
config SYS_CONFIG_NAME
default "rock5a-rk3588s"
-config BOARD_SPECIFIC_OPTIONS # dummy
- def_bool y
-
endif
diff --git a/board/radxa/rock5b-rk3588/Kconfig b/board/radxa/rock5b-rk3588/Kconfig
index 8f14446..41dfe24 100644
--- a/board/radxa/rock5b-rk3588/Kconfig
+++ b/board/radxa/rock5b-rk3588/Kconfig
@@ -9,7 +9,4 @@
config SYS_CONFIG_NAME
default "rock5b-rk3588"
-config BOARD_SPECIFIC_OPTIONS # dummy
- def_bool y
-
endif
diff --git a/board/radxa/rockpi4-rk3399/Kconfig b/board/radxa/rockpi4-rk3399/Kconfig
new file mode 100644
index 0000000..d826635
--- /dev/null
+++ b/board/radxa/rockpi4-rk3399/Kconfig
@@ -0,0 +1,15 @@
+if TARGET_ROCKPI4_RK3399
+
+config SYS_BOARD
+ default "rockpi4-rk3399"
+
+config SYS_VENDOR
+ default "radxa"
+
+config SYS_CONFIG_NAME
+ default "rockpi4-rk3399"
+
+config BOARD_SPECIFIC_OPTIONS # dummy
+ def_bool y
+
+endif
diff --git a/board/radxa/rockpi4-rk3399/MAINTAINERS b/board/radxa/rockpi4-rk3399/MAINTAINERS
new file mode 100644
index 0000000..da5273f
--- /dev/null
+++ b/board/radxa/rockpi4-rk3399/MAINTAINERS
@@ -0,0 +1,22 @@
+ROCK-PI-4
+M: Jagan Teki <jagan@amarulasolutions.com>
+R: Jonas Karlman <jonas@kwiboo.se>
+S: Maintained
+F: board/radxa/rockpi4-rk3399/
+F: configs/rock-pi-4-rk3399_defconfig
+F: configs/rock-pi-4c-rk3399_defconfig
+F: arch/arm/dts/rk3399-rock-pi-4*
+
+ROCK-4C+
+M: FUKAUMI Naoki <naoki@radxa.com>
+R: Jonas Karlman <jonas@kwiboo.se>
+S: Maintained
+F: configs/rock-4c-plus-rk3399_defconfig
+F: arch/arm/dts/rk3399-rock-4c-plus*
+
+ROCK-4SE
+M: Christopher Obbard <chris.obbard@collabora.com>
+R: Jonas Karlman <jonas@kwiboo.se>
+S: Maintained
+F: configs/rock-4se-rk3399_defconfig
+F: arch/arm/dts/rk3399-rock-4se*
diff --git a/board/rockchip/evb_rk3399/Makefile b/board/radxa/rockpi4-rk3399/Makefile
similarity index 78%
rename from board/rockchip/evb_rk3399/Makefile
rename to board/radxa/rockpi4-rk3399/Makefile
index aaa51c2..3d02253 100644
--- a/board/rockchip/evb_rk3399/Makefile
+++ b/board/radxa/rockpi4-rk3399/Makefile
@@ -4,4 +4,4 @@
# SPDX-License-Identifier: GPL-2.0+
#
-obj-y += evb-rk3399.o
+obj-y += rockpi4-rk3399.o
diff --git a/board/rockchip/evb_rk3399/evb-rk3399.c b/board/radxa/rockpi4-rk3399/rockpi4-rk3399.c
similarity index 65%
rename from board/rockchip/evb_rk3399/evb-rk3399.c
rename to board/radxa/rockpi4-rk3399/rockpi4-rk3399.c
index 3c773d0..a533128 100644
--- a/board/rockchip/evb_rk3399/evb-rk3399.c
+++ b/board/radxa/rockpi4-rk3399/rockpi4-rk3399.c
@@ -3,14 +3,8 @@
* (C) Copyright 2016 Rockchip Electronics Co., Ltd
*/
-#include <common.h>
#include <dm.h>
#include <efi_loader.h>
-#include <init.h>
-#include <log.h>
-#include <asm/arch-rockchip/periph.h>
-#include <linux/kernel.h>
-#include <power/regulator.h>
#define ROCKPI4_UPDATABLE_IMAGES 2
@@ -25,36 +19,15 @@
#endif
#ifndef CONFIG_SPL_BUILD
-int board_early_init_f(void)
-{
- struct udevice *regulator;
- int ret;
-
- ret = regulator_get_by_platname("vcc5v0_host", ®ulator);
- if (ret) {
- debug("%s vcc5v0_host init fail! ret %d\n", __func__, ret);
- goto out;
- }
-
- ret = regulator_set_enable(regulator, true);
- if (ret)
- debug("%s vcc5v0-host-en set fail! ret %d\n", __func__, ret);
-
-out:
- return 0;
-}
-
-#if defined(CONFIG_EFI_HAVE_CAPSULE_SUPPORT) && defined(CONFIG_EFI_PARTITION)
+#if IS_ENABLED(CONFIG_EFI_HAVE_CAPSULE_SUPPORT) && IS_ENABLED(CONFIG_EFI_PARTITION)
static bool board_is_rockpi_4b(void)
{
- return CONFIG_IS_ENABLED(TARGET_EVB_RK3399) &&
- of_machine_is_compatible("radxa,rockpi4b");
+ return of_machine_is_compatible("radxa,rockpi4b");
}
static bool board_is_rockpi_4c(void)
{
- return CONFIG_IS_ENABLED(TARGET_EVB_RK3399) &&
- of_machine_is_compatible("radxa,rockpi4c");
+ return of_machine_is_compatible("radxa,rockpi4c");
}
void rockchip_capsule_update_board_setup(void)
diff --git a/board/rikomagic/mk808/Kconfig b/board/rikomagic/mk808/Kconfig
index 4abad7e..61c27d2 100644
--- a/board/rikomagic/mk808/Kconfig
+++ b/board/rikomagic/mk808/Kconfig
@@ -9,7 +9,4 @@
config SYS_CONFIG_NAME
default "mk808"
-config BOARD_SPECIFIC_OPTIONS # dummy
- def_bool y
-
endif
diff --git a/board/rockchip/evb_px30/Kconfig b/board/rockchip/evb_px30/Kconfig
index 0042c8e..03ed808 100644
--- a/board/rockchip/evb_px30/Kconfig
+++ b/board/rockchip/evb_px30/Kconfig
@@ -9,7 +9,4 @@
config SYS_CONFIG_NAME
default "evb_px30"
-config BOARD_SPECIFIC_OPTIONS # dummy
- def_bool y
-
endif
diff --git a/board/rockchip/evb_px5/Kconfig b/board/rockchip/evb_px5/Kconfig
index 9a04ee7..7a42b4a 100644
--- a/board/rockchip/evb_px5/Kconfig
+++ b/board/rockchip/evb_px5/Kconfig
@@ -9,7 +9,4 @@
config SYS_CONFIG_NAME
default "evb_px5"
-config BOARD_SPECIFIC_OPTIONS # dummy
- def_bool y
-
endif
diff --git a/board/rockchip/evb_rk3036/Kconfig b/board/rockchip/evb_rk3036/Kconfig
index ef45f62..4abe8cf 100644
--- a/board/rockchip/evb_rk3036/Kconfig
+++ b/board/rockchip/evb_rk3036/Kconfig
@@ -9,7 +9,4 @@
config SYS_CONFIG_NAME
default "evb_rk3036"
-config BOARD_SPECIFIC_OPTIONS # dummy
- def_bool y
-
endif
diff --git a/board/rockchip/evb_rk3128/Kconfig b/board/rockchip/evb_rk3128/Kconfig
index 5b3095a..c36691c 100644
--- a/board/rockchip/evb_rk3128/Kconfig
+++ b/board/rockchip/evb_rk3128/Kconfig
@@ -9,7 +9,4 @@
config SYS_CONFIG_NAME
default "evb_rk3128"
-config BOARD_SPECIFIC_OPTIONS # dummy
- def_bool y
-
endif
diff --git a/board/rockchip/evb_rk3229/Kconfig b/board/rockchip/evb_rk3229/Kconfig
index 361dcb1..f5862d5 100644
--- a/board/rockchip/evb_rk3229/Kconfig
+++ b/board/rockchip/evb_rk3229/Kconfig
@@ -9,7 +9,4 @@
config SYS_CONFIG_NAME
default "evb_rk3229"
-config BOARD_SPECIFIC_OPTIONS # dummy
- def_bool y
-
endif
diff --git a/board/rockchip/evb_rk3288/Kconfig b/board/rockchip/evb_rk3288/Kconfig
index 8ab07f4..0707486 100644
--- a/board/rockchip/evb_rk3288/Kconfig
+++ b/board/rockchip/evb_rk3288/Kconfig
@@ -9,7 +9,4 @@
config SYS_CONFIG_NAME
default "evb_rk3288"
-config BOARD_SPECIFIC_OPTIONS # dummy
- def_bool y
-
endif
diff --git a/board/rockchip/evb_rk3308/Kconfig b/board/rockchip/evb_rk3308/Kconfig
index 0074429..b12d7f8 100644
--- a/board/rockchip/evb_rk3308/Kconfig
+++ b/board/rockchip/evb_rk3308/Kconfig
@@ -9,7 +9,4 @@
config SYS_CONFIG_NAME
default "evb_rk3308"
-config BOARD_SPECIFIC_OPTIONS # dummy
- def_bool y
-
endif
diff --git a/board/rockchip/evb_rk3328/Kconfig b/board/rockchip/evb_rk3328/Kconfig
index ef446b4..1e084bd 100644
--- a/board/rockchip/evb_rk3328/Kconfig
+++ b/board/rockchip/evb_rk3328/Kconfig
@@ -9,7 +9,4 @@
config SYS_CONFIG_NAME
default "evb_rk3328"
-config BOARD_SPECIFIC_OPTIONS # dummy
- def_bool y
-
endif
diff --git a/board/rockchip/evb_rk3328/MAINTAINERS b/board/rockchip/evb_rk3328/MAINTAINERS
index 5fc114a..675b72d 100644
--- a/board/rockchip/evb_rk3328/MAINTAINERS
+++ b/board/rockchip/evb_rk3328/MAINTAINERS
@@ -4,17 +4,21 @@
F: board/rockchip/evb_rk3328
F: include/configs/evb_rk3328.h
F: configs/evb-rk3328_defconfig
+F: arch/arm/dts/rk3328-evb.dts
+F: arch/arm/dts/rk3328-evb-u-boot.dtsi
NANOPI-R2C-RK3328
M: Tianling Shen <cnsztl@gmail.com>
S: Maintained
F: configs/nanopi-r2c-rk3328_defconfig
+F: arch/arm/dts/rk3328-nanopi-r2c.dts
F: arch/arm/dts/rk3328-nanopi-r2c-u-boot.dtsi
NANOPI-R2C-PLUS-RK3328
M: Tianling Shen <cnsztl@gmail.com>
S: Maintained
F: configs/nanopi-r2c-plus-rk3328_defconfig
+F: arch/arm/dts/rk3328-nanopi-r2c-plus.dts
F: arch/arm/dts/rk3328-nanopi-r2c-plus-u-boot.dtsi
NANOPI-R2S-RK3328
@@ -28,29 +32,36 @@
M: Tianling Shen <cnsztl@gmail.com>
S: Maintained
F: configs/orangepi-r1-plus-rk3328_defconfig
+F: arch/arm/dts/rk3328-orangepi-r1-plus.dts
F: arch/arm/dts/rk3328-orangepi-r1-plus-u-boot.dtsi
ORANGEPI-R1-PLUS-LTS-RK3328
M: Tianling Shen <cnsztl@gmail.com>
S: Maintained
F: configs/orangepi-r1-plus-lts-rk3328_defconfig
+F: arch/arm/dts/rk3328-orangepi-r1-plus-lts.dts
F: arch/arm/dts/rk3328-orangepi-r1-plus-lts-u-boot.dtsi
ROC-RK3328-CC
M: Loic Devulder <ldevulder@suse.com>
M: Chen-Yu Tsai <wens@csie.org>
+R: Jonas Karlman <jonas@kwiboo.se>
S: Maintained
F: configs/roc-cc-rk3328_defconfig
+F: arch/arm/dts/rk3328-roc-cc.dts
F: arch/arm/dts/rk3328-roc-cc-u-boot.dtsi
ROCK64-RK3328
M: Matwey V. Kornilov <matwey.kornilov@gmail.com>
+R: Jonas Karlman <jonas@kwiboo.se>
S: Maintained
F: configs/rock64-rk3328_defconfig
+F: arch/arm/dts/rk3328-rock64.dts
F: arch/arm/dts/rk3328-rock64-u-boot.dtsi
ROCKPIE-RK3328
M: Banglang Huang <banglang.huang@foxmail.com>
+R: Jonas Karlman <jonas@kwiboo.se>
S: Maintained
F: configs/rock-pi-e-rk3328_defconfig
F: arch/arm/dts/rk3328-rock-pi-e.dts
diff --git a/board/rockchip/evb_rk3328/README b/board/rockchip/evb_rk3328/README
deleted file mode 100644
index 6cbb66a..0000000
--- a/board/rockchip/evb_rk3328/README
+++ /dev/null
@@ -1,70 +0,0 @@
-Introduction
-============
-
-RK3328 key features we might use in U-Boot:
-* CPU: ARMv8 64bit quad-core Cortex-A53
-* IRAM: 36KB
-* DRAM: 4GB-16MB dual-channel
-* eMMC: support eMMC 5.0/5.1, suport HS400, HS200, DDR50
-* SD/MMC: support SD 3.0, MMC 4.51
-* USB: USB2.0 EHCI host port *2
-* Display: RGB/HDMI/DP/MIPI/EDP
-
-evb key features:
-* regulator: pwm regulator for CPU B/L
-* PMIC: rk808
-* debug console: UART2
-
-In order to support Arm Trust Firmware(ATF), we need to use the
-miniloader from rockchip which:
-* do DRAM init
-* load and verify ATF image
-* load and verify U-Boot image
-
-Here is the step-by-step to boot to U-Boot on rk3328.
-
-Get the Source and prebuild binary
-==================================
-
- > mkdir ~/evb_rk3328
- > cd ~/evb_rk3328
- > git clone https://github.com/ARM-software/arm-trusted-firmware.git
- > git clone https://github.com/rockchip-linux/rkbin
- > git clone https://github.com/rockchip-linux/rkflashtool
-
-Compile ATF
-===============
-
- > cd arm-trusted-firmware
- > make realclean
- > make CROSS_COMPILE=aarch64-linux-gnu- PLAT=rk3328 bl31
-
-Compile U-Boot
-==================
-
- > cd ../u-boot
- > make CROSS_COMPILE=aarch64-linux-gnu- evb-rk3328_defconfig all
-
-Compile rkflashtool
-=======================
-
- > cd ../rkflashtool
- > make
-
-Package image for miniloader
-================================
- > cd ..
- > cp arm-trusted-firmware/build/rk3328/release/bl31.bin rkbin/rk33
- > ./rkbin/tools/trust_merger rkbin/tools/RK3328TRUST.ini
- > ./rkbin/tools/loaderimage --pack --uboot u-boot/u-boot-dtb.bin uboot.img
- > mkdir image
- > mv trust.img ./image/
- > mv uboot.img ./image/rk3328evb-uboot.bin
-
-Flash image
-===============
-Power on(or reset with RESET KEY) with MASKROM KEY preesed, and then:
-
- > ./rkflashtool/rkflashloader rk3328evb
-
-You should be able to get U-Boot log message in console/UART2 now.
diff --git a/board/rockchip/evb_rk3399/Kconfig b/board/rockchip/evb_rk3399/Kconfig
index 412b81c..597b0a6 100644
--- a/board/rockchip/evb_rk3399/Kconfig
+++ b/board/rockchip/evb_rk3399/Kconfig
@@ -9,7 +9,4 @@
config SYS_CONFIG_NAME
default "evb_rk3399"
-config BOARD_SPECIFIC_OPTIONS # dummy
- def_bool y
-
endif
diff --git a/board/rockchip/evb_rk3399/MAINTAINERS b/board/rockchip/evb_rk3399/MAINTAINERS
index acdb840..8dab3fa 100644
--- a/board/rockchip/evb_rk3399/MAINTAINERS
+++ b/board/rockchip/evb_rk3399/MAINTAINERS
@@ -4,48 +4,53 @@
F: board/rockchip/evb_rk3399
F: include/configs/evb_rk3399.h
F: configs/evb-rk3399_defconfig
+F: arch/arm/dts/rk3399-evb*
F: configs/firefly-rk3399_defconfig
+F: arch/arm/dts/rk3399-firefly*
EAIDK-610
M: Andy Yan <andy.yan@rock-chips.com>
S: Maintained
F: configs/eaidk-610-rk3399_defconfig
-F: arch/arm/dts/rk3399-eaidk-610-u-boot.dtsi
+F: arch/arm/dts/rk3399-eaidk-610*
KHADAS-EDGE
M: Nick Xie <nick@khadas.com>
S: Maintained
F: configs/khadas-edge-rk3399_defconfig
+F: arch/arm/dts/rk3399-khadas-edge.dts
+F: arch/arm/dts/rk3399-khadas-edge.dtsi
F: arch/arm/dts/rk3399-khadas-edge-u-boot.dtsi
KHADAS-EDGE-CAPTAIN
M: Nick Xie <nick@khadas.com>
S: Maintained
F: configs/khadas-edge-captain-rk3399_defconfig
-F: arch/arm/dts/rk3399-khadas-edge-captain-u-boot.dtsi
+F: arch/arm/dts/rk3399-khadas-edge-captain*
KHADAS-EDGE-V
M: Nick Xie <nick@khadas.com>
S: Maintained
F: configs/khadas-edge-v-rk3399_defconfig
-F: arch/arm/dts/rk3399-khadas-edge-v-u-boot.dtsi
+F: arch/arm/dts/rk3399-khadas-edge-v*
LEEZ-P710
M: Andy Yan <andy.yan@rock-chips.com>
S: Maintained
-F: arch/arm/dts/rk3399-leez-p710-u-boot.dtsi
+F: arch/arm/dts/rk3399-leez-p710*
F: configs/leez-rk3399_defconfig
NANOPC-T4
M: Jagan Teki <jagan@amarulasolutions.com>
S: Maintained
F: configs/nanopc-t4-rk3399_defconfig
-F: arch/arm/dts/rk3399-nanopc-t4-u-boot.dtsi
+F: arch/arm/dts/rk3399-nanopc-t4*
NANOPI-M4
M: Jagan Teki <jagan@amarulasolutions.com>
S: Maintained
F: configs/nanopi-m4-rk3399_defconfig
+F: arch/arm/dts/rk3399-nanopi-m4.dts
F: arch/arm/dts/rk3399-nanopi-m4-u-boot.dtsi
NANOPI-M4-2GB
@@ -53,55 +58,34 @@
M: Deepak Das <deepakdas.linux@gmail.com>
S: Maintained
F: configs/nanopi-m4-2gb-rk3399_defconfig
-F: arch/arm/dts/rk3399-nanopi-m4-2gb-u-boot.dtsi
+F: arch/arm/dts/rk3399-nanopi-m4-2gb*
NANOPI-M4B
M: Alexandre Vicenzi <linux@alxd.me>
S: Maintained
F: configs/nanopi-m4b-rk3399_defconfig
-F: arch/arm/dts/rk3399-nanopi-m4b-u-boot.dtsi
+F: arch/arm/dts/rk3399-nanopi-m4b*
NANOPI-NEO4
M: Jagan Teki <jagan@amarulasolutions.com>
S: Maintained
F: configs/nanopi-neo4-rk3399_defconfig
-F: arch/arm/dts/rk3399-nanopi-neo4-u-boot.dtsi
+F: arch/arm/dts/rk3399-nanopi-neo4*
NANOPI-R4S
M: Xiaobo Tian <peterwillcn@gmail.com>
S: Maintained
F: configs/nanopi-r4s-rk3399_defconfig
-F: arch/arm/dts/rk3399-nanopi-r4s-u-boot.dtsi
+F: arch/arm/dts/rk3399-nanopi-r4s*
ORANGEPI-RK3399
M: Jagan Teki <jagan@amarulasolutions.com>
S: Maintained
F: configs/orangepi-rk3399_defconfig
-F: arch/arm/dts/rk3399-u-boot.dtsi
-F: arch/arm/dts/rk3399-orangepi-u-boot.dtsi
-
-ROCK-4C+
-M: FUKAUMI Naoki <naoki@radxa.com>
-S: Maintained
-F: configs/rock-4c-plus-rk3399_defconfig
-F: arch/arm/dts/rk3399-rock-4c-plus.dts
-
-ROCK-4SE
-M: Christopher Obbard <chris.obbard@collabora.com>
-S: Maintained
-F: configs/rock-4se-rk3399_defconfig
-F: arch/arm/dts/rk3399-rock-4se-u-boot.dtsi
-
-ROCK-PI-4
-M: Jagan Teki <jagan@amarulasolutions.com>
-S: Maintained
-F: configs/rock-pi-4-rk3399_defconfig
-F: arch/arm/dts/rk3399-rock-pi-4-u-boot.dtsi
-F: configs/rock-pi-4c-rk3399_defconfig
-F: arch/arm/dts/rk3399-rock-pi-4c-u-boot.dtsi
+F: arch/arm/dts/rk3399-orangepi*
ROCK-PI-N10
M: Jagan Teki <jagan@amarulasolutions.com>
S: Maintained
F: configs/rock-pi-n10-rk3399pro_defconfig
-F: arch/arm/dts/rk3399pro-rock-pi-n10-u-boot.dtsi
+F: arch/arm/dts/rk3399pro-rock-pi-n10*
diff --git a/board/rockchip/evb_rk3568/Kconfig b/board/rockchip/evb_rk3568/Kconfig
index f3d3a7e..ab710c5 100644
--- a/board/rockchip/evb_rk3568/Kconfig
+++ b/board/rockchip/evb_rk3568/Kconfig
@@ -9,7 +9,4 @@
config SYS_CONFIG_NAME
default "evb_rk3568"
-config BOARD_SPECIFIC_OPTIONS # dummy
- def_bool y
-
endif
diff --git a/board/rockchip/evb_rk3588/Kconfig b/board/rockchip/evb_rk3588/Kconfig
index d38efe6..5e15d2e 100644
--- a/board/rockchip/evb_rk3588/Kconfig
+++ b/board/rockchip/evb_rk3588/Kconfig
@@ -9,7 +9,4 @@
config SYS_CONFIG_NAME
default "evb_rk3588"
-config BOARD_SPECIFIC_OPTIONS # dummy
- def_bool y
-
endif
diff --git a/board/rockchip/evb_rk3588/MAINTAINERS b/board/rockchip/evb_rk3588/MAINTAINERS
index 2bd44bc..a858ab1 100644
--- a/board/rockchip/evb_rk3588/MAINTAINERS
+++ b/board/rockchip/evb_rk3588/MAINTAINERS
@@ -1,3 +1,18 @@
+COOLPI-4B-RK3588S
+M: Andy Yan <andyshrk@163.com>
+S: Maintained
+F: configs/coolpi-4b-rk3588s_defconfig
+F: arch/arm/dts/rk3588s-coolpi-4b.dts
+F: arch/arm/dts/rk3588s-coolpi-u-boot.dtsi
+
+COOLPI-CM5-EVB-RK3588
+M: Andy Yan <andyshrk@163.com>
+S: Maintained
+F: configs/coolpi-cm5-evb-rk3588_defconfig
+F: arch/arm/dts/rk3588-coolpi-cm5.dtsi
+F: arch/arm/dts/rk3588-coolpi-cm5-evb.dts
+F: arch/arm/dts/rk3588-coolpi-cm5-evb-u-boot.dtsi
+
EVB-RK3588
M: Kever Yang <kever.yang@rock-chips.com>
S: Maintained
@@ -7,6 +22,13 @@
F: arch/arm/dts/rk3588-evb1-v10.dts
F: arch/arm/dts/rk3588-evb1-v10-u-boot.dtsi
+GENERIC-RK3588
+M: Jonas Karlman <jonas@kwiboo.se>
+S: Maintained
+F: configs/generic-rk3588_defconfig
+F: arch/arm/dts/rk3588-generic.dts
+F: arch/arm/dts/rk3588-generic-u-boot.dtsi
+
ORANGEPI-5-RK3588
M: Jonas Karlman <jonas@kwiboo.se>
S: Maintained
diff --git a/board/rockchip/evb_rv1108/Kconfig b/board/rockchip/evb_rv1108/Kconfig
index 4a76e0b..91afefd 100644
--- a/board/rockchip/evb_rv1108/Kconfig
+++ b/board/rockchip/evb_rv1108/Kconfig
@@ -9,7 +9,4 @@
config SYS_CONFIG_NAME
default "evb_rv1108"
-config BOARD_SPECIFIC_OPTIONS # dummy
- def_bool y
-
endif
diff --git a/board/rockchip/evb_rv1108/evb_rv1108.c b/board/rockchip/evb_rv1108/evb_rv1108.c
index e6ac598..0d7a486 100644
--- a/board/rockchip/evb_rv1108/evb_rv1108.c
+++ b/board/rockchip/evb_rv1108/evb_rv1108.c
@@ -8,7 +8,6 @@
#include <init.h>
#include <syscon.h>
#include <asm/global_data.h>
-#include <asm/io.h>
#include <asm/arch-rockchip/clock.h>
#include <asm/arch-rockchip/grf_rv1108.h>
#include <asm/arch-rockchip/hardware.h>
diff --git a/board/rockchip/kylin_rk3036/Kconfig b/board/rockchip/kylin_rk3036/Kconfig
index 8d35b4e..debffe1 100644
--- a/board/rockchip/kylin_rk3036/Kconfig
+++ b/board/rockchip/kylin_rk3036/Kconfig
@@ -9,7 +9,4 @@
config SYS_CONFIG_NAME
default "kylin_rk3036"
-config BOARD_SPECIFIC_OPTIONS # dummy
- def_bool y
-
endif
diff --git a/board/rockchip/sheep_rk3368/Kconfig b/board/rockchip/sheep_rk3368/Kconfig
index d39b5e8..321bf81 100644
--- a/board/rockchip/sheep_rk3368/Kconfig
+++ b/board/rockchip/sheep_rk3368/Kconfig
@@ -9,7 +9,4 @@
config SYS_CONFIG_NAME
default "sheep_rk3368"
-config BOARD_SPECIFIC_OPTIONS # dummy
- def_bool y
-
endif
diff --git a/board/rockchip/tinker_rk3288/Kconfig b/board/rockchip/tinker_rk3288/Kconfig
index bca6c37..04a9f14 100644
--- a/board/rockchip/tinker_rk3288/Kconfig
+++ b/board/rockchip/tinker_rk3288/Kconfig
@@ -9,7 +9,4 @@
config SYS_CONFIG_NAME
default "tinker_rk3288"
-config BOARD_SPECIFIC_OPTIONS # dummy
- def_bool y
-
endif
diff --git a/board/rockchip/tinker_rk3288/tinker-rk3288.c b/board/rockchip/tinker_rk3288/tinker-rk3288.c
index f85209c..eff3a00 100644
--- a/board/rockchip/tinker_rk3288/tinker-rk3288.c
+++ b/board/rockchip/tinker_rk3288/tinker-rk3288.c
@@ -11,8 +11,6 @@
#include <init.h>
#include <net.h>
#include <netdev.h>
-#include <asm/arch-rockchip/bootrom.h>
-#include <asm/io.h>
static int get_ethaddr_from_eeprom(u8 *addr)
{
@@ -38,13 +36,3 @@
return 0;
}
-
-int mmc_get_env_dev(void)
-{
- u32 bootdevice_brom_id = readl(BROM_BOOTSOURCE_ID_ADDR);
-
- if (bootdevice_brom_id == BROM_BOOTSOURCE_EMMC)
- return 0;
-
- return 1;
-}
diff --git a/board/rockchip/toybrick_rk3588/Kconfig b/board/rockchip/toybrick_rk3588/Kconfig
new file mode 100644
index 0000000..8e781a1
--- /dev/null
+++ b/board/rockchip/toybrick_rk3588/Kconfig
@@ -0,0 +1,12 @@
+if TARGET_TOYBRICK_RK3588
+
+config SYS_BOARD
+ default "toybrick_rk3588"
+
+config SYS_VENDOR
+ default "rockchip"
+
+config SYS_CONFIG_NAME
+ default "toybrick_rk3588"
+
+endif
diff --git a/board/rockchip/toybrick_rk3588/MAINTAINERS b/board/rockchip/toybrick_rk3588/MAINTAINERS
new file mode 100644
index 0000000..cd4401c
--- /dev/null
+++ b/board/rockchip/toybrick_rk3588/MAINTAINERS
@@ -0,0 +1,8 @@
+TOYBRICK-RK3588
+M: Elon Zhang <zhangzj@rock-chips.com>
+S: Maintained
+F: board/rockchip/toybrick_rk3588
+F: include/configs/toybrick_rk3588.h
+F: configs/toybrick-rk3588_defconfig
+F: arch/arm/dts/rk3588-toybrick-x0.dts
+F: arch/arm/dts/rk3588-toybrick-x0-u-boot.dtsi
diff --git a/board/rockchip/toybrick_rk3588/Makefile b/board/rockchip/toybrick_rk3588/Makefile
new file mode 100644
index 0000000..75d4d94
--- /dev/null
+++ b/board/rockchip/toybrick_rk3588/Makefile
@@ -0,0 +1,6 @@
+# SPDX-License-Identifier: GPL-2.0+
+#
+# Copyright (c) 2024 Rockchip Electronics Co,. Ltd.
+#
+
+obj-y += toybrick-rk3588.o
diff --git a/board/rockchip/toybrick_rk3588/toybrick-rk3588.c b/board/rockchip/toybrick_rk3588/toybrick-rk3588.c
new file mode 100644
index 0000000..e3217f7
--- /dev/null
+++ b/board/rockchip/toybrick_rk3588/toybrick-rk3588.c
@@ -0,0 +1,39 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (c) 2024 Rockchip Electronics Co,. Ltd.
+ */
+
+#include <fdtdec.h>
+#include <fdt_support.h>
+
+#ifdef CONFIG_OF_BOARD_SETUP
+static int rk3588_add_reserved_memory_fdt_nodes(void *new_blob)
+{
+ struct fdt_memory gap1 = {
+ .start = 0x3fc000000,
+ .end = 0x3fc4fffff,
+ };
+ struct fdt_memory gap2 = {
+ .start = 0x3fff00000,
+ .end = 0x3ffffffff,
+ };
+ unsigned long flags = FDTDEC_RESERVED_MEMORY_NO_MAP;
+ int ret;
+
+ /*
+ * Inject the reserved-memory nodes into the DTS
+ */
+ ret = fdtdec_add_reserved_memory(new_blob, "gap1", &gap1, NULL, 0,
+ NULL, flags);
+ if (ret)
+ return ret;
+
+ return fdtdec_add_reserved_memory(new_blob, "gap2", &gap2, NULL, 0,
+ NULL, flags);
+}
+
+int ft_board_setup(void *blob, struct bd_info *bd)
+{
+ return rk3588_add_reserved_memory_fdt_nodes(blob);
+}
+#endif
diff --git a/board/samsung/common/exynos5-dt.c b/board/samsung/common/exynos5-dt.c
index 95cf6d2..b3e87c9 100644
--- a/board/samsung/common/exynos5-dt.c
+++ b/board/samsung/common/exynos5-dt.c
@@ -122,12 +122,6 @@
.index = 0,
};
-int dm_usb_gadget_handle_interrupts(struct udevice *dev)
-{
- dwc3_uboot_handle_interrupt(dev);
- return 0;
-}
-
int board_usb_init(int index, enum usb_init_type init)
{
struct exynos_usb3_phy *phy = (struct exynos_usb3_phy *)
diff --git a/board/socionext/developerbox/developerbox.c b/board/socionext/developerbox/developerbox.c
index ac4415f..062e4a7 100644
--- a/board/socionext/developerbox/developerbox.c
+++ b/board/socionext/developerbox/developerbox.c
@@ -125,10 +125,29 @@
struct draminfo *synquacer_draminfo = (void *)SQ_DRAMINFO_BASE;
struct draminfo_entry *ent = synquacer_draminfo->entry;
unsigned long size = 0;
- int i;
+ struct mm_region *mr;
+ int i, ri;
+
+ if (synquacer_draminfo->nr_regions < 1) {
+ log_err("Failed to get correct DRAM information\n");
+ return -EINVAL;
+ }
- for (i = 0; i < synquacer_draminfo->nr_regions; i++)
+ for (i = 0; i < synquacer_draminfo->nr_regions; i++) {
+ if (i >= MAX_DDR_REGIONS)
+ break;
+
+ ri = DDR_REGION_INDEX(i);
+ mem_map[ri].phys = ent[i].base;
+ mem_map[ri].size = ent[i].size;
+ mem_map[ri].virt = mem_map[ri].phys;
size += ent[i].size;
+ if (i == 0)
+ continue;
+
+ mr = &mem_map[DDR_REGION_INDEX(0)];
+ mem_map[ri].attrs = mr->attrs;
+ }
gd->ram_size = size;
gd->ram_base = ent[0].base;
@@ -162,43 +181,6 @@
return 0;
}
-void build_mem_map(void)
-{
- struct draminfo *synquacer_draminfo = (void *)SQ_DRAMINFO_BASE;
- struct draminfo_entry *ent = synquacer_draminfo->entry;
- struct mm_region *mr;
- int i, ri;
-
- if (synquacer_draminfo->nr_regions < 1) {
- log_err("Failed to get correct DRAM information\n");
- return;
- }
-
- /* Update memory region maps */
- for (i = 0; i < synquacer_draminfo->nr_regions; i++) {
- if (i >= MAX_DDR_REGIONS)
- break;
-
- ri = DDR_REGION_INDEX(i);
- mem_map[ri].phys = ent[i].base;
- mem_map[ri].size = ent[i].size;
- mem_map[ri].virt = mem_map[ri].phys;
- if (i == 0)
- continue;
-
- mr = &mem_map[DDR_REGION_INDEX(0)];
- mem_map[ri].attrs = mr->attrs;
- }
-}
-
-void enable_caches(void)
-{
- build_mem_map();
-
- icache_enable();
- dcache_enable();
-}
-
int print_cpuinfo(void)
{
printf("CPU: SC2A11:Cortex-A53 MPCore 24cores\n");
diff --git a/board/solidrun/mx6cuboxi/mx6cuboxi.c b/board/solidrun/mx6cuboxi/mx6cuboxi.c
index 8edabf4..7f4811d 100644
--- a/board/solidrun/mx6cuboxi/mx6cuboxi.c
+++ b/board/solidrun/mx6cuboxi/mx6cuboxi.c
@@ -336,20 +336,17 @@
* HB 1 1 x
*/
- gpio_direction_input(IMX_GPIO_NR(2, 8));
- val3 = gpio_get_value(IMX_GPIO_NR(2, 8));
+ val3 = !!dm_gpio_get_value(&board_detect_desc[0]);
if (val3 == 0)
return HUMMINGBOARD2;
- gpio_direction_input(IMX_GPIO_NR(3, 4));
- val2 = gpio_get_value(IMX_GPIO_NR(3, 4));
+ val2 = !!dm_gpio_get_value(&board_detect_desc[1]);
if (val2 == 0)
return HUMMINGBOARD;
- gpio_direction_input(IMX_GPIO_NR(4, 9));
- val1 = gpio_get_value(IMX_GPIO_NR(4, 9));
+ val1 = !!dm_gpio_get_value(&board_detect_desc[2]);
if (val1 == 0) {
return CUBOXI;
@@ -363,8 +360,8 @@
int val1, val2;
SETUP_IOMUX_PADS(som_rev_detect);
- val1 = gpio_get_value(IMX_GPIO_NR(6, 0));
- val2 = gpio_get_value(IMX_GPIO_NR(6, 4));
+ val1 = !!dm_gpio_get_value(&board_detect_desc[3]);
+ val2 = !!dm_gpio_get_value(&board_detect_desc[4]);
if (val1 == 1 && val2 == 0)
return true;
@@ -381,37 +378,6 @@
return (mmc_get_op_cond(mmc, true) < 0) ? 0 : 1;
}
-/* Override the default implementation, DT model is not accurate */
-int checkboard(void)
-{
- request_detect_gpios();
-
- switch (board_type()) {
- case CUBOXI:
- puts("Board: MX6 Cubox-i");
- break;
- case HUMMINGBOARD:
- puts("Board: MX6 HummingBoard");
- break;
- case HUMMINGBOARD2:
- puts("Board: MX6 HummingBoard2");
- break;
- case UNKNOWN:
- default:
- puts("Board: Unknown\n");
- goto out;
- }
-
- if (is_rev_15_som())
- puts(" (som rev 1.5)\n");
- else
- puts("\n");
-
- free_detect_gpios();
-out:
- return 0;
-}
-
static int find_ethernet_phy(void)
{
struct mii_dev *bus = NULL;
@@ -505,12 +471,15 @@
switch (board_type()) {
case CUBOXI:
env_set("board_name", "CUBOXI");
+ puts("Board: MX6 Cubox-i");
break;
case HUMMINGBOARD:
env_set("board_name", "HUMMINGBOARD");
+ puts("Board: MX6 HummingBoard");
break;
case HUMMINGBOARD2:
env_set("board_name", "HUMMINGBOARD2");
+ puts("Board: MX6 HummingBoard2");
break;
case UNKNOWN:
default:
@@ -522,8 +491,12 @@
else
env_set("board_rev", "MX6DL");
- if (is_rev_15_som())
+ if (is_rev_15_som()) {
env_set("som_rev", "V15");
+ puts(" (som rev 1.5)\n");
+ } else {
+ puts("\n");
+ }
if (has_emmc())
env_set("has_emmc", "yes");
diff --git a/board/sophgo/milkv_duo/Kconfig b/board/sophgo/milkv_duo/Kconfig
index 2a458f2..040a748 100644
--- a/board/sophgo/milkv_duo/Kconfig
+++ b/board/sophgo/milkv_duo/Kconfig
@@ -7,7 +7,7 @@
default "sophgo"
config SYS_CPU
- default "generic"
+ default "cv1800b"
config SYS_CONFIG_NAME
default "milkv_duo"
@@ -23,6 +23,6 @@
config BOARD_SPECIFIC_OPTIONS
def_bool y
- select GENERIC_RISCV
+ select SOPHGO_CV1800B
endif
diff --git a/board/st/stih410-b2260/board.c b/board/st/stih410-b2260/board.c
index e21cbc2..8281757 100644
--- a/board/st/stih410-b2260/board.c
+++ b/board/st/stih410-b2260/board.c
@@ -50,12 +50,6 @@
.index = 0,
};
-int dm_usb_gadget_handle_interrupts(struct udevice *dev)
-{
- dwc3_uboot_handle_interrupt(dev);
- return 0;
-}
-
int board_usb_init(int index, enum usb_init_type init)
{
int node;
diff --git a/board/st/stv0991/Kconfig b/board/st/stv0991/Kconfig
deleted file mode 100644
index 007712f..0000000
--- a/board/st/stv0991/Kconfig
+++ /dev/null
@@ -1,15 +0,0 @@
-if TARGET_STV0991
-
-config SYS_BOARD
- default "stv0991"
-
-config SYS_VENDOR
- default "st"
-
-config SYS_SOC
- default "stv0991"
-
-config SYS_CONFIG_NAME
- default "stv0991"
-
-endif
diff --git a/board/st/stv0991/MAINTAINERS b/board/st/stv0991/MAINTAINERS
deleted file mode 100644
index e7a2cca..0000000
--- a/board/st/stv0991/MAINTAINERS
+++ /dev/null
@@ -1,6 +0,0 @@
-STV0991 APPLICATION BOARD
-M: Vikas Manocha <vikas.manocha@st.com>
-S: Maintained
-F: board/st/stv0991/
-F: include/configs/stv0991.h
-F: configs/stv0991_defconfig
diff --git a/board/st/stv0991/Makefile b/board/st/stv0991/Makefile
deleted file mode 100644
index 7f6d719..0000000
--- a/board/st/stv0991/Makefile
+++ /dev/null
@@ -1,6 +0,0 @@
-# SPDX-License-Identifier: GPL-2.0+
-#
-# Copyright (C) 2014, STMicroelectronics - All Rights Reserved
-# Author(s): Vikas Manocha, <vikas.manocha@st.com> for STMicroelectronics.
-
-obj-y := stv0991.o
diff --git a/board/st/stv0991/stv0991.c b/board/st/stv0991/stv0991.c
deleted file mode 100644
index 57ca9f6..0000000
--- a/board/st/stv0991/stv0991.c
+++ /dev/null
@@ -1,119 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * Copyright (C) 2014, STMicroelectronics - All Rights Reserved
- * Author(s): Vikas Manocha, <vikas.manocha@st.com> for STMicroelectronics.
- */
-
-#include <common.h>
-#include <bootstage.h>
-#include <dm.h>
-#include <init.h>
-#include <miiphy.h>
-#include <net.h>
-#include <asm/arch/stv0991_periph.h>
-#include <asm/arch/stv0991_defs.h>
-#include <asm/arch/hardware.h>
-#include <asm/arch/gpio.h>
-#include <netdev.h>
-#include <asm/global_data.h>
-#include <asm/io.h>
-#include <dm/platform_data/serial_pl01x.h>
-
-DECLARE_GLOBAL_DATA_PTR;
-
-struct gpio_regs *const gpioa_regs =
- (struct gpio_regs *) GPIOA_BASE_ADDR;
-
-#ifndef CONFIG_OF_CONTROL
-static const struct pl01x_serial_plat serial_plat = {
- .base = 0x80406000,
- .type = TYPE_PL011,
- .clock = 2700 * 1000,
-};
-
-U_BOOT_DRVINFO(stv09911_serials) = {
- .name = "serial_pl01x",
- .plat = &serial_plat,
-};
-#endif
-
-#if CONFIG_IS_ENABLED(BOOTSTAGE)
-void show_boot_progress(int progress)
-{
- printf("%i\n", progress);
-}
-#endif
-
-void enable_eth_phy(void)
-{
- /* Set GPIOA_06 pad HIGH (Appli board)*/
- writel(readl(&gpioa_regs->dir) | 0x40, &gpioa_regs->dir);
- writel(readl(&gpioa_regs->data) | 0x40, &gpioa_regs->data);
-}
-int board_eth_enable(void)
-{
- stv0991_pinmux_config(ETH_GPIOB_10_31_C_0_4);
- clock_setup(ETH_CLOCK_CFG);
- enable_eth_phy();
- return 0;
-}
-
-int board_qspi_enable(void)
-{
- stv0991_pinmux_config(QSPI_CS_CLK_PAD);
- clock_setup(QSPI_CLOCK_CFG);
- return 0;
-}
-
-/*
- * Miscellaneous platform dependent initialisations
- */
-int board_init(void)
-{
- board_eth_enable();
- board_qspi_enable();
- return 0;
-}
-
-int board_uart_init(void)
-{
- stv0991_pinmux_config(UART_GPIOC_30_31);
- clock_setup(UART_CLOCK_CFG);
- return 0;
-}
-
-#ifdef CONFIG_BOARD_EARLY_INIT_F
-int board_early_init_f(void)
-{
- board_uart_init();
- return 0;
-}
-#endif
-
-int dram_init(void)
-{
- gd->ram_size = PHYS_SDRAM_1_SIZE;
- return 0;
-}
-
-int dram_init_banksize(void)
-{
- gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
- gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE;
-
- return 0;
-}
-
-#ifdef CONFIG_CMD_NET
-int board_eth_init(struct bd_info *bis)
-{
- int ret = 0;
-
-#if defined(CONFIG_ETH_DESIGNWARE)
- u32 interface = PHY_INTERFACE_MODE_MII;
- if (designware_initialize(GMAC_BASE_ADDR, interface) >= 0)
- ret++;
-#endif
- return ret;
-}
-#endif
diff --git a/board/starfive/visionfive2/MAINTAINERS b/board/starfive/visionfive2/MAINTAINERS
index 600ff95..d7f638f 100644
--- a/board/starfive/visionfive2/MAINTAINERS
+++ b/board/starfive/visionfive2/MAINTAINERS
@@ -1,7 +1,8 @@
STARFIVE JH7110 VISIONFIVE2 BOARD
-M: Yanhong Wang <yanhong.wang@starfivetech.com>
+M: Minda Chen <minda.chen@starfivetech.com>
S: Maintained
F: arch/riscv/include/asm/arch-jh7110/
F: board/starfive/visionfive2/
F: include/configs/starfive-visionfive2.h
F: configs/starfive_visionfive2_defconfig
+F: drivers/pci/pcie_starfive_jh7110.c
diff --git a/board/starfive/visionfive2/spl.c b/board/starfive/visionfive2/spl.c
index 1b49945..45848db 100644
--- a/board/starfive/visionfive2/spl.c
+++ b/board/starfive/visionfive2/spl.c
@@ -4,7 +4,6 @@
* Author: Yanhong Wang<yanhong.wang@starfivetech.com>
*/
-#include <common.h>
#include <asm/arch/eeprom.h>
#include <asm/arch/gpio.h>
#include <asm/arch/regs.h>
@@ -27,6 +26,26 @@
const char *value;
};
+static const struct starfive_vf2_pro milk_v_mars[] = {
+ {"/soc/ethernet@16030000", "starfive,tx-use-rgmii-clk", NULL},
+ {"/soc/ethernet@16040000", "starfive,tx-use-rgmii-clk", NULL},
+
+ {"/soc/ethernet@16030000/mdio/ethernet-phy@0",
+ "motorcomm,tx-clk-adj-enabled", NULL},
+ {"/soc/ethernet@16030000/mdio/ethernet-phy@0",
+ "motorcomm,tx-clk-100-inverted", NULL},
+ {"/soc/ethernet@16030000/mdio/ethernet-phy@0",
+ "motorcomm,tx-clk-1000-inverted", NULL},
+ {"/soc/ethernet@16030000/mdio/ethernet-phy@0",
+ "motorcomm,rx-clk-drv-microamp", "3970"},
+ {"/soc/ethernet@16030000/mdio/ethernet-phy@0",
+ "motorcomm,rx-data-drv-microamp", "2910"},
+ {"/soc/ethernet@16030000/mdio/ethernet-phy@0",
+ "rx-internal-delay-ps", "1900"},
+ {"/soc/ethernet@16030000/mdio/ethernet-phy@0",
+ "tx-internal-delay-ps", "1500"},
+};
+
static const struct starfive_vf2_pro starfive_vera[] = {
{"/soc/ethernet@16030000/mdio/ethernet-phy@0", "rx-internal-delay-ps",
"1900"},
@@ -67,6 +86,49 @@
"tx-internal-delay-ps", "0"},
};
+void spl_fdt_fixup_mars(void *fdt)
+{
+ static const char compat[] = "milkv,mars\0starfive,jh7110";
+ u32 phandle;
+ u8 i;
+ int offset;
+ int ret;
+
+ fdt_setprop(fdt, fdt_path_offset(fdt, "/"), "compatible", compat, sizeof(compat));
+ fdt_setprop_string(fdt, fdt_path_offset(fdt, "/"), "model",
+ "Milk-V Mars");
+
+ /* gmac0 */
+ offset = fdt_path_offset(fdt, "/soc/clock-controller@17000000");
+ phandle = fdt_get_phandle(fdt, offset);
+ offset = fdt_path_offset(fdt, "/soc/ethernet@16030000");
+
+ fdt_setprop_u32(fdt, offset, "assigned-clocks", phandle);
+ fdt_appendprop_u32(fdt, offset, "assigned-clocks", JH7110_AONCLK_GMAC0_TX);
+ fdt_setprop_u32(fdt, offset, "assigned-clock-parents", phandle);
+ fdt_appendprop_u32(fdt, offset, "assigned-clock-parents",
+ JH7110_AONCLK_GMAC0_RMII_RTX);
+
+ /* gmac1 */
+ fdt_setprop_string(fdt, fdt_path_offset(fdt, "/soc/ethernet@16040000"),
+ "status", "disabled");
+
+ for (i = 0; i < ARRAY_SIZE(milk_v_mars); i++) {
+ offset = fdt_path_offset(fdt, milk_v_mars[i].path);
+
+ if (milk_v_mars[i].value)
+ ret = fdt_setprop_u32(fdt, offset, milk_v_mars[i].name,
+ dectoul(milk_v_mars[i].value, NULL));
+ else
+ ret = fdt_setprop_empty(fdt, offset, milk_v_mars[i].name);
+
+ if (ret) {
+ pr_err("%s set prop %s fail.\n", __func__, milk_v_mars[i].name);
+ break;
+ }
+ }
+}
+
void spl_fdt_fixup_version_a(void *fdt)
{
static const char compat[] = "starfive,visionfive-2-v1.2a\0starfive,jh7110";
@@ -167,22 +229,34 @@
void spl_perform_fixups(struct spl_image_info *spl_image)
{
u8 version;
+ const char *product_id;
- version = get_pcb_revision_from_eeprom();
- switch (version) {
- case 'a':
- case 'A':
- spl_fdt_fixup_version_a(spl_image->fdt_addr);
- break;
+ product_id = get_product_id_from_eeprom();
+ if (!product_id) {
+ pr_err("Can't read EEPROM\n");
+ return;
+ }
+ if (!strncmp(product_id, "MARS", 4)) {
+ spl_fdt_fixup_mars(spl_image->fdt_addr);
+ } else if (!strncmp(product_id, "VF7110", 6)) {
+ version = get_pcb_revision_from_eeprom();
+ switch (version) {
+ case 'a':
+ case 'A':
+ spl_fdt_fixup_version_a(spl_image->fdt_addr);
+ break;
- case 'b':
- case 'B':
- default:
- spl_fdt_fixup_version_b(spl_image->fdt_addr);
+ case 'b':
+ case 'B':
+ default:
+ spl_fdt_fixup_version_b(spl_image->fdt_addr);
break;
+ };
+ } else {
+ pr_err("Unknown product %s\n", product_id);
};
- /* Update the memory size which read form eeprom or DT */
+ /* Update the memory size which read from eeprom or DT */
fdt_fixup_memory(spl_image->fdt_addr, 0x40000000, gd->ram_size);
}
diff --git a/board/starfive/visionfive2/starfive_visionfive2.c b/board/starfive/visionfive2/starfive_visionfive2.c
index 78e118d..a86bca5 100644
--- a/board/starfive/visionfive2/starfive_visionfive2.c
+++ b/board/starfive/visionfive2/starfive_visionfive2.c
@@ -4,11 +4,11 @@
* Author: Yanhong Wang<yanhong.wang@starfivetech.com>
*/
-#include <common.h>
#include <cpu_func.h>
#include <dm.h>
#include <fdt_support.h>
#include <env.h>
+#include <log.h>
#include <asm/arch/eeprom.h>
#include <asm/io.h>
#include <asm/sections.h>
@@ -17,6 +17,8 @@
DECLARE_GLOBAL_DATA_PTR;
#define JH7110_L2_PREFETCHER_BASE_ADDR 0x2030000
#define JH7110_L2_PREFETCHER_HART_OFFSET 0x2000
+#define FDTFILE_MILK_V_MARS \
+ "starfive/jh7110-milkv-mars.dtb"
#define FDTFILE_VISIONFIVE2_1_2A \
"starfive/jh7110-starfive-visionfive-2-v1.2a.dtb"
#define FDTFILE_VISIONFIVE2_1_3B \
@@ -48,20 +50,38 @@
{
u8 version;
const char *fdtfile;
+ const char *product_id;
- version = get_pcb_revision_from_eeprom();
- switch (version) {
- case 'a':
- case 'A':
- fdtfile = FDTFILE_VISIONFIVE2_1_2A;
- break;
+ fdtfile = env_get("fdtfile");
+ if (fdtfile)
+ return;
- case 'b':
- case 'B':
- default:
- fdtfile = FDTFILE_VISIONFIVE2_1_3B;
- break;
- };
+ product_id = get_product_id_from_eeprom();
+ if (!product_id) {
+ log_err("Can't read EEPROM\n");
+ return;
+ }
+ if (!strncmp(product_id, "MARS", 4)) {
+ fdtfile = FDTFILE_MILK_V_MARS;
+ } else if (!strncmp(product_id, "VF7110", 6)) {
+ version = get_pcb_revision_from_eeprom();
+
+ switch (version) {
+ case 'a':
+ case 'A':
+ fdtfile = FDTFILE_VISIONFIVE2_1_2A;
+ break;
+
+ case 'b':
+ case 'B':
+ default:
+ fdtfile = FDTFILE_VISIONFIVE2_1_3B;
+ break;
+ }
+ } else {
+ log_err("Unknown product\n");
+ return;
+ }
env_set("fdtfile", fdtfile);
}
diff --git a/board/starfive/visionfive2/visionfive2-i2c-eeprom.c b/board/starfive/visionfive2/visionfive2-i2c-eeprom.c
index c36de1a..ddef7d6 100644
--- a/board/starfive/visionfive2/visionfive2-i2c-eeprom.c
+++ b/board/starfive/visionfive2/visionfive2-i2c-eeprom.c
@@ -4,7 +4,6 @@
* Author: Yanhong Wang<yanhong.wang@starfivetech.com>
*/
-#include <common.h>
#include <command.h>
#include <env.h>
#include <i2c.h>
@@ -405,6 +404,14 @@
update_crc();
}
+const char *get_product_id_from_eeprom(void)
+{
+ if (read_eeprom())
+ return NULL;
+
+ return pbuf.eeprom.atom1.data.pstr;
+}
+
int do_mac(struct cmd_tbl *cmdtp, int flag, int argc, char *const argv[])
{
char *cmd;
diff --git a/board/theobroma-systems/common/common.c b/board/theobroma-systems/common/common.c
index 864bcdd..585da43 100644
--- a/board/theobroma-systems/common/common.c
+++ b/board/theobroma-systems/common/common.c
@@ -89,36 +89,6 @@
return 0;
}
-int mmc_get_env_dev(void)
-{
- const char *boot_device =
- ofnode_read_chosen_string("u-boot,spl-boot-device");
- struct udevice *devp;
-
- if (!boot_device) {
- debug("%s: /chosen/u-boot,spl-boot-device not set\n",
- __func__);
-#ifdef CONFIG_SYS_MMC_ENV_DEV
- return CONFIG_SYS_MMC_ENV_DEV;
-#else
- return 0;
-#endif
- }
-
- debug("%s: booted from %s\n", __func__, boot_device);
-
- if (uclass_find_device_by_ofnode(UCLASS_MMC, ofnode_path(boot_device), &devp))
-#ifdef CONFIG_SYS_MMC_ENV_DEV
- return CONFIG_SYS_MMC_ENV_DEV;
-#else
- return 0;
-#endif
-
- debug("%s: get MMC ENV from mmc%d\n", __func__, devp->seq_);
-
- return devp->seq_;
-}
-
enum env_location arch_env_get_location(enum env_operation op, int prio)
{
const char *boot_device =
diff --git a/board/theobroma-systems/jaguar_rk3588/Kconfig b/board/theobroma-systems/jaguar_rk3588/Kconfig
new file mode 100644
index 0000000..0ff417a
--- /dev/null
+++ b/board/theobroma-systems/jaguar_rk3588/Kconfig
@@ -0,0 +1,16 @@
+if TARGET_JAGUAR_RK3588
+
+config SYS_BOARD
+ default "jaguar_rk3588"
+
+config SYS_VENDOR
+ default "theobroma-systems"
+
+config SYS_CONFIG_NAME
+ default "jaguar_rk3588"
+
+config BOARD_SPECIFIC_OPTIONS # dummy
+ def_bool y
+ select ENV_IS_NOWHERE
+
+endif
diff --git a/board/theobroma-systems/jaguar_rk3588/MAINTAINERS b/board/theobroma-systems/jaguar_rk3588/MAINTAINERS
new file mode 100644
index 0000000..28fae4b
--- /dev/null
+++ b/board/theobroma-systems/jaguar_rk3588/MAINTAINERS
@@ -0,0 +1,13 @@
+JAGUAR-RK3588 (SBC-RK3588-AMR Single Board Computer)
+M: Klaus Goger <klaus.goger@theobroma-systems.com>
+M: Quentin Schulz <quentin.schulz@theobroma-systems.com>
+M: Heiko Stuebner <heiko.stuebner@cherry.de>
+S: Maintained
+F: board/theobroma-systems/jaguar_rk3588
+F: board/theobroma-systems/common
+F: doc/board/theobroma-systems/
+F: include/configs/jaguar_rk3588.h
+F: arch/arm/dts/rk3588-jaguar*
+F: configs/jaguar-rk3588_defconfig
+W: https://theobroma-systems.com/product/jaguar-sbc-rk3588/
+T: git git://git.theobroma-systems.com/jaguar-u-boot.git
diff --git a/board/theobroma-systems/jaguar_rk3588/Makefile b/board/theobroma-systems/jaguar_rk3588/Makefile
new file mode 100644
index 0000000..532aab0
--- /dev/null
+++ b/board/theobroma-systems/jaguar_rk3588/Makefile
@@ -0,0 +1,10 @@
+#
+# Copyright (c) 2023 Theobroma Systems Design und Consulting GmbH
+#
+# SPDX-License-Identifier: GPL-2.0+
+#
+
+obj-y += jaguar_rk3588.o
+ifneq ($(CONFIG_SPL_BUILD),y)
+obj-y += ../common/common.o
+endif
diff --git a/board/theobroma-systems/jaguar_rk3588/jaguar_rk3588.c b/board/theobroma-systems/jaguar_rk3588/jaguar_rk3588.c
new file mode 100644
index 0000000..a6d44f1
--- /dev/null
+++ b/board/theobroma-systems/jaguar_rk3588/jaguar_rk3588.c
@@ -0,0 +1,53 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * (C) Copyright 2023 Theobroma Systems Design und Consulting GmbH
+ */
+
+#include <phy.h>
+#include <eth_phy.h>
+
+#include <asm/types.h>
+#include <asm/arch-rockchip/cru_rk3588.h>
+#include <asm/arch-rockchip/hardware.h>
+#include <asm/arch-rockchip/ioc_rk3588.h>
+#include <asm-generic/u-boot.h>
+#include <dm/device.h>
+#include <dm/uclass-id.h>
+#include <linux/bitfield.h>
+
+#include "../common/common.h"
+
+#define GPIO2C3_SEL_MASK GENMASK(15, 12)
+#define GPIO2C3_ETH0_REFCLKO_25M FIELD_PREP(GPIO2C3_SEL_MASK, 1)
+
+#define REFCLKO25M_ETH0_OUT_SEL_MASK BIT(15)
+#define REFCLKO25M_ETH0_OUT_SEL_CPLL FIELD_PREP(REFCLKO25M_ETH0_OUT_SEL_MASK, 1)
+#define REFCLKO25M_ETH0_OUT_DIV_MASK GENMASK(14, 8)
+#define REFCLKO25M_ETH0_OUT_DIV(x) FIELD_PREP(REFCLKO25M_ETH0_OUT_DIV_MASK, (x) - 1)
+
+#define REFCLKO25M_ETH0_OUT_EN BIT(4)
+
+void setup_eth0refclko(void)
+{
+ /* Configure and enable ETH0_REFCLKO_25MHz */
+ static struct rk3588_bus_ioc * const bus_ioc = (void *)BUS_IOC_BASE;
+ static struct rk3588_cru * const cru = (void *)CRU_BASE;
+
+ /* 1. Pinmux */
+ rk_clrsetreg(&bus_ioc->gpio2c_iomux_sel_l, GPIO2C3_SEL_MASK, GPIO2C3_ETH0_REFCLKO_25M);
+ /* 2. Parent clock selection + divider => CPLL (1.5GHz) / 60 => 25MHz */
+ rk_clrsetreg(&cru->clksel_con[15],
+ REFCLKO25M_ETH0_OUT_SEL_MASK | REFCLKO25M_ETH0_OUT_DIV_MASK,
+ REFCLKO25M_ETH0_OUT_SEL_CPLL | REFCLKO25M_ETH0_OUT_DIV(60));
+ /* 3. Enable clock */
+ rk_clrreg(&cru->clkgate_con[5], REFCLKO25M_ETH0_OUT_EN);
+}
+
+int rockchip_early_misc_init_r(void)
+{
+ setup_boottargets();
+
+ setup_eth0refclko();
+
+ return 0;
+}
diff --git a/board/theobroma-systems/lion_rk3368/Kconfig b/board/theobroma-systems/lion_rk3368/Kconfig
index fddbf82..537a2e7 100644
--- a/board/theobroma-systems/lion_rk3368/Kconfig
+++ b/board/theobroma-systems/lion_rk3368/Kconfig
@@ -9,9 +9,6 @@
config SYS_CONFIG_NAME
default "lion_rk3368"
-config BOARD_SPECIFIC_OPTIONS # dummy
- def_bool y
-
config ENV_SIZE
default 0x2000
diff --git a/board/theobroma-systems/puma_rk3399/MAINTAINERS b/board/theobroma-systems/puma_rk3399/MAINTAINERS
index 93f570f..7e84a5b 100644
--- a/board/theobroma-systems/puma_rk3399/MAINTAINERS
+++ b/board/theobroma-systems/puma_rk3399/MAINTAINERS
@@ -4,8 +4,9 @@
S: Maintained
F: board/theobroma-systems/puma_rk3399
F: board/theobroma-systems/common
+F: doc/board/theobroma-systems
F: include/configs/puma_rk3399.h
-F: arch/arm/dts/rk3399-puma.dts
+F: arch/arm/dts/rk3399-puma*
F: configs/puma-rk3399_defconfig
W: https://www.theobroma-systems.com/rk3399-q7/tech-specs
T: git git://git.theobroma-systems.com/puma-u-boot.git
diff --git a/board/theobroma-systems/puma_rk3399/README b/board/theobroma-systems/puma_rk3399/README
index 649aa3c..39c9d61 100644
--- a/board/theobroma-systems/puma_rk3399/README
+++ b/board/theobroma-systems/puma_rk3399/README
@@ -1,89 +1 @@
-Introduction
-============
-
-The RK3399-Q7 (Puma) is a system-on-module featuring the Rockchip
-RK3399 in a Qseven-compatible form-factor.
-
-RK3399-Q7 features:
- * CPU: ARMv8 64bit Big-Little architecture,
- * Big: dual-core Cortex-A72
- * Little: quad-core Cortex-A53
- * IRAM: 200KB
- * DRAM: 4GB-128MB dual-channel
- * eMMC: onboard eMMC
- * SD/MMC
- * GbE (onboard Micrel KSZ9031) Gigabit ethernet PHY
- * USB:
- * USB3.0 dual role port
- * 2x USB3.0 host, 1x USB2.0 host via onboard USB3.0 hub
- * Display: HDMI/eDP/MIPI
- * Camera: 2x CSI (one on the edge connector, one on the Q7 specified CSI ZIF)
- * NOR Flash: onboard SPI NOR
- * Companion Controller: onboard additional Cortex-M0 microcontroller
- * RTC
- * fan controller
- * CAN
-
-Here is the step-by-step to boot to U-Boot on rk3399.
-
-Get the Source and build ATF binary
-===================================
-
- > git clone https://git.trustedfirmware.org/TF-A/trusted-firmware-a.git
-
-Compile the ATF
-===============
-
- > cd trusted-firmware-a
- > make CROSS_COMPILE=aarch64-linux-gnu- PLAT=rk3399 bl31
- > cp build/rk3399/release/bl31/bl31.elf ../u-boot/bl31.elf
-
-Compile the U-Boot
-==================
-
- > cd ../u-boot
- > make CROSS_COMPILE=aarch64-linux-gnu- puma-rk3399_defconfig all
-
-Flash the image
-===============
-
-Copy u-boot-rockchip.bin to offset 32k for SD/eMMC.
-Copy u-boot-rockchip-spi.bin to offset 0 for NOR-flash.
-
-SD-Card
--------
-
- > dd if=u-boot-rockchip.bin of=/dev/sdb seek=64
-
-eMMC
-----
-
-rkdeveloptool allows to flash the on-board eMMC via the USB OTG interface with
-help of the Rockchip loader binary.
-
- > git clone https://github.com/rockchip-linux/rkdeveloptool
- > cd rkdeveloptool
- > autoreconf -i && ./configure && make
- > git clone https://github.com/rockchip-linux/rkbin.git
- > cd rkbin
- > ./tools/boot_merger RKBOOT/RK3399MINIALL.ini
- > cd ..
- > ./rkdeveloptool db rkbin/rk3399_loader_v1.25.126.bin
- > ./rkdeveloptool wl 64 ../u-boot-rockchip.bin
-
-NOR-Flash
----------
-
-rkdeveloptool allows to flash the on-board SPI via the USB OTG interface with
-help of the Rockchip loader binary.
-
- > git clone https://github.com/rockchip-linux/rkdeveloptool
- > cd rkdeveloptool
- > autoreconf -i && ./configure && make
- > git clone https://github.com/rockchip-linux/rkbin.git
- > cd rkbin
- > ./tools/boot_merger RKBOOT/RK3399MINIALL_SPINOR.ini
- > cd ..
- > ./rkdeveloptool db rkbin/rk3399_loader_spinor_v1.25.114.bin
- > ./rkdeveloptool ef
- > ./rkdeveloptool wl 0 ../u-boot-rockchip-spi.bin
+See doc/board/theobroma-systems/puma_rk3399.rst.
diff --git a/board/theobroma-systems/puma_rk3399/puma-rk3399.c b/board/theobroma-systems/puma_rk3399/puma-rk3399.c
index a82f97b..eeb8a99 100644
--- a/board/theobroma-systems/puma_rk3399/puma-rk3399.c
+++ b/board/theobroma-systems/puma_rk3399/puma-rk3399.c
@@ -3,50 +3,10 @@
* (C) Copyright 2017 Theobroma Systems Design und Consulting GmbH
*/
-#include <dm.h>
-#include <syscon.h>
-#include <dm/pinctrl.h>
-#include <asm/io.h>
-#include <asm/arch-rockchip/clock.h>
-#include <asm/arch-rockchip/hardware.h>
-#include <asm/arch-rockchip/grf_rk3399.h>
-#include <asm/arch-rockchip/misc.h>
#include "../common/common.h"
-static void setup_iodomain(void)
+int rockchip_early_misc_init_r(void)
{
- const u32 GRF_IO_VSEL_GPIO4CD_SHIFT = 3;
- struct rk3399_grf_regs *grf =
- syscon_get_first_range(ROCKCHIP_SYSCON_GRF);
-
- /*
- * Set bit 3 in GRF_IO_VSEL so PCIE_RST# works (pin GPIO4_C6).
- * Linux assumes that PCIE_RST# works out of the box as it probes
- * PCIe before loading the iodomain driver.
- */
- rk_setreg(&grf->io_vsel, 1 << GRF_IO_VSEL_GPIO4CD_SHIFT);
-}
-
-int misc_init_r(void)
-{
- const u32 cpuid_offset = 0x7;
- const u32 cpuid_length = 0x10;
- u8 cpuid[cpuid_length];
- int ret;
-
- ret = rockchip_cpuid_from_efuse(cpuid_offset, cpuid_length, cpuid);
- if (ret)
- return ret;
-
- ret = rockchip_cpuid_set(cpuid, cpuid_length);
- if (ret)
- return ret;
-
- ret = rockchip_setup_macaddr();
- if (ret)
- return ret;
-
- setup_iodomain();
setup_boottargets();
return 0;
diff --git a/board/theobroma-systems/ringneck_px30/MAINTAINERS b/board/theobroma-systems/ringneck_px30/MAINTAINERS
index 06e1bea..97baf334 100644
--- a/board/theobroma-systems/ringneck_px30/MAINTAINERS
+++ b/board/theobroma-systems/ringneck_px30/MAINTAINERS
@@ -4,7 +4,8 @@
S: Maintained
F: board/theobroma-systems/ringneck_px30
F: board/theobroma-systems/common
+F: doc/board/theobroma-systems/
F: include/configs/ringneck_px30.h
F: arch/arm/dts/px30-ringneck*
F: configs/ringneck-px30_defconfig
-W: https://www.theobroma-systems.com/px30-uq7#tech-spec
+W: https://theobroma-systems.com/product/ringneck-som-px30-uq7/
diff --git a/board/theobroma-systems/ringneck_px30/README b/board/theobroma-systems/ringneck_px30/README
index e756b3a..915baf4 100644
--- a/board/theobroma-systems/ringneck_px30/README
+++ b/board/theobroma-systems/ringneck_px30/README
@@ -1,69 +1 @@
-Introduction
-============
-
-The PX30-uQ7 (Ringneck) SoM is a µQseven-compatible (40mmx70mm, MXM-230
-connector) system-on-module from Theobroma Systems[1], featuring the
-Rockchip PX30.
-
-It provides the following feature set:
- * up to 4GB DDR4
- * up to 128GB on-module eMMC (with 8-bit 1.8V interface)
- * SD card (on a baseboard) via edge connector
- * Fast Ethernet with on-module TI DP83825I PHY
- * MIPI-DSI/LVDS
- * MIPI-CSI
- * USB
- - 1x USB 2.0 dual-role
- - 3x USB 2.0 host
- * on-module companion controller (STM32 Cortex-M0 or ATtiny), implementing:
- - low-power RTC functionality (ISL1208 emulation)
- - fan controller (AMC6821 emulation)
- - USB<->CAN bridge controller (STM32 only)
- * on-module Espressif ESP32 for Bluetooth + 2.4GHz WiFi
- * on-module NXP SE05x Secure Element
-
-Here is the step-by-step to boot to U-Boot on px30.
-
-Get the Source and build ATF binary
-===================================
-
- > git clone https://git.trustedfirmware.org/TF-A/trusted-firmware-a.git
-
-Compile the ATF
-===============
-
- > cd trusted-firmware-a
- > make CROSS_COMPILE=aarch64-linux-gnu- PLAT=px30 bl31
- > cp build/px30/release/bl31/bl31.elf ../u-boot/bl31.elf
-
-Compile the U-Boot
-==================
-
- > cd ../u-boot
- > make CROSS_COMPILE=aarch64-linux-gnu- ringneck-px30_defconfig all
-
-Flash the image
-===============
-
-Copy u-boot-rockchip.bin to offset 32k for SD/eMMC.
-
-SD-Card
--------
-
- > dd if=u-boot-rockchip.bin of=/dev/sdb seek=64
-
-eMMC
-----
-
-rkdeveloptool allows to flash the on-board eMMC via the USB OTG interface with
-help of the Rockchip loader binary.
-
- > git clone https://github.com/rockchip-linux/rkdeveloptool
- > cd rkdeveloptool
- > autoreconf -i && ./configure && make
- > git clone https://github.com/rockchip-linux/rkbin.git
- > cd rkbin
- > ./tools/boot_merger RKBOOT/PX30MINIALL.ini
- > cd ..
- > ./rkdeveloptool db rkbin/px30_loader_v1.16.131.bin
- > ./rkdeveloptool wl 64 ../u-boot-rockchip.bin
+See doc/board/theobroma-systems/ringneck_px30.rst.
diff --git a/board/theobroma-systems/ringneck_px30/ringneck-px30.c b/board/theobroma-systems/ringneck_px30/ringneck-px30.c
index ff7e414..bfebfe5 100644
--- a/board/theobroma-systems/ringneck_px30/ringneck-px30.c
+++ b/board/theobroma-systems/ringneck_px30/ringneck-px30.c
@@ -4,29 +4,11 @@
*/
#include <asm/gpio.h>
-#include <asm/arch-rockchip/misc.h>
#include <linux/delay.h>
#include "../common/common.h"
-int misc_init_r(void)
+int rockchip_early_misc_init_r(void)
{
- const u32 cpuid_offset = 0x7;
- const u32 cpuid_length = 0x10;
- u8 cpuid[cpuid_length];
- int ret;
-
- ret = rockchip_cpuid_from_efuse(cpuid_offset, cpuid_length, cpuid);
- if (ret)
- return ret;
-
- ret = rockchip_cpuid_set(cpuid, cpuid_length);
- if (ret)
- return ret;
-
- ret = rockchip_setup_macaddr();
- if (ret)
- return ret;
-
setup_boottargets();
return 0;
diff --git a/board/ti/am43xx/board.c b/board/ti/am43xx/board.c
index ea0d0b9..a4679a2 100644
--- a/board/ti/am43xx/board.c
+++ b/board/ti/am43xx/board.c
@@ -759,17 +759,6 @@
.usb2_phy_power = (void *)USB2_PHY2_POWER,
.index = 1,
};
-
-int dm_usb_gadget_handle_interrupts(struct udevice *dev)
-{
- u32 status;
-
- status = dwc3_omap_uboot_interrupt_status(dev);
- if (status)
- dwc3_uboot_handle_interrupt(dev);
-
- return 0;
-}
#endif /* CONFIG_USB_DWC3 */
#if defined(CONFIG_USB_DWC3) || defined(CONFIG_USB_XHCI_OMAP)
diff --git a/board/toradex/apalis-imx8/apalis-imx8.c b/board/toradex/apalis-imx8/apalis-imx8.c
index 2483a63..0f993e6 100644
--- a/board/toradex/apalis-imx8/apalis-imx8.c
+++ b/board/toradex/apalis-imx8/apalis-imx8.c
@@ -133,7 +133,7 @@
struct tdx_user_fuses tdxramfuses;
int scierr = sc_misc_otp_fuse_read(-1, 6, &val);
- if (scierr) {
+ if (!scierr) {
/* QP has one A72 core disabled */
is_quadplus = ((val >> 4) & 0x3) != 0x0;
}
@@ -291,14 +291,6 @@
return 0;
}
-/*
- * Board specific reset that is system reset.
- */
-void reset_cpu(void)
-{
- /* TODO */
-}
-
#if defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP)
int ft_board_setup(void *blob, struct bd_info *bd)
{
diff --git a/board/toradex/colibri-imx8x/colibri-imx8x.c b/board/toradex/colibri-imx8x/colibri-imx8x.c
index 2c673a4..3565785 100644
--- a/board/toradex/colibri-imx8x/colibri-imx8x.c
+++ b/board/toradex/colibri-imx8x/colibri-imx8x.c
@@ -46,7 +46,7 @@
u32 val = 0;
int sc_err = sc_misc_otp_fuse_read(-1, 6, &val);
- if (sc_err) {
+ if (!sc_err) {
/* DX has two A35 cores disabled */
return (val & 0xf) != 0x0;
}
@@ -93,15 +93,6 @@
return 0;
}
-#if IS_ENABLED(CONFIG_DM_GPIO)
-static void board_gpio_init(void)
-{
- /* TODO */
-}
-#else
-static inline void board_gpio_init(void) {}
-#endif
-
#if IS_ENABLED(CONFIG_FEC_MXC)
#include <miiphy.h>
@@ -128,8 +119,6 @@
int board_init(void)
{
- board_gpio_init();
-
if (IS_ENABLED(CONFIG_IMX_SNVS_SEC_SC_AUTO)) {
int ret = snvs_security_sc_init();
@@ -140,14 +129,6 @@
return 0;
}
-/*
- * Board specific reset that is system reset.
- */
-void reset_cpu(void)
-{
- /* TODO */
-}
-
#if defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP)
int ft_board_setup(void *blob, struct bd_info *bd)
{
diff --git a/board/toradex/verdin-imx8mm/MAINTAINERS b/board/toradex/verdin-imx8mm/MAINTAINERS
index 8217bbc..d567f0e 100644
--- a/board/toradex/verdin-imx8mm/MAINTAINERS
+++ b/board/toradex/verdin-imx8mm/MAINTAINERS
@@ -2,10 +2,6 @@
M: Marcel Ziswiler <marcel.ziswiler@toradex.com>
W: https://www.toradex.com/computer-on-modules/verdin-arm-family/nxp-imx-8m-mini
S: Maintained
-F: arch/arm/dts/imx8mm-verdin.dtsi
-F: arch/arm/dts/imx8mm-verdin-dev.dtsi
-F: arch/arm/dts/imx8mm-verdin-wifi.dtsi
-F: arch/arm/dts/imx8mm-verdin-wifi-dev.dts
F: arch/arm/dts/imx8mm-verdin-wifi-dev-u-boot.dtsi
F: board/toradex/verdin-imx8mm/
F: board/toradex/common/
diff --git a/board/toradex/verdin-imx8mp/MAINTAINERS b/board/toradex/verdin-imx8mp/MAINTAINERS
index 85d6be8..9fe76d8 100644
--- a/board/toradex/verdin-imx8mp/MAINTAINERS
+++ b/board/toradex/verdin-imx8mp/MAINTAINERS
@@ -1,8 +1,4 @@
Verdin iMX8M Plus
-F: arch/arm/dts/imx8mp-verdin.dtsi
-F: arch/arm/dts/imx8mp-verdin-dev.dtsi
-F: arch/arm/dts/imx8mp-verdin-wifi.dtsi
-F: arch/arm/dts/imx8mp-verdin-wifi-dev.dts
F: arch/arm/dts/imx8mp-verdin-wifi-dev-u-boot.dtsi
F: board/toradex/verdin-imx8mp/
F: board/toradex/common/
diff --git a/board/turing/turing-rk1-rk3588/Kconfig b/board/turing/turing-rk1-rk3588/Kconfig
index 4c6cd6a..0def6e0 100644
--- a/board/turing/turing-rk1-rk3588/Kconfig
+++ b/board/turing/turing-rk1-rk3588/Kconfig
@@ -9,7 +9,4 @@
config SYS_CONFIG_NAME
default "turing-rk1-rk3588"
-config BOARD_SPECIFIC_OPTIONS # dummy
- def_bool y
-
endif
diff --git a/board/vamrs/rock960_rk3399/Kconfig b/board/vamrs/rock960_rk3399/Kconfig
index cacc53f..0c052c6 100644
--- a/board/vamrs/rock960_rk3399/Kconfig
+++ b/board/vamrs/rock960_rk3399/Kconfig
@@ -9,7 +9,4 @@
config SYS_CONFIG_NAME
default "rock960_rk3399"
-config BOARD_SPECIFIC_OPTIONS # dummy
- def_bool y
-
endif
diff --git a/board/vamrs/rock960_rk3399/MAINTAINERS b/board/vamrs/rock960_rk3399/MAINTAINERS
index 8821672..f2121b1 100644
--- a/board/vamrs/rock960_rk3399/MAINTAINERS
+++ b/board/vamrs/rock960_rk3399/MAINTAINERS
@@ -4,8 +4,10 @@
F: board/vamrs/rock960_rk3399/
F: include/configs/rock960_rk3399.h
F: configs/rock960-rk3399_defconfig
+F: arch/arm/dts/rk3399-rock960*
FICUS EE
M: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
S: Maintained
F: configs/ficus-rk3399_defconfig
+F: arch/arm/dts/rk3399-ficus*
diff --git a/board/vamrs/rock960_rk3399/Makefile b/board/vamrs/rock960_rk3399/Makefile
deleted file mode 100644
index 6c3e475..0000000
--- a/board/vamrs/rock960_rk3399/Makefile
+++ /dev/null
@@ -1,6 +0,0 @@
-# SPDX-License-Identifier: GPL-2.0+
-#
-# Copyright (C) 2018 Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
-#
-
-obj-y += rock960-rk3399.o
diff --git a/board/vamrs/rock960_rk3399/rock960-rk3399.c b/board/vamrs/rock960_rk3399/rock960-rk3399.c
deleted file mode 100644
index a7fc38d..0000000
--- a/board/vamrs/rock960_rk3399/rock960-rk3399.c
+++ /dev/null
@@ -1,28 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * Copyright (C) 2018 Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
- */
-
-#include <common.h>
-#include <syscon.h>
-#include <asm/io.h>
-#include <asm/arch-rockchip/clock.h>
-#include <asm/arch-rockchip/grf_rk3399.h>
-#include <asm/arch-rockchip/hardware.h>
-#include <linux/bitops.h>
-
-#ifdef CONFIG_MISC_INIT_R
-int misc_init_r(void)
-{
- struct rk3399_grf_regs *grf =
- syscon_get_first_range(ROCKCHIP_SYSCON_GRF);
-
- /**
- * Some SSD's to work on rock960 would require explicit
- * domain voltage change, so BT565 is in 1.8v domain
- */
- rk_setreg(&grf->io_vsel, BIT(0));
-
- return 0;
-}
-#endif
diff --git a/board/variscite/imx93_var_som/spl.c b/board/variscite/imx93_var_som/spl.c
index 36e1721..71f346c 100644
--- a/board/variscite/imx93_var_som/spl.c
+++ b/board/variscite/imx93_var_som/spl.c
@@ -121,7 +121,7 @@
preloader_console_init();
- ret = imx9_probe_mu(NULL, NULL);
+ ret = imx9_probe_mu();
if (ret) {
printf("Fail to init ELE API\n");
} else {
diff --git a/board/vscom/baltos/u-boot.lds b/board/vscom/baltos/u-boot.lds
deleted file mode 100644
index cb2ee67..0000000
--- a/board/vscom/baltos/u-boot.lds
+++ /dev/null
@@ -1,128 +0,0 @@
-/*
- * Copyright (c) 2004-2008 Texas Instruments
- *
- * (C) Copyright 2002
- * Gary Jennejohn, DENX Software Engineering, <garyj@denx.de>
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm")
-OUTPUT_ARCH(arm)
-ENTRY(_start)
-SECTIONS
-{
- . = 0x00000000;
-
- . = ALIGN(4);
- .text :
- {
- *(.__image_copy_start)
- *(.vectors)
- CPUDIR/start.o (.text*)
- board/vscom/baltos/built-in.o (.text*)
- *(.text*)
- }
-
- . = ALIGN(4);
- .rodata : { *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*))) }
-
- . = ALIGN(4);
- .data : {
- *(.data*)
- }
-
- . = ALIGN(4);
-
- . = .;
-
- . = ALIGN(4);
- __u_boot_list : {
- KEEP(*(SORT(__u_boot_list*)));
- }
-
- . = ALIGN(4);
-
- .image_copy_end :
- {
- *(.__image_copy_end)
- }
-
- .rel_dyn_start :
- {
- *(.__rel_dyn_start)
- }
-
- .rel.dyn : {
- *(.rel*)
- }
-
- .rel_dyn_end :
- {
- *(.__rel_dyn_end)
- }
-
- .hash : { *(.hash*) }
-
- .end :
- {
- *(.__end)
- }
-
- _image_binary_end = .;
-
- /*
- * Deprecated: this MMU section is used by pxa at present but
- * should not be used by new boards/CPUs.
- */
- . = ALIGN(4096);
- .mmutable : {
- *(.mmutable)
- }
-
-/*
- * Compiler-generated __bss_start and __bss_end, see arch/arm/lib/bss.c
- * __bss_base and __bss_limit are for linker only (overlay ordering)
- */
-
- .bss_start __rel_dyn_start (OVERLAY) : {
- KEEP(*(.__bss_start));
- __bss_base = .;
- }
-
- .bss __bss_base (OVERLAY) : {
- *(.bss*)
- . = ALIGN(4);
- __bss_limit = .;
- }
-
- .bss_end __bss_limit (OVERLAY) : {
- KEEP(*(.__bss_end));
- }
-
- .dynsym _image_binary_end : { *(.dynsym) }
- .dynbss : { *(.dynbss) }
- .dynstr : { *(.dynstr*) }
- .dynamic : { *(.dynamic*) }
- .gnu.hash : { *(.gnu.hash) }
- .plt : { *(.plt*) }
- .interp : { *(.interp*) }
- .gnu : { *(.gnu*) }
- .ARM.exidx : { *(.ARM.exidx*) }
-}
diff --git a/board/xilinx/Kconfig b/board/xilinx/Kconfig
index 843198f..5c4ad8f 100644
--- a/board/xilinx/Kconfig
+++ b/board/xilinx/Kconfig
@@ -45,6 +45,7 @@
default 0x1000 if ARCH_VERSAL || ARCH_VERSAL_NET
default 0x8000 if MICROBLAZE
default 0x100000 if ARCH_ZYNQ || ARCH_ZYNQMP
+ default 0x23000000 if TARGET_XILINX_MBV
depends on OF_BOARD || OF_SEPARATE
help
Offset in the memory where the board configuration DTB is placed.
diff --git a/board/xilinx/common/board.c b/board/xilinx/common/board.c
index 9641ed3..b47d2d2 100644
--- a/board/xilinx/common/board.c
+++ b/board/xilinx/common/board.c
@@ -12,6 +12,7 @@
#include <env.h>
#include <image.h>
#include <init.h>
+#include <jffs2/load_kernel.h>
#include <lmb.h>
#include <log.h>
#include <asm/global_data.h>
@@ -20,6 +21,7 @@
#include <i2c.h>
#include <linux/sizes.h>
#include <malloc.h>
+#include <mtd_node.h>
#include "board.h"
#include <dm.h>
#include <i2c_eeprom.h>
@@ -43,7 +45,7 @@
.image_index = 1,
},
#endif
-#if defined(XILINX_UBOOT_IMAGE_GUID)
+#if defined(XILINX_UBOOT_IMAGE_GUID) && defined(CONFIG_SPL_FS_LOAD_PAYLOAD_NAME)
{
.image_type_id = XILINX_UBOOT_IMAGE_GUID,
.fw_name = u"XILINX-UBOOT",
@@ -103,10 +105,14 @@
for (i = 0; i < size; i++) {
byte = eeprom[i];
- /* Remove all non printable chars but ignore MAC address */
- if ((i < offsetof(struct xilinx_legacy_format, eth_mac) ||
- i >= offsetof(struct xilinx_legacy_format, unused1)) &&
- (byte < '!' || byte > '~')) {
+ /* Ignore MAC address */
+ if (i >= offsetof(struct xilinx_legacy_format, eth_mac) &&
+ i < offsetof(struct xilinx_legacy_format, unused1)) {
+ continue;
+ }
+
+ /* Remove all non printable chars */
+ if (byte < '!' || byte > '~') {
eeprom[i] = 0;
continue;
}
@@ -358,6 +364,14 @@
void *fdt_blob;
*err = 0;
+
+ if (IS_ENABLED(CONFIG_TARGET_XILINX_MBV)) {
+ fdt_blob = (void *)CONFIG_XILINX_OF_BOARD_DTB_ADDR;
+
+ if (fdt_magic(fdt_blob) == FDT_MAGIC)
+ return fdt_blob;
+ }
+
if (!IS_ENABLED(CONFIG_SPL_BUILD) &&
!IS_ENABLED(CONFIG_VERSAL_NO_DDR) &&
!IS_ENABLED(CONFIG_ZYNQMP_NO_DDR)) {
@@ -693,6 +707,13 @@
u8 buf[MAX_RAND_SIZE];
int nodeoffset, ret;
+ static const struct node_info nodes[] = {
+ { "arm,pl353-nand-r2p1", MTD_DEV_TYPE_NAND, },
+ };
+
+ if (IS_ENABLED(CONFIG_FDT_FIXUP_PARTITIONS) && IS_ENABLED(CONFIG_NAND_ZYNQ))
+ fdt_fixup_mtdparts(blob, nodes, ARRAY_SIZE(nodes));
+
if (uclass_get_device(UCLASS_RNG, 0, &dev) || !dev) {
debug("No RNG device\n");
return 0;
diff --git a/board/xilinx/mbv/Kconfig b/board/xilinx/mbv/Kconfig
index d2dec39..a3a6f21 100644
--- a/board/xilinx/mbv/Kconfig
+++ b/board/xilinx/mbv/Kconfig
@@ -10,15 +10,25 @@
default "generic"
config TEXT_BASE
- default 0x80000000 if !RISCV_SMODE
- default 0x80400000 if RISCV_SMODE && ARCH_RV32I
+ default 0x21200000
+
+config SPL_TEXT_BASE
+ default 0x20000000
+
+config SPL_OPENSBI_LOAD_ADDR
+ hex
+ default 0x20200000
config BOARD_SPECIFIC_OPTIONS
def_bool y
select GENERIC_RISCV
+ select SUPPORT_SPL
imply BOARD_LATE_INIT
+ imply SPL_RAM_SUPPORT
+ imply SPL_RAM_DEVICE
imply CMD_SBI
imply CMD_PING
+ imply OF_HAS_PRIOR_STAGE
source "board/xilinx/Kconfig"
diff --git a/board/xilinx/mbv/board.c b/board/xilinx/mbv/board.c
index ccf4395..c478f7e 100644
--- a/board/xilinx/mbv/board.c
+++ b/board/xilinx/mbv/board.c
@@ -5,7 +5,17 @@
* Michal Simek <michal.simek@amd.com>
*/
+#include <spl.h>
+
int board_init(void)
{
return 0;
}
+
+#ifdef CONFIG_SPL
+u32 spl_boot_device(void)
+{
+ /* RISC-V QEMU only supports RAM as SPL boot device */
+ return BOOT_DEVICE_RAM;
+}
+#endif
diff --git a/board/xilinx/versal-net/board.c b/board/xilinx/versal-net/board.c
index 990ca16..da03024 100644
--- a/board/xilinx/versal-net/board.c
+++ b/board/xilinx/versal-net/board.c
@@ -371,3 +371,35 @@
void reset_cpu(void)
{
}
+
+#if defined(CONFIG_ENV_IS_NOWHERE)
+enum env_location env_get_location(enum env_operation op, int prio)
+{
+ u8 bootmode = versal_net_get_bootmode();
+
+ if (prio)
+ return ENVL_UNKNOWN;
+
+ switch (bootmode) {
+ case EMMC_MODE:
+ case SD_MODE:
+ case SD1_LSHFT_MODE:
+ case SD_MODE1:
+ if (IS_ENABLED(CONFIG_ENV_IS_IN_FAT))
+ return ENVL_FAT;
+ if (IS_ENABLED(CONFIG_ENV_IS_IN_EXT4))
+ return ENVL_EXT4;
+ return ENVL_NOWHERE;
+ case OSPI_MODE:
+ case QSPI_MODE_24BIT:
+ case QSPI_MODE_32BIT:
+ if (IS_ENABLED(CONFIG_ENV_IS_IN_SPI_FLASH))
+ return ENVL_SPI_FLASH;
+ return ENVL_NOWHERE;
+ case JTAG_MODE:
+ case SELECTMAP_MODE:
+ default:
+ return ENVL_NOWHERE;
+ }
+}
+#endif
diff --git a/board/xilinx/versal/board.c b/board/xilinx/versal/board.c
index 8c2e614..4f6d561 100644
--- a/board/xilinx/versal/board.c
+++ b/board/xilinx/versal/board.c
@@ -291,6 +291,7 @@
{
}
+#if defined(CONFIG_ENV_IS_NOWHERE)
enum env_location env_get_location(enum env_operation op, int prio)
{
u32 bootmode = versal_get_bootmode();
@@ -320,3 +321,4 @@
return ENVL_NOWHERE;
}
}
+#endif
diff --git a/board/xilinx/zynqmp/zynqmp.c b/board/xilinx/zynqmp/zynqmp.c
index ba49eb7..f370fb7 100644
--- a/board/xilinx/zynqmp/zynqmp.c
+++ b/board/xilinx/zynqmp/zynqmp.c
@@ -588,6 +588,7 @@
return bootseq;
}
+#if defined(CONFIG_ENV_IS_NOWHERE)
enum env_location env_get_location(enum env_operation op, int prio)
{
u32 bootmode = zynqmp_get_bootmode();
@@ -621,11 +622,37 @@
return ENVL_NOWHERE;
}
}
+#endif
#if defined(CONFIG_SET_DFU_ALT_INFO)
#define DFU_ALT_BUF_LEN SZ_1K
+static void mtd_found_part(u32 *base, u32 *size)
+{
+ struct mtd_info *part, *mtd;
+
+ mtd_probe_devices();
+
+ mtd = get_mtd_device_nm("nor0");
+ if (!IS_ERR_OR_NULL(mtd)) {
+ list_for_each_entry(part, &mtd->partitions, node) {
+ debug("0x%012llx-0x%012llx : \"%s\"\n",
+ part->offset, part->offset + part->size,
+ part->name);
+
+ if (*base >= part->offset &&
+ *base < part->offset + part->size) {
+ debug("Found my partition: %d/%s\n",
+ part->index, part->name);
+ *base = part->offset;
+ *size = part->size;
+ break;
+ }
+ }
+ }
+}
+
void set_dfu_alt_info(char *interface, char *devstr)
{
int multiboot, bootseq = 0, len = 0;
@@ -661,21 +688,38 @@
len += snprintf(buf + len, DFU_ALT_BUF_LEN, ".bin fat %d 1",
bootseq);
#if defined(CONFIG_SPL_FS_LOAD_PAYLOAD_NAME)
- len += snprintf(buf + len, DFU_ALT_BUF_LEN, ";%s fat %d 1",
- CONFIG_SPL_FS_LOAD_PAYLOAD_NAME, bootseq);
+ if (strlen(CONFIG_SPL_FS_LOAD_PAYLOAD_NAME))
+ len += snprintf(buf + len, DFU_ALT_BUF_LEN,
+ ";%s fat %d 1",
+ CONFIG_SPL_FS_LOAD_PAYLOAD_NAME,
+ bootseq);
#endif
break;
case QSPI_MODE_24BIT:
case QSPI_MODE_32BIT:
- len += snprintf(buf + len, DFU_ALT_BUF_LEN,
- "sf 0:0=boot.bin raw %x 0x1500000",
- multiboot * SZ_32K);
+ {
+ u32 base = multiboot * SZ_32K;
+ u32 size = 0x1500000;
+ u32 limit = size;
+
+ mtd_found_part(&base, &limit);
+
+#if defined(CONFIG_SYS_SPI_U_BOOT_OFFS)
+ size = limit;
+ limit = CONFIG_SYS_SPI_U_BOOT_OFFS;
+#endif
+
+ len += snprintf(buf + len, DFU_ALT_BUF_LEN,
+ "sf 0:0=boot.bin raw 0x%x 0x%x",
+ base, limit);
#if defined(CONFIG_SPL_FS_LOAD_PAYLOAD_NAME) && defined(CONFIG_SYS_SPI_U_BOOT_OFFS)
- len += snprintf(buf + len, DFU_ALT_BUF_LEN,
- ";%s raw 0x%x 0x500000",
- CONFIG_SPL_FS_LOAD_PAYLOAD_NAME,
- multiboot * SZ_32K + CONFIG_SYS_SPI_U_BOOT_OFFS);
+ if (strlen(CONFIG_SPL_FS_LOAD_PAYLOAD_NAME))
+ len += snprintf(buf + len, DFU_ALT_BUF_LEN,
+ ";%s raw 0x%x 0x%x",
+ CONFIG_SPL_FS_LOAD_PAYLOAD_NAME,
+ base + limit, size - limit);
#endif
+ }
break;
default:
return;
diff --git a/board/xilinx/zynqmp/zynqmp_kria.env b/board/xilinx/zynqmp/zynqmp_kria.env
index 0f940bd..846eceb 100644
--- a/board/xilinx/zynqmp/zynqmp_kria.env
+++ b/board/xilinx/zynqmp/zynqmp_kria.env
@@ -17,6 +17,7 @@
bootcmd_usb1=devnum=1; run usb_boot
bootcmd_usb2=devnum=2; run usb_boot
bootcmd_usb3=devnum=3; run usb_boot
+bootcmd_usb4=devnum=4; run usb_boot
bootdelay=2
bootfstype=fat
bootm_low=0
@@ -44,7 +45,8 @@
preboot=setenv boot_targets; setenv modeboot; run board_setup
# SOM specific boot methods
-som_cc_boot=if test ${card1_name} = SCK-KV-G; then setenv boot_targets mmc1 usb0 usb1 usb2 usb3 pxe dhcp && run distro_bootcmd; elif test ${card1_name} = SCK-KR-G; then setenv boot_targets usb0 usb1 usb2 usb3 pxe dhcp && run distro_bootcmd; else test ${card1_name} = SCK-KD-G; setenv boot_targets usb0 usb1 usb2 usb3 pxe dhcp && run distro_bootcmd; fi;"
+usb_boot_devices='usb0 usb1 usb2 usb3 usb4'
+som_cc_boot=if test ${card1_name} = SCK-KV-G; then setenv boot_targets mmc1 ${usb_boot_devices} pxe dhcp jtag && run distro_bootcmd; elif test ${card1_name} = SCK-KR-G; then setenv boot_targets ${usb_boot_devices} pxe dhcp jtag && run distro_bootcmd; else test ${card1_name} = SCK-KD-G; setenv boot_targets ${usb_boot_devices} pxe dhcp jtag && run distro_bootcmd; fi;"
som_mmc_boot=setenv boot_targets mmc0 && run distro_bootcmd
k26_starter=SMK-K26-XCL2G
diff --git a/boot/Kconfig b/boot/Kconfig
index 3d7aabd..777e408 100644
--- a/boot/Kconfig
+++ b/boot/Kconfig
@@ -2,39 +2,6 @@
menu "Boot images"
-config ANDROID_BOOT_IMAGE
- bool "Android Boot Images"
- default y if FASTBOOT
- help
- This enables support for booting images which use the Android
- image format header.
-
-config TIMESTAMP
- bool "Show image date and time when displaying image information"
- default y if CMD_DATE
- help
- When CONFIG_TIMESTAMP is selected, the timestamp (date and time) of
- an image is printed by image commands like bootm or iminfo. This
- is shown as 'Timestamp: xxx' and 'Created: xxx'. If this option is
- enabled, then U-Boot requires FITs to have a timestamp. If a FIT is
- loaded that does not, the message 'Wrong FIT format: no timestamp'
- is shown.
-
-config BUTTON_CMD
- bool "Support for running a command if a button is held during boot"
- depends on CMDLINE
- depends on BUTTON
- help
- For many embedded devices it's useful to enter a special flashing mode
- such as fastboot mode when a button is held during boot. This option
- allows arbitrary commands to be assigned to specific buttons. These will
- be run after "preboot" if the button is held. Configuration is done via
- the environment variables "button_cmd_N_name" and "button_cmd_N" where n is
- the button number (starting from 0). e.g:
-
- "button_cmd_0_name=vol_down"
- "button_cmd_0=fastboot usb 0"
-
menuconfig FIT
bool "Flattened Image Tree (FIT)"
select HASH
@@ -558,6 +525,16 @@
This provides a way to try out standard boot on an existing boot flow.
+config BOOTMETH_EFI_BOOTMGR
+ bool "Bootdev support for EFI boot manager"
+ depends on EFI_BOOTMGR
+ select BOOTMETH_GLOBAL
+ default y
+ help
+ Enable booting via the UEFI boot manager. Based on the EFI variables
+ the EFI binary to be launched is determined. To set the EFI variables
+ use the eficonfig command.
+
config BOOTMETH_VBE
bool "Bootdev support for Verified Boot for Embedded"
depends on FIT
@@ -711,6 +688,100 @@
endif # BOOTSTD
+config BOOTM
+ bool "Support booting an application image from memory"
+ default y
+ help
+ This is the main boot implementation in U-Boot, supporting a wide
+ variety of features including FIT and legacy-image boot, kernel and
+ FDT selection, setting up of the command line for the OS and many
+ other features.
+
+ This option should normally be enabled. It is used to implement the
+ 'bootm' command.
+
+config BOOTM_LINUX
+ bool "Support booting Linux OS images"
+ depends on BOOTM || CMD_BOOTZ || CMD_BOOTI
+ default y
+ help
+ Support booting the Linux kernel directly via a command such as bootm
+ or booti or bootz.
+
+config BOOTM_NETBSD
+ bool "Support booting NetBSD (non-EFI) loader images"
+ depends on BOOTM
+ default y
+ help
+ Support booting NetBSD via the bootm command.
+
+config BOOTM_OPENRTOS
+ bool "Support booting OPENRTOS / FreeRTOS images"
+ depends on BOOTM
+ help
+ Support booting OPENRTOS / FreeRTOS via the bootm command.
+
+config BOOTM_OSE
+ bool "Support booting Enea OSE images"
+ depends on (ARM && (ARM64 || CPU_V7A || CPU_V7R) || SANDBOX || PPC || X86)
+ depends on BOOTM
+ help
+ Support booting Enea OSE images via the bootm command.
+
+config BOOTM_PLAN9
+ bool "Support booting Plan9 OS images"
+ depends on BOOTM
+ default y
+ help
+ Support booting Plan9 images via the bootm command.
+
+config BOOTM_RTEMS
+ bool "Support booting RTEMS OS images"
+ depends on BOOTM
+ default y
+ help
+ Support booting RTEMS images via the bootm command.
+
+config BOOTM_VXWORKS
+ bool "Support booting VxWorks OS images"
+ depends on BOOTM
+ default y
+ help
+ Support booting VxWorks images via the bootm command.
+
+config ANDROID_BOOT_IMAGE
+ bool "Android Boot Images"
+ default y if FASTBOOT
+ help
+ This enables support for booting images which use the Android
+ image format header.
+
+config TIMESTAMP
+ bool "Show image date and time when displaying image information"
+ default y if CMD_DATE
+ help
+ When CONFIG_TIMESTAMP is selected, the timestamp (date and time) of
+ an image is printed by image commands like bootm or iminfo. This
+ is shown as 'Timestamp: xxx' and 'Created: xxx'. If this option is
+ enabled, then U-Boot requires FITs to have a timestamp. If a FIT is
+ loaded that does not, the message 'Wrong FIT format: no timestamp'
+ is shown.
+
+config BUTTON_CMD
+ bool "Support for running a command if a button is held during boot"
+ depends on CMDLINE
+ depends on BUTTON
+ help
+ For many embedded devices it's useful to enter a special flashing mode
+ such as fastboot mode when a button is held during boot. This option
+ allows arbitrary commands to be assigned to specific buttons. These will
+ be run after "preboot" if the button is held. Configuration is done via
+ the environment variables "button_cmd_N_name" and "button_cmd_N" where n is
+ the button number (starting from 0). e.g:
+
+ "button_cmd_0_name=vol_down"
+ "button_cmd_0=fastboot usb 0"
+
config LEGACY_IMAGE_FORMAT
bool "Enable support for the legacy image format"
default y if !FIT_SIGNATURE && !TI_SECURE_DEVICE
@@ -755,7 +826,7 @@
config SYS_BOOTM_LEN
hex "Maximum size of a decompresed OS image"
- depends on CMD_BOOTM || CMD_BOOTI || CMD_BOOTZ || \
+ depends on BOOTM || CMD_BOOTI || CMD_BOOTZ || \
LEGACY_IMAGE_FORMAT || SPL_LEGACY_IMAGE_FORMAT
default 0x4000000 if PPC || ARM64
default 0x1000000 if X86 || ARCH_MX6 || ARCH_MX7
diff --git a/boot/Makefile b/boot/Makefile
index f0a279c..bf767fd 100644
--- a/boot/Makefile
+++ b/boot/Makefile
@@ -6,7 +6,7 @@
ifndef CONFIG_SPL_BUILD
obj-$(CONFIG_BOOT_RETRY) += bootretry.o
-obj-$(CONFIG_CMD_BOOTM) += bootm.o bootm_os.o
+obj-$(CONFIG_BOOTM) += bootm.o bootm_os.o
obj-$(CONFIG_CMD_BOOTZ) += bootm.o bootm_os.o
obj-$(CONFIG_CMD_BOOTI) += bootm.o bootm_os.o
@@ -34,8 +34,8 @@
obj-$(CONFIG_$(SPL_TPL_)BOOTMETH_SANDBOX) += bootmeth_sandbox.o
obj-$(CONFIG_$(SPL_TPL_)BOOTMETH_SCRIPT) += bootmeth_script.o
obj-$(CONFIG_$(SPL_TPL_)CEDIT) += cedit.o
+obj-$(CONFIG_$(SPL_TPL_)BOOTMETH_EFI_BOOTMGR) += bootmeth_efi_mgr.o
ifdef CONFIG_$(SPL_TPL_)BOOTSTD_FULL
-obj-$(CONFIG_EFI_BOOTMGR) += bootmeth_efi_mgr.o
obj-$(CONFIG_$(SPL_TPL_)EXPO) += bootflow_menu.o
obj-$(CONFIG_$(SPL_TPL_)BOOTSTD) += bootflow_menu.o
endif
diff --git a/boot/android_ab.c b/boot/android_ab.c
index c9df6d2..1e5aa81 100644
--- a/boot/android_ab.c
+++ b/boot/android_ab.c
@@ -187,13 +187,12 @@
bool dec_tries)
{
struct bootloader_control *abc = NULL;
+ struct bootloader_control *backup_abc = NULL;
u32 crc32_le;
int slot, i, ret;
bool store_needed = false;
+ bool valid_backup = false;
char slot_suffix[4];
-#if ANDROID_AB_BACKUP_OFFSET
- struct bootloader_control *backup_abc = NULL;
-#endif
ret = ab_control_create_from_disk(dev_desc, part_info, &abc, 0);
if (ret < 0) {
@@ -205,53 +204,49 @@
return ret;
}
-#if ANDROID_AB_BACKUP_OFFSET
- ret = ab_control_create_from_disk(dev_desc, part_info, &backup_abc,
- ANDROID_AB_BACKUP_OFFSET);
- if (ret < 0) {
- free(abc);
- return ret;
+ if (CONFIG_ANDROID_AB_BACKUP_OFFSET) {
+ ret = ab_control_create_from_disk(dev_desc, part_info, &backup_abc,
+ CONFIG_ANDROID_AB_BACKUP_OFFSET);
+ if (ret < 0) {
+ free(abc);
+ return ret;
+ }
}
-#endif
crc32_le = ab_control_compute_crc(abc);
if (abc->crc32_le != crc32_le) {
log_err("ANDROID: Invalid CRC-32 (expected %.8x, found %.8x),",
crc32_le, abc->crc32_le);
-#if ANDROID_AB_BACKUP_OFFSET
- crc32_le = ab_control_compute_crc(backup_abc);
- if (backup_abc->crc32_le != crc32_le) {
- log_err("ANDROID: Invalid backup CRC-32 ")
- log_err("expected %.8x, found %.8x),",
- crc32_le, backup_abc->crc32_le);
-#endif
-
- log_err("re-initializing A/B metadata.\n");
+ if (CONFIG_ANDROID_AB_BACKUP_OFFSET) {
+ crc32_le = ab_control_compute_crc(backup_abc);
+ if (backup_abc->crc32_le != crc32_le) {
+ log_err(" ANDROID: Invalid backup CRC-32 ");
+ log_err("(expected %.8x, found %.8x),",
+ crc32_le, backup_abc->crc32_le);
+ } else {
+ valid_backup = true;
+ log_info(" copying A/B metadata from backup.\n");
+ memcpy(abc, backup_abc, sizeof(*abc));
+ }
+ }
+ if (!valid_backup) {
+ log_err(" re-initializing A/B metadata.\n");
ret = ab_control_default(abc);
if (ret < 0) {
-#if ANDROID_AB_BACKUP_OFFSET
- free(backup_abc);
-#endif
+ if (CONFIG_ANDROID_AB_BACKUP_OFFSET)
+ free(backup_abc);
free(abc);
return -ENODATA;
}
-#if ANDROID_AB_BACKUP_OFFSET
- } else {
- /*
- * Backup is valid. Copy it to the primary
- */
- memcpy(abc, backup_abc, sizeof(*abc));
}
-#endif
store_needed = true;
}
if (abc->magic != BOOT_CTRL_MAGIC) {
log_err("ANDROID: Unknown A/B metadata: %.8x\n", abc->magic);
-#if ANDROID_AB_BACKUP_OFFSET
- free(backup_abc);
-#endif
+ if (CONFIG_ANDROID_AB_BACKUP_OFFSET)
+ free(backup_abc);
free(abc);
return -ENODATA;
}
@@ -259,9 +254,8 @@
if (abc->version > BOOT_CTRL_VERSION) {
log_err("ANDROID: Unsupported A/B metadata version: %.8x\n",
abc->version);
-#if ANDROID_AB_BACKUP_OFFSET
- free(backup_abc);
-#endif
+ if (CONFIG_ANDROID_AB_BACKUP_OFFSET)
+ free(backup_abc);
free(abc);
return -ENODATA;
}
@@ -338,30 +332,29 @@
abc->crc32_le = ab_control_compute_crc(abc);
ret = ab_control_store(dev_desc, part_info, abc, 0);
if (ret < 0) {
-#if ANDROID_AB_BACKUP_OFFSET
- free(backup_abc);
-#endif
+ if (CONFIG_ANDROID_AB_BACKUP_OFFSET)
+ free(backup_abc);
free(abc);
return ret;
}
}
-#if ANDROID_AB_BACKUP_OFFSET
- /*
- * If the backup doesn't match the primary, write the primary
- * to the backup offset
- */
- if (memcmp(backup_abc, abc, sizeof(*abc)) != 0) {
- ret = ab_control_store(dev_desc, part_info, abc,
- ANDROID_AB_BACKUP_OFFSET);
- if (ret < 0) {
- free(backup_abc);
- free(abc);
- return ret;
+ if (CONFIG_ANDROID_AB_BACKUP_OFFSET) {
+ /*
+ * If the backup doesn't match the primary, write the primary
+ * to the backup offset
+ */
+ if (memcmp(backup_abc, abc, sizeof(*abc)) != 0) {
+ ret = ab_control_store(dev_desc, part_info, abc,
+ CONFIG_ANDROID_AB_BACKUP_OFFSET);
+ if (ret < 0) {
+ free(backup_abc);
+ free(abc);
+ return ret;
+ }
}
+ free(backup_abc);
}
- free(backup_abc);
-#endif
free(abc);
diff --git a/boot/bootmeth_cros.c b/boot/bootmeth_cros.c
index cd72db8..f015f2e 100644
--- a/boot/bootmeth_cros.c
+++ b/boot/bootmeth_cros.c
@@ -432,9 +432,9 @@
}
if (IS_ENABLED(CONFIG_X86)) {
- ret = zboot_start(map_to_sysmem(bflow->buf), bflow->size, 0, 0,
- map_to_sysmem(bflow->x86_setup),
- bflow->cmdline);
+ ret = zboot_run(map_to_sysmem(bflow->buf), bflow->size, 0, 0,
+ map_to_sysmem(bflow->x86_setup),
+ bflow->cmdline);
} else {
ret = bootm_boot_start(map_to_sysmem(bflow->buf),
bflow->cmdline);
diff --git a/boot/bootmeth_efi.c b/boot/bootmeth_efi.c
index c4eb331..aebc520 100644
--- a/boot/bootmeth_efi.c
+++ b/boot/bootmeth_efi.c
@@ -14,6 +14,7 @@
#include <bootmeth.h>
#include <command.h>
#include <dm.h>
+#include <efi_default_filename.h>
#include <efi_loader.h>
#include <fs.h>
#include <malloc.h>
@@ -23,43 +24,7 @@
#include <pxe_utils.h>
#include <linux/sizes.h>
-#define EFI_DIRNAME "efi/boot/"
-
-/**
- * get_efi_leafname() - Get the leaf name for the EFI file we expect
- *
- * @str: Place to put leaf name for this architecture, e.g. "bootaa64.efi".
- * Must have at least 16 bytes of space
- * @max_len: Length of @str, must be >=16
- */
-static int get_efi_leafname(char *str, int max_len)
-{
- const char *base;
-
- if (max_len < 16)
- return log_msg_ret("spc", -ENOSPC);
- if (IS_ENABLED(CONFIG_ARM64))
- base = "bootaa64";
- else if (IS_ENABLED(CONFIG_ARM))
- base = "bootarm";
- else if (IS_ENABLED(CONFIG_X86_RUN_32BIT))
- base = "bootia32";
- else if (IS_ENABLED(CONFIG_X86_RUN_64BIT))
- base = "bootx64";
- else if (IS_ENABLED(CONFIG_ARCH_RV32I))
- base = "bootriscv32";
- else if (IS_ENABLED(CONFIG_ARCH_RV64I))
- base = "bootriscv64";
- else if (IS_ENABLED(CONFIG_SANDBOX))
- base = "bootsbox";
- else
- return -EINVAL;
-
- strcpy(str, base);
- strcat(str, ".efi");
-
- return 0;
-}
+#define EFI_DIRNAME "/EFI/BOOT/"
static int get_efi_pxe_arch(void)
{
@@ -259,10 +224,7 @@
return -ENOENT;
strcpy(fname, EFI_DIRNAME);
- ret = get_efi_leafname(fname + strlen(fname),
- sizeof(fname) - strlen(fname));
- if (ret)
- return log_msg_ret("leaf", ret);
+ strcat(fname, BOOTEFI_NAME);
if (bflow->blk)
desc = dev_get_uclass_plat(bflow->blk);
@@ -489,7 +451,7 @@
{ }
};
-U_BOOT_DRIVER(bootmeth_efi) = {
+U_BOOT_DRIVER(bootmeth_4efi) = {
.name = "bootmeth_efi",
.id = UCLASS_BOOTMETH,
.of_match = distro_efi_bootmeth_ids,
diff --git a/boot/bootmeth_efi_mgr.c b/boot/bootmeth_efi_mgr.c
index ed29d7e..b7d429f 100644
--- a/boot/bootmeth_efi_mgr.c
+++ b/boot/bootmeth_efi_mgr.c
@@ -114,7 +114,7 @@
{ }
};
-U_BOOT_DRIVER(bootmeth_efi_mgr) = {
+U_BOOT_DRIVER(bootmeth_3efi_mgr) = {
.name = "bootmeth_efi_mgr",
.id = UCLASS_BOOTMETH,
.of_match = efi_mgr_bootmeth_ids,
diff --git a/boot/bootmeth_pxe.c b/boot/bootmeth_pxe.c
index 8d489a1..70f693a 100644
--- a/boot/bootmeth_pxe.c
+++ b/boot/bootmeth_pxe.c
@@ -184,7 +184,7 @@
{ }
};
-U_BOOT_DRIVER(bootmeth_pxe) = {
+U_BOOT_DRIVER(bootmeth_zpxe) = {
.name = "bootmeth_pxe",
.id = UCLASS_BOOTMETH,
.of_match = extlinux_bootmeth_pxe_ids,
diff --git a/boot/pxe_utils.c b/boot/pxe_utils.c
index 9620562..d5e1bea 100644
--- a/boot/pxe_utils.c
+++ b/boot/pxe_utils.c
@@ -5,6 +5,7 @@
*/
#include <common.h>
+#include <bootm.h>
#include <command.h>
#include <dm.h>
#include <env.h>
@@ -470,6 +471,220 @@
#endif
/**
+ * calc_fdt_fname() - Figure out the filename to use for the FDT
+ *
+ * Determine the path to the FDT filename, based on the "fdtfile" environment
+ * variable. Use <soc>-<board>.dtb as a fallback
+ *
+ * @fdtdir: Directory to use for the FDT file
+ * Return: allocated filename (including directory), or NULL if out of memory
+ */
+static char *calc_fdt_fname(const char *fdtdir)
+{
+ char *fdtfile;
+ char *f1, *f2, *f3, *f4, *slash;
+ int len;
+
+ f1 = env_get("fdtfile");
+ if (f1) {
+ f2 = "";
+ f3 = "";
+ f4 = "";
+ } else {
+ /*
+ * For complex cases where this code doesn't generate the
+ * correct filename, the board code should set $fdtfile during
+ * early boot, or the boot scripts should set $fdtfile before
+ * invoking "pxe" or "sysboot".
+ */
+ f1 = env_get("soc");
+ f2 = "-";
+ f3 = env_get("board");
+ f4 = ".dtb";
+ if (!f1) {
+ f1 = "";
+ f2 = "";
+ }
+ if (!f3) {
+ f2 = "";
+ f3 = "";
+ }
+ }
+
+ len = strlen(fdtdir);
+ if (!len)
+ slash = "./";
+ else if (fdtdir[len - 1] != '/')
+ slash = "/";
+ else
+ slash = "";
+
+ len = strlen(fdtdir) + strlen(slash) + strlen(f1) + strlen(f2) +
+ strlen(f3) + strlen(f4) + 1;
+ fdtfile = malloc(len);
+ if (!fdtfile) {
+ printf("malloc fail (FDT filename)\n");
+ return NULL;
+ }
+
+ snprintf(fdtfile, len, "%s%s%s%s%s%s", fdtdir, slash, f1, f2, f3, f4);
+
+ return fdtfile;
+}
+
+/**
+ * label_run_boot() - Run the correct boot procedure
+ *
+ * fdt usage is optional:
+ * It handles the following scenarios.
+ *
+ * Scenario 1: If fdt_addr_r specified and "fdt" or "fdtdir" label is
+ * defined in pxe file, retrieve fdt blob from server. Pass fdt_addr_r to
+ * bootm, and adjust argc appropriately.
+ *
+ * If retrieve fails and no exact fdt blob is specified in pxe file with
+ * "fdt" label, try Scenario 2.
+ *
+ * Scenario 2: If there is an fdt_addr specified, pass it along to
+ * bootm, and adjust argc appropriately.
+ *
+ * Scenario 3: If there is an fdtcontroladdr specified, pass it along to
+ * bootm, and adjust argc appropriately, unless the image type is fitImage.
+ *
+ * Scenario 4: fdt blob is not available.
+ *
+ * @ctx: PXE context
+ * @label: Label to process
+ * @kernel_addr: string containing the kernel address / config
+ * @initrd_str: string containing the initrd address / size
+ * @initrd_addr_str: initrd address, or NULL if none
+ * @initrd_filesize: initrd size in bytes; only valid if initrd_addr_str is not
+ * NULL
+ * Returns does not return on success, otherwise returns 0 if a localboot
+ * label was processed, or 1 on error
+ */
+static int label_run_boot(struct pxe_context *ctx, struct pxe_label *label,
+ char *kernel_addr, char *initrd_str,
+ char *initrd_addr_str, char *initrd_filesize)
+{
+ struct bootm_info bmi;
+ const char *fdt_addr;
+ ulong kernel_addr_r;
+ void *buf;
+ int ret;
+
+ if (IS_ENABLED(CONFIG_BOOTM))
+ bootm_init(&bmi);
+
+ fdt_addr = env_get("fdt_addr_r");
+
+ /* For FIT, the label can be identical to kernel one */
+ if (label->fdt && !strcmp(label->kernel_label, label->fdt)) {
+ fdt_addr = kernel_addr;
+ /* if fdt label is defined then get fdt from server */
+ } else if (fdt_addr) {
+ char *fdtfile = NULL;
+ char *fdtfilefree = NULL;
+
+ if (label->fdt) {
+ if (IS_ENABLED(CONFIG_SUPPORT_PASSING_ATAGS)) {
+ if (strcmp("-", label->fdt))
+ fdtfile = label->fdt;
+ } else {
+ fdtfile = label->fdt;
+ }
+ } else if (label->fdtdir) {
+ fdtfilefree = calc_fdt_fname(label->fdtdir);
+ if (!fdtfilefree)
+ return -ENOMEM;
+ fdtfile = fdtfilefree;
+ }
+
+ if (fdtfile) {
+ int err = get_relfile_envaddr(ctx, fdtfile,
+ "fdt_addr_r", NULL);
+
+ free(fdtfilefree);
+ if (err < 0) {
+ fdt_addr = NULL;
+
+ if (label->fdt) {
+ printf("Skipping %s for failure retrieving FDT\n",
+ label->name);
+ return -ENOENT;
+ }
+
+ if (label->fdtdir) {
+ printf("Skipping fdtdir %s for failure retrieving dts\n",
+ label->fdtdir);
+ }
+ }
+
+ if (label->kaslrseed)
+ label_boot_kaslrseed();
+
+#ifdef CONFIG_OF_LIBFDT_OVERLAY
+ if (label->fdtoverlays)
+ label_boot_fdtoverlay(ctx, label);
+#endif
+ } else {
+ fdt_addr = NULL;
+ }
+ }
+
+ bmi.addr_img = kernel_addr;
+
+ if (initrd_addr_str)
+ bmi.conf_ramdisk = initrd_str;
+
+ if (!fdt_addr) {
+ if (IS_ENABLED(CONFIG_SUPPORT_PASSING_ATAGS)) {
+ if (strcmp("-", label->fdt))
+ fdt_addr = env_get("fdt_addr");
+ } else {
+ fdt_addr = env_get("fdt_addr");
+ }
+ }
+
+ kernel_addr_r = genimg_get_kernel_addr(kernel_addr);
+ buf = map_sysmem(kernel_addr_r, 0);
+
+ if (!fdt_addr && genimg_get_format(buf) != IMAGE_FORMAT_FIT) {
+ if (IS_ENABLED(CONFIG_SUPPORT_PASSING_ATAGS)) {
+ if (strcmp("-", label->fdt))
+ fdt_addr = env_get("fdtcontroladdr");
+ } else {
+ fdt_addr = env_get("fdtcontroladdr");
+ }
+ }
+
+ bmi.conf_fdt = fdt_addr;
+
+ /* Try bootm for legacy and FIT format image */
+ if (genimg_get_format(buf) != IMAGE_FORMAT_INVALID &&
+ IS_ENABLED(CONFIG_BOOTM))
+ ret = bootm_run(&bmi);
+ /* Try booting an AArch64 Linux kernel image */
+ else if (IS_ENABLED(CONFIG_BOOTM))
+ ret = booti_run(&bmi);
+ /* Try booting a Image */
+ else if (IS_ENABLED(CONFIG_BOOTM))
+ ret = bootz_run(&bmi);
+ /* Try booting an x86_64 Linux kernel image */
+ else if (IS_ENABLED(CONFIG_ZBOOT))
+ ret = zboot_run(hextoul(kernel_addr, NULL), 0,
+ initrd_addr_str ?
+ hextoul(initrd_addr_str, NULL) : 0,
+ initrd_addr_str ?
+ hextoul(initrd_filesize, NULL) : 0,
+ 0, NULL);
+
+ unmap_sysmem(buf);
+
+ return 0;
+}
+
+/**
* label_boot() - Boot according to the contents of a pxe_label
*
* If we can't boot for any reason, we return. A successful boot never
@@ -491,8 +706,6 @@
*/
static int label_boot(struct pxe_context *ctx, struct pxe_label *label)
{
- char *bootm_argv[] = { "bootm", NULL, NULL, NULL, NULL };
- char *zboot_argv[] = { "zboot", NULL, "0", NULL, NULL };
char *kernel_addr = NULL;
char *initrd_addr_str = NULL;
char initrd_filesize[10];
@@ -500,11 +713,7 @@
char mac_str[29] = "";
char ip_str[68] = "";
char *fit_addr = NULL;
- int bootm_argc = 2;
- int zboot_argc = 3;
- int len = 0;
- ulong kernel_addr_r;
- void *buf;
+ int ret;
label_print(label);
@@ -545,9 +754,10 @@
/* For FIT, the label can be identical to kernel one */
if (label->initrd && !strcmp(label->kernel_label, label->initrd)) {
- initrd_addr_str = kernel_addr;
+ initrd_addr_str = kernel_addr;
} else if (label->initrd) {
ulong size;
+
if (get_relfile_envaddr(ctx, label->initrd, "ramdisk_addr_r",
&size) < 0) {
printf("Skipping %s for failure retrieving initrd\n",
@@ -593,7 +803,7 @@
}
if (label->append)
- strncpy(bootargs, label->append, sizeof(bootargs));
+ strlcpy(bootargs, label->append, sizeof(bootargs));
strcat(bootargs, ip_str);
strcat(bootargs, mac_str);
@@ -604,180 +814,8 @@
printf("append: %s\n", finalbootargs);
}
- /*
- * fdt usage is optional:
- * It handles the following scenarios.
- *
- * Scenario 1: If fdt_addr_r specified and "fdt" or "fdtdir" label is
- * defined in pxe file, retrieve fdt blob from server. Pass fdt_addr_r to
- * bootm, and adjust argc appropriately.
- *
- * If retrieve fails and no exact fdt blob is specified in pxe file with
- * "fdt" label, try Scenario 2.
- *
- * Scenario 2: If there is an fdt_addr specified, pass it along to
- * bootm, and adjust argc appropriately.
- *
- * Scenario 3: If there is an fdtcontroladdr specified, pass it along to
- * bootm, and adjust argc appropriately, unless the image type is fitImage.
- *
- * Scenario 4: fdt blob is not available.
- */
- bootm_argv[3] = env_get("fdt_addr_r");
-
- /* For FIT, the label can be identical to kernel one */
- if (label->fdt && !strcmp(label->kernel_label, label->fdt)) {
- bootm_argv[3] = kernel_addr;
- /* if fdt label is defined then get fdt from server */
- } else if (bootm_argv[3]) {
- char *fdtfile = NULL;
- char *fdtfilefree = NULL;
-
- if (label->fdt) {
- if (IS_ENABLED(CONFIG_SUPPORT_PASSING_ATAGS)) {
- if (strcmp("-", label->fdt))
- fdtfile = label->fdt;
- } else {
- fdtfile = label->fdt;
- }
- } else if (label->fdtdir) {
- char *f1, *f2, *f3, *f4, *slash;
-
- f1 = env_get("fdtfile");
- if (f1) {
- f2 = "";
- f3 = "";
- f4 = "";
- } else {
- /*
- * For complex cases where this code doesn't
- * generate the correct filename, the board
- * code should set $fdtfile during early boot,
- * or the boot scripts should set $fdtfile
- * before invoking "pxe" or "sysboot".
- */
- f1 = env_get("soc");
- f2 = "-";
- f3 = env_get("board");
- f4 = ".dtb";
- if (!f1) {
- f1 = "";
- f2 = "";
- }
- if (!f3) {
- f2 = "";
- f3 = "";
- }
- }
-
- len = strlen(label->fdtdir);
- if (!len)
- slash = "./";
- else if (label->fdtdir[len - 1] != '/')
- slash = "/";
- else
- slash = "";
-
- len = strlen(label->fdtdir) + strlen(slash) +
- strlen(f1) + strlen(f2) + strlen(f3) +
- strlen(f4) + 1;
- fdtfilefree = malloc(len);
- if (!fdtfilefree) {
- printf("malloc fail (FDT filename)\n");
- goto cleanup;
- }
-
- snprintf(fdtfilefree, len, "%s%s%s%s%s%s",
- label->fdtdir, slash, f1, f2, f3, f4);
- fdtfile = fdtfilefree;
- }
-
- if (fdtfile) {
- int err = get_relfile_envaddr(ctx, fdtfile,
- "fdt_addr_r", NULL);
-
- free(fdtfilefree);
- if (err < 0) {
- bootm_argv[3] = NULL;
-
- if (label->fdt) {
- printf("Skipping %s for failure retrieving FDT\n",
- label->name);
- goto cleanup;
- }
-
- if (label->fdtdir) {
- printf("Skipping fdtdir %s for failure retrieving dts\n",
- label->fdtdir);
- }
- }
-
- if (label->kaslrseed)
- label_boot_kaslrseed();
-
-#ifdef CONFIG_OF_LIBFDT_OVERLAY
- if (label->fdtoverlays)
- label_boot_fdtoverlay(ctx, label);
-#endif
- } else {
- bootm_argv[3] = NULL;
- }
- }
-
- bootm_argv[1] = kernel_addr;
- zboot_argv[1] = kernel_addr;
-
- if (initrd_addr_str) {
- bootm_argv[2] = initrd_str;
- bootm_argc = 3;
-
- zboot_argv[3] = initrd_addr_str;
- zboot_argv[4] = initrd_filesize;
- zboot_argc = 5;
- }
-
- if (!bootm_argv[3]) {
- if (IS_ENABLED(CONFIG_SUPPORT_PASSING_ATAGS)) {
- if (strcmp("-", label->fdt))
- bootm_argv[3] = env_get("fdt_addr");
- } else {
- bootm_argv[3] = env_get("fdt_addr");
- }
- }
-
- kernel_addr_r = genimg_get_kernel_addr(kernel_addr);
- buf = map_sysmem(kernel_addr_r, 0);
-
- if (!bootm_argv[3] && genimg_get_format(buf) != IMAGE_FORMAT_FIT) {
- if (IS_ENABLED(CONFIG_SUPPORT_PASSING_ATAGS)) {
- if (strcmp("-", label->fdt))
- bootm_argv[3] = env_get("fdtcontroladdr");
- } else {
- bootm_argv[3] = env_get("fdtcontroladdr");
- }
- }
-
- if (bootm_argv[3]) {
- if (!bootm_argv[2])
- bootm_argv[2] = "-";
- bootm_argc = 4;
- }
-
- /* Try bootm for legacy and FIT format image */
- if (genimg_get_format(buf) != IMAGE_FORMAT_INVALID &&
- IS_ENABLED(CONFIG_CMD_BOOTM))
- do_bootm(ctx->cmdtp, 0, bootm_argc, bootm_argv);
- /* Try booting an AArch64 Linux kernel image */
- else if (IS_ENABLED(CONFIG_CMD_BOOTI))
- do_booti(ctx->cmdtp, 0, bootm_argc, bootm_argv);
- /* Try booting a Image */
- else if (IS_ENABLED(CONFIG_CMD_BOOTZ))
- do_bootz(ctx->cmdtp, 0, bootm_argc, bootm_argv);
- /* Try booting an x86_64 Linux kernel image */
- else if (IS_ENABLED(CONFIG_CMD_ZBOOT))
- do_zboot_parent(ctx->cmdtp, 0, zboot_argc, zboot_argv, NULL);
-
- unmap_sysmem(buf);
+ ret = label_run_boot(ctx, label, kernel_addr, initrd_str,
+ initrd_addr_str, initrd_filesize);
cleanup:
free(fit_addr);
diff --git a/cmd/Kconfig b/cmd/Kconfig
index 102f62a..3830519 100644
--- a/cmd/Kconfig
+++ b/cmd/Kconfig
@@ -189,6 +189,17 @@
Show the command-line history, i.e. a list of commands that are in
the history buffer.
+config CMD_HISTORY_USE_CALLOC
+ bool "dynamically allocate memory"
+ default y
+ depends on CMD_HISTORY
+ help
+ Saying Y to this will use calloc to get the space for history
+ storing. Otherwise the history buffer will be an uninitialized
+ static array directly, without the memory allocation, and it is
+ writable after relocation to RAM. If u-boot is running from ROM
+ all the time or unsure, say Y to this.
+
config CMD_LICENSE
bool "license"
select BUILD_BIN2C
@@ -251,6 +262,7 @@
config CMD_BOOTM
bool "bootm"
+ depends on BOOTM
default y
help
Boot an application image from the memory.
@@ -322,48 +334,6 @@
help
Boot an AArch64 Linux Kernel image from memory.
-config BOOTM_LINUX
- bool "Support booting Linux OS images"
- depends on CMD_BOOTM || CMD_BOOTZ || CMD_BOOTI
- default y
- help
- Support booting the Linux kernel directly via a command such as bootm
- or booti or bootz.
-
-config BOOTM_NETBSD
- bool "Support booting NetBSD (non-EFI) loader images"
- depends on CMD_BOOTM
- default y
- help
- Support booting NetBSD via the bootm command.
-
-config BOOTM_OPENRTOS
- bool "Support booting OPENRTOS / FreeRTOS images"
- depends on CMD_BOOTM
- help
- Support booting OPENRTOS / FreeRTOS via the bootm command.
-
-config BOOTM_OSE
- bool "Support booting Enea OSE images"
- depends on (ARM && (ARM64 || CPU_V7A || CPU_V7R) || SANDBOX || PPC || X86)
- depends on CMD_BOOTM
- help
- Support booting Enea OSE images via the bootm command.
-
-config BOOTM_PLAN9
- bool "Support booting Plan9 OS images"
- depends on CMD_BOOTM
- default y
- help
- Support booting Plan9 images via the bootm command.
-
-config BOOTM_RTEMS
- bool "Support booting RTEMS OS images"
- depends on CMD_BOOTM
- default y
- help
- Support booting RTEMS images via the bootm command.
-
config CMD_SEAMA
bool "Support read SEAMA NAND images"
depends on MTD_RAW_NAND
@@ -380,13 +350,6 @@
is used to boot. Updating the parameters is not currently
supported.
-config BOOTM_VXWORKS
- bool "Support booting VxWorks OS images"
- depends on CMD_BOOTM
- default y
- help
- Support booting VxWorks images via the bootm command.
-
config CMD_BOOTEFI
bool "bootefi"
depends on EFI_LOADER
@@ -479,6 +442,17 @@
help
Boot an ELF/vxWorks image from the memory.
+config CMD_ELF_FDT_SETUP
+ bool "Flattened Device Tree setup in bootelf cmd"
+ default n
+ depends on CMD_ELF
+ select LIB_LIBFDT
+ select LMB
+ help
+ Do FDT setup in bootelf command optionally by param -d, which
+ allows to bring additional system info (e.g. /memory node) to
+ the Operating System or application.
+
config CMD_FDT
bool "Flattened Device Tree utility commands"
default y
@@ -590,6 +564,8 @@
config CMD_ZBOOT
bool "zboot - x86 boot command"
+ depends on ZBOOT
+ default y
help
With x86 machines it is common to boot a bzImage file which
contains both a kernel and a setup.bin file. The latter includes
diff --git a/cmd/acpi.c b/cmd/acpi.c
index 65caaa5..928e5dc 100644
--- a/cmd/acpi.c
+++ b/cmd/acpi.c
@@ -32,7 +32,7 @@
if (has_hdr) {
printf(" v%02d %.6s %.8s %x %.4s %x\n", hdr->revision,
hdr->oem_id, hdr->oem_table_id, hdr->oem_revision,
- hdr->aslc_id, hdr->aslc_revision);
+ hdr->creator_id, hdr->creator_revision);
} else {
printf("\n");
}
diff --git a/cmd/bootefi.c b/cmd/bootefi.c
index 9cf9027..578dbb1 100644
--- a/cmd/bootefi.c
+++ b/cmd/bootefi.c
@@ -154,9 +154,7 @@
!strcmp(argv[1], "bootmgr")) {
ret = efi_bootmgr_run(fdt);
- if (ret == EFI_INVALID_PARAMETER)
- return CMD_RET_USAGE;
- else if (ret)
+ if (ret != EFI_SUCCESS)
return CMD_RET_FAILURE;
return CMD_RET_SUCCESS;
@@ -173,9 +171,7 @@
}
ret = efi_install_fdt(fdt);
- if (ret == EFI_INVALID_PARAMETER)
- return CMD_RET_USAGE;
- else if (ret != EFI_SUCCESS)
+ if (ret != EFI_SUCCESS)
return CMD_RET_FAILURE;
return do_efi_selftest();
@@ -218,9 +214,7 @@
ret = efi_binary_run(image_buf, size, fdt);
- if (ret == EFI_INVALID_PARAMETER)
- return CMD_RET_USAGE;
- else if (ret)
+ if (ret != EFI_SUCCESS)
return CMD_RET_FAILURE;
return CMD_RET_SUCCESS;
diff --git a/cmd/elf.c b/cmd/elf.c
index b7b9f50..df4354d 100644
--- a/cmd/elf.c
+++ b/cmd/elf.c
@@ -38,6 +38,10 @@
/* Interpreter command to boot an arbitrary ELF image from memory */
int do_bootelf(struct cmd_tbl *cmdtp, int flag, int argc, char *const argv[])
{
+#if CONFIG_IS_ENABLED(CMD_ELF_FDT_SETUP)
+ struct bootm_headers img = {0};
+ unsigned long fdt_addr = 0; /* Address of the FDT */
+#endif
unsigned long addr; /* Address of the ELF image */
unsigned long rc; /* Return value from user code */
char *sload = NULL;
@@ -46,13 +50,25 @@
/* Consume 'bootelf' */
argc--; argv++;
- /* Check for flag. */
+ /* Check for [-p|-s] flag. */
if (argc >= 1 && (argv[0][0] == '-' && \
(argv[0][1] == 'p' || argv[0][1] == 's'))) {
sload = argv[0];
/* Consume flag. */
argc--; argv++;
}
+
+#if CONFIG_IS_ENABLED(CMD_ELF_FDT_SETUP)
+ /* Check for [-d fdt_addr_r] option. */
+ if ((argc >= 2) && (argv[0][0] == '-') && (argv[0][1] == 'd')) {
+ if (strict_strtoul(argv[1], 16, &fdt_addr) != 0)
+ return CMD_RET_USAGE;
+ /* Consume option. */
+ argc -= 2;
+ argv += 2;
+ }
+#endif
+
/* Check for address. */
if (argc >= 1 && strict_strtoul(argv[0], 16, &addr) != -EINVAL) {
/* Consume address */
@@ -68,6 +84,16 @@
else
addr = load_elf_image_shdr(addr);
+#if CONFIG_IS_ENABLED(CMD_ELF_FDT_SETUP)
+ if (fdt_addr) {
+ printf("## Setting up FDT at 0x%08lx ...\n", fdt_addr);
+ flush();
+
+ if (image_setup_libfdt(&img, (void *)fdt_addr, NULL))
+ return 1;
+ }
+#endif
+
if (!env_get_autostart())
return rcode;
@@ -298,9 +324,16 @@
U_BOOT_CMD(
bootelf, CONFIG_SYS_MAXARGS, 0, do_bootelf,
"Boot from an ELF image in memory",
- "[-p|-s] [address]\n"
+ "[-p|-s] "
+#if CONFIG_IS_ENABLED(CMD_ELF_FDT_SETUP)
+ "[-d fdt_addr_r] "
+#endif
+ "[address]\n"
"\t- load ELF image at [address] via program headers (-p)\n"
- "\t or via section headers (-s)"
+ "\t or via section headers (-s)\n"
+#if CONFIG_IS_ENABLED(CMD_ELF_FDT_SETUP)
+ "\t- setup FDT image at [fdt_addr_r] (-d)"
+#endif
);
U_BOOT_CMD(
diff --git a/cmd/fastboot.c b/cmd/fastboot.c
index c3c1923..792e83d 100644
--- a/cmd/fastboot.c
+++ b/cmd/fastboot.c
@@ -159,7 +159,7 @@
return CMD_RET_USAGE;
}
- fastboot_init((void *)buf_addr, buf_size);
+ fastboot_init(buf_addr, buf_size);
if (!strcmp(argv[1], "udp"))
return do_fastboot_udp(argc, argv, buf_addr, buf_size);
diff --git a/cmd/pmic.c b/cmd/pmic.c
index 49a405f..c9e9730 100644
--- a/cmd/pmic.c
+++ b/cmd/pmic.c
@@ -225,6 +225,6 @@
"list - list pmic devices\n"
"pmic dev [name] - show or [set] operating PMIC device\n"
"pmic dump - dump registers\n"
- "pmic read address - read byte of register at address\n"
- "pmic write address - write byte to register at address\n"
+ "pmic read <reg> - read byte of 'reg' register\n"
+ "pmic write <reg> <byte> - write 'byte' byte to 'reg' register\n"
);
diff --git a/cmd/riscv/sbi.c b/cmd/riscv/sbi.c
index 9daf0e2..bd9d9c4 100644
--- a/cmd/riscv/sbi.c
+++ b/cmd/riscv/sbi.c
@@ -81,6 +81,7 @@
break;
switch (impl_id) {
case 1: /* OpenSBI */
+ case 8: /* PolarFire Hart Software Services */
printf("%ld.%ld",
vers >> 16, vers & 0xffff);
break;
@@ -99,7 +100,7 @@
}
}
if (i == ARRAY_SIZE(implementations))
- printf("Unknown implementation ID %ld", ret);
+ printf("\nUnknown implementation ID 0x%x", impl_id);
}
printf("\nMachine:\n");
ret = sbi_get_mvendorid(&mvendorid);
diff --git a/cmd/rng.c b/cmd/rng.c
index 52f722c..e5ab868 100644
--- a/cmd/rng.c
+++ b/cmd/rng.c
@@ -17,7 +17,23 @@
u8 buf[64];
int devnum;
struct udevice *dev;
- int ret = CMD_RET_SUCCESS;
+ int ret = CMD_RET_SUCCESS, err;
+
+ if (argc == 2 && !strcmp(argv[1], "list")) {
+ int idx = 0;
+
+ uclass_foreach_dev_probe(UCLASS_RNG, dev) {
+ idx++;
+ printf("RNG #%d - %s\n", dev->seq_, dev->name);
+ }
+
+ if (!idx) {
+ log_err("No RNG device\n");
+ return CMD_RET_FAILURE;
+ }
+
+ return CMD_RET_SUCCESS;
+ }
switch (argc) {
case 1:
@@ -46,8 +62,9 @@
n = min(n, sizeof(buf));
- if (dm_rng_read(dev, buf, n)) {
- printf("Reading RNG failed\n");
+ err = dm_rng_read(dev, buf, n);
+ if (err) {
+ puts(err == -EINTR ? "Abort\n" : "Reading RNG failed\n");
ret = CMD_RET_FAILURE;
} else {
print_hex_dump_bytes("", DUMP_PREFIX_OFFSET, buf, n);
@@ -56,12 +73,9 @@
return ret;
}
-U_BOOT_LONGHELP(rng,
- "[dev [n]]\n"
- " - print n random bytes(max 64) read from dev\n");
-
U_BOOT_CMD(
rng, 3, 0, do_rng,
"print bytes from the hardware random number generator",
- rng_help_text
+ "list - list all the probed rng devices\n"
+ "rng [dev] [n] - print n random bytes(max 64) read from dev\n"
);
diff --git a/cmd/smbios.c b/cmd/smbios.c
index 66f6b76..d3bd8b1 100644
--- a/cmd/smbios.c
+++ b/cmd/smbios.c
@@ -14,6 +14,18 @@
DECLARE_GLOBAL_DATA_PTR;
+static const char * const wakeup_type_strings[] = {
+ "Reserved", /* 0x00 */
+ "Other", /* 0x01 */
+ "Unknown", /* 0x02 */
+ "APM Timer", /* 0x03 */
+ "Modem Ring", /* 0x04 */
+ "Lan Remote", /* 0x05 */
+ "Power Switch", /* 0x06 */
+ "PCI PME#", /* 0x07 */
+ "AC Power Restored", /* 0x08 */
+};
+
/**
* smbios_get_string() - get SMBIOS string from table
*
@@ -72,6 +84,14 @@
printf("\t%s: %s\n", label, smbios_get_string(table, index));
}
+const char *smbios_wakeup_type_str(u8 wakeup_type)
+{
+ if (wakeup_type >= ARRAY_SIZE(wakeup_type_strings))
+ /* Values over 0x08 are reserved. */
+ wakeup_type = 0;
+ return wakeup_type_strings[wakeup_type];
+}
+
static void smbios_print_type1(struct smbios_type1 *table)
{
printf("System Information\n");
@@ -81,11 +101,12 @@
smbios_print_str("Serial Number", table, table->serial_number);
if (table->length >= 0x19) {
printf("\tUUID: %pUl\n", table->uuid);
- smbios_print_str("Wake Up Type", table, table->serial_number);
+ printf("\tWake-up Type: %s\n",
+ smbios_wakeup_type_str(table->wakeup_type));
}
if (table->length >= 0x1b) {
- smbios_print_str("Serial Number", table, table->serial_number);
smbios_print_str("SKU Number", table, table->sku_number);
+ smbios_print_str("Family", table, table->family);
}
}
diff --git a/cmd/sysboot.c b/cmd/sysboot.c
index 63a7806..d14c570 100644
--- a/cmd/sysboot.c
+++ b/cmd/sysboot.c
@@ -77,6 +77,10 @@
if (argc < 6) {
filename = env_get("bootfile");
+ if (!filename) {
+ printf("Specify a filename or set the ${bootfile} environment variable\n");
+ return 1;
+ }
} else {
filename = argv[5];
env_set("bootfile", filename);
diff --git a/cmd/usb_mass_storage.c b/cmd/usb_mass_storage.c
index a8ddeb4..751701f 100644
--- a/cmd/usb_mass_storage.c
+++ b/cmd/usb_mass_storage.c
@@ -88,10 +88,6 @@
if (!strchr(devnum_part_str, ':'))
partnum = 0;
- /* f_mass_storage.c assumes SECTOR_SIZE sectors */
- if (block_dev->blksz != SECTOR_SIZE)
- goto cleanup;
-
ums_new = realloc(ums, (ums_count + 1) * sizeof(*ums));
if (!ums_new)
goto cleanup;
diff --git a/cmd/x86/Makefile b/cmd/x86/Makefile
index 5f82204..b1f39d3 100644
--- a/cmd/x86/Makefile
+++ b/cmd/x86/Makefile
@@ -5,3 +5,4 @@
obj-$(CONFIG_CMD_EXCEPTION) += exception.o
obj-$(CONFIG_USE_HOB) += hob.o
obj-$(CONFIG_HAVE_FSP) += fsp.o
+obj-$(CONFIG_CMD_ZBOOT) += zboot.o
diff --git a/cmd/x86/zboot.c b/cmd/x86/zboot.c
new file mode 100644
index 0000000..addf28c
--- /dev/null
+++ b/cmd/x86/zboot.c
@@ -0,0 +1,182 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (c) 2011 The Chromium OS Authors.
+ * (C) Copyright 2002
+ * Daniel Engström, Omicron Ceti AB, <daniel@omicron.se>
+ */
+
+#include <command.h>
+#include <mapmem.h>
+#include <vsprintf.h>
+#include <asm/zimage.h>
+
+static int do_zboot_start(struct cmd_tbl *cmdtp, int flag, int argc,
+ char *const argv[])
+{
+ ulong bzimage_addr = 0, bzimage_size, initrd_addr, initrd_size;
+ ulong base_addr;
+ const char *s, *cmdline;
+
+ /* argv[1] holds the address of the bzImage */
+ s = cmd_arg1(argc, argv) ? : env_get("fileaddr");
+ if (s)
+ bzimage_addr = hextoul(s, NULL);
+ bzimage_size = argc > 2 ? hextoul(argv[2], NULL) : 0;
+ initrd_addr = argc > 3 ? hextoul(argv[3], NULL) : 0;
+ initrd_size = argc > 4 ? hextoul(argv[4], NULL) : 0;
+ base_addr = argc > 5 ? hextoul(argv[5], NULL) : 0;
+ cmdline = argc > 6 ? env_get(argv[6]) : NULL;
+
+ zboot_start(bzimage_addr, bzimage_size, initrd_addr, initrd_size,
+ base_addr, cmdline);
+
+ return 0;
+}
+
+static int do_zboot_load(struct cmd_tbl *cmdtp, int flag, int argc,
+ char *const argv[])
+{
+ int ret;
+
+ ret = zboot_load();
+ if (ret)
+ return ret;
+
+ return 0;
+}
+
+static int do_zboot_setup(struct cmd_tbl *cmdtp, int flag, int argc,
+ char *const argv[])
+{
+ if (!state.base_ptr) {
+ printf("base is not set: use 'zboot load' first\n");
+ return CMD_RET_FAILURE;
+ }
+ if (zboot_setup()) {
+ puts("Setting up boot parameters failed ...\n");
+ return CMD_RET_FAILURE;
+ }
+
+ if (zboot_setup())
+ return CMD_RET_FAILURE;
+
+ return 0;
+}
+
+static int do_zboot_info(struct cmd_tbl *cmdtp, int flag, int argc,
+ char *const argv[])
+{
+ zboot_info();
+
+ return 0;
+}
+
+static int do_zboot_go(struct cmd_tbl *cmdtp, int flag, int argc,
+ char *const argv[])
+{
+ int ret;
+
+ ret = zboot_go();
+ if (ret) {
+ printf("Kernel returned! (err=%d)\n", ret);
+ return CMD_RET_FAILURE;
+ }
+
+ return 0;
+}
+
+static int do_zboot_dump(struct cmd_tbl *cmdtp, int flag, int argc,
+ char *const argv[])
+{
+ struct boot_params *base_ptr = state.base_ptr;
+
+ if (argc > 1)
+ base_ptr = (void *)hextoul(argv[1], NULL);
+ if (!base_ptr) {
+ printf("No zboot setup_base\n");
+ return CMD_RET_FAILURE;
+ }
+ zimage_dump(base_ptr, true);
+
+ return 0;
+}
+
+/* Note: This defines the complete_zboot() function */
+U_BOOT_SUBCMDS(zboot,
+ U_BOOT_CMD_MKENT(start, 8, 1, do_zboot_start, "", ""),
+ U_BOOT_CMD_MKENT(load, 1, 1, do_zboot_load, "", ""),
+ U_BOOT_CMD_MKENT(setup, 1, 1, do_zboot_setup, "", ""),
+ U_BOOT_CMD_MKENT(info, 1, 1, do_zboot_info, "", ""),
+ U_BOOT_CMD_MKENT(go, 1, 1, do_zboot_go, "", ""),
+ U_BOOT_CMD_MKENT(dump, 2, 1, do_zboot_dump, "", ""),
+)
+
+int do_zboot_states(struct cmd_tbl *cmdtp, int flag, int argc,
+ char *const argv[], int state_mask)
+{
+ int ret;
+
+ if (flag & ZBOOT_STATE_START)
+ ret = do_zboot_start(cmdtp, flag, argc, argv);
+ if (!ret && (flag & ZBOOT_STATE_LOAD))
+ ret = do_zboot_load(cmdtp, flag, argc, argv);
+ if (!ret && (flag & ZBOOT_STATE_SETUP))
+ ret = do_zboot_setup(cmdtp, flag, argc, argv);
+ if (!ret && (flag & ZBOOT_STATE_INFO))
+ ret = do_zboot_info(cmdtp, flag, argc, argv);
+ if (!ret && (flag & ZBOOT_STATE_GO))
+ ret = do_zboot_go(cmdtp, flag, argc, argv);
+ if (ret)
+ return ret;
+
+ return 0;
+}
+
+int do_zboot_parent(struct cmd_tbl *cmdtp, int flag, int argc,
+ char *const argv[], int *repeatable)
+{
+ /* determine if we have a sub command */
+ if (argc > 1) {
+ char *endp;
+
+ hextoul(argv[1], &endp);
+ /*
+ * endp pointing to nul means that argv[1] was just a valid
+ * number, so pass it along to the normal processing
+ */
+ if (*endp)
+ return do_zboot(cmdtp, flag, argc, argv, repeatable);
+ }
+
+ do_zboot_states(cmdtp, flag, argc, argv, ZBOOT_STATE_START |
+ ZBOOT_STATE_LOAD | ZBOOT_STATE_SETUP |
+ ZBOOT_STATE_INFO | ZBOOT_STATE_GO);
+
+ return CMD_RET_FAILURE;
+}
+
+U_BOOT_CMDREP_COMPLETE(
+ zboot, 8, do_zboot_parent, "Boot bzImage",
+ "[addr] [size] [initrd addr] [initrd size] [setup] [cmdline]\n"
+ " addr - The optional starting address of the bzimage.\n"
+ " If not set it defaults to the environment\n"
+ " variable \"fileaddr\".\n"
+ " size - The optional size of the bzimage. Defaults to\n"
+ " zero.\n"
+ " initrd addr - The address of the initrd image to use, if any.\n"
+ " initrd size - The size of the initrd image to use, if any.\n"
+ " setup - The address of the kernel setup region, if this\n"
+ " is not at addr\n"
+ " cmdline - Environment variable containing the kernel\n"
+ " command line, to override U-Boot's normal\n"
+ " cmdline generation\n"
+ "\n"
+ "Sub-commands to do part of the zboot sequence:\n"
+ "\tstart [addr [arg ...]] - specify arguments\n"
+ "\tload - load OS image\n"
+ "\tsetup - set up table\n"
+ "\tinfo - show summary info\n"
+ "\tgo - start OS\n"
+ "\tdump [addr] - dump info (optional address of boot params)",
+ complete_zboot
+);
diff --git a/common/button_cmd.c b/common/button_cmd.c
index b6a8434..8642c26 100644
--- a/common/button_cmd.c
+++ b/common/button_cmd.c
@@ -33,7 +33,7 @@
static int get_button_cmd(int n, struct button_cmd *cmd)
{
const char *cmd_str;
- struct udevice *btn;
+ struct udevice *btn = NULL;
char buf[24];
snprintf(buf, sizeof(buf), "button_cmd_%d_name", n);
diff --git a/common/cli_readline.c b/common/cli_readline.c
index 2507be2..cf4339d 100644
--- a/common/cli_readline.c
+++ b/common/cli_readline.c
@@ -86,6 +86,9 @@
static int hist_cur = -1;
static unsigned hist_num;
+#ifndef CONFIG_CMD_HISTORY_USE_CALLOC
+static char hist_data[HIST_MAX][HIST_SIZE + 1];
+#endif
static char *hist_list[HIST_MAX];
#define add_idx_minus_one() ((hist_add_idx == 0) ? hist_max : hist_add_idx-1)
@@ -100,20 +103,26 @@
static int hist_init(void)
{
- unsigned char *hist;
int i;
- hist_max = 0;
- hist_add_idx = 0;
- hist_cur = -1;
- hist_num = 0;
-
- hist = calloc(HIST_MAX, HIST_SIZE + 1);
+#ifndef CONFIG_CMD_HISTORY_USE_CALLOC
+ for (i = 0; i < HIST_MAX; i++) {
+ hist_list[i] = hist_data[i];
+ hist_list[i][0] = '\0';
+ }
+#else
+ unsigned char *hist = calloc(HIST_MAX, HIST_SIZE + 1);
if (!hist)
- return -ENOMEM;
+ panic("%s: calloc: out of memory!\n", __func__);
for (i = 0; i < HIST_MAX; i++)
hist_list[i] = hist + (i * (HIST_SIZE + 1));
+#endif
+
+ hist_max = 0;
+ hist_add_idx = 0;
+ hist_cur = -1;
+ hist_num = 0;
return 0;
}
@@ -643,10 +652,15 @@
static int initted;
/*
- * History uses a global array which is not
- * writable until after relocation to RAM.
- * Revert to non-history version if still
- * running from flash.
+ * Say N to CMD_HISTORY_USE_CALLOC will skip runtime
+ * allocation for the history buffer and directly
+ * use an uninitialized static array as the buffer.
+ * Doing this might have better performance and not
+ * increase the binary file's size, as it only marks
+ * the size. However, the array is only writable after
+ * relocation to RAM. If u-boot is running from ROM
+ * all the time, consider say Y to CMD_HISTORY_USE_CALLOC
+ * or disable CMD_HISTORY.
*/
if (IS_ENABLED(CONFIG_CMDLINE_EDITING) && (gd->flags & GD_FLG_RELOC)) {
if (!initted) {
diff --git a/common/spl/spl_fit.c b/common/spl/spl_fit.c
index 872df0c..e5195d4 100644
--- a/common/spl/spl_fit.c
+++ b/common/spl/spl_fit.c
@@ -550,7 +550,12 @@
buf = malloc_cache_aligned(size);
if (!buf) {
pr_err("Could not get FIT buffer of %lu bytes\n", (ulong)size);
- pr_err("\tcheck CONFIG_SPL_SYS_MALLOC_SIZE\n");
+
+ if (IS_ENABLED(CONFIG_SPL_SYS_MALLOC))
+ pr_err("\tcheck CONFIG_SPL_SYS_MALLOC_SIZE\n");
+ else
+ pr_err("\tcheck CONFIG_SPL_SYS_MALLOC_F_LEN\n");
+
buf = spl_get_load_buffer(0, size);
}
return buf;
diff --git a/common/spl/spl_opensbi.c b/common/spl/spl_opensbi.c
index 8127ebc..ec62aab 100644
--- a/common/spl/spl_opensbi.c
+++ b/common/spl/spl_opensbi.c
@@ -66,7 +66,7 @@
* Moving DTB in front of the kernel can avoid the error.
*/
#if CONFIG_IS_ENABLED(LOAD_FIT_OPENSBI_OS_BOOT) && \
- CONFIG_IS_ENABLED(PAYLOAD_ARGS_ADDR)
+ CONFIG_VAL(PAYLOAD_ARGS_ADDR)
memcpy((void *)CONFIG_SPL_PAYLOAD_ARGS_ADDR, spl_image->fdt_addr,
fdt_totalsize(spl_image->fdt_addr));
spl_image->fdt_addr = map_sysmem(CONFIG_SPL_PAYLOAD_ARGS_ADDR, 0);
diff --git a/configs/SBx81LIFKW_defconfig b/configs/SBx81LIFKW_defconfig
index cc17a8b..977daf9 100644
--- a/configs/SBx81LIFKW_defconfig
+++ b/configs/SBx81LIFKW_defconfig
@@ -6,6 +6,7 @@
CONFIG_SYS_KWD_CONFIG="board/alliedtelesis/SBx81LIFKW/kwbimage.cfg"
CONFIG_TEXT_BASE=0x00600000
CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0xc8012000
+# CONFIG_OF_UPSTREAM is not set
CONFIG_TARGET_SBx81LIFKW=y
CONFIG_ENV_SIZE=0x2000
CONFIG_ENV_OFFSET=0xC0000
diff --git a/configs/SBx81LIFXCAT_defconfig b/configs/SBx81LIFXCAT_defconfig
index 0612723..9bc8614 100644
--- a/configs/SBx81LIFXCAT_defconfig
+++ b/configs/SBx81LIFXCAT_defconfig
@@ -6,6 +6,7 @@
CONFIG_SYS_KWD_CONFIG="board/alliedtelesis/SBx81LIFXCAT/kwbimage.cfg"
CONFIG_TEXT_BASE=0x00600000
CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0xc8012000
+# CONFIG_OF_UPSTREAM is not set
CONFIG_TARGET_SBx81LIFXCAT=y
CONFIG_ENV_SIZE=0x2000
CONFIG_ENV_OFFSET=0xC0000
diff --git a/configs/am62x_beagleplay_a53_defconfig b/configs/am62x_beagleplay_a53_defconfig
index 8878450..d9751bc 100644
--- a/configs/am62x_beagleplay_a53_defconfig
+++ b/configs/am62x_beagleplay_a53_defconfig
@@ -88,9 +88,9 @@
CONFIG_MMC_SDHCI_AM654=y
CONFIG_PHY_REALTEK=y
CONFIG_PHY_TI=y
-CONFIG_PHY_FIXED=y
CONFIG_TI_AM65_CPSW_NUSS=y
CONFIG_PHY=y
+CONFIG_DM_ETH_PHY=y
CONFIG_PINCTRL=y
CONFIG_SPL_PINCTRL=y
CONFIG_PINCTRL_SINGLE=y
diff --git a/configs/am64x_evm_a53_defconfig b/configs/am64x_evm_a53_defconfig
index ad5472c..b7057be 100644
--- a/configs/am64x_evm_a53_defconfig
+++ b/configs/am64x_evm_a53_defconfig
@@ -16,7 +16,7 @@
CONFIG_ENV_SIZE=0x20000
CONFIG_DM_GPIO=y
CONFIG_SPL_DM_SPI=y
-CONFIG_DEFAULT_DEVICE_TREE="k3-am642-evm"
+CONFIG_DEFAULT_DEVICE_TREE="ti/k3-am642-evm"
CONFIG_SPL_TEXT_BASE=0x80080000
CONFIG_OF_LIBFDT_OVERLAY=y
CONFIG_DM_RESET=y
@@ -74,7 +74,7 @@
CONFIG_CMD_REGULATOR=y
CONFIG_OF_CONTROL=y
CONFIG_SPL_OF_CONTROL=y
-CONFIG_OF_LIST="k3-am642-evm k3-am642-sk"
+CONFIG_OF_LIST="ti/k3-am642-evm ti/k3-am642-sk"
CONFIG_MULTI_DTB_FIT=y
CONFIG_SPL_MULTI_DTB_FIT=y
CONFIG_SPL_MULTI_DTB_FIT_NO_COMPRESSION=y
@@ -170,3 +170,4 @@
CONFIG_USB_FUNCTION_MASS_STORAGE=y
CONFIG_SPL_DFU=y
CONFIG_FS_FAT_MAX_CLUSTSIZE=16384
+CONFIG_OF_UPSTREAM=y
diff --git a/configs/anbernic-rgxx3-rk3566_defconfig b/configs/anbernic-rgxx3-rk3566_defconfig
index ed6643d..c8c9238 100644
--- a/configs/anbernic-rgxx3-rk3566_defconfig
+++ b/configs/anbernic-rgxx3-rk3566_defconfig
@@ -2,29 +2,24 @@
CONFIG_SKIP_LOWLEVEL_INIT=y
CONFIG_COUNTER_FREQUENCY=24000000
CONFIG_ARCH_ROCKCHIP=y
-CONFIG_TEXT_BASE=0x00a00000
-CONFIG_SPL_LIBCOMMON_SUPPORT=y
-CONFIG_SPL_LIBGENERIC_SUPPORT=y
+CONFIG_SPL_GPIO=y
CONFIG_NR_DRAM_BANKS=2
-CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y
-CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0xc00000
CONFIG_DEFAULT_DEVICE_TREE="rk3566-anbernic-rgxx3"
CONFIG_ROCKCHIP_RK3568=y
CONFIG_SPL_ROCKCHIP_BACK_TO_BROM=y
-CONFIG_SPL_ROCKCHIP_COMMON_BOARD=y
CONFIG_ROCKCHIP_RK8XX_DISABLE_BOOT_ON_POWERON=y
CONFIG_SPL_MMC=y
CONFIG_SPL_SERIAL=y
-CONFIG_SPL_STACK_R_ADDR=0x600000
CONFIG_TARGET_ANBERNIC_RGXX3_RK3566=y
-CONFIG_SPL_STACK=0x400000
CONFIG_DEBUG_UART_BASE=0xFE660000
CONFIG_DEBUG_UART_CLOCK=24000000
CONFIG_SYS_LOAD_ADDR=0xc00800
CONFIG_DEBUG_UART=y
CONFIG_FIT=y
CONFIG_FIT_VERBOSE=y
+CONFIG_SPL_FIT_SIGNATURE=y
CONFIG_SPL_LOAD_FIT=y
+CONFIG_LEGACY_IMAGE_FORMAT=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_OF_STDOUT_VIA_ALIAS=y
CONFIG_DEFAULT_FDT_FILE="rockchip/rk3566-anbernic-rgxx3.dtb"
@@ -32,15 +27,11 @@
# CONFIG_DISPLAY_CPUINFO is not set
CONFIG_DISPLAY_BOARDINFO_LATE=y
CONFIG_BOARD_RNG_SEED=y
-CONFIG_SPL_MAX_SIZE=0x20000
+CONFIG_SPL_MAX_SIZE=0x40000
CONFIG_SPL_PAD_TO=0x7f8000
-CONFIG_SPL_HAS_BSS_LINKER_SECTION=y
-CONFIG_SPL_BSS_START_ADDR=0x4000000
-CONFIG_SPL_BSS_MAX_SIZE=0x4000
CONFIG_SPL_BOARD_INIT=y
# CONFIG_SPL_RAW_IMAGE_SUPPORT is not set
-# CONFIG_SPL_SHARES_INIT_SP_ADDR is not set
-CONFIG_SPL_STACK_R=y
+CONFIG_SPL_POWER=y
CONFIG_SPL_ATF=y
CONFIG_CMD_PWM=y
CONFIG_CMD_GPT=y
@@ -50,8 +41,10 @@
# CONFIG_SPL_DOS_PARTITION is not set
CONFIG_SPL_OF_CONTROL=y
CONFIG_OF_LIVE=y
+CONFIG_OF_SPL_REMOVE_PROPS="clock-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents"
CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y
# CONFIG_NET is not set
+CONFIG_SPL_DM_SEQ_ALIAS=y
CONFIG_SPL_REGMAP=y
CONFIG_SPL_SYSCON=y
CONFIG_SPL_CLK=y
@@ -67,13 +60,13 @@
CONFIG_MMC_SDHCI_SDMA=y
CONFIG_MMC_SDHCI_ROCKCHIP=y
CONFIG_PHY_ROCKCHIP_INNO_DSIDPHY=y
+CONFIG_SPL_PINCTRL=y
CONFIG_DM_PMIC=y
CONFIG_DM_PMIC_FAN53555=y
CONFIG_PMIC_RK8XX=y
-CONFIG_REGULATOR_PWM=y
-CONFIG_DM_REGULATOR_GPIO=y
+CONFIG_SPL_DM_REGULATOR=y
+CONFIG_SPL_DM_REGULATOR_FIXED=y
CONFIG_REGULATOR_RK8XX=y
-CONFIG_DM_REGULATOR_SCMI=y
CONFIG_PWM_ROCKCHIP=y
CONFIG_SPL_RAM=y
# CONFIG_RAM_ROCKCHIP_DEBUG is not set
@@ -89,5 +82,6 @@
CONFIG_DISPLAY_ROCKCHIP_DW_MIPI=y
CONFIG_VIDEO_BRIDGE=y
CONFIG_REGEX=y
+# CONFIG_RSA is not set
CONFIG_ERRNO_STR=y
# CONFIG_EFI_LOADER is not set
diff --git a/configs/bananapi-cm4-cm4io_defconfig b/configs/bananapi-cm4-cm4io_defconfig
index 116147f..cb78dab 100644
--- a/configs/bananapi-cm4-cm4io_defconfig
+++ b/configs/bananapi-cm4-cm4io_defconfig
@@ -6,7 +6,7 @@
CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x20000000
CONFIG_ENV_SIZE=0x2000
CONFIG_DM_GPIO=y
-CONFIG_DEFAULT_DEVICE_TREE="meson-g12b-bananapi-cm4-cm4io"
+CONFIG_DEFAULT_DEVICE_TREE="amlogic/meson-g12b-bananapi-cm4-cm4io"
CONFIG_OF_LIBFDT_OVERLAY=y
CONFIG_DM_RESET=y
CONFIG_MESON_G12A=y
diff --git a/configs/bananapi-m2-pro_defconfig b/configs/bananapi-m2-pro_defconfig
index 755bccb..196bc40 100644
--- a/configs/bananapi-m2-pro_defconfig
+++ b/configs/bananapi-m2-pro_defconfig
@@ -6,7 +6,7 @@
CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x20000000
CONFIG_ENV_SIZE=0x2000
CONFIG_DM_GPIO=y
-CONFIG_DEFAULT_DEVICE_TREE="meson-sm1-bananapi-m2-pro"
+CONFIG_DEFAULT_DEVICE_TREE="amlogic/meson-sm1-bananapi-m2-pro"
CONFIG_OF_LIBFDT_OVERLAY=y
CONFIG_DM_RESET=y
CONFIG_MESON_G12A=y
diff --git a/configs/bananapi-m2s_defconfig b/configs/bananapi-m2s_defconfig
index af8dace..7b137d5 100644
--- a/configs/bananapi-m2s_defconfig
+++ b/configs/bananapi-m2s_defconfig
@@ -6,7 +6,7 @@
CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x20000000
CONFIG_ENV_SIZE=0x2000
CONFIG_DM_GPIO=y
-CONFIG_DEFAULT_DEVICE_TREE="meson-g12b-a311d-bananapi-m2s"
+CONFIG_DEFAULT_DEVICE_TREE="amlogic/meson-g12b-a311d-bananapi-m2s"
CONFIG_OF_LIBFDT_OVERLAY=y
CONFIG_DM_RESET=y
CONFIG_MESON_G12A=y
diff --git a/configs/bananapi-m5_defconfig b/configs/bananapi-m5_defconfig
index 6de5d5f..99ed7c9 100644
--- a/configs/bananapi-m5_defconfig
+++ b/configs/bananapi-m5_defconfig
@@ -6,7 +6,7 @@
CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x20000000
CONFIG_ENV_SIZE=0x2000
CONFIG_DM_GPIO=y
-CONFIG_DEFAULT_DEVICE_TREE="meson-sm1-bananapi-m5"
+CONFIG_DEFAULT_DEVICE_TREE="amlogic/meson-sm1-bananapi-m5"
CONFIG_OF_LIBFDT_OVERLAY=y
CONFIG_DM_RESET=y
CONFIG_MESON_G12A=y
diff --git a/configs/beelink-gsking-x_defconfig b/configs/beelink-gsking-x_defconfig
index 99e36e9..c1e60ed 100644
--- a/configs/beelink-gsking-x_defconfig
+++ b/configs/beelink-gsking-x_defconfig
@@ -7,7 +7,7 @@
CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x20000000
CONFIG_ENV_SIZE=0x2000
CONFIG_DM_GPIO=y
-CONFIG_DEFAULT_DEVICE_TREE="meson-g12b-gsking-x"
+CONFIG_DEFAULT_DEVICE_TREE="amlogic/meson-g12b-gsking-x"
CONFIG_OF_LIBFDT_OVERLAY=y
CONFIG_DM_RESET=y
CONFIG_MESON_G12A=y
diff --git a/configs/beelink-gt1-ultimate_defconfig b/configs/beelink-gt1-ultimate_defconfig
index 00fdad8..0e30e13 100644
--- a/configs/beelink-gt1-ultimate_defconfig
+++ b/configs/beelink-gt1-ultimate_defconfig
@@ -6,7 +6,7 @@
CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x20000000
CONFIG_ENV_SIZE=0x2000
CONFIG_DM_GPIO=y
-CONFIG_DEFAULT_DEVICE_TREE="meson-gxm-gt1-ultimate"
+CONFIG_DEFAULT_DEVICE_TREE="amlogic/meson-gxm-gt1-ultimate"
CONFIG_OF_LIBFDT_OVERLAY=y
CONFIG_DM_RESET=y
CONFIG_MESON_GXM=y
diff --git a/configs/beelink-gtking_defconfig b/configs/beelink-gtking_defconfig
index 5c21d8e..0b644f0 100644
--- a/configs/beelink-gtking_defconfig
+++ b/configs/beelink-gtking_defconfig
@@ -7,7 +7,7 @@
CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x20000000
CONFIG_ENV_SIZE=0x2000
CONFIG_DM_GPIO=y
-CONFIG_DEFAULT_DEVICE_TREE="meson-g12b-gtking"
+CONFIG_DEFAULT_DEVICE_TREE="amlogic/meson-g12b-gtking"
CONFIG_OF_LIBFDT_OVERLAY=y
CONFIG_DM_RESET=y
CONFIG_MESON_G12A=y
diff --git a/configs/beelink-gtkingpro_defconfig b/configs/beelink-gtkingpro_defconfig
index 37bb4cd..a694617 100644
--- a/configs/beelink-gtkingpro_defconfig
+++ b/configs/beelink-gtkingpro_defconfig
@@ -7,7 +7,7 @@
CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x20000000
CONFIG_ENV_SIZE=0x2000
CONFIG_DM_GPIO=y
-CONFIG_DEFAULT_DEVICE_TREE="meson-g12b-gtking-pro"
+CONFIG_DEFAULT_DEVICE_TREE="amlogic/meson-g12b-gtking-pro"
CONFIG_OF_LIBFDT_OVERLAY=y
CONFIG_DM_RESET=y
CONFIG_MESON_G12A=y
diff --git a/configs/bpi-r2-pro-rk3568_defconfig b/configs/bpi-r2-pro-rk3568_defconfig
index e6e0e6f..5cc9524 100644
--- a/configs/bpi-r2-pro-rk3568_defconfig
+++ b/configs/bpi-r2-pro-rk3568_defconfig
@@ -2,18 +2,10 @@
CONFIG_SKIP_LOWLEVEL_INIT=y
CONFIG_COUNTER_FREQUENCY=24000000
CONFIG_ARCH_ROCKCHIP=y
-CONFIG_TEXT_BASE=0x00a00000
-CONFIG_SPL_LIBCOMMON_SUPPORT=y
-CONFIG_SPL_LIBGENERIC_SUPPORT=y
CONFIG_NR_DRAM_BANKS=2
-CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y
-CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0xc00000
CONFIG_DEFAULT_DEVICE_TREE="rk3568-bpi-r2-pro"
CONFIG_ROCKCHIP_RK3568=y
-CONFIG_SPL_ROCKCHIP_COMMON_BOARD=y
CONFIG_SPL_SERIAL=y
-CONFIG_SPL_STACK_R_ADDR=0x600000
-CONFIG_SPL_STACK=0x400000
CONFIG_DEBUG_UART_BASE=0xFE660000
CONFIG_DEBUG_UART_CLOCK=24000000
CONFIG_SYS_LOAD_ADDR=0xc00800
@@ -30,12 +22,7 @@
CONFIG_DISPLAY_BOARDINFO_LATE=y
CONFIG_SPL_MAX_SIZE=0x40000
CONFIG_SPL_PAD_TO=0x7f8000
-CONFIG_SPL_HAS_BSS_LINKER_SECTION=y
-CONFIG_SPL_BSS_START_ADDR=0x4000000
-CONFIG_SPL_BSS_MAX_SIZE=0x4000
# CONFIG_SPL_RAW_IMAGE_SUPPORT is not set
-# CONFIG_SPL_SHARES_INIT_SP_ADDR is not set
-CONFIG_SPL_STACK_R=y
CONFIG_SPL_ATF=y
CONFIG_SYS_PROMPT="BPI-R2PRO> "
CONFIG_CMD_GPIO=y
diff --git a/configs/chromebook_bob_defconfig b/configs/chromebook_bob_defconfig
index b5a5ae7..d032194 100644
--- a/configs/chromebook_bob_defconfig
+++ b/configs/chromebook_bob_defconfig
@@ -27,7 +27,6 @@
# CONFIG_DISPLAY_CPUINFO is not set
CONFIG_DISPLAY_BOARDINFO_LATE=y
CONFIG_BOARD_EARLY_INIT_R=y
-CONFIG_MISC_INIT_R=y
CONFIG_BLOBLIST=y
CONFIG_BLOBLIST_ADDR=0x100000
CONFIG_BLOBLIST_SIZE=0x1000
@@ -67,8 +66,7 @@
CONFIG_SYS_I2C_ROCKCHIP=y
CONFIG_I2C_MUX=y
CONFIG_CROS_EC_KEYB=y
-CONFIG_MISC=y
-CONFIG_ROCKCHIP_EFUSE=y
+CONFIG_ROCKCHIP_IODOMAIN=y
CONFIG_CROS_EC=y
CONFIG_CROS_EC_SPI=y
CONFIG_PWRSEQ=y
diff --git a/configs/chromebook_kevin_defconfig b/configs/chromebook_kevin_defconfig
index 20913d2..120c11c 100644
--- a/configs/chromebook_kevin_defconfig
+++ b/configs/chromebook_kevin_defconfig
@@ -28,7 +28,6 @@
# CONFIG_DISPLAY_CPUINFO is not set
CONFIG_DISPLAY_BOARDINFO_LATE=y
CONFIG_BOARD_EARLY_INIT_R=y
-CONFIG_MISC_INIT_R=y
CONFIG_BLOBLIST=y
CONFIG_BLOBLIST_ADDR=0x100000
CONFIG_BLOBLIST_SIZE=0x1000
@@ -68,8 +67,7 @@
CONFIG_SYS_I2C_ROCKCHIP=y
CONFIG_I2C_MUX=y
CONFIG_CROS_EC_KEYB=y
-CONFIG_MISC=y
-CONFIG_ROCKCHIP_EFUSE=y
+CONFIG_ROCKCHIP_IODOMAIN=y
CONFIG_CROS_EC=y
CONFIG_CROS_EC_SPI=y
CONFIG_PWRSEQ=y
diff --git a/configs/colibri_imx7_defconfig b/configs/colibri_imx7_defconfig
index 58eb431..16f923b 100644
--- a/configs/colibri_imx7_defconfig
+++ b/configs/colibri_imx7_defconfig
@@ -72,6 +72,7 @@
CONFIG_BOUNCE_BUFFER=y
CONFIG_BOOTCOUNT_LIMIT=y
CONFIG_BOOTCOUNT_ENV=y
+CONFIG_FSL_CAAM_JR_NTZ_ACCESS=y
CONFIG_DFU_NAND=y
CONFIG_USB_FUNCTION_FASTBOOT=y
CONFIG_FASTBOOT_BUF_ADDR=0x81100000
@@ -98,10 +99,12 @@
CONFIG_PMIC_RN5T567=y
CONFIG_MXC_UART=y
CONFIG_IMX_THERMAL=y
+CONFIG_IMX_WATCHDOG=y
CONFIG_USB=y
CONFIG_USB_EHCI_HCD=y
CONFIG_USB_GADGET=y
CONFIG_USB_GADGET_MANUFACTURER="Toradex"
CONFIG_USB_GADGET_VENDOR_NUM=0x1b67
CONFIG_USB_GADGET_PRODUCT_NUM=0x4000
+CONFIG_WDT=y
CONFIG_CI_UDC=y
diff --git a/configs/colibri_imx7_emmc_defconfig b/configs/colibri_imx7_emmc_defconfig
index 3382371..7c6a725 100644
--- a/configs/colibri_imx7_emmc_defconfig
+++ b/configs/colibri_imx7_emmc_defconfig
@@ -8,7 +8,6 @@
CONFIG_TARGET_COLIBRI_IMX7=y
CONFIG_TARGET_COLIBRI_IMX7_EMMC=y
CONFIG_OF_LIBFDT_OVERLAY=y
-CONFIG_ARMV7_BOOT_SEC_DEFAULT=y
CONFIG_IMX_RDC=y
CONFIG_IMX_BOOTAUX=y
CONFIG_IMX_HAB=y
@@ -62,6 +61,7 @@
CONFIG_SERVERIP="192.168.10.1"
CONFIG_BOOTCOUNT_LIMIT=y
CONFIG_BOOTCOUNT_ENV=y
+CONFIG_FSL_CAAM_JR_NTZ_ACCESS=y
CONFIG_USB_FUNCTION_FASTBOOT=y
CONFIG_FASTBOOT_BUF_ADDR=0x81100000
CONFIG_FASTBOOT_FLASH=y
@@ -85,10 +85,12 @@
CONFIG_PMIC_RN5T567=y
CONFIG_MXC_UART=y
CONFIG_IMX_THERMAL=y
+CONFIG_IMX_WATCHDOG=y
CONFIG_USB=y
CONFIG_USB_EHCI_HCD=y
CONFIG_USB_GADGET=y
CONFIG_USB_GADGET_MANUFACTURER="Toradex"
CONFIG_USB_GADGET_VENDOR_NUM=0x1b67
CONFIG_USB_GADGET_PRODUCT_NUM=0x4000
+CONFIG_WDT=y
CONFIG_CI_UDC=y
diff --git a/configs/colibri_vf_defconfig b/configs/colibri_vf_defconfig
index a5e6bcb..0249dc3 100644
--- a/configs/colibri_vf_defconfig
+++ b/configs/colibri_vf_defconfig
@@ -17,6 +17,7 @@
CONFIG_ENV_VARS_UBOOT_CONFIG=y
CONFIG_HAS_BOARD_SIZE_LIMIT=y
CONFIG_BOARD_SIZE_LIMIT=520192
+# CONFIG_BOOTM is not set
CONFIG_BOOTDELAY=1
CONFIG_FDT_FIXUP_PARTITIONS=y
CONFIG_USE_BOOTCOMMAND=y
@@ -33,7 +34,6 @@
# CONFIG_SYS_LONGHELP is not set
CONFIG_SYS_PROMPT="Colibri VFxx # "
# CONFIG_CMD_BOOTD is not set
-# CONFIG_CMD_BOOTM is not set
CONFIG_CMD_BOOTZ=y
# CONFIG_CMD_ELF is not set
# CONFIG_CMD_IMI is not set
diff --git a/configs/coolpi-4b-rk3588s_defconfig b/configs/coolpi-4b-rk3588s_defconfig
new file mode 100644
index 0000000..a0fe370
--- /dev/null
+++ b/configs/coolpi-4b-rk3588s_defconfig
@@ -0,0 +1,100 @@
+CONFIG_ARM=y
+CONFIG_SKIP_LOWLEVEL_INIT=y
+CONFIG_COUNTER_FREQUENCY=24000000
+CONFIG_ARCH_ROCKCHIP=y
+CONFIG_NR_DRAM_BANKS=2
+CONFIG_SF_DEFAULT_SPEED=24000000
+CONFIG_SF_DEFAULT_MODE=0x2000
+CONFIG_DEFAULT_DEVICE_TREE="rk3588s-coolpi-4b"
+CONFIG_ROCKCHIP_RK3588=y
+CONFIG_ROCKCHIP_SPI_IMAGE=y
+CONFIG_SPL_SERIAL=y
+CONFIG_TARGET_EVB_RK3588=y
+CONFIG_DEBUG_UART_BASE=0xFEB50000
+CONFIG_DEBUG_UART_CLOCK=24000000
+CONFIG_SPL_SPI_FLASH_SUPPORT=y
+CONFIG_SPL_SPI=y
+CONFIG_SYS_LOAD_ADDR=0xc00800
+CONFIG_PCI=y
+CONFIG_DEBUG_UART=y
+CONFIG_AHCI=y
+CONFIG_FIT=y
+CONFIG_FIT_VERBOSE=y
+CONFIG_SPL_FIT_SIGNATURE=y
+CONFIG_SPL_LOAD_FIT=y
+CONFIG_LEGACY_IMAGE_FORMAT=y
+CONFIG_OF_BOARD_SETUP=y
+CONFIG_DEFAULT_FDT_FILE="rockchip/rk3588s-coolpi-4b.dtb"
+# CONFIG_DISPLAY_CPUINFO is not set
+CONFIG_DISPLAY_BOARDINFO_LATE=y
+CONFIG_SPL_MAX_SIZE=0x40000
+CONFIG_SPL_PAD_TO=0x7f8000
+# CONFIG_SPL_RAW_IMAGE_SUPPORT is not set
+CONFIG_SPL_SPI_LOAD=y
+CONFIG_SYS_SPI_U_BOOT_OFFS=0x60000
+CONFIG_SPL_ATF=y
+CONFIG_CMD_GPIO=y
+CONFIG_CMD_GPT=y
+CONFIG_CMD_I2C=y
+CONFIG_CMD_MMC=y
+CONFIG_CMD_PCI=y
+CONFIG_CMD_USB=y
+# CONFIG_CMD_SETEXPR is not set
+CONFIG_CMD_REGULATOR=y
+# CONFIG_SPL_DOS_PARTITION is not set
+CONFIG_SPL_OF_CONTROL=y
+CONFIG_OF_LIVE=y
+CONFIG_OF_SPL_REMOVE_PROPS="clock-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents"
+CONFIG_SPL_DM_SEQ_ALIAS=y
+CONFIG_SPL_REGMAP=y
+CONFIG_SPL_SYSCON=y
+CONFIG_AHCI_PCI=y
+CONFIG_DWC_AHCI=y
+CONFIG_SPL_CLK=y
+CONFIG_ROCKCHIP_GPIO=y
+CONFIG_SYS_I2C_ROCKCHIP=y
+CONFIG_MISC=y
+CONFIG_SUPPORT_EMMC_RPMB=y
+CONFIG_MMC_IO_VOLTAGE=y
+CONFIG_SPL_MMC_IO_VOLTAGE=y
+CONFIG_MMC_UHS_SUPPORT=y
+CONFIG_SPL_MMC_UHS_SUPPORT=y
+CONFIG_MMC_HS400_ES_SUPPORT=y
+CONFIG_SPL_MMC_HS400_ES_SUPPORT=y
+CONFIG_MMC_HS400_SUPPORT=y
+CONFIG_SPL_MMC_HS400_SUPPORT=y
+CONFIG_MMC_DW=y
+CONFIG_MMC_DW_ROCKCHIP=y
+CONFIG_MMC_SDHCI=y
+CONFIG_MMC_SDHCI_SDMA=y
+CONFIG_MMC_SDHCI_ROCKCHIP=y
+CONFIG_SF_DEFAULT_BUS=5
+CONFIG_SPI_FLASH_SFDP_SUPPORT=y
+CONFIG_SPI_FLASH_XMC=y
+CONFIG_SPI_FLASH_XTX=y
+CONFIG_PHY_MOTORCOMM=y
+CONFIG_DWC_ETH_QOS=y
+CONFIG_DWC_ETH_QOS_ROCKCHIP=y
+CONFIG_NVME_PCI=y
+CONFIG_PCIE_DW_ROCKCHIP=y
+CONFIG_PHY_ROCKCHIP_INNO_USB2=y
+CONFIG_PHY_ROCKCHIP_NANENG_COMBOPHY=y
+CONFIG_PHY_ROCKCHIP_USBDP=y
+CONFIG_SPL_PINCTRL=y
+CONFIG_PWM_ROCKCHIP=y
+CONFIG_SPL_RAM=y
+CONFIG_SCSI=y
+CONFIG_BAUDRATE=1500000
+CONFIG_DEBUG_UART_SHIFT=2
+CONFIG_SYS_NS16550_MEM32=y
+CONFIG_ROCKCHIP_SFC=y
+CONFIG_SYSRESET=y
+CONFIG_USB=y
+CONFIG_USB_XHCI_HCD=y
+CONFIG_USB_EHCI_HCD=y
+CONFIG_USB_EHCI_GENERIC=y
+CONFIG_USB_OHCI_HCD=y
+CONFIG_USB_OHCI_GENERIC=y
+CONFIG_USB_DWC3=y
+CONFIG_USB_DWC3_GENERIC=y
+CONFIG_ERRNO_STR=y
diff --git a/configs/coolpi-cm5-evb-rk3588_defconfig b/configs/coolpi-cm5-evb-rk3588_defconfig
new file mode 100644
index 0000000..fc17660
--- /dev/null
+++ b/configs/coolpi-cm5-evb-rk3588_defconfig
@@ -0,0 +1,100 @@
+CONFIG_ARM=y
+CONFIG_SKIP_LOWLEVEL_INIT=y
+CONFIG_COUNTER_FREQUENCY=24000000
+CONFIG_ARCH_ROCKCHIP=y
+CONFIG_NR_DRAM_BANKS=2
+CONFIG_SF_DEFAULT_SPEED=24000000
+CONFIG_SF_DEFAULT_MODE=0x2000
+CONFIG_DEFAULT_DEVICE_TREE="rk3588-coolpi-cm5-evb"
+CONFIG_ROCKCHIP_RK3588=y
+CONFIG_ROCKCHIP_SPI_IMAGE=y
+CONFIG_SPL_SERIAL=y
+CONFIG_TARGET_EVB_RK3588=y
+CONFIG_DEBUG_UART_BASE=0xFEB50000
+CONFIG_DEBUG_UART_CLOCK=24000000
+CONFIG_SPL_SPI_FLASH_SUPPORT=y
+CONFIG_SPL_SPI=y
+CONFIG_SYS_LOAD_ADDR=0xc00800
+CONFIG_PCI=y
+CONFIG_DEBUG_UART=y
+CONFIG_AHCI=y
+CONFIG_FIT=y
+CONFIG_FIT_VERBOSE=y
+CONFIG_SPL_FIT_SIGNATURE=y
+CONFIG_SPL_LOAD_FIT=y
+CONFIG_LEGACY_IMAGE_FORMAT=y
+CONFIG_OF_BOARD_SETUP=y
+CONFIG_DEFAULT_FDT_FILE="rockchip/rk3588-coolpi-cm5-evb.dtb"
+# CONFIG_DISPLAY_CPUINFO is not set
+CONFIG_DISPLAY_BOARDINFO_LATE=y
+CONFIG_SPL_MAX_SIZE=0x40000
+CONFIG_SPL_PAD_TO=0x7f8000
+# CONFIG_SPL_RAW_IMAGE_SUPPORT is not set
+CONFIG_SPL_SPI_LOAD=y
+CONFIG_SYS_SPI_U_BOOT_OFFS=0x60000
+CONFIG_SPL_ATF=y
+CONFIG_CMD_GPIO=y
+CONFIG_CMD_GPT=y
+CONFIG_CMD_I2C=y
+CONFIG_CMD_MMC=y
+CONFIG_CMD_PCI=y
+CONFIG_CMD_USB=y
+# CONFIG_CMD_SETEXPR is not set
+CONFIG_CMD_REGULATOR=y
+# CONFIG_SPL_DOS_PARTITION is not set
+CONFIG_SPL_OF_CONTROL=y
+CONFIG_OF_LIVE=y
+CONFIG_OF_SPL_REMOVE_PROPS="clock-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents"
+CONFIG_SPL_DM_SEQ_ALIAS=y
+CONFIG_SPL_REGMAP=y
+CONFIG_SPL_SYSCON=y
+CONFIG_AHCI_PCI=y
+CONFIG_DWC_AHCI=y
+CONFIG_SPL_CLK=y
+CONFIG_ROCKCHIP_GPIO=y
+CONFIG_SYS_I2C_ROCKCHIP=y
+CONFIG_MISC=y
+CONFIG_SUPPORT_EMMC_RPMB=y
+CONFIG_MMC_IO_VOLTAGE=y
+CONFIG_SPL_MMC_IO_VOLTAGE=y
+CONFIG_MMC_UHS_SUPPORT=y
+CONFIG_SPL_MMC_UHS_SUPPORT=y
+CONFIG_MMC_HS400_ES_SUPPORT=y
+CONFIG_SPL_MMC_HS400_ES_SUPPORT=y
+CONFIG_MMC_HS400_SUPPORT=y
+CONFIG_SPL_MMC_HS400_SUPPORT=y
+CONFIG_MMC_DW=y
+CONFIG_MMC_DW_ROCKCHIP=y
+CONFIG_MMC_SDHCI=y
+CONFIG_MMC_SDHCI_SDMA=y
+CONFIG_MMC_SDHCI_ROCKCHIP=y
+CONFIG_SF_DEFAULT_BUS=5
+CONFIG_SPI_FLASH_SFDP_SUPPORT=y
+CONFIG_SPI_FLASH_XMC=y
+CONFIG_SPI_FLASH_XTX=y
+CONFIG_PHY_MOTORCOMM=y
+CONFIG_DWC_ETH_QOS=y
+CONFIG_DWC_ETH_QOS_ROCKCHIP=y
+CONFIG_NVME_PCI=y
+CONFIG_PCIE_DW_ROCKCHIP=y
+CONFIG_PHY_ROCKCHIP_INNO_USB2=y
+CONFIG_PHY_ROCKCHIP_NANENG_COMBOPHY=y
+CONFIG_PHY_ROCKCHIP_USBDP=y
+CONFIG_SPL_PINCTRL=y
+CONFIG_PWM_ROCKCHIP=y
+CONFIG_SPL_RAM=y
+CONFIG_SCSI=y
+CONFIG_BAUDRATE=1500000
+CONFIG_DEBUG_UART_SHIFT=2
+CONFIG_SYS_NS16550_MEM32=y
+CONFIG_ROCKCHIP_SFC=y
+CONFIG_SYSRESET=y
+CONFIG_USB=y
+CONFIG_USB_XHCI_HCD=y
+CONFIG_USB_EHCI_HCD=y
+CONFIG_USB_EHCI_GENERIC=y
+CONFIG_USB_OHCI_HCD=y
+CONFIG_USB_OHCI_GENERIC=y
+CONFIG_USB_DWC3=y
+CONFIG_USB_DWC3_GENERIC=y
+CONFIG_ERRNO_STR=y
diff --git a/configs/coreboot64_defconfig b/configs/coreboot64_defconfig
index dab5eaf..da42ad0 100644
--- a/configs/coreboot64_defconfig
+++ b/configs/coreboot64_defconfig
@@ -16,6 +16,7 @@
CONFIG_SHOW_BOOT_PROGRESS=y
CONFIG_USE_BOOTARGS=y
CONFIG_BOOTARGS="root=/dev/sdb3 init=/sbin/init rootwait ro"
+CONFIG_BOOTCOMMAND="bootflow scan -l; if bootflow menu; then cls; bootflow boot; fi"
CONFIG_SYS_PBSIZE=532
CONFIG_PRE_CONSOLE_BUFFER=y
CONFIG_SYS_CONSOLE_INFO_QUIET=y
@@ -59,6 +60,7 @@
CONFIG_SOUND=y
CONFIG_SOUND_I8254=y
CONFIG_VIDEO_COPY=y
+CONFIG_CONSOLE_TRUETYPE=y
CONFIG_CONSOLE_SCROLL_LINES=5
CONFIG_SPL_ACPI=y
CONFIG_CMD_DHRYSTONE=y
diff --git a/configs/coreboot_defconfig b/configs/coreboot_defconfig
index c846dfc..0b103ef 100644
--- a/configs/coreboot_defconfig
+++ b/configs/coreboot_defconfig
@@ -14,6 +14,7 @@
CONFIG_SHOW_BOOT_PROGRESS=y
CONFIG_USE_BOOTARGS=y
CONFIG_BOOTARGS="root=/dev/sdb3 init=/sbin/init rootwait ro"
+CONFIG_BOOTCOMMAND="bootflow scan -l; if bootflow menu; then cls; bootflow boot; fi"
CONFIG_PRE_CONSOLE_BUFFER=y
CONFIG_SYS_CONSOLE_INFO_QUIET=y
CONFIG_LOG=y
@@ -53,6 +54,7 @@
CONFIG_SOUND=y
CONFIG_SOUND_I8254=y
CONFIG_VIDEO_COPY=y
+CONFIG_CONSOLE_TRUETYPE=y
CONFIG_CONSOLE_SCROLL_LINES=5
CONFIG_CMD_DHRYSTONE=y
# CONFIG_GZIP is not set
diff --git a/configs/d2net_v2_defconfig b/configs/d2net_v2_defconfig
index bb1bcb0..69658a2 100644
--- a/configs/d2net_v2_defconfig
+++ b/configs/d2net_v2_defconfig
@@ -11,7 +11,7 @@
CONFIG_ENV_SIZE=0x1000
CONFIG_ENV_OFFSET=0x70000
CONFIG_ENV_SECT_SIZE=0x10000
-CONFIG_DEFAULT_DEVICE_TREE="kirkwood-d2net"
+CONFIG_DEFAULT_DEVICE_TREE="marvell/kirkwood-d2net"
CONFIG_IDENT_STRING=" D2 v2"
CONFIG_SYS_LOAD_ADDR=0x800000
CONFIG_ENV_ADDR=0x70000
diff --git a/configs/dns325_defconfig b/configs/dns325_defconfig
index edfe92c..b85f7ca 100644
--- a/configs/dns325_defconfig
+++ b/configs/dns325_defconfig
@@ -10,7 +10,7 @@
CONFIG_TARGET_DNS325=y
CONFIG_ENV_SIZE=0x20000
CONFIG_ENV_OFFSET=0xE0000
-CONFIG_DEFAULT_DEVICE_TREE="kirkwood-dns325"
+CONFIG_DEFAULT_DEVICE_TREE="marvell/kirkwood-dns325"
CONFIG_IDENT_STRING="\nD-Link DNS-325"
CONFIG_SYS_LOAD_ADDR=0x800000
# CONFIG_SYS_MALLOC_F is not set
diff --git a/configs/dockstar_defconfig b/configs/dockstar_defconfig
index 719fa39..7b5f194 100644
--- a/configs/dockstar_defconfig
+++ b/configs/dockstar_defconfig
@@ -13,7 +13,7 @@
CONFIG_TARGET_DOCKSTAR=y
CONFIG_ENV_SIZE=0x20000
CONFIG_ENV_OFFSET=0x80000
-CONFIG_DEFAULT_DEVICE_TREE="kirkwood-dockstar"
+CONFIG_DEFAULT_DEVICE_TREE="marvell/kirkwood-dockstar"
CONFIG_IDENT_STRING="\nSeagate FreeAgent DockStar"
CONFIG_SYS_LOAD_ADDR=0x800000
CONFIG_BOOTDELAY=3
diff --git a/configs/dreamplug_defconfig b/configs/dreamplug_defconfig
index 02a2635..8518eab 100644
--- a/configs/dreamplug_defconfig
+++ b/configs/dreamplug_defconfig
@@ -13,7 +13,7 @@
CONFIG_ENV_SIZE=0x1000
CONFIG_ENV_OFFSET=0x100000
CONFIG_ENV_SECT_SIZE=0x10000
-CONFIG_DEFAULT_DEVICE_TREE="kirkwood-dreamplug"
+CONFIG_DEFAULT_DEVICE_TREE="marvell/kirkwood-dreamplug"
CONFIG_IDENT_STRING="\nMarvell-DreamPlug"
CONFIG_SYS_LOAD_ADDR=0x800000
CONFIG_ENV_ADDR=0x100000
diff --git a/configs/ds109_defconfig b/configs/ds109_defconfig
index 304c098..ef805ec 100644
--- a/configs/ds109_defconfig
+++ b/configs/ds109_defconfig
@@ -14,7 +14,7 @@
CONFIG_ENV_SIZE=0x10000
CONFIG_ENV_OFFSET=0x3D0000
CONFIG_ENV_SECT_SIZE=0x10000
-CONFIG_DEFAULT_DEVICE_TREE="kirkwood-ds109"
+CONFIG_DEFAULT_DEVICE_TREE="marvell/kirkwood-ds109"
CONFIG_SYS_LOAD_ADDR=0x800000
CONFIG_ENV_ADDR=0x3D0000
# CONFIG_SYS_MALLOC_F is not set
diff --git a/configs/eaidk-610-rk3399_defconfig b/configs/eaidk-610-rk3399_defconfig
index 22ad98b..4d8b495 100644
--- a/configs/eaidk-610-rk3399_defconfig
+++ b/configs/eaidk-610-rk3399_defconfig
@@ -2,15 +2,11 @@
CONFIG_SKIP_LOWLEVEL_INIT=y
CONFIG_COUNTER_FREQUENCY=24000000
CONFIG_ARCH_ROCKCHIP=y
-CONFIG_TEXT_BASE=0x00200000
CONFIG_NR_DRAM_BANKS=1
-CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y
-CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x300000
CONFIG_ENV_OFFSET=0x3F8000
CONFIG_DEFAULT_DEVICE_TREE="rk3399-eaidk-610"
CONFIG_ROCKCHIP_RK3399=y
CONFIG_TARGET_EVB_RK3399=y
-CONFIG_SPL_STACK=0x400000
CONFIG_DEBUG_UART_BASE=0xFF1A0000
CONFIG_DEBUG_UART_CLOCK=24000000
CONFIG_SYS_LOAD_ADDR=0x800800
@@ -19,13 +15,7 @@
CONFIG_DISPLAY_BOARDINFO_LATE=y
CONFIG_SPL_MAX_SIZE=0x2e000
CONFIG_SPL_PAD_TO=0x7f8000
-CONFIG_SPL_HAS_BSS_LINKER_SECTION=y
-CONFIG_SPL_BSS_START_ADDR=0x400000
-CONFIG_SPL_BSS_MAX_SIZE=0x2000
# CONFIG_SPL_RAW_IMAGE_SUPPORT is not set
-# CONFIG_SPL_SHARES_INIT_SP_ADDR is not set
-CONFIG_SPL_STACK_R=y
-CONFIG_SPL_STACK_R_MALLOC_SIMPLE_LEN=0x10000
CONFIG_SPL_ATF_NO_PLATFORM_PARAM=y
CONFIG_TPL=y
CONFIG_CMD_BOOTZ=y
@@ -40,7 +30,6 @@
CONFIG_SYS_RELOC_GD_ENV_ADDR=y
CONFIG_ROCKCHIP_GPIO=y
CONFIG_SYS_I2C_ROCKCHIP=y
-CONFIG_MISC=y
CONFIG_MMC_DW=y
CONFIG_MMC_DW_ROCKCHIP=y
CONFIG_MMC_SDHCI=y
diff --git a/configs/evb-rk3308_defconfig b/configs/evb-rk3308_defconfig
index 2729060..d57b2f6 100644
--- a/configs/evb-rk3308_defconfig
+++ b/configs/evb-rk3308_defconfig
@@ -2,19 +2,11 @@
CONFIG_SKIP_LOWLEVEL_INIT=y
CONFIG_COUNTER_FREQUENCY=24000000
CONFIG_ARCH_ROCKCHIP=y
-CONFIG_TEXT_BASE=0x00600000
-CONFIG_SYS_MALLOC_F_LEN=0x2000
-CONFIG_SPL_LIBCOMMON_SUPPORT=y
-CONFIG_SPL_LIBGENERIC_SUPPORT=y
-CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y
-CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x800000
CONFIG_DEFAULT_DEVICE_TREE="rk3308-evb"
CONFIG_DM_RESET=y
CONFIG_ROCKCHIP_RK3308=y
CONFIG_SPL_DRIVERS_MISC=y
CONFIG_TARGET_EVB_RK3308=y
-CONFIG_SPL_STACK_R_ADDR=0xc00000
-CONFIG_SPL_STACK=0x400000
CONFIG_DEBUG_UART_BASE=0xFF0C0000
CONFIG_DEBUG_UART_CLOCK=24000000
CONFIG_SYS_LOAD_ADDR=0xc00800
@@ -28,11 +20,6 @@
# CONFIG_DISPLAY_CPUINFO is not set
CONFIG_SPL_MAX_SIZE=0x20000
CONFIG_SPL_PAD_TO=0x7f8000
-CONFIG_SPL_HAS_BSS_LINKER_SECTION=y
-CONFIG_SPL_BSS_START_ADDR=0x400000
-CONFIG_SPL_BSS_MAX_SIZE=0x2000
-# CONFIG_SPL_SHARES_INIT_SP_ADDR is not set
-CONFIG_SPL_STACK_R=y
# CONFIG_CMD_BDI is not set
# CONFIG_CMD_CONSOLE is not set
# CONFIG_CMD_ELF is not set
diff --git a/configs/evb-rk3328_defconfig b/configs/evb-rk3328_defconfig
index b9c541a..75a0e0f 100644
--- a/configs/evb-rk3328_defconfig
+++ b/configs/evb-rk3328_defconfig
@@ -2,22 +2,12 @@
CONFIG_SKIP_LOWLEVEL_INIT=y
CONFIG_COUNTER_FREQUENCY=24000000
CONFIG_ARCH_ROCKCHIP=y
-CONFIG_TEXT_BASE=0x00200000
CONFIG_NR_DRAM_BANKS=1
-CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y
-CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x300000
CONFIG_SF_DEFAULT_SPEED=20000000
CONFIG_ENV_OFFSET=0x3F8000
CONFIG_DEFAULT_DEVICE_TREE="rk3328-evb"
+CONFIG_DM_RESET=y
CONFIG_ROCKCHIP_RK3328=y
-CONFIG_TPL_ROCKCHIP_COMMON_BOARD=y
-CONFIG_TPL_LIBCOMMON_SUPPORT=y
-CONFIG_TPL_LIBGENERIC_SUPPORT=y
-CONFIG_SPL_DRIVERS_MISC=y
-CONFIG_SPL_STACK_R_ADDR=0x4000000
-CONFIG_SPL_STACK=0x400000
-CONFIG_TPL_SYS_MALLOC_F_LEN=0x800
-CONFIG_SPL_SYS_MALLOC_F_LEN=0x4000
CONFIG_DEBUG_UART_BASE=0xFF130000
CONFIG_DEBUG_UART_CLOCK=24000000
CONFIG_SYS_LOAD_ADDR=0x800800
@@ -25,38 +15,36 @@
# CONFIG_ANDROID_BOOT_IMAGE is not set
CONFIG_FIT=y
CONFIG_FIT_VERBOSE=y
+CONFIG_SPL_FIT_SIGNATURE=y
CONFIG_SPL_LOAD_FIT=y
+CONFIG_LEGACY_IMAGE_FORMAT=y
CONFIG_DEFAULT_FDT_FILE="rockchip/rk3328-evb.dtb"
# CONFIG_DISPLAY_CPUINFO is not set
CONFIG_DISPLAY_BOARDINFO_LATE=y
CONFIG_SPL_MAX_SIZE=0x40000
CONFIG_SPL_PAD_TO=0x7f8000
-CONFIG_SPL_HAS_BSS_LINKER_SECTION=y
-CONFIG_SPL_BSS_START_ADDR=0x2000000
-CONFIG_SPL_BSS_MAX_SIZE=0x2000
# CONFIG_SPL_RAW_IMAGE_SUPPORT is not set
-# CONFIG_SPL_SHARES_INIT_SP_ADDR is not set
-CONFIG_SPL_STACK_R=y
-CONFIG_SPL_STACK_R_MALLOC_SIMPLE_LEN=0x10000
CONFIG_SPL_ATF=y
CONFIG_SPL_ATF_NO_PLATFORM_PARAM=y
-CONFIG_TPL_SYS_MALLOC_SIMPLE=y
-CONFIG_TPL_DRIVERS_MISC=y
CONFIG_CMD_BOOTZ=y
+CONFIG_CMD_GPIO=y
CONFIG_CMD_GPT=y
CONFIG_CMD_MMC=y
CONFIG_CMD_USB=y
+CONFIG_CMD_ROCKUSB=y
+CONFIG_CMD_USB_MASS_STORAGE=y
# CONFIG_CMD_SETEXPR is not set
CONFIG_CMD_TIME=y
+CONFIG_CMD_REGULATOR=y
CONFIG_SPL_OF_CONTROL=y
CONFIG_TPL_OF_CONTROL=y
-CONFIG_OF_SPL_REMOVE_PROPS="pinctrl-0 pinctrl-names clock-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents"
+CONFIG_OF_SPL_REMOVE_PROPS="clock-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents"
CONFIG_TPL_OF_PLATDATA=y
CONFIG_ENV_IS_IN_MMC=y
CONFIG_SYS_RELOC_GD_ENV_ADDR=y
CONFIG_SYS_MMC_ENV_DEV=1
-CONFIG_NET_RANDOM_ETHADDR=y
CONFIG_TPL_DM=y
+CONFIG_SPL_DM_SEQ_ALIAS=y
CONFIG_REGMAP=y
CONFIG_SPL_REGMAP=y
CONFIG_TPL_REGMAP=y
@@ -69,9 +57,12 @@
CONFIG_FASTBOOT_CMD_OEM_FORMAT=y
CONFIG_ROCKCHIP_GPIO=y
CONFIG_SYS_I2C_ROCKCHIP=y
-CONFIG_MISC=y
CONFIG_MMC_DW=y
CONFIG_MMC_DW_ROCKCHIP=y
+CONFIG_PHY_MOTORCOMM=y
+CONFIG_PHY_REALTEK=y
+CONFIG_DM_ETH_PHY=y
+CONFIG_PHY_GIGE=y
CONFIG_ETH_DESIGNWARE=y
CONFIG_GMAC_ROCKCHIP=y
CONFIG_PHY_ROCKCHIP_INNO_USB2=y
@@ -79,31 +70,33 @@
CONFIG_SPL_PINCTRL=y
CONFIG_DM_PMIC=y
CONFIG_PMIC_RK8XX=y
-CONFIG_REGULATOR_PWM=y
CONFIG_DM_REGULATOR_FIXED=y
CONFIG_REGULATOR_RK8XX=y
CONFIG_PWM_ROCKCHIP=y
CONFIG_RAM=y
CONFIG_SPL_RAM=y
CONFIG_TPL_RAM=y
+CONFIG_DM_RNG=y
+CONFIG_RNG_ROCKCHIP=y
CONFIG_BAUDRATE=1500000
CONFIG_DEBUG_UART_SHIFT=2
-CONFIG_DEBUG_UART_ANNOUNCE=y
CONFIG_SYS_NS16550_MEM32=y
+CONFIG_SYSINFO=y
CONFIG_SYSRESET=y
# CONFIG_TPL_SYSRESET is not set
CONFIG_USB=y
+CONFIG_DM_USB_GADGET=y
CONFIG_USB_XHCI_HCD=y
+CONFIG_USB_XHCI_DWC3=y
CONFIG_USB_EHCI_HCD=y
CONFIG_USB_EHCI_GENERIC=y
CONFIG_USB_OHCI_HCD=y
CONFIG_USB_OHCI_GENERIC=y
-CONFIG_USB_DWC2=y
CONFIG_USB_DWC3=y
# CONFIG_USB_DWC3_GADGET is not set
-CONFIG_USB_DWC3_GENERIC=y
CONFIG_USB_GADGET=y
CONFIG_USB_GADGET_DWC2_OTG=y
+CONFIG_USB_FUNCTION_ROCKUSB=y
CONFIG_SPL_TINY_MEMSET=y
CONFIG_TPL_TINY_MEMSET=y
CONFIG_ERRNO_STR=y
diff --git a/configs/evb-rk3399_defconfig b/configs/evb-rk3399_defconfig
index d614052..d81c7f96 100644
--- a/configs/evb-rk3399_defconfig
+++ b/configs/evb-rk3399_defconfig
@@ -2,17 +2,13 @@
CONFIG_SKIP_LOWLEVEL_INIT=y
CONFIG_COUNTER_FREQUENCY=24000000
CONFIG_ARCH_ROCKCHIP=y
-CONFIG_TEXT_BASE=0x00200000
CONFIG_NR_DRAM_BANKS=1
-CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y
-CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x300000
CONFIG_SF_DEFAULT_SPEED=20000000
CONFIG_ENV_OFFSET=0x3F8000
CONFIG_DEFAULT_DEVICE_TREE="rk3399-evb"
CONFIG_DM_RESET=y
CONFIG_ROCKCHIP_RK3399=y
CONFIG_TARGET_EVB_RK3399=y
-CONFIG_SPL_STACK=0x400000
CONFIG_DEBUG_UART_BASE=0xFF1A0000
CONFIG_DEBUG_UART_CLOCK=24000000
CONFIG_SYS_LOAD_ADDR=0x800800
@@ -21,13 +17,7 @@
CONFIG_DISPLAY_BOARDINFO_LATE=y
CONFIG_SPL_MAX_SIZE=0x2e000
CONFIG_SPL_PAD_TO=0x7f8000
-CONFIG_SPL_HAS_BSS_LINKER_SECTION=y
-CONFIG_SPL_BSS_START_ADDR=0x400000
-CONFIG_SPL_BSS_MAX_SIZE=0x2000
# CONFIG_SPL_RAW_IMAGE_SUPPORT is not set
-# CONFIG_SPL_SHARES_INIT_SP_ADDR is not set
-CONFIG_SPL_STACK_R=y
-CONFIG_SPL_STACK_R_MALLOC_SIMPLE_LEN=0x10000
CONFIG_SPL_ATF_NO_PLATFORM_PARAM=y
CONFIG_TPL=y
CONFIG_CMD_BOOTZ=y
@@ -43,7 +33,6 @@
CONFIG_NET_RANDOM_ETHADDR=y
CONFIG_ROCKCHIP_GPIO=y
CONFIG_SYS_I2C_ROCKCHIP=y
-CONFIG_MISC=y
CONFIG_MMC_HS400_SUPPORT=y
CONFIG_MMC_DW=y
CONFIG_MMC_DW_ROCKCHIP=y
diff --git a/configs/evb-rk3568_defconfig b/configs/evb-rk3568_defconfig
index cb9b87f..6e8061f 100644
--- a/configs/evb-rk3568_defconfig
+++ b/configs/evb-rk3568_defconfig
@@ -2,18 +2,10 @@
CONFIG_SKIP_LOWLEVEL_INIT=y
CONFIG_COUNTER_FREQUENCY=24000000
CONFIG_ARCH_ROCKCHIP=y
-CONFIG_TEXT_BASE=0x00a00000
-CONFIG_SPL_LIBCOMMON_SUPPORT=y
-CONFIG_SPL_LIBGENERIC_SUPPORT=y
CONFIG_NR_DRAM_BANKS=2
-CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y
-CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0xc00000
CONFIG_DEFAULT_DEVICE_TREE="rk3568-evb"
CONFIG_ROCKCHIP_RK3568=y
-CONFIG_SPL_ROCKCHIP_COMMON_BOARD=y
CONFIG_SPL_SERIAL=y
-CONFIG_SPL_STACK_R_ADDR=0x600000
-CONFIG_SPL_STACK=0x400000
CONFIG_DEBUG_UART_BASE=0xFE660000
CONFIG_DEBUG_UART_CLOCK=24000000
CONFIG_SYS_LOAD_ADDR=0xc00800
@@ -28,12 +20,7 @@
CONFIG_DISPLAY_BOARDINFO_LATE=y
CONFIG_SPL_MAX_SIZE=0x40000
CONFIG_SPL_PAD_TO=0x7f8000
-CONFIG_SPL_HAS_BSS_LINKER_SECTION=y
-CONFIG_SPL_BSS_START_ADDR=0x4000000
-CONFIG_SPL_BSS_MAX_SIZE=0x4000
# CONFIG_SPL_RAW_IMAGE_SUPPORT is not set
-# CONFIG_SPL_SHARES_INIT_SP_ADDR is not set
-CONFIG_SPL_STACK_R=y
CONFIG_SPL_ATF=y
CONFIG_CMD_GPIO=y
CONFIG_CMD_GPT=y
diff --git a/configs/evb-rk3588_defconfig b/configs/evb-rk3588_defconfig
index 8a6aa91..c8db04c 100644
--- a/configs/evb-rk3588_defconfig
+++ b/configs/evb-rk3588_defconfig
@@ -2,19 +2,11 @@
CONFIG_SKIP_LOWLEVEL_INIT=y
CONFIG_COUNTER_FREQUENCY=24000000
CONFIG_ARCH_ROCKCHIP=y
-CONFIG_TEXT_BASE=0x00a00000
-CONFIG_SPL_LIBCOMMON_SUPPORT=y
-CONFIG_SPL_LIBGENERIC_SUPPORT=y
CONFIG_NR_DRAM_BANKS=2
-CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y
-CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0xc00000
CONFIG_DEFAULT_DEVICE_TREE="rk3588-evb1-v10"
CONFIG_ROCKCHIP_RK3588=y
-CONFIG_SPL_ROCKCHIP_COMMON_BOARD=y
CONFIG_SPL_SERIAL=y
-CONFIG_SPL_STACK_R_ADDR=0x600000
CONFIG_TARGET_EVB_RK3588=y
-CONFIG_SPL_STACK=0x400000
CONFIG_DEBUG_UART_BASE=0xFEB50000
CONFIG_DEBUG_UART_CLOCK=24000000
CONFIG_SYS_LOAD_ADDR=0xc00800
@@ -30,12 +22,7 @@
CONFIG_DISPLAY_BOARDINFO_LATE=y
CONFIG_SPL_MAX_SIZE=0x40000
CONFIG_SPL_PAD_TO=0x7f8000
-CONFIG_SPL_HAS_BSS_LINKER_SECTION=y
-CONFIG_SPL_BSS_START_ADDR=0x4000000
-CONFIG_SPL_BSS_MAX_SIZE=0x4000
# CONFIG_SPL_RAW_IMAGE_SUPPORT is not set
-# CONFIG_SPL_SHARES_INIT_SP_ADDR is not set
-CONFIG_SPL_STACK_R=y
CONFIG_SPL_ATF=y
CONFIG_CMD_GPIO=y
CONFIG_CMD_GPT=y
diff --git a/configs/ficus-rk3399_defconfig b/configs/ficus-rk3399_defconfig
index 90b07d8..4859042 100644
--- a/configs/ficus-rk3399_defconfig
+++ b/configs/ficus-rk3399_defconfig
@@ -42,6 +42,7 @@
CONFIG_NET_RANDOM_ETHADDR=y
CONFIG_ROCKCHIP_GPIO=y
CONFIG_SYS_I2C_ROCKCHIP=y
+CONFIG_ROCKCHIP_IODOMAIN=y
CONFIG_MMC_DW=y
CONFIG_MMC_DW_ROCKCHIP=y
CONFIG_MMC_SDHCI=y
diff --git a/configs/firefly-rk3399_defconfig b/configs/firefly-rk3399_defconfig
index b7c8e95..545c047 100644
--- a/configs/firefly-rk3399_defconfig
+++ b/configs/firefly-rk3399_defconfig
@@ -2,17 +2,13 @@
CONFIG_SKIP_LOWLEVEL_INIT=y
CONFIG_COUNTER_FREQUENCY=24000000
CONFIG_ARCH_ROCKCHIP=y
-CONFIG_TEXT_BASE=0x00200000
CONFIG_NR_DRAM_BANKS=1
-CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y
-CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x300000
CONFIG_SF_DEFAULT_SPEED=20000000
CONFIG_ENV_OFFSET=0x3F8000
CONFIG_DEFAULT_DEVICE_TREE="rk3399-firefly"
CONFIG_DM_RESET=y
CONFIG_ROCKCHIP_RK3399=y
CONFIG_TARGET_EVB_RK3399=y
-CONFIG_SPL_STACK=0x400000
CONFIG_DEBUG_UART_BASE=0xFF1A0000
CONFIG_DEBUG_UART_CLOCK=24000000
CONFIG_SYS_LOAD_ADDR=0x800800
@@ -20,16 +16,9 @@
CONFIG_DEBUG_UART=y
CONFIG_DEFAULT_FDT_FILE="rockchip/rk3399-firefly.dtb"
CONFIG_DISPLAY_BOARDINFO_LATE=y
-CONFIG_MISC_INIT_R=y
CONFIG_SPL_MAX_SIZE=0x2e000
CONFIG_SPL_PAD_TO=0x7f8000
-CONFIG_SPL_HAS_BSS_LINKER_SECTION=y
-CONFIG_SPL_BSS_START_ADDR=0x400000
-CONFIG_SPL_BSS_MAX_SIZE=0x2000
# CONFIG_SPL_RAW_IMAGE_SUPPORT is not set
-# CONFIG_SPL_SHARES_INIT_SP_ADDR is not set
-CONFIG_SPL_STACK_R=y
-CONFIG_SPL_STACK_R_MALLOC_SIMPLE_LEN=0x10000
CONFIG_SPL_ATF_NO_PLATFORM_PARAM=y
CONFIG_TPL=y
CONFIG_CMD_BOOTZ=y
@@ -45,8 +34,6 @@
CONFIG_SYS_RELOC_GD_ENV_ADDR=y
CONFIG_ROCKCHIP_GPIO=y
CONFIG_SYS_I2C_ROCKCHIP=y
-CONFIG_MISC=y
-CONFIG_ROCKCHIP_EFUSE=y
CONFIG_MMC_DW=y
CONFIG_MMC_DW_ROCKCHIP=y
CONFIG_MMC_SDHCI=y
diff --git a/configs/generic-rk3568_defconfig b/configs/generic-rk3568_defconfig
index 8fb79c9..e7d5e55 100644
--- a/configs/generic-rk3568_defconfig
+++ b/configs/generic-rk3568_defconfig
@@ -2,18 +2,10 @@
CONFIG_SKIP_LOWLEVEL_INIT=y
CONFIG_COUNTER_FREQUENCY=24000000
CONFIG_ARCH_ROCKCHIP=y
-CONFIG_TEXT_BASE=0x00a00000
-CONFIG_SPL_LIBCOMMON_SUPPORT=y
-CONFIG_SPL_LIBGENERIC_SUPPORT=y
CONFIG_NR_DRAM_BANKS=2
-CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y
-CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0xc00000
CONFIG_DEFAULT_DEVICE_TREE="rk3568-generic"
CONFIG_ROCKCHIP_RK3568=y
-CONFIG_SPL_ROCKCHIP_COMMON_BOARD=y
CONFIG_SPL_SERIAL=y
-CONFIG_SPL_STACK_R_ADDR=0x600000
-CONFIG_SPL_STACK=0x400000
CONFIG_DEBUG_UART_BASE=0xFE660000
CONFIG_DEBUG_UART_CLOCK=24000000
CONFIG_SYS_LOAD_ADDR=0xc00800
@@ -28,12 +20,7 @@
CONFIG_DISPLAY_BOARDINFO_LATE=y
CONFIG_SPL_MAX_SIZE=0x40000
CONFIG_SPL_PAD_TO=0x7f8000
-CONFIG_SPL_HAS_BSS_LINKER_SECTION=y
-CONFIG_SPL_BSS_START_ADDR=0x4000000
-CONFIG_SPL_BSS_MAX_SIZE=0x4000
# CONFIG_SPL_RAW_IMAGE_SUPPORT is not set
-# CONFIG_SPL_SHARES_INIT_SP_ADDR is not set
-CONFIG_SPL_STACK_R=y
CONFIG_SPL_ATF=y
CONFIG_CMD_GPIO=y
CONFIG_CMD_GPT=y
diff --git a/configs/generic-rk3588_defconfig b/configs/generic-rk3588_defconfig
new file mode 100644
index 0000000..b50f4f8
--- /dev/null
+++ b/configs/generic-rk3588_defconfig
@@ -0,0 +1,53 @@
+CONFIG_ARM=y
+CONFIG_SKIP_LOWLEVEL_INIT=y
+CONFIG_COUNTER_FREQUENCY=24000000
+CONFIG_ARCH_ROCKCHIP=y
+CONFIG_NR_DRAM_BANKS=2
+CONFIG_DEFAULT_DEVICE_TREE="rk3588-generic"
+CONFIG_ROCKCHIP_RK3588=y
+CONFIG_SPL_SERIAL=y
+CONFIG_TARGET_EVB_RK3588=y
+CONFIG_DEBUG_UART_BASE=0xFEB50000
+CONFIG_DEBUG_UART_CLOCK=24000000
+CONFIG_SYS_LOAD_ADDR=0xc00800
+CONFIG_DEBUG_UART=y
+CONFIG_FIT=y
+CONFIG_FIT_VERBOSE=y
+CONFIG_SPL_FIT_SIGNATURE=y
+CONFIG_SPL_LOAD_FIT=y
+CONFIG_LEGACY_IMAGE_FORMAT=y
+CONFIG_OF_BOARD_SETUP=y
+CONFIG_DEFAULT_FDT_FILE="rockchip/rk3588-generic.dtb"
+# CONFIG_DISPLAY_CPUINFO is not set
+CONFIG_DISPLAY_BOARDINFO_LATE=y
+CONFIG_SPL_MAX_SIZE=0x40000
+CONFIG_SPL_PAD_TO=0x7f8000
+# CONFIG_SPL_RAW_IMAGE_SUPPORT is not set
+CONFIG_SPL_ATF=y
+CONFIG_CMD_GPIO=y
+CONFIG_CMD_GPT=y
+CONFIG_CMD_MMC=y
+# CONFIG_CMD_SETEXPR is not set
+# CONFIG_SPL_DOS_PARTITION is not set
+CONFIG_SPL_OF_CONTROL=y
+CONFIG_OF_LIVE=y
+CONFIG_OF_SPL_REMOVE_PROPS="clock-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents"
+CONFIG_SPL_DM_SEQ_ALIAS=y
+CONFIG_SPL_REGMAP=y
+CONFIG_SPL_SYSCON=y
+CONFIG_SPL_CLK=y
+CONFIG_ROCKCHIP_GPIO=y
+CONFIG_MISC=y
+CONFIG_SUPPORT_EMMC_RPMB=y
+CONFIG_MMC_DW=y
+CONFIG_MMC_DW_ROCKCHIP=y
+CONFIG_MMC_SDHCI=y
+CONFIG_MMC_SDHCI_SDMA=y
+CONFIG_MMC_SDHCI_ROCKCHIP=y
+CONFIG_SPL_PINCTRL=y
+CONFIG_SPL_RAM=y
+CONFIG_BAUDRATE=1500000
+CONFIG_DEBUG_UART_SHIFT=2
+CONFIG_SYS_NS16550_MEM32=y
+CONFIG_SYSRESET=y
+CONFIG_ERRNO_STR=y
diff --git a/configs/goflexhome_defconfig b/configs/goflexhome_defconfig
index d577d58..53b2ce9 100644
--- a/configs/goflexhome_defconfig
+++ b/configs/goflexhome_defconfig
@@ -13,7 +13,7 @@
CONFIG_TARGET_GOFLEXHOME=y
CONFIG_ENV_SIZE=0x20000
CONFIG_ENV_OFFSET=0xC0000
-CONFIG_DEFAULT_DEVICE_TREE="kirkwood-goflexnet"
+CONFIG_DEFAULT_DEVICE_TREE="marvell/kirkwood-goflexnet"
CONFIG_IDENT_STRING="\nSeagate GoFlex Home"
CONFIG_SYS_LOAD_ADDR=0x800000
CONFIG_BOOTDELAY=3
diff --git a/configs/guruplug_defconfig b/configs/guruplug_defconfig
index 7cb649e..5371ee4 100644
--- a/configs/guruplug_defconfig
+++ b/configs/guruplug_defconfig
@@ -10,7 +10,7 @@
CONFIG_TARGET_GURUPLUG=y
CONFIG_ENV_SIZE=0x20000
CONFIG_ENV_OFFSET=0xE0000
-CONFIG_DEFAULT_DEVICE_TREE="kirkwood-guruplug-server-plus"
+CONFIG_DEFAULT_DEVICE_TREE="marvell/kirkwood-guruplug-server-plus"
CONFIG_IDENT_STRING="\nMarvell-GuruPlug"
CONFIG_SYS_LOAD_ADDR=0x800000
# CONFIG_SYS_MALLOC_F is not set
diff --git a/configs/ib62x0_defconfig b/configs/ib62x0_defconfig
index 074384e..32b0e1c 100644
--- a/configs/ib62x0_defconfig
+++ b/configs/ib62x0_defconfig
@@ -10,7 +10,7 @@
CONFIG_TARGET_IB62X0=y
CONFIG_ENV_SIZE=0x20000
CONFIG_ENV_OFFSET=0xE0000
-CONFIG_DEFAULT_DEVICE_TREE="kirkwood-ib62x0"
+CONFIG_DEFAULT_DEVICE_TREE="marvell/kirkwood-ib62x0"
CONFIG_IDENT_STRING=" RaidSonic ICY BOX IB-NAS62x0"
CONFIG_SYS_LOAD_ADDR=0x800000
# CONFIG_SYS_MALLOC_F is not set
diff --git a/configs/iconnect_defconfig b/configs/iconnect_defconfig
index f7b74c4..45ffbd9 100644
--- a/configs/iconnect_defconfig
+++ b/configs/iconnect_defconfig
@@ -13,7 +13,7 @@
CONFIG_TARGET_ICONNECT=y
CONFIG_ENV_SIZE=0x20000
CONFIG_ENV_OFFSET=0x80000
-CONFIG_DEFAULT_DEVICE_TREE="kirkwood-iconnect"
+CONFIG_DEFAULT_DEVICE_TREE="marvell/kirkwood-iconnect"
CONFIG_IDENT_STRING=" Iomega iConnect"
CONFIG_SYS_LOAD_ADDR=0x800000
CONFIG_PCI=y
diff --git a/configs/imx28_xea_defconfig b/configs/imx28_xea_defconfig
index 64a0561..822a329 100644
--- a/configs/imx28_xea_defconfig
+++ b/configs/imx28_xea_defconfig
@@ -21,12 +21,15 @@
CONFIG_SPL_SERIAL=y
CONFIG_SPL_STACK=0x20000
CONFIG_SPL_SYS_MALLOC_F_LEN=0x1000
+CONFIG_SPL_SIZE_LIMIT=0xa000
CONFIG_SPL=y
CONFIG_ENV_OFFSET_REDUND=0x90000
CONFIG_SPL_SPI_FLASH_SUPPORT=y
CONFIG_SPL_SPI=y
CONFIG_SYS_LOAD_ADDR=0x42000000
CONFIG_SPL_PAYLOAD="u-boot.img"
+CONFIG_HAS_BOARD_SIZE_LIMIT=y
+CONFIG_BOARD_SIZE_LIMIT=458752
CONFIG_TIMESTAMP=y
CONFIG_FIT=y
# CONFIG_BOOTMETH_EXTLINUX is not set
@@ -39,6 +42,7 @@
CONFIG_USE_PREBOOT=y
CONFIG_PREBOOT="run prebootcmd"
CONFIG_BOARD_EARLY_INIT_F=y
+CONFIG_BOARD_LATE_INIT=y
CONFIG_SPL_NO_BSS_LIMIT=y
CONFIG_SPL_BOARD_INIT=y
# CONFIG_SPL_RAW_IMAGE_SUPPORT is not set
diff --git a/configs/imx28_xea_sb_defconfig b/configs/imx28_xea_sb_defconfig
index 9872d35..8d48d8c 100644
--- a/configs/imx28_xea_sb_defconfig
+++ b/configs/imx28_xea_sb_defconfig
@@ -23,6 +23,7 @@
CONFIG_USE_PREBOOT=y
CONFIG_PREBOOT="run prebootcmd"
CONFIG_BOARD_EARLY_INIT_F=y
+CONFIG_BOARD_LATE_INIT=y
# CONFIG_SPL_FRAMEWORK is not set
CONFIG_SPL_NO_BSS_LIMIT=y
CONFIG_SPL_BOARD_INIT=y
diff --git a/configs/imx8mm_beacon_defconfig b/configs/imx8mm_beacon_defconfig
index b926798..0b601bb 100644
--- a/configs/imx8mm_beacon_defconfig
+++ b/configs/imx8mm_beacon_defconfig
@@ -10,7 +10,7 @@
CONFIG_ENV_SIZE=0x2000
CONFIG_ENV_OFFSET=0xFFFFDE00
CONFIG_DM_GPIO=y
-CONFIG_DEFAULT_DEVICE_TREE="imx8mm-beacon-kit"
+CONFIG_DEFAULT_DEVICE_TREE="freescale/imx8mm-beacon-kit"
CONFIG_SPL_TEXT_BASE=0x7E1000
CONFIG_TARGET_IMX8MM_BEACON=y
CONFIG_SYS_MONITOR_LEN=524288
diff --git a/configs/imx8mm_beacon_fspi_defconfig b/configs/imx8mm_beacon_fspi_defconfig
index 341ea47..eaf8dce 100644
--- a/configs/imx8mm_beacon_fspi_defconfig
+++ b/configs/imx8mm_beacon_fspi_defconfig
@@ -11,7 +11,7 @@
CONFIG_ENV_OFFSET=0xFFFFDE00
CONFIG_IMX_CONFIG="board/freescale/imx8mm_evk/imximage-8mm-lpddr4-fspi.cfg"
CONFIG_DM_GPIO=y
-CONFIG_DEFAULT_DEVICE_TREE="imx8mm-beacon-kit"
+CONFIG_DEFAULT_DEVICE_TREE="freescale/imx8mm-beacon-kit"
CONFIG_SPL_TEXT_BASE=0x7E2000
CONFIG_TARGET_IMX8MM_BEACON=y
CONFIG_SYS_MONITOR_LEN=524288
diff --git a/configs/imx8mm_evk_defconfig b/configs/imx8mm_evk_defconfig
index b51e393..e41facd 100644
--- a/configs/imx8mm_evk_defconfig
+++ b/configs/imx8mm_evk_defconfig
@@ -8,7 +8,7 @@
CONFIG_ENV_SIZE=0x1000
CONFIG_ENV_OFFSET=0x400000
CONFIG_DM_GPIO=y
-CONFIG_DEFAULT_DEVICE_TREE="imx8mm-evk"
+CONFIG_DEFAULT_DEVICE_TREE="freescale/imx8mm-evk"
CONFIG_SPL_TEXT_BASE=0x7E1000
CONFIG_TARGET_IMX8MM_EVK=y
CONFIG_SYS_MONITOR_LEN=524288
diff --git a/configs/imx8mm_evk_fspi_defconfig b/configs/imx8mm_evk_fspi_defconfig
index 34e8071..3aaf7a4 100644
--- a/configs/imx8mm_evk_fspi_defconfig
+++ b/configs/imx8mm_evk_fspi_defconfig
@@ -11,7 +11,7 @@
CONFIG_ENV_OFFSET=0x400000
CONFIG_IMX_CONFIG="board/freescale/imx8mm_evk/imximage-8mm-lpddr4-fspi.cfg"
CONFIG_DM_GPIO=y
-CONFIG_DEFAULT_DEVICE_TREE="imx8mm-evk"
+CONFIG_DEFAULT_DEVICE_TREE="freescale/imx8mm-evk"
CONFIG_SPL_TEXT_BASE=0x7E2000
CONFIG_TARGET_IMX8MM_EVK=y
CONFIG_SYS_MONITOR_LEN=524288
diff --git a/configs/imx8mm_venice_defconfig b/configs/imx8mm_venice_defconfig
index 97507db..cb6b97d 100644
--- a/configs/imx8mm_venice_defconfig
+++ b/configs/imx8mm_venice_defconfig
@@ -8,7 +8,7 @@
CONFIG_ENV_SIZE=0x8000
CONFIG_ENV_OFFSET=0x3f0000
CONFIG_DM_GPIO=y
-CONFIG_DEFAULT_DEVICE_TREE="imx8mm-venice"
+CONFIG_DEFAULT_DEVICE_TREE="freescale/imx8mm-venice-gw71xx-0x"
CONFIG_SPL_TEXT_BASE=0x7E1000
CONFIG_TARGET_IMX8MM_VENICE=y
CONFIG_OF_LIBFDT_OVERLAY=y
@@ -73,7 +73,7 @@
# CONFIG_SPL_EFI_PARTITION is not set
CONFIG_OF_CONTROL=y
CONFIG_SPL_OF_CONTROL=y
-CONFIG_OF_LIST="imx8mm-venice imx8mm-venice-gw71xx-0x imx8mm-venice-gw72xx-0x imx8mm-venice-gw73xx-0x imx8mm-venice-gw7901 imx8mm-venice-gw7902 imx8mm-venice-gw7903 imx8mm-venice-gw7904 imx8mm-venice-gw7905-0x"
+CONFIG_OF_LIST="freescale/imx8mm-venice-gw71xx-0x freescale/imx8mm-venice-gw72xx-0x freescale/imx8mm-venice-gw73xx-0x freescale/imx8mm-venice-gw7901 freescale/imx8mm-venice-gw7902 freescale/imx8mm-venice-gw7903 freescale/imx8mm-venice-gw7904 freescale/imx8mm-venice-gw7905-0x"
CONFIG_ENV_IS_IN_MMC=y
CONFIG_SYS_REDUNDAND_ENVIRONMENT=y
CONFIG_SYS_MMC_ENV_DEV=2
diff --git a/configs/imx8mn_beacon_2g_defconfig b/configs/imx8mn_beacon_2g_defconfig
index 2d4cd1f..e8009c4 100644
--- a/configs/imx8mn_beacon_2g_defconfig
+++ b/configs/imx8mn_beacon_2g_defconfig
@@ -11,7 +11,7 @@
CONFIG_ENV_SIZE=0x2000
CONFIG_ENV_OFFSET=0xFFFFDE00
CONFIG_DM_GPIO=y
-CONFIG_DEFAULT_DEVICE_TREE="imx8mn-beacon-kit"
+CONFIG_DEFAULT_DEVICE_TREE="freescale/imx8mn-beacon-kit"
CONFIG_SPL_TEXT_BASE=0x912000
CONFIG_TARGET_IMX8MN_BEACON=y
CONFIG_IMX8MN_BEACON_2GB_LPDDR=y
diff --git a/configs/imx8mn_beacon_defconfig b/configs/imx8mn_beacon_defconfig
index ec93301..ed671cf 100644
--- a/configs/imx8mn_beacon_defconfig
+++ b/configs/imx8mn_beacon_defconfig
@@ -11,7 +11,7 @@
CONFIG_ENV_SIZE=0x2000
CONFIG_ENV_OFFSET=0xFFFFDE00
CONFIG_DM_GPIO=y
-CONFIG_DEFAULT_DEVICE_TREE="imx8mn-beacon-kit"
+CONFIG_DEFAULT_DEVICE_TREE="freescale/imx8mn-beacon-kit"
CONFIG_SPL_TEXT_BASE=0x912000
CONFIG_TARGET_IMX8MN_BEACON=y
CONFIG_OF_LIBFDT_OVERLAY=y
diff --git a/configs/imx8mn_beacon_fspi_defconfig b/configs/imx8mn_beacon_fspi_defconfig
index 458afba..11c257a 100644
--- a/configs/imx8mn_beacon_fspi_defconfig
+++ b/configs/imx8mn_beacon_fspi_defconfig
@@ -11,7 +11,7 @@
CONFIG_ENV_SIZE=0x2000
CONFIG_ENV_OFFSET=0xFFFFDE00
CONFIG_DM_GPIO=y
-CONFIG_DEFAULT_DEVICE_TREE="imx8mn-beacon-kit"
+CONFIG_DEFAULT_DEVICE_TREE="freescale/imx8mn-beacon-kit"
CONFIG_SPL_TEXT_BASE=0x912000
CONFIG_TARGET_IMX8MN_BEACON=y
CONFIG_OF_LIBFDT_OVERLAY=y
diff --git a/configs/imx8mn_ddr4_evk_defconfig b/configs/imx8mn_ddr4_evk_defconfig
index 743dea5..56b8880 100644
--- a/configs/imx8mn_ddr4_evk_defconfig
+++ b/configs/imx8mn_ddr4_evk_defconfig
@@ -8,7 +8,7 @@
CONFIG_ENV_SIZE=0x1000
CONFIG_ENV_OFFSET=0x400000
CONFIG_DM_GPIO=y
-CONFIG_DEFAULT_DEVICE_TREE="imx8mn-ddr4-evk"
+CONFIG_DEFAULT_DEVICE_TREE="freescale/imx8mn-ddr4-evk"
CONFIG_SPL_TEXT_BASE=0x912000
CONFIG_TARGET_IMX8MN_DDR4_EVK=y
CONFIG_SYS_MONITOR_LEN=524288
diff --git a/configs/imx8mn_evk_defconfig b/configs/imx8mn_evk_defconfig
index 5098fe5..91b7586 100644
--- a/configs/imx8mn_evk_defconfig
+++ b/configs/imx8mn_evk_defconfig
@@ -8,7 +8,7 @@
CONFIG_ENV_SIZE=0x1000
CONFIG_ENV_OFFSET=0x400000
CONFIG_DM_GPIO=y
-CONFIG_DEFAULT_DEVICE_TREE="imx8mn-evk"
+CONFIG_DEFAULT_DEVICE_TREE="freescale/imx8mn-evk"
CONFIG_SPL_TEXT_BASE=0x912000
CONFIG_TARGET_IMX8MN_EVK=y
CONFIG_SYS_MONITOR_LEN=524288
diff --git a/configs/imx8mn_venice_defconfig b/configs/imx8mn_venice_defconfig
index dcf5035..0a4fba5 100644
--- a/configs/imx8mn_venice_defconfig
+++ b/configs/imx8mn_venice_defconfig
@@ -8,7 +8,7 @@
CONFIG_ENV_SIZE=0x8000
CONFIG_ENV_OFFSET=0x3f0000
CONFIG_DM_GPIO=y
-CONFIG_DEFAULT_DEVICE_TREE="imx8mn-venice"
+CONFIG_DEFAULT_DEVICE_TREE="freescale/imx8mn-venice-gw7902"
CONFIG_SPL_TEXT_BASE=0x912000
CONFIG_TARGET_IMX8MN_VENICE=y
CONFIG_OF_LIBFDT_OVERLAY=y
@@ -76,7 +76,7 @@
# CONFIG_SPL_EFI_PARTITION is not set
CONFIG_OF_CONTROL=y
CONFIG_SPL_OF_CONTROL=y
-CONFIG_OF_LIST="imx8mn-venice imx8mn-venice-gw7902"
+CONFIG_OF_LIST="freescale/imx8mn-venice-gw7902"
CONFIG_ENV_IS_IN_MMC=y
CONFIG_SYS_REDUNDAND_ENVIRONMENT=y
CONFIG_SYS_MMC_ENV_DEV=2
diff --git a/configs/imx8mp_beacon_defconfig b/configs/imx8mp_beacon_defconfig
index 9d09dd4..fe1678d 100644
--- a/configs/imx8mp_beacon_defconfig
+++ b/configs/imx8mp_beacon_defconfig
@@ -12,9 +12,10 @@
CONFIG_ENV_SIZE=0x2000
CONFIG_ENV_OFFSET=0xFFFFDE00
CONFIG_DM_GPIO=y
-CONFIG_DEFAULT_DEVICE_TREE="imx8mp-beacon-kit"
+CONFIG_DEFAULT_DEVICE_TREE="freescale/imx8mp-beacon-kit"
CONFIG_SPL_TEXT_BASE=0x920000
CONFIG_TARGET_IMX8MP_BEACON=y
+CONFIG_DM_RESET=y
CONFIG_SYS_MONITOR_LEN=524288
CONFIG_SPL_MMC=y
CONFIG_SPL_SERIAL=y
@@ -27,6 +28,7 @@
CONFIG_ARMV8_EA_EL3_FIRST=y
CONFIG_SPL_IMX_ROMAPI_LOADADDR=0x48000000
CONFIG_SYS_LOAD_ADDR=0x40480000
+CONFIG_PCI=y
# CONFIG_ANDROID_BOOT_IMAGE is not set
CONFIG_FIT=y
CONFIG_FIT_EXTERNAL_OFFSET=0x3000
@@ -65,6 +67,7 @@
CONFIG_CMD_GPIO=y
CONFIG_CMD_I2C=y
CONFIG_CMD_MMC=y
+CONFIG_CMD_PCI=y
CONFIG_CMD_USB=y
CONFIG_CMD_USB_SDP=y
CONFIG_CMD_USB_MASS_STORAGE=y
@@ -118,8 +121,11 @@
CONFIG_FEC_MXC=y
CONFIG_RGMII=y
CONFIG_MII=y
+CONFIG_NVME_PCI=y
+CONFIG_PCIE_DW_IMX=y
CONFIG_PHY=y
CONFIG_PHY_IMX8MQ_USB=y
+CONFIG_PHY_IMX8M_PCIE=y
CONFIG_PINCTRL=y
CONFIG_SPL_PINCTRL=y
CONFIG_PINCTRL_IMX8M=y
diff --git a/configs/imx8mp_evk_defconfig b/configs/imx8mp_evk_defconfig
index 2846faa..7e5dfce 100644
--- a/configs/imx8mp_evk_defconfig
+++ b/configs/imx8mp_evk_defconfig
@@ -8,7 +8,7 @@
CONFIG_ENV_SIZE=0x1000
CONFIG_ENV_OFFSET=0x400000
CONFIG_DM_GPIO=y
-CONFIG_DEFAULT_DEVICE_TREE="imx8mp-evk"
+CONFIG_DEFAULT_DEVICE_TREE="freescale/imx8mp-evk"
CONFIG_SPL_TEXT_BASE=0x920000
CONFIG_TARGET_IMX8MP_EVK=y
CONFIG_SYS_MONITOR_LEN=524288
diff --git a/configs/imx8mp_venice_defconfig b/configs/imx8mp_venice_defconfig
index ecb08ca..6e4addc 100644
--- a/configs/imx8mp_venice_defconfig
+++ b/configs/imx8mp_venice_defconfig
@@ -8,10 +8,11 @@
CONFIG_ENV_SIZE=0x8000
CONFIG_ENV_OFFSET=0x3f0000
CONFIG_DM_GPIO=y
-CONFIG_DEFAULT_DEVICE_TREE="imx8mp-venice"
+CONFIG_DEFAULT_DEVICE_TREE="freescale/imx8mp-venice-gw71xx-2x"
CONFIG_SPL_TEXT_BASE=0x920000
CONFIG_TARGET_IMX8MP_VENICE=y
CONFIG_OF_LIBFDT_OVERLAY=y
+CONFIG_DM_RESET=y
CONFIG_SYS_MONITOR_LEN=524288
CONFIG_SPL_MMC=y
CONFIG_SPL_SERIAL=y
@@ -21,6 +22,7 @@
CONFIG_ENV_OFFSET_REDUND=0x3f8000
CONFIG_SPL_IMX_ROMAPI_LOADADDR=0x48000000
CONFIG_SYS_LOAD_ADDR=0x40480000
+CONFIG_PCI=y
CONFIG_SYS_MEMTEST_START=0x40000000
CONFIG_SYS_MEMTEST_END=0x80000000
CONFIG_FIT=y
@@ -63,6 +65,7 @@
CONFIG_CMD_GPIO=y
CONFIG_CMD_I2C=y
CONFIG_CMD_MMC=y
+CONFIG_CMD_PCI=y
CONFIG_CMD_USB=y
CONFIG_SYS_DISABLE_AUTOLOAD=y
CONFIG_CMD_CACHE=y
@@ -75,7 +78,7 @@
# CONFIG_SPL_EFI_PARTITION is not set
CONFIG_OF_CONTROL=y
CONFIG_SPL_OF_CONTROL=y
-CONFIG_OF_LIST="imx8mp-venice imx8mp-venice-gw71xx-2x imx8mp-venice-gw72xx-2x imx8mp-venice-gw73xx-2x imx8mp-venice-gw74xx imx8mp-venice-gw7905-2x"
+CONFIG_OF_LIST="freescale/imx8mp-venice-gw71xx-2x freescale/imx8mp-venice-gw72xx-2x freescale/imx8mp-venice-gw73xx-2x freescale/imx8mp-venice-gw74xx freescale/imx8mp-venice-gw7905-2x"
CONFIG_ENV_IS_IN_MMC=y
CONFIG_SYS_REDUNDAND_ENVIRONMENT=y
CONFIG_SYS_MMC_ENV_DEV=2
@@ -84,6 +87,8 @@
CONFIG_IP_DEFRAG=y
CONFIG_TFTP_BLOCKSIZE=4096
CONFIG_SPL_DM=y
+CONFIG_REGMAP=y
+CONFIG_SYSCON=y
CONFIG_CLK_COMPOSITE_CCF=y
CONFIG_CLK_IMX8MP=y
CONFIG_GPIO_HOG=y
@@ -112,7 +117,10 @@
CONFIG_KSZ9477=y
CONFIG_RGMII=y
CONFIG_MII=y
+CONFIG_NVME_PCI=y
+CONFIG_PCIE_DW_IMX=y
CONFIG_PHY_IMX8MQ_USB=y
+CONFIG_PHY_IMX8M_PCIE=y
CONFIG_PINCTRL=y
CONFIG_SPL_PINCTRL=y
CONFIG_PINCTRL_IMX8M=y
diff --git a/configs/imx8mq_evk_defconfig b/configs/imx8mq_evk_defconfig
index 941b845..3a2d88a 100644
--- a/configs/imx8mq_evk_defconfig
+++ b/configs/imx8mq_evk_defconfig
@@ -11,7 +11,7 @@
CONFIG_SYS_I2C_MXC_I2C2=y
CONFIG_SYS_I2C_MXC_I2C3=y
CONFIG_DM_GPIO=y
-CONFIG_DEFAULT_DEVICE_TREE="imx8mq-evk"
+CONFIG_DEFAULT_DEVICE_TREE="freescale/imx8mq-evk"
CONFIG_SPL_TEXT_BASE=0x7E1000
CONFIG_TARGET_IMX8MQ_EVK=y
CONFIG_DM_RESET=y
diff --git a/configs/imx93-phyboard-segin_defconfig b/configs/imx93-phyboard-segin_defconfig
index 24f9bd5..54215c5 100644
--- a/configs/imx93-phyboard-segin_defconfig
+++ b/configs/imx93-phyboard-segin_defconfig
@@ -67,6 +67,7 @@
CONFIG_CMD_I2C=y
CONFIG_CMD_MMC=y
CONFIG_CMD_POWEROFF=y
+CONFIG_CMD_USB=y
CONFIG_CMD_SNTP=y
CONFIG_CMD_CACHE=y
CONFIG_CMD_EFIDEBUG=y
@@ -93,6 +94,12 @@
CONFIG_CLK_IMX93=y
CONFIG_DFU_MMC=y
CONFIG_DFU_RAM=y
+CONFIG_USB_FUNCTION_FASTBOOT=y
+CONFIG_FASTBOOT_BUF_ADDR=0x82800000
+CONFIG_FASTBOOT_BUF_SIZE=0x20000000
+CONFIG_FASTBOOT_FLASH=y
+CONFIG_FASTBOOT_UUU_SUPPORT=y
+CONFIG_FASTBOOT_FLASH_MMC_DEV=0
CONFIG_GPIO_HOG=y
CONFIG_IMX_RGPIO2P=y
CONFIG_DM_I2C=y
@@ -132,6 +139,13 @@
CONFIG_SYSRESET_WATCHDOG=y
CONFIG_DM_THERMAL=y
CONFIG_IMX_TMU=y
+CONFIG_USB=y
+CONFIG_USB_EHCI_HCD=y
+CONFIG_USB_GADGET=y
+CONFIG_USB_GADGET_MANUFACTURER="PHYTEC"
+CONFIG_USB_GADGET_VENDOR_NUM=0x1fc9
+CONFIG_USB_GADGET_PRODUCT_NUM=0x0152
+CONFIG_CI_UDC=y
CONFIG_ULP_WATCHDOG=y
CONFIG_LZO=y
CONFIG_BZIP2=y
diff --git a/configs/inetspace_v2_defconfig b/configs/inetspace_v2_defconfig
index 2e8e3f3..3fa7790 100644
--- a/configs/inetspace_v2_defconfig
+++ b/configs/inetspace_v2_defconfig
@@ -11,7 +11,7 @@
CONFIG_ENV_SIZE=0x1000
CONFIG_ENV_OFFSET=0x70000
CONFIG_ENV_SECT_SIZE=0x10000
-CONFIG_DEFAULT_DEVICE_TREE="kirkwood-is2"
+CONFIG_DEFAULT_DEVICE_TREE="marvell/kirkwood-is2"
CONFIG_IDENT_STRING=" IS v2"
CONFIG_SYS_LOAD_ADDR=0x800000
CONFIG_ENV_ADDR=0x70000
diff --git a/configs/iot_devkit_defconfig b/configs/iot_devkit_defconfig
index c492005..d02a28a 100644
--- a/configs/iot_devkit_defconfig
+++ b/configs/iot_devkit_defconfig
@@ -14,12 +14,12 @@
CONFIG_SYS_CLK_FREQ=16000000
CONFIG_SYS_LOAD_ADDR=0x30000000
CONFIG_LOCALVERSION="-iotdk-1.0"
+# CONFIG_BOOTM is not set
# CONFIG_ARCH_FIXUP_FDT_MEMORY is not set
CONFIG_SYS_CBSIZE=256
CONFIG_SYS_PBSIZE=280
CONFIG_SYS_PROMPT="IoTDK# "
# CONFIG_CMD_BOOTD is not set
-# CONFIG_CMD_BOOTM is not set
# CONFIG_CMD_ELF is not set
# CONFIG_CMD_XIMG is not set
# CONFIG_CMD_LOADB is not set
diff --git a/configs/j7200_evm_a72_defconfig b/configs/j7200_evm_a72_defconfig
index 743d090..0f2e83d 100644
--- a/configs/j7200_evm_a72_defconfig
+++ b/configs/j7200_evm_a72_defconfig
@@ -10,6 +10,8 @@
CONFIG_TARGET_J7200_A72_EVM=y
CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y
CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x80480000
+CONFIG_SF_DEFAULT_SPEED=25000000
+CONFIG_SF_DEFAULT_MODE=0
CONFIG_ENV_SIZE=0x20000
CONFIG_DM_GPIO=y
CONFIG_SPL_DM_SPI=y
@@ -60,7 +62,7 @@
# CONFIG_SPL_SPI_FLASH_TINY is not set
CONFIG_SPL_SPI_FLASH_SFDP_SUPPORT=y
CONFIG_SPL_SPI_LOAD=y
-CONFIG_SYS_SPI_U_BOOT_OFFS=0x280000
+CONFIG_SYS_SPI_U_BOOT_OFFS=0x300000
CONFIG_SPL_YMODEM_SUPPORT=y
CONFIG_CMD_ASKENV=y
CONFIG_CMD_DFU=y
@@ -139,7 +141,11 @@
CONFIG_SYS_FLASH_CFI=y
CONFIG_SYS_MAX_FLASH_BANKS_DETECT=y
CONFIG_DM_SPI_FLASH=y
-CONFIG_SPI_FLASH_STMICRO=y
+CONFIG_SPI_FLASH_SFDP_SUPPORT=y
+CONFIG_SPI_FLASH_SOFT_RESET=y
+CONFIG_SPI_FLASH_SOFT_RESET_ON_BOOT=y
+CONFIG_SPI_FLASH_SPANSION=y
+CONFIG_SPI_FLASH_S28HX_T=y
# CONFIG_SPI_FLASH_USE_4K_SECTORS is not set
CONFIG_SPI_FLASH_MTD=y
CONFIG_MULTIPLEXER=y
diff --git a/configs/j7200_evm_r5_defconfig b/configs/j7200_evm_r5_defconfig
index 8a238f4..d5b44e3 100644
--- a/configs/j7200_evm_r5_defconfig
+++ b/configs/j7200_evm_r5_defconfig
@@ -10,6 +10,8 @@
CONFIG_TARGET_J7200_R5_EVM=y
CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y
CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x41cf5bfc
+CONFIG_SF_DEFAULT_SPEED=25000000
+CONFIG_SF_DEFAULT_MODE=0
CONFIG_ENV_SIZE=0x20000
CONFIG_DM_GPIO=y
CONFIG_SPL_DM_SPI=y
@@ -60,7 +62,7 @@
# CONFIG_SPL_SPI_FLASH_TINY is not set
CONFIG_SPL_SPI_FLASH_SFDP_SUPPORT=y
CONFIG_SPL_SPI_LOAD=y
-CONFIG_SYS_SPI_U_BOOT_OFFS=0x80000
+CONFIG_SYS_SPI_U_BOOT_OFFS=0x100000
CONFIG_SPL_YMODEM_SUPPORT=y
CONFIG_HUSH_PARSER=y
CONFIG_CMD_DFU=y
@@ -116,7 +118,10 @@
CONFIG_SYS_MAX_FLASH_BANKS_DETECT=y
CONFIG_DM_SPI_FLASH=y
CONFIG_SPI_FLASH_SFDP_SUPPORT=y
-CONFIG_SPI_FLASH_STMICRO=y
+CONFIG_SPI_FLASH_SOFT_RESET=y
+CONFIG_SPI_FLASH_SOFT_RESET_ON_BOOT=y
+CONFIG_SPI_FLASH_SPANSION=y
+CONFIG_SPI_FLASH_S28HX_T=y
CONFIG_PINCTRL=y
# CONFIG_PINCTRL_GENERIC is not set
CONFIG_SPL_PINCTRL=y
diff --git a/configs/jaguar-rk3588_defconfig b/configs/jaguar-rk3588_defconfig
new file mode 100644
index 0000000..3233b75
--- /dev/null
+++ b/configs/jaguar-rk3588_defconfig
@@ -0,0 +1,109 @@
+CONFIG_ARM=y
+CONFIG_SKIP_LOWLEVEL_INIT=y
+CONFIG_COUNTER_FREQUENCY=24000000
+CONFIG_ARCH_ROCKCHIP=y
+CONFIG_SPL_GPIO=y
+CONFIG_NR_DRAM_BANKS=2
+CONFIG_SF_DEFAULT_SPEED=24000000
+CONFIG_SF_DEFAULT_MODE=0x2000
+CONFIG_ENV_SIZE=0x1f000
+CONFIG_DEFAULT_DEVICE_TREE="rk3588-jaguar"
+CONFIG_ROCKCHIP_RK3588=y
+CONFIG_ROCKCHIP_BOOT_MODE_REG=0x0
+CONFIG_SPL_SERIAL=y
+CONFIG_TARGET_JAGUAR_RK3588=y
+CONFIG_DEBUG_UART_BASE=0xfeb50000
+CONFIG_DEBUG_UART_CLOCK=24000000
+CONFIG_SYS_LOAD_ADDR=0xc00800
+CONFIG_DEBUG_UART=y
+CONFIG_FIT=y
+CONFIG_FIT_VERBOSE=y
+CONFIG_SPL_FIT_SIGNATURE=y
+CONFIG_SPL_LOAD_FIT=y
+# CONFIG_BOOTMETH_VBE is not set
+CONFIG_LEGACY_IMAGE_FORMAT=y
+CONFIG_DEFAULT_FDT_FILE="rockchip/rk3588-jaguar.dtb"
+# CONFIG_DISPLAY_CPUINFO is not set
+CONFIG_DISPLAY_BOARDINFO_LATE=y
+CONFIG_CYCLIC=y
+CONFIG_SPL_MAX_SIZE=0x40000
+CONFIG_SPL_PAD_TO=0x7f8000
+# CONFIG_SPL_RAW_IMAGE_SUPPORT is not set
+CONFIG_SPL_ATF=y
+# CONFIG_BOOTM_NETBSD is not set
+# CONFIG_BOOTM_PLAN9 is not set
+# CONFIG_BOOTM_RTEMS is not set
+# CONFIG_BOOTM_VXWORKS is not set
+# CONFIG_CMD_ELF is not set
+CONFIG_CMD_ADC=y
+CONFIG_CMD_GPIO=y
+CONFIG_CMD_GPT=y
+CONFIG_CMD_I2C=y
+# CONFIG_CMD_LOADB is not set
+# CONFIG_CMD_LOADS is not set
+CONFIG_CMD_MMC=y
+# CONFIG_CMD_SF is not set
+CONFIG_CMD_USB=y
+# CONFIG_CMD_SETEXPR is not set
+# CONFIG_CMD_MII is not set
+# CONFIG_CMD_BLOCK_CACHE is not set
+# CONFIG_CMD_EFICONFIG is not set
+CONFIG_CMD_PMIC=y
+CONFIG_CMD_REGULATOR=y
+CONFIG_CMD_EROFS=y
+CONFIG_CMD_SQUASHFS=y
+# CONFIG_SPL_DOS_PARTITION is not set
+CONFIG_SPL_OF_CONTROL=y
+CONFIG_OF_LIVE=y
+# CONFIG_OF_TAG_MIGRATE is not set
+CONFIG_OF_SPL_REMOVE_PROPS="interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents"
+CONFIG_ENV_OVERWRITE=y
+CONFIG_ENV_IS_IN_MMC=y
+CONFIG_SYS_RELOC_GD_ENV_ADDR=y
+CONFIG_SPL_DM_SEQ_ALIAS=y
+CONFIG_SPL_REGMAP=y
+CONFIG_SPL_SYSCON=y
+CONFIG_BUTTON=y
+CONFIG_BUTTON_ADC=y
+CONFIG_SPL_CLK=y
+CONFIG_CLK_GPIO=y
+CONFIG_ROCKCHIP_GPIO=y
+CONFIG_SYS_I2C_ROCKCHIP=y
+CONFIG_MISC=y
+CONFIG_SUPPORT_EMMC_RPMB=y
+CONFIG_MMC_IO_VOLTAGE=y
+CONFIG_SPL_MMC_IO_VOLTAGE=y
+CONFIG_MMC_UHS_SUPPORT=y
+CONFIG_SPL_MMC_UHS_SUPPORT=y
+CONFIG_MMC_HS400_ES_SUPPORT=y
+CONFIG_SPL_MMC_HS400_ES_SUPPORT=y
+CONFIG_MMC_HS400_SUPPORT=y
+CONFIG_SPL_MMC_HS400_SUPPORT=y
+CONFIG_MMC_DW=y
+CONFIG_MMC_DW_ROCKCHIP=y
+CONFIG_MMC_SDHCI=y
+CONFIG_MMC_SDHCI_SDMA=y
+CONFIG_MMC_SDHCI_ROCKCHIP=y
+# CONFIG_SPI_FLASH is not set
+CONFIG_SF_DEFAULT_BUS=5
+CONFIG_PHY_MICREL=y
+CONFIG_PHY_MICREL_KSZ90X1=y
+CONFIG_DWC_ETH_QOS=y
+CONFIG_DWC_ETH_QOS_ROCKCHIP=y
+CONFIG_PHY_ROCKCHIP_INNO_USB2=y
+CONFIG_SPL_PINCTRL=y
+CONFIG_DM_PMIC=y
+CONFIG_PMIC_RK8XX=y
+CONFIG_REGULATOR_RK8XX=y
+CONFIG_SPL_RAM=y
+CONFIG_SCSI=y
+CONFIG_DEBUG_UART_SHIFT=2
+CONFIG_SYS_NS16550_MEM32=y
+CONFIG_ROCKCHIP_SPI=y
+CONFIG_SYSRESET=y
+CONFIG_USB=y
+CONFIG_USB_EHCI_HCD=y
+CONFIG_USB_EHCI_GENERIC=y
+CONFIG_USB_OHCI_HCD=y
+CONFIG_USB_OHCI_GENERIC=y
+CONFIG_ERRNO_STR=y
diff --git a/configs/jethub_j100_defconfig b/configs/jethub_j100_defconfig
index 8632454..9de6b4b 100644
--- a/configs/jethub_j100_defconfig
+++ b/configs/jethub_j100_defconfig
@@ -8,7 +8,7 @@
CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x20000000
CONFIG_ENV_SIZE=0x2000
CONFIG_DM_GPIO=y
-CONFIG_DEFAULT_DEVICE_TREE="meson-axg-jethome-jethub-j100"
+CONFIG_DEFAULT_DEVICE_TREE="amlogic/meson-axg-jethome-jethub-j100"
CONFIG_OF_LIBFDT_OVERLAY=y
CONFIG_DM_RESET=y
CONFIG_MESON_AXG=y
diff --git a/configs/jethub_j80_defconfig b/configs/jethub_j80_defconfig
index ca0808f..8530687 100644
--- a/configs/jethub_j80_defconfig
+++ b/configs/jethub_j80_defconfig
@@ -8,7 +8,7 @@
CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x20000000
CONFIG_ENV_SIZE=0x2000
CONFIG_DM_GPIO=y
-CONFIG_DEFAULT_DEVICE_TREE="meson-gxl-s905w-jethome-jethub-j80"
+CONFIG_DEFAULT_DEVICE_TREE="amlogic/meson-gxl-s905w-jethome-jethub-j80"
CONFIG_OF_LIBFDT_OVERLAY=y
CONFIG_DM_RESET=y
CONFIG_MESON_GXL=y
diff --git a/configs/khadas-edge-captain-rk3399_defconfig b/configs/khadas-edge-captain-rk3399_defconfig
index 7f4e48a..310250e 100644
--- a/configs/khadas-edge-captain-rk3399_defconfig
+++ b/configs/khadas-edge-captain-rk3399_defconfig
@@ -2,15 +2,11 @@
CONFIG_SKIP_LOWLEVEL_INIT=y
CONFIG_COUNTER_FREQUENCY=24000000
CONFIG_ARCH_ROCKCHIP=y
-CONFIG_TEXT_BASE=0x00200000
CONFIG_NR_DRAM_BANKS=1
-CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y
-CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x300000
CONFIG_ENV_OFFSET=0x3F8000
CONFIG_DEFAULT_DEVICE_TREE="rk3399-khadas-edge-captain"
CONFIG_ROCKCHIP_RK3399=y
CONFIG_TARGET_EVB_RK3399=y
-CONFIG_SPL_STACK=0x400000
CONFIG_DEBUG_UART_BASE=0xFF1A0000
CONFIG_DEBUG_UART_CLOCK=24000000
CONFIG_SYS_LOAD_ADDR=0x800800
@@ -20,13 +16,7 @@
CONFIG_DISPLAY_BOARDINFO_LATE=y
CONFIG_SPL_MAX_SIZE=0x2e000
CONFIG_SPL_PAD_TO=0x7f8000
-CONFIG_SPL_HAS_BSS_LINKER_SECTION=y
-CONFIG_SPL_BSS_START_ADDR=0x400000
-CONFIG_SPL_BSS_MAX_SIZE=0x2000
# CONFIG_SPL_RAW_IMAGE_SUPPORT is not set
-# CONFIG_SPL_SHARES_INIT_SP_ADDR is not set
-CONFIG_SPL_STACK_R=y
-CONFIG_SPL_STACK_R_MALLOC_SIMPLE_LEN=0x10000
CONFIG_SPL_ATF_NO_PLATFORM_PARAM=y
CONFIG_TPL=y
CONFIG_SYS_PROMPT="kedge# "
@@ -43,7 +33,6 @@
CONFIG_NET_RANDOM_ETHADDR=y
CONFIG_ROCKCHIP_GPIO=y
CONFIG_SYS_I2C_ROCKCHIP=y
-CONFIG_MISC=y
CONFIG_MMC_DW=y
CONFIG_MMC_DW_ROCKCHIP=y
CONFIG_MMC_SDHCI=y
diff --git a/configs/khadas-edge-rk3399_defconfig b/configs/khadas-edge-rk3399_defconfig
index 9de8a53..3fe5542 100644
--- a/configs/khadas-edge-rk3399_defconfig
+++ b/configs/khadas-edge-rk3399_defconfig
@@ -2,15 +2,11 @@
CONFIG_SKIP_LOWLEVEL_INIT=y
CONFIG_COUNTER_FREQUENCY=24000000
CONFIG_ARCH_ROCKCHIP=y
-CONFIG_TEXT_BASE=0x00200000
CONFIG_NR_DRAM_BANKS=1
-CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y
-CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x300000
CONFIG_ENV_OFFSET=0x3F8000
CONFIG_DEFAULT_DEVICE_TREE="rk3399-khadas-edge"
CONFIG_ROCKCHIP_RK3399=y
CONFIG_TARGET_EVB_RK3399=y
-CONFIG_SPL_STACK=0x400000
CONFIG_DEBUG_UART_BASE=0xFF1A0000
CONFIG_DEBUG_UART_CLOCK=24000000
CONFIG_SYS_LOAD_ADDR=0x800800
@@ -20,13 +16,7 @@
CONFIG_DISPLAY_BOARDINFO_LATE=y
CONFIG_SPL_MAX_SIZE=0x2e000
CONFIG_SPL_PAD_TO=0x7f8000
-CONFIG_SPL_HAS_BSS_LINKER_SECTION=y
-CONFIG_SPL_BSS_START_ADDR=0x400000
-CONFIG_SPL_BSS_MAX_SIZE=0x2000
# CONFIG_SPL_RAW_IMAGE_SUPPORT is not set
-# CONFIG_SPL_SHARES_INIT_SP_ADDR is not set
-CONFIG_SPL_STACK_R=y
-CONFIG_SPL_STACK_R_MALLOC_SIMPLE_LEN=0x10000
CONFIG_SPL_ATF_NO_PLATFORM_PARAM=y
CONFIG_TPL=y
CONFIG_SYS_PROMPT="kedge# "
@@ -42,7 +32,6 @@
CONFIG_SYS_RELOC_GD_ENV_ADDR=y
CONFIG_ROCKCHIP_GPIO=y
CONFIG_SYS_I2C_ROCKCHIP=y
-CONFIG_MISC=y
CONFIG_MMC_DW=y
CONFIG_MMC_DW_ROCKCHIP=y
CONFIG_MMC_SDHCI=y
diff --git a/configs/khadas-edge-v-rk3399_defconfig b/configs/khadas-edge-v-rk3399_defconfig
index f31b8ec..4b41454 100644
--- a/configs/khadas-edge-v-rk3399_defconfig
+++ b/configs/khadas-edge-v-rk3399_defconfig
@@ -2,15 +2,11 @@
CONFIG_SKIP_LOWLEVEL_INIT=y
CONFIG_COUNTER_FREQUENCY=24000000
CONFIG_ARCH_ROCKCHIP=y
-CONFIG_TEXT_BASE=0x00200000
CONFIG_NR_DRAM_BANKS=1
-CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y
-CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x300000
CONFIG_ENV_OFFSET=0x3F8000
CONFIG_DEFAULT_DEVICE_TREE="rk3399-khadas-edge-v"
CONFIG_ROCKCHIP_RK3399=y
CONFIG_TARGET_EVB_RK3399=y
-CONFIG_SPL_STACK=0x400000
CONFIG_DEBUG_UART_BASE=0xFF1A0000
CONFIG_DEBUG_UART_CLOCK=24000000
CONFIG_SYS_LOAD_ADDR=0x800800
@@ -20,13 +16,7 @@
CONFIG_DISPLAY_BOARDINFO_LATE=y
CONFIG_SPL_MAX_SIZE=0x2e000
CONFIG_SPL_PAD_TO=0x7f8000
-CONFIG_SPL_HAS_BSS_LINKER_SECTION=y
-CONFIG_SPL_BSS_START_ADDR=0x400000
-CONFIG_SPL_BSS_MAX_SIZE=0x2000
# CONFIG_SPL_RAW_IMAGE_SUPPORT is not set
-# CONFIG_SPL_SHARES_INIT_SP_ADDR is not set
-CONFIG_SPL_STACK_R=y
-CONFIG_SPL_STACK_R_MALLOC_SIMPLE_LEN=0x10000
CONFIG_SPL_ATF_NO_PLATFORM_PARAM=y
CONFIG_TPL=y
CONFIG_SYS_PROMPT="kedge# "
@@ -43,7 +33,6 @@
CONFIG_NET_RANDOM_ETHADDR=y
CONFIG_ROCKCHIP_GPIO=y
CONFIG_SYS_I2C_ROCKCHIP=y
-CONFIG_MISC=y
CONFIG_MMC_DW=y
CONFIG_MMC_DW_ROCKCHIP=y
CONFIG_MMC_SDHCI=y
diff --git a/configs/khadas-vim2_defconfig b/configs/khadas-vim2_defconfig
index 59ef337..50f8b30 100644
--- a/configs/khadas-vim2_defconfig
+++ b/configs/khadas-vim2_defconfig
@@ -6,7 +6,7 @@
CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x20000000
CONFIG_ENV_SIZE=0x2000
CONFIG_DM_GPIO=y
-CONFIG_DEFAULT_DEVICE_TREE="meson-gxm-khadas-vim2"
+CONFIG_DEFAULT_DEVICE_TREE="amlogic/meson-gxm-khadas-vim2"
CONFIG_OF_LIBFDT_OVERLAY=y
CONFIG_DM_RESET=y
CONFIG_MESON_GXM=y
diff --git a/configs/khadas-vim3_android_ab_defconfig b/configs/khadas-vim3_android_ab_defconfig
index ee62fe3..37b8d6a 100644
--- a/configs/khadas-vim3_android_ab_defconfig
+++ b/configs/khadas-vim3_android_ab_defconfig
@@ -10,7 +10,7 @@
CONFIG_ENV_SIZE=0x10000
CONFIG_ENV_OFFSET=0x0
CONFIG_DM_GPIO=y
-CONFIG_DEFAULT_DEVICE_TREE="meson-g12b-a311d-khadas-vim3"
+CONFIG_DEFAULT_DEVICE_TREE="amlogic/meson-g12b-a311d-khadas-vim3"
CONFIG_OF_LIBFDT_OVERLAY=y
CONFIG_DM_RESET=y
CONFIG_MESON_G12A=y
diff --git a/configs/khadas-vim3_android_defconfig b/configs/khadas-vim3_android_defconfig
index cecbe50..55d59dd 100644
--- a/configs/khadas-vim3_android_defconfig
+++ b/configs/khadas-vim3_android_defconfig
@@ -10,7 +10,7 @@
CONFIG_ENV_SIZE=0x10000
CONFIG_ENV_OFFSET=0x0
CONFIG_DM_GPIO=y
-CONFIG_DEFAULT_DEVICE_TREE="meson-g12b-a311d-khadas-vim3"
+CONFIG_DEFAULT_DEVICE_TREE="amlogic/meson-g12b-a311d-khadas-vim3"
CONFIG_OF_LIBFDT_OVERLAY=y
CONFIG_DM_RESET=y
CONFIG_MESON_G12A=y
diff --git a/configs/khadas-vim3_defconfig b/configs/khadas-vim3_defconfig
index 5df4b92..32579b8 100644
--- a/configs/khadas-vim3_defconfig
+++ b/configs/khadas-vim3_defconfig
@@ -7,7 +7,7 @@
CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x20000000
CONFIG_ENV_SIZE=0x2000
CONFIG_DM_GPIO=y
-CONFIG_DEFAULT_DEVICE_TREE="meson-g12b-a311d-khadas-vim3"
+CONFIG_DEFAULT_DEVICE_TREE="amlogic/meson-g12b-a311d-khadas-vim3"
CONFIG_OF_LIBFDT_OVERLAY=y
CONFIG_DM_RESET=y
CONFIG_MESON_G12A=y
diff --git a/configs/khadas-vim3l_android_ab_defconfig b/configs/khadas-vim3l_android_ab_defconfig
index ec4e0dc..95e7027 100644
--- a/configs/khadas-vim3l_android_ab_defconfig
+++ b/configs/khadas-vim3l_android_ab_defconfig
@@ -10,7 +10,7 @@
CONFIG_ENV_SIZE=0x10000
CONFIG_ENV_OFFSET=0x0
CONFIG_DM_GPIO=y
-CONFIG_DEFAULT_DEVICE_TREE="meson-sm1-khadas-vim3l"
+CONFIG_DEFAULT_DEVICE_TREE="amlogic/meson-sm1-khadas-vim3l"
CONFIG_OF_LIBFDT_OVERLAY=y
CONFIG_DM_RESET=y
CONFIG_MESON_G12A=y
diff --git a/configs/khadas-vim3l_android_defconfig b/configs/khadas-vim3l_android_defconfig
index 206f8de..6372d11 100644
--- a/configs/khadas-vim3l_android_defconfig
+++ b/configs/khadas-vim3l_android_defconfig
@@ -10,7 +10,7 @@
CONFIG_ENV_SIZE=0x10000
CONFIG_ENV_OFFSET=0x0
CONFIG_DM_GPIO=y
-CONFIG_DEFAULT_DEVICE_TREE="meson-sm1-khadas-vim3l"
+CONFIG_DEFAULT_DEVICE_TREE="amlogic/meson-sm1-khadas-vim3l"
CONFIG_OF_LIBFDT_OVERLAY=y
CONFIG_DM_RESET=y
CONFIG_MESON_G12A=y
diff --git a/configs/khadas-vim3l_defconfig b/configs/khadas-vim3l_defconfig
index de8fdd8..b9f4690 100644
--- a/configs/khadas-vim3l_defconfig
+++ b/configs/khadas-vim3l_defconfig
@@ -7,7 +7,7 @@
CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x20000000
CONFIG_ENV_SIZE=0x2000
CONFIG_DM_GPIO=y
-CONFIG_DEFAULT_DEVICE_TREE="meson-sm1-khadas-vim3l"
+CONFIG_DEFAULT_DEVICE_TREE="amlogic/meson-sm1-khadas-vim3l"
CONFIG_OF_LIBFDT_OVERLAY=y
CONFIG_DM_RESET=y
CONFIG_MESON_G12A=y
diff --git a/configs/khadas-vim_defconfig b/configs/khadas-vim_defconfig
index 5ed7c1a..ac00e89 100644
--- a/configs/khadas-vim_defconfig
+++ b/configs/khadas-vim_defconfig
@@ -6,7 +6,7 @@
CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x20000000
CONFIG_ENV_SIZE=0x2000
CONFIG_DM_GPIO=y
-CONFIG_DEFAULT_DEVICE_TREE="meson-gxl-s905x-khadas-vim"
+CONFIG_DEFAULT_DEVICE_TREE="amlogic/meson-gxl-s905x-khadas-vim"
CONFIG_OF_LIBFDT_OVERLAY=y
CONFIG_DM_RESET=y
CONFIG_MESON_GXL=y
diff --git a/configs/leez-rk3399_defconfig b/configs/leez-rk3399_defconfig
index 76dd919..e508834 100644
--- a/configs/leez-rk3399_defconfig
+++ b/configs/leez-rk3399_defconfig
@@ -2,15 +2,11 @@
CONFIG_SKIP_LOWLEVEL_INIT=y
CONFIG_COUNTER_FREQUENCY=24000000
CONFIG_ARCH_ROCKCHIP=y
-CONFIG_TEXT_BASE=0x00200000
CONFIG_NR_DRAM_BANKS=1
-CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y
-CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x300000
CONFIG_ENV_OFFSET=0x3F8000
CONFIG_DEFAULT_DEVICE_TREE="rk3399-leez-p710"
CONFIG_ROCKCHIP_RK3399=y
CONFIG_TARGET_EVB_RK3399=y
-CONFIG_SPL_STACK=0x400000
CONFIG_DEBUG_UART_BASE=0xFF1A0000
CONFIG_DEBUG_UART_CLOCK=24000000
CONFIG_SYS_LOAD_ADDR=0x800800
@@ -19,12 +15,6 @@
CONFIG_DISPLAY_BOARDINFO_LATE=y
CONFIG_SPL_MAX_SIZE=0x2e000
CONFIG_SPL_PAD_TO=0x7f8000
-CONFIG_SPL_HAS_BSS_LINKER_SECTION=y
-CONFIG_SPL_BSS_START_ADDR=0x400000
-CONFIG_SPL_BSS_MAX_SIZE=0x2000
-# CONFIG_SPL_SHARES_INIT_SP_ADDR is not set
-CONFIG_SPL_STACK_R=y
-CONFIG_SPL_STACK_R_MALLOC_SIMPLE_LEN=0x10000
CONFIG_SPL_ATF_NO_PLATFORM_PARAM=y
CONFIG_TPL=y
CONFIG_CMD_BOOTZ=y
@@ -39,7 +29,6 @@
CONFIG_SYS_RELOC_GD_ENV_ADDR=y
CONFIG_ROCKCHIP_GPIO=y
CONFIG_SYS_I2C_ROCKCHIP=y
-CONFIG_MISC=y
CONFIG_MMC_DW=y
CONFIG_MMC_DW_ROCKCHIP=y
CONFIG_MMC_SDHCI=y
diff --git a/configs/libretech-ac_defconfig b/configs/libretech-ac_defconfig
index f0ab195..6ad0457 100644
--- a/configs/libretech-ac_defconfig
+++ b/configs/libretech-ac_defconfig
@@ -9,7 +9,7 @@
CONFIG_ENV_OFFSET=0xFFFF0000
CONFIG_ENV_SECT_SIZE=0x10000
CONFIG_DM_GPIO=y
-CONFIG_DEFAULT_DEVICE_TREE="meson-gxl-s805x-libretech-ac"
+CONFIG_DEFAULT_DEVICE_TREE="amlogic/meson-gxl-s805x-libretech-ac"
CONFIG_OF_LIBFDT_OVERLAY=y
CONFIG_DM_RESET=y
CONFIG_MESON_GXL=y
diff --git a/configs/libretech-cc_defconfig b/configs/libretech-cc_defconfig
index bb1a37a..beb919c 100644
--- a/configs/libretech-cc_defconfig
+++ b/configs/libretech-cc_defconfig
@@ -6,7 +6,7 @@
CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x20000000
CONFIG_ENV_SIZE=0x2000
CONFIG_DM_GPIO=y
-CONFIG_DEFAULT_DEVICE_TREE="meson-gxl-s905x-libretech-cc"
+CONFIG_DEFAULT_DEVICE_TREE="amlogic/meson-gxl-s905x-libretech-cc"
CONFIG_OF_LIBFDT_OVERLAY=y
CONFIG_DM_RESET=y
CONFIG_MESON_GXL=y
diff --git a/configs/libretech-cc_v2_defconfig b/configs/libretech-cc_v2_defconfig
index 8949e24..784a269 100644
--- a/configs/libretech-cc_v2_defconfig
+++ b/configs/libretech-cc_v2_defconfig
@@ -8,7 +8,7 @@
CONFIG_ENV_OFFSET=0xFFFF0000
CONFIG_ENV_SECT_SIZE=0x10000
CONFIG_DM_GPIO=y
-CONFIG_DEFAULT_DEVICE_TREE="meson-gxl-s905x-libretech-cc-v2"
+CONFIG_DEFAULT_DEVICE_TREE="amlogic/meson-gxl-s905x-libretech-cc-v2"
CONFIG_OF_LIBFDT_OVERLAY=y
CONFIG_DM_RESET=y
CONFIG_MESON_GXL=y
diff --git a/configs/libretech-s905d-pc_defconfig b/configs/libretech-s905d-pc_defconfig
index a5dc311..0adc0af 100644
--- a/configs/libretech-s905d-pc_defconfig
+++ b/configs/libretech-s905d-pc_defconfig
@@ -9,7 +9,7 @@
CONFIG_ENV_OFFSET=0xFFFF0000
CONFIG_ENV_SECT_SIZE=0x10000
CONFIG_DM_GPIO=y
-CONFIG_DEFAULT_DEVICE_TREE="meson-gxl-s905d-libretech-pc"
+CONFIG_DEFAULT_DEVICE_TREE="amlogic/meson-gxl-s905d-libretech-pc"
CONFIG_OF_LIBFDT_OVERLAY=y
CONFIG_DM_RESET=y
CONFIG_MESON_GXL=y
diff --git a/configs/libretech-s912-pc_defconfig b/configs/libretech-s912-pc_defconfig
index 68f462e..cbce0cf 100644
--- a/configs/libretech-s912-pc_defconfig
+++ b/configs/libretech-s912-pc_defconfig
@@ -8,7 +8,7 @@
CONFIG_ENV_OFFSET=0xFFFF0000
CONFIG_ENV_SECT_SIZE=0x10000
CONFIG_DM_GPIO=y
-CONFIG_DEFAULT_DEVICE_TREE="meson-gxm-s912-libretech-pc"
+CONFIG_DEFAULT_DEVICE_TREE="amlogic/meson-gxm-s912-libretech-pc"
CONFIG_OF_LIBFDT_OVERLAY=y
CONFIG_DM_RESET=y
CONFIG_MESON_GXM=y
diff --git a/configs/lschlv2_defconfig b/configs/lschlv2_defconfig
index 99bdbc1..ad06007 100644
--- a/configs/lschlv2_defconfig
+++ b/configs/lschlv2_defconfig
@@ -15,7 +15,7 @@
CONFIG_ENV_OFFSET=0x70000
CONFIG_ENV_SECT_SIZE=0x10000
CONFIG_DM_GPIO=y
-CONFIG_DEFAULT_DEVICE_TREE="kirkwood-lschlv2"
+CONFIG_DEFAULT_DEVICE_TREE="marvell/kirkwood-lschlv2"
CONFIG_IDENT_STRING=" LS-CHLv2"
CONFIG_SYS_LOAD_ADDR=0x800000
CONFIG_HAS_BOARD_SIZE_LIMIT=y
diff --git a/configs/lsxhl_defconfig b/configs/lsxhl_defconfig
index bb0a5dd..b2d9f0c 100644
--- a/configs/lsxhl_defconfig
+++ b/configs/lsxhl_defconfig
@@ -16,7 +16,7 @@
CONFIG_ENV_OFFSET=0x70000
CONFIG_ENV_SECT_SIZE=0x10000
CONFIG_DM_GPIO=y
-CONFIG_DEFAULT_DEVICE_TREE="kirkwood-lsxhl"
+CONFIG_DEFAULT_DEVICE_TREE="marvell/kirkwood-lsxhl"
CONFIG_IDENT_STRING=" LS-XHL"
CONFIG_SYS_LOAD_ADDR=0x800000
CONFIG_HAS_BOARD_SIZE_LIMIT=y
diff --git a/configs/lubancat-2-rk3568_defconfig b/configs/lubancat-2-rk3568_defconfig
index 80ae6ec..1c50a0c 100644
--- a/configs/lubancat-2-rk3568_defconfig
+++ b/configs/lubancat-2-rk3568_defconfig
@@ -2,18 +2,10 @@
CONFIG_SKIP_LOWLEVEL_INIT=y
CONFIG_COUNTER_FREQUENCY=24000000
CONFIG_ARCH_ROCKCHIP=y
-CONFIG_TEXT_BASE=0x00a00000
-CONFIG_SPL_LIBCOMMON_SUPPORT=y
-CONFIG_SPL_LIBGENERIC_SUPPORT=y
CONFIG_NR_DRAM_BANKS=2
-CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y
-CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0xc00000
CONFIG_DEFAULT_DEVICE_TREE="rk3568-lubancat-2"
CONFIG_ROCKCHIP_RK3568=y
-CONFIG_SPL_ROCKCHIP_COMMON_BOARD=y
CONFIG_SPL_SERIAL=y
-CONFIG_SPL_STACK_R_ADDR=0x600000
-CONFIG_SPL_STACK=0x400000
CONFIG_DEBUG_UART_BASE=0xFE660000
CONFIG_DEBUG_UART_CLOCK=24000000
CONFIG_SYS_LOAD_ADDR=0xc00800
@@ -28,12 +20,7 @@
CONFIG_DISPLAY_BOARDINFO_LATE=y
CONFIG_SPL_MAX_SIZE=0x40000
CONFIG_SPL_PAD_TO=0x7f8000
-CONFIG_SPL_HAS_BSS_LINKER_SECTION=y
-CONFIG_SPL_BSS_START_ADDR=0x4000000
-CONFIG_SPL_BSS_MAX_SIZE=0x4000
# CONFIG_SPL_RAW_IMAGE_SUPPORT is not set
-# CONFIG_SPL_SHARES_INIT_SP_ADDR is not set
-CONFIG_SPL_STACK_R=y
CONFIG_SPL_ATF=y
CONFIG_CMD_GPIO=y
CONFIG_CMD_GPT=y
diff --git a/configs/milkv_duo_defconfig b/configs/milkv_duo_defconfig
index 548adf1..e8413d7 100644
--- a/configs/milkv_duo_defconfig
+++ b/configs/milkv_duo_defconfig
@@ -17,6 +17,16 @@
CONFIG_SYS_PBSIZE=544
CONFIG_HUSH_PARSER=y
CONFIG_SYS_PROMPT="milkv_duo# "
+CONFIG_CMD_MMC=y
+CONFIG_CMD_PART=y
+CONFIG_CMD_FAT=y
+CONFIG_CMD_FS_GENERIC=y
CONFIG_ENV_OVERWRITE=y
+CONFIG_MMC=y
+CONFIG_MMC_IO_VOLTAGE=y
+CONFIG_MMC_UHS_SUPPORT=y
+CONFIG_MMC_SDHCI=y
+CONFIG_MMC_SDHCI_ADMA=y
+CONFIG_MMC_SDHCI_CV1800B=y
CONFIG_SYS_NS16550=y
CONFIG_SYS_NS16550_MEM32=y
diff --git a/configs/mx6cuboxi_defconfig b/configs/mx6cuboxi_defconfig
index 66d4aae..e3aba71 100644
--- a/configs/mx6cuboxi_defconfig
+++ b/configs/mx6cuboxi_defconfig
@@ -28,6 +28,7 @@
CONFIG_USE_PREBOOT=y
CONFIG_PREBOOT="if hdmidet; then usb start; setenv stdin serial,usbkbd; setenv stdout serial,vidconsole; setenv stderr serial,vidconsole; else setenv stdin serial; setenv stdout serial; setenv stderr serial; fi;"
CONFIG_SYS_PBSIZE=532
+# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_BOARD_EARLY_INIT_F=y
CONFIG_SPL_SYS_MALLOC=y
CONFIG_SPL_FS_EXT4=y
@@ -71,6 +72,8 @@
CONFIG_DM_REGULATOR_FIXED=y
CONFIG_DM_SERIAL=y
CONFIG_MXC_UART=y
+CONFIG_SYSRESET=y
+CONFIG_SYSRESET_WATCHDOG=y
CONFIG_DM_THERMAL=y
CONFIG_IMX_THERMAL=y
CONFIG_USB=y
@@ -89,3 +92,4 @@
CONFIG_SPLASH_SCREEN=y
CONFIG_SPLASH_SCREEN_ALIGN=y
CONFIG_BMP_16BPP=y
+CONFIG_IMX_WATCHDOG=y
diff --git a/configs/mx6memcal_defconfig b/configs/mx6memcal_defconfig
index 7f11e6f..6c5481c 100644
--- a/configs/mx6memcal_defconfig
+++ b/configs/mx6memcal_defconfig
@@ -14,6 +14,7 @@
CONFIG_SPL=y
CONFIG_SYS_MEMTEST_START=0x10000000
CONFIG_SYS_MEMTEST_END=0x20000000
+# CONFIG_BOOTM is not set
CONFIG_SUPPORT_RAW_INITRD=y
CONFIG_SYS_PBSIZE=528
CONFIG_SPL_SYS_MALLOC=y
@@ -21,7 +22,6 @@
CONFIG_HUSH_PARSER=y
CONFIG_SYS_MAXARGS=32
# CONFIG_CMD_BOOTD is not set
-# CONFIG_CMD_BOOTM is not set
# CONFIG_CMD_ELF is not set
# CONFIG_CMD_IMI is not set
# CONFIG_CMD_XIMG is not set
diff --git a/configs/nanopc-t4-rk3399_defconfig b/configs/nanopc-t4-rk3399_defconfig
index c18e7b1..cdfacb6 100644
--- a/configs/nanopc-t4-rk3399_defconfig
+++ b/configs/nanopc-t4-rk3399_defconfig
@@ -2,16 +2,12 @@
CONFIG_SKIP_LOWLEVEL_INIT=y
CONFIG_COUNTER_FREQUENCY=24000000
CONFIG_ARCH_ROCKCHIP=y
-CONFIG_TEXT_BASE=0x00200000
CONFIG_NR_DRAM_BANKS=1
-CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y
-CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x300000
CONFIG_ENV_OFFSET=0x3F8000
CONFIG_DEFAULT_DEVICE_TREE="rk3399-nanopc-t4"
CONFIG_DM_RESET=y
CONFIG_ROCKCHIP_RK3399=y
CONFIG_TARGET_EVB_RK3399=y
-CONFIG_SPL_STACK=0x400000
CONFIG_DEBUG_UART_BASE=0xFF1A0000
CONFIG_DEBUG_UART_CLOCK=24000000
CONFIG_SYS_LOAD_ADDR=0x800800
@@ -21,13 +17,7 @@
CONFIG_DISPLAY_BOARDINFO_LATE=y
CONFIG_SPL_MAX_SIZE=0x2e000
CONFIG_SPL_PAD_TO=0x7f8000
-CONFIG_SPL_HAS_BSS_LINKER_SECTION=y
-CONFIG_SPL_BSS_START_ADDR=0x400000
-CONFIG_SPL_BSS_MAX_SIZE=0x2000
# CONFIG_SPL_RAW_IMAGE_SUPPORT is not set
-# CONFIG_SPL_SHARES_INIT_SP_ADDR is not set
-CONFIG_SPL_STACK_R=y
-CONFIG_SPL_STACK_R_MALLOC_SIMPLE_LEN=0x10000
CONFIG_SPL_ATF_NO_PLATFORM_PARAM=y
CONFIG_TPL=y
CONFIG_CMD_BOOTZ=y
@@ -43,7 +33,6 @@
CONFIG_SYS_RELOC_GD_ENV_ADDR=y
CONFIG_ROCKCHIP_GPIO=y
CONFIG_SYS_I2C_ROCKCHIP=y
-CONFIG_MISC=y
CONFIG_MMC_DW=y
CONFIG_MMC_DW_ROCKCHIP=y
CONFIG_MMC_SDHCI=y
diff --git a/configs/nanopc-t6-rk3588_defconfig b/configs/nanopc-t6-rk3588_defconfig
index 7609932..5c7bc0b 100644
--- a/configs/nanopc-t6-rk3588_defconfig
+++ b/configs/nanopc-t6-rk3588_defconfig
@@ -3,22 +3,14 @@
CONFIG_SYS_HAS_NONCACHED_MEMORY=y
CONFIG_COUNTER_FREQUENCY=24000000
CONFIG_ARCH_ROCKCHIP=y
-CONFIG_TEXT_BASE=0x00a00000
-CONFIG_SPL_LIBCOMMON_SUPPORT=y
-CONFIG_SPL_LIBGENERIC_SUPPORT=y
CONFIG_NR_DRAM_BANKS=2
-CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y
-CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0xc00000
CONFIG_SF_DEFAULT_SPEED=24000000
CONFIG_SF_DEFAULT_MODE=0x2000
CONFIG_DEFAULT_DEVICE_TREE="rk3588-nanopc-t6"
CONFIG_ROCKCHIP_RK3588=y
-CONFIG_SPL_ROCKCHIP_COMMON_BOARD=y
CONFIG_ROCKCHIP_SPI_IMAGE=y
CONFIG_SPL_SERIAL=y
-CONFIG_SPL_STACK_R_ADDR=0x600000
CONFIG_TARGET_NANOPCT6_RK3588=y
-CONFIG_SPL_STACK=0x400000
CONFIG_DEBUG_UART_BASE=0xFEB50000
CONFIG_DEBUG_UART_CLOCK=24000000
CONFIG_SPL_SPI_FLASH_SUPPORT=y
@@ -37,12 +29,7 @@
CONFIG_DISPLAY_BOARDINFO_LATE=y
CONFIG_SPL_MAX_SIZE=0x40000
CONFIG_SPL_PAD_TO=0x7f8000
-CONFIG_SPL_HAS_BSS_LINKER_SECTION=y
-CONFIG_SPL_BSS_START_ADDR=0x4000000
-CONFIG_SPL_BSS_MAX_SIZE=0x4000
# CONFIG_SPL_RAW_IMAGE_SUPPORT is not set
-# CONFIG_SPL_SHARES_INIT_SP_ADDR is not set
-CONFIG_SPL_STACK_R=y
CONFIG_SPL_SPI_LOAD=y
CONFIG_SYS_SPI_U_BOOT_OFFS=0x60000
CONFIG_SPL_ATF=y
diff --git a/configs/nanopi-m4-2gb-rk3399_defconfig b/configs/nanopi-m4-2gb-rk3399_defconfig
index e3bdbcc..51596f5 100644
--- a/configs/nanopi-m4-2gb-rk3399_defconfig
+++ b/configs/nanopi-m4-2gb-rk3399_defconfig
@@ -2,15 +2,11 @@
CONFIG_SKIP_LOWLEVEL_INIT=y
CONFIG_COUNTER_FREQUENCY=24000000
CONFIG_ARCH_ROCKCHIP=y
-CONFIG_TEXT_BASE=0x00200000
CONFIG_NR_DRAM_BANKS=1
-CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y
-CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x300000
CONFIG_ENV_OFFSET=0x3F8000
CONFIG_DEFAULT_DEVICE_TREE="rk3399-nanopi-m4-2gb"
CONFIG_ROCKCHIP_RK3399=y
CONFIG_TARGET_EVB_RK3399=y
-CONFIG_SPL_STACK=0x400000
CONFIG_DEBUG_UART_BASE=0xFF1A0000
CONFIG_DEBUG_UART_CLOCK=24000000
CONFIG_SYS_LOAD_ADDR=0x800800
@@ -19,13 +15,7 @@
CONFIG_DISPLAY_BOARDINFO_LATE=y
CONFIG_SPL_MAX_SIZE=0x2e000
CONFIG_SPL_PAD_TO=0x7f8000
-CONFIG_SPL_HAS_BSS_LINKER_SECTION=y
-CONFIG_SPL_BSS_START_ADDR=0x400000
-CONFIG_SPL_BSS_MAX_SIZE=0x2000
# CONFIG_SPL_RAW_IMAGE_SUPPORT is not set
-# CONFIG_SPL_SHARES_INIT_SP_ADDR is not set
-CONFIG_SPL_STACK_R=y
-CONFIG_SPL_STACK_R_MALLOC_SIMPLE_LEN=0x10000
CONFIG_SPL_ATF_NO_PLATFORM_PARAM=y
CONFIG_TPL=y
CONFIG_CMD_BOOTZ=y
@@ -40,7 +30,6 @@
CONFIG_SYS_RELOC_GD_ENV_ADDR=y
CONFIG_ROCKCHIP_GPIO=y
CONFIG_SYS_I2C_ROCKCHIP=y
-CONFIG_MISC=y
CONFIG_MMC_DW=y
CONFIG_MMC_DW_ROCKCHIP=y
CONFIG_MMC_SDHCI=y
diff --git a/configs/nanopi-m4-rk3399_defconfig b/configs/nanopi-m4-rk3399_defconfig
index e51e51c..2af84fb 100644
--- a/configs/nanopi-m4-rk3399_defconfig
+++ b/configs/nanopi-m4-rk3399_defconfig
@@ -2,15 +2,11 @@
CONFIG_SKIP_LOWLEVEL_INIT=y
CONFIG_COUNTER_FREQUENCY=24000000
CONFIG_ARCH_ROCKCHIP=y
-CONFIG_TEXT_BASE=0x00200000
CONFIG_NR_DRAM_BANKS=1
-CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y
-CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x300000
CONFIG_ENV_OFFSET=0x3F8000
CONFIG_DEFAULT_DEVICE_TREE="rk3399-nanopi-m4"
CONFIG_ROCKCHIP_RK3399=y
CONFIG_TARGET_EVB_RK3399=y
-CONFIG_SPL_STACK=0x400000
CONFIG_DEBUG_UART_BASE=0xFF1A0000
CONFIG_DEBUG_UART_CLOCK=24000000
CONFIG_SYS_LOAD_ADDR=0x800800
@@ -19,13 +15,7 @@
CONFIG_DISPLAY_BOARDINFO_LATE=y
CONFIG_SPL_MAX_SIZE=0x2e000
CONFIG_SPL_PAD_TO=0x7f8000
-CONFIG_SPL_HAS_BSS_LINKER_SECTION=y
-CONFIG_SPL_BSS_START_ADDR=0x400000
-CONFIG_SPL_BSS_MAX_SIZE=0x2000
# CONFIG_SPL_RAW_IMAGE_SUPPORT is not set
-# CONFIG_SPL_SHARES_INIT_SP_ADDR is not set
-CONFIG_SPL_STACK_R=y
-CONFIG_SPL_STACK_R_MALLOC_SIMPLE_LEN=0x10000
CONFIG_SPL_ATF_NO_PLATFORM_PARAM=y
CONFIG_TPL=y
CONFIG_CMD_BOOTZ=y
@@ -40,7 +30,6 @@
CONFIG_SYS_RELOC_GD_ENV_ADDR=y
CONFIG_ROCKCHIP_GPIO=y
CONFIG_SYS_I2C_ROCKCHIP=y
-CONFIG_MISC=y
CONFIG_MMC_DW=y
CONFIG_MMC_DW_ROCKCHIP=y
CONFIG_MMC_SDHCI=y
diff --git a/configs/nanopi-m4b-rk3399_defconfig b/configs/nanopi-m4b-rk3399_defconfig
index ca57c7f..1b76f98 100644
--- a/configs/nanopi-m4b-rk3399_defconfig
+++ b/configs/nanopi-m4b-rk3399_defconfig
@@ -2,15 +2,11 @@
CONFIG_SKIP_LOWLEVEL_INIT=y
CONFIG_COUNTER_FREQUENCY=24000000
CONFIG_ARCH_ROCKCHIP=y
-CONFIG_TEXT_BASE=0x00200000
CONFIG_NR_DRAM_BANKS=1
-CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y
-CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x300000
CONFIG_ENV_OFFSET=0x3F8000
CONFIG_DEFAULT_DEVICE_TREE="rk3399-nanopi-m4b"
CONFIG_ROCKCHIP_RK3399=y
CONFIG_TARGET_EVB_RK3399=y
-CONFIG_SPL_STACK=0x400000
CONFIG_DEBUG_UART_BASE=0xFF1A0000
CONFIG_DEBUG_UART_CLOCK=24000000
CONFIG_SYS_LOAD_ADDR=0x800800
@@ -19,13 +15,7 @@
CONFIG_DISPLAY_BOARDINFO_LATE=y
CONFIG_SPL_MAX_SIZE=0x2e000
CONFIG_SPL_PAD_TO=0x7f8000
-CONFIG_SPL_HAS_BSS_LINKER_SECTION=y
-CONFIG_SPL_BSS_START_ADDR=0x400000
-CONFIG_SPL_BSS_MAX_SIZE=0x2000
# CONFIG_SPL_RAW_IMAGE_SUPPORT is not set
-# CONFIG_SPL_SHARES_INIT_SP_ADDR is not set
-CONFIG_SPL_STACK_R=y
-CONFIG_SPL_STACK_R_MALLOC_SIMPLE_LEN=0x10000
CONFIG_SPL_ATF_NO_PLATFORM_PARAM=y
CONFIG_TPL=y
CONFIG_CMD_BOOTZ=y
@@ -40,7 +30,6 @@
CONFIG_SYS_RELOC_GD_ENV_ADDR=y
CONFIG_ROCKCHIP_GPIO=y
CONFIG_SYS_I2C_ROCKCHIP=y
-CONFIG_MISC=y
CONFIG_MMC_DW=y
CONFIG_MMC_DW_ROCKCHIP=y
CONFIG_MMC_SDHCI=y
diff --git a/configs/nanopi-neo4-rk3399_defconfig b/configs/nanopi-neo4-rk3399_defconfig
index 02e7f4e..c176c5a 100644
--- a/configs/nanopi-neo4-rk3399_defconfig
+++ b/configs/nanopi-neo4-rk3399_defconfig
@@ -2,15 +2,11 @@
CONFIG_SKIP_LOWLEVEL_INIT=y
CONFIG_COUNTER_FREQUENCY=24000000
CONFIG_ARCH_ROCKCHIP=y
-CONFIG_TEXT_BASE=0x00200000
CONFIG_NR_DRAM_BANKS=1
-CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y
-CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x300000
CONFIG_ENV_OFFSET=0x3F8000
CONFIG_DEFAULT_DEVICE_TREE="rk3399-nanopi-neo4"
CONFIG_ROCKCHIP_RK3399=y
CONFIG_TARGET_EVB_RK3399=y
-CONFIG_SPL_STACK=0x400000
CONFIG_DEBUG_UART_BASE=0xFF1A0000
CONFIG_DEBUG_UART_CLOCK=24000000
CONFIG_SYS_LOAD_ADDR=0x800800
@@ -19,13 +15,7 @@
CONFIG_DISPLAY_BOARDINFO_LATE=y
CONFIG_SPL_MAX_SIZE=0x2e000
CONFIG_SPL_PAD_TO=0x7f8000
-CONFIG_SPL_HAS_BSS_LINKER_SECTION=y
-CONFIG_SPL_BSS_START_ADDR=0x400000
-CONFIG_SPL_BSS_MAX_SIZE=0x2000
# CONFIG_SPL_RAW_IMAGE_SUPPORT is not set
-# CONFIG_SPL_SHARES_INIT_SP_ADDR is not set
-CONFIG_SPL_STACK_R=y
-CONFIG_SPL_STACK_R_MALLOC_SIMPLE_LEN=0x10000
CONFIG_SPL_ATF_NO_PLATFORM_PARAM=y
CONFIG_TPL=y
CONFIG_CMD_BOOTZ=y
@@ -40,7 +30,6 @@
CONFIG_SYS_RELOC_GD_ENV_ADDR=y
CONFIG_ROCKCHIP_GPIO=y
CONFIG_SYS_I2C_ROCKCHIP=y
-CONFIG_MISC=y
CONFIG_MMC_DW=y
CONFIG_MMC_DW_ROCKCHIP=y
CONFIG_MMC_SDHCI=y
diff --git a/configs/nanopi-r2c-plus-rk3328_defconfig b/configs/nanopi-r2c-plus-rk3328_defconfig
index 320ed8b..beef682 100644
--- a/configs/nanopi-r2c-plus-rk3328_defconfig
+++ b/configs/nanopi-r2c-plus-rk3328_defconfig
@@ -2,23 +2,13 @@
CONFIG_SKIP_LOWLEVEL_INIT=y
CONFIG_COUNTER_FREQUENCY=24000000
CONFIG_ARCH_ROCKCHIP=y
-CONFIG_TEXT_BASE=0x00200000
CONFIG_SPL_GPIO=y
CONFIG_NR_DRAM_BANKS=1
-CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y
-CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x300000
CONFIG_SF_DEFAULT_SPEED=20000000
CONFIG_ENV_OFFSET=0x3F8000
CONFIG_DEFAULT_DEVICE_TREE="rk3328-nanopi-r2c-plus"
CONFIG_DM_RESET=y
CONFIG_ROCKCHIP_RK3328=y
-CONFIG_TPL_ROCKCHIP_COMMON_BOARD=y
-CONFIG_TPL_LIBCOMMON_SUPPORT=y
-CONFIG_TPL_LIBGENERIC_SUPPORT=y
-CONFIG_SPL_DRIVERS_MISC=y
-CONFIG_SPL_STACK_R_ADDR=0x600000
-CONFIG_SPL_STACK=0x400000
-CONFIG_TPL_SYS_MALLOC_F_LEN=0x800
CONFIG_DEBUG_UART_BASE=0xFF130000
CONFIG_DEBUG_UART_CLOCK=24000000
CONFIG_SYS_LOAD_ADDR=0x800800
@@ -26,30 +16,28 @@
# CONFIG_ANDROID_BOOT_IMAGE is not set
CONFIG_FIT=y
CONFIG_FIT_VERBOSE=y
+CONFIG_SPL_FIT_SIGNATURE=y
CONFIG_SPL_LOAD_FIT=y
+CONFIG_LEGACY_IMAGE_FORMAT=y
CONFIG_DEFAULT_FDT_FILE="rockchip/rk3328-nanopi-r2c-plus.dtb"
# CONFIG_DISPLAY_CPUINFO is not set
CONFIG_DISPLAY_BOARDINFO_LATE=y
-CONFIG_MISC_INIT_R=y
CONFIG_SPL_MAX_SIZE=0x40000
CONFIG_SPL_PAD_TO=0x7f8000
-CONFIG_SPL_HAS_BSS_LINKER_SECTION=y
-CONFIG_SPL_BSS_START_ADDR=0x2000000
-CONFIG_SPL_BSS_MAX_SIZE=0x2000
# CONFIG_SPL_RAW_IMAGE_SUPPORT is not set
-# CONFIG_SPL_SHARES_INIT_SP_ADDR is not set
-CONFIG_SPL_STACK_R=y
-CONFIG_SPL_I2C=y
CONFIG_SPL_POWER=y
CONFIG_SPL_ATF=y
CONFIG_SPL_ATF_NO_PLATFORM_PARAM=y
-CONFIG_TPL_SYS_MALLOC_SIMPLE=y
CONFIG_CMD_BOOTZ=y
+CONFIG_CMD_GPIO=y
CONFIG_CMD_GPT=y
CONFIG_CMD_MMC=y
CONFIG_CMD_USB=y
+CONFIG_CMD_ROCKUSB=y
+CONFIG_CMD_USB_MASS_STORAGE=y
# CONFIG_CMD_SETEXPR is not set
CONFIG_CMD_TIME=y
+CONFIG_CMD_REGULATOR=y
CONFIG_SPL_OF_CONTROL=y
CONFIG_TPL_OF_CONTROL=y
CONFIG_OF_SPL_REMOVE_PROPS="clock-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents"
@@ -57,8 +45,8 @@
CONFIG_ENV_IS_IN_MMC=y
CONFIG_SYS_RELOC_GD_ENV_ADDR=y
CONFIG_SYS_MMC_ENV_DEV=1
-CONFIG_NET_RANDOM_ETHADDR=y
CONFIG_TPL_DM=y
+CONFIG_SPL_DM_SEQ_ALIAS=y
CONFIG_REGMAP=y
CONFIG_SPL_REGMAP=y
CONFIG_TPL_REGMAP=y
@@ -71,9 +59,13 @@
CONFIG_FASTBOOT_CMD_OEM_FORMAT=y
CONFIG_ROCKCHIP_GPIO=y
CONFIG_SYS_I2C_ROCKCHIP=y
-CONFIG_MISC=y
CONFIG_MMC_DW=y
CONFIG_MMC_DW_ROCKCHIP=y
+CONFIG_PHY_MOTORCOMM=y
+CONFIG_PHY_REALTEK=y
+CONFIG_DM_MDIO=y
+CONFIG_DM_ETH_PHY=y
+CONFIG_PHY_GIGE=y
CONFIG_ETH_DESIGNWARE=y
CONFIG_GMAC_ROCKCHIP=y
CONFIG_PHY_ROCKCHIP_INNO_USB2=y
@@ -81,16 +73,18 @@
CONFIG_SPL_PINCTRL=y
CONFIG_DM_PMIC=y
CONFIG_PMIC_RK8XX=y
-CONFIG_SPL_PMIC_RK8XX=y
CONFIG_SPL_DM_REGULATOR=y
-CONFIG_REGULATOR_PWM=y
CONFIG_DM_REGULATOR_FIXED=y
CONFIG_SPL_DM_REGULATOR_FIXED=y
+CONFIG_DM_REGULATOR_GPIO=y
+CONFIG_SPL_DM_REGULATOR_GPIO=y
CONFIG_REGULATOR_RK8XX=y
CONFIG_PWM_ROCKCHIP=y
CONFIG_RAM=y
CONFIG_SPL_RAM=y
CONFIG_TPL_RAM=y
+CONFIG_DM_RNG=y
+CONFIG_RNG_ROCKCHIP=y
CONFIG_BAUDRATE=1500000
CONFIG_DEBUG_UART_SHIFT=2
CONFIG_SYS_NS16550_MEM32=y
@@ -98,17 +92,18 @@
CONFIG_SYSRESET=y
# CONFIG_TPL_SYSRESET is not set
CONFIG_USB=y
+CONFIG_DM_USB_GADGET=y
CONFIG_USB_XHCI_HCD=y
+CONFIG_USB_XHCI_DWC3=y
CONFIG_USB_EHCI_HCD=y
CONFIG_USB_EHCI_GENERIC=y
CONFIG_USB_OHCI_HCD=y
CONFIG_USB_OHCI_GENERIC=y
-CONFIG_USB_DWC2=y
CONFIG_USB_DWC3=y
# CONFIG_USB_DWC3_GADGET is not set
-CONFIG_USB_DWC3_GENERIC=y
CONFIG_USB_GADGET=y
CONFIG_USB_GADGET_DWC2_OTG=y
+CONFIG_USB_FUNCTION_ROCKUSB=y
CONFIG_SPL_TINY_MEMSET=y
CONFIG_TPL_TINY_MEMSET=y
CONFIG_ERRNO_STR=y
diff --git a/configs/nanopi-r2c-rk3328_defconfig b/configs/nanopi-r2c-rk3328_defconfig
index 583179d..8960c1a 100644
--- a/configs/nanopi-r2c-rk3328_defconfig
+++ b/configs/nanopi-r2c-rk3328_defconfig
@@ -2,23 +2,13 @@
CONFIG_SKIP_LOWLEVEL_INIT=y
CONFIG_COUNTER_FREQUENCY=24000000
CONFIG_ARCH_ROCKCHIP=y
-CONFIG_TEXT_BASE=0x00200000
CONFIG_SPL_GPIO=y
CONFIG_NR_DRAM_BANKS=1
-CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y
-CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x300000
CONFIG_SF_DEFAULT_SPEED=20000000
CONFIG_ENV_OFFSET=0x3F8000
CONFIG_DEFAULT_DEVICE_TREE="rk3328-nanopi-r2c"
CONFIG_DM_RESET=y
CONFIG_ROCKCHIP_RK3328=y
-CONFIG_TPL_ROCKCHIP_COMMON_BOARD=y
-CONFIG_TPL_LIBCOMMON_SUPPORT=y
-CONFIG_TPL_LIBGENERIC_SUPPORT=y
-CONFIG_SPL_DRIVERS_MISC=y
-CONFIG_SPL_STACK_R_ADDR=0x600000
-CONFIG_SPL_STACK=0x400000
-CONFIG_TPL_SYS_MALLOC_F_LEN=0x800
CONFIG_DEBUG_UART_BASE=0xFF130000
CONFIG_DEBUG_UART_CLOCK=24000000
CONFIG_SYS_LOAD_ADDR=0x800800
@@ -26,30 +16,28 @@
# CONFIG_ANDROID_BOOT_IMAGE is not set
CONFIG_FIT=y
CONFIG_FIT_VERBOSE=y
+CONFIG_SPL_FIT_SIGNATURE=y
CONFIG_SPL_LOAD_FIT=y
+CONFIG_LEGACY_IMAGE_FORMAT=y
CONFIG_DEFAULT_FDT_FILE="rockchip/rk3328-nanopi-r2c.dtb"
# CONFIG_DISPLAY_CPUINFO is not set
CONFIG_DISPLAY_BOARDINFO_LATE=y
-CONFIG_MISC_INIT_R=y
CONFIG_SPL_MAX_SIZE=0x40000
CONFIG_SPL_PAD_TO=0x7f8000
-CONFIG_SPL_HAS_BSS_LINKER_SECTION=y
-CONFIG_SPL_BSS_START_ADDR=0x2000000
-CONFIG_SPL_BSS_MAX_SIZE=0x2000
# CONFIG_SPL_RAW_IMAGE_SUPPORT is not set
-# CONFIG_SPL_SHARES_INIT_SP_ADDR is not set
-CONFIG_SPL_STACK_R=y
-CONFIG_SPL_I2C=y
CONFIG_SPL_POWER=y
CONFIG_SPL_ATF=y
CONFIG_SPL_ATF_NO_PLATFORM_PARAM=y
-CONFIG_TPL_SYS_MALLOC_SIMPLE=y
CONFIG_CMD_BOOTZ=y
+CONFIG_CMD_GPIO=y
CONFIG_CMD_GPT=y
CONFIG_CMD_MMC=y
CONFIG_CMD_USB=y
+CONFIG_CMD_ROCKUSB=y
+CONFIG_CMD_USB_MASS_STORAGE=y
# CONFIG_CMD_SETEXPR is not set
CONFIG_CMD_TIME=y
+CONFIG_CMD_REGULATOR=y
CONFIG_SPL_OF_CONTROL=y
CONFIG_TPL_OF_CONTROL=y
CONFIG_OF_SPL_REMOVE_PROPS="clock-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents"
@@ -57,8 +45,8 @@
CONFIG_ENV_IS_IN_MMC=y
CONFIG_SYS_RELOC_GD_ENV_ADDR=y
CONFIG_SYS_MMC_ENV_DEV=1
-CONFIG_NET_RANDOM_ETHADDR=y
CONFIG_TPL_DM=y
+CONFIG_SPL_DM_SEQ_ALIAS=y
CONFIG_REGMAP=y
CONFIG_SPL_REGMAP=y
CONFIG_TPL_REGMAP=y
@@ -71,9 +59,13 @@
CONFIG_FASTBOOT_CMD_OEM_FORMAT=y
CONFIG_ROCKCHIP_GPIO=y
CONFIG_SYS_I2C_ROCKCHIP=y
-CONFIG_MISC=y
CONFIG_MMC_DW=y
CONFIG_MMC_DW_ROCKCHIP=y
+CONFIG_PHY_MOTORCOMM=y
+CONFIG_PHY_REALTEK=y
+CONFIG_DM_MDIO=y
+CONFIG_DM_ETH_PHY=y
+CONFIG_PHY_GIGE=y
CONFIG_ETH_DESIGNWARE=y
CONFIG_GMAC_ROCKCHIP=y
CONFIG_PHY_ROCKCHIP_INNO_USB2=y
@@ -81,16 +73,18 @@
CONFIG_SPL_PINCTRL=y
CONFIG_DM_PMIC=y
CONFIG_PMIC_RK8XX=y
-CONFIG_SPL_PMIC_RK8XX=y
CONFIG_SPL_DM_REGULATOR=y
-CONFIG_REGULATOR_PWM=y
CONFIG_DM_REGULATOR_FIXED=y
CONFIG_SPL_DM_REGULATOR_FIXED=y
+CONFIG_DM_REGULATOR_GPIO=y
+CONFIG_SPL_DM_REGULATOR_GPIO=y
CONFIG_REGULATOR_RK8XX=y
CONFIG_PWM_ROCKCHIP=y
CONFIG_RAM=y
CONFIG_SPL_RAM=y
CONFIG_TPL_RAM=y
+CONFIG_DM_RNG=y
+CONFIG_RNG_ROCKCHIP=y
CONFIG_BAUDRATE=1500000
CONFIG_DEBUG_UART_SHIFT=2
CONFIG_SYS_NS16550_MEM32=y
@@ -98,17 +92,18 @@
CONFIG_SYSRESET=y
# CONFIG_TPL_SYSRESET is not set
CONFIG_USB=y
+CONFIG_DM_USB_GADGET=y
CONFIG_USB_XHCI_HCD=y
+CONFIG_USB_XHCI_DWC3=y
CONFIG_USB_EHCI_HCD=y
CONFIG_USB_EHCI_GENERIC=y
CONFIG_USB_OHCI_HCD=y
CONFIG_USB_OHCI_GENERIC=y
-CONFIG_USB_DWC2=y
CONFIG_USB_DWC3=y
# CONFIG_USB_DWC3_GADGET is not set
-CONFIG_USB_DWC3_GENERIC=y
CONFIG_USB_GADGET=y
CONFIG_USB_GADGET_DWC2_OTG=y
+CONFIG_USB_FUNCTION_ROCKUSB=y
CONFIG_SPL_TINY_MEMSET=y
CONFIG_TPL_TINY_MEMSET=y
CONFIG_ERRNO_STR=y
diff --git a/configs/nanopi-r2s-rk3328_defconfig b/configs/nanopi-r2s-rk3328_defconfig
index f7ed71e..96e67e2 100644
--- a/configs/nanopi-r2s-rk3328_defconfig
+++ b/configs/nanopi-r2s-rk3328_defconfig
@@ -2,23 +2,13 @@
CONFIG_SKIP_LOWLEVEL_INIT=y
CONFIG_COUNTER_FREQUENCY=24000000
CONFIG_ARCH_ROCKCHIP=y
-CONFIG_TEXT_BASE=0x00200000
CONFIG_SPL_GPIO=y
CONFIG_NR_DRAM_BANKS=1
-CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y
-CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x300000
CONFIG_SF_DEFAULT_SPEED=20000000
CONFIG_ENV_OFFSET=0x3F8000
CONFIG_DEFAULT_DEVICE_TREE="rk3328-nanopi-r2s"
CONFIG_DM_RESET=y
CONFIG_ROCKCHIP_RK3328=y
-CONFIG_TPL_ROCKCHIP_COMMON_BOARD=y
-CONFIG_TPL_LIBCOMMON_SUPPORT=y
-CONFIG_TPL_LIBGENERIC_SUPPORT=y
-CONFIG_SPL_DRIVERS_MISC=y
-CONFIG_SPL_STACK_R_ADDR=0x600000
-CONFIG_SPL_STACK=0x400000
-CONFIG_TPL_SYS_MALLOC_F_LEN=0x800
CONFIG_DEBUG_UART_BASE=0xFF130000
CONFIG_DEBUG_UART_CLOCK=24000000
CONFIG_SYS_LOAD_ADDR=0x800800
@@ -26,30 +16,28 @@
# CONFIG_ANDROID_BOOT_IMAGE is not set
CONFIG_FIT=y
CONFIG_FIT_VERBOSE=y
+CONFIG_SPL_FIT_SIGNATURE=y
CONFIG_SPL_LOAD_FIT=y
+CONFIG_LEGACY_IMAGE_FORMAT=y
CONFIG_DEFAULT_FDT_FILE="rockchip/rk3328-nanopi-r2s.dtb"
# CONFIG_DISPLAY_CPUINFO is not set
CONFIG_DISPLAY_BOARDINFO_LATE=y
-CONFIG_MISC_INIT_R=y
CONFIG_SPL_MAX_SIZE=0x40000
CONFIG_SPL_PAD_TO=0x7f8000
-CONFIG_SPL_HAS_BSS_LINKER_SECTION=y
-CONFIG_SPL_BSS_START_ADDR=0x2000000
-CONFIG_SPL_BSS_MAX_SIZE=0x2000
# CONFIG_SPL_RAW_IMAGE_SUPPORT is not set
-# CONFIG_SPL_SHARES_INIT_SP_ADDR is not set
-CONFIG_SPL_STACK_R=y
-CONFIG_SPL_I2C=y
CONFIG_SPL_POWER=y
CONFIG_SPL_ATF=y
CONFIG_SPL_ATF_NO_PLATFORM_PARAM=y
-CONFIG_TPL_SYS_MALLOC_SIMPLE=y
CONFIG_CMD_BOOTZ=y
+CONFIG_CMD_GPIO=y
CONFIG_CMD_GPT=y
CONFIG_CMD_MMC=y
CONFIG_CMD_USB=y
+CONFIG_CMD_ROCKUSB=y
+CONFIG_CMD_USB_MASS_STORAGE=y
# CONFIG_CMD_SETEXPR is not set
CONFIG_CMD_TIME=y
+CONFIG_CMD_REGULATOR=y
CONFIG_SPL_OF_CONTROL=y
CONFIG_TPL_OF_CONTROL=y
CONFIG_OF_SPL_REMOVE_PROPS="clock-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents"
@@ -57,8 +45,8 @@
CONFIG_ENV_IS_IN_MMC=y
CONFIG_SYS_RELOC_GD_ENV_ADDR=y
CONFIG_SYS_MMC_ENV_DEV=1
-CONFIG_NET_RANDOM_ETHADDR=y
CONFIG_TPL_DM=y
+CONFIG_SPL_DM_SEQ_ALIAS=y
CONFIG_REGMAP=y
CONFIG_SPL_REGMAP=y
CONFIG_TPL_REGMAP=y
@@ -71,9 +59,13 @@
CONFIG_FASTBOOT_CMD_OEM_FORMAT=y
CONFIG_ROCKCHIP_GPIO=y
CONFIG_SYS_I2C_ROCKCHIP=y
-CONFIG_MISC=y
CONFIG_MMC_DW=y
CONFIG_MMC_DW_ROCKCHIP=y
+CONFIG_PHY_MOTORCOMM=y
+CONFIG_PHY_REALTEK=y
+CONFIG_DM_MDIO=y
+CONFIG_DM_ETH_PHY=y
+CONFIG_PHY_GIGE=y
CONFIG_ETH_DESIGNWARE=y
CONFIG_GMAC_ROCKCHIP=y
CONFIG_PHY_ROCKCHIP_INNO_USB2=y
@@ -81,16 +73,18 @@
CONFIG_SPL_PINCTRL=y
CONFIG_DM_PMIC=y
CONFIG_PMIC_RK8XX=y
-CONFIG_SPL_PMIC_RK8XX=y
CONFIG_SPL_DM_REGULATOR=y
-CONFIG_REGULATOR_PWM=y
CONFIG_DM_REGULATOR_FIXED=y
CONFIG_SPL_DM_REGULATOR_FIXED=y
+CONFIG_DM_REGULATOR_GPIO=y
+CONFIG_SPL_DM_REGULATOR_GPIO=y
CONFIG_REGULATOR_RK8XX=y
CONFIG_PWM_ROCKCHIP=y
CONFIG_RAM=y
CONFIG_SPL_RAM=y
CONFIG_TPL_RAM=y
+CONFIG_DM_RNG=y
+CONFIG_RNG_ROCKCHIP=y
CONFIG_BAUDRATE=1500000
CONFIG_DEBUG_UART_SHIFT=2
CONFIG_SYS_NS16550_MEM32=y
@@ -98,17 +92,18 @@
CONFIG_SYSRESET=y
# CONFIG_TPL_SYSRESET is not set
CONFIG_USB=y
+CONFIG_DM_USB_GADGET=y
CONFIG_USB_XHCI_HCD=y
+CONFIG_USB_XHCI_DWC3=y
CONFIG_USB_EHCI_HCD=y
CONFIG_USB_EHCI_GENERIC=y
CONFIG_USB_OHCI_HCD=y
CONFIG_USB_OHCI_GENERIC=y
-CONFIG_USB_DWC2=y
CONFIG_USB_DWC3=y
# CONFIG_USB_DWC3_GADGET is not set
-CONFIG_USB_DWC3_GENERIC=y
CONFIG_USB_GADGET=y
CONFIG_USB_GADGET_DWC2_OTG=y
+CONFIG_USB_FUNCTION_ROCKUSB=y
CONFIG_SPL_TINY_MEMSET=y
CONFIG_TPL_TINY_MEMSET=y
CONFIG_ERRNO_STR=y
diff --git a/configs/nanopi-r4s-rk3399_defconfig b/configs/nanopi-r4s-rk3399_defconfig
index cacaab1..ea01d32 100644
--- a/configs/nanopi-r4s-rk3399_defconfig
+++ b/configs/nanopi-r4s-rk3399_defconfig
@@ -2,31 +2,20 @@
CONFIG_SKIP_LOWLEVEL_INIT=y
CONFIG_COUNTER_FREQUENCY=24000000
CONFIG_ARCH_ROCKCHIP=y
-CONFIG_TEXT_BASE=0x00200000
CONFIG_NR_DRAM_BANKS=1
-CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y
-CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x300000
CONFIG_ENV_OFFSET=0x3F8000
CONFIG_DEFAULT_DEVICE_TREE="rk3399-nanopi-r4s"
CONFIG_ROCKCHIP_RK3399=y
CONFIG_TARGET_EVB_RK3399=y
-CONFIG_SPL_STACK=0x400000
CONFIG_DEBUG_UART_BASE=0xFF1A0000
CONFIG_DEBUG_UART_CLOCK=24000000
CONFIG_SYS_LOAD_ADDR=0x800800
CONFIG_DEBUG_UART=y
CONFIG_DEFAULT_FDT_FILE="rockchip/rk3399-nanopi-r4s.dtb"
CONFIG_DISPLAY_BOARDINFO_LATE=y
-CONFIG_MISC_INIT_R=y
CONFIG_SPL_MAX_SIZE=0x2e000
CONFIG_SPL_PAD_TO=0x7f8000
-CONFIG_SPL_HAS_BSS_LINKER_SECTION=y
-CONFIG_SPL_BSS_START_ADDR=0x400000
-CONFIG_SPL_BSS_MAX_SIZE=0x2000
# CONFIG_SPL_RAW_IMAGE_SUPPORT is not set
-# CONFIG_SPL_SHARES_INIT_SP_ADDR is not set
-CONFIG_SPL_STACK_R=y
-CONFIG_SPL_STACK_R_MALLOC_SIMPLE_LEN=0x10000
CONFIG_SPL_ATF_NO_PLATFORM_PARAM=y
CONFIG_TPL=y
CONFIG_CMD_BOOTZ=y
@@ -41,9 +30,6 @@
CONFIG_SYS_RELOC_GD_ENV_ADDR=y
CONFIG_ROCKCHIP_GPIO=y
CONFIG_SYS_I2C_ROCKCHIP=y
-CONFIG_MISC=y
-CONFIG_ROCKCHIP_EFUSE=y
-CONFIG_ROCKCHIP_OTP=y
CONFIG_MMC_DW=y
CONFIG_MMC_DW_ROCKCHIP=y
CONFIG_MMC_SDHCI=y
diff --git a/configs/nanopi-r5c-rk3568_defconfig b/configs/nanopi-r5c-rk3568_defconfig
index f5a472d..0f1a946 100644
--- a/configs/nanopi-r5c-rk3568_defconfig
+++ b/configs/nanopi-r5c-rk3568_defconfig
@@ -3,18 +3,10 @@
CONFIG_SYS_HAS_NONCACHED_MEMORY=y
CONFIG_COUNTER_FREQUENCY=24000000
CONFIG_ARCH_ROCKCHIP=y
-CONFIG_TEXT_BASE=0x00a00000
-CONFIG_SPL_LIBCOMMON_SUPPORT=y
-CONFIG_SPL_LIBGENERIC_SUPPORT=y
CONFIG_NR_DRAM_BANKS=2
-CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y
-CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0xc00000
CONFIG_DEFAULT_DEVICE_TREE="rk3568-nanopi-r5c"
CONFIG_ROCKCHIP_RK3568=y
-CONFIG_SPL_ROCKCHIP_COMMON_BOARD=y
CONFIG_SPL_SERIAL=y
-CONFIG_SPL_STACK_R_ADDR=0x600000
-CONFIG_SPL_STACK=0x400000
CONFIG_DEBUG_UART_BASE=0xFE660000
CONFIG_DEBUG_UART_CLOCK=24000000
CONFIG_SYS_LOAD_ADDR=0xc00800
@@ -30,12 +22,7 @@
CONFIG_DISPLAY_BOARDINFO_LATE=y
CONFIG_SPL_MAX_SIZE=0x40000
CONFIG_SPL_PAD_TO=0x7f8000
-CONFIG_SPL_HAS_BSS_LINKER_SECTION=y
-CONFIG_SPL_BSS_START_ADDR=0x4000000
-CONFIG_SPL_BSS_MAX_SIZE=0x4000
# CONFIG_SPL_RAW_IMAGE_SUPPORT is not set
-# CONFIG_SPL_SHARES_INIT_SP_ADDR is not set
-CONFIG_SPL_STACK_R=y
CONFIG_SPL_ATF=y
CONFIG_CMD_GPIO=y
CONFIG_CMD_GPT=y
diff --git a/configs/nanopi-r5s-rk3568_defconfig b/configs/nanopi-r5s-rk3568_defconfig
index 99692d3..4ebf0cc 100644
--- a/configs/nanopi-r5s-rk3568_defconfig
+++ b/configs/nanopi-r5s-rk3568_defconfig
@@ -3,18 +3,10 @@
CONFIG_SYS_HAS_NONCACHED_MEMORY=y
CONFIG_COUNTER_FREQUENCY=24000000
CONFIG_ARCH_ROCKCHIP=y
-CONFIG_TEXT_BASE=0x00a00000
-CONFIG_SPL_LIBCOMMON_SUPPORT=y
-CONFIG_SPL_LIBGENERIC_SUPPORT=y
CONFIG_NR_DRAM_BANKS=2
-CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y
-CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0xc00000
CONFIG_DEFAULT_DEVICE_TREE="rk3568-nanopi-r5s"
CONFIG_ROCKCHIP_RK3568=y
-CONFIG_SPL_ROCKCHIP_COMMON_BOARD=y
CONFIG_SPL_SERIAL=y
-CONFIG_SPL_STACK_R_ADDR=0x600000
-CONFIG_SPL_STACK=0x400000
CONFIG_DEBUG_UART_BASE=0xFE660000
CONFIG_DEBUG_UART_CLOCK=24000000
CONFIG_SYS_LOAD_ADDR=0xc00800
@@ -30,12 +22,7 @@
CONFIG_DISPLAY_BOARDINFO_LATE=y
CONFIG_SPL_MAX_SIZE=0x40000
CONFIG_SPL_PAD_TO=0x7f8000
-CONFIG_SPL_HAS_BSS_LINKER_SECTION=y
-CONFIG_SPL_BSS_START_ADDR=0x4000000
-CONFIG_SPL_BSS_MAX_SIZE=0x4000
# CONFIG_SPL_RAW_IMAGE_SUPPORT is not set
-# CONFIG_SPL_SHARES_INIT_SP_ADDR is not set
-CONFIG_SPL_STACK_R=y
CONFIG_SPL_ATF=y
CONFIG_CMD_GPIO=y
CONFIG_CMD_GPT=y
diff --git a/configs/nas220_defconfig b/configs/nas220_defconfig
index f01b26f..4ea342a 100644
--- a/configs/nas220_defconfig
+++ b/configs/nas220_defconfig
@@ -10,7 +10,7 @@
CONFIG_TARGET_NAS220=y
CONFIG_ENV_SIZE=0x10000
CONFIG_ENV_OFFSET=0xA0000
-CONFIG_DEFAULT_DEVICE_TREE="kirkwood-blackarmor-nas220"
+CONFIG_DEFAULT_DEVICE_TREE="marvell/kirkwood-blackarmor-nas220"
CONFIG_IDENT_STRING="\nNAS 220"
CONFIG_SYS_LOAD_ADDR=0x800000
# CONFIG_SYS_MALLOC_F is not set
diff --git a/configs/net2big_v2_defconfig b/configs/net2big_v2_defconfig
index dda627a..39cbc33 100644
--- a/configs/net2big_v2_defconfig
+++ b/configs/net2big_v2_defconfig
@@ -12,7 +12,7 @@
CONFIG_ENV_SIZE=0x1000
CONFIG_ENV_OFFSET=0x70000
CONFIG_ENV_SECT_SIZE=0x10000
-CONFIG_DEFAULT_DEVICE_TREE="kirkwood-net2big"
+CONFIG_DEFAULT_DEVICE_TREE="marvell/kirkwood-net2big"
CONFIG_IDENT_STRING=" 2Big v2"
CONFIG_SYS_LOAD_ADDR=0x800000
CONFIG_ENV_ADDR=0x70000
diff --git a/configs/netspace_lite_v2_defconfig b/configs/netspace_lite_v2_defconfig
index 742e620..cd416cb 100644
--- a/configs/netspace_lite_v2_defconfig
+++ b/configs/netspace_lite_v2_defconfig
@@ -12,7 +12,7 @@
CONFIG_ENV_SIZE=0x1000
CONFIG_ENV_OFFSET=0x70000
CONFIG_ENV_SECT_SIZE=0x10000
-CONFIG_DEFAULT_DEVICE_TREE="kirkwood-ns2lite"
+CONFIG_DEFAULT_DEVICE_TREE="marvell/kirkwood-ns2lite"
CONFIG_IDENT_STRING=" NS v2 Lite"
CONFIG_SYS_LOAD_ADDR=0x800000
CONFIG_ENV_ADDR=0x70000
diff --git a/configs/netspace_max_v2_defconfig b/configs/netspace_max_v2_defconfig
index 7779e68..6a3d929 100644
--- a/configs/netspace_max_v2_defconfig
+++ b/configs/netspace_max_v2_defconfig
@@ -12,7 +12,7 @@
CONFIG_ENV_SIZE=0x1000
CONFIG_ENV_OFFSET=0x70000
CONFIG_ENV_SECT_SIZE=0x10000
-CONFIG_DEFAULT_DEVICE_TREE="kirkwood-ns2max"
+CONFIG_DEFAULT_DEVICE_TREE="marvell/kirkwood-ns2max"
CONFIG_IDENT_STRING=" NS Max v2"
CONFIG_SYS_LOAD_ADDR=0x800000
CONFIG_ENV_ADDR=0x70000
diff --git a/configs/netspace_mini_v2_defconfig b/configs/netspace_mini_v2_defconfig
index 9e3614b..e25631b 100644
--- a/configs/netspace_mini_v2_defconfig
+++ b/configs/netspace_mini_v2_defconfig
@@ -12,7 +12,7 @@
CONFIG_ENV_SIZE=0x1000
CONFIG_ENV_OFFSET=0x70000
CONFIG_ENV_SECT_SIZE=0x10000
-CONFIG_DEFAULT_DEVICE_TREE="kirkwood-ns2mini"
+CONFIG_DEFAULT_DEVICE_TREE="marvell/kirkwood-ns2mini"
CONFIG_IDENT_STRING=" NS v2 Mini"
CONFIG_SYS_LOAD_ADDR=0x800000
CONFIG_ENV_ADDR=0x70000
diff --git a/configs/netspace_v2_defconfig b/configs/netspace_v2_defconfig
index 1583a0a..b6ac2a8 100644
--- a/configs/netspace_v2_defconfig
+++ b/configs/netspace_v2_defconfig
@@ -12,7 +12,7 @@
CONFIG_ENV_SIZE=0x1000
CONFIG_ENV_OFFSET=0x70000
CONFIG_ENV_SECT_SIZE=0x10000
-CONFIG_DEFAULT_DEVICE_TREE="kirkwood-ns2"
+CONFIG_DEFAULT_DEVICE_TREE="marvell/kirkwood-ns2"
CONFIG_IDENT_STRING=" NS v2"
CONFIG_SYS_LOAD_ADDR=0x800000
CONFIG_ENV_ADDR=0x70000
diff --git a/configs/neu6a-io-rk3588_defconfig b/configs/neu6a-io-rk3588_defconfig
index d5301c6..307a540 100644
--- a/configs/neu6a-io-rk3588_defconfig
+++ b/configs/neu6a-io-rk3588_defconfig
@@ -2,19 +2,11 @@
CONFIG_SKIP_LOWLEVEL_INIT=y
CONFIG_COUNTER_FREQUENCY=24000000
CONFIG_ARCH_ROCKCHIP=y
-CONFIG_TEXT_BASE=0x00a00000
-CONFIG_SPL_LIBCOMMON_SUPPORT=y
-CONFIG_SPL_LIBGENERIC_SUPPORT=y
CONFIG_NR_DRAM_BANKS=2
-CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y
-CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0xc00000
CONFIG_DEFAULT_DEVICE_TREE="rk3588-edgeble-neu6a-io"
CONFIG_ROCKCHIP_RK3588=y
-CONFIG_SPL_ROCKCHIP_COMMON_BOARD=y
CONFIG_SPL_SERIAL=y
-CONFIG_SPL_STACK_R_ADDR=0x600000
CONFIG_TARGET_RK3588_NEU6=y
-CONFIG_SPL_STACK=0x400000
CONFIG_DEBUG_UART_BASE=0xFEB50000
CONFIG_DEBUG_UART_CLOCK=24000000
CONFIG_SYS_LOAD_ADDR=0xc00800
@@ -27,12 +19,7 @@
CONFIG_DISPLAY_BOARDINFO_LATE=y
CONFIG_SPL_MAX_SIZE=0x20000
CONFIG_SPL_PAD_TO=0x7f8000
-CONFIG_SPL_HAS_BSS_LINKER_SECTION=y
-CONFIG_SPL_BSS_START_ADDR=0x4000000
-CONFIG_SPL_BSS_MAX_SIZE=0x4000
# CONFIG_SPL_RAW_IMAGE_SUPPORT is not set
-# CONFIG_SPL_SHARES_INIT_SP_ADDR is not set
-CONFIG_SPL_STACK_R=y
CONFIG_SPL_ATF=y
CONFIG_CMD_GPT=y
CONFIG_CMD_MMC=y
diff --git a/configs/neu6b-io-rk3588_defconfig b/configs/neu6b-io-rk3588_defconfig
index b13c9b5..9ef2bb2 100644
--- a/configs/neu6b-io-rk3588_defconfig
+++ b/configs/neu6b-io-rk3588_defconfig
@@ -2,19 +2,11 @@
CONFIG_SKIP_LOWLEVEL_INIT=y
CONFIG_COUNTER_FREQUENCY=24000000
CONFIG_ARCH_ROCKCHIP=y
-CONFIG_TEXT_BASE=0x00a00000
-CONFIG_SPL_LIBCOMMON_SUPPORT=y
-CONFIG_SPL_LIBGENERIC_SUPPORT=y
CONFIG_NR_DRAM_BANKS=2
-CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y
-CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0xc00000
CONFIG_DEFAULT_DEVICE_TREE="rk3588-edgeble-neu6b-io"
CONFIG_ROCKCHIP_RK3588=y
-CONFIG_SPL_ROCKCHIP_COMMON_BOARD=y
CONFIG_SPL_SERIAL=y
-CONFIG_SPL_STACK_R_ADDR=0x600000
CONFIG_TARGET_RK3588_NEU6=y
-CONFIG_SPL_STACK=0x400000
CONFIG_DEBUG_UART_BASE=0xFEB50000
CONFIG_DEBUG_UART_CLOCK=24000000
CONFIG_SYS_LOAD_ADDR=0xc00800
@@ -27,12 +19,7 @@
CONFIG_DISPLAY_BOARDINFO_LATE=y
CONFIG_SPL_MAX_SIZE=0x20000
CONFIG_SPL_PAD_TO=0x7f8000
-CONFIG_SPL_HAS_BSS_LINKER_SECTION=y
-CONFIG_SPL_BSS_START_ADDR=0x4000000
-CONFIG_SPL_BSS_MAX_SIZE=0x4000
# CONFIG_SPL_RAW_IMAGE_SUPPORT is not set
-# CONFIG_SPL_SHARES_INIT_SP_ADDR is not set
-CONFIG_SPL_STACK_R=y
CONFIG_SPL_ATF=y
CONFIG_CMD_GPT=y
CONFIG_CMD_MMC=y
diff --git a/configs/nsa310s_defconfig b/configs/nsa310s_defconfig
index 89d8b18..e859a43 100644
--- a/configs/nsa310s_defconfig
+++ b/configs/nsa310s_defconfig
@@ -13,7 +13,7 @@
CONFIG_TARGET_NSA310S=y
CONFIG_ENV_SIZE=0x20000
CONFIG_ENV_OFFSET=0xE0000
-CONFIG_DEFAULT_DEVICE_TREE="kirkwood-nsa310s"
+CONFIG_DEFAULT_DEVICE_TREE="marvell/kirkwood-nsa310s"
CONFIG_DEBUG_UART_BASE=0xf1012000
CONFIG_DEBUG_UART_CLOCK=166666667
CONFIG_IDENT_STRING="\nZyXEL NSA310S/320S 1/2-Bay Power Media Server"
diff --git a/configs/nsa325_defconfig b/configs/nsa325_defconfig
index 5da4a00..88a8900 100644
--- a/configs/nsa325_defconfig
+++ b/configs/nsa325_defconfig
@@ -13,7 +13,7 @@
CONFIG_TARGET_NSA325=y
CONFIG_ENV_SIZE=0x20000
CONFIG_ENV_OFFSET=0xC0000
-CONFIG_DEFAULT_DEVICE_TREE="kirkwood-nsa325"
+CONFIG_DEFAULT_DEVICE_TREE="marvell/kirkwood-nsa325"
CONFIG_IDENT_STRING="\nZyXEL NSA325 2-Bay Power Media Server"
CONFIG_SYS_LOAD_ADDR=0x800000
CONFIG_PCI=y
diff --git a/configs/odroid-c4_defconfig b/configs/odroid-c4_defconfig
index fe1f861..4ef1e68 100644
--- a/configs/odroid-c4_defconfig
+++ b/configs/odroid-c4_defconfig
@@ -7,7 +7,7 @@
CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x20000000
CONFIG_ENV_SIZE=0x2000
CONFIG_DM_GPIO=y
-CONFIG_DEFAULT_DEVICE_TREE="meson-sm1-odroid-c4"
+CONFIG_DEFAULT_DEVICE_TREE="amlogic/meson-sm1-odroid-c4"
CONFIG_OF_LIBFDT_OVERLAY=y
CONFIG_DM_RESET=y
CONFIG_MESON_G12A=y
diff --git a/configs/odroid-go-ultra_defconfig b/configs/odroid-go-ultra_defconfig
index 49d628b..06437fe 100644
--- a/configs/odroid-go-ultra_defconfig
+++ b/configs/odroid-go-ultra_defconfig
@@ -7,7 +7,7 @@
CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x20000000
CONFIG_ENV_SIZE=0x2000
CONFIG_DM_GPIO=y
-CONFIG_DEFAULT_DEVICE_TREE="meson-g12b-odroid-go-ultra"
+CONFIG_DEFAULT_DEVICE_TREE="amlogic/meson-g12b-odroid-go-ultra"
CONFIG_OF_LIBFDT_OVERLAY=y
CONFIG_DM_RESET=y
CONFIG_MESON_G12A=y
diff --git a/configs/odroid-hc4_defconfig b/configs/odroid-hc4_defconfig
index 7720ab5..60233fb 100644
--- a/configs/odroid-hc4_defconfig
+++ b/configs/odroid-hc4_defconfig
@@ -7,7 +7,7 @@
CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x20000000
CONFIG_ENV_SIZE=0x2000
CONFIG_DM_GPIO=y
-CONFIG_DEFAULT_DEVICE_TREE="meson-sm1-odroid-hc4"
+CONFIG_DEFAULT_DEVICE_TREE="amlogic/meson-sm1-odroid-hc4"
CONFIG_OF_LIBFDT_OVERLAY=y
CONFIG_DM_RESET=y
CONFIG_MESON_G12A=y
diff --git a/configs/odroid-m1-rk3568_defconfig b/configs/odroid-m1-rk3568_defconfig
index 3130e34..b5ed9e4 100644
--- a/configs/odroid-m1-rk3568_defconfig
+++ b/configs/odroid-m1-rk3568_defconfig
@@ -2,22 +2,14 @@
CONFIG_SKIP_LOWLEVEL_INIT=y
CONFIG_COUNTER_FREQUENCY=24000000
CONFIG_ARCH_ROCKCHIP=y
-CONFIG_TEXT_BASE=0x00a00000
-CONFIG_SPL_LIBCOMMON_SUPPORT=y
-CONFIG_SPL_LIBGENERIC_SUPPORT=y
CONFIG_NR_DRAM_BANKS=2
-CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y
-CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0xc00000
CONFIG_SF_DEFAULT_SPEED=24000000
CONFIG_SF_DEFAULT_MODE=0x1000
CONFIG_DEFAULT_DEVICE_TREE="rk3568-odroid-m1"
CONFIG_ROCKCHIP_RK3568=y
-CONFIG_SPL_ROCKCHIP_COMMON_BOARD=y
CONFIG_ROCKCHIP_SPI_IMAGE=y
CONFIG_SPL_SERIAL=y
-CONFIG_SPL_STACK_R_ADDR=0x600000
CONFIG_TARGET_ODROID_M1_RK3568=y
-CONFIG_SPL_STACK=0x400000
CONFIG_DEBUG_UART_BASE=0xFE660000
CONFIG_DEBUG_UART_CLOCK=24000000
CONFIG_SPL_SPI_FLASH_SUPPORT=y
@@ -36,12 +28,7 @@
CONFIG_DISPLAY_BOARDINFO_LATE=y
CONFIG_SPL_MAX_SIZE=0x40000
CONFIG_SPL_PAD_TO=0x7f8000
-CONFIG_SPL_HAS_BSS_LINKER_SECTION=y
-CONFIG_SPL_BSS_START_ADDR=0x4000000
-CONFIG_SPL_BSS_MAX_SIZE=0x4000
# CONFIG_SPL_RAW_IMAGE_SUPPORT is not set
-# CONFIG_SPL_SHARES_INIT_SP_ADDR is not set
-CONFIG_SPL_STACK_R=y
CONFIG_SPL_SPI_LOAD=y
CONFIG_SYS_SPI_U_BOOT_OFFS=0x100000
CONFIG_SPL_ATF=y
diff --git a/configs/odroid-n2_defconfig b/configs/odroid-n2_defconfig
index 9694f04..a4cc766 100644
--- a/configs/odroid-n2_defconfig
+++ b/configs/odroid-n2_defconfig
@@ -7,7 +7,7 @@
CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x20000000
CONFIG_ENV_SIZE=0x2000
CONFIG_DM_GPIO=y
-CONFIG_DEFAULT_DEVICE_TREE="meson-g12b-odroid-n2"
+CONFIG_DEFAULT_DEVICE_TREE="amlogic/meson-g12b-odroid-n2"
CONFIG_OF_LIBFDT_OVERLAY=y
CONFIG_DM_RESET=y
CONFIG_MESON_G12A=y
diff --git a/configs/odroid-n2l_defconfig b/configs/odroid-n2l_defconfig
index 673e0cf..3f657d1 100644
--- a/configs/odroid-n2l_defconfig
+++ b/configs/odroid-n2l_defconfig
@@ -7,7 +7,7 @@
CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x20000000
CONFIG_ENV_SIZE=0x2000
CONFIG_DM_GPIO=y
-CONFIG_DEFAULT_DEVICE_TREE="meson-g12b-odroid-n2l"
+CONFIG_DEFAULT_DEVICE_TREE="amlogic/meson-g12b-odroid-n2l"
CONFIG_OF_LIBFDT_OVERLAY=y
CONFIG_DM_RESET=y
CONFIG_MESON_G12A=y
diff --git a/configs/openrd_base_defconfig b/configs/openrd_base_defconfig
index 29a14e0..057dd28 100644
--- a/configs/openrd_base_defconfig
+++ b/configs/openrd_base_defconfig
@@ -11,7 +11,7 @@
CONFIG_TARGET_OPENRD=y
CONFIG_ENV_SIZE=0x20000
CONFIG_ENV_OFFSET=0x80000
-CONFIG_DEFAULT_DEVICE_TREE="kirkwood-openrd-base"
+CONFIG_DEFAULT_DEVICE_TREE="marvell/kirkwood-openrd-base"
CONFIG_IDENT_STRING="\nOpenRD-Base"
CONFIG_SYS_LOAD_ADDR=0x800000
# CONFIG_SYS_MALLOC_F is not set
diff --git a/configs/openrd_client_defconfig b/configs/openrd_client_defconfig
index a95a435..05e4292 100644
--- a/configs/openrd_client_defconfig
+++ b/configs/openrd_client_defconfig
@@ -12,7 +12,7 @@
CONFIG_BOARD_IS_OPENRD_CLIENT=y
CONFIG_ENV_SIZE=0x20000
CONFIG_ENV_OFFSET=0x80000
-CONFIG_DEFAULT_DEVICE_TREE="kirkwood-openrd-client"
+CONFIG_DEFAULT_DEVICE_TREE="marvell/kirkwood-openrd-client"
CONFIG_IDENT_STRING="\nOpenRD-Client"
CONFIG_SYS_LOAD_ADDR=0x800000
# CONFIG_SYS_MALLOC_F is not set
diff --git a/configs/openrd_ultimate_defconfig b/configs/openrd_ultimate_defconfig
index e3f5294..6e13c6e 100644
--- a/configs/openrd_ultimate_defconfig
+++ b/configs/openrd_ultimate_defconfig
@@ -12,7 +12,7 @@
CONFIG_BOARD_IS_OPENRD_ULTIMATE=y
CONFIG_ENV_SIZE=0x20000
CONFIG_ENV_OFFSET=0x80000
-CONFIG_DEFAULT_DEVICE_TREE="kirkwood-openrd-ultimate"
+CONFIG_DEFAULT_DEVICE_TREE="marvell/kirkwood-openrd-ultimate"
CONFIG_IDENT_STRING="\nOpenRD-Ultimate"
CONFIG_SYS_LOAD_ADDR=0x800000
# CONFIG_SYS_MALLOC_F is not set
diff --git a/configs/orangepi-5-plus-rk3588_defconfig b/configs/orangepi-5-plus-rk3588_defconfig
index a58f96d..d6e23c1 100644
--- a/configs/orangepi-5-plus-rk3588_defconfig
+++ b/configs/orangepi-5-plus-rk3588_defconfig
@@ -3,22 +3,14 @@
CONFIG_SYS_HAS_NONCACHED_MEMORY=y
CONFIG_COUNTER_FREQUENCY=24000000
CONFIG_ARCH_ROCKCHIP=y
-CONFIG_TEXT_BASE=0x00a00000
-CONFIG_SPL_LIBCOMMON_SUPPORT=y
-CONFIG_SPL_LIBGENERIC_SUPPORT=y
CONFIG_NR_DRAM_BANKS=2
-CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y
-CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0xc00000
CONFIG_SF_DEFAULT_SPEED=24000000
CONFIG_SF_DEFAULT_MODE=0x2000
CONFIG_DEFAULT_DEVICE_TREE="rk3588-orangepi-5-plus"
CONFIG_ROCKCHIP_RK3588=y
-CONFIG_SPL_ROCKCHIP_COMMON_BOARD=y
CONFIG_ROCKCHIP_SPI_IMAGE=y
CONFIG_SPL_SERIAL=y
-CONFIG_SPL_STACK_R_ADDR=0x600000
CONFIG_TARGET_EVB_RK3588=y
-CONFIG_SPL_STACK=0x400000
CONFIG_DEBUG_UART_BASE=0xFEB50000
CONFIG_DEBUG_UART_CLOCK=24000000
CONFIG_SPL_SPI_FLASH_SUPPORT=y
@@ -38,12 +30,7 @@
CONFIG_DISPLAY_BOARDINFO_LATE=y
CONFIG_SPL_MAX_SIZE=0x40000
CONFIG_SPL_PAD_TO=0x7f8000
-CONFIG_SPL_HAS_BSS_LINKER_SECTION=y
-CONFIG_SPL_BSS_START_ADDR=0x4000000
-CONFIG_SPL_BSS_MAX_SIZE=0x4000
# CONFIG_SPL_RAW_IMAGE_SUPPORT is not set
-# CONFIG_SPL_SHARES_INIT_SP_ADDR is not set
-CONFIG_SPL_STACK_R=y
CONFIG_SPL_SPI_LOAD=y
CONFIG_SYS_SPI_U_BOOT_OFFS=0x60000
CONFIG_SPL_ATF=y
diff --git a/configs/orangepi-5-rk3588s_defconfig b/configs/orangepi-5-rk3588s_defconfig
index a9404c9..e6b3da1 100644
--- a/configs/orangepi-5-rk3588s_defconfig
+++ b/configs/orangepi-5-rk3588s_defconfig
@@ -2,22 +2,14 @@
CONFIG_SKIP_LOWLEVEL_INIT=y
CONFIG_COUNTER_FREQUENCY=24000000
CONFIG_ARCH_ROCKCHIP=y
-CONFIG_TEXT_BASE=0x00a00000
-CONFIG_SPL_LIBCOMMON_SUPPORT=y
-CONFIG_SPL_LIBGENERIC_SUPPORT=y
CONFIG_NR_DRAM_BANKS=2
-CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y
-CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0xc00000
CONFIG_SF_DEFAULT_SPEED=24000000
CONFIG_SF_DEFAULT_MODE=0x2000
CONFIG_DEFAULT_DEVICE_TREE="rk3588s-orangepi-5"
CONFIG_ROCKCHIP_RK3588=y
-CONFIG_SPL_ROCKCHIP_COMMON_BOARD=y
CONFIG_ROCKCHIP_SPI_IMAGE=y
CONFIG_SPL_SERIAL=y
-CONFIG_SPL_STACK_R_ADDR=0x600000
CONFIG_TARGET_EVB_RK3588=y
-CONFIG_SPL_STACK=0x400000
CONFIG_DEBUG_UART_BASE=0xFEB50000
CONFIG_DEBUG_UART_CLOCK=24000000
CONFIG_SPL_SPI_FLASH_SUPPORT=y
@@ -37,12 +29,7 @@
CONFIG_DISPLAY_BOARDINFO_LATE=y
CONFIG_SPL_MAX_SIZE=0x40000
CONFIG_SPL_PAD_TO=0x7f8000
-CONFIG_SPL_HAS_BSS_LINKER_SECTION=y
-CONFIG_SPL_BSS_START_ADDR=0x4000000
-CONFIG_SPL_BSS_MAX_SIZE=0x4000
# CONFIG_SPL_RAW_IMAGE_SUPPORT is not set
-# CONFIG_SPL_SHARES_INIT_SP_ADDR is not set
-CONFIG_SPL_STACK_R=y
CONFIG_SPL_SPI_LOAD=y
CONFIG_SYS_SPI_U_BOOT_OFFS=0x60000
CONFIG_SPL_ATF=y
diff --git a/configs/orangepi-r1-plus-lts-rk3328_defconfig b/configs/orangepi-r1-plus-lts-rk3328_defconfig
index d3d9417..5fbbd5f 100644
--- a/configs/orangepi-r1-plus-lts-rk3328_defconfig
+++ b/configs/orangepi-r1-plus-lts-rk3328_defconfig
@@ -2,54 +2,47 @@
CONFIG_SKIP_LOWLEVEL_INIT=y
CONFIG_COUNTER_FREQUENCY=24000000
CONFIG_ARCH_ROCKCHIP=y
-CONFIG_TEXT_BASE=0x00200000
CONFIG_SPL_GPIO=y
CONFIG_NR_DRAM_BANKS=1
-CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y
-CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x300000
CONFIG_SF_DEFAULT_SPEED=20000000
CONFIG_ENV_OFFSET=0x3F8000
CONFIG_DEFAULT_DEVICE_TREE="rk3328-orangepi-r1-plus-lts"
CONFIG_DM_RESET=y
CONFIG_ROCKCHIP_RK3328=y
-CONFIG_TPL_ROCKCHIP_COMMON_BOARD=y
-CONFIG_TPL_LIBCOMMON_SUPPORT=y
-CONFIG_TPL_LIBGENERIC_SUPPORT=y
-CONFIG_SPL_DRIVERS_MISC=y
-CONFIG_SPL_STACK_R_ADDR=0x600000
-CONFIG_SPL_STACK=0x400000
-CONFIG_TPL_SYS_MALLOC_F_LEN=0x800
+CONFIG_ROCKCHIP_SPI_IMAGE=y
CONFIG_DEBUG_UART_BASE=0xFF130000
CONFIG_DEBUG_UART_CLOCK=24000000
+CONFIG_SPL_SPI_FLASH_SUPPORT=y
+CONFIG_SPL_SPI=y
CONFIG_SYS_LOAD_ADDR=0x800800
CONFIG_DEBUG_UART=y
# CONFIG_ANDROID_BOOT_IMAGE is not set
CONFIG_FIT=y
CONFIG_FIT_VERBOSE=y
+CONFIG_SPL_FIT_SIGNATURE=y
CONFIG_SPL_LOAD_FIT=y
+CONFIG_LEGACY_IMAGE_FORMAT=y
CONFIG_DEFAULT_FDT_FILE="rockchip/rk3328-orangepi-r1-plus-lts.dtb"
# CONFIG_DISPLAY_CPUINFO is not set
CONFIG_DISPLAY_BOARDINFO_LATE=y
-CONFIG_MISC_INIT_R=y
CONFIG_SPL_MAX_SIZE=0x40000
CONFIG_SPL_PAD_TO=0x7f8000
-CONFIG_SPL_HAS_BSS_LINKER_SECTION=y
-CONFIG_SPL_BSS_START_ADDR=0x2000000
-CONFIG_SPL_BSS_MAX_SIZE=0x2000
# CONFIG_SPL_RAW_IMAGE_SUPPORT is not set
-# CONFIG_SPL_SHARES_INIT_SP_ADDR is not set
-CONFIG_SPL_STACK_R=y
-CONFIG_SPL_I2C=y
CONFIG_SPL_POWER=y
+CONFIG_SPL_SPI_LOAD=y
+CONFIG_SYS_SPI_U_BOOT_OFFS=0x60000
CONFIG_SPL_ATF=y
CONFIG_SPL_ATF_NO_PLATFORM_PARAM=y
-CONFIG_TPL_SYS_MALLOC_SIMPLE=y
CONFIG_CMD_BOOTZ=y
+CONFIG_CMD_GPIO=y
CONFIG_CMD_GPT=y
CONFIG_CMD_MMC=y
CONFIG_CMD_USB=y
+CONFIG_CMD_ROCKUSB=y
+CONFIG_CMD_USB_MASS_STORAGE=y
# CONFIG_CMD_SETEXPR is not set
CONFIG_CMD_TIME=y
+CONFIG_CMD_REGULATOR=y
CONFIG_SPL_OF_CONTROL=y
CONFIG_TPL_OF_CONTROL=y
CONFIG_OF_SPL_REMOVE_PROPS="clock-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents"
@@ -57,8 +50,8 @@
CONFIG_ENV_IS_IN_MMC=y
CONFIG_SYS_RELOC_GD_ENV_ADDR=y
CONFIG_SYS_MMC_ENV_DEV=1
-CONFIG_NET_RANDOM_ETHADDR=y
CONFIG_TPL_DM=y
+CONFIG_SPL_DM_SEQ_ALIAS=y
CONFIG_REGMAP=y
CONFIG_SPL_REGMAP=y
CONFIG_TPL_REGMAP=y
@@ -71,19 +64,27 @@
CONFIG_FASTBOOT_CMD_OEM_FORMAT=y
CONFIG_ROCKCHIP_GPIO=y
CONFIG_SYS_I2C_ROCKCHIP=y
-CONFIG_MISC=y
CONFIG_MMC_DW=y
CONFIG_MMC_DW_ROCKCHIP=y
+CONFIG_SPI_FLASH_SFDP_SUPPORT=y
CONFIG_SPI_FLASH_GIGADEVICE=y
+CONFIG_SPI_FLASH_MACRONIX=y
+CONFIG_SPI_FLASH_WINBOND=y
+CONFIG_SPI_FLASH_XMC=y
+CONFIG_SPI_FLASH_ZBIT=y
+CONFIG_PHY_MOTORCOMM=y
+CONFIG_PHY_REALTEK=y
+CONFIG_DM_MDIO=y
+CONFIG_DM_ETH_PHY=y
+CONFIG_PHY_GIGE=y
CONFIG_ETH_DESIGNWARE=y
CONFIG_GMAC_ROCKCHIP=y
+CONFIG_PHY_ROCKCHIP_INNO_USB2=y
CONFIG_PINCTRL=y
CONFIG_SPL_PINCTRL=y
CONFIG_DM_PMIC=y
CONFIG_PMIC_RK8XX=y
-CONFIG_SPL_PMIC_RK8XX=y
CONFIG_SPL_DM_REGULATOR=y
-CONFIG_REGULATOR_PWM=y
CONFIG_DM_REGULATOR_FIXED=y
CONFIG_SPL_DM_REGULATOR_FIXED=y
CONFIG_REGULATOR_RK8XX=y
@@ -91,6 +92,8 @@
CONFIG_RAM=y
CONFIG_SPL_RAM=y
CONFIG_TPL_RAM=y
+CONFIG_DM_RNG=y
+CONFIG_RNG_ROCKCHIP=y
CONFIG_BAUDRATE=1500000
CONFIG_DEBUG_UART_SHIFT=2
CONFIG_SYS_NS16550_MEM32=y
@@ -99,17 +102,18 @@
CONFIG_SYSRESET=y
# CONFIG_TPL_SYSRESET is not set
CONFIG_USB=y
+CONFIG_DM_USB_GADGET=y
CONFIG_USB_XHCI_HCD=y
+CONFIG_USB_XHCI_DWC3=y
CONFIG_USB_EHCI_HCD=y
CONFIG_USB_EHCI_GENERIC=y
CONFIG_USB_OHCI_HCD=y
CONFIG_USB_OHCI_GENERIC=y
-CONFIG_USB_DWC2=y
CONFIG_USB_DWC3=y
# CONFIG_USB_DWC3_GADGET is not set
-CONFIG_USB_DWC3_GENERIC=y
CONFIG_USB_GADGET=y
CONFIG_USB_GADGET_DWC2_OTG=y
+CONFIG_USB_FUNCTION_ROCKUSB=y
CONFIG_SPL_TINY_MEMSET=y
CONFIG_TPL_TINY_MEMSET=y
CONFIG_ERRNO_STR=y
diff --git a/configs/orangepi-r1-plus-rk3328_defconfig b/configs/orangepi-r1-plus-rk3328_defconfig
index 9356e87..c5afe5e 100644
--- a/configs/orangepi-r1-plus-rk3328_defconfig
+++ b/configs/orangepi-r1-plus-rk3328_defconfig
@@ -2,54 +2,47 @@
CONFIG_SKIP_LOWLEVEL_INIT=y
CONFIG_COUNTER_FREQUENCY=24000000
CONFIG_ARCH_ROCKCHIP=y
-CONFIG_TEXT_BASE=0x00200000
CONFIG_SPL_GPIO=y
CONFIG_NR_DRAM_BANKS=1
-CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y
-CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x300000
CONFIG_SF_DEFAULT_SPEED=20000000
CONFIG_ENV_OFFSET=0x3F8000
CONFIG_DEFAULT_DEVICE_TREE="rk3328-orangepi-r1-plus"
CONFIG_DM_RESET=y
CONFIG_ROCKCHIP_RK3328=y
-CONFIG_TPL_ROCKCHIP_COMMON_BOARD=y
-CONFIG_TPL_LIBCOMMON_SUPPORT=y
-CONFIG_TPL_LIBGENERIC_SUPPORT=y
-CONFIG_SPL_DRIVERS_MISC=y
-CONFIG_SPL_STACK_R_ADDR=0x600000
-CONFIG_SPL_STACK=0x400000
-CONFIG_TPL_SYS_MALLOC_F_LEN=0x800
+CONFIG_ROCKCHIP_SPI_IMAGE=y
CONFIG_DEBUG_UART_BASE=0xFF130000
CONFIG_DEBUG_UART_CLOCK=24000000
+CONFIG_SPL_SPI_FLASH_SUPPORT=y
+CONFIG_SPL_SPI=y
CONFIG_SYS_LOAD_ADDR=0x800800
CONFIG_DEBUG_UART=y
# CONFIG_ANDROID_BOOT_IMAGE is not set
CONFIG_FIT=y
CONFIG_FIT_VERBOSE=y
+CONFIG_SPL_FIT_SIGNATURE=y
CONFIG_SPL_LOAD_FIT=y
+CONFIG_LEGACY_IMAGE_FORMAT=y
CONFIG_DEFAULT_FDT_FILE="rockchip/rk3328-orangepi-r1-plus.dtb"
# CONFIG_DISPLAY_CPUINFO is not set
CONFIG_DISPLAY_BOARDINFO_LATE=y
-CONFIG_MISC_INIT_R=y
CONFIG_SPL_MAX_SIZE=0x40000
CONFIG_SPL_PAD_TO=0x7f8000
-CONFIG_SPL_HAS_BSS_LINKER_SECTION=y
-CONFIG_SPL_BSS_START_ADDR=0x2000000
-CONFIG_SPL_BSS_MAX_SIZE=0x2000
# CONFIG_SPL_RAW_IMAGE_SUPPORT is not set
-# CONFIG_SPL_SHARES_INIT_SP_ADDR is not set
-CONFIG_SPL_STACK_R=y
-CONFIG_SPL_I2C=y
CONFIG_SPL_POWER=y
+CONFIG_SPL_SPI_LOAD=y
+CONFIG_SYS_SPI_U_BOOT_OFFS=0x60000
CONFIG_SPL_ATF=y
CONFIG_SPL_ATF_NO_PLATFORM_PARAM=y
-CONFIG_TPL_SYS_MALLOC_SIMPLE=y
CONFIG_CMD_BOOTZ=y
+CONFIG_CMD_GPIO=y
CONFIG_CMD_GPT=y
CONFIG_CMD_MMC=y
CONFIG_CMD_USB=y
+CONFIG_CMD_ROCKUSB=y
+CONFIG_CMD_USB_MASS_STORAGE=y
# CONFIG_CMD_SETEXPR is not set
CONFIG_CMD_TIME=y
+CONFIG_CMD_REGULATOR=y
CONFIG_SPL_OF_CONTROL=y
CONFIG_TPL_OF_CONTROL=y
CONFIG_OF_SPL_REMOVE_PROPS="clock-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents"
@@ -57,8 +50,8 @@
CONFIG_ENV_IS_IN_MMC=y
CONFIG_SYS_RELOC_GD_ENV_ADDR=y
CONFIG_SYS_MMC_ENV_DEV=1
-CONFIG_NET_RANDOM_ETHADDR=y
CONFIG_TPL_DM=y
+CONFIG_SPL_DM_SEQ_ALIAS=y
CONFIG_REGMAP=y
CONFIG_SPL_REGMAP=y
CONFIG_TPL_REGMAP=y
@@ -71,19 +64,27 @@
CONFIG_FASTBOOT_CMD_OEM_FORMAT=y
CONFIG_ROCKCHIP_GPIO=y
CONFIG_SYS_I2C_ROCKCHIP=y
-CONFIG_MISC=y
CONFIG_MMC_DW=y
CONFIG_MMC_DW_ROCKCHIP=y
+CONFIG_SPI_FLASH_SFDP_SUPPORT=y
CONFIG_SPI_FLASH_GIGADEVICE=y
+CONFIG_SPI_FLASH_MACRONIX=y
+CONFIG_SPI_FLASH_WINBOND=y
+CONFIG_SPI_FLASH_XMC=y
+CONFIG_SPI_FLASH_ZBIT=y
+CONFIG_PHY_MOTORCOMM=y
+CONFIG_PHY_REALTEK=y
+CONFIG_DM_MDIO=y
+CONFIG_DM_ETH_PHY=y
+CONFIG_PHY_GIGE=y
CONFIG_ETH_DESIGNWARE=y
CONFIG_GMAC_ROCKCHIP=y
+CONFIG_PHY_ROCKCHIP_INNO_USB2=y
CONFIG_PINCTRL=y
CONFIG_SPL_PINCTRL=y
CONFIG_DM_PMIC=y
CONFIG_PMIC_RK8XX=y
-CONFIG_SPL_PMIC_RK8XX=y
CONFIG_SPL_DM_REGULATOR=y
-CONFIG_REGULATOR_PWM=y
CONFIG_DM_REGULATOR_FIXED=y
CONFIG_SPL_DM_REGULATOR_FIXED=y
CONFIG_REGULATOR_RK8XX=y
@@ -91,6 +92,8 @@
CONFIG_RAM=y
CONFIG_SPL_RAM=y
CONFIG_TPL_RAM=y
+CONFIG_DM_RNG=y
+CONFIG_RNG_ROCKCHIP=y
CONFIG_BAUDRATE=1500000
CONFIG_DEBUG_UART_SHIFT=2
CONFIG_SYS_NS16550_MEM32=y
@@ -99,17 +102,18 @@
CONFIG_SYSRESET=y
# CONFIG_TPL_SYSRESET is not set
CONFIG_USB=y
+CONFIG_DM_USB_GADGET=y
CONFIG_USB_XHCI_HCD=y
+CONFIG_USB_XHCI_DWC3=y
CONFIG_USB_EHCI_HCD=y
CONFIG_USB_EHCI_GENERIC=y
CONFIG_USB_OHCI_HCD=y
CONFIG_USB_OHCI_GENERIC=y
-CONFIG_USB_DWC2=y
CONFIG_USB_DWC3=y
# CONFIG_USB_DWC3_GADGET is not set
-CONFIG_USB_DWC3_GENERIC=y
CONFIG_USB_GADGET=y
CONFIG_USB_GADGET_DWC2_OTG=y
+CONFIG_USB_FUNCTION_ROCKUSB=y
CONFIG_SPL_TINY_MEMSET=y
CONFIG_TPL_TINY_MEMSET=y
CONFIG_ERRNO_STR=y
diff --git a/configs/orangepi-rk3399_defconfig b/configs/orangepi-rk3399_defconfig
index 27add8a..c6a92b2 100644
--- a/configs/orangepi-rk3399_defconfig
+++ b/configs/orangepi-rk3399_defconfig
@@ -2,15 +2,11 @@
CONFIG_SKIP_LOWLEVEL_INIT=y
CONFIG_COUNTER_FREQUENCY=24000000
CONFIG_ARCH_ROCKCHIP=y
-CONFIG_TEXT_BASE=0x00200000
CONFIG_NR_DRAM_BANKS=1
-CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y
-CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x300000
CONFIG_ENV_OFFSET=0x3F8000
CONFIG_DEFAULT_DEVICE_TREE="rk3399-orangepi"
CONFIG_ROCKCHIP_RK3399=y
CONFIG_TARGET_EVB_RK3399=y
-CONFIG_SPL_STACK=0x400000
CONFIG_DEBUG_UART_BASE=0xFF1A0000
CONFIG_DEBUG_UART_CLOCK=24000000
CONFIG_SYS_LOAD_ADDR=0x800800
@@ -19,13 +15,7 @@
CONFIG_DISPLAY_BOARDINFO_LATE=y
CONFIG_SPL_MAX_SIZE=0x2e000
CONFIG_SPL_PAD_TO=0x7f8000
-CONFIG_SPL_HAS_BSS_LINKER_SECTION=y
-CONFIG_SPL_BSS_START_ADDR=0x400000
-CONFIG_SPL_BSS_MAX_SIZE=0x2000
# CONFIG_SPL_RAW_IMAGE_SUPPORT is not set
-# CONFIG_SPL_SHARES_INIT_SP_ADDR is not set
-CONFIG_SPL_STACK_R=y
-CONFIG_SPL_STACK_R_MALLOC_SIMPLE_LEN=0x10000
CONFIG_SPL_ATF_NO_PLATFORM_PARAM=y
CONFIG_TPL=y
CONFIG_CMD_BOOTZ=y
@@ -40,7 +30,6 @@
CONFIG_SYS_RELOC_GD_ENV_ADDR=y
CONFIG_ROCKCHIP_GPIO=y
CONFIG_SYS_I2C_ROCKCHIP=y
-CONFIG_MISC=y
CONFIG_MMC_DW=y
CONFIG_MMC_DW_ROCKCHIP=y
CONFIG_MMC_SDHCI=y
diff --git a/configs/p212_defconfig b/configs/p212_defconfig
index 6b73607..9cf22ca 100644
--- a/configs/p212_defconfig
+++ b/configs/p212_defconfig
@@ -6,7 +6,7 @@
CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x20000000
CONFIG_ENV_SIZE=0x2000
CONFIG_DM_GPIO=y
-CONFIG_DEFAULT_DEVICE_TREE="meson-gxl-s905x-p212"
+CONFIG_DEFAULT_DEVICE_TREE="amlogic/meson-gxl-s905x-p212"
CONFIG_OF_LIBFDT_OVERLAY=y
CONFIG_DM_RESET=y
CONFIG_MESON_GXL=y
diff --git a/configs/phycore-imx8mp_defconfig b/configs/phycore-imx8mp_defconfig
index b3a7bbd..6c67f14 100644
--- a/configs/phycore-imx8mp_defconfig
+++ b/configs/phycore-imx8mp_defconfig
@@ -19,14 +19,13 @@
CONFIG_SPL_DRIVERS_MISC=y
CONFIG_SPL_STACK=0x960000
CONFIG_SPL=y
+CONFIG_ENV_OFFSET_REDUND=0x3e0000
CONFIG_SPL_IMX_ROMAPI_LOADADDR=0x48000000
CONFIG_SYS_LOAD_ADDR=0x40480000
CONFIG_FIT=y
CONFIG_FIT_EXTERNAL_OFFSET=0x3000
CONFIG_SPL_LOAD_FIT=y
CONFIG_OF_SYSTEM_SETUP=y
-CONFIG_USE_BOOTCOMMAND=y
-CONFIG_BOOTCOMMAND="if test ${dofastboot} = 1; then fastboot 0; fi; mmc dev ${mmcdev}; if mmc rescan; then if run loadimage; then run mmcboot; else run netboot; fi; fi;"
CONFIG_DEFAULT_FDT_FILE="oftree"
CONFIG_SYS_CBSIZE=2048
CONFIG_SYS_PBSIZE=2074
@@ -79,6 +78,7 @@
CONFIG_SPL_OF_CONTROL=y
CONFIG_ENV_OVERWRITE=y
CONFIG_ENV_IS_IN_MMC=y
+CONFIG_SYS_REDUNDAND_ENVIRONMENT=y
CONFIG_SYS_RELOC_GD_ENV_ADDR=y
CONFIG_SYS_MMC_ENV_DEV=2
CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y
diff --git a/configs/phycore_pcl063_defconfig b/configs/phycore_pcl063_defconfig
index 6b00df1..017054a 100644
--- a/configs/phycore_pcl063_defconfig
+++ b/configs/phycore_pcl063_defconfig
@@ -63,7 +63,7 @@
CONFIG_SPL_USB_HOST=y
CONFIG_USB_GADGET=y
CONFIG_USB_GADGET_MANUFACTURER="Phytec"
-CONFIG_USB_GADGET_VENDOR_NUM=0x01b67
+CONFIG_USB_GADGET_VENDOR_NUM=0x1b67
CONFIG_USB_GADGET_PRODUCT_NUM=0x4fff
CONFIG_CI_UDC=y
CONFIG_USB_GADGET_DOWNLOAD=y
diff --git a/configs/phycore_pcl063_ull_defconfig b/configs/phycore_pcl063_ull_defconfig
index 6195fcf..b3da43a 100644
--- a/configs/phycore_pcl063_ull_defconfig
+++ b/configs/phycore_pcl063_ull_defconfig
@@ -54,7 +54,7 @@
CONFIG_SPL_USB_HOST=y
CONFIG_USB_GADGET=y
CONFIG_USB_GADGET_MANUFACTURER="Phytec"
-CONFIG_USB_GADGET_VENDOR_NUM=0x01b67
+CONFIG_USB_GADGET_VENDOR_NUM=0x1b67
CONFIG_USB_GADGET_PRODUCT_NUM=0x4fff
CONFIG_CI_UDC=y
CONFIG_USB_GADGET_DOWNLOAD=y
diff --git a/configs/pinebook-pro-rk3399_defconfig b/configs/pinebook-pro-rk3399_defconfig
index de35741..23ac24a 100644
--- a/configs/pinebook-pro-rk3399_defconfig
+++ b/configs/pinebook-pro-rk3399_defconfig
@@ -2,10 +2,7 @@
CONFIG_SKIP_LOWLEVEL_INIT=y
CONFIG_COUNTER_FREQUENCY=24000000
CONFIG_ARCH_ROCKCHIP=y
-CONFIG_TEXT_BASE=0x00200000
CONFIG_NR_DRAM_BANKS=1
-CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y
-CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x300000
CONFIG_SF_DEFAULT_SPEED=20000000
CONFIG_ENV_SIZE=0x8000
CONFIG_ENV_OFFSET=0x3F8000
@@ -14,7 +11,6 @@
CONFIG_ROCKCHIP_RK3399=y
CONFIG_ROCKCHIP_SPI_IMAGE=y
CONFIG_TARGET_PINEBOOK_PRO_RK3399=y
-CONFIG_SPL_STACK=0x400000
CONFIG_DEBUG_UART_BASE=0xFF1A0000
CONFIG_DEBUG_UART_CLOCK=24000000
CONFIG_SPL_SPI_FLASH_SUPPORT=y
@@ -26,16 +22,9 @@
CONFIG_USE_PREBOOT=y
CONFIG_DEFAULT_FDT_FILE="rockchip/rk3399-pinebook-pro.dtb"
CONFIG_DISPLAY_BOARDINFO_LATE=y
-CONFIG_MISC_INIT_R=y
CONFIG_SPL_MAX_SIZE=0x40000
CONFIG_SPL_PAD_TO=0x7f8000
-CONFIG_SPL_HAS_BSS_LINKER_SECTION=y
-CONFIG_SPL_BSS_START_ADDR=0x400000
-CONFIG_SPL_BSS_MAX_SIZE=0x2000
# CONFIG_SPL_RAW_IMAGE_SUPPORT is not set
-# CONFIG_SPL_SHARES_INIT_SP_ADDR is not set
-CONFIG_SPL_STACK_R=y
-CONFIG_SPL_STACK_R_MALLOC_SIMPLE_LEN=0x10000
CONFIG_SPL_SPI_LOAD=y
CONFIG_SYS_SPI_U_BOOT_OFFS=0xE0000
CONFIG_SPL_ATF_NO_PLATFORM_PARAM=y
@@ -60,8 +49,7 @@
CONFIG_SYS_I2C_ROCKCHIP=y
CONFIG_LED=y
CONFIG_LED_GPIO=y
-CONFIG_MISC=y
-CONFIG_ROCKCHIP_EFUSE=y
+CONFIG_ROCKCHIP_IODOMAIN=y
CONFIG_MMC_IO_VOLTAGE=y
CONFIG_SPL_MMC_IO_VOLTAGE=y
CONFIG_MMC_UHS_SUPPORT=y
diff --git a/configs/pinephone-pro-rk3399_defconfig b/configs/pinephone-pro-rk3399_defconfig
index d08224f..8c6323f 100644
--- a/configs/pinephone-pro-rk3399_defconfig
+++ b/configs/pinephone-pro-rk3399_defconfig
@@ -2,10 +2,7 @@
CONFIG_SKIP_LOWLEVEL_INIT=y
CONFIG_COUNTER_FREQUENCY=24000000
CONFIG_ARCH_ROCKCHIP=y
-CONFIG_TEXT_BASE=0x00200000
CONFIG_NR_DRAM_BANKS=1
-CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y
-CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x300000
CONFIG_SF_DEFAULT_SPEED=20000000
CONFIG_ENV_SIZE=0x8000
CONFIG_ENV_OFFSET=0x3F8000
@@ -14,7 +11,6 @@
CONFIG_ROCKCHIP_RK3399=y
CONFIG_ROCKCHIP_SPI_IMAGE=y
CONFIG_TARGET_PINEPHONE_PRO_RK3399=y
-CONFIG_SPL_STACK=0x400000
CONFIG_DEBUG_UART_BASE=0xFF1A0000
CONFIG_DEBUG_UART_CLOCK=24000000
CONFIG_SPL_SPI_FLASH_SUPPORT=y
@@ -25,16 +21,9 @@
CONFIG_USE_PREBOOT=y
CONFIG_DEFAULT_FDT_FILE="rockchip/rk3399-pinephone-pro.dtb"
CONFIG_DISPLAY_BOARDINFO_LATE=y
-CONFIG_MISC_INIT_R=y
CONFIG_SPL_MAX_SIZE=0x40000
CONFIG_SPL_PAD_TO=0x7f8000
-CONFIG_SPL_HAS_BSS_LINKER_SECTION=y
-CONFIG_SPL_BSS_START_ADDR=0x400000
-CONFIG_SPL_BSS_MAX_SIZE=0x2000
# CONFIG_SPL_RAW_IMAGE_SUPPORT is not set
-# CONFIG_SPL_SHARES_INIT_SP_ADDR is not set
-CONFIG_SPL_STACK_R=y
-CONFIG_SPL_STACK_R_MALLOC_SIMPLE_LEN=0x10000
CONFIG_SPL_SPI_LOAD=y
CONFIG_SYS_SPI_U_BOOT_OFFS=0xE0000
CONFIG_SPL_ATF_NO_PLATFORM_PARAM=y
@@ -59,8 +48,7 @@
CONFIG_SYS_I2C_ROCKCHIP=y
CONFIG_LED=y
CONFIG_LED_GPIO=y
-CONFIG_MISC=y
-CONFIG_ROCKCHIP_EFUSE=y
+CONFIG_ROCKCHIP_IODOMAIN=y
CONFIG_MMC_DW=y
CONFIG_MMC_DW_ROCKCHIP=y
CONFIG_MMC_SDHCI=y
diff --git a/configs/pinetab2-rk3566_defconfig b/configs/pinetab2-rk3566_defconfig
new file mode 100644
index 0000000..bc7a77a
--- /dev/null
+++ b/configs/pinetab2-rk3566_defconfig
@@ -0,0 +1,105 @@
+CONFIG_ARM=y
+CONFIG_SKIP_LOWLEVEL_INIT=y
+CONFIG_COUNTER_FREQUENCY=24000000
+CONFIG_ARCH_ROCKCHIP=y
+CONFIG_SPL_GPIO=y
+CONFIG_NR_DRAM_BANKS=2
+CONFIG_SF_DEFAULT_MODE=0x1000
+CONFIG_DEFAULT_DEVICE_TREE="rk3566-pinetab2-v2.0"
+CONFIG_ROCKCHIP_RK3568=y
+CONFIG_ROCKCHIP_RK8XX_DISABLE_BOOT_ON_POWERON=y
+CONFIG_ROCKCHIP_SPI_IMAGE=y
+CONFIG_SPL_SERIAL=y
+CONFIG_TARGET_QUARTZ64_RK3566=y
+CONFIG_DEBUG_UART_BASE=0xFE660000
+CONFIG_DEBUG_UART_CLOCK=24000000
+CONFIG_SPL_SPI_FLASH_SUPPORT=y
+CONFIG_SPL_SPI=y
+CONFIG_SYS_LOAD_ADDR=0xc00800
+CONFIG_DEBUG_UART=y
+CONFIG_FIT=y
+CONFIG_FIT_VERBOSE=y
+CONFIG_SPL_FIT_SIGNATURE=y
+CONFIG_SPL_LOAD_FIT=y
+CONFIG_LEGACY_IMAGE_FORMAT=y
+CONFIG_DEFAULT_FDT_FILE="rockchip/rk3566-pinetab2-v2.0.dtb"
+# CONFIG_DISPLAY_CPUINFO is not set
+CONFIG_DISPLAY_BOARDINFO_LATE=y
+CONFIG_SPL_MAX_SIZE=0x40000
+CONFIG_SPL_PAD_TO=0x7f8000
+# CONFIG_SPL_RAW_IMAGE_SUPPORT is not set
+CONFIG_SPL_I2C=y
+CONFIG_SPL_POWER=y
+CONFIG_SPL_SPI_LOAD=y
+CONFIG_SYS_SPI_U_BOOT_OFFS=0x60000
+CONFIG_SPL_ATF=y
+CONFIG_CMD_GPIO=y
+CONFIG_CMD_GPT=y
+CONFIG_CMD_I2C=y
+CONFIG_CMD_MMC=y
+CONFIG_CMD_POWEROFF=y
+CONFIG_CMD_USB=y
+CONFIG_CMD_ROCKUSB=y
+CONFIG_CMD_USB_MASS_STORAGE=y
+# CONFIG_CMD_SETEXPR is not set
+CONFIG_CMD_PMIC=y
+CONFIG_CMD_REGULATOR=y
+# CONFIG_SPL_DOS_PARTITION is not set
+CONFIG_SPL_OF_CONTROL=y
+CONFIG_OF_LIVE=y
+CONFIG_OF_LIST="rk3566-pinetab2-v0.1 rk3566-pinetab2-v2.0"
+CONFIG_OF_SPL_REMOVE_PROPS="clock-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents"
+CONFIG_SPL_DM_SEQ_ALIAS=y
+CONFIG_SPL_REGMAP=y
+CONFIG_SPL_SYSCON=y
+CONFIG_BUTTON=y
+CONFIG_BUTTON_ADC=y
+CONFIG_BUTTON_GPIO=y
+CONFIG_SPL_CLK=y
+# CONFIG_USB_FUNCTION_FASTBOOT is not set
+CONFIG_ROCKCHIP_GPIO=y
+CONFIG_SYS_I2C_ROCKCHIP=y
+CONFIG_MISC=y
+CONFIG_SUPPORT_EMMC_RPMB=y
+CONFIG_MMC_DW=y
+CONFIG_MMC_DW_ROCKCHIP=y
+CONFIG_MMC_SDHCI=y
+CONFIG_MMC_SDHCI_SDMA=y
+CONFIG_MMC_SDHCI_ROCKCHIP=y
+CONFIG_SF_DEFAULT_BUS=4
+CONFIG_SPI_FLASH_SFDP_SUPPORT=y
+CONFIG_SPI_FLASH_SILICONKAISER=y
+CONFIG_PHY_ROCKCHIP_INNO_USB2=y
+CONFIG_PHY_ROCKCHIP_NANENG_COMBOPHY=y
+CONFIG_SPL_PINCTRL=y
+CONFIG_DM_PMIC=y
+CONFIG_PMIC_RK8XX=y
+CONFIG_SPL_PMIC_RK8XX=y
+CONFIG_SPL_DM_REGULATOR=y
+CONFIG_SPL_DM_REGULATOR_FIXED=y
+CONFIG_REGULATOR_RK8XX=y
+CONFIG_PWM_ROCKCHIP=y
+CONFIG_SPL_RAM=y
+CONFIG_BAUDRATE=1500000
+CONFIG_DEBUG_UART_SHIFT=2
+CONFIG_SYS_NS16550_MEM32=y
+CONFIG_ROCKCHIP_SFC=y
+CONFIG_SYSRESET=y
+CONFIG_SYSRESET_PSCI=y
+CONFIG_USB=y
+CONFIG_USB_XHCI_HCD=y
+CONFIG_USB_EHCI_HCD=y
+CONFIG_USB_EHCI_GENERIC=y
+CONFIG_USB_OHCI_HCD=y
+CONFIG_USB_OHCI_GENERIC=y
+CONFIG_USB_DWC3=y
+CONFIG_USB_DWC3_GENERIC=y
+CONFIG_USB_HOST_ETHER=y
+CONFIG_USB_ETHER_ASIX=y
+CONFIG_USB_ETHER_ASIX88179=y
+CONFIG_USB_ETHER_RTL8152=y
+CONFIG_USB_GADGET=y
+CONFIG_USB_GADGET_PRODUCT_NUM=0x350a
+CONFIG_USB_GADGET_DOWNLOAD=y
+CONFIG_USB_FUNCTION_ROCKUSB=y
+CONFIG_ERRNO_STR=y
diff --git a/configs/pogo_e02_defconfig b/configs/pogo_e02_defconfig
index e53ccf3..880cb20 100644
--- a/configs/pogo_e02_defconfig
+++ b/configs/pogo_e02_defconfig
@@ -13,7 +13,7 @@
CONFIG_TARGET_POGO_E02=y
CONFIG_ENV_SIZE=0x20000
CONFIG_ENV_OFFSET=0xC0000
-CONFIG_DEFAULT_DEVICE_TREE="kirkwood-pogo_e02"
+CONFIG_DEFAULT_DEVICE_TREE="marvell/kirkwood-pogo_e02"
CONFIG_IDENT_STRING="\nPogo E02"
CONFIG_SYS_LOAD_ADDR=0x800000
CONFIG_BOOTDELAY=3
diff --git a/configs/pogo_v4_defconfig b/configs/pogo_v4_defconfig
index 95e22b3..50046e8 100644
--- a/configs/pogo_v4_defconfig
+++ b/configs/pogo_v4_defconfig
@@ -12,7 +12,7 @@
CONFIG_TARGET_POGO_V4=y
CONFIG_ENV_SIZE=0x20000
CONFIG_ENV_OFFSET=0xC0000
-CONFIG_DEFAULT_DEVICE_TREE="kirkwood-pogoplug-series-4"
+CONFIG_DEFAULT_DEVICE_TREE="marvell/kirkwood-pogoplug-series-4"
CONFIG_IDENT_STRING="\nPogoplug V4"
CONFIG_SYS_LOAD_ADDR=0x800000
CONFIG_PCI=y
diff --git a/configs/puma-rk3399_defconfig b/configs/puma-rk3399_defconfig
index c2aa02e..c2759e1 100644
--- a/configs/puma-rk3399_defconfig
+++ b/configs/puma-rk3399_defconfig
@@ -25,7 +25,6 @@
CONFIG_DEBUG_UART=y
CONFIG_DEFAULT_FDT_FILE="rockchip/rk3399-puma-haikou.dtb"
CONFIG_DISPLAY_BOARDINFO_LATE=y
-CONFIG_MISC_INIT_R=y
CONFIG_SPL_MAX_SIZE=0x2e000
CONFIG_SPL_PAD_TO=0x7f8000
CONFIG_SPL_HAS_BSS_LINKER_SECTION=y
@@ -67,8 +66,7 @@
CONFIG_SPL_GPIO_HOG=y
CONFIG_ROCKCHIP_GPIO=y
CONFIG_SYS_I2C_ROCKCHIP=y
-CONFIG_MISC=y
-CONFIG_ROCKCHIP_EFUSE=y
+CONFIG_ROCKCHIP_IODOMAIN=y
CONFIG_MMC_DW=y
CONFIG_MMC_DW_ROCKCHIP=y
CONFIG_MMC_SDHCI=y
diff --git a/configs/qcom_defconfig b/configs/qcom_defconfig
index 222db64..1abb573 100644
--- a/configs/qcom_defconfig
+++ b/configs/qcom_defconfig
@@ -18,33 +18,58 @@
# CONFIG_DISPLAY_CPUINFO is not set
CONFIG_DISPLAY_BOARDINFO_LATE=y
CONFIG_CMD_BOOTMENU=y
+CONFIG_CMD_EEPROM=y
+CONFIG_SYS_I2C_EEPROM_BUS=2
+CONFIG_SYS_I2C_EEPROM_ADDR_LEN=2
+CONFIG_SYS_EEPROM_PAGE_WRITE_BITS=5
+# CONFIG_CMD_BIND is not set
CONFIG_CMD_CLK=y
CONFIG_CMD_GPIO=y
+CONFIG_CMD_I2C=y
CONFIG_CMD_MMC=y
CONFIG_CMD_UFS=y
CONFIG_CMD_USB=y
CONFIG_CMD_CAT=y
CONFIG_CMD_BMP=y
CONFIG_CMD_LOG=y
-# CONFIG_NET is not set
+CONFIG_OF_LIVE=y
CONFIG_BUTTON_QCOM_PMIC=y
CONFIG_CLK=y
CONFIG_CLK_QCOM_QCS404=y
CONFIG_CLK_QCOM_SDM845=y
CONFIG_MSM_GPIO=y
CONFIG_QCOM_PMIC_GPIO=y
+CONFIG_DM_I2C=y
+CONFIG_SYS_I2C_QUP=y
+CONFIG_I2C_MUX=y
CONFIG_DM_KEYBOARD=y
CONFIG_BUTTON_KEYBOARD=y
+CONFIG_IOMMU=y
+CONFIG_QCOM_HYP_SMMU=y
+CONFIG_MISC=y
+CONFIG_NVMEM=y
+CONFIG_I2C_EEPROM=y
CONFIG_MMC_HS200_SUPPORT=y
CONFIG_MMC_SDHCI=y
CONFIG_MMC_SDHCI_ADMA=y
CONFIG_MMC_SDHCI_MSM=y
+CONFIG_PHY_MICREL=y
+CONFIG_PHY_MICREL_KSZ90X1=y
+CONFIG_DM_MDIO=y
+CONFIG_DM_ETH_PHY=y
+CONFIG_DWC_ETH_QOS=y
+CONFIG_DWC_ETH_QOS_QCOM=y
+CONFIG_RGMII=y
CONFIG_PHY=y
+CONFIG_PHY_QCOM_QUSB2=y
+CONFIG_PHY_QCOM_USB_SNPS_FEMTO_V2=y
CONFIG_PINCTRL=y
CONFIG_PINCTRL_QCOM_QCS404=y
CONFIG_PINCTRL_QCOM_SDM845=y
CONFIG_DM_PMIC=y
CONFIG_PMIC_QCOM=y
+CONFIG_DM_REGULATOR=y
+CONFIG_DM_REGULATOR_FIXED=y
CONFIG_SCSI=y
CONFIG_MSM_SERIAL=y
CONFIG_MSM_GENI_SERIAL=y
@@ -55,6 +80,10 @@
CONFIG_USB_XHCI_HCD=y
CONFIG_USB_XHCI_DWC3=y
CONFIG_USB_DWC3=y
+CONFIG_USB_DWC3_GENERIC=y
+CONFIG_USB_GADGET=y
+CONFIG_USB_GADGET_DOWNLOAD=y
+CONFIG_USB_FUNCTION_MASS_STORAGE=y
CONFIG_UFS=y
CONFIG_VIDEO=y
# CONFIG_VIDEO_FONT_8X16 is not set
diff --git a/configs/qemu-x86_64_defconfig b/configs/qemu-x86_64_defconfig
index 451af0b..008eb46 100644
--- a/configs/qemu-x86_64_defconfig
+++ b/configs/qemu-x86_64_defconfig
@@ -6,7 +6,7 @@
CONFIG_MAX_CPUS=2
CONFIG_SPL_DM_SPI=y
CONFIG_DEFAULT_DEVICE_TREE="qemu-x86_i440fx"
-CONFIG_SPL_TEXT_BASE=0xfffd8000
+CONFIG_SPL_TEXT_BASE=0xfffd4000
CONFIG_SPL_SYS_MALLOC_F_LEN=0x2000
CONFIG_DEBUG_UART_BASE=0x3f8
CONFIG_DEBUG_UART_CLOCK=1843200
@@ -17,7 +17,7 @@
CONFIG_SMP=y
CONFIG_GENERATE_PIRQ_TABLE=y
CONFIG_GENERATE_MP_TABLE=y
-CONFIG_X86_OFFSET_U_BOOT=0xfff00000
+CONFIG_X86_OFFSET_U_BOOT=0xffe00000
CONFIG_SYS_MONITOR_BASE=0x01110000
CONFIG_FIT=y
CONFIG_SPL_LOAD_FIT=y
@@ -80,6 +80,7 @@
CONFIG_SYS_NS16550_PORT_MAPPED=y
CONFIG_SPI=y
CONFIG_USB_KEYBOARD=y
+CONFIG_CONSOLE_TRUETYPE=y
CONFIG_FRAMEBUFFER_SET_VESA_MODE=y
CONFIG_FRAMEBUFFER_VESA_MODE_USER=y
CONFIG_FRAMEBUFFER_VESA_MODE=0x144
diff --git a/configs/qemu-x86_defconfig b/configs/qemu-x86_defconfig
index b2a221b..947d15c 100644
--- a/configs/qemu-x86_defconfig
+++ b/configs/qemu-x86_defconfig
@@ -57,6 +57,7 @@
CONFIG_SYS_NS16550_PORT_MAPPED=y
CONFIG_SPI=y
CONFIG_USB_KEYBOARD=y
+CONFIG_CONSOLE_TRUETYPE=y
CONFIG_FRAMEBUFFER_SET_VESA_MODE=y
CONFIG_FRAMEBUFFER_VESA_MODE_USER=y
CONFIG_FRAMEBUFFER_VESA_MODE=0x144
diff --git a/configs/quartz64-a-rk3566_defconfig b/configs/quartz64-a-rk3566_defconfig
index ade0886..fef8043 100644
--- a/configs/quartz64-a-rk3566_defconfig
+++ b/configs/quartz64-a-rk3566_defconfig
@@ -2,23 +2,15 @@
CONFIG_SKIP_LOWLEVEL_INIT=y
CONFIG_COUNTER_FREQUENCY=24000000
CONFIG_ARCH_ROCKCHIP=y
-CONFIG_TEXT_BASE=0x00a00000
CONFIG_SPL_GPIO=y
-CONFIG_SPL_LIBCOMMON_SUPPORT=y
-CONFIG_SPL_LIBGENERIC_SUPPORT=y
CONFIG_NR_DRAM_BANKS=2
-CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y
-CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0xc00000
CONFIG_SF_DEFAULT_SPEED=24000000
CONFIG_SF_DEFAULT_MODE=0x2000
CONFIG_DEFAULT_DEVICE_TREE="rk3566-quartz64-a"
CONFIG_ROCKCHIP_RK3568=y
-CONFIG_SPL_ROCKCHIP_COMMON_BOARD=y
CONFIG_ROCKCHIP_SPI_IMAGE=y
CONFIG_SPL_SERIAL=y
-CONFIG_SPL_STACK_R_ADDR=0x600000
CONFIG_TARGET_QUARTZ64_RK3566=y
-CONFIG_SPL_STACK=0x400000
CONFIG_DEBUG_UART_BASE=0xFE660000
CONFIG_DEBUG_UART_CLOCK=24000000
CONFIG_SPL_SPI_FLASH_SUPPORT=y
@@ -37,12 +29,7 @@
CONFIG_DISPLAY_BOARDINFO_LATE=y
CONFIG_SPL_MAX_SIZE=0x40000
CONFIG_SPL_PAD_TO=0x7f8000
-CONFIG_SPL_HAS_BSS_LINKER_SECTION=y
-CONFIG_SPL_BSS_START_ADDR=0x4000000
-CONFIG_SPL_BSS_MAX_SIZE=0x4000
# CONFIG_SPL_RAW_IMAGE_SUPPORT is not set
-# CONFIG_SPL_SHARES_INIT_SP_ADDR is not set
-CONFIG_SPL_STACK_R=y
CONFIG_SPL_POWER=y
CONFIG_SPL_SPI_LOAD=y
CONFIG_SYS_SPI_U_BOOT_OFFS=0x60000
diff --git a/configs/quartz64-b-rk3566_defconfig b/configs/quartz64-b-rk3566_defconfig
index 8d01db5..bb541ed 100644
--- a/configs/quartz64-b-rk3566_defconfig
+++ b/configs/quartz64-b-rk3566_defconfig
@@ -2,22 +2,14 @@
CONFIG_SKIP_LOWLEVEL_INIT=y
CONFIG_COUNTER_FREQUENCY=24000000
CONFIG_ARCH_ROCKCHIP=y
-CONFIG_TEXT_BASE=0x00a00000
-CONFIG_SPL_LIBCOMMON_SUPPORT=y
-CONFIG_SPL_LIBGENERIC_SUPPORT=y
CONFIG_NR_DRAM_BANKS=2
-CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y
-CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0xc00000
CONFIG_SF_DEFAULT_SPEED=24000000
CONFIG_SF_DEFAULT_MODE=0x2000
CONFIG_DEFAULT_DEVICE_TREE="rk3566-quartz64-b"
CONFIG_ROCKCHIP_RK3568=y
-CONFIG_SPL_ROCKCHIP_COMMON_BOARD=y
CONFIG_ROCKCHIP_SPI_IMAGE=y
CONFIG_SPL_SERIAL=y
-CONFIG_SPL_STACK_R_ADDR=0x600000
CONFIG_TARGET_QUARTZ64_RK3566=y
-CONFIG_SPL_STACK=0x400000
CONFIG_DEBUG_UART_BASE=0xFE660000
CONFIG_DEBUG_UART_CLOCK=24000000
CONFIG_SPL_SPI_FLASH_SUPPORT=y
@@ -36,12 +28,7 @@
CONFIG_DISPLAY_BOARDINFO_LATE=y
CONFIG_SPL_MAX_SIZE=0x40000
CONFIG_SPL_PAD_TO=0x7f8000
-CONFIG_SPL_HAS_BSS_LINKER_SECTION=y
-CONFIG_SPL_BSS_START_ADDR=0x4000000
-CONFIG_SPL_BSS_MAX_SIZE=0x4000
# CONFIG_SPL_RAW_IMAGE_SUPPORT is not set
-# CONFIG_SPL_SHARES_INIT_SP_ADDR is not set
-CONFIG_SPL_STACK_R=y
CONFIG_SPL_SPI_LOAD=y
CONFIG_SYS_SPI_U_BOOT_OFFS=0x60000
CONFIG_SPL_ATF=y
diff --git a/configs/quartzpro64-rk3588_defconfig b/configs/quartzpro64-rk3588_defconfig
index 9cc4eb0..b2a66d3 100644
--- a/configs/quartzpro64-rk3588_defconfig
+++ b/configs/quartzpro64-rk3588_defconfig
@@ -3,19 +3,11 @@
CONFIG_SYS_HAS_NONCACHED_MEMORY=y
CONFIG_COUNTER_FREQUENCY=24000000
CONFIG_ARCH_ROCKCHIP=y
-CONFIG_TEXT_BASE=0x00a00000
-CONFIG_SPL_LIBCOMMON_SUPPORT=y
-CONFIG_SPL_LIBGENERIC_SUPPORT=y
CONFIG_NR_DRAM_BANKS=2
-CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y
-CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0xc00000
CONFIG_DEFAULT_DEVICE_TREE="rk3588-quartzpro64"
CONFIG_ROCKCHIP_RK3588=y
-CONFIG_SPL_ROCKCHIP_COMMON_BOARD=y
CONFIG_SPL_SERIAL=y
-CONFIG_SPL_STACK_R_ADDR=0x600000
CONFIG_TARGET_QUARTZPRO64_RK3588=y
-CONFIG_SPL_STACK=0x400000
CONFIG_DEBUG_UART_BASE=0xFEB50000
CONFIG_DEBUG_UART_CLOCK=24000000
CONFIG_SYS_LOAD_ADDR=0xc00800
@@ -33,12 +25,7 @@
CONFIG_DISPLAY_BOARDINFO_LATE=y
CONFIG_SPL_MAX_SIZE=0x40000
CONFIG_SPL_PAD_TO=0x7f8000
-CONFIG_SPL_HAS_BSS_LINKER_SECTION=y
-CONFIG_SPL_BSS_START_ADDR=0x4000000
-CONFIG_SPL_BSS_MAX_SIZE=0x4000
# CONFIG_SPL_RAW_IMAGE_SUPPORT is not set
-# CONFIG_SPL_SHARES_INIT_SP_ADDR is not set
-CONFIG_SPL_STACK_R=y
CONFIG_SPL_ATF=y
CONFIG_CMD_GPIO=y
CONFIG_CMD_GPT=y
diff --git a/configs/radxa-cm3-io-rk3566_defconfig b/configs/radxa-cm3-io-rk3566_defconfig
index 4b606dc..bf61db4 100644
--- a/configs/radxa-cm3-io-rk3566_defconfig
+++ b/configs/radxa-cm3-io-rk3566_defconfig
@@ -2,18 +2,10 @@
CONFIG_SKIP_LOWLEVEL_INIT=y
CONFIG_COUNTER_FREQUENCY=24000000
CONFIG_ARCH_ROCKCHIP=y
-CONFIG_TEXT_BASE=0x00a00000
-CONFIG_SPL_LIBCOMMON_SUPPORT=y
-CONFIG_SPL_LIBGENERIC_SUPPORT=y
CONFIG_NR_DRAM_BANKS=2
-CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y
-CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0xc00000
CONFIG_DEFAULT_DEVICE_TREE="rk3566-radxa-cm3-io"
CONFIG_ROCKCHIP_RK3568=y
-CONFIG_SPL_ROCKCHIP_COMMON_BOARD=y
CONFIG_SPL_SERIAL=y
-CONFIG_SPL_STACK_R_ADDR=0x600000
-CONFIG_SPL_STACK=0x400000
CONFIG_DEBUG_UART_BASE=0xFE660000
CONFIG_DEBUG_UART_CLOCK=24000000
CONFIG_SYS_LOAD_ADDR=0xc00800
@@ -28,12 +20,7 @@
CONFIG_DISPLAY_BOARDINFO_LATE=y
CONFIG_SPL_MAX_SIZE=0x40000
CONFIG_SPL_PAD_TO=0x7f8000
-CONFIG_SPL_HAS_BSS_LINKER_SECTION=y
-CONFIG_SPL_BSS_START_ADDR=0x4000000
-CONFIG_SPL_BSS_MAX_SIZE=0x4000
# CONFIG_SPL_RAW_IMAGE_SUPPORT is not set
-# CONFIG_SPL_SHARES_INIT_SP_ADDR is not set
-CONFIG_SPL_STACK_R=y
CONFIG_SPL_ATF=y
CONFIG_CMD_GPIO=y
CONFIG_CMD_GPT=y
diff --git a/configs/radxa-e25-rk3568_defconfig b/configs/radxa-e25-rk3568_defconfig
index fedb137..43aa8ec 100644
--- a/configs/radxa-e25-rk3568_defconfig
+++ b/configs/radxa-e25-rk3568_defconfig
@@ -3,18 +3,10 @@
CONFIG_SYS_HAS_NONCACHED_MEMORY=y
CONFIG_COUNTER_FREQUENCY=24000000
CONFIG_ARCH_ROCKCHIP=y
-CONFIG_TEXT_BASE=0x00a00000
-CONFIG_SPL_LIBCOMMON_SUPPORT=y
-CONFIG_SPL_LIBGENERIC_SUPPORT=y
CONFIG_NR_DRAM_BANKS=2
-CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y
-CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0xc00000
CONFIG_DEFAULT_DEVICE_TREE="rk3568-radxa-e25"
CONFIG_ROCKCHIP_RK3568=y
-CONFIG_SPL_ROCKCHIP_COMMON_BOARD=y
CONFIG_SPL_SERIAL=y
-CONFIG_SPL_STACK_R_ADDR=0x600000
-CONFIG_SPL_STACK=0x400000
CONFIG_DEBUG_UART_BASE=0xFE660000
CONFIG_DEBUG_UART_CLOCK=24000000
CONFIG_SYS_LOAD_ADDR=0xc00800
@@ -31,12 +23,7 @@
CONFIG_DISPLAY_BOARDINFO_LATE=y
CONFIG_SPL_MAX_SIZE=0x40000
CONFIG_SPL_PAD_TO=0x7f8000
-CONFIG_SPL_HAS_BSS_LINKER_SECTION=y
-CONFIG_SPL_BSS_START_ADDR=0x4000000
-CONFIG_SPL_BSS_MAX_SIZE=0x4000
# CONFIG_SPL_RAW_IMAGE_SUPPORT is not set
-# CONFIG_SPL_SHARES_INIT_SP_ADDR is not set
-CONFIG_SPL_STACK_R=y
CONFIG_SPL_ATF=y
CONFIG_CMD_GPIO=y
CONFIG_CMD_GPT=y
diff --git a/configs/radxa-zero2_defconfig b/configs/radxa-zero2_defconfig
index b795681..92e0a88 100644
--- a/configs/radxa-zero2_defconfig
+++ b/configs/radxa-zero2_defconfig
@@ -6,7 +6,7 @@
CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x20000000
CONFIG_ENV_SIZE=0x2000
CONFIG_DM_GPIO=y
-CONFIG_DEFAULT_DEVICE_TREE="meson-g12b-radxa-zero2"
+CONFIG_DEFAULT_DEVICE_TREE="amlogic/meson-g12b-radxa-zero2"
CONFIG_OF_LIBFDT_OVERLAY=y
CONFIG_DM_RESET=y
CONFIG_MESON_G12A=y
diff --git a/configs/radxa-zero_defconfig b/configs/radxa-zero_defconfig
index 103ff8a..5179c58 100644
--- a/configs/radxa-zero_defconfig
+++ b/configs/radxa-zero_defconfig
@@ -6,7 +6,7 @@
CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x20000000
CONFIG_ENV_SIZE=0x2000
CONFIG_DM_GPIO=y
-CONFIG_DEFAULT_DEVICE_TREE="meson-g12a-radxa-zero"
+CONFIG_DEFAULT_DEVICE_TREE="amlogic/meson-g12a-radxa-zero"
CONFIG_OF_LIBFDT_OVERLAY=y
CONFIG_DM_RESET=y
CONFIG_MESON_G12A=y
diff --git a/configs/roc-cc-rk3308_defconfig b/configs/roc-cc-rk3308_defconfig
index 7502da5..5e8f51e 100644
--- a/configs/roc-cc-rk3308_defconfig
+++ b/configs/roc-cc-rk3308_defconfig
@@ -2,19 +2,11 @@
CONFIG_SKIP_LOWLEVEL_INIT=y
CONFIG_COUNTER_FREQUENCY=24000000
CONFIG_ARCH_ROCKCHIP=y
-CONFIG_TEXT_BASE=0x00600000
-CONFIG_SYS_MALLOC_F_LEN=0x2000
-CONFIG_SPL_LIBCOMMON_SUPPORT=y
-CONFIG_SPL_LIBGENERIC_SUPPORT=y
-CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y
-CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x800000
CONFIG_DEFAULT_DEVICE_TREE="rk3308-roc-cc"
CONFIG_DM_RESET=y
CONFIG_ROCKCHIP_RK3308=y
CONFIG_SPL_DRIVERS_MISC=y
CONFIG_TARGET_ROC_RK3308_CC=y
-CONFIG_SPL_STACK_R_ADDR=0xc00000
-CONFIG_SPL_STACK=0x400000
CONFIG_DEBUG_UART_BASE=0xFF0C0000
CONFIG_DEBUG_UART_CLOCK=24000000
CONFIG_SYS_LOAD_ADDR=0xc00800
@@ -28,11 +20,6 @@
# CONFIG_DISPLAY_CPUINFO is not set
CONFIG_SPL_MAX_SIZE=0x20000
CONFIG_SPL_PAD_TO=0x7f8000
-CONFIG_SPL_HAS_BSS_LINKER_SECTION=y
-CONFIG_SPL_BSS_START_ADDR=0x400000
-CONFIG_SPL_BSS_MAX_SIZE=0x2000
-# CONFIG_SPL_SHARES_INIT_SP_ADDR is not set
-CONFIG_SPL_STACK_R=y
# CONFIG_CMD_BDI is not set
# CONFIG_CMD_CONSOLE is not set
# CONFIG_CMD_ELF is not set
diff --git a/configs/roc-cc-rk3328_defconfig b/configs/roc-cc-rk3328_defconfig
index 4ac3c94..6526d26 100644
--- a/configs/roc-cc-rk3328_defconfig
+++ b/configs/roc-cc-rk3328_defconfig
@@ -2,55 +2,40 @@
CONFIG_SKIP_LOWLEVEL_INIT=y
CONFIG_COUNTER_FREQUENCY=24000000
CONFIG_ARCH_ROCKCHIP=y
-CONFIG_TEXT_BASE=0x00200000
CONFIG_SPL_GPIO=y
CONFIG_NR_DRAM_BANKS=1
-CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y
-CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x300000
CONFIG_SF_DEFAULT_SPEED=20000000
CONFIG_ENV_OFFSET=0x3F8000
CONFIG_DEFAULT_DEVICE_TREE="rk3328-roc-cc"
CONFIG_DM_RESET=y
CONFIG_ROCKCHIP_RK3328=y
-CONFIG_TPL_ROCKCHIP_COMMON_BOARD=y
-CONFIG_TPL_LIBCOMMON_SUPPORT=y
-CONFIG_TPL_LIBGENERIC_SUPPORT=y
-CONFIG_SPL_DRIVERS_MISC=y
-CONFIG_SPL_STACK_R_ADDR=0x600000
-CONFIG_SPL_STACK=0x400000
-CONFIG_TPL_SYS_MALLOC_F_LEN=0x800
CONFIG_DEBUG_UART_BASE=0xFF130000
CONFIG_DEBUG_UART_CLOCK=24000000
CONFIG_SYS_LOAD_ADDR=0x800800
CONFIG_DEBUG_UART=y
-# CONFIG_ANDROID_BOOT_IMAGE is not set
CONFIG_FIT=y
CONFIG_FIT_VERBOSE=y
+CONFIG_SPL_FIT_SIGNATURE=y
CONFIG_SPL_LOAD_FIT=y
+CONFIG_LEGACY_IMAGE_FORMAT=y
CONFIG_DEFAULT_FDT_FILE="rockchip/rk3328-roc-cc.dtb"
# CONFIG_DISPLAY_CPUINFO is not set
CONFIG_DISPLAY_BOARDINFO_LATE=y
-CONFIG_MISC_INIT_R=y
CONFIG_SPL_MAX_SIZE=0x40000
CONFIG_SPL_PAD_TO=0x7f8000
-CONFIG_SPL_HAS_BSS_LINKER_SECTION=y
-CONFIG_SPL_BSS_START_ADDR=0x2000000
-CONFIG_SPL_BSS_MAX_SIZE=0x2000
# CONFIG_SPL_RAW_IMAGE_SUPPORT is not set
-# CONFIG_SPL_SHARES_INIT_SP_ADDR is not set
-CONFIG_SPL_STACK_R=y
-CONFIG_SPL_I2C=y
CONFIG_SPL_POWER=y
CONFIG_SPL_ATF=y
CONFIG_SPL_ATF_NO_PLATFORM_PARAM=y
-CONFIG_TPL_SYS_MALLOC_SIMPLE=y
CONFIG_CMD_BOOTZ=y
+CONFIG_CMD_GPIO=y
CONFIG_CMD_GPT=y
CONFIG_CMD_MMC=y
+CONFIG_CMD_POWEROFF=y
CONFIG_CMD_USB=y
-CONFIG_CMD_USB_MASS_STORAGE=y
# CONFIG_CMD_SETEXPR is not set
CONFIG_CMD_TIME=y
+CONFIG_CMD_REGULATOR=y
CONFIG_SPL_OF_CONTROL=y
CONFIG_TPL_OF_CONTROL=y
CONFIG_OF_SPL_REMOVE_PROPS="clock-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents"
@@ -58,8 +43,8 @@
CONFIG_ENV_IS_IN_MMC=y
CONFIG_SYS_RELOC_GD_ENV_ADDR=y
CONFIG_SYS_MMC_ENV_DEV=1
-CONFIG_NET_RANDOM_ETHADDR=y
CONFIG_TPL_DM=y
+CONFIG_SPL_DM_SEQ_ALIAS=y
CONFIG_REGMAP=y
CONFIG_SPL_REGMAP=y
CONFIG_TPL_REGMAP=y
@@ -68,14 +53,12 @@
CONFIG_TPL_SYSCON=y
CONFIG_CLK=y
CONFIG_SPL_CLK=y
-CONFIG_FASTBOOT_BUF_ADDR=0x800800
-CONFIG_FASTBOOT_CMD_OEM_FORMAT=y
CONFIG_ROCKCHIP_GPIO=y
CONFIG_SYS_I2C_ROCKCHIP=y
-CONFIG_MISC=y
CONFIG_MMC_DW=y
CONFIG_MMC_DW_ROCKCHIP=y
CONFIG_PHY_REALTEK=y
+CONFIG_DM_ETH_PHY=y
CONFIG_PHY_GIGE=y
CONFIG_ETH_DESIGNWARE=y
CONFIG_GMAC_ROCKCHIP=y
@@ -84,9 +67,7 @@
CONFIG_SPL_PINCTRL=y
CONFIG_DM_PMIC=y
CONFIG_PMIC_RK8XX=y
-CONFIG_SPL_PMIC_RK8XX=y
CONFIG_SPL_DM_REGULATOR=y
-CONFIG_REGULATOR_PWM=y
CONFIG_DM_REGULATOR_FIXED=y
CONFIG_SPL_DM_REGULATOR_FIXED=y
CONFIG_DM_REGULATOR_GPIO=y
@@ -95,6 +76,8 @@
CONFIG_RAM=y
CONFIG_SPL_RAM=y
CONFIG_TPL_RAM=y
+CONFIG_DM_RNG=y
+CONFIG_RNG_ROCKCHIP=y
CONFIG_BAUDRATE=1500000
CONFIG_DEBUG_UART_SHIFT=2
CONFIG_SYS_NS16550_MEM32=y
@@ -110,10 +93,7 @@
CONFIG_USB_OHCI_GENERIC=y
CONFIG_USB_DWC2=y
CONFIG_USB_DWC3=y
-# CONFIG_USB_DWC3_GADGET is not set
CONFIG_USB_DWC3_GENERIC=y
-CONFIG_USB_GADGET=y
-CONFIG_USB_GADGET_DWC2_OTG=y
CONFIG_SPL_TINY_MEMSET=y
CONFIG_TPL_TINY_MEMSET=y
CONFIG_ERRNO_STR=y
diff --git a/configs/roc-pc-mezzanine-rk3399_defconfig b/configs/roc-pc-mezzanine-rk3399_defconfig
index de6539b..1ff4e15 100644
--- a/configs/roc-pc-mezzanine-rk3399_defconfig
+++ b/configs/roc-pc-mezzanine-rk3399_defconfig
@@ -2,11 +2,8 @@
CONFIG_SKIP_LOWLEVEL_INIT=y
CONFIG_COUNTER_FREQUENCY=24000000
CONFIG_ARCH_ROCKCHIP=y
-CONFIG_TEXT_BASE=0x00200000
CONFIG_SPL_GPIO=y
CONFIG_NR_DRAM_BANKS=1
-CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y
-CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x300000
CONFIG_ENV_SIZE=0x8000
CONFIG_ENV_OFFSET=0x3F8000
CONFIG_ENV_SECT_SIZE=0x1000
@@ -15,7 +12,6 @@
CONFIG_ROCKCHIP_RK3399=y
CONFIG_ROCKCHIP_SPI_IMAGE=y
CONFIG_TARGET_ROC_PC_RK3399=y
-CONFIG_SPL_STACK=0x400000
CONFIG_DEBUG_UART_BASE=0xFF1A0000
CONFIG_DEBUG_UART_CLOCK=24000000
CONFIG_SPL_SPI_FLASH_SUPPORT=y
@@ -26,16 +22,9 @@
# CONFIG_ANDROID_BOOT_IMAGE is not set
CONFIG_DEFAULT_FDT_FILE="rockchip/rk3399-roc-pc-mezzanine.dtb"
CONFIG_DISPLAY_BOARDINFO_LATE=y
-CONFIG_MISC_INIT_R=y
CONFIG_SPL_MAX_SIZE=0x40000
CONFIG_SPL_PAD_TO=0x7f8000
-CONFIG_SPL_HAS_BSS_LINKER_SECTION=y
-CONFIG_SPL_BSS_START_ADDR=0x400000
-CONFIG_SPL_BSS_MAX_SIZE=0x2000
# CONFIG_SPL_RAW_IMAGE_SUPPORT is not set
-# CONFIG_SPL_SHARES_INIT_SP_ADDR is not set
-CONFIG_SPL_STACK_R=y
-CONFIG_SPL_STACK_R_MALLOC_SIMPLE_LEN=0x20000
CONFIG_SPL_ENV_SUPPORT=y
CONFIG_SPL_SPI_LOAD=y
CONFIG_SYS_SPI_U_BOOT_OFFS=0xE0000
@@ -55,8 +44,6 @@
CONFIG_SPL_DM_SEQ_ALIAS=y
CONFIG_ROCKCHIP_GPIO=y
CONFIG_SYS_I2C_ROCKCHIP=y
-CONFIG_MISC=y
-CONFIG_ROCKCHIP_EFUSE=y
CONFIG_MMC_DW=y
CONFIG_MMC_DW_ROCKCHIP=y
CONFIG_MMC_SDHCI=y
diff --git a/configs/roc-pc-rk3399_defconfig b/configs/roc-pc-rk3399_defconfig
index 7123a7a..a41f71d 100644
--- a/configs/roc-pc-rk3399_defconfig
+++ b/configs/roc-pc-rk3399_defconfig
@@ -2,11 +2,8 @@
CONFIG_SKIP_LOWLEVEL_INIT=y
CONFIG_COUNTER_FREQUENCY=24000000
CONFIG_ARCH_ROCKCHIP=y
-CONFIG_TEXT_BASE=0x00200000
CONFIG_SPL_GPIO=y
CONFIG_NR_DRAM_BANKS=1
-CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y
-CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x300000
CONFIG_SF_DEFAULT_SPEED=30000000
CONFIG_ENV_SIZE=0x8000
CONFIG_ENV_OFFSET=0x3F8000
@@ -16,7 +13,6 @@
CONFIG_ROCKCHIP_RK3399=y
CONFIG_ROCKCHIP_SPI_IMAGE=y
CONFIG_TARGET_ROC_PC_RK3399=y
-CONFIG_SPL_STACK=0x400000
CONFIG_DEBUG_UART_BASE=0xFF1A0000
CONFIG_DEBUG_UART_CLOCK=24000000
CONFIG_SPL_SPI_FLASH_SUPPORT=y
@@ -27,16 +23,9 @@
CONFIG_USE_PREBOOT=y
CONFIG_DEFAULT_FDT_FILE="rockchip/rk3399-roc-pc.dtb"
CONFIG_DISPLAY_BOARDINFO_LATE=y
-CONFIG_MISC_INIT_R=y
CONFIG_SPL_MAX_SIZE=0x40000
CONFIG_SPL_PAD_TO=0x7f8000
-CONFIG_SPL_HAS_BSS_LINKER_SECTION=y
-CONFIG_SPL_BSS_START_ADDR=0x400000
-CONFIG_SPL_BSS_MAX_SIZE=0x2000
# CONFIG_SPL_RAW_IMAGE_SUPPORT is not set
-# CONFIG_SPL_SHARES_INIT_SP_ADDR is not set
-CONFIG_SPL_STACK_R=y
-CONFIG_SPL_STACK_R_MALLOC_SIMPLE_LEN=0x20000
CONFIG_SPL_ENV_SUPPORT=y
CONFIG_SPL_SPI_LOAD=y
CONFIG_SYS_SPI_U_BOOT_OFFS=0xE0000
@@ -55,8 +44,6 @@
CONFIG_SPL_DM_SEQ_ALIAS=y
CONFIG_ROCKCHIP_GPIO=y
CONFIG_SYS_I2C_ROCKCHIP=y
-CONFIG_MISC=y
-CONFIG_ROCKCHIP_EFUSE=y
CONFIG_MMC_DW=y
CONFIG_MMC_DW_ROCKCHIP=y
CONFIG_MMC_SDHCI=y
diff --git a/configs/rock-3a-rk3568_defconfig b/configs/rock-3a-rk3568_defconfig
index 18372a5..c161bc9 100644
--- a/configs/rock-3a-rk3568_defconfig
+++ b/configs/rock-3a-rk3568_defconfig
@@ -2,21 +2,13 @@
CONFIG_SKIP_LOWLEVEL_INIT=y
CONFIG_COUNTER_FREQUENCY=24000000
CONFIG_ARCH_ROCKCHIP=y
-CONFIG_TEXT_BASE=0x00a00000
-CONFIG_SPL_LIBCOMMON_SUPPORT=y
-CONFIG_SPL_LIBGENERIC_SUPPORT=y
CONFIG_NR_DRAM_BANKS=2
-CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y
-CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0xc00000
CONFIG_SF_DEFAULT_SPEED=24000000
CONFIG_SF_DEFAULT_MODE=0x2000
CONFIG_DEFAULT_DEVICE_TREE="rk3568-rock-3a"
CONFIG_ROCKCHIP_RK3568=y
-CONFIG_SPL_ROCKCHIP_COMMON_BOARD=y
CONFIG_ROCKCHIP_SPI_IMAGE=y
CONFIG_SPL_SERIAL=y
-CONFIG_SPL_STACK_R_ADDR=0x600000
-CONFIG_SPL_STACK=0x400000
CONFIG_DEBUG_UART_BASE=0xFE660000
CONFIG_DEBUG_UART_CLOCK=24000000
CONFIG_SPL_SPI_FLASH_SUPPORT=y
@@ -35,12 +27,7 @@
CONFIG_DISPLAY_BOARDINFO_LATE=y
CONFIG_SPL_MAX_SIZE=0x40000
CONFIG_SPL_PAD_TO=0x7f8000
-CONFIG_SPL_HAS_BSS_LINKER_SECTION=y
-CONFIG_SPL_BSS_START_ADDR=0x4000000
-CONFIG_SPL_BSS_MAX_SIZE=0x4000
# CONFIG_SPL_RAW_IMAGE_SUPPORT is not set
-# CONFIG_SPL_SHARES_INIT_SP_ADDR is not set
-CONFIG_SPL_STACK_R=y
CONFIG_SPL_SPI_LOAD=y
CONFIG_SYS_SPI_U_BOOT_OFFS=0x60000
CONFIG_SPL_ATF=y
diff --git a/configs/rock-4c-plus-rk3399_defconfig b/configs/rock-4c-plus-rk3399_defconfig
index 18525c8..bebea4f 100644
--- a/configs/rock-4c-plus-rk3399_defconfig
+++ b/configs/rock-4c-plus-rk3399_defconfig
@@ -2,17 +2,13 @@
CONFIG_SKIP_LOWLEVEL_INIT=y
CONFIG_COUNTER_FREQUENCY=24000000
CONFIG_ARCH_ROCKCHIP=y
-CONFIG_TEXT_BASE=0x00200000
CONFIG_NR_DRAM_BANKS=1
-CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y
-CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x300000
CONFIG_ENV_OFFSET=0x3F8000
CONFIG_DEFAULT_DEVICE_TREE="rk3399-rock-4c-plus"
CONFIG_OF_LIBFDT_OVERLAY=y
CONFIG_DM_RESET=y
CONFIG_ROCKCHIP_RK3399=y
-CONFIG_TARGET_EVB_RK3399=y
-CONFIG_SPL_STACK=0x400000
+CONFIG_TARGET_ROCKPI4_RK3399=y
CONFIG_DEBUG_UART_BASE=0xFF1A0000
CONFIG_DEBUG_UART_CLOCK=24000000
CONFIG_SYS_LOAD_ADDR=0x800800
@@ -21,16 +17,9 @@
# CONFIG_ANDROID_BOOT_IMAGE is not set
CONFIG_DEFAULT_FDT_FILE="rockchip/rk3399-rock-4c-plus.dtb"
CONFIG_DISPLAY_BOARDINFO_LATE=y
-CONFIG_MISC_INIT_R=y
CONFIG_SPL_MAX_SIZE=0x2e000
CONFIG_SPL_PAD_TO=0x7f8000
-CONFIG_SPL_HAS_BSS_LINKER_SECTION=y
-CONFIG_SPL_BSS_START_ADDR=0x400000
-CONFIG_SPL_BSS_MAX_SIZE=0x2000
# CONFIG_SPL_RAW_IMAGE_SUPPORT is not set
-# CONFIG_SPL_SHARES_INIT_SP_ADDR is not set
-CONFIG_SPL_STACK_R=y
-CONFIG_SPL_STACK_R_MALLOC_SIMPLE_LEN=0x10000
CONFIG_SPL_ATF_NO_PLATFORM_PARAM=y
CONFIG_TPL=y
CONFIG_CMD_BOOTZ=y
@@ -52,8 +41,6 @@
CONFIG_DFU_MMC=y
CONFIG_ROCKCHIP_GPIO=y
CONFIG_SYS_I2C_ROCKCHIP=y
-CONFIG_MISC=y
-CONFIG_ROCKCHIP_EFUSE=y
CONFIG_MMC_DW=y
CONFIG_MMC_DW_ROCKCHIP=y
CONFIG_MMC_SDHCI=y
diff --git a/configs/rock-4se-rk3399_defconfig b/configs/rock-4se-rk3399_defconfig
index 171de23..7125025 100644
--- a/configs/rock-4se-rk3399_defconfig
+++ b/configs/rock-4se-rk3399_defconfig
@@ -2,17 +2,13 @@
CONFIG_SKIP_LOWLEVEL_INIT=y
CONFIG_COUNTER_FREQUENCY=24000000
CONFIG_ARCH_ROCKCHIP=y
-CONFIG_TEXT_BASE=0x00200000
CONFIG_NR_DRAM_BANKS=1
-CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y
-CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x300000
CONFIG_ENV_OFFSET=0x3F8000
CONFIG_DEFAULT_DEVICE_TREE="rk3399-rock-4se"
CONFIG_OF_LIBFDT_OVERLAY=y
CONFIG_DM_RESET=y
CONFIG_ROCKCHIP_RK3399=y
-CONFIG_TARGET_EVB_RK3399=y
-CONFIG_SPL_STACK=0x400000
+CONFIG_TARGET_ROCKPI4_RK3399=y
CONFIG_DEBUG_UART_BASE=0xFF1A0000
CONFIG_DEBUG_UART_CLOCK=24000000
CONFIG_SYS_LOAD_ADDR=0x800800
@@ -23,16 +19,9 @@
CONFIG_LEGACY_IMAGE_FORMAT=y
CONFIG_DEFAULT_FDT_FILE="rockchip/rk3399-rock-4se.dtb"
CONFIG_DISPLAY_BOARDINFO_LATE=y
-CONFIG_MISC_INIT_R=y
CONFIG_SPL_MAX_SIZE=0x2e000
CONFIG_SPL_PAD_TO=0x7f8000
-CONFIG_SPL_HAS_BSS_LINKER_SECTION=y
-CONFIG_SPL_BSS_START_ADDR=0x400000
-CONFIG_SPL_BSS_MAX_SIZE=0x2000
# CONFIG_SPL_RAW_IMAGE_SUPPORT is not set
-# CONFIG_SPL_SHARES_INIT_SP_ADDR is not set
-CONFIG_SPL_STACK_R=y
-CONFIG_SPL_STACK_R_MALLOC_SIMPLE_LEN=0x10000
CONFIG_TPL=y
CONFIG_CMD_BOOTZ=y
CONFIG_CMD_NVEDIT_EFI=y
@@ -53,8 +42,6 @@
CONFIG_DFU_MMC=y
CONFIG_ROCKCHIP_GPIO=y
CONFIG_SYS_I2C_ROCKCHIP=y
-CONFIG_MISC=y
-CONFIG_ROCKCHIP_EFUSE=y
CONFIG_MMC_DW=y
CONFIG_MMC_DW_ROCKCHIP=y
CONFIG_MMC_SDHCI=y
diff --git a/configs/rock-pi-4-rk3399_defconfig b/configs/rock-pi-4-rk3399_defconfig
index 83fc4ad..bca44be 100644
--- a/configs/rock-pi-4-rk3399_defconfig
+++ b/configs/rock-pi-4-rk3399_defconfig
@@ -2,17 +2,13 @@
CONFIG_SKIP_LOWLEVEL_INIT=y
CONFIG_COUNTER_FREQUENCY=24000000
CONFIG_ARCH_ROCKCHIP=y
-CONFIG_TEXT_BASE=0x00200000
CONFIG_NR_DRAM_BANKS=1
-CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y
-CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x300000
CONFIG_ENV_OFFSET=0x3F8000
CONFIG_DEFAULT_DEVICE_TREE="rk3399-rock-pi-4a"
CONFIG_OF_LIBFDT_OVERLAY=y
CONFIG_DM_RESET=y
CONFIG_ROCKCHIP_RK3399=y
-CONFIG_TARGET_EVB_RK3399=y
-CONFIG_SPL_STACK=0x400000
+CONFIG_TARGET_ROCKPI4_RK3399=y
CONFIG_DEBUG_UART_BASE=0xFF1A0000
CONFIG_DEBUG_UART_CLOCK=24000000
CONFIG_SYS_LOAD_ADDR=0x800800
@@ -23,16 +19,9 @@
CONFIG_LEGACY_IMAGE_FORMAT=y
CONFIG_DEFAULT_FDT_FILE="rockchip/rk3399-rock-pi-4a.dtb"
CONFIG_DISPLAY_BOARDINFO_LATE=y
-CONFIG_MISC_INIT_R=y
CONFIG_SPL_MAX_SIZE=0x2e000
CONFIG_SPL_PAD_TO=0x7f8000
-CONFIG_SPL_HAS_BSS_LINKER_SECTION=y
-CONFIG_SPL_BSS_START_ADDR=0x400000
-CONFIG_SPL_BSS_MAX_SIZE=0x2000
# CONFIG_SPL_RAW_IMAGE_SUPPORT is not set
-# CONFIG_SPL_SHARES_INIT_SP_ADDR is not set
-CONFIG_SPL_STACK_R=y
-CONFIG_SPL_STACK_R_MALLOC_SIMPLE_LEN=0x10000
CONFIG_SPL_ATF_NO_PLATFORM_PARAM=y
CONFIG_TPL=y
CONFIG_CMD_BOOTZ=y
@@ -54,8 +43,6 @@
CONFIG_DFU_MMC=y
CONFIG_ROCKCHIP_GPIO=y
CONFIG_SYS_I2C_ROCKCHIP=y
-CONFIG_MISC=y
-CONFIG_ROCKCHIP_EFUSE=y
CONFIG_MMC_DW=y
CONFIG_MMC_DW_ROCKCHIP=y
CONFIG_MMC_SDHCI=y
diff --git a/configs/rock-pi-4c-rk3399_defconfig b/configs/rock-pi-4c-rk3399_defconfig
index 0893440..e1adec6 100644
--- a/configs/rock-pi-4c-rk3399_defconfig
+++ b/configs/rock-pi-4c-rk3399_defconfig
@@ -2,17 +2,13 @@
CONFIG_SKIP_LOWLEVEL_INIT=y
CONFIG_COUNTER_FREQUENCY=24000000
CONFIG_ARCH_ROCKCHIP=y
-CONFIG_TEXT_BASE=0x00200000
CONFIG_NR_DRAM_BANKS=1
-CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y
-CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x300000
CONFIG_ENV_OFFSET=0x3F8000
CONFIG_DEFAULT_DEVICE_TREE="rk3399-rock-pi-4c"
CONFIG_OF_LIBFDT_OVERLAY=y
CONFIG_DM_RESET=y
CONFIG_ROCKCHIP_RK3399=y
-CONFIG_TARGET_EVB_RK3399=y
-CONFIG_SPL_STACK=0x400000
+CONFIG_TARGET_ROCKPI4_RK3399=y
CONFIG_DEBUG_UART_BASE=0xFF1A0000
CONFIG_DEBUG_UART_CLOCK=24000000
CONFIG_SYS_LOAD_ADDR=0x800800
@@ -21,16 +17,9 @@
# CONFIG_ANDROID_BOOT_IMAGE is not set
CONFIG_DEFAULT_FDT_FILE="rockchip/rk3399-rock-pi-4c.dtb"
CONFIG_DISPLAY_BOARDINFO_LATE=y
-CONFIG_MISC_INIT_R=y
CONFIG_SPL_MAX_SIZE=0x2e000
CONFIG_SPL_PAD_TO=0x7f8000
-CONFIG_SPL_HAS_BSS_LINKER_SECTION=y
-CONFIG_SPL_BSS_START_ADDR=0x400000
-CONFIG_SPL_BSS_MAX_SIZE=0x2000
# CONFIG_SPL_RAW_IMAGE_SUPPORT is not set
-# CONFIG_SPL_SHARES_INIT_SP_ADDR is not set
-CONFIG_SPL_STACK_R=y
-CONFIG_SPL_STACK_R_MALLOC_SIMPLE_LEN=0x10000
CONFIG_SPL_ATF_NO_PLATFORM_PARAM=y
CONFIG_TPL=y
CONFIG_CMD_BOOTZ=y
@@ -52,8 +41,6 @@
CONFIG_DFU_MMC=y
CONFIG_ROCKCHIP_GPIO=y
CONFIG_SYS_I2C_ROCKCHIP=y
-CONFIG_MISC=y
-CONFIG_ROCKCHIP_EFUSE=y
CONFIG_MMC_DW=y
CONFIG_MMC_DW_ROCKCHIP=y
CONFIG_MMC_SDHCI=y
diff --git a/configs/rock-pi-e-rk3328_defconfig b/configs/rock-pi-e-rk3328_defconfig
index 6dda900..2302925 100644
--- a/configs/rock-pi-e-rk3328_defconfig
+++ b/configs/rock-pi-e-rk3328_defconfig
@@ -2,56 +2,38 @@
CONFIG_SKIP_LOWLEVEL_INIT=y
CONFIG_COUNTER_FREQUENCY=24000000
CONFIG_ARCH_ROCKCHIP=y
-CONFIG_TEXT_BASE=0x00200000
CONFIG_SPL_GPIO=y
CONFIG_NR_DRAM_BANKS=1
-CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y
-CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x300000
CONFIG_SF_DEFAULT_SPEED=20000000
CONFIG_ENV_OFFSET=0x3F8000
CONFIG_DEFAULT_DEVICE_TREE="rk3328-rock-pi-e"
CONFIG_DM_RESET=y
CONFIG_ROCKCHIP_RK3328=y
-CONFIG_TPL_ROCKCHIP_COMMON_BOARD=y
-CONFIG_TPL_LIBCOMMON_SUPPORT=y
-CONFIG_TPL_LIBGENERIC_SUPPORT=y
-CONFIG_SPL_DRIVERS_MISC=y
-CONFIG_SPL_STACK_R_ADDR=0x4000000
-CONFIG_SPL_STACK=0x400000
-CONFIG_TPL_SYS_MALLOC_F_LEN=0x800
-CONFIG_SPL_SYS_MALLOC_F_LEN=0x4000
CONFIG_DEBUG_UART_BASE=0xFF130000
CONFIG_DEBUG_UART_CLOCK=24000000
CONFIG_SYS_LOAD_ADDR=0x800800
CONFIG_DEBUG_UART=y
-# CONFIG_ANDROID_BOOT_IMAGE is not set
CONFIG_FIT=y
CONFIG_FIT_VERBOSE=y
+CONFIG_SPL_FIT_SIGNATURE=y
CONFIG_SPL_LOAD_FIT=y
+CONFIG_LEGACY_IMAGE_FORMAT=y
CONFIG_DEFAULT_FDT_FILE="rockchip/rk3328-rock-pi-e.dtb"
# CONFIG_DISPLAY_CPUINFO is not set
CONFIG_DISPLAY_BOARDINFO_LATE=y
-CONFIG_MISC_INIT_R=y
CONFIG_SPL_MAX_SIZE=0x40000
CONFIG_SPL_PAD_TO=0x7f8000
-CONFIG_SPL_HAS_BSS_LINKER_SECTION=y
-CONFIG_SPL_BSS_START_ADDR=0x2000000
-CONFIG_SPL_BSS_MAX_SIZE=0x2000
# CONFIG_SPL_RAW_IMAGE_SUPPORT is not set
-# CONFIG_SPL_SHARES_INIT_SP_ADDR is not set
-CONFIG_SPL_STACK_R=y
-CONFIG_SPL_STACK_R_MALLOC_SIMPLE_LEN=0x10000
-CONFIG_SPL_I2C=y
CONFIG_SPL_POWER=y
CONFIG_SPL_ATF=y
CONFIG_SPL_ATF_NO_PLATFORM_PARAM=y
-CONFIG_TPL_SYS_MALLOC_SIMPLE=y
-CONFIG_TPL_DRIVERS_MISC=y
CONFIG_CMD_BOOTZ=y
+CONFIG_CMD_GPIO=y
CONFIG_CMD_GPT=y
CONFIG_CMD_MMC=y
CONFIG_CMD_USB=y
CONFIG_CMD_TIME=y
+CONFIG_CMD_REGULATOR=y
CONFIG_SPL_OF_CONTROL=y
CONFIG_TPL_OF_CONTROL=y
CONFIG_OF_SPL_REMOVE_PROPS="clock-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents"
@@ -59,8 +41,8 @@
CONFIG_ENV_IS_IN_MMC=y
CONFIG_SYS_RELOC_GD_ENV_ADDR=y
CONFIG_SYS_MMC_ENV_DEV=1
-CONFIG_NET_RANDOM_ETHADDR=y
CONFIG_TPL_DM=y
+CONFIG_SPL_DM_SEQ_ALIAS=y
CONFIG_REGMAP=y
CONFIG_SPL_REGMAP=y
CONFIG_TPL_REGMAP=y
@@ -69,15 +51,14 @@
CONFIG_TPL_SYSCON=y
CONFIG_CLK=y
CONFIG_SPL_CLK=y
-CONFIG_FASTBOOT_BUF_ADDR=0x800800
-CONFIG_FASTBOOT_CMD_OEM_FORMAT=y
CONFIG_ROCKCHIP_GPIO=y
CONFIG_SYS_I2C_ROCKCHIP=y
-CONFIG_MISC=y
CONFIG_MMC_DW=y
CONFIG_MMC_DW_ROCKCHIP=y
CONFIG_PHY_REALTEK=y
+CONFIG_DM_MDIO=y
CONFIG_DM_ETH_PHY=y
+CONFIG_PHY_GIGE=y
CONFIG_ETH_DESIGNWARE=y
CONFIG_GMAC_ROCKCHIP=y
CONFIG_PHY_ROCKCHIP_INNO_USB2=y
@@ -85,9 +66,7 @@
CONFIG_SPL_PINCTRL=y
CONFIG_DM_PMIC=y
CONFIG_PMIC_RK8XX=y
-CONFIG_SPL_PMIC_RK8XX=y
CONFIG_SPL_DM_REGULATOR=y
-CONFIG_REGULATOR_PWM=y
CONFIG_DM_REGULATOR_FIXED=y
CONFIG_SPL_DM_REGULATOR_FIXED=y
CONFIG_REGULATOR_RK8XX=y
@@ -95,9 +74,10 @@
CONFIG_RAM=y
CONFIG_SPL_RAM=y
CONFIG_TPL_RAM=y
+CONFIG_DM_RNG=y
+CONFIG_RNG_ROCKCHIP=y
CONFIG_BAUDRATE=1500000
CONFIG_DEBUG_UART_SHIFT=2
-CONFIG_DEBUG_UART_ANNOUNCE=y
CONFIG_SYS_NS16550_MEM32=y
CONFIG_SYSINFO=y
CONFIG_SYSINFO_SMBIOS=y
@@ -109,12 +89,8 @@
CONFIG_USB_EHCI_GENERIC=y
CONFIG_USB_OHCI_HCD=y
CONFIG_USB_OHCI_GENERIC=y
-CONFIG_USB_DWC2=y
CONFIG_USB_DWC3=y
-# CONFIG_USB_DWC3_GADGET is not set
CONFIG_USB_DWC3_GENERIC=y
-CONFIG_USB_GADGET=y
-CONFIG_USB_GADGET_DWC2_OTG=y
CONFIG_SPL_TINY_MEMSET=y
CONFIG_TPL_TINY_MEMSET=y
CONFIG_ERRNO_STR=y
diff --git a/configs/rock-pi-n10-rk3399pro_defconfig b/configs/rock-pi-n10-rk3399pro_defconfig
index dc4b3b4..6889cdc 100644
--- a/configs/rock-pi-n10-rk3399pro_defconfig
+++ b/configs/rock-pi-n10-rk3399pro_defconfig
@@ -2,17 +2,13 @@
CONFIG_SKIP_LOWLEVEL_INIT=y
CONFIG_COUNTER_FREQUENCY=24000000
CONFIG_ARCH_ROCKCHIP=y
-CONFIG_TEXT_BASE=0x00200000
CONFIG_SPL_GPIO=y
CONFIG_NR_DRAM_BANKS=1
-CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y
-CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x300000
CONFIG_ENV_OFFSET=0x3F8000
CONFIG_DEFAULT_DEVICE_TREE="rk3399pro-rock-pi-n10"
CONFIG_DM_RESET=y
CONFIG_ROCKCHIP_RK3399=y
CONFIG_TARGET_EVB_RK3399=y
-CONFIG_SPL_STACK=0x400000
CONFIG_DEBUG_UART_BASE=0xFF1A0000
CONFIG_DEBUG_UART_CLOCK=24000000
CONFIG_SYS_LOAD_ADDR=0x800800
@@ -22,16 +18,9 @@
CONFIG_DEFAULT_FDT_FILE="rockchip/rk3399pro-rock-pi-n10.dtb"
# CONFIG_CONSOLE_MUX is not set
CONFIG_DISPLAY_BOARDINFO_LATE=y
-CONFIG_MISC_INIT_R=y
CONFIG_SPL_MAX_SIZE=0x2e000
CONFIG_SPL_PAD_TO=0x7f8000
-CONFIG_SPL_HAS_BSS_LINKER_SECTION=y
-CONFIG_SPL_BSS_START_ADDR=0x400000
-CONFIG_SPL_BSS_MAX_SIZE=0x2000
# CONFIG_SPL_RAW_IMAGE_SUPPORT is not set
-# CONFIG_SPL_SHARES_INIT_SP_ADDR is not set
-CONFIG_SPL_STACK_R=y
-CONFIG_SPL_STACK_R_MALLOC_SIMPLE_LEN=0x10000
CONFIG_SPL_ATF_NO_PLATFORM_PARAM=y
CONFIG_TPL=y
CONFIG_CMD_BOOTZ=y
@@ -47,7 +36,6 @@
CONFIG_SYS_RELOC_GD_ENV_ADDR=y
CONFIG_ROCKCHIP_GPIO=y
CONFIG_SYS_I2C_ROCKCHIP=y
-CONFIG_MISC=y
CONFIG_MMC_DW=y
CONFIG_MMC_DW_ROCKCHIP=y
CONFIG_MMC_SDHCI=y
diff --git a/configs/rock-pi-s-rk3308_defconfig b/configs/rock-pi-s-rk3308_defconfig
index 9908a4b..1e9cd2c 100644
--- a/configs/rock-pi-s-rk3308_defconfig
+++ b/configs/rock-pi-s-rk3308_defconfig
@@ -2,20 +2,12 @@
CONFIG_SKIP_LOWLEVEL_INIT=y
CONFIG_COUNTER_FREQUENCY=24000000
CONFIG_ARCH_ROCKCHIP=y
-CONFIG_TEXT_BASE=0x00600000
-CONFIG_SYS_MALLOC_F_LEN=0x2000
-CONFIG_SPL_LIBCOMMON_SUPPORT=y
-CONFIG_SPL_LIBGENERIC_SUPPORT=y
-CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y
-CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x800000
CONFIG_DEFAULT_DEVICE_TREE="rk3308-rock-pi-s"
CONFIG_OF_LIBFDT_OVERLAY=y
CONFIG_DM_RESET=y
CONFIG_ROCKCHIP_RK3308=y
CONFIG_SPL_DRIVERS_MISC=y
CONFIG_TARGET_EVB_RK3308=y
-CONFIG_SPL_STACK_R_ADDR=0xc00000
-CONFIG_SPL_STACK=0x400000
CONFIG_DEBUG_UART_BASE=0xFF0A0000
CONFIG_DEBUG_UART_CLOCK=24000000
# CONFIG_DEBUG_UART_BOARD_INIT is not set
@@ -29,11 +21,6 @@
# CONFIG_DISPLAY_CPUINFO is not set
CONFIG_SPL_MAX_SIZE=0x20000
CONFIG_SPL_PAD_TO=0x7f8000
-CONFIG_SPL_HAS_BSS_LINKER_SECTION=y
-CONFIG_SPL_BSS_START_ADDR=0x400000
-CONFIG_SPL_BSS_MAX_SIZE=0x2000
-# CONFIG_SPL_SHARES_INIT_SP_ADDR is not set
-CONFIG_SPL_STACK_R=y
# CONFIG_CMD_BDI is not set
# CONFIG_CMD_CONSOLE is not set
# CONFIG_CMD_ELF is not set
diff --git a/configs/rock5a-rk3588s_defconfig b/configs/rock5a-rk3588s_defconfig
index efa7bcb..ebe2d4a 100644
--- a/configs/rock5a-rk3588s_defconfig
+++ b/configs/rock5a-rk3588s_defconfig
@@ -2,19 +2,11 @@
CONFIG_SKIP_LOWLEVEL_INIT=y
CONFIG_COUNTER_FREQUENCY=24000000
CONFIG_ARCH_ROCKCHIP=y
-CONFIG_TEXT_BASE=0x00a00000
-CONFIG_SPL_LIBCOMMON_SUPPORT=y
-CONFIG_SPL_LIBGENERIC_SUPPORT=y
CONFIG_NR_DRAM_BANKS=2
-CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y
-CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0xc00000
CONFIG_DEFAULT_DEVICE_TREE="rk3588s-rock-5a"
CONFIG_ROCKCHIP_RK3588=y
-CONFIG_SPL_ROCKCHIP_COMMON_BOARD=y
CONFIG_SPL_SERIAL=y
-CONFIG_SPL_STACK_R_ADDR=0x1000000
CONFIG_TARGET_ROCK5A_RK3588=y
-CONFIG_SPL_STACK=0x1000000
CONFIG_DEBUG_UART_BASE=0xFEB50000
CONFIG_DEBUG_UART_CLOCK=24000000
CONFIG_SYS_LOAD_ADDR=0xc00800
@@ -30,12 +22,7 @@
CONFIG_DISPLAY_BOARDINFO_LATE=y
CONFIG_SPL_MAX_SIZE=0x40000
CONFIG_SPL_PAD_TO=0x7f8000
-CONFIG_SPL_HAS_BSS_LINKER_SECTION=y
-CONFIG_SPL_BSS_START_ADDR=0x4000000
-CONFIG_SPL_BSS_MAX_SIZE=0x4000
# CONFIG_SPL_RAW_IMAGE_SUPPORT is not set
-# CONFIG_SPL_SHARES_INIT_SP_ADDR is not set
-CONFIG_SPL_STACK_R=y
CONFIG_SPL_ATF=y
CONFIG_CMD_GPIO=y
CONFIG_CMD_GPT=y
diff --git a/configs/rock5b-rk3588_defconfig b/configs/rock5b-rk3588_defconfig
index a0678ff..58c7c44 100644
--- a/configs/rock5b-rk3588_defconfig
+++ b/configs/rock5b-rk3588_defconfig
@@ -3,22 +3,14 @@
CONFIG_SYS_HAS_NONCACHED_MEMORY=y
CONFIG_COUNTER_FREQUENCY=24000000
CONFIG_ARCH_ROCKCHIP=y
-CONFIG_TEXT_BASE=0x00a00000
-CONFIG_SPL_LIBCOMMON_SUPPORT=y
-CONFIG_SPL_LIBGENERIC_SUPPORT=y
CONFIG_NR_DRAM_BANKS=2
-CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y
-CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0xc00000
CONFIG_SF_DEFAULT_SPEED=24000000
CONFIG_SF_DEFAULT_MODE=0x2000
CONFIG_DEFAULT_DEVICE_TREE="rk3588-rock-5b"
CONFIG_ROCKCHIP_RK3588=y
-CONFIG_SPL_ROCKCHIP_COMMON_BOARD=y
CONFIG_ROCKCHIP_SPI_IMAGE=y
CONFIG_SPL_SERIAL=y
-CONFIG_SPL_STACK_R_ADDR=0x600000
CONFIG_TARGET_ROCK5B_RK3588=y
-CONFIG_SPL_STACK=0x400000
CONFIG_DEBUG_UART_BASE=0xFEB50000
CONFIG_DEBUG_UART_CLOCK=24000000
CONFIG_SPL_SPI_FLASH_SUPPORT=y
@@ -38,12 +30,7 @@
CONFIG_DISPLAY_BOARDINFO_LATE=y
CONFIG_SPL_MAX_SIZE=0x40000
CONFIG_SPL_PAD_TO=0x7f8000
-CONFIG_SPL_HAS_BSS_LINKER_SECTION=y
-CONFIG_SPL_BSS_START_ADDR=0x4000000
-CONFIG_SPL_BSS_MAX_SIZE=0x4000
# CONFIG_SPL_RAW_IMAGE_SUPPORT is not set
-# CONFIG_SPL_SHARES_INIT_SP_ADDR is not set
-CONFIG_SPL_STACK_R=y
CONFIG_SPL_SPI_LOAD=y
CONFIG_SYS_SPI_U_BOOT_OFFS=0x60000
CONFIG_SPL_ATF=y
diff --git a/configs/rock64-rk3328_defconfig b/configs/rock64-rk3328_defconfig
index 0297d09..b0be1d1 100644
--- a/configs/rock64-rk3328_defconfig
+++ b/configs/rock64-rk3328_defconfig
@@ -2,54 +2,45 @@
CONFIG_SKIP_LOWLEVEL_INIT=y
CONFIG_COUNTER_FREQUENCY=24000000
CONFIG_ARCH_ROCKCHIP=y
-CONFIG_TEXT_BASE=0x00200000
CONFIG_SPL_GPIO=y
CONFIG_NR_DRAM_BANKS=1
-CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y
-CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x300000
CONFIG_SF_DEFAULT_SPEED=20000000
CONFIG_ENV_OFFSET=0x3F8000
CONFIG_DEFAULT_DEVICE_TREE="rk3328-rock64"
CONFIG_DM_RESET=y
CONFIG_ROCKCHIP_RK3328=y
-CONFIG_TPL_ROCKCHIP_COMMON_BOARD=y
-CONFIG_TPL_LIBCOMMON_SUPPORT=y
-CONFIG_TPL_LIBGENERIC_SUPPORT=y
-CONFIG_SPL_DRIVERS_MISC=y
-CONFIG_SPL_STACK_R_ADDR=0x600000
-CONFIG_SPL_STACK=0x400000
-CONFIG_TPL_SYS_MALLOC_F_LEN=0x800
+CONFIG_ROCKCHIP_SPI_IMAGE=y
CONFIG_DEBUG_UART_BASE=0xFF130000
CONFIG_DEBUG_UART_CLOCK=24000000
+CONFIG_SPL_SPI_FLASH_SUPPORT=y
+CONFIG_SPL_SPI=y
CONFIG_SYS_LOAD_ADDR=0x800800
CONFIG_DEBUG_UART=y
-# CONFIG_ANDROID_BOOT_IMAGE is not set
CONFIG_FIT=y
CONFIG_FIT_VERBOSE=y
+CONFIG_SPL_FIT_SIGNATURE=y
CONFIG_SPL_LOAD_FIT=y
+CONFIG_LEGACY_IMAGE_FORMAT=y
CONFIG_DEFAULT_FDT_FILE="rockchip/rk3328-rock64.dtb"
# CONFIG_DISPLAY_CPUINFO is not set
CONFIG_DISPLAY_BOARDINFO_LATE=y
-CONFIG_MISC_INIT_R=y
CONFIG_SPL_MAX_SIZE=0x40000
CONFIG_SPL_PAD_TO=0x7f8000
-CONFIG_SPL_HAS_BSS_LINKER_SECTION=y
-CONFIG_SPL_BSS_START_ADDR=0x2000000
-CONFIG_SPL_BSS_MAX_SIZE=0x2000
# CONFIG_SPL_RAW_IMAGE_SUPPORT is not set
-# CONFIG_SPL_SHARES_INIT_SP_ADDR is not set
-CONFIG_SPL_STACK_R=y
-CONFIG_SPL_I2C=y
CONFIG_SPL_POWER=y
+CONFIG_SPL_SPI_LOAD=y
+CONFIG_SYS_SPI_U_BOOT_OFFS=0x60000
CONFIG_SPL_ATF=y
CONFIG_SPL_ATF_NO_PLATFORM_PARAM=y
-CONFIG_TPL_SYS_MALLOC_SIMPLE=y
CONFIG_CMD_BOOTZ=y
+CONFIG_CMD_GPIO=y
CONFIG_CMD_GPT=y
CONFIG_CMD_MMC=y
+CONFIG_CMD_POWEROFF=y
CONFIG_CMD_USB=y
# CONFIG_CMD_SETEXPR is not set
CONFIG_CMD_TIME=y
+CONFIG_CMD_REGULATOR=y
CONFIG_SPL_OF_CONTROL=y
CONFIG_TPL_OF_CONTROL=y
CONFIG_OF_SPL_REMOVE_PROPS="clock-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents"
@@ -57,8 +48,8 @@
CONFIG_ENV_IS_IN_MMC=y
CONFIG_SYS_RELOC_GD_ENV_ADDR=y
CONFIG_SYS_MMC_ENV_DEV=1
-CONFIG_NET_RANDOM_ETHADDR=y
CONFIG_TPL_DM=y
+CONFIG_SPL_DM_SEQ_ALIAS=y
CONFIG_REGMAP=y
CONFIG_SPL_REGMAP=y
CONFIG_TPL_REGMAP=y
@@ -67,15 +58,18 @@
CONFIG_TPL_SYSCON=y
CONFIG_CLK=y
CONFIG_SPL_CLK=y
-CONFIG_FASTBOOT_BUF_ADDR=0x800800
-CONFIG_FASTBOOT_CMD_OEM_FORMAT=y
CONFIG_ROCKCHIP_GPIO=y
CONFIG_SYS_I2C_ROCKCHIP=y
-CONFIG_MISC=y
-CONFIG_ROCKCHIP_EFUSE=y
CONFIG_MMC_DW=y
CONFIG_MMC_DW_ROCKCHIP=y
+CONFIG_SPI_FLASH_SFDP_SUPPORT=y
CONFIG_SPI_FLASH_GIGADEVICE=y
+CONFIG_SPI_FLASH_MACRONIX=y
+CONFIG_SPI_FLASH_WINBOND=y
+CONFIG_SPI_FLASH_XTX=y
+CONFIG_PHY_REALTEK=y
+CONFIG_DM_ETH_PHY=y
+CONFIG_PHY_GIGE=y
CONFIG_ETH_DESIGNWARE=y
CONFIG_GMAC_ROCKCHIP=y
CONFIG_PHY_ROCKCHIP_INNO_USB2=y
@@ -83,9 +77,7 @@
CONFIG_SPL_PINCTRL=y
CONFIG_DM_PMIC=y
CONFIG_PMIC_RK8XX=y
-CONFIG_SPL_PMIC_RK8XX=y
CONFIG_SPL_DM_REGULATOR=y
-CONFIG_REGULATOR_PWM=y
CONFIG_DM_REGULATOR_FIXED=y
CONFIG_SPL_DM_REGULATOR_FIXED=y
CONFIG_REGULATOR_RK8XX=y
@@ -111,10 +103,7 @@
CONFIG_USB_OHCI_GENERIC=y
CONFIG_USB_DWC2=y
CONFIG_USB_DWC3=y
-# CONFIG_USB_DWC3_GADGET is not set
CONFIG_USB_DWC3_GENERIC=y
-CONFIG_USB_GADGET=y
-CONFIG_USB_GADGET_DWC2_OTG=y
CONFIG_SPL_TINY_MEMSET=y
CONFIG_TPL_TINY_MEMSET=y
CONFIG_ERRNO_STR=y
diff --git a/configs/rock960-rk3399_defconfig b/configs/rock960-rk3399_defconfig
index b93dda5..13575c5 100644
--- a/configs/rock960-rk3399_defconfig
+++ b/configs/rock960-rk3399_defconfig
@@ -2,15 +2,11 @@
CONFIG_SKIP_LOWLEVEL_INIT=y
CONFIG_COUNTER_FREQUENCY=24000000
CONFIG_ARCH_ROCKCHIP=y
-CONFIG_TEXT_BASE=0x00200000
-CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y
-CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x300000
CONFIG_ENV_OFFSET=0x3F8000
CONFIG_DEFAULT_DEVICE_TREE="rk3399-rock960"
CONFIG_DM_RESET=y
CONFIG_ROCKCHIP_RK3399=y
CONFIG_TARGET_ROCK960_RK3399=y
-CONFIG_SPL_STACK=0x400000
CONFIG_DEBUG_UART_BASE=0xFF1A0000
CONFIG_DEBUG_UART_CLOCK=24000000
CONFIG_SYS_LOAD_ADDR=0x800800
@@ -20,16 +16,9 @@
CONFIG_DEFAULT_FDT_FILE="rockchip/rk3399-rock960.dtb"
CONFIG_SYS_PBSIZE=1052
CONFIG_DISPLAY_BOARDINFO_LATE=y
-CONFIG_MISC_INIT_R=y
CONFIG_SPL_MAX_SIZE=0x2e000
CONFIG_SPL_PAD_TO=0x7f8000
-CONFIG_SPL_HAS_BSS_LINKER_SECTION=y
-CONFIG_SPL_BSS_START_ADDR=0x400000
-CONFIG_SPL_BSS_MAX_SIZE=0x2000
# CONFIG_SPL_RAW_IMAGE_SUPPORT is not set
-# CONFIG_SPL_SHARES_INIT_SP_ADDR is not set
-CONFIG_SPL_STACK_R=y
-CONFIG_SPL_STACK_R_MALLOC_SIMPLE_LEN=0x10000
CONFIG_SPL_ATF_NO_PLATFORM_PARAM=y
CONFIG_TPL=y
CONFIG_SYS_PROMPT="rock960 => "
@@ -50,7 +39,7 @@
CONFIG_SYS_MMC_ENV_DEV=1
CONFIG_ROCKCHIP_GPIO=y
CONFIG_SYS_I2C_ROCKCHIP=y
-CONFIG_MISC=y
+CONFIG_ROCKCHIP_IODOMAIN=y
CONFIG_MMC_DW=y
CONFIG_MMC_DW_ROCKCHIP=y
CONFIG_MMC_SDHCI=y
diff --git a/configs/rockpro64-rk3399_defconfig b/configs/rockpro64-rk3399_defconfig
index 711541f..d66b4a9 100644
--- a/configs/rockpro64-rk3399_defconfig
+++ b/configs/rockpro64-rk3399_defconfig
@@ -2,10 +2,7 @@
CONFIG_SKIP_LOWLEVEL_INIT=y
CONFIG_COUNTER_FREQUENCY=24000000
CONFIG_ARCH_ROCKCHIP=y
-CONFIG_TEXT_BASE=0x00200000
CONFIG_NR_DRAM_BANKS=1
-CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y
-CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x300000
CONFIG_ENV_SIZE=0x8000
CONFIG_ENV_OFFSET=0x3F8000
CONFIG_DEFAULT_DEVICE_TREE="rk3399-rockpro64"
@@ -13,7 +10,6 @@
CONFIG_ROCKCHIP_RK3399=y
CONFIG_ROCKCHIP_SPI_IMAGE=y
CONFIG_TARGET_ROCKPRO64_RK3399=y
-CONFIG_SPL_STACK=0x400000
CONFIG_DEBUG_UART_BASE=0xFF1A0000
CONFIG_DEBUG_UART_CLOCK=24000000
CONFIG_SPL_SPI_FLASH_SUPPORT=y
@@ -28,16 +24,9 @@
CONFIG_USE_PREBOOT=y
CONFIG_DEFAULT_FDT_FILE="rockchip/rk3399-rockpro64.dtb"
CONFIG_DISPLAY_BOARDINFO_LATE=y
-CONFIG_MISC_INIT_R=y
CONFIG_SPL_MAX_SIZE=0x40000
CONFIG_SPL_PAD_TO=0x7f8000
-CONFIG_SPL_HAS_BSS_LINKER_SECTION=y
-CONFIG_SPL_BSS_START_ADDR=0x400000
-CONFIG_SPL_BSS_MAX_SIZE=0x2000
# CONFIG_SPL_RAW_IMAGE_SUPPORT is not set
-# CONFIG_SPL_SHARES_INIT_SP_ADDR is not set
-CONFIG_SPL_STACK_R=y
-CONFIG_SPL_STACK_R_MALLOC_SIMPLE_LEN=0x10000
CONFIG_SPL_SPI_LOAD=y
CONFIG_SYS_SPI_U_BOOT_OFFS=0xE0000
CONFIG_SPL_ATF_NO_PLATFORM_PARAM=y
@@ -63,8 +52,7 @@
CONFIG_SYS_I2C_ROCKCHIP=y
CONFIG_LED=y
CONFIG_LED_GPIO=y
-CONFIG_MISC=y
-CONFIG_ROCKCHIP_EFUSE=y
+CONFIG_ROCKCHIP_IODOMAIN=y
CONFIG_MMC_DW=y
CONFIG_MMC_DW_ROCKCHIP=y
CONFIG_MMC_SDHCI=y
diff --git a/configs/s400_defconfig b/configs/s400_defconfig
index 8e22c95..d75d296 100644
--- a/configs/s400_defconfig
+++ b/configs/s400_defconfig
@@ -6,7 +6,7 @@
CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x20000000
CONFIG_ENV_SIZE=0x2000
CONFIG_DM_GPIO=y
-CONFIG_DEFAULT_DEVICE_TREE="meson-axg-s400"
+CONFIG_DEFAULT_DEVICE_TREE="amlogic/meson-axg-s400"
CONFIG_OF_LIBFDT_OVERLAY=y
CONFIG_DM_RESET=y
CONFIG_MESON_AXG=y
diff --git a/configs/sama7g54_curiosity_mmc_defconfig b/configs/sama7g54_curiosity_mmc_defconfig
new file mode 100644
index 0000000..fa363682
--- /dev/null
+++ b/configs/sama7g54_curiosity_mmc_defconfig
@@ -0,0 +1,123 @@
+CONFIG_ARM=y
+CONFIG_ARCH_AT91=y
+CONFIG_TEXT_BASE=0x66f00000
+CONFIG_SYS_MALLOC_LEN=0x1000000
+CONFIG_SYS_MALLOC_F_LEN=0x40000
+CONFIG_TARGET_SAMA7G54_CURIOSITY=y
+CONFIG_NR_DRAM_BANKS=1
+CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y
+CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x60044000
+CONFIG_SF_DEFAULT_SPEED=50000000
+CONFIG_ENV_SIZE=0x4000
+CONFIG_DM_GPIO=y
+CONFIG_DEFAULT_DEVICE_TREE="at91-sama7g54_curiosity"
+CONFIG_OF_LIBFDT_OVERLAY=y
+CONFIG_DM_RESET=y
+CONFIG_SYS_LOAD_ADDR=0x62000000
+CONFIG_SYS_MEMTEST_START=0x60000000
+CONFIG_SYS_MEMTEST_END=0x68000000
+CONFIG_ENV_VARS_UBOOT_CONFIG=y
+CONFIG_FIT=y
+# CONFIG_BOOTSTD is not set
+CONFIG_SYS_BOOTM_LEN=0x2000000
+CONFIG_NAND_BOOT=y
+CONFIG_QSPI_BOOT=y
+CONFIG_SD_BOOT=y
+CONFIG_BOOTDELAY=3
+CONFIG_USE_BOOTARGS=y
+CONFIG_BOOTARGS="console=ttyS0,115200 root=/dev/mmcblk1p2 rw rootwait"
+CONFIG_USE_BOOTCOMMAND=y
+CONFIG_BOOTCOMMAND="fatload mmc 1:1 0x61000000 at91-sama7g54_curiosity.dtb; fatload mmc 1:1 0x62000000 zImage; bootz 0x62000000 - 0x61000000"
+CONFIG_LOGLEVEL=6
+CONFIG_BOARD_TYPES=y
+CONFIG_DISPLAY_BOARDINFO_LATE=y
+CONFIG_HUSH_PARSER=y
+CONFIG_CMD_CPU=y
+CONFIG_CMD_BOOTZ=y
+CONFIG_CMD_MEMINFO=y
+CONFIG_CMD_MEM_SEARCH=y
+CONFIG_CMD_MX_CYCLIC=y
+CONFIG_CMD_MEMTEST=y
+CONFIG_CMD_STRINGS=y
+CONFIG_CMD_CLK=y
+CONFIG_CMD_DM=y
+CONFIG_CMD_GPIO=y
+CONFIG_CMD_I2C=y
+# CONFIG_CMD_LOADB is not set
+# CONFIG_CMD_LOADS is not set
+CONFIG_CMD_LSBLK=y
+CONFIG_CMD_MMC=y
+CONFIG_CMD_MTD=y
+CONFIG_CMD_NAND=y
+CONFIG_CMD_NAND_TRIMFFS=y
+CONFIG_CMD_NAND_LOCK_UNLOCK=y
+CONFIG_CMD_NAND_TORTURE=y
+CONFIG_CMD_SF_TEST=y
+CONFIG_CMD_CAT=y
+CONFIG_CMD_XXD=y
+CONFIG_CMD_RTC=y
+CONFIG_CMD_TIME=y
+CONFIG_CMD_EXT4=y
+CONFIG_CMD_EXT4_WRITE=y
+CONFIG_CMD_FAT=y
+CONFIG_CMD_FS_GENERIC=y
+CONFIG_CMD_MTDPARTS=y
+CONFIG_CMD_MTDPARTS_SPREAD=y
+CONFIG_CMD_MTDPARTS_SHOW_NET_SIZES=y
+CONFIG_MTDIDS_DEFAULT="nand0=nand0,nor0=nor0"
+CONFIG_MTDPARTS_DEFAULT="mtdparts=nand0:256k(bootstrap-nand)ro,1M(u-boot-nand)ro,256k(env-nand)ro,512k(dtb-nand)ro,6M(kernel-nand)ro,-(rootfs-nand)ro;nor0:256k(bootstrap-nor)ro,1M(u-boot-nor)ro,256k(env-nor)ro,512k(dtb-nor)ro,6M(kernel-nor)ro"
+CONFIG_OF_CONTROL=y
+# CONFIG_OF_TAG_MIGRATE is not set
+CONFIG_ENV_IS_IN_FAT=y
+CONFIG_ENV_FAT_DEVICE_AND_PART="1:1"
+CONFIG_SYS_RELOC_GD_ENV_ADDR=y
+CONFIG_USE_HOSTNAME=y
+CONFIG_HOSTNAME="SAMA7G54"
+CONFIG_VERSION_VARIABLE=y
+# CONFIG_NET is not set
+CONFIG_CLK=y
+CONFIG_CLK_CCF=y
+CONFIG_CLK_AT91=y
+CONFIG_AT91_UTMI=y
+CONFIG_AT91_GENERIC_CLK=y
+CONFIG_AT91_SAM9X60_PLL=y
+CONFIG_CPU=y
+CONFIG_ATMEL_PIO4=y
+CONFIG_DM_I2C=y
+CONFIG_I2C_SET_DEFAULT_BUS_NUM=y
+CONFIG_SYS_I2C_AT91=y
+CONFIG_LED=y
+CONFIG_LED_GPIO=y
+CONFIG_ATMEL_EBI=y
+CONFIG_MFD_ATMEL_SMC=y
+CONFIG_I2C_EEPROM=y
+CONFIG_MICROCHIP_FLEXCOM=y
+CONFIG_MMC_SDHCI=y
+CONFIG_MMC_SDHCI_ATMEL=y
+CONFIG_MTD=y
+CONFIG_DM_MTD=y
+CONFIG_DM_NAND_ATMEL=y
+CONFIG_SYS_NAND_ONFI_DETECTION=y
+CONFIG_DM_SPI_FLASH=y
+CONFIG_SPI_FLASH_SFDP_SUPPORT=y
+CONFIG_SPI_FLASH_SST=y
+# CONFIG_SPI_FLASH_USE_4K_SECTORS is not set
+CONFIG_SPI_FLASH_MTD=y
+CONFIG_PINCTRL=y
+CONFIG_PINCTRL_AT91PIO4=y
+CONFIG_RESET_AT91=y
+CONFIG_DM_RTC=y
+CONFIG_RTC_EMULATION=y
+CONFIG_DM_SERIAL=y
+CONFIG_ATMEL_USART=y
+CONFIG_SPI=y
+CONFIG_DM_SPI=y
+CONFIG_ATMEL_QSPI=y
+CONFIG_SYSRESET=y
+CONFIG_SYSRESET_AT91=y
+CONFIG_TIMER=y
+CONFIG_MCHP_PIT64B_TIMER=y
+CONFIG_FAT_WRITE=y
+CONFIG_CMD_DHRYSTONE=y
+# CONFIG_EFI_LOADER is not set
+CONFIG_PHANDLE_CHECK_SEQ=y
diff --git a/configs/sama7g54_curiosity_nandflash_defconfig b/configs/sama7g54_curiosity_nandflash_defconfig
new file mode 100644
index 0000000..331bb8d
--- /dev/null
+++ b/configs/sama7g54_curiosity_nandflash_defconfig
@@ -0,0 +1,122 @@
+CONFIG_ARM=y
+CONFIG_ARCH_AT91=y
+CONFIG_TEXT_BASE=0x66f00000
+CONFIG_SYS_MALLOC_LEN=0x1000000
+CONFIG_SYS_MALLOC_F_LEN=0x40000
+CONFIG_TARGET_SAMA7G54_CURIOSITY=y
+CONFIG_NR_DRAM_BANKS=1
+CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y
+CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x60044000
+CONFIG_SF_DEFAULT_SPEED=50000000
+CONFIG_ENV_SECT_SIZE=0x1000
+CONFIG_DM_GPIO=y
+CONFIG_DEFAULT_DEVICE_TREE="at91-sama7g54_curiosity"
+CONFIG_OF_LIBFDT_OVERLAY=y
+CONFIG_DM_RESET=y
+CONFIG_SYS_LOAD_ADDR=0x62000000
+CONFIG_SYS_MEMTEST_START=0x60000000
+CONFIG_SYS_MEMTEST_END=0x68000000
+CONFIG_ENV_VARS_UBOOT_CONFIG=y
+CONFIG_FIT=y
+# CONFIG_BOOTSTD is not set
+CONFIG_SYS_BOOTM_LEN=0x2000000
+CONFIG_NAND_BOOT=y
+CONFIG_QSPI_BOOT=y
+CONFIG_SD_BOOT=y
+CONFIG_BOOTDELAY=3
+CONFIG_USE_BOOTARGS=y
+CONFIG_BOOTARGS="console=ttyS0,115200 root=/dev/mmcblk1p2 rw rootwait"
+CONFIG_USE_BOOTCOMMAND=y
+CONFIG_BOOTCOMMAND="nand read 0x61000000 0x180000 0x80000; nand read 0x62000000 0x200000 0x600000; bootz 0x62000000 - 0x61000000"
+CONFIG_LOGLEVEL=6
+CONFIG_BOARD_TYPES=y
+CONFIG_DISPLAY_BOARDINFO_LATE=y
+CONFIG_HUSH_PARSER=y
+CONFIG_CMD_CPU=y
+CONFIG_CMD_BOOTZ=y
+CONFIG_CMD_MEMINFO=y
+CONFIG_CMD_MEM_SEARCH=y
+CONFIG_CMD_MX_CYCLIC=y
+CONFIG_CMD_MEMTEST=y
+CONFIG_CMD_STRINGS=y
+CONFIG_CMD_CLK=y
+CONFIG_CMD_DM=y
+CONFIG_CMD_GPIO=y
+CONFIG_CMD_I2C=y
+# CONFIG_CMD_LOADB is not set
+# CONFIG_CMD_LOADS is not set
+CONFIG_CMD_LSBLK=y
+CONFIG_CMD_MMC=y
+CONFIG_CMD_MTD=y
+CONFIG_CMD_NAND=y
+CONFIG_CMD_NAND_TRIMFFS=y
+CONFIG_CMD_NAND_LOCK_UNLOCK=y
+CONFIG_CMD_NAND_TORTURE=y
+CONFIG_CMD_SF_TEST=y
+CONFIG_CMD_CAT=y
+CONFIG_CMD_XXD=y
+CONFIG_CMD_RTC=y
+CONFIG_CMD_TIME=y
+CONFIG_CMD_EXT4=y
+CONFIG_CMD_EXT4_WRITE=y
+CONFIG_CMD_FAT=y
+CONFIG_CMD_FS_GENERIC=y
+CONFIG_CMD_MTDPARTS=y
+CONFIG_CMD_MTDPARTS_SPREAD=y
+CONFIG_CMD_MTDPARTS_SHOW_NET_SIZES=y
+CONFIG_MTDIDS_DEFAULT="nand0=nand0,nor0=nor0"
+CONFIG_MTDPARTS_DEFAULT="mtdparts=nand0:256k(bootstrap-nand)ro,1M(u-boot-nand)ro,256k(env-nand)ro,512k(dtb-nand)ro,6M(kernel-nand)ro,-(rootfs-nand)ro;nor0:256k(bootstrap-nor)ro,1M(u-boot-nor)ro,256k(env-nor)ro,512k(dtb-nor)ro,6M(kernel-nor)ro"
+CONFIG_OF_CONTROL=y
+# CONFIG_OF_TAG_MIGRATE is not set
+CONFIG_ENV_IS_IN_NAND=y
+CONFIG_SYS_RELOC_GD_ENV_ADDR=y
+CONFIG_USE_HOSTNAME=y
+CONFIG_HOSTNAME="SAMA7G54"
+CONFIG_VERSION_VARIABLE=y
+# CONFIG_NET is not set
+CONFIG_CLK=y
+CONFIG_CLK_CCF=y
+CONFIG_CLK_AT91=y
+CONFIG_AT91_UTMI=y
+CONFIG_AT91_GENERIC_CLK=y
+CONFIG_AT91_SAM9X60_PLL=y
+CONFIG_CPU=y
+CONFIG_ATMEL_PIO4=y
+CONFIG_DM_I2C=y
+CONFIG_I2C_SET_DEFAULT_BUS_NUM=y
+CONFIG_SYS_I2C_AT91=y
+CONFIG_LED=y
+CONFIG_LED_GPIO=y
+CONFIG_ATMEL_EBI=y
+CONFIG_MFD_ATMEL_SMC=y
+CONFIG_I2C_EEPROM=y
+CONFIG_MICROCHIP_FLEXCOM=y
+CONFIG_MMC_SDHCI=y
+CONFIG_MMC_SDHCI_ATMEL=y
+CONFIG_MTD=y
+CONFIG_DM_MTD=y
+CONFIG_DM_NAND_ATMEL=y
+CONFIG_SYS_NAND_ONFI_DETECTION=y
+CONFIG_DM_SPI_FLASH=y
+CONFIG_SPI_FLASH_SFDP_SUPPORT=y
+CONFIG_SPI_FLASH_SST=y
+# CONFIG_SPI_FLASH_USE_4K_SECTORS is not set
+CONFIG_SPI_FLASH_MTD=y
+CONFIG_PINCTRL=y
+CONFIG_PINCTRL_AT91PIO4=y
+CONFIG_RESET_AT91=y
+CONFIG_DM_RTC=y
+CONFIG_RTC_EMULATION=y
+CONFIG_DM_SERIAL=y
+CONFIG_ATMEL_USART=y
+CONFIG_SPI=y
+CONFIG_DM_SPI=y
+CONFIG_ATMEL_QSPI=y
+CONFIG_SYSRESET=y
+CONFIG_SYSRESET_AT91=y
+CONFIG_TIMER=y
+CONFIG_MCHP_PIT64B_TIMER=y
+CONFIG_FAT_WRITE=y
+CONFIG_CMD_DHRYSTONE=y
+# CONFIG_EFI_LOADER is not set
+CONFIG_PHANDLE_CHECK_SEQ=y
diff --git a/configs/sama7g54_curiosity_qspiflash_defconfig b/configs/sama7g54_curiosity_qspiflash_defconfig
new file mode 100644
index 0000000..00e5362
--- /dev/null
+++ b/configs/sama7g54_curiosity_qspiflash_defconfig
@@ -0,0 +1,122 @@
+CONFIG_ARM=y
+CONFIG_ARCH_AT91=y
+CONFIG_TEXT_BASE=0x66f00000
+CONFIG_SYS_MALLOC_LEN=0x1000000
+CONFIG_SYS_MALLOC_F_LEN=0x40000
+CONFIG_TARGET_SAMA7G54_CURIOSITY=y
+CONFIG_NR_DRAM_BANKS=1
+CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y
+CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x60044000
+CONFIG_SF_DEFAULT_SPEED=50000000
+CONFIG_ENV_SECT_SIZE=0x10000
+CONFIG_DM_GPIO=y
+CONFIG_DEFAULT_DEVICE_TREE="at91-sama7g54_curiosity"
+CONFIG_OF_LIBFDT_OVERLAY=y
+CONFIG_DM_RESET=y
+CONFIG_SYS_LOAD_ADDR=0x62000000
+CONFIG_SYS_MEMTEST_START=0x60000000
+CONFIG_SYS_MEMTEST_END=0x68000000
+CONFIG_ENV_VARS_UBOOT_CONFIG=y
+CONFIG_FIT=y
+# CONFIG_BOOTSTD is not set
+CONFIG_SYS_BOOTM_LEN=0x2000000
+CONFIG_NAND_BOOT=y
+CONFIG_QSPI_BOOT=y
+CONFIG_SD_BOOT=y
+CONFIG_BOOTDELAY=3
+CONFIG_USE_BOOTARGS=y
+CONFIG_BOOTARGS="console=ttyS0,115200 root=/dev/mmcblk1p2 rw rootwait"
+CONFIG_USE_BOOTCOMMAND=y
+CONFIG_BOOTCOMMAND="sf probe 0; sf read 0x61000000 0x180000 0x80000; sf read 0x62000000 0x200000 0x600000; bootz 0x62000000 - 0x61000000"
+CONFIG_LOGLEVEL=6
+CONFIG_BOARD_TYPES=y
+CONFIG_DISPLAY_BOARDINFO_LATE=y
+CONFIG_HUSH_PARSER=y
+CONFIG_CMD_CPU=y
+CONFIG_CMD_BOOTZ=y
+CONFIG_CMD_MEMINFO=y
+CONFIG_CMD_MEM_SEARCH=y
+CONFIG_CMD_MX_CYCLIC=y
+CONFIG_CMD_MEMTEST=y
+CONFIG_CMD_STRINGS=y
+CONFIG_CMD_CLK=y
+CONFIG_CMD_DM=y
+CONFIG_CMD_GPIO=y
+CONFIG_CMD_I2C=y
+# CONFIG_CMD_LOADB is not set
+# CONFIG_CMD_LOADS is not set
+CONFIG_CMD_LSBLK=y
+CONFIG_CMD_MMC=y
+CONFIG_CMD_MTD=y
+CONFIG_CMD_NAND=y
+CONFIG_CMD_NAND_TRIMFFS=y
+CONFIG_CMD_NAND_LOCK_UNLOCK=y
+CONFIG_CMD_NAND_TORTURE=y
+CONFIG_CMD_SF_TEST=y
+CONFIG_CMD_CAT=y
+CONFIG_CMD_XXD=y
+CONFIG_CMD_RTC=y
+CONFIG_CMD_TIME=y
+CONFIG_CMD_EXT4=y
+CONFIG_CMD_EXT4_WRITE=y
+CONFIG_CMD_FAT=y
+CONFIG_CMD_FS_GENERIC=y
+CONFIG_CMD_MTDPARTS=y
+CONFIG_CMD_MTDPARTS_SPREAD=y
+CONFIG_CMD_MTDPARTS_SHOW_NET_SIZES=y
+CONFIG_MTDIDS_DEFAULT="nand0=nand0,nor0=nor0"
+CONFIG_MTDPARTS_DEFAULT="mtdparts=nand0:256k(bootstrap-nand)ro,1M(u-boot-nand)ro,256k(env-nand)ro,512k(dtb-nand)ro,6M(kernel-nand)ro,-(rootfs-nand)ro;nor0:256k(bootstrap-nor)ro,1M(u-boot-nor)ro,256k(env-nor)ro,512k(dtb-nor)ro,6M(kernel-nor)ro"
+CONFIG_OF_CONTROL=y
+# CONFIG_OF_TAG_MIGRATE is not set
+CONFIG_ENV_IS_IN_SPI_FLASH=y
+CONFIG_SYS_RELOC_GD_ENV_ADDR=y
+CONFIG_USE_HOSTNAME=y
+CONFIG_HOSTNAME="SAMA7G54"
+CONFIG_VERSION_VARIABLE=y
+# CONFIG_NET is not set
+CONFIG_CLK=y
+CONFIG_CLK_CCF=y
+CONFIG_CLK_AT91=y
+CONFIG_AT91_UTMI=y
+CONFIG_AT91_GENERIC_CLK=y
+CONFIG_AT91_SAM9X60_PLL=y
+CONFIG_CPU=y
+CONFIG_ATMEL_PIO4=y
+CONFIG_DM_I2C=y
+CONFIG_I2C_SET_DEFAULT_BUS_NUM=y
+CONFIG_SYS_I2C_AT91=y
+CONFIG_LED=y
+CONFIG_LED_GPIO=y
+CONFIG_ATMEL_EBI=y
+CONFIG_MFD_ATMEL_SMC=y
+CONFIG_I2C_EEPROM=y
+CONFIG_MICROCHIP_FLEXCOM=y
+CONFIG_MMC_SDHCI=y
+CONFIG_MMC_SDHCI_ATMEL=y
+CONFIG_MTD=y
+CONFIG_DM_MTD=y
+CONFIG_DM_NAND_ATMEL=y
+CONFIG_SYS_NAND_ONFI_DETECTION=y
+CONFIG_DM_SPI_FLASH=y
+CONFIG_SPI_FLASH_SFDP_SUPPORT=y
+CONFIG_SPI_FLASH_SST=y
+# CONFIG_SPI_FLASH_USE_4K_SECTORS is not set
+CONFIG_SPI_FLASH_MTD=y
+CONFIG_PINCTRL=y
+CONFIG_PINCTRL_AT91PIO4=y
+CONFIG_RESET_AT91=y
+CONFIG_DM_RTC=y
+CONFIG_RTC_EMULATION=y
+CONFIG_DM_SERIAL=y
+CONFIG_ATMEL_USART=y
+CONFIG_SPI=y
+CONFIG_DM_SPI=y
+CONFIG_ATMEL_QSPI=y
+CONFIG_SYSRESET=y
+CONFIG_SYSRESET_AT91=y
+CONFIG_TIMER=y
+CONFIG_MCHP_PIT64B_TIMER=y
+CONFIG_FAT_WRITE=y
+CONFIG_CMD_DHRYSTONE=y
+# CONFIG_EFI_LOADER is not set
+CONFIG_PHANDLE_CHECK_SEQ=y
diff --git a/configs/sandbox64_defconfig b/configs/sandbox64_defconfig
index 3be9a00..2bd4eea 100644
--- a/configs/sandbox64_defconfig
+++ b/configs/sandbox64_defconfig
@@ -11,6 +11,7 @@
CONFIG_DEBUG_UART=y
CONFIG_SYS_MEMTEST_START=0x00100000
CONFIG_SYS_MEMTEST_END=0x00101000
+CONFIG_BUTTON_CMD=y
CONFIG_FIT=y
CONFIG_FIT_SIGNATURE=y
CONFIG_FIT_VERBOSE=y
@@ -134,7 +135,6 @@
CONFIG_DM_DEMO=y
CONFIG_DM_DEMO_SIMPLE=y
CONFIG_DM_DEMO_SHAPE=y
-CONFIG_DFU_SF=y
CONFIG_FASTBOOT_FLASH=y
CONFIG_FASTBOOT_FLASH_MMC_DEV=0
CONFIG_ARM_FFA_TRANSPORT=y
@@ -267,12 +267,8 @@
CONFIG_TPM=y
CONFIG_ERRNO_STR=y
CONFIG_GETOPT=y
-CONFIG_EFI_RUNTIME_UPDATE_CAPSULE=y
-CONFIG_EFI_CAPSULE_ON_DISK=y
-CONFIG_EFI_CAPSULE_FIRMWARE_RAW=y
CONFIG_EFI_SECURE_BOOT=y
CONFIG_TEST_FDTDEC=y
-CONFIG_FWU_MULTI_BANK_UPDATE=y
CONFIG_UNIT_TEST=y
CONFIG_UT_TIME=y
CONFIG_UT_DM=y
diff --git a/configs/sandbox_defconfig b/configs/sandbox_defconfig
index 4ad1036..93b52f2 100644
--- a/configs/sandbox_defconfig
+++ b/configs/sandbox_defconfig
@@ -10,6 +10,7 @@
CONFIG_DEBUG_UART=y
CONFIG_SYS_MEMTEST_START=0x00100000
CONFIG_SYS_MEMTEST_END=0x00101000
+CONFIG_BUTTON_CMD=y
CONFIG_FIT=y
CONFIG_FIT_RSASSA_PSS=y
CONFIG_FIT_CIPHER=y
diff --git a/configs/sandbox_flattree_defconfig b/configs/sandbox_flattree_defconfig
index 0390186..6bf8874 100644
--- a/configs/sandbox_flattree_defconfig
+++ b/configs/sandbox_flattree_defconfig
@@ -8,6 +8,7 @@
CONFIG_DEBUG_UART=y
CONFIG_SYS_MEMTEST_START=0x00100000
CONFIG_SYS_MEMTEST_END=0x00101000
+CONFIG_BUTTON_CMD=y
CONFIG_FIT=y
CONFIG_FIT_SIGNATURE=y
CONFIG_FIT_VERBOSE=y
diff --git a/configs/sandbox_noinst_defconfig b/configs/sandbox_noinst_defconfig
index 137b3c6..f372301 100644
--- a/configs/sandbox_noinst_defconfig
+++ b/configs/sandbox_noinst_defconfig
@@ -281,8 +281,6 @@
CONFIG_ZSTD=y
CONFIG_SPL_LZMA=y
CONFIG_ERRNO_STR=y
-CONFIG_EFI_CAPSULE_ON_DISK=y
-CONFIG_EFI_CAPSULE_FIRMWARE_RAW=y
CONFIG_UNIT_TEST=y
CONFIG_SPL_UNIT_TEST=y
CONFIG_UT_TIME=y
diff --git a/configs/sandbox_spl_defconfig b/configs/sandbox_spl_defconfig
index d0cd91e..f7b92dc 100644
--- a/configs/sandbox_spl_defconfig
+++ b/configs/sandbox_spl_defconfig
@@ -249,8 +249,6 @@
CONFIG_SPL_LZMA=y
CONFIG_ERRNO_STR=y
CONFIG_SPL_HEXDUMP=y
-CONFIG_EFI_CAPSULE_ON_DISK=y
-CONFIG_EFI_CAPSULE_FIRMWARE_RAW=y
CONFIG_UNIT_TEST=y
CONFIG_SPL_UNIT_TEST=y
CONFIG_UT_TIME=y
diff --git a/configs/sandbox_vpl_defconfig b/configs/sandbox_vpl_defconfig
index b138b35..72483d8 100644
--- a/configs/sandbox_vpl_defconfig
+++ b/configs/sandbox_vpl_defconfig
@@ -252,8 +252,6 @@
CONFIG_ZSTD=y
# CONFIG_VPL_LZMA is not set
CONFIG_ERRNO_STR=y
-CONFIG_EFI_CAPSULE_ON_DISK=y
-CONFIG_EFI_CAPSULE_FIRMWARE_RAW=y
CONFIG_UNIT_TEST=y
CONFIG_SPL_UNIT_TEST=y
CONFIG_UT_TIME=y
diff --git a/configs/sei510_defconfig b/configs/sei510_defconfig
index c4a49fb..791979e 100644
--- a/configs/sei510_defconfig
+++ b/configs/sei510_defconfig
@@ -10,7 +10,7 @@
CONFIG_ENV_SIZE=0x10000
CONFIG_ENV_OFFSET=0xFFFF0000
CONFIG_DM_GPIO=y
-CONFIG_DEFAULT_DEVICE_TREE="meson-g12a-sei510"
+CONFIG_DEFAULT_DEVICE_TREE="amlogic/meson-g12a-sei510"
CONFIG_OF_LIBFDT_OVERLAY=y
CONFIG_DM_RESET=y
CONFIG_MESON_G12A=y
diff --git a/configs/sei610_defconfig b/configs/sei610_defconfig
index ae254c6..ce53743 100644
--- a/configs/sei610_defconfig
+++ b/configs/sei610_defconfig
@@ -10,7 +10,7 @@
CONFIG_ENV_SIZE=0x10000
CONFIG_ENV_OFFSET=0xFFFF0000
CONFIG_DM_GPIO=y
-CONFIG_DEFAULT_DEVICE_TREE="meson-sm1-sei610"
+CONFIG_DEFAULT_DEVICE_TREE="amlogic/meson-sm1-sei610"
CONFIG_OF_LIBFDT_OVERLAY=y
CONFIG_DM_RESET=y
CONFIG_MESON_G12A=y
diff --git a/configs/sheevaplug_defconfig b/configs/sheevaplug_defconfig
index 0af87dc4..b673b3f 100644
--- a/configs/sheevaplug_defconfig
+++ b/configs/sheevaplug_defconfig
@@ -13,7 +13,7 @@
CONFIG_TARGET_SHEEVAPLUG=y
CONFIG_ENV_SIZE=0x20000
CONFIG_ENV_OFFSET=0x80000
-CONFIG_DEFAULT_DEVICE_TREE="kirkwood-sheevaplug"
+CONFIG_DEFAULT_DEVICE_TREE="marvell/kirkwood-sheevaplug"
CONFIG_IDENT_STRING="\nMarvell-Sheevaplug"
CONFIG_SYS_LOAD_ADDR=0x800000
CONFIG_HAS_BOARD_SIZE_LIMIT=y
diff --git a/configs/socfpga_agilex5_defconfig b/configs/socfpga_agilex5_defconfig
new file mode 100644
index 0000000..f39954a
--- /dev/null
+++ b/configs/socfpga_agilex5_defconfig
@@ -0,0 +1,116 @@
+CONFIG_ARM=y
+CONFIG_SPL_LDSCRIPT="arch/arm/mach-socfpga/u-boot-spl-soc64.lds"
+CONFIG_SYS_SPI_U_BOOT_OFFS=0x04000000
+CONFIG_ARCH_SOCFPGA=y
+CONFIG_TEXT_BASE=0x80200000
+CONFIG_SYS_MALLOC_F_LEN=0x2000
+CONFIG_NR_DRAM_BANKS=2
+CONFIG_ENV_SIZE=0x2000
+CONFIG_ENV_OFFSET=0x04100000
+CONFIG_DM_GPIO=y
+CONFIG_DEFAULT_DEVICE_TREE="socfpga_agilex5_socdk"
+CONFIG_TARGET_SOCFPGA_AGILEX5_SOCDK=y
+CONFIG_IDENT_STRING="socfpga_agilex5"
+CONFIG_SPL_FS_FAT=y
+CONFIG_DISTRO_DEFAULTS=y
+CONFIG_FIT=y
+CONFIG_SPL_FIT_SIGNATURE=y
+CONFIG_SPL_LOAD_FIT=y
+CONFIG_SPL_LOAD_FIT_ADDRESS=0x82000000
+# CONFIG_USE_SPL_FIT_GENERATOR is not set
+CONFIG_QSPI_BOOT=y
+CONFIG_BOOTDELAY=5
+CONFIG_USE_BOOTARGS=y
+CONFIG_BOOTARGS="console=ttyS0,115200 initrd=0x90000000 root=/dev/ram0 rw init=/sbin/init ramdisk_size=10000000 earlycon panic=-1 nosmp kvm-arm.mode=nvhe"
+CONFIG_LEGACY_IMAGE_FORMAT=y
+# CONFIG_SPL_RAW_IMAGE_SUPPORT is not set
+CONFIG_SPL_CRC32=y
+CONFIG_SPL_CACHE=y
+CONFIG_SPL_ATF=y
+CONFIG_SPL_ATF_NO_PLATFORM_PARAM=y
+CONFIG_SYS_PROMPT="SOCFPGA_AGILEX5 # "
+CONFIG_CMD_NVEDIT_SELECT=y
+CONFIG_CMD_MEMTEST=y
+CONFIG_CMD_GPIO=y
+CONFIG_CMD_I2C=y
+CONFIG_CMD_SF=y
+CONFIG_DOS_PARTITION=y
+CONFIG_SPL_DOS_PARTITION=y
+CONFIG_SPL_SYS_DISABLE_DCACHE_OPS=y
+CONFIG_CMD_MTD=y
+# CONFIG_SPI_FLASH_USE_4K_SECTORS is not set
+CONFIG_CMD_SPI=y
+CONFIG_CMD_USB=y
+CONFIG_CMD_CACHE=y
+CONFIG_SPL_SPI_FLASH_MTD=y
+CONFIG_SPI_FLASH_MTD=y
+CONFIG_SPL_MTD_SUPPORT=y
+CONFIG_CMD_UBI=y
+CONFIG_CMD_UBIFS=y
+CONFIG_MTD_UBI=y
+CONFIG_MTD_UBI_WL_THRESHOLD=4096
+CONFIG_MTD_UBI_BEB_LIMIT=20
+# CONFIG_ISO_PARTITION is not set
+# CONFIG_EFI_PARTITION is not set
+CONFIG_OF_LIST=""
+CONFIG_ENV_IS_IN_UBI=y
+CONFIG_ENV_UBI_PART="root"
+CONFIG_ENV_UBI_VOLUME="env"
+CONFIG_SYS_RELOC_GD_ENV_ADDR=y
+CONFIG_NET_RANDOM_ETHADDR=y
+CONFIG_SPL_DM_SEQ_ALIAS=y
+CONFIG_SPL_ALTERA_SDRAM=y
+CONFIG_FPGA_INTEL_PR=y
+CONFIG_DWAPB_GPIO=y
+CONFIG_DM_I2C=y
+CONFIG_SYS_I2C_DW=y
+CONFIG_MISC=y
+CONFIG_MTD=y
+CONFIG_DM_MTD=y
+CONFIG_SF_DEFAULT_MODE=0x2003
+CONFIG_SPI_FLASH_SPANSION=y
+CONFIG_SPI_FLASH_STMICRO=y
+CONFIG_UBI_SILENCE_MSG=y
+CONFIG_DM_ETH=y
+CONFIG_RGMII=y
+CONFIG_DM_RESET=y
+CONFIG_SYS_NS16550_MEM32=y
+CONFIG_SPI=y
+CONFIG_CADENCE_QSPI=y
+CONFIG_DESIGNWARE_SPI=y
+CONFIG_USB=y
+CONFIG_USB_DWC2=y
+CONFIG_USB_XHCI_HCD=y
+CONFIG_UBIFS_SILENCE_MSG=y
+# CONFIG_SPL_USE_TINY_PRINTF is not set
+CONFIG_PANIC_HANG=y
+CONFIG_SPL_SPI_LOAD=y
+CONFIG_SYS_LOAD_ADDR=0x82000000
+CONFIG_WDT=y
+CONFIG_CMD_WDT=y
+CONFIG_DESIGNWARE_WATCHDOG=y
+CONFIG_SPL_WDT=y
+CONFIG_WATCHDOG_AUTOSTART=n
+CONFIG_TIMER=y
+CONFIG_DESIGNWARE_APB_TIMER=y
+CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y
+CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x80300000
+CONFIG_SPL_MAX_SIZE=0x40000
+CONFIG_SPL_HAS_BSS_LINKER_SECTION=y
+CONFIG_SPL_BSS_START_ADDR=0xbff00000
+# CONFIG_SPL_SHARES_INIT_SP_ADDR is not set
+CONFIG_SPL_STACK=0x7f000
+CONFIG_SYS_SPL_MALLOC=y
+CONFIG_HAS_CUSTOM_SPL_MALLOC_START=y
+CONFIG_CUSTOM_SYS_SPL_MALLOC_ADDR=0xbfa00000
+CONFIG_SYS_SPL_MALLOC_SIZE=0x500000
+CONFIG_SPL_BSS_MAX_SIZE=0x100000
+# CONFIG_EFI_LOADER is not set
+CONFIG_I3C=y
+CONFIG_DW_I3C_MASTER=y
+CONFIG_CMD_I3C=y
+CONFIG_SYS_MAXARGS=32
+CONFIG_CMD_TIMER=y
+# CONFIG_BOOTFILE="Image" is not set for CONFIG_SPL_ATF=y
+CONFIG_USE_BOOTFILE=y
+CONFIG_BOOTFILE="kernel.itb"
diff --git a/configs/soquartz-blade-rk3566_defconfig b/configs/soquartz-blade-rk3566_defconfig
index 9693cc2..b9ac6b9 100644
--- a/configs/soquartz-blade-rk3566_defconfig
+++ b/configs/soquartz-blade-rk3566_defconfig
@@ -2,19 +2,11 @@
CONFIG_SKIP_LOWLEVEL_INIT=y
CONFIG_COUNTER_FREQUENCY=24000000
CONFIG_ARCH_ROCKCHIP=y
-CONFIG_TEXT_BASE=0x00a00000
-CONFIG_SPL_LIBCOMMON_SUPPORT=y
-CONFIG_SPL_LIBGENERIC_SUPPORT=y
CONFIG_NR_DRAM_BANKS=2
-CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y
-CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0xc00000
CONFIG_DEFAULT_DEVICE_TREE="rk3566-soquartz-blade"
CONFIG_ROCKCHIP_RK3568=y
-CONFIG_SPL_ROCKCHIP_COMMON_BOARD=y
CONFIG_SPL_SERIAL=y
-CONFIG_SPL_STACK_R_ADDR=0x600000
CONFIG_TARGET_QUARTZ64_RK3566=y
-CONFIG_SPL_STACK=0x400000
CONFIG_DEBUG_UART_BASE=0xFE660000
CONFIG_DEBUG_UART_CLOCK=24000000
CONFIG_SYS_LOAD_ADDR=0xc00800
@@ -31,12 +23,7 @@
CONFIG_DISPLAY_BOARDINFO_LATE=y
CONFIG_SPL_MAX_SIZE=0x40000
CONFIG_SPL_PAD_TO=0x7f8000
-CONFIG_SPL_HAS_BSS_LINKER_SECTION=y
-CONFIG_SPL_BSS_START_ADDR=0x4000000
-CONFIG_SPL_BSS_MAX_SIZE=0x4000
# CONFIG_SPL_RAW_IMAGE_SUPPORT is not set
-# CONFIG_SPL_SHARES_INIT_SP_ADDR is not set
-CONFIG_SPL_STACK_R=y
CONFIG_SPL_ATF=y
CONFIG_CMD_GPIO=y
CONFIG_CMD_GPT=y
diff --git a/configs/soquartz-cm4-rk3566_defconfig b/configs/soquartz-cm4-rk3566_defconfig
index 9c6b12d..e87a639 100644
--- a/configs/soquartz-cm4-rk3566_defconfig
+++ b/configs/soquartz-cm4-rk3566_defconfig
@@ -2,19 +2,11 @@
CONFIG_SKIP_LOWLEVEL_INIT=y
CONFIG_COUNTER_FREQUENCY=24000000
CONFIG_ARCH_ROCKCHIP=y
-CONFIG_TEXT_BASE=0x00a00000
-CONFIG_SPL_LIBCOMMON_SUPPORT=y
-CONFIG_SPL_LIBGENERIC_SUPPORT=y
CONFIG_NR_DRAM_BANKS=2
-CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y
-CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0xc00000
CONFIG_DEFAULT_DEVICE_TREE="rk3566-soquartz-cm4"
CONFIG_ROCKCHIP_RK3568=y
-CONFIG_SPL_ROCKCHIP_COMMON_BOARD=y
CONFIG_SPL_SERIAL=y
-CONFIG_SPL_STACK_R_ADDR=0x600000
CONFIG_TARGET_QUARTZ64_RK3566=y
-CONFIG_SPL_STACK=0x400000
CONFIG_DEBUG_UART_BASE=0xFE660000
CONFIG_DEBUG_UART_CLOCK=24000000
CONFIG_SYS_LOAD_ADDR=0xc00800
@@ -31,12 +23,7 @@
CONFIG_DISPLAY_BOARDINFO_LATE=y
CONFIG_SPL_MAX_SIZE=0x40000
CONFIG_SPL_PAD_TO=0x7f8000
-CONFIG_SPL_HAS_BSS_LINKER_SECTION=y
-CONFIG_SPL_BSS_START_ADDR=0x4000000
-CONFIG_SPL_BSS_MAX_SIZE=0x4000
# CONFIG_SPL_RAW_IMAGE_SUPPORT is not set
-# CONFIG_SPL_SHARES_INIT_SP_ADDR is not set
-CONFIG_SPL_STACK_R=y
CONFIG_SPL_ATF=y
CONFIG_CMD_GPIO=y
CONFIG_CMD_GPT=y
diff --git a/configs/soquartz-model-a-rk3566_defconfig b/configs/soquartz-model-a-rk3566_defconfig
index fd72d78..b2c1684 100644
--- a/configs/soquartz-model-a-rk3566_defconfig
+++ b/configs/soquartz-model-a-rk3566_defconfig
@@ -2,19 +2,11 @@
CONFIG_SKIP_LOWLEVEL_INIT=y
CONFIG_COUNTER_FREQUENCY=24000000
CONFIG_ARCH_ROCKCHIP=y
-CONFIG_TEXT_BASE=0x00a00000
-CONFIG_SPL_LIBCOMMON_SUPPORT=y
-CONFIG_SPL_LIBGENERIC_SUPPORT=y
CONFIG_NR_DRAM_BANKS=2
-CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y
-CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0xc00000
CONFIG_DEFAULT_DEVICE_TREE="rk3566-soquartz-model-a"
CONFIG_ROCKCHIP_RK3568=y
-CONFIG_SPL_ROCKCHIP_COMMON_BOARD=y
CONFIG_SPL_SERIAL=y
-CONFIG_SPL_STACK_R_ADDR=0x600000
CONFIG_TARGET_QUARTZ64_RK3566=y
-CONFIG_SPL_STACK=0x400000
CONFIG_DEBUG_UART_BASE=0xFE660000
CONFIG_DEBUG_UART_CLOCK=24000000
CONFIG_SYS_LOAD_ADDR=0xc00800
@@ -31,12 +23,7 @@
CONFIG_DISPLAY_BOARDINFO_LATE=y
CONFIG_SPL_MAX_SIZE=0x40000
CONFIG_SPL_PAD_TO=0x7f8000
-CONFIG_SPL_HAS_BSS_LINKER_SECTION=y
-CONFIG_SPL_BSS_START_ADDR=0x4000000
-CONFIG_SPL_BSS_MAX_SIZE=0x4000
# CONFIG_SPL_RAW_IMAGE_SUPPORT is not set
-# CONFIG_SPL_SHARES_INIT_SP_ADDR is not set
-CONFIG_SPL_STACK_R=y
CONFIG_SPL_ATF=y
CONFIG_CMD_GPIO=y
CONFIG_CMD_GPT=y
diff --git a/configs/starfive_visionfive2_defconfig b/configs/starfive_visionfive2_defconfig
index c68f3c2..fa80d48 100644
--- a/configs/starfive_visionfive2_defconfig
+++ b/configs/starfive_visionfive2_defconfig
@@ -30,8 +30,8 @@
# CONFIG_OF_BOARD_FIXUP is not set
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
CONFIG_FIT=y
+CONFIG_BOOTSTD_DEFAULTS=y
CONFIG_SYS_BOOTM_LEN=0x4000000
-CONFIG_DISTRO_DEFAULTS=y
CONFIG_BOOTSTAGE=y
CONFIG_QSPI_BOOT=y
CONFIG_SD_BOOT=y
@@ -40,7 +40,6 @@
CONFIG_BOOTARGS="console=ttyS0,115200 debug rootwait earlycon=sbi"
CONFIG_USE_PREBOOT=y
CONFIG_PREBOOT="nvme scan; usb start; setenv fdt_addr ${fdtcontroladdr}; fdt addr ${fdtcontroladdr};"
-CONFIG_DEFAULT_FDT_FILE="starfive/jh7110-starfive-visionfive-2.dtb"
CONFIG_SYS_CBSIZE=256
CONFIG_SYS_PBSIZE=276
CONFIG_DISPLAY_CPUINFO=y
diff --git a/configs/stv0991_defconfig b/configs/stv0991_defconfig
deleted file mode 100644
index e70db42..0000000
--- a/configs/stv0991_defconfig
+++ /dev/null
@@ -1,44 +0,0 @@
-CONFIG_ARM=y
-CONFIG_SYS_DCACHE_OFF=y
-CONFIG_TARGET_STV0991=y
-CONFIG_TEXT_BASE=0x00010000
-CONFIG_SYS_MALLOC_LEN=0x14000
-CONFIG_NR_DRAM_BANKS=1
-CONFIG_ENV_SIZE=0x10000
-CONFIG_ENV_OFFSET=0x30000
-CONFIG_ENV_SECT_SIZE=0x10000
-CONFIG_DEFAULT_DEVICE_TREE="stv0991"
-CONFIG_SYS_LOAD_ADDR=0x0
-CONFIG_ENV_ADDR=0x188000
-CONFIG_SYS_MEMTEST_START=0x00000000
-CONFIG_SYS_MEMTEST_END=0x00100000
-CONFIG_BOOTDELAY=3
-CONFIG_AUTOBOOT_KEYED=y
-CONFIG_AUTOBOOT_PROMPT="Hit SPACE in %d seconds to stop autoboot.\n"
-CONFIG_AUTOBOOT_STOP_STR=" "
-CONFIG_USE_BOOTCOMMAND=y
-CONFIG_BOOTCOMMAND="go 0x40040000"
-CONFIG_SYS_PBSIZE=1050
-# CONFIG_DISPLAY_CPUINFO is not set
-# CONFIG_DISPLAY_BOARDINFO is not set
-CONFIG_BOARD_EARLY_INIT_F=y
-# CONFIG_AUTO_COMPLETE is not set
-CONFIG_SYS_PROMPT="STV0991> "
-CONFIG_CMD_MEMTEST=y
-CONFIG_CMD_SPI=y
-# CONFIG_CMD_SETEXPR is not set
-CONFIG_CMD_PING=y
-CONFIG_OF_CONTROL=y
-CONFIG_ENV_IS_IN_SPI_FLASH=y
-# CONFIG_MMC is not set
-CONFIG_SPI_FLASH_STMICRO=y
-CONFIG_SPI_FLASH_WINBOND=y
-CONFIG_PHY_MICREL=y
-CONFIG_PHY_MICREL_KSZ8XXX=y
-CONFIG_PHY_RESET_DELAY=10000
-CONFIG_ETH_DESIGNWARE=y
-CONFIG_DW_ALTDESCRIPTOR=y
-CONFIG_MII=y
-CONFIG_CADENCE_QSPI=y
-CONFIG_HAS_CQSPI_REF_CLK=y
-CONFIG_CQSPI_REF_CLK=3000000
diff --git a/configs/tools-only_defconfig b/configs/tools-only_defconfig
index b54d2ce..5de482a 100644
--- a/configs/tools-only_defconfig
+++ b/configs/tools-only_defconfig
@@ -12,10 +12,10 @@
# CONFIG_BOOTSTD_FULL is not set
# CONFIG_BOOTMETH_CROS is not set
# CONFIG_BOOTMETH_VBE is not set
+# CONFIG_BOOTM is not set
CONFIG_USE_BOOTCOMMAND=y
CONFIG_BOOTCOMMAND="run distro_bootcmd"
# CONFIG_CMD_BOOTD is not set
-# CONFIG_CMD_BOOTM is not set
# CONFIG_CMD_BOOTI is not set
# CONFIG_CMD_ELF is not set
# CONFIG_CMD_EXTENSION is not set
diff --git a/configs/toybrick-rk3588_defconfig b/configs/toybrick-rk3588_defconfig
new file mode 100644
index 0000000..6ee92e9
--- /dev/null
+++ b/configs/toybrick-rk3588_defconfig
@@ -0,0 +1,68 @@
+CONFIG_ARM=y
+CONFIG_SKIP_LOWLEVEL_INIT=y
+CONFIG_COUNTER_FREQUENCY=24000000
+CONFIG_ARCH_ROCKCHIP=y
+CONFIG_NR_DRAM_BANKS=2
+CONFIG_DEFAULT_DEVICE_TREE="rk3588-toybrick-x0"
+CONFIG_ROCKCHIP_RK3588=y
+CONFIG_SPL_SERIAL=y
+CONFIG_TARGET_TOYBRICK_RK3588=y
+CONFIG_DEBUG_UART_BASE=0xFEB50000
+CONFIG_DEBUG_UART_CLOCK=24000000
+CONFIG_SYS_LOAD_ADDR=0xc00800
+CONFIG_DEBUG_UART=y
+CONFIG_FIT=y
+CONFIG_FIT_VERBOSE=y
+CONFIG_SPL_FIT_SIGNATURE=y
+CONFIG_SPL_LOAD_FIT=y
+CONFIG_LEGACY_IMAGE_FORMAT=y
+CONFIG_OF_BOARD_SETUP=y
+CONFIG_DEFAULT_FDT_FILE="rockchip/rk3588-toybrick-x0.dtb"
+# CONFIG_DISPLAY_CPUINFO is not set
+CONFIG_DISPLAY_BOARDINFO_LATE=y
+CONFIG_SPL_MAX_SIZE=0x40000
+CONFIG_SPL_PAD_TO=0x7f8000
+# CONFIG_SPL_RAW_IMAGE_SUPPORT is not set
+CONFIG_SPL_ATF=y
+CONFIG_CMD_GPIO=y
+CONFIG_CMD_GPT=y
+CONFIG_CMD_MMC=y
+CONFIG_CMD_USB=y
+# CONFIG_CMD_SETEXPR is not set
+CONFIG_CMD_REGULATOR=y
+# CONFIG_SPL_DOS_PARTITION is not set
+CONFIG_SPL_OF_CONTROL=y
+CONFIG_OF_LIVE=y
+CONFIG_OF_SPL_REMOVE_PROPS="pinctrl-0 pinctrl-names clock-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents"
+CONFIG_ENV_IS_IN_MMC=y
+CONFIG_SPL_REGMAP=y
+CONFIG_SPL_SYSCON=y
+CONFIG_SPL_CLK=y
+CONFIG_ROCKCHIP_GPIO=y
+CONFIG_SYS_I2C_ROCKCHIP=y
+CONFIG_MISC=y
+CONFIG_SUPPORT_EMMC_RPMB=y
+CONFIG_MMC_HS400_ES_SUPPORT=y
+CONFIG_MMC_HS400_SUPPORT=y
+CONFIG_MMC_DW=y
+CONFIG_MMC_DW_ROCKCHIP=y
+CONFIG_MMC_SDHCI=y
+CONFIG_MMC_SDHCI_SDMA=y
+CONFIG_MMC_SDHCI_ROCKCHIP=y
+CONFIG_PHY_REALTEK=y
+CONFIG_DWC_ETH_QOS=y
+CONFIG_DWC_ETH_QOS_ROCKCHIP=y
+CONFIG_PHY_ROCKCHIP_INNO_USB2=y
+CONFIG_REGULATOR_PWM=y
+CONFIG_PWM_ROCKCHIP=y
+CONFIG_SPL_RAM=y
+CONFIG_BAUDRATE=1500000
+CONFIG_DEBUG_UART_SHIFT=2
+CONFIG_SYS_NS16550_MEM32=y
+CONFIG_SYSRESET=y
+CONFIG_USB=y
+CONFIG_USB_EHCI_HCD=y
+CONFIG_USB_EHCI_GENERIC=y
+CONFIG_USB_OHCI_HCD=y
+CONFIG_USB_OHCI_GENERIC=y
+CONFIG_ERRNO_STR=y
diff --git a/configs/turing-rk1-rk3588_defconfig b/configs/turing-rk1-rk3588_defconfig
index 0f903cf..07f7b84 100644
--- a/configs/turing-rk1-rk3588_defconfig
+++ b/configs/turing-rk1-rk3588_defconfig
@@ -3,22 +3,14 @@
CONFIG_SYS_HAS_NONCACHED_MEMORY=y
CONFIG_COUNTER_FREQUENCY=24000000
CONFIG_ARCH_ROCKCHIP=y
-CONFIG_TEXT_BASE=0x00a00000
-CONFIG_SPL_LIBCOMMON_SUPPORT=y
-CONFIG_SPL_LIBGENERIC_SUPPORT=y
CONFIG_NR_DRAM_BANKS=2
-CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y
-CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0xc00000
CONFIG_SF_DEFAULT_SPEED=24000000
CONFIG_SF_DEFAULT_MODE=0x2000
CONFIG_DEFAULT_DEVICE_TREE="rk3588-turing-rk1"
CONFIG_ROCKCHIP_RK3588=y
-CONFIG_SPL_ROCKCHIP_COMMON_BOARD=y
CONFIG_ROCKCHIP_SPI_IMAGE=y
CONFIG_SPL_SERIAL=y
-CONFIG_SPL_STACK_R_ADDR=0x600000
CONFIG_TARGET_TURINGRK1_RK3588=y
-CONFIG_SPL_STACK=0x400000
CONFIG_DEBUG_UART_BASE=0xFEBC0000
CONFIG_DEBUG_UART_CLOCK=24000000
CONFIG_SPL_SPI_FLASH_SUPPORT=y
@@ -38,12 +30,7 @@
CONFIG_DISPLAY_BOARDINFO_LATE=y
CONFIG_SPL_MAX_SIZE=0x40000
CONFIG_SPL_PAD_TO=0x7f8000
-CONFIG_SPL_HAS_BSS_LINKER_SECTION=y
-CONFIG_SPL_BSS_START_ADDR=0x4000000
-CONFIG_SPL_BSS_MAX_SIZE=0x4000
# CONFIG_SPL_RAW_IMAGE_SUPPORT is not set
-# CONFIG_SPL_SHARES_INIT_SP_ADDR is not set
-CONFIG_SPL_STACK_R=y
CONFIG_SPL_SPI_LOAD=y
CONFIG_SYS_SPI_U_BOOT_OFFS=0x60000
CONFIG_SPL_ATF=y
diff --git a/configs/turris_omnia_defconfig b/configs/turris_omnia_defconfig
index 2914840..f2b3911 100644
--- a/configs/turris_omnia_defconfig
+++ b/configs/turris_omnia_defconfig
@@ -31,6 +31,7 @@
CONFIG_OF_BOARD_FIXUP=y
CONFIG_SYS_MEMTEST_START=0x00800000
CONFIG_SYS_MEMTEST_END=0x00ffffff
+CONFIG_LTO=y
CONFIG_HAS_BOARD_SIZE_LIMIT=y
CONFIG_BOARD_SIZE_LIMIT=983040
CONFIG_FIT=y
@@ -64,6 +65,7 @@
CONFIG_CMD_MMC=y
CONFIG_CMD_MTD=y
CONFIG_CMD_PCI=y
+CONFIG_CMD_POWEROFF=y
CONFIG_CMD_SATA=y
CONFIG_CMD_SPI=y
CONFIG_CMD_USB=y
@@ -71,6 +73,7 @@
CONFIG_CMD_TFTPPUT=y
CONFIG_CMD_CACHE=y
CONFIG_CMD_TIME=y
+CONFIG_CMD_RNG=y
CONFIG_CMD_AES=y
CONFIG_CMD_HASH=y
CONFIG_CMD_BTRFS=y
@@ -105,6 +108,7 @@
CONFIG_PCI_MVEBU=y
CONFIG_PINCTRL=y
CONFIG_PINCTRL_ARMADA_38X=y
+CONFIG_DM_RNG=y
CONFIG_DM_RTC=y
CONFIG_RTC_ARMADA38X=y
CONFIG_SERIAL_PROBE_ALL=y
@@ -112,6 +116,8 @@
CONFIG_DEBUG_UART_SHIFT=2
CONFIG_SYS_NS16550=y
CONFIG_KIRKWOOD_SPI=y
+CONFIG_SYSRESET=y
+CONFIG_SYSRESET_CMD_POWEROFF=y
CONFIG_USB=y
CONFIG_USB_XHCI_HCD=y
CONFIG_USB_EHCI_HCD=y
diff --git a/configs/u200_defconfig b/configs/u200_defconfig
index 21c90e7..879ae0d 100644
--- a/configs/u200_defconfig
+++ b/configs/u200_defconfig
@@ -6,7 +6,7 @@
CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x20000000
CONFIG_ENV_SIZE=0x2000
CONFIG_DM_GPIO=y
-CONFIG_DEFAULT_DEVICE_TREE="meson-g12a-u200"
+CONFIG_DEFAULT_DEVICE_TREE="amlogic/meson-g12a-u200"
CONFIG_OF_LIBFDT_OVERLAY=y
CONFIG_DM_RESET=y
CONFIG_MESON_G12A=y
diff --git a/configs/verdin-am62_r5_defconfig b/configs/verdin-am62_r5_defconfig
index a3febdc..5b4b81c 100644
--- a/configs/verdin-am62_r5_defconfig
+++ b/configs/verdin-am62_r5_defconfig
@@ -35,7 +35,7 @@
CONFIG_SPL_SYS_REPORT_STACK_F_USAGE=y
CONFIG_SPL_SYS_MALLOC_SIMPLE=y
CONFIG_SPL_STACK_R=y
-CONFIG_SPL_STACK_R_MALLOC_SIMPLE_LEN=0x140000
+CONFIG_SPL_STACK_R_MALLOC_SIMPLE_LEN=0x200000
CONFIG_SPL_SEPARATE_BSS=y
CONFIG_SPL_SYS_MALLOC=y
CONFIG_SPL_HAS_CUSTOM_MALLOC_START=y
diff --git a/configs/verdin-imx8mm_defconfig b/configs/verdin-imx8mm_defconfig
index afa42c1..4f1480c 100644
--- a/configs/verdin-imx8mm_defconfig
+++ b/configs/verdin-imx8mm_defconfig
@@ -8,7 +8,7 @@
CONFIG_ENV_SIZE=0x2000
CONFIG_ENV_OFFSET=0xFFFFDE00
CONFIG_DM_GPIO=y
-CONFIG_DEFAULT_DEVICE_TREE="imx8mm-verdin-wifi-dev"
+CONFIG_DEFAULT_DEVICE_TREE="freescale/imx8mm-verdin-wifi-dev"
CONFIG_SPL_TEXT_BASE=0x7E1000
CONFIG_TARGET_VERDIN_IMX8MM=y
CONFIG_OF_LIBFDT_OVERLAY=y
diff --git a/configs/verdin-imx8mp_defconfig b/configs/verdin-imx8mp_defconfig
index 7ac5e65..4490a4a 100644
--- a/configs/verdin-imx8mp_defconfig
+++ b/configs/verdin-imx8mp_defconfig
@@ -12,10 +12,11 @@
CONFIG_SYS_I2C_MXC_I2C3=y
CONFIG_SYS_I2C_MXC_I2C4=y
CONFIG_DM_GPIO=y
-CONFIG_DEFAULT_DEVICE_TREE="imx8mp-verdin-wifi-dev"
+CONFIG_DEFAULT_DEVICE_TREE="freescale/imx8mp-verdin-wifi-dev"
CONFIG_SPL_TEXT_BASE=0x920000
CONFIG_TARGET_VERDIN_IMX8MP=y
CONFIG_OF_LIBFDT_OVERLAY=y
+CONFIG_DM_RESET=y
CONFIG_SYS_MONITOR_LEN=524288
CONFIG_SPL_MMC=y
CONFIG_SPL_SERIAL=y
@@ -26,6 +27,7 @@
CONFIG_IMX_BOOTAUX=y
CONFIG_SPL_IMX_ROMAPI_LOADADDR=0x48000000
CONFIG_SYS_LOAD_ADDR=0x48200000
+CONFIG_PCI=y
CONFIG_SYS_MEMTEST_START=0x40000000
CONFIG_SYS_MEMTEST_END=0x80000000
CONFIG_REMAKE_ELF=y
@@ -76,6 +78,7 @@
CONFIG_CMD_GPIO=y
CONFIG_CMD_I2C=y
CONFIG_CMD_MMC=y
+CONFIG_CMD_PCI=y
CONFIG_CMD_READ=y
CONFIG_CMD_USB=y
CONFIG_CMD_USB_MASS_STORAGE=y
@@ -145,8 +148,11 @@
CONFIG_FEC_MXC=y
CONFIG_RGMII=y
CONFIG_MII=y
+CONFIG_NVME_PCI=y
+CONFIG_PCIE_DW_IMX=y
CONFIG_PHY=y
CONFIG_PHY_IMX8MQ_USB=y
+CONFIG_PHY_IMX8M_PCIE=y
CONFIG_PINCTRL=y
CONFIG_SPL_PINCTRL=y
CONFIG_PINCTRL_IMX8M=y
diff --git a/configs/warp7_defconfig b/configs/warp7_defconfig
index 9b518a1..48042b7 100644
--- a/configs/warp7_defconfig
+++ b/configs/warp7_defconfig
@@ -67,6 +67,8 @@
CONFIG_SPECIFY_CONSOLE_INDEX=y
CONFIG_DM_SERIAL=y
CONFIG_MXC_UART=y
+CONFIG_SYSRESET=y
+CONFIG_SYSRESET_WATCHDOG=y
CONFIG_IMX_THERMAL=y
CONFIG_USB=y
CONFIG_USB_EHCI_HCD=y
@@ -80,5 +82,6 @@
CONFIG_USB_ETHER=y
CONFIG_USB_ETH_CDC=y
CONFIG_USBNET_HOST_ADDR="de:ad:be:af:00:00"
+CONFIG_IMX_WATCHDOG=y
CONFIG_OPTEE_TZDRAM_SIZE=0x3000000
CONFIG_BOOTM_OPTEE=y
diff --git a/configs/wetek-core2_defconfig b/configs/wetek-core2_defconfig
index 01ffb8b..c4b126c 100644
--- a/configs/wetek-core2_defconfig
+++ b/configs/wetek-core2_defconfig
@@ -6,7 +6,7 @@
CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x20000000
CONFIG_ENV_SIZE=0x2000
CONFIG_DM_GPIO=y
-CONFIG_DEFAULT_DEVICE_TREE="meson-gxm-wetek-core2"
+CONFIG_DEFAULT_DEVICE_TREE="amlogic/meson-gxm-wetek-core2"
CONFIG_OF_LIBFDT_OVERLAY=y
CONFIG_DM_RESET=y
CONFIG_MESON_GXM=y
diff --git a/configs/xilinx_mbv32_defconfig b/configs/xilinx_mbv32_defconfig
index 2689495..4113409 100644
--- a/configs/xilinx_mbv32_defconfig
+++ b/configs/xilinx_mbv32_defconfig
@@ -1,30 +1,43 @@
CONFIG_RISCV=y
-CONFIG_TEXT_BASE=0x21200000
-CONFIG_SYS_MALLOC_LEN=0x800000
+CONFIG_SYS_MALLOC_LEN=0xe00000
CONFIG_NR_DRAM_BANKS=1
CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y
-CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x20200000
+CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x21200000
CONFIG_ENV_SIZE=0x20000
CONFIG_DEFAULT_DEVICE_TREE="xilinx-mbv32"
+CONFIG_SPL_STACK=0x20200000
+CONFIG_SPL_SIZE_LIMIT=0x40000
+CONFIG_SPL=y
CONFIG_DEBUG_UART_BASE=0x40600000
CONFIG_DEBUG_UART_CLOCK=1000000
CONFIG_SYS_CLK_FREQ=100000000
CONFIG_BOOT_SCRIPT_OFFSET=0x0
-CONFIG_SYS_LOAD_ADDR=0x80200000
+CONFIG_SYS_LOAD_ADDR=0x20200000
CONFIG_DEBUG_UART=y
CONFIG_TARGET_XILINX_MBV=y
+# CONFIG_SPL_SMP is not set
+CONFIG_REMAKE_ELF=y
CONFIG_FIT=y
+CONFIG_SPL_LOAD_FIT_ADDRESS=0x20200000
CONFIG_DISTRO_DEFAULTS=y
CONFIG_DISPLAY_CPUINFO=y
CONFIG_DISPLAY_BOARDINFO=y
# CONFIG_BOARD_LATE_INIT is not set
+CONFIG_SPL_MAX_SIZE=0x40000
+CONFIG_SPL_BSS_START_ADDR=0x24000000
+CONFIG_SPL_BSS_MAX_SIZE=0x80000
+# CONFIG_SPL_SHARES_INIT_SP_ADDR is not set
+CONFIG_SPL_SYS_MALLOC=y
+CONFIG_SPL_SYS_MALLOC_SIZE=0x800000
# CONFIG_CMD_MII is not set
CONFIG_CMD_TIMER=y
-CONFIG_OF_EMBED=y
CONFIG_SYS_RELOC_GD_ENV_ADDR=y
+CONFIG_SPL_DM_SEQ_ALIAS=y
CONFIG_DM_MTD=y
CONFIG_DEBUG_UART_ANNOUNCE=y
CONFIG_DEBUG_UART_SKIP_INIT=y
CONFIG_XILINX_UARTLITE=y
CONFIG_XILINX_TIMER=y
+# CONFIG_BINMAN_FDT is not set
CONFIG_PANIC_HANG=y
+CONFIG_SPL_GZIP=y
diff --git a/configs/xilinx_mbv32_smode_defconfig b/configs/xilinx_mbv32_smode_defconfig
index c724d1b..9938147 100644
--- a/configs/xilinx_mbv32_smode_defconfig
+++ b/configs/xilinx_mbv32_smode_defconfig
@@ -1,27 +1,40 @@
CONFIG_RISCV=y
-CONFIG_TEXT_BASE=0x21200000
-CONFIG_SYS_MALLOC_LEN=0x800000
+CONFIG_SYS_MALLOC_LEN=0xe00000
CONFIG_NR_DRAM_BANKS=1
CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y
-CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x20200000
+CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x21200000
CONFIG_ENV_SIZE=0x20000
CONFIG_DEFAULT_DEVICE_TREE="xilinx-mbv32"
+CONFIG_SPL_STACK=0x20200000
+CONFIG_SPL_SIZE_LIMIT=0x40000
+CONFIG_SPL=y
CONFIG_DEBUG_UART_BASE=0x40600000
CONFIG_DEBUG_UART_CLOCK=1000000
CONFIG_SYS_CLK_FREQ=100000000
CONFIG_BOOT_SCRIPT_OFFSET=0x0
-CONFIG_SYS_LOAD_ADDR=0x80200000
+CONFIG_SYS_LOAD_ADDR=0x20200000
CONFIG_TARGET_XILINX_MBV=y
+CONFIG_SPL_OPENSBI_LOAD_ADDR=0x20100000
CONFIG_RISCV_SMODE=y
+# CONFIG_SPL_SMP is not set
+CONFIG_REMAKE_ELF=y
CONFIG_FIT=y
+CONFIG_SPL_LOAD_FIT_ADDRESS=0x20200000
CONFIG_DISTRO_DEFAULTS=y
CONFIG_DISPLAY_CPUINFO=y
CONFIG_DISPLAY_BOARDINFO=y
# CONFIG_BOARD_LATE_INIT is not set
+CONFIG_SPL_MAX_SIZE=0x40000
+CONFIG_SPL_BSS_START_ADDR=0x24000000
+CONFIG_SPL_BSS_MAX_SIZE=0x80000
+# CONFIG_SPL_SHARES_INIT_SP_ADDR is not set
+CONFIG_SPL_SYS_MALLOC=y
+CONFIG_SPL_SYS_MALLOC_SIZE=0x800000
+CONFIG_SPL_OPENSBI_SCRATCH_OPTIONS=0x2
# CONFIG_CMD_MII is not set
CONFIG_CMD_TIMER=y
-CONFIG_OF_EMBED=y
CONFIG_SYS_RELOC_GD_ENV_ADDR=y
+CONFIG_SPL_DM_SEQ_ALIAS=y
CONFIG_DM_MTD=y
CONFIG_DEBUG_UART_UARTLITE=y
CONFIG_DEBUG_UART_ANNOUNCE=y
@@ -29,4 +42,6 @@
CONFIG_XILINX_UARTLITE=y
# CONFIG_RISCV_TIMER is not set
CONFIG_XILINX_TIMER=y
+# CONFIG_BINMAN_FDT is not set
CONFIG_PANIC_HANG=y
+CONFIG_SPL_GZIP=y
diff --git a/configs/xilinx_versal_mini_defconfig b/configs/xilinx_versal_mini_defconfig
index 9d3924c..143d262 100644
--- a/configs/xilinx_versal_mini_defconfig
+++ b/configs/xilinx_versal_mini_defconfig
@@ -18,6 +18,7 @@
CONFIG_SYS_MEMTEST_END=0x00001000
# CONFIG_EXPERT is not set
CONFIG_REMAKE_ELF=y
+# CONFIG_BOOTM is not set
# CONFIG_LEGACY_IMAGE_FORMAT is not set
# CONFIG_AUTOBOOT is not set
CONFIG_SYS_CBSIZE=1024
@@ -33,7 +34,6 @@
CONFIG_SYS_PROMPT="Versal> "
# CONFIG_CMD_CONSOLE is not set
# CONFIG_CMD_BOOTD is not set
-# CONFIG_CMD_BOOTM is not set
# CONFIG_CMD_BOOTI is not set
# CONFIG_CMD_ELF is not set
# CONFIG_CMD_FDT is not set
diff --git a/configs/xilinx_versal_mini_emmc0_defconfig b/configs/xilinx_versal_mini_emmc0_defconfig
index 5c949e3..b0e3462 100644
--- a/configs/xilinx_versal_mini_emmc0_defconfig
+++ b/configs/xilinx_versal_mini_emmc0_defconfig
@@ -15,6 +15,7 @@
CONFIG_SYS_LOAD_ADDR=0x8000000
# CONFIG_EXPERT is not set
CONFIG_REMAKE_ELF=y
+# CONFIG_BOOTM is not set
# CONFIG_AUTOBOOT is not set
CONFIG_SYS_CBSIZE=1024
CONFIG_SYS_PBSIZE=1049
@@ -30,7 +31,6 @@
# CONFIG_CMD_BDI is not set
# CONFIG_CMD_CONSOLE is not set
# CONFIG_CMD_BOOTD is not set
-# CONFIG_CMD_BOOTM is not set
# CONFIG_CMD_BOOTI is not set
# CONFIG_CMD_ELF is not set
# CONFIG_CMD_FDT is not set
diff --git a/configs/xilinx_versal_mini_emmc1_defconfig b/configs/xilinx_versal_mini_emmc1_defconfig
index 04cba5b..559b32c 100644
--- a/configs/xilinx_versal_mini_emmc1_defconfig
+++ b/configs/xilinx_versal_mini_emmc1_defconfig
@@ -15,6 +15,7 @@
CONFIG_SYS_LOAD_ADDR=0x8000000
# CONFIG_EXPERT is not set
CONFIG_REMAKE_ELF=y
+# CONFIG_BOOTM is not set
# CONFIG_AUTOBOOT is not set
CONFIG_SYS_CBSIZE=1024
CONFIG_SYS_PBSIZE=1049
@@ -30,7 +31,6 @@
# CONFIG_CMD_BDI is not set
# CONFIG_CMD_CONSOLE is not set
# CONFIG_CMD_BOOTD is not set
-# CONFIG_CMD_BOOTM is not set
# CONFIG_CMD_BOOTI is not set
# CONFIG_CMD_ELF is not set
# CONFIG_CMD_FDT is not set
diff --git a/configs/xilinx_versal_mini_ospi_defconfig b/configs/xilinx_versal_mini_ospi_defconfig
index 7a11035..c02c6ba 100644
--- a/configs/xilinx_versal_mini_ospi_defconfig
+++ b/configs/xilinx_versal_mini_ospi_defconfig
@@ -19,6 +19,7 @@
CONFIG_LTO=y
# CONFIG_EXPERT is not set
CONFIG_REMAKE_ELF=y
+# CONFIG_BOOTM is not set
# CONFIG_AUTOBOOT is not set
CONFIG_SYS_CONSOLE_INFO_QUIET=y
# CONFIG_DISPLAY_CPUINFO is not set
@@ -31,7 +32,6 @@
# CONFIG_CMD_BDI is not set
# CONFIG_CMD_CONSOLE is not set
# CONFIG_CMD_BOOTD is not set
-# CONFIG_CMD_BOOTM is not set
# CONFIG_CMD_BOOTI is not set
# CONFIG_CMD_ELF is not set
# CONFIG_CMD_FDT is not set
diff --git a/configs/xilinx_versal_mini_qspi_defconfig b/configs/xilinx_versal_mini_qspi_defconfig
index 58945a1..4d4b59a 100644
--- a/configs/xilinx_versal_mini_qspi_defconfig
+++ b/configs/xilinx_versal_mini_qspi_defconfig
@@ -17,6 +17,7 @@
CONFIG_LTO=y
# CONFIG_EXPERT is not set
CONFIG_REMAKE_ELF=y
+# CONFIG_BOOTM is not set
# CONFIG_AUTOBOOT is not set
# CONFIG_ARCH_FIXUP_FDT_MEMORY is not set
CONFIG_LOGLEVEL=0
@@ -32,7 +33,6 @@
# CONFIG_CMD_BDI is not set
# CONFIG_CMD_CONSOLE is not set
# CONFIG_CMD_BOOTD is not set
-# CONFIG_CMD_BOOTM is not set
# CONFIG_CMD_BOOTI is not set
# CONFIG_CMD_ELF is not set
# CONFIG_CMD_FDT is not set
diff --git a/configs/xilinx_versal_net_mini_defconfig b/configs/xilinx_versal_net_mini_defconfig
index 7dac1ec..317fc8e 100644
--- a/configs/xilinx_versal_net_mini_defconfig
+++ b/configs/xilinx_versal_net_mini_defconfig
@@ -20,6 +20,7 @@
CONFIG_SYS_MEMTEST_END=0x00001000
# CONFIG_EXPERT is not set
CONFIG_REMAKE_ELF=y
+# CONFIG_BOOTM is not set
# CONFIG_LEGACY_IMAGE_FORMAT is not set
# CONFIG_AUTOBOOT is not set
# CONFIG_ARCH_FIXUP_FDT_MEMORY is not set
@@ -33,7 +34,6 @@
CONFIG_SYS_PROMPT="Versal NET> "
# CONFIG_CMD_CONSOLE is not set
# CONFIG_CMD_BOOTD is not set
-# CONFIG_CMD_BOOTM is not set
# CONFIG_CMD_BOOTI is not set
# CONFIG_CMD_ELF is not set
# CONFIG_CMD_FDT is not set
diff --git a/configs/xilinx_versal_net_mini_emmc_defconfig b/configs/xilinx_versal_net_mini_emmc_defconfig
index fc88eee..31c4432 100644
--- a/configs/xilinx_versal_net_mini_emmc_defconfig
+++ b/configs/xilinx_versal_net_mini_emmc_defconfig
@@ -25,7 +25,7 @@
# CONFIG_CMD_BDI is not set
# CONFIG_CMD_CONSOLE is not set
# CONFIG_CMD_BOOTD is not set
-# CONFIG_CMD_BOOTM is not set
+# CONFIG_BOOTM is not set
# CONFIG_CMD_BOOTI is not set
# CONFIG_CMD_ELF is not set
# CONFIG_CMD_FDT is not set
diff --git a/configs/xilinx_versal_net_mini_ospi_defconfig b/configs/xilinx_versal_net_mini_ospi_defconfig
index d78c9f8..d0d91f9 100644
--- a/configs/xilinx_versal_net_mini_ospi_defconfig
+++ b/configs/xilinx_versal_net_mini_ospi_defconfig
@@ -30,7 +30,7 @@
# CONFIG_CMD_BDI is not set
# CONFIG_CMD_CONSOLE is not set
# CONFIG_CMD_BOOTD is not set
-# CONFIG_CMD_BOOTM is not set
+# CONFIG_BOOTM is not set
# CONFIG_CMD_BOOTI is not set
# CONFIG_CMD_ELF is not set
# CONFIG_CMD_FDT is not set
diff --git a/configs/xilinx_versal_net_mini_qspi_defconfig b/configs/xilinx_versal_net_mini_qspi_defconfig
index b0567f8..48b6d86 100644
--- a/configs/xilinx_versal_net_mini_qspi_defconfig
+++ b/configs/xilinx_versal_net_mini_qspi_defconfig
@@ -31,7 +31,7 @@
# CONFIG_CMD_BDI is not set
# CONFIG_CMD_CONSOLE is not set
# CONFIG_CMD_BOOTD is not set
-# CONFIG_CMD_BOOTM is not set
+# CONFIG_BOOTM is not set
# CONFIG_CMD_BOOTI is not set
# CONFIG_CMD_ELF is not set
# CONFIG_CMD_FDT is not set
diff --git a/configs/xilinx_versal_net_virt_defconfig b/configs/xilinx_versal_net_virt_defconfig
index 29cebe2..40c6a29 100644
--- a/configs/xilinx_versal_net_virt_defconfig
+++ b/configs/xilinx_versal_net_virt_defconfig
@@ -60,6 +60,9 @@
CONFIG_OF_BOARD=y
CONFIG_DTB_RESELECT=y
CONFIG_MULTI_DTB_FIT=y
+CONFIG_ENV_IS_NOWHERE=y
+CONFIG_ENV_IS_IN_FAT=y
+CONFIG_ENV_IS_IN_SPI_FLASH=y
CONFIG_SYS_REDUNDAND_ENVIRONMENT=y
CONFIG_SYS_RELOC_GD_ENV_ADDR=y
CONFIG_NET_RANDOM_ETHADDR=y
diff --git a/configs/xilinx_zynqmp_kria_defconfig b/configs/xilinx_zynqmp_kria_defconfig
index 7cb8b62..7af8b27 100644
--- a/configs/xilinx_zynqmp_kria_defconfig
+++ b/configs/xilinx_zynqmp_kria_defconfig
@@ -155,7 +155,6 @@
CONFIG_MMC_SDHCI=y
CONFIG_MMC_SDHCI_ZYNQ=y
CONFIG_DM_MTD=y
-CONFIG_SPI_FLASH_BAR=y
CONFIG_SPI_FLASH_STMICRO=y
# CONFIG_SPI_FLASH_USE_4K_SECTORS is not set
CONFIG_SPI_FLASH_MTD=y
diff --git a/configs/xilinx_zynqmp_mini_defconfig b/configs/xilinx_zynqmp_mini_defconfig
index 7fdd2ee..40d4a4a 100644
--- a/configs/xilinx_zynqmp_mini_defconfig
+++ b/configs/xilinx_zynqmp_mini_defconfig
@@ -13,6 +13,7 @@
CONFIG_SYS_MEMTEST_START=0x00000000
CONFIG_SYS_MEMTEST_END=0x00001000
CONFIG_REMAKE_ELF=y
+# CONFIG_BOOTM is not set
# CONFIG_LEGACY_IMAGE_FORMAT is not set
# CONFIG_AUTOBOOT is not set
CONFIG_SYS_CBSIZE=1024
@@ -26,7 +27,6 @@
# CONFIG_CMD_BDI is not set
# CONFIG_CMD_CONSOLE is not set
# CONFIG_CMD_BOOTD is not set
-# CONFIG_CMD_BOOTM is not set
# CONFIG_CMD_BOOTI is not set
# CONFIG_CMD_ELF is not set
# CONFIG_CMD_FDT is not set
diff --git a/configs/xilinx_zynqmp_mini_emmc0_defconfig b/configs/xilinx_zynqmp_mini_emmc0_defconfig
index bf34832..9cccf5d 100644
--- a/configs/xilinx_zynqmp_mini_emmc0_defconfig
+++ b/configs/xilinx_zynqmp_mini_emmc0_defconfig
@@ -17,6 +17,7 @@
CONFIG_REMAKE_ELF=y
# CONFIG_MP is not set
CONFIG_FIT=y
+# CONFIG_BOOTM is not set
CONFIG_SUPPORT_RAW_INITRD=y
# CONFIG_AUTOBOOT is not set
CONFIG_SYS_CBSIZE=1024
@@ -37,7 +38,6 @@
# CONFIG_CMD_BDI is not set
# CONFIG_CMD_CONSOLE is not set
# CONFIG_CMD_BOOTD is not set
-# CONFIG_CMD_BOOTM is not set
# CONFIG_CMD_BOOTI is not set
# CONFIG_CMD_ELF is not set
# CONFIG_CMD_FDT is not set
diff --git a/configs/xilinx_zynqmp_mini_emmc1_defconfig b/configs/xilinx_zynqmp_mini_emmc1_defconfig
index af70ccf..3919e23 100644
--- a/configs/xilinx_zynqmp_mini_emmc1_defconfig
+++ b/configs/xilinx_zynqmp_mini_emmc1_defconfig
@@ -17,6 +17,7 @@
CONFIG_REMAKE_ELF=y
# CONFIG_MP is not set
CONFIG_FIT=y
+# CONFIG_BOOTM is not set
CONFIG_SUPPORT_RAW_INITRD=y
# CONFIG_AUTOBOOT is not set
CONFIG_SYS_CBSIZE=1024
@@ -37,7 +38,6 @@
# CONFIG_CMD_BDI is not set
# CONFIG_CMD_CONSOLE is not set
# CONFIG_CMD_BOOTD is not set
-# CONFIG_CMD_BOOTM is not set
# CONFIG_CMD_BOOTI is not set
# CONFIG_CMD_ELF is not set
# CONFIG_CMD_FDT is not set
diff --git a/configs/xilinx_zynqmp_mini_nand_defconfig b/configs/xilinx_zynqmp_mini_nand_defconfig
index d2e920f..ae0c3ae 100644
--- a/configs/xilinx_zynqmp_mini_nand_defconfig
+++ b/configs/xilinx_zynqmp_mini_nand_defconfig
@@ -13,6 +13,7 @@
CONFIG_REMAKE_ELF=y
# CONFIG_MP is not set
CONFIG_FIT=y
+# CONFIG_BOOTM is not set
CONFIG_SUPPORT_RAW_INITRD=y
# CONFIG_AUTOBOOT is not set
CONFIG_SYS_CBSIZE=1024
@@ -27,7 +28,6 @@
# CONFIG_CMD_BDI is not set
# CONFIG_CMD_CONSOLE is not set
# CONFIG_CMD_BOOTD is not set
-# CONFIG_CMD_BOOTM is not set
# CONFIG_CMD_BOOTI is not set
# CONFIG_CMD_GO is not set
# CONFIG_CMD_RUN is not set
diff --git a/configs/xilinx_zynqmp_mini_nand_single_defconfig b/configs/xilinx_zynqmp_mini_nand_single_defconfig
index 31f6473..15d471c 100644
--- a/configs/xilinx_zynqmp_mini_nand_single_defconfig
+++ b/configs/xilinx_zynqmp_mini_nand_single_defconfig
@@ -13,6 +13,7 @@
CONFIG_REMAKE_ELF=y
# CONFIG_MP is not set
CONFIG_FIT=y
+# CONFIG_BOOTM is not set
CONFIG_SUPPORT_RAW_INITRD=y
# CONFIG_AUTOBOOT is not set
CONFIG_SYS_CBSIZE=1024
@@ -27,7 +28,6 @@
# CONFIG_CMD_BDI is not set
# CONFIG_CMD_CONSOLE is not set
# CONFIG_CMD_BOOTD is not set
-# CONFIG_CMD_BOOTM is not set
# CONFIG_CMD_BOOTI is not set
# CONFIG_CMD_GO is not set
# CONFIG_CMD_RUN is not set
diff --git a/configs/xilinx_zynqmp_mini_qspi_defconfig b/configs/xilinx_zynqmp_mini_qspi_defconfig
index 096feeb..071784c 100644
--- a/configs/xilinx_zynqmp_mini_qspi_defconfig
+++ b/configs/xilinx_zynqmp_mini_qspi_defconfig
@@ -19,6 +19,7 @@
CONFIG_SYS_LOAD_ADDR=0x8000000
# CONFIG_EXPERT is not set
CONFIG_REMAKE_ELF=y
+# CONFIG_BOOTM is not set
# CONFIG_LEGACY_IMAGE_FORMAT is not set
# CONFIG_AUTOBOOT is not set
# CONFIG_ARCH_FIXUP_FDT_MEMORY is not set
@@ -41,7 +42,6 @@
# CONFIG_CMD_BDI is not set
# CONFIG_CMD_CONSOLE is not set
# CONFIG_CMD_BOOTD is not set
-# CONFIG_CMD_BOOTM is not set
# CONFIG_CMD_BOOTI is not set
# CONFIG_CMD_ELF is not set
# CONFIG_CMD_FDT is not set
diff --git a/configs/zynq_cse_nand_defconfig b/configs/zynq_cse_nand_defconfig
index 0dbc804..982777b 100644
--- a/configs/zynq_cse_nand_defconfig
+++ b/configs/zynq_cse_nand_defconfig
@@ -19,6 +19,7 @@
CONFIG_REMAKE_ELF=y
CONFIG_SYS_CUSTOM_LDSCRIPT=y
CONFIG_SYS_LDSCRIPT="arch/arm/mach-zynq/u-boot.lds"
+# CONFIG_BOOTM is not set
# CONFIG_AUTOBOOT is not set
CONFIG_USE_PREBOOT=y
CONFIG_SYS_CBSIZE=1024
@@ -43,7 +44,6 @@
# CONFIG_CMD_BDI is not set
# CONFIG_CMD_CONSOLE is not set
# CONFIG_CMD_BOOTD is not set
-# CONFIG_CMD_BOOTM is not set
# CONFIG_CMD_ELF is not set
# CONFIG_CMD_FDT is not set
# CONFIG_CMD_GO is not set
diff --git a/configs/zynq_cse_nor_defconfig b/configs/zynq_cse_nor_defconfig
index d95f760..7d70dae 100644
--- a/configs/zynq_cse_nor_defconfig
+++ b/configs/zynq_cse_nor_defconfig
@@ -19,6 +19,7 @@
CONFIG_REMAKE_ELF=y
CONFIG_SYS_CUSTOM_LDSCRIPT=y
CONFIG_SYS_LDSCRIPT="arch/arm/mach-zynq/u-boot.lds"
+# CONFIG_BOOTM is not set
# CONFIG_AUTOBOOT is not set
CONFIG_USE_PREBOOT=y
CONFIG_SYS_CBSIZE=1024
@@ -43,7 +44,6 @@
# CONFIG_CMD_BDI is not set
# CONFIG_CMD_CONSOLE is not set
# CONFIG_CMD_BOOTD is not set
-# CONFIG_CMD_BOOTM is not set
# CONFIG_CMD_ELF is not set
# CONFIG_CMD_FDT is not set
# CONFIG_CMD_GO is not set
diff --git a/configs/zynq_cse_qspi_defconfig b/configs/zynq_cse_qspi_defconfig
index dd7f978..c7477aa 100644
--- a/configs/zynq_cse_qspi_defconfig
+++ b/configs/zynq_cse_qspi_defconfig
@@ -25,6 +25,7 @@
CONFIG_REMAKE_ELF=y
CONFIG_SYS_CUSTOM_LDSCRIPT=y
CONFIG_SYS_LDSCRIPT="arch/arm/mach-zynq/u-boot.lds"
+# CONFIG_BOOTM is not set
# CONFIG_AUTOBOOT is not set
# CONFIG_ARCH_FIXUP_FDT_MEMORY is not set
CONFIG_USE_PREBOOT=y
@@ -52,7 +53,6 @@
# CONFIG_CMD_BDI is not set
# CONFIG_CMD_CONSOLE is not set
# CONFIG_CMD_BOOTD is not set
-# CONFIG_CMD_BOOTM is not set
# CONFIG_CMD_ELF is not set
# CONFIG_CMD_FDT is not set
# CONFIG_CMD_GO is not set
diff --git a/doc/android/fastboot.rst b/doc/android/fastboot.rst
index 05d8f77..9e337ca 100644
--- a/doc/android/fastboot.rst
+++ b/doc/android/fastboot.rst
@@ -128,6 +128,7 @@
When executing the fastboot ``boot`` command, if ``fastboot_bootcmd`` is set
then that will be executed in place of ``bootm <CONFIG_FASTBOOT_BUF_ADDR>``.
+This is supported if CONFIG_CMDLINE is enabled, which it normally is.
Partition Names
---------------
diff --git a/doc/board/amlogic/jethub-j100.rst b/doc/board/amlogic/jethub-j100.rst
index 86acdaf..cbf1ea7 100644
--- a/doc/board/amlogic/jethub-j100.rst
+++ b/doc/board/amlogic/jethub-j100.rst
@@ -1,9 +1,9 @@
.. SPDX-License-Identifier: GPL-2.0+
-U-Boot for JetHub J100 (A113X)
-==============================
+U-Boot for JetHub J100/J110 (A113X)
+===================================
-JetHome Jethub D1 (http://jethome.ru/jethub-d1) is a home automation controller device
+JetHome Jethub D1/D1+ (http://jethome.ru/jethub-d1p) is a home automation controller device
manufactured by JetHome with the following specifications:
- Amlogic A113X (ARM Cortex-A53) quad-core up to 1.5GHz
@@ -23,7 +23,10 @@
The basic version also has:
- - TI CC2538 + CC2592 Zigbee Wireless with upto 20dBm output power and Zigbee 3.0
+ - Zigbee module one from:
+ - TI CC2538 + CC2592 Zigbee 3.0 Wireless
+ - TI CC2652P1 Zigbee 3.0 Wireless
+ - Silicon Labs EFT32MG21 Zigbee 3.0/Thread Wireless
- 1 x 1-Wire
- 2 x RS-485
- 4 x dry contact digital GPIO inputs
diff --git a/doc/board/anbernic/rgxx3.rst b/doc/board/anbernic/rgxx3.rst
index d159ed2..1e63e69 100644
--- a/doc/board/anbernic/rgxx3.rst
+++ b/doc/board/anbernic/rgxx3.rst
@@ -17,6 +17,7 @@
Additionally, the following very similar non-Anbernic devices are also
supported:
+ - Powkiddy RGB10MAX3
- Powkiddy RGB30
- Powkiddy RK2023
diff --git a/doc/board/emulation/qemu-x86.rst b/doc/board/emulation/qemu-x86.rst
index c604e42..4eeba46 100644
--- a/doc/board/emulation/qemu-x86.rst
+++ b/doc/board/emulation/qemu-x86.rst
@@ -134,7 +134,7 @@
U-Boot SPL 2023.07 (Jul 23 2023 - 08:00:12 -0600)
Trying to boot from SPI
- Jumping to 64-bit U-Boot: Note many features are missing
+ Jumping to 64-bit U-Boot
U-Boot 2023.07 (Jul 23 2023 - 08:00:12 -0600)
diff --git a/doc/board/index.rst b/doc/board/index.rst
index 62357c9..f0a11f8 100644
--- a/doc/board/index.rst
+++ b/doc/board/index.rst
@@ -53,6 +53,7 @@
ste/index
tbs/index
thead/index
+ theobroma-systems/index
ti/index
toradex/index
variscite/index
diff --git a/doc/board/phytec/phycore-am62x.rst b/doc/board/phytec/phycore-am62x.rst
index 1d641a7..bc6d524 100644
--- a/doc/board/phytec/phycore-am62x.rst
+++ b/doc/board/phytec/phycore-am62x.rst
@@ -92,9 +92,9 @@
To boot from a micro SD card on a HSFS device simply copy the following
artifacts to the FAT partition:
-* tiboot3.bin from R5 build as tiboot3.bin
-* tispl.bin_unsigned from Cortex-A build as tispl.bin
-* u-boot.img_unsigned from Cortex-A build as u-boot.img
+* tiboot3.bin from R5 build
+* tispl.bin from Cortex-A build
+* u-boot.img from Cortex-A build
Boot
----
diff --git a/doc/board/rockchip/rockchip.rst b/doc/board/rockchip/rockchip.rst
index e23ca42..5dd5ea7 100644
--- a/doc/board/rockchip/rockchip.rst
+++ b/doc/board/rockchip/rockchip.rst
@@ -60,9 +60,14 @@
- ODROID-GO Advance (odroid-go2)
* rk3328
- Rockchip Evb-RK3328 (evb-rk3328)
+ - Firefly ROC-RK3328-CC (roc-cc-rk3328)
+ - FriendlyElec NanoPi R2C (nanopi-r2c-rk3328)
+ - FriendlyElec NanoPi R2C Plus (nanopi-r2c-plus-rk3328)
+ - FriendlyElec NanoPi R2S (nanopi-r2s-rk3328)
- Pine64 Rock64 (rock64-rk3328)
- - Firefly-RK3328 (roc-cc-rk3328)
- - Radxa Rockpi E (rock-pi-e-rk3328)
+ - Radxa ROCK Pi E (rock-pi-e-rk3328)
+ - Xunlong Orange Pi R1 Plus (orangepi-r1-plus-rk3328)
+ - Xunlong Orange Pi R1 Plus LTS (orangepi-r1-plus-lts-rk3328)
* rk3368
- GeekBox (geekbox)
- PX5 EVB (evb-px5)
@@ -93,6 +98,7 @@
* rk3566
- Anbernic RGxx3 (anbernic-rgxx3-rk3566)
+ - Pine64 PineTab2 (pinetab2-rk3566)
- Pine64 Quartz64-A Board (quartz64-a-rk3566)
- Pine64 Quartz64-B Board (quartz64-b-rk3566)
- Pine64 SOQuartz on Blade (soquartz-blade-rk3566)
@@ -116,10 +122,13 @@
- Edgeble Neural Compute Module 6A SoM - Neu6a (neu6a-io-rk3588)
- Edgeble Neural Compute Module 6B SoM - Neu6b (neu6b-io-rk3588)
- FriendlyElec NanoPC-T6 (nanopc-t6-rk3588)
+ - Generic RK3588S/RK3588 (generic-rk3588)
- Pine64 QuartzPro64 (quartzpro64-rk3588)
- - Turing Machines RK1 (turing-rk1-rk3588)
- Radxa ROCK 5A (rock5a-rk3588s)
- Radxa ROCK 5B (rock5b-rk3588)
+ - Rockchip Toybrick TB-RK3588X (toybrick-rk3588)
+ - Theobroma Systems RK3588-SBC Jaguar (jaguar-rk3588)
+ - Turing Machines RK1 (turing-rk1-rk3588)
- Xunlong Orange Pi 5 (orangepi-5-rk3588s)
- Xunlong Orange Pi 5 Plus (orangepi-5-plus-rk3588)
diff --git a/doc/board/starfive/index.rst b/doc/board/starfive/index.rst
index 0c52dc7..2762bf7 100644
--- a/doc/board/starfive/index.rst
+++ b/doc/board/starfive/index.rst
@@ -6,4 +6,5 @@
.. toctree::
:maxdepth: 1
+ milk-v_mars.rst
visionfive2
diff --git a/doc/board/starfive/milk-v_mars.rst b/doc/board/starfive/milk-v_mars.rst
new file mode 100644
index 0000000..554932e
--- /dev/null
+++ b/doc/board/starfive/milk-v_mars.rst
@@ -0,0 +1,111 @@
+.. SPDX-License-Identifier: GPL-2.0+
+
+Milk-V Mars
+===========
+
+U-Boot for the Milk-V Mars uses the same U-Boot binaries as the VisionFive 2
+board. In U-Boot SPL the actual board is detected and the device-tree patched
+accordingly.
+
+Building
+~~~~~~~~
+
+1. Add the RISC-V toolchain to your PATH.
+2. Setup ARCH & cross compilation environment variable:
+
+.. code-block:: none
+
+ export CROSS_COMPILE=<riscv64 toolchain prefix>
+
+The M-mode software OpenSBI provides the supervisor binary interface (SBI) and
+is responsible for the switch to S-Mode. It is a prerequisite to build U-Boot.
+Support for the JH7110 was introduced in OpenSBI 1.2. It is recommended to use
+a current release.
+
+.. code-block:: console
+
+ git clone https://github.com/riscv/opensbi.git
+ cd opensbi
+ make PLATFORM=generic FW_TEXT_START=0x40000000 FW_OPTIONS=0
+
+Now build the U-Boot SPL and U-Boot proper.
+
+.. code-block:: console
+
+ cd <U-Boot-dir>
+ make starfive_visionfive2_defconfig
+ make OPENSBI=$(opensbi_dir)/build/platform/generic/firmware/fw_dynamic.bin
+
+This will generate the U-Boot SPL image (spl/u-boot-spl.bin.normal.out) as well
+as the FIT image (u-boot.itb) with OpenSBI and U-Boot.
+
+Device-tree selection
+~~~~~~~~~~~~~~~~~~~~~
+
+Depending on the board version U-Boot set variable $fdtfile to either
+starfive/jh7110-starfive-visionfive-2-v1.2a.dtb or
+starfive/jh7110-starfive-visionfive-2-v1.3b.dtb.
+
+To overrule this selection the variable can be set manually and saved in the
+environment
+
+::
+
+ setenv fdtfile my_device-tree.dtb
+ env save
+
+or the configuration variable CONFIG_DEFAULT_FDT_FILE can be used to set to
+provide a default value.
+
+Boot source selection
+~~~~~~~~~~~~~~~~~~~~~
+
+The board provides the DIP switches MSEL[1:0] to select the boot device out of
+SPI flash, eMMC, SD-card, UART. To select booting from SD-card set the DIP
+switches MSEL[1:0] to 10.
+
+Preparing the SD-Card
+~~~~~~~~~~~~~~~~~~~~~
+
+The device firmware loads U-Boot SPL (u-boot-spl.bin.normal.out) from the
+partition with type GUID 2E54B353-1271-4842-806F-E436D6AF6985. You are free
+to choose any partition number.
+
+With the default configuration U-Boot SPL loads the U-Boot FIT image
+(u-boot.itb) from partition 2 (CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_PARTITION=0x2).
+When formatting it is recommended to use GUID
+BC13C2FF-59E6-4262-A352-B275FD6F7172 for this partition.
+
+The FIT image (u-boot.itb) is a combination of OpenSBI's fw_dynamic.bin,
+u-boot-nodtb.bin and the device tree blob.
+
+Format the SD card (make sure the disk has GPT, otherwise use gdisk to switch)
+
+.. code-block:: bash
+
+ sudo sgdisk --clear \
+ --set-alignment=2 \
+ --new=1:4096:8191 --change-name=1:spl --typecode=1:2E54B353-1271-4842-806F-E436D6AF6985\
+ --new=2:8192:16383 --change-name=2:uboot --typecode=2:BC13C2FF-59E6-4262-A352-B275FD6F7172 \
+ --new=3:16384:1654784 --change-name=3:system --typecode=3:EBD0A0A2-B9E5-4433-87C0-68B6B72699C7 \
+ /dev/sdb
+
+Copy U-Boot to the SD card
+
+.. code-block:: bash
+
+ sudo dd if=u-boot-spl.bin.normal.out of=/dev/sdb1
+ sudo dd if=u-boot.itb of=/dev/sdb2
+
+ sudo mount /dev/sdb3 /mnt/
+ sudo cp u-boot-spl.bin.normal.out /mnt/
+ sudo cp u-boot.itb /mnt/
+ sudo cp Image.gz /mnt/
+ sudo cp initramfs.cpio.gz /mnt/
+ sudo cp jh7110-starfive-visionfive-2.dtb /mnt/
+ sudo umount /mnt
+
+Booting
+~~~~~~~
+
+Once you plugin the sdcard and power up, you should see the U-Boot prompt.
diff --git a/doc/board/starfive/visionfive2.rst b/doc/board/starfive/visionfive2.rst
index abda8ac..2c68df3 100644
--- a/doc/board/starfive/visionfive2.rst
+++ b/doc/board/starfive/visionfive2.rst
@@ -71,6 +71,24 @@
This will generate the U-Boot SPL image (spl/u-boot-spl.bin.normal.out) as well
as the FIT image (u-boot.itb) with OpenSBI and U-Boot.
+Device-tree selection
+~~~~~~~~~~~~~~~~~~~~~
+
+Depending on the board version U-Boot set variable $fdtfile to either
+starfive/jh7110-starfive-visionfive-2-v1.2a.dtb or
+starfive/jh7110-starfive-visionfive-2-v1.3b.dtb.
+
+To overrule this selection the variable can be set manually and saved in the
+environment
+
+::
+
+ setenv fdtfile my_device-tree.dtb
+ env save
+
+or the configuration variable CONFIG_DEFAULT_FDT_FILE can be used to provide
+a default value.
+
Flashing
~~~~~~~~
diff --git a/doc/board/theobroma-systems/index.rst b/doc/board/theobroma-systems/index.rst
new file mode 100644
index 0000000..b4da261
--- /dev/null
+++ b/doc/board/theobroma-systems/index.rst
@@ -0,0 +1,11 @@
+.. SPDX-License-Identifier: GPL-2.0+
+
+Theobroma Systems
+=================
+
+.. toctree::
+ :maxdepth: 2
+
+ jaguar_rk3588
+ puma_rk3399
+ ringneck_px30
diff --git a/doc/board/theobroma-systems/jaguar_rk3588.rst b/doc/board/theobroma-systems/jaguar_rk3588.rst
new file mode 100644
index 0000000..db15f94
--- /dev/null
+++ b/doc/board/theobroma-systems/jaguar_rk3588.rst
@@ -0,0 +1,100 @@
+.. SPDX-License-Identifier: GPL-2.0+
+
+SBC-RK3588-AMR Jaguar
+=====================
+
+The SBC-RK3588-AMR is a Single Board Computer designed by
+Theobroma Systems for autonomous mobile robots.
+
+It provides the following features:
+
+ * up to 32GB LDDR4
+ * up to 128GB on-module eMMC (with 8-bit 1.8V interface)
+ * SD card
+ * Gigabit Ethernet
+ * 1x USB-A 2.0 host
+ * PCIe M.2 2230 Key M (Gen 2 1-lane) for WiFi+BT
+ * PCIe M.2 2280 Key M (Gen 3 4-lane) for NVMe
+ * CAN
+ * RS485 UART
+ * 2x USB Type-C 3.1 host/device
+ * HDMI output
+ * 2x camera connectors (MIPI-CSI 2-lane I2C/SPI for IMUs GPIOs)
+ * EEPROM
+ * Secure Element
+ * ATtiny companion controller implementing:
+
+ - low-power RTC functionality (ISL1208 emulation)
+ - fan controller (AMC6821 emulation)
+
+ * 80-pin Mezzanine connector
+
+Here is the step-by-step to boot to U-Boot on SBC-RK3588-AMR Jaguar from Theobroma
+Systems.
+
+Get the TF-A and DDR init (TPL) binaries
+----------------------------------------
+
+.. prompt:: bash
+
+ git clone https://github.com/rockchip-linux/rkbin
+ cd rkbin
+ export RKBIN=$(pwd)
+ export BL31=$RKBIN/bin/rk35/rk3588_bl31_v1.38.elf
+ export ROCKCHIP_TPL=$RKBIN/bin/rk35/rk3588_ddr_lp4_2112MHz_lp5_2736MHz_v1.11.bin
+ sed -i 's/^uart baudrate=.*$/uart baudrate=115200/' tools/ddrbin_param.txt
+ ./tools/ddrbin_tool tools/ddrbin_param.txt "$ROCKCHIP_TPL"
+ ./tools/boot_merger RKBOOT/RK3588MINIALL.ini
+ export RKDB=$RKBIN/rk3588_spl_loader_v1.11.112.bin
+
+This will setup all required external dependencies for compiling U-Boot. This will
+be updated in the future once upstream Trusted-Firmware-A supports RK3588 or U-Boot
+gains support for open-source DRAM initialization in TPL.
+
+Build U-Boot
+------------
+
+.. prompt:: bash
+
+ cd ../u-boot
+ make CROSS_COMPILE=aarch64-linux-gnu- jaguar-rk3588_defconfig all
+
+This will build ``u-boot-rockchip.bin`` which can be written to an MMC device
+(eMMC or SD card).
+
+Flash the image
+---------------
+
+Copy ``u-boot-rockchip.bin`` to offset 32k for SD/eMMC.
+
+SD-Card
+~~~~~~~
+
+.. prompt:: bash
+
+ dd if=u-boot-rockchip.bin of=/dev/sdX seek=64
+
+.. note::
+
+ Replace ``/dev/sdX`` to match your SD card kernel device.
+
+eMMC
+~~~~
+
+``rkdeveloptool`` allows to flash the on-board eMMC via the USB OTG interface
+with help of the Rockchip loader binary.
+
+To enter the USB flashing mode, remove any SD card, insert a USB-C cable in the
+``DOWNLOAD`` USB Type-C connector (P11) and then power cycle or reset the board
+while pressing the ``BIOS`` (SW2) button. A new USB device should have appeared
+on your PC (check with ``lsusb -d 2207:350b``).
+
+To flash U-Boot on the eMMC with ``rkdeveloptool``:
+
+.. prompt:: bash
+
+ git clone https://github.com/rockchip-linux/rkdeveloptool
+ cd rkdeveloptool
+ autoreconf -i && CPPFLAGS=-Wno-format-truncation ./configure && make
+ ./rkdeveloptool db "$RKDB"
+ ./rkdeveloptool wl 64 ../u-boot-rockchip.bin
diff --git a/doc/board/theobroma-systems/puma_rk3399.rst b/doc/board/theobroma-systems/puma_rk3399.rst
new file mode 100644
index 0000000..5bc6385
--- /dev/null
+++ b/doc/board/theobroma-systems/puma_rk3399.rst
@@ -0,0 +1,126 @@
+.. SPDX-License-Identifier: GPL-2.0+
+
+RK3399-Q7 Puma
+==============
+
+The RK3399-Q7 (Puma) is a system-on-module featuring the Rockchip
+RK3399 in a Qseven-compatible form-factor.
+
+RK3399-Q7 features:
+
+ * CPU: ARMv8 64bit Big-Little architecture,
+
+ * Big: dual-core Cortex-A72
+ * Little: quad-core Cortex-A53
+ * IRAM: 200KB
+ * DRAM: 4GB-128MB dual-channel
+
+ * eMMC: onboard eMMC
+ * SD/MMC
+ * GbE (onboard Micrel KSZ9031) Gigabit ethernet PHY
+ * USB:
+
+ * USB3.0 dual role port
+ * 2x USB3.0 host, 1x USB2.0 host via onboard USB3.0 hub
+
+ * Display: HDMI/eDP/MIPI
+ * Camera: 2x CSI (one on the edge connector, one on the Q7 specified CSI ZIF)
+ * NOR Flash: onboard SPI NOR
+ * Companion Controller: onboard additional Cortex-M0 microcontroller
+ * RTC
+ * fan controller
+ * CAN
+
+Here is the step-by-step to boot to U-Boot on RK3399-Q7 from Theobroma Systems.
+
+Get the Source and build ATF binary
+-----------------------------------
+
+.. prompt:: bash
+
+ git clone https://git.trustedfirmware.org/TF-A/trusted-firmware-a.git
+ cd trusted-firmware-a
+ make CROSS_COMPILE=aarch64-linux-gnu- PLAT=rk3399 bl31
+ export BL31=$PWD/build/rk3399/release/bl31/bl31.elf
+
+Compile the U-Boot
+------------------
+
+.. prompt:: bash
+
+ cd ../u-boot
+ make CROSS_COMPILE=aarch64-linux-gnu- puma-rk3399_defconfig all
+
+This will build ``u-boot-rockchip.bin`` which can be written to an MMC device
+(eMMC or SD card), and ``u-boot-rockchip-spi.bin`` which can be written to the
+SPI-NOR flash.
+
+Flash the image
+---------------
+
+Copy ``u-boot-rockchip.bin`` to offset 32k for SD/eMMC.
+Copy ``u-boot-rockchip-spi.bin`` to offset 0 for NOR-flash.
+
+SD-Card
+~~~~~~~
+
+.. prompt:: bash
+
+ dd if=u-boot-rockchip.bin of=/dev/sdX seek=64
+
+.. note::
+
+ Replace ``/dev/sdX`` to match your SD card kernel device.
+
+eMMC
+~~~~
+
+``rkdeveloptool`` allows to flash the on-board eMMC via the USB OTG interface
+with help of the Rockchip loader binary.
+
+To enter the USB flashing mode on Haikou baseboard, remove any SD card, insert a
+micro-USB cable in the ``Q7 USB P1`` connector (P8), move ``SW5`` switch into
+``BIOS Disable`` mode, power cycle or reset the board and move ``SW5`` switch
+back to ``Normal Boot`` mode. A new USB device should have appeared on your PC
+(check with ``lsusb -d 2207:330c``).
+
+To flash U-Boot on the eMMC with ``rkdeveloptool``:
+
+.. prompt:: bash
+
+ git clone https://github.com/rockchip-linux/rkdeveloptool
+ cd rkdeveloptool
+ autoreconf -i && CPPFLAGS=-Wno-format-truncation ./configure && make
+ git clone https://github.com/rockchip-linux/rkbin.git
+ cd rkbin
+ ./tools/boot_merger RKBOOT/RK3399MINIALL.ini
+ cd ..
+ ./rkdeveloptool db rkbin/rk3399_loader_v1.30.130.bin
+ ./rkdeveloptool wl 64 ../u-boot-rockchip.bin
+
+NOR-Flash
+~~~~~~~~~
+
+``rkdeveloptool`` allows to flash the on-board SPI via the USB OTG interface with
+help of the Rockchip loader binary.
+
+To enter the USB flashing mode on Haikou baseboard, remove any SD card, insert a
+micro-USB cable in the ``Q7 USB P1`` connector (P8), move ``SW5`` switch into
+``BIOS Disable`` mode, power cycle or reset the board and move ``SW5`` switch
+back to ``Normal Boot`` mode. A new USB device should have appeared on your PC
+(check with ``lsusb -d 2207:330c``).
+
+To flash U-Boot on the SPI with ``rkdeveloptool``:
+
+.. prompt:: bash
+
+ git clone https://github.com/rockchip-linux/rkdeveloptool
+ cd rkdeveloptool
+ autoreconf -i && CPPFLAGS=-Wno-format-truncation ./configure && make
+ git clone https://github.com/rockchip-linux/rkbin.git
+ cd rkbin
+ ./tools/boot_merger RKBOOT/RK3399MINIALL_SPINOR.ini
+ cd ..
+ ./rkdeveloptool db rkbin/rk3399_loader_spinor_v1.30.114.bin
+ ./rkdeveloptool ef
+ ./rkdeveloptool wl 0 ../u-boot-rockchip-spi.bin
diff --git a/doc/board/theobroma-systems/ringneck_px30.rst b/doc/board/theobroma-systems/ringneck_px30.rst
new file mode 100644
index 0000000..c16b9ed
--- /dev/null
+++ b/doc/board/theobroma-systems/ringneck_px30.rst
@@ -0,0 +1,95 @@
+.. SPDX-License-Identifier: GPL-2.0+
+
+PX30-uQ7 Ringneck
+=================
+
+The PX30-uQ7 (Ringneck) SoM is a µQseven-compatible (40mmx70mm, MXM-230
+connector) system-on-module from Theobroma Systems, featuring the Rockchip PX30.
+
+It provides the following feature set:
+
+ * up to 4GB DDR4
+ * up to 128GB on-module eMMC (with 8-bit 1.8V interface)
+ * SD card (on a baseboard) via edge connector
+ * Fast Ethernet with on-module TI DP83825I PHY
+ * MIPI-DSI/LVDS
+ * MIPI-CSI
+ * USB
+
+ - 1x USB 2.0 dual-role
+ - 3x USB 2.0 host
+
+ * on-module companion controller (STM32 Cortex-M0 or ATtiny), implementing:
+
+ - low-power RTC functionality (ISL1208 emulation)
+ - fan controller (AMC6821 emulation)
+ - USB<->CAN bridge controller (STM32 only)
+
+ * on-module Espressif ESP32 for Bluetooth + 2.4GHz WiFi
+ * on-module NXP SE05x Secure Element
+
+Here is the step-by-step to boot to U-Boot on PX30-uQ7 Ringneck from Theobroma
+Systems.
+
+Get the Source and build ATF binary
+-----------------------------------
+
+.. prompt:: bash
+
+ git clone https://git.trustedfirmware.org/TF-A/trusted-firmware-a.git
+ cd trusted-firmware-a
+ make CROSS_COMPILE=aarch64-linux-gnu- PLAT=px30 bl31
+ export BL31=$PWD/build/px30/release/bl31/bl31.elf
+
+Compile the U-Boot
+------------------
+
+.. prompt:: bash
+
+ cd ../u-boot
+ make CROSS_COMPILE=aarch64-linux-gnu- ringneck-px30_defconfig all
+
+This will build ``u-boot-rockchip.bin`` which can be written to an MMC device
+(eMMC or SD card).
+
+Flash the image
+---------------
+
+Copy ``u-boot-rockchip.bin`` to offset 32k for SD/eMMC.
+
+SD-Card
+~~~~~~~
+
+.. prompt:: bash
+
+ dd if=u-boot-rockchip.bin of=/dev/sdX seek=64
+
+.. note::
+
+ Replace ``/dev/sdX`` to match your SD card kernel device.
+
+eMMC
+~~~~
+
+``rkdeveloptool`` allows to flash the on-board eMMC via the USB OTG interface
+with help of the Rockchip loader binary.
+
+To enter the USB flashing mode on Haikou baseboard, remove any SD card, insert a
+micro-USB cable in the ``Q7 USB P1`` connector (P8), move ``SW5`` switch into
+``BIOS Disable`` mode, power cycle or reset the board and move ``SW5`` switch
+back to ``Normal Boot`` mode. A new USB device should have appeared on your PC
+(check with ``lsusb -d 2207:330d``).
+
+To flash U-Boot on the eMMC with ``rkdeveloptool``:
+
+.. prompt:: bash
+
+ git clone https://github.com/rockchip-linux/rkdeveloptool
+ cd rkdeveloptool
+ autoreconf -i && CPPFLAGS=-Wno-format-truncation ./configure && make
+ git clone https://github.com/rockchip-linux/rkbin.git
+ cd rkbin
+ ./tools/boot_merger RKBOOT/PX30MINIALL.ini
+ cd ..
+ ./rkdeveloptool db rkbin/px30_loader_v2.08.135.bin
+ ./rkdeveloptool wl 64 ../u-boot-rockchip.bin
diff --git a/doc/board/toradex/apalis-imx8.rst b/doc/board/toradex/apalis-imx8.rst
index ffc4c7d..069d86c 100644
--- a/doc/board/toradex/apalis-imx8.rst
+++ b/doc/board/toradex/apalis-imx8.rst
@@ -20,36 +20,36 @@
Get and Build the ARM Trusted Firmware
--------------------------------------
+Download the imx-atf repository:
+
+.. code-block:: bash
+
+ $ git clone -b lf_v2.6 https://github.com/nxp-imx/imx-atf.git
+
+Compile it with an aarch64 toolchain:
+
.. code-block:: bash
- $ git clone -b imx_4.14.78_1.0.0_ga https://github.com/nxp-imx/imx-atf
$ cd imx-atf/
$ make PLAT=imx8qm bl31
Get scfw_tcm.bin and ahab-container.img
---------------------------------------
-.. code-block:: bash
-
- $ wget https://github.com/toradex/meta-fsl-bsp-release/blob/toradex-sumo-4.14.78-1.0.0_ga-bringup/imx/meta-bsp/recipes-
- bsp/imx-sc-firmware/files/mx8qm-apalis-scfw-tcm.bin?raw=true
- $ mv mx8qm-apalis-scfw-tcm.bin\?raw\=true mx8qm-apalis-scfw-tcm.bin
- $ wget https://www.nxp.com/lgfiles/NMG/MAD/YOCTO/firmware-imx-8.0.bin
- $ chmod +x firmware-imx-8.0.bin
- $ ./firmware-imx-8.0.bin
-
-Copy the following binaries to the U-Boot folder:
+Download imx-seco firmware and extract it:
.. code-block:: bash
- $ cp imx-atf/build/imx8qm/release/bl31.bin .
- $ cp u-boot/u-boot.bin .
+ $ wget https://www.nxp.com/lgfiles/NMG/MAD/YOCTO/imx-seco-5.8.7.bin
+ $ sh imx-seco-5.8.7.bin --auto-accept
-Copy the following firmware to the U-Boot folder:
+Copy the following binaries to the U-Boot folder:
.. code-block:: bash
- $ cp firmware-imx-8.0/firmware/seco/ahab-container.img .
+ $ wget https://github.com/toradex/i.MX-System-Controller-Firmware/raw/master/src/scfw_export_mx8qm_b0/build_mx8qm_b0/mx8qm-apalis-scfw-tcm.bin
+ $ cp ../imx-atf/build/imx8qm/release/bl31.bin .
+ $ cp ../imx-seco-5.8.7/firmware/seco/mx8qmb0-ahab-container.img mx8qm-ahab-container.img
Build U-Boot
------------
@@ -64,7 +64,7 @@
Get the latest version of the universal update utility (uuu) aka ``mfgtools 3.0``:
-https://community.nxp.com/external-link.jspa?url=https%3A%2F%2Fgithub.com%2FNXPmicro%2Fmfgtools%2Freleases
+https://github.com/nxp-imx/mfgtools/releases
Put the module into USB recovery aka serial downloader mode, connect the USB
device to your host and execute ``uuu``:
diff --git a/doc/board/toradex/colibri-imx8x.rst b/doc/board/toradex/colibri-imx8x.rst
index 9e61d98..378b259 100644
--- a/doc/board/toradex/colibri-imx8x.rst
+++ b/doc/board/toradex/colibri-imx8x.rst
@@ -20,26 +20,35 @@
Get and Build the ARM Trusted Firmware
--------------------------------------
+Download the imx-atf repository:
+
+.. code-block:: bash
+
+ $ git clone -b lf_v2.6 https://github.com/nxp-imx/imx-atf.git
+
+Compile it with an aarch64 toolchain:
+
.. code-block:: bash
- $ git clone -b toradex_imx_5.4.70_2.3.0 http://git.toradex.com/cgit/imx-atf.git/
$ make PLAT=imx8qx bl31 -C imx-atf
Get scfw_tcm.bin and ahab-container.img
---------------------------------------
+Download imx-seco firmware and extract it:
+
.. code-block:: bash
- $ wget https://github.com/toradex/i.MX-System-Controller-Firmware/raw/master/src/scfw_export_mx8qx_b0/build_mx8qx_b0/mx8qx-colibri-scfw-tcm.bin
- $ wget https://www.nxp.com/lgfiles/NMG/MAD/YOCTO/imx-seco-3.8.1.bin
- $ sh imx-seco-3.8.1.bin --auto-accept
+ $ wget https://www.nxp.com/lgfiles/NMG/MAD/YOCTO/imx-seco-5.8.7.bin
+ $ sh imx-seco-5.8.7.bin --auto-accept
Copy the following firmware to the U-Boot folder:
.. code-block:: bash
- $ cp imx-atf/build/imx8qx/release/bl31.bin .
- $ cp imx-seco-3.8.1/firmware/seco/mx8qxc0-ahab-container.img mx8qx-ahab-container.img
+ $ wget https://github.com/toradex/i.MX-System-Controller-Firmware/raw/master/src/scfw_export_mx8qx_b0/build_mx8qx_b0/mx8qx-colibri-scfw-tcm.bin
+ $ cp ../imx-atf/build/imx8qx/release/bl31.bin .
+ $ cp ../imx-seco-5.8.7/firmware/seco/mx8qxc0-ahab-container.img mx8qx-ahab-container.img
Build U-Boot
------------
@@ -54,7 +63,7 @@
Get the latest version of the universal update utility (uuu) aka ``mfgtools 3.0``:
-https://community.nxp.com/external-link.jspa?url=https%3A%2F%2Fgithub.com%2FNXPmicro%2Fmfgtools%2Freleases
+https://github.com/nxp-imx/mfgtools/releases
Put the module into USB recovery aka serial downloader mode, connect the USB
device to your host and execute ``uuu``:
diff --git a/doc/develop/commands.rst b/doc/develop/commands.rst
index ede880d..5ad4e59 100644
--- a/doc/develop/commands.rst
+++ b/doc/develop/commands.rst
@@ -88,7 +88,7 @@
.. code-block:: c
- int (*cmd)(struct cmd_tbl *cmdtp, int flag, int argc, const char *argv[]);
+ int (*cmd)(struct cmd_tbl *cmdtp, int flag, int argc, char *const argv[]);
cmdtp
Table entry describing the command (see above).
diff --git a/doc/develop/devicetree/control.rst b/doc/develop/devicetree/control.rst
index c94d841..4cc1457 100644
--- a/doc/develop/devicetree/control.rst
+++ b/doc/develop/devicetree/control.rst
@@ -36,10 +36,10 @@
-------------------------------
An fdt can be specified in source format as a text file. To read about
-the fdt syntax, take a look at the specification (dtspec_).
+the fdt syntax, take a look at `the devicetree specification`_.
-There is also a mailing list (dtlist_) for the compiler and associated
-tools.
+There is also a `devicetree compiler mailing list`_ for the compiler and
+associated tools.
In case you are wondering, OF stands for Open Firmware. This follows the
convention used in Linux.
@@ -89,7 +89,7 @@
Resyncing with devicetree-rebasing
----------------------------------
-The devicetee-rebasing repository (dtrepo_) maintains a fork cum mirror copy of
+The `devicetree-rebasing repository`_ maintains a fork cum mirror copy of
devicetree files along with the bindings synced at every Linux kernel major
release or intermediate release candidates. The U-Boot maintainers regularly
sync the `dts/upstream/` subtree from the devicetree-rebasing repo whenever
@@ -118,7 +118,7 @@
set` and set `DEFAULT_DEVICE_TREE=<name>` when prompted by Kconfig.
This should include your CPU or SoC's devicetree file. On top of that any U-Boot
-specific tweaks (see: dttweaks_) can be made for your board.
+specific tweaks (see: :ref:`dttweaks`) can be made for your board.
If `OF_EMBED` is selected by Kconfig, then it will be picked up and built into
the U-Boot image (including u-boot.bin). This is suitable for debugging
@@ -243,7 +243,7 @@
The DT schema project must be installed in order to validate the DT schema
binding documents and validate DTS files using the DT schema. For installation
-instructions, refer to the DT schema project page (dtschema_).
+instructions, refer to the `DT schema project page`_.
Several executables (dt-doc-validate, dt-mk-schema, dt-validate) will be
installed. Ensure they are in your PATH (~/.local/bin by default).
@@ -333,10 +333,10 @@
and there are still some differences in the bindings for certain boards.
While there has been discussion of having a separate repository for devicetree
files, in practice the Linux kernel Git repository has become the place where
-these are stored, with U-Boot taking copies via devicetree-rebasing repo
-(see: dtrepo_) and adding tweaks with u-boot.dtsi files.
+these are stored, with U-Boot taking copies via
+`devicetree-rebasing repository`_ and adding tweaks with u-boot.dtsi files.
-.. _dtspec: https://www.devicetree.org/specifications/
-.. _dtlist: https://www.spinics.net/lists/devicetree-compiler/
-.. _dtrepo: https://git.kernel.org/pub/scm/linux/kernel/git/devicetree/devicetree-rebasing.git
-.. _dtschema: https://github.com/devicetree-org/dt-schema/tree/main
+.. _the devicetree specification: https://www.devicetree.org/specifications/
+.. _devicetree compiler mailing list: https://www.spinics.net/lists/devicetree-compiler/
+.. _devicetree-rebasing repository: https://git.kernel.org/pub/scm/linux/kernel/git/devicetree/devicetree-rebasing.git
+.. _DT schema project page: https://github.com/devicetree-org/dt-schema/tree/main
diff --git a/doc/develop/release_cycle.rst b/doc/develop/release_cycle.rst
index db936a8..8d4c112 100644
--- a/doc/develop/release_cycle.rst
+++ b/doc/develop/release_cycle.rst
@@ -48,13 +48,14 @@
Current Status
--------------
-* U-Boot v2024.01 was released on Mon 08 January 2024.
+* U-Boot v2024.04 was released on Tue 02 April 2024.
-* The Merge Window for the next release (v2024.04) is **closed**.
+* The Merge Window for the next release (v2024.07) is **open** until the -rc1
+ release on Mon 22 April 2024.
* The next branch is now **closed**.
-* Release "v2024.04" is scheduled for 02 April 2024.
+* Release "v2024.07" is scheduled for 01 July 2024.
Future Releases
---------------
@@ -62,29 +63,29 @@
.. The following commented out dates are for when release candidates are
planned to be tagged.
-For the next scheduled release, release candidates were made on::
+.. For the next scheduled release, release candidates were made on::
-* U-Boot v2024.01-rc1 was released on Mon 29 January 2024.
+.. * U-Boot v2024.07-rc1 was released on Mon 22 April 2024.
-* U-Boot v2024.01-rc2 was released on Tue 13 February 2024.
+.. * U-Boot v2024.07-rc2 was released on Tue 06 May 2024.
-* U-Boot v2024.01-rc3 was released on Mon 26 February 2024.
+.. * U-Boot v2024.07-rc3 was released on Mon 20 May 2024.
-* U-Boot v2024.01-rc4 was released on Mon 11 March 2024.
+.. * U-Boot v2024.07-rc4 was released on Mon 03 June 2024.
-.. * U-Boot v2024.01-rc5 was released on Mon 25 March 2024.
+.. * U-Boot v2024.07-rc5 was released on Mon 17 June 2024.
Please note that the following dates are planned only and may be deviated from
as needed.
-* "v2024.04": end of MW = Mon, Jan 29, 2024; release = Tue, Apr 02, 2024
-
* "v2024.07": end of MW = Mon, Apr 22, 2024; release = Mon, Jul 01, 2024
* "v2024.10": end of MW = Mon, Jul 22, 2024; release = Mon, Oct 07, 2024
* "v2025.01": end of MW = Mon, Oct 21, 2024; release = Mon, Jan 06, 2025
+* "v2025.04": end of MW = Mon, Jan 27, 2025; release = Mon, Apr 07, 2025
+
Previous Releases
-----------------
@@ -92,6 +93,8 @@
<https://source.denx.de/u-boot/gitdm>`_, which was originally created by
Jonathan Corbet.
+* :doc:`statistics/u-boot-stats-v2024.04` which was released on 02 April 2024.
+
* :doc:`statistics/u-boot-stats-v2024.01` which was released on 08 January 2024.
* :doc:`statistics/u-boot-stats-v2023.10` which was released on 02 October 2023.
diff --git a/doc/develop/statistics/u-boot-stats-v2024.04.rst b/doc/develop/statistics/u-boot-stats-v2024.04.rst
new file mode 100644
index 0000000..b97b833
--- /dev/null
+++ b/doc/develop/statistics/u-boot-stats-v2024.04.rst
@@ -0,0 +1,877 @@
+:orphan:
+
+Release Statistics for U-Boot v2024.04
+======================================
+
+* Processed 1402 changesets from 200 developers
+
+* 28 employers found
+
+* A total of 124614 lines added, 48092 removed (delta 76522)
+
+.. table:: Developers with the most changesets
+ :widths: auto
+
+ ==================================== =====
+ Name Count
+ ==================================== =====
+ Simon Glass 143 (10.2%)
+ Heinrich Schuchardt 103 (7.3%)
+ Tom Rini 89 (6.3%)
+ Marek Vasut 69 (4.9%)
+ Sean Anderson 53 (3.8%)
+ Nishanth Menon 43 (3.1%)
+ Fabio Estevam 36 (2.6%)
+ Michal Simek 35 (2.5%)
+ Caleb Connolly 31 (2.2%)
+ Svyatoslav Ryhel 28 (2.0%)
+ Igor Prusov 25 (1.8%)
+ Francis Laniel 24 (1.7%)
+ Jonas Karlman 22 (1.6%)
+ Andrew Davis 22 (1.6%)
+ Masahisa Kojima 21 (1.5%)
+ Sam Protsenko 20 (1.4%)
+ AKASHI Takahiro 20 (1.4%)
+ Igor Opaniuk 16 (1.1%)
+ Mathieu Othacehe 16 (1.1%)
+ Patrice Chotard 15 (1.1%)
+ Roger Quadros 14 (1.0%)
+ Manorit Chawdhry 14 (1.0%)
+ Patrick Delaunay 14 (1.0%)
+ Enrico Leto 13 (0.9%)
+ Quentin Schulz 13 (0.9%)
+ Love Kumar 13 (0.9%)
+ Rasmus Villemoes 13 (0.9%)
+ Dario Binacchi 12 (0.9%)
+ Neha Malcom Francis 11 (0.8%)
+ Benjamin Hahn 10 (0.7%)
+ Devarsh Thakkar 10 (0.7%)
+ Bin Meng 10 (0.7%)
+ Paul Barker 9 (0.6%)
+ Venkatesh Yadav Abbarapu 9 (0.6%)
+ Yannic Moog 9 (0.6%)
+ Takahiro Kuwano 9 (0.6%)
+ Christian Taedcke 9 (0.6%)
+ Andre Przywara 8 (0.6%)
+ Hai Pham 8 (0.6%)
+ Jim Liu 8 (0.6%)
+ Julien Masson 8 (0.6%)
+ Maxim Uvarov 8 (0.6%)
+ Alexander Dahl 7 (0.5%)
+ Adam Ford 7 (0.5%)
+ Sébastien Szymanski 7 (0.5%)
+ Ion Agorria 7 (0.5%)
+ Mayuresh Chitale 7 (0.5%)
+ Ilias Apalodimas 6 (0.4%)
+ Randolph 6 (0.4%)
+ Leo Yu-Chi Liang 6 (0.4%)
+ Emanuele Ghidoli 6 (0.4%)
+ Tim Lunn 6 (0.4%)
+ Neil Armstrong 5 (0.4%)
+ Hiago De Franco 5 (0.4%)
+ Joao Paulo Goncalves 5 (0.4%)
+ Josua Mayer 5 (0.4%)
+ Shantur Rathore 5 (0.4%)
+ Brandon Maier 5 (0.4%)
+ Ivan T. Ivanov 5 (0.4%)
+ Max Krummenacher 5 (0.4%)
+ Tim Harvey 5 (0.4%)
+ Maksim Kiselev 4 (0.3%)
+ Frieder Schrempf 4 (0.3%)
+ Jesse Taube 4 (0.3%)
+ Mattijs Korpershoek 4 (0.3%)
+ Radu Pirea (NXP OSS) 4 (0.3%)
+ Samuel Holland 4 (0.3%)
+ Chris Morgan 4 (0.3%)
+ Csókás Bence 4 (0.3%)
+ Vishal Mahaveer 4 (0.3%)
+ Hugo Villeneuve 4 (0.3%)
+ Tanmay Shah 4 (0.3%)
+ Francesco Dolcini 3 (0.2%)
+ Wadim Egorov 3 (0.2%)
+ Aurelien Jarno 3 (0.2%)
+ Nam Cao 3 (0.2%)
+ Janne Grunau 3 (0.2%)
+ Kongyang Liu 3 (0.2%)
+ Tejas Bhumkar 3 (0.2%)
+ Dinesh Maniyam 3 (0.2%)
+ Moritz Fischer 3 (0.2%)
+ Lukasz Majewski 3 (0.2%)
+ Miquel Raynal 3 (0.2%)
+ Robert Marko 3 (0.2%)
+ Rafał Miłecki 3 (0.2%)
+ Andrejs Cainikovs 3 (0.2%)
+ Jaehoon Chung 3 (0.2%)
+ Christophe Leroy 3 (0.2%)
+ Christian Hewitt 2 (0.1%)
+ Vitor Soares 2 (0.1%)
+ Dhruva Gole 2 (0.1%)
+ Minda Chen 2 (0.1%)
+ Dan Carpenter 2 (0.1%)
+ Marek Mojík 2 (0.1%)
+ Andrey Skvortsov 2 (0.1%)
+ Duy Nguyen 2 (0.1%)
+ Michael Trimarchi 2 (0.1%)
+ Primoz Fiser 2 (0.1%)
+ Kever Yang 2 (0.1%)
+ Lukasz Tekieli 2 (0.1%)
+ Zong Li 2 (0.1%)
+ Dmitry Malkin 2 (0.1%)
+ Wei Ming Chen 2 (0.1%)
+ Anthony Loiseau 2 (0.1%)
+ Ivan Orlov 2 (0.1%)
+ Chunfeng Yun 2 (0.1%)
+ Robert Catherall 2 (0.1%)
+ Reid Tonking 2 (0.1%)
+ Udit Kumar 2 (0.1%)
+ Etienne Carriere 2 (0.1%)
+ Arnaud Ferraris 2 (0.1%)
+ Dmitrii Merkurev 2 (0.1%)
+ David Oberhollenzer 2 (0.1%)
+ Douglas Anderson 1 (0.1%)
+ Daniel Schwierzeck 1 (0.1%)
+ Linus Walleij 1 (0.1%)
+ Benjamin Gray 1 (0.1%)
+ Mark Kettenis 1 (0.1%)
+ Thomas Weißschuh 1 (0.1%)
+ Conor Dooley 1 (0.1%)
+ Bo Gan 1 (0.1%)
+ Leon M. Busch-George 1 (0.1%)
+ Thomas Perrot 1 (0.1%)
+ Max Resch 1 (0.1%)
+ Ludwig Kormann 1 (0.1%)
+ Philippe Coval 1 (0.1%)
+ Sam Edwards 1 (0.1%)
+ Florian Schmaus 1 (0.1%)
+ Aradhya Bhatia 1 (0.1%)
+ Parth Pancholi 1 (0.1%)
+ Ian Ray 1 (0.1%)
+ Niklas Söderlund 1 (0.1%)
+ Nils Le Roux 1 (0.1%)
+ Saeed Nowshadi 1 (0.1%)
+ Mike Looijmans 1 (0.1%)
+ MD Danish Anwar 1 (0.1%)
+ Ole P. Orhagen 1 (0.1%)
+ Andy Yan 1 (0.1%)
+ YouMin Chen 1 (0.1%)
+ Matthias Brugger 1 (0.1%)
+ kleines Filmröllchen 1 (0.1%)
+ Vincent Chen 1 (0.1%)
+ Ralph Siemsen 1 (0.1%)
+ Chuanhong Guo 1 (0.1%)
+ Nick Alilovic 1 (0.1%)
+ Ssunk 1 (0.1%)
+ Yang Xiwen 1 (0.1%)
+ Prasanth Babu Mantena 1 (0.1%)
+ Yann Gautier 1 (0.1%)
+ Joshua Riek 1 (0.1%)
+ Slawomir Stepien 1 (0.1%)
+ John Clark 1 (0.1%)
+ Tianling Shen 1 (0.1%)
+ Johan Jonker 1 (0.1%)
+ Hugh Cole-Baker 1 (0.1%)
+ Sekhar Nori 1 (0.1%)
+ Tobias Deiminger 1 (0.1%)
+ Hugo Cornelis 1 (0.1%)
+ Oliver Faso 1 (0.1%)
+ TracyMg_Li 1 (0.1%)
+ Konrad Dybcio 1 (0.1%)
+ Anatolij Gustschin 1 (0.1%)
+ Grzegorz Szymaszek 1 (0.1%)
+ Alexey Romanov 1 (0.1%)
+ Paul-Erwan Rio 1 (0.1%)
+ Peter Robinson 1 (0.1%)
+ Chris Packham 1 (0.1%)
+ Shubhrajyoti Datta 1 (0.1%)
+ Raymond Mao 1 (0.1%)
+ Tomas Alvarez Vanoli 1 (0.1%)
+ Matthias Schiffer 1 (0.1%)
+ Cody Green 1 (0.1%)
+ Piotr Kubik 1 (0.1%)
+ Ayoub Zaki 1 (0.1%)
+ Nikita Shubin 1 (0.1%)
+ Peter Geis 1 (0.1%)
+ Bryan Brattlof 1 (0.1%)
+ Yong-Xuan Wang 1 (0.1%)
+ Kuan Lim Lee 1 (0.1%)
+ Jan Kiszka 1 (0.1%)
+ Bruce Suen 1 (0.1%)
+ Vaishnav Achath 1 (0.1%)
+ Benjamin Szőke 1 (0.1%)
+ Alessandro Rubini 1 (0.1%)
+ Doug Zobel 1 (0.1%)
+ Nicolas Heemeryck 1 (0.1%)
+ Ricardo Salveti 1 (0.1%)
+ Cem Tenruh 1 (0.1%)
+ Gilles Talis 1 (0.1%)
+ Shawn Guo 1 (0.1%)
+ Godfrey Mwangi 1 (0.1%)
+ Jit Loon Lim 1 (0.1%)
+ Teik Heng Chong 1 (0.1%)
+ William Zhang 1 (0.1%)
+ Alex Bee 1 (0.1%)
+ Francois Berder 1 (0.1%)
+ Thierry Reding 1 (0.1%)
+ Jai Luthra 1 (0.1%)
+ Vignesh Raghavendra 1 (0.1%)
+ Robert Nelson 1 (0.1%)
+ ==================================== =====
+
+
+.. table:: Developers with the most changed lines
+ :widths: auto
+
+ ==================================== =====
+ Name Count
+ ==================================== =====
+ Neha Malcom Francis 16332 (11.2%)
+ Francis Laniel 14974 (10.3%)
+ Svyatoslav Ryhel 10521 (7.2%)
+ Tom Rini 9300 (6.4%)
+ Nishanth Menon 8556 (5.9%)
+ Mathieu Othacehe 6259 (4.3%)
+ Sam Protsenko 5717 (3.9%)
+ Wadim Egorov 5475 (3.8%)
+ Hai Pham 5242 (3.6%)
+ Marek Vasut 4753 (3.3%)
+ Robert Nelson 3746 (2.6%)
+ Julien Masson 3705 (2.5%)
+ Sean Anderson 3232 (2.2%)
+ Simon Glass 2938 (2.0%)
+ Gilles Talis 2893 (2.0%)
+ Heinrich Schuchardt 2839 (2.0%)
+ Love Kumar 2531 (1.7%)
+ Caleb Connolly 2350 (1.6%)
+ AKASHI Takahiro 2036 (1.4%)
+ Patrice Chotard 1685 (1.2%)
+ Manorit Chawdhry 1633 (1.1%)
+ Tim Lunn 1492 (1.0%)
+ Frieder Schrempf 1299 (0.9%)
+ Fabio Estevam 1241 (0.9%)
+ Masahisa Kojima 1168 (0.8%)
+ Andre Przywara 1116 (0.8%)
+ Neil Armstrong 1027 (0.7%)
+ Igor Prusov 999 (0.7%)
+ Paul Barker 911 (0.6%)
+ Cem Tenruh 905 (0.6%)
+ Joshua Riek 903 (0.6%)
+ Yannic Moog 828 (0.6%)
+ Jonas Karlman 796 (0.5%)
+ Andrew Davis 794 (0.5%)
+ TracyMg_Li 684 (0.5%)
+ Doug Zobel 654 (0.4%)
+ Vishal Mahaveer 651 (0.4%)
+ Quentin Schulz 649 (0.4%)
+ Enrico Leto 605 (0.4%)
+ Michal Simek 578 (0.4%)
+ Randolph 448 (0.3%)
+ Jesse Taube 431 (0.3%)
+ Jim Liu 424 (0.3%)
+ Konrad Dybcio 421 (0.3%)
+ Kongyang Liu 409 (0.3%)
+ Venkatesh Yadav Abbarapu 381 (0.3%)
+ Emanuele Ghidoli 370 (0.3%)
+ Adam Ford 337 (0.2%)
+ Igor Opaniuk 324 (0.2%)
+ Patrick Delaunay 272 (0.2%)
+ Rasmus Villemoes 256 (0.2%)
+ Ion Agorria 253 (0.2%)
+ Dmitrii Merkurev 242 (0.2%)
+ Benjamin Hahn 235 (0.2%)
+ Ilias Apalodimas 226 (0.2%)
+ Roger Quadros 218 (0.1%)
+ Jai Luthra 214 (0.1%)
+ Brandon Maier 209 (0.1%)
+ Robert Marko 205 (0.1%)
+ Vignesh Raghavendra 200 (0.1%)
+ Takahiro Kuwano 177 (0.1%)
+ Shubhrajyoti Datta 174 (0.1%)
+ Christian Taedcke 173 (0.1%)
+ Tanmay Shah 171 (0.1%)
+ Devarsh Thakkar 166 (0.1%)
+ Johan Jonker 165 (0.1%)
+ Tianling Shen 163 (0.1%)
+ Chris Morgan 159 (0.1%)
+ Benjamin Szőke 151 (0.1%)
+ Duy Nguyen 145 (0.1%)
+ Lukasz Majewski 142 (0.1%)
+ Lukasz Tekieli 138 (0.1%)
+ Max Resch 132 (0.1%)
+ Sébastien Szymanski 114 (0.1%)
+ Anatolij Gustschin 112 (0.1%)
+ Max Krummenacher 111 (0.1%)
+ Bin Meng 105 (0.1%)
+ Dario Binacchi 100 (0.1%)
+ Ivan T. Ivanov 97 (0.1%)
+ Leo Yu-Chi Liang 96 (0.1%)
+ Mayuresh Chitale 83 (0.1%)
+ Hiago De Franco 83 (0.1%)
+ David Oberhollenzer 81 (0.1%)
+ Alexander Dahl 79 (0.1%)
+ Raymond Mao 78 (0.1%)
+ Dmitry Malkin 74 (0.1%)
+ Zong Li 73 (0.1%)
+ Tim Harvey 69 (0.0%)
+ Vincent Chen 67 (0.0%)
+ Chunfeng Yun 66 (0.0%)
+ Maksim Kiselev 61 (0.0%)
+ Csókás Bence 61 (0.0%)
+ Marek Mojík 61 (0.0%)
+ Peter Robinson 59 (0.0%)
+ Aradhya Bhatia 56 (0.0%)
+ Rafał Miłecki 54 (0.0%)
+ Chris Packham 51 (0.0%)
+ Primoz Fiser 50 (0.0%)
+ Francesco Dolcini 49 (0.0%)
+ Samuel Holland 48 (0.0%)
+ Josua Mayer 45 (0.0%)
+ Radu Pirea (NXP OSS) 41 (0.0%)
+ Yong-Xuan Wang 38 (0.0%)
+ Mattijs Korpershoek 36 (0.0%)
+ Shantur Rathore 34 (0.0%)
+ Parth Pancholi 34 (0.0%)
+ Andrey Skvortsov 33 (0.0%)
+ Hugo Cornelis 32 (0.0%)
+ Vaishnav Achath 32 (0.0%)
+ Joao Paulo Goncalves 30 (0.0%)
+ Nicolas Heemeryck 30 (0.0%)
+ Arnaud Ferraris 28 (0.0%)
+ Nick Alilovic 28 (0.0%)
+ Maxim Uvarov 26 (0.0%)
+ Matthias Schiffer 26 (0.0%)
+ Nam Cao 25 (0.0%)
+ Janne Grunau 21 (0.0%)
+ Dinesh Maniyam 20 (0.0%)
+ Jaehoon Chung 20 (0.0%)
+ Christophe Leroy 20 (0.0%)
+ Miquel Raynal 18 (0.0%)
+ Andrejs Cainikovs 18 (0.0%)
+ Udit Kumar 18 (0.0%)
+ Linus Walleij 18 (0.0%)
+ Hugo Villeneuve 17 (0.0%)
+ Moritz Fischer 17 (0.0%)
+ Conor Dooley 16 (0.0%)
+ Ricardo Salveti 16 (0.0%)
+ Christian Hewitt 15 (0.0%)
+ Vitor Soares 15 (0.0%)
+ Alexey Romanov 15 (0.0%)
+ Tejas Bhumkar 13 (0.0%)
+ Anthony Loiseau 13 (0.0%)
+ Yang Xiwen 13 (0.0%)
+ Piotr Kubik 13 (0.0%)
+ Dhruva Gole 12 (0.0%)
+ Andy Yan 12 (0.0%)
+ Chuanhong Guo 12 (0.0%)
+ Hugh Cole-Baker 12 (0.0%)
+ Robert Catherall 11 (0.0%)
+ Reid Tonking 11 (0.0%)
+ Nikita Shubin 11 (0.0%)
+ Bryan Brattlof 11 (0.0%)
+ Michael Trimarchi 10 (0.0%)
+ Paul-Erwan Rio 10 (0.0%)
+ Thierry Reding 10 (0.0%)
+ Etienne Carriere 9 (0.0%)
+ Sam Edwards 9 (0.0%)
+ Niklas Söderlund 9 (0.0%)
+ Nils Le Roux 9 (0.0%)
+ MD Danish Anwar 9 (0.0%)
+ Kuan Lim Lee 9 (0.0%)
+ YouMin Chen 8 (0.0%)
+ Benjamin Gray 7 (0.0%)
+ Mark Kettenis 7 (0.0%)
+ Ayoub Zaki 7 (0.0%)
+ Shawn Guo 7 (0.0%)
+ Aurelien Jarno 6 (0.0%)
+ Ian Ray 6 (0.0%)
+ Ole P. Orhagen 6 (0.0%)
+ Alex Bee 6 (0.0%)
+ Saeed Nowshadi 5 (0.0%)
+ Mike Looijmans 5 (0.0%)
+ Tobias Deiminger 5 (0.0%)
+ Cody Green 5 (0.0%)
+ Teik Heng Chong 5 (0.0%)
+ Kever Yang 4 (0.0%)
+ Douglas Anderson 4 (0.0%)
+ Bo Gan 4 (0.0%)
+ Matthias Brugger 4 (0.0%)
+ Ssunk 4 (0.0%)
+ Ralph Siemsen 3 (0.0%)
+ Yann Gautier 3 (0.0%)
+ Grzegorz Szymaszek 3 (0.0%)
+ Minda Chen 2 (0.0%)
+ Dan Carpenter 2 (0.0%)
+ Wei Ming Chen 2 (0.0%)
+ Ivan Orlov 2 (0.0%)
+ Daniel Schwierzeck 2 (0.0%)
+ Ludwig Kormann 2 (0.0%)
+ Philippe Coval 2 (0.0%)
+ Prasanth Babu Mantena 2 (0.0%)
+ Oliver Faso 2 (0.0%)
+ Jan Kiszka 2 (0.0%)
+ Bruce Suen 2 (0.0%)
+ Thomas Weißschuh 1 (0.0%)
+ Leon M. Busch-George 1 (0.0%)
+ Thomas Perrot 1 (0.0%)
+ Florian Schmaus 1 (0.0%)
+ kleines Filmröllchen 1 (0.0%)
+ Slawomir Stepien 1 (0.0%)
+ John Clark 1 (0.0%)
+ Sekhar Nori 1 (0.0%)
+ Tomas Alvarez Vanoli 1 (0.0%)
+ Peter Geis 1 (0.0%)
+ Alessandro Rubini 1 (0.0%)
+ Godfrey Mwangi 1 (0.0%)
+ Jit Loon Lim 1 (0.0%)
+ William Zhang 1 (0.0%)
+ Francois Berder 1 (0.0%)
+ ==================================== =====
+
+
+.. table:: Developers with the most lines removed
+ :widths: auto
+
+ ==================================== =====
+ Name Count
+ ==================================== =====
+ Tom Rini 6982 (14.5%)
+ Marek Vasut 3629 (7.5%)
+ Neha Malcom Francis 3284 (6.8%)
+ Enrico Leto 333 (0.7%)
+ Andrew Davis 315 (0.7%)
+ Vishal Mahaveer 211 (0.4%)
+ Shubhrajyoti Datta 174 (0.4%)
+ Quentin Schulz 103 (0.2%)
+ Roger Quadros 69 (0.1%)
+ Takahiro Kuwano 57 (0.1%)
+ Francesco Dolcini 48 (0.1%)
+ David Oberhollenzer 35 (0.1%)
+ Yong-Xuan Wang 18 (0.0%)
+ Hugo Villeneuve 14 (0.0%)
+ Ricardo Salveti 4 (0.0%)
+ Sam Edwards 3 (0.0%)
+ Christophe Leroy 2 (0.0%)
+ Nam Cao 1 (0.0%)
+ Thierry Reding 1 (0.0%)
+ Ian Ray 1 (0.0%)
+ Jan Kiszka 1 (0.0%)
+ ==================================== =====
+
+
+.. table:: Developers with the most signoffs (total 184)
+ :widths: auto
+
+ ==================================== =====
+ Name Count
+ ==================================== =====
+ Michal Simek 26 (14.1%)
+ Mattijs Korpershoek 21 (11.4%)
+ Minkyu Kang 20 (10.9%)
+ Raymond Mao 12 (6.5%)
+ Ilias Apalodimas 10 (5.4%)
+ Svyatoslav Ryhel 8 (4.3%)
+ Tom Rini 7 (3.8%)
+ Francesco Dolcini 7 (3.8%)
+ Matthias Brugger 7 (3.8%)
+ Dario Binacchi 7 (3.8%)
+ Simon Glass 5 (2.7%)
+ Jagan Teki 3 (1.6%)
+ Neil Armstrong 3 (1.6%)
+ Heinrich Schuchardt 3 (1.6%)
+ Nishanth Menon 3 (1.6%)
+ Jonathan Corbet 2 (1.1%)
+ CL Wang 2 (1.1%)
+ Apurva Nandan 2 (1.1%)
+ Oleksandr Suvorov 2 (1.1%)
+ Ivan T. Ivanov 2 (1.1%)
+ Patrick Delaunay 2 (1.1%)
+ Jonas Karlman 2 (1.1%)
+ Sean Anderson 2 (1.1%)
+ Hai Pham 2 (1.1%)
+ Lukasz Majewski 1 (0.5%)
+ Daniel Schwierzeck 1 (0.5%)
+ Marek Behún 1 (0.5%)
+ Guillaume La Roque 1 (0.5%)
+ Nylon Chen 1 (0.5%)
+ Alexandre Torgue 1 (0.5%)
+ Harald Seiler 1 (0.5%)
+ Holger Brunck 1 (0.5%)
+ Siddharth Vadapalli 1 (0.5%)
+ Wei Liang Lim 1 (0.5%)
+ Martin Kurbanov 1 (0.5%)
+ Dmitry Rokosov 1 (0.5%)
+ Sreekanth Sunnam 1 (0.5%)
+ Cody Schuffelen 1 (0.5%)
+ Kever Yang 1 (0.5%)
+ Reid Tonking 1 (0.5%)
+ Bryan Brattlof 1 (0.5%)
+ Chuanhong Guo 1 (0.5%)
+ Zong Li 1 (0.5%)
+ Rasmus Villemoes 1 (0.5%)
+ Caleb Connolly 1 (0.5%)
+ Andre Przywara 1 (0.5%)
+ Masahisa Kojima 1 (0.5%)
+ Patrice Chotard 1 (0.5%)
+ ==================================== =====
+
+
+.. table:: Developers with the most reviews (total 899)
+ :widths: auto
+
+ ==================================== =====
+ Name Count
+ ==================================== =====
+ Simon Glass 181 (20.1%)
+ Tom Rini 79 (8.8%)
+ Ilias Apalodimas 66 (7.3%)
+ Kever Yang 48 (5.3%)
+ Fabio Estevam 38 (4.2%)
+ Mattijs Korpershoek 34 (3.8%)
+ Patrice Chotard 31 (3.4%)
+ Leo Yu-Chi Liang 30 (3.3%)
+ Heinrich Schuchardt 29 (3.2%)
+ Paul Barker 29 (3.2%)
+ Jagan Teki 22 (2.4%)
+ Marek Vasut 22 (2.4%)
+ Sumit Garg 21 (2.3%)
+ Neha Malcom Francis 20 (2.2%)
+ Andre Przywara 16 (1.8%)
+ Neil Armstrong 15 (1.7%)
+ Patrick Delaunay 15 (1.7%)
+ Sean Anderson 12 (1.3%)
+ Roger Quadros 10 (1.1%)
+ Peng Fan 10 (1.1%)
+ Jonathan Humphreys 10 (1.1%)
+ Igor Opaniuk 10 (1.1%)
+ Nishanth Menon 9 (1.0%)
+ Francesco Dolcini 7 (0.8%)
+ Chanho Park 7 (0.8%)
+ Stefan Roese 6 (0.7%)
+ Yu Chien Peter Lin 6 (0.7%)
+ Michael Trimarchi 6 (0.7%)
+ Dhruva Gole 6 (0.7%)
+ Dario Binacchi 5 (0.6%)
+ Andrew Davis 5 (0.6%)
+ Ian Ray 5 (0.6%)
+ Peter Robinson 5 (0.6%)
+ Michal Simek 4 (0.4%)
+ Ramon Fried 4 (0.4%)
+ Sam Protsenko 4 (0.4%)
+ Matthias Brugger 3 (0.3%)
+ Bryan Brattlof 3 (0.3%)
+ Christian Gmeiner 3 (0.3%)
+ Dragan Simic 3 (0.3%)
+ Alexander Sverdlin 3 (0.3%)
+ Nikhil M Jain 3 (0.3%)
+ Tien Fong Chee 3 (0.3%)
+ Teresa Remmet 3 (0.3%)
+ Etienne Carriere 3 (0.3%)
+ Manorit Chawdhry 3 (0.3%)
+ Lukasz Majewski 2 (0.2%)
+ Caleb Connolly 2 (0.2%)
+ Hugo Villeneuve 2 (0.2%)
+ Eugen Hristev 2 (0.2%)
+ Jens Wiklander 2 (0.2%)
+ Joao Marcos Costa 2 (0.2%)
+ Dan Carpenter 2 (0.2%)
+ Mark Kettenis 2 (0.2%)
+ Conor Dooley 2 (0.2%)
+ Udit Kumar 2 (0.2%)
+ Bin Meng 2 (0.2%)
+ Svyatoslav Ryhel 1 (0.1%)
+ Marek Behún 1 (0.1%)
+ Harald Seiler 1 (0.1%)
+ Masahisa Kojima 1 (0.1%)
+ Jernej Skrabec 1 (0.1%)
+ Geert Uytterhoeven 1 (0.1%)
+ Giulio Benetti 1 (0.1%)
+ Ravi Gunasekaran 1 (0.1%)
+ Weizhao Ouyang 1 (0.1%)
+ Philip Oberfichtner 1 (0.1%)
+ Padmarao Begari 1 (0.1%)
+ Pratyush Yadav 1 (0.1%)
+ Radhey Shyam Pandey 1 (0.1%)
+ Qu Wenruo 1 (0.1%)
+ Stefan Bosch 1 (0.1%)
+ Aleksandar Gerasimovski 1 (0.1%)
+ Miquel Raynal 1 (0.1%)
+ Linus Walleij 1 (0.1%)
+ Yannic Moog 1 (0.1%)
+ Frieder Schrempf 1 (0.1%)
+ ==================================== =====
+
+
+.. table:: Developers with the most test credits (total 84)
+ :widths: auto
+
+ ==================================== =====
+ Name Count
+ ==================================== =====
+ Sumit Garg 9 (10.7%)
+ Marcel Ziswiler 7 (8.3%)
+ Jens Maus 7 (8.3%)
+ Darko Alavanja 7 (8.3%)
+ Mattijs Korpershoek 4 (4.8%)
+ Patrice Chotard 4 (4.8%)
+ Nishanth Menon 4 (4.8%)
+ Dhruva Gole 4 (4.8%)
+ Andre Przywara 3 (3.6%)
+ Love Kumar 3 (3.6%)
+ Peter Robinson 2 (2.4%)
+ Christian Gmeiner 2 (2.4%)
+ Sam Edwards 2 (2.4%)
+ Hiago De Franco 2 (2.4%)
+ Simon Glass 1 (1.2%)
+ Ilias Apalodimas 1 (1.2%)
+ Fabio Estevam 1 (1.2%)
+ Leo Yu-Chi Liang 1 (1.2%)
+ Marek Vasut 1 (1.2%)
+ Chanho Park 1 (1.2%)
+ Conor Dooley 1 (1.2%)
+ Svyatoslav Ryhel 1 (1.2%)
+ Martin Kurbanov 1 (1.2%)
+ Enrico Leto 1 (1.2%)
+ Bartel Eerdekens 1 (1.2%)
+ Matwey V. Kornilov 1 (1.2%)
+ Akira Yokosawa 1 (1.2%)
+ Heiko Schocher 1 (1.2%)
+ Thomas Richard 1 (1.2%)
+ Agneli 1 (1.2%)
+ Lisandro Pérez Meyer 1 (1.2%)
+ Oliver Graute 1 (1.2%)
+ Slawomir Stepien 1 (1.2%)
+ Aurelien Jarno 1 (1.2%)
+ Primoz Fiser 1 (1.2%)
+ Alexander Dahl 1 (1.2%)
+ Adam Ford 1 (1.2%)
+ Mathieu Othacehe 1 (1.2%)
+ ==================================== =====
+
+
+.. table:: Developers who gave the most tested-by credits (total 84)
+ :widths: auto
+
+ ==================================== =====
+ Name Count
+ ==================================== =====
+ Caleb Connolly 10 (11.9%)
+ Ivan T. Ivanov 10 (11.9%)
+ Fabio Estevam 6 (7.1%)
+ Emanuele Ghidoli 6 (7.1%)
+ Igor Prusov 5 (6.0%)
+ Nishanth Menon 4 (4.8%)
+ Dmitry Malkin 4 (4.8%)
+ Heinrich Schuchardt 3 (3.6%)
+ Roger Quadros 3 (3.6%)
+ Andrew Davis 3 (3.6%)
+ Mayuresh Chitale 3 (3.6%)
+ Ilias Apalodimas 2 (2.4%)
+ Dmitrii Merkurev 2 (2.4%)
+ Simon Glass 1 (1.2%)
+ Svyatoslav Ryhel 1 (1.2%)
+ Primoz Fiser 1 (1.2%)
+ Mathieu Othacehe 1 (1.2%)
+ Tom Rini 1 (1.2%)
+ Manorit Chawdhry 1 (1.2%)
+ Masahisa Kojima 1 (1.2%)
+ Miquel Raynal 1 (1.2%)
+ Linus Walleij 1 (1.2%)
+ Jonas Karlman 1 (1.2%)
+ Prasanth Babu Mantena 1 (1.2%)
+ Oliver Faso 1 (1.2%)
+ Paul-Erwan Rio 1 (1.2%)
+ Robert Catherall 1 (1.2%)
+ Niklas Söderlund 1 (1.2%)
+ Joao Paulo Goncalves 1 (1.2%)
+ Shantur Rathore 1 (1.2%)
+ Maksim Kiselev 1 (1.2%)
+ Benjamin Szőke 1 (1.2%)
+ Ion Agorria 1 (1.2%)
+ Jesse Taube 1 (1.2%)
+ Randolph 1 (1.2%)
+ Joshua Riek 1 (1.2%)
+ ==================================== =====
+
+
+.. table:: Developers with the most report credits (total 20)
+ :widths: auto
+
+ ==================================== =====
+ Name Count
+ ==================================== =====
+ Simon Glass 2 (10.0%)
+ Tom Rini 2 (10.0%)
+ Marcel Ziswiler 2 (10.0%)
+ Dan Carpenter 2 (10.0%)
+ Trevor Woerner 2 (10.0%)
+ Heinrich Schuchardt 1 (5.0%)
+ Andre Przywara 1 (5.0%)
+ Christian Gmeiner 1 (5.0%)
+ Hiago De Franco 1 (5.0%)
+ Lisandro Pérez Meyer 1 (5.0%)
+ Neil Armstrong 1 (5.0%)
+ Sagar Karmarkar 1 (5.0%)
+ E Shattow 1 (5.0%)
+ Dave Jones 1 (5.0%)
+ Hong Guan 1 (5.0%)
+ ==================================== =====
+
+
+.. table:: Developers who gave the most report credits (total 23)
+ :widths: auto
+
+ ==================================== =====
+ Name Count
+ ==================================== =====
+ Fabio Estevam 6 (26.1%)
+ Tom Rini 4 (17.4%)
+ Heinrich Schuchardt 2 (8.7%)
+ Jonas Karlman 2 (8.7%)
+ Simon Glass 1 (4.3%)
+ Caleb Connolly 1 (4.3%)
+ Nishanth Menon 1 (4.3%)
+ Roger Quadros 1 (4.3%)
+ Aurelien Jarno 1 (4.3%)
+ Sean Anderson 1 (4.3%)
+ Michal Simek 1 (4.3%)
+ Frieder Schrempf 1 (4.3%)
+ Devarsh Thakkar 1 (4.3%)
+ ==================================== =====
+
+
+.. table:: Top changeset contributors by employer
+ :widths: auto
+
+ ==================================== =====
+ Name Count
+ ==================================== =====
+ (Unknown) 543 (38.7%)
+ Google LLC 149 (10.6%)
+ Texas Instruments 118 (8.4%)
+ Linaro 97 (6.9%)
+ Konsulko Group 89 (6.3%)
+ Renesas Electronics 72 (5.1%)
+ AMD 66 (4.7%)
+ DENX Software Engineering 46 (3.3%)
+ Amarula Solutions 38 (2.7%)
+ ST Microelectronics 32 (2.3%)
+ Toradex 28 (2.0%)
+ Phytec 23 (1.6%)
+ Socionext Inc. 21 (1.5%)
+ Siemens 14 (1.0%)
+ BayLibre SAS 12 (0.9%)
+ ARM 10 (0.7%)
+ Weidmüller Interface GmbH & Co. KG 9 (0.6%)
+ SUSE 6 (0.4%)
+ Intel 5 (0.4%)
+ Bootlin 4 (0.3%)
+ NXP 4 (0.3%)
+ linutronix 4 (0.3%)
+ Rockchip 4 (0.3%)
+ Samsung 3 (0.2%)
+ Collabora Ltd. 2 (0.1%)
+ Broadcom 1 (0.1%)
+ IBM 1 (0.1%)
+ NVidia 1 (0.1%)
+ ==================================== =====
+
+
+.. table:: Top lines changed by employer
+ :widths: auto
+
+ ==================================== =====
+ Name Count
+ ==================================== =====
+ (Unknown) 43650 (30.0%)
+ Texas Instruments 28698 (19.7%)
+ Amarula Solutions 15084 (10.4%)
+ Linaro 11911 (8.2%)
+ Renesas Electronics 10853 (7.5%)
+ Konsulko Group 9300 (6.4%)
+ Phytec 7443 (5.1%)
+ AMD 3853 (2.7%)
+ BayLibre SAS 3741 (2.6%)
+ Google LLC 3201 (2.2%)
+ ST Microelectronics 1969 (1.4%)
+ DENX Software Engineering 1602 (1.1%)
+ Socionext Inc. 1168 (0.8%)
+ ARM 1127 (0.8%)
+ Toradex 660 (0.5%)
+ Siemens 607 (0.4%)
+ Weidmüller Interface GmbH & Co. KG 173 (0.1%)
+ SUSE 101 (0.1%)
+ NXP 41 (0.0%)
+ linutronix 30 (0.0%)
+ Collabora Ltd. 28 (0.0%)
+ Intel 26 (0.0%)
+ Rockchip 24 (0.0%)
+ Samsung 20 (0.0%)
+ Bootlin 19 (0.0%)
+ NVidia 10 (0.0%)
+ IBM 7 (0.0%)
+ Broadcom 1 (0.0%)
+ ==================================== =====
+
+
+.. table:: Employers with the most signoffs (total 184)
+ :widths: auto
+
+ ==================================== =====
+ Name Count
+ ==================================== =====
+ Linaro 27 (14.7%)
+ AMD 27 (14.7%)
+ (Unknown) 26 (14.1%)
+ BayLibre SAS 22 (12.0%)
+ Samsung 20 (10.9%)
+ Amarula Solutions 9 (4.9%)
+ SUSE 9 (4.9%)
+ Texas Instruments 8 (4.3%)
+ Konsulko Group 7 (3.8%)
+ Toradex 7 (3.8%)
+ Google LLC 6 (3.3%)
+ ST Microelectronics 4 (2.2%)
+ Canonical 3 (1.6%)
+ Renesas Electronics 2 (1.1%)
+ DENX Software Engineering 2 (1.1%)
+ LWN.net 2 (1.1%)
+ ARM 1 (0.5%)
+ Rockchip 1 (0.5%)
+ Edgeble AI Technologies Pvt. Ltd. 1 (0.5%)
+ ==================================== =====
+
+
+.. table:: Employers with the most hackers (total 203)
+ :widths: auto
+
+ ==================================== =====
+ Name Count
+ ==================================== =====
+ (Unknown) 109 (53.7%)
+ Texas Instruments 17 (8.4%)
+ Linaro 12 (5.9%)
+ Toradex 8 (3.9%)
+ AMD 7 (3.4%)
+ Google LLC 4 (2.0%)
+ ST Microelectronics 4 (2.0%)
+ Renesas Electronics 4 (2.0%)
+ DENX Software Engineering 4 (2.0%)
+ Phytec 4 (2.0%)
+ Amarula Solutions 3 (1.5%)
+ Rockchip 3 (1.5%)
+ Intel 3 (1.5%)
+ BayLibre SAS 2 (1.0%)
+ SUSE 2 (1.0%)
+ ARM 2 (1.0%)
+ Siemens 2 (1.0%)
+ linutronix 2 (1.0%)
+ Bootlin 2 (1.0%)
+ Samsung 1 (0.5%)
+ Konsulko Group 1 (0.5%)
+ Socionext Inc. 1 (0.5%)
+ Weidmüller Interface GmbH & Co. KG 1 (0.5%)
+ NXP 1 (0.5%)
+ Collabora Ltd. 1 (0.5%)
+ NVidia 1 (0.5%)
+ IBM 1 (0.5%)
+ Broadcom 1 (0.5%)
+ ==================================== =====
diff --git a/doc/device-tree-bindings/misc/socfpga_dtreg.txt b/doc/device-tree-bindings/misc/socfpga_dtreg.txt
new file mode 100644
index 0000000..cf40fdd
--- /dev/null
+++ b/doc/device-tree-bindings/misc/socfpga_dtreg.txt
@@ -0,0 +1,80 @@
+* Firewall and privilege register settings in device tree
+
+Required properties:
+--------------------
+
+- compatible: should contain "intel,socfpga-dtreg"
+- reg: Physical base address and size of block register.
+- intel,offset-settings: 32-bit offset address of block register,
+ followed by 32-bit value settings and
+ the masking bits, only masking bit
+ set to 1 allows modification.
+
+The device tree node which describes secure and privilege register access
+configuration in compile time.
+
+Most of these registers are expected to work except for the case which some
+registers configuration are required for granting access to some other
+registers, for example CCU registers have to be properly configured before
+allowing register configuration access to fpga2sdram firewall as shown in
+below example.
+
+Some registers depend on runtime data for proper configuration are expected
+to be part of driver that generating these data for example configuration for
+soc_noc_fw_ddr_mpu_inst_0_ddr_scr block register depend on DDR size parsed from
+memory device tree node.
+
+Please refer details of tested examples below for both fpga2sdram and QoS
+configuration with default reset value and the comments.
+
+Example:
+--------
+
+Configuration for multiple dtreg node support in device tree:
+
+ socfpga_dtreg0: socfpga-dtreg0 {
+ compatible = "intel,socfpga-dtreg";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ bootph-all;
+
+ coh_cpu0_bypass_OC_Firewall_main_Firewall@f7100200 {
+ reg = <0xf7100200 0x00000014>;
+ intel,offset-settings =
+ /*
+ * Disable ocram security at CCU for
+ * non secure access
+ */
+ <0x0000004 0x8000ffff 0xe007ffff>,
+ <0x0000008 0x8000ffff 0xe007ffff>,
+ <0x000000c 0x8000ffff 0xe007ffff>,
+ <0x0000010 0x8000ffff 0xe007ffff>;
+ bootph-all;
+ };
+ };
+
+ socfpga_dtreg1: socfpga-dtreg1 {
+ compatible = "intel,socfpga-dtreg";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ bootph-all;
+
+ soc_noc_fw_mpfe_csr_inst_0_mpfe_scr@f8020000 {
+ reg = <0xf8020000 0x0000001c>;
+ intel,offset-settings =
+ /* Disable MPFE firewall for SMMU */
+ <0x00000000 0x00010101 0x00010101>,
+ /*
+ * Disable MPFE firewall for HMC
+ * adapter
+ */
+ <0x00000004 0x00000001 0x00010101>;
+ bootph-all;
+ };
+ };
+
+To call the nodes use:
+
+ ret = uclass_get_device_by_name(UCLASS_NOP, "socfpga-dtreg0", &dev);
+ ret = uclass_get_device_by_name(UCLASS_NOP, "socfpga-dtreg1", &dev);
+
diff --git a/doc/sphinx/cdomain.py b/doc/sphinx/cdomain.py
index 014a522..491a7ed 100644
--- a/doc/sphinx/cdomain.py
+++ b/doc/sphinx/cdomain.py
@@ -93,7 +93,7 @@
#
RE_expr = re.compile(r':c:(expr|texpr):`([^\`]+)`')
def markup_c_expr(match):
- return '\ ``' + match.group(2) + '``\ '
+ return '\\ ``' + match.group(2) + '``\\ '
#
# Parse Sphinx 3.x C markups, replacing them by backward-compatible ones
diff --git a/doc/sphinx/kernel_abi.py b/doc/sphinx/kernel_abi.py
index f3da859..32c50e4 100644
--- a/doc/sphinx/kernel_abi.py
+++ b/doc/sphinx/kernel_abi.py
@@ -147,7 +147,7 @@
code_block += "\n " + l
lines = code_block + "\n\n"
- line_regex = re.compile("^#define LINENO (\S+)\#([0-9]+)$")
+ line_regex = re.compile(r"^#define LINENO (\S+)\#([0-9]+)$")
ln = 0
n = 0
f = fname
diff --git a/doc/sphinx/kerneldoc.py b/doc/sphinx/kerneldoc.py
index 01a5542..bc8bb9e 100644
--- a/doc/sphinx/kerneldoc.py
+++ b/doc/sphinx/kerneldoc.py
@@ -130,7 +130,7 @@
result = ViewList()
lineoffset = 0;
- line_regex = re.compile("^#define LINENO ([0-9]+)$")
+ line_regex = re.compile(r"^#define LINENO ([0-9]+)$")
for line in lines:
match = line_regex.search(line)
if match:
diff --git a/doc/sphinx/maintainers_include.py b/doc/sphinx/maintainers_include.py
index dc8fed4..13557d3 100755
--- a/doc/sphinx/maintainers_include.py
+++ b/doc/sphinx/maintainers_include.py
@@ -78,8 +78,8 @@
# Drop needless input whitespace.
line = line.rstrip()
- # Linkify all non-wildcard refs to ReST files in Documentation/.
- pat = '(Documentation/([^\s\?\*]*)\.rst)'
+ # Linkify all non-wildcard refs to ReST files in doc/.
+ pat = r'(doc/([^\s\?\*]*)\.rst)'
m = re.search(pat, line)
if m:
# maintainers.rst is in a subdirectory, so include "../".
@@ -92,11 +92,11 @@
output = "| %s" % (line.replace("\\", "\\\\"))
# Look for and record field letter to field name mappings:
# R: Designated *reviewer*: FullName <address@domain>
- m = re.search("\s(\S):\s", line)
+ m = re.search(r"\s(\S):\s", line)
if m:
field_letter = m.group(1)
if field_letter and not field_letter in fields:
- m = re.search("\*([^\*]+)\*", line)
+ m = re.search(r"\*([^\*]+)\*", line)
if m:
fields[field_letter] = m.group(1)
elif subsystems:
@@ -114,7 +114,7 @@
field_content = ""
# Collapse whitespace in subsystem name.
- heading = re.sub("\s+", " ", line)
+ heading = re.sub(r"\s+", " ", line)
output = output + "%s\n%s" % (heading, "~" * len(heading))
field_prev = ""
else:
@@ -177,11 +177,11 @@
if not self.state.document.settings.file_insertion_enabled:
raise self.warning('"%s" directive disabled.' % self.name)
- # Walk up source path directories to find Documentation/../
+ # Walk up source path directories to find doc/../
path = self.state_machine.document.attributes['source']
path = os.path.realpath(path)
tail = path
- while tail != "Documentation" and tail != "":
+ while tail != "doc" and tail != "":
(path, tail) = os.path.split(path)
# Append "MAINTAINERS"
diff --git a/doc/usage/cmd/acpi.rst b/doc/usage/cmd/acpi.rst
index a630f1e..9f30972 100644
--- a/doc/usage/cmd/acpi.rst
+++ b/doc/usage/cmd/acpi.rst
@@ -6,8 +6,8 @@
acpi command
============
-Synopis
--------
+Synopsis
+--------
::
diff --git a/doc/usage/cmd/bootdev.rst b/doc/usage/cmd/bootdev.rst
index 658020e..f759aba 100644
--- a/doc/usage/cmd/bootdev.rst
+++ b/doc/usage/cmd/bootdev.rst
@@ -6,8 +6,8 @@
bootdev command
===============
-Synopis
--------
+Synopsis
+--------
::
diff --git a/doc/usage/cmd/bootflow.rst b/doc/usage/cmd/bootflow.rst
index 16ba986..6519e48 100644
--- a/doc/usage/cmd/bootflow.rst
+++ b/doc/usage/cmd/bootflow.rst
@@ -6,8 +6,8 @@
bootflow command
================
-Synopis
--------
+Synopsis
+--------
::
diff --git a/doc/usage/cmd/bootmeth.rst b/doc/usage/cmd/bootmeth.rst
index 95651fd..2903977 100644
--- a/doc/usage/cmd/bootmeth.rst
+++ b/doc/usage/cmd/bootmeth.rst
@@ -6,8 +6,8 @@
bootmeth command
================
-Synopis
--------
+Synopsis
+--------
::
diff --git a/doc/usage/cmd/cbsysinfo.rst b/doc/usage/cmd/cbsysinfo.rst
index 8c03a85..80d8ba1 100644
--- a/doc/usage/cmd/cbsysinfo.rst
+++ b/doc/usage/cmd/cbsysinfo.rst
@@ -3,8 +3,8 @@
cbsysinfo
=========
-Synopis
--------
+Synopsis
+--------
::
diff --git a/doc/usage/cmd/cedit.rst b/doc/usage/cmd/cedit.rst
index b39d708..5670805 100644
--- a/doc/usage/cmd/cedit.rst
+++ b/doc/usage/cmd/cedit.rst
@@ -6,8 +6,8 @@
cedit command
=============
-Synopis
--------
+Synopsis
+--------
::
diff --git a/doc/usage/cmd/cli.rst b/doc/usage/cmd/cli.rst
index 8148772..23e5ee7 100644
--- a/doc/usage/cmd/cli.rst
+++ b/doc/usage/cmd/cli.rst
@@ -6,8 +6,8 @@
cli command
===========
-Synopis
--------
+Synopsis
+--------
::
diff --git a/doc/usage/cmd/dm.rst b/doc/usage/cmd/dm.rst
index 9bef2ee..7651507 100644
--- a/doc/usage/cmd/dm.rst
+++ b/doc/usage/cmd/dm.rst
@@ -6,8 +6,8 @@
dm command
==========
-Synopis
--------
+Synopsis
+--------
::
diff --git a/doc/usage/cmd/env.rst b/doc/usage/cmd/env.rst
index a859e32..a7e2169 100644
--- a/doc/usage/cmd/env.rst
+++ b/doc/usage/cmd/env.rst
@@ -350,7 +350,7 @@
exists
CONFIG_CMD_ENV_EXISTS
-flsgs
+flags
CONFIG_CMD_ENV_FLAGS
erase
diff --git a/doc/usage/cmd/fdt.rst b/doc/usage/cmd/fdt.rst
index 3e8c32c..71a9fc6 100644
--- a/doc/usage/cmd/fdt.rst
+++ b/doc/usage/cmd/fdt.rst
@@ -6,8 +6,8 @@
fdt command
===========
-Synopis
--------
+Synopsis
+--------
::
diff --git a/doc/usage/cmd/font.rst b/doc/usage/cmd/font.rst
index adcd512..a8782546 100644
--- a/doc/usage/cmd/font.rst
+++ b/doc/usage/cmd/font.rst
@@ -6,8 +6,8 @@
font command
============
-Synopis
--------
+Synopsis
+--------
::
diff --git a/doc/usage/cmd/for.rst b/doc/usage/cmd/for.rst
index 4c98419..729bd4d 100644
--- a/doc/usage/cmd/for.rst
+++ b/doc/usage/cmd/for.rst
@@ -4,8 +4,8 @@
for command
===========
-Synopis
--------
+Synopsis
+--------
::
diff --git a/doc/usage/cmd/history.rst b/doc/usage/cmd/history.rst
index 564a159..b52b5b2 100644
--- a/doc/usage/cmd/history.rst
+++ b/doc/usage/cmd/history.rst
@@ -6,8 +6,8 @@
history command
===============
-Synopis
--------
+Synopsis
+--------
::
diff --git a/doc/usage/cmd/host.rst b/doc/usage/cmd/host.rst
index 072497d..a70a432 100644
--- a/doc/usage/cmd/host.rst
+++ b/doc/usage/cmd/host.rst
@@ -6,8 +6,8 @@
host command
============
-Synopis
--------
+Synopsis
+--------
::
diff --git a/doc/usage/cmd/if.rst b/doc/usage/cmd/if.rst
new file mode 100644
index 0000000..813f903
--- /dev/null
+++ b/doc/usage/cmd/if.rst
@@ -0,0 +1,72 @@
+.. SPDX-License-Identifier: GPL-2.0-or-later
+
+.. index::
+ single: if (command)
+
+if command
+==========
+
+Synopsis
+--------
+
+::
+
+ if <test statement>
+ then
+ <statements>
+ fi
+
+ if <test statement>
+ then
+ <statements>
+ else
+ <statements>
+ fi
+
+Description
+-----------
+
+The if command is used to conditionally execute statements.
+
+test statement
+ Any command. The test statement set the $? variable. If the value of
+ $? becomes 0 (true) the statements after the **then** statement will
+ be executed. Otherwise the statements after the **else** statement.
+
+Examples
+--------
+
+The examples shows how the value of a numeric variable can be tested with
+the :doc:`itest <itest>` command.
+
+::
+
+ => a=1; if itest $a == 0; then echo true; else echo false; fi
+ false
+ => a=0; if itest $a == 0; then echo true; else echo false; fi
+ true
+
+In the following example we try to load an EFI binary via TFTP. If loading
+succeeds, the binary is executed.
+
+::
+
+ if tftp $kernel_addr_r shellriscv64.efi; then bootefi $kernel_addr_r; fi
+
+Return value
+------------
+
+The value of $? is the return value of the last executed statement.
+
+::
+
+ => if true; then true; else true; fi; echo $?
+ 0
+ => if false; then true; else true; fi; echo $?
+ 0
+ => if false; then false; else false; fi; echo $?
+ 1
+ => if true; then false; else false; fi; echo $?
+ 1
+ => if false; then true; fi; echo $?
+ 1
diff --git a/doc/usage/cmd/itest.rst b/doc/usage/cmd/itest.rst
new file mode 100644
index 0000000..9c307fb
--- /dev/null
+++ b/doc/usage/cmd/itest.rst
@@ -0,0 +1,115 @@
+.. SPDX-License-Identifier: GPL-2.0+
+
+.. index::
+ single: itest (command)
+
+itest command
+=============
+
+Synopsis
+--------
+
+::
+
+ itest[.b | .w | .l | .q | .s] [*]<value1> <op> [*]<value2>
+
+Description
+-----------
+
+The itest command is used to compare two values. The return value $? is set
+accordingly.
+
+By default it is assumed that the values are 4 byte integers. By appending a
+postfix (.b, .w, .l, .q, .s) the size can be specified:
+
+======= ======================================================
+postfix meaning
+======= ======================================================
+.b 1 byte integer
+.w 2 byte integer
+.l 4 byte integer
+.q 8 byte integer (only available if CONFIG_PHYS_64BIT=y)
+.s string
+======= ======================================================
+
+value1, value2
+ values to compare. Numeric values are hexadecimal. If '*' is prefixed a
+ hexadecimal address is passed, which points to the value to be compared.
+
+op
+ operator, see table
+
+ ======== ======================
+ operator meaning
+ ======== ======================
+ -lt less than
+ < less than
+ -le less or equal
+ <= less or equal
+ -eq equal
+ == equal
+ -ne not equal
+ != not equal
+ <> not equal
+ -ge greater or equal
+ >= greater or equal
+ -gt greater than
+ > greater than
+ ======== ======================
+
+Examples
+========
+
+The itest command sets the result variable $? to true (0) or false (1):
+
+::
+
+ => itest 3 < 4; echo $?
+ 0
+ => itest 3 == 4; echo $?
+ 1
+
+This value can be used in the :doc:`if <if>` command:
+
+::
+
+ => if itest 0x3002 < 0x4001; then echo true; else echo false; fi
+ true
+
+Numbers will be truncated according to the postfix before comparing:
+
+::
+
+ => if itest.b 0x3002 < 0x4001; then echo true; else echo false; fi
+ false
+
+Postfix .s causes a string compare. The string '0xa1234' is alphabetically
+smaller than '0xb'.
+
+::
+
+ => if itest.s 0xa1234 < 0xb; then echo true; else echo false; fi
+ true
+
+A value prefixed by '*' is a pointer to the value in memory.
+
+::
+
+ => mm 0x4000
+ 00004000: 00000004 ?
+ 00004004: 00000003 ? =>
+ => if itest *0x4000 == 4; then echo true; else echo false; fi
+ true
+ => if itest *0x4004 == 3; then echo true; else echo false; fi
+ true
+
+Configuration
+-------------
+
+The command is only available if CONFIG_CMD_ITEST=y.
+
+Return value
+------------
+
+The return value $? is 0 (true) if the condition is true and 1 (false)
+otherwise.
diff --git a/doc/usage/cmd/md.rst b/doc/usage/cmd/md.rst
index 9ea148a..9a9919f 100644
--- a/doc/usage/cmd/md.rst
+++ b/doc/usage/cmd/md.rst
@@ -6,8 +6,8 @@
md command
==========
-Synopis
--------
+Synopsis
+--------
::
diff --git a/doc/usage/cmd/mtrr.rst b/doc/usage/cmd/mtrr.rst
index c656189..3c5c3ba 100644
--- a/doc/usage/cmd/mtrr.rst
+++ b/doc/usage/cmd/mtrr.rst
@@ -6,8 +6,8 @@
mtrr command
============
-Synopis
--------
+Synopsis
+--------
mtrr [list]
mtrr set <reg> <type> <start> <size>
diff --git a/doc/usage/cmd/panic.rst b/doc/usage/cmd/panic.rst
index ba5ea62..39d32ad 100644
--- a/doc/usage/cmd/panic.rst
+++ b/doc/usage/cmd/panic.rst
@@ -6,8 +6,8 @@
panic command
=============
-Synopis
--------
+Synopsis
+--------
::
diff --git a/doc/usage/cmd/part.rst b/doc/usage/cmd/part.rst
index 58be387..e7faecc 100644
--- a/doc/usage/cmd/part.rst
+++ b/doc/usage/cmd/part.rst
@@ -6,8 +6,8 @@
part command
============
-Synopis
--------
+Synopsis
+--------
::
diff --git a/doc/usage/cmd/rng.rst b/doc/usage/cmd/rng.rst
index 274e4d8..4a61e33 100644
--- a/doc/usage/cmd/rng.rst
+++ b/doc/usage/cmd/rng.rst
@@ -11,16 +11,22 @@
::
- rng [devnum [n]]
+ rng list
+ rng [dev] [n]
-Description
------------
+rng list
+--------
+
+List all the probed rng devices.
+
+rng [dev] [n]
+-------------
The *rng* command reads the random number generator(RNG) device and
prints the random bytes read on the console. A maximum of 64 bytes can
be read in one invocation of the command.
-devnum
+dev
The RNG device from which the random bytes are to be
read. Defaults to 0.
diff --git a/doc/usage/cmd/sf.rst b/doc/usage/cmd/sf.rst
index 24d5dc6..dfdca46 100644
--- a/doc/usage/cmd/sf.rst
+++ b/doc/usage/cmd/sf.rst
@@ -6,8 +6,8 @@
sf command
==========
-Synopis
--------
+Synopsis
+--------
::
diff --git a/doc/usage/cmd/sm.rst b/doc/usage/cmd/sm.rst
index b767647..e828fdd 100644
--- a/doc/usage/cmd/sm.rst
+++ b/doc/usage/cmd/sm.rst
@@ -6,8 +6,8 @@
sm command
==========
-Synopis
--------
+Synopsis
+--------
::
diff --git a/doc/usage/cmd/trace.rst b/doc/usage/cmd/trace.rst
index ad6db12..e798b2b 100644
--- a/doc/usage/cmd/trace.rst
+++ b/doc/usage/cmd/trace.rst
@@ -6,8 +6,8 @@
trace command
=============
-Synopis
--------
+Synopsis
+--------
::
diff --git a/doc/usage/cmd/ut.rst b/doc/usage/cmd/ut.rst
index ddc48ec..45bc9ff 100644
--- a/doc/usage/cmd/ut.rst
+++ b/doc/usage/cmd/ut.rst
@@ -6,8 +6,8 @@
ut command
==========
-Synopis
--------
+Synopsis
+--------
::
diff --git a/doc/usage/index.rst b/doc/usage/index.rst
index 0d174ee..2f211f7 100644
--- a/doc/usage/index.rst
+++ b/doc/usage/index.rst
@@ -71,6 +71,8 @@
cmd/gpt
cmd/history
cmd/host
+ cmd/if
+ cmd/itest
cmd/imxtract
cmd/load
cmd/loadb
diff --git a/doc/usage/partitions.rst b/doc/usage/partitions.rst
index 628469b..acf4573 100644
--- a/doc/usage/partitions.rst
+++ b/doc/usage/partitions.rst
@@ -44,9 +44,20 @@
<devtype><devletter><partnum>
devtype
- A device type like ``mmcsd`` or ``hd``. See the
- ``part_set_generic_name`` function in ``disk/part.c`` for a
- complete list.
+ The devtype field is set in dependence of the device class:
+
+ ======= ===============
+ devtype device class
+ ======= ===============
+ hd IDE or SATA
+ sd SCSI
+ usbd USB
+ mmcsd eMMC or SD-card
+ xx others
+ ======= ===============
+
+ See the ``part_set_generic_name`` function in ``disk/part.c``
+ for the complete list.
devletter
The device number as an offset from ``a``. For example, device
diff --git a/drivers/adc/Kconfig b/drivers/adc/Kconfig
index a01d738..c9cdbe6 100644
--- a/drivers/adc/Kconfig
+++ b/drivers/adc/Kconfig
@@ -13,6 +13,7 @@
config ADC_EXYNOS
bool "Enable Exynos 54xx ADC driver"
+ depends on ADC
help
This enables basic driver for Exynos ADC compatible with Exynos54xx.
It provides:
@@ -22,6 +23,7 @@
config ADC_SANDBOX
bool "Enable Sandbox ADC test driver"
+ depends on ADC
help
This enables driver for Sandbox ADC device emulation.
It provides:
@@ -31,6 +33,7 @@
config SARADC_MESON
bool "Enable Amlogic Meson SARADC driver"
+ depends on ADC
imply REGMAP
help
This enables driver for Amlogic Meson SARADC.
@@ -41,6 +44,7 @@
config SARADC_ROCKCHIP
bool "Enable Rockchip SARADC driver"
+ depends on ADC
help
This enables driver for Rockchip SARADC.
It provides:
diff --git a/drivers/adc/rockchip-saradc.c b/drivers/adc/rockchip-saradc.c
index 03caca7..10ded1b 100644
--- a/drivers/adc/rockchip-saradc.c
+++ b/drivers/adc/rockchip-saradc.c
@@ -10,12 +10,17 @@
#include <clk.h>
#include <dm.h>
#include <errno.h>
-#include <asm/io.h>
+#include <reset.h>
+#include <asm/arch-rockchip/hardware.h>
+#include <linux/bitfield.h>
#include <linux/bitops.h>
+#include <linux/delay.h>
#include <linux/err.h>
#include <linux/printk.h>
#include <power/regulator.h>
+#define usleep_range(a, b) udelay((b))
+
#define SARADC_CTRL_CHN_MASK GENMASK(2, 0)
#define SARADC_CTRL_POWER_CTRL BIT(3)
#define SARADC_CTRL_IRQ_ENABLE BIT(5)
@@ -23,77 +28,210 @@
#define SARADC_TIMEOUT (100 * 1000)
-struct rockchip_saradc_regs {
+struct rockchip_saradc_regs_v1 {
unsigned int data;
unsigned int stas;
unsigned int ctrl;
unsigned int dly_pu_soc;
};
+struct rockchip_saradc_regs_v2 {
+ unsigned int conv_con;
+#define SARADC2_SINGLE_MODE BIT(5)
+#define SARADC2_START BIT(4)
+#define SARADC2_CONV_CHANNELS GENMASK(3, 0)
+ unsigned int t_pd_soc;
+ unsigned int t_as_soc;
+ unsigned int t_das_soc;
+ unsigned int t_sel_soc;
+ unsigned int high_comp[16];
+ unsigned int low_comp[16];
+ unsigned int debounce;
+ unsigned int ht_int_en;
+ unsigned int lt_int_en;
+ unsigned int reserved[24];
+ unsigned int mt_int_en;
+ unsigned int end_int_en;
+#define SARADC2_EN_END_INT BIT(0)
+ unsigned int st_con;
+ unsigned int status;
+ unsigned int end_int_st;
+ unsigned int ht_int_st;
+ unsigned int lt_int_st;
+ unsigned int mt_int_st;
+ unsigned int data[16];
+ unsigned int auto_ch_en;
+};
+
+union rockchip_saradc_regs {
+ struct rockchip_saradc_regs_v1 *v1;
+ struct rockchip_saradc_regs_v2 *v2;
+};
struct rockchip_saradc_data {
int num_bits;
int num_channels;
unsigned long clk_rate;
+ int (*channel_data)(struct udevice *dev, int channel, unsigned int *data);
+ int (*start_channel)(struct udevice *dev, int channel);
+ int (*stop)(struct udevice *dev);
};
struct rockchip_saradc_priv {
- struct rockchip_saradc_regs *regs;
+ union rockchip_saradc_regs regs;
int active_channel;
const struct rockchip_saradc_data *data;
+ struct reset_ctl *reset;
};
+int rockchip_saradc_channel_data_v1(struct udevice *dev, int channel,
+ unsigned int *data)
+{
+ struct rockchip_saradc_priv *priv = dev_get_priv(dev);
+
+ if ((readl(&priv->regs.v1->ctrl) & SARADC_CTRL_IRQ_STATUS) !=
+ SARADC_CTRL_IRQ_STATUS)
+ return -EBUSY;
+
+ /* Read value */
+ *data = readl(&priv->regs.v1->data);
+
+ /* Power down adc */
+ writel(0, &priv->regs.v1->ctrl);
+
+ return 0;
+}
+
+int rockchip_saradc_channel_data_v2(struct udevice *dev, int channel,
+ unsigned int *data)
+{
+ struct rockchip_saradc_priv *priv = dev_get_priv(dev);
+
+ if (!(readl(&priv->regs.v2->end_int_st) & SARADC2_EN_END_INT))
+ return -EBUSY;
+
+ /* Read value */
+ *data = readl(&priv->regs.v2->data[channel]);
+
+ /* Acknowledge the interrupt */
+ writel(SARADC2_EN_END_INT, &priv->regs.v2->end_int_st);
+
+ return 0;
+}
int rockchip_saradc_channel_data(struct udevice *dev, int channel,
unsigned int *data)
{
struct rockchip_saradc_priv *priv = dev_get_priv(dev);
struct adc_uclass_plat *uc_pdata = dev_get_uclass_plat(dev);
+ int ret;
if (channel != priv->active_channel) {
pr_err("Requested channel is not active!");
return -EINVAL;
}
- if ((readl(&priv->regs->ctrl) & SARADC_CTRL_IRQ_STATUS) !=
- SARADC_CTRL_IRQ_STATUS)
- return -EBUSY;
+ ret = priv->data->channel_data(dev, channel, data);
+ if (ret) {
+ if (ret != -EBUSY)
+ pr_err("Error reading channel data, %d!", ret);
+ return ret;
+ }
- /* Read value */
- *data = readl(&priv->regs->data);
*data &= uc_pdata->data_mask;
- /* Power down adc */
- writel(0, &priv->regs->ctrl);
+ return 0;
+}
+
+int rockchip_saradc_start_channel_v1(struct udevice *dev, int channel)
+{
+ struct rockchip_saradc_priv *priv = dev_get_priv(dev);
+
+ /* 8 clock periods as delay between power up and start cmd */
+ writel(8, &priv->regs.v1->dly_pu_soc);
+
+ /* Select the channel to be used and trigger conversion */
+ writel(SARADC_CTRL_POWER_CTRL | (channel & SARADC_CTRL_CHN_MASK) |
+ SARADC_CTRL_IRQ_ENABLE, &priv->regs.v1->ctrl);
return 0;
}
+static void rockchip_saradc_reset_controller(struct reset_ctl *reset)
+{
+ reset_assert(reset);
+ usleep_range(10, 20);
+ reset_deassert(reset);
+}
+
+int rockchip_saradc_start_channel_v2(struct udevice *dev, int channel)
+{
+ struct rockchip_saradc_priv *priv = dev_get_priv(dev);
+
+ /*
+ * Downstream says
+ * """If read other chn at anytime, then chn1 will error, assert
+ * controller as a workaround."""
+ */
+ if (priv->reset)
+ rockchip_saradc_reset_controller(priv->reset);
+
+ writel(0xc, &priv->regs.v2->t_das_soc);
+ writel(0x20, &priv->regs.v2->t_pd_soc);
+
+ /* Acknowledge any previous interrupt */
+ writel(SARADC2_EN_END_INT, &priv->regs.v2->end_int_st);
+
+ rk_clrsetreg(&priv->regs.v2->conv_con,
+ SARADC2_CONV_CHANNELS | SARADC2_START | SARADC2_SINGLE_MODE,
+ FIELD_PREP(SARADC2_CONV_CHANNELS, channel) |
+ FIELD_PREP(SARADC2_START, 1) |
+ FIELD_PREP(SARADC2_SINGLE_MODE, 1));
+
+ return 0;
+}
+
int rockchip_saradc_start_channel(struct udevice *dev, int channel)
{
struct rockchip_saradc_priv *priv = dev_get_priv(dev);
+ int ret;
if (channel < 0 || channel >= priv->data->num_channels) {
pr_err("Requested channel is invalid!");
return -EINVAL;
}
- /* 8 clock periods as delay between power up and start cmd */
- writel(8, &priv->regs->dly_pu_soc);
-
- /* Select the channel to be used and trigger conversion */
- writel(SARADC_CTRL_POWER_CTRL | (channel & SARADC_CTRL_CHN_MASK) |
- SARADC_CTRL_IRQ_ENABLE, &priv->regs->ctrl);
+ ret = priv->data->start_channel(dev, channel);
+ if (ret) {
+ pr_err("Error starting channel, %d!", ret);
+ return ret;
+ }
priv->active_channel = channel;
return 0;
}
-int rockchip_saradc_stop(struct udevice *dev)
+int rockchip_saradc_stop_v1(struct udevice *dev)
{
struct rockchip_saradc_priv *priv = dev_get_priv(dev);
/* Power down adc */
- writel(0, &priv->regs->ctrl);
+ writel(0, &priv->regs.v1->ctrl);
+
+ return 0;
+}
+
+int rockchip_saradc_stop(struct udevice *dev)
+{
+ struct rockchip_saradc_priv *priv = dev_get_priv(dev);
+
+ if (priv->data->stop) {
+ int ret = priv->data->stop(dev);
+
+ if (ret) {
+ pr_err("Error stopping channel, %d!", ret);
+ return ret;
+ }
+ }
priv->active_channel = -1;
@@ -109,6 +247,8 @@
int vref_uv;
int ret;
+ priv->reset = devm_reset_control_get_optional(dev, "saradc-apb");
+
ret = clk_get_by_index(dev, 0, &clk);
if (ret)
return ret;
@@ -125,6 +265,9 @@
return ret;
}
+ if (priv->reset)
+ rockchip_saradc_reset_controller(priv->reset);
+
vref_uv = regulator_get_value(vref);
if (vref_uv < 0) {
printf("can't get vref-supply value: %d\n", vref_uv);
@@ -146,8 +289,8 @@
struct rockchip_saradc_data *data;
data = (struct rockchip_saradc_data *)dev_get_driver_data(dev);
- priv->regs = dev_read_addr_ptr(dev);
- if (!priv->regs) {
+ priv->regs.v1 = dev_read_addr_ptr(dev);
+ if (!priv->regs.v1) {
pr_err("Dev: %s - can't get address!", dev->name);
return -EINVAL;
}
@@ -171,18 +314,35 @@
.num_bits = 10,
.num_channels = 3,
.clk_rate = 1000000,
+ .channel_data = rockchip_saradc_channel_data_v1,
+ .start_channel = rockchip_saradc_start_channel_v1,
+ .stop = rockchip_saradc_stop_v1,
};
static const struct rockchip_saradc_data rk3066_tsadc_data = {
.num_bits = 12,
.num_channels = 2,
.clk_rate = 50000,
+ .channel_data = rockchip_saradc_channel_data_v1,
+ .start_channel = rockchip_saradc_start_channel_v1,
+ .stop = rockchip_saradc_stop_v1,
};
static const struct rockchip_saradc_data rk3399_saradc_data = {
.num_bits = 10,
.num_channels = 6,
.clk_rate = 1000000,
+ .channel_data = rockchip_saradc_channel_data_v1,
+ .start_channel = rockchip_saradc_start_channel_v1,
+ .stop = rockchip_saradc_stop_v1,
+};
+
+static const struct rockchip_saradc_data rk3588_saradc_data = {
+ .num_bits = 12,
+ .num_channels = 8,
+ .clk_rate = 1000000,
+ .channel_data = rockchip_saradc_channel_data_v2,
+ .start_channel = rockchip_saradc_start_channel_v2,
};
static const struct udevice_id rockchip_saradc_ids[] = {
@@ -192,6 +352,8 @@
.data = (ulong)&rk3066_tsadc_data },
{ .compatible = "rockchip,rk3399-saradc",
.data = (ulong)&rk3399_saradc_data },
+ { .compatible = "rockchip,rk3588-saradc",
+ .data = (ulong)&rk3588_saradc_data },
{ }
};
diff --git a/drivers/button/Kconfig b/drivers/button/Kconfig
index 097b05f..3918b05 100644
--- a/drivers/button/Kconfig
+++ b/drivers/button/Kconfig
@@ -12,6 +12,7 @@
config BUTTON_ADC
bool "Button adc"
depends on BUTTON
+ depends on ADC
help
Enable support for buttons which are connected to Analog to Digital
Converter device. The ADC driver must use driver model. Buttons are
diff --git a/drivers/clk/altera/Makefile b/drivers/clk/altera/Makefile
index 33db092..61ffa41 100644
--- a/drivers/clk/altera/Makefile
+++ b/drivers/clk/altera/Makefile
@@ -7,3 +7,4 @@
obj-$(CONFIG_TARGET_SOCFPGA_ARRIA10) += clk-arria10.o
obj-$(CONFIG_TARGET_SOCFPGA_N5X) += clk-n5x.o
obj-$(CONFIG_TARGET_SOCFPGA_N5X) += clk-mem-n5x.o
+obj-$(CONFIG_TARGET_SOCFPGA_AGILEX5) += clk-agilex5.o
diff --git a/drivers/clk/altera/clk-agilex5.c b/drivers/clk/altera/clk-agilex5.c
new file mode 100644
index 0000000..92f2abd
--- /dev/null
+++ b/drivers/clk/altera/clk-agilex5.c
@@ -0,0 +1,745 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (C) 2024 Intel Corporation <www.intel.com>
+ */
+
+#include <clk-uclass.h>
+#include <config.h>
+#include <errno.h>
+#include <dm.h>
+#include <log.h>
+#include <stdarg.h>
+#include <stdio.h>
+#include <time.h>
+#include <vsprintf.h>
+#include <asm/global_data.h>
+#include <asm/io.h>
+#include <asm/system.h>
+#include <asm/u-boot.h>
+#include <dm/lists.h>
+#include <dm/util.h>
+#include <linux/bitops.h>
+#include <linux/kernel.h>
+#include <linux/string.h>
+#include <linux/types.h>
+#include <asm/arch/clock_manager.h>
+#include <dt-bindings/clock/agilex5-clock.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+struct socfpga_clk_plat {
+ void __iomem *regs;
+};
+
+/*
+ * function to write the bypass register which requires a poll of the
+ * busy bit
+ */
+static void clk_write_bypass_mainpll(struct socfpga_clk_plat *plat, u32 val)
+{
+ CM_REG_WRITEL(plat, val, CLKMGR_MAINPLL_BYPASS);
+ cm_wait_for_fsm();
+}
+
+static void clk_write_bypass_perpll(struct socfpga_clk_plat *plat, u32 val)
+{
+ CM_REG_WRITEL(plat, val, CLKMGR_PERPLL_BYPASS);
+ cm_wait_for_fsm();
+}
+
+/* function to write the ctrl register which requires a poll of the busy bit */
+static void clk_write_ctrl(struct socfpga_clk_plat *plat, u32 val)
+{
+ CM_REG_WRITEL(plat, val, CLKMGR_CTRL);
+ cm_wait_for_fsm();
+}
+
+static const struct {
+ u32 reg;
+ u32 val;
+ u32 mask;
+} membus_pll[] = {
+ {
+ MEMBUS_CLKSLICE_REG,
+ /*
+ * BIT[7:7]
+ * Enable source synchronous mode
+ */
+ BIT(7),
+ BIT(7)
+ },
+ {
+ MEMBUS_SYNTHCALFOSC_INIT_CENTERFREQ_REG,
+ /*
+ * BIT[0:0]
+ * Sets synthcalfosc_init_centerfreq=1 to limit overshoot
+ * frequency during lock
+ */
+ BIT(0),
+ BIT(0)
+ },
+ {
+ MEMBUS_SYNTHPPM_WATCHDOGTMR_VF01_REG,
+ /*
+ * BIT[0:0]
+ * Sets synthppm_watchdogtmr_vf0=1 to give the pll more time
+ * to settle before lock is asserted.
+ */
+ BIT(0),
+ BIT(0)
+ },
+ {
+ MEMBUS_CALCLKSLICE0_DUTY_LOCOVR_REG,
+ /*
+ * BIT[6:0]
+ * Centering duty cycle for clkslice0 output
+ */
+ 0x4a,
+ GENMASK(6, 0)
+ },
+ {
+ MEMBUS_CALCLKSLICE1_DUTY_LOCOVR_REG,
+ /*
+ * BIT[6:0]
+ * Centering duty cycle for clkslice1 output
+ */
+ 0x4a,
+ GENMASK(6, 0)
+ },
+};
+
+static int membus_wait_for_req(struct socfpga_clk_plat *plat, u32 pll,
+ int timeout)
+{
+ int cnt = 0;
+ u32 req_status;
+
+ if (pll == MEMBUS_MAINPLL)
+ req_status = CM_REG_READL(plat, CLKMGR_MAINPLL_MEM);
+ else
+ req_status = CM_REG_READL(plat, CLKMGR_PERPLL_MEM);
+
+ while ((cnt < timeout) && (req_status & CLKMGR_MEM_REQ_SET_MSK)) {
+ if (pll == MEMBUS_MAINPLL)
+ req_status = CM_REG_READL(plat, CLKMGR_MAINPLL_MEM);
+ else
+ req_status = CM_REG_READL(plat, CLKMGR_PERPLL_MEM);
+ cnt++;
+ }
+
+ if (cnt >= timeout)
+ return -ETIMEDOUT;
+
+ return 0;
+}
+
+static int membus_write_pll(struct socfpga_clk_plat *plat, u32 pll,
+ u32 addr_offset, u32 wdat, int timeout)
+{
+ u32 addr;
+ u32 val;
+
+ addr = ((addr_offset | CLKMGR_MEM_ADDR_START) & CLKMGR_MEM_ADDR_MASK);
+
+ val = (CLKMGR_MEM_REQ_SET_MSK | CLKMGR_MEM_WR_SET_MSK |
+ (wdat << CLKMGR_MEM_WDAT_LSB_OFFSET) | addr);
+
+ if (pll == MEMBUS_MAINPLL)
+ CM_REG_WRITEL(plat, val, CLKMGR_MAINPLL_MEM);
+ else
+ CM_REG_WRITEL(plat, val, CLKMGR_PERPLL_MEM);
+
+ debug("MEMBUS: Write 0x%08x to addr = 0x%08x\n", wdat, addr);
+
+ return membus_wait_for_req(plat, pll, timeout);
+}
+
+static int membus_read_pll(struct socfpga_clk_plat *plat, u32 pll,
+ u32 addr_offset, u32 *rdata, int timeout)
+{
+ u32 addr;
+ u32 val;
+
+ addr = ((addr_offset | CLKMGR_MEM_ADDR_START) & CLKMGR_MEM_ADDR_MASK);
+
+ val = ((CLKMGR_MEM_REQ_SET_MSK & ~CLKMGR_MEM_WR_SET_MSK) | addr);
+
+ if (pll == MEMBUS_MAINPLL)
+ CM_REG_WRITEL(plat, val, CLKMGR_MAINPLL_MEM);
+ else
+ CM_REG_WRITEL(plat, val, CLKMGR_PERPLL_MEM);
+
+ *rdata = 0;
+
+ if (membus_wait_for_req(plat, pll, timeout))
+ return -ETIMEDOUT;
+
+ if (pll == MEMBUS_MAINPLL)
+ *rdata = CM_REG_READL(plat, CLKMGR_MAINPLL_MEMSTAT);
+ else
+ *rdata = CM_REG_READL(plat, CLKMGR_PERPLL_MEMSTAT);
+
+ debug("MEMBUS: Read 0x%08x from addr = 0x%08x\n", *rdata, addr);
+
+ return 0;
+}
+
+static void membus_pll_configs(struct socfpga_clk_plat *plat, u32 pll)
+{
+ int i;
+ u32 rdata;
+
+ for (i = 0; i < ARRAY_SIZE(membus_pll); i++) {
+ membus_read_pll(plat, pll, membus_pll[i].reg,
+ &rdata, MEMBUS_TIMEOUT);
+ membus_write_pll(plat, pll, membus_pll[i].reg,
+ ((rdata & ~membus_pll[i].mask) |
+ membus_pll[i].val),
+ MEMBUS_TIMEOUT);
+ }
+}
+
+static u32 calc_vocalib_pll(u32 pllm, u32 pllglob)
+{
+ u32 mdiv, refclkdiv, arefclkdiv, drefclkdiv, mscnt, hscnt, vcocalib;
+
+ mdiv = pllm & CLKMGR_PLLM_MDIV_MASK;
+ arefclkdiv = (pllglob & CLKMGR_PLLGLOB_AREFCLKDIV_MASK) >>
+ CLKMGR_PLLGLOB_AREFCLKDIV_OFFSET;
+ drefclkdiv = (pllglob & CLKMGR_PLLGLOB_DREFCLKDIV_MASK) >>
+ CLKMGR_PLLGLOB_DREFCLKDIV_OFFSET;
+ refclkdiv = (pllglob & CLKMGR_PLLGLOB_REFCLKDIV_MASK) >>
+ CLKMGR_PLLGLOB_REFCLKDIV_OFFSET;
+ mscnt = CLKMGR_VCOCALIB_MSCNT_CONST / (mdiv * BIT(drefclkdiv));
+ if (!mscnt)
+ mscnt = 1;
+ hscnt = (mdiv * mscnt * BIT(drefclkdiv) / refclkdiv) -
+ CLKMGR_VCOCALIB_HSCNT_CONST;
+ vcocalib = (hscnt & CLKMGR_VCOCALIB_HSCNT_MASK) |
+ ((mscnt << CLKMGR_VCOCALIB_MSCNT_OFFSET) &
+ CLKMGR_VCOCALIB_MSCNT_MASK);
+
+ /* Dump all the pll calibration settings for debug purposes */
+ debug("mdiv : %d\n", mdiv);
+ debug("arefclkdiv : %d\n", arefclkdiv);
+ debug("drefclkdiv : %d\n", drefclkdiv);
+ debug("refclkdiv : %d\n", refclkdiv);
+ debug("mscnt : %d\n", mscnt);
+ debug("hscnt : %d\n", hscnt);
+ debug("vcocalib : 0x%08x\n", vcocalib);
+
+ return vcocalib;
+}
+
+/*
+ * Setup clocks while making no assumptions about previous state of the clocks.
+ */
+static void clk_basic_init(struct udevice *dev,
+ const struct cm_config * const cfg)
+{
+ struct socfpga_clk_plat *plat = dev_get_plat(dev);
+ u32 vcocalib;
+
+ if (!cfg)
+ return;
+
+ if (IS_ENABLED(CONFIG_TARGET_SOCFPGA_AGILEX5_EMU)) {
+ /* Take both PLL out of reset and power up */
+ CM_REG_SETBITS(plat, CLKMGR_MAINPLL_PLLGLOB,
+ CLKMGR_PLLGLOB_PD_MASK | CLKMGR_PLLGLOB_RST_MASK);
+ CM_REG_SETBITS(plat, CLKMGR_PERPLL_PLLGLOB,
+ CLKMGR_PLLGLOB_PD_MASK | CLKMGR_PLLGLOB_RST_MASK);
+
+ cm_wait_for_lock(CLKMGR_STAT_ALLPLL_LOCKED_MASK);
+
+ /* Put both PLLs in bypass */
+ clk_write_bypass_mainpll(plat, CLKMGR_BYPASS_MAINPLL_ALL);
+ clk_write_bypass_perpll(plat, CLKMGR_BYPASS_PERPLL_ALL);
+
+ /* Take all PLLs out of bypass */
+ clk_write_bypass_mainpll(plat, 0);
+ clk_write_bypass_perpll(plat, 0);
+
+ /* Out of boot mode */
+ clk_write_ctrl(plat,
+ CM_REG_READL(plat, CLKMGR_CTRL) & ~CLKMGR_CTRL_BOOTMODE);
+ } else {
+#ifdef CONFIG_SPL_BUILD
+ /* Always force clock manager into boot mode before any configuration */
+ clk_write_ctrl(plat,
+ CM_REG_READL(plat, CLKMGR_CTRL) | CLKMGR_CTRL_BOOTMODE);
+#else
+ /* Skip clock configuration in SSBL if it's not in boot mode */
+ if (!(CM_REG_READL(plat, CLKMGR_CTRL) & CLKMGR_CTRL_BOOTMODE))
+ return;
+#endif
+
+ /* Put both PLLs in bypass */
+ clk_write_bypass_mainpll(plat, CLKMGR_BYPASS_MAINPLL_ALL);
+ clk_write_bypass_perpll(plat, CLKMGR_BYPASS_PERPLL_ALL);
+
+ /* Put both PLLs in Reset and Power Down */
+ CM_REG_CLRBITS(plat, CLKMGR_MAINPLL_PLLGLOB,
+ CLKMGR_PLLGLOB_PD_MASK | CLKMGR_PLLGLOB_RST_MASK);
+ CM_REG_CLRBITS(plat, CLKMGR_PERPLL_PLLGLOB,
+ CLKMGR_PLLGLOB_PD_MASK | CLKMGR_PLLGLOB_RST_MASK);
+
+ /* setup main PLL dividers where calculate the vcocalib value */
+ vcocalib = calc_vocalib_pll(cfg->main_pll_pllm, cfg->main_pll_pllglob);
+ CM_REG_WRITEL(plat, cfg->main_pll_pllglob & ~CLKMGR_PLLGLOB_RST_MASK,
+ CLKMGR_MAINPLL_PLLGLOB);
+ CM_REG_WRITEL(plat, cfg->main_pll_fdbck, CLKMGR_MAINPLL_FDBCK);
+ CM_REG_WRITEL(plat, vcocalib, CLKMGR_MAINPLL_VCOCALIB);
+ CM_REG_WRITEL(plat, cfg->main_pll_pllc0, CLKMGR_MAINPLL_PLLC0);
+ CM_REG_WRITEL(plat, cfg->main_pll_pllc1, CLKMGR_MAINPLL_PLLC1);
+ CM_REG_WRITEL(plat, cfg->main_pll_pllc2, CLKMGR_MAINPLL_PLLC2);
+ CM_REG_WRITEL(plat, cfg->main_pll_pllc3, CLKMGR_MAINPLL_PLLC3);
+ CM_REG_WRITEL(plat, cfg->main_pll_pllm, CLKMGR_MAINPLL_PLLM);
+ CM_REG_WRITEL(plat, cfg->main_pll_nocclk, CLKMGR_MAINPLL_NOCCLK);
+ CM_REG_WRITEL(plat, cfg->main_pll_nocdiv, CLKMGR_MAINPLL_NOCDIV);
+
+ /* setup peripheral PLL dividers where calculate the vcocalib value */
+ vcocalib = calc_vocalib_pll(cfg->per_pll_pllm, cfg->per_pll_pllglob);
+ CM_REG_WRITEL(plat, cfg->per_pll_pllglob & ~CLKMGR_PLLGLOB_RST_MASK,
+ CLKMGR_PERPLL_PLLGLOB);
+ CM_REG_WRITEL(plat, cfg->per_pll_fdbck, CLKMGR_PERPLL_FDBCK);
+ CM_REG_WRITEL(plat, vcocalib, CLKMGR_PERPLL_VCOCALIB);
+ CM_REG_WRITEL(plat, cfg->per_pll_pllc0, CLKMGR_PERPLL_PLLC0);
+ CM_REG_WRITEL(plat, cfg->per_pll_pllc1, CLKMGR_PERPLL_PLLC1);
+ CM_REG_WRITEL(plat, cfg->per_pll_pllc2, CLKMGR_PERPLL_PLLC2);
+ CM_REG_WRITEL(plat, cfg->per_pll_pllc3, CLKMGR_PERPLL_PLLC3);
+ CM_REG_WRITEL(plat, cfg->per_pll_pllm, CLKMGR_PERPLL_PLLM);
+ CM_REG_WRITEL(plat, cfg->per_pll_emacctl, CLKMGR_PERPLL_EMACCTL);
+ CM_REG_WRITEL(plat, cfg->per_pll_gpiodiv, CLKMGR_PERPLL_GPIODIV);
+
+ /* Configure ping pong counters in control group */
+ CM_REG_WRITEL(plat, cfg->ctl_emacactr, CLKMGR_CTL_EMACACTR);
+ CM_REG_WRITEL(plat, cfg->ctl_emacbctr, CLKMGR_CTL_EMACBCTR);
+ CM_REG_WRITEL(plat, cfg->ctl_emacptpctr, CLKMGR_CTL_EMACPTPCTR);
+ CM_REG_WRITEL(plat, cfg->ctl_gpiodbctr, CLKMGR_CTL_GPIODBCTR);
+ CM_REG_WRITEL(plat, cfg->ctl_s2fuser0ctr, CLKMGR_CTL_S2FUSER0CTR);
+ CM_REG_WRITEL(plat, cfg->ctl_s2fuser1ctr, CLKMGR_CTL_S2FUSER1CTR);
+ CM_REG_WRITEL(plat, cfg->ctl_psirefctr, CLKMGR_CTL_PSIREFCTR);
+ CM_REG_WRITEL(plat, cfg->ctl_usb31ctr, CLKMGR_CTL_USB31CTR);
+ CM_REG_WRITEL(plat, cfg->ctl_dsuctr, CLKMGR_CTL_DSUCTR);
+ CM_REG_WRITEL(plat, cfg->ctl_core01ctr, CLKMGR_CTL_CORE01CTR);
+ CM_REG_WRITEL(plat, cfg->ctl_core23ctr, CLKMGR_CTL_CORE23CTR);
+ CM_REG_WRITEL(plat, cfg->ctl_core2ctr, CLKMGR_CTL_CORE2CTR);
+ CM_REG_WRITEL(plat, cfg->ctl_core3ctr, CLKMGR_CTL_CORE3CTR);
+
+ /* Take both PLL out of reset and power up */
+ CM_REG_SETBITS(plat, CLKMGR_MAINPLL_PLLGLOB,
+ CLKMGR_PLLGLOB_PD_MASK | CLKMGR_PLLGLOB_RST_MASK);
+ CM_REG_SETBITS(plat, CLKMGR_PERPLL_PLLGLOB,
+ CLKMGR_PLLGLOB_PD_MASK | CLKMGR_PLLGLOB_RST_MASK);
+
+ /* Membus programming for mainpll */
+ membus_pll_configs(plat, MEMBUS_MAINPLL);
+ /* Membus programming for peripll */
+ membus_pll_configs(plat, MEMBUS_PERPLL);
+
+ /* Enable Main pll clkslices */
+ CM_REG_WRITEL(plat, CM_REG_READL(plat, CLKMGR_MAINPLL_PLLC0) |
+ CLKMGR_PLLCX_EN_SET_MSK,
+ CLKMGR_MAINPLL_PLLC0);
+ CM_REG_WRITEL(plat, CM_REG_READL(plat, CLKMGR_MAINPLL_PLLC1) |
+ CLKMGR_PLLCX_EN_SET_MSK,
+ CLKMGR_MAINPLL_PLLC1);
+ CM_REG_WRITEL(plat, CM_REG_READL(plat, CLKMGR_MAINPLL_PLLC2) |
+ CLKMGR_PLLCX_EN_SET_MSK,
+ CLKMGR_MAINPLL_PLLC2);
+ CM_REG_WRITEL(plat, CM_REG_READL(plat, CLKMGR_MAINPLL_PLLC3) |
+ CLKMGR_PLLCX_EN_SET_MSK,
+ CLKMGR_MAINPLL_PLLC3);
+
+ /* Enable Periph pll clkslices */
+ CM_REG_WRITEL(plat, CM_REG_READL(plat, CLKMGR_PERPLL_PLLC0) |
+ CLKMGR_PLLCX_EN_SET_MSK,
+ CLKMGR_PERPLL_PLLC0);
+ CM_REG_WRITEL(plat, CM_REG_READL(plat, CLKMGR_PERPLL_PLLC1) |
+ CLKMGR_PLLCX_EN_SET_MSK,
+ CLKMGR_PERPLL_PLLC1);
+ CM_REG_WRITEL(plat, CM_REG_READL(plat, CLKMGR_PERPLL_PLLC2) |
+ CLKMGR_PLLCX_EN_SET_MSK,
+ CLKMGR_PERPLL_PLLC2);
+ CM_REG_WRITEL(plat, CM_REG_READL(plat, CLKMGR_PERPLL_PLLC3) |
+ CLKMGR_PLLCX_EN_SET_MSK,
+ CLKMGR_PERPLL_PLLC3);
+
+ cm_wait_for_lock(CLKMGR_STAT_ALLPLL_LOCKED_MASK);
+
+ CM_REG_WRITEL(plat, CLKMGR_LOSTLOCK_SET_MASK, CLKMGR_MAINPLL_LOSTLOCK);
+ CM_REG_WRITEL(plat, CLKMGR_LOSTLOCK_SET_MASK, CLKMGR_PERPLL_LOSTLOCK);
+
+ CM_REG_WRITEL(plat, CM_REG_READL(plat, CLKMGR_MAINPLL_PLLGLOB) |
+ CLKMGR_PLLGLOB_CLR_LOSTLOCK_BYPASS_MASK,
+ CLKMGR_MAINPLL_PLLGLOB);
+ CM_REG_WRITEL(plat, CM_REG_READL(plat, CLKMGR_PERPLL_PLLGLOB) |
+ CLKMGR_PLLGLOB_CLR_LOSTLOCK_BYPASS_MASK,
+ CLKMGR_PERPLL_PLLGLOB);
+
+ /* Take all PLLs out of bypass */
+ clk_write_bypass_mainpll(plat, 0);
+ clk_write_bypass_perpll(plat, 0);
+
+ /* Clear the loss of lock bits (write 1 to clear) */
+ CM_REG_CLRBITS(plat, CLKMGR_INTRCLR,
+ CLKMGR_INTER_PERPLLLOST_MASK |
+ CLKMGR_INTER_MAINPLLLOST_MASK);
+
+ /* Take all ping pong counters out of reset */
+ CM_REG_CLRBITS(plat, CLKMGR_CTL_EXTCNTRST,
+ CLKMGR_CTL_EXTCNTRST_ALLCNTRST);
+
+#ifdef COUNTER_FREQUENCY_REAL
+ u32 cntfrq = COUNTER_FREQUENCY_REAL;
+ u32 counter_freq = 0;
+
+ /* Update with accurate clock frequency */
+ if (current_el() == 3) {
+ asm volatile("msr cntfrq_el0, %0" : : "r" (cntfrq) : "memory");
+ asm volatile("mrs %0, cntfrq_el0" : "=r" (counter_freq));
+ debug("Counter freq = 0x%x\n", counter_freq);
+ }
+#endif
+
+ /* Out of boot mode */
+ clk_write_ctrl(plat,
+ CM_REG_READL(plat, CLKMGR_CTRL) & ~CLKMGR_CTRL_BOOTMODE);
+ }
+}
+
+static u64 clk_get_vco_clk_hz(struct socfpga_clk_plat *plat,
+ u32 pllglob_reg, u32 pllm_reg)
+{
+ u64 fref, arefdiv, mdiv, reg, vco;
+
+ reg = CM_REG_READL(plat, pllglob_reg);
+
+ fref = (reg & CLKMGR_PLLGLOB_VCO_PSRC_MASK) >>
+ CLKMGR_PLLGLOB_VCO_PSRC_OFFSET;
+
+ switch (fref) {
+ case CLKMGR_VCO_PSRC_EOSC1:
+ fref = cm_get_osc_clk_hz();
+ break;
+ case CLKMGR_VCO_PSRC_INTOSC:
+ fref = cm_get_intosc_clk_hz();
+ break;
+ case CLKMGR_VCO_PSRC_F2S:
+ fref = cm_get_fpga_clk_hz();
+ break;
+ }
+
+ arefdiv = (reg & CLKMGR_PLLGLOB_AREFCLKDIV_MASK) >>
+ CLKMGR_PLLGLOB_AREFCLKDIV_OFFSET;
+
+ mdiv = CM_REG_READL(plat, pllm_reg) & CLKMGR_PLLM_MDIV_MASK;
+
+ vco = fref / arefdiv;
+ vco = vco * mdiv;
+
+ return vco;
+}
+
+static u64 clk_get_main_vco_clk_hz(struct socfpga_clk_plat *plat)
+{
+ return clk_get_vco_clk_hz(plat, CLKMGR_MAINPLL_PLLGLOB,
+ CLKMGR_MAINPLL_PLLM);
+}
+
+static u64 clk_get_per_vco_clk_hz(struct socfpga_clk_plat *plat)
+{
+ return clk_get_vco_clk_hz(plat, CLKMGR_PERPLL_PLLGLOB,
+ CLKMGR_PERPLL_PLLM);
+}
+
+static u32 clk_get_5_1_clk_src(struct socfpga_clk_plat *plat, u64 reg)
+{
+ u32 clksrc = CM_REG_READL(plat, reg);
+
+ return (clksrc & CLKMGR_CLKSRC_MASK) >> CLKMGR_CLKSRC_OFFSET;
+}
+
+static u64 clk_get_clksrc_hz(struct socfpga_clk_plat *plat, u32 clksrc_reg,
+ u32 main_reg, u32 per_reg)
+{
+ u64 clock;
+ u32 clklsrc = clk_get_5_1_clk_src(plat, clksrc_reg);
+
+ switch (clklsrc) {
+ case CLKMGR_CLKSRC_MAIN:
+ clock = clk_get_main_vco_clk_hz(plat);
+ clock /= (CM_REG_READL(plat, main_reg) &
+ CLKMGR_CLKCNT_MSK);
+ break;
+
+ case CLKMGR_CLKSRC_PER:
+ clock = clk_get_per_vco_clk_hz(plat);
+ clock /= (CM_REG_READL(plat, per_reg) &
+ CLKMGR_CLKCNT_MSK);
+ break;
+
+ case CLKMGR_CLKSRC_OSC1:
+ clock = cm_get_osc_clk_hz();
+ break;
+
+ case CLKMGR_CLKSRC_INTOSC:
+ clock = cm_get_intosc_clk_hz();
+ break;
+
+ case CLKMGR_CLKSRC_FPGA:
+ clock = cm_get_fpga_clk_hz();
+ break;
+ default:
+ return 0;
+ }
+
+ return clock;
+}
+
+static u64 clk_get_mpu_clk_hz(struct socfpga_clk_plat *plat)
+{
+ u64 clock;
+ u32 ctr_reg;
+ u32 cpu = ((read_mpidr() >> MPIDR_AFF1_OFFSET) & MPIDR_AFF1_OFFSET);
+
+ if (cpu > CORE1) {
+ ctr_reg = CLKMGR_CTL_CORE23CTR;
+
+ clock = clk_get_clksrc_hz(plat, ctr_reg,
+ CLKMGR_MAINPLL_PLLC0,
+ CLKMGR_PERPLL_PLLC0);
+ } else {
+ ctr_reg = CLKMGR_CTL_CORE01CTR;
+
+ clock = clk_get_clksrc_hz(plat, ctr_reg,
+ CLKMGR_MAINPLL_PLLC1,
+ CLKMGR_PERPLL_PLLC0);
+ }
+
+ if (cpu == CORE3)
+ ctr_reg = CLKMGR_CTL_CORE3CTR;
+ else if (cpu == CORE2)
+ ctr_reg = CLKMGR_CTL_CORE2CTR;
+ else
+ ctr_reg = CLKMGR_CTL_CORE01CTR;
+
+ clock /= 1 + (CM_REG_READL(plat, ctr_reg) &
+ CLKMGR_CLKCNT_MSK);
+
+ return clock;
+}
+
+static u32 clk_get_l3_main_clk_hz(struct socfpga_clk_plat *plat)
+{
+ return clk_get_clksrc_hz(plat, CLKMGR_MAINPLL_NOCCLK,
+ CLKMGR_MAINPLL_PLLC3,
+ CLKMGR_PERPLL_PLLC1);
+}
+
+static u32 clk_get_l4_main_clk_hz(struct socfpga_clk_plat *plat)
+{
+ u64 clock = clk_get_l3_main_clk_hz(plat);
+
+ return clock;
+}
+
+static u32 clk_get_l4_sp_clk_hz(struct socfpga_clk_plat *plat)
+{
+ u64 clock = clk_get_l3_main_clk_hz(plat);
+
+ clock /= BIT((CM_REG_READL(plat, CLKMGR_MAINPLL_NOCDIV) >>
+ CLKMGR_NOCDIV_L4SPCLK_OFFSET) &
+ CLKMGR_NOCDIV_DIVIDER_MASK);
+
+ return clock;
+}
+
+static u32 clk_get_l4_mp_clk_hz(struct socfpga_clk_plat *plat)
+{
+ u64 clock = clk_get_l3_main_clk_hz(plat);
+
+ clock /= BIT((CM_REG_READL(plat, CLKMGR_MAINPLL_NOCDIV) >>
+ CLKMGR_NOCDIV_L4MPCLK_OFFSET) &
+ CLKMGR_NOCDIV_DIVIDER_MASK);
+
+ return clock;
+}
+
+static u32 clk_get_sdmmc_clk_hz(struct socfpga_clk_plat *plat)
+{
+ u64 clock = clk_get_l4_mp_clk_hz(plat);
+
+ clock /= BIT((CM_REG_READL(plat, CLKMGR_MAINPLL_NOCDIV) >>
+ CLKMGR_NOCDIV_SOFTPHY_OFFSET) &
+ CLKMGR_NOCDIV_DIVIDER_MASK);
+
+ return clock;
+}
+
+static u32 clk_get_l4_sys_free_clk_hz(struct socfpga_clk_plat *plat)
+{
+ if (CM_REG_READL(plat, CLKMGR_STAT) & CLKMGR_STAT_BOOTMODE)
+ return clk_get_l3_main_clk_hz(plat) / 2;
+
+ return clk_get_l3_main_clk_hz(plat) / 4;
+}
+
+static u32 clk_get_emac_clk_hz(struct socfpga_clk_plat *plat, u32 emac_id)
+{
+ u32 ctl;
+ u32 ctr_reg;
+ u32 clock;
+ u32 div;
+ u32 reg;
+
+ if (emac_id == AGILEX5_EMAC_PTP_CLK) {
+ reg = CM_REG_READL(plat, CLKMGR_CTL_EMACPTPCTR);
+ ctr_reg = CLKMGR_CTL_EMACPTPCTR;
+ } else {
+ reg = CM_REG_READL(plat, CLKMGR_CTL_EMACACTR);
+ ctl = CM_REG_READL(plat, CLKMGR_PERPLL_EMACCTL);
+ if (emac_id == AGILEX5_EMAC0_CLK)
+ ctl = (ctl & CLKMGR_PERPLLGRP_EMACCTL_EMAC0SELB_MASK) >>
+ CLKMGR_PERPLLGRP_EMACCTL_EMAC0SELB_OFFSET;
+ else if (emac_id == AGILEX5_EMAC1_CLK)
+ ctl = (ctl & CLKMGR_PERPLLGRP_EMACCTL_EMAC1SELB_MASK) >>
+ CLKMGR_PERPLLGRP_EMACCTL_EMAC1SELB_OFFSET;
+ else if (emac_id == AGILEX5_EMAC2_CLK)
+ ctl = (ctl & CLKMGR_PERPLLGRP_EMACCTL_EMAC2SELB_MASK) >>
+ CLKMGR_PERPLLGRP_EMACCTL_EMAC2SELB_OFFSET;
+ else
+ return 0;
+
+ if (ctl) {
+ /* EMAC B source */
+ ctr_reg = CLKMGR_CTL_EMACBCTR;
+ } else {
+ /* EMAC A source */
+ ctr_reg = CLKMGR_CTL_EMACACTR;
+ }
+ }
+ /* Get EMAC clock source */
+ clock = (reg & CLKMGR_CTL_EMACCTR_SRC_MASK)
+ >> CLKMGR_CTL_EMACCTR_SRC_OFFSET;
+
+ reg = CM_REG_READL(plat, ctr_reg);
+ div = (reg & CLKMGR_CTL_EMACCTR_CNT_MASK)
+ >> CLKMGR_CTL_EMACCTR_CNT_OFFSET;
+
+ switch (clock) {
+ case CLKMGR_CLKSRC_MAIN:
+ clock = clk_get_main_vco_clk_hz(plat);
+
+ if (emac_id == AGILEX5_EMAC_PTP_CLK) {
+ clock /= (CM_REG_READL(plat, CLKMGR_MAINPLL_PLLC3) &
+ CLKMGR_CLKCNT_MSK);
+ } else {
+ clock /= (CM_REG_READL(plat, CLKMGR_MAINPLL_PLLC1) &
+ CLKMGR_CLKCNT_MSK);
+ }
+ break;
+
+ case CLKMGR_CLKSRC_PER:
+ clock = clk_get_per_vco_clk_hz(plat);
+
+ clock /= (CM_REG_READL(plat, CLKMGR_PERPLL_PLLC3) &
+ CLKMGR_CLKCNT_MSK);
+ break;
+
+ case CLKMGR_CLKSRC_OSC1:
+ clock = cm_get_osc_clk_hz();
+ break;
+
+ case CLKMGR_CLKSRC_INTOSC:
+ clock = cm_get_intosc_clk_hz();
+ break;
+
+ case CLKMGR_CLKSRC_FPGA:
+ clock = cm_get_fpga_clk_hz();
+ break;
+ }
+
+ clock /= 1 + div;
+
+ return clock;
+}
+
+static ulong socfpga_clk_get_rate(struct clk *clk)
+{
+ struct socfpga_clk_plat *plat = dev_get_plat(clk->dev);
+
+ switch (clk->id) {
+ case AGILEX5_MPU_CLK:
+ return clk_get_mpu_clk_hz(plat);
+ case AGILEX5_L4_MAIN_CLK:
+ return clk_get_l4_main_clk_hz(plat);
+ case AGILEX5_L4_SYS_FREE_CLK:
+ return clk_get_l4_sys_free_clk_hz(plat);
+ case AGILEX5_L4_MP_CLK:
+ return clk_get_l4_mp_clk_hz(plat);
+ case AGILEX5_L4_SP_CLK:
+ return clk_get_l4_sp_clk_hz(plat);
+ case AGILEX5_SDMMC_CLK:
+ case AGILEX5_NAND_CLK:
+ return clk_get_sdmmc_clk_hz(plat);
+ case AGILEX5_EMAC0_CLK:
+ case AGILEX5_EMAC1_CLK:
+ case AGILEX5_EMAC2_CLK:
+ case AGILEX5_EMAC_PTP_CLK:
+ return clk_get_emac_clk_hz(plat, clk->id);
+ case AGILEX5_USB_CLK:
+ case AGILEX5_NAND_X_CLK:
+ return clk_get_l4_mp_clk_hz(plat);
+ default:
+ return -ENXIO;
+ }
+}
+
+static int socfpga_clk_enable(struct clk *clk)
+{
+ return 0;
+}
+
+static int socfpga_clk_probe(struct udevice *dev)
+{
+ const struct cm_config *cm_default_cfg = cm_get_default_config();
+
+ clk_basic_init(dev, cm_default_cfg);
+
+ return 0;
+}
+
+static int socfpga_clk_of_to_plat(struct udevice *dev)
+{
+ struct socfpga_clk_plat *plat = dev_get_plat(dev);
+ fdt_addr_t addr;
+
+ addr = dev_read_addr(dev);
+ if (addr == FDT_ADDR_T_NONE)
+ return -EINVAL;
+ plat->regs = (void __iomem *)addr;
+
+ return 0;
+}
+
+static struct clk_ops socfpga_clk_ops = {
+ .enable = socfpga_clk_enable,
+ .get_rate = socfpga_clk_get_rate,
+};
+
+static const struct udevice_id socfpga_clk_match[] = {
+ { .compatible = "intel,agilex5-clkmgr" },
+ {}
+};
+
+U_BOOT_DRIVER(socfpga_agilex5_clk) = {
+ .name = "clk-agilex5",
+ .id = UCLASS_CLK,
+ .of_match = socfpga_clk_match,
+ .ops = &socfpga_clk_ops,
+ .probe = socfpga_clk_probe,
+ .of_to_plat = socfpga_clk_of_to_plat,
+ .plat_auto = sizeof(struct socfpga_clk_plat),
+};
diff --git a/drivers/clk/altera/clk-agilex5.h b/drivers/clk/altera/clk-agilex5.h
new file mode 100644
index 0000000..a4ddc1a
--- /dev/null
+++ b/drivers/clk/altera/clk-agilex5.h
@@ -0,0 +1,284 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Copyright (C) 2024 Intel Corporation <www.intel.com>
+ */
+
+#ifndef _CLK_AGILEX5_
+#define _CLK_AGILEX5_
+
+#ifndef __ASSEMBLY__
+#include <linux/bitops.h>
+#endif
+
+#define CORE0 1
+#define CORE1 2
+#define CORE2 3
+#define CORE3 4
+
+/* Derived from l4_main_clk (PSS clock) */
+#define COUNTER_FREQUENCY_REAL 400000000
+
+#define CM_REG_READL(plat, reg) \
+ readl((plat)->regs + (reg))
+
+#define CM_REG_WRITEL(plat, data, reg) \
+ writel(data, (plat)->regs + (reg))
+
+#define CM_REG_CLRBITS(plat, reg, clear) \
+ clrbits_le32((plat)->regs + (reg), (clear))
+
+#define CM_REG_SETBITS(plat, reg, set) \
+ setbits_le32((plat)->regs + (reg), (set))
+
+struct cm_config {
+ /* main group */
+ u32 main_pll_nocclk;
+ u32 main_pll_nocdiv;
+ u32 main_pll_pllglob;
+ u32 main_pll_fdbck;
+ u32 main_pll_pllc0;
+ u32 main_pll_pllc1;
+ u32 main_pll_pllc2;
+ u32 main_pll_pllc3;
+ u32 main_pll_pllm;
+
+ /* peripheral group */
+ u32 per_pll_emacctl;
+ u32 per_pll_gpiodiv;
+ u32 per_pll_pllglob;
+ u32 per_pll_fdbck;
+ u32 per_pll_pllc0;
+ u32 per_pll_pllc1;
+ u32 per_pll_pllc2;
+ u32 per_pll_pllc3;
+ u32 per_pll_pllm;
+
+ /* control group */
+ u32 ctl_emacactr;
+ u32 ctl_emacbctr;
+ u32 ctl_emacptpctr;
+ u32 ctl_gpiodbctr;
+ u32 ctl_s2fuser0ctr;
+ u32 ctl_s2fuser1ctr;
+ u32 ctl_psirefctr;
+ u32 ctl_usb31ctr;
+ u32 ctl_dsuctr;
+ u32 ctl_core01ctr;
+ u32 ctl_core23ctr;
+ u32 ctl_core2ctr;
+ u32 ctl_core3ctr;
+
+ /* incoming clock */
+ u32 hps_osc_clk_hz;
+ u32 fpga_clk_hz;
+ u32 spare[3];
+};
+
+/* Clock Manager registers */
+#define CLKMGR_CTRL 0
+#define CLKMGR_STAT 4
+#define CLKMGR_TESTIOCTRL 8
+#define CLKMGR_INTRGEN 0x0c
+#define CLKMGR_INTRMSK 0x10
+#define CLKMGR_INTRCLR 0x14
+#define CLKMGR_INTRSTS 0x18
+#define CLKMGR_INTRSTK 0x1c
+#define CLKMGR_INTRRAW 0x20
+
+/* Clock Manager Main PPL group registers */
+#define CLKMGR_MAINPLL_EN 0x24
+#define CLKMGR_MAINPLL_ENS 0x28
+#define CLKMGR_MAINPLL_ENR 0x2c
+#define CLKMGR_MAINPLL_BYPASS 0x30
+#define CLKMGR_MAINPLL_BYPASSS 0x34
+#define CLKMGR_MAINPLL_BYPASSR 0x38
+#define CLKMGR_MAINPLL_NOCCLK 0x40
+#define CLKMGR_MAINPLL_NOCDIV 0x44
+#define CLKMGR_MAINPLL_PLLGLOB 0x48
+#define CLKMGR_MAINPLL_FDBCK 0x4c
+#define CLKMGR_MAINPLL_MEM 0x50
+#define CLKMGR_MAINPLL_MEMSTAT 0x54
+#define CLKMGR_MAINPLL_VCOCALIB 0x58
+#define CLKMGR_MAINPLL_PLLC0 0x5c
+#define CLKMGR_MAINPLL_PLLC1 0x60
+#define CLKMGR_MAINPLL_PLLC2 0x64
+#define CLKMGR_MAINPLL_PLLC3 0x68
+#define CLKMGR_MAINPLL_PLLM 0x6c
+#define CLKMGR_MAINPLL_FHOP 0x70
+#define CLKMGR_MAINPLL_SSC 0x74
+#define CLKMGR_MAINPLL_LOSTLOCK 0x78
+
+/* Clock Manager Peripheral PPL group registers */
+#define CLKMGR_PERPLL_EN 0x7c
+#define CLKMGR_PERPLL_ENS 0x80
+#define CLKMGR_PERPLL_ENR 0x84
+#define CLKMGR_PERPLL_BYPASS 0x88
+#define CLKMGR_PERPLL_BYPASSS 0x8c
+#define CLKMGR_PERPLL_BYPASSR 0x90
+#define CLKMGR_PERPLL_EMACCTL 0x94
+#define CLKMGR_PERPLL_GPIODIV 0x98
+#define CLKMGR_PERPLL_PLLGLOB 0x9c
+#define CLKMGR_PERPLL_FDBCK 0xa0
+#define CLKMGR_PERPLL_MEM 0xa4
+#define CLKMGR_PERPLL_MEMSTAT 0xa8
+#define CLKMGR_PERPLL_VCOCALIB 0xac
+#define CLKMGR_PERPLL_PLLC0 0xb0
+#define CLKMGR_PERPLL_PLLC1 0xb4
+#define CLKMGR_PERPLL_PLLC2 0xb8
+#define CLKMGR_PERPLL_PLLC3 0xbc
+#define CLKMGR_PERPLL_PLLM 0xc0
+#define CLKMGR_PERPLL_FHOP 0xc4
+#define CLKMGR_PERPLL_SSC 0xc8
+#define CLKMGR_PERPLL_LOSTLOCK 0xcc
+
+/* Clock Manager Control group registers */
+#define CLKMGR_CTL_JTAG 0xd0
+#define CLKMGR_CTL_EMACACTR 0xd4
+#define CLKMGR_CTL_EMACBCTR 0xd8
+#define CLKMGR_CTL_EMACPTPCTR 0xdc
+#define CLKMGR_CTL_GPIODBCTR 0xe0
+#define CLKMGR_CTL_S2FUSER0CTR 0xe8
+#define CLKMGR_CTL_S2FUSER1CTR 0xec
+#define CLKMGR_CTL_PSIREFCTR 0xf0
+#define CLKMGR_CTL_EXTCNTRST 0xf4
+#define CLKMGR_CTL_USB31CTR 0xf8
+#define CLKMGR_CTL_DSUCTR 0xfc
+#define CLKMGR_CTL_CORE01CTR 0x100
+#define CLKMGR_CTL_CORE23CTR 0x104
+#define CLKMGR_CTL_CORE2CTR 0x108
+#define CLKMGR_CTL_CORE3CTR 0x10C
+
+#define CLKMGR_CTRL_BOOTMODE BIT(0)
+
+#define CLKMGR_STAT_BUSY BIT(0)
+#define CLKMGR_STAT_MAINPLL_LOCKED BIT(8)
+#define CLKMGR_STAT_MAIN_TRANS BIT(9)
+#define CLKMGR_STAT_PERPLL_LOCKED BIT(16)
+#define CLKMGR_STAT_PERF_TRANS BIT(17)
+#define CLKMGR_STAT_BOOTMODE BIT(24)
+#define CLKMGR_STAT_BOOTCLKSRC BIT(25)
+
+#define CLKMGR_STAT_ALLPLL_LOCKED_MASK \
+ (CLKMGR_STAT_MAINPLL_LOCKED | CLKMGR_STAT_PERPLL_LOCKED)
+
+#define CLKMGR_INTER_MAINPLLLOCKED_MASK 0x00000001
+#define CLKMGR_INTER_PERPLLLOCKED_MASK 0x00000002
+#define CLKMGR_INTER_MAINPLLLOST_MASK 0x00000004
+#define CLKMGR_INTER_PERPLLLOST_MASK 0x00000008
+
+#define CLKMGR_CLKSRC_MASK GENMASK(18, 16)
+#define CLKMGR_CLKSRC_OFFSET 16
+#define CLKMGR_CLKSRC_MAIN 0
+#define CLKMGR_CLKSRC_PER 1
+#define CLKMGR_CLKSRC_OSC1 2
+#define CLKMGR_CLKSRC_INTOSC 3
+#define CLKMGR_CLKSRC_FPGA 4
+#define CLKMGR_CLKCNT_MSK GENMASK(10, 0)
+
+#define CLKMGR_BYPASS_MAINPLL_ALL 0xf6
+#define CLKMGR_BYPASS_PERPLL_ALL 0xef
+
+#define CLKMGR_NOCDIV_SOFTPHY_DIV_ONE 0
+#define CLKMGR_NOCDIV_SOFTPHY_DIV_TWO 1
+#define CLKMGR_NOCDIV_SOFTPHY_DIV_FOUR 2
+#define CLKMGR_NOCDIV_L4SYSFREECLK_OFFSET 0
+#define CLKMGR_NOCDIV_L4MPCLK_OFFSET 4
+#define CLKMGR_NOCDIV_L4SPCLK_OFFSET 6
+#define CLKMGR_NOCDIV_SOFTPHY_OFFSET 16
+#define CLKMGR_NOCDIV_CCU_OFFSET 18
+#define CLKMGR_NOCDIV_MPUPERIPH_OFFSET 20
+#define CLKMGR_NOCDIV_CSATCLK_OFFSET 24
+#define CLKMGR_NOCDIV_CSTRACECLK_OFFSET 26
+#define CLKMGR_NOCDIV_CSPDBGCLK_OFFSET 28
+#define CLKMGR_NOCDIV_DIVIDER_MASK 0x3
+
+#define CLKMGR_PLLGLOB_PD_MASK BIT(0)
+#define CLKMGR_PLLGLOB_RST_MASK BIT(1)
+#define CLKMGR_PLLGLOB_AREFCLKDIV_MASK GENMASK(11, 8)
+#define CLKMGR_PLLGLOB_DREFCLKDIV_MASK GENMASK(13, 12)
+#define CLKMGR_PLLGLOB_REFCLKDIV_MASK GENMASK(13, 8)
+#define CLKMGR_PLLGLOB_MODCLKDIV_MASK GENMASK(24, 27)
+#define CLKMGR_PLLGLOB_AREFCLKDIV_OFFSET 8
+#define CLKMGR_PLLGLOB_DREFCLKDIV_OFFSET 12
+#define CLKMGR_PLLGLOB_REFCLKDIV_OFFSET 8
+#define CLKMGR_PLLGLOB_MODCLKDIV_OFFSET 24
+#define CLKMGR_PLLGLOB_VCO_PSRC_MASK GENMASK(17, 16)
+#define CLKMGR_PLLGLOB_VCO_PSRC_OFFSET 16
+#define CLKMGR_PLLGLOB_CLR_LOSTLOCK_BYPASS_MASK BIT(29)
+
+#define CLKMGR_VCO_PSRC_EOSC1 0
+#define CLKMGR_VCO_PSRC_INTOSC 1
+#define CLKMGR_VCO_PSRC_F2S 2
+
+#define CLKMGR_MEM_REQ_SET_MSK BIT(24)
+#define CLKMGR_MEM_WR_SET_MSK BIT(25)
+#define CLKMGR_MEM_ERR_MSK BIT(26)
+#define CLKMGR_MEM_WDAT_LSB_OFFSET 16
+#define CLKMGR_MEM_ADDR_MASK GENMASK(15, 0)
+#define CLKMGR_MEM_ADDR_START 0x00004000
+
+#define CLKMGR_PLLCX_EN_SET_MSK BIT(27)
+#define CLKMGR_PLLCX_MUTE_SET_MSK BIT(28)
+
+#define CLKMGR_VCOCALIB_MSCNT_MASK GENMASK(23, 16)
+#define CLKMGR_VCOCALIB_MSCNT_OFFSET 16
+#define CLKMGR_VCOCALIB_HSCNT_MASK GENMASK(9, 0)
+#define CLKMGR_VCOCALIB_MSCNT_CONST 100
+#define CLKMGR_VCOCALIB_HSCNT_CONST 4
+
+#define CLKMGR_PLLM_MDIV_MASK GENMASK(9, 0)
+
+#define CLKMGR_LOSTLOCK_SET_MASK BIT(0)
+
+#define CLKMGR_PERPLLGRP_EN_SDMMCCLK_MASK BIT(5)
+#define CLKMGR_PERPLLGRP_EMACCTL_EMAC0SELB_OFFSET 26
+#define CLKMGR_PERPLLGRP_EMACCTL_EMAC0SELB_MASK BIT(26)
+#define CLKMGR_PERPLLGRP_EMACCTL_EMAC1SELB_OFFSET 27
+#define CLKMGR_PERPLLGRP_EMACCTL_EMAC1SELB_MASK BIT(27)
+#define CLKMGR_PERPLLGRP_EMACCTL_EMAC2SELB_OFFSET 28
+#define CLKMGR_PERPLLGRP_EMACCTL_EMAC2SELB_MASK BIT(28)
+
+#define CLKMGR_CTL_EMACCTR_SRC_OFFSET 16
+#define CLKMGR_CTL_EMACCTR_SRC_MASK GENMASK(18, 16)
+#define CLKMGR_CTL_EMACCTR_CNT_OFFSET 0
+#define CLKMGR_CTL_EMACCTR_CNT_MASK GENMASK(10, 0)
+
+#define CLKMGR_CTL_EXTCNTRST_EMACACNTRST BIT(0)
+#define CLKMGR_CTL_EXTCNTRST_EMACBCNTRST BIT(1)
+#define CLKMGR_CTL_EXTCNTRST_EMACPTPCNTRST BIT(2)
+#define CLKMGR_CTL_EXTCNTRST_GPIODBCNTRST BIT(3)
+#define CLKMGR_CTL_EXTCNTRST_S2FUSER0CNTRST BIT(5)
+#define CLKMGR_CTL_EXTCNTRST_S2FUSER1CNTRST BIT(6)
+#define CLKMGR_CTL_EXTCNTRST_PSIREFCNTRST BIT(7)
+#define CLKMGR_CTL_EXTCNTRST_USB31REFCNTRST BIT(8)
+#define CLKMGR_CTL_EXTCNTRST_DSUCNTRST BIT(10)
+#define CLKMGR_CTL_EXTCNTRST_CORE01CNTRST BIT(11)
+#define CLKMGR_CTL_EXTCNTRST_CORE2CNTRST BIT(12)
+#define CLKMGR_CTL_EXTCNTRST_CORE3CNTRST BIT(13)
+#define CLKMGR_CTL_EXTCNTRST_ALLCNTRST \
+ (CLKMGR_CTL_EXTCNTRST_EMACACNTRST | \
+ CLKMGR_CTL_EXTCNTRST_EMACBCNTRST | \
+ CLKMGR_CTL_EXTCNTRST_EMACPTPCNTRST | \
+ CLKMGR_CTL_EXTCNTRST_GPIODBCNTRST | \
+ CLKMGR_CTL_EXTCNTRST_S2FUSER0CNTRST | \
+ CLKMGR_CTL_EXTCNTRST_S2FUSER1CNTRST | \
+ CLKMGR_CTL_EXTCNTRST_PSIREFCNTRST | \
+ CLKMGR_CTL_EXTCNTRST_USB31REFCNTRST | \
+ CLKMGR_CTL_EXTCNTRST_DSUCNTRST | \
+ CLKMGR_CTL_EXTCNTRST_CORE01CNTRST | \
+ CLKMGR_CTL_EXTCNTRST_CORE2CNTRST | \
+ CLKMGR_CTL_EXTCNTRST_CORE3CNTRST)
+
+#define MEMBUS_MAINPLL 0
+#define MEMBUS_PERPLL 1
+#define MEMBUS_TIMEOUT 1000
+
+#define MEMBUS_CLKSLICE_REG 0x27
+#define MEMBUS_SYNTHCALFOSC_INIT_CENTERFREQ_REG 0xb3
+#define MEMBUS_SYNTHPPM_WATCHDOGTMR_VF01_REG 0xe6
+#define MEMBUS_CALCLKSLICE0_DUTY_LOCOVR_REG 0x03
+#define MEMBUS_CALCLKSLICE1_DUTY_LOCOVR_REG 0x07
+
+#define MPIDR_AFF1_OFFSET 8
+#define MPIDR_AFF1_MASK 0x3
+#endif /* _CLK_AGILEX5_ */
diff --git a/drivers/clk/exynos/clk-exynos850.c b/drivers/clk/exynos/clk-exynos850.c
index cf94a3e..0c09ba0 100644
--- a/drivers/clk/exynos/clk-exynos850.c
+++ b/drivers/clk/exynos/clk-exynos850.c
@@ -10,6 +10,13 @@
#include <dt-bindings/clock/exynos850.h>
#include "clk.h"
+enum exynos850_cmu_id {
+ CMU_TOP,
+ CMU_PERI,
+ CMU_CORE,
+ CMU_HSI,
+};
+
/* ---- CMU_TOP ------------------------------------------------------------- */
/* Register Offset definitions for CMU_TOP (0x120e0000) */
@@ -19,9 +26,23 @@
#define PLL_CON3_PLL_SHARED0 0x014c
#define PLL_CON0_PLL_SHARED1 0x0180
#define PLL_CON3_PLL_SHARED1 0x018c
+#define CLK_CON_MUX_MUX_CLKCMU_CORE_BUS 0x1014
+#define CLK_CON_MUX_MUX_CLKCMU_CORE_CCI 0x1018
+#define CLK_CON_MUX_MUX_CLKCMU_CORE_MMC_EMBD 0x101c
+#define CLK_CON_MUX_MUX_CLKCMU_CORE_SSS 0x1020
+#define CLK_CON_MUX_MUX_CLKCMU_HSI_BUS 0x103c
+#define CLK_CON_MUX_MUX_CLKCMU_HSI_MMC_CARD 0x1040
+#define CLK_CON_MUX_MUX_CLKCMU_HSI_USB20DRD 0x1044
#define CLK_CON_MUX_MUX_CLKCMU_PERI_BUS 0x1070
#define CLK_CON_MUX_MUX_CLKCMU_PERI_IP 0x1074
#define CLK_CON_MUX_MUX_CLKCMU_PERI_UART 0x1078
+#define CLK_CON_DIV_CLKCMU_CORE_BUS 0x1820
+#define CLK_CON_DIV_CLKCMU_CORE_CCI 0x1824
+#define CLK_CON_DIV_CLKCMU_CORE_MMC_EMBD 0x1828
+#define CLK_CON_DIV_CLKCMU_CORE_SSS 0x182c
+#define CLK_CON_DIV_CLKCMU_HSI_BUS 0x1848
+#define CLK_CON_DIV_CLKCMU_HSI_MMC_CARD 0x184c
+#define CLK_CON_DIV_CLKCMU_HSI_USB20DRD 0x1850
#define CLK_CON_DIV_CLKCMU_PERI_BUS 0x187c
#define CLK_CON_DIV_CLKCMU_PERI_IP 0x1880
#define CLK_CON_DIV_CLKCMU_PERI_UART 0x1884
@@ -31,23 +52,40 @@
#define CLK_CON_DIV_PLL_SHARED1_DIV2 0x1898
#define CLK_CON_DIV_PLL_SHARED1_DIV3 0x189c
#define CLK_CON_DIV_PLL_SHARED1_DIV4 0x18a0
+#define CLK_CON_GAT_GATE_CLKCMU_CORE_BUS 0x201c
+#define CLK_CON_GAT_GATE_CLKCMU_CORE_CCI 0x2020
+#define CLK_CON_GAT_GATE_CLKCMU_CORE_MMC_EMBD 0x2024
+#define CLK_CON_GAT_GATE_CLKCMU_CORE_SSS 0x2028
+#define CLK_CON_GAT_GATE_CLKCMU_HSI_BUS 0x2044
+#define CLK_CON_GAT_GATE_CLKCMU_HSI_MMC_CARD 0x2048
+#define CLK_CON_GAT_GATE_CLKCMU_HSI_USB20DRD 0x204c
#define CLK_CON_GAT_GATE_CLKCMU_PERI_BUS 0x2080
#define CLK_CON_GAT_GATE_CLKCMU_PERI_IP 0x2084
#define CLK_CON_GAT_GATE_CLKCMU_PERI_UART 0x2088
-static const struct samsung_pll_clock top_pure_pll_clks[] = {
- PLL(pll_0822x, CLK_FOUT_SHARED0_PLL, "fout_shared0_pll", "clock-oscclk",
- PLL_CON3_PLL_SHARED0),
- PLL(pll_0822x, CLK_FOUT_SHARED1_PLL, "fout_shared1_pll", "clock-oscclk",
- PLL_CON3_PLL_SHARED1),
- PLL(pll_0831x, CLK_FOUT_MMC_PLL, "fout_mmc_pll", "clock-oscclk",
- PLL_CON3_PLL_MMC),
-};
-
-/* List of parent clocks for Muxes in CMU_TOP */
+/* List of parent clocks for Muxes in CMU_TOP: for PURECLKCOMP */
PNAME(mout_shared0_pll_p) = { "clock-oscclk", "fout_shared0_pll" };
PNAME(mout_shared1_pll_p) = { "clock-oscclk", "fout_shared1_pll" };
PNAME(mout_mmc_pll_p) = { "clock-oscclk", "fout_mmc_pll" };
+/* List of parent clocks for Muxes in CMU_TOP: for CMU_CORE */
+PNAME(mout_core_bus_p) = { "dout_shared1_div2", "dout_shared0_div3",
+ "dout_shared1_div3", "dout_shared0_div4" };
+PNAME(mout_core_cci_p) = { "dout_shared0_div2", "dout_shared1_div2",
+ "dout_shared0_div3", "dout_shared1_div3" };
+PNAME(mout_core_mmc_embd_p) = { "clock-oscclk", "dout_shared0_div2",
+ "dout_shared1_div2", "dout_shared0_div3",
+ "dout_shared1_div3", "mout_mmc_pll",
+ "clock-oscclk", "clock-oscclk" };
+PNAME(mout_core_sss_p) = { "dout_shared0_div3", "dout_shared1_div3",
+ "dout_shared0_div4", "dout_shared1_div4" };
+/* List of parent clocks for Muxes in CMU_TOP: for CMU_HSI */
+PNAME(mout_hsi_bus_p) = { "dout_shared0_div2", "dout_shared1_div2" };
+PNAME(mout_hsi_mmc_card_p) = { "clock-oscclk", "dout_shared0_div2",
+ "dout_shared1_div2", "dout_shared0_div3",
+ "dout_shared1_div3", "mout_mmc_pll",
+ "clock-oscclk", "clock-oscclk" };
+PNAME(mout_hsi_usb20drd_p) = { "clock-oscclk", "dout_shared0_div4",
+ "dout_shared1_div4", "clock-oscclk" };
/* List of parent clocks for Muxes in CMU_TOP: for CMU_PERI */
PNAME(mout_peri_bus_p) = { "dout_shared0_div4", "dout_shared1_div4" };
PNAME(mout_peri_uart_p) = { "clock-oscclk", "dout_shared0_div4",
@@ -55,6 +93,17 @@
PNAME(mout_peri_ip_p) = { "clock-oscclk", "dout_shared0_div4",
"dout_shared1_div4", "clock-oscclk" };
+/* PURECLKCOMP */
+
+static const struct samsung_pll_clock top_pure_pll_clks[] = {
+ PLL(pll_0822x, CLK_FOUT_SHARED0_PLL, "fout_shared0_pll", "clock-oscclk",
+ PLL_CON3_PLL_SHARED0),
+ PLL(pll_0822x, CLK_FOUT_SHARED1_PLL, "fout_shared1_pll", "clock-oscclk",
+ PLL_CON3_PLL_SHARED1),
+ PLL(pll_0831x, CLK_FOUT_MMC_PLL, "fout_mmc_pll", "clock-oscclk",
+ PLL_CON3_PLL_MMC),
+};
+
static const struct samsung_mux_clock top_pure_mux_clks[] = {
MUX(CLK_MOUT_SHARED0_PLL, "mout_shared0_pll", mout_shared0_pll_p,
PLL_CON0_PLL_SHARED0, 4, 1),
@@ -64,15 +113,6 @@
PLL_CON0_PLL_MMC, 4, 1),
};
-static const struct samsung_mux_clock top_peri_mux_clks[] = {
- MUX(CLK_MOUT_PERI_BUS, "mout_peri_bus", mout_peri_bus_p,
- CLK_CON_MUX_MUX_CLKCMU_PERI_BUS, 0, 1),
- MUX(CLK_MOUT_PERI_UART, "mout_peri_uart", mout_peri_uart_p,
- CLK_CON_MUX_MUX_CLKCMU_PERI_UART, 0, 2),
- MUX(CLK_MOUT_PERI_IP, "mout_peri_ip", mout_peri_ip_p,
- CLK_CON_MUX_MUX_CLKCMU_PERI_IP, 0, 2),
-};
-
static const struct samsung_div_clock top_pure_div_clks[] = {
DIV(CLK_DOUT_SHARED0_DIV3, "dout_shared0_div3", "mout_shared0_pll",
CLK_CON_DIV_PLL_SHARED0_DIV3, 0, 2),
@@ -88,15 +128,81 @@
CLK_CON_DIV_PLL_SHARED1_DIV4, 0, 1),
};
-static const struct samsung_div_clock top_peri_div_clks[] = {
- DIV(CLK_DOUT_PERI_BUS, "dout_peri_bus", "gout_peri_bus",
- CLK_CON_DIV_CLKCMU_PERI_BUS, 0, 4),
- DIV(CLK_DOUT_PERI_UART, "dout_peri_uart", "gout_peri_uart",
- CLK_CON_DIV_CLKCMU_PERI_UART, 0, 4),
- DIV(CLK_DOUT_PERI_IP, "dout_peri_ip", "gout_peri_ip",
- CLK_CON_DIV_CLKCMU_PERI_IP, 0, 4),
+/* CORE */
+
+static const struct samsung_mux_clock top_core_mux_clks[] = {
+ MUX(CLK_MOUT_CORE_BUS, "mout_core_bus", mout_core_bus_p,
+ CLK_CON_MUX_MUX_CLKCMU_CORE_BUS, 0, 2),
+ MUX(CLK_MOUT_CORE_CCI, "mout_core_cci", mout_core_cci_p,
+ CLK_CON_MUX_MUX_CLKCMU_CORE_CCI, 0, 2),
+ MUX(CLK_MOUT_CORE_MMC_EMBD, "mout_core_mmc_embd", mout_core_mmc_embd_p,
+ CLK_CON_MUX_MUX_CLKCMU_CORE_MMC_EMBD, 0, 3),
+ MUX(CLK_MOUT_CORE_SSS, "mout_core_sss", mout_core_sss_p,
+ CLK_CON_MUX_MUX_CLKCMU_CORE_SSS, 0, 2),
+};
+
+static const struct samsung_gate_clock top_core_gate_clks[] = {
+ GATE(CLK_GOUT_CORE_BUS, "gout_core_bus", "mout_core_bus",
+ CLK_CON_GAT_GATE_CLKCMU_CORE_BUS, 21, 0, 0),
+ GATE(CLK_GOUT_CORE_CCI, "gout_core_cci", "mout_core_cci",
+ CLK_CON_GAT_GATE_CLKCMU_CORE_CCI, 21, 0, 0),
+ GATE(CLK_GOUT_CORE_MMC_EMBD, "gout_core_mmc_embd", "mout_core_mmc_embd",
+ CLK_CON_GAT_GATE_CLKCMU_CORE_MMC_EMBD, 21, 0, 0),
+ GATE(CLK_GOUT_CORE_SSS, "gout_core_sss", "mout_core_sss",
+ CLK_CON_GAT_GATE_CLKCMU_CORE_SSS, 21, 0, 0),
};
+static const struct samsung_div_clock top_core_div_clks[] = {
+ DIV(CLK_DOUT_CORE_BUS, "dout_core_bus", "gout_core_bus",
+ CLK_CON_DIV_CLKCMU_CORE_BUS, 0, 4),
+ DIV(CLK_DOUT_CORE_CCI, "dout_core_cci", "gout_core_cci",
+ CLK_CON_DIV_CLKCMU_CORE_CCI, 0, 4),
+ DIV(CLK_DOUT_CORE_MMC_EMBD, "dout_core_mmc_embd", "gout_core_mmc_embd",
+ CLK_CON_DIV_CLKCMU_CORE_MMC_EMBD, 0, 9),
+ DIV(CLK_DOUT_CORE_SSS, "dout_core_sss", "gout_core_sss",
+ CLK_CON_DIV_CLKCMU_CORE_SSS, 0, 4),
+};
+
+/* HSI */
+
+static const struct samsung_mux_clock top_hsi_mux_clks[] = {
+ MUX(CLK_MOUT_HSI_BUS, "mout_hsi_bus", mout_hsi_bus_p,
+ CLK_CON_MUX_MUX_CLKCMU_HSI_BUS, 0, 1),
+ MUX(CLK_MOUT_HSI_MMC_CARD, "mout_hsi_mmc_card", mout_hsi_mmc_card_p,
+ CLK_CON_MUX_MUX_CLKCMU_HSI_MMC_CARD, 0, 3),
+ MUX(CLK_MOUT_HSI_USB20DRD, "mout_hsi_usb20drd", mout_hsi_usb20drd_p,
+ CLK_CON_MUX_MUX_CLKCMU_HSI_USB20DRD, 0, 2),
+};
+
+static const struct samsung_gate_clock top_hsi_gate_clks[] = {
+ GATE(CLK_GOUT_HSI_BUS, "gout_hsi_bus", "mout_hsi_bus",
+ CLK_CON_GAT_GATE_CLKCMU_HSI_BUS, 21, 0, 0),
+ GATE(CLK_GOUT_HSI_MMC_CARD, "gout_hsi_mmc_card", "mout_hsi_mmc_card",
+ CLK_CON_GAT_GATE_CLKCMU_HSI_MMC_CARD, 21, 0, 0),
+ GATE(CLK_GOUT_HSI_USB20DRD, "gout_hsi_usb20drd", "mout_hsi_usb20drd",
+ CLK_CON_GAT_GATE_CLKCMU_HSI_USB20DRD, 21, 0, 0),
+};
+
+static const struct samsung_div_clock top_hsi_div_clks[] = {
+ DIV(CLK_DOUT_HSI_BUS, "dout_hsi_bus", "gout_hsi_bus",
+ CLK_CON_DIV_CLKCMU_HSI_BUS, 0, 4),
+ DIV(CLK_DOUT_HSI_MMC_CARD, "dout_hsi_mmc_card", "gout_hsi_mmc_card",
+ CLK_CON_DIV_CLKCMU_HSI_MMC_CARD, 0, 9),
+ DIV(CLK_DOUT_HSI_USB20DRD, "dout_hsi_usb20drd", "gout_hsi_usb20drd",
+ CLK_CON_DIV_CLKCMU_HSI_USB20DRD, 0, 4),
+};
+
+/* PERI */
+
+static const struct samsung_mux_clock top_peri_mux_clks[] = {
+ MUX(CLK_MOUT_PERI_BUS, "mout_peri_bus", mout_peri_bus_p,
+ CLK_CON_MUX_MUX_CLKCMU_PERI_BUS, 0, 1),
+ MUX(CLK_MOUT_PERI_UART, "mout_peri_uart", mout_peri_uart_p,
+ CLK_CON_MUX_MUX_CLKCMU_PERI_UART, 0, 2),
+ MUX(CLK_MOUT_PERI_IP, "mout_peri_ip", mout_peri_ip_p,
+ CLK_CON_MUX_MUX_CLKCMU_PERI_IP, 0, 2),
+};
+
static const struct samsung_gate_clock top_peri_gate_clks[] = {
GATE(CLK_GOUT_PERI_BUS, "gout_peri_bus", "mout_peri_bus",
CLK_CON_GAT_GATE_CLKCMU_PERI_BUS, 21, 0, 0),
@@ -106,12 +212,31 @@
CLK_CON_GAT_GATE_CLKCMU_PERI_IP, 21, 0, 0),
};
+static const struct samsung_div_clock top_peri_div_clks[] = {
+ DIV(CLK_DOUT_PERI_BUS, "dout_peri_bus", "gout_peri_bus",
+ CLK_CON_DIV_CLKCMU_PERI_BUS, 0, 4),
+ DIV(CLK_DOUT_PERI_UART, "dout_peri_uart", "gout_peri_uart",
+ CLK_CON_DIV_CLKCMU_PERI_UART, 0, 4),
+ DIV(CLK_DOUT_PERI_IP, "dout_peri_ip", "gout_peri_ip",
+ CLK_CON_DIV_CLKCMU_PERI_IP, 0, 4),
+};
+
static const struct samsung_clk_group top_cmu_clks[] = {
/* CMU_TOP_PURECLKCOMP */
{ S_CLK_PLL, top_pure_pll_clks, ARRAY_SIZE(top_pure_pll_clks) },
{ S_CLK_MUX, top_pure_mux_clks, ARRAY_SIZE(top_pure_mux_clks) },
{ S_CLK_DIV, top_pure_div_clks, ARRAY_SIZE(top_pure_div_clks) },
+ /* CMU_TOP clocks for CMU_CORE */
+ { S_CLK_MUX, top_core_mux_clks, ARRAY_SIZE(top_core_mux_clks) },
+ { S_CLK_GATE, top_core_gate_clks, ARRAY_SIZE(top_core_gate_clks) },
+ { S_CLK_DIV, top_core_div_clks, ARRAY_SIZE(top_core_div_clks) },
+
+ /* CMU_TOP clocks for CMU_HSI */
+ { S_CLK_MUX, top_hsi_mux_clks, ARRAY_SIZE(top_hsi_mux_clks) },
+ { S_CLK_GATE, top_hsi_gate_clks, ARRAY_SIZE(top_hsi_gate_clks) },
+ { S_CLK_DIV, top_hsi_div_clks, ARRAY_SIZE(top_hsi_div_clks) },
+
/* CMU_TOP clocks for CMU_PERI */
{ S_CLK_MUX, top_peri_mux_clks, ARRAY_SIZE(top_peri_mux_clks) },
{ S_CLK_GATE, top_peri_gate_clks, ARRAY_SIZE(top_peri_gate_clks) },
@@ -120,7 +245,7 @@
static int exynos850_cmu_top_probe(struct udevice *dev)
{
- return samsung_cmu_register_one(dev, top_cmu_clks,
+ return samsung_cmu_register_one(dev, CMU_TOP, top_cmu_clks,
ARRAY_SIZE(top_cmu_clks));
}
@@ -129,11 +254,13 @@
{ }
};
+SAMSUNG_CLK_OPS(exynos850_cmu_top, CMU_TOP);
+
U_BOOT_DRIVER(exynos850_cmu_top) = {
.name = "exynos850-cmu-top",
.id = UCLASS_CLK,
.of_match = exynos850_cmu_top_ids,
- .ops = &ccf_clk_ops,
+ .ops = &exynos850_cmu_top_clk_ops,
.probe = exynos850_cmu_top_probe,
.flags = DM_FLAG_PRE_RELOC,
};
@@ -171,7 +298,8 @@
static int exynos850_cmu_peri_probe(struct udevice *dev)
{
- return samsung_register_cmu(dev, peri_cmu_clks, exynos850_cmu_top);
+ return samsung_register_cmu(dev, CMU_PERI, peri_cmu_clks,
+ exynos850_cmu_top);
}
static const struct udevice_id exynos850_cmu_peri_ids[] = {
@@ -179,11 +307,149 @@
{ }
};
+SAMSUNG_CLK_OPS(exynos850_cmu_peri, CMU_PERI);
+
U_BOOT_DRIVER(exynos850_cmu_peri) = {
.name = "exynos850-cmu-peri",
.id = UCLASS_CLK,
.of_match = exynos850_cmu_peri_ids,
- .ops = &ccf_clk_ops,
+ .ops = &exynos850_cmu_peri_clk_ops,
.probe = exynos850_cmu_peri_probe,
.flags = DM_FLAG_PRE_RELOC,
};
+
+/* ---- CMU_CORE ------------------------------------------------------------ */
+
+/* Register Offset definitions for CMU_CORE (0x12000000) */
+#define PLL_CON0_MUX_CLKCMU_CORE_BUS_USER 0x0600
+#define PLL_CON0_MUX_CLKCMU_CORE_MMC_EMBD_USER 0x0620
+#define CLK_CON_DIV_DIV_CLK_CORE_BUSP 0x1800
+#define CLK_CON_GAT_GOUT_CORE_MMC_EMBD_I_ACLK 0x20e8
+#define CLK_CON_GAT_GOUT_CORE_MMC_EMBD_SDCLKIN 0x20ec
+
+/* List of parent clocks for Muxes in CMU_CORE */
+PNAME(mout_core_bus_user_p) = { "clock-oscclk", "dout_core_bus" };
+PNAME(mout_core_mmc_embd_user_p) = { "clock-oscclk",
+ "dout_core_mmc_embd" };
+
+static const struct samsung_mux_clock core_mux_clks[] = {
+ MUX(CLK_MOUT_CORE_BUS_USER, "mout_core_bus_user", mout_core_bus_user_p,
+ PLL_CON0_MUX_CLKCMU_CORE_BUS_USER, 4, 1),
+ MUX_F(CLK_MOUT_CORE_MMC_EMBD_USER, "mout_core_mmc_embd_user",
+ mout_core_mmc_embd_user_p, PLL_CON0_MUX_CLKCMU_CORE_MMC_EMBD_USER,
+ 4, 1, CLK_SET_RATE_PARENT, 0),
+};
+
+static const struct samsung_div_clock core_div_clks[] = {
+ DIV(CLK_DOUT_CORE_BUSP, "dout_core_busp", "mout_core_bus_user",
+ CLK_CON_DIV_DIV_CLK_CORE_BUSP, 0, 2),
+};
+
+static const struct samsung_gate_clock core_gate_clks[] = {
+ GATE(CLK_GOUT_MMC_EMBD_ACLK, "gout_mmc_embd_aclk", "dout_core_busp",
+ CLK_CON_GAT_GOUT_CORE_MMC_EMBD_I_ACLK, 21, 0, 0),
+ GATE(CLK_GOUT_MMC_EMBD_SDCLKIN, "gout_mmc_embd_sdclkin",
+ "mout_core_mmc_embd_user", CLK_CON_GAT_GOUT_CORE_MMC_EMBD_SDCLKIN,
+ 21, CLK_SET_RATE_PARENT, 0),
+};
+
+static const struct samsung_clk_group core_cmu_clks[] = {
+ { S_CLK_MUX, core_mux_clks, ARRAY_SIZE(core_mux_clks) },
+ { S_CLK_DIV, core_div_clks, ARRAY_SIZE(core_div_clks) },
+ { S_CLK_GATE, core_gate_clks, ARRAY_SIZE(core_gate_clks) },
+};
+
+static int exynos850_cmu_core_probe(struct udevice *dev)
+{
+ return samsung_register_cmu(dev, CMU_CORE, core_cmu_clks,
+ exynos850_cmu_top);
+}
+
+static const struct udevice_id exynos850_cmu_core_ids[] = {
+ { .compatible = "samsung,exynos850-cmu-core" },
+ { }
+};
+
+SAMSUNG_CLK_OPS(exynos850_cmu_core, CMU_CORE);
+
+U_BOOT_DRIVER(exynos850_cmu_core) = {
+ .name = "exynos850-cmu-core",
+ .id = UCLASS_CLK,
+ .of_match = exynos850_cmu_core_ids,
+ .ops = &exynos850_cmu_core_clk_ops,
+ .probe = exynos850_cmu_core_probe,
+ .flags = DM_FLAG_PRE_RELOC,
+};
+
+/* ---- CMU_HSI ------------------------------------------------------------- */
+
+/* Register Offset definitions for CMU_HSI (0x13400000) */
+#define PLL_CON0_MUX_CLKCMU_HSI_BUS_USER 0x0600
+#define PLL_CON0_MUX_CLKCMU_HSI_MMC_CARD_USER 0x0610
+#define PLL_CON0_MUX_CLKCMU_HSI_USB20DRD_USER 0x0620
+#define CLK_CON_GAT_HSI_USB20DRD_TOP_I_REF_CLK_50 0x200c
+#define CLK_CON_GAT_HSI_USB20DRD_TOP_I_PHY_REFCLK_26 0x2010
+#define CLK_CON_GAT_GOUT_HSI_MMC_CARD_I_ACLK 0x2024
+#define CLK_CON_GAT_GOUT_HSI_MMC_CARD_SDCLKIN 0x2028
+#define CLK_CON_GAT_GOUT_HSI_USB20DRD_TOP_ACLK_PHYCTRL_20 0x203c
+#define CLK_CON_GAT_GOUT_HSI_USB20DRD_TOP_BUS_CLK_EARLY 0x2040
+
+/* List of parent clocks for Muxes in CMU_HSI */
+PNAME(mout_hsi_bus_user_p) = { "clock-oscclk", "dout_hsi_bus" };
+PNAME(mout_hsi_mmc_card_user_p) = { "clock-oscclk", "dout_hsi_mmc_card" };
+PNAME(mout_hsi_usb20drd_user_p) = { "clock-oscclk", "dout_hsi_usb20drd" };
+
+static const struct samsung_mux_clock hsi_mux_clks[] __initconst = {
+ MUX(CLK_MOUT_HSI_BUS_USER, "mout_hsi_bus_user", mout_hsi_bus_user_p,
+ PLL_CON0_MUX_CLKCMU_HSI_BUS_USER, 4, 1),
+ MUX_F(CLK_MOUT_HSI_MMC_CARD_USER, "mout_hsi_mmc_card_user",
+ mout_hsi_mmc_card_user_p, PLL_CON0_MUX_CLKCMU_HSI_MMC_CARD_USER,
+ 4, 1, CLK_SET_RATE_PARENT, 0),
+ MUX(CLK_MOUT_HSI_USB20DRD_USER, "mout_hsi_usb20drd_user",
+ mout_hsi_usb20drd_user_p, PLL_CON0_MUX_CLKCMU_HSI_USB20DRD_USER,
+ 4, 1),
+};
+
+static const struct samsung_gate_clock hsi_gate_clks[] __initconst = {
+ GATE(CLK_GOUT_USB_REF_CLK, "gout_usb_ref", "mout_hsi_usb20drd_user",
+ CLK_CON_GAT_HSI_USB20DRD_TOP_I_REF_CLK_50, 21, 0, 0),
+ GATE(CLK_GOUT_USB_PHY_REF_CLK, "gout_usb_phy_ref", "clock-oscclk",
+ CLK_CON_GAT_HSI_USB20DRD_TOP_I_PHY_REFCLK_26, 21, 0, 0),
+ GATE(CLK_GOUT_MMC_CARD_ACLK, "gout_mmc_card_aclk", "mout_hsi_bus_user",
+ CLK_CON_GAT_GOUT_HSI_MMC_CARD_I_ACLK, 21, 0, 0),
+ GATE(CLK_GOUT_MMC_CARD_SDCLKIN, "gout_mmc_card_sdclkin",
+ "mout_hsi_mmc_card_user",
+ CLK_CON_GAT_GOUT_HSI_MMC_CARD_SDCLKIN, 21, CLK_SET_RATE_PARENT, 0),
+ GATE(CLK_GOUT_USB_PHY_ACLK, "gout_usb_phy_aclk", "mout_hsi_bus_user",
+ CLK_CON_GAT_GOUT_HSI_USB20DRD_TOP_ACLK_PHYCTRL_20, 21, 0, 0),
+ GATE(CLK_GOUT_USB_BUS_EARLY_CLK, "gout_usb_bus_early",
+ "mout_hsi_bus_user",
+ CLK_CON_GAT_GOUT_HSI_USB20DRD_TOP_BUS_CLK_EARLY, 21, 0, 0),
+};
+
+static const struct samsung_clk_group hsi_cmu_clks[] = {
+ { S_CLK_MUX, hsi_mux_clks, ARRAY_SIZE(hsi_mux_clks) },
+ { S_CLK_GATE, hsi_gate_clks, ARRAY_SIZE(hsi_gate_clks) },
+};
+
+static int exynos850_cmu_hsi_probe(struct udevice *dev)
+{
+ return samsung_register_cmu(dev, CMU_HSI, hsi_cmu_clks,
+ exynos850_cmu_hsi);
+}
+
+static const struct udevice_id exynos850_cmu_hsi_ids[] = {
+ { .compatible = "samsung,exynos850-cmu-hsi" },
+ { }
+};
+
+SAMSUNG_CLK_OPS(exynos850_cmu_hsi, CMU_HSI);
+
+U_BOOT_DRIVER(exynos850_cmu_hsi) = {
+ .name = "exynos850-cmu-hsi",
+ .id = UCLASS_CLK,
+ .of_match = exynos850_cmu_hsi_ids,
+ .ops = &exynos850_cmu_hsi_clk_ops,
+ .probe = exynos850_cmu_hsi_probe,
+ .flags = DM_FLAG_PRE_RELOC,
+};
diff --git a/drivers/clk/exynos/clk-pll.c b/drivers/clk/exynos/clk-pll.c
index 4aacbc2..542d577 100644
--- a/drivers/clk/exynos/clk-pll.c
+++ b/drivers/clk/exynos/clk-pll.c
@@ -136,7 +136,7 @@
return clk;
}
-void samsung_clk_register_pll(void __iomem *base,
+void samsung_clk_register_pll(void __iomem *base, unsigned int cmu_id,
const struct samsung_pll_clock *clk_list,
unsigned int nr_clk)
{
@@ -145,10 +145,12 @@
for (cnt = 0; cnt < nr_clk; cnt++) {
struct clk *clk;
const struct samsung_pll_clock *pll_clk;
+ unsigned long clk_id;
pll_clk = &clk_list[cnt];
clk = _samsung_clk_register_pll(base, pll_clk);
- clk_dm(pll_clk->id, clk);
+ clk_id = SAMSUNG_TO_CLK_ID(cmu_id, pll_clk->id);
+ clk_dm(clk_id, clk);
}
}
diff --git a/drivers/clk/exynos/clk-pll.h b/drivers/clk/exynos/clk-pll.h
index bd79309..bdc94e7 100644
--- a/drivers/clk/exynos/clk-pll.h
+++ b/drivers/clk/exynos/clk-pll.h
@@ -15,9 +15,15 @@
#include <linux/clk-provider.h>
+struct samsung_pll_clock;
+
enum samsung_pll_type {
pll_0822x,
pll_0831x,
};
+void samsung_clk_register_pll(void __iomem *base, unsigned int cmu_id,
+ const struct samsung_pll_clock *clk_list,
+ unsigned int nr_clk);
+
#endif /* __EXYNOS_CLK_PLL_H */
diff --git a/drivers/clk/exynos/clk.c b/drivers/clk/exynos/clk.c
index 430767f..943e8bd 100644
--- a/drivers/clk/exynos/clk.c
+++ b/drivers/clk/exynos/clk.c
@@ -10,61 +10,67 @@
#include <dm.h>
#include "clk.h"
-void samsung_clk_register_mux(void __iomem *base,
- const struct samsung_mux_clock *clk_list,
- unsigned int nr_clk)
+static void samsung_clk_register_mux(void __iomem *base, unsigned int cmu_id,
+ const struct samsung_mux_clock *clk_list,
+ unsigned int nr_clk)
{
unsigned int cnt;
for (cnt = 0; cnt < nr_clk; cnt++) {
struct clk *clk;
const struct samsung_mux_clock *m;
+ unsigned long clk_id;
m = &clk_list[cnt];
clk = clk_register_mux(NULL, m->name, m->parent_names,
m->num_parents, m->flags, base + m->offset, m->shift,
m->width, m->mux_flags);
- clk_dm(m->id, clk);
+ clk_id = SAMSUNG_TO_CLK_ID(cmu_id, m->id);
+ clk_dm(clk_id, clk);
}
}
-void samsung_clk_register_div(void __iomem *base,
- const struct samsung_div_clock *clk_list,
- unsigned int nr_clk)
+static void samsung_clk_register_div(void __iomem *base, unsigned int cmu_id,
+ const struct samsung_div_clock *clk_list,
+ unsigned int nr_clk)
{
unsigned int cnt;
for (cnt = 0; cnt < nr_clk; cnt++) {
struct clk *clk;
const struct samsung_div_clock *d;
+ unsigned long clk_id;
d = &clk_list[cnt];
clk = clk_register_divider(NULL, d->name, d->parent_name,
d->flags, base + d->offset, d->shift,
d->width, d->div_flags);
- clk_dm(d->id, clk);
+ clk_id = SAMSUNG_TO_CLK_ID(cmu_id, d->id);
+ clk_dm(clk_id, clk);
}
}
-void samsung_clk_register_gate(void __iomem *base,
- const struct samsung_gate_clock *clk_list,
- unsigned int nr_clk)
+static void samsung_clk_register_gate(void __iomem *base, unsigned int cmu_id,
+ const struct samsung_gate_clock *clk_list,
+ unsigned int nr_clk)
{
unsigned int cnt;
for (cnt = 0; cnt < nr_clk; cnt++) {
struct clk *clk;
const struct samsung_gate_clock *g;
+ unsigned long clk_id;
g = &clk_list[cnt];
clk = clk_register_gate(NULL, g->name, g->parent_name,
g->flags, base + g->offset, g->bit_idx,
g->gate_flags, NULL);
- clk_dm(g->id, clk);
+ clk_id = SAMSUNG_TO_CLK_ID(cmu_id, g->id);
+ clk_dm(clk_id, clk);
}
}
-typedef void (*samsung_clk_register_fn)(void __iomem *base,
+typedef void (*samsung_clk_register_fn)(void __iomem *base, unsigned int cmu_id,
const void *clk_list,
unsigned int nr_clk);
@@ -78,34 +84,37 @@
/**
* samsung_cmu_register_clocks() - Register provided clock groups
* @base: Base address of CMU registers
+ * @cmu_id: CMU index number
* @clk_groups: list of clock groups
* @nr_groups: count of clock groups in @clk_groups
*
* Having the array of clock groups @clk_groups makes it possible to keep a
* correct clocks registration order.
*/
-void samsung_cmu_register_clocks(void __iomem *base,
- const struct samsung_clk_group *clk_groups,
- unsigned int nr_groups)
+static void samsung_cmu_register_clocks(void __iomem *base, unsigned int cmu_id,
+ const struct samsung_clk_group *clk_groups,
+ unsigned int nr_groups)
{
unsigned int i;
for (i = 0; i < nr_groups; i++) {
const struct samsung_clk_group *g = &clk_groups[i];
- samsung_clk_register_fns[g->type](base, g->clk_list, g->nr_clk);
+ samsung_clk_register_fns[g->type](base, cmu_id,
+ g->clk_list, g->nr_clk);
}
}
/**
* samsung_cmu_register_one - Register all CMU clocks
* @dev: CMU device
+ * @cmu_id: CMU index number
* @clk_groups: list of CMU clock groups
* @nr_groups: count of CMU clock groups in @clk_groups
*
* Return: 0 on success or negative value on error.
*/
-int samsung_cmu_register_one(struct udevice *dev,
+int samsung_cmu_register_one(struct udevice *dev, unsigned int cmu_id,
const struct samsung_clk_group *clk_groups,
unsigned int nr_groups)
{
@@ -115,7 +124,7 @@
if (!base)
return -EINVAL;
- samsung_cmu_register_clocks(base, clk_groups, nr_groups);
+ samsung_cmu_register_clocks(base, cmu_id, clk_groups, nr_groups);
return 0;
}
diff --git a/drivers/clk/exynos/clk.h b/drivers/clk/exynos/clk.h
index 91a51b8..ed0a395 100644
--- a/drivers/clk/exynos/clk.h
+++ b/drivers/clk/exynos/clk.h
@@ -13,6 +13,51 @@
#include <linux/clk-provider.h>
#include "clk-pll.h"
+#define _SAMSUNG_CLK_OPS(_name, _cmu) \
+static int _name##_of_xlate(struct clk *clk, \
+ struct ofnode_phandle_args *args) \
+{ \
+ if (args->args_count > 1) { \
+ debug("Invalid args_count: %d\n", args->args_count); \
+ return -EINVAL; \
+ } \
+ \
+ if (args->args_count) \
+ clk->id = SAMSUNG_TO_CLK_ID(_cmu, args->args[0]); \
+ else \
+ clk->id = 0; \
+ \
+ return 0; \
+} \
+ \
+static const struct clk_ops _name##_clk_ops = { \
+ .set_rate = ccf_clk_set_rate, \
+ .get_rate = ccf_clk_get_rate, \
+ .set_parent = ccf_clk_set_parent, \
+ .enable = ccf_clk_enable, \
+ .disable = ccf_clk_disable, \
+ .of_xlate = _name##_of_xlate, \
+}
+
+/**
+ * SAMSUNG_CLK_OPS - Define clock operations structure for specified CMU.
+ * @name: name of generated structure
+ * @cmu: CMU index
+ *
+ * Like ccf_clk_ops, but with custom .of_xlate callback.
+ */
+#define SAMSUNG_CLK_OPS(name, cmu) _SAMSUNG_CLK_OPS(name, cmu)
+
+/**
+ * SAMSUNG_TO_CLK_ID - Calculate a global clock index.
+ * @_cmu: CMU index
+ * @_id: local clock index (unique across @_cmu)
+ *
+ * Return: A global clock index unique across all CMUs.
+ * Keeps a range of 256 available clocks for every CMU.
+ */
+#define SAMSUNG_TO_CLK_ID(_cmu, _id) (((_cmu) << 8) | ((_id) & 0xff))
+
/**
* struct samsung_mux_clock - information about mux clock
* @id: platform specific id of the clock
@@ -179,29 +224,14 @@
unsigned int nr_clk;
};
-void samsung_clk_register_mux(void __iomem *base,
- const struct samsung_mux_clock *clk_list,
- unsigned int nr_clk);
-void samsung_clk_register_div(void __iomem *base,
- const struct samsung_div_clock *clk_list,
- unsigned int nr_clk);
-void samsung_clk_register_gate(void __iomem *base,
- const struct samsung_gate_clock *clk_list,
- unsigned int nr_clk);
-void samsung_clk_register_pll(void __iomem *base,
- const struct samsung_pll_clock *clk_list,
- unsigned int nr_clk);
-
-void samsung_cmu_register_clocks(void __iomem *base,
- const struct samsung_clk_group *clk_groups,
- unsigned int nr_groups);
-int samsung_cmu_register_one(struct udevice *dev,
+int samsung_cmu_register_one(struct udevice *dev, unsigned int cmu_id,
const struct samsung_clk_group *clk_groups,
unsigned int nr_groups);
/**
* samsung_register_cmu - Register CMU clocks ensuring parent CMU is present
* @dev: CMU device
+ * @cmu_id: CMU index number
* @clk_groups: list of CMU clock groups
* @parent_drv: name of parent CMU driver
*
@@ -210,7 +240,7 @@
*
* Return: 0 on success or negative value on error.
*/
-#define samsung_register_cmu(dev, clk_groups, parent_drv) \
+#define samsung_register_cmu(dev, cmu_id, clk_groups, parent_drv) \
({ \
struct udevice *__parent; \
int __ret; \
@@ -220,8 +250,8 @@
if (__ret || !__parent) \
__ret = -ENOENT; \
else \
- __ret = samsung_cmu_register_one(dev, clk_groups, \
- ARRAY_SIZE(clk_groups)); \
+ __ret = samsung_cmu_register_one(dev, cmu_id, \
+ clk_groups, ARRAY_SIZE(clk_groups)); \
__ret; \
})
diff --git a/drivers/clk/imx/clk-imx8mp.c b/drivers/clk/imx/clk-imx8mp.c
index a21a3ce..7dfc829 100644
--- a/drivers/clk/imx/clk-imx8mp.c
+++ b/drivers/clk/imx/clk-imx8mp.c
@@ -62,6 +62,10 @@
"sys_pll1_160m", "sys_pll1_800m", "sys_pll3_out",
"sys_pll2_250m", "audio_pll2_out", };
+static const char * const imx8mp_pcie_aux_sels[] = {"clock-osc-24m", "sys_pll2_200m", "sys_pll2_50m",
+ "sys_pll3_out", "sys_pll2_100m", "sys_pll1_80m",
+ "sys_pll1_160m", "sys_pll1_200m", };
+
static const char *imx8mp_i2c5_sels[] = {"clock-osc-24m", "sys_pll1_160m", "sys_pll2_50m",
"sys_pll3_out", "audio_pll1_out", "video_pll1_out",
"audio_pll2_out", "sys_pll1_133m", };
@@ -272,6 +276,7 @@
clk_dm(IMX8MP_CLK_DRAM_ALT, imx8m_clk_composite("dram_alt", imx8mp_dram_alt_sels, base + 0xa000));
clk_dm(IMX8MP_CLK_DRAM_APB, imx8m_clk_composite_critical("dram_apb", imx8mp_dram_apb_sels, base + 0xa080));
+ clk_dm(IMX8MP_CLK_PCIE_AUX, imx8m_clk_composite("pcie_aux", imx8mp_pcie_aux_sels, base + 0xa400));
clk_dm(IMX8MP_CLK_I2C5, imx8m_clk_composite("i2c5", imx8mp_i2c5_sels, base + 0xa480));
clk_dm(IMX8MP_CLK_I2C6, imx8m_clk_composite("i2c6", imx8mp_i2c6_sels, base + 0xa500));
clk_dm(IMX8MP_CLK_ENET_QOS, imx8m_clk_composite("enet_qos", imx8mp_enet_qos_sels, base + 0xa880));
@@ -322,6 +327,7 @@
clk_dm(IMX8MP_CLK_I2C2_ROOT, imx_clk_gate4("i2c2_root_clk", "i2c2", base + 0x4180, 0));
clk_dm(IMX8MP_CLK_I2C3_ROOT, imx_clk_gate4("i2c3_root_clk", "i2c3", base + 0x4190, 0));
clk_dm(IMX8MP_CLK_I2C4_ROOT, imx_clk_gate4("i2c4_root_clk", "i2c4", base + 0x41a0, 0));
+ clk_dm(IMX8MP_CLK_PCIE_ROOT, imx_clk_gate4("pcie_root_clk", "pcie_aux", base + 0x4250, 0));
clk_dm(IMX8MP_CLK_PWM1_ROOT, imx_clk_gate4("pwm1_root_clk", "pwm1", base + 0x4280, 0));
clk_dm(IMX8MP_CLK_PWM2_ROOT, imx_clk_gate4("pwm2_root_clk", "pwm2", base + 0x4290, 0));
clk_dm(IMX8MP_CLK_PWM3_ROOT, imx_clk_gate4("pwm3_root_clk", "pwm3", base + 0x42a0, 0));
diff --git a/drivers/clk/imx/clk-imx8qm.c b/drivers/clk/imx/clk-imx8qm.c
index 6c05d07..01e33de 100644
--- a/drivers/clk/imx/clk-imx8qm.c
+++ b/drivers/clk/imx/clk-imx8qm.c
@@ -95,20 +95,23 @@
resource = SC_R_SDHC_2;
pm_clk = SC_PM_CLK_PER;
break;
- case IMX8QM_UART0_IPG_CLK:
case IMX8QM_UART0_CLK:
+ case IMX8QM_UART0_IPG_CLK:
resource = SC_R_UART_0;
pm_clk = SC_PM_CLK_PER;
break;
case IMX8QM_UART1_CLK:
+ case IMX8QM_UART1_IPG_CLK:
resource = SC_R_UART_1;
pm_clk = SC_PM_CLK_PER;
break;
case IMX8QM_UART2_CLK:
+ case IMX8QM_UART2_IPG_CLK:
resource = SC_R_UART_2;
pm_clk = SC_PM_CLK_PER;
break;
case IMX8QM_UART3_CLK:
+ case IMX8QM_UART3_IPG_CLK:
resource = SC_R_UART_3;
pm_clk = SC_PM_CLK_PER;
break;
@@ -181,18 +184,22 @@
pm_clk = SC_PM_CLK_PER;
break;
case IMX8QM_UART0_CLK:
+ case IMX8QM_UART0_IPG_CLK:
resource = SC_R_UART_0;
pm_clk = SC_PM_CLK_PER;
break;
case IMX8QM_UART1_CLK:
+ case IMX8QM_UART1_IPG_CLK:
resource = SC_R_UART_1;
pm_clk = SC_PM_CLK_PER;
break;
case IMX8QM_UART2_CLK:
+ case IMX8QM_UART2_IPG_CLK:
resource = SC_R_UART_2;
pm_clk = SC_PM_CLK_PER;
break;
case IMX8QM_UART3_CLK:
+ case IMX8QM_UART3_IPG_CLK:
resource = SC_R_UART_3;
pm_clk = SC_PM_CLK_PER;
break;
@@ -283,18 +290,22 @@
pm_clk = SC_PM_CLK_PER;
break;
case IMX8QM_UART0_CLK:
+ case IMX8QM_UART0_IPG_CLK:
resource = SC_R_UART_0;
pm_clk = SC_PM_CLK_PER;
break;
case IMX8QM_UART1_CLK:
+ case IMX8QM_UART1_IPG_CLK:
resource = SC_R_UART_1;
pm_clk = SC_PM_CLK_PER;
break;
case IMX8QM_UART2_CLK:
+ case IMX8QM_UART2_IPG_CLK:
resource = SC_R_UART_2;
pm_clk = SC_PM_CLK_PER;
break;
case IMX8QM_UART3_CLK:
+ case IMX8QM_UART3_IPG_CLK:
resource = SC_R_UART_3;
pm_clk = SC_PM_CLK_PER;
break;
diff --git a/drivers/clk/imx/clk-imx8qxp.c b/drivers/clk/imx/clk-imx8qxp.c
index 8bf7e32..d900d4c 100644
--- a/drivers/clk/imx/clk-imx8qxp.c
+++ b/drivers/clk/imx/clk-imx8qxp.c
@@ -88,20 +88,23 @@
resource = SC_R_SDHC_1;
pm_clk = SC_PM_CLK_PER;
break;
- case IMX8QXP_UART0_IPG_CLK:
case IMX8QXP_UART0_CLK:
+ case IMX8QXP_UART0_IPG_CLK:
resource = SC_R_UART_0;
pm_clk = SC_PM_CLK_PER;
break;
case IMX8QXP_UART1_CLK:
+ case IMX8QXP_UART1_IPG_CLK:
resource = SC_R_UART_1;
pm_clk = SC_PM_CLK_PER;
break;
case IMX8QXP_UART2_CLK:
+ case IMX8QXP_UART2_IPG_CLK:
resource = SC_R_UART_2;
pm_clk = SC_PM_CLK_PER;
break;
case IMX8QXP_UART3_CLK:
+ case IMX8QXP_UART3_IPG_CLK:
resource = SC_R_UART_3;
pm_clk = SC_PM_CLK_PER;
break;
@@ -170,18 +173,22 @@
pm_clk = SC_PM_CLK_PER;
break;
case IMX8QXP_UART0_CLK:
+ case IMX8QXP_UART0_IPG_CLK:
resource = SC_R_UART_0;
pm_clk = SC_PM_CLK_PER;
break;
case IMX8QXP_UART1_CLK:
+ case IMX8QXP_UART1_IPG_CLK:
resource = SC_R_UART_1;
pm_clk = SC_PM_CLK_PER;
break;
case IMX8QXP_UART2_CLK:
+ case IMX8QXP_UART2_IPG_CLK:
resource = SC_R_UART_2;
pm_clk = SC_PM_CLK_PER;
break;
case IMX8QXP_UART3_CLK:
+ case IMX8QXP_UART3_IPG_CLK:
resource = SC_R_UART_3;
pm_clk = SC_PM_CLK_PER;
break;
@@ -263,18 +270,22 @@
pm_clk = SC_PM_CLK_PER;
break;
case IMX8QXP_UART0_CLK:
+ case IMX8QXP_UART0_IPG_CLK:
resource = SC_R_UART_0;
pm_clk = SC_PM_CLK_PER;
break;
case IMX8QXP_UART1_CLK:
+ case IMX8QXP_UART1_IPG_CLK:
resource = SC_R_UART_1;
pm_clk = SC_PM_CLK_PER;
break;
case IMX8QXP_UART2_CLK:
+ case IMX8QXP_UART2_IPG_CLK:
resource = SC_R_UART_2;
pm_clk = SC_PM_CLK_PER;
break;
case IMX8QXP_UART3_CLK:
+ case IMX8QXP_UART3_IPG_CLK:
resource = SC_R_UART_3;
pm_clk = SC_PM_CLK_PER;
break;
diff --git a/drivers/clk/qcom/Kconfig b/drivers/clk/qcom/Kconfig
index 0df0d18..8dae635 100644
--- a/drivers/clk/qcom/Kconfig
+++ b/drivers/clk/qcom/Kconfig
@@ -2,7 +2,7 @@
config CLK_QCOM
bool
- depends on CLK && DM_RESET
+ depends on CLK && DM_RESET && POWER_DOMAIN
def_bool n
menu "Qualcomm clock drivers"
diff --git a/drivers/clk/qcom/clock-apq8016.c b/drivers/clk/qcom/clock-apq8016.c
index e6647f7..5a58681 100644
--- a/drivers/clk/qcom/clock-apq8016.c
+++ b/drivers/clk/qcom/clock-apq8016.c
@@ -23,11 +23,7 @@
#define APCS_CLOCK_BRANCH_ENA_VOTE (0x45004)
#define SDCC_BCR(n) ((n * 0x1000) + 0x41000)
-#define SDCC_CMD_RCGR(n) ((n * 0x1000) + 0x41004)
-#define SDCC_CFG_RCGR(n) ((n * 0x1000) + 0x41008)
-#define SDCC_M(n) ((n * 0x1000) + 0x4100C)
-#define SDCC_N(n) ((n * 0x1000) + 0x41010)
-#define SDCC_D(n) ((n * 0x1000) + 0x41014)
+#define SDCC_CMD_RCGR(n) (((n + 1) * 0x1000) + 0x41004)
#define SDCC_APPS_CBCR(n) ((n * 0x1000) + 0x41018)
#define SDCC_AHB_CBCR(n) ((n * 0x1000) + 0x4101C)
@@ -38,31 +34,10 @@
#define BLSP1_UART2_BCR (0x3028)
#define BLSP1_UART2_APPS_CBCR (0x302C)
#define BLSP1_UART2_APPS_CMD_RCGR (0x3034)
-#define BLSP1_UART2_APPS_CFG_RCGR (0x3038)
-#define BLSP1_UART2_APPS_M (0x303C)
-#define BLSP1_UART2_APPS_N (0x3040)
-#define BLSP1_UART2_APPS_D (0x3044)
/* GPLL0 clock control registers */
#define GPLL0_STATUS_ACTIVE BIT(17)
-static const struct bcr_regs sdc_regs[] = {
- {
- .cfg_rcgr = SDCC_CFG_RCGR(1),
- .cmd_rcgr = SDCC_CMD_RCGR(1),
- .M = SDCC_M(1),
- .N = SDCC_N(1),
- .D = SDCC_D(1),
- },
- {
- .cfg_rcgr = SDCC_CFG_RCGR(2),
- .cmd_rcgr = SDCC_CMD_RCGR(2),
- .M = SDCC_M(2),
- .N = SDCC_N(2),
- .D = SDCC_D(2),
- }
-};
-
static struct pll_vote_clk gpll0_vote_clk = {
.status = GPLL0_STATUS,
.status_bit = GPLL0_STATUS_ACTIVE,
@@ -86,7 +61,7 @@
clk_enable_cbc(priv->base + SDCC_AHB_CBCR(slot));
/* 800Mhz/div, gpll0 */
- clk_rcg_set_rate_mnd(priv->base, &sdc_regs[slot], div, 0, 0,
+ clk_rcg_set_rate_mnd(priv->base, SDCC_CMD_RCGR(slot), div, 0, 0,
CFG_CLK_SRC_GPLL0, 8);
clk_enable_gpll0(priv->base, &gpll0_vote_clk);
clk_enable_cbc(priv->base + SDCC_APPS_CBCR(slot));
@@ -94,14 +69,6 @@
return rate;
}
-static const struct bcr_regs uart2_regs = {
- .cfg_rcgr = BLSP1_UART2_APPS_CFG_RCGR,
- .cmd_rcgr = BLSP1_UART2_APPS_CMD_RCGR,
- .M = BLSP1_UART2_APPS_M,
- .N = BLSP1_UART2_APPS_N,
- .D = BLSP1_UART2_APPS_D,
-};
-
/* UART: 115200 */
int apq8016_clk_init_uart(phys_addr_t base)
{
@@ -109,7 +76,7 @@
clk_enable_vote_clk(base, &gcc_blsp1_ahb_clk);
/* 7372800 uart block clock @ GPLL0 */
- clk_rcg_set_rate_mnd(base, &uart2_regs, 1, 144, 15625,
+ clk_rcg_set_rate_mnd(base, BLSP1_UART2_APPS_CMD_RCGR, 1, 144, 15625,
CFG_CLK_SRC_GPLL0, 16);
/* Vote for gpll0 clock */
diff --git a/drivers/clk/qcom/clock-apq8096.c b/drivers/clk/qcom/clock-apq8096.c
index a473161..479f977 100644
--- a/drivers/clk/qcom/clock-apq8096.c
+++ b/drivers/clk/qcom/clock-apq8096.c
@@ -26,31 +26,15 @@
#define SDCC2_APPS_CBCR (0x14004) /* branch control */
#define SDCC2_AHB_CBCR (0x14008)
#define SDCC2_CMD_RCGR (0x14010)
-#define SDCC2_CFG_RCGR (0x14014)
-#define SDCC2_M (0x14018)
-#define SDCC2_N (0x1401C)
-#define SDCC2_D (0x14020)
#define BLSP2_AHB_CBCR (0x25004)
#define BLSP2_UART2_APPS_CBCR (0x29004)
#define BLSP2_UART2_APPS_CMD_RCGR (0x2900C)
-#define BLSP2_UART2_APPS_CFG_RCGR (0x29010)
-#define BLSP2_UART2_APPS_M (0x29014)
-#define BLSP2_UART2_APPS_N (0x29018)
-#define BLSP2_UART2_APPS_D (0x2901C)
/* GPLL0 clock control registers */
#define GPLL0_STATUS_ACTIVE BIT(30)
#define APCS_GPLL_ENA_VOTE_GPLL0 BIT(0)
-static const struct bcr_regs sdc_regs = {
- .cfg_rcgr = SDCC2_CFG_RCGR,
- .cmd_rcgr = SDCC2_CMD_RCGR,
- .M = SDCC2_M,
- .N = SDCC2_N,
- .D = SDCC2_D,
-};
-
static const struct pll_vote_clk gpll0_vote_clk = {
.status = GPLL0_STATUS,
.status_bit = GPLL0_STATUS_ACTIVE,
@@ -69,7 +53,7 @@
int div = 5;
clk_enable_cbc(priv->base + SDCC2_AHB_CBCR);
- clk_rcg_set_rate_mnd(priv->base, &sdc_regs, div, 0, 0,
+ clk_rcg_set_rate_mnd(priv->base, SDCC2_CMD_RCGR, div, 0, 0,
CFG_CLK_SRC_GPLL0, 8);
clk_enable_gpll0(priv->base, &gpll0_vote_clk);
clk_enable_cbc(priv->base + SDCC2_APPS_CBCR);
@@ -77,21 +61,13 @@
return rate;
}
-static const struct bcr_regs uart2_regs = {
- .cfg_rcgr = BLSP2_UART2_APPS_CFG_RCGR,
- .cmd_rcgr = BLSP2_UART2_APPS_CMD_RCGR,
- .M = BLSP2_UART2_APPS_M,
- .N = BLSP2_UART2_APPS_N,
- .D = BLSP2_UART2_APPS_D,
-};
-
static int clk_init_uart(struct msm_clk_priv *priv)
{
/* Enable AHB clock */
clk_enable_vote_clk(priv->base, &gcc_blsp2_ahb_clk);
/* 7372800 uart block clock @ GPLL0 */
- clk_rcg_set_rate_mnd(priv->base, &uart2_regs, 1, 192, 15625,
+ clk_rcg_set_rate_mnd(priv->base, BLSP2_UART2_APPS_CMD_RCGR, 1, 192, 15625,
CFG_CLK_SRC_GPLL0, 16);
/* Vote for gpll0 clock */
diff --git a/drivers/clk/qcom/clock-qcom.c b/drivers/clk/qcom/clock-qcom.c
index 7c683e5..05e5ab7 100644
--- a/drivers/clk/qcom/clock-qcom.c
+++ b/drivers/clk/qcom/clock-qcom.c
@@ -22,7 +22,9 @@
#include <linux/bug.h>
#include <linux/delay.h>
#include <linux/bitops.h>
+#include <linux/iopoll.h>
#include <reset-uclass.h>
+#include <power-domain-uclass.h>
#include "clock-qcom.h"
@@ -30,6 +32,13 @@
#define CBCR_BRANCH_ENABLE_BIT BIT(0)
#define CBCR_BRANCH_OFF_BIT BIT(31)
+#define GDSC_SW_COLLAPSE_MASK BIT(0)
+#define GDSC_POWER_DOWN_COMPLETE BIT(15)
+#define GDSC_POWER_UP_COMPLETE BIT(16)
+#define GDSC_PWR_ON_MASK BIT(31)
+#define CFG_GDSCR_OFFSET 0x4
+#define GDSC_STATUS_POLL_TIMEOUT_US 1500
+
/* Enable clock controlled by CBC soft macro */
void clk_enable_cbc(phys_addr_t cbcr)
{
@@ -95,7 +104,7 @@
* root set rate for clocks with half integer and MND divider
* div should be pre-calculated ((div * 2) - 1)
*/
-void clk_rcg_set_rate_mnd(phys_addr_t base, const struct bcr_regs *regs,
+void clk_rcg_set_rate_mnd(phys_addr_t base, uint32_t cmd_rcgr,
int div, int m, int n, int source, u8 mnd_width)
{
u32 cfg;
@@ -111,13 +120,14 @@
debug("m %#x n %#x d %#x div %#x mask %#x\n", m_val, n_val, d_val, div, mask);
/* Program MND values */
- writel(m_val & mask, base + regs->M);
- writel(n_val & mask, base + regs->N);
- writel(d_val & mask, base + regs->D);
+ writel(m_val & mask, base + cmd_rcgr + RCG_M_REG);
+ writel(n_val & mask, base + cmd_rcgr + RCG_N_REG);
+ writel(d_val & mask, base + cmd_rcgr + RCG_D_REG);
/* setup src select and divider */
- cfg = readl(base + regs->cfg_rcgr);
- cfg &= ~(CFG_SRC_SEL_MASK | CFG_MODE_MASK | CFG_HW_CLK_CTRL_MASK);
+ cfg = readl(base + cmd_rcgr + RCG_CFG_REG);
+ cfg &= ~(CFG_SRC_SEL_MASK | CFG_MODE_MASK | CFG_HW_CLK_CTRL_MASK |
+ CFG_SRC_DIV_MASK);
cfg |= source & CFG_SRC_SEL_MASK; /* Select clock source */
if (div)
@@ -126,20 +136,20 @@
if (n && n != m)
cfg |= CFG_MODE_DUAL_EDGE;
- writel(cfg, base + regs->cfg_rcgr); /* Write new clock configuration */
+ writel(cfg, base + cmd_rcgr + RCG_CFG_REG); /* Write new clock configuration */
/* Inform h/w to start using the new config. */
- clk_bcr_update(base + regs->cmd_rcgr);
+ clk_bcr_update(base + cmd_rcgr);
}
/* root set rate for clocks with half integer and mnd_width=0 */
-void clk_rcg_set_rate(phys_addr_t base, const struct bcr_regs *regs, int div,
+void clk_rcg_set_rate(phys_addr_t base, uint32_t cmd_rcgr, int div,
int source)
{
u32 cfg;
/* setup src select and divider */
- cfg = readl(base + regs->cfg_rcgr);
+ cfg = readl(base + cmd_rcgr + RCG_CFG_REG);
cfg &= ~(CFG_SRC_SEL_MASK | CFG_MODE_MASK | CFG_HW_CLK_CTRL_MASK);
cfg |= source & CFG_CLK_SRC_MASK; /* Select clock source */
@@ -150,10 +160,10 @@
if (div)
cfg |= (2 * div - 1) & CFG_SRC_DIV_MASK;
- writel(cfg, base + regs->cfg_rcgr); /* Write new clock configuration */
+ writel(cfg, base + cmd_rcgr + RCG_CFG_REG); /* Write new clock configuration */
/* Inform h/w to start using the new config. */
- clk_bcr_update(base + regs->cmd_rcgr);
+ clk_bcr_update(base + cmd_rcgr);
}
const struct freq_tbl *qcom_find_freq(const struct freq_tbl *f, uint rate)
@@ -217,12 +227,13 @@
.ops = &msm_clk_ops,
.priv_auto = sizeof(struct msm_clk_priv),
.probe = msm_clk_probe,
+ .flags = DM_FLAG_PRE_RELOC | DM_FLAG_DEFAULT_PD_CTRL_OFF,
};
int qcom_cc_bind(struct udevice *parent)
{
struct msm_clk_data *data = (struct msm_clk_data *)dev_get_driver_data(parent);
- struct udevice *clkdev, *rstdev;
+ struct udevice *clkdev = NULL, *rstdev = NULL, *pwrdev;
struct driver *drv;
int ret;
@@ -237,20 +248,41 @@
if (ret)
return ret;
- /* Bail out early if resets are not specified for this platform */
- if (!data->resets)
- return ret;
+ if (data->resets) {
+ /* Get a handle to the common reset handler */
+ drv = lists_driver_lookup_name("qcom_reset");
+ if (!drv) {
+ ret = -ENOENT;
+ goto unbind_clkdev;
+ }
- /* Get a handle to the common reset handler */
- drv = lists_driver_lookup_name("qcom_reset");
- if (!drv)
- return -ENOENT;
+ /* Register the reset controller */
+ ret = device_bind_with_driver_data(parent, drv, "qcom_reset", (ulong)data,
+ dev_ofnode(parent), &rstdev);
+ if (ret)
+ goto unbind_clkdev;
+ }
- /* Register the reset controller */
- ret = device_bind_with_driver_data(parent, drv, "qcom_reset", (ulong)data,
- dev_ofnode(parent), &rstdev);
- if (ret)
- device_unbind(clkdev);
+ if (data->power_domains) {
+ /* Get a handle to the common power domain handler */
+ drv = lists_driver_lookup_name("qcom_power");
+ if (!drv) {
+ ret = -ENOENT;
+ goto unbind_rstdev;
+ }
+ /* Register the power domain controller */
+ ret = device_bind_with_driver_data(parent, drv, "qcom_power", (ulong)data,
+ dev_ofnode(parent), &pwrdev);
+ if (ret)
+ goto unbind_rstdev;
+ }
+
+ return 0;
+
+unbind_rstdev:
+ device_unbind(rstdev);
+unbind_clkdev:
+ device_unbind(clkdev);
return ret;
}
@@ -305,3 +337,80 @@
.ops = &qcom_reset_ops,
.probe = qcom_reset_probe,
};
+
+static int qcom_power_set(struct power_domain *pwr, bool on)
+{
+ struct msm_clk_data *data = (struct msm_clk_data *)dev_get_driver_data(pwr->dev);
+ void __iomem *base = dev_get_priv(pwr->dev);
+ const struct qcom_power_map *map;
+ u32 value;
+ int ret;
+
+ if (pwr->id >= data->num_power_domains)
+ return -ENODEV;
+
+ map = &data->power_domains[pwr->id];
+
+ if (!map->reg)
+ return -ENODEV;
+
+ value = readl(base + map->reg);
+
+ if (on)
+ value &= ~GDSC_SW_COLLAPSE_MASK;
+ else
+ value |= GDSC_SW_COLLAPSE_MASK;
+
+ writel(value, base + map->reg);
+
+ if (on)
+ ret = readl_poll_timeout(base + map->reg + CFG_GDSCR_OFFSET,
+ value,
+ (value & GDSC_POWER_UP_COMPLETE) ||
+ (value & GDSC_PWR_ON_MASK),
+ GDSC_STATUS_POLL_TIMEOUT_US);
+
+ else
+ ret = readl_poll_timeout(base + map->reg + CFG_GDSCR_OFFSET,
+ value,
+ (value & GDSC_POWER_DOWN_COMPLETE) ||
+ !(value & GDSC_PWR_ON_MASK),
+ GDSC_STATUS_POLL_TIMEOUT_US);
+
+
+ if (ret == -ETIMEDOUT)
+ printf("WARNING: GDSC %lu is stuck during power on/off\n",
+ pwr->id);
+ return ret;
+}
+
+static int qcom_power_on(struct power_domain *pwr)
+{
+ return qcom_power_set(pwr, true);
+}
+
+static int qcom_power_off(struct power_domain *pwr)
+{
+ return qcom_power_set(pwr, false);
+}
+
+static const struct power_domain_ops qcom_power_ops = {
+ .on = qcom_power_on,
+ .off = qcom_power_off,
+};
+
+static int qcom_power_probe(struct udevice *dev)
+{
+ /* Set our priv pointer to the base address */
+ dev_set_priv(dev, (void *)dev_read_addr(dev));
+
+ return 0;
+}
+
+U_BOOT_DRIVER(qcom_power) = {
+ .name = "qcom_power",
+ .id = UCLASS_POWER_DOMAIN,
+ .ops = &qcom_power_ops,
+ .probe = qcom_power_probe,
+ .flags = DM_FLAG_PRE_RELOC,
+};
diff --git a/drivers/clk/qcom/clock-qcom.h b/drivers/clk/qcom/clock-qcom.h
index 01088c1..a7f833a 100644
--- a/drivers/clk/qcom/clock-qcom.h
+++ b/drivers/clk/qcom/clock-qcom.h
@@ -12,6 +12,11 @@
#define CFG_CLK_SRC_GPLL0_EVEN (6 << 8)
#define CFG_CLK_SRC_MASK (7 << 8)
+#define RCG_CFG_REG 0x4
+#define RCG_M_REG 0x8
+#define RCG_N_REG 0xc
+#define RCG_D_REG 0x10
+
struct pll_vote_clk {
uintptr_t status;
int status_bit;
@@ -24,13 +29,6 @@
uintptr_t ena_vote;
int vote_bit;
};
-struct bcr_regs {
- uintptr_t cfg_rcgr;
- uintptr_t cmd_rcgr;
- uintptr_t M;
- uintptr_t N;
- uintptr_t D;
-};
struct freq_tbl {
uint freq;
@@ -59,9 +57,15 @@
u8 bit;
};
+struct qcom_power_map {
+ unsigned int reg;
+};
+
struct clk;
struct msm_clk_data {
+ const struct qcom_power_map *power_domains;
+ unsigned long num_power_domains;
const struct qcom_reset_map *resets;
unsigned long num_resets;
const struct gate_clk *clks;
@@ -82,9 +86,9 @@
void clk_enable_cbc(phys_addr_t cbcr);
void clk_enable_vote_clk(phys_addr_t base, const struct vote_clk *vclk);
const struct freq_tbl *qcom_find_freq(const struct freq_tbl *f, uint rate);
-void clk_rcg_set_rate_mnd(phys_addr_t base, const struct bcr_regs *regs,
+void clk_rcg_set_rate_mnd(phys_addr_t base, uint32_t cmd_rcgr,
int div, int m, int n, int source, u8 mnd_width);
-void clk_rcg_set_rate(phys_addr_t base, const struct bcr_regs *regs, int div,
+void clk_rcg_set_rate(phys_addr_t base, uint32_t cmd_rcgr, int div,
int source);
static inline void qcom_gate_clk_en(const struct msm_clk_priv *priv, unsigned long id)
diff --git a/drivers/clk/qcom/clock-qcs404.c b/drivers/clk/qcom/clock-qcs404.c
index 958312b..8a897a5 100644
--- a/drivers/clk/qcom/clock-qcs404.c
+++ b/drivers/clk/qcom/clock-qcs404.c
@@ -28,35 +28,22 @@
#define BLSP1_UART2_BCR (0x3028)
#define BLSP1_UART2_APPS_CBCR (0x302C)
#define BLSP1_UART2_APPS_CMD_RCGR (0x3034)
-#define BLSP1_UART2_APPS_CFG_RCGR (0x3038)
-#define BLSP1_UART2_APPS_M (0x303C)
-#define BLSP1_UART2_APPS_N (0x3040)
-#define BLSP1_UART2_APPS_D (0x3044)
/* I2C controller clock control registerss */
#define BLSP1_QUP0_I2C_APPS_CBCR (0x6028)
#define BLSP1_QUP0_I2C_APPS_CMD_RCGR (0x602C)
-#define BLSP1_QUP0_I2C_APPS_CFG_RCGR (0x6030)
#define BLSP1_QUP1_I2C_APPS_CBCR (0x2008)
#define BLSP1_QUP1_I2C_APPS_CMD_RCGR (0x200C)
-#define BLSP1_QUP1_I2C_APPS_CFG_RCGR (0x2010)
#define BLSP1_QUP2_I2C_APPS_CBCR (0x3010)
#define BLSP1_QUP2_I2C_APPS_CMD_RCGR (0x3000)
-#define BLSP1_QUP2_I2C_APPS_CFG_RCGR (0x3004)
#define BLSP1_QUP3_I2C_APPS_CBCR (0x4020)
#define BLSP1_QUP3_I2C_APPS_CMD_RCGR (0x4000)
-#define BLSP1_QUP3_I2C_APPS_CFG_RCGR (0x4004)
#define BLSP1_QUP4_I2C_APPS_CBCR (0x5020)
#define BLSP1_QUP4_I2C_APPS_CMD_RCGR (0x5000)
-#define BLSP1_QUP4_I2C_APPS_CFG_RCGR (0x5004)
/* SD controller clock control registers */
#define SDCC_BCR(n) (((n) * 0x1000) + 0x41000)
-#define SDCC_CMD_RCGR(n) (((n) * 0x1000) + 0x41004)
-#define SDCC_CFG_RCGR(n) (((n) * 0x1000) + 0x41008)
-#define SDCC_M(n) (((n) * 0x1000) + 0x4100C)
-#define SDCC_N(n) (((n) * 0x1000) + 0x41010)
-#define SDCC_D(n) (((n) * 0x1000) + 0x41014)
+#define SDCC_CMD_RCGR(n) (((n + 1) * 0x1000) + 0x41004)
#define SDCC_APPS_CBCR(n) (((n) * 0x1000) + 0x41018)
#define SDCC_AHB_CBCR(n) (((n) * 0x1000) + 0x4101C)
@@ -70,10 +57,6 @@
#define USB30_MOCK_UTMI_CMD_RCGR (0x3901C)
#define USB30_MOCK_UTMI_CFG_RCGR (0x39020)
#define USB30_MASTER_CMD_RCGR (0x39028)
-#define USB30_MASTER_CFG_RCGR (0x3902C)
-#define USB30_MASTER_M (0x39030)
-#define USB30_MASTER_N (0x39034)
-#define USB30_MASTER_D (0x39038)
#define USB2A_PHY_SLEEP_CBCR (0x4102C)
#define USB_HS_PHY_CFG_AHB_CBCR (0x41030)
@@ -83,12 +66,7 @@
#define ETH_SLAVE_AHB_CBCR (0x4e00c)
#define ETH_AXI_CBCR (0x4e010)
#define EMAC_PTP_CMD_RCGR (0x4e014)
-#define EMAC_PTP_CFG_RCGR (0x4e018)
#define EMAC_CMD_RCGR (0x4e01c)
-#define EMAC_CFG_RCGR (0x4e020)
-#define EMAC_M (0x4e024)
-#define EMAC_N (0x4e028)
-#define EMAC_D (0x4e02c)
/* GPLL0 clock control registers */
@@ -103,22 +81,6 @@
.vote_bit = BIT(10) | BIT(5) | BIT(4),
};
-static const struct bcr_regs uart2_regs = {
- .cfg_rcgr = BLSP1_UART2_APPS_CFG_RCGR,
- .cmd_rcgr = BLSP1_UART2_APPS_CMD_RCGR,
- .M = BLSP1_UART2_APPS_M,
- .N = BLSP1_UART2_APPS_N,
- .D = BLSP1_UART2_APPS_D,
-};
-
-static const struct bcr_regs sdc_regs = {
- .cfg_rcgr = SDCC_CFG_RCGR(1),
- .cmd_rcgr = SDCC_CMD_RCGR(1),
- .M = SDCC_M(1),
- .N = SDCC_N(1),
- .D = SDCC_D(1),
-};
-
static struct pll_vote_clk gpll0_vote_clk = {
.status = GPLL0_STATUS,
.status_bit = GPLL0_STATUS_ACTIVE,
@@ -133,60 +95,6 @@
.vote_bit = BIT(1),
};
-static const struct bcr_regs usb30_master_regs = {
- .cfg_rcgr = USB30_MASTER_CFG_RCGR,
- .cmd_rcgr = USB30_MASTER_CMD_RCGR,
- .M = USB30_MASTER_M,
- .N = USB30_MASTER_N,
- .D = USB30_MASTER_D,
-};
-
-static const struct bcr_regs emac_regs = {
- .cfg_rcgr = EMAC_CFG_RCGR,
- .cmd_rcgr = EMAC_CMD_RCGR,
- .M = EMAC_M,
- .N = EMAC_N,
- .D = EMAC_D,
-};
-
-static const struct bcr_regs emac_ptp_regs = {
- .cfg_rcgr = EMAC_PTP_CFG_RCGR,
- .cmd_rcgr = EMAC_PTP_CMD_RCGR,
- .M = EMAC_M,
- .N = EMAC_N,
- .D = EMAC_D,
-};
-
-static const struct bcr_regs blsp1_qup0_i2c_apps_regs = {
- .cmd_rcgr = BLSP1_QUP0_I2C_APPS_CMD_RCGR,
- .cfg_rcgr = BLSP1_QUP0_I2C_APPS_CFG_RCGR,
- /* mnd_width = 0 */
-};
-
-static const struct bcr_regs blsp1_qup1_i2c_apps_regs = {
- .cmd_rcgr = BLSP1_QUP1_I2C_APPS_CMD_RCGR,
- .cfg_rcgr = BLSP1_QUP1_I2C_APPS_CFG_RCGR,
- /* mnd_width = 0 */
-};
-
-static const struct bcr_regs blsp1_qup2_i2c_apps_regs = {
- .cmd_rcgr = BLSP1_QUP2_I2C_APPS_CMD_RCGR,
- .cfg_rcgr = BLSP1_QUP2_I2C_APPS_CFG_RCGR,
- /* mnd_width = 0 */
-};
-
-static const struct bcr_regs blsp1_qup3_i2c_apps_regs = {
- .cmd_rcgr = BLSP1_QUP3_I2C_APPS_CMD_RCGR,
- .cfg_rcgr = BLSP1_QUP3_I2C_APPS_CFG_RCGR,
- /* mnd_width = 0 */
-};
-
-static const struct bcr_regs blsp1_qup4_i2c_apps_regs = {
- .cmd_rcgr = BLSP1_QUP4_I2C_APPS_CMD_RCGR,
- .cfg_rcgr = BLSP1_QUP4_I2C_APPS_CFG_RCGR,
- /* mnd_width = 0 */
-};
-
static ulong qcs404_clk_set_rate(struct clk *clk, ulong rate)
{
struct msm_clk_priv *priv = dev_get_priv(clk->dev);
@@ -194,29 +102,29 @@
switch (clk->id) {
case GCC_BLSP1_UART2_APPS_CLK:
/* UART: 1843200Hz for a fixed 115200 baudrate (19200000 * (12/125)) */
- clk_rcg_set_rate_mnd(priv->base, &uart2_regs, 0, 12, 125,
+ clk_rcg_set_rate_mnd(priv->base, BLSP1_UART2_APPS_CMD_RCGR, 0, 12, 125,
CFG_CLK_SRC_CXO, 16);
clk_enable_cbc(priv->base + BLSP1_UART2_APPS_CBCR);
return 1843200;
case GCC_SDCC1_APPS_CLK:
/* SDCC1: 200MHz */
- clk_rcg_set_rate_mnd(priv->base, &sdc_regs, 7, 0, 0,
+ clk_rcg_set_rate_mnd(priv->base, SDCC_CMD_RCGR(0), 7, 0, 0,
CFG_CLK_SRC_GPLL0, 8);
clk_enable_gpll0(priv->base, &gpll0_vote_clk);
clk_enable_cbc(priv->base + SDCC_APPS_CBCR(1));
return rate;
case GCC_ETH_RGMII_CLK:
if (rate == 250000000)
- clk_rcg_set_rate_mnd(priv->base, &emac_regs, 3, 0, 0,
+ clk_rcg_set_rate_mnd(priv->base, EMAC_CMD_RCGR, 3, 0, 0,
CFG_CLK_SRC_GPLL1, 8);
else if (rate == 125000000)
- clk_rcg_set_rate_mnd(priv->base, &emac_regs, 7, 0, 0,
+ clk_rcg_set_rate_mnd(priv->base, EMAC_CMD_RCGR, 7, 0, 0,
CFG_CLK_SRC_GPLL1, 8);
else if (rate == 50000000)
- clk_rcg_set_rate_mnd(priv->base, &emac_regs, 19, 0, 0,
+ clk_rcg_set_rate_mnd(priv->base, EMAC_CMD_RCGR, 19, 0, 0,
CFG_CLK_SRC_GPLL1, 8);
else if (rate == 5000000)
- clk_rcg_set_rate_mnd(priv->base, &emac_regs, 3, 1, 50,
+ clk_rcg_set_rate_mnd(priv->base, EMAC_CMD_RCGR, 3, 1, 50,
CFG_CLK_SRC_GPLL1, 8);
return rate;
}
@@ -237,7 +145,7 @@
switch (clk->id) {
case GCC_USB30_MASTER_CLK:
clk_enable_cbc(priv->base + USB30_MASTER_CBCR);
- clk_rcg_set_rate_mnd(priv->base, &usb30_master_regs, 7, 0, 0,
+ clk_rcg_set_rate_mnd(priv->base, USB30_MASTER_CMD_RCGR, 7, 0, 0,
CFG_CLK_SRC_GPLL0, 8);
break;
case GCC_SYS_NOC_USB3_CLK:
@@ -259,14 +167,14 @@
/* SPEED_1000: freq -> 250MHz */
clk_enable_cbc(priv->base + ETH_PTP_CBCR);
clk_enable_gpll0(priv->base, &gpll1_vote_clk);
- clk_rcg_set_rate_mnd(priv->base, &emac_ptp_regs, 3, 0, 0,
+ clk_rcg_set_rate_mnd(priv->base, EMAC_PTP_CMD_RCGR, 3, 0, 0,
CFG_CLK_SRC_GPLL1, 8);
break;
case GCC_ETH_RGMII_CLK:
/* SPEED_1000: freq -> 250MHz */
clk_enable_cbc(priv->base + ETH_RGMII_CBCR);
clk_enable_gpll0(priv->base, &gpll1_vote_clk);
- clk_rcg_set_rate_mnd(priv->base, &emac_regs, 3, 0, 0,
+ clk_rcg_set_rate_mnd(priv->base, EMAC_CMD_RCGR, 3, 0, 0,
CFG_CLK_SRC_GPLL1, 8);
break;
case GCC_ETH_SLAVE_AHB_CLK:
@@ -280,27 +188,27 @@
break;
case GCC_BLSP1_QUP0_I2C_APPS_CLK:
clk_enable_cbc(priv->base + BLSP1_QUP0_I2C_APPS_CBCR);
- clk_rcg_set_rate(priv->base, &blsp1_qup0_i2c_apps_regs, 0,
+ clk_rcg_set_rate(priv->base, BLSP1_QUP0_I2C_APPS_CMD_RCGR, 0,
CFG_CLK_SRC_CXO);
break;
case GCC_BLSP1_QUP1_I2C_APPS_CLK:
clk_enable_cbc(priv->base + BLSP1_QUP1_I2C_APPS_CBCR);
- clk_rcg_set_rate(priv->base, &blsp1_qup1_i2c_apps_regs, 0,
+ clk_rcg_set_rate(priv->base, BLSP1_QUP1_I2C_APPS_CMD_RCGR, 0,
CFG_CLK_SRC_CXO);
break;
case GCC_BLSP1_QUP2_I2C_APPS_CLK:
clk_enable_cbc(priv->base + BLSP1_QUP2_I2C_APPS_CBCR);
- clk_rcg_set_rate(priv->base, &blsp1_qup2_i2c_apps_regs, 0,
+ clk_rcg_set_rate(priv->base, BLSP1_QUP2_I2C_APPS_CMD_RCGR, 0,
CFG_CLK_SRC_CXO);
break;
case GCC_BLSP1_QUP3_I2C_APPS_CLK:
clk_enable_cbc(priv->base + BLSP1_QUP3_I2C_APPS_CBCR);
- clk_rcg_set_rate(priv->base, &blsp1_qup3_i2c_apps_regs, 0,
+ clk_rcg_set_rate(priv->base, BLSP1_QUP3_I2C_APPS_CMD_RCGR, 0,
CFG_CLK_SRC_CXO);
break;
case GCC_BLSP1_QUP4_I2C_APPS_CLK:
clk_enable_cbc(priv->base + BLSP1_QUP4_I2C_APPS_CBCR);
- clk_rcg_set_rate(priv->base, &blsp1_qup4_i2c_apps_regs, 0,
+ clk_rcg_set_rate(priv->base, BLSP1_QUP4_I2C_APPS_CMD_RCGR, 0,
CFG_CLK_SRC_CXO);
break;
case GCC_SDCC1_AHB_CLK:
diff --git a/drivers/clk/qcom/clock-sdm845.c b/drivers/clk/qcom/clock-sdm845.c
index 36ffee7..e9c61eb 100644
--- a/drivers/clk/qcom/clock-sdm845.c
+++ b/drivers/clk/qcom/clock-sdm845.c
@@ -19,13 +19,11 @@
#include "clock-qcom.h"
-#define SE9_AHB_CBCR 0x25004
-#define SE9_UART_APPS_CBCR 0x29004
#define SE9_UART_APPS_CMD_RCGR 0x18148
-#define SE9_UART_APPS_CFG_RCGR 0x1814C
-#define SE9_UART_APPS_M 0x18150
-#define SE9_UART_APPS_N 0x18154
-#define SE9_UART_APPS_D 0x18158
+
+#define USB30_PRIM_MASTER_CLK_CMD_RCGR 0xf018
+#define USB30_PRIM_MOCK_UTMI_CLK_CMD_RCGR 0xf030
+#define USB3_PRIM_PHY_AUX_CMD_RCGR 0xf05c
static const struct freq_tbl ftbl_gcc_qupv3_wrap0_s0_clk_src[] = {
F(7372800, CFG_CLK_SRC_GPLL0_EVEN, 1, 384, 15625),
@@ -46,14 +44,6 @@
{ }
};
-static const struct bcr_regs uart2_regs = {
- .cfg_rcgr = SE9_UART_APPS_CFG_RCGR,
- .cmd_rcgr = SE9_UART_APPS_CMD_RCGR,
- .M = SE9_UART_APPS_M,
- .N = SE9_UART_APPS_N,
- .D = SE9_UART_APPS_D,
-};
-
static ulong sdm845_clk_set_rate(struct clk *clk, ulong rate)
{
struct msm_clk_priv *priv = dev_get_priv(clk->dev);
@@ -62,7 +52,7 @@
switch (clk->id) {
case GCC_QUPV3_WRAP1_S1_CLK: /* UART9 */
freq = qcom_find_freq(ftbl_gcc_qupv3_wrap0_s0_clk_src, rate);
- clk_rcg_set_rate_mnd(priv->base, &uart2_regs,
+ clk_rcg_set_rate_mnd(priv->base, SE9_UART_APPS_CMD_RCGR,
freq->pre_div, freq->m, freq->n, freq->src, 16);
return freq->freq;
default:
@@ -71,6 +61,8 @@
}
static const struct gate_clk sdm845_clks[] = {
+ GATE_CLK(GCC_AGGRE_USB3_SEC_AXI_CLK, 0x82020, 0x00000001),
+ GATE_CLK(GCC_CFG_NOC_USB3_SEC_AXI_CLK, 0x05030, 0x00000001),
GATE_CLK(GCC_QUPV3_WRAP0_S0_CLK, 0x5200c, 0x00000400),
GATE_CLK(GCC_QUPV3_WRAP0_S1_CLK, 0x5200c, 0x00000800),
GATE_CLK(GCC_QUPV3_WRAP0_S2_CLK, 0x5200c, 0x00001000),
@@ -135,6 +127,25 @@
debug("%s: clk %s\n", __func__, sdm845_clks[clk->id].name);
+ switch (clk->id) {
+ case GCC_USB30_PRIM_MASTER_CLK:
+ qcom_gate_clk_en(priv, GCC_USB_PHY_CFG_AHB2PHY_CLK);
+ /* These numbers are just pulled from the frequency tables in the Linux driver */
+ clk_rcg_set_rate_mnd(priv->base, USB30_PRIM_MASTER_CLK_CMD_RCGR,
+ (4.5 * 2) - 1, 0, 0, 1 << 8, 8);
+ clk_rcg_set_rate_mnd(priv->base, USB30_PRIM_MOCK_UTMI_CLK_CMD_RCGR,
+ 1, 0, 0, 0, 8);
+ clk_rcg_set_rate_mnd(priv->base, USB3_PRIM_PHY_AUX_CMD_RCGR,
+ 1, 0, 0, 0, 8);
+ break;
+ case GCC_USB30_SEC_MASTER_CLK:
+ qcom_gate_clk_en(priv, GCC_USB3_SEC_PHY_AUX_CLK);
+
+ qcom_gate_clk_en(priv, GCC_USB3_SEC_CLKREF_CLK);
+ qcom_gate_clk_en(priv, GCC_USB3_SEC_PHY_COM_AUX_CLK);
+ break;
+ }
+
qcom_gate_clk_en(priv, clk->id);
return 0;
@@ -160,11 +171,29 @@
[GCC_USB_PHY_CFG_AHB2PHY_BCR] = { 0x6a000 },
};
+static const struct qcom_power_map sdm845_gdscs[] = {
+ [PCIE_0_GDSC] = { 0x6b004 },
+ [PCIE_1_GDSC] = { 0x8d004 },
+ [UFS_CARD_GDSC] = { 0x75004 },
+ [UFS_PHY_GDSC] = { 0x77004 },
+ [USB30_PRIM_GDSC] = { 0xf004 },
+ [USB30_SEC_GDSC] = { 0x10004 },
+ [HLOS1_VOTE_AGGRE_NOC_MMU_AUDIO_TBU_GDSC] = { 0x7d030 },
+ [HLOS1_VOTE_AGGRE_NOC_MMU_PCIE_TBU_GDSC] = { 0x7d03c },
+ [HLOS1_VOTE_AGGRE_NOC_MMU_TBU1_GDSC] = { 0x7d034 },
+ [HLOS1_VOTE_AGGRE_NOC_MMU_TBU2_GDSC] = { 0x7d038 },
+ [HLOS1_VOTE_MMNOC_MMU_TBU_HF0_GDSC] = { 0x7d040 },
+ [HLOS1_VOTE_MMNOC_MMU_TBU_HF1_GDSC] = { 0x7d048 },
+ [HLOS1_VOTE_MMNOC_MMU_TBU_SF_GDSC] = { 0x7d044 },
+};
+
static struct msm_clk_data sdm845_clk_data = {
.resets = sdm845_gcc_resets,
.num_resets = ARRAY_SIZE(sdm845_gcc_resets),
.clks = sdm845_clks,
.num_clks = ARRAY_SIZE(sdm845_clks),
+ .power_domains = sdm845_gdscs,
+ .num_power_domains = ARRAY_SIZE(sdm845_gdscs),
.enable = sdm845_clk_enable,
.set_rate = sdm845_clk_set_rate,
@@ -183,5 +212,5 @@
.id = UCLASS_NOP,
.of_match = gcc_sdm845_of_match,
.bind = qcom_cc_bind,
- .flags = DM_FLAG_PRE_RELOC,
+ .flags = DM_FLAG_PRE_RELOC | DM_FLAG_DEFAULT_PD_CTRL_OFF,
};
diff --git a/drivers/clk/rockchip/clk_pll.c b/drivers/clk/rockchip/clk_pll.c
index 1bb31b3..66f8bb1 100644
--- a/drivers/clk/rockchip/clk_pll.c
+++ b/drivers/clk/rockchip/clk_pll.c
@@ -8,7 +8,6 @@
#include <dm.h>
#include <errno.h>
#include <log.h>
-#include <asm/io.h>
#include <asm/arch-rockchip/clock.h>
#include <asm/arch-rockchip/hardware.h>
#include <div64.h>
diff --git a/drivers/clk/rockchip/clk_px30.c b/drivers/clk/rockchip/clk_px30.c
index 93b7653..2875c15 100644
--- a/drivers/clk/rockchip/clk_px30.c
+++ b/drivers/clk/rockchip/clk_px30.c
@@ -15,7 +15,6 @@
#include <asm/arch-rockchip/cru_px30.h>
#include <asm/arch-rockchip/hardware.h>
#include <asm/global_data.h>
-#include <asm/io.h>
#include <dm/device-internal.h>
#include <dm/lists.h>
#include <dt-bindings/clock/px30-cru.h>
diff --git a/drivers/clk/rockchip/clk_rk3036.c b/drivers/clk/rockchip/clk_rk3036.c
index 6bc6d41..6238b14 100644
--- a/drivers/clk/rockchip/clk_rk3036.c
+++ b/drivers/clk/rockchip/clk_rk3036.c
@@ -10,7 +10,6 @@
#include <log.h>
#include <malloc.h>
#include <syscon.h>
-#include <asm/io.h>
#include <asm/arch-rockchip/clock.h>
#include <asm/arch-rockchip/cru_rk3036.h>
#include <asm/arch-rockchip/hardware.h>
diff --git a/drivers/clk/rockchip/clk_rk3066.c b/drivers/clk/rockchip/clk_rk3066.c
index 2c12f6e..f83335d 100644
--- a/drivers/clk/rockchip/clk_rk3066.c
+++ b/drivers/clk/rockchip/clk_rk3066.c
@@ -14,7 +14,6 @@
#include <malloc.h>
#include <mapmem.h>
#include <syscon.h>
-#include <asm/io.h>
#include <asm/arch-rockchip/clock.h>
#include <asm/arch-rockchip/cru_rk3066.h>
#include <asm/arch-rockchip/grf_rk3066.h>
diff --git a/drivers/clk/rockchip/clk_rk3128.c b/drivers/clk/rockchip/clk_rk3128.c
index 13e176c..182754e 100644
--- a/drivers/clk/rockchip/clk_rk3128.c
+++ b/drivers/clk/rockchip/clk_rk3128.c
@@ -10,7 +10,6 @@
#include <log.h>
#include <malloc.h>
#include <syscon.h>
-#include <asm/io.h>
#include <asm/arch-rockchip/clock.h>
#include <asm/arch-rockchip/cru_rk3128.h>
#include <asm/arch-rockchip/hardware.h>
diff --git a/drivers/clk/rockchip/clk_rk3188.c b/drivers/clk/rockchip/clk_rk3188.c
index ebdd1b3..f98b46a 100644
--- a/drivers/clk/rockchip/clk_rk3188.c
+++ b/drivers/clk/rockchip/clk_rk3188.c
@@ -13,7 +13,6 @@
#include <malloc.h>
#include <mapmem.h>
#include <syscon.h>
-#include <asm/io.h>
#include <asm/arch-rockchip/clock.h>
#include <asm/arch-rockchip/cru_rk3188.h>
#include <asm/arch-rockchip/grf_rk3188.h>
diff --git a/drivers/clk/rockchip/clk_rk322x.c b/drivers/clk/rockchip/clk_rk322x.c
index 28cdba7..9371c4f 100644
--- a/drivers/clk/rockchip/clk_rk322x.c
+++ b/drivers/clk/rockchip/clk_rk322x.c
@@ -10,7 +10,6 @@
#include <log.h>
#include <malloc.h>
#include <syscon.h>
-#include <asm/io.h>
#include <asm/arch-rockchip/clock.h>
#include <asm/arch-rockchip/cru_rk322x.h>
#include <asm/arch-rockchip/hardware.h>
diff --git a/drivers/clk/rockchip/clk_rk3288.c b/drivers/clk/rockchip/clk_rk3288.c
index e24c32c..0b7eefa 100644
--- a/drivers/clk/rockchip/clk_rk3288.c
+++ b/drivers/clk/rockchip/clk_rk3288.c
@@ -15,7 +15,6 @@
#include <mapmem.h>
#include <syscon.h>
#include <asm/global_data.h>
-#include <asm/io.h>
#include <asm/arch-rockchip/clock.h>
#include <asm/arch-rockchip/cru.h>
#include <asm/arch-rockchip/grf_rk3288.h>
diff --git a/drivers/clk/rockchip/clk_rk3308.c b/drivers/clk/rockchip/clk_rk3308.c
index d0a3f65..7755b01 100644
--- a/drivers/clk/rockchip/clk_rk3308.c
+++ b/drivers/clk/rockchip/clk_rk3308.c
@@ -12,7 +12,6 @@
#include <malloc.h>
#include <syscon.h>
#include <asm/global_data.h>
-#include <asm/io.h>
#include <asm/arch/cru_rk3308.h>
#include <asm/arch-rockchip/clock.h>
#include <asm/arch-rockchip/hardware.h>
diff --git a/drivers/clk/rockchip/clk_rk3328.c b/drivers/clk/rockchip/clk_rk3328.c
index ef97381..cfec1d9 100644
--- a/drivers/clk/rockchip/clk_rk3328.c
+++ b/drivers/clk/rockchip/clk_rk3328.c
@@ -15,7 +15,6 @@
#include <asm/arch-rockchip/cru_rk3328.h>
#include <asm/arch-rockchip/hardware.h>
#include <asm/arch-rockchip/grf_rk3328.h>
-#include <asm/io.h>
#include <dm/device-internal.h>
#include <dm/lists.h>
#include <dt-bindings/clock/rk3328-cru.h>
diff --git a/drivers/clk/rockchip/clk_rk3368.c b/drivers/clk/rockchip/clk_rk3368.c
index 3406ff5..1c5dfaa 100644
--- a/drivers/clk/rockchip/clk_rk3368.c
+++ b/drivers/clk/rockchip/clk_rk3368.c
@@ -18,7 +18,6 @@
#include <asm/arch-rockchip/clock.h>
#include <asm/arch-rockchip/cru_rk3368.h>
#include <asm/arch-rockchip/hardware.h>
-#include <asm/io.h>
#include <dm/device-internal.h>
#include <dm/lists.h>
#include <dt-bindings/clock/rk3368-cru.h>
diff --git a/drivers/clk/rockchip/clk_rk3399.c b/drivers/clk/rockchip/clk_rk3399.c
index c37e8a5..80f65a2 100644
--- a/drivers/clk/rockchip/clk_rk3399.c
+++ b/drivers/clk/rockchip/clk_rk3399.c
@@ -14,7 +14,6 @@
#include <mapmem.h>
#include <syscon.h>
#include <bitfield.h>
-#include <asm/io.h>
#include <asm/arch-rockchip/clock.h>
#include <asm/arch-rockchip/cru.h>
#include <asm/arch-rockchip/hardware.h>
diff --git a/drivers/clk/rockchip/clk_rk3568.c b/drivers/clk/rockchip/clk_rk3568.c
index 68f5bbb..57ef27d 100644
--- a/drivers/clk/rockchip/clk_rk3568.c
+++ b/drivers/clk/rockchip/clk_rk3568.c
@@ -13,7 +13,6 @@
#include <asm/arch-rockchip/cru_rk3568.h>
#include <asm/arch-rockchip/clock.h>
#include <asm/arch-rockchip/hardware.h>
-#include <asm/io.h>
#include <dm/device-internal.h>
#include <dm/lists.h>
#include <dt-bindings/clock/rk3568-cru.h>
diff --git a/drivers/clk/rockchip/clk_rk3588.c b/drivers/clk/rockchip/clk_rk3588.c
index a995dd5..8f33843 100644
--- a/drivers/clk/rockchip/clk_rk3588.c
+++ b/drivers/clk/rockchip/clk_rk3588.c
@@ -14,7 +14,6 @@
#include <asm/arch-rockchip/cru_rk3588.h>
#include <asm/arch-rockchip/clock.h>
#include <asm/arch-rockchip/hardware.h>
-#include <asm/io.h>
#include <dm/device-internal.h>
#include <dm/lists.h>
#include <dt-bindings/clock/rockchip,rk3588-cru.h>
diff --git a/drivers/clk/rockchip/clk_rv1108.c b/drivers/clk/rockchip/clk_rv1108.c
index b0c889a..fc442f7 100644
--- a/drivers/clk/rockchip/clk_rv1108.c
+++ b/drivers/clk/rockchip/clk_rv1108.c
@@ -13,7 +13,6 @@
#include <malloc.h>
#include <syscon.h>
#include <asm/global_data.h>
-#include <asm/io.h>
#include <asm/arch-rockchip/clock.h>
#include <asm/arch-rockchip/cru_rv1108.h>
#include <asm/arch-rockchip/hardware.h>
diff --git a/drivers/clk/rockchip/clk_rv1126.c b/drivers/clk/rockchip/clk_rv1126.c
index 580c0b1..cfdfcbd 100644
--- a/drivers/clk/rockchip/clk_rv1126.c
+++ b/drivers/clk/rockchip/clk_rv1126.c
@@ -16,7 +16,6 @@
#include <asm/arch-rockchip/grf_rv1126.h>
#include <asm/arch-rockchip/hardware.h>
#include <dm/device-internal.h>
-#include <asm/io.h>
#include <dm/lists.h>
#include <dt-bindings/clock/rockchip,rv1126-cru.h>
diff --git a/drivers/cpu/riscv_cpu.c b/drivers/cpu/riscv_cpu.c
index 5d1026b..9b1950e 100644
--- a/drivers/cpu/riscv_cpu.c
+++ b/drivers/cpu/riscv_cpu.c
@@ -21,13 +21,13 @@
static int riscv_cpu_get_desc(const struct udevice *dev, char *buf, int size)
{
- const char *isa;
+ const char *cpu;
- isa = dev_read_string(dev, "riscv,isa");
- if (size < (strlen(isa) + 1))
+ cpu = dev_read_string(dev, "compatible");
+ if (size < (strlen(cpu) + 1))
return -ENOSPC;
- strcpy(buf, isa);
+ strcpy(buf, cpu);
return 0;
}
diff --git a/drivers/crypto/fsl/Kconfig b/drivers/crypto/fsl/Kconfig
index eaad196..294e1c8 100644
--- a/drivers/crypto/fsl/Kconfig
+++ b/drivers/crypto/fsl/Kconfig
@@ -62,6 +62,12 @@
if FSL_CAAM
+config FSL_CAAM_JR_NTZ_ACCESS
+ bool "Give CAAM Job Ring access to non-secure world"
+ help
+ It is needed when OP-TEE is not used and Freescale CAAM Job Ring linux
+ driver is used.
+
config FSL_CAAM_RNG
bool "Enable Random Number Generator support"
depends on DM_RNG
diff --git a/drivers/crypto/fsl/jr.c b/drivers/crypto/fsl/jr.c
index ceb66dd..203f162 100644
--- a/drivers/crypto/fsl/jr.c
+++ b/drivers/crypto/fsl/jr.c
@@ -673,6 +673,21 @@
return ret;
}
+#if CONFIG_IS_ENABLED(FSL_CAAM_JR_NTZ_ACCESS)
+static void jr_setown_non_trusted(ccsr_sec_t *sec)
+{
+ u32 jrown_ns;
+ int i;
+
+ /* Set ownership of job rings to non-TrustZone mode */
+ for (i = 0; i < ARRAY_SIZE(sec->jrliodnr); i++) {
+ jrown_ns = sec_in32(&sec->jrliodnr[i].ms);
+ jrown_ns |= JROWN_NS | JRMID_NS;
+ sec_out32(&sec->jrliodnr[i].ms, jrown_ns);
+ }
+}
+#endif
+
int sec_init_idx(uint8_t sec_idx)
{
int ret = 0;
@@ -761,6 +776,10 @@
#if CONFIG_IS_ENABLED(OF_CONTROL)
init:
#endif
+#if CONFIG_IS_ENABLED(FSL_CAAM_JR_NTZ_ACCESS)
+ jr_setown_non_trusted(sec);
+#endif
+
ret = jr_init(sec_idx, caam);
if (ret < 0) {
printf("SEC%u: initialization failed\n", sec_idx);
diff --git a/drivers/crypto/fsl/jr.h b/drivers/crypto/fsl/jr.h
index 4e4c4af..b136cd8 100644
--- a/drivers/crypto/fsl/jr.h
+++ b/drivers/crypto/fsl/jr.h
@@ -37,6 +37,8 @@
#define JRNSLIODN_MASK 0x0fff0000
#define JRSLIODN_SHIFT 0
#define JRSLIODN_MASK 0x00000fff
+#define JROWN_NS 0x00000008
+#define JRMID_NS 0x00000001
#define JRDID_MS_PRIM_DID BIT(0)
#define JRDID_MS_PRIM_TZ BIT(4)
diff --git a/drivers/fastboot/Kconfig b/drivers/fastboot/Kconfig
index 5e5855a..d6e2be0 100644
--- a/drivers/fastboot/Kconfig
+++ b/drivers/fastboot/Kconfig
@@ -1,5 +1,4 @@
menu "Fastboot support"
- depends on CMDLINE
config FASTBOOT
bool
@@ -13,6 +12,10 @@
More information about the protocol and usecases:
https://android.googlesource.com/platform/system/core/+/refs/heads/master/fastboot/
+ Note that enabling CMDLINE is recommended since fastboot allows U-Boot
+ commands to be executed on request. The CMDLINE option is required
+ for anything other than simply booting the OS.
+
config USB_FUNCTION_FASTBOOT
bool "Enable USB fastboot gadget"
depends on USB_GADGET
diff --git a/drivers/fastboot/fb_command.c b/drivers/fastboot/fb_command.c
index f95f4e4..b8782bf 100644
--- a/drivers/fastboot/fb_command.c
+++ b/drivers/fastboot/fb_command.c
@@ -11,6 +11,7 @@
#include <fastboot-internal.h>
#include <fb_mmc.h>
#include <fb_nand.h>
+#include <mapmem.h>
#include <part.h>
#include <stdlib.h>
#include <linux/printk.h>
@@ -278,6 +279,7 @@
{
#define BYTES_PER_DOT 0x20000
u32 pre_dot_num, now_dot_num;
+ void *buf;
if (fastboot_data_len == 0 ||
(fastboot_bytes_received + fastboot_data_len) >
@@ -287,8 +289,10 @@
return;
}
/* Download data to fastboot_buf_addr */
- memcpy(fastboot_buf_addr + fastboot_bytes_received,
+ buf = map_sysmem(fastboot_buf_addr, 0);
+ memcpy(buf + fastboot_bytes_received,
fastboot_data, fastboot_data_len);
+ unmap_sysmem(buf);
pre_dot_num = fastboot_bytes_received / BYTES_PER_DOT;
fastboot_bytes_received += fastboot_data_len;
@@ -331,13 +335,16 @@
*/
static void __maybe_unused flash(char *cmd_parameter, char *response)
{
+ void *buf = map_sysmem(fastboot_buf_addr, 0);
+
if (IS_ENABLED(CONFIG_FASTBOOT_FLASH_MMC))
- fastboot_mmc_flash_write(cmd_parameter, fastboot_buf_addr,
- image_size, response);
+ fastboot_mmc_flash_write(cmd_parameter, buf, image_size,
+ response);
if (IS_ENABLED(CONFIG_FASTBOOT_FLASH_NAND))
- fastboot_nand_flash_write(cmd_parameter, fastboot_buf_addr,
- image_size, response);
+ fastboot_nand_flash_write(cmd_parameter, buf, image_size,
+ response);
+ unmap_sysmem(buf);
}
/**
diff --git a/drivers/fastboot/fb_common.c b/drivers/fastboot/fb_common.c
index 3576b06..5959545 100644
--- a/drivers/fastboot/fb_common.c
+++ b/drivers/fastboot/fb_common.c
@@ -11,6 +11,7 @@
*/
#include <bcb.h>
+#include <bootm.h>
#include <common.h>
#include <command.h>
#include <env.h>
@@ -20,7 +21,7 @@
/**
* fastboot_buf_addr - base address of the fastboot download buffer
*/
-void *fastboot_buf_addr;
+ulong fastboot_buf_addr;
/**
* fastboot_buf_size - size of the fastboot download buffer
@@ -142,22 +143,19 @@
*/
void fastboot_boot(void)
{
- char *s;
+ char *s = NULL;
- s = env_get("fastboot_bootcmd");
- if (s) {
- run_command(s, CMD_FLAG_ENV);
- } else if (IS_ENABLED(CONFIG_CMD_BOOTM)) {
- static char boot_addr_start[20];
- static char *const bootm_args[] = {
- "bootm", boot_addr_start, NULL
- };
+ if (IS_ENABLED(CONFIG_CMDLINE)) {
+ s = env_get("fastboot_bootcmd");
+ if (s)
+ run_command(s, CMD_FLAG_ENV);
+ }
- snprintf(boot_addr_start, sizeof(boot_addr_start) - 1,
- "0x%p", fastboot_buf_addr);
- printf("Booting kernel at %s...\n\n\n", boot_addr_start);
+ if (!s && IS_ENABLED(CONFIG_BOOTM)) {
+ int ret;
- do_bootm(NULL, 0, 2, bootm_args);
+ printf("Booting kernel at %lx...\n\n\n", fastboot_buf_addr);
+ ret = bootm_boot_start(fastboot_buf_addr, NULL);
/*
* This only happens if image is somehow faulty so we start
@@ -214,16 +212,9 @@
fastboot_progress_callback = progress;
}
-/*
- * fastboot_init() - initialise new fastboot protocol session
- *
- * @buf_addr: Pointer to download buffer, or NULL for default
- * @buf_size: Size of download buffer, or zero for default
- */
-void fastboot_init(void *buf_addr, u32 buf_size)
+void fastboot_init(ulong buf_addr, u32 buf_size)
{
- fastboot_buf_addr = buf_addr ? buf_addr :
- (void *)CONFIG_FASTBOOT_BUF_ADDR;
+ fastboot_buf_addr = buf_addr ? buf_addr : CONFIG_FASTBOOT_BUF_ADDR;
fastboot_buf_size = buf_size ? buf_size : CONFIG_FASTBOOT_BUF_SIZE;
fastboot_set_progress_callback(NULL);
}
diff --git a/drivers/firmware/psci.c b/drivers/firmware/psci.c
index c6b9efa..03544d7 100644
--- a/drivers/firmware/psci.c
+++ b/drivers/firmware/psci.c
@@ -135,10 +135,13 @@
PSCI_VERSION_MAJOR(psci_0_2_get_version()) == 0)
return 0;
- if (request_psci_features(ARM_SMCCC_ARCH_FEATURES) ==
+ if (request_psci_features(ARM_SMCCC_VERSION) ==
PSCI_RET_NOT_SUPPORTED)
return 0;
+ if (invoke_psci_fn(ARM_SMCCC_VERSION, 0, 0, 0) < ARM_SMCCC_VERSION_1_1)
+ return 0;
+
if (psci_method == PSCI_METHOD_HVC)
pdata->invoke_fn = smccc_invoke_hvc;
else
diff --git a/drivers/gpio/Kconfig b/drivers/gpio/Kconfig
index 2df3dc4..b050585 100644
--- a/drivers/gpio/Kconfig
+++ b/drivers/gpio/Kconfig
@@ -256,6 +256,9 @@
- MCP23008
- MCP23017
- MCP23018
+ - MCP23S08
+ - MCP23S17
+ - MCP23S18
config MSCC_SGPIO
bool "Microsemi Serial GPIO driver"
@@ -662,13 +665,6 @@
8-bit gpo expander, all gpo lines are controlled by writing
value into data register.
-config TURRIS_OMNIA_MCU
- bool "Turris Omnia MCU GPIO driver"
- depends on DM_GPIO
- default y if TARGET_TURRIS_OMNIA
- help
- Support for GPIOs on MCU connected to Turris Omnia via i2c.
-
config FTGPIO010
bool "Faraday Technology FTGPIO010 driver"
depends on DM_GPIO
diff --git a/drivers/gpio/Makefile b/drivers/gpio/Makefile
index da3da5d..4a29315 100644
--- a/drivers/gpio/Makefile
+++ b/drivers/gpio/Makefile
@@ -23,7 +23,7 @@
obj-$(CONFIG_INTEL_BROADWELL_GPIO) += intel_broadwell_gpio.o
obj-$(CONFIG_IPROC_GPIO) += iproc_gpio.o
obj-$(CONFIG_KIRKWOOD_GPIO) += kw_gpio.o
-obj-$(CONFIG_MCP230XX_GPIO) += mcp230xx_gpio.o
+obj-$(CONFIG_$(SPL_TPL_)MCP230XX_GPIO) += mcp230xx_gpio.o
obj-$(CONFIG_MXC_GPIO) += mxc_gpio.o
obj-$(CONFIG_MXS_GPIO) += mxs_gpio.o
obj-$(CONFIG_NPCM_GPIO) += npcm_gpio.o
@@ -73,7 +73,6 @@
obj-$(CONFIG_SL28CPLD_GPIO) += sl28cpld-gpio.o
obj-$(CONFIG_ZYNQMP_GPIO_MODEPIN) += zynqmp_gpio_modepin.o
obj-$(CONFIG_SLG7XL45106_I2C_GPO) += gpio_slg7xl45106.o
-obj-$(CONFIG_$(SPL_TPL_)TURRIS_OMNIA_MCU) += turris_omnia_mcu.o
obj-$(CONFIG_FTGPIO010) += ftgpio010.o
obj-$(CONFIG_ADP5585_GPIO) += adp5585_gpio.o
obj-$(CONFIG_RZG2L_GPIO) += rzg2l-gpio.o
diff --git a/drivers/gpio/mcp230xx_gpio.c b/drivers/gpio/mcp230xx_gpio.c
index 9f02fd4..df99fde 100644
--- a/drivers/gpio/mcp230xx_gpio.c
+++ b/drivers/gpio/mcp230xx_gpio.c
@@ -11,6 +11,7 @@
#include <errno.h>
#include <dm.h>
#include <i2c.h>
+#include <spi.h>
#include <asm/gpio.h>
#include <dm/device_compat.h>
#include <dt-bindings/gpio/gpio.h>
@@ -20,8 +21,15 @@
MCP23008,
MCP23017,
MCP23018,
+ MCP23S08,
+ MCP23S17,
+ MCP23S18,
};
+struct mcp230xx_info {
+ uint dev_addr;
+};
+
#define MCP230XX_IODIR 0x00
#define MCP230XX_GPPU 0x06
#define MCP230XX_GPIO 0x09
@@ -29,29 +37,136 @@
#define BANKSIZE 8
+#define MCP230XX_ADDR 0x20
+
+static int mcp230xx_read_spi(struct udevice *dev, uint reg_addr)
+{
+ struct mcp230xx_info *info = dev_get_plat(dev);
+ uint dev_addr, value = 0;
+ int ret;
+
+ /* set R/W bit for reading */
+ dev_addr = (info->dev_addr << 1) | 1;
+
+ ret = dm_spi_claim_bus(dev);
+ if (ret)
+ return ret;
+
+ ret = dm_spi_xfer(dev, 0, NULL, NULL, SPI_XFER_BEGIN);
+ if (ret < 0)
+ goto fail;
+ udelay(1);
+
+ ret = dm_spi_xfer(dev, 8, &dev_addr, NULL, 0);
+ if (ret < 0)
+ goto fail;
+
+ ret = dm_spi_xfer(dev, 8, ®_addr, NULL, 0);
+ if (ret < 0)
+ goto fail;
+
+ ret = dm_spi_xfer(dev, 8, NULL, &value, 0);
+
+fail:
+ dm_spi_xfer(dev, 0, NULL, NULL, SPI_XFER_END);
+ dm_spi_release_bus(dev);
+ if (ret < 0)
+ return ret;
+ return value;
+}
+
static int mcp230xx_read(struct udevice *dev, uint reg, uint offset)
{
struct gpio_dev_priv *uc_priv = dev_get_uclass_priv(dev);
int bank = offset / BANKSIZE;
int mask = 1 << (offset % BANKSIZE);
int shift = (uc_priv->gpio_count / BANKSIZE) - 1;
- int ret;
+ int reg_addr = (reg << shift) | bank;
+ int ret = 0;
+
+ switch (dev_get_driver_data(dev)) {
+ case MCP23008:
+ case MCP23017:
+ case MCP23018:
+ ret = dm_i2c_reg_read(dev, reg_addr);
+ break;
+ case MCP23S08:
+ case MCP23S17:
+ case MCP23S18:
+ ret = mcp230xx_read_spi(dev, reg_addr);
+ break;
+ default:
+ return -ENODEV;
+ }
- ret = dm_i2c_reg_read(dev, (reg << shift) | bank);
if (ret < 0)
return ret;
return !!(ret & mask);
}
+static int mcp230xx_clrset_spi(struct udevice *dev, uint reg_addr, uint clr, uint set)
+{
+ struct mcp230xx_info *info = dev_get_plat(dev);
+ int dev_addr, value;
+ int ret;
+
+ /* R/W bit = 0 for writing */
+ dev_addr = (info->dev_addr << 1);
+
+ ret = mcp230xx_read_spi(dev, reg_addr);
+ if (ret < 0)
+ return ret;
+
+ value = ret;
+ value &= ~clr;
+ value |= set;
+
+ ret = dm_spi_claim_bus(dev);
+ if (ret)
+ return ret;
+
+ ret = dm_spi_xfer(dev, 0, NULL, NULL, SPI_XFER_BEGIN);
+ if (ret < 0)
+ goto fail;
+ udelay(1);
+
+ ret = dm_spi_xfer(dev, 8, &dev_addr, NULL, 0);
+ if (ret < 0)
+ goto fail;
+
+ ret = dm_spi_xfer(dev, 8, ®_addr, NULL, 0);
+ if (ret < 0)
+ goto fail;
+
+ ret = dm_spi_xfer(dev, 8, &value, NULL, 0);
+
+fail:
+ dm_spi_xfer(dev, 0, NULL, NULL, SPI_XFER_END);
+ dm_spi_release_bus(dev);
+ return ret;
+}
+
static int mcp230xx_write(struct udevice *dev, uint reg, uint offset, bool val)
{
struct gpio_dev_priv *uc_priv = dev_get_uclass_priv(dev);
int bank = offset / BANKSIZE;
int mask = 1 << (offset % BANKSIZE);
int shift = (uc_priv->gpio_count / BANKSIZE) - 1;
+ int reg_addr = (reg << shift) | bank;
- return dm_i2c_reg_clrset(dev, (reg << shift) | bank, mask, val ? mask : 0);
+ switch (dev_get_driver_data(dev)) {
+ case MCP23008:
+ case MCP23017:
+ case MCP23018:
+ return dm_i2c_reg_clrset(dev, reg_addr, mask, val ? mask : 0);
+ case MCP23S08:
+ case MCP23S17:
+ case MCP23S18:
+ return mcp230xx_clrset_spi(dev, reg_addr, mask, val ? mask : 0);
+ default:
+ return -ENODEV;
+ }
}
static int mcp230xx_get_value(struct udevice *dev, uint offset)
@@ -181,22 +296,37 @@
static int mcp230xx_probe(struct udevice *dev)
{
struct gpio_dev_priv *uc_priv = dev_get_uclass_priv(dev);
- char name[32], label[8], *str;
+ struct mcp230xx_info *info = dev_get_plat(dev);
+ char name[32], label[32], *str;
int addr, gpio_count, size;
const u8 *tmp;
switch (dev_get_driver_data(dev)) {
case MCP23008:
+ case MCP23S08:
gpio_count = 8;
break;
case MCP23017:
case MCP23018:
+ case MCP23S17:
+ case MCP23S18:
gpio_count = 16;
break;
default:
return -ENODEV;
}
+ switch (dev_get_driver_data(dev)) {
+ case MCP23S08:
+ case MCP23S17:
+ case MCP23S18:
+ info->dev_addr = dev_read_u32_default(dev, "addr", MCP230XX_ADDR);
+ break;
+ default:
+ info->dev_addr = 0;
+ break;
+ }
+
addr = dev_read_addr(dev);
tmp = dev_read_prop(dev, "label", &size);
if (tmp) {
@@ -220,9 +350,14 @@
}
static const struct udevice_id mcp230xx_ids[] = {
+ /* i2c interface */
{ .compatible = "microchip,mcp23008", .data = MCP23008, },
{ .compatible = "microchip,mcp23017", .data = MCP23017, },
{ .compatible = "microchip,mcp23018", .data = MCP23018, },
+ /* spi interface */
+ { .compatible = "microchip,mcp23s08", .data = MCP23S08, },
+ { .compatible = "microchip,mcp23s17", .data = MCP23S17, },
+ { .compatible = "microchip,mcp23s18", .data = MCP23S18, },
{ }
};
@@ -231,5 +366,6 @@
.id = UCLASS_GPIO,
.ops = &mcp230xx_ops,
.probe = mcp230xx_probe,
+ .plat_auto = sizeof(struct mcp230xx_info),
.of_match = mcp230xx_ids,
};
diff --git a/drivers/gpio/msm_gpio.c b/drivers/gpio/msm_gpio.c
index 5e57b0c..f5d9ab5 100644
--- a/drivers/gpio/msm_gpio.c
+++ b/drivers/gpio/msm_gpio.c
@@ -35,19 +35,19 @@
#define GPIO_IN_OUT_REG(dev, x) \
(GPIO_CONFIG_REG(dev, x) + 0x4)
-static int msm_gpio_direction_input(struct udevice *dev, unsigned int gpio)
+static void msm_gpio_direction_input(struct udevice *dev, unsigned int gpio)
{
struct msm_gpio_bank *priv = dev_get_priv(dev);
/* Always NOP for special pins, assume they're in the correct state */
if (qcom_is_special_pin(priv->pin_data, gpio))
- return 0;
+ return;
/* Disable OE bit */
clrsetbits_le32(priv->base + GPIO_CONFIG_REG(dev, gpio),
GPIO_OE_MASK, GPIO_OE_DISABLE);
- return 0;
+ return;
}
static int msm_gpio_set_value(struct udevice *dev, unsigned int gpio, int value)
@@ -84,6 +84,23 @@
return 0;
}
+static int msm_gpio_set_flags(struct udevice *dev, unsigned int gpio, ulong flags)
+{
+ if (flags & GPIOD_IS_OUT_ACTIVE) {
+ return msm_gpio_direction_output(dev, gpio, 1);
+ } else if (flags & GPIOD_IS_OUT) {
+ return msm_gpio_direction_output(dev, gpio, 0);
+ } else if (flags & GPIOD_IS_IN) {
+ msm_gpio_direction_input(dev, gpio);
+ if (flags & GPIOD_PULL_UP)
+ return msm_gpio_set_value(dev, gpio, 1);
+ else if (flags & GPIOD_PULL_DOWN)
+ return msm_gpio_set_value(dev, gpio, 0);
+ }
+
+ return 0;
+}
+
static int msm_gpio_get_value(struct udevice *dev, unsigned int gpio)
{
struct msm_gpio_bank *priv = dev_get_priv(dev);
@@ -110,10 +127,8 @@
}
static const struct dm_gpio_ops gpio_msm_ops = {
- .direction_input = msm_gpio_direction_input,
- .direction_output = msm_gpio_direction_output,
+ .set_flags = msm_gpio_set_flags,
.get_value = msm_gpio_get_value,
- .set_value = msm_gpio_set_value,
.get_function = msm_gpio_get_function,
};
diff --git a/drivers/gpio/rk_gpio.c b/drivers/gpio/rk_gpio.c
index 4a6ae55..2e901ac 100644
--- a/drivers/gpio/rk_gpio.c
+++ b/drivers/gpio/rk_gpio.c
@@ -11,7 +11,6 @@
#include <syscon.h>
#include <linux/errno.h>
#include <asm/gpio.h>
-#include <asm/io.h>
#include <asm/arch-rockchip/clock.h>
#include <asm/arch-rockchip/hardware.h>
#include <asm/arch-rockchip/gpio.h>
@@ -201,8 +200,11 @@
priv->bank = args.args[1] / ROCKCHIP_GPIOS_PER_BANK;
} else {
uc_priv->gpio_count = ROCKCHIP_GPIOS_PER_BANK;
- end = strrchr(dev->name, '@');
- priv->bank = trailing_strtoln(dev->name, end);
+ ret = dev_read_alias_seq(dev, &priv->bank);
+ if (ret) {
+ end = strrchr(dev->name, '@');
+ priv->bank = trailing_strtoln(dev->name, end);
+ }
}
priv->name[0] = 'A' + priv->bank;
diff --git a/drivers/gpio/turris_omnia_mcu.c b/drivers/gpio/turris_omnia_mcu.c
deleted file mode 100644
index 2d2bf2d..0000000
--- a/drivers/gpio/turris_omnia_mcu.c
+++ /dev/null
@@ -1,316 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+
-// (C) 2022 Pali Rohár <pali@kernel.org>
-
-#include <common.h>
-#include <dm.h>
-#include <i2c.h>
-#include <asm/gpio.h>
-#include <linux/log2.h>
-
-enum commands_e {
- CMD_GET_STATUS_WORD = 0x01,
- CMD_GENERAL_CONTROL = 0x02,
-
- /* available if STS_FEATURES_SUPPORTED bit set in status word */
- CMD_GET_FEATURES = 0x10,
-
- /* available if FEAT_EXT_CMDS bit is set in features */
- CMD_GET_EXT_STATUS_DWORD = 0x11,
-
- /* available if FEAT_EXT_CMDS and FEAT_PERIPH_MCU bits are set in featurs */
- CMD_EXT_CONTROL = 0x12,
- CMD_GET_EXT_CONTROL_STATUS = 0x13,
-};
-
-/* CMD_GET_STATUS_WORD */
-enum sts_word_e {
- STS_MCU_TYPE_MASK = GENMASK(1, 0),
- STS_MCU_TYPE_STM32 = 0,
- STS_MCU_TYPE_GD32 = 1,
- STS_MCU_TYPE_MKL = 2,
- STS_FEATURES_SUPPORTED = BIT(2),
- STS_USER_REGULATOR_NOT_SUPPORTED = BIT(3),
- STS_CARD_DET = BIT(4),
- STS_MSATA_IND = BIT(5),
- STS_USB30_OVC = BIT(6),
- STS_USB31_OVC = BIT(7),
- STS_USB30_PWRON = BIT(8),
- STS_USB31_PWRON = BIT(9),
- STS_ENABLE_4V5 = BIT(10),
- STS_BUTTON_MODE = BIT(11),
- STS_BUTTON_PRESSED = BIT(12),
- STS_BUTTON_COUNTER_MASK = GENMASK(15, 13)
-};
-
-/* CMD_GENERAL_CONTROL */
-enum ctl_byte_e {
- CTL_LIGHT_RST = BIT(0),
- CTL_HARD_RST = BIT(1),
- /*CTL_RESERVED = BIT(2),*/
- CTL_USB30_PWRON = BIT(3),
- CTL_USB31_PWRON = BIT(4),
- CTL_ENABLE_4V5 = BIT(5),
- CTL_BUTTON_MODE = BIT(6),
- CTL_BOOTLOADER = BIT(7)
-};
-
-/* CMD_GET_FEATURES */
-enum features_e {
- FEAT_PERIPH_MCU = BIT(0),
- FEAT_EXT_CMDS = BIT(1),
-};
-
-struct turris_omnia_mcu_info {
- u16 features;
-};
-
-static int turris_omnia_mcu_get_function(struct udevice *dev, uint offset)
-{
- struct turris_omnia_mcu_info *info = dev_get_plat(dev);
-
- switch (offset) {
- /* bank 0 */
- case 0 ... 15:
- switch (offset) {
- case ilog2(STS_USB30_PWRON):
- case ilog2(STS_USB31_PWRON):
- case ilog2(STS_ENABLE_4V5):
- case ilog2(STS_BUTTON_MODE):
- return GPIOF_OUTPUT;
- default:
- return GPIOF_INPUT;
- }
-
- /* bank 1 - supported only when FEAT_EXT_CMDS is set */
- case (16 + 0) ... (16 + 31):
- if (!(info->features & FEAT_EXT_CMDS))
- return -EINVAL;
- return GPIOF_INPUT;
-
- /* bank 2 - supported only when FEAT_EXT_CMDS and FEAT_PERIPH_MCU is set */
- case (16 + 32 + 0) ... (16 + 32 + 15):
- if (!(info->features & FEAT_EXT_CMDS))
- return -EINVAL;
- if (!(info->features & FEAT_PERIPH_MCU))
- return -EINVAL;
- return GPIOF_OUTPUT;
-
- default:
- return -EINVAL;
- }
-}
-
-static int turris_omnia_mcu_get_value(struct udevice *dev, uint offset)
-{
- struct turris_omnia_mcu_info *info = dev_get_plat(dev);
- u8 val16[2];
- u8 val32[4];
- int ret;
-
- switch (offset) {
- /* bank 0 */
- case 0 ... 15:
- ret = dm_i2c_read(dev, CMD_GET_STATUS_WORD, val16, 2);
- if (ret)
- return ret;
- return ((((u16)val16[1] << 8) | val16[0]) >> offset) & 0x1;
-
- /* bank 1 - supported only when FEAT_EXT_CMDS is set */
- case (16 + 0) ... (16 + 31):
- if (!(info->features & FEAT_EXT_CMDS))
- return -EINVAL;
- ret = dm_i2c_read(dev, CMD_GET_EXT_STATUS_DWORD, val32, 4);
- if (ret)
- return ret;
- return ((((u32)val32[3] << 24) | ((u32)val32[2] << 16) |
- ((u32)val32[1] << 8) | val32[0]) >> (offset - 16)) & 0x1;
-
- /* bank 2 - supported only when FEAT_EXT_CMDS and FEAT_PERIPH_MCU is set */
- case (16 + 32 + 0) ... (16 + 32 + 15):
- if (!(info->features & FEAT_EXT_CMDS))
- return -EINVAL;
- if (!(info->features & FEAT_PERIPH_MCU))
- return -EINVAL;
- ret = dm_i2c_read(dev, CMD_GET_EXT_CONTROL_STATUS, val16, 2);
- if (ret)
- return ret;
- return ((((u16)val16[1] << 8) | val16[0]) >> (offset - 16 - 32)) & 0x1;
-
- default:
- return -EINVAL;
- }
-}
-
-static int turris_omnia_mcu_set_value(struct udevice *dev, uint offset, int value)
-{
- struct turris_omnia_mcu_info *info = dev_get_plat(dev);
- u8 val16[2];
- u8 val32[4];
-
- switch (offset) {
- /* bank 0 */
- case 0 ... 15:
- switch (offset) {
- case ilog2(STS_USB30_PWRON):
- val16[1] = CTL_USB30_PWRON;
- break;
- case ilog2(STS_USB31_PWRON):
- val16[1] = CTL_USB31_PWRON;
- break;
- case ilog2(STS_ENABLE_4V5):
- val16[1] = CTL_ENABLE_4V5;
- break;
- case ilog2(STS_BUTTON_MODE):
- val16[1] = CTL_BUTTON_MODE;
- break;
- default:
- return -EINVAL;
- }
- val16[0] = value ? val16[1] : 0;
- return dm_i2c_write(dev, CMD_GENERAL_CONTROL, val16, sizeof(val16));
-
- /* bank 2 - supported only when FEAT_EXT_CMDS and FEAT_PERIPH_MCU is set */
- case (16 + 32 + 0) ... (16 + 32 + 15):
- if (!(info->features & FEAT_EXT_CMDS))
- return -EINVAL;
- if (!(info->features & FEAT_PERIPH_MCU))
- return -EINVAL;
- val32[3] = BIT(offset - 16 - 32) >> 8;
- val32[2] = BIT(offset - 16 - 32) & 0xff;
- val32[1] = value ? val32[3] : 0;
- val32[0] = value ? val32[2] : 0;
- return dm_i2c_write(dev, CMD_EXT_CONTROL, val32, sizeof(val32));
-
- default:
- return -EINVAL;
- }
-}
-
-static int turris_omnia_mcu_direction_input(struct udevice *dev, uint offset)
-{
- int ret;
-
- ret = turris_omnia_mcu_get_function(dev, offset);
- if (ret < 0)
- return ret;
- else if (ret != GPIOF_INPUT)
- return -EOPNOTSUPP;
-
- return 0;
-}
-
-static int turris_omnia_mcu_direction_output(struct udevice *dev, uint offset, int value)
-{
- int ret;
-
- ret = turris_omnia_mcu_get_function(dev, offset);
- if (ret < 0)
- return ret;
- else if (ret != GPIOF_OUTPUT)
- return -EOPNOTSUPP;
-
- return turris_omnia_mcu_set_value(dev, offset, value);
-}
-
-static int turris_omnia_mcu_xlate(struct udevice *dev, struct gpio_desc *desc,
- struct ofnode_phandle_args *args)
-{
- uint bank, gpio, flags, offset;
- int ret;
-
- if (args->args_count != 3)
- return -EINVAL;
-
- bank = args->args[0];
- gpio = args->args[1];
- flags = args->args[2];
-
- switch (bank) {
- case 0:
- if (gpio >= 16)
- return -EINVAL;
- offset = gpio;
- break;
- case 1:
- if (gpio >= 32)
- return -EINVAL;
- offset = 16 + gpio;
- break;
- case 2:
- if (gpio >= 16)
- return -EINVAL;
- offset = 16 + 32 + gpio;
- break;
- default:
- return -EINVAL;
- }
-
- ret = turris_omnia_mcu_get_function(dev, offset);
- if (ret < 0)
- return ret;
-
- desc->offset = offset;
- desc->flags = gpio_flags_xlate(flags);
-
- return 0;
-}
-
-static const struct dm_gpio_ops turris_omnia_mcu_ops = {
- .direction_input = turris_omnia_mcu_direction_input,
- .direction_output = turris_omnia_mcu_direction_output,
- .get_value = turris_omnia_mcu_get_value,
- .set_value = turris_omnia_mcu_set_value,
- .get_function = turris_omnia_mcu_get_function,
- .xlate = turris_omnia_mcu_xlate,
-};
-
-static int turris_omnia_mcu_probe(struct udevice *dev)
-{
- struct turris_omnia_mcu_info *info = dev_get_plat(dev);
- struct gpio_dev_priv *uc_priv = dev_get_uclass_priv(dev);
- u16 status;
- u8 val[2];
- int ret;
-
- ret = dm_i2c_read(dev, CMD_GET_STATUS_WORD, val, 2);
- if (ret) {
- printf("Error: turris_omnia_mcu CMD_GET_STATUS_WORD failed: %d\n", ret);
- return ret;
- }
-
- status = ((u16)val[1] << 8) | val[0];
-
- if (status & STS_FEATURES_SUPPORTED) {
- ret = dm_i2c_read(dev, CMD_GET_FEATURES, val, 2);
- if (ret) {
- printf("Error: turris_omnia_mcu CMD_GET_FEATURES failed: %d\n", ret);
- return ret;
- }
- info->features = ((u16)val[1] << 8) | val[0];
- }
-
- uc_priv->bank_name = "mcu_";
-
- if ((info->features & FEAT_EXT_CMDS) && (info->features & FEAT_PERIPH_MCU))
- uc_priv->gpio_count = 16 + 32 + 16;
- else if (info->features & FEAT_EXT_CMDS)
- uc_priv->gpio_count = 16 + 32;
- else
- uc_priv->gpio_count = 16;
-
- return 0;
-}
-
-static const struct udevice_id turris_omnia_mcu_ids[] = {
- { .compatible = "cznic,turris-omnia-mcu" },
- { }
-};
-
-U_BOOT_DRIVER(turris_omnia_mcu) = {
- .name = "turris-omnia-mcu",
- .id = UCLASS_GPIO,
- .ops = &turris_omnia_mcu_ops,
- .probe = turris_omnia_mcu_probe,
- .plat_auto = sizeof(struct turris_omnia_mcu_info),
- .of_match = turris_omnia_mcu_ids,
-};
diff --git a/drivers/iommu/qcom-hyp-smmu.c b/drivers/iommu/qcom-hyp-smmu.c
index 8e5cdb5..f2b39de 100644
--- a/drivers/iommu/qcom-hyp-smmu.c
+++ b/drivers/iommu/qcom-hyp-smmu.c
@@ -319,7 +319,7 @@
}
#ifdef DEBUG
-static inline void dump_boot_mappings(struct arm_smmu_priv *priv)
+static inline void dump_boot_mappings(struct qcom_smmu_priv *priv)
{
u32 val;
int i;
diff --git a/drivers/misc/Kconfig b/drivers/misc/Kconfig
index f11ce72..6b06888 100644
--- a/drivers/misc/Kconfig
+++ b/drivers/misc/Kconfig
@@ -505,6 +505,17 @@
model. This should only be enabled for testing as it is not useful for
anything else.
+config TURRIS_OMNIA_MCU
+ bool "Enable Turris Omnia MCU driver"
+ depends on DM_I2C
+ depends on DM_GPIO
+ depends on DM_RNG
+ depends on SYSRESET
+ default y if TARGET_TURRIS_OMNIA
+ help
+ This enables support for Turris Omnia MCU connected GPIOs and
+ board power off.
+
config USB_HUB_USB251XB
tristate "USB251XB Hub Controller Configuration Driver"
depends on I2C
@@ -689,4 +700,11 @@
the base driver which provides common access methods for the
sub-drivers.
+config SPL_SOCFPGA_DT_REG
+ bool "Enable register setting from device tree in SPL"
+ depends on SPL
+ help
+ Enable register setting from device tree. This also
+ provides user a clean interface and all register settings are
+ centralized in one place, device tree.
endmenu
diff --git a/drivers/misc/Makefile b/drivers/misc/Makefile
index 0432db6..9e82990 100644
--- a/drivers/misc/Makefile
+++ b/drivers/misc/Makefile
@@ -81,6 +81,7 @@
obj-$(CONFIG_TEGRA186_BPMP) += tegra186_bpmp.o
obj-$(CONFIG_TEGRA_CAR) += tegra_car.o
obj-$(CONFIG_TEST_DRV) += test_drv.o
+obj-$(CONFIG_$(SPL_TPL_)TURRIS_OMNIA_MCU) += turris_omnia_mcu.o
obj-$(CONFIG_TWL4030_LED) += twl4030_led.o
obj-$(CONFIG_VEXPRESS_CONFIG) += vexpress_config.o
obj-$(CONFIG_WINBOND_W83627) += winbond_w83627.o
@@ -90,3 +91,4 @@
obj-$(CONFIG_ESM_K3) += k3_esm.o
obj-$(CONFIG_ESM_PMIC) += esm_pmic.o
obj-$(CONFIG_SL28CPLD) += sl28cpld.o
+obj-$(CONFIG_SPL_SOCFPGA_SEC_REG) += socfpga_dtreg.o
diff --git a/drivers/misc/imx_ele/ele_api.c b/drivers/misc/imx_ele/ele_api.c
index 0c01773..e0ec22c 100644
--- a/drivers/misc/imx_ele/ele_api.c
+++ b/drivers/misc/imx_ele/ele_api.c
@@ -528,6 +528,38 @@
return ret;
}
+int ele_commit(u16 fuse_id, u32 *response, u32 *info_type)
+{
+ struct udevice *dev = gd->arch.ele_dev;
+ int size = sizeof(struct ele_msg);
+ struct ele_msg msg;
+ int ret = 0;
+
+ if (!dev) {
+ printf("ele dev is not initialized\n");
+ return -ENODEV;
+ }
+
+ msg.version = ELE_VERSION;
+ msg.tag = ELE_CMD_TAG;
+ msg.size = 2;
+ msg.command = ELE_COMMIT_REQ;
+ msg.data[0] = fuse_id;
+
+ ret = misc_call(dev, false, &msg, size, &msg, size);
+ if (ret)
+ printf("Error: %s: ret %d, fuse_id 0x%x, response 0x%x\n",
+ __func__, ret, fuse_id, msg.data[0]);
+
+ if (response)
+ *response = msg.data[0];
+
+ if (info_type)
+ *info_type = msg.data[1];
+
+ return ret;
+}
+
int ele_write_secure_fuse(ulong signed_msg_blk, u32 *response)
{
struct udevice *dev = gd->arch.ele_dev;
diff --git a/drivers/misc/rockchip-io-domain.c b/drivers/misc/rockchip-io-domain.c
index 3f6227f..0ffea32 100644
--- a/drivers/misc/rockchip-io-domain.c
+++ b/drivers/misc/rockchip-io-domain.c
@@ -5,7 +5,6 @@
* Ported from linux drivers/soc/rockchip/io-domain.c
*/
-#include <common.h>
#include <dm.h>
#include <dm/device_compat.h>
#include <regmap.h>
@@ -28,6 +27,10 @@
#define MAX_VOLTAGE_1_8 1980000
#define MAX_VOLTAGE_3_3 3600000
+#define RK3399_PMUGRF_CON0 0x180
+#define RK3399_PMUGRF_CON0_VSEL BIT(8)
+#define RK3399_PMUGRF_VSEL_SUPPLY_NUM 9
+
#define RK3568_PMU_GRF_IO_VSEL0 0x0140
#define RK3568_PMU_GRF_IO_VSEL1 0x0144
#define RK3568_PMU_GRF_IO_VSEL2 0x0148
@@ -35,10 +38,10 @@
struct rockchip_iodomain_soc_data {
int grf_offset;
const char *supply_names[MAX_SUPPLIES];
- int (*write)(struct regmap *grf, int idx, int uV);
+ int (*write)(struct regmap *grf, uint offset, int idx, int uV);
};
-static int rk3568_iodomain_write(struct regmap *grf, int idx, int uV)
+static int rk3568_iodomain_write(struct regmap *grf, uint offset, int idx, int uV)
{
u32 is_3v3 = uV > MAX_VOLTAGE_1_8;
u32 val0, val1;
@@ -78,6 +81,64 @@
return 0;
}
+static int rockchip_iodomain_write(struct regmap *grf, uint offset, int idx, int uV)
+{
+ u32 val;
+
+ /* set value bit */
+ val = (uV > MAX_VOLTAGE_1_8) ? 0 : 1;
+ val <<= idx;
+
+ /* apply hiword-mask */
+ val |= (BIT(idx) << 16);
+
+ return regmap_write(grf, offset, val);
+}
+
+static int rk3399_pmu_iodomain_write(struct regmap *grf, uint offset, int idx, int uV)
+{
+ int ret = rockchip_iodomain_write(grf, offset, idx, uV);
+
+ if (!ret && idx == RK3399_PMUGRF_VSEL_SUPPLY_NUM) {
+ /*
+ * set pmu io iodomain to also use this framework
+ * instead of a special gpio.
+ */
+ u32 val = RK3399_PMUGRF_CON0_VSEL | (RK3399_PMUGRF_CON0_VSEL << 16);
+ ret = regmap_write(grf, RK3399_PMUGRF_CON0, val);
+ }
+
+ return ret;
+}
+
+static const struct rockchip_iodomain_soc_data soc_data_rk3399 = {
+ .grf_offset = 0xe640,
+ .supply_names = {
+ "bt656-supply", /* APIO2_VDD */
+ "audio-supply", /* APIO5_VDD */
+ "sdmmc-supply", /* SDMMC0_VDD */
+ "gpio1830-supply", /* APIO4_VDD */
+ },
+ .write = rockchip_iodomain_write,
+};
+
+static const struct rockchip_iodomain_soc_data soc_data_rk3399_pmu = {
+ .grf_offset = 0x180,
+ .supply_names = {
+ NULL,
+ NULL,
+ NULL,
+ NULL,
+ NULL,
+ NULL,
+ NULL,
+ NULL,
+ NULL,
+ "pmu1830-supply", /* PMUIO2_VDD */
+ },
+ .write = rk3399_pmu_iodomain_write,
+};
+
static const struct rockchip_iodomain_soc_data soc_data_rk3568_pmu = {
.grf_offset = 0x140,
.supply_names = {
@@ -96,6 +157,14 @@
static const struct udevice_id rockchip_iodomain_ids[] = {
{
+ .compatible = "rockchip,rk3399-io-voltage-domain",
+ .data = (ulong)&soc_data_rk3399,
+ },
+ {
+ .compatible = "rockchip,rk3399-pmu-io-voltage-domain",
+ .data = (ulong)&soc_data_rk3399_pmu,
+ },
+ {
.compatible = "rockchip,rk3568-pmu-io-voltage-domain",
.data = (ulong)&soc_data_rk3568_pmu,
},
@@ -152,7 +221,9 @@
continue;
}
- soc_data->write(grf, i, uV);
+ ret = soc_data->write(grf, soc_data->grf_offset, i, uV);
+ if (ret)
+ dev_err(dev, "%s: Couldn't write to GRF\n", supply_name);
}
return 0;
diff --git a/drivers/misc/socfpga_dtreg.c b/drivers/misc/socfpga_dtreg.c
new file mode 100644
index 0000000..ea5d0bc
--- /dev/null
+++ b/drivers/misc/socfpga_dtreg.c
@@ -0,0 +1,115 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (C) 2024 Intel Corporation <www.intel.com>
+ */
+
+#include <dm.h>
+#include <errno.h>
+#include <asm/io.h>
+#include <linux/sizes.h>
+
+#define NUMBER_OF_ELEMENTS 3
+
+static int socfpga_dtreg_probe(struct udevice *dev)
+{
+ const fdt32_t *list;
+ fdt_addr_t offset, base;
+ fdt_val_t val, read_val, mask, set_mask;
+ int size, i;
+ u32 blk_sz, reg;
+ ofnode node;
+ const char *name = NULL;
+
+ debug("%s(dev=%p)\n", __func__, dev);
+
+ if (!dev_has_ofnode(dev))
+ return 0;
+
+ dev_for_each_subnode(node, dev) {
+ name = ofnode_get_name(node);
+ if (!name)
+ return -EINVAL;
+
+ if (ofnode_read_u32_index(node, "reg", 1, &blk_sz))
+ return -EINVAL;
+
+ base = ofnode_get_addr(node);
+ if (base == FDT_ADDR_T_NONE)
+ return -EINVAL;
+
+ debug("%s(node_offset 0x%lx node_name %s ", __func__,
+ node.of_offset, name);
+ debug("node addr 0x%llx blk sz 0x%x)\n", base, blk_sz);
+
+ list = ofnode_read_prop(node, "intel,offset-settings", &size);
+ if (!list)
+ return -EINVAL;
+
+ debug("%s(intel,offset-settings property size=%x)\n", __func__,
+ size);
+ size /= sizeof(*list) * NUMBER_OF_ELEMENTS;
+
+ /*
+ * First element: offset
+ * Second element: val
+ * Third element: mask
+ */
+ for (i = 0; i < size; i++) {
+ offset = fdt32_to_cpu(*list++);
+ val = fdt32_to_cpu(*list++);
+
+ /* Reads the masking bit value from the list */
+ mask = fdt32_to_cpu(*list++);
+
+ /*
+ * Reads out the offsets, value and masking bits
+ * Ex: <0x00000000 0x00000230 0xffffffff>
+ */
+ debug("%s(intel,offset-settings 0x%llx : 0x%llx : 0x%llx)\n",
+ __func__, offset, val, mask);
+
+ if (blk_sz < offset + SZ_4) {
+ printf("%s: Overflow as offset 0x%llx or reg",
+ __func__, offset);
+ printf(" write is more than block size 0x%x\n",
+ blk_sz);
+ return -EINVAL;
+ }
+
+ if (mask != 0) {
+ if (mask == 0xffffffff) {
+ reg = base + offset;
+ writel(val, (uintptr_t)reg);
+ } else {
+ /* Mask the value with the masking bits */
+ set_mask = val & mask;
+
+ reg = base + offset;
+
+ /* Clears and sets specific bits in the register */
+ clrsetbits_le32((uintptr_t)reg, mask, set_mask);
+ }
+ }
+
+ read_val = readl((uintptr_t)reg);
+
+ /* Reads out the register, masked value and the read value */
+ debug("%s(reg 0x%x = wr : 0x%llx rd : 0x%llx)\n",
+ __func__, reg, set_mask, read_val);
+ }
+ }
+
+ return 0;
+};
+
+static const struct udevice_id socfpga_dtreg_ids[] = {
+ {.compatible = "intel,socfpga-dtreg"},
+ { }
+};
+
+U_BOOT_DRIVER(socfpga_dtreg) = {
+ .name = "socfpga-dtreg",
+ .id = UCLASS_NOP,
+ .of_match = socfpga_dtreg_ids,
+ .probe = socfpga_dtreg_probe,
+};
diff --git a/drivers/misc/turris_omnia_mcu.c b/drivers/misc/turris_omnia_mcu.c
new file mode 100644
index 0000000..6b2f17c
--- /dev/null
+++ b/drivers/misc/turris_omnia_mcu.c
@@ -0,0 +1,411 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2022 Pali Rohár <pali@kernel.org>
+ * Copyright (C) 2024 Marek Behún <kabel@kernel.org>
+ */
+
+#include <common.h>
+#include <console.h>
+#include <dm.h>
+#include <dm/lists.h>
+#include <i2c.h>
+#include <rng.h>
+#include <sysreset.h>
+#include <turris-omnia-mcu-interface.h>
+#include <asm/byteorder.h>
+#include <asm/gpio.h>
+#include <linux/delay.h>
+#include <linux/log2.h>
+
+#define CMD_TRNG_MAX_ENTROPY_LEN 64
+
+struct turris_omnia_mcu_info {
+ u32 features;
+};
+
+static int omnia_gpio_get_function(struct udevice *dev, uint offset)
+{
+ struct turris_omnia_mcu_info *info = dev_get_priv(dev->parent);
+
+ switch (offset) {
+ /* bank 0 */
+ case 0 ... 15:
+ switch (offset) {
+ case ilog2(STS_USB30_PWRON):
+ case ilog2(STS_USB31_PWRON):
+ case ilog2(STS_ENABLE_4V5):
+ case ilog2(STS_BUTTON_MODE):
+ return GPIOF_OUTPUT;
+ default:
+ return GPIOF_INPUT;
+ }
+
+ /* bank 1 - supported only when FEAT_EXT_CMDS is set */
+ case (16 + 0) ... (16 + 31):
+ if (!(info->features & FEAT_EXT_CMDS))
+ return -EINVAL;
+ return GPIOF_INPUT;
+
+ /* bank 2 - supported only when FEAT_EXT_CMDS and FEAT_PERIPH_MCU is set */
+ case (16 + 32 + 0) ... (16 + 32 + 15):
+ if (!(info->features & FEAT_EXT_CMDS))
+ return -EINVAL;
+ if (!(info->features & FEAT_PERIPH_MCU))
+ return -EINVAL;
+ return GPIOF_OUTPUT;
+
+ default:
+ return -EINVAL;
+ }
+}
+
+static int omnia_gpio_get_value(struct udevice *dev, uint offset)
+{
+ struct turris_omnia_mcu_info *info = dev_get_priv(dev->parent);
+ u32 val32;
+ u16 val16;
+ int ret;
+
+ switch (offset) {
+ /* bank 0 */
+ case 0 ... 15:
+ ret = dm_i2c_read(dev->parent, CMD_GET_STATUS_WORD,
+ (void *)&val16, sizeof(val16));
+ if (ret)
+ return ret;
+
+ return !!(le16_to_cpu(val16) & BIT(offset));
+
+ /* bank 1 - supported only when FEAT_EXT_CMDS is set */
+ case (16 + 0) ... (16 + 31):
+ if (!(info->features & FEAT_EXT_CMDS))
+ return -EINVAL;
+
+ ret = dm_i2c_read(dev->parent, CMD_GET_EXT_STATUS_DWORD,
+ (void *)&val32, sizeof(val32));
+ if (ret)
+ return ret;
+
+ return !!(le32_to_cpu(val32) & BIT(offset - 16));
+
+ /* bank 2 - supported only when FEAT_EXT_CMDS and FEAT_PERIPH_MCU is set */
+ case (16 + 32 + 0) ... (16 + 32 + 15):
+ if (!(info->features & FEAT_EXT_CMDS))
+ return -EINVAL;
+ if (!(info->features & FEAT_PERIPH_MCU))
+ return -EINVAL;
+
+ ret = dm_i2c_read(dev->parent, CMD_GET_EXT_CONTROL_STATUS,
+ (void *)&val16, sizeof(val16));
+ if (ret)
+ return ret;
+
+ return !!(le16_to_cpu(val16) & BIT(offset - 16 - 32));
+
+ default:
+ return -EINVAL;
+ }
+}
+
+static int omnia_gpio_set_value(struct udevice *dev, uint offset, int value)
+{
+ struct turris_omnia_mcu_info *info = dev_get_priv(dev->parent);
+ u16 valmask16[2];
+ u8 valmask8[2];
+
+ switch (offset) {
+ /* bank 0 */
+ case 0 ... 15:
+ switch (offset) {
+ case ilog2(STS_USB30_PWRON):
+ valmask8[1] = CTL_USB30_PWRON;
+ break;
+ case ilog2(STS_USB31_PWRON):
+ valmask8[1] = CTL_USB31_PWRON;
+ break;
+ case ilog2(STS_ENABLE_4V5):
+ valmask8[1] = CTL_ENABLE_4V5;
+ break;
+ case ilog2(STS_BUTTON_MODE):
+ valmask8[1] = CTL_BUTTON_MODE;
+ break;
+ default:
+ return -EINVAL;
+ }
+
+ valmask8[0] = value ? valmask8[1] : 0;
+
+ return dm_i2c_write(dev->parent, CMD_GENERAL_CONTROL, valmask8,
+ sizeof(valmask8));
+
+ /* bank 2 - supported only when FEAT_EXT_CMDS and FEAT_PERIPH_MCU is set */
+ case (16 + 32 + 0) ... (16 + 32 + 15):
+ if (!(info->features & FEAT_EXT_CMDS))
+ return -EINVAL;
+ if (!(info->features & FEAT_PERIPH_MCU))
+ return -EINVAL;
+
+ valmask16[1] = cpu_to_le16(BIT(offset - 16 - 32));
+ valmask16[0] = value ? valmask16[1] : 0;
+
+ return dm_i2c_write(dev->parent, CMD_EXT_CONTROL,
+ (void *)valmask16, sizeof(valmask16));
+
+ default:
+ return -EINVAL;
+ }
+}
+
+static int omnia_gpio_direction_input(struct udevice *dev, uint offset)
+{
+ int ret;
+
+ ret = omnia_gpio_get_function(dev, offset);
+ if (ret < 0)
+ return ret;
+ else if (ret != GPIOF_INPUT)
+ return -EOPNOTSUPP;
+
+ return 0;
+}
+
+static int omnia_gpio_direction_output(struct udevice *dev, uint offset, int value)
+{
+ int ret;
+
+ ret = omnia_gpio_get_function(dev, offset);
+ if (ret < 0)
+ return ret;
+ else if (ret != GPIOF_OUTPUT)
+ return -EOPNOTSUPP;
+
+ return omnia_gpio_set_value(dev, offset, value);
+}
+
+static int omnia_gpio_xlate(struct udevice *dev, struct gpio_desc *desc,
+ struct ofnode_phandle_args *args)
+{
+ uint bank, gpio, flags, offset;
+ int ret;
+
+ if (args->args_count != 3)
+ return -EINVAL;
+
+ bank = args->args[0];
+ gpio = args->args[1];
+ flags = args->args[2];
+
+ switch (bank) {
+ case 0:
+ if (gpio >= 16)
+ return -EINVAL;
+ offset = gpio;
+ break;
+ case 1:
+ if (gpio >= 32)
+ return -EINVAL;
+ offset = 16 + gpio;
+ break;
+ case 2:
+ if (gpio >= 16)
+ return -EINVAL;
+ offset = 16 + 32 + gpio;
+ break;
+ default:
+ return -EINVAL;
+ }
+
+ ret = omnia_gpio_get_function(dev, offset);
+ if (ret < 0)
+ return ret;
+
+ desc->offset = offset;
+ desc->flags = gpio_flags_xlate(flags);
+
+ return 0;
+}
+
+static const struct dm_gpio_ops omnia_gpio_ops = {
+ .direction_input = omnia_gpio_direction_input,
+ .direction_output = omnia_gpio_direction_output,
+ .get_value = omnia_gpio_get_value,
+ .set_value = omnia_gpio_set_value,
+ .get_function = omnia_gpio_get_function,
+ .xlate = omnia_gpio_xlate,
+};
+
+static int omnia_gpio_probe(struct udevice *dev)
+{
+ struct turris_omnia_mcu_info *info = dev_get_priv(dev->parent);
+ struct gpio_dev_priv *uc_priv = dev_get_uclass_priv(dev);
+
+ uc_priv->bank_name = "mcu_";
+
+ if ((info->features & FEAT_EXT_CMDS) && (info->features & FEAT_PERIPH_MCU))
+ uc_priv->gpio_count = 16 + 32 + 16;
+ else if (info->features & FEAT_EXT_CMDS)
+ uc_priv->gpio_count = 16 + 32;
+ else
+ uc_priv->gpio_count = 16;
+
+ return 0;
+}
+
+U_BOOT_DRIVER(turris_omnia_mcu_gpio) = {
+ .name = "turris-omnia-mcu-gpio",
+ .id = UCLASS_GPIO,
+ .ops = &omnia_gpio_ops,
+ .probe = omnia_gpio_probe,
+};
+
+static int omnia_sysreset_request(struct udevice *dev, enum sysreset_t type)
+{
+ struct {
+ u16 magic;
+ u16 arg;
+ u32 csum;
+ } __packed args;
+
+ if (type != SYSRESET_POWER_OFF)
+ return -EPROTONOSUPPORT;
+
+ args.magic = CMD_POWER_OFF_MAGIC;
+ args.arg = CMD_POWER_OFF_POWERON_BUTTON;
+ args.csum = 0xba3b7212;
+
+ return dm_i2c_write(dev->parent, CMD_POWER_OFF, (void *)&args,
+ sizeof(args));
+}
+
+static const struct sysreset_ops omnia_sysreset_ops = {
+ .request = omnia_sysreset_request,
+};
+
+U_BOOT_DRIVER(turris_omnia_mcu_sysreset) = {
+ .name = "turris-omnia-mcu-sysreset",
+ .id = UCLASS_SYSRESET,
+ .ops = &omnia_sysreset_ops,
+};
+
+static int omnia_rng_read(struct udevice *dev, void *data, size_t count)
+{
+ u8 buf[1 + CMD_TRNG_MAX_ENTROPY_LEN];
+ size_t len;
+ int ret;
+
+ while (count) {
+ ret = dm_i2c_read(dev->parent, CMD_TRNG_COLLECT_ENTROPY, buf,
+ sizeof(buf));
+ if (ret)
+ return ret;
+
+ len = min_t(size_t, buf[0],
+ min_t(size_t, CMD_TRNG_MAX_ENTROPY_LEN, count));
+
+ if (!len) {
+ /* wait 500ms (fail if interrupted), then try again */
+ for (int i = 0; i < 5; ++i) {
+ mdelay(100);
+ if (ctrlc())
+ return -EINTR;
+ }
+ continue;
+ }
+
+ memcpy(data, &buf[1], len);
+ data += len;
+ count -= len;
+ }
+
+ return 0;
+}
+
+static const struct dm_rng_ops omnia_rng_ops = {
+ .read = omnia_rng_read,
+};
+
+U_BOOT_DRIVER(turris_omnia_mcu_trng) = {
+ .name = "turris-omnia-mcu-trng",
+ .id = UCLASS_RNG,
+ .ops = &omnia_rng_ops,
+};
+
+static int turris_omnia_mcu_bind(struct udevice *dev)
+{
+ /* bind MCU GPIOs as a child device */
+ return device_bind_driver_to_node(dev, "turris-omnia-mcu-gpio",
+ "turris-omnia-mcu-gpio",
+ dev_ofnode(dev), NULL);
+}
+
+static int turris_omnia_mcu_probe(struct udevice *dev)
+{
+ struct turris_omnia_mcu_info *info = dev_get_priv(dev);
+ u32 dword;
+ u16 word;
+ int ret;
+
+ ret = dm_i2c_read(dev, CMD_GET_STATUS_WORD, (void *)&word, sizeof(word));
+ if (ret < 0) {
+ printf("Error: turris_omnia_mcu CMD_GET_STATUS_WORD failed: %d\n",
+ ret);
+ return ret;
+ }
+
+ if (le16_to_cpu(word) & STS_FEATURES_SUPPORTED) {
+ /* try read 32-bit features */
+ ret = dm_i2c_read(dev, CMD_GET_FEATURES, (void *)&dword,
+ sizeof(dword));
+ if (ret < 0) {
+ /* try read 16-bit features */
+ ret = dm_i2c_read(dev, CMD_GET_FEATURES, (void *)&word,
+ sizeof(word));
+ if (ret < 0) {
+ printf("Error: turris_omnia_mcu CMD_GET_FEATURES failed: %d\n",
+ ret);
+ return ret;
+ }
+
+ info->features = le16_to_cpu(word);
+ } else {
+ info->features = le32_to_cpu(dword);
+ if (info->features & FEAT_FROM_BIT_16_INVALID)
+ info->features &= GENMASK(15, 0);
+ }
+ }
+
+ /* bind sysreset if poweroff is supported */
+ if (info->features & FEAT_POWEROFF_WAKEUP) {
+ ret = device_bind_driver_to_node(dev,
+ "turris-omnia-mcu-sysreset",
+ "turris-omnia-mcu-sysreset",
+ dev_ofnode(dev), NULL);
+ if (ret < 0)
+ return ret;
+ }
+
+ /* bind rng if trng is supported */
+ if (info->features & FEAT_TRNG) {
+ ret = device_bind_driver_to_node(dev, "turris-omnia-mcu-trng",
+ "turris-omnia-mcu-trng",
+ dev_ofnode(dev), NULL);
+ if (ret < 0)
+ return ret;
+ }
+
+ return 0;
+}
+
+static const struct udevice_id turris_omnia_mcu_ids[] = {
+ { .compatible = "cznic,turris-omnia-mcu" },
+ { }
+};
+
+U_BOOT_DRIVER(turris_omnia_mcu) = {
+ .name = "turris-omnia-mcu",
+ .id = UCLASS_MISC,
+ .bind = turris_omnia_mcu_bind,
+ .probe = turris_omnia_mcu_probe,
+ .priv_auto = sizeof(struct turris_omnia_mcu_info),
+ .of_match = turris_omnia_mcu_ids,
+};
diff --git a/drivers/mmc/Kconfig b/drivers/mmc/Kconfig
index cef0579..f7fe6d1 100644
--- a/drivers/mmc/Kconfig
+++ b/drivers/mmc/Kconfig
@@ -568,6 +568,19 @@
If unsure, say N.
+config MMC_SDHCI_CV1800B
+ bool "SDHCI support for the CV1800B SD/SDIO/eMMC controller"
+ depends on BLK && DM_MMC
+ depends on MMC_SDHCI
+ depends on OF_CONTROL
+ help
+ This selects the CV1800B SD/SDIO/eMMC driver.
+
+ If you have a controller with this interface,
+ say Y here.
+
+ If unsure, say N.
+
config MMC_SDHCI_AM654
bool "SDHCI Controller on TI's Am654 devices"
depends on ARCH_K3
diff --git a/drivers/mmc/Makefile b/drivers/mmc/Makefile
index e9cf1fc..3374321 100644
--- a/drivers/mmc/Makefile
+++ b/drivers/mmc/Makefile
@@ -60,6 +60,7 @@
obj-$(CONFIG_MMC_SDHCI_BCM2835) += bcm2835_sdhci.o
obj-$(CONFIG_MMC_SDHCI_BCMSTB) += bcmstb_sdhci.o
obj-$(CONFIG_MMC_SDHCI_CADENCE) += sdhci-cadence.o
+obj-$(CONFIG_MMC_SDHCI_CV1800B) += cv1800b_sdhci.o
obj-$(CONFIG_MMC_SDHCI_AM654) += am654_sdhci.o
obj-$(CONFIG_MMC_SDHCI_IPROC) += iproc_sdhci.o
obj-$(CONFIG_MMC_SDHCI_KONA) += kona_sdhci.o
diff --git a/drivers/mmc/cv1800b_sdhci.c b/drivers/mmc/cv1800b_sdhci.c
new file mode 100644
index 0000000..2275c53
--- /dev/null
+++ b/drivers/mmc/cv1800b_sdhci.c
@@ -0,0 +1,116 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (c) 2024, Kongyang Liu <seashell11234455@gmail.com>
+ */
+
+#include <dm.h>
+#include <mmc.h>
+#include <sdhci.h>
+#include <linux/delay.h>
+
+#define SDHCI_PHY_TX_RX_DLY 0x240
+#define MMC_MAX_CLOCK 375000000
+#define TUNE_MAX_PHCODE 128
+
+struct cv1800b_sdhci_plat {
+ struct mmc_config cfg;
+ struct mmc mmc;
+};
+
+static void cv1800b_set_tap_delay(struct sdhci_host *host, u16 tap)
+{
+ sdhci_writel(host, tap << 16, SDHCI_PHY_TX_RX_DLY);
+}
+
+static void cv1800b_sdhci_reset(struct sdhci_host *host, u8 mask)
+{
+ sdhci_writeb(host, mask, SDHCI_SOFTWARE_RESET);
+ while (sdhci_readb(host, SDHCI_SOFTWARE_RESET) & mask)
+ udelay(10);
+}
+
+static int cv1800b_execute_tuning(struct mmc *mmc, u8 opcode)
+{
+ struct sdhci_host *host = dev_get_priv(mmc->dev);
+
+ u16 tap;
+
+ int current_size = 0;
+ int max_size = 0;
+ int max_window = 0;
+
+ for (tap = 0; tap < TUNE_MAX_PHCODE; tap++) {
+ cv1800b_set_tap_delay(host, tap);
+
+ if (mmc_send_tuning(host->mmc, opcode, NULL)) {
+ current_size = 0;
+ } else {
+ current_size++;
+ if (current_size > max_size) {
+ max_size = current_size;
+ max_window = tap;
+ }
+ }
+ }
+
+ cv1800b_sdhci_reset(host, SDHCI_RESET_CMD | SDHCI_RESET_DATA);
+
+ cv1800b_set_tap_delay(host, max_window - max_size / 2);
+
+ return 0;
+}
+
+const struct sdhci_ops cv1800b_sdhci_sd_ops = {
+ .platform_execute_tuning = cv1800b_execute_tuning,
+};
+
+static int cv1800b_sdhci_bind(struct udevice *dev)
+{
+ struct cv1800b_sdhci_plat *plat = dev_get_plat(dev);
+
+ return sdhci_bind(dev, &plat->mmc, &plat->cfg);
+}
+
+static int cv1800b_sdhci_probe(struct udevice *dev)
+{
+ struct mmc_uclass_priv *upriv = dev_get_uclass_priv(dev);
+ struct cv1800b_sdhci_plat *plat = dev_get_plat(dev);
+ struct sdhci_host *host = dev_get_priv(dev);
+ int ret;
+
+ host->name = dev->name;
+ host->ioaddr = devfdt_get_addr_ptr(dev);
+
+ upriv->mmc = &plat->mmc;
+ host->mmc = &plat->mmc;
+ host->mmc->priv = host;
+ host->mmc->dev = dev;
+ host->ops = &cv1800b_sdhci_sd_ops;
+ host->max_clk = MMC_MAX_CLOCK;
+
+ ret = mmc_of_parse(dev, &plat->cfg);
+ if (ret)
+ return ret;
+
+ ret = sdhci_setup_cfg(&plat->cfg, host, 0, 200000);
+ if (ret)
+ return ret;
+
+ return sdhci_probe(dev);
+}
+
+static const struct udevice_id cv1800b_sdhci_match[] = {
+ { .compatible = "sophgo,cv1800b-dwcmshc" },
+ { }
+};
+
+U_BOOT_DRIVER(cv1800b_sdhci) = {
+ .name = "sdhci-cv1800b",
+ .id = UCLASS_MMC,
+ .of_match = cv1800b_sdhci_match,
+ .bind = cv1800b_sdhci_bind,
+ .probe = cv1800b_sdhci_probe,
+ .priv_auto = sizeof(struct sdhci_host),
+ .plat_auto = sizeof(struct cv1800b_sdhci_plat),
+ .ops = &sdhci_ops,
+};
diff --git a/drivers/mtd/nand/raw/arasan_nfc.c b/drivers/mtd/nand/raw/arasan_nfc.c
index 1476640..ffcd963 100644
--- a/drivers/mtd/nand/raw/arasan_nfc.c
+++ b/drivers/mtd/nand/raw/arasan_nfc.c
@@ -1232,7 +1232,8 @@
struct nand_config *nand = &info->config;
struct mtd_info *mtd;
ofnode child;
- int err = -1;
+ int ret;
+ const char *str;
info->reg = dev_read_addr_ptr(dev);
mtd = nand_to_mtd(nand_chip);
@@ -1258,11 +1259,18 @@
writel(0x0, &info->reg->pgm_reg);
/* first scan to find the device and get the page size */
- if (nand_scan_ident(mtd, CONFIG_SYS_NAND_MAX_CHIPS, NULL)) {
+ ret = nand_scan_ident(mtd, CONFIG_SYS_NAND_MAX_CHIPS, NULL);
+ if (ret) {
printf("%s: nand_scan_ident failed\n", __func__);
- goto fail;
+ return ret;
}
+ str = ofnode_read_string(nand_chip->flash_node, "nand-ecc-mode");
+ if (!str || strcmp(str, "hw") != 0) {
+ printf("%s ecc mode is not supported\n", str);
+ return -EINVAL;
+ }
+
nand_chip->ecc.mode = NAND_ECC_HW;
nand_chip->ecc.hwctl = NULL;
nand_chip->ecc.read_page = arasan_nand_read_page_hwecc;
@@ -1282,26 +1290,26 @@
nand_chip->ecc.bytes = 0;
nand_chip->ecc.layout = &ondie_nand_oob_64;
} else {
- if (arasan_nand_ecc_init(mtd)) {
+ ret = arasan_nand_ecc_init(mtd);
+ if (ret) {
printf("%s: nand_ecc_init failed\n", __func__);
- goto fail;
+ return ret;
}
}
- if (nand_scan_tail(mtd)) {
+ ret = nand_scan_tail(mtd);
+ if (ret) {
printf("%s: nand_scan_tail failed\n", __func__);
- goto fail;
+ return ret;
}
- if (nand_register(0, mtd)) {
+ ret = nand_register(0, mtd);
+ if (ret) {
printf("Nand Register Fail\n");
- goto fail;
+ return ret;
}
- return 0;
-fail:
- free(nand);
- return err;
+ return ret;
}
static const struct udevice_id arasan_nand_dt_ids[] = {
diff --git a/drivers/net/dwc_eth_qos.c b/drivers/net/dwc_eth_qos.c
index 9b3bce1..1b4d0ed 100644
--- a/drivers/net/dwc_eth_qos.c
+++ b/drivers/net/dwc_eth_qos.c
@@ -159,7 +159,7 @@
ret = eqos_mdio_wait_idle(eqos);
if (ret) {
- pr_err("MDIO not idle at entry");
+ pr_err("MDIO not idle at entry\n");
return ret;
}
@@ -179,7 +179,7 @@
ret = eqos_mdio_wait_idle(eqos);
if (ret) {
- pr_err("MDIO read didn't complete");
+ pr_err("MDIO read didn't complete\n");
return ret;
}
@@ -203,7 +203,7 @@
ret = eqos_mdio_wait_idle(eqos);
if (ret) {
- pr_err("MDIO not idle at entry");
+ pr_err("MDIO not idle at entry\n");
return ret;
}
@@ -225,7 +225,7 @@
ret = eqos_mdio_wait_idle(eqos);
if (ret) {
- pr_err("MDIO read didn't complete");
+ pr_err("MDIO read didn't complete\n");
return ret;
}
@@ -242,37 +242,37 @@
ret = clk_enable(&eqos->clk_slave_bus);
if (ret < 0) {
- pr_err("clk_enable(clk_slave_bus) failed: %d", ret);
+ pr_err("clk_enable(clk_slave_bus) failed: %d\n", ret);
goto err;
}
ret = clk_enable(&eqos->clk_master_bus);
if (ret < 0) {
- pr_err("clk_enable(clk_master_bus) failed: %d", ret);
+ pr_err("clk_enable(clk_master_bus) failed: %d\n", ret);
goto err_disable_clk_slave_bus;
}
ret = clk_enable(&eqos->clk_rx);
if (ret < 0) {
- pr_err("clk_enable(clk_rx) failed: %d", ret);
+ pr_err("clk_enable(clk_rx) failed: %d\n", ret);
goto err_disable_clk_master_bus;
}
ret = clk_enable(&eqos->clk_ptp_ref);
if (ret < 0) {
- pr_err("clk_enable(clk_ptp_ref) failed: %d", ret);
+ pr_err("clk_enable(clk_ptp_ref) failed: %d\n", ret);
goto err_disable_clk_rx;
}
ret = clk_set_rate(&eqos->clk_ptp_ref, 125 * 1000 * 1000);
if (ret < 0) {
- pr_err("clk_set_rate(clk_ptp_ref) failed: %d", ret);
+ pr_err("clk_set_rate(clk_ptp_ref) failed: %d\n", ret);
goto err_disable_clk_ptp_ref;
}
ret = clk_enable(&eqos->clk_tx);
if (ret < 0) {
- pr_err("clk_enable(clk_tx) failed: %d", ret);
+ pr_err("clk_enable(clk_tx) failed: %d\n", ret);
goto err_disable_clk_ptp_ref;
}
#endif
@@ -305,26 +305,26 @@
ret = clk_enable(&eqos->clk_master_bus);
if (ret < 0) {
- pr_err("clk_enable(clk_master_bus) failed: %d", ret);
+ pr_err("clk_enable(clk_master_bus) failed: %d\n", ret);
goto err;
}
ret = clk_enable(&eqos->clk_rx);
if (ret < 0) {
- pr_err("clk_enable(clk_rx) failed: %d", ret);
+ pr_err("clk_enable(clk_rx) failed: %d\n", ret);
goto err_disable_clk_master_bus;
}
ret = clk_enable(&eqos->clk_tx);
if (ret < 0) {
- pr_err("clk_enable(clk_tx) failed: %d", ret);
+ pr_err("clk_enable(clk_tx) failed: %d\n", ret);
goto err_disable_clk_rx;
}
if (clk_valid(&eqos->clk_ck) && !eqos->clk_ck_enabled) {
ret = clk_enable(&eqos->clk_ck);
if (ret < 0) {
- pr_err("clk_enable(clk_ck) failed: %d", ret);
+ pr_err("clk_enable(clk_ck) failed: %d\n", ret);
goto err_disable_clk_tx;
}
eqos->clk_ck_enabled = true;
@@ -390,7 +390,7 @@
ret = dm_gpio_set_value(&eqos->phy_reset_gpio, 1);
if (ret < 0) {
- pr_err("dm_gpio_set_value(phy_reset, assert) failed: %d", ret);
+ pr_err("dm_gpio_set_value(phy_reset, assert) failed: %d\n", ret);
return ret;
}
@@ -398,13 +398,13 @@
ret = dm_gpio_set_value(&eqos->phy_reset_gpio, 0);
if (ret < 0) {
- pr_err("dm_gpio_set_value(phy_reset, deassert) failed: %d", ret);
+ pr_err("dm_gpio_set_value(phy_reset, deassert) failed: %d\n", ret);
return ret;
}
ret = reset_assert(&eqos->reset_ctl);
if (ret < 0) {
- pr_err("reset_assert() failed: %d", ret);
+ pr_err("reset_assert() failed: %d\n", ret);
return ret;
}
@@ -412,7 +412,7 @@
ret = reset_deassert(&eqos->reset_ctl);
if (ret < 0) {
- pr_err("reset_deassert() failed: %d", ret);
+ pr_err("reset_deassert() failed: %d\n", ret);
return ret;
}
@@ -448,14 +448,14 @@
ret = wait_for_bit_le32(&eqos->tegra186_regs->auto_cal_status,
EQOS_AUTO_CAL_STATUS_ACTIVE, true, 10, false);
if (ret) {
- pr_err("calibrate didn't start");
+ pr_err("calibrate didn't start\n");
goto failed;
}
ret = wait_for_bit_le32(&eqos->tegra186_regs->auto_cal_status,
EQOS_AUTO_CAL_STATUS_ACTIVE, false, 10, false);
if (ret) {
- pr_err("calibrate didn't finish");
+ pr_err("calibrate didn't finish\n");
goto failed;
}
@@ -586,13 +586,13 @@
rate = 2.5 * 1000 * 1000;
break;
default:
- pr_err("invalid speed %d", eqos->phy->speed);
+ pr_err("invalid speed %d\n", eqos->phy->speed);
return -EINVAL;
}
ret = clk_set_rate(&eqos->clk_tx, rate);
if (ret < 0) {
- pr_err("clk_set_rate(tx_clk, %lu) failed: %d", rate, ret);
+ pr_err("clk_set_rate(tx_clk, %lu) failed: %d\n", rate, ret);
return ret;
}
#endif
@@ -613,7 +613,7 @@
else
ret = eqos_set_half_duplex(dev);
if (ret < 0) {
- pr_err("eqos_set_*_duplex() failed: %d", ret);
+ pr_err("eqos_set_*_duplex() failed: %d\n", ret);
return ret;
}
@@ -631,32 +631,32 @@
ret = eqos_set_mii_speed_10(dev);
break;
default:
- pr_err("invalid speed %d", eqos->phy->speed);
+ pr_err("invalid speed %d\n", eqos->phy->speed);
return -EINVAL;
}
if (ret < 0) {
- pr_err("eqos_set_*mii_speed*() failed: %d", ret);
+ pr_err("eqos_set_*mii_speed*() failed: %d\n", ret);
return ret;
}
if (en_calibration) {
ret = eqos->config->ops->eqos_calibrate_pads(dev);
if (ret < 0) {
- pr_err("eqos_calibrate_pads() failed: %d",
+ pr_err("eqos_calibrate_pads() failed: %d\n",
ret);
return ret;
}
} else {
ret = eqos->config->ops->eqos_disable_calibration(dev);
if (ret < 0) {
- pr_err("eqos_disable_calibration() failed: %d",
+ pr_err("eqos_disable_calibration() failed: %d\n",
ret);
return ret;
}
}
ret = eqos->config->ops->eqos_set_tx_clk_speed(dev);
if (ret < 0) {
- pr_err("eqos_set_tx_clk_speed() failed: %d", ret);
+ pr_err("eqos_set_tx_clk_speed() failed: %d\n", ret);
return ret;
}
@@ -755,7 +755,7 @@
ret = eqos->config->ops->eqos_start_resets(dev);
if (ret < 0) {
- pr_err("eqos_start_resets() failed: %d", ret);
+ pr_err("eqos_start_resets() failed: %d\n", ret);
goto err;
}
@@ -773,13 +773,13 @@
EQOS_DMA_MODE_SWR, false,
eqos->config->swr_wait, false);
if (ret) {
- pr_err("EQOS_DMA_MODE_SWR stuck");
+ pr_err("EQOS_DMA_MODE_SWR stuck\n");
goto err_stop_resets;
}
ret = eqos->config->ops->eqos_calibrate_pads(dev);
if (ret < 0) {
- pr_err("eqos_calibrate_pads() failed: %d", ret);
+ pr_err("eqos_calibrate_pads() failed: %d\n", ret);
goto err_stop_resets;
}
@@ -812,7 +812,7 @@
}
if (!eqos->phy) {
- pr_err("phy_connect() failed");
+ pr_err("phy_connect() failed\n");
ret = -ENODEV;
goto err_stop_resets;
}
@@ -820,7 +820,7 @@
if (eqos->max_speed) {
ret = phy_set_supported(eqos->phy, eqos->max_speed);
if (ret) {
- pr_err("phy_set_supported() failed: %d", ret);
+ pr_err("phy_set_supported() failed: %d\n", ret);
goto err_shutdown_phy;
}
}
@@ -828,26 +828,26 @@
eqos->phy->node = eqos->phy_of_node;
ret = phy_config(eqos->phy);
if (ret < 0) {
- pr_err("phy_config() failed: %d", ret);
+ pr_err("phy_config() failed: %d\n", ret);
goto err_shutdown_phy;
}
}
ret = phy_startup(eqos->phy);
if (ret < 0) {
- pr_err("phy_startup() failed: %d", ret);
+ pr_err("phy_startup() failed: %d\n", ret);
goto err_shutdown_phy;
}
if (!eqos->phy->link) {
- pr_err("No link");
+ pr_err("No link\n");
ret = -EAGAIN;
goto err_shutdown_phy;
}
ret = eqos_adjust_link(dev);
if (ret < 0) {
- pr_err("eqos_adjust_link() failed: %d", ret);
+ pr_err("eqos_adjust_link() failed: %d\n", ret);
goto err_shutdown_phy;
}
@@ -1090,7 +1090,7 @@
err_stop_resets:
eqos->config->ops->eqos_stop_resets(dev);
err:
- pr_err("FAILED: %d", ret);
+ pr_err("FAILED: %d\n", ret);
return ret;
}
@@ -1361,7 +1361,7 @@
ret = reset_get_by_name(dev, "eqos", &eqos->reset_ctl);
if (ret) {
- pr_err("reset_get_by_name(rst) failed: %d", ret);
+ pr_err("reset_get_by_name(rst) failed: %d\n", ret);
return ret;
}
@@ -1369,37 +1369,37 @@
&eqos->phy_reset_gpio,
GPIOD_IS_OUT | GPIOD_IS_OUT_ACTIVE);
if (ret) {
- pr_err("gpio_request_by_name(phy reset) failed: %d", ret);
+ pr_err("gpio_request_by_name(phy reset) failed: %d\n", ret);
goto err_free_reset_eqos;
}
ret = clk_get_by_name(dev, "slave_bus", &eqos->clk_slave_bus);
if (ret) {
- pr_err("clk_get_by_name(slave_bus) failed: %d", ret);
+ pr_err("clk_get_by_name(slave_bus) failed: %d\n", ret);
goto err_free_gpio_phy_reset;
}
ret = clk_get_by_name(dev, "master_bus", &eqos->clk_master_bus);
if (ret) {
- pr_err("clk_get_by_name(master_bus) failed: %d", ret);
+ pr_err("clk_get_by_name(master_bus) failed: %d\n", ret);
goto err_free_gpio_phy_reset;
}
ret = clk_get_by_name(dev, "rx", &eqos->clk_rx);
if (ret) {
- pr_err("clk_get_by_name(rx) failed: %d", ret);
+ pr_err("clk_get_by_name(rx) failed: %d\n", ret);
goto err_free_gpio_phy_reset;
}
ret = clk_get_by_name(dev, "ptp_ref", &eqos->clk_ptp_ref);
if (ret) {
- pr_err("clk_get_by_name(ptp_ref) failed: %d", ret);
+ pr_err("clk_get_by_name(ptp_ref) failed: %d\n", ret);
goto err_free_gpio_phy_reset;
}
ret = clk_get_by_name(dev, "tx", &eqos->clk_tx);
if (ret) {
- pr_err("clk_get_by_name(tx) failed: %d", ret);
+ pr_err("clk_get_by_name(tx) failed: %d\n", ret);
goto err_free_gpio_phy_reset;
}
@@ -1436,19 +1436,19 @@
ret = clk_get_by_name(dev, "stmmaceth", &eqos->clk_master_bus);
if (ret) {
- pr_err("clk_get_by_name(master_bus) failed: %d", ret);
+ pr_err("clk_get_by_name(master_bus) failed: %d\n", ret);
goto err_probe;
}
ret = clk_get_by_name(dev, "mac-clk-rx", &eqos->clk_rx);
if (ret) {
- pr_err("clk_get_by_name(rx) failed: %d", ret);
+ pr_err("clk_get_by_name(rx) failed: %d\n", ret);
goto err_probe;
}
ret = clk_get_by_name(dev, "mac-clk-tx", &eqos->clk_tx);
if (ret) {
- pr_err("clk_get_by_name(tx) failed: %d", ret);
+ pr_err("clk_get_by_name(tx) failed: %d\n", ret);
goto err_probe;
}
@@ -1502,7 +1502,7 @@
eqos->regs = dev_read_addr(dev);
if (eqos->regs == FDT_ADDR_T_NONE) {
- pr_err("dev_read_addr() failed");
+ pr_err("dev_read_addr() failed\n");
return -ENODEV;
}
eqos->mac_regs = (void *)(eqos->regs + EQOS_MAC_REGS_BASE);
@@ -1514,19 +1514,19 @@
ret = eqos_probe_resources_core(dev);
if (ret < 0) {
- pr_err("eqos_probe_resources_core() failed: %d", ret);
+ pr_err("eqos_probe_resources_core() failed: %d\n", ret);
return ret;
}
ret = eqos->config->ops->eqos_probe_resources(dev);
if (ret < 0) {
- pr_err("eqos_probe_resources() failed: %d", ret);
+ pr_err("eqos_probe_resources() failed: %d\n", ret);
goto err_remove_resources_core;
}
ret = eqos->config->ops->eqos_start_clks(dev);
if (ret < 0) {
- pr_err("eqos_start_clks() failed: %d", ret);
+ pr_err("eqos_start_clks() failed: %d\n", ret);
goto err_remove_resources_tegra;
}
@@ -1536,7 +1536,7 @@
if (!eqos->mii) {
eqos->mii = mdio_alloc();
if (!eqos->mii) {
- pr_err("mdio_alloc() failed");
+ pr_err("mdio_alloc() failed\n");
ret = -ENOMEM;
goto err_stop_clks;
}
@@ -1547,7 +1547,7 @@
ret = mdio_register(eqos->mii);
if (ret < 0) {
- pr_err("mdio_register() failed: %d", ret);
+ pr_err("mdio_register() failed: %d\n", ret);
goto err_free_mdio;
}
}
diff --git a/drivers/net/e1000.c b/drivers/net/e1000.c
index 84a2a7c..4e7ba66 100644
--- a/drivers/net/e1000.c
+++ b/drivers/net/e1000.c
@@ -116,6 +116,8 @@
{ PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_I210_SERDES) },
{ PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_I210_SERDES_FLASHLESS) },
{ PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_I210_1000BASEKX) },
+ { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_I225_UNPROGRAMMED) },
+ { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_I225_IT) },
{}
};
@@ -1575,6 +1577,8 @@
case PCI_DEVICE_ID_INTEL_I210_SERDES:
case PCI_DEVICE_ID_INTEL_I210_SERDES_FLASHLESS:
case PCI_DEVICE_ID_INTEL_I210_1000BASEKX:
+ case PCI_DEVICE_ID_INTEL_I225_UNPROGRAMMED:
+ case PCI_DEVICE_ID_INTEL_I225_IT:
hw->mac_type = e1000_igb;
break;
default:
@@ -3258,7 +3262,8 @@
if (ret_val)
return ret_val;
} else if (hw->phy_type == e1000_phy_m88 ||
- hw->phy_type == e1000_phy_igb) {
+ hw->phy_type == e1000_phy_igb ||
+ hw->phy_type == e1000_phy_igc) {
ret_val = e1000_copper_link_mgp_setup(hw);
if (ret_val)
return ret_val;
@@ -4531,6 +4536,8 @@
case e1000_igb:
while (timeout) {
if (hw->mac_type == e1000_igb) {
+ if (hw->phy_type == e1000_phy_igc)
+ break;
if (E1000_READ_REG(hw, I210_EEMNGCTL) & cfg_mask)
break;
} else {
@@ -4769,6 +4776,7 @@
case e1000_phy_igp_3:
case e1000_phy_ife:
case e1000_phy_igb:
+ case e1000_phy_igc:
ret_val = e1000_phy_hw_reset(hw);
if (ret_val)
return ret_val;
@@ -4834,6 +4842,9 @@
case I210_I_PHY_ID:
hw->phy_type = e1000_phy_igb;
break;
+ case I225_I_PHY_ID:
+ hw->phy_type = e1000_phy_igc;
+ break;
/* Fall Through */
default:
/* Should never have loaded on this device */
@@ -4941,6 +4952,8 @@
case e1000_igb:
if (hw->phy_id == I210_I_PHY_ID)
match = true;
+ if (hw->phy_id == I225_I_PHY_ID)
+ match = true;
break;
default:
DEBUGOUT("Invalid MAC type %d\n", hw->mac_type);
diff --git a/drivers/net/e1000.h b/drivers/net/e1000.h
index f788394..e131112 100644
--- a/drivers/net/e1000.h
+++ b/drivers/net/e1000.h
@@ -212,6 +212,7 @@
e1000_phy_igp_3,
e1000_phy_ife,
e1000_phy_igb,
+ e1000_phy_igc,
e1000_phy_bm,
e1000_phy_undefined = 0xFF
} e1000_phy_type;
@@ -2420,6 +2421,7 @@
#define BME1000_E_PHY_ID 0x01410CB0
#define I210_I_PHY_ID 0x01410C00
+#define I225_I_PHY_ID 0x67C9DCC0
/* Miscellaneous PHY bit definitions. */
#define PHY_PREAMBLE 0xFFFFFFFF
diff --git a/drivers/net/fec_mxc.c b/drivers/net/fec_mxc.c
index ac93767..90af18f 100644
--- a/drivers/net/fec_mxc.c
+++ b/drivers/net/fec_mxc.c
@@ -1310,7 +1310,7 @@
#ifdef CONFIG_DM_REGULATOR
if (priv->phy_supply) {
- ret = regulator_set_enable(priv->phy_supply, true);
+ ret = regulator_set_enable_if_allowed(priv->phy_supply, true);
if (ret) {
printf("%s: Error enabling phy supply\n", dev->name);
return ret;
diff --git a/drivers/net/gmac_rockchip.c b/drivers/net/gmac_rockchip.c
index 04008d2..c1bae3f 100644
--- a/drivers/net/gmac_rockchip.c
+++ b/drivers/net/gmac_rockchip.c
@@ -13,7 +13,6 @@
#include <phy.h>
#include <syscon.h>
#include <asm/global_data.h>
-#include <asm/io.h>
#include <asm/arch-rockchip/periph.h>
#include <asm/arch-rockchip/clock.h>
#include <asm/arch-rockchip/hardware.h>
diff --git a/drivers/net/hifemac.c b/drivers/net/hifemac.c
index b61a29e..90cc247 100644
--- a/drivers/net/hifemac.c
+++ b/drivers/net/hifemac.c
@@ -15,6 +15,9 @@
#include <wait_bit.h>
#include <asm/io.h>
#include <dm/device_compat.h>
+#include <dm/lists.h>
+#include <linux/bitfield.h>
+#include <linux/ethtool.h>
#include <linux/delay.h>
#include <linux/kernel.h>
@@ -124,6 +127,57 @@
u32 link_status;
};
+struct hisi_femac_stat_entry {
+ const char *name;
+ u32 offset;
+ u32 mask;
+};
+
+/* please refer to the datasheet for the description of these entries */
+static const struct hisi_femac_stat_entry hisi_femac_stats_table[] = {
+ { "rxsof_cnt", 0x584, GENMASK(31, 28) },
+ { "rxeof_cnt", 0x584, GENMASK(27, 24) },
+ { "rxcrcok_cnt", 0x584, GENMASK(23, 20) },
+ { "rxcrcbad_cnt", 0x584, GENMASK(19, 16) },
+ { "txsof_cnt", 0x584, GENMASK(15, 12) },
+ { "txeof_cnt", 0x584, GENMASK(11, 8) },
+ { "txcrcok_cnt", 0x584, GENMASK(7, 4) },
+ { "txcrcbad_cnt", 0x584, GENMASK(3, 0) },
+ { "pkts_cpu", 0x5a0, GENMASK(15, 0) },
+ { "addr_cpu", 0x5a4, GENMASK(15, 0) },
+ { "pkts_port", 0x5a8, GENMASK(15, 0) },
+ { "pkts_cpu2tx", 0x5ac, GENMASK(15, 0) },
+ { "rxdvrise", 0x600, GENMASK(31, 0) },
+ { "ifinoctets", 0x604, GENMASK(31, 0) },
+ { "octets_rx", 0x608, GENMASK(31, 0) },
+ { "local_mac_match", 0x60c, GENMASK(31, 0) },
+ { "pkts", 0x610, GENMASK(31, 0) },
+ { "broadcastpkts", 0x614, GENMASK(31, 0) },
+ { "multicastpkts", 0x618, GENMASK(31, 0) },
+ { "ifinucastpkts", 0x61c, GENMASK(31, 0) },
+ { "ifinerrors", 0x620, GENMASK(31, 0) },
+ { "crcerr", 0x624, GENMASK(31, 0) },
+ { "abnormalsizepkts", 0x628, GENMASK(31, 0) },
+ { "dot3alignmenterr", 0x62c, GENMASK(31, 0) },
+ { "dot3pause", 0x630, GENMASK(31, 0) },
+ { "dropevents", 0x634, GENMASK(31, 0) },
+ { "flux_frame_cnt", 0x638, GENMASK(31, 0) },
+ { "flux_drop_cnt", 0x63c, GENMASK(31, 0) },
+ { "mac_not2cpu_pkts", 0x64c, GENMASK(31, 0) },
+ { "pkts_tx", 0x780, GENMASK(31, 0) },
+ { "broadcastpkts_tx", 0x784, GENMASK(31, 0) },
+ { "multicastpkts_tx", 0x788, GENMASK(31, 0) },
+ { "ifoutucastpkts_tx", 0x78c, GENMASK(31, 0) },
+ { "octets_tx", 0x790, GENMASK(31, 0) },
+ { "dot3pause", 0x794, GENMASK(31, 0) },
+ { "retry_times_tx", 0x798, GENMASK(31, 0) },
+ { "collisions", 0x79c, GENMASK(31, 0) },
+ { "dot3latecol", 0x7a0, GENMASK(31, 0) },
+ { "dot3colok", 0x7a4, GENMASK(31, 0) },
+ { "dot3excessivecol", 0x7a8, GENMASK(31, 0) },
+ { "dot3colcnt", 0x7ac, GENMASK(31, 0) },
+};
+
static void hisi_femac_irq_enable(struct hisi_femac_priv *priv, int irqs)
{
u32 val;
@@ -245,8 +299,10 @@
hisi_femac_rx_refill(priv);
ret = phy_startup(priv->phy);
- if (ret)
- return log_msg_ret("Failed to startup phy", ret);
+ if (ret) {
+ dev_err(dev, "Failed to startup phy: %d\n", ret);
+ return log_msg_ret("phy", ret);
+ }
if (!priv->phy->link) {
debug("%s: link down\n", __func__);
@@ -281,8 +337,10 @@
// wait until FIFO is empty
ret = wait_for_bit_le32(priv->glb_base + GLB_IRQ_RAW, IRQ_INT_TX_PER_PACKET, true, 50, false);
- if (ret == -ETIMEDOUT)
- return log_msg_ret("FIFO timeout", ret);
+ if (ret == -ETIMEDOUT) {
+ dev_err(dev, "FIFO timeout\n");
+ return log_msg_ret("net", ret);
+ }
return 0;
}
@@ -329,10 +387,43 @@
writel(SOFT_RESET_ALL, priv->glb_base + GLB_SOFT_RESET);
}
+static int hisi_femac_get_sset_count(struct udevice *dev)
+{
+ return ARRAY_SIZE(hisi_femac_stats_table);
+}
+
+static void hisi_femac_get_strings(struct udevice *dev, u8 *data)
+{
+ int i;
+
+ for (i = 0; i < ARRAY_SIZE(hisi_femac_stats_table); i++)
+ strcpy(data + i * ETH_GSTRING_LEN, hisi_femac_stats_table[i].name);
+}
+
+/* Non-constant mask variant of FIELD_GET/FIELD_PREP */
+#define field_get(_mask, _reg) (((_reg) & (_mask)) >> (ffs(_mask) - 1))
+
+static void hisi_femac_get_stats(struct udevice *dev, u64 *data)
+{
+ int i;
+ u32 mask, reg;
+ struct hisi_femac_priv *priv = dev_get_priv(dev);
+ void __iomem *port_base = priv->port_base;
+
+ for (i = 0; i < ARRAY_SIZE(hisi_femac_stats_table); i++) {
+ mask = hisi_femac_stats_table[i].mask;
+ reg = readl(port_base + hisi_femac_stats_table[i].offset);
+
+ data[i] = field_get(mask, reg);
+ }
+}
+
-int hisi_femac_of_to_plat(struct udevice *dev)
+static int hisi_femac_of_to_plat(struct udevice *dev)
{
int ret, i;
struct hisi_femac_priv *priv = dev_get_priv(dev);
+ ofnode mdio_node;
+ bool mdio_registered = false;
static const char * const clk_strs[] = {
[CLK_MAC] = "mac",
[CLK_BUS] = "bus",
@@ -340,40 +431,75 @@
};
priv->port_base = dev_remap_addr_name(dev, "port");
- if (IS_ERR(priv->port_base))
- return log_msg_ret("Failed to remap port address space", PTR_ERR(priv->port_base));
+ if (!priv->port_base) {
+ dev_err(dev, "Failed to remap port address space\n");
+ return log_msg_ret("net", -EINVAL);
+ }
priv->glb_base = dev_remap_addr_name(dev, "glb");
- if (IS_ERR(priv->glb_base))
- return log_msg_ret("Failed to remap global address space", PTR_ERR(priv->glb_base));
+ if (IS_ERR(priv->glb_base)) {
+ dev_err(dev, "Failed to remap global address space\n");
+ return log_msg_ret("net", -EINVAL);
+ }
for (i = 0; i < ARRAY_SIZE(clk_strs); i++) {
priv->clks[i] = devm_clk_get(dev, clk_strs[i]);
if (IS_ERR(priv->clks[i])) {
dev_err(dev, "Error getting clock %s\n", clk_strs[i]);
- return log_msg_ret("Failed to get clocks", PTR_ERR(priv->clks[i]));
+ return log_msg_ret("clk", PTR_ERR(priv->clks[i]));
}
}
priv->mac_rst = devm_reset_control_get(dev, "mac");
- if (IS_ERR(priv->mac_rst))
- return log_msg_ret("Failed to get MAC reset", PTR_ERR(priv->mac_rst));
+ if (IS_ERR(priv->mac_rst)) {
+ dev_err(dev, "Failed to get MAC reset %ld\n", PTR_ERR(priv->mac_rst));
+ return log_msg_ret("rst", PTR_ERR(priv->mac_rst));
+ }
priv->phy_rst = devm_reset_control_get(dev, "phy");
- if (IS_ERR(priv->phy_rst))
- return log_msg_ret("Failed to get PHY reset", PTR_ERR(priv->phy_rst));
+ if (IS_ERR(priv->phy_rst)) {
+ dev_err(dev, "Failed to get PHY reset %ld\n", PTR_ERR(priv->phy_rst));
+ return log_msg_ret("rst", PTR_ERR(priv->phy_rst));
+ }
ret = dev_read_u32_array(dev,
PHY_RESET_DELAYS_PROPERTY,
priv->phy_reset_delays,
DELAYS_NUM);
- if (ret < 0)
- return log_msg_ret("Failed to get PHY reset delays", ret);
+ if (ret < 0) {
+ dev_err(dev, "Failed to get PHY reset delays %d\n", ret);
+ return log_msg_ret("rst", ret);
+ }
priv->mac_reset_delay = dev_read_u32_default(dev,
MAC_RESET_DELAY_PROPERTY,
MAC_RESET_ASSERT_PERIOD);
+ /* Create MDIO bus */
+ ofnode_for_each_subnode(mdio_node, dev_ofnode(dev)) {
+ const char *subnode_name = ofnode_get_name(mdio_node);
+ struct udevice *mdiodev;
+
+ // Skip subnodes not starting with "mdio"
+ if (strncmp(subnode_name, "mdio", 4))
+ continue;
+
+ ret = device_bind_driver_to_node(dev, "hisi-femac-mdio",
+ subnode_name, mdio_node, &mdiodev);
+ if (ret) {
+ dev_err(dev, "Failed to register MDIO bus device %d\n", ret);
+ return log_msg_ret("net", ret);
+ }
+
+ mdio_registered = true;
+ break;
+ }
+
+ if (!mdio_registered) {
+ dev_err(dev, "No MDIO subnode is found!\n");
+ return log_msg_ret("mdio", -ENODATA);
+ }
+
return 0;
}
@@ -385,37 +511,49 @@
// Disable MAC clk before phy reset
ret = clk_disable(priv->clks[CLK_MAC]);
- if (ret < 0)
- return log_msg_ret("Failed to disable MAC clock", ret);
+ if (ret < 0) {
+ pr_err("%s: Failed to disable MAC clock %d\n", __func__, ret);
+ return log_msg_ret("clk", ret);
+ }
ret = clk_disable(priv->clks[CLK_BUS]);
- if (ret < 0)
- return log_msg_ret("Failed to disable bus clock", ret);
+ if (ret < 0) {
+ pr_err("%s: Failed to disable bus clock %d\n", __func__, ret);
+ return log_msg_ret("clk", ret);
+ }
udelay(delays[PRE_DELAY]);
ret = reset_assert(rst);
- if (ret < 0)
- return log_msg_ret("Failed to assert reset", ret);
+ if (ret < 0) {
+ pr_err("%s: Failed to assert reset %d\n", __func__, ret);
+ return log_msg_ret("rst", ret);
+ }
udelay(delays[PULSE]);
ret = reset_deassert(rst);
- if (ret < 0)
- return log_msg_ret("Failed to deassert reset", ret);
+ if (ret < 0) {
+ pr_err("%s: Failed to deassert reset %d\n", __func__, ret);
+ return log_msg_ret("rst", ret);
+ }
udelay(delays[POST_DELAY]);
ret = clk_enable(priv->clks[CLK_MAC]);
- if (ret < 0)
- return log_msg_ret("Failed to enable MAC clock", ret);
+ if (ret < 0) {
+ pr_err("%s: Failed to enable MAC clock %d\n", __func__, ret);
+ return log_msg_ret("clk", ret);
+ }
ret = clk_enable(priv->clks[CLK_BUS]);
- if (ret < 0)
- return log_msg_ret("Failed to enable MAC bus clock", ret);
+ if (ret < 0) {
+ pr_err("%s: Failed to enable MAC bus clock %d\n", __func__, ret);
+ return log_msg_ret("clk", ret);
+ }
return 0;
}
-int hisi_femac_probe(struct udevice *dev)
+static int hisi_femac_probe(struct udevice *dev)
{
struct hisi_femac_priv *priv = dev_get_priv(dev);
int ret, i;
@@ -423,30 +561,40 @@
// Enable clocks
for (i = 0; i < CLK_NUM; i++) {
ret = clk_prepare_enable(priv->clks[i]);
- if (ret < 0)
- return log_msg_ret("Failed to enable clks", ret);
+ if (ret < 0) {
+ dev_err(dev, "Failed to enable clk %d: %d\n", i, ret);
+ return log_msg_ret("clk", ret);
+ }
}
// Reset MAC
ret = reset_assert(priv->mac_rst);
- if (ret < 0)
- return log_msg_ret("Failed to assert MAC reset", ret);
+ if (ret < 0) {
+ dev_err(dev, "Failed to assert MAC reset: %d\n", ret);
+ return log_msg_ret("net", ret);
+ }
udelay(priv->mac_reset_delay);
ret = reset_deassert(priv->mac_rst);
- if (ret < 0)
- return log_msg_ret("Failed to deassert MAC reset", ret);
+ if (ret < 0) {
+ dev_err(dev, "Failed to deassert MAC reset: %d\n", ret);
+ return log_msg_ret("net", ret);
+ }
// Reset PHY
ret = hisi_femac_phy_reset(priv);
- if (ret < 0)
- return log_msg_ret("Failed to reset phy", ret);
+ if (ret < 0) {
+ dev_err(dev, "Failed to reset PHY: %d\n", ret);
+ return log_msg_ret("net", ret);
+ }
// Connect to PHY
priv->phy = dm_eth_phy_connect(dev);
- if (!priv->phy)
- return log_msg_ret("Failed to connect to phy", -EINVAL);
+ if (!priv->phy) {
+ dev_err(dev, "Failed to connect to phy\n");
+ return log_msg_ret("phy", -EINVAL);
+ }
hisi_femac_port_init(priv);
return 0;
@@ -459,6 +607,9 @@
.free_pkt = hisi_femac_free_pkt,
.stop = hisi_femac_stop,
.write_hwaddr = hisi_femac_set_hw_mac_addr,
+ .get_sset_count = hisi_femac_get_sset_count,
+ .get_strings = hisi_femac_get_strings,
+ .get_stats = hisi_femac_get_stats,
};
static const struct udevice_id hisi_femac_ids[] = {
diff --git a/drivers/net/hifemac_mdio.c b/drivers/net/hifemac_mdio.c
index 343c5f3..0b59d06 100644
--- a/drivers/net/hifemac_mdio.c
+++ b/drivers/net/hifemac_mdio.c
@@ -8,6 +8,7 @@
#include <dm.h>
#include <clk.h>
#include <miiphy.h>
+#include <dm/device_compat.h>
#include <linux/io.h>
#include <linux/iopoll.h>
@@ -74,7 +75,8 @@
data->membase = dev_remap_addr(dev);
if (IS_ERR(data->membase)) {
ret = PTR_ERR(data->membase);
- return log_msg_ret("Failed to remap base addr", ret);
+ dev_err(dev, "Failed to remap base addr %d\n", ret);
+ return log_msg_ret("mdio", ret);
}
// clk is optional
@@ -89,8 +91,10 @@
int ret;
ret = clk_prepare_enable(data->clk);
- if (ret)
- return log_msg_ret("Failed to enable clk", ret);
+ if (ret) {
+ dev_err(dev, "Failed to enable clock: %d\n", ret);
+ return log_msg_ret("clk", ret);
+ }
return 0;
}
@@ -112,5 +116,6 @@
.of_to_plat = hisi_femac_mdio_of_to_plat,
.probe = hisi_femac_mdio_probe,
.ops = &hisi_femac_mdio_ops,
+ .plat_auto = sizeof(struct mdio_perdev_priv),
.priv_auto = sizeof(struct hisi_femac_mdio_data),
};
diff --git a/drivers/net/phy/broadcom.c b/drivers/net/phy/broadcom.c
index 82e3bbe..ecccb7c 100644
--- a/drivers/net/phy/broadcom.c
+++ b/drivers/net/phy/broadcom.c
@@ -42,6 +42,12 @@
#define BCM54810_SHD_CLK_CTL 0x3
#define BCM54810_SHD_CLK_CTL_GTXCLK_EN BIT(9)
+#define BCM54XX_SHD_LEDS1 0x0d
+#define BCM_LED_SRC_LINKSPD2 0x1
+#define BCM_LED_SRC_ACTIVITYLED 0x3
+#define BCM54XX_SHD_LEDS1_LED3(src) (((src) & 0xf) << 4)
+#define BCM54XX_SHD_LEDS1_LED1(src) (((src) & 0xf) << 0)
+
static int bcm54xx_auxctl_read(struct phy_device *phydev, u16 regnum)
{
/* The register must be written to both the Shadow Register Select and
@@ -148,7 +154,16 @@
if (ret < 0)
return ret;
+ ret = bcm5461_config(phydev);
+ if (ret < 0)
+ return ret;
+
- return bcm5461_config(phydev);
+ /* Configure LEDs to blink. */
+ bcm_phy_write_shadow(phydev, BCM54XX_SHD_LEDS1,
+ BCM54XX_SHD_LEDS1_LED1(BCM_LED_SRC_ACTIVITYLED) |
+ BCM54XX_SHD_LEDS1_LED3(BCM_LED_SRC_LINKSPD2));
+
+ return 0;
}
static int bcm54xx_parse_status(struct phy_device *phydev)
diff --git a/drivers/net/phy/ethernet_id.c b/drivers/net/phy/ethernet_id.c
index 6cb1fd4..4dfdee6 100644
--- a/drivers/net/phy/ethernet_id.c
+++ b/drivers/net/phy/ethernet_id.c
@@ -18,12 +18,11 @@
{
struct phy_device *phydev;
struct ofnode_phandle_args phandle_args;
- struct gpio_desc gpio;
const char *node_name;
struct udevice *pdev;
- ofnode node;
- u32 id, assert, deassert;
u16 vendor, device;
+ ofnode node;
+ u32 id;
int ret;
if (dev_read_phandle_with_args(dev, "phy-handle", NULL, 0, 0,
@@ -41,35 +40,9 @@
return NULL;
}
- if (!IS_ENABLED(CONFIG_DM_ETH_PHY)) {
- ret = gpio_request_by_name_nodev(node, "reset-gpios", 0, &gpio,
- GPIOD_IS_OUT | GPIOD_ACTIVE_LOW);
- if (!ret) {
- assert = ofnode_read_u32_default(node,
- "reset-assert-us", 0);
- deassert = ofnode_read_u32_default(node,
- "reset-deassert-us",
- 0);
- ret = dm_gpio_set_value(&gpio, 1);
- if (ret) {
- dev_err(dev,
- "Failed assert gpio, err: %d\n", ret);
- return NULL;
- }
-
- udelay(assert);
-
- ret = dm_gpio_set_value(&gpio, 0);
- if (ret) {
- dev_err(dev,
- "Failed deassert gpio, err: %d\n",
- ret);
- return NULL;
- }
-
- udelay(deassert);
- }
- }
+ ret = phy_gpio_reset(dev);
+ if (ret)
+ return NULL;
if (phyaddr == -1)
phyaddr = ofnode_read_u32_default(phandle_args.node, "reg", -1);
diff --git a/drivers/net/phy/ncsi.c b/drivers/net/phy/ncsi.c
index eb3fd65..2bca116 100644
--- a/drivers/net/phy/ncsi.c
+++ b/drivers/net/phy/ncsi.c
@@ -286,11 +286,11 @@
}
c = &ncsi_priv->packages[np].channels[nc];
- c->cap_generic = ntohl(gc->cap) & NCSI_CAP_GENERIC_MASK;
- c->cap_bc = ntohl(gc->bc_cap) & NCSI_CAP_BC_MASK;
- c->cap_mc = ntohl(gc->mc_cap) & NCSI_CAP_MC_MASK;
- c->cap_aen = ntohl(gc->aen_cap) & NCSI_CAP_AEN_MASK;
- c->cap_vlan = ntohl(gc->vlan_mode) & NCSI_CAP_VLAN_MASK;
+ c->cap_generic = get_unaligned_be32(&gc->cap) & NCSI_CAP_GENERIC_MASK;
+ c->cap_bc = get_unaligned_be32(&gc->bc_cap) & NCSI_CAP_BC_MASK;
+ c->cap_mc = get_unaligned_be32(&gc->mc_cap) & NCSI_CAP_MC_MASK;
+ c->cap_aen = get_unaligned_be32(&gc->aen_cap) & NCSI_CAP_AEN_MASK;
+ c->cap_vlan = gc->vlan_mode & NCSI_CAP_VLAN_MASK;
/* End of probe for this channel */
}
@@ -551,7 +551,7 @@
checksum = ncsi_calculate_checksum((unsigned char *)hdr,
sizeof(*hdr) + len);
pchecksum = (__be32 *)((void *)(hdr + 1) + len);
- put_unaligned_be32(htonl(checksum), pchecksum);
+ put_unaligned_be32(checksum, pchecksum);
if (wait) {
net_set_timeout_handler(1000UL, ncsi_timeout_handler);
@@ -619,9 +619,12 @@
/* Link or configuration lost - just redo the discovery process */
ncsi_priv->state = NCSI_PROBE_PACKAGE_SP;
- for (i = 0; i < ncsi_priv->n_packages; i++)
+ for (i = 0; i < ncsi_priv->n_packages; i++) {
free(ncsi_priv->packages[i].channels);
+ ncsi_priv->packages[i].channels = NULL;
+ }
free(ncsi_priv->packages);
+ ncsi_priv->packages = NULL;
ncsi_priv->n_packages = 0;
ncsi_priv->current_package = NCSI_PACKAGE_MAX;
diff --git a/drivers/net/phy/phy.c b/drivers/net/phy/phy.c
index 63b3e46..270176c 100644
--- a/drivers/net/phy/phy.c
+++ b/drivers/net/phy/phy.c
@@ -18,6 +18,8 @@
#include <phy.h>
#include <errno.h>
#include <asm/global_data.h>
+#include <asm-generic/gpio.h>
+#include <dm/device_compat.h>
#include <dm/of_extra.h>
#include <linux/bitops.h>
#include <linux/delay.h>
@@ -566,7 +568,8 @@
return NULL;
}
- if (addr >= 0 && addr < PHY_MAX_ADDR && phy_id != PHY_FIXED_ID)
+ if (addr >= 0 && addr < PHY_MAX_ADDR && phy_id != PHY_FIXED_ID &&
+ phy_id != PHY_NCSI_ID)
bus->phymap[addr] = dev;
return dev;
@@ -642,12 +645,12 @@
{
/* If we have one, return the existing device, with new interface */
while (phy_mask) {
- int addr = ffs(phy_mask) - 1;
+ unsigned int addr = ffs(phy_mask) - 1;
if (bus->phymap[addr])
return bus->phymap[addr];
- phy_mask &= ~(1 << addr);
+ phy_mask &= ~(1U << addr);
}
return NULL;
}
@@ -768,6 +771,59 @@
return phy_reset(phydev);
}
+#if CONFIG_IS_ENABLED(DM_GPIO) && CONFIG_IS_ENABLED(OF_REAL) && \
+ !IS_ENABLED(CONFIG_DM_ETH_PHY)
+int phy_gpio_reset(struct udevice *dev)
+{
+ struct ofnode_phandle_args phandle_args;
+ struct gpio_desc gpio;
+ u32 assert, deassert;
+ ofnode node;
+ int ret;
+
+ ret = dev_read_phandle_with_args(dev, "phy-handle", NULL, 0, 0,
+ &phandle_args);
+ /* No PHY handle is OK */
+ if (ret)
+ return 0;
+
+ node = phandle_args.node;
+ if (!ofnode_valid(node))
+ return -EINVAL;
+
+ ret = gpio_request_by_name_nodev(node, "reset-gpios", 0, &gpio,
+ GPIOD_IS_OUT | GPIOD_ACTIVE_LOW);
+ /* No PHY reset GPIO is OK */
+ if (ret)
+ return 0;
+
+ assert = ofnode_read_u32_default(node, "reset-assert-us", 20000);
+ deassert = ofnode_read_u32_default(node, "reset-deassert-us", 1000);
+ ret = dm_gpio_set_value(&gpio, 1);
+ if (ret) {
+ dev_err(dev, "Failed assert gpio, err: %d\n", ret);
+ return ret;
+ }
+
+ udelay(assert);
+
+ ret = dm_gpio_set_value(&gpio, 0);
+ if (ret) {
+ dev_err(dev, "Failed deassert gpio, err: %d\n", ret);
+ return ret;
+ }
+
+ udelay(deassert);
+
+ return 0;
+}
+#else
+int phy_gpio_reset(struct udevice *dev)
+{
+ return 0;
+}
+#endif
+
struct phy_device *phy_find_by_mask(struct mii_dev *bus, uint phy_mask)
{
/* Reset the bus */
diff --git a/drivers/pci/Kconfig b/drivers/pci/Kconfig
index 463ec47..8d02ab8 100644
--- a/drivers/pci/Kconfig
+++ b/drivers/pci/Kconfig
@@ -413,4 +413,15 @@
Say Y here if you want to enable PLDA XpressRich PCIe controller
support on StarFive JH7110 SoC.
+config PCIE_DW_IMX
+ bool "i.MX DW PCIe controller support"
+ depends on ARCH_IMX8M
+ select PCIE_DW_COMMON
+ select DM_REGULATOR
+ select REGMAP
+ select SYSCON
+ help
+ Say Y here if you want to enable DW PCIe controller support on
+ iMX SoCs.
+
endif
diff --git a/drivers/pci/Makefile b/drivers/pci/Makefile
index 72ef8b4..2927c51 100644
--- a/drivers/pci/Makefile
+++ b/drivers/pci/Makefile
@@ -53,3 +53,4 @@
obj-$(CONFIG_PCIE_XILINX_NWL) += pcie-xilinx-nwl.o
obj-$(CONFIG_PCIE_PLDA_COMMON) += pcie_plda_common.o
obj-$(CONFIG_PCIE_STARFIVE_JH7110) += pcie_starfive_jh7110.o
+obj-$(CONFIG_PCIE_DW_IMX) += pcie_dw_imx.o
diff --git a/drivers/pci/pcie_dw_imx.c b/drivers/pci/pcie_dw_imx.c
new file mode 100644
index 0000000..a2ee228
--- /dev/null
+++ b/drivers/pci/pcie_dw_imx.c
@@ -0,0 +1,338 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2024 Linaro Ltd.
+ *
+ * Author: Sumit Garg <sumit.garg@linaro.org>
+ */
+
+#include <asm/io.h>
+#include <asm-generic/gpio.h>
+#include <clk.h>
+#include <dm.h>
+#include <dm/device_compat.h>
+#include <generic-phy.h>
+#include <linux/bitops.h>
+#include <linux/delay.h>
+#include <linux/err.h>
+#include <linux/iopoll.h>
+#include <log.h>
+#include <pci.h>
+#include <power/regulator.h>
+#include <regmap.h>
+#include <reset.h>
+#include <syscon.h>
+#include <time.h>
+
+#include "pcie_dw_common.h"
+
+#define PCIE_LINK_CAPABILITY 0x7c
+#define TARGET_LINK_SPEED_MASK 0xf
+#define LINK_SPEED_GEN_1 0x1
+#define LINK_SPEED_GEN_2 0x2
+#define LINK_SPEED_GEN_3 0x3
+
+#define PCIE_MISC_CONTROL_1_OFF 0x8bc
+#define PCIE_DBI_RO_WR_EN BIT(0)
+
+#define PCIE_PORT_DEBUG0 0x728
+#define PCIE_PORT_DEBUG1 0x72c
+#define PCIE_PORT_DEBUG1_LINK_UP BIT(4)
+#define PCIE_PORT_DEBUG1_LINK_IN_TRAINING BIT(29)
+
+#define PCIE_LINK_UP_TIMEOUT_MS 100
+
+#define IOMUXC_GPR14_OFFSET 0x38
+#define IMX8M_GPR_PCIE_CLK_REQ_OVERRIDE_EN BIT(10)
+#define IMX8M_GPR_PCIE_CLK_REQ_OVERRIDE BIT(11)
+
+struct pcie_dw_imx {
+ /* Must be first member of the struct */
+ struct pcie_dw dw;
+ struct regmap *iomuxc_gpr;
+ struct clk_bulk clks;
+ struct gpio_desc reset_gpio;
+ struct reset_ctl apps_reset;
+ struct phy phy;
+ struct udevice *vpcie;
+};
+
+static void pcie_dw_configure(struct pcie_dw_imx *priv, u32 cap_speed)
+{
+ dw_pcie_dbi_write_enable(&priv->dw, true);
+
+ clrsetbits_le32(priv->dw.dbi_base + PCIE_LINK_CAPABILITY,
+ TARGET_LINK_SPEED_MASK, cap_speed);
+
+ dw_pcie_dbi_write_enable(&priv->dw, false);
+}
+
+static void imx_pcie_ltssm_enable(struct pcie_dw_imx *priv)
+{
+ reset_deassert(&priv->apps_reset);
+}
+
+static void imx_pcie_ltssm_disable(struct pcie_dw_imx *priv)
+{
+ reset_assert(&priv->apps_reset);
+}
+
+static bool is_link_up(u32 val)
+{
+ return ((val & PCIE_PORT_DEBUG1_LINK_UP) &&
+ (!(val & PCIE_PORT_DEBUG1_LINK_IN_TRAINING)));
+}
+
+static int wait_link_up(struct pcie_dw_imx *priv)
+{
+ u32 val;
+
+ return readl_poll_sleep_timeout(priv->dw.dbi_base + PCIE_PORT_DEBUG1,
+ val, is_link_up(val), 10000, 100000);
+}
+
+static int pcie_link_up(struct pcie_dw_imx *priv, u32 cap_speed)
+{
+ int ret;
+
+ /* DW pre link configurations */
+ pcie_dw_configure(priv, cap_speed);
+
+ /* Initiate link training */
+ imx_pcie_ltssm_enable(priv);
+
+ /* Check that link was established */
+ ret = wait_link_up(priv);
+ if (ret)
+ imx_pcie_ltssm_disable(priv);
+
+ return ret;
+}
+
+static int imx_pcie_assert_core_reset(struct pcie_dw_imx *priv)
+{
+ if (dm_gpio_is_valid(&priv->reset_gpio)) {
+ dm_gpio_set_value(&priv->reset_gpio, 1);
+ mdelay(20);
+ }
+
+ return reset_assert(&priv->apps_reset);
+}
+
+static int imx_pcie_clk_enable(struct pcie_dw_imx *priv)
+{
+ int ret;
+
+ ret = clk_enable_bulk(&priv->clks);
+ if (ret)
+ return ret;
+
+ /*
+ * Set the over ride low and enabled make sure that
+ * REF_CLK is turned on.
+ */
+ regmap_update_bits(priv->iomuxc_gpr, IOMUXC_GPR14_OFFSET,
+ IMX8M_GPR_PCIE_CLK_REQ_OVERRIDE, 0);
+ regmap_update_bits(priv->iomuxc_gpr, IOMUXC_GPR14_OFFSET,
+ IMX8M_GPR_PCIE_CLK_REQ_OVERRIDE_EN,
+ IMX8M_GPR_PCIE_CLK_REQ_OVERRIDE_EN);
+
+ /* allow the clocks to stabilize */
+ udelay(500);
+
+ return 0;
+}
+
+static void imx_pcie_deassert_core_reset(struct pcie_dw_imx *priv)
+{
+ if (!dm_gpio_is_valid(&priv->reset_gpio))
+ return;
+
+ mdelay(100);
+ dm_gpio_set_value(&priv->reset_gpio, 0);
+ /* Wait for 100ms after PERST# deassertion (PCIe r5.0, 6.6.1) */
+ mdelay(100);
+}
+
+static int pcie_dw_imx_probe(struct udevice *dev)
+{
+ struct pcie_dw_imx *priv = dev_get_priv(dev);
+ struct udevice *ctlr = pci_get_controller(dev);
+ struct pci_controller *hose = dev_get_uclass_priv(ctlr);
+ int ret;
+
+ if (priv->vpcie) {
+ ret = regulator_set_enable(priv->vpcie, true);
+ if (ret) {
+ dev_err(dev, "failed to enable vpcie regulator\n");
+ return ret;
+ }
+ }
+
+ ret = imx_pcie_assert_core_reset(priv);
+ if (ret) {
+ dev_err(dev, "failed to assert core reset\n");
+ return ret;
+ }
+
+ ret = imx_pcie_clk_enable(priv);
+ if (ret) {
+ dev_err(dev, "failed to enable clocks\n");
+ goto err_clk;
+ }
+
+ ret = generic_phy_init(&priv->phy);
+ if (ret) {
+ dev_err(dev, "failed to initialize PHY\n");
+ goto err_phy_init;
+ }
+
+ ret = generic_phy_power_on(&priv->phy);
+ if (ret) {
+ dev_err(dev, "failed to power on PHY\n");
+ goto err_phy_power;
+ }
+
+ imx_pcie_deassert_core_reset(priv);
+
+ priv->dw.first_busno = dev_seq(dev);
+ priv->dw.dev = dev;
+ pcie_dw_setup_host(&priv->dw);
+
+ if (pcie_link_up(priv, LINK_SPEED_GEN_1)) {
+ printf("PCIE-%d: Link down\n", dev_seq(dev));
+ ret = -ENODEV;
+ goto err_link;
+ }
+
+ printf("PCIE-%d: Link up (Gen%d-x%d, Bus%d)\n", dev_seq(dev),
+ pcie_dw_get_link_speed(&priv->dw),
+ pcie_dw_get_link_width(&priv->dw),
+ hose->first_busno);
+
+ pcie_dw_prog_outbound_atu_unroll(&priv->dw, PCIE_ATU_REGION_INDEX0,
+ PCIE_ATU_TYPE_MEM,
+ priv->dw.mem.phys_start,
+ priv->dw.mem.bus_start, priv->dw.mem.size);
+
+ return 0;
+
+err_link:
+ generic_shutdown_phy(&priv->phy);
+err_phy_power:
+ generic_phy_exit(&priv->phy);
+err_phy_init:
+ clk_disable_bulk(&priv->clks);
+err_clk:
+ imx_pcie_deassert_core_reset(priv);
+
+ return ret;
+}
+
+static int pcie_dw_imx_remove(struct udevice *dev)
+{
+ struct pcie_dw_imx *priv = dev_get_priv(dev);
+
+ generic_shutdown_phy(&priv->phy);
+ dm_gpio_free(dev, &priv->reset_gpio);
+ reset_free(&priv->apps_reset);
+ clk_release_bulk(&priv->clks);
+
+ return 0;
+}
+
+static int pcie_dw_imx_of_to_plat(struct udevice *dev)
+{
+ struct pcie_dw_imx *priv = dev_get_priv(dev);
+ ofnode gpr;
+ int ret;
+
+ /* Get the controller base address */
+ priv->dw.dbi_base = (void *)dev_read_addr_name(dev, "dbi");
+ if ((fdt_addr_t)priv->dw.dbi_base == FDT_ADDR_T_NONE) {
+ dev_err(dev, "failed to get dbi_base address\n");
+ return -EINVAL;
+ }
+
+ /* Get the config space base address and size */
+ priv->dw.cfg_base = (void *)dev_read_addr_size_name(dev, "config",
+ &priv->dw.cfg_size);
+ if ((fdt_addr_t)priv->dw.cfg_base == FDT_ADDR_T_NONE) {
+ dev_err(dev, "failed to get cfg_base address\n");
+ return -EINVAL;
+ }
+
+ ret = clk_get_bulk(dev, &priv->clks);
+ if (ret) {
+ dev_err(dev, "failed to get PCIe clks\n");
+ return ret;
+ }
+
+ ret = reset_get_by_name(dev, "apps", &priv->apps_reset);
+ if (ret) {
+ dev_err(dev,
+ "Failed to get PCIe apps reset control\n");
+ goto err_reset;
+ }
+
+ ret = gpio_request_by_name(dev, "reset-gpio", 0, &priv->reset_gpio,
+ GPIOD_IS_OUT | GPIOD_IS_OUT_ACTIVE);
+ if (ret) {
+ dev_err(dev, "unable to get reset-gpio\n");
+ goto err_gpio;
+ }
+
+ ret = generic_phy_get_by_name(dev, "pcie-phy", &priv->phy);
+ if (ret) {
+ dev_err(dev, "failed to get pcie phy\n");
+ goto err_phy;
+ }
+
+ gpr = ofnode_by_compatible(ofnode_null(), "fsl,imx8mp-iomuxc-gpr");
+ if (ofnode_equal(gpr, ofnode_null())) {
+ dev_err(dev, "unable to find GPR node\n");
+ ret = -ENODEV;
+ goto err_phy;
+ }
+
+ priv->iomuxc_gpr = syscon_node_to_regmap(gpr);
+ if (IS_ERR(priv->iomuxc_gpr)) {
+ dev_err(dev, "unable to find iomuxc registers\n");
+ ret = PTR_ERR(priv->iomuxc_gpr);
+ goto err_phy;
+ }
+
+ /* vpcie-supply regulator is optional */
+ device_get_supply_regulator(dev, "vpcie-supply", &priv->vpcie);
+
+ return 0;
+
+err_phy:
+ dm_gpio_free(dev, &priv->reset_gpio);
+err_gpio:
+ reset_free(&priv->apps_reset);
+err_reset:
+ clk_release_bulk(&priv->clks);
+
+ return ret;
+}
+
+static const struct dm_pci_ops pcie_dw_imx_ops = {
+ .read_config = pcie_dw_read_config,
+ .write_config = pcie_dw_write_config,
+};
+
+static const struct udevice_id pcie_dw_imx_ids[] = {
+ { .compatible = "fsl,imx8mp-pcie" },
+ { }
+};
+
+U_BOOT_DRIVER(pcie_dw_imx) = {
+ .name = "pcie_dw_imx",
+ .id = UCLASS_PCI,
+ .of_match = pcie_dw_imx_ids,
+ .ops = &pcie_dw_imx_ops,
+ .of_to_plat = pcie_dw_imx_of_to_plat,
+ .probe = pcie_dw_imx_probe,
+ .remove = pcie_dw_imx_remove,
+ .priv_auto = sizeof(struct pcie_dw_imx),
+};
diff --git a/drivers/pci/pcie_imx.c b/drivers/pci/pcie_imx.c
index 4a18b0e09..78f2c7d 100644
--- a/drivers/pci/pcie_imx.c
+++ b/drivers/pci/pcie_imx.c
@@ -7,6 +7,14 @@
* Based on upstream Linux kernel driver:
* pci-imx6.c: Sean Cross <xobs@kosagi.com>
* pcie-designware.c: Jingoo Han <jg1.han@samsung.com>
+ *
+ * This is a legacy PCIe iMX driver kept to support older iMX6 SoCs. It is
+ * rather tied to quite old port of pcie-designware driver from Linux which
+ * suffices only iMX6 specific needs. But now we have modern PCIe iMX driver
+ * (drivers/pci/pcie_dw_imx.c) utilizing all the common DWC specific bits from
+ * (drivers/pci/pcie_dw_common.*). So you are encouraged to add any further iMX
+ * SoC support there or even better if you posses older iMX6 SoCs then switch
+ * those too in order to have a single modern PCIe iMX driver.
*/
#include <common.h>
diff --git a/drivers/phy/Kconfig b/drivers/phy/Kconfig
index 60138be..8f76787 100644
--- a/drivers/phy/Kconfig
+++ b/drivers/phy/Kconfig
@@ -284,6 +284,17 @@
help
Support the USB3.0 PHY in NXP i.MX8MQ or i.MX8MP SoC
+config PHY_IMX8M_PCIE
+ bool "NXP i.MX8MM/i.MX8MP PCIe PHY Driver"
+ depends on PHY
+ depends on IMX8MM || IMX8MP
+ select REGMAP
+ select SYSCON
+ help
+ Support the PCIe PHY in NXP i.MX8MM or i.MX8MP SoC
+
+ This PHY is found on i.MX8M devices supporting PCIe.
+
config PHY_XILINX_ZYNQMP
tristate "Xilinx ZynqMP PHY driver"
depends on PHY && ARCH_ZYNQMP
diff --git a/drivers/phy/Makefile b/drivers/phy/Makefile
index 2e87231..7a2b764 100644
--- a/drivers/phy/Makefile
+++ b/drivers/phy/Makefile
@@ -38,6 +38,7 @@
obj-$(CONFIG_PHY_MTK_TPHY) += phy-mtk-tphy.o
obj-$(CONFIG_PHY_NPCM_USB) += phy-npcm-usb.o
obj-$(CONFIG_PHY_IMX8MQ_USB) += phy-imx8mq-usb.o
+obj-$(CONFIG_PHY_IMX8M_PCIE) += phy-imx8m-pcie.o
obj-$(CONFIG_PHY_XILINX_ZYNQMP) += phy-zynqmp.o
obj-y += cadence/
obj-y += ti/
diff --git a/drivers/phy/phy-imx8m-pcie.c b/drivers/phy/phy-imx8m-pcie.c
new file mode 100644
index 0000000..2418388
--- /dev/null
+++ b/drivers/phy/phy-imx8m-pcie.c
@@ -0,0 +1,283 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright 2024 Linaro Ltd.
+ *
+ * Derived from Linux counterpart driver
+ */
+
+#include <asm/io.h>
+#include <clk.h>
+#include <dm.h>
+#include <dm/device_compat.h>
+#include <generic-phy.h>
+#include <linux/bitfield.h>
+#include <linux/clk-provider.h>
+#include <linux/iopoll.h>
+#include <syscon.h>
+#include <regmap.h>
+#include <reset.h>
+
+#include <dt-bindings/phy/phy-imx8-pcie.h>
+
+#define IMX8MM_PCIE_PHY_CMN_REG061 0x184
+#define ANA_PLL_CLK_OUT_TO_EXT_IO_EN BIT(0)
+#define IMX8MM_PCIE_PHY_CMN_REG062 0x188
+#define ANA_PLL_CLK_OUT_TO_EXT_IO_SEL BIT(3)
+#define IMX8MM_PCIE_PHY_CMN_REG063 0x18C
+#define AUX_PLL_REFCLK_SEL_SYS_PLL GENMASK(7, 6)
+#define IMX8MM_PCIE_PHY_CMN_REG064 0x190
+#define ANA_AUX_RX_TX_SEL_TX BIT(7)
+#define ANA_AUX_RX_TERM_GND_EN BIT(3)
+#define ANA_AUX_TX_TERM BIT(2)
+#define IMX8MM_PCIE_PHY_CMN_REG065 0x194
+#define ANA_AUX_RX_TERM (BIT(7) | BIT(4))
+#define ANA_AUX_TX_LVL GENMASK(3, 0)
+#define IMX8MM_PCIE_PHY_CMN_REG075 0x1D4
+#define ANA_PLL_DONE 0x3
+#define PCIE_PHY_TRSV_REG5 0x414
+#define PCIE_PHY_TRSV_REG6 0x418
+
+#define IMX8MM_GPR_PCIE_REF_CLK_SEL GENMASK(25, 24)
+#define IMX8MM_GPR_PCIE_REF_CLK_PLL FIELD_PREP(IMX8MM_GPR_PCIE_REF_CLK_SEL, 0x3)
+#define IMX8MM_GPR_PCIE_REF_CLK_EXT FIELD_PREP(IMX8MM_GPR_PCIE_REF_CLK_SEL, 0x2)
+#define IMX8MM_GPR_PCIE_AUX_EN BIT(19)
+#define IMX8MM_GPR_PCIE_CMN_RST BIT(18)
+#define IMX8MM_GPR_PCIE_POWER_OFF BIT(17)
+#define IMX8MM_GPR_PCIE_SSC_EN BIT(16)
+#define IMX8MM_GPR_PCIE_AUX_EN_OVERRIDE BIT(9)
+
+#define IOMUXC_GPR14_OFFSET 0x38
+
+enum imx8_pcie_phy_type {
+ IMX8MM,
+ IMX8MP,
+};
+
+struct imx8_pcie_phy_drvdata {
+ const char *gpr;
+ enum imx8_pcie_phy_type variant;
+};
+
+struct imx8_pcie_phy {
+ ulong base;
+ struct clk hsio_clk;
+ struct regmap *iomuxc_gpr;
+ struct reset_ctl perst;
+ struct reset_ctl reset;
+ u32 refclk_pad_mode;
+ u32 tx_deemph_gen1;
+ u32 tx_deemph_gen2;
+ bool clkreq_unused;
+ const struct imx8_pcie_phy_drvdata *drvdata;
+};
+
+static int imx8_pcie_phy_power_on(struct phy *phy)
+{
+ int ret;
+ u32 val, pad_mode;
+ struct imx8_pcie_phy *imx8_phy = dev_get_priv(phy->dev);
+
+ pad_mode = imx8_phy->refclk_pad_mode;
+ switch (imx8_phy->drvdata->variant) {
+ case IMX8MM:
+ reset_assert(&imx8_phy->reset);
+
+ /* Tune PHY de-emphasis setting to pass PCIe compliance. */
+ if (imx8_phy->tx_deemph_gen1)
+ writel(imx8_phy->tx_deemph_gen1,
+ imx8_phy->base + PCIE_PHY_TRSV_REG5);
+ if (imx8_phy->tx_deemph_gen2)
+ writel(imx8_phy->tx_deemph_gen2,
+ imx8_phy->base + PCIE_PHY_TRSV_REG6);
+ break;
+ case IMX8MP: /* Do nothing. */
+ break;
+ }
+
+ if (pad_mode == IMX8_PCIE_REFCLK_PAD_INPUT ||
+ pad_mode == IMX8_PCIE_REFCLK_PAD_UNUSED) {
+ /* Configure the pad as input */
+ val = readl(imx8_phy->base + IMX8MM_PCIE_PHY_CMN_REG061);
+ writel(val & ~ANA_PLL_CLK_OUT_TO_EXT_IO_EN,
+ imx8_phy->base + IMX8MM_PCIE_PHY_CMN_REG061);
+ } else {
+ /* Configure the PHY to output the refclock via pad */
+ writel(ANA_PLL_CLK_OUT_TO_EXT_IO_EN,
+ imx8_phy->base + IMX8MM_PCIE_PHY_CMN_REG061);
+ }
+
+ if (pad_mode == IMX8_PCIE_REFCLK_PAD_OUTPUT ||
+ pad_mode == IMX8_PCIE_REFCLK_PAD_UNUSED) {
+ /* Source clock from SoC internal PLL */
+ writel(ANA_PLL_CLK_OUT_TO_EXT_IO_SEL,
+ imx8_phy->base + IMX8MM_PCIE_PHY_CMN_REG062);
+ writel(AUX_PLL_REFCLK_SEL_SYS_PLL,
+ imx8_phy->base + IMX8MM_PCIE_PHY_CMN_REG063);
+ val = ANA_AUX_RX_TX_SEL_TX | ANA_AUX_TX_TERM;
+ writel(val | ANA_AUX_RX_TERM_GND_EN,
+ imx8_phy->base + IMX8MM_PCIE_PHY_CMN_REG064);
+ writel(ANA_AUX_RX_TERM | ANA_AUX_TX_LVL,
+ imx8_phy->base + IMX8MM_PCIE_PHY_CMN_REG065);
+ }
+
+ /* Set AUX_EN_OVERRIDE 1'b0, when the CLKREQ# isn't hooked */
+ regmap_update_bits(imx8_phy->iomuxc_gpr, IOMUXC_GPR14_OFFSET,
+ IMX8MM_GPR_PCIE_AUX_EN_OVERRIDE,
+ imx8_phy->clkreq_unused ?
+ 0 : IMX8MM_GPR_PCIE_AUX_EN_OVERRIDE);
+ regmap_update_bits(imx8_phy->iomuxc_gpr, IOMUXC_GPR14_OFFSET,
+ IMX8MM_GPR_PCIE_AUX_EN,
+ IMX8MM_GPR_PCIE_AUX_EN);
+ regmap_update_bits(imx8_phy->iomuxc_gpr, IOMUXC_GPR14_OFFSET,
+ IMX8MM_GPR_PCIE_POWER_OFF, 0);
+ regmap_update_bits(imx8_phy->iomuxc_gpr, IOMUXC_GPR14_OFFSET,
+ IMX8MM_GPR_PCIE_SSC_EN, 0);
+
+ regmap_update_bits(imx8_phy->iomuxc_gpr, IOMUXC_GPR14_OFFSET,
+ IMX8MM_GPR_PCIE_REF_CLK_SEL,
+ pad_mode == IMX8_PCIE_REFCLK_PAD_INPUT ?
+ IMX8MM_GPR_PCIE_REF_CLK_EXT :
+ IMX8MM_GPR_PCIE_REF_CLK_PLL);
+ udelay(200);
+
+ /* Do the PHY common block reset */
+ regmap_update_bits(imx8_phy->iomuxc_gpr, IOMUXC_GPR14_OFFSET,
+ IMX8MM_GPR_PCIE_CMN_RST,
+ IMX8MM_GPR_PCIE_CMN_RST);
+
+ switch (imx8_phy->drvdata->variant) {
+ case IMX8MP:
+ reset_deassert(&imx8_phy->perst);
+ fallthrough;
+ case IMX8MM:
+ reset_deassert(&imx8_phy->reset);
+ udelay(500);
+ break;
+ }
+
+ /* Polling to check the phy is ready or not. */
+ ret = readl_poll_timeout(imx8_phy->base + IMX8MM_PCIE_PHY_CMN_REG075,
+ val, val == ANA_PLL_DONE, 20000);
+ return ret;
+}
+
+static int imx8_pcie_phy_init(struct phy *phy)
+{
+ struct imx8_pcie_phy *imx8_phy = dev_get_priv(phy->dev);
+
+ return clk_enable(&imx8_phy->hsio_clk);
+}
+
+static int imx8_pcie_phy_exit(struct phy *phy)
+{
+ struct imx8_pcie_phy *imx8_phy = dev_get_priv(phy->dev);
+
+ return clk_disable(&imx8_phy->hsio_clk);
+}
+
+static const struct phy_ops imx8_pcie_phy_ops = {
+ .init = imx8_pcie_phy_init,
+ .exit = imx8_pcie_phy_exit,
+ .power_on = imx8_pcie_phy_power_on,
+};
+
+static const struct imx8_pcie_phy_drvdata imx8mm_drvdata = {
+ .gpr = "fsl,imx8mm-iomuxc-gpr",
+ .variant = IMX8MM,
+};
+
+static const struct imx8_pcie_phy_drvdata imx8mp_drvdata = {
+ .gpr = "fsl,imx8mp-iomuxc-gpr",
+ .variant = IMX8MP,
+};
+
+static const struct udevice_id imx8_pcie_phy_of_match[] = {
+ {.compatible = "fsl,imx8mm-pcie-phy", .data = (ulong)&imx8mm_drvdata, },
+ {.compatible = "fsl,imx8mp-pcie-phy", .data = (ulong)&imx8mp_drvdata, },
+ { },
+};
+
+static int imx8_pcie_phy_probe(struct udevice *dev)
+{
+ struct imx8_pcie_phy *imx8_phy = dev_get_priv(dev);
+ ofnode gpr;
+ int ret = 0;
+
+ imx8_phy->drvdata = (void *)dev_get_driver_data(dev);
+ imx8_phy->base = dev_read_addr(dev);
+ if (!imx8_phy->base)
+ return -EINVAL;
+
+ /* get PHY refclk pad mode */
+ dev_read_u32(dev, "fsl,refclk-pad-mode", &imx8_phy->refclk_pad_mode);
+
+ imx8_phy->tx_deemph_gen1 = dev_read_u32_default(dev,
+ "fsl,tx-deemph-gen1",
+ 0);
+ imx8_phy->tx_deemph_gen2 = dev_read_u32_default(dev,
+ "fsl,tx-deemph-gen2",
+ 0);
+ imx8_phy->clkreq_unused = dev_read_bool(dev, "fsl,clkreq-unsupported");
+
+ /* Grab GPR config register range */
+ gpr = ofnode_by_compatible(ofnode_null(), imx8_phy->drvdata->gpr);
+ if (ofnode_equal(gpr, ofnode_null())) {
+ dev_err(dev, "unable to find GPR node\n");
+ return -ENODEV;
+ }
+
+ imx8_phy->iomuxc_gpr = syscon_node_to_regmap(gpr);
+ if (IS_ERR(imx8_phy->iomuxc_gpr)) {
+ dev_err(dev, "unable to find iomuxc registers\n");
+ return PTR_ERR(imx8_phy->iomuxc_gpr);
+ }
+
+ ret = clk_get_by_name(dev, "ref", &imx8_phy->hsio_clk);
+ if (ret) {
+ dev_err(dev, "Failed to get PCIEPHY ref clock\n");
+ return ret;
+ }
+
+ ret = reset_get_by_name(dev, "pciephy", &imx8_phy->reset);
+ if (ret) {
+ dev_err(dev, "Failed to get PCIEPHY reset control\n");
+ return ret;
+ }
+
+ if (imx8_phy->drvdata->variant == IMX8MP) {
+ ret = reset_get_by_name(dev, "perst", &imx8_phy->perst);
+ if (ret) {
+ dev_err(dev,
+ "Failed to get PCIEPHY PHY PERST control\n");
+ goto err_perst;
+ }
+ }
+
+ return 0;
+
+err_perst:
+ reset_free(&imx8_phy->reset);
+ return ret;
+}
+
+static int imx8_pcie_phy_remove(struct udevice *dev)
+{
+ struct imx8_pcie_phy *imx8_phy = dev_get_priv(dev);
+
+ if (imx8_phy->drvdata->variant == IMX8MP)
+ reset_free(&imx8_phy->perst);
+
+ reset_free(&imx8_phy->reset);
+
+ return 0;
+}
+
+U_BOOT_DRIVER(nxp_imx8_pcie_phy) = {
+ .name = "nxp_imx8_pcie_phy",
+ .id = UCLASS_PHY,
+ .of_match = imx8_pcie_phy_of_match,
+ .probe = imx8_pcie_phy_probe,
+ .remove = imx8_pcie_phy_remove,
+ .ops = &imx8_pcie_phy_ops,
+ .priv_auto = sizeof(struct imx8_pcie_phy),
+};
diff --git a/drivers/phy/qcom/Kconfig b/drivers/phy/qcom/Kconfig
index f4ca174..b9fe608 100644
--- a/drivers/phy/qcom/Kconfig
+++ b/drivers/phy/qcom/Kconfig
@@ -12,6 +12,21 @@
help
Support for the USB PHY-s on Qualcomm IPQ40xx SoC-s.
+config PHY_QCOM_QUSB2
+ tristate "Qualcomm USB QUSB2 PHY driver"
+ depends on PHY && ARCH_SNAPDRAGON
+ help
+ Enable this to support the Super-Speed USB transceiver on various
+ Qualcomm chipsets.
+
+config PHY_QCOM_USB_SNPS_FEMTO_V2
+ tristate "Qualcomm SNPS FEMTO USB HS PHY v2"
+ depends on PHY && ARCH_SNAPDRAGON
+ help
+ Enable this to support the Qualcomm Synopsys DesignWare Core 7nm
+ High-Speed PHY driver. This driver supports the Hi-Speed PHY which
+ is usually paired with Synopsys DWC3 USB IPs on MSM SOCs.
+
config PHY_QCOM_USB_HS_28NM
tristate "Qualcomm 28nm High-Speed PHY"
depends on PHY && ARCH_SNAPDRAGON
diff --git a/drivers/phy/qcom/Makefile b/drivers/phy/qcom/Makefile
index 2113f17..5f4db4a 100644
--- a/drivers/phy/qcom/Makefile
+++ b/drivers/phy/qcom/Makefile
@@ -1,4 +1,6 @@
obj-$(CONFIG_PHY_QCOM_IPQ4019_USB) += phy-qcom-ipq4019-usb.o
obj-$(CONFIG_MSM8916_USB_PHY) += msm8916-usbh-phy.o
+obj-$(CONFIG_PHY_QCOM_QUSB2) += phy-qcom-qusb2.o
+obj-$(CONFIG_PHY_QCOM_USB_SNPS_FEMTO_V2) += phy-qcom-snps-femto-v2.o
obj-$(CONFIG_PHY_QCOM_USB_HS_28NM) += phy-qcom-usb-hs-28nm.o
obj-$(CONFIG_PHY_QCOM_USB_SS) += phy-qcom-usb-ss.o
diff --git a/drivers/phy/qcom/phy-qcom-qusb2.c b/drivers/phy/qcom/phy-qcom-qusb2.c
new file mode 100644
index 0000000..c91ba18
--- /dev/null
+++ b/drivers/phy/qcom/phy-qcom-qusb2.c
@@ -0,0 +1,429 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2023 Bhupesh Sharma <bhupesh.sharma@linaro.org>
+ *
+ * Based on Linux driver
+ */
+
+#include <dm.h>
+#include <generic-phy.h>
+#include <linux/bitops.h>
+#include <asm/io.h>
+#include <reset.h>
+#include <clk.h>
+#include <linux/delay.h>
+
+#include <dt-bindings/phy/phy-qcom-qusb2.h>
+
+#define QUSB2PHY_PLL 0x0
+#define QUSB2PHY_PLL_TEST 0x04
+#define CLK_REF_SEL BIT(7)
+
+#define QUSB2PHY_PLL_TUNE 0x08
+#define QUSB2PHY_PLL_USER_CTL1 0x0c
+#define QUSB2PHY_PLL_USER_CTL2 0x10
+#define QUSB2PHY_PLL_AUTOPGM_CTL1 0x1c
+#define QUSB2PHY_PLL_PWR_CTRL 0x18
+
+/* QUSB2PHY_PLL_STATUS register bits */
+#define PLL_LOCKED BIT(5)
+
+/* QUSB2PHY_PLL_COMMON_STATUS_ONE register bits */
+#define CORE_READY_STATUS BIT(0)
+
+/* QUSB2PHY_PORT_POWERDOWN register bits */
+#define CLAMP_N_EN BIT(5)
+#define FREEZIO_N BIT(1)
+#define POWER_DOWN BIT(0)
+
+/* QUSB2PHY_PWR_CTRL1 register bits */
+#define PWR_CTRL1_VREF_SUPPLY_TRIM BIT(5)
+#define PWR_CTRL1_CLAMP_N_EN BIT(1)
+
+#define QUSB2PHY_REFCLK_ENABLE BIT(0)
+
+#define PHY_CLK_SCHEME_SEL BIT(0)
+
+/* QUSB2PHY_INTR_CTRL register bits */
+#define DMSE_INTR_HIGH_SEL BIT(4)
+#define DPSE_INTR_HIGH_SEL BIT(3)
+#define CHG_DET_INTR_EN BIT(2)
+#define DMSE_INTR_EN BIT(1)
+#define DPSE_INTR_EN BIT(0)
+
+/* QUSB2PHY_PLL_CORE_INPUT_OVERRIDE register bits */
+#define CORE_PLL_EN_FROM_RESET BIT(4)
+#define CORE_RESET BIT(5)
+#define CORE_RESET_MUX BIT(6)
+
+/* QUSB2PHY_IMP_CTRL1 register bits */
+#define IMP_RES_OFFSET_MASK GENMASK(5, 0)
+#define IMP_RES_OFFSET_SHIFT 0x0
+
+/* QUSB2PHY_PLL_BIAS_CONTROL_2 register bits */
+#define BIAS_CTRL2_RES_OFFSET_MASK GENMASK(5, 0)
+#define BIAS_CTRL2_RES_OFFSET_SHIFT 0x0
+
+/* QUSB2PHY_CHG_CONTROL_2 register bits */
+#define CHG_CTRL2_OFFSET_MASK GENMASK(5, 4)
+#define CHG_CTRL2_OFFSET_SHIFT 0x4
+
+/* QUSB2PHY_PORT_TUNE1 register bits */
+#define HSTX_TRIM_MASK GENMASK(7, 4)
+#define HSTX_TRIM_SHIFT 0x4
+#define PREEMPH_WIDTH_HALF_BIT BIT(2)
+#define PREEMPHASIS_EN_MASK GENMASK(1, 0)
+#define PREEMPHASIS_EN_SHIFT 0x0
+
+/* QUSB2PHY_PORT_TUNE2 register bits */
+#define HSDISC_TRIM_MASK GENMASK(1, 0)
+#define HSDISC_TRIM_SHIFT 0x0
+
+#define QUSB2PHY_PLL_ANALOG_CONTROLS_TWO 0x04
+#define QUSB2PHY_PLL_CLOCK_INVERTERS 0x18c
+#define QUSB2PHY_PLL_CMODE 0x2c
+#define QUSB2PHY_PLL_LOCK_DELAY 0x184
+#define QUSB2PHY_PLL_DIGITAL_TIMERS_TWO 0xb4
+#define QUSB2PHY_PLL_BIAS_CONTROL_1 0x194
+#define QUSB2PHY_PLL_BIAS_CONTROL_2 0x198
+#define QUSB2PHY_PWR_CTRL2 0x214
+#define QUSB2PHY_IMP_CTRL1 0x220
+#define QUSB2PHY_IMP_CTRL2 0x224
+#define QUSB2PHY_CHG_CTRL2 0x23c
+
+struct qusb2_phy_init_tbl {
+ unsigned int offset;
+ unsigned int val;
+ /*
+ * register part of layout ?
+ * if yes, then offset gives index in the reg-layout
+ */
+ int in_layout;
+};
+
+struct qusb2_phy_cfg {
+ const struct qusb2_phy_init_tbl *tbl;
+ /* number of entries in the table */
+ unsigned int tbl_num;
+ /* offset to PHY_CLK_SCHEME register in TCSR map */
+ unsigned int clk_scheme_offset;
+
+ /* array of registers with different offsets */
+ const unsigned int *regs;
+ unsigned int mask_core_ready;
+ unsigned int disable_ctrl;
+ unsigned int autoresume_en;
+
+ /* true if PHY has PLL_TEST register to select clk_scheme */
+ bool has_pll_test;
+
+ /* true if TUNE1 register must be updated by fused value, else TUNE2 */
+ bool update_tune1_with_efuse;
+
+ /* true if PHY has PLL_CORE_INPUT_OVERRIDE register to reset PLL */
+ bool has_pll_override;
+};
+
+/* set of registers with offsets different per-PHY */
+enum qusb2phy_reg_layout {
+ QUSB2PHY_PLL_CORE_INPUT_OVERRIDE,
+ QUSB2PHY_PLL_STATUS,
+ QUSB2PHY_PORT_TUNE1,
+ QUSB2PHY_PORT_TUNE2,
+ QUSB2PHY_PORT_TUNE3,
+ QUSB2PHY_PORT_TUNE4,
+ QUSB2PHY_PORT_TUNE5,
+ QUSB2PHY_PORT_TEST1,
+ QUSB2PHY_PORT_TEST2,
+ QUSB2PHY_PORT_POWERDOWN,
+ QUSB2PHY_INTR_CTRL,
+};
+
+#define QUSB2_PHY_INIT_CFG(o, v) \
+ { \
+ .offset = o, .val = v, \
+ }
+
+#define QUSB2_PHY_INIT_CFG_L(o, v) \
+ { \
+ .offset = o, .val = v, .in_layout = 1, \
+ }
+
+static const struct qusb2_phy_init_tbl sm6115_init_tbl[] = {
+ QUSB2_PHY_INIT_CFG_L(QUSB2PHY_PORT_TUNE1, 0xf8),
+ QUSB2_PHY_INIT_CFG_L(QUSB2PHY_PORT_TUNE2, 0x53),
+ QUSB2_PHY_INIT_CFG_L(QUSB2PHY_PORT_TUNE3, 0x81),
+ QUSB2_PHY_INIT_CFG_L(QUSB2PHY_PORT_TUNE4, 0x17),
+
+ QUSB2_PHY_INIT_CFG(QUSB2PHY_PLL_TUNE, 0x30),
+ QUSB2_PHY_INIT_CFG(QUSB2PHY_PLL_USER_CTL1, 0x79),
+ QUSB2_PHY_INIT_CFG(QUSB2PHY_PLL_USER_CTL2, 0x21),
+
+ QUSB2_PHY_INIT_CFG_L(QUSB2PHY_PORT_TEST2, 0x14),
+
+ QUSB2_PHY_INIT_CFG(QUSB2PHY_PLL_AUTOPGM_CTL1, 0x9f),
+ QUSB2_PHY_INIT_CFG(QUSB2PHY_PLL_PWR_CTRL, 0x00),
+};
+
+static const unsigned int sm6115_regs_layout[] = {
+ [QUSB2PHY_PLL_STATUS] = 0x38, [QUSB2PHY_PORT_TUNE1] = 0x80,
+ [QUSB2PHY_PORT_TUNE2] = 0x84, [QUSB2PHY_PORT_TUNE3] = 0x88,
+ [QUSB2PHY_PORT_TUNE4] = 0x8c, [QUSB2PHY_PORT_TUNE5] = 0x90,
+ [QUSB2PHY_PORT_TEST1] = 0xb8, [QUSB2PHY_PORT_TEST2] = 0x9c,
+ [QUSB2PHY_PORT_POWERDOWN] = 0xb4, [QUSB2PHY_INTR_CTRL] = 0xbc,
+};
+
+static const struct qusb2_phy_init_tbl qusb2_v2_init_tbl[] = {
+ QUSB2_PHY_INIT_CFG(QUSB2PHY_PLL_ANALOG_CONTROLS_TWO, 0x03),
+ QUSB2_PHY_INIT_CFG(QUSB2PHY_PLL_CLOCK_INVERTERS, 0x7c),
+ QUSB2_PHY_INIT_CFG(QUSB2PHY_PLL_CMODE, 0x80),
+ QUSB2_PHY_INIT_CFG(QUSB2PHY_PLL_LOCK_DELAY, 0x0a),
+ QUSB2_PHY_INIT_CFG(QUSB2PHY_PLL_DIGITAL_TIMERS_TWO, 0x19),
+ QUSB2_PHY_INIT_CFG(QUSB2PHY_PLL_BIAS_CONTROL_1, 0x40),
+ QUSB2_PHY_INIT_CFG(QUSB2PHY_PLL_BIAS_CONTROL_2, 0x20),
+ QUSB2_PHY_INIT_CFG(QUSB2PHY_PWR_CTRL2, 0x21),
+ QUSB2_PHY_INIT_CFG(QUSB2PHY_IMP_CTRL1, 0x0),
+ QUSB2_PHY_INIT_CFG(QUSB2PHY_IMP_CTRL2, 0x58),
+
+ QUSB2_PHY_INIT_CFG_L(QUSB2PHY_PORT_TUNE1, 0x30),
+ QUSB2_PHY_INIT_CFG_L(QUSB2PHY_PORT_TUNE2, 0x29),
+ QUSB2_PHY_INIT_CFG_L(QUSB2PHY_PORT_TUNE3, 0xca),
+ QUSB2_PHY_INIT_CFG_L(QUSB2PHY_PORT_TUNE4, 0x04),
+ QUSB2_PHY_INIT_CFG_L(QUSB2PHY_PORT_TUNE5, 0x03),
+
+ QUSB2_PHY_INIT_CFG(QUSB2PHY_CHG_CTRL2, 0x0),
+};
+
+static const unsigned int qusb2_v2_regs_layout[] = {
+ [QUSB2PHY_PLL_CORE_INPUT_OVERRIDE] = 0xa8,
+ [QUSB2PHY_PLL_STATUS] = 0x1a0,
+ [QUSB2PHY_PORT_TUNE1] = 0x240,
+ [QUSB2PHY_PORT_TUNE2] = 0x244,
+ [QUSB2PHY_PORT_TUNE3] = 0x248,
+ [QUSB2PHY_PORT_TUNE4] = 0x24c,
+ [QUSB2PHY_PORT_TUNE5] = 0x250,
+ [QUSB2PHY_PORT_TEST1] = 0x254,
+ [QUSB2PHY_PORT_TEST2] = 0x258,
+ [QUSB2PHY_PORT_POWERDOWN] = 0x210,
+ [QUSB2PHY_INTR_CTRL] = 0x230,
+};
+
+static const struct qusb2_phy_cfg sm6115_phy_cfg = {
+ .tbl = sm6115_init_tbl,
+ .tbl_num = ARRAY_SIZE(sm6115_init_tbl),
+ .regs = sm6115_regs_layout,
+
+ .has_pll_test = true,
+ .disable_ctrl = (CLAMP_N_EN | FREEZIO_N | POWER_DOWN),
+ .mask_core_ready = PLL_LOCKED,
+ .autoresume_en = BIT(3),
+};
+
+static const struct qusb2_phy_cfg qusb2_v2_phy_cfg = {
+ .tbl = qusb2_v2_init_tbl,
+ .tbl_num = ARRAY_SIZE(qusb2_v2_init_tbl),
+ .regs = qusb2_v2_regs_layout,
+
+ .disable_ctrl = (PWR_CTRL1_VREF_SUPPLY_TRIM | PWR_CTRL1_CLAMP_N_EN |
+ POWER_DOWN),
+ .mask_core_ready = CORE_READY_STATUS,
+ .has_pll_override = true,
+ .autoresume_en = BIT(0),
+ .update_tune1_with_efuse = true,
+};
+
+/**
+ * struct qusb2_phy - structure holding qusb2 phy attributes
+ *
+ * @phy: generic phy
+ * @base: iomapped memory space for qubs2 phy
+ *
+ * @cfg_ahb_clk: AHB2PHY interface clock
+ * @phy_rst: phy reset control
+ *
+ * @cfg: phy config data
+ * @has_se_clk_scheme: indicate if PHY has single-ended ref clock scheme
+ */
+struct qusb2_phy {
+ struct phy *phy;
+ void __iomem *base;
+
+ struct clk cfg_ahb_clk;
+ struct reset_ctl phy_rst;
+
+ const struct qusb2_phy_cfg *cfg;
+ bool has_se_clk_scheme;
+};
+
+static inline void qusb2_phy_configure(void __iomem *base,
+ const unsigned int *regs,
+ const struct qusb2_phy_init_tbl tbl[],
+ int num)
+{
+ int i;
+
+ for (i = 0; i < num; i++) {
+ if (tbl[i].in_layout)
+ writel(tbl[i].val, base + regs[tbl[i].offset]);
+ else
+ writel(tbl[i].val, base + tbl[i].offset);
+ }
+}
+
+static int qusb2phy_do_reset(struct qusb2_phy *qphy)
+{
+ int ret;
+
+ ret = reset_assert(&qphy->phy_rst);
+ if (ret)
+ return ret;
+
+ udelay(500);
+
+ ret = reset_deassert(&qphy->phy_rst);
+ if (ret)
+ return ret;
+
+ return 0;
+}
+
+static int qusb2phy_power_on(struct phy *phy)
+{
+ struct qusb2_phy *qphy = dev_get_priv(phy->dev);
+ const struct qusb2_phy_cfg *cfg = qphy->cfg;
+ int ret;
+ u32 val;
+
+ ret = qusb2phy_do_reset(qphy);
+ if (ret)
+ return ret;
+
+ /* Disable the PHY */
+ setbits_le32(qphy->base + cfg->regs[QUSB2PHY_PORT_POWERDOWN],
+ qphy->cfg->disable_ctrl);
+
+ if (cfg->has_pll_test) {
+ /* save reset value to override reference clock scheme later */
+ val = readl(qphy->base + QUSB2PHY_PLL_TEST);
+ }
+
+ qusb2_phy_configure(qphy->base, cfg->regs, cfg->tbl, cfg->tbl_num);
+
+ /* Enable the PHY */
+ clrbits_le32(qphy->base + cfg->regs[QUSB2PHY_PORT_POWERDOWN],
+ POWER_DOWN);
+
+ /* Required to get phy pll lock successfully */
+ udelay(150);
+
+ if (cfg->has_pll_test) {
+ val |= CLK_REF_SEL;
+
+ writel(val, qphy->base + QUSB2PHY_PLL_TEST);
+
+ /* ensure above write is through */
+ readl(qphy->base + QUSB2PHY_PLL_TEST);
+ }
+
+ /* Required to get phy pll lock successfully */
+ udelay(100);
+
+ val = readb(qphy->base + cfg->regs[QUSB2PHY_PLL_STATUS]);
+ if (!(val & cfg->mask_core_ready)) {
+ pr_err("QUSB2PHY pll lock failed: status reg = %x\n", val);
+ ret = -EBUSY;
+ return ret;
+ }
+
+ return 0;
+}
+
+static int qusb2phy_power_off(struct phy *phy)
+{
+ struct qusb2_phy *qphy = dev_get_priv(phy->dev);
+
+ /* Disable the PHY */
+ setbits_le32(qphy->base + qphy->cfg->regs[QUSB2PHY_PORT_POWERDOWN],
+ qphy->cfg->disable_ctrl);
+
+ reset_assert(&qphy->phy_rst);
+
+ clk_disable(&qphy->cfg_ahb_clk);
+
+ return 0;
+}
+
+static int qusb2phy_clk_init(struct udevice *dev, struct qusb2_phy *qphy)
+{
+ int ret;
+
+ /* We ignore the ref clock as we currently lack a driver for rpmcc/rpmhcc where
+ * it usually comes from - we assume it's always on.
+ */
+ ret = clk_get_by_name(dev, "cfg_ahb", &qphy->cfg_ahb_clk);
+ if (ret == -ENOSYS || ret == -ENOENT)
+ return 0;
+ if (ret)
+ return ret;
+
+ ret = clk_enable(&qphy->cfg_ahb_clk);
+ if (ret)
+ return ret;
+
+ return 0;
+}
+
+static int qusb2phy_probe(struct udevice *dev)
+{
+ struct qusb2_phy *qphy = dev_get_priv(dev);
+ int ret;
+
+ qphy->base = (void __iomem *)dev_read_addr(dev);
+ if (IS_ERR(qphy->base))
+ return PTR_ERR(qphy->base);
+
+ ret = qusb2phy_clk_init(dev, qphy);
+ if (ret) {
+ printf("%s: Couldn't get clocks: %d\n", __func__, ret);
+ return ret;
+ }
+
+ ret = reset_get_by_index(dev, 0, &qphy->phy_rst);
+ if (ret) {
+ printf("%s: Couldn't get resets: %d\n", __func__, ret);
+ return ret;
+ }
+
+ qphy->cfg = (const struct qusb2_phy_cfg *)dev_get_driver_data(dev);
+ if (!qphy->cfg) {
+ printf("%s: Couldn't get driver data\n", __func__);
+ return -EINVAL;
+ }
+
+ debug("%s success qusb phy cfg %p\n", __func__, qphy->cfg);
+ return 0;
+}
+
+static struct phy_ops qusb2phy_ops = {
+ .power_on = qusb2phy_power_on,
+ .power_off = qusb2phy_power_off,
+};
+
+static const struct udevice_id qusb2phy_ids[] = {
+ { .compatible = "qcom,qusb2-phy" },
+ { .compatible = "qcom,qcm2290-qusb2-phy",
+ .data = (ulong)&sm6115_phy_cfg },
+ { .compatible = "qcom,sm6115-qusb2-phy",
+ .data = (ulong)&sm6115_phy_cfg },
+ { .compatible = "qcom,qusb2-v2-phy", .data = (ulong)&qusb2_v2_phy_cfg },
+ {}
+};
+
+U_BOOT_DRIVER(qcom_qusb2_phy) = {
+ .name = "qcom-qusb2-phy",
+ .id = UCLASS_PHY,
+ .of_match = qusb2phy_ids,
+ .ops = &qusb2phy_ops,
+ .probe = qusb2phy_probe,
+ .priv_auto = sizeof(struct qusb2_phy),
+};
diff --git a/drivers/phy/qcom/phy-qcom-snps-femto-v2.c b/drivers/phy/qcom/phy-qcom-snps-femto-v2.c
new file mode 100644
index 0000000..a1675b6
--- /dev/null
+++ b/drivers/phy/qcom/phy-qcom-snps-femto-v2.c
@@ -0,0 +1,216 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (c) 2020, The Linux Foundation. All rights reserved.
+ * Copyright (C) 2023 Bhupesh Sharma <bhupesh.sharma@linaro.org>
+ *
+ * Based on Linux driver
+ */
+
+#include <clk.h>
+#include <clk-uclass.h>
+#include <dm.h>
+#include <dm/device_compat.h>
+#include <dm/devres.h>
+#include <generic-phy.h>
+#include <malloc.h>
+#include <reset.h>
+
+#include <asm/io.h>
+#include <linux/bitops.h>
+#include <linux/clk-provider.h>
+#include <linux/delay.h>
+#include <linux/iopoll.h>
+
+#define USB2_PHY_USB_PHY_UTMI_CTRL0 (0x3c)
+#define SLEEPM BIT(0)
+#define OPMODE_MASK GENMASK(4, 3)
+#define OPMODE_NORMAL (0x00)
+#define OPMODE_NONDRIVING BIT(3)
+#define TERMSEL BIT(5)
+
+#define USB2_PHY_USB_PHY_UTMI_CTRL5 (0x50)
+#define POR BIT(1)
+
+#define USB2_PHY_USB_PHY_HS_PHY_CTRL_COMMON0 (0x54)
+#define SIDDQ BIT(2)
+#define RETENABLEN BIT(3)
+#define FSEL_MASK GENMASK(6, 4)
+#define FSEL_DEFAULT (0x3 << 4)
+
+#define USB2_PHY_USB_PHY_HS_PHY_CTRL_COMMON1 (0x58)
+#define VBUSVLDEXTSEL0 BIT(4)
+#define PLLBTUNE BIT(5)
+
+#define USB2_PHY_USB_PHY_HS_PHY_CTRL_COMMON2 (0x5c)
+#define VREGBYPASS BIT(0)
+
+#define USB2_PHY_USB_PHY_HS_PHY_CTRL1 (0x60)
+#define VBUSVLDEXT0 BIT(0)
+
+#define USB2_PHY_USB_PHY_HS_PHY_CTRL2 (0x64)
+#define USB2_AUTO_RESUME BIT(0)
+#define USB2_SUSPEND_N BIT(2)
+#define USB2_SUSPEND_N_SEL BIT(3)
+
+#define USB2_PHY_USB_PHY_CFG0 (0x94)
+#define UTMI_PHY_DATAPATH_CTRL_OVERRIDE_EN BIT(0)
+#define UTMI_PHY_CMN_CTRL_OVERRIDE_EN BIT(1)
+
+#define USB2_PHY_USB_PHY_REFCLK_CTRL (0xa0)
+#define REFCLK_SEL_MASK GENMASK(1, 0)
+#define REFCLK_SEL_DEFAULT (0x2 << 0)
+
+struct qcom_snps_hsphy {
+ void __iomem *base;
+ struct clk_bulk clks;
+ struct reset_ctl_bulk resets;
+};
+
+/*
+ * We should just be able to use clrsetbits_le32() here, but this results
+ * in crashes on some boards. This is suspected to be because of some bus
+ * arbitration quirks with the PHY (i.e. it takes several bus clock cycles
+ * for the write to actually go through). The readl_relaxed() at the end will
+ * block until the write is completed (and all registers updated), and thus
+ * ensure that we don't access the PHY registers when they're in an
+ * undetermined state.
+ */
+static inline void qcom_snps_hsphy_write_mask(void __iomem *base, u32 offset,
+ u32 mask, u32 val)
+{
+ u32 reg;
+
+ reg = readl_relaxed(base + offset);
+
+ reg &= ~mask;
+ reg |= val & mask;
+ writel_relaxed(reg, base + offset);
+
+ /* Ensure above write is completed */
+ readl_relaxed(base + offset);
+}
+
+static int qcom_snps_hsphy_usb_init(struct phy *phy)
+{
+ struct qcom_snps_hsphy *priv = dev_get_priv(phy->dev);
+
+ qcom_snps_hsphy_write_mask(priv->base, USB2_PHY_USB_PHY_CFG0,
+ UTMI_PHY_CMN_CTRL_OVERRIDE_EN,
+ UTMI_PHY_CMN_CTRL_OVERRIDE_EN);
+ qcom_snps_hsphy_write_mask(priv->base, USB2_PHY_USB_PHY_UTMI_CTRL5, POR,
+ POR);
+ qcom_snps_hsphy_write_mask(priv->base,
+ USB2_PHY_USB_PHY_HS_PHY_CTRL_COMMON0, FSEL_MASK, 0);
+ qcom_snps_hsphy_write_mask(priv->base,
+ USB2_PHY_USB_PHY_HS_PHY_CTRL_COMMON1,
+ PLLBTUNE, PLLBTUNE);
+ qcom_snps_hsphy_write_mask(priv->base, USB2_PHY_USB_PHY_REFCLK_CTRL,
+ REFCLK_SEL_DEFAULT, REFCLK_SEL_MASK);
+ qcom_snps_hsphy_write_mask(priv->base,
+ USB2_PHY_USB_PHY_HS_PHY_CTRL_COMMON1,
+ VBUSVLDEXTSEL0, VBUSVLDEXTSEL0);
+ qcom_snps_hsphy_write_mask(priv->base, USB2_PHY_USB_PHY_HS_PHY_CTRL1,
+ VBUSVLDEXT0, VBUSVLDEXT0);
+
+ qcom_snps_hsphy_write_mask(priv->base,
+ USB2_PHY_USB_PHY_HS_PHY_CTRL_COMMON2,
+ VREGBYPASS, VREGBYPASS);
+
+ qcom_snps_hsphy_write_mask(priv->base, USB2_PHY_USB_PHY_HS_PHY_CTRL2,
+ USB2_SUSPEND_N_SEL | USB2_SUSPEND_N,
+ USB2_SUSPEND_N_SEL | USB2_SUSPEND_N);
+
+ qcom_snps_hsphy_write_mask(priv->base, USB2_PHY_USB_PHY_UTMI_CTRL0,
+ SLEEPM, SLEEPM);
+
+ qcom_snps_hsphy_write_mask(
+ priv->base, USB2_PHY_USB_PHY_HS_PHY_CTRL_COMMON0, SIDDQ, 0);
+
+ qcom_snps_hsphy_write_mask(priv->base, USB2_PHY_USB_PHY_UTMI_CTRL5, POR,
+ 0);
+
+ qcom_snps_hsphy_write_mask(priv->base, USB2_PHY_USB_PHY_HS_PHY_CTRL2,
+ USB2_SUSPEND_N_SEL, 0);
+
+ qcom_snps_hsphy_write_mask(priv->base, USB2_PHY_USB_PHY_CFG0,
+ UTMI_PHY_CMN_CTRL_OVERRIDE_EN, 0);
+
+ return 0;
+}
+
+static int qcom_snps_hsphy_power_on(struct phy *phy)
+{
+ struct qcom_snps_hsphy *priv = dev_get_priv(phy->dev);
+ int ret;
+
+ clk_enable_bulk(&priv->clks);
+
+ ret = reset_deassert_bulk(&priv->resets);
+ if (ret)
+ return ret;
+
+ ret = qcom_snps_hsphy_usb_init(phy);
+ if (ret)
+ return ret;
+
+ return 0;
+}
+
+static int qcom_snps_hsphy_power_off(struct phy *phy)
+{
+ struct qcom_snps_hsphy *priv = dev_get_priv(phy->dev);
+
+ reset_assert_bulk(&priv->resets);
+ clk_disable_bulk(&priv->clks);
+
+ return 0;
+}
+
+static int qcom_snps_hsphy_phy_probe(struct udevice *dev)
+{
+ struct qcom_snps_hsphy *priv = dev_get_priv(dev);
+ int ret;
+
+ priv->base = dev_read_addr_ptr(dev);
+ if (IS_ERR(priv->base))
+ return PTR_ERR(priv->base);
+
+ ret = clk_get_bulk(dev, &priv->clks);
+ if (ret < 0 && ret != -ENOENT) {
+ printf("%s: Failed to get clocks %d\n", __func__, ret);
+ return ret;
+ }
+
+ ret = reset_get_bulk(dev, &priv->resets);
+ if (ret < 0) {
+ printf("failed to get resets, ret = %d\n", ret);
+ return ret;
+ }
+
+ clk_enable_bulk(&priv->clks);
+ reset_deassert_bulk(&priv->resets);
+
+ return 0;
+}
+
+static struct phy_ops qcom_snps_hsphy_phy_ops = {
+ .power_on = qcom_snps_hsphy_power_on,
+ .power_off = qcom_snps_hsphy_power_off,
+};
+
+static const struct udevice_id qcom_snps_hsphy_phy_ids[] = {
+ { .compatible = "qcom,sm8150-usb-hs-phy" },
+ { .compatible = "qcom,usb-snps-hs-5nm-phy" },
+ { .compatible = "qcom,usb-snps-hs-7nm-phy" },
+ { .compatible = "qcom,usb-snps-femto-v2-phy" },
+ {}
+};
+
+U_BOOT_DRIVER(qcom_usb_qcom_snps_hsphy) = {
+ .name = "qcom-snps-hsphy",
+ .id = UCLASS_PHY,
+ .of_match = qcom_snps_hsphy_phy_ids,
+ .ops = &qcom_snps_hsphy_phy_ops,
+ .probe = qcom_snps_hsphy_phy_probe,
+ .priv_auto = sizeof(struct qcom_snps_hsphy),
+};
diff --git a/drivers/phy/rockchip/phy-rockchip-inno-usb2.c b/drivers/phy/rockchip/phy-rockchip-inno-usb2.c
index 70e61ec..d392aed 100644
--- a/drivers/phy/rockchip/phy-rockchip-inno-usb2.c
+++ b/drivers/phy/rockchip/phy-rockchip-inno-usb2.c
@@ -6,23 +6,16 @@
* Copyright (C) 2020 Amarula Solutions(India)
*/
-#include <common.h>
#include <clk-uclass.h>
#include <dm.h>
-#include <asm/global_data.h>
#include <dm/device_compat.h>
#include <dm/device-internal.h>
#include <dm/lists.h>
#include <generic-phy.h>
-#include <reset.h>
+#include <regmap.h>
#include <syscon.h>
-#include <asm/gpio.h>
-#include <asm/io.h>
-#include <linux/iopoll.h>
#include <asm/arch-rockchip/clock.h>
-DECLARE_GLOBAL_DATA_PTR;
-
#define usleep_range(a, b) udelay((b))
#define BIT_WRITEABLE_SHIFT 16
@@ -42,16 +35,6 @@
struct rockchip_usb2phy_port_cfg {
struct usb2phy_reg phy_sus;
- struct usb2phy_reg bvalid_det_en;
- struct usb2phy_reg bvalid_det_st;
- struct usb2phy_reg bvalid_det_clr;
- struct usb2phy_reg ls_det_en;
- struct usb2phy_reg ls_det_st;
- struct usb2phy_reg ls_det_clr;
- struct usb2phy_reg utmi_avalid;
- struct usb2phy_reg utmi_bvalid;
- struct usb2phy_reg utmi_ls;
- struct usb2phy_reg utmi_hstdet;
};
struct rockchip_usb2phy_cfg {
@@ -61,30 +44,39 @@
};
struct rockchip_usb2phy {
- void *reg_base;
+ struct regmap *reg_base;
struct clk phyclk;
const struct rockchip_usb2phy_cfg *phy_cfg;
};
-static inline int property_enable(void *reg_base,
+static inline int property_enable(struct regmap *base,
const struct usb2phy_reg *reg, bool en)
{
unsigned int val, mask, tmp;
+ if (!reg->offset && !reg->enable && !reg->disable)
+ return 0;
+
tmp = en ? reg->enable : reg->disable;
mask = GENMASK(reg->bitend, reg->bitstart);
val = (tmp << reg->bitstart) | (mask << BIT_WRITEABLE_SHIFT);
- return writel(val, reg_base + reg->offset);
+ return regmap_write(base, reg->offset, val);
}
-static inline bool property_enabled(void *reg_base,
+static inline bool property_enabled(struct regmap *base,
const struct usb2phy_reg *reg)
{
+ int ret;
unsigned int tmp, orig;
unsigned int mask = GENMASK(reg->bitend, reg->bitstart);
- orig = readl(reg_base + reg->offset);
+ if (!reg->offset && !reg->enable && !reg->disable)
+ return false;
+
+ ret = regmap_read(base, reg->offset, &orig);
+ if (ret)
+ return false;
tmp = (orig & mask) >> reg->bitstart;
return tmp != reg->disable;
@@ -129,7 +121,6 @@
{
struct udevice *parent = dev_get_parent(phy->dev);
struct rockchip_usb2phy *priv = dev_get_priv(parent);
- const struct rockchip_usb2phy_port_cfg *port_cfg = us2phy_get_port(phy);
int ret;
ret = clk_enable(&priv->phyclk);
@@ -138,14 +129,6 @@
return ret;
}
- if (phy->id == USB2PHY_PORT_OTG) {
- property_enable(priv->reg_base, &port_cfg->bvalid_det_clr, true);
- property_enable(priv->reg_base, &port_cfg->bvalid_det_en, true);
- } else if (phy->id == USB2PHY_PORT_HOST) {
- property_enable(priv->reg_base, &port_cfg->bvalid_det_clr, true);
- property_enable(priv->reg_base, &port_cfg->bvalid_det_en, true);
- }
-
return 0;
}
@@ -248,7 +231,11 @@
unsigned int reg;
int index, ret;
- priv->reg_base = syscon_get_first_range(ROCKCHIP_SYSCON_GRF);
+ if (dev_read_bool(dev, "rockchip,usbgrf"))
+ priv->reg_base =
+ syscon_regmap_lookup_by_phandle(dev, "rockchip,usbgrf");
+ else
+ priv->reg_base = syscon_get_regmap(dev_get_parent(dev));
if (IS_ERR(priv->reg_base))
return PTR_ERR(priv->reg_base);
@@ -305,11 +292,8 @@
int ret = 0;
dev_for_each_subnode(node, dev) {
- if (!ofnode_valid(node)) {
- dev_info(dev, "subnode %s not found\n", dev->name);
- ret = -ENXIO;
- goto bind_fail;
- }
+ if (!ofnode_is_enabled(node))
+ continue;
name = ofnode_get_name(node);
dev_dbg(dev, "subnode %s\n", name);
@@ -348,27 +332,13 @@
static const struct rockchip_usb2phy_cfg rk3328_usb2phy_cfgs[] = {
{
.reg = 0x100,
- .clkout_ctl = { 0x108, 4, 4, 1, 0 },
+ .clkout_ctl = { 0x0108, 4, 4, 1, 0 },
.port_cfgs = {
[USB2PHY_PORT_OTG] = {
- .phy_sus = { 0x0100, 15, 0, 0, 0x1d1 },
- .bvalid_det_en = { 0x0110, 3, 2, 0, 3 },
- .bvalid_det_st = { 0x0114, 3, 2, 0, 3 },
- .bvalid_det_clr = { 0x0118, 3, 2, 0, 3 },
- .ls_det_en = { 0x0110, 0, 0, 0, 1 },
- .ls_det_st = { 0x0114, 0, 0, 0, 1 },
- .ls_det_clr = { 0x0118, 0, 0, 0, 1 },
- .utmi_avalid = { 0x0120, 10, 10, 0, 1 },
- .utmi_bvalid = { 0x0120, 9, 9, 0, 1 },
- .utmi_ls = { 0x0120, 5, 4, 0, 1 },
+ .phy_sus = { 0x0100, 1, 0, 2, 1 },
},
[USB2PHY_PORT_HOST] = {
- .phy_sus = { 0x104, 15, 0, 0, 0x1d1 },
- .ls_det_en = { 0x110, 1, 1, 0, 1 },
- .ls_det_st = { 0x114, 1, 1, 0, 1 },
- .ls_det_clr = { 0x118, 1, 1, 0, 1 },
- .utmi_ls = { 0x120, 17, 16, 0, 1 },
- .utmi_hstdet = { 0x120, 19, 19, 0, 1 }
+ .phy_sus = { 0x0104, 1, 0, 2, 1 },
}
},
},
@@ -382,19 +352,9 @@
.port_cfgs = {
[USB2PHY_PORT_OTG] = {
.phy_sus = { 0xe454, 1, 0, 2, 1 },
- .bvalid_det_en = { 0xe3c0, 3, 3, 0, 1 },
- .bvalid_det_st = { 0xe3e0, 3, 3, 0, 1 },
- .bvalid_det_clr = { 0xe3d0, 3, 3, 0, 1 },
- .utmi_avalid = { 0xe2ac, 7, 7, 0, 1 },
- .utmi_bvalid = { 0xe2ac, 12, 12, 0, 1 },
},
[USB2PHY_PORT_HOST] = {
- .phy_sus = { 0xe458, 1, 0, 0x2, 0x1 },
- .ls_det_en = { 0xe3c0, 6, 6, 0, 1 },
- .ls_det_st = { 0xe3e0, 6, 6, 0, 1 },
- .ls_det_clr = { 0xe3d0, 6, 6, 0, 1 },
- .utmi_ls = { 0xe2ac, 22, 21, 0, 1 },
- .utmi_hstdet = { 0xe2ac, 23, 23, 0, 1 }
+ .phy_sus = { 0xe458, 1, 0, 2, 1 },
}
},
},
@@ -404,19 +364,9 @@
.port_cfgs = {
[USB2PHY_PORT_OTG] = {
.phy_sus = { 0xe464, 1, 0, 2, 1 },
- .bvalid_det_en = { 0xe3c0, 8, 8, 0, 1 },
- .bvalid_det_st = { 0xe3e0, 8, 8, 0, 1 },
- .bvalid_det_clr = { 0xe3d0, 8, 8, 0, 1 },
- .utmi_avalid = { 0xe2ac, 10, 10, 0, 1 },
- .utmi_bvalid = { 0xe2ac, 16, 16, 0, 1 },
},
[USB2PHY_PORT_HOST] = {
- .phy_sus = { 0xe468, 1, 0, 0x2, 0x1 },
- .ls_det_en = { 0xe3c0, 11, 11, 0, 1 },
- .ls_det_st = { 0xe3e0, 11, 11, 0, 1 },
- .ls_det_clr = { 0xe3d0, 11, 11, 0, 1 },
- .utmi_ls = { 0xe2ac, 26, 25, 0, 1 },
- .utmi_hstdet = { 0xe2ac, 27, 27, 0, 1 }
+ .phy_sus = { 0xe468, 1, 0, 2, 1 },
}
},
},
@@ -429,24 +379,10 @@
.clkout_ctl = { 0x0008, 4, 4, 1, 0 },
.port_cfgs = {
[USB2PHY_PORT_OTG] = {
- .phy_sus = { 0x0000, 8, 0, 0x052, 0x1d1 },
- .bvalid_det_en = { 0x0080, 2, 2, 0, 1 },
- .bvalid_det_st = { 0x0084, 2, 2, 0, 1 },
- .bvalid_det_clr = { 0x0088, 2, 2, 0, 1 },
- .ls_det_en = { 0x0080, 0, 0, 0, 1 },
- .ls_det_st = { 0x0084, 0, 0, 0, 1 },
- .ls_det_clr = { 0x0088, 0, 0, 0, 1 },
- .utmi_avalid = { 0x00c0, 10, 10, 0, 1 },
- .utmi_bvalid = { 0x00c0, 9, 9, 0, 1 },
- .utmi_ls = { 0x00c0, 5, 4, 0, 1 },
+ .phy_sus = { 0x0000, 1, 0, 2, 1 },
},
[USB2PHY_PORT_HOST] = {
- .phy_sus = { 0x0004, 8, 0, 0x1d2, 0x1d1 },
- .ls_det_en = { 0x0080, 1, 1, 0, 1 },
- .ls_det_st = { 0x0084, 1, 1, 0, 1 },
- .ls_det_clr = { 0x0088, 1, 1, 0, 1 },
- .utmi_ls = { 0x00c0, 17, 16, 0, 1 },
- .utmi_hstdet = { 0x00c0, 19, 19, 0, 1 }
+ .phy_sus = { 0x0004, 1, 0, 2, 1 },
}
},
},
@@ -455,20 +391,10 @@
.clkout_ctl = { 0x0008, 4, 4, 1, 0 },
.port_cfgs = {
[USB2PHY_PORT_OTG] = {
- .phy_sus = { 0x0000, 8, 0, 0x1d2, 0x1d1 },
- .ls_det_en = { 0x0080, 0, 0, 0, 1 },
- .ls_det_st = { 0x0084, 0, 0, 0, 1 },
- .ls_det_clr = { 0x0088, 0, 0, 0, 1 },
- .utmi_ls = { 0x00c0, 5, 4, 0, 1 },
- .utmi_hstdet = { 0x00c0, 7, 7, 0, 1 }
+ .phy_sus = { 0x0000, 1, 0, 2, 1 },
},
[USB2PHY_PORT_HOST] = {
- .phy_sus = { 0x0004, 8, 0, 0x1d2, 0x1d1 },
- .ls_det_en = { 0x0080, 1, 1, 0, 1 },
- .ls_det_st = { 0x0084, 1, 1, 0, 1 },
- .ls_det_clr = { 0x0088, 1, 1, 0, 1 },
- .utmi_ls = { 0x00c0, 17, 16, 0, 1 },
- .utmi_hstdet = { 0x00c0, 19, 19, 0, 1 }
+ .phy_sus = { 0x0004, 1, 0, 2, 1 },
}
},
},
@@ -478,49 +404,37 @@
static const struct rockchip_usb2phy_cfg rk3588_phy_cfgs[] = {
{
.reg = 0x0000,
+ .clkout_ctl = { 0x0000, 0, 0, 1, 0 },
.port_cfgs = {
[USB2PHY_PORT_OTG] = {
.phy_sus = { 0x000c, 11, 11, 0, 1 },
- .ls_det_en = { 0x0080, 0, 0, 0, 1 },
- .ls_det_st = { 0x0084, 0, 0, 0, 1 },
- .ls_det_clr = { 0x0088, 0, 0, 0, 1 },
- .utmi_ls = { 0x00c0, 10, 9, 0, 1 },
}
},
},
{
.reg = 0x4000,
+ .clkout_ctl = { 0x0000, 0, 0, 1, 0 },
.port_cfgs = {
[USB2PHY_PORT_OTG] = {
- .phy_sus = { 0x000c, 11, 11, 0, 0 },
- .ls_det_en = { 0x0080, 0, 0, 0, 1 },
- .ls_det_st = { 0x0084, 0, 0, 0, 1 },
- .ls_det_clr = { 0x0088, 0, 0, 0, 1 },
- .utmi_ls = { 0x00c0, 10, 9, 0, 1 },
+ .phy_sus = { 0x000c, 11, 11, 0, 1 },
}
},
},
{
.reg = 0x8000,
+ .clkout_ctl = { 0x0000, 0, 0, 1, 0 },
.port_cfgs = {
[USB2PHY_PORT_HOST] = {
.phy_sus = { 0x0008, 2, 2, 0, 1 },
- .ls_det_en = { 0x0080, 0, 0, 0, 1 },
- .ls_det_st = { 0x0084, 0, 0, 0, 1 },
- .ls_det_clr = { 0x0088, 0, 0, 0, 1 },
- .utmi_ls = { 0x00c0, 10, 9, 0, 1 },
}
},
},
{
.reg = 0xc000,
+ .clkout_ctl = { 0x0000, 0, 0, 1, 0 },
.port_cfgs = {
[USB2PHY_PORT_HOST] = {
.phy_sus = { 0x0008, 2, 2, 0, 1 },
- .ls_det_en = { 0x0080, 0, 0, 0, 1 },
- .ls_det_st = { 0x0084, 0, 0, 0, 1 },
- .ls_det_clr = { 0x0088, 0, 0, 0, 1 },
- .utmi_ls = { 0x00c0, 10, 9, 0, 1 },
}
},
},
diff --git a/drivers/pinctrl/qcom/pinctrl-apq8016.c b/drivers/pinctrl/qcom/pinctrl-apq8016.c
index db0e212..a9a00f4 100644
--- a/drivers/pinctrl/qcom/pinctrl-apq8016.c
+++ b/drivers/pinctrl/qcom/pinctrl-apq8016.c
@@ -49,7 +49,8 @@
}
}
-static unsigned int apq8016_get_function_mux(unsigned int selector)
+static unsigned int apq8016_get_function_mux(__maybe_unused unsigned int pin,
+ unsigned int selector)
{
return msm_pinctrl_functions[selector].val;
}
diff --git a/drivers/pinctrl/qcom/pinctrl-apq8096.c b/drivers/pinctrl/qcom/pinctrl-apq8096.c
index 880df8f..9697cb5 100644
--- a/drivers/pinctrl/qcom/pinctrl-apq8096.c
+++ b/drivers/pinctrl/qcom/pinctrl-apq8096.c
@@ -44,7 +44,8 @@
}
}
-static unsigned int apq8096_get_function_mux(unsigned int selector)
+static unsigned int apq8096_get_function_mux(__maybe_unused unsigned int pin,
+ unsigned int selector)
{
return msm_pinctrl_functions[selector].val;
}
diff --git a/drivers/pinctrl/qcom/pinctrl-ipq4019.c b/drivers/pinctrl/qcom/pinctrl-ipq4019.c
index 74c04ab..4479230 100644
--- a/drivers/pinctrl/qcom/pinctrl-ipq4019.c
+++ b/drivers/pinctrl/qcom/pinctrl-ipq4019.c
@@ -40,7 +40,8 @@
return pin_name;
}
-static unsigned int ipq4019_get_function_mux(unsigned int selector)
+static unsigned int ipq4019_get_function_mux(__maybe_unused unsigned int pin,
+ unsigned int selector)
{
return msm_pinctrl_functions[selector].val;
}
diff --git a/drivers/pinctrl/qcom/pinctrl-qcom.c b/drivers/pinctrl/qcom/pinctrl-qcom.c
index ee0624d..909e566 100644
--- a/drivers/pinctrl/qcom/pinctrl-qcom.c
+++ b/drivers/pinctrl/qcom/pinctrl-qcom.c
@@ -83,14 +83,14 @@
unsigned int func_selector)
{
struct msm_pinctrl_priv *priv = dev_get_priv(dev);
+ u32 func = priv->data->get_function_mux(pin_selector, func_selector);
/* Always NOP for special pins, assume they're in the correct state */
if (qcom_is_special_pin(&priv->data->pin_data, pin_selector))
return 0;
clrsetbits_le32(priv->base + GPIO_CONFIG_REG(priv, pin_selector),
- TLMM_FUNC_SEL_MASK | TLMM_GPIO_DISABLE,
- priv->data->get_function_mux(func_selector) << 2);
+ TLMM_FUNC_SEL_MASK | TLMM_GPIO_DISABLE, func << 2);
return 0;
}
diff --git a/drivers/pinctrl/qcom/pinctrl-qcom.h b/drivers/pinctrl/qcom/pinctrl-qcom.h
index 07f2eae..49b7bfb 100644
--- a/drivers/pinctrl/qcom/pinctrl-qcom.h
+++ b/drivers/pinctrl/qcom/pinctrl-qcom.h
@@ -18,7 +18,8 @@
int functions_count;
const char *(*get_function_name)(struct udevice *dev,
unsigned int selector);
- unsigned int (*get_function_mux)(unsigned int selector);
+ unsigned int (*get_function_mux)(unsigned int pin,
+ unsigned int selector);
const char *(*get_pin_name)(struct udevice *dev,
unsigned int selector);
};
diff --git a/drivers/pinctrl/qcom/pinctrl-qcs404.c b/drivers/pinctrl/qcom/pinctrl-qcs404.c
index 3a2d468..4b7c670 100644
--- a/drivers/pinctrl/qcom/pinctrl-qcs404.c
+++ b/drivers/pinctrl/qcom/pinctrl-qcs404.c
@@ -94,7 +94,8 @@
}
}
-static unsigned int qcs404_get_function_mux(unsigned int selector)
+static unsigned int qcs404_get_function_mux(__maybe_unused unsigned int pin,
+ unsigned int selector)
{
return msm_pinctrl_functions[selector].val;
}
diff --git a/drivers/pinctrl/qcom/pinctrl-sdm845.c b/drivers/pinctrl/qcom/pinctrl-sdm845.c
index 76bd8c4..459a432 100644
--- a/drivers/pinctrl/qcom/pinctrl-sdm845.c
+++ b/drivers/pinctrl/qcom/pinctrl-sdm845.c
@@ -70,7 +70,8 @@
return pin_name;
}
-static unsigned int sdm845_get_function_mux(unsigned int selector)
+static unsigned int sdm845_get_function_mux(__maybe_unused unsigned int pin,
+ unsigned int selector)
{
return msm_pinctrl_functions[selector].val;
}
diff --git a/drivers/power/domain/imx8mp-hsiomix.c b/drivers/power/domain/imx8mp-hsiomix.c
index e2d772c..6188a04 100644
--- a/drivers/power/domain/imx8mp-hsiomix.c
+++ b/drivers/power/domain/imx8mp-hsiomix.c
@@ -6,9 +6,15 @@
#include <common.h>
#include <asm/io.h>
#include <clk.h>
+#include <clk-uclass.h>
#include <dm.h>
#include <dm/device.h>
#include <dm/device_compat.h>
+#include <dm/device-internal.h>
+#include <dm/lists.h>
+#include <linux/bitfield.h>
+#include <linux/delay.h>
+#include <linux/iopoll.h>
#include <power-domain-uclass.h>
#include <dt-bindings/power/imx8mp-power.h>
@@ -16,48 +22,94 @@
#define GPR_REG0 0x0
#define PCIE_CLOCK_MODULE_EN BIT(0)
#define USB_CLOCK_MODULE_EN BIT(1)
+#define PCIE_PHY_APB_RST BIT(4)
+#define PCIE_PHY_INIT_RST BIT(5)
+#define GPR_REG1 0x4
+#define PLL_LOCK BIT(13)
+#define GPR_REG2 0x8
+#define P_PLL_MASK GENMASK(5, 0)
+#define M_PLL_MASK GENMASK(15, 6)
+#define S_PLL_MASK GENMASK(18, 16)
+#define GPR_REG3 0xc
+#define PLL_CKE BIT(17)
+#define PLL_RST BIT(31)
struct imx8mp_hsiomix_priv {
void __iomem *base;
struct clk clk_usb;
+ struct clk clk_pcie;
struct power_domain pd_bus;
struct power_domain pd_usb;
+ struct power_domain pd_pcie;
struct power_domain pd_usb_phy1;
struct power_domain pd_usb_phy2;
+ struct power_domain pd_pcie_phy;
};
-static int imx8mp_hsiomix_on(struct power_domain *power_domain)
+static int imx8mp_hsiomix_set(struct power_domain *power_domain, bool power_on)
{
struct udevice *dev = power_domain->dev;
struct imx8mp_hsiomix_priv *priv = dev_get_priv(dev);
- struct power_domain *domain;
+ struct power_domain *domain = NULL;
+ struct clk *clk = NULL;
+ u32 gpr_reg0_bits = 0;
int ret;
- ret = power_domain_on(&priv->pd_bus);
- if (ret)
- return ret;
-
- if (power_domain->id == IMX8MP_HSIOBLK_PD_USB) {
+ switch (power_domain->id) {
+ case IMX8MP_HSIOBLK_PD_USB:
domain = &priv->pd_usb;
- } else if (power_domain->id == IMX8MP_HSIOBLK_PD_USB_PHY1) {
+ clk = &priv->clk_usb;
+ gpr_reg0_bits |= USB_CLOCK_MODULE_EN;
+ break;
+ case IMX8MP_HSIOBLK_PD_USB_PHY1:
domain = &priv->pd_usb_phy1;
- } else if (power_domain->id == IMX8MP_HSIOBLK_PD_USB_PHY2) {
+ break;
+ case IMX8MP_HSIOBLK_PD_USB_PHY2:
domain = &priv->pd_usb_phy2;
- } else {
- ret = -EINVAL;
- goto err_pd;
+ break;
+ case IMX8MP_HSIOBLK_PD_PCIE:
+ domain = &priv->pd_pcie;
+ clk = &priv->clk_pcie;
+ gpr_reg0_bits |= PCIE_CLOCK_MODULE_EN;
+ break;
+ case IMX8MP_HSIOBLK_PD_PCIE_PHY:
+ domain = &priv->pd_pcie_phy;
+ /* Bits to deassert PCIe PHY reset */
+ gpr_reg0_bits |= PCIE_PHY_APB_RST | PCIE_PHY_INIT_RST;
+ break;
+ default:
+ dev_err(dev, "unknown power domain id: %ld\n",
+ power_domain->id);
+ return -EINVAL;
}
- ret = power_domain_on(domain);
- if (ret)
- goto err_pd;
+ if (power_on) {
+ ret = power_domain_on(&priv->pd_bus);
+ if (ret)
+ return ret;
- ret = clk_enable(&priv->clk_usb);
- if (ret)
- goto err_clk;
+ ret = power_domain_on(domain);
+ if (ret)
+ goto err_pd;
- if (power_domain->id == IMX8MP_HSIOBLK_PD_USB)
- setbits_le32(priv->base + GPR_REG0, USB_CLOCK_MODULE_EN);
+ if (clk) {
+ ret = clk_enable(clk);
+ if (ret)
+ goto err_clk;
+ }
+
+ if (gpr_reg0_bits)
+ setbits_le32(priv->base + GPR_REG0, gpr_reg0_bits);
+ } else {
+ if (gpr_reg0_bits)
+ clrbits_le32(priv->base + GPR_REG0, gpr_reg0_bits);
+
+ if (clk)
+ clk_disable(clk);
+
+ power_domain_off(domain);
+ power_domain_off(&priv->pd_bus);
+ }
return 0;
@@ -68,36 +120,85 @@
return ret;
}
+static int imx8mp_hsiomix_on(struct power_domain *power_domain)
+{
+ return imx8mp_hsiomix_set(power_domain, true);
+}
+
static int imx8mp_hsiomix_off(struct power_domain *power_domain)
{
- struct udevice *dev = power_domain->dev;
- struct imx8mp_hsiomix_priv *priv = dev_get_priv(dev);
+ return imx8mp_hsiomix_set(power_domain, false);
+}
+
+static int imx8mp_hsiomix_of_xlate(struct power_domain *power_domain,
+ struct ofnode_phandle_args *args)
+{
+ power_domain->id = args->args[0];
+
+ return 0;
+}
- if (power_domain->id == IMX8MP_HSIOBLK_PD_USB)
- clrbits_le32(priv->base + GPR_REG0, USB_CLOCK_MODULE_EN);
+static int hsio_pll_clk_enable(struct clk *clk)
+{
+ void *base = (void *)dev_get_driver_data(clk->dev);
+ u32 val;
+ int ret;
- clk_disable(&priv->clk_usb);
+ /* Setup HSIO PLL as 100 MHz output clock */
+ clrsetbits_le32(base + GPR_REG2,
+ P_PLL_MASK | M_PLL_MASK | S_PLL_MASK,
+ FIELD_PREP(P_PLL_MASK, 12) |
+ FIELD_PREP(M_PLL_MASK, 800) |
+ FIELD_PREP(S_PLL_MASK, 4));
- if (power_domain->id == IMX8MP_HSIOBLK_PD_USB)
- power_domain_off(&priv->pd_usb);
- else if (power_domain->id == IMX8MP_HSIOBLK_PD_USB_PHY1)
- power_domain_off(&priv->pd_usb_phy1);
- else if (power_domain->id == IMX8MP_HSIOBLK_PD_USB_PHY2)
- power_domain_off(&priv->pd_usb_phy2);
+ /* de-assert PLL reset */
+ setbits_le32(base + GPR_REG3, PLL_RST);
- power_domain_off(&priv->pd_bus);
+ /* enable PLL */
+ setbits_le32(base + GPR_REG3, PLL_CKE);
- return 0;
+ /* Check if PLL is locked */
+ ret = readl_poll_sleep_timeout(base + GPR_REG1, val,
+ val & PLL_LOCK, 10, 100000);
+ if (ret)
+ dev_err(clk->dev, "failed to lock HSIO PLL\n");
+
+ return ret;
}
-static int imx8mp_hsiomix_of_xlate(struct power_domain *power_domain,
- struct ofnode_phandle_args *args)
+static int hsio_pll_clk_disable(struct clk *clk)
{
- power_domain->id = args->args[0];
+ void *base = (void *)dev_get_driver_data(clk->dev);
+
+ clrbits_le32(base + GPR_REG3, PLL_CKE | PLL_RST);
return 0;
}
+static const struct clk_ops hsio_pll_clk_ops = {
+ .enable = hsio_pll_clk_enable,
+ .disable = hsio_pll_clk_disable,
+};
+
+U_BOOT_DRIVER(hsio_pll) = {
+ .name = "hsio-pll",
+ .id = UCLASS_CLK,
+ .ops = &hsio_pll_clk_ops,
+};
+
+int imx8mp_hsiomix_bind(struct udevice *dev)
+{
+ struct driver *drv;
+
+ drv = lists_driver_lookup_name("hsio-pll");
+ if (!drv)
+ return -ENOENT;
+
+ return device_bind_with_driver_data(dev, drv, "hsio-pll",
+ (ulong)dev_read_addr_ptr(dev),
+ dev_ofnode(dev), NULL);
+}
+
static int imx8mp_hsiomix_probe(struct udevice *dev)
{
struct imx8mp_hsiomix_priv *priv = dev_get_priv(dev);
@@ -109,6 +210,10 @@
if (ret < 0)
return ret;
+ ret = clk_get_by_name(dev, "pcie", &priv->clk_pcie);
+ if (ret < 0)
+ return ret;
+
ret = power_domain_get_by_name(dev, &priv->pd_bus, "bus");
if (ret < 0)
return ret;
@@ -125,8 +230,20 @@
if (ret < 0)
goto err_pd_usb_phy2;
+ ret = power_domain_get_by_name(dev, &priv->pd_pcie, "pcie");
+ if (ret < 0)
+ goto err_pd_pcie;
+
+ ret = power_domain_get_by_name(dev, &priv->pd_pcie_phy, "pcie-phy");
+ if (ret < 0)
+ goto err_pd_pcie_phy;
+
return 0;
+err_pd_pcie_phy:
+ power_domain_free(&priv->pd_pcie);
+err_pd_pcie:
+ power_domain_free(&priv->pd_usb_phy2);
err_pd_usb_phy2:
power_domain_free(&priv->pd_usb_phy1);
err_pd_usb_phy1:
@@ -152,6 +269,7 @@
.id = UCLASS_POWER_DOMAIN,
.of_match = imx8mp_hsiomix_ids,
.probe = imx8mp_hsiomix_probe,
+ .bind = imx8mp_hsiomix_bind,
.priv_auto = sizeof(struct imx8mp_hsiomix_priv),
.ops = &imx8mp_hsiomix_ops,
};
diff --git a/drivers/power/pmic/Kconfig b/drivers/power/pmic/Kconfig
index 9b61b18..562c1a3 100644
--- a/drivers/power/pmic/Kconfig
+++ b/drivers/power/pmic/Kconfig
@@ -250,7 +250,7 @@
This driver implements register read/write operations.
config SPL_PMIC_RK8XX
- bool "Enable support for Rockchip PMIC RK8XX"
+ bool "Enable support for Rockchip PMIC RK8XX in SPL"
depends on SPL_DM_PMIC
---help---
The Rockchip RK808 PMIC provides four buck DC-DC convertors, 8 LDOs,
diff --git a/drivers/power/pmic/rk8xx.c b/drivers/power/pmic/rk8xx.c
index 4e3a173..3a8261d 100644
--- a/drivers/power/pmic/rk8xx.c
+++ b/drivers/power/pmic/rk8xx.c
@@ -9,8 +9,10 @@
#include <dm/lists.h>
#include <errno.h>
#include <log.h>
+#include <linux/bitfield.h>
#include <power/rk8xx_pmic.h>
#include <power/pmic.h>
+#include <spi.h>
#include <sysreset.h>
static int rk8xx_sysreset_request(struct udevice *dev, enum sysreset_t type)
@@ -32,6 +34,10 @@
pmic_clrsetbits(dev->parent, RK817_REG_SYS_CFG3, 0,
BIT(0));
break;
+ case RK806_ID:
+ pmic_clrsetbits(dev->parent, RK806_REG_SYS_CFG3, 0,
+ BIT(0));
+ break;
default:
printf("Unknown PMIC RK%x: Cannot shutdown\n",
priv->variant);
@@ -83,6 +89,11 @@
}
}
+static struct reg_data rk806_init_reg[] = {
+ /* RST_FUN */
+ { RK806_REG_SYS_CFG3, GENMASK(7, 6), BIT(7)},
+};
+
static struct reg_data rk817_init_reg[] = {
/* enable the under-voltage protection,
* the under-voltage protection will shutdown the LDO3 and reset the PMIC
@@ -92,7 +103,10 @@
static const struct pmic_child_info pmic_children_info[] = {
{ .prefix = "DCDC_REG", .driver = "rk8xx_buck"},
+ { .prefix = "dcdc-reg", .driver = "rk8xx_buck"},
{ .prefix = "LDO_REG", .driver = "rk8xx_ldo"},
+ { .prefix = "nldo-reg", .driver = "rk8xx_nldo"},
+ { .prefix = "pldo-reg", .driver = "rk8xx_pldo"},
{ .prefix = "SWITCH_REG", .driver = "rk8xx_switch"},
{ },
};
@@ -102,11 +116,51 @@
return RK808_NUM_OF_REGS;
}
+#if CONFIG_IS_ENABLED(SPI) && CONFIG_IS_ENABLED(DM_SPI)
+struct rk806_cmd {
+ uint8_t len: 4; /* Payload size in bytes - 1 */
+ uint8_t reserved: 2;
+ uint8_t crc_en: 1;
+ uint8_t op: 1; /* READ=0; WRITE=1; */
+ uint8_t reg_l;
+#define REG_L_MASK GENMASK(7, 0)
+ uint8_t reg_h;
+#define REG_H_MASK GENMASK(15, 8)
+};
+#endif
+
static int rk8xx_write(struct udevice *dev, uint reg, const uint8_t *buff,
int len)
{
int ret;
+#if CONFIG_IS_ENABLED(SPI) && CONFIG_IS_ENABLED(DM_SPI)
+ if (device_get_uclass_id(dev->parent) == UCLASS_SPI) {
+ struct spi_slave *spi = dev_get_parent_priv(dev);
+ struct rk806_cmd cmd = {
+ .op = 1,
+ .len = len - 1,
+ .reg_l = FIELD_GET(REG_L_MASK, reg),
+ .reg_h = FIELD_GET(REG_H_MASK, reg),
+ };
+
+ ret = dm_spi_claim_bus(dev);
+ if (ret) {
+ debug("Couldn't claim bus for device: %p!\n", dev);
+ return ret;
+ }
+
+ ret = spi_write_then_read(spi, (u8 *)&cmd, sizeof(cmd), buff, NULL, len);
+ if (ret)
+ debug("write error to device: %p register: %#x!\n",
+ dev, reg);
+
+ dm_spi_release_bus(dev);
+
+ return ret;
+ }
+#endif
+
ret = dm_i2c_write(dev, reg, buff, len);
if (ret) {
debug("write error to device: %p register: %#x!\n", dev, reg);
@@ -120,6 +174,33 @@
{
int ret;
+#if CONFIG_IS_ENABLED(SPI) && CONFIG_IS_ENABLED(DM_SPI)
+ if (device_get_uclass_id(dev->parent) == UCLASS_SPI) {
+ struct spi_slave *spi = dev_get_parent_priv(dev);
+ struct rk806_cmd cmd = {
+ .op = 0,
+ .len = len - 1,
+ .reg_l = FIELD_GET(REG_L_MASK, reg),
+ .reg_h = FIELD_GET(REG_H_MASK, reg),
+ };
+
+ ret = dm_spi_claim_bus(dev);
+ if (ret) {
+ debug("Couldn't claim bus for device: %p!\n", dev);
+ return ret;
+ }
+
+ ret = spi_write_then_read(spi, (u8 *)&cmd, sizeof(cmd), NULL, buff, len);
+ if (ret)
+ debug("read error to device: %p register: %#x!\n",
+ dev, reg);
+
+ dm_spi_release_bus(dev);
+
+ return ret;
+ }
+#endif
+
ret = dm_i2c_read(dev, reg, buff, len);
if (ret) {
debug("read error from device: %p register: %#x!\n", dev, reg);
@@ -181,6 +262,9 @@
device_is_compatible(dev, "rockchip,rk809")) {
id_msb = RK817_ID_MSB;
id_lsb = RK817_ID_LSB;
+ } else if (device_is_compatible(dev, "rockchip,rk806")) {
+ id_msb = RK806_ID_MSB;
+ id_lsb = RK806_ID_LSB;
} else {
id_msb = ID_MSB;
id_lsb = ID_LSB;
@@ -221,6 +305,12 @@
value = (power_en2 & 0x0f) | ((power_en3 & 0x0f) << 4);
pmic_reg_write(dev, RK817_POWER_EN_SAVE1, value);
break;
+ case RK806_ID:
+ on_source = RK806_ON_SOURCE;
+ off_source = RK806_OFF_SOURCE;
+ init_data = rk806_init_reg;
+ init_data_num = ARRAY_SIZE(rk806_init_reg);
+ break;
default:
printf("Unknown PMIC: RK%x!!\n", priv->variant);
return -EINVAL;
@@ -263,6 +353,7 @@
static const struct udevice_id rk8xx_ids[] = {
{ .compatible = "rockchip,rk805" },
+ { .compatible = "rockchip,rk806" },
{ .compatible = "rockchip,rk808" },
{ .compatible = "rockchip,rk809" },
{ .compatible = "rockchip,rk816" },
diff --git a/drivers/power/regulator/rk8xx.c b/drivers/power/regulator/rk8xx.c
index e80bd6c..1bd4605 100644
--- a/drivers/power/regulator/rk8xx.c
+++ b/drivers/power/regulator/rk8xx.c
@@ -25,6 +25,19 @@
#define NA 0xff
/* Field Definitions */
+#define RK806_BUCK_CONFIG(n) (0x10 + (n) - 1)
+#define RK806_BUCK_ON_VSEL(n) (0x1a + (n) - 1)
+#define RK806_BUCK_SLP_VSEL(n) (0x24 + (n) - 1)
+#define RK806_BUCK_VSEL_MASK 0xff
+
+#define RK806_NLDO_ON_VSEL(n) (0x43 + (n) - 1)
+#define RK806_NLDO_SLP_VSEL(n) (0x48 + (n) - 1)
+#define RK806_NLDO_VSEL_MASK 0xff
+
+#define RK806_PLDO_ON_VSEL(n) (0x4e + (n) - 1)
+#define RK806_PLDO_SLP_VSEL(n) (0x54 + (n) - 1)
+#define RK806_PLDO_VSEL_MASK 0xff
+
#define RK808_BUCK_VSEL_MASK 0x3f
#define RK808_BUCK4_VSEL_MASK 0xf
#define RK808_LDO_VSEL_MASK 0x1f
@@ -91,6 +104,49 @@
u8 max_sel;
};
+static const struct rk8xx_reg_info rk806_buck[] = {
+ /* buck 1 */
+ { 500000, 6250, RK806_BUCK_ON_VSEL(1), RK806_BUCK_SLP_VSEL(1), RK806_BUCK_CONFIG(1), RK806_BUCK_VSEL_MASK, 0x00, 0x9f },
+ { 1500000, 25000, RK806_BUCK_ON_VSEL(1), RK806_BUCK_SLP_VSEL(1), RK806_BUCK_CONFIG(1), RK806_BUCK_VSEL_MASK, 0xa0, 0xeb },
+ { 3400000, 0, RK806_BUCK_ON_VSEL(1), RK806_BUCK_SLP_VSEL(1), RK806_BUCK_CONFIG(1), RK806_BUCK_VSEL_MASK, 0xec, 0xff },
+ /* buck 2 */
+ { 500000, 6250, RK806_BUCK_ON_VSEL(2), RK806_BUCK_SLP_VSEL(2), RK806_BUCK_CONFIG(2), RK806_BUCK_VSEL_MASK, 0x00, 0x9f },
+ { 1500000, 25000, RK806_BUCK_ON_VSEL(2), RK806_BUCK_SLP_VSEL(2), RK806_BUCK_CONFIG(2), RK806_BUCK_VSEL_MASK, 0xa0, 0xeb },
+ { 3400000, 0, RK806_BUCK_ON_VSEL(2), RK806_BUCK_SLP_VSEL(2), RK806_BUCK_CONFIG(2), RK806_BUCK_VSEL_MASK, 0xec, 0xff },
+ /* buck 3 */
+ { 500000, 6250, RK806_BUCK_ON_VSEL(3), RK806_BUCK_SLP_VSEL(3), RK806_BUCK_CONFIG(3), RK806_BUCK_VSEL_MASK, 0x00, 0x9f },
+ { 1500000, 25000, RK806_BUCK_ON_VSEL(3), RK806_BUCK_SLP_VSEL(3), RK806_BUCK_CONFIG(3), RK806_BUCK_VSEL_MASK, 0xa0, 0xeb },
+ { 3400000, 0, RK806_BUCK_ON_VSEL(3), RK806_BUCK_SLP_VSEL(3), RK806_BUCK_CONFIG(3), RK806_BUCK_VSEL_MASK, 0xec, 0xff },
+ /* buck 4 */
+ { 500000, 6250, RK806_BUCK_ON_VSEL(4), RK806_BUCK_SLP_VSEL(4), RK806_BUCK_CONFIG(4), RK806_BUCK_VSEL_MASK, 0x00, 0x9f },
+ { 1500000, 25000, RK806_BUCK_ON_VSEL(4), RK806_BUCK_SLP_VSEL(4), RK806_BUCK_CONFIG(4), RK806_BUCK_VSEL_MASK, 0xa0, 0xeb },
+ { 3400000, 0, RK806_BUCK_ON_VSEL(4), RK806_BUCK_SLP_VSEL(4), RK806_BUCK_CONFIG(4), RK806_BUCK_VSEL_MASK, 0xec, 0xff },
+ /* buck 5 */
+ { 500000, 6250, RK806_BUCK_ON_VSEL(5), RK806_BUCK_SLP_VSEL(5), RK806_BUCK_CONFIG(5), RK806_BUCK_VSEL_MASK, 0x00, 0x9f },
+ { 1500000, 25000, RK806_BUCK_ON_VSEL(5), RK806_BUCK_SLP_VSEL(5), RK806_BUCK_CONFIG(5), RK806_BUCK_VSEL_MASK, 0xa0, 0xeb },
+ { 3400000, 0, RK806_BUCK_ON_VSEL(5), RK806_BUCK_SLP_VSEL(5), RK806_BUCK_CONFIG(5), RK806_BUCK_VSEL_MASK, 0xec, 0xff },
+ /* buck 6 */
+ { 500000, 6250, RK806_BUCK_ON_VSEL(6), RK806_BUCK_SLP_VSEL(6), RK806_BUCK_CONFIG(6), RK806_BUCK_VSEL_MASK, 0x00, 0x9f },
+ { 1500000, 25000, RK806_BUCK_ON_VSEL(6), RK806_BUCK_SLP_VSEL(6), RK806_BUCK_CONFIG(6), RK806_BUCK_VSEL_MASK, 0xa0, 0xeb },
+ { 3400000, 0, RK806_BUCK_ON_VSEL(6), RK806_BUCK_SLP_VSEL(6), RK806_BUCK_CONFIG(6), RK806_BUCK_VSEL_MASK, 0xec, 0xff },
+ /* buck 7 */
+ { 500000, 6250, RK806_BUCK_ON_VSEL(7), RK806_BUCK_SLP_VSEL(7), RK806_BUCK_CONFIG(7), RK806_BUCK_VSEL_MASK, 0x00, 0x9f },
+ { 1500000, 25000, RK806_BUCK_ON_VSEL(7), RK806_BUCK_SLP_VSEL(7), RK806_BUCK_CONFIG(7), RK806_BUCK_VSEL_MASK, 0xa0, 0xeb },
+ { 3400000, 0, RK806_BUCK_ON_VSEL(7), RK806_BUCK_SLP_VSEL(7), RK806_BUCK_CONFIG(7), RK806_BUCK_VSEL_MASK, 0xec, 0xff },
+ /* buck 8 */
+ { 500000, 6250, RK806_BUCK_ON_VSEL(8), RK806_BUCK_SLP_VSEL(8), RK806_BUCK_CONFIG(8), RK806_BUCK_VSEL_MASK, 0x00, 0x9f },
+ { 1500000, 25000, RK806_BUCK_ON_VSEL(8), RK806_BUCK_SLP_VSEL(8), RK806_BUCK_CONFIG(8), RK806_BUCK_VSEL_MASK, 0xa0, 0xeb },
+ { 3400000, 0, RK806_BUCK_ON_VSEL(8), RK806_BUCK_SLP_VSEL(8), RK806_BUCK_CONFIG(8), RK806_BUCK_VSEL_MASK, 0xec, 0xff },
+ /* buck 9 */
+ { 500000, 6250, RK806_BUCK_ON_VSEL(9), RK806_BUCK_SLP_VSEL(9), RK806_BUCK_CONFIG(9), RK806_BUCK_VSEL_MASK, 0x00, 0x9f },
+ { 1500000, 25000, RK806_BUCK_ON_VSEL(9), RK806_BUCK_SLP_VSEL(9), RK806_BUCK_CONFIG(9), RK806_BUCK_VSEL_MASK, 0xa0, 0xeb },
+ { 3400000, 0, RK806_BUCK_ON_VSEL(9), RK806_BUCK_SLP_VSEL(9), RK806_BUCK_CONFIG(9), RK806_BUCK_VSEL_MASK, 0xec, 0xff },
+ /* buck 10 */
+ { 500000, 6250, RK806_BUCK_ON_VSEL(10), RK806_BUCK_SLP_VSEL(10), RK806_BUCK_CONFIG(10), RK806_BUCK_VSEL_MASK, 0x00, 0x9f },
+ { 1500000, 25000, RK806_BUCK_ON_VSEL(10), RK806_BUCK_SLP_VSEL(10), RK806_BUCK_CONFIG(10), RK806_BUCK_VSEL_MASK, 0xa0, 0xeb },
+ { 3400000, 0, RK806_BUCK_ON_VSEL(10), RK806_BUCK_SLP_VSEL(10), RK806_BUCK_CONFIG(10), RK806_BUCK_VSEL_MASK, 0xec, 0xff },
+};
+
static const struct rk8xx_reg_info rk808_buck[] = {
{ 712500, 12500, REG_BUCK1_ON_VSEL, REG_BUCK1_SLP_VSEL, REG_BUCK1_CONFIG, RK808_BUCK_VSEL_MASK, 0x00, 0x3f },
{ 712500, 12500, REG_BUCK2_ON_VSEL, REG_BUCK2_SLP_VSEL, REG_BUCK2_CONFIG, RK808_BUCK_VSEL_MASK, 0x00, 0x3f },
@@ -148,6 +204,45 @@
};
#ifdef ENABLE_DRIVER
+static const struct rk8xx_reg_info rk806_nldo[] = {
+ /* nldo 1 */
+ { 500000, 12500, RK806_NLDO_ON_VSEL(1), RK806_NLDO_SLP_VSEL(1), NA, RK806_NLDO_VSEL_MASK, 0x00, 0xe7},
+ { 3400000, 0, RK806_NLDO_ON_VSEL(1), RK806_NLDO_SLP_VSEL(1), NA, RK806_NLDO_VSEL_MASK, 0xe8, 0xff},
+ /* nldo 2 */
+ { 500000, 12500, RK806_NLDO_ON_VSEL(2), RK806_NLDO_SLP_VSEL(2), NA, RK806_NLDO_VSEL_MASK, 0x00, 0xe7},
+ { 3400000, 0, RK806_NLDO_ON_VSEL(2), RK806_NLDO_SLP_VSEL(2), NA, RK806_NLDO_VSEL_MASK, 0xe8, 0xff},
+ /* nldo 3 */
+ { 500000, 12500, RK806_NLDO_ON_VSEL(3), RK806_NLDO_SLP_VSEL(3), NA, RK806_NLDO_VSEL_MASK, 0x00, 0xe7},
+ { 3400000, 0, RK806_NLDO_ON_VSEL(3), RK806_NLDO_SLP_VSEL(3), NA, RK806_NLDO_VSEL_MASK, 0xe8, 0xff},
+ /* nldo 4 */
+ { 500000, 12500, RK806_NLDO_ON_VSEL(4), RK806_NLDO_SLP_VSEL(4), NA, RK806_NLDO_VSEL_MASK, 0x00, 0xe7},
+ { 3400000, 0, RK806_NLDO_ON_VSEL(4), RK806_NLDO_SLP_VSEL(4), NA, RK806_NLDO_VSEL_MASK, 0xe8, 0xff},
+ /* nldo 5 */
+ { 500000, 12500, RK806_NLDO_ON_VSEL(5), RK806_NLDO_SLP_VSEL(5), NA, RK806_NLDO_VSEL_MASK, 0x00, 0xe7},
+ { 3400000, 0, RK806_NLDO_ON_VSEL(5), RK806_NLDO_SLP_VSEL(5), NA, RK806_NLDO_VSEL_MASK, 0xe8, 0xff},
+};
+
+static const struct rk8xx_reg_info rk806_pldo[] = {
+ /* pldo 1 */
+ { 500000, 12500, RK806_PLDO_ON_VSEL(1), RK806_PLDO_SLP_VSEL(1), NA, RK806_PLDO_VSEL_MASK, 0x00, 0xe7},
+ { 3400000, 0, RK806_PLDO_ON_VSEL(1), RK806_PLDO_SLP_VSEL(1), NA, RK806_PLDO_VSEL_MASK, 0xe8, 0xff},
+ /* pldo 2 */
+ { 500000, 12500, RK806_PLDO_ON_VSEL(2), RK806_PLDO_SLP_VSEL(2), NA, RK806_PLDO_VSEL_MASK, 0x00, 0xe7},
+ { 3400000, 0, RK806_PLDO_ON_VSEL(2), RK806_PLDO_SLP_VSEL(2), NA, RK806_PLDO_VSEL_MASK, 0xe8, 0xff},
+ /* pldo 3 */
+ { 500000, 12500, RK806_PLDO_ON_VSEL(3), RK806_PLDO_SLP_VSEL(3), NA, RK806_PLDO_VSEL_MASK, 0x00, 0xe7},
+ { 3400000, 0, RK806_PLDO_ON_VSEL(3), RK806_PLDO_SLP_VSEL(3), NA, RK806_PLDO_VSEL_MASK, 0xe8, 0xff},
+ /* pldo 4 */
+ { 500000, 12500, RK806_PLDO_ON_VSEL(4), RK806_PLDO_SLP_VSEL(4), NA, RK806_PLDO_VSEL_MASK, 0x00, 0xe7},
+ { 3400000, 0, RK806_PLDO_ON_VSEL(4), RK806_PLDO_SLP_VSEL(4), NA, RK806_PLDO_VSEL_MASK, 0xe8, 0xff},
+ /* pldo 5 */
+ { 500000, 12500, RK806_PLDO_ON_VSEL(5), RK806_PLDO_SLP_VSEL(5), NA, RK806_PLDO_VSEL_MASK, 0x00, 0xe7},
+ { 3400000, 0, RK806_PLDO_ON_VSEL(5), RK806_PLDO_SLP_VSEL(5), NA, RK806_PLDO_VSEL_MASK, 0xe8, 0xff},
+ /* pldo 6 */
+ { 500000, 12500, RK806_PLDO_ON_VSEL(6), RK806_PLDO_SLP_VSEL(6), NA, RK806_PLDO_VSEL_MASK, 0x00, 0xe7},
+ { 3400000, 0, RK806_PLDO_ON_VSEL(6), RK806_PLDO_SLP_VSEL(6), NA, RK806_PLDO_VSEL_MASK, 0xe8, 0xff},
+};
+
static const struct rk8xx_reg_info rk808_ldo[] = {
{ 1800000, 100000, REG_LDO1_ON_VSEL, REG_LDO1_SLP_VSEL, NA, RK808_LDO_VSEL_MASK, },
{ 1800000, 100000, REG_LDO2_ON_VSEL, REG_LDO2_SLP_VSEL, NA, RK808_LDO_VSEL_MASK, },
@@ -210,14 +305,6 @@
};
#endif
-static const u16 rk818_chrg_cur_input_array[] = {
- 450, 800, 850, 1000, 1250, 1500, 1750, 2000, 2250, 2500, 2750, 3000
-};
-
-static const uint rk818_chrg_shutdown_vsel_array[] = {
- 2780000, 2850000, 2920000, 2990000, 3060000, 3130000, 3190000, 3260000
-};
-
static const struct rk8xx_reg_info *get_buck_reg(struct udevice *pmic,
int num, int uvolt)
{
@@ -238,7 +325,12 @@
default:
return &rk816_buck[num + 4];
}
-
+ case RK806_ID:
+ if (uvolt < 1500000)
+ return &rk806_buck[num * 3 + 0];
+ else if (uvolt < 3400000)
+ return &rk806_buck[num * 3 + 1];
+ return &rk806_buck[num * 3 + 2];
case RK809_ID:
case RK817_ID:
switch (num) {
@@ -322,7 +414,11 @@
value = ((0 << buck) | (1 << (buck + 4)));
ret = pmic_reg_write(pmic, en_reg, value);
break;
-
+ case RK806_ID:
+ value = RK806_POWER_EN_CLRSETBITS(buck % 4, enable);
+ en_reg = RK806_POWER_EN((buck + 1) / 4);
+ ret = pmic_reg_write(pmic, en_reg, value);
+ break;
case RK808_ID:
case RK818_ID:
mask = 1 << buck;
@@ -397,6 +493,10 @@
ret = pmic_reg_read(pmic, RK816_REG_DCDC_EN1);
}
break;
+ case RK806_ID:
+ mask = BIT(buck % 4);
+ ret = pmic_reg_read(pmic, RK806_POWER_EN((buck + 1) / 4));
+ break;
case RK808_ID:
case RK818_ID:
mask = 1 << buck;
@@ -436,6 +536,20 @@
ret = pmic_clrsetbits(pmic, RK816_REG_DCDC_SLP_EN, mask,
enable ? mask : 0);
break;
+ case RK806_ID:
+ {
+ u8 reg;
+
+ if (buck + 1 >= 9) {
+ reg = RK806_POWER_SLP_EN1;
+ mask = BIT(buck + 1 - 3);
+ } else {
+ reg = RK806_POWER_SLP_EN0;
+ mask = BIT(buck + 1);
+ }
+ ret = pmic_clrsetbits(pmic, reg, mask, enable ? mask : 0);
+ }
+ break;
case RK808_ID:
case RK818_ID:
mask = 1 << buck;
@@ -473,6 +587,21 @@
return val;
ret = val & mask ? 1 : 0;
break;
+ case RK806_ID:
+ {
+ u8 reg;
+
+ if (buck + 1 >= 9) {
+ reg = RK806_POWER_SLP_EN1;
+ mask = BIT(buck + 1 - 3);
+ } else {
+ reg = RK806_POWER_SLP_EN0;
+ mask = BIT(buck + 1);
+ }
+ val = pmic_reg_read(pmic, reg);
+ }
+ ret = (val & mask) ? 1 : 0;
+ break;
case RK808_ID:
case RK818_ID:
mask = 1 << buck;
@@ -522,6 +651,34 @@
}
}
+static const struct rk8xx_reg_info *get_nldo_reg(struct udevice *pmic,
+ int num, int uvolt)
+{
+ const struct rk8xx_priv *priv = dev_get_priv(pmic);
+
+ switch (priv->variant) {
+ case RK806_ID:
+ default:
+ if (uvolt < 3400000)
+ return &rk806_nldo[num * 2 + 0];
+ return &rk806_nldo[num * 2 + 1];
+ }
+}
+
+static const struct rk8xx_reg_info *get_pldo_reg(struct udevice *pmic,
+ int num, int uvolt)
+{
+ const struct rk8xx_priv *priv = dev_get_priv(pmic);
+
+ switch (priv->variant) {
+ case RK806_ID:
+ default:
+ if (uvolt < 3400000)
+ return &rk806_pldo[num * 2 + 0];
+ return &rk806_pldo[num * 2 + 1];
+ }
+}
+
static int _ldo_get_enable(struct udevice *pmic, int ldo)
{
struct rk8xx_priv *priv = dev_get_priv(pmic);
@@ -569,6 +726,63 @@
return ret & mask ? true : false;
}
+static int _nldo_get_enable(struct udevice *pmic, int nldo)
+{
+ struct rk8xx_priv *priv = dev_get_priv(pmic);
+ uint mask = 0;
+ int ret = 0;
+ u8 en_reg = 0;
+
+ switch (priv->variant) {
+ case RK806_ID:
+ default:
+ if (nldo + 1 >= 5) {
+ mask = BIT(2);
+ en_reg = RK806_POWER_EN(5);
+ } else {
+ mask = BIT(nldo);
+ en_reg = RK806_POWER_EN(3);
+ }
+ ret = pmic_reg_read(pmic, en_reg);
+ break;
+ }
+
+ if (ret < 0)
+ return ret;
+
+ return (ret & mask) ? 1 : 0;
+}
+
+static int _pldo_get_enable(struct udevice *pmic, int pldo)
+{
+ struct rk8xx_priv *priv = dev_get_priv(pmic);
+ uint mask = 0;
+ int ret = 0;
+ u8 en_reg = 0;
+
+ switch (priv->variant) {
+ case RK806_ID:
+ default:
+ if (pldo + 1 <= 3) {
+ mask = BIT(pldo + 1);
+ en_reg = RK806_POWER_EN(4);
+ } else if (pldo + 1 == 6) {
+ mask = BIT(0);
+ en_reg = RK806_POWER_EN(4);
+ } else {
+ mask = BIT((pldo + 1) % 4);
+ en_reg = RK806_POWER_EN(5);
+ }
+ ret = pmic_reg_read(pmic, en_reg);
+ break;
+ }
+
+ if (ret < 0)
+ return ret;
+
+ return (ret & mask) ? 1 : 0;
+}
+
static int _ldo_set_enable(struct udevice *pmic, int ldo, bool enable)
{
struct rk8xx_priv *priv = dev_get_priv(pmic);
@@ -624,6 +838,62 @@
return ret;
}
+static int _nldo_set_enable(struct udevice *pmic, int nldo, bool enable)
+{
+ struct rk8xx_priv *priv = dev_get_priv(pmic);
+ uint value, en_reg;
+ int ret = 0;
+
+ switch (priv->variant) {
+ case RK806_ID:
+ default:
+ if (nldo + 1 >= 5) {
+ value = RK806_POWER_EN_CLRSETBITS(2, enable);
+ en_reg = RK806_POWER_EN(5);
+ } else {
+ value = RK806_POWER_EN_CLRSETBITS(nldo, enable);
+ en_reg = RK806_POWER_EN(3);
+ }
+ ret = pmic_reg_write(pmic, en_reg, value);
+ break;
+ }
+
+ if (enable)
+ udelay(500);
+
+ return ret;
+}
+
+static int _pldo_set_enable(struct udevice *pmic, int pldo, bool enable)
+{
+ struct rk8xx_priv *priv = dev_get_priv(pmic);
+ uint value, en_reg;
+ int ret = 0;
+
+ switch (priv->variant) {
+ case RK806_ID:
+ default:
+ /* PLDO */
+ if (pldo + 1 <= 3) {
+ value = RK806_POWER_EN_CLRSETBITS(pldo + 1, enable);
+ en_reg = RK806_POWER_EN(4);
+ } else if (pldo + 1 == 6) {
+ value = RK806_POWER_EN_CLRSETBITS(0, enable);
+ en_reg = RK806_POWER_EN(4);
+ } else {
+ value = RK806_POWER_EN_CLRSETBITS((pldo + 1) % 4, enable);
+ en_reg = RK806_POWER_EN(5);
+ }
+ ret = pmic_reg_write(pmic, en_reg, value);
+ break;
+ }
+
+ if (enable)
+ udelay(500);
+
+ return ret;
+}
+
static int _ldo_set_suspend_enable(struct udevice *pmic, int ldo, bool enable)
{
struct rk8xx_priv *priv = dev_get_priv(pmic);
@@ -660,6 +930,43 @@
return ret;
}
+static int _nldo_set_suspend_enable(struct udevice *pmic, int nldo, bool enable)
+{
+ struct rk8xx_priv *priv = dev_get_priv(pmic);
+ uint mask;
+ int ret = 0;
+
+ switch (priv->variant) {
+ case RK806_ID:
+ default:
+ mask = BIT(nldo);
+ ret = pmic_clrsetbits(pmic, RK806_POWER_SLP_EN1, mask, enable ? mask : 0);
+ break;
+ }
+
+ return ret;
+}
+
+static int _pldo_set_suspend_enable(struct udevice *pmic, int pldo, bool enable)
+{
+ struct rk8xx_priv *priv = dev_get_priv(pmic);
+ uint mask;
+ int ret = 0;
+
+ switch (priv->variant) {
+ case RK806_ID:
+ default:
+ if (pldo + 1 >= 6)
+ mask = BIT(0);
+ else
+ mask = BIT(pldo + 1);
+ ret = pmic_clrsetbits(pmic, RK806_POWER_SLP_EN2, mask, enable ? mask : 0);
+ break;
+ }
+
+ return ret;
+}
+
static int _ldo_get_suspend_enable(struct udevice *pmic, int ldo)
{
struct rk8xx_priv *priv = dev_get_priv(pmic);
@@ -704,6 +1011,45 @@
return ret;
}
+static int _nldo_get_suspend_enable(struct udevice *pmic, int nldo)
+{
+ struct rk8xx_priv *priv = dev_get_priv(pmic);
+ int val, ret = 0;
+ uint mask;
+
+ switch (priv->variant) {
+ case RK806_ID:
+ default:
+ mask = BIT(nldo);
+ val = pmic_reg_read(pmic, RK806_POWER_SLP_EN1);
+ ret = (val & mask) ? 1 : 0;
+ break;
+ }
+
+ return ret;
+}
+
+static int _pldo_get_suspend_enable(struct udevice *pmic, int pldo)
+{
+ struct rk8xx_priv *priv = dev_get_priv(pmic);
+ int val, ret = 0;
+ uint mask;
+
+ switch (priv->variant) {
+ case RK806_ID:
+ default:
+ if (pldo + 1 >= 6)
+ mask = BIT(0);
+ else
+ mask = BIT(pldo + 1);
+ val = pmic_reg_read(pmic, RK806_POWER_SLP_EN2);
+ ret = (val & mask) ? 1 : 0;
+ break;
+ }
+
+ return ret;
+}
+
static int buck_get_value(struct udevice *dev)
{
int buck = dev->driver_data - 1;
@@ -788,10 +1134,8 @@
return _buck_get_enable(dev->parent, buck);
}
-static int ldo_get_value(struct udevice *dev)
+static int _ldo_get_value(struct udevice *dev, const struct rk8xx_reg_info *info)
{
- int ldo = dev->driver_data - 1;
- const struct rk8xx_reg_info *info = get_ldo_reg(dev->parent, ldo, 0);
int mask = info->vsel_mask;
int ret, val;
@@ -805,10 +1149,32 @@
return info->min_uv + val * info->step_uv;
}
-static int ldo_set_value(struct udevice *dev, int uvolt)
+static int ldo_get_value(struct udevice *dev)
{
int ldo = dev->driver_data - 1;
- const struct rk8xx_reg_info *info = get_ldo_reg(dev->parent, ldo, uvolt);
+ const struct rk8xx_reg_info *info = get_ldo_reg(dev->parent, ldo, 0);
+
+ return _ldo_get_value(dev, info);
+}
+
+static int nldo_get_value(struct udevice *dev)
+{
+ int nldo = dev->driver_data - 1;
+ const struct rk8xx_reg_info *info = get_nldo_reg(dev->parent, nldo, 0);
+
+ return _ldo_get_value(dev, info);
+}
+
+static int pldo_get_value(struct udevice *dev)
+{
+ int pldo = dev->driver_data - 1;
+ const struct rk8xx_reg_info *info = get_pldo_reg(dev->parent, pldo, 0);
+
+ return _ldo_get_value(dev, info);
+}
+
+static int _ldo_set_value(struct udevice *dev, const struct rk8xx_reg_info *info, int uvolt)
+{
int mask = info->vsel_mask;
int val;
@@ -820,16 +1186,38 @@
else
val = ((uvolt - info->min_uv) / info->step_uv) + info->min_sel;
- debug("%s: volt=%d, ldo=%d, reg=0x%x, mask=0x%x, val=0x%x\n",
- __func__, uvolt, ldo + 1, info->vsel_reg, mask, val);
+ debug("%s: volt=%d, reg=0x%x, mask=0x%x, val=0x%x\n",
+ __func__, uvolt, info->vsel_reg, mask, val);
return pmic_clrsetbits(dev->parent, info->vsel_reg, mask, val);
}
-static int ldo_set_suspend_value(struct udevice *dev, int uvolt)
+static int ldo_set_value(struct udevice *dev, int uvolt)
{
int ldo = dev->driver_data - 1;
const struct rk8xx_reg_info *info = get_ldo_reg(dev->parent, ldo, uvolt);
+
+ return _ldo_set_value(dev, info, uvolt);
+}
+
+static int nldo_set_value(struct udevice *dev, int uvolt)
+{
+ int nldo = dev->driver_data - 1;
+ const struct rk8xx_reg_info *info = get_nldo_reg(dev->parent, nldo, uvolt);
+
+ return _ldo_set_value(dev, info, uvolt);
+}
+
+static int pldo_set_value(struct udevice *dev, int uvolt)
+{
+ int pldo = dev->driver_data - 1;
+ const struct rk8xx_reg_info *info = get_pldo_reg(dev->parent, pldo, uvolt);
+
+ return _ldo_set_value(dev, info, uvolt);
+}
+
+static int _ldo_set_suspend_value(struct udevice *dev, const struct rk8xx_reg_info *info, int uvolt)
+{
int mask = info->vsel_mask;
int val;
@@ -841,16 +1229,38 @@
else
val = ((uvolt - info->min_uv) / info->step_uv) + info->min_sel;
- debug("%s: volt=%d, ldo=%d, reg=0x%x, mask=0x%x, val=0x%x\n",
- __func__, uvolt, ldo + 1, info->vsel_sleep_reg, mask, val);
+ debug("%s: volt=%d, reg=0x%x, mask=0x%x, val=0x%x\n",
+ __func__, uvolt, info->vsel_sleep_reg, mask, val);
return pmic_clrsetbits(dev->parent, info->vsel_sleep_reg, mask, val);
}
-static int ldo_get_suspend_value(struct udevice *dev)
+static int ldo_set_suspend_value(struct udevice *dev, int uvolt)
{
int ldo = dev->driver_data - 1;
- const struct rk8xx_reg_info *info = get_ldo_reg(dev->parent, ldo, 0);
+ const struct rk8xx_reg_info *info = get_ldo_reg(dev->parent, ldo, uvolt);
+
+ return _ldo_set_suspend_value(dev->parent, info, uvolt);
+}
+
+static int nldo_set_suspend_value(struct udevice *dev, int uvolt)
+{
+ int nldo = dev->driver_data - 1;
+ const struct rk8xx_reg_info *info = get_nldo_reg(dev->parent, nldo, uvolt);
+
+ return _ldo_set_suspend_value(dev->parent, info, uvolt);
+}
+
+static int pldo_set_suspend_value(struct udevice *dev, int uvolt)
+{
+ int pldo = dev->driver_data - 1;
+ const struct rk8xx_reg_info *info = get_pldo_reg(dev->parent, pldo, uvolt);
+
+ return _ldo_set_suspend_value(dev->parent, info, uvolt);
+}
+
+static int _ldo_get_suspend_value(struct udevice *dev, const struct rk8xx_reg_info *info)
+{
int mask = info->vsel_mask;
int val, ret;
@@ -866,6 +1276,30 @@
return info->min_uv + val * info->step_uv;
}
+static int ldo_get_suspend_value(struct udevice *dev)
+{
+ int ldo = dev->driver_data - 1;
+ const struct rk8xx_reg_info *info = get_ldo_reg(dev->parent, ldo, 0);
+
+ return _ldo_get_suspend_value(dev->parent, info);
+}
+
+static int nldo_get_suspend_value(struct udevice *dev)
+{
+ int nldo = dev->driver_data - 1;
+ const struct rk8xx_reg_info *info = get_nldo_reg(dev->parent, nldo, 0);
+
+ return _ldo_get_suspend_value(dev->parent, info);
+}
+
+static int pldo_get_suspend_value(struct udevice *dev)
+{
+ int pldo = dev->driver_data - 1;
+ const struct rk8xx_reg_info *info = get_pldo_reg(dev->parent, pldo, 0);
+
+ return _ldo_get_suspend_value(dev->parent, info);
+}
+
static int ldo_set_enable(struct udevice *dev, bool enable)
{
int ldo = dev->driver_data - 1;
@@ -873,6 +1307,20 @@
return _ldo_set_enable(dev->parent, ldo, enable);
}
+static int nldo_set_enable(struct udevice *dev, bool enable)
+{
+ int nldo = dev->driver_data - 1;
+
+ return _nldo_set_enable(dev->parent, nldo, enable);
+}
+
+static int pldo_set_enable(struct udevice *dev, bool enable)
+{
+ int pldo = dev->driver_data - 1;
+
+ return _pldo_set_enable(dev->parent, pldo, enable);
+}
+
static int ldo_set_suspend_enable(struct udevice *dev, bool enable)
{
int ldo = dev->driver_data - 1;
@@ -880,6 +1328,20 @@
return _ldo_set_suspend_enable(dev->parent, ldo, enable);
}
+static int nldo_set_suspend_enable(struct udevice *dev, bool enable)
+{
+ int nldo = dev->driver_data - 1;
+
+ return _nldo_set_suspend_enable(dev->parent, nldo, enable);
+}
+
+static int pldo_set_suspend_enable(struct udevice *dev, bool enable)
+{
+ int pldo = dev->driver_data - 1;
+
+ return _pldo_set_suspend_enable(dev->parent, pldo, enable);
+}
+
static int ldo_get_suspend_enable(struct udevice *dev)
{
int ldo = dev->driver_data - 1;
@@ -887,6 +1349,20 @@
return _ldo_get_suspend_enable(dev->parent, ldo);
}
+static int nldo_get_suspend_enable(struct udevice *dev)
+{
+ int nldo = dev->driver_data - 1;
+
+ return _nldo_get_suspend_enable(dev->parent, nldo);
+}
+
+static int pldo_get_suspend_enable(struct udevice *dev)
+{
+ int pldo = dev->driver_data - 1;
+
+ return _pldo_get_suspend_enable(dev->parent, pldo);
+}
+
static int ldo_get_enable(struct udevice *dev)
{
int ldo = dev->driver_data - 1;
@@ -894,6 +1370,20 @@
return _ldo_get_enable(dev->parent, ldo);
}
+static int nldo_get_enable(struct udevice *dev)
+{
+ int nldo = dev->driver_data - 1;
+
+ return _nldo_get_enable(dev->parent, nldo);
+}
+
+static int pldo_get_enable(struct udevice *dev)
+{
+ int pldo = dev->driver_data - 1;
+
+ return _pldo_get_enable(dev->parent, pldo);
+}
+
static int switch_set_enable(struct udevice *dev, bool enable)
{
struct rk8xx_priv *priv = dev_get_priv(dev->parent);
@@ -909,7 +1399,7 @@
case RK809_ID:
mask = (1 << (sw + 2)) | (1 << (sw + 6));
ret = pmic_clrsetbits(dev->parent, RK817_POWER_EN(3), mask,
- enable ? mask : 0);
+ enable ? mask : (1 << (sw + 6)));
break;
case RK818_ID:
mask = 1 << 6;
@@ -1117,6 +1607,28 @@
.get_suspend_enable = ldo_get_suspend_enable,
};
+static const struct dm_regulator_ops rk8xx_nldo_ops = {
+ .get_value = nldo_get_value,
+ .set_value = nldo_set_value,
+ .set_suspend_value = nldo_set_suspend_value,
+ .get_suspend_value = nldo_get_suspend_value,
+ .get_enable = nldo_get_enable,
+ .set_enable = nldo_set_enable,
+ .set_suspend_enable = nldo_set_suspend_enable,
+ .get_suspend_enable = nldo_get_suspend_enable,
+};
+
+static const struct dm_regulator_ops rk8xx_pldo_ops = {
+ .get_value = pldo_get_value,
+ .set_value = pldo_set_value,
+ .set_suspend_value = pldo_set_suspend_value,
+ .get_suspend_value = pldo_get_suspend_value,
+ .get_enable = pldo_get_enable,
+ .set_enable = pldo_set_enable,
+ .set_suspend_enable = pldo_set_suspend_enable,
+ .get_suspend_enable = pldo_get_suspend_enable,
+};
+
static const struct dm_regulator_ops rk8xx_switch_ops = {
.get_value = switch_get_value,
.set_value = switch_set_value,
@@ -1142,6 +1654,20 @@
.probe = rk8xx_ldo_probe,
};
+U_BOOT_DRIVER(rk8xx_nldo) = {
+ .name = "rk8xx_nldo",
+ .id = UCLASS_REGULATOR,
+ .ops = &rk8xx_nldo_ops,
+ .probe = rk8xx_ldo_probe,
+};
+
+U_BOOT_DRIVER(rk8xx_pldo) = {
+ .name = "rk8xx_pldo",
+ .id = UCLASS_REGULATOR,
+ .ops = &rk8xx_pldo_ops,
+ .probe = rk8xx_ldo_probe,
+};
+
U_BOOT_DRIVER(rk8xx_switch) = {
.name = "rk8xx_switch",
.id = UCLASS_REGULATOR,
@@ -1160,26 +1686,3 @@
return _buck_set_enable(pmic, buck, true);
}
-
-int rk818_spl_configure_usb_input_current(struct udevice *pmic, int current_ma)
-{
- uint i;
-
- for (i = 0; i < ARRAY_SIZE(rk818_chrg_cur_input_array); i++)
- if (current_ma <= rk818_chrg_cur_input_array[i])
- break;
-
- return pmic_clrsetbits(pmic, REG_USB_CTRL, RK818_USB_ILIM_SEL_MASK, i);
-}
-
-int rk818_spl_configure_usb_chrg_shutdown(struct udevice *pmic, int uvolt)
-{
- uint i;
-
- for (i = 0; i < ARRAY_SIZE(rk818_chrg_shutdown_vsel_array); i++)
- if (uvolt <= rk818_chrg_shutdown_vsel_array[i])
- break;
-
- return pmic_clrsetbits(pmic, REG_USB_CTRL, RK818_USB_CHG_SD_VSEL_MASK,
- i);
-}
diff --git a/drivers/ram/rockchip/dmc-rk3368.c b/drivers/ram/rockchip/dmc-rk3368.c
index f36be94..5279bf0 100644
--- a/drivers/ram/rockchip/dmc-rk3368.c
+++ b/drivers/ram/rockchip/dmc-rk3368.c
@@ -13,10 +13,10 @@
#include <ram.h>
#include <regmap.h>
#include <syscon.h>
-#include <asm/io.h>
#include <asm/arch-rockchip/clock.h>
#include <asm/arch-rockchip/cru_rk3368.h>
#include <asm/arch-rockchip/grf_rk3368.h>
+#include <asm/arch-rockchip/hardware.h>
#include <asm/arch-rockchip/ddr_rk3368.h>
#include <asm/arch-rockchip/sdram.h>
#include <asm/arch-rockchip/sdram_rk3288.h>
diff --git a/drivers/ram/rockchip/sdram_px30.c b/drivers/ram/rockchip/sdram_px30.c
index 2728d93..21498e8 100644
--- a/drivers/ram/rockchip/sdram_px30.c
+++ b/drivers/ram/rockchip/sdram_px30.c
@@ -10,7 +10,6 @@
#include <log.h>
#include <ram.h>
#include <syscon.h>
-#include <asm/io.h>
#include <asm/arch-rockchip/clock.h>
#include <asm/arch-rockchip/cru_px30.h>
#include <asm/arch-rockchip/grf_px30.h>
diff --git a/drivers/ram/rockchip/sdram_rk3066.c b/drivers/ram/rockchip/sdram_rk3066.c
index 39c0be5..562cf54 100644
--- a/drivers/ram/rockchip/sdram_rk3066.c
+++ b/drivers/ram/rockchip/sdram_rk3066.c
@@ -17,7 +17,6 @@
#include <ram.h>
#include <regmap.h>
#include <syscon.h>
-#include <asm/io.h>
#include <asm/arch-rockchip/clock.h>
#include <asm/arch-rockchip/cru_rk3066.h>
#include <asm/arch-rockchip/ddr_rk3188.h>
diff --git a/drivers/ram/rockchip/sdram_rk3188.c b/drivers/ram/rockchip/sdram_rk3188.c
index ad9f936..e1b28c6 100644
--- a/drivers/ram/rockchip/sdram_rk3188.c
+++ b/drivers/ram/rockchip/sdram_rk3188.c
@@ -17,11 +17,11 @@
#include <ram.h>
#include <regmap.h>
#include <syscon.h>
-#include <asm/io.h>
#include <asm/arch-rockchip/clock.h>
#include <asm/arch-rockchip/cru_rk3188.h>
#include <asm/arch-rockchip/ddr_rk3188.h>
#include <asm/arch-rockchip/grf_rk3188.h>
+#include <asm/arch-rockchip/hardware.h>
#include <asm/arch-rockchip/pmu_rk3188.h>
#include <asm/arch-rockchip/sdram.h>
#include <asm/arch-rockchip/sdram_rk3288.h>
diff --git a/drivers/ram/rockchip/sdram_rk322x.c b/drivers/ram/rockchip/sdram_rk322x.c
index 892766a..5fc23c1 100644
--- a/drivers/ram/rockchip/sdram_rk322x.c
+++ b/drivers/ram/rockchip/sdram_rk322x.c
@@ -12,7 +12,6 @@
#include <regmap.h>
#include <syscon.h>
#include <asm/global_data.h>
-#include <asm/io.h>
#include <asm/arch-rockchip/clock.h>
#include <asm/arch-rockchip/cru_rk322x.h>
#include <asm/arch-rockchip/grf_rk322x.h>
diff --git a/drivers/ram/rockchip/sdram_rk3288.c b/drivers/ram/rockchip/sdram_rk3288.c
index c99118f..242d564 100644
--- a/drivers/ram/rockchip/sdram_rk3288.c
+++ b/drivers/ram/rockchip/sdram_rk3288.c
@@ -17,11 +17,11 @@
#include <ram.h>
#include <regmap.h>
#include <syscon.h>
-#include <asm/io.h>
#include <asm/arch-rockchip/clock.h>
#include <asm/arch-rockchip/cru.h>
#include <asm/arch-rockchip/ddr_rk3288.h>
#include <asm/arch-rockchip/grf_rk3288.h>
+#include <asm/arch-rockchip/hardware.h>
#include <asm/arch-rockchip/pmu_rk3288.h>
#include <asm/arch-rockchip/sdram.h>
#include <asm/arch-rockchip/sdram_rk3288.h>
diff --git a/drivers/ram/rockchip/sdram_rk3399.c b/drivers/ram/rockchip/sdram_rk3399.c
index 2bf8d48..02cc4a3 100644
--- a/drivers/ram/rockchip/sdram_rk3399.c
+++ b/drivers/ram/rockchip/sdram_rk3399.c
@@ -14,7 +14,6 @@
#include <ram.h>
#include <regmap.h>
#include <syscon.h>
-#include <asm/io.h>
#include <asm/arch-rockchip/clock.h>
#include <asm/arch-rockchip/cru.h>
#include <asm/arch-rockchip/grf_rk3399.h>
diff --git a/drivers/ram/rockchip/sdram_rv1126.c b/drivers/ram/rockchip/sdram_rv1126.c
index 0a78e18..849e15a 100644
--- a/drivers/ram/rockchip/sdram_rv1126.c
+++ b/drivers/ram/rockchip/sdram_rv1126.c
@@ -9,7 +9,6 @@
#include <dm.h>
#include <ram.h>
#include <syscon.h>
-#include <asm/io.h>
#include <asm/arch-rockchip/clock.h>
#include <asm/arch-rockchip/hardware.h>
#include <asm/arch-rockchip/cru_rv1126.h>
diff --git a/drivers/remoteproc/Kconfig b/drivers/remoteproc/Kconfig
index 781de53..a49802c 100644
--- a/drivers/remoteproc/Kconfig
+++ b/drivers/remoteproc/Kconfig
@@ -102,4 +102,11 @@
help
Say 'y' here to add support for TI' K3 remoteproc driver.
+config REMOTEPROC_MAX_FW_SIZE
+ hex "Maximum size of firmware file that needs to be loaded to the remote processor"
+ default 0x10000
+ help
+ Maximum size of the firmware file (elf, binary) that needs to be
+ loaded to the remote processor.
+
endmenu
diff --git a/drivers/remoteproc/rproc-uclass.c b/drivers/remoteproc/rproc-uclass.c
index 28b362c..aa7f758 100644
--- a/drivers/remoteproc/rproc-uclass.c
+++ b/drivers/remoteproc/rproc-uclass.c
@@ -13,6 +13,7 @@
#include <log.h>
#include <malloc.h>
#include <virtio_ring.h>
+#include <fs_loader.h>
#include <remoteproc.h>
#include <asm/io.h>
#include <dm/device-internal.h>
@@ -961,3 +962,106 @@
return 1;
}
+
+int rproc_set_firmware(struct udevice *rproc_dev, const char *fw_name)
+{
+ struct dm_rproc_uclass_pdata *uc_pdata;
+ int len;
+ char *p;
+
+ if (!rproc_dev || !fw_name)
+ return -EINVAL;
+
+ uc_pdata = dev_get_uclass_plat(rproc_dev);
+ if (!uc_pdata)
+ return -EINVAL;
+
+ len = strcspn(fw_name, "\n");
+ if (!len) {
+ debug("invalid firmware name\n");
+ return -EINVAL;
+ }
+
+ if (uc_pdata->fw_name)
+ free(uc_pdata->fw_name);
+
+ p = strndup(fw_name, len);
+ if (!p)
+ return -ENOMEM;
+
+ uc_pdata->fw_name = p;
+
+ return 0;
+}
+
+#if CONFIG_IS_ENABLED(FS_LOADER)
+int rproc_boot(struct udevice *rproc_dev)
+{
+ struct dm_rproc_uclass_pdata *uc_pdata;
+ struct udevice *fs_loader;
+ int core_id, ret = 0;
+ char *firmware;
+ void *addr;
+
+ if (!rproc_dev)
+ return -EINVAL;
+
+ uc_pdata = dev_get_uclass_plat(rproc_dev);
+ if (!uc_pdata)
+ return -EINVAL;
+
+ core_id = dev_seq(rproc_dev);
+ firmware = uc_pdata->fw_name;
+ if (!firmware) {
+ debug("No firmware name set for rproc core %d\n", core_id);
+ return -EINVAL;
+ }
+
+ /* Initialize all rproc cores */
+ if (!rproc_is_initialized()) {
+ ret = rproc_init();
+ if (ret) {
+ debug("rproc_init() failed: %d\n", ret);
+ return ret;
+ }
+ }
+
+ /* Loading firmware to a given address */
+ ret = get_fs_loader(&fs_loader);
+ if (ret) {
+ debug("could not get fs loader: %d\n", ret);
+ return ret;
+ }
+
+ if (CONFIG_REMOTEPROC_MAX_FW_SIZE) {
+ addr = malloc(CONFIG_REMOTEPROC_MAX_FW_SIZE);
+ if (!addr)
+ return -ENOMEM;
+ } else {
+ debug("CONFIG_REMOTEPROC_MAX_FW_SIZE not defined\n");
+ return -EINVAL;
+ }
+
+ ret = request_firmware_into_buf(fs_loader, firmware, addr, CONFIG_REMOTEPROC_MAX_FW_SIZE,
+ 0);
+ if (ret < 0) {
+ debug("could not request %s: %d\n", firmware, ret);
+ goto free_buffer;
+ }
+
+ ret = rproc_load(core_id, (ulong)addr, ret);
+ if (ret) {
+ debug("failed to load %s to rproc core %d from addr 0x%08lX err %d\n",
+ uc_pdata->fw_name, core_id, (ulong)addr, ret);
+ goto free_buffer;
+ }
+
+ ret = rproc_start(core_id);
+ if (ret)
+ debug("failed to start rproc core %d\n", core_id);
+
+free_buffer:
+ free(addr);
+ return ret;
+}
+#endif
diff --git a/drivers/remoteproc/ti_k3_dsp_rproc.c b/drivers/remoteproc/ti_k3_dsp_rproc.c
index 1c6515f..e790406 100644
--- a/drivers/remoteproc/ti_k3_dsp_rproc.c
+++ b/drivers/remoteproc/ti_k3_dsp_rproc.c
@@ -338,7 +338,8 @@
for (i = 0; i < dsp->num_mems; i++) {
/* C71 cores only have a L1P Cache, there are no L1P SRAMs */
- if (device_is_compatible(dev, "ti,j721e-c71-dsp") &&
+ if (((device_is_compatible(dev, "ti,j721e-c71-dsp")) ||
+ (device_is_compatible(dev, "ti,j721s2-c71-dsp"))) &&
!strcmp(mem_names[i], "l1pram")) {
dsp->mem[i].bus_addr = FDT_ADDR_T_NONE;
dsp->mem[i].dev_addr = FDT_ADDR_T_NONE;
@@ -457,6 +458,7 @@
static const struct udevice_id k3_dsp_ids[] = {
{ .compatible = "ti,j721e-c66-dsp", .data = (ulong)&c66_data, },
{ .compatible = "ti,j721e-c71-dsp", .data = (ulong)&c71_data, },
+ { .compatible = "ti,j721s2-c71-dsp", .data = (ulong)&c71_data, },
{}
};
diff --git a/drivers/remoteproc/ti_k3_r5f_rproc.c b/drivers/remoteproc/ti_k3_r5f_rproc.c
index 6f3e12d..631e548 100644
--- a/drivers/remoteproc/ti_k3_r5f_rproc.c
+++ b/drivers/remoteproc/ti_k3_r5f_rproc.c
@@ -855,7 +855,7 @@
.tcm_ecc_autoinit = false,
};
-static const struct k3_r5f_ip_data j7200_data = {
+static const struct k3_r5f_ip_data j7200_j721s2_data = {
.tcm_is_double = true,
.tcm_ecc_autoinit = true,
};
@@ -863,7 +863,8 @@
static const struct udevice_id k3_r5f_rproc_ids[] = {
{ .compatible = "ti,am654-r5f", .data = (ulong)&k3_data, },
{ .compatible = "ti,j721e-r5f", .data = (ulong)&k3_data, },
- { .compatible = "ti,j7200-r5f", .data = (ulong)&j7200_data, },
+ { .compatible = "ti,j7200-r5f", .data = (ulong)&j7200_j721s2_data, },
+ { .compatible = "ti,j721s2-r5f", .data = (ulong)&j7200_j721s2_data, },
{}
};
@@ -901,6 +902,7 @@
{ .compatible = "ti,am654-r5fss"},
{ .compatible = "ti,j721e-r5fss"},
{ .compatible = "ti,j7200-r5fss"},
+ { .compatible = "ti,j721s2-r5fss"},
{}
};
diff --git a/drivers/reset/reset-imx7.c b/drivers/reset/reset-imx7.c
index eaef2cc..a3b3132 100644
--- a/drivers/reset/reset-imx7.c
+++ b/drivers/reset/reset-imx7.c
@@ -9,12 +9,13 @@
#include <common.h>
#include <dm.h>
#include <dt-bindings/reset/imx7-reset.h>
+#include <dt-bindings/reset/imx8mp-reset.h>
#include <dt-bindings/reset/imx8mq-reset.h>
#include <reset-uclass.h>
#include <linux/bitops.h>
#include <linux/delay.h>
-struct imx7_reset_priv {
+struct imx_reset_priv {
void __iomem *base;
struct reset_ops ops;
};
@@ -64,9 +65,9 @@
[IMX7_RESET_DDRC_CORE_RST] = { SRC_DDRC_RCR, BIT(1) },
};
-static int imx7_reset_deassert_imx7(struct reset_ctl *rst)
+static int imx7_reset_deassert(struct reset_ctl *rst)
{
- struct imx7_reset_priv *priv = dev_get_priv(rst->dev);
+ struct imx_reset_priv *priv = dev_get_priv(rst->dev);
const struct imx7_src_signal *sig = imx7_src_signals;
u32 val;
@@ -95,9 +96,9 @@
return 0;
}
-static int imx7_reset_assert_imx7(struct reset_ctl *rst)
+static int imx7_reset_assert(struct reset_ctl *rst)
{
- struct imx7_reset_priv *priv = dev_get_priv(rst->dev);
+ struct imx_reset_priv *priv = dev_get_priv(rst->dev);
const struct imx7_src_signal *sig = imx7_src_signals;
u32 val;
@@ -185,9 +186,9 @@
[IMX8MQ_RESET_DDRC2_PRST] = { SRC_DDRC2_RCR, BIT(2) },
};
-static int imx7_reset_deassert_imx8mq(struct reset_ctl *rst)
+static int imx8mq_reset_deassert(struct reset_ctl *rst)
{
- struct imx7_reset_priv *priv = dev_get_priv(rst->dev);
+ struct imx_reset_priv *priv = dev_get_priv(rst->dev);
const struct imx7_src_signal *sig = imx8mq_src_signals;
u32 val;
@@ -223,9 +224,9 @@
return 0;
}
-static int imx7_reset_assert_imx8mq(struct reset_ctl *rst)
+static int imx8mq_reset_assert(struct reset_ctl *rst)
{
- struct imx7_reset_priv *priv = dev_get_priv(rst->dev);
+ struct imx_reset_priv *priv = dev_get_priv(rst->dev);
const struct imx7_src_signal *sig = imx8mq_src_signals;
u32 val;
@@ -252,43 +253,143 @@
return 0;
}
-static int imx7_reset_assert(struct reset_ctl *rst)
+enum imx8mp_src_registers {
+ SRC_SUPERMIX_RCR = 0x0018,
+ SRC_AUDIOMIX_RCR = 0x001c,
+ SRC_MLMIX_RCR = 0x0028,
+ SRC_GPU2D_RCR = 0x0038,
+ SRC_GPU3D_RCR = 0x003c,
+ SRC_VPU_G1_RCR = 0x0048,
+ SRC_VPU_G2_RCR = 0x004c,
+ SRC_VPUVC8KE_RCR = 0x0050,
+ SRC_NOC_RCR = 0x0054,
+};
+
+static const struct imx7_src_signal imx8mp_src_signals[IMX8MP_RESET_NUM] = {
+ [IMX8MP_RESET_A53_CORE_POR_RESET0] = { SRC_A53RCR0, BIT(0) },
+ [IMX8MP_RESET_A53_CORE_POR_RESET1] = { SRC_A53RCR0, BIT(1) },
+ [IMX8MP_RESET_A53_CORE_POR_RESET2] = { SRC_A53RCR0, BIT(2) },
+ [IMX8MP_RESET_A53_CORE_POR_RESET3] = { SRC_A53RCR0, BIT(3) },
+ [IMX8MP_RESET_A53_CORE_RESET0] = { SRC_A53RCR0, BIT(4) },
+ [IMX8MP_RESET_A53_CORE_RESET1] = { SRC_A53RCR0, BIT(5) },
+ [IMX8MP_RESET_A53_CORE_RESET2] = { SRC_A53RCR0, BIT(6) },
+ [IMX8MP_RESET_A53_CORE_RESET3] = { SRC_A53RCR0, BIT(7) },
+ [IMX8MP_RESET_A53_DBG_RESET0] = { SRC_A53RCR0, BIT(8) },
+ [IMX8MP_RESET_A53_DBG_RESET1] = { SRC_A53RCR0, BIT(9) },
+ [IMX8MP_RESET_A53_DBG_RESET2] = { SRC_A53RCR0, BIT(10) },
+ [IMX8MP_RESET_A53_DBG_RESET3] = { SRC_A53RCR0, BIT(11) },
+ [IMX8MP_RESET_A53_ETM_RESET0] = { SRC_A53RCR0, BIT(12) },
+ [IMX8MP_RESET_A53_ETM_RESET1] = { SRC_A53RCR0, BIT(13) },
+ [IMX8MP_RESET_A53_ETM_RESET2] = { SRC_A53RCR0, BIT(14) },
+ [IMX8MP_RESET_A53_ETM_RESET3] = { SRC_A53RCR0, BIT(15) },
+ [IMX8MP_RESET_A53_SOC_DBG_RESET] = { SRC_A53RCR0, BIT(20) },
+ [IMX8MP_RESET_A53_L2RESET] = { SRC_A53RCR0, BIT(21) },
+ [IMX8MP_RESET_SW_NON_SCLR_M7C_RST] = { SRC_M4RCR, BIT(0) },
+ [IMX8MP_RESET_OTG1_PHY_RESET] = { SRC_USBOPHY1_RCR, BIT(0) },
+ [IMX8MP_RESET_OTG2_PHY_RESET] = { SRC_USBOPHY2_RCR, BIT(0) },
+ [IMX8MP_RESET_SUPERMIX_RESET] = { SRC_SUPERMIX_RCR, BIT(0) },
+ [IMX8MP_RESET_AUDIOMIX_RESET] = { SRC_AUDIOMIX_RCR, BIT(0) },
+ [IMX8MP_RESET_MLMIX_RESET] = { SRC_MLMIX_RCR, BIT(0) },
+ [IMX8MP_RESET_PCIEPHY] = { SRC_PCIEPHY_RCR, BIT(2) },
+ [IMX8MP_RESET_PCIEPHY_PERST] = { SRC_PCIEPHY_RCR, BIT(3) },
+ [IMX8MP_RESET_PCIE_CTRL_APPS_EN] = { SRC_PCIEPHY_RCR, BIT(6) },
+ [IMX8MP_RESET_PCIE_CTRL_APPS_TURNOFF] = { SRC_PCIEPHY_RCR, BIT(11) },
+ [IMX8MP_RESET_HDMI_PHY_APB_RESET] = { SRC_HDMI_RCR, BIT(0) },
+ [IMX8MP_RESET_MEDIA_RESET] = { SRC_DISP_RCR, BIT(0) },
+ [IMX8MP_RESET_GPU2D_RESET] = { SRC_GPU2D_RCR, BIT(0) },
+ [IMX8MP_RESET_GPU3D_RESET] = { SRC_GPU3D_RCR, BIT(0) },
+ [IMX8MP_RESET_GPU_RESET] = { SRC_GPU_RCR, BIT(0) },
+ [IMX8MP_RESET_VPU_RESET] = { SRC_VPU_RCR, BIT(0) },
+ [IMX8MP_RESET_VPU_G1_RESET] = { SRC_VPU_G1_RCR, BIT(0) },
+ [IMX8MP_RESET_VPU_G2_RESET] = { SRC_VPU_G2_RCR, BIT(0) },
+ [IMX8MP_RESET_VPUVC8KE_RESET] = { SRC_VPUVC8KE_RCR, BIT(0) },
+ [IMX8MP_RESET_NOC_RESET] = { SRC_NOC_RCR, BIT(0) },
+};
+
+static int imx8mp_reset_set(struct reset_ctl *rst, bool assert)
{
- struct imx7_reset_priv *priv = dev_get_priv(rst->dev);
+ struct imx_reset_priv *priv = dev_get_priv(rst->dev);
+ unsigned int bit, value;
+
+ if (rst->id >= IMX8MP_RESET_NUM)
+ return -EINVAL;
+
+ bit = imx8mp_src_signals[rst->id].bit;
+ value = assert ? bit : 0;
+
+ switch (rst->id) {
+ case IMX8MP_RESET_PCIEPHY:
+ /*
+ * wait for more than 10us to release phy g_rst and
+ * btnrst
+ */
+ if (!assert)
+ udelay(10);
+ break;
+
+ case IMX8MP_RESET_PCIE_CTRL_APPS_EN:
+ case IMX8MP_RESET_PCIEPHY_PERST:
+ value = assert ? 0 : bit;
+ break;
+ }
+
+ clrsetbits_le32(priv->base + imx8mp_src_signals[rst->id].offset, bit,
+ value);
+
+ return 0;
+}
+
+static int imx8mp_reset_assert(struct reset_ctl *rst)
+{
+ return imx8mp_reset_set(rst, true);
+}
+
+static int imx8mp_reset_deassert(struct reset_ctl *rst)
+{
+ return imx8mp_reset_set(rst, false);
+}
+
+static int imx_reset_assert(struct reset_ctl *rst)
+{
+ struct imx_reset_priv *priv = dev_get_priv(rst->dev);
return priv->ops.rst_assert(rst);
}
-static int imx7_reset_deassert(struct reset_ctl *rst)
+static int imx_reset_deassert(struct reset_ctl *rst)
{
- struct imx7_reset_priv *priv = dev_get_priv(rst->dev);
+ struct imx_reset_priv *priv = dev_get_priv(rst->dev);
return priv->ops.rst_deassert(rst);
}
static const struct reset_ops imx7_reset_reset_ops = {
- .rst_assert = imx7_reset_assert,
- .rst_deassert = imx7_reset_deassert,
+ .rst_assert = imx_reset_assert,
+ .rst_deassert = imx_reset_deassert,
};
static const struct udevice_id imx7_reset_ids[] = {
{ .compatible = "fsl,imx7d-src" },
{ .compatible = "fsl,imx8mq-src" },
+ { .compatible = "fsl,imx8mp-src" },
{ }
};
static int imx7_reset_probe(struct udevice *dev)
{
- struct imx7_reset_priv *priv = dev_get_priv(dev);
+ struct imx_reset_priv *priv = dev_get_priv(dev);
priv->base = dev_remap_addr(dev);
if (!priv->base)
return -ENOMEM;
if (device_is_compatible(dev, "fsl,imx8mq-src")) {
- priv->ops.rst_assert = imx7_reset_assert_imx8mq;
- priv->ops.rst_deassert = imx7_reset_deassert_imx8mq;
+ priv->ops.rst_assert = imx8mq_reset_assert;
+ priv->ops.rst_deassert = imx8mq_reset_deassert;
} else if (device_is_compatible(dev, "fsl,imx7d-src")) {
- priv->ops.rst_assert = imx7_reset_assert_imx7;
- priv->ops.rst_deassert = imx7_reset_deassert_imx7;
+ priv->ops.rst_assert = imx7_reset_assert;
+ priv->ops.rst_deassert = imx7_reset_deassert;
+ } else if (device_is_compatible(dev, "fsl,imx8mp-src")) {
+ priv->ops.rst_assert = imx8mp_reset_assert;
+ priv->ops.rst_deassert = imx8mp_reset_deassert;
}
return 0;
@@ -300,5 +401,5 @@
.of_match = imx7_reset_ids,
.ops = &imx7_reset_reset_ops,
.probe = imx7_reset_probe,
- .priv_auto = sizeof(struct imx7_reset_priv),
+ .priv_auto = sizeof(struct imx_reset_priv),
};
diff --git a/drivers/rng/rockchip_rng.c b/drivers/rng/rockchip_rng.c
index ce5cbee..2426648 100644
--- a/drivers/rng/rockchip_rng.c
+++ b/drivers/rng/rockchip_rng.c
@@ -6,7 +6,6 @@
#include <dm.h>
#include <rng.h>
#include <asm/arch-rockchip/hardware.h>
-#include <asm/io.h>
#include <linux/bitops.h>
#include <linux/iopoll.h>
#include <linux/string.h>
@@ -302,7 +301,15 @@
static const struct udevice_id rockchip_rng_match[] = {
{
- .compatible = "rockchip,cryptov1-rng",
+ .compatible = "rockchip,rk3288-crypto",
+ .data = (ulong)&rk_cryptov1_soc_data,
+ },
+ {
+ .compatible = "rockchip,rk3328-crypto",
+ .data = (ulong)&rk_cryptov1_soc_data,
+ },
+ {
+ .compatible = "rockchip,rk3399-crypto",
.data = (ulong)&rk_cryptov1_soc_data,
},
{
diff --git a/drivers/rng/smccc_trng.c b/drivers/rng/smccc_trng.c
index 5bb7ebe..f59b806 100644
--- a/drivers/rng/smccc_trng.c
+++ b/drivers/rng/smccc_trng.c
@@ -165,7 +165,7 @@
struct smccc_trng_priv *priv = dev_get_priv(dev);
struct arm_smccc_res res;
- if (!(smccc_trng_is_supported(smccc->invoke_fn)))
+ if (!smccc || !(smccc_trng_is_supported(smccc->invoke_fn)))
return -ENODEV;
/* At least one of 64bit and 32bit interfaces is available */
diff --git a/drivers/rtc/goldfish_rtc.c b/drivers/rtc/goldfish_rtc.c
index 1ace990..3231eb0 100644
--- a/drivers/rtc/goldfish_rtc.c
+++ b/drivers/rtc/goldfish_rtc.c
@@ -72,7 +72,7 @@
return 0;
}
-int goldfish_rtc_probe(struct udevice *dev)
+static int goldfish_rtc_probe(struct udevice *dev)
{
struct goldfish_rtc *priv = dev_get_priv(dev);
fdt_addr_t addr;
diff --git a/drivers/serial/serial_msm_geni.c b/drivers/serial/serial_msm_geni.c
index e5c3dcf..5260474 100644
--- a/drivers/serial/serial_msm_geni.c
+++ b/drivers/serial/serial_msm_geni.c
@@ -603,7 +603,20 @@
.priv_auto = sizeof(struct msm_serial_data),
.probe = msm_serial_probe,
.ops = &msm_serial_ops,
- .flags = DM_FLAG_PRE_RELOC,
+ .flags = DM_FLAG_PRE_RELOC | DM_FLAG_DEFAULT_PD_CTRL_OFF,
+};
+
+static const struct udevice_id geniqup_ids[] = {
+ { .compatible = "qcom,geni-se-qup" },
+ { }
+};
+
+U_BOOT_DRIVER(geni_se_qup) = {
+ .name = "geni-se-qup",
+ .id = UCLASS_NOP,
+ .of_match = geniqup_ids,
+ .bind = dm_scan_fdt_dev,
+ .flags = DM_FLAG_PRE_RELOC | DM_FLAG_DEFAULT_PD_CTRL_OFF,
};
#ifdef CONFIG_DEBUG_UART_MSM_GENI
diff --git a/drivers/serial/serial_sbi.c b/drivers/serial/serial_sbi.c
index a51a96c..f3ecfcc 100644
--- a/drivers/serial/serial_sbi.c
+++ b/drivers/serial/serial_sbi.c
@@ -17,7 +17,7 @@
#else
-static int sbi_dbcn_available;
+static int sbi_dbcn_available __section(".data");
static inline void _debug_uart_init(void)
{
diff --git a/drivers/serial/serial_xuartlite.c b/drivers/serial/serial_xuartlite.c
index b6197da..35df413 100644
--- a/drivers/serial/serial_xuartlite.c
+++ b/drivers/serial/serial_xuartlite.c
@@ -23,7 +23,7 @@
#define ULITE_CONTROL_RST_TX 0x01
#define ULITE_CONTROL_RST_RX 0x02
-static bool little_endian;
+static bool little_endian __section(".data");
struct uartlite {
unsigned int rx_fifo;
diff --git a/drivers/soc/soc_xilinx_zynqmp.c b/drivers/soc/soc_xilinx_zynqmp.c
index 786825d..d8b4f17 100644
--- a/drivers/soc/soc_xilinx_zynqmp.c
+++ b/drivers/soc/soc_xilinx_zynqmp.c
@@ -44,6 +44,7 @@
ZYNQMP_VARIANT_DR = BIT(3),
ZYNQMP_VARIANT_DR_SE = BIT(4),
ZYNQMP_VARIANT_EG_SE = BIT(5),
+ ZYNQMP_VARIANT_TEG = BIT(6),
};
struct zynqmp_device {
@@ -75,6 +76,11 @@
.variants = ZYNQMP_VARIANT_EG | ZYNQMP_VARIANT_CG,
},
{
+ .id = 0x04718093,
+ .device = 3,
+ .variants = ZYNQMP_VARIANT_TEG,
+ },
+ {
.id = 0x04721093,
.device = 4,
.variants = ZYNQMP_VARIANT_EG | ZYNQMP_VARIANT_CG |
@@ -299,6 +305,8 @@
strlcat(priv->machine, "dr", sizeof(priv->machine));
} else if (device->variants & ZYNQMP_VARIANT_DR_SE) {
strlcat(priv->machine, "dr_SE", sizeof(priv->machine));
+ } else if (device->variants & ZYNQMP_VARIANT_TEG) {
+ strlcat(priv->machine, "teg", sizeof(priv->machine));
}
return 0;
diff --git a/drivers/spi/rk_spi.c b/drivers/spi/rk_spi.c
index 7de9433..c8694fd 100644
--- a/drivers/spi/rk_spi.c
+++ b/drivers/spi/rk_spi.c
@@ -453,8 +453,17 @@
* case of read-only transfers by using the full 16bits of each
* FIFO element.
*/
- if (!out)
+ if (!out) {
ret = rockchip_spi_16bit_reader(dev, &in, &len);
+ /*
+ * If "in" isn't 16b-aligned, we need to send the last byte
+ * ourselves. We however need to have the controller in RO mode
+ * which differs from the default.
+ */
+ clrsetbits_le32(®s->ctrlr0,
+ TMOD_MASK << TMOD_SHIFT,
+ TMOD_RO << TMOD_SHIFT);
+ }
/* This is the original 8bit reader/writer code */
while (len > 0) {
@@ -465,12 +474,13 @@
rkspi_enable_chip(regs, true);
toread = todo;
- towrite = todo;
+ /* Only write if we have something to write */
+ towrite = out ? todo : 0;
while (toread || towrite) {
u32 status = readl(®s->sr);
if (towrite && !(status & SR_TF_FULL)) {
- writel(out ? *out++ : 0, regs->txdr);
+ writel(*out++, regs->txdr);
towrite--;
}
if (toread && !(status & SR_RF_EMPT)) {
@@ -501,6 +511,10 @@
spi_cs_deactivate(dev, slave_plat->cs);
rkspi_enable_chip(regs, false);
+ if (!out)
+ clrsetbits_le32(®s->ctrlr0,
+ TMOD_MASK << TMOD_SHIFT,
+ TMOD_TR << TMOD_SHIFT);
return ret;
}
diff --git a/drivers/sysreset/sysreset_rockchip.c b/drivers/sysreset/sysreset_rockchip.c
index 0fc6b68..f353f9b 100644
--- a/drivers/sysreset/sysreset_rockchip.c
+++ b/drivers/sysreset/sysreset_rockchip.c
@@ -7,7 +7,6 @@
#include <dm.h>
#include <errno.h>
#include <sysreset.h>
-#include <asm/io.h>
#include <asm/arch-rockchip/clock.h>
#include <asm/arch-rockchip/cru_rk3328.h>
#include <asm/arch-rockchip/hardware.h>
diff --git a/drivers/tee/sandbox.c b/drivers/tee/sandbox.c
index 86219a9..ec66401 100644
--- a/drivers/tee/sandbox.c
+++ b/drivers/tee/sandbox.c
@@ -14,7 +14,7 @@
#include "optee/optee_private.h"
/*
- * The sandbox tee driver tries to emulate a generic Trusted Exectution
+ * The sandbox tee driver tries to emulate a generic Trusted Execution
* Environment (TEE) with the Trusted Applications (TA) OPTEE_TA_AVB and
* OPTEE_TA_RPC_TEST available.
*/
@@ -23,7 +23,7 @@
/**
* struct ta_entry - TA entries
* @uuid: UUID of an emulated TA
- * @open_session Called when a session is openened to the TA
+ * @open_session Called when a session is opened to the TA
* @invoke_func Called when a function in the TA is to be invoked
*
* This struct is used to register TAs in this sandbox emulation of a TEE.
@@ -140,8 +140,8 @@
provisioned = true;
/*
- * Either way, we asume both operations succeeded and that
- * the communication channel has now been stablished
+ * Either way, we assume both operations succeeded and that
+ * the communication channel has now been established
*/
return TEE_SUCCESS;
diff --git a/drivers/thermal/imx_tmu.c b/drivers/thermal/imx_tmu.c
index 4721cfb..ea6c832 100644
--- a/drivers/thermal/imx_tmu.c
+++ b/drivers/thermal/imx_tmu.c
@@ -402,6 +402,7 @@
#endif
static inline void imx_tmu_mx93_init(struct udevice *dev) { }
+static inline void imx_tmu_mx8mq_init(struct udevice *dev) { }
static void imx_tmu_arch_init(struct udevice *dev)
{
@@ -411,6 +412,8 @@
imx_tmu_mx8mp_init(dev);
else if (is_imx93())
imx_tmu_mx93_init(dev);
+ else if (is_imx8mq())
+ imx_tmu_mx8mq_init(dev);
else
dev_err(dev, "Unsupported SoC, TMU calibration not loaded!\n");
}
@@ -570,12 +573,14 @@
{
struct imx_tmu_plat *pdata = dev_get_plat(dev), *p_parent_data;
struct ofnode_phandle_args args;
- ofnode trips_np;
+ ofnode trips_np, cpu_thermal_np;
int ret;
dev_dbg(dev, "%s\n", __func__);
- pdata->polling_delay = IMX_TMU_POLLING_DELAY_MS;
+ cpu_thermal_np = ofnode_path("/thermal-zones/cpu-thermal");
+ pdata->polling_delay = ofnode_read_u32_default(cpu_thermal_np, "polling-delay",
+ IMX_TMU_POLLING_DELAY_MS);
if (pdata->zone_node) {
pdata->regs = (union tmu_regs *)dev_read_addr_ptr(dev);
diff --git a/drivers/usb/dwc3/core.c b/drivers/usb/dwc3/core.c
index 4b4fcd8..96e850b 100644
--- a/drivers/usb/dwc3/core.c
+++ b/drivers/usb/dwc3/core.c
@@ -983,18 +983,32 @@
}
}
+MODULE_ALIAS("platform:dwc3");
+MODULE_AUTHOR("Felipe Balbi <balbi@ti.com>");
+MODULE_LICENSE("GPL v2");
+MODULE_DESCRIPTION("DesignWare USB3 DRD Controller Driver");
+
+#if !CONFIG_IS_ENABLED(DM_USB_GADGET)
+__weak int dwc3_uboot_interrupt_status(struct udevice *dev)
+{
+ return 1;
+}
+
/**
- * dwc3_uboot_handle_interrupt - handle dwc3 core interrupt
+ * dm_usb_gadget_handle_interrupts - handle dwc3 core interrupt
* @dev: device of this controller
*
* Invokes dwc3 gadget interrupts.
*
* Generally called from board file.
*/
-void dwc3_uboot_handle_interrupt(struct udevice *dev)
+int dm_usb_gadget_handle_interrupts(struct udevice *dev)
{
struct dwc3 *dwc = NULL;
+ if (!dwc3_uboot_interrupt_status(dev))
+ return 0;
+
list_for_each_entry(dwc, &dwc3_list, list) {
if (dwc->dev != dev)
continue;
@@ -1002,12 +1016,10 @@
dwc3_gadget_uboot_handle_interrupt(dwc);
break;
}
-}
-MODULE_ALIAS("platform:dwc3");
-MODULE_AUTHOR("Felipe Balbi <balbi@ti.com>");
-MODULE_LICENSE("GPL v2");
-MODULE_DESCRIPTION("DesignWare USB3 DRD Controller Driver");
+ return 0;
+}
+#endif
#if CONFIG_IS_ENABLED(PHY) && CONFIG_IS_ENABLED(DM_USB)
int dwc3_setup_phy(struct udevice *dev, struct phy_bulk *phys)
diff --git a/drivers/usb/dwc3/dwc3-generic.c b/drivers/usb/dwc3/dwc3-generic.c
index a379a00..7a00529 100644
--- a/drivers/usb/dwc3/dwc3-generic.c
+++ b/drivers/usb/dwc3/dwc3-generic.c
@@ -425,6 +425,77 @@
.glue_configure = dwc3_ti_glue_configure,
};
+/* USB QSCRATCH Hardware registers */
+#define QSCRATCH_GENERAL_CFG 0x08
+#define PIPE_UTMI_CLK_SEL BIT(0)
+#define PIPE3_PHYSTATUS_SW BIT(3)
+#define PIPE_UTMI_CLK_DIS BIT(8)
+
+#define QSCRATCH_HS_PHY_CTRL 0x10
+#define UTMI_OTG_VBUS_VALID BIT(20)
+#define SW_SESSVLD_SEL BIT(28)
+
+#define QSCRATCH_SS_PHY_CTRL 0x30
+#define LANE0_PWR_PRESENT BIT(24)
+
+#define PWR_EVNT_IRQ_STAT_REG 0x58
+#define PWR_EVNT_LPM_IN_L2_MASK BIT(4)
+#define PWR_EVNT_LPM_OUT_L2_MASK BIT(5)
+
+#define SDM845_QSCRATCH_BASE_OFFSET 0xf8800
+#define SDM845_QSCRATCH_SIZE 0x400
+#define SDM845_DWC3_CORE_SIZE 0xcd00
+
+static void dwc3_qcom_vbus_override_enable(void __iomem *qscratch_base, bool enable)
+{
+ if (enable) {
+ setbits_le32(qscratch_base + QSCRATCH_SS_PHY_CTRL,
+ LANE0_PWR_PRESENT);
+ setbits_le32(qscratch_base + QSCRATCH_HS_PHY_CTRL,
+ UTMI_OTG_VBUS_VALID | SW_SESSVLD_SEL);
+ } else {
+ clrbits_le32(qscratch_base + QSCRATCH_SS_PHY_CTRL,
+ LANE0_PWR_PRESENT);
+ clrbits_le32(qscratch_base + QSCRATCH_HS_PHY_CTRL,
+ UTMI_OTG_VBUS_VALID | SW_SESSVLD_SEL);
+ }
+}
+
+/* For controllers running without superspeed PHYs */
+static void dwc3_qcom_select_utmi_clk(void __iomem *qscratch_base)
+{
+ /* Configure dwc3 to use UTMI clock as PIPE clock not present */
+ setbits_le32(qscratch_base + QSCRATCH_GENERAL_CFG,
+ PIPE_UTMI_CLK_DIS);
+
+ setbits_le32(qscratch_base + QSCRATCH_GENERAL_CFG,
+ PIPE_UTMI_CLK_SEL | PIPE3_PHYSTATUS_SW);
+
+ clrbits_le32(qscratch_base + QSCRATCH_GENERAL_CFG,
+ PIPE_UTMI_CLK_DIS);
+}
+
+static void dwc3_qcom_glue_configure(struct udevice *dev, int index,
+ enum usb_dr_mode mode)
+{
+ struct dwc3_glue_data *glue = dev_get_plat(dev);
+ void __iomem *qscratch_base = map_physmem(glue->regs, 0x400, MAP_NOCACHE);
+ if (IS_ERR_OR_NULL(qscratch_base)) {
+ log_err("%s: Invalid qscratch base address\n", dev->name);
+ return;
+ }
+
+ if (dev_read_bool(dev, "qcom,select-utmi-as-pipe-clk"))
+ dwc3_qcom_select_utmi_clk(qscratch_base);
+
+ if (mode != USB_DR_MODE_HOST)
+ dwc3_qcom_vbus_override_enable(qscratch_base, true);
+}
+
+struct dwc3_glue_ops qcom_ops = {
+ .glue_configure = dwc3_qcom_glue_configure,
+};
+
static int dwc3_rk_glue_get_ctrl_dev(struct udevice *dev, ofnode *node)
{
*node = dev_ofnode(dev);
@@ -512,6 +583,14 @@
else if (ret)
return ret;
+ if (device_is_compatible(dev, "qcom,dwc3")) {
+ reset_assert_bulk(&glue->resets);
+ /* We should wait at least 6 sleep clock cycles, that's
+ * (6 / 32764) * 1000000 ~= 200us. But some platforms
+ * have slower sleep clocks so we'll play it safe.
+ */
+ udelay(500);
+ }
ret = reset_deassert_bulk(&glue->resets);
if (ret) {
reset_release_bulk(&glue->resets);
@@ -629,7 +708,7 @@
{ .compatible = "rockchip,rk3399-dwc3" },
{ .compatible = "rockchip,rk3568-dwc3", .data = (ulong)&rk_ops },
{ .compatible = "rockchip,rk3588-dwc3", .data = (ulong)&rk_ops },
- { .compatible = "qcom,dwc3" },
+ { .compatible = "qcom,dwc3", .data = (ulong)&qcom_ops },
{ .compatible = "fsl,imx8mp-dwc3", .data = (ulong)&imx8mp_ops },
{ .compatible = "fsl,imx8mq-dwc3" },
{ .compatible = "intel,tangier-dwc3" },
diff --git a/drivers/usb/dwc3/dwc3-omap.c b/drivers/usb/dwc3/dwc3-omap.c
index 4fadb4a..53c4d48 100644
--- a/drivers/usb/dwc3/dwc3-omap.c
+++ b/drivers/usb/dwc3/dwc3-omap.c
@@ -428,7 +428,7 @@
}
/**
- * dwc3_omap_uboot_interrupt_status - check the status of interrupt
+ * dwc3_uboot_interrupt_status - check the status of interrupt
* @dev: device of this controller
*
* Checks the status of interrupts and returns true if an interrupt
@@ -436,7 +436,7 @@
*
* Generally called from board file.
*/
-int dwc3_omap_uboot_interrupt_status(struct udevice *dev)
+int dwc3_uboot_interrupt_status(struct udevice *dev)
{
struct dwc3_omap *omap = NULL;
diff --git a/drivers/usb/gadget/Kconfig b/drivers/usb/gadget/Kconfig
index c72a804..4621a6f 100644
--- a/drivers/usb/gadget/Kconfig
+++ b/drivers/usb/gadget/Kconfig
@@ -70,12 +70,21 @@
hex "Product ID of the USB device"
default 0x701a if ARCH_TEGRA
default 0x1010 if ARCH_SUNXI
- default 0x310a if ROCKCHIP_RK3036
+ default 0x110a if ROCKCHIP_RV1108
+ default 0x110b if ROCKCHIP_RV1126
default 0x300a if ROCKCHIP_RK3066
+ default 0x301a if ROCKCHIP_RK3036
+ default 0x310b if ROCKCHIP_RK3188
default 0x310c if ROCKCHIP_RK3128
- default 0x320a if ROCKCHIP_RK3229 || ROCKCHIP_RK3288
- default 0x330a if ROCKCHIP_RK3328
+ default 0x320a if ROCKCHIP_RK3288
+ default 0x320b if ROCKCHIP_RK322X
+ default 0x320c if ROCKCHIP_RK3328
+ default 0x330a if ROCKCHIP_RK3368
default 0x330c if ROCKCHIP_RK3399
+ default 0x330d if ROCKCHIP_PX30
+ default 0x330e if ROCKCHIP_RK3308
+ default 0x350a if ROCKCHIP_RK3568
+ default 0x350b if ROCKCHIP_RK3588
default 0x0
help
Product ID of the USB device emulated, reported to the host device.
diff --git a/drivers/usb/gadget/f_acm.c b/drivers/usb/gadget/f_acm.c
index de42e01..ba21612 100644
--- a/drivers/usb/gadget/f_acm.c
+++ b/drivers/usb/gadget/f_acm.c
@@ -623,12 +623,21 @@
static int acm_stdio_start(struct stdio_dev *dev)
{
+ struct udevice *udc;
int ret;
if (dev->priv) { /* function already exist */
return 0;
}
+ ret = udc_device_get_by_index(0, &udc);
+ if (ret) {
+ pr_err("USB init failed: %d\n", ret);
+ return ret;
+ }
+
+ g_dnl_clear_detach();
+
ret = g_dnl_register("usb_serial_acm");
if (ret)
return ret;
diff --git a/drivers/usb/gadget/f_mass_storage.c b/drivers/usb/gadget/f_mass_storage.c
index c725aed..ef90c7e 100644
--- a/drivers/usb/gadget/f_mass_storage.c
+++ b/drivers/usb/gadget/f_mass_storage.c
@@ -240,6 +240,7 @@
/* #define DUMP_MSGS */
#include <config.h>
+#include <div64.h>
#include <hexdump.h>
#include <log.h>
#include <malloc.h>
@@ -724,12 +725,13 @@
curlun->sense_data = SS_LOGICAL_BLOCK_ADDRESS_OUT_OF_RANGE;
return -EINVAL;
}
- file_offset = ((loff_t) lba) << 9;
+ file_offset = ((loff_t)lba) << curlun->blkbits;
/* Carry out the file reads */
amount_left = common->data_size_from_cmnd;
- if (unlikely(amount_left == 0))
+ if (unlikely(amount_left == 0)) {
return -EIO; /* No default reply */
+ }
for (;;) {
@@ -768,13 +770,13 @@
/* Perform the read */
rc = ums[common->lun].read_sector(&ums[common->lun],
- file_offset / SECTOR_SIZE,
- amount / SECTOR_SIZE,
+ lldiv(file_offset, curlun->blksize),
+ lldiv(amount, curlun->blksize),
(char __user *)bh->buf);
if (!rc)
return -EIO;
- nread = rc * SECTOR_SIZE;
+ nread = rc * curlun->blksize;
VLDBG(curlun, "file read %u @ %llu -> %d\n", amount,
(unsigned long long) file_offset,
@@ -787,7 +789,7 @@
} else if (nread < amount) {
LDBG(curlun, "partial file read: %d/%u\n",
(int) nread, amount);
- nread -= (nread & 511); /* Round down to a block */
+ nread -= (nread & (curlun->blksize - 1)); /* Round down to a block */
}
file_offset += nread;
amount_left -= nread;
@@ -861,7 +863,7 @@
/* Carry out the file writes */
get_some_more = 1;
- file_offset = usb_offset = ((loff_t) lba) << 9;
+ file_offset = usb_offset = ((loff_t)lba) << curlun->blkbits;
amount_left_to_req = common->data_size_from_cmnd;
amount_left_to_write = common->data_size_from_cmnd;
@@ -893,7 +895,7 @@
curlun->info_valid = 1;
continue;
}
- amount -= (amount & 511);
+ amount -= (amount & (curlun->blksize - 1));
if (amount == 0) {
/* Why were we were asked to transfer a
@@ -942,12 +944,12 @@
/* Perform the write */
rc = ums[common->lun].write_sector(&ums[common->lun],
- file_offset / SECTOR_SIZE,
- amount / SECTOR_SIZE,
+ lldiv(file_offset, curlun->blksize),
+ lldiv(amount, curlun->blksize),
(char __user *)bh->buf);
if (!rc)
return -EIO;
- nwritten = rc * SECTOR_SIZE;
+ nwritten = rc * curlun->blksize;
VLDBG(curlun, "file write %u @ %llu -> %d\n", amount,
(unsigned long long) file_offset,
@@ -960,7 +962,7 @@
} else if (nwritten < amount) {
LDBG(curlun, "partial file write: %d/%u\n",
(int) nwritten, amount);
- nwritten -= (nwritten & 511);
+ nwritten -= (nwritten & (curlun->blksize - 1));
/* Round down to a block */
}
file_offset += nwritten;
@@ -1034,8 +1036,8 @@
return -EIO; /* No default reply */
/* Prepare to carry out the file verify */
- amount_left = verification_length << 9;
- file_offset = ((loff_t) lba) << 9;
+ amount_left = verification_length << curlun->blkbits;
+ file_offset = ((loff_t) lba) << curlun->blkbits;
/* Write out all the dirty buffers before invalidating them */
@@ -1058,12 +1060,12 @@
/* Perform the read */
rc = ums[common->lun].read_sector(&ums[common->lun],
- file_offset / SECTOR_SIZE,
- amount / SECTOR_SIZE,
+ lldiv(file_offset, curlun->blksize),
+ lldiv(amount, curlun->blksize),
(char __user *)bh->buf);
if (!rc)
return -EIO;
- nread = rc * SECTOR_SIZE;
+ nread = rc * curlun->blksize;
VLDBG(curlun, "file read %u @ %llu -> %d\n", amount,
(unsigned long long) file_offset,
@@ -1075,7 +1077,7 @@
} else if (nread < amount) {
LDBG(curlun, "partial file verify: %d/%u\n",
(int) nread, amount);
- nread -= (nread & 511); /* Round down to a sector */
+ nread -= (nread & (curlun->blksize - 1)); /* Round down to a sector */
}
if (nread == 0) {
curlun->sense_data = SS_UNRECOVERED_READ_ERROR;
@@ -1183,7 +1185,7 @@
put_unaligned_be32(curlun->num_sectors - 1, &buf[0]);
/* Max logical block */
- put_unaligned_be32(512, &buf[4]); /* Block length */
+ put_unaligned_be32(curlun->blksize, &buf[4]); /* Block length */
return 8;
}
@@ -1370,7 +1372,7 @@
put_unaligned_be32(curlun->num_sectors, &buf[0]);
/* Number of blocks */
- put_unaligned_be32(512, &buf[4]); /* Block length */
+ put_unaligned_be32(curlun->blksize, &buf[4]); /* Block length */
buf[4] = 0x02; /* Current capacity */
return 12;
}
@@ -1781,6 +1783,16 @@
return 0;
}
+/* wrapper of check_command for data size in blocks handling */
+static int check_command_size_in_blocks(struct fsg_common *common,
+ int cmnd_size, enum data_direction data_dir,
+ unsigned int mask, int needs_medium, const char *name)
+{
+ common->data_size_from_cmnd <<= common->luns[common->lun].blkbits;
+ return check_command(common, cmnd_size, data_dir,
+ mask, needs_medium, name);
+}
+
static int do_scsi_command(struct fsg_common *common)
{
@@ -1865,30 +1877,30 @@
case SC_READ_6:
i = common->cmnd[4];
- common->data_size_from_cmnd = (i == 0 ? 256 : i) << 9;
- reply = check_command(common, 6, DATA_DIR_TO_HOST,
- (7<<1) | (1<<4), 1,
- "READ(6)");
+ common->data_size_from_cmnd = (i == 0 ? 256 : i);
+ reply = check_command_size_in_blocks(common, 6, DATA_DIR_TO_HOST,
+ (7<<1) | (1<<4), 1,
+ "READ(6)");
if (reply == 0)
reply = do_read(common);
break;
case SC_READ_10:
common->data_size_from_cmnd =
- get_unaligned_be16(&common->cmnd[7]) << 9;
- reply = check_command(common, 10, DATA_DIR_TO_HOST,
- (1<<1) | (0xf<<2) | (3<<7), 1,
- "READ(10)");
+ get_unaligned_be16(&common->cmnd[7]);
+ reply = check_command_size_in_blocks(common, 10, DATA_DIR_TO_HOST,
+ (1<<1) | (0xf<<2) | (3<<7), 1,
+ "READ(10)");
if (reply == 0)
reply = do_read(common);
break;
case SC_READ_12:
common->data_size_from_cmnd =
- get_unaligned_be32(&common->cmnd[6]) << 9;
- reply = check_command(common, 12, DATA_DIR_TO_HOST,
- (1<<1) | (0xf<<2) | (0xf<<6), 1,
- "READ(12)");
+ get_unaligned_be32(&common->cmnd[6]);
+ reply = check_command_size_in_blocks(common, 12, DATA_DIR_TO_HOST,
+ (1<<1) | (0xf<<2) | (0xf<<6), 1,
+ "READ(12)");
if (reply == 0)
reply = do_read(common);
break;
@@ -1983,30 +1995,30 @@
case SC_WRITE_6:
i = common->cmnd[4];
- common->data_size_from_cmnd = (i == 0 ? 256 : i) << 9;
- reply = check_command(common, 6, DATA_DIR_FROM_HOST,
- (7<<1) | (1<<4), 1,
- "WRITE(6)");
+ common->data_size_from_cmnd = (i == 0 ? 256 : i);
+ reply = check_command_size_in_blocks(common, 6, DATA_DIR_FROM_HOST,
+ (7<<1) | (1<<4), 1,
+ "WRITE(6)");
if (reply == 0)
reply = do_write(common);
break;
case SC_WRITE_10:
common->data_size_from_cmnd =
- get_unaligned_be16(&common->cmnd[7]) << 9;
- reply = check_command(common, 10, DATA_DIR_FROM_HOST,
- (1<<1) | (0xf<<2) | (3<<7), 1,
- "WRITE(10)");
+ get_unaligned_be16(&common->cmnd[7]);
+ reply = check_command_size_in_blocks(common, 10, DATA_DIR_FROM_HOST,
+ (1<<1) | (0xf<<2) | (3<<7), 1,
+ "WRITE(10)");
if (reply == 0)
reply = do_write(common);
break;
case SC_WRITE_12:
common->data_size_from_cmnd =
- get_unaligned_be32(&common->cmnd[6]) << 9;
- reply = check_command(common, 12, DATA_DIR_FROM_HOST,
- (1<<1) | (0xf<<2) | (0xf<<6), 1,
- "WRITE(12)");
+ get_unaligned_be32(&common->cmnd[6]);
+ reply = check_command_size_in_blocks(common, 12, DATA_DIR_FROM_HOST,
+ (1<<1) | (0xf<<2) | (0xf<<6), 1,
+ "WRITE(12)");
if (reply == 0)
reply = do_write(common);
break;
@@ -2497,7 +2509,7 @@
for (i = 0; i < nluns; i++) {
common->luns[i].removable = 1;
- rc = fsg_lun_open(&common->luns[i], ums[i].num_sectors, "");
+ rc = fsg_lun_open(&common->luns[i], ums[i].num_sectors, ums->block_dev.blksz, "");
if (rc)
goto error_luns;
}
diff --git a/drivers/usb/gadget/storage_common.c b/drivers/usb/gadget/storage_common.c
index 5674e8f..97dc6b6 100644
--- a/drivers/usb/gadget/storage_common.c
+++ b/drivers/usb/gadget/storage_common.c
@@ -269,6 +269,7 @@
#define ETOOSMALL 525
#include <log.h>
+#include <linux/log2.h>
#include <usb_mass_storage.h>
#include <dm/device_compat.h>
@@ -290,6 +291,8 @@
u32 sense_data;
u32 sense_data_info;
u32 unit_attention_data;
+ unsigned int blkbits;
+ unsigned int blksize; /* logical block size of bound block device */
struct device dev;
};
@@ -566,7 +569,7 @@
*/
static int fsg_lun_open(struct fsg_lun *curlun, unsigned int num_sectors,
- const char *filename)
+ unsigned int sector_size, const char *filename)
{
int ro;
@@ -574,9 +577,12 @@
ro = curlun->initially_ro;
curlun->ro = ro;
- curlun->file_length = num_sectors << 9;
+ curlun->file_length = num_sectors * sector_size;
curlun->num_sectors = num_sectors;
- debug("open backing file: %s\n", filename);
+ curlun->blksize = sector_size;
+ curlun->blkbits = order_base_2(sector_size >> 9) + 9;
+ debug("blksize: %u\n", sector_size);
+ debug("open backing file: '%s'\n", filename);
return 0;
}
diff --git a/drivers/video/Kconfig b/drivers/video/Kconfig
index 6f319ba..39c8252 100644
--- a/drivers/video/Kconfig
+++ b/drivers/video/Kconfig
@@ -180,6 +180,7 @@
config CONSOLE_TRUETYPE
bool "Support a console that uses TrueType fonts"
+ select X86_HARDFP if X86
help
TrueTrype fonts can provide outline-drawing capability rather than
needing to provide a bitmap for each font and size that is needed.
diff --git a/drivers/video/console_normal.c b/drivers/video/console_normal.c
index a023129..34ef5a5 100644
--- a/drivers/video/console_normal.c
+++ b/drivers/video/console_normal.c
@@ -7,6 +7,7 @@
*/
#include <common.h>
+#include <charset.h>
#include <dm.h>
#include <video.h>
#include <video_console.h>
@@ -63,7 +64,7 @@
return 0;
}
-static int console_putc_xy(struct udevice *dev, uint x_frac, uint y, char ch)
+static int console_putc_xy(struct udevice *dev, uint x_frac, uint y, int cp)
{
struct vidconsole_priv *vc_priv = dev_get_uclass_priv(dev);
struct udevice *vid = dev->parent;
@@ -73,8 +74,9 @@
int pbytes = VNBYTES(vid_priv->bpix);
int x, linenum, ret;
void *start, *line;
+ u8 ch = console_utf_to_cp437(cp);
uchar *pfont = fontdata->video_fontdata +
- (u8)ch * fontdata->char_pixel_bytes;
+ ch * fontdata->char_pixel_bytes;
if (x_frac + VID_TO_POS(vc_priv->x_charsize) > vc_priv->xsize_frac)
return -EAGAIN;
diff --git a/drivers/video/console_rotate.c b/drivers/video/console_rotate.c
index 65358a1..e4303df 100644
--- a/drivers/video/console_rotate.c
+++ b/drivers/video/console_rotate.c
@@ -7,6 +7,7 @@
*/
#include <common.h>
+#include <charset.h>
#include <dm.h>
#include <video.h>
#include <video_console.h>
@@ -67,7 +68,7 @@
return 0;
}
-static int console_putc_xy_1(struct udevice *dev, uint x_frac, uint y, char ch)
+static int console_putc_xy_1(struct udevice *dev, uint x_frac, uint y, int cp)
{
struct vidconsole_priv *vc_priv = dev_get_uclass_priv(dev);
struct udevice *vid = dev->parent;
@@ -77,8 +78,9 @@
int pbytes = VNBYTES(vid_priv->bpix);
int x, linenum, ret;
void *start, *line;
+ u8 ch = console_utf_to_cp437(cp);
uchar *pfont = fontdata->video_fontdata +
- (u8)ch * fontdata->char_pixel_bytes;
+ ch * fontdata->char_pixel_bytes;
if (x_frac + VID_TO_POS(vc_priv->x_charsize) > vc_priv->xsize_frac)
return -EAGAIN;
@@ -145,7 +147,7 @@
return 0;
}
-static int console_putc_xy_2(struct udevice *dev, uint x_frac, uint y, char ch)
+static int console_putc_xy_2(struct udevice *dev, uint x_frac, uint y, int cp)
{
struct vidconsole_priv *vc_priv = dev_get_uclass_priv(dev);
struct udevice *vid = dev->parent;
@@ -155,8 +157,9 @@
int pbytes = VNBYTES(vid_priv->bpix);
int linenum, x, ret;
void *start, *line;
+ u8 ch = console_utf_to_cp437(cp);
uchar *pfont = fontdata->video_fontdata +
- (u8)ch * fontdata->char_pixel_bytes;
+ ch * fontdata->char_pixel_bytes;
if (x_frac + VID_TO_POS(vc_priv->x_charsize) > vc_priv->xsize_frac)
return -EAGAIN;
@@ -227,7 +230,7 @@
return 0;
}
-static int console_putc_xy_3(struct udevice *dev, uint x_frac, uint y, char ch)
+static int console_putc_xy_3(struct udevice *dev, uint x_frac, uint y, int cp)
{
struct vidconsole_priv *vc_priv = dev_get_uclass_priv(dev);
struct udevice *vid = dev->parent;
@@ -237,8 +240,9 @@
int pbytes = VNBYTES(vid_priv->bpix);
int linenum, x, ret;
void *start, *line;
+ u8 ch = console_utf_to_cp437(cp);
uchar *pfont = fontdata->video_fontdata +
- (u8)ch * fontdata->char_pixel_bytes;
+ ch * fontdata->char_pixel_bytes;
if (x_frac + VID_TO_POS(vc_priv->x_charsize) > vc_priv->xsize_frac)
return -EAGAIN;
diff --git a/drivers/video/console_truetype.c b/drivers/video/console_truetype.c
index 547e5a8..28665a3 100644
--- a/drivers/video/console_truetype.c
+++ b/drivers/video/console_truetype.c
@@ -8,6 +8,7 @@
#include <dm.h>
#include <log.h>
#include <malloc.h>
+#include <spl.h>
#include <video.h>
#include <video_console.h>
@@ -262,7 +263,7 @@
}
static int console_truetype_putc_xy(struct udevice *dev, uint x, uint y,
- char ch)
+ int cp)
{
struct vidconsole_priv *vc_priv = dev_get_uclass_priv(dev);
struct udevice *vid = dev->parent;
@@ -281,7 +282,7 @@
int row, ret;
/* First get some basic metrics about this character */
- stbtt_GetCodepointHMetrics(font, ch, &advance, &lsb);
+ stbtt_GetCodepointHMetrics(font, cp, &advance, &lsb);
/*
* First out our current X position in fractional pixels. If we wrote
@@ -290,7 +291,7 @@
xpos = frac(VID_TO_PIXEL((double)x));
if (vc_priv->last_ch) {
xpos += met->scale * stbtt_GetCodepointKernAdvance(font,
- vc_priv->last_ch, ch);
+ vc_priv->last_ch, cp);
}
/*
@@ -320,7 +321,7 @@
* return NULL;
*/
data = stbtt_GetCodepointBitmapSubpixel(font, met->scale, met->scale,
- x_shift, 0, ch, &width, &height,
+ x_shift, 0, cp, &width, &height,
&xoff, &yoff);
if (!data)
return width_frac;
@@ -802,6 +803,9 @@
struct console_tt_store store;
const uint size = sizeof(store);
+ if (spl_phase() <= PHASE_SPL)
+ return -ENOSYS;
+
/*
* store the whole priv structure as it is simpler that picking out
* what we need
@@ -823,6 +827,9 @@
struct console_tt_priv *priv = dev_get_priv(dev);
struct console_tt_store store;
+ if (spl_phase() <= PHASE_SPL)
+ return -ENOSYS;
+
memcpy(&store, abuf_data(buf), sizeof(store));
vc_priv->xcur_frac = store.cur.xpos_frac;
@@ -847,6 +854,9 @@
uint out, val;
int ret;
+ if (spl_phase() <= PHASE_SPL)
+ return -ENOSYS;
+
if (!visible)
return 0;
diff --git a/drivers/video/rockchip/dw_mipi_dsi_rockchip.c b/drivers/video/rockchip/dw_mipi_dsi_rockchip.c
index 5e75b6e..fb78463 100644
--- a/drivers/video/rockchip/dw_mipi_dsi_rockchip.c
+++ b/drivers/video/rockchip/dw_mipi_dsi_rockchip.c
@@ -27,7 +27,6 @@
#include <common.h>
#include <log.h>
#include <video.h>
-#include <asm/io.h>
#include <dm/device-internal.h>
#include <linux/bitops.h>
#include <linux/time.h>
diff --git a/drivers/video/rockchip/rk3288_hdmi.c b/drivers/video/rockchip/rk3288_hdmi.c
index 8bedee5..efa8754 100644
--- a/drivers/video/rockchip/rk3288_hdmi.c
+++ b/drivers/video/rockchip/rk3288_hdmi.c
@@ -14,7 +14,6 @@
#include <regmap.h>
#include <syscon.h>
#include <asm/gpio.h>
-#include <asm/io.h>
#include <asm/arch-rockchip/clock.h>
#include <asm/arch-rockchip/hardware.h>
#include <asm/arch-rockchip/grf_rk3288.h>
diff --git a/drivers/video/rockchip/rk3288_mipi.c b/drivers/video/rockchip/rk3288_mipi.c
index c0dffa3..9d42119 100644
--- a/drivers/video/rockchip/rk3288_mipi.c
+++ b/drivers/video/rockchip/rk3288_mipi.c
@@ -14,7 +14,6 @@
#include "rk_mipi.h"
#include <syscon.h>
#include <asm/gpio.h>
-#include <asm/io.h>
#include <dm/uclass-internal.h>
#include <linux/err.h>
#include <linux/kernel.h>
diff --git a/drivers/video/rockchip/rk3288_vop.c b/drivers/video/rockchip/rk3288_vop.c
index 44f32bb..a468385 100644
--- a/drivers/video/rockchip/rk3288_vop.c
+++ b/drivers/video/rockchip/rk3288_vop.c
@@ -12,7 +12,6 @@
#include <syscon.h>
#include <video.h>
#include <asm/global_data.h>
-#include <asm/io.h>
#include <asm/arch-rockchip/clock.h>
#include <asm/arch-rockchip/grf_rk3288.h>
#include <asm/arch-rockchip/hardware.h>
diff --git a/drivers/video/rockchip/rk3399_hdmi.c b/drivers/video/rockchip/rk3399_hdmi.c
index 3041360..5f3f5d2 100644
--- a/drivers/video/rockchip/rk3399_hdmi.c
+++ b/drivers/video/rockchip/rk3399_hdmi.c
@@ -12,7 +12,6 @@
#include <regmap.h>
#include <syscon.h>
#include <asm/gpio.h>
-#include <asm/io.h>
#include <asm/arch-rockchip/clock.h>
#include <asm/arch-rockchip/hardware.h>
#include <asm/arch-rockchip/grf_rk3399.h>
diff --git a/drivers/video/rockchip/rk3399_mipi.c b/drivers/video/rockchip/rk3399_mipi.c
index 7fc79ba..b62d808 100644
--- a/drivers/video/rockchip/rk3399_mipi.c
+++ b/drivers/video/rockchip/rk3399_mipi.c
@@ -14,7 +14,6 @@
#include "rk_mipi.h"
#include <syscon.h>
#include <asm/gpio.h>
-#include <asm/io.h>
#include <dm/uclass-internal.h>
#include <linux/err.h>
#include <linux/kernel.h>
diff --git a/drivers/video/rockchip/rk3399_vop.c b/drivers/video/rockchip/rk3399_vop.c
index a34b491..cb589c7 100644
--- a/drivers/video/rockchip/rk3399_vop.c
+++ b/drivers/video/rockchip/rk3399_vop.c
@@ -13,7 +13,6 @@
#include <video.h>
#include <asm/arch-rockchip/hardware.h>
#include <asm/global_data.h>
-#include <asm/io.h>
#include "rk_vop.h"
DECLARE_GLOBAL_DATA_PTR;
diff --git a/drivers/video/rockchip/rk_edp.c b/drivers/video/rockchip/rk_edp.c
index dbd70ad..5f68a61 100644
--- a/drivers/video/rockchip/rk_edp.c
+++ b/drivers/video/rockchip/rk_edp.c
@@ -17,7 +17,6 @@
#include <reset.h>
#include <syscon.h>
#include <asm/gpio.h>
-#include <asm/io.h>
#include <asm/arch-rockchip/clock.h>
#include <asm/arch-rockchip/hardware.h>
#include <asm/arch-rockchip/edp_rk3288.h>
diff --git a/drivers/video/rockchip/rk_hdmi.c b/drivers/video/rockchip/rk_hdmi.c
index 8dcd4d5..044a29e 100644
--- a/drivers/video/rockchip/rk_hdmi.c
+++ b/drivers/video/rockchip/rk_hdmi.c
@@ -15,7 +15,6 @@
#include <regmap.h>
#include <syscon.h>
#include <asm/gpio.h>
-#include <asm/io.h>
#include <asm/arch-rockchip/clock.h>
#include <asm/arch-rockchip/hardware.h>
#include "rk_hdmi.h"
diff --git a/drivers/video/rockchip/rk_lvds.c b/drivers/video/rockchip/rk_lvds.c
index 9cf3e3c..d0a015e 100644
--- a/drivers/video/rockchip/rk_lvds.c
+++ b/drivers/video/rockchip/rk_lvds.c
@@ -13,7 +13,6 @@
#include <syscon.h>
#include <asm/global_data.h>
#include <asm/gpio.h>
-#include <asm/io.h>
#include <asm/arch-rockchip/clock.h>
#include <asm/arch-rockchip/grf_rk3288.h>
#include <asm/arch-rockchip/hardware.h>
diff --git a/drivers/video/vidconsole-uclass.c b/drivers/video/vidconsole-uclass.c
index 22d55df..5d06e51 100644
--- a/drivers/video/vidconsole-uclass.c
+++ b/drivers/video/vidconsole-uclass.c
@@ -11,6 +11,7 @@
#include <common.h>
#include <abuf.h>
+#include <charset.h>
#include <command.h>
#include <console.h>
#include <log.h>
@@ -20,7 +21,7 @@
#include <video_font.h> /* Bitmap font for code page 437 */
#include <linux/ctype.h>
-int vidconsole_putc_xy(struct udevice *dev, uint x, uint y, char ch)
+int vidconsole_putc_xy(struct udevice *dev, uint x, uint y, int ch)
{
struct vidconsole_ops *ops = vidconsole_get_ops(dev);
@@ -125,6 +126,7 @@
priv->xcur_frac = VID_TO_POS(x);
priv->xstart_frac = priv->xcur_frac;
priv->ycur = y;
+ vidconsole_entry_start(dev);
}
/**
@@ -134,8 +136,10 @@
* @row: new row
* @col: new column
*/
-static void set_cursor_position(struct vidconsole_priv *priv, int row, int col)
+static void set_cursor_position(struct udevice *dev, int row, int col)
{
+ struct vidconsole_priv *priv = dev_get_uclass_priv(dev);
+
/*
* Ensure we stay in the bounds of the screen.
*/
@@ -144,9 +148,7 @@
if (col >= priv->cols)
col = priv->cols - 1;
- priv->ycur = row * priv->y_charsize;
- priv->xcur_frac = priv->xstart_frac +
- VID_TO_POS(col * priv->x_charsize);
+ vidconsole_position_cursor(dev, col, row);
}
/**
@@ -193,7 +195,7 @@
int row = priv->row_saved;
int col = priv->col_saved;
- set_cursor_position(priv, row, col);
+ set_cursor_position(dev, row, col);
priv->escape = 0;
return;
}
@@ -255,7 +257,7 @@
if (row < 0)
row = 0;
/* Right and bottom overflows are handled in the callee. */
- set_cursor_position(priv, row, col);
+ set_cursor_position(dev, row, col);
break;
}
case 'H':
@@ -279,7 +281,7 @@
if (col)
--col;
- set_cursor_position(priv, row, col);
+ set_cursor_position(dev, row, col);
break;
}
@@ -426,8 +428,8 @@
priv->escape = 0;
}
-/* Put that actual character on the screen (using the CP437 code page). */
-static int vidconsole_output_glyph(struct udevice *dev, char ch)
+/* Put that actual character on the screen (using the UTF-32 code points). */
+static int vidconsole_output_glyph(struct udevice *dev, int ch)
{
struct vidconsole_priv *priv = dev_get_uclass_priv(dev);
int ret;
@@ -455,7 +457,7 @@
int vidconsole_put_char(struct udevice *dev, char ch)
{
struct vidconsole_priv *priv = dev_get_uclass_priv(dev);
- int ret;
+ int cp, ret;
if (priv->escape) {
vidconsole_escape_char(dev, ch);
@@ -489,7 +491,14 @@
priv->last_ch = 0;
break;
default:
- ret = vidconsole_output_glyph(dev, ch);
+ if (CONFIG_IS_ENABLED(CHARSET)) {
+ cp = utf8_to_utf32_stream(ch, priv->utf8_buf);
+ if (cp == 0)
+ return 0;
+ } else {
+ cp = ch;
+ }
+ ret = vidconsole_output_glyph(dev, cp);
if (ret < 0)
return ret;
break;
diff --git a/drivers/video/vidconsole_internal.h b/drivers/video/vidconsole_internal.h
index 0ec581b..bb0277e 100644
--- a/drivers/video/vidconsole_internal.h
+++ b/drivers/video/vidconsole_internal.h
@@ -6,6 +6,9 @@
* (C) Copyright 2023 Dzmitry Sankouski <dsankouski@gmail.com>
*/
+#include <charset.h>
+#include <config.h>
+
#define FLIPPED_DIRECTION 1
#define NORMAL_DIRECTION 0
@@ -142,3 +145,19 @@
* See details in video_console.h select_font function
**/
int console_simple_select_font(struct udevice *dev, const char *name, uint size);
+
+/**
+ * Internal function to convert Unicode code points to code page 437.
+ * Used by video consoles using bitmap fonts.
+ *
+ * @param codepoint Unicode code point
+ * @returns code page 437 character.
+ */
+static inline u8 console_utf_to_cp437(int codepoint)
+{
+ if (CONFIG_IS_ENABLED(CHARSET)) {
+ utf_to_cp(&codepoint, codepage_437);
+ return codepoint;
+ }
+ return codepoint;
+}
diff --git a/dts/upstream/Bindings/Makefile b/dts/upstream/Bindings/Makefile
index e799963..46ce251 100644
--- a/dts/upstream/Bindings/Makefile
+++ b/dts/upstream/Bindings/Makefile
@@ -28,7 +28,10 @@
find_all_cmd = find $(srctree)/$(src) \( -name '*.yaml' ! \
-name 'processed-schema*' \)
-find_cmd = $(find_all_cmd) | grep -F -e "$(subst :," -e ",$(DT_SCHEMA_FILES))"
+find_cmd = $(find_all_cmd) | \
+ sed 's|^$(srctree)/||' | \
+ grep -F -e "$(subst :," -e ",$(DT_SCHEMA_FILES))" | \
+ sed 's|^|$(srctree)/|'
CHK_DT_DOCS := $(shell $(find_cmd))
quiet_cmd_yamllint = LINT $(src)
diff --git a/dts/upstream/Bindings/arm/calxeda/l2ecc.yaml b/dts/upstream/Bindings/arm/calxeda/l2ecc.yaml
index a9fe012..76b65ea 100644
--- a/dts/upstream/Bindings/arm/calxeda/l2ecc.yaml
+++ b/dts/upstream/Bindings/arm/calxeda/l2ecc.yaml
@@ -16,7 +16,7 @@
properties:
compatible:
- const: "calxeda,hb-sregs-l2-ecc"
+ const: calxeda,hb-sregs-l2-ecc
reg:
maxItems: 1
diff --git a/dts/upstream/Bindings/arm/cpus.yaml b/dts/upstream/Bindings/arm/cpus.yaml
index ffd5263..cc5a21b 100644
--- a/dts/upstream/Bindings/arm/cpus.yaml
+++ b/dts/upstream/Bindings/arm/cpus.yaml
@@ -198,6 +198,7 @@
- qcom,kryo660
- qcom,kryo685
- qcom,kryo780
+ - qcom,oryon
- qcom,scorpion
enable-method:
diff --git a/dts/upstream/Bindings/arm/fsl.yaml b/dts/upstream/Bindings/arm/fsl.yaml
index 32b1958..228dcc5 100644
--- a/dts/upstream/Bindings/arm/fsl.yaml
+++ b/dts/upstream/Bindings/arm/fsl.yaml
@@ -967,6 +967,7 @@
- menlo,mx8menlo # Verdin iMX8M Mini Module on i.MX8MM Menlo board
- toradex,verdin-imx8mm-nonwifi-dahlia # Verdin iMX8M Mini Module on Dahlia
- toradex,verdin-imx8mm-nonwifi-dev # Verdin iMX8M Mini Module on Verdin Development Board
+ - toradex,verdin-imx8mm-nonwifi-mallow # Verdin iMX8M Mini Module on Mallow
- toradex,verdin-imx8mm-nonwifi-yavia # Verdin iMX8M Mini Module on Yavia
- const: toradex,verdin-imx8mm-nonwifi # Verdin iMX8M Mini Module without Wi-Fi / BT
- const: toradex,verdin-imx8mm # Verdin iMX8M Mini Module
@@ -977,6 +978,7 @@
- enum:
- toradex,verdin-imx8mm-wifi-dahlia # Verdin iMX8M Mini Wi-Fi / BT Module on Dahlia
- toradex,verdin-imx8mm-wifi-dev # Verdin iMX8M Mini Wi-Fi / BT M. on Verdin Development B.
+ - toradex,verdin-imx8mm-wifi-mallow # Verdin iMX8M Mini Wi-Fi / BT Module on Mallow
- toradex,verdin-imx8mm-wifi-yavia # Verdin iMX8M Mini Wi-Fi / BT Module on Yavia
- const: toradex,verdin-imx8mm-wifi # Verdin iMX8M Mini Wi-Fi / BT Module
- const: toradex,verdin-imx8mm # Verdin iMX8M Mini Module
@@ -1022,7 +1024,10 @@
- description: Variscite VAR-SOM-MX8MN based boards
items:
- - const: variscite,var-som-mx8mn-symphony
+ - enum:
+ - dimonoff,gateway-evk # i.MX8MN Dimonoff Gateway EVK Board
+ - rve,rve-gateway # i.MX8MN RVE Gateway Board
+ - variscite,var-som-mx8mn-symphony
- const: variscite,var-som-mx8mn
- const: fsl,imx8mn
@@ -1048,6 +1053,9 @@
- gateworks,imx8mp-gw73xx-2x # i.MX8MP Gateworks Board
- gateworks,imx8mp-gw74xx # i.MX8MP Gateworks Board
- gateworks,imx8mp-gw7905-2x # i.MX8MP Gateworks Board
+ - skov,imx8mp-skov-revb-hdmi # SKOV i.MX8MP climate control without panel
+ - skov,imx8mp-skov-revb-lt6 # SKOV i.MX8MP climate control with 7” panel
+ - skov,imx8mp-skov-revb-mi1010ait-1cp1 # SKOV i.MX8MP climate control with 10.1" panel
- toradex,verdin-imx8mp # Verdin iMX8M Plus Modules
- toradex,verdin-imx8mp-nonwifi # Verdin iMX8M Plus Modules without Wi-Fi / BT
- toradex,verdin-imx8mp-wifi # Verdin iMX8M Plus Wi-Fi / BT Modules
@@ -1100,6 +1108,7 @@
- enum:
- toradex,verdin-imx8mp-nonwifi-dahlia # Verdin iMX8M Plus Module on Dahlia
- toradex,verdin-imx8mp-nonwifi-dev # Verdin iMX8M Plus Module on Verdin Development Board
+ - toradex,verdin-imx8mp-nonwifi-mallow # Verdin iMX8M Plus Module on Mallow
- toradex,verdin-imx8mp-nonwifi-yavia # Verdin iMX8M Plus Module on Yavia
- const: toradex,verdin-imx8mp-nonwifi # Verdin iMX8M Plus Module without Wi-Fi / BT
- const: toradex,verdin-imx8mp # Verdin iMX8M Plus Module
@@ -1110,6 +1119,7 @@
- enum:
- toradex,verdin-imx8mp-wifi-dahlia # Verdin iMX8M Plus Wi-Fi / BT Module on Dahlia
- toradex,verdin-imx8mp-wifi-dev # Verdin iMX8M Plus Wi-Fi / BT M. on Verdin Development B.
+ - toradex,verdin-imx8mp-wifi-mallow # Verdin iMX8M Plus Wi-Fi / BT Module on Mallow
- toradex,verdin-imx8mp-wifi-yavia # Verdin iMX8M Plus Wi-Fi / BT Module on Yavia
- const: toradex,verdin-imx8mp-wifi # Verdin iMX8M Plus Wi-Fi / BT Module
- const: toradex,verdin-imx8mp # Verdin iMX8M Plus Module
@@ -1476,6 +1486,16 @@
- const: solidrun,lx2162a-som
- const: fsl,lx2160a
+ - description:
+ TQ-Systems TQMLX2160A is a series of socketable SOM featuring
+ LX2160A system-on-chip variants. MBLX2160A mainboard can be used a
+ starterkit.
+ items:
+ - enum:
+ - tq,lx2160a-tqmlx2160a-mblx2160a
+ - const: tq,lx2160a-tqmlx2160a
+ - const: fsl,lx2160a
+
- description: S32G2 based Boards
items:
- enum:
diff --git a/dts/upstream/Bindings/arm/google.yaml b/dts/upstream/Bindings/arm/google.yaml
new file mode 100644
index 0000000..e20b5c9
--- /dev/null
+++ b/dts/upstream/Bindings/arm/google.yaml
@@ -0,0 +1,53 @@
+# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/arm/google.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Google Tensor platforms
+
+maintainers:
+ - Peter Griffin <peter.griffin@linaro.org>
+
+description: |
+ ARM platforms using SoCs designed by Google branded "Tensor" used in Pixel
+ devices.
+
+ Currently upstream this is devices using "gs101" SoC which is found in Pixel
+ 6, Pixel 6 Pro and Pixel 6a.
+
+ Google have a few different names for the SoC:
+ - Marketing name ("Tensor")
+ - Codename ("Whitechapel")
+ - SoC ID ("gs101")
+ - Die ID ("S5P9845")
+
+ Likewise there are a couple of names for the actual device
+ - Marketing name ("Pixel 6")
+ - Codename ("Oriole")
+
+ Devicetrees should use the lowercased SoC ID and lowercased board codename,
+ e.g. gs101 and gs101-oriole.
+
+properties:
+ $nodename:
+ const: '/'
+ compatible:
+ oneOf:
+ - description: Google Pixel 6 / Oriole
+ items:
+ - enum:
+ - google,gs101-oriole
+ - const: google,gs101
+
+ # Bootloader requires empty ect node to be present
+ ect:
+ type: object
+ additionalProperties: false
+
+required:
+ - ect
+
+additionalProperties: true
+
+...
diff --git a/dts/upstream/Bindings/arm/hisilicon/controller/sysctrl.yaml b/dts/upstream/Bindings/arm/hisilicon/controller/sysctrl.yaml
index 5a53d43..7a221e1 100644
--- a/dts/upstream/Bindings/arm/hisilicon/controller/sysctrl.yaml
+++ b/dts/upstream/Bindings/arm/hisilicon/controller/sysctrl.yaml
@@ -82,6 +82,23 @@
ranges: true
+patternProperties:
+ '^clock@':
+ type: object
+ additionalProperties: false
+
+ properties:
+ compatible:
+ enum:
+ - hisilicon,hi3620-clock
+ - hisilicon,hi3620-mmc-clock
+
+ reg:
+ maxItems: 1
+
+ '#clock-cells':
+ const: 1
+
required:
- compatible
- reg
diff --git a/dts/upstream/Bindings/arm/marvell/armada-7k-8k.yaml b/dts/upstream/Bindings/arm/marvell/armada-7k-8k.yaml
index 52d7852..16d2e13 100644
--- a/dts/upstream/Bindings/arm/marvell/armada-7k-8k.yaml
+++ b/dts/upstream/Bindings/arm/marvell/armada-7k-8k.yaml
@@ -60,4 +60,26 @@
- const: marvell,armada-ap807-quad
- const: marvell,armada-ap807
+ - description:
+ Alleycat5X (98DX35xx) Reference Design as COM Express Carrier plus
+ Armada CN9130 COM Express CPU module
+ items:
+ - const: marvell,cn9130-ac5x-carrier
+ - const: marvell,rd-ac5x-carrier
+ - const: marvell,cn9130-cpu-module
+ - const: marvell,cn9130
+ - const: marvell,armada-ap807-quad
+ - const: marvell,armada-ap807
+
+ - description:
+ Alleycat5X (98DX35xx) Reference Design as COM Express Carrier plus
+ Armada CN9131 COM Express CPU module
+ items:
+ - const: marvell,cn9131-ac5x-carrier
+ - const: marvell,rd-ac5x-carrier
+ - const: marvell,cn9131-cpu-module
+ - const: marvell,cn9131
+ - const: marvell,armada-ap807-quad
+ - const: marvell,armada-ap807
+
additionalProperties: true
diff --git a/dts/upstream/Bindings/arm/mediatek.yaml b/dts/upstream/Bindings/arm/mediatek.yaml
index a5999b3..6f2f64a 100644
--- a/dts/upstream/Bindings/arm/mediatek.yaml
+++ b/dts/upstream/Bindings/arm/mediatek.yaml
@@ -176,6 +176,10 @@
- const: mediatek,mt8186
- items:
- enum:
+ - mediatek,mt8188-evb
+ - const: mediatek,mt8188
+ - items:
+ - enum:
- mediatek,mt8192-evb
- const: mediatek,mt8192
- items:
@@ -235,6 +239,13 @@
items:
- const: google,kappa
- const: mediatek,mt8183
+ - description: Google Katsu (ASUS Chromebook Detachable CZ1)
+ items:
+ - enum:
+ - google,katsu-sku32
+ - google,katsu-sku38
+ - const: google,katsu
+ - const: mediatek,mt8183
- description: Google Kodama (Lenovo 10e Chromebook Tablet)
items:
- enum:
@@ -244,6 +255,20 @@
- google,kodama-sku32
- const: google,kodama
- const: mediatek,mt8183
+ - description: Google Makomo (Lenovo 100e Chromebook 2nd Gen MTK 2)
+ items:
+ - enum:
+ - google,makomo-sku0
+ - google,makomo-sku1
+ - const: google,makomo
+ - const: mediatek,mt8183
+ - description: Google Pico (Acer Chromebook Spin 311)
+ items:
+ - enum:
+ - google,pico-sku1
+ - google,pico-sku2
+ - const: google,pico
+ - const: mediatek,mt8183
- description: Google Willow (Acer Chromebook 311 C722/C722T)
items:
- enum:
diff --git a/dts/upstream/Bindings/arm/mediatek/mediatek,audsys.txt b/dts/upstream/Bindings/arm/mediatek/mediatek,audsys.txt
deleted file mode 100644
index 699776b..0000000
--- a/dts/upstream/Bindings/arm/mediatek/mediatek,audsys.txt
+++ /dev/null
@@ -1,39 +0,0 @@
-MediaTek AUDSYS controller
-============================
-
-The MediaTek AUDSYS controller provides various clocks to the system.
-
-Required Properties:
-
-- compatible: Should be one of:
- - "mediatek,mt2701-audsys", "syscon"
- - "mediatek,mt6765-audsys", "syscon"
- - "mediatek,mt6779-audio", "syscon"
- - "mediatek,mt7622-audsys", "syscon"
- - "mediatek,mt7623-audsys", "mediatek,mt2701-audsys", "syscon"
- - "mediatek,mt8167-audiosys", "syscon"
- - "mediatek,mt8183-audiosys", "syscon"
- - "mediatek,mt8192-audsys", "syscon"
- - "mediatek,mt8516-audsys", "syscon"
-- #clock-cells: Must be 1
-
-The AUDSYS controller uses the common clk binding from
-Documentation/devicetree/bindings/clock/clock-bindings.txt
-The available clocks are defined in dt-bindings/clock/mt*-clk.h.
-
-Required sub-nodes:
--------
-For common binding part and usage, refer to
-../sonud/mt2701-afe-pcm.txt.
-
-Example:
-
- audsys: clock-controller@11220000 {
- compatible = "mediatek,mt7622-audsys", "syscon";
- reg = <0 0x11220000 0 0x2000>;
- #clock-cells = <1>;
-
- afe: audio-controller {
- ...
- };
- };
diff --git a/dts/upstream/Bindings/arm/mediatek/mediatek,audsys.yaml b/dts/upstream/Bindings/arm/mediatek/mediatek,audsys.yaml
new file mode 100644
index 0000000..45d4a66
--- /dev/null
+++ b/dts/upstream/Bindings/arm/mediatek/mediatek,audsys.yaml
@@ -0,0 +1,153 @@
+# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/arm/mediatek/mediatek,audsys.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: MediaTek AUDSYS controller
+
+maintainers:
+ - Eugen Hristev <eugen.hristev@collabora.com>
+
+description:
+ The MediaTek AUDSYS controller provides various clocks to the system.
+
+properties:
+ compatible:
+ oneOf:
+ - items:
+ - enum:
+ - mediatek,mt2701-audsys
+ - mediatek,mt6765-audsys
+ - mediatek,mt6779-audsys
+ - mediatek,mt7622-audsys
+ - mediatek,mt8167-audsys
+ - mediatek,mt8173-audsys
+ - mediatek,mt8183-audsys
+ - mediatek,mt8186-audsys
+ - mediatek,mt8192-audsys
+ - mediatek,mt8516-audsys
+ - const: syscon
+ - items:
+ # Special case for mt7623 for backward compatibility
+ - const: mediatek,mt7623-audsys
+ - const: mediatek,mt2701-audsys
+ - const: syscon
+
+ reg:
+ maxItems: 1
+
+ '#clock-cells':
+ const: 1
+
+ audio-controller:
+ $ref: /schemas/sound/mediatek,mt2701-audio.yaml#
+ type: object
+
+required:
+ - compatible
+ - '#clock-cells'
+
+additionalProperties: false
+
+examples:
+ - |
+ #include <dt-bindings/interrupt-controller/arm-gic.h>
+ #include <dt-bindings/interrupt-controller/irq.h>
+ #include <dt-bindings/power/mt2701-power.h>
+ #include <dt-bindings/clock/mt2701-clk.h>
+ soc {
+ #address-cells = <2>;
+ #size-cells = <2>;
+ audsys: clock-controller@11220000 {
+ compatible = "mediatek,mt7622-audsys", "syscon";
+ reg = <0 0x11220000 0 0x2000>;
+ #clock-cells = <1>;
+
+ afe: audio-controller {
+ compatible = "mediatek,mt2701-audio";
+ interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_LOW>,
+ <GIC_SPI 132 IRQ_TYPE_LEVEL_LOW>;
+ interrupt-names = "afe", "asys";
+ power-domains = <&scpsys MT2701_POWER_DOMAIN_IFR_MSC>;
+
+ clocks = <&infracfg CLK_INFRA_AUDIO>,
+ <&topckgen CLK_TOP_AUD_MUX1_SEL>,
+ <&topckgen CLK_TOP_AUD_MUX2_SEL>,
+ <&topckgen CLK_TOP_AUD_48K_TIMING>,
+ <&topckgen CLK_TOP_AUD_44K_TIMING>,
+ <&topckgen CLK_TOP_AUD_K1_SRC_SEL>,
+ <&topckgen CLK_TOP_AUD_K2_SRC_SEL>,
+ <&topckgen CLK_TOP_AUD_K3_SRC_SEL>,
+ <&topckgen CLK_TOP_AUD_K4_SRC_SEL>,
+ <&topckgen CLK_TOP_AUD_K1_SRC_DIV>,
+ <&topckgen CLK_TOP_AUD_K2_SRC_DIV>,
+ <&topckgen CLK_TOP_AUD_K3_SRC_DIV>,
+ <&topckgen CLK_TOP_AUD_K4_SRC_DIV>,
+ <&topckgen CLK_TOP_AUD_I2S1_MCLK>,
+ <&topckgen CLK_TOP_AUD_I2S2_MCLK>,
+ <&topckgen CLK_TOP_AUD_I2S3_MCLK>,
+ <&topckgen CLK_TOP_AUD_I2S4_MCLK>,
+ <&audsys CLK_AUD_I2SO1>,
+ <&audsys CLK_AUD_I2SO2>,
+ <&audsys CLK_AUD_I2SO3>,
+ <&audsys CLK_AUD_I2SO4>,
+ <&audsys CLK_AUD_I2SIN1>,
+ <&audsys CLK_AUD_I2SIN2>,
+ <&audsys CLK_AUD_I2SIN3>,
+ <&audsys CLK_AUD_I2SIN4>,
+ <&audsys CLK_AUD_ASRCO1>,
+ <&audsys CLK_AUD_ASRCO2>,
+ <&audsys CLK_AUD_ASRCO3>,
+ <&audsys CLK_AUD_ASRCO4>,
+ <&audsys CLK_AUD_AFE>,
+ <&audsys CLK_AUD_AFE_CONN>,
+ <&audsys CLK_AUD_A1SYS>,
+ <&audsys CLK_AUD_A2SYS>,
+ <&audsys CLK_AUD_AFE_MRGIF>;
+
+ clock-names = "infra_sys_audio_clk",
+ "top_audio_mux1_sel",
+ "top_audio_mux2_sel",
+ "top_audio_a1sys_hp",
+ "top_audio_a2sys_hp",
+ "i2s0_src_sel",
+ "i2s1_src_sel",
+ "i2s2_src_sel",
+ "i2s3_src_sel",
+ "i2s0_src_div",
+ "i2s1_src_div",
+ "i2s2_src_div",
+ "i2s3_src_div",
+ "i2s0_mclk_en",
+ "i2s1_mclk_en",
+ "i2s2_mclk_en",
+ "i2s3_mclk_en",
+ "i2so0_hop_ck",
+ "i2so1_hop_ck",
+ "i2so2_hop_ck",
+ "i2so3_hop_ck",
+ "i2si0_hop_ck",
+ "i2si1_hop_ck",
+ "i2si2_hop_ck",
+ "i2si3_hop_ck",
+ "asrc0_out_ck",
+ "asrc1_out_ck",
+ "asrc2_out_ck",
+ "asrc3_out_ck",
+ "audio_afe_pd",
+ "audio_afe_conn_pd",
+ "audio_a1sys_pd",
+ "audio_a2sys_pd",
+ "audio_mrgif_pd";
+
+ assigned-clocks = <&topckgen CLK_TOP_AUD_MUX1_SEL>,
+ <&topckgen CLK_TOP_AUD_MUX2_SEL>,
+ <&topckgen CLK_TOP_AUD_MUX1_DIV>,
+ <&topckgen CLK_TOP_AUD_MUX2_DIV>;
+ assigned-clock-parents = <&topckgen CLK_TOP_AUD1PLL_98M>,
+ <&topckgen CLK_TOP_AUD2PLL_90M>;
+ assigned-clock-rates = <0>, <0>, <49152000>, <45158400>;
+ };
+ };
+ };
diff --git a/dts/upstream/Bindings/arm/mediatek/mediatek,ethsys.txt b/dts/upstream/Bindings/arm/mediatek/mediatek,ethsys.txt
deleted file mode 100644
index eccd4b7..0000000
--- a/dts/upstream/Bindings/arm/mediatek/mediatek,ethsys.txt
+++ /dev/null
@@ -1,29 +0,0 @@
-Mediatek ethsys controller
-============================
-
-The Mediatek ethsys controller provides various clocks to the system.
-
-Required Properties:
-
-- compatible: Should be:
- - "mediatek,mt2701-ethsys", "syscon"
- - "mediatek,mt7622-ethsys", "syscon"
- - "mediatek,mt7623-ethsys", "mediatek,mt2701-ethsys", "syscon"
- - "mediatek,mt7629-ethsys", "syscon"
- - "mediatek,mt7981-ethsys", "syscon"
- - "mediatek,mt7986-ethsys", "syscon"
-- #clock-cells: Must be 1
-- #reset-cells: Must be 1
-
-The ethsys controller uses the common clk binding from
-Documentation/devicetree/bindings/clock/clock-bindings.txt
-The available clocks are defined in dt-bindings/clock/mt*-clk.h.
-
-Example:
-
-ethsys: clock-controller@1b000000 {
- compatible = "mediatek,mt2701-ethsys", "syscon";
- reg = <0 0x1b000000 0 0x1000>;
- #clock-cells = <1>;
- #reset-cells = <1>;
-};
diff --git a/dts/upstream/Bindings/arm/mediatek/mediatek,infracfg.yaml b/dts/upstream/Bindings/arm/mediatek/mediatek,infracfg.yaml
index ea98043..230b518 100644
--- a/dts/upstream/Bindings/arm/mediatek/mediatek,infracfg.yaml
+++ b/dts/upstream/Bindings/arm/mediatek/mediatek,infracfg.yaml
@@ -30,6 +30,7 @@
- mediatek,mt7629-infracfg
- mediatek,mt7981-infracfg
- mediatek,mt7986-infracfg
+ - mediatek,mt7988-infracfg
- mediatek,mt8135-infracfg
- mediatek,mt8167-infracfg
- mediatek,mt8173-infracfg
diff --git a/dts/upstream/Bindings/arm/mediatek/mediatek,mmsys.yaml b/dts/upstream/Bindings/arm/mediatek/mediatek,mmsys.yaml
index 536f5a5..b3c6888 100644
--- a/dts/upstream/Bindings/arm/mediatek/mediatek,mmsys.yaml
+++ b/dts/upstream/Bindings/arm/mediatek/mediatek,mmsys.yaml
@@ -32,6 +32,9 @@
- mediatek,mt8183-mmsys
- mediatek,mt8186-mmsys
- mediatek,mt8188-vdosys0
+ - mediatek,mt8188-vdosys1
+ - mediatek,mt8188-vppsys0
+ - mediatek,mt8188-vppsys1
- mediatek,mt8192-mmsys
- mediatek,mt8195-vdosys1
- mediatek,mt8195-vppsys0
diff --git a/dts/upstream/Bindings/arm/mediatek/mediatek,pericfg.yaml b/dts/upstream/Bindings/arm/mediatek/mediatek,pericfg.yaml
index 26158d0..33c94c4 100644
--- a/dts/upstream/Bindings/arm/mediatek/mediatek,pericfg.yaml
+++ b/dts/upstream/Bindings/arm/mediatek/mediatek,pericfg.yaml
@@ -28,6 +28,7 @@
- mediatek,mt8173-pericfg
- mediatek,mt8183-pericfg
- mediatek,mt8186-pericfg
+ - mediatek,mt8188-pericfg
- mediatek,mt8195-pericfg
- mediatek,mt8516-pericfg
- const: syscon
diff --git a/dts/upstream/Bindings/arm/msm/qcom,idle-state.txt b/dts/upstream/Bindings/arm/msm/qcom,idle-state.txt
deleted file mode 100644
index 606b4b1..0000000
--- a/dts/upstream/Bindings/arm/msm/qcom,idle-state.txt
+++ /dev/null
@@ -1,84 +0,0 @@
-QCOM Idle States for cpuidle driver
-
-ARM provides idle-state node to define the cpuidle states, as defined in [1].
-cpuidle-qcom is the cpuidle driver for Qualcomm SoCs and uses these idle
-states. Idle states have different enter/exit latency and residency values.
-The idle states supported by the QCOM SoC are defined as -
-
- * Standby
- * Retention
- * Standalone Power Collapse (Standalone PC or SPC)
- * Power Collapse (PC)
-
-Standby: Standby does a little more in addition to architectural clock gating.
-When the WFI instruction is executed the ARM core would gate its internal
-clocks. In addition to gating the clocks, QCOM cpus use this instruction as a
-trigger to execute the SPM state machine. The SPM state machine waits for the
-interrupt to trigger the core back in to active. This triggers the cache
-hierarchy to enter standby states, when all cpus are idle. An interrupt brings
-the SPM state machine out of its wait, the next step is to ensure that the
-cache hierarchy is also out of standby, and then the cpu is allowed to resume
-execution. This state is defined as a generic ARM WFI state by the ARM cpuidle
-driver and is not defined in the DT. The SPM state machine should be
-configured to execute this state by default and after executing every other
-state below.
-
-Retention: Retention is a low power state where the core is clock gated and
-the memory and the registers associated with the core are retained. The
-voltage may be reduced to the minimum value needed to keep the processor
-registers active. The SPM should be configured to execute the retention
-sequence and would wait for interrupt, before restoring the cpu to execution
-state. Retention may have a slightly higher latency than Standby.
-
-Standalone PC: A cpu can power down and warmboot if there is a sufficient time
-between the time it enters idle and the next known wake up. SPC mode is used
-to indicate a core entering a power down state without consulting any other
-cpu or the system resources. This helps save power only on that core. The SPM
-sequence for this idle state is programmed to power down the supply to the
-core, wait for the interrupt, restore power to the core, and ensure the
-system state including cache hierarchy is ready before allowing core to
-resume. Applying power and resetting the core causes the core to warmboot
-back into Elevation Level (EL) which trampolines the control back to the
-kernel. Entering a power down state for the cpu, needs to be done by trapping
-into a EL. Failing to do so, would result in a crash enforced by the warm boot
-code in the EL for the SoC. On SoCs with write-back L1 cache, the cache has to
-be flushed in s/w, before powering down the core.
-
-Power Collapse: This state is similar to the SPC mode, but distinguishes
-itself in that the cpu acknowledges and permits the SoC to enter deeper sleep
-modes. In a hierarchical power domain SoC, this means L2 and other caches can
-be flushed, system bus, clocks - lowered, and SoC main XO clock gated and
-voltages reduced, provided all cpus enter this state. Since the span of low
-power modes possible at this state is vast, the exit latency and the residency
-of this low power mode would be considered high even though at a cpu level,
-this essentially is cpu power down. The SPM in this state also may handshake
-with the Resource power manager (RPM) processor in the SoC to indicate a
-complete application processor subsystem shut down.
-
-The idle-state for QCOM SoCs are distinguished by the compatible property of
-the idle-states device node.
-
-The devicetree representation of the idle state should be -
-
-Required properties:
-
-- compatible: Must be one of -
- "qcom,idle-state-ret",
- "qcom,idle-state-spc",
- "qcom,idle-state-pc",
- and "arm,idle-state".
-
-Other required and optional properties are specified in [1].
-
-Example:
-
- idle-states {
- CPU_SPC: spc {
- compatible = "qcom,idle-state-spc", "arm,idle-state";
- entry-latency-us = <150>;
- exit-latency-us = <200>;
- min-residency-us = <2000>;
- };
- };
-
-[1]. Documentation/devicetree/bindings/cpu/idle-states.yaml
diff --git a/dts/upstream/Bindings/arm/qcom,coresight-remote-etm.yaml b/dts/upstream/Bindings/arm/qcom,coresight-remote-etm.yaml
new file mode 100644
index 0000000..4fd5752
--- /dev/null
+++ b/dts/upstream/Bindings/arm/qcom,coresight-remote-etm.yaml
@@ -0,0 +1,51 @@
+# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/arm/qcom,coresight-remote-etm.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Qualcomm Coresight Remote ETM(Embedded Trace Macrocell)
+
+maintainers:
+ - Jinlong Mao <quic_jinlmao@quicinc.com>
+ - Tao Zhang <quic_taozha@quicinc.com>
+
+description:
+ Support for ETM trace collection on remote processor using coresight
+ framework. Enabling this will allow turning on ETM tracing on remote
+ processor like modem processor via sysfs and collecting the trace
+ via coresight TMC sinks.
+
+properties:
+ compatible:
+ const: qcom,coresight-remote-etm
+
+ out-ports:
+ $ref: /schemas/graph.yaml#/properties/ports
+ additionalProperties: false
+
+ properties:
+ port:
+ description: Output connection to the CoreSight Trace bus.
+ $ref: /schemas/graph.yaml#/properties/port
+
+required:
+ - compatible
+ - out-ports
+
+additionalProperties: false
+
+examples:
+ - |
+ etm {
+ compatible = "qcom,coresight-remote-etm";
+
+ out-ports {
+ port {
+ modem_etm0_out_funnel_modem: endpoint {
+ remote-endpoint = <&funnel_modem_in_modem_etm0>;
+ };
+ };
+ };
+ };
+...
diff --git a/dts/upstream/Bindings/arm/qcom,coresight-tpdm.yaml b/dts/upstream/Bindings/arm/qcom,coresight-tpdm.yaml
index 3bad47b..61ddc3b 100644
--- a/dts/upstream/Bindings/arm/qcom,coresight-tpdm.yaml
+++ b/dts/upstream/Bindings/arm/qcom,coresight-tpdm.yaml
@@ -44,6 +44,23 @@
minItems: 1
maxItems: 2
+ qcom,dsb-element-size:
+ description:
+ Specifies the DSB(Discrete Single Bit) element size supported by
+ the monitor. The associated aggregator will read this size before it
+ is enabled. DSB element size currently only supports 32-bit and 64-bit.
+ $ref: /schemas/types.yaml#/definitions/uint8
+ enum: [32, 64]
+
+ qcom,dsb-msrs-num:
+ description:
+ Specifies the number of DSB(Discrete Single Bit) MSR(mux select register)
+ registers supported by the monitor. If this property is not configured
+ or set to 0, it means this DSB TPDM doesn't support MSR.
+ $ref: /schemas/types.yaml#/definitions/uint32
+ minimum: 0
+ maximum: 32
+
clocks:
maxItems: 1
@@ -77,6 +94,9 @@
compatible = "qcom,coresight-tpdm", "arm,primecell";
reg = <0x0684c000 0x1000>;
+ qcom,dsb-element-size = /bits/ 8 <32>;
+ qcom,dsb-msrs-num = <16>;
+
clocks = <&aoss_qmp>;
clock-names = "apb_pclk";
diff --git a/dts/upstream/Bindings/arm/qcom-soc.yaml b/dts/upstream/Bindings/arm/qcom-soc.yaml
index 97621c9..d0751a5 100644
--- a/dts/upstream/Bindings/arm/qcom-soc.yaml
+++ b/dts/upstream/Bindings/arm/qcom-soc.yaml
@@ -23,7 +23,7 @@
select:
properties:
compatible:
- pattern: "^qcom,.*(apq|ipq|mdm|msm|qcm|qcs|sa|sc|sdm|sdx|sm)[0-9]+.*$"
+ pattern: "^qcom,.*(apq|ipq|mdm|msm|qcm|qcs|q[dr]u|sa|sc|sd[amx]|sm|x1e)[0-9]+.*$"
required:
- compatible
@@ -31,17 +31,17 @@
compatible:
oneOf:
# Preferred naming style for compatibles of SoC components:
- - pattern: "^qcom,(apq|ipq|mdm|msm|qcm|qcs|sa|sc|sdm|sdx|sm)[0-9]+(pro)?-.*$"
+ - pattern: "^qcom,(apq|ipq|mdm|msm|qcm|qcs|q[dr]u|sa|sc|sd[amx]|sm|x1e)[0-9]+(pro)?-.*$"
- pattern: "^qcom,(sa|sc)8[0-9]+[a-z][a-z]?-.*$"
# Legacy namings - variations of existing patterns/compatibles are OK,
# but do not add completely new entries to these:
- - pattern: "^qcom,[ak]pss-wdt-(apq|ipq|mdm|msm|qcm|qcs|sa|sc|sdm|sdx|sm)[0-9]+.*$"
- - pattern: "^qcom,gcc-(apq|ipq|mdm|msm|qcm|qcs|sa|sc|sdm|sdx|sm)[0-9]+.*$"
- - pattern: "^qcom,mmcc-(apq|ipq|mdm|msm|qcm|qcs|sa|sc|sdm|sdx|sm)[0-9]+.*$"
- - pattern: "^qcom,pcie-(apq|ipq|mdm|msm|qcm|qcs|sa|sc|sdm|sdx|sm)[0-9]+.*$"
- - pattern: "^qcom,rpm-(apq|ipq|mdm|msm|qcm|qcs|sa|sc|sdm|sdx|sm)[0-9]+.*$"
- - pattern: "^qcom,scm-(apq|ipq|mdm|msm|qcm|qcs|sa|sc|sdm|sdx|sm)[0-9]+.*$"
+ - pattern: "^qcom,[ak]pss-wdt-(apq|ipq|mdm|msm|qcm|qcs|q[dr]u|sa|sc|sd[amx]|sm)[0-9]+.*$"
+ - pattern: "^qcom,gcc-(apq|ipq|mdm|msm|qcm|qcs|q[dr]u|sa|sc|sd[amx]|sm)[0-9]+.*$"
+ - pattern: "^qcom,mmcc-(apq|ipq|mdm|msm|qcm|qcs|q[dr]u|sa|sc|sd[amx]|sm)[0-9]+.*$"
+ - pattern: "^qcom,pcie-(apq|ipq|mdm|msm|qcm|qcs|q[dr]u|sa|sc|sd[amx]|sm|x1e)[0-9]+.*$"
+ - pattern: "^qcom,rpm-(apq|ipq|mdm|msm|qcm|qcs|q[dr]u|sa|sc|sd[amx]|sm)[0-9]+.*$"
+ - pattern: "^qcom,scm-(apq|ipq|mdm|msm|qcm|qcs|q[dr]u|sa|sc|sd[amx]|sm|x1e)[0-9]+.*$"
- enum:
- qcom,dsi-ctrl-6g-qcm2290
- qcom,gpucc-sdm630
diff --git a/dts/upstream/Bindings/arm/qcom.yaml b/dts/upstream/Bindings/arm/qcom.yaml
index 7f80f48..1a5fb88 100644
--- a/dts/upstream/Bindings/arm/qcom.yaml
+++ b/dts/upstream/Bindings/arm/qcom.yaml
@@ -87,29 +87,18 @@
sm8350
sm8450
sm8550
+ sm8650
+ x1e80100
The 'board' element must be one of the following strings:
adp
- ap-al02-c2
- ap-al02-c6
- ap-al02-c7
- ap-al02-c8
- ap-al02-c9
- ap-mi01.2
- ap-mi01.3
- ap-mi01.6
- ap-mi01.9
cdp
- cp01-c1
dragonboard
- hk01
- hk10-c1
- hk10-c2
idp
liquid
- rdp432-c2
mtp
+ qcp
qrd
rb2
ride
@@ -138,7 +127,7 @@
There are many devices in the list below that run the standard ChromeOS
bootloader setup and use the open source depthcharge bootloader to boot the
OS. These devices do not use the scheme described above. For details, see:
- https://docs.kernel.org/arm/google/chromebook-boot-flow.html
+ https://docs.kernel.org/arch/arm/google/chromebook-boot-flow.html
properties:
$nodename:
@@ -186,11 +175,24 @@
- items:
- enum:
+ - microsoft,dempsey
+ - microsoft,makepeace
+ - microsoft,moneypenny
- samsung,s3ve3g
- const: qcom,msm8226
- items:
- enum:
+ - htc,memul
+ - microsoft,superman-lte
+ - microsoft,tesla
+ - motorola,peregrine
+ - const: qcom,msm8926
+ - const: qcom,msm8226
+
+ - items:
+ - enum:
+ - huawei,kiwi
- longcheer,l9100
- samsung,a7
- sony,kanuti-tulip
@@ -397,6 +399,8 @@
- items:
- enum:
- fairphone,fp5
+ - qcom,qcm6490-idp
+ - qcom,qcs6490-rb3gen2
- const: qcom,qcm6490
- description: Qualcomm Technologies, Inc. Distributed Unit 1000 platform
@@ -1009,6 +1013,7 @@
- sony,pdx203-generic
- sony,pdx206-generic
- xiaomi,elish
+ - xiaomi,pipa
- const: qcom,sm8250
- items:
@@ -1034,6 +1039,18 @@
- qcom,sm8550-qrd
- const: qcom,sm8550
+ - items:
+ - enum:
+ - qcom,sm8650-mtp
+ - qcom,sm8650-qrd
+ - const: qcom,sm8650
+
+ - items:
+ - enum:
+ - qcom,x1e80100-crd
+ - qcom,x1e80100-qcp
+ - const: qcom,x1e80100
+
# Board compatibles go above
qcom,msm-id:
diff --git a/dts/upstream/Bindings/arm/rockchip.yaml b/dts/upstream/Bindings/arm/rockchip.yaml
index 5f7c6c4..5cf5cbe 100644
--- a/dts/upstream/Bindings/arm/rockchip.yaml
+++ b/dts/upstream/Bindings/arm/rockchip.yaml
@@ -30,9 +30,11 @@
- const: amarula,vyasa-rk3288
- const: rockchip,rk3288
- - description: Anbernic RG351M
+ - description: Anbernic RK3326 Handheld Gaming Console
items:
- - const: anbernic,rg351m
+ - enum:
+ - anbernic,rg351m
+ - anbernic,rg351v
- const: rockchip,rk3326
- description: Anbernic RG353P
@@ -95,22 +97,30 @@
- const: chipspark,rayeager-px2
- const: rockchip,rk3066a
+ - description: Cool Pi Compute Module 5(CM5) EVB
+ items:
+ - enum:
+ - coolpi,pi-cm5-evb
+ - const: coolpi,pi-cm5
+ - const: rockchip,rk3588
+
+ - description: Cool Pi 4 Model B
+ items:
+ - const: coolpi,pi-4b
+ - const: rockchip,rk3588s
+
- description: Edgeble Neural Compute Module 2(Neu2) SoM based boards
items:
- const: edgeble,neural-compute-module-2-io # Edgeble Neural Compute Module 2 IO Board
- const: edgeble,neural-compute-module-2 # Edgeble Neural Compute Module 2 SoM
- const: rockchip,rv1126
- - description: Edgeble Neural Compute Module 6(Neu6) Model A SoM based boards
- items:
- - const: edgeble,neural-compute-module-6a-io # Edgeble Neural Compute Module 6A IO Board
- - const: edgeble,neural-compute-module-6a # Edgeble Neural Compute Module 6A SoM
- - const: rockchip,rk3588
-
- - description: Edgeble Neural Compute Module 6(Neu6) Model B SoM based boards
+ - description: Edgeble Neural Compute Module 6(Neu6) SoM based boards
items:
- - const: edgeble,neural-compute-module-6b-io # Edgeble Neural Compute Module 6B IO Board
- - const: edgeble,neural-compute-module-6b # Edgeble Neural Compute Module 6B SoM
+ - const: edgeble,neural-compute-module-6a-io # Edgeble NCM6A-IO Board
+ - enum:
+ - edgeble,neural-compute-module-6a # Edgeble Neural Compute Module 6A SoM
+ - edgeble,neural-compute-module-6b # Edgeble Neural Compute Module 6B SoM
- const: rockchip,rk3588
- description: Elgin RV1108 R1
@@ -237,6 +247,11 @@
- const: geekbuying,geekbox
- const: rockchip,rk3368
+ - description: Geniatech XPI-3128
+ items:
+ - const: geniatech,xpi-3128
+ - const: rockchip,rk3128
+
- description: Google Bob (Asus Chromebook Flip C101PA)
items:
- const: google,bob-rev13
@@ -674,9 +689,12 @@
- const: pine64,soquartz
- const: rockchip,rk3566
- - description: Powkiddy RGB30
+ - description: Powkiddy RK3566 Handheld Gaming Console
items:
- - const: powkiddy,rgb30
+ - enum:
+ - powkiddy,rgb30
+ - powkiddy,rk2023
+ - powkiddy,x55
- const: rockchip,rk3566
- description: Radxa Compute Module 3(CM3)
@@ -875,6 +893,11 @@
- const: tsd,rk3399-puma-haikou
- const: rockchip,rk3399
+ - description: Theobroma Systems RK3588-SBC Jaguar
+ items:
+ - const: tsd,rk3588-jaguar
+ - const: rockchip,rk3588
+
- description: Tronsmart Orion R68 Meta
items:
- const: tronsmart,orion-r68-meta
@@ -922,6 +945,13 @@
- const: rockchip,rk3568-bpi-r2pro
- const: rockchip,rk3568
+ - description: Sonoff iHost Smart Home Hub
+ items:
+ - const: itead,sonoff-ihost
+ - enum:
+ - rockchip,rv1126
+ - rockchip,rv1109
+
additionalProperties: true
...
diff --git a/dts/upstream/Bindings/arm/samsung/samsung-boards.yaml b/dts/upstream/Bindings/arm/samsung/samsung-boards.yaml
index e3ffd81..01dcbd8 100644
--- a/dts/upstream/Bindings/arm/samsung/samsung-boards.yaml
+++ b/dts/upstream/Bindings/arm/samsung/samsung-boards.yaml
@@ -230,6 +230,12 @@
- samsung,exynosautov9-sadk # Samsung Exynos Auto v9 SADK
- const: samsung,exynosautov9
+ - description: Exynos Auto v920 based boards
+ items:
+ - enum:
+ - samsung,exynosautov920-sadk # Samsung Exynos Auto v920 SADK
+ - const: samsung,exynosautov920
+
required:
- compatible
diff --git a/dts/upstream/Bindings/arm/sprd/sprd.yaml b/dts/upstream/Bindings/arm/sprd/sprd.yaml
index eaa67b8..40fc3c8 100644
--- a/dts/upstream/Bindings/arm/sprd/sprd.yaml
+++ b/dts/upstream/Bindings/arm/sprd/sprd.yaml
@@ -35,6 +35,11 @@
- sprd,ums512-1h10
- const: sprd,ums512
+ - items:
+ - enum:
+ - sprd,ums9620-2h10
+ - const: sprd,ums9620
+
additionalProperties: true
...
diff --git a/dts/upstream/Bindings/arm/stm32/stm32.yaml b/dts/upstream/Bindings/arm/stm32/stm32.yaml
index df087c8..bc2f433 100644
--- a/dts/upstream/Bindings/arm/stm32/stm32.yaml
+++ b/dts/upstream/Bindings/arm/stm32/stm32.yaml
@@ -82,29 +82,19 @@
- shiratech,stm32mp157a-iot-box # IoT Box
- shiratech,stm32mp157a-stinger96 # Stinger96
- st,stm32mp157c-ed1
+ - st,stm32mp157c-ed1-scmi
- st,stm32mp157a-dk1
+ - st,stm32mp157a-dk1-scmi
- st,stm32mp157c-dk2
+ - st,stm32mp157c-dk2-scmi
- const: st,stm32mp157
- items:
- - const: st,stm32mp157a-dk1-scmi
- - const: st,stm32mp157a-dk1
- - const: st,stm32mp157
- - items:
- - const: st,stm32mp157c-dk2-scmi
- - const: st,stm32mp157c-dk2
- - const: st,stm32mp157
- - items:
- - const: st,stm32mp157c-ed1-scmi
- - const: st,stm32mp157c-ed1
- - const: st,stm32mp157
- - items:
- const: st,stm32mp157c-ev1
- const: st,stm32mp157c-ed1
- const: st,stm32mp157
- items:
- const: st,stm32mp157c-ev1-scmi
- - const: st,stm32mp157c-ev1
- const: st,stm32mp157c-ed1
- const: st,stm32mp157
diff --git a/dts/upstream/Bindings/arm/sunxi.yaml b/dts/upstream/Bindings/arm/sunxi.yaml
index 11c5ce9..a9d8e85 100644
--- a/dts/upstream/Bindings/arm/sunxi.yaml
+++ b/dts/upstream/Bindings/arm/sunxi.yaml
@@ -868,6 +868,11 @@
- const: topwise,a721
- const: allwinner,sun4i-a10
+ - description: Transpeed 8K618-T
+ items:
+ - const: transpeed,8k618-t
+ - const: allwinner,sun50i-h618
+
- description: Utoo P66
items:
- const: utoo,p66
@@ -1013,6 +1018,11 @@
- const: xunlong,orangepi-zero2
- const: allwinner,sun50i-h616
+ - description: Xunlong OrangePi Zero 2W
+ items:
+ - const: xunlong,orangepi-zero2w
+ - const: allwinner,sun50i-h618
+
- description: Xunlong OrangePi Zero 3
items:
- const: xunlong,orangepi-zero3
diff --git a/dts/upstream/Bindings/arm/ti/k3.yaml b/dts/upstream/Bindings/arm/ti/k3.yaml
index 03d2a0d..c6506bc 100644
--- a/dts/upstream/Bindings/arm/ti/k3.yaml
+++ b/dts/upstream/Bindings/arm/ti/k3.yaml
@@ -50,6 +50,7 @@
- enum:
- toradex,verdin-am62-nonwifi-dahlia # Verdin AM62 Module on Dahlia
- toradex,verdin-am62-nonwifi-dev # Verdin AM62 Module on Verdin Development Board
+ - toradex,verdin-am62-nonwifi-mallow # Verdin AM62 Module on Mallow
- toradex,verdin-am62-nonwifi-yavia # Verdin AM62 Module on Yavia
- const: toradex,verdin-am62-nonwifi # Verdin AM62 Module without Wi-Fi / BT
- const: toradex,verdin-am62 # Verdin AM62 Module
@@ -60,6 +61,7 @@
- enum:
- toradex,verdin-am62-wifi-dahlia # Verdin AM62 Wi-Fi / BT Module on Dahlia
- toradex,verdin-am62-wifi-dev # Verdin AM62 Wi-Fi / BT M. on Verdin Development B.
+ - toradex,verdin-am62-wifi-mallow # Verdin AM62 Wi-Fi / BT Module on Mallow
- toradex,verdin-am62-wifi-yavia # Verdin AM62 Wi-Fi / BT Module on Yavia
- const: toradex,verdin-am62-wifi # Verdin AM62 Wi-Fi / BT Module
- const: toradex,verdin-am62 # Verdin AM62 Module
diff --git a/dts/upstream/Bindings/arm/ti/omap.yaml b/dts/upstream/Bindings/arm/ti/omap.yaml
index b18fc04..93e04a1 100644
--- a/dts/upstream/Bindings/arm/ti/omap.yaml
+++ b/dts/upstream/Bindings/arm/ti/omap.yaml
@@ -134,6 +134,8 @@
- amazon,omap4-kc1 # Amazon Kindle Fire (first generation)
- motorola,droid4 # Motorola Droid 4 XT894
- motorola,droid-bionic # Motorola Droid Bionic XT875
+ - motorola,xyboard-mz609
+ - motorola,xyboard-mz617
- ti,omap4-panda
- ti,omap4-sdp
- const: ti,omap4430
diff --git a/dts/upstream/Bindings/ata/ceva,ahci-1v84.yaml b/dts/upstream/Bindings/ata/ceva,ahci-1v84.yaml
index b29ce59..9952e0e 100644
--- a/dts/upstream/Bindings/ata/ceva,ahci-1v84.yaml
+++ b/dts/upstream/Bindings/ata/ceva,ahci-1v84.yaml
@@ -7,7 +7,8 @@
title: Ceva AHCI SATA Controller
maintainers:
- - Piyush Mehta <piyush.mehta@amd.com>
+ - Mubin Sayyed <mubin.sayyed@amd.com>
+ - Radhey Shyam Pandey <radhey.shyam.pandey@amd.com>
description: |
The Ceva SATA controller mostly conforms to the AHCI interface with some
diff --git a/dts/upstream/Bindings/auxdisplay/hit,hd44780.yaml b/dts/upstream/Bindings/auxdisplay/hit,hd44780.yaml
index fde07e4..406a922 100644
--- a/dts/upstream/Bindings/auxdisplay/hit,hd44780.yaml
+++ b/dts/upstream/Bindings/auxdisplay/hit,hd44780.yaml
@@ -113,7 +113,7 @@
hd44780 {
compatible = "hit,hd44780";
display-height-chars = <2>;
- display-width-chars = <16>;
+ display-width-chars = <16>;
data-gpios = <&pcf8574 4 0>,
<&pcf8574 5 0>,
<&pcf8574 6 0>,
diff --git a/dts/upstream/Bindings/cache/qcom,llcc.yaml b/dts/upstream/Bindings/cache/qcom,llcc.yaml
index 580f9a9..07ccbda 100644
--- a/dts/upstream/Bindings/cache/qcom,llcc.yaml
+++ b/dts/upstream/Bindings/cache/qcom,llcc.yaml
@@ -33,6 +33,8 @@
- qcom,sm8350-llcc
- qcom,sm8450-llcc
- qcom,sm8550-llcc
+ - qcom,sm8650-llcc
+ - qcom,x1e80100-llcc
reg:
minItems: 2
@@ -64,6 +66,7 @@
compatible:
contains:
enum:
+ - qcom,qdu1000-llcc
- qcom,sc7180-llcc
- qcom,sm6350-llcc
then:
@@ -101,9 +104,9 @@
compatible:
contains:
enum:
- - qcom,qdu1000-llcc
- qcom,sc8180x-llcc
- qcom,sc8280xp-llcc
+ - qcom,x1e80100-llcc
then:
properties:
reg:
diff --git a/dts/upstream/Bindings/cache/sifive,ccache0.yaml b/dts/upstream/Bindings/cache/sifive,ccache0.yaml
index 8a6a78e..7e8cebe 100644
--- a/dts/upstream/Bindings/cache/sifive,ccache0.yaml
+++ b/dts/upstream/Bindings/cache/sifive,ccache0.yaml
@@ -38,7 +38,9 @@
- sifive,fu740-c000-ccache
- const: cache
- items:
- - const: starfive,jh7110-ccache
+ - enum:
+ - starfive,jh7100-ccache
+ - starfive,jh7110-ccache
- const: sifive,ccache0
- const: cache
- items:
@@ -88,6 +90,7 @@
contains:
enum:
- sifive,fu740-c000-ccache
+ - starfive,jh7100-ccache
- starfive,jh7110-ccache
- microchip,mpfs-ccache
@@ -111,6 +114,7 @@
contains:
enum:
- sifive,fu740-c000-ccache
+ - starfive,jh7100-ccache
- starfive,jh7110-ccache
then:
diff --git a/dts/upstream/Bindings/clock/baikal,bt1-ccu-pll.yaml b/dts/upstream/Bindings/clock/baikal,bt1-ccu-pll.yaml
index 624984d..7f8d982 100644
--- a/dts/upstream/Bindings/clock/baikal,bt1-ccu-pll.yaml
+++ b/dts/upstream/Bindings/clock/baikal,bt1-ccu-pll.yaml
@@ -125,7 +125,7 @@
clk25m: clock-oscillator-25m {
compatible = "fixed-clock";
#clock-cells = <0>;
- clock-frequency = <25000000>;
+ clock-frequency = <25000000>;
clock-output-names = "clk25m";
};
...
diff --git a/dts/upstream/Bindings/clock/brcm,kona-ccu.txt b/dts/upstream/Bindings/clock/brcm,kona-ccu.txt
deleted file mode 100644
index 8e5a7d8..0000000
--- a/dts/upstream/Bindings/clock/brcm,kona-ccu.txt
+++ /dev/null
@@ -1,138 +0,0 @@
-Broadcom Kona Family Clocks
-
-This binding is associated with Broadcom SoCs having "Kona" style
-clock control units (CCUs). A CCU is a clock provider that manages
-a set of clock signals. Each CCU is represented by a node in the
-device tree.
-
-This binding uses the common clock binding:
- Documentation/devicetree/bindings/clock/clock-bindings.txt
-
-Required properties:
-- compatible
- Shall have a value of the form "brcm,<model>-<which>-ccu",
- where <model> is a Broadcom SoC model number and <which> is
- the name of a defined CCU. For example:
- "brcm,bcm11351-root-ccu"
- The compatible strings used for each supported SoC family
- are defined below.
-- reg
- Shall define the base and range of the address space
- containing clock control registers
-- #clock-cells
- Shall have value <1>. The permitted clock-specifier values
- are defined below.
-- clock-output-names
- Shall be an ordered list of strings defining the names of
- the clocks provided by the CCU.
-
-Device tree example:
-
- slave_ccu: slave_ccu {
- compatible = "brcm,bcm11351-slave-ccu";
- reg = <0x3e011000 0x0f00>;
- #clock-cells = <1>;
- clock-output-names = "uartb",
- "uartb2",
- "uartb3",
- "uartb4";
- };
-
- ref_crystal_clk: ref_crystal {
- #clock-cells = <0>;
- compatible = "fixed-clock";
- clock-frequency = <26000000>;
- };
-
- uart@3e002000 {
- compatible = "brcm,bcm11351-dw-apb-uart", "snps,dw-apb-uart";
- reg = <0x3e002000 0x1000>;
- clocks = <&slave_ccu BCM281XX_SLAVE_CCU_UARTB3>;
- interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;
- reg-shift = <2>;
- reg-io-width = <4>;
- };
-
-BCM281XX family
----------------
-CCU compatible string values for SoCs in the BCM281XX family are:
- "brcm,bcm11351-root-ccu"
- "brcm,bcm11351-aon-ccu"
- "brcm,bcm11351-hub-ccu"
- "brcm,bcm11351-master-ccu"
- "brcm,bcm11351-slave-ccu"
-
-The following table defines the set of CCUs and clock specifiers for
-BCM281XX family clocks. When a clock consumer references a clocks,
-its symbolic specifier (rather than its numeric index value) should
-be used. These specifiers are defined in:
- "include/dt-bindings/clock/bcm281xx.h"
-
- CCU Clock Type Index Specifier
- --- ----- ---- ----- ---------
- root frac_1m peri 0 BCM281XX_ROOT_CCU_FRAC_1M
-
- aon hub_timer peri 0 BCM281XX_AON_CCU_HUB_TIMER
- aon pmu_bsc peri 1 BCM281XX_AON_CCU_PMU_BSC
- aon pmu_bsc_var peri 2 BCM281XX_AON_CCU_PMU_BSC_VAR
-
- hub tmon_1m peri 0 BCM281XX_HUB_CCU_TMON_1M
-
- master sdio1 peri 0 BCM281XX_MASTER_CCU_SDIO1
- master sdio2 peri 1 BCM281XX_MASTER_CCU_SDIO2
- master sdio3 peri 2 BCM281XX_MASTER_CCU_SDIO3
- master sdio4 peri 3 BCM281XX_MASTER_CCU_SDIO4
- master dmac peri 4 BCM281XX_MASTER_CCU_DMAC
- master usb_ic peri 5 BCM281XX_MASTER_CCU_USB_IC
- master hsic2_48m peri 6 BCM281XX_MASTER_CCU_HSIC_48M
- master hsic2_12m peri 7 BCM281XX_MASTER_CCU_HSIC_12M
-
- slave uartb peri 0 BCM281XX_SLAVE_CCU_UARTB
- slave uartb2 peri 1 BCM281XX_SLAVE_CCU_UARTB2
- slave uartb3 peri 2 BCM281XX_SLAVE_CCU_UARTB3
- slave uartb4 peri 3 BCM281XX_SLAVE_CCU_UARTB4
- slave ssp0 peri 4 BCM281XX_SLAVE_CCU_SSP0
- slave ssp2 peri 5 BCM281XX_SLAVE_CCU_SSP2
- slave bsc1 peri 6 BCM281XX_SLAVE_CCU_BSC1
- slave bsc2 peri 7 BCM281XX_SLAVE_CCU_BSC2
- slave bsc3 peri 8 BCM281XX_SLAVE_CCU_BSC3
- slave pwm peri 9 BCM281XX_SLAVE_CCU_PWM
-
-
-BCM21664 family
----------------
-CCU compatible string values for SoCs in the BCM21664 family are:
- "brcm,bcm21664-root-ccu"
- "brcm,bcm21664-aon-ccu"
- "brcm,bcm21664-master-ccu"
- "brcm,bcm21664-slave-ccu"
-
-The following table defines the set of CCUs and clock specifiers for
-BCM21664 family clocks. When a clock consumer references a clocks,
-its symbolic specifier (rather than its numeric index value) should
-be used. These specifiers are defined in:
- "include/dt-bindings/clock/bcm21664.h"
-
- CCU Clock Type Index Specifier
- --- ----- ---- ----- ---------
- root frac_1m peri 0 BCM21664_ROOT_CCU_FRAC_1M
-
- aon hub_timer peri 0 BCM21664_AON_CCU_HUB_TIMER
-
- master sdio1 peri 0 BCM21664_MASTER_CCU_SDIO1
- master sdio2 peri 1 BCM21664_MASTER_CCU_SDIO2
- master sdio3 peri 2 BCM21664_MASTER_CCU_SDIO3
- master sdio4 peri 3 BCM21664_MASTER_CCU_SDIO4
- master sdio1_sleep peri 4 BCM21664_MASTER_CCU_SDIO1_SLEEP
- master sdio2_sleep peri 5 BCM21664_MASTER_CCU_SDIO2_SLEEP
- master sdio3_sleep peri 6 BCM21664_MASTER_CCU_SDIO3_SLEEP
- master sdio4_sleep peri 7 BCM21664_MASTER_CCU_SDIO4_SLEEP
-
- slave uartb peri 0 BCM21664_SLAVE_CCU_UARTB
- slave uartb2 peri 1 BCM21664_SLAVE_CCU_UARTB2
- slave uartb3 peri 2 BCM21664_SLAVE_CCU_UARTB3
- slave uartb4 peri 3 BCM21664_SLAVE_CCU_UARTB4
- slave bsc1 peri 4 BCM21664_SLAVE_CCU_BSC1
- slave bsc2 peri 5 BCM21664_SLAVE_CCU_BSC2
- slave bsc3 peri 6 BCM21664_SLAVE_CCU_BSC3
- slave bsc4 peri 7 BCM21664_SLAVE_CCU_BSC4
diff --git a/dts/upstream/Bindings/clock/brcm,kona-ccu.yaml b/dts/upstream/Bindings/clock/brcm,kona-ccu.yaml
new file mode 100644
index 0000000..e565695
--- /dev/null
+++ b/dts/upstream/Bindings/clock/brcm,kona-ccu.yaml
@@ -0,0 +1,181 @@
+# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/clock/brcm,kona-ccu.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Broadcom Kona family clock control units (CCU)
+
+maintainers:
+ - Florian Fainelli <florian.fainelli@broadcom.com>
+ - Ray Jui <rjui@broadcom.com>
+ - Scott Branden <sbranden@broadcom.com>
+
+description: |
+ Broadcom "Kona" style clock control unit (CCU) is a clock provider that
+ manages a set of clock signals.
+
+ All available clock IDs are defined in
+ - include/dt-bindings/clock/bcm281xx.h for BCM281XX family
+ - include/dt-bindings/clock/bcm21664.h for BCM21664 family
+
+properties:
+ compatible:
+ enum:
+ - brcm,bcm11351-aon-ccu
+ - brcm,bcm11351-hub-ccu
+ - brcm,bcm11351-master-ccu
+ - brcm,bcm11351-root-ccu
+ - brcm,bcm11351-slave-ccu
+ - brcm,bcm21664-aon-ccu
+ - brcm,bcm21664-master-ccu
+ - brcm,bcm21664-root-ccu
+ - brcm,bcm21664-slave-ccu
+
+ reg:
+ maxItems: 1
+
+ '#clock-cells':
+ const: 1
+
+ clock-output-names:
+ minItems: 1
+ maxItems: 10
+
+required:
+ - compatible
+ - reg
+ - '#clock-cells'
+ - clock-output-names
+
+allOf:
+ - if:
+ properties:
+ compatible:
+ contains:
+ const: brcm,bcm11351-aon-ccu
+ then:
+ properties:
+ clock-output-names:
+ items:
+ - const: hub_timer
+ - const: pmu_bsc
+ - const: pmu_bsc_var
+ - if:
+ properties:
+ compatible:
+ contains:
+ const: brcm,bcm11351-hub-ccu
+ then:
+ properties:
+ clock-output-names:
+ const: tmon_1m
+ - if:
+ properties:
+ compatible:
+ contains:
+ const: brcm,bcm11351-master-ccu
+ then:
+ properties:
+ clock-output-names:
+ items:
+ - const: sdio1
+ - const: sdio2
+ - const: sdio3
+ - const: sdio4
+ - const: usb_ic
+ - const: hsic2_48m
+ - const: hsic2_12m
+ - if:
+ properties:
+ compatible:
+ contains:
+ enum:
+ - brcm,bcm11351-root-ccu
+ - brcm,bcm21664-root-ccu
+ then:
+ properties:
+ clock-output-names:
+ const: frac_1m
+ - if:
+ properties:
+ compatible:
+ contains:
+ const: brcm,bcm11351-slave-ccu
+ then:
+ properties:
+ clock-output-names:
+ items:
+ - const: uartb
+ - const: uartb2
+ - const: uartb3
+ - const: uartb4
+ - const: ssp0
+ - const: ssp2
+ - const: bsc1
+ - const: bsc2
+ - const: bsc3
+ - const: pwm
+ - if:
+ properties:
+ compatible:
+ contains:
+ const: brcm,bcm21664-aon-ccu
+ then:
+ properties:
+ clock-output-names:
+ const: hub_timer
+ - if:
+ properties:
+ compatible:
+ contains:
+ const: brcm,bcm21664-master-ccu
+ then:
+ properties:
+ clock-output-names:
+ items:
+ - const: sdio1
+ - const: sdio2
+ - const: sdio3
+ - const: sdio4
+ - const: sdio1_sleep
+ - const: sdio2_sleep
+ - const: sdio3_sleep
+ - const: sdio4_sleep
+ - if:
+ properties:
+ compatible:
+ contains:
+ const: brcm,bcm21664-slave-ccu
+ then:
+ properties:
+ clock-output-names:
+ items:
+ - const: uartb
+ - const: uartb2
+ - const: uartb3
+ - const: bsc1
+ - const: bsc2
+ - const: bsc3
+ - const: bsc4
+
+additionalProperties: false
+
+examples:
+ - |
+ clock-controller@3e011000 {
+ compatible = "brcm,bcm11351-slave-ccu";
+ reg = <0x3e011000 0x0f00>;
+ #clock-cells = <1>;
+ clock-output-names = "uartb",
+ "uartb2",
+ "uartb3",
+ "uartb4",
+ "ssp0",
+ "ssp2",
+ "bsc1",
+ "bsc2",
+ "bsc3",
+ "pwm";
+ };
+...
diff --git a/dts/upstream/Bindings/clock/fsl,imx93-anatop.yaml b/dts/upstream/Bindings/clock/fsl,imx93-anatop.yaml
new file mode 100644
index 0000000..8a3b247
--- /dev/null
+++ b/dts/upstream/Bindings/clock/fsl,imx93-anatop.yaml
@@ -0,0 +1,42 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/clock/fsl,imx93-anatop.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: NXP i.MX93 ANATOP Clock Module
+
+maintainers:
+ - Peng Fan <peng.fan@nxp.com>
+
+description: |
+ NXP i.MX93 ANATOP module which contains PLL and OSC to Clock Controller
+ Module.
+
+properties:
+ compatible:
+ items:
+ - const: fsl,imx93-anatop
+
+ reg:
+ maxItems: 1
+
+ '#clock-cells':
+ const: 1
+
+required:
+ - compatible
+ - reg
+ - '#clock-cells'
+
+additionalProperties: false
+
+examples:
+ - |
+ clock-controller@44480000 {
+ compatible = "fsl,imx93-anatop";
+ reg = <0x44480000 0x2000>;
+ #clock-cells = <1>;
+ };
+
+...
diff --git a/dts/upstream/Bindings/clock/google,gs101-clock.yaml b/dts/upstream/Bindings/clock/google,gs101-clock.yaml
new file mode 100644
index 0000000..ca7fdad
--- /dev/null
+++ b/dts/upstream/Bindings/clock/google,gs101-clock.yaml
@@ -0,0 +1,106 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/clock/google,gs101-clock.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Google GS101 SoC clock controller
+
+maintainers:
+ - Peter Griffin <peter.griffin@linaro.org>
+
+description: |
+ Google GS101 clock controller is comprised of several CMU units, generating
+ clocks for different domains. Those CMU units are modeled as separate device
+ tree nodes, and might depend on each other. The root clock in that clock tree
+ is OSCCLK (24.576 MHz). That external clock must be defined as a fixed-rate
+ clock in dts.
+
+ CMU_TOP is a top-level CMU, where all base clocks are prepared using PLLs and
+ dividers; all other leaf clocks (other CMUs) are usually derived from CMU_TOP.
+
+ Each clock is assigned an identifier and client nodes can use this identifier
+ to specify the clock which they consume. All clocks available for usage
+ in clock consumer nodes are defined as preprocessor macros in
+ 'dt-bindings/clock/gs101.h' header.
+
+properties:
+ compatible:
+ enum:
+ - google,gs101-cmu-top
+ - google,gs101-cmu-apm
+ - google,gs101-cmu-misc
+
+ clocks:
+ minItems: 1
+ maxItems: 2
+
+ clock-names:
+ minItems: 1
+ maxItems: 2
+
+ "#clock-cells":
+ const: 1
+
+ reg:
+ maxItems: 1
+
+required:
+ - compatible
+ - "#clock-cells"
+ - clocks
+ - clock-names
+ - reg
+
+allOf:
+ - if:
+ properties:
+ compatible:
+ contains:
+ enum:
+ - google,gs101-cmu-top
+ - google,gs101-cmu-apm
+ then:
+ properties:
+ clocks:
+ items:
+ - description: External reference clock (24.576 MHz)
+
+ clock-names:
+ items:
+ - const: oscclk
+
+ - if:
+ properties:
+ compatible:
+ contains:
+ const: google,gs101-cmu-misc
+
+ then:
+ properties:
+ clocks:
+ items:
+ - description: Misc bus clock (from CMU_TOP)
+ - description: Misc sss clock (from CMU_TOP)
+
+ clock-names:
+ items:
+ - const: bus
+ - const: sss
+
+additionalProperties: false
+
+examples:
+ # Clock controller node for CMU_TOP
+ - |
+ #include <dt-bindings/clock/google,gs101.h>
+
+ cmu_top: clock-controller@1e080000 {
+ compatible = "google,gs101-cmu-top";
+ reg = <0x1e080000 0x8000>;
+ #clock-cells = <1>;
+ clocks = <&ext_24_5m>;
+ clock-names = "oscclk";
+ };
+
+...
diff --git a/dts/upstream/Bindings/clock/hi3620-clock.txt b/dts/upstream/Bindings/clock/hi3620-clock.txt
deleted file mode 100644
index dad6269..0000000
--- a/dts/upstream/Bindings/clock/hi3620-clock.txt
+++ /dev/null
@@ -1,20 +0,0 @@
-* Hisilicon Hi3620 Clock Controller
-
-The Hi3620 clock controller generates and supplies clock to various
-controllers within the Hi3620 SoC.
-
-Required Properties:
-
-- compatible: should be one of the following.
- - "hisilicon,hi3620-clock" - controller compatible with Hi3620 SoC.
- - "hisilicon,hi3620-mmc-clock" - controller specific for Hi3620 mmc.
-
-- reg: physical base address of the controller and length of memory mapped
- region.
-
-- #clock-cells: should be 1.
-
-Each clock is assigned an identifier and client nodes use this identifier
-to specify the clock which they consume.
-
-All these identifier could be found in <dt-bindings/clock/hi3620-clock.h>.
diff --git a/dts/upstream/Bindings/clock/mediatek,apmixedsys.yaml b/dts/upstream/Bindings/clock/mediatek,apmixedsys.yaml
index 372c1d7..6855358 100644
--- a/dts/upstream/Bindings/clock/mediatek,apmixedsys.yaml
+++ b/dts/upstream/Bindings/clock/mediatek,apmixedsys.yaml
@@ -22,6 +22,7 @@
- mediatek,mt7622-apmixedsys
- mediatek,mt7981-apmixedsys
- mediatek,mt7986-apmixedsys
+ - mediatek,mt7988-apmixedsys
- mediatek,mt8135-apmixedsys
- mediatek,mt8173-apmixedsys
- mediatek,mt8516-apmixedsys
diff --git a/dts/upstream/Bindings/clock/mediatek,ethsys.yaml b/dts/upstream/Bindings/clock/mediatek,ethsys.yaml
new file mode 100644
index 0000000..f9cddac
--- /dev/null
+++ b/dts/upstream/Bindings/clock/mediatek,ethsys.yaml
@@ -0,0 +1,55 @@
+# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/clock/mediatek,ethsys.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Mediatek ethsys controller
+
+description:
+ The available clocks are defined in dt-bindings/clock/mt*-clk.h.
+
+maintainers:
+ - James Liao <jamesjj.liao@mediatek.com>
+
+properties:
+ compatible:
+ oneOf:
+ - items:
+ - enum:
+ - mediatek,mt2701-ethsys
+ - mediatek,mt7622-ethsys
+ - mediatek,mt7629-ethsys
+ - mediatek,mt7981-ethsys
+ - mediatek,mt7986-ethsys
+ - mediatek,mt7988-ethsys
+ - const: syscon
+ - items:
+ - const: mediatek,mt7623-ethsys
+ - const: mediatek,mt2701-ethsys
+ - const: syscon
+
+ reg:
+ maxItems: 1
+
+ "#clock-cells":
+ const: 1
+
+ "#reset-cells":
+ const: 1
+
+required:
+ - reg
+ - "#clock-cells"
+ - "#reset-cells"
+
+additionalProperties: false
+
+examples:
+ - |
+ clock-controller@1b000000 {
+ compatible = "mediatek,mt2701-ethsys", "syscon";
+ reg = <0x1b000000 0x1000>;
+ #clock-cells = <1>;
+ #reset-cells = <1>;
+ };
diff --git a/dts/upstream/Bindings/clock/mediatek,mt7988-ethwarp.yaml b/dts/upstream/Bindings/clock/mediatek,mt7988-ethwarp.yaml
new file mode 100644
index 0000000..e32a025
--- /dev/null
+++ b/dts/upstream/Bindings/clock/mediatek,mt7988-ethwarp.yaml
@@ -0,0 +1,52 @@
+# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/clock/mediatek,mt7988-ethwarp.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: MediaTek MT7988 ethwarp Controller
+
+maintainers:
+ - Daniel Golle <daniel@makrotopia.org>
+
+description:
+ The Mediatek MT7988 ethwarp controller provides clocks and resets for the
+ Ethernet related subsystems found the MT7988 SoC.
+ The clock values can be found in <dt-bindings/clock/mt*-clk.h>.
+
+properties:
+ compatible:
+ items:
+ - const: mediatek,mt7988-ethwarp
+
+ reg:
+ maxItems: 1
+
+ '#clock-cells':
+ const: 1
+
+ '#reset-cells':
+ const: 1
+
+required:
+ - compatible
+ - reg
+ - '#clock-cells'
+ - '#reset-cells'
+
+additionalProperties: false
+
+examples:
+ - |
+ #include <dt-bindings/reset/ti-syscon.h>
+ soc {
+ #address-cells = <2>;
+ #size-cells = <2>;
+
+ clock-controller@15031000 {
+ compatible = "mediatek,mt7988-ethwarp";
+ reg = <0 0x15031000 0 0x1000>;
+ #clock-cells = <1>;
+ #reset-cells = <1>;
+ };
+ };
diff --git a/dts/upstream/Bindings/clock/mediatek,mt7988-xfi-pll.yaml b/dts/upstream/Bindings/clock/mediatek,mt7988-xfi-pll.yaml
new file mode 100644
index 0000000..192f145
--- /dev/null
+++ b/dts/upstream/Bindings/clock/mediatek,mt7988-xfi-pll.yaml
@@ -0,0 +1,48 @@
+# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/clock/mediatek,mt7988-xfi-pll.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: MediaTek MT7988 XFI PLL Clock Controller
+
+maintainers:
+ - Daniel Golle <daniel@makrotopia.org>
+
+description:
+ The MediaTek XFI PLL controller provides the 156.25MHz clock for the
+ Ethernet SerDes PHY from the 40MHz top_xtal clock.
+
+properties:
+ compatible:
+ const: mediatek,mt7988-xfi-pll
+
+ reg:
+ maxItems: 1
+
+ resets:
+ maxItems: 1
+
+ '#clock-cells':
+ const: 1
+
+required:
+ - compatible
+ - reg
+ - resets
+ - '#clock-cells'
+
+additionalProperties: false
+
+examples:
+ - |
+ soc {
+ #address-cells = <2>;
+ #size-cells = <2>;
+ clock-controller@11f40000 {
+ compatible = "mediatek,mt7988-xfi-pll";
+ reg = <0 0x11f40000 0 0x1000>;
+ resets = <&watchdog 16>;
+ #clock-cells = <1>;
+ };
+ };
diff --git a/dts/upstream/Bindings/clock/mediatek,mt8188-clock.yaml b/dts/upstream/Bindings/clock/mediatek,mt8188-clock.yaml
index d7214d9..8605703 100644
--- a/dts/upstream/Bindings/clock/mediatek,mt8188-clock.yaml
+++ b/dts/upstream/Bindings/clock/mediatek,mt8188-clock.yaml
@@ -43,8 +43,6 @@
- mediatek,mt8188-vdecsys
- mediatek,mt8188-vdecsys-soc
- mediatek,mt8188-vencsys
- - mediatek,mt8188-vppsys0
- - mediatek,mt8188-vppsys1
- mediatek,mt8188-wpesys
- mediatek,mt8188-wpesys-vpp0
diff --git a/dts/upstream/Bindings/clock/mediatek,topckgen.yaml b/dts/upstream/Bindings/clock/mediatek,topckgen.yaml
index 6d087de..bdf3b55 100644
--- a/dts/upstream/Bindings/clock/mediatek,topckgen.yaml
+++ b/dts/upstream/Bindings/clock/mediatek,topckgen.yaml
@@ -37,6 +37,8 @@
- mediatek,mt7629-topckgen
- mediatek,mt7981-topckgen
- mediatek,mt7986-topckgen
+ - mediatek,mt7988-mcusys
+ - mediatek,mt7988-topckgen
- mediatek,mt8167-topckgen
- mediatek,mt8183-topckgen
- const: syscon
diff --git a/dts/upstream/Bindings/clock/qcom,a53pll.yaml b/dts/upstream/Bindings/clock/qcom,a53pll.yaml
index 9436266..5ca927a 100644
--- a/dts/upstream/Bindings/clock/qcom,a53pll.yaml
+++ b/dts/upstream/Bindings/clock/qcom,a53pll.yaml
@@ -16,6 +16,7 @@
properties:
compatible:
enum:
+ - qcom,ipq5018-a53pll
- qcom,ipq5332-a53pll
- qcom,ipq6018-a53pll
- qcom,ipq8074-a53pll
diff --git a/dts/upstream/Bindings/clock/qcom,camcc-sm8250.yaml b/dts/upstream/Bindings/clock/qcom,camcc-sm8250.yaml
index 426335a..3fd3dc1 100644
--- a/dts/upstream/Bindings/clock/qcom,camcc-sm8250.yaml
+++ b/dts/upstream/Bindings/clock/qcom,camcc-sm8250.yaml
@@ -15,6 +15,9 @@
See also:: include/dt-bindings/clock/qcom,camcc-sm8250.h
+allOf:
+ - $ref: qcom,gcc.yaml#
+
properties:
compatible:
const: qcom,sm8250-camcc
@@ -33,15 +36,6 @@
- const: bi_tcxo_ao
- const: sleep_clk
- '#clock-cells':
- const: 1
-
- '#reset-cells':
- const: 1
-
- '#power-domain-cells':
- const: 1
-
power-domains:
items:
- description: MMCX power domain
@@ -56,14 +50,10 @@
required:
- compatible
- - reg
- clocks
- clock-names
- - '#clock-cells'
- - '#reset-cells'
- - '#power-domain-cells'
-additionalProperties: false
+unevaluatedProperties: false
examples:
- |
diff --git a/dts/upstream/Bindings/clock/qcom,gcc-ipq6018.yaml b/dts/upstream/Bindings/clock/qcom,gcc-ipq6018.yaml
new file mode 100644
index 0000000..af5d883
--- /dev/null
+++ b/dts/upstream/Bindings/clock/qcom,gcc-ipq6018.yaml
@@ -0,0 +1,57 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/clock/qcom,gcc-ipq6018.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Qualcomm Global Clock & Reset Controller on IPQ6018
+
+maintainers:
+ - Stephen Boyd <sboyd@kernel.org>
+ - Taniya Das <quic_tdas@quicinc.com>
+ - Robert Marko <robimarko@gmail.com>
+
+description: |
+ Qualcomm global clock control module provides the clocks, resets and power
+ domains on IPQ6018.
+
+ See also::
+ include/dt-bindings/clock/qcom,gcc-ipq6018.h
+ include/dt-bindings/reset/qcom,gcc-ipq6018.h
+
+allOf:
+ - $ref: qcom,gcc.yaml#
+
+properties:
+ compatible:
+ const: qcom,gcc-ipq6018
+
+ clocks:
+ items:
+ - description: board XO clock
+ - description: sleep clock
+
+ clock-names:
+ items:
+ - const: xo
+ - const: sleep_clk
+
+required:
+ - compatible
+ - clocks
+ - clock-names
+
+unevaluatedProperties: false
+
+examples:
+ - |
+ clock-controller@1800000 {
+ compatible = "qcom,gcc-ipq6018";
+ reg = <0x01800000 0x80000>;
+ clocks = <&xo>, <&sleep_clk>;
+ clock-names = "xo", "sleep_clk";
+ #clock-cells = <1>;
+ #power-domain-cells = <1>;
+ #reset-cells = <1>;
+ };
+...
diff --git a/dts/upstream/Bindings/clock/qcom,gcc-ipq8074.yaml b/dts/upstream/Bindings/clock/qcom,gcc-ipq8074.yaml
index 52e7831..2d44ddc 100644
--- a/dts/upstream/Bindings/clock/qcom,gcc-ipq8074.yaml
+++ b/dts/upstream/Bindings/clock/qcom,gcc-ipq8074.yaml
@@ -27,11 +27,15 @@
items:
- description: board XO clock
- description: sleep clock
+ - description: Gen3 QMP PCIe PHY PIPE clock
+ - description: Gen2 QMP PCIe PHY PIPE clock
clock-names:
items:
- const: xo
- const: sleep_clk
+ - const: pcie0_pipe
+ - const: pcie1_pipe
required:
- compatible
diff --git a/dts/upstream/Bindings/clock/qcom,gcc-other.yaml b/dts/upstream/Bindings/clock/qcom,gcc-other.yaml
index 559fc21..7d05f0f 100644
--- a/dts/upstream/Bindings/clock/qcom,gcc-other.yaml
+++ b/dts/upstream/Bindings/clock/qcom,gcc-other.yaml
@@ -15,8 +15,6 @@
domains.
See also::
- include/dt-bindings/clock/qcom,gcc-ipq6018.h
- include/dt-bindings/reset/qcom,gcc-ipq6018.h
include/dt-bindings/clock/qcom,gcc-msm8953.h
include/dt-bindings/clock/qcom,gcc-mdm9607.h
@@ -26,7 +24,6 @@
properties:
compatible:
enum:
- - qcom,gcc-ipq6018
- qcom,gcc-mdm9607
required:
diff --git a/dts/upstream/Bindings/clock/qcom,qdu1000-ecpricc.yaml b/dts/upstream/Bindings/clock/qcom,qdu1000-ecpricc.yaml
new file mode 100644
index 0000000..fd21df0
--- /dev/null
+++ b/dts/upstream/Bindings/clock/qcom,qdu1000-ecpricc.yaml
@@ -0,0 +1,68 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/clock/qcom,qdu1000-ecpricc.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Qualcomm ECPRI Clock & Reset Controller for QDU1000 and QRU1000
+
+maintainers:
+ - Taniya Das <quic_tdas@quicinc.com>
+ - Imran Shaik <quic_imrashai@quicinc.com>
+
+description: |
+ Qualcomm ECPRI Specification V2.0 Common Public Radio Interface clock control
+ module which supports the clocks, resets on QDU1000 and QRU1000
+
+ See also:: include/dt-bindings/clock/qcom,qdu1000-ecpricc.h
+
+properties:
+ compatible:
+ enum:
+ - qcom,qdu1000-ecpricc
+
+ reg:
+ maxItems: 1
+
+ clocks:
+ items:
+ - description: Board XO source
+ - description: GPLL0 source from GCC
+ - description: GPLL1 source from GCC
+ - description: GPLL2 source from GCC
+ - description: GPLL3 source from GCC
+ - description: GPLL4 source from GCC
+ - description: GPLL5 source from GCC
+
+ '#clock-cells':
+ const: 1
+
+ '#reset-cells':
+ const: 1
+
+required:
+ - compatible
+ - reg
+ - clocks
+ - '#clock-cells'
+ - '#reset-cells'
+
+additionalProperties: false
+
+examples:
+ - |
+ #include <dt-bindings/clock/qcom,qdu1000-gcc.h>
+ #include <dt-bindings/clock/qcom,rpmh.h>
+ clock-controller@280000 {
+ compatible = "qcom,qdu1000-ecpricc";
+ reg = <0x00280000 0x31c00>;
+ clocks = <&rpmhcc RPMH_CXO_CLK>,
+ <&gcc GCC_ECPRI_CC_GPLL0_CLK_SRC>,
+ <&gcc GCC_ECPRI_CC_GPLL1_EVEN_CLK_SRC>,
+ <&gcc GCC_ECPRI_CC_GPLL2_EVEN_CLK_SRC>,
+ <&gcc GCC_ECPRI_CC_GPLL3_CLK_SRC>,
+ <&gcc GCC_ECPRI_CC_GPLL4_CLK_SRC>,
+ <&gcc GCC_ECPRI_CC_GPLL5_EVEN_CLK_SRC>;
+ #clock-cells = <1>;
+ #reset-cells = <1>;
+ };
diff --git a/dts/upstream/Bindings/clock/qcom,rpmhcc.yaml b/dts/upstream/Bindings/clock/qcom,rpmhcc.yaml
index 4eb5e59..ca85794 100644
--- a/dts/upstream/Bindings/clock/qcom,rpmhcc.yaml
+++ b/dts/upstream/Bindings/clock/qcom,rpmhcc.yaml
@@ -35,6 +35,8 @@
- qcom,sm8350-rpmh-clk
- qcom,sm8450-rpmh-clk
- qcom,sm8550-rpmh-clk
+ - qcom,sm8650-rpmh-clk
+ - qcom,x1e80100-rpmh-clk
clocks:
maxItems: 1
diff --git a/dts/upstream/Bindings/clock/qcom,sc7180-camcc.yaml b/dts/upstream/Bindings/clock/qcom,sc7180-camcc.yaml
index 2dfc2a4..c7fe640 100644
--- a/dts/upstream/Bindings/clock/qcom,sc7180-camcc.yaml
+++ b/dts/upstream/Bindings/clock/qcom,sc7180-camcc.yaml
@@ -15,6 +15,9 @@
See also:: include/dt-bindings/clock/qcom,camcc-sc7180.h
+allOf:
+ - $ref: qcom,gcc.yaml#
+
properties:
compatible:
const: qcom,sc7180-camcc
@@ -31,28 +34,15 @@
- const: iface
- const: xo
- '#clock-cells':
- const: 1
-
- '#reset-cells':
- const: 1
-
- '#power-domain-cells':
- const: 1
-
reg:
maxItems: 1
required:
- compatible
- - reg
- clocks
- clock-names
- - '#clock-cells'
- - '#reset-cells'
- - '#power-domain-cells'
-additionalProperties: false
+unevaluatedProperties: false
examples:
- |
diff --git a/dts/upstream/Bindings/clock/qcom,sc7280-camcc.yaml b/dts/upstream/Bindings/clock/qcom,sc7280-camcc.yaml
index 01feef1..dcef8de 100644
--- a/dts/upstream/Bindings/clock/qcom,sc7280-camcc.yaml
+++ b/dts/upstream/Bindings/clock/qcom,sc7280-camcc.yaml
@@ -15,6 +15,9 @@
See also:: include/dt-bindings/clock/qcom,camcc-sc7280.h
+allOf:
+ - $ref: qcom,gcc.yaml#
+
properties:
compatible:
const: qcom,sc7280-camcc
@@ -31,28 +34,15 @@
- const: bi_tcxo_ao
- const: sleep_clk
- '#clock-cells':
- const: 1
-
- '#reset-cells':
- const: 1
-
- '#power-domain-cells':
- const: 1
-
reg:
maxItems: 1
required:
- compatible
- - reg
- clocks
- clock-names
- - '#clock-cells'
- - '#reset-cells'
- - '#power-domain-cells'
-additionalProperties: false
+unevaluatedProperties: false
examples:
- |
diff --git a/dts/upstream/Bindings/clock/qcom,sdm845-camcc.yaml b/dts/upstream/Bindings/clock/qcom,sdm845-camcc.yaml
index 91d1f79..810b852 100644
--- a/dts/upstream/Bindings/clock/qcom,sdm845-camcc.yaml
+++ b/dts/upstream/Bindings/clock/qcom,sdm845-camcc.yaml
@@ -15,6 +15,9 @@
See also:: include/dt-bindings/clock/qcom,camcc-sm845.h
+allOf:
+ - $ref: qcom,gcc.yaml#
+
properties:
compatible:
const: qcom,sdm845-camcc
@@ -27,28 +30,15 @@
items:
- const: bi_tcxo
- '#clock-cells':
- const: 1
-
- '#reset-cells':
- const: 1
-
- '#power-domain-cells':
- const: 1
-
reg:
maxItems: 1
required:
- compatible
- - reg
- clocks
- clock-names
- - '#clock-cells'
- - '#reset-cells'
- - '#power-domain-cells'
-additionalProperties: false
+unevaluatedProperties: false
examples:
- |
diff --git a/dts/upstream/Bindings/clock/qcom,sm8450-camcc.yaml b/dts/upstream/Bindings/clock/qcom,sm8450-camcc.yaml
index dc3c18e..4898646 100644
--- a/dts/upstream/Bindings/clock/qcom,sm8450-camcc.yaml
+++ b/dts/upstream/Bindings/clock/qcom,sm8450-camcc.yaml
@@ -16,10 +16,15 @@
See also::
include/dt-bindings/clock/qcom,sm8450-camcc.h
include/dt-bindings/clock/qcom,sm8550-camcc.h
+ include/dt-bindings/clock/qcom,sc8280xp-camcc.h
+
+allOf:
+ - $ref: qcom,gcc.yaml#
properties:
compatible:
enum:
+ - qcom,sc8280xp-camcc
- qcom,sm8450-camcc
- qcom,sm8550-camcc
@@ -40,29 +45,16 @@
description:
A phandle to an OPP node describing required MMCX performance point.
- '#clock-cells':
- const: 1
-
- '#reset-cells':
- const: 1
-
- '#power-domain-cells':
- const: 1
-
reg:
maxItems: 1
required:
- compatible
- - reg
- clocks
- power-domains
- required-opps
- - '#clock-cells'
- - '#reset-cells'
- - '#power-domain-cells'
-additionalProperties: false
+unevaluatedProperties: false
examples:
- |
diff --git a/dts/upstream/Bindings/clock/qcom,sm8450-gpucc.yaml b/dts/upstream/Bindings/clock/qcom,sm8450-gpucc.yaml
index 2320be9..1a384e8 100644
--- a/dts/upstream/Bindings/clock/qcom,sm8450-gpucc.yaml
+++ b/dts/upstream/Bindings/clock/qcom,sm8450-gpucc.yaml
@@ -17,12 +17,14 @@
include/dt-bindings/clock/qcom,sm8450-gpucc.h
include/dt-bindings/clock/qcom,sm8550-gpucc.h
include/dt-bindings/reset/qcom,sm8450-gpucc.h
+ include/dt-bindings/reset/qcom,sm8650-gpucc.h
properties:
compatible:
enum:
- qcom,sm8450-gpucc
- qcom,sm8550-gpucc
+ - qcom,sm8650-gpucc
clocks:
items:
diff --git a/dts/upstream/Bindings/clock/qcom,sm8550-tcsr.yaml b/dts/upstream/Bindings/clock/qcom,sm8550-tcsr.yaml
index 1bf1a41..af16b05 100644
--- a/dts/upstream/Bindings/clock/qcom,sm8550-tcsr.yaml
+++ b/dts/upstream/Bindings/clock/qcom,sm8550-tcsr.yaml
@@ -13,12 +13,16 @@
Qualcomm TCSR clock control module provides the clocks, resets and
power domains on SM8550
- See also:: include/dt-bindings/clock/qcom,sm8550-tcsr.h
+ See also:
+ - include/dt-bindings/clock/qcom,sm8550-tcsr.h
+ - include/dt-bindings/clock/qcom,sm8650-tcsr.h
properties:
compatible:
items:
- - const: qcom,sm8550-tcsr
+ - enum:
+ - qcom,sm8550-tcsr
+ - qcom,sm8650-tcsr
- const: syscon
clocks:
diff --git a/dts/upstream/Bindings/clock/qcom,sm8650-dispcc.yaml b/dts/upstream/Bindings/clock/qcom,sm8650-dispcc.yaml
new file mode 100644
index 0000000..5e0c45c
--- /dev/null
+++ b/dts/upstream/Bindings/clock/qcom,sm8650-dispcc.yaml
@@ -0,0 +1,106 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/clock/qcom,sm8650-dispcc.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Qualcomm Display Clock & Reset Controller for SM8650
+
+maintainers:
+ - Bjorn Andersson <andersson@kernel.org>
+ - Neil Armstrong <neil.armstrong@linaro.org>
+
+description: |
+ Qualcomm display clock control module provides the clocks, resets and power
+ domains on SM8650.
+
+ See also:: include/dt-bindings/clock/qcom,sm8650-dispcc.h
+
+properties:
+ compatible:
+ enum:
+ - qcom,sm8650-dispcc
+
+ clocks:
+ items:
+ - description: Board XO source
+ - description: Board Always On XO source
+ - description: Display's AHB clock
+ - description: sleep clock
+ - description: Byte clock from DSI PHY0
+ - description: Pixel clock from DSI PHY0
+ - description: Byte clock from DSI PHY1
+ - description: Pixel clock from DSI PHY1
+ - description: Link clock from DP PHY0
+ - description: VCO DIV clock from DP PHY0
+ - description: Link clock from DP PHY1
+ - description: VCO DIV clock from DP PHY1
+ - description: Link clock from DP PHY2
+ - description: VCO DIV clock from DP PHY2
+ - description: Link clock from DP PHY3
+ - description: VCO DIV clock from DP PHY3
+
+ '#clock-cells':
+ const: 1
+
+ '#reset-cells':
+ const: 1
+
+ '#power-domain-cells':
+ const: 1
+
+ reg:
+ maxItems: 1
+
+ power-domains:
+ description:
+ A phandle and PM domain specifier for the MMCX power domain.
+ maxItems: 1
+
+ required-opps:
+ description:
+ A phandle to an OPP node describing required MMCX performance point.
+ maxItems: 1
+
+required:
+ - compatible
+ - reg
+ - clocks
+ - '#clock-cells'
+ - '#reset-cells'
+ - '#power-domain-cells'
+
+additionalProperties: false
+
+examples:
+ - |
+ #include <dt-bindings/clock/qcom,sm8650-gcc.h>
+ #include <dt-bindings/clock/qcom,rpmh.h>
+ #include <dt-bindings/power/qcom-rpmpd.h>
+ #include <dt-bindings/power/qcom,rpmhpd.h>
+ clock-controller@af00000 {
+ compatible = "qcom,sm8650-dispcc";
+ reg = <0x0af00000 0x10000>;
+ clocks = <&rpmhcc RPMH_CXO_CLK>,
+ <&rpmhcc RPMH_CXO_CLK_A>,
+ <&gcc GCC_DISP_AHB_CLK>,
+ <&sleep_clk>,
+ <&dsi0_phy 0>,
+ <&dsi0_phy 1>,
+ <&dsi1_phy 0>,
+ <&dsi1_phy 1>,
+ <&dp0_phy 0>,
+ <&dp0_phy 1>,
+ <&dp1_phy 0>,
+ <&dp1_phy 1>,
+ <&dp2_phy 0>,
+ <&dp2_phy 1>,
+ <&dp3_phy 0>,
+ <&dp3_phy 1>;
+ #clock-cells = <1>;
+ #reset-cells = <1>;
+ #power-domain-cells = <1>;
+ power-domains = <&rpmhpd RPMHPD_MMCX>;
+ required-opps = <&rpmhpd_opp_low_svs>;
+ };
+...
diff --git a/dts/upstream/Bindings/clock/qcom,sm8650-gcc.yaml b/dts/upstream/Bindings/clock/qcom,sm8650-gcc.yaml
new file mode 100644
index 0000000..b54761c
--- /dev/null
+++ b/dts/upstream/Bindings/clock/qcom,sm8650-gcc.yaml
@@ -0,0 +1,65 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/clock/qcom,sm8650-gcc.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Qualcomm Global Clock & Reset Controller on SM8650
+
+maintainers:
+ - Bjorn Andersson <andersson@kernel.org>
+
+description: |
+ Qualcomm global clock control module provides the clocks, resets and power
+ domains on SM8650
+
+ See also:: include/dt-bindings/clock/qcom,sm8650-gcc.h
+
+properties:
+ compatible:
+ const: qcom,sm8650-gcc
+
+ clocks:
+ items:
+ - description: Board XO source
+ - description: Board Always On XO source
+ - description: Sleep clock source
+ - description: PCIE 0 Pipe clock source
+ - description: PCIE 1 Pipe clock source
+ - description: PCIE 1 Phy Auxiliary clock source
+ - description: UFS Phy Rx symbol 0 clock source
+ - description: UFS Phy Rx symbol 1 clock source
+ - description: UFS Phy Tx symbol 0 clock source
+ - description: USB3 Phy wrapper pipe clock source
+
+required:
+ - compatible
+ - clocks
+
+allOf:
+ - $ref: qcom,gcc.yaml#
+
+unevaluatedProperties: false
+
+examples:
+ - |
+ #include <dt-bindings/clock/qcom,rpmh.h>
+ clock-controller@100000 {
+ compatible = "qcom,sm8650-gcc";
+ reg = <0x00100000 0x001f4200>;
+ clocks = <&rpmhcc RPMH_CXO_CLK>,
+ <&rpmhcc RPMH_CXO_CLK_A>,
+ <&sleep_clk>,
+ <&pcie0_phy>,
+ <&pcie1_phy>,
+ <&pcie_1_phy_aux_clk>,
+ <&ufs_mem_phy 0>,
+ <&ufs_mem_phy 1>,
+ <&ufs_mem_phy 2>,
+ <&usb_1_qmpphy>;
+ #clock-cells = <1>;
+ #reset-cells = <1>;
+ #power-domain-cells = <1>;
+ };
+
+...
diff --git a/dts/upstream/Bindings/clock/qcom,x1e80100-gcc.yaml b/dts/upstream/Bindings/clock/qcom,x1e80100-gcc.yaml
new file mode 100644
index 0000000..14a796d
--- /dev/null
+++ b/dts/upstream/Bindings/clock/qcom,x1e80100-gcc.yaml
@@ -0,0 +1,72 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/clock/qcom,x1e80100-gcc.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Qualcomm Global Clock & Reset Controller on X1E80100
+
+maintainers:
+ - Rajendra Nayak <quic_rjendra@quicinc.com>
+
+description: |
+ Qualcomm global clock control module provides the clocks, resets and power
+ domains on X1E80100
+
+ See also:: include/dt-bindings/clock/qcom,x1e80100-gcc.h
+
+properties:
+ compatible:
+ const: qcom,x1e80100-gcc
+
+ clocks:
+ items:
+ - description: Board XO source
+ - description: Sleep clock source
+ - description: PCIe 3 pipe clock
+ - description: PCIe 4 pipe clock
+ - description: PCIe 5 pipe clock
+ - description: PCIe 6a pipe clock
+ - description: PCIe 6b pipe clock
+ - description: USB QMP Phy 0 clock source
+ - description: USB QMP Phy 1 clock source
+ - description: USB QMP Phy 2 clock source
+
+ power-domains:
+ description:
+ A phandle and PM domain specifier for the CX power domain.
+ maxItems: 1
+
+required:
+ - compatible
+ - clocks
+ - power-domains
+
+allOf:
+ - $ref: qcom,gcc.yaml#
+
+unevaluatedProperties: false
+
+examples:
+ - |
+ #include <dt-bindings/power/qcom,rpmhpd.h>
+ clock-controller@100000 {
+ compatible = "qcom,x1e80100-gcc";
+ reg = <0x00100000 0x200000>;
+ clocks = <&bi_tcxo_div2>,
+ <&sleep_clk>,
+ <&pcie3_phy>,
+ <&pcie4_phy>,
+ <&pcie5_phy>,
+ <&pcie6a_phy>,
+ <&pcie6b_phy>,
+ <&usb_1_ss0_qmpphy 0>,
+ <&usb_1_ss1_qmpphy 1>,
+ <&usb_1_ss2_qmpphy 2>;
+ power-domains = <&rpmhpd RPMHPD_CX>;
+ #clock-cells = <1>;
+ #reset-cells = <1>;
+ #power-domain-cells = <1>;
+ };
+
+...
diff --git a/dts/upstream/Bindings/clock/renesas,9series.yaml b/dts/upstream/Bindings/clock/renesas,9series.yaml
index 3afdebd..af63196 100644
--- a/dts/upstream/Bindings/clock/renesas,9series.yaml
+++ b/dts/upstream/Bindings/clock/renesas,9series.yaml
@@ -21,6 +21,15 @@
1 -- DIF1
2 -- DIF2
3 -- DIF3
+ - 9FGV0841:
+ 0 -- DIF0
+ 1 -- DIF1
+ 2 -- DIF2
+ 3 -- DIF3
+ 4 -- DIF4
+ 5 -- DIF5
+ 6 -- DIF6
+ 7 -- DIF7
maintainers:
- Marek Vasut <marex@denx.de>
@@ -30,6 +39,7 @@
enum:
- renesas,9fgv0241
- renesas,9fgv0441
+ - renesas,9fgv0841
reg:
description: I2C device address
diff --git a/dts/upstream/Bindings/clock/silabs,si5351.txt b/dts/upstream/Bindings/clock/silabs,si5351.txt
deleted file mode 100644
index bfda6af..0000000
--- a/dts/upstream/Bindings/clock/silabs,si5351.txt
+++ /dev/null
@@ -1,126 +0,0 @@
-Binding for Silicon Labs Si5351a/b/c programmable i2c clock generator.
-
-Reference
-[1] Si5351A/B/C Data Sheet
- https://www.skyworksinc.com/-/media/Skyworks/SL/documents/public/data-sheets/Si5351-B.pdf
-
-The Si5351a/b/c are programmable i2c clock generators with up to 8 output
-clocks. Si5351a also has a reduced pin-count package (MSOP10) where only
-3 output clocks are accessible. The internal structure of the clock
-generators can be found in [1].
-
-==I2C device node==
-
-Required properties:
-- compatible: shall be one of the following:
- "silabs,si5351a" - Si5351a, QFN20 package
- "silabs,si5351a-msop" - Si5351a, MSOP10 package
- "silabs,si5351b" - Si5351b, QFN20 package
- "silabs,si5351c" - Si5351c, QFN20 package
-- reg: i2c device address, shall be 0x60 or 0x61.
-- #clock-cells: from common clock binding; shall be set to 1.
-- clocks: from common clock binding; list of parent clock
- handles, shall be xtal reference clock or xtal and clkin for
- si5351c only. Corresponding clock input names are "xtal" and
- "clkin" respectively.
-- #address-cells: shall be set to 1.
-- #size-cells: shall be set to 0.
-
-Optional properties:
-- silabs,pll-source: pair of (number, source) for each pll. Allows
- to overwrite clock source of pll A (number=0) or B (number=1).
-
-==Child nodes==
-
-Each of the clock outputs can be overwritten individually by
-using a child node to the I2C device node. If a child node for a clock
-output is not set, the eeprom configuration is not overwritten.
-
-Required child node properties:
-- reg: number of clock output.
-
-Optional child node properties:
-- silabs,clock-source: source clock of the output divider stage N, shall be
- 0 = multisynth N
- 1 = multisynth 0 for output clocks 0-3, else multisynth4
- 2 = xtal
- 3 = clkin (si5351c only)
-- silabs,drive-strength: output drive strength in mA, shall be one of {2,4,6,8}.
-- silabs,multisynth-source: source pll A(0) or B(1) of corresponding multisynth
- divider.
-- silabs,pll-master: boolean, multisynth can change pll frequency.
-- silabs,pll-reset: boolean, clock output can reset its pll.
-- silabs,disable-state : clock output disable state, shall be
- 0 = clock output is driven LOW when disabled
- 1 = clock output is driven HIGH when disabled
- 2 = clock output is FLOATING (HIGH-Z) when disabled
- 3 = clock output is NEVER disabled
-
-==Example==
-
-/* 25MHz reference crystal */
-ref25: ref25M {
- compatible = "fixed-clock";
- #clock-cells = <0>;
- clock-frequency = <25000000>;
-};
-
-i2c-master-node {
-
- /* Si5351a msop10 i2c clock generator */
- si5351a: clock-generator@60 {
- compatible = "silabs,si5351a-msop";
- reg = <0x60>;
- #address-cells = <1>;
- #size-cells = <0>;
- #clock-cells = <1>;
-
- /* connect xtal input to 25MHz reference */
- clocks = <&ref25>;
- clock-names = "xtal";
-
- /* connect xtal input as source of pll0 and pll1 */
- silabs,pll-source = <0 0>, <1 0>;
-
- /*
- * overwrite clkout0 configuration with:
- * - 8mA output drive strength
- * - pll0 as clock source of multisynth0
- * - multisynth0 as clock source of output divider
- * - multisynth0 can change pll0
- * - set initial clock frequency of 74.25MHz
- */
- clkout0 {
- reg = <0>;
- silabs,drive-strength = <8>;
- silabs,multisynth-source = <0>;
- silabs,clock-source = <0>;
- silabs,pll-master;
- clock-frequency = <74250000>;
- };
-
- /*
- * overwrite clkout1 configuration with:
- * - 4mA output drive strength
- * - pll1 as clock source of multisynth1
- * - multisynth1 as clock source of output divider
- * - multisynth1 can change pll1
- */
- clkout1 {
- reg = <1>;
- silabs,drive-strength = <4>;
- silabs,multisynth-source = <1>;
- silabs,clock-source = <0>;
- pll-master;
- };
-
- /*
- * overwrite clkout2 configuration with:
- * - xtal as clock source of output divider
- */
- clkout2 {
- reg = <2>;
- silabs,clock-source = <2>;
- };
- };
-};
diff --git a/dts/upstream/Bindings/clock/silabs,si5351.yaml b/dts/upstream/Bindings/clock/silabs,si5351.yaml
new file mode 100644
index 0000000..d3e0ec2
--- /dev/null
+++ b/dts/upstream/Bindings/clock/silabs,si5351.yaml
@@ -0,0 +1,265 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/clock/silabs,si5351.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Silicon Labs Si5351A/B/C programmable I2C clock generators
+
+description: |
+ The Silicon Labs Si5351A/B/C are programmable I2C clock generators with up to
+ 8 outputs. Si5351A also has a reduced pin-count package (10-MSOP) where only 3
+ output clocks are accessible. The internal structure of the clock generators
+ can be found in [1].
+
+ [1] Si5351A/B/C Data Sheet
+ https://www.skyworksinc.com/-/media/Skyworks/SL/documents/public/data-sheets/Si5351-B.pdf
+
+maintainers:
+ - Alvin Šipraga <alsi@bang-olufsen.dk>
+
+properties:
+ compatible:
+ enum:
+ - silabs,si5351a # Si5351A, 20-QFN package
+ - silabs,si5351a-msop # Si5351A, 10-MSOP package
+ - silabs,si5351b # Si5351B, 20-QFN package
+ - silabs,si5351c # Si5351C, 20-QFN package
+
+ reg:
+ enum:
+ - 0x60
+ - 0x61
+
+ "#address-cells":
+ const: 1
+
+ "#size-cells":
+ const: 0
+
+ "#clock-cells":
+ const: 1
+
+ clocks:
+ minItems: 1
+ maxItems: 2
+
+ clock-names:
+ minItems: 1
+ items:
+ - const: xtal
+ - const: clkin
+
+ silabs,pll-source:
+ $ref: /schemas/types.yaml#/definitions/uint32-matrix
+ description: |
+ A list of cell pairs containing a PLL index and its source. Allows to
+ overwrite clock source of the internal PLLs.
+ items:
+ items:
+ - description: PLL A (0) or PLL B (1)
+ enum: [ 0, 1 ]
+ - description: PLL source, XTAL (0) or CLKIN (1, Si5351C only).
+ enum: [ 0, 1 ]
+
+ silabs,pll-reset-mode:
+ $ref: /schemas/types.yaml#/definitions/uint32-matrix
+ minItems: 1
+ maxItems: 2
+ description: A list of cell pairs containing a PLL index and its reset mode.
+ items:
+ items:
+ - description: PLL A (0) or PLL B (1)
+ enum: [ 0, 1 ]
+ - description: |
+ Reset mode for the PLL. Mode can be one of:
+
+ 0 - reset whenever PLL rate is adjusted (default mode)
+ 1 - do not reset when PLL rate is adjusted
+
+ In mode 1, the PLL is only reset if the silabs,pll-reset is
+ specified in one of the clock output child nodes that also sources
+ the PLL. This mode may be preferable if output clocks are expected
+ to be adjusted without glitches.
+ enum: [ 0, 1 ]
+
+patternProperties:
+ "^clkout@[0-7]$":
+ type: object
+
+ additionalProperties: false
+
+ properties:
+ reg:
+ description: Clock output number.
+
+ clock-frequency: true
+
+ silabs,clock-source:
+ $ref: /schemas/types.yaml#/definitions/uint32
+ description: |
+ Source clock of the this output's divider stage.
+
+ 0 - use multisynth N for this output, where N is the output number
+ 1 - use either multisynth 0 (if output number is 0-3) or multisynth 4
+ (otherwise) for this output
+ 2 - use XTAL for this output
+ 3 - use CLKIN for this output (Si5351C only)
+
+ silabs,drive-strength:
+ $ref: /schemas/types.yaml#/definitions/uint32
+ enum: [ 2, 4, 6, 8 ]
+ description: Output drive strength in mA.
+
+ silabs,multisynth-source:
+ $ref: /schemas/types.yaml#/definitions/uint32
+ enum: [ 0, 1 ]
+ description:
+ Source PLL A (0) or B (1) for the corresponding multisynth divider.
+
+ silabs,pll-master:
+ type: boolean
+ description: |
+ The frequency of the source PLL is allowed to be changed by the
+ multisynth when setting the rate of this clock output.
+
+ silabs,pll-reset:
+ type: boolean
+ description: Reset the source PLL when enabling this clock output.
+
+ silabs,disable-state:
+ $ref: /schemas/types.yaml#/definitions/uint32
+ enum: [ 0, 1, 2, 3 ]
+ description: |
+ Clock output disable state. The state can be one of:
+
+ 0 - clock output is driven LOW when disabled
+ 1 - clock output is driven HIGH when disabled
+ 2 - clock output is FLOATING (HIGH-Z) when disabled
+ 3 - clock output is never disabled
+
+ allOf:
+ - if:
+ properties:
+ compatible:
+ contains:
+ const: silabs,si5351a-msop
+ then:
+ properties:
+ reg:
+ maximum: 2
+ else:
+ properties:
+ reg:
+ maximum: 7
+
+ - if:
+ properties:
+ compatible:
+ contains:
+ const: silabs,si5351c
+ then:
+ properties:
+ silabs,clock-source:
+ enum: [ 0, 1, 2, 3 ]
+ else:
+ properties:
+ silabs,clock-source:
+ enum: [ 0, 1, 2 ]
+
+ required:
+ - reg
+
+allOf:
+ - if:
+ properties:
+ compatible:
+ contains:
+ enum:
+ - silabs,si5351a
+ - silabs,si5351a-msop
+ - silabs,si5351b
+ then:
+ properties:
+ clocks:
+ maxItems: 1
+ clock-names:
+ maxItems: 1
+
+required:
+ - reg
+ - "#address-cells"
+ - "#size-cells"
+ - "#clock-cells"
+ - clocks
+ - clock-names
+
+unevaluatedProperties: false
+
+examples:
+ - |
+ i2c {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ clock-generator@60 {
+ compatible = "silabs,si5351a-msop";
+ reg = <0x60>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ #clock-cells = <1>;
+
+ /* Connect XTAL input to 25MHz reference */
+ clocks = <&ref25>;
+ clock-names = "xtal";
+
+ /* Use XTAL input as source of PLL0 and PLL1 */
+ silabs,pll-source = <0 0>, <1 0>;
+
+ /* Don't reset PLL1 on rate adjustment */
+ silabs,pll-reset-mode = <1 1>;
+
+ /*
+ * Overwrite CLK0 configuration with:
+ * - 8 mA output drive strength
+ * - PLL0 as clock source of multisynth 0
+ * - Multisynth 0 as clock source of output divider
+ * - Multisynth 0 can change PLL0
+ * - Set initial clock frequency of 74.25MHz
+ */
+ clkout@0 {
+ reg = <0>;
+ silabs,drive-strength = <8>;
+ silabs,multisynth-source = <0>;
+ silabs,clock-source = <0>;
+ silabs,pll-master;
+ clock-frequency = <74250000>;
+ };
+
+ /*
+ * Overwrite CLK1 configuration with:
+ * - 4 mA output drive strength
+ * - PLL1 as clock source of multisynth 1
+ * - Multisynth 1 as clock source of output divider
+ * - Multisynth 1 can change PLL1
+ * - Reset PLL1 when enabling this clock output
+ */
+ clkout@1 {
+ reg = <1>;
+ silabs,drive-strength = <4>;
+ silabs,multisynth-source = <1>;
+ silabs,clock-source = <0>;
+ silabs,pll-master;
+ silabs,pll-reset;
+ };
+
+ /*
+ * Overwrite CLK2 configuration with:
+ * - XTAL as clock source of output divider
+ */
+ clkout@2 {
+ reg = <2>;
+ silabs,clock-source = <2>;
+ };
+ };
+ };
diff --git a/dts/upstream/Bindings/clock/sophgo,cv1800-clk.yaml b/dts/upstream/Bindings/clock/sophgo,cv1800-clk.yaml
new file mode 100644
index 0000000..c1dc246
--- /dev/null
+++ b/dts/upstream/Bindings/clock/sophgo,cv1800-clk.yaml
@@ -0,0 +1,46 @@
+# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/clock/sophgo,cv1800-clk.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Sophgo CV1800 Series Clock Controller
+
+maintainers:
+ - Inochi Amaoto <inochiama@outlook.com>
+
+properties:
+ compatible:
+ enum:
+ - sophgo,cv1800-clk
+ - sophgo,cv1810-clk
+
+ reg:
+ maxItems: 1
+
+ clocks:
+ maxItems: 1
+
+ "#clock-cells":
+ const: 1
+ description:
+ See <dt-bindings/clock/sophgo,cv1800.h> for valid indices.
+
+required:
+ - compatible
+ - reg
+ - clocks
+ - "#clock-cells"
+
+additionalProperties: false
+
+examples:
+ - |
+ clock-controller@3002000 {
+ compatible = "sophgo,cv1800-clk";
+ reg = <0x03002000 0x1000>;
+ clocks = <&osc>;
+ #clock-cells = <1>;
+ };
+
+...
diff --git a/dts/upstream/Bindings/clock/st,stm32mp25-rcc.yaml b/dts/upstream/Bindings/clock/st,stm32mp25-rcc.yaml
new file mode 100644
index 0000000..7732e79
--- /dev/null
+++ b/dts/upstream/Bindings/clock/st,stm32mp25-rcc.yaml
@@ -0,0 +1,76 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/clock/st,stm32mp25-rcc.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: STM32MP25 Reset Clock Controller
+
+maintainers:
+ - Gabriel Fernandez <gabriel.fernandez@foss.st.com>
+
+description: |
+ The RCC hardware block is both a reset and a clock controller.
+ RCC makes also power management (resume/supend).
+
+ See also::
+ include/dt-bindings/clock/st,stm32mp25-rcc.h
+ include/dt-bindings/reset/st,stm32mp25-rcc.h
+
+properties:
+ compatible:
+ enum:
+ - st,stm32mp25-rcc
+
+ reg:
+ maxItems: 1
+
+ '#clock-cells':
+ const: 1
+
+ '#reset-cells':
+ const: 1
+
+ clocks:
+ items:
+ - description: CK_SCMI_HSE High Speed External oscillator (8 to 48 MHz)
+ - description: CK_SCMI_HSI High Speed Internal oscillator (~ 64 MHz)
+ - description: CK_SCMI_MSI Low Power Internal oscillator (~ 4 MHz or ~ 16 MHz)
+ - description: CK_SCMI_LSE Low Speed External oscillator (32 KHz)
+ - description: CK_SCMI_LSI Low Speed Internal oscillator (~ 32 KHz)
+
+ clock-names:
+ items:
+ - const: hse
+ - const: hsi
+ - const: msi
+ - const: lse
+ - const: lsi
+
+required:
+ - compatible
+ - reg
+ - '#clock-cells'
+ - '#reset-cells'
+ - clocks
+ - clock-names
+
+additionalProperties: false
+
+examples:
+ - |
+ #include <dt-bindings/clock/st,stm32mp25-rcc.h>
+
+ rcc: clock-controller@44200000 {
+ compatible = "st,stm32mp25-rcc";
+ reg = <0x44200000 0x10000>;
+ #clock-cells = <1>;
+ #reset-cells = <1>;
+ clock-names = "hse", "hsi", "msi", "lse", "lsi";
+ clocks = <&scmi_clk CK_SCMI_HSE>,
+ <&scmi_clk CK_SCMI_HSI>,
+ <&scmi_clk CK_SCMI_MSI>,
+ <&scmi_clk CK_SCMI_LSE>,
+ <&scmi_clk CK_SCMI_LSI>;
+ };
+...
diff --git a/dts/upstream/Bindings/clock/xlnx,clocking-wizard.yaml b/dts/upstream/Bindings/clock/xlnx,clocking-wizard.yaml
index 02bd556..9d5324d 100644
--- a/dts/upstream/Bindings/clock/xlnx,clocking-wizard.yaml
+++ b/dts/upstream/Bindings/clock/xlnx,clocking-wizard.yaml
@@ -20,6 +20,7 @@
- xlnx,clocking-wizard
- xlnx,clocking-wizard-v5.2
- xlnx,clocking-wizard-v6.0
+ - xlnx,versal-clk-wizard
reg:
diff --git a/dts/upstream/Bindings/clock/xlnx,versal-clk.yaml b/dts/upstream/Bindings/clock/xlnx,versal-clk.yaml
index 1ba687d..bef109d 100644
--- a/dts/upstream/Bindings/clock/xlnx,versal-clk.yaml
+++ b/dts/upstream/Bindings/clock/xlnx,versal-clk.yaml
@@ -31,11 +31,11 @@
clocks:
description: List of clock specifiers which are external input
clocks to the given clock controller.
- minItems: 3
+ minItems: 2
maxItems: 8
clock-names:
- minItems: 3
+ minItems: 2
maxItems: 8
required:
@@ -59,14 +59,33 @@
clocks:
items:
- description: reference clock
- - description: alternate reference clock
- description: alternate reference clock for programmable logic
clock-names:
items:
- const: ref
- - const: alt_ref
+ - const: pl_alt_ref
+
+ - if:
+ properties:
+ compatible:
+ contains:
+ enum:
+ - xlnx,versal-net-clk
+
+ then:
+ properties:
+ clocks:
+ items:
+ - description: reference clock
+ - description: alternate reference clock for programmable logic
+ - description: alternate reference clock
+
+ clock-names:
+ items:
+ - const: ref
- const: pl_alt_ref
+ - const: alt_ref
- if:
properties:
@@ -110,8 +129,8 @@
versal_clk: clock-controller {
#clock-cells = <1>;
compatible = "xlnx,versal-clk";
- clocks = <&ref>, <&alt_ref>, <&pl_alt_ref>;
- clock-names = "ref", "alt_ref", "pl_alt_ref";
+ clocks = <&ref>, <&pl_alt_ref>;
+ clock-names = "ref", "pl_alt_ref";
};
};
};
diff --git a/dts/upstream/Bindings/connector/usb-connector.yaml b/dts/upstream/Bindings/connector/usb-connector.yaml
index 7c8a3e8..fb216ce 100644
--- a/dts/upstream/Bindings/connector/usb-connector.yaml
+++ b/dts/upstream/Bindings/connector/usb-connector.yaml
@@ -66,7 +66,6 @@
Particularly, if use an output GPIO to control a VBUS regulator, should
model it as a regulator. See bindings/regulator/fixed-regulator.yaml
- # The following are optional properties for "usb-c-connector".
power-role:
description: Determines the power role that the Type C connector will
support. "dual" refers to Dual Role Port (DRP).
@@ -119,30 +118,6 @@
# The following are optional properties for "usb-c-connector" with power
# delivery support.
- source-pdos:
- description: An array of u32 with each entry providing supported power
- source data object(PDO), the detailed bit definitions of PDO can be found
- in "Universal Serial Bus Power Delivery Specification" chapter 6.4.1.2
- Source_Capabilities Message, the order of each entry(PDO) should follow
- the PD spec chapter 6.4.1. Required for power source and power dual role.
- User can specify the source PDO array via PDO_FIXED/BATT/VAR/PPS_APDO()
- defined in dt-bindings/usb/pd.h.
- minItems: 1
- maxItems: 7
- $ref: /schemas/types.yaml#/definitions/uint32-array
-
- sink-pdos:
- description: An array of u32 with each entry providing supported power sink
- data object(PDO), the detailed bit definitions of PDO can be found in
- "Universal Serial Bus Power Delivery Specification" chapter 6.4.1.3
- Sink Capabilities Message, the order of each entry(PDO) should follow the
- PD spec chapter 6.4.1. Required for power sink and power dual role. User
- can specify the sink PDO array via PDO_FIXED/BATT/VAR/PPS_APDO() defined
- in dt-bindings/usb/pd.h.
- minItems: 1
- maxItems: 7
- $ref: /schemas/types.yaml#/definitions/uint32-array
-
sink-vdos:
description: An array of u32 with each entry, a Vendor Defined Message Object (VDO),
providing additional information corresponding to the product, the detailed bit
@@ -166,10 +141,43 @@
maxItems: 6
$ref: /schemas/types.yaml#/definitions/uint32-array
+ accessory-mode-audio:
+ type: boolean
+ description: Whether the device supports Audio Adapter Accessory Mode. This
+ is only necessary if there are no other means to discover supported
+ alternative modes (e.g. through the UCSI firmware interface).
+
- op-sink-microwatt:
- description: Sink required operating power in microwatt, if source can't
- offer the power, Capability Mismatch is set. Required for power sink and
- power dual role.
+ accessory-mode-debug:
+ type: boolean
+ description: Whether the device supports Debug Accessory Mode. This
+ is only necessary if there are no other means to discover supported
+ alternative modes (e.g. through the UCSI firmware interface).
+
+ altmodes:
+ type: object
+ description: List of Alternative Modes supported by the schematics on the
+ particular device. This is only necessary if there are no other means to
+ discover supported alternative modes (e.g. through the UCSI firmware
+ interface).
+
+ additionalProperties: false
+
+ patternProperties:
+ "^(displayport)$":
+ type: object
+ description:
+ A single USB-C Alternative Mode as supported by the USB-C connector logic.
+
+ additionalProperties: false
+
+ properties:
+ svid:
+ $ref: /schemas/types.yaml#/definitions/uint16
+ description: Unique value assigned by USB-IF to the Vendor / AltMode.
+ enum: [ 0xff01 ]
+ vdo:
+ $ref: /schemas/types.yaml#/definitions/uint32
+ description: VDO returned by Discover Modes USB PD command.
port:
$ref: /schemas/graph.yaml#/properties/port
@@ -231,6 +239,20 @@
SNK_READY for non-pd link.
type: boolean
+ capabilities:
+ description: A child node to contain all the selectable USB Power Delivery capabilities.
+ type: object
+
+ patternProperties:
+ "^caps-[0-9]+$":
+ description: Child nodes under "capabilities" node. Each node contains a selectable USB
+ Power Delivery capability.
+ type: object
+ $ref: "#/$defs/capabilities"
+ unevaluatedProperties: false
+
+ additionalProperties: false
+
dependencies:
sink-vdos-v1: [ sink-vdos ]
sink-vdos: [ sink-vdos-v1 ]
@@ -238,7 +260,42 @@
required:
- compatible
+$defs:
+ capabilities:
+ type: object
+
+ properties:
+ source-pdos:
+ description: An array of u32 with each entry providing supported power
+ source data object(PDO), the detailed bit definitions of PDO can be found
+ in "Universal Serial Bus Power Delivery Specification" chapter 6.4.1.2
+ Source_Capabilities Message, the order of each entry(PDO) should follow
+ the PD spec chapter 6.4.1. Required for power source and power dual role.
+ User can specify the source PDO array via PDO_FIXED/BATT/VAR/PPS_APDO()
+ defined in dt-bindings/usb/pd.h.
+ minItems: 1
+ maxItems: 7
+ $ref: /schemas/types.yaml#/definitions/uint32-array
+
+ sink-pdos:
+ description: An array of u32 with each entry providing supported power sink
+ data object(PDO), the detailed bit definitions of PDO can be found in
+ "Universal Serial Bus Power Delivery Specification" chapter 6.4.1.3
+ Sink Capabilities Message, the order of each entry(PDO) should follow the
+ PD spec chapter 6.4.1. Required for power sink and power dual role. User
+ can specify the sink PDO array via PDO_FIXED/BATT/VAR/PPS_APDO() defined
+ in dt-bindings/usb/pd.h.
+ minItems: 1
+ maxItems: 7
+ $ref: /schemas/types.yaml#/definitions/uint32-array
+
+ op-sink-microwatt:
+ description: Sink required operating power in microwatt, if source can't
+ offer the power, Capability Mismatch is set. Required for power sink and
+ power dual role.
+
allOf:
+ - $ref: "#/$defs/capabilities"
- if:
properties:
compatible:
@@ -267,7 +324,7 @@
- typec-power-opmode
- new-source-frs-typec-current
-additionalProperties: false
+unevaluatedProperties: false
examples:
# Micro-USB connector with HS lines routed via controller (MUIC).
@@ -289,6 +346,13 @@
compatible = "usb-c-connector";
label = "USB-C";
+ altmodes {
+ displayport {
+ svid = /bits/ 16 <0xff01>;
+ vdo = <0x00001c46>;
+ };
+ };
+
ports {
#address-cells = <1>;
#size-cells = <0>;
diff --git a/dts/upstream/Bindings/cpu/idle-states.yaml b/dts/upstream/Bindings/cpu/idle-states.yaml
index b3a5356..239480e 100644
--- a/dts/upstream/Bindings/cpu/idle-states.yaml
+++ b/dts/upstream/Bindings/cpu/idle-states.yaml
@@ -243,9 +243,66 @@
just supports idle_standby, an idle-states node is not required.
===========================================
- 6 - References
+ 6 - Qualcomm specific STATES
===========================================
+ Idle states have different enter/exit latency and residency values.
+ The idle states supported by the QCOM SoC are defined as -
+
+ * Standby
+ * Retention
+ * Standalone Power Collapse (Standalone PC or SPC)
+ * Power Collapse (PC)
+
+ Standby: Standby does a little more in addition to architectural clock gating.
+ When the WFI instruction is executed the ARM core would gate its internal
+ clocks. In addition to gating the clocks, QCOM cpus use this instruction as a
+ trigger to execute the SPM state machine. The SPM state machine waits for the
+ interrupt to trigger the core back in to active. This triggers the cache
+ hierarchy to enter standby states, when all cpus are idle. An interrupt brings
+ the SPM state machine out of its wait, the next step is to ensure that the
+ cache hierarchy is also out of standby, and then the cpu is allowed to resume
+ execution. This state is defined as a generic ARM WFI state by the ARM cpuidle
+ driver and is not defined in the DT. The SPM state machine should be
+ configured to execute this state by default and after executing every other
+ state below.
+
+ Retention: Retention is a low power state where the core is clock gated and
+ the memory and the registers associated with the core are retained. The
+ voltage may be reduced to the minimum value needed to keep the processor
+ registers active. The SPM should be configured to execute the retention
+ sequence and would wait for interrupt, before restoring the cpu to execution
+ state. Retention may have a slightly higher latency than Standby.
+
+ Standalone PC: A cpu can power down and warmboot if there is a sufficient time
+ between the time it enters idle and the next known wake up. SPC mode is used
+ to indicate a core entering a power down state without consulting any other
+ cpu or the system resources. This helps save power only on that core. The SPM
+ sequence for this idle state is programmed to power down the supply to the
+ core, wait for the interrupt, restore power to the core, and ensure the
+ system state including cache hierarchy is ready before allowing core to
+ resume. Applying power and resetting the core causes the core to warmboot
+ back into Elevation Level (EL) which trampolines the control back to the
+ kernel. Entering a power down state for the cpu, needs to be done by trapping
+ into a EL. Failing to do so, would result in a crash enforced by the warm boot
+ code in the EL for the SoC. On SoCs with write-back L1 cache, the cache has to
+ be flushed in s/w, before powering down the core.
+
+ Power Collapse: This state is similar to the SPC mode, but distinguishes
+ itself in that the cpu acknowledges and permits the SoC to enter deeper sleep
+ modes. In a hierarchical power domain SoC, this means L2 and other caches can
+ be flushed, system bus, clocks - lowered, and SoC main XO clock gated and
+ voltages reduced, provided all cpus enter this state. Since the span of low
+ power modes possible at this state is vast, the exit latency and the residency
+ of this low power mode would be considered high even though at a cpu level,
+ this essentially is cpu power down. The SPM in this state also may handshake
+ with the Resource power manager (RPM) processor in the SoC to indicate a
+ complete application processor subsystem shut down.
+
+ ===========================================
+ 7 - References
+ ===========================================
+
[1] ARM Linux Kernel documentation - CPUs bindings
Documentation/devicetree/bindings/arm/cpus.yaml
@@ -301,9 +358,16 @@
properties:
compatible:
- enum:
- - arm,idle-state
- - riscv,idle-state
+ oneOf:
+ - items:
+ - enum:
+ - qcom,idle-state-ret
+ - qcom,idle-state-spc
+ - qcom,idle-state-pc
+ - const: arm,idle-state
+ - enum:
+ - arm,idle-state
+ - riscv,idle-state
arm,psci-suspend-param:
$ref: /schemas/types.yaml#/definitions/uint32
@@ -852,4 +916,13 @@
};
};
+ // Example 4 - Qualcomm SPC
+ idle-states {
+ cpu_spc: cpu-spc {
+ compatible = "qcom,idle-state-spc", "arm,idle-state";
+ entry-latency-us = <150>;
+ exit-latency-us = <200>;
+ min-residency-us = <2000>;
+ };
+ };
...
diff --git a/dts/upstream/Bindings/crypto/inside-secure,safexcel.yaml b/dts/upstream/Bindings/crypto/inside-secure,safexcel.yaml
new file mode 100644
index 0000000..ef07258
--- /dev/null
+++ b/dts/upstream/Bindings/crypto/inside-secure,safexcel.yaml
@@ -0,0 +1,86 @@
+# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/crypto/inside-secure,safexcel.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Inside Secure SafeXcel cryptographic engine
+
+maintainers:
+ - Antoine Tenart <atenart@kernel.org>
+
+properties:
+ compatible:
+ oneOf:
+ - const: inside-secure,safexcel-eip197b
+ - const: inside-secure,safexcel-eip197d
+ - const: inside-secure,safexcel-eip97ies
+ - const: inside-secure,safexcel-eip197
+ description: Equivalent of inside-secure,safexcel-eip197b
+ deprecated: true
+ - const: inside-secure,safexcel-eip97
+ description: Equivalent of inside-secure,safexcel-eip97ies
+ deprecated: true
+
+ reg:
+ maxItems: 1
+
+ interrupts:
+ maxItems: 6
+
+ interrupt-names:
+ items:
+ - const: ring0
+ - const: ring1
+ - const: ring2
+ - const: ring3
+ - const: eip
+ - const: mem
+
+ clocks:
+ minItems: 1
+ maxItems: 2
+
+ clock-names:
+ minItems: 1
+ items:
+ - const: core
+ - const: reg
+
+required:
+ - reg
+ - interrupts
+ - interrupt-names
+
+allOf:
+ - if:
+ properties:
+ clocks:
+ minItems: 2
+ then:
+ properties:
+ clock-names:
+ minItems: 2
+ required:
+ - clock-names
+
+additionalProperties: false
+
+examples:
+ - |
+ #include <dt-bindings/interrupt-controller/arm-gic.h>
+ #include <dt-bindings/interrupt-controller/irq.h>
+
+ crypto@800000 {
+ compatible = "inside-secure,safexcel-eip197b";
+ reg = <0x800000 0x200000>;
+ interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "ring0", "ring1", "ring2", "ring3", "eip", "mem";
+ clocks = <&cpm_syscon0 1 26>;
+ clock-names = "core";
+ };
diff --git a/dts/upstream/Bindings/crypto/inside-secure-safexcel.txt b/dts/upstream/Bindings/crypto/inside-secure-safexcel.txt
deleted file mode 100644
index 3bbf144..0000000
--- a/dts/upstream/Bindings/crypto/inside-secure-safexcel.txt
+++ /dev/null
@@ -1,40 +0,0 @@
-Inside Secure SafeXcel cryptographic engine
-
-Required properties:
-- compatible: Should be "inside-secure,safexcel-eip197b",
- "inside-secure,safexcel-eip197d" or
- "inside-secure,safexcel-eip97ies".
-- reg: Base physical address of the engine and length of memory mapped region.
-- interrupts: Interrupt numbers for the rings and engine.
-- interrupt-names: Should be "ring0", "ring1", "ring2", "ring3", "eip", "mem".
-
-Optional properties:
-- clocks: Reference to the crypto engine clocks, the second clock is
- needed for the Armada 7K/8K SoCs.
-- clock-names: mandatory if there is a second clock, in this case the
- name must be "core" for the first clock and "reg" for
- the second one.
-
-Backward compatibility:
-Two compatibles are kept for backward compatibility, but shouldn't be used for
-new submissions:
-- "inside-secure,safexcel-eip197" is equivalent to
- "inside-secure,safexcel-eip197b".
-- "inside-secure,safexcel-eip97" is equivalent to
- "inside-secure,safexcel-eip97ies".
-
-Example:
-
- crypto: crypto@800000 {
- compatible = "inside-secure,safexcel-eip197b";
- reg = <0x800000 0x200000>;
- interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>;
- interrupt-names = "mem", "ring0", "ring1", "ring2", "ring3",
- "eip";
- clocks = <&cpm_syscon0 1 26>;
- };
diff --git a/dts/upstream/Bindings/crypto/qcom,inline-crypto-engine.yaml b/dts/upstream/Bindings/crypto/qcom,inline-crypto-engine.yaml
index ca4f7d1..09e4315 100644
--- a/dts/upstream/Bindings/crypto/qcom,inline-crypto-engine.yaml
+++ b/dts/upstream/Bindings/crypto/qcom,inline-crypto-engine.yaml
@@ -16,6 +16,7 @@
- qcom,sa8775p-inline-crypto-engine
- qcom,sm8450-inline-crypto-engine
- qcom,sm8550-inline-crypto-engine
+ - qcom,sm8650-inline-crypto-engine
- const: qcom,inline-crypto-engine
reg:
diff --git a/dts/upstream/Bindings/crypto/qcom,prng.yaml b/dts/upstream/Bindings/crypto/qcom,prng.yaml
index 13070db..89c8800 100644
--- a/dts/upstream/Bindings/crypto/qcom,prng.yaml
+++ b/dts/upstream/Bindings/crypto/qcom,prng.yaml
@@ -21,6 +21,7 @@
- qcom,sc7280-trng
- qcom,sm8450-trng
- qcom,sm8550-trng
+ - qcom,sm8650-trng
- const: qcom,trng
reg:
diff --git a/dts/upstream/Bindings/crypto/qcom-qce.yaml b/dts/upstream/Bindings/crypto/qcom-qce.yaml
index 8e665d9..a48bd38 100644
--- a/dts/upstream/Bindings/crypto/qcom-qce.yaml
+++ b/dts/upstream/Bindings/crypto/qcom-qce.yaml
@@ -44,10 +44,12 @@
- items:
- enum:
+ - qcom,sc7280-qce
- qcom,sm8250-qce
- qcom,sm8350-qce
- qcom,sm8450-qce
- qcom,sm8550-qce
+ - qcom,sm8650-qce
- const: qcom,sm8150-qce
- const: qcom,qce
@@ -96,6 +98,7 @@
- qcom,crypto-v5.4
- qcom,ipq6018-qce
- qcom,ipq8074-qce
+ - qcom,ipq9574-qce
- qcom,msm8996-qce
- qcom,sdm845-qce
then:
@@ -129,6 +132,17 @@
- clocks
- clock-names
+ - if:
+ properties:
+ compatible:
+ contains:
+ enum:
+ - qcom,sm8150-qce
+ then:
+ properties:
+ clocks: false
+ clock-names: false
+
required:
- compatible
- reg
diff --git a/dts/upstream/Bindings/display/bridge/lontium,lt8912b.yaml b/dts/upstream/Bindings/display/bridge/lontium,lt8912b.yaml
index f201ae4..2cef252 100644
--- a/dts/upstream/Bindings/display/bridge/lontium,lt8912b.yaml
+++ b/dts/upstream/Bindings/display/bridge/lontium,lt8912b.yaml
@@ -55,6 +55,27 @@
- port@0
- port@1
+ vcchdmipll-supply:
+ description: A 1.8V supply that powers the HDMI PLL.
+
+ vcchdmitx-supply:
+ description: A 1.8V supply that powers the HDMI TX part.
+
+ vcclvdspll-supply:
+ description: A 1.8V supply that powers the LVDS PLL.
+
+ vcclvdstx-supply:
+ description: A 1.8V supply that powers the LVDS TX part.
+
+ vccmipirx-supply:
+ description: A 1.8V supply that powers the MIPI RX part.
+
+ vccsysclk-supply:
+ description: A 1.8V supply that powers the SYSCLK.
+
+ vdd-supply:
+ description: A 1.8V supply that powers the digital part.
+
required:
- compatible
- reg
diff --git a/dts/upstream/Bindings/display/bridge/nxp,tda998x.yaml b/dts/upstream/Bindings/display/bridge/nxp,tda998x.yaml
index 21d995f2..b8e9cf6 100644
--- a/dts/upstream/Bindings/display/bridge/nxp,tda998x.yaml
+++ b/dts/upstream/Bindings/display/bridge/nxp,tda998x.yaml
@@ -29,19 +29,22 @@
audio-ports:
description:
- Array of 8-bit values, 2 values per DAI (Documentation/sound/soc/dai.rst).
+ Array of 2 values per DAI (Documentation/sound/soc/dai.rst).
The implementation allows one or two DAIs.
If two DAIs are defined, they must be of different type.
$ref: /schemas/types.yaml#/definitions/uint32-matrix
+ minItems: 1
+ maxItems: 2
items:
- minItems: 1
items:
- description: |
The first value defines the DAI type: TDA998x_SPDIF or TDA998x_I2S
(see include/dt-bindings/display/tda998x.h).
+ enum: [ 1, 2 ]
- description:
The second value defines the tda998x AP_ENA reg content when the
DAI in question is used.
+ maximum: 0xff
'#sound-dai-cells':
enum: [ 0, 1 ]
diff --git a/dts/upstream/Bindings/display/mediatek/mediatek,aal.yaml b/dts/upstream/Bindings/display/mediatek/mediatek,aal.yaml
index 7fd42c8..b4c28e9 100644
--- a/dts/upstream/Bindings/display/mediatek/mediatek,aal.yaml
+++ b/dts/upstream/Bindings/display/mediatek/mediatek,aal.yaml
@@ -24,6 +24,7 @@
- enum:
- mediatek,mt8173-disp-aal
- mediatek,mt8183-disp-aal
+ - mediatek,mt8195-mdp3-aal
- items:
- enum:
- mediatek,mt2712-disp-aal
diff --git a/dts/upstream/Bindings/display/mediatek/mediatek,color.yaml b/dts/upstream/Bindings/display/mediatek/mediatek,color.yaml
index f21e440..b886ca0 100644
--- a/dts/upstream/Bindings/display/mediatek/mediatek,color.yaml
+++ b/dts/upstream/Bindings/display/mediatek/mediatek,color.yaml
@@ -26,6 +26,7 @@
- mediatek,mt2701-disp-color
- mediatek,mt8167-disp-color
- mediatek,mt8173-disp-color
+ - mediatek,mt8195-mdp3-color
- items:
- enum:
- mediatek,mt7623-disp-color
diff --git a/dts/upstream/Bindings/display/mediatek/mediatek,dsi.yaml b/dts/upstream/Bindings/display/mediatek/mediatek,dsi.yaml
index ed24b61..8611319 100644
--- a/dts/upstream/Bindings/display/mediatek/mediatek,dsi.yaml
+++ b/dts/upstream/Bindings/display/mediatek/mediatek,dsi.yaml
@@ -34,6 +34,10 @@
- enum:
- mediatek,mt6795-dsi
- const: mediatek,mt8173-dsi
+ - items:
+ - enum:
+ - mediatek,mt8195-dsi
+ - const: mediatek,mt8183-dsi
reg:
maxItems: 1
diff --git a/dts/upstream/Bindings/display/mediatek/mediatek,ethdr.yaml b/dts/upstream/Bindings/display/mediatek/mediatek,ethdr.yaml
index 801fa66..6778823 100644
--- a/dts/upstream/Bindings/display/mediatek/mediatek,ethdr.yaml
+++ b/dts/upstream/Bindings/display/mediatek/mediatek,ethdr.yaml
@@ -23,7 +23,11 @@
properties:
compatible:
- const: mediatek,mt8195-disp-ethdr
+ oneOf:
+ - const: mediatek,mt8195-disp-ethdr
+ - items:
+ - const: mediatek,mt8188-disp-ethdr
+ - const: mediatek,mt8195-disp-ethdr
reg:
maxItems: 7
diff --git a/dts/upstream/Bindings/display/mediatek/mediatek,mdp-rdma.yaml b/dts/upstream/Bindings/display/mediatek/mediatek,mdp-rdma.yaml
deleted file mode 100644
index dd12e2f..0000000
--- a/dts/upstream/Bindings/display/mediatek/mediatek,mdp-rdma.yaml
+++ /dev/null
@@ -1,88 +0,0 @@
-# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
-%YAML 1.2
----
-$id: http://devicetree.org/schemas/display/mediatek/mediatek,mdp-rdma.yaml#
-$schema: http://devicetree.org/meta-schemas/core.yaml#
-
-title: MediaTek MDP RDMA
-
-maintainers:
- - Chun-Kuang Hu <chunkuang.hu@kernel.org>
- - Philipp Zabel <p.zabel@pengutronix.de>
-
-description:
- The MediaTek MDP RDMA stands for Read Direct Memory Access.
- It provides real time data to the back-end panel driver, such as DSI,
- DPI and DP_INTF.
- It contains one line buffer to store the sufficient pixel data.
- RDMA device node must be siblings to the central MMSYS_CONFIG node.
- For a description of the MMSYS_CONFIG binding, see
- Documentation/devicetree/bindings/arm/mediatek/mediatek,mmsys.yaml for details.
-
-properties:
- compatible:
- const: mediatek,mt8195-vdo1-rdma
-
- reg:
- maxItems: 1
-
- interrupts:
- maxItems: 1
-
- power-domains:
- maxItems: 1
-
- clocks:
- items:
- - description: RDMA Clock
-
- iommus:
- maxItems: 1
-
- mediatek,gce-client-reg:
- description:
- The register of display function block to be set by gce. There are 4 arguments,
- such as gce node, subsys id, offset and register size. The subsys id that is
- mapping to the register of display function blocks is defined in the gce header
- include/dt-bindings/gce/<chip>-gce.h of each chips.
- $ref: /schemas/types.yaml#/definitions/phandle-array
- items:
- items:
- - description: phandle of GCE
- - description: GCE subsys id
- - description: register offset
- - description: register size
- maxItems: 1
-
-required:
- - compatible
- - reg
- - power-domains
- - clocks
- - iommus
- - mediatek,gce-client-reg
-
-additionalProperties: false
-
-examples:
- - |
- #include <dt-bindings/interrupt-controller/arm-gic.h>
- #include <dt-bindings/clock/mt8195-clk.h>
- #include <dt-bindings/power/mt8195-power.h>
- #include <dt-bindings/gce/mt8195-gce.h>
- #include <dt-bindings/memory/mt8195-memory-port.h>
-
- soc {
- #address-cells = <2>;
- #size-cells = <2>;
-
- rdma@1c104000 {
- compatible = "mediatek,mt8195-vdo1-rdma";
- reg = <0 0x1c104000 0 0x1000>;
- interrupts = <GIC_SPI 495 IRQ_TYPE_LEVEL_HIGH 0>;
- clocks = <&vdosys1 CLK_VDO1_MDP_RDMA0>;
- power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS1>;
- iommus = <&iommu_vdo M4U_PORT_L2_MDP_RDMA0>;
- mediatek,gce-client-reg = <&gce0 SUBSYS_1c10XXXX 0x4000 0x1000>;
- };
- };
diff --git a/dts/upstream/Bindings/display/mediatek/mediatek,merge.yaml b/dts/upstream/Bindings/display/mediatek/mediatek,merge.yaml
index eead5cb..dae8392 100644
--- a/dts/upstream/Bindings/display/mediatek/mediatek,merge.yaml
+++ b/dts/upstream/Bindings/display/mediatek/mediatek,merge.yaml
@@ -24,9 +24,13 @@
- enum:
- mediatek,mt8173-disp-merge
- mediatek,mt8195-disp-merge
+ - mediatek,mt8195-mdp3-merge
- items:
- const: mediatek,mt6795-disp-merge
- const: mediatek,mt8173-disp-merge
+ - items:
+ - const: mediatek,mt8188-disp-merge
+ - const: mediatek,mt8195-disp-merge
reg:
maxItems: 1
diff --git a/dts/upstream/Bindings/display/mediatek/mediatek,ovl.yaml b/dts/upstream/Bindings/display/mediatek/mediatek,ovl.yaml
index 3e1069b..c471a18 100644
--- a/dts/upstream/Bindings/display/mediatek/mediatek,ovl.yaml
+++ b/dts/upstream/Bindings/display/mediatek/mediatek,ovl.yaml
@@ -26,6 +26,7 @@
- mediatek,mt8173-disp-ovl
- mediatek,mt8183-disp-ovl
- mediatek,mt8192-disp-ovl
+ - mediatek,mt8195-mdp3-ovl
- items:
- enum:
- mediatek,mt7623-disp-ovl
diff --git a/dts/upstream/Bindings/display/mediatek/mediatek,padding.yaml b/dts/upstream/Bindings/display/mediatek/mediatek,padding.yaml
new file mode 100644
index 0000000..be07bbd
--- /dev/null
+++ b/dts/upstream/Bindings/display/mediatek/mediatek,padding.yaml
@@ -0,0 +1,83 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/display/mediatek/mediatek,padding.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: MediaTek Display Padding
+
+maintainers:
+ - Chun-Kuang Hu <chunkuang.hu@kernel.org>
+ - Philipp Zabel <p.zabel@pengutronix.de>
+
+description:
+ Padding provides ability to add pixels to width and height of a layer with
+ specified colors. Due to hardware design, Mixer in VDOSYS1 requires
+ width of a layer to be 2-pixel-align, or 4-pixel-align when ETHDR is enabled,
+ we need Padding to deal with odd width.
+ Please notice that even if the Padding is in bypass mode, settings in
+ register must be cleared to 0, or undefined behaviors could happen.
+
+properties:
+ compatible:
+ enum:
+ - mediatek,mt8188-disp-padding
+ - mediatek,mt8195-mdp3-padding
+
+ reg:
+ maxItems: 1
+
+ power-domains:
+ maxItems: 1
+
+ clocks:
+ items:
+ - description: Padding's clocks
+
+ mediatek,gce-client-reg:
+ description:
+ GCE (Global Command Engine) is a multi-core micro processor that helps
+ its clients to execute commands without interrupting CPU. This property
+ describes GCE client's information that is composed by 4 fields.
+ 1. Phandle of the GCE (there may be several GCE processors)
+ 2. Sub-system ID defined in the dt-binding like a user ID
+ (Please refer to include/dt-bindings/gce/<chip>-gce.h)
+ 3. Offset from base address of the subsys you are at
+ 4. Size of the register the client needs
+ $ref: /schemas/types.yaml#/definitions/phandle-array
+ items:
+ items:
+ - description: Phandle of the GCE
+ - description: Subsys ID defined in the dt-binding
+ - description: Offset from base address of the subsys
+ - description: Size of register
+ maxItems: 1
+
+required:
+ - compatible
+ - reg
+ - power-domains
+ - clocks
+ - mediatek,gce-client-reg
+
+additionalProperties: false
+
+examples:
+ - |
+ #include <dt-bindings/interrupt-controller/arm-gic.h>
+ #include <dt-bindings/clock/mediatek,mt8188-clk.h>
+ #include <dt-bindings/power/mediatek,mt8188-power.h>
+ #include <dt-bindings/gce/mt8195-gce.h>
+
+ soc {
+ #address-cells = <2>;
+ #size-cells = <2>;
+
+ padding0: padding@1c11d000 {
+ compatible = "mediatek,mt8188-disp-padding";
+ reg = <0 0x1c11d000 0 0x1000>;
+ clocks = <&vdosys1 CLK_VDO1_PADDING0>;
+ power-domains = <&spm MT8188_POWER_DOMAIN_VDOSYS1>;
+ mediatek,gce-client-reg = <&gce0 SUBSYS_1c11XXXX 0xd000 0x1000>;
+ };
+ };
diff --git a/dts/upstream/Bindings/display/mediatek/mediatek,split.yaml b/dts/upstream/Bindings/display/mediatek/mediatek,split.yaml
index a8a5c96..e4affc8 100644
--- a/dts/upstream/Bindings/display/mediatek/mediatek,split.yaml
+++ b/dts/upstream/Bindings/display/mediatek/mediatek,split.yaml
@@ -23,6 +23,7 @@
oneOf:
- enum:
- mediatek,mt8173-disp-split
+ - mediatek,mt8195-mdp3-split
- items:
- const: mediatek,mt6795-disp-split
- const: mediatek,mt8173-disp-split
@@ -38,6 +39,21 @@
the power controller specified by phandle. See
Documentation/devicetree/bindings/power/power-domain.yaml for details.
+ mediatek,gce-client-reg:
+ description:
+ The register of display function block to be set by gce. There are 4 arguments,
+ such as gce node, subsys id, offset and register size. The subsys id that is
+ mapping to the register of display function blocks is defined in the gce header
+ include/dt-bindings/gce/<chip>-gce.h of each chips.
+ $ref: /schemas/types.yaml#/definitions/phandle-array
+ items:
+ items:
+ - description: phandle of GCE
+ - description: GCE subsys id
+ - description: register offset
+ - description: register size
+ maxItems: 1
+
clocks:
items:
- description: SPLIT Clock
@@ -48,6 +64,17 @@
- power-domains
- clocks
+allOf:
+ - if:
+ properties:
+ compatible:
+ contains:
+ const: mediatek,mt8195-mdp3-split
+
+ then:
+ required:
+ - mediatek,gce-client-reg
+
additionalProperties: false
examples:
diff --git a/dts/upstream/Bindings/display/msm/dp-controller.yaml b/dts/upstream/Bindings/display/msm/dp-controller.yaml
index dbe398f..ae53cbf 100644
--- a/dts/upstream/Bindings/display/msm/dp-controller.yaml
+++ b/dts/upstream/Bindings/display/msm/dp-controller.yaml
@@ -26,8 +26,10 @@
- qcom,sc8280xp-edp
- qcom,sdm845-dp
- qcom,sm8350-dp
+ - qcom,sm8650-dp
- items:
- enum:
+ - qcom,sm8150-dp
- qcom,sm8250-dp
- qcom,sm8450-dp
- qcom,sm8550-dp
diff --git a/dts/upstream/Bindings/display/msm/dsi-controller-main.yaml b/dts/upstream/Bindings/display/msm/dsi-controller-main.yaml
index c6dbab6..4219936 100644
--- a/dts/upstream/Bindings/display/msm/dsi-controller-main.yaml
+++ b/dts/upstream/Bindings/display/msm/dsi-controller-main.yaml
@@ -25,6 +25,7 @@
- qcom,sc7180-dsi-ctrl
- qcom,sc7280-dsi-ctrl
- qcom,sdm660-dsi-ctrl
+ - qcom,sdm670-dsi-ctrl
- qcom,sdm845-dsi-ctrl
- qcom,sm6115-dsi-ctrl
- qcom,sm6125-dsi-ctrl
@@ -35,6 +36,7 @@
- qcom,sm8350-dsi-ctrl
- qcom,sm8450-dsi-ctrl
- qcom,sm8550-dsi-ctrl
+ - qcom,sm8650-dsi-ctrl
- const: qcom,mdss-dsi-ctrl
- enum:
- qcom,dsi-ctrl-6g-qcm2290
@@ -333,6 +335,7 @@
- qcom,sm8350-dsi-ctrl
- qcom,sm8450-dsi-ctrl
- qcom,sm8550-dsi-ctrl
+ - qcom,sm8650-dsi-ctrl
then:
properties:
clocks:
diff --git a/dts/upstream/Bindings/display/msm/dsi-phy-7nm.yaml b/dts/upstream/Bindings/display/msm/dsi-phy-7nm.yaml
index dd66195..7e764ea 100644
--- a/dts/upstream/Bindings/display/msm/dsi-phy-7nm.yaml
+++ b/dts/upstream/Bindings/display/msm/dsi-phy-7nm.yaml
@@ -22,6 +22,7 @@
- qcom,sm8350-dsi-phy-5nm
- qcom,sm8450-dsi-phy-5nm
- qcom,sm8550-dsi-phy-4nm
+ - qcom,sm8650-dsi-phy-4nm
reg:
items:
diff --git a/dts/upstream/Bindings/display/msm/mdss-common.yaml b/dts/upstream/Bindings/display/msm/mdss-common.yaml
index f69196e..c6305a6 100644
--- a/dts/upstream/Bindings/display/msm/mdss-common.yaml
+++ b/dts/upstream/Bindings/display/msm/mdss-common.yaml
@@ -61,17 +61,27 @@
ranges: true
+ # This is not a perfect description, but it's impossible to discern and match
+ # the entries like we do with interconnect-names
interconnects:
minItems: 1
items:
- description: Interconnect path from mdp0 (or a single mdp) port to the data bus
- description: Interconnect path from mdp1 port to the data bus
+ - description: Interconnect path from CPU to the reg bus
interconnect-names:
- minItems: 1
- items:
- - const: mdp0-mem
- - const: mdp1-mem
+ oneOf:
+ - minItems: 1
+ items:
+ - const: mdp0-mem
+ - const: cpu-cfg
+
+ - minItems: 2
+ items:
+ - const: mdp0-mem
+ - const: mdp1-mem
+ - const: cpu-cfg
resets:
items:
diff --git a/dts/upstream/Bindings/display/msm/qcom,qcm2290-mdss.yaml b/dts/upstream/Bindings/display/msm/qcom,qcm2290-mdss.yaml
index 5ad1556..f0cdb54 100644
--- a/dts/upstream/Bindings/display/msm/qcom,qcm2290-mdss.yaml
+++ b/dts/upstream/Bindings/display/msm/qcom,qcm2290-mdss.yaml
@@ -36,10 +36,14 @@
maxItems: 2
interconnects:
- maxItems: 1
+ items:
+ - description: Interconnect path from mdp0 port to the data bus
+ - description: Interconnect path from CPU to the reg bus
interconnect-names:
- maxItems: 1
+ items:
+ - const: mdp0-mem
+ - const: cpu-cfg
patternProperties:
"^display-controller@[0-9a-f]+$":
@@ -56,7 +60,9 @@
properties:
compatible:
- const: qcom,dsi-ctrl-6g-qcm2290
+ items:
+ - const: qcom,qcm2290-dsi-ctrl
+ - const: qcom,mdss-dsi-ctrl
"^phy@[0-9a-f]+$":
type: object
@@ -96,8 +102,10 @@
interrupt-controller;
#interrupt-cells = <1>;
- interconnects = <&mmrt_virt MASTER_MDP0 &bimc SLAVE_EBI1>;
- interconnect-names = "mdp0-mem";
+ interconnects = <&mmrt_virt MASTER_MDP0 &bimc SLAVE_EBI1>,
+ <&bimc MASTER_APPSS_PROC &config_noc SLAVE_DISPLAY_CFG>;
+ interconnect-names = "mdp0-mem",
+ "cpu-cfg";
iommus = <&apps_smmu 0x420 0x2>,
<&apps_smmu 0x421 0x0>;
@@ -136,7 +144,8 @@
};
dsi@5e94000 {
- compatible = "qcom,dsi-ctrl-6g-qcm2290";
+ compatible = "qcom,qcm2290-dsi-ctrl",
+ "qcom,mdss-dsi-ctrl";
reg = <0x05e94000 0x400>;
reg-names = "dsi_ctrl";
diff --git a/dts/upstream/Bindings/display/msm/qcom,sc7180-mdss.yaml b/dts/upstream/Bindings/display/msm/qcom,sc7180-mdss.yaml
index 3432a24..7a0555b 100644
--- a/dts/upstream/Bindings/display/msm/qcom,sc7180-mdss.yaml
+++ b/dts/upstream/Bindings/display/msm/qcom,sc7180-mdss.yaml
@@ -36,10 +36,14 @@
maxItems: 1
interconnects:
- maxItems: 1
+ items:
+ - description: Interconnect path from mdp0 port to the data bus
+ - description: Interconnect path from CPU to the reg bus
interconnect-names:
- maxItems: 1
+ items:
+ - const: mdp0-mem
+ - const: cpu-cfg
patternProperties:
"^display-controller@[0-9a-f]+$":
@@ -106,8 +110,10 @@
interrupt-controller;
#interrupt-cells = <1>;
- interconnects = <&mmss_noc MASTER_MDP0 &mc_virt SLAVE_EBI1>;
- interconnect-names = "mdp0-mem";
+ interconnects = <&mmss_noc MASTER_MDP0 &mc_virt SLAVE_EBI1>,
+ <&gem_noc MASTER_APPSS_PROC &config_noc SLAVE_DISPLAY_CFG>;
+ interconnect-names = "mdp0-mem",
+ "cpu-cfg";
iommus = <&apps_smmu 0x800 0x2>;
ranges;
diff --git a/dts/upstream/Bindings/display/msm/qcom,sc7280-mdss.yaml b/dts/upstream/Bindings/display/msm/qcom,sc7280-mdss.yaml
index bbb7278..2947f27 100644
--- a/dts/upstream/Bindings/display/msm/qcom,sc7280-mdss.yaml
+++ b/dts/upstream/Bindings/display/msm/qcom,sc7280-mdss.yaml
@@ -36,10 +36,14 @@
maxItems: 1
interconnects:
- maxItems: 1
+ items:
+ - description: Interconnect path from mdp0 port to the data bus
+ - description: Interconnect path from CPU to the reg bus
interconnect-names:
- maxItems: 1
+ items:
+ - const: mdp0-mem
+ - const: cpu-cfg
patternProperties:
"^display-controller@[0-9a-f]+$":
@@ -118,8 +122,10 @@
interrupt-controller;
#interrupt-cells = <1>;
- interconnects = <&mmss_noc MASTER_MDP0 &mc_virt SLAVE_EBI1>;
- interconnect-names = "mdp0-mem";
+ interconnects = <&mmss_noc MASTER_MDP0 &mc_virt SLAVE_EBI1>,
+ <&gem_noc MASTER_APPSS_PROC &cnoc2 SLAVE_DISPLAY_CFG>;
+ interconnect-names = "mdp0-mem",
+ "cpu-cfg";
iommus = <&apps_smmu 0x900 0x402>;
ranges;
diff --git a/dts/upstream/Bindings/display/msm/qcom,sdm670-mdss.yaml b/dts/upstream/Bindings/display/msm/qcom,sdm670-mdss.yaml
new file mode 100644
index 0000000..7dc2693
--- /dev/null
+++ b/dts/upstream/Bindings/display/msm/qcom,sdm670-mdss.yaml
@@ -0,0 +1,292 @@
+# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/display/msm/qcom,sdm670-mdss.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Qualcomm SDM670 Display MDSS
+
+maintainers:
+ - Richard Acayan <mailingradian@gmail.com>
+
+description:
+ SDM670 MSM Mobile Display Subsystem (MDSS), which encapsulates sub-blocks
+ like DPU display controller, DSI and DP interfaces etc.
+
+$ref: /schemas/display/msm/mdss-common.yaml#
+
+properties:
+ compatible:
+ const: qcom,sdm670-mdss
+
+ clocks:
+ items:
+ - description: Display AHB clock from gcc
+ - description: Display core clock
+
+ clock-names:
+ items:
+ - const: iface
+ - const: core
+
+ iommus:
+ maxItems: 2
+
+ interconnects:
+ maxItems: 2
+
+ interconnect-names:
+ maxItems: 2
+
+patternProperties:
+ "^display-controller@[0-9a-f]+$":
+ type: object
+ additionalProperties: true
+
+ properties:
+ compatible:
+ const: qcom,sdm670-dpu
+
+ "^displayport-controller@[0-9a-f]+$":
+ type: object
+ additionalProperties: true
+
+ properties:
+ compatible:
+ const: qcom,sdm670-dp
+
+ "^dsi@[0-9a-f]+$":
+ type: object
+ additionalProperties: true
+
+ properties:
+ compatible:
+ contains:
+ const: qcom,sdm670-dsi-ctrl
+
+ "^phy@[0-9a-f]+$":
+ type: object
+ additionalProperties: true
+
+ properties:
+ compatible:
+ const: qcom,dsi-phy-10nm
+
+required:
+ - compatible
+
+unevaluatedProperties: false
+
+examples:
+ - |
+ #include <dt-bindings/clock/qcom,dispcc-sdm845.h>
+ #include <dt-bindings/clock/qcom,gcc-sdm845.h>
+ #include <dt-bindings/clock/qcom,rpmh.h>
+ #include <dt-bindings/interconnect/qcom,sdm670-rpmh.h>
+ #include <dt-bindings/interrupt-controller/arm-gic.h>
+ #include <dt-bindings/power/qcom-rpmpd.h>
+
+ display-subsystem@ae00000 {
+ compatible = "qcom,sdm670-mdss";
+ reg = <0x0ae00000 0x1000>;
+ reg-names = "mdss";
+ power-domains = <&dispcc MDSS_GDSC>;
+
+ clocks = <&gcc GCC_DISP_AHB_CLK>,
+ <&dispcc DISP_CC_MDSS_MDP_CLK>;
+ clock-names = "iface", "core";
+
+ interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-controller;
+ #interrupt-cells = <1>;
+
+ interconnects = <&mmss_noc MASTER_MDP_PORT0 0 &mem_noc SLAVE_EBI_CH0 0>,
+ <&mmss_noc MASTER_MDP_PORT1 0 &mem_noc SLAVE_EBI_CH0 0>;
+ interconnect-names = "mdp0-mem", "mdp1-mem";
+
+ iommus = <&apps_smmu 0x880 0x8>,
+ <&apps_smmu 0xc80 0x8>;
+
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges;
+
+ display-controller@ae01000 {
+ compatible = "qcom,sdm670-dpu";
+ reg = <0x0ae01000 0x8f000>,
+ <0x0aeb0000 0x2008>;
+ reg-names = "mdp", "vbif";
+
+ clocks = <&gcc GCC_DISP_AXI_CLK>,
+ <&dispcc DISP_CC_MDSS_AHB_CLK>,
+ <&dispcc DISP_CC_MDSS_AXI_CLK>,
+ <&dispcc DISP_CC_MDSS_MDP_CLK>,
+ <&dispcc DISP_CC_MDSS_VSYNC_CLK>;
+ clock-names = "gcc-bus", "iface", "bus", "core", "vsync";
+
+ interrupt-parent = <&mdss>;
+ interrupts = <0>;
+ power-domains = <&rpmhpd SDM670_CX>;
+ operating-points-v2 = <&mdp_opp_table>;
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+ dpu_intf1_out: endpoint {
+ remote-endpoint = <&mdss_dsi0_in>;
+ };
+ };
+
+ port@1 {
+ reg = <1>;
+ dpu_intf2_out: endpoint {
+ remote-endpoint = <&mdss_dsi1_in>;
+ };
+ };
+ };
+ };
+
+ dsi@ae94000 {
+ compatible = "qcom,sdm670-dsi-ctrl", "qcom,mdss-dsi-ctrl";
+ reg = <0x0ae94000 0x400>;
+ reg-names = "dsi_ctrl";
+
+ interrupt-parent = <&mdss>;
+ interrupts = <4>;
+
+ clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK>,
+ <&dispcc DISP_CC_MDSS_BYTE0_INTF_CLK>,
+ <&dispcc DISP_CC_MDSS_PCLK0_CLK>,
+ <&dispcc DISP_CC_MDSS_ESC0_CLK>,
+ <&dispcc DISP_CC_MDSS_AHB_CLK>,
+ <&dispcc DISP_CC_MDSS_AXI_CLK>;
+ clock-names = "byte",
+ "byte_intf",
+ "pixel",
+ "core",
+ "iface",
+ "bus";
+ assigned-clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK_SRC>,
+ <&dispcc DISP_CC_MDSS_PCLK0_CLK_SRC>;
+ assigned-clock-parents = <&mdss_dsi0_phy 0>, <&mdss_dsi0_phy 1>;
+
+ operating-points-v2 = <&dsi_opp_table>;
+ power-domains = <&rpmhpd SDM670_CX>;
+
+ phys = <&mdss_dsi0_phy>;
+ phy-names = "dsi";
+
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+ mdss_dsi0_in: endpoint {
+ remote-endpoint = <&dpu_intf1_out>;
+ };
+ };
+
+ port@1 {
+ reg = <1>;
+ mdss_dsi0_out: endpoint {
+ };
+ };
+ };
+ };
+
+ mdss_dsi0_phy: phy@ae94400 {
+ compatible = "qcom,dsi-phy-10nm";
+ reg = <0x0ae94400 0x200>,
+ <0x0ae94600 0x280>,
+ <0x0ae94a00 0x1e0>;
+ reg-names = "dsi_phy",
+ "dsi_phy_lane",
+ "dsi_pll";
+
+ #clock-cells = <1>;
+ #phy-cells = <0>;
+
+ clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>,
+ <&rpmhcc RPMH_CXO_CLK>;
+ clock-names = "iface", "ref";
+ vdds-supply = <&vreg_dsi_phy>;
+ };
+
+ dsi@ae96000 {
+ compatible = "qcom,sdm670-dsi-ctrl", "qcom,mdss-dsi-ctrl";
+ reg = <0x0ae96000 0x400>;
+ reg-names = "dsi_ctrl";
+
+ interrupt-parent = <&mdss>;
+ interrupts = <5>;
+
+ clocks = <&dispcc DISP_CC_MDSS_BYTE1_CLK>,
+ <&dispcc DISP_CC_MDSS_BYTE1_INTF_CLK>,
+ <&dispcc DISP_CC_MDSS_PCLK1_CLK>,
+ <&dispcc DISP_CC_MDSS_ESC1_CLK>,
+ <&dispcc DISP_CC_MDSS_AHB_CLK>,
+ <&dispcc DISP_CC_MDSS_AXI_CLK>;
+ clock-names = "byte",
+ "byte_intf",
+ "pixel",
+ "core",
+ "iface",
+ "bus";
+ assigned-clocks = <&dispcc DISP_CC_MDSS_BYTE1_CLK_SRC>,
+ <&dispcc DISP_CC_MDSS_PCLK1_CLK_SRC>;
+ assigned-clock-parents = <&dsi1_phy 0>, <&dsi1_phy 1>;
+
+ operating-points-v2 = <&dsi_opp_table>;
+ power-domains = <&rpmhpd SDM670_CX>;
+
+ phys = <&dsi1_phy>;
+ phy-names = "dsi";
+
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+ mdss_dsi1_in: endpoint {
+ remote-endpoint = <&dpu_intf2_out>;
+ };
+ };
+
+ port@1 {
+ reg = <1>;
+ mdss_dsi1_out: endpoint {
+ };
+ };
+ };
+ };
+
+ mdss_dsi1_phy: phy@ae96400 {
+ compatible = "qcom,dsi-phy-10nm";
+ reg = <0x0ae96400 0x200>,
+ <0x0ae96600 0x280>,
+ <0x0ae96a00 0x10e>;
+ reg-names = "dsi_phy",
+ "dsi_phy_lane",
+ "dsi_pll";
+
+ #clock-cells = <1>;
+ #phy-cells = <0>;
+
+ clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>,
+ <&rpmhcc RPMH_CXO_CLK>;
+ clock-names = "iface", "ref";
+ vdds-supply = <&vreg_dsi_phy>;
+ };
+ };
+...
diff --git a/dts/upstream/Bindings/display/msm/qcom,sdm845-dpu.yaml b/dts/upstream/Bindings/display/msm/qcom,sdm845-dpu.yaml
index b917064..dc11fd4 100644
--- a/dts/upstream/Bindings/display/msm/qcom,sdm845-dpu.yaml
+++ b/dts/upstream/Bindings/display/msm/qcom,sdm845-dpu.yaml
@@ -13,7 +13,9 @@
properties:
compatible:
- const: qcom,sdm845-dpu
+ enum:
+ - qcom,sdm670-dpu
+ - qcom,sdm845-dpu
reg:
items:
diff --git a/dts/upstream/Bindings/display/msm/qcom,sm6115-mdss.yaml b/dts/upstream/Bindings/display/msm/qcom,sm6115-mdss.yaml
index dde5c2a..309de19 100644
--- a/dts/upstream/Bindings/display/msm/qcom,sm6115-mdss.yaml
+++ b/dts/upstream/Bindings/display/msm/qcom,sm6115-mdss.yaml
@@ -29,6 +29,16 @@
iommus:
maxItems: 2
+ interconnects:
+ items:
+ - description: Interconnect path from mdp0 port to the data bus
+ - description: Interconnect path from CPU to the reg bus
+
+ interconnect-names:
+ items:
+ - const: mdp0-mem
+ - const: cpu-cfg
+
patternProperties:
"^display-controller@[0-9a-f]+$":
type: object
diff --git a/dts/upstream/Bindings/display/msm/qcom,sm6125-mdss.yaml b/dts/upstream/Bindings/display/msm/qcom,sm6125-mdss.yaml
index 671c2c2..3deb9dc 100644
--- a/dts/upstream/Bindings/display/msm/qcom,sm6125-mdss.yaml
+++ b/dts/upstream/Bindings/display/msm/qcom,sm6125-mdss.yaml
@@ -35,10 +35,14 @@
maxItems: 1
interconnects:
- maxItems: 2
+ items:
+ - description: Interconnect path from mdp0 port to the data bus
+ - description: Interconnect path from CPU to the reg bus
interconnect-names:
- maxItems: 2
+ items:
+ - const: mdp0-mem
+ - const: cpu-cfg
patternProperties:
"^display-controller@[0-9a-f]+$":
diff --git a/dts/upstream/Bindings/display/msm/qcom,sm6350-mdss.yaml b/dts/upstream/Bindings/display/msm/qcom,sm6350-mdss.yaml
index e1dcb45..c9ba1fa 100644
--- a/dts/upstream/Bindings/display/msm/qcom,sm6350-mdss.yaml
+++ b/dts/upstream/Bindings/display/msm/qcom,sm6350-mdss.yaml
@@ -35,10 +35,14 @@
maxItems: 1
interconnects:
- maxItems: 2
+ items:
+ - description: Interconnect path from mdp0 port to the data bus
+ - description: Interconnect path from CPU to the reg bus
interconnect-names:
- maxItems: 2
+ items:
+ - const: mdp0-mem
+ - const: cpu-cfg
patternProperties:
"^display-controller@[0-9a-f]+$":
diff --git a/dts/upstream/Bindings/display/msm/qcom,sm6375-mdss.yaml b/dts/upstream/Bindings/display/msm/qcom,sm6375-mdss.yaml
index b15c395..8e8a288 100644
--- a/dts/upstream/Bindings/display/msm/qcom,sm6375-mdss.yaml
+++ b/dts/upstream/Bindings/display/msm/qcom,sm6375-mdss.yaml
@@ -35,10 +35,14 @@
maxItems: 1
interconnects:
- maxItems: 2
+ items:
+ - description: Interconnect path from mdp0 port to the data bus
+ - description: Interconnect path from CPU to the reg bus
interconnect-names:
- maxItems: 2
+ items:
+ - const: mdp0-mem
+ - const: cpu-cfg
patternProperties:
"^display-controller@[0-9a-f]+$":
diff --git a/dts/upstream/Bindings/display/msm/qcom,sm8150-mdss.yaml b/dts/upstream/Bindings/display/msm/qcom,sm8150-mdss.yaml
index a2a8be7..c0d6a4f 100644
--- a/dts/upstream/Bindings/display/msm/qcom,sm8150-mdss.yaml
+++ b/dts/upstream/Bindings/display/msm/qcom,sm8150-mdss.yaml
@@ -69,7 +69,7 @@
properties:
compatible:
- const: qcom,dsi-phy-7nm
+ const: qcom,dsi-phy-7nm-8150
unevaluatedProperties: false
@@ -247,7 +247,7 @@
};
dsi0_phy: phy@ae94400 {
- compatible = "qcom,dsi-phy-7nm";
+ compatible = "qcom,dsi-phy-7nm-8150";
reg = <0x0ae94400 0x200>,
<0x0ae94600 0x280>,
<0x0ae94900 0x260>;
@@ -318,7 +318,7 @@
};
dsi1_phy: phy@ae96400 {
- compatible = "qcom,dsi-phy-7nm";
+ compatible = "qcom,dsi-phy-7nm-8150";
reg = <0x0ae96400 0x200>,
<0x0ae96600 0x280>,
<0x0ae96900 0x260>;
diff --git a/dts/upstream/Bindings/display/msm/qcom,sm8250-mdss.yaml b/dts/upstream/Bindings/display/msm/qcom,sm8250-mdss.yaml
index 9949759..51368cd 100644
--- a/dts/upstream/Bindings/display/msm/qcom,sm8250-mdss.yaml
+++ b/dts/upstream/Bindings/display/msm/qcom,sm8250-mdss.yaml
@@ -52,6 +52,16 @@
compatible:
const: qcom,sm8250-dpu
+ "^displayport-controller@[0-9a-f]+$":
+ type: object
+ additionalProperties: true
+
+ properties:
+ compatible:
+ items:
+ - const: qcom,sm8250-dp
+ - const: qcom,sm8350-dp
+
"^dsi@[0-9a-f]+$":
type: object
additionalProperties: true
diff --git a/dts/upstream/Bindings/display/msm/qcom,sm8450-mdss.yaml b/dts/upstream/Bindings/display/msm/qcom,sm8450-mdss.yaml
index 001b26e..747a2e9 100644
--- a/dts/upstream/Bindings/display/msm/qcom,sm8450-mdss.yaml
+++ b/dts/upstream/Bindings/display/msm/qcom,sm8450-mdss.yaml
@@ -30,10 +30,10 @@
maxItems: 1
interconnects:
- maxItems: 2
+ maxItems: 3
interconnect-names:
- maxItems: 2
+ maxItems: 3
patternProperties:
"^display-controller@[0-9a-f]+$":
@@ -91,9 +91,12 @@
reg = <0x0ae00000 0x1000>;
reg-names = "mdss";
- interconnects = <&mmss_noc MASTER_MDP_DISP 0 &mc_virt SLAVE_EBI1_DISP 0>,
- <&mmss_noc MASTER_MDP_DISP 0 &mc_virt SLAVE_EBI1_DISP 0>;
- interconnect-names = "mdp0-mem", "mdp1-mem";
+ interconnects = <&mmss_noc MASTER_MDP_DISP &mc_virt SLAVE_EBI1_DISP>,
+ <&mmss_noc MASTER_MDP_DISP &mc_virt SLAVE_EBI1_DISP>,
+ <&gem_noc MASTER_APPSS_PROC &config_noc SLAVE_DISPLAY_CFG>;
+ interconnect-names = "mdp0-mem",
+ "mdp1-mem",
+ "cpu-cfg";
resets = <&dispcc DISP_CC_MDSS_CORE_BCR>;
diff --git a/dts/upstream/Bindings/display/msm/qcom,sm8650-dpu.yaml b/dts/upstream/Bindings/display/msm/qcom,sm8650-dpu.yaml
new file mode 100644
index 0000000..a01d15a
--- /dev/null
+++ b/dts/upstream/Bindings/display/msm/qcom,sm8650-dpu.yaml
@@ -0,0 +1,127 @@
+# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/display/msm/qcom,sm8650-dpu.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Qualcomm SM8650 Display DPU
+
+maintainers:
+ - Neil Armstrong <neil.armstrong@linaro.org>
+
+$ref: /schemas/display/msm/dpu-common.yaml#
+
+properties:
+ compatible:
+ const: qcom,sm8650-dpu
+
+ reg:
+ items:
+ - description: Address offset and size for mdp register set
+ - description: Address offset and size for vbif register set
+
+ reg-names:
+ items:
+ - const: mdp
+ - const: vbif
+
+ clocks:
+ items:
+ - description: Display hf axi
+ - description: Display MDSS ahb
+ - description: Display lut
+ - description: Display core
+ - description: Display vsync
+
+ clock-names:
+ items:
+ - const: nrt_bus
+ - const: iface
+ - const: lut
+ - const: core
+ - const: vsync
+
+required:
+ - compatible
+ - reg
+ - reg-names
+ - clocks
+ - clock-names
+
+unevaluatedProperties: false
+
+examples:
+ - |
+ #include <dt-bindings/interrupt-controller/arm-gic.h>
+ #include <dt-bindings/power/qcom,rpmhpd.h>
+
+ display-controller@ae01000 {
+ compatible = "qcom,sm8650-dpu";
+ reg = <0x0ae01000 0x8f000>,
+ <0x0aeb0000 0x2008>;
+ reg-names = "mdp", "vbif";
+
+ clocks = <&gcc_axi_clk>,
+ <&dispcc_ahb_clk>,
+ <&dispcc_mdp_lut_clk>,
+ <&dispcc_mdp_clk>,
+ <&dispcc_vsync_clk>;
+ clock-names = "nrt_bus",
+ "iface",
+ "lut",
+ "core",
+ "vsync";
+
+ assigned-clocks = <&dispcc_vsync_clk>;
+ assigned-clock-rates = <19200000>;
+
+ operating-points-v2 = <&mdp_opp_table>;
+ power-domains = <&rpmhpd RPMHPD_MMCX>;
+
+ interrupt-parent = <&mdss>;
+ interrupts = <0>;
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+ dpu_intf1_out: endpoint {
+ remote-endpoint = <&dsi0_in>;
+ };
+ };
+
+ port@1 {
+ reg = <1>;
+ dpu_intf2_out: endpoint {
+ remote-endpoint = <&dsi1_in>;
+ };
+ };
+ };
+
+ mdp_opp_table: opp-table {
+ compatible = "operating-points-v2";
+
+ opp-200000000 {
+ opp-hz = /bits/ 64 <200000000>;
+ required-opps = <&rpmhpd_opp_low_svs>;
+ };
+
+ opp-325000000 {
+ opp-hz = /bits/ 64 <325000000>;
+ required-opps = <&rpmhpd_opp_svs>;
+ };
+
+ opp-375000000 {
+ opp-hz = /bits/ 64 <375000000>;
+ required-opps = <&rpmhpd_opp_svs_l1>;
+ };
+
+ opp-514000000 {
+ opp-hz = /bits/ 64 <514000000>;
+ required-opps = <&rpmhpd_opp_nom>;
+ };
+ };
+ };
+...
diff --git a/dts/upstream/Bindings/display/msm/qcom,sm8650-mdss.yaml b/dts/upstream/Bindings/display/msm/qcom,sm8650-mdss.yaml
new file mode 100644
index 0000000..bd11119
--- /dev/null
+++ b/dts/upstream/Bindings/display/msm/qcom,sm8650-mdss.yaml
@@ -0,0 +1,328 @@
+# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/display/msm/qcom,sm8650-mdss.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Qualcomm SM8650 Display MDSS
+
+maintainers:
+ - Neil Armstrong <neil.armstrong@linaro.org>
+
+description:
+ SM8650 MSM Mobile Display Subsystem(MDSS), which encapsulates sub-blocks like
+ DPU display controller, DSI and DP interfaces etc.
+
+$ref: /schemas/display/msm/mdss-common.yaml#
+
+properties:
+ compatible:
+ const: qcom,sm8650-mdss
+
+ clocks:
+ items:
+ - description: Display AHB
+ - description: Display hf AXI
+ - description: Display core
+
+ iommus:
+ maxItems: 1
+
+ interconnects:
+ maxItems: 2
+
+ interconnect-names:
+ maxItems: 2
+
+patternProperties:
+ "^display-controller@[0-9a-f]+$":
+ type: object
+ properties:
+ compatible:
+ const: qcom,sm8650-dpu
+
+ "^displayport-controller@[0-9a-f]+$":
+ type: object
+ properties:
+ compatible:
+ const: qcom,sm8650-dp
+
+ "^dsi@[0-9a-f]+$":
+ type: object
+ properties:
+ compatible:
+ items:
+ - const: qcom,sm8650-dsi-ctrl
+ - const: qcom,mdss-dsi-ctrl
+
+ "^phy@[0-9a-f]+$":
+ type: object
+ properties:
+ compatible:
+ const: qcom,sm8650-dsi-phy-4nm
+
+required:
+ - compatible
+
+unevaluatedProperties: false
+
+examples:
+ - |
+ #include <dt-bindings/clock/qcom,rpmh.h>
+ #include <dt-bindings/interrupt-controller/arm-gic.h>
+ #include <dt-bindings/power/qcom,rpmhpd.h>
+
+ display-subsystem@ae00000 {
+ compatible = "qcom,sm8650-mdss";
+ reg = <0x0ae00000 0x1000>;
+ reg-names = "mdss";
+
+ resets = <&dispcc_core_bcr>;
+
+ power-domains = <&dispcc_gdsc>;
+
+ clocks = <&gcc_ahb_clk>,
+ <&gcc_axi_clk>,
+ <&dispcc_mdp_clk>;
+ clock-names = "bus", "nrt_bus", "core";
+
+ interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-controller;
+ #interrupt-cells = <1>;
+
+ iommus = <&apps_smmu 0x1c00 0x2>;
+
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges;
+
+ display-controller@ae01000 {
+ compatible = "qcom,sm8650-dpu";
+ reg = <0x0ae01000 0x8f000>,
+ <0x0aeb0000 0x2008>;
+ reg-names = "mdp", "vbif";
+
+ clocks = <&gcc_axi_clk>,
+ <&dispcc_ahb_clk>,
+ <&dispcc_mdp_lut_clk>,
+ <&dispcc_mdp_clk>,
+ <&dispcc_mdp_vsync_clk>;
+ clock-names = "nrt_bus",
+ "iface",
+ "lut",
+ "core",
+ "vsync";
+
+ assigned-clocks = <&dispcc_mdp_vsync_clk>;
+ assigned-clock-rates = <19200000>;
+
+ operating-points-v2 = <&mdp_opp_table>;
+ power-domains = <&rpmhpd RPMHPD_MMCX>;
+
+ interrupt-parent = <&mdss>;
+ interrupts = <0>;
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+ dpu_intf1_out: endpoint {
+ remote-endpoint = <&dsi0_in>;
+ };
+ };
+
+ port@1 {
+ reg = <1>;
+ dpu_intf2_out: endpoint {
+ remote-endpoint = <&dsi1_in>;
+ };
+ };
+ };
+
+ mdp_opp_table: opp-table {
+ compatible = "operating-points-v2";
+
+ opp-200000000 {
+ opp-hz = /bits/ 64 <200000000>;
+ required-opps = <&rpmhpd_opp_low_svs>;
+ };
+
+ opp-325000000 {
+ opp-hz = /bits/ 64 <325000000>;
+ required-opps = <&rpmhpd_opp_svs>;
+ };
+
+ opp-375000000 {
+ opp-hz = /bits/ 64 <375000000>;
+ required-opps = <&rpmhpd_opp_svs_l1>;
+ };
+
+ opp-514000000 {
+ opp-hz = /bits/ 64 <514000000>;
+ required-opps = <&rpmhpd_opp_nom>;
+ };
+ };
+ };
+
+ dsi@ae94000 {
+ compatible = "qcom,sm8650-dsi-ctrl", "qcom,mdss-dsi-ctrl";
+ reg = <0x0ae94000 0x400>;
+ reg-names = "dsi_ctrl";
+
+ interrupt-parent = <&mdss>;
+ interrupts = <4>;
+
+ clocks = <&dispc_byte_clk>,
+ <&dispcc_intf_clk>,
+ <&dispcc_pclk>,
+ <&dispcc_esc_clk>,
+ <&dispcc_ahb_clk>,
+ <&gcc_bus_clk>;
+ clock-names = "byte",
+ "byte_intf",
+ "pixel",
+ "core",
+ "iface",
+ "bus";
+
+ assigned-clocks = <&dispcc_byte_clk>,
+ <&dispcc_pclk>;
+ assigned-clock-parents = <&dsi0_phy 0>, <&dsi0_phy 1>;
+
+ operating-points-v2 = <&dsi_opp_table>;
+ power-domains = <&rpmhpd RPMHPD_MMCX>;
+
+ phys = <&dsi0_phy>;
+ phy-names = "dsi";
+
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+ dsi0_in: endpoint {
+ remote-endpoint = <&dpu_intf1_out>;
+ };
+ };
+
+ port@1 {
+ reg = <1>;
+ dsi0_out: endpoint {
+ };
+ };
+ };
+
+ dsi_opp_table: opp-table {
+ compatible = "operating-points-v2";
+
+ opp-187500000 {
+ opp-hz = /bits/ 64 <187500000>;
+ required-opps = <&rpmhpd_opp_low_svs>;
+ };
+
+ opp-300000000 {
+ opp-hz = /bits/ 64 <300000000>;
+ required-opps = <&rpmhpd_opp_svs>;
+ };
+
+ opp-358000000 {
+ opp-hz = /bits/ 64 <358000000>;
+ required-opps = <&rpmhpd_opp_svs_l1>;
+ };
+ };
+ };
+
+ dsi0_phy: phy@ae94400 {
+ compatible = "qcom,sm8650-dsi-phy-4nm";
+ reg = <0x0ae95000 0x200>,
+ <0x0ae95200 0x280>,
+ <0x0ae95500 0x400>;
+ reg-names = "dsi_phy",
+ "dsi_phy_lane",
+ "dsi_pll";
+
+ #clock-cells = <1>;
+ #phy-cells = <0>;
+
+ clocks = <&dispcc_iface_clk>,
+ <&rpmhcc_ref_clk>;
+ clock-names = "iface", "ref";
+ };
+
+ dsi@ae96000 {
+ compatible = "qcom,sm8650-dsi-ctrl", "qcom,mdss-dsi-ctrl";
+ reg = <0x0ae96000 0x400>;
+ reg-names = "dsi_ctrl";
+
+ interrupt-parent = <&mdss>;
+ interrupts = <5>;
+
+ clocks = <&dispc_byte_clk>,
+ <&dispcc_intf_clk>,
+ <&dispcc_pclk>,
+ <&dispcc_esc_clk>,
+ <&dispcc_ahb_clk>,
+ <&gcc_bus_clk>;
+ clock-names = "byte",
+ "byte_intf",
+ "pixel",
+ "core",
+ "iface",
+ "bus";
+
+ assigned-clocks = <&dispcc_byte_clk>,
+ <&dispcc_pclk>;
+ assigned-clock-parents = <&dsi1_phy 0>, <&dsi1_phy 1>;
+
+ operating-points-v2 = <&dsi_opp_table>;
+ power-domains = <&rpmhpd RPMHPD_MMCX>;
+
+ phys = <&dsi1_phy>;
+ phy-names = "dsi";
+
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+ dsi1_in: endpoint {
+ remote-endpoint = <&dpu_intf2_out>;
+ };
+ };
+
+ port@1 {
+ reg = <1>;
+ dsi1_out: endpoint {
+ };
+ };
+ };
+ };
+
+ dsi1_phy: phy@ae96400 {
+ compatible = "qcom,sm8650-dsi-phy-4nm";
+ reg = <0x0ae97000 0x200>,
+ <0x0ae97200 0x280>,
+ <0x0ae97500 0x400>;
+ reg-names = "dsi_phy",
+ "dsi_phy_lane",
+ "dsi_pll";
+
+ #clock-cells = <1>;
+ #phy-cells = <0>;
+
+ clocks = <&dispcc_iface_clk>,
+ <&rpmhcc_ref_clk>;
+ clock-names = "iface", "ref";
+ };
+ };
+...
diff --git a/dts/upstream/Bindings/display/panel/fascontek,fs035vg158.yaml b/dts/upstream/Bindings/display/panel/fascontek,fs035vg158.yaml
new file mode 100644
index 0000000..d13c4bd
--- /dev/null
+++ b/dts/upstream/Bindings/display/panel/fascontek,fs035vg158.yaml
@@ -0,0 +1,56 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/display/panel/fascontek,fs035vg158.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Fascontek FS035VG158 3.5" (640x480 pixels) 24-bit IPS LCD panel
+
+maintainers:
+ - John Watts <contact@jookia.org>
+
+allOf:
+ - $ref: panel-common.yaml#
+ - $ref: /schemas/spi/spi-peripheral-props.yaml#
+
+properties:
+ compatible:
+ const: fascontek,fs035vg158
+
+ spi-3wire: true
+
+required:
+ - compatible
+ - reg
+ - port
+ - power-supply
+ - reset-gpios
+
+unevaluatedProperties: false
+
+examples:
+ - |
+ #include <dt-bindings/gpio/gpio.h>
+
+ spi {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ panel@0 {
+ compatible = "fascontek,fs035vg158";
+ reg = <0>;
+
+ spi-3wire;
+ spi-max-frequency = <3125000>;
+
+ reset-gpios = <&gpe 2 GPIO_ACTIVE_LOW>;
+
+ backlight = <&backlight>;
+ power-supply = <&vcc>;
+
+ port {
+ panel_input: endpoint {
+ remote-endpoint = <&panel_output>;
+ };
+ };
+ };
+ };
diff --git a/dts/upstream/Bindings/display/panel/himax,hx8394.yaml b/dts/upstream/Bindings/display/panel/himax,hx8394.yaml
index ffb3528..916bb7f 100644
--- a/dts/upstream/Bindings/display/panel/himax,hx8394.yaml
+++ b/dts/upstream/Bindings/display/panel/himax,hx8394.yaml
@@ -23,6 +23,7 @@
items:
- enum:
- hannstar,hsd060bhw4
+ - powkiddy,x55-panel
- const: himax,hx8394
reg: true
@@ -31,6 +32,8 @@
backlight: true
+ rotation: true
+
port: true
vcc-supply:
diff --git a/dts/upstream/Bindings/display/panel/ilitek,ili9805.yaml b/dts/upstream/Bindings/display/panel/ilitek,ili9805.yaml
new file mode 100644
index 0000000..f4f91f9
--- /dev/null
+++ b/dts/upstream/Bindings/display/panel/ilitek,ili9805.yaml
@@ -0,0 +1,62 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/display/panel/ilitek,ili9805.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Ilitek ILI9805 based MIPI-DSI panels
+
+maintainers:
+ - Michael Trimarchi <michael@amarulasolutions.com>
+
+allOf:
+ - $ref: panel-common.yaml#
+
+properties:
+ compatible:
+ items:
+ - enum:
+ - giantplus,gpm1790a0
+ - tianma,tm041xdhg01
+ - const: ilitek,ili9805
+
+ avdd-supply: true
+ dvdd-supply: true
+ reg: true
+
+required:
+ - compatible
+ - avdd-supply
+ - dvdd-supply
+ - reg
+ - reset-gpios
+ - port
+ - backlight
+
+unevaluatedProperties: false
+
+examples:
+ - |
+ #include <dt-bindings/gpio/gpio.h>
+
+ dsi {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ panel@0 {
+ compatible = "giantplus,gpm1790a0", "ilitek,ili9805";
+ reg = <0>;
+ avdd-supply = <&avdd_display>;
+ dvdd-supply = <&dvdd_display>;
+ reset-gpios = <&r_pio 0 5 GPIO_ACTIVE_LOW>; /* PL05 */
+ backlight = <&backlight>;
+
+ port {
+ panel_in: endpoint {
+ remote-endpoint = <&mipi_dsi_out>;
+ };
+ };
+ };
+ };
+
+...
diff --git a/dts/upstream/Bindings/display/panel/ilitek,ili9881c.yaml b/dts/upstream/Bindings/display/panel/ilitek,ili9881c.yaml
index e7ab622..b1e624b 100644
--- a/dts/upstream/Bindings/display/panel/ilitek,ili9881c.yaml
+++ b/dts/upstream/Bindings/display/panel/ilitek,ili9881c.yaml
@@ -16,6 +16,7 @@
compatible:
items:
- enum:
+ - ampire,am8001280g
- bananapi,lhr050h41
- feixin,k101-im2byl02
- tdo,tl050hdv35
diff --git a/dts/upstream/Bindings/display/panel/leadtek,ltk035c5444t.yaml b/dts/upstream/Bindings/display/panel/leadtek,ltk035c5444t.yaml
index ebdca5f..7a55961 100644
--- a/dts/upstream/Bindings/display/panel/leadtek,ltk035c5444t.yaml
+++ b/dts/upstream/Bindings/display/panel/leadtek,ltk035c5444t.yaml
@@ -18,16 +18,12 @@
compatible:
const: leadtek,ltk035c5444t
- backlight: true
- port: true
- power-supply: true
- reg: true
- reset-gpios: true
-
spi-3wire: true
required:
- compatible
+ - reg
+ - port
- power-supply
- reset-gpios
diff --git a/dts/upstream/Bindings/display/panel/newvision,nv3051d.yaml b/dts/upstream/Bindings/display/panel/newvision,nv3051d.yaml
index cce775a..7a634fb 100644
--- a/dts/upstream/Bindings/display/panel/newvision,nv3051d.yaml
+++ b/dts/upstream/Bindings/display/panel/newvision,nv3051d.yaml
@@ -21,7 +21,7 @@
- enum:
- anbernic,rg351v-panel
- anbernic,rg353p-panel
- - anbernic,rg353v-panel
+ - powkiddy,rk2023-panel
- const: newvision,nv3051d
reg: true
diff --git a/dts/upstream/Bindings/display/panel/panel-simple-lvds-dual-ports.yaml b/dts/upstream/Bindings/display/panel/panel-simple-lvds-dual-ports.yaml
index a5a596f..716ece5 100644
--- a/dts/upstream/Bindings/display/panel/panel-simple-lvds-dual-ports.yaml
+++ b/dts/upstream/Bindings/display/panel/panel-simple-lvds-dual-ports.yaml
@@ -33,6 +33,8 @@
# AU Optronics Corporation 13.3" FHD (1920x1080) TFT LCD panel
- auo,g133han01
+ # AU Optronics Corporation 15.6" FHD (1920x1080) TFT LCD panel
+ - auo,g156han04
# AU Optronics Corporation 18.5" FHD (1920x1080) TFT LCD panel
- auo,g185han01
# AU Optronics Corporation 19.0" (1280x1024) TFT LCD panel
diff --git a/dts/upstream/Bindings/display/panel/panel-simple.yaml b/dts/upstream/Bindings/display/panel/panel-simple.yaml
index 11422af..634a10c 100644
--- a/dts/upstream/Bindings/display/panel/panel-simple.yaml
+++ b/dts/upstream/Bindings/display/panel/panel-simple.yaml
@@ -73,6 +73,8 @@
- auo,t215hvn01
# Shanghai AVIC Optoelectronics 7" 1024x600 color TFT-LCD panel
- avic,tm070ddh03
+ # BOE BP101WX1-100 10.1" WXGA (1280x800) LVDS panel
+ - boe,bp101wx1-100
# BOE EV121WXM-N10-1850 12.1" WXGA (1280x800) TFT LCD panel
- boe,ev121wxm-n10-1850
# BOE HV070WSA-100 7.01" WSVGA TFT LCD panel
@@ -144,6 +146,8 @@
- edt,etmv570g2dhu
# E Ink VB3300-KCA
- eink,vb3300-kca
+ # Evervision Electronics Co. Ltd. VGG644804 5.7" VGA TFT LCD Panel
+ - evervision,vgg644804
# Evervision Electronics Co. Ltd. VGG804821 5.0" WVGA TFT LCD Panel
- evervision,vgg804821
# Foxlink Group 5" WVGA TFT LCD panel
diff --git a/dts/upstream/Bindings/display/panel/sitronix,st7701.yaml b/dts/upstream/Bindings/display/panel/sitronix,st7701.yaml
index 4dc0cd4..b348f5b 100644
--- a/dts/upstream/Bindings/display/panel/sitronix,st7701.yaml
+++ b/dts/upstream/Bindings/display/panel/sitronix,st7701.yaml
@@ -27,6 +27,7 @@
compatible:
items:
- enum:
+ - anbernic,rg-arc-panel
- densitron,dmt028vghmcmi-1a
- elida,kd50t048a
- techstar,ts8550b
diff --git a/dts/upstream/Bindings/display/panel/synaptics,r63353.yaml b/dts/upstream/Bindings/display/panel/synaptics,r63353.yaml
new file mode 100644
index 0000000..e5617d1
--- /dev/null
+++ b/dts/upstream/Bindings/display/panel/synaptics,r63353.yaml
@@ -0,0 +1,61 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/display/panel/synaptics,r63353.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Synaptics R63353 based MIPI-DSI panels
+
+maintainers:
+ - Michael Trimarchi <michael@amarulasolutions.com>
+
+allOf:
+ - $ref: panel-common.yaml#
+
+properties:
+ compatible:
+ items:
+ - enum:
+ - sharp,ls068b3sx02
+ - const: syna,r63353
+
+ avdd-supply: true
+ dvdd-supply: true
+ reg: true
+
+required:
+ - compatible
+ - avdd-supply
+ - dvdd-supply
+ - reg
+ - reset-gpios
+ - port
+ - backlight
+
+unevaluatedProperties: false
+
+examples:
+ - |
+ #include <dt-bindings/gpio/gpio.h>
+
+ dsi {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ panel@0 {
+ compatible = "sharp,ls068b3sx02", "syna,r63353";
+ reg = <0>;
+ avdd-supply = <&avdd_display>;
+ dvdd-supply = <&dvdd_display>;
+ reset-gpios = <&r_pio 0 5 GPIO_ACTIVE_LOW>; /* PL05 */
+ backlight = <&backlight>;
+
+ port {
+ panel_in: endpoint {
+ remote-endpoint = <&mipi_dsi_out>;
+ };
+ };
+ };
+ };
+
+...
diff --git a/dts/upstream/Bindings/display/rockchip/inno_hdmi-rockchip.txt b/dts/upstream/Bindings/display/rockchip/inno_hdmi-rockchip.txt
deleted file mode 100644
index cec2171..0000000
--- a/dts/upstream/Bindings/display/rockchip/inno_hdmi-rockchip.txt
+++ /dev/null
@@ -1,49 +0,0 @@
-Rockchip specific extensions to the Innosilicon HDMI
-================================
-
-Required properties:
-- compatible:
- "rockchip,rk3036-inno-hdmi";
-- reg:
- Physical base address and length of the controller's registers.
-- clocks, clock-names:
- Phandle to hdmi controller clock, name should be "pclk"
-- interrupts:
- HDMI interrupt number
-- ports:
- Contain one port node with endpoint definitions as defined in
- Documentation/devicetree/bindings/graph.txt.
-- pinctrl-0, pinctrl-name:
- Switch the iomux of HPD/CEC pins to HDMI function.
-
-Example:
-hdmi: hdmi@20034000 {
- compatible = "rockchip,rk3036-inno-hdmi";
- reg = <0x20034000 0x4000>;
- interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cru PCLK_HDMI>;
- clock-names = "pclk";
- pinctrl-names = "default";
- pinctrl-0 = <&hdmi_ctl>;
-
- hdmi_in: port {
- #address-cells = <1>;
- #size-cells = <0>;
- hdmi_in_lcdc: endpoint@0 {
- reg = <0>;
- remote-endpoint = <&lcdc_out_hdmi>;
- };
- };
-};
-
-&pinctrl {
- hdmi {
- hdmi_ctl: hdmi-ctl {
- rockchip,pins = <1 8 RK_FUNC_1 &pcfg_pull_none>,
- <1 9 RK_FUNC_1 &pcfg_pull_none>,
- <1 10 RK_FUNC_1 &pcfg_pull_none>,
- <1 11 RK_FUNC_1 &pcfg_pull_none>;
- };
- };
-
-};
diff --git a/dts/upstream/Bindings/display/rockchip/rockchip,inno-hdmi.yaml b/dts/upstream/Bindings/display/rockchip/rockchip,inno-hdmi.yaml
new file mode 100644
index 0000000..be78dcf
--- /dev/null
+++ b/dts/upstream/Bindings/display/rockchip/rockchip,inno-hdmi.yaml
@@ -0,0 +1,139 @@
+# SPDX-License-Identifier: GPL-2.0
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/display/rockchip/rockchip,inno-hdmi.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Rockchip Innosilicon HDMI controller
+
+maintainers:
+ - Sandy Huang <hjc@rock-chips.com>
+ - Heiko Stuebner <heiko@sntech.de>
+
+properties:
+ compatible:
+ enum:
+ - rockchip,rk3036-inno-hdmi
+ - rockchip,rk3128-inno-hdmi
+
+ reg:
+ maxItems: 1
+
+ interrupts:
+ maxItems: 1
+
+ clocks:
+ minItems: 1
+ items:
+ - description: The HDMI controller main clock
+ - description: The HDMI PHY reference clock
+
+ clock-names:
+ minItems: 1
+ items:
+ - const: pclk
+ - const: ref
+
+ power-domains:
+ maxItems: 1
+
+ ports:
+ $ref: /schemas/graph.yaml#/properties/ports
+
+ properties:
+ port@0:
+ $ref: /schemas/graph.yaml#/properties/port
+ description:
+ Port node with one endpoint connected to a vop node.
+
+ port@1:
+ $ref: /schemas/graph.yaml#/properties/port
+ description:
+ Port node with one endpoint connected to a hdmi-connector node.
+
+ required:
+ - port@0
+ - port@1
+
+required:
+ - compatible
+ - reg
+ - interrupts
+ - clocks
+ - clock-names
+ - pinctrl-0
+ - pinctrl-names
+ - ports
+
+allOf:
+ - if:
+ properties:
+ compatible:
+ contains:
+ const: rockchip,rk3036-inno-hdmi
+
+ then:
+ properties:
+ power-domains: false
+
+ - if:
+ properties:
+ compatible:
+ contains:
+ const: rockchip,rk3128-inno-hdmi
+
+ then:
+ properties:
+ clocks:
+ minItems: 2
+ clock-names:
+ minItems: 2
+ required:
+ - power-domains
+
+additionalProperties: false
+
+examples:
+ - |
+ #include <dt-bindings/clock/rk3036-cru.h>
+ #include <dt-bindings/interrupt-controller/arm-gic.h>
+ #include <dt-bindings/pinctrl/rockchip.h>
+ hdmi: hdmi@20034000 {
+ compatible = "rockchip,rk3036-inno-hdmi";
+ reg = <0x20034000 0x4000>;
+ interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cru PCLK_HDMI>;
+ clock-names = "pclk";
+ pinctrl-names = "default";
+ pinctrl-0 = <&hdmi_ctl>;
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ hdmi_in: port@0 {
+ reg = <0>;
+ hdmi_in_vop: endpoint {
+ remote-endpoint = <&vop_out_hdmi>;
+ };
+ };
+
+ hdmi_out: port@1 {
+ reg = <1>;
+ hdmi_out_con: endpoint {
+ remote-endpoint = <&hdmi_con_in>;
+ };
+ };
+ };
+ };
+
+ pinctrl {
+ hdmi {
+ hdmi_ctl: hdmi-ctl {
+ rockchip,pins = <1 RK_PB0 1 &pcfg_pull_none>,
+ <1 RK_PB1 1 &pcfg_pull_none>,
+ <1 RK_PB2 1 &pcfg_pull_none>,
+ <1 RK_PB3 1 &pcfg_pull_none>;
+ };
+ };
+ };
diff --git a/dts/upstream/Bindings/display/rockchip/rockchip-vop2.yaml b/dts/upstream/Bindings/display/rockchip/rockchip-vop2.yaml
index b60b904..2531726 100644
--- a/dts/upstream/Bindings/display/rockchip/rockchip-vop2.yaml
+++ b/dts/upstream/Bindings/display/rockchip/rockchip-vop2.yaml
@@ -8,8 +8,8 @@
description:
VOP2 (Video Output Processor v2) is the display controller for the Rockchip
- series of SoCs which transfers the image data from a video memory
- buffer to an external LCD interface.
+ series of SoCs which transfers the image data from a video memory buffer to
+ an external LCD interface.
maintainers:
- Sandy Huang <hjc@rock-chips.com>
@@ -20,6 +20,7 @@
enum:
- rockchip,rk3566-vop
- rockchip,rk3568-vop
+ - rockchip,rk3588-vop
reg:
items:
@@ -27,8 +28,8 @@
Must contain one entry corresponding to the base address and length
of the register space.
- description:
- Can optionally contain a second entry corresponding to
- the CRTC gamma LUT address.
+ Can optionally contain a second entry corresponding to the CRTC gamma
+ LUT address.
reg-names:
items:
@@ -41,45 +42,63 @@
The VOP interrupt is shared by several interrupt sources, such as
frame start (VSYNC), line flag and other status interrupts.
+ # See compatible-specific constraints below.
clocks:
+ minItems: 5
items:
- - description: Clock for ddr buffer transfer.
- - description: Clock for the ahb bus to R/W the phy regs.
+ - description: Clock for ddr buffer transfer via axi.
+ - description: Clock for the ahb bus to R/W the regs.
- description: Pixel clock for video port 0.
- description: Pixel clock for video port 1.
- description: Pixel clock for video port 2.
+ - description: Pixel clock for video port 3.
+ - description: Peripheral(vop grf/dsi) clock.
clock-names:
+ minItems: 5
items:
- const: aclk
- const: hclk
- const: dclk_vp0
- const: dclk_vp1
- const: dclk_vp2
+ - const: dclk_vp3
+ - const: pclk_vop
rockchip,grf:
$ref: /schemas/types.yaml#/definitions/phandle
description:
- Phandle to GRF regs used for misc control
+ Phandle to GRF regs used for control the polarity of dclk/hsync/vsync of DPI,
+ also used for query vop memory bisr enable status, etc.
+
+ rockchip,vo1-grf:
+ $ref: /schemas/types.yaml#/definitions/phandle
+ description:
+ Phandle to VO GRF regs used for control the polarity of dclk/hsync/vsync of hdmi
+ on rk3588.
+
+ rockchip,vop-grf:
+ $ref: /schemas/types.yaml#/definitions/phandle
+ description:
+ Phandle to VOP GRF regs used for control data path between vopr and hdmi/edp.
+
+ rockchip,pmu:
+ $ref: /schemas/types.yaml#/definitions/phandle
+ description:
+ Phandle to PMU GRF used for query vop memory bisr status on rk3588.
ports:
$ref: /schemas/graph.yaml#/properties/ports
- properties:
- port@0:
+ patternProperties:
+ "^port@[0-3]$":
$ref: /schemas/graph.yaml#/properties/port
- description:
- Output endpoint of VP0
+ description: Output endpoint of VP0/1/2/3.
- port@1:
- $ref: /schemas/graph.yaml#/properties/port
- description:
- Output endpoint of VP1
+ required:
+ - port@0
- port@2:
- $ref: /schemas/graph.yaml#/properties/port
- description:
- Output endpoint of VP2
+ unevaluatedProperties: false
iommus:
maxItems: 1
@@ -96,6 +115,49 @@
- clock-names
- ports
+allOf:
+ - if:
+ properties:
+ compatible:
+ contains:
+ const: rockchip,rk3588-vop
+ then:
+ properties:
+ clocks:
+ minItems: 7
+ clock-names:
+ minItems: 7
+
+ ports:
+ required:
+ - port@0
+ - port@1
+ - port@2
+ - port@3
+
+ required:
+ - rockchip,grf
+ - rockchip,vo1-grf
+ - rockchip,vop-grf
+ - rockchip,pmu
+
+ else:
+ properties:
+ rockchip,vo1-grf: false
+ rockchip,vop-grf: false
+ rockchip,pmu: false
+
+ clocks:
+ maxItems: 5
+ clock-names:
+ maxItems: 5
+
+ ports:
+ required:
+ - port@0
+ - port@1
+ - port@2
+
additionalProperties: false
examples:
diff --git a/dts/upstream/Bindings/display/samsung/samsung,exynos-mixer.yaml b/dts/upstream/Bindings/display/samsung/samsung,exynos-mixer.yaml
index 25d53fd..597c9cc 100644
--- a/dts/upstream/Bindings/display/samsung/samsung,exynos-mixer.yaml
+++ b/dts/upstream/Bindings/display/samsung/samsung,exynos-mixer.yaml
@@ -85,7 +85,7 @@
clocks:
minItems: 6
maxItems: 6
- regs:
+ reg:
minItems: 2
maxItems: 2
@@ -99,7 +99,7 @@
clocks:
minItems: 4
maxItems: 4
- regs:
+ reg:
minItems: 2
maxItems: 2
@@ -116,7 +116,7 @@
clocks:
minItems: 3
maxItems: 3
- regs:
+ reg:
minItems: 1
maxItems: 1
diff --git a/dts/upstream/Bindings/display/ti/ti,am65x-dss.yaml b/dts/upstream/Bindings/display/ti/ti,am65x-dss.yaml
index ae09cd3..b6767ef 100644
--- a/dts/upstream/Bindings/display/ti/ti,am65x-dss.yaml
+++ b/dts/upstream/Bindings/display/ti/ti,am65x-dss.yaml
@@ -23,6 +23,7 @@
compatible:
enum:
- ti,am625-dss
+ - ti,am62a7,dss
- ti,am65x-dss
reg:
@@ -87,6 +88,7 @@
For AM65x DSS, the OLDI output port node from video port 1.
For AM625 DSS, the internal DPI output port node from video
port 1.
+ For AM62A7 DSS, the port is tied off inside the SoC.
port@1:
$ref: /schemas/graph.yaml#/properties/port
@@ -108,6 +110,18 @@
Input memory (from main memory to dispc) bandwidth limit in
bytes per second
+allOf:
+ - if:
+ properties:
+ compatible:
+ contains:
+ const: ti,am62a7-dss
+ then:
+ properties:
+ ports:
+ properties:
+ port@0: false
+
required:
- compatible
- reg
diff --git a/dts/upstream/Bindings/dma/dma-controller.yaml b/dts/upstream/Bindings/dma/dma-controller.yaml
index 04d150d..e6afca5 100644
--- a/dts/upstream/Bindings/dma/dma-controller.yaml
+++ b/dts/upstream/Bindings/dma/dma-controller.yaml
@@ -19,19 +19,4 @@
additionalProperties: true
-examples:
- - |
- dma: dma-controller@48000000 {
- compatible = "ti,omap-sdma";
- reg = <0x48000000 0x1000>;
- interrupts = <0 12 0x4>,
- <0 13 0x4>,
- <0 14 0x4>,
- <0 15 0x4>;
- #dma-cells = <1>;
- dma-channels = <32>;
- dma-requests = <127>;
- dma-channel-mask = <0xfffe>;
- };
-
...
diff --git a/dts/upstream/Bindings/dma/dma-router.yaml b/dts/upstream/Bindings/dma/dma-router.yaml
index 346fe0f..5ad2feb 100644
--- a/dts/upstream/Bindings/dma/dma-router.yaml
+++ b/dts/upstream/Bindings/dma/dma-router.yaml
@@ -40,15 +40,4 @@
additionalProperties: true
-examples:
- - |
- sdma_xbar: dma-router@4a002b78 {
- compatible = "ti,dra7-dma-crossbar";
- reg = <0x4a002b78 0xfc>;
- #dma-cells = <1>;
- dma-requests = <205>;
- ti,dma-safe-map = <0>;
- dma-masters = <&sdma>;
- };
-
...
diff --git a/dts/upstream/Bindings/dma/loongson,ls2x-apbdma.yaml b/dts/upstream/Bindings/dma/loongson,ls2x-apbdma.yaml
new file mode 100644
index 0000000..6a1b49a
--- /dev/null
+++ b/dts/upstream/Bindings/dma/loongson,ls2x-apbdma.yaml
@@ -0,0 +1,62 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/dma/loongson,ls2x-apbdma.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Loongson LS2X APB DMA controller
+
+description:
+ The Loongson LS2X APB DMA controller is used for transferring data
+ between system memory and the peripherals on the APB bus.
+
+maintainers:
+ - Binbin Zhou <zhoubinbin@loongson.cn>
+
+allOf:
+ - $ref: dma-controller.yaml#
+
+properties:
+ compatible:
+ oneOf:
+ - const: loongson,ls2k1000-apbdma
+ - items:
+ - const: loongson,ls2k0500-apbdma
+ - const: loongson,ls2k1000-apbdma
+
+ reg:
+ maxItems: 1
+
+ interrupts:
+ maxItems: 1
+
+ clocks:
+ maxItems: 1
+
+ '#dma-cells':
+ const: 1
+
+required:
+ - compatible
+ - reg
+ - interrupts
+ - clocks
+ - '#dma-cells'
+
+additionalProperties: false
+
+examples:
+ - |
+ #include <dt-bindings/interrupt-controller/irq.h>
+ #include <dt-bindings/clock/loongson,ls2k-clk.h>
+
+ dma-controller@1fe00c00 {
+ compatible = "loongson,ls2k1000-apbdma";
+ reg = <0x1fe00c00 0x8>;
+ interrupt-parent = <&liointc1>;
+ interrupts = <12 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&clk LOONGSON2_APB_CLK>;
+ #dma-cells = <1>;
+ };
+
+...
diff --git a/dts/upstream/Bindings/dma/nvidia,tegra210-adma.yaml b/dts/upstream/Bindings/dma/nvidia,tegra210-adma.yaml
index 4003dbe..877147e 100644
--- a/dts/upstream/Bindings/dma/nvidia,tegra210-adma.yaml
+++ b/dts/upstream/Bindings/dma/nvidia,tegra210-adma.yaml
@@ -53,6 +53,9 @@
ADMA_CHn_CTRL register.
const: 1
+ dma-channel-mask:
+ maxItems: 1
+
required:
- compatible
- reg
diff --git a/dts/upstream/Bindings/dma/qcom,gpi.yaml b/dts/upstream/Bindings/dma/qcom,gpi.yaml
index 88d0de3..deb64cb 100644
--- a/dts/upstream/Bindings/dma/qcom,gpi.yaml
+++ b/dts/upstream/Bindings/dma/qcom,gpi.yaml
@@ -32,6 +32,8 @@
- qcom,sm8350-gpi-dma
- qcom,sm8450-gpi-dma
- qcom,sm8550-gpi-dma
+ - qcom,sm8650-gpi-dma
+ - qcom,x1e80100-gpi-dma
- const: qcom,sm6350-gpi-dma
- items:
- enum:
diff --git a/dts/upstream/Bindings/dma/renesas,rz-dmac.yaml b/dts/upstream/Bindings/dma/renesas,rz-dmac.yaml
index c284abc..a42b6a2 100644
--- a/dts/upstream/Bindings/dma/renesas,rz-dmac.yaml
+++ b/dts/upstream/Bindings/dma/renesas,rz-dmac.yaml
@@ -16,7 +16,7 @@
compatible:
items:
- enum:
- - renesas,r9a07g043-dmac # RZ/G2UL
+ - renesas,r9a07g043-dmac # RZ/G2UL and RZ/Five
- renesas,r9a07g044-dmac # RZ/G2{L,LC}
- renesas,r9a07g054-dmac # RZ/V2L
- const: renesas,rz-dmac
diff --git a/dts/upstream/Bindings/dma/sifive,fu540-c000-pdma.yaml b/dts/upstream/Bindings/dma/sifive,fu540-c000-pdma.yaml
index a1af0b9..3b22183 100644
--- a/dts/upstream/Bindings/dma/sifive,fu540-c000-pdma.yaml
+++ b/dts/upstream/Bindings/dma/sifive,fu540-c000-pdma.yaml
@@ -29,6 +29,7 @@
compatible:
items:
- enum:
+ - microchip,mpfs-pdma
- sifive,fu540-c000-pdma
- const: sifive,pdma0
description:
diff --git a/dts/upstream/Bindings/dma/ti/k3-bcdma.yaml b/dts/upstream/Bindings/dma/ti/k3-bcdma.yaml
index 4ca300a..27b8e16 100644
--- a/dts/upstream/Bindings/dma/ti/k3-bcdma.yaml
+++ b/dts/upstream/Bindings/dma/ti/k3-bcdma.yaml
@@ -37,11 +37,11 @@
reg:
minItems: 3
- maxItems: 5
+ maxItems: 9
reg-names:
minItems: 3
- maxItems: 5
+ maxItems: 9
"#dma-cells":
const: 3
@@ -141,7 +141,10 @@
ti,sci-rm-range-tchan: false
reg:
- maxItems: 3
+ items:
+ - description: BCDMA Control /Status Registers region
+ - description: RX Channel Realtime Registers region
+ - description: Ring Realtime Registers region
reg-names:
items:
@@ -161,14 +164,29 @@
properties:
reg:
minItems: 5
+ items:
+ - description: BCDMA Control /Status Registers region
+ - description: Block Copy Channel Realtime Registers region
+ - description: RX Channel Realtime Registers region
+ - description: TX Channel Realtime Registers region
+ - description: Ring Realtime Registers region
+ - description: Ring Configuration Registers region
+ - description: TX Channel Configuration Registers region
+ - description: RX Channel Configuration Registers region
+ - description: Block Copy Channel Configuration Registers region
reg-names:
+ minItems: 5
items:
- const: gcfg
- const: bchanrt
- const: rchanrt
- const: tchanrt
- const: ringrt
+ - const: ring
+ - const: tchan
+ - const: rchan
+ - const: bchan
required:
- ti,sci-rm-range-bchan
@@ -184,7 +202,11 @@
ti,sci-rm-range-bchan: false
reg:
- maxItems: 4
+ items:
+ - description: BCDMA Control /Status Registers region
+ - description: RX Channel Realtime Registers region
+ - description: TX Channel Realtime Registers region
+ - description: Ring Realtime Registers region
reg-names:
items:
@@ -220,8 +242,13 @@
<0x0 0x4c000000 0x0 0x20000>,
<0x0 0x4a820000 0x0 0x20000>,
<0x0 0x4aa40000 0x0 0x20000>,
- <0x0 0x4bc00000 0x0 0x100000>;
- reg-names = "gcfg", "bchanrt", "rchanrt", "tchanrt", "ringrt";
+ <0x0 0x4bc00000 0x0 0x100000>,
+ <0x0 0x48600000 0x0 0x8000>,
+ <0x0 0x484a4000 0x0 0x2000>,
+ <0x0 0x484c2000 0x0 0x2000>,
+ <0x0 0x48420000 0x0 0x2000>;
+ reg-names = "gcfg", "bchanrt", "rchanrt", "tchanrt", "ringrt",
+ "ring", "tchan", "rchan", "bchan";
msi-parent = <&inta_main_dmss>;
#dma-cells = <3>;
diff --git a/dts/upstream/Bindings/dma/ti/k3-pktdma.yaml b/dts/upstream/Bindings/dma/ti/k3-pktdma.yaml
index a69f62f..11e064c 100644
--- a/dts/upstream/Bindings/dma/ti/k3-pktdma.yaml
+++ b/dts/upstream/Bindings/dma/ti/k3-pktdma.yaml
@@ -45,14 +45,28 @@
The second cell is the ASEL value for the channel
reg:
- maxItems: 4
+ minItems: 4
+ items:
+ - description: Packet DMA Control /Status Registers region
+ - description: RX Channel Realtime Registers region
+ - description: TX Channel Realtime Registers region
+ - description: Ring Realtime Registers region
+ - description: Ring Configuration Registers region
+ - description: TX Configuration Registers region
+ - description: RX Configuration Registers region
+ - description: RX Flow Configuration Registers region
reg-names:
+ minItems: 4
items:
- const: gcfg
- const: rchanrt
- const: tchanrt
- const: ringrt
+ - const: ring
+ - const: tchan
+ - const: rchan
+ - const: rflow
msi-parent: true
@@ -136,8 +150,14 @@
reg = <0x0 0x485c0000 0x0 0x100>,
<0x0 0x4a800000 0x0 0x20000>,
<0x0 0x4aa00000 0x0 0x40000>,
- <0x0 0x4b800000 0x0 0x400000>;
- reg-names = "gcfg", "rchanrt", "tchanrt", "ringrt";
+ <0x0 0x4b800000 0x0 0x400000>,
+ <0x0 0x485e0000 0x0 0x20000>,
+ <0x0 0x484a0000 0x0 0x4000>,
+ <0x0 0x484c0000 0x0 0x2000>,
+ <0x0 0x48430000 0x0 0x4000>;
+ reg-names = "gcfg", "rchanrt", "tchanrt", "ringrt",
+ "ring", "tchan", "rchan", "rflow";
+
msi-parent = <&inta_main_dmss>;
#dma-cells = <2>;
diff --git a/dts/upstream/Bindings/dma/ti/k3-udma.yaml b/dts/upstream/Bindings/dma/ti/k3-udma.yaml
index 22f6c5e..b18cf2b 100644
--- a/dts/upstream/Bindings/dma/ti/k3-udma.yaml
+++ b/dts/upstream/Bindings/dma/ti/k3-udma.yaml
@@ -69,13 +69,24 @@
- ti,j721e-navss-mcu-udmap
reg:
- maxItems: 3
+ minItems: 3
+ items:
+ - description: UDMA-P Control /Status Registers region
+ - description: RX Channel Realtime Registers region
+ - description: TX Channel Realtime Registers region
+ - description: TX Configuration Registers region
+ - description: RX Configuration Registers region
+ - description: RX Flow Configuration Registers region
reg-names:
+ minItems: 3
items:
- const: gcfg
- const: rchanrt
- const: tchanrt
+ - const: tchan
+ - const: rchan
+ - const: rflow
msi-parent: true
@@ -158,8 +169,11 @@
compatible = "ti,am654-navss-main-udmap";
reg = <0x0 0x31150000 0x0 0x100>,
<0x0 0x34000000 0x0 0x100000>,
- <0x0 0x35000000 0x0 0x100000>;
- reg-names = "gcfg", "rchanrt", "tchanrt";
+ <0x0 0x35000000 0x0 0x100000>,
+ <0x0 0x30b00000 0x0 0x20000>,
+ <0x0 0x30c00000 0x0 0x8000>,
+ <0x0 0x30d00000 0x0 0x4000>;
+ reg-names = "gcfg", "rchanrt", "tchanrt", "tchan", "rchan", "rflow";
#dma-cells = <1>;
ti,ringacc = <&ringacc>;
diff --git a/dts/upstream/Bindings/dts-coding-style.rst b/dts/upstream/Bindings/dts-coding-style.rst
new file mode 100644
index 0000000..a9bdd2b
--- /dev/null
+++ b/dts/upstream/Bindings/dts-coding-style.rst
@@ -0,0 +1,196 @@
+.. SPDX-License-Identifier: GPL-2.0
+
+=====================================
+Devicetree Sources (DTS) Coding Style
+=====================================
+
+When writing Devicetree Sources (DTS) please observe below guidelines. They
+should be considered complementary to any rules expressed already in
+the Devicetree Specification and the dtc compiler (including W=1 and W=2
+builds).
+
+Individual architectures and subarchitectures can define additional rules,
+making the coding style stricter.
+
+Naming and Valid Characters
+---------------------------
+
+The Devicetree Specification allows a broad range of characters in node
+and property names, but this coding style narrows the range down to achieve
+better code readability.
+
+1. Node and property names can use only the following characters:
+
+ * Lowercase characters: [a-z]
+ * Digits: [0-9]
+ * Dash: -
+
+2. Labels can use only the following characters:
+
+ * Lowercase characters: [a-z]
+ * Digits: [0-9]
+ * Underscore: _
+
+3. Unless a bus defines differently, unit addresses shall use lowercase
+ hexadecimal digits, without leading zeros (padding).
+
+4. Hex values in properties, e.g. "reg", shall use lowercase hex. The address
+ part can be padded with leading zeros.
+
+Example::
+
+ gpi_dma2: dma-controller@a00000 {
+ compatible = "qcom,sm8550-gpi-dma", "qcom,sm6350-gpi-dma";
+ reg = <0x0 0x00a00000 0x0 0x60000>;
+ }
+
+Order of Nodes
+--------------
+
+1. Nodes on any bus, thus using unit addresses for children, shall be
+ ordered by unit address in ascending order.
+ Alternatively for some subarchitectures, nodes of the same type can be
+ grouped together, e.g. all I2C controllers one after another even if this
+ breaks unit address ordering.
+
+2. Nodes without unit addresses shall be ordered alpha-numerically by the node
+ name. For a few node types, they can be ordered by the main property, e.g.
+ pin configuration states ordered by value of "pins" property.
+
+3. When extending nodes in the board DTS via &label, the entries shall be
+ ordered either alpha-numerically or by keeping the order from DTSI, where
+ the choice depends on the subarchitecture.
+
+The above-described ordering rules are easy to enforce during review, reduce
+chances of conflicts for simultaneous additions of new nodes to a file and help
+in navigating through the DTS source.
+
+Example::
+
+ /* SoC DTSI */
+
+ / {
+ cpus {
+ /* ... */
+ };
+
+ psci {
+ /* ... */
+ };
+
+ soc@0 {
+ dma: dma-controller@10000 {
+ /* ... */
+ };
+
+ clk: clock-controller@80000 {
+ /* ... */
+ };
+ };
+ };
+
+ /* Board DTS - alphabetical order */
+
+ &clk {
+ /* ... */
+ };
+
+ &dma {
+ /* ... */
+ };
+
+ /* Board DTS - alternative order, keep as DTSI */
+
+ &dma {
+ /* ... */
+ };
+
+ &clk {
+ /* ... */
+ };
+
+Order of Properties in Device Node
+----------------------------------
+
+The following order of properties in device nodes is preferred:
+
+1. "compatible"
+2. "reg"
+3. "ranges"
+4. Standard/common properties (defined by common bindings, e.g. without
+ vendor-prefixes)
+5. Vendor-specific properties
+6. "status" (if applicable)
+7. Child nodes, where each node is preceded with a blank line
+
+The "status" property is by default "okay", thus it can be omitted.
+
+The above-described ordering follows this approach:
+
+1. Most important properties start the node: compatible then bus addressing to
+ match unit address.
+2. Each node will have common properties in similar place.
+3. Status is the last information to annotate that device node is or is not
+ finished (board resources are needed).
+
+Example::
+
+ /* SoC DTSI */
+
+ device_node: device-class@6789abc {
+ compatible = "vendor,device";
+ reg = <0x0 0x06789abc 0x0 0xa123>;
+ ranges = <0x0 0x0 0x06789abc 0x1000>;
+ #dma-cells = <1>;
+ clocks = <&clock_controller 0>, <&clock_controller 1>;
+ clock-names = "bus", "host";
+ vendor,custom-property = <2>;
+ status = "disabled";
+
+ child_node: child-class@100 {
+ reg = <0x100 0x200>;
+ /* ... */
+ };
+ };
+
+ /* Board DTS */
+
+ &device_node {
+ vdd-supply = <&board_vreg1>;
+ status = "okay";
+ }
+
+Indentation
+-----------
+
+1. Use indentation according to Documentation/process/coding-style.rst.
+2. Each entry in arrays with multiple cells, e.g. "reg" with two IO addresses,
+ shall be enclosed in <>.
+3. For arrays spanning across lines, it is preferred to align the continued
+ entries with opening < from the first line.
+
+Example::
+
+ thermal-sensor@c271000 {
+ compatible = "qcom,sm8550-tsens", "qcom,tsens-v2";
+ reg = <0x0 0x0c271000 0x0 0x1000>,
+ <0x0 0x0c222000 0x0 0x1000>;
+ };
+
+Organizing DTSI and DTS
+-----------------------
+
+The DTSI and DTS files shall be organized in a way representing the common,
+reusable parts of hardware. Typically, this means organizing DTSI and DTS files
+into several files:
+
+1. DTSI with contents of the entire SoC, without nodes for hardware not present
+ on the SoC.
+2. If applicable: DTSI with common or re-usable parts of the hardware, e.g.
+ entire System-on-Module.
+3. DTS representing the board.
+
+Hardware components that are present on the board shall be placed in the
+board DTS, not in the SoC or SoM DTSI. A partial exception is a common
+external reference SoC input clock, which could be coded as a fixed-clock in
+the SoC DTSI with its frequency provided by each board DTS.
diff --git a/dts/upstream/Bindings/eeprom/at24.yaml b/dts/upstream/Bindings/eeprom/at24.yaml
index b6864d0..1812ef3 100644
--- a/dts/upstream/Bindings/eeprom/at24.yaml
+++ b/dts/upstream/Bindings/eeprom/at24.yaml
@@ -123,6 +123,7 @@
- enum:
- onnn,cat24c04
- onnn,cat24c05
+ - rohm,br24g04
- const: atmel,24c04
- items:
- const: renesas,r1ex24016
diff --git a/dts/upstream/Bindings/firmware/qcom,scm.yaml b/dts/upstream/Bindings/firmware/qcom,scm.yaml
index 0613a37..47d3d2d 100644
--- a/dts/upstream/Bindings/firmware/qcom,scm.yaml
+++ b/dts/upstream/Bindings/firmware/qcom,scm.yaml
@@ -63,7 +63,9 @@
- qcom,scm-sm8350
- qcom,scm-sm8450
- qcom,scm-sm8550
+ - qcom,scm-sm8650
- qcom,scm-qcs404
+ - qcom,scm-x1e80100
- const: qcom,scm
clocks:
@@ -178,21 +180,6 @@
minItems: 3
maxItems: 3
- # Interconnects
- - if:
- not:
- properties:
- compatible:
- contains:
- enum:
- - qcom,scm-qdu1000
- - qcom,scm-sc8280xp
- - qcom,scm-sm8450
- - qcom,scm-sm8550
- then:
- properties:
- interconnects: false
-
# Interrupts
- if:
not:
@@ -202,6 +189,7 @@
enum:
- qcom,scm-sm8450
- qcom,scm-sm8550
+ - qcom,scm-sm8650
then:
properties:
interrupts: false
diff --git a/dts/upstream/Bindings/firmware/xilinx/xlnx,zynqmp-firmware.yaml b/dts/upstream/Bindings/firmware/xilinx/xlnx,zynqmp-firmware.yaml
index 8228644..8e58485 100644
--- a/dts/upstream/Bindings/firmware/xilinx/xlnx,zynqmp-firmware.yaml
+++ b/dts/upstream/Bindings/firmware/xilinx/xlnx,zynqmp-firmware.yaml
@@ -95,8 +95,8 @@
versal_clk: clock-controller {
#clock-cells = <1>;
compatible = "xlnx,versal-clk";
- clocks = <&ref>, <&alt_ref>, <&pl_alt_ref>;
- clock-names = "ref", "alt_ref", "pl_alt_ref";
+ clocks = <&ref>, <&pl_alt_ref>;
+ clock-names = "ref", "pl_alt_ref";
};
};
diff --git a/dts/upstream/Bindings/fpga/altera-fpga2sdram-bridge.txt b/dts/upstream/Bindings/fpga/altera-fpga2sdram-bridge.txt
deleted file mode 100644
index 5dd0ff0..0000000
--- a/dts/upstream/Bindings/fpga/altera-fpga2sdram-bridge.txt
+++ /dev/null
@@ -1,13 +0,0 @@
-Altera FPGA To SDRAM Bridge Driver
-
-Required properties:
-- compatible : Should contain "altr,socfpga-fpga2sdram-bridge"
-
-See Documentation/devicetree/bindings/fpga/fpga-bridge.txt for generic bindings.
-
-Example:
- fpga_bridge3: fpga-bridge@ffc25080 {
- compatible = "altr,socfpga-fpga2sdram-bridge";
- reg = <0xffc25080 0x4>;
- bridge-enable = <0>;
- };
diff --git a/dts/upstream/Bindings/fpga/altera-freeze-bridge.txt b/dts/upstream/Bindings/fpga/altera-freeze-bridge.txt
deleted file mode 100644
index 8b26fbc..0000000
--- a/dts/upstream/Bindings/fpga/altera-freeze-bridge.txt
+++ /dev/null
@@ -1,20 +0,0 @@
-Altera Freeze Bridge Controller Driver
-
-The Altera Freeze Bridge Controller manages one or more freeze bridges.
-The controller can freeze/disable the bridges which prevents signal
-changes from passing through the bridge. The controller can also
-unfreeze/enable the bridges which allows traffic to pass through the
-bridge normally.
-
-Required properties:
-- compatible : Should contain "altr,freeze-bridge-controller"
-- regs : base address and size for freeze bridge module
-
-See Documentation/devicetree/bindings/fpga/fpga-bridge.txt for generic bindings.
-
-Example:
- freeze-controller@100000450 {
- compatible = "altr,freeze-bridge-controller";
- regs = <0x1000 0x10>;
- bridge-enable = <0>;
- };
diff --git a/dts/upstream/Bindings/fpga/altera-hps2fpga-bridge.txt b/dts/upstream/Bindings/fpga/altera-hps2fpga-bridge.txt
deleted file mode 100644
index 68cce39..0000000
--- a/dts/upstream/Bindings/fpga/altera-hps2fpga-bridge.txt
+++ /dev/null
@@ -1,36 +0,0 @@
-Altera FPGA/HPS Bridge Driver
-
-Required properties:
-- regs : base address and size for AXI bridge module
-- compatible : Should contain one of:
- "altr,socfpga-lwhps2fpga-bridge",
- "altr,socfpga-hps2fpga-bridge", or
- "altr,socfpga-fpga2hps-bridge"
-- resets : Phandle and reset specifier for this bridge's reset
-- clocks : Clocks used by this module.
-
-See Documentation/devicetree/bindings/fpga/fpga-bridge.txt for generic bindings.
-
-Example:
- fpga_bridge0: fpga-bridge@ff400000 {
- compatible = "altr,socfpga-lwhps2fpga-bridge";
- reg = <0xff400000 0x100000>;
- resets = <&rst LWHPS2FPGA_RESET>;
- clocks = <&l4_main_clk>;
- bridge-enable = <0>;
- };
-
- fpga_bridge1: fpga-bridge@ff500000 {
- compatible = "altr,socfpga-hps2fpga-bridge";
- reg = <0xff500000 0x10000>;
- resets = <&rst HPS2FPGA_RESET>;
- clocks = <&l4_main_clk>;
- bridge-enable = <1>;
- };
-
- fpga_bridge2: fpga-bridge@ff600000 {
- compatible = "altr,socfpga-fpga2hps-bridge";
- reg = <0xff600000 0x100000>;
- resets = <&rst FPGA2HPS_RESET>;
- clocks = <&l4_main_clk>;
- };
diff --git a/dts/upstream/Bindings/fpga/altr,freeze-bridge-controller.yaml b/dts/upstream/Bindings/fpga/altr,freeze-bridge-controller.yaml
new file mode 100644
index 0000000..fccffee
--- /dev/null
+++ b/dts/upstream/Bindings/fpga/altr,freeze-bridge-controller.yaml
@@ -0,0 +1,41 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/fpga/altr,freeze-bridge-controller.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Altera Freeze Bridge Controller
+
+description:
+ The Altera Freeze Bridge Controller manages one or more freeze bridges.
+ The controller can freeze/disable the bridges which prevents signal
+ changes from passing through the bridge. The controller can also
+ unfreeze/enable the bridges which allows traffic to pass through the bridge
+ normally.
+
+maintainers:
+ - Xu Yilun <yilun.xu@intel.com>
+
+allOf:
+ - $ref: fpga-bridge.yaml#
+
+properties:
+ compatible:
+ const: altr,freeze-bridge-controller
+
+ reg:
+ maxItems: 1
+
+required:
+ - compatible
+ - reg
+
+unevaluatedProperties: false
+
+examples:
+ - |
+ fpga-bridge@100000450 {
+ compatible = "altr,freeze-bridge-controller";
+ reg = <0x1000 0x10>;
+ bridge-enable = <0>;
+ };
diff --git a/dts/upstream/Bindings/fpga/altr,socfpga-fpga2sdram-bridge.yaml b/dts/upstream/Bindings/fpga/altr,socfpga-fpga2sdram-bridge.yaml
new file mode 100644
index 0000000..22b5845
--- /dev/null
+++ b/dts/upstream/Bindings/fpga/altr,socfpga-fpga2sdram-bridge.yaml
@@ -0,0 +1,33 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/fpga/altr,socfpga-fpga2sdram-bridge.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Altera FPGA To SDRAM Bridge
+
+maintainers:
+ - Xu Yilun <yilun.xu@intel.com>
+
+allOf:
+ - $ref: fpga-bridge.yaml#
+
+properties:
+ compatible:
+ const: altr,socfpga-fpga2sdram-bridge
+
+ reg:
+ maxItems: 1
+
+required:
+ - compatible
+
+unevaluatedProperties: false
+
+examples:
+ - |
+ fpga-bridge@ffc25080 {
+ compatible = "altr,socfpga-fpga2sdram-bridge";
+ reg = <0xffc25080 0x4>;
+ bridge-enable = <0>;
+ };
diff --git a/dts/upstream/Bindings/fpga/altr,socfpga-hps2fpga-bridge.yaml b/dts/upstream/Bindings/fpga/altr,socfpga-hps2fpga-bridge.yaml
new file mode 100644
index 0000000..d19c666
--- /dev/null
+++ b/dts/upstream/Bindings/fpga/altr,socfpga-hps2fpga-bridge.yaml
@@ -0,0 +1,49 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/fpga/altr,socfpga-hps2fpga-bridge.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Altera FPGA/HPS Bridge
+
+maintainers:
+ - Xu Yilun <yilun.xu@intel.com>
+
+allOf:
+ - $ref: fpga-bridge.yaml#
+
+properties:
+ compatible:
+ enum:
+ - altr,socfpga-lwhps2fpga-bridge
+ - altr,socfpga-hps2fpga-bridge
+ - altr,socfpga-fpga2hps-bridge
+
+ reg:
+ maxItems: 1
+
+ resets:
+ maxItems: 1
+
+ clocks:
+ maxItems: 1
+
+required:
+ - compatible
+ - reg
+ - clocks
+ - resets
+
+unevaluatedProperties: false
+
+examples:
+ - |
+ #include <dt-bindings/reset/altr,rst-mgr.h>
+
+ fpga-bridge@ff400000 {
+ compatible = "altr,socfpga-lwhps2fpga-bridge";
+ reg = <0xff400000 0x100000>;
+ bridge-enable = <0>;
+ clocks = <&l4_main_clk>;
+ resets = <&rst LWHPS2FPGA_RESET>;
+ };
diff --git a/dts/upstream/Bindings/fpga/fpga-bridge.txt b/dts/upstream/Bindings/fpga/fpga-bridge.txt
deleted file mode 100644
index 72e0691..0000000
--- a/dts/upstream/Bindings/fpga/fpga-bridge.txt
+++ /dev/null
@@ -1,13 +0,0 @@
-FPGA Bridge Device Tree Binding
-
-Optional properties:
-- bridge-enable : 0 if driver should disable bridge at startup
- 1 if driver should enable bridge at startup
- Default is to leave bridge in current state.
-
-Example:
- fpga_bridge3: fpga-bridge@ffc25080 {
- compatible = "altr,socfpga-fpga2sdram-bridge";
- reg = <0xffc25080 0x4>;
- bridge-enable = <0>;
- };
diff --git a/dts/upstream/Bindings/fpga/fpga-bridge.yaml b/dts/upstream/Bindings/fpga/fpga-bridge.yaml
new file mode 100644
index 0000000..1ccb2aa
--- /dev/null
+++ b/dts/upstream/Bindings/fpga/fpga-bridge.yaml
@@ -0,0 +1,30 @@
+# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/fpga/fpga-bridge.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: FPGA Bridge
+
+maintainers:
+ - Michal Simek <michal.simek@amd.com>
+
+properties:
+ $nodename:
+ pattern: "^fpga-bridge(@.*|-([0-9]|[1-9][0-9]+))?$"
+
+ bridge-enable:
+ description: |
+ 0 if driver should disable bridge at startup
+ 1 if driver should enable bridge at startup
+ Default is to leave bridge in current state.
+ $ref: /schemas/types.yaml#/definitions/uint32
+ enum: [ 0, 1 ]
+
+additionalProperties: true
+
+examples:
+ - |
+ fpga-bridge {
+ bridge-enable = <0>;
+ };
diff --git a/dts/upstream/Bindings/fpga/xlnx,pr-decoupler.yaml b/dts/upstream/Bindings/fpga/xlnx,pr-decoupler.yaml
index a7d4b8e..5bf731f 100644
--- a/dts/upstream/Bindings/fpga/xlnx,pr-decoupler.yaml
+++ b/dts/upstream/Bindings/fpga/xlnx,pr-decoupler.yaml
@@ -9,6 +9,9 @@
maintainers:
- Nava kishore Manne <nava.kishore.manne@amd.com>
+allOf:
+ - $ref: fpga-bridge.yaml#
+
description: |
The Xilinx LogiCORE Partial Reconfig(PR) Decoupler manages one or more
decouplers/fpga bridges. The controller can decouple/disable the bridges
@@ -51,7 +54,7 @@
- clocks
- clock-names
-additionalProperties: false
+unevaluatedProperties: false
examples:
- |
diff --git a/dts/upstream/Bindings/gnss/u-blox,neo-6m.yaml b/dts/upstream/Bindings/gnss/u-blox,neo-6m.yaml
index 4835a28..cd80668 100644
--- a/dts/upstream/Bindings/gnss/u-blox,neo-6m.yaml
+++ b/dts/upstream/Bindings/gnss/u-blox,neo-6m.yaml
@@ -28,6 +28,9 @@
port or the USB host-controller port to which this device is attached,
depending on the bus used. Required for the DDC, SPI or USB busses.
+ reset-gpios:
+ maxItems: 1
+
vcc-supply:
description: >
Main voltage regulator
@@ -49,10 +52,13 @@
examples:
- |
+ #include <dt-bindings/gpio/gpio.h>
+
serial {
gnss {
compatible = "u-blox,neo-8";
v-bckp-supply = <&gnss_v_bckp_reg>;
vcc-supply = <&gnss_vcc_reg>;
+ reset-gpios = <&gpio 1 GPIO_ACTIVE_LOW>;
};
};
diff --git a/dts/upstream/Bindings/gpio/brcm,brcmstb-gpio.yaml b/dts/upstream/Bindings/gpio/brcm,brcmstb-gpio.yaml
index 4a896ff..a1e71c9 100644
--- a/dts/upstream/Bindings/gpio/brcm,brcmstb-gpio.yaml
+++ b/dts/upstream/Bindings/gpio/brcm,brcmstb-gpio.yaml
@@ -72,7 +72,7 @@
- reg
- gpio-controller
- "#gpio-cells"
- - "brcm,gpio-bank-widths"
+ - brcm,gpio-bank-widths
additionalProperties: false
diff --git a/dts/upstream/Bindings/gpio/nuvoton,sgpio.yaml b/dts/upstream/Bindings/gpio/nuvoton,sgpio.yaml
new file mode 100644
index 0000000..9e32e54
--- /dev/null
+++ b/dts/upstream/Bindings/gpio/nuvoton,sgpio.yaml
@@ -0,0 +1,87 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/gpio/nuvoton,sgpio.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Nuvoton SGPIO controller
+
+maintainers:
+ - Jim LIU <JJLIU0@nuvoton.com>
+
+description: |
+ This SGPIO controller is for NUVOTON NPCM7xx and NPCM8xx SoC and detailed
+ information is in the NPCM7XX/8XX SERIAL I/O EXPANSION INTERFACE section.
+ Nuvoton NPCM7xx SGPIO module is combines a serial to parallel IC (HC595)
+ and a parallel to serial IC (HC165).
+ Clock is a division of the APB3 clock.
+ This interface has 4 pins (D_out , D_in, S_CLK, LDSH).
+ NPCM7xx/NPCM8xx have two sgpio modules. Each module can support up
+ to 64 output pins, and up to 64 input pins, the pin is only for GPI or GPO.
+ GPIO pins can be programmed to support the following options
+ - Support interrupt option for each input port and various interrupt
+ sensitivity options (level-high, level-low, edge-high, edge-low)
+ - ngpios is number of nuvoton,input-ngpios GPIO lines and nuvoton,output-ngpios GPIO lines.
+ nuvoton,input-ngpios GPIO lines is only for GPI.
+ nuvoton,output-ngpios GPIO lines is only for GPO.
+
+properties:
+ compatible:
+ enum:
+ - nuvoton,npcm750-sgpio
+ - nuvoton,npcm845-sgpio
+
+ reg:
+ maxItems: 1
+
+ gpio-controller: true
+
+ '#gpio-cells':
+ const: 2
+
+ interrupts:
+ maxItems: 1
+
+ clocks:
+ maxItems: 1
+
+ nuvoton,input-ngpios:
+ $ref: /schemas/types.yaml#/definitions/uint32
+ description:
+ The numbers of GPIO's exposed. GPIO lines are only for GPI.
+ minimum: 0
+ maximum: 64
+
+ nuvoton,output-ngpios:
+ $ref: /schemas/types.yaml#/definitions/uint32
+ description:
+ The numbers of GPIO's exposed. GPIO lines are only for GPO.
+ minimum: 0
+ maximum: 64
+
+required:
+ - compatible
+ - reg
+ - gpio-controller
+ - '#gpio-cells'
+ - interrupts
+ - nuvoton,input-ngpios
+ - nuvoton,output-ngpios
+ - clocks
+
+additionalProperties: false
+
+examples:
+ - |
+ #include <dt-bindings/clock/nuvoton,npcm7xx-clock.h>
+ #include <dt-bindings/interrupt-controller/arm-gic.h>
+ gpio8: gpio@101000 {
+ compatible = "nuvoton,npcm750-sgpio";
+ reg = <0x101000 0x200>;
+ clocks = <&clk NPCM7XX_CLK_APB3>;
+ interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ nuvoton,input-ngpios = <64>;
+ nuvoton,output-ngpios = <64>;
+ };
diff --git a/dts/upstream/Bindings/gpio/realtek,rtd-gpio.yaml b/dts/upstream/Bindings/gpio/realtek,rtd-gpio.yaml
new file mode 100644
index 0000000..dd768db
--- /dev/null
+++ b/dts/upstream/Bindings/gpio/realtek,rtd-gpio.yaml
@@ -0,0 +1,69 @@
+# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
+# Copyright 2023 Realtek Semiconductor Corporation
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/gpio/realtek,rtd-gpio.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Realtek DHC GPIO controller
+
+maintainers:
+ - Tzuyi Chang <tychang@realtek.com>
+
+description:
+ The GPIO controller is designed for the Realtek DHC (Digital Home Center)
+ RTD series SoC family, which are high-definition media processor SoCs.
+
+properties:
+ compatible:
+ enum:
+ - realtek,rtd1295-misc-gpio
+ - realtek,rtd1295-iso-gpio
+ - realtek,rtd1315e-iso-gpio
+ - realtek,rtd1319-iso-gpio
+ - realtek,rtd1319d-iso-gpio
+ - realtek,rtd1395-iso-gpio
+ - realtek,rtd1619-iso-gpio
+ - realtek,rtd1619b-iso-gpio
+
+ reg:
+ items:
+ - description: GPIO controller registers
+ - description: GPIO interrupt registers
+
+ interrupts:
+ items:
+ - description: Interrupt number of the assert GPIO interrupt, which is
+ triggered when there is a rising edge.
+ - description: Interrupt number of the deassert GPIO interrupt, which is
+ triggered when there is a falling edge.
+
+ gpio-ranges: true
+
+ gpio-controller: true
+
+ "#gpio-cells":
+ const: 2
+
+required:
+ - compatible
+ - reg
+ - interrupts
+ - gpio-ranges
+ - gpio-controller
+ - "#gpio-cells"
+
+additionalProperties: false
+
+examples:
+ - |
+ gpio@100 {
+ compatible = "realtek,rtd1319d-iso-gpio";
+ reg = <0x100 0x100>,
+ <0x0 0xb0>;
+ interrupt-parent = <&iso_irq_mux>;
+ interrupts = <19>, <20>;
+ gpio-ranges = <&pinctrl 0 0 82>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ };
diff --git a/dts/upstream/Bindings/gpio/rockchip,gpio-bank.yaml b/dts/upstream/Bindings/gpio/rockchip,gpio-bank.yaml
index affd823..d76987c 100644
--- a/dts/upstream/Bindings/gpio/rockchip,gpio-bank.yaml
+++ b/dts/upstream/Bindings/gpio/rockchip,gpio-bank.yaml
@@ -41,6 +41,13 @@
"#interrupt-cells":
const: 2
+patternProperties:
+ "^.+-hog(-[0-9]+)?$":
+ type: object
+
+ required:
+ - gpio-hog
+
required:
- compatible
- reg
diff --git a/dts/upstream/Bindings/gpio/snps,dw-apb-gpio.yaml b/dts/upstream/Bindings/gpio/snps,dw-apb-gpio.yaml
index eefe7b3..ab2afc0 100644
--- a/dts/upstream/Bindings/gpio/snps,dw-apb-gpio.yaml
+++ b/dts/upstream/Bindings/gpio/snps,dw-apb-gpio.yaml
@@ -65,6 +65,8 @@
minItems: 1
maxItems: 32
+ gpio-ranges: true
+
ngpios:
default: 32
minimum: 1
diff --git a/dts/upstream/Bindings/gpio/xlnx,gpio-xilinx.yaml b/dts/upstream/Bindings/gpio/xlnx,gpio-xilinx.yaml
index c1060e5..d3d8a2e 100644
--- a/dts/upstream/Bindings/gpio/xlnx,gpio-xilinx.yaml
+++ b/dts/upstream/Bindings/gpio/xlnx,gpio-xilinx.yaml
@@ -126,7 +126,7 @@
- |
#include <dt-bindings/interrupt-controller/arm-gic.h>
- gpio@e000a000 {
+ gpio@a0020000 {
compatible = "xlnx,xps-gpio-1.00.a";
reg = <0xa0020000 0x10000>;
#gpio-cells = <2>;
diff --git a/dts/upstream/Bindings/gpio/xlnx,zynqmp-gpio-modepin.yaml b/dts/upstream/Bindings/gpio/xlnx,zynqmp-gpio-modepin.yaml
index 56143f1..bb93baa 100644
--- a/dts/upstream/Bindings/gpio/xlnx,zynqmp-gpio-modepin.yaml
+++ b/dts/upstream/Bindings/gpio/xlnx,zynqmp-gpio-modepin.yaml
@@ -12,7 +12,8 @@
PS_MODE). Every pin can be configured as input/output.
maintainers:
- - Piyush Mehta <piyush.mehta@amd.com>
+ - Mubin Sayyed <mubin.sayyed@amd.com>
+ - Radhey Shyam Pandey <radhey.shyam.pandey@amd.com>
properties:
compatible:
@@ -23,6 +24,8 @@
"#gpio-cells":
const: 2
+ label: true
+
required:
- compatible
- gpio-controller
@@ -37,6 +40,7 @@
compatible = "xlnx,zynqmp-gpio-modepin";
gpio-controller;
#gpio-cells = <2>;
+ label = "modepin";
};
};
diff --git a/dts/upstream/Bindings/gpu/arm,mali-midgard.yaml b/dts/upstream/Bindings/gpu/arm,mali-midgard.yaml
index ca02bab..0801da3 100644
--- a/dts/upstream/Bindings/gpu/arm,mali-midgard.yaml
+++ b/dts/upstream/Bindings/gpu/arm,mali-midgard.yaml
@@ -42,6 +42,11 @@
- const: arm,mali-t760
- items:
- enum:
+ - samsung,exynos7-mali
+ - const: samsung,exynos5433-mali
+ - const: arm,mali-t760
+ - items:
+ - enum:
- rockchip,rk3399-mali
- const: arm,mali-t860
diff --git a/dts/upstream/Bindings/gpu/arm,mali-utgard.yaml b/dts/upstream/Bindings/gpu/arm,mali-utgard.yaml
index 0fae1ef..abd4aa3 100644
--- a/dts/upstream/Bindings/gpu/arm,mali-utgard.yaml
+++ b/dts/upstream/Bindings/gpu/arm,mali-utgard.yaml
@@ -29,6 +29,7 @@
- allwinner,sun50i-a64-mali
- rockchip,rk3036-mali
- rockchip,rk3066-mali
+ - rockchip,rk3128-mali
- rockchip,rk3188-mali
- rockchip,rk3228-mali
- samsung,exynos4210-mali
diff --git a/dts/upstream/Bindings/gpu/brcm,bcm-v3d.yaml b/dts/upstream/Bindings/gpu/brcm,bcm-v3d.yaml
index dae55b8..dc078ce 100644
--- a/dts/upstream/Bindings/gpu/brcm,bcm-v3d.yaml
+++ b/dts/upstream/Bindings/gpu/brcm,bcm-v3d.yaml
@@ -17,6 +17,7 @@
compatible:
enum:
- brcm,2711-v3d
+ - brcm,2712-v3d
- brcm,7268-v3d
- brcm,7278-v3d
diff --git a/dts/upstream/Bindings/gpu/img,powervr.yaml b/dts/upstream/Bindings/gpu/img,powervr.yaml
new file mode 100644
index 0000000..a13298f
--- /dev/null
+++ b/dts/upstream/Bindings/gpu/img,powervr.yaml
@@ -0,0 +1,73 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+# Copyright (c) 2023 Imagination Technologies Ltd.
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/gpu/img,powervr.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Imagination Technologies PowerVR and IMG GPU
+
+maintainers:
+ - Frank Binns <frank.binns@imgtec.com>
+
+properties:
+ compatible:
+ items:
+ - enum:
+ - ti,am62-gpu
+ - const: img,img-axe # IMG AXE GPU model/revision is fully discoverable
+
+ reg:
+ maxItems: 1
+
+ clocks:
+ minItems: 1
+ maxItems: 3
+
+ clock-names:
+ items:
+ - const: core
+ - const: mem
+ - const: sys
+ minItems: 1
+
+ interrupts:
+ maxItems: 1
+
+ power-domains:
+ maxItems: 1
+
+required:
+ - compatible
+ - reg
+ - clocks
+ - clock-names
+ - interrupts
+
+additionalProperties: false
+
+allOf:
+ - if:
+ properties:
+ compatible:
+ contains:
+ const: ti,am62-gpu
+ then:
+ properties:
+ clocks:
+ maxItems: 1
+
+examples:
+ - |
+ #include <dt-bindings/interrupt-controller/irq.h>
+ #include <dt-bindings/interrupt-controller/arm-gic.h>
+ #include <dt-bindings/soc/ti,sci_pm_domain.h>
+
+ gpu@fd00000 {
+ compatible = "ti,am62-gpu", "img,img-axe";
+ reg = <0x0fd00000 0x20000>;
+ clocks = <&k3_clks 187 0>;
+ clock-names = "core";
+ interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
+ power-domains = <&k3_pds 187 TI_SCI_PD_EXCLUSIVE>;
+ };
diff --git a/dts/upstream/Bindings/gpu/samsung-g2d.yaml b/dts/upstream/Bindings/gpu/samsung-g2d.yaml
index e7daae8..132aaa4 100644
--- a/dts/upstream/Bindings/gpu/samsung-g2d.yaml
+++ b/dts/upstream/Bindings/gpu/samsung-g2d.yaml
@@ -22,36 +22,20 @@
interrupts:
maxItems: 1
- clocks: {}
- clock-names: {}
- iommus: {}
- power-domains: {}
+ clocks:
+ minItems: 1
+ maxItems: 2
-if:
- properties:
- compatible:
- contains:
- const: samsung,exynos5250-g2d
+ clock-names:
+ minItems: 1
+ maxItems: 2
-then:
- properties:
- clocks:
- items:
- - description: fimg2d clock
- clock-names:
- items:
- - const: fimg2d
+ iommus:
+ minItems: 1
+ maxItems: 2
-else:
- properties:
- clocks:
- items:
- - description: sclk_fimg2d clock
- - description: fimg2d clock
- clock-names:
- items:
- - const: sclk_fimg2d
- - const: fimg2d
+ power-domains:
+ maxItems: 1
required:
- compatible
@@ -60,6 +44,33 @@
- clocks
- clock-names
+allOf:
+ - if:
+ properties:
+ compatible:
+ contains:
+ const: samsung,exynos5250-g2d
+
+ then:
+ properties:
+ clocks:
+ items:
+ - description: fimg2d clock
+ clock-names:
+ items:
+ - const: fimg2d
+
+ else:
+ properties:
+ clocks:
+ items:
+ - description: sclk_fimg2d clock
+ - description: fimg2d clock
+ clock-names:
+ items:
+ - const: sclk_fimg2d
+ - const: fimg2d
+
additionalProperties: false
examples:
diff --git a/dts/upstream/Bindings/gpu/samsung-rotator.yaml b/dts/upstream/Bindings/gpu/samsung-rotator.yaml
index d60626ff..18bf44e 100644
--- a/dts/upstream/Bindings/gpu/samsung-rotator.yaml
+++ b/dts/upstream/Bindings/gpu/samsung-rotator.yaml
@@ -12,10 +12,11 @@
properties:
compatible:
enum:
- - "samsung,s5pv210-rotator"
- - "samsung,exynos4210-rotator"
- - "samsung,exynos4212-rotator"
- - "samsung,exynos5250-rotator"
+ - samsung,s5pv210-rotator
+ - samsung,exynos4210-rotator
+ - samsung,exynos4212-rotator
+ - samsung,exynos5250-rotator
+
reg:
maxItems: 1
diff --git a/dts/upstream/Bindings/gpu/samsung-scaler.yaml b/dts/upstream/Bindings/gpu/samsung-scaler.yaml
index 5317ac6..9fb530e 100644
--- a/dts/upstream/Bindings/gpu/samsung-scaler.yaml
+++ b/dts/upstream/Bindings/gpu/samsung-scaler.yaml
@@ -21,40 +21,20 @@
interrupts:
maxItems: 1
- clocks: {}
- clock-names: {}
- iommus: {}
- power-domains: {}
+ clocks:
+ minItems: 1
+ maxItems: 3
-if:
- properties:
- compatible:
- contains:
- const: samsung,exynos5420-scaler
+ clock-names:
+ minItems: 1
+ maxItems: 3
-then:
- properties:
- clocks:
- items:
- - description: mscl clock
+ iommus:
+ minItems: 1
+ maxItems: 2
- clock-names:
- items:
- - const: mscl
-
-else:
- properties:
- clocks:
- items:
- - description: pclk clock
- - description: aclk clock
- - description: aclk_xiu clock
-
- clock-names:
- items:
- - const: pclk
- - const: aclk
- - const: aclk_xiu
+ power-domains:
+ maxItems: 1
required:
- compatible
@@ -63,6 +43,39 @@
- clocks
- clock-names
+allOf:
+ - if:
+ properties:
+ compatible:
+ contains:
+ const: samsung,exynos5420-scaler
+
+ then:
+ properties:
+ clocks:
+ items:
+ - description: mscl clock
+ clock-names:
+ items:
+ - const: mscl
+ iommus:
+ minItems: 2
+
+ else:
+ properties:
+ clocks:
+ items:
+ - description: pclk clock
+ - description: aclk clock
+ - description: aclk_xiu clock
+ clock-names:
+ items:
+ - const: pclk
+ - const: aclk
+ - const: aclk_xiu
+ iommus:
+ maxItems: 1
+
additionalProperties: false
examples:
diff --git a/dts/upstream/Bindings/hwinfo/samsung,exynos-chipid.yaml b/dts/upstream/Bindings/hwinfo/samsung,exynos-chipid.yaml
index 95cbdcb..780ccb5 100644
--- a/dts/upstream/Bindings/hwinfo/samsung,exynos-chipid.yaml
+++ b/dts/upstream/Bindings/hwinfo/samsung,exynos-chipid.yaml
@@ -11,9 +11,21 @@
properties:
compatible:
- enum:
- - samsung,exynos4210-chipid
- - samsung,exynos850-chipid
+ oneOf:
+ - enum:
+ - samsung,exynos4210-chipid
+ - samsung,exynos850-chipid
+ - items:
+ - enum:
+ - samsung,exynos5433-chipid
+ - samsung,exynos7-chipid
+ - const: samsung,exynos4210-chipid
+ - items:
+ - enum:
+ - samsung,exynos7885-chipid
+ - samsung,exynosautov9-chipid
+ - samsung,exynosautov920-chipid
+ - const: samsung,exynos850-chipid
reg:
maxItems: 1
diff --git a/dts/upstream/Bindings/hwmon/gpio-fan.txt b/dts/upstream/Bindings/hwmon/gpio-fan.txt
deleted file mode 100644
index f4cfa35..0000000
--- a/dts/upstream/Bindings/hwmon/gpio-fan.txt
+++ /dev/null
@@ -1,41 +0,0 @@
-Bindings for fan connected to GPIO lines
-
-Required properties:
-- compatible : "gpio-fan"
-
-Optional properties:
-- gpios: Specifies the pins that map to bits in the control value,
- ordered MSB-->LSB.
-- gpio-fan,speed-map: A mapping of possible fan RPM speeds and the
- control value that should be set to achieve them. This array
- must have the RPM values in ascending order.
-- alarm-gpios: This pin going active indicates something is wrong with
- the fan, and a udev event will be fired.
-- #cooling-cells: If used as a cooling device, must be <2>
- Also see:
- Documentation/devicetree/bindings/thermal/thermal-cooling-devices.yaml
- min and max states are derived from the speed-map of the fan.
-
-Note: At least one the "gpios" or "alarm-gpios" properties must be set.
-
-Examples:
-
- gpio_fan {
- compatible = "gpio-fan";
- gpios = <&gpio1 14 1
- &gpio1 13 1>;
- gpio-fan,speed-map = <0 0
- 3000 1
- 6000 2>;
- alarm-gpios = <&gpio1 15 1>;
- };
- gpio_fan_cool: gpio_fan {
- compatible = "gpio-fan";
- gpios = <&gpio2 14 1
- &gpio2 13 1>;
- gpio-fan,speed-map = <0 0>,
- <3000 1>,
- <6000 2>;
- alarm-gpios = <&gpio2 15 1>;
- #cooling-cells = <2>; /* min followed by max */
- };
diff --git a/dts/upstream/Bindings/hwmon/gpio-fan.yaml b/dts/upstream/Bindings/hwmon/gpio-fan.yaml
new file mode 100644
index 0000000..7f30cfc
--- /dev/null
+++ b/dts/upstream/Bindings/hwmon/gpio-fan.yaml
@@ -0,0 +1,60 @@
+# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/hwmon/gpio-fan.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Fan connected to GPIO lines
+
+maintainers:
+ - Rob Herring <robh@kernel.org>
+
+properties:
+ compatible:
+ const: gpio-fan
+
+ gpios:
+ description: |
+ Specifies the pins that map to bits in the control value,
+ ordered MSB-->LSB.
+ minItems: 1
+ maxItems: 7
+
+ alarm-gpios:
+ maxItems: 1
+
+ gpio-fan,speed-map:
+ $ref: /schemas/types.yaml#/definitions/uint32-matrix
+ minItems: 2
+ maxItems: 127
+ items:
+ items:
+ - description: fan speed in RPMs
+ - description: control value
+ description: |
+ A mapping of possible fan RPM speeds and the
+ control value that should be set to achieve them. This array
+ must have the RPM values in ascending order.
+
+ '#cooling-cells':
+ const: 2
+
+required:
+ - compatible
+ - gpios
+ - gpio-fan,speed-map
+
+additionalProperties: false
+
+examples:
+ - |
+ gpio-fan {
+ compatible = "gpio-fan";
+ gpios = <&gpio2 14 1
+ &gpio2 13 1>;
+ gpio-fan,speed-map = < 0 0>,
+ <3000 1>,
+ <6000 2>;
+ alarm-gpios = <&gpio2 15 1>;
+ #cooling-cells = <2>; /* min followed by max */
+ };
diff --git a/dts/upstream/Bindings/hwmon/iio-hwmon.yaml b/dts/upstream/Bindings/hwmon/iio-hwmon.yaml
index e5b2478..be5c7d4 100644
--- a/dts/upstream/Bindings/hwmon/iio-hwmon.yaml
+++ b/dts/upstream/Bindings/hwmon/iio-hwmon.yaml
@@ -19,7 +19,7 @@
io-channels:
minItems: 1
- maxItems: 8 # Should be enough
+ maxItems: 51 # Should be enough
description: >
List of phandles to ADC channels to read the monitoring values
diff --git a/dts/upstream/Bindings/hwmon/lltc,ltc4286.yaml b/dts/upstream/Bindings/hwmon/lltc,ltc4286.yaml
new file mode 100644
index 0000000..98ca163
--- /dev/null
+++ b/dts/upstream/Bindings/hwmon/lltc,ltc4286.yaml
@@ -0,0 +1,50 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/hwmon/lltc,ltc4286.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: LTC4286 power monitors
+
+maintainers:
+ - Delphine CC Chiu <Delphine_CC_Chiu@Wiwynn.com>
+
+properties:
+ compatible:
+ enum:
+ - lltc,ltc4286
+ - lltc,ltc4287
+
+ reg:
+ maxItems: 1
+
+ adi,vrange-low-enable:
+ description:
+ This property is a bool parameter to represent the
+ voltage range is 25.6 volts or 102.4 volts for this chip.
+ The default is 102.4 volts.
+ type: boolean
+
+ shunt-resistor-micro-ohms:
+ description:
+ Resistor value micro-ohms.
+
+required:
+ - compatible
+ - reg
+
+additionalProperties: false
+
+examples:
+ - |
+ i2c {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ power-monitor@40 {
+ compatible = "lltc,ltc4286";
+ reg = <0x40>;
+ adi,vrange-low-enable;
+ shunt-resistor-micro-ohms = <300>;
+ };
+ };
diff --git a/dts/upstream/Bindings/hwmon/lm75.yaml b/dts/upstream/Bindings/hwmon/lm75.yaml
index 0b69897..ed269e4 100644
--- a/dts/upstream/Bindings/hwmon/lm75.yaml
+++ b/dts/upstream/Bindings/hwmon/lm75.yaml
@@ -14,6 +14,7 @@
compatible:
enum:
- adi,adt75
+ - ams,as6200
- atmel,at30ts74
- dallas,ds1775
- dallas,ds75
@@ -48,10 +49,28 @@
vs-supply:
description: phandle to the regulator that provides the +VS supply
+ interrupts:
+ maxItems: 1
+
required:
- compatible
- reg
+allOf:
+ - if:
+ not:
+ properties:
+ compatible:
+ contains:
+ enum:
+ - ams,as6200
+ - ti,tmp100
+ - ti,tmp101
+ - ti,tmp112
+ then:
+ properties:
+ interrupts: false
+
additionalProperties: false
examples:
@@ -64,5 +83,19 @@
compatible = "st,stlm75";
reg = <0x48>;
vs-supply = <&vs>;
+ };
+ };
+ - |
+ #include <dt-bindings/interrupt-controller/irq.h>
+ i2c {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ temperature-sensor@48 {
+ compatible = "ams,as6200";
+ reg = <0x48>;
+ vs-supply = <&vs>;
+ interrupt-parent = <&gpio1>;
+ interrupts = <17 IRQ_TYPE_EDGE_BOTH>;
};
};
diff --git a/dts/upstream/Bindings/i2c/i2c-exynos5.yaml b/dts/upstream/Bindings/i2c/i2c-exynos5.yaml
index 3e52a0d..df9c57b 100644
--- a/dts/upstream/Bindings/i2c/i2c-exynos5.yaml
+++ b/dts/upstream/Bindings/i2c/i2c-exynos5.yaml
@@ -25,7 +25,16 @@
- samsung,exynos5250-hsi2c # Exynos5250 and Exynos5420
- samsung,exynos5260-hsi2c # Exynos5260
- samsung,exynos7-hsi2c # Exynos7
- - samsung,exynosautov9-hsi2c # ExynosAutoV9 and Exynos850
+ - samsung,exynosautov9-hsi2c
+ - items:
+ - enum:
+ - samsung,exynos5433-hsi2c
+ - tesla,fsd-hsi2c
+ - const: samsung,exynos7-hsi2c
+ - items:
+ - enum:
+ - samsung,exynos850-hsi2c
+ - const: samsung,exynosautov9-hsi2c
- const: samsung,exynos5-hsi2c # Exynos5250 and Exynos5420
deprecated: true
diff --git a/dts/upstream/Bindings/i2c/samsung,s3c2410-i2c.yaml b/dts/upstream/Bindings/i2c/samsung,s3c2410-i2c.yaml
index b204e35..1303502 100644
--- a/dts/upstream/Bindings/i2c/samsung,s3c2410-i2c.yaml
+++ b/dts/upstream/Bindings/i2c/samsung,s3c2410-i2c.yaml
@@ -11,14 +11,20 @@
properties:
compatible:
- enum:
- - samsung,s3c2410-i2c
- - samsung,s3c2440-i2c
- # For s3c2440-like I2C used inside HDMIPHY block found on several SoCs:
- - samsung,s3c2440-hdmiphy-i2c
- # For s3c2440-like I2C used as a host to SATA PHY controller on an
- # internal bus:
- - samsung,exynos5-sata-phy-i2c
+ oneOf:
+ - enum:
+ - samsung,s3c2410-i2c
+ - samsung,s3c2440-i2c
+ # For s3c2440-like I2C used inside HDMIPHY block found on several SoCs:
+ - samsung,s3c2440-hdmiphy-i2c
+ # For s3c2440-like I2C used as a host to SATA PHY controller on an
+ # internal bus:
+ - samsung,exynos5-sata-phy-i2c
+ - items:
+ - enum:
+ - samsung,exynos7885-i2c
+ - samsung,exynos850-i2c
+ - const: samsung,s3c2440-i2c
'#address-cells':
const: 1
diff --git a/dts/upstream/Bindings/i2c/st,stm32-i2c.yaml b/dts/upstream/Bindings/i2c/st,stm32-i2c.yaml
index 94b75d9..1b31b87 100644
--- a/dts/upstream/Bindings/i2c/st,stm32-i2c.yaml
+++ b/dts/upstream/Bindings/i2c/st,stm32-i2c.yaml
@@ -19,6 +19,7 @@
- st,stm32f7-i2c
- st,stm32mp13-i2c
- st,stm32mp15-i2c
+ - st,stm32mp25-i2c
then:
properties:
i2c-scl-rising-time-ns:
@@ -41,6 +42,30 @@
clock-frequency:
enum: [100000, 400000]
+ - if:
+ properties:
+ compatible:
+ contains:
+ enum:
+ - st,stm32f4-i2c
+ - st,stm32f7-i2c
+ - st,stm32mp13-i2c
+ - st,stm32mp15-i2c
+ then:
+ properties:
+ interrupts:
+ minItems: 2
+
+ interrupt-names:
+ minItems: 2
+ else:
+ properties:
+ interrupts:
+ maxItems: 1
+
+ interrupt-names:
+ maxItems: 1
+
properties:
compatible:
enum:
@@ -48,6 +73,7 @@
- st,stm32f7-i2c
- st,stm32mp13-i2c
- st,stm32mp15-i2c
+ - st,stm32mp25-i2c
reg:
maxItems: 1
@@ -56,11 +82,13 @@
items:
- description: interrupt ID for I2C event
- description: interrupt ID for I2C error
+ minItems: 1
interrupt-names:
items:
- const: event
- const: error
+ minItems: 1
resets:
maxItems: 1
diff --git a/dts/upstream/Bindings/iio/adc/adi,ad7091r5.yaml b/dts/upstream/Bindings/iio/adc/adi,ad7091r5.yaml
index ce7ba63..ddec974 100644
--- a/dts/upstream/Bindings/iio/adc/adi,ad7091r5.yaml
+++ b/dts/upstream/Bindings/iio/adc/adi,ad7091r5.yaml
@@ -4,36 +4,92 @@
$id: http://devicetree.org/schemas/iio/adc/adi,ad7091r5.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
-title: Analog Devices AD7091R5 4-Channel 12-Bit ADC
+title: Analog Devices AD7091R-2/-4/-5/-8 Multi-Channel 12-Bit ADCs
maintainers:
- Michael Hennerich <michael.hennerich@analog.com>
+ - Marcelo Schmitt <marcelo.schmitt@analog.com>
description: |
- Analog Devices AD7091R5 4-Channel 12-Bit ADC
+ Analog Devices AD7091R5 4-Channel 12-Bit ADC supporting I2C interface
https://www.analog.com/media/en/technical-documentation/data-sheets/ad7091r-5.pdf
+ Analog Devices AD7091R-2/AD7091R-4/AD7091R-8 2-/4-/8-Channel 12-Bit ADCs
+ supporting SPI interface
+ https://www.analog.com/media/en/technical-documentation/data-sheets/AD7091R-2_7091R-4_7091R-8.pdf
properties:
compatible:
enum:
+ - adi,ad7091r2
+ - adi,ad7091r4
- adi,ad7091r5
+ - adi,ad7091r8
reg:
maxItems: 1
+ vdd-supply:
+ description:
+ Provide VDD power to the sensor (VDD range is from 2.7V to 5.25V).
+
+ vdrive-supply:
+ description:
+ Determines the voltage level at which the interface logic will operate.
+ The V_drive voltage range is from 1.8V to 5.25V and must not exceed VDD by
+ more than 0.3V.
+
vref-supply:
description:
Phandle to the vref power supply
- interrupts:
+ convst-gpios:
+ description:
+ GPIO connected to the CONVST pin.
+ This logic input is used to initiate conversions on the analog
+ input channels.
+ maxItems: 1
+
+ reset-gpios:
maxItems: 1
+ interrupts:
+ description:
+ Interrupt for signaling when conversion results exceed the high limit for
+ ADC readings or fall below the low limit for them. Interrupt source must
+ be attached to ALERT/BUSY/GPO0 pin.
+ maxItems: 1
required:
- compatible
- reg
+allOf:
+ - $ref: /schemas/spi/spi-peripheral-props.yaml#
+
-additionalProperties: false
+ # AD7091R-2 does not have ALERT/BUSY/GPO pin
+ - if:
+ properties:
+ compatible:
+ contains:
+ enum:
+ - adi,ad7091r2
+ then:
+ properties:
+ interrupts: false
+
+ - if:
+ properties:
+ compatible:
+ contains:
+ enum:
+ - adi,ad7091r2
+ - adi,ad7091r4
+ - adi,ad7091r8
+ then:
+ required:
+ - convst-gpios
+
+unevaluatedProperties: false
examples:
- |
@@ -51,4 +107,22 @@
interrupt-parent = <&gpio>;
};
};
+ - |
+ #include <dt-bindings/gpio/gpio.h>
+ #include <dt-bindings/interrupt-controller/irq.h>
+ spi {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ adc@0 {
+ compatible = "adi,ad7091r8";
+ reg = <0x0>;
+ spi-max-frequency = <1000000>;
+ vref-supply = <&adc_vref>;
+ convst-gpios = <&gpio 25 GPIO_ACTIVE_LOW>;
+ reset-gpios = <&gpio 27 GPIO_ACTIVE_LOW>;
+ interrupts = <22 IRQ_TYPE_EDGE_FALLING>;
+ interrupt-parent = <&gpio>;
+ };
+ };
...
diff --git a/dts/upstream/Bindings/iio/adc/adi,ad7780.yaml b/dts/upstream/Bindings/iio/adc/adi,ad7780.yaml
index 5fcc8dd..be2616f 100644
--- a/dts/upstream/Bindings/iio/adc/adi,ad7780.yaml
+++ b/dts/upstream/Bindings/iio/adc/adi,ad7780.yaml
@@ -80,9 +80,9 @@
compatible = "adi,ad7780";
reg = <0>;
- avdd-supply = <&vdd_supply>;
- powerdown-gpios = <&gpio0 12 GPIO_ACTIVE_HIGH>;
- adi,gain-gpios = <&gpio1 5 GPIO_ACTIVE_LOW>;
+ avdd-supply = <&vdd_supply>;
+ powerdown-gpios = <&gpio0 12 GPIO_ACTIVE_HIGH>;
+ adi,gain-gpios = <&gpio1 5 GPIO_ACTIVE_LOW>;
adi,filter-gpios = <&gpio2 15 GPIO_ACTIVE_LOW>;
};
};
diff --git a/dts/upstream/Bindings/iio/adc/maxim,max34408.yaml b/dts/upstream/Bindings/iio/adc/maxim,max34408.yaml
new file mode 100644
index 0000000..4cba856
--- /dev/null
+++ b/dts/upstream/Bindings/iio/adc/maxim,max34408.yaml
@@ -0,0 +1,139 @@
+# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/iio/adc/maxim,max34408.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Maxim MAX34408/MAX34409 current monitors with overcurrent control
+
+maintainers:
+ - Ivan Mikhaylov <fr0st61te@gmail.com>
+
+description: |
+ The MAX34408/MAX34409 are two- and four-channel current monitors that are
+ configured and monitored with a standard I2C/SMBus serial interface. Each
+ unidirectional current sensor offers precision high-side operation with a
+ low full-scale sense voltage. The devices automatically sequence through
+ two or four channels and collect the current-sense samples and average them
+ to reduce the effect of impulse noise. The raw ADC samples are compared to
+ user-programmable digital thresholds to indicate overcurrent conditions.
+ Overcurrent conditions trigger a hardware output to provide an immediate
+ indication to shut down any necessary external circuitry.
+
+ Specifications about the devices can be found at:
+ https://www.analog.com/media/en/technical-documentation/data-sheets/MAX34408-MAX34409.pdf
+
+properties:
+ compatible:
+ enum:
+ - maxim,max34408
+ - maxim,max34409
+
+ "#address-cells":
+ const: 1
+
+ "#size-cells":
+ const: 0
+
+ reg:
+ maxItems: 1
+
+ interrupts:
+ maxItems: 1
+
+ powerdown-gpios:
+ description:
+ Shutdown Output. Open-drain output. This output transitions to high impedance
+ when any of the digital comparator thresholds are exceeded as long as the ENA
+ pin is high.
+ maxItems: 1
+
+ powerdown-status-gpios:
+ description:
+ SHTDN Enable Input. CMOS digital input. Connect to GND to clear the latch and
+ unconditionally deassert (force low) the SHTDN output and reset the shutdown
+ delay. Connect to VDD to enable normal latch operation of the SHTDN output.
+ maxItems: 1
+
+ vdd-supply: true
+
+patternProperties:
+ "^channel@[0-3]$":
+ $ref: adc.yaml
+ type: object
+ description:
+ Represents the internal channels of the ADC.
+
+ properties:
+ reg:
+ items:
+ - minimum: 0
+ maximum: 3
+
+ maxim,rsense-val-micro-ohms:
+ description:
+ Adjust the Rsense value to monitor higher or lower current levels for
+ input.
+ enum: [250, 500, 1000, 5000, 10000, 50000, 100000, 200000, 500000]
+ default: 1000
+
+ required:
+ - reg
+ - maxim,rsense-val-micro-ohms
+
+ unevaluatedProperties: false
+
+required:
+ - compatible
+ - reg
+
+allOf:
+ - if:
+ properties:
+ compatible:
+ contains:
+ const: maxim,max34408
+ then:
+ patternProperties:
+ "^channel@[2-3]$": false
+ "^channel@[0-1]$":
+ properties:
+ reg:
+ maximum: 1
+ else:
+ patternProperties:
+ "^channel@[0-3]$":
+ properties:
+ reg:
+ maximum: 3
+
+additionalProperties: false
+
+examples:
+ - |
+ #include <dt-bindings/gpio/gpio.h>
+
+ i2c {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ adc@1e {
+ compatible = "maxim,max34409";
+ reg = <0x1e>;
+ powerdown-gpios = <&gpio0 1 GPIO_ACTIVE_LOW>;
+ powerdown-status-gpios = <&gpio0 2 GPIO_ACTIVE_HIGH>;
+
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ channel@0 {
+ reg = <0x0>;
+ maxim,rsense-val-micro-ohms = <5000>;
+ };
+
+ channel@1 {
+ reg = <0x1>;
+ maxim,rsense-val-micro-ohms = <10000>;
+ };
+ };
+ };
diff --git a/dts/upstream/Bindings/iio/adc/qcom,spmi-iadc.yaml b/dts/upstream/Bindings/iio/adc/qcom,spmi-iadc.yaml
index 73def67..5ed893e 100644
--- a/dts/upstream/Bindings/iio/adc/qcom,spmi-iadc.yaml
+++ b/dts/upstream/Bindings/iio/adc/qcom,spmi-iadc.yaml
@@ -25,7 +25,7 @@
- const: qcom,spmi-iadc
reg:
- description: IADC base address and length in the SPMI PMIC register map
+ description: IADC base address in the SPMI PMIC register map
maxItems: 1
qcom,external-resistor-micro-ohms:
@@ -50,15 +50,17 @@
examples:
- |
#include <dt-bindings/interrupt-controller/irq.h>
- spmi {
+
+ pmic {
#address-cells = <1>;
#size-cells = <0>;
- pmic_iadc: adc@3600 {
+
+ adc@3600 {
compatible = "qcom,pm8941-iadc", "qcom,spmi-iadc";
reg = <0x3600>;
interrupts = <0x0 0x36 0x0 IRQ_TYPE_EDGE_RISING>;
qcom,external-resistor-micro-ohms = <10000>;
- #io-channel-cells = <1>;
+ #io-channel-cells = <1>;
};
};
...
diff --git a/dts/upstream/Bindings/iio/adc/qcom,spmi-rradc.yaml b/dts/upstream/Bindings/iio/adc/qcom,spmi-rradc.yaml
index b3a6263..f39bc92 100644
--- a/dts/upstream/Bindings/iio/adc/qcom,spmi-rradc.yaml
+++ b/dts/upstream/Bindings/iio/adc/qcom,spmi-rradc.yaml
@@ -43,9 +43,9 @@
#address-cells = <1>;
#size-cells = <0>;
- pmic_rradc: adc@4500 {
+ adc@4500 {
compatible = "qcom,pmi8998-rradc";
reg = <0x4500>;
- #io-channel-cells = <1>;
+ #io-channel-cells = <1>;
};
};
diff --git a/dts/upstream/Bindings/iio/adc/qcom,spmi-vadc.yaml b/dts/upstream/Bindings/iio/adc/qcom,spmi-vadc.yaml
index ad7d6fc..40fa071 100644
--- a/dts/upstream/Bindings/iio/adc/qcom,spmi-vadc.yaml
+++ b/dts/upstream/Bindings/iio/adc/qcom,spmi-vadc.yaml
@@ -236,11 +236,11 @@
examples:
- |
- spmi {
+ pmic {
#address-cells = <1>;
#size-cells = <0>;
- /* VADC node */
- pmic_vadc: adc@3100 {
+
+ adc@3100 {
compatible = "qcom,spmi-vadc";
reg = <0x3100>;
interrupts = <0x0 0x31 0x0 0x1>;
@@ -281,9 +281,10 @@
#include <dt-bindings/iio/qcom,spmi-adc7-pm8350.h>
#include <dt-bindings/interrupt-controller/irq.h>
- spmi {
+ pmic {
#address-cells = <1>;
#size-cells = <0>;
+
adc@3100 {
reg = <0x3100>;
compatible = "qcom,spmi-adc7";
diff --git a/dts/upstream/Bindings/iio/adc/samsung,exynos-adc.yaml b/dts/upstream/Bindings/iio/adc/samsung,exynos-adc.yaml
index 582d0a0..4e40f6b 100644
--- a/dts/upstream/Bindings/iio/adc/samsung,exynos-adc.yaml
+++ b/dts/upstream/Bindings/iio/adc/samsung,exynos-adc.yaml
@@ -11,18 +11,23 @@
properties:
compatible:
- enum:
- - samsung,exynos-adc-v1 # Exynos5250
- - samsung,exynos-adc-v2
- - samsung,exynos3250-adc
- - samsung,exynos4212-adc # Exynos4212 and Exynos4412
- - samsung,exynos7-adc
- - samsung,s3c2410-adc
- - samsung,s3c2416-adc
- - samsung,s3c2440-adc
- - samsung,s3c2443-adc
- - samsung,s3c6410-adc
- - samsung,s5pv210-adc
+ oneOf:
+ - enum:
+ - samsung,exynos-adc-v1 # Exynos5250
+ - samsung,exynos-adc-v2
+ - samsung,exynos3250-adc
+ - samsung,exynos4212-adc # Exynos4212 and Exynos4412
+ - samsung,exynos7-adc
+ - samsung,s3c2410-adc
+ - samsung,s3c2416-adc
+ - samsung,s3c2440-adc
+ - samsung,s3c2443-adc
+ - samsung,s3c6410-adc
+ - samsung,s5pv210-adc
+ - items:
+ - enum:
+ - samsung,exynos5433-adc
+ - const: samsung,exynos7-adc
reg:
maxItems: 1
diff --git a/dts/upstream/Bindings/iio/adc/ti,palmas-gpadc.yaml b/dts/upstream/Bindings/iio/adc/ti,palmas-gpadc.yaml
index 720c16a..f94057d 100644
--- a/dts/upstream/Bindings/iio/adc/ti,palmas-gpadc.yaml
+++ b/dts/upstream/Bindings/iio/adc/ti,palmas-gpadc.yaml
@@ -67,19 +67,4 @@
- compatible
- "#io-channel-cells"
-examples:
- - |
- #include <dt-bindings/clock/mt8183-clk.h>
- pmic {
- compatible = "ti,twl6035-pmic", "ti,palmas-pmic";
- adc {
- compatible = "ti,palmas-gpadc";
- interrupts = <18 0>,
- <16 0>,
- <17 0>;
- #io-channel-cells = <1>;
- ti,channel0-current-microamp = <5>;
- ti,channel3-current-microamp = <10>;
- };
- };
...
diff --git a/dts/upstream/Bindings/iio/amplifiers/adi,hmc425a.yaml b/dts/upstream/Bindings/iio/amplifiers/adi,hmc425a.yaml
index 2ee6080..67de9d4 100644
--- a/dts/upstream/Bindings/iio/amplifiers/adi,hmc425a.yaml
+++ b/dts/upstream/Bindings/iio/amplifiers/adi,hmc425a.yaml
@@ -12,6 +12,9 @@
description: |
Digital Step Attenuator IIO devices with gpio interface.
Offer various frequency and attenuation ranges.
+ ADRF5750 2 dB LSB, 4-Bit, Silicon Digital Attenuator, 10 MHz to 60 GHz
+ https://www.analog.com/media/en/technical-documentation/data-sheets/adrf5740.pdf
+
HMC425A 0.5 dB LSB GaAs MMIC 6-BIT DIGITAL POSITIVE CONTROL ATTENUATOR, 2.2 - 8.0 GHz
https://www.analog.com/media/en/technical-documentation/data-sheets/hmc425A.pdf
@@ -22,6 +25,7 @@
properties:
compatible:
enum:
+ - adi,adrf5740
- adi,hmc425a
- adi,hmc540s
diff --git a/dts/upstream/Bindings/iio/chemical/aosong,ags02ma.yaml b/dts/upstream/Bindings/iio/chemical/aosong,ags02ma.yaml
new file mode 100644
index 0000000..35e7b09
--- /dev/null
+++ b/dts/upstream/Bindings/iio/chemical/aosong,ags02ma.yaml
@@ -0,0 +1,47 @@
+# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/iio/chemical/aosong,ags02ma.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Aosong AGS02MA VOC Sensor
+
+description: |
+ AGS02MA is an TVOC (Total Volatile Organic Compounds) i2c sensor with default
+ address of 0x1a.
+
+ Datasheet:
+ https://asairsensors.com/wp-content/uploads/2021/09/AGS02MA.pdf
+
+maintainers:
+ - Anshul Dalal <anshulusr@gmail.com>
+
+properties:
+ compatible:
+ enum:
+ - aosong,ags02ma
+
+ reg:
+ maxItems: 1
+
+ vdd-supply: true
+
+required:
+ - compatible
+ - reg
+ - vdd-supply
+
+additionalProperties: false
+
+examples:
+ - |
+ i2c {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ voc-sensor@1a {
+ compatible = "aosong,ags02ma";
+ reg = <0x1a>;
+ vdd-supply = <&vdd_regulator>;
+ };
+ };
diff --git a/dts/upstream/Bindings/iio/dac/adi,ad5791.yaml b/dts/upstream/Bindings/iio/dac/adi,ad5791.yaml
index 3a84739..c81285d 100644
--- a/dts/upstream/Bindings/iio/dac/adi,ad5791.yaml
+++ b/dts/upstream/Bindings/iio/dac/adi,ad5791.yaml
@@ -26,6 +26,11 @@
vdd-supply: true
vss-supply: true
+ adi,rbuf-gain2-en:
+ description: Specify to allow an external amplifier to be connected in a
+ gain of two configuration.
+ type: boolean
+
required:
- compatible
- reg
diff --git a/dts/upstream/Bindings/iio/dac/microchip,mcp4821.yaml b/dts/upstream/Bindings/iio/dac/microchip,mcp4821.yaml
new file mode 100644
index 0000000..0dc577c
--- /dev/null
+++ b/dts/upstream/Bindings/iio/dac/microchip,mcp4821.yaml
@@ -0,0 +1,86 @@
+# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/iio/dac/microchip,mcp4821.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Microchip MCP4821 and similar DACs
+
+description: |
+ Supports MCP48x1 (single channel) and MCP48x2 (dual channel) series of DACs.
+ Device supports simplex communication over SPI in Mode 0 and Mode 3.
+
+ +---------+--------------+-------------+
+ | Device | Resolution | Channels |
+ |---------|--------------|-------------|
+ | MCP4801 | 8-bit | 1 |
+ | MCP4802 | 8-bit | 2 |
+ | MCP4811 | 10-bit | 1 |
+ | MCP4812 | 10-bit | 2 |
+ | MCP4821 | 12-bit | 1 |
+ | MCP4822 | 12-bit | 2 |
+ +---------+--------------+-------------+
+
+ Datasheet:
+ MCP48x1: https://ww1.microchip.com/downloads/en/DeviceDoc/22244B.pdf
+ MCP48x2: https://ww1.microchip.com/downloads/en/DeviceDoc/20002249B.pdf
+
+maintainers:
+ - Anshul Dalal <anshulusr@gmail.com>
+
+allOf:
+ - $ref: /schemas/spi/spi-peripheral-props.yaml#
+
+properties:
+ compatible:
+ enum:
+ - microchip,mcp4801
+ - microchip,mcp4802
+ - microchip,mcp4811
+ - microchip,mcp4812
+ - microchip,mcp4821
+ - microchip,mcp4822
+
+ reg:
+ maxItems: 1
+
+ vdd-supply: true
+
+ ldac-gpios:
+ description: |
+ Active Low LDAC (Latch DAC Input) pin used to update the DAC output.
+ maxItems: 1
+
+ powerdown-gpios:
+ description: |
+ Active Low SHDN pin used to enter the shutdown mode.
+ maxItems: 1
+
+ spi-cpha: true
+ spi-cpol: true
+
+required:
+ - compatible
+ - reg
+ - vdd-supply
+
+additionalProperties: false
+
+examples:
+ - |
+ #include <dt-bindings/gpio/gpio.h>
+
+ spi {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ dac@0 {
+ compatible = "microchip,mcp4821";
+ reg = <0>;
+ vdd-supply = <&vdd_regulator>;
+ ldac-gpios = <&gpio0 1 GPIO_ACTIVE_HIGH>;
+ powerdown-gpios = <&gpio0 2 GPIO_ACTIVE_HIGH>;
+ spi-cpha;
+ spi-cpol;
+ };
+ };
diff --git a/dts/upstream/Bindings/iio/humidity/ti,hdc3020.yaml b/dts/upstream/Bindings/iio/humidity/ti,hdc3020.yaml
new file mode 100644
index 0000000..7f6d0f9
--- /dev/null
+++ b/dts/upstream/Bindings/iio/humidity/ti,hdc3020.yaml
@@ -0,0 +1,55 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/iio/humidity/ti,hdc3020.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: HDC3020/HDC3021/HDC3022 humidity and temperature iio sensors
+
+maintainers:
+ - Li peiyu <579lpy@gmail.com>
+ - Javier Carrasco <javier.carrasco.cruz@gmail.com>
+
+description:
+ https://www.ti.com/lit/ds/symlink/hdc3020.pdf
+
+ The HDC302x is an integrated capacitive based relative humidity (RH)
+ and temperature sensor.
+
+properties:
+ compatible:
+ oneOf:
+ - items:
+ - enum:
+ - ti,hdc3021
+ - ti,hdc3022
+ - const: ti,hdc3020
+ - const: ti,hdc3020
+
+ interrupts:
+ maxItems: 1
+
+ vdd-supply: true
+
+ reg:
+ maxItems: 1
+
+required:
+ - compatible
+ - reg
+ - vdd-supply
+
+additionalProperties: false
+
+examples:
+ - |
+ i2c {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ humidity-sensor@47 {
+ compatible = "ti,hdc3021", "ti,hdc3020";
+ reg = <0x47>;
+ vdd-supply = <&vcc_3v3>;
+ };
+ };
diff --git a/dts/upstream/Bindings/iio/imu/adi,adis16460.yaml b/dts/upstream/Bindings/iio/imu/adi,adis16460.yaml
index 4e43c80..4cacc99 100644
--- a/dts/upstream/Bindings/iio/imu/adi,adis16460.yaml
+++ b/dts/upstream/Bindings/iio/imu/adi,adis16460.yaml
@@ -25,6 +25,10 @@
spi-cpol: true
+ spi-cs-inactive-delay-ns:
+ minimum: 16000
+ default: 16000
+
interrupts:
maxItems: 1
diff --git a/dts/upstream/Bindings/iio/imu/adi,adis16475.yaml b/dts/upstream/Bindings/iio/imu/adi,adis16475.yaml
index c73533c..9b7ad60 100644
--- a/dts/upstream/Bindings/iio/imu/adi,adis16475.yaml
+++ b/dts/upstream/Bindings/iio/imu/adi,adis16475.yaml
@@ -47,6 +47,10 @@
spi-max-frequency:
maximum: 2000000
+ spi-cs-inactive-delay-ns:
+ minimum: 16000
+ default: 16000
+
interrupts:
maxItems: 1
diff --git a/dts/upstream/Bindings/iio/imu/bosch,bmi323.yaml b/dts/upstream/Bindings/iio/imu/bosch,bmi323.yaml
new file mode 100644
index 0000000..64ef26e
--- /dev/null
+++ b/dts/upstream/Bindings/iio/imu/bosch,bmi323.yaml
@@ -0,0 +1,77 @@
+# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/iio/imu/bosch,bmi323.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Bosch BMI323 6-Axis IMU
+
+maintainers:
+ - Jagath Jog J <jagathjog1996@gmail.com>
+
+description:
+ BMI323 is a 6-axis inertial measurement unit that supports acceleration and
+ gyroscopic measurements with hardware fifo buffering. Sensor also provides
+ events information such as motion, steps, orientation, single and double
+ tap detection.
+
+properties:
+ compatible:
+ const: bosch,bmi323
+
+ reg:
+ maxItems: 1
+
+ vdd-supply: true
+ vddio-supply: true
+
+ interrupts:
+ minItems: 1
+ maxItems: 2
+
+ interrupt-names:
+ minItems: 1
+ maxItems: 2
+ items:
+ enum:
+ - INT1
+ - INT2
+
+ drive-open-drain:
+ description:
+ set if the specified interrupt pin should be configured as
+ open drain. If not set, defaults to push-pull.
+
+ mount-matrix:
+ description:
+ an optional 3x3 mounting rotation matrix.
+
+required:
+ - compatible
+ - reg
+ - vdd-supply
+ - vddio-supply
+
+allOf:
+ - $ref: /schemas/spi/spi-peripheral-props.yaml#
+
+unevaluatedProperties: false
+
+examples:
+ - |
+ // Example for I2C
+ #include <dt-bindings/interrupt-controller/irq.h>
+ i2c {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ imu@68 {
+ compatible = "bosch,bmi323";
+ reg = <0x68>;
+ vddio-supply = <&vddio>;
+ vdd-supply = <&vdd>;
+ interrupt-parent = <&gpio1>;
+ interrupts = <29 IRQ_TYPE_EDGE_RISING>;
+ interrupt-names = "INT1";
+ };
+ };
diff --git a/dts/upstream/Bindings/iio/light/liteon,ltr390.yaml b/dts/upstream/Bindings/iio/light/liteon,ltr390.yaml
new file mode 100644
index 0000000..5d98ef2
--- /dev/null
+++ b/dts/upstream/Bindings/iio/light/liteon,ltr390.yaml
@@ -0,0 +1,56 @@
+# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/iio/light/liteon,ltr390.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Lite-On LTR390 ALS and UV Sensor
+
+description: |
+ The Lite-On LTR390 is an ALS (Ambient Light Sensor) and a UV sensor in a
+ single package with i2c address of 0x53.
+
+ Datasheet:
+ https://optoelectronics.liteon.com/upload/download/DS86-2015-0004/LTR-390UV_Final_%20DS_V1%201.pdf
+
+maintainers:
+ - Anshul Dalal <anshulusr@gmail.com>
+
+properties:
+ compatible:
+ enum:
+ - liteon,ltr390
+
+ reg:
+ maxItems: 1
+
+ interrupts:
+ maxItems: 1
+ description: |
+ Level interrupt pin with open drain output.
+ The sensor pulls this pin low when the measured reading is greater than
+ some configured threshold.
+
+ vdd-supply: true
+
+required:
+ - compatible
+ - reg
+
+additionalProperties: false
+
+examples:
+ - |
+ #include <dt-bindings/interrupt-controller/irq.h>
+
+ i2c {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ light-sensor@53 {
+ compatible = "liteon,ltr390";
+ reg = <0x53>;
+ interrupts = <18 IRQ_TYPE_EDGE_FALLING>;
+ vdd-supply = <&vdd_regulator>;
+ };
+ };
diff --git a/dts/upstream/Bindings/iio/light/vishay,veml6075.yaml b/dts/upstream/Bindings/iio/light/vishay,veml6075.yaml
new file mode 100644
index 0000000..abee04c
--- /dev/null
+++ b/dts/upstream/Bindings/iio/light/vishay,veml6075.yaml
@@ -0,0 +1,39 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/iio/light/vishay,veml6075.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Vishay VEML6075 UVA and UVB sensor
+
+maintainers:
+ - Javier Carrasco <javier.carrasco.cruz@gmail.com>
+
+properties:
+ compatible:
+ const: vishay,veml6075
+
+ reg:
+ maxItems: 1
+
+ vdd-supply: true
+
+required:
+ - compatible
+ - reg
+
+additionalProperties: false
+
+examples:
+ - |
+ i2c {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ uv-sensor@10 {
+ compatible = "vishay,veml6075";
+ reg = <0x10>;
+ vdd-supply = <&vdd_reg>;
+ };
+ };
+...
diff --git a/dts/upstream/Bindings/iio/pressure/honeywell,hsc030pa.yaml b/dts/upstream/Bindings/iio/pressure/honeywell,hsc030pa.yaml
new file mode 100644
index 0000000..65a24ed
--- /dev/null
+++ b/dts/upstream/Bindings/iio/pressure/honeywell,hsc030pa.yaml
@@ -0,0 +1,142 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/iio/pressure/honeywell,hsc030pa.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Honeywell TruStability HSC and SSC pressure sensor series
+
+description: |
+ support for Honeywell TruStability HSC and SSC digital pressure sensor
+ series.
+
+ These sensors have either an I2C, an SPI or an analog interface. Only the
+ digital versions are supported by this driver.
+
+ There are 118 models with different pressure ranges available in each family.
+ The vendor calls them "HSC series" and "SSC series". All of them have an
+ identical programming model but differ in pressure range, unit and transfer
+ function.
+
+ To support different models one needs to specify the pressure range as well
+ as the transfer function. Pressure range can either be provided via
+ pressure-triplet (directly extracted from the part number) or in case it's
+ a custom chip via numerical range limits converted to pascals.
+
+ The transfer function defines the ranges of raw conversion values delivered
+ by the sensor. pmin-pascal and pmax-pascal corespond to the minimum and
+ maximum pressure that can be measured.
+
+ Please note that in case of an SPI-based sensor, the clock signal should not
+ exceed 800kHz and the MOSI signal is not required.
+
+ Specifications about the devices can be found at:
+ https://prod-edam.honeywell.com/content/dam/honeywell-edam/sps/siot/en-us/products/sensors/pressure-sensors/board-mount-pressure-sensors/trustability-hsc-series/documents/sps-siot-trustability-hsc-series-high-accuracy-board-mount-pressure-sensors-50099148-a-en-ciid-151133.pdf
+ https://prod-edam.honeywell.com/content/dam/honeywell-edam/sps/siot/en-us/products/sensors/pressure-sensors/board-mount-pressure-sensors/trustability-ssc-series/documents/sps-siot-trustability-ssc-series-standard-accuracy-board-mount-pressure-sensors-50099533-a-en-ciid-151134.pdf
+
+maintainers:
+ - Petre Rodan <petre.rodan@subdimension.ro>
+
+properties:
+ compatible:
+ const: honeywell,hsc030pa
+
+ reg:
+ maxItems: 1
+
+ honeywell,transfer-function:
+ description: |
+ Transfer function which defines the range of valid values delivered by
+ the sensor.
+ 0 - A, 10% to 90% of 2^14
+ 1 - B, 5% to 95% of 2^14
+ 2 - C, 5% to 85% of 2^14
+ 3 - F, 4% to 94% of 2^14
+ enum: [0, 1, 2, 3]
+ $ref: /schemas/types.yaml#/definitions/uint32
+
+ honeywell,pressure-triplet:
+ description: |
+ Case-sensitive five character string that defines pressure range, unit
+ and type as part of the device nomenclature. In the unlikely case of a
+ custom chip, set to "NA" and provide pmin-pascal and pmax-pascal.
+ enum: [001BA, 1.6BA, 2.5BA, 004BA, 006BA, 010BA, 1.6MD, 2.5MD, 004MD,
+ 006MD, 010MD, 016MD, 025MD, 040MD, 060MD, 100MD, 160MD, 250MD,
+ 400MD, 600MD, 001BD, 1.6BD, 2.5BD, 004BD, 2.5MG, 004MG, 006MG,
+ 010MG, 016MG, 025MG, 040MG, 060MG, 100MG, 160MG, 250MG, 400MG,
+ 600MG, 001BG, 1.6BG, 2.5BG, 004BG, 006BG, 010BG, 100KA, 160KA,
+ 250KA, 400KA, 600KA, 001GA, 160LD, 250LD, 400LD, 600LD, 001KD,
+ 1.6KD, 2.5KD, 004KD, 006KD, 010KD, 016KD, 025KD, 040KD, 060KD,
+ 100KD, 160KD, 250KD, 400KD, 250LG, 400LG, 600LG, 001KG, 1.6KG,
+ 2.5KG, 004KG, 006KG, 010KG, 016KG, 025KG, 040KG, 060KG, 100KG,
+ 160KG, 250KG, 400KG, 600KG, 001GG, 015PA, 030PA, 060PA, 100PA,
+ 150PA, 0.5ND, 001ND, 002ND, 004ND, 005ND, 010ND, 020ND, 030ND,
+ 001PD, 005PD, 015PD, 030PD, 060PD, 001NG, 002NG, 004NG, 005NG,
+ 010NG, 020NG, 030NG, 001PG, 005PG, 015PG, 030PG, 060PG, 100PG,
+ 150PG, NA]
+ $ref: /schemas/types.yaml#/definitions/string
+
+ honeywell,pmin-pascal:
+ description: |
+ Minimum pressure value the sensor can measure in pascal.
+ To be specified only if honeywell,pressure-triplet is set to "NA".
+
+ honeywell,pmax-pascal:
+ description: |
+ Maximum pressure value the sensor can measure in pascal.
+ To be specified only if honeywell,pressure-triplet is set to "NA".
+
+ vdd-supply:
+ description:
+ Provide VDD power to the sensor (either 3.3V or 5V depending on the chip)
+
+ spi-max-frequency:
+ maximum: 800000
+
+required:
+ - compatible
+ - reg
+ - honeywell,transfer-function
+ - honeywell,pressure-triplet
+
+additionalProperties: false
+
+dependentSchemas:
+ honeywell,pmin-pascal:
+ properties:
+ honeywell,pressure-triplet:
+ const: NA
+ honeywell,pmax-pascal:
+ properties:
+ honeywell,pressure-triplet:
+ const: NA
+
+examples:
+ - |
+ i2c {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ pressure@28 {
+ compatible = "honeywell,hsc030pa";
+ reg = <0x28>;
+ honeywell,transfer-function = <0>;
+ honeywell,pressure-triplet = "030PA";
+ };
+ };
+ - |
+ spi {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ pressure@0 {
+ compatible = "honeywell,hsc030pa";
+ reg = <0>;
+ spi-max-frequency = <800000>;
+ honeywell,transfer-function = <0>;
+ honeywell,pressure-triplet = "NA";
+ honeywell,pmin-pascal = <0>;
+ honeywell,pmax-pascal = <200000>;
+ };
+ };
+...
diff --git a/dts/upstream/Bindings/iio/pressure/honeywell,mprls0025pa.yaml b/dts/upstream/Bindings/iio/pressure/honeywell,mprls0025pa.yaml
index b31f812..d9e903f 100644
--- a/dts/upstream/Bindings/iio/pressure/honeywell,mprls0025pa.yaml
+++ b/dts/upstream/Bindings/iio/pressure/honeywell,mprls0025pa.yaml
@@ -53,12 +53,10 @@
honeywell,pmin-pascal:
description:
Minimum pressure value the sensor can measure in pascal.
- $ref: /schemas/types.yaml#/definitions/uint32
honeywell,pmax-pascal:
description:
Maximum pressure value the sensor can measure in pascal.
- $ref: /schemas/types.yaml#/definitions/uint32
honeywell,transfer-function:
description: |
diff --git a/dts/upstream/Bindings/iio/temperature/melexis,mlx90632.yaml b/dts/upstream/Bindings/iio/temperature/melexis,mlx90632.yaml
index 4a55e7f..03bb5d4 100644
--- a/dts/upstream/Bindings/iio/temperature/melexis,mlx90632.yaml
+++ b/dts/upstream/Bindings/iio/temperature/melexis,mlx90632.yaml
@@ -4,7 +4,7 @@
$id: http://devicetree.org/schemas/iio/temperature/melexis,mlx90632.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
-title: Melexis MLX90632 contactless Infra Red temperature sensor
+title: Melexis MLX90632 and MLX90635 contactless Infra Red temperature sensor
maintainers:
- Crt Mori <cmo@melexis.com>
@@ -27,9 +27,24 @@
Since measured object emissivity effects Infra Red energy emitted,
emissivity should be set before requesting the object temperature.
+ https://www.melexis.com/en/documents/documentation/datasheets/datasheet-mlx90635
+
+ MLX90635 is most suitable for consumer applications where
+ measured object temperature is in range between -20 to 100 degrees
+ Celsius with relative error of measurement 2 degree Celsius in
+ object temperature range for industrial applications, while just 0.2
+ degree Celsius for human body measurement applications. Since it can
+ operate and measure ambient temperature in range of -20 to 85 degrees
+ Celsius it is suitable also for outdoor use.
+
+ Since measured object emissivity effects Infra Red energy emitted,
+ emissivity should be set before requesting the object temperature.
+
properties:
compatible:
- const: melexis,mlx90632
+ enum:
+ - melexis,mlx90632
+ - melexis,mlx90635
reg:
maxItems: 1
diff --git a/dts/upstream/Bindings/iio/temperature/microchip,mcp9600.yaml b/dts/upstream/Bindings/iio/temperature/microchip,mcp9600.yaml
new file mode 100644
index 0000000..d2cafa3
--- /dev/null
+++ b/dts/upstream/Bindings/iio/temperature/microchip,mcp9600.yaml
@@ -0,0 +1,70 @@
+# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/iio/temperature/microchip,mcp9600.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Microchip MCP9600 thermocouple EMF converter
+
+maintainers:
+ - Andrew Hepp <andrew.hepp@ahepp.dev>
+
+description:
+ https://ww1.microchip.com/downloads/en/DeviceDoc/MCP960X-Data-Sheet-20005426.pdf
+
+properties:
+ compatible:
+ const: microchip,mcp9600
+
+ reg:
+ maxItems: 1
+
+ interrupts:
+ minItems: 1
+ maxItems: 6
+
+ interrupt-names:
+ minItems: 1
+ maxItems: 6
+ items:
+ enum:
+ - open-circuit
+ - short-circuit
+ - alert1
+ - alert2
+ - alert3
+ - alert4
+
+ thermocouple-type:
+ $ref: /schemas/types.yaml#/definitions/uint32
+ description:
+ Type of thermocouple (THERMOCOUPLE_TYPE_K if omitted).
+ Use defines in dt-bindings/iio/temperature/thermocouple.h.
+ Supported types are B, E, J, K, N, R, S, T.
+
+ vdd-supply: true
+
+required:
+ - compatible
+ - reg
+
+additionalProperties: false
+
+examples:
+ - |
+ #include <dt-bindings/iio/temperature/thermocouple.h>
+ #include <dt-bindings/interrupt-controller/irq.h>
+ i2c {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ temperature-sensor@60 {
+ compatible = "microchip,mcp9600";
+ reg = <0x60>;
+ interrupt-parent = <&gpio>;
+ interrupts = <25 IRQ_TYPE_EDGE_RISING>;
+ interrupt-names = "open-circuit";
+ thermocouple-type = <THERMOCOUPLE_TYPE_K>;
+ vdd-supply = <&vdd>;
+ };
+ };
diff --git a/dts/upstream/Bindings/index.rst b/dts/upstream/Bindings/index.rst
index d9002a3..cc1fbdc 100644
--- a/dts/upstream/Bindings/index.rst
+++ b/dts/upstream/Bindings/index.rst
@@ -4,6 +4,7 @@
:maxdepth: 1
ABI
+ dts-coding-style
writing-bindings
writing-schema
submitting-patches
diff --git a/dts/upstream/Bindings/input/adafruit,seesaw-gamepad.yaml b/dts/upstream/Bindings/input/adafruit,seesaw-gamepad.yaml
new file mode 100644
index 0000000..5e86f6d
--- /dev/null
+++ b/dts/upstream/Bindings/input/adafruit,seesaw-gamepad.yaml
@@ -0,0 +1,63 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/input/adafruit,seesaw-gamepad.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Adafruit Mini I2C Gamepad with seesaw
+
+maintainers:
+ - Anshul Dalal <anshulusr@gmail.com>
+
+description: |
+ Adafruit Mini I2C Gamepad
+
+ +-----------------------------+
+ | ___ |
+ | / \ (X) |
+ | | S | __ __ (Y) (A) |
+ | \___/ |ST| |SE| (B) |
+ | |
+ +-----------------------------+
+
+ S -> 10-bit precision bidirectional analog joystick
+ ST -> Start
+ SE -> Select
+ X, A, B, Y -> Digital action buttons
+
+ Datasheet: https://cdn-learn.adafruit.com/downloads/pdf/gamepad-qt.pdf
+ Product page: https://www.adafruit.com/product/5743
+ Arduino Driver: https://github.com/adafruit/Adafruit_Seesaw
+
+properties:
+ compatible:
+ const: adafruit,seesaw-gamepad
+
+ reg:
+ maxItems: 1
+
+ interrupts:
+ maxItems: 1
+ description:
+ The gamepad's IRQ pin triggers a rising edge if interrupts are enabled.
+
+required:
+ - compatible
+ - reg
+
+additionalProperties: false
+
+examples:
+ - |
+ #include <dt-bindings/interrupt-controller/irq.h>
+
+ i2c {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ joystick@50 {
+ compatible = "adafruit,seesaw-gamepad";
+ interrupts = <18 IRQ_TYPE_EDGE_RISING>;
+ reg = <0x50>;
+ };
+ };
diff --git a/dts/upstream/Bindings/input/elan,ekth6915.yaml b/dts/upstream/Bindings/input/elan,ekth6915.yaml
index 3e2d216..dc4ac41 100644
--- a/dts/upstream/Bindings/input/elan,ekth6915.yaml
+++ b/dts/upstream/Bindings/input/elan,ekth6915.yaml
@@ -18,8 +18,9 @@
properties:
compatible:
- items:
- - const: elan,ekth6915
+ enum:
+ - elan,ekth6915
+ - ilitek,ili2901
reg:
const: 0x10
diff --git a/dts/upstream/Bindings/input/gpio-keys.yaml b/dts/upstream/Bindings/input/gpio-keys.yaml
index 159cd9d..cc78c21 100644
--- a/dts/upstream/Bindings/input/gpio-keys.yaml
+++ b/dts/upstream/Bindings/input/gpio-keys.yaml
@@ -31,7 +31,23 @@
maxItems: 1
interrupts:
- maxItems: 1
+ oneOf:
+ - items:
+ - description: Optional key interrupt or wakeup interrupt
+ - items:
+ - description: Key interrupt
+ - description: Wakeup interrupt
+
+ interrupt-names:
+ description:
+ Optional interrupt names, can be used to specify a separate dedicated
+ wake-up interrupt in addition to the gpio irq
+ oneOf:
+ - items:
+ - enum: [ irq, wakeup ]
+ - items:
+ - const: irq
+ - const: wakeup
label:
description: Descriptive name of the key.
@@ -97,6 +113,20 @@
- required:
- gpios
+ allOf:
+ - if:
+ properties:
+ interrupts:
+ minItems: 2
+ required:
+ - interrupts
+ then:
+ properties:
+ interrupt-names:
+ minItems: 2
+ required:
+ - interrupt-names
+
dependencies:
wakeup-event-action: [ wakeup-source ]
linux,input-value: [ gpios ]
@@ -137,6 +167,15 @@
linux,code = <108>;
interrupts = <1 IRQ_TYPE_EDGE_FALLING>;
};
+
+ key-wakeup {
+ label = "GPIO Key WAKEUP";
+ linux,code = <143>;
+ interrupts-extended = <&intc 2 IRQ_TYPE_EDGE_FALLING>,
+ <&intc_wakeup 0 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "irq", "wakeup";
+ wakeup-source;
+ };
};
...
diff --git a/dts/upstream/Bindings/input/gpio-mouse.txt b/dts/upstream/Bindings/input/gpio-mouse.txt
deleted file mode 100644
index 519510a..0000000
--- a/dts/upstream/Bindings/input/gpio-mouse.txt
+++ /dev/null
@@ -1,32 +0,0 @@
-Device-Tree bindings for GPIO attached mice
-
-This simply uses standard GPIO handles to define a simple mouse connected
-to 5-7 GPIO lines.
-
-Required properties:
- - compatible: must be "gpio-mouse"
- - scan-interval-ms: The scanning interval in milliseconds
- - up-gpios: GPIO line phandle to the line indicating "up"
- - down-gpios: GPIO line phandle to the line indicating "down"
- - left-gpios: GPIO line phandle to the line indicating "left"
- - right-gpios: GPIO line phandle to the line indicating "right"
-
-Optional properties:
- - button-left-gpios: GPIO line handle to the left mouse button
- - button-middle-gpios: GPIO line handle to the middle mouse button
- - button-right-gpios: GPIO line handle to the right mouse button
-Example:
-
-#include <dt-bindings/gpio/gpio.h>
-
-gpio-mouse {
- compatible = "gpio-mouse";
- scan-interval-ms = <50>;
- up-gpios = <&gpio0 0 GPIO_ACTIVE_LOW>;
- down-gpios = <&gpio0 1 GPIO_ACTIVE_LOW>;
- left-gpios = <&gpio0 2 GPIO_ACTIVE_LOW>;
- right-gpios = <&gpio0 3 GPIO_ACTIVE_LOW>;
- button-left-gpios = <&gpio0 4 GPIO_ACTIVE_LOW>;
- button-middle-gpios = <&gpio0 5 GPIO_ACTIVE_LOW>;
- button-right-gpios = <&gpio0 6 GPIO_ACTIVE_LOW>;
-};
diff --git a/dts/upstream/Bindings/input/gpio-mouse.yaml b/dts/upstream/Bindings/input/gpio-mouse.yaml
new file mode 100644
index 0000000..3928ec6
--- /dev/null
+++ b/dts/upstream/Bindings/input/gpio-mouse.yaml
@@ -0,0 +1,68 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/input/gpio-mouse.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: GPIO attached mouse
+
+description: |
+ This simply uses standard GPIO handles to define a simple mouse connected
+ to 5-7 GPIO lines.
+
+maintainers:
+ - Anshul Dalal <anshulusr@gmail.com>
+
+properties:
+ compatible:
+ const: gpio-mouse
+
+ scan-interval-ms:
+ maxItems: 1
+
+ up-gpios:
+ maxItems: 1
+
+ down-gpios:
+ maxItems: 1
+
+ left-gpios:
+ maxItems: 1
+
+ right-gpios:
+ maxItems: 1
+
+ button-left-gpios:
+ maxItems: 1
+
+ button-middle-gpios:
+ maxItems: 1
+
+ button-right-gpios:
+ maxItems: 1
+
+required:
+ - compatible
+ - scan-interval-ms
+ - up-gpios
+ - down-gpios
+ - left-gpios
+ - right-gpios
+
+additionalProperties: false
+
+examples:
+ - |
+ #include <dt-bindings/gpio/gpio.h>
+
+ gpio-mouse {
+ compatible = "gpio-mouse";
+ scan-interval-ms = <50>;
+ up-gpios = <&gpio0 0 GPIO_ACTIVE_LOW>;
+ down-gpios = <&gpio0 1 GPIO_ACTIVE_LOW>;
+ left-gpios = <&gpio0 2 GPIO_ACTIVE_LOW>;
+ right-gpios = <&gpio0 3 GPIO_ACTIVE_LOW>;
+ button-left-gpios = <&gpio0 4 GPIO_ACTIVE_LOW>;
+ button-middle-gpios = <&gpio0 5 GPIO_ACTIVE_LOW>;
+ button-right-gpios = <&gpio0 6 GPIO_ACTIVE_LOW>;
+ };
diff --git a/dts/upstream/Bindings/input/iqs269a.yaml b/dts/upstream/Bindings/input/iqs269a.yaml
index 3c430d3..2c3f693 100644
--- a/dts/upstream/Bindings/input/iqs269a.yaml
+++ b/dts/upstream/Bindings/input/iqs269a.yaml
@@ -9,6 +9,9 @@
maintainers:
- Jeff LaBundy <jeff@labundy.com>
+allOf:
+ - $ref: input.yaml#
+
description: |
The Azoteq IQS269A is an 8-channel capacitive touch controller that features
additional Hall-effect and inductive sensing capabilities.
@@ -17,7 +20,10 @@
properties:
compatible:
- const: azoteq,iqs269a
+ enum:
+ - azoteq,iqs269a
+ - azoteq,iqs269a-00
+ - azoteq,iqs269a-d0
reg:
maxItems: 1
@@ -204,6 +210,73 @@
default: 1
description: Specifies the slider coordinate filter strength.
+ azoteq,touch-hold-ms:
+ multipleOf: 256
+ minimum: 256
+ maximum: 65280
+ default: 5120
+ description:
+ Specifies the length of time (in ms) for which the channel selected by
+ 'azoteq,gpio3-select' must be held in a state of touch in order for an
+ approximately 60-ms pulse to be asserted on the GPIO4 pin.
+
+ linux,keycodes:
+ minItems: 1
+ maxItems: 8
+ description: |
+ Specifies the numeric keycodes associated with each available gesture in
+ the following order (enter 0 for unused gestures):
+ 0: Slider 0 tap
+ 1: Slider 0 hold
+ 2: Slider 0 positive flick or swipe
+ 3: Slider 0 negative flick or swipe
+ 4: Slider 1 tap
+ 5: Slider 1 hold
+ 6: Slider 1 positive flick or swipe
+ 7: Slider 1 negative flick or swipe
+
+ azoteq,gesture-swipe:
+ type: boolean
+ description:
+ Directs the device to interpret axial gestures as a swipe (finger remains
+ on slider) instead of a flick (finger leaves slider).
+
+ azoteq,timeout-tap-ms:
+ multipleOf: 16
+ minimum: 0
+ maximum: 4080
+ default: 400
+ description:
+ Specifies the length of time (in ms) within which a slider touch must be
+ released in order to be interpreted as a tap. Default and maximum values
+ as well as step size are reduced by a factor of 4 with device version 2.
+
+ azoteq,timeout-swipe-ms:
+ multipleOf: 16
+ minimum: 0
+ maximum: 4080
+ default: 2000
+ description:
+ Specifies the length of time (in ms) within which an axial gesture must be
+ completed in order to be interpreted as a flick or swipe. Default and max-
+ imum values as well as step size are reduced by a factor of 4 with device
+ version 2.
+
+ azoteq,thresh-swipe:
+ $ref: /schemas/types.yaml#/definitions/uint32
+ minimum: 0
+ maximum: 255
+ default: 128
+ description:
+ Specifies the number of points across which an axial gesture must travel
+ in order to be interpreted as a flick or swipe.
+
+dependencies:
+ azoteq,gesture-swipe: ["linux,keycodes"]
+ azoteq,timeout-tap-ms: ["linux,keycodes"]
+ azoteq,timeout-swipe-ms: ["linux,keycodes"]
+ azoteq,thresh-swipe: ["linux,keycodes"]
+
patternProperties:
"^channel@[0-7]$":
type: object
@@ -454,6 +527,21 @@
additionalProperties: false
+if:
+ properties:
+ compatible:
+ contains:
+ enum:
+ - azoteq,iqs269a-d0
+then:
+ patternProperties:
+ "^channel@[0-7]$":
+ properties:
+ azoteq,slider1-select: false
+else:
+ properties:
+ azoteq,touch-hold-ms: false
+
required:
- compatible
- reg
@@ -484,6 +572,14 @@
azoteq,hall-enable;
azoteq,suspend-mode = <2>;
+ linux,keycodes = <KEY_PLAYPAUSE>,
+ <KEY_STOPCD>,
+ <KEY_NEXTSONG>,
+ <KEY_PREVIOUSSONG>;
+
+ azoteq,timeout-tap-ms = <400>;
+ azoteq,timeout-swipe-ms = <800>;
+
channel@0 {
reg = <0x0>;
diff --git a/dts/upstream/Bindings/input/mediatek,pmic-keys.yaml b/dts/upstream/Bindings/input/mediatek,pmic-keys.yaml
index e34c9e7..70567d92 100644
--- a/dts/upstream/Bindings/input/mediatek,pmic-keys.yaml
+++ b/dts/upstream/Bindings/input/mediatek,pmic-keys.yaml
@@ -90,26 +90,4 @@
unevaluatedProperties: false
-examples:
- - |
- #include <dt-bindings/input/input.h>
- #include <dt-bindings/interrupt-controller/arm-gic.h>
-
- pmic {
- compatible = "mediatek,mt6397";
-
- keys {
- compatible = "mediatek,mt6397-keys";
- mediatek,long-press-mode = <1>;
- power-off-time-sec = <0>;
-
- key-power {
- linux,keycodes = <KEY_POWER>;
- wakeup-source;
- };
-
- key-home {
- linux,keycodes = <KEY_VOLUMEDOWN>;
- };
- };
- };
+...
diff --git a/dts/upstream/Bindings/input/microchip,cap11xx.yaml b/dts/upstream/Bindings/input/microchip,cap11xx.yaml
index 5b5d4f7..7ade03f 100644
--- a/dts/upstream/Bindings/input/microchip,cap11xx.yaml
+++ b/dts/upstream/Bindings/input/microchip,cap11xx.yaml
@@ -45,13 +45,13 @@
Enables the Linux input system's autorepeat feature on the input device.
linux,keycodes:
- minItems: 6
- maxItems: 6
+ minItems: 3
+ maxItems: 8
description: |
Specifies an array of numeric keycode values to
be used for the channels. If this property is
omitted, KEY_A, KEY_B, etc are used as defaults.
- The array must have exactly six entries.
+ The number of entries must correspond to the number of channels.
microchip,sensor-gain:
$ref: /schemas/types.yaml#/definitions/uint32
@@ -70,6 +70,59 @@
open drain. This property allows using the active
high push-pull output.
+ microchip,sensitivity-delta-sense:
+ $ref: /schemas/types.yaml#/definitions/uint32
+ default: 32
+ enum: [1, 2, 4, 8, 16, 32, 64, 128]
+ description:
+ Controls the sensitivity multiplier of a touch detection.
+ Higher value means more sensitive settings.
+ At the more sensitive settings, touches are detected for a smaller delta
+ capacitance corresponding to a "lighter" touch.
+
+ microchip,signal-guard:
+ $ref: /schemas/types.yaml#/definitions/uint32-array
+ minItems: 3
+ maxItems: 8
+ items:
+ enum: [0, 1]
+ description: |
+ 0 - off
+ 1 - on
+ The signal guard isolates the signal from virtual grounds.
+ If enabled then the behavior of the channel is changed to signal guard.
+ The number of entries must correspond to the number of channels.
+
+ microchip,input-threshold:
+ $ref: /schemas/types.yaml#/definitions/uint32-array
+ minItems: 3
+ maxItems: 8
+ items:
+ minimum: 0
+ maximum: 127
+ description:
+ Specifies the delta threshold that is used to determine if a touch has
+ been detected. A higher value means a larger difference in capacitance
+ is required for a touch to be registered, making the touch sensor less
+ sensitive.
+ The number of entries must correspond to the number of channels.
+
+ microchip,calib-sensitivity:
+ $ref: /schemas/types.yaml#/definitions/uint32-array
+ minItems: 3
+ maxItems: 8
+ items:
+ enum: [1, 2, 4]
+ description: |
+ Specifies an array of numeric values that controls the gain
+ used by the calibration routine to enable sensor inputs
+ to be more sensitive for proximity detection.
+ Gain is based on touch pad capacitance range
+ 1 - 5-50pF
+ 2 - 0-25pF
+ 4 - 0-12.5pF
+ The number of entries must correspond to the number of channels.
+
patternProperties:
"^led@[0-7]$":
type: object
@@ -99,10 +152,29 @@
contains:
enum:
- microchip,cap1106
+ - microchip,cap1203
+ - microchip,cap1206
+ - microchip,cap1293
+ - microchip,cap1298
then:
patternProperties:
"^led@[0-7]$": false
+ - if:
+ properties:
+ compatible:
+ contains:
+ enum:
+ - microchip,cap1106
+ - microchip,cap1126
+ - microchip,cap1188
+ - microchip,cap1203
+ - microchip,cap1206
+ then:
+ properties:
+ microchip,signal-guard: false
+ microchip,calib-sensitivity: false
+
required:
- compatible
- interrupts
@@ -122,6 +194,8 @@
reg = <0x28>;
autorepeat;
microchip,sensor-gain = <2>;
+ microchip,sensitivity-delta-sense = <16>;
+ microchip,input-threshold = <21>, <18>, <46>, <46>, <46>, <21>;
linux,keycodes = <103>, /* KEY_UP */
<106>, /* KEY_RIGHT */
diff --git a/dts/upstream/Bindings/input/sprd,sc27xx-vibrator.yaml b/dts/upstream/Bindings/input/sprd,sc27xx-vibrator.yaml
index a401a0b..4c8d303 100644
--- a/dts/upstream/Bindings/input/sprd,sc27xx-vibrator.yaml
+++ b/dts/upstream/Bindings/input/sprd,sc27xx-vibrator.yaml
@@ -28,21 +28,4 @@
additionalProperties: false
-examples:
- - |
- #include <dt-bindings/interrupt-controller/arm-gic.h>
- sc2731_pmic: pmic@0 {
- compatible = "sprd,sc2731";
- reg = <0 0>;
- spi-max-frequency = <26000000>;
- interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
- interrupt-controller;
- #interrupt-cells = <2>;
- #address-cells = <1>;
- #size-cells = <0>;
-
- vibrator@eb4 {
- compatible = "sprd,sc2731-vibrator";
- reg = <0xeb4>;
- };
- };
+...
diff --git a/dts/upstream/Bindings/input/ti,drv2665.txt b/dts/upstream/Bindings/input/ti,drv2665.txt
deleted file mode 100644
index 1ba97ac..0000000
--- a/dts/upstream/Bindings/input/ti,drv2665.txt
+++ /dev/null
@@ -1,17 +0,0 @@
-* Texas Instruments - drv2665 Haptics driver
-
-Required properties:
- - compatible - "ti,drv2665" - DRV2665
- - reg - I2C slave address
- - vbat-supply - Required supply regulator
-
-Example:
-
-haptics: haptics@59 {
- compatible = "ti,drv2665";
- reg = <0x59>;
- vbat-supply = <&vbat>;
-};
-
-For more product information please see the link below:
-http://www.ti.com/product/drv2665
diff --git a/dts/upstream/Bindings/input/ti,drv2667.txt b/dts/upstream/Bindings/input/ti,drv2667.txt
deleted file mode 100644
index 996382c..0000000
--- a/dts/upstream/Bindings/input/ti,drv2667.txt
+++ /dev/null
@@ -1,17 +0,0 @@
-* Texas Instruments - drv2667 Haptics driver
-
-Required properties:
- - compatible - "ti,drv2667" - DRV2667
- - reg - I2C slave address
- - vbat-supply - Required supply regulator
-
-Example:
-
-haptics: haptics@59 {
- compatible = "ti,drv2667";
- reg = <0x59>;
- vbat-supply = <&vbat>;
-};
-
-For more product information please see the link below:
-http://www.ti.com/product/drv2667
diff --git a/dts/upstream/Bindings/input/ti,drv266x.yaml b/dts/upstream/Bindings/input/ti,drv266x.yaml
new file mode 100644
index 0000000..da18188
--- /dev/null
+++ b/dts/upstream/Bindings/input/ti,drv266x.yaml
@@ -0,0 +1,50 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/input/ti,drv266x.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Texas Instruments - drv266x Haptics driver
+
+description: |
+ Product Page:
+ http://www.ti.com/product/drv2665
+ http://www.ti.com/product/drv2667
+
+maintainers:
+ - Anshul Dalal <anshulusr@gmail.com>
+
+properties:
+ compatible:
+ enum:
+ - ti,drv2665
+ - ti,drv2667
+
+ reg:
+ maxItems: 1
+
+ vbat-supply:
+ description: Required supply regulator
+
+required:
+ - compatible
+ - reg
+ - vbat-supply
+
+additionalProperties: false
+
+examples:
+ - |
+ #include <dt-bindings/gpio/gpio.h>
+
+
+ i2c {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ haptics@59 {
+ compatible = "ti,drv2667";
+ reg = <0x59>;
+ vbat-supply = <&vbat>;
+ };
+ };
diff --git a/dts/upstream/Bindings/input/touchscreen/neonode,zforce.yaml b/dts/upstream/Bindings/input/touchscreen/neonode,zforce.yaml
new file mode 100644
index 0000000..c2ee89b
--- /dev/null
+++ b/dts/upstream/Bindings/input/touchscreen/neonode,zforce.yaml
@@ -0,0 +1,72 @@
+# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/input/touchscreen/neonode,zforce.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Neonode infrared touchscreen controller
+
+maintainers:
+ - Heiko Stuebner <heiko@sntech.de>
+
+allOf:
+ - $ref: touchscreen.yaml#
+
+properties:
+ compatible:
+ const: neonode,zforce
+
+ reg:
+ maxItems: 1
+
+ interrupts:
+ maxItems: 1
+
+ reset-gpios:
+ maxItems: 1
+
+ irq-gpios:
+ maxItems: 1
+
+ x-size:
+ deprecated: true
+ $ref: /schemas/types.yaml#/definitions/uint32
+
+ y-size:
+ deprecated: true
+ $ref: /schemas/types.yaml#/definitions/uint32
+
+ vdd-supply: true
+
+required:
+ - compatible
+ - reg
+ - interrupts
+ - reset-gpios
+
+unevaluatedProperties: false
+
+examples:
+ - |
+ #include <dt-bindings/interrupt-controller/irq.h>
+
+ i2c {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ touchscreen@50 {
+ compatible = "neonode,zforce";
+ reg = <0x50>;
+ interrupts = <2 0>;
+ vdd-supply = <®_zforce_vdd>;
+
+ reset-gpios = <&gpio5 9 0>; /* RST */
+ irq-gpios = <&gpio5 6 0>; /* IRQ, optional */
+
+ touchscreen-min-x = <0>;
+ touchscreen-size-x = <800>;
+ touchscreen-min-y = <0>;
+ touchscreen-size-y = <600>;
+ };
+ };
+...
diff --git a/dts/upstream/Bindings/input/touchscreen/samsung,s6sy761.txt b/dts/upstream/Bindings/input/touchscreen/samsung,s6sy761.txt
deleted file mode 100644
index 6805d10..0000000
--- a/dts/upstream/Bindings/input/touchscreen/samsung,s6sy761.txt
+++ /dev/null
@@ -1,32 +0,0 @@
-* Samsung S6SY761 touchscreen controller
-
-Required properties:
-- compatible : must be "samsung,s6sy761"
-- reg : I2C slave address, (e.g. 0x48)
-- interrupts : interrupt specification
-- avdd-supply : analogic power supply
-- vdd-supply : power supply
-
-Optional properties:
-- touchscreen-size-x : see touchscreen.txt. This property is embedded in the
- device. If defined it forces a different x resolution.
-- touchscreen-size-y : see touchscreen.txt. This property is embedded in the
- device. If defined it forces a different y resolution.
-
-Example:
-
-i2c@00000000 {
-
- /* ... */
-
- touchscreen@48 {
- compatible = "samsung,s6sy761";
- reg = <0x48>;
- interrupt-parent = <&gpa1>;
- interrupts = <1 IRQ_TYPE_NONE>;
- avdd-supply = <&ldo30_reg>;
- vdd-supply = <&ldo31_reg>;
- touchscreen-size-x = <4096>;
- touchscreen-size-y = <4096>;
- };
-};
diff --git a/dts/upstream/Bindings/input/touchscreen/samsung,s6sy761.yaml b/dts/upstream/Bindings/input/touchscreen/samsung,s6sy761.yaml
new file mode 100644
index 0000000..1ffd17a
--- /dev/null
+++ b/dts/upstream/Bindings/input/touchscreen/samsung,s6sy761.yaml
@@ -0,0 +1,54 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/input/touchscreen/samsung,s6sy761.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Samsung S6SY761 touchscreen controller
+
+maintainers:
+ - Andi Shyti <andi.shyti@kernel.org>
+
+allOf:
+ - $ref: touchscreen.yaml#
+
+properties:
+ compatible:
+ const: samsung,s6sy761
+
+ reg:
+ maxItems: 1
+
+ interrupts:
+ maxItems: 1
+
+ avdd-supply: true
+ vdd-supply: true
+
+unevaluatedProperties: false
+
+required:
+ - compatible
+ - reg
+ - interrupts
+ - avdd-supply
+ - vdd-supply
+
+examples:
+ - |
+ #include <dt-bindings/interrupt-controller/irq.h>
+ i2c {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ touchscreen@48 {
+ compatible = "samsung,s6sy761";
+ reg = <0x48>;
+ interrupt-parent = <&gpa1>;
+ interrupts = <1 IRQ_TYPE_LEVEL_HIGH>;
+ avdd-supply = <&ldo30_reg>;
+ vdd-supply = <&ldo31_reg>;
+ touchscreen-size-x = <4096>;
+ touchscreen-size-y = <4096>;
+ };
+ };
diff --git a/dts/upstream/Bindings/input/touchscreen/zforce_ts.txt b/dts/upstream/Bindings/input/touchscreen/zforce_ts.txt
deleted file mode 100644
index e3c27c4..0000000
--- a/dts/upstream/Bindings/input/touchscreen/zforce_ts.txt
+++ /dev/null
@@ -1,34 +0,0 @@
-* Neonode infrared touchscreen controller
-
-Required properties:
-- compatible: must be "neonode,zforce"
-- reg: I2C address of the chip
-- interrupts: interrupt to which the chip is connected
-- reset-gpios: reset gpio the chip is connected to
-- x-size: horizontal resolution of touchscreen
-- y-size: vertical resolution of touchscreen
-
-Optional properties:
-- irq-gpios : interrupt gpio the chip is connected to
-- vdd-supply: Regulator controlling the controller supply
-
-Example:
-
- i2c@00000000 {
- /* ... */
-
- zforce_ts@50 {
- compatible = "neonode,zforce";
- reg = <0x50>;
- interrupts = <2 0>;
- vdd-supply = <®_zforce_vdd>;
-
- reset-gpios = <&gpio5 9 0>; /* RST */
- irq-gpios = <&gpio5 6 0>; /* IRQ, optional */
-
- x-size = <800>;
- y-size = <600>;
- };
-
- /* ... */
- };
diff --git a/dts/upstream/Bindings/interconnect/qcom,msm8998-bwmon.yaml b/dts/upstream/Bindings/interconnect/qcom,msm8998-bwmon.yaml
index 73f809c..05067e1 100644
--- a/dts/upstream/Bindings/interconnect/qcom,msm8998-bwmon.yaml
+++ b/dts/upstream/Bindings/interconnect/qcom,msm8998-bwmon.yaml
@@ -25,13 +25,16 @@
- const: qcom,msm8998-bwmon # BWMON v4
- items:
- enum:
+ - qcom,qcm2290-cpu-bwmon
- qcom,sc7180-cpu-bwmon
- qcom,sc7280-cpu-bwmon
- qcom,sc8280xp-cpu-bwmon
- qcom,sdm845-cpu-bwmon
+ - qcom,sm6115-cpu-bwmon
- qcom,sm6350-llcc-bwmon
- qcom,sm8250-cpu-bwmon
- qcom,sm8550-cpu-bwmon
+ - qcom,sm8650-cpu-bwmon
- const: qcom,sdm845-bwmon # BWMON v4, unified register space
- items:
- enum:
@@ -40,6 +43,7 @@
- qcom,sm6350-cpu-bwmon
- qcom,sm8250-llcc-bwmon
- qcom,sm8550-llcc-bwmon
+ - qcom,sm8650-llcc-bwmon
- const: qcom,sc7280-llcc-bwmon
- const: qcom,sc7280-llcc-bwmon # BWMON v5
- const: qcom,sdm845-llcc-bwmon # BWMON v5
diff --git a/dts/upstream/Bindings/interconnect/qcom,sm6115.yaml b/dts/upstream/Bindings/interconnect/qcom,sm6115.yaml
new file mode 100644
index 0000000..14b1a0b
--- /dev/null
+++ b/dts/upstream/Bindings/interconnect/qcom,sm6115.yaml
@@ -0,0 +1,152 @@
+# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/interconnect/qcom,sm6115.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Qualcomm SM6115 Network-On-Chip interconnect
+
+maintainers:
+ - Konrad Dybcio <konradybcio@kernel.org>
+
+description:
+ The Qualcomm SM6115 interconnect providers support adjusting the
+ bandwidth requirements between the various NoC fabrics.
+
+properties:
+ compatible:
+ enum:
+ - qcom,sm6115-bimc
+ - qcom,sm6115-cnoc
+ - qcom,sm6115-snoc
+
+ reg:
+ maxItems: 1
+
+ clocks:
+ minItems: 1
+ maxItems: 4
+
+ clock-names:
+ minItems: 1
+ maxItems: 4
+
+# Child node's properties
+patternProperties:
+ '^interconnect-[a-z0-9]+$':
+ type: object
+ description:
+ The interconnect providers do not have a separate QoS register space,
+ but share parent's space.
+
+ $ref: qcom,rpm-common.yaml#
+
+ properties:
+ compatible:
+ enum:
+ - qcom,sm6115-clk-virt
+ - qcom,sm6115-mmrt-virt
+ - qcom,sm6115-mmnrt-virt
+
+ required:
+ - compatible
+
+ unevaluatedProperties: false
+
+required:
+ - compatible
+ - reg
+
+allOf:
+ - $ref: qcom,rpm-common.yaml#
+ - if:
+ properties:
+ compatible:
+ const: qcom,sm6115-cnoc
+
+ then:
+ properties:
+ clocks:
+ items:
+ - description: USB-NoC AXI clock
+
+ clock-names:
+ items:
+ - const: usb_axi
+
+ - if:
+ properties:
+ compatible:
+ const: qcom,sm6115-snoc
+
+ then:
+ properties:
+ clocks:
+ items:
+ - description: CPU-NoC AXI clock.
+ - description: UFS-NoC AXI clock.
+ - description: USB-NoC AXI clock.
+ - description: IPA clock.
+
+ clock-names:
+ items:
+ - const: cpu_axi
+ - const: ufs_axi
+ - const: usb_axi
+ - const: ipa
+
+ - if:
+ properties:
+ compatible:
+ enum:
+ - qcom,sm6115-bimc
+ - qcom,sm6115-clk-virt
+ - qcom,sm6115-mmrt-virt
+ - qcom,sm6115-mmnrt-virt
+
+ then:
+ properties:
+ clocks: false
+ clock-names: false
+
+unevaluatedProperties: false
+
+examples:
+ - |
+ #include <dt-bindings/clock/qcom,gcc-sm6115.h>
+ #include <dt-bindings/clock/qcom,rpmcc.h>
+
+ snoc: interconnect@1880000 {
+ compatible = "qcom,sm6115-snoc";
+ reg = <0x01880000 0x60200>;
+ clocks = <&gcc GCC_SYS_NOC_CPUSS_AHB_CLK>,
+ <&gcc GCC_SYS_NOC_UFS_PHY_AXI_CLK>,
+ <&gcc GCC_SYS_NOC_USB3_PRIM_AXI_CLK>,
+ <&rpmcc RPM_SMD_IPA_CLK>;
+ clock-names = "cpu_axi",
+ "ufs_axi",
+ "usb_axi",
+ "ipa";
+ #interconnect-cells = <1>;
+
+ qup_virt: interconnect-clk {
+ compatible = "qcom,sm6115-clk-virt";
+ #interconnect-cells = <1>;
+ };
+
+ mmnrt_virt: interconnect-mmnrt {
+ compatible = "qcom,sm6115-mmnrt-virt";
+ #interconnect-cells = <1>;
+ };
+
+ mmrt_virt: interconnect-mmrt {
+ compatible = "qcom,sm6115-mmrt-virt";
+ #interconnect-cells = <1>;
+ };
+ };
+
+ cnoc: interconnect@1900000 {
+ compatible = "qcom,sm6115-cnoc";
+ reg = <0x01900000 0x8200>;
+ #interconnect-cells = <1>;
+ };
diff --git a/dts/upstream/Bindings/interconnect/qcom,sm8650-rpmh.yaml b/dts/upstream/Bindings/interconnect/qcom,sm8650-rpmh.yaml
new file mode 100644
index 0000000..f9322de
--- /dev/null
+++ b/dts/upstream/Bindings/interconnect/qcom,sm8650-rpmh.yaml
@@ -0,0 +1,136 @@
+# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/interconnect/qcom,sm8650-rpmh.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Qualcomm RPMh Network-On-Chip Interconnect on SM8650
+
+maintainers:
+ - Abel Vesa <abel.vesa@linaro.org>
+ - Neil Armstrong <neil.armstrong@linaro.org>
+
+description: |
+ RPMh interconnect providers support system bandwidth requirements through
+ RPMh hardware accelerators known as Bus Clock Manager (BCM). The provider is
+ able to communicate with the BCM through the Resource State Coordinator (RSC)
+ associated with each execution environment. Provider nodes must point to at
+ least one RPMh device child node pertaining to their RSC and each provider
+ can map to multiple RPMh resources.
+
+ See also:: include/dt-bindings/interconnect/qcom,sm8650-rpmh.h
+
+properties:
+ compatible:
+ enum:
+ - qcom,sm8650-aggre1-noc
+ - qcom,sm8650-aggre2-noc
+ - qcom,sm8650-clk-virt
+ - qcom,sm8650-cnoc-main
+ - qcom,sm8650-config-noc
+ - qcom,sm8650-gem-noc
+ - qcom,sm8650-lpass-ag-noc
+ - qcom,sm8650-lpass-lpiaon-noc
+ - qcom,sm8650-lpass-lpicx-noc
+ - qcom,sm8650-mc-virt
+ - qcom,sm8650-mmss-noc
+ - qcom,sm8650-nsp-noc
+ - qcom,sm8650-pcie-anoc
+ - qcom,sm8650-system-noc
+
+ reg:
+ maxItems: 1
+
+ clocks:
+ minItems: 1
+ maxItems: 2
+
+required:
+ - compatible
+
+allOf:
+ - $ref: qcom,rpmh-common.yaml#
+ - if:
+ properties:
+ compatible:
+ contains:
+ enum:
+ - qcom,sm8650-clk-virt
+ - qcom,sm8650-mc-virt
+ then:
+ properties:
+ reg: false
+ else:
+ required:
+ - reg
+
+ - if:
+ properties:
+ compatible:
+ contains:
+ enum:
+ - qcom,sm8650-pcie-anoc
+ then:
+ properties:
+ clocks:
+ items:
+ - description: aggre-NOC PCIe AXI clock
+ - description: cfg-NOC PCIe a-NOC AHB clock
+
+ - if:
+ properties:
+ compatible:
+ contains:
+ enum:
+ - qcom,sm8650-aggre1-noc
+ then:
+ properties:
+ clocks:
+ items:
+ - description: aggre UFS PHY AXI clock
+ - description: aggre USB3 PRIM AXI clock
+
+ - if:
+ properties:
+ compatible:
+ contains:
+ enum:
+ - qcom,sm8650-aggre2-noc
+ then:
+ properties:
+ clocks:
+ items:
+ - description: RPMH CC IPA clock
+
+ - if:
+ properties:
+ compatible:
+ contains:
+ enum:
+ - qcom,sm8650-aggre1-noc
+ - qcom,sm8650-aggre2-noc
+ - qcom,sm8650-pcie-anoc
+ then:
+ required:
+ - clocks
+ else:
+ properties:
+ clocks: false
+
+unevaluatedProperties: false
+
+examples:
+ - |
+ clk_virt: interconnect-0 {
+ compatible = "qcom,sm8650-clk-virt";
+ #interconnect-cells = <2>;
+ qcom,bcm-voters = <&apps_bcm_voter>;
+ };
+
+ aggre1_noc: interconnect@16e0000 {
+ compatible = "qcom,sm8650-aggre1-noc";
+ reg = <0x016e0000 0x14400>;
+ #interconnect-cells = <2>;
+ clocks = <&gcc_phy_axi_clk>, <&gcc_prim_axi_clk>;
+ qcom,bcm-voters = <&apps_bcm_voter>;
+ };
diff --git a/dts/upstream/Bindings/interconnect/qcom,x1e80100-rpmh.yaml b/dts/upstream/Bindings/interconnect/qcom,x1e80100-rpmh.yaml
new file mode 100644
index 0000000..08b0210
--- /dev/null
+++ b/dts/upstream/Bindings/interconnect/qcom,x1e80100-rpmh.yaml
@@ -0,0 +1,83 @@
+# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/interconnect/qcom,x1e80100-rpmh.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Qualcomm RPMh Network-On-Chip Interconnect on X1E80100
+
+maintainers:
+ - Rajendra Nayak <quic_rjendra@quicinc.com>
+ - Abel Vesa <abel.vesa@linaro.org>
+
+description: |
+ RPMh interconnect providers support system bandwidth requirements through
+ RPMh hardware accelerators known as Bus Clock Manager (BCM). The provider is
+ able to communicate with the BCM through the Resource State Coordinator (RSC)
+ associated with each execution environment. Provider nodes must point to at
+ least one RPMh device child node pertaining to their RSC and each provider
+ can map to multiple RPMh resources.
+
+ See also:: include/dt-bindings/interconnect/qcom,x1e80100-rpmh.h
+
+properties:
+ compatible:
+ enum:
+ - qcom,x1e80100-aggre1-noc
+ - qcom,x1e80100-aggre2-noc
+ - qcom,x1e80100-clk-virt
+ - qcom,x1e80100-cnoc-cfg
+ - qcom,x1e80100-cnoc-main
+ - qcom,x1e80100-gem-noc
+ - qcom,x1e80100-lpass-ag-noc
+ - qcom,x1e80100-lpass-lpiaon-noc
+ - qcom,x1e80100-lpass-lpicx-noc
+ - qcom,x1e80100-mc-virt
+ - qcom,x1e80100-mmss-noc
+ - qcom,x1e80100-nsp-noc
+ - qcom,x1e80100-pcie-center-anoc
+ - qcom,x1e80100-pcie-north-anoc
+ - qcom,x1e80100-pcie-south-anoc
+ - qcom,x1e80100-system-noc
+ - qcom,x1e80100-usb-center-anoc
+ - qcom,x1e80100-usb-north-anoc
+ - qcom,x1e80100-usb-south-anoc
+
+ reg:
+ maxItems: 1
+
+required:
+ - compatible
+
+allOf:
+ - $ref: qcom,rpmh-common.yaml#
+ - if:
+ properties:
+ compatible:
+ contains:
+ enum:
+ - qcom,x1e80100-clk-virt
+ - qcom,x1e80100-mc-virt
+ then:
+ properties:
+ reg: false
+ else:
+ required:
+ - reg
+
+unevaluatedProperties: false
+
+examples:
+ - |
+ clk_virt: interconnect-0 {
+ compatible = "qcom,x1e80100-clk-virt";
+ #interconnect-cells = <2>;
+ qcom,bcm-voters = <&apps_bcm_voter>;
+ };
+
+ aggre1_noc: interconnect@16e0000 {
+ compatible = "qcom,x1e80100-aggre1-noc";
+ reg = <0x016e0000 0x14400>;
+ #interconnect-cells = <2>;
+ qcom,bcm-voters = <&apps_bcm_voter>;
+ };
diff --git a/dts/upstream/Bindings/interrupt-controller/loongson,liointc.yaml b/dts/upstream/Bindings/interrupt-controller/loongson,liointc.yaml
index 00b570c..60441f0 100644
--- a/dts/upstream/Bindings/interrupt-controller/loongson,liointc.yaml
+++ b/dts/upstream/Bindings/interrupt-controller/loongson,liointc.yaml
@@ -11,8 +11,13 @@
description: |
This interrupt controller is found in the Loongson-3 family of chips and
- Loongson-2K1000 chip, as the primary package interrupt controller which
+ Loongson-2K series chips, as the primary package interrupt controller which
can route local I/O interrupt to interrupt lines of cores.
+ Be aware of the following points.
+ 1.The Loongson-2K0500 is a single core CPU;
+ 2.The Loongson-2K0500/2K1000 has 64 device interrupt sources as inputs, so we
+ need to define two nodes in dts{i} to describe the "0-31" and "32-61" interrupt
+ sources respectively.
allOf:
- $ref: /schemas/interrupt-controller.yaml#
@@ -33,6 +38,7 @@
- const: main
- const: isr0
- const: isr1
+ minItems: 2
interrupt-controller: true
@@ -45,11 +51,9 @@
interrupt-names:
description: List of names for the parent interrupts.
items:
- - const: int0
- - const: int1
- - const: int2
- - const: int3
+ pattern: int[0-3]
minItems: 1
+ maxItems: 4
'#interrupt-cells':
const: 2
@@ -69,6 +73,7 @@
- compatible
- reg
- interrupts
+ - interrupt-names
- interrupt-controller
- '#interrupt-cells'
- loongson,parent_int_map
@@ -86,7 +91,8 @@
then:
properties:
reg:
- minItems: 3
+ minItems: 2
+ maxItems: 3
required:
- reg-names
diff --git a/dts/upstream/Bindings/interrupt-controller/qcom,mpm.yaml b/dts/upstream/Bindings/interrupt-controller/qcom,mpm.yaml
index 6a20611..ebb40c4 100644
--- a/dts/upstream/Bindings/interrupt-controller/qcom,mpm.yaml
+++ b/dts/upstream/Bindings/interrupt-controller/qcom,mpm.yaml
@@ -29,6 +29,12 @@
maxItems: 1
description:
Specifies the base address and size of vMPM registers in RPM MSG RAM.
+ deprecated: true
+
+ qcom,rpm-msg-ram:
+ $ref: /schemas/types.yaml#/definitions/phandle
+ description:
+ Phandle to the APSS MPM slice of the RPM Message RAM
interrupts:
maxItems: 1
@@ -67,34 +73,46 @@
required:
- compatible
- - reg
- interrupts
- mboxes
- interrupt-controller
- '#interrupt-cells'
- qcom,mpm-pin-count
- qcom,mpm-pin-map
+ - qcom,rpm-msg-ram
additionalProperties: false
examples:
- |
#include <dt-bindings/interrupt-controller/arm-gic.h>
- mpm: interrupt-controller@45f01b8 {
- compatible = "qcom,mpm";
- interrupts = <GIC_SPI 197 IRQ_TYPE_EDGE_RISING>;
- reg = <0x45f01b8 0x1000>;
- mboxes = <&apcs_glb 1>;
- interrupt-controller;
- #interrupt-cells = <2>;
- interrupt-parent = <&intc>;
- qcom,mpm-pin-count = <96>;
- qcom,mpm-pin-map = <2 275>,
- <5 296>,
- <12 422>,
- <24 79>,
- <86 183>,
- <90 260>,
- <91 260>;
- #power-domain-cells = <0>;
+
+ remoteproc-rpm {
+ compatible = "qcom,msm8998-rpm-proc", "qcom,rpm-proc";
+
+ glink-edge {
+ compatible = "qcom,glink-rpm";
+
+ interrupts = <GIC_SPI 168 IRQ_TYPE_EDGE_RISING>;
+ qcom,rpm-msg-ram = <&rpm_msg_ram>;
+ mboxes = <&apcs_glb 0>;
+ };
+
+ mpm: interrupt-controller {
+ compatible = "qcom,mpm";
+ qcom,rpm-msg-ram = <&apss_mpm>;
+ interrupts = <GIC_SPI 197 IRQ_TYPE_EDGE_RISING>;
+ mboxes = <&apcs_glb 1>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ interrupt-parent = <&intc>;
+ qcom,mpm-pin-count = <96>;
+ qcom,mpm-pin-map = <2 275>,
+ <5 296>,
+ <12 422>,
+ <24 79>,
+ <86 183>,
+ <91 260>;
+ #power-domain-cells = <0>;
+ };
};
diff --git a/dts/upstream/Bindings/interrupt-controller/qcom,pdc.yaml b/dts/upstream/Bindings/interrupt-controller/qcom,pdc.yaml
index 86d6189..4bdc832 100644
--- a/dts/upstream/Bindings/interrupt-controller/qcom,pdc.yaml
+++ b/dts/upstream/Bindings/interrupt-controller/qcom,pdc.yaml
@@ -35,12 +35,16 @@
- qcom,sdm845-pdc
- qcom,sdx55-pdc
- qcom,sdx65-pdc
+ - qcom,sdx75-pdc
- qcom,sm4450-pdc
- qcom,sm6350-pdc
- qcom,sm8150-pdc
- qcom,sm8250-pdc
- qcom,sm8350-pdc
- qcom,sm8450-pdc
+ - qcom,sm8550-pdc
+ - qcom,sm8650-pdc
+ - qcom,x1e80100-pdc
- const: qcom,pdc
reg:
diff --git a/dts/upstream/Bindings/interrupt-controller/renesas,rzg2l-irqc.yaml b/dts/upstream/Bindings/interrupt-controller/renesas,rzg2l-irqc.yaml
index 2ef3081..d3b5aec 100644
--- a/dts/upstream/Bindings/interrupt-controller/renesas,rzg2l-irqc.yaml
+++ b/dts/upstream/Bindings/interrupt-controller/renesas,rzg2l-irqc.yaml
@@ -26,6 +26,7 @@
- renesas,r9a07g043u-irqc # RZ/G2UL
- renesas,r9a07g044-irqc # RZ/G2{L,LC}
- renesas,r9a07g054-irqc # RZ/V2L
+ - renesas,r9a08g045-irqc # RZ/G3S
- const: renesas,rzg2l-irqc
'#interrupt-cells':
@@ -167,7 +168,9 @@
properties:
compatible:
contains:
- const: renesas,r9a07g043u-irqc
+ enum:
+ - renesas,r9a07g043u-irqc
+ - renesas,r9a08g045-irqc
then:
properties:
interrupts:
diff --git a/dts/upstream/Bindings/interrupt-controller/sifive,plic-1.0.0.yaml b/dts/upstream/Bindings/interrupt-controller/sifive,plic-1.0.0.yaml
index 0c07e8d..709b221 100644
--- a/dts/upstream/Bindings/interrupt-controller/sifive,plic-1.0.0.yaml
+++ b/dts/upstream/Bindings/interrupt-controller/sifive,plic-1.0.0.yaml
@@ -66,6 +66,7 @@
- enum:
- allwinner,sun20i-d1-plic
- sophgo,cv1800b-plic
+ - sophgo,cv1812h-plic
- sophgo,sg2042-plic
- thead,th1520-plic
- const: thead,c900-plic
diff --git a/dts/upstream/Bindings/interrupt-controller/st,stih407-irq-syscfg.yaml b/dts/upstream/Bindings/interrupt-controller/st,stih407-irq-syscfg.yaml
index 2b153d7..e44e4e5 100644
--- a/dts/upstream/Bindings/interrupt-controller/st,stih407-irq-syscfg.yaml
+++ b/dts/upstream/Bindings/interrupt-controller/st,stih407-irq-syscfg.yaml
@@ -55,8 +55,8 @@
- |
#include <dt-bindings/interrupt-controller/irq-st.h>
irq-syscfg {
- compatible = "st,stih407-irq-syscfg";
- st,syscfg = <&syscfg_cpu>;
+ compatible = "st,stih407-irq-syscfg";
+ st,syscfg = <&syscfg_cpu>;
st,irq-device = <ST_IRQ_SYSCFG_PMU_0>,
<ST_IRQ_SYSCFG_PMU_1>;
st,fiq-device = <ST_IRQ_SYSCFG_DISABLED>,
diff --git a/dts/upstream/Bindings/iommu/apple,dart.yaml b/dts/upstream/Bindings/iommu/apple,dart.yaml
index 903edf8..7adb1de 100644
--- a/dts/upstream/Bindings/iommu/apple,dart.yaml
+++ b/dts/upstream/Bindings/iommu/apple,dart.yaml
@@ -24,6 +24,7 @@
compatible:
enum:
- apple,t8103-dart
+ - apple,t8103-usb4-dart
- apple,t8110-dart
- apple,t6000-dart
diff --git a/dts/upstream/Bindings/iommu/arm,smmu.yaml b/dts/upstream/Bindings/iommu/arm,smmu.yaml
index aa9e1c0..a4042ae 100644
--- a/dts/upstream/Bindings/iommu/arm,smmu.yaml
+++ b/dts/upstream/Bindings/iommu/arm,smmu.yaml
@@ -56,6 +56,8 @@
- qcom,sm8350-smmu-500
- qcom,sm8450-smmu-500
- qcom,sm8550-smmu-500
+ - qcom,sm8650-smmu-500
+ - qcom,x1e80100-smmu-500
- const: qcom,smmu-500
- const: arm,mmu-500
@@ -89,6 +91,8 @@
- qcom,sm8150-smmu-500
- qcom,sm8250-smmu-500
- qcom,sm8350-smmu-500
+ - qcom,sm8450-smmu-500
+ - qcom,sm8550-smmu-500
- const: qcom,adreno-smmu
- const: qcom,smmu-500
- const: arm,mmu-500
@@ -434,6 +438,30 @@
compatible:
items:
- enum:
+ - qcom,sm8350-smmu-500
+ - const: qcom,adreno-smmu
+ - const: qcom,smmu-500
+ - const: arm,mmu-500
+ then:
+ properties:
+ clock-names:
+ items:
+ - const: bus
+ - const: iface
+ - const: ahb
+ - const: hlos1_vote_gpu_smmu
+ - const: cx_gmu
+ - const: hub_cx_int
+ - const: hub_aon
+ clocks:
+ minItems: 7
+ maxItems: 7
+
+ - if:
+ properties:
+ compatible:
+ items:
+ - enum:
- qcom,sm6115-smmu-500
- qcom,sm6125-smmu-500
- const: qcom,adreno-smmu
@@ -453,6 +481,50 @@
- description: Voter clock required for HLOS SMMU access
- description: Interface clock required for register access
+ - if:
+ properties:
+ compatible:
+ const: qcom,sm8450-smmu-500
+ then:
+ properties:
+ clock-names:
+ items:
+ - const: gmu
+ - const: hub
+ - const: hlos
+ - const: bus
+ - const: iface
+ - const: ahb
+
+ clocks:
+ items:
+ - description: GMU clock
+ - description: GPU HUB clock
+ - description: HLOS vote clock
+ - description: GPU memory bus clock
+ - description: GPU SNoC bus clock
+ - description: GPU AHB clock
+
+ - if:
+ properties:
+ compatible:
+ const: qcom,sm8550-smmu-500
+ then:
+ properties:
+ clock-names:
+ items:
+ - const: hlos
+ - const: bus
+ - const: iface
+ - const: ahb
+
+ clocks:
+ items:
+ - description: HLOS vote clock
+ - description: GPU memory bus clock
+ - description: GPU SNoC bus clock
+ - description: GPU AHB clock
+
# Disallow clocks for all other platforms with specific compatibles
- if:
properties:
@@ -472,9 +544,8 @@
- qcom,sdx65-smmu-500
- qcom,sm6350-smmu-500
- qcom,sm6375-smmu-500
- - qcom,sm8350-smmu-500
- - qcom,sm8450-smmu-500
- - qcom,sm8550-smmu-500
+ - qcom,sm8650-smmu-500
+ - qcom,x1e80100-smmu-500
then:
properties:
clock-names: false
diff --git a/dts/upstream/Bindings/iommu/rockchip,iommu.yaml b/dts/upstream/Bindings/iommu/rockchip,iommu.yaml
index ba9124f..621dde0 100644
--- a/dts/upstream/Bindings/iommu/rockchip,iommu.yaml
+++ b/dts/upstream/Bindings/iommu/rockchip,iommu.yaml
@@ -19,9 +19,14 @@
properties:
compatible:
- enum:
- - rockchip,iommu
- - rockchip,rk3568-iommu
+ oneOf:
+ - enum:
+ - rockchip,iommu
+ - rockchip,rk3568-iommu
+ - items:
+ - enum:
+ - rockchip,rk3588-iommu
+ - const: rockchip,rk3568-iommu
reg:
items:
diff --git a/dts/upstream/Bindings/leds/allwinner,sun50i-a100-ledc.yaml b/dts/upstream/Bindings/leds/allwinner,sun50i-a100-ledc.yaml
new file mode 100644
index 0000000..760cb33
--- /dev/null
+++ b/dts/upstream/Bindings/leds/allwinner,sun50i-a100-ledc.yaml
@@ -0,0 +1,137 @@
+# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/leds/allwinner,sun50i-a100-ledc.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Allwinner A100 LED Controller
+
+maintainers:
+ - Samuel Holland <samuel@sholland.org>
+
+description:
+ The LED controller found in Allwinner sunxi SoCs uses a one-wire serial
+ interface to drive up to 1024 RGB LEDs.
+
+properties:
+ compatible:
+ oneOf:
+ - const: allwinner,sun50i-a100-ledc
+ - items:
+ - enum:
+ - allwinner,sun20i-d1-ledc
+ - allwinner,sun50i-r329-ledc
+ - const: allwinner,sun50i-a100-ledc
+
+ reg:
+ maxItems: 1
+
+ "#address-cells":
+ const: 1
+
+ "#size-cells":
+ const: 0
+
+ interrupts:
+ maxItems: 1
+
+ clocks:
+ items:
+ - description: Bus clock
+ - description: Module clock
+
+ clock-names:
+ items:
+ - const: bus
+ - const: mod
+
+ resets:
+ maxItems: 1
+
+ dmas:
+ maxItems: 1
+ description: TX DMA channel
+
+ dma-names:
+ const: tx
+
+ allwinner,pixel-format:
+ description: Pixel format (subpixel transmission order), default is "grb"
+ enum:
+ - bgr
+ - brg
+ - gbr
+ - grb
+ - rbg
+ - rgb
+
+ allwinner,t0h-ns:
+ default: 336
+ description: Length of high pulse when transmitting a "0" bit
+
+ allwinner,t0l-ns:
+ default: 840
+ description: Length of low pulse when transmitting a "0" bit
+
+ allwinner,t1h-ns:
+ default: 882
+ description: Length of high pulse when transmitting a "1" bit
+
+ allwinner,t1l-ns:
+ default: 294
+ description: Length of low pulse when transmitting a "1" bit
+
+ allwinner,treset-ns:
+ default: 300000
+ description: Minimum delay between transmission frames
+
+patternProperties:
+ "^multi-led@[0-9a-f]+$":
+ type: object
+ $ref: leds-class-multicolor.yaml#
+ unevaluatedProperties: false
+ properties:
+ reg:
+ minimum: 0
+ maximum: 1023
+ description: Index of the LED in the series (must be contiguous)
+
+ required:
+ - reg
+
+required:
+ - compatible
+ - reg
+ - interrupts
+ - clocks
+ - clock-names
+ - resets
+
+additionalProperties: false
+
+examples:
+ - |
+ #include <dt-bindings/interrupt-controller/irq.h>
+ #include <dt-bindings/leds/common.h>
+
+ ledc: led-controller@2008000 {
+ compatible = "allwinner,sun20i-d1-ledc",
+ "allwinner,sun50i-a100-ledc";
+ reg = <0x2008000 0x400>;
+ interrupts = <36 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&ccu 12>, <&ccu 34>;
+ clock-names = "bus", "mod";
+ resets = <&ccu 12>;
+ dmas = <&dma 42>;
+ dma-names = "tx";
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ multi-led@0 {
+ reg = <0x0>;
+ color = <LED_COLOR_ID_RGB>;
+ function = LED_FUNCTION_INDICATOR;
+ };
+ };
+
+...
diff --git a/dts/upstream/Bindings/leds/awinic,aw200xx.yaml b/dts/upstream/Bindings/leds/awinic,aw200xx.yaml
index feb5feb..54d6d1f 100644
--- a/dts/upstream/Bindings/leds/awinic,aw200xx.yaml
+++ b/dts/upstream/Bindings/leds/awinic,aw200xx.yaml
@@ -10,15 +10,19 @@
- Martin Kurbanov <mmkurbanov@sberdevices.ru>
description: |
- This controller is present on AW20036/AW20054/AW20072.
- It is a 3x12/6x9/6x12 matrix LED programmed via
- an I2C interface, up to 36/54/72 LEDs or 12/18/24 RGBs,
- 3 pattern controllers for auto breathing or group dimming control.
+ It is a matrix LED driver programmed via an I2C interface. Devices have
+ a set of individually controlled leds and support 3 pattern controllers
+ for auto breathing or group dimming control. Supported devices:
+ - AW20036 (3x12) 36 LEDs
+ - AW20054 (6x9) 54 LEDs
+ - AW20072 (6x12) 72 LEDs
+ - AW20108 (9x12) 108 LEDs
For more product information please see the link below:
aw20036 - https://www.awinic.com/en/productDetail/AW20036QNR#tech-docs
aw20054 - https://www.awinic.com/en/productDetail/AW20054QNR#tech-docs
aw20072 - https://www.awinic.com/en/productDetail/AW20072QNR#tech-docs
+ aw20108 - https://www.awinic.com/en/productDetail/AW20108QNR#tech-docs
properties:
compatible:
@@ -26,6 +30,7 @@
- awinic,aw20036
- awinic,aw20054
- awinic,aw20072
+ - awinic,aw20108
reg:
maxItems: 1
@@ -36,13 +41,11 @@
"#size-cells":
const: 0
- awinic,display-rows:
- $ref: /schemas/types.yaml#/definitions/uint32
- description:
- Leds matrix size
+ enable-gpios:
+ maxItems: 1
patternProperties:
- "^led@[0-9a-f]$":
+ "^led@[0-9a-f]+$":
type: object
$ref: common.yaml#
unevaluatedProperties: false
@@ -60,16 +63,11 @@
since the chip has a single global setting.
The maximum output current of each LED is calculated by the
following formula:
- IMAXled = 160000 * (592 / 600.5) * (1 / display-rows)
+ IMAXled = 160000 * (592 / 600.5) * (1 / max-current-switch-number)
And the minimum output current formula:
- IMINled = 3300 * (592 / 600.5) * (1 / display-rows)
-
-required:
- - compatible
- - reg
- - "#address-cells"
- - "#size-cells"
- - awinic,display-rows
+ IMINled = 3300 * (592 / 600.5) * (1 / max-current-switch-number)
+ where max-current-switch-number is determinated by led configuration
+ and depends on how leds are physically connected to the led driver.
allOf:
- if:
@@ -78,18 +76,67 @@
contains:
const: awinic,aw20036
then:
+ patternProperties:
+ "^led@[0-9a-f]+$":
+ properties:
+ reg:
+ items:
+ minimum: 0
+ maximum: 36
+
+ - if:
properties:
- awinic,display-rows:
- enum: [1, 2, 3]
- else:
+ compatible:
+ contains:
+ const: awinic,aw20054
+ then:
+ patternProperties:
+ "^led@[0-9a-f]+$":
+ properties:
+ reg:
+ items:
+ minimum: 0
+ maximum: 54
+
+ - if:
properties:
- awinic,display-rows:
- enum: [1, 2, 3, 4, 5, 6, 7]
+ compatible:
+ contains:
+ const: awinic,aw20072
+ then:
+ patternProperties:
+ "^led@[0-9a-f]+$":
+ properties:
+ reg:
+ items:
+ minimum: 0
+ maximum: 72
+
+ - if:
+ properties:
+ compatible:
+ contains:
+ const: awinic,aw20108
+ then:
+ patternProperties:
+ "^led@[0-9a-f]+$":
+ properties:
+ reg:
+ items:
+ minimum: 0
+ maximum: 108
+
+required:
+ - compatible
+ - reg
+ - "#address-cells"
+ - "#size-cells"
additionalProperties: false
examples:
- |
+ #include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/leds/common.h>
i2c {
@@ -101,7 +148,7 @@
reg = <0x3a>;
#address-cells = <1>;
#size-cells = <0>;
- awinic,display-rows = <3>;
+ enable-gpios = <&gpio 3 GPIO_ACTIVE_HIGH>;
led@0 {
reg = <0x0>;
diff --git a/dts/upstream/Bindings/leds/backlight/mps,mp3309c.yaml b/dts/upstream/Bindings/leds/backlight/mps,mp3309c.yaml
index 4191e33..527a373 100644
--- a/dts/upstream/Bindings/leds/backlight/mps,mp3309c.yaml
+++ b/dts/upstream/Bindings/leds/backlight/mps,mp3309c.yaml
@@ -14,8 +14,8 @@
programmable switching frequency to optimize efficiency.
It supports two different dimming modes:
- - analog mode, via I2C commands (default)
- - PWM controlled mode.
+ - analog mode, via I2C commands, as default mode (32 dimming levels)
+ - PWM controlled mode (optional)
The datasheet is available at:
https://www.monolithicpower.com/en/mp3309c.html
@@ -50,8 +50,6 @@
required:
- compatible
- reg
- - max-brightness
- - default-brightness
unevaluatedProperties: false
@@ -66,8 +64,8 @@
compatible = "mps,mp3309c";
reg = <0x17>;
pwms = <&pwm1 0 3333333 0>; /* 300 Hz --> (1/f) * 1*10^9 */
- max-brightness = <100>;
- default-brightness = <80>;
+ brightness-levels = <0 4 8 16 32 64 128 255>;
+ default-brightness = <6>;
mps,overvoltage-protection-microvolt = <24000000>;
};
};
diff --git a/dts/upstream/Bindings/leds/common.yaml b/dts/upstream/Bindings/leds/common.yaml
index c8d0ba5..55a8d13 100644
--- a/dts/upstream/Bindings/leds/common.yaml
+++ b/dts/upstream/Bindings/leds/common.yaml
@@ -167,7 +167,7 @@
Note that this flag is mainly used for PWM-LEDs, where it is not possible
to map brightness to current. Drivers for other controllers should use
led-max-microamp.
- $ref: /schemas/types.yaml#definitions/uint32
+ $ref: /schemas/types.yaml#/definitions/uint32
panic-indicator:
description:
diff --git a/dts/upstream/Bindings/leds/qcom,spmi-flash-led.yaml b/dts/upstream/Bindings/leds/qcom,spmi-flash-led.yaml
index a8736fd..1ba6076 100644
--- a/dts/upstream/Bindings/leds/qcom,spmi-flash-led.yaml
+++ b/dts/upstream/Bindings/leds/qcom,spmi-flash-led.yaml
@@ -89,9 +89,11 @@
examples:
- |
#include <dt-bindings/leds/common.h>
- spmi {
+
+ pmic {
#address-cells = <1>;
#size-cells = <0>;
+
led-controller@ee00 {
compatible = "qcom,pm8350c-flash-led", "qcom,spmi-flash-led";
reg = <0xee00>;
diff --git a/dts/upstream/Bindings/loongarch/cpus.yaml b/dts/upstream/Bindings/loongarch/cpus.yaml
new file mode 100644
index 0000000..f175872
--- /dev/null
+++ b/dts/upstream/Bindings/loongarch/cpus.yaml
@@ -0,0 +1,61 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/loongarch/cpus.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: LoongArch CPUs
+
+maintainers:
+ - Binbin Zhou <zhoubinbin@loongson.cn>
+
+description:
+ This document describes the list of LoongArch CPU cores that support FDT,
+ it describe the layout of CPUs in a system through the "cpus" node.
+
+allOf:
+ - $ref: /schemas/cpu.yaml#
+
+properties:
+ compatible:
+ enum:
+ - loongson,la264
+ - loongson,la364
+
+ reg:
+ maxItems: 1
+
+ clocks:
+ maxItems: 1
+
+required:
+ - compatible
+ - reg
+ - clocks
+
+unevaluatedProperties: false
+
+examples:
+ - |
+ #include <dt-bindings/clock/loongson,ls2k-clk.h>
+
+ cpus {
+ #size-cells = <0>;
+ #address-cells = <1>;
+
+ cpu@0 {
+ compatible = "loongson,la264";
+ device_type = "cpu";
+ reg = <0>;
+ clocks = <&clk LOONGSON2_NODE_CLK>;
+ };
+
+ cpu@1 {
+ compatible = "loongson,la264";
+ device_type = "cpu";
+ reg = <1>;
+ clocks = <&clk LOONGSON2_NODE_CLK>;
+ };
+ };
+
+...
diff --git a/dts/upstream/Bindings/loongarch/loongson.yaml b/dts/upstream/Bindings/loongarch/loongson.yaml
new file mode 100644
index 0000000..e1a4a97
--- /dev/null
+++ b/dts/upstream/Bindings/loongarch/loongson.yaml
@@ -0,0 +1,34 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/loongarch/loongson.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Loongson SoC-based boards
+
+maintainers:
+ - Binbin Zhou <zhoubinbin@loongson.cn>
+
+properties:
+ $nodename:
+ const: '/'
+ compatible:
+ oneOf:
+ - description: Loongson-2K0500 processor based boards
+ items:
+ - const: loongson,ls2k0500-ref
+ - const: loongson,ls2k0500
+
+ - description: Loongson-2K1000 processor based boards
+ items:
+ - const: loongson,ls2k1000-ref
+ - const: loongson,ls2k1000
+
+ - description: Loongson-2K2000 processor based boards
+ items:
+ - const: loongson,ls2k2000-ref
+ - const: loongson,ls2k2000
+
+additionalProperties: true
+
+...
diff --git a/dts/upstream/Bindings/mailbox/qcom,apcs-kpss-global.yaml b/dts/upstream/Bindings/mailbox/qcom,apcs-kpss-global.yaml
index a38413f..79eb523 100644
--- a/dts/upstream/Bindings/mailbox/qcom,apcs-kpss-global.yaml
+++ b/dts/upstream/Bindings/mailbox/qcom,apcs-kpss-global.yaml
@@ -25,6 +25,24 @@
- const: qcom,ipq6018-apcs-apps-global
- items:
- enum:
+ - qcom,qcs404-apcs-apps-global
+ - const: qcom,msm8916-apcs-kpss-global
+ - const: syscon
+ - items:
+ - enum:
+ - qcom,msm8976-apcs-kpss-global
+ - const: qcom,msm8994-apcs-kpss-global
+ - const: syscon
+ - items:
+ - enum:
+ - qcom,msm8998-apcs-hmss-global
+ - qcom,sdm660-apcs-hmss-global
+ - qcom,sm4250-apcs-hmss-global
+ - qcom,sm6115-apcs-hmss-global
+ - qcom,sm6125-apcs-hmss-global
+ - const: qcom,msm8994-apcs-kpss-global
+ - items:
+ - enum:
- qcom,sc7180-apss-shared
- qcom,sc8180x-apss-shared
- qcom,sm8150-apss-shared
@@ -34,22 +52,14 @@
- qcom,msm8916-apcs-kpss-global
- qcom,msm8939-apcs-kpss-global
- qcom,msm8953-apcs-kpss-global
- - qcom,msm8976-apcs-kpss-global
- qcom,msm8994-apcs-kpss-global
- - qcom,qcs404-apcs-apps-global
- qcom,sdx55-apcs-gcc
- const: syscon
- enum:
- qcom,ipq6018-apcs-apps-global
- - qcom,ipq8074-apcs-apps-global
- qcom,msm8996-apcs-hmss-global
- - qcom,msm8998-apcs-hmss-global
- qcom,qcm2290-apcs-hmss-global
- - qcom,sdm660-apcs-hmss-global
- qcom,sdm845-apss-shared
- - qcom,sm4250-apcs-hmss-global
- - qcom,sm6115-apcs-hmss-global
- - qcom,sm6125-apcs-hmss-global
reg:
maxItems: 1
@@ -80,20 +90,38 @@
- if:
properties:
compatible:
- enum:
- - qcom,msm8916-apcs-kpss-global
- - qcom,msm8939-apcs-kpss-global
- - qcom,qcs404-apcs-apps-global
+ contains:
+ enum:
+ - qcom,msm8916-apcs-kpss-global
+ then:
+ properties:
+ clocks:
+ items:
+ - description: primary pll parent of the clock driver
+ - description: auxiliary parent
+ clock-names:
+ items:
+ - const: pll
+ - const: aux
+
+ - if:
+ properties:
+ compatible:
+ contains:
+ enum:
+ - qcom,msm8939-apcs-kpss-global
then:
properties:
clocks:
items:
- description: primary pll parent of the clock driver
- description: auxiliary parent
+ - description: reference clock
clock-names:
items:
- const: pll
- const: aux
+ - const: ref
- if:
properties:
@@ -113,6 +141,7 @@
- const: ref
- const: pll
- const: aux
+
- if:
properties:
compatible:
@@ -137,16 +166,10 @@
compatible:
enum:
- qcom,msm8953-apcs-kpss-global
- - qcom,msm8976-apcs-kpss-global
- qcom,msm8994-apcs-kpss-global
- qcom,msm8996-apcs-hmss-global
- - qcom,msm8998-apcs-hmss-global
- qcom,qcm2290-apcs-hmss-global
- - qcom,sdm660-apcs-hmss-global
- qcom,sdm845-apss-shared
- - qcom,sm4250-apcs-hmss-global
- - qcom,sm6115-apcs-hmss-global
- - qcom,sm6125-apcs-hmss-global
then:
properties:
clocks: false
@@ -192,7 +215,8 @@
#define GCC_APSS_AHB_CLK_SRC 1
#define GCC_GPLL0_AO_OUT_MAIN 123
apcs: mailbox@b011000 {
- compatible = "qcom,qcs404-apcs-apps-global", "syscon";
+ compatible = "qcom,qcs404-apcs-apps-global",
+ "qcom,msm8916-apcs-kpss-global", "syscon";
reg = <0x0b011000 0x1000>;
#mbox-cells = <1>;
clocks = <&apcs_hfpll>, <&gcc GCC_GPLL0_AO_OUT_MAIN>;
diff --git a/dts/upstream/Bindings/mailbox/qcom-ipcc.yaml b/dts/upstream/Bindings/mailbox/qcom-ipcc.yaml
index a35f948..8f00486 100644
--- a/dts/upstream/Bindings/mailbox/qcom-ipcc.yaml
+++ b/dts/upstream/Bindings/mailbox/qcom-ipcc.yaml
@@ -35,6 +35,7 @@
- qcom,sm8450-ipcc
- qcom,sm8550-ipcc
- qcom,sm8650-ipcc
+ - qcom,x1e80100-ipcc
- const: qcom,ipcc
reg:
diff --git a/dts/upstream/Bindings/mailbox/xlnx,zynqmp-ipi-mailbox.yaml b/dts/upstream/Bindings/mailbox/xlnx,zynqmp-ipi-mailbox.yaml
index 8b15a05..fe83b5c 100644
--- a/dts/upstream/Bindings/mailbox/xlnx,zynqmp-ipi-mailbox.yaml
+++ b/dts/upstream/Bindings/mailbox/xlnx,zynqmp-ipi-mailbox.yaml
@@ -37,7 +37,9 @@
properties:
compatible:
- const: xlnx,zynqmp-ipi-mailbox
+ enum:
+ - xlnx,zynqmp-ipi-mailbox
+ - xlnx,versal-ipi-mailbox
method:
description: |
@@ -58,6 +60,12 @@
'#size-cells':
const: 2
+ reg:
+ maxItems: 2
+
+ reg-names:
+ maxItems: 2
+
xlnx,ipi-id:
description: |
Remote Xilinx IPI agent ID of which the mailbox is connected to.
@@ -76,7 +84,17 @@
properties:
compatible:
- const: xlnx,zynqmp-ipi-dest-mailbox
+ enum:
+ - xlnx,zynqmp-ipi-dest-mailbox
+ - xlnx,versal-ipi-dest-mailbox
+
+ reg:
+ minItems: 1
+ maxItems: 4
+
+ reg-names:
+ minItems: 1
+ maxItems: 4
xlnx,ipi-id:
description:
@@ -88,23 +106,44 @@
description:
It contains tx(0) or rx(1) channel IPI id number.
- reg:
- maxItems: 4
+ allOf:
+ - if:
+ properties:
+ compatible:
+ contains:
+ enum:
+ - xlnx,zynqmp-ipi-dest-mailbox
+ then:
+ properties:
+ reg:
+ maxItems: 4
- reg-names:
- items:
- - const: local_request_region
- - const: local_response_region
- - const: remote_request_region
- - const: remote_response_region
+ reg-names:
+ items:
+ - const: local_request_region
+ - const: local_response_region
+ - const: remote_request_region
+ - const: remote_response_region
+ else:
+ properties:
+ reg:
+ minItems: 1
+ items:
+ - description: Remote IPI agent control register region
+ - description: Remote IPI agent optional message buffers
+
+ reg-names:
+ minItems: 1
+ items:
+ - const: ctrl
+ - const: msg
required:
- compatible
- reg
- reg-names
- "#mbox-cells"
-
-additionalProperties: false
+ - xlnx,ipi-id
required:
- compatible
@@ -113,6 +152,36 @@
- '#size-cells'
- xlnx,ipi-id
+allOf:
+ - if:
+ properties:
+ compatible:
+ contains:
+ enum:
+ - xlnx,zynqmp-ipi-mailbox
+ then:
+ properties:
+ reg: false
+ reg-names: false
+
+ else:
+ properties:
+ reg:
+ items:
+ - description: Host IPI agent control register region
+ - description: Host IPI agent optional message buffers
+
+ reg-names:
+ items:
+ - const: ctrl
+ - const: msg
+
+ required:
+ - reg
+ - reg-names
+
+additionalProperties: false
+
examples:
- |
#include<dt-bindings/interrupt-controller/arm-gic.h>
@@ -144,4 +213,41 @@
};
};
+ - |
+ #include<dt-bindings/interrupt-controller/arm-gic.h>
+
+ bus {
+ #address-cells = <2>;
+ #size-cells = <2>;
+ mailbox@ff300000 {
+ compatible = "xlnx,versal-ipi-mailbox";
+ interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
+ #address-cells = <2>;
+ #size-cells = <2>;
+ reg = <0x0 0xff300000 0x0 0x1000>,
+ <0x0 0xff990000 0x0 0x1ff>;
+ reg-names = "ctrl", "msg";
+ xlnx,ipi-id = <0>;
+ ranges;
+
+ /* buffered IPI */
+ mailbox@ff340000 {
+ compatible = "xlnx,versal-ipi-dest-mailbox";
+ reg = <0x0 0xff340000 0x0 0x1000>,
+ <0x0 0xff990400 0x0 0x1ff>;
+ reg-names = "ctrl", "msg";
+ #mbox-cells = <1>;
+ xlnx,ipi-id = <4>;
+ };
+
+ /* bufferless IPI */
+ mailbox@ff370000 {
+ compatible = "xlnx,versal-ipi-dest-mailbox";
+ reg = <0x0 0xff370000 0x0 0x1000>;
+ reg-names = "ctrl";
+ #mbox-cells = <1>;
+ xlnx,ipi-id = <7>;
+ };
+ };
+ };
...
diff --git a/dts/upstream/Bindings/media/cnm,wave521c.yaml b/dts/upstream/Bindings/media/cnm,wave521c.yaml
new file mode 100644
index 0000000..6a11c1d
--- /dev/null
+++ b/dts/upstream/Bindings/media/cnm,wave521c.yaml
@@ -0,0 +1,61 @@
+# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/media/cnm,wave521c.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Chips&Media Wave 5 Series multi-standard codec IP
+
+maintainers:
+ - Nas Chung <nas.chung@chipsnmedia.com>
+ - Jackson Lee <jackson.lee@chipsnmedia.com>
+
+description:
+ The Chips&Media WAVE codec IP is a multi format video encoder/decoder
+
+properties:
+ compatible:
+ items:
+ - enum:
+ - ti,j721s2-wave521c
+ - const: cnm,wave521c
+
+ reg:
+ maxItems: 1
+
+ clocks:
+ items:
+ - description: VCODEC clock
+
+ interrupts:
+ maxItems: 1
+
+ power-domains:
+ maxItems: 1
+
+ resets:
+ maxItems: 1
+
+ sram:
+ $ref: /schemas/types.yaml#/definitions/phandle
+ description:
+ The VPU uses the SRAM to store some of the reference data instead of
+ storing it on DMA memory. It is mainly used for the purpose of reducing
+ bandwidth.
+
+required:
+ - compatible
+ - reg
+ - clocks
+
+additionalProperties: false
+
+examples:
+ - |
+ vpu: video-codec@12345678 {
+ compatible = "ti,j721s2-wave521c", "cnm,wave521c";
+ reg = <0x12345678 0x1000>;
+ clocks = <&clks 42>;
+ interrupts = <42>;
+ sram = <&sram>;
+ };
diff --git a/dts/upstream/Bindings/media/i2c/alliedvision,alvium-csi2.yaml b/dts/upstream/Bindings/media/i2c/alliedvision,alvium-csi2.yaml
new file mode 100644
index 0000000..d3329e9
--- /dev/null
+++ b/dts/upstream/Bindings/media/i2c/alliedvision,alvium-csi2.yaml
@@ -0,0 +1,81 @@
+# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/media/i2c/alliedvision,alvium-csi2.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Allied Vision Alvium Camera
+
+maintainers:
+ - Tommaso Merciai <tomm.merciai@gmail.com>
+ - Martin Hecht <martin.hecht@avnet.eu>
+
+allOf:
+ - $ref: /schemas/media/video-interface-devices.yaml#
+
+properties:
+ compatible:
+ const: alliedvision,alvium-csi2
+
+ reg:
+ maxItems: 1
+
+ vcc-ext-in-supply:
+ description: |
+ The regulator that supplies power to the VCC_EXT_IN pins.
+
+ port:
+ description: Digital Output Port
+ $ref: /schemas/graph.yaml#/$defs/port-base
+ additionalProperties: false
+
+ properties:
+ endpoint:
+ $ref: /schemas/media/video-interfaces.yaml#
+ unevaluatedProperties: false
+
+ properties:
+ link-frequencies: true
+
+ data-lanes:
+ minItems: 1
+ items:
+ - const: 1
+ - const: 2
+ - const: 3
+ - const: 4
+
+ required:
+ - data-lanes
+ - link-frequencies
+
+required:
+ - compatible
+ - reg
+ - vcc-ext-in-supply
+ - port
+
+additionalProperties: false
+
+examples:
+ - |
+ i2c {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ alvium: camera@3c {
+ compatible = "alliedvision,alvium-csi2";
+ reg = <0x3c>;
+ vcc-ext-in-supply = <®_vcc_ext_in>;
+
+ port {
+ alvium_out: endpoint {
+ remote-endpoint = <&mipi_csi_0_in>;
+ data-lanes = <1 2 3 4>;
+ link-frequencies = /bits/ 64 <681250000>;
+ };
+ };
+ };
+ };
+
+...
diff --git a/dts/upstream/Bindings/media/i2c/asahi-kasei,ak7375.yaml b/dts/upstream/Bindings/media/i2c/asahi-kasei,ak7375.yaml
index 22a810f..fe312cc 100644
--- a/dts/upstream/Bindings/media/i2c/asahi-kasei,ak7375.yaml
+++ b/dts/upstream/Bindings/media/i2c/asahi-kasei,ak7375.yaml
@@ -15,7 +15,9 @@
properties:
compatible:
- const: asahi-kasei,ak7375
+ enum:
+ - asahi-kasei,ak7345
+ - asahi-kasei,ak7375
reg:
maxItems: 1
diff --git a/dts/upstream/Bindings/media/i2c/galaxycore,gc0308.yaml b/dts/upstream/Bindings/media/i2c/galaxycore,gc0308.yaml
new file mode 100644
index 0000000..f81e7da
--- /dev/null
+++ b/dts/upstream/Bindings/media/i2c/galaxycore,gc0308.yaml
@@ -0,0 +1,108 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/media/i2c/galaxycore,gc0308.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Galaxycore GC0308 and GC0309 Image Sensors
+
+maintainers:
+ - Sebastian Reichel <sre@kernel.org>
+
+description: |
+ The GalaxyCore GC0308 (1/6.5") and GC0309 (1/9") are 640x480 VGA sensors
+ programmable through an I2C interface and connected via parallel bus.
+ They include an ISP capable of auto exposure and auto white balance.
+
+allOf:
+ - $ref: ../video-interface-devices.yaml#
+
+properties:
+ compatible:
+ oneOf:
+ - const: galaxycore,gc0308
+ - items:
+ - const: galaxycore,gc0309
+ - const: galaxycore,gc0308
+
+ reg:
+ const: 0x21
+
+ clocks:
+ description: Reference to the xclk clock.
+ maxItems: 1
+
+ reset-gpios:
+ description: GPIO descriptor for the reset pin.
+ maxItems: 1
+
+ powerdown-gpios:
+ description: GPIO descriptor for the powerdown pin.
+ maxItems: 1
+
+ vdd28-supply:
+ description: 2.8V supply
+
+ port:
+ $ref: /schemas/graph.yaml#/$defs/port-base
+ description: |
+ Video output port.
+
+ properties:
+ endpoint:
+ $ref: /schemas/media/video-interfaces.yaml#
+ unevaluatedProperties: false
+
+ properties:
+ bus-width: true
+ data-shift: true
+ hsync-active: true
+ vsync-active: true
+ data-active: true
+ pclk-sample: true
+
+ required:
+ - bus-width
+
+ additionalProperties: false
+
+required:
+ - compatible
+ - reg
+ - clocks
+ - powerdown-gpios
+ - port
+
+additionalProperties: false
+
+examples:
+ - |
+ #include <dt-bindings/gpio/gpio.h>
+
+ i2c {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ camera-sensor@21 {
+ compatible = "galaxycore,gc0308";
+ reg = <0x21>;
+ clocks = <&camera_clk>;
+ powerdown-gpios = <&gpio1 5 GPIO_ACTIVE_HIGH>;
+ reset-gpios = <&gpio1 6 GPIO_ACTIVE_LOW>;
+ vdd28-supply = <&vdd28>;
+
+ port {
+ gc0308_ep: endpoint {
+ remote-endpoint = <¶llel_from_gc0308>;
+ bus-width = <8>;
+ data-shift = <2>; /* lines 9:2 are used */
+ hsync-active = <1>; /* active high */
+ vsync-active = <1>; /* active high */
+ data-active = <1>; /* active high */
+ pclk-sample = <1>; /* sample on rising edge */
+ };
+ };
+ };
+ };
+
+...
diff --git a/dts/upstream/Bindings/media/i2c/galaxycore,gc2145.yaml b/dts/upstream/Bindings/media/i2c/galaxycore,gc2145.yaml
new file mode 100644
index 0000000..1726ecc
--- /dev/null
+++ b/dts/upstream/Bindings/media/i2c/galaxycore,gc2145.yaml
@@ -0,0 +1,113 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/media/i2c/galaxycore,gc2145.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Galaxy Core 1/5'' UXGA CMOS Image Sensor
+
+maintainers:
+ - Alain Volmat <alain.volmat@foss.st.com>
+
+description:
+ The Galaxy Core GC2145 is a 2 Megapixel CMOS image sensor, for mobile
+ phone camera applications and digital camera products. GC2145 incorporates a
+ 1616V x 1232H active pixel array, on-chip 10-bit ADC, and image signal
+ processor allowing AE/AWB/interpolation/de-noise/color-conversion and
+ gamma correction. Bayer RGB, RGB565 and YCbCr 4:2:2 can be provided by the
+ sensor. It is programmable through an I2C interface. Image data is sent
+ either through a parallel interface or through MIPI CSI-2.
+
+allOf:
+ - $ref: ../video-interface-devices.yaml#
+
+properties:
+ compatible:
+ const: galaxycore,gc2145
+
+ reg:
+ const: 0x3c
+
+ clocks:
+ maxItems: 1
+
+ powerdown-gpios:
+ maxItems: 1
+
+ reset-gpios:
+ maxItems: 1
+
+ iovdd-supply:
+ description: Power Supply for I/O circuits (1.7 - 3V).
+
+ avdd-supply:
+ description: Power for analog circuit/sensor array (2.7 - 3V).
+
+ dvdd-supply:
+ description: Power for digital core (1.7 - 1.9V).
+
+ orientation: true
+
+ rotation: true
+
+ port:
+ $ref: /schemas/graph.yaml#/$defs/port-base
+
+ properties:
+ endpoint:
+ $ref: /schemas/media/video-interfaces.yaml#
+ unevaluatedProperties: false
+
+ properties:
+ link-frequencies: true
+
+ required:
+ - link-frequencies
+
+ required:
+ - endpoint
+
+ additionalProperties: false
+
+required:
+ - compatible
+ - reg
+ - clocks
+ - powerdown-gpios
+ - reset-gpios
+ - iovdd-supply
+ - avdd-supply
+ - dvdd-supply
+ - port
+
+additionalProperties: false
+
+examples:
+ - |
+ #include <dt-bindings/gpio/gpio.h>
+
+ i2c {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ camera@3c {
+ compatible = "galaxycore,gc2145";
+ reg = <0x3c>;
+ clocks = <&clk_ext_camera>;
+ iovdd-supply = <&scmi_v3v3_sw>;
+ avdd-supply = <&scmi_v3v3_sw>;
+ dvdd-supply = <&scmi_v3v3_sw>;
+ powerdown-gpios = <&mcp23017 3 (GPIO_ACTIVE_LOW | GPIO_PUSH_PULL)>;
+ reset-gpios = <&mcp23017 4 (GPIO_ACTIVE_LOW | GPIO_PUSH_PULL)>;
+
+ port {
+ endpoint {
+ remote-endpoint = <&mipid02_0>;
+ data-lanes = <1 2>;
+ link-frequencies = /bits/ 64 <120000000 192000000 240000000>;
+ };
+ };
+ };
+ };
+
+...
diff --git a/dts/upstream/Bindings/media/i2c/ov8856.yaml b/dts/upstream/Bindings/media/i2c/ov8856.yaml
index 57f5e48..816dac9 100644
--- a/dts/upstream/Bindings/media/i2c/ov8856.yaml
+++ b/dts/upstream/Bindings/media/i2c/ov8856.yaml
@@ -67,19 +67,17 @@
properties:
data-lanes:
- description: |-
- The driver only supports four-lane operation.
- items:
- - const: 1
- - const: 2
- - const: 3
- - const: 4
-
- link-frequencies:
- description: Frequencies listed are driver, not h/w limitations.
- maxItems: 2
- items:
- enum: [ 360000000, 180000000 ]
+ oneOf:
+ - items:
+ - const: 1
+ - items:
+ - const: 1
+ - const: 2
+ - items:
+ - const: 1
+ - const: 2
+ - const: 3
+ - const: 4
required:
- link-frequencies
diff --git a/dts/upstream/Bindings/media/i2c/ovti,ov64a40.yaml b/dts/upstream/Bindings/media/i2c/ovti,ov64a40.yaml
new file mode 100644
index 0000000..2b6143a
--- /dev/null
+++ b/dts/upstream/Bindings/media/i2c/ovti,ov64a40.yaml
@@ -0,0 +1,103 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/media/i2c/ovti,ov64a40.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: OmniVision OV64A40 Image Sensor
+
+maintainers:
+ - Jacopo Mondi <jacopo.mondi@ideasonboard.com>
+
+allOf:
+ - $ref: /schemas/media/video-interface-devices.yaml#
+
+properties:
+ compatible:
+ const: ovti,ov64a40
+
+ reg:
+ maxItems: 1
+
+ clocks:
+ maxItems: 1
+
+ avdd-supply:
+ description: Analog voltage supply, 2.8 volts
+
+ dvdd-supply:
+ description: Digital core voltage supply, 1.1 volts
+
+ dovdd-supply:
+ description: Digital I/O voltage supply, 1.8 volts
+
+ powerdown-gpios:
+ maxItems: 1
+
+ reset-gpios:
+ maxItems: 1
+
+ port:
+ $ref: /schemas/graph.yaml#/$defs/port-base
+ additionalProperties: false
+
+ properties:
+ endpoint:
+ $ref: /schemas/media/video-interfaces.yaml#
+ additionalProperties: false
+
+ properties:
+ bus-type:
+ enum:
+ - 1 # MIPI CSI-2 C-PHY
+ - 4 # MIPI CSI-2 D-PHY
+ data-lanes: true
+ link-frequencies: true
+ clock-noncontinuous: true
+ remote-endpoint: true
+
+ required:
+ - bus-type
+ - data-lanes
+ - link-frequencies
+
+required:
+ - compatible
+ - reg
+ - clocks
+ - port
+
+unevaluatedProperties: false
+
+examples:
+ - |
+ #include <dt-bindings/gpio/gpio.h>
+
+ i2c {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ camera@36 {
+ compatible = "ovti,ov64a40";
+ reg = <0x36>;
+ clocks = <&camera_clk>;
+ dovdd-supply = <&vgen4_reg>;
+ avdd-supply = <&vgen3_reg>;
+ dvdd-supply = <&vgen2_reg>;
+ powerdown-gpios = <&gpio1 9 GPIO_ACTIVE_HIGH>;
+ reset-gpios = <&gpio1 10 GPIO_ACTIVE_LOW>;
+ rotation = <180>;
+ orientation = <2>;
+
+ port {
+ endpoint {
+ remote-endpoint = <&mipi_csi2_in>;
+ bus-type = <4>;
+ data-lanes = <1 2 3 4>;
+ link-frequencies = /bits/ 64 <456000000>;
+ };
+ };
+ };
+ };
+
+...
diff --git a/dts/upstream/Bindings/media/i2c/sony,imx335.yaml b/dts/upstream/Bindings/media/i2c/sony,imx335.yaml
index a167dcd..106c36e 100644
--- a/dts/upstream/Bindings/media/i2c/sony,imx335.yaml
+++ b/dts/upstream/Bindings/media/i2c/sony,imx335.yaml
@@ -32,6 +32,15 @@
description: Clock frequency from 6 to 27 MHz, 37.125MHz, 74.25MHz
maxItems: 1
+ avdd-supply:
+ description: Analog power supply (2.9V)
+
+ ovdd-supply:
+ description: Interface power supply (1.8V)
+
+ dvdd-supply:
+ description: Digital power supply (1.2V)
+
reset-gpios:
description: Reference to the GPIO connected to the XCLR pin, if any.
maxItems: 1
@@ -79,6 +88,10 @@
assigned-clock-parents = <&imx335_clk_parent>;
assigned-clock-rates = <24000000>;
+ avdd-supply = <&camera_vdda_2v9>;
+ ovdd-supply = <&camera_vddo_1v8>;
+ dvdd-supply = <&camera_vddd_1v2>;
+
port {
imx335: endpoint {
remote-endpoint = <&cam>;
diff --git a/dts/upstream/Bindings/media/i2c/techwell,tw9900.yaml b/dts/upstream/Bindings/media/i2c/techwell,tw9900.yaml
new file mode 100644
index 0000000..e37317f
--- /dev/null
+++ b/dts/upstream/Bindings/media/i2c/techwell,tw9900.yaml
@@ -0,0 +1,137 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/media/i2c/techwell,tw9900.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Techwell TW9900 NTSC/PAL video decoder
+
+maintainers:
+ - Mehdi Djait <mehdi.djait@bootlin.com>
+
+description:
+ The tw9900 is a multi-standard video decoder, supporting NTSC, PAL standards
+ with auto-detection features.
+
+properties:
+ compatible:
+ const: techwell,tw9900
+
+ reg:
+ maxItems: 1
+
+ vdd-supply:
+ description: VDD power supply
+
+ reset-gpios:
+ description: GPIO descriptor for the RESET input pin
+ maxItems: 1
+
+ powerdown-gpios:
+ description: GPIO descriptor for the POWERDOWN input pin
+ maxItems: 1
+
+ ports:
+ $ref: /schemas/graph.yaml#/properties/ports
+
+ properties:
+ port@0:
+ $ref: /schemas/graph.yaml#/$defs/port-base
+ description: Analog input port
+
+ properties:
+ endpoint@0:
+ $ref: /schemas/graph.yaml#/properties/endpoint
+ description: CVBS over MUX0
+
+ endpoint@1:
+ $ref: /schemas/graph.yaml#/properties/endpoint
+ description: CVBS over MUX1
+
+ endpoint@2:
+ $ref: /schemas/graph.yaml#/properties/endpoint
+ description: Chroma over CIN0 and Y over MUX0
+
+ endpoint@3:
+ $ref: /schemas/graph.yaml#/properties/endpoint
+ description: Chroma over CIN0 and Y over MUX1
+
+ oneOf:
+ - required:
+ - endpoint@0
+ - required:
+ - endpoint@1
+ - required:
+ - endpoint@2
+ - required:
+ - endpoint@3
+
+ port@1:
+ $ref: /schemas/graph.yaml#/properties/port
+ description: Video port for the decoder output.
+
+
+ required:
+ - port@0
+ - port@1
+
+required:
+ - compatible
+ - ports
+ - reg
+ - vdd-supply
+
+additionalProperties: false
+
+examples:
+ - |
+ #include <dt-bindings/display/sdtv-standards.h>
+ #include <dt-bindings/gpio/gpio.h>
+
+ composite_connector {
+ compatible = "composite-video-connector";
+ label = "tv";
+ sdtv-standards = <(SDTV_STD_PAL | SDTV_STD_NTSC)>;
+
+ port {
+ composite_to_tw9900: endpoint {
+ remote-endpoint = <&tw9900_to_composite>;
+ };
+ };
+ };
+
+ i2c {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ video-decoder@44 {
+ compatible = "techwell,tw9900";
+ reg = <0x44>;
+
+ vdd-supply = <&tw9900_supply>;
+ reset-gpios = <&gpio2 5 GPIO_ACTIVE_LOW>;
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ reg = <0>;
+ tw9900_to_composite: endpoint@0 {
+ reg = <0>;
+ remote-endpoint = <&composite_to_tw9900>;
+ };
+ };
+
+ port@1 {
+ reg = <1>;
+ endpoint {
+ remote-endpoint = <&cif_in>;
+ };
+ };
+ };
+ };
+ };
diff --git a/dts/upstream/Bindings/media/i2c/thine,thp7312.yaml b/dts/upstream/Bindings/media/i2c/thine,thp7312.yaml
new file mode 100644
index 0000000..1978fbb
--- /dev/null
+++ b/dts/upstream/Bindings/media/i2c/thine,thp7312.yaml
@@ -0,0 +1,224 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+# Copyright (c) 2023 Ideas on Board
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/media/i2c/thine,thp7312.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: THine THP7312
+
+maintainers:
+ - Paul Elder <paul.elder@@ideasonboard.com>
+
+description:
+ The THP7312 is a standalone ISP controlled over i2c, and is capable of
+ various image processing and correction functions, including 3A control. It
+ can be connected to CMOS image sensors from various vendors, supporting both
+ MIPI CSI-2 and parallel interfaces. It can also output on either MIPI CSI-2
+ or parallel. The hardware is capable of transmitting and receiving MIPI
+ interlaved data strams with data types or multiple virtual channel
+ identifiers.
+
+allOf:
+ - $ref: /schemas/media/video-interface-devices.yaml#
+
+properties:
+ compatible:
+ const: thine,thp7312
+
+ reg:
+ maxItems: 1
+
+ clocks:
+ maxItems: 1
+ description: CLKI clock input
+
+ thine,boot-mode:
+ $ref: /schemas/types.yaml#/definitions/uint32
+ minimum: 0
+ maximum: 1
+ default: 1
+ description:
+ Boot mode of the THP7312, reflecting the value of the BOOT[0] pin strap.
+ 0 is for the SPI/2-wire slave boot, 1 is for the SPI master boot (from
+ external flash ROM).
+
+ reset-gpios:
+ maxItems: 1
+ description:
+ Reference to the GPIO connected to the RESET_N pin, if any.
+ Must be released (set high) after all supplies are applied.
+
+ vddcore-supply:
+ description:
+ 1.2V supply for core, PLL, MIPI rx and MIPI tx.
+
+ vhtermrx-supply:
+ description:
+ Supply for input (RX). 1.8V for MIPI, or 1.8/2.8/3.3V for parallel.
+
+ vddtx-supply:
+ description:
+ Supply for output (TX). 1.8V for MIPI, or 1.8/2.8/3.3V for parallel.
+
+ vddhost-supply:
+ description:
+ Supply for host interface. 1.8V, 2.8V, or 3.3V.
+
+ vddcmos-supply:
+ description:
+ Supply for sensor interface. 1.8V, 2.8V, or 3.3V.
+
+ vddgpio-0-supply:
+ description:
+ Supply for GPIO_0. 1.8V, 2.8V, or 3.3V.
+
+ vddgpio-1-supply:
+ description:
+ Supply for GPIO_1. 1.8V, 2.8V, or 3.3V.
+
+ orientation: true
+ rotation: true
+
+ port:
+ $ref: /schemas/graph.yaml#/$defs/port-base
+ additionalProperties: false
+
+ properties:
+ endpoint:
+ $ref: /schemas/media/video-interfaces.yaml#
+ unevaluatedProperties: false
+
+ properties:
+ bus-type:
+ const: 4 # CSI-2 D-PHY
+
+ data-lanes:
+ description:
+ This property is for lane reordering between the THP7312 and the
+ SoC. The sensor supports either two-lane, or four-lane operation.
+ If this property is omitted four-lane operation is assumed. For
+ two-lane operation the property must be set to <1 2>.
+ minItems: 2
+ maxItems: 4
+ items:
+ maximum: 4
+
+ sensors:
+ type: object
+ description: List of connected sensors
+
+ properties:
+ "#address-cells":
+ const: 1
+
+ "#size-cells":
+ const: 0
+
+ patternProperties:
+ "^sensor@[01]$":
+ type: object
+ description:
+ Sensors connected to the first and second input, with one node per
+ sensor.
+
+ properties:
+ thine,model:
+ $ref: /schemas/types.yaml#/definitions/string
+ description:
+ Model of the connected sensors. Must be a valid compatible string.
+
+ reg:
+ description: THP7312 input port number
+ items:
+ - maximum: 1
+
+ data-lanes:
+ $ref: /schemas/media/video-interfaces.yaml#/properties/data-lanes
+ items:
+ maxItems: 4
+ description:
+ This property is for lane reordering between the THP7312 and the imaging
+ sensor that it is connected to.
+
+ required:
+ - reg
+ - data-lanes
+
+ additionalProperties: false
+
+ required:
+ - "#address-cells"
+ - "#size-cells"
+
+ additionalProperties: false
+
+required:
+ - compatible
+ - reg
+ - reset-gpios
+ - clocks
+ - vddcore-supply
+ - vhtermrx-supply
+ - vddtx-supply
+ - vddhost-supply
+ - vddcmos-supply
+ - vddgpio-0-supply
+ - vddgpio-1-supply
+ - sensors
+ - port
+
+additionalProperties: false
+
+examples:
+ - |
+ #include <dt-bindings/gpio/gpio.h>
+ #include <dt-bindings/media/video-interfaces.h>
+
+ i2c {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ camera@61 {
+ compatible = "thine,thp7312";
+ reg = <0x61>;
+
+ pinctrl-names = "default";
+ pinctrl-0 = <&cam1_pins_default>;
+
+ reset-gpios = <&pio 119 GPIO_ACTIVE_LOW>;
+ clocks = <&camera61_clk>;
+
+ vddcore-supply = <&vsys_v4p2>;
+ vhtermrx-supply = <&vsys_v4p2>;
+ vddtx-supply = <&vsys_v4p2>;
+ vddhost-supply = <&vsys_v4p2>;
+ vddcmos-supply = <&vsys_v4p2>;
+ vddgpio-0-supply = <&vsys_v4p2>;
+ vddgpio-1-supply = <&vsys_v4p2>;
+
+ orientation = <0>;
+ rotation = <0>;
+
+ sensors {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ sensor@0 {
+ thine,model = "sony,imx258";
+ reg = <0>;
+
+ data-lanes = <4 1 3 2>;
+ };
+ };
+
+ port {
+ thp7312_2_endpoint: endpoint {
+ remote-endpoint = <&mipi_thp7312_2>;
+ bus-type = <MEDIA_BUS_TYPE_CSI2_DPHY>;
+ data-lanes = <4 2 1 3>;
+ };
+ };
+ };
+ };
+...
diff --git a/dts/upstream/Bindings/media/mediatek,mdp3-fg.yaml b/dts/upstream/Bindings/media/mediatek,mdp3-fg.yaml
new file mode 100644
index 0000000..03f31b0
--- /dev/null
+++ b/dts/upstream/Bindings/media/mediatek,mdp3-fg.yaml
@@ -0,0 +1,61 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/media/mediatek,mdp3-fg.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: MediaTek Media Data Path 3 Film Grain
+
+maintainers:
+ - Matthias Brugger <matthias.bgg@gmail.com>
+ - Moudy Ho <moudy.ho@mediatek.com>
+
+description:
+ Film Grain (FG) is a Media Data Path 3 (MDP3) component used to add
+ the film grain according to the AOMedia Video 1 (AV1) standard.
+
+properties:
+ compatible:
+ enum:
+ - mediatek,mt8195-mdp3-fg
+
+ reg:
+ maxItems: 1
+
+ mediatek,gce-client-reg:
+ description:
+ The register of display function block to be set by gce. There are 4 arguments,
+ such as gce node, subsys id, offset and register size. The subsys id that is
+ mapping to the register of display function blocks is defined in the gce header
+ include/dt-bindings/gce/<chip>-gce.h of each chips.
+ $ref: /schemas/types.yaml#/definitions/phandle-array
+ items:
+ items:
+ - description: phandle of GCE
+ - description: GCE subsys id
+ - description: register offset
+ - description: register size
+ maxItems: 1
+
+ clocks:
+ maxItems: 1
+
+required:
+ - compatible
+ - reg
+ - mediatek,gce-client-reg
+ - clocks
+
+additionalProperties: false
+
+examples:
+ - |
+ #include <dt-bindings/clock/mt8195-clk.h>
+ #include <dt-bindings/gce/mt8195-gce.h>
+
+ display@14002000 {
+ compatible = "mediatek,mt8195-mdp3-fg";
+ reg = <0x14002000 0x1000>;
+ mediatek,gce-client-reg = <&gce1 SUBSYS_1400XXXX 0x2000 0x1000>;
+ clocks = <&vppsys0 CLK_VPP0_MDP_FG>;
+ };
diff --git a/dts/upstream/Bindings/media/mediatek,mdp3-hdr.yaml b/dts/upstream/Bindings/media/mediatek,mdp3-hdr.yaml
new file mode 100644
index 0000000..d4609bb
--- /dev/null
+++ b/dts/upstream/Bindings/media/mediatek,mdp3-hdr.yaml
@@ -0,0 +1,61 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/media/mediatek,mdp3-hdr.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: MediaTek Media Data Path 3 HDR
+
+maintainers:
+ - Matthias Brugger <matthias.bgg@gmail.com>
+ - Moudy Ho <moudy.ho@mediatek.com>
+
+description:
+ A Media Data Path 3 (MDP3) component used to perform conversion from
+ High Dynamic Range (HDR) to Standard Dynamic Range (SDR).
+
+properties:
+ compatible:
+ enum:
+ - mediatek,mt8195-mdp3-hdr
+
+ reg:
+ maxItems: 1
+
+ mediatek,gce-client-reg:
+ description:
+ The register of display function block to be set by gce. There are 4 arguments,
+ such as gce node, subsys id, offset and register size. The subsys id that is
+ mapping to the register of display function blocks is defined in the gce header
+ include/dt-bindings/gce/<chip>-gce.h of each chips.
+ $ref: /schemas/types.yaml#/definitions/phandle-array
+ items:
+ items:
+ - description: phandle of GCE
+ - description: GCE subsys id
+ - description: register offset
+ - description: register size
+ maxItems: 1
+
+ clocks:
+ maxItems: 1
+
+required:
+ - compatible
+ - reg
+ - mediatek,gce-client-reg
+ - clocks
+
+additionalProperties: false
+
+examples:
+ - |
+ #include <dt-bindings/clock/mt8195-clk.h>
+ #include <dt-bindings/gce/mt8195-gce.h>
+
+ display@14004000 {
+ compatible = "mediatek,mt8195-mdp3-hdr";
+ reg = <0x14004000 0x1000>;
+ mediatek,gce-client-reg = <&gce1 SUBSYS_1400XXXX 0x4000 0x1000>;
+ clocks = <&vppsys0 CLK_VPP0_MDP_HDR>;
+ };
diff --git a/dts/upstream/Bindings/media/mediatek,mdp3-rdma.yaml b/dts/upstream/Bindings/media/mediatek,mdp3-rdma.yaml
index 7032c7e..59db830 100644
--- a/dts/upstream/Bindings/media/mediatek,mdp3-rdma.yaml
+++ b/dts/upstream/Bindings/media/mediatek,mdp3-rdma.yaml
@@ -20,8 +20,14 @@
properties:
compatible:
- items:
- - const: mediatek,mt8183-mdp3-rdma
+ oneOf:
+ - enum:
+ - mediatek,mt8183-mdp3-rdma
+ - mediatek,mt8195-mdp3-rdma
+ - mediatek,mt8195-vdo1-rdma
+ - items:
+ - const: mediatek,mt8188-vdo1-rdma
+ - const: mediatek,mt8195-vdo1-rdma
reg:
maxItems: 1
@@ -45,6 +51,14 @@
include/dt-bindings/gce/<chip>-gce.h of each chips.
$ref: /schemas/types.yaml#/definitions/uint32-array
+ mediatek,scp:
+ $ref: /schemas/types.yaml#/definitions/phandle
+ description:
+ Phandle to the System Control Processor (SCP) used for initializing
+ and stopping the MDP3, for sending frame data locations to the MDP3's
+ VPU and to install Inter-Processor Interrupt handlers to control
+ processing states.
+
power-domains:
maxItems: 1
@@ -52,6 +66,7 @@
items:
- description: RDMA clock
- description: RSZ clock
+ minItems: 1
iommus:
maxItems: 1
@@ -60,16 +75,72 @@
items:
- description: used for 1st data pipe from RDMA
- description: used for 2nd data pipe from RDMA
+ - description: used for 3rd data pipe from RDMA
+ - description: used for 4th data pipe from RDMA
+ - description: used for the data pipe from SPLIT
+ minItems: 1
+
+ interrupts:
+ maxItems: 1
+
+ '#dma-cells':
+ const: 1
required:
- compatible
- reg
- mediatek,gce-client-reg
- - mediatek,gce-events
- power-domains
- clocks
- iommus
- - mboxes
+ - '#dma-cells'
+
+allOf:
+ - if:
+ properties:
+ compatible:
+ contains:
+ const: mediatek,mt8183-mdp3-rdma
+
+ then:
+ properties:
+ clocks:
+ minItems: 2
+
+ mboxes:
+ minItems: 2
+
+ required:
+ - mboxes
+ - mediatek,gce-events
+
+ - if:
+ properties:
+ compatible:
+ contains:
+ const: mediatek,mt8195-mdp3-rdma
+
+ then:
+ properties:
+ clocks:
+ maxItems: 1
+
+ mboxes:
+ minItems: 5
+
+ required:
+ - mediatek,gce-events
+
+ - if:
+ properties:
+ compatible:
+ contains:
+ const: mediatek,mt8195-vdo1-rdma
+
+ then:
+ properties:
+ clocks:
+ maxItems: 1
additionalProperties: false
@@ -80,16 +151,17 @@
#include <dt-bindings/power/mt8183-power.h>
#include <dt-bindings/memory/mt8183-larb-port.h>
- mdp3_rdma0: mdp3-rdma0@14001000 {
- compatible = "mediatek,mt8183-mdp3-rdma";
- reg = <0x14001000 0x1000>;
- mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0x1000 0x1000>;
- mediatek,gce-events = <CMDQ_EVENT_MDP_RDMA0_SOF>,
- <CMDQ_EVENT_MDP_RDMA0_EOF>;
- power-domains = <&spm MT8183_POWER_DOMAIN_DISP>;
- clocks = <&mmsys CLK_MM_MDP_RDMA0>,
- <&mmsys CLK_MM_MDP_RSZ1>;
- iommus = <&iommu>;
- mboxes = <&gce 20 CMDQ_THR_PRIO_LOWEST>,
- <&gce 21 CMDQ_THR_PRIO_LOWEST>;
+ dma-controller@14001000 {
+ compatible = "mediatek,mt8183-mdp3-rdma";
+ reg = <0x14001000 0x1000>;
+ mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0x1000 0x1000>;
+ mediatek,gce-events = <CMDQ_EVENT_MDP_RDMA0_SOF>,
+ <CMDQ_EVENT_MDP_RDMA0_EOF>;
+ power-domains = <&spm MT8183_POWER_DOMAIN_DISP>;
+ clocks = <&mmsys CLK_MM_MDP_RDMA0>,
+ <&mmsys CLK_MM_MDP_RSZ1>;
+ iommus = <&iommu>;
+ mboxes = <&gce 20 CMDQ_THR_PRIO_LOWEST>,
+ <&gce 21 CMDQ_THR_PRIO_LOWEST>;
+ #dma-cells = <1>;
};
diff --git a/dts/upstream/Bindings/media/mediatek,mdp3-rsz.yaml b/dts/upstream/Bindings/media/mediatek,mdp3-rsz.yaml
index 78f9de6..f5676be 100644
--- a/dts/upstream/Bindings/media/mediatek,mdp3-rsz.yaml
+++ b/dts/upstream/Bindings/media/mediatek,mdp3-rsz.yaml
@@ -15,9 +15,13 @@
properties:
compatible:
- items:
+ oneOf:
- enum:
- mediatek,mt8183-mdp3-rsz
+ - items:
+ - enum:
+ - mediatek,mt8195-mdp3-rsz
+ - const: mediatek,mt8183-mdp3-rsz
reg:
maxItems: 1
diff --git a/dts/upstream/Bindings/media/mediatek,mdp3-stitch.yaml b/dts/upstream/Bindings/media/mediatek,mdp3-stitch.yaml
new file mode 100644
index 0000000..d815bea
--- /dev/null
+++ b/dts/upstream/Bindings/media/mediatek,mdp3-stitch.yaml
@@ -0,0 +1,61 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/media/mediatek,mdp3-stitch.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: MediaTek Media Data Path 3 STITCH
+
+maintainers:
+ - Matthias Brugger <matthias.bgg@gmail.com>
+ - Moudy Ho <moudy.ho@mediatek.com>
+
+description:
+ One of Media Data Path 3 (MDP3) components used to combine multiple video frame
+ with overlapping fields of view to produce a segmented panorame.
+
+properties:
+ compatible:
+ enum:
+ - mediatek,mt8195-mdp3-stitch
+
+ reg:
+ maxItems: 1
+
+ mediatek,gce-client-reg:
+ description:
+ The register of display function block to be set by gce. There are 4 arguments,
+ such as gce node, subsys id, offset and register size. The subsys id that is
+ mapping to the register of display function blocks is defined in the gce header
+ include/dt-bindings/gce/<chip>-gce.h of each chips.
+ $ref: /schemas/types.yaml#/definitions/phandle-array
+ items:
+ items:
+ - description: phandle of GCE
+ - description: GCE subsys id
+ - description: register offset
+ - description: register size
+ maxItems: 1
+
+ clocks:
+ maxItems: 1
+
+required:
+ - compatible
+ - reg
+ - mediatek,gce-client-reg
+ - clocks
+
+additionalProperties: false
+
+examples:
+ - |
+ #include <dt-bindings/clock/mt8195-clk.h>
+ #include <dt-bindings/gce/mt8195-gce.h>
+
+ display@14003000 {
+ compatible = "mediatek,mt8195-mdp3-stitch";
+ reg = <0x14003000 0x1000>;
+ mediatek,gce-client-reg = <&gce1 SUBSYS_1400XXXX 0x3000 0x1000>;
+ clocks = <&vppsys0 CLK_VPP0_STITCH>;
+ };
diff --git a/dts/upstream/Bindings/media/mediatek,mdp3-tcc.yaml b/dts/upstream/Bindings/media/mediatek,mdp3-tcc.yaml
new file mode 100644
index 0000000..14ea556
--- /dev/null
+++ b/dts/upstream/Bindings/media/mediatek,mdp3-tcc.yaml
@@ -0,0 +1,62 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/media/mediatek,mdp3-tcc.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: MediaTek Media Data Path 3 Tone Curve Conversion
+
+maintainers:
+ - Matthias Brugger <matthias.bgg@gmail.com>
+
+description:
+ Tone Curve Conversion (TCC) is one of Media Profile Path 3 (MDP3) components.
+ It is used to handle the tone mapping of various gamma curves in order to
+ achieve HDR10 effects. This helps adapt the content to the color and
+ brightness range that standard display devices typically support.
+
+properties:
+ compatible:
+ enum:
+ - mediatek,mt8195-mdp3-tcc
+
+ reg:
+ maxItems: 1
+
+ mediatek,gce-client-reg:
+ description:
+ The register of display function block to be set by gce. There are 4 arguments,
+ such as gce node, subsys id, offset and register size. The subsys id that is
+ mapping to the register of display function blocks is defined in the gce header
+ include/dt-bindings/gce/<chip>-gce.h of each chips.
+ $ref: /schemas/types.yaml#/definitions/phandle-array
+ items:
+ items:
+ - description: phandle of GCE
+ - description: GCE subsys id
+ - description: register offset
+ - description: register size
+ maxItems: 1
+
+ clocks:
+ maxItems: 1
+
+required:
+ - compatible
+ - reg
+ - mediatek,gce-client-reg
+ - clocks
+
+additionalProperties: false
+
+examples:
+ - |
+ #include <dt-bindings/clock/mt8195-clk.h>
+ #include <dt-bindings/gce/mt8195-gce.h>
+
+ display@1400b000 {
+ compatible = "mediatek,mt8195-mdp3-tcc";
+ reg = <0x1400b000 0x1000>;
+ mediatek,gce-client-reg = <&gce1 SUBSYS_1400XXXX 0xb000 0x1000>;
+ clocks = <&vppsys0 CLK_VPP0_MDP_TCC>;
+ };
diff --git a/dts/upstream/Bindings/media/mediatek,mdp3-tdshp.yaml b/dts/upstream/Bindings/media/mediatek,mdp3-tdshp.yaml
new file mode 100644
index 0000000..8ab7f2d
--- /dev/null
+++ b/dts/upstream/Bindings/media/mediatek,mdp3-tdshp.yaml
@@ -0,0 +1,61 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/media/mediatek,mdp3-tdshp.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: MediaTek Media Data Path 3 Two-Dimensional Sharpness
+
+maintainers:
+ - Matthias Brugger <matthias.bgg@gmail.com>
+ - Moudy Ho <moudy.ho@mediatek.com>
+
+description:
+ Two-Dimensional Sharpness (TDSHP) is a Media Profile Path 3 (MDP3) component
+ used to perform image edge sharpening and enhance vividness and contrast.
+
+properties:
+ compatible:
+ enum:
+ - mediatek,mt8195-mdp3-tdshp
+
+ reg:
+ maxItems: 1
+
+ mediatek,gce-client-reg:
+ description:
+ The register of display function block to be set by gce. There are 4 arguments,
+ such as gce node, subsys id, offset and register size. The subsys id that is
+ mapping to the register of display function blocks is defined in the gce header
+ include/dt-bindings/gce/<chip>-gce.h of each chips.
+ $ref: /schemas/types.yaml#/definitions/phandle-array
+ items:
+ items:
+ - description: phandle of GCE
+ - description: GCE subsys id
+ - description: register offset
+ - description: register size
+ maxItems: 1
+
+ clocks:
+ maxItems: 1
+
+required:
+ - compatible
+ - reg
+ - mediatek,gce-client-reg
+ - clocks
+
+additionalProperties: false
+
+examples:
+ - |
+ #include <dt-bindings/clock/mt8195-clk.h>
+ #include <dt-bindings/gce/mt8195-gce.h>
+
+ display@14007000 {
+ compatible = "mediatek,mt8195-mdp3-tdshp";
+ reg = <0x14007000 0x1000>;
+ mediatek,gce-client-reg = <&gce1 SUBSYS_1400XXXX 0x7000 0x1000>;
+ clocks = <&vppsys0 CLK_VPP0_MDP_TDSHP>;
+ };
diff --git a/dts/upstream/Bindings/media/mediatek,mdp3-wrot.yaml b/dts/upstream/Bindings/media/mediatek,mdp3-wrot.yaml
index 0baa771..53a6793 100644
--- a/dts/upstream/Bindings/media/mediatek,mdp3-wrot.yaml
+++ b/dts/upstream/Bindings/media/mediatek,mdp3-wrot.yaml
@@ -15,9 +15,13 @@
properties:
compatible:
- items:
+ oneOf:
- enum:
- mediatek,mt8183-mdp3-wrot
+ - items:
+ - enum:
+ - mediatek,mt8195-mdp3-wrot
+ - const: mediatek,mt8183-mdp3-wrot
reg:
maxItems: 1
@@ -50,6 +54,9 @@
iommus:
maxItems: 1
+ '#dma-cells':
+ const: 1
+
required:
- compatible
- reg
@@ -58,6 +65,7 @@
- power-domains
- clocks
- iommus
+ - '#dma-cells'
additionalProperties: false
@@ -68,13 +76,14 @@
#include <dt-bindings/power/mt8183-power.h>
#include <dt-bindings/memory/mt8183-larb-port.h>
- mdp3_wrot0: mdp3-wrot0@14005000 {
- compatible = "mediatek,mt8183-mdp3-wrot";
- reg = <0x14005000 0x1000>;
- mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0x5000 0x1000>;
- mediatek,gce-events = <CMDQ_EVENT_MDP_WROT0_SOF>,
- <CMDQ_EVENT_MDP_WROT0_EOF>;
- power-domains = <&spm MT8183_POWER_DOMAIN_DISP>;
- clocks = <&mmsys CLK_MM_MDP_WROT0>;
- iommus = <&iommu>;
+ dma-controller@14005000 {
+ compatible = "mediatek,mt8183-mdp3-wrot";
+ reg = <0x14005000 0x1000>;
+ mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0x5000 0x1000>;
+ mediatek,gce-events = <CMDQ_EVENT_MDP_WROT0_SOF>,
+ <CMDQ_EVENT_MDP_WROT0_EOF>;
+ power-domains = <&spm MT8183_POWER_DOMAIN_DISP>;
+ clocks = <&mmsys CLK_MM_MDP_WROT0>;
+ iommus = <&iommu>;
+ #dma-cells = <1>;
};
diff --git a/dts/upstream/Bindings/media/rockchip-isp1.yaml b/dts/upstream/Bindings/media/rockchip-isp1.yaml
index e466dff..afcaa427 100644
--- a/dts/upstream/Bindings/media/rockchip-isp1.yaml
+++ b/dts/upstream/Bindings/media/rockchip-isp1.yaml
@@ -90,15 +90,16 @@
description: connection point for input on the parallel interface
properties:
- bus-type:
- enum: [5, 6]
-
endpoint:
$ref: video-interfaces.yaml#
unevaluatedProperties: false
- required:
- - bus-type
+ properties:
+ bus-type:
+ enum: [5, 6]
+
+ required:
+ - bus-type
anyOf:
- required:
diff --git a/dts/upstream/Bindings/media/samsung,s5p-mfc.yaml b/dts/upstream/Bindings/media/samsung,s5p-mfc.yaml
index 084b445..b46cc78 100644
--- a/dts/upstream/Bindings/media/samsung,s5p-mfc.yaml
+++ b/dts/upstream/Bindings/media/samsung,s5p-mfc.yaml
@@ -24,6 +24,7 @@
- samsung,mfc-v7 # Exynos5420
- samsung,mfc-v8 # Exynos5800
- samsung,mfc-v10 # Exynos7880
+ - tesla,fsd-mfc # Tesla FSD
- items:
- enum:
- samsung,exynos3250-mfc # Exynos3250
@@ -49,7 +50,9 @@
iommu-names:
minItems: 1
- maxItems: 2
+ items:
+ - const: left
+ - const: right
power-domains:
maxItems: 1
@@ -84,7 +87,7 @@
- const: sclk_mfc
iommus:
maxItems: 1
- iommus-names: false
+ iommu-names: false
- if:
properties:
@@ -102,11 +105,9 @@
- const: aclk
- const: aclk_xiu
iommus:
- maxItems: 2
- iommus-names:
- items:
- - const: left
- - const: right
+ minItems: 2
+ iommu-names:
+ minItems: 2
- if:
properties:
@@ -123,11 +124,9 @@
- const: mfc
- const: sclk_mfc
iommus:
- maxItems: 2
- iommus-names:
- items:
- - const: left
- - const: right
+ minItems: 2
+ iommu-names:
+ minItems: 2
- if:
properties:
@@ -144,11 +143,9 @@
items:
- const: mfc
iommus:
- maxItems: 2
- iommus-names:
- items:
- - const: left
- - const: right
+ minItems: 2
+ iommu-names:
+ minItems: 2
- if:
properties:
@@ -161,9 +158,23 @@
clocks:
minItems: 1
maxItems: 2
+
+ - if:
+ properties:
+ compatible:
+ contains:
+ enum:
+ - tesla,fsd-mfc
+ then:
+ properties:
+ clocks:
+ maxItems: 1
+ clock-names:
+ items:
+ - const: mfc
iommus:
- minItems: 1
maxItems: 2
+ iommus-names: false
examples:
- |
diff --git a/dts/upstream/Bindings/media/st,stm32-dcmipp.yaml b/dts/upstream/Bindings/media/st,stm32-dcmipp.yaml
new file mode 100644
index 0000000..87731f3
--- /dev/null
+++ b/dts/upstream/Bindings/media/st,stm32-dcmipp.yaml
@@ -0,0 +1,89 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/media/st,stm32-dcmipp.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: STMicroelectronics STM32 DCMIPP Digital Camera Memory Interface Pixel Processor
+
+maintainers:
+ - Hugues Fruchet <hugues.fruchet@foss.st.com>
+ - Alain Volmat <alain.volmat@foss.st.com>
+
+properties:
+ compatible:
+ const: st,stm32mp13-dcmipp
+
+ reg:
+ maxItems: 1
+
+ interrupts:
+ maxItems: 1
+
+ clocks:
+ maxItems: 1
+
+ resets:
+ maxItems: 1
+
+ port:
+ $ref: /schemas/graph.yaml#/$defs/port-base
+ unevaluatedProperties: false
+ description:
+ DCMIPP supports a single port node with parallel bus.
+
+ properties:
+ endpoint:
+ $ref: video-interfaces.yaml#
+ unevaluatedProperties: false
+
+ properties:
+ bus-type:
+ enum: [5, 6]
+ default: 5
+
+ bus-width:
+ enum: [8, 10, 12, 14]
+ default: 8
+
+ pclk-sample: true
+ hsync-active: true
+ vsync-active: true
+
+ required:
+ - pclk-sample
+
+required:
+ - compatible
+ - reg
+ - interrupts
+ - clocks
+ - resets
+ - port
+
+additionalProperties: false
+
+examples:
+ - |
+ #include <dt-bindings/interrupt-controller/arm-gic.h>
+ #include <dt-bindings/clock/stm32mp13-clks.h>
+ #include <dt-bindings/reset/stm32mp13-resets.h>
+ dcmipp@5a000000 {
+ compatible = "st,stm32mp13-dcmipp";
+ reg = <0x5a000000 0x400>;
+ interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>;
+ resets = <&rcc DCMIPP_R>;
+ clocks = <&rcc DCMIPP_K>;
+
+ port {
+ endpoint {
+ remote-endpoint = <&mipid02_2>;
+ bus-width = <8>;
+ hsync-active = <0>;
+ vsync-active = <0>;
+ pclk-sample = <0>;
+ };
+ };
+ };
+
+...
diff --git a/dts/upstream/Bindings/media/starfive,jh7110-camss.yaml b/dts/upstream/Bindings/media/starfive,jh7110-camss.yaml
new file mode 100644
index 0000000..c66586d
--- /dev/null
+++ b/dts/upstream/Bindings/media/starfive,jh7110-camss.yaml
@@ -0,0 +1,180 @@
+# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/media/starfive,jh7110-camss.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Starfive SoC CAMSS ISP
+
+maintainers:
+ - Jack Zhu <jack.zhu@starfivetech.com>
+ - Changhuang Liang <changhuang.liang@starfivetech.com>
+
+description:
+ The Starfive CAMSS ISP is a Camera interface for Starfive JH7110 SoC. It
+ consists of a VIN controller (Video In Controller, a top-level control unit)
+ and an ISP.
+
+properties:
+ compatible:
+ const: starfive,jh7110-camss
+
+ reg:
+ maxItems: 2
+
+ reg-names:
+ items:
+ - const: syscon
+ - const: isp
+
+ clocks:
+ maxItems: 7
+
+ clock-names:
+ items:
+ - const: apb_func
+ - const: wrapper_clk_c
+ - const: dvp_inv
+ - const: axiwr
+ - const: mipi_rx0_pxl
+ - const: ispcore_2x
+ - const: isp_axi
+
+ resets:
+ maxItems: 6
+
+ reset-names:
+ items:
+ - const: wrapper_p
+ - const: wrapper_c
+ - const: axird
+ - const: axiwr
+ - const: isp_top_n
+ - const: isp_top_axi
+
+ power-domains:
+ items:
+ - description: JH7110 ISP Power Domain Switch Controller.
+
+ interrupts:
+ maxItems: 4
+
+ ports:
+ $ref: /schemas/graph.yaml#/properties/ports
+
+ properties:
+ port@0:
+ $ref: /schemas/graph.yaml#/$defs/port-base
+ unevaluatedProperties: false
+ description: Input port for receiving DVP data.
+
+ properties:
+ endpoint:
+ $ref: video-interfaces.yaml#
+ unevaluatedProperties: false
+
+ properties:
+ bus-type:
+ enum: [5, 6]
+
+ bus-width:
+ enum: [8, 10, 12]
+
+ data-shift:
+ enum: [0, 2]
+ default: 0
+
+ hsync-active:
+ enum: [0, 1]
+ default: 1
+
+ vsync-active:
+ enum: [0, 1]
+ default: 1
+
+ required:
+ - bus-type
+ - bus-width
+
+ port@1:
+ $ref: /schemas/graph.yaml#/properties/port
+ description: Input port for receiving CSI data.
+
+ required:
+ - port@0
+ - port@1
+
+required:
+ - compatible
+ - reg
+ - reg-names
+ - clocks
+ - clock-names
+ - resets
+ - reset-names
+ - power-domains
+ - interrupts
+ - ports
+
+additionalProperties: false
+
+examples:
+ - |
+ isp@19840000 {
+ compatible = "starfive,jh7110-camss";
+ reg = <0x19840000 0x10000>,
+ <0x19870000 0x30000>;
+ reg-names = "syscon", "isp";
+ clocks = <&ispcrg 0>,
+ <&ispcrg 13>,
+ <&ispcrg 2>,
+ <&ispcrg 12>,
+ <&ispcrg 1>,
+ <&syscrg 51>,
+ <&syscrg 52>;
+ clock-names = "apb_func",
+ "wrapper_clk_c",
+ "dvp_inv",
+ "axiwr",
+ "mipi_rx0_pxl",
+ "ispcore_2x",
+ "isp_axi";
+ resets = <&ispcrg 0>,
+ <&ispcrg 1>,
+ <&ispcrg 10>,
+ <&ispcrg 11>,
+ <&syscrg 41>,
+ <&syscrg 42>;
+ reset-names = "wrapper_p",
+ "wrapper_c",
+ "axird",
+ "axiwr",
+ "isp_top_n",
+ "isp_top_axi";
+ power-domains = <&pwrc 5>;
+ interrupts = <92>, <87>, <88>, <90>;
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ port@0 {
+ reg = <0>;
+ vin_from_sc2235: endpoint {
+ remote-endpoint = <&sc2235_to_vin>;
+ bus-type = <5>;
+ bus-width = <8>;
+ data-shift = <2>;
+ hsync-active = <1>;
+ vsync-active = <0>;
+ pclk-sample = <1>;
+ };
+ };
+
+ port@1 {
+ reg = <1>;
+ vin_from_csi2rx: endpoint {
+ remote-endpoint = <&csi2rx_to_vin>;
+ };
+ };
+ };
+ };
diff --git a/dts/upstream/Bindings/mfd/ams,as3711.yaml b/dts/upstream/Bindings/mfd/ams,as3711.yaml
new file mode 100644
index 0000000..ad8649c
--- /dev/null
+++ b/dts/upstream/Bindings/mfd/ams,as3711.yaml
@@ -0,0 +1,223 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/mfd/ams,as3711.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Austria MicroSystems AS3711 Quad Buck High Current PMIC with Charger
+
+maintainers:
+ - Guennadi Liakhovetski <guennadi.liakhovetski@linux.intel.com>
+
+description:
+ AS3711 is an I2C PMIC from Austria MicroSystems with multiple DC/DC and LDO
+ power supplies, a battery charger and an RTC. So far only bindings for the
+ two step-up DC/DC converters are defined.
+
+properties:
+ compatible:
+ const: ams,as3711
+
+ reg:
+ maxItems: 1
+
+ backlight:
+ description:
+ Step-up converter configuration, to be used as a backlight source
+ type: object
+ additionalProperties: false
+ properties:
+ compatible:
+ const: ams,as3711-bl
+
+ su1-dev:
+ description: Framebuffer phandle for the first step-up converter
+ $ref: /schemas/types.yaml#/definitions/phandle
+
+ su1-max-uA:
+ description: Maximum current for the first step-up converter
+ $ref: /schemas/types.yaml#/definitions/uint32
+
+ su2-dev:
+ description: Framebuffer phandle for the second step-up converter
+ $ref: /schemas/types.yaml#/definitions/phandle
+
+ su2-max-uA:
+ description: Maximum current for the second step-up converter
+ $ref: /schemas/types.yaml#/definitions/uint32
+
+ su2-feedback-voltage:
+ description: Second step-up converter uses voltage feedback
+ type: boolean
+
+ su2-feedback-curr1:
+ description:
+ Second step-up converter uses CURR1 input for current feedback
+ type: boolean
+
+ su2-feedback-curr2:
+ description:
+ Second step-up converter uses CURR2 input for current feedback
+ type: boolean
+
+ su2-feedback-curr3:
+ description:
+ Second step-up converter uses CURR3 input for current feedback
+ type: boolean
+
+ su2-feedback-curr-auto:
+ description:
+ Second step-up converter uses automatic current feedback selection
+ type: boolean
+
+ su2-fbprot-lx-sd4:
+ description:
+ Second step-up converter uses LX_SD4 for over-voltage protection
+ type: boolean
+
+ su2-fbprot-gpio2:
+ description:
+ Second step-up converter uses GPIO2 for over-voltage protection
+ type: boolean
+
+ su2-fbprot-gpio3:
+ description:
+ Second step-up converter uses GPIO3 for over-voltage protection
+ type: boolean
+
+ su2-fbprot-gpio4:
+ description:
+ Second step-up converter uses GPIO4 for over-voltage protection
+ type: boolean
+
+ su2-auto-curr1:
+ description:
+ Second step-up converter uses CURR1 input for automatic current
+ feedback
+ type: boolean
+
+ su2-auto-curr2:
+ description:
+ Second step-up converter uses CURR2 input for automatic current
+ feedback
+ type: boolean
+
+ su2-auto-curr3:
+ description:
+ Second step-up converter uses CURR3 input for automatic current
+ feedback
+ type: boolean
+
+ required:
+ - compatible
+
+ dependentRequired:
+ # To use the SU1 converter as a backlight source the following two
+ # properties must be provided:
+ su1-dev: [ su1-max-uA ]
+ su1-max-uA: [ su1-dev ]
+
+ # To use the SU2 converter as a backlight source the following two
+ # properties must be provided:
+ su2-dev: [ su2-max-uA ]
+ su2-max-uA: [ su2-dev ]
+
+ su2-feedback-voltage: [ su2-dev ]
+ su2-feedback-curr1: [ su2-dev ]
+ su2-feedback-curr2: [ su2-dev ]
+ su2-feedback-curr3: [ su2-dev ]
+ su2-feedback-curr-auto: [ su2-dev ]
+ su2-fbprot-lx-sd4: [ su2-dev ]
+ su2-fbprot-gpio2: [ su2-dev ]
+ su2-fbprot-gpio3: [ su2-dev ]
+ su2-fbprot-gpio4: [ su2-dev ]
+ su2-auto-curr1: [ su2-feedback-curr-auto ]
+ su2-auto-curr2: [ su2-feedback-curr-auto ]
+ su2-auto-curr3: [ su2-feedback-curr-auto ]
+
+ dependentSchemas:
+ su2-dev:
+ allOf:
+ - oneOf:
+ - required:
+ - su2-feedback-voltage
+ - required:
+ - su2-feedback-curr1
+ - required:
+ - su2-feedback-curr2
+ - required:
+ - su2-feedback-curr3
+ - required:
+ - su2-feedback-curr-auto
+ - oneOf:
+ - required:
+ - su2-fbprot-lx-sd4
+ - required:
+ - su2-fbprot-gpio2
+ - required:
+ - su2-fbprot-gpio3
+ - required:
+ - su2-fbprot-gpio4
+
+ su2-feedback-curr-auto:
+ anyOf:
+ - required:
+ - su2-auto-curr1
+ - required:
+ - su2-auto-curr2
+ - required:
+ - su2-auto-curr3
+
+ regulators:
+ description: Other DC/DC and LDO supplies
+ type: object
+ unevaluatedProperties: false
+ patternProperties:
+ "^(sd[1-4]|ldo[1-8])$":
+ type: object
+ $ref: /schemas/regulator/regulator.yaml#
+ unevaluatedProperties: false
+
+required:
+ - compatible
+ - reg
+
+additionalProperties: false
+
+examples:
+ - |
+ i2c {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ pmic@40 {
+ compatible = "ams,as3711";
+ reg = <0x40>;
+
+ regulators {
+ sd4 {
+ regulator-name = "1.215V";
+ regulator-min-microvolt = <1215000>;
+ regulator-max-microvolt = <1235000>;
+ };
+ ldo2 {
+ regulator-name = "2.8V CPU";
+ regulator-min-microvolt = <2800000>;
+ regulator-max-microvolt = <2800000>;
+ regulator-always-on;
+ regulator-boot-on;
+ };
+ };
+
+ backlight {
+ compatible = "ams,as3711-bl";
+ su2-dev = <&lcdc>;
+ su2-max-uA = <36000>;
+ su2-feedback-curr-auto;
+ su2-fbprot-gpio4;
+ su2-auto-curr1;
+ su2-auto-curr2;
+ su2-auto-curr3;
+ };
+ };
+ };
diff --git a/dts/upstream/Bindings/mfd/as3711.txt b/dts/upstream/Bindings/mfd/as3711.txt
deleted file mode 100644
index d98cf18..0000000
--- a/dts/upstream/Bindings/mfd/as3711.txt
+++ /dev/null
@@ -1,73 +0,0 @@
-AS3711 is an I2C PMIC from Austria MicroSystems with multiple DCDC and LDO power
-supplies, a battery charger and an RTC. So far only bindings for the two stepup
-DCDC converters are defined. Other DCDC and LDO supplies are configured, using
-standard regulator properties, they must belong to a sub-node, called
-"regulators" and be called "sd1" to "sd4" and "ldo1" to "ldo8." Stepup converter
-configuration should be placed in a subnode, called "backlight."
-
-Compulsory properties:
-- compatible : must be "ams,as3711"
-- reg : specifies the I2C address
-
-To use the SU1 converter as a backlight source the following two properties must
-be provided:
-- su1-dev : framebuffer phandle
-- su1-max-uA : maximum current
-
-To use the SU2 converter as a backlight source the following two properties must
-be provided:
-- su2-dev : framebuffer phandle
-- su1-max-uA : maximum current
-
-Additionally one of these properties must be provided to select the type of
-feedback used:
-- su2-feedback-voltage : voltage feedback is used
-- su2-feedback-curr1 : CURR1 input used for current feedback
-- su2-feedback-curr2 : CURR2 input used for current feedback
-- su2-feedback-curr3 : CURR3 input used for current feedback
-- su2-feedback-curr-auto: automatic current feedback selection
-
-and one of these to select the over-voltage protection pin
-- su2-fbprot-lx-sd4 : LX_SD4 is used for over-voltage protection
-- su2-fbprot-gpio2 : GPIO2 is used for over-voltage protection
-- su2-fbprot-gpio3 : GPIO3 is used for over-voltage protection
-- su2-fbprot-gpio4 : GPIO4 is used for over-voltage protection
-
-If "su2-feedback-curr-auto" is selected, one or more of the following properties
-have to be specified:
-- su2-auto-curr1 : use CURR1 input for current feedback
-- su2-auto-curr2 : use CURR2 input for current feedback
-- su2-auto-curr3 : use CURR3 input for current feedback
-
-Example:
-
-as3711@40 {
- compatible = "ams,as3711";
- reg = <0x40>;
-
- regulators {
- sd4 {
- regulator-name = "1.215V";
- regulator-min-microvolt = <1215000>;
- regulator-max-microvolt = <1235000>;
- };
- ldo2 {
- regulator-name = "2.8V CPU";
- regulator-min-microvolt = <2800000>;
- regulator-max-microvolt = <2800000>;
- regulator-always-on;
- regulator-boot-on;
- };
- };
-
- backlight {
- compatible = "ams,as3711-bl";
- su2-dev = <&lcdc>;
- su2-max-uA = <36000>;
- su2-feedback-curr-auto;
- su2-fbprot-gpio4;
- su2-auto-curr1;
- su2-auto-curr2;
- su2-auto-curr3;
- };
-};
diff --git a/dts/upstream/Bindings/mfd/hisilicon,hi6421-spmi-pmic.yaml b/dts/upstream/Bindings/mfd/hisilicon,hi6421-spmi-pmic.yaml
index bdff5b6..6a82435 100644
--- a/dts/upstream/Bindings/mfd/hisilicon,hi6421-spmi-pmic.yaml
+++ b/dts/upstream/Bindings/mfd/hisilicon,hi6421-spmi-pmic.yaml
@@ -17,7 +17,7 @@
node.
The SPMI controller part is provided by
- Documentation/devicetree/bindings/mfd/hisilicon,hi6421-spmi-pmic.yaml
+ Documentation/devicetree/bindings/spmi/hisilicon,hisi-spmi-controller.yaml
properties:
$nodename:
@@ -42,13 +42,6 @@
additionalProperties: false
- properties:
- '#address-cells':
- const: 1
-
- '#size-cells':
- const: 0
-
patternProperties:
'^ldo[0-9]+$':
type: object
@@ -66,72 +59,75 @@
examples:
- |
+ #include <dt-bindings/spmi/spmi.h>
- pmic: pmic@0 {
- compatible = "hisilicon,hi6421v600-spmi";
- reg = <0 0>;
+ spmi {
+ #address-cells = <2>;
+ #size-cells = <0>;
- #interrupt-cells = <2>;
- interrupt-controller;
- interrupt-parent = <&gpio28>;
- interrupts = <0 0>;
+ pmic@0 {
+ compatible = "hisilicon,hi6421v600-spmi";
+ reg = <0 SPMI_USID>;
- regulators {
- #address-cells = <1>;
- #size-cells = <0>;
+ #interrupt-cells = <2>;
+ interrupt-controller;
+ interrupt-parent = <&gpio28>;
+ interrupts = <0 0>;
- ldo3: ldo3 {
- regulator-name = "ldo3";
- regulator-min-microvolt = <1500000>;
- regulator-max-microvolt = <2000000>;
- regulator-boot-on;
- };
+ regulators {
+ ldo3 {
+ regulator-name = "ldo3";
+ regulator-min-microvolt = <1500000>;
+ regulator-max-microvolt = <2000000>;
+ regulator-boot-on;
+ };
- ldo4: ldo4 {
- regulator-name = "ldo4";
- regulator-min-microvolt = <1725000>;
- regulator-max-microvolt = <1900000>;
- regulator-boot-on;
- };
+ ldo4 {
+ regulator-name = "ldo4";
+ regulator-min-microvolt = <1725000>;
+ regulator-max-microvolt = <1900000>;
+ regulator-boot-on;
+ };
- ldo9: ldo9 {
- regulator-name = "ldo9";
- regulator-min-microvolt = <1750000>;
- regulator-max-microvolt = <3300000>;
- regulator-boot-on;
- };
+ ldo9 {
+ regulator-name = "ldo9";
+ regulator-min-microvolt = <1750000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-boot-on;
+ };
- ldo15: ldo15 {
- regulator-name = "ldo15";
- regulator-min-microvolt = <1800000>;
- regulator-max-microvolt = <3000000>;
- regulator-always-on;
- };
+ ldo15 {
+ regulator-name = "ldo15";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <3000000>;
+ regulator-always-on;
+ };
- ldo16: ldo16 {
- regulator-name = "ldo16";
- regulator-min-microvolt = <1800000>;
- regulator-max-microvolt = <3000000>;
- regulator-boot-on;
- };
+ ldo16 {
+ regulator-name = "ldo16";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <3000000>;
+ regulator-boot-on;
+ };
- ldo17: ldo17 {
- regulator-name = "ldo17";
- regulator-min-microvolt = <2500000>;
- regulator-max-microvolt = <3300000>;
- };
+ ldo17 {
+ regulator-name = "ldo17";
+ regulator-min-microvolt = <2500000>;
+ regulator-max-microvolt = <3300000>;
+ };
- ldo33: ldo33 {
- regulator-name = "ldo33";
- regulator-min-microvolt = <2500000>;
- regulator-max-microvolt = <3300000>;
- regulator-boot-on;
- };
+ ldo33 {
+ regulator-name = "ldo33";
+ regulator-min-microvolt = <2500000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-boot-on;
+ };
- ldo34: ldo34 {
- regulator-name = "ldo34";
- regulator-min-microvolt = <2600000>;
- regulator-max-microvolt = <3300000>;
+ ldo34 {
+ regulator-name = "ldo34";
+ regulator-min-microvolt = <2600000>;
+ regulator-max-microvolt = <3300000>;
+ };
+ };
};
- };
};
diff --git a/dts/upstream/Bindings/mfd/qcom,pm8008.yaml b/dts/upstream/Bindings/mfd/qcom,pm8008.yaml
index 9e4eed3..0c75d8b 100644
--- a/dts/upstream/Bindings/mfd/qcom,pm8008.yaml
+++ b/dts/upstream/Bindings/mfd/qcom,pm8008.yaml
@@ -99,10 +99,12 @@
- |
#include <dt-bindings/mfd/qcom-pm8008.h>
#include <dt-bindings/interrupt-controller/irq.h>
- qupv3_se13_i2c {
+
+ i2c {
#address-cells = <1>;
#size-cells = <0>;
- pm8008i@8 {
+
+ pmic@8 {
compatible = "qcom,pm8008";
reg = <0x8>;
#address-cells = <1>;
diff --git a/dts/upstream/Bindings/mfd/qcom,spmi-pmic.yaml b/dts/upstream/Bindings/mfd/qcom,spmi-pmic.yaml
index 9fa5686..8103fb6 100644
--- a/dts/upstream/Bindings/mfd/qcom,spmi-pmic.yaml
+++ b/dts/upstream/Bindings/mfd/qcom,spmi-pmic.yaml
@@ -66,6 +66,7 @@
- qcom,pm8841
- qcom,pm8909
- qcom,pm8916
+ - qcom,pm8937
- qcom,pm8941
- qcom,pm8950
- qcom,pm8953
@@ -134,9 +135,15 @@
type: object
$ref: /schemas/sound/qcom,pm8916-wcd-analog-codec.yaml#
+ "^battery@[0-9a-f]+$":
+ type: object
+ oneOf:
+ - $ref: /schemas/power/supply/qcom,pm8916-bms-vm.yaml#
+
"^charger@[0-9a-f]+$":
type: object
oneOf:
+ - $ref: /schemas/power/supply/qcom,pm8916-lbc.yaml#
- $ref: /schemas/power/supply/qcom,pm8941-charger.yaml#
- $ref: /schemas/power/supply/qcom,pm8941-coincell.yaml#
- $ref: /schemas/power/supply/qcom,pmi8998-charger.yaml#
diff --git a/dts/upstream/Bindings/mfd/qcom,tcsr.yaml b/dts/upstream/Bindings/mfd/qcom,tcsr.yaml
index 33c3d02..798705a 100644
--- a/dts/upstream/Bindings/mfd/qcom,tcsr.yaml
+++ b/dts/upstream/Bindings/mfd/qcom,tcsr.yaml
@@ -29,6 +29,8 @@
- qcom,sdx65-tcsr
- qcom,sm4450-tcsr
- qcom,sm8150-tcsr
+ - qcom,sm8250-tcsr
+ - qcom,sm8350-tcsr
- qcom,sm8450-tcsr
- qcom,tcsr-apq8064
- qcom,tcsr-apq8084
diff --git a/dts/upstream/Bindings/mfd/samsung,exynos5433-lpass.yaml b/dts/upstream/Bindings/mfd/samsung,exynos5433-lpass.yaml
index b97b068..f154103 100644
--- a/dts/upstream/Bindings/mfd/samsung,exynos5433-lpass.yaml
+++ b/dts/upstream/Bindings/mfd/samsung,exynos5433-lpass.yaml
@@ -85,7 +85,7 @@
};
i2s@11440000 {
- compatible = "samsung,exynos7-i2s";
+ compatible = "samsung,exynos5433-i2s", "samsung,exynos7-i2s";
reg = <0x11440000 0x100>;
dmas = <&adma 0>, <&adma 2>;
dma-names = "tx", "rx";
diff --git a/dts/upstream/Bindings/mfd/sprd,ums512-glbreg.yaml b/dts/upstream/Bindings/mfd/sprd,ums512-glbreg.yaml
index 996bd4a..a750fa2 100644
--- a/dts/upstream/Bindings/mfd/sprd,ums512-glbreg.yaml
+++ b/dts/upstream/Bindings/mfd/sprd,ums512-glbreg.yaml
@@ -19,7 +19,9 @@
properties:
compatible:
items:
- - const: sprd,ums512-glbregs
+ - enum:
+ - sprd,ums512-glbregs
+ - sprd,ums9620-glbregs
- const: syscon
- const: simple-mfd
diff --git a/dts/upstream/Bindings/mfd/ti,am3359-tscadc.yaml b/dts/upstream/Bindings/mfd/ti,am3359-tscadc.yaml
index 23a6326..70b5dfc 100644
--- a/dts/upstream/Bindings/mfd/ti,am3359-tscadc.yaml
+++ b/dts/upstream/Bindings/mfd/ti,am3359-tscadc.yaml
@@ -61,8 +61,6 @@
- interrupts
- clocks
- clock-names
- - dmas
- - dma-names
additionalProperties: false
diff --git a/dts/upstream/Bindings/misc/fsl,dpaa2-console.yaml b/dts/upstream/Bindings/misc/fsl,dpaa2-console.yaml
index 8cc951f..59b83ea 100644
--- a/dts/upstream/Bindings/misc/fsl,dpaa2-console.yaml
+++ b/dts/upstream/Bindings/misc/fsl,dpaa2-console.yaml
@@ -12,7 +12,7 @@
properties:
compatible:
- const: "fsl,dpaa2-console"
+ const: fsl,dpaa2-console
reg:
maxItems: 1
diff --git a/dts/upstream/Bindings/mmc/arasan,sdhci.yaml b/dts/upstream/Bindings/mmc/arasan,sdhci.yaml
index 3e99801..9075add 100644
--- a/dts/upstream/Bindings/mmc/arasan,sdhci.yaml
+++ b/dts/upstream/Bindings/mmc/arasan,sdhci.yaml
@@ -226,8 +226,8 @@
interrupt-parent = <&gic>;
interrupts = <0 48 4>;
reg = <0xff160000 0x1000>;
- clocks = <&clk200>, <&clk200>;
- clock-names = "clk_xin", "clk_ahb";
+ clocks = <&clk200>, <&clk200>, <&clk1200>;
+ clock-names = "clk_xin", "clk_ahb", "gate";
clock-output-names = "clk_out_sd0", "clk_in_sd0";
#clock-cells = <1>;
clk-phase-sd-hs = <63>, <72>;
@@ -239,8 +239,8 @@
interrupt-parent = <&gic>;
interrupts = <0 126 4>;
reg = <0xf1040000 0x10000>;
- clocks = <&clk200>, <&clk200>;
- clock-names = "clk_xin", "clk_ahb";
+ clocks = <&clk200>, <&clk200>, <&clk1200>;
+ clock-names = "clk_xin", "clk_ahb", "gate";
clock-output-names = "clk_out_sd0", "clk_in_sd0";
#clock-cells = <1>;
clk-phase-sd-hs = <132>, <60>;
diff --git a/dts/upstream/Bindings/mmc/arm,pl18x.yaml b/dts/upstream/Bindings/mmc/arm,pl18x.yaml
index 2459a55..940b126 100644
--- a/dts/upstream/Bindings/mmc/arm,pl18x.yaml
+++ b/dts/upstream/Bindings/mmc/arm,pl18x.yaml
@@ -203,7 +203,7 @@
bus-width = <4>;
cap-sd-highspeed;
cap-mmc-highspeed;
- cd-gpios = <&gpio2 31 0x4>;
+ cd-gpios = <&gpio2 31 0x4>;
st,sig-dir-dat0;
st,sig-dir-dat2;
st,sig-dir-cmd;
diff --git a/dts/upstream/Bindings/mmc/brcm,sdhci-brcmstb.yaml b/dts/upstream/Bindings/mmc/brcm,sdhci-brcmstb.yaml
index c028039..cbd3d6c 100644
--- a/dts/upstream/Bindings/mmc/brcm,sdhci-brcmstb.yaml
+++ b/dts/upstream/Bindings/mmc/brcm,sdhci-brcmstb.yaml
@@ -20,10 +20,8 @@
- const: brcm,sdhci-brcmstb
- items:
- enum:
+ - brcm,bcm74165b0-sdhci
- brcm,bcm7445-sdhci
- - const: brcm,sdhci-brcmstb
- - items:
- - enum:
- brcm,bcm7425-sdhci
- const: brcm,sdhci-brcmstb
diff --git a/dts/upstream/Bindings/mmc/marvell,xenon-sdhci.yaml b/dts/upstream/Bindings/mmc/marvell,xenon-sdhci.yaml
index 3a8e748..cfe6237 100644
--- a/dts/upstream/Bindings/mmc/marvell,xenon-sdhci.yaml
+++ b/dts/upstream/Bindings/mmc/marvell,xenon-sdhci.yaml
@@ -27,7 +27,9 @@
- marvell,armada-ap806-sdhci
- items:
- - const: marvell,armada-ap807-sdhci
+ - enum:
+ - marvell,armada-ap807-sdhci
+ - marvell,ac5-sdhci
- const: marvell,armada-ap806-sdhci
- items:
diff --git a/dts/upstream/Bindings/mmc/mtk-sd.yaml b/dts/upstream/Bindings/mmc/mtk-sd.yaml
index 3fffa46..c532ec9 100644
--- a/dts/upstream/Bindings/mmc/mtk-sd.yaml
+++ b/dts/upstream/Bindings/mmc/mtk-sd.yaml
@@ -145,6 +145,15 @@
minimum: 0
maximum: 7
+ mediatek,tuning-step:
+ $ref: /schemas/types.yaml#/definitions/uint32
+ description:
+ Some SoCs need extend tuning step for better delay value to avoid CRC issue.
+ If not present, default tuning step is 32. For eMMC and SD, this can yield
+ satisfactory calibration results in most cases.
+ enum: [32, 64]
+ default: 32
+
resets:
maxItems: 1
diff --git a/dts/upstream/Bindings/mmc/renesas,sdhi.yaml b/dts/upstream/Bindings/mmc/renesas,sdhi.yaml
index 94e2287..f7a4c6b 100644
--- a/dts/upstream/Bindings/mmc/renesas,sdhi.yaml
+++ b/dts/upstream/Bindings/mmc/renesas,sdhi.yaml
@@ -56,7 +56,7 @@
- renesas,sdhi-r8a77980 # R-Car V3H
- renesas,sdhi-r8a77990 # R-Car E3
- renesas,sdhi-r8a77995 # R-Car D3
- - renesas,sdhi-r9a07g043 # RZ/G2UL
+ - renesas,sdhi-r9a07g043 # RZ/G2UL and RZ/Five
- renesas,sdhi-r9a07g044 # RZ/G2{L,LC}
- renesas,sdhi-r9a07g054 # RZ/V2L
- renesas,sdhi-r9a08g045 # RZ/G3S
diff --git a/dts/upstream/Bindings/mmc/samsung,exynos-dw-mshc.yaml b/dts/upstream/Bindings/mmc/samsung,exynos-dw-mshc.yaml
index 6ee78a3..5fe6579 100644
--- a/dts/upstream/Bindings/mmc/samsung,exynos-dw-mshc.yaml
+++ b/dts/upstream/Bindings/mmc/samsung,exynos-dw-mshc.yaml
@@ -14,15 +14,22 @@
properties:
compatible:
- enum:
- - samsung,exynos4210-dw-mshc
- - samsung,exynos4412-dw-mshc
- - samsung,exynos5250-dw-mshc
- - samsung,exynos5420-dw-mshc
- - samsung,exynos5420-dw-mshc-smu
- - samsung,exynos7-dw-mshc
- - samsung,exynos7-dw-mshc-smu
- - axis,artpec8-dw-mshc
+ oneOf:
+ - enum:
+ - axis,artpec8-dw-mshc
+ - samsung,exynos4210-dw-mshc
+ - samsung,exynos4412-dw-mshc
+ - samsung,exynos5250-dw-mshc
+ - samsung,exynos5420-dw-mshc
+ - samsung,exynos5420-dw-mshc-smu
+ - samsung,exynos7-dw-mshc
+ - samsung,exynos7-dw-mshc-smu
+ - items:
+ - enum:
+ - samsung,exynos5433-dw-mshc-smu
+ - samsung,exynos7885-dw-mshc-smu
+ - samsung,exynos850-dw-mshc-smu
+ - const: samsung,exynos7-dw-mshc-smu
reg:
maxItems: 1
diff --git a/dts/upstream/Bindings/mmc/sdhci-msm.yaml b/dts/upstream/Bindings/mmc/sdhci-msm.yaml
index 86fae73..c24c537 100644
--- a/dts/upstream/Bindings/mmc/sdhci-msm.yaml
+++ b/dts/upstream/Bindings/mmc/sdhci-msm.yaml
@@ -22,6 +22,8 @@
- items:
- enum:
- qcom,apq8084-sdhci
+ - qcom,ipq4019-sdhci
+ - qcom,ipq8074-sdhci
- qcom,msm8226-sdhci
- qcom,msm8953-sdhci
- qcom,msm8974-sdhci
diff --git a/dts/upstream/Bindings/mmc/sdhci-pxa.yaml b/dts/upstream/Bindings/mmc/sdhci-pxa.yaml
index 09455f9..4869dde 100644
--- a/dts/upstream/Bindings/mmc/sdhci-pxa.yaml
+++ b/dts/upstream/Bindings/mmc/sdhci-pxa.yaml
@@ -18,7 +18,7 @@
const: marvell,armada-380-sdhci
then:
properties:
- regs:
+ reg:
minItems: 3
reg-names:
minItems: 3
@@ -26,7 +26,7 @@
- reg-names
else:
properties:
- regs:
+ reg:
maxItems: 1
reg-names:
maxItems: 1
diff --git a/dts/upstream/Bindings/mmc/snps,dwcmshc-sdhci.yaml b/dts/upstream/Bindings/mmc/snps,dwcmshc-sdhci.yaml
index a43eb83..42804d9 100644
--- a/dts/upstream/Bindings/mmc/snps,dwcmshc-sdhci.yaml
+++ b/dts/upstream/Bindings/mmc/snps,dwcmshc-sdhci.yaml
@@ -19,6 +19,7 @@
- rockchip,rk3568-dwcmshc
- rockchip,rk3588-dwcmshc
- snps,dwcmshc-sdhci
+ - thead,th1520-dwcmshc
reg:
maxItems: 1
diff --git a/dts/upstream/Bindings/mmc/synopsys-dw-mshc.yaml b/dts/upstream/Bindings/mmc/synopsys-dw-mshc.yaml
index b13b516..a629277 100644
--- a/dts/upstream/Bindings/mmc/synopsys-dw-mshc.yaml
+++ b/dts/upstream/Bindings/mmc/synopsys-dw-mshc.yaml
@@ -35,6 +35,9 @@
- const: biu
- const: ciu
+ iommus:
+ maxItems: 1
+
altr,sysmgr-syscon:
$ref: /schemas/types.yaml#/definitions/phandle-array
items:
@@ -62,6 +65,7 @@
altr,sysmgr-syscon: true
else:
properties:
+ iommus: false
altr,sysmgr-syscon: false
required:
diff --git a/dts/upstream/Bindings/mtd/partitions/u-boot.yaml b/dts/upstream/Bindings/mtd/partitions/u-boot.yaml
index 3c56efe..327fa87 100644
--- a/dts/upstream/Bindings/mtd/partitions/u-boot.yaml
+++ b/dts/upstream/Bindings/mtd/partitions/u-boot.yaml
@@ -7,7 +7,7 @@
title: U-Boot bootloader partition
description: |
- U-Boot is a bootlodaer commonly used in embedded devices. It's almost always
+ U-Boot is a bootloader commonly used in embedded devices. It's almost always
located on some kind of flash device.
Device configuration is stored as a set of environment variables that are
diff --git a/dts/upstream/Bindings/net/dsa/dsa.yaml b/dts/upstream/Bindings/net/dsa/dsa.yaml
index 6107189..2abd036 100644
--- a/dts/upstream/Bindings/net/dsa/dsa.yaml
+++ b/dts/upstream/Bindings/net/dsa/dsa.yaml
@@ -46,4 +46,10 @@
$ref: dsa-port.yaml#
unevaluatedProperties: false
+oneOf:
+ - required:
+ - ports
+ - required:
+ - ethernet-ports
+
...
diff --git a/dts/upstream/Bindings/net/dsa/marvell,mv88e6060.yaml b/dts/upstream/Bindings/net/dsa/marvell,mv88e6060.yaml
new file mode 100644
index 0000000..4f1adf0
--- /dev/null
+++ b/dts/upstream/Bindings/net/dsa/marvell,mv88e6060.yaml
@@ -0,0 +1,88 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/net/dsa/marvell,mv88e6060.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Marvell MV88E6060 DSA switch
+
+maintainers:
+ - Andrew Lunn <andrew@lunn.ch>
+
+description:
+ The Marvell MV88E6060 switch has been produced and sold by Marvell
+ since at least 2008. The switch has one pin ADDR4 that controls the
+ MDIO address of the switch to be 0x10 or 0x00, and on the MDIO bus
+ connected to the switch, the PHYs inside the switch appear as
+ independent devices on address 0x00-0x04 or 0x10-0x14, so in difference
+ from many other DSA switches this switch does not have an internal
+ MDIO bus for the PHY devices.
+
+properties:
+ compatible:
+ const: marvell,mv88e6060
+ description:
+ The MV88E6060 is the oldest Marvell DSA switch product, and
+ as such a bit limited in features compared to later hardware.
+
+ reg:
+ maxItems: 1
+
+ reset-gpios:
+ description:
+ GPIO to be used to reset the whole device
+ maxItems: 1
+
+allOf:
+ - $ref: dsa.yaml#/$defs/ethernet-ports
+
+required:
+ - compatible
+ - reg
+
+unevaluatedProperties: false
+
+examples:
+ - |
+ #include <dt-bindings/gpio/gpio.h>
+ #include <dt-bindings/interrupt-controller/irq.h>
+ mdio {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ ethernet-switch@16 {
+ compatible = "marvell,mv88e6060";
+ reg = <16>;
+
+ ethernet-ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ ethernet-port@0 {
+ reg = <0>;
+ label = "lan1";
+ };
+ ethernet-port@1 {
+ reg = <1>;
+ label = "lan2";
+ };
+ ethernet-port@2 {
+ reg = <2>;
+ label = "lan3";
+ };
+ ethernet-port@3 {
+ reg = <3>;
+ label = "lan4";
+ };
+ ethernet-port@5 {
+ reg = <5>;
+ phy-mode = "rev-mii";
+ ethernet = <ðc>;
+ fixed-link {
+ speed = <100>;
+ full-duplex;
+ };
+ };
+ };
+ };
+ };
diff --git a/dts/upstream/Bindings/net/dsa/marvell,mv88e6xxx.yaml b/dts/upstream/Bindings/net/dsa/marvell,mv88e6xxx.yaml
new file mode 100644
index 0000000..19f15bd
--- /dev/null
+++ b/dts/upstream/Bindings/net/dsa/marvell,mv88e6xxx.yaml
@@ -0,0 +1,337 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/net/dsa/marvell,mv88e6xxx.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Marvell MV88E6xxx DSA switch family
+
+maintainers:
+ - Andrew Lunn <andrew@lunn.ch>
+
+description:
+ The Marvell MV88E6xxx switch series has been produced and sold
+ by Marvell since at least 2008. The switch has a few compatibles which
+ just indicate the base address of the switch, then operating systems
+ can investigate switch ID registers to find out which actual version
+ of the switch it is dealing with.
+
+properties:
+ compatible:
+ oneOf:
+ - enum:
+ - marvell,mv88e6085
+ - marvell,mv88e6190
+ - marvell,mv88e6250
+ description: |
+ marvell,mv88e6085: This switch uses base address 0x10.
+ This switch and its siblings will be autodetected from
+ ID registers found in the switch, so only "marvell,mv88e6085" should be
+ specified. This includes the following list of MV88Exxxx switches:
+ 6085, 6095, 6097, 6123, 6131, 6141, 6161, 6165, 6171, 6172, 6175, 6176,
+ 6185, 6240, 6320, 6321, 6341, 6350, 6351, 6352
+ marvell,mv88e6190: This switch uses base address 0x00.
+ This switch and its siblings will be autodetected from
+ ID registers found in the switch, so only "marvell,mv88e6190" should be
+ specified. This includes the following list of MV88Exxxx switches:
+ 6190, 6190X, 6191, 6290, 6361, 6390, 6390X
+ marvell,mv88e6250: This switch uses base address 0x08 or 0x18.
+ This switch and its siblings will be autodetected from
+ ID registers found in the switch, so only "marvell,mv88e6250" should be
+ specified. This includes the following list of MV88Exxxx switches:
+ 6220, 6250
+ - items:
+ - const: marvell,turris-mox-mv88e6085
+ - const: marvell,mv88e6085
+ - items:
+ - const: marvell,turris-mox-mv88e6190
+ - const: marvell,mv88e6190
+
+ reg:
+ maxItems: 1
+
+ eeprom-length:
+ $ref: /schemas/types.yaml#/definitions/uint32
+ description: Set to the length of an EEPROM connected to the switch. Must be
+ set if the switch can not detect the presence and/or size of a connected
+ EEPROM, otherwise optional.
+
+ reset-gpios:
+ description:
+ GPIO to be used to reset the whole device
+ maxItems: 1
+
+ interrupts:
+ description: The switch provides an external interrupt line, but it is
+ not always used by target systems.
+ maxItems: 1
+
+ interrupt-controller:
+ description: The switch has an internal interrupt controller used by
+ the different sub-blocks.
+
+ '#interrupt-cells':
+ description: The internal interrupt controller only supports triggering
+ on active high level interrupts so the second cell must alway be set to
+ IRQ_TYPE_LEVEL_HIGH.
+ const: 2
+
+ mdio:
+ $ref: /schemas/net/mdio.yaml#
+ unevaluatedProperties: false
+ description: Marvell MV88E6xxx switches have an varying combination of
+ internal and external MDIO buses, in some cases a combined bus that
+ can be used both internally and externally. This node is for the
+ primary bus, used internally and sometimes also externally.
+
+ mdio-external:
+ $ref: /schemas/net/mdio.yaml#
+ unevaluatedProperties: false
+ description: Marvell MV88E6xxx switches that have a separate external
+ MDIO bus use this port to access external components on the MDIO bus.
+
+ properties:
+ compatible:
+ const: marvell,mv88e6xxx-mdio-external
+
+ required:
+ - compatible
+
+allOf:
+ - $ref: dsa.yaml#/$defs/ethernet-ports
+
+required:
+ - compatible
+ - reg
+
+unevaluatedProperties: false
+
+examples:
+ - |
+ #include <dt-bindings/gpio/gpio.h>
+ mdio {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ ethernet-switch@0 {
+ compatible = "marvell,mv88e6085";
+ reg = <0>;
+ reset-gpios = <&gpio5 1 GPIO_ACTIVE_LOW>;
+
+ mdio {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ sw_phy0: ethernet-phy@0 {
+ reg = <0x0>;
+ };
+
+ sw_phy1: ethernet-phy@1 {
+ reg = <0x1>;
+ };
+
+ sw_phy2: ethernet-phy@2 {
+ reg = <0x2>;
+ };
+
+ sw_phy3: ethernet-phy@3 {
+ reg = <0x3>;
+ };
+ };
+
+ ethernet-ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ ethernet-port@0 {
+ reg = <0>;
+ label = "lan4";
+ phy-handle = <&sw_phy0>;
+ phy-mode = "internal";
+ };
+
+ ethernet-port@1 {
+ reg = <1>;
+ label = "lan3";
+ phy-handle = <&sw_phy1>;
+ phy-mode = "internal";
+ };
+
+ ethernet-port@2 {
+ reg = <2>;
+ label = "lan2";
+ phy-handle = <&sw_phy2>;
+ phy-mode = "internal";
+ };
+
+ ethernet-port@3 {
+ reg = <3>;
+ label = "lan1";
+ phy-handle = <&sw_phy3>;
+ phy-mode = "internal";
+ };
+
+ ethernet-port@5 {
+ reg = <5>;
+ ethernet = <&fec>;
+ phy-mode = "rgmii-id";
+
+ fixed-link {
+ speed = <1000>;
+ full-duplex;
+ };
+ };
+ };
+ };
+ };
+ - |
+ #include <dt-bindings/interrupt-controller/irq.h>
+ mdio {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ ethernet-switch@0 {
+ compatible = "marvell,mv88e6190";
+ #interrupt-cells = <2>;
+ interrupt-controller;
+ interrupt-parent = <&gpio1>;
+ interrupts = <7 IRQ_TYPE_LEVEL_LOW>;
+ pinctrl-0 = <&switch_interrupt_pins>;
+ pinctrl-names = "default";
+ reg = <0>;
+
+ mdio {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ switch0phy1: ethernet-phy@1 {
+ reg = <0x1>;
+ };
+
+ switch0phy2: ethernet-phy@2 {
+ reg = <0x2>;
+ };
+
+ switch0phy3: ethernet-phy@3 {
+ reg = <0x3>;
+ };
+
+ switch0phy4: ethernet-phy@4 {
+ reg = <0x4>;
+ };
+
+ switch0phy5: ethernet-phy@5 {
+ reg = <0x5>;
+ };
+
+ switch0phy6: ethernet-phy@6 {
+ reg = <0x6>;
+ };
+
+ switch0phy7: ethernet-phy@7 {
+ reg = <0x7>;
+ };
+
+ switch0phy8: ethernet-phy@8 {
+ reg = <0x8>;
+ };
+ };
+
+ mdio-external {
+ compatible = "marvell,mv88e6xxx-mdio-external";
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ phy1: ethernet-phy@b {
+ reg = <0xb>;
+ compatible = "ethernet-phy-ieee802.3-c45";
+ };
+
+ phy2: ethernet-phy@c {
+ reg = <0xc>;
+ compatible = "ethernet-phy-ieee802.3-c45";
+ };
+ };
+
+ ethernet-ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ ethernet-port@0 {
+ ethernet = <ð0>;
+ phy-mode = "rgmii";
+ reg = <0>;
+
+ fixed-link {
+ full-duplex;
+ pause;
+ speed = <1000>;
+ };
+ };
+
+ ethernet-port@1 {
+ label = "lan1";
+ phy-handle = <&switch0phy1>;
+ reg = <1>;
+ };
+
+ ethernet-port@2 {
+ label = "lan2";
+ phy-handle = <&switch0phy2>;
+ reg = <2>;
+ };
+
+ ethernet-port@3 {
+ label = "lan3";
+ phy-handle = <&switch0phy3>;
+ reg = <3>;
+ };
+
+ ethernet-port@4 {
+ label = "lan4";
+ phy-handle = <&switch0phy4>;
+ reg = <4>;
+ };
+
+ ethernet-port@5 {
+ label = "lan5";
+ phy-handle = <&switch0phy5>;
+ reg = <5>;
+ };
+
+ ethernet-port@6 {
+ label = "lan6";
+ phy-handle = <&switch0phy6>;
+ reg = <6>;
+ };
+
+ ethernet-port@7 {
+ label = "lan7";
+ phy-handle = <&switch0phy7>;
+ reg = <7>;
+ };
+
+ ethernet-port@8 {
+ label = "lan8";
+ phy-handle = <&switch0phy8>;
+ reg = <8>;
+ };
+
+ ethernet-port@9 {
+ /* 88X3310P external phy */
+ label = "lan9";
+ phy-handle = <&phy1>;
+ phy-mode = "xaui";
+ reg = <9>;
+ };
+
+ ethernet-port@a {
+ /* 88X3310P external phy */
+ label = "lan10";
+ phy-handle = <&phy2>;
+ phy-mode = "xaui";
+ reg = <0xa>;
+ };
+ };
+ };
+ };
diff --git a/dts/upstream/Bindings/net/dsa/marvell.txt b/dts/upstream/Bindings/net/dsa/marvell.txt
deleted file mode 100644
index 6ec0c18..0000000
--- a/dts/upstream/Bindings/net/dsa/marvell.txt
+++ /dev/null
@@ -1,109 +0,0 @@
-Marvell DSA Switch Device Tree Bindings
----------------------------------------
-
-WARNING: This binding is currently unstable. Do not program it into a
-FLASH never to be changed again. Once this binding is stable, this
-warning will be removed.
-
-If you need a stable binding, use the old dsa.txt binding.
-
-Marvell Switches are MDIO devices. The following properties should be
-placed as a child node of an mdio device.
-
-The properties described here are those specific to Marvell devices.
-Additional required and optional properties can be found in dsa.txt.
-
-The compatibility string is used only to find an identification register,
-which is at a different MDIO base address in different switch families.
-- "marvell,mv88e6085" : Switch has base address 0x10. Use with models:
- 6085, 6095, 6097, 6123, 6131, 6141, 6161, 6165,
- 6171, 6172, 6175, 6176, 6185, 6240, 6320, 6321,
- 6341, 6350, 6351, 6352
-- "marvell,mv88e6190" : Switch has base address 0x00. Use with models:
- 6190, 6190X, 6191, 6290, 6361, 6390, 6390X
-- "marvell,mv88e6250" : Switch has base address 0x08 or 0x18. Use with model:
- 6220, 6250
-
-Required properties:
-- compatible : Should be one of "marvell,mv88e6085",
- "marvell,mv88e6190" or "marvell,mv88e6250" as
- indicated above
-- reg : Address on the MII bus for the switch.
-
-Optional properties:
-
-- reset-gpios : Should be a gpio specifier for a reset line
-- interrupts : Interrupt from the switch
-- interrupt-controller : Indicates the switch is itself an interrupt
- controller. This is used for the PHY interrupts.
-#interrupt-cells = <2> : Controller uses two cells, number and flag
-- eeprom-length : Set to the length of an EEPROM connected to the
- switch. Must be set if the switch can not detect
- the presence and/or size of a connected EEPROM,
- otherwise optional.
-- mdio : Container of PHY and devices on the switches MDIO
- bus.
-- mdio? : Container of PHYs and devices on the external MDIO
- bus. The node must contains a compatible string of
- "marvell,mv88e6xxx-mdio-external"
-
-Example:
-
- mdio {
- #address-cells = <1>;
- #size-cells = <0>;
- interrupt-parent = <&gpio0>;
- interrupts = <27 IRQ_TYPE_LEVEL_LOW>;
- interrupt-controller;
- #interrupt-cells = <2>;
-
- switch0: switch@0 {
- compatible = "marvell,mv88e6085";
- reg = <0>;
- reset-gpios = <&gpio5 1 GPIO_ACTIVE_LOW>;
-
- mdio {
- #address-cells = <1>;
- #size-cells = <0>;
- switch1phy0: switch1phy0@0 {
- reg = <0>;
- interrupt-parent = <&switch0>;
- interrupts = <0 IRQ_TYPE_LEVEL_HIGH>;
- };
- };
- };
- };
-
- mdio {
- #address-cells = <1>;
- #size-cells = <0>;
- interrupt-parent = <&gpio0>;
- interrupts = <27 IRQ_TYPE_LEVEL_LOW>;
- interrupt-controller;
- #interrupt-cells = <2>;
-
- switch0: switch@0 {
- compatible = "marvell,mv88e6190";
- reg = <0>;
- reset-gpios = <&gpio5 1 GPIO_ACTIVE_LOW>;
-
- mdio {
- #address-cells = <1>;
- #size-cells = <0>;
- switch1phy0: switch1phy0@0 {
- reg = <0>;
- interrupt-parent = <&switch0>;
- interrupts = <0 IRQ_TYPE_LEVEL_HIGH>;
- };
- };
-
- mdio1 {
- compatible = "marvell,mv88e6xxx-mdio-external";
- #address-cells = <1>;
- #size-cells = <0>;
- switch1phy9: switch1phy0@9 {
- reg = <9>;
- };
- };
- };
- };
diff --git a/dts/upstream/Bindings/net/dsa/microchip,ksz.yaml b/dts/upstream/Bindings/net/dsa/microchip,ksz.yaml
index b3029c6..c963dc0 100644
--- a/dts/upstream/Bindings/net/dsa/microchip,ksz.yaml
+++ b/dts/upstream/Bindings/net/dsa/microchip,ksz.yaml
@@ -11,7 +11,6 @@
- Woojung Huh <Woojung.Huh@microchip.com>
allOf:
- - $ref: dsa.yaml#/$defs/ethernet-ports
- $ref: /schemas/spi/spi-peripheral-props.yaml#
properties:
@@ -78,6 +77,39 @@
- compatible
- reg
+if:
+ not:
+ properties:
+ compatible:
+ enum:
+ - microchip,ksz8863
+ - microchip,ksz8873
+then:
+ $ref: dsa.yaml#/$defs/ethernet-ports
+else:
+ patternProperties:
+ "^(ethernet-)?ports$":
+ patternProperties:
+ "^(ethernet-)?port@[0-2]$":
+ $ref: dsa-port.yaml#
+ unevaluatedProperties: false
+ properties:
+ microchip,rmii-clk-internal:
+ $ref: /schemas/types.yaml#/definitions/flag
+ description:
+ When ksz88x3 is acting as clock provier (via REFCLKO) it
+ can select between internal and external RMII reference
+ clock. Internal reference clock means that the clock for
+ the RMII of ksz88x3 is provided by the ksz88x3 internally
+ and the REFCLKI pin is unconnected. For the external
+ reference clock, the clock needs to be fed back to ksz88x3
+ via REFCLKI.
+ If microchip,rmii-clk-internal is set, ksz88x3 will provide
+ rmii reference clock internally, otherwise reference clock
+ should be provided externally.
+ dependencies:
+ microchip,rmii-clk-internal: [ethernet]
+
unevaluatedProperties: false
examples:
diff --git a/dts/upstream/Bindings/net/ethernet-switch.yaml b/dts/upstream/Bindings/net/ethernet-switch.yaml
index 72ac67c..b3b7e1a 100644
--- a/dts/upstream/Bindings/net/ethernet-switch.yaml
+++ b/dts/upstream/Bindings/net/ethernet-switch.yaml
@@ -20,9 +20,26 @@
select: false
-properties:
- $nodename:
- pattern: "^(ethernet-)?switch(@.*)?$"
+allOf:
+ # This condition is here to satisfy the case where certain device
+ # nodes have to preserve non-standard names because of
+ # backward-compatibility with boot loaders inspecting certain
+ # node names.
+ - if:
+ properties:
+ compatible:
+ contains:
+ enum:
+ - marvell,turris-mox-mv88e6085
+ - marvell,turris-mox-mv88e6190
+ then:
+ properties:
+ $nodename:
+ pattern: "switch[0-3]@[0-3]+$"
+ else:
+ properties:
+ $nodename:
+ pattern: "^(ethernet-)?switch(@.*)?$"
patternProperties:
"^(ethernet-)?ports$":
diff --git a/dts/upstream/Bindings/net/lantiq,pef2256.yaml b/dts/upstream/Bindings/net/lantiq,pef2256.yaml
new file mode 100644
index 0000000..7da8370
--- /dev/null
+++ b/dts/upstream/Bindings/net/lantiq,pef2256.yaml
@@ -0,0 +1,213 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/net/lantiq,pef2256.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Lantiq PEF2256
+
+maintainers:
+ - Herve Codina <herve.codina@bootlin.com>
+
+description:
+ The Lantiq PEF2256, also known as Infineon PEF2256 or FALC56, is a framer and
+ line interface component designed to fulfill all required interfacing between
+ an analog E1/T1/J1 line and the digital PCM system highway/H.100 bus.
+
+properties:
+ compatible:
+ items:
+ - const: lantiq,pef2256
+
+ reg:
+ maxItems: 1
+
+ clocks:
+ items:
+ - description: Master Clock
+ - description: System Clock Receive
+ - description: System Clock Transmit
+
+ clock-names:
+ items:
+ - const: mclk
+ - const: sclkr
+ - const: sclkx
+
+ interrupts:
+ maxItems: 1
+
+ reset-gpios:
+ description:
+ GPIO used to reset the device.
+ maxItems: 1
+
+ pinctrl:
+ $ref: /schemas/pinctrl/pinctrl.yaml#
+ additionalProperties: false
+
+ patternProperties:
+ '-pins$':
+ type: object
+ $ref: /schemas/pinctrl/pinmux-node.yaml#
+ additionalProperties: false
+
+ properties:
+ pins:
+ enum: [ RPA, RPB, RPC, RPD, XPA, XPB, XPC, XPD ]
+
+ function:
+ enum: [ SYPR, RFM, RFMB, RSIGM, RSIG, DLR, FREEZE, RFSP, LOS,
+ SYPX, XFMS, XSIG, TCLK, XMFB, XSIGM, DLX, XCLK, XLT,
+ GPI, GPOH, GPOL ]
+
+ required:
+ - pins
+ - function
+
+ lantiq,data-rate-bps:
+ enum: [2048000, 4096000, 8192000, 16384000]
+ default: 2048000
+ description:
+ Data rate (bit per seconds) on the system highway.
+
+ lantiq,clock-falling-edge:
+ $ref: /schemas/types.yaml#/definitions/flag
+ description:
+ Data is sent on falling edge of the clock (and received on the rising
+ edge). If 'clock-falling-edge' is not present, data is sent on the
+ rising edge (and received on the falling edge).
+
+ lantiq,channel-phase:
+ $ref: /schemas/types.yaml#/definitions/uint32
+ enum: [0, 1, 2, 3, 4, 5, 6, 7]
+ default: 0
+ description: |
+ The pef2256 delivers a full frame (32 8-bit time-slots in E1 and 24 8-bit
+ time-slots 8 8-bit signaling in E1/J1) every 125us. This lead to a data
+ rate of 2048000 bit/s. When lantiq,data-rate-bps is more than 2048000
+ bit/s, the data (all 32 8-bit) present in the frame are interleave with
+ unused time-slots. The lantiq,channel-phase property allows to set the
+ correct alignment of the interleave mechanism.
+ For instance, suppose lantiq,data-rate-bps = 8192000 (ie 4*2048000), and
+ lantiq,channel-phase = 2, the interleave schema with unused time-slots
+ (nu) and used time-slots (XX) for TSi is
+ nu nu XX nu nu nu XX nu nu nu XX nu
+ <-- TSi --> <- TSi+1 -> <- TSi+2 ->
+ With lantiq,data-rate-bps = 8192000, and lantiq,channel-phase = 1, the
+ interleave schema is
+ nu XX nu nu nu XX nu nu nu XX nu nu
+ <-- TSi --> <- TSi+1 -> <- TSi+2 ->
+ With lantiq,data-rate-bps = 4096000 (ie 2*2048000), and
+ lantiq,channel-phase = 1, the interleave schema is
+ nu XX nu XX nu XX
+ <-- TSi --> <- TSi+1 -> <- TSi+2 ->
+
+patternProperties:
+ '^codec(-([0-9]|[1-2][0-9]|3[0-1]))?$':
+ type: object
+ $ref: /schemas/sound/dai-common.yaml
+ unevaluatedProperties: false
+ description:
+ Codec provided by the pef2256. This codec allows to use some of the PCM
+ system highway time-slots as audio channels to transport audio data over
+ the E1/T1/J1 lines.
+ The time-slots used by the codec must be set and so, the properties
+ 'dai-tdm-slot-num', 'dai-tdm-slot-width', 'dai-tdm-slot-tx-mask' and
+ 'dai-tdm-slot-rx-mask' must be present in the sound card node for
+ sub-nodes that involve the codec. The codec uses 8-bit time-slots.
+ 'dai-tdm-tdm-slot-with' must be set to 8.
+ The tx and rx masks define the pef2256 time-slots assigned to the codec.
+
+ properties:
+ compatible:
+ const: lantiq,pef2256-codec
+
+ '#sound-dai-cells':
+ const: 0
+
+ required:
+ - compatible
+ - '#sound-dai-cells'
+
+required:
+ - compatible
+ - reg
+ - clocks
+ - clock-names
+ - interrupts
+
+additionalProperties: false
+
+examples:
+ - |
+ #include <dt-bindings/gpio/gpio.h>
+ #include <dt-bindings/interrupt-controller/irq.h>
+
+ pef2256: framer@2000000 {
+ compatible = "lantiq,pef2256";
+ reg = <0x2000000 0x100>;
+ interrupts = <8 IRQ_TYPE_LEVEL_LOW>;
+ interrupt-parent = <&intc>;
+ clocks = <&clk_mclk>, <&clk_sclkr>, <&clk_sclkx>;
+ clock-names = "mclk", "sclkr", "sclkx";
+ reset-gpios = <&gpio 11 GPIO_ACTIVE_LOW>;
+ lantiq,data-rate-bps = <4096000>;
+
+ pinctrl {
+ pef2256_rpa_sypr: rpa-pins {
+ pins = "RPA";
+ function = "SYPR";
+ };
+ pef2256_xpa_sypx: xpa-pins {
+ pins = "XPA";
+ function = "SYPX";
+ };
+ };
+
+ pef2256_codec0: codec-0 {
+ compatible = "lantiq,pef2256-codec";
+ #sound-dai-cells = <0>;
+ sound-name-prefix = "PEF2256_0";
+ };
+
+ pef2256_codec1: codec-1 {
+ compatible = "lantiq,pef2256-codec";
+ #sound-dai-cells = <0>;
+ sound-name-prefix = "PEF2256_1";
+ };
+ };
+
+ sound {
+ compatible = "simple-audio-card";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ simple-audio-card,dai-link@0 { /* CPU DAI1 - pef2256 codec 1 */
+ reg = <0>;
+ cpu {
+ sound-dai = <&cpu_dai1>;
+ };
+ codec {
+ sound-dai = <&pef2256_codec0>;
+ dai-tdm-slot-num = <4>;
+ dai-tdm-slot-width = <8>;
+ /* TS 1, 2, 3, 4 */
+ dai-tdm-slot-tx-mask = <0 1 1 1 1>;
+ dai-tdm-slot-rx-mask = <0 1 1 1 1>;
+ };
+ };
+ simple-audio-card,dai-link@1 { /* CPU DAI2 - pef2256 codec 2 */
+ reg = <1>;
+ cpu {
+ sound-dai = <&cpu_dai2>;
+ };
+ codec {
+ sound-dai = <&pef2256_codec1>;
+ dai-tdm-slot-num = <4>;
+ dai-tdm-slot-width = <8>;
+ /* TS 5, 6, 7, 8 */
+ dai-tdm-slot-tx-mask = <0 0 0 0 0 1 1 1 1>;
+ dai-tdm-slot-rx-mask = <0 0 0 0 0 1 1 1 1>;
+ };
+ };
+ };
diff --git a/dts/upstream/Bindings/net/marvell,aquantia.yaml b/dts/upstream/Bindings/net/marvell,aquantia.yaml
new file mode 100644
index 0000000..9854fab
--- /dev/null
+++ b/dts/upstream/Bindings/net/marvell,aquantia.yaml
@@ -0,0 +1,116 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/net/marvell,aquantia.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Marvell Aquantia Ethernet PHY
+
+maintainers:
+ - Christian Marangi <ansuelsmth@gmail.com>
+
+description: |
+ Marvell Aquantia Ethernet PHY require a firmware to be loaded to actually
+ work.
+
+ This can be done and is implemented by OEM in 3 different way:
+ - Attached SPI flash directly to the PHY with the firmware. The PHY
+ will self load the firmware in the presence of this configuration.
+ - Read from a dedicated partition on system NAND declared in an
+ NVMEM cell, and loaded to the PHY using its mailbox interface.
+ - Manually provided firmware loaded from a file in the filesystem.
+
+allOf:
+ - $ref: ethernet-phy.yaml#
+
+select:
+ properties:
+ compatible:
+ contains:
+ enum:
+ - ethernet-phy-id03a1.b445
+ - ethernet-phy-id03a1.b460
+ - ethernet-phy-id03a1.b4a2
+ - ethernet-phy-id03a1.b4d0
+ - ethernet-phy-id03a1.b4e0
+ - ethernet-phy-id03a1.b5c2
+ - ethernet-phy-id03a1.b4b0
+ - ethernet-phy-id03a1.b662
+ - ethernet-phy-id03a1.b712
+ - ethernet-phy-id31c3.1c12
+ required:
+ - compatible
+
+properties:
+ reg:
+ maxItems: 1
+
+ firmware-name:
+ description: specify the name of PHY firmware to load
+
+ nvmem-cells:
+ description: phandle to the firmware nvmem cell
+ maxItems: 1
+
+ nvmem-cell-names:
+ const: firmware
+
+required:
+ - compatible
+ - reg
+
+unevaluatedProperties: false
+
+examples:
+ - |
+ mdio {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ ethernet-phy@0 {
+ compatible = "ethernet-phy-id31c3.1c12",
+ "ethernet-phy-ieee802.3-c45";
+
+ reg = <0>;
+ firmware-name = "AQR-G4_v5.4.C-AQR_CIG_WF-1945_0x8_ID44776_VER1630.cld";
+ };
+
+ ethernet-phy@1 {
+ compatible = "ethernet-phy-id31c3.1c12",
+ "ethernet-phy-ieee802.3-c45";
+
+ reg = <1>;
+ nvmem-cells = <&aqr_fw>;
+ nvmem-cell-names = "firmware";
+ };
+ };
+
+ flash {
+ compatible = "jedec,spi-nor";
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ partitions {
+ compatible = "fixed-partitions";
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ /* ... */
+
+ partition@650000 {
+ compatible = "nvmem-cells";
+ label = "0:ethphyfw";
+ reg = <0x650000 0x80000>;
+ read-only;
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ aqr_fw: aqr_fw@0 {
+ reg = <0x0 0x5f42a>;
+ };
+ };
+
+ /* ... */
+
+ };
+ };
diff --git a/dts/upstream/Bindings/net/marvell,mvusb.yaml b/dts/upstream/Bindings/net/marvell,mvusb.yaml
index 3a33251..ab838c1 100644
--- a/dts/upstream/Bindings/net/marvell,mvusb.yaml
+++ b/dts/upstream/Bindings/net/marvell,mvusb.yaml
@@ -50,11 +50,14 @@
#address-cells = <1>;
#size-cells = <0>;
- switch@0 {
+ ethernet-switch@0 {
compatible = "marvell,mv88e6190";
reg = <0x0>;
- ports {
+ ethernet-ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
/* Port definitions */
};
diff --git a/dts/upstream/Bindings/net/marvell,orion-mdio.yaml b/dts/upstream/Bindings/net/marvell,orion-mdio.yaml
index e35da8b..7342985 100644
--- a/dts/upstream/Bindings/net/marvell,orion-mdio.yaml
+++ b/dts/upstream/Bindings/net/marvell,orion-mdio.yaml
@@ -39,28 +39,6 @@
allOf:
- $ref: mdio.yaml#
- - if:
- required:
- - interrupts
-
- then:
- properties:
- reg:
- items:
- - items:
- - $ref: /schemas/types.yaml#/definitions/cell
- - const: 0x84
-
- else:
- properties:
- reg:
- items:
- - items:
- - $ref: /schemas/types.yaml#/definitions/cell
- - enum:
- - 0x4
- - 0x10
-
unevaluatedProperties: false
examples:
diff --git a/dts/upstream/Bindings/net/marvell,prestera.yaml b/dts/upstream/Bindings/net/marvell,prestera.yaml
index 5ea8b73..16ff892 100644
--- a/dts/upstream/Bindings/net/marvell,prestera.yaml
+++ b/dts/upstream/Bindings/net/marvell,prestera.yaml
@@ -78,8 +78,8 @@
pcie@0 {
#address-cells = <3>;
#size-cells = <2>;
- ranges = <0x0 0x0 0x0 0x0 0x0 0x0>;
- reg = <0x0 0x0 0x0 0x0 0x0 0x0>;
+ ranges = <0x02000000 0x0 0x100000 0x10000000 0x0 0x0>;
+ reg = <0x0 0x1000>;
device_type = "pci";
switch@0,0 {
diff --git a/dts/upstream/Bindings/net/pcs/mediatek,sgmiisys.yaml b/dts/upstream/Bindings/net/pcs/mediatek,sgmiisys.yaml
index 66a9519..1bacc0e 100644
--- a/dts/upstream/Bindings/net/pcs/mediatek,sgmiisys.yaml
+++ b/dts/upstream/Bindings/net/pcs/mediatek,sgmiisys.yaml
@@ -15,15 +15,22 @@
properties:
compatible:
- items:
- - enum:
- - mediatek,mt7622-sgmiisys
- - mediatek,mt7629-sgmiisys
- - mediatek,mt7981-sgmiisys_0
- - mediatek,mt7981-sgmiisys_1
- - mediatek,mt7986-sgmiisys_0
- - mediatek,mt7986-sgmiisys_1
- - const: syscon
+ oneOf:
+ - items:
+ - enum:
+ - mediatek,mt7622-sgmiisys
+ - mediatek,mt7629-sgmiisys
+ - mediatek,mt7981-sgmiisys_0
+ - mediatek,mt7981-sgmiisys_1
+ - mediatek,mt7986-sgmiisys_0
+ - mediatek,mt7986-sgmiisys_1
+ - const: syscon
+ - items:
+ - enum:
+ - mediatek,mt7988-sgmiisys0
+ - mediatek,mt7988-sgmiisys1
+ - const: simple-mfd
+ - const: syscon
reg:
maxItems: 1
@@ -35,11 +42,51 @@
description: Invert polarity of the SGMII data lanes
type: boolean
+ pcs:
+ type: object
+ description: MediaTek LynxI HSGMII PCS
+ properties:
+ compatible:
+ const: mediatek,mt7988-sgmii
+
+ clocks:
+ maxItems: 3
+
+ clock-names:
+ items:
+ - const: sgmii_sel
+ - const: sgmii_tx
+ - const: sgmii_rx
+
+ required:
+ - compatible
+ - clocks
+ - clock-names
+
+ additionalProperties: false
+
required:
- compatible
- reg
- '#clock-cells'
+allOf:
+ - if:
+ properties:
+ compatible:
+ contains:
+ enum:
+ - mediatek,mt7988-sgmiisys0
+ - mediatek,mt7988-sgmiisys1
+
+ then:
+ required:
+ - pcs
+
+ else:
+ properties:
+ pcs: false
+
additionalProperties: false
examples:
diff --git a/dts/upstream/Bindings/net/qcom,ipa.yaml b/dts/upstream/Bindings/net/qcom,ipa.yaml
index 2d5e4ff..c302186 100644
--- a/dts/upstream/Bindings/net/qcom,ipa.yaml
+++ b/dts/upstream/Bindings/net/qcom,ipa.yaml
@@ -43,15 +43,21 @@
properties:
compatible:
- enum:
- - qcom,msm8998-ipa
- - qcom,sc7180-ipa
- - qcom,sc7280-ipa
- - qcom,sdm845-ipa
- - qcom,sdx55-ipa
- - qcom,sdx65-ipa
- - qcom,sm6350-ipa
- - qcom,sm8350-ipa
+ oneOf:
+ - enum:
+ - qcom,msm8998-ipa
+ - qcom,sc7180-ipa
+ - qcom,sc7280-ipa
+ - qcom,sdm845-ipa
+ - qcom,sdx55-ipa
+ - qcom,sdx65-ipa
+ - qcom,sm6350-ipa
+ - qcom,sm8350-ipa
+ - qcom,sm8550-ipa
+ - items:
+ - enum:
+ - qcom,sm8650-ipa
+ - const: qcom,sm8550-ipa
reg:
items:
diff --git a/dts/upstream/Bindings/net/renesas,etheravb.yaml b/dts/upstream/Bindings/net/renesas,etheravb.yaml
index 5d074f2..890f785 100644
--- a/dts/upstream/Bindings/net/renesas,etheravb.yaml
+++ b/dts/upstream/Bindings/net/renesas,etheravb.yaml
@@ -55,9 +55,10 @@
- items:
- enum:
- - renesas,r9a07g043-gbeth # RZ/G2UL
+ - renesas,r9a07g043-gbeth # RZ/G2UL and RZ/Five
- renesas,r9a07g044-gbeth # RZ/G2{L,LC}
- renesas,r9a07g054-gbeth # RZ/V2L
+ - renesas,r9a08g045-gbeth # RZ/G3S
- const: renesas,rzg2l-gbeth # RZ/{G2L,G2UL,V2L} family
reg: true
diff --git a/dts/upstream/Bindings/net/renesas,ethertsn.yaml b/dts/upstream/Bindings/net/renesas,ethertsn.yaml
new file mode 100644
index 0000000..ea35d19
--- /dev/null
+++ b/dts/upstream/Bindings/net/renesas,ethertsn.yaml
@@ -0,0 +1,135 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/net/renesas,ethertsn.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Renesas Ethernet TSN End-station
+
+maintainers:
+ - Niklas Söderlund <niklas.soderlund@ragnatech.se>
+
+description:
+ The RTSN device provides Ethernet network using a 10 Mbps, 100 Mbps, or 1
+ Gbps full-duplex link via MII/GMII/RMII/RGMII. Depending on the connected PHY.
+
+allOf:
+ - $ref: ethernet-controller.yaml#
+
+properties:
+ compatible:
+ items:
+ - enum:
+ - renesas,r8a779g0-ethertsn # R-Car V4H
+ - const: renesas,rcar-gen4-ethertsn
+
+ reg:
+ items:
+ - description: TSN End Station target
+ - description: generalized Precision Time Protocol target
+
+ reg-names:
+ items:
+ - const: tsnes
+ - const: gptp
+
+ interrupts:
+ items:
+ - description: TX data interrupt
+ - description: RX data interrupt
+
+ interrupt-names:
+ items:
+ - const: tx
+ - const: rx
+
+ clocks:
+ maxItems: 1
+
+ power-domains:
+ maxItems: 1
+
+ resets:
+ maxItems: 1
+
+ phy-mode:
+ contains:
+ enum:
+ - mii
+ - rgmii
+
+ phy-handle:
+ $ref: /schemas/types.yaml#/definitions/phandle
+ description:
+ Specifies a reference to a node representing a PHY device.
+
+ rx-internal-delay-ps:
+ enum: [0, 1800]
+ default: 0
+
+ tx-internal-delay-ps:
+ enum: [0, 2000]
+ default: 0
+
+ '#address-cells':
+ const: 1
+
+ '#size-cells':
+ const: 0
+
+patternProperties:
+ "^ethernet-phy@[0-9a-f]$":
+ type: object
+ $ref: ethernet-phy.yaml#
+ unevaluatedProperties: false
+
+required:
+ - compatible
+ - reg
+ - reg-names
+ - interrupts
+ - interrupt-names
+ - clocks
+ - power-domains
+ - resets
+ - phy-mode
+ - phy-handle
+ - '#address-cells'
+ - '#size-cells'
+
+additionalProperties: false
+
+examples:
+ - |
+ #include <dt-bindings/clock/r8a779g0-cpg-mssr.h>
+ #include <dt-bindings/interrupt-controller/arm-gic.h>
+ #include <dt-bindings/power/r8a779g0-sysc.h>
+ #include <dt-bindings/gpio/gpio.h>
+
+ tsn0: ethernet@e6460000 {
+ compatible = "renesas,r8a779g0-ethertsn", "renesas,rcar-gen4-ethertsn";
+ reg = <0xe6460000 0x7000>,
+ <0xe6449000 0x500>;
+ reg-names = "tsnes", "gptp";
+ interrupts = <GIC_SPI 429 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 430 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "tx", "rx";
+ clocks = <&cpg CPG_MOD 2723>;
+ power-domains = <&sysc R8A779G0_PD_ALWAYS_ON>;
+ resets = <&cpg 2723>;
+
+ phy-mode = "rgmii";
+ tx-internal-delay-ps = <2000>;
+ phy-handle = <&phy3>;
+
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ phy3: ethernet-phy@3 {
+ compatible = "ethernet-phy-ieee802.3-c45";
+ reg = <0>;
+ interrupt-parent = <&gpio4>;
+ interrupts = <3 IRQ_TYPE_LEVEL_LOW>;
+ reset-gpios = <&gpio1 23 GPIO_ACTIVE_LOW>;
+ };
+ };
diff --git a/dts/upstream/Bindings/net/sff,sfp.yaml b/dts/upstream/Bindings/net/sff,sfp.yaml
index 973e478..bf6cbc7 100644
--- a/dts/upstream/Bindings/net/sff,sfp.yaml
+++ b/dts/upstream/Bindings/net/sff,sfp.yaml
@@ -120,7 +120,7 @@
pinctrl-names = "default";
pinctrl-0 = <&cps_sfpp0_pins>;
tx-disable-gpios = <&cps_gpio1 29 GPIO_ACTIVE_HIGH>;
- tx-fault-gpios = <&cps_gpio1 26 GPIO_ACTIVE_HIGH>;
+ tx-fault-gpios = <&cps_gpio1 26 GPIO_ACTIVE_HIGH>;
};
mdio {
diff --git a/dts/upstream/Bindings/net/xlnx,axi-ethernet.yaml b/dts/upstream/Bindings/net/xlnx,axi-ethernet.yaml
index 1d33d80..bbe89ea 100644
--- a/dts/upstream/Bindings/net/xlnx,axi-ethernet.yaml
+++ b/dts/upstream/Bindings/net/xlnx,axi-ethernet.yaml
@@ -122,6 +122,20 @@
and "phy-handle" should point to an external PHY if exists.
maxItems: 1
+ dmas:
+ minItems: 2
+ maxItems: 32
+ description: TX and RX DMA channel phandle
+
+ dma-names:
+ items:
+ pattern: "^[tr]x_chan([0-9]|1[0-5])$"
+ description:
+ Should be "tx_chan0", "tx_chan1" ... "tx_chan15" for DMA Tx channel
+ Should be "rx_chan0", "rx_chan1" ... "rx_chan15" for DMA Rx channel
+ minItems: 2
+ maxItems: 32
+
required:
- compatible
- interrupts
@@ -143,6 +157,8 @@
clocks = <&axi_clk>, <&axi_clk>, <&pl_enet_ref_clk>, <&mgt_clk>;
phy-mode = "mii";
reg = <0x40c00000 0x40000>,<0x50c00000 0x40000>;
+ dmas = <&xilinx_dma 0>, <&xilinx_dma 1>;
+ dma-names = "tx_chan0", "rx_chan0";
xlnx,rxcsum = <0x2>;
xlnx,rxmem = <0x800>;
xlnx,txcsum = <0x2>;
diff --git a/dts/upstream/Bindings/nvmem/st,stm32-romem.yaml b/dts/upstream/Bindings/nvmem/st,stm32-romem.yaml
index a69de3e..92bfe25 100644
--- a/dts/upstream/Bindings/nvmem/st,stm32-romem.yaml
+++ b/dts/upstream/Bindings/nvmem/st,stm32-romem.yaml
@@ -24,6 +24,7 @@
- st,stm32f4-otp
- st,stm32mp13-bsec
- st,stm32mp15-bsec
+ - st,stm32mp25-bsec
reg:
maxItems: 1
diff --git a/dts/upstream/Bindings/pci/brcm,stb-pcie.yaml b/dts/upstream/Bindings/pci/brcm,stb-pcie.yaml
index 7e15aae..22491f7 100644
--- a/dts/upstream/Bindings/pci/brcm,stb-pcie.yaml
+++ b/dts/upstream/Bindings/pci/brcm,stb-pcie.yaml
@@ -64,6 +64,24 @@
aspm-no-l0s: true
+ brcm,clkreq-mode:
+ description: A string that determines the operating
+ clkreq mode of the PCIe RC HW with respect to controlling the refclk
+ signal. There are three different modes -- "safe", which drives the
+ refclk signal unconditionally and will work for all devices but does
+ not provide any power savings; "no-l1ss" -- which provides Clock
+ Power Management, L0s, and L1, but cannot provide L1 substate (L1SS)
+ power savings. If the downstream device connected to the RC is L1SS
+ capable AND the OS enables L1SS, all PCIe traffic may abruptly halt,
+ potentially hanging the system; "default" -- which provides L0s, L1,
+ and L1SS, but not compliant to provide Clock Power Management;
+ specifically, may not be able to meet the T_CLRon max timing of 400ns
+ as specified in "Dynamic Clock Control", section 3.2.5.2.2 PCI
+ Express Mini CEM 2.1 specification. This situation is atypical and
+ should happen only with older devices.
+ $ref: /schemas/types.yaml#/definitions/string
+ enum: [ safe, no-l1ss, default ]
+
brcm,scb-sizes:
description: u64 giving the 64bit PCIe memory
viewport size of a memory controller. There may be up to
diff --git a/dts/upstream/Bindings/pci/qcom,pcie.yaml b/dts/upstream/Bindings/pci/qcom,pcie.yaml
index eadba38..a93ab3b 100644
--- a/dts/upstream/Bindings/pci/qcom,pcie.yaml
+++ b/dts/upstream/Bindings/pci/qcom,pcie.yaml
@@ -42,6 +42,10 @@
- qcom,pcie-sm8450-pcie1
- qcom,pcie-sm8550
- items:
+ - enum:
+ - qcom,pcie-sm8650
+ - const: qcom,pcie-sm8550
+ - items:
- const: qcom,pcie-msm8998
- const: qcom,pcie-msm8996
@@ -62,7 +66,8 @@
maxItems: 8
iommu-map:
- maxItems: 2
+ minItems: 1
+ maxItems: 16
# Common definitions for clocks, clock-names and reset.
# Platform constraints are described later.
@@ -88,7 +93,7 @@
minItems: 1
maxItems: 12
- resets-names:
+ reset-names:
minItems: 1
maxItems: 12
@@ -483,6 +488,33 @@
compatible:
contains:
enum:
+ - qcom,pcie-sc8180x
+ then:
+ properties:
+ clocks:
+ minItems: 8
+ maxItems: 8
+ clock-names:
+ items:
+ - const: pipe # PIPE clock
+ - const: aux # Auxiliary clock
+ - const: cfg # Configuration clock
+ - const: bus_master # Master AXI clock
+ - const: bus_slave # Slave AXI clock
+ - const: slave_q2a # Slave Q2A clock
+ - const: ref # REFERENCE clock
+ - const: tbu # PCIe TBU clock
+ resets:
+ maxItems: 1
+ reset-names:
+ items:
+ - const: pci # PCIe core reset
+
+ - if:
+ properties:
+ compatible:
+ contains:
+ enum:
- qcom,pcie-sdm845
then:
oneOf:
@@ -526,8 +558,33 @@
compatible:
contains:
enum:
- - qcom,pcie-sc8180x
- qcom,pcie-sm8150
+ then:
+ properties:
+ clocks:
+ minItems: 8
+ maxItems: 8
+ clock-names:
+ items:
+ - const: pipe # PIPE clock
+ - const: aux # Auxiliary clock
+ - const: cfg # Configuration clock
+ - const: bus_master # Master AXI clock
+ - const: bus_slave # Slave AXI clock
+ - const: slave_q2a # Slave Q2A clock
+ - const: tbu # PCIe TBU clock
+ - const: ref # REFERENCE clock
+ resets:
+ maxItems: 1
+ reset-names:
+ items:
+ - const: pci # PCIe core reset
+
+ - if:
+ properties:
+ compatible:
+ contains:
+ enum:
- qcom,pcie-sm8250
then:
oneOf:
diff --git a/dts/upstream/Bindings/pci/rcar-pci-host.yaml b/dts/upstream/Bindings/pci/rcar-pci-host.yaml
index 8fdfbc7..b6a7cb3 100644
--- a/dts/upstream/Bindings/pci/rcar-pci-host.yaml
+++ b/dts/upstream/Bindings/pci/rcar-pci-host.yaml
@@ -68,6 +68,15 @@
phy-names:
const: pcie
+ vpcie1v5-supply:
+ description: The 1.5v regulator to use for PCIe.
+
+ vpcie3v3-supply:
+ description: The 3.3v regulator to use for PCIe.
+
+ vpcie12v-supply:
+ description: The 12v regulator to use for PCIe.
+
required:
- compatible
- reg
@@ -121,5 +130,7 @@
clock-names = "pcie", "pcie_bus";
power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
resets = <&cpg 319>;
+ vpcie3v3-supply = <&pcie_3v3>;
+ vpcie12v-supply = <&pcie_12v>;
};
};
diff --git a/dts/upstream/Bindings/pci/rockchip-dw-pcie.yaml b/dts/upstream/Bindings/pci/rockchip-dw-pcie.yaml
index 1ae8dcf..5f71921 100644
--- a/dts/upstream/Bindings/pci/rockchip-dw-pcie.yaml
+++ b/dts/upstream/Bindings/pci/rockchip-dw-pcie.yaml
@@ -49,6 +49,7 @@
- description: APB clock for PCIe
- description: Auxiliary clock for PCIe
- description: PIPE clock
+ - description: Reference clock for PCIe
clock-names:
minItems: 5
@@ -59,6 +60,7 @@
- const: pclk
- const: aux
- const: pipe
+ - const: ref
interrupts:
items:
diff --git a/dts/upstream/Bindings/pci/ti,j721e-pci-ep.yaml b/dts/upstream/Bindings/pci/ti,j721e-pci-ep.yaml
index 6229218..97f2579 100644
--- a/dts/upstream/Bindings/pci/ti,j721e-pci-ep.yaml
+++ b/dts/upstream/Bindings/pci/ti,j721e-pci-ep.yaml
@@ -10,13 +10,11 @@
maintainers:
- Kishon Vijay Abraham I <kishon@ti.com>
-allOf:
- - $ref: cdns-pcie-ep.yaml#
-
properties:
compatible:
oneOf:
- const: ti,j721e-pcie-ep
+ - const: ti,j784s4-pcie-ep
- description: PCIe EP controller in AM64
items:
- const: ti,am64-pcie-ep
@@ -65,6 +63,41 @@
items:
- const: link_state
+allOf:
+ - $ref: cdns-pcie-ep.yaml#
+ - if:
+ properties:
+ compatible:
+ enum:
+ - ti,am64-pcie-ep
+ then:
+ properties:
+ num-lanes:
+ const: 1
+
+ - if:
+ properties:
+ compatible:
+ enum:
+ - ti,j7200-pcie-ep
+ - ti,j721e-pcie-ep
+ then:
+ properties:
+ num-lanes:
+ minimum: 1
+ maximum: 2
+
+ - if:
+ properties:
+ compatible:
+ enum:
+ - ti,j784s4-pcie-ep
+ then:
+ properties:
+ num-lanes:
+ minimum: 1
+ maximum: 4
+
required:
- compatible
- reg
diff --git a/dts/upstream/Bindings/pci/ti,j721e-pci-host.yaml b/dts/upstream/Bindings/pci/ti,j721e-pci-host.yaml
index a2c5eae..b7a534c 100644
--- a/dts/upstream/Bindings/pci/ti,j721e-pci-host.yaml
+++ b/dts/upstream/Bindings/pci/ti,j721e-pci-host.yaml
@@ -10,13 +10,11 @@
maintainers:
- Kishon Vijay Abraham I <kishon@ti.com>
-allOf:
- - $ref: cdns-pcie-host.yaml#
-
properties:
compatible:
oneOf:
- const: ti,j721e-pcie-host
+ - const: ti,j784s4-pcie-host
- description: PCIe controller in AM64
items:
- const: ti,am64-pcie-host
@@ -94,6 +92,41 @@
interrupts:
maxItems: 1
+allOf:
+ - $ref: cdns-pcie-host.yaml#
+ - if:
+ properties:
+ compatible:
+ enum:
+ - ti,am64-pcie-host
+ then:
+ properties:
+ num-lanes:
+ const: 1
+
+ - if:
+ properties:
+ compatible:
+ enum:
+ - ti,j7200-pcie-host
+ - ti,j721e-pcie-host
+ then:
+ properties:
+ num-lanes:
+ minimum: 1
+ maximum: 2
+
+ - if:
+ properties:
+ compatible:
+ enum:
+ - ti,j784s4-pcie-host
+ then:
+ properties:
+ num-lanes:
+ minimum: 1
+ maximum: 4
+
required:
- compatible
- reg
diff --git a/dts/upstream/Bindings/pci/toshiba,visconti-pcie.yaml b/dts/upstream/Bindings/pci/toshiba,visconti-pcie.yaml
index 53da2ed..120e3bb 100644
--- a/dts/upstream/Bindings/pci/toshiba,visconti-pcie.yaml
+++ b/dts/upstream/Bindings/pci/toshiba,visconti-pcie.yaml
@@ -83,7 +83,7 @@
<0x0 0x28050000 0x0 0x00010000>,
<0x0 0x24200000 0x0 0x00002000>,
<0x0 0x24162000 0x0 0x00001000>;
- reg-names = "dbi", "config", "ulreg", "smu", "mpu";
+ reg-names = "dbi", "config", "ulreg", "smu", "mpu";
device_type = "pci";
bus-range = <0x00 0xff>;
num-lanes = <2>;
diff --git a/dts/upstream/Bindings/perf/fsl-imx-ddr.yaml b/dts/upstream/Bindings/perf/fsl-imx-ddr.yaml
index e9fad4b..6c96a42 100644
--- a/dts/upstream/Bindings/perf/fsl-imx-ddr.yaml
+++ b/dts/upstream/Bindings/perf/fsl-imx-ddr.yaml
@@ -27,6 +27,9 @@
- fsl,imx8mq-ddr-pmu
- fsl,imx8mp-ddr-pmu
- const: fsl,imx8m-ddr-pmu
+ - items:
+ - const: fsl,imx8dxl-ddr-pmu
+ - const: fsl,imx8-ddr-pmu
reg:
maxItems: 1
diff --git a/dts/upstream/Bindings/phy/amlogic,g12a-mipi-dphy-analog.yaml b/dts/upstream/Bindings/phy/amlogic,g12a-mipi-dphy-analog.yaml
index c8c83ac..81c2654 100644
--- a/dts/upstream/Bindings/phy/amlogic,g12a-mipi-dphy-analog.yaml
+++ b/dts/upstream/Bindings/phy/amlogic,g12a-mipi-dphy-analog.yaml
@@ -16,20 +16,8 @@
"#phy-cells":
const: 0
- reg:
- maxItems: 1
-
required:
- compatible
- - reg
- "#phy-cells"
additionalProperties: false
-
-examples:
- - |
- phy@0 {
- compatible = "amlogic,g12a-mipi-dphy-analog";
- reg = <0x0 0xc>;
- #phy-cells = <0>;
- };
diff --git a/dts/upstream/Bindings/phy/amlogic,meson-axg-mipi-pcie-analog.yaml b/dts/upstream/Bindings/phy/amlogic,meson-axg-mipi-pcie-analog.yaml
index 009a398..70def36 100644
--- a/dts/upstream/Bindings/phy/amlogic,meson-axg-mipi-pcie-analog.yaml
+++ b/dts/upstream/Bindings/phy/amlogic,meson-axg-mipi-pcie-analog.yaml
@@ -9,16 +9,6 @@
maintainers:
- Remi Pommarel <repk@triplefau.lt>
-description: |+
- The Everything-Else Power Domains node should be the child of a syscon
- node with the required property:
-
- - compatible: Should be the following:
- "amlogic,meson-gx-hhi-sysctrl", "simple-mfd", "syscon"
-
- Refer to the bindings described in
- Documentation/devicetree/bindings/mfd/syscon.yaml
-
properties:
compatible:
const: amlogic,axg-mipi-pcie-analog-phy
@@ -31,10 +21,3 @@
- "#phy-cells"
additionalProperties: false
-
-examples:
- - |
- mpphy: phy {
- compatible = "amlogic,axg-mipi-pcie-analog-phy";
- #phy-cells = <0>;
- };
diff --git a/dts/upstream/Bindings/phy/mediatek,dsi-phy.yaml b/dts/upstream/Bindings/phy/mediatek,dsi-phy.yaml
index 6703689..f6e494d 100644
--- a/dts/upstream/Bindings/phy/mediatek,dsi-phy.yaml
+++ b/dts/upstream/Bindings/phy/mediatek,dsi-phy.yaml
@@ -31,6 +31,7 @@
- items:
- enum:
- mediatek,mt8188-mipi-tx
+ - mediatek,mt8195-mipi-tx
- mediatek,mt8365-mipi-tx
- const: mediatek,mt8183-mipi-tx
- const: mediatek,mt2701-mipi-tx
diff --git a/dts/upstream/Bindings/phy/mediatek,tphy.yaml b/dts/upstream/Bindings/phy/mediatek,tphy.yaml
index 2bb9154..acba072 100644
--- a/dts/upstream/Bindings/phy/mediatek,tphy.yaml
+++ b/dts/upstream/Bindings/phy/mediatek,tphy.yaml
@@ -235,6 +235,15 @@
Specify the flag to enable BC1.2 if support it
type: boolean
+ mediatek,force-mode:
+ description:
+ The force mode is used to manually switch the shared phy mode between
+ USB3 and PCIe, when USB3 phy type is selected by the consumer, and
+ force-mode is set, will cause phy's power and pipe toggled and force
+ phy as USB3 mode which switched from default PCIe mode. But perfer to
+ use the property "mediatek,syscon-type" for newer SoCs that support it.
+ type: boolean
+
mediatek,syscon-type:
$ref: /schemas/types.yaml#/definitions/phandle-array
maxItems: 1
diff --git a/dts/upstream/Bindings/phy/qcom,sc8280xp-qmp-pcie-phy.yaml b/dts/upstream/Bindings/phy/qcom,sc8280xp-qmp-pcie-phy.yaml
index 2c3d655..6c03f2d 100644
--- a/dts/upstream/Bindings/phy/qcom,sc8280xp-qmp-pcie-phy.yaml
+++ b/dts/upstream/Bindings/phy/qcom,sc8280xp-qmp-pcie-phy.yaml
@@ -36,6 +36,8 @@
- qcom,sm8450-qmp-gen4x2-pcie-phy
- qcom,sm8550-qmp-gen3x2-pcie-phy
- qcom,sm8550-qmp-gen4x2-pcie-phy
+ - qcom,sm8650-qmp-gen3x2-pcie-phy
+ - qcom,sm8650-qmp-gen4x2-pcie-phy
reg:
minItems: 1
@@ -147,6 +149,8 @@
- qcom,sm8450-qmp-gen3x2-pcie-phy
- qcom,sm8550-qmp-gen3x2-pcie-phy
- qcom,sm8550-qmp-gen4x2-pcie-phy
+ - qcom,sm8650-qmp-gen3x2-pcie-phy
+ - qcom,sm8650-qmp-gen4x2-pcie-phy
then:
properties:
clocks:
@@ -189,6 +193,7 @@
contains:
enum:
- qcom,sm8550-qmp-gen4x2-pcie-phy
+ - qcom,sm8650-qmp-gen4x2-pcie-phy
then:
properties:
resets:
diff --git a/dts/upstream/Bindings/phy/qcom,sc8280xp-qmp-ufs-phy.yaml b/dts/upstream/Bindings/phy/qcom,sc8280xp-qmp-ufs-phy.yaml
index f3a3296..8474eef 100644
--- a/dts/upstream/Bindings/phy/qcom,sc8280xp-qmp-ufs-phy.yaml
+++ b/dts/upstream/Bindings/phy/qcom,sc8280xp-qmp-ufs-phy.yaml
@@ -32,6 +32,7 @@
- qcom,sm8350-qmp-ufs-phy
- qcom,sm8450-qmp-ufs-phy
- qcom,sm8550-qmp-ufs-phy
+ - qcom,sm8650-qmp-ufs-phy
reg:
maxItems: 1
@@ -112,6 +113,7 @@
- qcom,sm8250-qmp-ufs-phy
- qcom,sm8350-qmp-ufs-phy
- qcom,sm8550-qmp-ufs-phy
+ - qcom,sm8650-qmp-ufs-phy
then:
properties:
clocks:
diff --git a/dts/upstream/Bindings/phy/qcom,sc8280xp-qmp-usb3-uni-phy.yaml b/dts/upstream/Bindings/phy/qcom,sc8280xp-qmp-usb3-uni-phy.yaml
index 57702f7..15d82c6 100644
--- a/dts/upstream/Bindings/phy/qcom,sc8280xp-qmp-usb3-uni-phy.yaml
+++ b/dts/upstream/Bindings/phy/qcom,sc8280xp-qmp-usb3-uni-phy.yaml
@@ -32,6 +32,7 @@
- qcom,sm8150-qmp-usb3-uni-phy
- qcom,sm8250-qmp-usb3-uni-phy
- qcom,sm8350-qmp-usb3-uni-phy
+ - qcom,x1e80100-qmp-usb3-uni-phy
reg:
@@ -135,6 +136,7 @@
- qcom,sm8150-qmp-usb3-uni-phy
- qcom,sm8250-qmp-usb3-uni-phy
- qcom,sm8350-qmp-usb3-uni-phy
+ - qcom,x1e80100-qmp-usb3-uni-phy
then:
properties:
clocks:
@@ -171,6 +173,7 @@
enum:
- qcom,sa8775p-qmp-usb3-uni-phy
- qcom,sc8280xp-qmp-usb3-uni-phy
+ - qcom,x1e80100-qmp-usb3-uni-phy
then:
required:
- power-domains
diff --git a/dts/upstream/Bindings/phy/qcom,sc8280xp-qmp-usb43dp-phy.yaml b/dts/upstream/Bindings/phy/qcom,sc8280xp-qmp-usb43dp-phy.yaml
index 9af203d..2d0d7e9 100644
--- a/dts/upstream/Bindings/phy/qcom,sc8280xp-qmp-usb43dp-phy.yaml
+++ b/dts/upstream/Bindings/phy/qcom,sc8280xp-qmp-usb43dp-phy.yaml
@@ -27,6 +27,8 @@
- qcom,sm8350-qmp-usb3-dp-phy
- qcom,sm8450-qmp-usb3-dp-phy
- qcom,sm8550-qmp-usb3-dp-phy
+ - qcom,sm8650-qmp-usb3-dp-phy
+ - qcom,x1e80100-qmp-usb3-dp-phy
reg:
maxItems: 1
@@ -62,12 +64,12 @@
"#clock-cells":
const: 1
description:
- See include/dt-bindings/dt-bindings/phy/phy-qcom-qmp.h
+ See include/dt-bindings/phy/phy-qcom-qmp.h
"#phy-cells":
const: 1
description:
- See include/dt-bindings/dt-bindings/phy/phy-qcom-qmp.h
+ See include/dt-bindings/phy/phy-qcom-qmp.h
orientation-switch:
description:
@@ -128,6 +130,8 @@
- qcom,sc8280xp-qmp-usb43dp-phy
- qcom,sm6350-qmp-usb3-dp-phy
- qcom,sm8550-qmp-usb3-dp-phy
+ - qcom,sm8650-qmp-usb3-dp-phy
+ - qcom,x1e80100-qmp-usb3-dp-phy
then:
required:
- power-domains
diff --git a/dts/upstream/Bindings/phy/qcom,snps-eusb2-phy.yaml b/dts/upstream/Bindings/phy/qcom,snps-eusb2-phy.yaml
index c958286..b82f7f5 100644
--- a/dts/upstream/Bindings/phy/qcom,snps-eusb2-phy.yaml
+++ b/dts/upstream/Bindings/phy/qcom,snps-eusb2-phy.yaml
@@ -18,6 +18,8 @@
- items:
- enum:
- qcom,sdx75-snps-eusb2-phy
+ - qcom,sm8650-snps-eusb2-phy
+ - qcom,x1e80100-snps-eusb2-phy
- const: qcom,sm8550-snps-eusb2-phy
- const: qcom,sm8550-snps-eusb2-phy
diff --git a/dts/upstream/Bindings/pinctrl/pinctrl-single.yaml b/dts/upstream/Bindings/pinctrl/pinctrl-single.yaml
index 45a307d..c114955 100644
--- a/dts/upstream/Bindings/pinctrl/pinctrl-single.yaml
+++ b/dts/upstream/Bindings/pinctrl/pinctrl-single.yaml
@@ -31,6 +31,7 @@
- ti,omap3-padconf
- ti,omap4-padconf
- ti,omap5-padconf
+ - ti,j7200-padconf
- const: pinctrl-single
reg:
diff --git a/dts/upstream/Bindings/pinctrl/qcom,ipq5018-tlmm.yaml b/dts/upstream/Bindings/pinctrl/qcom,ipq5018-tlmm.yaml
index fad0118..2330060 100644
--- a/dts/upstream/Bindings/pinctrl/qcom,ipq5018-tlmm.yaml
+++ b/dts/upstream/Bindings/pinctrl/qcom,ipq5018-tlmm.yaml
@@ -23,13 +23,6 @@
interrupts:
maxItems: 1
- interrupt-controller: true
- "#interrupt-cells": true
- gpio-controller: true
- "#gpio-cells": true
- gpio-ranges: true
- wakeup-parent: true
-
gpio-reserved-ranges:
minItems: 1
maxItems: 24
@@ -95,7 +88,10 @@
- compatible
- reg
-additionalProperties: false
+allOf:
+ - $ref: /schemas/pinctrl/qcom,tlmm-common.yaml#
+
+unevaluatedProperties: false
examples:
- |
diff --git a/dts/upstream/Bindings/pinctrl/qcom,ipq5332-tlmm.yaml b/dts/upstream/Bindings/pinctrl/qcom,ipq5332-tlmm.yaml
index 3d3086a..e571cd6 100644
--- a/dts/upstream/Bindings/pinctrl/qcom,ipq5332-tlmm.yaml
+++ b/dts/upstream/Bindings/pinctrl/qcom,ipq5332-tlmm.yaml
@@ -26,13 +26,6 @@
interrupts:
maxItems: 1
- interrupt-controller: true
- "#interrupt-cells": true
- gpio-controller: true
- "#gpio-cells": true
- gpio-ranges: true
- wakeup-parent: true
-
gpio-reserved-ranges:
minItems: 1
maxItems: 27
@@ -100,7 +93,7 @@
- compatible
- reg
-additionalProperties: false
+unevaluatedProperties: false
examples:
- |
diff --git a/dts/upstream/Bindings/pinctrl/qcom,ipq6018-pinctrl.yaml b/dts/upstream/Bindings/pinctrl/qcom,ipq6018-pinctrl.yaml
index 7c3e5e0..ed00fba 100644
--- a/dts/upstream/Bindings/pinctrl/qcom,ipq6018-pinctrl.yaml
+++ b/dts/upstream/Bindings/pinctrl/qcom,ipq6018-pinctrl.yaml
@@ -22,12 +22,6 @@
interrupts:
maxItems: 1
- interrupt-controller: true
- "#interrupt-cells": true
- gpio-controller: true
- "#gpio-cells": true
- gpio-ranges: true
-
patternProperties:
"-state$":
oneOf:
@@ -100,7 +94,7 @@
- compatible
- reg
-additionalProperties: false
+unevaluatedProperties: false
examples:
- |
diff --git a/dts/upstream/Bindings/pinctrl/qcom,ipq8074-pinctrl.yaml b/dts/upstream/Bindings/pinctrl/qcom,ipq8074-pinctrl.yaml
index e053fbd..6f90dbb 100644
--- a/dts/upstream/Bindings/pinctrl/qcom,ipq8074-pinctrl.yaml
+++ b/dts/upstream/Bindings/pinctrl/qcom,ipq8074-pinctrl.yaml
@@ -23,13 +23,6 @@
interrupts:
maxItems: 1
- interrupt-controller: true
- "#interrupt-cells": true
- gpio-controller: true
- "#gpio-cells": true
- gpio-ranges: true
- wakeup-parent: true
-
gpio-reserved-ranges:
minItems: 1
maxItems: 35
@@ -103,7 +96,7 @@
- compatible
- reg
-additionalProperties: false
+unevaluatedProperties: false
examples:
- |
diff --git a/dts/upstream/Bindings/pinctrl/qcom,ipq9574-tlmm.yaml b/dts/upstream/Bindings/pinctrl/qcom,ipq9574-tlmm.yaml
index e5e9962..bca903b 100644
--- a/dts/upstream/Bindings/pinctrl/qcom,ipq9574-tlmm.yaml
+++ b/dts/upstream/Bindings/pinctrl/qcom,ipq9574-tlmm.yaml
@@ -23,13 +23,6 @@
interrupts:
maxItems: 1
- interrupt-controller: true
- "#interrupt-cells": true
- gpio-controller: true
- "#gpio-cells": true
- gpio-ranges: true
- wakeup-parent: true
-
gpio-reserved-ranges:
minItems: 1
maxItems: 33
@@ -97,7 +90,7 @@
- compatible
- reg
-additionalProperties: false
+unevaluatedProperties: false
examples:
- |
diff --git a/dts/upstream/Bindings/pinctrl/qcom,lpass-lpi-common.yaml b/dts/upstream/Bindings/pinctrl/qcom,lpass-lpi-common.yaml
new file mode 100644
index 0000000..3b50457
--- /dev/null
+++ b/dts/upstream/Bindings/pinctrl/qcom,lpass-lpi-common.yaml
@@ -0,0 +1,75 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/pinctrl/qcom,lpass-lpi-common.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Qualcomm SoC LPASS LPI TLMM Common Properties
+
+maintainers:
+ - Bjorn Andersson <andersson@kernel.org>
+ - Srinivas Kandagatla <srinivas.kandagatla@linaro.org>
+ - Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
+
+description:
+ Common properties for the Top Level Mode Multiplexer pin controllers in the
+ Low Power Audio SubSystem (LPASS) Low Power Island (LPI) of Qualcomm SoCs.
+
+properties:
+ gpio-controller: true
+
+ "#gpio-cells":
+ description:
+ Specifying the pin number and flags, as defined in
+ include/dt-bindings/gpio/gpio.h
+ const: 2
+
+ gpio-ranges:
+ maxItems: 1
+
+required:
+ - gpio-controller
+ - "#gpio-cells"
+ - gpio-ranges
+
+allOf:
+ - $ref: pinctrl.yaml#
+
+additionalProperties: true
+
+$defs:
+ qcom-tlmm-state:
+ properties:
+ drive-strength:
+ enum: [2, 4, 6, 8, 10, 12, 14, 16]
+ default: 2
+ description:
+ Selects the drive strength for the specified pins, in mA.
+
+ slew-rate:
+ enum: [0, 1, 2, 3]
+ default: 0
+ description: |
+ 0: No adjustments
+ 1: Higher Slew rate (faster edges)
+ 2: Lower Slew rate (slower edges)
+ 3: Reserved (No adjustments)
+
+ bias-bus-hold: true
+ bias-pull-down: true
+ bias-pull-up: true
+ bias-disable: true
+ input-enable: true
+ output-high: true
+ output-low: true
+
+ required:
+ - pins
+ - function
+
+ allOf:
+ - $ref: pincfg-node.yaml#
+ - $ref: pinmux-node.yaml#
+
+ additionalProperties: true
+
diff --git a/dts/upstream/Bindings/pinctrl/qcom,mdm9607-tlmm.yaml b/dts/upstream/Bindings/pinctrl/qcom,mdm9607-tlmm.yaml
index 5ece3b9..bd3cbb4 100644
--- a/dts/upstream/Bindings/pinctrl/qcom,mdm9607-tlmm.yaml
+++ b/dts/upstream/Bindings/pinctrl/qcom,mdm9607-tlmm.yaml
@@ -25,19 +25,7 @@
interrupts:
maxItems: 1
- interrupt-controller: true
- "#interrupt-cells": true
- gpio-controller: true
gpio-reserved-ranges: true
- "#gpio-cells": true
- gpio-ranges: true
- wakeup-parent: true
-
-required:
- - compatible
- - reg
-
-additionalProperties: false
patternProperties:
"-state$":
@@ -110,6 +98,12 @@
required:
- pins
+required:
+ - compatible
+ - reg
+
+unevaluatedProperties: false
+
examples:
- |
#include <dt-bindings/interrupt-controller/arm-gic.h>
diff --git a/dts/upstream/Bindings/pinctrl/qcom,mdm9615-pinctrl.yaml b/dts/upstream/Bindings/pinctrl/qcom,mdm9615-pinctrl.yaml
index 5885aee..299e0b4 100644
--- a/dts/upstream/Bindings/pinctrl/qcom,mdm9615-pinctrl.yaml
+++ b/dts/upstream/Bindings/pinctrl/qcom,mdm9615-pinctrl.yaml
@@ -23,18 +23,6 @@
interrupts:
maxItems: 1
- interrupt-controller: true
- '#interrupt-cells': true
- gpio-controller: true
- '#gpio-cells': true
- gpio-ranges: true
-
-required:
- - compatible
- - reg
-
-additionalProperties: false
-
patternProperties:
"-state$":
oneOf:
@@ -74,6 +62,12 @@
required:
- pins
+required:
+ - compatible
+ - reg
+
+unevaluatedProperties: false
+
examples:
- |
#include <dt-bindings/interrupt-controller/arm-gic.h>
diff --git a/dts/upstream/Bindings/pinctrl/qcom,msm8226-pinctrl.yaml b/dts/upstream/Bindings/pinctrl/qcom,msm8226-pinctrl.yaml
index a602bf0..68d3fa2 100644
--- a/dts/upstream/Bindings/pinctrl/qcom,msm8226-pinctrl.yaml
+++ b/dts/upstream/Bindings/pinctrl/qcom,msm8226-pinctrl.yaml
@@ -23,12 +23,6 @@
interrupts:
maxItems: 1
- interrupt-controller: true
- "#interrupt-cells": true
- gpio-controller: true
- "#gpio-cells": true
- gpio-ranges: true
-
gpio-reserved-ranges:
maxItems: 1
@@ -82,7 +76,7 @@
- compatible
- reg
-additionalProperties: false
+unevaluatedProperties: false
examples:
- |
diff --git a/dts/upstream/Bindings/pinctrl/qcom,msm8660-pinctrl.yaml b/dts/upstream/Bindings/pinctrl/qcom,msm8660-pinctrl.yaml
index a059716..61f5be2 100644
--- a/dts/upstream/Bindings/pinctrl/qcom,msm8660-pinctrl.yaml
+++ b/dts/upstream/Bindings/pinctrl/qcom,msm8660-pinctrl.yaml
@@ -23,13 +23,6 @@
interrupts:
maxItems: 1
- interrupt-controller: true
- "#interrupt-cells": true
- gpio-controller: true
- "#gpio-cells": true
- gpio-ranges: true
- wakeup-parent: true
-
gpio-reserved-ranges:
minItems: 1
maxItems: 86
@@ -92,7 +85,7 @@
- compatible
- reg
-additionalProperties: false
+unevaluatedProperties: false
examples:
- |
diff --git a/dts/upstream/Bindings/pinctrl/qcom,msm8909-tlmm.yaml b/dts/upstream/Bindings/pinctrl/qcom,msm8909-tlmm.yaml
index 5095e86..295dd5f 100644
--- a/dts/upstream/Bindings/pinctrl/qcom,msm8909-tlmm.yaml
+++ b/dts/upstream/Bindings/pinctrl/qcom,msm8909-tlmm.yaml
@@ -25,19 +25,7 @@
interrupts:
maxItems: 1
- interrupt-controller: true
- "#interrupt-cells": true
- gpio-controller: true
gpio-reserved-ranges: true
- "#gpio-cells": true
- gpio-ranges: true
- wakeup-parent: true
-
-required:
- - compatible
- - reg
-
-additionalProperties: false
patternProperties:
"-state$":
@@ -108,6 +96,12 @@
required:
- pins
+required:
+ - compatible
+ - reg
+
+unevaluatedProperties: false
+
examples:
- |
#include <dt-bindings/interrupt-controller/arm-gic.h>
diff --git a/dts/upstream/Bindings/pinctrl/qcom,msm8916-pinctrl.yaml b/dts/upstream/Bindings/pinctrl/qcom,msm8916-pinctrl.yaml
index 063d004..904af87 100644
--- a/dts/upstream/Bindings/pinctrl/qcom,msm8916-pinctrl.yaml
+++ b/dts/upstream/Bindings/pinctrl/qcom,msm8916-pinctrl.yaml
@@ -23,13 +23,6 @@
interrupts:
maxItems: 1
- interrupt-controller: true
- "#interrupt-cells": true
- gpio-controller: true
- "#gpio-cells": true
- gpio-ranges: true
- wakeup-parent: true
-
gpio-reserved-ranges:
minItems: 1
maxItems: 61
@@ -114,7 +107,7 @@
- compatible
- reg
-additionalProperties: false
+unevaluatedProperties: false
examples:
- |
diff --git a/dts/upstream/Bindings/pinctrl/qcom,msm8953-pinctrl.yaml b/dts/upstream/Bindings/pinctrl/qcom,msm8953-pinctrl.yaml
index 798aac9..8a3a962 100644
--- a/dts/upstream/Bindings/pinctrl/qcom,msm8953-pinctrl.yaml
+++ b/dts/upstream/Bindings/pinctrl/qcom,msm8953-pinctrl.yaml
@@ -22,12 +22,7 @@
interrupts:
maxItems: 1
- interrupt-controller: true
- "#interrupt-cells": true
- gpio-controller: true
gpio-reserved-ranges: true
- "#gpio-cells": true
- gpio-ranges: true
patternProperties:
"-state$":
@@ -117,7 +112,7 @@
- compatible
- reg
-additionalProperties: false
+unevaluatedProperties: false
examples:
- |
diff --git a/dts/upstream/Bindings/pinctrl/qcom,msm8960-pinctrl.yaml b/dts/upstream/Bindings/pinctrl/qcom,msm8960-pinctrl.yaml
index 9172b50..4661874 100644
--- a/dts/upstream/Bindings/pinctrl/qcom,msm8960-pinctrl.yaml
+++ b/dts/upstream/Bindings/pinctrl/qcom,msm8960-pinctrl.yaml
@@ -23,13 +23,6 @@
interrupts:
maxItems: 1
- interrupt-controller: true
- "#interrupt-cells": true
- gpio-controller: true
- "#gpio-cells": true
- gpio-ranges: true
- wakeup-parent: true
-
gpio-reserved-ranges:
minItems: 1
maxItems: 76
@@ -108,7 +101,7 @@
- compatible
- reg
-additionalProperties: false
+unevaluatedProperties: false
examples:
- |
diff --git a/dts/upstream/Bindings/pinctrl/qcom,msm8974-pinctrl.yaml b/dts/upstream/Bindings/pinctrl/qcom,msm8974-pinctrl.yaml
index 8a3be65..840fdaa 100644
--- a/dts/upstream/Bindings/pinctrl/qcom,msm8974-pinctrl.yaml
+++ b/dts/upstream/Bindings/pinctrl/qcom,msm8974-pinctrl.yaml
@@ -23,13 +23,6 @@
interrupts:
maxItems: 1
- interrupt-controller: true
- "#interrupt-cells": true
- gpio-controller: true
- "#gpio-cells": true
- gpio-ranges: true
- wakeup-parent: true
-
gpio-reserved-ranges:
minItems: 1
maxItems: 73
@@ -124,7 +117,7 @@
- compatible
- reg
-additionalProperties: false
+unevaluatedProperties: false
examples:
- |
diff --git a/dts/upstream/Bindings/pinctrl/qcom,msm8976-pinctrl.yaml b/dts/upstream/Bindings/pinctrl/qcom,msm8976-pinctrl.yaml
index ca95de0..d4391c1 100644
--- a/dts/upstream/Bindings/pinctrl/qcom,msm8976-pinctrl.yaml
+++ b/dts/upstream/Bindings/pinctrl/qcom,msm8976-pinctrl.yaml
@@ -23,13 +23,6 @@
interrupts:
maxItems: 1
- interrupt-controller: true
- "#interrupt-cells": true
- gpio-controller: true
- "#gpio-cells": true
- gpio-ranges: true
- wakeup-parent: true
-
gpio-reserved-ranges:
minItems: 1
maxItems: 73
@@ -104,7 +97,7 @@
- compatible
- reg
-additionalProperties: false
+unevaluatedProperties: false
examples:
- |
diff --git a/dts/upstream/Bindings/pinctrl/qcom,msm8994-pinctrl.yaml b/dts/upstream/Bindings/pinctrl/qcom,msm8994-pinctrl.yaml
index 41525ec..fa90981 100644
--- a/dts/upstream/Bindings/pinctrl/qcom,msm8994-pinctrl.yaml
+++ b/dts/upstream/Bindings/pinctrl/qcom,msm8994-pinctrl.yaml
@@ -25,13 +25,6 @@
interrupts:
maxItems: 1
- interrupt-controller: true
- "#interrupt-cells": true
- gpio-controller: true
- "#gpio-cells": true
- gpio-ranges: true
- wakeup-parent: true
-
gpio-reserved-ranges:
minItems: 1
maxItems: 73
@@ -114,7 +107,7 @@
- compatible
- reg
-additionalProperties: false
+unevaluatedProperties: false
examples:
- |
diff --git a/dts/upstream/Bindings/pinctrl/qcom,msm8996-pinctrl.yaml b/dts/upstream/Bindings/pinctrl/qcom,msm8996-pinctrl.yaml
index 59d406b..c5010c1 100644
--- a/dts/upstream/Bindings/pinctrl/qcom,msm8996-pinctrl.yaml
+++ b/dts/upstream/Bindings/pinctrl/qcom,msm8996-pinctrl.yaml
@@ -23,13 +23,6 @@
interrupts:
maxItems: 1
- interrupt-controller: true
- "#interrupt-cells": true
- gpio-controller: true
- "#gpio-cells": true
- gpio-ranges: true
- wakeup-parent: true
-
gpio-reserved-ranges:
minItems: 1
maxItems: 75
@@ -133,7 +126,7 @@
- compatible
- reg
-additionalProperties: false
+unevaluatedProperties: false
examples:
- |
diff --git a/dts/upstream/Bindings/pinctrl/qcom,msm8998-pinctrl.yaml b/dts/upstream/Bindings/pinctrl/qcom,msm8998-pinctrl.yaml
index bd6d7ca..bcaa231 100644
--- a/dts/upstream/Bindings/pinctrl/qcom,msm8998-pinctrl.yaml
+++ b/dts/upstream/Bindings/pinctrl/qcom,msm8998-pinctrl.yaml
@@ -23,13 +23,6 @@
interrupts:
maxItems: 1
- interrupt-controller: true
- "#interrupt-cells": true
- gpio-controller: true
- "#gpio-cells": true
- gpio-ranges: true
- wakeup-parent: true
-
gpio-reserved-ranges:
minItems: 1
maxItems: 75
@@ -118,7 +111,7 @@
- compatible
- reg
-additionalProperties: false
+unevaluatedProperties: false
examples:
- |
diff --git a/dts/upstream/Bindings/pinctrl/qcom,pmic-mpp.yaml b/dts/upstream/Bindings/pinctrl/qcom,pmic-mpp.yaml
index 80f9606..fe717d8 100644
--- a/dts/upstream/Bindings/pinctrl/qcom,pmic-mpp.yaml
+++ b/dts/upstream/Bindings/pinctrl/qcom,pmic-mpp.yaml
@@ -158,34 +158,40 @@
- |
#include <dt-bindings/pinctrl/qcom,pmic-mpp.h>
- pm8841_mpp: mpps@a000 {
- compatible = "qcom,pm8841-mpp", "qcom,spmi-mpp";
- reg = <0xa000 0>;
- gpio-controller;
- #gpio-cells = <2>;
- gpio-ranges = <&pm8841_mpp 0 0 4>;
- gpio-line-names = "VDD_PX_BIAS", "WLAN_LED_CTRL",
- "BT_LED_CTRL", "GPIO-F";
- interrupt-controller;
- #interrupt-cells = <2>;
+ pmic {
+ #address-cells = <1>;
+ #size-cells = <0>;
- pinctrl-names = "default";
- pinctrl-0 = <&pm8841_default>;
+ pm8841_mpp: mpps@a000 {
+ compatible = "qcom,pm8841-mpp", "qcom,spmi-mpp";
+ reg = <0xa000>;
- mpp1-state {
- pins = "mpp1";
- function = "digital";
- input-enable;
- power-source = <PM8841_MPP_S3>;
- };
+ gpio-controller;
+ #gpio-cells = <2>;
+ gpio-ranges = <&pm8841_mpp 0 0 4>;
+ gpio-line-names = "VDD_PX_BIAS", "WLAN_LED_CTRL",
+ "BT_LED_CTRL", "GPIO-F";
+ interrupt-controller;
+ #interrupt-cells = <2>;
- default-state {
- gpio-pins {
- pins = "mpp1", "mpp2", "mpp3", "mpp4";
- function = "digital";
- input-enable;
- power-source = <PM8841_MPP_S3>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pm8841_default>;
+
+ mpp1-state {
+ pins = "mpp1";
+ function = "digital";
+ input-enable;
+ power-source = <PM8841_MPP_S3>;
+ };
+
+ default-state {
+ gpio-pins {
+ pins = "mpp1", "mpp2", "mpp3", "mpp4";
+ function = "digital";
+ input-enable;
+ power-source = <PM8841_MPP_S3>;
+ };
+ };
};
- };
};
...
diff --git a/dts/upstream/Bindings/pinctrl/qcom,qcm2290-tlmm.yaml b/dts/upstream/Bindings/pinctrl/qcom,qcm2290-tlmm.yaml
index c323f6d..e123beb 100644
--- a/dts/upstream/Bindings/pinctrl/qcom,qcm2290-tlmm.yaml
+++ b/dts/upstream/Bindings/pinctrl/qcom,qcm2290-tlmm.yaml
@@ -22,13 +22,6 @@
interrupts:
maxItems: 1
- interrupt-controller: true
- "#interrupt-cells": true
- gpio-controller: true
- "#gpio-cells": true
- gpio-ranges: true
- wakeup-parent: true
-
patternProperties:
"-state$":
oneOf:
@@ -92,7 +85,7 @@
- compatible
- reg
-additionalProperties: false
+unevaluatedProperties: false
examples:
- |
diff --git a/dts/upstream/Bindings/pinctrl/qcom,qcs404-pinctrl.yaml b/dts/upstream/Bindings/pinctrl/qcom,qcs404-pinctrl.yaml
index b1b9cd3..4009501 100644
--- a/dts/upstream/Bindings/pinctrl/qcom,qcs404-pinctrl.yaml
+++ b/dts/upstream/Bindings/pinctrl/qcom,qcs404-pinctrl.yaml
@@ -29,13 +29,6 @@
interrupts:
maxItems: 1
- interrupt-controller: true
- "#interrupt-cells": true
- gpio-controller: true
- "#gpio-cells": true
- gpio-ranges: true
- wakeup-parent: true
-
gpio-reserved-ranges:
minItems: 1
maxItems: 60
@@ -130,7 +123,7 @@
- compatible
- reg
-additionalProperties: false
+unevaluatedProperties: false
examples:
- |
diff --git a/dts/upstream/Bindings/pinctrl/qcom,qdu1000-tlmm.yaml b/dts/upstream/Bindings/pinctrl/qcom,qdu1000-tlmm.yaml
index 237cac4..88afeae 100644
--- a/dts/upstream/Bindings/pinctrl/qcom,qdu1000-tlmm.yaml
+++ b/dts/upstream/Bindings/pinctrl/qcom,qdu1000-tlmm.yaml
@@ -23,10 +23,8 @@
reg:
maxItems: 1
- interrupts: true
- interrupt-controller: true
- "#interrupt-cells": true
- gpio-controller: true
+ interrupts:
+ maxItems: 1
gpio-reserved-ranges:
minItems: 1
@@ -35,10 +33,6 @@
gpio-line-names:
maxItems: 151
- "#gpio-cells": true
- gpio-ranges: true
- wakeup-parent: true
-
patternProperties:
"-state$":
oneOf:
@@ -101,7 +95,7 @@
- compatible
- reg
-additionalProperties: false
+unevaluatedProperties: false
examples:
- |
diff --git a/dts/upstream/Bindings/pinctrl/qcom,sa8775p-tlmm.yaml b/dts/upstream/Bindings/pinctrl/qcom,sa8775p-tlmm.yaml
index 2173c52..e9abbf2 100644
--- a/dts/upstream/Bindings/pinctrl/qcom,sa8775p-tlmm.yaml
+++ b/dts/upstream/Bindings/pinctrl/qcom,sa8775p-tlmm.yaml
@@ -22,13 +22,8 @@
reg:
maxItems: 1
- interrupts: true
- interrupt-controller: true
- "#interrupt-cells": true
- gpio-controller: true
- "#gpio-cells": true
- gpio-ranges: true
- wakeup-parent: true
+ interrupts:
+ maxItems: 1
gpio-reserved-ranges:
minItems: 1
@@ -37,12 +32,6 @@
gpio-line-names:
maxItems: 148
-required:
- - compatible
- - reg
-
-additionalProperties: false
-
patternProperties:
"-state$":
oneOf:
@@ -108,6 +97,12 @@
required:
- pins
+required:
+ - compatible
+ - reg
+
+unevaluatedProperties: false
+
examples:
- |
#include <dt-bindings/interrupt-controller/arm-gic.h>
diff --git a/dts/upstream/Bindings/pinctrl/qcom,sc7180-pinctrl.yaml b/dts/upstream/Bindings/pinctrl/qcom,sc7180-pinctrl.yaml
index 573e459..5606f21 100644
--- a/dts/upstream/Bindings/pinctrl/qcom,sc7180-pinctrl.yaml
+++ b/dts/upstream/Bindings/pinctrl/qcom,sc7180-pinctrl.yaml
@@ -29,13 +29,6 @@
interrupts:
maxItems: 1
- interrupt-controller: true
- "#interrupt-cells": true
- gpio-controller: true
- "#gpio-cells": true
- gpio-ranges: true
- wakeup-parent: true
-
gpio-reserved-ranges:
minItems: 1
maxItems: 60
@@ -112,7 +105,7 @@
- reg
- reg-names
-additionalProperties: false
+unevaluatedProperties: false
examples:
- |
diff --git a/dts/upstream/Bindings/pinctrl/qcom,sc7280-lpass-lpi-pinctrl.yaml b/dts/upstream/Bindings/pinctrl/qcom,sc7280-lpass-lpi-pinctrl.yaml
index 00c5a00..08801cc 100644
--- a/dts/upstream/Bindings/pinctrl/qcom,sc7280-lpass-lpi-pinctrl.yaml
+++ b/dts/upstream/Bindings/pinctrl/qcom,sc7280-lpass-lpi-pinctrl.yaml
@@ -20,16 +20,6 @@
reg:
maxItems: 2
- gpio-controller: true
-
- "#gpio-cells":
- description: Specifying the pin number and flags, as defined in
- include/dt-bindings/gpio/gpio.h
- const: 2
-
- gpio-ranges:
- maxItems: 1
-
patternProperties:
"-state$":
oneOf:
@@ -45,7 +35,8 @@
description:
Pinctrl node's client devices use subnodes for desired pin configuration.
Client device subnodes use below standard properties.
- $ref: /schemas/pinctrl/pincfg-node.yaml
+ $ref: qcom,lpass-lpi-common.yaml#/$defs/qcom-tlmm-state
+ unevaluatedProperties: false
properties:
pins:
@@ -68,42 +59,14 @@
Specify the alternative function to be configured for the specified
pins.
- drive-strength:
- enum: [2, 4, 6, 8, 10, 12, 14, 16]
- default: 2
- description:
- Selects the drive strength for the specified pins, in mA.
-
- slew-rate:
- enum: [0, 1, 2, 3]
- default: 0
- description: |
- 0: No adjustments
- 1: Higher Slew rate (faster edges)
- 2: Lower Slew rate (slower edges)
- 3: Reserved (No adjustments)
-
- bias-pull-down: true
- bias-pull-up: true
- bias-bus-hold: true
- bias-disable: true
- output-high: true
- output-low: true
-
- required:
- - pins
- - function
-
- additionalProperties: false
-
required:
- compatible
- reg
- - gpio-controller
- - "#gpio-cells"
- - gpio-ranges
+
+allOf:
+ - $ref: qcom,lpass-lpi-common.yaml#
-additionalProperties: false
+unevaluatedProperties: false
examples:
- |
diff --git a/dts/upstream/Bindings/pinctrl/qcom,sc7280-pinctrl.yaml b/dts/upstream/Bindings/pinctrl/qcom,sc7280-pinctrl.yaml
index c8735ab..5329fe2 100644
--- a/dts/upstream/Bindings/pinctrl/qcom,sc7280-pinctrl.yaml
+++ b/dts/upstream/Bindings/pinctrl/qcom,sc7280-pinctrl.yaml
@@ -23,24 +23,6 @@
description: Specifies the TLMM summary IRQ
maxItems: 1
- interrupt-controller: true
-
- '#interrupt-cells':
- description:
- Specifies the PIN numbers and Flags, as defined in defined in
- include/dt-bindings/interrupt-controller/irq.h
- const: 2
-
- gpio-controller: true
-
- '#gpio-cells':
- description: Specifying the pin number and flags, as defined in
- include/dt-bindings/gpio/gpio.h
- const: 2
-
- gpio-ranges:
- maxItems: 1
-
gpio-reserved-ranges:
minItems: 1
maxItems: 88
@@ -48,8 +30,6 @@
gpio-line-names:
maxItems: 175
- wakeup-parent: true
-
patternProperties:
"-state$":
oneOf:
@@ -124,14 +104,8 @@
required:
- compatible
- reg
- - interrupts
- - interrupt-controller
- - '#interrupt-cells'
- - gpio-controller
- - '#gpio-cells'
- - gpio-ranges
-additionalProperties: false
+unevaluatedProperties: false
examples:
- |
diff --git a/dts/upstream/Bindings/pinctrl/qcom,sc8180x-tlmm.yaml b/dts/upstream/Bindings/pinctrl/qcom,sc8180x-tlmm.yaml
index b086a51..c122bb8 100644
--- a/dts/upstream/Bindings/pinctrl/qcom,sc8180x-tlmm.yaml
+++ b/dts/upstream/Bindings/pinctrl/qcom,sc8180x-tlmm.yaml
@@ -31,20 +31,7 @@
interrupts:
maxItems: 1
- interrupt-controller: true
- '#interrupt-cells': true
- gpio-controller: true
gpio-reserved-ranges: true
- '#gpio-cells': true
- gpio-ranges: true
- wakeup-parent: true
-
-required:
- - compatible
- - reg
- - reg-names
-
-additionalProperties: false
patternProperties:
"-state$":
@@ -106,6 +93,13 @@
required:
- pins
+required:
+ - compatible
+ - reg
+ - reg-names
+
+unevaluatedProperties: false
+
examples:
- |
#include <dt-bindings/interrupt-controller/arm-gic.h>
diff --git a/dts/upstream/Bindings/pinctrl/qcom,sc8280xp-lpass-lpi-pinctrl.yaml b/dts/upstream/Bindings/pinctrl/qcom,sc8280xp-lpass-lpi-pinctrl.yaml
index a9167da..240e6d4 100644
--- a/dts/upstream/Bindings/pinctrl/qcom,sc8280xp-lpass-lpi-pinctrl.yaml
+++ b/dts/upstream/Bindings/pinctrl/qcom,sc8280xp-lpass-lpi-pinctrl.yaml
@@ -32,16 +32,6 @@
- const: core
- const: audio
- gpio-controller: true
-
- "#gpio-cells":
- description: Specifying the pin number and flags, as defined in
- include/dt-bindings/gpio/gpio.h
- const: 2
-
- gpio-ranges:
- maxItems: 1
-
patternProperties:
"-state$":
oneOf:
@@ -57,7 +47,8 @@
description:
Pinctrl node's client devices use subnodes for desired pin configuration.
Client device subnodes use below standard properties.
- $ref: /schemas/pinctrl/pincfg-node.yaml
+ $ref: qcom,lpass-lpi-common.yaml#/$defs/qcom-tlmm-state
+ unevaluatedProperties: false
properties:
pins:
@@ -79,48 +70,16 @@
Specify the alternative function to be configured for the specified
pins.
- drive-strength:
- enum: [2, 4, 6, 8, 10, 12, 14, 16]
- default: 2
- description:
- Selects the drive strength for the specified pins, in mA.
-
- slew-rate:
- enum: [0, 1, 2, 3]
- default: 0
- description: |
- 0: No adjustments
- 1: Higher Slew rate (faster edges)
- 2: Lower Slew rate (slower edges)
- 3: Reserved (No adjustments)
-
- bias-bus-hold: true
- bias-pull-down: true
- bias-pull-up: true
- bias-disable: true
- input-enable: true
- output-high: true
- output-low: true
-
- required:
- - pins
- - function
-
- additionalProperties: false
-
allOf:
- - $ref: pinctrl.yaml#
+ - $ref: qcom,lpass-lpi-common.yaml#
required:
- compatible
- reg
- clocks
- clock-names
- - gpio-controller
- - "#gpio-cells"
- - gpio-ranges
-additionalProperties: false
+unevaluatedProperties: false
examples:
- |
diff --git a/dts/upstream/Bindings/pinctrl/qcom,sc8280xp-tlmm.yaml b/dts/upstream/Bindings/pinctrl/qcom,sc8280xp-tlmm.yaml
index 4bd6d79..ed344de 100644
--- a/dts/upstream/Bindings/pinctrl/qcom,sc8280xp-tlmm.yaml
+++ b/dts/upstream/Bindings/pinctrl/qcom,sc8280xp-tlmm.yaml
@@ -25,19 +25,7 @@
interrupts:
maxItems: 1
- interrupt-controller: true
- "#interrupt-cells": true
- gpio-controller: true
gpio-reserved-ranges: true
- "#gpio-cells": true
- gpio-ranges: true
- wakeup-parent: true
-
-required:
- - compatible
- - reg
-
-additionalProperties: false
patternProperties:
"-state$":
@@ -108,6 +96,12 @@
required:
- pins
+required:
+ - compatible
+ - reg
+
+unevaluatedProperties: false
+
examples:
- |
#include <dt-bindings/interrupt-controller/arm-gic.h>
diff --git a/dts/upstream/Bindings/pinctrl/qcom,sdm630-pinctrl.yaml b/dts/upstream/Bindings/pinctrl/qcom,sdm630-pinctrl.yaml
index 508e063..a00cb43 100644
--- a/dts/upstream/Bindings/pinctrl/qcom,sdm630-pinctrl.yaml
+++ b/dts/upstream/Bindings/pinctrl/qcom,sdm630-pinctrl.yaml
@@ -34,10 +34,6 @@
interrupts:
maxItems: 1
- interrupt-controller: true
- "#interrupt-cells": true
- gpio-controller: true
-
gpio-reserved-ranges:
minItems: 1
maxItems: 57
@@ -45,10 +41,6 @@
gpio-line-names:
maxItems: 114
- "#gpio-cells": true
- gpio-ranges: true
- wakeup-parent: true
-
patternProperties:
"-state$":
oneOf:
@@ -130,7 +122,7 @@
- compatible
- reg
-additionalProperties: false
+unevaluatedProperties: false
examples:
- |
diff --git a/dts/upstream/Bindings/pinctrl/qcom,sdm670-tlmm.yaml b/dts/upstream/Bindings/pinctrl/qcom,sdm670-tlmm.yaml
index 84a15f7..b56e717 100644
--- a/dts/upstream/Bindings/pinctrl/qcom,sdm670-tlmm.yaml
+++ b/dts/upstream/Bindings/pinctrl/qcom,sdm670-tlmm.yaml
@@ -25,23 +25,10 @@
interrupts:
maxItems: 1
- interrupt-controller: true
- "#interrupt-cells": true
- gpio-controller: true
gpio-reserved-ranges:
minItems: 1
maxItems: 75
- "#gpio-cells": true
- gpio-ranges: true
- wakeup-parent: true
-
-required:
- - compatible
- - reg
-
-additionalProperties: false
-
patternProperties:
"-state$":
oneOf:
@@ -98,6 +85,12 @@
required:
- pins
+required:
+ - compatible
+ - reg
+
+unevaluatedProperties: false
+
examples:
- |
#include <dt-bindings/interrupt-controller/arm-gic.h>
diff --git a/dts/upstream/Bindings/pinctrl/qcom,sdm845-pinctrl.yaml b/dts/upstream/Bindings/pinctrl/qcom,sdm845-pinctrl.yaml
index d301881..dfe5616 100644
--- a/dts/upstream/Bindings/pinctrl/qcom,sdm845-pinctrl.yaml
+++ b/dts/upstream/Bindings/pinctrl/qcom,sdm845-pinctrl.yaml
@@ -26,10 +26,6 @@
interrupts:
maxItems: 1
- interrupt-controller: true
- "#interrupt-cells": true
- gpio-controller: true
-
gpio-reserved-ranges:
minItems: 1
maxItems: 75
@@ -37,10 +33,6 @@
gpio-line-names:
maxItems: 150
- "#gpio-cells": true
- gpio-ranges: true
- wakeup-parent: true
-
patternProperties:
"-state$":
oneOf:
@@ -110,7 +102,7 @@
- compatible
- reg
-additionalProperties: false
+unevaluatedProperties: false
examples:
- |
diff --git a/dts/upstream/Bindings/pinctrl/qcom,sdx55-pinctrl.yaml b/dts/upstream/Bindings/pinctrl/qcom,sdx55-pinctrl.yaml
index 67af99d..edbcff9 100644
--- a/dts/upstream/Bindings/pinctrl/qcom,sdx55-pinctrl.yaml
+++ b/dts/upstream/Bindings/pinctrl/qcom,sdx55-pinctrl.yaml
@@ -23,12 +23,6 @@
interrupts:
maxItems: 1
- interrupt-controller: true
- "#interrupt-cells": true
- gpio-controller: true
- "#gpio-cells": true
- gpio-ranges: true
-
gpio-reserved-ranges:
maxItems: 1
@@ -102,7 +96,7 @@
- compatible
- reg
-additionalProperties: false
+unevaluatedProperties: false
examples:
- |
diff --git a/dts/upstream/Bindings/pinctrl/qcom,sdx65-tlmm.yaml b/dts/upstream/Bindings/pinctrl/qcom,sdx65-tlmm.yaml
index 2731978..a31b638 100644
--- a/dts/upstream/Bindings/pinctrl/qcom,sdx65-tlmm.yaml
+++ b/dts/upstream/Bindings/pinctrl/qcom,sdx65-tlmm.yaml
@@ -22,12 +22,6 @@
interrupts:
maxItems: 1
- interrupt-controller: true
- "#interrupt-cells": true
- gpio-controller: true
- "#gpio-cells": true
- gpio-ranges: true
-
gpio-reserved-ranges:
maxItems: 1
@@ -122,7 +116,7 @@
- compatible
- reg
-additionalProperties: false
+unevaluatedProperties: false
examples:
- |
diff --git a/dts/upstream/Bindings/pinctrl/qcom,sdx75-tlmm.yaml b/dts/upstream/Bindings/pinctrl/qcom,sdx75-tlmm.yaml
index 7cb96aa..cb1d978 100644
--- a/dts/upstream/Bindings/pinctrl/qcom,sdx75-tlmm.yaml
+++ b/dts/upstream/Bindings/pinctrl/qcom,sdx75-tlmm.yaml
@@ -22,10 +22,8 @@
reg:
maxItems: 1
- interrupts: true
- interrupt-controller: true
- "#interrupt-cells": true
- gpio-controller: true
+ interrupts:
+ maxItems: 1
gpio-reserved-ranges:
minItems: 1
@@ -34,10 +32,6 @@
gpio-line-names:
maxItems: 133
- "#gpio-cells": true
- gpio-ranges: true
- wakeup-parent: true
-
patternProperties:
"-state$":
oneOf:
@@ -100,7 +94,7 @@
- compatible
- reg
-additionalProperties: false
+unevaluatedProperties: false
examples:
- |
diff --git a/dts/upstream/Bindings/pinctrl/qcom,sm4450-tlmm.yaml b/dts/upstream/Bindings/pinctrl/qcom,sm4450-tlmm.yaml
new file mode 100644
index 0000000..bb08ca5
--- /dev/null
+++ b/dts/upstream/Bindings/pinctrl/qcom,sm4450-tlmm.yaml
@@ -0,0 +1,151 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/pinctrl/qcom,sm4450-tlmm.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Qualcomm Technologies, Inc. SM4450 TLMM block
+
+maintainers:
+ - Tengfei Fan <quic_tengfan@quicinc.com>
+
+description:
+ Top Level Mode Multiplexer pin controller in Qualcomm SM4450 SoC.
+
+allOf:
+ - $ref: /schemas/pinctrl/qcom,tlmm-common.yaml#
+
+properties:
+ compatible:
+ const: qcom,sm4450-pinctrl
+
+ reg:
+ maxItems: 1
+
+ interrupts: true
+ interrupt-controller: true
+ "#interrupt-cells": true
+ gpio-controller: true
+
+ gpio-reserved-ranges:
+ minItems: 1
+ maxItems: 68
+
+ gpio-line-names:
+ maxItems: 136
+
+ "#gpio-cells": true
+ gpio-ranges: true
+ wakeup-parent: true
+
+patternProperties:
+ "-state$":
+ oneOf:
+ - $ref: "#/$defs/qcom-sm4450-tlmm-state"
+ - patternProperties:
+ "-pins$":
+ $ref: "#/$defs/qcom-sm4450-tlmm-state"
+ additionalProperties: false
+
+$defs:
+ qcom-sm4450-tlmm-state:
+ type: object
+ description:
+ Pinctrl node's client devices use subnodes for desired pin configuration.
+ Client device subnodes use below standard properties.
+ $ref: qcom,tlmm-common.yaml#/$defs/qcom-tlmm-state
+ unevaluatedProperties: false
+
+ properties:
+ pins:
+ description:
+ List of gpio pins affected by the properties specified in this
+ subnode.
+ items:
+ oneOf:
+ - pattern: "^gpio([0-9]|[1-9][0-9]|1[0-2][0-9]|13[0-5])$"
+ - enum: [ sdc2_clk, sdc2_cmd, sdc2_data, ufs_reset ]
+ minItems: 1
+ maxItems: 36
+
+ function:
+ description:
+ Specify the alternative function to be configured for the specified
+ pins.
+ enum: [ gpio, atest_char, atest_char0, atest_char1, atest_char2,
+ atest_char3, atest_usb0, atest_usb00, atest_usb01, atest_usb02,
+ atest_usb03, audio_ref, cam_mclk, cci_async, cci_i2c,
+ cci_timer0, cci_timer1, cci_timer2, cci_timer3, cci_timer4,
+ cmu_rng0, cmu_rng1, cmu_rng2, cmu_rng3, coex_uart1, cri_trng,
+ cri_trng0, cri_trng1, dbg_out, ddr_bist, ddr_pxi0, ddr_pxi1,
+ dp0_hot, gcc_gp1, gcc_gp2, gcc_gp3, host2wlan_sol, ibi_i3c,
+ jitter_bist, mdp_vsync, mdp_vsync0, mdp_vsync1, mdp_vsync2,
+ mdp_vsync3, mi2s0_data0, mi2s0_data1, mi2s0_sck, mi2s0_ws,
+ mi2s2_data0, mi2s2_data1, mi2s2_sck, mi2s2_ws, mi2s_mclk0,
+ mi2s_mclk1, nav_gpio0, nav_gpio1, nav_gpio2, pcie0_clk,
+ phase_flag0, phase_flag1, phase_flag10, phase_flag11,
+ phase_flag12, phase_flag13, phase_flag14, phase_flag15,
+ phase_flag16, phase_flag17, phase_flag18, phase_flag19,
+ phase_flag2, phase_flag20, phase_flag21, phase_flag22,
+ phase_flag23, phase_flag24, phase_flag25, phase_flag26,
+ phase_flag27, phase_flag28, phase_flag29, phase_flag3,
+ phase_flag30, phase_flag31, phase_flag4, phase_flag5,
+ phase_flag6, phase_flag7, phase_flag8, phase_flag9,
+ pll_bist, pll_clk, prng_rosc0, prng_rosc1, prng_rosc2,
+ prng_rosc3, qdss_cti, qdss_gpio, qdss_gpio0, qdss_gpio1,
+ qdss_gpio10, qdss_gpio11, qdss_gpio12, qdss_gpio13, qdss_gpio14,
+ qdss_gpio15, qdss_gpio2, qdss_gpio3, qdss_gpio4, qdss_gpio5,
+ qdss_gpio6, qdss_gpio7, qdss_gpio8, qdss_gpio9, qlink0_enable,
+ qlink0_request, qlink0_wmss, qlink1_enable, qlink1_request,
+ qlink1_wmss, qlink2_enable, qlink2_request, qlink2_wmss,
+ qup0_se0, qup0_se1, qup0_se2, qup0_se3, qup0_se4, qup0_se5,
+ qup0_se6, qup0_se7, qup1_se0, qup1_se1, qup1_se2, qup1_se3,
+ qup1_se4, qup1_se5, qup1_se6, sd_write, tb_trig, tgu_ch0,
+ tgu_ch1, tgu_ch2, tgu_ch3, tmess_prng0, tmess_prng1,
+ tmess_prng2, tmess_prng3, tsense_pwm1, tsense_pwm2, uim0_clk,
+ uim0_data, uim0_present, uim0_reset, uim1_clk, uim1_data,
+ uim1_present, uim1_reset, usb0_hs, usb0_phy, vfr_0, vfr_1,
+ vsense_trigger ]
+
+ required:
+ - pins
+
+required:
+ - compatible
+ - reg
+
+additionalProperties: false
+
+examples:
+ - |
+ #include <dt-bindings/interrupt-controller/arm-gic.h>
+ tlmm: pinctrl@f100000 {
+ compatible = "qcom,sm4450-tlmm";
+ reg = <0x0f100000 0x300000>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ gpio-ranges = <&tlmm 0 0 137>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>;
+
+ gpio-wo-state {
+ pins = "gpio1";
+ function = "gpio";
+ };
+
+ uart-w-state {
+ rx-pins {
+ pins = "gpio23";
+ function = "qup1_se2";
+ bias-pull-up;
+ };
+
+ tx-pins {
+ pins = "gpio22";
+ function = "qup1_se2";
+ bias-disable;
+ };
+ };
+ };
+...
diff --git a/dts/upstream/Bindings/pinctrl/qcom,sm6115-lpass-lpi-pinctrl.yaml b/dts/upstream/Bindings/pinctrl/qcom,sm6115-lpass-lpi-pinctrl.yaml
index abac331..f4cf2ce 100644
--- a/dts/upstream/Bindings/pinctrl/qcom,sm6115-lpass-lpi-pinctrl.yaml
+++ b/dts/upstream/Bindings/pinctrl/qcom,sm6115-lpass-lpi-pinctrl.yaml
@@ -31,16 +31,6 @@
items:
- const: audio
- gpio-controller: true
-
- "#gpio-cells":
- description: Specifying the pin number and flags, as defined in
- include/dt-bindings/gpio/gpio.h
- const: 2
-
- gpio-ranges:
- maxItems: 1
-
patternProperties:
"-state$":
oneOf:
@@ -56,7 +46,8 @@
description:
Pinctrl node's client devices use subnodes for desired pin configuration.
Client device subnodes use below standard properties.
- $ref: /schemas/pinctrl/pincfg-node.yaml
+ $ref: qcom,lpass-lpi-common.yaml#/$defs/qcom-tlmm-state
+ unevaluatedProperties: false
properties:
pins:
@@ -75,48 +66,17 @@
Specify the alternative function to be configured for the specified
pins.
- drive-strength:
- enum: [2, 4, 6, 8, 10, 12, 14, 16]
- default: 2
- description:
- Selects the drive strength for the specified pins, in mA.
-
- slew-rate:
- enum: [0, 1, 2, 3]
- default: 0
- description: |
- 0: No adjustments
- 1: Higher Slew rate (faster edges)
- 2: Lower Slew rate (slower edges)
- 3: Reserved (No adjustments)
-
- bias-bus-hold: true
- bias-pull-down: true
- bias-pull-up: true
- bias-disable: true
- input-enable: true
- output-high: true
- output-low: true
-
- required:
- - pins
- - function
-
- additionalProperties: false
allOf:
- - $ref: pinctrl.yaml#
+ - $ref: qcom,lpass-lpi-common.yaml#
required:
- compatible
- reg
- clocks
- clock-names
- - gpio-controller
- - "#gpio-cells"
- - gpio-ranges
-additionalProperties: false
+unevaluatedProperties: false
examples:
- |
diff --git a/dts/upstream/Bindings/pinctrl/qcom,sm6115-tlmm.yaml b/dts/upstream/Bindings/pinctrl/qcom,sm6115-tlmm.yaml
index 871df54..7f36f9b 100644
--- a/dts/upstream/Bindings/pinctrl/qcom,sm6115-tlmm.yaml
+++ b/dts/upstream/Bindings/pinctrl/qcom,sm6115-tlmm.yaml
@@ -29,13 +29,7 @@
interrupts:
maxItems: 1
- interrupt-controller: true
- "#interrupt-cells": true
- gpio-controller: true
- "#gpio-cells": true
- gpio-ranges: true
gpio-reserved-ranges: true
- wakeup-parent: true
patternProperties:
"-state$":
@@ -97,7 +91,7 @@
- reg
- reg-names
-additionalProperties: false
+unevaluatedProperties: false
examples:
- |
diff --git a/dts/upstream/Bindings/pinctrl/qcom,sm6125-tlmm.yaml b/dts/upstream/Bindings/pinctrl/qcom,sm6125-tlmm.yaml
index 8d77707..ddeaeaa 100644
--- a/dts/upstream/Bindings/pinctrl/qcom,sm6125-tlmm.yaml
+++ b/dts/upstream/Bindings/pinctrl/qcom,sm6125-tlmm.yaml
@@ -30,20 +30,7 @@
interrupts:
maxItems: 1
- interrupt-controller: true
- "#interrupt-cells": true
- gpio-controller: true
gpio-reserved-ranges: true
- "#gpio-cells": true
- gpio-ranges: true
- wakeup-parent: true
-
-required:
- - compatible
- - reg
- - reg-names
-
-additionalProperties: false
patternProperties:
"-state$":
@@ -105,6 +92,13 @@
required:
- pins
+required:
+ - compatible
+ - reg
+ - reg-names
+
+unevaluatedProperties: false
+
examples:
- |
#include <dt-bindings/interrupt-controller/arm-gic.h>
diff --git a/dts/upstream/Bindings/pinctrl/qcom,sm6350-tlmm.yaml b/dts/upstream/Bindings/pinctrl/qcom,sm6350-tlmm.yaml
index 27af379..a4771f8 100644
--- a/dts/upstream/Bindings/pinctrl/qcom,sm6350-tlmm.yaml
+++ b/dts/upstream/Bindings/pinctrl/qcom,sm6350-tlmm.yaml
@@ -26,10 +26,6 @@
minItems: 9
maxItems: 9
- interrupt-controller: true
- "#interrupt-cells": true
- gpio-controller: true
-
gpio-reserved-ranges:
minItems: 1
maxItems: 78
@@ -37,16 +33,6 @@
gpio-line-names:
maxItems: 156
- "#gpio-cells": true
- gpio-ranges: true
- wakeup-parent: true
-
-required:
- - compatible
- - reg
-
-additionalProperties: false
-
patternProperties:
"-state$":
oneOf:
@@ -112,6 +98,12 @@
required:
- pins
+required:
+ - compatible
+ - reg
+
+unevaluatedProperties: false
+
examples:
- |
#include <dt-bindings/interrupt-controller/arm-gic.h>
diff --git a/dts/upstream/Bindings/pinctrl/qcom,sm6375-tlmm.yaml b/dts/upstream/Bindings/pinctrl/qcom,sm6375-tlmm.yaml
index 6e02ba2..047f828 100644
--- a/dts/upstream/Bindings/pinctrl/qcom,sm6375-tlmm.yaml
+++ b/dts/upstream/Bindings/pinctrl/qcom,sm6375-tlmm.yaml
@@ -25,19 +25,7 @@
interrupts:
maxItems: 1
- interrupt-controller: true
- "#interrupt-cells": true
- gpio-controller: true
gpio-reserved-ranges: true
- "#gpio-cells": true
- gpio-ranges: true
- wakeup-parent: true
-
-required:
- - compatible
- - reg
-
-additionalProperties: false
patternProperties:
"-state$":
@@ -113,6 +101,12 @@
required:
- pins
+required:
+ - compatible
+ - reg
+
+unevaluatedProperties: false
+
examples:
- |
#include <dt-bindings/interrupt-controller/arm-gic.h>
diff --git a/dts/upstream/Bindings/pinctrl/qcom,sm7150-tlmm.yaml b/dts/upstream/Bindings/pinctrl/qcom,sm7150-tlmm.yaml
index ede0f3a..7f23f93 100644
--- a/dts/upstream/Bindings/pinctrl/qcom,sm7150-tlmm.yaml
+++ b/dts/upstream/Bindings/pinctrl/qcom,sm7150-tlmm.yaml
@@ -32,13 +32,6 @@
interrupts:
maxItems: 1
- interrupt-controller: true
- "#interrupt-cells": true
- gpio-controller: true
- "#gpio-cells": true
- gpio-ranges: true
- wakeup-parent: true
-
gpio-reserved-ranges:
minItems: 1
maxItems: 60
@@ -111,7 +104,7 @@
- reg
- reg-names
-additionalProperties: false
+unevaluatedProperties: false
examples:
- |
diff --git a/dts/upstream/Bindings/pinctrl/qcom,sm8150-pinctrl.yaml b/dts/upstream/Bindings/pinctrl/qcom,sm8150-pinctrl.yaml
index c643962..bdb7ed4 100644
--- a/dts/upstream/Bindings/pinctrl/qcom,sm8150-pinctrl.yaml
+++ b/dts/upstream/Bindings/pinctrl/qcom,sm8150-pinctrl.yaml
@@ -30,13 +30,6 @@
interrupts:
maxItems: 1
- interrupt-controller: true
- "#interrupt-cells": true
- gpio-controller: true
- "#gpio-cells": true
- gpio-ranges: true
- wakeup-parent: true
-
gpio-reserved-ranges:
minItems: 1
maxItems: 88
@@ -113,7 +106,7 @@
- reg
- reg-names
-additionalProperties: false
+unevaluatedProperties: false
examples:
- |
diff --git a/dts/upstream/Bindings/pinctrl/qcom,sm8250-lpass-lpi-pinctrl.yaml b/dts/upstream/Bindings/pinctrl/qcom,sm8250-lpass-lpi-pinctrl.yaml
index 4b4be7e..750c996 100644
--- a/dts/upstream/Bindings/pinctrl/qcom,sm8250-lpass-lpi-pinctrl.yaml
+++ b/dts/upstream/Bindings/pinctrl/qcom,sm8250-lpass-lpi-pinctrl.yaml
@@ -30,16 +30,6 @@
- const: core
- const: audio
- gpio-controller: true
-
- "#gpio-cells":
- description: Specifying the pin number and flags, as defined in
- include/dt-bindings/gpio/gpio.h
- const: 2
-
- gpio-ranges:
- maxItems: 1
-
patternProperties:
"-state$":
oneOf:
@@ -55,7 +45,8 @@
description:
Pinctrl node's client devices use subnodes for desired pin configuration.
Client device subnodes use below standard properties.
- $ref: /schemas/pinctrl/pincfg-node.yaml
+ $ref: qcom,lpass-lpi-common.yaml#/$defs/qcom-tlmm-state
+ unevaluatedProperties: false
properties:
pins:
@@ -78,48 +69,16 @@
Specify the alternative function to be configured for the specified
pins.
- drive-strength:
- enum: [2, 4, 6, 8, 10, 12, 14, 16]
- default: 2
- description:
- Selects the drive strength for the specified pins, in mA.
-
- slew-rate:
- enum: [0, 1, 2, 3]
- default: 0
- description: |
- 0: No adjustments
- 1: Higher Slew rate (faster edges)
- 2: Lower Slew rate (slower edges)
- 3: Reserved (No adjustments)
-
- bias-pull-down: true
- bias-pull-up: true
- bias-bus-hold: true
- bias-disable: true
- input-enable: true
- output-high: true
- output-low: true
-
- required:
- - pins
- - function
-
- additionalProperties: false
-
allOf:
- - $ref: pinctrl.yaml#
+ - $ref: qcom,lpass-lpi-common.yaml#
required:
- compatible
- reg
- clocks
- clock-names
- - gpio-controller
- - "#gpio-cells"
- - gpio-ranges
-additionalProperties: false
+unevaluatedProperties: false
examples:
- |
diff --git a/dts/upstream/Bindings/pinctrl/qcom,sm8250-pinctrl.yaml b/dts/upstream/Bindings/pinctrl/qcom,sm8250-pinctrl.yaml
index 021c547..b5d0434 100644
--- a/dts/upstream/Bindings/pinctrl/qcom,sm8250-pinctrl.yaml
+++ b/dts/upstream/Bindings/pinctrl/qcom,sm8250-pinctrl.yaml
@@ -28,13 +28,6 @@
interrupts:
maxItems: 1
- interrupt-controller: true
- "#interrupt-cells": true
- gpio-controller: true
- "#gpio-cells": true
- gpio-ranges: true
- wakeup-parent: true
-
gpio-reserved-ranges:
minItems: 1
maxItems: 90
@@ -106,7 +99,7 @@
- reg
- reg-names
-additionalProperties: false
+unevaluatedProperties: false
examples:
- |
diff --git a/dts/upstream/Bindings/pinctrl/qcom,sm8350-lpass-lpi-pinctrl.yaml b/dts/upstream/Bindings/pinctrl/qcom,sm8350-lpass-lpi-pinctrl.yaml
index 2e65ae0..9d782f9 100644
--- a/dts/upstream/Bindings/pinctrl/qcom,sm8350-lpass-lpi-pinctrl.yaml
+++ b/dts/upstream/Bindings/pinctrl/qcom,sm8350-lpass-lpi-pinctrl.yaml
@@ -33,16 +33,6 @@
- const: core
- const: audio
- gpio-controller: true
-
- "#gpio-cells":
- description: Specifying the pin number and flags, as defined in
- include/dt-bindings/gpio/gpio.h
- const: 2
-
- gpio-ranges:
- maxItems: 1
-
patternProperties:
"-state$":
oneOf:
@@ -58,7 +48,8 @@
description:
Pinctrl node's client devices use subnodes for desired pin configuration.
Client device subnodes use below standard properties.
- $ref: /schemas/pinctrl/pincfg-node.yaml
+ $ref: qcom,lpass-lpi-common.yaml#/$defs/qcom-tlmm-state
+ unevaluatedProperties: false
properties:
pins:
@@ -81,48 +72,16 @@
Specify the alternative function to be configured for the specified
pins.
- drive-strength:
- enum: [2, 4, 6, 8, 10, 12, 14, 16]
- default: 2
- description:
- Selects the drive strength for the specified pins, in mA.
-
- slew-rate:
- enum: [0, 1, 2, 3]
- default: 0
- description: |
- 0: No adjustments
- 1: Higher Slew rate (faster edges)
- 2: Lower Slew rate (slower edges)
- 3: Reserved (No adjustments)
-
- bias-bus-hold: true
- bias-pull-down: true
- bias-pull-up: true
- bias-disable: true
- input-enable: true
- output-high: true
- output-low: true
-
- required:
- - pins
- - function
-
- additionalProperties: false
-
allOf:
- - $ref: pinctrl.yaml#
+ - $ref: qcom,lpass-lpi-common.yaml#
required:
- compatible
- reg
- clocks
- clock-names
- - gpio-controller
- - "#gpio-cells"
- - gpio-ranges
-additionalProperties: false
+unevaluatedProperties: false
examples:
- |
diff --git a/dts/upstream/Bindings/pinctrl/qcom,sm8350-tlmm.yaml b/dts/upstream/Bindings/pinctrl/qcom,sm8350-tlmm.yaml
index 6e8f41f..ec5e096 100644
--- a/dts/upstream/Bindings/pinctrl/qcom,sm8350-tlmm.yaml
+++ b/dts/upstream/Bindings/pinctrl/qcom,sm8350-tlmm.yaml
@@ -25,10 +25,6 @@
interrupts:
maxItems: 1
- interrupt-controller: true
- "#interrupt-cells": true
- gpio-controller: true
-
gpio-reserved-ranges:
minItems: 1
maxItems: 102
@@ -36,16 +32,6 @@
gpio-line-names:
maxItems: 203
- "#gpio-cells": true
- gpio-ranges: true
- wakeup-parent: true
-
-required:
- - compatible
- - reg
-
-additionalProperties: false
-
patternProperties:
"-state$":
oneOf:
@@ -108,6 +94,12 @@
required:
- pins
+required:
+ - compatible
+ - reg
+
+unevaluatedProperties: false
+
examples:
- |
#include <dt-bindings/interrupt-controller/arm-gic.h>
diff --git a/dts/upstream/Bindings/pinctrl/qcom,sm8450-lpass-lpi-pinctrl.yaml b/dts/upstream/Bindings/pinctrl/qcom,sm8450-lpass-lpi-pinctrl.yaml
index 1eefa9a..e756559 100644
--- a/dts/upstream/Bindings/pinctrl/qcom,sm8450-lpass-lpi-pinctrl.yaml
+++ b/dts/upstream/Bindings/pinctrl/qcom,sm8450-lpass-lpi-pinctrl.yaml
@@ -32,16 +32,6 @@
- const: core
- const: audio
- gpio-controller: true
-
- "#gpio-cells":
- description: Specifying the pin number and flags, as defined in
- include/dt-bindings/gpio/gpio.h
- const: 2
-
- gpio-ranges:
- maxItems: 1
-
patternProperties:
"-state$":
oneOf:
@@ -57,7 +47,8 @@
description:
Pinctrl node's client devices use subnodes for desired pin configuration.
Client device subnodes use below standard properties.
- $ref: /schemas/pinctrl/pincfg-node.yaml
+ $ref: qcom,lpass-lpi-common.yaml#/$defs/qcom-tlmm-state
+ unevaluatedProperties: false
properties:
pins:
@@ -81,48 +72,16 @@
Specify the alternative function to be configured for the specified
pins.
- drive-strength:
- enum: [2, 4, 6, 8, 10, 12, 14, 16]
- default: 2
- description:
- Selects the drive strength for the specified pins, in mA.
-
- slew-rate:
- enum: [0, 1, 2, 3]
- default: 0
- description: |
- 0: No adjustments
- 1: Higher Slew rate (faster edges)
- 2: Lower Slew rate (slower edges)
- 3: Reserved (No adjustments)
-
- bias-bus-hold: true
- bias-pull-down: true
- bias-pull-up: true
- bias-disable: true
- input-enable: true
- output-high: true
- output-low: true
-
- required:
- - pins
- - function
-
- additionalProperties: false
-
allOf:
- - $ref: pinctrl.yaml#
+ - $ref: qcom,lpass-lpi-common.yaml#
required:
- compatible
- reg
- clocks
- clock-names
- - gpio-controller
- - "#gpio-cells"
- - gpio-ranges
-additionalProperties: false
+unevaluatedProperties: false
examples:
- |
diff --git a/dts/upstream/Bindings/pinctrl/qcom,sm8450-tlmm.yaml b/dts/upstream/Bindings/pinctrl/qcom,sm8450-tlmm.yaml
index 5163fe3..16fd2c5 100644
--- a/dts/upstream/Bindings/pinctrl/qcom,sm8450-tlmm.yaml
+++ b/dts/upstream/Bindings/pinctrl/qcom,sm8450-tlmm.yaml
@@ -25,10 +25,6 @@
interrupts:
maxItems: 1
- interrupt-controller: true
- "#interrupt-cells": true
- gpio-controller: true
-
gpio-reserved-ranges:
minItems: 1
maxItems: 105
@@ -36,16 +32,6 @@
gpio-line-names:
maxItems: 210
- "#gpio-cells": true
- gpio-ranges: true
- wakeup-parent: true
-
-required:
- - compatible
- - reg
-
-additionalProperties: false
-
patternProperties:
"-state$":
oneOf:
@@ -107,6 +93,12 @@
required:
- pins
+required:
+ - compatible
+ - reg
+
+unevaluatedProperties: false
+
examples:
- |
#include <dt-bindings/interrupt-controller/arm-gic.h>
diff --git a/dts/upstream/Bindings/pinctrl/qcom,sm8550-lpass-lpi-pinctrl.yaml b/dts/upstream/Bindings/pinctrl/qcom,sm8550-lpass-lpi-pinctrl.yaml
index ef97432..bf4a72f 100644
--- a/dts/upstream/Bindings/pinctrl/qcom,sm8550-lpass-lpi-pinctrl.yaml
+++ b/dts/upstream/Bindings/pinctrl/qcom,sm8550-lpass-lpi-pinctrl.yaml
@@ -16,7 +16,11 @@
properties:
compatible:
- const: qcom,sm8550-lpass-lpi-pinctrl
+ oneOf:
+ - const: qcom,sm8550-lpass-lpi-pinctrl
+ - items:
+ - const: qcom,x1e80100-lpass-lpi-pinctrl
+ - const: qcom,sm8550-lpass-lpi-pinctrl
reg:
items:
@@ -33,16 +37,6 @@
- const: core
- const: audio
- gpio-controller: true
-
- "#gpio-cells":
- description: Specifying the pin number and flags, as defined in
- include/dt-bindings/gpio/gpio.h
- const: 2
-
- gpio-ranges:
- maxItems: 1
-
patternProperties:
"-state$":
oneOf:
@@ -58,7 +52,8 @@
description:
Pinctrl node's client devices use subnodes for desired pin configuration.
Client device subnodes use below standard properties.
- $ref: /schemas/pinctrl/pincfg-node.yaml
+ $ref: qcom,lpass-lpi-common.yaml#/$defs/qcom-tlmm-state
+ unevaluatedProperties: false
properties:
pins:
@@ -81,48 +76,16 @@
Specify the alternative function to be configured for the specified
pins.
- drive-strength:
- enum: [2, 4, 6, 8, 10, 12, 14, 16]
- default: 2
- description:
- Selects the drive strength for the specified pins, in mA.
-
- slew-rate:
- enum: [0, 1, 2, 3]
- default: 0
- description: |
- 0: No adjustments
- 1: Higher Slew rate (faster edges)
- 2: Lower Slew rate (slower edges)
- 3: Reserved (No adjustments)
-
- bias-bus-hold: true
- bias-pull-down: true
- bias-pull-up: true
- bias-disable: true
- input-enable: true
- output-high: true
- output-low: true
-
- required:
- - pins
- - function
-
- additionalProperties: false
-
allOf:
- - $ref: pinctrl.yaml#
+ - $ref: qcom,lpass-lpi-common.yaml#
required:
- compatible
- reg
- clocks
- clock-names
- - gpio-controller
- - "#gpio-cells"
- - gpio-ranges
-additionalProperties: false
+unevaluatedProperties: false
examples:
- |
diff --git a/dts/upstream/Bindings/pinctrl/qcom,sm8550-tlmm.yaml b/dts/upstream/Bindings/pinctrl/qcom,sm8550-tlmm.yaml
index f789c77..c2ae79d 100644
--- a/dts/upstream/Bindings/pinctrl/qcom,sm8550-tlmm.yaml
+++ b/dts/upstream/Bindings/pinctrl/qcom,sm8550-tlmm.yaml
@@ -22,10 +22,8 @@
reg:
maxItems: 1
- interrupts: true
- interrupt-controller: true
- "#interrupt-cells": true
- gpio-controller: true
+ interrupts:
+ maxItems: 1
gpio-reserved-ranges:
minItems: 1
@@ -34,10 +32,6 @@
gpio-line-names:
maxItems: 210
- "#gpio-cells": true
- gpio-ranges: true
- wakeup-parent: true
-
patternProperties:
"-state$":
oneOf:
@@ -117,7 +111,7 @@
- compatible
- reg
-additionalProperties: false
+unevaluatedProperties: false
examples:
- |
diff --git a/dts/upstream/Bindings/pinctrl/qcom,sm8650-lpass-lpi-pinctrl.yaml b/dts/upstream/Bindings/pinctrl/qcom,sm8650-lpass-lpi-pinctrl.yaml
new file mode 100644
index 0000000..db72143
--- /dev/null
+++ b/dts/upstream/Bindings/pinctrl/qcom,sm8650-lpass-lpi-pinctrl.yaml
@@ -0,0 +1,107 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/pinctrl/qcom,sm8650-lpass-lpi-pinctrl.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Qualcomm SM8650 SoC LPASS LPI TLMM
+
+maintainers:
+ - Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
+ - Srinivas Kandagatla <srinivas.kandagatla@linaro.org>
+
+description:
+ Top Level Mode Multiplexer pin controller in the Low Power Audio SubSystem
+ (LPASS) Low Power Island (LPI) of Qualcomm SM8650 SoC.
+
+properties:
+ compatible:
+ const: qcom,sm8650-lpass-lpi-pinctrl
+
+ reg:
+ items:
+ - description: LPASS LPI TLMM Control and Status registers
+
+ clocks:
+ items:
+ - description: LPASS Core voting clock
+ - description: LPASS Audio voting clock
+
+ clock-names:
+ items:
+ - const: core
+ - const: audio
+
+patternProperties:
+ "-state$":
+ oneOf:
+ - $ref: "#/$defs/qcom-sm8650-lpass-state"
+ - patternProperties:
+ "-pins$":
+ $ref: "#/$defs/qcom-sm8650-lpass-state"
+ additionalProperties: false
+
+$defs:
+ qcom-sm8650-lpass-state:
+ type: object
+ description:
+ Pinctrl node's client devices use subnodes for desired pin configuration.
+ Client device subnodes use below standard properties.
+ $ref: qcom,lpass-lpi-common.yaml#/$defs/qcom-tlmm-state
+ unevaluatedProperties: false
+
+ properties:
+ pins:
+ description:
+ List of gpio pins affected by the properties specified in this
+ subnode.
+ items:
+ pattern: "^gpio([0-9]|1[0-9]|2[0-2])$"
+
+ function:
+ enum: [ dmic1_clk, dmic1_data, dmic2_clk, dmic2_data, dmic3_clk,
+ dmic3_data, dmic4_clk, dmic4_data, ext_mclk1_a, ext_mclk1_b,
+ ext_mclk1_c, ext_mclk1_d, ext_mclk1_e, gpio, i2s0_clk,
+ i2s0_data, i2s0_ws, i2s1_clk, i2s1_data, i2s1_ws, i2s2_clk,
+ i2s2_data, i2s2_ws, i2s3_clk, i2s3_data, i2s3_ws, i2s4_clk,
+ i2s4_data, i2s4_ws, qca_swr_clk, qca_swr_data, slimbus_clk,
+ slimbus_data, swr_rx_clk, swr_rx_data, swr_tx_clk, swr_tx_data,
+ wsa_swr_clk, wsa_swr_data, wsa2_swr_clk, wsa2_swr_data ]
+ description:
+ Specify the alternative function to be configured for the specified
+ pins.
+
+allOf:
+ - $ref: qcom,lpass-lpi-common.yaml#
+
+required:
+ - compatible
+ - reg
+ - clocks
+ - clock-names
+
+unevaluatedProperties: false
+
+examples:
+ - |
+ #include <dt-bindings/sound/qcom,q6dsp-lpass-ports.h>
+
+ lpass_tlmm: pinctrl@6e80000 {
+ compatible = "qcom,sm8650-lpass-lpi-pinctrl";
+ reg = <0x06e80000 0x20000>;
+
+ clocks = <&q6prmcc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
+ <&q6prmcc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>;
+ clock-names = "core", "audio";
+
+ gpio-controller;
+ #gpio-cells = <2>;
+ gpio-ranges = <&lpass_tlmm 0 0 23>;
+
+ tx-swr-sleep-clk-state {
+ pins = "gpio0";
+ function = "swr_tx_clk";
+ drive-strength = <2>;
+ bias-pull-down;
+ };
+ };
diff --git a/dts/upstream/Bindings/pinctrl/qcom,sm8650-tlmm.yaml b/dts/upstream/Bindings/pinctrl/qcom,sm8650-tlmm.yaml
new file mode 100644
index 0000000..c0a06ab
--- /dev/null
+++ b/dts/upstream/Bindings/pinctrl/qcom,sm8650-tlmm.yaml
@@ -0,0 +1,141 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/pinctrl/qcom,sm8650-tlmm.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Qualcomm Technologies, Inc. SM8650 TLMM block
+
+maintainers:
+ - Bjorn Andersson <andersson@kernel.org>
+
+description:
+ Top Level Mode Multiplexer pin controller in Qualcomm SM8650 SoC.
+
+allOf:
+ - $ref: /schemas/pinctrl/qcom,tlmm-common.yaml#
+
+properties:
+ compatible:
+ const: qcom,sm8650-tlmm
+
+ reg:
+ maxItems: 1
+
+ interrupts:
+ maxItems: 1
+
+ gpio-reserved-ranges:
+ minItems: 1
+ maxItems: 105
+
+ gpio-line-names:
+ maxItems: 210
+
+patternProperties:
+ "-state$":
+ oneOf:
+ - $ref: "#/$defs/qcom-sm8650-tlmm-state"
+ - patternProperties:
+ "-pins$":
+ $ref: "#/$defs/qcom-sm8650-tlmm-state"
+ additionalProperties: false
+
+$defs:
+ qcom-sm8650-tlmm-state:
+ type: object
+ description:
+ Pinctrl node's client devices use subnodes for desired pin configuration.
+ Client device subnodes use below standard properties.
+ $ref: qcom,tlmm-common.yaml#/$defs/qcom-tlmm-state
+ unevaluatedProperties: false
+
+ properties:
+ pins:
+ description:
+ List of gpio pins affected by the properties specified in this
+ subnode.
+ items:
+ oneOf:
+ - pattern: "^gpio([0-9]|[1-9][0-9]|1[0-9][0-9]|20[0-9])$"
+ - enum: [ ufs_reset, sdc2_clk, sdc2_cmd, sdc2_data ]
+ minItems: 1
+ maxItems: 36
+
+ function:
+ description:
+ Specify the alternative function to be configured for the specified
+ pins.
+ enum: [ gpio, aoss_cti, atest_char, atest_usb, audio_ext_mclk0,
+ audio_ext_mclk1, audio_ref_clk, cam_aon_mclk2, cam_aon_mclk4,
+ cam_mclk, cci_async_in, cci_i2c_scl, cci_i2c_sda, cci_timer,
+ cmu_rng, coex_uart1_rx, coex_uart1_tx, coex_uart2_rx,
+ coex_uart2_tx, cri_trng, dbg_out_clk, ddr_bist_complete,
+ ddr_bist_fail, ddr_bist_start, ddr_bist_stop, ddr_pxi0,
+ ddr_pxi1, ddr_pxi2, ddr_pxi3, do_not, dp_hot, gcc_gp1,
+ gcc_gp2, gcc_gp3, gnss_adc0, gnss_adc1, i2chub0_se0,
+ i2chub0_se1, i2chub0_se2, i2chub0_se3, i2chub0_se4,
+ i2chub0_se5, i2chub0_se6, i2chub0_se7, i2chub0_se8,
+ i2chub0_se9, i2s0_data0, i2s0_data1, i2s0_sck, i2s0_ws,
+ i2s1_data0, i2s1_data1, i2s1_sck, i2s1_ws, ibi_i3c,
+ jitter_bist, mdp_vsync, mdp_vsync0_out, mdp_vsync1_out,
+ mdp_vsync2_out, mdp_vsync3_out, mdp_vsync_e, nav_gpio0,
+ nav_gpio1, nav_gpio2, nav_gpio3, pcie0_clk_req_n,
+ pcie1_clk_req_n, phase_flag, pll_bist_sync, pll_clk_aux,
+ prng_rosc0, prng_rosc1, prng_rosc2, prng_rosc3, qdss_cti,
+ qdss_gpio, qlink_big_enable, qlink_big_request,
+ qlink_little_enable, qlink_little_request, qlink_wmss,
+ qspi0, qspi1, qspi2, qspi3, qspi_clk, qspi_cs, qup1_se0,
+ qup1_se1, qup1_se2, qup1_se3, qup1_se4, qup1_se5, qup1_se6,
+ qup1_se7, qup2_se0, qup2_se1, qup2_se2, qup2_se3, qup2_se4,
+ qup2_se5, qup2_se6, qup2_se7, sd_write_protect, sdc40, sdc41,
+ sdc42, sdc43, sdc4_clk, sdc4_cmd, tb_trig_sdc2, tb_trig_sdc4,
+ tgu_ch0_trigout, tgu_ch1_trigout, tgu_ch2_trigout,
+ tgu_ch3_trigout, tmess_prng0, tmess_prng1, tmess_prng2,
+ tmess_prng3, tsense_pwm1, tsense_pwm2, tsense_pwm3, uim0_clk,
+ uim0_data, uim0_present, uim0_reset, uim1_clk, uim1_data,
+ uim1_present, uim1_reset, usb1_hs, usb_phy, vfr_0, vfr_1,
+ vsense_trigger_mirnat ]
+
+ required:
+ - pins
+
+required:
+ - compatible
+ - reg
+
+unevaluatedProperties: false
+
+examples:
+ - |
+ #include <dt-bindings/interrupt-controller/arm-gic.h>
+ tlmm: pinctrl@f100000 {
+ compatible = "qcom,sm8650-tlmm";
+ reg = <0x0f100000 0x300000>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ gpio-ranges = <&tlmm 0 0 211>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>;
+
+ gpio-wo-state {
+ pins = "gpio1";
+ function = "gpio";
+ };
+
+ uart-w-state {
+ rx-pins {
+ pins = "gpio60";
+ function = "qup1_se7";
+ bias-pull-up;
+ };
+
+ tx-pins {
+ pins = "gpio61";
+ function = "qup1_se7";
+ bias-disable;
+ };
+ };
+ };
+...
diff --git a/dts/upstream/Bindings/pinctrl/qcom,x1e80100-tlmm.yaml b/dts/upstream/Bindings/pinctrl/qcom,x1e80100-tlmm.yaml
new file mode 100644
index 0000000..a1333e0
--- /dev/null
+++ b/dts/upstream/Bindings/pinctrl/qcom,x1e80100-tlmm.yaml
@@ -0,0 +1,137 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/pinctrl/qcom,x1e80100-tlmm.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Qualcomm Technologies, Inc. X1E80100 TLMM block
+
+maintainers:
+ - Rajendra Nayak <quic_rjendra@quicinc.com>
+
+description:
+ Top Level Mode Multiplexer pin controller in Qualcomm X1E80100 SoC.
+
+allOf:
+ - $ref: /schemas/pinctrl/qcom,tlmm-common.yaml#
+
+properties:
+ compatible:
+ const: qcom,x1e80100-tlmm
+
+ reg:
+ maxItems: 1
+
+ interrupts:
+ maxItems: 1
+
+ gpio-reserved-ranges:
+ minItems: 1
+ maxItems: 119
+
+ gpio-line-names:
+ maxItems: 238
+
+patternProperties:
+ "-state$":
+ oneOf:
+ - $ref: "#/$defs/qcom-x1e80100-tlmm-state"
+ - patternProperties:
+ "-pins$":
+ $ref: "#/$defs/qcom-x1e80100-tlmm-state"
+ additionalProperties: false
+
+$defs:
+ qcom-x1e80100-tlmm-state:
+ type: object
+ description:
+ Pinctrl node's client devices use subnodes for desired pin configuration.
+ Client device subnodes use below standard properties.
+ $ref: qcom,tlmm-common.yaml#/$defs/qcom-tlmm-state
+ unevaluatedProperties: false
+
+ properties:
+ pins:
+ description:
+ List of gpio pins affected by the properties specified in this
+ subnode.
+ items:
+ oneOf:
+ - pattern: "^gpio([0-9]|[1-9][0-9]|1[0-9][0-9]|2[0-2][0-9]|23[0-7])$"
+ - enum: [ ufs_reset, sdc2_clk, sdc2_cmd, sdc2_data ]
+ minItems: 1
+ maxItems: 36
+
+ function:
+ description:
+ Specify the alternative function to be configured for the specified
+ pins.
+ enum: [ aon_cci, aoss_cti, atest_char, atest_char0,
+ atest_char1, atest_char2, atest_char3, atest_usb,
+ audio_ext, audio_ref, cam_aon, cam_mclk, cci_async,
+ cci_i2c, cci_timer0, cci_timer1, cci_timer2, cci_timer3,
+ cci_timer4, cmu_rng0, cmu_rng1, cmu_rng2, cmu_rng3,
+ cri_trng, dbg_out, ddr_bist, ddr_pxi0, ddr_pxi1,
+ ddr_pxi2, ddr_pxi3, ddr_pxi4, ddr_pxi5, ddr_pxi6, ddr_pxi7,
+ edp0_hot, edp0_lcd, edp1_hot, edp1_lcd, eusb0_ac, eusb1_ac,
+ eusb2_ac, eusb3_ac, eusb5_ac, eusb6_ac, gcc_gp1, gcc_gp2,
+ gcc_gp3, gpio, i2s0_data0, i2s0_data1, i2s0_sck, i2s0_ws, i2s1_data0,
+ i2s1_data1, i2s1_sck, i2s1_ws, ibi_i3c, jitter_bist, mdp_vsync0,
+ mdp_vsync1, mdp_vsync2, mdp_vsync3, mdp_vsync4, mdp_vsync5,
+ mdp_vsync6, mdp_vsync7, mdp_vsync8, pcie3_clk, pcie4_clk,
+ pcie5_clk, pcie6a_clk, pcie6b_clk, phase_flag, pll_bist, pll_clk,
+ prng_rosc0, prng_rosc1, prng_rosc2, prng_rosc3, qdss_cti,
+ qdss_gpio, qspi00, qspi01, qspi02, qspi03, qspi0_clk, qspi0_cs0,
+ qspi0_cs1, qup0_se0, qup0_se1, qup0_se2, qup0_se3, qup0_se4,
+ qup0_se5, qup0_se6, qup0_se7, qup1_se0, qup1_se1, qup1_se2, qup1_se3,
+ qup1_se4, qup1_se5, qup1_se6, qup1_se7, qup2_se0, qup2_se1, qup2_se2,
+ qup2_se3, qup2_se4, qup2_se5, qup2_se6, qup2_se7, sd_write, sdc4_clk,
+ sdc4_cmd, sdc4_data0, sdc4_data1, sdc4_data2, sdc4_data3, sys_throttle,
+ tb_trig, tgu_ch0, tgu_ch1, tgu_ch2, tgu_ch3, tgu_ch4, tgu_ch5,
+ tgu_ch6, tgu_ch7, tmess_prng0, tmess_prng1, tmess_prng2, tmess_prng3,
+ tsense_pwm1, tsense_pwm2, sense_pwm3, tsense_pwm4, usb0_dp, usb0_phy,
+ usb0_sbrx, usb0_sbtx, usb1_dp, usb1_phy, usb1_sbrx, usb1_sbtx,
+ usb2_dp, usb2_phy, usb2_sbrx, usb2_sbtx, vsense_trigger ]
+
+ required:
+ - pins
+
+required:
+ - compatible
+ - reg
+
+unevaluatedProperties: false
+
+examples:
+ - |
+ #include <dt-bindings/interrupt-controller/arm-gic.h>
+ tlmm: pinctrl@f100000 {
+ compatible = "qcom,x1e80100-tlmm";
+ reg = <0x0f100000 0xf00000>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ gpio-ranges = <&tlmm 0 0 239>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>;
+
+ gpio-wo-state {
+ pins = "gpio1";
+ function = "gpio";
+ };
+
+ uart-w-state {
+ rx-pins {
+ pins = "gpio26";
+ function = "qup2_se7";
+ bias-pull-up;
+ };
+
+ tx-pins {
+ pins = "gpio27";
+ function = "qup2_se7";
+ bias-disable;
+ };
+ };
+ };
+...
diff --git a/dts/upstream/Bindings/pinctrl/renesas,rza2-pinctrl.yaml b/dts/upstream/Bindings/pinctrl/renesas,rza2-pinctrl.yaml
index 8271e7b..8b8e4e1 100644
--- a/dts/upstream/Bindings/pinctrl/renesas,rza2-pinctrl.yaml
+++ b/dts/upstream/Bindings/pinctrl/renesas,rza2-pinctrl.yaml
@@ -20,7 +20,7 @@
properties:
compatible:
- const: "renesas,r7s9210-pinctrl" # RZ/A2M
+ const: renesas,r7s9210-pinctrl # RZ/A2M
reg:
maxItems: 1
diff --git a/dts/upstream/Bindings/pinctrl/renesas,rzg2l-pinctrl.yaml b/dts/upstream/Bindings/pinctrl/renesas,rzg2l-pinctrl.yaml
index b5ca40d..d476de8 100644
--- a/dts/upstream/Bindings/pinctrl/renesas,rzg2l-pinctrl.yaml
+++ b/dts/upstream/Bindings/pinctrl/renesas,rzg2l-pinctrl.yaml
@@ -185,17 +185,17 @@
sd1_mux {
pinmux = <RZG2L_PORT_PINMUX(19, 0, 1)>, /* CD */
<RZG2L_PORT_PINMUX(19, 1, 1)>; /* WP */
- power-source = <3300>;
+ power-source = <3300>;
};
sd1_data {
pins = "SD1_DATA0", "SD1_DATA1", "SD1_DATA2", "SD1_DATA3";
- power-source = <3300>;
+ power-source = <3300>;
};
sd1_ctrl {
pins = "SD1_CLK", "SD1_CMD";
- power-source = <3300>;
+ power-source = <3300>;
};
};
};
diff --git a/dts/upstream/Bindings/pinctrl/samsung,pinctrl-wakeup-interrupt.yaml b/dts/upstream/Bindings/pinctrl/samsung,pinctrl-wakeup-interrupt.yaml
index 1de91a5..4dfb49b 100644
--- a/dts/upstream/Bindings/pinctrl/samsung,pinctrl-wakeup-interrupt.yaml
+++ b/dts/upstream/Bindings/pinctrl/samsung,pinctrl-wakeup-interrupt.yaml
@@ -28,15 +28,27 @@
properties:
compatible:
- enum:
- - samsung,s3c2410-wakeup-eint
- - samsung,s3c2412-wakeup-eint
- - samsung,s3c64xx-wakeup-eint
- - samsung,s5pv210-wakeup-eint
- - samsung,exynos4210-wakeup-eint
- - samsung,exynos7-wakeup-eint
- - samsung,exynos850-wakeup-eint
- - samsung,exynosautov9-wakeup-eint
+ oneOf:
+ - enum:
+ - samsung,s3c2410-wakeup-eint
+ - samsung,s3c2412-wakeup-eint
+ - samsung,s3c64xx-wakeup-eint
+ - samsung,s5pv210-wakeup-eint
+ - samsung,exynos4210-wakeup-eint
+ - samsung,exynos7-wakeup-eint
+ - samsung,exynosautov920-wakeup-eint
+ - items:
+ - enum:
+ - samsung,exynos5433-wakeup-eint
+ - samsung,exynos7885-wakeup-eint
+ - samsung,exynos850-wakeup-eint
+ - const: samsung,exynos7-wakeup-eint
+ - items:
+ - enum:
+ - google,gs101-wakeup-eint
+ - samsung,exynosautov9-wakeup-eint
+ - const: samsung,exynos850-wakeup-eint
+ - const: samsung,exynos7-wakeup-eint
interrupts:
description:
@@ -79,11 +91,14 @@
- if:
properties:
compatible:
- contains:
- enum:
- - samsung,s5pv210-wakeup-eint
- - samsung,exynos4210-wakeup-eint
- - samsung,exynos7-wakeup-eint
+ # Match without "contains", to skip newer variants which are still
+ # compatible with samsung,exynos7-wakeup-eint
+ enum:
+ - samsung,s5pv210-wakeup-eint
+ - samsung,exynos4210-wakeup-eint
+ - samsung,exynos5433-wakeup-eint
+ - samsung,exynos7-wakeup-eint
+ - samsung,exynos7885-wakeup-eint
then:
properties:
interrupts:
@@ -98,7 +113,7 @@
contains:
enum:
- samsung,exynos850-wakeup-eint
- - samsung,exynosautov9-wakeup-eint
+ - samsung,exynosautov920-wakeup-eint
then:
properties:
interrupts: false
diff --git a/dts/upstream/Bindings/pinctrl/samsung,pinctrl.yaml b/dts/upstream/Bindings/pinctrl/samsung,pinctrl.yaml
index 2661462..118549c 100644
--- a/dts/upstream/Bindings/pinctrl/samsung,pinctrl.yaml
+++ b/dts/upstream/Bindings/pinctrl/samsung,pinctrl.yaml
@@ -35,6 +35,7 @@
compatible:
enum:
+ - google,gs101-pinctrl
- samsung,s3c2412-pinctrl
- samsung,s3c2416-pinctrl
- samsung,s3c2440-pinctrl
@@ -53,6 +54,7 @@
- samsung,exynos7885-pinctrl
- samsung,exynos850-pinctrl
- samsung,exynosautov9-pinctrl
+ - samsung,exynosautov920-pinctrl
- tesla,fsd-pinctrl
interrupts:
@@ -313,7 +315,8 @@
pinctrl-0 = <&initial_alive>;
wakeup-interrupt-controller {
- compatible = "samsung,exynos7-wakeup-eint";
+ compatible = "samsung,exynos5433-wakeup-eint",
+ "samsung,exynos7-wakeup-eint";
interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
};
diff --git a/dts/upstream/Bindings/pinctrl/xlnx,zynq-pinctrl.yaml b/dts/upstream/Bindings/pinctrl/xlnx,zynq-pinctrl.yaml
index b85f9e3..d2676f9 100644
--- a/dts/upstream/Bindings/pinctrl/xlnx,zynq-pinctrl.yaml
+++ b/dts/upstream/Bindings/pinctrl/xlnx,zynq-pinctrl.yaml
@@ -39,7 +39,7 @@
phandle to the SLCR.
patternProperties:
- '^(.*-)?(default|gpio)$':
+ '^(.*-)?(default|gpio-grp)$':
type: object
patternProperties:
'^mux':
diff --git a/dts/upstream/Bindings/pinctrl/xlnx,zynqmp-pinctrl.yaml b/dts/upstream/Bindings/pinctrl/xlnx,zynqmp-pinctrl.yaml
index 01b6f2b..f13d315 100644
--- a/dts/upstream/Bindings/pinctrl/xlnx,zynqmp-pinctrl.yaml
+++ b/dts/upstream/Bindings/pinctrl/xlnx,zynqmp-pinctrl.yaml
@@ -31,7 +31,7 @@
const: xlnx,zynqmp-pinctrl
patternProperties:
- '^(.*-)?(default|gpio)$':
+ '^(.*-)?(default|gpio-grp)$':
type: object
patternProperties:
'^mux':
diff --git a/dts/upstream/Bindings/power/fsl,scu-pd.yaml b/dts/upstream/Bindings/power/fsl,scu-pd.yaml
index 407b7cf..7a0f1a4 100644
--- a/dts/upstream/Bindings/power/fsl,scu-pd.yaml
+++ b/dts/upstream/Bindings/power/fsl,scu-pd.yaml
@@ -20,6 +20,7 @@
compatible:
items:
- enum:
+ - fsl,imx8dl-scu-pd
- fsl,imx8qm-scu-pd
- fsl,imx8qxp-scu-pd
- const: fsl,scu-pd
diff --git a/dts/upstream/Bindings/power/qcom,rpmpd.yaml b/dts/upstream/Bindings/power/qcom,rpmpd.yaml
index da9c584..2ff246c 100644
--- a/dts/upstream/Bindings/power/qcom,rpmpd.yaml
+++ b/dts/upstream/Bindings/power/qcom,rpmpd.yaml
@@ -39,7 +39,6 @@
- qcom,sc7280-rpmhpd
- qcom,sc8180x-rpmhpd
- qcom,sc8280xp-rpmhpd
- - qcom,sc8380xp-rpmhpd
- qcom,sdm660-rpmpd
- qcom,sdm670-rpmhpd
- qcom,sdm845-rpmhpd
@@ -57,6 +56,7 @@
- qcom,sm8450-rpmhpd
- qcom,sm8550-rpmhpd
- qcom,sm8650-rpmhpd
+ - qcom,x1e80100-rpmhpd
- items:
- enum:
- qcom,msm8937-rpmpd
diff --git a/dts/upstream/Bindings/power/reset/nvmem-reboot-mode.yaml b/dts/upstream/Bindings/power/reset/nvmem-reboot-mode.yaml
index 14a262b..627f8a6 100644
--- a/dts/upstream/Bindings/power/reset/nvmem-reboot-mode.yaml
+++ b/dts/upstream/Bindings/power/reset/nvmem-reboot-mode.yaml
@@ -28,17 +28,15 @@
items:
- const: reboot-mode
-patternProperties:
- "^mode-.+":
- $ref: /schemas/types.yaml#/definitions/uint32
- description: Vendor-specific mode value written to the mode register
+allOf:
+ - $ref: reboot-mode.yaml#
required:
- compatible
- nvmem-cells
- nvmem-cell-names
-additionalProperties: false
+unevaluatedProperties: false
examples:
- |
diff --git a/dts/upstream/Bindings/power/reset/qcom,pon.yaml b/dts/upstream/Bindings/power/reset/qcom,pon.yaml
index 5e46012..fc8105a 100644
--- a/dts/upstream/Bindings/power/reset/qcom,pon.yaml
+++ b/dts/upstream/Bindings/power/reset/qcom,pon.yaml
@@ -111,21 +111,24 @@
#include <dt-bindings/interrupt-controller/irq.h>
#include <dt-bindings/input/linux-event-codes.h>
#include <dt-bindings/spmi/spmi.h>
- spmi_bus: spmi@c440000 {
+
+ spmi@c440000 {
reg = <0x0c440000 0x1100>;
#address-cells = <2>;
#size-cells = <0>;
- pmk8350: pmic@0 {
+
+ pmic@0 {
reg = <0x0 SPMI_USID>;
#address-cells = <1>;
#size-cells = <0>;
- pmk8350_pon: pon_hlos@1300 {
- reg = <0x1300>;
+
+ pon@800 {
compatible = "qcom,pm8998-pon";
+ reg = <0x800>;
pwrkey {
compatible = "qcom,pm8941-pwrkey";
- interrupts = < 0x0 0x8 0 IRQ_TYPE_EDGE_BOTH >;
+ interrupts = <0x0 0x8 0 IRQ_TYPE_EDGE_BOTH>;
debounce = <15625>;
bias-pull-up;
linux,code = <KEY_POWER>;
diff --git a/dts/upstream/Bindings/power/reset/syscon-reboot-mode.yaml b/dts/upstream/Bindings/power/reset/syscon-reboot-mode.yaml
index 9b1ffce..b6acff1 100644
--- a/dts/upstream/Bindings/power/reset/syscon-reboot-mode.yaml
+++ b/dts/upstream/Bindings/power/reset/syscon-reboot-mode.yaml
@@ -29,12 +29,10 @@
$ref: /schemas/types.yaml#/definitions/uint32
description: Offset in the register map for the mode register (in bytes)
-patternProperties:
- "^mode-.+":
- $ref: /schemas/types.yaml#/definitions/uint32
- description: Vendor-specific mode value written to the mode register
+allOf:
+ - $ref: reboot-mode.yaml#
-additionalProperties: false
+unevaluatedProperties: false
required:
- compatible
diff --git a/dts/upstream/Bindings/power/reset/xlnx,zynqmp-power.yaml b/dts/upstream/Bindings/power/reset/xlnx,zynqmp-power.yaml
index 45792e2..7998316 100644
--- a/dts/upstream/Bindings/power/reset/xlnx,zynqmp-power.yaml
+++ b/dts/upstream/Bindings/power/reset/xlnx,zynqmp-power.yaml
@@ -57,7 +57,7 @@
firmware {
zynqmp-firmware {
- zynqmp-power {
+ power-management {
compatible = "xlnx,zynqmp-power";
interrupts = <0 35 4>;
};
@@ -70,7 +70,7 @@
firmware {
zynqmp-firmware {
- zynqmp-power {
+ power-management {
compatible = "xlnx,zynqmp-power";
interrupt-parent = <&gic>;
interrupts = <0 35 4>;
diff --git a/dts/upstream/Bindings/power/supply/bq24190.yaml b/dts/upstream/Bindings/power/supply/bq24190.yaml
index d3ebc9d..131b7e5 100644
--- a/dts/upstream/Bindings/power/supply/bq24190.yaml
+++ b/dts/upstream/Bindings/power/supply/bq24190.yaml
@@ -20,6 +20,7 @@
- ti,bq24192
- ti,bq24192i
- ti,bq24196
+ - ti,bq24296
reg:
maxItems: 1
diff --git a/dts/upstream/Bindings/power/supply/richtek,rt9455.yaml b/dts/upstream/Bindings/power/supply/richtek,rt9455.yaml
index 07e38be..89f9603 100644
--- a/dts/upstream/Bindings/power/supply/richtek,rt9455.yaml
+++ b/dts/upstream/Bindings/power/supply/richtek,rt9455.yaml
@@ -79,10 +79,10 @@
interrupt-parent = <&gpio1>;
interrupts = <0 IRQ_TYPE_LEVEL_LOW>;
- richtek,output-charge-current = <500000>;
- richtek,end-of-charge-percentage = <10>;
- richtek,battery-regulation-voltage = <4200000>;
- richtek,boost-output-voltage = <5050000>;
+ richtek,output-charge-current = <500000>;
+ richtek,end-of-charge-percentage = <10>;
+ richtek,battery-regulation-voltage = <4200000>;
+ richtek,boost-output-voltage = <5050000>;
richtek,min-input-voltage-regulation = <4500000>;
richtek,avg-input-current-regulation = <500000>;
diff --git a/dts/upstream/Bindings/power/wakeup-source.txt b/dts/upstream/Bindings/power/wakeup-source.txt
index 697333a..75bc20b 100644
--- a/dts/upstream/Bindings/power/wakeup-source.txt
+++ b/dts/upstream/Bindings/power/wakeup-source.txt
@@ -3,16 +3,20 @@
Any device nodes
----------------
-Nodes that describe devices which has wakeup capability must contain an
+Nodes that describe devices which have wakeup capability may contain a
"wakeup-source" boolean property.
-Also, if device is marked as a wakeup source, then all the primary
-interrupt(s) can be used as wakeup interrupt(s).
+If the device is marked as a wakeup-source, interrupt wake capability depends
+on the device specific "interrupt-names" property. If no interrupts are labeled
+as wake capable, then it is up to the device to determine which interrupts can
+wake the system.
+
+However if a device has a dedicated interrupt as the wakeup source, then it
+needs to specify/identify it using a device specific interrupt name. In such
+cases only that interrupt can be used as a wakeup interrupt.
-However if the devices have dedicated interrupt as the wakeup source
-then they need to specify/identify the same using device specific
-interrupt name. In such cases only that interrupt can be used as wakeup
-interrupt.
+While various legacy interrupt names exist, new devices should use "wakeup" as
+the canonical interrupt name.
List of legacy properties and respective binding document
---------------------------------------------------------
diff --git a/dts/upstream/Bindings/pwm/mediatek,pwm-disp.yaml b/dts/upstream/Bindings/pwm/mediatek,pwm-disp.yaml
index 153e146..afcdeed 100644
--- a/dts/upstream/Bindings/pwm/mediatek,pwm-disp.yaml
+++ b/dts/upstream/Bindings/pwm/mediatek,pwm-disp.yaml
@@ -8,7 +8,6 @@
maintainers:
- Jitao Shi <jitao.shi@mediatek.com>
- - Xinlei Lee <xinlei.lee@mediatek.com>
allOf:
- $ref: pwm.yaml#
diff --git a/dts/upstream/Bindings/pwm/pwm-omap-dmtimer.txt b/dts/upstream/Bindings/pwm/pwm-omap-dmtimer.txt
deleted file mode 100644
index 25ecfe1..0000000
--- a/dts/upstream/Bindings/pwm/pwm-omap-dmtimer.txt
+++ /dev/null
@@ -1,22 +0,0 @@
-* OMAP PWM for dual-mode timers
-
-Required properties:
-- compatible: Shall contain "ti,omap-dmtimer-pwm".
-- ti,timers: phandle to PWM capable OMAP timer. See timer/ti,timer-dm.yaml for info
- about these timers.
-- #pwm-cells: Should be 3. See pwm.yaml in this directory for a description of
- the cells format.
-
-Optional properties:
-- ti,prescaler: Should be a value between 0 and 7, see the timers datasheet
-- ti,clock-source: Set dmtimer parent clock, values between 0 and 2:
- - 0x00 - high-frequency system clock (timer_sys_ck)
- - 0x01 - 32-kHz always-on clock (timer_32k_ck)
- - 0x02 - external clock (timer_ext_ck, OMAP2 only)
-
-Example:
- pwm9: dmtimer-pwm@9 {
- compatible = "ti,omap-dmtimer-pwm";
- ti,timers = <&timer9>;
- #pwm-cells = <3>;
- };
diff --git a/dts/upstream/Bindings/pwm/pwm-samsung.yaml b/dts/upstream/Bindings/pwm/pwm-samsung.yaml
index 2162f66..17a2b92 100644
--- a/dts/upstream/Bindings/pwm/pwm-samsung.yaml
+++ b/dts/upstream/Bindings/pwm/pwm-samsung.yaml
@@ -29,7 +29,11 @@
- samsung,exynos4210-pwm # 32-bit, Exynos
- items:
- enum:
+ - samsung,exynos5433-pwm
+ - samsung,exynos7-pwm
- samsung,exynosautov9-pwm
+ - samsung,exynosautov920-pwm
+ - tesla,fsd-pwm
- const: samsung,exynos4210-pwm
reg:
diff --git a/dts/upstream/Bindings/pwm/ti,omap-dmtimer-pwm.yaml b/dts/upstream/Bindings/pwm/ti,omap-dmtimer-pwm.yaml
new file mode 100644
index 0000000..1e8e094
--- /dev/null
+++ b/dts/upstream/Bindings/pwm/ti,omap-dmtimer-pwm.yaml
@@ -0,0 +1,59 @@
+# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/pwm/ti,omap-dmtimer-pwm.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: TI dual mode timer PWM controller
+
+maintainers:
+ - Tony Lindgren <tony@atomide.com>
+
+description:
+ TI dual mode timer instances have an IO pin for PWM capability
+
+allOf:
+ - $ref: pwm.yaml#
+
+properties:
+ compatible:
+ const: ti,omap-dmtimer-pwm
+
+ "#pwm-cells":
+ const: 3
+
+ ti,timers:
+ description: Timer instance phandle for the PWM
+ $ref: /schemas/types.yaml#/definitions/phandle
+
+ ti,prescaler:
+ description: |
+ Legacy clock prescaler for timer. The timer counter is prescaled
+ with 2^n where n is the prescaler.
+ $ref: /schemas/types.yaml#/definitions/uint32
+ enum: [ 0, 1, 2, 3, 4, 5, 6, 7 ]
+ deprecated: true
+
+ ti,clock-source:
+ description: |
+ Legacy clock for timer, please use assigned-clocks instead.
+ 0x00 - high-frequency system clock (timer_sys_ck)
+ 0x01 - 32-kHz always-on clock (timer_32k_ck)
+ 0x02 - external clock (timer_ext_ck, OMAP2 only)
+ $ref: /schemas/types.yaml#/definitions/uint32
+ enum: [ 0, 1, 2 ]
+ deprecated: true
+
+required:
+ - compatible
+ - ti,timers
+
+unevaluatedProperties: false
+
+examples:
+ - |
+ pwm9: pwm {
+ compatible = "ti,omap-dmtimer-pwm";
+ ti,timers = <&timer9>;
+ #pwm-cells = <3>;
+ };
diff --git a/dts/upstream/Bindings/regulator/fixed-regulator.yaml b/dts/upstream/Bindings/regulator/fixed-regulator.yaml
index ce7751b..9ff9abf 100644
--- a/dts/upstream/Bindings/regulator/fixed-regulator.yaml
+++ b/dts/upstream/Bindings/regulator/fixed-regulator.yaml
@@ -105,6 +105,8 @@
description:
Interrupt signaling a critical under-voltage event.
+ system-critical-regulator: true
+
required:
- compatible
- regulator-name
diff --git a/dts/upstream/Bindings/regulator/mps,mp5416.yaml b/dts/upstream/Bindings/regulator/mps,mp5416.yaml
index 0221397..f825ee9 100644
--- a/dts/upstream/Bindings/regulator/mps,mp5416.yaml
+++ b/dts/upstream/Bindings/regulator/mps,mp5416.yaml
@@ -62,8 +62,8 @@
regulator-name = "buck1";
regulator-min-microvolt = <600000>;
regulator-max-microvolt = <2187500>;
- regulator-min-microamp = <3800000>;
- regulator-max-microamp = <6800000>;
+ regulator-min-microamp = <3800000>;
+ regulator-max-microamp = <6800000>;
regulator-boot-on;
};
diff --git a/dts/upstream/Bindings/regulator/mps,mpq7920.yaml b/dts/upstream/Bindings/regulator/mps,mpq7920.yaml
index 6de5b02..0d34af9 100644
--- a/dts/upstream/Bindings/regulator/mps,mpq7920.yaml
+++ b/dts/upstream/Bindings/regulator/mps,mpq7920.yaml
@@ -98,8 +98,8 @@
regulator-name = "buck1";
regulator-min-microvolt = <400000>;
regulator-max-microvolt = <3587500>;
- regulator-min-microamp = <460000>;
- regulator-max-microamp = <7600000>;
+ regulator-min-microamp = <460000>;
+ regulator-max-microamp = <7600000>;
regulator-boot-on;
mps,buck-ovp-disable;
mps,buck-phase-delay = /bits/ 8 <2>;
diff --git a/dts/upstream/Bindings/regulator/qcom,rpmh-regulator.yaml b/dts/upstream/Bindings/regulator/qcom,rpmh-regulator.yaml
index acd37f2..27c6d51 100644
--- a/dts/upstream/Bindings/regulator/qcom,rpmh-regulator.yaml
+++ b/dts/upstream/Bindings/regulator/qcom,rpmh-regulator.yaml
@@ -42,6 +42,7 @@
For PM7325, smps1 - smps8, ldo1 - ldo19
For PM8005, smps1 - smps4
For PM8009, smps1 - smps2, ldo1 - ldo7
+ For PM8010, ldo1 - ldo7
For PM8150, smps1 - smps10, ldo1 - ldo18
For PM8150L, smps1 - smps8, ldo1 - ldo11, bob, flash, rgb
For PM8350, smps1 - smps12, ldo1 - ldo10
@@ -68,6 +69,7 @@
- qcom,pm8005-rpmh-regulators
- qcom,pm8009-rpmh-regulators
- qcom,pm8009-1-rpmh-regulators
+ - qcom,pm8010-rpmh-regulators
- qcom,pm8150-rpmh-regulators
- qcom,pm8150l-rpmh-regulators
- qcom,pm8350-rpmh-regulators
@@ -242,6 +244,18 @@
properties:
compatible:
enum:
+ - qcom,pm8010-rpmh-regulators
+ then:
+ properties:
+ vdd-l1-l2-supply: true
+ vdd-l3-l4-supply: true
+ patternProperties:
+ "^vdd-l[5-7]-supply$": true
+
+ - if:
+ properties:
+ compatible:
+ enum:
- qcom,pm8150-rpmh-regulators
- qcom,pmc8180-rpmh-regulators
- qcom,pmm8155au-rpmh-regulators
diff --git a/dts/upstream/Bindings/regulator/qcom,smd-rpm-regulator.yaml b/dts/upstream/Bindings/regulator/qcom,smd-rpm-regulator.yaml
index 9ea8ac0..f2fd2df 100644
--- a/dts/upstream/Bindings/regulator/qcom,smd-rpm-regulator.yaml
+++ b/dts/upstream/Bindings/regulator/qcom,smd-rpm-regulator.yaml
@@ -47,6 +47,9 @@
For pm8916, s1, s2, s3, s4, l1, l2, l3, l4, l5, l6, l7, l8, l9, l10, l11,
l12, l13, l14, l15, l16, l17, l18
+ For pm8937, s1, s2, s3, s4, l1, l2, l3, l4, l5, l6, l7, l8, l9, l10,
+ l11, l12, l13, l14, l15, l16, l17, l18, l19, l20, l21, l22, l23
+
For pm8941, s1, s2, s3, s4, l1, l2, l3, l4, l5, l6, l7, l8, l9, l10, l11,
l12, l13, l14, l15, l16, l17, l18, l19, l20, l21, l22, l23, l24, lvs1, lvs2,
lvs3, 5vs1, 5vs2
@@ -92,6 +95,7 @@
- qcom,rpm-pm8841-regulators
- qcom,rpm-pm8909-regulators
- qcom,rpm-pm8916-regulators
+ - qcom,rpm-pm8937-regulators
- qcom,rpm-pm8941-regulators
- qcom,rpm-pm8950-regulators
- qcom,rpm-pm8953-regulators
diff --git a/dts/upstream/Bindings/regulator/qcom,spmi-regulator.yaml b/dts/upstream/Bindings/regulator/qcom,spmi-regulator.yaml
index 7a1b7d2..aea849e 100644
--- a/dts/upstream/Bindings/regulator/qcom,spmi-regulator.yaml
+++ b/dts/upstream/Bindings/regulator/qcom,spmi-regulator.yaml
@@ -22,6 +22,7 @@
- qcom,pm8841-regulators
- qcom,pm8909-regulators
- qcom,pm8916-regulators
+ - qcom,pm8937-regulators
- qcom,pm8941-regulators
- qcom,pm8950-regulators
- qcom,pm8994-regulators
@@ -296,6 +297,24 @@
compatible:
contains:
enum:
+ - qcom,pm8937-regulators
+ then:
+ properties:
+ vdd_l1_l19-supply: true
+ vdd_l20_l21-supply: true
+ vdd_l2_l23-supply: true
+ vdd_l3-supply: true
+ vdd_l4_l5_l6_l7_l16-supply: true
+ vdd_l8_l11_l12_l17_l22-supply: true
+ vdd_l9_l10_l13_l14_l15_l18-supply: true
+ patternProperties:
+ "^vdd_s[1-6]-supply$": true
+
+ - if:
+ properties:
+ compatible:
+ contains:
+ enum:
- qcom,pm8950-regulators
then:
properties:
diff --git a/dts/upstream/Bindings/regulator/qcom,usb-vbus-regulator.yaml b/dts/upstream/Bindings/regulator/qcom,usb-vbus-regulator.yaml
index 89c564d..534f87e 100644
--- a/dts/upstream/Bindings/regulator/qcom,usb-vbus-regulator.yaml
+++ b/dts/upstream/Bindings/regulator/qcom,usb-vbus-regulator.yaml
@@ -36,10 +36,11 @@
examples:
- |
- pm8150b {
+ pmic {
#address-cells = <1>;
#size-cells = <0>;
- pm8150b_vbus: usb-vbus-regulator@1100 {
+
+ usb-vbus-regulator@1100 {
compatible = "qcom,pm8150b-vbus-reg";
reg = <0x1100>;
regulator-min-microamp = <500000>;
diff --git a/dts/upstream/Bindings/regulator/regulator.yaml b/dts/upstream/Bindings/regulator/regulator.yaml
index 9daf0fc..1ef380d 100644
--- a/dts/upstream/Bindings/regulator/regulator.yaml
+++ b/dts/upstream/Bindings/regulator/regulator.yaml
@@ -114,6 +114,11 @@
description: Enable pull down resistor when the regulator is disabled.
type: boolean
+ system-critical-regulator:
+ description: Set if the regulator is critical to system stability or
+ functionality.
+ type: boolean
+
regulator-over-current-protection:
description: Enable over current protection.
type: boolean
@@ -181,6 +186,14 @@
be enabled but limit setting can be omitted. Limit is given as microvolt
offset from voltage set to regulator.
+ regulator-uv-less-critical-window-ms:
+ description: Specifies the time window (in milliseconds) following a
+ critical under-voltage event during which the system can continue to
+ operate safely while performing less critical operations. This property
+ provides a defined duration before a more severe reaction to the
+ under-voltage event is needed, allowing for certain non-urgent actions to
+ be carried out in preparation for potential power loss.
+
regulator-temp-protection-kelvin:
description: Set over temperature protection limit. This is a limit where
hardware performs emergency shutdown. Zero can be passed to disable
diff --git a/dts/upstream/Bindings/remoteproc/fsl,imx-rproc.yaml b/dts/upstream/Bindings/remoteproc/fsl,imx-rproc.yaml
index 30632ef..df36e29 100644
--- a/dts/upstream/Bindings/remoteproc/fsl,imx-rproc.yaml
+++ b/dts/upstream/Bindings/remoteproc/fsl,imx-rproc.yaml
@@ -113,10 +113,10 @@
};
imx7d-cm4 {
- compatible = "fsl,imx7d-cm4";
- memory-region = <&m4_reserved_sysmem1>, <&m4_reserved_sysmem2>;
- syscon = <&src>;
- clocks = <&clks IMX7D_ARM_M4_ROOT_CLK>;
+ compatible = "fsl,imx7d-cm4";
+ memory-region = <&m4_reserved_sysmem1>, <&m4_reserved_sysmem2>;
+ syscon = <&src>;
+ clocks = <&clks IMX7D_ARM_M4_ROOT_CLK>;
};
- |
diff --git a/dts/upstream/Bindings/remoteproc/qcom,sc7180-pas.yaml b/dts/upstream/Bindings/remoteproc/qcom,sc7180-pas.yaml
index f10f329..c054b84 100644
--- a/dts/upstream/Bindings/remoteproc/qcom,sc7180-pas.yaml
+++ b/dts/upstream/Bindings/remoteproc/qcom,sc7180-pas.yaml
@@ -18,7 +18,10 @@
enum:
- qcom,sc7180-adsp-pas
- qcom,sc7180-mpss-pas
+ - qcom,sc7280-adsp-pas
+ - qcom,sc7280-cdsp-pas
- qcom,sc7280-mpss-pas
+ - qcom,sc7280-wpss-pas
reg:
maxItems: 1
@@ -75,6 +78,7 @@
compatible:
enum:
- qcom,sc7180-adsp-pas
+ - qcom,sc7280-adsp-pas
then:
properties:
power-domains:
@@ -114,6 +118,23 @@
power-domains:
items:
- description: CX power domain
+ - description: MSS power domain
+ power-domain-names:
+ items:
+ - const: cx
+ - const: mss
+
+ - if:
+ properties:
+ compatible:
+ enum:
+ - qcom,sc7280-cdsp-pas
+ - qcom,sc7280-wpss-pas
+ then:
+ properties:
+ power-domains:
+ items:
+ - description: CX power domain
- description: MX power domain
power-domain-names:
items:
diff --git a/dts/upstream/Bindings/reset/amlogic,meson-reset.yaml b/dts/upstream/Bindings/reset/amlogic,meson-reset.yaml
index d3fdee8..f0c6c0d 100644
--- a/dts/upstream/Bindings/reset/amlogic,meson-reset.yaml
+++ b/dts/upstream/Bindings/reset/amlogic,meson-reset.yaml
@@ -18,6 +18,7 @@
- amlogic,meson-axg-reset # Reset Controller on AXG and compatible SoCs
- amlogic,meson-a1-reset # Reset Controller on A1 and compatible SoCs
- amlogic,meson-s4-reset # Reset Controller on S4 and compatible SoCs
+ - amlogic,c3-reset # Reset Controller on C3 and compatible SoCs
reg:
maxItems: 1
diff --git a/dts/upstream/Bindings/reset/fsl,imx-src.yaml b/dts/upstream/Bindings/reset/fsl,imx-src.yaml
index b11ac53..f5ec1d5 100644
--- a/dts/upstream/Bindings/reset/fsl,imx-src.yaml
+++ b/dts/upstream/Bindings/reset/fsl,imx-src.yaml
@@ -28,28 +28,17 @@
properties:
compatible:
oneOf:
- - const: "fsl,imx51-src"
- - items:
- - const: "fsl,imx50-src"
- - const: "fsl,imx51-src"
- - items:
- - const: "fsl,imx53-src"
- - const: "fsl,imx51-src"
- - items:
- - const: "fsl,imx6q-src"
- - const: "fsl,imx51-src"
- - items:
- - const: "fsl,imx6sx-src"
- - const: "fsl,imx51-src"
- - items:
- - const: "fsl,imx6sl-src"
- - const: "fsl,imx51-src"
- - items:
- - const: "fsl,imx6ul-src"
- - const: "fsl,imx51-src"
+ - const: fsl,imx51-src
- items:
- - const: "fsl,imx6sll-src"
- - const: "fsl,imx51-src"
+ - enum:
+ - fsl,imx50-src
+ - fsl,imx53-src
+ - fsl,imx6q-src
+ - fsl,imx6sx-src
+ - fsl,imx6sl-src
+ - fsl,imx6ul-src
+ - fsl,imx6sll-src
+ - const: fsl,imx51-src
reg:
maxItems: 1
diff --git a/dts/upstream/Bindings/reset/hisilicon,hi3660-reset.yaml b/dts/upstream/Bindings/reset/hisilicon,hi3660-reset.yaml
index cdfcf32..e4de002 100644
--- a/dts/upstream/Bindings/reset/hisilicon,hi3660-reset.yaml
+++ b/dts/upstream/Bindings/reset/hisilicon,hi3660-reset.yaml
@@ -50,32 +50,9 @@
examples:
- |
- #include <dt-bindings/interrupt-controller/irq.h>
- #include <dt-bindings/interrupt-controller/arm-gic.h>
- #include <dt-bindings/clock/hi3660-clock.h>
-
- iomcu: iomcu@ffd7e000 {
- compatible = "hisilicon,hi3660-iomcu", "syscon";
- reg = <0xffd7e000 0x1000>;
- };
-
- iomcu_rst: iomcu_rst_controller {
+ iomcu_rst_controller {
compatible = "hisilicon,hi3660-reset";
hisilicon,rst-syscon = <&iomcu>;
#reset-cells = <2>;
};
-
- /* Specifying reset lines connected to IP modules */
- i2c@ffd71000 {
- compatible = "snps,designware-i2c";
- reg = <0xffd71000 0x1000>;
- interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>;
- #address-cells = <1>;
- #size-cells = <0>;
- clock-frequency = <400000>;
- clocks = <&crg_ctrl HI3660_CLK_GATE_I2C0>;
- resets = <&iomcu_rst 0x20 3>;
- pinctrl-names = "default";
- pinctrl-0 = <&i2c0_pmx_func &i2c0_cfg_func>;
- };
...
diff --git a/dts/upstream/Bindings/reset/qcom,aoss-reset.yaml b/dts/upstream/Bindings/reset/qcom,aoss-reset.yaml
index d92e2b3..24beb71 100644
--- a/dts/upstream/Bindings/reset/qcom,aoss-reset.yaml
+++ b/dts/upstream/Bindings/reset/qcom,aoss-reset.yaml
@@ -18,17 +18,17 @@
oneOf:
- description: on SC7180 SoCs the following compatibles must be specified
items:
- - const: "qcom,sc7180-aoss-cc"
- - const: "qcom,sdm845-aoss-cc"
+ - const: qcom,sc7180-aoss-cc
+ - const: qcom,sdm845-aoss-cc
- description: on SC7280 SoCs the following compatibles must be specified
items:
- - const: "qcom,sc7280-aoss-cc"
- - const: "qcom,sdm845-aoss-cc"
+ - const: qcom,sc7280-aoss-cc
+ - const: qcom,sdm845-aoss-cc
- description: on SDM845 SoCs the following compatibles must be specified
items:
- - const: "qcom,sdm845-aoss-cc"
+ - const: qcom,sdm845-aoss-cc
reg:
maxItems: 1
diff --git a/dts/upstream/Bindings/reset/qcom,pdc-global.yaml b/dts/upstream/Bindings/reset/qcom,pdc-global.yaml
index ca5d793..f514363 100644
--- a/dts/upstream/Bindings/reset/qcom,pdc-global.yaml
+++ b/dts/upstream/Bindings/reset/qcom,pdc-global.yaml
@@ -18,16 +18,16 @@
oneOf:
- description: on SC7180 SoCs the following compatibles must be specified
items:
- - const: "qcom,sc7180-pdc-global"
- - const: "qcom,sdm845-pdc-global"
+ - const: qcom,sc7180-pdc-global
+ - const: qcom,sdm845-pdc-global
- description: on SC7280 SoCs the following compatibles must be specified
items:
- - const: "qcom,sc7280-pdc-global"
+ - const: qcom,sc7280-pdc-global
- description: on SDM845 SoCs the following compatibles must be specified
items:
- - const: "qcom,sdm845-pdc-global"
+ - const: qcom,sdm845-pdc-global
reg:
maxItems: 1
diff --git a/dts/upstream/Bindings/reset/renesas,rzg2l-usbphy-ctrl.yaml b/dts/upstream/Bindings/reset/renesas,rzg2l-usbphy-ctrl.yaml
index 731b8ce..03c1861 100644
--- a/dts/upstream/Bindings/reset/renesas,rzg2l-usbphy-ctrl.yaml
+++ b/dts/upstream/Bindings/reset/renesas,rzg2l-usbphy-ctrl.yaml
@@ -17,7 +17,7 @@
compatible:
items:
- enum:
- - renesas,r9a07g043-usbphy-ctrl # RZ/G2UL
+ - renesas,r9a07g043-usbphy-ctrl # RZ/G2UL and RZ/Five
- renesas,r9a07g044-usbphy-ctrl # RZ/G2{L,LC}
- renesas,r9a07g054-usbphy-ctrl # RZ/V2L
- const: renesas,rzg2l-usbphy-ctrl
diff --git a/dts/upstream/Bindings/reset/xlnx,zynqmp-reset.yaml b/dts/upstream/Bindings/reset/xlnx,zynqmp-reset.yaml
index 49db668..1f1b42d 100644
--- a/dts/upstream/Bindings/reset/xlnx,zynqmp-reset.yaml
+++ b/dts/upstream/Bindings/reset/xlnx,zynqmp-reset.yaml
@@ -7,7 +7,8 @@
title: Zynq UltraScale+ MPSoC and Versal reset
maintainers:
- - Piyush Mehta <piyush.mehta@amd.com>
+ - Mubin Sayyed <mubin.sayyed@amd.com>
+ - Radhey Shyam Pandey <radhey.shyam.pandey@amd.com>
description: |
The Zynq UltraScale+ MPSoC and Versal has several different resets.
diff --git a/dts/upstream/Bindings/riscv/cpus.yaml b/dts/upstream/Bindings/riscv/cpus.yaml
index f392e36..9d8670c 100644
--- a/dts/upstream/Bindings/riscv/cpus.yaml
+++ b/dts/upstream/Bindings/riscv/cpus.yaml
@@ -32,6 +32,7 @@
oneOf:
- items:
- enum:
+ - amd,mbv32
- andestech,ax45mp
- canaan,k210
- sifive,bullet0
@@ -62,8 +63,8 @@
mmu-type:
description:
- Identifies the MMU address translation mode used on this
- hart. These values originate from the RISC-V Privileged
+ Identifies the largest MMU address translation mode supported by
+ this hart. These values originate from the RISC-V Privileged
Specification document, available from
https://riscv.org/specifications/
$ref: /schemas/types.yaml#/definitions/string
@@ -79,6 +80,11 @@
description:
The blocksize in bytes for the Zicbom cache operations.
+ riscv,cbop-block-size:
+ $ref: /schemas/types.yaml#/definitions/uint32
+ description:
+ The blocksize in bytes for the Zicbop cache operations.
+
riscv,cboz-block-size:
$ref: /schemas/types.yaml#/definitions/uint32
description:
diff --git a/dts/upstream/Bindings/riscv/extensions.yaml b/dts/upstream/Bindings/riscv/extensions.yaml
index c91ab0e..63d81dc 100644
--- a/dts/upstream/Bindings/riscv/extensions.yaml
+++ b/dts/upstream/Bindings/riscv/extensions.yaml
@@ -48,7 +48,7 @@
insensitive, letters in the riscv,isa string must be all
lowercase.
$ref: /schemas/types.yaml#/definitions/string
- pattern: ^rv(?:64|32)imaf?d?q?c?b?k?j?p?v?h?(?:[hsxz](?:[a-z])+)?(?:_[hsxz](?:[a-z])+)*$
+ pattern: ^rv(?:64|32)imaf?d?q?c?b?k?j?p?v?h?(?:[hsxz](?:[0-9a-z])+)?(?:_[hsxz](?:[0-9a-z])+)*$
deprecated: true
riscv,isa-base:
@@ -171,6 +171,12 @@
memory types as ratified in the 20191213 version of the privileged
ISA specification.
+ - const: zacas
+ description: |
+ The Zacas extension for Atomic Compare-and-Swap (CAS) instructions
+ is supported as ratified at commit 5059e0ca641c ("update to
+ ratified") of the riscv-zacas.
+
- const: zba
description: |
The standard Zba bit-manipulation extension for address generation
@@ -190,12 +196,111 @@
multiplication as ratified at commit 6d33919 ("Merge pull request
#158 from hirooih/clmul-fix-loop-end-condition") of riscv-bitmanip.
+ - const: zbkb
+ description:
+ The standard Zbkb bitmanip instructions for cryptography as ratified
+ in version 1.0 of RISC-V Cryptography Extensions Volume I
+ specification.
+
+ - const: zbkc
+ description:
+ The standard Zbkc carry-less multiply instructions as ratified
+ in version 1.0 of RISC-V Cryptography Extensions Volume I
+ specification.
+
+ - const: zbkx
+ description:
+ The standard Zbkx crossbar permutation instructions as ratified
+ in version 1.0 of RISC-V Cryptography Extensions Volume I
+ specification.
+
- const: zbs
description: |
The standard Zbs bit-manipulation extension for single-bit
instructions as ratified at commit 6d33919 ("Merge pull request #158
from hirooih/clmul-fix-loop-end-condition") of riscv-bitmanip.
+ - const: zfa
+ description:
+ The standard Zfa extension for additional floating point
+ instructions, as ratified in commit 056b6ff ("Zfa is ratified") of
+ riscv-isa-manual.
+
+ - const: zfh
+ description:
+ The standard Zfh extension for 16-bit half-precision binary
+ floating-point instructions, as ratified in commit 64074bc ("Update
+ version numbers for Zfh/Zfinx") of riscv-isa-manual.
+
+ - const: zfhmin
+ description:
+ The standard Zfhmin extension which provides minimal support for
+ 16-bit half-precision binary floating-point instructions, as ratified
+ in commit 64074bc ("Update version numbers for Zfh/Zfinx") of
+ riscv-isa-manual.
+
+ - const: zk
+ description:
+ The standard Zk Standard Scalar cryptography extension as ratified
+ in version 1.0 of RISC-V Cryptography Extensions Volume I
+ specification.
+
+ - const: zkn
+ description:
+ The standard Zkn NIST algorithm suite extensions as ratified in
+ version 1.0 of RISC-V Cryptography Extensions Volume I
+ specification.
+
+ - const: zknd
+ description: |
+ The standard Zknd for NIST suite: AES decryption instructions as
+ ratified in version 1.0 of RISC-V Cryptography Extensions Volume I
+ specification.
+
+ - const: zkne
+ description: |
+ The standard Zkne for NIST suite: AES encryption instructions as
+ ratified in version 1.0 of RISC-V Cryptography Extensions Volume I
+ specification.
+
+ - const: zknh
+ description: |
+ The standard Zknh for NIST suite: hash function instructions as
+ ratified in version 1.0 of RISC-V Cryptography Extensions Volume I
+ specification.
+
+ - const: zkr
+ description:
+ The standard Zkr entropy source extension as ratified in version
+ 1.0 of RISC-V Cryptography Extensions Volume I specification.
+ This string being present means that the CSR associated to this
+ extension is accessible at the privilege level to which that
+ device-tree has been provided.
+
+ - const: zks
+ description:
+ The standard Zks ShangMi algorithm suite extensions as ratified in
+ version 1.0 of RISC-V Cryptography Extensions Volume I
+ specification.
+
+ - const: zksed
+ description: |
+ The standard Zksed for ShangMi suite: SM4 block cipher instructions
+ as ratified in version 1.0 of RISC-V Cryptography Extensions
+ Volume I specification.
+
+ - const: zksh
+ description: |
+ The standard Zksh for ShangMi suite: SM3 hash function instructions
+ as ratified in version 1.0 of RISC-V Cryptography Extensions
+ Volume I specification.
+
+ - const: zkt
+ description:
+ The standard Zkt for data independent execution latency as ratified
+ in version 1.0 of RISC-V Cryptography Extensions Volume I
+ specification.
+
- const: zicbom
description:
The standard Zicbom extension for base cache management operations as
@@ -246,6 +351,12 @@
The standard Zihintpause extension for pause hints, as ratified in
commit d8ab5c7 ("Zihintpause is ratified") of the riscv-isa-manual.
+ - const: zihintntl
+ description:
+ The standard Zihintntl extension for non-temporal locality hints, as
+ ratified in commit 0dc91f5 ("Zihintntl is ratified") of the
+ riscv-isa-manual.
+
- const: zihpm
description:
The standard Zihpm extension for hardware performance counters, as
@@ -258,5 +369,113 @@
in commit 2e5236 ("Ztso is now ratified.") of the
riscv-isa-manual.
+ - const: zvbb
+ description:
+ The standard Zvbb extension for vectored basic bit-manipulation
+ instructions, as ratified in commit 56ed795 ("Update
+ riscv-crypto-spec-vector.adoc") of riscv-crypto.
+
+ - const: zvbc
+ description:
+ The standard Zvbc extension for vectored carryless multiplication
+ instructions, as ratified in commit 56ed795 ("Update
+ riscv-crypto-spec-vector.adoc") of riscv-crypto.
+
+ - const: zvfh
+ description:
+ The standard Zvfh extension for vectored half-precision
+ floating-point instructions, as ratified in commit e2ccd05
+ ("Remove draft warnings from Zvfh[min]") of riscv-v-spec.
+
+ - const: zvfhmin
+ description:
+ The standard Zvfhmin extension for vectored minimal half-precision
+ floating-point instructions, as ratified in commit e2ccd05
+ ("Remove draft warnings from Zvfh[min]") of riscv-v-spec.
+
+ - const: zvkb
+ description:
+ The standard Zvkb extension for vector cryptography bit-manipulation
+ instructions, as ratified in commit 56ed795 ("Update
+ riscv-crypto-spec-vector.adoc") of riscv-crypto.
+
+ - const: zvkg
+ description:
+ The standard Zvkg extension for vector GCM/GMAC instructions, as
+ ratified in commit 56ed795 ("Update riscv-crypto-spec-vector.adoc")
+ of riscv-crypto.
+
+ - const: zvkn
+ description:
+ The standard Zvkn extension for NIST algorithm suite instructions, as
+ ratified in commit 56ed795 ("Update riscv-crypto-spec-vector.adoc")
+ of riscv-crypto.
+
+ - const: zvknc
+ description:
+ The standard Zvknc extension for NIST algorithm suite with carryless
+ multiply instructions, as ratified in commit 56ed795 ("Update
+ riscv-crypto-spec-vector.adoc") of riscv-crypto.
+
+ - const: zvkned
+ description:
+ The standard Zvkned extension for Vector AES block cipher
+ instructions, as ratified in commit 56ed795 ("Update
+ riscv-crypto-spec-vector.adoc") of riscv-crypto.
+
+ - const: zvkng
+ description:
+ The standard Zvkng extension for NIST algorithm suite with GCM
+ instructions, as ratified in commit 56ed795 ("Update
+ riscv-crypto-spec-vector.adoc") of riscv-crypto.
+
+ - const: zvknha
+ description: |
+ The standard Zvknha extension for NIST suite: vector SHA-2 secure,
+ hash (SHA-256 only) instructions, as ratified in commit
+ 56ed795 ("Update riscv-crypto-spec-vector.adoc") of riscv-crypto.
+
+ - const: zvknhb
+ description: |
+ The standard Zvknhb extension for NIST suite: vector SHA-2 secure,
+ hash (SHA-256 and SHA-512) instructions, as ratified in commit
+ 56ed795 ("Update riscv-crypto-spec-vector.adoc") of riscv-crypto.
+
+ - const: zvks
+ description:
+ The standard Zvks extension for ShangMi algorithm suite
+ instructions, as ratified in commit 56ed795 ("Update
+ riscv-crypto-spec-vector.adoc") of riscv-crypto.
+
+ - const: zvksc
+ description:
+ The standard Zvksc extension for ShangMi algorithm suite with
+ carryless multiplication instructions, as ratified in commit 56ed795
+ ("Update riscv-crypto-spec-vector.adoc") of riscv-crypto.
+
+ - const: zvksed
+ description: |
+ The standard Zvksed extension for ShangMi suite: SM4 block cipher
+ instructions, as ratified in commit 56ed795 ("Update
+ riscv-crypto-spec-vector.adoc") of riscv-crypto.
+
+ - const: zvksh
+ description: |
+ The standard Zvksh extension for ShangMi suite: SM3 secure hash
+ instructions, as ratified in commit 56ed795 ("Update
+ riscv-crypto-spec-vector.adoc") of riscv-crypto.
+
+ - const: zvksg
+ description:
+ The standard Zvksg extension for ShangMi algorithm suite with GCM
+ instructions, as ratified in commit 56ed795 ("Update
+ riscv-crypto-spec-vector.adoc") of riscv-crypto.
+
+ - const: zvkt
+ description:
+ The standard Zvkt extension for vector data-independent execution
+ latency, as ratified in commit 56ed795 ("Update
+ riscv-crypto-spec-vector.adoc") of riscv-crypto.
+
additionalProperties: true
...
diff --git a/dts/upstream/Bindings/riscv/sophgo.yaml b/dts/upstream/Bindings/riscv/sophgo.yaml
index 86748c5..9bc813d 100644
--- a/dts/upstream/Bindings/riscv/sophgo.yaml
+++ b/dts/upstream/Bindings/riscv/sophgo.yaml
@@ -24,6 +24,10 @@
- const: sophgo,cv1800b
- items:
- enum:
+ - sophgo,huashan-pi
+ - const: sophgo,cv1812h
+ - items:
+ - enum:
- milkv,pioneer
- const: sophgo,sg2042
diff --git a/dts/upstream/Bindings/rng/starfive,jh7110-trng.yaml b/dts/upstream/Bindings/rng/starfive,jh7110-trng.yaml
index 2b76ce2..4639247 100644
--- a/dts/upstream/Bindings/rng/starfive,jh7110-trng.yaml
+++ b/dts/upstream/Bindings/rng/starfive,jh7110-trng.yaml
@@ -11,7 +11,11 @@
properties:
compatible:
- const: starfive,jh7110-trng
+ oneOf:
+ - items:
+ - const: starfive,jh8100-trng
+ - const: starfive,jh7110-trng
+ - const: starfive,jh7110-trng
reg:
maxItems: 1
diff --git a/dts/upstream/Bindings/rtc/adi,max31335.yaml b/dts/upstream/Bindings/rtc/adi,max31335.yaml
new file mode 100644
index 0000000..0125cf6
--- /dev/null
+++ b/dts/upstream/Bindings/rtc/adi,max31335.yaml
@@ -0,0 +1,70 @@
+# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/rtc/adi,max31335.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Analog Devices MAX31335 RTC
+
+maintainers:
+ - Antoniu Miclaus <antoniu.miclaus@analog.com>
+
+description:
+ Analog Devices MAX31335 I2C RTC ±2ppm Automotive Real-Time Clock with
+ Integrated MEMS Resonator.
+
+allOf:
+ - $ref: rtc.yaml#
+
+properties:
+ compatible:
+ const: adi,max31335
+
+ reg:
+ maxItems: 1
+
+ interrupts:
+ maxItems: 1
+
+ "#clock-cells":
+ description:
+ RTC can be used as a clock source through its clock output pin.
+ const: 0
+
+ adi,tc-diode:
+ description:
+ Select the diode configuration for the trickle charger.
+ schottky - Schottky diode in series.
+ standard+schottky - standard diode + Schottky diode in series.
+ enum: [schottky, standard+schottky]
+
+ trickle-resistor-ohms:
+ description:
+ Selected resistor for trickle charger. Should be specified if trickle
+ charger should be enabled.
+ enum: [3000, 6000, 11000]
+
+required:
+ - compatible
+ - reg
+
+unevaluatedProperties: false
+
+examples:
+ - |
+ #include <dt-bindings/interrupt-controller/irq.h>
+ i2c {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ rtc@68 {
+ compatible = "adi,max31335";
+ reg = <0x68>;
+ pinctrl-0 = <&rtc_nint_pins>;
+ interrupts-extended = <&gpio1 16 IRQ_TYPE_LEVEL_HIGH>;
+ aux-voltage-chargeable = <1>;
+ trickle-resistor-ohms = <6000>;
+ adi,tc-diode = "schottky";
+ };
+ };
+...
diff --git a/dts/upstream/Bindings/rtc/epson,rx8900.yaml b/dts/upstream/Bindings/rtc/epson,rx8900.yaml
index 1df7c45..b770149 100644
--- a/dts/upstream/Bindings/rtc/epson,rx8900.yaml
+++ b/dts/upstream/Bindings/rtc/epson,rx8900.yaml
@@ -29,6 +29,8 @@
trickle-diode-disable: true
+ wakeup-source: true
+
required:
- compatible
- reg
diff --git a/dts/upstream/Bindings/rtc/nuvoton,ma35d1-rtc.yaml b/dts/upstream/Bindings/rtc/nuvoton,ma35d1-rtc.yaml
new file mode 100644
index 0000000..5e4ade8
--- /dev/null
+++ b/dts/upstream/Bindings/rtc/nuvoton,ma35d1-rtc.yaml
@@ -0,0 +1,48 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/rtc/nuvoton,ma35d1-rtc.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Nuvoton MA35D1 Real Time Clock
+
+maintainers:
+ - Min-Jen Chen <mjchen@nuvoton.com>
+
+allOf:
+ - $ref: rtc.yaml#
+
+properties:
+ compatible:
+ enum:
+ - nuvoton,ma35d1-rtc
+
+ reg:
+ maxItems: 1
+
+ interrupts:
+ maxItems: 1
+
+ clocks:
+ maxItems: 1
+
+required:
+ - compatible
+ - reg
+ - interrupts
+ - clocks
+
+unevaluatedProperties: false
+
+examples:
+ - |
+ #include <dt-bindings/interrupt-controller/arm-gic.h>
+ #include <dt-bindings/clock/nuvoton,ma35d1-clk.h>
+ rtc@40410000 {
+ compatible = "nuvoton,ma35d1-rtc";
+ reg = <0x40410000 0x200>;
+ interrupts = <GIC_SPI 5 IRQ_TYPE_EDGE_RISING>;
+ clocks = <&clk RTC_GATE>;
+ };
+
+...
diff --git a/dts/upstream/Bindings/rtc/qcom-pm8xxx-rtc.yaml b/dts/upstream/Bindings/rtc/qcom-pm8xxx-rtc.yaml
index b95a69c..d274bb7 100644
--- a/dts/upstream/Bindings/rtc/qcom-pm8xxx-rtc.yaml
+++ b/dts/upstream/Bindings/rtc/qcom-pm8xxx-rtc.yaml
@@ -61,27 +61,27 @@
examples:
- |
+ #include <dt-bindings/interrupt-controller/irq.h>
#include <dt-bindings/spmi/spmi.h>
- spmi_bus: spmi@c440000 {
- reg = <0x0c440000 0x1100>;
- #address-cells = <2>;
- #size-cells = <0>;
- pmicintc: pmic@0 {
- reg = <0x0 SPMI_USID>;
- compatible = "qcom,pm8921";
- interrupts = <104 8>;
- #interrupt-cells = <2>;
- interrupt-controller;
- #address-cells = <1>;
+
+ spmi {
+ #address-cells = <2>;
#size-cells = <0>;
- pm8921_rtc: rtc@11d {
- compatible = "qcom,pm8921-rtc";
- reg = <0x11d>;
- interrupts = <0x27 0>;
- nvmem-cells = <&rtc_offset>;
- nvmem-cell-names = "offset";
+ pmic@0 {
+ compatible = "qcom,pm8941", "qcom,spmi-pmic";
+ reg = <0x0 SPMI_USID>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ rtc@6000 {
+ compatible = "qcom,pm8941-rtc";
+ reg = <0x6000>, <0x6100>;
+ reg-names = "rtc", "alarm";
+ interrupts = <0x0 0x61 0x1 IRQ_TYPE_EDGE_RISING>;
+ nvmem-cells = <&rtc_offset>;
+ nvmem-cell-names = "offset";
+ };
};
- };
};
...
diff --git a/dts/upstream/Bindings/rtc/s3c-rtc.yaml b/dts/upstream/Bindings/rtc/s3c-rtc.yaml
index d51b236..bf4e11d 100644
--- a/dts/upstream/Bindings/rtc/s3c-rtc.yaml
+++ b/dts/upstream/Bindings/rtc/s3c-rtc.yaml
@@ -17,6 +17,11 @@
- samsung,s3c2416-rtc
- samsung,s3c2443-rtc
- samsung,s3c6410-rtc
+ - items:
+ - enum:
+ - samsung,exynos7-rtc
+ - samsung,exynos850-rtc
+ - const: samsung,s3c6410-rtc
- const: samsung,exynos3250-rtc
deprecated: true
diff --git a/dts/upstream/Bindings/security/tpm/google,cr50.txt b/dts/upstream/Bindings/security/tpm/google,cr50.txt
deleted file mode 100644
index cd69c2e..0000000
--- a/dts/upstream/Bindings/security/tpm/google,cr50.txt
+++ /dev/null
@@ -1,19 +0,0 @@
-* H1 Secure Microcontroller with Cr50 Firmware on SPI Bus.
-
-H1 Secure Microcontroller running Cr50 firmware provides several
-functions, including TPM-like functionality. It communicates over
-SPI using the FIFO protocol described in the PTP Spec, section 6.
-
-Required properties:
-- compatible: Should be "google,cr50".
-- spi-max-frequency: Maximum SPI frequency.
-
-Example:
-
-&spi0 {
- tpm@0 {
- compatible = "google,cr50";
- reg = <0>;
- spi-max-frequency = <800000>;
- };
-};
diff --git a/dts/upstream/Bindings/security/tpm/ibmvtpm.txt b/dts/upstream/Bindings/security/tpm/ibmvtpm.txt
deleted file mode 100644
index d89f999..0000000
--- a/dts/upstream/Bindings/security/tpm/ibmvtpm.txt
+++ /dev/null
@@ -1,41 +0,0 @@
-* Device Tree Bindings for IBM Virtual Trusted Platform Module(vtpm)
-
-Required properties:
-
-- compatible : property name that conveys the platform architecture
- identifiers, as 'IBM,vtpm'
-- device_type : specifies type of virtual device
-- interrupts : property specifying the interrupt source number and
- sense code associated with this virtual I/O Adapters
-- ibm,my-drc-index : integer index for the connector between the device
- and its parent - present only if Dynamic
- Reconfiguration(DR) Connector is enabled
-- ibm,#dma-address-cells: specifies the number of cells that are used to
- encode the physical address field of dma-window
- properties
-- ibm,#dma-size-cells : specifies the number of cells that are used to
- encode the size field of dma-window properties
-- ibm,my-dma-window : specifies DMA window associated with this virtual
- IOA
-- ibm,loc-code : specifies the unique and persistent location code
- associated with this virtual I/O Adapters
-- linux,sml-base : 64-bit base address of the reserved memory allocated
- for the firmware event log
-- linux,sml-size : size of the memory allocated for the firmware event log
-
-Example (IBM Virtual Trusted Platform Module)
----------------------------------------------
-
- vtpm@30000003 {
- ibm,#dma-size-cells = <0x2>;
- compatible = "IBM,vtpm";
- device_type = "IBM,vtpm";
- ibm,my-drc-index = <0x30000003>;
- ibm,#dma-address-cells = <0x2>;
- linux,sml-base = <0xc60e 0x0>;
- interrupts = <0xa0003 0x0>;
- ibm,my-dma-window = <0x10000003 0x0 0x0 0x0 0x10000000>;
- ibm,loc-code = "U8286.41A.10082DV-V3-C3";
- reg = <0x30000003>;
- linux,sml-size = <0xbce10200>;
- };
diff --git a/dts/upstream/Bindings/security/tpm/st33zp24-i2c.txt b/dts/upstream/Bindings/security/tpm/st33zp24-i2c.txt
deleted file mode 100644
index 0dc121b..0000000
--- a/dts/upstream/Bindings/security/tpm/st33zp24-i2c.txt
+++ /dev/null
@@ -1,34 +0,0 @@
-* STMicroelectronics SAS. ST33ZP24 TPM SoC
-
-Required properties:
-- compatible: Should be "st,st33zp24-i2c".
-- clock-frequency: I²C work frequency.
-- reg: address on the bus
-
-Optional ST33ZP24 Properties:
-- interrupts: GPIO interrupt to which the chip is connected
-- lpcpd-gpios: Output GPIO pin used for ST33ZP24 power management D1/D2 state.
-If set, power must be present when the platform is going into sleep/hibernate mode.
-
-Optional SoC Specific Properties:
-- pinctrl-names: Contains only one value - "default".
-- pintctrl-0: Specifies the pin control groups used for this controller.
-
-Example (for ARM-based BeagleBoard xM with ST33ZP24 on I2C2):
-
-&i2c2 {
-
-
- st33zp24: st33zp24@13 {
-
- compatible = "st,st33zp24-i2c";
-
- reg = <0x13>;
- clock-frequency = <400000>;
-
- interrupt-parent = <&gpio5>;
- interrupts = <7 IRQ_TYPE_LEVEL_HIGH>;
-
- lpcpd-gpios = <&gpio5 15 GPIO_ACTIVE_HIGH>;
- };
-};
diff --git a/dts/upstream/Bindings/security/tpm/st33zp24-spi.txt b/dts/upstream/Bindings/security/tpm/st33zp24-spi.txt
deleted file mode 100644
index 3719897..0000000
--- a/dts/upstream/Bindings/security/tpm/st33zp24-spi.txt
+++ /dev/null
@@ -1,32 +0,0 @@
-* STMicroelectronics SAS. ST33ZP24 TPM SoC
-
-Required properties:
-- compatible: Should be "st,st33zp24-spi".
-- spi-max-frequency: Maximum SPI frequency (<= 10000000).
-
-Optional ST33ZP24 Properties:
-- interrupts: GPIO interrupt to which the chip is connected
-- lpcpd-gpios: Output GPIO pin used for ST33ZP24 power management D1/D2 state.
-If set, power must be present when the platform is going into sleep/hibernate mode.
-
-Optional SoC Specific Properties:
-- pinctrl-names: Contains only one value - "default".
-- pintctrl-0: Specifies the pin control groups used for this controller.
-
-Example (for ARM-based BeagleBoard xM with ST33ZP24 on SPI4):
-
-&mcspi4 {
-
-
- st33zp24@0 {
-
- compatible = "st,st33zp24-spi";
-
- spi-max-frequency = <10000000>;
-
- interrupt-parent = <&gpio5>;
- interrupts = <7 IRQ_TYPE_LEVEL_HIGH>;
-
- lpcpd-gpios = <&gpio5 15 GPIO_ACTIVE_HIGH>;
- };
-};
diff --git a/dts/upstream/Bindings/security/tpm/tpm-i2c.txt b/dts/upstream/Bindings/security/tpm/tpm-i2c.txt
deleted file mode 100644
index a65d7b7..0000000
--- a/dts/upstream/Bindings/security/tpm/tpm-i2c.txt
+++ /dev/null
@@ -1,26 +0,0 @@
-* Device Tree Bindings for I2C based Trusted Platform Module(TPM)
-
-Required properties:
-
-- compatible : 'manufacturer,model', eg. nuvoton,npct650
-- label : human readable string describing the device, eg. "tpm"
-- linux,sml-base : 64-bit base address of the reserved memory allocated for
- the firmware event log
-- linux,sml-size : size of the memory allocated for the firmware event log
-
-Optional properties:
-
-- powered-while-suspended: present when the TPM is left powered on between
- suspend and resume (makes the suspend/resume
- callbacks do nothing).
-
-Example (for OpenPower Systems with Nuvoton TPM 2.0 on I2C)
-----------------------------------------------------------
-
-tpm@57 {
- reg = <0x57>;
- label = "tpm";
- compatible = "nuvoton,npct650", "nuvoton,npct601";
- linux,sml-base = <0x7f 0xfd450000>;
- linux,sml-size = <0x10000>;
-};
diff --git a/dts/upstream/Bindings/security/tpm/tpm_tis_mmio.txt b/dts/upstream/Bindings/security/tpm/tpm_tis_mmio.txt
deleted file mode 100644
index 7c63044..0000000
--- a/dts/upstream/Bindings/security/tpm/tpm_tis_mmio.txt
+++ /dev/null
@@ -1,25 +0,0 @@
-Trusted Computing Group MMIO Trusted Platform Module
-
-The TCG defines multi vendor standard for accessing a TPM chip, this
-is the standard protocol defined to access the TPM via MMIO. Typically
-this interface will be implemented over Intel's LPC bus.
-
-Refer to the 'TCG PC Client Specific TPM Interface Specification (TIS)' TCG
-publication for the specification.
-
-Required properties:
-
-- compatible: should contain a string below for the chip, followed by
- "tcg,tpm-tis-mmio". Valid chip strings are:
- * "atmel,at97sc3204"
-- reg: The location of the MMIO registers, should be at least 0x5000 bytes
-- interrupts: An optional interrupt indicating command completion.
-
-Example:
-
- tpm_tis@90000 {
- compatible = "atmel,at97sc3204", "tcg,tpm-tis-mmio";
- reg = <0x90000 0x5000>;
- interrupt-parent = <&EIC0>;
- interrupts = <1 2>;
- };
diff --git a/dts/upstream/Bindings/security/tpm/tpm_tis_spi.txt b/dts/upstream/Bindings/security/tpm/tpm_tis_spi.txt
deleted file mode 100644
index b800667..0000000
--- a/dts/upstream/Bindings/security/tpm/tpm_tis_spi.txt
+++ /dev/null
@@ -1,23 +0,0 @@
-Required properties:
-- compatible: should be one of the following
- "st,st33htpm-spi"
- "infineon,slb9670"
- "tcg,tpm_tis-spi"
-- spi-max-frequency: Maximum SPI frequency (depends on TPMs).
-
-Optional SoC Specific Properties:
-- pinctrl-names: Contains only one value - "default".
-- pintctrl-0: Specifies the pin control groups used for this controller.
-
-Example (for ARM-based BeagleBoard xM with TPM_TIS on SPI4):
-
-&mcspi4 {
-
-
- tpm_tis@0 {
-
- compatible = "tcg,tpm_tis-spi";
-
- spi-max-frequency = <10000000>;
- };
-};
diff --git a/dts/upstream/Bindings/serial/arm,dcc.yaml b/dts/upstream/Bindings/serial/arm,dcc.yaml
new file mode 100644
index 0000000..fd05893
--- /dev/null
+++ b/dts/upstream/Bindings/serial/arm,dcc.yaml
@@ -0,0 +1,30 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/serial/arm,dcc.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: ARM DCC (Data communication channel) serial emulation
+
+maintainers:
+ - Michal Simek <michal.simek@amd.com>
+
+description: |
+ ARM DCC (Data communication channel) serial emulation interface available
+ via JTAG can be also used as one of serial line tightly coupled with every
+ ARM CPU available in the system.
+
+properties:
+ compatible:
+ const: arm,dcc
+
+required:
+ - compatible
+
+additionalProperties: false
+
+examples:
+ - |
+ serial {
+ compatible = "arm,dcc";
+ };
diff --git a/dts/upstream/Bindings/serial/fsl,s32-linflexuart.yaml b/dts/upstream/Bindings/serial/fsl,s32-linflexuart.yaml
index 9205399..7a10555 100644
--- a/dts/upstream/Bindings/serial/fsl,s32-linflexuart.yaml
+++ b/dts/upstream/Bindings/serial/fsl,s32-linflexuart.yaml
@@ -13,7 +13,7 @@
https://www.nxp.com/webapp/Download?colCode=S32V234RM.
maintainers:
- - Chester Lin <clin@suse.com>
+ - Chester Lin <chester62515@gmail.com>
allOf:
- $ref: serial.yaml#
diff --git a/dts/upstream/Bindings/serial/fsl-imx-uart.yaml b/dts/upstream/Bindings/serial/fsl-imx-uart.yaml
index 8303555..9c6dc16 100644
--- a/dts/upstream/Bindings/serial/fsl-imx-uart.yaml
+++ b/dts/upstream/Bindings/serial/fsl-imx-uart.yaml
@@ -9,10 +9,6 @@
maintainers:
- Fabio Estevam <festevam@gmail.com>
-allOf:
- - $ref: serial.yaml#
- - $ref: rs485.yaml#
-
properties:
compatible:
oneOf:
@@ -68,7 +64,11 @@
- const: tx
interrupts:
- maxItems: 1
+ items:
+ - description: UART RX Interrupt
+ - description: UART TX Interrupt
+ - description: UART RTS Interrupt
+ minItems: 1
wakeup-source: true
@@ -110,6 +110,25 @@
- clock-names
- interrupts
+allOf:
+ - $ref: serial.yaml#
+ - $ref: rs485.yaml#
+
+ - if:
+ properties:
+ compatible:
+ contains:
+ const: fsl,imx1-uart
+ then:
+ properties:
+ interrupts:
+ minItems: 3
+ maxItems: 3
+ else:
+ properties:
+ interrupts:
+ maxItems: 1
+
unevaluatedProperties: false
examples:
diff --git a/dts/upstream/Bindings/serial/qcom,msm-uartdm.yaml b/dts/upstream/Bindings/serial/qcom,msm-uartdm.yaml
index ee52bf8..e0fa363 100644
--- a/dts/upstream/Bindings/serial/qcom,msm-uartdm.yaml
+++ b/dts/upstream/Bindings/serial/qcom,msm-uartdm.yaml
@@ -48,9 +48,17 @@
- const: tx
- const: rx
+ interconnects:
+ maxItems: 1
+
interrupts:
maxItems: 1
+ operating-points-v2: true
+
+ power-domains:
+ maxItems: 1
+
qcom,rx-crci:
$ref: /schemas/types.yaml#/definitions/uint32
description:
@@ -99,7 +107,9 @@
examples:
- |
+ #include <dt-bindings/interconnect/qcom,msm8996.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
+ #include <dt-bindings/power/qcom-rpmpd.h>
serial@f991e000 {
compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
@@ -109,4 +119,7 @@
clock-names = "core", "iface";
dmas = <&dma0 0>, <&dma0 1>;
dma-names = "tx", "rx";
+ power-domains = <&rpmpd MSM8996_VDDCX>;
+ operating-points-v2 = <&uart_opp_table>;
+ interconnects = <&pnoc MASTER_BLSP_1 &bimc SLAVE_EBI_CH0>;
};
diff --git a/dts/upstream/Bindings/serial/renesas,sci.yaml b/dts/upstream/Bindings/serial/renesas,sci.yaml
index 9f73052..64d3db6 100644
--- a/dts/upstream/Bindings/serial/renesas,sci.yaml
+++ b/dts/upstream/Bindings/serial/renesas,sci.yaml
@@ -17,7 +17,7 @@
oneOf:
- items:
- enum:
- - renesas,r9a07g043-sci # RZ/G2UL
+ - renesas,r9a07g043-sci # RZ/G2UL and RZ/Five
- renesas,r9a07g044-sci # RZ/G2{L,LC}
- renesas,r9a07g054-sci # RZ/V2L
- const: renesas,sci # generic SCI compatible UART
diff --git a/dts/upstream/Bindings/serial/samsung_uart.yaml b/dts/upstream/Bindings/serial/samsung_uart.yaml
index ac60ab1..133259e 100644
--- a/dts/upstream/Bindings/serial/samsung_uart.yaml
+++ b/dts/upstream/Bindings/serial/samsung_uart.yaml
@@ -18,17 +18,29 @@
properties:
compatible:
oneOf:
- - items:
- - const: samsung,exynosautov9-uart
- - const: samsung,exynos850-uart
- enum:
- apple,s5l-uart
- axis,artpec8-uart
+ - google,gs101-uart
- samsung,s3c6400-uart
- samsung,s5pv210-uart
- samsung,exynos4210-uart
- samsung,exynos5433-uart
- samsung,exynos850-uart
+ - items:
+ - enum:
+ - samsung,exynos7-uart
+ - tesla,fsd-uart
+ - const: samsung,exynos4210-uart
+ - items:
+ - enum:
+ - samsung,exynos7885-uart
+ - const: samsung,exynos5433-uart
+ - items:
+ - enum:
+ - samsung,exynosautov9-uart
+ - samsung,exynosautov920-uart
+ - const: samsung,exynos850-uart
reg:
maxItems: 1
@@ -122,6 +134,16 @@
- const: uart
- const: clk_uart_baud0
+ - if:
+ properties:
+ compatible:
+ contains:
+ enum:
+ - google,gs101-uart
+ then:
+ required:
+ - samsung,uart-fifosize
+
unevaluatedProperties: false
examples:
diff --git a/dts/upstream/Bindings/serial/snps-dw-apb-uart.yaml b/dts/upstream/Bindings/serial/snps-dw-apb-uart.yaml
index 17c5531..1001d2a 100644
--- a/dts/upstream/Bindings/serial/snps-dw-apb-uart.yaml
+++ b/dts/upstream/Bindings/serial/snps-dw-apb-uart.yaml
@@ -11,6 +11,7 @@
allOf:
- $ref: serial.yaml#
+ - $ref: rs485.yaml#
properties:
compatible:
diff --git a/dts/upstream/Bindings/serial/sprd-uart.yaml b/dts/upstream/Bindings/serial/sprd-uart.yaml
index 28ff77a..f4dbb6d 100644
--- a/dts/upstream/Bindings/serial/sprd-uart.yaml
+++ b/dts/upstream/Bindings/serial/sprd-uart.yaml
@@ -20,6 +20,7 @@
- sprd,sc9860-uart
- sprd,sc9863a-uart
- sprd,ums512-uart
+ - sprd,ums9620-uart
- const: sprd,sc9836-uart
- const: sprd,sc9836-uart
diff --git a/dts/upstream/Bindings/soc/amlogic/amlogic,meson-gx-hhi-sysctrl.yaml b/dts/upstream/Bindings/soc/amlogic/amlogic,meson-gx-hhi-sysctrl.yaml
index 16977e4..c6bce40 100644
--- a/dts/upstream/Bindings/soc/amlogic/amlogic,meson-gx-hhi-sysctrl.yaml
+++ b/dts/upstream/Bindings/soc/amlogic/amlogic,meson-gx-hhi-sysctrl.yaml
@@ -158,3 +158,36 @@
};
};
};
+
+ - |
+ system-controller@ff63c000 {
+ compatible = "amlogic,meson-axg-hhi-sysctrl", "simple-mfd", "syscon";
+ reg = <0xff63c000 0x400>;
+
+ clock-controller {
+ compatible = "amlogic,axg-clkc";
+ #clock-cells = <1>;
+ clocks = <&xtal>;
+ clock-names = "xtal";
+ };
+
+ power-controller {
+ compatible = "amlogic,meson-axg-pwrc";
+ #power-domain-cells = <1>;
+ amlogic,ao-sysctrl = <&sysctrl_AO>;
+
+ resets = <&reset_viu>,
+ <&reset_venc>,
+ <&reset_vcbus>,
+ <&reset_vencl>,
+ <&reset_vid_lock>;
+ reset-names = "viu", "venc", "vcbus", "vencl", "vid_lock";
+ clocks = <&clk_vpu>, <&clk_vapb>;
+ clock-names = "vpu", "vapb";
+ };
+
+ phy {
+ compatible = "amlogic,axg-mipi-pcie-analog-phy";
+ #phy-cells = <0>;
+ };
+ };
diff --git a/dts/upstream/Bindings/soc/mediatek/mediatek,pwrap.yaml b/dts/upstream/Bindings/soc/mediatek/mediatek,pwrap.yaml
index a06ac21..4737e5f 100644
--- a/dts/upstream/Bindings/soc/mediatek/mediatek,pwrap.yaml
+++ b/dts/upstream/Bindings/soc/mediatek/mediatek,pwrap.yaml
@@ -41,7 +41,6 @@
- mediatek,mt8173-pwrap
- mediatek,mt8183-pwrap
- mediatek,mt8186-pwrap
- - mediatek,mt8188-pwrap
- mediatek,mt8195-pwrap
- mediatek,mt8365-pwrap
- mediatek,mt8516-pwrap
@@ -50,6 +49,11 @@
- mediatek,mt8186-pwrap
- mediatek,mt8195-pwrap
- const: syscon
+ - items:
+ - enum:
+ - mediatek,mt8188-pwrap
+ - const: mediatek,mt8195-pwrap
+ - const: syscon
reg:
minItems: 1
diff --git a/dts/upstream/Bindings/soc/mediatek/mtk-svs.yaml b/dts/upstream/Bindings/soc/mediatek/mtk-svs.yaml
index 7eda63d..742b91d 100644
--- a/dts/upstream/Bindings/soc/mediatek/mtk-svs.yaml
+++ b/dts/upstream/Bindings/soc/mediatek/mtk-svs.yaml
@@ -22,8 +22,10 @@
compatible:
enum:
- mediatek,mt8183-svs
+ - mediatek,mt8186-svs
- mediatek,mt8188-svs
- mediatek,mt8192-svs
+ - mediatek,mt8195-svs
reg:
maxItems: 1
diff --git a/dts/upstream/Bindings/soc/microchip/microchip,mpfs-sys-controller.yaml b/dts/upstream/Bindings/soc/microchip/microchip,mpfs-sys-controller.yaml
index 365a9fe..a3fa04f 100644
--- a/dts/upstream/Bindings/soc/microchip/microchip,mpfs-sys-controller.yaml
+++ b/dts/upstream/Bindings/soc/microchip/microchip,mpfs-sys-controller.yaml
@@ -26,6 +26,16 @@
compatible:
const: microchip,mpfs-sys-controller
+ microchip,bitstream-flash:
+ $ref: /schemas/types.yaml#/definitions/phandle
+ description:
+ The SPI flash connected to the system controller's QSPI controller.
+ The system controller may retrieve FPGA bitstreams from this flash to
+ perform In-Application Programming (IAP) or during device initialisation
+ for Auto Update. The MSS and system controller have separate QSPI
+ controllers and this flash is connected to both. Software running in the
+ MSS can write bitstreams to the flash.
+
required:
- compatible
- mboxes
diff --git a/dts/upstream/Bindings/soc/qcom/qcom,aoss-qmp.yaml b/dts/upstream/Bindings/soc/qcom/qcom,aoss-qmp.yaml
index d1c7c2b..b4478f4 100644
--- a/dts/upstream/Bindings/soc/qcom/qcom,aoss-qmp.yaml
+++ b/dts/upstream/Bindings/soc/qcom/qcom,aoss-qmp.yaml
@@ -38,6 +38,8 @@
- qcom,sm8350-aoss-qmp
- qcom,sm8450-aoss-qmp
- qcom,sm8550-aoss-qmp
+ - qcom,sm8650-aoss-qmp
+ - qcom,x1e80100-aoss-qmp
- const: qcom,aoss-qmp
reg:
diff --git a/dts/upstream/Bindings/soc/qcom/qcom,pmic-glink.yaml b/dts/upstream/Bindings/soc/qcom/qcom,pmic-glink.yaml
index 422921c..61df97f 100644
--- a/dts/upstream/Bindings/soc/qcom/qcom,pmic-glink.yaml
+++ b/dts/upstream/Bindings/soc/qcom/qcom,pmic-glink.yaml
@@ -20,14 +20,20 @@
properties:
compatible:
- items:
- - enum:
- - qcom,sc8180x-pmic-glink
- - qcom,sc8280xp-pmic-glink
- - qcom,sm8350-pmic-glink
- - qcom,sm8450-pmic-glink
- - qcom,sm8550-pmic-glink
- - const: qcom,pmic-glink
+ oneOf:
+ - items:
+ - enum:
+ - qcom,sc8180x-pmic-glink
+ - qcom,sc8280xp-pmic-glink
+ - qcom,sm8350-pmic-glink
+ - qcom,sm8450-pmic-glink
+ - qcom,sm8550-pmic-glink
+ - const: qcom,pmic-glink
+ - items:
+ - enum:
+ - qcom,sm8650-pmic-glink
+ - const: qcom,sm8550-pmic-glink
+ - const: qcom,pmic-glink
'#address-cells':
const: 1
diff --git a/dts/upstream/Bindings/soc/qcom/qcom-stats.yaml b/dts/upstream/Bindings/soc/qcom/qcom-stats.yaml
index 96a7f18..686a7ef 100644
--- a/dts/upstream/Bindings/soc/qcom/qcom-stats.yaml
+++ b/dts/upstream/Bindings/soc/qcom/qcom-stats.yaml
@@ -31,10 +31,24 @@
reg:
maxItems: 1
+ qcom,qmp:
+ $ref: /schemas/types.yaml#/definitions/phandle
+ description: Reference to the AOSS side-channel message RAM
+
required:
- compatible
- reg
+allOf:
+ - if:
+ not:
+ properties:
+ compatible:
+ const: qcom,rpmh-stats
+ then:
+ properties:
+ qcom,qmp: false
+
additionalProperties: false
examples:
diff --git a/dts/upstream/Bindings/soc/rockchip/grf.yaml b/dts/upstream/Bindings/soc/rockchip/grf.yaml
index 1309bf5..9793ea6 100644
--- a/dts/upstream/Bindings/soc/rockchip/grf.yaml
+++ b/dts/upstream/Bindings/soc/rockchip/grf.yaml
@@ -28,6 +28,8 @@
- rockchip,rk3588-sys-grf
- rockchip,rk3588-pcie3-phy-grf
- rockchip,rk3588-pcie3-pipe-grf
+ - rockchip,rk3588-vo-grf
+ - rockchip,rk3588-vop-grf
- rockchip,rv1108-usbgrf
- const: syscon
- items:
diff --git a/dts/upstream/Bindings/soc/samsung/exynos-pmu.yaml b/dts/upstream/Bindings/soc/samsung/exynos-pmu.yaml
index e1d716d..15fcd8f 100644
--- a/dts/upstream/Bindings/soc/samsung/exynos-pmu.yaml
+++ b/dts/upstream/Bindings/soc/samsung/exynos-pmu.yaml
@@ -15,6 +15,7 @@
compatible:
contains:
enum:
+ - google,gs101-pmu
- samsung,exynos3250-pmu
- samsung,exynos4210-pmu
- samsung,exynos4212-pmu
@@ -35,6 +36,7 @@
oneOf:
- items:
- enum:
+ - google,gs101-pmu
- samsung,exynos3250-pmu
- samsung,exynos4210-pmu
- samsung,exynos4212-pmu
@@ -50,6 +52,14 @@
- const: syscon
- items:
- enum:
+ - samsung,exynos7885-pmu
+ - samsung,exynosautov9-pmu
+ - samsung,exynosautov920-pmu
+ - tesla,fsd-pmu
+ - const: samsung,exynos7-pmu
+ - const: syscon
+ - items:
+ - enum:
- samsung,exynos3250-pmu
- samsung,exynos4210-pmu
- samsung,exynos4212-pmu
diff --git a/dts/upstream/Bindings/soc/samsung/exynos-usi.yaml b/dts/upstream/Bindings/soc/samsung/exynos-usi.yaml
index a683690..8b478d6 100644
--- a/dts/upstream/Bindings/soc/samsung/exynos-usi.yaml
+++ b/dts/upstream/Bindings/soc/samsung/exynos-usi.yaml
@@ -24,7 +24,10 @@
compatible:
oneOf:
- items:
- - const: samsung,exynosautov9-usi
+ - enum:
+ - google,gs101-usi
+ - samsung,exynosautov9-usi
+ - samsung,exynosautov920-usi
- const: samsung,exynos850-usi
- enum:
- samsung,exynos850-usi
@@ -155,7 +158,7 @@
};
hsi2c_0: i2c@13820000 {
- compatible = "samsung,exynosautov9-hsi2c";
+ compatible = "samsung,exynos850-hsi2c", "samsung,exynosautov9-hsi2c";
reg = <0x13820000 0xc0>;
interrupts = <GIC_SPI 227 IRQ_TYPE_LEVEL_HIGH>;
#address-cells = <1>;
diff --git a/dts/upstream/Bindings/soc/samsung/samsung,exynos-sysreg.yaml b/dts/upstream/Bindings/soc/samsung/samsung,exynos-sysreg.yaml
index 163e912..1794e37 100644
--- a/dts/upstream/Bindings/soc/samsung/samsung,exynos-sysreg.yaml
+++ b/dts/upstream/Bindings/soc/samsung/samsung,exynos-sysreg.yaml
@@ -14,9 +14,14 @@
oneOf:
- items:
- enum:
+ - google,gs101-apm-sysreg
+ - google,gs101-peric0-sysreg
+ - google,gs101-peric1-sysreg
- samsung,exynos3-sysreg
- samsung,exynos4-sysreg
- samsung,exynos5-sysreg
+ - samsung,exynosautov920-peric0-sysreg
+ - samsung,exynosautov920-peric1-sysreg
- tesla,fsd-cam-sysreg
- tesla,fsd-fsys0-sysreg
- tesla,fsd-fsys1-sysreg
diff --git a/dts/upstream/Bindings/arm/xilinx.yaml b/dts/upstream/Bindings/soc/xilinx/xilinx.yaml
similarity index 95%
rename from dts/upstream/Bindings/arm/xilinx.yaml
rename to dts/upstream/Bindings/soc/xilinx/xilinx.yaml
index f57ed03..d4c0fe1 100644
--- a/dts/upstream/Bindings/arm/xilinx.yaml
+++ b/dts/upstream/Bindings/soc/xilinx/xilinx.yaml
@@ -1,7 +1,7 @@
# SPDX-License-Identifier: GPL-2.0
%YAML 1.2
---
-$id: http://devicetree.org/schemas/arm/xilinx.yaml#
+$id: http://devicetree.org/schemas/soc/xilinx/xilinx.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Xilinx Zynq Platforms
@@ -132,6 +132,11 @@
- const: xlnx,zynqmp-smk-k26
- const: xlnx,zynqmp
+ - description: AMD MicroBlaze V (QEMU)
+ items:
+ - const: qemu,mbv
+ - const: amd,mbv
+
additionalProperties: true
...
diff --git a/dts/upstream/Bindings/sound/adi,max98363.yaml b/dts/upstream/Bindings/sound/adi,max98363.yaml
index a844b63..c388cda 100644
--- a/dts/upstream/Bindings/sound/adi,max98363.yaml
+++ b/dts/upstream/Bindings/sound/adi,max98363.yaml
@@ -39,7 +39,7 @@
examples:
- |
- soundwire-controller@3250000 {
+ soundwire@3250000 {
#address-cells = <2>;
#size-cells = <0>;
reg = <0x3250000 0x2000>;
diff --git a/dts/upstream/Bindings/sound/allwinner,sun4i-a10-spdif.yaml b/dts/upstream/Bindings/sound/allwinner,sun4i-a10-spdif.yaml
index 8108c56..aa32dc9 100644
--- a/dts/upstream/Bindings/sound/allwinner,sun4i-a10-spdif.yaml
+++ b/dts/upstream/Bindings/sound/allwinner,sun4i-a10-spdif.yaml
@@ -22,6 +22,7 @@
- const: allwinner,sun6i-a31-spdif
- const: allwinner,sun8i-h3-spdif
- const: allwinner,sun50i-h6-spdif
+ - const: allwinner,sun50i-h616-spdif
- items:
- const: allwinner,sun8i-a83t-spdif
- const: allwinner,sun8i-h3-spdif
@@ -62,6 +63,8 @@
enum:
- allwinner,sun6i-a31-spdif
- allwinner,sun8i-h3-spdif
+ - allwinner,sun50i-h6-spdif
+ - allwinner,sun50i-h616-spdif
then:
required:
@@ -73,7 +76,7 @@
contains:
enum:
- allwinner,sun8i-h3-spdif
- - allwinner,sun50i-h6-spdif
+ - allwinner,sun50i-h616-spdif
then:
properties:
diff --git a/dts/upstream/Bindings/sound/audio-graph-port.yaml b/dts/upstream/Bindings/sound/audio-graph-port.yaml
index 60b5e3f..b13c08d 100644
--- a/dts/upstream/Bindings/sound/audio-graph-port.yaml
+++ b/dts/upstream/Bindings/sound/audio-graph-port.yaml
@@ -19,6 +19,12 @@
properties:
mclk-fs:
$ref: simple-card.yaml#/definitions/mclk-fs
+ playback-only:
+ description: port connection used only for playback
+ $ref: /schemas/types.yaml#/definitions/flag
+ capture-only:
+ description: port connection used only for capture
+ $ref: /schemas/types.yaml#/definitions/flag
endpoint-base:
allOf:
diff --git a/dts/upstream/Bindings/sound/es8328.txt b/dts/upstream/Bindings/sound/es8328.txt
deleted file mode 100644
index 33fbf05..0000000
--- a/dts/upstream/Bindings/sound/es8328.txt
+++ /dev/null
@@ -1,38 +0,0 @@
-Everest ES8328 audio CODEC
-
-This device supports both I2C and SPI.
-
-Required properties:
-
- - compatible : Should be "everest,es8328" or "everest,es8388"
- - DVDD-supply : Regulator providing digital core supply voltage 1.8 - 3.6V
- - AVDD-supply : Regulator providing analog supply voltage 3.3V
- - PVDD-supply : Regulator providing digital IO supply voltage 1.8 - 3.6V
- - IPVDD-supply : Regulator providing analog output voltage 3.3V
- - clocks : A 22.5792 or 11.2896 MHz clock
- - reg : the I2C address of the device for I2C, the chip select number for SPI
-
-Pins on the device (for linking into audio routes):
-
- * LOUT1
- * LOUT2
- * ROUT1
- * ROUT2
- * LINPUT1
- * RINPUT1
- * LINPUT2
- * RINPUT2
- * Mic Bias
-
-
-Example:
-
-codec: es8328@11 {
- compatible = "everest,es8328";
- DVDD-supply = <®_3p3v>;
- AVDD-supply = <®_3p3v>;
- PVDD-supply = <®_3p3v>;
- HPVDD-supply = <®_3p3v>;
- clocks = <&clks 169>;
- reg = <0x11>;
-};
diff --git a/dts/upstream/Bindings/sound/everest,es8328.yaml b/dts/upstream/Bindings/sound/everest,es8328.yaml
new file mode 100644
index 0000000..a0f4670
--- /dev/null
+++ b/dts/upstream/Bindings/sound/everest,es8328.yaml
@@ -0,0 +1,77 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/sound/everest,es8328.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Everest ES8328 audio CODEC
+
+description:
+ Everest Audio Codec, which can be connected via I2C or SPI.
+ Pins on the device (for linking into audio routes) are
+ * LOUT1
+ * LOUT2
+ * ROUT1
+ * ROUT2
+ * LINPUT1
+ * RINPUT1
+ * LINPUT2
+ * RINPUT2
+ * Mic Bias
+
+maintainers:
+ - David Yang <yangxiaohua@everest-semi.com>
+
+properties:
+ compatible:
+ enum:
+ - everest,es8328
+ - everest,es8388
+
+ reg:
+ maxItems: 1
+
+ "#sound-dai-cells":
+ const: 0
+
+ clocks:
+ items:
+ - description: A 22.5792 or 11.2896 MHz clock
+
+ DVDD-supply:
+ description: Regulator providing digital core supply voltage 1.8 - 3.6V
+
+ AVDD-supply:
+ description: Regulator providing analog supply voltage 3.3V
+
+ PVDD-supply:
+ description: Regulator providing digital IO supply voltage 1.8 - 3.6V
+
+ HPVDD-supply:
+ description: Regulator providing analog output voltage 3.3V
+
+required:
+ - compatible
+ - clocks
+ - DVDD-supply
+ - AVDD-supply
+ - PVDD-supply
+ - HPVDD-supply
+
+additionalProperties: false
+
+examples:
+ - |
+ i2c {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ es8328: codec@11 {
+ compatible = "everest,es8328";
+ reg = <0x11>;
+ AVDD-supply = <®_3p3v>;
+ DVDD-supply = <®_3p3v>;
+ HPVDD-supply = <®_3p3v>;
+ PVDD-supply = <®_3p3v>;
+ clocks = <&clks 169>;
+ };
+ };
diff --git a/dts/upstream/Bindings/sound/fsl,mqs.txt b/dts/upstream/Bindings/sound/fsl,mqs.txt
deleted file mode 100644
index d66284b..0000000
--- a/dts/upstream/Bindings/sound/fsl,mqs.txt
+++ /dev/null
@@ -1,36 +0,0 @@
-fsl,mqs audio CODEC
-
-Required properties:
- - compatible : Must contain one of "fsl,imx6sx-mqs", "fsl,codec-mqs"
- "fsl,imx8qm-mqs", "fsl,imx8qxp-mqs", "fsl,imx93-mqs".
- - clocks : A list of phandles + clock-specifiers, one for each entry in
- clock-names
- - clock-names : "mclk" - must required.
- "core" - required if compatible is "fsl,imx8qm-mqs", it
- is for register access.
- - gpr : A phandle of General Purpose Registers in IOMUX Controller.
- Required if compatible is "fsl,imx6sx-mqs".
-
-Required if compatible is "fsl,imx8qm-mqs":
- - power-domains: A phandle of PM domain provider node.
- - reg: Offset and length of the register set for the device.
-
-Example:
-
-mqs: mqs {
- compatible = "fsl,imx6sx-mqs";
- gpr = <&gpr>;
- clocks = <&clks IMX6SX_CLK_SAI1>;
- clock-names = "mclk";
- status = "disabled";
-};
-
-mqs: mqs@59850000 {
- compatible = "fsl,imx8qm-mqs";
- reg = <0x59850000 0x10000>;
- clocks = <&clk IMX8QM_AUD_MQS_IPG>,
- <&clk IMX8QM_AUD_MQS_HMCLK>;
- clock-names = "core", "mclk";
- power-domains = <&pd_mqs0>;
- status = "disabled";
-};
diff --git a/dts/upstream/Bindings/sound/fsl,mqs.yaml b/dts/upstream/Bindings/sound/fsl,mqs.yaml
new file mode 100644
index 0000000..8b33353
--- /dev/null
+++ b/dts/upstream/Bindings/sound/fsl,mqs.yaml
@@ -0,0 +1,105 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/sound/fsl,mqs.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: NXP Medium Quality Sound (MQS)
+
+maintainers:
+ - Shengjiu Wang <shengjiu.wang@nxp.com>
+ - Chancel Liu <chancel.liu@nxp.com>
+
+description: |
+ Medium quality sound (MQS) is used to generate medium quality audio
+ via a standard GPIO in the pinmux, allowing the user to connect
+ stereo speakers or headphones to a power amplifier without an
+ additional DAC chip.
+
+properties:
+ compatible:
+ enum:
+ - fsl,imx6sx-mqs
+ - fsl,imx8qm-mqs
+ - fsl,imx8qxp-mqs
+ - fsl,imx93-mqs
+
+ clocks:
+ minItems: 1
+ maxItems: 2
+
+ clock-names:
+ minItems: 1
+ maxItems: 2
+
+ gpr:
+ $ref: /schemas/types.yaml#/definitions/phandle
+ description: The phandle to the General Purpose Register (GPR) node
+
+ reg:
+ maxItems: 1
+
+ power-domains:
+ maxItems: 1
+
+ resets:
+ maxItems: 1
+
+required:
+ - compatible
+ - clocks
+ - clock-names
+
+allOf:
+ - if:
+ properties:
+ compatible:
+ contains:
+ enum:
+ - fsl,imx8qm-mqs
+ - fsl,imx8qxp-mqs
+ then:
+ properties:
+ clocks:
+ items:
+ - description: Master clock
+ - description: Clock for register access
+ clock-names:
+ items:
+ - const: mclk
+ - const: core
+ required:
+ - reg
+ - power-domains
+ else:
+ properties:
+ clocks:
+ items:
+ - description: Master clock
+ clock-names:
+ items:
+ - const: mclk
+ required:
+ - gpr
+
+additionalProperties: false
+
+examples:
+ - |
+ #include <dt-bindings/clock/imx6sx-clock.h>
+ mqs0: mqs {
+ compatible = "fsl,imx6sx-mqs";
+ gpr = <&gpr>;
+ clocks = <&clks IMX6SX_CLK_SAI1>;
+ clock-names = "mclk";
+ };
+
+ - |
+ #include <dt-bindings/firmware/imx/rsrc.h>
+ mqs1: mqs@59850000 {
+ compatible = "fsl,imx8qm-mqs";
+ reg = <0x59850000 0x10000>;
+ clocks = <&mqs0_lpcg 0>, <&mqs0_lpcg 1>;
+ clock-names = "mclk", "core";
+ power-domains = <&pd IMX_SC_R_MQS_0>;
+ };
diff --git a/dts/upstream/Bindings/sound/fsl,xcvr.yaml b/dts/upstream/Bindings/sound/fsl,xcvr.yaml
index 799b362..0eb0c1b 100644
--- a/dts/upstream/Bindings/sound/fsl,xcvr.yaml
+++ b/dts/upstream/Bindings/sound/fsl,xcvr.yaml
@@ -38,7 +38,10 @@
- const: txfifo
interrupts:
- maxItems: 1
+ items:
+ - description: WAKEUPMIX Audio XCVR Interrupt 1
+ - description: WAKEUPMIX Audio XCVR Interrupt 2
+ minItems: 1
clocks:
items:
@@ -78,6 +81,23 @@
- dma-names
- resets
+allOf:
+ - if:
+ properties:
+ compatible:
+ contains:
+ enum:
+ - fsl,imx93-xcvr
+ then:
+ properties:
+ interrupts:
+ minItems: 2
+ maxItems: 2
+ else:
+ properties:
+ interrupts:
+ maxItems: 1
+
additionalProperties: false
examples:
diff --git a/dts/upstream/Bindings/sound/google,sc7280-herobrine.yaml b/dts/upstream/Bindings/sound/google,sc7280-herobrine.yaml
index ec4b6e5..cdcd7c6 100644
--- a/dts/upstream/Bindings/sound/google,sc7280-herobrine.yaml
+++ b/dts/upstream/Bindings/sound/google,sc7280-herobrine.yaml
@@ -7,7 +7,6 @@
title: Google SC7280-Herobrine ASoC sound card driver
maintainers:
- - Srinivasa Rao Mandadapu <srivasam@codeaurora.org>
- Judy Hsiao <judyhsiao@chromium.org>
description:
diff --git a/dts/upstream/Bindings/sound/mediatek,mt2701-audio.yaml b/dts/upstream/Bindings/sound/mediatek,mt2701-audio.yaml
new file mode 100644
index 0000000..45382c4
--- /dev/null
+++ b/dts/upstream/Bindings/sound/mediatek,mt2701-audio.yaml
@@ -0,0 +1,116 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/sound/mediatek,mt2701-audio.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: MediaTek Audio Front End (AFE) PCM controller for mt2701
+
+description:
+ The AFE PCM node must be a subnode of the MediaTek audsys device tree node.
+
+maintainers:
+ - Eugen Hristev <eugen.hristev@collabora.com>
+
+properties:
+ compatible:
+ enum:
+ - mediatek,mt2701-audio
+ - mediatek,mt7622-audio
+
+ interrupts:
+ items:
+ - description: AFE interrupt
+ - description: ASYS interrupt
+
+ interrupt-names:
+ items:
+ - const: afe
+ - const: asys
+
+ power-domains:
+ maxItems: 1
+
+ clocks:
+ items:
+ - description: audio infra sys clock
+ - description: top audio mux 1
+ - description: top audio mux 2
+ - description: top audio sys a1 clock
+ - description: top audio sys a2 clock
+ - description: i2s0 source selection
+ - description: i2s1 source selection
+ - description: i2s2 source selection
+ - description: i2s3 source selection
+ - description: i2s0 source divider
+ - description: i2s1 source divider
+ - description: i2s2 source divider
+ - description: i2s3 source divider
+ - description: i2s0 master clock
+ - description: i2s1 master clock
+ - description: i2s2 master clock
+ - description: i2s3 master clock
+ - description: i2so0 hopping clock
+ - description: i2so1 hopping clock
+ - description: i2so2 hopping clock
+ - description: i2so3 hopping clock
+ - description: i2si0 hopping clock
+ - description: i2si1 hopping clock
+ - description: i2si2 hopping clock
+ - description: i2si3 hopping clock
+ - description: asrc0 output clock
+ - description: asrc1 output clock
+ - description: asrc2 output clock
+ - description: asrc3 output clock
+ - description: audio front end pd clock
+ - description: audio front end conn pd clock
+ - description: top audio a1 sys pd
+ - description: top audio a2 sys pd
+ - description: audio merge interface pd
+
+ clock-names:
+ items:
+ - const: infra_sys_audio_clk
+ - const: top_audio_mux1_sel
+ - const: top_audio_mux2_sel
+ - const: top_audio_a1sys_hp
+ - const: top_audio_a2sys_hp
+ - const: i2s0_src_sel
+ - const: i2s1_src_sel
+ - const: i2s2_src_sel
+ - const: i2s3_src_sel
+ - const: i2s0_src_div
+ - const: i2s1_src_div
+ - const: i2s2_src_div
+ - const: i2s3_src_div
+ - const: i2s0_mclk_en
+ - const: i2s1_mclk_en
+ - const: i2s2_mclk_en
+ - const: i2s3_mclk_en
+ - const: i2so0_hop_ck
+ - const: i2so1_hop_ck
+ - const: i2so2_hop_ck
+ - const: i2so3_hop_ck
+ - const: i2si0_hop_ck
+ - const: i2si1_hop_ck
+ - const: i2si2_hop_ck
+ - const: i2si3_hop_ck
+ - const: asrc0_out_ck
+ - const: asrc1_out_ck
+ - const: asrc2_out_ck
+ - const: asrc3_out_ck
+ - const: audio_afe_pd
+ - const: audio_afe_conn_pd
+ - const: audio_a1sys_pd
+ - const: audio_a2sys_pd
+ - const: audio_mrgif_pd
+
+required:
+ - compatible
+ - interrupts
+ - interrupt-names
+ - power-domains
+ - clocks
+ - clock-names
+
+additionalProperties: false
diff --git a/dts/upstream/Bindings/sound/mediatek,mt8188-mt6359.yaml b/dts/upstream/Bindings/sound/mediatek,mt8188-mt6359.yaml
index 4c8c950..f94ad07 100644
--- a/dts/upstream/Bindings/sound/mediatek,mt8188-mt6359.yaml
+++ b/dts/upstream/Bindings/sound/mediatek,mt8188-mt6359.yaml
@@ -15,6 +15,7 @@
properties:
compatible:
enum:
+ - mediatek,mt8188-es8326
- mediatek,mt8188-mt6359-evb
- mediatek,mt8188-nau8825
- mediatek,mt8188-rt5682s
diff --git a/dts/upstream/Bindings/sound/mt2701-afe-pcm.txt b/dts/upstream/Bindings/sound/mt2701-afe-pcm.txt
deleted file mode 100644
index f548e6a..0000000
--- a/dts/upstream/Bindings/sound/mt2701-afe-pcm.txt
+++ /dev/null
@@ -1,146 +0,0 @@
-Mediatek AFE PCM controller for mt2701
-
-Required properties:
-- compatible: should be one of the following.
- - "mediatek,mt2701-audio"
- - "mediatek,mt7622-audio"
-- interrupts: should contain AFE and ASYS interrupts
-- interrupt-names: should be "afe" and "asys"
-- power-domains: should define the power domain
-- clocks: Must contain an entry for each entry in clock-names
- See ../clocks/clock-bindings.txt for details
-- clock-names: should have these clock names:
- "infra_sys_audio_clk",
- "top_audio_mux1_sel",
- "top_audio_mux2_sel",
- "top_audio_a1sys_hp",
- "top_audio_a2sys_hp",
- "i2s0_src_sel",
- "i2s1_src_sel",
- "i2s2_src_sel",
- "i2s3_src_sel",
- "i2s0_src_div",
- "i2s1_src_div",
- "i2s2_src_div",
- "i2s3_src_div",
- "i2s0_mclk_en",
- "i2s1_mclk_en",
- "i2s2_mclk_en",
- "i2s3_mclk_en",
- "i2so0_hop_ck",
- "i2so1_hop_ck",
- "i2so2_hop_ck",
- "i2so3_hop_ck",
- "i2si0_hop_ck",
- "i2si1_hop_ck",
- "i2si2_hop_ck",
- "i2si3_hop_ck",
- "asrc0_out_ck",
- "asrc1_out_ck",
- "asrc2_out_ck",
- "asrc3_out_ck",
- "audio_afe_pd",
- "audio_afe_conn_pd",
- "audio_a1sys_pd",
- "audio_a2sys_pd",
- "audio_mrgif_pd";
-- assigned-clocks: list of input clocks and dividers for the audio system.
- See ../clocks/clock-bindings.txt for details.
-- assigned-clocks-parents: parent of input clocks of assigned clocks.
-- assigned-clock-rates: list of clock frequencies of assigned clocks.
-
-Must be a subnode of MediaTek audsys device tree node.
-See ../arm/mediatek/mediatek,audsys.txt for details about the parent node.
-
-Example:
-
- audsys: audio-subsystem@11220000 {
- compatible = "mediatek,mt2701-audsys", "syscon";
- ...
-
- afe: audio-controller {
- compatible = "mediatek,mt2701-audio";
- interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_LOW>,
- <GIC_SPI 132 IRQ_TYPE_LEVEL_LOW>;
- interrupt-names = "afe", "asys";
- power-domains = <&scpsys MT2701_POWER_DOMAIN_IFR_MSC>;
-
- clocks = <&infracfg CLK_INFRA_AUDIO>,
- <&topckgen CLK_TOP_AUD_MUX1_SEL>,
- <&topckgen CLK_TOP_AUD_MUX2_SEL>,
- <&topckgen CLK_TOP_AUD_48K_TIMING>,
- <&topckgen CLK_TOP_AUD_44K_TIMING>,
- <&topckgen CLK_TOP_AUD_K1_SRC_SEL>,
- <&topckgen CLK_TOP_AUD_K2_SRC_SEL>,
- <&topckgen CLK_TOP_AUD_K3_SRC_SEL>,
- <&topckgen CLK_TOP_AUD_K4_SRC_SEL>,
- <&topckgen CLK_TOP_AUD_K1_SRC_DIV>,
- <&topckgen CLK_TOP_AUD_K2_SRC_DIV>,
- <&topckgen CLK_TOP_AUD_K3_SRC_DIV>,
- <&topckgen CLK_TOP_AUD_K4_SRC_DIV>,
- <&topckgen CLK_TOP_AUD_I2S1_MCLK>,
- <&topckgen CLK_TOP_AUD_I2S2_MCLK>,
- <&topckgen CLK_TOP_AUD_I2S3_MCLK>,
- <&topckgen CLK_TOP_AUD_I2S4_MCLK>,
- <&audsys CLK_AUD_I2SO1>,
- <&audsys CLK_AUD_I2SO2>,
- <&audsys CLK_AUD_I2SO3>,
- <&audsys CLK_AUD_I2SO4>,
- <&audsys CLK_AUD_I2SIN1>,
- <&audsys CLK_AUD_I2SIN2>,
- <&audsys CLK_AUD_I2SIN3>,
- <&audsys CLK_AUD_I2SIN4>,
- <&audsys CLK_AUD_ASRCO1>,
- <&audsys CLK_AUD_ASRCO2>,
- <&audsys CLK_AUD_ASRCO3>,
- <&audsys CLK_AUD_ASRCO4>,
- <&audsys CLK_AUD_AFE>,
- <&audsys CLK_AUD_AFE_CONN>,
- <&audsys CLK_AUD_A1SYS>,
- <&audsys CLK_AUD_A2SYS>,
- <&audsys CLK_AUD_AFE_MRGIF>;
-
- clock-names = "infra_sys_audio_clk",
- "top_audio_mux1_sel",
- "top_audio_mux2_sel",
- "top_audio_a1sys_hp",
- "top_audio_a2sys_hp",
- "i2s0_src_sel",
- "i2s1_src_sel",
- "i2s2_src_sel",
- "i2s3_src_sel",
- "i2s0_src_div",
- "i2s1_src_div",
- "i2s2_src_div",
- "i2s3_src_div",
- "i2s0_mclk_en",
- "i2s1_mclk_en",
- "i2s2_mclk_en",
- "i2s3_mclk_en",
- "i2so0_hop_ck",
- "i2so1_hop_ck",
- "i2so2_hop_ck",
- "i2so3_hop_ck",
- "i2si0_hop_ck",
- "i2si1_hop_ck",
- "i2si2_hop_ck",
- "i2si3_hop_ck",
- "asrc0_out_ck",
- "asrc1_out_ck",
- "asrc2_out_ck",
- "asrc3_out_ck",
- "audio_afe_pd",
- "audio_afe_conn_pd",
- "audio_a1sys_pd",
- "audio_a2sys_pd",
- "audio_mrgif_pd";
-
- assigned-clocks = <&topckgen CLK_TOP_AUD_MUX1_SEL>,
- <&topckgen CLK_TOP_AUD_MUX2_SEL>,
- <&topckgen CLK_TOP_AUD_MUX1_DIV>,
- <&topckgen CLK_TOP_AUD_MUX2_DIV>;
- assigned-clock-parents = <&topckgen CLK_TOP_AUD1PLL_98M>,
- <&topckgen CLK_TOP_AUD2PLL_90M>;
- assigned-clock-rates = <0>, <0>, <49152000>, <45158400>;
- };
- };
diff --git a/dts/upstream/Bindings/sound/nuvoton,nau8821.yaml b/dts/upstream/Bindings/sound/nuvoton,nau8821.yaml
index 3e54abd..054b539 100644
--- a/dts/upstream/Bindings/sound/nuvoton,nau8821.yaml
+++ b/dts/upstream/Bindings/sound/nuvoton,nau8821.yaml
@@ -89,6 +89,14 @@
$ref: /schemas/types.yaml#/definitions/uint32
default: 3072000
+ nuvoton,dmic-slew-rate:
+ description: The range 0 to 7 represents the speed of DMIC slew rate.
+ The lowest value 0 means the slowest rate and the highest value
+ 7 means the fastest rate.
+ $ref: /schemas/types.yaml#/definitions/uint32
+ maximum: 7
+ default: 0
+
nuvoton,left-input-single-end:
description: Enable left input with single-ended settings if set.
For the headset mic application, the single-ended control is
@@ -127,6 +135,7 @@
nuvoton,jack-insert-debounce = <7>;
nuvoton,jack-eject-debounce = <0>;
nuvoton,dmic-clk-threshold = <3072000>;
+ nuvoton,dmic-slew-rate = <0>;
#sound-dai-cells = <0>;
};
};
diff --git a/dts/upstream/Bindings/sound/nvidia,tegra-audio-max9808x.yaml b/dts/upstream/Bindings/sound/nvidia,tegra-audio-max9808x.yaml
index c29d794..241d20f 100644
--- a/dts/upstream/Bindings/sound/nvidia,tegra-audio-max9808x.yaml
+++ b/dts/upstream/Bindings/sound/nvidia,tegra-audio-max9808x.yaml
@@ -64,7 +64,7 @@
#include <dt-bindings/clock/tegra30-car.h>
#include <dt-bindings/soc/tegra-pmc.h>
sound {
- compatible = "lge,tegra-audio-max98089-p895",
+ compatible = "lg,tegra-audio-max98089-p895",
"nvidia,tegra-audio-max98089";
nvidia,model = "LG Optimus Vu MAX98089";
diff --git a/dts/upstream/Bindings/sound/qcom,lpass-rx-macro.yaml b/dts/upstream/Bindings/sound/qcom,lpass-rx-macro.yaml
index ec4b0ac..b8540b3 100644
--- a/dts/upstream/Bindings/sound/qcom,lpass-rx-macro.yaml
+++ b/dts/upstream/Bindings/sound/qcom,lpass-rx-macro.yaml
@@ -11,12 +11,18 @@
properties:
compatible:
- enum:
- - qcom,sc7280-lpass-rx-macro
- - qcom,sm8250-lpass-rx-macro
- - qcom,sm8450-lpass-rx-macro
- - qcom,sm8550-lpass-rx-macro
- - qcom,sc8280xp-lpass-rx-macro
+ oneOf:
+ - enum:
+ - qcom,sc7280-lpass-rx-macro
+ - qcom,sm8250-lpass-rx-macro
+ - qcom,sm8450-lpass-rx-macro
+ - qcom,sm8550-lpass-rx-macro
+ - qcom,sc8280xp-lpass-rx-macro
+ - items:
+ - enum:
+ - qcom,sm8650-lpass-rx-macro
+ - qcom,x1e80100-lpass-rx-macro
+ - const: qcom,sm8550-lpass-rx-macro
reg:
maxItems: 1
@@ -96,8 +102,9 @@
- if:
properties:
compatible:
- enum:
- - qcom,sm8550-lpass-rx-macro
+ contains:
+ enum:
+ - qcom,sm8550-lpass-rx-macro
then:
properties:
clocks:
diff --git a/dts/upstream/Bindings/sound/qcom,lpass-tx-macro.yaml b/dts/upstream/Bindings/sound/qcom,lpass-tx-macro.yaml
index 962701e..3e2ae16 100644
--- a/dts/upstream/Bindings/sound/qcom,lpass-tx-macro.yaml
+++ b/dts/upstream/Bindings/sound/qcom,lpass-tx-macro.yaml
@@ -11,13 +11,19 @@
properties:
compatible:
- enum:
- - qcom,sc7280-lpass-tx-macro
- - qcom,sm6115-lpass-tx-macro
- - qcom,sm8250-lpass-tx-macro
- - qcom,sm8450-lpass-tx-macro
- - qcom,sm8550-lpass-tx-macro
- - qcom,sc8280xp-lpass-tx-macro
+ oneOf:
+ - enum:
+ - qcom,sc7280-lpass-tx-macro
+ - qcom,sm6115-lpass-tx-macro
+ - qcom,sm8250-lpass-tx-macro
+ - qcom,sm8450-lpass-tx-macro
+ - qcom,sm8550-lpass-tx-macro
+ - qcom,sc8280xp-lpass-tx-macro
+ - items:
+ - enum:
+ - qcom,sm8650-lpass-tx-macro
+ - qcom,x1e80100-lpass-tx-macro
+ - const: qcom,sm8550-lpass-tx-macro
reg:
maxItems: 1
@@ -118,8 +124,9 @@
- if:
properties:
compatible:
- enum:
- - qcom,sm8550-lpass-tx-macro
+ contains:
+ enum:
+ - qcom,sm8550-lpass-tx-macro
then:
properties:
clocks:
diff --git a/dts/upstream/Bindings/sound/qcom,lpass-va-macro.yaml b/dts/upstream/Bindings/sound/qcom,lpass-va-macro.yaml
index 4a56108..6b483fa 100644
--- a/dts/upstream/Bindings/sound/qcom,lpass-va-macro.yaml
+++ b/dts/upstream/Bindings/sound/qcom,lpass-va-macro.yaml
@@ -11,12 +11,18 @@
properties:
compatible:
- enum:
- - qcom,sc7280-lpass-va-macro
- - qcom,sm8250-lpass-va-macro
- - qcom,sm8450-lpass-va-macro
- - qcom,sm8550-lpass-va-macro
- - qcom,sc8280xp-lpass-va-macro
+ oneOf:
+ - enum:
+ - qcom,sc7280-lpass-va-macro
+ - qcom,sm8250-lpass-va-macro
+ - qcom,sm8450-lpass-va-macro
+ - qcom,sm8550-lpass-va-macro
+ - qcom,sc8280xp-lpass-va-macro
+ - items:
+ - enum:
+ - qcom,sm8650-lpass-va-macro
+ - qcom,x1e80100-lpass-va-macro
+ - const: qcom,sm8550-lpass-va-macro
reg:
maxItems: 1
diff --git a/dts/upstream/Bindings/sound/qcom,lpass-wsa-macro.yaml b/dts/upstream/Bindings/sound/qcom,lpass-wsa-macro.yaml
index eea7609..06b5f7b 100644
--- a/dts/upstream/Bindings/sound/qcom,lpass-wsa-macro.yaml
+++ b/dts/upstream/Bindings/sound/qcom,lpass-wsa-macro.yaml
@@ -11,12 +11,18 @@
properties:
compatible:
- enum:
- - qcom,sc7280-lpass-wsa-macro
- - qcom,sm8250-lpass-wsa-macro
- - qcom,sm8450-lpass-wsa-macro
- - qcom,sm8550-lpass-wsa-macro
- - qcom,sc8280xp-lpass-wsa-macro
+ oneOf:
+ - enum:
+ - qcom,sc7280-lpass-wsa-macro
+ - qcom,sm8250-lpass-wsa-macro
+ - qcom,sm8450-lpass-wsa-macro
+ - qcom,sm8550-lpass-wsa-macro
+ - qcom,sc8280xp-lpass-wsa-macro
+ - items:
+ - enum:
+ - qcom,sm8650-lpass-wsa-macro
+ - qcom,x1e80100-lpass-wsa-macro
+ - const: qcom,sm8550-lpass-wsa-macro
reg:
maxItems: 1
@@ -94,8 +100,9 @@
- if:
properties:
compatible:
- enum:
- - qcom,sm8550-lpass-wsa-macro
+ contains:
+ enum:
+ - qcom,sm8550-lpass-wsa-macro
then:
properties:
clocks:
diff --git a/dts/upstream/Bindings/sound/qcom,sm8250.yaml b/dts/upstream/Bindings/sound/qcom,sm8250.yaml
index e082a4f..6f41974 100644
--- a/dts/upstream/Bindings/sound/qcom,sm8250.yaml
+++ b/dts/upstream/Bindings/sound/qcom,sm8250.yaml
@@ -21,6 +21,11 @@
- lenovo,yoga-c630-sndcard
- qcom,db845c-sndcard
- const: qcom,sdm845-sndcard
+ - items:
+ - enum:
+ - qcom,sm8550-sndcard
+ - qcom,sm8650-sndcard
+ - const: qcom,sm8450-sndcard
- enum:
- qcom,apq8016-sbc-sndcard
- qcom,msm8916-qdsp6-sndcard
@@ -30,6 +35,7 @@
- qcom,sdm845-sndcard
- qcom,sm8250-sndcard
- qcom,sm8450-sndcard
+ - qcom,x1e80100-sndcard
audio-routing:
$ref: /schemas/types.yaml#/definitions/non-unique-string-array
diff --git a/dts/upstream/Bindings/sound/qcom,wcd934x.yaml b/dts/upstream/Bindings/sound/qcom,wcd934x.yaml
index 4df59f3..beb0ff0 100644
--- a/dts/upstream/Bindings/sound/qcom,wcd934x.yaml
+++ b/dts/upstream/Bindings/sound/qcom,wcd934x.yaml
@@ -201,9 +201,9 @@
- |
codec@1,0{
compatible = "slim217,250";
- reg = <1 0>;
+ reg = <1 0>;
reset-gpios = <&tlmm 64 0>;
- slim-ifc-dev = <&wcd9340_ifd>;
+ slim-ifc-dev = <&wcd9340_ifd>;
#sound-dai-cells = <1>;
interrupt-parent = <&tlmm>;
interrupts = <54 4>;
diff --git a/dts/upstream/Bindings/sound/qcom,wcd938x-sdw.yaml b/dts/upstream/Bindings/sound/qcom,wcd938x-sdw.yaml
index b430dd3..7b31bf9 100644
--- a/dts/upstream/Bindings/sound/qcom,wcd938x-sdw.yaml
+++ b/dts/upstream/Bindings/sound/qcom,wcd938x-sdw.yaml
@@ -51,7 +51,7 @@
reg = <0x03210000 0x2000>;
wcd938x_rx: codec@0,4 {
compatible = "sdw20217010d00";
- reg = <0 4>;
+ reg = <0 4>;
qcom,rx-port-mapping = <1 2 3 4 5>;
};
};
@@ -62,7 +62,7 @@
reg = <0x03230000 0x2000>;
wcd938x_tx: codec@0,3 {
compatible = "sdw20217010d00";
- reg = <0 3>;
+ reg = <0 3>;
qcom,tx-port-mapping = <2 3 4 5>;
};
};
diff --git a/dts/upstream/Bindings/sound/qcom,wcd938x.yaml b/dts/upstream/Bindings/sound/qcom,wcd938x.yaml
index 0185657..adbfa67 100644
--- a/dts/upstream/Bindings/sound/qcom,wcd938x.yaml
+++ b/dts/upstream/Bindings/sound/qcom,wcd938x.yaml
@@ -137,7 +137,7 @@
reg = <0x03210000 0x2000>;
wcd938x_rx: codec@0,4 {
compatible = "sdw20217010d00";
- reg = <0 4>;
+ reg = <0 4>;
qcom,rx-port-mapping = <1 2 3 4 5>;
};
};
@@ -148,7 +148,7 @@
reg = <0x03230000 0x2000>;
wcd938x_tx: codec@0,3 {
compatible = "sdw20217010d00";
- reg = <0 3>;
+ reg = <0 3>;
qcom,tx-port-mapping = <2 3 4 5>;
};
};
diff --git a/dts/upstream/Bindings/sound/qcom,wsa883x.yaml b/dts/upstream/Bindings/sound/qcom,wsa883x.yaml
index ba572a7..8e462cd 100644
--- a/dts/upstream/Bindings/sound/qcom,wsa883x.yaml
+++ b/dts/upstream/Bindings/sound/qcom,wsa883x.yaml
@@ -52,7 +52,7 @@
- |
#include <dt-bindings/gpio/gpio.h>
- soundwire-controller@3250000 {
+ soundwire@3250000 {
#address-cells = <2>;
#size-cells = <0>;
reg = <0x3250000 0x2000>;
diff --git a/dts/upstream/Bindings/sound/qcom,wsa8840.yaml b/dts/upstream/Bindings/sound/qcom,wsa8840.yaml
index e6723c9..d717017 100644
--- a/dts/upstream/Bindings/sound/qcom,wsa8840.yaml
+++ b/dts/upstream/Bindings/sound/qcom,wsa8840.yaml
@@ -48,7 +48,7 @@
- |
#include <dt-bindings/gpio/gpio.h>
- soundwire-controller {
+ soundwire {
#address-cells = <2>;
#size-cells = <0>;
diff --git a/dts/upstream/Bindings/sound/renesas,rsnd.yaml b/dts/upstream/Bindings/sound/renesas,rsnd.yaml
index 13a5a0a..0d7a6b5 100644
--- a/dts/upstream/Bindings/sound/renesas,rsnd.yaml
+++ b/dts/upstream/Bindings/sound/renesas,rsnd.yaml
@@ -9,20 +9,6 @@
maintainers:
- Kuninori Morimoto <kuninori.morimoto.gx@renesas.com>
-definitions:
- port-def:
- $ref: audio-graph-port.yaml#/definitions/port-base
- unevaluatedProperties: false
- patternProperties:
- "^endpoint(@[0-9a-f]+)?":
- $ref: audio-graph-port.yaml#/definitions/endpoint-base
- properties:
- playback:
- $ref: /schemas/types.yaml#/definitions/phandle-array
- capture:
- $ref: /schemas/types.yaml#/definitions/phandle-array
- unevaluatedProperties: false
-
properties:
compatible:
@@ -125,7 +111,17 @@
# ports is below
port:
- $ref: "#/definitions/port-def"
+ $ref: audio-graph-port.yaml#/definitions/port-base
+ unevaluatedProperties: false
+ patternProperties:
+ "^endpoint(@[0-9a-f]+)?":
+ $ref: audio-graph-port.yaml#/definitions/endpoint-base
+ properties:
+ playback:
+ $ref: /schemas/types.yaml#/definitions/phandle-array
+ capture:
+ $ref: /schemas/types.yaml#/definitions/phandle-array
+ unevaluatedProperties: false
rcar_sound,dvc:
description: DVC subnode.
@@ -269,7 +265,7 @@
unevaluatedProperties: false
patternProperties:
'^port(@[0-9a-f]+)?$':
- $ref: "#/definitions/port-def"
+ $ref: "#/properties/port"
required:
- compatible
@@ -501,19 +497,19 @@
rcar_sound,dai {
dai0 {
playback = <&ssi5>, <&src5>;
- capture = <&ssi6>;
+ capture = <&ssi6>;
};
dai1 {
playback = <&ssi3>;
};
dai2 {
- capture = <&ssi4>;
+ capture = <&ssi4>;
};
dai3 {
playback = <&ssi7>;
};
dai4 {
- capture = <&ssi8>;
+ capture = <&ssi8>;
};
};
@@ -527,7 +523,7 @@
frame-master = <&rsnd_endpoint0>;
playback = <&ssi0>, <&src0>, <&dvc0>;
- capture = <&ssi1>, <&src1>, <&dvc1>;
+ capture = <&ssi1>, <&src1>, <&dvc1>;
};
};
};
diff --git a/dts/upstream/Bindings/sound/renesas,rz-ssi.yaml b/dts/upstream/Bindings/sound/renesas,rz-ssi.yaml
index 3b5ae45..8b9695f 100644
--- a/dts/upstream/Bindings/sound/renesas,rz-ssi.yaml
+++ b/dts/upstream/Bindings/sound/renesas,rz-ssi.yaml
@@ -16,7 +16,7 @@
compatible:
items:
- enum:
- - renesas,r9a07g043-ssi # RZ/G2UL
+ - renesas,r9a07g043-ssi # RZ/G2UL and RZ/Five
- renesas,r9a07g044-ssi # RZ/G2{L,LC}
- renesas,r9a07g054-ssi # RZ/V2L
- const: renesas,rz-ssi
diff --git a/dts/upstream/Bindings/sound/samsung-i2s.yaml b/dts/upstream/Bindings/sound/samsung-i2s.yaml
index 30b3b6e..f45f73b 100644
--- a/dts/upstream/Bindings/sound/samsung-i2s.yaml
+++ b/dts/upstream/Bindings/sound/samsung-i2s.yaml
@@ -44,13 +44,18 @@
frequencies supported by Exynos7 I2S and 7.1 channel TDM support
for playback and capture TDM (Time division multiplexing) to allow
transfer of multiple channel audio data on single data line.
- enum:
- - samsung,s3c6410-i2s
- - samsung,s5pv210-i2s
- - samsung,exynos5420-i2s
- - samsung,exynos7-i2s
- - samsung,exynos7-i2s1
- - tesla,fsd-i2s
+ oneOf:
+ - enum:
+ - samsung,s3c6410-i2s
+ - samsung,s5pv210-i2s
+ - samsung,exynos5420-i2s
+ - samsung,exynos7-i2s
+ - samsung,exynos7-i2s1
+ - tesla,fsd-i2s
+ - items:
+ - enum:
+ - samsung,exynos5433-i2s
+ - const: samsung,exynos7-i2s
'#address-cells':
const: 1
diff --git a/dts/upstream/Bindings/sound/sound-card-common.yaml b/dts/upstream/Bindings/sound/sound-card-common.yaml
index 3a94117..721950f 100644
--- a/dts/upstream/Bindings/sound/sound-card-common.yaml
+++ b/dts/upstream/Bindings/sound/sound-card-common.yaml
@@ -17,6 +17,13 @@
pair of strings, the first being the connection's sink, the second
being the connection's source.
+ ignore-suspend-widgets:
+ $ref: /schemas/types.yaml#/definitions/non-unique-string-array
+ description: |
+ A list of audio sound widgets which are marked ignoring system suspend.
+ Paths between these endpoints are still active over suspend of the main
+ application processor that the current operating system is running.
+
model:
$ref: /schemas/types.yaml#/definitions/string
description: User specified audio sound card name
diff --git a/dts/upstream/Bindings/sound/tas2562.yaml b/dts/upstream/Bindings/sound/tas2562.yaml
index f01c0dd..d28c102 100644
--- a/dts/upstream/Bindings/sound/tas2562.yaml
+++ b/dts/upstream/Bindings/sound/tas2562.yaml
@@ -18,7 +18,6 @@
Specifications about the audio amplifier can be found at:
https://www.ti.com/lit/gpn/tas2562
- https://www.ti.com/lit/gpn/tas2563
https://www.ti.com/lit/gpn/tas2564
https://www.ti.com/lit/gpn/tas2110
@@ -29,7 +28,6 @@
compatible:
enum:
- ti,tas2562
- - ti,tas2563
- ti,tas2564
- ti,tas2110
diff --git a/dts/upstream/Bindings/sound/ti,tas2781.yaml b/dts/upstream/Bindings/sound/ti,tas2781.yaml
index a69e6c2..9762386 100644
--- a/dts/upstream/Bindings/sound/ti,tas2781.yaml
+++ b/dts/upstream/Bindings/sound/ti,tas2781.yaml
@@ -5,36 +5,46 @@
$id: http://devicetree.org/schemas/sound/ti,tas2781.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
-title: Texas Instruments TAS2781 SmartAMP
+title: Texas Instruments TAS2563/TAS2781 SmartAMP
maintainers:
- Shenghao Ding <shenghao-ding@ti.com>
-description:
- The TAS2781 is a mono, digital input Class-D audio amplifier
- optimized for efficiently driving high peak power into small
- loudspeakers. An integrated on-chip DSP supports Texas Instruments
- Smart Amp speaker protection algorithm. The integrated speaker
- voltage and current sense provides for real time
+description: |
+ The TAS2563/TAS2781 is a mono, digital input Class-D audio
+ amplifier optimized for efficiently driving high peak power into
+ small loudspeakers. An integrated on-chip DSP supports Texas
+ Instruments Smart Amp speaker protection algorithm. The
+ integrated speaker voltage and current sense provides for real time
monitoring of loudspeaker behavior.
-allOf:
- - $ref: dai-common.yaml#
+ Specifications about the audio amplifier can be found at:
+ https://www.ti.com/lit/gpn/tas2563
+ https://www.ti.com/lit/gpn/tas2781
properties:
compatible:
- enum:
- - ti,tas2781
+ description: |
+ ti,tas2563: 6.1-W Boosted Class-D Audio Amplifier With Integrated
+ DSP and IV Sense, 16/20/24/32bit stereo I2S or multichannel TDM.
+
+ ti,tas2781: 24-V Class-D Amplifier with Real Time Integrated Speaker
+ Protection and Audio Processing, 16/20/24/32bit stereo I2S or
+ multichannel TDM.
+ oneOf:
+ - items:
+ - enum:
+ - ti,tas2563
+ - const: ti,tas2781
+ - enum:
+ - ti,tas2781
reg:
description:
- I2C address, in multiple tas2781s case, all the i2c address
+ I2C address, in multiple-AMP case, all the i2c address
aggregate as one Audio Device to support multiple audio slots.
maxItems: 8
minItems: 1
- items:
- minimum: 0x38
- maximum: 0x3f
reset-gpios:
maxItems: 1
@@ -49,6 +59,44 @@
- compatible
- reg
+allOf:
+ - $ref: dai-common.yaml#
+ - if:
+ properties:
+ compatible:
+ contains:
+ enum:
+ - ti,tas2563
+ then:
+ properties:
+ reg:
+ description:
+ I2C address, in multiple-AMP case, all the i2c address
+ aggregate as one Audio Device to support multiple audio slots.
+ maxItems: 4
+ minItems: 1
+ items:
+ minimum: 0x4c
+ maximum: 0x4f
+
+ - if:
+ properties:
+ compatible:
+ contains:
+ enum:
+ - ti,tas2781
+ then:
+ properties:
+ reg:
+ description:
+ I2C address, in multiple-AMP case, all the i2c address
+ aggregate as one Audio Device to support multiple audio slots.
+ maxItems: 8
+ minItems: 1
+ items:
+ minimum: 0x38
+ maximum: 0x3f
+
additionalProperties: false
examples:
diff --git a/dts/upstream/Bindings/sound/ti,tlv320aic32x4.yaml b/dts/upstream/Bindings/sound/ti,tlv320aic32x4.yaml
index a7cc9aa..4783e6d 100644
--- a/dts/upstream/Bindings/sound/ti,tlv320aic32x4.yaml
+++ b/dts/upstream/Bindings/sound/ti,tlv320aic32x4.yaml
@@ -90,7 +90,7 @@
ldoin-supply = <®_3v3>;
clocks = <&clks 201>;
clock-names = "mclk";
- aic32x4-gpio-func= <
+ aic32x4-gpio-func = <
0xff /* AIC32X4_MFPX_DEFAULT_VALUE */
0xff /* AIC32X4_MFPX_DEFAULT_VALUE */
0x04 /* MFP3 AIC32X4_MFP3_GPIO_ENABLED */
diff --git a/dts/upstream/Bindings/spi/adi,axi-spi-engine.txt b/dts/upstream/Bindings/spi/adi,axi-spi-engine.txt
deleted file mode 100644
index 8a18d71..0000000
--- a/dts/upstream/Bindings/spi/adi,axi-spi-engine.txt
+++ /dev/null
@@ -1,31 +0,0 @@
-Analog Devices AXI SPI Engine controller Device Tree Bindings
-
-Required properties:
-- compatible : Must be "adi,axi-spi-engine-1.00.a""
-- reg : Physical base address and size of the register map.
-- interrupts : Property with a value describing the interrupt
- number.
-- clock-names : List of input clock names - "s_axi_aclk", "spi_clk"
-- clocks : Clock phandles and specifiers (See clock bindings for
- details on clock-names and clocks).
-- #address-cells : Must be <1>
-- #size-cells : Must be <0>
-
-Optional subnodes:
- Subnodes are use to represent the SPI slave devices connected to the SPI
- master. They follow the generic SPI bindings as outlined in spi-bus.txt.
-
-Example:
-
- spi@@44a00000 {
- compatible = "adi,axi-spi-engine-1.00.a";
- reg = <0x44a00000 0x1000>;
- interrupts = <0 56 4>;
- clocks = <&clkc 15 &clkc 15>;
- clock-names = "s_axi_aclk", "spi_clk";
-
- #address-cells = <1>;
- #size-cells = <0>;
-
- /* SPI devices */
- };
diff --git a/dts/upstream/Bindings/spi/adi,axi-spi-engine.yaml b/dts/upstream/Bindings/spi/adi,axi-spi-engine.yaml
new file mode 100644
index 0000000..d48faa4
--- /dev/null
+++ b/dts/upstream/Bindings/spi/adi,axi-spi-engine.yaml
@@ -0,0 +1,66 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/spi/adi,axi-spi-engine.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Analog Devices AXI SPI Engine Controller
+
+description: |
+ The AXI SPI Engine controller is part of the SPI Engine framework[1] and
+ allows memory mapped access to the SPI Engine control bus. This allows it
+ to be used as a general purpose software driven SPI controller as well as
+ some optional advanced acceleration and offloading capabilities.
+
+ [1] https://wiki.analog.com/resources/fpga/peripherals/spi_engine
+
+maintainers:
+ - Michael Hennerich <Michael.Hennerich@analog.com>
+ - Nuno Sá <nuno.sa@analog.com>
+
+allOf:
+ - $ref: /schemas/spi/spi-controller.yaml#
+
+properties:
+ compatible:
+ const: adi,axi-spi-engine-1.00.a
+
+ reg:
+ maxItems: 1
+
+ interrupts:
+ maxItems: 1
+
+ clocks:
+ items:
+ - description: The AXI interconnect clock.
+ - description: The SPI controller clock.
+
+ clock-names:
+ items:
+ - const: s_axi_aclk
+ - const: spi_clk
+
+required:
+ - compatible
+ - reg
+ - interrupts
+ - clocks
+ - clock-names
+
+unevaluatedProperties: false
+
+examples:
+ - |
+ spi@44a00000 {
+ compatible = "adi,axi-spi-engine-1.00.a";
+ reg = <0x44a00000 0x1000>;
+ interrupts = <0 56 4>;
+ clocks = <&clkc 15>, <&clkc 15>;
+ clock-names = "s_axi_aclk", "spi_clk";
+
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ /* SPI devices */
+ };
diff --git a/dts/upstream/Bindings/spi/renesas,rspi.yaml b/dts/upstream/Bindings/spi/renesas,rspi.yaml
index 4d8ec69..0ef3f84 100644
--- a/dts/upstream/Bindings/spi/renesas,rspi.yaml
+++ b/dts/upstream/Bindings/spi/renesas,rspi.yaml
@@ -21,7 +21,7 @@
- enum:
- renesas,rspi-r7s72100 # RZ/A1H
- renesas,rspi-r7s9210 # RZ/A2
- - renesas,r9a07g043-rspi # RZ/G2UL
+ - renesas,r9a07g043-rspi # RZ/G2UL and RZ/Five
- renesas,r9a07g044-rspi # RZ/G2{L,LC}
- renesas,r9a07g054-rspi # RZ/V2L
- const: renesas,rspi-rz
diff --git a/dts/upstream/Bindings/spi/snps,dw-apb-ssi.yaml b/dts/upstream/Bindings/spi/snps,dw-apb-ssi.yaml
index 6348a38..fde3776 100644
--- a/dts/upstream/Bindings/spi/snps,dw-apb-ssi.yaml
+++ b/dts/upstream/Bindings/spi/snps,dw-apb-ssi.yaml
@@ -72,8 +72,6 @@
- const: snps,dw-apb-ssi
- description: Intel Keem Bay SPI Controller
const: intel,keembay-ssi
- - description: Intel Thunder Bay SPI Controller
- const: intel,thunderbay-ssi
- description: Intel Mount Evans Integrated Management Complex SPI Controller
const: intel,mountevans-imc-ssi
- description: AMD Pensando Elba SoC SPI Controller
diff --git a/dts/upstream/Bindings/spi/st,stm32-spi.yaml b/dts/upstream/Bindings/spi/st,stm32-spi.yaml
index ae0f082..4bd9aeb 100644
--- a/dts/upstream/Bindings/spi/st,stm32-spi.yaml
+++ b/dts/upstream/Bindings/spi/st,stm32-spi.yaml
@@ -23,7 +23,9 @@
compatible:
enum:
- st,stm32f4-spi
+ - st,stm32f7-spi
- st,stm32h7-spi
+ - st,stm32mp25-spi
reg:
maxItems: 1
diff --git a/dts/upstream/Bindings/thermal/allwinner,sun8i-a83t-ths.yaml b/dts/upstream/Bindings/thermal/allwinner,sun8i-a83t-ths.yaml
index fbd4212..9b2272a 100644
--- a/dts/upstream/Bindings/thermal/allwinner,sun8i-a83t-ths.yaml
+++ b/dts/upstream/Bindings/thermal/allwinner,sun8i-a83t-ths.yaml
@@ -16,6 +16,7 @@
- allwinner,sun8i-a83t-ths
- allwinner,sun8i-h3-ths
- allwinner,sun8i-r40-ths
+ - allwinner,sun20i-d1-ths
- allwinner,sun50i-a64-ths
- allwinner,sun50i-a100-ths
- allwinner,sun50i-h5-ths
@@ -61,6 +62,7 @@
compatible:
contains:
enum:
+ - allwinner,sun20i-d1-ths
- allwinner,sun50i-a100-ths
- allwinner,sun50i-h6-ths
@@ -84,7 +86,9 @@
properties:
compatible:
contains:
- const: allwinner,sun8i-h3-ths
+ enum:
+ - allwinner,sun8i-h3-ths
+ - allwinner,sun20i-d1-ths
then:
properties:
@@ -103,6 +107,7 @@
enum:
- allwinner,sun8i-h3-ths
- allwinner,sun8i-r40-ths
+ - allwinner,sun20i-d1-ths
- allwinner,sun50i-a64-ths
- allwinner,sun50i-a100-ths
- allwinner,sun50i-h5-ths
diff --git a/dts/upstream/Bindings/thermal/loongson,ls2k-thermal.yaml b/dts/upstream/Bindings/thermal/loongson,ls2k-thermal.yaml
index 7538469..b634f57 100644
--- a/dts/upstream/Bindings/thermal/loongson,ls2k-thermal.yaml
+++ b/dts/upstream/Bindings/thermal/loongson,ls2k-thermal.yaml
@@ -10,6 +10,9 @@
- zhanghongchen <zhanghongchen@loongson.cn>
- Yinbo Zhu <zhuyinbo@loongson.cn>
+allOf:
+ - $ref: /schemas/thermal/thermal-sensor.yaml#
+
properties:
compatible:
oneOf:
@@ -26,12 +29,16 @@
interrupts:
maxItems: 1
+ '#thermal-sensor-cells':
+ const: 1
+
required:
- compatible
- reg
- interrupts
+ - '#thermal-sensor-cells'
-additionalProperties: false
+unevaluatedProperties: false
examples:
- |
@@ -41,4 +48,5 @@
reg = <0x1fe01500 0x30>;
interrupt-parent = <&liointc0>;
interrupts = <7 IRQ_TYPE_LEVEL_LOW>;
+ #thermal-sensor-cells = <1>;
};
diff --git a/dts/upstream/Bindings/thermal/mediatek,thermal.yaml b/dts/upstream/Bindings/thermal/mediatek,thermal.yaml
new file mode 100644
index 0000000..d96a2e3
--- /dev/null
+++ b/dts/upstream/Bindings/thermal/mediatek,thermal.yaml
@@ -0,0 +1,99 @@
+# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/thermal/mediatek,thermal.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Mediatek thermal controller for on-SoC temperatures
+
+maintainers:
+ - Sascha Hauer <s.hauer@pengutronix.de>
+
+description:
+ This device does not have its own ADC, instead it directly controls the AUXADC
+ via AHB bus accesses. For this reason it needs phandles to the AUXADC. Also it
+ controls a mux in the apmixedsys register space via AHB bus accesses, so a
+ phandle to the APMIXEDSYS is also needed.
+
+allOf:
+ - $ref: thermal-sensor.yaml#
+
+properties:
+ compatible:
+ enum:
+ - mediatek,mt2701-thermal
+ - mediatek,mt2712-thermal
+ - mediatek,mt7622-thermal
+ - mediatek,mt7981-thermal
+ - mediatek,mt7986-thermal
+ - mediatek,mt8173-thermal
+ - mediatek,mt8183-thermal
+ - mediatek,mt8365-thermal
+ - mediatek,mt8516-thermal
+
+ reg:
+ maxItems: 1
+
+ interrupts:
+ maxItems: 1
+
+ clocks:
+ items:
+ - description: Main clock needed for register access
+ - description: The AUXADC clock
+
+ clock-names:
+ items:
+ - const: therm
+ - const: auxadc
+
+ mediatek,auxadc:
+ $ref: /schemas/types.yaml#/definitions/phandle
+ description: A phandle to the AUXADC which the thermal controller uses
+
+ mediatek,apmixedsys:
+ $ref: /schemas/types.yaml#/definitions/phandle
+ description: A phandle to the APMIXEDSYS controller
+
+ resets:
+ description: Reset controller controlling the thermal controller
+
+ nvmem-cells:
+ items:
+ - description:
+ NVMEM cell with EEPROMA phandle to the calibration data provided by an
+ NVMEM device. If unspecified default values shall be used.
+
+ nvmem-cell-names:
+ items:
+ - const: calibration-data
+
+required:
+ - reg
+ - interrupts
+ - clocks
+ - clock-names
+ - mediatek,auxadc
+ - mediatek,apmixedsys
+
+unevaluatedProperties: false
+
+examples:
+ - |
+ #include <dt-bindings/interrupt-controller/irq.h>
+ #include <dt-bindings/clock/mt8173-clk.h>
+ #include <dt-bindings/reset/mt8173-resets.h>
+
+ thermal@1100b000 {
+ compatible = "mediatek,mt8173-thermal";
+ reg = <0x1100b000 0x1000>;
+ interrupts = <0 70 IRQ_TYPE_LEVEL_LOW>;
+ clocks = <&pericfg CLK_PERI_THERM>, <&pericfg CLK_PERI_AUXADC>;
+ clock-names = "therm", "auxadc";
+ resets = <&pericfg MT8173_PERI_THERM_SW_RST>;
+ mediatek,auxadc = <&auxadc>;
+ mediatek,apmixedsys = <&apmixedsys>;
+ nvmem-cells = <&thermal_calibration_data>;
+ nvmem-cell-names = "calibration-data";
+ #thermal-sensor-cells = <1>;
+ };
diff --git a/dts/upstream/Bindings/thermal/mediatek-thermal.txt b/dts/upstream/Bindings/thermal/mediatek-thermal.txt
deleted file mode 100644
index ac39c71..0000000
--- a/dts/upstream/Bindings/thermal/mediatek-thermal.txt
+++ /dev/null
@@ -1,52 +0,0 @@
-* Mediatek Thermal
-
-This describes the device tree binding for the Mediatek thermal controller
-which measures the on-SoC temperatures. This device does not have its own ADC,
-instead it directly controls the AUXADC via AHB bus accesses. For this reason
-this device needs phandles to the AUXADC. Also it controls a mux in the
-apmixedsys register space via AHB bus accesses, so a phandle to the APMIXEDSYS
-is also needed.
-
-Required properties:
-- compatible:
- - "mediatek,mt8173-thermal" : For MT8173 family of SoCs
- - "mediatek,mt2701-thermal" : For MT2701 family of SoCs
- - "mediatek,mt2712-thermal" : For MT2712 family of SoCs
- - "mediatek,mt7622-thermal" : For MT7622 SoC
- - "mediatek,mt7981-thermal", "mediatek,mt7986-thermal" : For MT7981 SoC
- - "mediatek,mt7986-thermal" : For MT7986 SoC
- - "mediatek,mt8183-thermal" : For MT8183 family of SoCs
- - "mediatek,mt8365-thermal" : For MT8365 family of SoCs
- - "mediatek,mt8516-thermal", "mediatek,mt2701-thermal : For MT8516 family of SoCs
-- reg: Address range of the thermal controller
-- interrupts: IRQ for the thermal controller
-- clocks, clock-names: Clocks needed for the thermal controller. required
- clocks are:
- "therm": Main clock needed for register access
- "auxadc": The AUXADC clock
-- mediatek,auxadc: A phandle to the AUXADC which the thermal controller uses
-- mediatek,apmixedsys: A phandle to the APMIXEDSYS controller.
-- #thermal-sensor-cells : Should be 0. See Documentation/devicetree/bindings/thermal/thermal-sensor.yaml for a description.
-
-Optional properties:
-- resets: Reference to the reset controller controlling the thermal controller.
-- nvmem-cells: A phandle to the calibration data provided by a nvmem device. If
- unspecified default values shall be used.
-- nvmem-cell-names: Should be "calibration-data"
-
-Example:
-
- thermal: thermal@1100b000 {
- #thermal-sensor-cells = <1>;
- compatible = "mediatek,mt8173-thermal";
- reg = <0 0x1100b000 0 0x1000>;
- interrupts = <0 70 IRQ_TYPE_LEVEL_LOW>;
- clocks = <&pericfg CLK_PERI_THERM>, <&pericfg CLK_PERI_AUXADC>;
- clock-names = "therm", "auxadc";
- resets = <&pericfg MT8173_PERI_THERM_SW_RST>;
- reset-names = "therm";
- mediatek,auxadc = <&auxadc>;
- mediatek,apmixedsys = <&apmixedsys>;
- nvmem-cells = <&thermal_calibration_data>;
- nvmem-cell-names = "calibration-data";
- };
diff --git a/dts/upstream/Bindings/thermal/qcom-spmi-adc-tm-hc.yaml b/dts/upstream/Bindings/thermal/qcom-spmi-adc-tm-hc.yaml
index 01253d5..7541e27 100644
--- a/dts/upstream/Bindings/thermal/qcom-spmi-adc-tm-hc.yaml
+++ b/dts/upstream/Bindings/thermal/qcom-spmi-adc-tm-hc.yaml
@@ -114,12 +114,14 @@
- |
#include <dt-bindings/iio/qcom,spmi-vadc.h>
#include <dt-bindings/interrupt-controller/irq.h>
- spmi_bus {
+
+ pmic {
#address-cells = <1>;
#size-cells = <0>;
+
pm8998_adc: adc@3100 {
- reg = <0x3100>;
compatible = "qcom,spmi-adc-rev2";
+ reg = <0x3100>;
#address-cells = <1>;
#size-cells = <0>;
#io-channel-cells = <1>;
@@ -130,7 +132,7 @@
};
};
- pm8998_adc_tm: adc-tm@3400 {
+ adc-tm@3400 {
compatible = "qcom,spmi-adc-tm-hc";
reg = <0x3400>;
interrupts = <0x2 0x34 0x0 IRQ_TYPE_EDGE_RISING>;
diff --git a/dts/upstream/Bindings/thermal/qcom-spmi-adc-tm5.yaml b/dts/upstream/Bindings/thermal/qcom-spmi-adc-tm5.yaml
index 3c81def..d9d2657 100644
--- a/dts/upstream/Bindings/thermal/qcom-spmi-adc-tm5.yaml
+++ b/dts/upstream/Bindings/thermal/qcom-spmi-adc-tm5.yaml
@@ -167,12 +167,14 @@
- |
#include <dt-bindings/iio/qcom,spmi-vadc.h>
#include <dt-bindings/interrupt-controller/irq.h>
- spmi_bus {
+
+ pmic {
#address-cells = <1>;
#size-cells = <0>;
+
pm8150b_adc: adc@3100 {
- reg = <0x3100>;
compatible = "qcom,spmi-adc5";
+ reg = <0x3100>;
#address-cells = <1>;
#size-cells = <0>;
#io-channel-cells = <1>;
@@ -186,7 +188,7 @@
};
};
- pm8150b_adc_tm: adc-tm@3500 {
+ adc-tm@3500 {
compatible = "qcom,spmi-adc-tm5";
reg = <0x3500>;
interrupts = <0x2 0x35 0x0 IRQ_TYPE_EDGE_RISING>;
@@ -207,12 +209,14 @@
#include <dt-bindings/iio/qcom,spmi-adc7-pmk8350.h>
#include <dt-bindings/iio/qcom,spmi-adc7-pm8350.h>
#include <dt-bindings/interrupt-controller/irq.h>
- spmi_bus {
+
+ pmic {
#address-cells = <1>;
#size-cells = <0>;
+
pmk8350_vadc: adc@3100 {
- reg = <0x3100>;
compatible = "qcom,spmi-adc7";
+ reg = <0x3100>;
#address-cells = <1>;
#size-cells = <0>;
#io-channel-cells = <1>;
@@ -233,7 +237,7 @@
};
};
- pmk8350_adc_tm: adc-tm@3400 {
+ adc-tm@3400 {
compatible = "qcom,spmi-adc-tm5-gen2";
reg = <0x3400>;
interrupts = <0x0 0x34 0x0 IRQ_TYPE_EDGE_RISING>;
diff --git a/dts/upstream/Bindings/thermal/qcom-tsens.yaml b/dts/upstream/Bindings/thermal/qcom-tsens.yaml
index 437b747..99d9c52 100644
--- a/dts/upstream/Bindings/thermal/qcom-tsens.yaml
+++ b/dts/upstream/Bindings/thermal/qcom-tsens.yaml
@@ -66,6 +66,7 @@
- qcom,sm8350-tsens
- qcom,sm8450-tsens
- qcom,sm8550-tsens
+ - qcom,sm8650-tsens
- const: qcom,tsens-v2
- description: v2 of TSENS with combined interrupt
diff --git a/dts/upstream/Bindings/thermal/thermal-zones.yaml b/dts/upstream/Bindings/thermal/thermal-zones.yaml
index 4a8dabc..dbd5262 100644
--- a/dts/upstream/Bindings/thermal/thermal-zones.yaml
+++ b/dts/upstream/Bindings/thermal/thermal-zones.yaml
@@ -75,6 +75,22 @@
framework and assumes that the thermal sensors in this zone
support interrupts.
+ critical-action:
+ $ref: /schemas/types.yaml#/definitions/string
+ description: |
+ The action the OS should perform after the critical temperature is reached.
+ By default the system will shutdown as a safe action to prevent damage
+ to the hardware, if the property is not set.
+ The shutdown action should be always the default and preferred one.
+ Choose 'reboot' with care, as the hardware may be in thermal stress,
+ thus leading to infinite reboots that may cause damage to the hardware.
+ Make sure the firmware/bootloader will act as the last resort and take
+ over the thermal control.
+
+ enum:
+ - shutdown
+ - reboot
+
thermal-sensors:
$ref: /schemas/types.yaml#/definitions/phandle-array
maxItems: 1
diff --git a/dts/upstream/Bindings/timer/sifive,clint.yaml b/dts/upstream/Bindings/timer/sifive,clint.yaml
index e8be6c4..fced6f2 100644
--- a/dts/upstream/Bindings/timer/sifive,clint.yaml
+++ b/dts/upstream/Bindings/timer/sifive,clint.yaml
@@ -33,11 +33,13 @@
- sifive,fu540-c000-clint # SiFive FU540
- starfive,jh7100-clint # StarFive JH7100
- starfive,jh7110-clint # StarFive JH7110
+ - starfive,jh8100-clint # StarFive JH8100
- const: sifive,clint0 # SiFive CLINT v0 IP block
- items:
- enum:
- allwinner,sun20i-d1-clint
- sophgo,cv1800b-clint
+ - sophgo,cv1812h-clint
- thead,th1520-clint
- const: thead,c900-clint
- items:
diff --git a/dts/upstream/Bindings/timer/thead,c900-aclint-mtimer.yaml b/dts/upstream/Bindings/timer/thead,c900-aclint-mtimer.yaml
index fbd2356..2e92bcd 100644
--- a/dts/upstream/Bindings/timer/thead,c900-aclint-mtimer.yaml
+++ b/dts/upstream/Bindings/timer/thead,c900-aclint-mtimer.yaml
@@ -17,7 +17,12 @@
- const: thead,c900-aclint-mtimer
reg:
- maxItems: 1
+ items:
+ - description: MTIMECMP Registers
+
+ reg-names:
+ items:
+ - const: mtimecmp
interrupts-extended:
minItems: 1
@@ -28,6 +33,7 @@
required:
- compatible
- reg
+ - reg-names
- interrupts-extended
examples:
@@ -39,5 +45,6 @@
<&cpu3intc 7>,
<&cpu4intc 7>;
reg = <0xac000000 0x00010000>;
+ reg-names = "mtimecmp";
};
...
diff --git a/dts/upstream/Bindings/tpm/google,cr50.yaml b/dts/upstream/Bindings/tpm/google,cr50.yaml
new file mode 100644
index 0000000..9302e12
--- /dev/null
+++ b/dts/upstream/Bindings/tpm/google,cr50.yaml
@@ -0,0 +1,65 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/tpm/google,cr50.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Google Security Chip H1 (running Cr50 firmware)
+
+maintainers:
+ - Andrey Pronin <apronin@chromium.org>
+
+description: |
+ Google has designed a family of security chips called "Titan".
+ One member is the H1 built into Chromebooks and running Cr50 firmware:
+ https://www.osfc.io/2018/talks/google-secure-microcontroller-and-ccd-closed-case-debugging/
+
+ The chip provides several functions, including TPM 2.0 like functionality.
+ It communicates over SPI or I²C using the FIFO protocol described in the
+ TCG PC Client Platform TPM Profile Specification for TPM 2.0 (PTP), sec 6:
+ https://trustedcomputinggroup.org/resource/pc-client-platform-tpm-profile-ptp-specification/
+
+properties:
+ compatible:
+ const: google,cr50
+
+allOf:
+ - $ref: tpm-common.yaml#
+
+anyOf:
+ - $ref: /schemas/spi/spi-peripheral-props.yaml#
+ - $ref: tcg,tpm-tis-i2c.yaml#/properties/reg
+
+required:
+ - compatible
+ - reg
+
+unevaluatedProperties: false
+
+examples:
+ - |
+ spi {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ tpm@0 {
+ reg = <0>;
+ compatible = "google,cr50";
+ spi-max-frequency = <800000>;
+ };
+ };
+
+ - |
+ #include <dt-bindings/interrupt-controller/irq.h>
+ i2c {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ tpm@50 {
+ compatible = "google,cr50";
+ reg = <0x50>;
+ interrupts-extended = <&pio 88 IRQ_TYPE_EDGE_FALLING>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&cr50_int>;
+ };
+ };
diff --git a/dts/upstream/Bindings/tpm/ibm,vtpm.yaml b/dts/upstream/Bindings/tpm/ibm,vtpm.yaml
new file mode 100644
index 0000000..50a3fd3
--- /dev/null
+++ b/dts/upstream/Bindings/tpm/ibm,vtpm.yaml
@@ -0,0 +1,104 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/tpm/ibm,vtpm.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: IBM Virtual Trusted Platform Module (vTPM)
+
+maintainers:
+ - Nayna Jain <nayna@linux.ibm.com>
+
+description: |
+ Virtual TPM is used on IBM POWER7+ and POWER8 systems running POWERVM.
+ It is supported through the adjunct partition with firmware release 740
+ or higher. With vTPM support, each lpar is able to have its own vTPM
+ without the physical TPM hardware. The TPM functionality is provided by
+ communicating with the vTPM adjunct partition through Hypervisor calls
+ (Hcalls) and Command/Response Queue (CRQ) commands.
+
+properties:
+ compatible:
+ enum:
+ - IBM,vtpm
+ - IBM,vtpm20
+
+ device_type:
+ description:
+ type of virtual device
+ enum:
+ - IBM,vtpm
+ - IBM,vtpm20
+
+ reg:
+ maxItems: 1
+
+ 'ibm,#dma-address-cells':
+ description:
+ number of cells that are used to encode the physical address field of
+ dma-window properties
+ $ref: /schemas/types.yaml#/definitions/uint32-array
+
+ 'ibm,#dma-size-cells':
+ description:
+ number of cells that are used to encode the size field of
+ dma-window properties
+ $ref: /schemas/types.yaml#/definitions/uint32-array
+
+ ibm,my-dma-window:
+ description:
+ DMA window associated with this virtual I/O Adapter
+ $ref: /schemas/types.yaml#/definitions/uint32-array
+ minItems: 5
+ maxItems: 5
+
+ ibm,my-drc-index:
+ description:
+ integer index for the connector between the device and its parent;
+ present only if Dynamic Reconfiguration (DR) Connector is enabled
+ $ref: /schemas/types.yaml#/definitions/uint32
+
+ ibm,loc-code:
+ description:
+ unique and persistent location code associated with this virtual
+ I/O Adapter
+ $ref: /schemas/types.yaml#/definitions/string
+
+required:
+ - compatible
+ - device_type
+ - reg
+ - interrupts
+ - ibm,#dma-address-cells
+ - ibm,#dma-size-cells
+ - ibm,my-dma-window
+ - ibm,my-drc-index
+ - ibm,loc-code
+ - linux,sml-base
+ - linux,sml-size
+
+allOf:
+ - $ref: tpm-common.yaml#
+
+unevaluatedProperties: false
+
+examples:
+ - |
+ soc {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ tpm@30000003 {
+ compatible = "IBM,vtpm";
+ device_type = "IBM,vtpm";
+ reg = <0x30000003>;
+ interrupts = <0xa0003 0x0>;
+ ibm,#dma-address-cells = <0x2>;
+ ibm,#dma-size-cells = <0x2>;
+ ibm,my-dma-window = <0x10000003 0x0 0x0 0x0 0x10000000>;
+ ibm,my-drc-index = <0x30000003>;
+ ibm,loc-code = "U8286.41A.10082DV-V3-C3";
+ linux,sml-base = <0xc60e 0x0>;
+ linux,sml-size = <0xbce10200>;
+ };
+ };
diff --git a/dts/upstream/Bindings/tpm/microsoft,ftpm.yaml b/dts/upstream/Bindings/tpm/microsoft,ftpm.yaml
new file mode 100644
index 0000000..fdb8196
--- /dev/null
+++ b/dts/upstream/Bindings/tpm/microsoft,ftpm.yaml
@@ -0,0 +1,47 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/tpm/microsoft,ftpm.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Microsoft firmware-based Trusted Platform Module (fTPM)
+
+maintainers:
+ - Thirupathaiah Annapureddy <thiruan@microsoft.com>
+ - Sasha Levin <sashal@kernel.org>
+
+description: |
+ Commodity CPU architectures, such as ARM and Intel CPUs, have started to
+ offer trusted computing features in their CPUs aimed at displacing dedicated
+ trusted hardware. Unfortunately, these CPU architectures raise serious
+ challenges to building trusted systems because they omit providing secure
+ resources outside the CPU perimeter.
+
+ Microsoft's firmware-based TPM 2.0 (fTPM) leverages ARM TrustZone to overcome
+ these challenges and provide software with security guarantees similar to
+ those of dedicated trusted hardware.
+
+ https://www.microsoft.com/en-us/research/publication/ftpm-software-implementation-tpm-chip/
+ https://github.com/Microsoft/ms-tpm-20-ref/tree/main/Samples/ARM32-FirmwareTPM
+
+properties:
+ compatible:
+ const: microsoft,ftpm
+
+required:
+ - compatible
+ - linux,sml-base
+ - linux,sml-size
+
+allOf:
+ - $ref: tpm-common.yaml#
+
+unevaluatedProperties: false
+
+examples:
+ - |
+ tpm {
+ compatible = "microsoft,ftpm";
+ linux,sml-base = <0x0 0xc0000000>;
+ linux,sml-size = <0x10000>;
+ };
diff --git a/dts/upstream/Bindings/tpm/tcg,tpm-tis-i2c.yaml b/dts/upstream/Bindings/tpm/tcg,tpm-tis-i2c.yaml
new file mode 100644
index 0000000..3ab4434
--- /dev/null
+++ b/dts/upstream/Bindings/tpm/tcg,tpm-tis-i2c.yaml
@@ -0,0 +1,90 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/tpm/tcg,tpm-tis-i2c.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: I²C-attached Trusted Platform Module conforming to TCG TIS specification
+
+maintainers:
+ - Lukas Wunner <lukas@wunner.de>
+
+description: |
+ The Trusted Computing Group (TCG) has defined a multi-vendor standard
+ for accessing a TPM chip. It can be transported over various buses,
+ one of them being I²C. The standard is named:
+ TCG PC Client Specific TPM Interface Specification (TIS)
+ https://trustedcomputinggroup.org/resource/pc-client-work-group-pc-client-specific-tpm-interface-specification-tis/
+
+ The I²C interface was not originally part of the standard, but added
+ in 2017 with a separate document:
+ TCG PC Client Platform TPM Profile Specification for TPM 2.0 (PTP)
+ https://trustedcomputinggroup.org/resource/pc-client-platform-tpm-profile-ptp-specification/
+
+ Recent TPM 2.0 chips conform to this generic interface, others use a
+ vendor-specific I²C interface.
+
+properties:
+ compatible:
+ oneOf:
+ - description: Generic TPM 2.0 chips conforming to TCG PTP interface
+ items:
+ - enum:
+ - infineon,slb9673
+ - nuvoton,npct75x
+ - const: tcg,tpm-tis-i2c
+
+ - description: TPM 1.2 and 2.0 chips with vendor-specific I²C interface
+ items:
+ - enum:
+ - atmel,at97sc3204t # TPM 1.2
+ - infineon,slb9635tt # TPM 1.2 (maximum 100 kHz)
+ - infineon,slb9645tt # TPM 1.2 (maximum 400 kHz)
+ - infineon,tpm_i2c_infineon # TPM 1.2
+ - nuvoton,npct501 # TPM 1.2
+ - nuvoton,npct601 # TPM 2.0
+ - st,st33zp24-i2c # TPM 2.0
+ - winbond,wpct301 # TPM 1.2
+
+ reg:
+ description: address of TPM on the I²C bus
+
+allOf:
+ - $ref: tpm-common.yaml#
+
+required:
+ - compatible
+ - reg
+
+unevaluatedProperties: false
+
+examples:
+ - |
+ i2c {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ tpm@57 {
+ label = "tpm";
+ compatible = "nuvoton,npct601";
+ reg = <0x57>;
+ linux,sml-base = <0x7f 0xfd450000>;
+ linux,sml-size = <0x10000>;
+ };
+ };
+
+ - |
+ #include <dt-bindings/gpio/gpio.h>
+ #include <dt-bindings/interrupt-controller/irq.h>
+ i2c {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ tpm@13 {
+ reg = <0x13>;
+ compatible = "st,st33zp24-i2c";
+ interrupt-parent = <&gpio5>;
+ interrupts = <7 IRQ_TYPE_LEVEL_HIGH>;
+ lpcpd-gpios = <&gpio5 15 GPIO_ACTIVE_HIGH>;
+ };
+ };
diff --git a/dts/upstream/Bindings/tpm/tcg,tpm-tis-mmio.yaml b/dts/upstream/Bindings/tpm/tcg,tpm-tis-mmio.yaml
new file mode 100644
index 0000000..87bce06
--- /dev/null
+++ b/dts/upstream/Bindings/tpm/tcg,tpm-tis-mmio.yaml
@@ -0,0 +1,49 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/tpm/tcg,tpm-tis-mmio.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: MMIO-accessed Trusted Platform Module conforming to TCG TIS specification
+
+maintainers:
+ - Lukas Wunner <lukas@wunner.de>
+
+description: |
+ The Trusted Computing Group (TCG) has defined a multi-vendor standard
+ for accessing a TPM chip. It can be transported over various buses,
+ one of them being LPC (via MMIO). The standard is named:
+ TCG PC Client Specific TPM Interface Specification (TIS)
+ https://trustedcomputinggroup.org/resource/pc-client-work-group-pc-client-specific-tpm-interface-specification-tis/
+
+properties:
+ compatible:
+ items:
+ - enum:
+ - at97sc3201
+ - atmel,at97sc3204
+ - socionext,synquacer-tpm-mmio
+ - const: tcg,tpm-tis-mmio
+
+ reg:
+ description:
+ location and length of the MMIO registers, length should be
+ at least 0x5000 bytes
+
+allOf:
+ - $ref: tpm-common.yaml#
+
+required:
+ - compatible
+ - reg
+
+unevaluatedProperties: false
+
+examples:
+ - |
+ tpm@90000 {
+ compatible = "atmel,at97sc3204", "tcg,tpm-tis-mmio";
+ reg = <0x90000 0x5000>;
+ interrupt-parent = <&EIC0>;
+ interrupts = <1 2>;
+ };
diff --git a/dts/upstream/Bindings/tpm/tcg,tpm_tis-spi.yaml b/dts/upstream/Bindings/tpm/tcg,tpm_tis-spi.yaml
new file mode 100644
index 0000000..c3413b4
--- /dev/null
+++ b/dts/upstream/Bindings/tpm/tcg,tpm_tis-spi.yaml
@@ -0,0 +1,75 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/tpm/tcg,tpm_tis-spi.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: SPI-attached Trusted Platform Module conforming to TCG TIS specification
+
+maintainers:
+ - Lukas Wunner <lukas@wunner.de>
+
+description: |
+ The Trusted Computing Group (TCG) has defined a multi-vendor standard
+ for accessing a TPM chip. It can be transported over various buses,
+ one of them being SPI. The standard is named:
+ TCG PC Client Specific TPM Interface Specification (TIS)
+ https://trustedcomputinggroup.org/resource/pc-client-work-group-pc-client-specific-tpm-interface-specification-tis/
+
+properties:
+ compatible:
+ items:
+ - enum:
+ - infineon,slb9670
+ - st,st33htpm-spi
+ - st,st33zp24-spi
+ - const: tcg,tpm_tis-spi
+
+allOf:
+ - $ref: tpm-common.yaml#
+ - $ref: /schemas/spi/spi-peripheral-props.yaml#
+ - if:
+ properties:
+ compatible:
+ contains:
+ const: st,st33zp24-spi
+ then:
+ properties:
+ spi-max-frequency:
+ maximum: 10000000
+
+required:
+ - compatible
+ - reg
+
+unevaluatedProperties: false
+
+examples:
+ - |
+ spi {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ tpm@0 {
+ reg = <0>;
+ compatible = "infineon,slb9670", "tcg,tpm_tis-spi";
+ spi-max-frequency = <10000000>;
+ };
+ };
+
+ - |
+ #include <dt-bindings/gpio/gpio.h>
+ #include <dt-bindings/interrupt-controller/irq.h>
+ spi {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ tpm@0 {
+ reg = <0>;
+ compatible = "st,st33zp24-spi", "tcg,tpm_tis-spi";
+ spi-max-frequency = <10000000>;
+ interrupt-parent = <&gpio5>;
+ interrupts = <7 IRQ_TYPE_LEVEL_HIGH>;
+ lpcpd-gpios = <&gpio5 15 GPIO_ACTIVE_HIGH>;
+ };
+ };
diff --git a/dts/upstream/Bindings/tpm/tpm-common.yaml b/dts/upstream/Bindings/tpm/tpm-common.yaml
new file mode 100644
index 0000000..3c1241b
--- /dev/null
+++ b/dts/upstream/Bindings/tpm/tpm-common.yaml
@@ -0,0 +1,87 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/tpm/tpm-common.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Trusted Platform Module common properties
+
+maintainers:
+ - Lukas Wunner <lukas@wunner.de>
+
+properties:
+ $nodename:
+ pattern: '^tpm(@[0-9a-f]+)?$'
+
+ interrupts:
+ description: indicates command completion
+ maxItems: 1
+
+ label:
+ description: human readable string describing the device, e.g. "tpm"
+
+ linux,sml-base:
+ description:
+ base address of reserved memory allocated for firmware event log
+ $ref: /schemas/types.yaml#/definitions/uint64
+
+ linux,sml-size:
+ description:
+ size of reserved memory allocated for firmware event log
+ $ref: /schemas/types.yaml#/definitions/uint32
+
+ memory-region:
+ description: reserved memory allocated for firmware event log
+ maxItems: 1
+
+ powered-while-suspended:
+ description:
+ present when the TPM is left powered on between suspend and resume
+ (makes the suspend/resume callbacks do nothing)
+ type: boolean
+
+ resets:
+ description: Reset controller to reset the TPM
+ maxItems: 1
+
+ reset-gpios:
+ description: Output GPIO pin to reset the TPM
+ maxItems: 1
+
+# must always have both linux,sml-base and linux,sml-size
+dependentRequired:
+ linux,sml-base: ['linux,sml-size']
+ linux,sml-size: ['linux,sml-base']
+
+# must only have either memory-region or linux,sml-base
+# as well as either resets or reset-gpios
+dependentSchemas:
+ memory-region:
+ properties:
+ linux,sml-base: false
+ linux,sml-base:
+ properties:
+ memory-region: false
+ resets:
+ properties:
+ reset-gpios: false
+ reset-gpios:
+ properties:
+ resets: false
+
+allOf:
+ - if:
+ properties:
+ compatible:
+ contains:
+ pattern: '^st,st33zp24'
+ then:
+ properties:
+ lpcpd-gpios:
+ description:
+ Output GPIO pin used for ST33ZP24 power management of D1/D2 state.
+ If set, power must be present when the platform is going into
+ sleep/hibernate mode.
+ maxItems: 1
+
+additionalProperties: true
diff --git a/dts/upstream/Bindings/trivial-devices.yaml b/dts/upstream/Bindings/trivial-devices.yaml
index c3190f2..79dcd92 100644
--- a/dts/upstream/Bindings/trivial-devices.yaml
+++ b/dts/upstream/Bindings/trivial-devices.yaml
@@ -49,8 +49,6 @@
- ams,iaq-core
# i2c serial eeprom (24cxx)
- at,24c08
- # i2c trusted platform module (TPM)
- - atmel,at97sc3204t
# ATSHA204 - i2c h/w symmetric crypto module
- atmel,atsha204
# ATSHA204A - i2c h/w symmetric crypto module
@@ -117,6 +115,10 @@
- fsl,mpl3115
# MPR121: Proximity Capacitive Touch Sensor Controller
- fsl,mpr121
+ # Monolithic Power Systems Inc. multi-phase controller mp2856
+ - mps,mp2856
+ # Monolithic Power Systems Inc. multi-phase controller mp2857
+ - mps,mp2857
# Monolithic Power Systems Inc. multi-phase controller mp2888
- mps,mp2888
# Monolithic Power Systems Inc. multi-phase controller mp2971
@@ -125,6 +127,8 @@
- mps,mp2973
# Monolithic Power Systems Inc. multi-phase controller mp2975
- mps,mp2975
+ # Monolithic Power Systems Inc. multi-phase hot-swap controller mp5990
+ - mps,mp5990
# Honeywell Humidicon HIH-6130 humidity/temperature sensor
- honeywell,hi6130
# IBM Common Form Factor Power Supply Versions (all versions)
@@ -145,12 +149,6 @@
- infineon,ir38263
# Infineon IRPS5401 Voltage Regulator (PMIC)
- infineon,irps5401
- # Infineon SLB9635 (Soft-) I2C TPM (old protocol, max 100khz)
- - infineon,slb9635tt
- # Infineon SLB9645 I2C TPM (new protocol, max 400khz)
- - infineon,slb9645tt
- # Infineon SLB9673 I2C TPM 2.0
- - infineon,slb9673
# Infineon TLV493D-A1B6 I2C 3D Magnetic Sensor
- infineon,tlv493d-a1b6
# Infineon Multi-phase Digital VR Controller xdpe11280
@@ -179,6 +177,8 @@
- isil,isl29030
# Intersil ISL68137 Digital Output Configurable PWM Controller
- isil,isl68137
+ # Intersil ISL76682 Ambient Light Sensor
+ - isil,isl76682
# Linear Technology LTC2488
- lineartechnology,ltc2488
# 5 Bit Programmable, Pulse-Width Modulator
@@ -301,10 +301,6 @@
- national,lm85
# I2C ±0.33°C Accurate, 12-Bit + Sign Temperature Sensor and Thermal Window Comparator
- national,lm92
- # i2c trusted platform module (TPM)
- - nuvoton,npct501
- # i2c trusted platform module (TPM2)
- - nuvoton,npct601
# Nuvoton Temperature Sensor
- nuvoton,w83773g
# OKI ML86V7667 video decoder
@@ -349,8 +345,6 @@
- silabs,si7020
# Skyworks SKY81452: Six-Channel White LED Driver with Touch Panel Bias Supply
- skyworks,sky81452
- # Socionext SynQuacer TPM MMIO module
- - socionext,synquacer-tpm-mmio
# SparkFun Qwiic Joystick (COM-15168) with i2c interface
- sparkfun,qwiic-joystick
# i2c serial eeprom (24cxx)
@@ -405,8 +399,6 @@
- winbond,w83793
# Vicor Corporation Digital Supervisor
- vicor,pli1209bc
- # i2c trusted platform module (TPM)
- - winbond,wpct301
required:
- compatible
diff --git a/dts/upstream/Bindings/ufs/qcom,ufs.yaml b/dts/upstream/Bindings/ufs/qcom,ufs.yaml
index 2cf3d01..10c1464 100644
--- a/dts/upstream/Bindings/ufs/qcom,ufs.yaml
+++ b/dts/upstream/Bindings/ufs/qcom,ufs.yaml
@@ -27,6 +27,7 @@
- qcom,msm8996-ufshc
- qcom,msm8998-ufshc
- qcom,sa8775p-ufshc
+ - qcom,sc7280-ufshc
- qcom,sc8280xp-ufshc
- qcom,sdm845-ufshc
- qcom,sm6115-ufshc
@@ -118,6 +119,7 @@
enum:
- qcom,msm8998-ufshc
- qcom,sa8775p-ufshc
+ - qcom,sc7280-ufshc
- qcom,sc8280xp-ufshc
- qcom,sm8250-ufshc
- qcom,sm8350-ufshc
diff --git a/dts/upstream/Bindings/ufs/samsung,exynos-ufs.yaml b/dts/upstream/Bindings/ufs/samsung,exynos-ufs.yaml
index 88cc1e3..b2b509b 100644
--- a/dts/upstream/Bindings/ufs/samsung,exynos-ufs.yaml
+++ b/dts/upstream/Bindings/ufs/samsung,exynos-ufs.yaml
@@ -55,9 +55,12 @@
samsung,sysreg:
$ref: /schemas/types.yaml#/definitions/phandle-array
- description: Should be phandle/offset pair. The phandle to the syscon node
- which indicates the FSYSx sysreg interface and the offset of
- the control register for UFS io coherency setting.
+ items:
+ - items:
+ - description: phandle to FSYSx sysreg node
+ - description: offset of the control register for UFS io coherency setting
+ description:
+ Phandle and offset to the FSYSx sysreg for UFS io coherency setting.
dma-coherent: true
diff --git a/dts/upstream/Bindings/ufs/ufs-common.yaml b/dts/upstream/Bindings/ufs/ufs-common.yaml
index 985ea8f..31fe7f3 100644
--- a/dts/upstream/Bindings/ufs/ufs-common.yaml
+++ b/dts/upstream/Bindings/ufs/ufs-common.yaml
@@ -87,6 +87,8 @@
description:
Specifies max. load that can be drawn from VCCQ2 supply.
+ msi-parent: true
+
dependencies:
freq-table-hz: [ clocks ]
operating-points-v2: [ clocks, clock-names ]
diff --git a/dts/upstream/Bindings/usb/dwc3-xilinx.yaml b/dts/upstream/Bindings/usb/dwc3-xilinx.yaml
index bb373eb..00f87a5 100644
--- a/dts/upstream/Bindings/usb/dwc3-xilinx.yaml
+++ b/dts/upstream/Bindings/usb/dwc3-xilinx.yaml
@@ -7,7 +7,8 @@
title: Xilinx SuperSpeed DWC3 USB SoC controller
maintainers:
- - Piyush Mehta <piyush.mehta@amd.com>
+ - Mubin Sayyed <mubin.sayyed@amd.com>
+ - Radhey Shyam Pandey <radhey.shyam.pandey@amd.com>
properties:
compatible:
diff --git a/dts/upstream/Bindings/usb/generic-xhci.yaml b/dts/upstream/Bindings/usb/generic-xhci.yaml
index 594ebb3..6ceafa4a 100644
--- a/dts/upstream/Bindings/usb/generic-xhci.yaml
+++ b/dts/upstream/Bindings/usb/generic-xhci.yaml
@@ -9,9 +9,6 @@
maintainers:
- Mathias Nyman <mathias.nyman@intel.com>
-allOf:
- - $ref: usb-xhci.yaml#
-
properties:
compatible:
oneOf:
@@ -25,6 +22,11 @@
- marvell,armada-380-xhci
- marvell,armada-8k-xhci
- const: generic-xhci
+ - description: Broadcom SoCs with power domains
+ items:
+ - enum:
+ - brcm,bcm2711-xhci
+ - const: brcm,xhci-brcm-v2
- description: Broadcom STB SoCs with xHCI
enum:
- brcm,xhci-brcm-v2
@@ -49,6 +51,9 @@
- const: core
- const: reg
+ power-domains:
+ maxItems: 1
+
unevaluatedProperties: false
required:
@@ -56,6 +61,20 @@
- reg
- interrupts
+allOf:
+ - $ref: usb-xhci.yaml#
+ - if:
+ properties:
+ compatible:
+ contains:
+ const: brcm,bcm2711-xhci
+ then:
+ required:
+ - power-domains
+ else:
+ properties:
+ power-domains: false
+
examples:
- |
usb@f0931000 {
diff --git a/dts/upstream/Bindings/usb/genesys,gl850g.yaml b/dts/upstream/Bindings/usb/genesys,gl850g.yaml
index ee08b9c..37cf524 100644
--- a/dts/upstream/Bindings/usb/genesys,gl850g.yaml
+++ b/dts/upstream/Bindings/usb/genesys,gl850g.yaml
@@ -29,6 +29,11 @@
description:
the regulator that provides 3.3V core power to the hub.
+ peer-hub:
+ $ref: /schemas/types.yaml#/definitions/phandle
+ description:
+ phandle to the peer hub on the controller.
+
required:
- compatible
- reg
diff --git a/dts/upstream/Bindings/usb/mediatek,mtk-xhci.yaml b/dts/upstream/Bindings/usb/mediatek,mtk-xhci.yaml
index e9644e3..924fd3d 100644
--- a/dts/upstream/Bindings/usb/mediatek,mtk-xhci.yaml
+++ b/dts/upstream/Bindings/usb/mediatek,mtk-xhci.yaml
@@ -124,6 +124,17 @@
defined in the xHCI spec on MTK's controller.
default: 5000
+ rx-fifo-depth:
+ $ref: /schemas/types.yaml#/definitions/uint32
+ description:
+ It is a quirk used to work around Gen1 isoc-in endpoint transfer issue
+ that still send out unexpected ACK after device finishes the burst
+ transfer with a short packet and cause an exception, specially on a 4K
+ camera device, it happens on controller before about IPM v1.6.0;
+ the side-effect is that it may cause performance drop about 10%,
+ including bulk transfer, prefer to use 3k here. The size is in bytes.
+ enum: [1024, 2048, 3072, 4096]
+
# the following properties are only used for case 1
wakeup-source:
description: enable USB remote wakeup, see power/wakeup-source.txt
diff --git a/dts/upstream/Bindings/usb/microchip,usb5744.yaml b/dts/upstream/Bindings/usb/microchip,usb5744.yaml
index 6d4cfd9..445183d 100644
--- a/dts/upstream/Bindings/usb/microchip,usb5744.yaml
+++ b/dts/upstream/Bindings/usb/microchip,usb5744.yaml
@@ -16,8 +16,9 @@
USB 2.0 traffic.
maintainers:
- - Piyush Mehta <piyush.mehta@amd.com>
- Michal Simek <michal.simek@amd.com>
+ - Mubin Sayyed <mubin.sayyed@amd.com>
+ - Radhey Shyam Pandey <radhey.shyam.pandey@amd.com>
properties:
compatible:
diff --git a/dts/upstream/Bindings/usb/nxp,ptn5110.yaml b/dts/upstream/Bindings/usb/nxp,ptn5110.yaml
index 28eb25e..eaedb4c 100644
--- a/dts/upstream/Bindings/usb/nxp,ptn5110.yaml
+++ b/dts/upstream/Bindings/usb/nxp,ptn5110.yaml
@@ -4,7 +4,7 @@
$id: http://devicetree.org/schemas/usb/nxp,ptn5110.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
-title: NXP PTN5110 Typec Port Cotroller
+title: NXP PTN5110 Type-C Port Controller
maintainers:
- Li Jun <jun.li@nxp.com>
diff --git a/dts/upstream/Bindings/usb/qcom,dwc3.yaml b/dts/upstream/Bindings/usb/qcom,dwc3.yaml
index 915c820..63d150b 100644
--- a/dts/upstream/Bindings/usb/qcom,dwc3.yaml
+++ b/dts/upstream/Bindings/usb/qcom,dwc3.yaml
@@ -46,6 +46,8 @@
- qcom,sm8350-dwc3
- qcom,sm8450-dwc3
- qcom,sm8550-dwc3
+ - qcom,sm8650-dwc3
+ - qcom,x1e80100-dwc3
- const: qcom,dwc3
reg:
@@ -97,12 +99,29 @@
- const: apps-usb
interrupts:
- minItems: 1
- maxItems: 4
+ description: |
+ Different types of interrupts are used based on HS PHY used on target:
+ - pwr_event: Used for wakeup based on other power events.
+ - hs_phY_irq: Apart from DP/DM/QUSB2 PHY interrupts, there is
+ hs_phy_irq which is not triggered by default and its
+ functionality is mutually exclusive to that of
+ {dp/dm}_hs_phy_irq and qusb2_phy_irq.
+ - qusb2_phy: SoCs with QUSB2 PHY do not have separate DP/DM IRQs and
+ expose only a single IRQ whose behavior can be modified
+ by the QUSB2PHY_INTR_CTRL register. The required DPSE/
+ DMSE configuration is done in QUSB2PHY_INTR_CTRL register
+ of PHY address space.
+ - {dp/dm}_hs_phy_irq: These IRQ's directly reflect changes on the DP/
+ DM pads of the SoC. These are used for wakeup
+ only on SoCs with non-QUSB2 targets with
+ exception of SDM670/SDM845/SM6350.
+ - ss_phy_irq: Used for remote wakeup in Super Speed mode of operation.
+ minItems: 2
+ maxItems: 5
interrupt-names:
- minItems: 1
- maxItems: 4
+ minItems: 2
+ maxItems: 5
qcom,select-utmi-as-pipe-clk:
description:
@@ -263,6 +282,7 @@
contains:
enum:
- qcom,sc8280xp-dwc3
+ - qcom,x1e80100-dwc3
then:
properties:
clocks:
@@ -288,8 +308,8 @@
then:
properties:
clocks:
- minItems: 5
- maxItems: 6
+ minItems: 4
+ maxItems: 5
clock-names:
oneOf:
- items:
@@ -298,13 +318,11 @@
- const: iface
- const: sleep
- const: mock_utmi
- - const: bus
- items:
- const: cfg_noc
- const: core
- const: sleep
- const: mock_utmi
- - const: bus
- if:
properties:
@@ -318,6 +336,7 @@
- qcom,sm8250-dwc3
- qcom,sm8450-dwc3
- qcom,sm8550-dwc3
+ - qcom,sm8650-dwc3
then:
properties:
clocks:
@@ -357,59 +376,20 @@
compatible:
contains:
enum:
- - qcom,ipq4019-dwc3
+ - qcom,ipq5018-dwc3
- qcom,ipq6018-dwc3
- - qcom,ipq8064-dwc3
- qcom,ipq8074-dwc3
- - qcom,msm8994-dwc3
- - qcom,qcs404-dwc3
- - qcom,sc7180-dwc3
- - qcom,sdm670-dwc3
- - qcom,sdm845-dwc3
- - qcom,sdx55-dwc3
- - qcom,sdx65-dwc3
- - qcom,sdx75-dwc3
- - qcom,sm4250-dwc3
- - qcom,sm6125-dwc3
- - qcom,sm6350-dwc3
- - qcom,sm8150-dwc3
- - qcom,sm8250-dwc3
- - qcom,sm8350-dwc3
- - qcom,sm8450-dwc3
- - qcom,sm8550-dwc3
- then:
- properties:
- interrupts:
- items:
- - description: The interrupt that is asserted
- when a wakeup event is received on USB2 bus.
- - description: The interrupt that is asserted
- when a wakeup event is received on USB3 bus.
- - description: Wakeup event on DM line.
- - description: Wakeup event on DP line.
- interrupt-names:
- items:
- - const: hs_phy_irq
- - const: ss_phy_irq
- - const: dm_hs_phy_irq
- - const: dp_hs_phy_irq
-
- - if:
- properties:
- compatible:
- contains:
- enum:
- qcom,msm8953-dwc3
- - qcom,msm8996-dwc3
- qcom,msm8998-dwc3
- - qcom,sm6115-dwc3
then:
properties:
interrupts:
- maxItems: 2
+ minItems: 2
+ maxItems: 3
interrupt-names:
items:
- - const: hs_phy_irq
+ - const: pwr_event
+ - const: qusb2_phy
- const: ss_phy_irq
- if:
@@ -417,37 +397,21 @@
compatible:
contains:
enum:
- - qcom,ipq5018-dwc3
- - qcom,ipq5332-dwc3
+ - qcom,msm8996-dwc3
+ - qcom,qcs404-dwc3
- qcom,sdm660-dwc3
- then:
- properties:
- interrupts:
- minItems: 1
- maxItems: 2
- interrupt-names:
- minItems: 1
- items:
- - const: hs_phy_irq
- - const: ss_phy_irq
-
- - if:
- properties:
- compatible:
- contains:
- enum:
- - qcom,sc7280-dwc3
+ - qcom,sm6115-dwc3
+ - qcom,sm6125-dwc3
then:
properties:
interrupts:
minItems: 3
maxItems: 4
interrupt-names:
- minItems: 3
items:
+ - const: pwr_event
+ - const: qusb2_phy
- const: hs_phy_irq
- - const: dp_hs_phy_irq
- - const: dm_hs_phy_irq
- const: ss_phy_irq
- if:
@@ -455,7 +419,8 @@
compatible:
contains:
enum:
- - qcom,sc8280xp-dwc3
+ - qcom,ipq5332-dwc3
+ - qcom,x1e80100-dwc3
then:
properties:
interrupts:
@@ -472,16 +437,35 @@
compatible:
contains:
enum:
+ - qcom,ipq4019-dwc3
+ - qcom,ipq8064-dwc3
+ - qcom,msm8994-dwc3
- qcom,sa8775p-dwc3
+ - qcom,sc7180-dwc3
+ - qcom,sc7280-dwc3
+ - qcom,sc8280xp-dwc3
+ - qcom,sdm670-dwc3
+ - qcom,sdm845-dwc3
+ - qcom,sdx55-dwc3
+ - qcom,sdx65-dwc3
+ - qcom,sdx75-dwc3
+ - qcom,sm4250-dwc3
+ - qcom,sm6350-dwc3
+ - qcom,sm8150-dwc3
+ - qcom,sm8250-dwc3
+ - qcom,sm8350-dwc3
+ - qcom,sm8450-dwc3
+ - qcom,sm8550-dwc3
+ - qcom,sm8650-dwc3
then:
properties:
interrupts:
- minItems: 3
- maxItems: 4
+ minItems: 4
+ maxItems: 5
interrupt-names:
- minItems: 3
items:
- const: pwr_event
+ - const: hs_phy_irq
- const: dp_hs_phy_irq
- const: dm_hs_phy_irq
- const: ss_phy_irq
@@ -519,12 +503,13 @@
<&gcc GCC_USB30_PRIM_MASTER_CLK>;
assigned-clock-rates = <19200000>, <150000000>;
- interrupts = <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 486 IRQ_TYPE_LEVEL_HIGH>,
+ interrupts = <GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 489 IRQ_TYPE_EDGE_BOTH>,
<GIC_SPI 488 IRQ_TYPE_EDGE_BOTH>,
- <GIC_SPI 489 IRQ_TYPE_EDGE_BOTH>;
- interrupt-names = "hs_phy_irq", "ss_phy_irq",
- "dm_hs_phy_irq", "dp_hs_phy_irq";
+ <GIC_SPI 486 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "pwr_event", "hs_phy_irq",
+ "dp_hs_phy_irq", "dm_hs_phy_irq", "ss_phy_irq";
power-domains = <&gcc USB30_PRIM_GDSC>;
diff --git a/dts/upstream/Bindings/usb/qcom,wcd939x-usbss.yaml b/dts/upstream/Bindings/usb/qcom,wcd939x-usbss.yaml
new file mode 100644
index 0000000..7ddfd33
--- /dev/null
+++ b/dts/upstream/Bindings/usb/qcom,wcd939x-usbss.yaml
@@ -0,0 +1,102 @@
+# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/usb/qcom,wcd939x-usbss.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Qualcomm WCD9380/WCD9385 USB SubSystem Altmode/Analog Audio Switch
+
+maintainers:
+ - Neil Armstrong <neil.armstrong@linaro.org>
+
+description:
+ Qualcomm WCD9390/WCD9395 is a standalone Hi-Fi audio codec IC with a
+ functionally separate USB SubSystem for Altmode/Analog Audio Switch
+ accessible over an I2C interface.
+ The Audio Headphone and Microphone data path between the Codec and the
+ USB-C Mux subsystems are external to the IC, thus requiring DT port-endpoint
+ graph description to handle USB-C altmode & orientation switching for Audio
+ Accessory Mode.
+
+properties:
+ compatible:
+ oneOf:
+ - const: qcom,wcd9390-usbss
+ - items:
+ - const: qcom,wcd9395-usbss
+ - const: qcom,wcd9390-usbss
+
+ reg:
+ maxItems: 1
+
+ reset-gpios:
+ maxItems: 1
+
+ vdd-supply:
+ description: USBSS VDD power supply
+
+ mode-switch:
+ description: Flag the port as possible handle of altmode switching
+ type: boolean
+
+ orientation-switch:
+ description: Flag the port as possible handler of orientation switching
+ type: boolean
+
+ ports:
+ $ref: /schemas/graph.yaml#/properties/ports
+ properties:
+ port@0:
+ $ref: /schemas/graph.yaml#/properties/port
+ description:
+ A port node to link the WCD939x USB SubSystem to a TypeC controller for the
+ purpose of handling altmode muxing and orientation switching.
+
+ port@1:
+ $ref: /schemas/graph.yaml#/properties/port
+ description:
+ A port node to link the WCD939x USB SubSystem to the Codec SubSystem for the
+ purpose of handling USB-C Audio Accessory Mode muxing and orientation switching.
+
+required:
+ - compatible
+ - reg
+ - ports
+
+additionalProperties: false
+
+examples:
+ - |
+ i2c {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ typec-mux@42 {
+ compatible = "qcom,wcd9390-usbss";
+ reg = <0x42>;
+
+ vdd-supply = <&vreg_bob>;
+
+ mode-switch;
+ orientation-switch;
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+ wcd9390_usbss_sbu: endpoint {
+ remote-endpoint = <&typec_sbu>;
+ };
+ };
+ port@1 {
+ reg = <1>;
+ wcd9390_usbss_codec: endpoint {
+ remote-endpoint = <&wcd9390_codec_usbss>;
+ };
+ };
+ };
+ };
+ };
+...
diff --git a/dts/upstream/Bindings/usb/renesas,usbhs.yaml b/dts/upstream/Bindings/usb/renesas,usbhs.yaml
index bad55df..40ada78 100644
--- a/dts/upstream/Bindings/usb/renesas,usbhs.yaml
+++ b/dts/upstream/Bindings/usb/renesas,usbhs.yaml
@@ -19,7 +19,7 @@
- items:
- enum:
- renesas,usbhs-r7s9210 # RZ/A2
- - renesas,usbhs-r9a07g043 # RZ/G2UL
+ - renesas,usbhs-r9a07g043 # RZ/G2UL and RZ/Five
- renesas,usbhs-r9a07g044 # RZ/G2{L,LC}
- renesas,usbhs-r9a07g054 # RZ/V2L
- const: renesas,rza2-usbhs
diff --git a/dts/upstream/Bindings/usb/snps,dwc3.yaml b/dts/upstream/Bindings/usb/snps,dwc3.yaml
index ee5af4b..203a1eb 100644
--- a/dts/upstream/Bindings/usb/snps,dwc3.yaml
+++ b/dts/upstream/Bindings/usb/snps,dwc3.yaml
@@ -432,6 +432,10 @@
items:
enum: [1, 4, 8, 16, 32, 64, 128, 256]
+ num-hc-interrupters:
+ maximum: 8
+ default: 1
+
port:
$ref: /schemas/graph.yaml#/properties/port
description:
diff --git a/dts/upstream/Bindings/usb/ti,tps6598x.yaml b/dts/upstream/Bindings/usb/ti,tps6598x.yaml
index 323d664..1745e28 100644
--- a/dts/upstream/Bindings/usb/ti,tps6598x.yaml
+++ b/dts/upstream/Bindings/usb/ti,tps6598x.yaml
@@ -38,6 +38,10 @@
- const: main
- const: patch-address
+ reset-gpios:
+ description: GPIO used for the HRESET pin.
+ maxItems: 1
+
wakeup-source: true
interrupts:
@@ -90,6 +94,7 @@
examples:
- |
+ #include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/interrupt-controller/irq.h>
i2c {
#address-cells = <1>;
@@ -106,6 +111,7 @@
pinctrl-names = "default";
pinctrl-0 = <&typec_pins>;
+ reset-gpios = <&gpio1 6 GPIO_ACTIVE_HIGH>;
typec_con: connector {
compatible = "usb-c-connector";
diff --git a/dts/upstream/Bindings/usb/usb-xhci.yaml b/dts/upstream/Bindings/usb/usb-xhci.yaml
index 180a261..4238ae8 100644
--- a/dts/upstream/Bindings/usb/usb-xhci.yaml
+++ b/dts/upstream/Bindings/usb/usb-xhci.yaml
@@ -29,6 +29,12 @@
description: Interrupt moderation interval
default: 5000
+ num-hc-interrupters:
+ description: Maximum number of interrupters to allocate
+ $ref: /schemas/types.yaml#/definitions/uint16
+ minimum: 1
+ maximum: 1024
+
additionalProperties: true
examples:
diff --git a/dts/upstream/Bindings/usb/xlnx,usb2.yaml b/dts/upstream/Bindings/usb/xlnx,usb2.yaml
index 868dffe..a7f75fe 100644
--- a/dts/upstream/Bindings/usb/xlnx,usb2.yaml
+++ b/dts/upstream/Bindings/usb/xlnx,usb2.yaml
@@ -7,7 +7,8 @@
title: Xilinx udc controller
maintainers:
- - Piyush Mehta <piyush.mehta@amd.com>
+ - Mubin Sayyed <mubin.sayyed@amd.com>
+ - Radhey Shyam Pandey <radhey.shyam.pandey@amd.com>
properties:
compatible:
diff --git a/dts/upstream/Bindings/vendor-prefixes.yaml b/dts/upstream/Bindings/vendor-prefixes.yaml
index 309b94c..1a0dc04 100644
--- a/dts/upstream/Bindings/vendor-prefixes.yaml
+++ b/dts/upstream/Bindings/vendor-prefixes.yaml
@@ -79,6 +79,8 @@
description: ALFA Network Inc.
"^allegro,.*":
description: Allegro DVT
+ "^alliedvision,.*":
+ description: Allied Vision Technologies GmbH
"^allo,.*":
description: Allo.com
"^allwinner,.*":
@@ -119,6 +121,8 @@
description: Andes Technology Corporation
"^anvo,.*":
description: Anvo-Systems Dresden GmbH
+ "^aosong,.*":
+ description: Guangzhou Aosong Electronic Co., Ltd.
"^apm,.*":
description: Applied Micro Circuits Corporation (APM)
"^apple,.*":
@@ -294,6 +298,8 @@
description: CompuLab Ltd.
"^congatec,.*":
description: congatec GmbH
+ "^coolpi,.*":
+ description: cool-pi.com
"^coreriver,.*":
description: CORERIVER Semiconductor Co.,Ltd.
"^corpro,.*":
@@ -352,6 +358,8 @@
description: Digi International Inc.
"^digilent,.*":
description: Diglent, Inc.
+ "^dimonoff,.*":
+ description: Dimonoff inc.
"^diodes,.*":
description: Diodes, Inc.
"^dioo,.*":
@@ -474,6 +482,8 @@
description: Fairphone B.V.
"^faraday,.*":
description: Faraday Technology Corporation
+ "^fascontek,.*":
+ description: Fascontek
"^fastrax,.*":
description: Fastrax Oy
"^fcs,.*":
@@ -502,6 +512,8 @@
description: Fujitsu Ltd.
"^fxtec,.*":
description: FX Technology Ltd.
+ "^galaxycore,.*":
+ description: GalaxyCore Inc.
"^gardena,.*":
description: GARDENA GmbH
"^gateway,.*":
@@ -597,6 +609,8 @@
description: Hewlett Packard Enterprise
"^hsg,.*":
description: HannStar Display Co.
+ "^htc,.*":
+ description: HTC Corporation
"^huawei,.*":
description: Huawei Technologies Co., Ltd.
"^hugsun,.*":
@@ -1179,6 +1193,8 @@
description: Shenzhen Roofull Technology Co, Ltd
"^roseapplepi,.*":
description: RoseapplePi.org
+ "^rve,.*":
+ description: Recharge Véhicule Électrique (RVE) inc.
"^saef,.*":
description: Saef Technology Limited
"^samsung,.*":
@@ -1281,6 +1297,8 @@
description: Skyworks Solutions, Inc.
"^smartlabs,.*":
description: SmartLabs LLC
+ "^smi,.*":
+ description: Silicon Motion Technology Corporation
"^smsc,.*":
description: Standard Microsystems Corporation
"^snps,.*":
@@ -1381,6 +1399,8 @@
description: Technologic Systems
"^techstar,.*":
description: Shenzhen Techstar Electronics Co., Ltd.
+ "^techwell,.*":
+ description: Techwell, Inc.
"^teejet,.*":
description: TeeJet
"^teltonika,.*":
@@ -1434,6 +1454,8 @@
description: TPO
"^tq,.*":
description: TQ-Systems GmbH
+ "^transpeed,.*":
+ description: Transpeed
"^traverse,.*":
description: Traverse Technologies Australia Pty Ltd
"^tronfy,.*":
diff --git a/dts/upstream/Bindings/w1/amd,axi-1wire-host.yaml b/dts/upstream/Bindings/w1/amd,axi-1wire-host.yaml
new file mode 100644
index 0000000..ef70fa2
--- /dev/null
+++ b/dts/upstream/Bindings/w1/amd,axi-1wire-host.yaml
@@ -0,0 +1,44 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/w1/amd,axi-1wire-host.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: AMD AXI 1-wire bus host for programmable logic
+
+maintainers:
+ - Kris Chaplin <kris.chaplin@amd.com>
+
+properties:
+ compatible:
+ const: amd,axi-1wire-host
+
+ reg:
+ maxItems: 1
+
+ clocks:
+ maxItems: 1
+
+ interrupts:
+ maxItems: 1
+
+required:
+ - compatible
+ - reg
+ - clocks
+ - interrupts
+
+additionalProperties: false
+
+examples:
+ - |
+ #include <dt-bindings/interrupt-controller/arm-gic.h>
+
+ onewire@a0000000 {
+ compatible = "amd,axi-1wire-host";
+ reg = <0xa0000000 0x10000>;
+ clocks = <&zynqmp_clk 0x47>;
+ interrupts = <GIC_SPI 0x59 IRQ_TYPE_LEVEL_HIGH>;
+ };
+
+...
diff --git a/dts/upstream/Bindings/watchdog/allwinner,sun4i-a10-wdt.yaml b/dts/upstream/Bindings/watchdog/allwinner,sun4i-a10-wdt.yaml
index 274519f..64c8f73 100644
--- a/dts/upstream/Bindings/watchdog/allwinner,sun4i-a10-wdt.yaml
+++ b/dts/upstream/Bindings/watchdog/allwinner,sun4i-a10-wdt.yaml
@@ -6,13 +6,13 @@
title: Allwinner A10 Watchdog
-allOf:
- - $ref: watchdog.yaml#
-
maintainers:
- Chen-Yu Tsai <wens@csie.org>
- Maxime Ripard <mripard@kernel.org>
+allOf:
+ - $ref: watchdog.yaml#
+
properties:
compatible:
oneOf:
diff --git a/dts/upstream/Bindings/watchdog/alphascale,asm9260-wdt.yaml b/dts/upstream/Bindings/watchdog/alphascale,asm9260-wdt.yaml
index fea84f5..6425fe5 100644
--- a/dts/upstream/Bindings/watchdog/alphascale,asm9260-wdt.yaml
+++ b/dts/upstream/Bindings/watchdog/alphascale,asm9260-wdt.yaml
@@ -6,12 +6,12 @@
title: Alphascale asm9260 Watchdog timer
-allOf:
- - $ref: watchdog.yaml#
-
maintainers:
- Oleksij Rempel <linux@rempel-privat.de>
+allOf:
+ - $ref: watchdog.yaml#
+
properties:
compatible:
const: alphascale,asm9260-wdt
diff --git a/dts/upstream/Bindings/watchdog/apple,wdt.yaml b/dts/upstream/Bindings/watchdog/apple,wdt.yaml
index 9296811..21872e1 100644
--- a/dts/upstream/Bindings/watchdog/apple,wdt.yaml
+++ b/dts/upstream/Bindings/watchdog/apple,wdt.yaml
@@ -6,12 +6,12 @@
title: Apple SoC Watchdog
-allOf:
- - $ref: watchdog.yaml#
-
maintainers:
- Sven Peter <sven@svenpeter.dev>
+allOf:
+ - $ref: watchdog.yaml#
+
properties:
compatible:
items:
diff --git a/dts/upstream/Bindings/watchdog/arm-smc-wdt.yaml b/dts/upstream/Bindings/watchdog/arm-smc-wdt.yaml
index b557385..8e9d0b7 100644
--- a/dts/upstream/Bindings/watchdog/arm-smc-wdt.yaml
+++ b/dts/upstream/Bindings/watchdog/arm-smc-wdt.yaml
@@ -6,12 +6,12 @@
title: ARM Secure Monitor Call based watchdog
-allOf:
- - $ref: watchdog.yaml#
-
maintainers:
- Julius Werner <jwerner@chromium.org>
+allOf:
+ - $ref: watchdog.yaml#
+
properties:
compatible:
enum:
diff --git a/dts/upstream/Bindings/watchdog/brcm,bcm7038-wdt.yaml b/dts/upstream/Bindings/watchdog/brcm,bcm7038-wdt.yaml
index 526ff90..e898167 100644
--- a/dts/upstream/Bindings/watchdog/brcm,bcm7038-wdt.yaml
+++ b/dts/upstream/Bindings/watchdog/brcm,bcm7038-wdt.yaml
@@ -6,14 +6,14 @@
title: BCM63xx and BCM7038 watchdog timer
-allOf:
- - $ref: watchdog.yaml#
-
maintainers:
- Florian Fainelli <f.fainelli@gmail.com>
- Justin Chen <justinpopo6@gmail.com>
- Rafał Miłecki <rafal@milecki.pl>
+allOf:
+ - $ref: watchdog.yaml#
+
properties:
compatible:
enum:
@@ -29,11 +29,11 @@
The clock running the watchdog. If no clock is found the driver will
default to 27000000 Hz.
-unevaluatedProperties: false
-
required:
- reg
+unevaluatedProperties: false
+
examples:
- |
watchdog@f040a7e8 {
diff --git a/dts/upstream/Bindings/watchdog/cnxt,cx92755-wdt.yaml b/dts/upstream/Bindings/watchdog/cnxt,cx92755-wdt.yaml
index 1844d7e..13236ee 100644
--- a/dts/upstream/Bindings/watchdog/cnxt,cx92755-wdt.yaml
+++ b/dts/upstream/Bindings/watchdog/cnxt,cx92755-wdt.yaml
@@ -12,12 +12,12 @@
timer counters. The first timer (called "Timer A") is the only one that can be
used as watchdog.
-allOf:
- - $ref: watchdog.yaml#
-
maintainers:
- Baruch Siach <baruch@tkos.co.il>
+allOf:
+ - $ref: watchdog.yaml#
+
properties:
compatible:
const: cnxt,cx92755-wdt
diff --git a/dts/upstream/Bindings/watchdog/dlg,da9062-watchdog.yaml b/dts/upstream/Bindings/watchdog/dlg,da9062-watchdog.yaml
index f058628..c8f6981 100644
--- a/dts/upstream/Bindings/watchdog/dlg,da9062-watchdog.yaml
+++ b/dts/upstream/Bindings/watchdog/dlg,da9062-watchdog.yaml
@@ -4,7 +4,7 @@
$id: http://devicetree.org/schemas/watchdog/dlg,da9062-watchdog.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
-title: Dialog Semiconductor DA9062/61 Watchdog Timer
+title: Dialog Semiconductor DA906{1,2,3} Watchdog Timer
maintainers:
- Steve Twiss <stwiss.opensource@diasemi.com>
@@ -14,9 +14,13 @@
properties:
compatible:
- enum:
- - dlg,da9061-watchdog
- - dlg,da9062-watchdog
+ oneOf:
+ - enum:
+ - dlg,da9062-watchdog
+ - dlg,da9063-watchdog
+ - items:
+ - const: dlg,da9061-watchdog
+ - const: dlg,da9062-watchdog
dlg,use-sw-pm:
type: boolean
diff --git a/dts/upstream/Bindings/watchdog/intel,keembay-wdt.yaml b/dts/upstream/Bindings/watchdog/intel,keembay-wdt.yaml
index 1437ff8..8231dde 100644
--- a/dts/upstream/Bindings/watchdog/intel,keembay-wdt.yaml
+++ b/dts/upstream/Bindings/watchdog/intel,keembay-wdt.yaml
@@ -9,6 +9,9 @@
maintainers:
- Wan Ahmad Zainie <wan.ahmad.zainie.wan.mohamad@intel.com>
+allOf:
+ - $ref: watchdog.yaml#
+
properties:
compatible:
enum:
@@ -37,7 +40,7 @@
- interrupt-names
- clocks
-additionalProperties: false
+unevaluatedProperties: false
examples:
- |
diff --git a/dts/upstream/Bindings/watchdog/maxim,max63xx.yaml b/dts/upstream/Bindings/watchdog/maxim,max63xx.yaml
index 1a6490c..442c21f 100644
--- a/dts/upstream/Bindings/watchdog/maxim,max63xx.yaml
+++ b/dts/upstream/Bindings/watchdog/maxim,max63xx.yaml
@@ -6,14 +6,14 @@
title: Maxim 63xx Watchdog Timers
-allOf:
- - $ref: watchdog.yaml#
- - $ref: /schemas/memory-controllers/mc-peripheral-props.yaml#
-
maintainers:
- Marc Zyngier <maz@kernel.org>
- Linus Walleij <linus.walleij@linaro.org>
+allOf:
+ - $ref: watchdog.yaml#
+ - $ref: /schemas/memory-controllers/mc-peripheral-props.yaml#
+
properties:
compatible:
enum:
diff --git a/dts/upstream/Bindings/watchdog/mediatek,mtk-wdt.yaml b/dts/upstream/Bindings/watchdog/mediatek,mtk-wdt.yaml
index cc50283..8d25202 100644
--- a/dts/upstream/Bindings/watchdog/mediatek,mtk-wdt.yaml
+++ b/dts/upstream/Bindings/watchdog/mediatek,mtk-wdt.yaml
@@ -25,6 +25,7 @@
- mediatek,mt6735-wdt
- mediatek,mt6795-wdt
- mediatek,mt7986-wdt
+ - mediatek,mt7988-wdt
- mediatek,mt8183-wdt
- mediatek,mt8186-wdt
- mediatek,mt8188-wdt
diff --git a/dts/upstream/Bindings/watchdog/nxp,pnx4008-wdt.yaml b/dts/upstream/Bindings/watchdog/nxp,pnx4008-wdt.yaml
new file mode 100644
index 0000000..35ef940
--- /dev/null
+++ b/dts/upstream/Bindings/watchdog/nxp,pnx4008-wdt.yaml
@@ -0,0 +1,34 @@
+# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/watchdog/nxp,pnx4008-wdt.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: NXP PNX watchdog timer
+
+maintainers:
+ - Roland Stigge <stigge@antcom.de>
+
+allOf:
+ - $ref: watchdog.yaml#
+
+properties:
+ compatible:
+ const: nxp,pnx4008-wdt
+
+ reg:
+ maxItems: 1
+
+required:
+ - compatible
+ - reg
+
+unevaluatedProperties: false
+
+examples:
+ - |
+ watchdog@4003c000 {
+ compatible = "nxp,pnx4008-wdt";
+ reg = <0x4003c000 0x1000>;
+ timeout-sec = <10>;
+ };
diff --git a/dts/upstream/Bindings/watchdog/pnx4008-wdt.txt b/dts/upstream/Bindings/watchdog/pnx4008-wdt.txt
deleted file mode 100644
index 4b76bec..0000000
--- a/dts/upstream/Bindings/watchdog/pnx4008-wdt.txt
+++ /dev/null
@@ -1,17 +0,0 @@
-* NXP PNX watchdog timer
-
-Required properties:
-- compatible: must be "nxp,pnx4008-wdt"
-- reg: physical base address of the controller and length of memory mapped
- region.
-
-Optional properties:
-- timeout-sec: contains the watchdog timeout in seconds.
-
-Example:
-
- watchdog@4003c000 {
- compatible = "nxp,pnx4008-wdt";
- reg = <0x4003C000 0x1000>;
- timeout-sec = <10>;
- };
diff --git a/dts/upstream/Bindings/watchdog/qca,ar7130-wdt.yaml b/dts/upstream/Bindings/watchdog/qca,ar7130-wdt.yaml
new file mode 100644
index 0000000..82040ca
--- /dev/null
+++ b/dts/upstream/Bindings/watchdog/qca,ar7130-wdt.yaml
@@ -0,0 +1,33 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/watchdog/qca,ar7130-wdt.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Qualcomm Atheros AR7130 Watchdog Timer (WDT) Controller
+
+maintainers:
+ - Gabor Juhos <juhosg@openwrt.org>
+
+allOf:
+ - $ref: watchdog.yaml#
+
+properties:
+ compatible:
+ const: qca,ar7130-wdt
+
+ reg:
+ maxItems: 1
+
+required:
+ - compatible
+ - reg
+
+unevaluatedProperties: false
+
+examples:
+ - |
+ watchdog@18060008 {
+ compatible = "qca,ar7130-wdt";
+ reg = <0x18060008 0x8>;
+ };
diff --git a/dts/upstream/Bindings/watchdog/qca-ar7130-wdt.txt b/dts/upstream/Bindings/watchdog/qca-ar7130-wdt.txt
deleted file mode 100644
index 7a89e5f..0000000
--- a/dts/upstream/Bindings/watchdog/qca-ar7130-wdt.txt
+++ /dev/null
@@ -1,13 +0,0 @@
-* Qualcomm Atheros AR7130 Watchdog Timer (WDT) Controller
-
-Required properties:
-- compatible: must be "qca,ar7130-wdt"
-- reg: physical base address of the controller and length of memory mapped
- region.
-
-Example:
-
-wdt@18060008 {
- compatible = "qca,ar9330-wdt", "qca,ar7130-wdt";
- reg = <0x18060008 0x8>;
-};
diff --git a/dts/upstream/Bindings/watchdog/qcom,pm8916-wdt.yaml b/dts/upstream/Bindings/watchdog/qcom,pm8916-wdt.yaml
index 568eb84..dc6af20 100644
--- a/dts/upstream/Bindings/watchdog/qcom,pm8916-wdt.yaml
+++ b/dts/upstream/Bindings/watchdog/qcom,pm8916-wdt.yaml
@@ -30,22 +30,27 @@
#include <dt-bindings/interrupt-controller/irq.h>
#include <dt-bindings/spmi/spmi.h>
- pmic@0 {
- compatible = "qcom,pm8916", "qcom,spmi-pmic";
- reg = <0x0 SPMI_USID>;
- #address-cells = <1>;
+ spmi {
+ #address-cells = <2>;
#size-cells = <0>;
- pon@800 {
- compatible = "qcom,pm8916-pon";
- reg = <0x800>;
- mode-bootloader = <0x2>;
- mode-recovery = <0x1>;
+ pmic@0 {
+ compatible = "qcom,pm8916", "qcom,spmi-pmic";
+ reg = <0x0 SPMI_USID>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ pon@800 {
+ compatible = "qcom,pm8916-pon";
+ reg = <0x800>;
+ mode-bootloader = <0x2>;
+ mode-recovery = <0x1>;
- watchdog {
- compatible = "qcom,pm8916-wdt";
- interrupts = <0x0 0x8 6 IRQ_TYPE_EDGE_RISING>;
- timeout-sec = <60>;
+ watchdog {
+ compatible = "qcom,pm8916-wdt";
+ interrupts = <0x0 0x8 6 IRQ_TYPE_EDGE_RISING>;
+ timeout-sec = <60>;
+ };
};
};
};
diff --git a/dts/upstream/Bindings/watchdog/qcom-wdt.yaml b/dts/upstream/Bindings/watchdog/qcom-wdt.yaml
index c12bc85..a4f35c5 100644
--- a/dts/upstream/Bindings/watchdog/qcom-wdt.yaml
+++ b/dts/upstream/Bindings/watchdog/qcom-wdt.yaml
@@ -123,7 +123,7 @@
compatible = "qcom,apss-wdt-sm8150", "qcom,kpss-wdt";
reg = <0x17c10000 0x1000>;
clocks = <&sleep_clk>;
- interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>;
+ interrupts = <GIC_SPI 0 IRQ_TYPE_EDGE_RISING>;
timeout-sec = <10>;
};
diff --git a/dts/upstream/Bindings/watchdog/realtek,rtd119x.txt b/dts/upstream/Bindings/watchdog/realtek,rtd119x.txt
deleted file mode 100644
index 0565305..0000000
--- a/dts/upstream/Bindings/watchdog/realtek,rtd119x.txt
+++ /dev/null
@@ -1,17 +0,0 @@
-Realtek RTD1295 Watchdog
-========================
-
-Required properties:
-
-- compatible : Should be "realtek,rtd1295-watchdog"
-- reg : Specifies the physical base address and size of registers
-- clocks : Specifies one clock input
-
-
-Example:
-
- watchdog@98007680 {
- compatible = "realtek,rtd1295-watchdog";
- reg = <0x98007680 0x100>;
- clocks = <&osc27M>;
- };
diff --git a/dts/upstream/Bindings/watchdog/realtek,rtd1295-watchdog.yaml b/dts/upstream/Bindings/watchdog/realtek,rtd1295-watchdog.yaml
new file mode 100644
index 0000000..2a0ea16
--- /dev/null
+++ b/dts/upstream/Bindings/watchdog/realtek,rtd1295-watchdog.yaml
@@ -0,0 +1,38 @@
+# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/watchdog/realtek,rtd1295-watchdog.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Realtek RTD1295 Watchdog
+
+maintainers:
+ - Andreas Färber <afaerber@suse.de>
+
+allOf:
+ - $ref: watchdog.yaml#
+
+properties:
+ compatible:
+ const: realtek,rtd1295-watchdog
+
+ reg:
+ maxItems: 1
+
+ clocks:
+ maxItems: 1
+
+required:
+ - compatible
+ - reg
+ - clocks
+
+unevaluatedProperties: false
+
+examples:
+ - |
+ watchdog@98007680 {
+ compatible = "realtek,rtd1295-watchdog";
+ reg = <0x98007680 0x100>;
+ clocks = <&osc27M>;
+ };
diff --git a/dts/upstream/Bindings/watchdog/samsung-wdt.yaml b/dts/upstream/Bindings/watchdog/samsung-wdt.yaml
index 8fb6656..77a5ddd 100644
--- a/dts/upstream/Bindings/watchdog/samsung-wdt.yaml
+++ b/dts/upstream/Bindings/watchdog/samsung-wdt.yaml
@@ -16,14 +16,20 @@
properties:
compatible:
- enum:
- - samsung,s3c2410-wdt # for S3C2410
- - samsung,s3c6410-wdt # for S3C6410, S5PV210 and Exynos4
- - samsung,exynos5250-wdt # for Exynos5250
- - samsung,exynos5420-wdt # for Exynos5420
- - samsung,exynos7-wdt # for Exynos7
- - samsung,exynos850-wdt # for Exynos850
- - samsung,exynosautov9-wdt # for Exynosautov9
+ oneOf:
+ - enum:
+ - google,gs101-wdt # for Google gs101
+ - samsung,s3c2410-wdt # for S3C2410
+ - samsung,s3c6410-wdt # for S3C6410, S5PV210 and Exynos4
+ - samsung,exynos5250-wdt # for Exynos5250
+ - samsung,exynos5420-wdt # for Exynos5420
+ - samsung,exynos7-wdt # for Exynos7
+ - samsung,exynos850-wdt # for Exynos850
+ - samsung,exynosautov9-wdt # for Exynosautov9
+ - items:
+ - enum:
+ - tesla,fsd-wdt
+ - const: samsung,exynos7-wdt
reg:
maxItems: 1
@@ -42,13 +48,14 @@
samsung,cluster-index:
$ref: /schemas/types.yaml#/definitions/uint32
description:
- Index of CPU cluster on which watchdog is running (in case of Exynos850)
+ Index of CPU cluster on which watchdog is running (in case of Exynos850
+ or Google gs101).
samsung,syscon-phandle:
$ref: /schemas/types.yaml#/definitions/phandle
description:
Phandle to the PMU system controller node (in case of Exynos5250,
- Exynos5420, Exynos7 and Exynos850).
+ Exynos5420, Exynos7, Exynos850 and gs101).
required:
- compatible
@@ -64,6 +71,7 @@
compatible:
contains:
enum:
+ - google,gs101-wdt
- samsung,exynos5250-wdt
- samsung,exynos5420-wdt
- samsung,exynos7-wdt
@@ -77,6 +85,7 @@
compatible:
contains:
enum:
+ - google,gs101-wdt
- samsung,exynos850-wdt
- samsung,exynosautov9-wdt
then:
diff --git a/dts/upstream/Bindings/watchdog/snps,dw-wdt.yaml b/dts/upstream/Bindings/watchdog/snps,dw-wdt.yaml
index 76eceed..c7aab04 100644
--- a/dts/upstream/Bindings/watchdog/snps,dw-wdt.yaml
+++ b/dts/upstream/Bindings/watchdog/snps,dw-wdt.yaml
@@ -6,12 +6,12 @@
title: Synopsys Designware Watchdog Timer
-allOf:
- - $ref: watchdog.yaml#
-
maintainers:
- Jamie Iles <jamie@jamieiles.com>
+allOf:
+ - $ref: watchdog.yaml#
+
properties:
compatible:
oneOf:
@@ -73,13 +73,13 @@
minItems: 16
maxItems: 16
-unevaluatedProperties: false
-
required:
- compatible
- reg
- clocks
+unevaluatedProperties: false
+
examples:
- |
watchdog@ffd02000 {
diff --git a/dts/upstream/Bindings/watchdog/technologic,ts7200-wdt.yaml b/dts/upstream/Bindings/watchdog/technologic,ts7200-wdt.yaml
new file mode 100644
index 0000000..7e4bfef
--- /dev/null
+++ b/dts/upstream/Bindings/watchdog/technologic,ts7200-wdt.yaml
@@ -0,0 +1,45 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/watchdog/technologic,ts7200-wdt.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Technologic Systems TS-72xx based SBCs watchdog
+
+maintainers:
+ - Nikita Shubin <nikita.shubin@maquefel.me>
+
+allOf:
+ - $ref: watchdog.yaml#
+
+properties:
+ compatible:
+ oneOf:
+ - const: technologic,ts7200-wdt
+ - items:
+ - enum:
+ - technologic,ts7300-wdt
+ - technologic,ts7260-wdt
+ - technologic,ts7250-wdt
+ - const: technologic,ts7200-wdt
+
+ reg:
+ items:
+ - description: control register
+ - description: feed register
+
+required:
+ - compatible
+ - reg
+
+unevaluatedProperties: false
+
+examples:
+ - |
+ watchdog@23800000 {
+ compatible = "technologic,ts7200-wdt";
+ reg = <0x23800000 0x01>, <0x23c00000 0x01>;
+ timeout-sec = <30>;
+ };
+
+...
diff --git a/dts/upstream/include/dt-bindings/arm/qcom,ids.h b/dts/upstream/include/dt-bindings/arm/qcom,ids.h
index f724834..51e0f60 100644
--- a/dts/upstream/include/dt-bindings/arm/qcom,ids.h
+++ b/dts/upstream/include/dt-bindings/arm/qcom,ids.h
@@ -255,6 +255,7 @@
#define QCOM_ID_SA8775P 534
#define QCOM_ID_QRU1000 539
#define QCOM_ID_QDU1000 545
+#define QCOM_ID_SM8650 557
#define QCOM_ID_SM4450 568
#define QCOM_ID_QDU1010 587
#define QCOM_ID_QRU1032 588
diff --git a/dts/upstream/include/dt-bindings/clock/g12a-clkc.h b/dts/upstream/include/dt-bindings/clock/g12a-clkc.h
index 387767f..fd09819 100644
--- a/dts/upstream/include/dt-bindings/clock/g12a-clkc.h
+++ b/dts/upstream/include/dt-bindings/clock/g12a-clkc.h
@@ -279,5 +279,13 @@
#define CLKID_MIPI_DSI_PXCLK_DIV 268
#define CLKID_MIPI_DSI_PXCLK_SEL 269
#define CLKID_MIPI_DSI_PXCLK 270
+#define CLKID_CTS_ENCL 271
+#define CLKID_CTS_ENCL_SEL 272
+#define CLKID_MIPI_ISP_DIV 273
+#define CLKID_MIPI_ISP_SEL 274
+#define CLKID_MIPI_ISP 275
+#define CLKID_MIPI_ISP_GATE 276
+#define CLKID_MIPI_ISP_CSI_PHY0 277
+#define CLKID_MIPI_ISP_CSI_PHY1 278
#endif /* __G12A_CLKC_H */
diff --git a/dts/upstream/include/dt-bindings/clock/google,gs101.h b/dts/upstream/include/dt-bindings/clock/google,gs101.h
new file mode 100644
index 0000000..21adec2
--- /dev/null
+++ b/dts/upstream/include/dt-bindings/clock/google,gs101.h
@@ -0,0 +1,392 @@
+/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */
+/*
+ * Copyright (C) 2023 Linaro Ltd.
+ * Author: Peter Griffin <peter.griffin@linaro.org>
+ *
+ * Device Tree binding constants for Google gs101 clock controller.
+ */
+
+#ifndef _DT_BINDINGS_CLOCK_GOOGLE_GS101_H
+#define _DT_BINDINGS_CLOCK_GOOGLE_GS101_H
+
+/* CMU_TOP PLL */
+#define CLK_FOUT_SHARED0_PLL 1
+#define CLK_FOUT_SHARED1_PLL 2
+#define CLK_FOUT_SHARED2_PLL 3
+#define CLK_FOUT_SHARED3_PLL 4
+#define CLK_FOUT_SPARE_PLL 5
+
+/* CMU_TOP MUX */
+#define CLK_MOUT_PLL_SHARED0 6
+#define CLK_MOUT_PLL_SHARED1 7
+#define CLK_MOUT_PLL_SHARED2 8
+#define CLK_MOUT_PLL_SHARED3 9
+#define CLK_MOUT_PLL_SPARE 10
+#define CLK_MOUT_CMU_BO_BUS 11
+#define CLK_MOUT_CMU_BUS0_BUS 12
+#define CLK_MOUT_CMU_BUS1_BUS 13
+#define CLK_MOUT_CMU_BUS2_BUS 14
+#define CLK_MOUT_CMU_CIS_CLK0 15
+#define CLK_MOUT_CMU_CIS_CLK1 16
+#define CLK_MOUT_CMU_CIS_CLK2 17
+#define CLK_MOUT_CMU_CIS_CLK3 18
+#define CLK_MOUT_CMU_CIS_CLK4 19
+#define CLK_MOUT_CMU_CIS_CLK5 20
+#define CLK_MOUT_CMU_CIS_CLK6 21
+#define CLK_MOUT_CMU_CIS_CLK7 22
+#define CLK_MOUT_CMU_CMU_BOOST 23
+#define CLK_MOUT_CMU_BOOST_OPTION1 24
+#define CLK_MOUT_CMU_CORE_BUS 25
+#define CLK_MOUT_CMU_CPUCL0_DBG 26
+#define CLK_MOUT_CMU_CPUCL0_SWITCH 27
+#define CLK_MOUT_CMU_CPUCL1_SWITCH 28
+#define CLK_MOUT_CMU_CPUCL2_SWITCH 29
+#define CLK_MOUT_CMU_CSIS_BUS 30
+#define CLK_MOUT_CMU_DISP_BUS 31
+#define CLK_MOUT_CMU_DNS_BUS 32
+#define CLK_MOUT_CMU_DPU_BUS 33
+#define CLK_MOUT_CMU_EH_BUS 34
+#define CLK_MOUT_CMU_G2D_G2D 35
+#define CLK_MOUT_CMU_G2D_MSCL 36
+#define CLK_MOUT_CMU_G3AA_G3AA 37
+#define CLK_MOUT_CMU_G3D_BUSD 38
+#define CLK_MOUT_CMU_G3D_GLB 39
+#define CLK_MOUT_CMU_G3D_SWITCH 40
+#define CLK_MOUT_CMU_GDC_GDC0 41
+#define CLK_MOUT_CMU_GDC_GDC1 42
+#define CLK_MOUT_CMU_GDC_SCSC 43
+#define CLK_MOUT_CMU_HPM 44
+#define CLK_MOUT_CMU_HSI0_BUS 45
+#define CLK_MOUT_CMU_HSI0_DPGTC 46
+#define CLK_MOUT_CMU_HSI0_USB31DRD 47
+#define CLK_MOUT_CMU_HSI0_USBDPDBG 48
+#define CLK_MOUT_CMU_HSI1_BUS 49
+#define CLK_MOUT_CMU_HSI1_PCIE 50
+#define CLK_MOUT_CMU_HSI2_BUS 51
+#define CLK_MOUT_CMU_HSI2_MMC_CARD 52
+#define CLK_MOUT_CMU_HSI2_PCIE 53
+#define CLK_MOUT_CMU_HSI2_UFS_EMBD 54
+#define CLK_MOUT_CMU_IPP_BUS 55
+#define CLK_MOUT_CMU_ITP_BUS 56
+#define CLK_MOUT_CMU_MCSC_ITSC 57
+#define CLK_MOUT_CMU_MCSC_MCSC 58
+#define CLK_MOUT_CMU_MFC_MFC 59
+#define CLK_MOUT_CMU_MIF_BUSP 60
+#define CLK_MOUT_CMU_MIF_SWITCH 61
+#define CLK_MOUT_CMU_MISC_BUS 62
+#define CLK_MOUT_CMU_MISC_SSS 63
+#define CLK_MOUT_CMU_PDP_BUS 64
+#define CLK_MOUT_CMU_PDP_VRA 65
+#define CLK_MOUT_CMU_PERIC0_BUS 66
+#define CLK_MOUT_CMU_PERIC0_IP 67
+#define CLK_MOUT_CMU_PERIC1_BUS 68
+#define CLK_MOUT_CMU_PERIC1_IP 69
+#define CLK_MOUT_CMU_TNR_BUS 70
+#define CLK_MOUT_CMU_TOP_BOOST_OPTION1 71
+#define CLK_MOUT_CMU_TOP_CMUREF 72
+#define CLK_MOUT_CMU_TPU_BUS 73
+#define CLK_MOUT_CMU_TPU_TPU 74
+#define CLK_MOUT_CMU_TPU_TPUCTL 75
+#define CLK_MOUT_CMU_TPU_UART 76
+#define CLK_MOUT_CMU_CMUREF 77
+
+/* CMU_TOP Dividers */
+#define CLK_DOUT_CMU_BO_BUS 78
+#define CLK_DOUT_CMU_BUS0_BUS 79
+#define CLK_DOUT_CMU_BUS1_BUS 80
+#define CLK_DOUT_CMU_BUS2_BUS 81
+#define CLK_DOUT_CMU_CIS_CLK0 82
+#define CLK_DOUT_CMU_CIS_CLK1 83
+#define CLK_DOUT_CMU_CIS_CLK2 84
+#define CLK_DOUT_CMU_CIS_CLK3 85
+#define CLK_DOUT_CMU_CIS_CLK4 86
+#define CLK_DOUT_CMU_CIS_CLK5 87
+#define CLK_DOUT_CMU_CIS_CLK6 88
+#define CLK_DOUT_CMU_CIS_CLK7 89
+#define CLK_DOUT_CMU_CORE_BUS 90
+#define CLK_DOUT_CMU_CPUCL0_DBG 91
+#define CLK_DOUT_CMU_CPUCL0_SWITCH 92
+#define CLK_DOUT_CMU_CPUCL1_SWITCH 93
+#define CLK_DOUT_CMU_CPUCL2_SWITCH 94
+#define CLK_DOUT_CMU_CSIS_BUS 95
+#define CLK_DOUT_CMU_DISP_BUS 96
+#define CLK_DOUT_CMU_DNS_BUS 97
+#define CLK_DOUT_CMU_DPU_BUS 98
+#define CLK_DOUT_CMU_EH_BUS 99
+#define CLK_DOUT_CMU_G2D_G2D 100
+#define CLK_DOUT_CMU_G2D_MSCL 101
+#define CLK_DOUT_CMU_G3AA_G3AA 102
+#define CLK_DOUT_CMU_G3D_BUSD 103
+#define CLK_DOUT_CMU_G3D_GLB 104
+#define CLK_DOUT_CMU_G3D_SWITCH 105
+#define CLK_DOUT_CMU_GDC_GDC0 106
+#define CLK_DOUT_CMU_GDC_GDC1 107
+#define CLK_DOUT_CMU_GDC_SCSC 108
+#define CLK_DOUT_CMU_CMU_HPM 109
+#define CLK_DOUT_CMU_HSI0_BUS 110
+#define CLK_DOUT_CMU_HSI0_DPGTC 111
+#define CLK_DOUT_CMU_HSI0_USB31DRD 112
+#define CLK_DOUT_CMU_HSI0_USBDPDBG 113
+#define CLK_DOUT_CMU_HSI1_BUS 114
+#define CLK_DOUT_CMU_HSI1_PCIE 115
+#define CLK_DOUT_CMU_HSI2_BUS 116
+#define CLK_DOUT_CMU_HSI2_MMC_CARD 117
+#define CLK_DOUT_CMU_HSI2_PCIE 118
+#define CLK_DOUT_CMU_HSI2_UFS_EMBD 119
+#define CLK_DOUT_CMU_IPP_BUS 120
+#define CLK_DOUT_CMU_ITP_BUS 121
+#define CLK_DOUT_CMU_MCSC_ITSC 122
+#define CLK_DOUT_CMU_MCSC_MCSC 123
+#define CLK_DOUT_CMU_MFC_MFC 124
+#define CLK_DOUT_CMU_MIF_BUSP 125
+#define CLK_DOUT_CMU_MISC_BUS 126
+#define CLK_DOUT_CMU_MISC_SSS 127
+#define CLK_DOUT_CMU_OTP 128
+#define CLK_DOUT_CMU_PDP_BUS 129
+#define CLK_DOUT_CMU_PDP_VRA 130
+#define CLK_DOUT_CMU_PERIC0_BUS 131
+#define CLK_DOUT_CMU_PERIC0_IP 132
+#define CLK_DOUT_CMU_PERIC1_BUS 133
+#define CLK_DOUT_CMU_PERIC1_IP 134
+#define CLK_DOUT_CMU_TNR_BUS 135
+#define CLK_DOUT_CMU_TPU_BUS 136
+#define CLK_DOUT_CMU_TPU_TPU 137
+#define CLK_DOUT_CMU_TPU_TPUCTL 138
+#define CLK_DOUT_CMU_TPU_UART 139
+#define CLK_DOUT_CMU_CMU_BOOST 140
+#define CLK_DOUT_CMU_CMU_CMUREF 141
+#define CLK_DOUT_CMU_SHARED0_DIV2 142
+#define CLK_DOUT_CMU_SHARED0_DIV3 143
+#define CLK_DOUT_CMU_SHARED0_DIV4 144
+#define CLK_DOUT_CMU_SHARED0_DIV5 145
+#define CLK_DOUT_CMU_SHARED1_DIV2 146
+#define CLK_DOUT_CMU_SHARED1_DIV3 147
+#define CLK_DOUT_CMU_SHARED1_DIV4 148
+#define CLK_DOUT_CMU_SHARED2_DIV2 149
+#define CLK_DOUT_CMU_SHARED3_DIV2 150
+
+/* CMU_TOP Gates */
+#define CLK_GOUT_CMU_BUS0_BOOST 151
+#define CLK_GOUT_CMU_BUS1_BOOST 152
+#define CLK_GOUT_CMU_BUS2_BOOST 153
+#define CLK_GOUT_CMU_CORE_BOOST 154
+#define CLK_GOUT_CMU_CPUCL0_BOOST 155
+#define CLK_GOUT_CMU_CPUCL1_BOOST 156
+#define CLK_GOUT_CMU_CPUCL2_BOOST 157
+#define CLK_GOUT_CMU_MIF_BOOST 158
+#define CLK_GOUT_CMU_MIF_SWITCH 159
+#define CLK_GOUT_CMU_BO_BUS 160
+#define CLK_GOUT_CMU_BUS0_BUS 161
+#define CLK_GOUT_CMU_BUS1_BUS 162
+#define CLK_GOUT_CMU_BUS2_BUS 163
+#define CLK_GOUT_CMU_CIS_CLK0 164
+#define CLK_GOUT_CMU_CIS_CLK1 165
+#define CLK_GOUT_CMU_CIS_CLK2 166
+#define CLK_GOUT_CMU_CIS_CLK3 167
+#define CLK_GOUT_CMU_CIS_CLK4 168
+#define CLK_GOUT_CMU_CIS_CLK5 169
+#define CLK_GOUT_CMU_CIS_CLK6 170
+#define CLK_GOUT_CMU_CIS_CLK7 171
+#define CLK_GOUT_CMU_CMU_BOOST 172
+#define CLK_GOUT_CMU_CORE_BUS 173
+#define CLK_GOUT_CMU_CPUCL0_DBG 174
+#define CLK_GOUT_CMU_CPUCL0_SWITCH 175
+#define CLK_GOUT_CMU_CPUCL1_SWITCH 176
+#define CLK_GOUT_CMU_CPUCL2_SWITCH 177
+#define CLK_GOUT_CMU_CSIS_BUS 178
+#define CLK_GOUT_CMU_DISP_BUS 179
+#define CLK_GOUT_CMU_DNS_BUS 180
+#define CLK_GOUT_CMU_DPU_BUS 181
+#define CLK_GOUT_CMU_EH_BUS 182
+#define CLK_GOUT_CMU_G2D_G2D 183
+#define CLK_GOUT_CMU_G2D_MSCL 184
+#define CLK_GOUT_CMU_G3AA_G3AA 185
+#define CLK_GOUT_CMU_G3D_BUSD 186
+#define CLK_GOUT_CMU_G3D_GLB 187
+#define CLK_GOUT_CMU_G3D_SWITCH 188
+#define CLK_GOUT_CMU_GDC_GDC0 189
+#define CLK_GOUT_CMU_GDC_GDC1 190
+#define CLK_GOUT_CMU_GDC_SCSC 191
+#define CLK_GOUT_CMU_HPM 192
+#define CLK_GOUT_CMU_HSI0_BUS 193
+#define CLK_GOUT_CMU_HSI0_DPGTC 194
+#define CLK_GOUT_CMU_HSI0_USB31DRD 195
+#define CLK_GOUT_CMU_HSI0_USBDPDBG 196
+#define CLK_GOUT_CMU_HSI1_BUS 197
+#define CLK_GOUT_CMU_HSI1_PCIE 198
+#define CLK_GOUT_CMU_HSI2_BUS 199
+#define CLK_GOUT_CMU_HSI2_MMC_CARD 200
+#define CLK_GOUT_CMU_HSI2_PCIE 201
+#define CLK_GOUT_CMU_HSI2_UFS_EMBD 202
+#define CLK_GOUT_CMU_IPP_BUS 203
+#define CLK_GOUT_CMU_ITP_BUS 204
+#define CLK_GOUT_CMU_MCSC_ITSC 205
+#define CLK_GOUT_CMU_MCSC_MCSC 206
+#define CLK_GOUT_CMU_MFC_MFC 207
+#define CLK_GOUT_CMU_MIF_BUSP 208
+#define CLK_GOUT_CMU_MISC_BUS 209
+#define CLK_GOUT_CMU_MISC_SSS 210
+#define CLK_GOUT_CMU_PDP_BUS 211
+#define CLK_GOUT_CMU_PDP_VRA 212
+#define CLK_GOUT_CMU_G3AA 213
+#define CLK_GOUT_CMU_PERIC0_BUS 214
+#define CLK_GOUT_CMU_PERIC0_IP 215
+#define CLK_GOUT_CMU_PERIC1_BUS 216
+#define CLK_GOUT_CMU_PERIC1_IP 217
+#define CLK_GOUT_CMU_TNR_BUS 218
+#define CLK_GOUT_CMU_TOP_CMUREF 219
+#define CLK_GOUT_CMU_TPU_BUS 220
+#define CLK_GOUT_CMU_TPU_TPU 221
+#define CLK_GOUT_CMU_TPU_TPUCTL 222
+#define CLK_GOUT_CMU_TPU_UART 223
+
+/* CMU_APM */
+#define CLK_MOUT_APM_FUNC 1
+#define CLK_MOUT_APM_FUNCSRC 2
+#define CLK_DOUT_APM_BOOST 3
+#define CLK_DOUT_APM_USI0_UART 4
+#define CLK_DOUT_APM_USI0_USI 5
+#define CLK_DOUT_APM_USI1_UART 6
+#define CLK_GOUT_APM_APM_CMU_APM_PCLK 7
+#define CLK_GOUT_BUS0_BOOST_OPTION1 8
+#define CLK_GOUT_CMU_BOOST_OPTION1 9
+#define CLK_GOUT_CORE_BOOST_OPTION1 10
+#define CLK_GOUT_APM_FUNC 11
+#define CLK_GOUT_APM_APBIF_GPIO_ALIVE_PCLK 12
+#define CLK_GOUT_APM_APBIF_GPIO_FAR_ALIVE_PCLK 13
+#define CLK_GOUT_APM_APBIF_PMU_ALIVE_PCLK 14
+#define CLK_GOUT_APM_APBIF_RTC_PCLK 15
+#define CLK_GOUT_APM_APBIF_TRTC_PCLK 16
+#define CLK_GOUT_APM_APM_USI0_UART_IPCLK 17
+#define CLK_GOUT_APM_APM_USI0_UART_PCLK 18
+#define CLK_GOUT_APM_APM_USI0_USI_IPCLK 19
+#define CLK_GOUT_APM_APM_USI0_USI_PCLK 20
+#define CLK_GOUT_APM_APM_USI1_UART_IPCLK 21
+#define CLK_GOUT_APM_APM_USI1_UART_PCLK 22
+#define CLK_GOUT_APM_D_TZPC_APM_PCLK 23
+#define CLK_GOUT_APM_GPC_APM_PCLK 24
+#define CLK_GOUT_APM_GREBEINTEGRATION_HCLK 25
+#define CLK_GOUT_APM_INTMEM_ACLK 26
+#define CLK_GOUT_APM_INTMEM_PCLK 27
+#define CLK_GOUT_APM_LHM_AXI_G_SWD_I_CLK 28
+#define CLK_GOUT_APM_LHM_AXI_P_AOCAPM_I_CLK 29
+#define CLK_GOUT_APM_LHM_AXI_P_APM_I_CLK 30
+#define CLK_GOUT_APM_LHS_AXI_D_APM_I_CLK 31
+#define CLK_GOUT_APM_LHS_AXI_G_DBGCORE_I_CLK 32
+#define CLK_GOUT_APM_LHS_AXI_G_SCAN2DRAM_I_CLK 33
+#define CLK_GOUT_APM_MAILBOX_APM_AOC_PCLK 34
+#define CLK_GOUT_APM_MAILBOX_APM_AP_PCLK 35
+#define CLK_GOUT_APM_MAILBOX_APM_GSA_PCLK 36
+#define CLK_GOUT_APM_MAILBOX_APM_SWD_PCLK 37
+#define CLK_GOUT_APM_MAILBOX_APM_TPU_PCLK 38
+#define CLK_GOUT_APM_MAILBOX_AP_AOC_PCLK 39
+#define CLK_GOUT_APM_MAILBOX_AP_DBGCORE_PCLK 40
+#define CLK_GOUT_APM_PMU_INTR_GEN_PCLK 41
+#define CLK_GOUT_APM_ROM_CRC32_HOST_ACLK 42
+#define CLK_GOUT_APM_ROM_CRC32_HOST_PCLK 43
+#define CLK_GOUT_APM_CLK_APM_BUS_CLK 44
+#define CLK_GOUT_APM_CLK_APM_USI0_UART_CLK 45
+#define CLK_GOUT_APM_CLK_APM_USI0_USI_CLK 46
+#define CLK_GOUT_APM_CLK_APM_USI1_UART_CLK 47
+#define CLK_GOUT_APM_SPEEDY_APM_PCLK 48
+#define CLK_GOUT_APM_SPEEDY_SUB_APM_PCLK 49
+#define CLK_GOUT_APM_SSMT_D_APM_ACLK 50
+#define CLK_GOUT_APM_SSMT_D_APM_PCLK 51
+#define CLK_GOUT_APM_SSMT_G_DBGCORE_ACLK 52
+#define CLK_GOUT_APM_SSMT_G_DBGCORE_PCLK 53
+#define CLK_GOUT_APM_SS_DBGCORE_SS_DBGCORE_HCLK 54
+#define CLK_GOUT_APM_SYSMMU_D_APM_CLK_S2 55
+#define CLK_GOUT_APM_SYSREG_APM_PCLK 56
+#define CLK_GOUT_APM_UASC_APM_ACLK 57
+#define CLK_GOUT_APM_UASC_APM_PCLK 58
+#define CLK_GOUT_APM_UASC_DBGCORE_ACLK 59
+#define CLK_GOUT_APM_UASC_DBGCORE_PCLK 60
+#define CLK_GOUT_APM_UASC_G_SWD_ACLK 61
+#define CLK_GOUT_APM_UASC_G_SWD_PCLK 62
+#define CLK_GOUT_APM_UASC_P_AOCAPM_ACLK 63
+#define CLK_GOUT_APM_UASC_P_AOCAPM_PCLK 64
+#define CLK_GOUT_APM_UASC_P_APM_ACLK 65
+#define CLK_GOUT_APM_UASC_P_APM_PCLK 66
+#define CLK_GOUT_APM_WDT_APM_PCLK 67
+#define CLK_GOUT_APM_XIU_DP_APM_ACLK 68
+#define CLK_APM_PLL_DIV2_APM 69
+#define CLK_APM_PLL_DIV4_APM 70
+#define CLK_APM_PLL_DIV16_APM 71
+
+/* CMU_MISC */
+#define CLK_MOUT_MISC_BUS_USER 1
+#define CLK_MOUT_MISC_SSS_USER 2
+#define CLK_MOUT_MISC_GIC 3
+#define CLK_DOUT_MISC_BUSP 4
+#define CLK_DOUT_MISC_GIC 5
+#define CLK_GOUT_MISC_MISC_CMU_MISC_PCLK 6
+#define CLK_GOUT_MISC_OTP_CON_BIRA_I_OSCCLK 7
+#define CLK_GOUT_MISC_OTP_CON_BISR_I_OSCCLK 8
+#define CLK_GOUT_MISC_OTP_CON_TOP_I_OSCCLK 9
+#define CLK_GOUT_MISC_CLK_MISC_OSCCLK_CLK 10
+#define CLK_GOUT_MISC_ADM_AHB_SSS_HCLKM 11
+#define CLK_GOUT_MISC_AD_APB_DIT_PCLKM 12
+#define CLK_GOUT_MISC_AD_APB_PUF_PCLKM 13
+#define CLK_GOUT_MISC_DIT_ICLKL2A 14
+#define CLK_GOUT_MISC_D_TZPC_MISC_PCLK 15
+#define CLK_GOUT_MISC_GIC_GICCLK 16
+#define CLK_GOUT_MISC_GPC_MISC_PCLK 17
+#define CLK_GOUT_MISC_LHM_AST_ICC_CPUGIC_I_CLK 18
+#define CLK_GOUT_MISC_LHM_AXI_D_SSS_I_CLK 19
+#define CLK_GOUT_MISC_LHM_AXI_P_GIC_I_CLK 20
+#define CLK_GOUT_MISC_LHM_AXI_P_MISC_I_CLK 21
+#define CLK_GOUT_MISC_LHS_ACEL_D_MISC_I_CLK 22
+#define CLK_GOUT_MISC_LHS_AST_IRI_GICCPU_I_CLK 23
+#define CLK_GOUT_MISC_LHS_AXI_D_SSS_I_CLK 24
+#define CLK_GOUT_MISC_MCT_PCLK 25
+#define CLK_GOUT_MISC_OTP_CON_BIRA_PCLK 26
+#define CLK_GOUT_MISC_OTP_CON_BISR_PCLK 27
+#define CLK_GOUT_MISC_OTP_CON_TOP_PCLK 28
+#define CLK_GOUT_MISC_PDMA_ACLK 29
+#define CLK_GOUT_MISC_PPMU_DMA_ACLK 30
+#define CLK_GOUT_MISC_PPMU_MISC_ACLK 31
+#define CLK_GOUT_MISC_PPMU_MISC_PCLK 32
+#define CLK_GOUT_MISC_PUF_I_CLK 33
+#define CLK_GOUT_MISC_QE_DIT_ACLK 34
+#define CLK_GOUT_MISC_QE_DIT_PCLK 35
+#define CLK_GOUT_MISC_QE_PDMA_ACLK 36
+#define CLK_GOUT_MISC_QE_PDMA_PCLK 37
+#define CLK_GOUT_MISC_QE_PPMU_DMA_ACLK 38
+#define CLK_GOUT_MISC_QE_PPMU_DMA_PCLK 39
+#define CLK_GOUT_MISC_QE_RTIC_ACLK 40
+#define CLK_GOUT_MISC_QE_RTIC_PCLK 41
+#define CLK_GOUT_MISC_QE_SPDMA_ACLK 42
+#define CLK_GOUT_MISC_QE_SPDMA_PCLK 43
+#define CLK_GOUT_MISC_QE_SSS_ACLK 44
+#define CLK_GOUT_MISC_QE_SSS_PCLK 45
+#define CLK_GOUT_MISC_CLK_MISC_BUSD_CLK 46
+#define CLK_GOUT_MISC_CLK_MISC_BUSP_CLK 47
+#define CLK_GOUT_MISC_CLK_MISC_GIC_CLK 48
+#define CLK_GOUT_MISC_CLK_MISC_SSS_CLK 49
+#define CLK_GOUT_MISC_RTIC_I_ACLK 50
+#define CLK_GOUT_MISC_RTIC_I_PCLK 51
+#define CLK_GOUT_MISC_SPDMA_ACLK 52
+#define CLK_GOUT_MISC_SSMT_DIT_ACLK 53
+#define CLK_GOUT_MISC_SSMT_DIT_PCLK 54
+#define CLK_GOUT_MISC_SSMT_PDMA_ACLK 55
+#define CLK_GOUT_MISC_SSMT_PDMA_PCLK 56
+#define CLK_GOUT_MISC_SSMT_PPMU_DMA_ACLK 57
+#define CLK_GOUT_MISC_SSMT_PPMU_DMA_PCLK 58
+#define CLK_GOUT_MISC_SSMT_RTIC_ACLK 59
+#define CLK_GOUT_MISC_SSMT_RTIC_PCLK 60
+#define CLK_GOUT_MISC_SSMT_SPDMA_ACLK 61
+#define CLK_GOUT_MISC_SSMT_SPDMA_PCLK 62
+#define CLK_GOUT_MISC_SSMT_SSS_ACLK 63
+#define CLK_GOUT_MISC_SSMT_SSS_PCLK 64
+#define CLK_GOUT_MISC_SSS_I_ACLK 65
+#define CLK_GOUT_MISC_SSS_I_PCLK 66
+#define CLK_GOUT_MISC_SYSMMU_MISC_CLK_S2 67
+#define CLK_GOUT_MISC_SYSMMU_SSS_CLK_S1 68
+#define CLK_GOUT_MISC_SYSREG_MISC_PCLK 69
+#define CLK_GOUT_MISC_TMU_SUB_PCLK 70
+#define CLK_GOUT_MISC_TMU_TOP_PCLK 71
+#define CLK_GOUT_MISC_WDT_CLUSTER0_PCLK 72
+#define CLK_GOUT_MISC_WDT_CLUSTER1_PCLK 73
+#define CLK_GOUT_MISC_XIU_D_MISC_ACLK 74
+
+#endif /* _DT_BINDINGS_CLOCK_GOOGLE_GS101_H */
diff --git a/dts/upstream/include/dt-bindings/clock/mediatek,mt7988-clk.h b/dts/upstream/include/dt-bindings/clock/mediatek,mt7988-clk.h
new file mode 100644
index 0000000..63376e4
--- /dev/null
+++ b/dts/upstream/include/dt-bindings/clock/mediatek,mt7988-clk.h
@@ -0,0 +1,280 @@
+/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */
+/*
+ * Copyright (c) 2023 MediaTek Inc.
+ * Author: Sam Shih <sam.shih@mediatek.com>
+ * Author: Xiufeng Li <Xiufeng.Li@mediatek.com>
+ */
+
+#ifndef _DT_BINDINGS_CLK_MT7988_H
+#define _DT_BINDINGS_CLK_MT7988_H
+
+/* APMIXEDSYS */
+
+#define CLK_APMIXED_NETSYSPLL 0
+#define CLK_APMIXED_MPLL 1
+#define CLK_APMIXED_MMPLL 2
+#define CLK_APMIXED_APLL2 3
+#define CLK_APMIXED_NET1PLL 4
+#define CLK_APMIXED_NET2PLL 5
+#define CLK_APMIXED_WEDMCUPLL 6
+#define CLK_APMIXED_SGMPLL 7
+#define CLK_APMIXED_ARM_B 8
+#define CLK_APMIXED_CCIPLL2_B 9
+#define CLK_APMIXED_USXGMIIPLL 10
+#define CLK_APMIXED_MSDCPLL 11
+
+/* TOPCKGEN */
+
+#define CLK_TOP_XTAL 0
+#define CLK_TOP_XTAL_D2 1
+#define CLK_TOP_RTC_32K 2
+#define CLK_TOP_RTC_32P7K 3
+#define CLK_TOP_MPLL_D2 4
+#define CLK_TOP_MPLL_D3_D2 5
+#define CLK_TOP_MPLL_D4 6
+#define CLK_TOP_MPLL_D8 7
+#define CLK_TOP_MPLL_D8_D2 8
+#define CLK_TOP_MMPLL_D2 9
+#define CLK_TOP_MMPLL_D3_D5 10
+#define CLK_TOP_MMPLL_D4 11
+#define CLK_TOP_MMPLL_D6_D2 12
+#define CLK_TOP_MMPLL_D8 13
+#define CLK_TOP_APLL2_D4 14
+#define CLK_TOP_NET1PLL_D4 15
+#define CLK_TOP_NET1PLL_D5 16
+#define CLK_TOP_NET1PLL_D5_D2 17
+#define CLK_TOP_NET1PLL_D5_D4 18
+#define CLK_TOP_NET1PLL_D8 19
+#define CLK_TOP_NET1PLL_D8_D2 20
+#define CLK_TOP_NET1PLL_D8_D4 21
+#define CLK_TOP_NET1PLL_D8_D8 22
+#define CLK_TOP_NET1PLL_D8_D16 23
+#define CLK_TOP_NET2PLL_D2 24
+#define CLK_TOP_NET2PLL_D4 25
+#define CLK_TOP_NET2PLL_D4_D4 26
+#define CLK_TOP_NET2PLL_D4_D8 27
+#define CLK_TOP_NET2PLL_D6 28
+#define CLK_TOP_NET2PLL_D8 29
+#define CLK_TOP_NETSYS_SEL 30
+#define CLK_TOP_NETSYS_500M_SEL 31
+#define CLK_TOP_NETSYS_2X_SEL 32
+#define CLK_TOP_NETSYS_GSW_SEL 33
+#define CLK_TOP_ETH_GMII_SEL 34
+#define CLK_TOP_NETSYS_MCU_SEL 35
+#define CLK_TOP_NETSYS_PAO_2X_SEL 36
+#define CLK_TOP_EIP197_SEL 37
+#define CLK_TOP_AXI_INFRA_SEL 38
+#define CLK_TOP_UART_SEL 39
+#define CLK_TOP_EMMC_250M_SEL 40
+#define CLK_TOP_EMMC_400M_SEL 41
+#define CLK_TOP_SPI_SEL 42
+#define CLK_TOP_SPIM_MST_SEL 43
+#define CLK_TOP_NFI1X_SEL 44
+#define CLK_TOP_SPINFI_SEL 45
+#define CLK_TOP_PWM_SEL 46
+#define CLK_TOP_I2C_SEL 47
+#define CLK_TOP_PCIE_MBIST_250M_SEL 48
+#define CLK_TOP_PEXTP_TL_SEL 49
+#define CLK_TOP_PEXTP_TL_P1_SEL 50
+#define CLK_TOP_PEXTP_TL_P2_SEL 51
+#define CLK_TOP_PEXTP_TL_P3_SEL 52
+#define CLK_TOP_USB_SYS_SEL 53
+#define CLK_TOP_USB_SYS_P1_SEL 54
+#define CLK_TOP_USB_XHCI_SEL 55
+#define CLK_TOP_USB_XHCI_P1_SEL 56
+#define CLK_TOP_USB_FRMCNT_SEL 57
+#define CLK_TOP_USB_FRMCNT_P1_SEL 58
+#define CLK_TOP_AUD_SEL 59
+#define CLK_TOP_A1SYS_SEL 60
+#define CLK_TOP_AUD_L_SEL 61
+#define CLK_TOP_A_TUNER_SEL 62
+#define CLK_TOP_SSPXTP_SEL 63
+#define CLK_TOP_USB_PHY_SEL 64
+#define CLK_TOP_USXGMII_SBUS_0_SEL 65
+#define CLK_TOP_USXGMII_SBUS_1_SEL 66
+#define CLK_TOP_SGM_0_SEL 67
+#define CLK_TOP_SGM_SBUS_0_SEL 68
+#define CLK_TOP_SGM_1_SEL 69
+#define CLK_TOP_SGM_SBUS_1_SEL 70
+#define CLK_TOP_XFI_PHY_0_XTAL_SEL 71
+#define CLK_TOP_XFI_PHY_1_XTAL_SEL 72
+#define CLK_TOP_SYSAXI_SEL 73
+#define CLK_TOP_SYSAPB_SEL 74
+#define CLK_TOP_ETH_REFCK_50M_SEL 75
+#define CLK_TOP_ETH_SYS_200M_SEL 76
+#define CLK_TOP_ETH_SYS_SEL 77
+#define CLK_TOP_ETH_XGMII_SEL 78
+#define CLK_TOP_BUS_TOPS_SEL 79
+#define CLK_TOP_NPU_TOPS_SEL 80
+#define CLK_TOP_DRAMC_SEL 81
+#define CLK_TOP_DRAMC_MD32_SEL 82
+#define CLK_TOP_INFRA_F26M_SEL 83
+#define CLK_TOP_PEXTP_P0_SEL 84
+#define CLK_TOP_PEXTP_P1_SEL 85
+#define CLK_TOP_PEXTP_P2_SEL 86
+#define CLK_TOP_PEXTP_P3_SEL 87
+#define CLK_TOP_DA_XTP_GLB_P0_SEL 88
+#define CLK_TOP_DA_XTP_GLB_P1_SEL 89
+#define CLK_TOP_DA_XTP_GLB_P2_SEL 90
+#define CLK_TOP_DA_XTP_GLB_P3_SEL 91
+#define CLK_TOP_CKM_SEL 92
+#define CLK_TOP_DA_SEL 93
+#define CLK_TOP_PEXTP_SEL 94
+#define CLK_TOP_TOPS_P2_26M_SEL 95
+#define CLK_TOP_MCUSYS_BACKUP_625M_SEL 96
+#define CLK_TOP_NETSYS_SYNC_250M_SEL 97
+#define CLK_TOP_MACSEC_SEL 98
+#define CLK_TOP_NETSYS_TOPS_400M_SEL 99
+#define CLK_TOP_NETSYS_PPEFB_250M_SEL 100
+#define CLK_TOP_NETSYS_WARP_SEL 101
+#define CLK_TOP_ETH_MII_SEL 102
+#define CLK_TOP_NPU_SEL 103
+#define CLK_TOP_AUD_I2S_M 104
+
+/* MCUSYS */
+
+#define CLK_MCU_BUS_DIV_SEL 0
+#define CLK_MCU_ARM_DIV_SEL 1
+
+/* INFRACFG_AO */
+
+#define CLK_INFRA_MUX_UART0_SEL 0
+#define CLK_INFRA_MUX_UART1_SEL 1
+#define CLK_INFRA_MUX_UART2_SEL 2
+#define CLK_INFRA_MUX_SPI0_SEL 3
+#define CLK_INFRA_MUX_SPI1_SEL 4
+#define CLK_INFRA_MUX_SPI2_SEL 5
+#define CLK_INFRA_PWM_SEL 6
+#define CLK_INFRA_PWM_CK1_SEL 7
+#define CLK_INFRA_PWM_CK2_SEL 8
+#define CLK_INFRA_PWM_CK3_SEL 9
+#define CLK_INFRA_PWM_CK4_SEL 10
+#define CLK_INFRA_PWM_CK5_SEL 11
+#define CLK_INFRA_PWM_CK6_SEL 12
+#define CLK_INFRA_PWM_CK7_SEL 13
+#define CLK_INFRA_PWM_CK8_SEL 14
+#define CLK_INFRA_PCIE_GFMUX_TL_O_P0_SEL 15
+#define CLK_INFRA_PCIE_GFMUX_TL_O_P1_SEL 16
+#define CLK_INFRA_PCIE_GFMUX_TL_O_P2_SEL 17
+#define CLK_INFRA_PCIE_GFMUX_TL_O_P3_SEL 18
+
+/* INFRACFG */
+
+#define CLK_INFRA_PCIE_PERI_26M_CK_P0 19
+#define CLK_INFRA_PCIE_PERI_26M_CK_P1 20
+#define CLK_INFRA_PCIE_PERI_26M_CK_P2 21
+#define CLK_INFRA_PCIE_PERI_26M_CK_P3 22
+#define CLK_INFRA_66M_GPT_BCK 23
+#define CLK_INFRA_66M_PWM_HCK 24
+#define CLK_INFRA_66M_PWM_BCK 25
+#define CLK_INFRA_66M_PWM_CK1 26
+#define CLK_INFRA_66M_PWM_CK2 27
+#define CLK_INFRA_66M_PWM_CK3 28
+#define CLK_INFRA_66M_PWM_CK4 29
+#define CLK_INFRA_66M_PWM_CK5 30
+#define CLK_INFRA_66M_PWM_CK6 31
+#define CLK_INFRA_66M_PWM_CK7 32
+#define CLK_INFRA_66M_PWM_CK8 33
+#define CLK_INFRA_133M_CQDMA_BCK 34
+#define CLK_INFRA_66M_AUD_SLV_BCK 35
+#define CLK_INFRA_AUD_26M 36
+#define CLK_INFRA_AUD_L 37
+#define CLK_INFRA_AUD_AUD 38
+#define CLK_INFRA_AUD_EG2 39
+#define CLK_INFRA_DRAMC_F26M 40
+#define CLK_INFRA_133M_DBG_ACKM 41
+#define CLK_INFRA_66M_AP_DMA_BCK 42
+#define CLK_INFRA_66M_SEJ_BCK 43
+#define CLK_INFRA_PRE_CK_SEJ_F13M 44
+#define CLK_INFRA_26M_THERM_SYSTEM 45
+#define CLK_INFRA_I2C_BCK 46
+#define CLK_INFRA_52M_UART0_CK 47
+#define CLK_INFRA_52M_UART1_CK 48
+#define CLK_INFRA_52M_UART2_CK 49
+#define CLK_INFRA_NFI 50
+#define CLK_INFRA_SPINFI 51
+#define CLK_INFRA_66M_NFI_HCK 52
+#define CLK_INFRA_104M_SPI0 53
+#define CLK_INFRA_104M_SPI1 54
+#define CLK_INFRA_104M_SPI2_BCK 55
+#define CLK_INFRA_66M_SPI0_HCK 56
+#define CLK_INFRA_66M_SPI1_HCK 57
+#define CLK_INFRA_66M_SPI2_HCK 58
+#define CLK_INFRA_66M_FLASHIF_AXI 59
+#define CLK_INFRA_RTC 60
+#define CLK_INFRA_26M_ADC_BCK 61
+#define CLK_INFRA_RC_ADC 62
+#define CLK_INFRA_MSDC400 63
+#define CLK_INFRA_MSDC2_HCK 64
+#define CLK_INFRA_133M_MSDC_0_HCK 65
+#define CLK_INFRA_66M_MSDC_0_HCK 66
+#define CLK_INFRA_133M_CPUM_BCK 67
+#define CLK_INFRA_BIST2FPC 68
+#define CLK_INFRA_I2C_X16W_MCK_CK_P1 69
+#define CLK_INFRA_I2C_X16W_PCK_CK_P1 70
+#define CLK_INFRA_133M_USB_HCK 71
+#define CLK_INFRA_133M_USB_HCK_CK_P1 72
+#define CLK_INFRA_66M_USB_HCK 73
+#define CLK_INFRA_66M_USB_HCK_CK_P1 74
+#define CLK_INFRA_USB_SYS 75
+#define CLK_INFRA_USB_SYS_CK_P1 76
+#define CLK_INFRA_USB_REF 77
+#define CLK_INFRA_USB_CK_P1 78
+#define CLK_INFRA_USB_FRMCNT 79
+#define CLK_INFRA_USB_FRMCNT_CK_P1 80
+#define CLK_INFRA_USB_PIPE 81
+#define CLK_INFRA_USB_PIPE_CK_P1 82
+#define CLK_INFRA_USB_UTMI 83
+#define CLK_INFRA_USB_UTMI_CK_P1 84
+#define CLK_INFRA_USB_XHCI 85
+#define CLK_INFRA_USB_XHCI_CK_P1 86
+#define CLK_INFRA_PCIE_GFMUX_TL_P0 87
+#define CLK_INFRA_PCIE_GFMUX_TL_P1 88
+#define CLK_INFRA_PCIE_GFMUX_TL_P2 89
+#define CLK_INFRA_PCIE_GFMUX_TL_P3 90
+#define CLK_INFRA_PCIE_PIPE_P0 91
+#define CLK_INFRA_PCIE_PIPE_P1 92
+#define CLK_INFRA_PCIE_PIPE_P2 93
+#define CLK_INFRA_PCIE_PIPE_P3 94
+#define CLK_INFRA_133M_PCIE_CK_P0 95
+#define CLK_INFRA_133M_PCIE_CK_P1 96
+#define CLK_INFRA_133M_PCIE_CK_P2 97
+#define CLK_INFRA_133M_PCIE_CK_P3 98
+
+/* ETHDMA */
+
+#define CLK_ETHDMA_XGP1_EN 0
+#define CLK_ETHDMA_XGP2_EN 1
+#define CLK_ETHDMA_XGP3_EN 2
+#define CLK_ETHDMA_FE_EN 3
+#define CLK_ETHDMA_GP2_EN 4
+#define CLK_ETHDMA_GP1_EN 5
+#define CLK_ETHDMA_GP3_EN 6
+#define CLK_ETHDMA_ESW_EN 7
+#define CLK_ETHDMA_CRYPT0_EN 8
+#define CLK_ETHDMA_NR_CLK 9
+
+/* SGMIISYS_0 */
+
+#define CLK_SGM0_TX_EN 0
+#define CLK_SGM0_RX_EN 1
+#define CLK_SGMII0_NR_CLK 2
+
+/* SGMIISYS_1 */
+
+#define CLK_SGM1_TX_EN 0
+#define CLK_SGM1_RX_EN 1
+#define CLK_SGMII1_NR_CLK 2
+
+/* ETHWARP */
+
+#define CLK_ETHWARP_WOCPU2_EN 0
+#define CLK_ETHWARP_WOCPU1_EN 1
+#define CLK_ETHWARP_WOCPU0_EN 2
+#define CLK_ETHWARP_NR_CLK 3
+
+/* XFIPLL */
+#define CLK_XFIPLL_PLL 0
+#define CLK_XFIPLL_PLL_EN 1
+
+#endif /* _DT_BINDINGS_CLK_MT7988_H */
diff --git a/dts/upstream/include/dt-bindings/clock/qcom,gcc-msm8939.h b/dts/upstream/include/dt-bindings/clock/qcom,gcc-msm8939.h
index 2d545ed..9a9bc55 100644
--- a/dts/upstream/include/dt-bindings/clock/qcom,gcc-msm8939.h
+++ b/dts/upstream/include/dt-bindings/clock/qcom,gcc-msm8939.h
@@ -193,6 +193,12 @@
#define GCC_VENUS0_CORE1_VCODEC0_CLK 184
#define GCC_OXILI_TIMER_CLK 185
#define SYSTEM_MM_NOC_BFDCD_CLK_SRC 186
+#define CSI2_CLK_SRC 187
+#define GCC_CAMSS_CSI2_AHB_CLK 188
+#define GCC_CAMSS_CSI2_CLK 189
+#define GCC_CAMSS_CSI2PHY_CLK 190
+#define GCC_CAMSS_CSI2PIX_CLK 191
+#define GCC_CAMSS_CSI2RDI_CLK 192
/* Indexes for GDSCs */
#define BIMC_GDSC 0
diff --git a/dts/upstream/include/dt-bindings/clock/qcom,qdu1000-ecpricc.h b/dts/upstream/include/dt-bindings/clock/qcom,qdu1000-ecpricc.h
new file mode 100644
index 0000000..731e404
--- /dev/null
+++ b/dts/upstream/include/dt-bindings/clock/qcom,qdu1000-ecpricc.h
@@ -0,0 +1,147 @@
+/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */
+/*
+ * Copyright (c) 2022-2023, Qualcomm Innovation Center, Inc. All rights reserved.
+ */
+
+#ifndef _DT_BINDINGS_CLK_QCOM_ECPRI_CC_QDU1000_H
+#define _DT_BINDINGS_CLK_QCOM_ECPRI_CC_QDU1000_H
+
+/* ECPRI_CC clocks */
+#define ECPRI_CC_PLL0 0
+#define ECPRI_CC_PLL1 1
+#define ECPRI_CC_ECPRI_CG_CLK 2
+#define ECPRI_CC_ECPRI_CLK_SRC 3
+#define ECPRI_CC_ECPRI_DMA_CLK 4
+#define ECPRI_CC_ECPRI_DMA_CLK_SRC 5
+#define ECPRI_CC_ECPRI_DMA_NOC_CLK 6
+#define ECPRI_CC_ECPRI_FAST_CLK 7
+#define ECPRI_CC_ECPRI_FAST_CLK_SRC 8
+#define ECPRI_CC_ECPRI_FAST_DIV2_CLK 9
+#define ECPRI_CC_ECPRI_FAST_DIV2_CLK_SRC 10
+#define ECPRI_CC_ECPRI_FAST_DIV2_NOC_CLK 11
+#define ECPRI_CC_ECPRI_FR_CLK 12
+#define ECPRI_CC_ECPRI_ORAN_CLK_SRC 13
+#define ECPRI_CC_ECPRI_ORAN_DIV2_CLK 14
+#define ECPRI_CC_ETH_100G_C2C0_HM_FF_CLK_SRC 15
+#define ECPRI_CC_ETH_100G_C2C0_UDP_FIFO_CLK 16
+#define ECPRI_CC_ETH_100G_C2C1_UDP_FIFO_CLK 17
+#define ECPRI_CC_ETH_100G_C2C_0_HM_FF_0_CLK 18
+#define ECPRI_CC_ETH_100G_C2C_0_HM_FF_1_CLK 19
+#define ECPRI_CC_ETH_100G_C2C_HM_FF_0_DIV_CLK_SRC 20
+#define ECPRI_CC_ETH_100G_C2C_HM_FF_1_DIV_CLK_SRC 21
+#define ECPRI_CC_ETH_100G_C2C_HM_MACSEC_CLK 22
+#define ECPRI_CC_ETH_100G_C2C_HM_MACSEC_CLK_SRC 23
+#define ECPRI_CC_ETH_100G_DBG_C2C_HM_FF_0_CLK 24
+#define ECPRI_CC_ETH_100G_DBG_C2C_HM_FF_0_DIV_CLK_SRC 25
+#define ECPRI_CC_ETH_100G_DBG_C2C_HM_FF_1_CLK 26
+#define ECPRI_CC_ETH_100G_DBG_C2C_HM_FF_1_DIV_CLK_SRC 27
+#define ECPRI_CC_ETH_100G_DBG_C2C_HM_FF_CLK_SRC 28
+#define ECPRI_CC_ETH_100G_DBG_C2C_UDP_FIFO_CLK 29
+#define ECPRI_CC_ETH_100G_FH0_HM_FF_CLK_SRC 30
+#define ECPRI_CC_ETH_100G_FH0_MACSEC_CLK_SRC 31
+#define ECPRI_CC_ETH_100G_FH1_HM_FF_CLK_SRC 32
+#define ECPRI_CC_ETH_100G_FH1_MACSEC_CLK_SRC 33
+#define ECPRI_CC_ETH_100G_FH2_HM_FF_CLK_SRC 34
+#define ECPRI_CC_ETH_100G_FH2_MACSEC_CLK_SRC 35
+#define ECPRI_CC_ETH_100G_FH_0_HM_FF_0_CLK 36
+#define ECPRI_CC_ETH_100G_FH_0_HM_FF_0_DIV_CLK_SRC 37
+#define ECPRI_CC_ETH_100G_FH_0_HM_FF_1_CLK 38
+#define ECPRI_CC_ETH_100G_FH_0_HM_FF_1_DIV_CLK_SRC 39
+#define ECPRI_CC_ETH_100G_FH_0_HM_FF_2_CLK 40
+#define ECPRI_CC_ETH_100G_FH_0_HM_FF_2_DIV_CLK_SRC 41
+#define ECPRI_CC_ETH_100G_FH_0_HM_FF_3_CLK 42
+#define ECPRI_CC_ETH_100G_FH_0_HM_FF_3_DIV_CLK_SRC 43
+#define ECPRI_CC_ETH_100G_FH_0_UDP_FIFO_CLK 44
+#define ECPRI_CC_ETH_100G_FH_1_HM_FF_0_CLK 45
+#define ECPRI_CC_ETH_100G_FH_1_HM_FF_0_DIV_CLK_SRC 46
+#define ECPRI_CC_ETH_100G_FH_1_HM_FF_1_CLK 47
+#define ECPRI_CC_ETH_100G_FH_1_HM_FF_1_DIV_CLK_SRC 48
+#define ECPRI_CC_ETH_100G_FH_1_HM_FF_2_CLK 49
+#define ECPRI_CC_ETH_100G_FH_1_HM_FF_2_DIV_CLK_SRC 50
+#define ECPRI_CC_ETH_100G_FH_1_HM_FF_3_CLK 51
+#define ECPRI_CC_ETH_100G_FH_1_HM_FF_3_DIV_CLK_SRC 52
+#define ECPRI_CC_ETH_100G_FH_1_UDP_FIFO_CLK 53
+#define ECPRI_CC_ETH_100G_FH_2_HM_FF_0_CLK 54
+#define ECPRI_CC_ETH_100G_FH_2_HM_FF_0_DIV_CLK_SRC 55
+#define ECPRI_CC_ETH_100G_FH_2_HM_FF_1_CLK 56
+#define ECPRI_CC_ETH_100G_FH_2_HM_FF_1_DIV_CLK_SRC 57
+#define ECPRI_CC_ETH_100G_FH_2_HM_FF_2_CLK 58
+#define ECPRI_CC_ETH_100G_FH_2_HM_FF_2_DIV_CLK_SRC 59
+#define ECPRI_CC_ETH_100G_FH_2_HM_FF_3_CLK 60
+#define ECPRI_CC_ETH_100G_FH_2_HM_FF_3_DIV_CLK_SRC 61
+#define ECPRI_CC_ETH_100G_FH_2_UDP_FIFO_CLK 62
+#define ECPRI_CC_ETH_100G_FH_MACSEC_0_CLK 63
+#define ECPRI_CC_ETH_100G_FH_MACSEC_1_CLK 64
+#define ECPRI_CC_ETH_100G_FH_MACSEC_2_CLK 65
+#define ECPRI_CC_ETH_100G_MAC_C2C_HM_REF_CLK 66
+#define ECPRI_CC_ETH_100G_MAC_C2C_HM_REF_CLK_SRC 67
+#define ECPRI_CC_ETH_100G_MAC_DBG_C2C_HM_REF_CLK 68
+#define ECPRI_CC_ETH_100G_MAC_DBG_C2C_HM_REF_CLK_SRC 69
+#define ECPRI_CC_ETH_100G_MAC_FH0_HM_REF_CLK 70
+#define ECPRI_CC_ETH_100G_MAC_FH0_HM_REF_CLK_SRC 71
+#define ECPRI_CC_ETH_100G_MAC_FH1_HM_REF_CLK 72
+#define ECPRI_CC_ETH_100G_MAC_FH1_HM_REF_CLK_SRC 73
+#define ECPRI_CC_ETH_100G_MAC_FH2_HM_REF_CLK 74
+#define ECPRI_CC_ETH_100G_MAC_FH2_HM_REF_CLK_SRC 75
+#define ECPRI_CC_ETH_DBG_NFAPI_AXI_CLK 76
+#define ECPRI_CC_ETH_DBG_NOC_AXI_CLK 77
+#define ECPRI_CC_ETH_PHY_0_OCK_SRAM_CLK 78
+#define ECPRI_CC_ETH_PHY_1_OCK_SRAM_CLK 79
+#define ECPRI_CC_ETH_PHY_2_OCK_SRAM_CLK 80
+#define ECPRI_CC_ETH_PHY_3_OCK_SRAM_CLK 81
+#define ECPRI_CC_ETH_PHY_4_OCK_SRAM_CLK 82
+#define ECPRI_CC_MSS_EMAC_CLK 83
+#define ECPRI_CC_MSS_EMAC_CLK_SRC 84
+#define ECPRI_CC_MSS_ORAN_CLK 85
+#define ECPRI_CC_PHY0_LANE0_RX_CLK 86
+#define ECPRI_CC_PHY0_LANE0_TX_CLK 87
+#define ECPRI_CC_PHY0_LANE1_RX_CLK 88
+#define ECPRI_CC_PHY0_LANE1_TX_CLK 89
+#define ECPRI_CC_PHY0_LANE2_RX_CLK 90
+#define ECPRI_CC_PHY0_LANE2_TX_CLK 91
+#define ECPRI_CC_PHY0_LANE3_RX_CLK 92
+#define ECPRI_CC_PHY0_LANE3_TX_CLK 93
+#define ECPRI_CC_PHY1_LANE0_RX_CLK 94
+#define ECPRI_CC_PHY1_LANE0_TX_CLK 95
+#define ECPRI_CC_PHY1_LANE1_RX_CLK 96
+#define ECPRI_CC_PHY1_LANE1_TX_CLK 97
+#define ECPRI_CC_PHY1_LANE2_RX_CLK 98
+#define ECPRI_CC_PHY1_LANE2_TX_CLK 99
+#define ECPRI_CC_PHY1_LANE3_RX_CLK 100
+#define ECPRI_CC_PHY1_LANE3_TX_CLK 101
+#define ECPRI_CC_PHY2_LANE0_RX_CLK 102
+#define ECPRI_CC_PHY2_LANE0_TX_CLK 103
+#define ECPRI_CC_PHY2_LANE1_RX_CLK 104
+#define ECPRI_CC_PHY2_LANE1_TX_CLK 105
+#define ECPRI_CC_PHY2_LANE2_RX_CLK 106
+#define ECPRI_CC_PHY2_LANE2_TX_CLK 107
+#define ECPRI_CC_PHY2_LANE3_RX_CLK 108
+#define ECPRI_CC_PHY2_LANE3_TX_CLK 109
+#define ECPRI_CC_PHY3_LANE0_RX_CLK 110
+#define ECPRI_CC_PHY3_LANE0_TX_CLK 111
+#define ECPRI_CC_PHY3_LANE1_RX_CLK 112
+#define ECPRI_CC_PHY3_LANE1_TX_CLK 113
+#define ECPRI_CC_PHY3_LANE2_RX_CLK 114
+#define ECPRI_CC_PHY3_LANE2_TX_CLK 115
+#define ECPRI_CC_PHY3_LANE3_RX_CLK 116
+#define ECPRI_CC_PHY3_LANE3_TX_CLK 117
+#define ECPRI_CC_PHY4_LANE0_RX_CLK 118
+#define ECPRI_CC_PHY4_LANE0_TX_CLK 119
+#define ECPRI_CC_PHY4_LANE1_RX_CLK 120
+#define ECPRI_CC_PHY4_LANE1_TX_CLK 121
+#define ECPRI_CC_PHY4_LANE2_RX_CLK 122
+#define ECPRI_CC_PHY4_LANE2_TX_CLK 123
+#define ECPRI_CC_PHY4_LANE3_RX_CLK 124
+#define ECPRI_CC_PHY4_LANE3_TX_CLK 125
+
+/* ECPRI_CC resets */
+#define ECPRI_CC_CLK_CTL_TOP_ECPRI_CC_ECPRI_SS_BCR 0
+#define ECPRI_CC_CLK_CTL_TOP_ECPRI_CC_ETH_C2C_BCR 1
+#define ECPRI_CC_CLK_CTL_TOP_ECPRI_CC_ETH_FH0_BCR 2
+#define ECPRI_CC_CLK_CTL_TOP_ECPRI_CC_ETH_FH1_BCR 3
+#define ECPRI_CC_CLK_CTL_TOP_ECPRI_CC_ETH_FH2_BCR 4
+#define ECPRI_CC_CLK_CTL_TOP_ECPRI_CC_ETH_WRAPPER_TOP_BCR 5
+#define ECPRI_CC_CLK_CTL_TOP_ECPRI_CC_MODEM_BCR 6
+#define ECPRI_CC_CLK_CTL_TOP_ECPRI_CC_NOC_BCR 7
+
+#endif
diff --git a/dts/upstream/include/dt-bindings/clock/qcom,sc8280xp-camcc.h b/dts/upstream/include/dt-bindings/clock/qcom,sc8280xp-camcc.h
new file mode 100644
index 0000000..ea5ec73
--- /dev/null
+++ b/dts/upstream/include/dt-bindings/clock/qcom,sc8280xp-camcc.h
@@ -0,0 +1,179 @@
+/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */
+/*
+ * Copyright (c) 2021, The Linux Foundation. All rights reserved.
+ * Copyright (c) 2023, Linaro Ltd.
+ */
+
+#ifndef __DT_BINDINGS_CLK_QCOM_CAMCC_SC8280XP_H__
+#define __DT_BINDINGS_CLK_QCOM_CAMCC_SC8280XP_H__
+
+/* CAMCC clocks */
+#define CAMCC_PLL0 0
+#define CAMCC_PLL0_OUT_EVEN 1
+#define CAMCC_PLL0_OUT_ODD 2
+#define CAMCC_PLL1 3
+#define CAMCC_PLL1_OUT_EVEN 4
+#define CAMCC_PLL2 5
+#define CAMCC_PLL3 6
+#define CAMCC_PLL3_OUT_EVEN 7
+#define CAMCC_PLL4 8
+#define CAMCC_PLL4_OUT_EVEN 9
+#define CAMCC_PLL5 10
+#define CAMCC_PLL5_OUT_EVEN 11
+#define CAMCC_PLL6 12
+#define CAMCC_PLL6_OUT_EVEN 13
+#define CAMCC_PLL7 14
+#define CAMCC_PLL7_OUT_EVEN 15
+#define CAMCC_PLL7_OUT_ODD 16
+#define CAMCC_BPS_AHB_CLK 17
+#define CAMCC_BPS_AREG_CLK 18
+#define CAMCC_BPS_AXI_CLK 19
+#define CAMCC_BPS_CLK 20
+#define CAMCC_BPS_CLK_SRC 21
+#define CAMCC_CAMNOC_AXI_CLK 22
+#define CAMCC_CAMNOC_AXI_CLK_SRC 23
+#define CAMCC_CAMNOC_DCD_XO_CLK 24
+#define CAMCC_CCI_0_CLK 25
+#define CAMCC_CCI_0_CLK_SRC 26
+#define CAMCC_CCI_1_CLK 27
+#define CAMCC_CCI_1_CLK_SRC 28
+#define CAMCC_CCI_2_CLK 29
+#define CAMCC_CCI_2_CLK_SRC 30
+#define CAMCC_CCI_3_CLK 31
+#define CAMCC_CCI_3_CLK_SRC 32
+#define CAMCC_CORE_AHB_CLK 33
+#define CAMCC_CPAS_AHB_CLK 34
+#define CAMCC_CPHY_RX_CLK_SRC 35
+#define CAMCC_CSI0PHYTIMER_CLK 36
+#define CAMCC_CSI0PHYTIMER_CLK_SRC 37
+#define CAMCC_CSI1PHYTIMER_CLK 38
+#define CAMCC_CSI1PHYTIMER_CLK_SRC 39
+#define CAMCC_CSI2PHYTIMER_CLK 40
+#define CAMCC_CSI2PHYTIMER_CLK_SRC 41
+#define CAMCC_CSI3PHYTIMER_CLK 42
+#define CAMCC_CSI3PHYTIMER_CLK_SRC 43
+#define CAMCC_CSIPHY0_CLK 44
+#define CAMCC_CSIPHY1_CLK 45
+#define CAMCC_CSIPHY2_CLK 46
+#define CAMCC_CSIPHY3_CLK 47
+#define CAMCC_FAST_AHB_CLK_SRC 48
+#define CAMCC_GDSC_CLK 49
+#define CAMCC_ICP_AHB_CLK 50
+#define CAMCC_ICP_CLK 51
+#define CAMCC_ICP_CLK_SRC 52
+#define CAMCC_IFE_0_AXI_CLK 53
+#define CAMCC_IFE_0_CLK 54
+#define CAMCC_IFE_0_CLK_SRC 55
+#define CAMCC_IFE_0_CPHY_RX_CLK 56
+#define CAMCC_IFE_0_CSID_CLK 57
+#define CAMCC_IFE_0_CSID_CLK_SRC 58
+#define CAMCC_IFE_0_DSP_CLK 59
+#define CAMCC_IFE_1_AXI_CLK 60
+#define CAMCC_IFE_1_CLK 61
+#define CAMCC_IFE_1_CLK_SRC 62
+#define CAMCC_IFE_1_CPHY_RX_CLK 63
+#define CAMCC_IFE_1_CSID_CLK 64
+#define CAMCC_IFE_1_CSID_CLK_SRC 65
+#define CAMCC_IFE_1_DSP_CLK 66
+#define CAMCC_IFE_2_AXI_CLK 67
+#define CAMCC_IFE_2_CLK 68
+#define CAMCC_IFE_2_CLK_SRC 69
+#define CAMCC_IFE_2_CPHY_RX_CLK 70
+#define CAMCC_IFE_2_CSID_CLK 71
+#define CAMCC_IFE_2_CSID_CLK_SRC 72
+#define CAMCC_IFE_2_DSP_CLK 73
+#define CAMCC_IFE_3_AXI_CLK 74
+#define CAMCC_IFE_3_CLK 75
+#define CAMCC_IFE_3_CLK_SRC 76
+#define CAMCC_IFE_3_CPHY_RX_CLK 77
+#define CAMCC_IFE_3_CSID_CLK 78
+#define CAMCC_IFE_3_CSID_CLK_SRC 79
+#define CAMCC_IFE_3_DSP_CLK 80
+#define CAMCC_IFE_LITE_0_CLK 81
+#define CAMCC_IFE_LITE_0_CLK_SRC 82
+#define CAMCC_IFE_LITE_0_CPHY_RX_CLK 83
+#define CAMCC_IFE_LITE_0_CSID_CLK 84
+#define CAMCC_IFE_LITE_0_CSID_CLK_SRC 85
+#define CAMCC_IFE_LITE_1_CLK 86
+#define CAMCC_IFE_LITE_1_CLK_SRC 87
+#define CAMCC_IFE_LITE_1_CPHY_RX_CLK 88
+#define CAMCC_IFE_LITE_1_CSID_CLK 89
+#define CAMCC_IFE_LITE_1_CSID_CLK_SRC 90
+#define CAMCC_IFE_LITE_2_CLK 91
+#define CAMCC_IFE_LITE_2_CLK_SRC 92
+#define CAMCC_IFE_LITE_2_CPHY_RX_CLK 93
+#define CAMCC_IFE_LITE_2_CSID_CLK 94
+#define CAMCC_IFE_LITE_2_CSID_CLK_SRC 95
+#define CAMCC_IFE_LITE_3_CLK 96
+#define CAMCC_IFE_LITE_3_CLK_SRC 97
+#define CAMCC_IFE_LITE_3_CPHY_RX_CLK 98
+#define CAMCC_IFE_LITE_3_CSID_CLK 99
+#define CAMCC_IFE_LITE_3_CSID_CLK_SRC 100
+#define CAMCC_IPE_0_AHB_CLK 101
+#define CAMCC_IPE_0_AREG_CLK 102
+#define CAMCC_IPE_0_AXI_CLK 103
+#define CAMCC_IPE_0_CLK 104
+#define CAMCC_IPE_0_CLK_SRC 105
+#define CAMCC_IPE_1_AHB_CLK 106
+#define CAMCC_IPE_1_AREG_CLK 107
+#define CAMCC_IPE_1_AXI_CLK 108
+#define CAMCC_IPE_1_CLK 109
+#define CAMCC_JPEG_CLK 110
+#define CAMCC_JPEG_CLK_SRC 111
+#define CAMCC_LRME_CLK 112
+#define CAMCC_LRME_CLK_SRC 113
+#define CAMCC_MCLK0_CLK 114
+#define CAMCC_MCLK0_CLK_SRC 115
+#define CAMCC_MCLK1_CLK 116
+#define CAMCC_MCLK1_CLK_SRC 117
+#define CAMCC_MCLK2_CLK 118
+#define CAMCC_MCLK2_CLK_SRC 119
+#define CAMCC_MCLK3_CLK 120
+#define CAMCC_MCLK3_CLK_SRC 121
+#define CAMCC_MCLK4_CLK 122
+#define CAMCC_MCLK4_CLK_SRC 123
+#define CAMCC_MCLK5_CLK 124
+#define CAMCC_MCLK5_CLK_SRC 125
+#define CAMCC_MCLK6_CLK 126
+#define CAMCC_MCLK6_CLK_SRC 127
+#define CAMCC_MCLK7_CLK 128
+#define CAMCC_MCLK7_CLK_SRC 129
+#define CAMCC_SLEEP_CLK 130
+#define CAMCC_SLEEP_CLK_SRC 131
+#define CAMCC_SLOW_AHB_CLK_SRC 132
+#define CAMCC_XO_CLK_SRC 133
+
+/* CAMCC resets */
+#define CAMCC_BPS_BCR 0
+#define CAMCC_CAMNOC_BCR 1
+#define CAMCC_CCI_BCR 2
+#define CAMCC_CPAS_BCR 3
+#define CAMCC_CSI0PHY_BCR 4
+#define CAMCC_CSI1PHY_BCR 5
+#define CAMCC_CSI2PHY_BCR 6
+#define CAMCC_CSI3PHY_BCR 7
+#define CAMCC_ICP_BCR 8
+#define CAMCC_IFE_0_BCR 9
+#define CAMCC_IFE_1_BCR 10
+#define CAMCC_IFE_2_BCR 11
+#define CAMCC_IFE_3_BCR 12
+#define CAMCC_IFE_LITE_0_BCR 13
+#define CAMCC_IFE_LITE_1_BCR 14
+#define CAMCC_IFE_LITE_2_BCR 15
+#define CAMCC_IFE_LITE_3_BCR 16
+#define CAMCC_IPE_0_BCR 17
+#define CAMCC_IPE_1_BCR 18
+#define CAMCC_JPEG_BCR 19
+#define CAMCC_LRME_BCR 20
+
+/* CAMCC GDSCRs */
+#define BPS_GDSC 0
+#define IFE_0_GDSC 1
+#define IFE_1_GDSC 2
+#define IFE_2_GDSC 3
+#define IFE_3_GDSC 4
+#define IPE_0_GDSC 5
+#define IPE_1_GDSC 6
+#define TITAN_TOP_GDSC 7
+
+#endif /* __DT_BINDINGS_CLK_QCOM_CAMCC_SC8280XP_H__ */
diff --git a/dts/upstream/include/dt-bindings/clock/qcom,sm8650-dispcc.h b/dts/upstream/include/dt-bindings/clock/qcom,sm8650-dispcc.h
new file mode 100644
index 0000000..b0a668b
--- /dev/null
+++ b/dts/upstream/include/dt-bindings/clock/qcom,sm8650-dispcc.h
@@ -0,0 +1,102 @@
+/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */
+/*
+ * Copyright (c) 2022, Qualcomm Innovation Center, Inc. All rights reserved
+ * Copyright (c) 2023, Linaro Ltd.
+ */
+
+#ifndef _DT_BINDINGS_CLK_QCOM_SM8650_DISP_CC_H
+#define _DT_BINDINGS_CLK_QCOM_SM8650_DISP_CC_H
+
+/* DISP_CC clocks */
+#define DISP_CC_MDSS_ACCU_CLK 0
+#define DISP_CC_MDSS_AHB1_CLK 1
+#define DISP_CC_MDSS_AHB_CLK 2
+#define DISP_CC_MDSS_AHB_CLK_SRC 3
+#define DISP_CC_MDSS_BYTE0_CLK 4
+#define DISP_CC_MDSS_BYTE0_CLK_SRC 5
+#define DISP_CC_MDSS_BYTE0_DIV_CLK_SRC 6
+#define DISP_CC_MDSS_BYTE0_INTF_CLK 7
+#define DISP_CC_MDSS_BYTE1_CLK 8
+#define DISP_CC_MDSS_BYTE1_CLK_SRC 9
+#define DISP_CC_MDSS_BYTE1_DIV_CLK_SRC 10
+#define DISP_CC_MDSS_BYTE1_INTF_CLK 11
+#define DISP_CC_MDSS_DPTX0_AUX_CLK 12
+#define DISP_CC_MDSS_DPTX0_AUX_CLK_SRC 13
+#define DISP_CC_MDSS_DPTX0_CRYPTO_CLK 14
+#define DISP_CC_MDSS_DPTX0_LINK_CLK 15
+#define DISP_CC_MDSS_DPTX0_LINK_CLK_SRC 16
+#define DISP_CC_MDSS_DPTX0_LINK_DIV_CLK_SRC 17
+#define DISP_CC_MDSS_DPTX0_LINK_INTF_CLK 18
+#define DISP_CC_MDSS_DPTX0_PIXEL0_CLK 19
+#define DISP_CC_MDSS_DPTX0_PIXEL0_CLK_SRC 20
+#define DISP_CC_MDSS_DPTX0_PIXEL1_CLK 21
+#define DISP_CC_MDSS_DPTX0_PIXEL1_CLK_SRC 22
+#define DISP_CC_MDSS_DPTX0_USB_ROUTER_LINK_INTF_CLK 23
+#define DISP_CC_MDSS_DPTX1_AUX_CLK 24
+#define DISP_CC_MDSS_DPTX1_AUX_CLK_SRC 25
+#define DISP_CC_MDSS_DPTX1_CRYPTO_CLK 26
+#define DISP_CC_MDSS_DPTX1_LINK_CLK 27
+#define DISP_CC_MDSS_DPTX1_LINK_CLK_SRC 28
+#define DISP_CC_MDSS_DPTX1_LINK_DIV_CLK_SRC 29
+#define DISP_CC_MDSS_DPTX1_LINK_INTF_CLK 30
+#define DISP_CC_MDSS_DPTX1_PIXEL0_CLK 31
+#define DISP_CC_MDSS_DPTX1_PIXEL0_CLK_SRC 32
+#define DISP_CC_MDSS_DPTX1_PIXEL1_CLK 33
+#define DISP_CC_MDSS_DPTX1_PIXEL1_CLK_SRC 34
+#define DISP_CC_MDSS_DPTX1_USB_ROUTER_LINK_INTF_CLK 35
+#define DISP_CC_MDSS_DPTX2_AUX_CLK 36
+#define DISP_CC_MDSS_DPTX2_AUX_CLK_SRC 37
+#define DISP_CC_MDSS_DPTX2_CRYPTO_CLK 38
+#define DISP_CC_MDSS_DPTX2_LINK_CLK 39
+#define DISP_CC_MDSS_DPTX2_LINK_CLK_SRC 40
+#define DISP_CC_MDSS_DPTX2_LINK_DIV_CLK_SRC 41
+#define DISP_CC_MDSS_DPTX2_LINK_INTF_CLK 42
+#define DISP_CC_MDSS_DPTX2_PIXEL0_CLK 43
+#define DISP_CC_MDSS_DPTX2_PIXEL0_CLK_SRC 44
+#define DISP_CC_MDSS_DPTX2_PIXEL1_CLK 45
+#define DISP_CC_MDSS_DPTX2_PIXEL1_CLK_SRC 46
+#define DISP_CC_MDSS_DPTX3_AUX_CLK 47
+#define DISP_CC_MDSS_DPTX3_AUX_CLK_SRC 48
+#define DISP_CC_MDSS_DPTX3_CRYPTO_CLK 49
+#define DISP_CC_MDSS_DPTX3_LINK_CLK 50
+#define DISP_CC_MDSS_DPTX3_LINK_CLK_SRC 51
+#define DISP_CC_MDSS_DPTX3_LINK_DIV_CLK_SRC 52
+#define DISP_CC_MDSS_DPTX3_LINK_INTF_CLK 53
+#define DISP_CC_MDSS_DPTX3_PIXEL0_CLK 54
+#define DISP_CC_MDSS_DPTX3_PIXEL0_CLK_SRC 55
+#define DISP_CC_MDSS_ESC0_CLK 56
+#define DISP_CC_MDSS_ESC0_CLK_SRC 57
+#define DISP_CC_MDSS_ESC1_CLK 58
+#define DISP_CC_MDSS_ESC1_CLK_SRC 59
+#define DISP_CC_MDSS_MDP1_CLK 60
+#define DISP_CC_MDSS_MDP_CLK 61
+#define DISP_CC_MDSS_MDP_CLK_SRC 62
+#define DISP_CC_MDSS_MDP_LUT1_CLK 63
+#define DISP_CC_MDSS_MDP_LUT_CLK 64
+#define DISP_CC_MDSS_NON_GDSC_AHB_CLK 65
+#define DISP_CC_MDSS_PCLK0_CLK 66
+#define DISP_CC_MDSS_PCLK0_CLK_SRC 67
+#define DISP_CC_MDSS_PCLK1_CLK 68
+#define DISP_CC_MDSS_PCLK1_CLK_SRC 69
+#define DISP_CC_MDSS_RSCC_AHB_CLK 70
+#define DISP_CC_MDSS_RSCC_VSYNC_CLK 71
+#define DISP_CC_MDSS_VSYNC1_CLK 72
+#define DISP_CC_MDSS_VSYNC_CLK 73
+#define DISP_CC_MDSS_VSYNC_CLK_SRC 74
+#define DISP_CC_PLL0 75
+#define DISP_CC_PLL1 76
+#define DISP_CC_SLEEP_CLK 77
+#define DISP_CC_SLEEP_CLK_SRC 78
+#define DISP_CC_XO_CLK 79
+#define DISP_CC_XO_CLK_SRC 80
+
+/* DISP_CC resets */
+#define DISP_CC_MDSS_CORE_BCR 0
+#define DISP_CC_MDSS_CORE_INT2_BCR 1
+#define DISP_CC_MDSS_RSCC_BCR 2
+
+/* DISP_CC GDSCR */
+#define MDSS_GDSC 0
+#define MDSS_INT2_GDSC 1
+
+#endif
diff --git a/dts/upstream/include/dt-bindings/clock/qcom,sm8650-gcc.h b/dts/upstream/include/dt-bindings/clock/qcom,sm8650-gcc.h
new file mode 100644
index 0000000..0c543ba
--- /dev/null
+++ b/dts/upstream/include/dt-bindings/clock/qcom,sm8650-gcc.h
@@ -0,0 +1,254 @@
+/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */
+/*
+ * Copyright (c) 2022, Qualcomm Innovation Center, Inc. All rights reserved.
+ * Copyright (c) 2023, Linaro Limited
+ */
+
+#ifndef _DT_BINDINGS_CLK_QCOM_GCC_SM8650_H
+#define _DT_BINDINGS_CLK_QCOM_GCC_SM8650_H
+
+/* GCC clocks */
+#define GCC_AGGRE_NOC_PCIE_AXI_CLK 0
+#define GCC_AGGRE_UFS_PHY_AXI_CLK 1
+#define GCC_AGGRE_UFS_PHY_AXI_HW_CTL_CLK 2
+#define GCC_AGGRE_USB3_PRIM_AXI_CLK 3
+#define GCC_BOOT_ROM_AHB_CLK 4
+#define GCC_CAMERA_AHB_CLK 5
+#define GCC_CAMERA_HF_AXI_CLK 6
+#define GCC_CAMERA_SF_AXI_CLK 7
+#define GCC_CAMERA_XO_CLK 8
+#define GCC_CFG_NOC_PCIE_ANOC_AHB_CLK 9
+#define GCC_CFG_NOC_USB3_PRIM_AXI_CLK 10
+#define GCC_CNOC_PCIE_SF_AXI_CLK 11
+#define GCC_DDRSS_GPU_AXI_CLK 12
+#define GCC_DDRSS_PCIE_SF_QTB_CLK 13
+#define GCC_DISP_AHB_CLK 14
+#define GCC_DISP_HF_AXI_CLK 15
+#define GCC_DISP_XO_CLK 16
+#define GCC_GP1_CLK 17
+#define GCC_GP1_CLK_SRC 18
+#define GCC_GP2_CLK 19
+#define GCC_GP2_CLK_SRC 20
+#define GCC_GP3_CLK 21
+#define GCC_GP3_CLK_SRC 22
+#define GCC_GPLL0 23
+#define GCC_GPLL0_OUT_EVEN 24
+#define GCC_GPLL1 25
+#define GCC_GPLL3 26
+#define GCC_GPLL4 27
+#define GCC_GPLL6 28
+#define GCC_GPLL7 29
+#define GCC_GPLL9 30
+#define GCC_GPU_CFG_AHB_CLK 31
+#define GCC_GPU_GPLL0_CLK_SRC 32
+#define GCC_GPU_GPLL0_DIV_CLK_SRC 33
+#define GCC_GPU_MEMNOC_GFX_CLK 34
+#define GCC_GPU_SNOC_DVM_GFX_CLK 35
+#define GCC_PCIE_0_AUX_CLK 36
+#define GCC_PCIE_0_AUX_CLK_SRC 37
+#define GCC_PCIE_0_CFG_AHB_CLK 38
+#define GCC_PCIE_0_MSTR_AXI_CLK 39
+#define GCC_PCIE_0_PHY_RCHNG_CLK 40
+#define GCC_PCIE_0_PHY_RCHNG_CLK_SRC 41
+#define GCC_PCIE_0_PIPE_CLK 42
+#define GCC_PCIE_0_PIPE_CLK_SRC 43
+#define GCC_PCIE_0_SLV_AXI_CLK 44
+#define GCC_PCIE_0_SLV_Q2A_AXI_CLK 45
+#define GCC_PCIE_1_AUX_CLK 46
+#define GCC_PCIE_1_AUX_CLK_SRC 47
+#define GCC_PCIE_1_CFG_AHB_CLK 48
+#define GCC_PCIE_1_MSTR_AXI_CLK 49
+#define GCC_PCIE_1_PHY_AUX_CLK 50
+#define GCC_PCIE_1_PHY_AUX_CLK_SRC 51
+#define GCC_PCIE_1_PHY_RCHNG_CLK 52
+#define GCC_PCIE_1_PHY_RCHNG_CLK_SRC 53
+#define GCC_PCIE_1_PIPE_CLK 54
+#define GCC_PCIE_1_PIPE_CLK_SRC 55
+#define GCC_PCIE_1_SLV_AXI_CLK 56
+#define GCC_PCIE_1_SLV_Q2A_AXI_CLK 57
+#define GCC_PDM2_CLK 58
+#define GCC_PDM2_CLK_SRC 59
+#define GCC_PDM_AHB_CLK 60
+#define GCC_PDM_XO4_CLK 61
+#define GCC_QMIP_CAMERA_NRT_AHB_CLK 62
+#define GCC_QMIP_CAMERA_RT_AHB_CLK 63
+#define GCC_QMIP_DISP_AHB_CLK 64
+#define GCC_QMIP_GPU_AHB_CLK 65
+#define GCC_QMIP_PCIE_AHB_CLK 66
+#define GCC_QMIP_VIDEO_CV_CPU_AHB_CLK 67
+#define GCC_QMIP_VIDEO_CVP_AHB_CLK 68
+#define GCC_QMIP_VIDEO_V_CPU_AHB_CLK 69
+#define GCC_QMIP_VIDEO_VCODEC_AHB_CLK 70
+#define GCC_QUPV3_I2C_CORE_CLK 71
+#define GCC_QUPV3_I2C_S0_CLK 72
+#define GCC_QUPV3_I2C_S0_CLK_SRC 73
+#define GCC_QUPV3_I2C_S1_CLK 74
+#define GCC_QUPV3_I2C_S1_CLK_SRC 75
+#define GCC_QUPV3_I2C_S2_CLK 76
+#define GCC_QUPV3_I2C_S2_CLK_SRC 77
+#define GCC_QUPV3_I2C_S3_CLK 78
+#define GCC_QUPV3_I2C_S3_CLK_SRC 79
+#define GCC_QUPV3_I2C_S4_CLK 80
+#define GCC_QUPV3_I2C_S4_CLK_SRC 81
+#define GCC_QUPV3_I2C_S5_CLK 82
+#define GCC_QUPV3_I2C_S5_CLK_SRC 83
+#define GCC_QUPV3_I2C_S6_CLK 84
+#define GCC_QUPV3_I2C_S6_CLK_SRC 85
+#define GCC_QUPV3_I2C_S7_CLK 86
+#define GCC_QUPV3_I2C_S7_CLK_SRC 87
+#define GCC_QUPV3_I2C_S8_CLK 88
+#define GCC_QUPV3_I2C_S8_CLK_SRC 89
+#define GCC_QUPV3_I2C_S9_CLK 90
+#define GCC_QUPV3_I2C_S9_CLK_SRC 91
+#define GCC_QUPV3_I2C_S_AHB_CLK 92
+#define GCC_QUPV3_WRAP1_CORE_2X_CLK 93
+#define GCC_QUPV3_WRAP1_CORE_CLK 94
+#define GCC_QUPV3_WRAP1_QSPI_REF_CLK 95
+#define GCC_QUPV3_WRAP1_QSPI_REF_CLK_SRC 96
+#define GCC_QUPV3_WRAP1_S0_CLK 97
+#define GCC_QUPV3_WRAP1_S0_CLK_SRC 98
+#define GCC_QUPV3_WRAP1_S1_CLK 99
+#define GCC_QUPV3_WRAP1_S1_CLK_SRC 100
+#define GCC_QUPV3_WRAP1_S2_CLK 101
+#define GCC_QUPV3_WRAP1_S2_CLK_SRC 102
+#define GCC_QUPV3_WRAP1_S3_CLK 103
+#define GCC_QUPV3_WRAP1_S3_CLK_SRC 104
+#define GCC_QUPV3_WRAP1_S4_CLK 105
+#define GCC_QUPV3_WRAP1_S4_CLK_SRC 106
+#define GCC_QUPV3_WRAP1_S5_CLK 107
+#define GCC_QUPV3_WRAP1_S5_CLK_SRC 108
+#define GCC_QUPV3_WRAP1_S6_CLK 109
+#define GCC_QUPV3_WRAP1_S6_CLK_SRC 110
+#define GCC_QUPV3_WRAP1_S7_CLK 111
+#define GCC_QUPV3_WRAP1_S7_CLK_SRC 112
+#define GCC_QUPV3_WRAP2_CORE_2X_CLK 113
+#define GCC_QUPV3_WRAP2_CORE_CLK 114
+#define GCC_QUPV3_WRAP2_IBI_CTRL_0_CLK_SRC 115
+#define GCC_QUPV3_WRAP2_IBI_CTRL_2_CLK 116
+#define GCC_QUPV3_WRAP2_IBI_CTRL_3_CLK 117
+#define GCC_QUPV3_WRAP2_S0_CLK 118
+#define GCC_QUPV3_WRAP2_S0_CLK_SRC 119
+#define GCC_QUPV3_WRAP2_S1_CLK 120
+#define GCC_QUPV3_WRAP2_S1_CLK_SRC 121
+#define GCC_QUPV3_WRAP2_S2_CLK 122
+#define GCC_QUPV3_WRAP2_S2_CLK_SRC 123
+#define GCC_QUPV3_WRAP2_S3_CLK 124
+#define GCC_QUPV3_WRAP2_S3_CLK_SRC 125
+#define GCC_QUPV3_WRAP2_S4_CLK 126
+#define GCC_QUPV3_WRAP2_S4_CLK_SRC 127
+#define GCC_QUPV3_WRAP2_S5_CLK 128
+#define GCC_QUPV3_WRAP2_S5_CLK_SRC 129
+#define GCC_QUPV3_WRAP2_S6_CLK 130
+#define GCC_QUPV3_WRAP2_S6_CLK_SRC 131
+#define GCC_QUPV3_WRAP2_S7_CLK 132
+#define GCC_QUPV3_WRAP2_S7_CLK_SRC 133
+#define GCC_QUPV3_WRAP3_CORE_2X_CLK 134
+#define GCC_QUPV3_WRAP3_CORE_CLK 135
+#define GCC_QUPV3_WRAP3_QSPI_REF_CLK 136
+#define GCC_QUPV3_WRAP3_QSPI_REF_CLK_SRC 137
+#define GCC_QUPV3_WRAP3_S0_CLK 138
+#define GCC_QUPV3_WRAP3_S0_CLK_SRC 139
+#define GCC_QUPV3_WRAP_1_M_AHB_CLK 140
+#define GCC_QUPV3_WRAP_1_S_AHB_CLK 141
+#define GCC_QUPV3_WRAP_2_IBI_2_AHB_CLK 142
+#define GCC_QUPV3_WRAP_2_IBI_3_AHB_CLK 143
+#define GCC_QUPV3_WRAP_2_M_AHB_CLK 144
+#define GCC_QUPV3_WRAP_2_S_AHB_CLK 145
+#define GCC_QUPV3_WRAP_3_M_AHB_CLK 146
+#define GCC_QUPV3_WRAP_3_S_AHB_CLK 147
+#define GCC_SDCC2_AHB_CLK 148
+#define GCC_SDCC2_APPS_CLK 149
+#define GCC_SDCC2_APPS_CLK_SRC 150
+#define GCC_SDCC4_AHB_CLK 151
+#define GCC_SDCC4_APPS_CLK 152
+#define GCC_SDCC4_APPS_CLK_SRC 153
+#define GCC_UFS_PHY_AHB_CLK 154
+#define GCC_UFS_PHY_AXI_CLK 155
+#define GCC_UFS_PHY_AXI_CLK_SRC 156
+#define GCC_UFS_PHY_AXI_HW_CTL_CLK 157
+#define GCC_UFS_PHY_ICE_CORE_CLK 158
+#define GCC_UFS_PHY_ICE_CORE_CLK_SRC 159
+#define GCC_UFS_PHY_ICE_CORE_HW_CTL_CLK 160
+#define GCC_UFS_PHY_PHY_AUX_CLK 161
+#define GCC_UFS_PHY_PHY_AUX_CLK_SRC 162
+#define GCC_UFS_PHY_PHY_AUX_HW_CTL_CLK 163
+#define GCC_UFS_PHY_RX_SYMBOL_0_CLK 164
+#define GCC_UFS_PHY_RX_SYMBOL_0_CLK_SRC 165
+#define GCC_UFS_PHY_RX_SYMBOL_1_CLK 166
+#define GCC_UFS_PHY_RX_SYMBOL_1_CLK_SRC 167
+#define GCC_UFS_PHY_TX_SYMBOL_0_CLK 168
+#define GCC_UFS_PHY_TX_SYMBOL_0_CLK_SRC 169
+#define GCC_UFS_PHY_UNIPRO_CORE_CLK 170
+#define GCC_UFS_PHY_UNIPRO_CORE_CLK_SRC 171
+#define GCC_UFS_PHY_UNIPRO_CORE_HW_CTL_CLK 172
+#define GCC_USB30_PRIM_MASTER_CLK 173
+#define GCC_USB30_PRIM_MASTER_CLK_SRC 174
+#define GCC_USB30_PRIM_MOCK_UTMI_CLK 175
+#define GCC_USB30_PRIM_MOCK_UTMI_CLK_SRC 176
+#define GCC_USB30_PRIM_MOCK_UTMI_POSTDIV_CLK_SRC 177
+#define GCC_USB30_PRIM_SLEEP_CLK 178
+#define GCC_USB3_PRIM_PHY_AUX_CLK 179
+#define GCC_USB3_PRIM_PHY_AUX_CLK_SRC 180
+#define GCC_USB3_PRIM_PHY_COM_AUX_CLK 181
+#define GCC_USB3_PRIM_PHY_PIPE_CLK 182
+#define GCC_USB3_PRIM_PHY_PIPE_CLK_SRC 183
+#define GCC_VIDEO_AHB_CLK 184
+#define GCC_VIDEO_AXI0_CLK 185
+#define GCC_VIDEO_AXI1_CLK 186
+#define GCC_VIDEO_XO_CLK 187
+#define GCC_GPLL0_AO 188
+#define GCC_GPLL0_OUT_EVEN_AO 189
+#define GCC_GPLL1_AO 190
+#define GCC_GPLL3_AO 191
+#define GCC_GPLL4_AO 192
+#define GCC_GPLL6_AO 193
+
+/* GCC resets */
+#define GCC_CAMERA_BCR 0
+#define GCC_DISPLAY_BCR 1
+#define GCC_GPU_BCR 2
+#define GCC_PCIE_0_BCR 3
+#define GCC_PCIE_0_LINK_DOWN_BCR 4
+#define GCC_PCIE_0_NOCSR_COM_PHY_BCR 5
+#define GCC_PCIE_0_PHY_BCR 6
+#define GCC_PCIE_0_PHY_NOCSR_COM_PHY_BCR 7
+#define GCC_PCIE_1_BCR 8
+#define GCC_PCIE_1_LINK_DOWN_BCR 9
+#define GCC_PCIE_1_NOCSR_COM_PHY_BCR 10
+#define GCC_PCIE_1_PHY_BCR 11
+#define GCC_PCIE_1_PHY_NOCSR_COM_PHY_BCR 12
+#define GCC_PCIE_PHY_BCR 13
+#define GCC_PCIE_PHY_CFG_AHB_BCR 14
+#define GCC_PCIE_PHY_COM_BCR 15
+#define GCC_PDM_BCR 16
+#define GCC_QUPV3_WRAPPER_1_BCR 17
+#define GCC_QUPV3_WRAPPER_2_BCR 18
+#define GCC_QUPV3_WRAPPER_3_BCR 19
+#define GCC_QUPV3_WRAPPER_I2C_BCR 20
+#define GCC_QUSB2PHY_PRIM_BCR 21
+#define GCC_QUSB2PHY_SEC_BCR 22
+#define GCC_SDCC2_BCR 23
+#define GCC_SDCC4_BCR 24
+#define GCC_UFS_PHY_BCR 25
+#define GCC_USB30_PRIM_BCR 26
+#define GCC_USB3_DP_PHY_PRIM_BCR 27
+#define GCC_USB3_DP_PHY_SEC_BCR 28
+#define GCC_USB3_PHY_PRIM_BCR 29
+#define GCC_USB3_PHY_SEC_BCR 30
+#define GCC_USB3PHY_PHY_PRIM_BCR 31
+#define GCC_USB3PHY_PHY_SEC_BCR 32
+#define GCC_VIDEO_AXI0_CLK_ARES 33
+#define GCC_VIDEO_AXI1_CLK_ARES 34
+#define GCC_VIDEO_BCR 35
+
+/* GCC power domains */
+#define PCIE_0_GDSC 0
+#define PCIE_0_PHY_GDSC 1
+#define PCIE_1_GDSC 2
+#define PCIE_1_PHY_GDSC 3
+#define UFS_PHY_GDSC 4
+#define UFS_MEM_PHY_GDSC 5
+#define USB30_PRIM_GDSC 6
+#define USB3_PHY_GDSC 7
+
+#endif
diff --git a/dts/upstream/include/dt-bindings/clock/qcom,sm8650-gpucc.h b/dts/upstream/include/dt-bindings/clock/qcom,sm8650-gpucc.h
new file mode 100644
index 0000000..d0dc457
--- /dev/null
+++ b/dts/upstream/include/dt-bindings/clock/qcom,sm8650-gpucc.h
@@ -0,0 +1,43 @@
+/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */
+/*
+ * Copyright (c) 2022, Qualcomm Innovation Center, Inc. All rights reserved
+ * Copyright (c) 2023, Linaro Limited
+ */
+
+#ifndef _DT_BINDINGS_CLK_QCOM_GPU_CC_SM8650_H
+#define _DT_BINDINGS_CLK_QCOM_GPU_CC_SM8650_H
+
+/* GPU_CC clocks */
+#define GPU_CC_AHB_CLK 0
+#define GPU_CC_CRC_AHB_CLK 1
+#define GPU_CC_CX_ACCU_SHIFT_CLK 2
+#define GPU_CC_CX_FF_CLK 3
+#define GPU_CC_CX_GMU_CLK 4
+#define GPU_CC_CXO_AON_CLK 5
+#define GPU_CC_CXO_CLK 6
+#define GPU_CC_DEMET_CLK 7
+#define GPU_CC_DPM_CLK 8
+#define GPU_CC_FF_CLK_SRC 9
+#define GPU_CC_FREQ_MEASURE_CLK 10
+#define GPU_CC_GMU_CLK_SRC 11
+#define GPU_CC_GX_ACCU_SHIFT_CLK 12
+#define GPU_CC_GX_FF_CLK 13
+#define GPU_CC_GX_GFX3D_CLK 14
+#define GPU_CC_GX_GFX3D_RDVM_CLK 15
+#define GPU_CC_GX_GMU_CLK 16
+#define GPU_CC_GX_VSENSE_CLK 17
+#define GPU_CC_HLOS1_VOTE_GPU_SMMU_CLK 18
+#define GPU_CC_HUB_AON_CLK 19
+#define GPU_CC_HUB_CLK_SRC 20
+#define GPU_CC_HUB_CX_INT_CLK 21
+#define GPU_CC_HUB_DIV_CLK_SRC 22
+#define GPU_CC_MEMNOC_GFX_CLK 23
+#define GPU_CC_PLL0 24
+#define GPU_CC_PLL1 25
+#define GPU_CC_SLEEP_CLK 26
+
+/* GDSCs */
+#define GPU_GX_GDSC 0
+#define GPU_CX_GDSC 1
+
+#endif
diff --git a/dts/upstream/include/dt-bindings/clock/qcom,sm8650-tcsr.h b/dts/upstream/include/dt-bindings/clock/qcom,sm8650-tcsr.h
new file mode 100644
index 0000000..b2c72d4
--- /dev/null
+++ b/dts/upstream/include/dt-bindings/clock/qcom,sm8650-tcsr.h
@@ -0,0 +1,18 @@
+/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */
+/*
+ * Copyright (c) 2022, Qualcomm Innovation Center, Inc. All rights reserved.
+ * Copyright (c) 2023, Linaro Limited
+ */
+
+#ifndef _DT_BINDINGS_CLK_QCOM_TCSR_CC_SM8650_H
+#define _DT_BINDINGS_CLK_QCOM_TCSR_CC_SM8650_H
+
+/* TCSR CC clocks */
+#define TCSR_PCIE_0_CLKREF_EN 0
+#define TCSR_PCIE_1_CLKREF_EN 1
+#define TCSR_UFS_CLKREF_EN 2
+#define TCSR_UFS_PAD_CLKREF_EN 3
+#define TCSR_USB2_CLKREF_EN 4
+#define TCSR_USB3_CLKREF_EN 5
+
+#endif
diff --git a/dts/upstream/include/dt-bindings/clock/qcom,videocc-sm8150.h b/dts/upstream/include/dt-bindings/clock/qcom,videocc-sm8150.h
index e24ee84..c557b78 100644
--- a/dts/upstream/include/dt-bindings/clock/qcom,videocc-sm8150.h
+++ b/dts/upstream/include/dt-bindings/clock/qcom,videocc-sm8150.h
@@ -16,6 +16,10 @@
/* VIDEO_CC Resets */
#define VIDEO_CC_MVSC_CORE_CLK_BCR 0
+#define VIDEO_CC_INTERFACE_BCR 1
+#define VIDEO_CC_MVS0_BCR 2
+#define VIDEO_CC_MVS1_BCR 3
+#define VIDEO_CC_MVSC_BCR 4
/* VIDEO_CC GDSCRs */
#define VENUS_GDSC 0
diff --git a/dts/upstream/include/dt-bindings/clock/qcom,x1e80100-gcc.h b/dts/upstream/include/dt-bindings/clock/qcom,x1e80100-gcc.h
new file mode 100644
index 0000000..24ba9e2
--- /dev/null
+++ b/dts/upstream/include/dt-bindings/clock/qcom,x1e80100-gcc.h
@@ -0,0 +1,485 @@
+/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */
+/*
+ * Copyright (c) 2023, Qualcomm Innovation Center, Inc. All rights reserved.
+ */
+
+#ifndef _DT_BINDINGS_CLK_QCOM_GCC_X1E80100_H
+#define _DT_BINDINGS_CLK_QCOM_GCC_X1E80100_H
+
+/* GCC clocks */
+#define GCC_AGGRE_NOC_USB_NORTH_AXI_CLK 0
+#define GCC_AGGRE_NOC_USB_SOUTH_AXI_CLK 1
+#define GCC_AGGRE_UFS_PHY_AXI_CLK 2
+#define GCC_AGGRE_USB2_PRIM_AXI_CLK 3
+#define GCC_AGGRE_USB3_MP_AXI_CLK 4
+#define GCC_AGGRE_USB3_PRIM_AXI_CLK 5
+#define GCC_AGGRE_USB3_SEC_AXI_CLK 6
+#define GCC_AGGRE_USB3_TERT_AXI_CLK 7
+#define GCC_AGGRE_USB4_0_AXI_CLK 8
+#define GCC_AGGRE_USB4_1_AXI_CLK 9
+#define GCC_AGGRE_USB4_2_AXI_CLK 10
+#define GCC_AGGRE_USB_NOC_AXI_CLK 11
+#define GCC_AV1E_AHB_CLK 12
+#define GCC_AV1E_AXI_CLK 13
+#define GCC_AV1E_XO_CLK 14
+#define GCC_BOOT_ROM_AHB_CLK 15
+#define GCC_CAMERA_AHB_CLK 16
+#define GCC_CAMERA_HF_AXI_CLK 17
+#define GCC_CAMERA_SF_AXI_CLK 18
+#define GCC_CAMERA_XO_CLK 19
+#define GCC_CFG_NOC_PCIE_ANOC_AHB_CLK 20
+#define GCC_CFG_NOC_PCIE_ANOC_NORTH_AHB_CLK 21
+#define GCC_CFG_NOC_PCIE_ANOC_SOUTH_AHB_CLK 22
+#define GCC_CFG_NOC_USB2_PRIM_AXI_CLK 23
+#define GCC_CFG_NOC_USB3_MP_AXI_CLK 24
+#define GCC_CFG_NOC_USB3_PRIM_AXI_CLK 25
+#define GCC_CFG_NOC_USB3_SEC_AXI_CLK 26
+#define GCC_CFG_NOC_USB3_TERT_AXI_CLK 27
+#define GCC_CFG_NOC_USB_ANOC_AHB_CLK 28
+#define GCC_CFG_NOC_USB_ANOC_NORTH_AHB_CLK 29
+#define GCC_CFG_NOC_USB_ANOC_SOUTH_AHB_CLK 30
+#define GCC_CNOC_PCIE1_TUNNEL_CLK 31
+#define GCC_CNOC_PCIE2_TUNNEL_CLK 32
+#define GCC_CNOC_PCIE_NORTH_SF_AXI_CLK 33
+#define GCC_CNOC_PCIE_SOUTH_SF_AXI_CLK 34
+#define GCC_CNOC_PCIE_TUNNEL_CLK 35
+#define GCC_DDRSS_GPU_AXI_CLK 36
+#define GCC_DISP_AHB_CLK 37
+#define GCC_DISP_HF_AXI_CLK 38
+#define GCC_DISP_XO_CLK 39
+#define GCC_GP1_CLK 40
+#define GCC_GP1_CLK_SRC 41
+#define GCC_GP2_CLK 42
+#define GCC_GP2_CLK_SRC 43
+#define GCC_GP3_CLK 44
+#define GCC_GP3_CLK_SRC 45
+#define GCC_GPLL0 46
+#define GCC_GPLL0_OUT_EVEN 47
+#define GCC_GPLL4 48
+#define GCC_GPLL7 49
+#define GCC_GPLL8 50
+#define GCC_GPLL9 51
+#define GCC_GPU_CFG_AHB_CLK 52
+#define GCC_GPU_GPLL0_CPH_CLK_SRC 53
+#define GCC_GPU_GPLL0_DIV_CPH_CLK_SRC 54
+#define GCC_GPU_MEMNOC_GFX_CLK 55
+#define GCC_GPU_SNOC_DVM_GFX_CLK 56
+#define GCC_PCIE0_PHY_RCHNG_CLK 57
+#define GCC_PCIE1_PHY_RCHNG_CLK 58
+#define GCC_PCIE2_PHY_RCHNG_CLK 59
+#define GCC_PCIE_0_AUX_CLK 60
+#define GCC_PCIE_0_AUX_CLK_SRC 61
+#define GCC_PCIE_0_CFG_AHB_CLK 62
+#define GCC_PCIE_0_MSTR_AXI_CLK 63
+#define GCC_PCIE_0_PHY_RCHNG_CLK_SRC 64
+#define GCC_PCIE_0_PIPE_CLK 65
+#define GCC_PCIE_0_SLV_AXI_CLK 66
+#define GCC_PCIE_0_SLV_Q2A_AXI_CLK 67
+#define GCC_PCIE_1_AUX_CLK 68
+#define GCC_PCIE_1_AUX_CLK_SRC 69
+#define GCC_PCIE_1_CFG_AHB_CLK 70
+#define GCC_PCIE_1_MSTR_AXI_CLK 71
+#define GCC_PCIE_1_PHY_RCHNG_CLK_SRC 72
+#define GCC_PCIE_1_PIPE_CLK 73
+#define GCC_PCIE_1_SLV_AXI_CLK 74
+#define GCC_PCIE_1_SLV_Q2A_AXI_CLK 75
+#define GCC_PCIE_2_AUX_CLK 76
+#define GCC_PCIE_2_AUX_CLK_SRC 77
+#define GCC_PCIE_2_CFG_AHB_CLK 78
+#define GCC_PCIE_2_MSTR_AXI_CLK 79
+#define GCC_PCIE_2_PHY_RCHNG_CLK_SRC 80
+#define GCC_PCIE_2_PIPE_CLK 81
+#define GCC_PCIE_2_SLV_AXI_CLK 82
+#define GCC_PCIE_2_SLV_Q2A_AXI_CLK 83
+#define GCC_PCIE_3_AUX_CLK 84
+#define GCC_PCIE_3_AUX_CLK_SRC 85
+#define GCC_PCIE_3_CFG_AHB_CLK 86
+#define GCC_PCIE_3_MSTR_AXI_CLK 87
+#define GCC_PCIE_3_PHY_AUX_CLK 88
+#define GCC_PCIE_3_PHY_RCHNG_CLK 89
+#define GCC_PCIE_3_PHY_RCHNG_CLK_SRC 90
+#define GCC_PCIE_3_PIPE_CLK 91
+#define GCC_PCIE_3_PIPE_DIV_CLK_SRC 92
+#define GCC_PCIE_3_PIPEDIV2_CLK 93
+#define GCC_PCIE_3_SLV_AXI_CLK 94
+#define GCC_PCIE_3_SLV_Q2A_AXI_CLK 95
+#define GCC_PCIE_4_AUX_CLK 96
+#define GCC_PCIE_4_AUX_CLK_SRC 97
+#define GCC_PCIE_4_CFG_AHB_CLK 98
+#define GCC_PCIE_4_MSTR_AXI_CLK 99
+#define GCC_PCIE_4_PHY_RCHNG_CLK 100
+#define GCC_PCIE_4_PHY_RCHNG_CLK_SRC 101
+#define GCC_PCIE_4_PIPE_CLK 102
+#define GCC_PCIE_4_PIPE_DIV_CLK_SRC 103
+#define GCC_PCIE_4_PIPEDIV2_CLK 104
+#define GCC_PCIE_4_SLV_AXI_CLK 105
+#define GCC_PCIE_4_SLV_Q2A_AXI_CLK 106
+#define GCC_PCIE_5_AUX_CLK 107
+#define GCC_PCIE_5_AUX_CLK_SRC 108
+#define GCC_PCIE_5_CFG_AHB_CLK 109
+#define GCC_PCIE_5_MSTR_AXI_CLK 110
+#define GCC_PCIE_5_PHY_RCHNG_CLK 111
+#define GCC_PCIE_5_PHY_RCHNG_CLK_SRC 112
+#define GCC_PCIE_5_PIPE_CLK 113
+#define GCC_PCIE_5_PIPE_DIV_CLK_SRC 114
+#define GCC_PCIE_5_PIPEDIV2_CLK 115
+#define GCC_PCIE_5_SLV_AXI_CLK 116
+#define GCC_PCIE_5_SLV_Q2A_AXI_CLK 117
+#define GCC_PCIE_6A_AUX_CLK 118
+#define GCC_PCIE_6A_AUX_CLK_SRC 119
+#define GCC_PCIE_6A_CFG_AHB_CLK 120
+#define GCC_PCIE_6A_MSTR_AXI_CLK 121
+#define GCC_PCIE_6A_PHY_AUX_CLK 122
+#define GCC_PCIE_6A_PHY_RCHNG_CLK 123
+#define GCC_PCIE_6A_PHY_RCHNG_CLK_SRC 124
+#define GCC_PCIE_6A_PIPE_CLK 125
+#define GCC_PCIE_6A_PIPE_DIV_CLK_SRC 126
+#define GCC_PCIE_6A_PIPEDIV2_CLK 127
+#define GCC_PCIE_6A_SLV_AXI_CLK 128
+#define GCC_PCIE_6A_SLV_Q2A_AXI_CLK 129
+#define GCC_PCIE_6B_AUX_CLK 130
+#define GCC_PCIE_6B_AUX_CLK_SRC 131
+#define GCC_PCIE_6B_CFG_AHB_CLK 132
+#define GCC_PCIE_6B_MSTR_AXI_CLK 133
+#define GCC_PCIE_6B_PHY_AUX_CLK 134
+#define GCC_PCIE_6B_PHY_RCHNG_CLK 135
+#define GCC_PCIE_6B_PHY_RCHNG_CLK_SRC 136
+#define GCC_PCIE_6B_PIPE_CLK 137
+#define GCC_PCIE_6B_PIPE_DIV_CLK_SRC 138
+#define GCC_PCIE_6B_PIPEDIV2_CLK 139
+#define GCC_PCIE_6B_SLV_AXI_CLK 140
+#define GCC_PCIE_6B_SLV_Q2A_AXI_CLK 141
+#define GCC_PCIE_RSCC_AHB_CLK 142
+#define GCC_PCIE_RSCC_XO_CLK 143
+#define GCC_PCIE_RSCC_XO_CLK_SRC 144
+#define GCC_PDM2_CLK 145
+#define GCC_PDM2_CLK_SRC 146
+#define GCC_PDM_AHB_CLK 147
+#define GCC_PDM_XO4_CLK 148
+#define GCC_QMIP_AV1E_AHB_CLK 149
+#define GCC_QMIP_CAMERA_NRT_AHB_CLK 150
+#define GCC_QMIP_CAMERA_RT_AHB_CLK 151
+#define GCC_QMIP_DISP_AHB_CLK 152
+#define GCC_QMIP_GPU_AHB_CLK 153
+#define GCC_QMIP_VIDEO_CV_CPU_AHB_CLK 154
+#define GCC_QMIP_VIDEO_CVP_AHB_CLK 155
+#define GCC_QMIP_VIDEO_V_CPU_AHB_CLK 156
+#define GCC_QMIP_VIDEO_VCODEC_AHB_CLK 157
+#define GCC_QUPV3_WRAP0_CORE_2X_CLK 158
+#define GCC_QUPV3_WRAP0_CORE_CLK 159
+#define GCC_QUPV3_WRAP0_QSPI_S2_CLK 160
+#define GCC_QUPV3_WRAP0_QSPI_S3_CLK 161
+#define GCC_QUPV3_WRAP0_S0_CLK 162
+#define GCC_QUPV3_WRAP0_S0_CLK_SRC 163
+#define GCC_QUPV3_WRAP0_S1_CLK 164
+#define GCC_QUPV3_WRAP0_S1_CLK_SRC 165
+#define GCC_QUPV3_WRAP0_S2_CLK 166
+#define GCC_QUPV3_WRAP0_S2_CLK_SRC 167
+#define GCC_QUPV3_WRAP0_S2_DIV_CLK_SRC 168
+#define GCC_QUPV3_WRAP0_S3_CLK 169
+#define GCC_QUPV3_WRAP0_S3_CLK_SRC 170
+#define GCC_QUPV3_WRAP0_S3_DIV_CLK_SRC 171
+#define GCC_QUPV3_WRAP0_S4_CLK 172
+#define GCC_QUPV3_WRAP0_S4_CLK_SRC 173
+#define GCC_QUPV3_WRAP0_S5_CLK 174
+#define GCC_QUPV3_WRAP0_S5_CLK_SRC 175
+#define GCC_QUPV3_WRAP0_S6_CLK 176
+#define GCC_QUPV3_WRAP0_S6_CLK_SRC 177
+#define GCC_QUPV3_WRAP0_S7_CLK 178
+#define GCC_QUPV3_WRAP0_S7_CLK_SRC 179
+#define GCC_QUPV3_WRAP1_CORE_2X_CLK 180
+#define GCC_QUPV3_WRAP1_CORE_CLK 181
+#define GCC_QUPV3_WRAP1_QSPI_S2_CLK 182
+#define GCC_QUPV3_WRAP1_QSPI_S3_CLK 183
+#define GCC_QUPV3_WRAP1_S0_CLK 184
+#define GCC_QUPV3_WRAP1_S0_CLK_SRC 185
+#define GCC_QUPV3_WRAP1_S1_CLK 186
+#define GCC_QUPV3_WRAP1_S1_CLK_SRC 187
+#define GCC_QUPV3_WRAP1_S2_CLK 188
+#define GCC_QUPV3_WRAP1_S2_CLK_SRC 189
+#define GCC_QUPV3_WRAP1_S2_DIV_CLK_SRC 190
+#define GCC_QUPV3_WRAP1_S3_CLK 191
+#define GCC_QUPV3_WRAP1_S3_CLK_SRC 192
+#define GCC_QUPV3_WRAP1_S3_DIV_CLK_SRC 193
+#define GCC_QUPV3_WRAP1_S4_CLK 194
+#define GCC_QUPV3_WRAP1_S4_CLK_SRC 195
+#define GCC_QUPV3_WRAP1_S5_CLK 196
+#define GCC_QUPV3_WRAP1_S5_CLK_SRC 197
+#define GCC_QUPV3_WRAP1_S6_CLK 198
+#define GCC_QUPV3_WRAP1_S6_CLK_SRC 199
+#define GCC_QUPV3_WRAP1_S7_CLK 200
+#define GCC_QUPV3_WRAP1_S7_CLK_SRC 201
+#define GCC_QUPV3_WRAP2_CORE_2X_CLK 202
+#define GCC_QUPV3_WRAP2_CORE_CLK 203
+#define GCC_QUPV3_WRAP2_QSPI_S2_CLK 204
+#define GCC_QUPV3_WRAP2_QSPI_S3_CLK 205
+#define GCC_QUPV3_WRAP2_S0_CLK 206
+#define GCC_QUPV3_WRAP2_S0_CLK_SRC 207
+#define GCC_QUPV3_WRAP2_S1_CLK 208
+#define GCC_QUPV3_WRAP2_S1_CLK_SRC 209
+#define GCC_QUPV3_WRAP2_S2_CLK 210
+#define GCC_QUPV3_WRAP2_S2_CLK_SRC 211
+#define GCC_QUPV3_WRAP2_S2_DIV_CLK_SRC 212
+#define GCC_QUPV3_WRAP2_S3_CLK 213
+#define GCC_QUPV3_WRAP2_S3_CLK_SRC 214
+#define GCC_QUPV3_WRAP2_S3_DIV_CLK_SRC 215
+#define GCC_QUPV3_WRAP2_S4_CLK 216
+#define GCC_QUPV3_WRAP2_S4_CLK_SRC 217
+#define GCC_QUPV3_WRAP2_S5_CLK 218
+#define GCC_QUPV3_WRAP2_S5_CLK_SRC 219
+#define GCC_QUPV3_WRAP2_S6_CLK 220
+#define GCC_QUPV3_WRAP2_S6_CLK_SRC 221
+#define GCC_QUPV3_WRAP2_S7_CLK 222
+#define GCC_QUPV3_WRAP2_S7_CLK_SRC 223
+#define GCC_QUPV3_WRAP_0_M_AHB_CLK 224
+#define GCC_QUPV3_WRAP_0_S_AHB_CLK 225
+#define GCC_QUPV3_WRAP_1_M_AHB_CLK 226
+#define GCC_QUPV3_WRAP_1_S_AHB_CLK 227
+#define GCC_QUPV3_WRAP_2_M_AHB_CLK 228
+#define GCC_QUPV3_WRAP_2_S_AHB_CLK 229
+#define GCC_SDCC2_AHB_CLK 230
+#define GCC_SDCC2_APPS_CLK 231
+#define GCC_SDCC2_APPS_CLK_SRC 232
+#define GCC_SDCC4_AHB_CLK 233
+#define GCC_SDCC4_APPS_CLK 234
+#define GCC_SDCC4_APPS_CLK_SRC 235
+#define GCC_SYS_NOC_USB_AXI_CLK 236
+#define GCC_UFS_PHY_AHB_CLK 237
+#define GCC_UFS_PHY_AXI_CLK 238
+#define GCC_UFS_PHY_AXI_CLK_SRC 239
+#define GCC_UFS_PHY_ICE_CORE_CLK 240
+#define GCC_UFS_PHY_ICE_CORE_CLK_SRC 241
+#define GCC_UFS_PHY_PHY_AUX_CLK 242
+#define GCC_UFS_PHY_PHY_AUX_CLK_SRC 243
+#define GCC_UFS_PHY_RX_SYMBOL_0_CLK 244
+#define GCC_UFS_PHY_RX_SYMBOL_1_CLK 245
+#define GCC_UFS_PHY_TX_SYMBOL_0_CLK 246
+#define GCC_UFS_PHY_UNIPRO_CORE_CLK 247
+#define GCC_UFS_PHY_UNIPRO_CORE_CLK_SRC 248
+#define GCC_USB20_MASTER_CLK 249
+#define GCC_USB20_MASTER_CLK_SRC 250
+#define GCC_USB20_MOCK_UTMI_CLK 251
+#define GCC_USB20_MOCK_UTMI_CLK_SRC 252
+#define GCC_USB20_MOCK_UTMI_POSTDIV_CLK_SRC 253
+#define GCC_USB20_SLEEP_CLK 254
+#define GCC_USB30_MP_MASTER_CLK 255
+#define GCC_USB30_MP_MASTER_CLK_SRC 256
+#define GCC_USB30_MP_MOCK_UTMI_CLK 257
+#define GCC_USB30_MP_MOCK_UTMI_CLK_SRC 258
+#define GCC_USB30_MP_MOCK_UTMI_POSTDIV_CLK_SRC 259
+#define GCC_USB30_MP_SLEEP_CLK 260
+#define GCC_USB30_PRIM_MASTER_CLK 261
+#define GCC_USB30_PRIM_MASTER_CLK_SRC 262
+#define GCC_USB30_PRIM_MOCK_UTMI_CLK 263
+#define GCC_USB30_PRIM_MOCK_UTMI_CLK_SRC 264
+#define GCC_USB30_PRIM_MOCK_UTMI_POSTDIV_CLK_SRC 265
+#define GCC_USB30_PRIM_SLEEP_CLK 266
+#define GCC_USB30_SEC_MASTER_CLK 267
+#define GCC_USB30_SEC_MASTER_CLK_SRC 268
+#define GCC_USB30_SEC_MOCK_UTMI_CLK 269
+#define GCC_USB30_SEC_MOCK_UTMI_CLK_SRC 270
+#define GCC_USB30_SEC_MOCK_UTMI_POSTDIV_CLK_SRC 271
+#define GCC_USB30_SEC_SLEEP_CLK 272
+#define GCC_USB30_TERT_MASTER_CLK 273
+#define GCC_USB30_TERT_MASTER_CLK_SRC 274
+#define GCC_USB30_TERT_MOCK_UTMI_CLK 275
+#define GCC_USB30_TERT_MOCK_UTMI_CLK_SRC 276
+#define GCC_USB30_TERT_MOCK_UTMI_POSTDIV_CLK_SRC 277
+#define GCC_USB30_TERT_SLEEP_CLK 278
+#define GCC_USB3_MP_PHY_AUX_CLK 279
+#define GCC_USB3_MP_PHY_AUX_CLK_SRC 280
+#define GCC_USB3_MP_PHY_COM_AUX_CLK 281
+#define GCC_USB3_MP_PHY_PIPE_0_CLK 282
+#define GCC_USB3_MP_PHY_PIPE_1_CLK 283
+#define GCC_USB3_PRIM_PHY_AUX_CLK 284
+#define GCC_USB3_PRIM_PHY_AUX_CLK_SRC 285
+#define GCC_USB3_PRIM_PHY_COM_AUX_CLK 286
+#define GCC_USB3_PRIM_PHY_PIPE_CLK 287
+#define GCC_USB3_SEC_PHY_AUX_CLK 288
+#define GCC_USB3_SEC_PHY_AUX_CLK_SRC 289
+#define GCC_USB3_SEC_PHY_COM_AUX_CLK 290
+#define GCC_USB3_SEC_PHY_PIPE_CLK 291
+#define GCC_USB3_TERT_PHY_AUX_CLK 292
+#define GCC_USB3_TERT_PHY_AUX_CLK_SRC 293
+#define GCC_USB3_TERT_PHY_COM_AUX_CLK 294
+#define GCC_USB3_TERT_PHY_PIPE_CLK 295
+#define GCC_USB4_0_CFG_AHB_CLK 296
+#define GCC_USB4_0_DP0_CLK 297
+#define GCC_USB4_0_DP1_CLK 298
+#define GCC_USB4_0_MASTER_CLK 299
+#define GCC_USB4_0_MASTER_CLK_SRC 300
+#define GCC_USB4_0_PHY_P2RR2P_PIPE_CLK 301
+#define GCC_USB4_0_PHY_PCIE_PIPE_CLK 302
+#define GCC_USB4_0_PHY_PCIE_PIPE_CLK_SRC 303
+#define GCC_USB4_0_PHY_RX0_CLK 304
+#define GCC_USB4_0_PHY_RX1_CLK 305
+#define GCC_USB4_0_PHY_USB_PIPE_CLK 306
+#define GCC_USB4_0_SB_IF_CLK 307
+#define GCC_USB4_0_SB_IF_CLK_SRC 308
+#define GCC_USB4_0_SYS_CLK 309
+#define GCC_USB4_0_TMU_CLK 310
+#define GCC_USB4_0_TMU_CLK_SRC 311
+#define GCC_USB4_1_CFG_AHB_CLK 312
+#define GCC_USB4_1_DP0_CLK 313
+#define GCC_USB4_1_DP1_CLK 314
+#define GCC_USB4_1_MASTER_CLK 315
+#define GCC_USB4_1_MASTER_CLK_SRC 316
+#define GCC_USB4_1_PHY_P2RR2P_PIPE_CLK 317
+#define GCC_USB4_1_PHY_PCIE_PIPE_CLK 318
+#define GCC_USB4_1_PHY_PCIE_PIPE_CLK_SRC 319
+#define GCC_USB4_1_PHY_RX0_CLK 320
+#define GCC_USB4_1_PHY_RX1_CLK 321
+#define GCC_USB4_1_PHY_USB_PIPE_CLK 322
+#define GCC_USB4_1_SB_IF_CLK 323
+#define GCC_USB4_1_SB_IF_CLK_SRC 324
+#define GCC_USB4_1_SYS_CLK 325
+#define GCC_USB4_1_TMU_CLK 326
+#define GCC_USB4_1_TMU_CLK_SRC 327
+#define GCC_USB4_2_CFG_AHB_CLK 328
+#define GCC_USB4_2_DP0_CLK 329
+#define GCC_USB4_2_DP1_CLK 330
+#define GCC_USB4_2_MASTER_CLK 331
+#define GCC_USB4_2_MASTER_CLK_SRC 332
+#define GCC_USB4_2_PHY_P2RR2P_PIPE_CLK 333
+#define GCC_USB4_2_PHY_PCIE_PIPE_CLK 334
+#define GCC_USB4_2_PHY_PCIE_PIPE_CLK_SRC 335
+#define GCC_USB4_2_PHY_RX0_CLK 336
+#define GCC_USB4_2_PHY_RX1_CLK 337
+#define GCC_USB4_2_PHY_USB_PIPE_CLK 338
+#define GCC_USB4_2_SB_IF_CLK 339
+#define GCC_USB4_2_SB_IF_CLK_SRC 340
+#define GCC_USB4_2_SYS_CLK 341
+#define GCC_USB4_2_TMU_CLK 342
+#define GCC_USB4_2_TMU_CLK_SRC 343
+#define GCC_VIDEO_AHB_CLK 344
+#define GCC_VIDEO_AXI0_CLK 345
+#define GCC_VIDEO_AXI1_CLK 346
+#define GCC_VIDEO_XO_CLK 347
+#define GCC_PCIE_3_PIPE_CLK_SRC 348
+#define GCC_PCIE_4_PIPE_CLK_SRC 349
+#define GCC_PCIE_5_PIPE_CLK_SRC 350
+#define GCC_PCIE_6A_PIPE_CLK_SRC 351
+#define GCC_PCIE_6B_PIPE_CLK_SRC 352
+#define GCC_USB3_PRIM_PHY_PIPE_CLK_SRC 353
+#define GCC_USB3_SEC_PHY_PIPE_CLK_SRC 354
+#define GCC_USB3_TERT_PHY_PIPE_CLK_SRC 355
+
+/* GCC power domains */
+#define GCC_PCIE_0_TUNNEL_GDSC 0
+#define GCC_PCIE_1_TUNNEL_GDSC 1
+#define GCC_PCIE_2_TUNNEL_GDSC 2
+#define GCC_PCIE_3_GDSC 3
+#define GCC_PCIE_3_PHY_GDSC 4
+#define GCC_PCIE_4_GDSC 5
+#define GCC_PCIE_4_PHY_GDSC 6
+#define GCC_PCIE_5_GDSC 7
+#define GCC_PCIE_5_PHY_GDSC 8
+#define GCC_PCIE_6_PHY_GDSC 9
+#define GCC_PCIE_6A_GDSC 10
+#define GCC_PCIE_6B_GDSC 11
+#define GCC_UFS_MEM_PHY_GDSC 12
+#define GCC_UFS_PHY_GDSC 13
+#define GCC_USB20_PRIM_GDSC 14
+#define GCC_USB30_MP_GDSC 15
+#define GCC_USB30_PRIM_GDSC 16
+#define GCC_USB30_SEC_GDSC 17
+#define GCC_USB30_TERT_GDSC 18
+#define GCC_USB3_MP_SS0_PHY_GDSC 19
+#define GCC_USB3_MP_SS1_PHY_GDSC 20
+#define GCC_USB4_0_GDSC 21
+#define GCC_USB4_1_GDSC 22
+#define GCC_USB4_2_GDSC 23
+#define GCC_USB_0_PHY_GDSC 24
+#define GCC_USB_1_PHY_GDSC 25
+#define GCC_USB_2_PHY_GDSC 26
+
+/* GCC resets */
+#define GCC_AV1E_BCR 0
+#define GCC_CAMERA_BCR 1
+#define GCC_DISPLAY_BCR 2
+#define GCC_GPU_BCR 3
+#define GCC_PCIE_0_LINK_DOWN_BCR 4
+#define GCC_PCIE_0_NOCSR_COM_PHY_BCR 5
+#define GCC_PCIE_0_PHY_BCR 6
+#define GCC_PCIE_0_PHY_NOCSR_COM_PHY_BCR 7
+#define GCC_PCIE_0_TUNNEL_BCR 8
+#define GCC_PCIE_1_LINK_DOWN_BCR 9
+#define GCC_PCIE_1_NOCSR_COM_PHY_BCR 10
+#define GCC_PCIE_1_PHY_BCR 11
+#define GCC_PCIE_1_PHY_NOCSR_COM_PHY_BCR 12
+#define GCC_PCIE_1_TUNNEL_BCR 13
+#define GCC_PCIE_2_LINK_DOWN_BCR 14
+#define GCC_PCIE_2_NOCSR_COM_PHY_BCR 15
+#define GCC_PCIE_2_PHY_BCR 16
+#define GCC_PCIE_2_PHY_NOCSR_COM_PHY_BCR 17
+#define GCC_PCIE_2_TUNNEL_BCR 18
+#define GCC_PCIE_3_BCR 19
+#define GCC_PCIE_3_LINK_DOWN_BCR 20
+#define GCC_PCIE_3_NOCSR_COM_PHY_BCR 21
+#define GCC_PCIE_3_PHY_BCR 22
+#define GCC_PCIE_3_PHY_NOCSR_COM_PHY_BCR 23
+#define GCC_PCIE_4_BCR 24
+#define GCC_PCIE_4_LINK_DOWN_BCR 25
+#define GCC_PCIE_4_NOCSR_COM_PHY_BCR 26
+#define GCC_PCIE_4_PHY_BCR 27
+#define GCC_PCIE_4_PHY_NOCSR_COM_PHY_BCR 28
+#define GCC_PCIE_5_BCR 29
+#define GCC_PCIE_5_LINK_DOWN_BCR 30
+#define GCC_PCIE_5_NOCSR_COM_PHY_BCR 31
+#define GCC_PCIE_5_PHY_BCR 32
+#define GCC_PCIE_5_PHY_NOCSR_COM_PHY_BCR 33
+#define GCC_PCIE_6A_BCR 34
+#define GCC_PCIE_6A_LINK_DOWN_BCR 35
+#define GCC_PCIE_6A_NOCSR_COM_PHY_BCR 36
+#define GCC_PCIE_6A_PHY_BCR 37
+#define GCC_PCIE_6A_PHY_NOCSR_COM_PHY_BCR 38
+#define GCC_PCIE_6B_BCR 39
+#define GCC_PCIE_6B_LINK_DOWN_BCR 40
+#define GCC_PCIE_6B_NOCSR_COM_PHY_BCR 41
+#define GCC_PCIE_6B_PHY_BCR 42
+#define GCC_PCIE_6B_PHY_NOCSR_COM_PHY_BCR 43
+#define GCC_PCIE_PHY_BCR 44
+#define GCC_PCIE_PHY_CFG_AHB_BCR 45
+#define GCC_PCIE_PHY_COM_BCR 46
+#define GCC_PCIE_RSCC_BCR 47
+#define GCC_PDM_BCR 48
+#define GCC_QUPV3_WRAPPER_0_BCR 49
+#define GCC_QUPV3_WRAPPER_1_BCR 50
+#define GCC_QUPV3_WRAPPER_2_BCR 51
+#define GCC_QUSB2PHY_HS0_MP_BCR 52
+#define GCC_QUSB2PHY_HS1_MP_BCR 53
+#define GCC_QUSB2PHY_PRIM_BCR 54
+#define GCC_QUSB2PHY_SEC_BCR 55
+#define GCC_QUSB2PHY_TERT_BCR 56
+#define GCC_QUSB2PHY_USB20_HS_BCR 57
+#define GCC_SDCC2_BCR 58
+#define GCC_SDCC4_BCR 59
+#define GCC_UFS_PHY_BCR 60
+#define GCC_USB20_PRIM_BCR 61
+#define GCC_USB30_MP_BCR 62
+#define GCC_USB30_PRIM_BCR 63
+#define GCC_USB30_SEC_BCR 64
+#define GCC_USB30_TERT_BCR 65
+#define GCC_USB3_MP_SS0_PHY_BCR 66
+#define GCC_USB3_MP_SS1_PHY_BCR 67
+#define GCC_USB3_PHY_PRIM_BCR 68
+#define GCC_USB3_PHY_SEC_BCR 69
+#define GCC_USB3_PHY_TERT_BCR 70
+#define GCC_USB3_UNIPHY_MP0_BCR 71
+#define GCC_USB3_UNIPHY_MP1_BCR 72
+#define GCC_USB3PHY_PHY_PRIM_BCR 73
+#define GCC_USB3PHY_PHY_SEC_BCR 74
+#define GCC_USB3PHY_PHY_TERT_BCR 75
+#define GCC_USB3UNIPHY_PHY_MP0_BCR 76
+#define GCC_USB3UNIPHY_PHY_MP1_BCR 77
+#define GCC_USB4_0_BCR 78
+#define GCC_USB4_0_DP0_PHY_PRIM_BCR 79
+#define GCC_USB4_1_DP0_PHY_SEC_BCR 80
+#define GCC_USB4_2_DP0_PHY_TERT_BCR 81
+#define GCC_USB4_1_BCR 82
+#define GCC_USB4_2_BCR 83
+#define GCC_USB_0_PHY_BCR 84
+#define GCC_USB_1_PHY_BCR 85
+#define GCC_USB_2_PHY_BCR 86
+#define GCC_VIDEO_BCR 87
+#endif
diff --git a/dts/upstream/include/dt-bindings/clock/sophgo,cv1800.h b/dts/upstream/include/dt-bindings/clock/sophgo,cv1800.h
new file mode 100644
index 0000000..cfbeca2
--- /dev/null
+++ b/dts/upstream/include/dt-bindings/clock/sophgo,cv1800.h
@@ -0,0 +1,176 @@
+/* SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause */
+/*
+ * Copyright (C) 2023 Sophgo Ltd.
+ */
+
+#ifndef __DT_BINDINGS_SOPHGO_CV1800_CLK_H__
+#define __DT_BINDINGS_SOPHGO_CV1800_CLK_H__
+
+#define CLK_MPLL 0
+#define CLK_TPLL 1
+#define CLK_FPLL 2
+#define CLK_MIPIMPLL 3
+#define CLK_A0PLL 4
+#define CLK_DISPPLL 5
+#define CLK_CAM0PLL 6
+#define CLK_CAM1PLL 7
+
+#define CLK_MIPIMPLL_D3 8
+#define CLK_CAM0PLL_D2 9
+#define CLK_CAM0PLL_D3 10
+
+#define CLK_TPU 11
+#define CLK_TPU_FAB 12
+#define CLK_AHB_ROM 13
+#define CLK_DDR_AXI_REG 14
+#define CLK_RTC_25M 15
+#define CLK_SRC_RTC_SYS_0 16
+#define CLK_TEMPSEN 17
+#define CLK_SARADC 18
+#define CLK_EFUSE 19
+#define CLK_APB_EFUSE 20
+#define CLK_DEBUG 21
+#define CLK_AP_DEBUG 22
+#define CLK_XTAL_MISC 23
+#define CLK_AXI4_EMMC 24
+#define CLK_EMMC 25
+#define CLK_EMMC_100K 26
+#define CLK_AXI4_SD0 27
+#define CLK_SD0 28
+#define CLK_SD0_100K 29
+#define CLK_AXI4_SD1 30
+#define CLK_SD1 31
+#define CLK_SD1_100K 32
+#define CLK_SPI_NAND 33
+#define CLK_ETH0_500M 34
+#define CLK_AXI4_ETH0 35
+#define CLK_ETH1_500M 36
+#define CLK_AXI4_ETH1 37
+#define CLK_APB_GPIO 38
+#define CLK_APB_GPIO_INTR 39
+#define CLK_GPIO_DB 40
+#define CLK_AHB_SF 41
+#define CLK_AHB_SF1 42
+#define CLK_A24M 43
+#define CLK_AUDSRC 44
+#define CLK_APB_AUDSRC 45
+#define CLK_SDMA_AXI 46
+#define CLK_SDMA_AUD0 47
+#define CLK_SDMA_AUD1 48
+#define CLK_SDMA_AUD2 49
+#define CLK_SDMA_AUD3 50
+#define CLK_I2C 51
+#define CLK_APB_I2C 52
+#define CLK_APB_I2C0 53
+#define CLK_APB_I2C1 54
+#define CLK_APB_I2C2 55
+#define CLK_APB_I2C3 56
+#define CLK_APB_I2C4 57
+#define CLK_APB_WDT 58
+#define CLK_PWM_SRC 59
+#define CLK_PWM 60
+#define CLK_SPI 61
+#define CLK_APB_SPI0 62
+#define CLK_APB_SPI1 63
+#define CLK_APB_SPI2 64
+#define CLK_APB_SPI3 65
+#define CLK_1M 66
+#define CLK_CAM0_200 67
+#define CLK_PM 68
+#define CLK_TIMER0 69
+#define CLK_TIMER1 70
+#define CLK_TIMER2 71
+#define CLK_TIMER3 72
+#define CLK_TIMER4 73
+#define CLK_TIMER5 74
+#define CLK_TIMER6 75
+#define CLK_TIMER7 76
+#define CLK_UART0 77
+#define CLK_APB_UART0 78
+#define CLK_UART1 79
+#define CLK_APB_UART1 80
+#define CLK_UART2 81
+#define CLK_APB_UART2 82
+#define CLK_UART3 83
+#define CLK_APB_UART3 84
+#define CLK_UART4 85
+#define CLK_APB_UART4 86
+#define CLK_APB_I2S0 87
+#define CLK_APB_I2S1 88
+#define CLK_APB_I2S2 89
+#define CLK_APB_I2S3 90
+#define CLK_AXI4_USB 91
+#define CLK_APB_USB 92
+#define CLK_USB_125M 93
+#define CLK_USB_33K 94
+#define CLK_USB_12M 95
+#define CLK_AXI4 96
+#define CLK_AXI6 97
+#define CLK_DSI_ESC 98
+#define CLK_AXI_VIP 99
+#define CLK_SRC_VIP_SYS_0 100
+#define CLK_SRC_VIP_SYS_1 101
+#define CLK_SRC_VIP_SYS_2 102
+#define CLK_SRC_VIP_SYS_3 103
+#define CLK_SRC_VIP_SYS_4 104
+#define CLK_CSI_BE_VIP 105
+#define CLK_CSI_MAC0_VIP 106
+#define CLK_CSI_MAC1_VIP 107
+#define CLK_CSI_MAC2_VIP 108
+#define CLK_CSI0_RX_VIP 109
+#define CLK_CSI1_RX_VIP 110
+#define CLK_ISP_TOP_VIP 111
+#define CLK_IMG_D_VIP 112
+#define CLK_IMG_V_VIP 113
+#define CLK_SC_TOP_VIP 114
+#define CLK_SC_D_VIP 115
+#define CLK_SC_V1_VIP 116
+#define CLK_SC_V2_VIP 117
+#define CLK_SC_V3_VIP 118
+#define CLK_DWA_VIP 119
+#define CLK_BT_VIP 120
+#define CLK_DISP_VIP 121
+#define CLK_DSI_MAC_VIP 122
+#define CLK_LVDS0_VIP 123
+#define CLK_LVDS1_VIP 124
+#define CLK_PAD_VI_VIP 125
+#define CLK_PAD_VI1_VIP 126
+#define CLK_PAD_VI2_VIP 127
+#define CLK_CFG_REG_VIP 128
+#define CLK_VIP_IP0 129
+#define CLK_VIP_IP1 130
+#define CLK_VIP_IP2 131
+#define CLK_VIP_IP3 132
+#define CLK_IVE_VIP 133
+#define CLK_RAW_VIP 134
+#define CLK_OSDC_VIP 135
+#define CLK_CAM0_VIP 136
+#define CLK_AXI_VIDEO_CODEC 137
+#define CLK_VC_SRC0 138
+#define CLK_VC_SRC1 139
+#define CLK_VC_SRC2 140
+#define CLK_H264C 141
+#define CLK_APB_H264C 142
+#define CLK_H265C 143
+#define CLK_APB_H265C 144
+#define CLK_JPEG 145
+#define CLK_APB_JPEG 146
+#define CLK_CAM0 147
+#define CLK_CAM1 148
+#define CLK_WGN 149
+#define CLK_WGN0 150
+#define CLK_WGN1 151
+#define CLK_WGN2 152
+#define CLK_KEYSCAN 153
+#define CLK_CFG_REG_VC 154
+#define CLK_C906_0 155
+#define CLK_C906_1 156
+#define CLK_A53 157
+#define CLK_CPU_AXI0 158
+#define CLK_CPU_GIC 159
+#define CLK_XTAL_AP 160
+
+// Only for CV181x
+#define CLK_DISP_SRC_VIP 161
+
+#endif /* __DT_BINDINGS_SOPHGO_CV1800_CLK_H__ */
diff --git a/dts/upstream/include/dt-bindings/clock/st,stm32mp25-rcc.h b/dts/upstream/include/dt-bindings/clock/st,stm32mp25-rcc.h
new file mode 100644
index 0000000..b6cf05a
--- /dev/null
+++ b/dts/upstream/include/dt-bindings/clock/st,stm32mp25-rcc.h
@@ -0,0 +1,492 @@
+/* SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause */
+/*
+ * Copyright (C) STMicroelectronics 2023 - All Rights Reserved
+ * Author: Gabriel Fernandez <gabriel.fernandez@foss.st.com>
+ */
+
+#ifndef _DT_BINDINGS_STM32MP25_CLKS_H_
+#define _DT_BINDINGS_STM32MP25_CLKS_H_
+
+/* INTERNAL/EXTERNAL OSCILLATORS */
+#define HSI_CK 0
+#define HSE_CK 1
+#define MSI_CK 2
+#define LSI_CK 3
+#define LSE_CK 4
+#define I2S_CK 5
+#define RTC_CK 6
+#define SPDIF_CK_SYMB 7
+
+/* PLL CLOCKS */
+#define PLL1_CK 8
+#define PLL2_CK 9
+#define PLL3_CK 10
+#define PLL4_CK 11
+#define PLL5_CK 12
+#define PLL6_CK 13
+#define PLL7_CK 14
+#define PLL8_CK 15
+
+#define CK_CPU1 16
+
+/* APB DIV CLOCKS */
+#define CK_ICN_APB1 17
+#define CK_ICN_APB2 18
+#define CK_ICN_APB3 19
+#define CK_ICN_APB4 20
+#define CK_ICN_APBDBG 21
+
+/* GLOBAL TIMER */
+#define TIMG1_CK 22
+#define TIMG2_CK 23
+
+/* FLEXGEN CLOCKS */
+#define CK_ICN_HS_MCU 24
+#define CK_ICN_SDMMC 25
+#define CK_ICN_DDR 26
+#define CK_ICN_DISPLAY 27
+#define CK_ICN_HSL 28
+#define CK_ICN_NIC 29
+#define CK_ICN_VID 30
+#define CK_FLEXGEN_07 31
+#define CK_FLEXGEN_08 32
+#define CK_FLEXGEN_09 33
+#define CK_FLEXGEN_10 34
+#define CK_FLEXGEN_11 35
+#define CK_FLEXGEN_12 36
+#define CK_FLEXGEN_13 37
+#define CK_FLEXGEN_14 38
+#define CK_FLEXGEN_15 39
+#define CK_FLEXGEN_16 40
+#define CK_FLEXGEN_17 41
+#define CK_FLEXGEN_18 42
+#define CK_FLEXGEN_19 43
+#define CK_FLEXGEN_20 44
+#define CK_FLEXGEN_21 45
+#define CK_FLEXGEN_22 46
+#define CK_FLEXGEN_23 47
+#define CK_FLEXGEN_24 48
+#define CK_FLEXGEN_25 49
+#define CK_FLEXGEN_26 50
+#define CK_FLEXGEN_27 51
+#define CK_FLEXGEN_28 52
+#define CK_FLEXGEN_29 53
+#define CK_FLEXGEN_30 54
+#define CK_FLEXGEN_31 55
+#define CK_FLEXGEN_32 56
+#define CK_FLEXGEN_33 57
+#define CK_FLEXGEN_34 58
+#define CK_FLEXGEN_35 59
+#define CK_FLEXGEN_36 60
+#define CK_FLEXGEN_37 61
+#define CK_FLEXGEN_38 62
+#define CK_FLEXGEN_39 63
+#define CK_FLEXGEN_40 64
+#define CK_FLEXGEN_41 65
+#define CK_FLEXGEN_42 66
+#define CK_FLEXGEN_43 67
+#define CK_FLEXGEN_44 68
+#define CK_FLEXGEN_45 69
+#define CK_FLEXGEN_46 70
+#define CK_FLEXGEN_47 71
+#define CK_FLEXGEN_48 72
+#define CK_FLEXGEN_49 73
+#define CK_FLEXGEN_50 74
+#define CK_FLEXGEN_51 75
+#define CK_FLEXGEN_52 76
+#define CK_FLEXGEN_53 77
+#define CK_FLEXGEN_54 78
+#define CK_FLEXGEN_55 79
+#define CK_FLEXGEN_56 80
+#define CK_FLEXGEN_57 81
+#define CK_FLEXGEN_58 82
+#define CK_FLEXGEN_59 83
+#define CK_FLEXGEN_60 84
+#define CK_FLEXGEN_61 85
+#define CK_FLEXGEN_62 86
+#define CK_FLEXGEN_63 87
+
+/* LOW SPEED MCU CLOCK */
+#define CK_ICN_LS_MCU 88
+
+#define CK_BUS_STM500 89
+#define CK_BUS_FMC 90
+#define CK_BUS_GPU 91
+#define CK_BUS_ETH1 92
+#define CK_BUS_ETH2 93
+#define CK_BUS_PCIE 94
+#define CK_BUS_DDRPHYC 95
+#define CK_BUS_SYSCPU1 96
+#define CK_BUS_ETHSW 97
+#define CK_BUS_HPDMA1 98
+#define CK_BUS_HPDMA2 99
+#define CK_BUS_HPDMA3 100
+#define CK_BUS_ADC12 101
+#define CK_BUS_ADC3 102
+#define CK_BUS_IPCC1 103
+#define CK_BUS_CCI 104
+#define CK_BUS_CRC 105
+#define CK_BUS_MDF1 106
+#define CK_BUS_OSPIIOM 107
+#define CK_BUS_BKPSRAM 108
+#define CK_BUS_HASH 109
+#define CK_BUS_RNG 110
+#define CK_BUS_CRYP1 111
+#define CK_BUS_CRYP2 112
+#define CK_BUS_SAES 113
+#define CK_BUS_PKA 114
+#define CK_BUS_GPIOA 115
+#define CK_BUS_GPIOB 116
+#define CK_BUS_GPIOC 117
+#define CK_BUS_GPIOD 118
+#define CK_BUS_GPIOE 119
+#define CK_BUS_GPIOF 120
+#define CK_BUS_GPIOG 121
+#define CK_BUS_GPIOH 122
+#define CK_BUS_GPIOI 123
+#define CK_BUS_GPIOJ 124
+#define CK_BUS_GPIOK 125
+#define CK_BUS_LPSRAM1 126
+#define CK_BUS_LPSRAM2 127
+#define CK_BUS_LPSRAM3 128
+#define CK_BUS_GPIOZ 129
+#define CK_BUS_LPDMA 130
+#define CK_BUS_HSEM 131
+#define CK_BUS_IPCC2 132
+#define CK_BUS_RTC 133
+#define CK_BUS_SPI8 134
+#define CK_BUS_LPUART1 135
+#define CK_BUS_I2C8 136
+#define CK_BUS_LPTIM3 137
+#define CK_BUS_LPTIM4 138
+#define CK_BUS_LPTIM5 139
+#define CK_BUS_IWDG5 140
+#define CK_BUS_WWDG2 141
+#define CK_BUS_I3C4 142
+#define CK_BUS_TIM2 143
+#define CK_BUS_TIM3 144
+#define CK_BUS_TIM4 145
+#define CK_BUS_TIM5 146
+#define CK_BUS_TIM6 147
+#define CK_BUS_TIM7 148
+#define CK_BUS_TIM10 149
+#define CK_BUS_TIM11 150
+#define CK_BUS_TIM12 151
+#define CK_BUS_TIM13 152
+#define CK_BUS_TIM14 153
+#define CK_BUS_LPTIM1 154
+#define CK_BUS_LPTIM2 155
+#define CK_BUS_SPI2 156
+#define CK_BUS_SPI3 157
+#define CK_BUS_SPDIFRX 158
+#define CK_BUS_USART2 159
+#define CK_BUS_USART3 160
+#define CK_BUS_UART4 161
+#define CK_BUS_UART5 162
+#define CK_BUS_I2C1 163
+#define CK_BUS_I2C2 164
+#define CK_BUS_I2C3 165
+#define CK_BUS_I2C4 166
+#define CK_BUS_I2C5 167
+#define CK_BUS_I2C6 168
+#define CK_BUS_I2C7 169
+#define CK_BUS_I3C1 170
+#define CK_BUS_I3C2 171
+#define CK_BUS_I3C3 172
+#define CK_BUS_TIM1 173
+#define CK_BUS_TIM8 174
+#define CK_BUS_TIM15 175
+#define CK_BUS_TIM16 176
+#define CK_BUS_TIM17 177
+#define CK_BUS_TIM20 178
+#define CK_BUS_SAI1 179
+#define CK_BUS_SAI2 180
+#define CK_BUS_SAI3 181
+#define CK_BUS_SAI4 182
+#define CK_BUS_USART1 183
+#define CK_BUS_USART6 184
+#define CK_BUS_UART7 185
+#define CK_BUS_UART8 186
+#define CK_BUS_UART9 187
+#define CK_BUS_FDCAN 188
+#define CK_BUS_SPI1 189
+#define CK_BUS_SPI4 190
+#define CK_BUS_SPI5 191
+#define CK_BUS_SPI6 192
+#define CK_BUS_SPI7 193
+#define CK_BUS_BSEC 194
+#define CK_BUS_IWDG1 195
+#define CK_BUS_IWDG2 196
+#define CK_BUS_IWDG3 197
+#define CK_BUS_IWDG4 198
+#define CK_BUS_WWDG1 199
+#define CK_BUS_VREF 200
+#define CK_BUS_DTS 201
+#define CK_BUS_SERC 202
+#define CK_BUS_HDP 203
+#define CK_BUS_IS2M 204
+#define CK_BUS_DSI 205
+#define CK_BUS_LTDC 206
+#define CK_BUS_CSI 207
+#define CK_BUS_DCMIPP 208
+#define CK_BUS_DDRC 209
+#define CK_BUS_DDRCFG 210
+#define CK_BUS_GICV2M 211
+#define CK_BUS_USBTC 212
+#define CK_BUS_USB3PCIEPHY 214
+#define CK_BUS_STGEN 215
+#define CK_BUS_VDEC 216
+#define CK_BUS_VENC 217
+#define CK_SYSDBG 218
+#define CK_KER_TIM2 219
+#define CK_KER_TIM3 220
+#define CK_KER_TIM4 221
+#define CK_KER_TIM5 222
+#define CK_KER_TIM6 223
+#define CK_KER_TIM7 224
+#define CK_KER_TIM10 225
+#define CK_KER_TIM11 226
+#define CK_KER_TIM12 227
+#define CK_KER_TIM13 228
+#define CK_KER_TIM14 229
+#define CK_KER_TIM1 230
+#define CK_KER_TIM8 231
+#define CK_KER_TIM15 232
+#define CK_KER_TIM16 233
+#define CK_KER_TIM17 234
+#define CK_KER_TIM20 235
+#define CK_BUS_SYSRAM 236
+#define CK_BUS_VDERAM 237
+#define CK_BUS_RETRAM 238
+#define CK_BUS_OSPI1 239
+#define CK_BUS_OSPI2 240
+#define CK_BUS_OTFD1 241
+#define CK_BUS_OTFD2 242
+#define CK_BUS_SRAM1 243
+#define CK_BUS_SRAM2 244
+#define CK_BUS_SDMMC1 245
+#define CK_BUS_SDMMC2 246
+#define CK_BUS_SDMMC3 247
+#define CK_BUS_DDR 248
+#define CK_BUS_RISAF4 249
+#define CK_BUS_USB2OHCI 250
+#define CK_BUS_USB2EHCI 251
+#define CK_BUS_USB3DR 252
+#define CK_KER_LPTIM1 253
+#define CK_KER_LPTIM2 254
+#define CK_KER_USART2 255
+#define CK_KER_UART4 256
+#define CK_KER_USART3 257
+#define CK_KER_UART5 258
+#define CK_KER_SPI2 259
+#define CK_KER_SPI3 260
+#define CK_KER_SPDIFRX 261
+#define CK_KER_I2C1 262
+#define CK_KER_I2C2 263
+#define CK_KER_I3C1 264
+#define CK_KER_I3C2 265
+#define CK_KER_I2C3 266
+#define CK_KER_I2C5 267
+#define CK_KER_I3C3 268
+#define CK_KER_I2C4 269
+#define CK_KER_I2C6 270
+#define CK_KER_I2C7 271
+#define CK_KER_SPI1 272
+#define CK_KER_SPI4 273
+#define CK_KER_SPI5 274
+#define CK_KER_SPI6 275
+#define CK_KER_SPI7 276
+#define CK_KER_USART1 277
+#define CK_KER_USART6 278
+#define CK_KER_UART7 279
+#define CK_KER_UART8 280
+#define CK_KER_UART9 281
+#define CK_KER_MDF1 282
+#define CK_KER_SAI1 283
+#define CK_KER_SAI2 284
+#define CK_KER_SAI3 285
+#define CK_KER_SAI4 286
+#define CK_KER_FDCAN 287
+#define CK_KER_DSIBLANE 288
+#define CK_KER_DSIPHY 289
+#define CK_KER_CSI 290
+#define CK_KER_CSITXESC 291
+#define CK_KER_CSIPHY 292
+#define CK_KER_LVDSPHY 293
+#define CK_KER_STGEN 294
+#define CK_KER_USB3PCIEPHY 295
+#define CK_KER_USB2PHY2EN 296
+#define CK_KER_I3C4 297
+#define CK_KER_SPI8 298
+#define CK_KER_I2C8 299
+#define CK_KER_LPUART1 300
+#define CK_KER_LPTIM3 301
+#define CK_KER_LPTIM4 302
+#define CK_KER_LPTIM5 303
+#define CK_KER_TSDBG 304
+#define CK_KER_TPIU 305
+#define CK_BUS_ETR 306
+#define CK_BUS_SYSATB 307
+#define CK_KER_ADC12 308
+#define CK_KER_ADC3 309
+#define CK_KER_OSPI1 310
+#define CK_KER_OSPI2 311
+#define CK_KER_FMC 312
+#define CK_KER_SDMMC1 313
+#define CK_KER_SDMMC2 314
+#define CK_KER_SDMMC3 315
+#define CK_KER_ETH1 316
+#define CK_KER_ETH2 317
+#define CK_KER_ETH1PTP 318
+#define CK_KER_ETH2PTP 319
+#define CK_KER_USB2PHY1 320
+#define CK_KER_USB2PHY2 321
+#define CK_KER_ETHSW 322
+#define CK_KER_ETHSWREF 323
+#define CK_MCO1 324
+#define CK_MCO2 325
+#define CK_KER_DTS 326
+#define CK_ETH1_RX 327
+#define CK_ETH1_TX 328
+#define CK_ETH1_MAC 329
+#define CK_ETH2_RX 330
+#define CK_ETH2_TX 331
+#define CK_ETH2_MAC 332
+#define CK_ETH1_STP 333
+#define CK_ETH2_STP 334
+#define CK_KER_USBTC 335
+#define CK_BUS_ADF1 336
+#define CK_KER_ADF1 337
+#define CK_BUS_LVDS 338
+#define CK_KER_LTDC 339
+#define CK_KER_GPU 340
+#define CK_BUS_ETHSWACMCFG 341
+#define CK_BUS_ETHSWACMMSG 342
+#define HSE_DIV2_CK 343
+
+#define STM32MP25_LAST_CLK 344
+
+#define CK_SCMI_ICN_HS_MCU 0
+#define CK_SCMI_ICN_SDMMC 1
+#define CK_SCMI_ICN_DDR 2
+#define CK_SCMI_ICN_DISPLAY 3
+#define CK_SCMI_ICN_HSL 4
+#define CK_SCMI_ICN_NIC 5
+#define CK_SCMI_ICN_VID 6
+#define CK_SCMI_FLEXGEN_07 7
+#define CK_SCMI_FLEXGEN_08 8
+#define CK_SCMI_FLEXGEN_09 9
+#define CK_SCMI_FLEXGEN_10 10
+#define CK_SCMI_FLEXGEN_11 11
+#define CK_SCMI_FLEXGEN_12 12
+#define CK_SCMI_FLEXGEN_13 13
+#define CK_SCMI_FLEXGEN_14 14
+#define CK_SCMI_FLEXGEN_15 15
+#define CK_SCMI_FLEXGEN_16 16
+#define CK_SCMI_FLEXGEN_17 17
+#define CK_SCMI_FLEXGEN_18 18
+#define CK_SCMI_FLEXGEN_19 19
+#define CK_SCMI_FLEXGEN_20 20
+#define CK_SCMI_FLEXGEN_21 21
+#define CK_SCMI_FLEXGEN_22 22
+#define CK_SCMI_FLEXGEN_23 23
+#define CK_SCMI_FLEXGEN_24 24
+#define CK_SCMI_FLEXGEN_25 25
+#define CK_SCMI_FLEXGEN_26 26
+#define CK_SCMI_FLEXGEN_27 27
+#define CK_SCMI_FLEXGEN_28 28
+#define CK_SCMI_FLEXGEN_29 29
+#define CK_SCMI_FLEXGEN_30 30
+#define CK_SCMI_FLEXGEN_31 31
+#define CK_SCMI_FLEXGEN_32 32
+#define CK_SCMI_FLEXGEN_33 33
+#define CK_SCMI_FLEXGEN_34 34
+#define CK_SCMI_FLEXGEN_35 35
+#define CK_SCMI_FLEXGEN_36 36
+#define CK_SCMI_FLEXGEN_37 37
+#define CK_SCMI_FLEXGEN_38 38
+#define CK_SCMI_FLEXGEN_39 39
+#define CK_SCMI_FLEXGEN_40 40
+#define CK_SCMI_FLEXGEN_41 41
+#define CK_SCMI_FLEXGEN_42 42
+#define CK_SCMI_FLEXGEN_43 43
+#define CK_SCMI_FLEXGEN_44 44
+#define CK_SCMI_FLEXGEN_45 45
+#define CK_SCMI_FLEXGEN_46 46
+#define CK_SCMI_FLEXGEN_47 47
+#define CK_SCMI_FLEXGEN_48 48
+#define CK_SCMI_FLEXGEN_49 49
+#define CK_SCMI_FLEXGEN_50 50
+#define CK_SCMI_FLEXGEN_51 51
+#define CK_SCMI_FLEXGEN_52 52
+#define CK_SCMI_FLEXGEN_53 53
+#define CK_SCMI_FLEXGEN_54 54
+#define CK_SCMI_FLEXGEN_55 55
+#define CK_SCMI_FLEXGEN_56 56
+#define CK_SCMI_FLEXGEN_57 57
+#define CK_SCMI_FLEXGEN_58 58
+#define CK_SCMI_FLEXGEN_59 59
+#define CK_SCMI_FLEXGEN_60 60
+#define CK_SCMI_FLEXGEN_61 61
+#define CK_SCMI_FLEXGEN_62 62
+#define CK_SCMI_FLEXGEN_63 63
+#define CK_SCMI_ICN_LS_MCU 64
+#define CK_SCMI_HSE 65
+#define CK_SCMI_LSE 66
+#define CK_SCMI_HSI 67
+#define CK_SCMI_LSI 68
+#define CK_SCMI_MSI 69
+#define CK_SCMI_HSE_DIV2 70
+#define CK_SCMI_CPU1 71
+#define CK_SCMI_SYSCPU1 72
+#define CK_SCMI_PLL2 73
+#define CK_SCMI_PLL3 74
+#define CK_SCMI_RTC 75
+#define CK_SCMI_RTCCK 76
+#define CK_SCMI_ICN_APB1 77
+#define CK_SCMI_ICN_APB2 78
+#define CK_SCMI_ICN_APB3 79
+#define CK_SCMI_ICN_APB4 80
+#define CK_SCMI_ICN_APBDBG 81
+#define CK_SCMI_TIMG1 82
+#define CK_SCMI_TIMG2 83
+#define CK_SCMI_BKPSRAM 84
+#define CK_SCMI_BSEC 85
+#define CK_SCMI_ETR 87
+#define CK_SCMI_FMC 88
+#define CK_SCMI_GPIOA 89
+#define CK_SCMI_GPIOB 90
+#define CK_SCMI_GPIOC 91
+#define CK_SCMI_GPIOD 92
+#define CK_SCMI_GPIOE 93
+#define CK_SCMI_GPIOF 94
+#define CK_SCMI_GPIOG 95
+#define CK_SCMI_GPIOH 96
+#define CK_SCMI_GPIOI 97
+#define CK_SCMI_GPIOJ 98
+#define CK_SCMI_GPIOK 99
+#define CK_SCMI_GPIOZ 100
+#define CK_SCMI_HPDMA1 101
+#define CK_SCMI_HPDMA2 102
+#define CK_SCMI_HPDMA3 103
+#define CK_SCMI_HSEM 104
+#define CK_SCMI_IPCC1 105
+#define CK_SCMI_IPCC2 106
+#define CK_SCMI_LPDMA 107
+#define CK_SCMI_RETRAM 108
+#define CK_SCMI_SRAM1 109
+#define CK_SCMI_SRAM2 110
+#define CK_SCMI_LPSRAM1 111
+#define CK_SCMI_LPSRAM2 112
+#define CK_SCMI_LPSRAM3 113
+#define CK_SCMI_VDERAM 114
+#define CK_SCMI_SYSRAM 115
+#define CK_SCMI_OSPI1 116
+#define CK_SCMI_OSPI2 117
+#define CK_SCMI_TPIU 118
+#define CK_SCMI_SYSDBG 119
+#define CK_SCMI_SYSATB 120
+#define CK_SCMI_TSDBG 121
+#define CK_SCMI_STM500 122
+
+#endif /* _DT_BINDINGS_STM32MP25_CLKS_H_ */
diff --git a/dts/upstream/include/dt-bindings/dma/fsl-edma.h b/dts/upstream/include/dt-bindings/dma/fsl-edma.h
new file mode 100644
index 0000000..fd11478
--- /dev/null
+++ b/dts/upstream/include/dt-bindings/dma/fsl-edma.h
@@ -0,0 +1,21 @@
+/* SPDX-License-Identifier: GPL-2.0 OR BSD-2-Clause */
+
+#ifndef _FSL_EDMA_DT_BINDING_H_
+#define _FSL_EDMA_DT_BINDING_H_
+
+/* Receive Channel */
+#define FSL_EDMA_RX 0x1
+
+/* iMX8 audio remote DMA */
+#define FSL_EDMA_REMOTE 0x2
+
+/* FIFO is continue memory region */
+#define FSL_EDMA_MULTI_FIFO 0x4
+
+/* Channel need stick to even channel */
+#define FSL_EDMA_EVEN_CH 0x8
+
+/* Channel need stick to odd channel */
+#define FSL_EDMA_ODD_CH 0x10
+
+#endif
diff --git a/dts/upstream/include/dt-bindings/iio/qcom,spmi-adc7-pm7325.h b/dts/upstream/include/dt-bindings/iio/qcom,spmi-adc7-pm7325.h
new file mode 100644
index 0000000..9690801
--- /dev/null
+++ b/dts/upstream/include/dt-bindings/iio/qcom,spmi-adc7-pm7325.h
@@ -0,0 +1,69 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+/*
+ * Copyright (c) 2020 The Linux Foundation. All rights reserved.
+ */
+
+#ifndef _DT_BINDINGS_QCOM_SPMI_VADC_PM7325_H
+#define _DT_BINDINGS_QCOM_SPMI_VADC_PM7325_H
+
+#ifndef PM7325_SID
+#define PM7325_SID 1
+#endif
+
+#include <dt-bindings/iio/qcom,spmi-vadc.h>
+
+/* ADC channels for PM7325_ADC for PMIC7 */
+#define PM7325_ADC7_REF_GND (PM7325_SID << 8 | ADC7_REF_GND)
+#define PM7325_ADC7_1P25VREF (PM7325_SID << 8 | ADC7_1P25VREF)
+#define PM7325_ADC7_VREF_VADC (PM7325_SID << 8 | ADC7_VREF_VADC)
+#define PM7325_ADC7_DIE_TEMP (PM7325_SID << 8 | ADC7_DIE_TEMP)
+
+#define PM7325_ADC7_AMUX_THM1 (PM7325_SID << 8 | ADC7_AMUX_THM1)
+#define PM7325_ADC7_AMUX_THM2 (PM7325_SID << 8 | ADC7_AMUX_THM2)
+#define PM7325_ADC7_AMUX_THM3 (PM7325_SID << 8 | ADC7_AMUX_THM3)
+#define PM7325_ADC7_AMUX_THM4 (PM7325_SID << 8 | ADC7_AMUX_THM4)
+#define PM7325_ADC7_AMUX_THM5 (PM7325_SID << 8 | ADC7_AMUX_THM5)
+#define PM7325_ADC7_GPIO1 (PM7325_SID << 8 | ADC7_GPIO1)
+#define PM7325_ADC7_GPIO2 (PM7325_SID << 8 | ADC7_GPIO2)
+#define PM7325_ADC7_GPIO3 (PM7325_SID << 8 | ADC7_GPIO3)
+#define PM7325_ADC7_GPIO4 (PM7325_SID << 8 | ADC7_GPIO4)
+
+/* 30k pull-up1 */
+#define PM7325_ADC7_AMUX_THM1_30K_PU (PM7325_SID << 8 | ADC7_AMUX_THM1_30K_PU)
+#define PM7325_ADC7_AMUX_THM2_30K_PU (PM7325_SID << 8 | ADC7_AMUX_THM2_30K_PU)
+#define PM7325_ADC7_AMUX_THM3_30K_PU (PM7325_SID << 8 | ADC7_AMUX_THM3_30K_PU)
+#define PM7325_ADC7_AMUX_THM4_30K_PU (PM7325_SID << 8 | ADC7_AMUX_THM4_30K_PU)
+#define PM7325_ADC7_AMUX_THM5_30K_PU (PM7325_SID << 8 | ADC7_AMUX_THM5_30K_PU)
+#define PM7325_ADC7_GPIO1_30K_PU (PM7325_SID << 8 | ADC7_GPIO1_30K_PU)
+#define PM7325_ADC7_GPIO2_30K_PU (PM7325_SID << 8 | ADC7_GPIO2_30K_PU)
+#define PM7325_ADC7_GPIO3_30K_PU (PM7325_SID << 8 | ADC7_GPIO3_30K_PU)
+#define PM7325_ADC7_GPIO4_30K_PU (PM7325_SID << 8 | ADC7_GPIO4_30K_PU)
+
+/* 100k pull-up2 */
+#define PM7325_ADC7_AMUX_THM1_100K_PU (PM7325_SID << 8 | ADC7_AMUX_THM1_100K_PU)
+#define PM7325_ADC7_AMUX_THM2_100K_PU (PM7325_SID << 8 | ADC7_AMUX_THM2_100K_PU)
+#define PM7325_ADC7_AMUX_THM3_100K_PU (PM7325_SID << 8 | ADC7_AMUX_THM3_100K_PU)
+#define PM7325_ADC7_AMUX_THM4_100K_PU (PM7325_SID << 8 | ADC7_AMUX_THM4_100K_PU)
+#define PM7325_ADC7_AMUX_THM5_100K_PU (PM7325_SID << 8 | ADC7_AMUX_THM5_100K_PU)
+#define PM7325_ADC7_GPIO1_100K_PU (PM7325_SID << 8 | ADC7_GPIO1_100K_PU)
+#define PM7325_ADC7_GPIO2_100K_PU (PM7325_SID << 8 | ADC7_GPIO2_100K_PU)
+#define PM7325_ADC7_GPIO3_100K_PU (PM7325_SID << 8 | ADC7_GPIO3_100K_PU)
+#define PM7325_ADC7_GPIO4_100K_PU (PM7325_SID << 8 | ADC7_GPIO4_100K_PU)
+
+/* 400k pull-up3 */
+#define PM7325_ADC7_AMUX_THM1_400K_PU (PM7325_SID << 8 | ADC7_AMUX_THM1_400K_PU)
+#define PM7325_ADC7_AMUX_THM2_400K_PU (PM7325_SID << 8 | ADC7_AMUX_THM2_400K_PU)
+#define PM7325_ADC7_AMUX_THM3_400K_PU (PM7325_SID << 8 | ADC7_AMUX_THM3_400K_PU)
+#define PM7325_ADC7_AMUX_THM4_400K_PU (PM7325_SID << 8 | ADC7_AMUX_THM4_400K_PU)
+#define PM7325_ADC7_AMUX_THM5_400K_PU (PM7325_SID << 8 | ADC7_AMUX_THM5_400K_PU)
+#define PM7325_ADC7_GPIO1_400K_PU (PM7325_SID << 8 | ADC7_GPIO1_400K_PU)
+#define PM7325_ADC7_GPIO2_400K_PU (PM7325_SID << 8 | ADC7_GPIO2_400K_PU)
+#define PM7325_ADC7_GPIO3_400K_PU (PM7325_SID << 8 | ADC7_GPIO3_400K_PU)
+#define PM7325_ADC7_GPIO4_400K_PU (PM7325_SID << 8 | ADC7_GPIO4_400K_PU)
+
+/* 1/3 Divider */
+#define PM7325_ADC7_GPIO4_DIV3 (PM7325_SID << 8 | ADC7_GPIO4_DIV3)
+
+#define PM7325_ADC7_VPH_PWR (PM7325_SID << 8 | ADC7_VPH_PWR)
+
+#endif /* _DT_BINDINGS_QCOM_SPMI_VADC_PM7325_H */
diff --git a/dts/upstream/include/dt-bindings/iio/qcom,spmi-adc7-smb139x.h b/dts/upstream/include/dt-bindings/iio/qcom,spmi-adc7-smb139x.h
new file mode 100644
index 0000000..c0680d1
--- /dev/null
+++ b/dts/upstream/include/dt-bindings/iio/qcom,spmi-adc7-smb139x.h
@@ -0,0 +1,19 @@
+/* SPDX-License-Identifier: GPL-2.0-only OR BSD-3-Clause */
+/*
+ * Copyright (c) 2020 The Linux Foundation. All rights reserved.
+ */
+
+#ifndef _DT_BINDINGS_QCOM_SPMI_VADC_SMB139X_H
+#define _DT_BINDINGS_QCOM_SPMI_VADC_SMB139X_H
+
+#include <dt-bindings/iio/qcom,spmi-vadc.h>
+
+#define SMB139x_1_ADC7_SMB_TEMP (SMB139x_1_SID << 8 | ADC7_SMB_TEMP)
+#define SMB139x_1_ADC7_ICHG_SMB (SMB139x_1_SID << 8 | ADC7_ICHG_SMB)
+#define SMB139x_1_ADC7_IIN_SMB (SMB139x_1_SID << 8 | ADC7_IIN_SMB)
+
+#define SMB139x_2_ADC7_SMB_TEMP (SMB139x_2_SID << 8 | ADC7_SMB_TEMP)
+#define SMB139x_2_ADC7_ICHG_SMB (SMB139x_2_SID << 8 | ADC7_ICHG_SMB)
+#define SMB139x_2_ADC7_IIN_SMB (SMB139x_2_SID << 8 | ADC7_IIN_SMB)
+
+#endif
diff --git a/dts/upstream/include/dt-bindings/iio/qcom,spmi-vadc.h b/dts/upstream/include/dt-bindings/iio/qcom,spmi-vadc.h
index 08adfe2..ef07ecd 100644
--- a/dts/upstream/include/dt-bindings/iio/qcom,spmi-vadc.h
+++ b/dts/upstream/include/dt-bindings/iio/qcom,spmi-vadc.h
@@ -239,12 +239,15 @@
#define ADC7_GPIO3 0x0c
#define ADC7_GPIO4 0x0d
+#define ADC7_SMB_TEMP 0x06
#define ADC7_CHG_TEMP 0x10
#define ADC7_USB_IN_V_16 0x11
#define ADC7_VDC_16 0x12
#define ADC7_CC1_ID 0x13
#define ADC7_VREF_BAT_THERM 0x15
#define ADC7_IIN_FB 0x17
+#define ADC7_ICHG_SMB 0x18
+#define ADC7_IIN_SMB 0x19
/* 30k pull-up1 */
#define ADC7_AMUX_THM1_30K_PU 0x24
diff --git a/dts/upstream/include/dt-bindings/interconnect/qcom,sm6115.h b/dts/upstream/include/dt-bindings/interconnect/qcom,sm6115.h
new file mode 100644
index 0000000..21090e5
--- /dev/null
+++ b/dts/upstream/include/dt-bindings/interconnect/qcom,sm6115.h
@@ -0,0 +1,111 @@
+/* SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause */
+/*
+ * Copyright (c) 2020, The Linux Foundation. All rights reserved.
+ * Copyright (c) 2023, Linaro Limited
+ */
+
+#ifndef __DT_BINDINGS_INTERCONNECT_QCOM_SM6115_H
+#define __DT_BINDINGS_INTERCONNECT_QCOM_SM6115_H
+
+/* BIMC */
+#define MASTER_AMPSS_M0 0
+#define MASTER_SNOC_BIMC_RT 1
+#define MASTER_SNOC_BIMC_NRT 2
+#define SNOC_BIMC_MAS 3
+#define MASTER_GRAPHICS_3D 4
+#define MASTER_TCU_0 5
+#define SLAVE_EBI_CH0 6
+#define BIMC_SNOC_SLV 7
+
+/* CNOC */
+#define SNOC_CNOC_MAS 0
+#define MASTER_QDSS_DAP 1
+#define SLAVE_AHB2PHY_USB 2
+#define SLAVE_APSS_THROTTLE_CFG 3
+#define SLAVE_BIMC_CFG 4
+#define SLAVE_BOOT_ROM 5
+#define SLAVE_CAMERA_NRT_THROTTLE_CFG 6
+#define SLAVE_CAMERA_RT_THROTTLE_CFG 7
+#define SLAVE_CAMERA_CFG 8
+#define SLAVE_CLK_CTL 9
+#define SLAVE_RBCPR_CX_CFG 10
+#define SLAVE_RBCPR_MX_CFG 11
+#define SLAVE_CRYPTO_0_CFG 12
+#define SLAVE_DCC_CFG 13
+#define SLAVE_DDR_PHY_CFG 14
+#define SLAVE_DDR_SS_CFG 15
+#define SLAVE_DISPLAY_CFG 16
+#define SLAVE_DISPLAY_THROTTLE_CFG 17
+#define SLAVE_GPU_CFG 18
+#define SLAVE_GPU_THROTTLE_CFG 19
+#define SLAVE_HWKM_CORE 20
+#define SLAVE_IMEM_CFG 21
+#define SLAVE_IPA_CFG 22
+#define SLAVE_LPASS 23
+#define SLAVE_MAPSS 24
+#define SLAVE_MDSP_MPU_CFG 25
+#define SLAVE_MESSAGE_RAM 26
+#define SLAVE_CNOC_MSS 27
+#define SLAVE_PDM 28
+#define SLAVE_PIMEM_CFG 29
+#define SLAVE_PKA_CORE 30
+#define SLAVE_PMIC_ARB 31
+#define SLAVE_QDSS_CFG 32
+#define SLAVE_QM_CFG 33
+#define SLAVE_QM_MPU_CFG 34
+#define SLAVE_QPIC 35
+#define SLAVE_QUP_0 36
+#define SLAVE_RPM 37
+#define SLAVE_SDCC_1 38
+#define SLAVE_SDCC_2 39
+#define SLAVE_SECURITY 40
+#define SLAVE_SNOC_CFG 41
+#define SLAVE_TCSR 42
+#define SLAVE_TLMM 43
+#define SLAVE_USB3 44
+#define SLAVE_VENUS_CFG 45
+#define SLAVE_VENUS_THROTTLE_CFG 46
+#define SLAVE_VSENSE_CTRL_CFG 47
+#define SLAVE_SERVICE_CNOC 48
+
+/* SNOC */
+#define MASTER_CRYPTO_CORE0 0
+#define MASTER_SNOC_CFG 1
+#define MASTER_TIC 2
+#define MASTER_ANOC_SNOC 3
+#define BIMC_SNOC_MAS 4
+#define MASTER_PIMEM 5
+#define MASTER_QDSS_BAM 6
+#define MASTER_QPIC 7
+#define MASTER_QUP_0 8
+#define MASTER_IPA 9
+#define MASTER_QDSS_ETR 10
+#define MASTER_SDCC_1 11
+#define MASTER_SDCC_2 12
+#define MASTER_USB3 13
+#define SLAVE_APPSS 14
+#define SNOC_CNOC_SLV 15
+#define SLAVE_OCIMEM 16
+#define SLAVE_PIMEM 17
+#define SNOC_BIMC_SLV 18
+#define SLAVE_SERVICE_SNOC 19
+#define SLAVE_QDSS_STM 20
+#define SLAVE_TCU 21
+#define SLAVE_ANOC_SNOC 22
+
+/* CLK Virtual */
+#define MASTER_QUP_CORE_0 0
+#define SLAVE_QUP_CORE_0 1
+
+/* MMRT Virtual */
+#define MASTER_CAMNOC_HF 0
+#define MASTER_MDP_PORT0 1
+#define SLAVE_SNOC_BIMC_RT 2
+
+/* MMNRT Virtual */
+#define MASTER_CAMNOC_SF 0
+#define MASTER_VIDEO_P0 1
+#define MASTER_VIDEO_PROC 2
+#define SLAVE_SNOC_BIMC_NRT 3
+
+#endif
diff --git a/dts/upstream/include/dt-bindings/interconnect/qcom,sm8650-rpmh.h b/dts/upstream/include/dt-bindings/interconnect/qcom,sm8650-rpmh.h
new file mode 100644
index 0000000..6c1eaf0
--- /dev/null
+++ b/dts/upstream/include/dt-bindings/interconnect/qcom,sm8650-rpmh.h
@@ -0,0 +1,154 @@
+/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */
+/*
+ * Copyright (c) 2021, The Linux Foundation. All rights reserved.
+ * Copyright (c) 2023, Linaro Limited
+ */
+
+#ifndef __DT_BINDINGS_INTERCONNECT_QCOM_SM8650_H
+#define __DT_BINDINGS_INTERCONNECT_QCOM_SM8650_H
+
+#define MASTER_QSPI_0 0
+#define MASTER_QUP_1 1
+#define MASTER_QUP_3 2
+#define MASTER_SDCC_4 3
+#define MASTER_UFS_MEM 4
+#define MASTER_USB3_0 5
+#define SLAVE_A1NOC_SNOC 6
+
+#define MASTER_QDSS_BAM 0
+#define MASTER_QUP_2 1
+#define MASTER_CRYPTO 2
+#define MASTER_IPA 3
+#define MASTER_SP 4
+#define MASTER_QDSS_ETR 5
+#define MASTER_QDSS_ETR_1 6
+#define MASTER_SDCC_2 7
+#define SLAVE_A2NOC_SNOC 8
+
+#define MASTER_QUP_CORE_0 0
+#define MASTER_QUP_CORE_1 1
+#define MASTER_QUP_CORE_2 2
+#define SLAVE_QUP_CORE_0 3
+#define SLAVE_QUP_CORE_1 4
+#define SLAVE_QUP_CORE_2 5
+
+#define MASTER_CNOC_CFG 0
+#define SLAVE_AHB2PHY_SOUTH 1
+#define SLAVE_AHB2PHY_NORTH 2
+#define SLAVE_CAMERA_CFG 3
+#define SLAVE_CLK_CTL 4
+#define SLAVE_RBCPR_CX_CFG 5
+#define SLAVE_CPR_HMX 6
+#define SLAVE_RBCPR_MMCX_CFG 7
+#define SLAVE_RBCPR_MXA_CFG 8
+#define SLAVE_RBCPR_MXC_CFG 9
+#define SLAVE_CPR_NSPCX 10
+#define SLAVE_CRYPTO_0_CFG 11
+#define SLAVE_CX_RDPM 12
+#define SLAVE_DISPLAY_CFG 13
+#define SLAVE_GFX3D_CFG 14
+#define SLAVE_I2C 15
+#define SLAVE_I3C_IBI0_CFG 16
+#define SLAVE_I3C_IBI1_CFG 17
+#define SLAVE_IMEM_CFG 18
+#define SLAVE_CNOC_MSS 19
+#define SLAVE_MX_2_RDPM 20
+#define SLAVE_MX_RDPM 21
+#define SLAVE_PCIE_0_CFG 22
+#define SLAVE_PCIE_1_CFG 23
+#define SLAVE_PCIE_RSCC 24
+#define SLAVE_PDM 25
+#define SLAVE_PRNG 26
+#define SLAVE_QDSS_CFG 27
+#define SLAVE_QSPI_0 28
+#define SLAVE_QUP_3 29
+#define SLAVE_QUP_1 30
+#define SLAVE_QUP_2 31
+#define SLAVE_SDCC_2 32
+#define SLAVE_SDCC_4 33
+#define SLAVE_SPSS_CFG 34
+#define SLAVE_TCSR 35
+#define SLAVE_TLMM 36
+#define SLAVE_UFS_MEM_CFG 37
+#define SLAVE_USB3_0 38
+#define SLAVE_VENUS_CFG 39
+#define SLAVE_VSENSE_CTRL_CFG 40
+#define SLAVE_CNOC_MNOC_CFG 41
+#define SLAVE_NSP_QTB_CFG 42
+#define SLAVE_PCIE_ANOC_CFG 43
+#define SLAVE_SERVICE_CNOC_CFG 44
+#define SLAVE_QDSS_STM 45
+#define SLAVE_TCU 46
+
+#define MASTER_GEM_NOC_CNOC 0
+#define MASTER_GEM_NOC_PCIE_SNOC 1
+#define SLAVE_AOSS 2
+#define SLAVE_IPA_CFG 3
+#define SLAVE_IPC_ROUTER_CFG 4
+#define SLAVE_TME_CFG 5
+#define SLAVE_APPSS 6
+#define SLAVE_CNOC_CFG 7
+#define SLAVE_DDRSS_CFG 8
+#define SLAVE_IMEM 9
+#define SLAVE_SERVICE_CNOC 10
+#define SLAVE_PCIE_0 11
+#define SLAVE_PCIE_1 12
+
+#define MASTER_GPU_TCU 0
+#define MASTER_SYS_TCU 1
+#define MASTER_UBWC_P_TCU 2
+#define MASTER_APPSS_PROC 3
+#define MASTER_GFX3D 4
+#define MASTER_LPASS_GEM_NOC 5
+#define MASTER_MSS_PROC 6
+#define MASTER_MNOC_HF_MEM_NOC 7
+#define MASTER_MNOC_SF_MEM_NOC 8
+#define MASTER_COMPUTE_NOC 9
+#define MASTER_ANOC_PCIE_GEM_NOC 10
+#define MASTER_SNOC_SF_MEM_NOC 11
+#define MASTER_UBWC_P 12
+#define MASTER_GIC 13
+#define SLAVE_GEM_NOC_CNOC 14
+#define SLAVE_LLCC 15
+#define SLAVE_MEM_NOC_PCIE_SNOC 16
+
+#define MASTER_LPIAON_NOC 0
+#define SLAVE_LPASS_GEM_NOC 1
+
+#define MASTER_LPASS_LPINOC 0
+#define SLAVE_LPIAON_NOC_LPASS_AG_NOC 1
+
+#define MASTER_LPASS_PROC 0
+#define SLAVE_LPICX_NOC_LPIAON_NOC 1
+
+#define MASTER_LLCC 0
+#define SLAVE_EBI1 1
+
+#define MASTER_CAMNOC_HF 0
+#define MASTER_CAMNOC_ICP 1
+#define MASTER_CAMNOC_SF 2
+#define MASTER_MDP 3
+#define MASTER_CDSP_HCP 4
+#define MASTER_VIDEO 5
+#define MASTER_VIDEO_CV_PROC 6
+#define MASTER_VIDEO_PROC 7
+#define MASTER_VIDEO_V_PROC 8
+#define MASTER_CNOC_MNOC_CFG 9
+#define SLAVE_MNOC_HF_MEM_NOC 10
+#define SLAVE_MNOC_SF_MEM_NOC 11
+#define SLAVE_SERVICE_MNOC 12
+
+#define MASTER_CDSP_PROC 0
+#define SLAVE_CDSP_MEM_NOC 1
+
+#define MASTER_PCIE_ANOC_CFG 0
+#define MASTER_PCIE_0 1
+#define MASTER_PCIE_1 2
+#define SLAVE_ANOC_PCIE_GEM_NOC 3
+#define SLAVE_SERVICE_PCIE_ANOC 4
+
+#define MASTER_A1NOC_SNOC 0
+#define MASTER_A2NOC_SNOC 1
+#define SLAVE_SNOC_GEM_NOC_SF 2
+
+#endif
diff --git a/dts/upstream/include/dt-bindings/interconnect/qcom,x1e80100-rpmh.h b/dts/upstream/include/dt-bindings/interconnect/qcom,x1e80100-rpmh.h
new file mode 100644
index 0000000..a38c347
--- /dev/null
+++ b/dts/upstream/include/dt-bindings/interconnect/qcom,x1e80100-rpmh.h
@@ -0,0 +1,207 @@
+/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */
+/*
+ * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved.
+ * Copyright (c) 2023, Linaro Limited
+ */
+
+#ifndef __DT_BINDINGS_INTERCONNECT_QCOM_X1E80100_H
+#define __DT_BINDINGS_INTERCONNECT_QCOM_X1E80100_H
+
+#define MASTER_QSPI_0 0
+#define MASTER_QUP_1 1
+#define MASTER_SDCC_4 2
+#define MASTER_UFS_MEM 3
+#define SLAVE_A1NOC_SNOC 4
+
+#define MASTER_QUP_0 0
+#define MASTER_QUP_2 1
+#define MASTER_CRYPTO 2
+#define MASTER_SP 3
+#define MASTER_QDSS_ETR 4
+#define MASTER_QDSS_ETR_1 5
+#define MASTER_SDCC_2 6
+#define SLAVE_A2NOC_SNOC 7
+
+#define MASTER_DDR_PERF_MODE 0
+#define MASTER_QUP_CORE_0 1
+#define MASTER_QUP_CORE_1 2
+#define MASTER_QUP_CORE_2 3
+#define SLAVE_DDR_PERF_MODE 4
+#define SLAVE_QUP_CORE_0 5
+#define SLAVE_QUP_CORE_1 6
+#define SLAVE_QUP_CORE_2 7
+
+#define MASTER_CNOC_CFG 0
+#define SLAVE_AHB2PHY_SOUTH 1
+#define SLAVE_AHB2PHY_NORTH 2
+#define SLAVE_AHB2PHY_2 3
+#define SLAVE_AV1_ENC_CFG 4
+#define SLAVE_CAMERA_CFG 5
+#define SLAVE_CLK_CTL 6
+#define SLAVE_CRYPTO_0_CFG 7
+#define SLAVE_DISPLAY_CFG 8
+#define SLAVE_GFX3D_CFG 9
+#define SLAVE_IMEM_CFG 10
+#define SLAVE_IPC_ROUTER_CFG 11
+#define SLAVE_PCIE_0_CFG 12
+#define SLAVE_PCIE_1_CFG 13
+#define SLAVE_PCIE_2_CFG 14
+#define SLAVE_PCIE_3_CFG 15
+#define SLAVE_PCIE_4_CFG 16
+#define SLAVE_PCIE_5_CFG 17
+#define SLAVE_PCIE_6A_CFG 18
+#define SLAVE_PCIE_6B_CFG 19
+#define SLAVE_PCIE_RSC_CFG 20
+#define SLAVE_PDM 21
+#define SLAVE_PRNG 22
+#define SLAVE_QDSS_CFG 23
+#define SLAVE_QSPI_0 24
+#define SLAVE_QUP_0 25
+#define SLAVE_QUP_1 26
+#define SLAVE_QUP_2 27
+#define SLAVE_SDCC_2 28
+#define SLAVE_SDCC_4 29
+#define SLAVE_SMMUV3_CFG 30
+#define SLAVE_TCSR 31
+#define SLAVE_TLMM 32
+#define SLAVE_UFS_MEM_CFG 33
+#define SLAVE_USB2 34
+#define SLAVE_USB3_0 35
+#define SLAVE_USB3_1 36
+#define SLAVE_USB3_2 37
+#define SLAVE_USB3_MP 38
+#define SLAVE_USB4_0 39
+#define SLAVE_USB4_1 40
+#define SLAVE_USB4_2 41
+#define SLAVE_VENUS_CFG 42
+#define SLAVE_LPASS_QTB_CFG 43
+#define SLAVE_CNOC_MNOC_CFG 44
+#define SLAVE_NSP_QTB_CFG 45
+#define SLAVE_QDSS_STM 46
+#define SLAVE_TCU 47
+
+#define MASTER_GEM_NOC_CNOC 0
+#define MASTER_GEM_NOC_PCIE_SNOC 1
+#define SLAVE_AOSS 2
+#define SLAVE_TME_CFG 3
+#define SLAVE_APPSS 4
+#define SLAVE_CNOC_CFG 5
+#define SLAVE_BOOT_IMEM 6
+#define SLAVE_IMEM 7
+#define SLAVE_PCIE_0 8
+#define SLAVE_PCIE_1 9
+#define SLAVE_PCIE_2 10
+#define SLAVE_PCIE_3 11
+#define SLAVE_PCIE_4 12
+#define SLAVE_PCIE_5 13
+#define SLAVE_PCIE_6A 14
+#define SLAVE_PCIE_6B 15
+
+#define MASTER_GPU_TCU 0
+#define MASTER_PCIE_TCU 1
+#define MASTER_SYS_TCU 2
+#define MASTER_APPSS_PROC 3
+#define MASTER_GFX3D 4
+#define MASTER_LPASS_GEM_NOC 5
+#define MASTER_MNOC_HF_MEM_NOC 6
+#define MASTER_MNOC_SF_MEM_NOC 7
+#define MASTER_COMPUTE_NOC 8
+#define MASTER_ANOC_PCIE_GEM_NOC 9
+#define MASTER_SNOC_SF_MEM_NOC 10
+#define MASTER_GIC2 11
+#define SLAVE_GEM_NOC_CNOC 12
+#define SLAVE_LLCC 13
+#define SLAVE_MEM_NOC_PCIE_SNOC 14
+#define MASTER_MNOC_HF_MEM_NOC_DISP 15
+#define MASTER_ANOC_PCIE_GEM_NOC_DISP 16
+#define SLAVE_LLCC_DISP 17
+#define MASTER_ANOC_PCIE_GEM_NOC_PCIE 18
+#define SLAVE_LLCC_PCIE 19
+
+#define MASTER_LPIAON_NOC 0
+#define SLAVE_LPASS_GEM_NOC 1
+
+#define MASTER_LPASS_LPINOC 0
+#define SLAVE_LPIAON_NOC_LPASS_AG_NOC 1
+
+#define MASTER_LPASS_PROC 0
+#define SLAVE_LPICX_NOC_LPIAON_NOC 1
+
+#define MASTER_LLCC 0
+#define SLAVE_EBI1 1
+#define MASTER_LLCC_DISP 2
+#define SLAVE_EBI1_DISP 3
+#define MASTER_LLCC_PCIE 4
+#define SLAVE_EBI1_PCIE 5
+
+#define MASTER_AV1_ENC 0
+#define MASTER_CAMNOC_HF 1
+#define MASTER_CAMNOC_ICP 2
+#define MASTER_CAMNOC_SF 3
+#define MASTER_EVA 4
+#define MASTER_MDP 5
+#define MASTER_VIDEO 6
+#define MASTER_VIDEO_CV_PROC 7
+#define MASTER_VIDEO_V_PROC 8
+#define MASTER_CNOC_MNOC_CFG 9
+#define SLAVE_MNOC_HF_MEM_NOC 10
+#define SLAVE_MNOC_SF_MEM_NOC 11
+#define SLAVE_SERVICE_MNOC 12
+#define MASTER_MDP_DISP 13
+#define SLAVE_MNOC_HF_MEM_NOC_DISP 14
+
+#define MASTER_CDSP_PROC 0
+#define SLAVE_CDSP_MEM_NOC 1
+
+#define MASTER_PCIE_NORTH 0
+#define MASTER_PCIE_SOUTH 1
+#define SLAVE_ANOC_PCIE_GEM_NOC 2
+#define MASTER_PCIE_NORTH_PCIE 3
+#define MASTER_PCIE_SOUTH_PCIE 4
+#define SLAVE_ANOC_PCIE_GEM_NOC_PCIE 5
+
+#define MASTER_PCIE_3 0
+#define MASTER_PCIE_4 1
+#define MASTER_PCIE_5 2
+#define SLAVE_PCIE_NORTH 3
+#define MASTER_PCIE_3_PCIE 4
+#define MASTER_PCIE_4_PCIE 5
+#define MASTER_PCIE_5_PCIE 6
+#define SLAVE_PCIE_NORTH_PCIE 7
+
+#define MASTER_PCIE_0 0
+#define MASTER_PCIE_1 1
+#define MASTER_PCIE_2 2
+#define MASTER_PCIE_6A 3
+#define MASTER_PCIE_6B 4
+#define SLAVE_PCIE_SOUTH 5
+#define MASTER_PCIE_0_PCIE 6
+#define MASTER_PCIE_1_PCIE 7
+#define MASTER_PCIE_2_PCIE 8
+#define MASTER_PCIE_6A_PCIE 9
+#define MASTER_PCIE_6B_PCIE 10
+#define SLAVE_PCIE_SOUTH_PCIE 11
+
+#define MASTER_A1NOC_SNOC 0
+#define MASTER_A2NOC_SNOC 1
+#define MASTER_GIC1 2
+#define MASTER_USB_NOC_SNOC 3
+#define SLAVE_SNOC_GEM_NOC_SF 4
+
+#define MASTER_AGGRE_USB_NORTH 0
+#define MASTER_AGGRE_USB_SOUTH 1
+#define SLAVE_USB_NOC_SNOC 2
+
+#define MASTER_USB2 0
+#define MASTER_USB3_MP 1
+#define SLAVE_AGGRE_USB_NORTH 2
+
+#define MASTER_USB3_0 0
+#define MASTER_USB3_1 1
+#define MASTER_USB3_2 2
+#define MASTER_USB4_0 3
+#define MASTER_USB4_1 4
+#define MASTER_USB4_2 5
+#define SLAVE_AGGRE_USB_SOUTH 6
+
+#endif
diff --git a/dts/upstream/include/dt-bindings/power/meson-g12a-power.h b/dts/upstream/include/dt-bindings/power/meson-g12a-power.h
index 44ec0c5..01fd0ac 100644
--- a/dts/upstream/include/dt-bindings/power/meson-g12a-power.h
+++ b/dts/upstream/include/dt-bindings/power/meson-g12a-power.h
@@ -10,5 +10,6 @@
#define PWRC_G12A_VPU_ID 0
#define PWRC_G12A_ETH_ID 1
#define PWRC_G12A_NNA_ID 2
+#define PWRC_G12A_ISP_ID 3
#endif
diff --git a/dts/upstream/include/dt-bindings/reset/amlogic,c3-reset.h b/dts/upstream/include/dt-bindings/reset/amlogic,c3-reset.h
new file mode 100644
index 0000000..d912786
--- /dev/null
+++ b/dts/upstream/include/dt-bindings/reset/amlogic,c3-reset.h
@@ -0,0 +1,119 @@
+/* SPDX-License-Identifier: (GPL-2.0-only OR MIT) */
+/*
+ * Copyright (c) 2023 Amlogic, Inc. All rights reserved.
+ */
+
+#ifndef _DT_BINDINGS_AMLOGIC_C3_RESET_H
+#define _DT_BINDINGS_AMLOGIC_C3_RESET_H
+
+/* RESET0 */
+/* 0-3 */
+#define RESET_USBCTRL 4
+/* 5-7 */
+#define RESET_USBPHY20 8
+/* 9 */
+#define RESET_USB2DRD 10
+#define RESET_MIPI_DSI_HOST 11
+#define RESET_MIPI_DSI_PHY 12
+/* 13-20 */
+#define RESET_GE2D 21
+#define RESET_DWAP 22
+/* 23-31 */
+
+/* RESET1 */
+#define RESET_AUDIO 32
+/* 33-34 */
+#define RESET_DDRAPB 35
+#define RESET_DDR 36
+#define RESET_DOS_CAPB3 37
+#define RESET_DOS 38
+/* 39-46 */
+#define RESET_NNA 47
+#define RESET_ETHERNET 48
+#define RESET_ISP 49
+#define RESET_VC9000E_APB 50
+#define RESET_VC9000E_A 51
+/* 52 */
+#define RESET_VC9000E_CORE 53
+/* 54-63 */
+
+/* RESET2 */
+#define RESET_ABUS_ARB 64
+#define RESET_IRCTRL 65
+/* 66 */
+#define RESET_TEMP_PII 67
+/* 68-72 */
+#define RESET_SPICC_0 73
+#define RESET_SPICC_1 74
+#define RESET_RSA 75
+
+/* 76-79 */
+#define RESET_MSR_CLK 80
+#define RESET_SPIFC 81
+#define RESET_SAR_ADC 82
+/* 83-87 */
+#define RESET_ACODEC 88
+/* 89-90 */
+#define RESET_WATCHDOG 91
+/* 92-95 */
+
+/* RESET3 */
+#define RESET_ISP_NIC_GPV 96
+#define RESET_ISP_NIC_MAIN 97
+#define RESET_ISP_NIC_VCLK 98
+#define RESET_ISP_NIC_VOUT 99
+#define RESET_ISP_NIC_ALL 100
+#define RESET_VOUT 101
+#define RESET_VOUT_VENC 102
+/* 103 */
+#define RESET_CVE_NIC_GPV 104
+#define RESET_CVE_NIC_MAIN 105
+#define RESET_CVE_NIC_GE2D 106
+#define RESET_CVE_NIC_DW 106
+#define RESET_CVE_NIC_CVE 108
+#define RESET_CVE_NIC_ALL 109
+#define RESET_CVE 110
+/* 112-127 */
+
+/* RESET4 */
+#define RESET_RTC 128
+#define RESET_PWM_AB 129
+#define RESET_PWM_CD 130
+#define RESET_PWM_EF 131
+#define RESET_PWM_GH 132
+#define RESET_PWM_IJ 133
+#define RESET_PWM_KL 134
+#define RESET_PWM_MN 135
+/* 136-137 */
+#define RESET_UART_A 138
+#define RESET_UART_B 139
+#define RESET_UART_C 140
+#define RESET_UART_D 141
+#define RESET_UART_E 142
+#define RESET_UART_F 143
+#define RESET_I2C_S_A 144
+#define RESET_I2C_M_A 145
+#define RESET_I2C_M_B 146
+#define RESET_I2C_M_C 147
+#define RESET_I2C_M_D 148
+/* 149-151 */
+#define RESET_SD_EMMC_A 152
+#define RESET_SD_EMMC_B 153
+#define RESET_SD_EMMC_C 154
+
+/* RESET5 */
+/* 160-172 */
+#define RESET_BRG_NIC_NNA 173
+#define RESET_BRG_MUX_NIC_MAIN 174
+#define RESET_BRG_AO_NIC_ALL 175
+/* 176-183 */
+#define RESET_BRG_NIC_VAPB 184
+#define RESET_BRG_NIC_SDIO_B 185
+#define RESET_BRG_NIC_SDIO_A 186
+#define RESET_BRG_NIC_EMMC 187
+#define RESET_BRG_NIC_DSU 188
+#define RESET_BRG_NIC_SYSCLK 189
+#define RESET_BRG_NIC_MAIN 190
+#define RESET_BRG_NIC_ALL 191
+
+#endif
diff --git a/dts/upstream/include/dt-bindings/reset/mediatek,mt7988-resets.h b/dts/upstream/include/dt-bindings/reset/mediatek,mt7988-resets.h
new file mode 100644
index 0000000..4933019
--- /dev/null
+++ b/dts/upstream/include/dt-bindings/reset/mediatek,mt7988-resets.h
@@ -0,0 +1,13 @@
+/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */
+/*
+ * Copyright (c) 2023 Daniel Golle <daniel@makrotopia.org>
+ * Author: Daniel Golle <daniel@makrotopia.org>
+ */
+
+#ifndef _DT_BINDINGS_RESET_CONTROLLER_MT7988
+#define _DT_BINDINGS_RESET_CONTROLLER_MT7988
+
+/* ETHWARP resets */
+#define MT7988_ETHWARP_RST_SWITCH 0
+
+#endif /* _DT_BINDINGS_RESET_CONTROLLER_MT7988 */
diff --git a/dts/upstream/include/dt-bindings/reset/mt8188-resets.h b/dts/upstream/include/dt-bindings/reset/mt8188-resets.h
index ba9a5e9..5a58c54 100644
--- a/dts/upstream/include/dt-bindings/reset/mt8188-resets.h
+++ b/dts/upstream/include/dt-bindings/reset/mt8188-resets.h
@@ -38,4 +38,79 @@
#define MT8188_INFRA_RST1_THERMAL_CTRL_RST 1
#define MT8188_INFRA_RST3_PTP_CTRL_RST 2
+#define MT8188_VDO0_RST_DISP_OVL0 0
+#define MT8188_VDO0_RST_FAKE_ENG0 1
+#define MT8188_VDO0_RST_DISP_CCORR0 2
+#define MT8188_VDO0_RST_DISP_MUTEX0 3
+#define MT8188_VDO0_RST_DISP_GAMMA0 4
+#define MT8188_VDO0_RST_DISP_DITHER0 5
+#define MT8188_VDO0_RST_DISP_WDMA0 6
+#define MT8188_VDO0_RST_DISP_RDMA0 7
+#define MT8188_VDO0_RST_DSI0 8
+#define MT8188_VDO0_RST_DSI1 9
+#define MT8188_VDO0_RST_DSC_WRAP0 10
+#define MT8188_VDO0_RST_VPP_MERGE0 11
+#define MT8188_VDO0_RST_DP_INTF0 12
+#define MT8188_VDO0_RST_DISP_AAL0 13
+#define MT8188_VDO0_RST_INLINEROT0 14
+#define MT8188_VDO0_RST_APB_BUS 15
+#define MT8188_VDO0_RST_DISP_COLOR0 16
+#define MT8188_VDO0_RST_MDP_WROT0 17
+#define MT8188_VDO0_RST_DISP_RSZ0 18
+
+#define MT8188_VDO1_RST_SMI_LARB2 0
+#define MT8188_VDO1_RST_SMI_LARB3 1
+#define MT8188_VDO1_RST_GALS 2
+#define MT8188_VDO1_RST_FAKE_ENG0 3
+#define MT8188_VDO1_RST_FAKE_ENG1 4
+#define MT8188_VDO1_RST_MDP_RDMA0 5
+#define MT8188_VDO1_RST_MDP_RDMA1 6
+#define MT8188_VDO1_RST_MDP_RDMA2 7
+#define MT8188_VDO1_RST_MDP_RDMA3 8
+#define MT8188_VDO1_RST_VPP_MERGE0 9
+#define MT8188_VDO1_RST_VPP_MERGE1 10
+#define MT8188_VDO1_RST_VPP_MERGE2 11
+#define MT8188_VDO1_RST_VPP_MERGE3 12
+#define MT8188_VDO1_RST_VPP_MERGE4 13
+#define MT8188_VDO1_RST_VPP2_TO_VDO1_DL_ASYNC 14
+#define MT8188_VDO1_RST_VPP3_TO_VDO1_DL_ASYNC 15
+#define MT8188_VDO1_RST_DISP_MUTEX 16
+#define MT8188_VDO1_RST_MDP_RDMA4 17
+#define MT8188_VDO1_RST_MDP_RDMA5 18
+#define MT8188_VDO1_RST_MDP_RDMA6 19
+#define MT8188_VDO1_RST_MDP_RDMA7 20
+#define MT8188_VDO1_RST_DP_INTF1_MMCK 21
+#define MT8188_VDO1_RST_DPI0_MM_CK 22
+#define MT8188_VDO1_RST_DPI1_MM_CK 23
+#define MT8188_VDO1_RST_MERGE0_DL_ASYNC 24
+#define MT8188_VDO1_RST_MERGE1_DL_ASYNC 25
+#define MT8188_VDO1_RST_MERGE2_DL_ASYNC 26
+#define MT8188_VDO1_RST_MERGE3_DL_ASYNC 27
+#define MT8188_VDO1_RST_MERGE4_DL_ASYNC 28
+#define MT8188_VDO1_RST_VDO0_DSC_TO_VDO1_DL_ASYNC 29
+#define MT8188_VDO1_RST_VDO0_MERGE_TO_VDO1_DL_ASYNC 30
+#define MT8188_VDO1_RST_PADDING0 31
+#define MT8188_VDO1_RST_PADDING1 32
+#define MT8188_VDO1_RST_PADDING2 33
+#define MT8188_VDO1_RST_PADDING3 34
+#define MT8188_VDO1_RST_PADDING4 35
+#define MT8188_VDO1_RST_PADDING5 36
+#define MT8188_VDO1_RST_PADDING6 37
+#define MT8188_VDO1_RST_PADDING7 38
+#define MT8188_VDO1_RST_DISP_RSZ0 39
+#define MT8188_VDO1_RST_DISP_RSZ1 40
+#define MT8188_VDO1_RST_DISP_RSZ2 41
+#define MT8188_VDO1_RST_DISP_RSZ3 42
+#define MT8188_VDO1_RST_HDR_VDO_FE0 43
+#define MT8188_VDO1_RST_HDR_GFX_FE0 44
+#define MT8188_VDO1_RST_HDR_VDO_BE 45
+#define MT8188_VDO1_RST_HDR_VDO_FE1 46
+#define MT8188_VDO1_RST_HDR_GFX_FE1 47
+#define MT8188_VDO1_RST_DISP_MIXER 48
+#define MT8188_VDO1_RST_HDR_VDO_FE0_DL_ASYNC 49
+#define MT8188_VDO1_RST_HDR_VDO_FE1_DL_ASYNC 50
+#define MT8188_VDO1_RST_HDR_GFX_FE0_DL_ASYNC 51
+#define MT8188_VDO1_RST_HDR_GFX_FE1_DL_ASYNC 52
+#define MT8188_VDO1_RST_HDR_VDO_BE_DL_ASYNC 53
+
#endif /* _DT_BINDINGS_RESET_CONTROLLER_MT8188 */
diff --git a/dts/upstream/include/dt-bindings/reset/qcom,sm8650-gpucc.h b/dts/upstream/include/dt-bindings/reset/qcom,sm8650-gpucc.h
new file mode 100644
index 0000000..f021a6c
--- /dev/null
+++ b/dts/upstream/include/dt-bindings/reset/qcom,sm8650-gpucc.h
@@ -0,0 +1,20 @@
+/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */
+/*
+ * Copyright (c) 2019, The Linux Foundation. All rights reserved.
+ * Copyright (c) 2023, Linaro Limited
+ */
+
+#ifndef _DT_BINDINGS_RESET_QCOM_GPU_CC_SM8650_H
+#define _DT_BINDINGS_RESET_QCOM_GPU_CC_SM8650_H
+
+#define GPUCC_GPU_CC_ACD_BCR 0
+#define GPUCC_GPU_CC_CX_BCR 1
+#define GPUCC_GPU_CC_FAST_HUB_BCR 2
+#define GPUCC_GPU_CC_FF_BCR 3
+#define GPUCC_GPU_CC_GFX3D_AON_BCR 4
+#define GPUCC_GPU_CC_GMU_BCR 5
+#define GPUCC_GPU_CC_GX_BCR 6
+#define GPUCC_GPU_CC_XO_BCR 7
+#define GPUCC_GPU_CC_GX_ACD_IROOT_BCR 8
+
+#endif
diff --git a/dts/upstream/include/dt-bindings/reset/st,stm32mp25-rcc.h b/dts/upstream/include/dt-bindings/reset/st,stm32mp25-rcc.h
new file mode 100644
index 0000000..d561593
--- /dev/null
+++ b/dts/upstream/include/dt-bindings/reset/st,stm32mp25-rcc.h
@@ -0,0 +1,167 @@
+/* SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause */
+/*
+ * Copyright (C) STMicroelectronics 2023 - All Rights Reserved
+ * Author(s): Gabriel Fernandez <gabriel.fernandez@foss.st.com>
+ */
+
+#ifndef _DT_BINDINGS_STM32MP25_RESET_H_
+#define _DT_BINDINGS_STM32MP25_RESET_H_
+
+#define TIM1_R 0
+#define TIM2_R 1
+#define TIM3_R 2
+#define TIM4_R 3
+#define TIM5_R 4
+#define TIM6_R 5
+#define TIM7_R 6
+#define TIM8_R 7
+#define TIM10_R 8
+#define TIM11_R 9
+#define TIM12_R 10
+#define TIM13_R 11
+#define TIM14_R 12
+#define TIM15_R 13
+#define TIM16_R 14
+#define TIM17_R 15
+#define TIM20_R 16
+#define LPTIM1_R 17
+#define LPTIM2_R 18
+#define LPTIM3_R 19
+#define LPTIM4_R 20
+#define LPTIM5_R 21
+#define SPI1_R 22
+#define SPI2_R 23
+#define SPI3_R 24
+#define SPI4_R 25
+#define SPI5_R 26
+#define SPI6_R 27
+#define SPI7_R 28
+#define SPI8_R 29
+#define SPDIFRX_R 30
+#define USART1_R 31
+#define USART2_R 32
+#define USART3_R 33
+#define UART4_R 34
+#define UART5_R 35
+#define USART6_R 36
+#define UART7_R 37
+#define UART8_R 38
+#define UART9_R 39
+#define LPUART1_R 40
+#define IS2M_R 41
+#define I2C1_R 42
+#define I2C2_R 43
+#define I2C3_R 44
+#define I2C4_R 45
+#define I2C5_R 46
+#define I2C6_R 47
+#define I2C7_R 48
+#define I2C8_R 49
+#define SAI1_R 50
+#define SAI2_R 51
+#define SAI3_R 52
+#define SAI4_R 53
+#define MDF1_R 54
+#define MDF2_R 55
+#define FDCAN_R 56
+#define HDP_R 57
+#define ADC12_R 58
+#define ADC3_R 59
+#define ETH1_R 60
+#define ETH2_R 61
+#define USB2_R 62
+#define USB2PHY1_R 63
+#define USB2PHY2_R 64
+#define USB3DR_R 65
+#define USB3PCIEPHY_R 66
+#define USBTC_R 67
+#define ETHSW_R 68
+#define SDMMC1_R 69
+#define SDMMC1DLL_R 70
+#define SDMMC2_R 71
+#define SDMMC2DLL_R 72
+#define SDMMC3_R 73
+#define SDMMC3DLL_R 74
+#define GPU_R 75
+#define LTDC_R 76
+#define DSI_R 77
+#define LVDS_R 78
+#define CSI_R 79
+#define DCMIPP_R 80
+#define CCI_R 81
+#define VDEC_R 82
+#define VENC_R 83
+#define WWDG1_R 84
+#define WWDG2_R 85
+#define VREF_R 86
+#define DTS_R 87
+#define CRC_R 88
+#define SERC_R 89
+#define OSPIIOM_R 90
+#define I3C1_R 91
+#define I3C2_R 92
+#define I3C3_R 93
+#define I3C4_R 94
+#define IWDG2_KER_R 95
+#define IWDG4_KER_R 96
+#define RNG_R 97
+#define PKA_R 98
+#define SAES_R 99
+#define HASH_R 100
+#define CRYP1_R 101
+#define CRYP2_R 102
+#define PCIE_R 103
+#define OSPI1_R 104
+#define OSPI1DLL_R 105
+#define OSPI2_R 106
+#define OSPI2DLL_R 107
+#define FMC_R 108
+#define DBG_R 109
+#define GPIOA_R 110
+#define GPIOB_R 111
+#define GPIOC_R 112
+#define GPIOD_R 113
+#define GPIOE_R 114
+#define GPIOF_R 115
+#define GPIOG_R 116
+#define GPIOH_R 117
+#define GPIOI_R 118
+#define GPIOJ_R 119
+#define GPIOK_R 120
+#define GPIOZ_R 121
+#define HPDMA1_R 122
+#define HPDMA2_R 123
+#define HPDMA3_R 124
+#define LPDMA_R 125
+#define HSEM_R 126
+#define IPCC1_R 127
+#define IPCC2_R 128
+#define C2_HOLDBOOT_R 129
+#define C1_HOLDBOOT_R 130
+#define C1_R 131
+#define C1P1POR_R 132
+#define C1P1_R 133
+#define C2_R 134
+#define C3_R 135
+#define SYS_R 136
+#define VSW_R 137
+#define C1MS_R 138
+#define DDRCP_R 139
+#define DDRCAPB_R 140
+#define DDRPHYCAPB_R 141
+#define DDRCFG_R 142
+#define DDR_R 143
+
+#define STM32MP25_LAST_RESET 144
+
+#define RST_SCMI_C1_R 0
+#define RST_SCMI_C2_R 1
+#define RST_SCMI_C1_HOLDBOOT_R 2
+#define RST_SCMI_C2_HOLDBOOT_R 3
+#define RST_SCMI_FMC 4
+#define RST_SCMI_OSPI1 5
+#define RST_SCMI_OSPI1DLL 6
+#define RST_SCMI_OSPI2 7
+#define RST_SCMI_OSPI2DLL 8
+
+#endif /* _DT_BINDINGS_STM32MP25_RESET_H_ */
diff --git a/dts/upstream/include/dt-bindings/soc/rockchip,vop2.h b/dts/upstream/include/dt-bindings/soc/rockchip,vop2.h
index 6e66a80..668f199 100644
--- a/dts/upstream/include/dt-bindings/soc/rockchip,vop2.h
+++ b/dts/upstream/include/dt-bindings/soc/rockchip,vop2.h
@@ -10,5 +10,9 @@
#define ROCKCHIP_VOP2_EP_LVDS0 5
#define ROCKCHIP_VOP2_EP_MIPI1 6
#define ROCKCHIP_VOP2_EP_LVDS1 7
+#define ROCKCHIP_VOP2_EP_HDMI1 8
+#define ROCKCHIP_VOP2_EP_EDP1 9
+#define ROCKCHIP_VOP2_EP_DP0 10
+#define ROCKCHIP_VOP2_EP_DP1 11
#endif /* __DT_BINDINGS_ROCKCHIP_VOP2_H */
diff --git a/dts/upstream/src/arm/Makefile b/dts/upstream/src/arm/Makefile
new file mode 100644
index 0000000..9a8f6aa
--- /dev/null
+++ b/dts/upstream/src/arm/Makefile
@@ -0,0 +1,14 @@
+# SPDX-License-Identifier: GPL-2.0+
+
+include $(srctree)/scripts/Makefile.dts
+
+targets += $(dtb-y)
+
+# Add any required device tree compiler flags here
+DTC_FLAGS += -a 0x8
+
+PHONY += dtbs
+dtbs: $(addprefix $(obj)/, $(dtb-y))
+ @:
+
+clean-files := */*.dtb */*.dtbo
diff --git a/dts/upstream/src/arm/amazon/alpine.dtsi b/dts/upstream/src/arm/amazon/alpine.dtsi
index ff68dfb..90bd12f 100644
--- a/dts/upstream/src/arm/amazon/alpine.dtsi
+++ b/dts/upstream/src/arm/amazon/alpine.dtsi
@@ -167,7 +167,6 @@
msix: msix@fbe00000 {
compatible = "al,alpine-msix";
reg = <0x0 0xfbe00000 0x0 0x100000>;
- interrupt-controller;
msi-controller;
al,msi-base-spi = <96>;
al,msi-num-spis = <64>;
diff --git a/dts/upstream/src/arm/aspeed/aspeed-bmc-facebook-bletchley.dts b/dts/upstream/src/arm/aspeed/aspeed-bmc-facebook-bletchley.dts
index e899de6..5be0e8f 100644
--- a/dts/upstream/src/arm/aspeed/aspeed-bmc-facebook-bletchley.dts
+++ b/dts/upstream/src/arm/aspeed/aspeed-bmc-facebook-bletchley.dts
@@ -45,8 +45,8 @@
num-chipselects = <1>;
cs-gpios = <&gpio0 ASPEED_GPIO(Z, 0) GPIO_ACTIVE_LOW>;
- tpmdev@0 {
- compatible = "tcg,tpm_tis-spi";
+ tpm@0 {
+ compatible = "infineon,slb9670", "tcg,tpm_tis-spi";
spi-max-frequency = <33000000>;
reg = <0>;
};
diff --git a/dts/upstream/src/arm/aspeed/aspeed-bmc-facebook-wedge400.dts b/dts/upstream/src/arm/aspeed/aspeed-bmc-facebook-wedge400.dts
index a677c82..5a8169b 100644
--- a/dts/upstream/src/arm/aspeed/aspeed-bmc-facebook-wedge400.dts
+++ b/dts/upstream/src/arm/aspeed/aspeed-bmc-facebook-wedge400.dts
@@ -80,8 +80,8 @@
gpio-miso = <&gpio ASPEED_GPIO(R, 5) GPIO_ACTIVE_HIGH>;
num-chipselects = <1>;
- tpmdev@0 {
- compatible = "tcg,tpm_tis-spi";
+ tpm@0 {
+ compatible = "infineon,slb9670", "tcg,tpm_tis-spi";
spi-max-frequency = <33000000>;
reg = <0>;
};
diff --git a/dts/upstream/src/arm/aspeed/aspeed-bmc-opp-tacoma.dts b/dts/upstream/src/arm/aspeed/aspeed-bmc-opp-tacoma.dts
index 3f6010e..213023b 100644
--- a/dts/upstream/src/arm/aspeed/aspeed-bmc-opp-tacoma.dts
+++ b/dts/upstream/src/arm/aspeed/aspeed-bmc-opp-tacoma.dts
@@ -456,7 +456,7 @@
status = "okay";
tpm: tpm@2e {
- compatible = "tcg,tpm-tis-i2c";
+ compatible = "nuvoton,npct75x", "tcg,tpm-tis-i2c";
reg = <0x2e>;
};
};
diff --git a/dts/upstream/src/arm/aspeed/aspeed-g4.dtsi b/dts/upstream/src/arm/aspeed/aspeed-g4.dtsi
index 530491a..857cb26 100644
--- a/dts/upstream/src/arm/aspeed/aspeed-g4.dtsi
+++ b/dts/upstream/src/arm/aspeed/aspeed-g4.dtsi
@@ -466,7 +466,6 @@
i2c0: i2c-bus@40 {
#address-cells = <1>;
#size-cells = <0>;
- #interrupt-cells = <1>;
reg = <0x40 0x40>;
compatible = "aspeed,ast2400-i2c-bus";
@@ -482,7 +481,6 @@
i2c1: i2c-bus@80 {
#address-cells = <1>;
#size-cells = <0>;
- #interrupt-cells = <1>;
reg = <0x80 0x40>;
compatible = "aspeed,ast2400-i2c-bus";
@@ -498,7 +496,6 @@
i2c2: i2c-bus@c0 {
#address-cells = <1>;
#size-cells = <0>;
- #interrupt-cells = <1>;
reg = <0xc0 0x40>;
compatible = "aspeed,ast2400-i2c-bus";
@@ -515,7 +512,6 @@
i2c3: i2c-bus@100 {
#address-cells = <1>;
#size-cells = <0>;
- #interrupt-cells = <1>;
reg = <0x100 0x40>;
compatible = "aspeed,ast2400-i2c-bus";
@@ -532,7 +528,6 @@
i2c4: i2c-bus@140 {
#address-cells = <1>;
#size-cells = <0>;
- #interrupt-cells = <1>;
reg = <0x140 0x40>;
compatible = "aspeed,ast2400-i2c-bus";
@@ -549,7 +544,6 @@
i2c5: i2c-bus@180 {
#address-cells = <1>;
#size-cells = <0>;
- #interrupt-cells = <1>;
reg = <0x180 0x40>;
compatible = "aspeed,ast2400-i2c-bus";
@@ -566,7 +560,6 @@
i2c6: i2c-bus@1c0 {
#address-cells = <1>;
#size-cells = <0>;
- #interrupt-cells = <1>;
reg = <0x1c0 0x40>;
compatible = "aspeed,ast2400-i2c-bus";
@@ -583,7 +576,6 @@
i2c7: i2c-bus@300 {
#address-cells = <1>;
#size-cells = <0>;
- #interrupt-cells = <1>;
reg = <0x300 0x40>;
compatible = "aspeed,ast2400-i2c-bus";
@@ -600,7 +592,6 @@
i2c8: i2c-bus@340 {
#address-cells = <1>;
#size-cells = <0>;
- #interrupt-cells = <1>;
reg = <0x340 0x40>;
compatible = "aspeed,ast2400-i2c-bus";
@@ -617,7 +608,6 @@
i2c9: i2c-bus@380 {
#address-cells = <1>;
#size-cells = <0>;
- #interrupt-cells = <1>;
reg = <0x380 0x40>;
compatible = "aspeed,ast2400-i2c-bus";
@@ -634,7 +624,6 @@
i2c10: i2c-bus@3c0 {
#address-cells = <1>;
#size-cells = <0>;
- #interrupt-cells = <1>;
reg = <0x3c0 0x40>;
compatible = "aspeed,ast2400-i2c-bus";
@@ -651,7 +640,6 @@
i2c11: i2c-bus@400 {
#address-cells = <1>;
#size-cells = <0>;
- #interrupt-cells = <1>;
reg = <0x400 0x40>;
compatible = "aspeed,ast2400-i2c-bus";
@@ -668,7 +656,6 @@
i2c12: i2c-bus@440 {
#address-cells = <1>;
#size-cells = <0>;
- #interrupt-cells = <1>;
reg = <0x440 0x40>;
compatible = "aspeed,ast2400-i2c-bus";
@@ -685,7 +672,6 @@
i2c13: i2c-bus@480 {
#address-cells = <1>;
#size-cells = <0>;
- #interrupt-cells = <1>;
reg = <0x480 0x40>;
compatible = "aspeed,ast2400-i2c-bus";
diff --git a/dts/upstream/src/arm/aspeed/aspeed-g5.dtsi b/dts/upstream/src/arm/aspeed/aspeed-g5.dtsi
index 04f98d1..e6f3cf3c 100644
--- a/dts/upstream/src/arm/aspeed/aspeed-g5.dtsi
+++ b/dts/upstream/src/arm/aspeed/aspeed-g5.dtsi
@@ -363,6 +363,7 @@
interrupts = <40>;
reg = <0x1e780200 0x0100>;
clocks = <&syscon ASPEED_CLK_APB>;
+ #interrupt-cells = <2>;
interrupt-controller;
bus-frequency = <12000000>;
pinctrl-names = "default";
@@ -594,7 +595,6 @@
i2c0: i2c-bus@40 {
#address-cells = <1>;
#size-cells = <0>;
- #interrupt-cells = <1>;
reg = <0x40 0x40>;
compatible = "aspeed,ast2500-i2c-bus";
@@ -610,7 +610,6 @@
i2c1: i2c-bus@80 {
#address-cells = <1>;
#size-cells = <0>;
- #interrupt-cells = <1>;
reg = <0x80 0x40>;
compatible = "aspeed,ast2500-i2c-bus";
@@ -626,7 +625,6 @@
i2c2: i2c-bus@c0 {
#address-cells = <1>;
#size-cells = <0>;
- #interrupt-cells = <1>;
reg = <0xc0 0x40>;
compatible = "aspeed,ast2500-i2c-bus";
@@ -643,7 +641,6 @@
i2c3: i2c-bus@100 {
#address-cells = <1>;
#size-cells = <0>;
- #interrupt-cells = <1>;
reg = <0x100 0x40>;
compatible = "aspeed,ast2500-i2c-bus";
@@ -660,7 +657,6 @@
i2c4: i2c-bus@140 {
#address-cells = <1>;
#size-cells = <0>;
- #interrupt-cells = <1>;
reg = <0x140 0x40>;
compatible = "aspeed,ast2500-i2c-bus";
@@ -677,7 +673,6 @@
i2c5: i2c-bus@180 {
#address-cells = <1>;
#size-cells = <0>;
- #interrupt-cells = <1>;
reg = <0x180 0x40>;
compatible = "aspeed,ast2500-i2c-bus";
@@ -694,7 +689,6 @@
i2c6: i2c-bus@1c0 {
#address-cells = <1>;
#size-cells = <0>;
- #interrupt-cells = <1>;
reg = <0x1c0 0x40>;
compatible = "aspeed,ast2500-i2c-bus";
@@ -711,7 +705,6 @@
i2c7: i2c-bus@300 {
#address-cells = <1>;
#size-cells = <0>;
- #interrupt-cells = <1>;
reg = <0x300 0x40>;
compatible = "aspeed,ast2500-i2c-bus";
@@ -728,7 +721,6 @@
i2c8: i2c-bus@340 {
#address-cells = <1>;
#size-cells = <0>;
- #interrupt-cells = <1>;
reg = <0x340 0x40>;
compatible = "aspeed,ast2500-i2c-bus";
@@ -745,7 +737,6 @@
i2c9: i2c-bus@380 {
#address-cells = <1>;
#size-cells = <0>;
- #interrupt-cells = <1>;
reg = <0x380 0x40>;
compatible = "aspeed,ast2500-i2c-bus";
@@ -762,7 +753,6 @@
i2c10: i2c-bus@3c0 {
#address-cells = <1>;
#size-cells = <0>;
- #interrupt-cells = <1>;
reg = <0x3c0 0x40>;
compatible = "aspeed,ast2500-i2c-bus";
@@ -779,7 +769,6 @@
i2c11: i2c-bus@400 {
#address-cells = <1>;
#size-cells = <0>;
- #interrupt-cells = <1>;
reg = <0x400 0x40>;
compatible = "aspeed,ast2500-i2c-bus";
@@ -796,7 +785,6 @@
i2c12: i2c-bus@440 {
#address-cells = <1>;
#size-cells = <0>;
- #interrupt-cells = <1>;
reg = <0x440 0x40>;
compatible = "aspeed,ast2500-i2c-bus";
@@ -813,7 +801,6 @@
i2c13: i2c-bus@480 {
#address-cells = <1>;
#size-cells = <0>;
- #interrupt-cells = <1>;
reg = <0x480 0x40>;
compatible = "aspeed,ast2500-i2c-bus";
diff --git a/dts/upstream/src/arm/aspeed/aspeed-g6.dtsi b/dts/upstream/src/arm/aspeed/aspeed-g6.dtsi
index c4d1faa..29f9469 100644
--- a/dts/upstream/src/arm/aspeed/aspeed-g6.dtsi
+++ b/dts/upstream/src/arm/aspeed/aspeed-g6.dtsi
@@ -474,6 +474,7 @@
reg = <0x1e780500 0x100>;
interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&syscon ASPEED_CLK_APB2>;
+ #interrupt-cells = <2>;
interrupt-controller;
bus-frequency = <12000000>;
pinctrl-names = "default";
@@ -488,6 +489,7 @@
reg = <0x1e780600 0x100>;
interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&syscon ASPEED_CLK_APB2>;
+ #interrupt-cells = <2>;
interrupt-controller;
bus-frequency = <12000000>;
pinctrl-names = "default";
@@ -902,7 +904,6 @@
i2c0: i2c-bus@80 {
#address-cells = <1>;
#size-cells = <0>;
- #interrupt-cells = <1>;
reg = <0x80 0x80>;
compatible = "aspeed,ast2600-i2c-bus";
clocks = <&syscon ASPEED_CLK_APB2>;
@@ -917,7 +918,6 @@
i2c1: i2c-bus@100 {
#address-cells = <1>;
#size-cells = <0>;
- #interrupt-cells = <1>;
reg = <0x100 0x80>;
compatible = "aspeed,ast2600-i2c-bus";
clocks = <&syscon ASPEED_CLK_APB2>;
@@ -932,7 +932,6 @@
i2c2: i2c-bus@180 {
#address-cells = <1>;
#size-cells = <0>;
- #interrupt-cells = <1>;
reg = <0x180 0x80>;
compatible = "aspeed,ast2600-i2c-bus";
clocks = <&syscon ASPEED_CLK_APB2>;
@@ -947,7 +946,6 @@
i2c3: i2c-bus@200 {
#address-cells = <1>;
#size-cells = <0>;
- #interrupt-cells = <1>;
reg = <0x200 0x80>;
compatible = "aspeed,ast2600-i2c-bus";
clocks = <&syscon ASPEED_CLK_APB2>;
@@ -962,7 +960,6 @@
i2c4: i2c-bus@280 {
#address-cells = <1>;
#size-cells = <0>;
- #interrupt-cells = <1>;
reg = <0x280 0x80>;
compatible = "aspeed,ast2600-i2c-bus";
clocks = <&syscon ASPEED_CLK_APB2>;
@@ -977,7 +974,6 @@
i2c5: i2c-bus@300 {
#address-cells = <1>;
#size-cells = <0>;
- #interrupt-cells = <1>;
reg = <0x300 0x80>;
compatible = "aspeed,ast2600-i2c-bus";
clocks = <&syscon ASPEED_CLK_APB2>;
@@ -992,7 +988,6 @@
i2c6: i2c-bus@380 {
#address-cells = <1>;
#size-cells = <0>;
- #interrupt-cells = <1>;
reg = <0x380 0x80>;
compatible = "aspeed,ast2600-i2c-bus";
clocks = <&syscon ASPEED_CLK_APB2>;
@@ -1007,7 +1002,6 @@
i2c7: i2c-bus@400 {
#address-cells = <1>;
#size-cells = <0>;
- #interrupt-cells = <1>;
reg = <0x400 0x80>;
compatible = "aspeed,ast2600-i2c-bus";
clocks = <&syscon ASPEED_CLK_APB2>;
@@ -1022,7 +1016,6 @@
i2c8: i2c-bus@480 {
#address-cells = <1>;
#size-cells = <0>;
- #interrupt-cells = <1>;
reg = <0x480 0x80>;
compatible = "aspeed,ast2600-i2c-bus";
clocks = <&syscon ASPEED_CLK_APB2>;
@@ -1037,7 +1030,6 @@
i2c9: i2c-bus@500 {
#address-cells = <1>;
#size-cells = <0>;
- #interrupt-cells = <1>;
reg = <0x500 0x80>;
compatible = "aspeed,ast2600-i2c-bus";
clocks = <&syscon ASPEED_CLK_APB2>;
@@ -1052,7 +1044,6 @@
i2c10: i2c-bus@580 {
#address-cells = <1>;
#size-cells = <0>;
- #interrupt-cells = <1>;
reg = <0x580 0x80>;
compatible = "aspeed,ast2600-i2c-bus";
clocks = <&syscon ASPEED_CLK_APB2>;
@@ -1067,7 +1058,6 @@
i2c11: i2c-bus@600 {
#address-cells = <1>;
#size-cells = <0>;
- #interrupt-cells = <1>;
reg = <0x600 0x80>;
compatible = "aspeed,ast2600-i2c-bus";
clocks = <&syscon ASPEED_CLK_APB2>;
@@ -1082,7 +1072,6 @@
i2c12: i2c-bus@680 {
#address-cells = <1>;
#size-cells = <0>;
- #interrupt-cells = <1>;
reg = <0x680 0x80>;
compatible = "aspeed,ast2600-i2c-bus";
clocks = <&syscon ASPEED_CLK_APB2>;
@@ -1097,7 +1086,6 @@
i2c13: i2c-bus@700 {
#address-cells = <1>;
#size-cells = <0>;
- #interrupt-cells = <1>;
reg = <0x700 0x80>;
compatible = "aspeed,ast2600-i2c-bus";
clocks = <&syscon ASPEED_CLK_APB2>;
@@ -1112,7 +1100,6 @@
i2c14: i2c-bus@780 {
#address-cells = <1>;
#size-cells = <0>;
- #interrupt-cells = <1>;
reg = <0x780 0x80>;
compatible = "aspeed,ast2600-i2c-bus";
clocks = <&syscon ASPEED_CLK_APB2>;
@@ -1127,7 +1114,6 @@
i2c15: i2c-bus@800 {
#address-cells = <1>;
#size-cells = <0>;
- #interrupt-cells = <1>;
reg = <0x800 0x80>;
compatible = "aspeed,ast2600-i2c-bus";
clocks = <&syscon ASPEED_CLK_APB2>;
diff --git a/dts/upstream/src/arm/aspeed/ast2600-facebook-netbmc-common.dtsi b/dts/upstream/src/arm/aspeed/ast2600-facebook-netbmc-common.dtsi
index 31590d3..00e5887 100644
--- a/dts/upstream/src/arm/aspeed/ast2600-facebook-netbmc-common.dtsi
+++ b/dts/upstream/src/arm/aspeed/ast2600-facebook-netbmc-common.dtsi
@@ -35,8 +35,8 @@
gpio-mosi = <&gpio0 ASPEED_GPIO(X, 4) GPIO_ACTIVE_HIGH>;
gpio-miso = <&gpio0 ASPEED_GPIO(X, 5) GPIO_ACTIVE_HIGH>;
- tpmdev@0 {
- compatible = "tcg,tpm_tis-spi";
+ tpm@0 {
+ compatible = "infineon,slb9670", "tcg,tpm_tis-spi";
spi-max-frequency = <33000000>;
reg = <0>;
};
diff --git a/dts/upstream/src/arm/broadcom/bcm-cygnus.dtsi b/dts/upstream/src/arm/broadcom/bcm-cygnus.dtsi
index f9f79ed..07ca0d9 100644
--- a/dts/upstream/src/arm/broadcom/bcm-cygnus.dtsi
+++ b/dts/upstream/src/arm/broadcom/bcm-cygnus.dtsi
@@ -167,6 +167,7 @@
#gpio-cells = <2>;
gpio-controller;
interrupt-controller;
+ #interrupt-cells = <2>;
interrupt-parent = <&mailbox>;
interrupts = <0>;
};
@@ -247,6 +248,7 @@
gpio-controller;
interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
interrupt-controller;
+ #interrupt-cells = <2>;
};
i2c1: i2c@1800b000 {
@@ -518,6 +520,7 @@
gpio-controller;
interrupt-controller;
+ #interrupt-cells = <2>;
interrupts = <GIC_SPI 174 IRQ_TYPE_LEVEL_HIGH>;
gpio-ranges = <&pinctrl 0 42 1>,
<&pinctrl 1 44 3>,
diff --git a/dts/upstream/src/arm/broadcom/bcm-hr2.dtsi b/dts/upstream/src/arm/broadcom/bcm-hr2.dtsi
index 788a680..75545b1 100644
--- a/dts/upstream/src/arm/broadcom/bcm-hr2.dtsi
+++ b/dts/upstream/src/arm/broadcom/bcm-hr2.dtsi
@@ -200,6 +200,7 @@
gpio-controller;
ngpios = <4>;
interrupt-controller;
+ #interrupt-cells = <2>;
interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>;
};
diff --git a/dts/upstream/src/arm/broadcom/bcm-nsp.dtsi b/dts/upstream/src/arm/broadcom/bcm-nsp.dtsi
index 9d20ba3..6a4482c 100644
--- a/dts/upstream/src/arm/broadcom/bcm-nsp.dtsi
+++ b/dts/upstream/src/arm/broadcom/bcm-nsp.dtsi
@@ -180,6 +180,7 @@
gpio-controller;
ngpios = <32>;
interrupt-controller;
+ #interrupt-cells = <2>;
interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
gpio-ranges = <&pinctrl 0 0 32>;
};
@@ -352,6 +353,7 @@
gpio-controller;
ngpios = <4>;
interrupt-controller;
+ #interrupt-cells = <2>;
interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>;
};
diff --git a/dts/upstream/src/arm/broadcom/bcm2711-rpi.dtsi b/dts/upstream/src/arm/broadcom/bcm2711-rpi.dtsi
index 98817a6..d233a19 100644
--- a/dts/upstream/src/arm/broadcom/bcm2711-rpi.dtsi
+++ b/dts/upstream/src/arm/broadcom/bcm2711-rpi.dtsi
@@ -1,6 +1,7 @@
// SPDX-License-Identifier: GPL-2.0
#include "bcm2835-rpi.dtsi"
+#include <dt-bindings/power/raspberrypi-power.h>
#include <dt-bindings/reset/raspberrypi,firmware-reset.h>
/ {
@@ -76,3 +77,7 @@
&vchiq {
interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
};
+
+&xhci {
+ power-domains = <&power RPI_POWER_DOMAIN_USB>;
+};
diff --git a/dts/upstream/src/arm/broadcom/bcm2711.dtsi b/dts/upstream/src/arm/broadcom/bcm2711.dtsi
index 4a379a1..22c7f15 100644
--- a/dts/upstream/src/arm/broadcom/bcm2711.dtsi
+++ b/dts/upstream/src/arm/broadcom/bcm2711.dtsi
@@ -604,6 +604,20 @@
};
};
+ xhci: usb@7e9c0000 {
+ compatible = "brcm,bcm2711-xhci", "brcm,xhci-brcm-v2";
+ reg = <0x0 0x7e9c0000 0x100000>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ interrupts = <GIC_SPI 176 IRQ_TYPE_LEVEL_HIGH>;
+ /* DWC2 and this IP block share the same USB PHY,
+ * enabling both at the same time results in lockups.
+ * So keep this node disabled and let the bootloader
+ * decide which interface should be enabled.
+ */
+ status = "disabled";
+ };
+
v3d: gpu@7ec00000 {
compatible = "brcm,2711-v3d";
reg = <0x0 0x7ec00000 0x4000>,
diff --git a/dts/upstream/src/arm/broadcom/bcm63138.dtsi b/dts/upstream/src/arm/broadcom/bcm63138.dtsi
index 93281c4..4ef0228 100644
--- a/dts/upstream/src/arm/broadcom/bcm63138.dtsi
+++ b/dts/upstream/src/arm/broadcom/bcm63138.dtsi
@@ -232,6 +232,12 @@
interrupt-names = "nand";
};
+ serial@4400 {
+ compatible = "brcm,bcm63138-hs-uart", "brcm,bcmbca-hs-uart";
+ reg = <0x4400 0x1e0>;
+ interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
+ };
+
bootlut: bootlut@8000 {
compatible = "brcm,bcm63138-bootlut";
reg = <0x8000 0x50>;
diff --git a/dts/upstream/src/arm/intel/ixp/intel-ixp42x-gateway-7001.dts b/dts/upstream/src/arm/intel/ixp/intel-ixp42x-gateway-7001.dts
index 4d70f6a..6d5e690 100644
--- a/dts/upstream/src/arm/intel/ixp/intel-ixp42x-gateway-7001.dts
+++ b/dts/upstream/src/arm/intel/ixp/intel-ixp42x-gateway-7001.dts
@@ -60,6 +60,8 @@
* We have slots (IDSEL) 1 and 2 with one assigned IRQ
* each handling all IRQs.
*/
+ #interrupt-cells = <1>;
+ interrupt-map-mask = <0xf800 0 0 7>;
interrupt-map =
/* IDSEL 1 */
<0x0800 0 0 1 &gpio0 11 IRQ_TYPE_LEVEL_LOW>, /* INT A on slot 1 is irq 11 */
diff --git a/dts/upstream/src/arm/intel/ixp/intel-ixp42x-goramo-multilink.dts b/dts/upstream/src/arm/intel/ixp/intel-ixp42x-goramo-multilink.dts
index 9ec0169..5f4c849 100644
--- a/dts/upstream/src/arm/intel/ixp/intel-ixp42x-goramo-multilink.dts
+++ b/dts/upstream/src/arm/intel/ixp/intel-ixp42x-goramo-multilink.dts
@@ -89,6 +89,8 @@
* The slots have Ethernet, Ethernet, NEC and MPCI.
* The IDSELs are 11, 12, 13, 14.
*/
+ #interrupt-cells = <1>;
+ interrupt-map-mask = <0xf800 0 0 7>;
interrupt-map =
/* IDSEL 11 - Ethernet A */
<0x5800 0 0 1 &gpio0 4 IRQ_TYPE_LEVEL_LOW>, /* INT A on slot 11 is irq 4 */
diff --git a/dts/upstream/src/arm/intel/ixp/intel-ixp42x-usrobotics-usr8200.dts b/dts/upstream/src/arm/intel/ixp/intel-ixp42x-usrobotics-usr8200.dts
index 90fd51b..2c89db3 100644
--- a/dts/upstream/src/arm/intel/ixp/intel-ixp42x-usrobotics-usr8200.dts
+++ b/dts/upstream/src/arm/intel/ixp/intel-ixp42x-usrobotics-usr8200.dts
@@ -165,6 +165,24 @@
#address-cells = <1>;
#size-cells = <0>;
+ /*
+ * PHY 0..4 are internal to the MV88E6060 switch but appear
+ * as independent devices.
+ */
+ phy0: ethernet-phy@0 {
+ reg = <0>;
+ };
+ phy1: ethernet-phy@1 {
+ reg = <1>;
+ };
+ phy2: ethernet-phy@2 {
+ reg = <2>;
+ };
+ phy3: ethernet-phy@3 {
+ reg = <3>;
+ };
+
+ /* Altima AMI101L used by the WAN port */
phy9: ethernet-phy@9 {
reg = <9>;
};
@@ -181,21 +199,25 @@
port@0 {
reg = <0>;
label = "lan1";
+ phy-handle = <&phy0>;
};
port@1 {
reg = <1>;
label = "lan2";
+ phy-handle = <&phy1>;
};
port@2 {
reg = <2>;
label = "lan3";
+ phy-handle = <&phy2>;
};
port@3 {
reg = <3>;
label = "lan4";
+ phy-handle = <&phy3>;
};
port@5 {
diff --git a/dts/upstream/src/arm/intel/socfpga/socfpga.dtsi b/dts/upstream/src/arm/intel/socfpga/socfpga.dtsi
index 4c1d140..35be141 100644
--- a/dts/upstream/src/arm/intel/socfpga/socfpga.dtsi
+++ b/dts/upstream/src/arm/intel/socfpga/socfpga.dtsi
@@ -768,7 +768,7 @@
status = "disabled";
};
- nand0: nand@ff900000 {
+ nand0: nand-controller@ff900000 {
#address-cells = <0x1>;
#size-cells = <0x0>;
compatible = "altr,socfpga-denali-nand";
diff --git a/dts/upstream/src/arm/intel/socfpga/socfpga_arria10.dtsi b/dts/upstream/src/arm/intel/socfpga/socfpga_arria10.dtsi
index f36063c..6b6e775 100644
--- a/dts/upstream/src/arm/intel/socfpga/socfpga_arria10.dtsi
+++ b/dts/upstream/src/arm/intel/socfpga/socfpga_arria10.dtsi
@@ -669,7 +669,7 @@
status = "disabled";
};
- nand: nand@ffb90000 {
+ nand: nand-controller@ffb90000 {
#address-cells = <1>;
#size-cells = <0>;
compatible = "altr,socfpga-denali-nand";
diff --git a/dts/upstream/src/arm/intel/socfpga/socfpga_arria10_socdk_qspi.dts b/dts/upstream/src/arm/intel/socfpga/socfpga_arria10_socdk_qspi.dts
index 11ccdc6..0434f1c 100644
--- a/dts/upstream/src/arm/intel/socfpga/socfpga_arria10_socdk_qspi.dts
+++ b/dts/upstream/src/arm/intel/socfpga/socfpga_arria10_socdk_qspi.dts
@@ -17,8 +17,6 @@
spi-max-frequency = <100000000>;
m25p,fast-read;
- cdns,page-size = <256>;
- cdns,block-size = <16>;
cdns,read-delay = <3>;
cdns,tshsl-ns = <50>;
cdns,tsd2d-ns = <50>;
diff --git a/dts/upstream/src/arm/intel/socfpga/socfpga_arria5_socdk.dts b/dts/upstream/src/arm/intel/socfpga/socfpga_arria5_socdk.dts
index c483857..7342f59 100644
--- a/dts/upstream/src/arm/intel/socfpga/socfpga_arria5_socdk.dts
+++ b/dts/upstream/src/arm/intel/socfpga/socfpga_arria5_socdk.dts
@@ -124,8 +124,6 @@
spi-max-frequency = <100000000>;
m25p,fast-read;
- cdns,page-size = <256>;
- cdns,block-size = <16>;
cdns,read-delay = <4>;
cdns,tshsl-ns = <50>;
cdns,tsd2d-ns = <50>;
diff --git a/dts/upstream/src/arm/intel/socfpga/socfpga_cyclone5_socdk.dts b/dts/upstream/src/arm/intel/socfpga/socfpga_cyclone5_socdk.dts
index c7f5fa0..d37a982 100644
--- a/dts/upstream/src/arm/intel/socfpga/socfpga_cyclone5_socdk.dts
+++ b/dts/upstream/src/arm/intel/socfpga/socfpga_cyclone5_socdk.dts
@@ -129,8 +129,6 @@
spi-max-frequency = <100000000>;
m25p,fast-read;
- cdns,page-size = <256>;
- cdns,block-size = <16>;
cdns,read-delay = <4>;
cdns,tshsl-ns = <50>;
cdns,tsd2d-ns = <50>;
diff --git a/dts/upstream/src/arm/intel/socfpga/socfpga_cyclone5_sockit.dts b/dts/upstream/src/arm/intel/socfpga/socfpga_cyclone5_sockit.dts
index 3dd99c7..9e4db74 100644
--- a/dts/upstream/src/arm/intel/socfpga/socfpga_cyclone5_sockit.dts
+++ b/dts/upstream/src/arm/intel/socfpga/socfpga_cyclone5_sockit.dts
@@ -174,8 +174,6 @@
spi-max-frequency = <100000000>;
m25p,fast-read;
- cdns,page-size = <256>;
- cdns,block-size = <16>;
cdns,read-delay = <4>;
cdns,tshsl-ns = <50>;
cdns,tsd2d-ns = <50>;
diff --git a/dts/upstream/src/arm/intel/socfpga/socfpga_cyclone5_sodia.dts b/dts/upstream/src/arm/intel/socfpga/socfpga_cyclone5_sodia.dts
index 2564671..ce0d651 100644
--- a/dts/upstream/src/arm/intel/socfpga/socfpga_cyclone5_sodia.dts
+++ b/dts/upstream/src/arm/intel/socfpga/socfpga_cyclone5_sodia.dts
@@ -121,8 +121,6 @@
spi-max-frequency = <100000000>;
m25p,fast-read;
- cdns,page-size = <256>;
- cdns,block-size = <16>;
cdns,read-delay = <4>;
cdns,tshsl-ns = <50>;
cdns,tsd2d-ns = <50>;
diff --git a/dts/upstream/src/arm/intel/socfpga/socfpga_cyclone5_vining_fpga.dts b/dts/upstream/src/arm/intel/socfpga/socfpga_cyclone5_vining_fpga.dts
index e0630b0..65f390b 100644
--- a/dts/upstream/src/arm/intel/socfpga/socfpga_cyclone5_vining_fpga.dts
+++ b/dts/upstream/src/arm/intel/socfpga/socfpga_cyclone5_vining_fpga.dts
@@ -229,8 +229,6 @@
spi-max-frequency = <100000000>;
m25p,fast-read;
- cdns,page-size = <256>;
- cdns,block-size = <16>;
cdns,read-delay = <4>;
cdns,tshsl-ns = <50>;
cdns,tsd2d-ns = <50>;
@@ -246,8 +244,6 @@
spi-max-frequency = <100000000>;
m25p,fast-read;
- cdns,page-size = <256>;
- cdns,block-size = <16>;
cdns,read-delay = <4>;
cdns,tshsl-ns = <50>;
cdns,tsd2d-ns = <50>;
diff --git a/dts/upstream/src/arm/marvell/armada-370-rd.dts b/dts/upstream/src/arm/marvell/armada-370-rd.dts
index b459a67..f23f6b3 100644
--- a/dts/upstream/src/arm/marvell/armada-370-rd.dts
+++ b/dts/upstream/src/arm/marvell/armada-370-rd.dts
@@ -95,7 +95,7 @@
gpio-fan {
compatible = "gpio-fan";
gpios = <&gpio0 8 GPIO_ACTIVE_HIGH>;
- gpio-fan,speed-map = <0 0 3000 1>;
+ gpio-fan,speed-map = <0 0>, <3000 1>;
pinctrl-0 = <&fan_pins>;
pinctrl-names = "default";
};
@@ -149,39 +149,37 @@
};
};
- switch: switch@10 {
+ switch: ethernet-switch@10 {
compatible = "marvell,mv88e6085";
- #address-cells = <1>;
- #size-cells = <0>;
reg = <0x10>;
interrupt-controller;
#interrupt-cells = <2>;
- ports {
+ ethernet-ports {
#address-cells = <1>;
#size-cells = <0>;
- port@0 {
+ ethernet-port@0 {
reg = <0>;
label = "lan0";
};
- port@1 {
+ ethernet-port@1 {
reg = <1>;
label = "lan1";
};
- port@2 {
+ ethernet-port@2 {
reg = <2>;
label = "lan2";
};
- port@3 {
+ ethernet-port@3 {
reg = <3>;
label = "lan3";
};
- port@5 {
+ ethernet-port@5 {
reg = <5>;
ethernet = <ð1>;
phy-mode = "rgmii-id";
@@ -196,25 +194,25 @@
#address-cells = <1>;
#size-cells = <0>;
- switchphy0: switchphy@0 {
+ switchphy0: ethernet-phy@0 {
reg = <0>;
interrupt-parent = <&switch>;
interrupts = <0 IRQ_TYPE_LEVEL_HIGH>;
};
- switchphy1: switchphy@1 {
+ switchphy1: ethernet-phy@1 {
reg = <1>;
interrupt-parent = <&switch>;
interrupts = <1 IRQ_TYPE_LEVEL_HIGH>;
};
- switchphy2: switchphy@2 {
+ switchphy2: ethernet-phy@2 {
reg = <2>;
interrupt-parent = <&switch>;
interrupts = <2 IRQ_TYPE_LEVEL_HIGH>;
};
- switchphy3: switchphy@3 {
+ switchphy3: ethernet-phy@3 {
reg = <3>;
interrupt-parent = <&switch>;
interrupts = <3 IRQ_TYPE_LEVEL_HIGH>;
diff --git a/dts/upstream/src/arm/marvell/armada-370-seagate-nas-2bay.dts b/dts/upstream/src/arm/marvell/armada-370-seagate-nas-2bay.dts
index 8dd242e..6ec3dd3 100644
--- a/dts/upstream/src/arm/marvell/armada-370-seagate-nas-2bay.dts
+++ b/dts/upstream/src/arm/marvell/armada-370-seagate-nas-2bay.dts
@@ -25,9 +25,9 @@
gpio-fan {
gpio-fan,speed-map =
- < 0 3
- 950 2
- 1400 1
- 1800 0>;
+ < 0 3>,
+ < 950 2>,
+ <1400 1>,
+ <1800 0>;
};
};
diff --git a/dts/upstream/src/arm/marvell/armada-370-seagate-nas-4bay.dts b/dts/upstream/src/arm/marvell/armada-370-seagate-nas-4bay.dts
index 370ca9c..3011578 100644
--- a/dts/upstream/src/arm/marvell/armada-370-seagate-nas-4bay.dts
+++ b/dts/upstream/src/arm/marvell/armada-370-seagate-nas-4bay.dts
@@ -106,10 +106,10 @@
gpio-fan {
gpio-fan,speed-map =
- < 0 3
- 800 2
- 1050 1
- 1300 0>;
+ < 0 3>,
+ < 800 2>,
+ <1050 1>,
+ <1300 0>;
};
};
diff --git a/dts/upstream/src/arm/marvell/armada-370-synology-ds213j.dts b/dts/upstream/src/arm/marvell/armada-370-synology-ds213j.dts
index b07d11d..02599a3 100644
--- a/dts/upstream/src/arm/marvell/armada-370-synology-ds213j.dts
+++ b/dts/upstream/src/arm/marvell/armada-370-synology-ds213j.dts
@@ -113,14 +113,14 @@
&gpio2 0 GPIO_ACTIVE_HIGH
&gpio2 1 GPIO_ACTIVE_HIGH>;
alarm-gpios = <&gpio1 6 GPIO_ACTIVE_HIGH>;
- gpio-fan,speed-map = < 0 0
- 1000 1
- 1150 2
- 1350 4
- 1500 3
- 1650 5
- 1750 6
- 1900 7 >;
+ gpio-fan,speed-map = < 0 0>,
+ <1000 1>,
+ <1150 2>,
+ <1350 4>,
+ <1500 3>,
+ <1650 5>,
+ <1750 6>,
+ <1900 7>;
};
gpio-leds {
diff --git a/dts/upstream/src/arm/marvell/armada-381-netgear-gs110emx.dts b/dts/upstream/src/arm/marvell/armada-381-netgear-gs110emx.dts
index f4c4b21..5baf83e 100644
--- a/dts/upstream/src/arm/marvell/armada-381-netgear-gs110emx.dts
+++ b/dts/upstream/src/arm/marvell/armada-381-netgear-gs110emx.dts
@@ -77,51 +77,49 @@
pinctrl-0 = <&mdio_pins>;
status = "okay";
- switch@0 {
+ ethernet-switch@0 {
compatible = "marvell,mv88e6190";
- #address-cells = <1>;
#interrupt-cells = <2>;
interrupt-controller;
interrupt-parent = <&gpio1>;
interrupts = <7 IRQ_TYPE_LEVEL_LOW>;
pinctrl-0 = <&switch_interrupt_pins>;
pinctrl-names = "default";
- #size-cells = <0>;
reg = <0>;
mdio {
#address-cells = <1>;
#size-cells = <0>;
- switch0phy1: switch0phy1@1 {
+ switch0phy1: ethernet-phy@1 {
reg = <0x1>;
};
- switch0phy2: switch0phy2@2 {
+ switch0phy2: ethernet-phy@2 {
reg = <0x2>;
};
- switch0phy3: switch0phy3@3 {
+ switch0phy3: ethernet-phy@3 {
reg = <0x3>;
};
- switch0phy4: switch0phy4@4 {
+ switch0phy4: ethernet-phy@4 {
reg = <0x4>;
};
- switch0phy5: switch0phy5@5 {
+ switch0phy5: ethernet-phy@5 {
reg = <0x5>;
};
- switch0phy6: switch0phy6@6 {
+ switch0phy6: ethernet-phy@6 {
reg = <0x6>;
};
- switch0phy7: switch0phy7@7 {
+ switch0phy7: ethernet-phy@7 {
reg = <0x7>;
};
- switch0phy8: switch0phy8@8 {
+ switch0phy8: ethernet-phy@8 {
reg = <0x8>;
};
};
@@ -142,11 +140,11 @@
};
};
- ports {
+ ethernet-ports {
#address-cells = <1>;
#size-cells = <0>;
- port@0 {
+ ethernet-port@0 {
ethernet = <ð0>;
phy-mode = "rgmii";
reg = <0>;
@@ -158,55 +156,55 @@
};
};
- port@1 {
+ ethernet-port@1 {
label = "lan1";
phy-handle = <&switch0phy1>;
reg = <1>;
};
- port@2 {
+ ethernet-port@2 {
label = "lan2";
phy-handle = <&switch0phy2>;
reg = <2>;
};
- port@3 {
+ ethernet-port@3 {
label = "lan3";
phy-handle = <&switch0phy3>;
reg = <3>;
};
- port@4 {
+ ethernet-port@4 {
label = "lan4";
phy-handle = <&switch0phy4>;
reg = <4>;
};
- port@5 {
+ ethernet-port@5 {
label = "lan5";
phy-handle = <&switch0phy5>;
reg = <5>;
};
- port@6 {
+ ethernet-port@6 {
label = "lan6";
phy-handle = <&switch0phy6>;
reg = <6>;
};
- port@7 {
+ ethernet-port@7 {
label = "lan7";
phy-handle = <&switch0phy7>;
reg = <7>;
};
- port@8 {
+ ethernet-port@8 {
label = "lan8";
phy-handle = <&switch0phy8>;
reg = <8>;
};
- port@9 {
+ ethernet-port@9 {
/* 88X3310P external phy */
label = "lan9";
phy-handle = <&phy1>;
@@ -214,7 +212,7 @@
reg = <9>;
};
- port@a {
+ ethernet-port@a {
/* 88X3310P external phy */
label = "lan10";
phy-handle = <&phy2>;
diff --git a/dts/upstream/src/arm/marvell/armada-385-clearfog-gtr-l8.dts b/dts/upstream/src/arm/marvell/armada-385-clearfog-gtr-l8.dts
index 1990f7d..1707d1b 100644
--- a/dts/upstream/src/arm/marvell/armada-385-clearfog-gtr-l8.dts
+++ b/dts/upstream/src/arm/marvell/armada-385-clearfog-gtr-l8.dts
@@ -7,66 +7,66 @@
};
&mdio {
- switch0: switch0@4 {
+ switch0: ethernet-switch@4 {
compatible = "marvell,mv88e6190";
reg = <4>;
pinctrl-names = "default";
pinctrl-0 = <&cf_gtr_switch_reset_pins>;
reset-gpios = <&gpio0 18 GPIO_ACTIVE_LOW>;
- ports {
+ ethernet-ports {
#address-cells = <1>;
#size-cells = <0>;
- port@1 {
+ ethernet-port@1 {
reg = <1>;
label = "lan8";
phy-handle = <&switch0phy0>;
};
- port@2 {
+ ethernet-port@2 {
reg = <2>;
label = "lan7";
phy-handle = <&switch0phy1>;
};
- port@3 {
+ ethernet-port@3 {
reg = <3>;
label = "lan6";
phy-handle = <&switch0phy2>;
};
- port@4 {
+ ethernet-port@4 {
reg = <4>;
label = "lan5";
phy-handle = <&switch0phy3>;
};
- port@5 {
+ ethernet-port@5 {
reg = <5>;
label = "lan4";
phy-handle = <&switch0phy4>;
};
- port@6 {
+ ethernet-port@6 {
reg = <6>;
label = "lan3";
phy-handle = <&switch0phy5>;
};
- port@7 {
+ ethernet-port@7 {
reg = <7>;
label = "lan2";
phy-handle = <&switch0phy6>;
};
- port@8 {
+ ethernet-port@8 {
reg = <8>;
label = "lan1";
phy-handle = <&switch0phy7>;
};
- port@10 {
+ ethernet-port@10 {
reg = <10>;
phy-mode = "2500base-x";
@@ -83,35 +83,35 @@
#address-cells = <1>;
#size-cells = <0>;
- switch0phy0: switch0phy0@1 {
+ switch0phy0: ethernet-phy@1 {
reg = <0x1>;
};
- switch0phy1: switch0phy1@2 {
+ switch0phy1: ethernet-phy@2 {
reg = <0x2>;
};
- switch0phy2: switch0phy2@3 {
+ switch0phy2: ethernet-phy@3 {
reg = <0x3>;
};
- switch0phy3: switch0phy3@4 {
+ switch0phy3: ethernet-phy@4 {
reg = <0x4>;
};
- switch0phy4: switch0phy4@5 {
+ switch0phy4: ethernet-phy@5 {
reg = <0x5>;
};
- switch0phy5: switch0phy5@6 {
+ switch0phy5: ethernet-phy@6 {
reg = <0x6>;
};
- switch0phy6: switch0phy6@7 {
+ switch0phy6: ethernet-phy@7 {
reg = <0x7>;
};
- switch0phy7: switch0phy7@8 {
+ switch0phy7: ethernet-phy@8 {
reg = <0x8>;
};
};
diff --git a/dts/upstream/src/arm/marvell/armada-385-clearfog-gtr-s4.dts b/dts/upstream/src/arm/marvell/armada-385-clearfog-gtr-s4.dts
index b795ad5..a7678a7 100644
--- a/dts/upstream/src/arm/marvell/armada-385-clearfog-gtr-s4.dts
+++ b/dts/upstream/src/arm/marvell/armada-385-clearfog-gtr-s4.dts
@@ -11,42 +11,42 @@
};
&mdio {
- switch0: switch0@4 {
+ switch0: ethernet-switch@4 {
compatible = "marvell,mv88e6085";
reg = <4>;
pinctrl-names = "default";
pinctrl-0 = <&cf_gtr_switch_reset_pins>;
reset-gpios = <&gpio0 18 GPIO_ACTIVE_LOW>;
- ports {
+ ethernet-ports {
#address-cells = <1>;
#size-cells = <0>;
- port@1 {
+ ethernet-port@1 {
reg = <1>;
label = "lan2";
phy-handle = <&switch0phy0>;
};
- port@2 {
+ ethernet-port@2 {
reg = <2>;
label = "lan1";
phy-handle = <&switch0phy1>;
};
- port@3 {
+ ethernet-port@3 {
reg = <3>;
label = "lan4";
phy-handle = <&switch0phy2>;
};
- port@4 {
+ ethernet-port@4 {
reg = <4>;
label = "lan3";
phy-handle = <&switch0phy3>;
};
- port@5 {
+ ethernet-port@5 {
reg = <5>;
phy-mode = "2500base-x";
ethernet = <ð1>;
@@ -63,19 +63,19 @@
#address-cells = <1>;
#size-cells = <0>;
- switch0phy0: switch0phy0@11 {
+ switch0phy0: ethernet-phy@11 {
reg = <0x11>;
};
- switch0phy1: switch0phy1@12 {
+ switch0phy1: ethernet-phy@12 {
reg = <0x12>;
};
- switch0phy2: switch0phy2@13 {
+ switch0phy2: ethernet-phy@13 {
reg = <0x13>;
};
- switch0phy3: switch0phy3@14 {
+ switch0phy3: ethernet-phy@14 {
reg = <0x14>;
};
};
diff --git a/dts/upstream/src/arm/marvell/armada-385-linksys.dtsi b/dts/upstream/src/arm/marvell/armada-385-linksys.dtsi
index fc8216f..4116ed6 100644
--- a/dts/upstream/src/arm/marvell/armada-385-linksys.dtsi
+++ b/dts/upstream/src/arm/marvell/armada-385-linksys.dtsi
@@ -158,42 +158,40 @@
&mdio {
status = "okay";
- switch@0 {
+ ethernet-switch@0 {
compatible = "marvell,mv88e6085";
- #address-cells = <1>;
- #size-cells = <0>;
reg = <0>;
- ports {
+ ethernet-ports {
#address-cells = <1>;
#size-cells = <0>;
- port@0 {
+ ethernet-port@0 {
reg = <0>;
label = "lan4";
};
- port@1 {
+ ethernet-port@1 {
reg = <1>;
label = "lan3";
};
- port@2 {
+ ethernet-port@2 {
reg = <2>;
label = "lan2";
};
- port@3 {
+ ethernet-port@3 {
reg = <3>;
label = "lan1";
};
- port@4 {
+ ethernet-port@4 {
reg = <4>;
label = "wan";
};
- port@5 {
+ ethernet-port@5 {
reg = <5>;
phy-mode = "sgmii";
ethernet = <ð2>;
diff --git a/dts/upstream/src/arm/marvell/armada-385-synology-ds116.dts b/dts/upstream/src/arm/marvell/armada-385-synology-ds116.dts
index ea91ff9..6caa5c5 100644
--- a/dts/upstream/src/arm/marvell/armada-385-synology-ds116.dts
+++ b/dts/upstream/src/arm/marvell/armada-385-synology-ds116.dts
@@ -131,14 +131,14 @@
gpios = <&gpio1 18 GPIO_ACTIVE_HIGH>,
<&gpio1 17 GPIO_ACTIVE_HIGH>,
<&gpio1 16 GPIO_ACTIVE_HIGH>;
- gpio-fan,speed-map = < 0 0
- 1500 1
- 2500 2
- 3000 3
- 3400 4
- 3700 5
- 3900 6
- 4000 7>;
+ gpio-fan,speed-map = < 0 0>,
+ <1500 1>,
+ <2500 2>,
+ <3000 3>,
+ <3400 4>,
+ <3700 5>,
+ <3900 6>,
+ <4000 7>;
#cooling-cells = <2>;
};
diff --git a/dts/upstream/src/arm/marvell/armada-385-turris-omnia.dts b/dts/upstream/src/arm/marvell/armada-385-turris-omnia.dts
index 2d8d319..7b755bb 100644
--- a/dts/upstream/src/arm/marvell/armada-385-turris-omnia.dts
+++ b/dts/upstream/src/arm/marvell/armada-385-turris-omnia.dts
@@ -435,12 +435,10 @@
};
/* Switch MV88E6176 at address 0x10 */
- switch@10 {
+ ethernet-switch@10 {
pinctrl-names = "default";
pinctrl-0 = <&swint_pins>;
compatible = "marvell,mv88e6085";
- #address-cells = <1>;
- #size-cells = <0>;
dsa,member = <0 0>;
reg = <0x10>;
@@ -448,36 +446,36 @@
interrupt-parent = <&gpio1>;
interrupts = <13 IRQ_TYPE_LEVEL_LOW>;
- ports {
+ ethernet-ports {
#address-cells = <1>;
#size-cells = <0>;
- ports@0 {
+ ethernet-port@0 {
reg = <0>;
label = "lan0";
};
- ports@1 {
+ ethernet-port@1 {
reg = <1>;
label = "lan1";
};
- ports@2 {
+ ethernet-port@2 {
reg = <2>;
label = "lan2";
};
- ports@3 {
+ ethernet-port@3 {
reg = <3>;
label = "lan3";
};
- ports@4 {
+ ethernet-port@4 {
reg = <4>;
label = "lan4";
};
- ports@5 {
+ ethernet-port@5 {
reg = <5>;
ethernet = <ð1>;
phy-mode = "rgmii-id";
@@ -488,7 +486,7 @@
};
};
- ports@6 {
+ ethernet-port@6 {
reg = <6>;
ethernet = <ð0>;
phy-mode = "rgmii-id";
diff --git a/dts/upstream/src/arm/marvell/armada-388-clearfog.dts b/dts/upstream/src/arm/marvell/armada-388-clearfog.dts
index 32c569d..3290cca 100644
--- a/dts/upstream/src/arm/marvell/armada-388-clearfog.dts
+++ b/dts/upstream/src/arm/marvell/armada-388-clearfog.dts
@@ -92,44 +92,42 @@
&mdio {
status = "okay";
- switch@4 {
+ ethernet-switch@4 {
compatible = "marvell,mv88e6085";
- #address-cells = <1>;
- #size-cells = <0>;
reg = <4>;
pinctrl-0 = <&clearfog_dsa0_clk_pins &clearfog_dsa0_pins>;
pinctrl-names = "default";
- ports {
+ ethernet-ports {
#address-cells = <1>;
#size-cells = <0>;
- port@0 {
+ ethernet-port@0 {
reg = <0>;
label = "lan5";
};
- port@1 {
+ ethernet-port@1 {
reg = <1>;
label = "lan4";
};
- port@2 {
+ ethernet-port@2 {
reg = <2>;
label = "lan3";
};
- port@3 {
+ ethernet-port@3 {
reg = <3>;
label = "lan2";
};
- port@4 {
+ ethernet-port@4 {
reg = <4>;
label = "lan1";
};
- port@5 {
+ ethernet-port@5 {
reg = <5>;
ethernet = <ð1>;
phy-mode = "1000base-x";
@@ -140,7 +138,7 @@
};
};
- port@6 {
+ ethernet-port@6 {
/* 88E1512 external phy */
reg = <6>;
label = "lan6";
diff --git a/dts/upstream/src/arm/marvell/armada-388-gp.dts b/dts/upstream/src/arm/marvell/armada-388-gp.dts
index e2ba505..1de0a17 100644
--- a/dts/upstream/src/arm/marvell/armada-388-gp.dts
+++ b/dts/upstream/src/arm/marvell/armada-388-gp.dts
@@ -237,8 +237,8 @@
gpio-fan {
compatible = "gpio-fan";
gpios = <&expander1 3 GPIO_ACTIVE_HIGH>;
- gpio-fan,speed-map = < 0 0
- 3000 1>;
+ gpio-fan,speed-map = < 0 0>,
+ <3000 1>;
};
};
diff --git a/dts/upstream/src/arm/marvell/armada-xp-linksys-mamba.dts b/dts/upstream/src/arm/marvell/armada-xp-linksys-mamba.dts
index 7a0614f..ea859f7 100644
--- a/dts/upstream/src/arm/marvell/armada-xp-linksys-mamba.dts
+++ b/dts/upstream/src/arm/marvell/armada-xp-linksys-mamba.dts
@@ -265,42 +265,40 @@
&mdio {
status = "okay";
- switch@0 {
+ ethernet-switch@0 {
compatible = "marvell,mv88e6085";
- #address-cells = <1>;
- #size-cells = <0>;
reg = <0>;
- ports {
+ ethernet-ports {
#address-cells = <1>;
#size-cells = <0>;
- port@0 {
+ ethernet-port@0 {
reg = <0>;
label = "lan4";
};
- port@1 {
+ ethernet-port@1 {
reg = <1>;
label = "lan3";
};
- port@2 {
+ ethernet-port@2 {
reg = <2>;
label = "lan2";
};
- port@3 {
+ ethernet-port@3 {
reg = <3>;
label = "lan1";
};
- port@4 {
+ ethernet-port@4 {
reg = <4>;
label = "internet";
};
- port@5 {
+ ethernet-port@5 {
reg = <5>;
phy-mode = "rgmii-id";
ethernet = <ð0>;
diff --git a/dts/upstream/src/arm/marvell/kirkwood-dnskw.dtsi b/dts/upstream/src/arm/marvell/kirkwood-dnskw.dtsi
index eb91746..0738eb6 100644
--- a/dts/upstream/src/arm/marvell/kirkwood-dnskw.dtsi
+++ b/dts/upstream/src/arm/marvell/kirkwood-dnskw.dtsi
@@ -38,9 +38,9 @@
pinctrl-names = "default";
gpios = <&gpio1 14 GPIO_ACTIVE_HIGH
&gpio1 13 GPIO_ACTIVE_HIGH>;
- gpio-fan,speed-map = <0 0
- 3000 1
- 6000 2>;
+ gpio-fan,speed-map = <0 0>,
+ <3000 1>,
+ <6000 2>;
};
gpio_poweroff {
diff --git a/dts/upstream/src/arm/marvell/kirkwood-l-50.dts b/dts/upstream/src/arm/marvell/kirkwood-l-50.dts
index dffb9f8..c841eb8 100644
--- a/dts/upstream/src/arm/marvell/kirkwood-l-50.dts
+++ b/dts/upstream/src/arm/marvell/kirkwood-l-50.dts
@@ -65,6 +65,7 @@
gpio2: gpio-expander@20 {
#gpio-cells = <2>;
#interrupt-cells = <2>;
+ interrupt-controller;
compatible = "semtech,sx1505q";
reg = <0x20>;
@@ -79,6 +80,7 @@
gpio3: gpio-expander@21 {
#gpio-cells = <2>;
#interrupt-cells = <2>;
+ interrupt-controller;
compatible = "semtech,sx1505q";
reg = <0x21>;
diff --git a/dts/upstream/src/arm/marvell/kirkwood-linkstation-6282.dtsi b/dts/upstream/src/arm/marvell/kirkwood-linkstation-6282.dtsi
index 377b6e9..dfac204 100644
--- a/dts/upstream/src/arm/marvell/kirkwood-linkstation-6282.dtsi
+++ b/dts/upstream/src/arm/marvell/kirkwood-linkstation-6282.dtsi
@@ -118,10 +118,11 @@
gpios = <&gpio0 17 GPIO_ACTIVE_LOW
&gpio0 16 GPIO_ACTIVE_LOW>;
- gpio-fan,speed-map = <0 3
- 1500 2
- 3250 1
- 5000 0>;
+ gpio-fan,speed-map =
+ < 0 3>,
+ <1500 2>,
+ <3250 1>,
+ <5000 0>;
alarm-gpios = <&gpio1 11 GPIO_ACTIVE_HIGH>;
};
diff --git a/dts/upstream/src/arm/marvell/kirkwood-linkstation-lswxl.dts b/dts/upstream/src/arm/marvell/kirkwood-linkstation-lswxl.dts
index c6024b5..0425df8 100644
--- a/dts/upstream/src/arm/marvell/kirkwood-linkstation-lswxl.dts
+++ b/dts/upstream/src/arm/marvell/kirkwood-linkstation-lswxl.dts
@@ -69,10 +69,11 @@
gpios = <&gpio1 16 GPIO_ACTIVE_LOW
&gpio1 15 GPIO_ACTIVE_LOW>;
- gpio-fan,speed-map = <0 3
- 1500 2
- 3250 1
- 5000 0>;
+ gpio-fan,speed-map =
+ < 0 3>,
+ <1500 2>,
+ <3250 1>,
+ <5000 0>;
alarm-gpios = <&gpio1 8 GPIO_ACTIVE_HIGH>;
};
diff --git a/dts/upstream/src/arm/marvell/kirkwood-lsxl.dtsi b/dts/upstream/src/arm/marvell/kirkwood-lsxl.dtsi
index 88b70ba..f80af24 100644
--- a/dts/upstream/src/arm/marvell/kirkwood-lsxl.dtsi
+++ b/dts/upstream/src/arm/marvell/kirkwood-lsxl.dtsi
@@ -172,10 +172,11 @@
pinctrl-names = "default";
gpios = <&gpio0 19 GPIO_ACTIVE_LOW
&gpio0 18 GPIO_ACTIVE_LOW>;
- gpio-fan,speed-map = <0 3
- 1500 2
- 3250 1
- 5000 0>;
+ gpio-fan,speed-map =
+ <0 3>,
+ <1500 2>,
+ <3250 1>,
+ <5000 0>;
alarm-gpios = <&gpio1 8 GPIO_ACTIVE_HIGH>;
};
diff --git a/dts/upstream/src/arm/marvell/kirkwood-ns2max.dts b/dts/upstream/src/arm/marvell/kirkwood-ns2max.dts
index c0a087e..044958b 100644
--- a/dts/upstream/src/arm/marvell/kirkwood-ns2max.dts
+++ b/dts/upstream/src/arm/marvell/kirkwood-ns2max.dts
@@ -29,15 +29,15 @@
&gpio1 1 GPIO_ACTIVE_LOW
&gpio0 23 GPIO_ACTIVE_LOW>;
gpio-fan,speed-map =
- < 0 0
- 1500 15
- 1700 14
- 1800 13
- 2100 12
- 3100 11
- 3300 10
- 4300 9
- 5500 8>;
+ < 0 0>,
+ <1500 15>,
+ <1700 14>,
+ <1800 13>,
+ <2100 12>,
+ <3100 11>,
+ <3300 10>,
+ <4300 9>,
+ <5500 8>;
alarm-gpios = <&gpio0 25 GPIO_ACTIVE_LOW>;
};
diff --git a/dts/upstream/src/arm/marvell/kirkwood-ns2mini.dts b/dts/upstream/src/arm/marvell/kirkwood-ns2mini.dts
index 5b9fa14..3fbe008 100644
--- a/dts/upstream/src/arm/marvell/kirkwood-ns2mini.dts
+++ b/dts/upstream/src/arm/marvell/kirkwood-ns2mini.dts
@@ -30,15 +30,15 @@
&gpio1 1 GPIO_ACTIVE_LOW
&gpio0 23 GPIO_ACTIVE_LOW>;
gpio-fan,speed-map =
- < 0 0
- 3000 15
- 3180 14
- 4140 13
- 4570 12
- 6760 11
- 7140 10
- 7980 9
- 9200 8>;
+ < 0 0>,
+ <3000 15>,
+ <3180 14>,
+ <4140 13>,
+ <4570 12>,
+ <6760 11>,
+ <7140 10>,
+ <7980 9>,
+ <9200 8>;
alarm-gpios = <&gpio0 25 GPIO_ACTIVE_LOW>;
};
diff --git a/dts/upstream/src/arm/marvell/kirkwood-synology.dtsi b/dts/upstream/src/arm/marvell/kirkwood-synology.dtsi
index 9b66660..20964eb 100644
--- a/dts/upstream/src/arm/marvell/kirkwood-synology.dtsi
+++ b/dts/upstream/src/arm/marvell/kirkwood-synology.dtsi
@@ -286,14 +286,15 @@
gpios = <&gpio1 0 GPIO_ACTIVE_HIGH
&gpio1 1 GPIO_ACTIVE_HIGH
&gpio1 2 GPIO_ACTIVE_HIGH>;
- gpio-fan,speed-map = < 0 0
- 2200 1
- 2500 2
- 3000 4
- 3300 3
- 3700 5
- 3800 6
- 4200 7 >;
+ gpio-fan,speed-map =
+ < 0 0>,
+ <2200 1>,
+ <2500 2>,
+ <3000 4>,
+ <3300 3>,
+ <3700 5>,
+ <3800 6>,
+ <4200 7>;
};
gpio-fan-150-15-18 {
@@ -306,14 +307,15 @@
&gpio0 16 GPIO_ACTIVE_HIGH
&gpio0 17 GPIO_ACTIVE_HIGH>;
alarm-gpios = <&gpio0 18 GPIO_ACTIVE_HIGH>;
- gpio-fan,speed-map = < 0 0
- 2200 1
- 2500 2
- 3000 4
- 3300 3
- 3700 5
- 3800 6
- 4200 7 >;
+ gpio-fan,speed-map =
+ < 0 0>,
+ <2200 1>,
+ <2500 2>,
+ <3000 4>,
+ <3300 3>,
+ <3700 5>,
+ <3800 6>,
+ <4200 7>;
};
gpio-fan-100-32-35 {
@@ -326,14 +328,15 @@
&gpio1 1 GPIO_ACTIVE_HIGH
&gpio1 2 GPIO_ACTIVE_HIGH>;
alarm-gpios = <&gpio1 3 GPIO_ACTIVE_HIGH>;
- gpio-fan,speed-map = < 0 0
- 2500 1
- 3100 2
- 3800 3
- 4600 4
- 4800 5
- 4900 6
- 5000 7 >;
+ gpio-fan,speed-map =
+ < 0 0>,
+ <2500 1>,
+ <3100 2>,
+ <3800 3>,
+ <4600 4>,
+ <4800 5>,
+ <4900 6>,
+ <5000 7>;
};
gpio-fan-100-15-18 {
@@ -346,14 +349,15 @@
&gpio0 16 GPIO_ACTIVE_HIGH
&gpio0 17 GPIO_ACTIVE_HIGH>;
alarm-gpios = <&gpio0 18 GPIO_ACTIVE_HIGH>;
- gpio-fan,speed-map = < 0 0
- 2500 1
- 3100 2
- 3800 3
- 4600 4
- 4800 5
- 4900 6
- 5000 7 >;
+ gpio-fan,speed-map =
+ < 0 0>,
+ <2500 1>,
+ <3100 2>,
+ <3800 3>,
+ <4600 4>,
+ <4800 5>,
+ <4900 6>,
+ <5000 7>;
};
gpio-fan-100-15-35-1 {
@@ -366,14 +370,15 @@
&gpio0 16 GPIO_ACTIVE_HIGH
&gpio0 17 GPIO_ACTIVE_HIGH>;
alarm-gpios = <&gpio1 3 GPIO_ACTIVE_HIGH>;
- gpio-fan,speed-map = < 0 0
- 2500 1
- 3100 2
- 3800 3
- 4600 4
- 4800 5
- 4900 6
- 5000 7 >;
+ gpio-fan,speed-map =
+ < 0 0>,
+ <2500 1>,
+ <3100 2>,
+ <3800 3>,
+ <4600 4>,
+ <4800 5>,
+ <4900 6>,
+ <5000 7>;
};
gpio-fan-100-15-35-3 {
@@ -388,14 +393,15 @@
alarm-gpios = <&gpio1 3 GPIO_ACTIVE_HIGH
&gpio1 12 GPIO_ACTIVE_HIGH
&gpio1 13 GPIO_ACTIVE_HIGH>;
- gpio-fan,speed-map = < 0 0
- 2500 1
- 3100 2
- 3800 3
- 4600 4
- 4800 5
- 4900 6
- 5000 7 >;
+ gpio-fan,speed-map =
+ < 0 0>,
+ <2500 1>,
+ <3100 2>,
+ <3800 3>,
+ <4600 4>,
+ <4800 5>,
+ <4900 6>,
+ <5000 7>;
};
gpio-leds-alarm-12 {
diff --git a/dts/upstream/src/arm/marvell/mvebu-linkstation-fan.dtsi b/dts/upstream/src/arm/marvell/mvebu-linkstation-fan.dtsi
index e172029..a260c42 100644
--- a/dts/upstream/src/arm/marvell/mvebu-linkstation-fan.dtsi
+++ b/dts/upstream/src/arm/marvell/mvebu-linkstation-fan.dtsi
@@ -50,10 +50,10 @@
pinctrl-names = "default";
gpio-fan,speed-map =
- <0 3
- 1500 2
- 3250 1
- 5000 0>;
+ < 0 3>,
+ <1500 2>,
+ <3250 1>,
+ <5000 0>;
};
};
diff --git a/dts/upstream/src/arm/microchip/at91-sam9x60_curiosity.dts b/dts/upstream/src/arm/microchip/at91-sam9x60_curiosity.dts
index 83372c1..c6fbdd2 100644
--- a/dts/upstream/src/arm/microchip/at91-sam9x60_curiosity.dts
+++ b/dts/upstream/src/arm/microchip/at91-sam9x60_curiosity.dts
@@ -249,6 +249,8 @@
ethernet-phy@0 {
reg = <0x0>;
+ interrupt-parent = <&pioB>;
+ interrupts = <8 IRQ_TYPE_LEVEL_LOW>;
};
};
@@ -353,6 +355,7 @@
AT91_PIOB 5 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB5 periph A */
AT91_PIOB 6 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB6 periph A */
AT91_PIOB 7 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB7 periph A */
+ AT91_PIOB 8 AT91_PERIPH_GPIO AT91_PINCTRL_NONE /* PB8 IRQ GPIO */
AT91_PIOB 9 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB9 periph A */
AT91_PIOB 10 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PB10 periph A */
};
diff --git a/dts/upstream/src/arm/microchip/at91-sam9x60ek.dts b/dts/upstream/src/arm/microchip/at91-sam9x60ek.dts
index 5cd5930..f3cbb67 100644
--- a/dts/upstream/src/arm/microchip/at91-sam9x60ek.dts
+++ b/dts/upstream/src/arm/microchip/at91-sam9x60ek.dts
@@ -292,6 +292,8 @@
ethernet-phy@0 {
reg = <0x0>;
+ interrupt-parent = <&pioB>;
+ interrupts = <8 IRQ_TYPE_LEVEL_LOW>;
};
};
@@ -465,6 +467,7 @@
AT91_PIOB 5 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB5 periph A */
AT91_PIOB 6 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB6 periph A */
AT91_PIOB 7 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB7 periph A */
+ AT91_PIOB 8 AT91_PERIPH_GPIO AT91_PINCTRL_NONE /* PB8 IRQ GPIO */
AT91_PIOB 9 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB9 periph A */
AT91_PIOB 10 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PB10 periph A */
};
diff --git a/dts/upstream/src/arm/microchip/at91-sama5d27_som1_ek.dts b/dts/upstream/src/arm/microchip/at91-sama5d27_som1_ek.dts
index d0a6dbd..f3ffb8f 100644
--- a/dts/upstream/src/arm/microchip/at91-sama5d27_som1_ek.dts
+++ b/dts/upstream/src/arm/microchip/at91-sama5d27_som1_ek.dts
@@ -54,7 +54,6 @@
sdmmc0: sdio-host@a0000000 {
bus-width = <8>;
- mmc-ddr-3_3v;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_sdmmc0_default>;
status = "okay";
diff --git a/dts/upstream/src/arm/microchip/at91-sama5d27_wlsom1_ek.dts b/dts/upstream/src/arm/microchip/at91-sama5d27_wlsom1_ek.dts
index e055b9e..1523983 100644
--- a/dts/upstream/src/arm/microchip/at91-sama5d27_wlsom1_ek.dts
+++ b/dts/upstream/src/arm/microchip/at91-sama5d27_wlsom1_ek.dts
@@ -197,7 +197,6 @@
&sdmmc0 {
bus-width = <4>;
- mmc-ddr-3_3v;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_sdmmc0_default>;
status = "okay";
diff --git a/dts/upstream/src/arm/nuvoton/nuvoton-wpcm450.dtsi b/dts/upstream/src/arm/nuvoton/nuvoton-wpcm450.dtsi
index fd671c7..6e1f0f1 100644
--- a/dts/upstream/src/arm/nuvoton/nuvoton-wpcm450.dtsi
+++ b/dts/upstream/src/arm/nuvoton/nuvoton-wpcm450.dtsi
@@ -120,6 +120,7 @@
interrupts = <2 IRQ_TYPE_LEVEL_HIGH>,
<3 IRQ_TYPE_LEVEL_HIGH>,
<4 IRQ_TYPE_LEVEL_HIGH>;
+ #interrupt-cells = <2>;
interrupt-controller;
};
@@ -128,6 +129,7 @@
gpio-controller;
#gpio-cells = <2>;
interrupts = <5 IRQ_TYPE_LEVEL_HIGH>;
+ #interrupt-cells = <2>;
interrupt-controller;
};
diff --git a/dts/upstream/src/arm/nvidia/tegra20-colibri.dtsi b/dts/upstream/src/arm/nvidia/tegra20-colibri.dtsi
index 16b374e..8c1d5c9 100644
--- a/dts/upstream/src/arm/nvidia/tegra20-colibri.dtsi
+++ b/dts/upstream/src/arm/nvidia/tegra20-colibri.dtsi
@@ -446,7 +446,7 @@
tegra_ac97: ac97@70002000 {
status = "okay";
nvidia,codec-reset-gpio =
- <&gpio TEGRA_GPIO(V, 0) GPIO_ACTIVE_HIGH>;
+ <&gpio TEGRA_GPIO(V, 0) GPIO_ACTIVE_LOW>;
nvidia,codec-sync-gpio =
<&gpio TEGRA_GPIO(P, 0) GPIO_ACTIVE_HIGH>;
};
diff --git a/dts/upstream/src/arm/nvidia/tegra30-apalis-v1.1.dtsi b/dts/upstream/src/arm/nvidia/tegra30-apalis-v1.1.dtsi
index 1640763..ff0d684 100644
--- a/dts/upstream/src/arm/nvidia/tegra30-apalis-v1.1.dtsi
+++ b/dts/upstream/src/arm/nvidia/tegra30-apalis-v1.1.dtsi
@@ -997,7 +997,6 @@
compatible = "st,stmpe811";
reg = <0x41>;
irq-gpio = <&gpio TEGRA_GPIO(V, 0) GPIO_ACTIVE_LOW>;
- interrupt-controller;
id = <0>;
blocks = <0x5>;
irq-trigger = <0x1>;
diff --git a/dts/upstream/src/arm/nvidia/tegra30-apalis.dtsi b/dts/upstream/src/arm/nvidia/tegra30-apalis.dtsi
index 3b6fad2..d38f1dd 100644
--- a/dts/upstream/src/arm/nvidia/tegra30-apalis.dtsi
+++ b/dts/upstream/src/arm/nvidia/tegra30-apalis.dtsi
@@ -980,7 +980,6 @@
compatible = "st,stmpe811";
reg = <0x41>;
irq-gpio = <&gpio TEGRA_GPIO(V, 0) GPIO_ACTIVE_LOW>;
- interrupt-controller;
id = <0>;
blocks = <0x5>;
irq-trigger = <0x1>;
diff --git a/dts/upstream/src/arm/nvidia/tegra30-colibri.dtsi b/dts/upstream/src/arm/nvidia/tegra30-colibri.dtsi
index 4eb526f..81c8a5f 100644
--- a/dts/upstream/src/arm/nvidia/tegra30-colibri.dtsi
+++ b/dts/upstream/src/arm/nvidia/tegra30-colibri.dtsi
@@ -861,7 +861,6 @@
compatible = "st,stmpe811";
reg = <0x41>;
irq-gpio = <&gpio TEGRA_GPIO(V, 0) GPIO_ACTIVE_LOW>;
- interrupt-controller;
id = <0>;
blocks = <0x5>;
irq-trigger = <0x1>;
diff --git a/dts/upstream/src/arm/nxp/imx/imx1-ads.dts b/dts/upstream/src/arm/nxp/imx/imx1-ads.dts
index 5833fb6..2c817c4 100644
--- a/dts/upstream/src/arm/nxp/imx/imx1-ads.dts
+++ b/dts/upstream/src/arm/nxp/imx/imx1-ads.dts
@@ -65,7 +65,7 @@
pinctrl-0 = <&pinctrl_weim>;
status = "okay";
- nor: nor@0,0 {
+ nor: flash@0,0 {
compatible = "cfi-flash";
reg = <0 0x00000000 0x02000000>;
bank-width = <4>;
diff --git a/dts/upstream/src/arm/nxp/imx/imx1-apf9328.dts b/dts/upstream/src/arm/nxp/imx/imx1-apf9328.dts
index 1f11e95..e66eef8 100644
--- a/dts/upstream/src/arm/nxp/imx/imx1-apf9328.dts
+++ b/dts/upstream/src/arm/nxp/imx/imx1-apf9328.dts
@@ -45,7 +45,7 @@
pinctrl-0 = <&pinctrl_weim>;
status = "okay";
- nor: nor@0,0 {
+ nor: flash@0,0 {
compatible = "cfi-flash";
reg = <0 0x00000000 0x02000000>;
bank-width = <2>;
diff --git a/dts/upstream/src/arm/nxp/imx/imx1.dtsi b/dts/upstream/src/arm/nxp/imx/imx1.dtsi
index e312f1e..1ac1096 100644
--- a/dts/upstream/src/arm/nxp/imx/imx1.dtsi
+++ b/dts/upstream/src/arm/nxp/imx/imx1.dtsi
@@ -68,7 +68,7 @@
interrupt-parent = <&aitc>;
ranges;
- aipi@200000 {
+ bus@200000 {
compatible = "fsl,aipi-bus", "simple-bus";
#address-cells = <1>;
#size-cells = <1>;
@@ -155,7 +155,7 @@
};
};
- aipi@210000 {
+ bus@210000 {
compatible = "fsl,aipi-bus", "simple-bus";
#address-cells = <1>;
#size-cells = <1>;
@@ -268,9 +268,12 @@
status = "disabled";
};
- esram: esram@300000 {
+ esram: sram@300000 {
compatible = "mmio-sram";
reg = <0x00300000 0x20000>;
+ ranges = <0 0x00300000 0x20000>;
+ #address-cells = <1>;
+ #size-cells = <1>;
};
};
};
diff --git a/dts/upstream/src/arm/nxp/imx/imx25-eukrea-cpuimx25.dtsi b/dts/upstream/src/arm/nxp/imx/imx25-eukrea-cpuimx25.dtsi
index 0703f62..93a6e4e 100644
--- a/dts/upstream/src/arm/nxp/imx/imx25-eukrea-cpuimx25.dtsi
+++ b/dts/upstream/src/arm/nxp/imx/imx25-eukrea-cpuimx25.dtsi
@@ -27,7 +27,7 @@
pinctrl-0 = <&pinctrl_i2c1>;
status = "okay";
- pcf8563@51 {
+ rtc@51 {
compatible = "nxp,pcf8563";
reg = <0x51>;
};
diff --git a/dts/upstream/src/arm/nxp/imx/imx25-eukrea-mbimxsd25-baseboard-cmo-qvga.dts b/dts/upstream/src/arm/nxp/imx/imx25-eukrea-mbimxsd25-baseboard-cmo-qvga.dts
index fc8a502..6cddb2c 100644
--- a/dts/upstream/src/arm/nxp/imx/imx25-eukrea-mbimxsd25-baseboard-cmo-qvga.dts
+++ b/dts/upstream/src/arm/nxp/imx/imx25-eukrea-mbimxsd25-baseboard-cmo-qvga.dts
@@ -16,7 +16,7 @@
bus-width = <18>;
display-timings {
native-mode = <&qvga_timings>;
- qvga_timings: 320x240 {
+ qvga_timings: timing0 {
clock-frequency = <6500000>;
hactive = <320>;
vactive = <240>;
diff --git a/dts/upstream/src/arm/nxp/imx/imx25-eukrea-mbimxsd25-baseboard-dvi-svga.dts b/dts/upstream/src/arm/nxp/imx/imx25-eukrea-mbimxsd25-baseboard-dvi-svga.dts
index 80a7f96..64b2ffa 100644
--- a/dts/upstream/src/arm/nxp/imx/imx25-eukrea-mbimxsd25-baseboard-dvi-svga.dts
+++ b/dts/upstream/src/arm/nxp/imx/imx25-eukrea-mbimxsd25-baseboard-dvi-svga.dts
@@ -16,7 +16,7 @@
bus-width = <18>;
display-timings {
native-mode = <&dvi_svga_timings>;
- dvi_svga_timings: 800x600 {
+ dvi_svga_timings: timing0 {
clock-frequency = <40000000>;
hactive = <800>;
vactive = <600>;
diff --git a/dts/upstream/src/arm/nxp/imx/imx25-eukrea-mbimxsd25-baseboard-dvi-vga.dts b/dts/upstream/src/arm/nxp/imx/imx25-eukrea-mbimxsd25-baseboard-dvi-vga.dts
index 24027a1..fb074bf 100644
--- a/dts/upstream/src/arm/nxp/imx/imx25-eukrea-mbimxsd25-baseboard-dvi-vga.dts
+++ b/dts/upstream/src/arm/nxp/imx/imx25-eukrea-mbimxsd25-baseboard-dvi-vga.dts
@@ -16,7 +16,7 @@
bus-width = <18>;
display-timings {
native-mode = <&dvi_vga_timings>;
- dvi_vga_timings: 640x480 {
+ dvi_vga_timings: timing0 {
clock-frequency = <31250000>;
hactive = <640>;
vactive = <480>;
diff --git a/dts/upstream/src/arm/nxp/imx/imx25-pdk.dts b/dts/upstream/src/arm/nxp/imx/imx25-pdk.dts
index 04f4b12..dd176fb 100644
--- a/dts/upstream/src/arm/nxp/imx/imx25-pdk.dts
+++ b/dts/upstream/src/arm/nxp/imx/imx25-pdk.dts
@@ -68,7 +68,7 @@
bus-width = <18>;
display-timings {
native-mode = <&wvga_timings>;
- wvga_timings: 640x480 {
+ wvga_timings: timing0 {
hactive = <640>;
vactive = <480>;
hback-porch = <45>;
@@ -122,6 +122,7 @@
codec: sgtl5000@a {
compatible = "fsl,sgtl5000";
reg = <0x0a>;
+ #sound-dai-cells = <0>;
clocks = <&clks 129>;
VDDA-supply = <®_2p5v>;
VDDIO-supply = <®_3p3v>;
diff --git a/dts/upstream/src/arm/nxp/imx/imx25.dtsi b/dts/upstream/src/arm/nxp/imx/imx25.dtsi
index 534c70b..9cfff21 100644
--- a/dts/upstream/src/arm/nxp/imx/imx25.dtsi
+++ b/dts/upstream/src/arm/nxp/imx/imx25.dtsi
@@ -68,6 +68,16 @@
};
};
+ usbphy0: usb-phy0 {
+ compatible = "usb-nop-xceiv";
+ #phy-cells = <0>;
+ };
+
+ usbphy1: usb-phy1 {
+ compatible = "usb-nop-xceiv";
+ #phy-cells = <0>;
+ };
+
soc: soc {
#address-cells = <1>;
#size-cells = <1>;
@@ -93,7 +103,7 @@
compatible = "fsl,imx25-i2c", "fsl,imx21-i2c";
reg = <0x43f80000 0x4000>;
clocks = <&clks 48>;
- clock-names = "";
+ clock-names = "ipg";
interrupts = <3>;
status = "disabled";
};
@@ -104,7 +114,7 @@
compatible = "fsl,imx25-i2c", "fsl,imx21-i2c";
reg = <0x43f84000 0x4000>;
clocks = <&clks 48>;
- clock-names = "";
+ clock-names = "ipg";
interrupts = <10>;
status = "disabled";
};
@@ -151,7 +161,7 @@
compatible = "fsl,imx25-i2c", "fsl,imx21-i2c";
reg = <0x43f98000 0x4000>;
clocks = <&clks 48>;
- clock-names = "";
+ clock-names = "ipg";
interrupts = <4>;
status = "disabled";
};
@@ -178,12 +188,9 @@
};
kpp: kpp@43fa8000 {
- #address-cells = <1>;
- #size-cells = <0>;
compatible = "fsl,imx25-kpp", "fsl,imx21-kpp";
reg = <0x43fa8000 0x4000>;
clocks = <&clks 102>;
- clock-names = "";
interrupts = <24>;
status = "disabled";
};
@@ -542,7 +549,7 @@
};
iim: efuse@53ff0000 {
- compatible = "fsl,imx25-iim", "fsl,imx27-iim";
+ compatible = "fsl,imx25-iim";
reg = <0x53ff0000 0x4000>;
interrupts = <19>;
clocks = <&clks 99>;
@@ -597,7 +604,7 @@
#size-cells = <1>;
};
- emi@80000000 {
+ bus@80000000 {
compatible = "fsl,emi-bus", "simple-bus";
#address-cells = <1>;
#size-cells = <1>;
@@ -617,22 +624,4 @@
};
};
};
-
- usbphy {
- compatible = "simple-bus";
- #address-cells = <1>;
- #size-cells = <0>;
-
- usbphy0: usb-phy@0 {
- reg = <0>;
- compatible = "usb-nop-xceiv";
- #phy-cells = <0>;
- };
-
- usbphy1: usb-phy@1 {
- reg = <1>;
- compatible = "usb-nop-xceiv";
- #phy-cells = <0>;
- };
- };
};
diff --git a/dts/upstream/src/arm/nxp/imx/imx27-apf27dev.dts b/dts/upstream/src/arm/nxp/imx/imx27-apf27dev.dts
index a21f1f7..849306c 100644
--- a/dts/upstream/src/arm/nxp/imx/imx27-apf27dev.dts
+++ b/dts/upstream/src/arm/nxp/imx/imx27-apf27dev.dts
@@ -16,7 +16,7 @@
fsl,pcr = <0xfae80083>; /* non-standard but required */
display-timings {
native-mode = <&timing0>;
- timing0: 800x480 {
+ timing0: timing0 {
clock-frequency = <33000033>;
hactive = <800>;
vactive = <480>;
@@ -47,7 +47,7 @@
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_gpio_leds>;
- user {
+ led-user {
label = "Heartbeat";
gpios = <&gpio6 14 GPIO_ACTIVE_HIGH>;
linux,default-trigger = "heartbeat";
diff --git a/dts/upstream/src/arm/nxp/imx/imx27-eukrea-cpuimx27.dtsi b/dts/upstream/src/arm/nxp/imx/imx27-eukrea-cpuimx27.dtsi
index 74110bb..c7e9235 100644
--- a/dts/upstream/src/arm/nxp/imx/imx27-eukrea-cpuimx27.dtsi
+++ b/dts/upstream/src/arm/nxp/imx/imx27-eukrea-cpuimx27.dtsi
@@ -33,7 +33,7 @@
pinctrl-0 = <&pinctrl_i2c1>;
status = "okay";
- pcf8563@51 {
+ rtc@51 {
compatible = "nxp,pcf8563";
reg = <0x51>;
};
@@ -90,7 +90,7 @@
&weim {
status = "okay";
- nor: nor@0,0 {
+ nor: flash@0,0 {
#address-cells = <1>;
#size-cells = <1>;
compatible = "cfi-flash";
diff --git a/dts/upstream/src/arm/nxp/imx/imx27-eukrea-mbimxsd27-baseboard.dts b/dts/upstream/src/arm/nxp/imx/imx27-eukrea-mbimxsd27-baseboard.dts
index 145e459..d787936 100644
--- a/dts/upstream/src/arm/nxp/imx/imx27-eukrea-mbimxsd27-baseboard.dts
+++ b/dts/upstream/src/arm/nxp/imx/imx27-eukrea-mbimxsd27-baseboard.dts
@@ -16,7 +16,7 @@
display-timings {
native-mode = <&timing0>;
- timing0: 320x240 {
+ timing0: timing0 {
clock-frequency = <6500000>;
hactive = <320>;
vactive = <240>;
diff --git a/dts/upstream/src/arm/nxp/imx/imx27-pdk.dts b/dts/upstream/src/arm/nxp/imx/imx27-pdk.dts
index 35123b7..21d4369 100644
--- a/dts/upstream/src/arm/nxp/imx/imx27-pdk.dts
+++ b/dts/upstream/src/arm/nxp/imx/imx27-pdk.dts
@@ -14,18 +14,12 @@
reg = <0xa0000000 0x08000000>;
};
- usbphy {
- compatible = "simple-bus";
- #address-cells = <1>;
- #size-cells = <0>;
- usbphy0: usbphy@0 {
- compatible = "usb-nop-xceiv";
- reg = <0>;
- clocks = <&clks IMX27_CLK_DUMMY>;
- clock-names = "main_clk";
- #phy-cells = <0>;
- };
+ usbphy0: usbphy {
+ compatible = "usb-nop-xceiv";
+ clocks = <&clks IMX27_CLK_DUMMY>;
+ clock-names = "main_clk";
+ #phy-cells = <0>;
};
};
diff --git a/dts/upstream/src/arm/nxp/imx/imx27-phytec-phycard-s-rdk.dts b/dts/upstream/src/arm/nxp/imx/imx27-phytec-phycard-s-rdk.dts
index 25442eb..27c93b9 100644
--- a/dts/upstream/src/arm/nxp/imx/imx27-phytec-phycard-s-rdk.dts
+++ b/dts/upstream/src/arm/nxp/imx/imx27-phytec-phycard-s-rdk.dts
@@ -19,7 +19,7 @@
fsl,pcr = <0xf0c88080>; /* non-standard but required */
display-timings {
native-mode = <&timing0>;
- timing0: 640x480 {
+ timing0: timing0 {
hactive = <640>;
vactive = <480>;
hback-porch = <112>;
diff --git a/dts/upstream/src/arm/nxp/imx/imx27-phytec-phycore-rdk.dts b/dts/upstream/src/arm/nxp/imx/imx27-phytec-phycore-rdk.dts
index 7f0cd4d..b8048e1 100644
--- a/dts/upstream/src/arm/nxp/imx/imx27-phytec-phycore-rdk.dts
+++ b/dts/upstream/src/arm/nxp/imx/imx27-phytec-phycore-rdk.dts
@@ -19,7 +19,7 @@
display-timings {
native-mode = <&timing0>;
- timing0: 240x320 {
+ timing0: timing0 {
clock-frequency = <5500000>;
hactive = <240>;
vactive = <320>;
@@ -48,15 +48,12 @@
regulator-always-on;
};
- usbphy {
- usbphy2: usbphy@2 {
- compatible = "usb-nop-xceiv";
- reg = <2>;
- vcc-supply = <®_5v0>;
- clocks = <&clks IMX27_CLK_DUMMY>;
- clock-names = "main_clk";
- #phy-cells = <0>;
- };
+ usbphy2: usbphy {
+ compatible = "usb-nop-xceiv";
+ vcc-supply = <®_5v0>;
+ clocks = <&clks IMX27_CLK_DUMMY>;
+ clock-names = "main_clk";
+ #phy-cells = <0>;
};
};
diff --git a/dts/upstream/src/arm/nxp/imx/imx27-phytec-phycore-som.dtsi b/dts/upstream/src/arm/nxp/imx/imx27-phytec-phycore-som.dtsi
index 7b2ea4c..e958d72 100644
--- a/dts/upstream/src/arm/nxp/imx/imx27-phytec-phycore-som.dtsi
+++ b/dts/upstream/src/arm/nxp/imx/imx27-phytec-phycore-som.dtsi
@@ -29,19 +29,13 @@
regulator-max-microvolt = <5000000>;
};
- usbphy {
- compatible = "simple-bus";
- #address-cells = <1>;
- #size-cells = <0>;
- usbphy0: usbphy@0 {
- compatible = "usb-nop-xceiv";
- reg = <0>;
- vcc-supply = <&sw3_reg>;
- clocks = <&clks IMX27_CLK_DUMMY>;
- clock-names = "main_clk";
- #phy-cells = <0>;
- };
+ usbphy0: usbphy {
+ compatible = "usb-nop-xceiv";
+ vcc-supply = <&sw3_reg>;
+ clocks = <&clks IMX27_CLK_DUMMY>;
+ clock-names = "main_clk";
+ #phy-cells = <0>;
};
};
@@ -49,12 +43,12 @@
status = "okay";
/* SSI0 <=> PINS_4 (MC13783 Audio) */
- ssi0 {
+ mux-ssi0 {
fsl,audmux-port = <0>;
fsl,port-config = <0xcb205000>;
};
- pins4 {
+ mux-pins4 {
fsl,audmux-port = <2>;
fsl,port-config = <0x00001000>;
};
@@ -186,7 +180,7 @@
reg = <0x52>;
};
- pcf8563@51 {
+ rtc@51 {
compatible = "nxp,pcf8563";
reg = <0x51>;
};
@@ -314,7 +308,7 @@
&weim {
status = "okay";
- nor: nor@0,0 {
+ nor: flash@0,0 {
compatible = "cfi-flash";
reg = <0 0x00000000 0x02000000>;
bank-width = <2>;
diff --git a/dts/upstream/src/arm/nxp/imx/imx27.dtsi b/dts/upstream/src/arm/nxp/imx/imx27.dtsi
index faba12e..ec47269 100644
--- a/dts/upstream/src/arm/nxp/imx/imx27.dtsi
+++ b/dts/upstream/src/arm/nxp/imx/imx27.dtsi
@@ -81,7 +81,7 @@
interrupt-parent = <&aitc>;
ranges;
- aipi1: aipi@10000000 { /* AIPI1 */
+ aipi1: bus@10000000 { /* AIPI1 */
compatible = "fsl,aipi-bus", "simple-bus";
#address-cells = <1>;
#size-cells = <1>;
@@ -453,7 +453,7 @@
};
};
- aipi2: aipi@10020000 { /* AIPI2 */
+ aipi2: bus@10020000 { /* AIPI2 */
compatible = "fsl,aipi-bus", "simple-bus";
#address-cells = <1>;
#size-cells = <1>;
@@ -588,6 +588,9 @@
iram: sram@ffff4c00 {
compatible = "mmio-sram";
reg = <0xffff4c00 0xb400>;
+ ranges = <0 0xffff4c00 0xb400>;
+ #address-cells = <1>;
+ #size-cells = <1>;
};
};
};
diff --git a/dts/upstream/src/arm/nxp/imx/imx53-cx9020.dts b/dts/upstream/src/arm/nxp/imx/imx53-cx9020.dts
index 055d23a..0814f56 100644
--- a/dts/upstream/src/arm/nxp/imx/imx53-cx9020.dts
+++ b/dts/upstream/src/arm/nxp/imx/imx53-cx9020.dts
@@ -22,7 +22,7 @@
};
display-0 {
- #address-cells =<1>;
+ #address-cells = <1>;
#size-cells = <0>;
compatible = "fsl,imx-parallel-display";
interface-pix-fmt = "rgb24";
diff --git a/dts/upstream/src/arm/nxp/imx/imx6dl-b105pv2.dts b/dts/upstream/src/arm/nxp/imx/imx6dl-b105pv2.dts
index 7d4ae11..63cdf24 100644
--- a/dts/upstream/src/arm/nxp/imx/imx6dl-b105pv2.dts
+++ b/dts/upstream/src/arm/nxp/imx/imx6dl-b105pv2.dts
@@ -22,7 +22,7 @@
compatible = "ilitek,ili251x";
reg = <0x41>;
pinctrl-names = "default";
- pinctrl-0 =<&pinctrl_q7_gpio0>;
+ pinctrl-0 = <&pinctrl_q7_gpio0>;
interrupt-parent = <&gpio5>;
interrupts = <2 IRQ_TYPE_EDGE_FALLING>;
reset-gpios = <&tca6424a 21 GPIO_ACTIVE_LOW>;
diff --git a/dts/upstream/src/arm/nxp/imx/imx6dl-b105v2.dts b/dts/upstream/src/arm/nxp/imx/imx6dl-b105v2.dts
index 9c5938e..2e75d70 100644
--- a/dts/upstream/src/arm/nxp/imx/imx6dl-b105v2.dts
+++ b/dts/upstream/src/arm/nxp/imx/imx6dl-b105v2.dts
@@ -22,7 +22,7 @@
compatible = "ilitek,ili251x";
reg = <0x41>;
pinctrl-names = "default";
- pinctrl-0 =<&pinctrl_q7_gpio0>;
+ pinctrl-0 = <&pinctrl_q7_gpio0>;
interrupt-parent = <&gpio5>;
interrupts = <2 IRQ_TYPE_EDGE_FALLING>;
reset-gpios = <&tca6424a 21 GPIO_ACTIVE_LOW>;
diff --git a/dts/upstream/src/arm/nxp/imx/imx6dl-b125pv2.dts b/dts/upstream/src/arm/nxp/imx/imx6dl-b125pv2.dts
index 01df7cf..94625d5 100644
--- a/dts/upstream/src/arm/nxp/imx/imx6dl-b125pv2.dts
+++ b/dts/upstream/src/arm/nxp/imx/imx6dl-b125pv2.dts
@@ -22,7 +22,7 @@
compatible = "eeti,exc80h60";
reg = <0x2a>;
pinctrl-names = "default";
- pinctrl-0 =<&pinctrl_q7_gpio0>;
+ pinctrl-0 = <&pinctrl_q7_gpio0>;
interrupt-parent = <&gpio5>;
interrupts = <2 IRQ_TYPE_LEVEL_LOW>;
reset-gpios = <&tca6424a 21 GPIO_ACTIVE_HIGH>;
diff --git a/dts/upstream/src/arm/nxp/imx/imx6dl-b125v2.dts b/dts/upstream/src/arm/nxp/imx/imx6dl-b125v2.dts
index a015453..b3cfa81 100644
--- a/dts/upstream/src/arm/nxp/imx/imx6dl-b125v2.dts
+++ b/dts/upstream/src/arm/nxp/imx/imx6dl-b125v2.dts
@@ -22,7 +22,7 @@
compatible = "eeti,exc80h60";
reg = <0x2a>;
pinctrl-names = "default";
- pinctrl-0 =<&pinctrl_q7_gpio0>;
+ pinctrl-0 = <&pinctrl_q7_gpio0>;
interrupt-parent = <&gpio5>;
interrupts = <2 IRQ_TYPE_LEVEL_LOW>;
reset-gpios = <&tca6424a 21 GPIO_ACTIVE_HIGH>;
diff --git a/dts/upstream/src/arm/nxp/imx/imx6dl-b155v2.dts b/dts/upstream/src/arm/nxp/imx/imx6dl-b155v2.dts
index b71ee6b..7edc788 100644
--- a/dts/upstream/src/arm/nxp/imx/imx6dl-b155v2.dts
+++ b/dts/upstream/src/arm/nxp/imx/imx6dl-b155v2.dts
@@ -22,7 +22,7 @@
compatible = "eeti,exc80h84";
reg = <0x2a>;
pinctrl-names = "default";
- pinctrl-0 =<&pinctrl_q7_gpio0>;
+ pinctrl-0 = <&pinctrl_q7_gpio0>;
interrupt-parent = <&gpio5>;
interrupts = <2 IRQ_TYPE_LEVEL_LOW>;
touchscreen-inverted-x;
diff --git a/dts/upstream/src/arm/nxp/imx/imx6q-apalis-ixora-v1.2.dts b/dts/upstream/src/arm/nxp/imx/imx6q-apalis-ixora-v1.2.dts
index 717decd..3ac7a45 100644
--- a/dts/upstream/src/arm/nxp/imx/imx6q-apalis-ixora-v1.2.dts
+++ b/dts/upstream/src/arm/nxp/imx/imx6q-apalis-ixora-v1.2.dts
@@ -76,6 +76,7 @@
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_enable_can1_power>;
regulator-name = "can1_supply";
+ startup-delay-us = <1000>;
};
reg_can2_supply: regulator-can2-supply {
@@ -85,6 +86,7 @@
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_enable_can2_power>;
regulator-name = "can2_supply";
+ startup-delay-us = <1000>;
};
};
diff --git a/dts/upstream/src/arm/nxp/imx/imx6q-b850v3.dts b/dts/upstream/src/arm/nxp/imx/imx6q-b850v3.dts
index db8c332..cad112e 100644
--- a/dts/upstream/src/arm/nxp/imx/imx6q-b850v3.dts
+++ b/dts/upstream/src/arm/nxp/imx/imx6q-b850v3.dts
@@ -227,7 +227,6 @@
#address-cells = <3>;
#size-cells = <2>;
- #interrupt-cells = <1>;
bridge@2,1 {
compatible = "pci10b5,8605";
@@ -235,7 +234,6 @@
#address-cells = <3>;
#size-cells = <2>;
- #interrupt-cells = <1>;
/* Intel Corporation I210 Gigabit Network Connection */
ethernet@3,0 {
@@ -250,7 +248,6 @@
#address-cells = <3>;
#size-cells = <2>;
- #interrupt-cells = <1>;
/* Intel Corporation I210 Gigabit Network Connection */
switch_nic: ethernet@4,0 {
diff --git a/dts/upstream/src/arm/nxp/imx/imx6q-bx50v3.dtsi b/dts/upstream/src/arm/nxp/imx/imx6q-bx50v3.dtsi
index 99f4f6a..c1ae7c4 100644
--- a/dts/upstream/src/arm/nxp/imx/imx6q-bx50v3.dtsi
+++ b/dts/upstream/src/arm/nxp/imx/imx6q-bx50v3.dtsi
@@ -245,6 +245,7 @@
reg = <0x74>;
gpio-controller;
#gpio-cells = <2>;
+ #interrupt-cells = <2>;
interrupt-controller;
interrupt-parent = <&gpio2>;
interrupts = <3 IRQ_TYPE_LEVEL_LOW>;
@@ -390,7 +391,6 @@
#address-cells = <3>;
#size-cells = <2>;
- #interrupt-cells = <1>;
};
};
diff --git a/dts/upstream/src/arm/nxp/imx/imx6q-var-mx6customboard.dts b/dts/upstream/src/arm/nxp/imx/imx6q-var-mx6customboard.dts
index 6f9d094..18a6208 100644
--- a/dts/upstream/src/arm/nxp/imx/imx6q-var-mx6customboard.dts
+++ b/dts/upstream/src/arm/nxp/imx/imx6q-var-mx6customboard.dts
@@ -16,7 +16,7 @@
compatible = "variscite,mx6customboard", "variscite,var-som-imx6q", "fsl,imx6q";
panel0: lvds-panel0 {
- compatible = "panel-lvds";
+ compatible = "panel-lvds";
backlight = <&backlight_lvds>;
width-mm = <152>;
height-mm = <91>;
@@ -43,7 +43,7 @@
};
panel1: lvds-panel1 {
- compatible = "panel-lvds";
+ compatible = "panel-lvds";
width-mm = <152>;
height-mm = <91>;
data-mapping = "jeida-18";
diff --git a/dts/upstream/src/arm/nxp/imx/imx6qdl-apalis.dtsi b/dts/upstream/src/arm/nxp/imx/imx6qdl-apalis.dtsi
index 4cc9652..ea40623 100644
--- a/dts/upstream/src/arm/nxp/imx/imx6qdl-apalis.dtsi
+++ b/dts/upstream/src/arm/nxp/imx/imx6qdl-apalis.dtsi
@@ -12,6 +12,13 @@
model = "Toradex Apalis iMX6Q/D Module";
compatible = "toradex,apalis_imx6q", "fsl,imx6q";
+ aliases {
+ mmc0 = &usdhc3; /* eMMC */
+ mmc1 = &usdhc1; /* MMC1 slot */
+ mmc2 = &usdhc2; /* SD1 slot */
+ /delete-property/ mmc3;
+ };
+
/* Will be filled by the bootloader */
memory@10000000 {
device_type = "memory";
@@ -166,7 +173,7 @@
reg_usb_host_vbus: regulator-usb-host-vbus {
compatible = "regulator-fixed";
enable-active-high;
- gpio = <&gpio1 0 GPIO_ACTIVE_HIGH>;
+ gpio = <&gpio1 0 GPIO_ACTIVE_HIGH>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_regulator_usbh_pwr>;
regulator-max-microvolt = <5000000>;
@@ -619,7 +626,6 @@
blocks = <0x5>;
id = <0>;
interrupts = <10 IRQ_TYPE_LEVEL_LOW>;
- interrupt-controller;
interrupt-parent = <&gpio4>;
irq-trigger = <0x1>;
pinctrl-names = "default";
diff --git a/dts/upstream/src/arm/nxp/imx/imx6qdl-colibri.dtsi b/dts/upstream/src/arm/nxp/imx/imx6qdl-colibri.dtsi
index 11d9c7a..d3a7a6e 100644
--- a/dts/upstream/src/arm/nxp/imx/imx6qdl-colibri.dtsi
+++ b/dts/upstream/src/arm/nxp/imx/imx6qdl-colibri.dtsi
@@ -12,6 +12,13 @@
model = "Toradex Colibri iMX6DL/S Module";
compatible = "toradex,colibri_imx6dl", "fsl,imx6dl";
+ aliases {
+ mmc0 = &usdhc3; /* eMMC */
+ mmc1 = &usdhc1; /* MMC/SD Slot */
+ /delete-property/ mmc2;
+ /delete-property/ mmc3;
+ };
+
backlight: backlight {
compatible = "pwm-backlight";
brightness-levels = <0 45 63 88 119 158 203 255>;
@@ -543,7 +550,6 @@
blocks = <0x5>;
interrupts = <20 IRQ_TYPE_LEVEL_LOW>;
interrupt-parent = <&gpio6>;
- interrupt-controller;
id = <0>;
irq-trigger = <0x1>;
pinctrl-names = "default";
diff --git a/dts/upstream/src/arm/nxp/imx/imx6qdl-emcon-avari.dtsi b/dts/upstream/src/arm/nxp/imx/imx6qdl-emcon-avari.dtsi
index f1a41c7..5587069 100644
--- a/dts/upstream/src/arm/nxp/imx/imx6qdl-emcon-avari.dtsi
+++ b/dts/upstream/src/arm/nxp/imx/imx6qdl-emcon-avari.dtsi
@@ -54,7 +54,7 @@
clk_codec: clock-codec {
compatible = "fixed-clock";
#clock-cells = <0>;
- clock-frequency = <12000000>;
+ clock-frequency = <12000000>;
};
sound {
diff --git a/dts/upstream/src/arm/nxp/imx/imx6qdl-emcon.dtsi b/dts/upstream/src/arm/nxp/imx/imx6qdl-emcon.dtsi
index a63e73a..42b2ba2 100644
--- a/dts/upstream/src/arm/nxp/imx/imx6qdl-emcon.dtsi
+++ b/dts/upstream/src/arm/nxp/imx/imx6qdl-emcon.dtsi
@@ -225,7 +225,6 @@
pinctrl-0 = <&pinctrl_pmic>;
interrupt-parent = <&gpio2>;
interrupts = <8 IRQ_TYPE_LEVEL_LOW>;
- interrupt-controller;
onkey {
compatible = "dlg,da9063-onkey";
diff --git a/dts/upstream/src/arm/nxp/imx/imx6qdl-mba6.dtsi b/dts/upstream/src/arm/nxp/imx/imx6qdl-mba6.dtsi
index da0f8da..4d2abcd 100644
--- a/dts/upstream/src/arm/nxp/imx/imx6qdl-mba6.dtsi
+++ b/dts/upstream/src/arm/nxp/imx/imx6qdl-mba6.dtsi
@@ -500,21 +500,21 @@
pinctrl_pwm1: pwm1grp {
fsl,pins = <
- /* 100 k PD, DSE 120 OHM, SPPEED LO */
+ /* 100 k PD, DSE 120 OHM, SPEED LO */
MX6QDL_PAD_GPIO_9__PWM1_OUT 0x00003050
>;
};
pinctrl_pwm3: pwm3grp {
fsl,pins = <
- /* 100 k PD, DSE 120 OHM, SPPEED LO */
+ /* 100 k PD, DSE 120 OHM, SPEED LO */
MX6QDL_PAD_SD4_DAT1__PWM3_OUT 0x00003050
>;
};
pinctrl_pwm4: pwm4grp {
fsl,pins = <
- /* 100 k PD, DSE 120 OHM, SPPEED LO */
+ /* 100 k PD, DSE 120 OHM, SPEED LO */
MX6QDL_PAD_SD4_DAT2__PWM4_OUT 0x00003050
>;
};
diff --git a/dts/upstream/src/arm/nxp/imx/imx6qdl-phytec-pfla02.dtsi b/dts/upstream/src/arm/nxp/imx/imx6qdl-phytec-pfla02.dtsi
index 1139745..c0c47ad 100644
--- a/dts/upstream/src/arm/nxp/imx/imx6qdl-phytec-pfla02.dtsi
+++ b/dts/upstream/src/arm/nxp/imx/imx6qdl-phytec-pfla02.dtsi
@@ -124,6 +124,7 @@
reg = <0x58>;
interrupt-parent = <&gpio2>;
interrupts = <9 IRQ_TYPE_LEVEL_LOW>; /* active-low GPIO2_9 */
+ #interrupt-cells = <2>;
interrupt-controller;
regulators {
diff --git a/dts/upstream/src/arm/nxp/imx/imx6qdl-phytec-phycore-som.dtsi b/dts/upstream/src/arm/nxp/imx/imx6qdl-phytec-phycore-som.dtsi
index 86b4269..85e278e 100644
--- a/dts/upstream/src/arm/nxp/imx/imx6qdl-phytec-phycore-som.dtsi
+++ b/dts/upstream/src/arm/nxp/imx/imx6qdl-phytec-phycore-som.dtsi
@@ -100,6 +100,7 @@
interrupt-parent = <&gpio1>;
interrupts = <2 IRQ_TYPE_LEVEL_LOW>;
interrupt-controller;
+ #interrupt-cells = <2>;
gpio-controller;
#gpio-cells = <2>;
diff --git a/dts/upstream/src/arm/nxp/imx/imx6qdl-skov-cpu-revc.dtsi b/dts/upstream/src/arm/nxp/imx/imx6qdl-skov-cpu-revc.dtsi
index b81799d..596b3bb 100644
--- a/dts/upstream/src/arm/nxp/imx/imx6qdl-skov-cpu-revc.dtsi
+++ b/dts/upstream/src/arm/nxp/imx/imx6qdl-skov-cpu-revc.dtsi
@@ -25,7 +25,7 @@
compatible = "ti,tsc2046e-adc";
reg = <0>;
pinctrl-0 = <&pinctrl_touch>;
- pinctrl-names ="default";
+ pinctrl-names = "default";
spi-max-frequency = <1000000>;
interrupts-extended = <&gpio3 19 IRQ_TYPE_LEVEL_LOW>;
#io-channel-cells = <1>;
diff --git a/dts/upstream/src/arm/nxp/imx/imx6qdl.dtsi b/dts/upstream/src/arm/nxp/imx/imx6qdl.dtsi
index bda182e..81142c5 100644
--- a/dts/upstream/src/arm/nxp/imx/imx6qdl.dtsi
+++ b/dts/upstream/src/arm/nxp/imx/imx6qdl.dtsi
@@ -475,7 +475,7 @@
<&sdma 20 23 1>, <&sdma 21 23 1>, <&sdma 22 23 1>;
dma-names = "rxa", "rxb", "rxc",
"txa", "txb", "txc";
- fsl,asrc-rate = <48000>;
+ fsl,asrc-rate = <48000>;
fsl,asrc-width = <16>;
status = "okay";
};
diff --git a/dts/upstream/src/arm/nxp/imx/imx6sx.dtsi b/dts/upstream/src/arm/nxp/imx/imx6sx.dtsi
index f6b3592..df3a375 100644
--- a/dts/upstream/src/arm/nxp/imx/imx6sx.dtsi
+++ b/dts/upstream/src/arm/nxp/imx/imx6sx.dtsi
@@ -418,7 +418,7 @@
<&sdma 21 23 1>, <&sdma 22 23 1>;
dma-names = "rxa", "rxb", "rxc",
"txa", "txb", "txc";
- fsl,asrc-rate = <48000>;
+ fsl,asrc-rate = <48000>;
fsl,asrc-width = <16>;
status = "okay";
};
@@ -1010,7 +1010,7 @@
clock-names = "ipg", "ahb", "per";
bus-width = <4>;
fsl,tuning-start-tap = <20>;
- fsl,tuning-step= <2>;
+ fsl,tuning-step = <2>;
status = "disabled";
};
@@ -1024,7 +1024,7 @@
clock-names = "ipg", "ahb", "per";
bus-width = <4>;
fsl,tuning-start-tap = <20>;
- fsl,tuning-step= <2>;
+ fsl,tuning-step = <2>;
status = "disabled";
};
@@ -1038,7 +1038,7 @@
clock-names = "ipg", "ahb", "per";
bus-width = <4>;
fsl,tuning-start-tap = <20>;
- fsl,tuning-step= <2>;
+ fsl,tuning-step = <2>;
status = "disabled";
};
diff --git a/dts/upstream/src/arm/nxp/imx/imx6ul.dtsi b/dts/upstream/src/arm/nxp/imx/imx6ul.dtsi
index 3b87d98..a27a755 100644
--- a/dts/upstream/src/arm/nxp/imx/imx6ul.dtsi
+++ b/dts/upstream/src/arm/nxp/imx/imx6ul.dtsi
@@ -364,7 +364,7 @@
<&sdma 20 23 1>, <&sdma 21 23 1>, <&sdma 22 23 1>;
dma-names = "rxa", "rxb", "rxc",
"txa", "txb", "txc";
- fsl,asrc-rate = <48000>;
+ fsl,asrc-rate = <48000>;
fsl,asrc-width = <16>;
status = "okay";
};
diff --git a/dts/upstream/src/arm/nxp/imx/imx6ull-phytec-tauri.dtsi b/dts/upstream/src/arm/nxp/imx/imx6ull-phytec-tauri.dtsi
index 44cc4ff..d12fb44 100644
--- a/dts/upstream/src/arm/nxp/imx/imx6ull-phytec-tauri.dtsi
+++ b/dts/upstream/src/arm/nxp/imx/imx6ull-phytec-tauri.dtsi
@@ -116,7 +116,7 @@
tpm_tis: tpm@1 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_tpm>;
- compatible = "tcg,tpm_tis-spi";
+ compatible = "infineon,slb9670", "tcg,tpm_tis-spi";
reg = <1>;
spi-max-frequency = <20000000>;
interrupt-parent = <&gpio5>;
diff --git a/dts/upstream/src/arm/nxp/imx/imx7-tqma7.dtsi b/dts/upstream/src/arm/nxp/imx/imx7-tqma7.dtsi
index fe42b0a..3fc3130 100644
--- a/dts/upstream/src/arm/nxp/imx/imx7-tqma7.dtsi
+++ b/dts/upstream/src/arm/nxp/imx/imx7-tqma7.dtsi
@@ -128,11 +128,16 @@
};
};
- /* NXP SE97BTP with temperature sensor + eeprom */
+ /* LM75A temperature sensor, TQMa7x 01xx */
+ lm75a: temperature-sensor@48 {
+ compatible = "national,lm75a";
+ reg = <0x48>;
+ };
+
+ /* NXP SE97BTP with temperature sensor + eeprom, TQMa7x 02xx */
se97b: temperature-sensor-eeprom@1e {
compatible = "nxp,se97b", "jedec,jc-42.4-temp";
reg = <0x1e>;
- status = "okay";
};
/* ST M24C64 */
diff --git a/dts/upstream/src/arm/nxp/imx/imx7d-colibri-emmc.dtsi b/dts/upstream/src/arm/nxp/imx/imx7d-colibri-emmc.dtsi
index 3740e34..9670f45 100644
--- a/dts/upstream/src/arm/nxp/imx/imx7d-colibri-emmc.dtsi
+++ b/dts/upstream/src/arm/nxp/imx/imx7d-colibri-emmc.dtsi
@@ -11,6 +11,10 @@
/* Required to properly pass MAC addresses from bootloader. */
ethernet0 = &fec1;
ethernet1 = &fec2;
+ mmc0 = &usdhc3; /* eMMC */
+ mmc1 = &usdhc1; /* MMC/SD slot */
+ /delete-property/ mmc2;
+ /delete-property/ mmc3;
};
memory@80000000 {
diff --git a/dts/upstream/src/arm/nxp/imx/imx7d-flex-concentrator.dts b/dts/upstream/src/arm/nxp/imx/imx7d-flex-concentrator.dts
index 3a72384..9984b34 100644
--- a/dts/upstream/src/arm/nxp/imx/imx7d-flex-concentrator.dts
+++ b/dts/upstream/src/arm/nxp/imx/imx7d-flex-concentrator.dts
@@ -130,7 +130,7 @@
* TCG specification - Section 6.4.1 Clocking:
* TPM shall support a SPI clock frequency range of 10-24 MHz.
*/
- st33htph: tpm-tis@0 {
+ st33htph: tpm@0 {
compatible = "st,st33htpm-spi", "tcg,tpm_tis-spi";
reg = <0>;
spi-max-frequency = <24000000>;
diff --git a/dts/upstream/src/arm/nxp/imx/imx7d-meerkat96.dts b/dts/upstream/src/arm/nxp/imx/imx7d-meerkat96.dts
index dd8003b..f0fda15 100644
--- a/dts/upstream/src/arm/nxp/imx/imx7d-meerkat96.dts
+++ b/dts/upstream/src/arm/nxp/imx/imx7d-meerkat96.dts
@@ -212,7 +212,7 @@
keep-power-in-suspend;
wakeup-source;
vmmc-supply = <®_wlreg_on>;
- vqmmc-supply =<®_3p3v>;
+ vqmmc-supply = <®_3p3v>;
status = "okay";
brcmf: wifi@1 {
diff --git a/dts/upstream/src/arm/nxp/imx/imx7d-pico-dwarf.dts b/dts/upstream/src/arm/nxp/imx/imx7d-pico-dwarf.dts
index 12361fc..1b96565 100644
--- a/dts/upstream/src/arm/nxp/imx/imx7d-pico-dwarf.dts
+++ b/dts/upstream/src/arm/nxp/imx/imx7d-pico-dwarf.dts
@@ -63,6 +63,7 @@
gpio-controller;
#gpio-cells = <2>;
#interrupt-cells = <2>;
+ interrupt-controller;
reg = <0x25>;
};
diff --git a/dts/upstream/src/arm/nxp/imx/imx7d-pico.dtsi b/dts/upstream/src/arm/nxp/imx/imx7d-pico.dtsi
index c5eefe8..8d5037a 100644
--- a/dts/upstream/src/arm/nxp/imx/imx7d-pico.dtsi
+++ b/dts/upstream/src/arm/nxp/imx/imx7d-pico.dtsi
@@ -108,6 +108,14 @@
assigned-clock-rates = <0>, <32768>;
};
+&cpu0 {
+ cpu-supply = <&sw1a_reg>;
+};
+
+&cpu1 {
+ cpu-supply = <&sw1a_reg>;
+};
+
&ecspi3 {
cs-gpios = <&gpio4 11 GPIO_ACTIVE_LOW>;
pinctrl-names = "default";
diff --git a/dts/upstream/src/arm/nxp/imx/imx7d-smegw01.dts b/dts/upstream/src/arm/nxp/imx/imx7d-smegw01.dts
index 85b97b5..7ed27c7 100644
--- a/dts/upstream/src/arm/nxp/imx/imx7d-smegw01.dts
+++ b/dts/upstream/src/arm/nxp/imx/imx7d-smegw01.dts
@@ -149,7 +149,7 @@
&i2c2 {
pinctrl-names = "default";
- pinctrl-0 =<&pinctrl_i2c2>;
+ pinctrl-0 = <&pinctrl_i2c2>;
clock-frequency = <100000>;
status = "okay";
diff --git a/dts/upstream/src/arm/nxp/imx/imx7d.dtsi b/dts/upstream/src/arm/nxp/imx/imx7d.dtsi
index 4b94b8a..0484e34 100644
--- a/dts/upstream/src/arm/nxp/imx/imx7d.dtsi
+++ b/dts/upstream/src/arm/nxp/imx/imx7d.dtsi
@@ -217,9 +217,6 @@
};
&ca_funnel_in_ports {
- #address-cells = <1>;
- #size-cells = <0>;
-
port@1 {
reg = <1>;
ca_funnel_in_port1: endpoint {
diff --git a/dts/upstream/src/arm/nxp/imx/imx7s.dtsi b/dts/upstream/src/arm/nxp/imx/imx7s.dtsi
index 5387da8..9c81c6b 100644
--- a/dts/upstream/src/arm/nxp/imx/imx7s.dtsi
+++ b/dts/upstream/src/arm/nxp/imx/imx7s.dtsi
@@ -183,6 +183,15 @@
interrupt-parent = <&gpc>;
ranges;
+ ocram: sram@900000 {
+ compatible = "mmio-sram";
+ reg = <0x00900000 0x20000>;
+ ranges = <0 0x00900000 0x20000>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ clocks = <&clks IMX7D_OCRAM_CLK>;
+ };
+
funnel@30041000 {
compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
reg = <0x30041000 0x1000>;
@@ -190,7 +199,11 @@
clock-names = "apb_pclk";
ca_funnel_in_ports: in-ports {
- port {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
ca_funnel_in_port0: endpoint {
remote-endpoint = <&etm0_out_port>;
};
@@ -605,6 +618,7 @@
nvmem-cells = <&tempmon_calib>, <&fuse_grade>;
nvmem-cell-names = "calib", "temp_grade";
clocks = <&clks IMX7D_PLL_SYS_MAIN_CLK>;
+ #thermal-sensor-cells = <0>;
};
};
@@ -720,6 +734,8 @@
clocks = <&clks IMX7D_ECSPI4_ROOT_CLK>,
<&clks IMX7D_ECSPI4_ROOT_CLK>;
clock-names = "ipg", "per";
+ dma-names = "rx", "tx";
+ dmas = <&sdma 6 7 1>, <&sdma 7 7 2>;
status = "disabled";
};
@@ -811,7 +827,7 @@
};
lcdif: lcdif@30730000 {
- compatible = "fsl,imx7d-lcdif", "fsl,imx28-lcdif";
+ compatible = "fsl,imx7d-lcdif", "fsl,imx6sx-lcdif";
reg = <0x30730000 0x10000>;
interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clks IMX7D_LCDIF_PIXEL_ROOT_CLK>,
@@ -850,6 +866,26 @@
};
};
};
+
+ mipi_dsi: dsi@30760000 {
+ compatible = "fsl,imx7d-mipi-dsim", "fsl,imx8mm-mipi-dsim";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0x30760000 0x400>;
+ clocks = <&clks IMX7D_MIPI_DSI_ROOT_CLK>,
+ <&clks IMX7D_MIPI_DPHY_ROOT_CLK>;
+ clock-names = "bus_clk", "sclk_mipi";
+ assigned-clocks = <&clks IMX7D_MIPI_DSI_ROOT_SRC>,
+ <&clks IMX7D_PLL_SYS_PFD5_CLK>;
+ assigned-clock-parents = <&clks IMX7D_PLL_SYS_PFD5_CLK>;
+ assigned-clock-rates = <0>, <333000000>;
+ power-domains = <&pgc_mipi_phy>;
+ interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>;
+ samsung,burst-clock-frequency = <891000000>;
+ samsung,esc-clock-frequency = <20000000>;
+ samsung,pll-clock-frequency = <24000000>;
+ status = "disabled";
+ };
};
aips3: bus@30800000 {
@@ -875,6 +911,8 @@
clocks = <&clks IMX7D_ECSPI1_ROOT_CLK>,
<&clks IMX7D_ECSPI1_ROOT_CLK>;
clock-names = "ipg", "per";
+ dma-names = "rx", "tx";
+ dmas = <&sdma 0 7 1>, <&sdma 1 7 2>;
status = "disabled";
};
@@ -887,6 +925,8 @@
clocks = <&clks IMX7D_ECSPI2_ROOT_CLK>,
<&clks IMX7D_ECSPI2_ROOT_CLK>;
clock-names = "ipg", "per";
+ dma-names = "rx", "tx";
+ dmas = <&sdma 2 7 1>, <&sdma 3 7 2>;
status = "disabled";
};
@@ -899,6 +939,8 @@
clocks = <&clks IMX7D_ECSPI3_ROOT_CLK>,
<&clks IMX7D_ECSPI3_ROOT_CLK>;
clock-names = "ipg", "per";
+ dma-names = "rx", "tx";
+ dmas = <&sdma 4 7 1>, <&sdma 5 7 2>;
status = "disabled";
};
@@ -1275,7 +1317,7 @@
gpmi: nand-controller@33002000 {
compatible = "fsl,imx7d-gpmi-nand";
#address-cells = <1>;
- #size-cells = <1>;
+ #size-cells = <0>;
reg = <0x33002000 0x2000>, <0x33004000 0x4000>;
reg-names = "gpmi-nand", "bch";
interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
diff --git a/dts/upstream/src/arm/nxp/imx/mba6ulx.dtsi b/dts/upstream/src/arm/nxp/imx/mba6ulx.dtsi
index 5a8b867..e78d0a7 100644
--- a/dts/upstream/src/arm/nxp/imx/mba6ulx.dtsi
+++ b/dts/upstream/src/arm/nxp/imx/mba6ulx.dtsi
@@ -467,7 +467,7 @@
pinctrl_pwm2: pwm2grp {
fsl,pins = <
- /* 100 k PD, DSE 120 OHM, SPPEED LO */
+ /* 100 k PD, DSE 120 OHM, SPEED LO */
MX6UL_PAD_GPIO1_IO09__PWM2_OUT 0x00003050
>;
};
diff --git a/dts/upstream/src/arm/nxp/lpc/lpc18xx.dtsi b/dts/upstream/src/arm/nxp/lpc/lpc18xx.dtsi
index 9cf09c1..6dd7329 100644
--- a/dts/upstream/src/arm/nxp/lpc/lpc18xx.dtsi
+++ b/dts/upstream/src/arm/nxp/lpc/lpc18xx.dtsi
@@ -74,7 +74,7 @@
sct_pwm: pwm@40000000 {
compatible = "nxp,lpc1850-sct-pwm";
reg = <0x40000000 0x1000>;
- clocks =<&ccu1 CLK_CPU_SCT>;
+ clocks = <&ccu1 CLK_CPU_SCT>;
clock-names = "pwm";
resets = <&rgu 37>;
#pwm-cells = <3>;
diff --git a/dts/upstream/src/arm/nxp/ls/ls1021a.dtsi b/dts/upstream/src/arm/nxp/ls/ls1021a.dtsi
index 49c78c8..d471cc5 100644
--- a/dts/upstream/src/arm/nxp/ls/ls1021a.dtsi
+++ b/dts/upstream/src/arm/nxp/ls/ls1021a.dtsi
@@ -112,7 +112,7 @@
compatible = "fsl,ls1021a-msi";
reg = <0x0 0x1570e00 0x0 0x8>;
msi-controller;
- interrupts = <GIC_SPI 179 IRQ_TYPE_LEVEL_HIGH>;
+ interrupts = <GIC_SPI 179 IRQ_TYPE_LEVEL_HIGH>;
};
msi2: msi-controller@1570e08 {
diff --git a/dts/upstream/src/arm/nxp/mxs/imx23-sansa.dts b/dts/upstream/src/arm/nxp/mxs/imx23-sansa.dts
index 636cf09..b23e7ad 100644
--- a/dts/upstream/src/arm/nxp/mxs/imx23-sansa.dts
+++ b/dts/upstream/src/arm/nxp/mxs/imx23-sansa.dts
@@ -175,10 +175,8 @@
#address-cells = <1>;
#size-cells = <0>;
compatible = "i2c-gpio";
- gpios = <
- &gpio1 24 0 /* SDA */
- &gpio1 22 0 /* SCL */
- >;
+ sda-gpios = <&gpio1 24 0>;
+ scl-gpios = <&gpio1 22 0>;
i2c-gpio,delay-us = <2>; /* ~100 kHz */
};
@@ -186,10 +184,8 @@
#address-cells = <1>;
#size-cells = <0>;
compatible = "i2c-gpio";
- gpios = <
- &gpio0 31 0 /* SDA */
- &gpio0 30 0 /* SCL */
- >;
+ sda-gpios = <&gpio0 31 0>;
+ scl-gpios = <&gpio0 30 0>;
i2c-gpio,delay-us = <2>; /* ~100 kHz */
touch: touch@20 {
diff --git a/dts/upstream/src/arm/nxp/mxs/imx23.dtsi b/dts/upstream/src/arm/nxp/mxs/imx23.dtsi
index fdf18b7..0309592 100644
--- a/dts/upstream/src/arm/nxp/mxs/imx23.dtsi
+++ b/dts/upstream/src/arm/nxp/mxs/imx23.dtsi
@@ -110,7 +110,7 @@
reg = <0x80018000 0x2000>;
gpio0: gpio@0 {
- compatible = "fsl,imx23-gpio", "fsl,mxs-gpio";
+ compatible = "fsl,imx23-gpio";
reg = <0>;
interrupts = <16>;
gpio-controller;
@@ -120,7 +120,7 @@
};
gpio1: gpio@1 {
- compatible = "fsl,imx23-gpio", "fsl,mxs-gpio";
+ compatible = "fsl,imx23-gpio";
reg = <1>;
interrupts = <17>;
gpio-controller;
@@ -130,7 +130,7 @@
};
gpio2: gpio@2 {
- compatible = "fsl,imx23-gpio", "fsl,mxs-gpio";
+ compatible = "fsl,imx23-gpio";
reg = <2>;
interrupts = <18>;
gpio-controller;
@@ -412,7 +412,7 @@
status = "disabled";
};
- dma_apbx: dma-apbx@80024000 {
+ dma_apbx: dma-controller@80024000 {
compatible = "fsl,imx23-dma-apbx";
reg = <0x80024000 0x2000>;
interrupts = <7>, <5>, <9>, <26>,
@@ -484,7 +484,7 @@
ranges;
clks: clkctrl@80040000 {
- compatible = "fsl,imx23-clkctrl", "fsl,clkctrl";
+ compatible = "fsl,imx23-clkctrl";
reg = <0x80040000 0x2000>;
#clock-cells = <1>;
};
diff --git a/dts/upstream/src/arm/nxp/mxs/imx28-lwe.dtsi b/dts/upstream/src/arm/nxp/mxs/imx28-lwe.dtsi
index bb971e6..69fcb0d 100644
--- a/dts/upstream/src/arm/nxp/mxs/imx28-lwe.dtsi
+++ b/dts/upstream/src/arm/nxp/mxs/imx28-lwe.dtsi
@@ -18,6 +18,7 @@
memory@40000000 {
reg = <0x40000000 0x08000000>;
+ device_type = "memory";
};
reg_3v3: regulator-reg-3v3 {
diff --git a/dts/upstream/src/arm/nxp/mxs/imx28-tx28.dts b/dts/upstream/src/arm/nxp/mxs/imx28-tx28.dts
index 153e401..5485fe11 100644
--- a/dts/upstream/src/arm/nxp/mxs/imx28-tx28.dts
+++ b/dts/upstream/src/arm/nxp/mxs/imx28-tx28.dts
@@ -260,6 +260,7 @@
sgtl5000: sgtl5000@a {
compatible = "fsl,sgtl5000";
reg = <0x0a>;
+ #sound-dai-cells = <0>;
VDDA-supply = <®_2p5v>;
VDDIO-supply = <®_3p3v>;
clocks = <&mclk>;
diff --git a/dts/upstream/src/arm/nxp/mxs/imx28.dtsi b/dts/upstream/src/arm/nxp/mxs/imx28.dtsi
index 6932d23..4817fba 100644
--- a/dts/upstream/src/arm/nxp/mxs/imx28.dtsi
+++ b/dts/upstream/src/arm/nxp/mxs/imx28.dtsi
@@ -164,7 +164,7 @@
reg = <0x80018000 0x2000>;
gpio0: gpio@0 {
- compatible = "fsl,imx28-gpio", "fsl,mxs-gpio";
+ compatible = "fsl,imx28-gpio";
reg = <0>;
interrupts = <127>;
gpio-controller;
@@ -174,7 +174,7 @@
};
gpio1: gpio@1 {
- compatible = "fsl,imx28-gpio", "fsl,mxs-gpio";
+ compatible = "fsl,imx28-gpio";
reg = <1>;
interrupts = <126>;
gpio-controller;
@@ -184,7 +184,7 @@
};
gpio2: gpio@2 {
- compatible = "fsl,imx28-gpio", "fsl,mxs-gpio";
+ compatible = "fsl,imx28-gpio";
reg = <2>;
interrupts = <125>;
gpio-controller;
@@ -194,7 +194,7 @@
};
gpio3: gpio@3 {
- compatible = "fsl,imx28-gpio", "fsl,mxs-gpio";
+ compatible = "fsl,imx28-gpio";
reg = <3>;
interrupts = <124>;
gpio-controller;
@@ -204,7 +204,7 @@
};
gpio4: gpio@4 {
- compatible = "fsl,imx28-gpio", "fsl,mxs-gpio";
+ compatible = "fsl,imx28-gpio";
reg = <4>;
interrupts = <123>;
gpio-controller;
@@ -990,7 +990,7 @@
status = "disabled";
};
- dma_apbx: dma-apbx@80024000 {
+ dma_apbx: dma-controller@80024000 {
compatible = "fsl,imx28-dma-apbx";
reg = <0x80024000 0x2000>;
interrupts = <78>, <79>, <66>, <0>,
@@ -1100,7 +1100,7 @@
ranges;
clks: clkctrl@80040000 {
- compatible = "fsl,imx28-clkctrl", "fsl,clkctrl";
+ compatible = "fsl,imx28-clkctrl";
reg = <0x80040000 0x2000>;
#clock-cells = <1>;
};
diff --git a/dts/upstream/src/arm/nxp/vf/vf-colibri-eval-v3.dtsi b/dts/upstream/src/arm/nxp/vf/vf-colibri-eval-v3.dtsi
index 14c411f..5a19da9 100644
--- a/dts/upstream/src/arm/nxp/vf/vf-colibri-eval-v3.dtsi
+++ b/dts/upstream/src/arm/nxp/vf/vf-colibri-eval-v3.dtsi
@@ -55,7 +55,7 @@
brightness-levels = <0 4 8 16 32 64 128 255>;
default-brightness-level = <6>;
power-supply = <®_3v3>;
- status = "okay";
+ status = "okay";
};
&dcu0 {
diff --git a/dts/upstream/src/arm/nxp/vf/vf610-bk4.dts b/dts/upstream/src/arm/nxp/vf/vf610-bk4.dts
index e4f691d..722182f 100644
--- a/dts/upstream/src/arm/nxp/vf/vf610-bk4.dts
+++ b/dts/upstream/src/arm/nxp/vf/vf610-bk4.dts
@@ -68,7 +68,7 @@
#address-cells = <1>;
#size-cells = <0>;
/* PTD12 ->RPIO[91] */
- sck-gpios = <&gpio2 27 GPIO_ACTIVE_LOW>;
+ sck-gpios = <&gpio2 27 GPIO_ACTIVE_LOW>;
/* PTD10 ->RPIO[89] */
miso-gpios = <&gpio2 25 GPIO_ACTIVE_HIGH>;
num-chipselects = <0>;
@@ -79,7 +79,7 @@
gpio-controller;
#gpio-cells = <2>;
/* PTB18 -> RGPIO[40] */
- load-gpios = <&gpio1 8 GPIO_ACTIVE_LOW>;
+ load-gpios = <&gpio1 8 GPIO_ACTIVE_LOW>;
spi-max-frequency = <100000>;
};
};
diff --git a/dts/upstream/src/arm/nxp/vf/vf610-zii-cfu1.dts b/dts/upstream/src/arm/nxp/vf/vf610-zii-cfu1.dts
index 1a19aec..7e72f86 100644
--- a/dts/upstream/src/arm/nxp/vf/vf610-zii-cfu1.dts
+++ b/dts/upstream/src/arm/nxp/vf/vf610-zii-cfu1.dts
@@ -162,7 +162,7 @@
suppress-preamble;
status = "okay";
- switch0: switch0@0 {
+ switch0: ethernet-switch@0 {
compatible = "marvell,mv88e6085";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_switch>;
@@ -173,26 +173,26 @@
interrupt-controller;
#interrupt-cells = <2>;
- ports {
+ ethernet-ports {
#address-cells = <1>;
#size-cells = <0>;
- port@0 {
+ ethernet-port@0 {
reg = <0>;
label = "eth_cu_1000_1";
};
- port@1 {
+ ethernet-port@1 {
reg = <1>;
label = "eth_cu_1000_2";
};
- port@2 {
+ ethernet-port@2 {
reg = <2>;
label = "eth_cu_1000_3";
};
- port@5 {
+ ethernet-port@5 {
reg = <5>;
label = "eth_fc_1000_1";
phy-mode = "1000base-x";
@@ -200,7 +200,7 @@
sfp = <&sff>;
};
- port@6 {
+ ethernet-port@6 {
reg = <6>;
phy-mode = "rmii";
ethernet = <&fec1>;
diff --git a/dts/upstream/src/arm/nxp/vf/vf610-zii-dev-rev-b.dts b/dts/upstream/src/arm/nxp/vf/vf610-zii-dev-rev-b.dts
index 16b4e06..029f49b 100644
--- a/dts/upstream/src/arm/nxp/vf/vf610-zii-dev-rev-b.dts
+++ b/dts/upstream/src/arm/nxp/vf/vf610-zii-dev-rev-b.dts
@@ -294,11 +294,11 @@
pinctrl-names = "default";
#address-cells = <1>;
#size-cells = <0>;
- sck-gpios = <&gpio1 12 GPIO_ACTIVE_HIGH>;
+ sck-gpios = <&gpio1 12 GPIO_ACTIVE_HIGH>;
mosi-gpios = <&gpio1 11 GPIO_ACTIVE_HIGH>;
miso-gpios = <&gpio1 10 GPIO_ACTIVE_HIGH>;
- cs-gpios = <&gpio1 9 GPIO_ACTIVE_LOW
- &gpio1 8 GPIO_ACTIVE_HIGH>;
+ cs-gpios = <&gpio1 9 GPIO_ACTIVE_LOW
+ &gpio1 8 GPIO_ACTIVE_HIGH>;
num-chipselects = <2>;
flash@0 {
@@ -338,6 +338,7 @@
reg = <0x22>;
gpio-controller;
#gpio-cells = <2>;
+ #interrupt-cells = <2>;
interrupt-controller;
interrupt-parent = <&gpio3>;
interrupts = <2 IRQ_TYPE_LEVEL_LOW>;
diff --git a/dts/upstream/src/arm/nxp/vf/vf610-zii-scu4-aib.dts b/dts/upstream/src/arm/nxp/vf/vf610-zii-scu4-aib.dts
index df13354..77492ee 100644
--- a/dts/upstream/src/arm/nxp/vf/vf610-zii-scu4-aib.dts
+++ b/dts/upstream/src/arm/nxp/vf/vf610-zii-scu4-aib.dts
@@ -47,17 +47,17 @@
#address-cells = <1>;
#size-cells = <0>;
- switch0: switch0@0 {
+ switch0: ethernet-switch@0 {
compatible = "marvell,mv88e6190";
reg = <0>;
dsa,member = <0 0>;
eeprom-length = <65536>;
- ports {
+ ethernet-ports {
#address-cells = <1>;
#size-cells = <0>;
- port@0 {
+ ethernet-port@0 {
reg = <0>;
phy-mode = "rmii";
ethernet = <&fec1>;
@@ -68,37 +68,37 @@
};
};
- port@1 {
+ ethernet-port@1 {
reg = <1>;
label = "aib2main_1";
};
- port@2 {
+ ethernet-port@2 {
reg = <2>;
label = "aib2main_2";
};
- port@3 {
+ ethernet-port@3 {
reg = <3>;
label = "eth_cu_1000_5";
};
- port@4 {
+ ethernet-port@4 {
reg = <4>;
label = "eth_cu_1000_6";
};
- port@5 {
+ ethernet-port@5 {
reg = <5>;
label = "eth_cu_1000_4";
};
- port@6 {
+ ethernet-port@6 {
reg = <6>;
label = "eth_cu_1000_7";
};
- port@7 {
+ ethernet-port@7 {
reg = <7>;
label = "modem_pic";
@@ -108,7 +108,7 @@
};
};
- switch0port10: port@10 {
+ switch0port10: ethernet-port@10 {
reg = <10>;
label = "dsa";
phy-mode = "xgmii";
@@ -130,32 +130,32 @@
#address-cells = <1>;
#size-cells = <0>;
- switch1: switch1@0 {
+ switch1: ethernet-switch@0 {
compatible = "marvell,mv88e6190";
reg = <0>;
dsa,member = <0 1>;
eeprom-length = <65536>;
- ports {
+ ethernet-ports {
#address-cells = <1>;
#size-cells = <0>;
- port@1 {
+ ethernet-port@1 {
reg = <1>;
label = "eth_cu_1000_3";
};
- port@2 {
+ ethernet-port@2 {
reg = <2>;
label = "eth_cu_100_2";
};
- port@3 {
+ ethernet-port@3 {
reg = <3>;
label = "eth_cu_100_3";
};
- switch1port9: port@9 {
+ switch1port9: ethernet-port@9 {
reg = <9>;
label = "dsa";
phy-mode = "xgmii";
@@ -168,7 +168,7 @@
};
};
- switch1port10: port@10 {
+ switch1port10: ethernet-port@10 {
reg = <10>;
label = "dsa";
phy-mode = "xgmii";
@@ -188,17 +188,17 @@
#address-cells = <1>;
#size-cells = <0>;
- switch2: switch2@0 {
+ switch2: ethernet-switch@0 {
compatible = "marvell,mv88e6190";
reg = <0>;
dsa,member = <0 2>;
eeprom-length = <65536>;
- ports {
+ ethernet-ports {
#address-cells = <1>;
#size-cells = <0>;
- port@2 {
+ ethernet-port@2 {
reg = <2>;
label = "eth_fc_1000_2";
phy-mode = "1000base-x";
@@ -206,7 +206,7 @@
sfp = <&sff1>;
};
- port@3 {
+ ethernet-port@3 {
reg = <3>;
label = "eth_fc_1000_3";
phy-mode = "1000base-x";
@@ -214,7 +214,7 @@
sfp = <&sff2>;
};
- port@4 {
+ ethernet-port@4 {
reg = <4>;
label = "eth_fc_1000_4";
phy-mode = "1000base-x";
@@ -222,7 +222,7 @@
sfp = <&sff3>;
};
- port@5 {
+ ethernet-port@5 {
reg = <5>;
label = "eth_fc_1000_5";
phy-mode = "1000base-x";
@@ -230,7 +230,7 @@
sfp = <&sff4>;
};
- port@6 {
+ ethernet-port@6 {
reg = <6>;
label = "eth_fc_1000_6";
phy-mode = "1000base-x";
@@ -238,7 +238,7 @@
sfp = <&sff5>;
};
- port@7 {
+ ethernet-port@7 {
reg = <7>;
label = "eth_fc_1000_7";
phy-mode = "1000base-x";
@@ -246,7 +246,7 @@
sfp = <&sff6>;
};
- port@9 {
+ ethernet-port@9 {
reg = <9>;
label = "eth_fc_1000_1";
phy-mode = "1000base-x";
@@ -254,7 +254,7 @@
sfp = <&sff0>;
};
- switch2port10: port@10 {
+ switch2port10: ethernet-port@10 {
reg = <10>;
label = "dsa";
phy-mode = "2500base-x";
@@ -276,17 +276,17 @@
#address-cells = <1>;
#size-cells = <0>;
- switch3: switch3@0 {
+ switch3: ethernet-switch@0 {
compatible = "marvell,mv88e6190";
reg = <0>;
dsa,member = <0 3>;
eeprom-length = <65536>;
- ports {
+ ethernet-ports {
#address-cells = <1>;
#size-cells = <0>;
- port@2 {
+ ethernet-port@2 {
reg = <2>;
label = "eth_fc_1000_8";
phy-mode = "1000base-x";
@@ -294,7 +294,7 @@
sfp = <&sff7>;
};
- port@3 {
+ ethernet-port@3 {
reg = <3>;
label = "eth_fc_1000_9";
phy-mode = "1000base-x";
@@ -302,7 +302,7 @@
sfp = <&sff8>;
};
- port@4 {
+ ethernet-port@4 {
reg = <4>;
label = "eth_fc_1000_10";
phy-mode = "1000base-x";
@@ -310,7 +310,7 @@
sfp = <&sff9>;
};
- switch3port9: port@9 {
+ switch3port9: ethernet-port@9 {
reg = <9>;
label = "dsa";
phy-mode = "2500base-x";
@@ -322,7 +322,7 @@
};
};
- switch3port10: port@10 {
+ switch3port10: ethernet-port@10 {
reg = <10>;
label = "dsa";
phy-mode = "xgmii";
diff --git a/dts/upstream/src/arm/nxp/vf/vf610-zii-spb4.dts b/dts/upstream/src/arm/nxp/vf/vf610-zii-spb4.dts
index 1461804..2a49046 100644
--- a/dts/upstream/src/arm/nxp/vf/vf610-zii-spb4.dts
+++ b/dts/upstream/src/arm/nxp/vf/vf610-zii-spb4.dts
@@ -123,7 +123,7 @@
suppress-preamble;
status = "okay";
- switch0: switch0@0 {
+ switch0: ethernet-switch@0 {
compatible = "marvell,mv88e6190";
pinctrl-0 = <&pinctrl_gpio_switch0>;
pinctrl-names = "default";
@@ -134,11 +134,11 @@
interrupt-controller;
#interrupt-cells = <2>;
- ports {
+ ethernet-ports {
#address-cells = <1>;
#size-cells = <0>;
- port@0 {
+ ethernet-port@0 {
reg = <0>;
phy-mode = "rmii";
ethernet = <&fec1>;
@@ -149,32 +149,32 @@
};
};
- port@1 {
+ ethernet-port@1 {
reg = <1>;
label = "eth_cu_1000_1";
};
- port@2 {
+ ethernet-port@2 {
reg = <2>;
label = "eth_cu_1000_2";
};
- port@3 {
+ ethernet-port@3 {
reg = <3>;
label = "eth_cu_1000_3";
};
- port@4 {
+ ethernet-port@4 {
reg = <4>;
label = "eth_cu_1000_4";
};
- port@5 {
+ ethernet-port@5 {
reg = <5>;
label = "eth_cu_1000_5";
};
- port@6 {
+ ethernet-port@6 {
reg = <6>;
label = "eth_cu_1000_6";
};
diff --git a/dts/upstream/src/arm/nxp/vf/vf610-zii-ssmb-dtu.dts b/dts/upstream/src/arm/nxp/vf/vf610-zii-ssmb-dtu.dts
index 463c245..078d869 100644
--- a/dts/upstream/src/arm/nxp/vf/vf610-zii-ssmb-dtu.dts
+++ b/dts/upstream/src/arm/nxp/vf/vf610-zii-ssmb-dtu.dts
@@ -112,7 +112,7 @@
suppress-preamble;
status = "okay";
- switch0: switch0@0 {
+ switch0: ethernet-switch@0 {
compatible = "marvell,mv88e6190";
pinctrl-0 = <&pinctrl_gpio_switch0>;
pinctrl-names = "default";
@@ -123,11 +123,11 @@
interrupt-controller;
#interrupt-cells = <2>;
- ports {
+ ethernet-ports {
#address-cells = <1>;
#size-cells = <0>;
- port@0 {
+ ethernet-port@0 {
reg = <0>;
phy-mode = "rmii";
ethernet = <&fec1>;
@@ -138,27 +138,27 @@
};
};
- port@1 {
+ ethernet-port@1 {
reg = <1>;
label = "eth_cu_100_3";
};
- port@5 {
+ ethernet-port@5 {
reg = <5>;
label = "eth_cu_1000_4";
};
- port@6 {
+ ethernet-port@6 {
reg = <6>;
label = "eth_cu_1000_5";
};
- port@8 {
+ ethernet-port@8 {
reg = <8>;
label = "eth_cu_1000_1";
};
- port@9 {
+ ethernet-port@9 {
reg = <9>;
label = "eth_cu_1000_2";
phy-handle = <&phy9>;
@@ -167,12 +167,12 @@
};
};
- mdio1 {
+ mdio-external {
compatible = "marvell,mv88e6xxx-mdio-external";
#address-cells = <1>;
#size-cells = <0>;
- phy9: phy9@0 {
+ phy9: ethernet-phy@0 {
compatible = "ethernet-phy-ieee802.3-c45";
pinctrl-0 = <&pinctrl_gpio_phy9>;
pinctrl-names = "default";
diff --git a/dts/upstream/src/arm/nxp/vf/vf610-zii-ssmb-spu3.dts b/dts/upstream/src/arm/nxp/vf/vf610-zii-ssmb-spu3.dts
index f5ae0d5..22c8f44 100644
--- a/dts/upstream/src/arm/nxp/vf/vf610-zii-ssmb-spu3.dts
+++ b/dts/upstream/src/arm/nxp/vf/vf610-zii-ssmb-spu3.dts
@@ -137,7 +137,7 @@
suppress-preamble;
status = "okay";
- switch0: switch0@0 {
+ switch0: ethernet-switch@0 {
compatible = "marvell,mv88e6190";
pinctrl-0 = <&pinctrl_gpio_switch0>;
pinctrl-names = "default";
@@ -148,11 +148,11 @@
interrupt-controller;
#interrupt-cells = <2>;
- ports {
+ ethernet-ports {
#address-cells = <1>;
#size-cells = <0>;
- port@0 {
+ ethernet-port@0 {
reg = <0>;
phy-mode = "rmii";
ethernet = <&fec1>;
@@ -163,32 +163,32 @@
};
};
- port@1 {
+ ethernet-port@1 {
reg = <1>;
label = "eth_cu_1000_1";
};
- port@2 {
+ ethernet-port@2 {
reg = <2>;
label = "eth_cu_1000_2";
};
- port@3 {
+ ethernet-port@3 {
reg = <3>;
label = "eth_cu_1000_3";
};
- port@4 {
+ ethernet-port@4 {
reg = <4>;
label = "eth_cu_1000_4";
};
- port@5 {
+ ethernet-port@5 {
reg = <5>;
label = "eth_cu_1000_5";
};
- port@6 {
+ ethernet-port@6 {
reg = <6>;
label = "eth_cu_1000_6";
};
diff --git a/dts/upstream/src/arm/qcom/pm8018.dtsi b/dts/upstream/src/arm/qcom/pm8018.dtsi
new file mode 100644
index 0000000..22f3c7b
--- /dev/null
+++ b/dts/upstream/src/arm/qcom/pm8018.dtsi
@@ -0,0 +1,55 @@
+// SPDX-License-Identifier: GPL-2.0+ OR MIT
+/*
+ * Device Tree Source for Qualcomm PM8018
+ *
+ * Copyright (C) 2016 BayLibre, SAS.
+ * Author : Neil Armstrong <narmstrong@baylibre.com>
+ */
+
+&ssbi {
+ pm8018: pmic {
+ compatible = "qcom,pm8018", "qcom,pm8921";
+ #interrupt-cells = <2>;
+ interrupt-controller;
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ pwrkey@1c {
+ compatible = "qcom,pm8018-pwrkey",
+ "qcom,pm8921-pwrkey";
+ reg = <0x1c>;
+ interrupts-extended = <&pm8018 50 IRQ_TYPE_EDGE_RISING>,
+ <&pm8018 51 IRQ_TYPE_EDGE_RISING>;
+ debounce = <15625>;
+ pull-up;
+ };
+
+ pm8018_mpps: mpps@50 {
+ compatible = "qcom,pm8018-mpp", "qcom,ssbi-mpp";
+ reg = <0x50>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ gpio-ranges = <&pm8018_mpps 0 0 6>;
+ };
+
+ rtc@11d {
+ compatible = "qcom,pm8018-rtc", "qcom,pm8921-rtc";
+ reg = <0x11d>;
+ interrupts-extended = <&pm8018 39 IRQ_TYPE_EDGE_RISING>;
+ allow-set-time;
+ };
+
+ pm8018_gpio: gpio@150 {
+ compatible = "qcom,pm8058-gpio",
+ "qcom,ssbi-gpio";
+ reg = <0x150>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ gpio-controller;
+ gpio-ranges = <&pm8018_gpio 0 0 6>;
+ #gpio-cells = <2>;
+ };
+ };
+};
diff --git a/dts/upstream/src/arm/qcom/pm8058.dtsi b/dts/upstream/src/arm/qcom/pm8058.dtsi
new file mode 100644
index 0000000..984b797
--- /dev/null
+++ b/dts/upstream/src/arm/qcom/pm8058.dtsi
@@ -0,0 +1,159 @@
+// SPDX-License-Identifier: GPL-2.0
+
+&ssbi {
+ pm8058: pmic {
+ compatible = "qcom,pm8058";
+ #interrupt-cells = <2>;
+ interrupt-controller;
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ pwrkey@1c {
+ compatible = "qcom,pm8058-pwrkey";
+ reg = <0x1c>;
+ interrupts-extended = <&pm8058 50 IRQ_TYPE_EDGE_RISING>,
+ <&pm8058 51 IRQ_TYPE_EDGE_RISING>;
+ debounce = <15625>;
+ pull-up;
+ };
+
+ pm8058_led48: led@48 {
+ compatible = "qcom,pm8058-keypad-led";
+ reg = <0x48>;
+ status = "disabled";
+ };
+
+ vibrator@4a {
+ compatible = "qcom,pm8058-vib";
+ reg = <0x4a>;
+ };
+
+ pm8058_mpps: mpps@50 {
+ compatible = "qcom,pm8058-mpp",
+ "qcom,ssbi-mpp";
+ reg = <0x50>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ gpio-ranges = <&pm8058_mpps 0 0 12>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+
+ pm8058_led131: led@131 {
+ compatible = "qcom,pm8058-led";
+ reg = <0x131>;
+ status = "disabled";
+ };
+
+ pm8058_led132: led@132 {
+ compatible = "qcom,pm8058-led";
+ reg = <0x132>;
+ status = "disabled";
+ };
+
+ pm8058_led133: led@133 {
+ compatible = "qcom,pm8058-led";
+ reg = <0x133>;
+ status = "disabled";
+ };
+
+ pm8058_keypad: keypad@148 {
+ compatible = "qcom,pm8058-keypad";
+ reg = <0x148>;
+ interrupts-extended = <&pm8058 74 IRQ_TYPE_EDGE_RISING>,
+ <&pm8058 75 IRQ_TYPE_EDGE_RISING>;
+ debounce = <15>;
+ scan-delay = <32>;
+ row-hold = <91500>;
+ };
+
+ pm8058_gpio: gpio@150 {
+ compatible = "qcom,pm8058-gpio",
+ "qcom,ssbi-gpio";
+ reg = <0x150>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ gpio-controller;
+ gpio-ranges = <&pm8058_gpio 0 0 44>;
+ #gpio-cells = <2>;
+ };
+
+ pm8058_xoadc: xoadc@197 {
+ compatible = "qcom,pm8058-adc";
+ reg = <0x197>;
+ interrupts-extended = <&pm8058 76 IRQ_TYPE_EDGE_RISING>;
+ #address-cells = <2>;
+ #size-cells = <0>;
+ #io-channel-cells = <2>;
+
+ vcoin: adc-channel@0 {
+ reg = <0x00 0x00>;
+ };
+
+ vbat: adc-channel@1 {
+ reg = <0x00 0x01>;
+ };
+
+ dcin: adc-channel@2 {
+ reg = <0x00 0x02>;
+ };
+
+ ichg: adc-channel@3 {
+ reg = <0x00 0x03>;
+ };
+
+ vph_pwr: adc-channel@4 {
+ reg = <0x00 0x04>;
+ };
+
+ usb_vbus: adc-channel@a {
+ reg = <0x00 0x0a>;
+ };
+
+ die_temp: adc-channel@b {
+ reg = <0x00 0x0b>;
+ };
+
+ ref_625mv: adc-channel@c {
+ reg = <0x00 0x0c>;
+ };
+
+ ref_1250mv: adc-channel@d {
+ reg = <0x00 0x0d>;
+ };
+
+ ref_325mv: adc-channel@e {
+ reg = <0x00 0x0e>;
+ };
+
+ ref_muxoff: adc-channel@f {
+ reg = <0x00 0x0f>;
+ };
+ };
+
+ rtc@1e8 {
+ compatible = "qcom,pm8058-rtc";
+ reg = <0x1e8>;
+ interrupts-extended = <&pm8058 39 IRQ_TYPE_EDGE_RISING>;
+ allow-set-time;
+ };
+ };
+};
+
+/ {
+ /*
+ * These channels from the ADC are simply hardware monitors.
+ * That is why the ADC is referred to as "HKADC" - HouseKeeping
+ * ADC.
+ */
+ iio-hwmon {
+ compatible = "iio-hwmon";
+ io-channels = <&pm8058_xoadc 0x00 0x01>, /* Battery */
+ <&pm8058_xoadc 0x00 0x02>, /* DC in (charger) */
+ <&pm8058_xoadc 0x00 0x04>, /* VPH the main system voltage */
+ <&pm8058_xoadc 0x00 0x0b>, /* Die temperature */
+ <&pm8058_xoadc 0x00 0x0c>, /* Reference voltage 1.25V */
+ <&pm8058_xoadc 0x00 0x0d>, /* Reference voltage 0.625V */
+ <&pm8058_xoadc 0x00 0x0e>; /* Reference voltage 0.325V */
+ };
+};
diff --git a/dts/upstream/src/arm/qcom/qcom-pm8226.dtsi b/dts/upstream/src/arm/qcom/pm8226.dtsi
similarity index 99%
rename from dts/upstream/src/arm/qcom/qcom-pm8226.dtsi
rename to dts/upstream/src/arm/qcom/pm8226.dtsi
index 2413778..2fd4f13 100644
--- a/dts/upstream/src/arm/qcom/qcom-pm8226.dtsi
+++ b/dts/upstream/src/arm/qcom/pm8226.dtsi
@@ -82,6 +82,8 @@
"usb-valid",
"dc-valid";
+ status = "disabled";
+
chg_otg: otg-vbus { };
};
diff --git a/dts/upstream/src/arm/qcom/pm8821.dtsi b/dts/upstream/src/arm/qcom/pm8821.dtsi
new file mode 100644
index 0000000..064e3ba
--- /dev/null
+++ b/dts/upstream/src/arm/qcom/pm8821.dtsi
@@ -0,0 +1,22 @@
+// SPDX-License-Identifier: GPL-2.0
+
+/* This PMIC is used on a secondary SSBI bus */
+&ssbi2 {
+ pm8821: pmic {
+ compatible = "qcom,pm8821";
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ pm8821_mpps: mpps@50 {
+ compatible = "qcom,pm8821-mpp", "qcom,ssbi-mpp";
+ reg = <0x50>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ gpio-ranges = <&pm8821_mpps 0 0 4>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+ };
+};
diff --git a/dts/upstream/src/arm/qcom/qcom-pm8841.dtsi b/dts/upstream/src/arm/qcom/pm8841.dtsi
similarity index 100%
rename from dts/upstream/src/arm/qcom/qcom-pm8841.dtsi
rename to dts/upstream/src/arm/qcom/pm8841.dtsi
diff --git a/dts/upstream/src/arm/qcom/pm8921.dtsi b/dts/upstream/src/arm/qcom/pm8921.dtsi
new file mode 100644
index 0000000..058962a
--- /dev/null
+++ b/dts/upstream/src/arm/qcom/pm8921.dtsi
@@ -0,0 +1,137 @@
+// SPDX-License-Identifier: GPL-2.0
+
+&ssbi {
+ pm8921: pmic {
+ compatible = "qcom,pm8921";
+ #interrupt-cells = <2>;
+ interrupt-controller;
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ pwrkey@1c {
+ compatible = "qcom,pm8921-pwrkey";
+ reg = <0x1c>;
+ interrupts-extended = <&pm8921 50 IRQ_TYPE_EDGE_RISING>,
+ <&pm8921 51 IRQ_TYPE_EDGE_RISING>;
+ debounce = <15625>;
+ pull-up;
+ };
+
+ pm8921_mpps: mpps@50 {
+ compatible = "qcom,pm8921-mpp",
+ "qcom,ssbi-mpp";
+ reg = <0x50>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ gpio-ranges = <&pm8921_mpps 0 0 12>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+
+ rtc@11d {
+ compatible = "qcom,pm8921-rtc";
+ reg = <0x11d>;
+ interrupts-extended = <&pm8921 39 IRQ_TYPE_EDGE_RISING>;
+ allow-set-time;
+ };
+
+ pm8921_keypad: keypad@148 {
+ compatible = "qcom,pm8921-keypad";
+ reg = <0x148>;
+ interrupts-extended = <&pm8921 74 IRQ_TYPE_EDGE_RISING>,
+ <&pm8921 75 IRQ_TYPE_EDGE_RISING>;
+ debounce = <15>;
+ scan-delay = <32>;
+ row-hold = <91500>;
+ status = "disabled";
+ };
+
+ pm8921_gpio: gpio@150 {
+
+ compatible = "qcom,pm8921-gpio",
+ "qcom,ssbi-gpio";
+ reg = <0x150>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ gpio-controller;
+ gpio-ranges = <&pm8921_gpio 0 0 44>;
+ #gpio-cells = <2>;
+
+ };
+
+ pm8921_xoadc: xoadc@197 {
+ compatible = "qcom,pm8921-adc";
+ reg = <0x197>;
+ interrupts-extended = <&pm8921 78 IRQ_TYPE_EDGE_RISING>;
+ #address-cells = <2>;
+ #size-cells = <0>;
+ #io-channel-cells = <2>;
+
+ vcoin: adc-channel@0 {
+ reg = <0x00 0x00>;
+ };
+
+ vbat: adc-channel@1 {
+ reg = <0x00 0x01>;
+ };
+
+ dcin: adc-channel@2 {
+ reg = <0x00 0x02>;
+ };
+
+ vph_pwr: adc-channel@4 {
+ reg = <0x00 0x04>;
+ };
+
+ batt_therm: adc-channel@8 {
+ reg = <0x00 0x08>;
+ };
+
+ batt_id: adc-channel@9 {
+ reg = <0x00 0x09>;
+ };
+
+ usb_vbus: adc-channel@a {
+ reg = <0x00 0x0a>;
+ };
+
+ die_temp: adc-channel@b {
+ reg = <0x00 0x0b>;
+ };
+
+ ref_625mv: adc-channel@c {
+ reg = <0x00 0x0c>;
+ };
+
+ ref_1250mv: adc-channel@d {
+ reg = <0x00 0x0d>;
+ };
+
+ chg_temp: adc-channel@e {
+ reg = <0x00 0x0e>;
+ };
+
+ ref_muxoff: adc-channel@f {
+ reg = <0x00 0x0f>;
+ };
+ };
+ };
+};
+
+/ {
+ /*
+ * These channels from the ADC are simply hardware monitors.
+ * That is why the ADC is referred to as "HKADC" - HouseKeeping
+ * ADC.
+ */
+ iio-hwmon {
+ compatible = "iio-hwmon";
+ io-channels = <&pm8921_xoadc 0x00 0x01>, /* Battery */
+ <&pm8921_xoadc 0x00 0x02>, /* DC in (charger) */
+ <&pm8921_xoadc 0x00 0x04>, /* VPH the main system voltage */
+ <&pm8921_xoadc 0x00 0x0b>, /* Die temperature */
+ <&pm8921_xoadc 0x00 0x0c>, /* Reference voltage 1.25V */
+ <&pm8921_xoadc 0x00 0x0d>, /* Reference voltage 0.625V */
+ <&pm8921_xoadc 0x00 0x0e>; /* Charger temperature */
+ };
+};
diff --git a/dts/upstream/src/arm/qcom/qcom-pm8941.dtsi b/dts/upstream/src/arm/qcom/pm8941.dtsi
similarity index 99%
rename from dts/upstream/src/arm/qcom/qcom-pm8941.dtsi
rename to dts/upstream/src/arm/qcom/pm8941.dtsi
index ed0ba59..aca0052 100644
--- a/dts/upstream/src/arm/qcom/qcom-pm8941.dtsi
+++ b/dts/upstream/src/arm/qcom/pm8941.dtsi
@@ -99,6 +99,8 @@
usb-otg-in-supply = <&pm8941_5vs1>;
+ status = "disabled";
+
chg_otg: otg-vbus { };
};
diff --git a/dts/upstream/src/arm/qcom/qcom-pma8084.dtsi b/dts/upstream/src/arm/qcom/pma8084.dtsi
similarity index 100%
rename from dts/upstream/src/arm/qcom/qcom-pma8084.dtsi
rename to dts/upstream/src/arm/qcom/pma8084.dtsi
diff --git a/dts/upstream/src/arm/qcom/qcom-pmx55.dtsi b/dts/upstream/src/arm/qcom/pmx55.dtsi
similarity index 100%
rename from dts/upstream/src/arm/qcom/qcom-pmx55.dtsi
rename to dts/upstream/src/arm/qcom/pmx55.dtsi
diff --git a/dts/upstream/src/arm/qcom/qcom-pmx65.dtsi b/dts/upstream/src/arm/qcom/pmx65.dtsi
similarity index 100%
rename from dts/upstream/src/arm/qcom/qcom-pmx65.dtsi
rename to dts/upstream/src/arm/qcom/pmx65.dtsi
diff --git a/dts/upstream/src/arm/qcom/qcom-apq8026-asus-sparrow.dts b/dts/upstream/src/arm/qcom/qcom-apq8026-asus-sparrow.dts
index aa0e0e8..a2ca456 100644
--- a/dts/upstream/src/arm/qcom/qcom-apq8026-asus-sparrow.dts
+++ b/dts/upstream/src/arm/qcom/qcom-apq8026-asus-sparrow.dts
@@ -6,7 +6,7 @@
/dts-v1/;
#include "qcom-msm8226.dtsi"
-#include "qcom-pm8226.dtsi"
+#include "pm8226.dtsi"
/delete-node/ &adsp_region;
@@ -253,6 +253,8 @@
qcom,fast-charge-high-threshold-voltage = <4400000>;
qcom,auto-recharge-threshold-voltage = <4300000>;
qcom,minimum-input-voltage = <4400000>;
+
+ status = "okay";
};
&tlmm {
diff --git a/dts/upstream/src/arm/qcom/qcom-apq8026-huawei-sturgeon.dts b/dts/upstream/src/arm/qcom/qcom-apq8026-huawei-sturgeon.dts
index de19640..ac22896 100644
--- a/dts/upstream/src/arm/qcom/qcom-apq8026-huawei-sturgeon.dts
+++ b/dts/upstream/src/arm/qcom/qcom-apq8026-huawei-sturgeon.dts
@@ -6,7 +6,7 @@
/dts-v1/;
#include "qcom-msm8226.dtsi"
-#include "qcom-pm8226.dtsi"
+#include "pm8226.dtsi"
#include <dt-bindings/input/ti-drv260x.h>
/delete-node/ &adsp_region;
@@ -335,6 +335,8 @@
qcom,fast-charge-current-limit = <300000>;
qcom,fast-charge-safe-current = <600000>;
qcom,auto-recharge-threshold-voltage = <4240000>;
+
+ status = "okay";
};
&tlmm {
diff --git a/dts/upstream/src/arm/qcom/qcom-apq8026-lg-lenok.dts b/dts/upstream/src/arm/qcom/qcom-apq8026-lg-lenok.dts
index b887e53..0a1fd5e 100644
--- a/dts/upstream/src/arm/qcom/qcom-apq8026-lg-lenok.dts
+++ b/dts/upstream/src/arm/qcom/qcom-apq8026-lg-lenok.dts
@@ -6,7 +6,7 @@
/dts-v1/;
#include "qcom-msm8226.dtsi"
-#include "qcom-pm8226.dtsi"
+#include "pm8226.dtsi"
/delete-node/ &adsp_region;
@@ -292,6 +292,8 @@
qcom,fast-charge-high-threshold-voltage = <4350000>;
qcom,auto-recharge-threshold-voltage = <4240000>;
qcom,minimum-input-voltage = <4450000>;
+
+ status = "okay";
};
&tlmm {
diff --git a/dts/upstream/src/arm/qcom/qcom-apq8026-samsung-matisse-wifi.dts b/dts/upstream/src/arm/qcom/qcom-apq8026-samsung-matisse-wifi.dts
index f516e04..cffc069 100644
--- a/dts/upstream/src/arm/qcom/qcom-apq8026-samsung-matisse-wifi.dts
+++ b/dts/upstream/src/arm/qcom/qcom-apq8026-samsung-matisse-wifi.dts
@@ -7,7 +7,7 @@
#include <dt-bindings/input/input.h>
#include "qcom-msm8226.dtsi"
-#include "qcom-pm8226.dtsi"
+#include "pm8226.dtsi"
/delete-node/ &adsp_region;
/delete-node/ &smem_region;
diff --git a/dts/upstream/src/arm/qcom/qcom-apq8060-dragonboard.dts b/dts/upstream/src/arm/qcom/qcom-apq8060-dragonboard.dts
index 569cbf0..009afd8 100644
--- a/dts/upstream/src/arm/qcom/qcom-apq8060-dragonboard.dts
+++ b/dts/upstream/src/arm/qcom/qcom-apq8060-dragonboard.dts
@@ -5,6 +5,7 @@
#include <dt-bindings/pinctrl/qcom,pmic-gpio.h>
#include <dt-bindings/pinctrl/qcom,pmic-mpp.h>
#include "qcom-msm8660.dtsi"
+#include "pm8058.dtsi"
/ {
model = "Qualcomm APQ8060 Dragonboard";
@@ -71,7 +72,7 @@
/* Trig on both edges - getting close or far away */
interrupts-extended = <&pm8058_gpio 34 IRQ_TYPE_EDGE_BOTH>;
/* MPP05 analog input to the XOADC */
- io-channels = <&xoadc 0x00 0x05>;
+ io-channels = <&pm8058_xoadc 0x00 0x05>;
io-channel-names = "aout";
pinctrl-names = "default";
pinctrl-0 = <&dragon_cm3605_gpios>, <&dragon_cm3605_mpps>;
@@ -272,6 +273,10 @@
};
};
+&pm8058 {
+ interrupts-extended = <&tlmm 88 IRQ_TYPE_LEVEL_LOW>;
+};
+
&pm8058_gpio {
dragon_ethernet_gpios: ethernet-state {
pinconf {
@@ -447,6 +452,8 @@
* that means
*/
regulators-0 {
+ compatible = "qcom,rpm-pm8901-regulators";
+
vdd_l0-supply = <&pm8901_s4>;
vdd_l1-supply = <&vph>;
vdd_l2-supply = <&vph>;
@@ -464,57 +471,63 @@
lvs3_in-supply = <&pm8058_s2>;
mvs_in-supply = <&pm8058_s3>;
- l0 {
+ pm8901_l0: l0 {
regulator-min-microvolt = <1200000>;
regulator-max-microvolt = <1200000>;
bias-pull-down;
};
- l1 {
+
+ pm8901_l1: l1 {
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
bias-pull-down;
};
- l2 {
+
+ pm8901_l2: l2 {
/* TMA340 requires strictly 3.3V */
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
bias-pull-down;
};
- l3 {
+
+ pm8901_l3: l3 {
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
bias-pull-down;
};
- l4 {
+
+ pm8901_l4: l4 {
regulator-min-microvolt = <2600000>;
regulator-max-microvolt = <2600000>;
bias-pull-down;
};
- l5 {
+
+ pm8901_l5: l5 {
regulator-min-microvolt = <2850000>;
regulator-max-microvolt = <2850000>;
bias-pull-down;
};
- l6 {
+
+ pm8901_l6: l6 {
regulator-min-microvolt = <2200000>;
regulator-max-microvolt = <2200000>;
bias-pull-down;
};
/* s0 and s1 are SAW regulators controlled over SPM */
- s2 {
+ pm8901_s2: s2 {
regulator-min-microvolt = <1300000>;
regulator-max-microvolt = <1300000>;
qcom,switch-mode-frequency = <1600000>;
bias-pull-down;
};
- s3 {
+ pm8901_s3: s3 {
regulator-min-microvolt = <1100000>;
regulator-max-microvolt = <1100000>;
qcom,switch-mode-frequency = <1600000>;
bias-pull-down;
};
- s4 {
+ pm8901_s4: s4 {
regulator-min-microvolt = <1225000>;
regulator-max-microvolt = <1225000>;
qcom,switch-mode-frequency = <1600000>;
@@ -522,17 +535,22 @@
};
/* LVS0 thru 3 and mvs are just switches */
- lvs0 {
+ pm8901_lvs0: lvs0 {
regulator-always-on;
};
- lvs1 { };
- lvs2 { };
- lvs3 { };
- mvs { };
+
+ pm8901_lvs1: lvs1 { };
+
+ pm8901_lvs2: lvs2 { };
+
+ pm8901_lvs3: lvs3 { };
+ pm8901_mvs: mvs { };
};
regulators-1 {
+ compatible = "qcom,rpm-pm8058-regulators";
+
vdd_l0_l1_lvs-supply = <&pm8058_s3>;
vdd_l2_l11_l12-supply = <&vph>;
vdd_l3_l4_l5-supply = <&vph>;
@@ -554,144 +572,169 @@
vdd_s4-supply = <&vph>;
vdd_ncp-supply = <&vph>;
- l0 {
+ pm8058_l0: l0 {
regulator-min-microvolt = <1200000>;
regulator-max-microvolt = <1200000>;
bias-pull-down;
};
- l1 {
+
+ pm8058_l1: l1 {
regulator-min-microvolt = <1200000>;
regulator-max-microvolt = <1200000>;
bias-pull-down;
};
- l2 {
+
+ pm8058_l2: l2 {
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <2600000>;
bias-pull-down;
};
- l3 {
+
+ pm8058_l3: l3 {
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
bias-pull-down;
};
- l4 {
+
+ pm8058_l4: l4 {
regulator-min-microvolt = <2850000>;
regulator-max-microvolt = <2850000>;
bias-pull-down;
};
- l5 {
+
+ pm8058_l5: l5 {
regulator-min-microvolt = <2850000>;
regulator-max-microvolt = <2850000>;
bias-pull-down;
};
- l6 {
+
+ pm8058_l6: l6 {
regulator-min-microvolt = <3000000>;
regulator-max-microvolt = <3600000>;
bias-pull-down;
};
- l7 {
+
+ pm8058_l7: l7 {
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
bias-pull-down;
};
- l8 {
+
+ pm8058_l8: l8 {
regulator-min-microvolt = <2900000>;
regulator-max-microvolt = <3050000>;
bias-pull-down;
};
- l9 {
+
+ pm8058_l9: l9 {
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
bias-pull-down;
};
- l10 {
+
+ pm8058_l10: l10 {
regulator-min-microvolt = <2600000>;
regulator-max-microvolt = <2600000>;
bias-pull-down;
};
- l11 {
+
+ pm8058_l11: l11 {
regulator-min-microvolt = <1500000>;
regulator-max-microvolt = <1500000>;
bias-pull-down;
};
- l12 {
+
+ pm8058_l12: l12 {
regulator-min-microvolt = <2900000>;
regulator-max-microvolt = <2900000>;
bias-pull-down;
};
- l13 {
+
+ pm8058_l13: l13 {
regulator-min-microvolt = <2050000>;
regulator-max-microvolt = <2050000>;
bias-pull-down;
};
- l14 {
+
+ pm8058_l14: l14 {
regulator-min-microvolt = <2850000>;
regulator-max-microvolt = <2850000>;
};
- l15 {
+
+ pm8058_l15: l15 {
regulator-min-microvolt = <2850000>;
regulator-max-microvolt = <2850000>;
bias-pull-down;
};
- l16 {
+
+ pm8058_l16: l16 {
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
bias-pull-down;
regulator-always-on;
};
- l17 {
+
+ pm8058_l17: l17 {
// 1.5V according to schematic
regulator-min-microvolt = <2600000>;
regulator-max-microvolt = <2600000>;
bias-pull-down;
};
- l18 {
+
+ pm8058_l18: l18 {
regulator-min-microvolt = <2200000>;
regulator-max-microvolt = <2200000>;
bias-pull-down;
};
- l19 {
+
+ pm8058_l19: l19 {
regulator-min-microvolt = <2500000>;
regulator-max-microvolt = <2500000>;
bias-pull-down;
};
- l20 {
+
+ pm8058_l20: l20 {
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
bias-pull-down;
};
- l21 {
+
+ pm8058_l21: l21 {
// 1.1 V according to schematic
regulator-min-microvolt = <1200000>;
regulator-max-microvolt = <1200000>;
bias-pull-down;
regulator-always-on;
};
- l22 {
+
+ pm8058_l22: l22 {
// 1.2 V according to schematic
regulator-min-microvolt = <1150000>;
regulator-max-microvolt = <1150000>;
bias-pull-down;
};
- l23 {
+
+ pm8058_l23: l23 {
// Unused
regulator-min-microvolt = <1200000>;
regulator-max-microvolt = <1200000>;
bias-pull-down;
};
- l24 {
+
+ pm8058_l24: l24 {
// Unused
regulator-min-microvolt = <1200000>;
regulator-max-microvolt = <1200000>;
bias-pull-down;
};
- l25 {
+
+ pm8058_l25: l25 {
regulator-min-microvolt = <1200000>;
regulator-max-microvolt = <1200000>;
bias-pull-down;
};
- s0 {
+ pm8058_s0: s0 {
// regulator-min-microvolt = <500000>;
// regulator-max-microvolt = <1325000>;
regulator-min-microvolt = <1100000>;
@@ -699,7 +742,8 @@
qcom,switch-mode-frequency = <1600000>;
bias-pull-down;
};
- s1 {
+
+ pm8058_s1: s1 {
// regulator-min-microvolt = <500000>;
// regulator-max-microvolt = <1250000>;
regulator-min-microvolt = <1100000>;
@@ -707,21 +751,24 @@
qcom,switch-mode-frequency = <1600000>;
bias-pull-down;
};
- s2 {
+
+ pm8058_s2: s2 {
// 1.3 V according to schematic
regulator-min-microvolt = <1200000>;
regulator-max-microvolt = <1400000>;
qcom,switch-mode-frequency = <1600000>;
bias-pull-down;
};
- s3 {
+
+ pm8058_s3: s3 {
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
qcom,switch-mode-frequency = <1600000>;
regulator-always-on;
bias-pull-down;
};
- s4 {
+
+ pm8058_s4: s4 {
regulator-min-microvolt = <2200000>;
regulator-max-microvolt = <2200000>;
qcom,switch-mode-frequency = <1600000>;
@@ -730,14 +777,15 @@
};
/* LVS0 and LVS1 are just switches */
- lvs0 {
+ pm8058_lvs0: lvs0 {
bias-pull-down;
};
- lvs1 {
+
+ pm8058_lvs1: lvs1 {
bias-pull-down;
};
- ncp {
+ pm8058_ncp: ncp {
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
qcom,switch-mode-frequency = <1600000>;
@@ -944,28 +992,32 @@
};
};
-&xoadc {
+&pm8058_xoadc {
/* Reference voltage 2.2 V */
xoadc-ref-supply = <&pm8058_l18>;
/* Board-specific channels */
- mpp5@5 {
+ adc-channel@5 {
/* Connected to AOUT of ALS sensor */
reg = <0x00 0x05>;
};
- mpp6@6 {
+
+ adc-channel@6 {
/* Connected to test point TP43 */
reg = <0x00 0x06>;
};
- mpp7@7 {
+
+ adc-channel@7 {
/* Connected to battery thermistor */
reg = <0x00 0x07>;
};
- mpp8@8 {
+
+ adc-channel@8 {
/* Connected to battery ID detector */
reg = <0x00 0x08>;
};
- mpp9@9 {
+
+ adc-channel@9 {
/* Connected to XO thermistor */
reg = <0x00 0x09>;
};
diff --git a/dts/upstream/src/arm/qcom/qcom-apq8064-asus-nexus7-flo.dts b/dts/upstream/src/arm/qcom/qcom-apq8064-asus-nexus7-flo.dts
index c0dd639..d460743 100644
--- a/dts/upstream/src/arm/qcom/qcom-apq8064-asus-nexus7-flo.dts
+++ b/dts/upstream/src/arm/qcom/qcom-apq8064-asus-nexus7-flo.dts
@@ -1,8 +1,12 @@
// SPDX-License-Identifier: GPL-2.0
-#include "qcom-apq8064-v2.0.dtsi"
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/input/input.h>
#include <dt-bindings/pinctrl/qcom,pmic-gpio.h>
+
+#include "qcom-apq8064-v2.0.dtsi"
+#include "pm8821.dtsi"
+#include "pm8921.dtsi"
+
/ {
model = "Asus Nexus7(flo)";
compatible = "asus,nexus7-flo", "qcom,apq8064";
@@ -180,24 +184,26 @@
status = "okay";
};
-/* eMMC */
-&sdcc1 {
- vmmc-supply = <&pm8921_l5>;
- vqmmc-supply = <&pm8921_s4>;
- status = "okay";
-};
-
&mdp_dsi1_out {
remote-endpoint = <&dsi0_in>;
};
+&pm8821 {
+ interrupts-extended = <&tlmm_pinmux 76 IRQ_TYPE_LEVEL_LOW>;
+};
+
+&pm8921 {
+ interrupts-extended = <&tlmm_pinmux 74 IRQ_TYPE_LEVEL_LOW>;
+};
+
&rpm {
regulators {
+ compatible = "qcom,rpm-pm8921-regulators";
+
vdd_l1_l2_l12_l18-supply = <&pm8921_s4>;
vin_lvs1_3_6-supply = <&pm8921_s4>;
vin_lvs4_5_7-supply = <&pm8921_s4>;
-
vdd_l24-supply = <&pm8921_s1>;
vdd_l25-supply = <&pm8921_s1>;
vin_lvs2-supply = <&pm8921_s1>;
@@ -209,7 +215,7 @@
vdd_ncp-supply = <&pm8921_l6>;
/* Buck SMPS */
- s1 {
+ pm8921_s1: s1 {
regulator-always-on;
regulator-min-microvolt = <1225000>;
regulator-max-microvolt = <1225000>;
@@ -218,7 +224,7 @@
};
/* msm otg HSUSB_VDDCX */
- s3 {
+ pm8921_s3: s3 {
regulator-min-microvolt = <500000>;
regulator-max-microvolt = <1150000>;
qcom,switch-mode-frequency = <4800000>;
@@ -231,55 +237,58 @@
* tabla2x-slim-CDC_VDD_CP
* tabla2x-slim-VDDIO_CDC
*/
- s4 {
+ pm8921_s4: s4 {
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
qcom,switch-mode-frequency = <3200000>;
regulator-always-on;
};
- s7 {
+ pm8921_s7: s7 {
regulator-min-microvolt = <1300000>;
regulator-max-microvolt = <1300000>;
qcom,switch-mode-frequency = <3200000>;
};
/* mipi_dsi.1-dsi1_pll_vdda */
- l2 {
+ pm8921_l2: l2 {
regulator-min-microvolt = <1200000>;
regulator-max-microvolt = <1200000>;
regulator-always-on;
};
/* msm_otg-HSUSB_3p3 */
- l3 {
+ pm8921_l3: l3 {
regulator-min-microvolt = <3075000>;
regulator-max-microvolt = <3075000>;
bias-pull-down;
};
/* msm_otg-HSUSB_1p8 */
- l4 {
+ pm8921_l4: l4 {
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
bias-pull-down;
};
/* msm_sdcc.1-sdc_vdd */
- l5 {
+ pm8921_l5: l5 {
regulator-min-microvolt = <2950000>;
regulator-max-microvolt = <2950000>;
regulator-always-on;
bias-pull-down;
};
- l6 {
+ pm8921_l6: l6 {
regulator-min-microvolt = <2950000>;
regulator-max-microvolt = <2950000>;
};
+ pm8921_l8: l8 {
+ };
+
/* mipi_dsi.1-dsi1_avdd */
- l11 {
+ pm8921_l11: l11 {
regulator-min-microvolt = <3000000>;
regulator-max-microvolt = <3000000>;
bias-pull-down;
@@ -287,14 +296,14 @@
};
/* pwm_power for backlight */
- l17 {
+ pm8921_l17: l17 {
regulator-min-microvolt = <3000000>;
regulator-max-microvolt = <3000000>;
regulator-always-on;
};
/* camera, qdsp6 */
- l23 {
+ pm8921_l23: l23 {
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
bias-pull-down;
@@ -304,37 +313,44 @@
* tabla2x-slim-CDC_VDDA_A_1P2V
* tabla2x-slim-VDDD_CDC_D
*/
- l25 {
+ pm8921_l25: l25 {
regulator-min-microvolt = <1250000>;
regulator-max-microvolt = <1250000>;
bias-pull-down;
};
- lvs1 {
+ pm8921_lvs1: lvs1 {
bias-pull-down;
};
- lvs4 {
+ pm8921_lvs4: lvs4 {
bias-pull-down;
};
- lvs5 {
+ pm8921_lvs5: lvs5 {
bias-pull-down;
};
- lvs6 {
+ pm8921_lvs6: lvs6 {
bias-pull-down;
};
/*
* mipi_dsi.1-dsi1_vddio
* pil_riva-pll_vdd
*/
- lvs7 {
+ pm8921_lvs7: lvs7 {
bias-pull-down;
};
};
};
+/* eMMC */
+&sdcc1 {
+ vmmc-supply = <&pm8921_l5>;
+ vqmmc-supply = <&pm8921_s4>;
+ status = "okay";
+};
+
&usb_hs1_phy {
v3p3-supply = <&pm8921_l3>;
v1p8-supply = <&pm8921_l4>;
diff --git a/dts/upstream/src/arm/qcom/qcom-apq8064-cm-qs600.dts b/dts/upstream/src/arm/qcom/qcom-apq8064-cm-qs600.dts
index d6ecfd8..671d58c 100644
--- a/dts/upstream/src/arm/qcom/qcom-apq8064-cm-qs600.dts
+++ b/dts/upstream/src/arm/qcom/qcom-apq8064-cm-qs600.dts
@@ -1,8 +1,11 @@
// SPDX-License-Identifier: GPL-2.0
-#include "qcom-apq8064-v2.0.dtsi"
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/pinctrl/qcom,pmic-gpio.h>
+#include "qcom-apq8064-v2.0.dtsi"
+#include "pm8821.dtsi"
+#include "pm8921.dtsi"
+
/ {
model = "CompuLab CM-QS600";
compatible = "qcom,apq8064-cm-qs600", "qcom,apq8064";
@@ -69,6 +72,14 @@
status = "okay";
};
+&pm8821 {
+ interrupts-extended = <&tlmm_pinmux 76 IRQ_TYPE_LEVEL_LOW>;
+};
+
+&pm8921 {
+ interrupts-extended = <&tlmm_pinmux 74 IRQ_TYPE_LEVEL_LOW>;
+};
+
&pm8921_gpio {
wlan_default_gpios: wlan-gpios-state {
pinconf {
@@ -82,6 +93,8 @@
&rpm {
regulators {
+ compatible = "qcom,rpm-pm8921-regulators";
+
vin_lvs1_3_6-supply = <&pm8921_s4>;
vin_lvs2-supply = <&pm8921_s1>;
vin_lvs4_5_7-supply = <&pm8921_s4>;
@@ -93,9 +106,8 @@
vdd_l27-supply = <&pm8921_s7>;
vdd_l28-supply = <&pm8921_s7>;
-
/* Buck SMPS */
- s1 {
+ pm8921_s1: s1 {
regulator-always-on;
regulator-min-microvolt = <1225000>;
regulator-max-microvolt = <1225000>;
@@ -103,52 +115,51 @@
bias-pull-down;
};
- s3 {
+ pm8921_s3: s3 {
regulator-min-microvolt = <1000000>;
regulator-max-microvolt = <1400000>;
qcom,switch-mode-frequency = <4800000>;
};
- s4 {
+ pm8921_s4: s4 {
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
qcom,switch-mode-frequency = <3200000>;
};
- s7 {
+ pm8921_s7: s7 {
regulator-min-microvolt = <1300000>;
regulator-max-microvolt = <1300000>;
qcom,switch-mode-frequency = <3200000>;
};
- l3 {
+ pm8921_l3: l3 {
regulator-min-microvolt = <3050000>;
regulator-max-microvolt = <3300000>;
bias-pull-down;
};
- l4 {
+ pm8921_l4: l4 {
regulator-min-microvolt = <1000000>;
regulator-max-microvolt = <1800000>;
bias-pull-down;
};
- l5 {
+ pm8921_l5: l5 {
regulator-min-microvolt = <2750000>;
regulator-max-microvolt = <3000000>;
bias-pull-down;
};
- l23 {
+ pm8921_l23: l23 {
regulator-min-microvolt = <1700000>;
regulator-max-microvolt = <1900000>;
bias-pull-down;
};
- lvs6 {
+ pm8921_lvs6: lvs6 {
bias-pull-down;
};
-
};
};
diff --git a/dts/upstream/src/arm/qcom/qcom-apq8064-ifc6410.dts b/dts/upstream/src/arm/qcom/qcom-apq8064-ifc6410.dts
index b0c5e7b..ed86b24 100644
--- a/dts/upstream/src/arm/qcom/qcom-apq8064-ifc6410.dts
+++ b/dts/upstream/src/arm/qcom/qcom-apq8064-ifc6410.dts
@@ -1,9 +1,12 @@
// SPDX-License-Identifier: GPL-2.0
-#include "qcom-apq8064-v2.0.dtsi"
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/leds/common.h>
#include <dt-bindings/pinctrl/qcom,pmic-gpio.h>
+#include "qcom-apq8064-v2.0.dtsi"
+#include "pm8821.dtsi"
+#include "pm8921.dtsi"
+
/ {
model = "Qualcomm APQ8064/IFC6410";
compatible = "qcom,apq8064-ifc6410", "qcom,apq8064";
@@ -170,6 +173,14 @@
perst-gpios = <&tlmm_pinmux 27 GPIO_ACTIVE_LOW>;
};
+&pm8821 {
+ interrupts-extended = <&tlmm_pinmux 76 IRQ_TYPE_LEVEL_LOW>;
+};
+
+&pm8921 {
+ interrupts-extended = <&tlmm_pinmux 74 IRQ_TYPE_LEVEL_LOW>;
+};
+
&pm8921_gpio {
wlan_default_gpios: wlan-gpios-state {
pinconf {
@@ -192,6 +203,8 @@
&rpm {
regulators {
+ compatible = "qcom,rpm-pm8921-regulators";
+
vin_lvs1_3_6-supply = <&pm8921_s4>;
vin_lvs2-supply = <&pm8921_s1>;
vin_lvs4_5_7-supply = <&pm8921_s4>;
@@ -203,9 +216,8 @@
vdd_l27-supply = <&pm8921_s7>;
vdd_l28-supply = <&pm8921_s7>;
-
/* Buck SMPS */
- s1 {
+ pm8921_s1: s1 {
regulator-always-on;
regulator-min-microvolt = <1225000>;
regulator-max-microvolt = <1225000>;
@@ -213,59 +225,63 @@
bias-pull-down;
};
- s3 {
+ pm8921_s3: s3 {
regulator-min-microvolt = <1000000>;
regulator-max-microvolt = <1400000>;
qcom,switch-mode-frequency = <4800000>;
};
- s4 {
+ pm8921_s4: s4 {
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
qcom,switch-mode-frequency = <3200000>;
};
- s7 {
+ pm8921_s7: s7 {
regulator-min-microvolt = <1300000>;
regulator-max-microvolt = <1300000>;
qcom,switch-mode-frequency = <3200000>;
};
- l3 {
+ pm8921_l3: l3 {
regulator-min-microvolt = <3050000>;
regulator-max-microvolt = <3300000>;
bias-pull-down;
};
- l4 {
+ pm8921_l4: l4 {
regulator-min-microvolt = <1000000>;
regulator-max-microvolt = <1800000>;
bias-pull-down;
};
- l5 {
+ pm8921_l5: l5 {
regulator-min-microvolt = <2750000>;
regulator-max-microvolt = <3000000>;
bias-pull-down;
};
- l6 {
+ pm8921_l6: l6 {
regulator-min-microvolt = <2950000>;
regulator-max-microvolt = <2950000>;
bias-pull-down;
};
- l23 {
+ pm8921_l23: l23 {
regulator-min-microvolt = <1700000>;
regulator-max-microvolt = <1900000>;
bias-pull-down;
};
- lvs1 {
+ pm8921_lvs1: lvs1 {
bias-pull-down;
};
- lvs6 {
+ pm8921_lvs6: lvs6 {
+ bias-pull-down;
+ };
+
+ pm8921_hdmi_switch: hdmi-switch {
bias-pull-down;
};
};
diff --git a/dts/upstream/src/arm/qcom/qcom-apq8064-sony-xperia-lagan-yuga.dts b/dts/upstream/src/arm/qcom/qcom-apq8064-sony-xperia-lagan-yuga.dts
index 9244512..2412aa3 100644
--- a/dts/upstream/src/arm/qcom/qcom-apq8064-sony-xperia-lagan-yuga.dts
+++ b/dts/upstream/src/arm/qcom/qcom-apq8064-sony-xperia-lagan-yuga.dts
@@ -1,10 +1,13 @@
// SPDX-License-Identifier: GPL-2.0
-#include "qcom-apq8064-v2.0.dtsi"
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/input/input.h>
#include <dt-bindings/mfd/qcom-rpm.h>
#include <dt-bindings/pinctrl/qcom,pmic-gpio.h>
+#include "qcom-apq8064-v2.0.dtsi"
+#include "pm8821.dtsi"
+#include "pm8921.dtsi"
+
/ {
model = "Sony Xperia Z";
compatible = "sony,xperia-yuga", "qcom,apq8064";
@@ -65,6 +68,14 @@
status = "okay";
};
+&pm8821 {
+ interrupts-extended = <&tlmm_pinmux 76 IRQ_TYPE_LEVEL_LOW>;
+};
+
+&pm8921 {
+ interrupts-extended = <&tlmm_pinmux 74 IRQ_TYPE_LEVEL_LOW>;
+};
+
&pm8921_gpio {
gpio_keys_pin_a: gpio-keys-active-state {
pins = "gpio3", "gpio4", "gpio29", "gpio35";
@@ -82,11 +93,25 @@
&riva {
pinctrl-names = "default";
pinctrl-0 = <&riva_wlan_pin_a>, <&riva_bt_pin_a>, <&riva_fm_pin_a>;
+
+ vddcx-supply = <&pm8921_s3>;
+ vddmx-supply = <&pm8921_l24>;
+ vddpx-supply = <&pm8921_s4>;
+
status = "okay";
+
+ iris {
+ vddxo-supply = <&pm8921_l4>;
+ vddrfa-supply = <&pm8921_s2>;
+ vddpa-supply = <&pm8921_l10>;
+ vdddig-supply = <&pm8921_lvs2>;
+ };
};
&rpm {
regulators {
+ compatible = "qcom,rpm-pm8921-regulators";
+
vin_l1_l2_l12_l18-supply = <&pm8921_s4>;
vin_lvs_1_3_6-supply = <&pm8921_s4>;
vin_lvs_4_5_7-supply = <&pm8921_s4>;
@@ -98,7 +123,7 @@
vin_l28-supply = <&pm8921_s7>;
/* Buck SMPS */
- s1 {
+ pm8921_s1: s1 {
regulator-always-on;
regulator-min-microvolt = <1225000>;
regulator-max-microvolt = <1225000>;
@@ -106,21 +131,21 @@
bias-pull-down;
};
- s2 {
+ pm8921_s2: s2 {
regulator-min-microvolt = <1300000>;
regulator-max-microvolt = <1300000>;
qcom,switch-mode-frequency = <1600000>;
bias-pull-down;
};
- s3 {
+ pm8921_s3: s3 {
regulator-min-microvolt = <500000>;
regulator-max-microvolt = <1150000>;
qcom,switch-mode-frequency = <4800000>;
bias-pull-down;
};
- s4 {
+ pm8921_s4: s4 {
regulator-always-on;
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
@@ -129,205 +154,207 @@
qcom,force-mode = <QCOM_RPM_FORCE_MODE_AUTO>;
};
- s7 {
+ pm8921_s7: s7 {
regulator-min-microvolt = <1300000>;
regulator-max-microvolt = <1300000>;
qcom,switch-mode-frequency = <3200000>;
};
- s8 {
+ pm8921_s8: s8 {
regulator-min-microvolt = <2200000>;
regulator-max-microvolt = <2200000>;
qcom,switch-mode-frequency = <1600000>;
};
/* PMOS LDO */
- l1 {
+ pm8921_l1: l1 {
regulator-always-on;
regulator-min-microvolt = <1100000>;
regulator-max-microvolt = <1100000>;
bias-pull-down;
};
- l2 {
+ pm8921_l2: l2 {
regulator-min-microvolt = <1200000>;
regulator-max-microvolt = <1200000>;
bias-pull-down;
};
- l3 {
+ pm8921_l3: l3 {
regulator-min-microvolt = <3075000>;
regulator-max-microvolt = <3075000>;
bias-pull-down;
};
- l4 {
+ pm8921_l4: l4 {
regulator-always-on;
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
bias-pull-down;
};
- l5 {
+ pm8921_l5: l5 {
regulator-min-microvolt = <2950000>;
regulator-max-microvolt = <2950000>;
bias-pull-down;
};
- l6 {
+ pm8921_l6: l6 {
regulator-min-microvolt = <2950000>;
regulator-max-microvolt = <2950000>;
bias-pull-down;
};
- l7 {
+ pm8921_l7: l7 {
regulator-min-microvolt = <1850000>;
regulator-max-microvolt = <2950000>;
bias-pull-down;
};
- l8 {
+ pm8921_l8: l8 {
regulator-min-microvolt = <2800000>;
regulator-max-microvolt = <2800000>;
bias-pull-down;
};
- l9 {
+ pm8921_l9: l9 {
regulator-min-microvolt = <3000000>;
regulator-max-microvolt = <3000000>;
bias-pull-down;
};
- l10 {
+ pm8921_l10: l10 {
regulator-min-microvolt = <2900000>;
regulator-max-microvolt = <2900000>;
bias-pull-down;
};
- l11 {
+ pm8921_l11: l11 {
regulator-min-microvolt = <3000000>;
regulator-max-microvolt = <3000000>;
bias-pull-down;
};
- l12 {
+ pm8921_l12: l12 {
regulator-min-microvolt = <1200000>;
regulator-max-microvolt = <1200000>;
bias-pull-down;
};
- l14 {
+ pm8921_l14: l14 {
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
bias-pull-down;
};
- l15 {
+ pm8921_l15: l15 {
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <2950000>;
bias-pull-down;
};
- l16 {
+ pm8921_l16: l16 {
regulator-min-microvolt = <2800000>;
regulator-max-microvolt = <2800000>;
bias-pull-down;
};
- l17 {
+ pm8921_l17: l17 {
regulator-min-microvolt = <2000000>;
regulator-max-microvolt = <2000000>;
bias-pull-down;
};
- l18 {
+ pm8921_l18: l18 {
regulator-min-microvolt = <1200000>;
regulator-max-microvolt = <1200000>;
bias-pull-down;
};
- l21 {
+ pm8921_l21: l21 {
regulator-min-microvolt = <1050000>;
regulator-max-microvolt = <1050000>;
bias-pull-down;
};
- l22 {
+ pm8921_l22: l22 {
regulator-min-microvolt = <2600000>;
regulator-max-microvolt = <2600000>;
bias-pull-down;
};
- l23 {
+ pm8921_l23: l23 {
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
bias-pull-down;
};
- l24 {
+ pm8921_l24: l24 {
regulator-min-microvolt = <750000>;
regulator-max-microvolt = <1150000>;
bias-pull-down;
};
- l25 {
+ pm8921_l25: l25 {
regulator-always-on;
regulator-min-microvolt = <1250000>;
regulator-max-microvolt = <1250000>;
bias-pull-down;
};
- l27 {
+ pm8921_l27: l27 {
regulator-min-microvolt = <1100000>;
regulator-max-microvolt = <1100000>;
};
- l28 {
+ pm8921_l28: l28 {
regulator-min-microvolt = <1050000>;
regulator-max-microvolt = <1050000>;
bias-pull-down;
};
- l29 {
+ pm8921_l29: l29 {
regulator-min-microvolt = <2000000>;
regulator-max-microvolt = <2000000>;
bias-pull-down;
};
/* Low Voltage Switch */
- lvs1 {
+ pm8921_lvs1: lvs1 {
bias-pull-down;
};
- lvs2 {
+ pm8921_lvs2: lvs2 {
bias-pull-down;
};
- lvs3 {
+ pm8921_lvs3: lvs3 {
bias-pull-down;
};
- lvs4 {
+ pm8921_lvs4: lvs4 {
bias-pull-down;
};
- lvs5 {
+ pm8921_lvs5: lvs5 {
bias-pull-down;
};
- lvs6 {
+ pm8921_lvs6: lvs6 {
bias-pull-down;
};
- lvs7 {
+ pm8921_lvs7: lvs7 {
bias-pull-down;
};
- usb-switch {};
+ pm8921_usb_switch: usb-switch {};
- hdmi-switch {};
+ pm8921_hdmi_switch: hdmi-switch {
+ bias-pull-down;
+ };
- ncp {
+ pm8921_ncp: ncp {
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
qcom,switch-mode-frequency = <1600000>;
diff --git a/dts/upstream/src/arm/qcom/qcom-apq8064.dtsi b/dts/upstream/src/arm/qcom/qcom-apq8064.dtsi
index 59fd86b..3faf570 100644
--- a/dts/upstream/src/arm/qcom/qcom-apq8064.dtsi
+++ b/dts/upstream/src/arm/qcom/qcom-apq8064.dtsi
@@ -284,23 +284,6 @@
};
};
-
- /*
- * These channels from the ADC are simply hardware monitors.
- * That is why the ADC is referred to as "HKADC" - HouseKeeping
- * ADC.
- */
- iio-hwmon {
- compatible = "iio-hwmon";
- io-channels = <&xoadc 0x00 0x01>, /* Battery */
- <&xoadc 0x00 0x02>, /* DC in (charger) */
- <&xoadc 0x00 0x04>, /* VPH the main system voltage */
- <&xoadc 0x00 0x0b>, /* Die temperature */
- <&xoadc 0x00 0x0c>, /* Reference voltage 1.25V */
- <&xoadc 0x00 0x0d>, /* Reference voltage 0.625V */
- <&xoadc 0x00 0x0e>; /* Charger temperature */
- };
-
soc: soc {
#address-cells = <1>;
#size-cells = <1>;
@@ -655,133 +638,16 @@
clock-names = "core";
};
- ssbi@c00000 {
+ ssbi2: ssbi@c00000 {
compatible = "qcom,ssbi";
reg = <0x00c00000 0x1000>;
qcom,controller-type = "pmic-arbiter";
-
- pm8821: pmic {
- compatible = "qcom,pm8821";
- interrupt-parent = <&tlmm_pinmux>;
- interrupts = <76 IRQ_TYPE_LEVEL_LOW>;
- #interrupt-cells = <2>;
- interrupt-controller;
- #address-cells = <1>;
- #size-cells = <0>;
-
- pm8821_mpps: mpps@50 {
- compatible = "qcom,pm8821-mpp", "qcom,ssbi-mpp";
- reg = <0x50>;
- interrupt-controller;
- #interrupt-cells = <2>;
- gpio-controller;
- #gpio-cells = <2>;
- gpio-ranges = <&pm8821_mpps 0 0 4>;
- };
- };
};
- ssbi@500000 {
+ ssbi: ssbi@500000 {
compatible = "qcom,ssbi";
reg = <0x00500000 0x1000>;
qcom,controller-type = "pmic-arbiter";
-
- pmicintc: pmic {
- compatible = "qcom,pm8921";
- interrupt-parent = <&tlmm_pinmux>;
- interrupts = <74 8>;
- #interrupt-cells = <2>;
- interrupt-controller;
- #address-cells = <1>;
- #size-cells = <0>;
-
- pm8921_gpio: gpio@150 {
-
- compatible = "qcom,pm8921-gpio",
- "qcom,ssbi-gpio";
- reg = <0x150>;
- interrupt-controller;
- #interrupt-cells = <2>;
- gpio-controller;
- gpio-ranges = <&pm8921_gpio 0 0 44>;
- #gpio-cells = <2>;
-
- };
-
- pm8921_mpps: mpps@50 {
- compatible = "qcom,pm8921-mpp",
- "qcom,ssbi-mpp";
- reg = <0x50>;
- gpio-controller;
- #gpio-cells = <2>;
- gpio-ranges = <&pm8921_mpps 0 0 12>;
- interrupt-controller;
- #interrupt-cells = <2>;
- };
-
- rtc@11d {
- compatible = "qcom,pm8921-rtc";
- interrupt-parent = <&pmicintc>;
- interrupts = <39 1>;
- reg = <0x11d>;
- allow-set-time;
- };
-
- pwrkey@1c {
- compatible = "qcom,pm8921-pwrkey";
- reg = <0x1c>;
- interrupt-parent = <&pmicintc>;
- interrupts = <50 1>, <51 1>;
- debounce = <15625>;
- pull-up;
- };
-
- xoadc: xoadc@197 {
- compatible = "qcom,pm8921-adc";
- reg = <197>;
- interrupts-extended = <&pmicintc 78 IRQ_TYPE_EDGE_RISING>;
- #address-cells = <2>;
- #size-cells = <0>;
- #io-channel-cells = <2>;
-
- vcoin: adc-channel@0 {
- reg = <0x00 0x00>;
- };
- vbat: adc-channel@1 {
- reg = <0x00 0x01>;
- };
- dcin: adc-channel@2 {
- reg = <0x00 0x02>;
- };
- vph_pwr: adc-channel@4 {
- reg = <0x00 0x04>;
- };
- batt_therm: adc-channel@8 {
- reg = <0x00 0x08>;
- };
- batt_id: adc-channel@9 {
- reg = <0x00 0x09>;
- };
- usb_vbus: adc-channel@a {
- reg = <0x00 0x0a>;
- };
- die_temp: adc-channel@b {
- reg = <0x00 0x0b>;
- };
- ref_625mv: adc-channel@c {
- reg = <0x00 0x0c>;
- };
- ref_1250mv: adc-channel@d {
- reg = <0x00 0x0d>;
- };
- chg_temp: adc-channel@e {
- reg = <0x00 0x0e>;
- };
- ref_muxoff: adc-channel@f {
- reg = <0x00 0x0f>;
- };
- };
- };
};
qfprom: qfprom@700000 {
@@ -891,60 +757,6 @@
clocks = <&pxo_board>, <&cxo_board>;
clock-names = "pxo", "cxo";
};
-
- regulators {
- compatible = "qcom,rpm-pm8921-regulators";
-
- pm8921_s1: s1 {};
- pm8921_s2: s2 {};
- pm8921_s3: s3 {};
- pm8921_s4: s4 {};
- pm8921_s7: s7 {};
- pm8921_s8: s8 {};
-
- pm8921_l1: l1 {};
- pm8921_l2: l2 {};
- pm8921_l3: l3 {};
- pm8921_l4: l4 {};
- pm8921_l5: l5 {};
- pm8921_l6: l6 {};
- pm8921_l7: l7 {};
- pm8921_l8: l8 {};
- pm8921_l9: l9 {};
- pm8921_l10: l10 {};
- pm8921_l11: l11 {};
- pm8921_l12: l12 {};
- pm8921_l14: l14 {};
- pm8921_l15: l15 {};
- pm8921_l16: l16 {};
- pm8921_l17: l17 {};
- pm8921_l18: l18 {};
- pm8921_l21: l21 {};
- pm8921_l22: l22 {};
- pm8921_l23: l23 {};
- pm8921_l24: l24 {};
- pm8921_l25: l25 {};
- pm8921_l26: l26 {};
- pm8921_l27: l27 {};
- pm8921_l28: l28 {};
- pm8921_l29: l29 {};
-
- pm8921_lvs1: lvs1 {};
- pm8921_lvs2: lvs2 {};
- pm8921_lvs3: lvs3 {};
- pm8921_lvs4: lvs4 {};
- pm8921_lvs5: lvs5 {};
- pm8921_lvs6: lvs6 {};
- pm8921_lvs7: lvs7 {};
-
- pm8921_usb_switch: usb-switch {};
-
- pm8921_hdmi_switch: hdmi-switch {
- bias-pull-down;
- };
-
- pm8921_ncp: ncp {};
- };
};
usb1: usb@12500000 {
@@ -1472,7 +1284,7 @@
qcom,ncb = <3>;
};
- pcie: pci@1b500000 {
+ pcie: pcie@1b500000 {
compatible = "qcom,pcie-apq8064";
reg = <0x1b500000 0x1000>,
<0x1b502000 0x80>,
@@ -1623,10 +1435,6 @@
memory-region = <&wcnss_mem>;
- vddcx-supply = <&pm8921_s3>;
- vddmx-supply = <&pm8921_l24>;
- vddpx-supply = <&pm8921_s4>;
-
status = "disabled";
iris {
@@ -1634,11 +1442,6 @@
clocks = <&cxo_board>;
clock-names = "xo";
-
- vddxo-supply = <&pm8921_l4>;
- vddrfa-supply = <&pm8921_s2>;
- vddpa-supply = <&pm8921_l10>;
- vdddig-supply = <&pm8921_lvs2>;
};
smd-edge {
diff --git a/dts/upstream/src/arm/qcom/qcom-apq8074-dragonboard.dts b/dts/upstream/src/arm/qcom/qcom-apq8074-dragonboard.dts
index 6d1b243..6fce011 100644
--- a/dts/upstream/src/arm/qcom/qcom-apq8074-dragonboard.dts
+++ b/dts/upstream/src/arm/qcom/qcom-apq8074-dragonboard.dts
@@ -4,8 +4,8 @@
#include <dt-bindings/leds/common.h>
#include <dt-bindings/pinctrl/qcom,pmic-gpio.h>
#include "qcom-msm8974.dtsi"
-#include "qcom-pm8841.dtsi"
-#include "qcom-pm8941.dtsi"
+#include "pm8841.dtsi"
+#include "pm8941.dtsi"
/delete-node/ &mpss_region;
@@ -49,6 +49,33 @@
no-map;
};
};
+
+ vreg_boost: vreg-boost {
+ compatible = "regulator-fixed";
+
+ regulator-name = "vreg-boost";
+ regulator-min-microvolt = <3150000>;
+ regulator-max-microvolt = <3150000>;
+
+ regulator-always-on;
+ regulator-boot-on;
+
+ gpio = <&pm8941_gpios 21 GPIO_ACTIVE_HIGH>;
+ enable-active-high;
+
+ pinctrl-names = "default";
+ pinctrl-0 = <&boost_bypass_n_pin>;
+ };
+
+ vreg_vph_pwr: vreg-vph-pwr {
+ compatible = "regulator-fixed";
+ regulator-name = "vph-pwr";
+
+ regulator-min-microvolt = <3600000>;
+ regulator-max-microvolt = <3600000>;
+
+ regulator-always-on;
+ };
};
&blsp1_uart2 {
@@ -403,6 +430,10 @@
pinctrl-1 = <&sdc2_off>;
};
+&smbb {
+ status = "okay";
+};
+
&tlmm {
sdc1_on: sdc1-on-state {
clk-pins {
diff --git a/dts/upstream/src/arm/qcom/qcom-apq8084-ifc6540.dts b/dts/upstream/src/arm/qcom/qcom-apq8084-ifc6540.dts
index 116e59a..1df24c9 100644
--- a/dts/upstream/src/arm/qcom/qcom-apq8084-ifc6540.dts
+++ b/dts/upstream/src/arm/qcom/qcom-apq8084-ifc6540.dts
@@ -1,6 +1,6 @@
// SPDX-License-Identifier: GPL-2.0
#include "qcom-apq8084.dtsi"
-#include "qcom-pma8084.dtsi"
+#include "pma8084.dtsi"
/ {
model = "Qualcomm APQ8084/IFC6540";
diff --git a/dts/upstream/src/arm/qcom/qcom-apq8084-mtp.dts b/dts/upstream/src/arm/qcom/qcom-apq8084-mtp.dts
index c6b6680..d4e6aee 100644
--- a/dts/upstream/src/arm/qcom/qcom-apq8084-mtp.dts
+++ b/dts/upstream/src/arm/qcom/qcom-apq8084-mtp.dts
@@ -1,6 +1,6 @@
// SPDX-License-Identifier: GPL-2.0
#include "qcom-apq8084.dtsi"
-#include "qcom-pma8084.dtsi"
+#include "pma8084.dtsi"
/ {
model = "Qualcomm APQ 8084-MTP";
diff --git a/dts/upstream/src/arm/qcom/qcom-ipq4019-ap.dk04.1.dtsi b/dts/upstream/src/arm/qcom/qcom-ipq4019-ap.dk04.1.dtsi
index 468ebc4..374af6d 100644
--- a/dts/upstream/src/arm/qcom/qcom-ipq4019-ap.dk04.1.dtsi
+++ b/dts/upstream/src/arm/qcom/qcom-ipq4019-ap.dk04.1.dtsi
@@ -98,7 +98,7 @@
};
};
- pci@40000000 {
+ pcie@40000000 {
status = "okay";
perst-gpios = <&tlmm 38 GPIO_ACTIVE_LOW>;
};
diff --git a/dts/upstream/src/arm/qcom/qcom-ipq4019.dtsi b/dts/upstream/src/arm/qcom/qcom-ipq4019.dtsi
index 9844e0b..f989bd7 100644
--- a/dts/upstream/src/arm/qcom/qcom-ipq4019.dtsi
+++ b/dts/upstream/src/arm/qcom/qcom-ipq4019.dtsi
@@ -224,7 +224,7 @@
};
sdhci: mmc@7824900 {
- compatible = "qcom,sdhci-msm-v4";
+ compatible = "qcom,ipq4019-sdhci", "qcom,sdhci-msm-v4";
reg = <0x7824900 0x11c>, <0x7824000 0x800>;
reg-names = "hc", "core";
interrupts = <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>;
@@ -417,7 +417,7 @@
reg = <0x4ab000 0x4>;
};
- pcie0: pci@40000000 {
+ pcie0: pcie@40000000 {
compatible = "qcom,pcie-ipq4019";
reg = <0x40000000 0xf1d>,
<0x40000f20 0xa8>,
diff --git a/dts/upstream/src/arm/qcom/qcom-ipq8064.dtsi b/dts/upstream/src/arm/qcom/qcom-ipq8064.dtsi
index 6198f42..6a7f4dd 100644
--- a/dts/upstream/src/arm/qcom/qcom-ipq8064.dtsi
+++ b/dts/upstream/src/arm/qcom/qcom-ipq8064.dtsi
@@ -366,7 +366,7 @@
};
};
- qcom,ssbi@500000 {
+ ssbi@500000 {
compatible = "qcom,ssbi";
reg = <0x00500000 0x1000>;
qcom,controller-type = "pmic-arbiter";
@@ -1076,7 +1076,7 @@
status = "disabled";
};
- pcie0: pci@1b500000 {
+ pcie0: pcie@1b500000 {
compatible = "qcom,pcie-ipq8064";
reg = <0x1b500000 0x1000
0x1b502000 0x80
@@ -1127,7 +1127,7 @@
perst-gpios = <&qcom_pinmux 3 GPIO_ACTIVE_LOW>;
};
- pcie1: pci@1b700000 {
+ pcie1: pcie@1b700000 {
compatible = "qcom,pcie-ipq8064";
reg = <0x1b700000 0x1000
0x1b702000 0x80
@@ -1178,7 +1178,7 @@
perst-gpios = <&qcom_pinmux 48 GPIO_ACTIVE_LOW>;
};
- pcie2: pci@1b900000 {
+ pcie2: pcie@1b900000 {
compatible = "qcom,pcie-ipq8064";
reg = <0x1b900000 0x1000
0x1b902000 0x80
diff --git a/dts/upstream/src/arm/qcom/qcom-mdm9615-wp8548-mangoh-green.dts b/dts/upstream/src/arm/qcom/qcom-mdm9615-wp8548-mangoh-green.dts
index b269fdc..e3b4b93 100644
--- a/dts/upstream/src/arm/qcom/qcom-mdm9615-wp8548-mangoh-green.dts
+++ b/dts/upstream/src/arm/qcom/qcom-mdm9615-wp8548-mangoh-green.dts
@@ -6,11 +6,11 @@
* Author : Neil Armstrong <narmstrong@baylibre.com>
*/
+#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/input/input.h>
+#include <dt-bindings/interrupt-controller/irq.h>
#include "qcom-mdm9615-wp8548.dtsi"
-#include <dt-bindings/interrupt-controller/irq.h>
-#include <dt-bindings/gpio/gpio.h>
/ {
model = "MangOH Green with WP8548 Module";
diff --git a/dts/upstream/src/arm/qcom/qcom-mdm9615-wp8548.dtsi b/dts/upstream/src/arm/qcom/qcom-mdm9615-wp8548.dtsi
index 92c8003..0dd52ca 100644
--- a/dts/upstream/src/arm/qcom/qcom-mdm9615-wp8548.dtsi
+++ b/dts/upstream/src/arm/qcom/qcom-mdm9615-wp8548.dtsi
@@ -7,6 +7,7 @@
*/
#include "qcom-mdm9615.dtsi"
+#include "pm8018.dtsi"
/ {
model = "Sierra Wireless WP8548 Module";
@@ -76,7 +77,11 @@
};
};
-&pmicgpio {
+&pm8018 {
+ interrupts-extended = <&intc GIC_PPI 226 IRQ_TYPE_LEVEL_HIGH>;
+};
+
+&pm8018_gpio {
usb_vbus_5v_pins: usb-vbus-5v-state {
pins = "gpio4";
function = "normal";
@@ -129,6 +134,142 @@
pinctrl-names = "default";
};
+&rpm {
+ regulators {
+ compatible = "qcom,rpm-pm8018-regulators";
+
+ vin_lvs1-supply = <&pm8018_s3>;
+
+ vdd_l7-supply = <&pm8018_s4>;
+ vdd_l8-supply = <&pm8018_s3>;
+ vdd_l9_l10_l11_l12-supply = <&pm8018_s5>;
+
+ /* Buck SMPS */
+ pm8018_s1: s1 {
+ regulator-min-microvolt = <500000>;
+ regulator-max-microvolt = <1150000>;
+ qcom,switch-mode-frequency = <1600000>;
+ bias-pull-down;
+ };
+
+ pm8018_s2: s2 {
+ regulator-min-microvolt = <1225000>;
+ regulator-max-microvolt = <1300000>;
+ qcom,switch-mode-frequency = <1600000>;
+ bias-pull-down;
+ };
+
+ pm8018_s3: s3 {
+ regulator-always-on;
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ qcom,switch-mode-frequency = <1600000>;
+ bias-pull-down;
+ };
+
+ pm8018_s4: s4 {
+ regulator-min-microvolt = <2100000>;
+ regulator-max-microvolt = <2200000>;
+ qcom,switch-mode-frequency = <1600000>;
+ bias-pull-down;
+ };
+
+ pm8018_s5: s5 {
+ regulator-always-on;
+ regulator-min-microvolt = <1350000>;
+ regulator-max-microvolt = <1350000>;
+ qcom,switch-mode-frequency = <1600000>;
+ bias-pull-down;
+ };
+
+ /* PMOS LDO */
+ pm8018_l2: l2 {
+ regulator-always-on;
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ bias-pull-down;
+ };
+
+ pm8018_l3: l3 {
+ regulator-always-on;
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ bias-pull-down;
+ };
+
+ pm8018_l4: l4 {
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ bias-pull-down;
+ };
+
+ pm8018_l5: l5 {
+ regulator-min-microvolt = <2850000>;
+ regulator-max-microvolt = <2850000>;
+ bias-pull-down;
+ };
+
+ pm8018_l6: l6 {
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <2850000>;
+ bias-pull-down;
+ };
+
+ pm8018_l7: l7 {
+ regulator-min-microvolt = <1850000>;
+ regulator-max-microvolt = <1900000>;
+ bias-pull-down;
+ };
+
+ pm8018_l8: l8 {
+ regulator-min-microvolt = <1200000>;
+ regulator-max-microvolt = <1200000>;
+ bias-pull-down;
+ };
+
+ pm8018_l9: l9 {
+ regulator-min-microvolt = <750000>;
+ regulator-max-microvolt = <1150000>;
+ bias-pull-down;
+ };
+
+ pm8018_l10: l10 {
+ regulator-min-microvolt = <1050000>;
+ regulator-max-microvolt = <1050000>;
+ bias-pull-down;
+ };
+
+ pm8018_l11: l11 {
+ regulator-min-microvolt = <1050000>;
+ regulator-max-microvolt = <1050000>;
+ bias-pull-down;
+ };
+
+ pm8018_l12: l12 {
+ regulator-min-microvolt = <1050000>;
+ regulator-max-microvolt = <1050000>;
+ bias-pull-down;
+ };
+
+ pm8018_l13: l13 {
+ regulator-min-microvolt = <1850000>;
+ regulator-max-microvolt = <2950000>;
+ bias-pull-down;
+ };
+
+ pm8018_l14: l14 {
+ regulator-min-microvolt = <2850000>;
+ regulator-max-microvolt = <2850000>;
+ bias-pull-down;
+ };
+
+ /* Low Voltage Switch */
+ pm8018_lvs1: lvs1 {
+ bias-pull-down;
+ };
+ };
+};
+
&sdcc1 {
status = "okay";
};
diff --git a/dts/upstream/src/arm/qcom/qcom-mdm9615.dtsi b/dts/upstream/src/arm/qcom/qcom-mdm9615.dtsi
index 63e21aa2..34c6099 100644
--- a/dts/upstream/src/arm/qcom/qcom-mdm9615.dtsi
+++ b/dts/upstream/src/arm/qcom/qcom-mdm9615.dtsi
@@ -256,57 +256,10 @@
};
};
- qcom,ssbi@500000 {
+ ssbi: ssbi@500000 {
compatible = "qcom,ssbi";
reg = <0x500000 0x1000>;
qcom,controller-type = "pmic-arbiter";
-
- pmicintc: pmic {
- compatible = "qcom,pm8018", "qcom,pm8921";
- interrupts = <GIC_PPI 226 IRQ_TYPE_LEVEL_HIGH>;
- #interrupt-cells = <2>;
- interrupt-controller;
- #address-cells = <1>;
- #size-cells = <0>;
-
- pwrkey@1c {
- compatible = "qcom,pm8018-pwrkey", "qcom,pm8921-pwrkey";
- reg = <0x1c>;
- interrupt-parent = <&pmicintc>;
- interrupts = <50 IRQ_TYPE_EDGE_RISING>,
- <51 IRQ_TYPE_EDGE_RISING>;
- debounce = <15625>;
- pull-up;
- };
-
- pmicmpp: mpps@50 {
- compatible = "qcom,pm8018-mpp", "qcom,ssbi-mpp";
- interrupt-controller;
- #interrupt-cells = <2>;
- reg = <0x50>;
- gpio-controller;
- #gpio-cells = <2>;
- gpio-ranges = <&pmicmpp 0 0 6>;
- };
-
- rtc@11d {
- compatible = "qcom,pm8018-rtc", "qcom,pm8921-rtc";
- interrupt-parent = <&pmicintc>;
- interrupts = <39 IRQ_TYPE_EDGE_RISING>;
- reg = <0x11d>;
- allow-set-time;
- };
-
- pmicgpio: gpio@150 {
- compatible = "qcom,pm8018-gpio", "qcom,ssbi-gpio";
- reg = <0x150>;
- interrupt-controller;
- #interrupt-cells = <2>;
- gpio-controller;
- gpio-ranges = <&pmicgpio 0 0 6>;
- #gpio-cells = <2>;
- };
- };
};
sdcc1bam: dma-controller@12182000 {
@@ -383,140 +336,6 @@
<GIC_SPI 21 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 22 IRQ_TYPE_EDGE_RISING>;
interrupt-names = "ack", "err", "wakeup";
-
- regulators {
- compatible = "qcom,rpm-pm8018-regulators";
-
- vin_lvs1-supply = <&pm8018_s3>;
-
- vdd_l7-supply = <&pm8018_s4>;
- vdd_l8-supply = <&pm8018_s3>;
- vdd_l9_l10_l11_l12-supply = <&pm8018_s5>;
-
- /* Buck SMPS */
- pm8018_s1: s1 {
- regulator-min-microvolt = <500000>;
- regulator-max-microvolt = <1150000>;
- qcom,switch-mode-frequency = <1600000>;
- bias-pull-down;
- };
-
- pm8018_s2: s2 {
- regulator-min-microvolt = <1225000>;
- regulator-max-microvolt = <1300000>;
- qcom,switch-mode-frequency = <1600000>;
- bias-pull-down;
- };
-
- pm8018_s3: s3 {
- regulator-always-on;
- regulator-min-microvolt = <1800000>;
- regulator-max-microvolt = <1800000>;
- qcom,switch-mode-frequency = <1600000>;
- bias-pull-down;
- };
-
- pm8018_s4: s4 {
- regulator-min-microvolt = <2100000>;
- regulator-max-microvolt = <2200000>;
- qcom,switch-mode-frequency = <1600000>;
- bias-pull-down;
- };
-
- pm8018_s5: s5 {
- regulator-always-on;
- regulator-min-microvolt = <1350000>;
- regulator-max-microvolt = <1350000>;
- qcom,switch-mode-frequency = <1600000>;
- bias-pull-down;
- };
-
- /* PMOS LDO */
- pm8018_l2: l2 {
- regulator-always-on;
- regulator-min-microvolt = <1800000>;
- regulator-max-microvolt = <1800000>;
- bias-pull-down;
- };
-
- pm8018_l3: l3 {
- regulator-always-on;
- regulator-min-microvolt = <1800000>;
- regulator-max-microvolt = <1800000>;
- bias-pull-down;
- };
-
- pm8018_l4: l4 {
- regulator-min-microvolt = <3300000>;
- regulator-max-microvolt = <3300000>;
- bias-pull-down;
- };
-
- pm8018_l5: l5 {
- regulator-min-microvolt = <2850000>;
- regulator-max-microvolt = <2850000>;
- bias-pull-down;
- };
-
- pm8018_l6: l6 {
- regulator-min-microvolt = <1800000>;
- regulator-max-microvolt = <2850000>;
- bias-pull-down;
- };
-
- pm8018_l7: l7 {
- regulator-min-microvolt = <1850000>;
- regulator-max-microvolt = <1900000>;
- bias-pull-down;
- };
-
- pm8018_l8: l8 {
- regulator-min-microvolt = <1200000>;
- regulator-max-microvolt = <1200000>;
- bias-pull-down;
- };
-
- pm8018_l9: l9 {
- regulator-min-microvolt = <750000>;
- regulator-max-microvolt = <1150000>;
- bias-pull-down;
- };
-
- pm8018_l10: l10 {
- regulator-min-microvolt = <1050000>;
- regulator-max-microvolt = <1050000>;
- bias-pull-down;
- };
-
- pm8018_l11: l11 {
- regulator-min-microvolt = <1050000>;
- regulator-max-microvolt = <1050000>;
- bias-pull-down;
- };
-
- pm8018_l12: l12 {
- regulator-min-microvolt = <1050000>;
- regulator-max-microvolt = <1050000>;
- bias-pull-down;
- };
-
- pm8018_l13: l13 {
- regulator-min-microvolt = <1850000>;
- regulator-max-microvolt = <2950000>;
- bias-pull-down;
- };
-
- pm8018_l14: l14 {
- regulator-min-microvolt = <2850000>;
- regulator-max-microvolt = <2850000>;
- bias-pull-down;
- };
-
- /* Low Voltage Switch */
- pm8018_lvs1: lvs1 {
- bias-pull-down;
- };
- };
};
};
};
diff --git a/dts/upstream/src/arm/qcom/qcom-msm8226-microsoft-common.dtsi b/dts/upstream/src/arm/qcom/qcom-msm8226-microsoft-common.dtsi
new file mode 100644
index 0000000..525d8c6
--- /dev/null
+++ b/dts/upstream/src/arm/qcom/qcom-msm8226-microsoft-common.dtsi
@@ -0,0 +1,327 @@
+// SPDX-License-Identifier: BSD-3-Clause
+/*
+ * Common Board Device Tree for Microsoft MSM8x26-based Lumias
+ *
+ * Copyright (c) 2023, Jack Matthews <jm5112356@gmail.com>
+ * Copyright (c) 2023, Ivaylo Ivanov <ivo.ivanov.ivanov1@gmail.com>
+ * Copyright (c) 2023, Dominik Kobinski <dominikkobinski314@gmail.com>
+ * Copyright (c) 2023, Rayyan Ansari <rayyan@ansari.sh>
+ */
+
+#include "qcom-msm8226.dtsi"
+#include "pm8226.dtsi"
+#include <dt-bindings/input/input.h>
+
+/*
+ * Delete all generic (msm8226.dtsi) reserved
+ * memory mappings which are different on these devices.
+ */
+/delete-node/ &smem_region;
+
+/ {
+ aliases {
+ mmc0 = &sdhc_1; /* eMMC */
+ mmc1 = &sdhc_2; /* microSD */
+ display0 = &framebuffer;
+ };
+
+ chosen {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges;
+
+ stdout-path = "display0";
+
+ framebuffer: framebuffer@3200000 {
+ compatible = "simple-framebuffer";
+ reg = <0x3200000 0x800000>;
+ format = "a8r8g8b8";
+ width = <720>;
+ height = <1280>;
+ stride = <(720 * 4)>;
+
+ clocks = <&mmcc MDSS_AHB_CLK>,
+ <&mmcc MDSS_AXI_CLK>,
+ <&mmcc MDSS_BYTE0_CLK>,
+ <&mmcc MDSS_MDP_CLK>,
+ <&mmcc MDSS_PCLK0_CLK>,
+ <&mmcc MDSS_VSYNC_CLK>;
+ power-domains = <&mmcc MDSS_GDSC>;
+ };
+ };
+
+ gpio_keys: gpio-keys {
+ compatible = "gpio-keys";
+
+ pinctrl-0 = <&gpio_keys_default>;
+ pinctrl-names = "default";
+
+ label = "GPIO Buttons";
+
+ key-volume-up {
+ label = "Volume Up";
+ gpios = <&tlmm 106 GPIO_ACTIVE_LOW>;
+ linux,code = <KEY_VOLUMEUP>;
+ };
+ };
+
+ /*
+ * This device being a WP platform has a different
+ * memory layout than other Android based devices.
+ * This smem memory region is directly copied from
+ * the original UEFI firmware.
+ */
+ reserved-memory {
+ display_reserved: framebuffer@3200000 {
+ reg = <0x03200000 0x800000>;
+ no-map;
+ };
+
+ smem_region: smem@fa00000 {
+ reg = <0x0fa00000 0x100000>;
+ no-map;
+ };
+ };
+};
+
+&blsp1_i2c5 {
+ status = "okay";
+
+ touchscreen: touchscreen@4b {
+ compatible = "syna,rmi4-i2c";
+ reg = <0x4b>;
+
+ interrupts-extended = <&tlmm 17 IRQ_TYPE_EDGE_FALLING>;
+ vdd-supply = <&pm8226_l15>;
+ vio-supply = <&pm8226_l6>;
+
+ pinctrl-0 = <&touchscreen_default>;
+ pinctrl-names = "default";
+
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ rmi4-f01@1 {
+ reg = <0x01>;
+ syna,nosleep-mode = <1>;
+ };
+
+ rmi4-f11@11 {
+ reg = <0x11>;
+ syna,sensor-type = <1>;
+ };
+ };
+};
+
+&blsp1_uart3 {
+ status = "okay";
+};
+
+&pm8226_resin {
+ linux,code = <KEY_VOLUMEDOWN>;
+ status = "okay";
+};
+
+&pm8226_vib {
+ status = "okay";
+};
+
+&rpm_requests {
+ regulators {
+ compatible = "qcom,rpm-pm8226-regulators";
+
+ /* These values were taken from the original firmware DSDT */
+ pm8226_s1: s1 {
+ regulator-min-microvolt = <1050000>;
+ regulator-max-microvolt = <1050000>;
+ };
+
+ pm8226_s3: s3 {
+ regulator-min-microvolt = <1300000>;
+ regulator-max-microvolt = <1300000>;
+ };
+
+ pm8226_s4: s4 {
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <2100000>;
+ };
+
+ pm8226_s5: s5 {
+ regulator-min-microvolt = <1150000>;
+ regulator-max-microvolt = <1150000>;
+ };
+
+ pm8226_l3: l3 {
+ regulator-min-microvolt = <750000>;
+ regulator-max-microvolt = <1150000>;
+ };
+
+ pm8226_l4: l4 {
+ regulator-min-microvolt = <1200000>;
+ regulator-max-microvolt = <1200000>;
+ };
+
+ pm8226_l5: l5 {
+ regulator-min-microvolt = <1200000>;
+ regulator-max-microvolt = <1200000>;
+ };
+
+ pm8226_l6: l6 {
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ };
+
+ pm8226_l7: l7 {
+ regulator-min-microvolt = <1850000>;
+ regulator-max-microvolt = <1850000>;
+ };
+
+ pm8226_l8: l8 {
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-always-on;
+ };
+
+ pm8226_l9: l9 {
+ regulator-min-microvolt = <2050000>;
+ regulator-max-microvolt = <2050000>;
+ };
+
+ pm8226_l10: l10 {
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ };
+
+ pm8226_l12: l12 {
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ };
+
+ pm8226_l14: l14 {
+ regulator-min-microvolt = <2750000>;
+ regulator-max-microvolt = <2750000>;
+ };
+
+ pm8226_l15: l15 {
+ regulator-min-microvolt = <2850000>;
+ regulator-max-microvolt = <2850000>;
+ };
+
+ pm8226_l16: l16 {
+ regulator-min-microvolt = <3000000>;
+ regulator-max-microvolt = <3000000>;
+ };
+
+ pm8226_l17: l17 {
+ regulator-min-microvolt = <2950000>;
+ regulator-max-microvolt = <2950000>;
+ regulator-system-load = <200000>;
+ regulator-allow-set-load;
+ };
+
+ pm8226_l18: l18 {
+ regulator-min-microvolt = <2950000>;
+ regulator-max-microvolt = <2950000>;
+ regulator-system-load = <200000>;
+ regulator-allow-set-load;
+ };
+
+ pm8226_l19: l19 {
+ regulator-min-microvolt = <2850000>;
+ regulator-max-microvolt = <2850000>;
+ };
+
+ pm8226_l20: l20 {
+ regulator-min-microvolt = <3075000>;
+ regulator-max-microvolt = <3075000>;
+ };
+
+ pm8226_l21: l21 {
+ regulator-min-microvolt = <1850000>;
+ regulator-max-microvolt = <2950000>;
+ };
+
+ pm8226_l22: l22 {
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ };
+
+ pm8226_l23: l23 {
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ };
+
+ pm8226_l24: l24 {
+ regulator-min-microvolt = <1300000>;
+ regulator-max-microvolt = <1300000>;
+ };
+
+ pm8226_l25: l25 {
+ regulator-min-microvolt = <1775000>;
+ regulator-max-microvolt = <2075000>;
+ };
+
+ pm8226_l27: l27 {
+ regulator-min-microvolt = <2050000>;
+ regulator-max-microvolt = <2050000>;
+ };
+
+ pm8226_l28: l28 {
+ regulator-min-microvolt = <2000000>;
+ regulator-max-microvolt = <3000000>;
+ };
+ };
+};
+
+&sdhc_1 {
+ vmmc-supply = <&pm8226_l17>;
+ vqmmc-supply = <&pm8226_l6>;
+
+ status = "okay";
+};
+
+&sdhc_2 {
+ vmmc-supply = <&pm8226_l18>;
+ vqmmc-supply = <&pm8226_l21>;
+
+ status = "okay";
+};
+
+&usb {
+ extcon = <&smbb>;
+ dr_mode = "peripheral";
+
+ status = "okay";
+};
+
+&usb_hs_phy {
+ extcon = <&smbb>;
+ v1p8-supply = <&pm8226_l10>;
+ v3p3-supply = <&pm8226_l20>;
+};
+
+&tlmm {
+ gpio_keys_default: gpio-keys-default-state {
+ pins = "gpio106", "gpio107", "gpio108";
+ function = "gpio";
+ drive-strength = <2>;
+ bias-pull-up;
+ };
+
+ touchscreen_default: touchscreen-default-state {
+ irq-pins {
+ pins = "gpio17";
+ function = "gpio";
+ drive-strength = <8>;
+ bias-pull-up;
+ };
+
+ reset-pins {
+ pins = "gpio16";
+ function = "gpio";
+ drive-strength = <8>;
+ bias-disable;
+ output-high;
+ };
+ };
+};
diff --git a/dts/upstream/src/arm/qcom/qcom-msm8226-microsoft-dempsey.dts b/dts/upstream/src/arm/qcom/qcom-msm8226-microsoft-dempsey.dts
new file mode 100644
index 0000000..2c664b5
--- /dev/null
+++ b/dts/upstream/src/arm/qcom/qcom-msm8226-microsoft-dempsey.dts
@@ -0,0 +1,17 @@
+// SPDX-License-Identifier: BSD-3-Clause
+/*
+ * Copyright (c) 2023, Jack Matthews <jm5112356@gmail.com>
+ * Copyright (c) 2023, Ivaylo Ivanov <ivo.ivanov.ivanov1@gmail.com>
+ * Copyright (c) 2023, Dominik Kobinski <dominikkobinski314@gmail.com>
+ * Copyright (c) 2023, Rayyan Ansari <rayyan@ansari.sh>
+ */
+
+/dts-v1/;
+
+#include "qcom-msm8226-microsoft-common.dtsi"
+
+/ {
+ model = "Microsoft Lumia 640";
+ compatible = "microsoft,dempsey", "qcom,msm8226";
+ chassis-type = "handset";
+};
diff --git a/dts/upstream/src/arm/qcom/qcom-msm8226-microsoft-makepeace.dts b/dts/upstream/src/arm/qcom/qcom-msm8226-microsoft-makepeace.dts
new file mode 100644
index 0000000..731c5c3
--- /dev/null
+++ b/dts/upstream/src/arm/qcom/qcom-msm8226-microsoft-makepeace.dts
@@ -0,0 +1,17 @@
+// SPDX-License-Identifier: BSD-3-Clause
+/*
+ * Copyright (c) 2023, Jack Matthews <jm5112356@gmail.com>
+ * Copyright (c) 2023, Ivaylo Ivanov <ivo.ivanov.ivanov1@gmail.com>
+ * Copyright (c) 2023, Dominik Kobinski <dominikkobinski314@gmail.com>
+ * Copyright (c) 2023, Rayyan Ansari <rayyan@ansari.sh>
+ */
+
+/dts-v1/;
+
+#include "qcom-msm8226-microsoft-common.dtsi"
+
+/ {
+ model = "Microsoft Lumia 640 XL";
+ compatible = "microsoft,makepeace", "qcom,msm8226";
+ chassis-type = "handset";
+};
diff --git a/dts/upstream/src/arm/qcom/qcom-msm8226-microsoft-moneypenny.dts b/dts/upstream/src/arm/qcom/qcom-msm8226-microsoft-moneypenny.dts
new file mode 100644
index 0000000..992b711
--- /dev/null
+++ b/dts/upstream/src/arm/qcom/qcom-msm8226-microsoft-moneypenny.dts
@@ -0,0 +1,23 @@
+// SPDX-License-Identifier: BSD-3-Clause
+/*
+ * Copyright (c) 2023, Jack Matthews <jm5112356@gmail.com>
+ * Copyright (c) 2023, Ivaylo Ivanov <ivo.ivanov.ivanov1@gmail.com>
+ * Copyright (c) 2023, Dominik Kobinski <dominikkobinski314@gmail.com>
+ * Copyright (c) 2023, Rayyan Ansari <rayyan@ansari.sh>
+ */
+
+/dts-v1/;
+
+#include "qcom-msm8226-microsoft-common.dtsi"
+
+/ {
+ model = "Nokia Lumia 630";
+ compatible = "microsoft,moneypenny", "qcom,msm8226";
+ chassis-type = "handset";
+};
+
+&framebuffer {
+ width = <480>;
+ height = <854>;
+ stride = <(480 * 4)>;
+};
diff --git a/dts/upstream/src/arm/qcom/qcom-msm8226.dtsi b/dts/upstream/src/arm/qcom/qcom-msm8226.dtsi
index 97a377b..b492c95 100644
--- a/dts/upstream/src/arm/qcom/qcom-msm8226.dtsi
+++ b/dts/upstream/src/arm/qcom/qcom-msm8226.dtsi
@@ -442,8 +442,8 @@
<&gcc GPLL0_VOTE>,
<&gcc GPLL1_VOTE>,
<&rpmcc RPM_SMD_GFX3D_CLK_SRC>,
- <0>,
- <0>;
+ <&mdss_dsi0_phy 1>,
+ <&mdss_dsi0_phy 0>;
clock-names = "xo",
"mmss_gpll0_vote",
"gpll0_vote",
@@ -875,8 +875,8 @@
offset = <0x65c>;
mode-bootloader = <0x77665500>;
- mode-normal = <0x77665501>;
- mode-recovery = <0x77665502>;
+ mode-normal = <0x77665501>;
+ mode-recovery = <0x77665502>;
};
};
@@ -1006,6 +1006,46 @@
"ref";
};
};
+
+ gpu: adreno@fdb00000 {
+ compatible = "qcom,adreno-305.18", "qcom,adreno";
+ reg = <0xfdb00000 0x10000>;
+ reg-names = "kgsl_3d0_reg_memory";
+
+ interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "kgsl_3d0_irq";
+
+ clocks = <&mmcc OXILI_GFX3D_CLK>,
+ <&mmcc OXILICX_AHB_CLK>,
+ <&mmcc OXILICX_AXI_CLK>;
+ clock-names = "core", "iface", "mem_iface";
+
+ sram = <&gmu_sram>;
+ power-domains = <&mmcc OXILICX_GDSC>;
+ operating-points-v2 = <&gpu_opp_table>;
+
+ status = "disabled";
+
+ gpu_opp_table: opp-table {
+ compatible = "operating-points-v2";
+
+ opp-450000000 {
+ opp-hz = /bits/ 64 <450000000>;
+ };
+
+ opp-320000000 {
+ opp-hz = /bits/ 64 <320000000>;
+ };
+
+ opp-200000000 {
+ opp-hz = /bits/ 64 <200000000>;
+ };
+
+ opp-19000000 {
+ opp-hz = /bits/ 64 <19000000>;
+ };
+ };
+ };
};
thermal-zones {
diff --git a/dts/upstream/src/arm/qcom/qcom-msm8660-surf.dts b/dts/upstream/src/arm/qcom/qcom-msm8660-surf.dts
index be18f1b..69fe651 100644
--- a/dts/upstream/src/arm/qcom/qcom-msm8660-surf.dts
+++ b/dts/upstream/src/arm/qcom/qcom-msm8660-surf.dts
@@ -2,6 +2,7 @@
#include <dt-bindings/input/input.h>
#include "qcom-msm8660.dtsi"
+#include "pm8058.dtsi"
/ {
model = "Qualcomm MSM8660 SURF";
@@ -35,30 +36,42 @@
};
&pm8058 {
- keypad@148 {
- linux,keymap = <
- MATRIX_KEY(0, 0, KEY_FN_F1)
- MATRIX_KEY(0, 1, KEY_UP)
- MATRIX_KEY(0, 2, KEY_LEFT)
- MATRIX_KEY(0, 3, KEY_VOLUMEUP)
- MATRIX_KEY(1, 0, KEY_FN_F2)
- MATRIX_KEY(1, 1, KEY_RIGHT)
- MATRIX_KEY(1, 2, KEY_DOWN)
- MATRIX_KEY(1, 3, KEY_VOLUMEDOWN)
- MATRIX_KEY(2, 3, KEY_ENTER)
- MATRIX_KEY(4, 0, KEY_CAMERA_FOCUS)
- MATRIX_KEY(4, 1, KEY_UP)
- MATRIX_KEY(4, 2, KEY_LEFT)
- MATRIX_KEY(4, 3, KEY_HOME)
- MATRIX_KEY(4, 4, KEY_FN_F3)
- MATRIX_KEY(5, 0, KEY_CAMERA)
- MATRIX_KEY(5, 1, KEY_RIGHT)
- MATRIX_KEY(5, 2, KEY_DOWN)
- MATRIX_KEY(5, 3, KEY_BACK)
- MATRIX_KEY(5, 4, KEY_MENU)
- >;
- keypad,num-rows = <6>;
- keypad,num-columns = <5>;
+ interrupts-extended = <&tlmm 88 IRQ_TYPE_LEVEL_LOW>;
+};
+
+&pm8058_keypad {
+ linux,keymap = <
+ MATRIX_KEY(0, 0, KEY_FN_F1)
+ MATRIX_KEY(0, 1, KEY_UP)
+ MATRIX_KEY(0, 2, KEY_LEFT)
+ MATRIX_KEY(0, 3, KEY_VOLUMEUP)
+ MATRIX_KEY(1, 0, KEY_FN_F2)
+ MATRIX_KEY(1, 1, KEY_RIGHT)
+ MATRIX_KEY(1, 2, KEY_DOWN)
+ MATRIX_KEY(1, 3, KEY_VOLUMEDOWN)
+ MATRIX_KEY(2, 3, KEY_ENTER)
+ MATRIX_KEY(4, 0, KEY_CAMERA_FOCUS)
+ MATRIX_KEY(4, 1, KEY_UP)
+ MATRIX_KEY(4, 2, KEY_LEFT)
+ MATRIX_KEY(4, 3, KEY_HOME)
+ MATRIX_KEY(4, 4, KEY_FN_F3)
+ MATRIX_KEY(5, 0, KEY_CAMERA)
+ MATRIX_KEY(5, 1, KEY_RIGHT)
+ MATRIX_KEY(5, 2, KEY_DOWN)
+ MATRIX_KEY(5, 3, KEY_BACK)
+ MATRIX_KEY(5, 4, KEY_MENU)
+ >;
+ keypad,num-rows = <6>;
+ keypad,num-columns = <5>;
+};
+
+&rpm {
+ regulators-0 {
+ compatible = "qcom,rpm-pm8901-regulators";
+ };
+
+ regulators-1 {
+ compatible = "qcom,rpm-pm8058-regulators";
};
};
diff --git a/dts/upstream/src/arm/qcom/qcom-msm8660.dtsi b/dts/upstream/src/arm/qcom/qcom-msm8660.dtsi
index 78023ed..a7c245b 100644
--- a/dts/upstream/src/arm/qcom/qcom-msm8660.dtsi
+++ b/dts/upstream/src/arm/qcom/qcom-msm8660.dtsi
@@ -73,22 +73,6 @@
};
};
- /*
- * These channels from the ADC are simply hardware monitors.
- * That is why the ADC is referred to as "HKADC" - HouseKeeping
- * ADC.
- */
- iio-hwmon {
- compatible = "iio-hwmon";
- io-channels = <&xoadc 0x00 0x01>, /* Battery */
- <&xoadc 0x00 0x02>, /* DC in (charger) */
- <&xoadc 0x00 0x04>, /* VPH the main system voltage */
- <&xoadc 0x00 0x0b>, /* Die temperature */
- <&xoadc 0x00 0x0c>, /* Reference voltage 1.25V */
- <&xoadc 0x00 0x0d>, /* Reference voltage 0.625V */
- <&xoadc 0x00 0x0e>; /* Reference voltage 0.325V */
- };
-
soc: soc {
#address-cells = <1>;
#size-cells = <1>;
@@ -334,143 +318,10 @@
status = "disabled";
};
- ssbi@500000 {
+ ssbi: ssbi@500000 {
compatible = "qcom,ssbi";
reg = <0x500000 0x1000>;
qcom,controller-type = "pmic-arbiter";
-
- pm8058: pmic {
- compatible = "qcom,pm8058";
- interrupt-parent = <&tlmm>;
- interrupts = <88 8>;
- #interrupt-cells = <2>;
- interrupt-controller;
- #address-cells = <1>;
- #size-cells = <0>;
-
- pm8058_gpio: gpio@150 {
- compatible = "qcom,pm8058-gpio",
- "qcom,ssbi-gpio";
- reg = <0x150>;
- interrupt-controller;
- #interrupt-cells = <2>;
- gpio-controller;
- gpio-ranges = <&pm8058_gpio 0 0 44>;
- #gpio-cells = <2>;
-
- };
-
- pm8058_mpps: mpps@50 {
- compatible = "qcom,pm8058-mpp",
- "qcom,ssbi-mpp";
- reg = <0x50>;
- gpio-controller;
- #gpio-cells = <2>;
- gpio-ranges = <&pm8058_mpps 0 0 12>;
- interrupt-controller;
- #interrupt-cells = <2>;
- };
-
- pwrkey@1c {
- compatible = "qcom,pm8058-pwrkey";
- reg = <0x1c>;
- interrupt-parent = <&pm8058>;
- interrupts = <50 1>, <51 1>;
- debounce = <15625>;
- pull-up;
- };
-
- pm8058_keypad: keypad@148 {
- compatible = "qcom,pm8058-keypad";
- reg = <0x148>;
- interrupt-parent = <&pm8058>;
- interrupts = <74 1>, <75 1>;
- debounce = <15>;
- scan-delay = <32>;
- row-hold = <91500>;
- };
-
- xoadc: xoadc@197 {
- compatible = "qcom,pm8058-adc";
- reg = <0x197>;
- interrupts-extended = <&pm8058 76 IRQ_TYPE_EDGE_RISING>;
- #address-cells = <2>;
- #size-cells = <0>;
- #io-channel-cells = <2>;
-
- vcoin: adc-channel@0 {
- reg = <0x00 0x00>;
- };
- vbat: adc-channel@1 {
- reg = <0x00 0x01>;
- };
- dcin: adc-channel@2 {
- reg = <0x00 0x02>;
- };
- ichg: adc-channel@3 {
- reg = <0x00 0x03>;
- };
- vph_pwr: adc-channel@4 {
- reg = <0x00 0x04>;
- };
- usb_vbus: adc-channel@a {
- reg = <0x00 0x0a>;
- };
- die_temp: adc-channel@b {
- reg = <0x00 0x0b>;
- };
- ref_625mv: adc-channel@c {
- reg = <0x00 0x0c>;
- };
- ref_1250mv: adc-channel@d {
- reg = <0x00 0x0d>;
- };
- ref_325mv: adc-channel@e {
- reg = <0x00 0x0e>;
- };
- ref_muxoff: adc-channel@f {
- reg = <0x00 0x0f>;
- };
- };
-
- rtc@1e8 {
- compatible = "qcom,pm8058-rtc";
- reg = <0x1e8>;
- interrupt-parent = <&pm8058>;
- interrupts = <39 1>;
- allow-set-time;
- };
-
- vibrator@4a {
- compatible = "qcom,pm8058-vib";
- reg = <0x4a>;
- };
-
- pm8058_led48: led@48 {
- compatible = "qcom,pm8058-keypad-led";
- reg = <0x48>;
- status = "disabled";
- };
-
- pm8058_led131: led@131 {
- compatible = "qcom,pm8058-led";
- reg = <0x131>;
- status = "disabled";
- };
-
- pm8058_led132: led@132 {
- compatible = "qcom,pm8058-led";
- reg = <0x132>;
- status = "disabled";
- };
-
- pm8058_led133: led@133 {
- compatible = "qcom,pm8058-led";
- reg = <0x133>;
- status = "disabled";
- };
-
- };
};
l2cc: clock-controller@2082000 {
@@ -496,72 +347,6 @@
clocks = <&pxo_board>;
clock-names = "pxo";
};
-
- regulators-0 {
- compatible = "qcom,rpm-pm8901-regulators";
-
- pm8901_l0: l0 {};
- pm8901_l1: l1 {};
- pm8901_l2: l2 {};
- pm8901_l3: l3 {};
- pm8901_l4: l4 {};
- pm8901_l5: l5 {};
- pm8901_l6: l6 {};
-
- /* S0 and S1 Handled as SAW regulators by SPM */
- pm8901_s2: s2 {};
- pm8901_s3: s3 {};
- pm8901_s4: s4 {};
-
- pm8901_lvs0: lvs0 {};
- pm8901_lvs1: lvs1 {};
- pm8901_lvs2: lvs2 {};
- pm8901_lvs3: lvs3 {};
-
- pm8901_mvs: mvs {};
- };
-
- regulators-1 {
- compatible = "qcom,rpm-pm8058-regulators";
-
- pm8058_l0: l0 {};
- pm8058_l1: l1 {};
- pm8058_l2: l2 {};
- pm8058_l3: l3 {};
- pm8058_l4: l4 {};
- pm8058_l5: l5 {};
- pm8058_l6: l6 {};
- pm8058_l7: l7 {};
- pm8058_l8: l8 {};
- pm8058_l9: l9 {};
- pm8058_l10: l10 {};
- pm8058_l11: l11 {};
- pm8058_l12: l12 {};
- pm8058_l13: l13 {};
- pm8058_l14: l14 {};
- pm8058_l15: l15 {};
- pm8058_l16: l16 {};
- pm8058_l17: l17 {};
- pm8058_l18: l18 {};
- pm8058_l19: l19 {};
- pm8058_l20: l20 {};
- pm8058_l21: l21 {};
- pm8058_l22: l22 {};
- pm8058_l23: l23 {};
- pm8058_l24: l24 {};
- pm8058_l25: l25 {};
-
- pm8058_s0: s0 {};
- pm8058_s1: s1 {};
- pm8058_s2: s2 {};
- pm8058_s3: s3 {};
- pm8058_s4: s4 {};
-
- pm8058_lvs0: lvs0 {};
- pm8058_lvs1: lvs1 {};
-
- pm8058_ncp: ncp {};
- };
};
amba {
diff --git a/dts/upstream/src/arm/qcom/qcom-msm8926-htc-memul.dts b/dts/upstream/src/arm/qcom/qcom-msm8926-htc-memul.dts
new file mode 100644
index 0000000..ed328b2
--- /dev/null
+++ b/dts/upstream/src/arm/qcom/qcom-msm8926-htc-memul.dts
@@ -0,0 +1,372 @@
+// SPDX-License-Identifier: BSD-3-Clause
+/*
+ * Copyright (c) 2023, Luca Weiss <luca@z3ntu.xyz>
+ */
+
+/dts-v1/;
+
+#include "qcom-msm8226.dtsi"
+#include "pm8226.dtsi"
+
+/delete-node/ &adsp_region;
+/delete-node/ &smem_region;
+
+/ {
+ model = "HTC One Mini 2";
+ compatible = "htc,memul", "qcom,msm8926", "qcom,msm8226";
+ chassis-type = "handset";
+
+ aliases {
+ mmc1 = &sdhc_2; /* SDC2 SD card slot */
+ };
+
+ gpio-keys {
+ compatible = "gpio-keys";
+
+ key-power {
+ label = "Power";
+ gpios = <&tlmm 106 GPIO_ACTIVE_LOW>;
+ linux,code = <KEY_POWER>;
+ debounce-interval = <15>;
+ };
+
+ key-volume-down {
+ label = "Volume Down";
+ gpios = <&tlmm 107 GPIO_ACTIVE_LOW>;
+ linux,code = <KEY_VOLUMEDOWN>;
+ debounce-interval = <15>;
+ };
+
+ key-volume-up {
+ label = "Volume Up";
+ gpios = <&tlmm 108 GPIO_ACTIVE_LOW>;
+ linux,code = <KEY_VOLUMEUP>;
+ debounce-interval = <15>;
+ };
+ };
+
+ reserved-memory {
+ unknown@5b00000 {
+ reg = <0x05b00000 0x200000>;
+ no-map;
+ };
+
+ unknown@7500000 {
+ reg = <0x07500000 0xb00000>;
+ no-map;
+ };
+
+ mpss_region: mpss@8000000 {
+ reg = <0x08000000 0x4f00000>;
+ no-map;
+ };
+
+ unknown@cf00000 {
+ reg = <0x0cf00000 0x200000>;
+ no-map;
+ };
+
+ mba_region: mba@d100000 {
+ reg = <0x0d100000 0x3a000>;
+ no-map;
+ };
+
+ unknown@d13a000 {
+ reg = <0x0d13a000 0xc6000>;
+ no-map;
+ };
+
+ wcnss_region: wcnss@d200000 {
+ reg = <0x0d200000 0x650000>;
+ no-map;
+ };
+
+ unknown@d850000 {
+ reg = <0x0d850000 0x3b0000>;
+ no-map;
+ };
+
+ adsp_region: adsp@dc00000 {
+ reg = <0x0dc00000 0x1400000>;
+ no-map;
+ };
+
+ unknown@f000000 {
+ reg = <0x0f000000 0x500000>;
+ no-map;
+ };
+
+ venus_region: venus@f500000 {
+ reg = <0x0f500000 0x500000>;
+ no-map;
+ };
+
+ smem_region: smem@fa00000 {
+ reg = <0x0fa00000 0x100000>;
+ no-map;
+ };
+
+ unknown@fb00000 {
+ reg = <0x0fb00000 0x1b00000>;
+ no-map;
+ };
+ };
+};
+
+&adsp {
+ firmware-name = "qcom/msm8926/memul/adsp.mbn";
+ status = "okay";
+};
+
+&blsp1_i2c2 {
+ status = "okay";
+
+ magnetometer@d {
+ compatible = "asahi-kasei,ak8963";
+ reg = <0x0d>;
+ interrupts-extended = <&tlmm 66 IRQ_TYPE_EDGE_RISING>;
+ vdd-supply = <&pm8226_l19>;
+ vid-supply = <&pm8226_l28>;
+ };
+
+ accelerometer@18 {
+ compatible = "bosch,bma250e";
+ reg = <0x18>;
+ interrupts-extended = <&tlmm 63 IRQ_TYPE_EDGE_RISING>;
+ vdd-supply = <&pm8226_l19>;
+ vddio-supply = <&pm8226_l28>;
+ };
+};
+
+&blsp1_i2c4 {
+ status = "okay";
+
+ /* TFA9887 @ 34 */
+ /* TFA9887 @ 35 */
+};
+
+&blsp1_i2c5 {
+ status = "okay";
+
+ touchscreen@20 {
+ compatible = "syna,rmi4-i2c";
+ reg = <0x20>;
+
+ interrupts-extended = <&tlmm 17 IRQ_TYPE_EDGE_FALLING>;
+ vdd-supply = <&pm8226_l19>;
+
+ syna,startup-delay-ms = <160>;
+
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ rmi4-f01@1 {
+ reg = <0x1>;
+ syna,nosleep-mode = <1>;
+ };
+
+ rmi4-f12@12 {
+ reg = <0x12>;
+ syna,sensor-type = <1>;
+ };
+ };
+};
+
+&blsp1_i2c6 {
+ status = "okay";
+
+ /* NCP6924 Camera Regulators @ 10 */
+ /* PN544 NFC @ 28 */
+ /* TPS61310 Flash/Torch @ 33 */
+};
+
+&pm8226_vib {
+ status = "okay";
+};
+
+&rpm_requests {
+ regulators {
+ compatible = "qcom,rpm-pm8226-regulators";
+
+ pm8226_s3: s3 {
+ regulator-min-microvolt = <1200000>;
+ regulator-max-microvolt = <1350000>;
+ };
+
+ pm8226_s4: s4 {
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <2200000>;
+ };
+
+ pm8226_s5: s5 {
+ regulator-min-microvolt = <1150000>;
+ regulator-max-microvolt = <1150000>;
+ };
+
+ pm8226_l1: l1 {
+ regulator-min-microvolt = <1225000>;
+ regulator-max-microvolt = <1225000>;
+ };
+
+ pm8226_l2: l2 {
+ regulator-min-microvolt = <1200000>;
+ regulator-max-microvolt = <1200000>;
+ };
+
+ pm8226_l3: l3 {
+ regulator-min-microvolt = <750000>;
+ regulator-max-microvolt = <1337500>;
+ };
+
+ pm8226_l4: l4 {
+ regulator-min-microvolt = <1200000>;
+ regulator-max-microvolt = <1200000>;
+ };
+
+ pm8226_l5: l5 {
+ regulator-min-microvolt = <1200000>;
+ regulator-max-microvolt = <1200000>;
+ };
+
+ pm8226_l6: l6 {
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ };
+
+ pm8226_l7: l7 {
+ regulator-min-microvolt = <1850000>;
+ regulator-max-microvolt = <1850000>;
+ };
+
+ pm8226_l8: l8 {
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ };
+
+ pm8226_l9: l9 {
+ regulator-min-microvolt = <2050000>;
+ regulator-max-microvolt = <2050000>;
+ };
+
+ pm8226_l10: l10 {
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ };
+
+ pm8226_l12: l12 {
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ };
+
+ pm8226_l14: l14 {
+ regulator-min-microvolt = <2750000>;
+ regulator-max-microvolt = <2750000>;
+ };
+
+ pm8226_l15: l15 {
+ regulator-min-microvolt = <3000000>;
+ regulator-max-microvolt = <3000000>;
+ };
+
+ pm8226_l16: l16 {
+ regulator-min-microvolt = <3000000>;
+ regulator-max-microvolt = <3350000>;
+ };
+
+ pm8226_l17: l17 {
+ regulator-min-microvolt = <2950000>;
+ regulator-max-microvolt = <2950000>;
+ };
+
+ pm8226_l18: l18 {
+ regulator-min-microvolt = <2950000>;
+ regulator-max-microvolt = <2950000>;
+ };
+
+ pm8226_l19: l19 {
+ regulator-min-microvolt = <2850000>;
+ regulator-max-microvolt = <2850000>;
+ };
+
+ pm8226_l20: l20 {
+ regulator-min-microvolt = <3075000>;
+ regulator-max-microvolt = <3075000>;
+ };
+
+ pm8226_l21: l21 {
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <2950000>;
+ regulator-allow-set-load;
+ };
+
+ pm8226_l22: l22 {
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <2950000>;
+ };
+
+ pm8226_l23: l23 {
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <3000000>;
+ };
+
+ pm8226_l24: l24 {
+ regulator-min-microvolt = <1300000>;
+ regulator-max-microvolt = <1350000>;
+ };
+
+ pm8226_l25: l25 {
+ regulator-min-microvolt = <1775000>;
+ regulator-max-microvolt = <2125000>;
+ };
+
+ pm8226_l26: l26 {
+ regulator-min-microvolt = <1225000>;
+ regulator-max-microvolt = <1225000>;
+ };
+
+ pm8226_l27: l27 {
+ regulator-min-microvolt = <2050000>;
+ regulator-max-microvolt = <2050000>;
+ };
+
+ pm8226_l28: l28 {
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ };
+
+ pm8226_lvs1: lvs1 {};
+ };
+};
+
+&sdhc_2 {
+ vmmc-supply = <&pm8226_l18>;
+ vqmmc-supply = <&pm8226_l21>;
+
+ bus-width = <4>;
+ cd-gpios = <&tlmm 38 GPIO_ACTIVE_LOW>;
+
+ status = "okay";
+};
+
+&smbb {
+ qcom,fast-charge-safe-current = <1750000>;
+ qcom,fast-charge-current-limit = <1750000>;
+ qcom,fast-charge-safe-voltage = <4360000>;
+ qcom,fast-charge-high-threshold-voltage = <4350000>;
+ qcom,auto-recharge-threshold-voltage = <4300000>;
+ qcom,minimum-input-voltage = <4300000>;
+
+ status = "okay";
+};
+
+&usb {
+ extcon = <&smbb>;
+ dr_mode = "peripheral";
+ status = "okay";
+};
+
+&usb_hs_phy {
+ extcon = <&smbb>;
+ v1p8-supply = <&pm8226_l10>;
+ v3p3-supply = <&pm8226_l20>;
+};
diff --git a/dts/upstream/src/arm/qcom/qcom-msm8926-microsoft-superman-lte.dts b/dts/upstream/src/arm/qcom/qcom-msm8926-microsoft-superman-lte.dts
new file mode 100644
index 0000000..9b48661
--- /dev/null
+++ b/dts/upstream/src/arm/qcom/qcom-msm8926-microsoft-superman-lte.dts
@@ -0,0 +1,53 @@
+// SPDX-License-Identifier: BSD-3-Clause
+/*
+ * Copyright (c) 2023, Jack Matthews <jm5112356@gmail.com>
+ * Copyright (c) 2023, Ivaylo Ivanov <ivo.ivanov.ivanov1@gmail.com>
+ * Copyright (c) 2023, Dominik Kobinski <dominikkobinski314@gmail.com>
+ * Copyright (c) 2023, Rayyan Ansari <rayyan@ansari.sh>
+ */
+
+/dts-v1/;
+
+#include "qcom-msm8226-microsoft-common.dtsi"
+
+/* This device has touchscreen on i2c3 instead */
+/delete-node/ &touchscreen;
+
+/ {
+ model = "Nokia Lumia 735";
+ compatible = "microsoft,superman-lte", "qcom,msm8926", "qcom,msm8226";
+ chassis-type = "handset";
+};
+
+&blsp1_i2c3 {
+ status = "okay";
+
+ touchscreen: touchscreen@4b {
+ compatible = "syna,rmi4-i2c";
+ reg = <0x4b>;
+
+ interrupts-extended = <&tlmm 17 IRQ_TYPE_EDGE_FALLING>;
+ vdd-supply = <&pm8226_l15>;
+ vio-supply = <&pm8226_l6>;
+
+ pinctrl-0 = <&touchscreen_default>;
+ pinctrl-names = "default";
+
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ rmi4-f01@1 {
+ reg = <0x01>;
+ syna,nosleep-mode = <1>;
+ };
+
+ rmi4-f11@11 {
+ reg = <0x11>;
+ syna,sensor-type = <1>;
+ };
+ };
+};
+
+&blsp1_i2c5 {
+ status = "disabled";
+};
diff --git a/dts/upstream/src/arm/qcom/qcom-msm8926-microsoft-tesla.dts b/dts/upstream/src/arm/qcom/qcom-msm8926-microsoft-tesla.dts
new file mode 100644
index 0000000..53a6d4e
--- /dev/null
+++ b/dts/upstream/src/arm/qcom/qcom-msm8926-microsoft-tesla.dts
@@ -0,0 +1,67 @@
+// SPDX-License-Identifier: BSD-3-Clause
+/*
+ * Copyright (c) 2023, Jack Matthews <jm5112356@gmail.com>
+ * Copyright (c) 2023, Ivaylo Ivanov <ivo.ivanov.ivanov1@gmail.com>
+ * Copyright (c) 2023, Dominik Kobinski <dominikkobinski314@gmail.com>
+ * Copyright (c) 2023, Rayyan Ansari <rayyan@ansari.sh>
+ */
+
+/dts-v1/;
+
+#include "qcom-msm8226-microsoft-common.dtsi"
+
+/* This device has touchscreen on i2c1 instead */
+/delete-node/ &touchscreen;
+
+/ {
+ model = "Nokia Lumia 830";
+ compatible = "microsoft,tesla", "qcom,msm8926", "qcom,msm8226";
+ chassis-type = "handset";
+};
+
+&blsp1_i2c1 {
+ status = "okay";
+
+ touchscreen: touchscreen@4b {
+ compatible = "syna,rmi4-i2c";
+ reg = <0x4b>;
+
+ interrupts-extended = <&tlmm 17 IRQ_TYPE_EDGE_FALLING>;
+ vdd-supply = <&pm8226_l15>;
+ vio-supply = <&pm8226_l6>;
+
+ pinctrl-0 = <&touchscreen_default>;
+ pinctrl-names = "default";
+
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ rmi4-f01@1 {
+ reg = <0x01>;
+ syna,nosleep-mode = <1>;
+ };
+
+ rmi4-f12@12 {
+ reg = <0x12>;
+ syna,sensor-type = <1>;
+ };
+ };
+};
+
+&blsp1_i2c5 {
+ status = "disabled";
+};
+
+&gpio_keys {
+ key-camera-snapshot {
+ label = "Camera Snapshot";
+ gpios = <&tlmm 107 GPIO_ACTIVE_LOW>;
+ linux,code = <KEY_CAMERA>;
+ };
+
+ key-camera-focus {
+ label = "Camera Focus";
+ gpios = <&tlmm 108 GPIO_ACTIVE_LOW>;
+ linux,code = <KEY_CAMERA_FOCUS>;
+ };
+};
diff --git a/dts/upstream/src/arm/qcom/qcom-msm8926-motorola-peregrine.dts b/dts/upstream/src/arm/qcom/qcom-msm8926-motorola-peregrine.dts
new file mode 100644
index 0000000..0cbe2d2
--- /dev/null
+++ b/dts/upstream/src/arm/qcom/qcom-msm8926-motorola-peregrine.dts
@@ -0,0 +1,291 @@
+// SPDX-License-Identifier: BSD-3-Clause
+
+/dts-v1/;
+
+#include "qcom-msm8226.dtsi"
+#include "pm8226.dtsi"
+
+/delete-node/ &smem_region;
+
+/ {
+ model = "Motorola Moto G 4G (2013)";
+ compatible = "motorola,peregrine", "qcom,msm8926", "qcom,msm8226";
+ chassis-type = "handset";
+
+ aliases {
+ mmc0 = &sdhc_1; /* SDC1 eMMC slot */
+ mmc1 = &sdhc_2; /* SDC2 SD card slot */
+ };
+
+ chosen {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges;
+
+ framebuffer0: framebuffer@3200000 {
+ compatible = "simple-framebuffer";
+ reg = <0x03200000 0x800000>;
+ width = <720>;
+ height = <1280>;
+ stride = <(720 * 3)>;
+ format = "r8g8b8";
+ };
+ };
+
+ gpio-keys {
+ compatible = "gpio-keys";
+
+ event-hall-sensor {
+ label = "Hall Effect Sensor";
+ gpios = <&tlmm 51 GPIO_ACTIVE_LOW>;
+ linux,input-type = <EV_SW>;
+ linux,code = <SW_LID>;
+ linux,can-disable;
+ };
+
+ key-volume-up {
+ label = "Volume Up";
+ gpios = <&tlmm 106 GPIO_ACTIVE_LOW>;
+ linux,code = <KEY_VOLUMEUP>;
+ debounce-interval = <15>;
+ };
+ };
+
+ reserved-memory {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges;
+
+ framebuffer@3200000 {
+ reg = <0x03200000 0x800000>;
+ no-map;
+ };
+
+ smem_region: smem@fa00000 {
+ reg = <0x0fa00000 0x100000>;
+ no-map;
+ };
+ };
+};
+
+&blsp1_i2c3 {
+ status = "okay";
+
+ sensor@48 {
+ compatible = "ti,tmp108";
+ reg = <0x48>;
+ };
+};
+
+&blsp1_uart3 {
+ status = "okay";
+};
+
+&pm8226_resin {
+ linux,code = <KEY_VOLUMEDOWN>;
+ status = "okay";
+};
+
+&pm8226_vib {
+ status = "okay";
+};
+
+&rpm_requests {
+ regulators {
+ compatible = "qcom,rpm-pm8226-regulators";
+
+ pm8226_s3: s3 {
+ regulator-min-microvolt = <1200000>;
+ regulator-max-microvolt = <1300000>;
+ };
+
+ pm8226_s4: s4 {
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <2200000>;
+ };
+
+ pm8226_s5: s5 {
+ regulator-min-microvolt = <1150000>;
+ regulator-max-microvolt = <1150000>;
+ };
+
+ pm8226_l1: l1 {
+ regulator-min-microvolt = <1225000>;
+ regulator-max-microvolt = <1225000>;
+ };
+
+ pm8226_l2: l2 {
+ regulator-min-microvolt = <1200000>;
+ regulator-max-microvolt = <1200000>;
+ };
+
+ pm8226_l3: l3 {
+ regulator-min-microvolt = <750000>;
+ regulator-max-microvolt = <1337500>;
+ };
+
+ pm8226_l4: l4 {
+ regulator-min-microvolt = <1200000>;
+ regulator-max-microvolt = <1200000>;
+ };
+
+ pm8226_l5: l5 {
+ regulator-min-microvolt = <1200000>;
+ regulator-max-microvolt = <1200000>;
+ };
+
+ pm8226_l6: l6 {
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-allow-set-load;
+ };
+
+ pm8226_l7: l7 {
+ regulator-min-microvolt = <1850000>;
+ regulator-max-microvolt = <1850000>;
+ };
+
+ pm8226_l8: l8 {
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ };
+
+ pm8226_l9: l9 {
+ regulator-min-microvolt = <2050000>;
+ regulator-max-microvolt = <2050000>;
+ };
+
+ pm8226_l10: l10 {
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ };
+
+ pm8226_l12: l12 {
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ };
+
+ pm8226_l14: l14 {
+ regulator-min-microvolt = <2750000>;
+ regulator-max-microvolt = <2750000>;
+ };
+
+ pm8226_l15: l15 {
+ regulator-min-microvolt = <2800000>;
+ regulator-max-microvolt = <2800000>;
+ };
+
+ pm8226_l16: l16 {
+ regulator-min-microvolt = <3000000>;
+ regulator-max-microvolt = <3350000>;
+ };
+
+ pm8226_l17: l17 {
+ regulator-min-microvolt = <2950000>;
+ regulator-max-microvolt = <2950000>;
+ };
+
+ pm8226_l18: l18 {
+ regulator-min-microvolt = <2950000>;
+ regulator-max-microvolt = <2950000>;
+ };
+
+ pm8226_l19: l19 {
+ regulator-min-microvolt = <2850000>;
+ regulator-max-microvolt = <2850000>;
+ };
+
+ pm8226_l20: l20 {
+ regulator-min-microvolt = <3075000>;
+ regulator-max-microvolt = <3075000>;
+ };
+
+ pm8226_l21: l21 {
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <2950000>;
+ regulator-allow-set-load;
+ };
+
+ pm8226_l22: l22 {
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <2950000>;
+ };
+
+ pm8226_l23: l23 {
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <2950000>;
+ };
+
+ pm8226_l24: l24 {
+ regulator-min-microvolt = <1300000>;
+ regulator-max-microvolt = <1350000>;
+ };
+
+ pm8226_l25: l25 {
+ regulator-min-microvolt = <1775000>;
+ regulator-max-microvolt = <2125000>;
+ };
+
+ pm8226_l26: l26 {
+ regulator-min-microvolt = <1225000>;
+ regulator-max-microvolt = <1225000>;
+ };
+
+ pm8226_l27: l27 {
+ regulator-min-microvolt = <2050000>;
+ regulator-max-microvolt = <2050000>;
+ };
+
+ pm8226_l28: l28 {
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <3400000>;
+ regulator-boot-on;
+ };
+
+ pm8226_lvs1: lvs1 {
+ /* Pull-up for I2C lines */
+ regulator-always-on;
+ };
+ };
+};
+
+&sdhc_1 {
+ vmmc-supply = <&pm8226_l17>;
+ vqmmc-supply = <&pm8226_l6>;
+
+ bus-width = <8>;
+ non-removable;
+
+ status = "okay";
+};
+
+&sdhc_2 {
+ vmmc-supply = <&pm8226_l18>;
+ vqmmc-supply = <&pm8226_l21>;
+
+ bus-width = <4>;
+ cd-gpios = <&tlmm 115 GPIO_ACTIVE_HIGH>;
+
+ status = "okay";
+};
+
+&smbb {
+ qcom,fast-charge-safe-current = <2000000>;
+ qcom,fast-charge-current-limit = <1900000>;
+ qcom,fast-charge-safe-voltage = <4400000>;
+ qcom,minimum-input-voltage = <4300000>;
+
+ status = "okay";
+};
+
+&usb {
+ extcon = <&smbb>;
+ dr_mode = "peripheral";
+ status = "okay";
+};
+
+&usb_hs_phy {
+ extcon = <&smbb>;
+ v1p8-supply = <&pm8226_l10>;
+ v3p3-supply = <&pm8226_l20>;
+};
diff --git a/dts/upstream/src/arm/qcom/qcom-msm8960-cdp.dts b/dts/upstream/src/arm/qcom/qcom-msm8960-cdp.dts
index 6c1bc38..36f4c99 100644
--- a/dts/upstream/src/arm/qcom/qcom-msm8960-cdp.dts
+++ b/dts/upstream/src/arm/qcom/qcom-msm8960-cdp.dts
@@ -2,6 +2,7 @@
#include <dt-bindings/input/input.h>
#include "qcom-msm8960.dtsi"
+#include "pm8921.dtsi"
/ {
model = "Qualcomm MSM8960 CDP";
@@ -88,17 +89,21 @@
};
};
-&pmicintc {
- keypad@148 {
- linux,keymap = <
- MATRIX_KEY(0, 0, KEY_VOLUMEUP)
- MATRIX_KEY(0, 1, KEY_VOLUMEDOWN)
- MATRIX_KEY(0, 2, KEY_CAMERA_FOCUS)
- MATRIX_KEY(0, 3, KEY_CAMERA)
- >;
- keypad,num-rows = <1>;
- keypad,num-columns = <5>;
- };
+&pm8921 {
+ interrupts-extended = <&msmgpio 104 IRQ_TYPE_LEVEL_LOW>;
+};
+
+&pm8921_keypad {
+ linux,keymap = <
+ MATRIX_KEY(0, 0, KEY_VOLUMEUP)
+ MATRIX_KEY(0, 1, KEY_VOLUMEDOWN)
+ MATRIX_KEY(0, 2, KEY_CAMERA_FOCUS)
+ MATRIX_KEY(0, 3, KEY_CAMERA)
+ >;
+ keypad,num-rows = <1>;
+ keypad,num-columns = <5>;
+
+ status = "okay";
};
&rpm {
diff --git a/dts/upstream/src/arm/qcom/qcom-msm8960-samsung-expressatt.dts b/dts/upstream/src/arm/qcom/qcom-msm8960-samsung-expressatt.dts
index 13e85c2..1a51163 100644
--- a/dts/upstream/src/arm/qcom/qcom-msm8960-samsung-expressatt.dts
+++ b/dts/upstream/src/arm/qcom/qcom-msm8960-samsung-expressatt.dts
@@ -1,8 +1,9 @@
// SPDX-License-Identifier: GPL-2.0
#include <dt-bindings/input/input.h>
+#include <dt-bindings/reset/qcom,gcc-msm8960.h>
#include "qcom-msm8960.dtsi"
-#include <dt-bindings/reset/qcom,gcc-msm8960.h>
+#include "pm8921.dtsi"
/ {
model = "Samsung Galaxy Express SGH-I437";
@@ -84,6 +85,10 @@
};
};
+&pm8921 {
+ interrupts-extended = <&msmgpio 104 IRQ_TYPE_LEVEL_LOW>;
+};
+
&rpm {
regulators {
compatible = "qcom,rpm-pm8921-regulators";
diff --git a/dts/upstream/src/arm/qcom/qcom-msm8960.dtsi b/dts/upstream/src/arm/qcom/qcom-msm8960.dtsi
index d13080f..f420740 100644
--- a/dts/upstream/src/arm/qcom/qcom-msm8960.dtsi
+++ b/dts/upstream/src/arm/qcom/qcom-msm8960.dtsi
@@ -200,10 +200,6 @@
<GIC_SPI 21 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 22 IRQ_TYPE_EDGE_RISING>;
interrupt-names = "ack", "err", "wakeup";
-
- regulators {
- compatible = "qcom,rpm-pm8921-regulators";
- };
};
acc0: clock-controller@2088000 {
@@ -259,49 +255,10 @@
};
};
- ssbi@500000 {
+ ssbi: ssbi@500000 {
compatible = "qcom,ssbi";
reg = <0x500000 0x1000>;
qcom,controller-type = "pmic-arbiter";
-
- pmicintc: pmic {
- compatible = "qcom,pm8921";
- interrupt-parent = <&msmgpio>;
- interrupts = <104 IRQ_TYPE_LEVEL_LOW>;
- #interrupt-cells = <2>;
- interrupt-controller;
- #address-cells = <1>;
- #size-cells = <0>;
-
- pwrkey@1c {
- compatible = "qcom,pm8921-pwrkey";
- reg = <0x1c>;
- interrupt-parent = <&pmicintc>;
- interrupts = <50 IRQ_TYPE_EDGE_RISING>,
- <51 IRQ_TYPE_EDGE_RISING>;
- debounce = <15625>;
- pull-up;
- };
-
- keypad@148 {
- compatible = "qcom,pm8921-keypad";
- reg = <0x148>;
- interrupt-parent = <&pmicintc>;
- interrupts = <74 IRQ_TYPE_EDGE_RISING>,
- <75 IRQ_TYPE_EDGE_RISING>;
- debounce = <15>;
- scan-delay = <32>;
- row-hold = <91500>;
- };
-
- rtc@11d {
- compatible = "qcom,pm8921-rtc";
- interrupt-parent = <&pmicintc>;
- interrupts = <39 IRQ_TYPE_EDGE_RISING>;
- reg = <0x11d>;
- allow-set-time;
- };
- };
};
rng@1a500000 {
diff --git a/dts/upstream/src/arm/qcom/qcom-msm8974-lge-nexus5-hammerhead.dts b/dts/upstream/src/arm/qcom/qcom-msm8974-lge-nexus5-hammerhead.dts
index 60bdfdd..4aaae85 100644
--- a/dts/upstream/src/arm/qcom/qcom-msm8974-lge-nexus5-hammerhead.dts
+++ b/dts/upstream/src/arm/qcom/qcom-msm8974-lge-nexus5-hammerhead.dts
@@ -1,7 +1,7 @@
// SPDX-License-Identifier: GPL-2.0
#include "qcom-msm8974.dtsi"
-#include "qcom-pm8841.dtsi"
-#include "qcom-pm8941.dtsi"
+#include "pm8841.dtsi"
+#include "pm8941.dtsi"
#include <dt-bindings/input/input.h>
#include <dt-bindings/leds/common.h>
#include <dt-bindings/pinctrl/qcom,pmic-gpio.h>
@@ -60,6 +60,33 @@
enable-gpios = <&tlmm 60 GPIO_ACTIVE_HIGH>;
};
+ vreg_boost: vreg-boost {
+ compatible = "regulator-fixed";
+
+ regulator-name = "vreg-boost";
+ regulator-min-microvolt = <3150000>;
+ regulator-max-microvolt = <3150000>;
+
+ regulator-always-on;
+ regulator-boot-on;
+
+ gpio = <&pm8941_gpios 21 GPIO_ACTIVE_HIGH>;
+ enable-active-high;
+
+ pinctrl-names = "default";
+ pinctrl-0 = <&boost_bypass_n_pin>;
+ };
+
+ vreg_vph_pwr: vreg-vph-pwr {
+ compatible = "regulator-fixed";
+ regulator-name = "vph-pwr";
+
+ regulator-min-microvolt = <3600000>;
+ regulator-max-microvolt = <3600000>;
+
+ regulator-always-on;
+ };
+
vreg_wlan: wlan-regulator {
compatible = "regulator-fixed";
@@ -340,6 +367,7 @@
&remoteproc_adsp {
cx-supply = <&pm8841_s2>;
+ status = "okay";
};
&remoteproc_mss {
@@ -347,6 +375,7 @@
mss-supply = <&pm8841_s3>;
mx-supply = <&pm8841_s1>;
pll-supply = <&pm8941_l12>;
+ status = "okay";
};
&rpm_requests {
diff --git a/dts/upstream/src/arm/qcom/qcom-msm8974-sony-xperia-rhine.dtsi b/dts/upstream/src/arm/qcom/qcom-msm8974-sony-xperia-rhine.dtsi
index 68a2f90..d34659e 100644
--- a/dts/upstream/src/arm/qcom/qcom-msm8974-sony-xperia-rhine.dtsi
+++ b/dts/upstream/src/arm/qcom/qcom-msm8974-sony-xperia-rhine.dtsi
@@ -1,7 +1,7 @@
// SPDX-License-Identifier: GPL-2.0
#include "qcom-msm8974.dtsi"
-#include "qcom-pm8841.dtsi"
-#include "qcom-pm8941.dtsi"
+#include "pm8841.dtsi"
+#include "pm8941.dtsi"
#include <dt-bindings/input/input.h>
#include <dt-bindings/leds/common.h>
#include <dt-bindings/pinctrl/qcom,pmic-gpio.h>
@@ -65,6 +65,33 @@
pmsg-size = <0x80000>;
};
};
+
+ vreg_boost: vreg-boost {
+ compatible = "regulator-fixed";
+
+ regulator-name = "vreg-boost";
+ regulator-min-microvolt = <3150000>;
+ regulator-max-microvolt = <3150000>;
+
+ regulator-always-on;
+ regulator-boot-on;
+
+ gpio = <&pm8941_gpios 21 GPIO_ACTIVE_HIGH>;
+ enable-active-high;
+
+ pinctrl-names = "default";
+ pinctrl-0 = <&boost_bypass_n_pin>;
+ };
+
+ vreg_vph_pwr: vreg-vph-pwr {
+ compatible = "regulator-fixed";
+ regulator-name = "vph-pwr";
+
+ regulator-min-microvolt = <3600000>;
+ regulator-max-microvolt = <3600000>;
+
+ regulator-always-on;
+ };
};
&blsp1_i2c2 {
@@ -190,6 +217,7 @@
&remoteproc_adsp {
cx-supply = <&pm8841_s2>;
+ status = "okay";
};
&remoteproc_mss {
@@ -197,6 +225,7 @@
mss-supply = <&pm8841_s3>;
mx-supply = <&pm8841_s1>;
pll-supply = <&pm8941_l12>;
+ status = "okay";
};
&rpm_requests {
@@ -425,6 +454,8 @@
qcom,fast-charge-low-threshold-voltage = <3400000>;
qcom,auto-recharge-threshold-voltage = <4200000>;
qcom,minimum-input-voltage = <4300000>;
+
+ status = "okay";
};
&tlmm {
diff --git a/dts/upstream/src/arm/qcom/qcom-msm8974.dtsi b/dts/upstream/src/arm/qcom/qcom-msm8974.dtsi
index 0bc2e66..b141398 100644
--- a/dts/upstream/src/arm/qcom/qcom-msm8974.dtsi
+++ b/dts/upstream/src/arm/qcom/qcom-msm8974.dtsi
@@ -346,6 +346,20 @@
reg = <0xf9011000 0x1000>;
};
+ saw_l2: power-controller@f9012000 {
+ compatible = "qcom,saw2";
+ reg = <0xf9012000 0x1000>;
+ regulator;
+ };
+
+ watchdog@f9017000 {
+ compatible = "qcom,apss-wdt-msm8974", "qcom,kpss-wdt";
+ reg = <0xf9017000 0x1000>;
+ interrupts = <GIC_SPI 3 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 4 IRQ_TYPE_EDGE_RISING>;
+ clocks = <&sleep_clk>;
+ };
+
timer@f9020000 {
#address-cells = <1>;
#size-cells = <1>;
@@ -405,52 +419,46 @@
};
};
- saw0: power-controller@f9089000 {
- compatible = "qcom,msm8974-saw2-v2.1-cpu", "qcom,saw2";
- reg = <0xf9089000 0x1000>, <0xf9009000 0x1000>;
- };
-
- saw1: power-controller@f9099000 {
- compatible = "qcom,msm8974-saw2-v2.1-cpu", "qcom,saw2";
- reg = <0xf9099000 0x1000>, <0xf9009000 0x1000>;
- };
-
- saw2: power-controller@f90a9000 {
- compatible = "qcom,msm8974-saw2-v2.1-cpu", "qcom,saw2";
- reg = <0xf90a9000 0x1000>, <0xf9009000 0x1000>;
- };
-
- saw3: power-controller@f90b9000 {
- compatible = "qcom,msm8974-saw2-v2.1-cpu", "qcom,saw2";
- reg = <0xf90b9000 0x1000>, <0xf9009000 0x1000>;
- };
-
- saw_l2: power-controller@f9012000 {
- compatible = "qcom,saw2";
- reg = <0xf9012000 0x1000>;
- regulator;
- };
-
acc0: power-manager@f9088000 {
compatible = "qcom,kpss-acc-v2";
reg = <0xf9088000 0x1000>, <0xf9008000 0x1000>;
};
+ saw0: power-controller@f9089000 {
+ compatible = "qcom,msm8974-saw2-v2.1-cpu", "qcom,saw2";
+ reg = <0xf9089000 0x1000>, <0xf9009000 0x1000>;
+ };
+
acc1: power-manager@f9098000 {
compatible = "qcom,kpss-acc-v2";
reg = <0xf9098000 0x1000>, <0xf9008000 0x1000>;
};
+ saw1: power-controller@f9099000 {
+ compatible = "qcom,msm8974-saw2-v2.1-cpu", "qcom,saw2";
+ reg = <0xf9099000 0x1000>, <0xf9009000 0x1000>;
+ };
+
acc2: power-manager@f90a8000 {
compatible = "qcom,kpss-acc-v2";
reg = <0xf90a8000 0x1000>, <0xf9008000 0x1000>;
};
+ saw2: power-controller@f90a9000 {
+ compatible = "qcom,msm8974-saw2-v2.1-cpu", "qcom,saw2";
+ reg = <0xf90a9000 0x1000>, <0xf9009000 0x1000>;
+ };
+
acc3: power-manager@f90b8000 {
compatible = "qcom,kpss-acc-v2";
reg = <0xf90b8000 0x1000>, <0xf9008000 0x1000>;
};
+ saw3: power-controller@f90b9000 {
+ compatible = "qcom,msm8974-saw2-v2.1-cpu", "qcom,saw2";
+ reg = <0xf90b9000 0x1000>, <0xf9009000 0x1000>;
+ };
+
sdhc_1: mmc@f9824900 {
compatible = "qcom,msm8974-sdhci", "qcom,sdhci-msm-v4";
reg = <0xf9824900 0x11c>, <0xf9824000 0x800>;
@@ -1063,6 +1071,15 @@
};
};
+ bimc: interconnect@fc380000 {
+ reg = <0xfc380000 0x6a000>;
+ compatible = "qcom,msm8974-bimc";
+ #interconnect-cells = <1>;
+ clock-names = "bus", "bus_a";
+ clocks = <&rpmcc RPM_SMD_BIMC_CLK>,
+ <&rpmcc RPM_SMD_BIMC_A_CLK>;
+ };
+
gcc: clock-controller@fc400000 {
compatible = "qcom,gcc-msm8974";
#clock-cells = <1>;
@@ -1101,22 +1118,13 @@
};
};
- bimc: interconnect@fc380000 {
- reg = <0xfc380000 0x6a000>;
- compatible = "qcom,msm8974-bimc";
- #interconnect-cells = <1>;
- clock-names = "bus", "bus_a";
- clocks = <&rpmcc RPM_SMD_BIMC_CLK>,
- <&rpmcc RPM_SMD_BIMC_A_CLK>;
- };
-
snoc: interconnect@fc460000 {
reg = <0xfc460000 0x4000>;
compatible = "qcom,msm8974-snoc";
#interconnect-cells = <1>;
clock-names = "bus", "bus_a";
clocks = <&rpmcc RPM_SMD_SNOC_CLK>,
- <&rpmcc RPM_SMD_SNOC_A_CLK>;
+ <&rpmcc RPM_SMD_SNOC_A_CLK>;
};
pnoc: interconnect@fc468000 {
@@ -1125,7 +1133,7 @@
#interconnect-cells = <1>;
clock-names = "bus", "bus_a";
clocks = <&rpmcc RPM_SMD_PNOC_CLK>,
- <&rpmcc RPM_SMD_PNOC_A_CLK>;
+ <&rpmcc RPM_SMD_PNOC_A_CLK>;
};
ocmemnoc: interconnect@fc470000 {
@@ -1134,7 +1142,7 @@
#interconnect-cells = <1>;
clock-names = "bus", "bus_a";
clocks = <&rpmcc RPM_SMD_OCMEMGX_CLK>,
- <&rpmcc RPM_SMD_OCMEMGX_A_CLK>;
+ <&rpmcc RPM_SMD_OCMEMGX_A_CLK>;
};
mmssnoc: interconnect@fc478000 {
@@ -1143,7 +1151,7 @@
#interconnect-cells = <1>;
clock-names = "bus", "bus_a";
clocks = <&mmcc MMSS_S0_AXI_CLK>,
- <&mmcc MMSS_S0_AXI_CLK>;
+ <&mmcc MMSS_S0_AXI_CLK>;
};
cnoc: interconnect@fc480000 {
@@ -1152,7 +1160,7 @@
#interconnect-cells = <1>;
clock-names = "bus", "bus_a";
clocks = <&rpmcc RPM_SMD_CNOC_CLK>,
- <&rpmcc RPM_SMD_CNOC_A_CLK>;
+ <&rpmcc RPM_SMD_CNOC_A_CLK>;
};
tsens: thermal-sensor@fc4a9000 {
@@ -1633,13 +1641,6 @@
bias-pull-up;
drive-strength = <2>;
};
-
- cd-pins {
- pins = "gpio54";
- function = "gpio";
- bias-disable;
- drive-strength = <2>;
- };
};
blsp1_uart2_default: blsp1-uart2-default-state {
@@ -2408,31 +2409,4 @@
<GIC_PPI 1 0xf08>;
clock-frequency = <19200000>;
};
-
- vreg_boost: vreg-boost {
- compatible = "regulator-fixed";
-
- regulator-name = "vreg-boost";
- regulator-min-microvolt = <3150000>;
- regulator-max-microvolt = <3150000>;
-
- regulator-always-on;
- regulator-boot-on;
-
- gpio = <&pm8941_gpios 21 GPIO_ACTIVE_HIGH>;
- enable-active-high;
-
- pinctrl-names = "default";
- pinctrl-0 = <&boost_bypass_n_pin>;
- };
-
- vreg_vph_pwr: vreg-vph-pwr {
- compatible = "regulator-fixed";
- regulator-name = "vph-pwr";
-
- regulator-min-microvolt = <3600000>;
- regulator-max-microvolt = <3600000>;
-
- regulator-always-on;
- };
};
diff --git a/dts/upstream/src/arm/qcom/qcom-msm8974pro-fairphone-fp2.dts b/dts/upstream/src/arm/qcom/qcom-msm8974pro-fairphone-fp2.dts
index 42d253b..fe227fd 100644
--- a/dts/upstream/src/arm/qcom/qcom-msm8974pro-fairphone-fp2.dts
+++ b/dts/upstream/src/arm/qcom/qcom-msm8974pro-fairphone-fp2.dts
@@ -1,7 +1,7 @@
// SPDX-License-Identifier: GPL-2.0
#include "qcom-msm8974pro.dtsi"
-#include "qcom-pm8841.dtsi"
-#include "qcom-pm8941.dtsi"
+#include "pm8841.dtsi"
+#include "pm8941.dtsi"
#include <dt-bindings/input/input.h>
#include <dt-bindings/leds/common.h>
#include <dt-bindings/pinctrl/qcom,pmic-gpio.h>
@@ -57,6 +57,33 @@
enable-gpios = <&tlmm 86 GPIO_ACTIVE_HIGH>;
vcc-supply = <&pm8941_l18>;
};
+
+ vreg_boost: vreg-boost {
+ compatible = "regulator-fixed";
+
+ regulator-name = "vreg-boost";
+ regulator-min-microvolt = <3150000>;
+ regulator-max-microvolt = <3150000>;
+
+ regulator-always-on;
+ regulator-boot-on;
+
+ gpio = <&pm8941_gpios 21 GPIO_ACTIVE_HIGH>;
+ enable-active-high;
+
+ pinctrl-names = "default";
+ pinctrl-0 = <&boost_bypass_n_pin>;
+ };
+
+ vreg_vph_pwr: vreg-vph-pwr {
+ compatible = "regulator-fixed";
+ regulator-name = "vph-pwr";
+
+ regulator-min-microvolt = <3600000>;
+ regulator-max-microvolt = <3600000>;
+
+ regulator-always-on;
+ };
};
&blsp1_i2c2 {
@@ -381,6 +408,8 @@
qcom,fast-charge-high-threshold-voltage = <4350000>;
qcom,auto-recharge-threshold-voltage = <4240000>;
qcom,minimum-input-voltage = <4450000>;
+
+ status = "okay";
};
&tlmm {
diff --git a/dts/upstream/src/arm/qcom/qcom-msm8974pro-oneplus-bacon.dts b/dts/upstream/src/arm/qcom/qcom-msm8974pro-oneplus-bacon.dts
index 8230d0e..4c8edad 100644
--- a/dts/upstream/src/arm/qcom/qcom-msm8974pro-oneplus-bacon.dts
+++ b/dts/upstream/src/arm/qcom/qcom-msm8974pro-oneplus-bacon.dts
@@ -1,7 +1,7 @@
// SPDX-License-Identifier: GPL-2.0
#include "qcom-msm8974pro.dtsi"
-#include "qcom-pm8841.dtsi"
-#include "qcom-pm8941.dtsi"
+#include "pm8841.dtsi"
+#include "pm8941.dtsi"
#include <dt-bindings/input/input.h>
#include <dt-bindings/pinctrl/qcom,pmic-gpio.h>
@@ -51,6 +51,33 @@
debounce-interval = <150>;
};
};
+
+ vreg_boost: vreg-boost {
+ compatible = "regulator-fixed";
+
+ regulator-name = "vreg-boost";
+ regulator-min-microvolt = <3150000>;
+ regulator-max-microvolt = <3150000>;
+
+ regulator-always-on;
+ regulator-boot-on;
+
+ gpio = <&pm8941_gpios 21 GPIO_ACTIVE_HIGH>;
+ enable-active-high;
+
+ pinctrl-names = "default";
+ pinctrl-0 = <&boost_bypass_n_pin>;
+ };
+
+ vreg_vph_pwr: vreg-vph-pwr {
+ compatible = "regulator-fixed";
+ regulator-name = "vph-pwr";
+
+ regulator-min-microvolt = <3600000>;
+ regulator-max-microvolt = <3600000>;
+
+ regulator-always-on;
+ };
};
&blsp1_i2c1 {
@@ -433,6 +460,10 @@
status = "okay";
};
+&smbb {
+ status = "okay";
+};
+
&tlmm {
gpio_hall_sensor_default: gpio-hall-sensor-default-state {
pins = "gpio68";
diff --git a/dts/upstream/src/arm/qcom/qcom-msm8974pro-samsung-klte.dts b/dts/upstream/src/arm/qcom/qcom-msm8974pro-samsung-klte.dts
index 3e2c865..b93539e 100644
--- a/dts/upstream/src/arm/qcom/qcom-msm8974pro-samsung-klte.dts
+++ b/dts/upstream/src/arm/qcom/qcom-msm8974pro-samsung-klte.dts
@@ -1,6 +1,6 @@
// SPDX-License-Identifier: GPL-2.0
#include "qcom-msm8974pro.dtsi"
-#include "qcom-pma8084.dtsi"
+#include "pma8084.dtsi"
#include <dt-bindings/input/input.h>
#include <dt-bindings/pinctrl/qcom,pmic-gpio.h>
#include <dt-bindings/leds/common.h>
@@ -155,7 +155,15 @@
enable-active-high;
};
- /delete-node/ vreg-boost;
+ vreg_vph_pwr: vreg-vph-pwr {
+ compatible = "regulator-fixed";
+ regulator-name = "vph-pwr";
+
+ regulator-min-microvolt = <3600000>;
+ regulator-max-microvolt = <3600000>;
+
+ regulator-always-on;
+ };
};
&blsp1_i2c2 {
@@ -355,7 +363,6 @@
vddr-supply = <&vreg_panel>;
reset-gpios = <&pma8084_gpios 17 GPIO_ACTIVE_LOW>;
- te-gpios = <&tlmm 12 GPIO_ACTIVE_HIGH>;
port {
panel_in: endpoint {
diff --git a/dts/upstream/src/arm/qcom/qcom-msm8974pro-sony-xperia-shinano-castor.dts b/dts/upstream/src/arm/qcom/qcom-msm8974pro-sony-xperia-shinano-castor.dts
index 11468d1..ee94741 100644
--- a/dts/upstream/src/arm/qcom/qcom-msm8974pro-sony-xperia-shinano-castor.dts
+++ b/dts/upstream/src/arm/qcom/qcom-msm8974pro-sony-xperia-shinano-castor.dts
@@ -1,7 +1,7 @@
// SPDX-License-Identifier: GPL-2.0
#include "qcom-msm8974pro.dtsi"
-#include "qcom-pm8841.dtsi"
-#include "qcom-pm8941.dtsi"
+#include "pm8841.dtsi"
+#include "pm8941.dtsi"
#include <dt-bindings/input/input.h>
#include <dt-bindings/leds/common.h>
#include <dt-bindings/pinctrl/qcom,pmic-gpio.h>
@@ -84,6 +84,33 @@
pinctrl-0 = <&lcd_dcdc_en_pin_a>;
};
+ vreg_boost: vreg-boost {
+ compatible = "regulator-fixed";
+
+ regulator-name = "vreg-boost";
+ regulator-min-microvolt = <3150000>;
+ regulator-max-microvolt = <3150000>;
+
+ regulator-always-on;
+ regulator-boot-on;
+
+ gpio = <&pm8941_gpios 21 GPIO_ACTIVE_HIGH>;
+ enable-active-high;
+
+ pinctrl-names = "default";
+ pinctrl-0 = <&boost_bypass_n_pin>;
+ };
+
+ vreg_vph_pwr: vreg-vph-pwr {
+ compatible = "regulator-fixed";
+ regulator-name = "vph-pwr";
+
+ regulator-min-microvolt = <3600000>;
+ regulator-max-microvolt = <3600000>;
+
+ regulator-always-on;
+ };
+
vreg_wlan: wlan-regulator {
compatible = "regulator-fixed";
@@ -297,6 +324,7 @@
&remoteproc_adsp {
cx-supply = <&pm8841_s2>;
+ status = "okay";
};
&remoteproc_mss {
@@ -304,6 +332,7 @@
mss-supply = <&pm8841_s3>;
mx-supply = <&pm8841_s1>;
pll-supply = <&pm8941_l12>;
+ status = "okay";
};
&rpm_requests {
@@ -558,6 +587,8 @@
qcom,fast-charge-low-threshold-voltage = <3400000>;
qcom,auto-recharge-threshold-voltage = <4200000>;
qcom,minimum-input-voltage = <4300000>;
+
+ status = "okay";
};
&tlmm {
diff --git a/dts/upstream/src/arm/qcom/qcom-sdx55-mtp.dts b/dts/upstream/src/arm/qcom/qcom-sdx55-mtp.dts
index 7e97ad5..2470693 100644
--- a/dts/upstream/src/arm/qcom/qcom-sdx55-mtp.dts
+++ b/dts/upstream/src/arm/qcom/qcom-sdx55-mtp.dts
@@ -9,7 +9,7 @@
#include "qcom-sdx55.dtsi"
#include <dt-bindings/regulator/qcom,rpmh-regulator.h>
#include <arm64/qcom/pm8150b.dtsi>
-#include "qcom-pmx55.dtsi"
+#include "pmx55.dtsi"
/ {
model = "Qualcomm Technologies, Inc. SDX55 MTP";
diff --git a/dts/upstream/src/arm/qcom/qcom-sdx55-t55.dts b/dts/upstream/src/arm/qcom/qcom-sdx55-t55.dts
index 51058b0..082f7ed 100644
--- a/dts/upstream/src/arm/qcom/qcom-sdx55-t55.dts
+++ b/dts/upstream/src/arm/qcom/qcom-sdx55-t55.dts
@@ -8,7 +8,7 @@
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/regulator/qcom,rpmh-regulator.h>
#include "qcom-sdx55.dtsi"
-#include "qcom-pmx55.dtsi"
+#include "pmx55.dtsi"
/ {
model = "Thundercomm T55 Development Kit";
diff --git a/dts/upstream/src/arm/qcom/qcom-sdx55-telit-fn980-tlb.dts b/dts/upstream/src/arm/qcom/qcom-sdx55-telit-fn980-tlb.dts
index 8fadc6e..e336a15 100644
--- a/dts/upstream/src/arm/qcom/qcom-sdx55-telit-fn980-tlb.dts
+++ b/dts/upstream/src/arm/qcom/qcom-sdx55-telit-fn980-tlb.dts
@@ -8,7 +8,7 @@
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/regulator/qcom,rpmh-regulator.h>
#include "qcom-sdx55.dtsi"
-#include "qcom-pmx55.dtsi"
+#include "pmx55.dtsi"
/ {
model = "Telit FN980 TLB";
diff --git a/dts/upstream/src/arm/qcom/qcom-sdx55.dtsi b/dts/upstream/src/arm/qcom/qcom-sdx55.dtsi
index 2aa5089..27429d0 100644
--- a/dts/upstream/src/arm/qcom/qcom-sdx55.dtsi
+++ b/dts/upstream/src/arm/qcom/qcom-sdx55.dtsi
@@ -228,31 +228,26 @@
usb_qmpphy: phy@ff6000 {
compatible = "qcom,sdx55-qmp-usb3-uni-phy";
- reg = <0x00ff6000 0x1c0>;
- status = "disabled";
- #address-cells = <1>;
- #size-cells = <1>;
- ranges;
+ reg = <0x00ff6000 0x1000>;
clocks = <&gcc GCC_USB3_PHY_AUX_CLK>,
+ <&gcc GCC_USB3_PRIM_CLKREF_CLK>,
<&gcc GCC_USB_PHY_CFG_AHB2PHY_CLK>,
- <&gcc GCC_USB3_PRIM_CLKREF_CLK>;
- clock-names = "aux", "cfg_ahb", "ref";
+ <&gcc GCC_USB3_PHY_PIPE_CLK>;
+ clock-names = "aux",
+ "ref",
+ "cfg_ahb",
+ "pipe";
+ clock-output-names = "usb3_uni_phy_pipe_clk_src";
+ #clock-cells = <0>;
+ #phy-cells = <0>;
- resets = <&gcc GCC_USB3PHY_PHY_BCR>,
- <&gcc GCC_USB3_PHY_BCR>;
- reset-names = "phy", "common";
+ resets = <&gcc GCC_USB3_PHY_BCR>,
+ <&gcc GCC_USB3PHY_PHY_BCR>;
+ reset-names = "phy",
+ "phy_phy";
- usb_ssphy: phy@ff6200 {
- reg = <0x00ff6200 0x170>,
- <0x00ff6400 0x200>,
- <0x00ff6800 0x800>;
- #phy-cells = <0>;
- #clock-cells = <0>;
- clocks = <&gcc GCC_USB3_PHY_PIPE_CLK>;
- clock-names = "pipe0";
- clock-output-names = "usb3_uni_phy_pipe_clk_src";
- };
+ status = "disabled";
};
mc_virt: interconnect@1100000 {
@@ -345,10 +340,10 @@
"msi8";
#interrupt-cells = <1>;
interrupt-map-mask = <0 0 0 0x7>;
- interrupt-map = <0 0 0 1 &intc 0 0 0 141 IRQ_TYPE_LEVEL_HIGH>, /* int_a */
- <0 0 0 2 &intc 0 0 0 142 IRQ_TYPE_LEVEL_HIGH>, /* int_b */
- <0 0 0 3 &intc 0 0 0 143 IRQ_TYPE_LEVEL_HIGH>, /* int_c */
- <0 0 0 4 &intc 0 0 0 144 IRQ_TYPE_LEVEL_HIGH>; /* int_d */
+ interrupt-map = <0 0 0 1 &intc 0 141 IRQ_TYPE_LEVEL_HIGH>, /* int_a */
+ <0 0 0 2 &intc 0 142 IRQ_TYPE_LEVEL_HIGH>, /* int_b */
+ <0 0 0 3 &intc 0 143 IRQ_TYPE_LEVEL_HIGH>, /* int_c */
+ <0 0 0 4 &intc 0 144 IRQ_TYPE_LEVEL_HIGH>; /* int_d */
clocks = <&gcc GCC_PCIE_PIPE_CLK>,
<&gcc GCC_PCIE_AUX_CLK>,
@@ -436,9 +431,9 @@
status = "disabled";
};
- pcie_phy: phy@1c07000 {
+ pcie_phy: phy@1c06000 {
compatible = "qcom,sdx55-qmp-pcie-phy";
- reg = <0x01c07000 0x2000>;
+ reg = <0x01c06000 0x2000>;
#address-cells = <1>;
#size-cells = <1>;
ranges;
@@ -585,10 +580,10 @@
<&gcc GCC_USB30_MASTER_CLK>;
assigned-clock-rates = <19200000>, <200000000>;
- interrupts = <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 198 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 158 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>;
+ interrupts-extended = <&intc GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>,
+ <&pdc 51 IRQ_TYPE_LEVEL_HIGH>,
+ <&pdc 11 IRQ_TYPE_EDGE_BOTH>,
+ <&pdc 10 IRQ_TYPE_EDGE_BOTH>;
interrupt-names = "hs_phy_irq", "ss_phy_irq",
"dm_hs_phy_irq", "dp_hs_phy_irq";
@@ -603,7 +598,7 @@
iommus = <&apps_smmu 0x1a0 0x0>;
snps,dis_u2_susphy_quirk;
snps,dis_enblslpm_quirk;
- phys = <&usb_hsphy>, <&usb_ssphy>;
+ phys = <&usb_hsphy>, <&usb_qmpphy>;
phy-names = "usb2-phy", "usb3-phy";
};
};
@@ -612,7 +607,7 @@
compatible = "qcom,sdx55-pdc", "qcom,pdc";
reg = <0x0b210000 0x30000>;
qcom,pdc-ranges = <0 179 52>;
- #interrupt-cells = <3>;
+ #interrupt-cells = <2>;
interrupt-parent = <&intc>;
interrupt-controller;
};
diff --git a/dts/upstream/src/arm/qcom/qcom-sdx65-mtp.dts b/dts/upstream/src/arm/qcom/qcom-sdx65-mtp.dts
index 9649c85..07c10c8 100644
--- a/dts/upstream/src/arm/qcom/qcom-sdx65-mtp.dts
+++ b/dts/upstream/src/arm/qcom/qcom-sdx65-mtp.dts
@@ -12,7 +12,7 @@
#include <dt-bindings/regulator/qcom,rpmh-regulator.h>
#include <arm64/qcom/pmk8350.dtsi>
#include <arm64/qcom/pm7250b.dtsi>
-#include "qcom-pmx65.dtsi"
+#include "pmx65.dtsi"
/ {
model = "Qualcomm Technologies, Inc. SDX65 MTP";
diff --git a/dts/upstream/src/arm/qcom/qcom-sdx65.dtsi b/dts/upstream/src/arm/qcom/qcom-sdx65.dtsi
index e559ada..40591a4 100644
--- a/dts/upstream/src/arm/qcom/qcom-sdx65.dtsi
+++ b/dts/upstream/src/arm/qcom/qcom-sdx65.dtsi
@@ -204,8 +204,16 @@
gcc: clock-controller@100000 {
compatible = "qcom,gcc-sdx65";
reg = <0x00100000 0x001f7400>;
- clocks = <&rpmhcc RPMH_CXO_CLK>, <&rpmhcc RPMH_CXO_CLK_A>, <&sleep_clk>;
- clock-names = "bi_tcxo", "bi_tcxo_ao", "sleep_clk";
+ clocks = <&rpmhcc RPMH_CXO_CLK>,
+ <&rpmhcc RPMH_CXO_CLK_A>,
+ <&sleep_clk>,
+ <&pcie_phy>,
+ <0>;
+ clock-names = "bi_tcxo",
+ "bi_tcxo_ao",
+ "sleep_clk",
+ "pcie_pipe_clk",
+ "usb3_phy_wrapper_gcc_usb30_pipe_clk";
#power-domain-cells = <1>;
#clock-cells = <1>;
#reset-cells = <1>;
@@ -233,32 +241,27 @@
usb_qmpphy: phy@ff6000 {
compatible = "qcom,sdx65-qmp-usb3-uni-phy";
- reg = <0x00ff6000 0x1c8>;
- #address-cells = <1>;
- #size-cells = <1>;
- ranges;
+ reg = <0x00ff6000 0x2000>;
clocks = <&gcc GCC_USB3_PHY_AUX_CLK>,
+ <&gcc GCC_USB3_PRIM_CLKREF_EN>,
<&gcc GCC_USB_PHY_CFG_AHB2PHY_CLK>,
- <&gcc GCC_USB3_PRIM_CLKREF_EN>;
- clock-names = "aux", "cfg_ahb", "ref";
+ <&gcc GCC_USB3_PHY_PIPE_CLK>;
+ clock-names = "aux",
+ "ref",
+ "cfg_ahb",
+ "pipe";
+ clock-output-names = "usb3_uni_phy_pipe_clk_src";
+ #clock-cells = <0>;
+ #phy-cells = <0>;
- resets = <&gcc GCC_USB3PHY_PHY_BCR>,
- <&gcc GCC_USB3_PHY_BCR>;
- reset-names = "phy", "common";
+ resets = <&gcc GCC_USB3_PHY_BCR>,
+ <&gcc GCC_USB3PHY_PHY_BCR>;
+ reset-names = "phy",
+ "phy_phy";
status = "disabled";
- usb_ssphy: phy@ff6200 {
- reg = <0x00ff6e00 0x160>,
- <0x00ff7000 0x1ec>,
- <0x00ff6200 0x1e00>;
- #phy-cells = <0>;
- #clock-cells = <0>;
- clocks = <&gcc GCC_USB3_PHY_PIPE_CLK>;
- clock-names = "pipe0";
- clock-output-names = "usb3_uni_phy_pipe_clk_src";
- };
};
system_noc: interconnect@1620000 {
@@ -338,7 +341,7 @@
power-domains = <&gcc PCIE_GDSC>;
phys = <&pcie_phy>;
- phy-names = "pcie-phy";
+ phy-names = "pciephy";
max-link-speed = <3>;
num-lanes = <2>;
@@ -520,7 +523,7 @@
iommus = <&apps_smmu 0x1a0 0x0>;
snps,dis_u2_susphy_quirk;
snps,dis_enblslpm_quirk;
- phys = <&usb_hsphy>, <&usb_ssphy>;
+ phys = <&usb_hsphy>, <&usb_qmpphy>;
phy-names = "usb2-phy", "usb3-phy";
};
};
@@ -530,7 +533,7 @@
reg = <0x0c264000 0x1000>;
};
- spmi_bus: qcom,spmi@c440000 {
+ spmi_bus: spmi@c440000 {
compatible = "qcom,spmi-pmic-arb";
reg = <0xc440000 0xd00>,
<0xc600000 0x2000000>,
diff --git a/dts/upstream/src/arm/renesas/iwg20d-q7-dbcm-ca.dtsi b/dts/upstream/src/arm/renesas/iwg20d-q7-dbcm-ca.dtsi
index e10f992..de52218 100644
--- a/dts/upstream/src/arm/renesas/iwg20d-q7-dbcm-ca.dtsi
+++ b/dts/upstream/src/arm/renesas/iwg20d-q7-dbcm-ca.dtsi
@@ -27,6 +27,15 @@
};
};
};
+
+ reg_1p8v: regulator-1p8v {
+ compatible = "regulator-fixed";
+ regulator-name = "1P8V";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-boot-on;
+ regulator-always-on;
+ };
};
&can1 {
@@ -69,6 +78,12 @@
clocks = <&cec_clock>;
clock-names = "cec";
+ avdd-supply = <®_1p8v>;
+ dvdd-supply = <®_1p8v>;
+ pvdd-supply = <®_1p8v>;
+ dvdd-3v-supply = <®_3p3v>;
+ bgvdd-supply = <®_1p8v>;
+
adi,input-depth = <8>;
adi,input-colorspace = "rgb";
adi,input-clock = "1x";
diff --git a/dts/upstream/src/arm/renesas/r8a7740-armadillo800eva.dts b/dts/upstream/src/arm/renesas/r8a7740-armadillo800eva.dts
index d21e00e..e1ac2c1 100644
--- a/dts/upstream/src/arm/renesas/r8a7740-armadillo800eva.dts
+++ b/dts/upstream/src/arm/renesas/r8a7740-armadillo800eva.dts
@@ -132,7 +132,7 @@
i2c-gpio,delay-us = <5>;
};
- backlight {
+ backlight: backlight {
compatible = "pwm-backlight";
pwms = <&tpu 2 33333 PWM_POLARITY_INVERTED>;
brightness-levels = <0 1 2 4 8 16 32 64 128 255>;
@@ -143,6 +143,18 @@
enable-gpios = <&pfc 61 GPIO_ACTIVE_HIGH>;
};
+ panel {
+ compatible = "ampire,am-800480l1tmqw-t00h";
+ backlight = <&backlight>;
+ power-supply = <®_5p0v>;
+
+ port {
+ panel_in: endpoint {
+ remote-endpoint = <&lcdc0_rgb>;
+ };
+ };
+ };
+
sound {
compatible = "simple-audio-card";
@@ -228,10 +240,22 @@
};
};
-&pfc {
+&lcdc0 {
pinctrl-0 = <&lcd0_pins>;
pinctrl-names = "default";
+ status = "okay";
+
+ ports {
+ port@0 {
+ endpoint {
+ remote-endpoint = <&panel_in>;
+ };
+ };
+ };
+};
+
+&pfc {
ether_pins: ether {
groups = "gether_mii", "gether_int";
function = "gether";
diff --git a/dts/upstream/src/arm/renesas/r8a7740.dtsi b/dts/upstream/src/arm/renesas/r8a7740.dtsi
index 1b2cf5f..55884ec 100644
--- a/dts/upstream/src/arm/renesas/r8a7740.dtsi
+++ b/dts/upstream/src/arm/renesas/r8a7740.dtsi
@@ -398,6 +398,61 @@
status = "disabled";
};
+ lcdc0: lcd-controller@fe940000 {
+ compatible = "renesas,r8a7740-lcdc";
+ reg = <0xfe940000 0x4000>;
+ interrupts = <GIC_SPI 177 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&mstp1_clks R8A7740_CLK_LCDC0>,
+ <&cpg_clocks R8A7740_CLK_M3>, <&lcdlclk0_clk>,
+ <&vou_clk>;
+ clock-names = "fck", "media", "lclk", "video";
+ power-domains = <&pd_a4lc>;
+ status = "disabled";
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+
+ lcdc0_rgb: endpoint {
+ };
+ };
+ };
+ };
+
+ lcdc1: lcd-controller@fe944000 {
+ compatible = "renesas,r8a7740-lcdc";
+ reg = <0xfe944000 0x4000>;
+ interrupts = <GIC_SPI 178 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&mstp1_clks R8A7740_CLK_LCDC1>,
+ <&cpg_clocks R8A7740_CLK_M3>, <&lcdlclk1_clk>,
+ <&vou_clk>;
+ clock-names = "fck", "media", "lclk", "video";
+ power-domains = <&pd_a4lc>;
+ status = "disabled";
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+
+ lcdc1_rgb: endpoint {
+ };
+ };
+
+ port@1 {
+ reg = <1>;
+
+ lcdc1_hdmi: endpoint {
+ };
+ };
+ };
+ };
+
tmu0: timer@fff80000 {
compatible = "renesas,tmu-r8a7740", "renesas,tmu";
reg = <0xfff80000 0x2c>;
@@ -474,6 +529,16 @@
#clock-cells = <0>;
clock-frequency = <0>;
};
+ lcdlclk0_clk: lcdlclk0 {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <0>;
+ };
+ lcdlclk1_clk: lcdlclk1 {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <0>;
+ };
/* Special CPG clocks */
cpg_clocks: cpg_clocks@e6150000 {
diff --git a/dts/upstream/src/arm/renesas/r8a7745-iwg22d-sodimm-dbhd-ca.dts b/dts/upstream/src/arm/renesas/r8a7745-iwg22d-sodimm-dbhd-ca.dts
index b1f679d..a0b5743 100644
--- a/dts/upstream/src/arm/renesas/r8a7745-iwg22d-sodimm-dbhd-ca.dts
+++ b/dts/upstream/src/arm/renesas/r8a7745-iwg22d-sodimm-dbhd-ca.dts
@@ -34,6 +34,15 @@
};
};
};
+
+ reg_1p8v: regulator-1p8v {
+ compatible = "regulator-fixed";
+ regulator-name = "1P8V";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-boot-on;
+ regulator-always-on;
+ };
};
&du {
@@ -81,6 +90,12 @@
clock-names = "cec";
pd-gpios = <&gpio2 24 GPIO_ACTIVE_HIGH>;
+ avdd-supply = <®_1p8v>;
+ dvdd-supply = <®_1p8v>;
+ pvdd-supply = <®_1p8v>;
+ dvdd-3v-supply = <®_3p3v>;
+ bgvdd-supply = <®_1p8v>;
+
adi,input-depth = <8>;
adi,input-colorspace = "rgb";
adi,input-clock = "1x";
diff --git a/dts/upstream/src/arm/renesas/r8a7745-iwg22d-sodimm.dts b/dts/upstream/src/arm/renesas/r8a7745-iwg22d-sodimm.dts
index c105932..2441104 100644
--- a/dts/upstream/src/arm/renesas/r8a7745-iwg22d-sodimm.dts
+++ b/dts/upstream/src/arm/renesas/r8a7745-iwg22d-sodimm.dts
@@ -182,7 +182,7 @@
VDDIO-supply = <®_3p3v>;
};
- stmpe811@44 {
+ port-expander@44 {
compatible = "st,stmpe811";
reg = <0x44>;
interrupt-parent = <&gpio4>;
@@ -197,7 +197,7 @@
/* internal ADC reference */
st,ref-sel = <0>;
- stmpe_touchscreen {
+ touchscreen {
compatible = "st,stmpe-ts";
/* 8 sample average control */
st,ave-ctrl = <3>;
diff --git a/dts/upstream/src/arm/renesas/r8a7779-marzen.dts b/dts/upstream/src/arm/renesas/r8a7779-marzen.dts
index 08ea149..9b13e8d 100644
--- a/dts/upstream/src/arm/renesas/r8a7779-marzen.dts
+++ b/dts/upstream/src/arm/renesas/r8a7779-marzen.dts
@@ -52,10 +52,10 @@
states = <3300000 1>, <1800000 0>;
};
- keyboard-irq {
+ keypad-0 {
compatible = "gpio-keys";
- pinctrl-0 = <&keyboard_irq_pins>;
+ pinctrl-0 = <&keypad0_pins>;
pinctrl-names = "default";
interrupt-parent = <&gpio0>;
@@ -76,11 +76,11 @@
};
};
- keyboard-gpio {
+ keypad-1 {
compatible = "gpio-keys-polled";
poll-interval = <50>;
- pinctrl-0 = <&keyboard_gpio_pins>;
+ pinctrl-0 = <&keypad1_pins>;
pinctrl-names = "default";
key-3 {
@@ -193,7 +193,7 @@
};
&gpio0 {
- keyboard-irq-hog {
+ keypad0-hog {
gpio-hog;
gpios = <17 GPIO_ACTIVE_LOW>, <18 GPIO_ACTIVE_LOW>;
input;
@@ -215,6 +215,35 @@
};
&lbsc {
+ flash@0 {
+ compatible = "cfi-flash";
+ reg = <0x0 0x04000000>;
+ pinctrl-0 = <&flash_pins>;
+ pinctrl-names = "default";
+ bank-width = <2>;
+
+ partitions {
+ compatible = "fixed-partitions";
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ partition@0 {
+ label = "uboot";
+ reg = <0x00000000 0x00040000>;
+ read-only;
+ };
+ partition@40000 {
+ label = "uboot-env";
+ reg = <0x00040000 0x00040000>;
+ read-only;
+ };
+ partition@80000 {
+ label = "flash";
+ reg = <0x00080000 0x03f80000>;
+ };
+ };
+ };
+
ethernet@18000000 {
compatible = "smsc,lan89218", "smsc,lan9115";
reg = <0x18000000 0x100>;
@@ -266,6 +295,11 @@
};
};
+ flash_pins: flash {
+ groups = "lbsc_cs0";
+ function = "lbsc";
+ };
+
scif2_pins: scif2 {
groups = "scif2_data_c";
function = "scif2";
@@ -286,11 +320,11 @@
function = "hspi0";
};
- keyboard_irq_pins: keyboard-irq {
+ keypad0_pins: keypad-0 {
pins = "GP_0_17", "GP_0_18";
bias-pull-up;
};
- keyboard_gpio_pins: keyboard-gpio {
+ keypad1_pins: keypad-1 {
pins = "GP_0_19", "GP_0_20";
bias-pull-up;
};
diff --git a/dts/upstream/src/arm/renesas/r8a7790-lager.dts b/dts/upstream/src/arm/renesas/r8a7790-lager.dts
index 4d666ad..8590981 100644
--- a/dts/upstream/src/arm/renesas/r8a7790-lager.dts
+++ b/dts/upstream/src/arm/renesas/r8a7790-lager.dts
@@ -122,6 +122,15 @@
};
};
+ fixedregulator1v8: regulator-1v8 {
+ compatible = "regulator-fixed";
+ regulator-name = "fixed-1.8V";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-boot-on;
+ regulator-always-on;
+ };
+
fixedregulator3v3: regulator-3v3 {
compatible = "regulator-fixed";
regulator-name = "fixed-3.3V";
@@ -303,7 +312,7 @@
*
* IIC0/I2C0 does not appear to support fallback to GPIO.
*/
- i2cexio0: i2c-10 {
+ i2cexio0: i2c-mux1 {
compatible = "i2c-demux-pinctrl";
i2c-parent = <&iic0>, <&i2c0>;
i2c-bus-name = "i2c-exio0";
@@ -316,7 +325,7 @@
* This is similar to the arangement described for i2cexio0 (above)
* with a fallback to GPIO also provided.
*/
- i2cexio1: i2c-11 {
+ i2cexio1: i2c-mux2 {
compatible = "i2c-demux-pinctrl";
i2c-parent = <&iic1>, <&i2c1>, <&gpioi2c1>;
i2c-bus-name = "i2c-exio1";
@@ -328,7 +337,7 @@
* IIC2 and I2C2 may be switched using pinmux.
* A fallback to GPIO is also provided.
*/
- i2chdmi: i2c-12 {
+ i2chdmi: i2c-mux3 {
compatible = "i2c-demux-pinctrl";
i2c-parent = <&iic2>, <&i2c2>, <&gpioi2c2>;
i2c-bus-name = "i2c-hdmi";
@@ -361,6 +370,12 @@
clocks = <&cec_clock>;
clock-names = "cec";
+ avdd-supply = <&fixedregulator1v8>;
+ dvdd-supply = <&fixedregulator1v8>;
+ pvdd-supply = <&fixedregulator1v8>;
+ dvdd-3v-supply = <&fixedregulator3v3>;
+ bgvdd-supply = <&fixedregulator1v8>;
+
adi,input-depth = <8>;
adi,input-colorspace = "rgb";
adi,input-clock = "1x";
@@ -417,7 +432,7 @@
* IIC3 and I2C3 may be switched using pinmux.
* IIC3/I2C3 does not appear to support fallback to GPIO.
*/
- i2cpwr: i2c-13 {
+ i2cpwr: i2c-mux4 {
compatible = "i2c-demux-pinctrl";
pinctrl-names = "default";
pinctrl-0 = <&pmic_irq_pins>;
@@ -432,6 +447,7 @@
interrupt-parent = <&irqc0>;
interrupts = <2 IRQ_TYPE_LEVEL_LOW>;
interrupt-controller;
+ #interrupt-cells = <2>;
rtc {
compatible = "dlg,da9063-rtc";
diff --git a/dts/upstream/src/arm/renesas/r8a7790-stout.dts b/dts/upstream/src/arm/renesas/r8a7790-stout.dts
index fe14727..683f739 100644
--- a/dts/upstream/src/arm/renesas/r8a7790-stout.dts
+++ b/dts/upstream/src/arm/renesas/r8a7790-stout.dts
@@ -44,6 +44,15 @@
};
};
+ fixedregulator1v8: regulator-1v8 {
+ compatible = "regulator-fixed";
+ regulator-name = "fixed-1.8V";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-boot-on;
+ regulator-always-on;
+ };
+
fixedregulator3v3: regulator-3v3 {
compatible = "regulator-fixed";
regulator-name = "fixed-3.3V";
@@ -296,6 +305,12 @@
clocks = <&osc4_clk>;
clock-names = "cec";
+ avdd-supply = <&fixedregulator1v8>;
+ dvdd-supply = <&fixedregulator1v8>;
+ pvdd-supply = <&fixedregulator1v8>;
+ dvdd-3v-supply = <&fixedregulator3v3>;
+ bgvdd-supply = <&fixedregulator1v8>;
+
adi,input-depth = <8>;
adi,input-colorspace = "rgb";
adi,input-clock = "1x";
@@ -332,6 +347,7 @@
interrupt-parent = <&irqc0>;
interrupts = <2 IRQ_TYPE_LEVEL_LOW>;
interrupt-controller;
+ #interrupt-cells = <2>;
onkey {
compatible = "dlg,da9063-onkey";
diff --git a/dts/upstream/src/arm/renesas/r8a7791-koelsch.dts b/dts/upstream/src/arm/renesas/r8a7791-koelsch.dts
index 545515b..0efd9f9 100644
--- a/dts/upstream/src/arm/renesas/r8a7791-koelsch.dts
+++ b/dts/upstream/src/arm/renesas/r8a7791-koelsch.dts
@@ -174,6 +174,24 @@
};
};
+ reg_1p8v: regulator-1v8 {
+ compatible = "regulator-fixed";
+ regulator-name = "fixed-1.8V";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-boot-on;
+ regulator-always-on;
+ };
+
+ reg_3p3v: regulator-3v3 {
+ compatible = "regulator-fixed";
+ regulator-name = "fixed-3.3V";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-boot-on;
+ regulator-always-on;
+ };
+
vcc_sdhi0: regulator-vcc-sdhi0 {
compatible = "regulator-fixed";
@@ -340,7 +358,7 @@
* I2C1 is routed to EXIO connector B, pins 64 (SCL) + 66 (SDA).
* A fallback to GPIO is provided.
*/
- i2cexio1: i2c-12 {
+ i2cexio1: i2c-mux1 {
compatible = "i2c-demux-pinctrl";
i2c-parent = <&i2c1>, <&gpioi2c1>;
i2c-bus-name = "i2c-exio1";
@@ -351,7 +369,7 @@
/*
* A fallback to GPIO is provided for I2C2.
*/
- i2chdmi: i2c-13 {
+ i2chdmi: i2c-mux2 {
compatible = "i2c-demux-pinctrl";
i2c-parent = <&i2c2>, <&gpioi2c2>;
i2c-bus-name = "i2c-hdmi";
@@ -384,6 +402,12 @@
clocks = <&cec_clock>;
clock-names = "cec";
+ avdd-supply = <®_1p8v>;
+ dvdd-supply = <®_1p8v>;
+ pvdd-supply = <®_1p8v>;
+ dvdd-3v-supply = <®_3p3v>;
+ bgvdd-supply = <®_1p8v>;
+
adi,input-depth = <8>;
adi,input-colorspace = "rgb";
adi,input-clock = "1x";
@@ -446,7 +470,7 @@
* I2C4 is routed to EXIO connector E, pins 37 (SCL) + 39 (SDA).
* A fallback to GPIO is provided.
*/
- i2cexio4: i2c-14 {
+ i2cexio4: i2c-mux3 {
compatible = "i2c-demux-pinctrl";
i2c-parent = <&i2c4>, <&gpioi2c4>;
i2c-bus-name = "i2c-exio4";
@@ -795,6 +819,7 @@
interrupt-parent = <&irqc0>;
interrupts = <2 IRQ_TYPE_LEVEL_LOW>;
interrupt-controller;
+ #interrupt-cells = <2>;
rtc {
compatible = "dlg,da9063-rtc";
diff --git a/dts/upstream/src/arm/renesas/r8a7791-porter.dts b/dts/upstream/src/arm/renesas/r8a7791-porter.dts
index ec0a20d..93c86e9 100644
--- a/dts/upstream/src/arm/renesas/r8a7791-porter.dts
+++ b/dts/upstream/src/arm/renesas/r8a7791-porter.dts
@@ -47,6 +47,24 @@
reg = <2 0x00000000 0 0x40000000>;
};
+ reg_1p8v: regulator-1v8 {
+ compatible = "regulator-fixed";
+ regulator-name = "fixed-1.8V";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-boot-on;
+ regulator-always-on;
+ };
+
+ reg_3p3v: regulator-3v3 {
+ compatible = "regulator-fixed";
+ regulator-name = "fixed-3.3V";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-boot-on;
+ regulator-always-on;
+ };
+
vcc_sdhi0: regulator-vcc-sdhi0 {
compatible = "regulator-fixed";
@@ -148,7 +166,7 @@
/*
* A fallback to GPIO is provided for I2C2.
*/
- i2chdmi: i2c-10 {
+ i2chdmi: i2c-mux1 {
compatible = "i2c-demux-pinctrl";
i2c-parent = <&i2c2>, <&gpioi2c2>;
i2c-bus-name = "i2c-hdmi";
@@ -179,6 +197,12 @@
interrupt-parent = <&gpio3>;
interrupts = <29 IRQ_TYPE_LEVEL_LOW>;
+ avdd-supply = <®_1p8v>;
+ dvdd-supply = <®_1p8v>;
+ pvdd-supply = <®_1p8v>;
+ dvdd-3v-supply = <®_3p3v>;
+ bgvdd-supply = <®_1p8v>;
+
adi,input-depth = <8>;
adi,input-colorspace = "rgb";
adi,input-clock = "1x";
@@ -389,6 +413,7 @@
interrupt-parent = <&irqc0>;
interrupts = <2 IRQ_TYPE_LEVEL_LOW>;
interrupt-controller;
+ #interrupt-cells = <2>;
watchdog {
compatible = "dlg,da9063-watchdog";
diff --git a/dts/upstream/src/arm/renesas/r8a7792-blanche.dts b/dts/upstream/src/arm/renesas/r8a7792-blanche.dts
index e793134..540a9ad 100644
--- a/dts/upstream/src/arm/renesas/r8a7792-blanche.dts
+++ b/dts/upstream/src/arm/renesas/r8a7792-blanche.dts
@@ -30,6 +30,15 @@
reg = <0 0x40000000 0 0x40000000>;
};
+ d1_8v: regulator-1v8 {
+ compatible = "regulator-fixed";
+ regulator-name = "D1.8V";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-boot-on;
+ regulator-always-on;
+ };
+
d3_3v: regulator-3v3 {
compatible = "regulator-fixed";
regulator-name = "D3.3V";
@@ -182,6 +191,35 @@
};
&lbsc {
+ flash@0 {
+ compatible = "cfi-flash";
+ reg = <0x00000000 0x04000000>;
+ pinctrl-0 = <&flash_pins>;
+ pinctrl-names = "default";
+ bank-width = <2>;
+
+ partitions {
+ compatible = "fixed-partitions";
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ partition@0 {
+ label = "uboot";
+ reg = <0x00000000 0x00040000>;
+ read-only;
+ };
+ partition@40000 {
+ label = "uboot-env";
+ reg = <0x00040000 0x00040000>;
+ read-only;
+ };
+ partition@80000 {
+ label = "flash";
+ reg = <0x00080000 0x03f80000>;
+ };
+ };
+ };
+
ethernet@18000000 {
compatible = "smsc,lan89218", "smsc,lan9115";
reg = <0x18000000 0x100>;
@@ -240,6 +278,11 @@
function = "du1";
};
+ flash_pins: flash {
+ groups = "lbsc_cs0";
+ function = "lbsc";
+ };
+
keyboard_pins: keyboard {
pins = "GP_3_10", "GP_3_11", "GP_3_12", "GP_3_15", "GP_11_2";
bias-pull-up;
@@ -296,6 +339,12 @@
interrupt-parent = <&irqc>;
interrupts = <3 IRQ_TYPE_EDGE_FALLING>;
+ avdd-supply = <&d1_8v>;
+ dvdd-supply = <&d1_8v>;
+ pvdd-supply = <&d1_8v>;
+ dvdd-3v-supply = <&d3_3v>;
+ bgvdd-supply = <&d1_8v>;
+
adi,input-depth = <8>;
adi,input-colorspace = "rgb";
adi,input-clock = "1x";
@@ -332,6 +381,7 @@
interrupt-parent = <&irqc>;
interrupts = <2 IRQ_TYPE_LEVEL_LOW>;
interrupt-controller;
+ #interrupt-cells = <2>;
rtc {
compatible = "dlg,da9063-rtc";
diff --git a/dts/upstream/src/arm/renesas/r8a7792-wheat.dts b/dts/upstream/src/arm/renesas/r8a7792-wheat.dts
index f87e78f..000f21a 100644
--- a/dts/upstream/src/arm/renesas/r8a7792-wheat.dts
+++ b/dts/upstream/src/arm/renesas/r8a7792-wheat.dts
@@ -29,6 +29,15 @@
reg = <0 0x40000000 0 0x40000000>;
};
+ d1_8v: regulator-1v8 {
+ compatible = "regulator-fixed";
+ regulator-name = "D1.8V";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-boot-on;
+ regulator-always-on;
+ };
+
d3_3v: regulator-3v3 {
compatible = "regulator-fixed";
regulator-name = "D3.3V";
@@ -254,6 +263,12 @@
reg = <0x3d>, <0x4d>, <0x2d>, <0x5d>;
reg-names = "main", "edid", "cec", "packet";
+ avdd-supply = <&d1_8v>;
+ dvdd-supply = <&d1_8v>;
+ pvdd-supply = <&d1_8v>;
+ dvdd-3v-supply = <&d3_3v>;
+ bgvdd-supply = <&d1_8v>;
+
adi,input-depth = <8>;
adi,input-colorspace = "rgb";
adi,input-clock = "1x";
@@ -283,6 +298,12 @@
reg = <0x39>, <0x49>, <0x29>, <0x59>;
reg-names = "main", "edid", "cec", "packet";
+ avdd-supply = <&d1_8v>;
+ dvdd-supply = <&d1_8v>;
+ pvdd-supply = <&d1_8v>;
+ dvdd-3v-supply = <&d3_3v>;
+ bgvdd-supply = <&d1_8v>;
+
adi,input-depth = <8>;
adi,input-colorspace = "rgb";
adi,input-clock = "1x";
diff --git a/dts/upstream/src/arm/renesas/r8a7793-gose.dts b/dts/upstream/src/arm/renesas/r8a7793-gose.dts
index 79b537b..1ea6c75 100644
--- a/dts/upstream/src/arm/renesas/r8a7793-gose.dts
+++ b/dts/upstream/src/arm/renesas/r8a7793-gose.dts
@@ -165,6 +165,24 @@
};
};
+ reg_1p8v: regulator-1v8 {
+ compatible = "regulator-fixed";
+ regulator-name = "fixed-1.8V";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-boot-on;
+ regulator-always-on;
+ };
+
+ reg_3p3v: regulator-3v3 {
+ compatible = "regulator-fixed";
+ regulator-name = "fixed-3.3V";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-boot-on;
+ regulator-always-on;
+ };
+
vcc_sdhi0: regulator-vcc-sdhi0 {
compatible = "regulator-fixed";
@@ -324,7 +342,7 @@
/*
* A fallback to GPIO is provided for I2C2.
*/
- i2chdmi: i2c-11 {
+ i2chdmi: i2c-mux1 {
compatible = "i2c-demux-pinctrl";
i2c-parent = <&i2c2>, <&gpioi2c2>;
i2c-bus-name = "i2c-hdmi";
@@ -368,6 +386,12 @@
interrupt-parent = <&gpio3>;
interrupts = <29 IRQ_TYPE_LEVEL_LOW>;
+ avdd-supply = <®_1p8v>;
+ dvdd-supply = <®_1p8v>;
+ pvdd-supply = <®_1p8v>;
+ dvdd-3v-supply = <®_3p3v>;
+ bgvdd-supply = <®_1p8v>;
+
adi,input-depth = <8>;
adi,input-colorspace = "rgb";
adi,input-clock = "1x";
@@ -430,7 +454,7 @@
* I2C4 is routed to EXIO connector E, pins 37 (SCL) + 39 (SDA).
* A fallback to GPIO is provided.
*/
- i2cexio4: i2c-12 {
+ i2cexio4: i2c-mux2 {
compatible = "i2c-demux-pinctrl";
i2c-parent = <&i2c4>, <&gpioi2c4>;
i2c-bus-name = "i2c-exio4";
@@ -735,6 +759,7 @@
interrupt-parent = <&irqc0>;
interrupts = <2 IRQ_TYPE_LEVEL_LOW>;
interrupt-controller;
+ #interrupt-cells = <2>;
rtc {
compatible = "dlg,da9063-rtc";
diff --git a/dts/upstream/src/arm/renesas/r8a7794-alt.dts b/dts/upstream/src/arm/renesas/r8a7794-alt.dts
index 08df031..b5ecafb 100644
--- a/dts/upstream/src/arm/renesas/r8a7794-alt.dts
+++ b/dts/upstream/src/arm/renesas/r8a7794-alt.dts
@@ -192,7 +192,7 @@
/*
* A fallback to GPIO is provided for I2C1.
*/
- i2chdmi: i2c-11 {
+ i2chdmi: i2c-mux1 {
compatible = "i2c-demux-pinctrl";
i2c-parent = <&i2c1>, <&gpioi2c1>;
i2c-bus-name = "i2c-hdmi";
@@ -222,7 +222,7 @@
* I2C4 is routed to EXIO connector B, pins 73 (SCL) + 74 (SDA).
* A fallback to GPIO is provided.
*/
- i2cexio4: i2c-14 {
+ i2cexio4: i2c-mux2 {
compatible = "i2c-demux-pinctrl";
i2c-parent = <&i2c4>, <&gpioi2c4>;
i2c-bus-name = "i2c-exio4";
@@ -453,6 +453,7 @@
interrupt-parent = <&gpio3>;
interrupts = <31 IRQ_TYPE_LEVEL_LOW>;
interrupt-controller;
+ #interrupt-cells = <2>;
rtc {
compatible = "dlg,da9063-rtc";
diff --git a/dts/upstream/src/arm/renesas/r8a7794-silk.dts b/dts/upstream/src/arm/renesas/r8a7794-silk.dts
index b7af1be..595e074 100644
--- a/dts/upstream/src/arm/renesas/r8a7794-silk.dts
+++ b/dts/upstream/src/arm/renesas/r8a7794-silk.dts
@@ -102,6 +102,15 @@
};
};
+ d1_8v: regulator-d1-8v {
+ compatible = "regulator-fixed";
+ regulator-name = "D1.8V";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-boot-on;
+ regulator-always-on;
+ };
+
d3_3v: regulator-d3-3v {
compatible = "regulator-fixed";
regulator-name = "D3.3V";
@@ -225,7 +234,7 @@
/*
* A fallback to GPIO is provided for I2C1.
*/
- i2chdmi: i2c-10 {
+ i2chdmi: i2c-mux1 {
compatible = "i2c-demux-pinctrl";
i2c-parent = <&i2c1>, <&gpioi2c1>;
i2c-bus-name = "i2c-hdmi";
@@ -256,6 +265,12 @@
interrupt-parent = <&gpio5>;
interrupts = <23 IRQ_TYPE_LEVEL_LOW>;
+ avdd-supply = <&d1_8v>;
+ dvdd-supply = <&d1_8v>;
+ pvdd-supply = <&d1_8v>;
+ dvdd-3v-supply = <&d3_3v>;
+ bgvdd-supply = <&d1_8v>;
+
adi,input-depth = <8>;
adi,input-colorspace = "rgb";
adi,input-clock = "1x";
@@ -424,6 +439,7 @@
interrupt-parent = <&gpio3>;
interrupts = <31 IRQ_TYPE_LEVEL_LOW>;
interrupt-controller;
+ #interrupt-cells = <2>;
onkey {
compatible = "dlg,da9063-onkey";
diff --git a/dts/upstream/src/arm/renesas/r9a06g032.dtsi b/dts/upstream/src/arm/renesas/r9a06g032.dtsi
index 0fa565a..fa63e1a 100644
--- a/dts/upstream/src/arm/renesas/r9a06g032.dtsi
+++ b/dts/upstream/src/arm/renesas/r9a06g032.dtsi
@@ -437,7 +437,7 @@
};
can0: can@52104000 {
- compatible = "renesas,r9a06g032-sja1000","renesas,rzn1-sja1000";
+ compatible = "renesas,r9a06g032-sja1000", "renesas,rzn1-sja1000";
reg = <0x52104000 0x800>;
reg-io-width = <4>;
interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>;
diff --git a/dts/upstream/src/arm/rockchip/rk3036-kylin.dts b/dts/upstream/src/arm/rockchip/rk3036-kylin.dts
index 67e1e04..e32c73d 100644
--- a/dts/upstream/src/arm/rockchip/rk3036-kylin.dts
+++ b/dts/upstream/src/arm/rockchip/rk3036-kylin.dts
@@ -8,11 +8,26 @@
model = "Rockchip RK3036 KylinBoard";
compatible = "rockchip,rk3036-kylin", "rockchip,rk3036";
+ chosen {
+ stdout-path = "serial2:115200n8";
+ };
+
memory@60000000 {
device_type = "memory";
reg = <0x60000000 0x20000000>;
};
+ hdmi_con: hdmi-con {
+ compatible = "hdmi-connector";
+ type = "a";
+
+ port {
+ hdmi_con_in: endpoint {
+ remote-endpoint = <&hdmi_out_con>;
+ };
+ };
+ };
+
leds: gpio-leds {
compatible = "gpio-leds";
@@ -110,6 +125,12 @@
status = "okay";
};
+&hdmi_out {
+ hdmi_out_con: endpoint {
+ remote-endpoint = <&hdmi_con_in>;
+ };
+};
+
&i2c1 {
clock-frequency = <400000>;
diff --git a/dts/upstream/src/arm/rockchip/rk3036.dtsi b/dts/upstream/src/arm/rockchip/rk3036.dtsi
index 78686fc..04af224 100644
--- a/dts/upstream/src/arm/rockchip/rk3036.dtsi
+++ b/dts/upstream/src/arm/rockchip/rk3036.dtsi
@@ -17,6 +17,9 @@
interrupt-parent = <&gic>;
aliases {
+ gpio0 = &gpio0;
+ gpio1 = &gpio1;
+ gpio2 = &gpio2;
i2c0 = &i2c0;
i2c1 = &i2c1;
i2c2 = &i2c2;
@@ -282,7 +285,6 @@
clocks = <&cru HCLK_EMMC>, <&cru SCLK_EMMC>,
<&cru SCLK_EMMC_DRV>, <&cru SCLK_EMMC_SAMPLE>;
clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
- rockchip,default-sample-phase = <158>;
disable-wp;
dmas = <&pdma 12>;
dma-names = "rx-tx";
@@ -402,12 +404,20 @@
pinctrl-0 = <&hdmi_ctl>;
status = "disabled";
- hdmi_in: port {
+ ports {
#address-cells = <1>;
#size-cells = <0>;
- hdmi_in_vop: endpoint@0 {
+
+ hdmi_in: port@0 {
reg = <0>;
- remote-endpoint = <&vop_out_hdmi>;
+
+ hdmi_in_vop: endpoint {
+ remote-endpoint = <&vop_out_hdmi>;
+ };
+ };
+
+ hdmi_out: port@1 {
+ reg = <1>;
};
};
};
diff --git a/dts/upstream/src/arm/rockchip/rk3066a.dtsi b/dts/upstream/src/arm/rockchip/rk3066a.dtsi
index de9915d..30139f2 100644
--- a/dts/upstream/src/arm/rockchip/rk3066a.dtsi
+++ b/dts/upstream/src/arm/rockchip/rk3066a.dtsi
@@ -13,6 +13,11 @@
/ {
compatible = "rockchip,rk3066a";
+ aliases {
+ gpio4 = &gpio4;
+ gpio6 = &gpio6;
+ };
+
cpus {
#address-cells = <1>;
#size-cells = <0>;
diff --git a/dts/upstream/src/arm/rockchip/rk3128-evb.dts b/dts/upstream/src/arm/rockchip/rk3128-evb.dts
index c38f424..c7ab7fc 100644
--- a/dts/upstream/src/arm/rockchip/rk3128-evb.dts
+++ b/dts/upstream/src/arm/rockchip/rk3128-evb.dts
@@ -12,11 +12,6 @@
compatible = "rockchip,rk3128-evb", "rockchip,rk3128";
aliases {
- gpio0 = &gpio0;
- gpio1 = &gpio1;
- gpio2 = &gpio2;
- gpio3 = &gpio3;
- i2c1 = &i2c1;
mmc0 = &emmc;
};
diff --git a/dts/upstream/src/arm/rockchip/rk3128-xpi-3128.dts b/dts/upstream/src/arm/rockchip/rk3128-xpi-3128.dts
new file mode 100644
index 0000000..03a9788
--- /dev/null
+++ b/dts/upstream/src/arm/rockchip/rk3128-xpi-3128.dts
@@ -0,0 +1,425 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+
+/dts-v1/;
+
+#include <dt-bindings/input/input.h>
+#include <dt-bindings/leds/common.h>
+#include "rk3128.dtsi"
+
+/ {
+ model = "Geniatech XPI-3128";
+ compatible = "geniatech,xpi-3128", "rockchip,rk3128";
+
+ aliases {
+ ethernet0 = &gmac;
+ mmc0 = &emmc;
+ mmc1 = &sdmmc;
+ };
+
+ memory@60000000 {
+ device_type = "memory";
+ reg = <0x60000000 0x40000000>;
+ };
+
+ chosen {
+ stdout-path = &uart1;
+ };
+
+ adc-keys {
+ compatible = "adc-keys";
+ io-channels = <&saradc 1>;
+ io-channel-names = "buttons";
+ keyup-threshold-microvolt = <3300000>;
+
+ button-recovery {
+ label = "Recovery";
+ linux,code = <KEY_VENDOR>;
+ press-threshold-microvolt = <0>;
+ };
+ };
+
+ dc_5v: dc-5v-regulator {
+ compatible = "regulator-fixed";
+ regulator-name = "DC_5V";
+ regulator-min-microvolt = <5000000>;
+ regulator-max-microvolt = <5000000>;
+ regulator-always-on;
+ regulator-boot-on;
+ };
+
+ /*
+ * This is a vbus-supply, which also supplies the GL852G usb hub,
+ * thus has to be always-on
+ */
+ host_pwr_5v: host-pwr-5v-regulator {
+ compatible = "regulator-fixed";
+ gpio = <&gpio3 RK_PC4 GPIO_ACTIVE_HIGH>;
+ startup-delay-us = <1500>;
+ regulator-name = "HOST_PWR_5V";
+ regulator-min-microvolt = <5000000>;
+ regulator-max-microvolt = <5000000>;
+ vin-supply = <&dc_5v>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&host_drv>;
+ enable-active-high;
+ regulator-always-on;
+ };
+
+ ir-receiver {
+ compatible = "gpio-ir-receiver";
+ gpios = <&gpio3 RK_PD2 GPIO_ACTIVE_LOW>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&ir_int>;
+ };
+
+ leds {
+ compatible = "gpio-leds";
+
+ led-power {
+ gpios = <&gpio0 RK_PD2 GPIO_ACTIVE_HIGH>;
+ function = LED_FUNCTION_POWER;
+ color = <LED_COLOR_ID_BLUE>;
+ default-state = "on";
+ pinctrl-names = "default";
+ pinctrl-0 = <&power_led>;
+ };
+
+ led-spd {
+ gpios = <&gpio3 RK_PB3 GPIO_ACTIVE_LOW>;
+ function = LED_FUNCTION_LAN;
+ color = <LED_COLOR_ID_GREEN>;
+ /*
+ * currently not allowed to be set as per
+ * https://www.kernel.org/doc/Documentation/devicetree/bindings/leds/common.yaml
+ * and needs to set in userspace:
+ *
+ * linux,default-trigger = "netdev";
+ */
+ pinctrl-names = "default";
+ pinctrl-0 = <&spd_led>;
+ };
+ };
+
+ mcu3v3: mcu3v3-regulator {
+ compatible = "regulator-fixed";
+ regulator-name = "MCU3V3";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ vin-supply = <&vcc_io>;
+ regulator-always-on;
+ regulator-boot-on;
+ };
+
+ vcc_ddr: vcc-ddr-regulator {
+ compatible = "regulator-fixed";
+ regulator-name = "VCC_DDR";
+ regulator-min-microvolt = <1500000>;
+ regulator-max-microvolt = <1500000>;
+ vin-supply = <&vcc_sys>;
+ regulator-always-on;
+ regulator-boot-on;
+ };
+
+ vcc_io: vcc-io-regulator {
+ compatible = "regulator-fixed";
+ regulator-name = "VCC_IO";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ vin-supply = <&vcc_sys>;
+ regulator-always-on;
+ regulator-boot-on;
+ };
+
+ vcc_lan: vcc-lan-regulator {
+ compatible = "regulator-fixed";
+ regulator-name = "VCC_LAN";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ vin-supply = <&vcc_io>;
+ regulator-always-on;
+ regulator-boot-on;
+ };
+
+ vcc_sd: vcc-sd-regulator {
+ compatible = "regulator-fixed";
+ gpio = <&gpio1 RK_PB6 GPIO_ACTIVE_LOW>;
+ startup-delay-us = <500>;
+ regulator-name = "VCC_SD";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ vin-supply = <&vcc_io>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&sdmmc_pwren>;
+ };
+
+ vcc_sys: vcc-sys-regulator {
+ compatible = "regulator-fixed";
+ regulator-name = "VCC_SYS";
+ regulator-min-microvolt = <5000000>;
+ regulator-max-microvolt = <5000000>;
+ vin-supply = <&dc_5v>;
+ regulator-always-on;
+ regulator-boot-on;
+ };
+
+ vcc33_hdmi: vcc33-hdmi-regulator {
+ compatible = "regulator-fixed";
+ regulator-name = "VCC33_HDMI";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ vin-supply = <&vcca_33>;
+ regulator-always-on;
+ regulator-boot-on;
+ };
+
+ vcca_33: vcca-33-regulator {
+ compatible = "regulator-fixed";
+ regulator-name = "VCCA_33";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ vin-supply = <&vcc_sys>;
+ regulator-always-on;
+ regulator-boot-on;
+ };
+
+ vdd_11: vdd-11-regulator {
+ compatible = "regulator-fixed";
+ regulator-name = "VDD_11";
+ regulator-min-microvolt = <1100000>;
+ regulator-max-microvolt = <1100000>;
+ vin-supply = <&vcc_sys>;
+ regulator-always-on;
+ regulator-boot-on;
+ };
+
+ vdd11_hdmi: vdd11-hdmi-regulator {
+ compatible = "regulator-fixed";
+ regulator-name = "VDD11_HDMI";
+ regulator-min-microvolt = <1100000>;
+ regulator-max-microvolt = <1100000>;
+ vin-supply = <&vdd_11>;
+ regulator-always-on;
+ regulator-boot-on;
+ };
+
+ vdd_arm: vdd-arm-regulator {
+ compatible = "pwm-regulator";
+ regulator-name = "VDD_ARM";
+ pwms = <&pwm1 0 25000 1>;
+ pwm-supply = <&vcc_sys>;
+ regulator-min-microvolt = <900000>;
+ regulator-max-microvolt = <1400000>;
+ regulator-always-on;
+ regulator-boot-on;
+ };
+
+ /*
+ * As per schematics vdd_log is minimum 900 mV, maximum 1400 mV.
+ * Since there are HW blocks in PD_LOGIC (which are all driven by
+ * this supply), that either do not have a driver at all or the
+ * driver does not implement regulator support we have to make
+ * sure here that the voltage never drops below 1050 mV.
+ */
+ vdd_log: vdd-log-regulator {
+ compatible = "pwm-regulator";
+ regulator-name = "VDD_LOG";
+ pwms = <&pwm2 0 25000 1>;
+ pwm-dutycycle-range = <30 100>;
+ pwm-supply = <&vcc_sys>;
+ regulator-min-microvolt = <1050000>;
+ regulator-max-microvolt = <1400000>;
+ regulator-ramp-delay = <4000>;
+ regulator-always-on;
+ regulator-boot-on;
+ };
+
+};
+
+&cpu0 {
+ cpu-supply = <&vdd_arm>;
+};
+
+&emmc {
+ bus-width = <8>;
+ vmmc-supply = <&vcc_io>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&emmc_clk &emmc_cmd &emmc_bus8>;
+ cap-mmc-highspeed;
+ mmc-ddr-3_3v;
+ no-sd;
+ no-sdio;
+ status = "okay";
+};
+
+&gmac {
+ clock_in_out = "output";
+ phy-supply = <&vcc_lan>;
+ phy-mode = "rmii";
+ phy-handle = <&phy0>;
+ assigned-clocks = <&cru SCLK_MAC_SRC>;
+ assigned-clock-rates= <50000000>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&rmii_pins>;
+ status = "okay";
+};
+
+&gpio0 {
+ gpio-line-names = /* GPIO0 A0-A7 */
+ "", "", "HEADER_5", "HEADER_3",
+ "", "", "", "",
+ /* GPIO0 B0-B7 */
+ "HEADER_22", "HEADER_23", "", "HEADER_19",
+ "HEADER_26", "HEADER_21", "HEADER_24", "",
+ /* GPIO0 C0-C7 */
+ "", "HEADER_18", "", "",
+ "", "", "", "",
+ /* GPIO0 D0-D7 */
+ "HEADER_36", "", "", "",
+ "", "", "HEADER_13", "";
+};
+
+&gpio1 {
+ gpio-line-names = /* GPIO1 A0-A7 */
+ "HEADER_7", "HEADER_35", "HEADER_33", "HEADER_37",
+ "HEADER_40", "HEADER_38", "", "",
+ /* GPIO1 B0-B7 */
+ "HEADER_11", "", "", "HEADER_29",
+ "HEADER_31", "", "", "",
+ /* GPIO1 C0-C7 */
+ "", "", "", "",
+ "", "", "", "",
+ /* GPIO1 D0-D7 */
+ "", "", "", "",
+ "", "", "", "";
+};
+
+&gpio2 {
+ gpio-line-names = /* GPIO2 A0-A7 */
+ "", "", "", "",
+ "", "", "", "",
+ /* GPIO2 B0-B7 */
+ "", "", "", "",
+ "", "", "", "",
+ /* GPIO2 C0-C7 */
+ "", "", "", "",
+ "HEADER_27", "", "", "",
+ /* GPIO2 D0-D7 */
+ "", "", "HEADER_8", "HEADER_10",
+ "", "", "", "";
+};
+
+&gpio3 {
+ gpio-line-names = /* GPIO3 A0-A7 */
+ "", "", "", "",
+ "", "", "", "",
+ /* GPIO3 B0-B7 */
+ "", "", "", "",
+ "", "", "", "",
+ /* GPIO3 C0-C7 */
+ "", "HEADER_32", "", "",
+ "", "", "", "HEADER_12",
+ /* GPIO3 D0-D7 */
+ "", "", "", "HEADER_15",
+ "", "", "", "";
+};
+
+&gpu {
+ mali-supply = <&vdd_log>;
+ status = "okay";
+};
+
+&mdio {
+ phy0: ethernet-phy@1 {
+ compatible = "ethernet-phy-ieee802.3-c22";
+ reg = <1>;
+ max-speed = <100>;
+ /* T2.2.4 min. 1 us */
+ reset-assert-us = <10>;
+ /* T2.2.1 + T2.2.2 + T2.2.3 min. 6.05 us */
+ reset-deassert-us = <20>;
+ reset-gpios = <&gpio2 RK_PD0 GPIO_ACTIVE_LOW>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&dp83848c_rst>;
+ };
+};
+
+&pinctrl {
+ dp83848c {
+ dp83848c_rst: dp83848c-rst {
+ rockchip,pins = <2 RK_PD0 RK_FUNC_GPIO &pcfg_pull_none>;
+ };
+ };
+
+ ir-receiver {
+ ir_int: ir-int {
+ rockchip,pins = <3 RK_PD2 RK_FUNC_GPIO &pcfg_pull_none>;
+ };
+ };
+
+ leds {
+ power_led: power-led {
+ rockchip,pins = <0 RK_PD2 RK_FUNC_GPIO &pcfg_pull_none>;
+ };
+
+ spd_led: spd-led {
+ rockchip,pins = <3 RK_PB3 RK_FUNC_GPIO &pcfg_pull_none>;
+ };
+ };
+
+ usb2 {
+ host_drv: host-drv {
+ rockchip,pins = <3 RK_PC4 RK_FUNC_GPIO &pcfg_pull_none>;
+ };
+ };
+};
+
+&pwm1 {
+ status = "okay";
+};
+
+&pwm2 {
+ status = "okay";
+};
+
+&saradc {
+ vref-supply = <&vcc_io>;
+ status = "okay";
+};
+
+&sdmmc {
+ bus-width = <4>;
+ vmmc-supply = <&vcc_sd>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&sdmmc_bus4 &sdmmc_clk &sdmmc_cmd &sdmmc_det>;
+ disable-wp;
+ cap-sd-highspeed;
+ no-mmc;
+ no-sdio;
+ status = "okay";
+};
+
+&uart1 {
+ status = "okay";
+};
+
+&usb_host_ehci {
+ status = "okay";
+};
+
+&usb_otg {
+ vusb_a-supply = <&vcc_io>;
+ vusb_d-supply = <&vdd_11>;
+ status = "okay";
+};
+
+&usb2phy {
+ status = "okay";
+};
+
+&usb2phy_host {
+ status = "okay";
+};
+
+&usb2phy_otg {
+ status = "okay";
+};
diff --git a/dts/upstream/src/arm/rockchip/rk3128.dtsi b/dts/upstream/src/arm/rockchip/rk3128.dtsi
index 01edf24..e2264c4 100644
--- a/dts/upstream/src/arm/rockchip/rk3128.dtsi
+++ b/dts/upstream/src/arm/rockchip/rk3128.dtsi
@@ -8,6 +8,7 @@
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/interrupt-controller/irq.h>
#include <dt-bindings/pinctrl/rockchip.h>
+#include <dt-bindings/power/rk3128-power.h>
/ {
compatible = "rockchip,rk3128";
@@ -15,6 +16,20 @@
#address-cells = <1>;
#size-cells = <1>;
+ aliases {
+ gpio0 = &gpio0;
+ gpio1 = &gpio1;
+ gpio2 = &gpio2;
+ gpio3 = &gpio3;
+ i2c0 = &i2c0;
+ i2c1 = &i2c1;
+ i2c2 = &i2c2;
+ i2c3 = &i2c3;
+ serial0 = &uart0;
+ serial1 = &uart1;
+ serial2 = &uart2;
+ };
+
arm-pmu {
compatible = "arm,cortex-a7-pmu";
interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>,
@@ -100,6 +115,27 @@
};
};
+ gpu_opp_table: opp-table-1 {
+ compatible = "operating-points-v2";
+
+ opp-200000000 {
+ opp-hz = /bits/ 64 <200000000>;
+ opp-microvolt = <975000 975000 1250000>;
+ };
+ opp-300000000 {
+ opp-hz = /bits/ 64 <300000000>;
+ opp-microvolt = <1050000 1050000 1250000>;
+ };
+ opp-400000000 {
+ opp-hz = /bits/ 64 <400000000>;
+ opp-microvolt = <1150000 1150000 1250000>;
+ };
+ opp-480000000 {
+ opp-hz = /bits/ 64 <480000000>;
+ opp-microvolt = <1250000 1250000 1250000>;
+ };
+ };
+
timer {
compatible = "arm,armv7-timer";
interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
@@ -130,11 +166,121 @@
};
};
+ gpu: gpu@10090000 {
+ compatible = "rockchip,rk3128-mali", "arm,mali-400";
+ reg = <0x10090000 0x10000>;
+ interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "gp",
+ "gpmmu",
+ "pp0",
+ "ppmmu0",
+ "pp1",
+ "ppmmu1";
+ clocks = <&cru ACLK_GPU>, <&cru ACLK_GPU>;
+ clock-names = "bus", "core";
+ operating-points-v2 = <&gpu_opp_table>;
+ resets = <&cru SRST_GPU>;
+ power-domains = <&power RK3128_PD_GPU>;
+ status = "disabled";
+ };
+
pmu: syscon@100a0000 {
compatible = "rockchip,rk3128-pmu", "syscon", "simple-mfd";
reg = <0x100a0000 0x1000>;
+
+ power: power-controller {
+ compatible = "rockchip,rk3128-power-controller";
+ #power-domain-cells = <1>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ power-domain@RK3128_PD_VIO {
+ reg = <RK3128_PD_VIO>;
+ clocks = <&cru ACLK_CIF>,
+ <&cru HCLK_CIF>,
+ <&cru DCLK_EBC>,
+ <&cru HCLK_EBC>,
+ <&cru ACLK_IEP>,
+ <&cru HCLK_IEP>,
+ <&cru ACLK_LCDC0>,
+ <&cru HCLK_LCDC0>,
+ <&cru PCLK_MIPI>,
+ <&cru ACLK_RGA>,
+ <&cru HCLK_RGA>,
+ <&cru ACLK_VIO0>,
+ <&cru ACLK_VIO1>,
+ <&cru HCLK_VIO>,
+ <&cru HCLK_VIO_H2P>,
+ <&cru DCLK_VOP>,
+ <&cru SCLK_VOP>;
+ pm_qos = <&qos_ebc>,
+ <&qos_iep>,
+ <&qos_lcdc>,
+ <&qos_rga>,
+ <&qos_vip>;
+ #power-domain-cells = <0>;
+ };
+
+ power-domain@RK3128_PD_VIDEO {
+ reg = <RK3128_PD_VIDEO>;
+ clocks = <&cru ACLK_VDPU>,
+ <&cru HCLK_VDPU>,
+ <&cru ACLK_VEPU>,
+ <&cru HCLK_VEPU>,
+ <&cru SCLK_HEVC_CORE>;
+ pm_qos = <&qos_vpu>;
+ #power-domain-cells = <0>;
+ };
+
+ power-domain@RK3128_PD_GPU {
+ reg = <RK3128_PD_GPU>;
+ clocks = <&cru ACLK_GPU>;
+ pm_qos = <&qos_gpu>;
+ #power-domain-cells = <0>;
+ };
+ };
};
+ qos_gpu: qos@1012d000 {
+ compatible = "rockchip,rk3128-qos", "syscon";
+ reg = <0x1012d000 0x20>;
+ };
+
+ qos_vpu: qos@1012e000 {
+ compatible = "rockchip,rk3128-qos", "syscon";
+ reg = <0x1012e000 0x20>;
+ };
+
+ qos_rga: qos@1012f000 {
+ compatible = "rockchip,rk3128-qos", "syscon";
+ reg = <0x1012f000 0x20>;
+ };
+
+ qos_ebc: qos@1012f080 {
+ compatible = "rockchip,rk3128-qos", "syscon";
+ reg = <0x1012f080 0x20>;
+ };
+
+ qos_iep: qos@1012f100 {
+ compatible = "rockchip,rk3128-qos", "syscon";
+ reg = <0x1012f100 0x20>;
+ };
+
+ qos_lcdc: qos@1012f180 {
+ compatible = "rockchip,rk3128-qos", "syscon";
+ reg = <0x1012f180 0x20>;
+ };
+
+ qos_vip: qos@1012f200 {
+ compatible = "rockchip,rk3128-qos", "syscon";
+ reg = <0x1012f200 0x20>;
+ };
+
gic: interrupt-controller@10139000 {
compatible = "arm,cortex-a7-gic";
reg = <0x10139000 0x1000>,
@@ -154,6 +300,9 @@
clocks = <&cru HCLK_OTG>;
clock-names = "otg";
dr_mode = "otg";
+ g-np-tx-fifo-size = <16>;
+ g-rx-fifo-size = <280>;
+ g-tx-fifo-size = <256 128 128 64 32 16>;
phys = <&usb2phy_otg>;
phy-names = "usb2-phy";
status = "disabled";
@@ -163,6 +312,7 @@
compatible = "generic-ehci";
reg = <0x101c0000 0x20000>;
interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cru HCLK_HOST2>;
phys = <&usb2phy_host>;
phy-names = "usb";
status = "disabled";
@@ -172,6 +322,7 @@
compatible = "generic-ohci";
reg = <0x101e0000 0x20000>;
interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cru HCLK_HOST2>;
phys = <&usb2phy_host>;
phy-names = "usb";
status = "disabled";
@@ -261,6 +412,8 @@
clocks = <&cru SCLK_OTGPHY0>;
clock-names = "phyclk";
clock-output-names = "usb480m_phy";
+ assigned-clocks = <&cru SCLK_USB480M>;
+ assigned-clock-parents = <&usb2phy>;
#clock-cells = <0>;
status = "disabled";
@@ -518,6 +671,34 @@
#dma-cells = <1>;
};
+ gmac: ethernet@2008c000 {
+ compatible = "rockchip,rk3128-gmac";
+ reg = <0x2008c000 0x4000>;
+ interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "macirq", "eth_wake_irq";
+ clocks = <&cru SCLK_MAC>,
+ <&cru SCLK_MAC_RX>, <&cru SCLK_MAC_TX>,
+ <&cru SCLK_MAC_REF>, <&cru SCLK_MAC_REFOUT>,
+ <&cru ACLK_GMAC>, <&cru PCLK_GMAC>;
+ clock-names = "stmmaceth",
+ "mac_clk_rx", "mac_clk_tx",
+ "clk_mac_ref", "clk_mac_refout",
+ "aclk_mac", "pclk_mac";
+ resets = <&cru SRST_GMAC>;
+ reset-names = "stmmaceth";
+ rockchip,grf = <&grf>;
+ rx-fifo-depth = <4096>;
+ tx-fifo-depth = <2048>;
+ status = "disabled";
+
+ mdio: mdio {
+ compatible = "snps,dwmac-mdio";
+ #address-cells = <0x1>;
+ #size-cells = <0x0>;
+ };
+ };
+
pinctrl: pinctrl {
compatible = "rockchip,rk3128-pinctrl";
rockchip,grf = <&grf>;
@@ -843,6 +1024,10 @@
rockchip,pins = <1 RK_PB7 1 &pcfg_pull_default>;
};
+ sdmmc_det: sdmmc-det {
+ rockchip,pins = <1 RK_PC1 1 &pcfg_pull_default>;
+ };
+
sdmmc_wp: sdmmc-wp {
rockchip,pins = <1 RK_PA7 1 &pcfg_pull_default>;
};
diff --git a/dts/upstream/src/arm/rockchip/rk322x.dtsi b/dts/upstream/src/arm/rockchip/rk322x.dtsi
index a721744..831561f 100644
--- a/dts/upstream/src/arm/rockchip/rk322x.dtsi
+++ b/dts/upstream/src/arm/rockchip/rk322x.dtsi
@@ -15,6 +15,10 @@
interrupt-parent = <&gic>;
aliases {
+ gpio0 = &gpio0;
+ gpio1 = &gpio1;
+ gpio2 = &gpio2;
+ gpio3 = &gpio3;
serial0 = &uart0;
serial1 = &uart1;
serial2 = &uart2;
diff --git a/dts/upstream/src/arm/rockchip/rk3288.dtsi b/dts/upstream/src/arm/rockchip/rk3288.dtsi
index cb9cdad..ead343d 100644
--- a/dts/upstream/src/arm/rockchip/rk3288.dtsi
+++ b/dts/upstream/src/arm/rockchip/rk3288.dtsi
@@ -19,6 +19,15 @@
aliases {
ethernet0 = &gmac;
+ gpio0 = &gpio0;
+ gpio1 = &gpio1;
+ gpio2 = &gpio2;
+ gpio3 = &gpio3;
+ gpio4 = &gpio4;
+ gpio5 = &gpio5;
+ gpio6 = &gpio6;
+ gpio7 = &gpio7;
+ gpio8 = &gpio8;
i2c0 = &i2c0;
i2c1 = &i2c1;
i2c2 = &i2c2;
diff --git a/dts/upstream/src/arm/rockchip/rk3xxx.dtsi b/dts/upstream/src/arm/rockchip/rk3xxx.dtsi
index cb4e42e..f37137f 100644
--- a/dts/upstream/src/arm/rockchip/rk3xxx.dtsi
+++ b/dts/upstream/src/arm/rockchip/rk3xxx.dtsi
@@ -16,6 +16,10 @@
aliases {
ethernet0 = &emac;
+ gpio0 = &gpio0;
+ gpio1 = &gpio1;
+ gpio2 = &gpio2;
+ gpio3 = &gpio3;
i2c0 = &i2c0;
i2c1 = &i2c1;
i2c2 = &i2c2;
diff --git a/dts/upstream/src/arm/rockchip/rv1108.dtsi b/dts/upstream/src/arm/rockchip/rv1108.dtsi
index abf3006..f3291f3 100644
--- a/dts/upstream/src/arm/rockchip/rv1108.dtsi
+++ b/dts/upstream/src/arm/rockchip/rv1108.dtsi
@@ -196,7 +196,6 @@
pwm4: pwm@10280000 {
compatible = "rockchip,rv1108-pwm", "rockchip,rk3288-pwm";
reg = <0x10280000 0x10>;
- interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cru SCLK_PWM>, <&cru PCLK_PWM>;
clock-names = "pwm", "pclk";
pinctrl-names = "default";
@@ -208,7 +207,6 @@
pwm5: pwm@10280010 {
compatible = "rockchip,rv1108-pwm", "rockchip,rk3288-pwm";
reg = <0x10280010 0x10>;
- interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cru SCLK_PWM>, <&cru PCLK_PWM>;
clock-names = "pwm", "pclk";
pinctrl-names = "default";
@@ -220,7 +218,6 @@
pwm6: pwm@10280020 {
compatible = "rockchip,rv1108-pwm", "rockchip,rk3288-pwm";
reg = <0x10280020 0x10>;
- interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cru SCLK_PWM>, <&cru PCLK_PWM>;
clock-names = "pwm", "pclk";
pinctrl-names = "default";
@@ -232,7 +229,6 @@
pwm7: pwm@10280030 {
compatible = "rockchip,rv1108-pwm", "rockchip,rk3288-pwm";
reg = <0x10280030 0x10>;
- interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cru SCLK_PWM>, <&cru PCLK_PWM>;
clock-names = "pwm", "pclk";
pinctrl-names = "default";
@@ -386,7 +382,6 @@
pwm0: pwm@20040000 {
compatible = "rockchip,rv1108-pwm", "rockchip,rk3288-pwm";
reg = <0x20040000 0x10>;
- interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cru SCLK_PWM0_PMU>, <&cru PCLK_PWM0_PMU>;
clock-names = "pwm", "pclk";
pinctrl-names = "default";
@@ -398,7 +393,6 @@
pwm1: pwm@20040010 {
compatible = "rockchip,rv1108-pwm", "rockchip,rk3288-pwm";
reg = <0x20040010 0x10>;
- interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cru SCLK_PWM0_PMU>, <&cru PCLK_PWM0_PMU>;
clock-names = "pwm", "pclk";
pinctrl-names = "default";
@@ -410,7 +404,6 @@
pwm2: pwm@20040020 {
compatible = "rockchip,rv1108-pwm", "rockchip,rk3288-pwm";
reg = <0x20040020 0x10>;
- interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cru SCLK_PWM0_PMU>, <&cru PCLK_PWM0_PMU>;
clock-names = "pwm", "pclk";
pinctrl-names = "default";
@@ -422,7 +415,6 @@
pwm3: pwm@20040030 {
compatible = "rockchip,rv1108-pwm", "rockchip,rk3288-pwm";
reg = <0x20040030 0x10>;
- interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cru SCLK_PWM0_PMU>, <&cru PCLK_PWM0_PMU>;
clock-names = "pwm", "pclk";
pinctrl-names = "default";
diff --git a/dts/upstream/src/arm/rockchip/rv1109-sonoff-ihost.dts b/dts/upstream/src/arm/rockchip/rv1109-sonoff-ihost.dts
new file mode 100644
index 0000000..45dced8
--- /dev/null
+++ b/dts/upstream/src/arm/rockchip/rv1109-sonoff-ihost.dts
@@ -0,0 +1,21 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (c) 2020 Rockchip Electronics Co., Ltd.
+ */
+
+/dts-v1/;
+#include "rv1109.dtsi"
+#include "rv1126-sonoff-ihost.dtsi"
+
+/ {
+ model = "Sonoff iHost 2G";
+ compatible = "itead,sonoff-ihost", "rockchip,rv1109";
+};
+
+&cpu0 {
+ cpu-supply = <&vdd_arm>;
+};
+
+&cpu1 {
+ cpu-supply = <&vdd_arm>;
+};
diff --git a/dts/upstream/src/arm/rockchip/rv1109.dtsi b/dts/upstream/src/arm/rockchip/rv1109.dtsi
new file mode 100644
index 0000000..9cbaa08
--- /dev/null
+++ b/dts/upstream/src/arm/rockchip/rv1109.dtsi
@@ -0,0 +1,23 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (c) 2019 Fuzhou Rockchip Electronics Co., Ltd.
+ */
+
+/dts-v1/;
+
+#include "rv1126.dtsi"
+
+/ {
+ compatible = "rockchip,rv1109";
+
+ cpus {
+ /delete-node/ cpu@f02;
+ /delete-node/ cpu@f03;
+ };
+
+ arm-pmu {
+ interrupts = <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-affinity = <&cpu0>, <&cpu1>;
+ };
+};
diff --git a/dts/upstream/src/arm/rockchip/rv1126-edgeble-neu2-io.dts b/dts/upstream/src/arm/rockchip/rv1126-edgeble-neu2-io.dts
index f09be84..0c2396b 100644
--- a/dts/upstream/src/arm/rockchip/rv1126-edgeble-neu2-io.dts
+++ b/dts/upstream/src/arm/rockchip/rv1126-edgeble-neu2-io.dts
@@ -61,7 +61,7 @@
phy-mode = "rgmii";
phy-supply = <&vcc_3v3>;
pinctrl-names = "default";
- pinctrl-0 = <&rgmiim1_pins &clk_out_ethernetm1_pins>;
+ pinctrl-0 = <&rgmiim1_miim &rgmiim1_bus2 &rgmiim1_bus4 &clk_out_ethernetm1_pins>;
tx_delay = <0x2a>;
rx_delay = <0x1a>;
status = "okay";
diff --git a/dts/upstream/src/arm/rockchip/rv1126-pinctrl.dtsi b/dts/upstream/src/arm/rockchip/rv1126-pinctrl.dtsi
index bb34b0c..06b1d7f 100644
--- a/dts/upstream/src/arm/rockchip/rv1126-pinctrl.dtsi
+++ b/dts/upstream/src/arm/rockchip/rv1126-pinctrl.dtsi
@@ -87,6 +87,16 @@
<0 RK_PB5 1 &pcfg_pull_none_drv_level_0_smt>;
};
};
+ i2c2 {
+ /omit-if-no-ref/
+ i2c2_xfer: i2c2-xfer {
+ rockchip,pins =
+ /* i2c2_scl */
+ <0 RK_PC2 1 &pcfg_pull_none_drv_level_0_smt>,
+ /* i2c2_sda */
+ <0 RK_PC3 1 &pcfg_pull_none_drv_level_0_smt>;
+ };
+ };
pwm2 {
/omit-if-no-ref/
pwm2m0_pins: pwm2m0-pins {
@@ -105,36 +115,56 @@
};
rgmii {
/omit-if-no-ref/
- rgmiim1_pins: rgmiim1-pins {
+ rgmiim1_miim: rgmiim1-miim {
rockchip,pins =
/* rgmii_mdc_m1 */
<2 RK_PC2 2 &pcfg_pull_none>,
/* rgmii_mdio_m1 */
- <2 RK_PC1 2 &pcfg_pull_none>,
- /* rgmii_rxclk_m1 */
- <2 RK_PD3 2 &pcfg_pull_none>,
+ <2 RK_PC1 2 &pcfg_pull_none>;
+ };
+ /omit-if-no-ref/
+ rgmiim1_rxer: rgmiim1-rxer {
+ rockchip,pins =
+ /* rgmii_rxer_m1 */
+ <2 RK_PC0 2 &pcfg_pull_none>;
+ };
+ /omit-if-no-ref/
+ rgmiim1_bus2: rgmiim1-bus2 {
+ rockchip,pins =
/* rgmii_rxd0_m1 */
<2 RK_PB5 2 &pcfg_pull_none>,
/* rgmii_rxd1_m1 */
<2 RK_PB6 2 &pcfg_pull_none>,
- /* rgmii_rxd2_m1 */
- <2 RK_PC7 2 &pcfg_pull_none>,
- /* rgmii_rxd3_m1 */
- <2 RK_PD0 2 &pcfg_pull_none>,
/* rgmii_rxdv_m1 */
<2 RK_PB4 2 &pcfg_pull_none>,
- /* rgmii_txclk_m1 */
- <2 RK_PD2 2 &pcfg_pull_none_drv_level_3>,
/* rgmii_txd0_m1 */
<2 RK_PC3 2 &pcfg_pull_none_drv_level_3>,
/* rgmii_txd1_m1 */
<2 RK_PC4 2 &pcfg_pull_none_drv_level_3>,
+ /* rgmii_txen_m1 */
+ <2 RK_PC6 2 &pcfg_pull_none_drv_level_3>;
+ };
+ /omit-if-no-ref/
+ rgmiim1_bus4: rgmiim1-bus4 {
+ rockchip,pins =
+ /* rgmii_rxclk_m1 */
+ <2 RK_PD3 2 &pcfg_pull_none>,
+ /* rgmii_rxd2_m1 */
+ <2 RK_PC7 2 &pcfg_pull_none>,
+ /* rgmii_rxd3_m1 */
+ <2 RK_PD0 2 &pcfg_pull_none>,
+ /* rgmii_txclk_m1 */
+ <2 RK_PD2 2 &pcfg_pull_none_drv_level_3>,
/* rgmii_txd2_m1 */
<2 RK_PD1 2 &pcfg_pull_none_drv_level_3>,
/* rgmii_txd3_m1 */
- <2 RK_PA4 2 &pcfg_pull_none_drv_level_3>,
- /* rgmii_txen_m1 */
- <2 RK_PC6 2 &pcfg_pull_none_drv_level_3>;
+ <2 RK_PA4 2 &pcfg_pull_none_drv_level_3>;
+ };
+ /omit-if-no-ref/
+ rgmiim1_mclkinout: rgmiim1-mclkinout {
+ rockchip,pins =
+ /* rgmii_clk_m1 */
+ <2 RK_PB7 2 &pcfg_pull_none>;
};
};
sdmmc0 {
@@ -263,6 +293,14 @@
/* uart3_tx_m0 */
<3 RK_PC6 4 &pcfg_pull_up>;
};
+ /omit-if-no-ref/
+ uart3m2_xfer: uart3m2-xfer {
+ rockchip,pins =
+ /* uart3_rx_m2 */
+ <3 RK_PA1 4 &pcfg_pull_up>,
+ /* uart3_tx_m2 */
+ <3 RK_PA0 4 &pcfg_pull_up>;
+ };
};
uart4 {
/omit-if-no-ref/
@@ -273,6 +311,14 @@
/* uart4_tx_m0 */
<3 RK_PA4 4 &pcfg_pull_up>;
};
+ /omit-if-no-ref/
+ uart4m2_xfer: uart4m2-xfer {
+ rockchip,pins =
+ /* uart4_rx_m2 */
+ <1 RK_PD4 3 &pcfg_pull_up>,
+ /* uart4_tx_m2 */
+ <1 RK_PD5 3 &pcfg_pull_up>;
+ };
};
uart5 {
/omit-if-no-ref/
diff --git a/dts/upstream/src/arm/rockchip/rv1126-sonoff-ihost.dts b/dts/upstream/src/arm/rockchip/rv1126-sonoff-ihost.dts
new file mode 100644
index 0000000..77386a4
--- /dev/null
+++ b/dts/upstream/src/arm/rockchip/rv1126-sonoff-ihost.dts
@@ -0,0 +1,29 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (c) 2020 Rockchip Electronics Co., Ltd.
+ */
+
+/dts-v1/;
+#include "rv1126.dtsi"
+#include "rv1126-sonoff-ihost.dtsi"
+
+/ {
+ model = "Sonoff iHost 4G";
+ compatible = "itead,sonoff-ihost", "rockchip,rv1126";
+};
+
+&cpu0 {
+ cpu-supply = <&vdd_arm>;
+};
+
+&cpu1 {
+ cpu-supply = <&vdd_arm>;
+};
+
+&cpu2 {
+ cpu-supply = <&vdd_arm>;
+};
+
+&cpu3 {
+ cpu-supply = <&vdd_arm>;
+};
diff --git a/dts/upstream/src/arm/rockchip/rv1126-sonoff-ihost.dtsi b/dts/upstream/src/arm/rockchip/rv1126-sonoff-ihost.dtsi
new file mode 100644
index 0000000..32b329e
--- /dev/null
+++ b/dts/upstream/src/arm/rockchip/rv1126-sonoff-ihost.dtsi
@@ -0,0 +1,404 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (c) 2020 Rockchip Electronics Co., Ltd.
+ * Copyright (c) 2022 Edgeble AI Technologies Pvt. Ltd.
+ */
+
+/ {
+ aliases {
+ ethernet0 = &gmac;
+ mmc0 = &emmc;
+ };
+
+ chosen {
+ stdout-path = "serial2:1500000n8";
+ };
+
+ vcc5v0_sys: regulator-vcc5v0-sys {
+ compatible = "regulator-fixed";
+ regulator-name = "vcc5v0_sys";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <5000000>;
+ regulator-max-microvolt = <5000000>;
+ };
+
+ sdio_pwrseq: pwrseq-sdio {
+ compatible = "mmc-pwrseq-simple";
+ clocks = <&rk809 1>;
+ clock-names = "ext_clock";
+ pinctrl-names = "default";
+ pinctrl-0 = <&wifi_enable_h>;
+ reset-gpios = <&gpio1 RK_PD0 GPIO_ACTIVE_LOW>;
+ };
+};
+
+&emmc {
+ bus-width = <8>;
+ cap-mmc-highspeed;
+ mmc-hs200-1_8v;
+ non-removable;
+ pinctrl-names = "default";
+ pinctrl-0 = <&emmc_bus8 &emmc_cmd &emmc_clk &emmc_rstnout>;
+ rockchip,default-sample-phase = <90>;
+ vmmc-supply = <&vcc_3v3>;
+ vqmmc-supply = <&vcc_1v8>;
+ status = "okay";
+};
+
+&i2c0 {
+ clock-frequency = <400000>;
+ status = "okay";
+
+ rk809: pmic@20 {
+ compatible = "rockchip,rk809";
+ reg = <0x20>;
+ interrupt-parent = <&gpio0>;
+ interrupts = <RK_PB1 IRQ_TYPE_LEVEL_LOW>;
+ #clock-cells = <1>;
+ clock-output-names = "rk808-clkout1", "rk808-clkout2";
+ pinctrl-names = "default";
+ pinctrl-0 = <&pmic_int_l>;
+ rockchip,system-power-controller;
+ wakeup-source;
+
+ vcc1-supply = <&vcc5v0_sys>;
+ vcc2-supply = <&vcc5v0_sys>;
+ vcc3-supply = <&vcc5v0_sys>;
+ vcc4-supply = <&vcc5v0_sys>;
+ vcc5-supply = <&vcc_buck5>;
+ vcc6-supply = <&vcc_buck5>;
+ vcc7-supply = <&vcc5v0_sys>;
+ vcc8-supply = <&vcc3v3_sys>;
+ vcc9-supply = <&vcc5v0_sys>;
+
+ regulators {
+ vdd_npu_vepu: DCDC_REG1 {
+ regulator-name = "vdd_npu_vepu";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-initial-mode = <0x2>;
+ regulator-min-microvolt = <650000>;
+ regulator-max-microvolt = <950000>;
+ regulator-ramp-delay = <6001>;
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ };
+ };
+
+ vdd_arm: DCDC_REG2 {
+ regulator-name = "vdd_arm";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-initial-mode = <0x2>;
+ regulator-min-microvolt = <725000>;
+ regulator-max-microvolt = <1350000>;
+ regulator-ramp-delay = <6001>;
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ };
+ };
+
+ vcc_ddr: DCDC_REG3 {
+ regulator-name = "vcc_ddr";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-initial-mode = <0x2>;
+ regulator-state-mem {
+ regulator-on-in-suspend;
+ };
+ };
+
+ vcc3v3_sys: DCDC_REG4 {
+ regulator-name = "vcc3v3_sys";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-initial-mode = <0x2>;
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-state-mem {
+ regulator-on-in-suspend;
+ regulator-suspend-microvolt = <3300000>;
+ };
+ };
+
+ vcc_buck5: DCDC_REG5 {
+ regulator-name = "vcc_buck5";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <2200000>;
+ regulator-max-microvolt = <2200000>;
+ regulator-state-mem {
+ regulator-on-in-suspend;
+ regulator-suspend-microvolt = <2200000>;
+ };
+ };
+
+ vcc_0v8: LDO_REG1 {
+ regulator-name = "vcc_0v8";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <800000>;
+ regulator-max-microvolt = <800000>;
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ };
+ };
+
+ vcc1v8_pmu: LDO_REG2 {
+ regulator-name = "vcc1v8_pmu";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-state-mem {
+ regulator-on-in-suspend;
+ regulator-suspend-microvolt = <1800000>;
+ };
+ };
+
+ vdd0v8_pmu: LDO_REG3 {
+ regulator-name = "vcc0v8_pmu";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <800000>;
+ regulator-max-microvolt = <800000>;
+ regulator-state-mem {
+ regulator-on-in-suspend;
+ regulator-suspend-microvolt = <800000>;
+ };
+ };
+
+ vcc_1v8: LDO_REG4 {
+ regulator-name = "vcc_1v8";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-state-mem {
+ regulator-on-in-suspend;
+ regulator-suspend-microvolt = <1800000>;
+ };
+ };
+
+ vcc_dovdd: LDO_REG5 {
+ regulator-name = "vcc_dovdd";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ };
+ };
+
+ vcc_dvdd: LDO_REG6 {
+ regulator-name = "vcc_dvdd";
+ regulator-min-microvolt = <1200000>;
+ regulator-max-microvolt = <1200000>;
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ };
+ };
+
+ vcc_avdd: LDO_REG7 {
+ regulator-name = "vcc_avdd";
+ regulator-min-microvolt = <2800000>;
+ regulator-max-microvolt = <2800000>;
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ };
+ };
+
+ vccio_sd: LDO_REG8 {
+ regulator-name = "vccio_sd";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ };
+ };
+
+ vcc3v3_sd: LDO_REG9 {
+ regulator-name = "vcc3v3_sd";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ };
+ };
+
+ vcc_5v0: SWITCH_REG1 {
+ regulator-name = "vcc_5v0";
+ };
+
+ vcc_3v3: SWITCH_REG2 {
+ regulator-name = "vcc_3v3";
+ regulator-always-on;
+ regulator-boot-on;
+ };
+ };
+ };
+};
+
+&i2c2 {
+ status = "okay";
+ clock-frequency = <400000>;
+
+ pcf8563: rtc@51 {
+ compatible = "nxp,pcf8563";
+ reg = <0x51>;
+ #clock-cells = <0>;
+ interrupt-parent = <&gpio0>;
+ interrupts = <RK_PA2 IRQ_TYPE_LEVEL_LOW>;
+ clock-output-names = "xin32k";
+ };
+};
+
+&gmac {
+ assigned-clocks = <&cru CLK_GMAC_SRC_M1>, <&cru CLK_GMAC_SRC>,
+ <&cru CLK_GMAC_TX_RX>;
+ assigned-clock-parents = <&cru CLK_GMAC_RGMII_M1>, <&cru CLK_GMAC_SRC_M1>,
+ <&cru RMII_MODE_CLK>;
+ assigned-clock-rates = <0>, <50000000>;
+ clock_in_out = "output";
+ phy-handle = <&phy>;
+ phy-mode = "rmii";
+ phy-supply = <&vcc_3v3>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&rgmiim1_miim &rgmiim1_rxer &rgmiim1_bus2 &rgmiim1_mclkinout>;
+ status = "okay";
+};
+
+&mdio {
+ phy: ethernet-phy@0 {
+ compatible = "ethernet-phy-ieee802.3-c22";
+ reg = <0x0>;
+ pinctrl-names = "default";
+ pinctrl-0 = <ð_phy_rst>;
+ reset-active-low;
+ reset-assert-us = <50000>;
+ reset-deassert-us = <10000>;
+ reset-gpios = <&gpio2 RK_PA6 GPIO_ACTIVE_LOW>;
+ };
+};
+
+&pinctrl {
+ ethernet {
+ eth_phy_rst: eth-phy-rst {
+ rockchip,pins = <2 RK_PA6 RK_FUNC_GPIO &pcfg_pull_down>;
+ };
+ };
+ bt {
+ bt_enable: bt-enable {
+ rockchip,pins = <1 RK_PC6 RK_FUNC_GPIO &pcfg_pull_none>;
+ };
+
+ bt_wake_dev: bt-wake-dev {
+ rockchip,pins = <1 RK_PC7 RK_FUNC_GPIO &pcfg_pull_none>;
+ };
+
+ bt_wake_host: bt-wake-host {
+ rockchip,pins = <1 RK_PC5 RK_FUNC_GPIO &pcfg_pull_none>;
+ };
+ };
+
+ pmic {
+ pmic_int_l: pmic-int-l {
+ rockchip,pins = <0 RK_PB1 RK_FUNC_GPIO &pcfg_pull_up>;
+ };
+ };
+
+ wifi {
+ wifi_enable_h: wifi-enable-h {
+ rockchip,pins = <1 RK_PD0 RK_FUNC_GPIO &pcfg_pull_none>;
+ };
+ };
+};
+
+&pmu_io_domains {
+ pmuio0-supply = <&vcc1v8_pmu>;
+ pmuio1-supply = <&vcc3v3_sys>;
+ vccio1-supply = <&vcc_1v8>;
+ vccio2-supply = <&vccio_sd>;
+ vccio3-supply = <&vcc_1v8>;
+ vccio4-supply = <&vcc_dovdd>;
+ vccio5-supply = <&vcc_1v8>;
+ vccio6-supply = <&vcc_1v8>;
+ vccio7-supply = <&vcc_dovdd>;
+ status = "okay";
+};
+
+&saradc {
+ vref-supply = <&vcc_1v8>;
+ status = "okay";
+};
+
+&sdio {
+ bus-width = <4>;
+ cap-sd-highspeed;
+ cap-sdio-irq;
+ keep-power-in-suspend;
+ max-frequency = <100000000>;
+ mmc-pwrseq = <&sdio_pwrseq>;
+ non-removable;
+ pinctrl-names = "default";
+ pinctrl-0 = <&sdmmc1_clk &sdmmc1_cmd &sdmmc1_bus4>;
+ rockchip,default-sample-phase = <90>;
+ sd-uhs-sdr104;
+ vmmc-supply = <&vcc3v3_sys>;
+ vqmmc-supply = <&vcc_1v8>;
+ status = "okay";
+};
+
+&sdmmc {
+ bus-width = <4>;
+ cap-mmc-highspeed;
+ cap-sd-highspeed;
+ card-detect-delay = <200>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&sdmmc0_clk &sdmmc0_cmd &sdmmc0_bus4 &sdmmc0_det>;
+ rockchip,default-sample-phase = <90>;
+ sd-uhs-sdr12;
+ sd-uhs-sdr25;
+ sd-uhs-sdr104;
+ vqmmc-supply = <&vccio_sd>;
+ status = "okay";
+};
+
+&uart0 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&uart0_xfer &uart0_ctsn &uart0_rtsn>;
+ uart-has-rtscts;
+ status = "okay";
+
+ bluetooth {
+ compatible = "realtek,rtl8723ds-bt";
+ device-wake-gpios = <&gpio1 RK_PC7 GPIO_ACTIVE_HIGH>; /* BT_WAKE */
+ enable-gpios = <&gpio1 RK_PC6 GPIO_ACTIVE_HIGH>; /* BT_RST */
+ host-wake-gpios = <&gpio1 RK_PC5 GPIO_ACTIVE_HIGH>; /* BT_WAKE_HOST */
+ max-speed = <2000000>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&bt_enable>, <&bt_wake_dev>, <&bt_wake_host>;
+ };
+};
+
+&uart2 {
+ status = "okay";
+};
+
+&uart3 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&uart3m2_xfer>;
+ status = "okay";
+};
+
+&uart4 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&uart4m2_xfer>;
+ status = "okay";
+};
diff --git a/dts/upstream/src/arm/rockchip/rv1126.dtsi b/dts/upstream/src/arm/rockchip/rv1126.dtsi
index 9ccd1ba..bb603ca 100644
--- a/dts/upstream/src/arm/rockchip/rv1126.dtsi
+++ b/dts/upstream/src/arm/rockchip/rv1126.dtsi
@@ -21,6 +21,13 @@
aliases {
i2c0 = &i2c0;
+ i2c2 = &i2c2;
+ serial0 = &uart0;
+ serial1 = &uart1;
+ serial2 = &uart2;
+ serial3 = &uart3;
+ serial4 = &uart4;
+ serial5 = &uart5;
};
cpus {
@@ -231,6 +238,20 @@
status = "disabled";
};
+ i2c2: i2c@ff400000 {
+ compatible = "rockchip,rv1126-i2c", "rockchip,rk3399-i2c";
+ reg = <0xff400000 0x1000>;
+ interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
+ rockchip,grf = <&pmugrf>;
+ clocks = <&pmucru CLK_I2C2>, <&pmucru PCLK_I2C2>;
+ clock-names = "i2c", "pclk";
+ pinctrl-names = "default";
+ pinctrl-0 = <&i2c2_xfer>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+ };
+
uart1: serial@ff410000 {
compatible = "rockchip,rv1126-uart", "snps,dw-apb-uart";
reg = <0xff410000 0x100>;
diff --git a/dts/upstream/src/arm/samsung/exynos4.dtsi b/dts/upstream/src/arm/samsung/exynos4.dtsi
index f775b93..7f981b5 100644
--- a/dts/upstream/src/arm/samsung/exynos4.dtsi
+++ b/dts/upstream/src/arm/samsung/exynos4.dtsi
@@ -203,16 +203,16 @@
camera: camera@11800000 {
compatible = "samsung,fimc";
+ ranges = <0x0 0x11800000 0xa0000>;
status = "disabled";
#address-cells = <1>;
#size-cells = <1>;
#clock-cells = <1>;
clock-output-names = "cam_a_clkout", "cam_b_clkout";
- ranges;
- fimc_0: fimc@11800000 {
+ fimc_0: fimc@0 {
compatible = "samsung,exynos4210-fimc";
- reg = <0x11800000 0x1000>;
+ reg = <0x0 0x1000>;
interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clock CLK_FIMC0>,
<&clock CLK_SCLK_FIMC0>;
@@ -223,9 +223,9 @@
status = "disabled";
};
- fimc_1: fimc@11810000 {
+ fimc_1: fimc@10000 {
compatible = "samsung,exynos4210-fimc";
- reg = <0x11810000 0x1000>;
+ reg = <0x00010000 0x1000>;
interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clock CLK_FIMC1>,
<&clock CLK_SCLK_FIMC1>;
@@ -236,9 +236,9 @@
status = "disabled";
};
- fimc_2: fimc@11820000 {
+ fimc_2: fimc@20000 {
compatible = "samsung,exynos4210-fimc";
- reg = <0x11820000 0x1000>;
+ reg = <0x00020000 0x1000>;
interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clock CLK_FIMC2>,
<&clock CLK_SCLK_FIMC2>;
@@ -249,9 +249,9 @@
status = "disabled";
};
- fimc_3: fimc@11830000 {
+ fimc_3: fimc@30000 {
compatible = "samsung,exynos4210-fimc";
- reg = <0x11830000 0x1000>;
+ reg = <0x00030000 0x1000>;
interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clock CLK_FIMC3>,
<&clock CLK_SCLK_FIMC3>;
@@ -262,9 +262,9 @@
status = "disabled";
};
- csis_0: csis@11880000 {
+ csis_0: csis@80000 {
compatible = "samsung,exynos4210-csis";
- reg = <0x11880000 0x4000>;
+ reg = <0x00080000 0x4000>;
interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clock CLK_CSIS0>,
<&clock CLK_SCLK_CSIS0>;
@@ -278,9 +278,9 @@
#size-cells = <0>;
};
- csis_1: csis@11890000 {
+ csis_1: csis@90000 {
compatible = "samsung,exynos4210-csis";
- reg = <0x11890000 0x4000>;
+ reg = <0x00090000 0x4000>;
interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clock CLK_CSIS1>,
<&clock CLK_SCLK_CSIS1>;
diff --git a/dts/upstream/src/arm/samsung/exynos4210-i9100.dts b/dts/upstream/src/arm/samsung/exynos4210-i9100.dts
index a9ec1f6..0d84957 100644
--- a/dts/upstream/src/arm/samsung/exynos4210-i9100.dts
+++ b/dts/upstream/src/arm/samsung/exynos4210-i9100.dts
@@ -184,6 +184,28 @@
};
};
+ i2c-gpio-2 {
+ compatible = "i2c-gpio";
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ sda-gpios = <&gpk1 2 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
+ scl-gpios = <&gpk1 0 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
+ i2c-gpio,delay-us = <2>;
+
+ touchscreen@20 {
+ compatible = "cypress,aries-touchkey";
+ reg = <0x20>;
+
+ interrupt-parent = <&gpl0>;
+ interrupts = <5 IRQ_TYPE_EDGE_FALLING>;
+
+ vdd-supply = <&vtouchled_reg>;
+ vcc-supply = <&vtouch_reg>;
+ linux,keycodes = <KEY_MENU>, <KEY_BACK>;
+ };
+ };
+
spi-3 {
compatible = "spi-gpio";
#address-cells = <1>;
@@ -380,6 +402,23 @@
vusb_a-supply = <&vusbdac_reg>;
};
+&i2c_1 {
+ status = "okay";
+
+ samsung,i2c-sda-delay = <100>;
+ samsung,i2c-slave-addr = <0x10>;
+ samsung,i2c-max-bus-freq = <100000>;
+
+ lis3dh: accelerometer@19 {
+ compatible = "st,lis3dh-accel";
+ reg = <0x19>;
+
+ mount-matrix = "0", "-1", "0",
+ "1", "0", "0",
+ "0", "0", "1";
+ };
+};
+
&i2c_3 {
status = "okay";
@@ -513,7 +552,6 @@
regulator-name = "TOUCH_2.8V";
regulator-min-microvolt = <2800000>;
regulator-max-microvolt = <2800000>;
- regulator-always-on;
};
vpll_reg: LDO10 {
@@ -527,6 +565,14 @@
regulator-name = "VT_CAM_1.8V";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
+
+ /*
+ * Force-enable this regulator; otherwise the
+ * kernel hangs very early in the boot process
+ * for about 12 seconds, without apparent
+ * reason.
+ */
+ regulator-always-on;
};
vcclcd_reg: LDO13 {
diff --git a/dts/upstream/src/arm/samsung/exynos4212-tab3.dtsi b/dts/upstream/src/arm/samsung/exynos4212-tab3.dtsi
index d7954ff..e5254e3 100644
--- a/dts/upstream/src/arm/samsung/exynos4212-tab3.dtsi
+++ b/dts/upstream/src/arm/samsung/exynos4212-tab3.dtsi
@@ -434,6 +434,7 @@
};
&fimd {
+ samsung,invert-vclk;
status = "okay";
};
diff --git a/dts/upstream/src/arm/samsung/exynos4x12.dtsi b/dts/upstream/src/arm/samsung/exynos4x12.dtsi
index 84c1db2..b4b5e76 100644
--- a/dts/upstream/src/arm/samsung/exynos4x12.dtsi
+++ b/dts/upstream/src/arm/samsung/exynos4x12.dtsi
@@ -451,14 +451,15 @@
};
&camera {
+ ranges = <0x0 0x11800000 0xba1000>;
clocks = <&clock CLK_SCLK_CAM0>, <&clock CLK_SCLK_CAM1>,
<&clock CLK_PIXELASYNCM0>, <&clock CLK_PIXELASYNCM1>;
clock-names = "sclk_cam0", "sclk_cam1", "pxl_async0", "pxl_async1";
/* fimc_[0-3] are configured outside, under phandles */
- fimc_lite_0: fimc-lite@12390000 {
+ fimc_lite_0: fimc-lite@b90000 {
compatible = "samsung,exynos4212-fimc-lite";
- reg = <0x12390000 0x1000>;
+ reg = <0x00b90000 0x1000>;
interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>;
power-domains = <&pd_isp>;
clocks = <&isp_clock CLK_ISP_FIMC_LITE0>;
@@ -467,9 +468,9 @@
status = "disabled";
};
- fimc_lite_1: fimc-lite@123a0000 {
+ fimc_lite_1: fimc-lite@ba0000 {
compatible = "samsung,exynos4212-fimc-lite";
- reg = <0x123a0000 0x1000>;
+ reg = <0x00ba0000 0x1000>;
interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>;
power-domains = <&pd_isp>;
clocks = <&isp_clock CLK_ISP_FIMC_LITE1>;
@@ -478,9 +479,9 @@
status = "disabled";
};
- fimc_is: fimc-is@12000000 {
+ fimc_is: fimc-is@800000 {
compatible = "samsung,exynos4212-fimc-is";
- reg = <0x12000000 0x260000>;
+ reg = <0x00800000 0x260000>;
interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>;
power-domains = <&pd_isp>;
@@ -516,18 +517,15 @@
iommus = <&sysmmu_fimc_isp>, <&sysmmu_fimc_drc>,
<&sysmmu_fimc_fd>, <&sysmmu_fimc_mcuctl>;
iommu-names = "isp", "drc", "fd", "mcuctl";
+ samsung,pmu-syscon = <&pmu_system_controller>;
#address-cells = <1>;
#size-cells = <1>;
ranges;
status = "disabled";
- pmu@10020000 {
- reg = <0x10020000 0x3000>;
- };
-
- i2c1_isp: i2c-isp@12140000 {
+ i2c1_isp: i2c-isp@940000 {
compatible = "samsung,exynos4212-i2c-isp";
- reg = <0x12140000 0x100>;
+ reg = <0x00940000 0x100>;
clocks = <&isp_clock CLK_ISP_I2C1_ISP>;
clock-names = "i2c_isp";
#address-cells = <1>;
diff --git a/dts/upstream/src/arm/samsung/s5pv210.dtsi b/dts/upstream/src/arm/samsung/s5pv210.dtsi
index f7de5b5..ed560c9 100644
--- a/dts/upstream/src/arm/samsung/s5pv210.dtsi
+++ b/dts/upstream/src/arm/samsung/s5pv210.dtsi
@@ -549,17 +549,17 @@
camera: camera@fa600000 {
compatible = "samsung,fimc";
+ ranges = <0x0 0xfa600000 0xe01000>;
clocks = <&clocks SCLK_CAM0>, <&clocks SCLK_CAM1>;
clock-names = "sclk_cam0", "sclk_cam1";
#address-cells = <1>;
#size-cells = <1>;
#clock-cells = <1>;
clock-output-names = "cam_a_clkout", "cam_b_clkout";
- ranges;
- csis0: csis@fa600000 {
+ csis0: csis@0 {
compatible = "samsung,s5pv210-csis";
- reg = <0xfa600000 0x4000>;
+ reg = <0x00000000 0x4000>;
interrupt-parent = <&vic2>;
interrupts = <29>;
clocks = <&clocks CLK_CSIS>,
@@ -572,9 +572,9 @@
#size-cells = <0>;
};
- fimc0: fimc@fb200000 {
+ fimc0: fimc@c00000 {
compatible = "samsung,s5pv210-fimc";
- reg = <0xfb200000 0x1000>;
+ reg = <0x00c00000 0x1000>;
interrupts = <5>;
interrupt-parent = <&vic2>;
clocks = <&clocks CLK_FIMC0>,
@@ -586,9 +586,9 @@
samsung,cam-if;
};
- fimc1: fimc@fb300000 {
+ fimc1: fimc@d00000 {
compatible = "samsung,s5pv210-fimc";
- reg = <0xfb300000 0x1000>;
+ reg = <0x00d00000 0x1000>;
interrupt-parent = <&vic2>;
interrupts = <6>;
clocks = <&clocks CLK_FIMC1>,
@@ -602,9 +602,9 @@
samsung,lcd-wb;
};
- fimc2: fimc@fb400000 {
+ fimc2: fimc@e00000 {
compatible = "samsung,s5pv210-fimc";
- reg = <0xfb400000 0x1000>;
+ reg = <0x00e00000 0x1000>;
interrupt-parent = <&vic2>;
interrupts = <7>;
clocks = <&clocks CLK_FIMC2>,
diff --git a/dts/upstream/src/arm/st/ste-dbx5x0.dtsi b/dts/upstream/src/arm/st/ste-dbx5x0.dtsi
index d5d8877..0f87abe 100644
--- a/dts/upstream/src/arm/st/ste-dbx5x0.dtsi
+++ b/dts/upstream/src/arm/st/ste-dbx5x0.dtsi
@@ -425,7 +425,7 @@
gpio0: gpio@8012e000 {
compatible = "stericsson,db8500-gpio",
"st,nomadik-gpio";
- reg = <0x8012e000 0x80>;
+ reg = <0x8012e000 0x80>;
interrupts = <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>;
interrupt-controller;
#interrupt-cells = <2>;
@@ -440,7 +440,7 @@
gpio1: gpio@8012e080 {
compatible = "stericsson,db8500-gpio",
"st,nomadik-gpio";
- reg = <0x8012e080 0x80>;
+ reg = <0x8012e080 0x80>;
interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>;
interrupt-controller;
#interrupt-cells = <2>;
@@ -455,7 +455,7 @@
gpio2: gpio@8000e000 {
compatible = "stericsson,db8500-gpio",
"st,nomadik-gpio";
- reg = <0x8000e000 0x80>;
+ reg = <0x8000e000 0x80>;
interrupts = <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>;
interrupt-controller;
#interrupt-cells = <2>;
@@ -470,7 +470,7 @@
gpio3: gpio@8000e080 {
compatible = "stericsson,db8500-gpio",
"st,nomadik-gpio";
- reg = <0x8000e080 0x80>;
+ reg = <0x8000e080 0x80>;
interrupts = <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>;
interrupt-controller;
#interrupt-cells = <2>;
@@ -485,7 +485,7 @@
gpio4: gpio@8000e100 {
compatible = "stericsson,db8500-gpio",
"st,nomadik-gpio";
- reg = <0x8000e100 0x80>;
+ reg = <0x8000e100 0x80>;
interrupts = <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>;
interrupt-controller;
#interrupt-cells = <2>;
@@ -500,7 +500,7 @@
gpio5: gpio@8000e180 {
compatible = "stericsson,db8500-gpio",
"st,nomadik-gpio";
- reg = <0x8000e180 0x80>;
+ reg = <0x8000e180 0x80>;
interrupts = <GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>;
interrupt-controller;
#interrupt-cells = <2>;
@@ -515,7 +515,7 @@
gpio6: gpio@8011e000 {
compatible = "stericsson,db8500-gpio",
"st,nomadik-gpio";
- reg = <0x8011e000 0x80>;
+ reg = <0x8011e000 0x80>;
interrupts = <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>;
interrupt-controller;
#interrupt-cells = <2>;
@@ -530,7 +530,7 @@
gpio7: gpio@8011e080 {
compatible = "stericsson,db8500-gpio",
"st,nomadik-gpio";
- reg = <0x8011e080 0x80>;
+ reg = <0x8011e080 0x80>;
interrupts = <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>;
interrupt-controller;
#interrupt-cells = <2>;
@@ -545,7 +545,7 @@
gpio8: gpio@a03fe000 {
compatible = "stericsson,db8500-gpio",
"st,nomadik-gpio";
- reg = <0xa03fe000 0x80>;
+ reg = <0xa03fe000 0x80>;
interrupts = <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>;
interrupt-controller;
#interrupt-cells = <2>;
diff --git a/dts/upstream/src/arm/st/ste-href-ab8500.dtsi b/dts/upstream/src/arm/st/ste-href-ab8500.dtsi
index e1de9d3..5eeb44c 100644
--- a/dts/upstream/src/arm/st/ste-href-ab8500.dtsi
+++ b/dts/upstream/src/arm/st/ste-href-ab8500.dtsi
@@ -9,6 +9,54 @@
soc {
prcmu@80157000 {
ab8500 {
+ phy {
+ pinctrl-names = "default", "sleep";
+ pinctrl-0 = <&usb_a_1_default>;
+ pinctrl-1 = <&usb_a_1_sleep>;
+ };
+
+ regulator {
+ ab8500_ldo_aux1_reg: ab8500_ldo_aux1 {
+ regulator-name = "V-DISPLAY";
+ };
+
+ ab8500_ldo_aux2_reg: ab8500_ldo_aux2 {
+ regulator-name = "V-eMMC1";
+ };
+
+ ab8500_ldo_aux3_reg: ab8500_ldo_aux3 {
+ regulator-name = "V-MMC-SD";
+ };
+
+ ab8500_ldo_intcore_reg: ab8500_ldo_intcore {
+ regulator-name = "V-INTCORE";
+ };
+
+ ab8500_ldo_tvout_reg: ab8500_ldo_tvout {
+ regulator-name = "V-TVOUT";
+ };
+
+ ab8500_ldo_audio_reg: ab8500_ldo_audio {
+ regulator-name = "V-AUD";
+ };
+
+ ab8500_ldo_anamic1_reg: ab8500_ldo_anamic1 {
+ regulator-name = "V-AMIC1";
+ };
+
+ ab8500_ldo_anamic2_reg: ab8500_ldo_anamic2 {
+ regulator-name = "V-AMIC2";
+ };
+
+ ab8500_ldo_dmic_reg: ab8500_ldo_dmic {
+ regulator-name = "V-DMIC";
+ };
+
+ ab8500_ldo_ana_reg: ab8500_ldo_ana {
+ regulator-name = "V-CSI/DSI";
+ };
+ };
+
gpio {
/* Hog a few default settings */
pinctrl-names = "default";
diff --git a/dts/upstream/src/arm/st/ste-href-ab8505.dtsi b/dts/upstream/src/arm/st/ste-href-ab8505.dtsi
new file mode 100644
index 0000000..268db68
--- /dev/null
+++ b/dts/upstream/src/arm/st/ste-href-ab8505.dtsi
@@ -0,0 +1,490 @@
+// SPDX-License-Identifier: GPL-2.0-or-later
+/*
+ * Copyright 2023 Linus Walleij <linus.walleij@linaro.org>
+ */
+
+#include "ste-ab8505.dtsi"
+
+/ {
+ soc {
+ prcmu@80157000 {
+ ab8505 {
+ phy {
+ pinctrl-names = "default", "sleep";
+ pinctrl-0 = <&usb_a_1_default>;
+ pinctrl-1 = <&usb_a_1_sleep>;
+ };
+
+ regulator {
+ ab8500_ldo_aux1_reg: ab8500_ldo_aux1 {
+ regulator-name = "V-DISPLAY";
+ };
+
+ ab8500_ldo_aux2_reg: ab8500_ldo_aux2 {
+ regulator-name = "V-eMMC1";
+ };
+
+ ab8500_ldo_aux3_reg: ab8500_ldo_aux3 {
+ regulator-name = "V-MMC-SD";
+ };
+
+ ab8500_ldo_intcore_reg: ab8500_ldo_intcore {
+ regulator-name = "V-INTCORE";
+ };
+
+ ab8500_ldo_tvout_reg: ab8500_ldo_tvout {
+ regulator-name = "V-TVOUT";
+ };
+
+ ab8500_ldo_audio_reg: ab8500_ldo_audio {
+ regulator-name = "V-AUD";
+ };
+
+ ab8500_ldo_anamic1_reg: ab8500_ldo_anamic1 {
+ regulator-name = "V-AMIC1";
+ };
+
+ ab8500_ldo_anamic2_reg: ab8500_ldo_anamic2 {
+ regulator-name = "V-AMIC2";
+ };
+
+ ab8500_ldo_dmic_reg: ab8500_ldo_dmic {
+ regulator-name = "V-DMIC";
+ };
+
+ ab8500_ldo_ana_reg: ab8500_ldo_ana {
+ regulator-name = "V-CSI/DSI";
+ };
+ };
+
+ gpio {
+ /* Hog a few default settings */
+ pinctrl-names = "default";
+ pinctrl-0 = <&gpio2_default_mode>,
+ <&gpio4_default_mode>,
+ <&gpio10_default_mode>,
+ <&gpio11_default_mode>,
+ <&gpio12_default_mode>,
+ <&gpio13_default_mode>,
+ <&gpio16_default_mode>,
+ <&gpio24_default_mode>,
+ <&gpio25_default_mode>,
+ <&gpio36_default_mode>,
+ <&gpio37_default_mode>,
+ <&gpio38_default_mode>,
+ <&gpio39_default_mode>,
+ <&gpio42_default_mode>,
+ <&gpio26_default_mode>,
+ <&gpio35_default_mode>,
+ <&ycbcr_default_mode>,
+ <&pwm_default_mode>,
+ <&adi1_default_mode>,
+ <&usbuicc_default_mode>,
+ <&dmic_default_mode>,
+ <&extcpena_default_mode>,
+ <&modsclsda_default_mode>;
+
+ /*
+ * Pins 2, 4, 10, 11, 12, 13, 16, 24, 25, 36, 37, 38, 39 and 42
+ * are muxed in as GPIO, and configured as INPUT PULL DOWN
+ */
+ gpio2 {
+ gpio2_default_mode: gpio2_default {
+ default_mux {
+ function = "gpio";
+ groups = "gpio2_a_1";
+ };
+ default_cfg {
+ pins = "GPIO2_T9";
+ input-enable;
+ bias-pull-down;
+ };
+ };
+ };
+ gpio4 {
+ gpio4_default_mode: gpio4_default {
+ default_mux {
+ function = "gpio";
+ groups = "gpio4_a_1";
+ };
+ default_cfg {
+ pins = "GPIO4_W2";
+ input-enable;
+ bias-pull-down;
+ };
+ };
+ };
+ gpio10 {
+ gpio10_default_mode: gpio10_default {
+ default_mux {
+ function = "gpio";
+ groups = "gpio10_d_1";
+ };
+ default_cfg {
+ pins = "GPIO10_U17";
+ input-enable;
+ bias-pull-down;
+ };
+ };
+ };
+ gpio11 {
+ gpio11_default_mode: gpio11_default {
+ default_mux {
+ function = "gpio";
+ groups = "gpio11_d_1";
+ };
+ default_cfg {
+ pins = "GPIO11_AA18";
+ input-enable;
+ bias-pull-down;
+ };
+ };
+ };
+ gpio12 {
+ gpio12_default_mode: gpio12_default {
+ default_mux {
+ function = "gpio";
+ groups = "gpio12_d_1";
+ };
+ default_cfg {
+ pins = "GPIO12_U16";
+ input-enable;
+ bias-pull-down;
+ };
+ };
+ };
+ gpio13 {
+ gpio13_default_mode: gpio13_default {
+ default_mux {
+ function = "gpio";
+ groups = "gpio13_d_1";
+ };
+ default_cfg {
+ pins = "GPIO13_W17";
+ input-enable;
+ bias-pull-down;
+ };
+ };
+ };
+ gpio16 {
+ gpio16_default_mode: gpio16_default {
+ default_mux {
+ function = "gpio";
+ groups = "gpio16_a_1";
+ };
+ default_cfg {
+ pins = "GPIO16_F15";
+ input-enable;
+ bias-pull-down;
+ };
+ };
+ };
+ gpio24 {
+ gpio24_default_mode: gpio24_default {
+ default_mux {
+ function = "gpio";
+ groups = "gpio24_a_1";
+ };
+ default_cfg {
+ pins = "GPIO24_T14";
+ input-enable;
+ bias-pull-down;
+ };
+ };
+ };
+ gpio25 {
+ gpio25_default_mode: gpio25_default {
+ default_mux {
+ function = "gpio";
+ groups = "gpio25_a_1";
+ };
+ default_cfg {
+ pins = "GPIO25_R16";
+ input-enable;
+ bias-pull-down;
+ };
+ };
+ };
+ gpio36 {
+ gpio36_default_mode: gpio36_default {
+ default_mux {
+ function = "gpio";
+ groups = "gpio36_a_1";
+ };
+ default_cfg {
+ pins = "GPIO36_A17";
+ input-enable;
+ bias-pull-down;
+ };
+ };
+ };
+ gpio37 {
+ gpio37_default_mode: gpio37_default {
+ default_mux {
+ function = "gpio";
+ groups = "gpio37_a_1";
+ };
+ default_cfg {
+ pins = "GPIO37_E15";
+ input-enable;
+ bias-pull-down;
+ };
+ };
+ };
+ gpio38 {
+ gpio38_default_mode: gpio38_default {
+ default_mux {
+ function = "gpio";
+ groups = "gpio38_a_1";
+ };
+ default_cfg {
+ pins = "GPIO38_C17";
+ input-enable;
+ bias-pull-down;
+ };
+ };
+ };
+ gpio39 {
+ gpio39_default_mode: gpio39_default {
+ default_mux {
+ function = "gpio";
+ groups = "gpio39_a_1";
+ };
+ default_cfg {
+ pins = "GPIO39_E16";
+ input-enable;
+ bias-pull-down;
+ };
+ };
+ };
+ gpio42 {
+ gpio42_default_mode: gpio42_default {
+ default_mux {
+ function = "gpio";
+ groups = "gpio42_a_1";
+ };
+ default_cfg {
+ pins = "GPIO42_U2";
+ input-enable;
+ bias-pull-down;
+ };
+ };
+ };
+ /*
+ * Pins 26 and 35 muxed in as GPIO, and configured as OUTPUT LOW
+ */
+ gpio26 {
+ gpio26_default_mode: gpio26_default {
+ default_mux {
+ function = "gpio";
+ groups = "gpio26_d_1";
+ };
+ default_cfg {
+ pins = "GPIO26_M16";
+ output-low;
+ };
+ };
+ };
+ gpio35 {
+ gpio35_default_mode: gpio35_default {
+ default_mux {
+ function = "gpio";
+ groups = "gpio35_d_1";
+ };
+ default_cfg {
+ pins = "GPIO35_W15";
+ output-low;
+ };
+ };
+ };
+ /*
+ * This sets up the YCBCR connector pins, i.e. analog video out.
+ * Set as input with no bias.
+ */
+ ycbcr {
+ ycbcr_default_mode: ycbcr_default {
+ default_mux {
+ function = "ycbcr";
+ groups = "ycbcr0123_d_1";
+ };
+ default_cfg {
+ pins = "GPIO6_Y18",
+ "GPIO7_AA20",
+ "GPIO8_W18",
+ "GPIO9_AA19";
+ input-enable;
+ bias-disable;
+ };
+ };
+ };
+ /* This sets up the PWM pins 14 and 15 */
+ pwm {
+ pwm_default_mode: pwm_default {
+ default_mux {
+ function = "pwmout";
+ groups = "pwmout1_d_1", "pwmout2_d_1";
+ };
+ default_cfg {
+ pins = "GPIO14_F14",
+ "GPIO15_B17";
+ input-enable;
+ bias-pull-down;
+ };
+ };
+ };
+ /* This sets up audio interface 1 */
+ adi1 {
+ adi1_default_mode: adi1_default {
+ default_mux {
+ function = "adi1";
+ groups = "adi1_d_1";
+ };
+ default_cfg {
+ pins = "GPIO17_P5",
+ "GPIO18_R5",
+ "GPIO19_U5",
+ "GPIO20_T5";
+ input-enable;
+ bias-pull-down;
+ };
+ };
+ };
+ /* This sets up the USB UICC pins */
+ usbuicc {
+ usbuicc_default_mode: usbuicc_default {
+ default_mux {
+ function = "usbuicc";
+ groups = "usbuicc_d_1";
+ };
+ default_cfg {
+ pins = "GPIO21_H19",
+ "GPIO22_G20",
+ "GPIO23_G19";
+ input-enable;
+ bias-pull-down;
+ };
+ };
+ };
+ /* This sets up the microphone pins */
+ dmic {
+ dmic_default_mode: dmic_default {
+ default_mux {
+ function = "dmic";
+ groups = "dmic12_d_1",
+ "dmic34_d_1",
+ "dmic56_d_1";
+ };
+ default_cfg {
+ pins = "GPIO27_J6",
+ "GPIO28_K6",
+ "GPIO29_G6",
+ "GPIO30_H6",
+ "GPIO31_F5",
+ "GPIO32_G5";
+ input-enable;
+ bias-pull-down;
+ };
+ };
+ };
+ extcpena {
+ extcpena_default_mode: extcpena_default {
+ default_mux {
+ function = "extcpena";
+ groups = "extcpena_d_1";
+ };
+ default_cfg {
+ pins = "GPIO34_R17";
+ input-enable;
+ bias-pull-down;
+ };
+ };
+ };
+ /* Modem I2C setup (SCL and SDA pins) */
+ modsclsda {
+ modsclsda_default_mode: modsclsda_default {
+ default_mux {
+ function = "modsclsda";
+ groups = "modsclsda_d_1";
+ };
+ default_cfg {
+ pins = "GPIO40_T19",
+ "GPIO41_U19";
+ input-enable;
+ bias-pull-down;
+ };
+ };
+ };
+ /*
+ * Clock output pins associated with regulators.
+ */
+ sysclkreq2 {
+ sysclkreq2_default_mode: sysclkreq2_default {
+ default_mux {
+ function = "sysclkreq";
+ groups = "sysclkreq2_d_1";
+ };
+ default_cfg {
+ pins = "GPIO1_T10";
+ input-enable;
+ bias-disable;
+ };
+ };
+ sysclkreq2_sleep_mode: sysclkreq2_sleep {
+ default_mux {
+ function = "gpio";
+ groups = "gpio1_a_1";
+ };
+ default_cfg {
+ pins = "GPIO1_T10";
+ input-enable;
+ bias-pull-down;
+ };
+ };
+ };
+ sysclkreq4 {
+ sysclkreq4_default_mode: sysclkreq4_default {
+ default_mux {
+ function = "sysclkreq";
+ groups = "sysclkreq4_d_1";
+ };
+ default_cfg {
+ pins = "GPIO3_U9";
+ input-enable;
+ bias-disable;
+ };
+ };
+ sysclkreq4_sleep_mode: sysclkreq4_sleep {
+ default_mux {
+ function = "gpio";
+ groups = "gpio3_a_1";
+ };
+ default_cfg {
+ pins = "GPIO3_U9";
+ input-enable;
+ bias-pull-down;
+ };
+ };
+ };
+ };
+ /*
+ * Charging is not working on the HREF unless an actual battery is
+ * mounted, most HREFs have a DC cable in to the "battery power"
+ * which means this will only be cofusing. So do not enable charging
+ * of the HREFs.
+ */
+ ab8500_fg {
+ status = "disabled";
+ };
+ ab8500_btemp {
+ status = "disabled";
+ };
+ ab8500_charger {
+ status = "disabled";
+ };
+ ab8500_chargalg {
+ status = "disabled";
+ };
+ };
+ };
+ };
+};
diff --git a/dts/upstream/src/arm/st/ste-href.dtsi b/dts/upstream/src/arm/st/ste-href.dtsi
index 13b11db..fbf0309 100644
--- a/dts/upstream/src/arm/st/ste-href.dtsi
+++ b/dts/upstream/src/arm/st/ste-href.dtsi
@@ -242,61 +242,6 @@
status = "okay";
};
- prcmu@80157000 {
- ab8500 {
- gpio {
- };
-
- phy {
- pinctrl-names = "default", "sleep";
- pinctrl-0 = <&usb_a_1_default>;
- pinctrl-1 = <&usb_a_1_sleep>;
- };
-
- regulator {
- ab8500_ldo_aux1_reg: ab8500_ldo_aux1 {
- regulator-name = "V-DISPLAY";
- };
-
- ab8500_ldo_aux2_reg: ab8500_ldo_aux2 {
- regulator-name = "V-eMMC1";
- };
-
- ab8500_ldo_aux3_reg: ab8500_ldo_aux3 {
- regulator-name = "V-MMC-SD";
- };
-
- ab8500_ldo_intcore_reg: ab8500_ldo_intcore {
- regulator-name = "V-INTCORE";
- };
-
- ab8500_ldo_tvout_reg: ab8500_ldo_tvout {
- regulator-name = "V-TVOUT";
- };
-
- ab8500_ldo_audio_reg: ab8500_ldo_audio {
- regulator-name = "V-AUD";
- };
-
- ab8500_ldo_anamic1_reg: ab8500_ldo_anamic1 {
- regulator-name = "V-AMIC1";
- };
-
- ab8500_ldo_anamic2_reg: ab8500_ldo_anamic2 {
- regulator-name = "V-AMIC2";
- };
-
- ab8500_ldo_dmic_reg: ab8500_ldo_dmic {
- regulator-name = "V-DMIC";
- };
-
- ab8500_ldo_ana_reg: ab8500_ldo_ana {
- regulator-name = "V-CSI/DSI";
- };
- };
- };
- };
-
pinctrl {
sdi0 {
sdi0_default_mode: sdi0_default {
diff --git a/dts/upstream/src/arm/st/ste-href520-tvk.dts b/dts/upstream/src/arm/st/ste-href520-tvk.dts
index 7f661f8..5677df4 100644
--- a/dts/upstream/src/arm/st/ste-href520-tvk.dts
+++ b/dts/upstream/src/arm/st/ste-href520-tvk.dts
@@ -5,6 +5,7 @@
/dts-v1/;
#include "ste-db8520.dtsi"
+#include "ste-href-ab8505.dtsi"
#include "ste-hrefv60plus.dtsi"
#include "ste-href-tvk1281618-r3.dtsi"
diff --git a/dts/upstream/src/arm/st/ste-hrefprev60-stuib.dts b/dts/upstream/src/arm/st/ste-hrefprev60-stuib.dts
index a29e345..b142bb2 100644
--- a/dts/upstream/src/arm/st/ste-hrefprev60-stuib.dts
+++ b/dts/upstream/src/arm/st/ste-hrefprev60-stuib.dts
@@ -5,6 +5,7 @@
/dts-v1/;
#include "ste-db8500.dtsi"
+#include "ste-href-ab8500.dtsi"
#include "ste-hrefprev60.dtsi"
#include "ste-href-stuib.dtsi"
diff --git a/dts/upstream/src/arm/st/ste-hrefprev60-tvk.dts b/dts/upstream/src/arm/st/ste-hrefprev60-tvk.dts
index 1968bd1..5da1ff4 100644
--- a/dts/upstream/src/arm/st/ste-hrefprev60-tvk.dts
+++ b/dts/upstream/src/arm/st/ste-hrefprev60-tvk.dts
@@ -5,6 +5,7 @@
/dts-v1/;
#include "ste-db8500.dtsi"
+#include "ste-href-ab8500.dtsi"
#include "ste-hrefprev60.dtsi"
#include "ste-href-tvk1281618-r2.dtsi"
diff --git a/dts/upstream/src/arm/st/ste-hrefprev60.dtsi b/dts/upstream/src/arm/st/ste-hrefprev60.dtsi
index 9859ee9..c87fd27 100644
--- a/dts/upstream/src/arm/st/ste-hrefprev60.dtsi
+++ b/dts/upstream/src/arm/st/ste-hrefprev60.dtsi
@@ -62,7 +62,7 @@
// External Micro SD slot
mmc@80126000 {
- cd-gpios = <&tc3589x_gpio 3 GPIO_ACTIVE_HIGH>;
+ cd-gpios = <&tc3589x_gpio 3 GPIO_ACTIVE_HIGH>;
};
pinctrl {
diff --git a/dts/upstream/src/arm/st/ste-hrefv60plus-stuib.dts b/dts/upstream/src/arm/st/ste-hrefv60plus-stuib.dts
index 7a5b6aa..c4abe24 100644
--- a/dts/upstream/src/arm/st/ste-hrefv60plus-stuib.dts
+++ b/dts/upstream/src/arm/st/ste-hrefv60plus-stuib.dts
@@ -7,6 +7,7 @@
/dts-v1/;
#include "ste-db8500.dtsi"
+#include "ste-href-ab8500.dtsi"
#include "ste-hrefv60plus.dtsi"
#include "ste-href-stuib.dtsi"
diff --git a/dts/upstream/src/arm/st/ste-hrefv60plus-tvk.dts b/dts/upstream/src/arm/st/ste-hrefv60plus-tvk.dts
index d5af3f3..f55e8de 100644
--- a/dts/upstream/src/arm/st/ste-hrefv60plus-tvk.dts
+++ b/dts/upstream/src/arm/st/ste-hrefv60plus-tvk.dts
@@ -7,6 +7,7 @@
/dts-v1/;
#include "ste-db8500.dtsi"
+#include "ste-href-ab8500.dtsi"
#include "ste-hrefv60plus.dtsi"
#include "ste-href-tvk1281618-r2.dtsi"
diff --git a/dts/upstream/src/arm/st/ste-hrefv60plus.dtsi b/dts/upstream/src/arm/st/ste-hrefv60plus.dtsi
index e66fa59..b23966c 100644
--- a/dts/upstream/src/arm/st/ste-hrefv60plus.dtsi
+++ b/dts/upstream/src/arm/st/ste-hrefv60plus.dtsi
@@ -3,7 +3,6 @@
* Copyright 2012 ST-Ericsson AB
*/
-#include "ste-href-ab8500.dtsi"
#include "ste-href.dtsi"
/ {
@@ -191,7 +190,7 @@
// External Micro SD slot
mmc@80126000 {
- cd-gpios = <&gpio2 31 GPIO_ACTIVE_HIGH>; // 95
+ cd-gpios = <&gpio2 31 GPIO_ACTIVE_HIGH>; // 95
};
pinctrl {
diff --git a/dts/upstream/src/arm/st/ste-nomadik-stn8815.dtsi b/dts/upstream/src/arm/st/ste-nomadik-stn8815.dtsi
index 6816eef..4d37c5f 100644
--- a/dts/upstream/src/arm/st/ste-nomadik-stn8815.dtsi
+++ b/dts/upstream/src/arm/st/ste-nomadik-stn8815.dtsi
@@ -52,7 +52,7 @@
gpio0: gpio@101e4000 {
compatible = "st,nomadik-gpio";
- reg = <0x101e4000 0x80>;
+ reg = <0x101e4000 0x80>;
interrupt-parent = <&vica>;
interrupts = <6>;
interrupt-controller;
@@ -66,7 +66,7 @@
gpio1: gpio@101e5000 {
compatible = "st,nomadik-gpio";
- reg = <0x101e5000 0x80>;
+ reg = <0x101e5000 0x80>;
interrupt-parent = <&vica>;
interrupts = <7>;
interrupt-controller;
@@ -80,7 +80,7 @@
gpio2: gpio@101e6000 {
compatible = "st,nomadik-gpio";
- reg = <0x101e6000 0x80>;
+ reg = <0x101e6000 0x80>;
interrupt-parent = <&vica>;
interrupts = <8>;
interrupt-controller;
@@ -94,7 +94,7 @@
gpio3: gpio@101e7000 {
compatible = "st,nomadik-gpio";
- reg = <0x101e7000 0x80>;
+ reg = <0x101e7000 0x80>;
ngpio = <28>;
interrupt-parent = <&vica>;
interrupts = <9>;
diff --git a/dts/upstream/src/arm/st/ste-snowball.dts b/dts/upstream/src/arm/st/ste-snowball.dts
index 27c2ec5..1322abf 100644
--- a/dts/upstream/src/arm/st/ste-snowball.dts
+++ b/dts/upstream/src/arm/st/ste-snowball.dts
@@ -266,7 +266,7 @@
pinctrl-1 = <&mc0_a_1_sleep>;
/* GPIO218 MMC_CD */
- cd-gpios = <&gpio6 26 GPIO_ACTIVE_LOW>;
+ cd-gpios = <&gpio6 26 GPIO_ACTIVE_LOW>;
status = "okay";
};
diff --git a/dts/upstream/src/arm/st/ste-ux500-samsung-codina-tmo.dts b/dts/upstream/src/arm/st/ste-ux500-samsung-codina-tmo.dts
index 463942a..c623cc3 100644
--- a/dts/upstream/src/arm/st/ste-ux500-samsung-codina-tmo.dts
+++ b/dts/upstream/src/arm/st/ste-ux500-samsung-codina-tmo.dts
@@ -310,7 +310,7 @@
pinctrl-names = "default", "sleep";
pinctrl-0 = <&mc0_a_2_default>;
pinctrl-1 = <&mc0_a_2_sleep>;
- cd-gpios = <&gpio6 25 GPIO_ACTIVE_LOW>; // GPIO217
+ cd-gpios = <&gpio6 25 GPIO_ACTIVE_LOW>; // GPIO217
status = "okay";
};
diff --git a/dts/upstream/src/arm/st/ste-ux500-samsung-codina.dts b/dts/upstream/src/arm/st/ste-ux500-samsung-codina.dts
index c1ae0e2..2355ca6 100644
--- a/dts/upstream/src/arm/st/ste-ux500-samsung-codina.dts
+++ b/dts/upstream/src/arm/st/ste-ux500-samsung-codina.dts
@@ -402,7 +402,7 @@
pinctrl-names = "default", "sleep";
pinctrl-0 = <&mc0_a_2_default>;
pinctrl-1 = <&mc0_a_2_sleep>;
- cd-gpios = <&gpio6 25 GPIO_ACTIVE_LOW>; // GPIO217
+ cd-gpios = <&gpio6 25 GPIO_ACTIVE_LOW>; // GPIO217
status = "okay";
};
diff --git a/dts/upstream/src/arm/st/ste-ux500-samsung-gavini.dts b/dts/upstream/src/arm/st/ste-ux500-samsung-gavini.dts
index b21e40d..ad9a20c 100644
--- a/dts/upstream/src/arm/st/ste-ux500-samsung-gavini.dts
+++ b/dts/upstream/src/arm/st/ste-ux500-samsung-gavini.dts
@@ -362,7 +362,7 @@
pinctrl-0 = <&mc0_a_2_default>;
pinctrl-1 = <&mc0_a_2_sleep>;
/* "flash detect" actually card detect */
- cd-gpios = <&gpio6 25 GPIO_ACTIVE_LOW>;
+ cd-gpios = <&gpio6 25 GPIO_ACTIVE_LOW>;
status = "okay";
};
diff --git a/dts/upstream/src/arm/st/ste-ux500-samsung-janice.dts b/dts/upstream/src/arm/st/ste-ux500-samsung-janice.dts
index 6e586e8..229f7c3 100644
--- a/dts/upstream/src/arm/st/ste-ux500-samsung-janice.dts
+++ b/dts/upstream/src/arm/st/ste-ux500-samsung-janice.dts
@@ -412,7 +412,7 @@
pinctrl-names = "default", "sleep";
pinctrl-0 = <&mc0_a_2_default>;
pinctrl-1 = <&mc0_a_2_sleep>;
- cd-gpios = <&gpio6 25 GPIO_ACTIVE_LOW>; // GPIO217
+ cd-gpios = <&gpio6 25 GPIO_ACTIVE_LOW>; // GPIO217
status = "okay";
};
diff --git a/dts/upstream/src/arm/st/ste-ux500-samsung-kyle.dts b/dts/upstream/src/arm/st/ste-ux500-samsung-kyle.dts
index ba44210..cdb147d 100644
--- a/dts/upstream/src/arm/st/ste-ux500-samsung-kyle.dts
+++ b/dts/upstream/src/arm/st/ste-ux500-samsung-kyle.dts
@@ -238,7 +238,7 @@
pinctrl-names = "default", "sleep";
pinctrl-0 = <&mc0_a_1_default>;
pinctrl-1 = <&mc0_a_1_sleep>;
- cd-gpios = <&gpio6 25 GPIO_ACTIVE_LOW>; // GPIO217
+ cd-gpios = <&gpio6 25 GPIO_ACTIVE_LOW>; // GPIO217
status = "okay";
};
diff --git a/dts/upstream/src/arm/st/stm32429i-eval.dts b/dts/upstream/src/arm/st/stm32429i-eval.dts
index 576235e..afa417b 100644
--- a/dts/upstream/src/arm/st/stm32429i-eval.dts
+++ b/dts/upstream/src/arm/st/stm32429i-eval.dts
@@ -222,7 +222,6 @@
reg = <0x42>;
interrupts = <8 3>;
interrupt-parent = <&gpioi>;
- interrupt-controller;
wakeup-source;
stmpegpio: stmpe_gpio {
diff --git a/dts/upstream/src/arm/st/stm32f469-disco.dts b/dts/upstream/src/arm/st/stm32f469-disco.dts
index cbbd521..8a4f8dd 100644
--- a/dts/upstream/src/arm/st/stm32f469-disco.dts
+++ b/dts/upstream/src/arm/st/stm32f469-disco.dts
@@ -69,20 +69,13 @@
serial0 = &usart3;
};
- mmc_vcard: mmc_vcard {
+ vcc_3v3: vcc-3v3 {
compatible = "regulator-fixed";
- regulator-name = "mmc_vcard";
+ regulator-name = "vcc_3v3";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
};
- vdd_dsi: vdd-dsi {
- compatible = "regulator-fixed";
- regulator-name = "vdd_dsi";
- regulator-min-microvolt = <3300000>;
- regulator-max-microvolt = <3300000>;
- };
-
soc {
dma-ranges = <0xc0000000 0x0 0x10000000>;
};
@@ -164,7 +157,7 @@
compatible = "orisetech,otm8009a";
reg = <0>; /* dsi virtual channel (0..3) */
reset-gpios = <&gpioh 7 GPIO_ACTIVE_LOW>;
- power-supply = <&vdd_dsi>;
+ power-supply = <&vcc_3v3>;
status = "okay";
port {
@@ -219,7 +212,7 @@
&sdio {
status = "okay";
- vmmc-supply = <&mmc_vcard>;
+ vmmc-supply = <&vcc_3v3>;
cd-gpios = <&gpiog 2 GPIO_ACTIVE_LOW>;
broken-cd;
pinctrl-names = "default", "opendrain";
diff --git a/dts/upstream/src/arm/st/stm32f746.dtsi b/dts/upstream/src/arm/st/stm32f746.dtsi
index 53a8e2d..65c72b6 100644
--- a/dts/upstream/src/arm/st/stm32f746.dtsi
+++ b/dts/upstream/src/arm/st/stm32f746.dtsi
@@ -274,6 +274,26 @@
clocks = <&rcc 0 STM32F7_APB1_CLOCK(CAN3)>;
};
+ spi2: spi@40003800 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ compatible = "st,stm32f7-spi";
+ reg = <0x40003800 0x400>;
+ interrupts = <36>;
+ clocks = <&rcc 0 STM32F7_APB1_CLOCK(SPI2)>;
+ status = "disabled";
+ };
+
+ spi3: spi@40003c00 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ compatible = "st,stm32f7-spi";
+ reg = <0x40003c00 0x400>;
+ interrupts = <51>;
+ clocks = <&rcc 0 STM32F7_APB1_CLOCK(SPI3)>;
+ status = "disabled";
+ };
+
usart2: serial@40004400 {
compatible = "st,stm32f7-uart";
reg = <0x40004400 0x400>;
@@ -491,9 +511,30 @@
status = "disabled";
};
+ spi1: spi@40013000 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ compatible = "st,stm32f7-spi";
+ reg = <0x40013000 0x400>;
+ interrupts = <35>;
+ clocks = <&rcc 0 STM32F7_APB2_CLOCK(SPI1)>;
+ status = "disabled";
+ };
+
+ spi4: spi@40013400 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ compatible = "st,stm32f7-spi";
+ reg = <0x40013400 0x400>;
+ interrupts = <84>;
+ clocks = <&rcc 0 STM32F7_APB2_CLOCK(SPI4)>;
+ status = "disabled";
+ };
+
syscfg: syscon@40013800 {
compatible = "st,stm32-syscfg", "syscon";
reg = <0x40013800 0x400>;
+ clocks = <&rcc 0 STM32F7_APB2_CLOCK(SYSCFG)>;
};
exti: interrupt-controller@40013c00 {
@@ -554,6 +595,26 @@
};
};
+ spi5: spi@40015000 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ compatible = "st,stm32f7-spi";
+ reg = <0x40015000 0x400>;
+ interrupts = <85>;
+ clocks = <&rcc 0 STM32F7_APB2_CLOCK(SPI5)>;
+ status = "disabled";
+ };
+
+ spi6: spi@40015400 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ compatible = "st,stm32f7-spi";
+ reg = <0x40015400 0x400>;
+ interrupts = <86>;
+ clocks = <&rcc 0 STM32F7_APB2_CLOCK(SPI6)>;
+ status = "disabled";
+ };
+
ltdc: display-controller@40016800 {
compatible = "st,stm32-ltdc";
reg = <0x40016800 0x200>;
diff --git a/dts/upstream/src/arm/st/stm32mp135.dtsi b/dts/upstream/src/arm/st/stm32mp135.dtsi
index abf2acd..68d32f9 100644
--- a/dts/upstream/src/arm/st/stm32mp135.dtsi
+++ b/dts/upstream/src/arm/st/stm32mp135.dtsi
@@ -8,5 +8,16 @@
/ {
soc {
+ dcmipp: dcmipp@5a000000 {
+ compatible = "st,stm32mp13-dcmipp";
+ reg = <0x5a000000 0x400>;
+ interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>;
+ resets = <&rcc DCMIPP_R>;
+ clocks = <&rcc DCMIPP_K>;
+ status = "disabled";
+
+ port {
+ };
+ };
};
};
diff --git a/dts/upstream/src/arm/st/stm32mp151.dtsi b/dts/upstream/src/arm/st/stm32mp151.dtsi
index 6150891..fa4cbd3 100644
--- a/dts/upstream/src/arm/st/stm32mp151.dtsi
+++ b/dts/upstream/src/arm/st/stm32mp151.dtsi
@@ -1521,6 +1521,8 @@
clocks = <&usbphyc>, <&rcc USBH>;
resets = <&rcc USBH_R>;
interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;
+ phys = <&usbphyc_port0>;
+ phy-names = "usb";
status = "disabled";
};
@@ -1531,6 +1533,8 @@
resets = <&rcc USBH_R>;
interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>;
companion = <&usbh_ohci>;
+ phys = <&usbphyc_port0>;
+ phy-names = "usb";
status = "disabled";
};
diff --git a/dts/upstream/src/arm/st/stm32mp151a-prtt1l.dtsi b/dts/upstream/src/arm/st/stm32mp151a-prtt1l.dtsi
index dd23de8..3938d35 100644
--- a/dts/upstream/src/arm/st/stm32mp151a-prtt1l.dtsi
+++ b/dts/upstream/src/arm/st/stm32mp151a-prtt1l.dtsi
@@ -206,8 +206,6 @@
};
&usbh_ehci {
- phys = <&usbphyc_port0>;
- phy-names = "usb";
status = "okay";
};
diff --git a/dts/upstream/src/arm/st/stm32mp157a-dk1-scmi.dts b/dts/upstream/src/arm/st/stm32mp157a-dk1-scmi.dts
index afcd628..ce59372 100644
--- a/dts/upstream/src/arm/st/stm32mp157a-dk1-scmi.dts
+++ b/dts/upstream/src/arm/st/stm32mp157a-dk1-scmi.dts
@@ -11,7 +11,7 @@
/ {
model = "STMicroelectronics STM32MP157A-DK1 SCMI Discovery Board";
- compatible = "st,stm32mp157a-dk1-scmi", "st,stm32mp157a-dk1", "st,stm32mp157";
+ compatible = "st,stm32mp157a-dk1-scmi", "st,stm32mp157";
reserved-memory {
optee@de000000 {
@@ -59,7 +59,7 @@
/delete-property/ st,syscfg-holdboot;
resets = <&scmi_reset RST_SCMI_MCU>,
<&scmi_reset RST_SCMI_MCU_HOLD_BOOT>;
- reset-names = "mcu_rst", "hold_boot";
+ reset-names = "mcu_rst", "hold_boot";
};
&rcc {
diff --git a/dts/upstream/src/arm/st/stm32mp157a-stinger96.dtsi b/dts/upstream/src/arm/st/stm32mp157a-stinger96.dtsi
index 5f85598..5c1cc48 100644
--- a/dts/upstream/src/arm/st/stm32mp157a-stinger96.dtsi
+++ b/dts/upstream/src/arm/st/stm32mp157a-stinger96.dtsi
@@ -313,8 +313,6 @@
};
&usbh_ehci {
- phys = <&usbphyc_port0>;
- phy-names = "usb";
status = "okay";
};
diff --git a/dts/upstream/src/arm/st/stm32mp157c-dk2-scmi.dts b/dts/upstream/src/arm/st/stm32mp157c-dk2-scmi.dts
index 39358d9..c20a738 100644
--- a/dts/upstream/src/arm/st/stm32mp157c-dk2-scmi.dts
+++ b/dts/upstream/src/arm/st/stm32mp157c-dk2-scmi.dts
@@ -11,7 +11,7 @@
/ {
model = "STMicroelectronics STM32MP157C-DK2 SCMI Discovery Board";
- compatible = "st,stm32mp157c-dk2-scmi", "st,stm32mp157c-dk2", "st,stm32mp157";
+ compatible = "st,stm32mp157c-dk2-scmi", "st,stm32mp157";
reserved-memory {
optee@de000000 {
@@ -65,7 +65,7 @@
/delete-property/ st,syscfg-holdboot;
resets = <&scmi_reset RST_SCMI_MCU>,
<&scmi_reset RST_SCMI_MCU_HOLD_BOOT>;
- reset-names = "mcu_rst", "hold_boot";
+ reset-names = "mcu_rst", "hold_boot";
};
&rcc {
diff --git a/dts/upstream/src/arm/st/stm32mp157c-dk2.dts b/dts/upstream/src/arm/st/stm32mp157c-dk2.dts
index 510cca5..7a701f7 100644
--- a/dts/upstream/src/arm/st/stm32mp157c-dk2.dts
+++ b/dts/upstream/src/arm/st/stm32mp157c-dk2.dts
@@ -64,7 +64,6 @@
reg = <0x38>;
interrupts = <2 2>;
interrupt-parent = <&gpiof>;
- interrupt-controller;
touchscreen-size-x = <480>;
touchscreen-size-y = <800>;
status = "okay";
diff --git a/dts/upstream/src/arm/st/stm32mp157c-ed1-scmi.dts b/dts/upstream/src/arm/st/stm32mp157c-ed1-scmi.dts
index 07ea765..5e2eaf5 100644
--- a/dts/upstream/src/arm/st/stm32mp157c-ed1-scmi.dts
+++ b/dts/upstream/src/arm/st/stm32mp157c-ed1-scmi.dts
@@ -11,7 +11,7 @@
/ {
model = "STMicroelectronics STM32MP157C-ED1 SCMI eval daughter";
- compatible = "st,stm32mp157c-ed1-scmi", "st,stm32mp157c-ed1", "st,stm32mp157";
+ compatible = "st,stm32mp157c-ed1-scmi", "st,stm32mp157";
reserved-memory {
optee@fe000000 {
@@ -64,7 +64,7 @@
/delete-property/ st,syscfg-holdboot;
resets = <&scmi_reset RST_SCMI_MCU>,
<&scmi_reset RST_SCMI_MCU_HOLD_BOOT>;
- reset-names = "mcu_rst", "hold_boot";
+ reset-names = "mcu_rst", "hold_boot";
};
&rcc {
diff --git a/dts/upstream/src/arm/st/stm32mp157c-emstamp-argon.dtsi b/dts/upstream/src/arm/st/stm32mp157c-emstamp-argon.dtsi
index f928cfb..4792004 100644
--- a/dts/upstream/src/arm/st/stm32mp157c-emstamp-argon.dtsi
+++ b/dts/upstream/src/arm/st/stm32mp157c-emstamp-argon.dtsi
@@ -500,14 +500,10 @@
};
&usbh_ehci {
- phys = <&usbphyc_port0>;
- phy-names = "usb";
status = "okay";
};
&usbh_ohci {
- phys = <&usbphyc_port0>;
- phy-names = "usb";
status = "okay";
};
diff --git a/dts/upstream/src/arm/st/stm32mp157c-ev1-scmi.dts b/dts/upstream/src/arm/st/stm32mp157c-ev1-scmi.dts
index 813086e..3226fb9 100644
--- a/dts/upstream/src/arm/st/stm32mp157c-ev1-scmi.dts
+++ b/dts/upstream/src/arm/st/stm32mp157c-ev1-scmi.dts
@@ -11,8 +11,7 @@
/ {
model = "STMicroelectronics STM32MP157C-EV1 SCMI eval daughter on eval mother";
- compatible = "st,stm32mp157c-ev1-scmi", "st,stm32mp157c-ev1", "st,stm32mp157c-ed1",
- "st,stm32mp157";
+ compatible = "st,stm32mp157c-ev1-scmi", "st,stm32mp157c-ed1", "st,stm32mp157";
reserved-memory {
optee@fe000000 {
@@ -70,7 +69,7 @@
/delete-property/ st,syscfg-holdboot;
resets = <&scmi_reset RST_SCMI_MCU>,
<&scmi_reset RST_SCMI_MCU_HOLD_BOOT>;
- reset-names = "mcu_rst", "hold_boot";
+ reset-names = "mcu_rst", "hold_boot";
};
&rcc {
diff --git a/dts/upstream/src/arm/st/stm32mp157c-ev1.dts b/dts/upstream/src/arm/st/stm32mp157c-ev1.dts
index cd9c3ff..9eb9a1b 100644
--- a/dts/upstream/src/arm/st/stm32mp157c-ev1.dts
+++ b/dts/upstream/src/arm/st/stm32mp157c-ev1.dts
@@ -362,7 +362,6 @@
};
&usbh_ehci {
- phys = <&usbphyc_port0>;
status = "okay";
#address-cells = <1>;
#size-cells = <0>;
diff --git a/dts/upstream/src/arm/st/stm32mp157c-osd32mp1-red.dts b/dts/upstream/src/arm/st/stm32mp157c-osd32mp1-red.dts
index bd67a1d..527c33b 100644
--- a/dts/upstream/src/arm/st/stm32mp157c-osd32mp1-red.dts
+++ b/dts/upstream/src/arm/st/stm32mp157c-osd32mp1-red.dts
@@ -197,14 +197,10 @@
};
&usbh_ehci {
- phys = <&usbphyc_port0>;
- phy-names = "usb";
status = "okay";
};
&usbh_ohci {
- phys = <&usbphyc_port0>;
- phy-names = "usb";
status = "okay";
};
diff --git a/dts/upstream/src/arm/st/stm32mp157c-phycore-stm32mp15-som.dtsi b/dts/upstream/src/arm/st/stm32mp157c-phycore-stm32mp15-som.dtsi
index 4e8b2d2..bf0c320 100644
--- a/dts/upstream/src/arm/st/stm32mp157c-phycore-stm32mp15-som.dtsi
+++ b/dts/upstream/src/arm/st/stm32mp157c-phycore-stm32mp15-som.dtsi
@@ -547,14 +547,10 @@
};
&usbh_ehci {
- phys = <&usbphyc_port0>;
- phy-names = "usb";
status = "okay";
};
&usbh_ohci {
- phys = <&usbphyc_port0>;
- phy-names = "usb";
status = "okay";
};
diff --git a/dts/upstream/src/arm/st/stm32mp15xc-lxa-tac.dtsi b/dts/upstream/src/arm/st/stm32mp15xc-lxa-tac.dtsi
index f09b7c3..fc3a238 100644
--- a/dts/upstream/src/arm/st/stm32mp15xc-lxa-tac.dtsi
+++ b/dts/upstream/src/arm/st/stm32mp15xc-lxa-tac.dtsi
@@ -567,9 +567,6 @@
};
&usbh_ehci {
- phys = <&usbphyc_port0>;
- phy-names = "usb";
-
status = "okay";
};
diff --git a/dts/upstream/src/arm/st/stm32mp15xx-dhcom-drc02.dtsi b/dts/upstream/src/arm/st/stm32mp15xx-dhcom-drc02.dtsi
index 35b1034..bb4f8a0 100644
--- a/dts/upstream/src/arm/st/stm32mp15xx-dhcom-drc02.dtsi
+++ b/dts/upstream/src/arm/st/stm32mp15xx-dhcom-drc02.dtsi
@@ -152,7 +152,6 @@
};
&usbh_ehci {
- phys = <&usbphyc_port0>;
status = "okay";
};
diff --git a/dts/upstream/src/arm/st/stm32mp15xx-dhcom-pdk2.dtsi b/dts/upstream/src/arm/st/stm32mp15xx-dhcom-pdk2.dtsi
index 46b87a2..466d970 100644
--- a/dts/upstream/src/arm/st/stm32mp15xx-dhcom-pdk2.dtsi
+++ b/dts/upstream/src/arm/st/stm32mp15xx-dhcom-pdk2.dtsi
@@ -305,7 +305,6 @@
};
&usbh_ehci {
- phys = <&usbphyc_port0>;
status = "okay";
};
diff --git a/dts/upstream/src/arm/st/stm32mp15xx-dhcom-picoitx.dtsi b/dts/upstream/src/arm/st/stm32mp15xx-dhcom-picoitx.dtsi
index abc5953..b5bc53acc 100644
--- a/dts/upstream/src/arm/st/stm32mp15xx-dhcom-picoitx.dtsi
+++ b/dts/upstream/src/arm/st/stm32mp15xx-dhcom-picoitx.dtsi
@@ -119,12 +119,10 @@
};
&usbh_ehci {
- phys = <&usbphyc_port0>;
status = "okay";
};
&usbh_ohci {
- phys = <&usbphyc_port0>;
status = "okay";
};
diff --git a/dts/upstream/src/arm/st/stm32mp15xx-dhcor-avenger96.dtsi b/dts/upstream/src/arm/st/stm32mp15xx-dhcor-avenger96.dtsi
index 0069ad7..343a461 100644
--- a/dts/upstream/src/arm/st/stm32mp15xx-dhcor-avenger96.dtsi
+++ b/dts/upstream/src/arm/st/stm32mp15xx-dhcor-avenger96.dtsi
@@ -489,8 +489,6 @@
};
&usbh_ehci {
- phys = <&usbphyc_port0>;
- phy-names = "usb";
status = "okay";
};
diff --git a/dts/upstream/src/arm/st/stm32mp15xx-dhcor-drc-compact.dtsi b/dts/upstream/src/arm/st/stm32mp15xx-dhcor-drc-compact.dtsi
index 92d906b..bc4ddcb 100644
--- a/dts/upstream/src/arm/st/stm32mp15xx-dhcor-drc-compact.dtsi
+++ b/dts/upstream/src/arm/st/stm32mp15xx-dhcor-drc-compact.dtsi
@@ -312,12 +312,10 @@
};
&usbh_ehci {
- phys = <&usbphyc_port0>;
status = "okay";
};
&usbh_ohci {
- phys = <&usbphyc_port0>;
status = "okay";
};
diff --git a/dts/upstream/src/arm/st/stm32mp15xx-dhcor-testbench.dtsi b/dts/upstream/src/arm/st/stm32mp15xx-dhcor-testbench.dtsi
index ab7f0ba..6e79c4b 100644
--- a/dts/upstream/src/arm/st/stm32mp15xx-dhcor-testbench.dtsi
+++ b/dts/upstream/src/arm/st/stm32mp15xx-dhcor-testbench.dtsi
@@ -168,12 +168,10 @@
};
&usbh_ehci {
- phys = <&usbphyc_port0>;
status = "okay";
};
&usbh_ohci {
- phys = <&usbphyc_port0>;
status = "okay";
};
diff --git a/dts/upstream/src/arm/st/stm32mp15xx-dkx.dtsi b/dts/upstream/src/arm/st/stm32mp15xx-dkx.dtsi
index 511113f..f7634c5 100644
--- a/dts/upstream/src/arm/st/stm32mp15xx-dkx.dtsi
+++ b/dts/upstream/src/arm/st/stm32mp15xx-dkx.dtsi
@@ -680,7 +680,6 @@
};
&usbh_ehci {
- phys = <&usbphyc_port0>;
status = "okay";
#address-cells = <1>;
#size-cells = <0>;
diff --git a/dts/upstream/src/arm/ti/keystone/keystone-k2e-netcp.dtsi b/dts/upstream/src/arm/ti/keystone/keystone-k2e-netcp.dtsi
index bff73a0..5c88a90 100644
--- a/dts/upstream/src/arm/ti/keystone/keystone-k2e-netcp.dtsi
+++ b/dts/upstream/src/arm/ti/keystone/keystone-k2e-netcp.dtsi
@@ -36,9 +36,9 @@
qpend {
qpend-0 {
qrange = <658 8>;
- interrupts =<0 40 0xf04 0 41 0xf04 0 42 0xf04
- 0 43 0xf04 0 44 0xf04 0 45 0xf04
- 0 46 0xf04 0 47 0xf04>;
+ interrupts = <0 40 0xf04 0 41 0xf04 0 42 0xf04
+ 0 43 0xf04 0 44 0xf04 0 45 0xf04
+ 0 46 0xf04 0 47 0xf04>;
};
qpend-1 {
qrange = <528 16>;
diff --git a/dts/upstream/src/arm/ti/keystone/keystone-k2g-evm.dts b/dts/upstream/src/arm/ti/keystone/keystone-k2g-evm.dts
index 7bfc80f..f0ddbbc 100644
--- a/dts/upstream/src/arm/ti/keystone/keystone-k2g-evm.dts
+++ b/dts/upstream/src/arm/ti/keystone/keystone-k2g-evm.dts
@@ -9,7 +9,7 @@
#include "keystone-k2g.dtsi"
/ {
- compatible = "ti,k2g-evm", "ti,k2g", "ti,keystone";
+ compatible = "ti,k2g-evm", "ti,k2g", "ti,keystone";
model = "Texas Instruments K2G General Purpose EVM";
memory@800000000 {
diff --git a/dts/upstream/src/arm/ti/keystone/keystone-k2g-netcp.dtsi b/dts/upstream/src/arm/ti/keystone/keystone-k2g-netcp.dtsi
index f630693..7109ca0 100644
--- a/dts/upstream/src/arm/ti/keystone/keystone-k2g-netcp.dtsi
+++ b/dts/upstream/src/arm/ti/keystone/keystone-k2g-netcp.dtsi
@@ -37,9 +37,9 @@
qpend {
qpend-0 {
qrange = <77 8>;
- interrupts =<0 308 0xf04 0 309 0xf04 0 310 0xf04
- 0 311 0xf04 0 312 0xf04 0 313 0xf04
- 0 314 0xf04 0 315 0xf04>;
+ interrupts = <0 308 0xf04 0 309 0xf04 0 310 0xf04
+ 0 311 0xf04 0 312 0xf04 0 313 0xf04
+ 0 314 0xf04 0 315 0xf04>;
qalloc-by-id;
};
};
diff --git a/dts/upstream/src/arm/ti/keystone/keystone-k2hk-evm.dts b/dts/upstream/src/arm/ti/keystone/keystone-k2hk-evm.dts
index 206df8a..8dfb542 100644
--- a/dts/upstream/src/arm/ti/keystone/keystone-k2hk-evm.dts
+++ b/dts/upstream/src/arm/ti/keystone/keystone-k2hk-evm.dts
@@ -10,7 +10,7 @@
#include "keystone-k2hk.dtsi"
/ {
- compatible = "ti,k2hk-evm", "ti,k2hk", "ti,keystone";
+ compatible = "ti,k2hk-evm", "ti,k2hk", "ti,keystone";
model = "Texas Instruments Keystone 2 Kepler/Hawking EVM";
reserved-memory {
diff --git a/dts/upstream/src/arm/ti/keystone/keystone-k2hk-netcp.dtsi b/dts/upstream/src/arm/ti/keystone/keystone-k2hk-netcp.dtsi
index 8a421c6..c2ee775 100644
--- a/dts/upstream/src/arm/ti/keystone/keystone-k2hk-netcp.dtsi
+++ b/dts/upstream/src/arm/ti/keystone/keystone-k2hk-netcp.dtsi
@@ -49,9 +49,9 @@
qpend {
qpend-0 {
qrange = <658 8>;
- interrupts =<0 40 0xf04 0 41 0xf04 0 42 0xf04
- 0 43 0xf04 0 44 0xf04 0 45 0xf04
- 0 46 0xf04 0 47 0xf04>;
+ interrupts = <0 40 0xf04 0 41 0xf04 0 42 0xf04
+ 0 43 0xf04 0 44 0xf04 0 45 0xf04
+ 0 46 0xf04 0 47 0xf04>;
};
qpend-1 {
qrange = <8704 16>;
diff --git a/dts/upstream/src/arm/ti/keystone/keystone-k2l-netcp.dtsi b/dts/upstream/src/arm/ti/keystone/keystone-k2l-netcp.dtsi
index 5ec6680..1afebd7 100644
--- a/dts/upstream/src/arm/ti/keystone/keystone-k2l-netcp.dtsi
+++ b/dts/upstream/src/arm/ti/keystone/keystone-k2l-netcp.dtsi
@@ -36,9 +36,9 @@
qpend {
qpend-0 {
qrange = <658 8>;
- interrupts =<0 40 0xf04 0 41 0xf04 0 42 0xf04
- 0 43 0xf04 0 44 0xf04 0 45 0xf04
- 0 46 0xf04 0 47 0xf04>;
+ interrupts = <0 40 0xf04 0 41 0xf04 0 42 0xf04
+ 0 43 0xf04 0 44 0xf04 0 45 0xf04
+ 0 46 0xf04 0 47 0xf04>;
};
qpend-1 {
qrange = <528 16>;
diff --git a/dts/upstream/src/arm/ti/omap/am335x-moxa-uc-2100-common.dtsi b/dts/upstream/src/arm/ti/omap/am335x-moxa-uc-2100-common.dtsi
index b8730aa..a59331a 100644
--- a/dts/upstream/src/arm/ti/omap/am335x-moxa-uc-2100-common.dtsi
+++ b/dts/upstream/src/arm/ti/omap/am335x-moxa-uc-2100-common.dtsi
@@ -217,7 +217,7 @@
pinctrl-names = "default";
pinctrl-0 = <&spi1_pins>;
- tpm_spi_tis@0 {
+ tpm@0 {
compatible = "tcg,tpm_tis-spi";
reg = <0>;
spi-max-frequency = <500000>;
diff --git a/dts/upstream/src/arm/ti/omap/am571x-idk.dts b/dts/upstream/src/arm/ti/omap/am571x-idk.dts
index 4842502..322cf79 100644
--- a/dts/upstream/src/arm/ti/omap/am571x-idk.dts
+++ b/dts/upstream/src/arm/ti/omap/am571x-idk.dts
@@ -168,8 +168,8 @@
};
&extcon_usb2 {
- id-gpio = <&gpio5 7 GPIO_ACTIVE_HIGH>;
- vbus-gpio = <&gpio7 22 GPIO_ACTIVE_HIGH>;
+ id-gpios = <&gpio5 7 GPIO_ACTIVE_HIGH>;
+ vbus-gpios = <&gpio7 22 GPIO_ACTIVE_HIGH>;
};
&sn65hvs882 {
diff --git a/dts/upstream/src/arm/ti/omap/am5729-beagleboneai.dts b/dts/upstream/src/arm/ti/omap/am5729-beagleboneai.dts
index 9a234dc..3e834fc 100644
--- a/dts/upstream/src/arm/ti/omap/am5729-beagleboneai.dts
+++ b/dts/upstream/src/arm/ti/omap/am5729-beagleboneai.dts
@@ -197,7 +197,7 @@
extcon_usb1: extcon_usb1 {
compatible = "linux,extcon-usb-gpio";
ti,enable-id-detection;
- id-gpio = <&gpio3 13 GPIO_ACTIVE_HIGH>;
+ id-gpios = <&gpio3 13 GPIO_ACTIVE_HIGH>;
};
};
@@ -415,7 +415,6 @@
reg = <0x41>;
interrupts = <30 IRQ_TYPE_LEVEL_LOW>;
interrupt-parent = <&gpio2>;
- interrupt-controller;
id = <0>;
blocks = <0x5>;
irq-trigger = <0x1>;
diff --git a/dts/upstream/src/arm/ti/omap/am572x-idk-common.dtsi b/dts/upstream/src/arm/ti/omap/am572x-idk-common.dtsi
index 1d66278..3fca848 100644
--- a/dts/upstream/src/arm/ti/omap/am572x-idk-common.dtsi
+++ b/dts/upstream/src/arm/ti/omap/am572x-idk-common.dtsi
@@ -169,8 +169,8 @@
};
&extcon_usb2 {
- id-gpio = <&gpio3 16 GPIO_ACTIVE_HIGH>;
- vbus-gpio = <&gpio3 26 GPIO_ACTIVE_HIGH>;
+ id-gpios = <&gpio3 16 GPIO_ACTIVE_HIGH>;
+ vbus-gpios = <&gpio3 26 GPIO_ACTIVE_HIGH>;
};
&sn65hvs882 {
diff --git a/dts/upstream/src/arm/ti/omap/dra7-evm-common.dtsi b/dts/upstream/src/arm/ti/omap/dra7-evm-common.dtsi
index 4cdffd6..ed5199d 100644
--- a/dts/upstream/src/arm/ti/omap/dra7-evm-common.dtsi
+++ b/dts/upstream/src/arm/ti/omap/dra7-evm-common.dtsi
@@ -15,12 +15,12 @@
extcon_usb1: extcon_usb1 {
compatible = "linux,extcon-usb-gpio";
- id-gpio = <&pcf_gpio_21 1 GPIO_ACTIVE_HIGH>;
+ id-gpios = <&pcf_gpio_21 1 GPIO_ACTIVE_HIGH>;
};
extcon_usb2: extcon_usb2 {
compatible = "linux,extcon-usb-gpio";
- id-gpio = <&pcf_gpio_21 2 GPIO_ACTIVE_HIGH>;
+ id-gpios = <&pcf_gpio_21 2 GPIO_ACTIVE_HIGH>;
};
sound0: sound0 {
diff --git a/dts/upstream/src/arm/ti/omap/dra71-evm.dts b/dts/upstream/src/arm/ti/omap/dra71-evm.dts
index a643644..f747ac5 100644
--- a/dts/upstream/src/arm/ti/omap/dra71-evm.dts
+++ b/dts/upstream/src/arm/ti/omap/dra71-evm.dts
@@ -293,11 +293,11 @@
};
&extcon_usb1 {
- vbus-gpio = <&pcf_lcd 14 GPIO_ACTIVE_HIGH>;
+ vbus-gpios = <&pcf_lcd 14 GPIO_ACTIVE_HIGH>;
};
&extcon_usb2 {
- vbus-gpio = <&pcf_lcd 15 GPIO_ACTIVE_HIGH>;
+ vbus-gpios = <&pcf_lcd 15 GPIO_ACTIVE_HIGH>;
};
&ipu2 {
diff --git a/dts/upstream/src/arm/ti/omap/dra72-evm-common.dtsi b/dts/upstream/src/arm/ti/omap/dra72-evm-common.dtsi
index 31ab0c6..f8151c6 100644
--- a/dts/upstream/src/arm/ti/omap/dra72-evm-common.dtsi
+++ b/dts/upstream/src/arm/ti/omap/dra72-evm-common.dtsi
@@ -96,12 +96,12 @@
extcon_usb1: extcon_usb1 {
compatible = "linux,extcon-usb-gpio";
- id-gpio = <&pcf_gpio_21 1 GPIO_ACTIVE_HIGH>;
+ id-gpios = <&pcf_gpio_21 1 GPIO_ACTIVE_HIGH>;
};
extcon_usb2: extcon_usb2 {
compatible = "linux,extcon-usb-gpio";
- id-gpio = <&pcf_gpio_21 2 GPIO_ACTIVE_HIGH>;
+ id-gpios = <&pcf_gpio_21 2 GPIO_ACTIVE_HIGH>;
};
hdmi0: connector {
diff --git a/dts/upstream/src/arm/ti/omap/dra76-evm.dts b/dts/upstream/src/arm/ti/omap/dra76-evm.dts
index 57868ac..cf9c3d3 100644
--- a/dts/upstream/src/arm/ti/omap/dra76-evm.dts
+++ b/dts/upstream/src/arm/ti/omap/dra76-evm.dts
@@ -533,11 +533,11 @@
};
&extcon_usb1 {
- vbus-gpio = <&pcf_lcd 14 GPIO_ACTIVE_HIGH>;
+ vbus-gpios = <&pcf_lcd 14 GPIO_ACTIVE_HIGH>;
};
&extcon_usb2 {
- vbus-gpio = <&pcf_lcd 15 GPIO_ACTIVE_HIGH>;
+ vbus-gpios = <&pcf_lcd 15 GPIO_ACTIVE_HIGH>;
};
&m_can0 {
diff --git a/dts/upstream/src/arm/ti/omap/logicpd-torpedo-37xx-devkit.dts b/dts/upstream/src/arm/ti/omap/logicpd-torpedo-37xx-devkit.dts
index 533ce7c..fbff15a 100644
--- a/dts/upstream/src/arm/ti/omap/logicpd-torpedo-37xx-devkit.dts
+++ b/dts/upstream/src/arm/ti/omap/logicpd-torpedo-37xx-devkit.dts
@@ -52,7 +52,7 @@
&uart2 {
/delete-property/dma-names;
- bluetooth {
+ bluetooth-gnss {
compatible = "ti,wl1283-st";
enable-gpios = <&gpio6 2 GPIO_ACTIVE_HIGH>; /* gpio 162 */
max-speed = <3000000>;
diff --git a/dts/upstream/src/arm/ti/omap/motorola-mapphone-common.dtsi b/dts/upstream/src/arm/ti/omap/motorola-mapphone-common.dtsi
index a2bb360..a0c53d9 100644
--- a/dts/upstream/src/arm/ti/omap/motorola-mapphone-common.dtsi
+++ b/dts/upstream/src/arm/ti/omap/motorola-mapphone-common.dtsi
@@ -6,15 +6,6 @@
#include "motorola-cpcap-mapphone.dtsi"
/ {
- chosen {
- stdout-path = &uart3;
- };
-
- aliases {
- display0 = &lcd0;
- display1 = &hdmi0;
- };
-
/*
* We seem to have only 1021 MB accessible, 1021 - 1022 is locked,
* then 1023 - 1024 seems to contain mbm.
@@ -63,46 +54,6 @@
regulator-always-on;
};
- /* FS USB Host PHY on port 1 for mdm6600 */
- fsusb1_phy: usb-phy@1 {
- compatible = "motorola,mapphone-mdm6600";
- pinctrl-0 = <&usb_mdm6600_pins>;
- pinctrl-1 = <&usb_mdm6600_sleep_pins>;
- pinctrl-names = "default", "sleep";
- enable-gpios = <&gpio3 31 GPIO_ACTIVE_LOW>; /* gpio_95 */
- power-gpios = <&gpio2 22 GPIO_ACTIVE_HIGH>; /* gpio_54 */
- reset-gpios = <&gpio2 17 GPIO_ACTIVE_HIGH>; /* gpio_49 */
- /* mode: gpio_148 gpio_149 */
- motorola,mode-gpios = <&gpio5 20 GPIO_ACTIVE_HIGH>,
- <&gpio5 21 GPIO_ACTIVE_HIGH>;
- /* cmd: gpio_103 gpio_104 gpio_142 */
- motorola,cmd-gpios = <&gpio4 7 GPIO_ACTIVE_HIGH>,
- <&gpio4 8 GPIO_ACTIVE_HIGH>,
- <&gpio5 14 GPIO_ACTIVE_HIGH>;
- /* status: gpio_52 gpio_53 gpio_55 */
- motorola,status-gpios = <&gpio2 20 GPIO_ACTIVE_HIGH>,
- <&gpio2 21 GPIO_ACTIVE_HIGH>,
- <&gpio2 23 GPIO_ACTIVE_HIGH>;
- #phy-cells = <0>;
- };
-
- /* HS USB host TLL nop-phy on port 2 for w3glte */
- hsusb2_phy: usb-phy@2 {
- compatible = "usb-nop-xceiv";
- #phy-cells = <0>;
- };
-
- /* LCD regulator from sw5 source */
- lcd_regulator: regulator-lcd {
- compatible = "regulator-fixed";
- regulator-name = "lcd";
- regulator-min-microvolt = <5050000>;
- regulator-max-microvolt = <5050000>;
- gpio = <&gpio4 0 GPIO_ACTIVE_HIGH>; /* gpio96 */
- enable-active-high;
- vin-supply = <&sw5>;
- };
-
/* This is probably coming straight from the battery.. */
wl12xx_vmmc: regulator-wl12xx {
compatible = "regulator-fixed";
@@ -133,41 +84,6 @@
dais = <&mcbsp2_port>, <&mcbsp3_port>;
};
-
- pwm8: pwm-8 {
- pinctrl-names = "default";
- pinctrl-0 = <&vibrator_direction_pin>;
-
- compatible = "ti,omap-dmtimer-pwm";
- #pwm-cells = <3>;
- ti,timers = <&timer8>;
- ti,clock-source = <0x01>;
- };
-
- pwm9: pwm-9 {
- pinctrl-names = "default";
- pinctrl-0 = <&vibrator_enable_pin>;
-
- compatible = "ti,omap-dmtimer-pwm";
- #pwm-cells = <3>;
- ti,timers = <&timer9>;
- ti,clock-source = <0x01>;
- };
-
- vibrator {
- compatible = "pwm-vibrator";
- pwms = <&pwm9 0 10000000 0>, <&pwm8 0 10000000 0>;
- pwm-names = "enable", "direction";
- direction-duty-cycle-ns = <10000000>;
- };
-
- backlight: backlight {
- compatible = "led-backlight";
-
- leds = <&backlight_led>;
- brightness-levels = <31 63 95 127 159 191 223 255>;
- default-brightness-level = <6>;
- };
};
&cpu_thermal {
@@ -197,57 +113,6 @@
status = "okay";
};
-&dsi1 {
- status = "okay";
- vdd-supply = <&vcsi>;
-
- port {
- dsi1_out_ep: endpoint {
- remote-endpoint = <&lcd0_in>;
- lanes = <0 1 2 3 4 5>;
- };
- };
-
- lcd0: panel@0 {
- compatible = "motorola,droid4-panel", "panel-dsi-cm";
- reg = <0>;
- label = "lcd0";
- vddi-supply = <&lcd_regulator>;
- reset-gpios = <&gpio4 5 GPIO_ACTIVE_HIGH>; /* gpio101 */
-
- backlight = <&backlight>;
-
- width-mm = <50>;
- height-mm = <89>;
- rotation = <90>;
-
- panel-timing {
- clock-frequency = <0>; /* Calculated by dsi */
-
- hback-porch = <2>;
- hactive = <540>;
- hfront-porch = <0>;
- hsync-len = <2>;
-
- vback-porch = <1>;
- vactive = <960>;
- vfront-porch = <0>;
- vsync-len = <1>;
-
- hsync-active = <0>;
- vsync-active = <0>;
- de-active = <1>;
- pixelclk-active = <1>;
- };
-
- port {
- lcd0_in: endpoint {
- remote-endpoint = <&dsi1_out_ep>;
- };
- };
- };
-};
-
&hdmi {
status = "okay";
pinctrl-0 = <&dss_hdmi_pins>;
@@ -262,13 +127,6 @@
};
};
-/* Battery NVRAM on 1-wire handled by w1_ds250x driver */
-&hdqw1w {
- pinctrl-0 = <&hdq_pins>;
- pinctrl-names = "default";
- ti,mode = "1w";
-};
-
&i2c1 {
tmp105@48 {
compatible = "ti,tmp105";
@@ -322,34 +180,6 @@
};
};
-&i2c2 {
- touchscreen@4a {
- compatible = "atmel,maxtouch";
- reg = <0x4a>;
- pinctrl-names = "default";
- pinctrl-0 = <&touchscreen_pins>;
-
- reset-gpios = <&gpio6 13 GPIO_ACTIVE_LOW>; /* gpio173 */
-
- /* gpio_183 with sys_nirq2 pad as wakeup */
- interrupts-extended = <&gpio6 23 IRQ_TYPE_LEVEL_LOW>,
- <&omap4_pmx_core 0x160>;
- interrupt-names = "irq", "wakeup";
- wakeup-source;
- };
-
- isl29030@44 {
- compatible = "isil,isl29030";
- reg = <0x44>;
-
- pinctrl-names = "default";
- pinctrl-0 = <&als_proximity_pins>;
-
- interrupt-parent = <&gpio6>;
- interrupts = <17 IRQ_TYPE_LEVEL_LOW>; /* gpio177 */
- };
-};
-
&omap4_pmx_core {
/* hdmi_hpd.gpio_63 */
@@ -359,13 +189,6 @@
>;
};
- hdq_pins: hdq-pins {
- pinctrl-single,pins = <
- /* 0x4a100120 hdq_sio.hdq_sio aa27 */
- OMAP4_IOPAD(0x120, PIN_INPUT | MUX_MODE0)
- >;
- };
-
/* hdmi_cec.hdmi_cec, hdmi_scl.hdmi_scl, hdmi_sda.hdmi_sda */
dss_hdmi_pins: dss-hdmi-pins {
pinctrl-single,pins = <
@@ -427,73 +250,6 @@
>;
};
- touchscreen_pins: touchscreen-pins {
- pinctrl-single,pins = <
- OMAP4_IOPAD(0x180, PIN_OUTPUT | MUX_MODE3)
- OMAP4_IOPAD(0x1a0, PIN_INPUT_PULLUP | MUX_MODE3)
- >;
- };
-
- als_proximity_pins: als-proximity-pins {
- pinctrl-single,pins = <
- OMAP4_IOPAD(0x18c, PIN_INPUT_PULLUP | MUX_MODE3)
- >;
- };
-
- usb_mdm6600_pins: usb-mdm6600-pins {
- pinctrl-single,pins = <
- /* enable 0x4a1000d8 usbb1_ulpitll_dat7.gpio_95 ag16 */
- OMAP4_IOPAD(0x0d8, PIN_INPUT | MUX_MODE3)
-
- /* power 0x4a10007c gpmc_nwp.gpio_54 c25 */
- OMAP4_IOPAD(0x07c, PIN_OUTPUT | MUX_MODE3)
-
- /* reset 0x4a100072 gpmc_a25.gpio_49 d20 */
- OMAP4_IOPAD(0x072, PIN_OUTPUT | MUX_MODE3)
-
- /* mode0/bpwake 0x4a10014e sdmmc5_dat1.gpio_148 af4 */
- OMAP4_IOPAD(0x14e, PIN_OUTPUT | MUX_MODE3)
-
- /* mode1/apwake 0x4a100150 sdmmc5_dat2.gpio_149 ag3 */
- OMAP4_IOPAD(0x150, PIN_OFF_OUTPUT_LOW | PIN_INPUT | MUX_MODE3)
-
- /* status0 0x4a10007e gpmc_clk.gpio_55 b22 */
- OMAP4_IOPAD(0x07e, PIN_INPUT | MUX_MODE3)
-
- /* status1 0x4a10007a gpmc_ncs3.gpio_53 c22 */
- OMAP4_IOPAD(0x07a, PIN_INPUT | MUX_MODE3)
-
- /* status2 0x4a100078 gpmc_ncs2.gpio_52 d21 */
- OMAP4_IOPAD(0x078, PIN_INPUT | MUX_MODE3)
-
- /* cmd0 0x4a100094 gpmc_ncs6.gpio_103 c24 */
- OMAP4_IOPAD(0x094, PIN_OUTPUT | MUX_MODE3)
-
- /* cmd1 0x4a100096 gpmc_ncs7.gpio_104 d24 */
- OMAP4_IOPAD(0x096, PIN_OUTPUT | MUX_MODE3)
-
- /* cmd2 0x4a100142 uart3_rts_sd.gpio_142 f28 */
- OMAP4_IOPAD(0x142, PIN_OUTPUT | MUX_MODE3)
- >;
- };
-
- /* Modem sleep pins to keep gpio_49 high with internal pull */
- usb_mdm6600_sleep_pins: usb-mdm6600-sleep-pins {
- pinctrl-single,pins = <
- OMAP4_IOPAD(0x0d8, PIN_INPUT | MUX_MODE3)
- OMAP4_IOPAD(0x07c, PIN_OUTPUT | MUX_MODE3)
- OMAP4_IOPAD(0x072, PIN_INPUT_PULLUP | MUX_MODE7) /* Keep gpio_49 reset high */
- OMAP4_IOPAD(0x14e, PIN_OUTPUT | MUX_MODE3)
- OMAP4_IOPAD(0x150, PIN_OFF_OUTPUT_LOW | PIN_INPUT | MUX_MODE3)
- OMAP4_IOPAD(0x07e, PIN_INPUT | MUX_MODE3)
- OMAP4_IOPAD(0x07a, PIN_INPUT | MUX_MODE3)
- OMAP4_IOPAD(0x078, PIN_INPUT | MUX_MODE3)
- OMAP4_IOPAD(0x094, PIN_OUTPUT | MUX_MODE3)
- OMAP4_IOPAD(0x096, PIN_OUTPUT | MUX_MODE3)
- OMAP4_IOPAD(0x142, PIN_OUTPUT | MUX_MODE3)
- >;
- };
-
usb_ulpi_pins: usb-ulpi-pins {
pinctrl-single,pins = <
OMAP4_IOPAD(0x196, MUX_MODE7)
@@ -601,18 +357,6 @@
OMAP4_IOPAD(0x10c, PIN_INPUT | MUX_MODE1) /* abe_mcbsp3_fsx */
>;
};
-
- vibrator_direction_pin: vibrator-direction-pins {
- pinctrl-single,pins = <
- OMAP4_IOPAD(0x1ce, PIN_OUTPUT | MUX_MODE1) /* dmtimer8_pwm_evt (gpio_27) */
- >;
- };
-
- vibrator_enable_pin: vibrator-enable-pins {
- pinctrl-single,pins = <
- OMAP4_IOPAD(0X1d0, PIN_OUTPUT | MUX_MODE1) /* dmtimer9_pwm_evt (gpio_28) */
- >;
- };
};
&omap4_pmx_wkup {
@@ -629,17 +373,6 @@
status = "disabled";
};
-/* Configure pwm clock source for timers 8 & 9 */
-&timer8 {
- assigned-clocks = <&abe_clkctrl OMAP4_TIMER8_CLKCTRL 24>;
- assigned-clock-parents = <&sys_32k_ck>;
-};
-
-&timer9 {
- assigned-clocks = <&l4_per_clkctrl OMAP4_TIMER9_CLKCTRL 24>;
- assigned-clock-parents = <&sys_32k_ck>;
-};
-
/*
* The uart1 port is wired to mdm6600 with rts and cts. The modem uses gpio_149
* for wake-up events for both the USB PHY and the UART. We can use gpio_149
@@ -672,20 +405,6 @@
};
};
-&usbhsohci {
- phys = <&fsusb1_phy>;
- phy-names = "usb";
-};
-
-&usbhsehci {
- phys = <&hsusb2_phy>;
-};
-
-&usbhshost {
- port1-mode = "ohci-phy-4pin-dpdm";
- port2-mode = "ehci-tll";
-};
-
/* Internal UTMI+ PHY used for OTG, CPCAP ULPI PHY for detection and charger */
&usb_otg_hs {
interface-type = <1>;
@@ -698,23 +417,6 @@
power = <150>;
};
-&i2c4 {
- ak8975: magnetometer@c {
- compatible = "asahi-kasei,ak8975";
- reg = <0x0c>;
-
- vdd-supply = <&vhvio>;
-
- interrupt-parent = <&gpio6>;
- interrupts = <15 IRQ_TYPE_EDGE_RISING>; /* gpio175 */
-
- rotation-matrix = "-1", "0", "0",
- "0", "1", "0",
- "0", "0", "-1";
-
- };
-};
-
&mcbsp2 {
#sound-dai-cells = <0>;
pinctrl-names = "default";
diff --git a/dts/upstream/src/arm/ti/omap/motorola-mapphone-handset.dtsi b/dts/upstream/src/arm/ti/omap/motorola-mapphone-handset.dtsi
new file mode 100644
index 0000000..f3f9ff0
--- /dev/null
+++ b/dts/upstream/src/arm/ti/omap/motorola-mapphone-handset.dtsi
@@ -0,0 +1,234 @@
+// SPDX-License-Identifier: GPL-2.0-only
+/dts-v1/;
+
+#include "motorola-mapphone-common.dtsi"
+
+/ {
+ /* FS USB Host PHY on port 1 for mdm6600 */
+ fsusb1_phy: usb-phy@1 {
+ compatible = "motorola,mapphone-mdm6600";
+ pinctrl-0 = <&usb_mdm6600_pins>;
+ pinctrl-1 = <&usb_mdm6600_sleep_pins>;
+ pinctrl-names = "default", "sleep";
+ enable-gpios = <&gpio3 31 GPIO_ACTIVE_LOW>; /* gpio_95 */
+ power-gpios = <&gpio2 22 GPIO_ACTIVE_HIGH>; /* gpio_54 */
+ reset-gpios = <&gpio2 17 GPIO_ACTIVE_HIGH>; /* gpio_49 */
+ /* mode: gpio_148 gpio_149 */
+ motorola,mode-gpios = <&gpio5 20 GPIO_ACTIVE_HIGH>,
+ <&gpio5 21 GPIO_ACTIVE_HIGH>;
+ /* cmd: gpio_103 gpio_104 gpio_142 */
+ motorola,cmd-gpios = <&gpio4 7 GPIO_ACTIVE_HIGH>,
+ <&gpio4 8 GPIO_ACTIVE_HIGH>,
+ <&gpio5 14 GPIO_ACTIVE_HIGH>;
+ /* status: gpio_52 gpio_53 gpio_55 */
+ motorola,status-gpios = <&gpio2 20 GPIO_ACTIVE_HIGH>,
+ <&gpio2 21 GPIO_ACTIVE_HIGH>,
+ <&gpio2 23 GPIO_ACTIVE_HIGH>;
+ #phy-cells = <0>;
+ };
+
+ /* HS USB host TLL nop-phy on port 2 for w3glte */
+ hsusb2_phy: usb-phy@2 {
+ compatible = "usb-nop-xceiv";
+ #phy-cells = <0>;
+ };
+
+ pwm8: pwm-8 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&vibrator_direction_pin>;
+
+ compatible = "ti,omap-dmtimer-pwm";
+ #pwm-cells = <3>;
+ ti,timers = <&timer8>;
+ ti,clock-source = <0x01>;
+ };
+
+ pwm9: pwm-9 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&vibrator_enable_pin>;
+
+ compatible = "ti,omap-dmtimer-pwm";
+ #pwm-cells = <3>;
+ ti,timers = <&timer9>;
+ ti,clock-source = <0x01>;
+ };
+
+ vibrator {
+ compatible = "pwm-vibrator";
+ pwms = <&pwm9 0 10000000 0>, <&pwm8 0 10000000 0>;
+ pwm-names = "enable", "direction";
+ direction-duty-cycle-ns = <10000000>;
+ };
+};
+
+/* Battery NVRAM on 1-wire handled by w1_ds250x driver */
+&hdqw1w {
+ pinctrl-0 = <&hdq_pins>;
+ pinctrl-names = "default";
+ ti,mode = "1w";
+};
+
+&i2c2 {
+ touchscreen@4a {
+ compatible = "atmel,maxtouch";
+ reg = <0x4a>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&touchscreen_pins>;
+
+ reset-gpios = <&gpio6 13 GPIO_ACTIVE_LOW>; /* gpio173 */
+
+ /* gpio_183 with sys_nirq2 pad as wakeup */
+ interrupts-extended = <&gpio6 23 IRQ_TYPE_LEVEL_LOW>,
+ <&omap4_pmx_core 0x160>;
+ interrupt-names = "irq", "wakeup";
+ wakeup-source;
+ };
+
+ isl29030@44 {
+ compatible = "isil,isl29030";
+ reg = <0x44>;
+
+ pinctrl-names = "default";
+ pinctrl-0 = <&als_proximity_pins>;
+
+ interrupt-parent = <&gpio6>;
+ interrupts = <17 IRQ_TYPE_LEVEL_LOW>; /* gpio177 */
+ };
+};
+
+&omap4_pmx_core {
+ hdq_pins: hdq-pins {
+ pinctrl-single,pins = <
+ /* 0x4a100120 hdq_sio.hdq_sio aa27 */
+ OMAP4_IOPAD(0x120, PIN_INPUT | MUX_MODE0)
+ >;
+ };
+
+ /* kpd_row0.gpio_178 */
+ tmp105_irq: tmp105-irq-pins {
+ pinctrl-single,pins = <
+ OMAP4_IOPAD(0x18e, PIN_INPUT_PULLUP | MUX_MODE3)
+ >;
+ };
+
+ touchscreen_pins: touchscreen-pins {
+ pinctrl-single,pins = <
+ OMAP4_IOPAD(0x180, PIN_OUTPUT | MUX_MODE3)
+ OMAP4_IOPAD(0x1a0, PIN_INPUT_PULLUP | MUX_MODE3)
+ >;
+ };
+
+ usb_mdm6600_pins: usb-mdm6600-pins {
+ pinctrl-single,pins = <
+ /* enable 0x4a1000d8 usbb1_ulpitll_dat7.gpio_95 ag16 */
+ OMAP4_IOPAD(0x0d8, PIN_INPUT | MUX_MODE3)
+
+ /* power 0x4a10007c gpmc_nwp.gpio_54 c25 */
+ OMAP4_IOPAD(0x07c, PIN_OUTPUT | MUX_MODE3)
+
+ /* reset 0x4a100072 gpmc_a25.gpio_49 d20 */
+ OMAP4_IOPAD(0x072, PIN_OUTPUT | MUX_MODE3)
+
+ /* mode0/bpwake 0x4a10014e sdmmc5_dat1.gpio_148 af4 */
+ OMAP4_IOPAD(0x14e, PIN_OUTPUT | MUX_MODE3)
+
+ /* mode1/apwake 0x4a100150 sdmmc5_dat2.gpio_149 ag3 */
+ OMAP4_IOPAD(0x150, PIN_OFF_OUTPUT_LOW | PIN_INPUT | MUX_MODE3)
+
+ /* status0 0x4a10007e gpmc_clk.gpio_55 b22 */
+ OMAP4_IOPAD(0x07e, PIN_INPUT | MUX_MODE3)
+
+ /* status1 0x4a10007a gpmc_ncs3.gpio_53 c22 */
+ OMAP4_IOPAD(0x07a, PIN_INPUT | MUX_MODE3)
+
+ /* status2 0x4a100078 gpmc_ncs2.gpio_52 d21 */
+ OMAP4_IOPAD(0x078, PIN_INPUT | MUX_MODE3)
+
+ /* cmd0 0x4a100094 gpmc_ncs6.gpio_103 c24 */
+ OMAP4_IOPAD(0x094, PIN_OUTPUT | MUX_MODE3)
+
+ /* cmd1 0x4a100096 gpmc_ncs7.gpio_104 d24 */
+ OMAP4_IOPAD(0x096, PIN_OUTPUT | MUX_MODE3)
+
+ /* cmd2 0x4a100142 uart3_rts_sd.gpio_142 f28 */
+ OMAP4_IOPAD(0x142, PIN_OUTPUT | MUX_MODE3)
+ >;
+ };
+
+ /* Modem sleep pins to keep gpio_49 high with internal pull */
+ usb_mdm6600_sleep_pins: usb-mdm6600-sleep-pins {
+ pinctrl-single,pins = <
+ OMAP4_IOPAD(0x0d8, PIN_INPUT | MUX_MODE3)
+ OMAP4_IOPAD(0x07c, PIN_OUTPUT | MUX_MODE3)
+ OMAP4_IOPAD(0x072, PIN_INPUT_PULLUP | MUX_MODE7) /* Keep gpio_49 reset high */
+ OMAP4_IOPAD(0x14e, PIN_OUTPUT | MUX_MODE3)
+ OMAP4_IOPAD(0x150, PIN_OFF_OUTPUT_LOW | PIN_INPUT | MUX_MODE3)
+ OMAP4_IOPAD(0x07e, PIN_INPUT | MUX_MODE3)
+ OMAP4_IOPAD(0x07a, PIN_INPUT | MUX_MODE3)
+ OMAP4_IOPAD(0x078, PIN_INPUT | MUX_MODE3)
+ OMAP4_IOPAD(0x094, PIN_OUTPUT | MUX_MODE3)
+ OMAP4_IOPAD(0x096, PIN_OUTPUT | MUX_MODE3)
+ OMAP4_IOPAD(0x142, PIN_OUTPUT | MUX_MODE3)
+ >;
+ };
+
+ als_proximity_pins: als-proximity-pins {
+ pinctrl-single,pins = <
+ OMAP4_IOPAD(0x18c, PIN_INPUT_PULLUP | MUX_MODE3)
+ >;
+ };
+
+ vibrator_direction_pin: vibrator-direction-pins {
+ pinctrl-single,pins = <
+ OMAP4_IOPAD(0x1ce, PIN_OUTPUT | MUX_MODE1) /* dmtimer8_pwm_evt (gpio_27) */
+ >;
+ };
+
+ vibrator_enable_pin: vibrator-enable-pins {
+ pinctrl-single,pins = <
+ OMAP4_IOPAD(0X1d0, PIN_OUTPUT | MUX_MODE1) /* dmtimer9_pwm_evt (gpio_28) */
+ >;
+ };
+};
+
+/* Configure pwm clock source for timers 8 & 9 */
+&timer8 {
+ assigned-clocks = <&abe_clkctrl OMAP4_TIMER8_CLKCTRL 24>;
+ assigned-clock-parents = <&sys_32k_ck>;
+};
+
+&timer9 {
+ assigned-clocks = <&l4_per_clkctrl OMAP4_TIMER9_CLKCTRL 24>;
+ assigned-clock-parents = <&sys_32k_ck>;
+};
+
+&usbhsohci {
+ phys = <&fsusb1_phy>;
+ phy-names = "usb";
+};
+
+&usbhsehci {
+ phys = <&hsusb2_phy>;
+};
+
+&usbhshost {
+ port1-mode = "ohci-phy-4pin-dpdm";
+ port2-mode = "ehci-tll";
+};
+
+&i2c4 {
+ ak8975: magnetometer@c {
+ compatible = "asahi-kasei,ak8975";
+ reg = <0x0c>;
+
+ vdd-supply = <&vhvio>;
+
+ interrupt-parent = <&gpio6>;
+ interrupts = <15 IRQ_TYPE_EDGE_RISING>; /* gpio175 */
+
+ rotation-matrix = "-1", "0", "0",
+ "0", "1", "0",
+ "0", "0", "-1";
+
+ };
+};
diff --git a/dts/upstream/src/arm/ti/omap/motorola-mapphone-mz607-mz617.dtsi b/dts/upstream/src/arm/ti/omap/motorola-mapphone-mz607-mz617.dtsi
new file mode 100644
index 0000000..a356b3a
--- /dev/null
+++ b/dts/upstream/src/arm/ti/omap/motorola-mapphone-mz607-mz617.dtsi
@@ -0,0 +1,21 @@
+// SPDX-License-Identifier: GPL-2.0-only
+/dts-v1/;
+
+#include "motorola-mapphone-common.dtsi"
+
+&keypad {
+ keypad,num-rows = <8>;
+ keypad,num-columns = <8>;
+ linux,keymap = <MATRIX_KEY(5, 0, KEY_VOLUMEUP)>,
+ <MATRIX_KEY(3, 0, KEY_VOLUMEDOWN)>;
+};
+
+/*
+ * On tablets, mmc1 regulator is vsimcard instead of vwlan2 in the stock kernel
+ * dtb. The regulator may not be wired even if a MMC cage is added though.
+ */
+&mmc1 {
+ vmmc-supply = <&vsimcard>;
+ bus-width = <4>;
+ cd-gpios = <&gpio6 16 GPIO_ACTIVE_LOW>; /* gpio_176 */
+};
diff --git a/dts/upstream/src/arm/ti/omap/motorola-mapphone-xt8xx.dtsi b/dts/upstream/src/arm/ti/omap/motorola-mapphone-xt8xx.dtsi
new file mode 100644
index 0000000..8b8de92
--- /dev/null
+++ b/dts/upstream/src/arm/ti/omap/motorola-mapphone-xt8xx.dtsi
@@ -0,0 +1,75 @@
+// SPDX-License-Identifier: GPL-2.0-only
+/dts-v1/;
+
+#include "motorola-mapphone-handset.dtsi"
+
+/ {
+ backlight: backlight {
+ compatible = "led-backlight";
+
+ leds = <&backlight_led>;
+ brightness-levels = <31 63 95 127 159 191 223 255>;
+ default-brightness-level = <6>;
+ };
+
+ /* LCD regulator from sw5 source */
+ lcd_regulator: regulator-lcd {
+ compatible = "regulator-fixed";
+ regulator-name = "lcd";
+ regulator-min-microvolt = <5050000>;
+ regulator-max-microvolt = <5050000>;
+ gpio = <&gpio4 0 GPIO_ACTIVE_HIGH>; /* gpio96 */
+ enable-active-high;
+ vin-supply = <&sw5>;
+ };
+};
+
+&dsi1 {
+ status = "okay";
+ vdd-supply = <&vcsi>;
+
+ port {
+ dsi1_out_ep: endpoint {
+ remote-endpoint = <&lcd0_in>;
+ lanes = <0 1 2 3 4 5>;
+ };
+ };
+
+ lcd0: panel@0 {
+ compatible = "motorola,droid4-panel", "panel-dsi-cm";
+ reg = <0>;
+ label = "lcd0";
+ vddi-supply = <&lcd_regulator>;
+ reset-gpios = <&gpio4 5 GPIO_ACTIVE_HIGH>; /* gpio101 */
+ backlight = <&backlight>;
+
+ width-mm = <50>;
+ height-mm = <89>;
+ rotation = <90>;
+
+ panel-timing {
+ clock-frequency = <0>; /* Calculated by dsi */
+
+ hback-porch = <2>;
+ hactive = <540>;
+ hfront-porch = <0>;
+ hsync-len = <2>;
+
+ vback-porch = <1>;
+ vactive = <960>;
+ vfront-porch = <0>;
+ vsync-len = <1>;
+
+ hsync-active = <0>;
+ vsync-active = <0>;
+ de-active = <1>;
+ pixelclk-active = <1>;
+ };
+
+ port {
+ lcd0_in: endpoint {
+ remote-endpoint = <&dsi1_out_ep>;
+ };
+ };
+ };
+};
diff --git a/dts/upstream/src/arm/ti/omap/omap4-droid-bionic-xt875.dts b/dts/upstream/src/arm/ti/omap/omap4-droid-bionic-xt875.dts
index ccf03a7..1d9000f 100644
--- a/dts/upstream/src/arm/ti/omap/omap4-droid-bionic-xt875.dts
+++ b/dts/upstream/src/arm/ti/omap/omap4-droid-bionic-xt875.dts
@@ -1,11 +1,20 @@
// SPDX-License-Identifier: GPL-2.0-only
/dts-v1/;
-#include "motorola-mapphone-common.dtsi"
+#include "motorola-mapphone-xt8xx.dtsi"
/ {
model = "Motorola Droid Bionic XT875";
compatible = "motorola,droid-bionic", "ti,omap4430", "ti,omap4";
+
+ chosen {
+ stdout-path = &uart3;
+ };
+
+ aliases {
+ display0 = &lcd0;
+ display1 = &hdmi0;
+ };
};
&keypad {
diff --git a/dts/upstream/src/arm/ti/omap/omap4-droid4-xt894.dts b/dts/upstream/src/arm/ti/omap/omap4-droid4-xt894.dts
index e833c21..cc3f3e1 100644
--- a/dts/upstream/src/arm/ti/omap/omap4-droid4-xt894.dts
+++ b/dts/upstream/src/arm/ti/omap/omap4-droid4-xt894.dts
@@ -1,9 +1,21 @@
// SPDX-License-Identifier: GPL-2.0-only
/dts-v1/;
-#include "motorola-mapphone-common.dtsi"
+#include "motorola-mapphone-xt8xx.dtsi"
/ {
+ model = "Motorola Droid 4 XT894";
+ compatible = "motorola,droid4", "ti,omap4430", "ti,omap4";
+
+ chosen {
+ stdout-path = &uart3;
+ };
+
+ aliases {
+ display0 = &lcd0;
+ display1 = &hdmi0;
+ };
+
gpio_keys {
compatible = "gpio-keys";
@@ -33,11 +45,6 @@
};
};
-/ {
- model = "Motorola Droid 4 XT894";
- compatible = "motorola,droid4", "ti,omap4430", "ti,omap4";
-};
-
&keypad {
keypad,num-rows = <8>;
keypad,num-columns = <8>;
diff --git a/dts/upstream/src/arm/ti/omap/omap4-epson-embt2ws.dts b/dts/upstream/src/arm/ti/omap/omap4-epson-embt2ws.dts
index 01d7838..24f7d02 100644
--- a/dts/upstream/src/arm/ti/omap/omap4-epson-embt2ws.dts
+++ b/dts/upstream/src/arm/ti/omap/omap4-epson-embt2ws.dts
@@ -51,6 +51,12 @@
regulator-name = "unknown";
};
+ wl12xx_pwrseq: wl12xx-pwrseq {
+ compatible = "mmc-pwrseq-simple";
+ clocks = <&twl 1>;
+ clock-names = "ext_clock";
+ };
+
/* regulator for wl12xx on sdio2 */
wl12xx_vmmc: wl12xx-vmmc {
pinctrl-names = "default";
@@ -74,6 +80,7 @@
twl: pmic@48 {
compatible = "ti,twl6032";
reg = <0x48>;
+ #clock-cells = <1>;
/* IRQ# = 7 */
interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>; /* IRQ_SYS_1N cascaded to gic */
interrupt-controller;
@@ -294,6 +301,7 @@
pinctrl-names = "default";
pinctrl-0 = <&wl12xx_pins>;
vmmc-supply = <&wl12xx_vmmc>;
+ mmc-pwrseq = <&wl12xx_pwrseq>;
interrupts-extended = <&wakeupgen GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH
&omap4_pmx_core 0x12e>;
non-removable;
@@ -454,10 +462,12 @@
interrupts-extended = <&wakeupgen GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH
&omap4_pmx_core OMAP4_UART2_RX>;
- /*
- * BT + GPS in WL1283 in WG7500 requiring CLK32KAUDIO of pmic
- * which does not have a driver
- */
+ bluetooth-gnss {
+ compatible = "ti,wl1283-st";
+ enable-gpios = <&gpio1 25 GPIO_ACTIVE_HIGH>; /* GPIO_25 */
+ clocks = <&twl 1>;
+ clock-names = "ext_clock";
+ };
};
&uart3 {
diff --git a/dts/upstream/src/arm/ti/omap/omap4-xyboard-mz609.dts b/dts/upstream/src/arm/ti/omap/omap4-xyboard-mz609.dts
new file mode 100644
index 0000000..762934e
--- /dev/null
+++ b/dts/upstream/src/arm/ti/omap/omap4-xyboard-mz609.dts
@@ -0,0 +1,46 @@
+// SPDX-License-Identifier: GPL-2.0-only
+/dts-v1/;
+
+#include "motorola-mapphone-mz607-mz617.dtsi"
+
+/ {
+ model = "Motorola Xyboard MZ609";
+ compatible = "motorola,xyboard-mz609", "ti,omap4430", "ti,omap4";
+
+ chosen {
+ stdout-path = &uart3;
+ };
+
+ aliases {
+ display1 = &hdmi0;
+ };
+
+ backlight: backlight {
+ compatible = "led-backlight";
+
+ leds = <&backlight_led>;
+ brightness-levels = <31 63 95 127 159 191 223 255>;
+ default-brightness-level = <6>;
+ };
+};
+
+&i2c1 {
+ led-controller@38 {
+ compatible = "ti,lm3532";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0x38>;
+
+ enable-gpios = <&gpio6 12 GPIO_ACTIVE_HIGH>;
+
+ ramp-up-us = <1024>;
+ ramp-down-us = <8193>;
+
+ backlight_led: led@0 {
+ reg = <0>;
+ led-sources = <2>;
+ ti,led-mode = <0>;
+ label = ":backlight";
+ };
+ };
+};
diff --git a/dts/upstream/src/arm/ti/omap/omap4-xyboard-mz617.dts b/dts/upstream/src/arm/ti/omap/omap4-xyboard-mz617.dts
new file mode 100644
index 0000000..b9caea3
--- /dev/null
+++ b/dts/upstream/src/arm/ti/omap/omap4-xyboard-mz617.dts
@@ -0,0 +1,17 @@
+// SPDX-License-Identifier: GPL-2.0-only
+/dts-v1/;
+
+#include "motorola-mapphone-mz607-mz617.dtsi"
+
+/ {
+ model = "Motorola Xyboard MZ617";
+ compatible = "motorola,xyboard-mz617", "ti,omap4430", "ti,omap4";
+
+ chosen {
+ stdout-path = &uart3;
+ };
+
+ aliases {
+ display1 = &hdmi0;
+ };
+};
diff --git a/dts/upstream/src/arm64/allwinner/sun50i-h618-orangepi-zero2w.dts b/dts/upstream/src/arm64/allwinner/sun50i-h618-orangepi-zero2w.dts
new file mode 100644
index 0000000..21ca197
--- /dev/null
+++ b/dts/upstream/src/arm64/allwinner/sun50i-h618-orangepi-zero2w.dts
@@ -0,0 +1,176 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (C) 2023 Arm Ltd.
+ */
+
+/dts-v1/;
+
+#include "sun50i-h616.dtsi"
+
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/interrupt-controller/arm-gic.h>
+#include <dt-bindings/leds/common.h>
+
+/ {
+ model = "OrangePi Zero 2W";
+ compatible = "xunlong,orangepi-zero2w", "allwinner,sun50i-h618";
+
+ aliases {
+ serial0 = &uart0;
+ };
+
+ chosen {
+ stdout-path = "serial0:115200n8";
+ };
+
+ leds {
+ compatible = "gpio-leds";
+
+ led-0 {
+ function = LED_FUNCTION_STATUS;
+ color = <LED_COLOR_ID_GREEN>;
+ gpios = <&pio 2 13 GPIO_ACTIVE_HIGH>; /* PC13 */
+ };
+ };
+
+ reg_vcc5v: vcc5v {
+ /* board wide 5V supply directly from the USB-C socket */
+ compatible = "regulator-fixed";
+ regulator-name = "vcc-5v";
+ regulator-min-microvolt = <5000000>;
+ regulator-max-microvolt = <5000000>;
+ regulator-always-on;
+ };
+
+ reg_vcc3v3: vcc3v3 {
+ /* SY8089 DC/DC converter */
+ compatible = "regulator-fixed";
+ regulator-name = "vcc-3v3";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ vin-supply = <®_vcc5v>;
+ regulator-always-on;
+ };
+};
+
+&ehci1 {
+ status = "okay";
+};
+
+/* USB 2 & 3 are on the FPC connector (or the exansion board) */
+
+&mmc0 {
+ cd-gpios = <&pio 5 6 GPIO_ACTIVE_LOW>; /* PF6 */
+ bus-width = <4>;
+ vmmc-supply = <®_vcc3v3>;
+ status = "okay";
+};
+
+&ohci1 {
+ status = "okay";
+};
+
+&pio {
+ vcc-pc-supply = <®_dldo1>;
+ vcc-pf-supply = <®_dldo1>; /* internally via VCC-IO */
+ vcc-pg-supply = <®_aldo1>;
+ vcc-ph-supply = <®_dldo1>; /* internally via VCC-IO */
+ vcc-pi-supply = <®_dldo1>;
+};
+
+&r_i2c {
+ status = "okay";
+
+ axp313: pmic@36 {
+ compatible = "x-powers,axp313a";
+ reg = <0x36>;
+ #interrupt-cells = <1>;
+ interrupt-controller;
+ interrupt-parent = <&pio>;
+ interrupts = <2 9 IRQ_TYPE_LEVEL_LOW>; /* PC9 */
+
+ vin1-supply = <®_vcc5v>;
+ vin2-supply = <®_vcc5v>;
+ vin3-supply = <®_vcc5v>;
+
+ regulators {
+ /* Supplies VCC-PLL and DRAM */
+ reg_aldo1: aldo1 {
+ regulator-always-on;
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-name = "vcc1v8";
+ };
+
+ /* Supplies VCC-IO, so needs to be always on. */
+ reg_dldo1: dldo1 {
+ regulator-always-on;
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-name = "vcc3v3";
+ };
+
+ reg_dcdc1: dcdc1 {
+ regulator-always-on;
+ regulator-min-microvolt = <810000>;
+ regulator-max-microvolt = <990000>;
+ regulator-name = "vdd-gpu-sys";
+ };
+
+ reg_dcdc2: dcdc2 {
+ regulator-always-on;
+ regulator-min-microvolt = <810000>;
+ regulator-max-microvolt = <1100000>;
+ regulator-name = "vdd-cpu";
+ };
+
+ reg_dcdc3: dcdc3 {
+ regulator-always-on;
+ regulator-min-microvolt = <1100000>;
+ regulator-max-microvolt = <1100000>;
+ regulator-name = "vdd-dram";
+ };
+ };
+ };
+};
+
+&spi0 {
+ status = "okay";
+ pinctrl-names = "default";
+ pinctrl-0 = <&spi0_pins>, <&spi0_cs0_pin>;
+
+ flash@0 {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ compatible = "jedec,spi-nor";
+ reg = <0>;
+ spi-max-frequency = <40000000>;
+ };
+};
+
+&uart0 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&uart0_ph_pins>;
+ status = "okay";
+};
+
+&usbotg {
+ /*
+ * PHY0 pins are connected to a USB-C socket, but a role switch
+ * is not implemented: both CC pins are pulled to GND.
+ * The VBUS pins power the device, so a fixed peripheral mode
+ * is the best choice.
+ * The board can be powered via GPIOs, in this case port0 *can*
+ * act as a host (with a cable/adapter ignoring CC), as VBUS is
+ * then provided by the GPIOs. Any user of this setup would
+ * need to adjust the DT accordingly: dr_mode set to "host",
+ * enabling OHCI0 and EHCI0.
+ */
+ dr_mode = "peripheral";
+ status = "okay";
+};
+
+&usbphy {
+ usb1_vbus-supply = <®_vcc5v>;
+ status = "okay";
+};
diff --git a/dts/upstream/src/arm64/allwinner/sun50i-h618-transpeed-8k618-t.dts b/dts/upstream/src/arm64/allwinner/sun50i-h618-transpeed-8k618-t.dts
new file mode 100644
index 0000000..8ea1fd4
--- /dev/null
+++ b/dts/upstream/src/arm64/allwinner/sun50i-h618-transpeed-8k618-t.dts
@@ -0,0 +1,161 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (C) 2023 Arm Ltd.
+ */
+
+/dts-v1/;
+
+#include "sun50i-h616.dtsi"
+
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/interrupt-controller/arm-gic.h>
+
+/ {
+ model = "Transpeed 8K618-T";
+ compatible = "transpeed,8k618-t", "allwinner,sun50i-h618";
+
+ aliases {
+ serial0 = &uart0;
+ };
+
+ chosen {
+ stdout-path = "serial0:115200n8";
+ };
+
+ reg_vcc5v: vcc5v {
+ /* board wide 5V supply directly from the DC input */
+ compatible = "regulator-fixed";
+ regulator-name = "vcc-5v";
+ regulator-min-microvolt = <5000000>;
+ regulator-max-microvolt = <5000000>;
+ regulator-always-on;
+ };
+
+ reg_vcc3v3: vcc3v3 {
+ /* discrete 3.3V regulator */
+ compatible = "regulator-fixed";
+ regulator-name = "vcc-3v3";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-always-on;
+ };
+};
+
+&ehci0 {
+ status = "okay";
+};
+
+&ehci1 {
+ status = "okay";
+};
+
+&ir {
+ status = "okay";
+};
+
+&mmc0 {
+ vmmc-supply = <®_dldo1>;
+ cd-gpios = <&pio 8 16 GPIO_ACTIVE_LOW>; /* PI16 */
+ bus-width = <4>;
+ status = "okay";
+};
+
+&mmc2 {
+ vmmc-supply = <®_dldo1>;
+ vqmmc-supply = <®_aldo1>;
+ bus-width = <8>;
+ non-removable;
+ cap-mmc-hw-reset;
+ mmc-ddr-1_8v;
+ mmc-hs200-1_8v;
+ status = "okay";
+};
+
+&ohci0 {
+ status = "okay";
+};
+
+&ohci1 {
+ status = "okay";
+};
+
+&r_i2c {
+ status = "okay";
+
+ axp313: pmic@36 {
+ compatible = "x-powers,axp313a";
+ reg = <0x36>;
+ #interrupt-cells = <1>;
+ interrupt-controller;
+
+ vin1-supply = <®_vcc5v>;
+ vin2-supply = <®_vcc5v>;
+ vin3-supply = <®_vcc5v>;
+
+ regulators {
+ reg_aldo1: aldo1 {
+ regulator-always-on;
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-name = "vcc-1v8-pll";
+ };
+
+ reg_dldo1: dldo1 {
+ regulator-always-on;
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-name = "vcc-3v3-io-mmc";
+ };
+
+ reg_dcdc1: dcdc1 {
+ regulator-always-on;
+ regulator-min-microvolt = <810000>;
+ regulator-max-microvolt = <990000>;
+ regulator-name = "vdd-gpu-sys";
+ };
+
+ reg_dcdc2: dcdc2 {
+ regulator-always-on;
+ regulator-min-microvolt = <810000>;
+ regulator-max-microvolt = <1100000>;
+ regulator-name = "vdd-cpu";
+ };
+
+ reg_dcdc3: dcdc3 {
+ regulator-always-on;
+ regulator-min-microvolt = <1360000>;
+ regulator-max-microvolt = <1360000>;
+ regulator-name = "vdd-dram";
+ };
+ };
+ };
+};
+
+&pio {
+ vcc-pc-supply = <®_aldo1>;
+ vcc-pg-supply = <®_dldo1>;
+ vcc-ph-supply = <®_dldo1>;
+ vcc-pi-supply = <®_dldo1>;
+};
+
+&uart0 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&uart0_ph_pins>;
+ status = "okay";
+};
+
+&uart1 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&uart1_pins>, <&uart1_rts_cts_pins>;
+ uart-has-rtscts;
+ status = "okay";
+};
+
+&usbotg {
+ dr_mode = "host"; /* USB A type receptable */
+ status = "okay";
+};
+
+&usbphy {
+ status = "okay";
+};
diff --git a/dts/upstream/src/arm64/altera/socfpga_stratix10.dtsi b/dts/upstream/src/arm64/altera/socfpga_stratix10.dtsi
index 439497a..072fe20 100644
--- a/dts/upstream/src/arm64/altera/socfpga_stratix10.dtsi
+++ b/dts/upstream/src/arm64/altera/socfpga_stratix10.dtsi
@@ -59,6 +59,25 @@
};
};
+ firmware {
+ svc {
+ compatible = "intel,stratix10-svc";
+ method = "smc";
+ memory-region = <&service_reserved>;
+
+ fpga_mgr: fpga-mgr {
+ compatible = "intel,stratix10-soc-fpga-mgr";
+ };
+ };
+ };
+
+ fpga-region {
+ compatible = "fpga-region";
+ #address-cells = <0x2>;
+ #size-cells = <0x2>;
+ fpga-mgr = <&fpga_mgr>;
+ };
+
pmu {
compatible = "arm,armv8-pmuv3";
interrupts = <0 170 4>,
@@ -125,7 +144,7 @@
};
};
- soc {
+ soc@0 {
#address-cells = <1>;
#size-cells = <1>;
compatible = "simple-bus";
@@ -133,13 +152,6 @@
interrupt-parent = <&intc>;
ranges = <0 0 0 0xffffffff>;
- base_fpga_region {
- #address-cells = <0x2>;
- #size-cells = <0x2>;
- compatible = "fpga-region";
- fpga-mgr = <&fpga_mgr>;
- };
-
clkmgr: clock-controller@ffd10000 {
compatible = "intel,stratix10-clkmgr";
reg = <0xffd10000 0x1000>;
@@ -510,6 +522,7 @@
resets = <&rst USB1_RESET>, <&rst USB1_OCP_RESET>;
reset-names = "dwc2", "dwc2-ecc";
clocks = <&clkmgr STRATIX10_USB_CLK>;
+ clock-names = "otg";
iommus = <&smmu 7>;
status = "disabled";
};
@@ -620,18 +633,6 @@
status = "disabled";
};
-
- firmware {
- svc {
- compatible = "intel,stratix10-svc";
- method = "smc";
- memory-region = <&service_reserved>;
-
- fpga_mgr: fpga-mgr {
- compatible = "intel,stratix10-soc-fpga-mgr";
- };
- };
- };
};
usbphy0: usbphy0 {
diff --git a/dts/upstream/src/arm64/altera/socfpga_stratix10_socdk.dts b/dts/upstream/src/arm64/altera/socfpga_stratix10_socdk.dts
index 468fcc7..26173f0 100644
--- a/dts/upstream/src/arm64/altera/socfpga_stratix10_socdk.dts
+++ b/dts/upstream/src/arm64/altera/socfpga_stratix10_socdk.dts
@@ -51,7 +51,7 @@
regulator-max-microvolt = <330000>;
};
- soc {
+ soc@0 {
eccmgr {
sdmmca-ecc@ff8c8c00 {
compatible = "altr,socfpga-s10-sdmmc-ecc",
@@ -66,14 +66,14 @@
};
&pinctrl0 {
- i2c1_pmx_func: i2c1-pmx-func {
+ i2c1_pmx_func: i2c1-pmx-func-pins {
pinctrl-single,pins = <
0x78 0x4 /* I2C1_SDA (IO6-B) PIN30SEL) */
0x7c 0x4 /* I2C1_SCL (IO7-B) PIN31SEL */
>;
};
- i2c1_pmx_func_gpio: i2c1-pmx-func-gpio {
+ i2c1_pmx_func_gpio: i2c1-pmx-func-gpio-pins {
pinctrl-single,pins = <
0x78 0x8 /* I2C1_SDA (IO6-B) PIN30SEL) */
0x7c 0x8 /* I2C1_SCL (IO7-B) PIN31SEL */
@@ -187,8 +187,6 @@
spi-max-frequency = <100000000>;
m25p,fast-read;
- cdns,page-size = <256>;
- cdns,block-size = <16>;
cdns,read-delay = <1>;
cdns,tshsl-ns = <50>;
cdns,tsd2d-ns = <50>;
diff --git a/dts/upstream/src/arm64/altera/socfpga_stratix10_socdk_nand.dts b/dts/upstream/src/arm64/altera/socfpga_stratix10_socdk_nand.dts
index 532164a..81d0e91 100644
--- a/dts/upstream/src/arm64/altera/socfpga_stratix10_socdk_nand.dts
+++ b/dts/upstream/src/arm64/altera/socfpga_stratix10_socdk_nand.dts
@@ -51,7 +51,7 @@
regulator-max-microvolt = <330000>;
};
- soc {
+ soc@0 {
eccmgr {
sdmmca-ecc@ff8c8c00 {
compatible = "altr,socfpga-s10-sdmmc-ecc",
@@ -102,7 +102,7 @@
&nand {
status = "okay";
- flash@0 {
+ nand@0 {
reg = <0>;
#address-cells = <1>;
#size-cells = <1>;
@@ -176,8 +176,6 @@
spi-max-frequency = <100000000>;
m25p,fast-read;
- cdns,page-size = <256>;
- cdns,block-size = <16>;
cdns,read-delay = <1>;
cdns,tshsl-ns = <50>;
cdns,tsd2d-ns = <50>;
diff --git a/dts/upstream/src/arm64/altera/socfpga_stratix10_swvp.dts b/dts/upstream/src/arm64/altera/socfpga_stratix10_swvp.dts
index ff413f8..0d837d3 100644
--- a/dts/upstream/src/arm64/altera/socfpga_stratix10_swvp.dts
+++ b/dts/upstream/src/arm64/altera/socfpga_stratix10_swvp.dts
@@ -80,8 +80,6 @@
&mmc {
status = "okay";
- altr,dw-mshc-ciu-div = <0x3>;
- altr,dw-mshc-sdr-timing = <0x0 0x3>;
cap-sd-highspeed;
cap-mmc-highspeed;
broken-cd;
diff --git a/dts/upstream/src/arm64/amazon/alpine-v2.dtsi b/dts/upstream/src/arm64/amazon/alpine-v2.dtsi
index dccbba6..dbf2dce 100644
--- a/dts/upstream/src/arm64/amazon/alpine-v2.dtsi
+++ b/dts/upstream/src/arm64/amazon/alpine-v2.dtsi
@@ -145,7 +145,6 @@
msix: msix@fbe00000 {
compatible = "al,alpine-msix";
reg = <0x0 0xfbe00000 0x0 0x100000>;
- interrupt-controller;
msi-controller;
al,msi-base-spi = <160>;
al,msi-num-spis = <160>;
diff --git a/dts/upstream/src/arm64/amazon/alpine-v3.dtsi b/dts/upstream/src/arm64/amazon/alpine-v3.dtsi
index 39481d7..3ea178a 100644
--- a/dts/upstream/src/arm64/amazon/alpine-v3.dtsi
+++ b/dts/upstream/src/arm64/amazon/alpine-v3.dtsi
@@ -355,7 +355,6 @@
msix: msix@fbe00000 {
compatible = "al,alpine-msix";
reg = <0x0 0xfbe00000 0x0 0x100000>;
- interrupt-controller;
msi-controller;
al,msi-base-spi = <336>;
al,msi-num-spis = <959>;
diff --git a/dts/upstream/src/arm64/amlogic/amlogic-c3.dtsi b/dts/upstream/src/arm64/amlogic/amlogic-c3.dtsi
index 998f505..2ad1f8e 100644
--- a/dts/upstream/src/arm64/amlogic/amlogic-c3.dtsi
+++ b/dts/upstream/src/arm64/amlogic/amlogic-c3.dtsi
@@ -81,6 +81,12 @@
#size-cells = <2>;
ranges = <0x0 0x0 0x0 0xfe000000 0x0 0x480000>;
+ watchdog@2100 {
+ compatible = "amlogic,c3-wdt", "amlogic,t7-wdt";
+ reg = <0x0 0x2100 0x0 0x10>;
+ clocks = <&xtal>;
+ };
+
periphs_pinctrl: pinctrl@4000 {
compatible = "amlogic,c3-periphs-pinctrl";
#address-cells = <2>;
diff --git a/dts/upstream/src/arm64/amlogic/meson-axg-jethome-jethub-j110-rev-2.dts b/dts/upstream/src/arm64/amlogic/meson-axg-jethome-jethub-j110-rev-2.dts
index 0062667..8a18ce9 100644
--- a/dts/upstream/src/arm64/amlogic/meson-axg-jethome-jethub-j110-rev-2.dts
+++ b/dts/upstream/src/arm64/amlogic/meson-axg-jethome-jethub-j110-rev-2.dts
@@ -30,8 +30,20 @@
&uart_B {
bluetooth {
compatible = "realtek,rtl8822cs-bt";
- enable-gpios = <&gpio GPIOZ_7 GPIO_ACTIVE_HIGH>;
+ enable-gpios = <&gpio GPIOZ_7 GPIO_ACTIVE_HIGH>;
host-wake-gpios = <&gpio GPIOZ_8 GPIO_ACTIVE_HIGH>;
device-wake-gpios = <&gpio GPIOZ_6 GPIO_ACTIVE_HIGH>;
};
};
+
+&i2c_AO {
+ /* EEPROM on base board */
+ eeprompd: eeprom@56 {
+ compatible = "atmel,24c64";
+ reg = <0x56>;
+ pagesize = <0x20>;
+ label = "eeprompd";
+ address-width = <0x10>;
+ vcc-supply = <&vddao_3v3>;
+ };
+};
diff --git a/dts/upstream/src/arm64/amlogic/meson-axg-jethome-jethub-j110-rev-3.dts b/dts/upstream/src/arm64/amlogic/meson-axg-jethome-jethub-j110-rev-3.dts
index c2d22b0..c356bd2 100644
--- a/dts/upstream/src/arm64/amlogic/meson-axg-jethome-jethub-j110-rev-3.dts
+++ b/dts/upstream/src/arm64/amlogic/meson-axg-jethome-jethub-j110-rev-3.dts
@@ -25,3 +25,15 @@
&sd_emmc_b {
broken-cd;/* cd-gpios = <&gpio_ao GPIOAO_3 GPIO_ACTIVE_LOW>;*/
};
+
+&i2c_AO {
+ /* EEPROM on base board */
+ eeprompd: eeprom@56 {
+ compatible = "atmel,24c64";
+ reg = <0x56>;
+ pagesize = <0x20>;
+ label = "eeprompd";
+ address-width = <0x10>;
+ vcc-supply = <&vddao_3v3>;
+ };
+};
diff --git a/dts/upstream/src/arm64/amlogic/meson-axg-s400.dts b/dts/upstream/src/arm64/amlogic/meson-axg-s400.dts
index df16eea..c890566 100644
--- a/dts/upstream/src/arm64/amlogic/meson-axg-s400.dts
+++ b/dts/upstream/src/arm64/amlogic/meson-axg-s400.dts
@@ -66,7 +66,6 @@
VDDA-supply = <&vcc_3v3>;
VDDP-supply = <&vcc_3v3>;
VDDD-supply = <&vcc_3v3>;
- status = "okay";
sound-name-prefix = "Linein";
};
@@ -75,14 +74,12 @@
compatible = "everest,es7154";
VDD-supply = <&vcc_3v3>;
PVDD-supply = <&vcc_5v>;
- status = "okay";
sound-name-prefix = "Lineout";
};
spdif_dit: audio-codec-2 {
#sound-dai-cells = <0>;
compatible = "linux,spdif-dit";
- status = "okay";
sound-name-prefix = "DIT";
};
@@ -91,14 +88,12 @@
compatible = "dmic-codec";
num-channels = <7>;
wakeup-delay-ms = <50>;
- status = "okay";
sound-name-prefix = "MIC";
};
spdif_dir: audio-codec-4 {
#sound-dai-cells = <0>;
compatible = "linux,spdif-dir";
- status = "okay";
sound-name-prefix = "DIR";
};
diff --git a/dts/upstream/src/arm64/amlogic/meson-axg.dtsi b/dts/upstream/src/arm64/amlogic/meson-axg.dtsi
index a49aa62..7e5ac9d 100644
--- a/dts/upstream/src/arm64/amlogic/meson-axg.dtsi
+++ b/dts/upstream/src/arm64/amlogic/meson-axg.dtsi
@@ -432,6 +432,27 @@
};
};
+ nand_all_pins: nand-all-pins {
+ mux {
+ groups = "emmc_nand_d0",
+ "emmc_nand_d1",
+ "emmc_nand_d2",
+ "emmc_nand_d3",
+ "emmc_nand_d4",
+ "emmc_nand_d5",
+ "emmc_nand_d6",
+ "emmc_nand_d7",
+ "nand_ce0",
+ "nand_ale",
+ "nand_cle",
+ "nand_wen_clk",
+ "nand_ren_wr";
+ function = "nand";
+ input-enable;
+ bias-pull-up;
+ };
+ };
+
emmc_ds_pins: emmc_ds {
mux {
groups = "emmc_ds";
@@ -1913,6 +1934,8 @@
reg = <0x0 0x7800 0x0 0x100>,
<0x0 0x7000 0x0 0x800>;
reg-names = "nfc", "emmc";
+ pinctrl-0 = <&nand_all_pins>;
+ pinctrl-names = "default";
#address-cells = <1>;
#size-cells = <0>;
interrupts = <GIC_SPI 34 IRQ_TYPE_EDGE_RISING>;
diff --git a/dts/upstream/src/arm64/amlogic/meson-g12a-sei510.dts b/dts/upstream/src/arm64/amlogic/meson-g12a-sei510.dts
index 0ad0c2b..4c4550d 100644
--- a/dts/upstream/src/arm64/amlogic/meson-g12a-sei510.dts
+++ b/dts/upstream/src/arm64/amlogic/meson-g12a-sei510.dts
@@ -45,7 +45,6 @@
compatible = "dmic-codec";
num-channels = <2>;
wakeup-delay-ms = <50>;
- status = "okay";
sound-name-prefix = "MIC";
};
diff --git a/dts/upstream/src/arm64/amlogic/meson-g12a-x96-max.dts b/dts/upstream/src/arm64/amlogic/meson-g12a-x96-max.dts
index 4969a76..9b55982 100644
--- a/dts/upstream/src/arm64/amlogic/meson-g12a-x96-max.dts
+++ b/dts/upstream/src/arm64/amlogic/meson-g12a-x96-max.dts
@@ -22,7 +22,6 @@
spdif_dit: audio-codec-1 {
#sound-dai-cells = <0>;
compatible = "linux,spdif-dit";
- status = "okay";
sound-name-prefix = "DIT";
};
diff --git a/dts/upstream/src/arm64/amlogic/meson-g12b-bananapi-cm4.dtsi b/dts/upstream/src/arm64/amlogic/meson-g12b-bananapi-cm4.dtsi
index 995ce10..08c33ec 100644
--- a/dts/upstream/src/arm64/amlogic/meson-g12b-bananapi-cm4.dtsi
+++ b/dts/upstream/src/arm64/amlogic/meson-g12b-bananapi-cm4.dtsi
@@ -369,7 +369,7 @@
bluetooth {
compatible = "realtek,rtl8822cs-bt";
- enable-gpios = <&gpio GPIOX_17 GPIO_ACTIVE_HIGH>;
+ enable-gpios = <&gpio GPIOX_17 GPIO_ACTIVE_HIGH>;
host-wake-gpios = <&gpio GPIOX_19 GPIO_ACTIVE_HIGH>;
device-wake-gpios = <&gpio GPIOX_18 GPIO_ACTIVE_HIGH>;
};
diff --git a/dts/upstream/src/arm64/amlogic/meson-g12b-bananapi.dtsi b/dts/upstream/src/arm64/amlogic/meson-g12b-bananapi.dtsi
index 0a6a128..4b8db87 100644
--- a/dts/upstream/src/arm64/amlogic/meson-g12b-bananapi.dtsi
+++ b/dts/upstream/src/arm64/amlogic/meson-g12b-bananapi.dtsi
@@ -487,7 +487,7 @@
bluetooth {
compatible = "realtek,rtl8822cs-bt";
- enable-gpios = <&gpio GPIOX_17 GPIO_ACTIVE_HIGH>;
+ enable-gpios = <&gpio GPIOX_17 GPIO_ACTIVE_HIGH>;
host-wake-gpios = <&gpio GPIOX_19 GPIO_ACTIVE_HIGH>;
device-wake-gpios = <&gpio GPIOX_18 GPIO_ACTIVE_HIGH>;
};
diff --git a/dts/upstream/src/arm64/amlogic/meson-g12b-gtking.dts b/dts/upstream/src/arm64/amlogic/meson-g12b-gtking.dts
index 8fc2e14..0da386c 100644
--- a/dts/upstream/src/arm64/amlogic/meson-g12b-gtking.dts
+++ b/dts/upstream/src/arm64/amlogic/meson-g12b-gtking.dts
@@ -22,7 +22,6 @@
spdif_dit: audio-codec-1 {
#sound-dai-cells = <0>;
compatible = "linux,spdif-dit";
- status = "okay";
sound-name-prefix = "DIT";
};
diff --git a/dts/upstream/src/arm64/amlogic/meson-g12b-ugoos-am6.dts b/dts/upstream/src/arm64/amlogic/meson-g12b-ugoos-am6.dts
index ce548b3..6396f19 100644
--- a/dts/upstream/src/arm64/amlogic/meson-g12b-ugoos-am6.dts
+++ b/dts/upstream/src/arm64/amlogic/meson-g12b-ugoos-am6.dts
@@ -17,7 +17,6 @@
spdif_dit: audio-codec-1 {
#sound-dai-cells = <0>;
compatible = "linux,spdif-dit";
- status = "okay";
sound-name-prefix = "DIT";
};
diff --git a/dts/upstream/src/arm64/amlogic/meson-gx-p23x-q20x.dtsi b/dts/upstream/src/arm64/amlogic/meson-gx-p23x-q20x.dtsi
index 18f7b73..e59c3c9 100644
--- a/dts/upstream/src/arm64/amlogic/meson-gx-p23x-q20x.dtsi
+++ b/dts/upstream/src/arm64/amlogic/meson-gx-p23x-q20x.dtsi
@@ -26,7 +26,6 @@
spdif_dit: audio-codec-0 {
#sound-dai-cells = <0>;
compatible = "linux,spdif-dit";
- status = "okay";
sound-name-prefix = "DIT";
};
diff --git a/dts/upstream/src/arm64/amlogic/meson-gxbb-kii-pro.dts b/dts/upstream/src/arm64/amlogic/meson-gxbb-kii-pro.dts
index e238f1f..f28452b 100644
--- a/dts/upstream/src/arm64/amlogic/meson-gxbb-kii-pro.dts
+++ b/dts/upstream/src/arm64/amlogic/meson-gxbb-kii-pro.dts
@@ -18,7 +18,6 @@
spdif_dit: audio-codec-0 {
#sound-dai-cells = <0>;
compatible = "linux,spdif-dit";
- status = "okay";
sound-name-prefix = "DIT";
};
diff --git a/dts/upstream/src/arm64/amlogic/meson-gxbb-p200.dts b/dts/upstream/src/arm64/amlogic/meson-gxbb-p200.dts
index 292c718..591455c 100644
--- a/dts/upstream/src/arm64/amlogic/meson-gxbb-p200.dts
+++ b/dts/upstream/src/arm64/amlogic/meson-gxbb-p200.dts
@@ -18,7 +18,6 @@
spdif_dit: audio-codec-0 {
#sound-dai-cells = <0>;
compatible = "linux,spdif-dit";
- status = "okay";
sound-name-prefix = "DIT";
};
diff --git a/dts/upstream/src/arm64/amlogic/meson-gxbb-vega-s95.dtsi b/dts/upstream/src/arm64/amlogic/meson-gxbb-vega-s95.dtsi
index e830308..74df325 100644
--- a/dts/upstream/src/arm64/amlogic/meson-gxbb-vega-s95.dtsi
+++ b/dts/upstream/src/arm64/amlogic/meson-gxbb-vega-s95.dtsi
@@ -21,7 +21,6 @@
spdif_dit: audio-codec-0 {
#sound-dai-cells = <0>;
compatible = "linux,spdif-dit";
- status = "okay";
sound-name-prefix = "DIT";
};
diff --git a/dts/upstream/src/arm64/amlogic/meson-gxbb-wetek-play2.dts b/dts/upstream/src/arm64/amlogic/meson-gxbb-wetek-play2.dts
index e1b74b1..376760d 100644
--- a/dts/upstream/src/arm64/amlogic/meson-gxbb-wetek-play2.dts
+++ b/dts/upstream/src/arm64/amlogic/meson-gxbb-wetek-play2.dts
@@ -17,7 +17,6 @@
spdif_dit: audio-codec-0 {
#sound-dai-cells = <0>;
compatible = "linux,spdif-dit";
- status = "okay";
sound-name-prefix = "DIT";
};
diff --git a/dts/upstream/src/arm64/amlogic/meson-gxm-nexbox-a1.dts b/dts/upstream/src/arm64/amlogic/meson-gxm-nexbox-a1.dts
index 7d525bd..ad2dd4a 100644
--- a/dts/upstream/src/arm64/amlogic/meson-gxm-nexbox-a1.dts
+++ b/dts/upstream/src/arm64/amlogic/meson-gxm-nexbox-a1.dts
@@ -28,7 +28,6 @@
spdif_dit: audio-codec-0 {
#sound-dai-cells = <0>;
compatible = "linux,spdif-dit";
- status = "okay";
sound-name-prefix = "DIT";
};
diff --git a/dts/upstream/src/arm64/amlogic/meson-gxm-rbox-pro.dts b/dts/upstream/src/arm64/amlogic/meson-gxm-rbox-pro.dts
index 50d49ae..d05dde8 100644
--- a/dts/upstream/src/arm64/amlogic/meson-gxm-rbox-pro.dts
+++ b/dts/upstream/src/arm64/amlogic/meson-gxm-rbox-pro.dts
@@ -37,7 +37,6 @@
spdif_dit: audio-codec-0 {
#sound-dai-cells = <0>;
compatible = "linux,spdif-dit";
- status = "okay";
sound-name-prefix = "DIT";
};
diff --git a/dts/upstream/src/arm64/amlogic/meson-s4-s805x2-aq222.dts b/dts/upstream/src/arm64/amlogic/meson-s4-s805x2-aq222.dts
index c1f322c..983cadd 100644
--- a/dts/upstream/src/arm64/amlogic/meson-s4-s805x2-aq222.dts
+++ b/dts/upstream/src/arm64/amlogic/meson-s4-s805x2-aq222.dts
@@ -15,7 +15,7 @@
#size-cells = <2>;
aliases {
- serial0 = &uart_B;
+ serial0 = &uart_b;
};
memory@0 {
@@ -23,9 +23,20 @@
reg = <0x0 0x0 0x0 0x40000000>;
};
+ reserved-memory {
+ #address-cells = <2>;
+ #size-cells = <2>;
+ ranges;
+
+ /* 52 MiB reserved for ARM Trusted Firmware */
+ secmon_reserved: secmon@5000000 {
+ reg = <0x0 0x05000000 0x0 0x3400000>;
+ no-map;
+ };
+ };
};
-&uart_B {
+&uart_b {
status = "okay";
};
@@ -33,4 +44,49 @@
status = "okay";
pinctrl-0 = <&remote_pins>;
pinctrl-names = "default";
+};
+
+&nand {
+ status = "okay";
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ pinctrl-0 = <&nand_pins>;
+ pinctrl-names = "default";
+
+ nand@0 {
+ reg = <0>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ nand-on-flash-bbt;
+
+ partition@0 {
+ label = "boot";
+ reg = <0x0 0x00200000>;
+ };
+ partition@200000 {
+ label = "env";
+ reg = <0x00200000 0x00400000>;
+ };
+ partition@600000 {
+ label = "system";
+ reg = <0x00600000 0x00a00000>;
+ };
+ partition@1000000 {
+ label = "rootfs";
+ reg = <0x01000000 0x03000000>;
+ };
+ partition@4000000 {
+ label = "media";
+ reg = <0x04000000 0x8000000>;
+ };
+ };
+};
+
+&spicc0 {
+ status = "okay";
+ pinctrl-names = "default";
+ pinctrl-0 = <&spicc0_pins_x>;
+ cs-gpios = <&gpio GPIOX_10 GPIO_ACTIVE_LOW>;
};
diff --git a/dts/upstream/src/arm64/amlogic/meson-s4.dtsi b/dts/upstream/src/arm64/amlogic/meson-s4.dtsi
index e0cfc54..ce90b35 100644
--- a/dts/upstream/src/arm64/amlogic/meson-s4.dtsi
+++ b/dts/upstream/src/arm64/amlogic/meson-s4.dtsi
@@ -6,6 +6,10 @@
#include <dt-bindings/interrupt-controller/irq.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/gpio/meson-s4-gpio.h>
+#include <dt-bindings/clock/amlogic,s4-pll-clkc.h>
+#include <dt-bindings/clock/amlogic,s4-peripherals-clkc.h>
+#include <dt-bindings/power/meson-s4-power.h>
/ {
cpus {
@@ -92,6 +96,44 @@
#size-cells = <2>;
ranges = <0x0 0x0 0x0 0xfe000000 0x0 0x480000>;
+ clkc_periphs: clock-controller@0 {
+ compatible = "amlogic,s4-peripherals-clkc";
+ reg = <0x0 0x0 0x0 0x49c>;
+ clocks = <&clkc_pll CLKID_FCLK_DIV2>,
+ <&clkc_pll CLKID_FCLK_DIV2P5>,
+ <&clkc_pll CLKID_FCLK_DIV3>,
+ <&clkc_pll CLKID_FCLK_DIV4>,
+ <&clkc_pll CLKID_FCLK_DIV5>,
+ <&clkc_pll CLKID_FCLK_DIV7>,
+ <&clkc_pll CLKID_HIFI_PLL>,
+ <&clkc_pll CLKID_GP0_PLL>,
+ <&clkc_pll CLKID_MPLL0>,
+ <&clkc_pll CLKID_MPLL1>,
+ <&clkc_pll CLKID_MPLL2>,
+ <&clkc_pll CLKID_MPLL3>,
+ <&clkc_pll CLKID_HDMI_PLL>,
+ <&xtal>;
+ clock-names = "fclk_div2", "fclk_div2p5", "fclk_div3",
+ "fclk_div4", "fclk_div5", "fclk_div7",
+ "hifi_pll", "gp0_pll", "mpll0", "mpll1",
+ "mpll2", "mpll3", "hdmi_pll", "xtal";
+ #clock-cells = <1>;
+ };
+
+ clkc_pll: clock-controller@8000 {
+ compatible = "amlogic,s4-pll-clkc";
+ reg = <0x0 0x8000 0x0 0x1e8>;
+ clocks = <&xtal>;
+ clock-names = "xtal";
+ #clock-cells = <1>;
+ };
+
+ watchdog@2100 {
+ compatible = "amlogic,s4-wdt", "amlogic,t7-wdt";
+ reg = <0x0 0x2100 0x0 0x10>;
+ clocks = <&xtal>;
+ };
+
periphs_pinctrl: pinctrl@4000 {
compatible = "amlogic,meson-s4-periphs-pinctrl";
#address-cells = <2>;
@@ -114,6 +156,187 @@
bias-disable;
};
};
+
+ i2c0_pins1: i2c0-pins1 {
+ mux {
+ groups = "i2c0_sda",
+ "i2c0_scl";
+ function = "i2c0";
+ drive-strength-microamp = <3000>;
+ bias-disable;
+ };
+ };
+
+ i2c1_pins1: i2c1-pins1 {
+ mux {
+ groups = "i2c1_sda_c",
+ "i2c1_scl_c";
+ function = "i2c1";
+ drive-strength-microamp = <3000>;
+ bias-disable;
+ };
+ };
+
+ i2c1_pins2: i2c1-pins2 {
+ mux {
+ groups = "i2c1_sda_d",
+ "i2c1_scl_d";
+ function = "i2c1";
+ drive-strength-microamp = <3000>;
+ bias-disable;
+ };
+ };
+
+ i2c1_pins3: i2c1-pins3 {
+ mux {
+ groups = "i2c1_sda_h",
+ "i2c1_scl_h";
+ function = "i2c1";
+ drive-strength-microamp = <3000>;
+ bias-disable;
+ };
+ };
+
+ i2c1_pins4: i2c1-pins4 {
+ mux {
+ groups = "i2c1_sda_x",
+ "i2c1_scl_x";
+ function = "i2c1";
+ drive-strength-microamp = <3000>;
+ bias-disable;
+ };
+ };
+
+ i2c2_pins1: i2c2-pins1 {
+ mux {
+ groups = "i2c2_sda_d",
+ "i2c2_scl_d";
+ function = "i2c2";
+ drive-strength-microamp = <3000>;
+ bias-disable;
+ };
+ };
+
+ i2c2_pins2: i2c2-pins2 {
+ mux {
+ groups = "i2c2_sda_h8",
+ "i2c2_scl_h9";
+ function = "i2c2";
+ drive-strength-microamp = <3000>;
+ bias-disable;
+ };
+ };
+
+ i2c2_pins3: i2c2-pins3 {
+ mux {
+ groups = "i2c2_sda_h0",
+ "i2c2_scl_h1";
+ function = "i2c2";
+ drive-strength-microamp = <3000>;
+ bias-disable;
+ };
+ };
+
+ i2c3_pins1: i2c3-pins1 {
+ mux {
+ groups = "i2c3_sda_x",
+ "i2c3_scl_x";
+ function = "i2c3";
+ drive-strength-microamp = <3000>;
+ bias-disable;
+ };
+ };
+
+ i2c3_pins2: i2c3-pins2 {
+ mux {
+ groups = "i2c3_sda_z",
+ "i2c3_scl_z";
+ function = "i2c3";
+ drive-strength-microamp = <3000>;
+ bias-disable;
+ };
+ };
+
+ i2c4_pins1: i2c4-pins1 {
+ mux {
+ groups = "i2c4_sda_c",
+ "i2c4_scl_c";
+ function = "i2c4";
+ drive-strength-microamp = <3000>;
+ bias-disable;
+ };
+ };
+
+ i2c4_pins2: i2c4-pins2 {
+ mux {
+ groups = "i2c4_sda_d",
+ "i2c4_scl_d";
+ function = "i2c4";
+ drive-strength-microamp = <3000>;
+ bias-disable;
+ };
+ };
+
+ i2c4_pins3: i2c4-pins3 {
+ mux {
+ groups = "i2c4_sda_z",
+ "i2c4_scl_z";
+ function = "i2c4";
+ drive-strength-microamp = <3000>;
+ bias-disable;
+ };
+ };
+
+ nand_pins: nand-pins {
+ mux {
+ groups = "emmc_nand_d0",
+ "emmc_nand_d1",
+ "emmc_nand_d2",
+ "emmc_nand_d3",
+ "emmc_nand_d4",
+ "emmc_nand_d5",
+ "emmc_nand_d6",
+ "emmc_nand_d7",
+ "nand_ce0",
+ "nand_ale",
+ "nand_cle",
+ "nand_wen_clk",
+ "nand_ren_wr";
+ function = "nand";
+ input-enable;
+ };
+ };
+
+ spicc0_pins_x: spicc0-pins_x {
+ mux {
+ groups = "spi_a_mosi_x",
+ "spi_a_miso_x",
+ "spi_a_clk_x";
+ function = "spi_a";
+ drive-strength-microamp = <3000>;
+ };
+ };
+
+ spicc0_pins_h: spicc0-pins-h {
+ mux {
+ groups = "spi_a_mosi_h",
+ "spi_a_miso_h",
+ "spi_a_clk_h";
+ function = "spi_a";
+ drive-strength-microamp = <3000>;
+ };
+ };
+
+ spicc0_pins_z: spicc0-pins-z {
+ mux {
+ groups = "spi_a_mosi_z",
+ "spi_a_miso_z",
+ "spi_a_clk_z";
+ function = "spi_a";
+ drive-strength-microamp = <3000>;
+ };
+ };
+
};
gpio_intc: interrupt-controller@4080 {
@@ -126,14 +349,120 @@
<10 11 12 13 14 15 16 17 18 19 20 21>;
};
+ eth_phy: mdio-multiplexer@28000 {
+ compatible = "amlogic,g12a-mdio-mux";
+ reg = <0x0 0x28000 0x0 0xa4>;
+
+ #address-cells = <1>;
+ #size-cells = <0>;
+ clocks = <&clkc_periphs CLKID_ETHPHY>,
+ <&xtal>,
+ <&clkc_pll CLKID_MPLL_50M>;
+ clock-names = "pclk", "clkin0", "clkin1";
+ mdio-parent-bus = <&mdio0>;
+
+ ext_mdio: mdio@0 {
+ reg = <0>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+
+ int_mdio: mdio@1 {
+ reg = <1>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ internal_ephy: ethernet-phy@8 {
+ compatible = "ethernet-phy-id0180.3301",
+ "ethernet-phy-ieee802.3-c22";
+ interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>;
+ reg = <8>;
+ max-speed = <100>;
+ };
+ };
+ };
+
+ spicc0: spi@50000 {
+ compatible = "amlogic,meson-g12a-spicc";
+ reg = <0x0 0x50000 0x0 0x44>;
+ interrupts = <GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&clkc_periphs CLKID_SPICC0>,
+ <&clkc_periphs CLKID_SPICC0_EN>;
+ clock-names = "core", "pclk";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+ };
+
+ i2c0: i2c@66000 {
+ compatible = "amlogic,meson-axg-i2c";
+ reg = <0x0 0x66000 0x0 0x20>;
+ interrupts = <GIC_SPI 160 IRQ_TYPE_EDGE_RISING>;
+ clocks = <&clkc_periphs CLKID_I2C_M_A>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+ };
+
+ i2c1: i2c@68000 {
+ compatible = "amlogic,meson-axg-i2c";
+ reg = <0x0 0x68000 0x0 0x20>;
+ interrupts = <GIC_SPI 161 IRQ_TYPE_EDGE_RISING>;
+ clocks = <&clkc_periphs CLKID_I2C_M_B>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+ };
+
- uart_B: serial@7a000 {
+ i2c2: i2c@6a000 {
+ compatible = "amlogic,meson-axg-i2c";
+ reg = <0x0 0x6a000 0x0 0x20>;
+ interrupts = <GIC_SPI 162 IRQ_TYPE_EDGE_RISING>;
+ clocks = <&clkc_periphs CLKID_I2C_M_C>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+ };
+
+ i2c3: i2c@6c000 {
+ compatible = "amlogic,meson-axg-i2c";
+ reg = <0x0 0x6c000 0x0 0x20>;
+ interrupts = <GIC_SPI 163 IRQ_TYPE_EDGE_RISING>;
+ clocks = <&clkc_periphs CLKID_I2C_M_D>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+ };
+
+ i2c4: i2c@6e000 {
+ compatible = "amlogic,meson-axg-i2c";
+ reg = <0x0 0x6e000 0x0 0x20>;
+ interrupts = <GIC_SPI 164 IRQ_TYPE_EDGE_RISING>;
+ clocks = <&clkc_periphs CLKID_I2C_M_E>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+ };
+
+ nand: nand-controller@8c800 {
+ compatible = "amlogic,meson-axg-nfc";
+ reg = <0x0 0x8c800 0x0 0x100>, <0x0 0x8c000 0x0 0x4>;
+ reg-names = "nfc", "emmc";
+ interrupts = <GIC_SPI 175 IRQ_TYPE_EDGE_RISING>;
+ clocks = <&clkc_periphs CLKID_SD_EMMC_C>,
+ <&clkc_pll CLKID_FCLK_DIV2>;
+ clock-names = "core", "device";
+ status = "disabled";
+ };
+
+ uart_b: serial@7a000 {
compatible = "amlogic,meson-s4-uart",
"amlogic,meson-ao-uart";
reg = <0x0 0x7a000 0x0 0x18>;
interrupts = <GIC_SPI 169 IRQ_TYPE_EDGE_RISING>;
- status = "disabled";
- clocks = <&xtal>, <&xtal>, <&xtal>;
+ clocks = <&xtal>, <&clkc_periphs CLKID_UART_B>, <&xtal>;
clock-names = "xtal", "pclk", "baud";
+ status = "disabled";
};
reset: reset-controller@2000 {
@@ -154,5 +483,30 @@
reg = <0x0 0x440788 0x0 0x0c>;
};
};
+
+ ethmac: ethernet@fdc00000 {
+ compatible = "amlogic,meson-axg-dwmac",
+ "snps,dwmac-3.70a",
+ "snps,dwmac";
+ reg = <0x0 0xfdc00000 0x0 0x10000>,
+ <0x0 0xfe024000 0x0 0x8>;
+
+ interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "macirq";
+ power-domains = <&pwrc PWRC_S4_ETH_ID>;
+ clocks = <&clkc_periphs CLKID_ETH>,
+ <&clkc_pll CLKID_FCLK_DIV2>,
+ <&clkc_pll CLKID_MPLL2>;
+ clock-names = "stmmaceth", "clkin0", "clkin1";
+ rx-fifo-depth = <4096>;
+ tx-fifo-depth = <2048>;
+ status = "disabled";
+
+ mdio0: mdio {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ compatible = "snps,dwmac-mdio";
+ };
+ };
};
};
diff --git a/dts/upstream/src/arm64/amlogic/meson-sm1-sei610.dts b/dts/upstream/src/arm64/amlogic/meson-sm1-sei610.dts
index 095579c..1099320 100644
--- a/dts/upstream/src/arm64/amlogic/meson-sm1-sei610.dts
+++ b/dts/upstream/src/arm64/amlogic/meson-sm1-sei610.dts
@@ -32,7 +32,6 @@
compatible = "dmic-codec";
num-channels = <2>;
wakeup-delay-ms = <50>;
- status = "okay";
sound-name-prefix = "MIC";
};
diff --git a/dts/upstream/src/arm64/arm/juno-base.dtsi b/dts/upstream/src/arm64/arm/juno-base.dtsi
index 8b4d280..b897f55 100644
--- a/dts/upstream/src/arm64/arm/juno-base.dtsi
+++ b/dts/upstream/src/arm64/arm/juno-base.dtsi
@@ -747,7 +747,7 @@
};
thermal-zones {
- pmic {
+ pmic-thermal {
polling-delay = <1000>;
polling-delay-passive = <100>;
thermal-sensors = <&scpi_sensors0 0>;
@@ -760,7 +760,7 @@
};
};
- soc {
+ soc-thermal {
polling-delay = <1000>;
polling-delay-passive = <100>;
thermal-sensors = <&scpi_sensors0 3>;
@@ -773,28 +773,28 @@
};
};
- big_cluster_thermal_zone: big-cluster {
+ big_cluster_thermal_zone: big-cluster-thermal {
polling-delay = <1000>;
polling-delay-passive = <100>;
thermal-sensors = <&scpi_sensors0 21>;
status = "disabled";
};
- little_cluster_thermal_zone: little-cluster {
+ little_cluster_thermal_zone: little-cluster-thermal {
polling-delay = <1000>;
polling-delay-passive = <100>;
thermal-sensors = <&scpi_sensors0 22>;
status = "disabled";
};
- gpu0_thermal_zone: gpu0 {
+ gpu0_thermal_zone: gpu0-thermal {
polling-delay = <1000>;
polling-delay-passive = <100>;
thermal-sensors = <&scpi_sensors0 23>;
status = "disabled";
};
- gpu1_thermal_zone: gpu1 {
+ gpu1_thermal_zone: gpu1-thermal {
polling-delay = <1000>;
polling-delay-passive = <100>;
thermal-sensors = <&scpi_sensors0 24>;
diff --git a/dts/upstream/src/arm64/arm/juno-scmi.dtsi b/dts/upstream/src/arm64/arm/juno-scmi.dtsi
index ec85cd2..31929e2 100644
--- a/dts/upstream/src/arm64/arm/juno-scmi.dtsi
+++ b/dts/upstream/src/arm64/arm/juno-scmi.dtsi
@@ -76,27 +76,27 @@
};
thermal-zones {
- pmic {
+ pmic-thermal {
thermal-sensors = <&scmi_sensors0 0>;
};
- soc {
+ soc-thermal {
thermal-sensors = <&scmi_sensors0 3>;
};
- big-cluster {
+ big-cluster-thermal {
thermal-sensors = <&scmi_sensors0 21>;
};
- little-cluster {
+ little-cluster-thermal {
thermal-sensors = <&scmi_sensors0 22>;
};
- gpu0 {
+ gpu0-thermal {
thermal-sensors = <&scmi_sensors0 23>;
};
- gpu1 {
+ gpu1-thermal {
thermal-sensors = <&scmi_sensors0 24>;
};
};
diff --git a/dts/upstream/src/arm64/broadcom/northstar2/ns2.dtsi b/dts/upstream/src/arm64/broadcom/northstar2/ns2.dtsi
index 9dcd25e..896d1f3 100644
--- a/dts/upstream/src/arm64/broadcom/northstar2/ns2.dtsi
+++ b/dts/upstream/src/arm64/broadcom/northstar2/ns2.dtsi
@@ -586,6 +586,7 @@
#gpio-cells = <2>;
gpio-controller;
interrupt-controller;
+ #interrupt-cells = <2>;
interrupts = <GIC_SPI 400 IRQ_TYPE_LEVEL_HIGH>;
};
diff --git a/dts/upstream/src/arm64/broadcom/stingray/stingray.dtsi b/dts/upstream/src/arm64/broadcom/stingray/stingray.dtsi
index f049687..d8516ec 100644
--- a/dts/upstream/src/arm64/broadcom/stingray/stingray.dtsi
+++ b/dts/upstream/src/arm64/broadcom/stingray/stingray.dtsi
@@ -450,6 +450,7 @@
#gpio-cells = <2>;
gpio-controller;
interrupt-controller;
+ #interrupt-cells = <2>;
interrupts = <GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH>;
gpio-ranges = <&pinmux 0 0 16>,
<&pinmux 16 71 2>,
diff --git a/dts/upstream/src/arm64/exynos/exynos5433.dtsi b/dts/upstream/src/arm64/exynos/exynos5433.dtsi
index 91ae046..7fbbec0 100644
--- a/dts/upstream/src/arm64/exynos/exynos5433.dtsi
+++ b/dts/upstream/src/arm64/exynos/exynos5433.dtsi
@@ -361,7 +361,8 @@
ranges = <0x0 0x0 0x0 0x18000000>;
chipid@10000000 {
- compatible = "samsung,exynos4210-chipid";
+ compatible = "samsung,exynos5433-chipid",
+ "samsung,exynos4210-chipid";
reg = <0x10000000 0x100>;
};
@@ -850,7 +851,8 @@
reg = <0x10580000 0x1a20>, <0x11090000 0x100>;
wakeup-interrupt-controller {
- compatible = "samsung,exynos7-wakeup-eint";
+ compatible = "samsung,exynos5433-wakeup-eint",
+ "samsung,exynos7-wakeup-eint";
interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
};
};
@@ -1546,7 +1548,7 @@
};
adc: adc@14d10000 {
- compatible = "samsung,exynos7-adc";
+ compatible = "samsung,exynos5433-adc", "samsung,exynos7-adc";
reg = <0x14d10000 0x100>;
interrupts = <GIC_SPI 438 IRQ_TYPE_LEVEL_HIGH>;
clock-names = "adc";
@@ -1556,7 +1558,7 @@
};
i2s1: i2s@14d60000 {
- compatible = "samsung,exynos7-i2s";
+ compatible = "samsung,exynos5433-i2s", "samsung,exynos7-i2s";
reg = <0x14d60000 0x100>;
dmas = <&pdma0 31>, <&pdma0 30>;
dma-names = "tx", "rx";
@@ -1571,7 +1573,7 @@
};
pwm: pwm@14dd0000 {
- compatible = "samsung,exynos4210-pwm";
+ compatible = "samsung,exynos5433-pwm", "samsung,exynos4210-pwm";
reg = <0x14dd0000 0x100>;
interrupts = <GIC_SPI 416 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 417 IRQ_TYPE_LEVEL_HIGH>,
@@ -1586,7 +1588,8 @@
};
hsi2c_0: i2c@14e40000 {
- compatible = "samsung,exynos7-hsi2c";
+ compatible = "samsung,exynos5433-hsi2c",
+ "samsung,exynos7-hsi2c";
reg = <0x14e40000 0x1000>;
interrupts = <GIC_SPI 428 IRQ_TYPE_LEVEL_HIGH>;
#address-cells = <1>;
@@ -1599,7 +1602,8 @@
};
hsi2c_1: i2c@14e50000 {
- compatible = "samsung,exynos7-hsi2c";
+ compatible = "samsung,exynos5433-hsi2c",
+ "samsung,exynos7-hsi2c";
reg = <0x14e50000 0x1000>;
interrupts = <GIC_SPI 429 IRQ_TYPE_LEVEL_HIGH>;
#address-cells = <1>;
@@ -1612,7 +1616,8 @@
};
hsi2c_2: i2c@14e60000 {
- compatible = "samsung,exynos7-hsi2c";
+ compatible = "samsung,exynos5433-hsi2c",
+ "samsung,exynos7-hsi2c";
reg = <0x14e60000 0x1000>;
interrupts = <GIC_SPI 430 IRQ_TYPE_LEVEL_HIGH>;
#address-cells = <1>;
@@ -1625,7 +1630,8 @@
};
hsi2c_3: i2c@14e70000 {
- compatible = "samsung,exynos7-hsi2c";
+ compatible = "samsung,exynos5433-hsi2c",
+ "samsung,exynos7-hsi2c";
reg = <0x14e70000 0x1000>;
interrupts = <GIC_SPI 431 IRQ_TYPE_LEVEL_HIGH>;
#address-cells = <1>;
@@ -1638,7 +1644,8 @@
};
hsi2c_4: i2c@14ec0000 {
- compatible = "samsung,exynos7-hsi2c";
+ compatible = "samsung,exynos5433-hsi2c",
+ "samsung,exynos7-hsi2c";
reg = <0x14ec0000 0x1000>;
interrupts = <GIC_SPI 424 IRQ_TYPE_LEVEL_HIGH>;
#address-cells = <1>;
@@ -1651,7 +1658,8 @@
};
hsi2c_5: i2c@14ed0000 {
- compatible = "samsung,exynos7-hsi2c";
+ compatible = "samsung,exynos5433-hsi2c",
+ "samsung,exynos7-hsi2c";
reg = <0x14ed0000 0x1000>;
interrupts = <GIC_SPI 425 IRQ_TYPE_LEVEL_HIGH>;
#address-cells = <1>;
@@ -1664,7 +1672,8 @@
};
hsi2c_6: i2c@14ee0000 {
- compatible = "samsung,exynos7-hsi2c";
+ compatible = "samsung,exynos5433-hsi2c",
+ "samsung,exynos7-hsi2c";
reg = <0x14ee0000 0x1000>;
interrupts = <GIC_SPI 426 IRQ_TYPE_LEVEL_HIGH>;
#address-cells = <1>;
@@ -1677,7 +1686,8 @@
};
hsi2c_7: i2c@14ef0000 {
- compatible = "samsung,exynos7-hsi2c";
+ compatible = "samsung,exynos5433-hsi2c",
+ "samsung,exynos7-hsi2c";
reg = <0x14ef0000 0x1000>;
interrupts = <GIC_SPI 427 IRQ_TYPE_LEVEL_HIGH>;
#address-cells = <1>;
@@ -1690,7 +1700,8 @@
};
hsi2c_8: i2c@14d90000 {
- compatible = "samsung,exynos7-hsi2c";
+ compatible = "samsung,exynos5433-hsi2c",
+ "samsung,exynos7-hsi2c";
reg = <0x14d90000 0x1000>;
interrupts = <GIC_SPI 443 IRQ_TYPE_LEVEL_HIGH>;
#address-cells = <1>;
@@ -1703,7 +1714,8 @@
};
hsi2c_9: i2c@14da0000 {
- compatible = "samsung,exynos7-hsi2c";
+ compatible = "samsung,exynos5433-hsi2c",
+ "samsung,exynos7-hsi2c";
reg = <0x14da0000 0x1000>;
interrupts = <GIC_SPI 444 IRQ_TYPE_LEVEL_HIGH>;
#address-cells = <1>;
@@ -1716,7 +1728,8 @@
};
hsi2c_10: i2c@14de0000 {
- compatible = "samsung,exynos7-hsi2c";
+ compatible = "samsung,exynos5433-hsi2c",
+ "samsung,exynos7-hsi2c";
reg = <0x14de0000 0x1000>;
interrupts = <GIC_SPI 445 IRQ_TYPE_LEVEL_HIGH>;
#address-cells = <1>;
@@ -1729,7 +1742,8 @@
};
hsi2c_11: i2c@14df0000 {
- compatible = "samsung,exynos7-hsi2c";
+ compatible = "samsung,exynos5433-hsi2c",
+ "samsung,exynos7-hsi2c";
reg = <0x14df0000 0x1000>;
interrupts = <GIC_SPI 446 IRQ_TYPE_LEVEL_HIGH>;
#address-cells = <1>;
@@ -1820,7 +1834,8 @@
};
mshc_0: mmc@15540000 {
- compatible = "samsung,exynos7-dw-mshc-smu";
+ compatible = "samsung,exynos5433-dw-mshc-smu",
+ "samsung,exynos7-dw-mshc-smu";
interrupts = <GIC_SPI 225 IRQ_TYPE_LEVEL_HIGH>;
#address-cells = <1>;
#size-cells = <0>;
@@ -1833,7 +1848,8 @@
};
mshc_1: mmc@15550000 {
- compatible = "samsung,exynos7-dw-mshc-smu";
+ compatible = "samsung,exynos5433-dw-mshc-smu",
+ "samsung,exynos7-dw-mshc-smu";
interrupts = <GIC_SPI 226 IRQ_TYPE_LEVEL_HIGH>;
#address-cells = <1>;
#size-cells = <0>;
@@ -1846,7 +1862,8 @@
};
mshc_2: mmc@15560000 {
- compatible = "samsung,exynos7-dw-mshc-smu";
+ compatible = "samsung,exynos5433-dw-mshc-smu",
+ "samsung,exynos7-dw-mshc-smu";
interrupts = <GIC_SPI 227 IRQ_TYPE_LEVEL_HIGH>;
#address-cells = <1>;
#size-cells = <0>;
@@ -1897,7 +1914,8 @@
};
i2s0: i2s@11440000 {
- compatible = "samsung,exynos7-i2s";
+ compatible = "samsung,exynos5433-i2s",
+ "samsung,exynos7-i2s";
reg = <0x11440000 0x100>;
dmas = <&adma 0>, <&adma 2>;
dma-names = "tx", "rx";
diff --git a/dts/upstream/src/arm64/exynos/exynos7.dtsi b/dts/upstream/src/arm64/exynos/exynos7.dtsi
index 6ed80dd..9cb6bd6 100644
--- a/dts/upstream/src/arm64/exynos/exynos7.dtsi
+++ b/dts/upstream/src/arm64/exynos/exynos7.dtsi
@@ -128,7 +128,8 @@
ranges = <0 0 0 0x18000000>;
chipid@10000000 {
- compatible = "samsung,exynos4210-chipid";
+ compatible = "samsung,exynos7-chipid",
+ "samsung,exynos4210-chipid";
reg = <0x10000000 0x100>;
};
@@ -279,7 +280,7 @@
};
serial_0: serial@13630000 {
- compatible = "samsung,exynos4210-uart";
+ compatible = "samsung,exynos7-uart", "samsung,exynos4210-uart";
reg = <0x13630000 0x100>;
interrupts = <GIC_SPI 440 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clock_peric0 PCLK_UART0>,
@@ -289,7 +290,7 @@
};
serial_1: serial@14c20000 {
- compatible = "samsung,exynos4210-uart";
+ compatible = "samsung,exynos7-uart", "samsung,exynos4210-uart";
reg = <0x14c20000 0x100>;
interrupts = <GIC_SPI 456 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clock_peric1 PCLK_UART1>,
@@ -299,7 +300,7 @@
};
serial_2: serial@14c30000 {
- compatible = "samsung,exynos4210-uart";
+ compatible = "samsung,exynos7-uart", "samsung,exynos4210-uart";
reg = <0x14c30000 0x100>;
interrupts = <GIC_SPI 457 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clock_peric1 PCLK_UART2>,
@@ -309,7 +310,7 @@
};
serial_3: serial@14c40000 {
- compatible = "samsung,exynos4210-uart";
+ compatible = "samsung,exynos7-uart", "samsung,exynos4210-uart";
reg = <0x14c40000 0x100>;
interrupts = <GIC_SPI 458 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clock_peric1 PCLK_UART3>,
@@ -539,7 +540,7 @@
};
rtc: rtc@10590000 {
- compatible = "samsung,s3c6410-rtc";
+ compatible = "samsung,exynos7-rtc", "samsung,s3c6410-rtc";
reg = <0x10590000 0x100>;
interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>;
@@ -559,7 +560,8 @@
};
gpu: gpu@14ac0000 {
- compatible = "samsung,exynos5433-mali", "arm,mali-t760";
+ compatible = "samsung,exynos7-mali",
+ "samsung,exynos5433-mali", "arm,mali-t760";
reg = <0x14ac0000 0x5000>;
interrupts = <GIC_SPI 241 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 242 IRQ_TYPE_LEVEL_HIGH>,
@@ -619,7 +621,7 @@
};
pwm: pwm@136c0000 {
- compatible = "samsung,exynos4210-pwm";
+ compatible = "samsung,exynos7-pwm", "samsung,exynos4210-pwm";
reg = <0x136c0000 0x100>;
interrupts = <GIC_SPI 449 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 450 IRQ_TYPE_LEVEL_HIGH>,
diff --git a/dts/upstream/src/arm64/exynos/exynos7885.dtsi b/dts/upstream/src/arm64/exynos/exynos7885.dtsi
index d69fc23..008228f 100644
--- a/dts/upstream/src/arm64/exynos/exynos7885.dtsi
+++ b/dts/upstream/src/arm64/exynos/exynos7885.dtsi
@@ -172,7 +172,8 @@
ranges = <0x0 0x0 0x0 0x20000000>;
chipid@10000000 {
- compatible = "samsung,exynos850-chipid";
+ compatible = "samsung,exynos7885-chipid",
+ "samsung,exynos850-chipid";
reg = <0x10000000 0x24>;
};
@@ -264,7 +265,8 @@
reg = <0x11cb0000 0x1000>;
wakeup-interrupt-controller {
- compatible = "samsung,exynos7-wakeup-eint";
+ compatible = "samsung,exynos7885-wakeup-eint",
+ "samsung,exynos7-wakeup-eint";
interrupt-parent = <&gic>;
interrupts = <GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>;
};
@@ -289,12 +291,14 @@
};
pmu_system_controller: system-controller@11c80000 {
- compatible = "samsung,exynos7-pmu", "syscon";
+ compatible = "samsung,exynos7885-pmu",
+ "samsung,exynos7-pmu", "syscon";
reg = <0x11c80000 0x10000>;
};
mmc_0: mmc@13500000 {
- compatible = "samsung,exynos7-dw-mshc-smu";
+ compatible = "samsung,exynos7885-dw-mshc-smu",
+ "samsung,exynos7-dw-mshc-smu";
reg = <0x13500000 0x2000>;
interrupts = <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>;
#address-cells = <1>;
@@ -307,7 +311,8 @@
};
serial_0: serial@13800000 {
- compatible = "samsung,exynos5433-uart";
+ compatible = "samsung,exynos7885-uart",
+ "samsung,exynos5433-uart";
reg = <0x13800000 0x100>;
interrupts = <GIC_SPI 246 IRQ_TYPE_LEVEL_HIGH>;
pinctrl-names = "default";
@@ -320,7 +325,8 @@
};
serial_1: serial@13810000 {
- compatible = "samsung,exynos5433-uart";
+ compatible = "samsung,exynos7885-uart",
+ "samsung,exynos5433-uart";
reg = <0x13810000 0x100>;
interrupts = <GIC_SPI 247 IRQ_TYPE_LEVEL_HIGH>;
pinctrl-names = "default";
@@ -333,7 +339,8 @@
};
serial_2: serial@13820000 {
- compatible = "samsung,exynos5433-uart";
+ compatible = "samsung,exynos7885-uart",
+ "samsung,exynos5433-uart";
reg = <0x13820000 0x100>;
interrupts = <GIC_SPI 279 IRQ_TYPE_LEVEL_HIGH>;
pinctrl-names = "default";
@@ -346,7 +353,8 @@
};
i2c_0: i2c@13830000 {
- compatible = "samsung,s3c2440-i2c";
+ compatible = "samsung,exynos7885-i2c",
+ "samsung,s3c2440-i2c";
reg = <0x13830000 0x100>;
interrupts = <GIC_SPI 248 IRQ_TYPE_LEVEL_HIGH>;
#address-cells = <1>;
@@ -359,7 +367,8 @@
};
i2c_1: i2c@13840000 {
- compatible = "samsung,s3c2440-i2c";
+ compatible = "samsung,exynos7885-i2c",
+ "samsung,s3c2440-i2c";
reg = <0x13840000 0x100>;
interrupts = <GIC_SPI 249 IRQ_TYPE_LEVEL_HIGH>;
#address-cells = <1>;
@@ -372,7 +381,8 @@
};
i2c_2: i2c@13850000 {
- compatible = "samsung,s3c2440-i2c";
+ compatible = "samsung,exynos7885-i2c",
+ "samsung,s3c2440-i2c";
reg = <0x13850000 0x100>;
interrupts = <GIC_SPI 250 IRQ_TYPE_LEVEL_HIGH>;
#address-cells = <1>;
@@ -385,7 +395,8 @@
};
i2c_3: i2c@13860000 {
- compatible = "samsung,s3c2440-i2c";
+ compatible = "samsung,exynos7885-i2c",
+ "samsung,s3c2440-i2c";
reg = <0x13860000 0x100>;
interrupts = <GIC_SPI 251 IRQ_TYPE_LEVEL_HIGH>;
#address-cells = <1>;
@@ -398,7 +409,8 @@
};
i2c_4: i2c@13870000 {
- compatible = "samsung,s3c2440-i2c";
+ compatible = "samsung,exynos7885-i2c",
+ "samsung,s3c2440-i2c";
reg = <0x13870000 0x100>;
interrupts = <GIC_SPI 252 IRQ_TYPE_LEVEL_HIGH>;
#address-cells = <1>;
@@ -411,7 +423,8 @@
};
i2c_5: i2c@13880000 {
- compatible = "samsung,s3c2440-i2c";
+ compatible = "samsung,exynos7885-i2c",
+ "samsung,s3c2440-i2c";
reg = <0x13880000 0x100>;
interrupts = <GIC_SPI 253 IRQ_TYPE_LEVEL_HIGH>;
#address-cells = <1>;
@@ -424,7 +437,8 @@
};
i2c_6: i2c@13890000 {
- compatible = "samsung,s3c2440-i2c";
+ compatible = "samsung,exynos7885-i2c",
+ "samsung,s3c2440-i2c";
reg = <0x13890000 0x100>;
interrupts = <GIC_SPI 254 IRQ_TYPE_LEVEL_HIGH>;
#address-cells = <1>;
@@ -437,7 +451,8 @@
};
i2c_7: i2c@11cd0000 {
- compatible = "samsung,s3c2440-i2c";
+ compatible = "samsung,exynos7885-i2c",
+ "samsung,s3c2440-i2c";
reg = <0x11cd0000 0x100>;
interrupts = <GIC_SPI 255 IRQ_TYPE_LEVEL_HIGH>;
#address-cells = <1>;
diff --git a/dts/upstream/src/arm64/exynos/exynos850.dtsi b/dts/upstream/src/arm64/exynos/exynos850.dtsi
index 53104e6..da3f4a7 100644
--- a/dts/upstream/src/arm64/exynos/exynos850.dtsi
+++ b/dts/upstream/src/arm64/exynos/exynos850.dtsi
@@ -359,7 +359,8 @@
reg = <0x11850000 0x1000>;
wakeup-interrupt-controller {
- compatible = "samsung,exynos850-wakeup-eint";
+ compatible = "samsung,exynos850-wakeup-eint",
+ "samsung,exynos7-wakeup-eint";
};
};
@@ -368,7 +369,8 @@
reg = <0x11c30000 0x1000>;
wakeup-interrupt-controller {
- compatible = "samsung,exynos850-wakeup-eint";
+ compatible = "samsung,exynos850-wakeup-eint",
+ "samsung,exynos7-wakeup-eint";
};
};
@@ -396,7 +398,7 @@
};
rtc: rtc@11a30000 {
- compatible = "samsung,s3c6410-rtc";
+ compatible = "samsung,exynos850-rtc", "samsung,s3c6410-rtc";
reg = <0x11a30000 0x100>;
interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>;
@@ -406,7 +408,8 @@
};
mmc_0: mmc@12100000 {
- compatible = "samsung,exynos7-dw-mshc-smu";
+ compatible = "samsung,exynos850-dw-mshc-smu",
+ "samsung,exynos7-dw-mshc-smu";
reg = <0x12100000 0x2000>;
interrupts = <GIC_SPI 452 IRQ_TYPE_LEVEL_HIGH>;
#address-cells = <1>;
@@ -419,7 +422,7 @@
};
i2c_0: i2c@13830000 {
- compatible = "samsung,s3c2440-i2c";
+ compatible = "samsung,exynos850-i2c", "samsung,s3c2440-i2c";
reg = <0x13830000 0x100>;
interrupts = <GIC_SPI 196 IRQ_TYPE_LEVEL_HIGH>;
#address-cells = <1>;
@@ -432,7 +435,7 @@
};
i2c_1: i2c@13840000 {
- compatible = "samsung,s3c2440-i2c";
+ compatible = "samsung,exynos850-i2c", "samsung,s3c2440-i2c";
reg = <0x13840000 0x100>;
interrupts = <GIC_SPI 197 IRQ_TYPE_LEVEL_HIGH>;
#address-cells = <1>;
@@ -445,7 +448,7 @@
};
i2c_2: i2c@13850000 {
- compatible = "samsung,s3c2440-i2c";
+ compatible = "samsung,exynos850-i2c", "samsung,s3c2440-i2c";
reg = <0x13850000 0x100>;
interrupts = <GIC_SPI 198 IRQ_TYPE_LEVEL_HIGH>;
#address-cells = <1>;
@@ -458,7 +461,7 @@
};
i2c_3: i2c@13860000 {
- compatible = "samsung,s3c2440-i2c";
+ compatible = "samsung,exynos850-i2c", "samsung,s3c2440-i2c";
reg = <0x13860000 0x100>;
interrupts = <GIC_SPI 199 IRQ_TYPE_LEVEL_HIGH>;
#address-cells = <1>;
@@ -471,7 +474,7 @@
};
i2c_4: i2c@13870000 {
- compatible = "samsung,s3c2440-i2c";
+ compatible = "samsung,exynos850-i2c", "samsung,s3c2440-i2c";
reg = <0x13870000 0x100>;
interrupts = <GIC_SPI 200 IRQ_TYPE_LEVEL_HIGH>;
#address-cells = <1>;
@@ -485,7 +488,7 @@
/* I2C_5 (also called CAM_PMIC_I2C in TRM) */
i2c_5: i2c@13880000 {
- compatible = "samsung,s3c2440-i2c";
+ compatible = "samsung,exynos850-i2c", "samsung,s3c2440-i2c";
reg = <0x13880000 0x100>;
interrupts = <GIC_SPI 201 IRQ_TYPE_LEVEL_HIGH>;
#address-cells = <1>;
@@ -499,7 +502,7 @@
/* I2C_6 (also called MOTOR_I2C in TRM) */
i2c_6: i2c@13890000 {
- compatible = "samsung,s3c2440-i2c";
+ compatible = "samsung,exynos850-i2c", "samsung,s3c2440-i2c";
reg = <0x13890000 0x100>;
interrupts = <GIC_SPI 202 IRQ_TYPE_LEVEL_HIGH>;
#address-cells = <1>;
@@ -640,7 +643,8 @@
status = "disabled";
hsi2c_0: i2c@138a0000 {
- compatible = "samsung,exynosautov9-hsi2c";
+ compatible = "samsung,exynos850-hsi2c",
+ "samsung,exynosautov9-hsi2c";
reg = <0x138a0000 0xc0>;
interrupts = <GIC_SPI 193 IRQ_TYPE_LEVEL_HIGH>;
#address-cells = <1>;
@@ -668,7 +672,8 @@
status = "disabled";
hsi2c_1: i2c@138b0000 {
- compatible = "samsung,exynosautov9-hsi2c";
+ compatible = "samsung,exynos850-hsi2c",
+ "samsung,exynosautov9-hsi2c";
reg = <0x138b0000 0xc0>;
interrupts = <GIC_SPI 194 IRQ_TYPE_LEVEL_HIGH>;
#address-cells = <1>;
@@ -696,7 +701,8 @@
status = "disabled";
hsi2c_2: i2c@138c0000 {
- compatible = "samsung,exynosautov9-hsi2c";
+ compatible = "samsung,exynos850-hsi2c",
+ "samsung,exynosautov9-hsi2c";
reg = <0x138c0000 0xc0>;
interrupts = <GIC_SPI 195 IRQ_TYPE_LEVEL_HIGH>;
#address-cells = <1>;
@@ -738,7 +744,8 @@
status = "disabled";
hsi2c_3: i2c@11d00000 {
- compatible = "samsung,exynosautov9-hsi2c";
+ compatible = "samsung,exynos850-hsi2c",
+ "samsung,exynosautov9-hsi2c";
reg = <0x11d00000 0xc0>;
interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
#address-cells = <1>;
@@ -778,7 +785,8 @@
status = "disabled";
hsi2c_4: i2c@11d20000 {
- compatible = "samsung,exynosautov9-hsi2c";
+ compatible = "samsung,exynos850-hsi2c",
+ "samsung,exynosautov9-hsi2c";
reg = <0x11d20000 0xc0>;
interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>;
#address-cells = <1>;
diff --git a/dts/upstream/src/arm64/exynos/exynosautov9-sadk.dts b/dts/upstream/src/arm64/exynos/exynosautov9-sadk.dts
index bc1815f..de2c1de 100644
--- a/dts/upstream/src/arm64/exynos/exynosautov9-sadk.dts
+++ b/dts/upstream/src/arm64/exynos/exynosautov9-sadk.dts
@@ -9,6 +9,7 @@
/dts-v1/;
#include "exynosautov9.dtsi"
#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/input/input.h>
/ {
model = "Samsung ExynosAuto v9 SADK board";
@@ -32,6 +33,31 @@
<0xa 0x00000000 0x2 0x00000000>;
};
+ gpio-keys {
+ compatible = "gpio-keys";
+ pinctrl-names = "default";
+ pinctrl-0 = <&key_wakeup &key_volup &key_voldown>;
+
+ key-wakeup {
+ label = "Wakeup";
+ linux,code = <KEY_WAKEUP>;
+ gpios = <&gpa0 0 GPIO_ACTIVE_LOW>;
+ wakeup-source;
+ };
+
+ key-volume-down {
+ label = "Volume Down";
+ linux,code = <KEY_VOLUMEDOWN>;
+ gpios = <&gpg2 0 GPIO_ACTIVE_LOW>;
+ };
+
+ key-volume-up {
+ label = "Volume Up";
+ linux,code = <KEY_VOLUMEUP>;
+ gpios = <&gpg1 5 GPIO_ACTIVE_LOW>;
+ };
+ };
+
ufs_0_fixed_vcc_reg: regulator-0 {
compatible = "regulator-fixed";
regulator-name = "ufs-vcc";
@@ -49,6 +75,31 @@
};
};
+&pinctrl_alive {
+ key_wakeup: key-wakeup-pins {
+ samsung,pins = "gpa0-0";
+ samsung,pin-function = <EXYNOS_PIN_FUNC_EINT>;
+ samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
+ samsung,pin-drv = <EXYNOS5420_PIN_DRV_LV1>;
+ };
+};
+
+&pinctrl_peric1 {
+ key_voldown: key-voldown-pins {
+ samsung,pins = "gpg2-0";
+ samsung,pin-function = <EXYNOS_PIN_FUNC_EINT>;
+ samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
+ samsung,pin-drv = <EXYNOS5420_PIN_DRV_LV1>;
+ };
+
+ key_volup: key-volup-pins {
+ samsung,pins = "gpg1-5";
+ samsung,pin-function = <EXYNOS_PIN_FUNC_EINT>;
+ samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
+ samsung,pin-drv = <EXYNOS5420_PIN_DRV_LV1>;
+ };
+};
+
&pwm {
pinctrl-names = "default";
pinctrl-0 = <&pwm_tout3>;
diff --git a/dts/upstream/src/arm64/exynos/exynosautov9.dtsi b/dts/upstream/src/arm64/exynos/exynosautov9.dtsi
index b228cd7..c871a2f 100644
--- a/dts/upstream/src/arm64/exynos/exynosautov9.dtsi
+++ b/dts/upstream/src/arm64/exynos/exynosautov9.dtsi
@@ -166,7 +166,8 @@
ranges = <0x0 0x0 0x0 0x20000000>;
chipid@10000000 {
- compatible = "samsung,exynos850-chipid";
+ compatible = "samsung,exynosautov9-chipid",
+ "samsung,exynos850-chipid";
reg = <0x10000000 0x24>;
};
@@ -309,7 +310,9 @@
reg = <0x10450000 0x1000>;
wakeup-interrupt-controller {
- compatible = "samsung,exynosautov9-wakeup-eint";
+ compatible = "samsung,exynosautov9-wakeup-eint",
+ "samsung,exynos850-wakeup-eint",
+ "samsung,exynos7-wakeup-eint";
};
};
@@ -349,7 +352,8 @@
};
pmu_system_controller: system-controller@10460000 {
- compatible = "samsung,exynos7-pmu", "syscon";
+ compatible = "samsung,exynosautov9-pmu",
+ "samsung,exynos7-pmu", "syscon";
reg = <0x10460000 0x10000>;
reboot: syscon-reboot {
diff --git a/dts/upstream/src/arm64/exynos/exynosautov920-pinctrl.dtsi b/dts/upstream/src/arm64/exynos/exynosautov920-pinctrl.dtsi
new file mode 100644
index 0000000..663e826
--- /dev/null
+++ b/dts/upstream/src/arm64/exynos/exynosautov920-pinctrl.dtsi
@@ -0,0 +1,1266 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Samsung's ExynosAutov920 SoC pin-mux and pin-config device tree source
+ *
+ * Copyright (c) 2023 Samsung Electronics Co., Ltd.
+ *
+ * Samsung's ExynosAutov920 SoC pin-mux and pin-config options are listed as
+ * device tree nodes in this file.
+ */
+
+#include <dt-bindings/interrupt-controller/arm-gic.h>
+
+#include "exynos-pinctrl.h"
+
+&pinctrl_alive {
+ gpa0: gpa0-gpio-bank {
+ gpio-controller;
+ #gpio-cells = <2>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ interrupt-parent = <&gic>;
+ interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;
+ };
+
+ gpa1: gpa1-gpio-bank {
+ gpio-controller;
+ #gpio-cells = <2>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ interrupt-parent = <&gic>;
+ interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
+ };
+
+ gpq0: gpq0-gpio-bank {
+ gpio-controller;
+ #gpio-cells = <2>;
+
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+};
+
+&pinctrl_aud {
+ gpb0: gpb0-gpio-bank {
+ gpio-controller;
+ #gpio-cells = <2>;
+
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+
+ gpb1: gpb1-gpio-bank {
+ gpio-controller;
+ #gpio-cells = <2>;
+
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+
+ gpb2: gpb2-gpio-bank {
+ gpio-controller;
+ #gpio-cells = <2>;
+
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+
+ gpb3: gpb3-gpio-bank {
+ gpio-controller;
+ #gpio-cells = <2>;
+
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+
+ gpb4: gpb4-gpio-bank {
+ gpio-controller;
+ #gpio-cells = <2>;
+
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+
+ gpb5: gpb5-gpio-bank {
+ gpio-controller;
+ #gpio-cells = <2>;
+
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+
+ gpb6: gpb6-gpio-bank {
+ gpio-controller;
+ #gpio-cells = <2>;
+
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+};
+
+&pinctrl_hsi0 {
+ gph0: gph0-gpio-bank {
+ gpio-controller;
+ #gpio-cells = <2>;
+
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+
+ gph1: gph1-gpio-bank {
+ gpio-controller;
+ #gpio-cells = <2>;
+
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+};
+
+&pinctrl_hsi1 {
+ gph8: gph8-gpio-bank {
+ gpio-controller;
+ #gpio-cells = <2>;
+
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+};
+
+&pinctrl_hsi2 {
+ gph3: gph3-gpio-bank {
+ gpio-controller;
+ #gpio-cells = <2>;
+
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+
+ gph4: gph4-gpio-bank {
+ gpio-controller;
+ #gpio-cells = <2>;
+
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+
+ gph5: gph5-gpio-bank {
+ gpio-controller;
+ #gpio-cells = <2>;
+
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+
+ gph6: gph6-gpio-bank {
+ gpio-controller;
+ #gpio-cells = <2>;
+
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+};
+
+&pinctrl_hsi2ufs {
+ gph2: gph2-gpio-bank {
+ gpio-controller;
+ #gpio-cells = <2>;
+
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+
+ ufs_refclk_out: ufs-refclk-out-pins {
+ samsung,pins = "gph2-0";
+ samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
+ samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
+ samsung,pin-con-pdn = <EXYNOS_PIN_PULL_NONE>;
+ };
+
+ ufs_rst_n: ufs-rst-n-pins {
+ samsung,pins = "gph2-1";
+ samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
+ samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
+ samsung,pin-con-pdn = <EXYNOS_PIN_PULL_DOWN>;
+ };
+
+ ufs_refclk_out_1: ufs-refclk-out-1-pins {
+ samsung,pins = "gph2-2";
+ samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
+ samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
+ samsung,pin-con-pdn = <EXYNOS_PIN_PULL_DOWN>;
+ };
+
+ ufs_rst_n_1: ufs-rst-n-1-pins {
+ samsung,pins = "gph2-3";
+ samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
+ samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
+ samsung,pin-con-pdn = <EXYNOS_PIN_PULL_DOWN>;
+ };
+};
+
+&pinctrl_peric0 {
+ gpg0: gpg0-gpio-bank {
+ gpio-controller;
+ #gpio-cells = <2>;
+
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+
+ gpg2: gpg2-gpio-bank {
+ gpio-controller;
+ #gpio-cells = <2>;
+
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+
+ gpg3: gpg3-gpio-bank {
+ gpio-controller;
+ #gpio-cells = <2>;
+
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+
+ gpg4: gpg4-gpio-bank {
+ gpio-controller;
+ #gpio-cells = <2>;
+
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+
+ gpg5: gpg5-gpio-bank {
+ gpio-controller;
+ #gpio-cells = <2>;
+
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+
+ gpp0: gpp0-gpio-bank {
+ gpio-controller;
+ #gpio-cells = <2>;
+
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+
+ gpp1: gpp1-gpio-bank {
+ gpio-controller;
+ #gpio-cells = <2>;
+
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+
+ gpp2: gpp2-gpio-bank {
+ gpio-controller;
+ #gpio-cells = <2>;
+
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+
+ gpp3: gpp3-gpio-bank {
+ gpio-controller;
+ #gpio-cells = <2>;
+
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+
+ gpp4: gpp4-gpio-bank {
+ gpio-controller;
+ #gpio-cells = <2>;
+
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+
+ /* PWM PERIC0 */
+ pwm_tout0: pwm-tout0-pins {
+ samsung,pins = "gpg0-0";
+ samsung,pin-function = <EXYNOS_PIN_FUNC_4>;
+ samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
+ };
+
+ pwm_tout1: pwm-tout1-pins {
+ samsung,pins = "gpg0-1";
+ samsung,pin-function = <EXYNOS_PIN_FUNC_4>;
+ samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
+ };
+
+ pwm_tout2: pwm-tout2-pins {
+ samsung,pins = "gpg0-2";
+ samsung,pin-function = <EXYNOS_PIN_FUNC_4>;
+ samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
+ };
+
+ pwm_tout3: pwm-tout3-pins {
+ samsung,pins = "gpg0-3";
+ samsung,pin-function = <EXYNOS_PIN_FUNC_4>;
+ samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
+ };
+
+ /* UART PERIC0_USI00 */
+ uart0_bus: uart0-bus-pins {
+ samsung,pins = "gpp0-0", "gpp0-1", "gpp0-2", "gpp0-3";
+ samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
+ samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
+ };
+
+ uart0_bus_dual: uart0-bus-dual-pins {
+ samsung,pins = "gpp0-0", "gpp0-1";
+ samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
+ samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
+ };
+
+ /* UART PERIC0_USI01 */
+ uart1_bus: uart1-bus-pins {
+ samsung,pins = "gpp0-4", "gpp0-5", "gpp0-6", "gpp0-7";
+ samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
+ samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
+ };
+
+ uart1_bus_dual: uart1-bus-dual-pins {
+ samsung,pins = "gpp0-4", "gpp0-5";
+ samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
+ samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
+ };
+
+ /* UART PERIC0_USI02 */
+ uart2_bus: uart2-bus-pins {
+ samsung,pins = "gpp1-0", "gpp1-1", "gpp1-2", "gpp1-3";
+ samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
+ samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
+ };
+
+ uart2_bus_dual: uart2-bus-dual-pins {
+ samsung,pins = "gpp1-0", "gpp1-1";
+ samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
+ samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
+ };
+
+ /* UART PERIC0_USI03 */
+ uart3_bus: uart3-bus-pins {
+ samsung,pins = "gpp1-4", "gpp1-5", "gpp1-6", "gpp1-7";
+ samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
+ samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
+ };
+
+ uart3_bus_dual: uart3-bus-dual-pins {
+ samsung,pins = "gpp1-4", "gpp1-5";
+ samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
+ samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
+ };
+
+ /* UART PERIC0_USI04 */
+ uart4_bus: uart4-bus-pins {
+ samsung,pins = "gpp2-0", "gpp2-1", "gpp2-2", "gpp2-3";
+ samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
+ samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
+ };
+
+ uart4_bus_dual: uart4-bus-dual-pins {
+ samsung,pins = "gpp2-0", "gpp2-1";
+ samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
+ samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
+ };
+
+ /* UART PERIC0_USI05 */
+ uart5_bus: uart5-bus-pins {
+ samsung,pins = "gpp2-4", "gpp2-5", "gpp2-6", "gpp2-7";
+ samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
+ samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
+ };
+
+ uart5_bus_dual: uart5-bus-dual-pins {
+ samsung,pins = "gpp2-4", "gpp2-5";
+ samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
+ samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
+ };
+
+ /* UART PERIC0_USI06 */
+ uart6_bus: uart6-bus-pins {
+ samsung,pins = "gpp3-0", "gpp3-1", "gpp3-2", "gpp3-3";
+ samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
+ samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
+ };
+
+ uart6_bus_dual: uart6-bus-dual-pins {
+ samsung,pins = "gpp3-0", "gpp3-1";
+ samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
+ samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
+ };
+
+ /* UART PERIC0_USI07 */
+ uart7_bus: uart7-bus-pins {
+ samsung,pins = "gpp3-4", "gpp3-5", "gpp3-6", "gpp3-7";
+ samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
+ samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
+ };
+
+ uart7_bus_dual: uart7-bus-dual-pins {
+ samsung,pins = "gpp3-4", "gpp3-5";
+ samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
+ samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
+ };
+
+ /* UART PERIC0_USI08 */
+ uart8_bus: uart8-bus-pins {
+ samsung,pins = "gpp4-0", "gpp4-1", "gpp4-2", "gpp4-3";
+ samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
+ samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
+ };
+
+ uart8_bus_dual: uart8-bus-dual-pins {
+ samsung,pins = "gpp4-0", "gpp4-1";
+ samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
+ samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
+ };
+
+ /* I2C PERIC0 USI00 */
+ hsi2c0_bus: hsi2c0-bus-pins {
+ samsung,pins = "gpp0-0", "gpp0-1";
+ samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
+ samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
+ };
+
+ /* I2C PERIC0 USI00_I2C */
+ hsi2c1_bus: hsi2c1-bus-pins {
+ samsung,pins = "gpp0-2", "gpp0-3";
+ samsung,pin-function = <EXYNOS_PIN_FUNC_3>;
+ samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
+ };
+
+ /* I2C PERIC0 USI01 */
+ hsi2c2_bus: hsi2c2-bus-pins {
+ samsung,pins = "gpp0-4", "gpp0-5";
+ samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
+ samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
+ };
+
+ /* I2C PERIC0 USI01_I2C */
+ hsi2c3_bus: hsi2c3-bus-pins {
+ samsung,pins = "gpp0-6", "gpp0-7";
+ samsung,pin-function = <EXYNOS_PIN_FUNC_3>;
+ samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
+ };
+
+ /* I2C PERIC0 USI02 */
+ hsi2c4_bus: hsi2c4-bus-pins {
+ samsung,pins = "gpp1-0", "gpp1-1";
+ samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
+ samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
+ };
+
+ /* I2C PERIC0 USI02_I2C */
+ hsi2c5_bus: hsi2c5-bus-pins {
+ samsung,pins = "gpp1-2", "gpp1-3";
+ samsung,pin-function = <EXYNOS_PIN_FUNC_3>;
+ samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
+ };
+
+ /* I2C PERIC0 USI03 */
+ hsi2c6_bus: hsi2c6-bus-pins {
+ samsung,pins = "gpp1-4", "gpp1-5";
+ samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
+ samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
+ };
+
+ /* I2C PERIC0 USI03_I2C */
+ hsi2c7_bus: hsi2c7-bus-pins {
+ samsung,pins = "gpp1-6", "gpp1-7";
+ samsung,pin-function = <EXYNOS_PIN_FUNC_3>;
+ samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
+ };
+
+ /* I2C PERIC0 USI04 */
+ hsi2c8_bus: hsi2c8-bus-pins {
+ samsung,pins = "gpp2-0", "gpp2-1";
+ samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
+ samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
+ };
+
+ /* I2C PERIC0 USI04_I2C */
+ hsi2c9_bus: hsi2c9-bus-pins {
+ samsung,pins = "gpp2-2", "gpp2-3";
+ samsung,pin-function = <EXYNOS_PIN_FUNC_3>;
+ samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
+ };
+
+ /* I2C PERIC0 USI05 */
+ hsi2c10_bus: hsi2c10-bus-pins {
+ samsung,pins = "gpp2-4", "gpp2-5";
+ samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
+ samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
+ };
+
+ /* I2C PERIC0 USI05_I2C */
+ hsi2c11_bus: hsi2c11-bus-pins {
+ samsung,pins = "gpp2-6", "gpp2-7";
+ samsung,pin-function = <EXYNOS_PIN_FUNC_3>;
+ samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
+ };
+
+ /* I2C PERIC0 USI06 */
+ hsi2c12_bus: hsi2c12-bus-pins {
+ samsung,pins = "gpp3-0", "gpp3-1";
+ samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
+ samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
+ };
+
+ /* I2C PERIC0 USI06_I2C */
+ hsi2c13_bus: hsi2c13-bus-pins {
+ samsung,pins = "gpp3-2", "gpp3-3";
+ samsung,pin-function = <EXYNOS_PIN_FUNC_3>;
+ samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
+ };
+
+ /* I2C PERIC0 USI07 */
+ hsi2c14_bus: hsi2c14-bus-pins {
+ samsung,pins = "gpp3-4", "gpp3-5";
+ samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
+ samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
+ };
+
+ /* I2C PERIC0 USI07_I2C */
+ hsi2c15_bus: hsi2c15-bus-pins {
+ samsung,pins = "gpp3-6", "gpp3-7";
+ samsung,pin-function = <EXYNOS_PIN_FUNC_3>;
+ samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
+ };
+
+ /* I2C PERIC0 USI08 */
+ hsi2c16_bus: hsi2c16-bus-pins {
+ samsung,pins = "gpp4-0", "gpp4-1";
+ samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
+ samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
+ };
+
+ /* I2C PERIC0 USI08_I2C */
+ hsi2c17_bus: hsi2c17-bus-pins {
+ samsung,pins = "gpp4-2", "gpp4-3";
+ samsung,pin-function = <EXYNOS_PIN_FUNC_3>;
+ samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
+ };
+
+ /* SPI PERIC0 USI00 */
+ spi0_bus: spi0-bus-pins {
+ samsung,pins = "gpp0-0", "gpp0-1", "gpp0-2";
+ samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
+ samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
+ };
+
+ spi0_cs: spi0-cs-pins {
+ samsung,pins = "gpp0-3";
+ samsung,pin-function = <EXYNOS_PIN_FUNC_OUTPUT>;
+ samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
+ };
+
+ spi0_cs_func: spi0-cs-func-pins {
+ samsung,pins = "gpp0-3";
+ samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
+ samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
+ };
+
+ /* SPI PERIC0 USI01 */
+ spi1_bus: spi1-bus-pins {
+ samsung,pins = "gpp0-4", "gpp0-5", "gpp0-6";
+ samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
+ samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
+ };
+
+ spi1_cs: spi1-cs-pins {
+ samsung,pins = "gpp0-7";
+ samsung,pin-function = <EXYNOS_PIN_FUNC_OUTPUT>;
+ samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
+ };
+
+ spi1_cs_func: spi1-cs-func-pins {
+ samsung,pins = "gpp0-7";
+ samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
+ samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
+ };
+
+ /* SPI PERIC0 USI02 */
+ spi2_bus: spi2-bus-pins {
+ samsung,pins = "gpp1-0", "gpp1-1", "gpp1-2";
+ samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
+ samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
+ };
+
+ spi2_cs: spi2-cs-pins {
+ samsung,pins = "gpp1-3";
+ samsung,pin-function = <EXYNOS_PIN_FUNC_OUTPUT>;
+ samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
+ };
+
+ spi2_cs_func: spi2-cs-func-pins {
+ samsung,pins = "gpp1-3";
+ samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
+ samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
+ };
+
+ /* SPI PERIC0 USI03 */
+ spi3_bus: spi3-bus-pins {
+ samsung,pins = "gpp1-4", "gpp1-5", "gpp1-6";
+ samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
+ samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
+ };
+
+ spi3_cs: spi3-cs-pins {
+ samsung,pins = "gpp1-7";
+ samsung,pin-function = <EXYNOS_PIN_FUNC_OUTPUT>;
+ samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
+ };
+
+ spi3_cs_func: spi3-cs-func-pins {
+ samsung,pins = "gpp1-7";
+ samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
+ samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
+ };
+
+ /* SPI PERIC0 USI04 */
+ spi4_bus: spi4-bus-pins {
+ samsung,pins = "gpp2-0", "gpp2-1", "gpp2-2";
+ samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
+ samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
+ };
+
+ spi4_cs: spi4-cs-pins {
+ samsung,pins = "gpp2-3";
+ samsung,pin-function = <EXYNOS_PIN_FUNC_OUTPUT>;
+ samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
+ };
+
+ spi4_cs_func: spi4-cs-func-pins {
+ samsung,pins = "gpp2-3";
+ samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
+ samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
+ };
+
+ /* SPI PERIC0 USI05 */
+ spi5_bus: spi5-bus-pins {
+ samsung,pins = "gpp2-4", "gpp2-5", "gpp2-6";
+ samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
+ samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
+ };
+
+ spi5_cs: spi5-cs-pins {
+ samsung,pins = "gpp2-7";
+ samsung,pin-function = <EXYNOS_PIN_FUNC_OUTPUT>;
+ samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
+ };
+
+ spi5_cs_func: spi5-cs-func-pins {
+ samsung,pins = "gpp2-7";
+ samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
+ samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
+ };
+
+ /* SPI PERIC0 USI06 */
+ spi6_bus: spi6-bus-pins {
+ samsung,pins = "gpp3-0", "gpp3-1", "gpp3-2";
+ samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
+ samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
+ };
+
+ spi6_cs: spi6-cs-pins {
+ samsung,pins = "gpp3-3";
+ samsung,pin-function = <EXYNOS_PIN_FUNC_OUTPUT>;
+ samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
+ };
+
+ spi6_cs_func: spi6-cs-func-pins {
+ samsung,pins = "gpp3-3";
+ samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
+ samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
+ };
+
+ /* SPI PERIC0 USI07 */
+ spi7_bus: spi7-bus-pins {
+ samsung,pins = "gpp3-4", "gpp3-5", "gpp3-6";
+ samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
+ samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
+ };
+
+ spi7_cs: spi7-cs-pins {
+ samsung,pins = "gpp3-7";
+ samsung,pin-function = <EXYNOS_PIN_FUNC_OUTPUT>;
+ samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
+ };
+
+ spi7_cs_func: spi7-cs-func-pins {
+ samsung,pins = "gpp3-7";
+ samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
+ samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
+ };
+
+ /* SPI PERIC0 USI08 */
+ spi8_bus: spi8-bus-pins {
+ samsung,pins = "gpp4-0", "gpp4-1", "gpp4-2";
+ samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
+ samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
+ };
+
+ spi8_cs: spi8-cs-pins {
+ samsung,pins = "gpp4-3";
+ samsung,pin-function = <EXYNOS_PIN_FUNC_OUTPUT>;
+ samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
+ };
+
+ spi8_cs_func: spi8-cs-func-pins {
+ samsung,pins = "gpp4-3";
+ samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
+ samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
+ };
+
+ /* I3C PERIC0 */
+ i3c0_bus: i3c0-bus-pins {
+ samsung,pins = "gpp2-6", "gpp2-7";
+ samsung,pin-function = <EXYNOS_PIN_FUNC_4>;
+ samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
+ };
+
+ i3c1_bus: i3c1-bus-pins {
+ samsung,pins = "gpp3-2", "gpp3-3";
+ samsung,pin-function = <EXYNOS_PIN_FUNC_4>;
+ samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
+ };
+
+ i3c2_bus: i3c2-bus-pins {
+ samsung,pins = "gpp3-6", "gpp3-7";
+ samsung,pin-function = <EXYNOS_PIN_FUNC_4>;
+ samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
+ };
+
+ i3c3_bus: i3c3-bus-pins {
+ samsung,pins = "gpp4-2", "gpp4-3";
+ samsung,pin-function = <EXYNOS_PIN_FUNC_4>;
+ samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
+ };
+};
+
+&pinctrl_peric1 {
+ gpg1: gpg1-gpio-bank {
+ gpio-controller;
+ #gpio-cells = <2>;
+
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+
+ gpp5: gpp5-gpio-bank {
+ gpio-controller;
+ #gpio-cells = <2>;
+
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+
+ gpp6: gpp6-gpio-bank {
+ gpio-controller;
+ #gpio-cells = <2>;
+
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+
+ gpp7: gpp7-gpio-bank {
+ gpio-controller;
+ #gpio-cells = <2>;
+
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+
+ gpp8: gpp8-gpio-bank {
+ gpio-controller;
+ #gpio-cells = <2>;
+
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+
+ gpp9: gpp9-gpio-bank {
+ gpio-controller;
+ #gpio-cells = <2>;
+
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+
+ gpp10: gpp10-gpio-bank {
+ gpio-controller;
+ #gpio-cells = <2>;
+
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+
+ gpp11: gpp11-gpio-bank {
+ gpio-controller;
+ #gpio-cells = <2>;
+
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+
+ gpp12: gpp12-gpio-bank {
+ gpio-controller;
+ #gpio-cells = <2>;
+
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+
+ /* UART PERIC1 USI09 */
+ uart9_bus: uart9-bus-pins {
+ samsung,pins = "gpp5-0", "gpp5-1", "gpp5-2", "gpp5-3";
+ samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
+ samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
+ };
+
+ uart9_bus_dual: uart9-bus-dual-pins {
+ samsung,pins = "gpp5-0", "gpp5-1";
+ samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
+ samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
+ };
+
+ /* UART PERIC1 USI10 */
+ uart10_bus: uart10-bus-pins {
+ samsung,pins = "gpp5-4", "gpp5-5", "gpp5-6", "gpp5-7";
+ samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
+ samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
+ };
+
+ uart10_bus_dual: uart10-bus-dual-pins {
+ samsung,pins = "gpp5-4", "gpp5-5";
+ samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
+ samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
+ };
+
+ /* UART PERIC1 USI11 */
+ uart11_bus: uart11-bus-pins {
+ samsung,pins = "gpp10-0", "gpp10-1", "gpp10-2", "gpp10-3";
+ samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
+ samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
+ };
+
+ uart11_bus_dual: uart11-bus-dual-pins {
+ samsung,pins = "gpp10-0", "gpp10-1";
+ samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
+ samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
+ };
+
+ /* UART PERIC1_USI12 */
+ uart12_bus: uart12-bus-pins {
+ samsung,pins = "gpp7-0", "gpp7-1", "gpp7-2", "gpp7-3";
+ samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
+ samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
+ };
+
+ uart12_bus_dual: uart12-bus-dual-pins {
+ samsung,pins = "gpp7-0", "gpp7-1";
+ samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
+ samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
+ };
+
+ /* UART PERIC1_USI13 */
+ uart13_bus: uart13-bus-pins {
+ samsung,pins = "gpp7-4", "gpp7-5", "gpp7-6", "gpp7-7";
+ samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
+ samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
+ };
+
+ uart13_bus_dual: uart13-bus-dual-pins {
+ samsung,pins = "gpp7-4", "gpp7-5";
+ samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
+ samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
+ };
+
+ /* UART PERIC1 USI14 */
+ uart14_bus: uart14-bus-pins {
+ samsung,pins = "gpp8-0", "gpp8-1", "gpp8-2", "gpp8-3";
+ samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
+ samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
+ };
+
+ uart14_bus_dual: uart14-bus-dual-pins {
+ samsung,pins = "gpp8-0", "gpp8-1";
+ samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
+ samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
+ };
+
+ /* UART PERIC1 USI15 */
+ uart15_bus: uart15-bus-pins {
+ samsung,pins = "gpp11-0", "gpp11-1", "gpp11-2", "gpp11-3";
+ samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
+ samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
+ };
+
+ uart15_bus_dual: uart15-bus-dual-pins {
+ samsung,pins = "gpp11-0", "gpp11-1";
+ samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
+ samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
+ };
+
+ /* UART PERIC1 USI16 */
+ uart16_bus: uart16-bus-pins {
+ samsung,pins = "gpp9-0", "gpp9-1", "gpp9-2", "gpp9-3";
+ samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
+ samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
+ };
+
+ uart16_bus_dual: uart16-bus-dual-pins {
+ samsung,pins = "gpp9-0", "gpp9-1";
+ samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
+ samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
+ };
+
+ /* UART PERIC1 USI17 */
+ uart17_bus: uart17-bus-pins {
+ samsung,pins = "gpp12-0", "gpp12-1", "gpp12-2", "gpp12-3";
+ samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
+ samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
+ };
+
+ uart17_bus_dual: uart17-bus-dual-pins {
+ samsung,pins = "gpp12-0", "gpp12-1";
+ samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
+ samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
+ };
+
+ /* I2C PERIC1 USI09 */
+ hsi2c18_bus: hsi2c18-bus-pins {
+ samsung,pins = "gpp5-0", "gpp5-1";
+ samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
+ samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
+ };
+
+ /* I2C PERIC1 USI09_I2C */
+ hsi2c19_bus: hsi2c19-bus-pins {
+ samsung,pins = "gpp5-2", "gpp5-3";
+ samsung,pin-function = <EXYNOS_PIN_FUNC_3>;
+ samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
+ };
+
+ /* I2C PERIC1 USI10 */
+ hsi2c20_bus: hsi2c20-bus-pins {
+ samsung,pins = "gpp5-4", "gpp5-5";
+ samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
+ samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
+ };
+
+ /* I2C PERIC1 USI10_I2C */
+ hsi2c21_bus: hsi2c21-bus-pins {
+ samsung,pins = "gpp5-6", "gpp5-7";
+ samsung,pin-function = <EXYNOS_PIN_FUNC_3>;
+ samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
+ };
+
+ /* I2C PERIC1 USI11 */
+ hsi2c22_bus: hsi2c22-bus-pins {
+ samsung,pins = "gpp10-0", "gpp10-1";
+ samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
+ samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
+ };
+
+ /* I2C PERIC1 USI11_I2C */
+ hsi2c23_bus: hsi2c23-bus-pins {
+ samsung,pins = "gpp10-2", "gpp10-3";
+ samsung,pin-function = <EXYNOS_PIN_FUNC_3>;
+ samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
+ };
+
+ /* I2C PERIC1 USI12 */
+ hsi2c24_bus: hsi2c24-bus-pins {
+ samsung,pins = "gpp7-0", "gpp7-1";
+ samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
+ samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
+ };
+
+ /* I2C PERIC1 USI12_I2C */
+ hsi2c25_bus: hsi2c25-bus-pins {
+ samsung,pins = "gpp7-2", "gpp7-3";
+ samsung,pin-function = <EXYNOS_PIN_FUNC_3>;
+ samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
+ };
+
+ /* I2C PERIC1 USI13 */
+ hsi2c26_bus: hsi2c26-bus-pins {
+ samsung,pins = "gpp7-4", "gpp7-5";
+ samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
+ samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
+ };
+
+ /* I2C PERIC1 USI13_I2C */
+ hsi2c27_bus: hsi2c27-bus-pins {
+ samsung,pins = "gpp7-6", "gpp7-7";
+ samsung,pin-function = <EXYNOS_PIN_FUNC_3>;
+ samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
+ };
+
+ /* I2C PERIC1 USI14 */
+ hsi2c28_bus: hsi2c28-bus-pins {
+ samsung,pins = "gpp8-0", "gpp8-1";
+ samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
+ samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
+ };
+
+ /* I2C PERIC1 USI14_I2C */
+ hsi2c29_bus: hsi2c29-bus-pins {
+ samsung,pins = "gpp8-2", "gpp8-3";
+ samsung,pin-function = <EXYNOS_PIN_FUNC_3>;
+ samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
+ };
+
+ /* I2C PERIC1 USI15 */
+ hsi2c30_bus: hsi2c30-bus-pins {
+ samsung,pins = "gpp11-0", "gpp11-1";
+ samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
+ samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
+ };
+
+ /* I2C PERIC1 USI15_I2C */
+ hsi2c31_bus: hsi2c31-bus-pins {
+ samsung,pins = "gpp11-2", "gpp11-3";
+ samsung,pin-function = <EXYNOS_PIN_FUNC_3>;
+ samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
+ };
+
+ /* I2C PERIC1 USI16 */
+ hsi2c32_bus: hsi2c32-bus-pins {
+ samsung,pins = "gpp9-0", "gpp9-1";
+ samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
+ samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
+ };
+
+ /* I2C PERIC1 USI16_I2C */
+ hsi2c33_bus: hsi2c33-bus-pins {
+ samsung,pins = "gpp9-2", "gpp9-3";
+ samsung,pin-function = <EXYNOS_PIN_FUNC_3>;
+ samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
+ };
+
+ /* I2C PERIC1 USI17 */
+ hsi2c34_bus: hsi2c34-bus-pins {
+ samsung,pins = "gpp12-0", "gpp12-1";
+ samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
+ samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
+ };
+
+ /* I2C PERIC1 USI17_I2C */
+ hsi2c35_bus: hsi2c35-bus-pins {
+ samsung,pins = "gpp12-2", "gpp12-3";
+ samsung,pin-function = <EXYNOS_PIN_FUNC_3>;
+ samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
+ };
+
+ /* SPI PERIC1 USI09 */
+ spi9_bus: spi9-bus-pins {
+ samsung,pins = "gpp5-0", "gpp5-1", "gpp5-2";
+ samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
+ samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
+ };
+
+ spi9_cs: spi9-cs-pins {
+ samsung,pins = "gpp5-3";
+ samsung,pin-function = <EXYNOS_PIN_FUNC_OUTPUT>;
+ samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
+ };
+
+ spi9_cs_func: spi9-cs-func-pins {
+ samsung,pins = "gpp5-3";
+ samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
+ samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
+ };
+
+ /* SPI PERIC1 USI10 */
+ spi10_bus: spi10-bus-pins {
+ samsung,pins = "gpp5-4", "gpp5-5", "gpp5-6";
+ samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
+ samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
+ };
+
+ spi10_cs: spi10-cs-pins {
+ samsung,pins = "gpp5-7";
+ samsung,pin-function = <EXYNOS_PIN_FUNC_OUTPUT>;
+ samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
+ };
+
+ spi10_cs_func: spi10-cs-func-pins {
+ samsung,pins = "gpp5-7";
+ samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
+ samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
+ };
+
+ /* SPI PERIC1 USI11 */
+ spi11_bus: spi11-bus-pins {
+ samsung,pins = "gpp10-0", "gpp10-1", "gpp10-2";
+ samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
+ samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
+ };
+
+ spi11_cs: spi11-cs-pins {
+ samsung,pins = "gpp10-3";
+ samsung,pin-function = <EXYNOS_PIN_FUNC_OUTPUT>;
+ samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
+ };
+
+ spi11_cs_func: spi11-cs-func-pins {
+ samsung,pins = "gpp10-3";
+ samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
+ samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
+ };
+
+ /* SPI PERIC1 USI12 */
+ spi12_bus: spi12-bus-pins {
+ samsung,pins = "gpp7-0", "gpp7-1", "gpp7-2";
+ samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
+ samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
+ };
+
+ spi12_cs: spi12-cs-pins {
+ samsung,pins = "gpp7-3";
+ samsung,pin-function = <EXYNOS_PIN_FUNC_OUTPUT>;
+ samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
+ };
+
+ spi12_cs_func: spi12-cs-func-pins {
+ samsung,pins = "gpp7-3";
+ samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
+ samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
+ };
+
+ /* SPI PERIC1 USI13 */
+ spi13_bus: spi13-bus-pins {
+ samsung,pins = "gpp7-4", "gpp7-5", "gpp7-6";
+ samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
+ samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
+ };
+
+ spi13_cs: spi13-cs-pins {
+ samsung,pins = "gpp7-7";
+ samsung,pin-function = <EXYNOS_PIN_FUNC_OUTPUT>;
+ samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
+ };
+
+ spi13_cs_func: spi13-cs-func-pins {
+ samsung,pins = "gpp7-7";
+ samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
+ samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
+ };
+
+ /* SPI PERIC1 USI14 */
+ spi14_bus: spi14-bus-pins {
+ samsung,pins = "gpp8-0", "gpp8-1", "gpp8-2";
+ samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
+ samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
+ };
+
+ spi14_cs: spi14-cs-pins {
+ samsung,pins = "gpp8-3";
+ samsung,pin-function = <EXYNOS_PIN_FUNC_OUTPUT>;
+ samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
+ };
+
+ spi14_cs_func: spi14-cs-func-pins {
+ samsung,pins = "gpp8-3";
+ samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
+ samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
+ };
+
+ /* SPI PERIC1 USI15 */
+ spi15_bus: spi15-bus-pins {
+ samsung,pins = "gpp11-0", "gpp11-1", "gpp11-2";
+ samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
+ samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
+ };
+
+ spi15_cs: spi15-cs-pins {
+ samsung,pins = "gpp11-3";
+ samsung,pin-function = <EXYNOS_PIN_FUNC_OUTPUT>;
+ samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
+ };
+
+ spi15_cs_func: spi15-cs-func-pins {
+ samsung,pins = "gpp11-3";
+ samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
+ samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
+ };
+
+ /* SPI PERIC1 USI16 */
+ spi16_bus: spi16-bus-pins {
+ samsung,pins = "gpp9-0", "gpp9-1", "gpp9-2";
+ samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
+ samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
+ };
+
+ spi16_cs: spi16-cs-pins {
+ samsung,pins = "gpp9-3";
+ samsung,pin-function = <EXYNOS_PIN_FUNC_OUTPUT>;
+ samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
+ };
+
+ spi16_cs_func: spi16-cs-func-pins {
+ samsung,pins = "gpp9-3";
+ samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
+ samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
+ };
+
+ /* SPI PERIC1 USI17 */
+ spi17_bus: spi17-bus-pins {
+ samsung,pins = "gpp12-0", "gpp12-1", "gpp12-2";
+ samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
+ samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
+ };
+
+ spi17_cs: spi17-cs-pins {
+ samsung,pins = "gpp12-3";
+ samsung,pin-function = <EXYNOS_PIN_FUNC_OUTPUT>;
+ samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
+ };
+
+ spi17_cs_func: spi17-cs-func-pins {
+ samsung,pins = "gpp12-3";
+ samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
+ samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
+ };
+
+ /* I3C PERIC1 */
+ i3c4_bus: i3c4-bus-pins {
+ samsung,pins = "gpp7-2", "gpp7-3";
+ samsung,pin-function = <EXYNOS_PIN_FUNC_4>;
+ samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
+ };
+
+ i3c5_bus: i3c5-bus-pins {
+ samsung,pins = "gpp7-6", "gpp7-7";
+ samsung,pin-function = <EXYNOS_PIN_FUNC_4>;
+ samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
+ };
+
+ i3c6_bus: i3c6-bus-pins {
+ samsung,pins = "gpp8-2", "gpp8-3";
+ samsung,pin-function = <EXYNOS_PIN_FUNC_4>;
+ samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
+ };
+
+ i3c7_bus: i3c7-bus-pins {
+ samsung,pins = "gpp11-2", "gpp11-3";
+ samsung,pin-function = <EXYNOS_PIN_FUNC_4>;
+ samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
+ };
+};
diff --git a/dts/upstream/src/arm64/exynos/exynosautov920-sadk.dts b/dts/upstream/src/arm64/exynos/exynosautov920-sadk.dts
new file mode 100644
index 0000000..a397f06
--- /dev/null
+++ b/dts/upstream/src/arm64/exynos/exynosautov920-sadk.dts
@@ -0,0 +1,88 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Samsung's ExynosAutov920 SADK board device tree source
+ *
+ * Copyright (c) 2023 Samsung Electronics Co., Ltd.
+ *
+ */
+
+/dts-v1/;
+#include "exynosautov920.dtsi"
+#include "exynos-pinctrl.h"
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/input/input.h>
+
+/ {
+ model = "Samsung ExynosAutov920 SADK board";
+ compatible = "samsung,exynosautov920-sadk", "samsung,exynosautov920";
+
+ #address-cells = <2>;
+ #size-cells = <2>;
+
+ aliases {
+ serial0 = &serial_0;
+ };
+
+ chosen {
+ stdout-path = &serial_0;
+ };
+
+ gpio-keys {
+ compatible = "gpio-keys";
+ pinctrl-names = "default";
+ pinctrl-0 = <&key_wakeup &key_back>;
+
+ key-wakeup {
+ label = "KEY_WAKEUP";
+ linux,code = <KEY_WAKEUP>;
+ gpios = <&gpa0 0 GPIO_ACTIVE_LOW>;
+ wakeup-source;
+ };
+
+ key-back {
+ label = "KEY_BACK";
+ linux,code = <KEY_BACK>;
+ gpios = <&gpp6 3 GPIO_ACTIVE_LOW>;
+ };
+ };
+
+ memory@80000000 {
+ device_type = "memory";
+ reg = <0x0 0x80000000 0x0 0x70000000>,
+ <0x8 0x80000000 0x1 0xfba00000>,
+ <0xa 0x00000000 0x2 0x00000000>;
+ };
+};
+
+&pinctrl_alive {
+ key_wakeup: key-wakeup-pins {
+ samsung,pins = "gpa0-0";
+ samsung,pin-function = <EXYNOS_PIN_FUNC_EINT>;
+ };
+};
+
+&pinctrl_peric1 {
+ key_back: key-back-pins {
+ samsung,pins = "gpp6-3";
+ samsung,pin-function = <EXYNOS_PIN_FUNC_EINT>;
+ };
+};
+
+&pwm {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pwm_tout0>;
+ status = "okay";
+};
+
+&serial_0 {
+ status = "okay";
+};
+
+&usi_0 {
+ samsung,clkreq-on; /* needed for UART mode */
+ status = "okay";
+};
+
+&xtcxo {
+ clock-frequency = <38400000>;
+};
diff --git a/dts/upstream/src/arm64/exynos/exynosautov920.dtsi b/dts/upstream/src/arm64/exynos/exynosautov920.dtsi
new file mode 100644
index 0000000..c1c8566
--- /dev/null
+++ b/dts/upstream/src/arm64/exynos/exynosautov920.dtsi
@@ -0,0 +1,312 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Samsung's ExynosAutov920 SoC device tree source
+ *
+ * Copyright (c) 2023 Samsung Electronics Co., Ltd.
+ *
+ */
+
+#include <dt-bindings/interrupt-controller/arm-gic.h>
+#include <dt-bindings/soc/samsung,exynos-usi.h>
+
+/ {
+ compatible = "samsung,exynosautov920";
+ #address-cells = <2>;
+ #size-cells = <1>;
+
+ interrupt-parent = <&gic>;
+
+ aliases {
+ pinctrl0 = &pinctrl_alive;
+ pinctrl1 = &pinctrl_aud;
+ pinctrl2 = &pinctrl_hsi0;
+ pinctrl3 = &pinctrl_hsi1;
+ pinctrl4 = &pinctrl_hsi2;
+ pinctrl5 = &pinctrl_hsi2ufs;
+ pinctrl6 = &pinctrl_peric0;
+ pinctrl7 = &pinctrl_peric1;
+ };
+
+ arm-pmu {
+ compatible = "arm,cortex-a78-pmu";
+ interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_LOW>;
+ };
+
+ xtcxo: clock {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-output-names = "oscclk";
+ };
+
+ /*
+ * FIXME: Keep the stub clock for serial driver, until proper clock
+ * driver is implemented.
+ */
+ clock_usi: clock-usi {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <200000000>;
+ clock-output-names = "usi";
+ };
+
+ cpus: cpus {
+ #address-cells = <2>;
+ #size-cells = <0>;
+
+ cpu-map {
+ cluster0 {
+ core0 {
+ cpu = <&cpu0>;
+ };
+ core1 {
+ cpu = <&cpu1>;
+ };
+ core2 {
+ cpu = <&cpu2>;
+ };
+ core3 {
+ cpu = <&cpu3>;
+ };
+ };
+
+ cluster1 {
+ core0 {
+ cpu = <&cpu4>;
+ };
+ core1 {
+ cpu = <&cpu5>;
+ };
+ core2 {
+ cpu = <&cpu6>;
+ };
+ core3 {
+ cpu = <&cpu7>;
+ };
+ };
+
+ cluster2 {
+ core0 {
+ cpu = <&cpu8>;
+ };
+ core1 {
+ cpu = <&cpu9>;
+ };
+ };
+ };
+
+ cpu0: cpu@0 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a78ae";
+ reg = <0x0 0x0>;
+ enable-method = "psci";
+ };
+
+ cpu1: cpu@100 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a78ae";
+ reg = <0x0 0x100>;
+ enable-method = "psci";
+ };
+
+ cpu2: cpu@200 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a78ae";
+ reg = <0x0 0x200>;
+ enable-method = "psci";
+ };
+
+ cpu3: cpu@300 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a78ae";
+ reg = <0x0 0x300>;
+ enable-method = "psci";
+ };
+
+ cpu4: cpu@10000 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a78ae";
+ reg = <0x0 0x10000>;
+ enable-method = "psci";
+ };
+
+ cpu5: cpu@10100 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a78ae";
+ reg = <0x0 0x10100>;
+ enable-method = "psci";
+ };
+
+ cpu6: cpu@10200 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a78ae";
+ reg = <0x0 0x10200>;
+ enable-method = "psci";
+ };
+
+ cpu7: cpu@10300 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a78ae";
+ reg = <0x0 0x10300>;
+ enable-method = "psci";
+ };
+
+ cpu8: cpu@20000 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a78ae";
+ reg = <0x0 0x20000>;
+ enable-method = "psci";
+ };
+
+ cpu9: cpu@20100 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a78ae";
+ reg = <0x0 0x20100>;
+ enable-method = "psci";
+ };
+ };
+
+ psci {
+ compatible = "arm,psci-1.0";
+ method = "smc";
+ };
+
+ soc: soc@0 {
+ compatible = "simple-bus";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0x0 0x0 0x0 0x20000000>;
+
+ chipid@10000000 {
+ compatible = "samsung,exynosautov920-chipid",
+ "samsung,exynos850-chipid";
+ reg = <0x10000000 0x24>;
+ };
+
+ gic: interrupt-controller@10400000 {
+ compatible = "arm,gic-v3";
+ #interrupt-cells = <3>;
+ #address-cells = <0>;
+ interrupt-controller;
+ reg = <0x10400000 0x10000>,
+ <0x10460000 0x140000>;
+ interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
+ };
+
+ syscon_peric0: syscon@10820000 {
+ compatible = "samsung,exynosautov920-peric0-sysreg",
+ "syscon";
+ reg = <0x10820000 0x2000>;
+ };
+
+ pinctrl_peric0: pinctrl@10830000 {
+ compatible = "samsung,exynosautov920-pinctrl";
+ reg = <0x10830000 0x10000>;
+ interrupts = <GIC_SPI 753 IRQ_TYPE_LEVEL_HIGH>;
+ };
+
+ usi_0: usi@108800c0 {
+ compatible = "samsung,exynosautov920-usi",
+ "samsung,exynos850-usi";
+ reg = <0x108800c0 0x20>;
+ samsung,sysreg = <&syscon_peric0 0x1000>;
+ samsung,mode = <USI_V2_UART>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges;
+ clocks = <&clock_usi>, <&clock_usi>;
+ clock-names = "pclk", "ipclk";
+ status = "disabled";
+
+ serial_0: serial@10880000 {
+ compatible = "samsung,exynosautov920-uart",
+ "samsung,exynos850-uart";
+ reg = <0x10880000 0xc0>;
+ interrupts = <GIC_SPI 764 IRQ_TYPE_LEVEL_HIGH>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&uart0_bus>;
+ clocks = <&clock_usi>, <&clock_usi>;
+ clock-names = "uart", "clk_uart_baud0";
+ samsung,uart-fifosize = <256>;
+ status = "disabled";
+ };
+ };
+
+ pwm: pwm@109b0000 {
+ compatible = "samsung,exynosautov920-pwm",
+ "samsung,exynos4210-pwm";
+ reg = <0x109b0000 0x100>;
+ samsung,pwm-outputs = <0>, <1>, <2>, <3>;
+ #pwm-cells = <3>;
+ clocks = <&xtcxo>;
+ clock-names = "timers";
+ status = "disabled";
+ };
+
+ syscon_peric1: syscon@10c20000 {
+ compatible = "samsung,exynosautov920-peric1-sysreg",
+ "syscon";
+ reg = <0x10c20000 0x2000>;
+ };
+
+ pinctrl_peric1: pinctrl@10c30000 {
+ compatible = "samsung,exynosautov920-pinctrl";
+ reg = <0x10c30000 0x10000>;
+ interrupts = <GIC_SPI 781 IRQ_TYPE_LEVEL_HIGH>;
+ };
+
+ pinctrl_alive: pinctrl@11850000 {
+ compatible = "samsung,exynosautov920-pinctrl";
+ reg = <0x11850000 0x10000>;
+
+ wakeup-interrupt-controller {
+ compatible = "samsung,exynosautov920-wakeup-eint";
+ };
+ };
+
+ pmu_system_controller: system-controller@11860000 {
+ compatible = "samsung,exynosautov920-pmu",
+ "samsung,exynos7-pmu","syscon";
+ reg = <0x11860000 0x10000>;
+ };
+
+ pinctrl_hsi0: pinctrl@16040000 {
+ compatible = "samsung,exynosautov920-pinctrl";
+ reg = <0x16040000 0x10000>;
+ interrupts = <GIC_SPI 442 IRQ_TYPE_LEVEL_HIGH>;
+ };
+
+ pinctrl_hsi1: pinctrl@16450000 {
+ compatible = "samsung,exynosautov920-pinctrl";
+ reg = <0x16450000 0x10000>;
+ interrupts = <GIC_SPI 456 IRQ_TYPE_LEVEL_HIGH>;
+ };
+
+ pinctrl_hsi2: pinctrl@16c10000 {
+ compatible = "samsung,exynosautov920-pinctrl";
+ reg = <0x16c10000 0x10000>;
+ interrupts = <GIC_SPI 602 IRQ_TYPE_LEVEL_HIGH>;
+ };
+
+ pinctrl_hsi2ufs: pinctrl@16d20000 {
+ compatible = "samsung,exynosautov920-pinctrl";
+ reg = <0x16d20000 0x10000>;
+ interrupts = <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>;
+ };
+
+ pinctrl_aud: pinctrl@1a460000 {
+ compatible = "samsung,exynosautov920-pinctrl";
+ reg = <0x1a460000 0x10000>;
+ };
+ };
+
+ timer {
+ compatible = "arm,armv8-timer";
+ interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>,
+ <GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>,
+ <GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>,
+ <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>,
+ <GIC_PPI 12 IRQ_TYPE_LEVEL_LOW>;
+ };
+};
+
+#include "exynosautov920-pinctrl.dtsi"
diff --git a/dts/upstream/src/arm64/exynos/google/gs101-oriole.dts b/dts/upstream/src/arm64/exynos/google/gs101-oriole.dts
new file mode 100644
index 0000000..4a71f75
--- /dev/null
+++ b/dts/upstream/src/arm64/exynos/google/gs101-oriole.dts
@@ -0,0 +1,105 @@
+// SPDX-License-Identifier: GPL-2.0-only
+/*
+ * Oriole Device Tree
+ *
+ * Copyright 2021-2023 Google LLC
+ * Copyright 2023 Linaro Ltd - <peter.griffin@linaro.org>
+ */
+
+/dts-v1/;
+
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/input/input.h>
+#include "gs101-pinctrl.h"
+#include "gs101.dtsi"
+
+/ {
+ model = "Oriole";
+ compatible = "google,gs101-oriole", "google,gs101";
+
+ aliases {
+ serial0 = &serial_0;
+ };
+
+ chosen {
+ /* Bootloader expects bootargs specified otherwise it crashes */
+ bootargs = "";
+ stdout-path = &serial_0;
+ };
+
+ gpio-keys {
+ compatible = "gpio-keys";
+ pinctrl-names = "default";
+ pinctrl-0 = <&key_voldown>, <&key_volup>, <&key_power>;
+
+ button-vol-down {
+ label = "KEY_VOLUMEDOWN";
+ linux,code = <KEY_VOLUMEDOWN>;
+ gpios = <&gpa7 3 GPIO_ACTIVE_LOW>;
+ wakeup-source;
+ };
+
+ button-vol-up {
+ label = "KEY_VOLUMEUP";
+ linux,code = <KEY_VOLUMEUP>;
+ gpios = <&gpa8 1 GPIO_ACTIVE_LOW>;
+ wakeup-source;
+ };
+
+ button-power {
+ label = "KEY_POWER";
+ linux,code = <KEY_POWER>;
+ gpios = <&gpa10 1 GPIO_ACTIVE_LOW>;
+ wakeup-source;
+ };
+ };
+};
+
+&ext_24_5m {
+ clock-frequency = <24576000>;
+};
+
+&ext_200m {
+ clock-frequency = <200000000>;
+};
+
+&pinctrl_far_alive {
+ key_voldown: key-voldown-pins {
+ samsung,pins = "gpa7-3";
+ samsung,pin-function = <GS101_PIN_FUNC_EINT>;
+ samsung,pin-pud = <GS101_PIN_PULL_NONE>;
+ samsung,pin-drv = <GS101_PIN_DRV_2_5_MA>;
+ };
+
+ key_volup: key-volup-pins {
+ samsung,pins = "gpa8-1";
+ samsung,pin-function = <GS101_PIN_FUNC_EINT>;
+ samsung,pin-pud = <GS101_PIN_PULL_NONE>;
+ samsung,pin-drv = <GS101_PIN_DRV_2_5_MA>;
+ };
+};
+
+&pinctrl_gpio_alive {
+ key_power: key-power-pins {
+ samsung,pins = "gpa10-1";
+ samsung,pin-function = <GS101_PIN_FUNC_EINT>;
+ samsung,pin-pud = <GS101_PIN_PULL_NONE>;
+ samsung,pin-drv = <GS101_PIN_DRV_2_5_MA>;
+ };
+};
+
+&serial_0 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&uart0_bus>;
+ status = "okay";
+};
+
+&usi_uart {
+ samsung,clkreq-on; /* needed for UART mode */
+ status = "okay";
+};
+
+&watchdog_cl0 {
+ timeout-sec = <30>;
+ status = "okay";
+};
diff --git a/dts/upstream/src/arm64/exynos/google/gs101-pinctrl.dtsi b/dts/upstream/src/arm64/exynos/google/gs101-pinctrl.dtsi
new file mode 100644
index 0000000..e6a9776
--- /dev/null
+++ b/dts/upstream/src/arm64/exynos/google/gs101-pinctrl.dtsi
@@ -0,0 +1,1249 @@
+// SPDX-License-Identifier: GPL-2.0-only
+/*
+ * GS101 SoC pin-mux and pin-config device tree source
+ *
+ * Copyright 2019-2023 Google LLC
+ * Copyright 2023 Linaro Ltd - <peter.griffin@linaro.org>
+ */
+
+#include "gs101-pinctrl.h"
+
+&pinctrl_gpio_alive {
+ gpa0: gpa0-gpio-bank {
+ gpio-controller;
+ #gpio-cells = <2>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ interrupt-parent = <&gic>;
+ interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH 0>,
+ <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH 0>,
+ <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH 0>,
+ <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH 0>,
+ <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH 0>,
+ <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH 0>,
+ <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH 0>,
+ <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH 0>;
+ };
+
+ gpa1: gpa1-gpio-bank {
+ gpio-controller;
+ #gpio-cells = <2>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ interrupt-parent = <&gic>;
+ interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH 0>,
+ <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH 0>,
+ <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH 0>,
+ <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH 0>,
+ <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH 0>,
+ <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH 0>,
+ <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH 0>;
+ };
+
+ gpa2: gpa2-gpio-bank {
+ gpio-controller;
+ #gpio-cells = <2>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ interrupt-parent = <&gic>;
+ interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH 0>,
+ <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH 0>,
+ <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH 0>,
+ <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH 0>,
+ <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH 0>;
+ };
+
+ gpa3: gpa3-gpio-bank {
+ gpio-controller;
+ #gpio-cells = <2>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ interrupt-parent = <&gic>;
+ interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH 0>,
+ <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH 0>,
+ <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH 0>,
+ <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH 0>;
+ };
+
+ gpa4: gpa4-gpio-bank {
+ gpio-controller;
+ #gpio-cells = <2>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ interrupt-parent = <&gic>;
+ interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH 0>,
+ <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH 0>,
+ <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH 0>,
+ <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH 0>;
+ };
+
+ gpa5: gpa5-gpio-bank {
+ gpio-controller;
+ #gpio-cells = <2>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH 0>,
+ <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH 0>,
+ <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH 0>,
+ <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH 0>,
+ <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH 0>,
+ <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH 0>,
+ <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH 0>;
+ };
+
+ gpa9: gpa9-gpio-bank {
+ gpio-controller;
+ #gpio-cells = <2>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH 0>,
+ <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH 0>,
+ <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH 0>,
+ <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH 0>,
+ <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH 0>,
+ <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH 0>,
+ <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH 0>,
+ <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH 0>;
+ };
+
+ gpa10: gpa10-gpio-bank {
+ gpio-controller;
+ #gpio-cells = <2>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH 0>,
+ <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH 0>;
+ };
+
+ uart15_bus: uart15-bus-pins {
+ samsung,pins = "gpa2-3", "gpa2-4";
+ samsung,pin-function = <GS101_PIN_FUNC_2>;
+ samsung,pin-pud = <GS101_PIN_PULL_NONE>;
+ };
+
+ uart16_bus: uart16-bus-pins {
+ samsung,pins = "gpa3-0", "gpa3-1", "gpa3-2", "gpa3-3";
+ samsung,pin-function = <GS101_PIN_FUNC_2>;
+ samsung,pin-pud = <GS101_PIN_PULL_NONE>;
+ };
+
+ uart17_bus: uart17-bus-pins {
+ samsung,pins = "gpa4-0", "gpa4-1", "gpa4-2", "gpa4-3";
+ samsung,pin-function = <GS101_PIN_FUNC_2>;
+ samsung,pin-pud = <GS101_PIN_PULL_NONE>;
+ };
+
+ spi15_bus: spi15-bus-pins {
+ samsung,pins = "gpa4-0", "gpa4-1", "gpa4-2";
+ samsung,pin-function = <GS101_PIN_FUNC_2>;
+ samsung,pin-pud = <GS101_PIN_PULL_NONE>;
+ samsung,pin-drv = <GS101_PIN_DRV_2_5_MA>;
+ };
+
+ spi15_cs: spi15-cs-pins {
+ samsung,pins = "gpa4-3";
+ samsung,pin-function = <GS101_PIN_FUNC_OUTPUT>;
+ samsung,pin-pud = <GS101_PIN_PULL_NONE>;
+ samsung,pin-drv = <GS101_PIN_DRV_2_5_MA>;
+ };
+};
+
+&pinctrl_far_alive {
+ gpa6: gpa6-gpio-bank {
+ gpio-controller;
+ #gpio-cells = <2>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ interrupt-parent = <&gic>;
+ interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH 0>,
+ <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH 0>,
+ <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH 0>,
+ <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH 0>,
+ <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH 0>,
+ <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH 0>,
+ <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH 0>,
+ <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH 0>;
+ };
+
+ gpa7: gpa7-gpio-bank {
+ gpio-controller;
+ #gpio-cells = <2>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ interrupt-parent = <&gic>;
+ interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH 0>,
+ <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH 0>,
+ <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH 0>,
+ <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH 0>;
+ };
+
+ gpa8: gpa8-gpio-bank {
+ gpio-controller;
+ #gpio-cells = <2>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ interrupt-parent = <&gic>;
+ interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH 0>,
+ <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH 0>,
+ <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH 0>,
+ <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH 0>,
+ <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH 0>,
+ <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH 0>,
+ <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH 0>,
+ <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH 0>;
+ };
+
+ gpa11: gpa11-gpio-bank {
+ gpio-controller;
+ #gpio-cells = <2>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ interrupt-parent = <&gic>;
+ interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH 0>,
+ <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH 0>;
+ };
+};
+
+&pinctrl_gsacore {
+ gps0: gps0-gpio-bank {
+ gpio-controller;
+ #gpio-cells = <2>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+
+ gps1: gps1-gpio-bank {
+ gpio-controller;
+ #gpio-cells = <2>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+
+ gps2: gps2-gpio-bank {
+ gpio-controller;
+ #gpio-cells = <2>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+};
+
+&pinctrl_gsactrl {
+ gps3: gps3-gpio-bank {
+ gpio-controller;
+ #gpio-cells = <2>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+};
+
+&pinctrl_hsi1 {
+ gph0: gph0-gpio-bank {
+ gpio-controller;
+ #gpio-cells = <2>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+
+ gph1: gph1-gpio-bank {
+ gpio-controller;
+ #gpio-cells = <2>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+
+ pcie0_clkreq: pcie0-clkreq-pins{
+ samsung,pins = "gph0-1";
+ samsung,pin-function = <GS101_PIN_FUNC_2>;
+ samsung,pin-pud = <GS101_PIN_PULL_UP>;
+ samsung,pin-drv = <GS101_PIN_DRV_10_MA>;
+ samsung,pin-con-pdn = <GS101_PIN_PDN_PREV>;
+ samsung,pin-pud-pdn = <GS101_PIN_PULL_UP>;
+ };
+
+ pcie0_perst: pcie0-perst-pins {
+ samsung,pins = "gph0-0";
+ samsung,pin-function = <GS101_PIN_FUNC_OUTPUT>;
+ samsung,pin-drv = <GS101_PIN_DRV_10_MA>;
+ samsung,pin-con-pdn = <GS101_PIN_PDN_PREV>;
+ };
+};
+
+&pinctrl_hsi2 {
+ gph2: gph2-gpio-bank {
+ gpio-controller;
+ #gpio-cells = <2>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+
+ gph3: gph3-gpio-bank {
+ gpio-controller;
+ #gpio-cells = <2>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+
+ gph4: gph4-gpio-bank {
+ gpio-controller;
+ #gpio-cells = <2>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+
+ sd2_clk: sd2-clk-pins {
+ samsung,pins = "gph4-0";
+ samsung,pin-function = <GS101_PIN_FUNC_2>;
+ samsung,pin-pud = <GS101_PIN_PULL_NONE>;
+ samsung,pin-drv = <GS101_PIN_DRV_7_5_MA>;
+ };
+
+ sd2_cmd: sd2-cmd-pins {
+ samsung,pins = "gph4-1";
+ samsung,pin-function = <GS101_PIN_FUNC_2>;
+ samsung,pin-pud = <GS101_PIN_PULL_UP>;
+ samsung,pin-drv = <GS101_PIN_DRV_7_5_MA>;
+ };
+
+ sd2_bus1: sd2-bus-width1-pins {
+ samsung,pins = "gph4-2";
+ samsung,pin-function = <GS101_PIN_FUNC_2>;
+ samsung,pin-pud = <GS101_PIN_PULL_UP>;
+ samsung,pin-drv = <GS101_PIN_DRV_7_5_MA>;
+ };
+
+ sd2_bus4: sd2-bus-width4-pins {
+ samsung,pins = "gph4-3", "gph4-4", "gph4-5";
+ samsung,pin-function = <GS101_PIN_FUNC_2>;
+ samsung,pin-pud = <GS101_PIN_PULL_UP>;
+ samsung,pin-drv = <GS101_PIN_DRV_7_5_MA>;
+ };
+
+ sd2_clk_fast_slew_rate_1x: sd2-clk-fast-slew-rate-1x-pins {
+ samsung,pins = "gph4-0";
+ samsung,pin-function = <GS101_PIN_FUNC_2>;
+ samsung,pin-pud = <GS101_PIN_PULL_NONE>;
+ samsung,pin-drv = <GS101_PIN_DRV_2_5_MA>;
+ };
+
+ sd2_clk_fast_slew_rate_2x: sd2-clk-fast-slew-rate-2x-pins {
+ samsung,pins = "gph4-0";
+ samsung,pin-function = <GS101_PIN_FUNC_2>;
+ samsung,pin-pud = <GS101_PIN_PULL_NONE>;
+ samsung,pin-drv = <GS101_PIN_DRV_5_MA>;
+ };
+
+ sd2_clk_fast_slew_rate_3x: sd2-clk-fast-slew-rate-3x-pins {
+ samsung,pins = "gph4-0";
+ samsung,pin-function = <GS101_PIN_FUNC_2>;
+ samsung,pin-pud = <GS101_PIN_PULL_NONE>;
+ samsung,pin-drv = <GS101_PIN_DRV_7_5_MA>;
+ };
+
+ sd2_clk_fast_slew_rate_4x: sd2-clk-fast-slew-rate-4x-pins {
+ samsung,pins = "gph4-0";
+ samsung,pin-function = <GS101_PIN_FUNC_2>;
+ samsung,pin-pud = <GS101_PIN_PULL_NONE>;
+ samsung,pin-drv = <GS101_PIN_DRV_10_MA>;
+ };
+
+ ufs_rst_n: ufs-rst-n-pins {
+ samsung,pins = "gph3-1";
+ samsung,pin-function = <GS101_PIN_FUNC_2>;
+ samsung,pin-pud = <GS101_PIN_PULL_NONE>;
+ samsung,pin-con-pdn = <GS101_PIN_PDN_PREV>;
+ samsung,pin-pud-pdn = <GS101_PIN_PULL_NONE>;
+ };
+
+ ufs_refclk_out: ufs-refclk-out-pins {
+ samsung,pins = "gph3-0";
+ samsung,pin-function = <GS101_PIN_FUNC_2>;
+ samsung,pin-pud = <GS101_PIN_PULL_NONE>;
+ samsung,pin-con-pdn = <GS101_PIN_PDN_PREV>;
+ samsung,pin-pud-pdn = <GS101_PIN_PULL_NONE>;
+ };
+
+ pcie1_clkreq: pcie1-clkreq-pins {
+ samsung,pins = "gph2-1";
+ samsung,pin-function = <GS101_PIN_FUNC_2>;
+ samsung,pin-pud = <GS101_PIN_PULL_UP>;
+ samsung,pin-drv = <GS101_PIN_DRV_10_MA>;
+ samsung,pin-con-pdn = <GS101_PIN_PDN_PREV>;
+ samsung,pin-pud-pdn = <GS101_PIN_PULL_UP>;
+ };
+
+ pcie1_perst: pcie1-perst-pins {
+ samsung,pins = "gph2-0";
+ samsung,pin-function = <GS101_PIN_FUNC_OUTPUT>;
+ samsung,pin-drv = <GS101_PIN_DRV_10_MA>;
+ samsung,pin-con-pdn = <GS101_PIN_PDN_PREV>;
+ };
+};
+
+&pinctrl_peric0 {
+ gpp0: gpp0-gpio-bank {
+ gpio-controller;
+ #gpio-cells = <2>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+
+ gpp1: gpp1-gpio-bank {
+ gpio-controller;
+ #gpio-cells = <2>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+
+ gpp2: gpp2-gpio-bank {
+ gpio-controller;
+ #gpio-cells = <2>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+
+ gpp3: gpp3-gpio-bank {
+ gpio-controller;
+ #gpio-cells = <2>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+
+ gpp4: gpp4-gpio-bank {
+ gpio-controller;
+ #gpio-cells = <2>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+
+ gpp5: gpp5-gpio-bank {
+ gpio-controller;
+ #gpio-cells = <2>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+
+ gpp6: gpp6-gpio-bank {
+ gpio-controller;
+ #gpio-cells = <2>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+
+ gpp7: gpp7-gpio-bank {
+ gpio-controller;
+ #gpio-cells = <2>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+
+ gpp8: gpp8-gpio-bank {
+ gpio-controller;
+ #gpio-cells = <2>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+
+ gpp9: gpp9-gpio-bank {
+ gpio-controller;
+ #gpio-cells = <2>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+
+ gpp10: gpp10-gpio-bank {
+ gpio-controller;
+ #gpio-cells = <2>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+
+ gpp11: gpp11-gpio-bank {
+ gpio-controller;
+ #gpio-cells = <2>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+
+ gpp12: gpp12-gpio-bank {
+ gpio-controller;
+ #gpio-cells = <2>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+
+ gpp13: gpp13-gpio-bank {
+ gpio-controller;
+ #gpio-cells = <2>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+
+ gpp14: gpp14-gpio-bank {
+ gpio-controller;
+ #gpio-cells = <2>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+
+ gpp15: gpp15-gpio-bank {
+ gpio-controller;
+ #gpio-cells = <2>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+
+ gpp16: gpp16-gpio-bank {
+ gpio-controller;
+ #gpio-cells = <2>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+
+ gpp17: gpp17-gpio-bank {
+ gpio-controller;
+ #gpio-cells = <2>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+
+ gpp18: gpp18-gpio-bank {
+ gpio-controller;
+ #gpio-cells = <2>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+
+ gpp19: gpp19-gpio-bank {
+ gpio-controller;
+ #gpio-cells = <2>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+
+ /* USI_PERIC0_UART_DBG */
+ uart0_bus: uart0-bus-pins {
+ samsung,pins = "gpp1-2", "gpp1-3";
+ samsung,pin-function = <GS101_PIN_FUNC_2>;
+ samsung,pin-pud = <GS101_PIN_PULL_NONE>;
+ };
+
+ disp_te_pri_on: disp-te-pri-on-pins {
+ samsung,pins = "gpp0-3";
+ samsung,pin-function = <GS101_PIN_FUNC_EINT>;
+ };
+
+ disp_te_pri_off: disp-te-pri-off-pins {
+ samsung,pins = "gpp0-3";
+ samsung,pin-function = <GS101_PIN_FUNC_INPUT>;
+ };
+
+ disp_te_sec_on: disp-te-sec-on-pins {
+ samsung,pins = "gpp0-4";
+ samsung,pin-function = <GS101_PIN_FUNC_EINT>;
+ };
+
+ disp_te_sec_off: disp-te-sec-off-pins {
+ samsung,pins = "gpp0-4";
+ samsung,pin-function = <GS101_PIN_FUNC_INPUT>;
+ };
+
+ sensor_mclk1_out: sensor-mclk1-out-pins {
+ samsung,pins = "gpp3-0";
+ samsung,pin-function = <GS101_PIN_FUNC_OUTPUT>;
+ samsung,pin-pud = <GS101_PIN_PULL_DOWN>;
+ samsung,pin-drv = <GS101_PIN_DRV_5_MA>;
+ };
+
+ sensor_mclk1_fn: sensor-mclk1-fn-pins {
+ samsung,pins = "gpp3-0";
+ samsung,pin-function = <GS101_PIN_FUNC_2>;
+ samsung,pin-pud = <GS101_PIN_PULL_NONE>;
+ samsung,pin-drv = <GS101_PIN_DRV_5_MA>;
+ };
+
+ sensor_mclk2_out: sensor-mclk2-out-pins {
+ samsung,pins = "gpp5-0";
+ samsung,pin-function = <GS101_PIN_FUNC_OUTPUT>;
+ samsung,pin-pud = <GS101_PIN_PULL_DOWN>;
+ samsung,pin-drv = <GS101_PIN_DRV_5_MA>;
+ };
+
+ sensor_mclk2_fn: sensor-mclk2-fn-pins {
+ samsung,pins = "gpp5-0";
+ samsung,pin-function = <GS101_PIN_FUNC_2>;
+ samsung,pin-pud = <GS101_PIN_PULL_NONE>;
+ samsung,pin-drv = <GS101_PIN_DRV_5_MA>;
+ };
+
+ sensor_mclk3_out: sensor-mclk3-out-pins {
+ samsung,pins = "gpp7-0";
+ samsung,pin-function = <GS101_PIN_FUNC_OUTPUT>;
+ samsung,pin-pud = <GS101_PIN_PULL_DOWN>;
+ samsung,pin-drv = <GS101_PIN_DRV_5_MA>;
+ };
+
+ sensor_mclk3_fn: sensor-mclk3-fn-pins {
+ samsung,pins = "gpp7-0";
+ samsung,pin-function = <GS101_PIN_FUNC_2>;
+ samsung,pin-pud = <GS101_PIN_PULL_NONE>;
+ samsung,pin-drv = <GS101_PIN_DRV_5_MA>;
+ };
+
+ sensor_mclk4_out: sensor-mclk4-out-pins {
+ samsung,pins = "gpp9-0";
+ samsung,pin-function = <GS101_PIN_FUNC_OUTPUT>;
+ samsung,pin-pud = <GS101_PIN_PULL_DOWN>;
+ samsung,pin-drv = <GS101_PIN_DRV_5_MA>;
+ };
+
+ sensor_mclk4_fn: sensor-mclk4-fn-pins {
+ samsung,pins = "gpp9-0";
+ samsung,pin-function = <GS101_PIN_FUNC_2>;
+ samsung,pin-pud = <GS101_PIN_PULL_NONE>;
+ samsung,pin-drv = <GS101_PIN_DRV_5_MA>;
+ };
+
+ sensor_mclk5_out: sensor-mclk5-out-pins {
+ samsung,pins = "gpp11-0";
+ samsung,pin-function = <GS101_PIN_FUNC_OUTPUT>;
+ samsung,pin-pud = <GS101_PIN_PULL_DOWN>;
+ samsung,pin-drv = <GS101_PIN_DRV_5_MA>;
+ };
+
+ sensor_mclk5_fn: sensor-mclk5-fn-pins {
+ samsung,pins = "gpp11-0";
+ samsung,pin-function = <GS101_PIN_FUNC_2>;
+ samsung,pin-pud = <GS101_PIN_PULL_NONE>;
+ samsung,pin-drv = <GS101_PIN_DRV_5_MA>;
+ };
+
+ sensor_mclk6_out: sensor-mclk6-out-pins {
+ samsung,pins = "gpp13-0";
+ samsung,pin-function = <GS101_PIN_FUNC_OUTPUT>;
+ samsung,pin-pud = <GS101_PIN_PULL_DOWN>;
+ samsung,pin-drv = <GS101_PIN_DRV_5_MA>;
+ };
+
+ sensor_mclk6_fn: sensor-mclk6-fn-pins {
+ samsung,pins = "gpp13-0";
+ samsung,pin-function = <GS101_PIN_FUNC_2>;
+ samsung,pin-pud = <GS101_PIN_PULL_NONE>;
+ samsung,pin-drv = <GS101_PIN_DRV_5_MA>;
+ };
+
+ sensor_mclk7_out: sensor-mclk7-out-pins {
+ samsung,pins = "gpp15-0";
+ samsung,pin-function = <GS101_PIN_FUNC_OUTPUT>;
+ samsung,pin-pud = <GS101_PIN_PULL_DOWN>;
+ samsung,pin-drv = <GS101_PIN_DRV_5_MA>;
+ };
+
+ sensor_mclk7_fn: sensor-mclk7-fn-pins {
+ samsung,pins = "gpp15-0";
+ samsung,pin-function = <GS101_PIN_FUNC_2>;
+ samsung,pin-pud = <GS101_PIN_PULL_NONE>;
+ samsung,pin-drv = <GS101_PIN_DRV_5_MA>;
+ };
+
+ sensor_mclk8_out: sensor-mclk8-out-pins {
+ samsung,pins = "gpp17-0";
+ samsung,pin-function = <GS101_PIN_FUNC_OUTPUT>;
+ samsung,pin-pud = <GS101_PIN_PULL_DOWN>;
+ samsung,pin-drv = <GS101_PIN_DRV_5_MA>;
+ };
+
+ sensor_mclk8_fn: sensor-mclk8-fn-pins {
+ samsung,pins = "gpp17-0";
+ samsung,pin-function = <GS101_PIN_FUNC_2>;
+ samsung,pin-pud = <GS101_PIN_PULL_NONE>;
+ samsung,pin-drv = <GS101_PIN_DRV_5_MA>;
+ };
+
+ hsi2c14_bus: hsi2c14-bus-pins {
+ samsung,pins = "gpp18-0", "gpp18-1";
+ samsung,pin-function = <GS101_PIN_FUNC_2>;
+ samsung,pin-pud = <GS101_PIN_PULL_NONE>;
+ samsung,pin-drv = <GS101_PIN_DRV_2_5_MA>;
+ };
+
+ uart14_bus_single: uart14-bus-pins {
+ samsung,pins = "gpp18-0", "gpp18-1",
+ "gpp18-2", "gpp18-3";
+ samsung,pin-function = <GS101_PIN_FUNC_2>;
+ samsung,pin-pud = <GS101_PIN_PULL_NONE>;
+ };
+
+ spi14_bus: spi14-bus-pins {
+ samsung,pins = "gpp18-0", "gpp18-1", "gpp18-2";
+ samsung,pin-function = <GS101_PIN_FUNC_2>;
+ samsung,pin-pud = <GS101_PIN_PULL_NONE>;
+ samsung,pin-drv = <GS101_PIN_DRV_2_5_MA>;
+ };
+
+ spi14_cs: spi14-cs-pins {
+ samsung,pins = "gpp18-3";
+ samsung,pin-function = <GS101_PIN_FUNC_OUTPUT>;
+ samsung,pin-pud = <GS101_PIN_PULL_NONE>;
+ samsung,pin-drv = <GS101_PIN_DRV_2_5_MA>;
+ };
+
+ spi14_cs_func: spi14-cs-func-pins {
+ samsung,pins = "gpp18-3";
+ samsung,pin-function = <GS101_PIN_FUNC_2>;
+ samsung,pin-pud = <GS101_PIN_PULL_NONE>;
+ samsung,pin-drv = <GS101_PIN_DRV_2_5_MA>;
+ };
+
+ hsi2c8_bus: hsi2c8-bus-pins {
+ samsung,pins = "gpp16-0", "gpp16-1";
+ samsung,pin-function = <GS101_PIN_FUNC_3>;
+ samsung,pin-pud = <GS101_PIN_PULL_NONE>;
+ samsung,pin-drv = <GS101_PIN_DRV_2_5_MA>;
+ samsung,pin-pud-pdn = <GS101_PIN_PDN_OUT0>;
+ };
+
+ uart8_bus_single: uart8-bus-pins {
+ samsung,pins = "gpp16-0", "gpp16-1", "gpp16-2",
+ "gpp16-3";
+ samsung,pin-function = <GS101_PIN_FUNC_3>;
+ samsung,pin-pud = <GS101_PIN_PULL_NONE>;
+ };
+
+ spi8_bus: spi8-bus-pins {
+ samsung,pins = "gpp16-0", "gpp16-1", "gpp16-2";
+ samsung,pin-function = <GS101_PIN_FUNC_3>;
+ samsung,pin-pud = <GS101_PIN_PULL_NONE>;
+ samsung,pin-drv = <GS101_PIN_DRV_2_5_MA>;
+ };
+
+ spi8_cs: spi8-cs-pins {
+ samsung,pins = "gpp16-3";
+ samsung,pin-function = <GS101_PIN_FUNC_OUTPUT>;
+ samsung,pin-pud = <GS101_PIN_PULL_NONE>;
+ samsung,pin-drv = <GS101_PIN_DRV_2_5_MA>;
+ };
+
+ spi8_cs_func: spi8-cs-func-pins {
+ samsung,pins = "gpp16-3";
+ samsung,pin-function = <GS101_PIN_FUNC_3>;
+ samsung,pin-pud = <GS101_PIN_PULL_NONE>;
+ samsung,pin-drv = <GS101_PIN_DRV_2_5_MA>;
+ };
+
+ hsi2c7_bus: hsi2c7-bus-pins {
+ samsung,pins = "gpp14-0", "gpp14-1";
+ samsung,pin-function = <GS101_PIN_FUNC_3>;
+ samsung,pin-pud = <GS101_PIN_PULL_NONE>;
+ samsung,pin-drv = <GS101_PIN_DRV_2_5_MA>;
+ };
+
+ uart7_bus_single: uart7-bus-pins {
+ samsung,pins = "gpp14-0", "gpp14-1",
+ "gpp14-2", "gpp14-3";
+ samsung,pin-function = <GS101_PIN_FUNC_3>;
+ samsung,pin-pud = <GS101_PIN_PULL_NONE>;
+ };
+
+ spi7_bus: spi7-bus-pins {
+ samsung,pins = "gpp14-0", "gpp14-1", "gpp14-2";
+ samsung,pin-function = <GS101_PIN_FUNC_3>;
+ samsung,pin-pud = <GS101_PIN_PULL_NONE>;
+ samsung,pin-drv = <GS101_PIN_DRV_2_5_MA>;
+ };
+
+ spi7_cs: spi7-cs-pins {
+ samsung,pins = "gpp14-3";
+ samsung,pin-function = <GS101_PIN_FUNC_OUTPUT>;
+ samsung,pin-pud = <GS101_PIN_PULL_NONE>;
+ samsung,pin-drv = <GS101_PIN_DRV_2_5_MA>;
+ };
+
+ spi7_cs_func: spi7-cs-func-pins {
+ samsung,pins = "gpp14-3";
+ samsung,pin-function = <GS101_PIN_FUNC_3>;
+ samsung,pin-pud = <GS101_PIN_PULL_NONE>;
+ samsung,pin-drv = <GS101_PIN_DRV_2_5_MA>;
+ };
+
+ hsi2c6_bus: hsi2c6-bus-pins {
+ samsung,pins = "gpp12-0", "gpp12-1";
+ samsung,pin-function = <GS101_PIN_FUNC_3>;
+ samsung,pin-pud = <GS101_PIN_PULL_NONE>;
+ samsung,pin-drv = <GS101_PIN_DRV_2_5_MA>;
+ };
+
+ uart6_bus_single: uart6-bus-pins {
+ samsung,pins = "gpp12-0", "gpp12-1",
+ "gpp12-2", "gpp12-3";
+ samsung,pin-function = <GS101_PIN_FUNC_3>;
+ samsung,pin-pud = <GS101_PIN_PULL_NONE>;
+ };
+
+ spi6_bus: spi6-bus-pins {
+ samsung,pins = "gpp12-0", "gpp12-1", "gpp12-2";
+ samsung,pin-function = <GS101_PIN_FUNC_3>;
+ samsung,pin-pud = <GS101_PIN_PULL_NONE>;
+ samsung,pin-drv = <GS101_PIN_DRV_2_5_MA>;
+ };
+
+ spi6_cs: spi6-cs-pins {
+ samsung,pins = "gpp12-3";
+ samsung,pin-function = <GS101_PIN_FUNC_OUTPUT>;
+ samsung,pin-pud = <GS101_PIN_PULL_NONE>;
+ samsung,pin-drv = <GS101_PIN_DRV_2_5_MA>;
+ };
+
+ spi6_cs_func: spi6-cs-func-pins {
+ samsung,pins = "gpp12-3";
+ samsung,pin-function = <GS101_PIN_FUNC_3>;
+ samsung,pin-pud = <GS101_PIN_PULL_NONE>;
+ samsung,pin-drv = <GS101_PIN_DRV_2_5_MA>;
+ };
+
+ hsi2c5_bus: hsi2c5-bus-pins {
+ samsung,pins = "gpp10-0", "gpp10-1";
+ samsung,pin-function = <GS101_PIN_FUNC_3>;
+ samsung,pin-pud = <GS101_PIN_PULL_NONE>;
+ samsung,pin-drv = <GS101_PIN_DRV_2_5_MA>;
+ };
+
+ uart5_bus_single: uart5-bus-pins {
+ samsung,pins = "gpp10-0", "gpp10-1",
+ "gpp10-2", "gpp10-3";
+ samsung,pin-function = <GS101_PIN_FUNC_3>;
+ samsung,pin-pud = <GS101_PIN_PULL_NONE>;
+ };
+
+ spi5_bus: spi5-bus-pins {
+ samsung,pins = "gpp10-0", "gpp10-1", "gpp10-2";
+ samsung,pin-drv = <GS101_PIN_DRV_2_5_MA>;
+ samsung,pin-function = <GS101_PIN_FUNC_3>;
+ samsung,pin-pud = <GS101_PIN_PULL_NONE>;
+ samsung,pin-con-pdn = <GS101_PIN_PDN_PREV>;
+ samsung,pin-pud-pdn = <GS101_PIN_PULL_NONE>;
+ };
+
+ spi5_cs_func: spi5-cs-func-pins {
+ samsung,pins = "gpp10-3";
+ samsung,pin-drv = <GS101_PIN_DRV_2_5_MA>;
+ samsung,pin-function = <GS101_PIN_FUNC_3>;
+ samsung,pin-pud = <GS101_PIN_PULL_NONE>;
+ samsung,pin-con-pdn = <GS101_PIN_PDN_PREV>;
+ samsung,pin-pud-pdn = <GS101_PIN_PULL_NONE>;
+ };
+
+ hsi2c4_bus: hsi2c4-bus-pins {
+ samsung,pins = "gpp8-0", "gpp8-1";
+ samsung,pin-function = <GS101_PIN_FUNC_3>;
+ samsung,pin-pud = <GS101_PIN_PULL_NONE>;
+ samsung,pin-drv = <GS101_PIN_DRV_2_5_MA>;
+ };
+
+ uart4_bus_single: uart4-bus-pins {
+ samsung,pins = "gpp8-0", "gpp8-1",
+ "gpp8-2", "gpp8-3";
+ samsung,pin-function = <GS101_PIN_FUNC_3>;
+ samsung,pin-pud = <GS101_PIN_PULL_NONE>;
+ };
+
+ spi4_bus: spi4-bus-pins {
+ samsung,pins = "gpp8-0", "gpp8-1", "gpp8-2";
+ samsung,pin-function = <GS101_PIN_FUNC_3>;
+ samsung,pin-pud = <GS101_PIN_PULL_NONE>;
+ samsung,pin-drv = <GS101_PIN_DRV_2_5_MA>;
+ };
+
+ spi4_cs: spi4-cs-pins {
+ samsung,pins = "gpp8-3";
+ samsung,pin-function = <GS101_PIN_FUNC_OUTPUT>;
+ samsung,pin-pud = <GS101_PIN_PULL_NONE>;
+ samsung,pin-drv = <GS101_PIN_DRV_2_5_MA>;
+ };
+
+ spi4_cs_func: spi4-cs-func-pins {
+ samsung,pins = "gpp8-3";
+ samsung,pin-function = <GS101_PIN_FUNC_3>;
+ samsung,pin-pud = <GS101_PIN_PULL_NONE>;
+ samsung,pin-drv = <GS101_PIN_DRV_2_5_MA>;
+ };
+
+ hsi2c3_bus: hsi2c3-bus-pins {
+ samsung,pins = "gpp6-0", "gpp6-1";
+ samsung,pin-function = <GS101_PIN_FUNC_3>;
+ samsung,pin-pud = <GS101_PIN_PULL_NONE>;
+ samsung,pin-drv = <GS101_PIN_DRV_2_5_MA>;
+ };
+
+ uart3_bus_single: uart3-bus-pins {
+ samsung,pins = "gpp6-0", "gpp6-1",
+ "gpp6-2", "gpp6-3";
+ samsung,pin-function = <GS101_PIN_FUNC_3>;
+ samsung,pin-pud = <GS101_PIN_PULL_NONE>;
+ };
+
+ spi3_bus: spi3-bus-pins {
+ samsung,pins = "gpp6-0", "gpp6-1", "gpp6-2";
+ samsung,pin-function = <GS101_PIN_FUNC_3>;
+ samsung,pin-pud = <GS101_PIN_PULL_NONE>;
+ samsung,pin-drv = <GS101_PIN_DRV_2_5_MA>;
+ };
+
+ spi3_cs: spi3-cs-pins {
+ samsung,pins = "gpp6-3";
+ samsung,pin-function = <GS101_PIN_FUNC_OUTPUT>;
+ samsung,pin-pud = <GS101_PIN_PULL_NONE>;
+ samsung,pin-drv = <GS101_PIN_DRV_2_5_MA>;
+ };
+
+ spi3_cs_func: spi3-cs-func-pins {
+ samsung,pins = "gpp6-3";
+ samsung,pin-function = <GS101_PIN_FUNC_3>;
+ samsung,pin-pud = <GS101_PIN_PULL_NONE>;
+ samsung,pin-drv = <GS101_PIN_DRV_2_5_MA>;
+ };
+
+ hsi2c2_bus: hsi2c2-bus-pins {
+ samsung,pins = "gpp4-0", "gpp4-1";
+ samsung,pin-function = <GS101_PIN_FUNC_3>;
+ samsung,pin-pud = <GS101_PIN_PULL_NONE>;
+ samsung,pin-drv = <GS101_PIN_DRV_2_5_MA>;
+ };
+
+ uart2_bus_single: uart2-bus-pins {
+ samsung,pins = "gpp4-0", "gpp4-1",
+ "gpp4-2", "gpp4-3";
+ samsung,pin-function = <GS101_PIN_FUNC_3>;
+ samsung,pin-pud = <GS101_PIN_PULL_NONE>;
+ };
+
+ spi2_bus: spi2-bus-pins {
+ samsung,pins = "gpp4-0", "gpp4-1", "gpp4-2";
+ samsung,pin-function = <GS101_PIN_FUNC_3>;
+ samsung,pin-pud = <GS101_PIN_PULL_NONE>;
+ samsung,pin-drv = <GS101_PIN_DRV_2_5_MA>;
+ };
+
+ spi2_cs: spi2-cs-pins {
+ samsung,pins = "gpp4-3";
+ samsung,pin-function = <GS101_PIN_FUNC_OUTPUT>;
+ samsung,pin-pud = <GS101_PIN_PULL_NONE>;
+ samsung,pin-drv = <GS101_PIN_DRV_2_5_MA>;
+ };
+
+ spi2_cs_func: spi2-cs-func-pins {
+ samsung,pins = "gpp4-3";
+ samsung,pin-function = <GS101_PIN_FUNC_3>;
+ samsung,pin-pud = <GS101_PIN_PULL_NONE>;
+ samsung,pin-drv = <GS101_PIN_DRV_2_5_MA>;
+ };
+
+ hsi2c1_bus: hsi2c1-bus-pins {
+ samsung,pins = "gpp2-0", "gpp2-1";
+ samsung,pin-function = <GS101_PIN_FUNC_3>;
+ samsung,pin-pud = <GS101_PIN_PULL_NONE>;
+ samsung,pin-drv = <GS101_PIN_DRV_2_5_MA>;
+ };
+
+ uart1_bus_single: uart1-bus-pins {
+ samsung,pins = "gpp2-0", "gpp2-1",
+ "gpp2-2", "gpp2-3";
+ samsung,pin-function = <GS101_PIN_FUNC_3>;
+ samsung,pin-pud = <GS101_PIN_PULL_NONE>;
+ };
+
+ spi1_bus: spi1-bus-pins {
+ samsung,pins = "gpp2-0", "gpp2-1", "gpp2-2";
+ samsung,pin-function = <GS101_PIN_FUNC_3>;
+ samsung,pin-pud = <GS101_PIN_PULL_NONE>;
+ samsung,pin-drv = <GS101_PIN_DRV_2_5_MA>;
+ };
+
+ spi1_cs: spi1-cs-pins {
+ samsung,pins = "gpp2-3";
+ samsung,pin-function = <GS101_PIN_FUNC_OUTPUT>;
+ samsung,pin-pud = <GS101_PIN_PULL_NONE>;
+ samsung,pin-drv = <GS101_PIN_DRV_2_5_MA>;
+ };
+
+ spi1_cs_func: spi1-cs-func-pins {
+ samsung,pins = "gpp2-3";
+ samsung,pin-function = <GS101_PIN_FUNC_3>;
+ samsung,pin-pud = <GS101_PIN_PULL_NONE>;
+ samsung,pin-drv = <GS101_PIN_DRV_2_5_MA>;
+ };
+};
+
+&pinctrl_peric1 {
+ gpp20: gpp20-gpio-bank {
+ gpio-controller;
+ #gpio-cells = <2>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+
+ gpp21: gpp21-gpio-bank {
+ gpio-controller;
+ #gpio-cells = <2>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+
+ gpp22: gpp22-gpio-bank {
+ gpio-controller;
+ #gpio-cells = <2>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+
+ gpp23: gpp23-gpio-bank {
+ gpio-controller;
+ #gpio-cells = <2>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+
+ gpp24: gpp24-gpio-bank {
+ gpio-controller;
+ #gpio-cells = <2>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+
+ gpp25: gpp25-gpio-bank {
+ gpio-controller;
+ #gpio-cells = <2>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+
+ gpp26: gpp26-gpio-bank {
+ gpio-controller;
+ #gpio-cells = <2>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+
+ gpp27: gpp27-gpio-bank {
+ gpio-controller;
+ #gpio-cells = <2>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+
+ hsi2c13_bus: hsi2c13-bus-pins {
+ samsung,pins = "gpp25-0", "gpp25-1";
+ samsung,pin-function = <GS101_PIN_FUNC_2>;
+ samsung,pin-pud = <GS101_PIN_PULL_NONE>;
+ samsung,pin-drv = <GS101_PIN_DRV_2_5_MA>;
+ };
+
+ uart13_bus_single: uart13-bus-pins {
+ samsung,pins = "gpp25-0", "gpp25-1",
+ "gpp25-2", "gpp25-3";
+ samsung,pin-function = <GS101_PIN_FUNC_2>;
+ samsung,pin-pud = <GS101_PIN_PULL_NONE>;
+ };
+
+ spi13_bus: spi13-bus-pins {
+ samsung,pins = "gpp25-0", "gpp25-1", "gpp25-2";
+ samsung,pin-function = <GS101_PIN_FUNC_2>;
+ samsung,pin-pud = <GS101_PIN_PULL_NONE>;
+ samsung,pin-drv = <GS101_PIN_DRV_2_5_MA>;
+ };
+
+ spi13_cs: spi13-cs-pins {
+ samsung,pins = "gpp25-3";
+ samsung,pin-function = <GS101_PIN_FUNC_OUTPUT>;
+ samsung,pin-pud = <GS101_PIN_PULL_NONE>;
+ samsung,pin-drv = <GS101_PIN_DRV_2_5_MA>;
+ };
+
+ spi13_cs_func: spi13-cs-func-pins {
+ samsung,pins = "gpp25-3";
+ samsung,pin-function = <GS101_PIN_FUNC_2>;
+ samsung,pin-pud = <GS101_PIN_PULL_NONE>;
+ samsung,pin-drv = <GS101_PIN_DRV_2_5_MA>;
+ };
+
+ hsi2c12_bus: hsi2c12-bus-pins {
+ samsung,pins = "gpp23-4", "gpp23-5";
+ samsung,pin-function = <GS101_PIN_FUNC_2>;
+ samsung,pin-pud = <GS101_PIN_PULL_NONE>;
+ samsung,pin-drv = <GS101_PIN_DRV_2_5_MA>;
+ };
+
+ uart12_bus_single: uart12-bus-pins {
+ samsung,pins = "gpp23-4", "gpp23-5",
+ "gpp23-6", "gpp23-7";
+ samsung,pin-function = <GS101_PIN_FUNC_2>;
+ samsung,pin-pud = <GS101_PIN_PULL_NONE>;
+ };
+
+ spi12_bus: spi12-bus-pins {
+ samsung,pins = "gpp23-4", "gpp23-5", "gpp23-6";
+ samsung,pin-function = <GS101_PIN_FUNC_2>;
+ samsung,pin-pud = <GS101_PIN_PULL_NONE>;
+ samsung,pin-drv = <GS101_PIN_DRV_2_5_MA>;
+ };
+
+ spi14_cs2: spi14-cs2-pins {
+ samsung,pins = "gpp23-6";
+ samsung,pin-function = <GS101_PIN_FUNC_OUTPUT>;
+ samsung,pin-pud = <GS101_PIN_PULL_NONE>;
+ samsung,pin-drv = <GS101_PIN_DRV_2_5_MA>;
+ };
+
+ spi12_cs: spi12-cs-pins {
+ samsung,pins = "gpp23-7";
+ samsung,pin-function = <GS101_PIN_FUNC_OUTPUT>;
+ samsung,pin-pud = <GS101_PIN_PULL_NONE>;
+ samsung,pin-drv = <GS101_PIN_DRV_2_5_MA>;
+ };
+
+ spi12_cs_func: spi12-cs-func-pins {
+ samsung,pins = "gpp23-7";
+ samsung,pin-function = <GS101_PIN_FUNC_2>;
+ samsung,pin-pud = <GS101_PIN_PULL_NONE>;
+ samsung,pin-drv = <GS101_PIN_DRV_2_5_MA>;
+ };
+
+ hsi2c11_bus: hsi2c11-bus-pins {
+ samsung,pins = "gpp23-0", "gpp23-1";
+ samsung,pin-function = <GS101_PIN_FUNC_2>;
+ samsung,pin-pud = <GS101_PIN_PULL_NONE>;
+ samsung,pin-drv = <GS101_PIN_DRV_2_5_MA>;
+ };
+
+ uart11_bus_single: uart11-bus-pins {
+ samsung,pins = "gpp23-0", "gpp23-1",
+ "gpp23-2", "gpp23-3";
+ samsung,pin-function = <GS101_PIN_FUNC_2>;
+ samsung,pin-pud = <GS101_PIN_PULL_NONE>;
+ };
+
+ spi11_bus: spi11-bus-pins {
+ samsung,pins = "gpp23-0", "gpp23-1", "gpp23-2";
+ samsung,pin-function = <GS101_PIN_FUNC_2>;
+ samsung,pin-pud = <GS101_PIN_PULL_NONE>;
+ samsung,pin-drv = <GS101_PIN_DRV_2_5_MA>;
+ };
+
+ spi11_cs: spi11-cs-pins {
+ samsung,pins = "gpp23-3";
+ samsung,pin-function = <GS101_PIN_FUNC_OUTPUT>;
+ samsung,pin-pud = <GS101_PIN_PULL_NONE>;
+ samsung,pin-drv = <GS101_PIN_DRV_2_5_MA>;
+ };
+
+ spi11_cs_func: spi11-cs-func-pins {
+ samsung,pins = "gpp23-3";
+ samsung,pin-function = <GS101_PIN_FUNC_2>;
+ samsung,pin-pud = <GS101_PIN_PULL_NONE>;
+ samsung,pin-drv = <GS101_PIN_DRV_2_5_MA>;
+ };
+
+ hsi2c10_bus: hsi2c10-bus-pins {
+ samsung,pins = "gpp21-0", "gpp21-1";
+ samsung,pin-function = <GS101_PIN_FUNC_2>;
+ samsung,pin-pud = <GS101_PIN_PULL_NONE>;
+ samsung,pin-drv = <GS101_PIN_DRV_2_5_MA>;
+ };
+
+ uart10_bus_single: uart10-bus-pins {
+ samsung,pins = "gpp21-0", "gpp21-1",
+ "gpp21-2", "gpp21-3";
+ samsung,pin-function = <GS101_PIN_FUNC_2>;
+ samsung,pin-pud = <GS101_PIN_PULL_NONE>;
+ };
+
+ spi10_bus: spi10-bus-pins {
+ samsung,pins = "gpp21-0", "gpp21-1", "gpp21-2";
+ samsung,pin-function = <GS101_PIN_FUNC_2>;
+ samsung,pin-pud = <GS101_PIN_PULL_NONE>;
+ samsung,pin-drv = <GS101_PIN_DRV_2_5_MA>;
+ };
+
+ spi10_cs: spi10-cs-pins {
+ samsung,pins = "gpp21-3";
+ samsung,pin-function = <GS101_PIN_FUNC_OUTPUT>;
+ samsung,pin-pud = <GS101_PIN_PULL_NONE>;
+ samsung,pin-drv = <GS101_PIN_DRV_2_5_MA>;
+ };
+
+ spi10_cs_func: spi10-cs-func-pins {
+ samsung,pins = "gpp21-3";
+ samsung,pin-function = <GS101_PIN_FUNC_2>;
+ samsung,pin-pud = <GS101_PIN_PULL_NONE>;
+ samsung,pin-drv = <GS101_PIN_DRV_2_5_MA>;
+ };
+
+ hsi2c9_bus: hsi2c9-bus-pins {
+ samsung,pins = "gpp20-4", "gpp20-5";
+ samsung,pin-function = <GS101_PIN_FUNC_2>;
+ samsung,pin-pud = <GS101_PIN_PULL_NONE>;
+ samsung,pin-drv = <GS101_PIN_DRV_2_5_MA>;
+ };
+
+ uart9_bus_single: uart9-bus-pins {
+ samsung,pins = "gpp20-4", "gpp20-5",
+ "gpp20-6", "gpp20-7";
+ samsung,pin-function = <GS101_PIN_FUNC_2>;
+ samsung,pin-pud = <GS101_PIN_PULL_NONE>;
+ };
+
+ spi9_bus: spi9-bus-pins {
+ samsung,pins = "gpp20-4", "gpp20-5", "gpp20-6";
+ samsung,pin-function = <GS101_PIN_FUNC_2>;
+ samsung,pin-pud = <GS101_PIN_PULL_NONE>;
+ samsung,pin-drv = <GS101_PIN_DRV_2_5_MA>;
+ };
+
+ spi9_cs: spi9-cs-pins {
+ samsung,pins = "gpp20-7";
+ samsung,pin-function = <GS101_PIN_FUNC_OUTPUT>;
+ samsung,pin-pud = <GS101_PIN_PULL_NONE>;
+ samsung,pin-drv = <GS101_PIN_DRV_2_5_MA>;
+ };
+
+ spi9_cs_func: spi9-cs-func-pins {
+ samsung,pins = "gpp20-7";
+ samsung,pin-function = <GS101_PIN_FUNC_2>;
+ samsung,pin-pud = <GS101_PIN_PULL_NONE>;
+ samsung,pin-drv = <GS101_PIN_DRV_2_5_MA>;
+ };
+
+ hsi2c0_bus: hsi2c0-bus-pins {
+ samsung,pins = "gpp20-0", "gpp20-1";
+ samsung,pin-function = <GS101_PIN_FUNC_3>;
+ samsung,pin-pud = <GS101_PIN_PULL_NONE>;
+ samsung,pin-drv = <GS101_PIN_DRV_2_5_MA>;
+ };
+
+ uart0_bus_single: uart0-bus-pins {
+ samsung,pins = "gpp20-0", "gpp20-1",
+ "gpp20-2", "gpp20-3";
+ samsung,pin-function = <GS101_PIN_FUNC_3>;
+ samsung,pin-pud = <GS101_PIN_PULL_NONE>;
+ };
+
+ spi0_bus: spi0-bus-pins {
+ samsung,pins = "gpp20-0", "gpp20-1", "gpp20-2";
+ samsung,pin-function = <GS101_PIN_FUNC_3>;
+ samsung,pin-pud = <GS101_PIN_PULL_NONE>;
+ samsung,pin-drv = <GS101_PIN_DRV_2_5_MA>;
+ };
+
+ spi0_cs: spi0-cs-pins {
+ samsung,pins = "gpp20-3";
+ samsung,pin-function = <GS101_PIN_FUNC_OUTPUT>;
+ samsung,pin-pud = <GS101_PIN_PULL_NONE>;
+ samsung,pin-drv = <GS101_PIN_DRV_2_5_MA>;
+ };
+
+ spi0_cs_func: spi0-cs-func-pins {
+ samsung,pins = "gpp20-3";
+ samsung,pin-function = <GS101_PIN_FUNC_3>;
+ samsung,pin-pud = <GS101_PIN_PULL_NONE>;
+ samsung,pin-drv = <GS101_PIN_DRV_2_5_MA>;
+ };
+};
diff --git a/dts/upstream/src/arm64/exynos/google/gs101-pinctrl.h b/dts/upstream/src/arm64/exynos/google/gs101-pinctrl.h
new file mode 100644
index 0000000..b7d276b
--- /dev/null
+++ b/dts/upstream/src/arm64/exynos/google/gs101-pinctrl.h
@@ -0,0 +1,33 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Pinctrl binding constants for GS101
+ *
+ * Copyright 2020-2023 Google LLC
+ */
+
+#ifndef __DTS_ARM64_SAMSUNG_EXYNOS_GOOGLE_PINCTRL_GS101_H__
+#define __DTS_ARM64_SAMSUNG_EXYNOS_GOOGLE_PINCTRL_GS101_H__
+
+#define GS101_PIN_PULL_NONE 0
+#define GS101_PIN_PULL_DOWN 1
+#define GS101_PIN_PULL_UP 3
+
+/* Pin function in power down mode */
+#define GS101_PIN_PDN_OUT0 0
+#define GS101_PIN_PDN_OUT1 1
+#define GS101_PIN_PDN_INPUT 2
+#define GS101_PIN_PDN_PREV 3
+
+/* GS101 drive strengths */
+#define GS101_PIN_DRV_2_5_MA 0
+#define GS101_PIN_DRV_5_MA 1
+#define GS101_PIN_DRV_7_5_MA 2
+#define GS101_PIN_DRV_10_MA 3
+
+#define GS101_PIN_FUNC_INPUT 0
+#define GS101_PIN_FUNC_OUTPUT 1
+#define GS101_PIN_FUNC_2 2
+#define GS101_PIN_FUNC_3 3
+#define GS101_PIN_FUNC_EINT 0xf
+
+#endif /* __DTS_ARM64_SAMSUNG_EXYNOS_GOOGLE_PINCTRL_GS101_H__ */
diff --git a/dts/upstream/src/arm64/exynos/google/gs101.dtsi b/dts/upstream/src/arm64/exynos/google/gs101.dtsi
new file mode 100644
index 0000000..d838e3a
--- /dev/null
+++ b/dts/upstream/src/arm64/exynos/google/gs101.dtsi
@@ -0,0 +1,473 @@
+// SPDX-License-Identifier: GPL-2.0-only
+/*
+ * GS101 SoC
+ *
+ * Copyright 2019-2023 Google LLC
+ * Copyright 2023 Linaro Ltd - <peter.griffin@linaro.org>
+ */
+
+#include <dt-bindings/clock/google,gs101.h>
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/interrupt-controller/arm-gic.h>
+#include <dt-bindings/soc/samsung,exynos-usi.h>
+
+/ {
+ compatible = "google,gs101";
+ #address-cells = <2>;
+ #size-cells = <1>;
+
+ interrupt-parent = <&gic>;
+
+ aliases {
+ pinctrl0 = &pinctrl_gpio_alive;
+ pinctrl1 = &pinctrl_far_alive;
+ pinctrl2 = &pinctrl_gsacore;
+ pinctrl3 = &pinctrl_gsactrl;
+ pinctrl4 = &pinctrl_peric0;
+ pinctrl5 = &pinctrl_peric1;
+ pinctrl6 = &pinctrl_hsi1;
+ pinctrl7 = &pinctrl_hsi2;
+ };
+
+ cpus {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ cpu-map {
+ cluster0 {
+ core0 {
+ cpu = <&cpu0>;
+ };
+ core1 {
+ cpu = <&cpu1>;
+ };
+ core2 {
+ cpu = <&cpu2>;
+ };
+ core3 {
+ cpu = <&cpu3>;
+ };
+ };
+
+ cluster1 {
+ core0 {
+ cpu = <&cpu4>;
+ };
+ core1 {
+ cpu = <&cpu5>;
+ };
+ };
+
+ cluster2 {
+ core0 {
+ cpu = <&cpu6>;
+ };
+ core1 {
+ cpu = <&cpu7>;
+ };
+ };
+ };
+
+ cpu0: cpu@0 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a55";
+ reg = <0x0000>;
+ enable-method = "psci";
+ cpu-idle-states = <&ANANKE_CPU_SLEEP>;
+ capacity-dmips-mhz = <250>;
+ dynamic-power-coefficient = <70>;
+ };
+
+ cpu1: cpu@100 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a55";
+ reg = <0x0100>;
+ enable-method = "psci";
+ cpu-idle-states = <&ANANKE_CPU_SLEEP>;
+ capacity-dmips-mhz = <250>;
+ dynamic-power-coefficient = <70>;
+ };
+
+ cpu2: cpu@200 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a55";
+ reg = <0x0200>;
+ enable-method = "psci";
+ cpu-idle-states = <&ANANKE_CPU_SLEEP>;
+ capacity-dmips-mhz = <250>;
+ dynamic-power-coefficient = <70>;
+ };
+
+ cpu3: cpu@300 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a55";
+ reg = <0x0300>;
+ enable-method = "psci";
+ cpu-idle-states = <&ANANKE_CPU_SLEEP>;
+ capacity-dmips-mhz = <250>;
+ dynamic-power-coefficient = <70>;
+ };
+
+ cpu4: cpu@400 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a76";
+ reg = <0x0400>;
+ enable-method = "psci";
+ cpu-idle-states = <&ENYO_CPU_SLEEP>;
+ capacity-dmips-mhz = <620>;
+ dynamic-power-coefficient = <284>;
+ };
+
+ cpu5: cpu@500 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a76";
+ reg = <0x0500>;
+ enable-method = "psci";
+ cpu-idle-states = <&ENYO_CPU_SLEEP>;
+ capacity-dmips-mhz = <620>;
+ dynamic-power-coefficient = <284>;
+ };
+
+ cpu6: cpu@600 {
+ device_type = "cpu";
+ compatible = "arm,cortex-x1";
+ reg = <0x0600>;
+ enable-method = "psci";
+ cpu-idle-states = <&HERA_CPU_SLEEP>;
+ capacity-dmips-mhz = <1024>;
+ dynamic-power-coefficient = <650>;
+ };
+
+ cpu7: cpu@700 {
+ device_type = "cpu";
+ compatible = "arm,cortex-x1";
+ reg = <0x0700>;
+ enable-method = "psci";
+ cpu-idle-states = <&HERA_CPU_SLEEP>;
+ capacity-dmips-mhz = <1024>;
+ dynamic-power-coefficient = <650>;
+ };
+
+ idle-states {
+ entry-method = "psci";
+
+ ANANKE_CPU_SLEEP: cpu-ananke-sleep {
+ idle-state-name = "c2";
+ compatible = "arm,idle-state";
+ arm,psci-suspend-param = <0x0010000>;
+ entry-latency-us = <70>;
+ exit-latency-us = <160>;
+ min-residency-us = <2000>;
+ };
+
+ ENYO_CPU_SLEEP: cpu-enyo-sleep {
+ idle-state-name = "c2";
+ compatible = "arm,idle-state";
+ arm,psci-suspend-param = <0x0010000>;
+ entry-latency-us = <150>;
+ exit-latency-us = <190>;
+ min-residency-us = <2500>;
+ };
+
+ HERA_CPU_SLEEP: cpu-hera-sleep {
+ idle-state-name = "c2";
+ compatible = "arm,idle-state";
+ arm,psci-suspend-param = <0x0010000>;
+ entry-latency-us = <235>;
+ exit-latency-us = <220>;
+ min-residency-us = <3500>;
+ };
+ };
+ };
+
+ /* TODO replace with CCF clock */
+ dummy_clk: clock-3 {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <12345>;
+ clock-output-names = "pclk";
+ };
+
+ /* ect node is required to be present by bootloader */
+ ect {
+ };
+
+ ext_24_5m: clock-1 {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-output-names = "oscclk";
+ };
+
+ ext_200m: clock-2 {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-output-names = "ext-200m";
+ };
+
+ pmu-0 {
+ compatible = "arm,cortex-a55-pmu";
+ interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH &ppi_cluster0>;
+ };
+
+ pmu-1 {
+ compatible = "arm,cortex-a76-pmu";
+ interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH &ppi_cluster1>;
+ };
+
+ pmu-2 {
+ compatible = "arm,cortex-x1-pmu";
+ interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH &ppi_cluster2>;
+ };
+
+ pmu-3 {
+ compatible = "arm,dsu-pmu";
+ interrupts = <GIC_SPI 257 IRQ_TYPE_LEVEL_HIGH 0>;
+ cpus = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>,
+ <&cpu4>, <&cpu5>, <&cpu6>, <&cpu7>;
+ };
+
+ psci {
+ compatible = "arm,psci-1.0";
+ method = "smc";
+ };
+
+ reserved_memory: reserved-memory {
+ #address-cells = <2>;
+ #size-cells = <1>;
+ ranges;
+
+ gsa_reserved_protected: gsa@90200000 {
+ reg = <0x0 0x90200000 0x400000>;
+ no-map;
+ };
+
+ tpu_fw_reserved: tpu-fw@93000000 {
+ reg = <0x0 0x93000000 0x1000000>;
+ no-map;
+ };
+
+ aoc_reserve: aoc@94000000 {
+ reg = <0x0 0x94000000 0x03000000>;
+ no-map;
+ };
+
+ abl_reserved: abl@f8800000 {
+ reg = <0x0 0xf8800000 0x02000000>;
+ no-map;
+ };
+
+ dss_log_reserved: dss-log-reserved@fd3f0000 {
+ reg = <0x0 0xfd3f0000 0x0000e000>;
+ no-map;
+ };
+
+ debug_kinfo_reserved: debug-kinfo-reserved@fd3fe000 {
+ reg = <0x0 0xfd3fe000 0x00001000>;
+ no-map;
+ };
+
+ bldr_log_reserved: bldr-log-reserved@fd800000 {
+ reg = <0x0 0xfd800000 0x00100000>;
+ no-map;
+ };
+
+ bldr_log_hist_reserved: bldr-log-hist-reserved@fd900000 {
+ reg = <0x0 0xfd900000 0x00002000>;
+ no-map;
+ };
+ };
+
+ soc: soc@0 {
+ compatible = "simple-bus";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0x0 0x0 0x0 0x40000000>;
+
+ cmu_misc: clock-controller@10010000 {
+ compatible = "google,gs101-cmu-misc";
+ reg = <0x10010000 0x8000>;
+ #clock-cells = <1>;
+ clocks = <&cmu_top CLK_DOUT_CMU_MISC_BUS>,
+ <&cmu_top CLK_DOUT_CMU_MISC_SSS>;
+ clock-names = "bus", "sss";
+ };
+
+ watchdog_cl0: watchdog@10060000 {
+ compatible = "google,gs101-wdt";
+ reg = <0x10060000 0x100>;
+ interrupts = <GIC_SPI 765 IRQ_TYPE_LEVEL_HIGH 0>;
+ clocks = <&cmu_misc CLK_GOUT_MISC_WDT_CLUSTER0_PCLK>,
+ <&ext_24_5m>;
+ clock-names = "watchdog", "watchdog_src";
+ samsung,syscon-phandle = <&pmu_system_controller>;
+ samsung,cluster-index = <0>;
+ status = "disabled";
+ };
+
+ watchdog_cl1: watchdog@10070000 {
+ compatible = "google,gs101-wdt";
+ reg = <0x10070000 0x100>;
+ interrupts = <GIC_SPI 766 IRQ_TYPE_LEVEL_HIGH 0>;
+ clocks = <&cmu_misc CLK_GOUT_MISC_WDT_CLUSTER1_PCLK>,
+ <&ext_24_5m>;
+ clock-names = "watchdog", "watchdog_src";
+ samsung,syscon-phandle = <&pmu_system_controller>;
+ samsung,cluster-index = <1>;
+ status = "disabled";
+ };
+
+ gic: interrupt-controller@10400000 {
+ compatible = "arm,gic-v3";
+ #interrupt-cells = <4>;
+ interrupt-controller;
+ reg = <0x10400000 0x10000>, /* GICD */
+ <0x10440000 0x100000>;/* GICR * 8 */
+ interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH 0>;
+
+ ppi-partitions {
+ ppi_cluster0: interrupt-partition-0 {
+ affinity = <&cpu0 &cpu1 &cpu2 &cpu3>;
+ };
+
+ ppi_cluster1: interrupt-partition-1 {
+ affinity = <&cpu4 &cpu5>;
+ };
+
+ ppi_cluster2: interrupt-partition-2 {
+ affinity = <&cpu6 &cpu7>;
+ };
+ };
+ };
+
+ sysreg_peric0: syscon@10820000 {
+ compatible = "google,gs101-peric0-sysreg", "syscon";
+ reg = <0x10820000 0x10000>;
+ };
+
+ pinctrl_peric0: pinctrl@10840000 {
+ compatible = "google,gs101-pinctrl";
+ reg = <0x10840000 0x00001000>;
+ interrupts = <GIC_SPI 625 IRQ_TYPE_LEVEL_HIGH 0>;
+ };
+
+ usi_uart: usi@10a000c0 {
+ compatible = "google,gs101-usi",
+ "samsung,exynos850-usi";
+ reg = <0x10a000c0 0x20>;
+ ranges;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ clocks = <&dummy_clk>, <&dummy_clk>;
+ clock-names = "pclk", "ipclk";
+ samsung,sysreg = <&sysreg_peric0 0x1020>;
+ samsung,mode = <USI_V2_UART>;
+ status = "disabled";
+
+ serial_0: serial@10a00000 {
+ compatible = "google,gs101-uart";
+ reg = <0x10a00000 0xc0>;
+ reg-io-width = <4>;
+ interrupts = <GIC_SPI 634
+ IRQ_TYPE_LEVEL_HIGH 0>;
+ clocks = <&dummy_clk 0>, <&dummy_clk 0>;
+ clock-names = "uart", "clk_uart_baud0";
+ samsung,uart-fifosize = <256>;
+ status = "disabled";
+ };
+ };
+
+ sysreg_peric1: syscon@10c20000 {
+ compatible = "google,gs101-peric1-sysreg", "syscon";
+ reg = <0x10c20000 0x10000>;
+ };
+
+ pinctrl_peric1: pinctrl@10c40000 {
+ compatible = "google,gs101-pinctrl";
+ reg = <0x10c40000 0x00001000>;
+ interrupts = <GIC_SPI 644 IRQ_TYPE_LEVEL_HIGH 0>;
+ };
+
+ pinctrl_hsi1: pinctrl@11840000 {
+ compatible = "google,gs101-pinctrl";
+ reg = <0x11840000 0x00001000>;
+ interrupts = <GIC_SPI 471 IRQ_TYPE_LEVEL_HIGH 0>;
+ };
+
+ pinctrl_hsi2: pinctrl@14440000 {
+ compatible = "google,gs101-pinctrl";
+ reg = <0x14440000 0x00001000>;
+ interrupts = <GIC_SPI 503 IRQ_TYPE_LEVEL_HIGH 0>;
+ };
+
+ cmu_apm: clock-controller@17400000 {
+ compatible = "google,gs101-cmu-apm";
+ reg = <0x17400000 0x8000>;
+ #clock-cells = <1>;
+
+ clocks = <&ext_24_5m>;
+ clock-names = "oscclk";
+ };
+
+ sysreg_apm: syscon@174204e0 {
+ compatible = "google,gs101-apm-sysreg", "syscon";
+ reg = <0x174204e0 0x1000>;
+ };
+
+ pmu_system_controller: system-controller@17460000 {
+ compatible = "google,gs101-pmu", "syscon";
+ reg = <0x17460000 0x10000>;
+ };
+
+ pinctrl_gpio_alive: pinctrl@174d0000 {
+ compatible = "google,gs101-pinctrl";
+ reg = <0x174d0000 0x00001000>;
+
+ wakeup-interrupt-controller {
+ compatible = "google,gs101-wakeup-eint",
+ "samsung,exynos850-wakeup-eint",
+ "samsung,exynos7-wakeup-eint";
+ };
+ };
+
+ pinctrl_far_alive: pinctrl@174e0000 {
+ compatible = "google,gs101-pinctrl";
+ reg = <0x174e0000 0x00001000>;
+
+ wakeup-interrupt-controller {
+ compatible = "google,gs101-wakeup-eint",
+ "samsung,exynos850-wakeup-eint",
+ "samsung,exynos7-wakeup-eint";
+ };
+ };
+
+ pinctrl_gsactrl: pinctrl@17940000 {
+ compatible = "google,gs101-pinctrl";
+ reg = <0x17940000 0x00001000>;
+ };
+
+ pinctrl_gsacore: pinctrl@17a80000 {
+ compatible = "google,gs101-pinctrl";
+ reg = <0x17a80000 0x00001000>;
+ };
+
+ cmu_top: clock-controller@1e080000 {
+ compatible = "google,gs101-cmu-top";
+ reg = <0x1e080000 0x8000>;
+ #clock-cells = <1>;
+
+ clocks = <&ext_24_5m>;
+ clock-names = "oscclk";
+ };
+ };
+
+ timer {
+ compatible = "arm,armv8-timer";
+ interrupts =
+ <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW) 0>,
+ <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW) 0>,
+ <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW) 0>,
+ <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW) 0>;
+ };
+};
+
+#include "gs101-pinctrl.dtsi"
diff --git a/dts/upstream/src/arm64/freescale/fsl-ls1012a.dtsi b/dts/upstream/src/arm64/freescale/fsl-ls1012a.dtsi
index a863022..1e3fe38 100644
--- a/dts/upstream/src/arm64/freescale/fsl-ls1012a.dtsi
+++ b/dts/upstream/src/arm64/freescale/fsl-ls1012a.dtsi
@@ -307,46 +307,46 @@
reg = <0x0 0x1f00000 0x0 0x10000>;
interrupts = <0 33 0x4>;
fsl,tmu-range = <0xb0000 0x9002a 0x6004c 0x60062>;
- fsl,tmu-calibration = <0x00000000 0x00000025
- 0x00000001 0x0000002c
- 0x00000002 0x00000032
- 0x00000003 0x00000039
- 0x00000004 0x0000003f
- 0x00000005 0x00000046
- 0x00000006 0x0000004c
- 0x00000007 0x00000053
- 0x00000008 0x00000059
- 0x00000009 0x0000005f
- 0x0000000a 0x00000066
- 0x0000000b 0x0000006c
+ fsl,tmu-calibration =
+ <0x00000000 0x00000025>,
+ <0x00000001 0x0000002c>,
+ <0x00000002 0x00000032>,
+ <0x00000003 0x00000039>,
+ <0x00000004 0x0000003f>,
+ <0x00000005 0x00000046>,
+ <0x00000006 0x0000004c>,
+ <0x00000007 0x00000053>,
+ <0x00000008 0x00000059>,
+ <0x00000009 0x0000005f>,
+ <0x0000000a 0x00000066>,
+ <0x0000000b 0x0000006c>,
- 0x00010000 0x00000026
- 0x00010001 0x0000002d
- 0x00010002 0x00000035
- 0x00010003 0x0000003d
- 0x00010004 0x00000045
- 0x00010005 0x0000004d
- 0x00010006 0x00000055
- 0x00010007 0x0000005d
- 0x00010008 0x00000065
- 0x00010009 0x0000006d
+ <0x00010000 0x00000026>,
+ <0x00010001 0x0000002d>,
+ <0x00010002 0x00000035>,
+ <0x00010003 0x0000003d>,
+ <0x00010004 0x00000045>,
+ <0x00010005 0x0000004d>,
+ <0x00010006 0x00000055>,
+ <0x00010007 0x0000005d>,
+ <0x00010008 0x00000065>,
+ <0x00010009 0x0000006d>,
- 0x00020000 0x00000026
- 0x00020001 0x00000030
- 0x00020002 0x0000003a
- 0x00020003 0x00000044
- 0x00020004 0x0000004e
- 0x00020005 0x00000059
- 0x00020006 0x00000063
+ <0x00020000 0x00000026>,
+ <0x00020001 0x00000030>,
+ <0x00020002 0x0000003a>,
+ <0x00020003 0x00000044>,
+ <0x00020004 0x0000004e>,
+ <0x00020005 0x00000059>,
+ <0x00020006 0x00000063>,
- 0x00030000 0x00000014
- 0x00030001 0x00000021
- 0x00030002 0x0000002e
- 0x00030003 0x0000003a
- 0x00030004 0x00000047
- 0x00030005 0x00000053
- 0x00030006 0x00000060>;
- big-endian;
+ <0x00030000 0x00000014>,
+ <0x00030001 0x00000021>,
+ <0x00030002 0x0000002e>,
+ <0x00030003 0x0000003a>,
+ <0x00030004 0x00000047>,
+ <0x00030005 0x00000053>,
+ <0x00030006 0x00000060>;
#thermal-sensor-cells = <1>;
};
diff --git a/dts/upstream/src/arm64/freescale/fsl-ls1028a.dtsi b/dts/upstream/src/arm64/freescale/fsl-ls1028a.dtsi
index eefe357..ae534c2 100644
--- a/dts/upstream/src/arm64/freescale/fsl-ls1028a.dtsi
+++ b/dts/upstream/src/arm64/freescale/fsl-ls1028a.dtsi
@@ -1026,49 +1026,50 @@
reg = <0x0 0x1f80000 0x0 0x10000>;
interrupts = <0 23 0x4>;
fsl,tmu-range = <0xb0000 0xa0026 0x80048 0x70061>;
- fsl,tmu-calibration = <0x00000000 0x00000024
- 0x00000001 0x0000002b
- 0x00000002 0x00000031
- 0x00000003 0x00000038
- 0x00000004 0x0000003f
- 0x00000005 0x00000045
- 0x00000006 0x0000004c
- 0x00000007 0x00000053
- 0x00000008 0x00000059
- 0x00000009 0x00000060
- 0x0000000a 0x00000066
- 0x0000000b 0x0000006d
+ fsl,tmu-calibration =
+ <0x00000000 0x00000024>,
+ <0x00000001 0x0000002b>,
+ <0x00000002 0x00000031>,
+ <0x00000003 0x00000038>,
+ <0x00000004 0x0000003f>,
+ <0x00000005 0x00000045>,
+ <0x00000006 0x0000004c>,
+ <0x00000007 0x00000053>,
+ <0x00000008 0x00000059>,
+ <0x00000009 0x00000060>,
+ <0x0000000a 0x00000066>,
+ <0x0000000b 0x0000006d>,
- 0x00010000 0x0000001c
- 0x00010001 0x00000024
- 0x00010002 0x0000002c
- 0x00010003 0x00000035
- 0x00010004 0x0000003d
- 0x00010005 0x00000045
- 0x00010006 0x0000004d
- 0x00010007 0x00000055
- 0x00010008 0x0000005e
- 0x00010009 0x00000066
- 0x0001000a 0x0000006e
+ <0x00010000 0x0000001c>,
+ <0x00010001 0x00000024>,
+ <0x00010002 0x0000002c>,
+ <0x00010003 0x00000035>,
+ <0x00010004 0x0000003d>,
+ <0x00010005 0x00000045>,
+ <0x00010006 0x0000004d>,
+ <0x00010007 0x00000055>,
+ <0x00010008 0x0000005e>,
+ <0x00010009 0x00000066>,
+ <0x0001000a 0x0000006e>,
- 0x00020000 0x00000018
- 0x00020001 0x00000022
- 0x00020002 0x0000002d
- 0x00020003 0x00000038
- 0x00020004 0x00000043
- 0x00020005 0x0000004d
- 0x00020006 0x00000058
- 0x00020007 0x00000063
- 0x00020008 0x0000006e
+ <0x00020000 0x00000018>,
+ <0x00020001 0x00000022>,
+ <0x00020002 0x0000002d>,
+ <0x00020003 0x00000038>,
+ <0x00020004 0x00000043>,
+ <0x00020005 0x0000004d>,
+ <0x00020006 0x00000058>,
+ <0x00020007 0x00000063>,
+ <0x00020008 0x0000006e>,
- 0x00030000 0x00000010
- 0x00030001 0x0000001c
- 0x00030002 0x00000029
- 0x00030003 0x00000036
- 0x00030004 0x00000042
- 0x00030005 0x0000004f
- 0x00030006 0x0000005b
- 0x00030007 0x00000068>;
+ <0x00030000 0x00000010>,
+ <0x00030001 0x0000001c>,
+ <0x00030002 0x00000029>,
+ <0x00030003 0x00000036>,
+ <0x00030004 0x00000042>,
+ <0x00030005 0x0000004f>,
+ <0x00030006 0x0000005b>,
+ <0x00030007 0x00000068>;
little-endian;
#thermal-sensor-cells = <1>;
};
diff --git a/dts/upstream/src/arm64/freescale/fsl-ls1043a.dtsi b/dts/upstream/src/arm64/freescale/fsl-ls1043a.dtsi
index 229bb4b..d333b77 100644
--- a/dts/upstream/src/arm64/freescale/fsl-ls1043a.dtsi
+++ b/dts/upstream/src/arm64/freescale/fsl-ls1043a.dtsi
@@ -447,46 +447,47 @@
reg = <0x0 0x1f00000 0x0 0x10000>;
interrupts = <0 33 0x4>;
fsl,tmu-range = <0xb0000 0x9002a 0x6004c 0x70062>;
- fsl,tmu-calibration = <0x00000000 0x00000023
- 0x00000001 0x0000002a
- 0x00000002 0x00000031
- 0x00000003 0x00000037
- 0x00000004 0x0000003e
- 0x00000005 0x00000044
- 0x00000006 0x0000004b
- 0x00000007 0x00000051
- 0x00000008 0x00000058
- 0x00000009 0x0000005e
- 0x0000000a 0x00000065
- 0x0000000b 0x0000006b
+ fsl,tmu-calibration =
+ <0x00000000 0x00000023>,
+ <0x00000001 0x0000002a>,
+ <0x00000002 0x00000031>,
+ <0x00000003 0x00000037>,
+ <0x00000004 0x0000003e>,
+ <0x00000005 0x00000044>,
+ <0x00000006 0x0000004b>,
+ <0x00000007 0x00000051>,
+ <0x00000008 0x00000058>,
+ <0x00000009 0x0000005e>,
+ <0x0000000a 0x00000065>,
+ <0x0000000b 0x0000006b>,
- 0x00010000 0x00000023
- 0x00010001 0x0000002b
- 0x00010002 0x00000033
- 0x00010003 0x0000003b
- 0x00010004 0x00000043
- 0x00010005 0x0000004b
- 0x00010006 0x00000054
- 0x00010007 0x0000005c
- 0x00010008 0x00000064
- 0x00010009 0x0000006c
+ <0x00010000 0x00000023>,
+ <0x00010001 0x0000002b>,
+ <0x00010002 0x00000033>,
+ <0x00010003 0x0000003b>,
+ <0x00010004 0x00000043>,
+ <0x00010005 0x0000004b>,
+ <0x00010006 0x00000054>,
+ <0x00010007 0x0000005c>,
+ <0x00010008 0x00000064>,
+ <0x00010009 0x0000006c>,
- 0x00020000 0x00000021
- 0x00020001 0x0000002c
- 0x00020002 0x00000036
- 0x00020003 0x00000040
- 0x00020004 0x0000004b
- 0x00020005 0x00000055
- 0x00020006 0x0000005f
+ <0x00020000 0x00000021>,
+ <0x00020001 0x0000002c>,
+ <0x00020002 0x00000036>,
+ <0x00020003 0x00000040>,
+ <0x00020004 0x0000004b>,
+ <0x00020005 0x00000055>,
+ <0x00020006 0x0000005f>,
- 0x00030000 0x00000013
- 0x00030001 0x0000001d
- 0x00030002 0x00000028
- 0x00030003 0x00000032
- 0x00030004 0x0000003d
- 0x00030005 0x00000047
- 0x00030006 0x00000052
- 0x00030007 0x0000005c>;
+ <0x00030000 0x00000013>,
+ <0x00030001 0x0000001d>,
+ <0x00030002 0x00000028>,
+ <0x00030003 0x00000032>,
+ <0x00030004 0x0000003d>,
+ <0x00030005 0x00000047>,
+ <0x00030006 0x00000052>,
+ <0x00030007 0x0000005c>;
#thermal-sensor-cells = <1>;
};
diff --git a/dts/upstream/src/arm64/freescale/fsl-ls1046a.dtsi b/dts/upstream/src/arm64/freescale/fsl-ls1046a.dtsi
index 50f68ca..1515cec 100644
--- a/dts/upstream/src/arm64/freescale/fsl-ls1046a.dtsi
+++ b/dts/upstream/src/arm64/freescale/fsl-ls1046a.dtsi
@@ -445,46 +445,46 @@
fsl,tmu-range = <0xb0000 0x9002a 0x6004c 0x70062>;
fsl,tmu-calibration =
/* Calibration data group 1 */
- <0x00000000 0x00000023
- 0x00000001 0x00000029
- 0x00000002 0x0000002f
- 0x00000003 0x00000036
- 0x00000004 0x0000003c
- 0x00000005 0x00000042
- 0x00000006 0x00000049
- 0x00000007 0x0000004f
- 0x00000008 0x00000055
- 0x00000009 0x0000005c
- 0x0000000a 0x00000062
- 0x0000000b 0x00000068
+ <0x00000000 0x00000023>,
+ <0x00000001 0x00000029>,
+ <0x00000002 0x0000002f>,
+ <0x00000003 0x00000036>,
+ <0x00000004 0x0000003c>,
+ <0x00000005 0x00000042>,
+ <0x00000006 0x00000049>,
+ <0x00000007 0x0000004f>,
+ <0x00000008 0x00000055>,
+ <0x00000009 0x0000005c>,
+ <0x0000000a 0x00000062>,
+ <0x0000000b 0x00000068>,
/* Calibration data group 2 */
- 0x00010000 0x00000022
- 0x00010001 0x0000002a
- 0x00010002 0x00000032
- 0x00010003 0x0000003a
- 0x00010004 0x00000042
- 0x00010005 0x0000004a
- 0x00010006 0x00000052
- 0x00010007 0x0000005a
- 0x00010008 0x00000062
- 0x00010009 0x0000006a
+ <0x00010000 0x00000022>,
+ <0x00010001 0x0000002a>,
+ <0x00010002 0x00000032>,
+ <0x00010003 0x0000003a>,
+ <0x00010004 0x00000042>,
+ <0x00010005 0x0000004a>,
+ <0x00010006 0x00000052>,
+ <0x00010007 0x0000005a>,
+ <0x00010008 0x00000062>,
+ <0x00010009 0x0000006a>,
/* Calibration data group 3 */
- 0x00020000 0x00000021
- 0x00020001 0x0000002b
- 0x00020002 0x00000035
- 0x00020003 0x0000003e
- 0x00020004 0x00000048
- 0x00020005 0x00000052
- 0x00020006 0x0000005c
+ <0x00020000 0x00000021>,
+ <0x00020001 0x0000002b>,
+ <0x00020002 0x00000035>,
+ <0x00020003 0x0000003e>,
+ <0x00020004 0x00000048>,
+ <0x00020005 0x00000052>,
+ <0x00020006 0x0000005c>,
/* Calibration data group 4 */
- 0x00030000 0x00000011
- 0x00030001 0x0000001a
- 0x00030002 0x00000024
- 0x00030003 0x0000002e
- 0x00030004 0x00000038
- 0x00030005 0x00000042
- 0x00030006 0x0000004c
- 0x00030007 0x00000056>;
+ <0x00030000 0x00000011>,
+ <0x00030001 0x0000001a>,
+ <0x00030002 0x00000024>,
+ <0x00030003 0x0000002e>,
+ <0x00030004 0x00000038>,
+ <0x00030005 0x00000042>,
+ <0x00030006 0x0000004c>,
+ <0x00030007 0x00000056>;
big-endian;
#thermal-sensor-cells = <1>;
};
diff --git a/dts/upstream/src/arm64/freescale/fsl-ls1088a.dtsi b/dts/upstream/src/arm64/freescale/fsl-ls1088a.dtsi
index 8f6090a..8616d5e 100644
--- a/dts/upstream/src/arm64/freescale/fsl-ls1088a.dtsi
+++ b/dts/upstream/src/arm64/freescale/fsl-ls1088a.dtsi
@@ -284,46 +284,46 @@
fsl,tmu-range = <0xb0000 0x9002a 0x6004c 0x70062>;
fsl,tmu-calibration =
/* Calibration data group 1 */
- <0x00000000 0x00000023
- 0x00000001 0x0000002a
- 0x00000002 0x00000030
- 0x00000003 0x00000037
- 0x00000004 0x0000003d
- 0x00000005 0x00000044
- 0x00000006 0x0000004a
- 0x00000007 0x00000051
- 0x00000008 0x00000057
- 0x00000009 0x0000005e
- 0x0000000a 0x00000064
- 0x0000000b 0x0000006b
+ <0x00000000 0x00000023>,
+ <0x00000001 0x0000002a>,
+ <0x00000002 0x00000030>,
+ <0x00000003 0x00000037>,
+ <0x00000004 0x0000003d>,
+ <0x00000005 0x00000044>,
+ <0x00000006 0x0000004a>,
+ <0x00000007 0x00000051>,
+ <0x00000008 0x00000057>,
+ <0x00000009 0x0000005e>,
+ <0x0000000a 0x00000064>,
+ <0x0000000b 0x0000006b>,
/* Calibration data group 2 */
- 0x00010000 0x00000022
- 0x00010001 0x0000002a
- 0x00010002 0x00000032
- 0x00010003 0x0000003a
- 0x00010004 0x00000042
- 0x00010005 0x0000004a
- 0x00010006 0x00000052
- 0x00010007 0x0000005a
- 0x00010008 0x00000062
- 0x00010009 0x0000006a
+ <0x00010000 0x00000022>,
+ <0x00010001 0x0000002a>,
+ <0x00010002 0x00000032>,
+ <0x00010003 0x0000003a>,
+ <0x00010004 0x00000042>,
+ <0x00010005 0x0000004a>,
+ <0x00010006 0x00000052>,
+ <0x00010007 0x0000005a>,
+ <0x00010008 0x00000062>,
+ <0x00010009 0x0000006a>,
/* Calibration data group 3 */
- 0x00020000 0x00000021
- 0x00020001 0x0000002b
- 0x00020002 0x00000035
- 0x00020003 0x00000040
- 0x00020004 0x0000004a
- 0x00020005 0x00000054
- 0x00020006 0x0000005e
+ <0x00020000 0x00000021>,
+ <0x00020001 0x0000002b>,
+ <0x00020002 0x00000035>,
+ <0x00020003 0x00000040>,
+ <0x00020004 0x0000004a>,
+ <0x00020005 0x00000054>,
+ <0x00020006 0x0000005e>,
/* Calibration data group 4 */
- 0x00030000 0x00000010
- 0x00030001 0x0000001c
- 0x00030002 0x00000027
- 0x00030003 0x00000032
- 0x00030004 0x0000003e
- 0x00030005 0x00000049
- 0x00030006 0x00000054
- 0x00030007 0x00000060>;
+ <0x00030000 0x00000010>,
+ <0x00030001 0x0000001c>,
+ <0x00030002 0x00000027>,
+ <0x00030003 0x00000032>,
+ <0x00030004 0x0000003e>,
+ <0x00030005 0x00000049>,
+ <0x00030006 0x00000054>,
+ <0x00030007 0x00000060>;
little-endian;
#thermal-sensor-cells = <1>;
};
diff --git a/dts/upstream/src/arm64/freescale/fsl-ls208xa.dtsi b/dts/upstream/src/arm64/freescale/fsl-ls208xa.dtsi
index 717288b..0b72928 100644
--- a/dts/upstream/src/arm64/freescale/fsl-ls208xa.dtsi
+++ b/dts/upstream/src/arm64/freescale/fsl-ls208xa.dtsi
@@ -321,42 +321,43 @@
reg = <0x0 0x1f80000 0x0 0x10000>;
interrupts = <0 23 0x4>;
fsl,tmu-range = <0xb0000 0x9002a 0x6004c 0x30062>;
- fsl,tmu-calibration = <0x00000000 0x00000026
- 0x00000001 0x0000002d
- 0x00000002 0x00000032
- 0x00000003 0x00000039
- 0x00000004 0x0000003f
- 0x00000005 0x00000046
- 0x00000006 0x0000004d
- 0x00000007 0x00000054
- 0x00000008 0x0000005a
- 0x00000009 0x00000061
- 0x0000000a 0x0000006a
- 0x0000000b 0x00000071
+ fsl,tmu-calibration =
+ <0x00000000 0x00000026>,
+ <0x00000001 0x0000002d>,
+ <0x00000002 0x00000032>,
+ <0x00000003 0x00000039>,
+ <0x00000004 0x0000003f>,
+ <0x00000005 0x00000046>,
+ <0x00000006 0x0000004d>,
+ <0x00000007 0x00000054>,
+ <0x00000008 0x0000005a>,
+ <0x00000009 0x00000061>,
+ <0x0000000a 0x0000006a>,
+ <0x0000000b 0x00000071>,
- 0x00010000 0x00000025
- 0x00010001 0x0000002c
- 0x00010002 0x00000035
- 0x00010003 0x0000003d
- 0x00010004 0x00000045
- 0x00010005 0x0000004e
- 0x00010006 0x00000057
- 0x00010007 0x00000061
- 0x00010008 0x0000006b
- 0x00010009 0x00000076
+ <0x00010000 0x00000025>,
+ <0x00010001 0x0000002c>,
+ <0x00010002 0x00000035>,
+ <0x00010003 0x0000003d>,
+ <0x00010004 0x00000045>,
+ <0x00010005 0x0000004e>,
+ <0x00010006 0x00000057>,
+ <0x00010007 0x00000061>,
+ <0x00010008 0x0000006b>,
+ <0x00010009 0x00000076>,
- 0x00020000 0x00000029
- 0x00020001 0x00000033
- 0x00020002 0x0000003d
- 0x00020003 0x00000049
- 0x00020004 0x00000056
- 0x00020005 0x00000061
- 0x00020006 0x0000006d
+ <0x00020000 0x00000029>,
+ <0x00020001 0x00000033>,
+ <0x00020002 0x0000003d>,
+ <0x00020003 0x00000049>,
+ <0x00020004 0x00000056>,
+ <0x00020005 0x00000061>,
+ <0x00020006 0x0000006d>,
- 0x00030000 0x00000021
- 0x00030001 0x0000002a
- 0x00030002 0x0000003c
- 0x00030003 0x0000004e>;
+ <0x00030000 0x00000021>,
+ <0x00030001 0x0000002a>,
+ <0x00030002 0x0000003c>,
+ <0x00030003 0x0000004e>;
little-endian;
#thermal-sensor-cells = <1>;
};
diff --git a/dts/upstream/src/arm64/freescale/fsl-lx2160a-tqmlx2160a-mblx2160a.dts b/dts/upstream/src/arm64/freescale/fsl-lx2160a-tqmlx2160a-mblx2160a.dts
new file mode 100644
index 0000000..da0f58e
--- /dev/null
+++ b/dts/upstream/src/arm64/freescale/fsl-lx2160a-tqmlx2160a-mblx2160a.dts
@@ -0,0 +1,338 @@
+// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
+/*
+ * Copyright (c) 2020-2023 TQ-Systems GmbH <linux@ew.tq-group.com>,
+ * D-82229 Seefeld, Germany.
+ * Author: Gregor Herburger
+ */
+
+/dts-v1/;
+
+#include <dt-bindings/input/input.h>
+#include <dt-bindings/leds/common.h>
+#include <dt-bindings/net/ti-dp83867.h>
+
+#include "fsl-lx2160a-tqmlx2160a.dtsi"
+
+/ {
+ model = "TQ Systems GmbH MBLX2160A Starterkit";
+ compatible = "tq,lx2160a-tqmlx2160a-mblx2160a", "tq,lx2160a-tqmlx2160a",
+ "fsl,lx2160a";
+
+ aliases {
+ mmc0 = &esdhc0;
+ mmc1 = &esdhc1;
+ serial0 = &uart0;
+ serial1 = &uart1;
+ serial2 = &uart2;
+ serial3 = &uart3;
+ };
+
+ chosen {
+ stdout-path = &uart0;
+ };
+
+ gpio-keys {
+ compatible = "gpio-keys";
+
+ button-user1 {
+ label = "button:user1";
+ gpios = <&gpio2 9 GPIO_ACTIVE_LOW>;
+ linux,code = <KEY_F1>;
+ };
+
+ button-user2 {
+ label = "button:user2";
+ gpios = <&gpio2 10 GPIO_ACTIVE_LOW>;
+ linux,code = <KEY_F2>;
+ };
+ };
+
+ leds {
+ compatible = "gpio-leds";
+
+ led-user1 {
+ gpios = <&gpioex1 15 GPIO_ACTIVE_LOW>;
+ color = <LED_COLOR_ID_BLUE>;
+ function = LED_FUNCTION_HEARTBEAT;
+ function-enumerator = <0>;
+ linux,default-trigger = "heartbeat";
+ };
+
+ led-user2 {
+ gpios = <&gpio2 8 GPIO_ACTIVE_LOW>;
+ color = <LED_COLOR_ID_BLUE>;
+ function = LED_FUNCTION_HEARTBEAT;
+ function-enumerator = <1>;
+ linux,default-trigger = "heartbeat";
+ };
+ };
+
+ sfp_xfi1: sfp-xfi1 {
+ compatible = "sff,sfp";
+ i2c-bus = <&xfi1_i2c>;
+ mod-def0-gpios = <&gpioex2 2 GPIO_ACTIVE_LOW>;
+ los-gpios = <&gpioex2 3 GPIO_ACTIVE_HIGH>;
+ tx-fault-gpios = <&gpioex2 0 GPIO_ACTIVE_HIGH>;
+ tx-disable-gpios = <&gpioex2 1 GPIO_ACTIVE_HIGH>;
+ status = "disabled";
+ };
+
+ sfp_xfi2: sfp-xfi2 {
+ compatible = "sff,sfp";
+ i2c-bus = <&xfi2_i2c>;
+ mod-def0-gpios = <&gpioex2 6 GPIO_ACTIVE_LOW>;
+ los-gpios = <&gpioex2 7 GPIO_ACTIVE_HIGH>;
+ tx-fault-gpios = <&gpioex2 4 GPIO_ACTIVE_HIGH>;
+ tx-disable-gpios = <&gpioex2 5 GPIO_ACTIVE_HIGH>;
+ status = "disabled";
+ };
+};
+
+&can0 {
+ status = "okay";
+};
+
+&can1 {
+ status = "okay";
+};
+
+&dpmac17 {
+ phy-handle = <&dp83867_2_3>;
+ phy-connection-type = "rgmii-id";
+};
+
+&dpmac18 {
+ phy-handle = <&dp83867_2_4>;
+ phy-connection-type = "rgmii-id";
+};
+
+&emdio1 {
+ status = "okay";
+
+ dp83867_1_1: ethernet-phy@1 {
+ reg = <1>;
+ ti,clk-output-sel = <DP83867_CLK_O_SEL_OFF>;
+ };
+
+ dp83867_1_2: ethernet-phy@2 {
+ reg = <2>;
+ ti,clk-output-sel = <DP83867_CLK_O_SEL_OFF>;
+ };
+
+ dp83867_1_3: ethernet-phy@3 {
+ reg = <3>;
+ ti,clk-output-sel = <DP83867_CLK_O_SEL_OFF>;
+ };
+
+ dp83867_1_4: ethernet-phy@4 {
+ reg = <4>;
+ ti,clk-output-sel = <DP83867_CLK_O_SEL_OFF>;
+ };
+
+ dp83867_1_5: ethernet-phy@5 {
+ reg = <5>;
+ ti,clk-output-sel = <DP83867_CLK_O_SEL_OFF>;
+ };
+
+ dp83867_1_6: ethernet-phy@6 {
+ reg = <6>;
+ ti,clk-output-sel = <DP83867_CLK_O_SEL_OFF>;
+ };
+};
+
+&emdio2 {
+ status = "okay";
+
+ dp83867_2_1: ethernet-phy@1 {
+ reg = <1>;
+ ti,clk-output-sel = <DP83867_CLK_O_SEL_OFF>;
+ };
+
+ dp83867_2_2: ethernet-phy@2 {
+ reg = <2>;
+ ti,clk-output-sel = <DP83867_CLK_O_SEL_OFF>;
+ };
+
+ dp83867_2_3: ethernet-phy@3 {
+ reg = <3>;
+ ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_25_NS>;
+ ti,tx-internal-delay = <DP83867_RGMIIDCTL_2_25_NS>;
+ ti,clk-output-sel = <DP83867_CLK_O_SEL_OFF>;
+ };
+
+ dp83867_2_4: ethernet-phy@4 {
+ reg = <4>;
+ ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_25_NS>;
+ ti,tx-internal-delay = <DP83867_RGMIIDCTL_2_25_NS>;
+ ti,clk-output-sel = <DP83867_CLK_O_SEL_OFF>;
+ };
+};
+
+&esdhc0 {
+ sd-uhs-sdr104;
+ sd-uhs-sdr50;
+ sd-uhs-sdr25;
+ sd-uhs-sdr12;
+ no-mmc;
+ no-sdio;
+ wp-gpios = <&gpio0 30 GPIO_ACTIVE_LOW>;
+ cd-gpios = <&gpio0 31 GPIO_ACTIVE_LOW>;
+ status = "okay";
+};
+
+&i2c0 {
+ gpioex3: gpio@20 {
+ compatible = "nxp,pca9555";
+ reg = <0x20>;
+ #gpio-cells = <2>;
+ gpio-controller;
+ vcc-supply = <®_vcc3v3>;
+ };
+};
+
+&i2c4 {
+ status = "okay";
+
+ mux@70 {
+ compatible = "nxp,pca9544";
+ reg = <0x70>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ vdd-supply = <®_vcc3v3>;
+
+ i2c@0 {
+ reg = <0>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+
+ i2c@1 {
+ reg = <1>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+
+ i2c@2 {
+ reg = <2>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ gpioex0: gpio@20 {
+ compatible = "nxp,pca9555";
+ reg = <0x20>;
+ #gpio-cells = <2>;
+ gpio-controller;
+ vcc-supply = <®_vcc3v3>;
+ };
+
+ gpioex1: gpio@21 {
+ compatible = "nxp,pca9555";
+ reg = <0x21>;
+ #gpio-cells = <2>;
+ gpio-controller;
+ vcc-supply = <®_vcc3v3>;
+ };
+
+ gpioex2: gpio@22 {
+ compatible = "nxp,pca9555";
+ reg = <0x22>;
+ #gpio-cells = <2>;
+ gpio-controller;
+ vcc-supply = <®_vcc3v3>;
+ };
+ };
+
+ i2c@3 {
+ reg = <3>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+ };
+};
+
+&i2c5 {
+ status = "okay";
+
+ mux@70 {
+ compatible = "nxp,pca9544";
+ reg = <0x70>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ vdd-supply = <®_vcc3v3>;
+
+ i2c@0 {
+ reg = <0>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+
+ xfi1_i2c: i2c@1 {
+ reg = <1>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+
+ xfi2_i2c: i2c@2 {
+ reg = <2>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+
+ i2c@3 {
+ reg = <3>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+ };
+};
+
+&pcs_mdio17 {
+ status = "okay";
+};
+
+&pcs_mdio18 {
+ status = "okay";
+};
+
+&uart0 {
+ status = "okay";
+};
+
+&uart1 {
+ status = "okay";
+};
+
+&uart2 {
+ status = "okay";
+};
+
+&uart3 {
+ status = "okay";
+};
+
+&usb0 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "okay";
+
+ hub_2_0: hub@1 {
+ compatible = "usb451,8142";
+ reg = <1>;
+ peer-hub = <&hub_3_0>;
+ reset-gpios = <&gpioex1 0 GPIO_ACTIVE_LOW>;
+ vcc-supply = <®_vcc3v3>;
+ };
+
+ hub_3_0: hub@2 {
+ compatible = "usb451,8140";
+ reg = <2>;
+ peer-hub = <&hub_2_0>;
+ reset-gpios = <&gpioex1 0 GPIO_ACTIVE_LOW>;
+ vcc-supply = <®_vcc3v3>;
+ };
+};
+
+&usb1 {
+ dr_mode = "otg";
+ status = "okay";
+};
diff --git a/dts/upstream/src/arm64/freescale/fsl-lx2160a-tqmlx2160a-mblx2160a_12_x_x.dtso b/dts/upstream/src/arm64/freescale/fsl-lx2160a-tqmlx2160a-mblx2160a_12_x_x.dtso
new file mode 100644
index 0000000..8284a56
--- /dev/null
+++ b/dts/upstream/src/arm64/freescale/fsl-lx2160a-tqmlx2160a-mblx2160a_12_x_x.dtso
@@ -0,0 +1,29 @@
+// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
+/*
+ * Copyright (c) 2020-2023 TQ-Systems GmbH <linux@ew.tq-group.com>,
+ * D-82229 Seefeld, Germany.
+ * Author: Gregor Herburger
+ */
+
+/dts-v1/;
+/plugin/;
+
+&dpmac9 {
+ phy-handle = <&dp83867_2_1>;
+ phy-connection-type = "sgmii";
+ managed = "in-band-status";
+};
+
+&dpmac10 {
+ phy-handle = <&dp83867_2_2>;
+ phy-connection-type = "sgmii";
+ managed = "in-band-status";
+};
+
+&pcs_mdio9 {
+ status = "okay";
+};
+
+&pcs_mdio10 {
+ status = "okay";
+};
diff --git a/dts/upstream/src/arm64/freescale/fsl-lx2160a-tqmlx2160a-mblx2160a_14_x_x.dtso b/dts/upstream/src/arm64/freescale/fsl-lx2160a-tqmlx2160a-mblx2160a_14_x_x.dtso
new file mode 100644
index 0000000..636b17a
--- /dev/null
+++ b/dts/upstream/src/arm64/freescale/fsl-lx2160a-tqmlx2160a-mblx2160a_14_x_x.dtso
@@ -0,0 +1,17 @@
+// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
+/*
+ * Copyright (c) 2020-2023 TQ-Systems GmbH <linux@ew.tq-group.com>,
+ * D-82229 Seefeld, Germany.
+ * Author: Gregor Herburger
+ */
+
+/dts-v1/;
+/plugin/;
+
+&dpmac1 {
+ managed = "in-band-status";
+};
+
+&pcs_mdio1 {
+ status = "okay";
+};
diff --git a/dts/upstream/src/arm64/freescale/fsl-lx2160a-tqmlx2160a-mblx2160a_x_11_x.dtso b/dts/upstream/src/arm64/freescale/fsl-lx2160a-tqmlx2160a-mblx2160a_x_11_x.dtso
new file mode 100644
index 0000000..6d0c808
--- /dev/null
+++ b/dts/upstream/src/arm64/freescale/fsl-lx2160a-tqmlx2160a-mblx2160a_x_11_x.dtso
@@ -0,0 +1,49 @@
+// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
+/*
+ * Copyright (c) 2020-2023 TQ-Systems GmbH <linux@ew.tq-group.com>,
+ * D-82229 Seefeld, Germany.
+ * Author: Gregor Herburger
+ */
+
+/dts-v1/;
+/plugin/;
+
+&dpmac12 {
+ phy-handle = <&dp83867_1_1>;
+ phy-connection-type = "sgmii";
+ managed = "in-band-status";
+};
+
+&dpmac13 {
+ phy-handle = <&dp83867_1_5>;
+ phy-connection-type = "sgmii";
+ managed = "in-band-status";
+};
+
+&dpmac14 {
+ phy-handle = <&dp83867_1_6>;
+ phy-connection-type = "sgmii";
+ managed = "in-band-status";
+};
+
+&dpmac16 {
+ phy-handle = <&dp83867_1_4>;
+ phy-connection-type = "sgmii";
+ managed = "in-band-status";
+};
+
+&pcs_mdio12 {
+ status = "okay";
+};
+
+&pcs_mdio13 {
+ status = "okay";
+};
+
+&pcs_mdio14 {
+ status = "okay";
+};
+
+&pcs_mdio16 {
+ status = "okay";
+};
diff --git a/dts/upstream/src/arm64/freescale/fsl-lx2160a-tqmlx2160a-mblx2160a_x_7_x.dtso b/dts/upstream/src/arm64/freescale/fsl-lx2160a-tqmlx2160a-mblx2160a_x_7_x.dtso
new file mode 100644
index 0000000..db88a86
--- /dev/null
+++ b/dts/upstream/src/arm64/freescale/fsl-lx2160a-tqmlx2160a-mblx2160a_x_7_x.dtso
@@ -0,0 +1,55 @@
+// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
+/*
+ * Copyright (c) 2020-2023 TQ-Systems GmbH <linux@ew.tq-group.com>,
+ * D-82229 Seefeld, Germany.
+ * Author: Gregor Herburger
+ */
+
+/dts-v1/;
+/plugin/;
+
+&dpmac12 {
+ phy-handle = <&dp83867_1_1>;
+ phy-connection-type = "sgmii";
+ managed = "in-band-status";
+};
+
+&dpmac13 {
+ sfp = <&sfp_xfi1>;
+ managed = "in-band-status";
+};
+
+&dpmac14 {
+ sfp = <&sfp_xfi2>;
+ managed = "in-band-status";
+};
+
+&dpmac16 {
+ phy-handle = <&dp83867_1_4>;
+ phy-connection-type = "sgmii";
+ managed = "in-band-status";
+};
+
+&pcs_mdio12 {
+ status = "okay";
+};
+
+&pcs_mdio13 {
+ status = "okay";
+};
+
+&pcs_mdio14 {
+ status = "okay";
+};
+
+&pcs_mdio16 {
+ status = "okay";
+};
+
+&sfp_xfi1 {
+ status = "okay";
+};
+
+&sfp_xfi2 {
+ status = "okay";
+};
diff --git a/dts/upstream/src/arm64/freescale/fsl-lx2160a-tqmlx2160a-mblx2160a_x_8_x.dtso b/dts/upstream/src/arm64/freescale/fsl-lx2160a-tqmlx2160a-mblx2160a_x_8_x.dtso
new file mode 100644
index 0000000..f6dfa76
--- /dev/null
+++ b/dts/upstream/src/arm64/freescale/fsl-lx2160a-tqmlx2160a-mblx2160a_x_8_x.dtso
@@ -0,0 +1,47 @@
+// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
+/*
+ * Copyright (c) 2020-2023 TQ-Systems GmbH <linux@ew.tq-group.com>,
+ * D-82229 Seefeld, Germany.
+ * Author: Gregor Herburger
+ */
+
+/dts-v1/;
+/plugin/;
+
+&dpmac13 {
+ sfp = <&sfp_xfi1>;
+ managed = "in-band-status";
+};
+
+&dpmac14 {
+ sfp = <&sfp_xfi2>;
+ managed = "in-band-status";
+};
+
+&pcs_mdio13 {
+ status = "okay";
+};
+
+&pcs_mdio14 {
+ status = "okay";
+};
+
+&sata0 {
+ status = "okay";
+};
+
+&sata1 {
+ status = "okay";
+};
+
+&sata2 {
+ status = "okay";
+};
+
+&sfp_xfi1 {
+ status = "okay";
+};
+
+&sfp_xfi2 {
+ status = "okay";
+};
diff --git a/dts/upstream/src/arm64/freescale/fsl-lx2160a-tqmlx2160a.dtsi b/dts/upstream/src/arm64/freescale/fsl-lx2160a-tqmlx2160a.dtsi
new file mode 100644
index 0000000..89a4765
--- /dev/null
+++ b/dts/upstream/src/arm64/freescale/fsl-lx2160a-tqmlx2160a.dtsi
@@ -0,0 +1,97 @@
+// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
+/*
+ * Copyright (c) 2020-2023 TQ-Systems GmbH <linux@ew.tq-group.com>,
+ * D-82229 Seefeld, Germany.
+ * Author: Gregor Herburger
+ */
+
+#include "fsl-lx2160a.dtsi"
+
+/ {
+ reg_vcc3v3: regulator-vcc3v3 {
+ compatible = "regulator-fixed";
+ regulator-name = "VCC3V3";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-always-on;
+ };
+};
+
+
+&emdio1 {
+ status = "okay";
+};
+
+&emdio2 {
+ status = "okay";
+};
+
+&esdhc1 {
+ bus-width = <8>;
+ no-sd;
+ no-sdio;
+ non-removable;
+ mmc-hs200-1_8v;
+ status = "okay";
+};
+
+&fspi {
+ status = "okay";
+
+ flash0: flash@0 {
+ compatible = "jedec,spi-nor";
+ reg = <0>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ spi-max-frequency = <10000000>;
+ spi-rx-bus-width = <1>;
+ spi-tx-bus-width = <1>;
+
+ partitions {
+ compatible = "fixed-partitions";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ };
+ };
+
+ flash1: flash@1 {
+ compatible = "jedec,spi-nor";
+ reg = <1>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ spi-max-frequency = <10000000>;
+ spi-rx-bus-width = <1>;
+ spi-tx-bus-width = <1>;
+ };
+};
+
+&i2c0 {
+ scl-gpios = <&gpio2 11 GPIO_ACTIVE_HIGH>;
+ status = "okay";
+
+ sensor0: temperature-sensor@1f {
+ compatible = "nxp,se97", "jedec,jc-42.4-temp";
+ reg = <0x1f>;
+ };
+
+ eeprom1: eeprom@57 {
+ compatible = "atmel,24c02";
+ reg = <0x57>;
+ pagesize = <16>;
+ read-only;
+ vcc-supply = <®_vcc3v3>;
+ };
+
+ rtc: rtc@51 {
+ compatible = "nxp,pcf85063a";
+ reg = <0x51>;
+ quartz-load-femtofarads = <12500>;
+ };
+
+ eeprom2: eeprom@50 {
+ compatible = "atmel,24c64";
+ reg = <0x50>;
+ pagesize = <32>;
+ vcc-supply = <®_vcc3v3>;
+ };
+};
diff --git a/dts/upstream/src/arm64/freescale/fsl-lx2160a.dtsi b/dts/upstream/src/arm64/freescale/fsl-lx2160a.dtsi
index f176ca2..6640b49 100644
--- a/dts/upstream/src/arm64/freescale/fsl-lx2160a.dtsi
+++ b/dts/upstream/src/arm64/freescale/fsl-lx2160a.dtsi
@@ -732,9 +732,9 @@
fsl,tmu-range = <0x800000e6 0x8001017d>;
fsl,tmu-calibration =
/* Calibration data group 1 */
- <0x00000000 0x00000035
+ <0x00000000 0x00000035>,
/* Calibration data group 2 */
- 0x00000001 0x00000154>;
+ <0x00000001 0x00000154>;
little-endian;
#thermal-sensor-cells = <1>;
};
diff --git a/dts/upstream/src/arm64/freescale/imx8-apalis-ixora-v1.2.dtsi b/dts/upstream/src/arm64/freescale/imx8-apalis-ixora-v1.2.dtsi
index 72136c4..f6654fd 100644
--- a/dts/upstream/src/arm64/freescale/imx8-apalis-ixora-v1.2.dtsi
+++ b/dts/upstream/src/arm64/freescale/imx8-apalis-ixora-v1.2.dtsi
@@ -68,6 +68,7 @@
gpio = <&lsio_gpio5 22 GPIO_ACTIVE_HIGH>;
enable-active-high;
regulator-name = "can1_supply";
+ startup-delay-us = <1000>;
};
reg_can2_supply: regulator-can2-supply {
@@ -77,6 +78,7 @@
gpio = <&lsio_gpio2 8 GPIO_ACTIVE_HIGH>;
enable-active-high;
regulator-name = "can2_supply";
+ startup-delay-us = <1000>;
};
reg_usb_host_vbus: regulator-usb-host-vbus {
diff --git a/dts/upstream/src/arm64/freescale/imx8-ss-audio.dtsi b/dts/upstream/src/arm64/freescale/imx8-ss-audio.dtsi
index 9d75ce4..f057c6b 100644
--- a/dts/upstream/src/arm64/freescale/imx8-ss-audio.dtsi
+++ b/dts/upstream/src/arm64/freescale/imx8-ss-audio.dtsi
@@ -24,7 +24,6 @@
compatible = "fsl,imx8qm-edma";
reg = <0x591f0000 0x190000>;
#dma-cells = <3>;
- shared-interrupt;
dma-channels = <24>;
dma-channel-mask = <0x5c0c00>;
interrupts = <GIC_SPI 374 IRQ_TYPE_LEVEL_HIGH>, /* 0 asrc 0 */
@@ -127,7 +126,6 @@
compatible = "fsl,imx8qm-edma";
reg = <0x599f0000 0xc0000>;
#dma-cells = <3>;
- shared-interrupt;
dma-channels = <11>;
dma-channel-mask = <0xc0>;
interrupts = <GIC_SPI 382 IRQ_TYPE_LEVEL_HIGH>, /* 0 asrc 1 */
diff --git a/dts/upstream/src/arm64/freescale/imx8dxl-ss-conn.dtsi b/dts/upstream/src/arm64/freescale/imx8dxl-ss-conn.dtsi
index a414df6..6d13e4f 100644
--- a/dts/upstream/src/arm64/freescale/imx8dxl-ss-conn.dtsi
+++ b/dts/upstream/src/arm64/freescale/imx8dxl-ss-conn.dtsi
@@ -13,6 +13,13 @@
clock-frequency = <250000000>;
clock-output-names = "conn_enet0_root_clk";
};
+
+ clk_dummy: clock-dummy {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <0>;
+ clock-output-names = "clk_dummy";
+ };
};
&conn_subsys {
@@ -22,7 +29,7 @@
interrupt-parent = <&gic>;
interrupts = <GIC_SPI 163 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 162 IRQ_TYPE_LEVEL_HIGH>;
- interrupt-names = "eth_wake_irq", "macirq";
+ interrupt-names = "macirq", "eth_wake_irq";
clocks = <&eqos_lpcg IMX_LPCG_CLK_4>,
<&eqos_lpcg IMX_LPCG_CLK_6>,
<&eqos_lpcg IMX_LPCG_CLK_0>,
@@ -53,13 +60,6 @@
rx-burst-size-dword = <0x10>;
power-domains = <&pd IMX_SC_R_USB_1>;
status = "disabled";
-
- clk_dummy: clock-dummy {
- compatible = "fixed-clock";
- #clock-cells = <0>;
- clock-frequency = <0>;
- clock-output-names = "clk_dummy";
- };
};
usbmisc2: usbmisc@5b0e0200 {
diff --git a/dts/upstream/src/arm64/freescale/imx8dxl-ss-ddr.dtsi b/dts/upstream/src/arm64/freescale/imx8dxl-ss-ddr.dtsi
index 550f513..3569abb 100644
--- a/dts/upstream/src/arm64/freescale/imx8dxl-ss-ddr.dtsi
+++ b/dts/upstream/src/arm64/freescale/imx8dxl-ss-ddr.dtsi
@@ -4,6 +4,6 @@
*/
&ddr_pmu0 {
- compatible = "fsl,imx8-ddr-pmu";
+ compatible = "fsl,imx8dxl-ddr-pmu", "fsl,imx8-ddr-pmu";
interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
};
diff --git a/dts/upstream/src/arm64/freescale/imx8mm-beacon-som.dtsi b/dts/upstream/src/arm64/freescale/imx8mm-beacon-som.dtsi
index f264102..62ed646 100644
--- a/dts/upstream/src/arm64/freescale/imx8mm-beacon-som.dtsi
+++ b/dts/upstream/src/arm64/freescale/imx8mm-beacon-som.dtsi
@@ -3,6 +3,8 @@
* Copyright 2020 Compass Electronics Group, LLC
*/
+#include "imx8mm-overdrive.dtsi"
+
/ {
aliases {
rtc0 = &rtc;
diff --git a/dts/upstream/src/arm64/freescale/imx8mm-emcon-avari.dtsi b/dts/upstream/src/arm64/freescale/imx8mm-emcon-avari.dtsi
index d897a85..44c2cba 100644
--- a/dts/upstream/src/arm64/freescale/imx8mm-emcon-avari.dtsi
+++ b/dts/upstream/src/arm64/freescale/imx8mm-emcon-avari.dtsi
@@ -104,7 +104,7 @@
compatible = "nxp,pca8574";
reg = <0x3a>;
gpio-controller;
- #gpio-cells = <1>;
+ #gpio-cells = <2>;
};
};
diff --git a/dts/upstream/src/arm64/freescale/imx8mm-evk.dtsi b/dts/upstream/src/arm64/freescale/imx8mm-evk.dtsi
index a882c86..b53104e 100644
--- a/dts/upstream/src/arm64/freescale/imx8mm-evk.dtsi
+++ b/dts/upstream/src/arm64/freescale/imx8mm-evk.dtsi
@@ -367,12 +367,6 @@
interrupts = <11 8>;
status = "okay";
- port {
- typec1_dr_sw: endpoint {
- remote-endpoint = <&usb1_drd_sw>;
- };
- };
-
typec1_con: connector {
compatible = "usb-c-connector";
label = "USB-C";
@@ -384,6 +378,12 @@
PDO_VAR(5000, 20000, 3000)>;
op-sink-microwatt = <15000000>;
self-powered;
+
+ port {
+ typec1_dr_sw: endpoint {
+ remote-endpoint = <&usb1_drd_sw>;
+ };
+ };
};
};
};
diff --git a/dts/upstream/src/arm64/freescale/imx8mm-nitrogen-r2.dts b/dts/upstream/src/arm64/freescale/imx8mm-nitrogen-r2.dts
index 0e8f0d7..12fb79d 100644
--- a/dts/upstream/src/arm64/freescale/imx8mm-nitrogen-r2.dts
+++ b/dts/upstream/src/arm64/freescale/imx8mm-nitrogen-r2.dts
@@ -220,7 +220,7 @@
#address-cells = <1>;
#size-cells = <0>;
- i2c3@0 {
+ i2c@0 {
reg = <0>;
#address-cells = <1>;
#size-cells = <0>;
diff --git a/dts/upstream/src/arm64/freescale/imx8mm-overdrive.dtsi b/dts/upstream/src/arm64/freescale/imx8mm-overdrive.dtsi
new file mode 100644
index 0000000..b31436b
--- /dev/null
+++ b/dts/upstream/src/arm64/freescale/imx8mm-overdrive.dtsi
@@ -0,0 +1,29 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+
+&gpu_2d {
+ assigned-clocks = <&clk IMX8MM_CLK_GPU2D_CORE>,
+ <&clk IMX8MM_GPU_PLL_OUT>;
+ assigned-clock-parents = <&clk IMX8MM_GPU_PLL_OUT>;
+ assigned-clock-rates = <0>, <1000000000>;
+};
+
+&gpu_3d {
+ assigned-clocks = <&clk IMX8MM_CLK_GPU3D_CORE>,
+ <&clk IMX8MM_GPU_PLL_OUT>;
+ assigned-clock-parents = <&clk IMX8MM_GPU_PLL_OUT>;
+ assigned-clock-rates = <0>, <1000000000>;
+};
+
+&vpu_blk_ctrl {
+ assigned-clocks = <&clk IMX8MM_CLK_VPU_G1>,
+ <&clk IMX8MM_CLK_VPU_G2>,
+ <&clk IMX8MM_CLK_VPU_H1>,
+ <&clk IMX8MM_VPU_PLL_OUT>;
+ assigned-clock-parents = <&clk IMX8MM_SYS_PLL3_OUT>,
+ <&clk IMX8MM_VPU_PLL_OUT>,
+ <&clk IMX8MM_SYS_PLL3_OUT>;
+ assigned-clock-rates = <750000000>,
+ <700000000>,
+ <750000000>,
+ <700000000>;
+};
diff --git a/dts/upstream/src/arm64/freescale/imx8mm-phygate-tauri-l.dts b/dts/upstream/src/arm64/freescale/imx8mm-phygate-tauri-l.dts
index 968f475..27a9025 100644
--- a/dts/upstream/src/arm64/freescale/imx8mm-phygate-tauri-l.dts
+++ b/dts/upstream/src/arm64/freescale/imx8mm-phygate-tauri-l.dts
@@ -120,7 +120,7 @@
};
tpm: tpm@1 {
- compatible = "tcg,tpm_tis-spi";
+ compatible = "infineon,slb9670", "tcg,tpm_tis-spi";
interrupts = <11 IRQ_TYPE_LEVEL_LOW>;
interrupt-parent = <&gpio2>;
pinctrl-names = "default";
diff --git a/dts/upstream/src/arm64/freescale/imx8mm-tqma8mqml-mba8mx.dts b/dts/upstream/src/arm64/freescale/imx8mm-tqma8mqml-mba8mx.dts
index 156d793..ea6e8b8 100644
--- a/dts/upstream/src/arm64/freescale/imx8mm-tqma8mqml-mba8mx.dts
+++ b/dts/upstream/src/arm64/freescale/imx8mm-tqma8mqml-mba8mx.dts
@@ -11,6 +11,7 @@
/ {
model = "TQ-Systems GmbH i.MX8MM TQMa8MxML on MBa8Mx";
compatible = "tq,imx8mm-tqma8mqml-mba8mx", "tq,imx8mm-tqma8mqml", "fsl,imx8mm";
+ chassis-type = "embedded";
aliases {
eeprom0 = &eeprom3;
diff --git a/dts/upstream/src/arm64/freescale/imx8mm-venice-gw72xx.dtsi b/dts/upstream/src/arm64/freescale/imx8mm-venice-gw72xx.dtsi
index 3a0a10e..752caa3 100644
--- a/dts/upstream/src/arm64/freescale/imx8mm-venice-gw72xx.dtsi
+++ b/dts/upstream/src/arm64/freescale/imx8mm-venice-gw72xx.dtsi
@@ -84,8 +84,15 @@
&ecspi2 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_spi2>;
- cs-gpios = <&gpio5 13 GPIO_ACTIVE_LOW>;
+ cs-gpios = <&gpio5 13 GPIO_ACTIVE_LOW>,
+ <&gpio1 10 GPIO_ACTIVE_LOW>;
status = "okay";
+
+ tpm@1 {
+ compatible = "atmel,attpm20p", "tcg,tpm_tis-spi";
+ reg = <0x1>;
+ spi-max-frequency = <36000000>;
+ };
};
&gpio1 {
@@ -152,23 +159,30 @@
pcie@0,0 {
reg = <0x0000 0 0 0 0>;
- #address-cells = <1>;
- #size-cells = <0>;
+ device_type = "pci";
+ #address-cells = <3>;
+ #size-cells = <2>;
+ ranges;
- pcie@1,0 {
+ pcie@0,0 {
reg = <0x0000 0 0 0 0>;
- #address-cells = <1>;
- #size-cells = <0>;
+ device_type = "pci";
+ #address-cells = <3>;
+ #size-cells = <2>;
+ ranges;
- pcie@2,3 {
+ pcie@3,0 {
reg = <0x1800 0 0 0 0>;
- #address-cells = <1>;
- #size-cells = <0>;
+ device_type = "pci";
+ #address-cells = <3>;
+ #size-cells = <2>;
+ ranges;
- eth1: pcie@5,0 {
+ eth1: ethernet@0,0 {
reg = <0x0000 0 0 0 0>;
- #address-cells = <1>;
- #size-cells = <0>;
+ #address-cells = <3>;
+ #size-cells = <2>;
+ ranges;
local-mac-address = [00 00 00 00 00 00];
};
@@ -312,6 +326,7 @@
MX8MM_IOMUXC_ECSPI2_MOSI_ECSPI2_MOSI 0xd6
MX8MM_IOMUXC_ECSPI2_MISO_ECSPI2_MISO 0xd6
MX8MM_IOMUXC_ECSPI2_SS0_GPIO5_IO13 0xd6
+ MX8MM_IOMUXC_GPIO1_IO10_GPIO1_IO10 0xd6
>;
};
diff --git a/dts/upstream/src/arm64/freescale/imx8mm-venice-gw73xx.dtsi b/dts/upstream/src/arm64/freescale/imx8mm-venice-gw73xx.dtsi
index d79fe9f..2aa6c10 100644
--- a/dts/upstream/src/arm64/freescale/imx8mm-venice-gw73xx.dtsi
+++ b/dts/upstream/src/arm64/freescale/imx8mm-venice-gw73xx.dtsi
@@ -109,7 +109,7 @@
status = "okay";
tpm@1 {
- compatible = "tcg,tpm_tis-spi";
+ compatible = "atmel,attpm20p", "tcg,tpm_tis-spi";
reg = <0x1>;
spi-max-frequency = <36000000>;
};
@@ -179,23 +179,30 @@
pcie@0,0 {
reg = <0x0000 0 0 0 0>;
- #address-cells = <1>;
- #size-cells = <0>;
+ device_type = "pci";
+ #address-cells = <3>;
+ #size-cells = <2>;
+ ranges;
- pcie@1,0 {
+ pcie@0,0 {
reg = <0x0000 0 0 0 0>;
- #address-cells = <1>;
- #size-cells = <0>;
+ device_type = "pci";
+ #address-cells = <3>;
+ #size-cells = <2>;
+ ranges;
- pcie@2,4 {
+ pcie@4,0 {
reg = <0x2000 0 0 0 0>;
- #address-cells = <1>;
- #size-cells = <0>;
+ device_type = "pci";
+ #address-cells = <3>;
+ #size-cells = <2>;
+ ranges;
- eth1: pcie@6,0 {
+ eth1: ethernet@0,0 {
reg = <0x0000 0 0 0 0>;
- #address-cells = <1>;
- #size-cells = <0>;
+ #address-cells = <3>;
+ #size-cells = <2>;
+ ranges;
local-mac-address = [00 00 00 00 00 00];
};
diff --git a/dts/upstream/src/arm64/freescale/imx8mm-venice-gw7902.dts b/dts/upstream/src/arm64/freescale/imx8mm-venice-gw7902.dts
index 06a394a..c11260c 100644
--- a/dts/upstream/src/arm64/freescale/imx8mm-venice-gw7902.dts
+++ b/dts/upstream/src/arm64/freescale/imx8mm-venice-gw7902.dts
@@ -635,13 +635,16 @@
pcie@0,0 {
reg = <0x0000 0 0 0 0>;
- #address-cells = <1>;
- #size-cells = <0>;
+ device_type = "pci";
+ #address-cells = <3>;
+ #size-cells = <2>;
+ ranges;
- eth1: pcie@1,0 {
+ eth1: ethernet@0,0 {
reg = <0x0000 0 0 0 0>;
- #address-cells = <1>;
- #size-cells = <0>;
+ #address-cells = <3>;
+ #size-cells = <2>;
+ ranges;
local-mac-address = [00 00 00 00 00 00];
};
diff --git a/dts/upstream/src/arm64/freescale/imx8mm-verdin-mallow.dtsi b/dts/upstream/src/arm64/freescale/imx8mm-verdin-mallow.dtsi
new file mode 100644
index 0000000..4a0799d
--- /dev/null
+++ b/dts/upstream/src/arm64/freescale/imx8mm-verdin-mallow.dtsi
@@ -0,0 +1,173 @@
+// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
+/*
+ * Copyright 2023 Toradex
+ *
+ * Common dtsi for Verdin IMX8MM SoM on Mallow carrier board
+ *
+ * https://www.toradex.com/computer-on-modules/verdin-arm-family/nxp-imx-8m-mini-nano
+ * https://www.toradex.com/products/carrier-board/mallow-carrier-board
+ */
+
+#include <dt-bindings/leds/common.h>
+
+/ {
+ leds {
+ compatible = "gpio-leds";
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_leds>;
+
+ /* SODIMM 52 - USER_LED_1_RED */
+ led-0 {
+ color = <LED_COLOR_ID_RED>;
+ function = LED_FUNCTION_DEBUG;
+ function-enumerator = <1>;
+ gpios = <&gpio3 0 GPIO_ACTIVE_HIGH>;
+ };
+
+ /* SODIMM 54 - USER_LED_1_GREEN */
+ led-1 {
+ color = <LED_COLOR_ID_GREEN>;
+ function = LED_FUNCTION_DEBUG;
+ function-enumerator = <1>;
+ gpios = <&gpio3 1 GPIO_ACTIVE_HIGH>;
+ };
+
+ /* SODIMM 56 - USER_LED_2_RED */
+ led-2 {
+ color = <LED_COLOR_ID_RED>;
+ function = LED_FUNCTION_DEBUG;
+ function-enumerator = <2>;
+ gpios = <&gpio3 6 GPIO_ACTIVE_HIGH>;
+ };
+
+ /* SODIMM 58 - USER_LED_2_GREEN */
+ led-3 {
+ color = <LED_COLOR_ID_GREEN>;
+ function = LED_FUNCTION_DEBUG;
+ function-enumerator = <2>;
+ gpios = <&gpio3 7 GPIO_ACTIVE_HIGH>;
+ };
+ };
+};
+
+/* Verdin SPI_1 */
+&ecspi2 {
+ pinctrl-0 = <&pinctrl_ecspi2>, <&pinctrl_tpm_cs>;
+ cs-gpios = <&gpio5 13 GPIO_ACTIVE_LOW>, <&gpio3 2 GPIO_ACTIVE_LOW>;
+ status = "okay";
+
+ tpm@1 {
+ compatible = "infineon,slb9670", "tcg,tpm_tis-spi";
+ reg = <1>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_tpm_irq>;
+ interrupt-parent = <&gpio3>;
+ interrupts = <14 IRQ_TYPE_LEVEL_LOW>;
+ spi-max-frequency = <18500000>;
+ };
+};
+
+/* EEPROM on Mallow */
+&eeprom_carrier_board {
+ status = "okay";
+};
+
+/* Verdin ETH_1 */
+&fec1 {
+ status = "okay";
+};
+
+/* Temperature sensor on Mallow */
+&hwmon_temp {
+ compatible = "ti,tmp1075";
+ status = "okay";
+};
+
+/* Verdin I2C_2_DSI */
+&i2c2 {
+ status = "okay";
+};
+
+/* Verdin I2C_4_CSI */
+&i2c3 {
+ status = "okay";
+};
+
+/* Verdin I2C_1 */
+&i2c4 {
+ status = "okay";
+};
+
+/* Verdin PCIE_1 */
+&pcie0 {
+ status = "okay";
+};
+
+&pcie_phy {
+ status = "okay";
+};
+
+/* Verdin PWM_3_DSI */
+&pwm1 {
+ status = "okay";
+};
+
+/* Verdin PWM_1 */
+&pwm2 {
+ status = "okay";
+};
+
+/* Verdin PWM_2 */
+&pwm3 {
+ status = "okay";
+};
+
+/* Verdin UART_3 */
+&uart1 {
+ status = "okay";
+};
+
+/* Verdin UART_1 */
+&uart2 {
+ status = "okay";
+};
+
+/* Verdin UART_2 */
+&uart3 {
+ status = "okay";
+};
+
+/* Verdin USB_1 */
+&usbotg1 {
+ status = "okay";
+};
+
+/* Verdin USB_2 */
+&usbotg2 {
+ status = "okay";
+};
+
+/* Verdin SD_1 */
+&usdhc2 {
+ status = "okay";
+};
+
+&iomuxc {
+ pinctrl_leds: ledsgrp {
+ fsl,pins =
+ <MX8MM_IOMUXC_NAND_ALE_GPIO3_IO0 0x106>, /* SODIMM 52 */
+ <MX8MM_IOMUXC_NAND_CE0_B_GPIO3_IO1 0x106>, /* SODIMM 54 */
+ <MX8MM_IOMUXC_NAND_DATA00_GPIO3_IO6 0x106>, /* SODIMM 56 */
+ <MX8MM_IOMUXC_NAND_DATA01_GPIO3_IO7 0x106>; /* SODIMM 58 */
+ };
+
+ pinctrl_tpm_cs: tpmcsgrp {
+ fsl,pins =
+ <MX8MM_IOMUXC_NAND_CE1_B_GPIO3_IO2 0x146>; /* SODIMM 64 */
+ };
+
+ pinctrl_tpm_irq: tpmirqgrp {
+ fsl,pins =
+ <MX8MM_IOMUXC_NAND_DQS_GPIO3_IO14 0x141>; /* SODIMM 66 */
+ };
+};
diff --git a/dts/upstream/src/arm64/freescale/imx8mm-verdin-nonwifi-mallow.dts b/dts/upstream/src/arm64/freescale/imx8mm-verdin-nonwifi-mallow.dts
new file mode 100644
index 0000000..1b1999f
--- /dev/null
+++ b/dts/upstream/src/arm64/freescale/imx8mm-verdin-nonwifi-mallow.dts
@@ -0,0 +1,18 @@
+// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
+/*
+ * Copyright 2023 Toradex
+ */
+
+/dts-v1/;
+
+#include "imx8mm-verdin.dtsi"
+#include "imx8mm-verdin-nonwifi.dtsi"
+#include "imx8mm-verdin-mallow.dtsi"
+
+/ {
+ model = "Toradex Verdin iMX8M Mini on Mallow";
+ compatible = "toradex,verdin-imx8mm-nonwifi-mallow",
+ "toradex,verdin-imx8mm-nonwifi",
+ "toradex,verdin-imx8mm",
+ "fsl,imx8mm";
+};
diff --git a/dts/upstream/src/arm64/freescale/imx8mm-verdin-wifi-mallow.dts b/dts/upstream/src/arm64/freescale/imx8mm-verdin-wifi-mallow.dts
new file mode 100644
index 0000000..2916145
--- /dev/null
+++ b/dts/upstream/src/arm64/freescale/imx8mm-verdin-wifi-mallow.dts
@@ -0,0 +1,18 @@
+// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
+/*
+ * Copyright 2023 Toradex
+ */
+
+/dts-v1/;
+
+#include "imx8mm-verdin.dtsi"
+#include "imx8mm-verdin-wifi.dtsi"
+#include "imx8mm-verdin-mallow.dtsi"
+
+/ {
+ model = "Toradex Verdin iMX8M Mini WB on Mallow";
+ compatible = "toradex,verdin-imx8mm-wifi-mallow",
+ "toradex,verdin-imx8mm-wifi",
+ "toradex,verdin-imx8mm",
+ "fsl,imx8mm";
+};
diff --git a/dts/upstream/src/arm64/freescale/imx8mm.dtsi b/dts/upstream/src/arm64/freescale/imx8mm.dtsi
index 738024b..8a1b42b 100644
--- a/dts/upstream/src/arm64/freescale/imx8mm.dtsi
+++ b/dts/upstream/src/arm64/freescale/imx8mm.dtsi
@@ -636,6 +636,8 @@
clk: clock-controller@30380000 {
compatible = "fsl,imx8mm-ccm";
reg = <0x30380000 0x10000>;
+ interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
#clock-cells = <1>;
clocks = <&osc_32k>, <&osc_24m>, <&clk_ext1>, <&clk_ext2>,
<&clk_ext3>, <&clk_ext4>;
@@ -647,7 +649,6 @@
<&clk IMX8MM_CLK_AUDIO_AHB>,
<&clk IMX8MM_CLK_IPG_AUDIO_ROOT>,
<&clk IMX8MM_SYS_PLL3>,
- <&clk IMX8MM_VIDEO_PLL1>,
<&clk IMX8MM_AUDIO_PLL1>;
assigned-clock-parents = <&clk IMX8MM_SYS_PLL1_800M>,
<&clk IMX8MM_ARM_PLL_OUT>,
@@ -657,7 +658,6 @@
<400000000>,
<400000000>,
<750000000>,
- <594000000>,
<393216000>;
};
@@ -1133,7 +1133,7 @@
assigned-clock-parents = <&clk IMX8MM_VIDEO_PLL1_OUT>,
<&clk IMX8MM_SYS_PLL2_1000M>,
<&clk IMX8MM_SYS_PLL1_800M>;
- assigned-clock-rates = <594000000>, <500000000>, <200000000>;
+ assigned-clock-rates = <24000000>, <500000000>, <200000000>;
interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
power-domains = <&disp_blk_ctrl IMX8MM_DISPBLK_PD_LCDIF>;
status = "disabled";
@@ -1151,12 +1151,8 @@
clocks = <&clk IMX8MM_CLK_DSI_CORE>,
<&clk IMX8MM_CLK_DSI_PHY_REF>;
clock-names = "bus_clk", "sclk_mipi";
- assigned-clocks = <&clk IMX8MM_CLK_DSI_CORE>,
- <&clk IMX8MM_CLK_DSI_PHY_REF>;
- assigned-clock-parents = <&clk IMX8MM_SYS_PLL1_266M>,
- <&clk IMX8MM_CLK_24M>;
- assigned-clock-rates = <266000000>, <24000000>;
- samsung,pll-clock-frequency = <24000000>;
+ assigned-clocks = <&clk IMX8MM_CLK_DSI_CORE>;
+ assigned-clock-parents = <&clk IMX8MM_SYS_PLL1_266M>;
interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>;
power-domains = <&disp_blk_ctrl IMX8MM_DISPBLK_PD_MIPI_DSI>;
status = "disabled";
@@ -1408,7 +1404,7 @@
assigned-clocks = <&clk IMX8MM_CLK_GPU3D_CORE>,
<&clk IMX8MM_GPU_PLL_OUT>;
assigned-clock-parents = <&clk IMX8MM_GPU_PLL_OUT>;
- assigned-clock-rates = <0>, <1000000000>;
+ assigned-clock-rates = <0>, <800000000>;
power-domains = <&pgc_gpu>;
};
@@ -1423,7 +1419,7 @@
assigned-clocks = <&clk IMX8MM_CLK_GPU2D_CORE>,
<&clk IMX8MM_GPU_PLL_OUT>;
assigned-clock-parents = <&clk IMX8MM_GPU_PLL_OUT>;
- assigned-clock-rates = <0>, <1000000000>;
+ assigned-clock-rates = <0>, <800000000>;
power-domains = <&pgc_gpu>;
};
diff --git a/dts/upstream/src/arm64/freescale/imx8mn-beacon-som.dtsi b/dts/upstream/src/arm64/freescale/imx8mn-beacon-som.dtsi
index 90073b1..2a64115 100644
--- a/dts/upstream/src/arm64/freescale/imx8mn-beacon-som.dtsi
+++ b/dts/upstream/src/arm64/freescale/imx8mn-beacon-som.dtsi
@@ -3,6 +3,8 @@
* Copyright 2020 Compass Electronics Group, LLC
*/
+#include "imx8mn-overdrive.dtsi"
+
/ {
aliases {
rtc0 = &rtc;
diff --git a/dts/upstream/src/arm64/freescale/imx8mn-bsh-smm-s2-common.dtsi b/dts/upstream/src/arm64/freescale/imx8mn-bsh-smm-s2-common.dtsi
index 22a754d..bbb07c6 100644
--- a/dts/upstream/src/arm64/freescale/imx8mn-bsh-smm-s2-common.dtsi
+++ b/dts/upstream/src/arm64/freescale/imx8mn-bsh-smm-s2-common.dtsi
@@ -7,6 +7,7 @@
/dts-v1/;
#include "imx8mn.dtsi"
+#include "imx8mn-bsh-smm-s2-display.dtsi"
/ {
chosen {
diff --git a/dts/upstream/src/arm64/freescale/imx8mn-bsh-smm-s2-display.dtsi b/dts/upstream/src/arm64/freescale/imx8mn-bsh-smm-s2-display.dtsi
new file mode 100644
index 0000000..7675583
--- /dev/null
+++ b/dts/upstream/src/arm64/freescale/imx8mn-bsh-smm-s2-display.dtsi
@@ -0,0 +1,121 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright 2021 BSH
+ */
+
+/ {
+ backlight: backlight {
+ compatible = "pwm-backlight";
+ pwms = <&pwm1 0 700000 0>; /* 700000 ns = 1337Hz */
+ brightness-levels = <0 100>;
+ num-interpolated-steps = <100>;
+ default-brightness-level = <50>;
+ status = "okay";
+ };
+
+ reg_3v3_dvdd: regulator-3v3-O3 {
+ compatible = "regulator-fixed";
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_dvdd>;
+ regulator-name = "3v3-dvdd-supply";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ gpio = <&gpio1 7 GPIO_ACTIVE_LOW>;
+ };
+
+ reg_v3v3_avdd: regulator-3v3-O2 {
+ compatible = "regulator-fixed";
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_avdd>;
+ regulator-name = "3v3-avdd-supply";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ gpio = <&gpio1 5 GPIO_ACTIVE_LOW>;
+ };
+};
+
+&pwm1 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_bl>;
+ status = "okay";
+};
+
+&lcdif {
+ assigned-clocks = <&clk IMX8MN_VIDEO_PLL1>;
+ assigned-clock-rates = <594000000>;
+ status = "okay";
+};
+
+&pgc_dispmix {
+ assigned-clocks = <&clk IMX8MN_CLK_DISP_AXI>, <&clk IMX8MN_CLK_DISP_APB>;
+ assigned-clock-parents = <&clk IMX8MN_SYS_PLL2_1000M>, <&clk IMX8MN_SYS_PLL1_800M>;
+ assigned-clock-rates = <500000000>, <200000000>;
+};
+
+&mipi_dsi {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ samsung,esc-clock-frequency = <20000000>;
+ samsung,pll-clock-frequency = <12000000>;
+ status = "okay";
+
+ panel@0 {
+ compatible = "sharp,ls068b3sx02", "syna,r63353";
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_panel>;
+ reg = <0>;
+
+ backlight = <&backlight>;
+ dvdd-supply = <®_3v3_dvdd>;
+ avdd-supply = <®_v3v3_avdd>;
+ reset-gpios = <&gpio4 29 GPIO_ACTIVE_HIGH>;
+
+ port {
+ panel_in: endpoint {
+ remote-endpoint = <&mipi_dsi_out>;
+ };
+ };
+
+ };
+
+ ports {
+ port@1 {
+ reg = <1>;
+
+ mipi_dsi_out: endpoint {
+ remote-endpoint = <&panel_in>;
+ };
+ };
+ };
+};
+
+&gpu {
+ status = "okay";
+};
+
+&iomuxc {
+ pinctrl_avdd: avddgrp {
+ fsl,pins = <
+ MX8MN_IOMUXC_GPIO1_IO05_GPIO1_IO5 0x16 /* VDD 3V3_VO2 */
+ >;
+ };
+
+ /* This is for both PWM and voltage regulators for display */
+ pinctrl_bl: blgrp {
+ fsl,pins = <
+ MX8MN_IOMUXC_GPIO1_IO01_PWM1_OUT 0x16
+ >;
+ };
+
+ pinctrl_dvdd: dvddgrp {
+ fsl,pins = <
+ MX8MN_IOMUXC_GPIO1_IO07_GPIO1_IO7 0x16 /* VDD 3V3_VO3 */
+ >;
+ };
+
+ pinctrl_panel: panelgrp {
+ fsl,pins = <
+ MX8MN_IOMUXC_SAI3_RXC_GPIO4_IO29 0x16 /* panel reset */
+ >;
+ };
+};
diff --git a/dts/upstream/src/arm64/freescale/imx8mn-dimonoff-gateway-evk.dts b/dts/upstream/src/arm64/freescale/imx8mn-dimonoff-gateway-evk.dts
new file mode 100644
index 0000000..6f9b829
--- /dev/null
+++ b/dts/upstream/src/arm64/freescale/imx8mn-dimonoff-gateway-evk.dts
@@ -0,0 +1,160 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright 2022 DimOnOff
+ */
+
+/dts-v1/;
+
+#include <dt-bindings/usb/pd.h>
+#include "imx8mn-var-som-symphony.dts"
+
+/ {
+ model = "DimOnOff Gateway EVK board";
+ compatible = "dimonoff,gateway-evk", "variscite,var-som-mx8mn",
+ "fsl,imx8mn";
+
+ /*
+ * U30 FPF2193 regulator.
+ * Source = BASE_PER_3V3 = SOM_3V3 (COM pin 49).
+ */
+ reg_disp_3v3: regulator-disp-3v3 {
+ compatible = "regulator-fixed";
+ regulator-name = "Display 3V3";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-always-on;
+ regulator-boot-on;
+ };
+
+ gpio-keys {
+ compatible = "gpio-keys";
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_gpio_keys>;
+
+ key-enter {
+ label = "enter";
+ gpios = <&gpio1 8 GPIO_ACTIVE_LOW>;
+ linux,code = <KEY_ENTER>;
+ wakeup-source;
+ };
+ };
+
+ /* Bourns PEC12R rotary encoder, 24 steps. */
+ rotary: rotary-encoder {
+ compatible = "rotary-encoder";
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_rotary>;
+ gpios = <&gpio5 12 GPIO_ACTIVE_LOW>, /* A */
+ <&gpio5 13 GPIO_ACTIVE_LOW>; /* B */
+ linux,axis = <0>; /* REL_X */
+ rotary-encoder,encoding = "gray";
+ rotary-encoder,relative-axis;
+ };
+};
+
+/* Disable Asynchronous Sample Rate Converter (audio) */
+&easrc {
+ status = "disabled";
+};
+
+&ecspi1 {
+ /* Resistive touch controller */
+ /delete-node/ touchscreen@0;
+};
+
+&gpu {
+ status = "disabled";
+};
+
+&i2c2 {
+ adc@48 {
+ compatible = "ti,ads7924";
+ reg = <0x48>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_adc>;
+ vref-supply = <®_disp_3v3>;
+ reset-gpios = <&gpio5 5 GPIO_ACTIVE_LOW>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ channel@0 {
+ reg = <0>;
+ label = "Pot0";
+ };
+ channel@1 {
+ reg = <1>;
+ label = "Pot1";
+ };
+ channel@2 {
+ reg = <2>;
+ label = "Pot2";
+ };
+ channel@3 {
+ reg = <3>;
+ label = "Pot3";
+ };
+ };
+
+ rtc@51 {
+ compatible = "nxp,pcf2129";
+ reg = <0x51>;
+ reset-source; /* For watchdog. */
+ };
+
+ rtc@53 {
+ compatible = "nxp,pcf2131";
+ reg = <0x53>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_rtc>;
+ reset-source; /* For watchdog. */
+ interrupt-parent = <&gpio5>;
+ interrupts = <10 IRQ_TYPE_EDGE_FALLING>; /* J17.6 on EVK */
+ };
+};
+
+&i2c3 {
+ touchscreen@38 {
+ status = "disabled";
+ };
+
+ codec@1a {
+ status = "disabled";
+ };
+
+ /* DS1337 RTC module */
+ rtc@68 {
+ status = "disabled";
+ };
+};
+
+&sai5 {
+ status = "disabled";
+};
+
+&iomuxc {
+ pinctrl_gpio_keys: gpiokeysgrp {
+ fsl,pins = <
+ MX8MN_IOMUXC_GPIO1_IO08_GPIO1_IO8 0xc6
+ >;
+ };
+
+ pinctrl_rotary: rotarygrp {
+ fsl,pins = <
+ MX8MN_IOMUXC_ECSPI2_MISO_GPIO5_IO12 0x00000156
+ MX8MN_IOMUXC_ECSPI2_SS0_GPIO5_IO13 0x00000156
+ >;
+ };
+
+ pinctrl_adc: adcgrp {
+ fsl,pins = <
+ MX8MN_IOMUXC_SPDIF_EXT_CLK_GPIO5_IO5 0x00000156
+ >;
+ };
+
+ pinctrl_rtc: rtcgrp {
+ fsl,pins = <
+ MX8MN_IOMUXC_ECSPI2_SCLK_GPIO5_IO10 0x00000156
+ MX8MN_IOMUXC_ECSPI2_MOSI_GPIO5_IO11 0x00000156
+ >;
+ };
+};
diff --git a/dts/upstream/src/arm64/freescale/imx8mn-evk.dtsi b/dts/upstream/src/arm64/freescale/imx8mn-evk.dtsi
index 3f6a198..a0e13d3 100644
--- a/dts/upstream/src/arm64/freescale/imx8mn-evk.dtsi
+++ b/dts/upstream/src/arm64/freescale/imx8mn-evk.dtsi
@@ -221,12 +221,6 @@
interrupts = <11 IRQ_TYPE_LEVEL_LOW>;
status = "okay";
- port {
- typec1_dr_sw: endpoint {
- remote-endpoint = <&usb1_drd_sw>;
- };
- };
-
typec1_con: connector {
compatible = "usb-c-connector";
label = "USB-C";
@@ -238,6 +232,12 @@
PDO_VAR(5000, 20000, 3000)>;
op-sink-microwatt = <15000000>;
self-powered;
+
+ port {
+ typec1_dr_sw: endpoint {
+ remote-endpoint = <&usb1_drd_sw>;
+ };
+ };
};
};
};
diff --git a/dts/upstream/src/arm64/freescale/imx8mn-overdrive.dtsi b/dts/upstream/src/arm64/freescale/imx8mn-overdrive.dtsi
new file mode 100644
index 0000000..5d03fb8
--- /dev/null
+++ b/dts/upstream/src/arm64/freescale/imx8mn-overdrive.dtsi
@@ -0,0 +1,18 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+
+&gpu {
+ assigned-clocks = <&clk IMX8MN_CLK_GPU_CORE>,
+ <&clk IMX8MN_CLK_GPU_SHADER>,
+ <&clk IMX8MN_CLK_GPU_AXI>,
+ <&clk IMX8MN_CLK_GPU_AHB>,
+ <&clk IMX8MN_GPU_PLL>;
+ assigned-clock-parents = <&clk IMX8MN_GPU_PLL_OUT>,
+ <&clk IMX8MN_GPU_PLL_OUT>,
+ <&clk IMX8MN_SYS_PLL1_800M>,
+ <&clk IMX8MN_SYS_PLL1_800M>;
+ assigned-clock-rates = <600000000>,
+ <600000000>,
+ <800000000>,
+ <400000000>,
+ <1200000000>;
+};
diff --git a/dts/upstream/src/arm64/freescale/imx8mn-rve-gateway.dts b/dts/upstream/src/arm64/freescale/imx8mn-rve-gateway.dts
new file mode 100644
index 0000000..1b633bd
--- /dev/null
+++ b/dts/upstream/src/arm64/freescale/imx8mn-rve-gateway.dts
@@ -0,0 +1,285 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright 2023 DimOnOff
+ */
+
+/dts-v1/;
+
+#include <dt-bindings/usb/pd.h>
+#include "imx8mn-var-som.dtsi"
+
+/ {
+ model = "RVE gateway";
+ compatible = "rve,rve-gateway", "variscite,var-som-mx8mn", "fsl,imx8mn";
+
+ crystal_duart_24m: crystal-duart-24m {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <24000000>;
+ };
+
+ gpio-keys {
+ compatible = "gpio-keys";
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_gpio_keys>;
+
+ key-enter {
+ label = "enter";
+ gpios = <&gpio1 1 GPIO_ACTIVE_LOW>;
+ linux,code = <KEY_ENTER>;
+ };
+
+ key-exit {
+ label = "exit";
+ gpios = <&gpio3 23 GPIO_ACTIVE_LOW>;
+ linux,code = <KEY_ESC>;
+ };
+ };
+
+ lcd {
+ compatible = "hit,hd44780";
+ display-height-chars = <2>;
+ display-width-chars = <20>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_lcd>;
+ data-gpios = <&gpio5 1 GPIO_ACTIVE_HIGH>,
+ <&gpio1 6 GPIO_ACTIVE_HIGH>,
+ <&gpio1 14 GPIO_ACTIVE_HIGH>,
+ <&gpio4 28 GPIO_ACTIVE_HIGH>,
+ <&gpio5 24 GPIO_ACTIVE_HIGH>,
+ <&gpio5 2 GPIO_ACTIVE_HIGH>,
+ <&gpio1 12 GPIO_ACTIVE_HIGH>,
+ <&gpio5 25 GPIO_ACTIVE_HIGH>;
+ enable-gpios = <&gpio5 23 GPIO_ACTIVE_HIGH>;
+ rs-gpios = <&gpio1 7 GPIO_ACTIVE_HIGH>;
+ rw-gpios = <&gpio4 27 GPIO_ACTIVE_HIGH>;
+ };
+
+ reg_3p3v: regulator-3p3v {
+ compatible = "regulator-fixed";
+ regulator-name = "3P3V";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-always-on;
+ };
+
+ /* Bourns PEC12R rotary encoder, 24 steps. */
+ rotary: rotary-encoder {
+ compatible = "rotary-encoder";
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_rotary>;
+ gpios = <&gpio1 5 GPIO_ACTIVE_LOW>, /* A */
+ <&gpio3 21 GPIO_ACTIVE_LOW>; /* B */
+ linux,axis = <0>; /* REL_X */
+ rotary-encoder,encoding = "gray";
+ rotary-encoder,relative-axis;
+ };
+};
+
+&ecspi1 {
+ cs-gpios = <&gpio5 9 GPIO_ACTIVE_LOW>;
+
+ duart1: serial@0 {
+ compatible = "nxp,sc16is752";
+ reg = <0>;
+ spi-rx-bus-width = <1>;
+ spi-tx-bus-width = <1>;
+ spi-max-frequency = <4000000>;
+ clocks = <&crystal_duart_24m>;
+ interrupt-parent = <&gpio3>;
+ interrupts = <22 IRQ_TYPE_EDGE_FALLING>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ gpio-line-names = "RADIO0", "RADIO1", "RADIO2", "RADIO3",
+ "RADIO4", "RADIO_RESET", "TP12", "TP11";
+ linux,rs485-enabled-at-boot-time;
+ rs485-rts-active-low;
+ };
+
+ /delete-node/ touchscreen@0;
+};
+
+&ecspi2 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_ecspi2>;
+ cs-gpios = <&gpio5 13 GPIO_ACTIVE_LOW>;
+ /delete-property/ dmas;
+ /delete-property/ dma-names;
+ status = "okay";
+
+ duart2: serial@0 {
+ compatible = "nxp,sc16is752";
+ reg = <0>;
+ spi-rx-bus-width = <1>;
+ spi-tx-bus-width = <1>;
+ spi-max-frequency = <4000000>;
+ clocks = <&crystal_duart_24m>;
+ interrupt-parent = <&gpio3>;
+ interrupts = <20 IRQ_TYPE_EDGE_FALLING>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ gpio-line-names = "LED_B_USER", "LED_R_USER", "LED_G_USER",
+ "GPIO_EXT3", "GPIO_EXT2", "GPIO_EXT1",
+ "GPIO_EXT0", "TP13";
+ linux,rs485-enabled-at-boot-time;
+ rs485-rts-active-low;
+ };
+};
+
+/* Configure PWM pins in GPIO mode: */
+&gpio5 {
+ gpio-line-names = "", "", "", "PWM3", "PWM2", "PWM1";
+};
+
+&gpu {
+ status = "disabled";
+};
+
+&i2c2 {
+ clock-frequency = <400000>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_i2c2>;
+ status = "okay";
+
+ /* Carrier board EEPROM */
+ eeprom_cb: eeprom@56 {
+ compatible = "atmel,24c04";
+ reg = <0x56>;
+ pagesize = <16>;
+ vcc-supply = <®_3p3v>;
+ };
+
+ lm75: sensor@48 {
+ compatible = "st,stlm75";
+ reg = <0x48>;
+ vs-supply = <®_3p3v>;
+ };
+
+ mcp7940: rtc@6f {
+ compatible = "microchip,mcp7940x";
+ reg = <0x6f>;
+ };
+};
+
+&i2c3 {
+ codec@1a {
+ status = "disabled";
+ };
+};
+
+&i2c4 {
+ clock-frequency = <400000>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_i2c4>;
+ status = "okay";
+
+ pcf8574_1: gpio@38 {
+ compatible = "nxp,pcf8574";
+ reg = <0x38>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ gpio-line-names = "LED_B_COMM3", "LED_R_COMM3", "LED_G_COMM3",
+ "TP14", "TP15", "LED_G_COMM4", "LED_R_COMM4",
+ "LED_B_COMM4";
+ };
+
+ pcf8574_2: gpio@39 {
+ compatible = "nxp,pcf8574";
+ reg = <0x39>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ gpio-line-names = "LED_B_COMM2", "LED_G_COMM2", "LED_B_COMM1",
+ "LED_R_COMM2", "LED_R_COMM1", "LED_G_COMM1",
+ "TP16", "TP17";
+ };
+};
+
+/* Bluetooth */
+&uart2 {
+ status = "disabled";
+};
+
+&usbotg1 {
+ dr_mode = "host";
+ disable-over-current;
+ status = "okay";
+};
+
+/* SD interface on expansion connector. */
+&usdhc2 {
+ vmmc-supply = <®_3p3v>;
+ cd-gpios = <&gpio1 13 GPIO_ACTIVE_LOW>;
+};
+
+&iomuxc {
+ pinctrl_ecspi1: ecspi1grp {
+ fsl,pins = <
+ MX8MN_IOMUXC_ECSPI1_SCLK_ECSPI1_SCLK 0x13
+ MX8MN_IOMUXC_ECSPI1_MOSI_ECSPI1_MOSI 0x13
+ MX8MN_IOMUXC_ECSPI1_MISO_ECSPI1_MISO 0x13
+ MX8MN_IOMUXC_ECSPI1_SS0_GPIO5_IO9 0x13 /* SS0 */
+ MX8MN_IOMUXC_SAI5_RXD1_GPIO3_IO22 0x13 /* SC16 IRQ */
+ >;
+ };
+
+ pinctrl_ecspi2: ecspi2grp {
+ fsl,pins = <
+ MX8MN_IOMUXC_ECSPI2_SCLK_ECSPI2_SCLK 0x13
+ MX8MN_IOMUXC_ECSPI2_MOSI_ECSPI2_MOSI 0x13
+ MX8MN_IOMUXC_ECSPI2_MISO_ECSPI2_MISO 0x13
+ MX8MN_IOMUXC_ECSPI2_SS0_GPIO5_IO13 0x13 /* SS0 */
+ MX8MN_IOMUXC_SAI5_RXC_GPIO3_IO20 0x13 /* SC16 IRQ */
+ >;
+ };
+
+ pinctrl_gpio_keys: gpiokeysgrp {
+ fsl,pins = <
+ MX8MN_IOMUXC_GPIO1_IO01_GPIO1_IO1 0xc6 /* Enter */
+ MX8MN_IOMUXC_SAI5_RXD2_GPIO3_IO23 0xc6 /* Exit */
+ >;
+ };
+
+ pinctrl_i2c2: i2c2grp {
+ fsl,pins = <
+ MX8MN_IOMUXC_I2C2_SCL_I2C2_SCL 0x400001c3
+ MX8MN_IOMUXC_I2C2_SDA_I2C2_SDA 0x400001c3
+ >;
+ };
+
+ pinctrl_i2c4: i2c4grp {
+ fsl,pins = <
+ MX8MN_IOMUXC_I2C4_SCL_I2C4_SCL 0x400001c3
+ MX8MN_IOMUXC_I2C4_SDA_I2C4_SDA 0x400001c3
+ >;
+ };
+
+ pinctrl_lcd: lcdgrp {
+ fsl,pins = <
+ MX8MN_IOMUXC_SAI3_TXD_GPIO5_IO1 0x00000156 /* D0 */
+ MX8MN_IOMUXC_GPIO1_IO06_GPIO1_IO6 0x00000156 /* D1 */
+ MX8MN_IOMUXC_GPIO1_IO14_GPIO1_IO14 0x00000156 /* D2 */
+ MX8MN_IOMUXC_SAI3_RXFS_GPIO4_IO28 0x00000156 /* D3 */
+ MX8MN_IOMUXC_UART2_RXD_GPIO5_IO24 0x00000156 /* D4 */
+ MX8MN_IOMUXC_SAI3_MCLK_GPIO5_IO2 0x00000156 /* D5 */
+ MX8MN_IOMUXC_GPIO1_IO12_GPIO1_IO12 0x00000156 /* D6 */
+ MX8MN_IOMUXC_UART2_TXD_GPIO5_IO25 0x00000156 /* D7 */
+ MX8MN_IOMUXC_UART1_TXD_GPIO5_IO23 0x00000156 /* E */
+ MX8MN_IOMUXC_GPIO1_IO07_GPIO1_IO7 0x00000156 /* RS */
+ MX8MN_IOMUXC_SAI2_MCLK_GPIO4_IO27 0x00000156 /* R/W */
+ >;
+ };
+
+ pinctrl_rotary: rotarygrp {
+ fsl,pins = <
+ MX8MN_IOMUXC_GPIO1_IO05_GPIO1_IO5 0x00000156 /* A */
+ MX8MN_IOMUXC_SAI5_RXD0_GPIO3_IO21 0x00000156 /* B */
+ >;
+ };
+
+ /* Override Card Detect function GPIO value (GPIO1_IO10) from SOM: */
+ pinctrl_usdhc2_gpio: usdhc2gpiogrp {
+ fsl,pins = <
+ MX8MN_IOMUXC_GPIO1_IO13_GPIO1_IO13 0x41
+ >;
+ };
+};
diff --git a/dts/upstream/src/arm64/freescale/imx8mn-tqma8mqnl-mba8mx.dts b/dts/upstream/src/arm64/freescale/imx8mn-tqma8mqnl-mba8mx.dts
index 3f1e49b..c07d591 100644
--- a/dts/upstream/src/arm64/freescale/imx8mn-tqma8mqnl-mba8mx.dts
+++ b/dts/upstream/src/arm64/freescale/imx8mn-tqma8mqnl-mba8mx.dts
@@ -11,6 +11,7 @@
/ {
model = "TQ-Systems GmbH i.MX8MN TQMa8MxNL on MBa8Mx";
compatible = "tq,imx8mn-tqma8mqnl-mba8mx", "tq,imx8mn-tqma8mqnl", "fsl,imx8mn";
+ chassis-type = "embedded";
aliases {
eeprom0 = &eeprom3;
diff --git a/dts/upstream/src/arm64/freescale/imx8mn-var-som-symphony.dts b/dts/upstream/src/arm64/freescale/imx8mn-var-som-symphony.dts
index a7a5744..a6b94d1 100644
--- a/dts/upstream/src/arm64/freescale/imx8mn-var-som-symphony.dts
+++ b/dts/upstream/src/arm64/freescale/imx8mn-var-som-symphony.dts
@@ -57,6 +57,15 @@
linux,default-trigger = "heartbeat";
};
};
+
+ /* Peripherals supply, enabled by Q2 after SOM_3V3 rises. */
+ reg_per_3v3: regulator-peripheral-3v3 {
+ compatible = "regulator-fixed";
+ regulator-name = "per_3v3";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-always-on;
+ };
};
ðphy {
@@ -79,6 +88,7 @@
interrupts = <7 IRQ_TYPE_EDGE_FALLING>;
#gpio-cells = <2>;
wakeup-source;
+ vcc-supply = <®_per_3v3>;
/* USB 3.0 OTG (usbotg1) / SATA port switch, set to USB 3.0 */
usb3-sata-sel-hog {
diff --git a/dts/upstream/src/arm64/freescale/imx8mn-var-som.dtsi b/dts/upstream/src/arm64/freescale/imx8mn-var-som.dtsi
index b8946ed..b364307 100644
--- a/dts/upstream/src/arm64/freescale/imx8mn-var-som.dtsi
+++ b/dts/upstream/src/arm64/freescale/imx8mn-var-som.dtsi
@@ -31,6 +31,14 @@
gpio = <&gpio2 9 GPIO_ACTIVE_HIGH>;
enable-active-high;
};
+
+ reg_3v3_fixed: regulator-3v3-fixed {
+ compatible = "regulator-fixed";
+ regulator-name = "fixed_3v3";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-always-on;
+ };
};
&A53_0 {
@@ -234,6 +242,7 @@
compatible = "atmel,24c04";
reg = <0x52>;
pagesize = <16>;
+ vcc-supply = <®_3v3_fixed>;
};
};
diff --git a/dts/upstream/src/arm64/freescale/imx8mn.dtsi b/dts/upstream/src/arm64/freescale/imx8mn.dtsi
index 1bb1d0c..136e75c 100644
--- a/dts/upstream/src/arm64/freescale/imx8mn.dtsi
+++ b/dts/upstream/src/arm64/freescale/imx8mn.dtsi
@@ -637,6 +637,8 @@
clk: clock-controller@30380000 {
compatible = "fsl,imx8mn-ccm";
reg = <0x30380000 0x10000>;
+ interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
#clock-cells = <1>;
clocks = <&osc_32k>, <&osc_24m>, <&clk_ext1>, <&clk_ext2>,
<&clk_ext3>, <&clk_ext4>;
diff --git a/dts/upstream/src/arm64/freescale/imx8mp-beacon-kit.dts b/dts/upstream/src/arm64/freescale/imx8mp-beacon-kit.dts
index 0bea079..a080574 100644
--- a/dts/upstream/src/arm64/freescale/imx8mp-beacon-kit.dts
+++ b/dts/upstream/src/arm64/freescale/imx8mp-beacon-kit.dts
@@ -94,6 +94,17 @@
};
};
+ bridge-connector {
+ compatible = "hdmi-connector";
+ type = "a";
+
+ port {
+ hdmi_con: endpoint {
+ remote-endpoint = <&adv7535_out>;
+ };
+ };
+ };
+
leds {
compatible = "gpio-leds";
pinctrl-names = "default";
@@ -153,6 +164,21 @@
enable-active-high;
};
+ sound-adv7535 {
+ compatible = "simple-audio-card";
+ simple-audio-card,name = "sound-adv7535";
+ simple-audio-card,format = "i2s";
+
+ simple-audio-card,cpu {
+ sound-dai = <&sai5>;
+ system-clock-direction-out;
+ };
+
+ simple-audio-card,codec {
+ sound-dai = <&adv_bridge>;
+ };
+ };
+
sound-dmic {
compatible = "simple-audio-card";
simple-audio-card,name = "sound-pdm";
@@ -208,7 +234,7 @@
status = "okay";
tpm: tpm@0 {
- compatible = "infineon,slb9670";
+ compatible = "infineon,slb9670", "tcg,tpm_tis-spi";
reg = <0>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_tpm>;
@@ -274,6 +300,35 @@
#interrupt-cells = <2>;
};
+ adv_bridge: hdmi@3d {
+ compatible = "adi,adv7535";
+ reg = <0x3d>, <0x3c>, <0x3e>, <0x3f>;
+ reg-names = "main", "cec", "edid", "packet";
+ adi,dsi-lanes = <4>;
+ #sound-dai-cells = <0>;
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+
+ adv7535_in: endpoint {
+ remote-endpoint = <&dsi_out>;
+ };
+ };
+
+ port@1 {
+ reg = <1>;
+
+ adv7535_out: endpoint {
+ remote-endpoint = <&hdmi_con>;
+ };
+ };
+ };
+ };
+
pcieclk: clock-generator@68 {
compatible = "renesas,9fgv0241";
reg = <0x68>;
@@ -398,6 +453,10 @@
};
};
+&lcdif1 {
+ status = "okay";
+};
+
&micfil {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_pdm>;
@@ -407,6 +466,21 @@
status = "okay";
};
+&mipi_dsi {
+ samsung,esc-clock-frequency = <10000000>;
+ status = "okay";
+
+ ports {
+ port@1 {
+ reg = <1>;
+
+ dsi_out: endpoint {
+ remote-endpoint = <&adv7535_in>;
+ };
+ };
+ };
+};
+
&pcie {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_pcie>;
@@ -433,6 +507,16 @@
status = "okay";
};
+&sai5 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_sai5>;
+ assigned-clocks = <&clk IMX8MP_CLK_SAI5>;
+ assigned-clock-parents = <&clk IMX8MP_AUDIO_PLL1_OUT>;
+ assigned-clock-rates = <12288000>;
+ fsl,sai-mclk-direction-output;
+ status = "okay";
+};
+
&snvs_pwrkey {
status = "okay";
};
@@ -612,6 +696,14 @@
>;
};
+ pinctrl_sai5: sai5grp {
+ fsl,pins = <
+ MX8MP_IOMUXC_SAI5_RXD3__AUDIOMIX_SAI5_TX_DATA00 0xd6
+ MX8MP_IOMUXC_SAI5_RXD2__AUDIOMIX_SAI5_TX_BCLK 0xd6
+ MX8MP_IOMUXC_SAI5_RXD1__AUDIOMIX_SAI5_TX_SYNC 0xd6
+ >;
+ };
+
pinctrl_tpm: tpmgrp {
fsl,pins = <
MX8MP_IOMUXC_SAI1_RXFS__GPIO4_IO00 0x19 /* Reset */
diff --git a/dts/upstream/src/arm64/freescale/imx8mp-data-modul-edm-sbc.dts b/dts/upstream/src/arm64/freescale/imx8mp-data-modul-edm-sbc.dts
index d98a040..5828c9d 100644
--- a/dts/upstream/src/arm64/freescale/imx8mp-data-modul-edm-sbc.dts
+++ b/dts/upstream/src/arm64/freescale/imx8mp-data-modul-edm-sbc.dts
@@ -486,7 +486,7 @@
&uart4 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_uart4>;
- status = "okay";
+ status = "disabled";
};
&usb3_phy0 {
diff --git a/dts/upstream/src/arm64/freescale/imx8mp-debix-model-a.dts b/dts/upstream/src/arm64/freescale/imx8mp-debix-model-a.dts
index 267ceff..2c19766 100644
--- a/dts/upstream/src/arm64/freescale/imx8mp-debix-model-a.dts
+++ b/dts/upstream/src/arm64/freescale/imx8mp-debix-model-a.dts
@@ -75,7 +75,7 @@
&eqos {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_eqos>;
- phy-connection-type = "rgmii-id";
+ phy-mode = "rgmii-id";
phy-handle = <ðphy0>;
status = "okay";
diff --git a/dts/upstream/src/arm64/freescale/imx8mp-debix-som-a-bmb-08.dts b/dts/upstream/src/arm64/freescale/imx8mp-debix-som-a-bmb-08.dts
index 0afd902..b11d694 100644
--- a/dts/upstream/src/arm64/freescale/imx8mp-debix-som-a-bmb-08.dts
+++ b/dts/upstream/src/arm64/freescale/imx8mp-debix-som-a-bmb-08.dts
@@ -63,6 +63,50 @@
regulator-always-on;
};
+ reg_csi1_1v8: regulator-csi1-vdd1v8 {
+ compatible = "regulator-fixed";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-name = "CSI1_VDD1V8";
+ gpio = <&expander0 13 GPIO_ACTIVE_HIGH>;
+ enable-active-high;
+ vin-supply = <®_baseboard_vdd3v3>;
+ };
+
+ reg_csi1_3v3: regulator-csi1-vdd3v3 {
+ compatible = "regulator-fixed";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-name = "CSI1_VDD3V3";
+ gpio = <&expander0 14 GPIO_ACTIVE_HIGH>;
+ enable-active-high;
+ vin-supply = <®_vdd5v0>;
+ };
+
+ reg_csi2_1v8: regulator-csi2-vdd1v8 {
+ compatible = "regulator-fixed";
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_reg_csi2_1v8>;
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-name = "CSI2_VDD1V8";
+ gpio = <&gpio3 21 GPIO_ACTIVE_HIGH>;
+ enable-active-high;
+ vin-supply = <®_baseboard_vdd3v3>;
+ };
+
+ reg_csi2_3v3: regulator-csi2-vdd3v3 {
+ compatible = "regulator-fixed";
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_reg_csi2_3v3>;
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-name = "CSI2_VDD3V3";
+ gpio = <&gpio4 25 GPIO_ACTIVE_HIGH>;
+ enable-active-high;
+ vin-supply = <®_vdd5v0>;
+ };
+
regulator-vbus-usb20 {
compatible = "regulator-fixed";
regulator-min-microvolt = <5000000>;
@@ -413,6 +457,18 @@
>;
};
+ pinctrl_reg_csi2_1v8: regcsi21v8grp {
+ fsl,pins = <
+ MX8MP_IOMUXC_SAI5_RXD0__GPIO3_IO21 0x19
+ >;
+ };
+
+ pinctrl_reg_csi2_3v3: regcsi23v3grp {
+ fsl,pins = <
+ MX8MP_IOMUXC_SAI2_TXC__GPIO4_IO25 0x19
+ >;
+ };
+
pinctrl_uart2: uart2grp {
fsl,pins = <
MX8MP_IOMUXC_UART2_RXD__UART2_DCE_RX 0x14f
diff --git a/dts/upstream/src/arm64/freescale/imx8mp-debix-som-a.dtsi b/dts/upstream/src/arm64/freescale/imx8mp-debix-som-a.dtsi
index bc312aa..91094c2 100644
--- a/dts/upstream/src/arm64/freescale/imx8mp-debix-som-a.dtsi
+++ b/dts/upstream/src/arm64/freescale/imx8mp-debix-som-a.dtsi
@@ -6,6 +6,8 @@
#include "imx8mp.dtsi"
+#include <dt-bindings/leds/common.h>
+
/ {
model = "Polyhex i.MX8MPlus Debix SOM A";
compatible = "polyhex,imx8mp-debix-som-a", "fsl,imx8mp";
@@ -20,6 +22,20 @@
gpio = <&gpio2 19 GPIO_ACTIVE_HIGH>;
enable-active-high;
};
+
+ gpio-leds {
+ compatible = "gpio-leds";
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_gpio_led>;
+
+ led-0 {
+ gpios = <&gpio3 16 GPIO_ACTIVE_HIGH>;
+ default-state = "on";
+ linux,default-trigger = "heartbeat";
+ function = LED_FUNCTION_STATUS;
+ color = <LED_COLOR_ID_GREEN>;
+ };
+ };
};
&A53_0 {
@@ -203,6 +219,12 @@
};
&iomuxc {
+ pinctrl_gpio_led: gpioledgrp {
+ fsl,pins = <
+ MX8MP_IOMUXC_NAND_READY_B__GPIO3_IO16 0x19
+ >;
+ };
+
pinctrl_i2c1: i2c1grp {
fsl,pins = <
MX8MP_IOMUXC_I2C1_SCL__I2C1_SCL 0x400001c2
diff --git a/dts/upstream/src/arm64/freescale/imx8mp-dhcom-som.dtsi b/dts/upstream/src/arm64/freescale/imx8mp-dhcom-som.dtsi
index d8963f3..43f1d45 100644
--- a/dts/upstream/src/arm64/freescale/imx8mp-dhcom-som.dtsi
+++ b/dts/upstream/src/arm64/freescale/imx8mp-dhcom-som.dtsi
@@ -255,7 +255,7 @@
<&clk IMX8MP_AUDIO_PLL2_OUT>;
assigned-clock-parents = <&clk IMX8MP_AUDIO_PLL2_OUT>;
assigned-clock-rates = <13000000>, <13000000>, <156000000>;
- reset-gpios = <&gpio3 21 GPIO_ACTIVE_HIGH>;
+ reset-gpios = <&gpio4 1 GPIO_ACTIVE_HIGH>;
status = "disabled";
ports {
@@ -420,6 +420,18 @@
reg = <0x53>;
};
+ eeprom0wl: eeprom@58 {
+ compatible = "atmel,24c32d-wl"; /* M24C32-D WL page of 0x50 */
+ pagesize = <32>;
+ reg = <0x58>;
+ };
+
+ eeprom1wl: eeprom@5b {
+ compatible = "atmel,24c32d-wl"; /* M24C32-D WL page of 0x53 */
+ pagesize = <32>;
+ reg = <0x5b>;
+ };
+
ioexp: gpio@74 {
compatible = "nxp,pca9539";
reg = <0x74>;
diff --git a/dts/upstream/src/arm64/freescale/imx8mp-evk.dts b/dts/upstream/src/arm64/freescale/imx8mp-evk.dts
index cc9d468..f87fa5a 100644
--- a/dts/upstream/src/arm64/freescale/imx8mp-evk.dts
+++ b/dts/upstream/src/arm64/freescale/imx8mp-evk.dts
@@ -137,6 +137,28 @@
};
};
+
+ reserved-memory {
+ #address-cells = <2>;
+ #size-cells = <2>;
+ ranges;
+
+ dsp_vdev0vring0: vdev0vring0@942f0000 {
+ reg = <0 0x942f0000 0 0x8000>;
+ no-map;
+ };
+
+ dsp_vdev0vring1: vdev0vring1@942f8000 {
+ reg = <0 0x942f8000 0 0x8000>;
+ no-map;
+ };
+
+ dsp_vdev0buffer: vdev0buffer@94300000 {
+ compatible = "shared-dma-pool";
+ reg = <0 0x94300000 0 0x100000>;
+ no-map;
+ };
+ };
};
&flexspi {
diff --git a/dts/upstream/src/arm64/freescale/imx8mp-msc-sm2s-ep1.dts b/dts/upstream/src/arm64/freescale/imx8mp-msc-sm2s-ep1.dts
index e4215c8..da4b180 100644
--- a/dts/upstream/src/arm64/freescale/imx8mp-msc-sm2s-ep1.dts
+++ b/dts/upstream/src/arm64/freescale/imx8mp-msc-sm2s-ep1.dts
@@ -57,8 +57,8 @@
clocks = <&clk IMX8MP_CLK_CLKOUT1>;
#sound-dai-cells = <0>;
- VDDA-supply = <®_vcc_3v3_audio>;
- VDDD-supply = <®_vcc_1v8_audio>;
+ VDDA-supply = <®_vcc_3v3_audio>;
+ VDDD-supply = <®_vcc_1v8_audio>;
VDDIO-supply = <®_vcc_1v8_audio>;
};
};
diff --git a/dts/upstream/src/arm64/freescale/imx8mp-skov-reva.dtsi b/dts/upstream/src/arm64/freescale/imx8mp-skov-reva.dtsi
new file mode 100644
index 0000000..59813ef
--- /dev/null
+++ b/dts/upstream/src/arm64/freescale/imx8mp-skov-reva.dtsi
@@ -0,0 +1,711 @@
+// SPDX-License-Identifier: (GPL-2.0 OR MIT)
+
+#include "imx8mp.dtsi"
+
+#include <dt-bindings/leds/common.h>
+
+/ {
+ aliases {
+ /* some of this aliases like backlight0, ethernetX and switch0
+ * are needed for the bootloader.
+ */
+ backlight0 = &backlight;
+ ethernet0 = &eqos;
+ ethernet1 = &lan1;
+ ethernet2 = &lan2;
+ rtc0 = &i2c_rtc;
+ rtc1 = &snvs_rtc;
+ switch0 = &switch;
+ };
+
+ /*
+ * Backlight is present only on some of boards, so it is disabled by
+ * default.
+ */
+ backlight: backlight {
+ compatible = "pwm-backlight";
+ pinctrl-0 = <&pinctrl_backlight>;
+ pwms = <&pwm1 0 20000 0>;
+ power-supply = <®_24v>;
+ enable-gpios = <&gpio4 24 GPIO_ACTIVE_HIGH>;
+ brightness-levels = <0 255>;
+ num-interpolated-steps = <17>;
+ default-brightness-level = <8>;
+ status = "disabled";
+ };
+
+ leds {
+ compatible = "gpio-leds";
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_gpio_led>;
+
+ led-0 {
+ label = "D1";
+ color = <LED_COLOR_ID_GREEN>;
+ gpios = <&gpio1 5 GPIO_ACTIVE_HIGH>;
+ function = LED_FUNCTION_STATUS;
+ default-state = "on";
+ linux,default-trigger = "heartbeat";
+ };
+
+ led-1 {
+ label = "D2";
+ color = <LED_COLOR_ID_GREEN>;
+ gpios = <&gpio1 6 GPIO_ACTIVE_HIGH>;
+ default-state = "off";
+ };
+
+ led-2 {
+ label = "D3";
+ color = <LED_COLOR_ID_GREEN>;
+ gpios = <&gpio1 7 GPIO_ACTIVE_HIGH>;
+ default-state = "on";
+ };
+ };
+
+ reg_1v2: regulator-1v2 {
+ compatible = "regulator-fixed";
+ vin-supply = <®_5v_p>;
+ regulator-name = "1V2";
+ regulator-min-microvolt = <1200000>;
+ regulator-max-microvolt = <1200000>;
+ };
+
+ reg_2v5: regulator-2v5 {
+ compatible = "regulator-fixed";
+ vin-supply = <®_5v_s>;
+ regulator-name = "2V5";
+ regulator-min-microvolt = <2500000>;
+ regulator-max-microvolt = <2500000>;
+ };
+
+ reg_3v3: regulator-3v3 {
+ compatible = "regulator-fixed";
+ vin-supply = <®_5v_s>;
+ regulator-name = "3V3";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ };
+
+ /*
+ * This regulator will provide power as long as possible even if
+ * undervoltage is detected.
+ */
+ reg_5v_p: regulator-5v-p {
+ compatible = "regulator-fixed";
+ regulator-name = "5V_P";
+ vin-supply = <®_24v>;
+ regulator-min-microvolt = <5000000>;
+ regulator-max-microvolt = <5000000>;
+ };
+
+ /*
+ * This regulator will be automatically shutdown if undervoltage is
+ * detected.
+ */
+ reg_5v_s: regulator-5v-s {
+ compatible = "regulator-fixed";
+ regulator-name = "5V_S";
+ vin-supply = <®_24v>;
+ regulator-min-microvolt = <5000000>;
+ regulator-max-microvolt = <5000000>;
+ };
+
+ reg_24v: regulator-24v {
+ compatible = "regulator-fixed";
+ regulator-name = "24V";
+ regulator-min-microvolt = <24000000>;
+ regulator-max-microvolt = <24000000>;
+ };
+
+ reg_can2rs: regulator-can2rs {
+ compatible = "regulator-fixed";
+ regulator-name = "CAN2RS";
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_can2rs>;
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ gpio = <&gpio4 22 GPIO_ACTIVE_LOW>;
+ };
+
+ reg_canrs: regulator-canrs {
+ compatible = "regulator-fixed";
+ regulator-name = "CANRS";
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_canrs>;
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ gpio = <&gpio4 21 GPIO_ACTIVE_LOW>;
+ };
+
+ reg_tft_vcom: regulator-tft-vcom {
+ compatible = "pwm-regulator";
+ pwms = <&pwm4 0 20000 0>;
+ regulator-name = "VCOM";
+ vin-supply = <®_5v_s>;
+ regulator-min-microvolt = <3600000>;
+ regulator-max-microvolt = <3600000>;
+ regulator-always-on;
+ voltage-table = <3600000 26>;
+ status = "disabled";
+ };
+
+ reg_vsd_3v3: regulator-vsd-3v3 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_reg_vsd_3v3>;
+ vin-supply = <®_vdd_3v3>;
+ compatible = "regulator-fixed";
+ regulator-name = "VSD_3V3";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ gpio = <&gpio2 19 GPIO_ACTIVE_HIGH>;
+ enable-active-high;
+ };
+};
+
+&A53_0 {
+ cpu-supply = <®_vdd_arm>;
+};
+
+&A53_1 {
+ cpu-supply = <®_vdd_arm>;
+};
+
+&A53_2 {
+ cpu-supply = <®_vdd_arm>;
+};
+
+&A53_3 {
+ cpu-supply = <®_vdd_arm>;
+};
+
+&ecspi2 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_ecspi2>;
+ cs-gpios = <&gpio5 13 GPIO_ACTIVE_LOW>;
+ status = "okay";
+
+ adc: adc@0 {
+ compatible = "microchip,mcp3002";
+ reg = <0>;
+ vref-supply = <®_vdd_3v3>;
+ spi-max-frequency = <1000000>;
+ #io-channel-cells = <1>;
+ };
+};
+
+&eqos {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_eqos>;
+ phy-mode = "rgmii-txid";
+ status = "okay";
+
+ fixed-link {
+ speed = <1000>;
+ full-duplex;
+ };
+};
+
+&flexcan1 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_flexcan1>;
+ xceiver-supply = <®_canrs>;
+ status = "okay";
+};
+
+&flexcan2 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_flexcan2>;
+ xceiver-supply = <®_can2rs>;
+ status = "okay";
+};
+
+&i2c1 {
+ clock-frequency = <100000>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_i2c1>;
+ status = "okay";
+
+ pmic@25 {
+ compatible = "nxp,pca9450c";
+ reg = <0x25>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_pmic>;
+ interrupts-extended = <&gpio1 3 IRQ_TYPE_EDGE_RISING>;
+ sd-vsel-gpios = <&gpio1 4 GPIO_ACTIVE_HIGH>;
+
+ regulators {
+ reg_vdd_soc: BUCK1 {
+ regulator-name = "VDD_SOC";
+ regulator-min-microvolt = <600000>;
+ regulator-max-microvolt = <2187500>;
+ vin-supply = <®_5v_p>;
+ regulator-boot-on;
+ regulator-always-on;
+ regulator-ramp-delay = <3125>;
+ };
+
+ reg_vdd_arm: BUCK2 {
+ regulator-name = "VDD_ARM";
+ regulator-min-microvolt = <600000>;
+ regulator-max-microvolt = <2187500>;
+ vin-supply = <®_5v_p>;
+ regulator-boot-on;
+ regulator-always-on;
+ regulator-ramp-delay = <3125>;
+ nxp,dvs-run-voltage = <950000>;
+ nxp,dvs-standby-voltage = <850000>;
+ };
+
+ reg_vdd_3v3: BUCK4 {
+ regulator-name = "VDD_3V3";
+ regulator-min-microvolt = <600000>;
+ regulator-max-microvolt = <3400000>;
+ vin-supply = <®_5v_p>;
+ regulator-boot-on;
+ regulator-always-on;
+ };
+
+ reg_vdd_1v8: BUCK5 {
+ regulator-name = "VDD_1V8";
+ regulator-min-microvolt = <600000>;
+ regulator-max-microvolt = <3400000>;
+ vin-supply = <®_5v_p>;
+ regulator-boot-on;
+ regulator-always-on;
+ };
+
+ reg_nvcc_dram_1v1: BUCK6 {
+ regulator-name = "NVCC_DRAM_1V1";
+ regulator-min-microvolt = <600000>;
+ regulator-max-microvolt = <3400000>;
+ vin-supply = <®_5v_p>;
+ regulator-boot-on;
+ regulator-always-on;
+ };
+
+ reg_nvcc_snvs_1v8: LDO1 {
+ regulator-name = "NVCC_SNVS_1V8";
+ regulator-min-microvolt = <1600000>;
+ regulator-max-microvolt = <3300000>;
+ vin-supply = <®_5v_p>;
+ regulator-boot-on;
+ regulator-always-on;
+ };
+
+ reg_vdda_1v8: LDO3 {
+ regulator-name = "VDDA_1V8";
+ regulator-min-microvolt = <800000>;
+ regulator-max-microvolt = <3300000>;
+ vin-supply = <®_5v_p>;
+ regulator-boot-on;
+ regulator-always-on;
+ };
+
+ reg_nvcc_sd2: LDO5 {
+ regulator-name = "NVCC_SD2";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <3300000>;
+ vin-supply = <®_5v_p>;
+ regulator-boot-on;
+ regulator-always-on;
+ };
+ };
+ };
+};
+
+&i2c3 {
+ clock-frequency = <100000>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_i2c3>;
+ status = "okay";
+
+ i2c_rtc: rtc@51 {
+ compatible = "nxp,pcf85063tp";
+ reg = <0x51>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_rtc>;
+ interrupts-extended = <&gpio4 31 IRQ_TYPE_EDGE_FALLING>;
+ quartz-load-femtofarads = <12500>;
+ };
+};
+
+&i2c4 {
+ clock-frequency = <380000>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_i2c4>;
+ status = "okay";
+
+ switch: switch@5f {
+ compatible = "microchip,ksz9893";
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_switch>;
+ reset-gpios = <&gpio5 1 GPIO_ACTIVE_LOW>;
+ reg = <0x5f>;
+
+ ethernet-ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ lan1: port@0 {
+ reg = <0>;
+ phy-mode = "internal";
+ label = "lan1";
+ };
+
+ lan2: port@1 {
+ reg = <1>;
+ phy-mode = "internal";
+ label = "lan2";
+ };
+
+ port@2 {
+ reg = <2>;
+ label = "cpu";
+ ethernet = <&eqos>;
+ phy-mode = "rgmii";
+ /* 2ns RX delay is implemented on PCB */
+ tx-internal-delay-ps = <2000>;
+ rx-internal-delay-ps = <0>;
+
+ fixed-link {
+ speed = <1000>;
+ full-duplex;
+ };
+ };
+ };
+ };
+};
+
+&pwm1 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_pwm1>;
+};
+
+&pwm4 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_pwm4>;
+};
+
+&uart1 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_uart1>;
+ status = "okay";
+};
+
+&uart2 {
+ /* console */
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_uart2>;
+ status = "okay";
+};
+
+&usb3_0 {
+ status = "okay";
+};
+
+&usb3_1 {
+ status = "okay";
+};
+
+&usb3_phy0 {
+ vbus-supply = <®_3v3>;
+ status = "okay";
+};
+
+&usb3_phy1 {
+ vbus-supply = <®_3v3>;
+ status = "okay";
+};
+
+&usb_dwc3_0 {
+ dr_mode = "host";
+};
+
+&usb_dwc3_1 {
+ dr_mode = "host";
+};
+
+/* SD Card */
+&usdhc2 {
+ pinctrl-names = "default", "state_100mhz", "state_200mhz";
+ pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>;
+ pinctrl-1 = <&pinctrl_usdhc2_100mhz>, <&pinctrl_usdhc2_gpio>;
+ pinctrl-2 = <&pinctrl_usdhc2_200mhz>, <&pinctrl_usdhc2_gpio>;
+ vmmc-supply = <®_vsd_3v3>;
+ vqmmc-supply = <®_nvcc_sd2>;
+ cd-gpios = <&gpio2 12 GPIO_ACTIVE_LOW>;
+ wp-gpios = <&gpio2 20 GPIO_ACTIVE_HIGH>;
+ bus-width = <4>;
+ status = "okay";
+};
+
+/* eMMC */
+&usdhc3 {
+ assigned-clocks = <&clk IMX8MP_CLK_USDHC3>;
+ assigned-clock-rates = <400000000>;
+ pinctrl-names = "default", "state_100mhz", "state_200mhz";
+ pinctrl-0 = <&pinctrl_usdhc3>;
+ pinctrl-1 = <&pinctrl_usdhc3_100mhz>;
+ pinctrl-2 = <&pinctrl_usdhc3_200mhz>;
+ vmmc-supply = <®_vdd_3v3>;
+ vqmmc-supply = <®_vdd_1v8>;
+ bus-width = <8>;
+ no-sd;
+ no-sdio;
+ non-removable;
+ status = "okay";
+};
+
+&wdog1 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_wdog>;
+ fsl,ext-reset-output;
+ status = "okay";
+};
+
+&iomuxc {
+ pinctrl_backlight: backlightgrp {
+ fsl,pins = <
+ MX8MP_IOMUXC_SAI2_TXFS__GPIO4_IO24 0x0100
+ >;
+ };
+
+ pinctrl_can2rs: can2rsgrp {
+ fsl,pins = <
+ MX8MP_IOMUXC_SAI2_RXC__GPIO4_IO22 0x154
+ >;
+ };
+
+ pinctrl_canrs: canrsgrp {
+ fsl,pins = <
+ MX8MP_IOMUXC_SAI2_RXFS__GPIO4_IO21 0x154
+ >;
+ };
+
+ pinctrl_ecspi2: ecspi2grp {
+ fsl,pins = <
+ MX8MP_IOMUXC_ECSPI2_SCLK__ECSPI2_SCLK 0x44
+ MX8MP_IOMUXC_ECSPI2_MOSI__ECSPI2_MOSI 0x44
+ MX8MP_IOMUXC_ECSPI2_MISO__ECSPI2_MISO 0x44
+ MX8MP_IOMUXC_ECSPI2_SS0__GPIO5_IO13 0x40
+ >;
+ };
+
+ pinctrl_eqos: eqosgrp {
+ fsl,pins = <
+ MX8MP_IOMUXC_ENET_RD0__ENET_QOS_RGMII_RD0 0x91
+ MX8MP_IOMUXC_ENET_RD1__ENET_QOS_RGMII_RD1 0x91
+ MX8MP_IOMUXC_ENET_RD2__ENET_QOS_RGMII_RD2 0x91
+ MX8MP_IOMUXC_ENET_RD3__ENET_QOS_RGMII_RD3 0x91
+ MX8MP_IOMUXC_ENET_RXC__CCM_ENET_QOS_CLOCK_GENERATE_RX_CLK 0x91
+ MX8MP_IOMUXC_ENET_RX_CTL__ENET_QOS_RGMII_RX_CTL 0x91
+ MX8MP_IOMUXC_ENET_TD0__ENET_QOS_RGMII_TD0 0x1f
+ MX8MP_IOMUXC_ENET_TD1__ENET_QOS_RGMII_TD1 0x1f
+ MX8MP_IOMUXC_ENET_TD2__ENET_QOS_RGMII_TD2 0x1f
+ MX8MP_IOMUXC_ENET_TD3__ENET_QOS_RGMII_TD3 0x1f
+ MX8MP_IOMUXC_ENET_TX_CTL__ENET_QOS_RGMII_TX_CTL 0x1f
+ MX8MP_IOMUXC_ENET_TXC__CCM_ENET_QOS_CLOCK_GENERATE_TX_CLK 0x1f
+ >;
+ };
+
+ pinctrl_flexcan1: flexcan1grp {
+ fsl,pins = <
+ MX8MP_IOMUXC_SPDIF_RX__CAN1_RX 0x154
+ MX8MP_IOMUXC_SPDIF_TX__CAN1_TX 0x154
+ >;
+ };
+
+ pinctrl_flexcan2: flexcan2grp {
+ fsl,pins = <
+ MX8MP_IOMUXC_SAI2_MCLK__CAN2_RX 0x154
+ MX8MP_IOMUXC_SAI2_TXD0__CAN2_TX 0x154
+ >;
+ };
+
+ pinctrl_gpio_led: gpioledgrp {
+ fsl,pins = <
+ MX8MP_IOMUXC_GPIO1_IO05__GPIO1_IO05 0x19
+ MX8MP_IOMUXC_GPIO1_IO06__GPIO1_IO06 0x19
+ MX8MP_IOMUXC_GPIO1_IO07__GPIO1_IO07 0x19
+ >;
+ };
+
+ pinctrl_i2c1: i2c1grp {
+ fsl,pins = <
+ MX8MP_IOMUXC_I2C1_SCL__I2C1_SCL 0x400001c2
+ MX8MP_IOMUXC_I2C1_SDA__I2C1_SDA 0x400001c2
+ >;
+ };
+
+ pinctrl_i2c3: i2c3grp {
+ fsl,pins = <
+ MX8MP_IOMUXC_I2C3_SCL__I2C3_SCL 0x400001c2
+ MX8MP_IOMUXC_I2C3_SDA__I2C3_SDA 0x400001c2
+ >;
+ };
+
+ pinctrl_i2c4: i2c4grp {
+ fsl,pins = <
+ MX8MP_IOMUXC_I2C4_SCL__I2C4_SCL 0x400001c3
+ MX8MP_IOMUXC_I2C4_SDA__I2C4_SDA 0x400001c3
+ >;
+ };
+
+ pinctrl_pmic: pmicirqgrp {
+ fsl,pins = <
+ MX8MP_IOMUXC_GPIO1_IO03__GPIO1_IO03 0x41
+ MX8MP_IOMUXC_GPIO1_IO04__GPIO1_IO04 0x41
+ >;
+ };
+
+ pinctrl_pwm1: pwm1grp {
+ fsl,pins = <
+ MX8MP_IOMUXC_SPDIF_EXT_CLK__PWM1_OUT 0x116
+ >;
+ };
+
+ pinctrl_pwm4: pwm4grp {
+ fsl,pins = <
+ MX8MP_IOMUXC_SAI3_MCLK__PWM4_OUT 0x116
+ >;
+ };
+
+ pinctrl_reg_vsd_3v3: regvsd3v3grp {
+ fsl,pins = <
+ MX8MP_IOMUXC_SD2_RESET_B__GPIO2_IO19 0x40
+ >;
+ };
+
+ pinctrl_rtc: rtcgrp {
+ fsl,pins = <
+ MX8MP_IOMUXC_SAI3_TXFS__GPIO4_IO31 0x41
+ >;
+ };
+
+ pinctrl_switch: switchgrp {
+ fsl,pins = <
+ MX8MP_IOMUXC_SAI3_TXC__GPIO5_IO00 0x41
+ MX8MP_IOMUXC_SAI3_TXD__GPIO5_IO01 0x41
+ >;
+ };
+
+ pinctrl_touchscreen: touchscreengrp {
+ fsl,pins = <
+ /* external 10 k pull up */
+ /* CTP_INT */
+ MX8MP_IOMUXC_SAI3_RXFS__GPIO4_IO28 0x41
+ /* CTP_RST */
+ MX8MP_IOMUXC_SAI3_RXC__GPIO4_IO29 0x41
+ >;
+ };
+
+ pinctrl_uart1: uart1grp {
+ fsl,pins = <
+ MX8MP_IOMUXC_UART1_RXD__UART1_DCE_RX 0x140
+ MX8MP_IOMUXC_UART1_TXD__UART1_DCE_TX 0x140
+ MX8MP_IOMUXC_UART3_RXD__UART1_DTE_RTS 0x140
+ >;
+ };
+
+ pinctrl_uart2: uart2grp {
+ fsl,pins = <
+ MX8MP_IOMUXC_UART2_RXD__UART2_DCE_RX 0x14f
+ MX8MP_IOMUXC_UART2_TXD__UART2_DCE_TX 0x14f
+ >;
+ };
+
+ pinctrl_usdhc2: usdhc2grp {
+ fsl,pins = <
+ MX8MP_IOMUXC_SD2_CLK__USDHC2_CLK 0x190
+ MX8MP_IOMUXC_SD2_CMD__USDHC2_CMD 0x1d0
+ MX8MP_IOMUXC_SD2_DATA0__USDHC2_DATA0 0x1d0
+ MX8MP_IOMUXC_SD2_DATA1__USDHC2_DATA1 0x1d0
+ MX8MP_IOMUXC_SD2_DATA2__USDHC2_DATA2 0x1d0
+ MX8MP_IOMUXC_SD2_DATA3__USDHC2_DATA3 0x1d0
+ >;
+ };
+
+ pinctrl_usdhc2_100mhz: usdhc2-100mhzgrp {
+ fsl,pins = <
+ MX8MP_IOMUXC_SD2_CLK__USDHC2_CLK 0x194
+ MX8MP_IOMUXC_SD2_CMD__USDHC2_CMD 0x1d4
+ MX8MP_IOMUXC_SD2_DATA0__USDHC2_DATA0 0x1d4
+ MX8MP_IOMUXC_SD2_DATA1__USDHC2_DATA1 0x1d4
+ MX8MP_IOMUXC_SD2_DATA2__USDHC2_DATA2 0x1d4
+ MX8MP_IOMUXC_SD2_DATA3__USDHC2_DATA3 0x1d4
+ >;
+ };
+
+ pinctrl_usdhc2_200mhz: usdhc2-200mhzgrp {
+ fsl,pins = <
+ MX8MP_IOMUXC_SD2_CLK__USDHC2_CLK 0x196
+ MX8MP_IOMUXC_SD2_CMD__USDHC2_CMD 0x1d6
+ MX8MP_IOMUXC_SD2_DATA0__USDHC2_DATA0 0x1d6
+ MX8MP_IOMUXC_SD2_DATA1__USDHC2_DATA1 0x1d6
+ MX8MP_IOMUXC_SD2_DATA2__USDHC2_DATA2 0x1d6
+ MX8MP_IOMUXC_SD2_DATA3__USDHC2_DATA3 0x1d6
+ >;
+ };
+
+ pinctrl_usdhc2_gpio: usdhc2gpiogrp {
+ fsl,pins = <
+ MX8MP_IOMUXC_SD2_CD_B__GPIO2_IO12 0x1c4
+ MX8MP_IOMUXC_SD2_WP__GPIO2_IO20 0x1c4
+ >;
+ };
+
+ pinctrl_usdhc3: usdhc3grp {
+ fsl,pins = <
+ MX8MP_IOMUXC_NAND_WE_B__USDHC3_CLK 0x190
+ MX8MP_IOMUXC_NAND_WP_B__USDHC3_CMD 0x1d0
+ MX8MP_IOMUXC_NAND_DATA04__USDHC3_DATA0 0x1d0
+ MX8MP_IOMUXC_NAND_DATA05__USDHC3_DATA1 0x1d0
+ MX8MP_IOMUXC_NAND_DATA06__USDHC3_DATA2 0x1d0
+ MX8MP_IOMUXC_NAND_DATA07__USDHC3_DATA3 0x1d0
+ MX8MP_IOMUXC_NAND_RE_B__USDHC3_DATA4 0x1d0
+ MX8MP_IOMUXC_NAND_CE2_B__USDHC3_DATA5 0x1d0
+ MX8MP_IOMUXC_NAND_CE3_B__USDHC3_DATA6 0x1d0
+ MX8MP_IOMUXC_NAND_CLE__USDHC3_DATA7 0x1d0
+ MX8MP_IOMUXC_NAND_CE1_B__USDHC3_STROBE 0x190
+ >;
+ };
+
+ pinctrl_usdhc3_100mhz: usdhc3-100mhzgrp {
+ fsl,pins = <
+ MX8MP_IOMUXC_NAND_WE_B__USDHC3_CLK 0x194
+ MX8MP_IOMUXC_NAND_WP_B__USDHC3_CMD 0x1d4
+ MX8MP_IOMUXC_NAND_DATA04__USDHC3_DATA0 0x1d4
+ MX8MP_IOMUXC_NAND_DATA05__USDHC3_DATA1 0x1d4
+ MX8MP_IOMUXC_NAND_DATA06__USDHC3_DATA2 0x1d4
+ MX8MP_IOMUXC_NAND_DATA07__USDHC3_DATA3 0x1d4
+ MX8MP_IOMUXC_NAND_RE_B__USDHC3_DATA4 0x1d4
+ MX8MP_IOMUXC_NAND_CE2_B__USDHC3_DATA5 0x1d4
+ MX8MP_IOMUXC_NAND_CE3_B__USDHC3_DATA6 0x1d4
+ MX8MP_IOMUXC_NAND_CLE__USDHC3_DATA7 0x1d4
+ MX8MP_IOMUXC_NAND_CE1_B__USDHC3_STROBE 0x194
+ >;
+ };
+
+ pinctrl_usdhc3_200mhz: usdhc3-200mhzgrp {
+ fsl,pins = <
+ MX8MP_IOMUXC_NAND_WE_B__USDHC3_CLK 0x196
+ MX8MP_IOMUXC_NAND_WP_B__USDHC3_CMD 0x1d6
+ MX8MP_IOMUXC_NAND_DATA04__USDHC3_DATA0 0x1d6
+ MX8MP_IOMUXC_NAND_DATA05__USDHC3_DATA1 0x1d6
+ MX8MP_IOMUXC_NAND_DATA06__USDHC3_DATA2 0x1d6
+ MX8MP_IOMUXC_NAND_DATA07__USDHC3_DATA3 0x1d6
+ MX8MP_IOMUXC_NAND_RE_B__USDHC3_DATA4 0x1d6
+ MX8MP_IOMUXC_NAND_CE2_B__USDHC3_DATA5 0x1d6
+ MX8MP_IOMUXC_NAND_CE3_B__USDHC3_DATA6 0x1d6
+ MX8MP_IOMUXC_NAND_CLE__USDHC3_DATA7 0x1d6
+ MX8MP_IOMUXC_NAND_CE1_B__USDHC3_STROBE 0x196
+ >;
+ };
+
+ pinctrl_wdog: wdoggrp {
+ fsl,pins = <
+ MX8MP_IOMUXC_GPIO1_IO02__WDOG1_WDOG_B 0xc6
+ >;
+ };
+};
diff --git a/dts/upstream/src/arm64/freescale/imx8mp-skov-revb-hdmi.dts b/dts/upstream/src/arm64/freescale/imx8mp-skov-revb-hdmi.dts
new file mode 100644
index 0000000..c1ca69d
--- /dev/null
+++ b/dts/upstream/src/arm64/freescale/imx8mp-skov-revb-hdmi.dts
@@ -0,0 +1,20 @@
+// SPDX-License-Identifier: (GPL-2.0 OR MIT)
+
+/dts-v1/;
+
+#include "imx8mp-skov-reva.dtsi"
+
+/ {
+ model = "SKOV IMX8MP CPU revB - HDMI";
+ compatible = "skov,imx8mp-skov-revb-hdmi", "fsl,imx8mp";
+};
+
+&iomuxc {
+ pinctrl_hdmi: hdmigrp {
+ fsl,pins = <
+ MX8MP_IOMUXC_HDMI_DDC_SCL__HDMIMIX_HDMI_SCL 0x1c3
+ MX8MP_IOMUXC_HDMI_DDC_SDA__HDMIMIX_HDMI_SDA 0x1c3
+ MX8MP_IOMUXC_HDMI_HPD__HDMIMIX_HDMI_HPD 0x19
+ >;
+ };
+};
diff --git a/dts/upstream/src/arm64/freescale/imx8mp-skov-revb-lt6.dts b/dts/upstream/src/arm64/freescale/imx8mp-skov-revb-lt6.dts
new file mode 100644
index 0000000..ccbd3ab
--- /dev/null
+++ b/dts/upstream/src/arm64/freescale/imx8mp-skov-revb-lt6.dts
@@ -0,0 +1,101 @@
+// SPDX-License-Identifier: (GPL-2.0 OR MIT)
+
+/dts-v1/;
+
+#include "imx8mp-skov-reva.dtsi"
+
+/ {
+ model = "SKOV IMX8MP CPU revB - LT6";
+ compatible = "skov,imx8mp-skov-revb-lt6", "fsl,imx8mp";
+
+ touchscreen {
+ compatible = "resistive-adc-touch";
+ io-channels = <&adc_ts 1>, <&adc_ts 3>, <&adc_ts 4>, <&adc_ts 5>;
+ io-channel-names = "y", "z1", "z2", "x";
+ touchscreen-min-pressure = <65000>;
+ touchscreen-inverted-y;
+ touchscreen-swapped-x-y;
+ touchscreen-x-plate-ohms = <300>;
+ };
+};
+
+®_tft_vcom {
+ regulator-min-microvolt = <3600000>;
+ regulator-max-microvolt = <3600000>;
+ voltage-table = <3600000 26>;
+ status = "okay";
+};
+
+&pwm4 {
+ status = "okay";
+};
+
+&backlight {
+ status = "okay";
+};
+
+&ecspi1 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_ecspi1>;
+ cs-gpios = <&gpio5 9 GPIO_ACTIVE_LOW>;
+ status = "okay";
+
+ adc_ts: adc@0 {
+ compatible = "ti,tsc2046e-adc";
+ reg = <0>;
+ pinctrl-0 = <&pinctrl_touch>;
+ pinctrl-names ="default";
+ spi-max-frequency = <1000000>;
+ interrupts-extended = <&gpio4 25 IRQ_TYPE_LEVEL_LOW>;
+ #io-channel-cells = <1>;
+
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ channel@1 {
+ reg = <1>;
+ settling-time-us = <700>;
+ oversampling-ratio = <5>;
+ };
+
+ channel@3 {
+ reg = <3>;
+ settling-time-us = <700>;
+ oversampling-ratio = <5>;
+ };
+
+ channel@4 {
+ reg = <4>;
+ settling-time-us = <700>;
+ oversampling-ratio = <5>;
+ };
+
+ channel@5 {
+ reg = <5>;
+ settling-time-us = <700>;
+ oversampling-ratio = <5>;
+ };
+ };
+};
+
+&pwm1 {
+ status = "okay";
+};
+
+&iomuxc {
+ pinctrl_ecspi1: ecspi1grp {
+ fsl,pins = <
+ MX8MP_IOMUXC_ECSPI1_SCLK__ECSPI1_SCLK 0x44
+ MX8MP_IOMUXC_ECSPI1_MOSI__ECSPI1_MOSI 0x44
+ MX8MP_IOMUXC_ECSPI1_MISO__ECSPI1_MISO 0x44
+ MX8MP_IOMUXC_ECSPI1_SS0__GPIO5_IO09 0x40
+ >;
+ };
+
+ pinctrl_touch: touchgrp {
+ fsl,pins = <
+ /* external pull up */
+ MX8MP_IOMUXC_SAI2_TXC__GPIO4_IO25 0x40
+ >;
+ };
+};
diff --git a/dts/upstream/src/arm64/freescale/imx8mp-skov-revb-mi1010ait-1cp1.dts b/dts/upstream/src/arm64/freescale/imx8mp-skov-revb-mi1010ait-1cp1.dts
new file mode 100644
index 0000000..3c2efdc
--- /dev/null
+++ b/dts/upstream/src/arm64/freescale/imx8mp-skov-revb-mi1010ait-1cp1.dts
@@ -0,0 +1,100 @@
+// SPDX-License-Identifier: (GPL-2.0 OR MIT)
+
+/dts-v1/;
+
+#include "imx8mp-skov-reva.dtsi"
+
+/ {
+ model = "SKOV IMX8MP CPU revB - MI1010AIT-1CP1";
+ compatible = "skov,imx8mp-skov-revb-mi1010ait-1cp1", "fsl,imx8mp";
+
+ panel {
+ compatible = "multi-inno,mi1010ait-1cp";
+ backlight = <&backlight>;
+ power-supply = <®_tft_vcom>;
+
+ port {
+ in_lvds0: endpoint {
+ remote-endpoint = <&ldb_lvds_ch0>;
+ };
+ };
+ };
+};
+
+&backlight {
+ status = "okay";
+};
+
+&i2c2 {
+ clock-frequency = <100000>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_i2c2>;
+ status = "okay";
+
+ touchscreen@38 {
+ compatible = "edt,edt-ft5406";
+ reg = <0x38>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_touchscreen>;
+ interrupts-extended = <&gpio4 28 IRQ_TYPE_EDGE_FALLING>;
+ reset-gpios = <&gpio4 29 GPIO_ACTIVE_LOW>;
+ touchscreen-size-x = <1280>;
+ touchscreen-size-y = <800>;
+ vcc-supply = <®_vdd_3v3>;
+ iovcc-supply = <®_vdd_3v3>;
+ wakeup-source;
+ };
+};
+
+&lcdif2 {
+ status = "okay";
+};
+
+&lvds_bridge {
+ /* IMX8MP_CLK_MEDIA_LDB = IMX8MP_CLK_MEDIA_DISP2_PIX * 7 */
+ assigned-clock-rates = <482300000>;
+ status = "okay";
+
+ ports {
+ port@1 {
+ ldb_lvds_ch0: endpoint {
+ remote-endpoint = <&in_lvds0>;
+ };
+ };
+ };
+};
+
+&media_blk_ctrl {
+ /* currently it is not possible to let display clocks confugure
+ * automatically, so we need to set them manually
+ */
+ assigned-clock-rates = <500000000>, <200000000>, <0>,
+ /* IMX8MP_CLK_MEDIA_DISP2_PIX = pixelclk of lvds panel */
+ <68900000>,
+ /* IMX8MP_VIDEO_PLL1 = IMX8MP_CLK_MEDIA_LDB * 2 */
+ <964600000>;
+};
+
+&pwm4 {
+ status = "okay";
+};
+
+&pwm1 {
+ status = "okay";
+};
+
+®_tft_vcom {
+ regulator-min-microvolt = <3160000>;
+ regulator-max-microvolt = <3160000>;
+ voltage-table = <3160000 73>;
+ status = "okay";
+};
+
+&iomuxc {
+ pinctrl_i2c2: i2c2grp {
+ fsl,pins = <
+ MX8MP_IOMUXC_I2C2_SCL__I2C2_SCL 0x400001c2
+ MX8MP_IOMUXC_I2C2_SDA__I2C2_SDA 0x400001c2
+ >;
+ };
+};
diff --git a/dts/upstream/src/arm64/freescale/imx8mp-tqma8mpql-mba8mpxl-lvds-g133han01.dtso b/dts/upstream/src/arm64/freescale/imx8mp-tqma8mpql-mba8mpxl-lvds-g133han01.dtso
new file mode 100644
index 0000000..5058cd9
--- /dev/null
+++ b/dts/upstream/src/arm64/freescale/imx8mp-tqma8mpql-mba8mpxl-lvds-g133han01.dtso
@@ -0,0 +1,77 @@
+// SPDX-License-Identifier: (GPL-2.0-or-later OR MIT)
+/*
+ * Copyright (c) 2023 TQ-Systems GmbH <linux@ew.tq-group.com>,
+ * D-82229 Seefeld, Germany.
+ * Author: Alexander Stein
+ */
+
+/dts-v1/;
+/plugin/;
+
+#include <dt-bindings/clock/imx8mp-clock.h>
+
+&{/} {
+ compatible = "tq,imx8mp-tqma8mpql-mba8mpxl", "tq,imx8mp-tqma8mpql", "fsl,imx8mp";
+};
+
+&backlight_lvds {
+ status = "okay";
+};
+
+&display {
+ compatible = "auo,g133han01";
+ status = "okay";
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+ dual-lvds-odd-pixels;
+
+ panel_in_lvds0: endpoint {
+ remote-endpoint = <&ldb_lvds_ch0>;
+ };
+ };
+
+ port@1 {
+ reg = <1>;
+ dual-lvds-even-pixels;
+
+ panel_in_lvds1: endpoint {
+ remote-endpoint = <&ldb_lvds_ch1>;
+ };
+ };
+ };
+};
+
+&lcdif2 {
+ status = "okay";
+};
+
+&lvds_bridge {
+ assigned-clocks = <&clk IMX8MP_CLK_MEDIA_LDB>,
+ <&clk IMX8MP_VIDEO_PLL1>;
+ assigned-clock-parents = <&clk IMX8MP_VIDEO_PLL1_OUT>;
+ assigned-clock-rates = <0>, <988400000>;
+ status = "okay";
+
+ ports {
+ port@1 {
+ ldb_lvds_ch0: endpoint {
+ remote-endpoint = <&panel_in_lvds0>;
+ };
+ };
+
+ port@2 {
+ ldb_lvds_ch1: endpoint {
+ remote-endpoint = <&panel_in_lvds1>;
+ };
+ };
+ };
+};
+
+&pwm2 {
+ status = "okay";
+};
diff --git a/dts/upstream/src/arm64/freescale/imx8mp-tqma8mpql-mba8mpxl.dts b/dts/upstream/src/arm64/freescale/imx8mp-tqma8mpql-mba8mpxl.dts
index 4240e20..86d3da3 100644
--- a/dts/upstream/src/arm64/freescale/imx8mp-tqma8mpql-mba8mpxl.dts
+++ b/dts/upstream/src/arm64/freescale/imx8mp-tqma8mpql-mba8mpxl.dts
@@ -15,6 +15,7 @@
/ {
model = "TQ-Systems i.MX8MPlus TQMa8MPxL on MBa8MPxL";
compatible = "tq,imx8mp-tqma8mpql-mba8mpxl", "tq,imx8mp-tqma8mpql", "fsl,imx8mp";
+ chassis-type = "embedded";
chosen {
stdout-path = &uart4;
@@ -55,6 +56,21 @@
clock-frequency = <25000000>;
};
+ connector {
+ compatible = "gpio-usb-b-connector", "usb-b-connector";
+ type = "micro";
+ label = "X29";
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_usbcon0>;
+ id-gpios = <&gpio1 10 GPIO_ACTIVE_HIGH>;
+
+ port {
+ usb_dr_connector: endpoint {
+ remote-endpoint = <&usb3_dwc>;
+ };
+ };
+ };
+
fan0: pwm-fan {
compatible = "pwm-fan";
pinctrl-names = "default";
@@ -168,6 +184,13 @@
enable-active-high;
};
+ reg_vcc_1v8: regulator-1v8 {
+ compatible = "regulator-fixed";
+ regulator-name = "VCC_1V8";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ };
+
reg_vcc_3v3: regulator-3v3 {
compatible = "regulator-fixed";
regulator-name = "VCC_3V3";
@@ -464,7 +487,7 @@
clock-names = "mclk";
clocks = <&audio_blk_ctrl IMX8MP_CLK_AUDIOMIX_SAI3_MCLK1>;
reset-gpios = <&gpio4 29 GPIO_ACTIVE_LOW>;
- iov-supply = <®_vcc_3v3>;
+ iov-supply = <®_vcc_1v8>;
ldoin-supply = <®_vcc_3v3>;
};
@@ -602,7 +625,6 @@
&usb3_1 {
fsl,disable-port-power-control;
fsl,permanently-attached;
- dr_mode = "host";
status = "okay";
};
@@ -626,13 +648,10 @@
role-switch-default-mode = "peripheral";
status = "okay";
- connector {
- compatible = "gpio-usb-b-connector", "usb-b-connector";
- type = "micro";
- label = "X29";
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_usbcon0>;
- id-gpios = <&gpio1 10 GPIO_ACTIVE_HIGH>;
+ port {
+ usb3_dwc: endpoint {
+ remote-endpoint = <&usb_dr_connector>;
+ };
};
};
diff --git a/dts/upstream/src/arm64/freescale/imx8mp-venice-gw71xx.dtsi b/dts/upstream/src/arm64/freescale/imx8mp-venice-gw71xx.dtsi
index bf47b5e..0e8d0f3 100644
--- a/dts/upstream/src/arm64/freescale/imx8mp-venice-gw71xx.dtsi
+++ b/dts/upstream/src/arm64/freescale/imx8mp-venice-gw71xx.dtsi
@@ -8,6 +8,21 @@
#include <dt-bindings/phy/phy-imx8-pcie.h>
/ {
+ connector {
+ compatible = "gpio-usb-b-connector", "usb-b-connector";
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_usbcon1>;
+ type = "micro";
+ label = "Type-C";
+ id-gpios = <&gpio3 21 GPIO_ACTIVE_HIGH>;
+
+ port {
+ usb_dr_connector: endpoint {
+ remote-endpoint = <&usb3_dwc>;
+ };
+ };
+ };
+
led-controller {
compatible = "gpio-leds";
pinctrl-names = "default";
@@ -132,13 +147,10 @@
role-switch-default-mode = "peripheral";
status = "okay";
- connector {
- compatible = "gpio-usb-b-connector", "usb-b-connector";
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_usbcon1>;
- type = "micro";
- label = "Type-C";
- id-gpios = <&gpio3 21 GPIO_ACTIVE_HIGH>;
+ port {
+ usb3_dwc: endpoint {
+ remote-endpoint = <&usb_dr_connector>;
+ };
};
};
diff --git a/dts/upstream/src/arm64/freescale/imx8mp-venice-gw72xx.dtsi b/dts/upstream/src/arm64/freescale/imx8mp-venice-gw72xx.dtsi
index f942e94..41c79d2 100644
--- a/dts/upstream/src/arm64/freescale/imx8mp-venice-gw72xx.dtsi
+++ b/dts/upstream/src/arm64/freescale/imx8mp-venice-gw72xx.dtsi
@@ -8,6 +8,21 @@
#include <dt-bindings/phy/phy-imx8-pcie.h>
/ {
+ connector {
+ compatible = "gpio-usb-b-connector", "usb-b-connector";
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_usbcon1>;
+ type = "micro";
+ label = "otg";
+ id-gpios = <&gpio3 21 GPIO_ACTIVE_HIGH>;
+
+ port {
+ usb_dr_connector: endpoint {
+ remote-endpoint = <&usb3_dwc>;
+ };
+ };
+ };
+
led-controller {
compatible = "gpio-leds";
pinctrl-names = "default";
@@ -83,8 +98,15 @@
&ecspi2 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_spi2>;
- cs-gpios = <&gpio5 13 GPIO_ACTIVE_LOW>;
+ cs-gpios = <&gpio5 13 GPIO_ACTIVE_LOW>,
+ <&gpio1 10 GPIO_ACTIVE_LOW>;
status = "okay";
+
+ tpm@1 {
+ compatible = "atmel,attpm20p", "tcg,tpm_tis-spi";
+ reg = <0x1>;
+ spi-max-frequency = <36000000>;
+ };
};
&gpio4 {
@@ -175,13 +197,10 @@
role-switch-default-mode = "peripheral";
status = "okay";
- connector {
- compatible = "gpio-usb-b-connector", "usb-b-connector";
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_usbcon1>;
- type = "micro";
- label = "otg";
- id-gpios = <&gpio3 21 GPIO_ACTIVE_HIGH>;
+ port {
+ usb3_dwc: endpoint {
+ remote-endpoint = <&usb_dr_connector>;
+ };
};
};
@@ -285,6 +304,7 @@
MX8MP_IOMUXC_ECSPI2_MOSI__ECSPI2_MOSI 0x140
MX8MP_IOMUXC_ECSPI2_MISO__ECSPI2_MISO 0x140
MX8MP_IOMUXC_ECSPI2_SS0__GPIO5_IO13 0x140
+ MX8MP_IOMUXC_GPIO1_IO10__GPIO1_IO10 0x140
>;
};
diff --git a/dts/upstream/src/arm64/freescale/imx8mp-venice-gw73xx.dtsi b/dts/upstream/src/arm64/freescale/imx8mp-venice-gw73xx.dtsi
index b0d42b1..d5c400b 100644
--- a/dts/upstream/src/arm64/freescale/imx8mp-venice-gw73xx.dtsi
+++ b/dts/upstream/src/arm64/freescale/imx8mp-venice-gw73xx.dtsi
@@ -8,6 +8,21 @@
#include <dt-bindings/phy/phy-imx8-pcie.h>
/ {
+ connector {
+ compatible = "gpio-usb-b-connector", "usb-b-connector";
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_usbcon1>;
+ type = "micro";
+ label = "otg";
+ id-gpios = <&gpio3 21 GPIO_ACTIVE_HIGH>;
+
+ port {
+ usb_dr_connector: endpoint {
+ remote-endpoint = <&usb3_dwc>;
+ };
+ };
+ };
+
led-controller {
compatible = "gpio-leds";
pinctrl-names = "default";
@@ -100,7 +115,7 @@
status = "okay";
tpm@1 {
- compatible = "tcg,tpm_tis-spi";
+ compatible = "atmel,attpm20p", "tcg,tpm_tis-spi";
reg = <0x1>;
spi-max-frequency = <36000000>;
};
@@ -201,13 +216,10 @@
role-switch-default-mode = "peripheral";
status = "okay";
- connector {
- compatible = "gpio-usb-b-connector", "usb-b-connector";
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_usbcon1>;
- type = "micro";
- label = "otg";
- id-gpios = <&gpio3 21 GPIO_ACTIVE_HIGH>;
+ port {
+ usb3_dwc: endpoint {
+ remote-endpoint = <&usb_dr_connector>;
+ };
};
};
diff --git a/dts/upstream/src/arm64/freescale/imx8mp-venice-gw74xx.dts b/dts/upstream/src/arm64/freescale/imx8mp-venice-gw74xx.dts
index 2ab9f4c..cae586c 100644
--- a/dts/upstream/src/arm64/freescale/imx8mp-venice-gw74xx.dts
+++ b/dts/upstream/src/arm64/freescale/imx8mp-venice-gw74xx.dts
@@ -35,6 +35,21 @@
reg = <0x0 0x40000000 0 0x80000000>;
};
+ connector {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_usbcon1>;
+ compatible = "gpio-usb-b-connector", "usb-b-connector";
+ type = "micro";
+ label = "Type-C";
+ id-gpios = <&gpio1 10 GPIO_ACTIVE_HIGH>;
+
+ port {
+ usb_dr_connector: endpoint {
+ remote-endpoint = <&usb3_dwc>;
+ };
+ };
+ };
+
gpio-keys {
compatible = "gpio-keys";
@@ -181,9 +196,7 @@
status = "okay";
tpm@0 {
- compatible = "tcg,tpm_tis-spi";
- #address-cells = <0x1>;
- #size-cells = <0x1>;
+ compatible = "atmel,attpm20p", "tcg,tpm_tis-spi";
reg = <0x0>;
spi-max-frequency = <36000000>;
};
@@ -694,13 +707,10 @@
role-switch-default-mode = "peripheral";
status = "okay";
- connector {
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_usbcon1>;
- compatible = "gpio-usb-b-connector", "usb-b-connector";
- type = "micro";
- label = "Type-C";
- id-gpios = <&gpio1 10 GPIO_ACTIVE_HIGH>;
+ port {
+ usb3_dwc: endpoint {
+ remote-endpoint = <&usb_dr_connector>;
+ };
};
};
diff --git a/dts/upstream/src/arm64/freescale/imx8mp-verdin-mallow.dtsi b/dts/upstream/src/arm64/freescale/imx8mp-verdin-mallow.dtsi
new file mode 100644
index 0000000..8482393
--- /dev/null
+++ b/dts/upstream/src/arm64/freescale/imx8mp-verdin-mallow.dtsi
@@ -0,0 +1,199 @@
+// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
+/*
+ * Copyright 2023 Toradex
+ *
+ * Common dtsi for Verdin IMX8MP SoM on Mallow carrier board
+ *
+ * https://www.toradex.com/computer-on-modules/verdin-arm-family/nxp-imx-8m-plus
+ * https://www.toradex.com/products/carrier-board/mallow-carrier-board
+ */
+
+#include <dt-bindings/leds/common.h>
+
+/ {
+ leds {
+ compatible = "gpio-leds";
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_leds>;
+
+ /* SODIMM 52 - USER_LED_1_RED */
+ led-0 {
+ color = <LED_COLOR_ID_RED>;
+ function = LED_FUNCTION_DEBUG;
+ function-enumerator = <1>;
+ gpios = <&gpio3 0 GPIO_ACTIVE_HIGH>;
+ };
+
+ /* SODIMM 54 - USER_LED_1_GREEN */
+ led-1 {
+ color = <LED_COLOR_ID_GREEN>;
+ function = LED_FUNCTION_DEBUG;
+ function-enumerator = <1>;
+ gpios = <&gpio3 1 GPIO_ACTIVE_HIGH>;
+ };
+
+ /* SODIMM 56 - USER_LED_2_RED */
+ led-2 {
+ color = <LED_COLOR_ID_RED>;
+ function = LED_FUNCTION_DEBUG;
+ function-enumerator = <2>;
+ gpios = <&gpio3 6 GPIO_ACTIVE_HIGH>;
+ };
+
+ /* SODIMM 58 - USER_LED_2_GREEN */
+ led-3 {
+ color = <LED_COLOR_ID_GREEN>;
+ function = LED_FUNCTION_DEBUG;
+ function-enumerator = <2>;
+ gpios = <&gpio3 7 GPIO_ACTIVE_HIGH>;
+ };
+ };
+};
+
+&backlight {
+ power-supply = <®_3p3v>;
+};
+
+/* Verdin SPI_1 */
+&ecspi1 {
+ pinctrl-0 = <&pinctrl_ecspi1>, <&pinctrl_tpm_cs>;
+ cs-gpios = <&gpio5 9 GPIO_ACTIVE_LOW>, <&gpio3 16 GPIO_ACTIVE_LOW>;
+ status = "okay";
+
+ tpm@1 {
+ compatible = "infineon,slb9670", "tcg,tpm_tis-spi";
+ reg = <1>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_tpm_irq>;
+ interrupt-parent = <&gpio3>;
+ interrupts = <14 IRQ_TYPE_LEVEL_LOW>;
+ spi-max-frequency = <18500000>;
+ };
+};
+
+/* EEPROM on Mallow */
+&eeprom_carrier_board {
+ status = "okay";
+};
+
+/* Verdin ETH_1 */
+&eqos {
+ status = "okay";
+};
+
+/* Verdin CAN_1 */
+&flexcan1 {
+ status = "okay";
+};
+
+/* Verdin CAN_2 */
+&flexcan2 {
+ status = "okay";
+};
+
+/* Temperature sensor on Mallow */
+&hwmon_temp {
+ compatible = "ti,tmp1075";
+ status = "okay";
+};
+
+/* Verdin I2C_2_DSI */
+&i2c2 {
+ status = "okay";
+};
+
+/* Verdin I2C_4_CSI */
+&i2c3 {
+ status = "okay";
+};
+
+/* Verdin I2C_1 */
+&i2c4 {
+ status = "okay";
+};
+
+/* Verdin PCIE_1 */
+&pcie {
+ status = "okay";
+};
+
+&pcie_phy {
+ status = "okay";
+};
+
+/* Verdin PWM_1 */
+&pwm1 {
+ status = "okay";
+};
+
+/* Verdin PWM_2 */
+&pwm2 {
+ status = "okay";
+};
+
+/* Verdin PWM_3_DSI */
+&pwm3 {
+ status = "okay";
+};
+
+®_usdhc2_vmmc {
+ vin-supply = <®_3p3v>;
+};
+
+/* Verdin UART_1 */
+&uart1 {
+ status = "okay";
+};
+
+/* Verdin UART_2 */
+&uart2 {
+ status = "okay";
+};
+
+/* Verdin UART_3 */
+&uart3 {
+ status = "okay";
+};
+
+/* Verdin USB_1 */
+&usb3_0 {
+ status = "okay";
+};
+
+&usb3_phy0 {
+ status = "okay";
+};
+
+/* Verdin USB_2 */
+&usb3_1 {
+ status = "okay";
+};
+
+&usb3_phy1 {
+ status = "okay";
+};
+
+/* Verdin SD_1 */
+&usdhc2 {
+ status = "okay";
+};
+
+&iomuxc {
+ pinctrl_leds: ledsgrp {
+ fsl,pins =
+ <MX8MP_IOMUXC_NAND_ALE__GPIO3_IO00 0x106>, /* SODIMM 52 */
+ <MX8MP_IOMUXC_NAND_CE0_B__GPIO3_IO01 0x106>, /* SODIMM 54 */
+ <MX8MP_IOMUXC_NAND_DATA00__GPIO3_IO06 0x106>, /* SODIMM 56 */
+ <MX8MP_IOMUXC_NAND_DATA01__GPIO3_IO07 0x106>; /* SODIMM 58 */
+ };
+
+ pinctrl_tpm_cs: tpmcsgrp {
+ fsl,pins =
+ <MX8MP_IOMUXC_NAND_READY_B__GPIO3_IO16 0x82>; /* SODIMM 64 */
+ };
+
+ pinctrl_tpm_irq: tpmirqgrp {
+ fsl,pins =
+ <MX8MP_IOMUXC_NAND_DQS__GPIO3_IO14 0x16>; /* SODIMM 66 */
+ };
+};
diff --git a/dts/upstream/src/arm64/freescale/imx8mp-verdin-nonwifi-mallow.dts b/dts/upstream/src/arm64/freescale/imx8mp-verdin-nonwifi-mallow.dts
new file mode 100644
index 0000000..6a536a4
--- /dev/null
+++ b/dts/upstream/src/arm64/freescale/imx8mp-verdin-nonwifi-mallow.dts
@@ -0,0 +1,18 @@
+// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
+/*
+ * Copyright 2023 Toradex
+ */
+
+/dts-v1/;
+
+#include "imx8mp-verdin.dtsi"
+#include "imx8mp-verdin-nonwifi.dtsi"
+#include "imx8mp-verdin-mallow.dtsi"
+
+/ {
+ model = "Toradex Verdin iMX8M Plus on Mallow Board";
+ compatible = "toradex,verdin-imx8mp-nonwifi-mallow",
+ "toradex,verdin-imx8mp-nonwifi",
+ "toradex,verdin-imx8mp",
+ "fsl,imx8mp";
+};
diff --git a/dts/upstream/src/arm64/freescale/imx8mp-verdin-wifi-mallow.dts b/dts/upstream/src/arm64/freescale/imx8mp-verdin-wifi-mallow.dts
new file mode 100644
index 0000000..08b7aef
--- /dev/null
+++ b/dts/upstream/src/arm64/freescale/imx8mp-verdin-wifi-mallow.dts
@@ -0,0 +1,18 @@
+// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
+/*
+ * Copyright 2023 Toradex
+ */
+
+/dts-v1/;
+
+#include "imx8mp-verdin.dtsi"
+#include "imx8mp-verdin-wifi.dtsi"
+#include "imx8mp-verdin-mallow.dtsi"
+
+/ {
+ model = "Toradex Verdin iMX8M Plus WB on Mallow Board";
+ compatible = "toradex,verdin-imx8mp-wifi-mallow",
+ "toradex,verdin-imx8mp-wifi",
+ "toradex,verdin-imx8mp",
+ "fsl,imx8mp";
+};
diff --git a/dts/upstream/src/arm64/freescale/imx8mp-verdin.dtsi b/dts/upstream/src/arm64/freescale/imx8mp-verdin.dtsi
index 04f2083..c3305f0 100644
--- a/dts/upstream/src/arm64/freescale/imx8mp-verdin.dtsi
+++ b/dts/upstream/src/arm64/freescale/imx8mp-verdin.dtsi
@@ -45,6 +45,23 @@
status = "disabled";
};
+ connector {
+ compatible = "gpio-usb-b-connector", "usb-b-connector";
+ id-gpios = <&gpio2 10 GPIO_ACTIVE_HIGH>;
+ label = "Type-C";
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_usb_1_id>;
+ self-powered;
+ type = "micro";
+ vbus-supply = <®_usb1_vbus>;
+
+ port {
+ usb_dr_connector: endpoint {
+ remote-endpoint = <&usb3_dwc>;
+ };
+ };
+ };
+
gpio-keys {
compatible = "gpio-keys";
pinctrl-names = "default";
@@ -835,15 +852,10 @@
srp-disable;
usb-role-switch;
- connector {
- compatible = "gpio-usb-b-connector", "usb-b-connector";
- id-gpios = <&gpio2 10 GPIO_ACTIVE_HIGH>;
- label = "Type-C";
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_usb_1_id>;
- self-powered;
- type = "micro";
- vbus-supply = <®_usb1_vbus>;
+ port {
+ usb3_dwc: endpoint {
+ remote-endpoint = <&usb_dr_connector>;
+ };
};
};
diff --git a/dts/upstream/src/arm64/freescale/imx8mp.dtsi b/dts/upstream/src/arm64/freescale/imx8mp.dtsi
index 1264da6..39a550c 100644
--- a/dts/upstream/src/arm64/freescale/imx8mp.dtsi
+++ b/dts/upstream/src/arm64/freescale/imx8mp.dtsi
@@ -264,6 +264,7 @@
dsp_reserved: dsp@92400000 {
reg = <0 0x92400000 0 0x2000000>;
no-map;
+ status = "disabled";
};
};
@@ -726,6 +727,8 @@
clk: clock-controller@30380000 {
compatible = "fsl,imx8mp-ccm";
reg = <0x30380000 0x10000>;
+ interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
#clock-cells = <1>;
clocks = <&osc_32k>, <&osc_24m>, <&clk_ext1>, <&clk_ext2>,
<&clk_ext3>, <&clk_ext4>;
@@ -793,8 +796,8 @@
<&clk IMX8MP_CLK_AUDIO_AXI>;
assigned-clocks = <&clk IMX8MP_CLK_AUDIO_AHB>,
<&clk IMX8MP_CLK_AUDIO_AXI_SRC>;
- assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_800M>,
- <&clk IMX8MP_SYS_PLL1_800M>;
+ assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_800M>,
+ <&clk IMX8MP_SYS_PLL1_800M>;
assigned-clock-rates = <400000000>,
<600000000>;
};
@@ -887,6 +890,15 @@
clocks = <&clk IMX8MP_CLK_ML_AXI>,
<&clk IMX8MP_CLK_ML_AHB>,
<&clk IMX8MP_CLK_NPU_ROOT>;
+ assigned-clocks = <&clk IMX8MP_CLK_ML_CORE>,
+ <&clk IMX8MP_CLK_ML_AXI>,
+ <&clk IMX8MP_CLK_ML_AHB>;
+ assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_800M>,
+ <&clk IMX8MP_SYS_PLL1_800M>,
+ <&clk IMX8MP_SYS_PLL1_800M>;
+ assigned-clock-rates = <800000000>,
+ <800000000>,
+ <300000000>;
};
};
};
@@ -1808,7 +1820,7 @@
compatible = "fsl,imx8mp-ldb";
reg = <0x5c 0x4>, <0x128 0x4>;
reg-names = "ldb", "lvds";
- clocks = <&clk IMX8MP_CLK_MEDIA_LDB>;
+ clocks = <&clk IMX8MP_CLK_MEDIA_LDB_ROOT>;
clock-names = "ldb";
assigned-clocks = <&clk IMX8MP_CLK_MEDIA_LDB>;
assigned-clock-parents = <&clk IMX8MP_VIDEO_PLL1_OUT>;
@@ -2012,6 +2024,18 @@
interconnect-names = "g1", "g2", "vc8000e";
};
+ npu: npu@38500000 {
+ compatible = "vivante,gc";
+ reg = <0x38500000 0x200000>;
+ interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&clk IMX8MP_CLK_NPU_ROOT>,
+ <&clk IMX8MP_CLK_NPU_ROOT>,
+ <&clk IMX8MP_CLK_ML_AXI>,
+ <&clk IMX8MP_CLK_ML_AHB>;
+ clock-names = "core", "shader", "bus", "reg";
+ power-domains = <&pgc_mlmix>;
+ };
+
gic: interrupt-controller@38800000 {
compatible = "arm,gic-v3";
reg = <0x38800000 0x10000>,
diff --git a/dts/upstream/src/arm64/freescale/imx8mq-kontron-pitx-imx8m.dts b/dts/upstream/src/arm64/freescale/imx8mq-kontron-pitx-imx8m.dts
index 6376417..d8cf1f2 100644
--- a/dts/upstream/src/arm64/freescale/imx8mq-kontron-pitx-imx8m.dts
+++ b/dts/upstream/src/arm64/freescale/imx8mq-kontron-pitx-imx8m.dts
@@ -65,7 +65,7 @@
status = "okay";
tpm@0 {
- compatible = "infineon,slb9670";
+ compatible = "infineon,slb9670", "tcg,tpm_tis-spi";
reg = <0>;
spi-max-frequency = <43000000>;
};
diff --git a/dts/upstream/src/arm64/freescale/imx8mq-phanbell.dts b/dts/upstream/src/arm64/freescale/imx8mq-phanbell.dts
index a3b9d61..e34045d 100644
--- a/dts/upstream/src/arm64/freescale/imx8mq-phanbell.dts
+++ b/dts/upstream/src/arm64/freescale/imx8mq-phanbell.dts
@@ -39,7 +39,7 @@
fan: gpio-fan {
compatible = "gpio-fan";
- gpio-fan,speed-map = <0 0 8600 1>;
+ gpio-fan,speed-map = <0 0>, <8600 1>;
gpios = <&gpio3 5 GPIO_ACTIVE_HIGH>;
#cooling-cells = <2>;
pinctrl-names = "default";
diff --git a/dts/upstream/src/arm64/freescale/imx8mq-tqma8mq-mba8mx.dts b/dts/upstream/src/arm64/freescale/imx8mq-tqma8mq-mba8mx.dts
index 0d8def2..b302dac 100644
--- a/dts/upstream/src/arm64/freescale/imx8mq-tqma8mq-mba8mx.dts
+++ b/dts/upstream/src/arm64/freescale/imx8mq-tqma8mq-mba8mx.dts
@@ -11,6 +11,7 @@
/ {
model = "TQ-Systems GmbH i.MX8MQ TQMa8MQ on MBa8Mx";
compatible = "tq,imx8mq-tqma8mq-mba8mx", "tq,imx8mq-tqma8mq", "fsl,imx8mq";
+ chassis-type = "embedded";
aliases {
eeprom0 = &eeprom3;
diff --git a/dts/upstream/src/arm64/freescale/imx8qm-ss-dma.dtsi b/dts/upstream/src/arm64/freescale/imx8qm-ss-dma.dtsi
index 8439dd6..69cb867 100644
--- a/dts/upstream/src/arm64/freescale/imx8qm-ss-dma.dtsi
+++ b/dts/upstream/src/arm64/freescale/imx8qm-ss-dma.dtsi
@@ -128,21 +128,25 @@
&lpuart0 {
compatible = "fsl,imx8qm-lpuart", "fsl,imx8qxp-lpuart";
dmas = <&edma2 13 0 0>, <&edma2 12 0 1>;
+ dma-names = "rx","tx";
};
&lpuart1 {
compatible = "fsl,imx8qm-lpuart", "fsl,imx8qxp-lpuart";
dmas = <&edma2 15 0 0>, <&edma2 14 0 1>;
+ dma-names = "rx","tx";
};
&lpuart2 {
compatible = "fsl,imx8qm-lpuart", "fsl,imx8qxp-lpuart";
dmas = <&edma2 17 0 0>, <&edma2 16 0 1>;
+ dma-names = "rx","tx";
};
&lpuart3 {
compatible = "fsl,imx8qm-lpuart", "fsl,imx8qxp-lpuart";
dmas = <&edma2 19 0 0>, <&edma2 18 0 1>;
+ dma-names = "rx","tx";
};
&i2c0 {
diff --git a/dts/upstream/src/arm64/freescale/imx8qxp-mek.dts b/dts/upstream/src/arm64/freescale/imx8qxp-mek.dts
index 9961172..8360bb8 100644
--- a/dts/upstream/src/arm64/freescale/imx8qxp-mek.dts
+++ b/dts/upstream/src/arm64/freescale/imx8qxp-mek.dts
@@ -31,7 +31,7 @@
};
gpio-sbu-mux {
- compatible = "gpio-sbu-mux";
+ compatible = "nxp,cbdtu02043", "gpio-sbu-mux";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_typec_mux>;
select-gpios = <&lsio_gpio5 9 GPIO_ACTIVE_HIGH>;
@@ -50,6 +50,10 @@
status = "okay";
};
+&dsp_reserved {
+ status = "okay";
+};
+
&fec1 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_fec1>;
@@ -152,12 +156,6 @@
interrupt-parent = <&lsio_gpio1>;
interrupts = <3 IRQ_TYPE_LEVEL_LOW>;
- port {
- typec_dr_sw: endpoint {
- remote-endpoint = <&usb3_drd_sw>;
- };
- };
-
usb_con1: connector {
compatible = "usb-c-connector";
label = "USB-C";
@@ -169,8 +167,17 @@
#address-cells = <1>;
#size-cells = <0>;
+ port@0 {
+ reg = <0>;
+
+ typec_dr_sw: endpoint {
+ remote-endpoint = <&usb3_drd_sw>;
+ };
+ };
+
port@1 {
reg = <1>;
+
typec_con_ss: endpoint {
remote-endpoint = <&usb3_data_ss>;
};
diff --git a/dts/upstream/src/arm64/freescale/imx8qxp-ss-vpu.dtsi b/dts/upstream/src/arm64/freescale/imx8qxp-ss-vpu.dtsi
new file mode 100644
index 0000000..7894a3a
--- /dev/null
+++ b/dts/upstream/src/arm64/freescale/imx8qxp-ss-vpu.dtsi
@@ -0,0 +1,17 @@
+// SPDX-License-Identifier: (GPL-2.0-or-later OR X11)
+/*
+ * Copyright 2023 TQ-Systems GmbH <linux@ew.tq-group.com>,
+ * D-82229 Seefeld, Germany.
+ * Author: Alexander Stein
+ */
+
+&vpu_core0 {
+ reg = <0x2d040000 0x10000>;
+};
+
+&vpu_core1 {
+ reg = <0x2d050000 0x10000>;
+};
+
+/delete-node/ &mu2_m0;
+/delete-node/ &vpu_core2;
diff --git a/dts/upstream/src/arm64/freescale/imx8qxp.dtsi b/dts/upstream/src/arm64/freescale/imx8qxp.dtsi
index c80c85a..958267b 100644
--- a/dts/upstream/src/arm64/freescale/imx8qxp.dtsi
+++ b/dts/upstream/src/arm64/freescale/imx8qxp.dtsi
@@ -48,7 +48,6 @@
serial3 = &lpuart3;
vpu-core0 = &vpu_core0;
vpu-core1 = &vpu_core1;
- vpu-core2 = &vpu_core2;
};
cpus {
@@ -184,6 +183,7 @@
dsp_reserved: dsp@92400000 {
reg = <0 0x92400000 0 0x2000000>;
no-map;
+ status = "disabled";
};
encoder_rpc: encoder-rpc@94400000 {
@@ -317,6 +317,7 @@
};
#include "imx8qxp-ss-img.dtsi"
+#include "imx8qxp-ss-vpu.dtsi"
#include "imx8qxp-ss-adma.dtsi"
#include "imx8qxp-ss-conn.dtsi"
#include "imx8qxp-ss-lsio.dtsi"
diff --git a/dts/upstream/src/arm64/freescale/imx93-11x11-evk.dts b/dts/upstream/src/arm64/freescale/imx93-11x11-evk.dts
index 2b9d477..9921ea1 100644
--- a/dts/upstream/src/arm64/freescale/imx93-11x11-evk.dts
+++ b/dts/upstream/src/arm64/freescale/imx93-11x11-evk.dts
@@ -76,6 +76,7 @@
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
gpio = <&gpio3 7 GPIO_ACTIVE_HIGH>;
+ off-on-delay-us = <12000>;
enable-active-high;
};
};
@@ -237,18 +238,19 @@
>;
};
+ /* need to config the SION for data and cmd pad, refer to ERR052021 */
pinctrl_usdhc1: usdhc1grp {
fsl,pins = <
MX93_PAD_SD1_CLK__USDHC1_CLK 0x15fe
- MX93_PAD_SD1_CMD__USDHC1_CMD 0x13fe
- MX93_PAD_SD1_DATA0__USDHC1_DATA0 0x13fe
- MX93_PAD_SD1_DATA1__USDHC1_DATA1 0x13fe
- MX93_PAD_SD1_DATA2__USDHC1_DATA2 0x13fe
- MX93_PAD_SD1_DATA3__USDHC1_DATA3 0x13fe
- MX93_PAD_SD1_DATA4__USDHC1_DATA4 0x13fe
- MX93_PAD_SD1_DATA5__USDHC1_DATA5 0x13fe
- MX93_PAD_SD1_DATA6__USDHC1_DATA6 0x13fe
- MX93_PAD_SD1_DATA7__USDHC1_DATA7 0x13fe
+ MX93_PAD_SD1_CMD__USDHC1_CMD 0x400013fe
+ MX93_PAD_SD1_DATA0__USDHC1_DATA0 0x400013fe
+ MX93_PAD_SD1_DATA1__USDHC1_DATA1 0x400013fe
+ MX93_PAD_SD1_DATA2__USDHC1_DATA2 0x400013fe
+ MX93_PAD_SD1_DATA3__USDHC1_DATA3 0x400013fe
+ MX93_PAD_SD1_DATA4__USDHC1_DATA4 0x400013fe
+ MX93_PAD_SD1_DATA5__USDHC1_DATA5 0x400013fe
+ MX93_PAD_SD1_DATA6__USDHC1_DATA6 0x400013fe
+ MX93_PAD_SD1_DATA7__USDHC1_DATA7 0x400013fe
MX93_PAD_SD1_STROBE__USDHC1_STROBE 0x15fe
>;
};
@@ -265,14 +267,15 @@
>;
};
+ /* need to config the SION for data and cmd pad, refer to ERR052021 */
pinctrl_usdhc2: usdhc2grp {
fsl,pins = <
MX93_PAD_SD2_CLK__USDHC2_CLK 0x15fe
- MX93_PAD_SD2_CMD__USDHC2_CMD 0x13fe
- MX93_PAD_SD2_DATA0__USDHC2_DATA0 0x13fe
- MX93_PAD_SD2_DATA1__USDHC2_DATA1 0x13fe
- MX93_PAD_SD2_DATA2__USDHC2_DATA2 0x13fe
- MX93_PAD_SD2_DATA3__USDHC2_DATA3 0x13fe
+ MX93_PAD_SD2_CMD__USDHC2_CMD 0x400013fe
+ MX93_PAD_SD2_DATA0__USDHC2_DATA0 0x400013fe
+ MX93_PAD_SD2_DATA1__USDHC2_DATA1 0x400013fe
+ MX93_PAD_SD2_DATA2__USDHC2_DATA2 0x400013fe
+ MX93_PAD_SD2_DATA3__USDHC2_DATA3 0x400013fe
MX93_PAD_SD2_VSELECT__USDHC2_VSELECT 0x51e
>;
};
diff --git a/dts/upstream/src/arm64/freescale/imx93-tqma9352-mba93xxca.dts b/dts/upstream/src/arm64/freescale/imx93-tqma9352-mba93xxca.dts
new file mode 100644
index 0000000..af795ec
--- /dev/null
+++ b/dts/upstream/src/arm64/freescale/imx93-tqma9352-mba93xxca.dts
@@ -0,0 +1,709 @@
+// SPDX-License-Identifier: (GPL-2.0-or-later OR MIT)
+/*
+ * Copyright (c) 2022-2023 TQ-Systems GmbH <linux@ew.tq-group.com>,
+ * D-82229 Seefeld, Germany.
+ * Author: Markus Niebel
+ * Author: Alexander Stein
+ */
+/dts-v1/;
+
+#include <dt-bindings/input/input.h>
+#include <dt-bindings/leds/common.h>
+#include <dt-bindings/net/ti-dp83867.h>
+#include <dt-bindings/pwm/pwm.h>
+
+#include "imx93-tqma9352.dtsi"
+
+/{
+ model = "TQ-Systems i.MX93 TQMa93xxLA/TQMa93xxCA on MBa93xxCA starter kit";
+ compatible = "tq,imx93-tqma9352-mba93xxca",
+ "tq,imx93-tqma9352", "fsl,imx93";
+ chassis-type = "embedded";
+
+ chosen {
+ stdout-path = &lpuart1;
+ };
+
+ aliases {
+ eeprom0 = &eeprom0;
+ rtc0 = &pcf85063;
+ rtc1 = &bbnsm_rtc;
+ };
+
+ backlight_lvds: backlight {
+ compatible = "pwm-backlight";
+ pwms = <&tpm5 0 5000000 0>;
+ brightness-levels = <0 4 8 16 32 64 128 255>;
+ default-brightness-level = <7>;
+ power-supply = <®_12v0>;
+ enable-gpios = <&expander2 2 GPIO_ACTIVE_HIGH>;
+ status = "disabled";
+ };
+
+ fan0: pwm-fan {
+ compatible = "pwm-fan";
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_pwmfan>;
+ fan-supply = <®_pwm_fan>;
+ #cooling-cells = <2>;
+ /* typical 25 kHz -> 40.000 nsec */
+ pwms = <&tpm6 0 40000 PWM_POLARITY_INVERTED>;
+ cooling-levels = <0 32 64 128 196 240>;
+ pulses-per-revolution = <2>;
+ interrupt-parent = <&gpio2>;
+ interrupts = <9 IRQ_TYPE_EDGE_FALLING>;
+ status = "disabled";
+ };
+
+ gpio-keys {
+ compatible = "gpio-keys";
+ autorepeat;
+
+ switch-a {
+ label = "switcha";
+ linux,code = <BTN_0>;
+ gpios = <&expander0 6 GPIO_ACTIVE_LOW>;
+ wakeup-source;
+ };
+
+ switch-b {
+ label = "switchb";
+ linux,code = <BTN_1>;
+ gpios = <&expander0 7 GPIO_ACTIVE_LOW>;
+ wakeup-source;
+ };
+ };
+
+ gpio-leds {
+ compatible = "gpio-leds";
+
+ led-1 {
+ color = <LED_COLOR_ID_GREEN>;
+ function = LED_FUNCTION_STATUS;
+ gpios = <&expander2 6 GPIO_ACTIVE_HIGH>;
+ linux,default-trigger = "default-on";
+ };
+
+ led-2 {
+ color = <LED_COLOR_ID_AMBER>;
+ function = LED_FUNCTION_HEARTBEAT;
+ gpios = <&expander2 7 GPIO_ACTIVE_HIGH>;
+ linux,default-trigger = "heartbeat";
+ };
+ };
+
+ iio-hwmon {
+ compatible = "iio-hwmon";
+ io-channels = <&adc1 0>, <&adc1 1>, <&adc1 2>, <&adc1 3>;
+ };
+
+ reg_3v3: regulator-3v3 {
+ compatible = "regulator-fixed";
+ regulator-name = "V_3V3_MB";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ };
+
+ reg_5v0: regulator-5v0 {
+ compatible = "regulator-fixed";
+ regulator-name = "V_5V0_MB";
+ regulator-min-microvolt = <5000000>;
+ regulator-max-microvolt = <5000000>;
+ };
+
+ reg_12v0: regulator-12v0 {
+ compatible = "regulator-fixed";
+ regulator-name = "V_12V";
+ regulator-min-microvolt = <12000000>;
+ regulator-max-microvolt = <12000000>;
+ gpio = <&expander1 7 GPIO_ACTIVE_HIGH>;
+ enable-active-high;
+ };
+
+ reg_mpcie_1v5: regulator-mpcie-1v5 {
+ compatible = "regulator-fixed";
+ regulator-name = "V_1V5_MPCIE";
+ regulator-min-microvolt = <1500000>;
+ regulator-max-microvolt = <1500000>;
+ gpio = <&expander0 2 GPIO_ACTIVE_HIGH>;
+ enable-active-high;
+ };
+
+ reg_mpcie_3v3: regulator-mpcie-3v3 {
+ compatible = "regulator-fixed";
+ regulator-name = "V_3V3_MPCIE";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ gpio = <&expander0 3 GPIO_ACTIVE_HIGH>;
+ enable-active-high;
+ };
+
+ reg_pwm_fan: regulator-pwm-fan {
+ compatible = "regulator-fixed";
+ regulator-name = "FAN_PWR";
+ regulator-min-microvolt = <12000000>;
+ regulator-max-microvolt = <12000000>;
+ gpio = <&expander0 0 GPIO_ACTIVE_HIGH>;
+ enable-active-high;
+ vin-supply = <®_12v0>;
+ };
+
+ thermal-zones {
+ cpu-thermal {
+ trips {
+ cpu_active0: trip-active0 {
+ temperature = <40000>;
+ hysteresis = <5000>;
+ type = "active";
+ };
+
+ cpu_active1: trip-active1 {
+ temperature = <48000>;
+ hysteresis = <3000>;
+ type = "active";
+ };
+
+ cpu_active2: trip-active2 {
+ temperature = <60000>;
+ hysteresis = <10000>;
+ type = "active";
+ };
+ };
+
+ cooling-maps {
+ map1 {
+ trip = <&cpu_active0>;
+ cooling-device = <&fan0 1 1>;
+ };
+
+ map2 {
+ trip = <&cpu_active1>;
+ cooling-device = <&fan0 2 2>;
+ };
+
+ map3 {
+ trip = <&cpu_active2>;
+ cooling-device = <&fan0 3 3>;
+ };
+ };
+ };
+ };
+};
+
+&adc1 {
+ status = "okay";
+};
+
+&eqos {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_eqos>;
+ phy-mode = "rgmii-id";
+ phy-handle = <ðphy_eqos>;
+ status = "okay";
+
+ mdio {
+ compatible = "snps,dwmac-mdio";
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ ethphy_eqos: ethernet-phy@0 {
+ compatible = "ethernet-phy-ieee802.3-c22";
+ reg = <0>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_eqos_phy>;
+ reset-gpios = <&expander1 0 GPIO_ACTIVE_LOW>;
+ reset-assert-us = <500000>;
+ reset-deassert-us = <50000>;
+ interrupt-parent = <&gpio3>;
+ interrupts = <26 IRQ_TYPE_EDGE_FALLING>;
+ enet-phy-lane-no-swap;
+ ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_25_NS>;
+ ti,tx-internal-delay = <DP83867_RGMIIDCTL_2_25_NS>;
+ ti,fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>;
+ ti,dp83867-rxctrl-strap-quirk;
+ ti,clk-output-sel = <DP83867_CLK_O_SEL_OFF>;
+ };
+ };
+};
+
+&fec {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_fec>;
+ phy-mode = "rgmii-id";
+ phy-handle = <ðphy_fec>;
+ fsl,magic-packet;
+ status = "okay";
+
+ mdio {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ clock-frequency = <5000000>;
+
+ ethphy_fec: ethernet-phy@0 {
+ compatible = "ethernet-phy-ieee802.3-c22";
+ reg = <0>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_fec_phy>;
+ reset-gpios = <&expander1 1 GPIO_ACTIVE_LOW>;
+ reset-assert-us = <500000>;
+ reset-deassert-us = <50000>;
+ interrupt-parent = <&gpio3>;
+ interrupts = <27 IRQ_TYPE_EDGE_FALLING>;
+ enet-phy-lane-no-swap;
+ ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_25_NS>;
+ ti,tx-internal-delay = <DP83867_RGMIIDCTL_2_25_NS>;
+ ti,fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>;
+ ti,dp83867-rxctrl-strap-quirk;
+ ti,clk-output-sel = <DP83867_CLK_O_SEL_OFF>;
+ };
+ };
+};
+
+&flexcan1 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_flexcan1>;
+ xceiver-supply = <®_3v3>;
+ status = "okay";
+};
+
+&flexcan2 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_flexcan2>;
+ xceiver-supply = <®_3v3>;
+ status = "okay";
+};
+
+&gpio1 {
+ expander-irq-hog {
+ gpio-hog;
+ gpios = <12 GPIO_ACTIVE_LOW>;
+ input;
+ line-name = "PEX_INT#";
+ };
+
+ tcpc-irq-hog {
+ gpio-hog;
+ gpios = <2 GPIO_ACTIVE_LOW>;
+ input;
+ line-name = "USB_C_ALERT#";
+ };
+};
+
+&lpi2c3 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ clock-frequency = <400000>;
+ pinctrl-names = "default", "sleep";
+ pinctrl-0 = <&pinctrl_lpi2c3>;
+ pinctrl-1 = <&pinctrl_lpi2c3>;
+ status = "okay";
+
+ temperature-sensor@1c {
+ compatible = "nxp,se97b", "jedec,jc-42.4-temp";
+ reg = <0x1c>;
+ };
+
+ eeprom2: eeprom@54 {
+ compatible = "nxp,se97b", "atmel,24c02";
+ reg = <0x54>;
+ pagesize = <16>;
+ vcc-supply = <®_3v3>;
+ };
+
+ expander0: gpio@70 {
+ compatible = "nxp,pca9538";
+ reg = <0x70>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_pexp_irq>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ interrupt-parent = <&gpio1>;
+ interrupts = <12 IRQ_TYPE_LEVEL_LOW>;
+ vcc-supply = <®_3v3>;
+ gpio-line-names = "FAN_PWR_EN", "MPCIE_WAKE#",
+ "MPCIE_1V5_EN", "MPCIE_3V3_EN",
+ "MPCIE_PERST#", "MPCIE_WDISABLE#",
+ "BUTTON_A#", "BUTTON_B#";
+
+ mpcie-wake-hog {
+ gpio-hog;
+ gpios = <1 GPIO_ACTIVE_LOW>;
+ input;
+ line-name = "MPCIE_WAKE#";
+ };
+
+ /*
+ * Controls the mPCIE slot reset which is low active as
+ * reset signal. The output-low states, the signal is
+ * inactive, e.g. not in reset
+ */
+ mpcie_rst_hog: mpcie-rst-hog {
+ gpio-hog;
+ gpios = <4 GPIO_ACTIVE_LOW>;
+ output-low;
+ line-name = "MPCIE_PERST#";
+ };
+
+ /*
+ * Controls the mPCIE slot WDISABLE pin which is low active
+ * as disable signal. The output-low states, the signal is
+ * inactive, e.g. not disabled
+ */
+ mpcie_wdisable_hog: mpcie-wdisable-hog {
+ gpio-hog;
+ gpios = <5 GPIO_ACTIVE_LOW>;
+ output-low;
+ line-name = "MPCIE_WDISABLE#";
+ };
+ };
+
+ expander1: gpio@71 {
+ compatible = "nxp,pca9538";
+ reg = <0x71>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ vcc-supply = <®_3v3>;
+ gpio-line-names = "ENET1_RESET#", "ENET2_RESET#",
+ "USB_RESET#", "",
+ "WLAN_PD#", "WLAN_W_DISABLE#",
+ "WLAN_PERST#", "12V_EN";
+
+ /*
+ * Controls the on board USB Hub reset which is low
+ * active as reset signal. The output-low states, the
+ * signal is inactive, e.g. no reset
+ */
+ usb-reset-hog {
+ gpio-hog;
+ gpios = <2 GPIO_ACTIVE_LOW>;
+ output-low;
+ line-name = "USB_RESET#";
+ };
+
+ /*
+ * Controls the WiFi card PD pin which is low active
+ * as power down signal. The output-high states, the signal
+ * is active, e.g. card is powered down
+ */
+ wlan-pd-hog {
+ gpio-hog;
+ gpios = <4 GPIO_ACTIVE_LOW>;
+ output-high;
+ line-name = "WLAN_PD#";
+ };
+
+ /*
+ * Controls the WiFi card disable pin which is low active
+ * as disable signal. The output-high states, the signal
+ * is active, e.g. card is disabled
+ */
+ wlan-wdisable-hog {
+ gpio-hog;
+ gpios = <5 GPIO_ACTIVE_LOW>;
+ output-high;
+ line-name = "WLAN_W_DISABLE#";
+ };
+
+ /*
+ * Controls the WiFi card reset pin which is low active
+ * as reset signal. The output-high states, the signal
+ * is active, e.g. card in reset
+ */
+ wlan-perst-hog {
+ gpio-hog;
+ gpios = <6 GPIO_ACTIVE_LOW>;
+ output-high;
+ line-name = "WLAN_PERST#";
+ };
+ };
+
+ expander2: gpio@72 {
+ compatible = "nxp,pca9538";
+ reg = <0x72>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ vcc-supply = <®_3v3>;
+ gpio-line-names = "LCD_RESET#", "LCD_PWR_EN",
+ "LCD_BLT_EN", "DP_EN",
+ "MIPI_CSI_EN", "MIPI_CSI_RST#",
+ "USER_LED1", "USER_LED2";
+ };
+};
+
+&lpi2c5 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ clock-frequency = <400000>;
+ pinctrl-names = "default", "sleep";
+ pinctrl-0 = <&pinctrl_lpi2c5>;
+ pinctrl-1 = <&pinctrl_lpi2c5>;
+ status = "okay";
+};
+
+&lpspi6 {
+ pinctrl-names = "default", "sleep";
+ pinctrl-0 = <&pinctrl_lpspi6>;
+ pinctrl-1 = <&pinctrl_lpspi6>;
+ status = "okay";
+};
+
+&lpuart1 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_uart1>;
+ status = "okay";
+};
+
+&lpuart2 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_uart2>;
+ linux,rs485-enabled-at-boot-time;
+ status = "okay";
+};
+
+/* disabled per default, console for M33 */
+&lpuart3 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_uart3>;
+ status = "disabled";
+};
+
+&lpuart6 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_uart6>;
+ status = "okay";
+};
+
+&lpuart8 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_uart8>;
+ status = "okay";
+};
+
+&tpm5 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_tpm5>;
+};
+
+&tpm6 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_tpm6>;
+ status = "okay";
+};
+
+&usdhc2 {
+ pinctrl-names = "default", "state_100mhz", "state_200mhz";
+ pinctrl-0 = <&pinctrl_usdhc2_hs>, <&pinctrl_usdhc2_gpio>;
+ pinctrl-1 = <&pinctrl_usdhc2_uhs>, <&pinctrl_usdhc2_gpio>;
+ pinctrl-2 = <&pinctrl_usdhc2_uhs>, <&pinctrl_usdhc2_gpio>;
+ cd-gpios = <&gpio3 0 GPIO_ACTIVE_LOW>;
+ vmmc-supply = <®_usdhc2_vmmc>;
+ bus-width = <4>;
+ no-sdio;
+ no-mmc;
+ disable-wp;
+ status = "okay";
+};
+
+&iomuxc {
+ pinctrl_eqos: eqosgrp {
+ fsl,pins = <
+ /* PD | FSEL_2 | DSE X4 */
+ MX93_PAD_ENET1_MDC__ENET_QOS_MDC 0x51e
+ MX93_PAD_ENET1_MDIO__ENET_QOS_MDIO 0x4000051e
+ /* PD | FSEL_2 | DSE X6 */
+ MX93_PAD_ENET1_RD0__ENET_QOS_RGMII_RD0 0x57e
+ MX93_PAD_ENET1_RD1__ENET_QOS_RGMII_RD1 0x57e
+ MX93_PAD_ENET1_RD2__ENET_QOS_RGMII_RD2 0x57e
+ MX93_PAD_ENET1_RD3__ENET_QOS_RGMII_RD3 0x57e
+ /* PD | FSEL_3 | DSE X6 */
+ MX93_PAD_ENET1_RXC__CCM_ENET_QOS_CLOCK_GENERATE_RX_CLK 0x5fe
+ MX93_PAD_ENET1_RX_CTL__ENET_QOS_RGMII_RX_CTL 0x57e
+ /* PD | FSEL_2 | DSE X4 */
+ MX93_PAD_ENET1_TD0__ENET_QOS_RGMII_TD0 0x51e
+ MX93_PAD_ENET1_TD1__ENET_QOS_RGMII_TD1 0x51e
+ MX93_PAD_ENET1_TD2__ENET_QOS_RGMII_TD2 0x51e
+ MX93_PAD_ENET1_TD3__ENET_QOS_RGMII_TD3 0x51e
+ MX93_PAD_ENET1_TX_CTL__ENET_QOS_RGMII_TX_CTL 0x51e
+ /* PD | FSEL_3 | DSE X3 */
+ MX93_PAD_ENET1_TXC__CCM_ENET_QOS_CLOCK_GENERATE_TX_CLK 0x58e
+ >;
+ };
+
+ pinctrl_eqos_phy: eqosphygrp {
+ fsl,pins = <
+ MX93_PAD_CCM_CLKO1__GPIO3_IO26 0x1306
+ >;
+ };
+
+ pinctrl_fec: fecgrp {
+ fsl,pins = <
+ /* PD | FSEL_2 | DSE X4 */
+ MX93_PAD_ENET2_MDC__ENET1_MDC 0x51e
+ MX93_PAD_ENET2_MDIO__ENET1_MDIO 0x4000051e
+ /* PD | FSEL_2 | DSE X6 */
+ MX93_PAD_ENET2_RD0__ENET1_RGMII_RD0 0x57e
+ MX93_PAD_ENET2_RD1__ENET1_RGMII_RD1 0x57e
+ MX93_PAD_ENET2_RD2__ENET1_RGMII_RD2 0x57e
+ MX93_PAD_ENET2_RD3__ENET1_RGMII_RD3 0x57e
+ /* PD | FSEL_3 | DSE X6 */
+ MX93_PAD_ENET2_RXC__ENET1_RGMII_RXC 0x5fe
+ MX93_PAD_ENET2_RX_CTL__ENET1_RGMII_RX_CTL 0x57e
+ /* PD | FSEL_2 | DSE X4 */
+ MX93_PAD_ENET2_TD0__ENET1_RGMII_TD0 0x51e
+ MX93_PAD_ENET2_TD1__ENET1_RGMII_TD1 0x51e
+ MX93_PAD_ENET2_TD2__ENET1_RGMII_TD2 0x51e
+ MX93_PAD_ENET2_TD3__ENET1_RGMII_TD3 0x51e
+ MX93_PAD_ENET2_TX_CTL__ENET1_RGMII_TX_CTL 0x51e
+ /* PD | FSEL_3 | DSE X3 */
+ MX93_PAD_ENET2_TXC__ENET1_RGMII_TXC 0x58e
+ >;
+ };
+
+ pinctrl_fec_phy: fecphygrp {
+ fsl,pins = <
+ MX93_PAD_CCM_CLKO2__GPIO3_IO27 0x1306
+ >;
+ };
+
+ pinctrl_flexcan1: flexcan1grp {
+ fsl,pins = <
+ MX93_PAD_PDM_BIT_STREAM0__CAN1_RX 0x139e
+ MX93_PAD_PDM_CLK__CAN1_TX 0x139e
+ >;
+ };
+
+ pinctrl_flexcan2: flexcan2grp {
+ fsl,pins = <
+ MX93_PAD_GPIO_IO25__CAN2_TX 0x139e
+ MX93_PAD_GPIO_IO27__CAN2_RX 0x139e
+ >;
+ };
+
+ pinctrl_lpi2c3: lpi2c3grp {
+ fsl,pins = <
+ MX93_PAD_GPIO_IO28__LPI2C3_SDA 0x40000b9e
+ MX93_PAD_GPIO_IO29__LPI2C3_SCL 0x40000b9e
+ >;
+ };
+
+ pinctrl_lpi2c5: lpi2c5grp {
+ fsl,pins = <
+ MX93_PAD_GPIO_IO22__LPI2C5_SDA 0x40000b9e
+ MX93_PAD_GPIO_IO23__LPI2C5_SCL 0x40000b9e
+ >;
+ };
+
+ pinctrl_lpspi6: lpspi6grp {
+ fsl,pins = <
+ MX93_PAD_GPIO_IO00__LPSPI6_PCS0 0x3fe
+ MX93_PAD_GPIO_IO01__LPSPI6_SIN 0x3fe
+ MX93_PAD_GPIO_IO02__LPSPI6_SOUT 0x3fe
+ MX93_PAD_GPIO_IO03__LPSPI6_SCK 0x3fe
+ >;
+ };
+
+ pinctrl_pexp_irq: pexpirqgrp {
+ fsl,pins = <
+ MX93_PAD_SAI1_TXC__GPIO1_IO12 0x1306
+ >;
+ };
+
+ pinctrl_pwmfan: pwmfangrp {
+ fsl,pins = <
+ MX93_PAD_GPIO_IO09__GPIO2_IO09 0x1306
+ >;
+ };
+
+ pinctrl_tpm5: tpm5grp {
+ fsl,pins = <
+ MX93_PAD_GPIO_IO06__TPM5_CH0 0x57e
+ >;
+ };
+
+ pinctrl_tpm6: tpm6grp {
+ fsl,pins = <
+ MX93_PAD_GPIO_IO08__TPM6_CH0 0x57e
+ >;
+ };
+
+ pinctrl_typec: typecgrp {
+ fsl,pins = <
+ MX93_PAD_I2C2_SCL__GPIO1_IO02 0x1306
+ >;
+ };
+
+ pinctrl_uart1: uart1grp {
+ fsl,pins = <
+ MX93_PAD_UART1_RXD__LPUART1_RX 0x31e
+ MX93_PAD_UART1_TXD__LPUART1_TX 0x31e
+ >;
+ };
+
+ pinctrl_uart2: uart2grp {
+ fsl,pins = <
+ MX93_PAD_UART2_TXD__LPUART2_TX 0x31e
+ MX93_PAD_UART2_RXD__LPUART2_RX 0x31e
+ MX93_PAD_SAI1_TXD0__LPUART2_RTS_B 0x51e
+ >;
+ };
+
+ pinctrl_uart3: uart3grp {
+ fsl,pins = <
+ MX93_PAD_GPIO_IO14__LPUART3_TX 0x31e
+ MX93_PAD_GPIO_IO15__LPUART3_RX 0x31e
+ >;
+ };
+
+ pinctrl_uart6: uart6grp {
+ fsl,pins = <
+ MX93_PAD_GPIO_IO04__LPUART6_TX 0x31e
+ MX93_PAD_GPIO_IO05__LPUART6_RX 0x31e
+ >;
+ };
+
+ pinctrl_uart8: uart8grp {
+ fsl,pins = <
+ MX93_PAD_GPIO_IO12__LPUART8_TX 0x31e
+ MX93_PAD_GPIO_IO13__LPUART8_RX 0x31e
+ >;
+ };
+
+ pinctrl_usdhc2_gpio: usdhc2gpiogrp {
+ fsl,pins = <
+ MX93_PAD_SD2_CD_B__GPIO3_IO00 0x31e
+ >;
+ };
+
+ pinctrl_usdhc2_hs: usdhc2hsgrp {
+ fsl,pins = <
+ /* HYS | PD | PU | FSEL_3 | DSE X5 */
+ MX93_PAD_SD2_CLK__USDHC2_CLK 0x17be
+ /* HYS | PD | PU | FSEL_3 | DSE X4 */
+ MX93_PAD_SD2_CMD__USDHC2_CMD 0x139e
+ /* HYS | PD | PU | FSEL_3 | DSE X3 */
+ MX93_PAD_SD2_DATA0__USDHC2_DATA0 0x138e
+ MX93_PAD_SD2_DATA1__USDHC2_DATA1 0x138e
+ MX93_PAD_SD2_DATA2__USDHC2_DATA2 0x138e
+ MX93_PAD_SD2_DATA3__USDHC2_DATA3 0x138e
+ /* PD | PU | FSEL_2 | DSE X3 */
+ MX93_PAD_SD2_VSELECT__USDHC2_VSELECT 0x50e
+ >;
+ };
+
+ pinctrl_usdhc2_uhs: usdhc2uhsgrp {
+ fsl,pins = <
+ /* HYS | PD | PU | FSEL_3 | DSE X6 */
+ MX93_PAD_SD2_CLK__USDHC2_CLK 0x17fe
+ /* HYS | PD | PU | FSEL_3 | DSE X4 */
+ MX93_PAD_SD2_CMD__USDHC2_CMD 0x139e
+ MX93_PAD_SD2_DATA0__USDHC2_DATA0 0x139e
+ MX93_PAD_SD2_DATA1__USDHC2_DATA1 0x139e
+ MX93_PAD_SD2_DATA2__USDHC2_DATA2 0x139e
+ MX93_PAD_SD2_DATA3__USDHC2_DATA3 0x139e
+ /* PD | PU | FSEL_2 | DSE X3 */
+ MX93_PAD_SD2_VSELECT__USDHC2_VSELECT 0x50e
+ >;
+ };
+};
diff --git a/dts/upstream/src/arm64/freescale/imx93-tqma9352-mba93xxla.dts b/dts/upstream/src/arm64/freescale/imx93-tqma9352-mba93xxla.dts
index 3c5c67e..eb3f4cf 100644
--- a/dts/upstream/src/arm64/freescale/imx93-tqma9352-mba93xxla.dts
+++ b/dts/upstream/src/arm64/freescale/imx93-tqma9352-mba93xxla.dts
@@ -18,6 +18,7 @@
model = "TQ-Systems i.MX93 TQMa93xxLA on MBa93xxLA SBC";
compatible = "tq,imx93-tqma9352-mba93xxla",
"tq,imx93-tqma9352", "fsl,imx93";
+ chassis-type = "embedded";
chosen {
stdout-path = &lpuart1;
diff --git a/dts/upstream/src/arm64/freescale/imx93.dtsi b/dts/upstream/src/arm64/freescale/imx93.dtsi
index 34c0540..8f2e7c4 100644
--- a/dts/upstream/src/arm64/freescale/imx93.dtsi
+++ b/dts/upstream/src/arm64/freescale/imx93.dtsi
@@ -171,6 +171,18 @@
status = "disabled";
};
+ mqs1: mqs1 {
+ compatible = "fsl,imx93-mqs";
+ gpr = <&aonmix_ns_gpr>;
+ status = "disabled";
+ };
+
+ mqs2: mqs2 {
+ compatible = "fsl,imx93-mqs";
+ gpr = <&wakeupmix_gpr>;
+ status = "disabled";
+ };
+
soc@0 {
compatible = "simple-bus";
#address-cells = <1>;
@@ -282,6 +294,19 @@
status = "disabled";
};
+ i3c1: i3c-master@44330000 {
+ compatible = "silvaco,i3c-master-v1";
+ reg = <0x44330000 0x10000>;
+ interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
+ #address-cells = <3>;
+ #size-cells = <0>;
+ clocks = <&clk IMX93_CLK_BUS_AON>,
+ <&clk IMX93_CLK_I3C1_GATE>,
+ <&clk IMX93_CLK_I3C1_SLOW>;
+ clock-names = "pclk", "fast_clk", "slow_clk";
+ status = "disabled";
+ };
+
lpi2c1: i2c@44340000 {
compatible = "fsl,imx93-lpi2c", "fsl,imx7ulp-lpi2c";
reg = <0x44340000 0x10000>;
@@ -367,6 +392,19 @@
status = "disabled";
};
+ sai1: sai@443b0000 {
+ compatible = "fsl,imx93-sai";
+ reg = <0x443b0000 0x10000>;
+ interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&clk IMX93_CLK_SAI1_IPG>, <&clk IMX93_CLK_DUMMY>,
+ <&clk IMX93_CLK_SAI1_GATE>, <&clk IMX93_CLK_DUMMY>,
+ <&clk IMX93_CLK_DUMMY>;
+ clock-names = "bus", "mclk0", "mclk1", "mclk2", "mclk3";
+ dmas = <&edma1 22 0 1>, <&edma1 21 0 0>;
+ dma-names = "rx", "tx";
+ status = "disabled";
+ };
+
iomuxc: pinctrl@443c0000 {
compatible = "fsl,imx93-iomuxc";
reg = <0x443c0000 0x10000>;
@@ -395,6 +433,8 @@
#clock-cells = <1>;
clocks = <&osc_32k>, <&osc_24m>, <&clk_ext1>;
clock-names = "osc_32k", "osc_24m", "clk_ext1";
+ assigned-clocks = <&clk IMX93_CLK_AUDIO_PLL>;
+ assigned-clock-rates = <393216000>;
status = "okay";
};
@@ -422,9 +462,10 @@
};
};
- anatop: anatop@44480000 {
- compatible = "fsl,imx93-anatop", "syscon";
+ clock-controller@44480000 {
+ compatible = "fsl,imx93-anatop";
reg = <0x44480000 0x2000>;
+ #clock-cells = <1>;
};
tmu: tmu@44482000 {
@@ -447,6 +488,21 @@
#thermal-sensor-cells = <1>;
};
+ micfil: micfil@44520000 {
+ compatible = "fsl,imx93-micfil";
+ reg = <0x44520000 0x10000>;
+ interrupts = <GIC_SPI 202 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 201 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 200 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 199 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&clk IMX93_CLK_PDM_IPG>,
+ <&clk IMX93_CLK_PDM_GATE>,
+ <&clk IMX93_CLK_AUDIO_PLL>;
+ clock-names = "ipg_clk", "ipg_clk_app", "pll8k";
+ dmas = <&edma1 29 0 5>;
+ dma-names = "rx";
+ status = "disabled";
+ };
adc1: adc@44530000 {
compatible = "nxp,imx93-adc";
@@ -473,7 +529,6 @@
compatible = "fsl,imx93-edma4";
reg = <0x42000000 0x210000>;
#dma-cells = <3>;
- shared-interrupt;
dma-channels = <64>;
interrupts = <GIC_SPI 128 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 128 IRQ_TYPE_LEVEL_HIGH>,
@@ -616,6 +671,19 @@
status = "disabled";
};
+ i3c2: i3c-master@42520000 {
+ compatible = "silvaco,i3c-master-v1";
+ reg = <0x42520000 0x10000>;
+ interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>;
+ #address-cells = <3>;
+ #size-cells = <0>;
+ clocks = <&clk IMX93_CLK_BUS_WAKEUP>,
+ <&clk IMX93_CLK_I3C2_GATE>,
+ <&clk IMX93_CLK_I3C2_SLOW>;
+ clock-names = "pclk", "fast_clk", "slow_clk";
+ status = "disabled";
+ };
+
lpi2c3: i2c@42530000 {
compatible = "fsl,imx93-lpi2c", "fsl,imx7ulp-lpi2c";
reg = <0x42530000 0x10000>;
@@ -738,6 +806,51 @@
status = "disabled";
};
+ sai2: sai@42650000 {
+ compatible = "fsl,imx93-sai";
+ reg = <0x42650000 0x10000>;
+ interrupts = <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&clk IMX93_CLK_SAI2_IPG>, <&clk IMX93_CLK_DUMMY>,
+ <&clk IMX93_CLK_SAI2_GATE>, <&clk IMX93_CLK_DUMMY>,
+ <&clk IMX93_CLK_DUMMY>;
+ clock-names = "bus", "mclk0", "mclk1", "mclk2", "mclk3";
+ dmas = <&edma2 59 0 1>, <&edma2 58 0 0>;
+ dma-names = "rx", "tx";
+ status = "disabled";
+ };
+
+ sai3: sai@42660000 {
+ compatible = "fsl,imx93-sai";
+ reg = <0x42660000 0x10000>;
+ interrupts = <GIC_SPI 171 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&clk IMX93_CLK_SAI3_IPG>, <&clk IMX93_CLK_DUMMY>,
+ <&clk IMX93_CLK_SAI3_GATE>, <&clk IMX93_CLK_DUMMY>,
+ <&clk IMX93_CLK_DUMMY>;
+ clock-names = "bus", "mclk0", "mclk1", "mclk2", "mclk3";
+ dmas = <&edma2 61 0 1>, <&edma2 60 0 0>;
+ dma-names = "rx", "tx";
+ status = "disabled";
+ };
+
+ xcvr: xcvr@42680000 {
+ compatible = "fsl,imx93-xcvr";
+ reg = <0x42680000 0x800>,
+ <0x42680800 0x400>,
+ <0x42680c00 0x080>,
+ <0x42680e00 0x080>;
+ reg-names = "ram", "regs", "rxfifo", "txfifo";
+ interrupts = <GIC_SPI 203 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 204 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&clk IMX93_CLK_BUS_WAKEUP>,
+ <&clk IMX93_CLK_SPDIF_GATE>,
+ <&clk IMX93_CLK_DUMMY>,
+ <&clk IMX93_CLK_AUD_XCVR_GATE>;
+ clock-names = "ipg", "phy", "spba", "pll_ipg";
+ dmas = <&edma2 65 0 1>, <&edma2 66 0 0>;
+ dma-names = "rx", "tx";
+ status = "disabled";
+ };
+
lpuart7: serial@42690000 {
compatible = "fsl,imx93-lpuart", "fsl,imx8ulp-lpuart", "fsl,imx7ulp-lpuart";
reg = <0x42690000 0x1000>;
@@ -755,7 +868,7 @@
interrupts = <GIC_SPI 211 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clk IMX93_CLK_LPUART8_GATE>;
clock-names = "ipg";
- dmas = <&edma2 90 0 1>, <&edma2 89 0 0>;
+ dmas = <&edma2 90 0 1>, <&edma2 89 0 0>;
dma-names = "rx", "tx";
status = "disabled";
};
@@ -874,7 +987,7 @@
<&clk IMX93_CLK_USDHC1_GATE>;
clock-names = "ipg", "ahb", "per";
bus-width = <8>;
- fsl,tuning-start-tap = <20>;
+ fsl,tuning-start-tap = <1>;
fsl,tuning-step = <2>;
status = "disabled";
};
@@ -888,7 +1001,7 @@
<&clk IMX93_CLK_USDHC2_GATE>;
clock-names = "ipg", "ahb", "per";
bus-width = <4>;
- fsl,tuning-start-tap = <20>;
+ fsl,tuning-start-tap = <1>;
fsl,tuning-step = <2>;
status = "disabled";
};
@@ -951,7 +1064,7 @@
<&clk IMX93_CLK_USDHC3_GATE>;
clock-names = "ipg", "ahb", "per";
bus-width = <4>;
- fsl,tuning-start-tap = <20>;
+ fsl,tuning-start-tap = <1>;
fsl,tuning-step = <2>;
status = "disabled";
};
diff --git a/dts/upstream/src/arm64/hisilicon/hikey970-pmic.dtsi b/dts/upstream/src/arm64/hisilicon/hikey970-pmic.dtsi
index 970047f..299c4ab 100644
--- a/dts/upstream/src/arm64/hisilicon/hikey970-pmic.dtsi
+++ b/dts/upstream/src/arm64/hisilicon/hikey970-pmic.dtsi
@@ -10,10 +10,9 @@
/ {
spmi: spmi@fff24000 {
compatible = "hisilicon,kirin970-spmi-controller";
+ reg = <0x0 0xfff24000 0x0 0x1000>;
#address-cells = <2>;
#size-cells = <0>;
- status = "okay";
- reg = <0x0 0xfff24000 0x0 0x1000>;
hisilicon,spmi-channel = <2>;
pmic: pmic@0 {
@@ -25,9 +24,6 @@
gpios = <&gpio28 0 0>;
regulators {
- #address-cells = <1>;
- #size-cells = <0>;
-
ldo3: ldo3 { /* HDMI */
regulator-name = "ldo3";
regulator-min-microvolt = <1500000>;
diff --git a/dts/upstream/src/arm64/intel/socfpga_agilex.dtsi b/dts/upstream/src/arm64/intel/socfpga_agilex.dtsi
index d3adb6a..76aafa1 100644
--- a/dts/upstream/src/arm64/intel/socfpga_agilex.dtsi
+++ b/dts/upstream/src/arm64/intel/socfpga_agilex.dtsi
@@ -60,6 +60,25 @@
};
};
+ firmware {
+ svc {
+ compatible = "intel,agilex-svc";
+ method = "smc";
+ memory-region = <&service_reserved>;
+
+ fpga_mgr: fpga-mgr {
+ compatible = "intel,agilex-soc-fpga-mgr";
+ };
+ };
+ };
+
+ fpga-region {
+ compatible = "fpga-region";
+ #address-cells = <0x2>;
+ #size-cells = <0x2>;
+ fpga-mgr = <&fpga_mgr>;
+ };
+
pmu {
compatible = "arm,armv8-pmuv3";
interrupts = <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
@@ -130,7 +149,7 @@
compatible = "usb-nop-xceiv";
};
- soc {
+ soc@0 {
#address-cells = <1>;
#size-cells = <1>;
compatible = "simple-bus";
@@ -138,13 +157,6 @@
interrupt-parent = <&intc>;
ranges = <0 0 0 0xffffffff>;
- base_fpga_region {
- #address-cells = <0x2>;
- #size-cells = <0x2>;
- compatible = "fpga-region";
- fpga-mgr = <&fpga_mgr>;
- };
-
clkmgr: clock-controller@ffd10000 {
compatible = "intel,agilex-clkmgr";
reg = <0xffd10000 0x1000>;
@@ -368,7 +380,7 @@
pinctrl-single,function-mask = <0x0000000f>;
};
- pinctrl1: pinconf@ffd13100 {
+ pinctrl1: pinctrl@ffd13100 {
compatible = "pinctrl-single";
#pinctrl-cells = <1>;
reg = <0xffd13100 0x20>;
@@ -659,17 +671,5 @@
status = "disabled";
};
-
- firmware {
- svc {
- compatible = "intel,agilex-svc";
- method = "smc";
- memory-region = <&service_reserved>;
-
- fpga_mgr: fpga-mgr {
- compatible = "intel,agilex-soc-fpga-mgr";
- };
- };
- };
};
};
diff --git a/dts/upstream/src/arm64/intel/socfpga_agilex5.dtsi b/dts/upstream/src/arm64/intel/socfpga_agilex5.dtsi
index dcdaf70..d66d425 100644
--- a/dts/upstream/src/arm64/intel/socfpga_agilex5.dtsi
+++ b/dts/upstream/src/arm64/intel/socfpga_agilex5.dtsi
@@ -73,7 +73,7 @@
ranges;
#interrupt-cells = <3>;
#address-cells = <2>;
- #size-cells =<2>;
+ #size-cells = <2>;
interrupt-controller;
#redistributor-regions = <1>;
redistributor-stride = <0x0 0x20000>;
@@ -315,7 +315,7 @@
num-cs = <4>;
clocks = <&clkmgr AGILEX5_L4_MAIN_CLK>;
dmas = <&dmac0 2>, <&dmac0 3>;
- dma-names ="tx", "rx";
+ dma-names = "tx", "rx";
status = "disabled";
};
diff --git a/dts/upstream/src/arm64/intel/socfpga_agilex_n6000.dts b/dts/upstream/src/arm64/intel/socfpga_agilex_n6000.dts
index 1a32840..d22de06 100644
--- a/dts/upstream/src/arm64/intel/socfpga_agilex_n6000.dts
+++ b/dts/upstream/src/arm64/intel/socfpga_agilex_n6000.dts
@@ -26,7 +26,7 @@
reg = <0 0x80000000 0 0>;
};
- soc {
+ soc@0 {
bus@80000000 {
compatible = "simple-bus";
reg = <0x80000000 0x60000000>,
diff --git a/dts/upstream/src/arm64/intel/socfpga_agilex_socdk.dts b/dts/upstream/src/arm64/intel/socfpga_agilex_socdk.dts
index 0536906..ad99aef 100644
--- a/dts/upstream/src/arm64/intel/socfpga_agilex_socdk.dts
+++ b/dts/upstream/src/arm64/intel/socfpga_agilex_socdk.dts
@@ -113,8 +113,6 @@
spi-max-frequency = <100000000>;
m25p,fast-read;
- cdns,page-size = <256>;
- cdns,block-size = <16>;
cdns,read-delay = <2>;
cdns,tshsl-ns = <50>;
cdns,tsd2d-ns = <50>;
diff --git a/dts/upstream/src/arm64/intel/socfpga_n5x_socdk.dts b/dts/upstream/src/arm64/intel/socfpga_n5x_socdk.dts
index 5ddfdff..2d70a92 100644
--- a/dts/upstream/src/arm64/intel/socfpga_n5x_socdk.dts
+++ b/dts/upstream/src/arm64/intel/socfpga_n5x_socdk.dts
@@ -25,12 +25,11 @@
reg = <0 0x80000000 0 0>;
};
- soc {
+ soc@0 {
sdram_edac: memory-controller@f87f8000 {
compatible = "snps,ddrc-3.80a";
reg = <0xf87f8000 0x400>;
interrupts = <0 175 4>;
- status = "okay";
};
};
};
@@ -91,8 +90,6 @@
spi-max-frequency = <100000000>;
m25p,fast-read;
- cdns,page-size = <256>;
- cdns,block-size = <16>;
cdns,read-delay = <2>;
cdns,tshsl-ns = <50>;
cdns,tsd2d-ns = <50>;
diff --git a/dts/upstream/src/arm64/lg/lg1312.dtsi b/dts/upstream/src/arm64/lg/lg1312.dtsi
index 48ec4eb..b864ffa 100644
--- a/dts/upstream/src/arm64/lg/lg1312.dtsi
+++ b/dts/upstream/src/arm64/lg/lg1312.dtsi
@@ -126,7 +126,6 @@
amba {
#address-cells = <2>;
#size-cells = <1>;
- #interrupt-cells = <3>;
compatible = "simple-bus";
interrupt-parent = <&gic>;
diff --git a/dts/upstream/src/arm64/lg/lg1313.dtsi b/dts/upstream/src/arm64/lg/lg1313.dtsi
index 3869460..996fb39 100644
--- a/dts/upstream/src/arm64/lg/lg1313.dtsi
+++ b/dts/upstream/src/arm64/lg/lg1313.dtsi
@@ -126,7 +126,6 @@
amba {
#address-cells = <2>;
#size-cells = <1>;
- #interrupt-cells = <3>;
compatible = "simple-bus";
interrupt-parent = <&gic>;
diff --git a/dts/upstream/src/arm64/marvell/ac5x-rd-carrier-cn9131.dts b/dts/upstream/src/arm64/marvell/ac5x-rd-carrier-cn9131.dts
new file mode 100644
index 0000000..2a0b070
--- /dev/null
+++ b/dts/upstream/src/arm64/marvell/ac5x-rd-carrier-cn9131.dts
@@ -0,0 +1,44 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (C) 2023 Marvell International Ltd.
+ *
+ * Device tree for the AC5X RD Type 7 Com Express carrier board,
+ * Utilizing the CN913x COM Express CPU module board.
+ * This specific carrier board in this mode of operation (external)
+ * only maintains a PCIe link with the CPU module,
+ * which does not require any special DTS definitions.
+ *
+ * AC5X RD works here in external mode (switch selectable at the back of the
+ * board), and connect via an external cable a kit
+ * which would allow it to use an external CN9131 CPU COM Express module,
+ * mounted on top of an interposer kit.
+ *
+ * So in this case, once the switch is set to external mode as explained above,
+ * the AC5X RD becomes part of the carrier solution.
+ *
+ * When the board boots in the external CPU mode, the internal CPU is disabled,
+ * and only the switch portion of the SOC acts as a PCIe end-point, Hence there
+ * is no need to describe this internal (disabled CPU) in the device tree.
+ *
+ * There is no CPU booting in this mode on the carrier, only on the
+ * CN9131 COM Express CPU module.
+ * What runs the Linux is the CN9131 on the COM Express CPU module,
+ * And it accesses the switch end-point on the AC5X RD portion of the carrier
+ * via PCIe.
+ */
+
+#include "cn9131-db-comexpress.dtsi"
+#include "ac5x-rd-carrier.dtsi"
+
+/ {
+ model = "Marvell Armada AC5X RD COM EXPRESS type 7 carrier board with CN9131 CPU module";
+ compatible = "marvell,cn9131-ac5x-carrier", "marvell,rd-ac5x-carrier",
+ "marvell,cn9131-cpu-module", "marvell,cn9131",
+ "marvell,armada-ap807-quad", "marvell,armada-ap807";
+
+ memory@0 {
+ device_type = "memory";
+ reg = <0x0 0x0 0x2 0x00000000>;
+ };
+
+};
diff --git a/dts/upstream/src/arm64/marvell/ac5x-rd-carrier.dtsi b/dts/upstream/src/arm64/marvell/ac5x-rd-carrier.dtsi
new file mode 100644
index 0000000..f98629a
--- /dev/null
+++ b/dts/upstream/src/arm64/marvell/ac5x-rd-carrier.dtsi
@@ -0,0 +1,34 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (C) 2023 Marvell International Ltd.
+ *
+ * Device tree for the AC5X RD Type 7 Com Express carrier board,
+ * This specific board in external mode (see below) only maintains
+ * a PCIe link with the COM Express CPU module, which does not
+ * require any special DTS definitions.
+ *
+ * AC5X RD can either work as you would expect, as a complete standalone
+ * box using the internal CPU, or you can move the switch on the back of
+ * the box to "external" mode, and connect via an external cable a kit
+ * which would allow it to use an external CPU COM Express module,
+ * mounted on top of an interposer kit.
+ *
+ * So in this case, once the switch is set to external mode as explained above,
+ * the AC5X RD becomes part of the carrier solution.
+ * This is a development/reference solution, not a full commercial solution,
+ * hence it was designed with the flexibility to be configured in different
+ * modes of operation.
+ *
+ * When the board boots in the external CPU mode, the internal CPU is disabled,
+ * and only the switch portion of the SOC acts as a PCIe end-point, Hence there
+ * is no need to describe this internal (disabled CPU) in the device tree.
+ *
+ * There is no CPU booting in this mode on the carrier,
+ * only on the COM Express CPU module.
+ */
+
+/ {
+ model = "Marvell Armada AC5X RD COM EXPRESS type 7 carrier board";
+ compatible = "marvell,rd-ac5x-carrier";
+
+};
diff --git a/dts/upstream/src/arm64/marvell/armada-3720-espressobin-ultra.dts b/dts/upstream/src/arm64/marvell/armada-3720-espressobin-ultra.dts
index f9abef8..870bb38 100644
--- a/dts/upstream/src/arm64/marvell/armada-3720-espressobin-ultra.dts
+++ b/dts/upstream/src/arm64/marvell/armada-3720-espressobin-ultra.dts
@@ -126,32 +126,32 @@
reset-gpios = <&gpiosb 23 GPIO_ACTIVE_LOW>;
- ports {
- switch0port1: port@1 {
+ ethernet-ports {
+ switch0port1: ethernet-port@1 {
reg = <1>;
label = "lan0";
phy-handle = <&switch0phy0>;
};
- switch0port2: port@2 {
+ switch0port2: ethernet-port@2 {
reg = <2>;
label = "lan1";
phy-handle = <&switch0phy1>;
};
- switch0port3: port@3 {
+ switch0port3: ethernet-port@3 {
reg = <3>;
label = "lan2";
phy-handle = <&switch0phy2>;
};
- switch0port4: port@4 {
+ switch0port4: ethernet-port@4 {
reg = <4>;
label = "lan3";
phy-handle = <&switch0phy3>;
};
- switch0port5: port@5 {
+ switch0port5: ethernet-port@5 {
reg = <5>;
label = "wan";
phy-handle = <&extphy>;
@@ -160,7 +160,7 @@
};
mdio {
- switch0phy3: switch0phy3@14 {
+ switch0phy3: ethernet-phy@14 {
reg = <0x14>;
};
};
diff --git a/dts/upstream/src/arm64/marvell/armada-3720-espressobin.dtsi b/dts/upstream/src/arm64/marvell/armada-3720-espressobin.dtsi
index 49cbdb5..fed2dce 100644
--- a/dts/upstream/src/arm64/marvell/armada-3720-espressobin.dtsi
+++ b/dts/upstream/src/arm64/marvell/armada-3720-espressobin.dtsi
@@ -145,19 +145,17 @@
};
&mdio {
- switch0: switch0@1 {
+ switch0: ethernet-switch@1 {
compatible = "marvell,mv88e6085";
- #address-cells = <1>;
- #size-cells = <0>;
reg = <1>;
dsa,member = <0 0>;
- ports {
+ ethernet-ports {
#address-cells = <1>;
#size-cells = <0>;
- switch0port0: port@0 {
+ switch0port0: ethernet-port@0 {
reg = <0>;
label = "cpu";
ethernet = <ð0>;
@@ -168,19 +166,19 @@
};
};
- switch0port1: port@1 {
+ switch0port1: ethernet-port@1 {
reg = <1>;
label = "wan";
phy-handle = <&switch0phy0>;
};
- switch0port2: port@2 {
+ switch0port2: ethernet-port@2 {
reg = <2>;
label = "lan0";
phy-handle = <&switch0phy1>;
};
- switch0port3: port@3 {
+ switch0port3: ethernet-port@3 {
reg = <3>;
label = "lan1";
phy-handle = <&switch0phy2>;
@@ -192,13 +190,13 @@
#address-cells = <1>;
#size-cells = <0>;
- switch0phy0: switch0phy0@11 {
+ switch0phy0: ethernet-phy@11 {
reg = <0x11>;
};
- switch0phy1: switch0phy1@12 {
+ switch0phy1: ethernet-phy@12 {
reg = <0x12>;
};
- switch0phy2: switch0phy2@13 {
+ switch0phy2: ethernet-phy@13 {
reg = <0x13>;
};
};
diff --git a/dts/upstream/src/arm64/marvell/armada-3720-gl-mv1000.dts b/dts/upstream/src/arm64/marvell/armada-3720-gl-mv1000.dts
index b1b45b4..63fbc83 100644
--- a/dts/upstream/src/arm64/marvell/armada-3720-gl-mv1000.dts
+++ b/dts/upstream/src/arm64/marvell/armada-3720-gl-mv1000.dts
@@ -152,31 +152,29 @@
};
&mdio {
- switch0: switch0@1 {
+ switch0: ethernet-switch@1 {
compatible = "marvell,mv88e6085";
- #address-cells = <1>;
- #size-cells = <0>;
reg = <1>;
dsa,member = <0 0>;
- ports: ports {
+ ports: ethernet-ports {
#address-cells = <1>;
#size-cells = <0>;
- port@0 {
+ ethernet-port@0 {
reg = <0>;
label = "cpu";
ethernet = <ð0>;
};
- port@1 {
+ ethernet-port@1 {
reg = <1>;
label = "wan";
phy-handle = <&switch0phy0>;
};
- port@2 {
+ ethernet-port@2 {
reg = <2>;
label = "lan0";
phy-handle = <&switch0phy1>;
@@ -185,7 +183,7 @@
nvmem-cell-names = "mac-address";
};
- port@3 {
+ ethernet-port@3 {
reg = <3>;
label = "lan1";
phy-handle = <&switch0phy2>;
@@ -199,13 +197,13 @@
#address-cells = <1>;
#size-cells = <0>;
- switch0phy0: switch0phy0@11 {
+ switch0phy0: ethernet-phy@11 {
reg = <0x11>;
};
- switch0phy1: switch0phy1@12 {
+ switch0phy1: ethernet-phy@12 {
reg = <0x12>;
};
- switch0phy2: switch0phy2@13 {
+ switch0phy2: ethernet-phy@13 {
reg = <0x13>;
};
};
diff --git a/dts/upstream/src/arm64/marvell/armada-3720-turris-mox.dts b/dts/upstream/src/arm64/marvell/armada-3720-turris-mox.dts
index 9eab2bb..f1a9f22 100644
--- a/dts/upstream/src/arm64/marvell/armada-3720-turris-mox.dts
+++ b/dts/upstream/src/arm64/marvell/armada-3720-turris-mox.dts
@@ -130,7 +130,7 @@
compatible = "microchip,mcp7940x";
reg = <0x6f>;
interrupt-parent = <&gpiosb>;
- interrupts = <5 0>; /* GPIO2_5 */
+ interrupts = <5 IRQ_TYPE_EDGE_FALLING>; /* GPIO2_5 */
};
};
@@ -304,9 +304,15 @@
reg = <1>;
};
- /* switch nodes are enabled by U-Boot if modules are present */
+ /*
+ * NOTE: switch nodes are enabled by U-Boot if modules are present
+ * DO NOT change this node name (switch0@10) even if it is not following
+ * conventions! Deployed U-Boot binaries are explicitly looking for
+ * this node in order to augment the device tree!
+ * Also do not touch the "ports" or "port@n" nodes. These are also ABI.
+ */
switch0@10 {
- compatible = "marvell,mv88e6190";
+ compatible = "marvell,turris-mox-mv88e6190", "marvell,mv88e6190";
reg = <0x10>;
dsa,member = <0 0>;
interrupt-parent = <&moxtet>;
@@ -317,35 +323,35 @@
#address-cells = <1>;
#size-cells = <0>;
- switch0phy1: switch0phy1@1 {
+ switch0phy1: ethernet-phy@1 {
reg = <0x1>;
};
- switch0phy2: switch0phy2@2 {
+ switch0phy2: ethernet-phy@2 {
reg = <0x2>;
};
- switch0phy3: switch0phy3@3 {
+ switch0phy3: ethernet-phy@3 {
reg = <0x3>;
};
- switch0phy4: switch0phy4@4 {
+ switch0phy4: ethernet-phy@4 {
reg = <0x4>;
};
- switch0phy5: switch0phy5@5 {
+ switch0phy5: ethernet-phy@5 {
reg = <0x5>;
};
- switch0phy6: switch0phy6@6 {
+ switch0phy6: ethernet-phy@6 {
reg = <0x6>;
};
- switch0phy7: switch0phy7@7 {
+ switch0phy7: ethernet-phy@7 {
reg = <0x7>;
};
- switch0phy8: switch0phy8@8 {
+ switch0phy8: ethernet-phy@8 {
reg = <0x8>;
};
};
@@ -430,8 +436,9 @@
};
};
+ /* NOTE: this node name is ABI, don't change it! */
switch0@2 {
- compatible = "marvell,mv88e6085";
+ compatible = "marvell,turris-mox-mv88e6085", "marvell,mv88e6085";
reg = <0x2>;
dsa,member = <0 0>;
interrupt-parent = <&moxtet>;
@@ -442,19 +449,19 @@
#address-cells = <1>;
#size-cells = <0>;
- switch0phy1_topaz: switch0phy1@11 {
+ switch0phy1_topaz: ethernet-phy@11 {
reg = <0x11>;
};
- switch0phy2_topaz: switch0phy2@12 {
+ switch0phy2_topaz: ethernet-phy@12 {
reg = <0x12>;
};
- switch0phy3_topaz: switch0phy3@13 {
+ switch0phy3_topaz: ethernet-phy@13 {
reg = <0x13>;
};
- switch0phy4_topaz: switch0phy4@14 {
+ switch0phy4_topaz: ethernet-phy@14 {
reg = <0x14>;
};
};
@@ -497,8 +504,9 @@
};
};
+ /* NOTE: this node name is ABI, don't change it! */
switch1@11 {
- compatible = "marvell,mv88e6190";
+ compatible = "marvell,turris-mox-mv88e6190", "marvell,mv88e6190";
reg = <0x11>;
dsa,member = <0 1>;
interrupt-parent = <&moxtet>;
@@ -509,35 +517,35 @@
#address-cells = <1>;
#size-cells = <0>;
- switch1phy1: switch1phy1@1 {
+ switch1phy1: ethernet-phy@1 {
reg = <0x1>;
};
- switch1phy2: switch1phy2@2 {
+ switch1phy2: ethernet-phy@2 {
reg = <0x2>;
};
- switch1phy3: switch1phy3@3 {
+ switch1phy3: ethernet-phy@3 {
reg = <0x3>;
};
- switch1phy4: switch1phy4@4 {
+ switch1phy4: ethernet-phy@4 {
reg = <0x4>;
};
- switch1phy5: switch1phy5@5 {
+ switch1phy5: ethernet-phy@5 {
reg = <0x5>;
};
- switch1phy6: switch1phy6@6 {
+ switch1phy6: ethernet-phy@6 {
reg = <0x6>;
};
- switch1phy7: switch1phy7@7 {
+ switch1phy7: ethernet-phy@7 {
reg = <0x7>;
};
- switch1phy8: switch1phy8@8 {
+ switch1phy8: ethernet-phy@8 {
reg = <0x8>;
};
};
@@ -622,8 +630,9 @@
};
};
+ /* NOTE: this node name is ABI, don't change it! */
switch1@2 {
- compatible = "marvell,mv88e6085";
+ compatible = "marvell,turris-mox-mv88e6085", "marvell,mv88e6085";
reg = <0x2>;
dsa,member = <0 1>;
interrupt-parent = <&moxtet>;
@@ -634,19 +643,19 @@
#address-cells = <1>;
#size-cells = <0>;
- switch1phy1_topaz: switch1phy1@11 {
+ switch1phy1_topaz: ethernet-phy@11 {
reg = <0x11>;
};
- switch1phy2_topaz: switch1phy2@12 {
+ switch1phy2_topaz: ethernet-phy@12 {
reg = <0x12>;
};
- switch1phy3_topaz: switch1phy3@13 {
+ switch1phy3_topaz: ethernet-phy@13 {
reg = <0x13>;
};
- switch1phy4_topaz: switch1phy4@14 {
+ switch1phy4_topaz: ethernet-phy@14 {
reg = <0x14>;
};
};
@@ -689,8 +698,9 @@
};
};
+ /* NOTE: this node name is ABI, don't change it! */
switch2@12 {
- compatible = "marvell,mv88e6190";
+ compatible = "marvell,turris-mox-mv88e6190", "marvell,mv88e6190";
reg = <0x12>;
dsa,member = <0 2>;
interrupt-parent = <&moxtet>;
@@ -701,35 +711,35 @@
#address-cells = <1>;
#size-cells = <0>;
- switch2phy1: switch2phy1@1 {
+ switch2phy1: ethernet-phy@1 {
reg = <0x1>;
};
- switch2phy2: switch2phy2@2 {
+ switch2phy2: ethernet-phy@2 {
reg = <0x2>;
};
- switch2phy3: switch2phy3@3 {
+ switch2phy3: ethernet-phy@3 {
reg = <0x3>;
};
- switch2phy4: switch2phy4@4 {
+ switch2phy4: ethernet-phy@4 {
reg = <0x4>;
};
- switch2phy5: switch2phy5@5 {
+ switch2phy5: ethernet-phy@5 {
reg = <0x5>;
};
- switch2phy6: switch2phy6@6 {
+ switch2phy6: ethernet-phy@6 {
reg = <0x6>;
};
- switch2phy7: switch2phy7@7 {
+ switch2phy7: ethernet-phy@7 {
reg = <0x7>;
};
- switch2phy8: switch2phy8@8 {
+ switch2phy8: ethernet-phy@8 {
reg = <0x8>;
};
};
@@ -805,8 +815,9 @@
};
};
+ /* NOTE: this node name is ABI, don't change it! */
switch2@2 {
- compatible = "marvell,mv88e6085";
+ compatible = "marvell,turris-mox-mv88e6085", "marvell,mv88e6085";
reg = <0x2>;
dsa,member = <0 2>;
interrupt-parent = <&moxtet>;
@@ -817,19 +828,19 @@
#address-cells = <1>;
#size-cells = <0>;
- switch2phy1_topaz: switch2phy1@11 {
+ switch2phy1_topaz: ethernet-phy@11 {
reg = <0x11>;
};
- switch2phy2_topaz: switch2phy2@12 {
+ switch2phy2_topaz: ethernet-phy@12 {
reg = <0x12>;
};
- switch2phy3_topaz: switch2phy3@13 {
+ switch2phy3_topaz: ethernet-phy@13 {
reg = <0x13>;
};
- switch2phy4_topaz: switch2phy4@14 {
+ switch2phy4_topaz: ethernet-phy@14 {
reg = <0x14>;
};
};
diff --git a/dts/upstream/src/arm64/marvell/armada-7040-mochabin.dts b/dts/upstream/src/arm64/marvell/armada-7040-mochabin.dts
index 4820281..40b7ee7 100644
--- a/dts/upstream/src/arm64/marvell/armada-7040-mochabin.dts
+++ b/dts/upstream/src/arm64/marvell/armada-7040-mochabin.dts
@@ -301,10 +301,8 @@
};
/* 88E6141 Topaz switch */
- switch: switch@3 {
+ switch: ethernet-switch@3 {
compatible = "marvell,mv88e6085";
- #address-cells = <1>;
- #size-cells = <0>;
reg = <3>;
pinctrl-names = "default";
@@ -314,35 +312,35 @@
interrupt-parent = <&cp0_gpio1>;
interrupts = <1 IRQ_TYPE_LEVEL_LOW>;
- ports {
+ ethernet-ports {
#address-cells = <1>;
#size-cells = <0>;
- swport1: port@1 {
+ swport1: ethernet-port@1 {
reg = <1>;
label = "lan0";
phy-handle = <&swphy1>;
};
- swport2: port@2 {
+ swport2: ethernet-port@2 {
reg = <2>;
label = "lan1";
phy-handle = <&swphy2>;
};
- swport3: port@3 {
+ swport3: ethernet-port@3 {
reg = <3>;
label = "lan2";
phy-handle = <&swphy3>;
};
- swport4: port@4 {
+ swport4: ethernet-port@4 {
reg = <4>;
label = "lan3";
phy-handle = <&swphy4>;
};
- port@5 {
+ ethernet-port@5 {
reg = <5>;
label = "cpu";
ethernet = <&cp0_eth1>;
@@ -355,19 +353,19 @@
#address-cells = <1>;
#size-cells = <0>;
- swphy1: swphy1@17 {
+ swphy1: ethernet-phy@17 {
reg = <17>;
};
- swphy2: swphy2@18 {
+ swphy2: ethernet-phy@18 {
reg = <18>;
};
- swphy3: swphy3@19 {
+ swphy3: ethernet-phy@19 {
reg = <19>;
};
- swphy4: swphy4@20 {
+ swphy4: ethernet-phy@20 {
reg = <20>;
};
};
diff --git a/dts/upstream/src/arm64/marvell/armada-8040-clearfog-gt-8k.dts b/dts/upstream/src/arm64/marvell/armada-8040-clearfog-gt-8k.dts
index 4125202..67892f0 100644
--- a/dts/upstream/src/arm64/marvell/armada-8040-clearfog-gt-8k.dts
+++ b/dts/upstream/src/arm64/marvell/armada-8040-clearfog-gt-8k.dts
@@ -497,42 +497,42 @@
reset-deassert-us = <10000>;
};
- switch0: switch0@4 {
+ switch0: ethernet-switch@4 {
compatible = "marvell,mv88e6085";
reg = <4>;
pinctrl-names = "default";
pinctrl-0 = <&cp1_switch_reset_pins>;
reset-gpios = <&cp1_gpio1 24 GPIO_ACTIVE_LOW>;
- ports {
+ ethernet-ports {
#address-cells = <1>;
#size-cells = <0>;
- port@1 {
+ ethernet-port@1 {
reg = <1>;
label = "lan2";
phy-handle = <&switch0phy0>;
};
- port@2 {
+ ethernet-port@2 {
reg = <2>;
label = "lan1";
phy-handle = <&switch0phy1>;
};
- port@3 {
+ ethernet-port@3 {
reg = <3>;
label = "lan4";
phy-handle = <&switch0phy2>;
};
- port@4 {
+ ethernet-port@4 {
reg = <4>;
label = "lan3";
phy-handle = <&switch0phy3>;
};
- port@5 {
+ ethernet-port@5 {
reg = <5>;
label = "cpu";
ethernet = <&cp1_eth2>;
@@ -545,19 +545,19 @@
#address-cells = <1>;
#size-cells = <0>;
- switch0phy0: switch0phy0@11 {
+ switch0phy0: ethernet-phy@11 {
reg = <0x11>;
};
- switch0phy1: switch0phy1@12 {
+ switch0phy1: ethernet-phy@12 {
reg = <0x12>;
};
- switch0phy2: switch0phy2@13 {
+ switch0phy2: ethernet-phy@13 {
reg = <0x13>;
};
- switch0phy3: switch0phy3@14 {
+ switch0phy3: ethernet-phy@14 {
reg = <0x14>;
};
};
diff --git a/dts/upstream/src/arm64/marvell/armada-ap80x.dtsi b/dts/upstream/src/arm64/marvell/armada-ap80x.dtsi
index 2c920e2..7ec7c78 100644
--- a/dts/upstream/src/arm64/marvell/armada-ap80x.dtsi
+++ b/dts/upstream/src/arm64/marvell/armada-ap80x.dtsi
@@ -138,7 +138,6 @@
odmi: odmi@300000 {
compatible = "marvell,odmi-controller";
- interrupt-controller;
msi-controller;
marvell,odmi-frames = <4>;
reg = <0x300000 0x4000>,
diff --git a/dts/upstream/src/arm64/marvell/cn9130-crb.dtsi b/dts/upstream/src/arm64/marvell/cn9130-crb.dtsi
index 47d45ff..6fcc34f 100644
--- a/dts/upstream/src/arm64/marvell/cn9130-crb.dtsi
+++ b/dts/upstream/src/arm64/marvell/cn9130-crb.dtsi
@@ -207,11 +207,9 @@
reg = <0>;
};
- switch6: switch0@6 {
+ switch6: ethernet-switch@6 {
/* Actual device is MV88E6393X */
compatible = "marvell,mv88e6190";
- #address-cells = <1>;
- #size-cells = <0>;
reg = <6>;
interrupt-parent = <&cp0_gpio1>;
interrupts = <28 IRQ_TYPE_LEVEL_LOW>;
@@ -220,59 +218,59 @@
dsa,member = <0 0>;
- ports {
+ ethernet-ports {
#address-cells = <1>;
#size-cells = <0>;
- port@1 {
+ ethernet-port@1 {
reg = <1>;
label = "p1";
phy-handle = <&switch0phy1>;
};
- port@2 {
+ ethernet-port@2 {
reg = <2>;
label = "p2";
phy-handle = <&switch0phy2>;
};
- port@3 {
+ ethernet-port@3 {
reg = <3>;
label = "p3";
phy-handle = <&switch0phy3>;
};
- port@4 {
+ ethernet-port@4 {
reg = <4>;
label = "p4";
phy-handle = <&switch0phy4>;
};
- port@5 {
+ ethernet-port@5 {
reg = <5>;
label = "p5";
phy-handle = <&switch0phy5>;
};
- port@6 {
+ ethernet-port@6 {
reg = <6>;
label = "p6";
phy-handle = <&switch0phy6>;
};
- port@7 {
+ ethernet-port@7 {
reg = <7>;
label = "p7";
phy-handle = <&switch0phy7>;
};
- port@8 {
+ ethernet-port@8 {
reg = <8>;
label = "p8";
phy-handle = <&switch0phy8>;
};
- port@9 {
+ ethernet-port@9 {
reg = <9>;
label = "p9";
phy-mode = "10gbase-r";
@@ -280,7 +278,7 @@
managed = "in-band-status";
};
- port@a {
+ ethernet-port@a {
reg = <10>;
ethernet = <&cp0_eth0>;
phy-mode = "10gbase-r";
@@ -293,35 +291,35 @@
#address-cells = <1>;
#size-cells = <0>;
- switch0phy1: switch0phy1@1 {
+ switch0phy1: ethernet-phy@1 {
reg = <0x1>;
};
- switch0phy2: switch0phy2@2 {
+ switch0phy2: ethernet-phy@2 {
reg = <0x2>;
};
- switch0phy3: switch0phy3@3 {
+ switch0phy3: ethernet-phy@3 {
reg = <0x3>;
};
- switch0phy4: switch0phy4@4 {
+ switch0phy4: ethernet-phy@4 {
reg = <0x4>;
};
- switch0phy5: switch0phy5@5 {
+ switch0phy5: ethernet-phy@5 {
reg = <0x5>;
};
- switch0phy6: switch0phy6@6 {
+ switch0phy6: ethernet-phy@6 {
reg = <0x6>;
};
- switch0phy7: switch0phy7@7 {
+ switch0phy7: ethernet-phy@7 {
reg = <0x7>;
};
- switch0phy8: switch0phy8@8 {
+ switch0phy8: ethernet-phy@8 {
reg = <0x8>;
};
};
diff --git a/dts/upstream/src/arm64/marvell/cn9130-db-comexpress.dtsi b/dts/upstream/src/arm64/marvell/cn9130-db-comexpress.dtsi
new file mode 100644
index 0000000..028496e
--- /dev/null
+++ b/dts/upstream/src/arm64/marvell/cn9130-db-comexpress.dtsi
@@ -0,0 +1,96 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (C) 2023 Marvell International Ltd.
+ *
+ * Device tree for the CN9130-DB Com Express CPU module board.
+ */
+
+#include "cn9130-db.dtsi"
+
+/ {
+ model = "Marvell Armada CN9130-DB COM EXPRESS type 7 CPU module board";
+ compatible = "marvell,cn9130-cpu-module", "marvell,cn9130",
+ "marvell,armada-ap807-quad", "marvell,armada-ap807";
+
+};
+
+&ap0_reg_sd_vccq {
+ regulator-max-microvolt = <1800000>;
+ states = <1800000 0x1 1800000 0x0>;
+ /delete-property/ gpios;
+};
+
+&cp0_reg_usb3_vbus0 {
+ /delete-property/ gpio;
+};
+
+&cp0_reg_usb3_vbus1 {
+ /delete-property/ gpio;
+};
+
+&cp0_reg_sd_vcc {
+ status = "disabled";
+};
+
+&cp0_reg_sd_vccq {
+ status = "disabled";
+};
+
+&cp0_sdhci0 {
+ status = "disabled";
+};
+
+&cp0_eth0 {
+ status = "disabled";
+};
+
+&cp0_eth1 {
+ status = "okay";
+ phy = <&phy0>;
+ phy-mode = "rgmii-id";
+};
+
+&cp0_eth2 {
+ status = "disabled";
+};
+
+&cp0_mdio {
+ status = "okay";
+ pinctrl-0 = <&cp0_ge_mdio_pins>;
+ phy0: ethernet-phy@0 {
+ status = "okay";
+ };
+};
+
+&cp0_syscon0 {
+ cp0_pinctrl: pinctrl {
+ compatible = "marvell,cp115-standalone-pinctrl";
+
+ cp0_ge_mdio_pins: ge-mdio-pins {
+ marvell,pins = "mpp40", "mpp41";
+ marvell,function = "ge";
+ };
+ };
+};
+
+&cp0_sdhci0 {
+ status = "disabled";
+};
+
+&cp0_spi1 {
+ status = "okay";
+};
+
+&cp0_usb3_0 {
+ status = "okay";
+ usb-phy = <&cp0_usb3_0_phy0>;
+ phy-names = "usb";
+ /delete-property/ phys;
+};
+
+&cp0_usb3_1 {
+ status = "okay";
+ usb-phy = <&cp0_usb3_0_phy1>;
+ phy-names = "usb";
+ /delete-property/ phys;
+};
diff --git a/dts/upstream/src/arm64/marvell/cn9131-db-comexpress.dtsi b/dts/upstream/src/arm64/marvell/cn9131-db-comexpress.dtsi
new file mode 100644
index 0000000..6f3914b
--- /dev/null
+++ b/dts/upstream/src/arm64/marvell/cn9131-db-comexpress.dtsi
@@ -0,0 +1,108 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (C) 2023 Marvell International Ltd.
+ *
+ * Device tree for the CN9131-DB Com Express CPU module board.
+ */
+
+#include "cn9131-db.dtsi"
+
+/ {
+ model = "Marvell Armada CN9131-DB COM EXPRESS type 7 CPU module board";
+ compatible = "marvell,cn9131-cpu-module", "marvell,cn9131", "marvell,cn9130",
+ "marvell,armada-ap807-quad", "marvell,armada-ap807";
+
+};
+
+&ap0_reg_sd_vccq {
+ regulator-max-microvolt = <1800000>;
+ states = <1800000 0x1 1800000 0x0>;
+ /delete-property/ gpios;
+};
+
+&cp0_reg_usb3_vbus0 {
+ /delete-property/ gpio;
+};
+
+&cp0_reg_usb3_vbus1 {
+ /delete-property/ gpio;
+};
+
+&cp1_reg_usb3_vbus0 {
+ /delete-property/ gpio;
+};
+
+&cp0_reg_sd_vcc {
+ status = "disabled";
+};
+
+&cp0_reg_sd_vccq {
+ status = "disabled";
+};
+
+&cp0_sdhci0 {
+ status = "disabled";
+};
+
+&cp0_eth0 {
+ status = "disabled";
+};
+
+&cp0_eth1 {
+ status = "okay";
+ phy = <&phy0>;
+ phy-mode = "rgmii-id";
+};
+
+&cp0_eth2 {
+ status = "disabled";
+};
+
+&cp0_mdio {
+ status = "okay";
+ pinctrl-0 = <&cp0_ge_mdio_pins>;
+ phy0: ethernet-phy@0 {
+ status = "okay";
+ };
+};
+
+&cp0_syscon0 {
+ cp0_pinctrl: pinctrl {
+ compatible = "marvell,cp115-standalone-pinctrl";
+
+ cp0_ge_mdio_pins: ge-mdio-pins {
+ marvell,pins = "mpp40", "mpp41";
+ marvell,function = "ge";
+ };
+ };
+};
+
+&cp0_sdhci0 {
+ status = "disabled";
+};
+
+&cp0_spi1 {
+ status = "okay";
+};
+
+&cp0_usb3_0 {
+ status = "okay";
+ usb-phy = <&cp0_usb3_0_phy0>;
+ phy-names = "usb";
+ /delete-property/ phys;
+};
+
+&cp0_usb3_1 {
+ status = "okay";
+ usb-phy = <&cp0_usb3_0_phy1>;
+ phy-names = "usb";
+ /delete-property/ phys;
+};
+
+&cp1_usb3_1 {
+ status = "okay";
+ usb-phy = <&cp1_usb3_0_phy0>;
+ /* Generic PHY, providing serdes lanes */
+ phys = <&cp1_comphy3 1>;
+ phy-names = "usb";
+};
diff --git a/dts/upstream/src/arm64/mediatek/mt6358.dtsi b/dts/upstream/src/arm64/mediatek/mt6358.dtsi
index b605313..a1b9601 100644
--- a/dts/upstream/src/arm64/mediatek/mt6358.dtsi
+++ b/dts/upstream/src/arm64/mediatek/mt6358.dtsi
@@ -8,8 +8,6 @@
pmic: pmic {
compatible = "mediatek,mt6358";
interrupt-controller;
- interrupt-parent = <&pio>;
- interrupts = <182 IRQ_TYPE_LEVEL_HIGH>;
#interrupt-cells = <2>;
mt6358codec: mt6358codec {
@@ -128,7 +126,6 @@
};
mt6358_vrf12_reg: ldo_vrf12 {
- compatible = "regulator-fixed";
regulator-name = "vrf12";
regulator-min-microvolt = <1200000>;
regulator-max-microvolt = <1200000>;
@@ -136,7 +133,6 @@
};
mt6358_vio18_reg: ldo_vio18 {
- compatible = "regulator-fixed";
regulator-name = "vio18";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
@@ -153,7 +149,6 @@
};
mt6358_vcamio_reg: ldo_vcamio {
- compatible = "regulator-fixed";
regulator-name = "vcamio";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
@@ -168,7 +163,6 @@
};
mt6358_vcn18_reg: ldo_vcn18 {
- compatible = "regulator-fixed";
regulator-name = "vcn18";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
@@ -176,7 +170,6 @@
};
mt6358_vfe28_reg: ldo_vfe28 {
- compatible = "regulator-fixed";
regulator-name = "vfe28";
regulator-min-microvolt = <2800000>;
regulator-max-microvolt = <2800000>;
@@ -193,7 +186,6 @@
};
mt6358_vcn28_reg: ldo_vcn28 {
- compatible = "regulator-fixed";
regulator-name = "vcn28";
regulator-min-microvolt = <2800000>;
regulator-max-microvolt = <2800000>;
@@ -218,7 +210,6 @@
};
mt6358_vxo22_reg: ldo_vxo22 {
- compatible = "regulator-fixed";
regulator-name = "vxo22";
regulator-min-microvolt = <2200000>;
regulator-max-microvolt = <2200000>;
@@ -234,7 +225,6 @@
};
mt6358_vaux18_reg: ldo_vaux18 {
- compatible = "regulator-fixed";
regulator-name = "vaux18";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
@@ -249,7 +239,6 @@
};
mt6358_vbif28_reg: ldo_vbif28 {
- compatible = "regulator-fixed";
regulator-name = "vbif28";
regulator-min-microvolt = <2800000>;
regulator-max-microvolt = <2800000>;
@@ -280,7 +269,6 @@
};
mt6358_vio28_reg: ldo_vio28 {
- compatible = "regulator-fixed";
regulator-name = "vio28";
regulator-min-microvolt = <2800000>;
regulator-max-microvolt = <2800000>;
@@ -288,7 +276,6 @@
};
mt6358_va12_reg: ldo_va12 {
- compatible = "regulator-fixed";
regulator-name = "va12";
regulator-min-microvolt = <1200000>;
regulator-max-microvolt = <1200000>;
@@ -297,27 +284,19 @@
};
mt6358_vrf18_reg: ldo_vrf18 {
- compatible = "regulator-fixed";
regulator-name = "vrf18";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
regulator-enable-ramp-delay = <120>;
};
- mt6358_vcn33_bt_reg: ldo_vcn33_bt {
- regulator-name = "vcn33_bt";
+ mt6358_vcn33_reg: ldo_vcn33 {
+ regulator-name = "vcn33";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3500000>;
regulator-enable-ramp-delay = <270>;
};
- mt6358_vcn33_wifi_reg: ldo_vcn33_wifi {
- regulator-name = "vcn33_wifi";
- regulator-min-microvolt = <3300000>;
- regulator-max-microvolt = <3500000>;
- regulator-enable-ramp-delay = <270>;
- };
-
mt6358_vcama2_reg: ldo_vcama2 {
regulator-name = "vcama2";
regulator-min-microvolt = <1800000>;
@@ -340,7 +319,6 @@
};
mt6358_vaud28_reg: ldo_vaud28 {
- compatible = "regulator-fixed";
regulator-name = "vaud28";
regulator-min-microvolt = <2800000>;
regulator-max-microvolt = <2800000>;
diff --git a/dts/upstream/src/arm64/mediatek/mt7622-bananapi-bpi-r64.dts b/dts/upstream/src/arm64/mediatek/mt7622-bananapi-bpi-r64.dts
index c466821..a1f4204 100644
--- a/dts/upstream/src/arm64/mediatek/mt7622-bananapi-bpi-r64.dts
+++ b/dts/upstream/src/arm64/mediatek/mt7622-bananapi-bpi-r64.dts
@@ -153,8 +153,7 @@
reg = <0>;
interrupt-controller;
#interrupt-cells = <1>;
- interrupt-parent = <&pio>;
- interrupts = <53 IRQ_TYPE_LEVEL_HIGH>;
+ interrupts-extended = <&pio 53 IRQ_TYPE_LEVEL_HIGH>;
reset-gpios = <&pio 54 0>;
ports {
diff --git a/dts/upstream/src/arm64/mediatek/mt7986a-bananapi-bpi-r3.dts b/dts/upstream/src/arm64/mediatek/mt7986a-bananapi-bpi-r3.dts
index b876e50..d06d4af 100644
--- a/dts/upstream/src/arm64/mediatek/mt7986a-bananapi-bpi-r3.dts
+++ b/dts/upstream/src/arm64/mediatek/mt7986a-bananapi-bpi-r3.dts
@@ -205,8 +205,7 @@
reg = <31>;
interrupt-controller;
#interrupt-cells = <1>;
- interrupt-parent = <&pio>;
- interrupts = <66 IRQ_TYPE_LEVEL_HIGH>;
+ interrupts-extended = <&pio 66 IRQ_TYPE_LEVEL_HIGH>;
reset-gpios = <&pio 5 GPIO_ACTIVE_HIGH>;
};
};
diff --git a/dts/upstream/src/arm64/mediatek/mt8173-elm-hana.dtsi b/dts/upstream/src/arm64/mediatek/mt8173-elm-hana.dtsi
index bdcd35c..90cbbc1 100644
--- a/dts/upstream/src/arm64/mediatek/mt8173-elm-hana.dtsi
+++ b/dts/upstream/src/arm64/mediatek/mt8173-elm-hana.dtsi
@@ -13,8 +13,7 @@
touchscreen2: touchscreen@34 {
compatible = "melfas,mip4_ts";
reg = <0x34>;
- interrupt-parent = <&pio>;
- interrupts = <88 IRQ_TYPE_LEVEL_LOW>;
+ interrupts-extended = <&pio 88 IRQ_TYPE_LEVEL_LOW>;
};
/*
@@ -26,8 +25,7 @@
compatible = "hid-over-i2c";
reg = <0x20>;
hid-descr-addr = <0x0020>;
- interrupt-parent = <&pio>;
- interrupts = <88 IRQ_TYPE_LEVEL_LOW>;
+ interrupts-extended = <&pio 88 IRQ_TYPE_LEVEL_LOW>;
};
};
@@ -39,8 +37,7 @@
*/
trackpad2: trackpad@2c {
compatible = "hid-over-i2c";
- interrupt-parent = <&pio>;
- interrupts = <117 IRQ_TYPE_LEVEL_LOW>;
+ interrupts-extended = <&pio 117 IRQ_TYPE_LEVEL_LOW>;
reg = <0x2c>;
hid-descr-addr = <0x0020>;
wakeup-source;
diff --git a/dts/upstream/src/arm64/mediatek/mt8173-elm.dtsi b/dts/upstream/src/arm64/mediatek/mt8173-elm.dtsi
index 1114956..8d614ac 100644
--- a/dts/upstream/src/arm64/mediatek/mt8173-elm.dtsi
+++ b/dts/upstream/src/arm64/mediatek/mt8173-elm.dtsi
@@ -245,8 +245,7 @@
reg = <0x1a>;
avdd-supply = <&mt6397_vgp1_reg>;
cpvdd-supply = <&mt6397_vcama_reg>;
- interrupt-parent = <&pio>;
- interrupts = <3 IRQ_TYPE_EDGE_BOTH>;
+ interrupts-extended = <&pio 3 IRQ_TYPE_EDGE_BOTH>;
pinctrl-names = "default";
pinctrl-0 = <&rt5650_irq>;
#sound-dai-cells = <1>;
@@ -308,8 +307,7 @@
da9211: da9211@68 {
compatible = "dlg,da9211";
reg = <0x68>;
- interrupt-parent = <&pio>;
- interrupts = <15 IRQ_TYPE_LEVEL_LOW>;
+ interrupts-extended = <&pio 15 IRQ_TYPE_LEVEL_LOW>;
regulators {
da9211_vcpu_reg: BUCKA {
@@ -353,8 +351,7 @@
touchscreen: touchscreen@10 {
compatible = "elan,ekth3500";
reg = <0x10>;
- interrupt-parent = <&pio>;
- interrupts = <88 IRQ_TYPE_LEVEL_LOW>;
+ interrupts-extended = <&pio 88 IRQ_TYPE_LEVEL_LOW>;
};
};
@@ -366,8 +363,7 @@
trackpad: trackpad@15 {
compatible = "elan,ekth3000";
- interrupt-parent = <&pio>;
- interrupts = <117 IRQ_TYPE_LEVEL_LOW>;
+ interrupts-extended = <&pio 117 IRQ_TYPE_LEVEL_LOW>;
reg = <0x15>;
vcc-supply = <&mt6397_vgp6_reg>;
wakeup-source;
@@ -439,8 +435,7 @@
btmrvl: btmrvl@2 {
compatible = "marvell,sd8897-bt";
reg = <2>;
- interrupt-parent = <&pio>;
- interrupts = <119 IRQ_TYPE_LEVEL_LOW>;
+ interrupts-extended = <&pio 119 IRQ_TYPE_LEVEL_LOW>;
marvell,wakeup-pin = /bits/ 16 <0x0d>;
marvell,wakeup-gap-ms = /bits/ 16 <0x64>;
};
@@ -448,8 +443,7 @@
mwifiex: mwifiex@1 {
compatible = "marvell,sd8897";
reg = <1>;
- interrupt-parent = <&pio>;
- interrupts = <38 IRQ_TYPE_LEVEL_LOW>;
+ interrupts-extended = <&pio 38 IRQ_TYPE_LEVEL_LOW>;
marvell,wakeup-pin = <3>;
};
};
@@ -933,8 +927,7 @@
compatible = "mediatek,mt6397";
#address-cells = <1>;
#size-cells = <1>;
- interrupt-parent = <&pio>;
- interrupts = <11 IRQ_TYPE_LEVEL_HIGH>;
+ interrupts-extended = <&pio 11 IRQ_TYPE_LEVEL_HIGH>;
interrupt-controller;
#interrupt-cells = <2>;
@@ -1160,8 +1153,7 @@
compatible = "google,cros-ec-spi";
reg = <0x0>;
spi-max-frequency = <12000000>;
- interrupt-parent = <&pio>;
- interrupts = <0 IRQ_TYPE_LEVEL_LOW>;
+ interrupts-extended = <&pio 0 IRQ_TYPE_LEVEL_LOW>;
google,cros-ec-spi-msg-delay = <500>;
i2c_tunnel: i2c-tunnel0 {
diff --git a/dts/upstream/src/arm64/mediatek/mt8173-evb.dts b/dts/upstream/src/arm64/mediatek/mt8173-evb.dts
index d258c80..0e5c628 100644
--- a/dts/upstream/src/arm64/mediatek/mt8173-evb.dts
+++ b/dts/upstream/src/arm64/mediatek/mt8173-evb.dts
@@ -303,8 +303,7 @@
pmic: pmic {
compatible = "mediatek,mt6397";
- interrupt-parent = <&pio>;
- interrupts = <11 IRQ_TYPE_LEVEL_HIGH>;
+ interrupts-extended = <&pio 11 IRQ_TYPE_LEVEL_HIGH>;
interrupt-controller;
#interrupt-cells = <2>;
diff --git a/dts/upstream/src/arm64/mediatek/mt8173.dtsi b/dts/upstream/src/arm64/mediatek/mt8173.dtsi
index c47d7d9..cac4cd0 100644
--- a/dts/upstream/src/arm64/mediatek/mt8173.dtsi
+++ b/dts/upstream/src/arm64/mediatek/mt8173.dtsi
@@ -1368,10 +1368,9 @@
#clock-cells = <1>;
};
- vcodec_dec: vcodec@16000000 {
+ vcodec_dec: vcodec@16020000 {
compatible = "mediatek,mt8173-vcodec-dec";
- reg = <0 0x16000000 0 0x100>, /* VDEC_SYS */
- <0 0x16020000 0 0x1000>, /* VDEC_MISC */
+ reg = <0 0x16020000 0 0x1000>, /* VDEC_MISC */
<0 0x16021000 0 0x800>, /* VDEC_LD */
<0 0x16021800 0 0x800>, /* VDEC_TOP */
<0 0x16022000 0 0x1000>, /* VDEC_CM */
@@ -1382,6 +1381,8 @@
<0 0x16027000 0 0x800>, /* VDEC_HWQ */
<0 0x16027800 0 0x800>, /* VDEC_HWB */
<0 0x16028400 0 0x400>; /* VDEC_HWG */
+ reg-names = "misc", "ld", "top", "cm", "ad", "av", "pp",
+ "hwd", "hwq", "hwb", "hwg";
interrupts = <GIC_SPI 204 IRQ_TYPE_LEVEL_LOW>;
iommus = <&iommu M4U_PORT_HW_VDEC_MC_EXT>,
<&iommu M4U_PORT_HW_VDEC_PP_EXT>,
@@ -1392,6 +1393,7 @@
<&iommu M4U_PORT_HW_VDEC_VLD_EXT>,
<&iommu M4U_PORT_HW_VDEC_VLD2_EXT>;
mediatek,vpu = <&vpu>;
+ mediatek,vdecsys = <&vdecsys>;
power-domains = <&spm MT8173_POWER_DOMAIN_VDEC>;
clocks = <&apmixedsys CLK_APMIXED_VCODECPLL>,
<&topckgen CLK_TOP_UNIVPLL_D2>,
diff --git a/dts/upstream/src/arm64/mediatek/mt8183-evb.dts b/dts/upstream/src/arm64/mediatek/mt8183-evb.dts
index 77f9ab9..681dedd 100644
--- a/dts/upstream/src/arm64/mediatek/mt8183-evb.dts
+++ b/dts/upstream/src/arm64/mediatek/mt8183-evb.dts
@@ -381,6 +381,10 @@
};
};
+&pmic {
+ interrupts-extended = <&pio 182 IRQ_TYPE_LEVEL_HIGH>;
+};
+
&mfg {
domain-supply = <&mt6358_vgpu_reg>;
};
diff --git a/dts/upstream/src/arm64/mediatek/mt8183-kukui-audio-da7219.dtsi b/dts/upstream/src/arm64/mediatek/mt8183-kukui-audio-da7219.dtsi
index 2c69e76..8b57706 100644
--- a/dts/upstream/src/arm64/mediatek/mt8183-kukui-audio-da7219.dtsi
+++ b/dts/upstream/src/arm64/mediatek/mt8183-kukui-audio-da7219.dtsi
@@ -11,8 +11,7 @@
pinctrl-0 = <&da7219_pins>;
compatible = "dlg,da7219";
reg = <0x1a>;
- interrupt-parent = <&pio>;
- interrupts = <165 IRQ_TYPE_LEVEL_LOW 165 0>;
+ interrupts-extended = <&pio 165 IRQ_TYPE_LEVEL_LOW>;
dlg,micbias-lvl = <2600>;
dlg,mic-amp-in-sel = "diff";
diff --git a/dts/upstream/src/arm64/mediatek/mt8183-kukui-audio-ts3a227e.dtsi b/dts/upstream/src/arm64/mediatek/mt8183-kukui-audio-ts3a227e.dtsi
index 0799c48..548e22c 100644
--- a/dts/upstream/src/arm64/mediatek/mt8183-kukui-audio-ts3a227e.dtsi
+++ b/dts/upstream/src/arm64/mediatek/mt8183-kukui-audio-ts3a227e.dtsi
@@ -11,8 +11,7 @@
pinctrl-0 = <&ts3a227e_pins>;
compatible = "ti,ts3a227e";
reg = <0x3b>;
- interrupt-parent = <&pio>;
- interrupts = <157 IRQ_TYPE_LEVEL_LOW>;
+ interrupts-extended = <&pio 157 IRQ_TYPE_LEVEL_LOW>;
status = "okay";
};
};
diff --git a/dts/upstream/src/arm64/mediatek/mt8183-kukui-jacuzzi-damu.dts b/dts/upstream/src/arm64/mediatek/mt8183-kukui-jacuzzi-damu.dts
index 552bfc7..0b45aee 100644
--- a/dts/upstream/src/arm64/mediatek/mt8183-kukui-jacuzzi-damu.dts
+++ b/dts/upstream/src/arm64/mediatek/mt8183-kukui-jacuzzi-damu.dts
@@ -18,8 +18,7 @@
compatible = "hid-over-i2c";
reg = <0x10>;
- interrupt-parent = <&pio>;
- interrupts = <155 IRQ_TYPE_LEVEL_LOW>;
+ interrupts-extended = <&pio 155 IRQ_TYPE_LEVEL_LOW>;
pinctrl-names = "default";
pinctrl-0 = <&touchscreen_pins>;
diff --git a/dts/upstream/src/arm64/mediatek/mt8183-kukui-jacuzzi-fennel-sku1.dts b/dts/upstream/src/arm64/mediatek/mt8183-kukui-jacuzzi-fennel-sku1.dts
index 77b96dd..b595622 100644
--- a/dts/upstream/src/arm64/mediatek/mt8183-kukui-jacuzzi-fennel-sku1.dts
+++ b/dts/upstream/src/arm64/mediatek/mt8183-kukui-jacuzzi-fennel-sku1.dts
@@ -30,8 +30,7 @@
compatible = "hid-over-i2c";
reg = <0x10>;
- interrupt-parent = <&pio>;
- interrupts = <155 IRQ_TYPE_LEVEL_LOW>;
+ interrupts-extended = <&pio 155 IRQ_TYPE_LEVEL_LOW>;
pinctrl-names = "default";
pinctrl-0 = <&touchscreen_pins>;
diff --git a/dts/upstream/src/arm64/mediatek/mt8183-kukui-jacuzzi-fennel-sku6.dts b/dts/upstream/src/arm64/mediatek/mt8183-kukui-jacuzzi-fennel-sku6.dts
index 37e6e58..5a1c393 100644
--- a/dts/upstream/src/arm64/mediatek/mt8183-kukui-jacuzzi-fennel-sku6.dts
+++ b/dts/upstream/src/arm64/mediatek/mt8183-kukui-jacuzzi-fennel-sku6.dts
@@ -17,8 +17,7 @@
compatible = "hid-over-i2c";
reg = <0x10>;
- interrupt-parent = <&pio>;
- interrupts = <155 IRQ_TYPE_LEVEL_LOW>;
+ interrupts-extended = <&pio 155 IRQ_TYPE_LEVEL_LOW>;
pinctrl-names = "default";
pinctrl-0 = <&touchscreen_pins>;
diff --git a/dts/upstream/src/arm64/mediatek/mt8183-kukui-jacuzzi-fennel-sku7.dts b/dts/upstream/src/arm64/mediatek/mt8183-kukui-jacuzzi-fennel-sku7.dts
index 0e09604..3ea4fdb 100644
--- a/dts/upstream/src/arm64/mediatek/mt8183-kukui-jacuzzi-fennel-sku7.dts
+++ b/dts/upstream/src/arm64/mediatek/mt8183-kukui-jacuzzi-fennel-sku7.dts
@@ -17,8 +17,7 @@
compatible = "hid-over-i2c";
reg = <0x10>;
- interrupt-parent = <&pio>;
- interrupts = <155 IRQ_TYPE_LEVEL_LOW>;
+ interrupts-extended = <&pio 155 IRQ_TYPE_LEVEL_LOW>;
pinctrl-names = "default";
pinctrl-0 = <&touchscreen_pins>;
diff --git a/dts/upstream/src/arm64/mediatek/mt8183-kukui-jacuzzi-makomo-sku0.dts b/dts/upstream/src/arm64/mediatek/mt8183-kukui-jacuzzi-makomo-sku0.dts
new file mode 100644
index 0000000..4eb2a0d
--- /dev/null
+++ b/dts/upstream/src/arm64/mediatek/mt8183-kukui-jacuzzi-makomo-sku0.dts
@@ -0,0 +1,24 @@
+// SPDX-License-Identifier: (GPL-2.0 OR MIT)
+/*
+ * Copyright 2023 Google LLC
+ */
+
+/dts-v1/;
+#include "mt8183-kukui-jacuzzi-fennel.dtsi"
+#include "mt8183-kukui-audio-da7219-rt1015p.dtsi"
+
+/ {
+ model = "Google makomo sku0 board";
+ chassis-type = "laptop";
+ compatible = "google,makomo-sku0", "google,makomo", "mediatek,mt8183";
+};
+
+&qca_wifi {
+ qcom,ath10k-calibration-variant = "GO_FENNEL14";
+};
+
+&mmc1_pins_uhs {
+ pins-clk {
+ drive-strength = <MTK_DRIVE_6mA>;
+ };
+};
diff --git a/dts/upstream/src/arm64/mediatek/mt8183-kukui-jacuzzi-makomo-sku1.dts b/dts/upstream/src/arm64/mediatek/mt8183-kukui-jacuzzi-makomo-sku1.dts
new file mode 100644
index 0000000..6a73336
--- /dev/null
+++ b/dts/upstream/src/arm64/mediatek/mt8183-kukui-jacuzzi-makomo-sku1.dts
@@ -0,0 +1,24 @@
+// SPDX-License-Identifier: (GPL-2.0 OR MIT)
+/*
+ * Copyright 2023 Google LLC
+ */
+
+/dts-v1/;
+#include "mt8183-kukui-jacuzzi-fennel.dtsi"
+#include "mt8183-kukui-audio-ts3a227e-rt1015p.dtsi"
+
+/ {
+ model = "Google makomo sku1 board";
+ chassis-type = "laptop";
+ compatible = "google,makomo-sku1", "google,makomo", "mediatek,mt8183";
+};
+
+&qca_wifi {
+ qcom,ath10k-calibration-variant = "GO_FENNEL14";
+};
+
+&mmc1_pins_uhs {
+ pins-clk {
+ drive-strength = <MTK_DRIVE_6mA>;
+ };
+};
diff --git a/dts/upstream/src/arm64/mediatek/mt8183-kukui-jacuzzi-pico.dts b/dts/upstream/src/arm64/mediatek/mt8183-kukui-jacuzzi-pico.dts
new file mode 100644
index 0000000..8ce9568
--- /dev/null
+++ b/dts/upstream/src/arm64/mediatek/mt8183-kukui-jacuzzi-pico.dts
@@ -0,0 +1,35 @@
+// SPDX-License-Identifier: (GPL-2.0 OR MIT)
+/*
+ * Copyright 2023 Google LLC
+ */
+
+/dts-v1/;
+#include "mt8183-kukui-jacuzzi.dtsi"
+#include "mt8183-kukui-audio-ts3a227e-max98357a.dtsi"
+
+/ {
+ model = "Google pico board";
+ chassis-type = "convertible";
+ compatible = "google,pico-sku1", "google,pico", "mediatek,mt8183";
+};
+
+&i2c_tunnel {
+ google,remote-bus = <0>;
+};
+
+&i2c2 {
+ i2c-scl-internal-delay-ns = <25000>;
+
+ trackpad@2c {
+ compatible = "hid-over-i2c";
+ reg = <0x2c>;
+ hid-descr-addr = <0x20>;
+
+ pinctrl-names = "default";
+ pinctrl-0 = <&trackpad_pins>;
+
+ interrupts-extended = <&pio 7 IRQ_TYPE_LEVEL_LOW>;
+
+ wakeup-source;
+ };
+};
diff --git a/dts/upstream/src/arm64/mediatek/mt8183-kukui-jacuzzi-pico6.dts b/dts/upstream/src/arm64/mediatek/mt8183-kukui-jacuzzi-pico6.dts
new file mode 100644
index 0000000..a2e74b8
--- /dev/null
+++ b/dts/upstream/src/arm64/mediatek/mt8183-kukui-jacuzzi-pico6.dts
@@ -0,0 +1,110 @@
+// SPDX-License-Identifier: (GPL-2.0 OR MIT)
+/*
+ * Copyright 2023 Google LLC
+ */
+
+/dts-v1/;
+#include "mt8183-kukui-jacuzzi.dtsi"
+#include "mt8183-kukui-audio-ts3a227e-max98357a.dtsi"
+
+/ {
+ model = "Google pico6 board";
+ chassis-type = "convertible";
+ compatible = "google,pico-sku2", "google,pico", "mediatek,mt8183";
+
+ bt_wakeup: bt-wakeup {
+ compatible = "gpio-keys";
+ pinctrl-names = "default";
+ pinctrl-0 = <&bt_pins_wakeup>;
+
+ wobt {
+ label = "Wake on BT";
+ gpios = <&pio 42 GPIO_ACTIVE_HIGH>;
+ linux,code = <KEY_WAKEUP>;
+ wakeup-source;
+ };
+ };
+};
+
+&i2c_tunnel {
+ google,remote-bus = <0>;
+};
+
+&i2c2 {
+ i2c-scl-internal-delay-ns = <25000>;
+
+ trackpad@2c {
+ compatible = "hid-over-i2c";
+ reg = <0x2c>;
+ hid-descr-addr = <0x20>;
+
+ pinctrl-names = "default";
+ pinctrl-0 = <&trackpad_pins>;
+
+ interrupts-extended = <&pio 7 IRQ_TYPE_LEVEL_LOW>;
+
+ wakeup-source;
+ };
+};
+
+&wifi_wakeup {
+ wowlan {
+ gpios = <&pio 113 GPIO_ACTIVE_LOW>;
+ };
+};
+
+&wifi_pwrseq {
+ post-power-on-delay-ms = <50>;
+
+ /* Toggle WIFI_ENABLE to reset the chip. */
+ reset-gpios = <&pio 8 GPIO_ACTIVE_LOW>;
+};
+
+&wifi_pins_pwrseq {
+ pins-wifi-enable {
+ pinmux = <PINMUX_GPIO8__FUNC_GPIO8>;
+ };
+};
+
+&mmc1_pins_default {
+ pins-cmd-dat {
+ drive-strength = <MTK_DRIVE_6mA>;
+ };
+ pins-clk {
+ drive-strength = <MTK_DRIVE_6mA>;
+ };
+};
+
+&mmc1_pins_uhs {
+ pins-clk {
+ drive-strength = <MTK_DRIVE_6mA>;
+ };
+};
+
+&mmc1 {
+ bt_reset: bt-reset {
+ compatible = "mediatek,mt7921s-bluetooth";
+ pinctrl-names = "default";
+ pinctrl-0 = <&bt_pins_reset>;
+ reset-gpios = <&pio 120 GPIO_ACTIVE_LOW>;
+ };
+};
+
+&pio {
+ bt_pins_wakeup: bt-pins-wakeup {
+ piins-bt-wakeup {
+ pinmux = <PINMUX_GPIO42__FUNC_GPIO42>;
+ input-enable;
+ };
+ };
+
+ bt_pins_reset: bt-pins-reset {
+ pins-bt-reset {
+ pinmux = <PINMUX_GPIO120__FUNC_GPIO120>;
+ output-high;
+ };
+ };
+};
+
+/delete-node/ &bluetooth;
+/delete-node/ &bt_pins;
diff --git a/dts/upstream/src/arm64/mediatek/mt8183-kukui-jacuzzi.dtsi b/dts/upstream/src/arm64/mediatek/mt8183-kukui-jacuzzi.dtsi
index 8202603..7592e3b 100644
--- a/dts/upstream/src/arm64/mediatek/mt8183-kukui-jacuzzi.dtsi
+++ b/dts/upstream/src/arm64/mediatek/mt8183-kukui-jacuzzi.dtsi
@@ -149,7 +149,6 @@
reg = <0x58>;
pinctrl-names = "default";
pinctrl-0 = <&anx7625_pins>;
- panel_flags = <1>;
enable-gpios = <&pio 45 GPIO_ACTIVE_HIGH>;
reset-gpios = <&pio 73 GPIO_ACTIVE_HIGH>;
vdd10-supply = <&pp1200_mipibrdg>;
diff --git a/dts/upstream/src/arm64/mediatek/mt8183-kukui-kakadu-sku22.dts b/dts/upstream/src/arm64/mediatek/mt8183-kukui-kakadu-sku22.dts
index fcce8ea..1ecf394 100644
--- a/dts/upstream/src/arm64/mediatek/mt8183-kukui-kakadu-sku22.dts
+++ b/dts/upstream/src/arm64/mediatek/mt8183-kukui-kakadu-sku22.dts
@@ -14,6 +14,24 @@
"google,kakadu", "mediatek,mt8183";
};
+&i2c0 {
+ touchscreen: touchscreen@10 {
+ compatible = "hid-over-i2c";
+ reg = <0x10>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&open_touch>;
+
+ interrupts-extended = <&pio 155 IRQ_TYPE_EDGE_FALLING>;
+
+ post-power-on-delay-ms = <10>;
+ hid-descr-addr = <0x0001>;
+ };
+};
+
+&panel {
+ compatible = "boe,tv105wum-nw0";
+};
+
&sound {
compatible = "mediatek,mt8183_mt6358_ts3a227_rt1015p";
};
diff --git a/dts/upstream/src/arm64/mediatek/mt8183-kukui-kakadu.dts b/dts/upstream/src/arm64/mediatek/mt8183-kukui-kakadu.dts
index ebfabba..ba74109 100644
--- a/dts/upstream/src/arm64/mediatek/mt8183-kukui-kakadu.dts
+++ b/dts/upstream/src/arm64/mediatek/mt8183-kukui-kakadu.dts
@@ -13,3 +13,21 @@
compatible = "google,kakadu-rev3", "google,kakadu-rev2",
"google,kakadu", "mediatek,mt8183";
};
+
+&i2c0 {
+ touchscreen: touchscreen@10 {
+ compatible = "hid-over-i2c";
+ reg = <0x10>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&open_touch>;
+
+ interrupts-extended = <&pio 155 IRQ_TYPE_EDGE_FALLING>;
+
+ post-power-on-delay-ms = <10>;
+ hid-descr-addr = <0x0001>;
+ };
+};
+
+&panel {
+ compatible = "boe,tv105wum-nw0";
+};
diff --git a/dts/upstream/src/arm64/mediatek/mt8183-kukui-kakadu.dtsi b/dts/upstream/src/arm64/mediatek/mt8183-kukui-kakadu.dtsi
index a11adeb2..b6a9830 100644
--- a/dts/upstream/src/arm64/mediatek/mt8183-kukui-kakadu.dtsi
+++ b/dts/upstream/src/arm64/mediatek/mt8183-kukui-kakadu.dtsi
@@ -63,19 +63,6 @@
&i2c0 {
status = "okay";
-
- touchscreen: touchscreen@10 {
- compatible = "hid-over-i2c";
- reg = <0x10>;
- pinctrl-names = "default";
- pinctrl-0 = <&open_touch>;
-
- interrupt-parent = <&pio>;
- interrupts = <155 IRQ_TYPE_EDGE_FALLING>;
-
- post-power-on-delay-ms = <10>;
- hid-descr-addr = <0x0001>;
- };
};
&mt6358_vcama2_reg {
@@ -384,5 +371,5 @@
&panel {
status = "okay";
- compatible = "boe,tv105wum-nw0";
+ /* compatible will be set in board dts */
};
diff --git a/dts/upstream/src/arm64/mediatek/mt8183-kukui-katsu-sku32.dts b/dts/upstream/src/arm64/mediatek/mt8183-kukui-katsu-sku32.dts
new file mode 100644
index 0000000..0536100
--- /dev/null
+++ b/dts/upstream/src/arm64/mediatek/mt8183-kukui-katsu-sku32.dts
@@ -0,0 +1,36 @@
+// SPDX-License-Identifier: (GPL-2.0 OR MIT)
+/*
+ * Copyright 2023 Google LLC
+ */
+
+/dts-v1/;
+#include "mt8183-kukui-kakadu.dtsi"
+#include "mt8183-kukui-audio-da7219-rt1015p.dtsi"
+
+/ {
+ model = "Google katsu board";
+ chassis-type = "tablet";
+ compatible = "google,katsu-sku32", "google,katsu", "mediatek,mt8183";
+};
+
+&i2c0 {
+ touchscreen1: touchscreen@5d {
+ compatible = "goodix,gt7375p";
+ reg = <0x5d>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&open_touch>;
+
+ interrupts-extended = <&pio 155 IRQ_TYPE_LEVEL_LOW>;
+
+ reset-gpios = <&pio 156 GPIO_ACTIVE_LOW>;
+ vdd-supply = <&lcd_pp3300>;
+ };
+};
+
+&panel {
+ compatible = "starry,2081101qfh032011-53g";
+};
+
+&qca_wifi {
+ qcom,ath10k-calibration-variant = "GO_KATSU";
+};
diff --git a/dts/upstream/src/arm64/mediatek/mt8183-kukui-katsu-sku38.dts b/dts/upstream/src/arm64/mediatek/mt8183-kukui-katsu-sku38.dts
new file mode 100644
index 0000000..cf008ed
--- /dev/null
+++ b/dts/upstream/src/arm64/mediatek/mt8183-kukui-katsu-sku38.dts
@@ -0,0 +1,40 @@
+// SPDX-License-Identifier: (GPL-2.0 OR MIT)
+/*
+ * Copyright 2023 Google LLC
+ */
+
+/dts-v1/;
+#include "mt8183-kukui-kakadu.dtsi"
+#include "mt8183-kukui-audio-rt1015p.dtsi"
+
+/ {
+ model = "Google katsu sku38 board";
+ chassis-type = "tablet";
+ compatible = "google,katsu-sku38", "google,katsu", "mediatek,mt8183";
+};
+
+&i2c0 {
+ touchscreen1: touchscreen@5d {
+ compatible = "goodix,gt7375p";
+ reg = <0x5d>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&open_touch>;
+
+ interrupts-extended = <&pio 155 IRQ_TYPE_LEVEL_LOW>;
+
+ reset-gpios = <&pio 156 GPIO_ACTIVE_LOW>;
+ vdd-supply = <&lcd_pp3300>;
+ };
+};
+
+&panel {
+ compatible = "starry,2081101qfh032011-53g";
+};
+
+&qca_wifi {
+ qcom,ath10k-calibration-variant = "GO_KATSU";
+};
+
+&sound {
+ compatible = "mediatek,mt8183_mt6358_ts3a227_rt1015p";
+};
diff --git a/dts/upstream/src/arm64/mediatek/mt8183-kukui-kodama.dtsi b/dts/upstream/src/arm64/mediatek/mt8183-kukui-kodama.dtsi
index 4864c39..306c951 100644
--- a/dts/upstream/src/arm64/mediatek/mt8183-kukui-kodama.dtsi
+++ b/dts/upstream/src/arm64/mediatek/mt8183-kukui-kodama.dtsi
@@ -48,8 +48,7 @@
touchscreen: touchscreen@10 {
compatible = "hid-over-i2c";
reg = <0x10>;
- interrupt-parent = <&pio>;
- interrupts = <155 IRQ_TYPE_LEVEL_LOW>;
+ interrupts-extended = <&pio 155 IRQ_TYPE_LEVEL_LOW>;
pinctrl-names = "default";
pinctrl-0 = <&touch_default>;
diff --git a/dts/upstream/src/arm64/mediatek/mt8183-kukui-krane.dtsi b/dts/upstream/src/arm64/mediatek/mt8183-kukui-krane.dtsi
index d5f41c6..382e4c6 100644
--- a/dts/upstream/src/arm64/mediatek/mt8183-kukui-krane.dtsi
+++ b/dts/upstream/src/arm64/mediatek/mt8183-kukui-krane.dtsi
@@ -54,8 +54,7 @@
pinctrl-names = "default";
pinctrl-0 = <&open_touch>;
- interrupt-parent = <&pio>;
- interrupts = <155 IRQ_TYPE_EDGE_FALLING>;
+ interrupts-extended = <&pio 155 IRQ_TYPE_EDGE_FALLING>;
post-power-on-delay-ms = <10>;
hid-descr-addr = <0x0001>;
diff --git a/dts/upstream/src/arm64/mediatek/mt8183-kukui.dtsi b/dts/upstream/src/arm64/mediatek/mt8183-kukui.dtsi
index 7881a27..1b3396b 100644
--- a/dts/upstream/src/arm64/mediatek/mt8183-kukui.dtsi
+++ b/dts/upstream/src/arm64/mediatek/mt8183-kukui.dtsi
@@ -846,6 +846,10 @@
};
};
+&pmic {
+ interrupts-extended = <&pio 182 IRQ_TYPE_LEVEL_HIGH>;
+};
+
&pwm0 {
status = "okay";
pinctrl-names = "default";
@@ -884,14 +888,13 @@
status = "okay";
cs-gpios = <&pio 86 GPIO_ACTIVE_LOW>;
- cr50@0 {
+ tpm@0 {
compatible = "google,cr50";
reg = <0>;
spi-max-frequency = <1000000>;
pinctrl-names = "default";
pinctrl-0 = <&h1_int_od_l>;
- interrupt-parent = <&pio>;
- interrupts = <153 IRQ_TYPE_EDGE_RISING>;
+ interrupts-extended = <&pio 153 IRQ_TYPE_EDGE_RISING>;
};
};
@@ -918,8 +921,7 @@
compatible = "google,cros-ec-spi";
reg = <0>;
spi-max-frequency = <3000000>;
- interrupt-parent = <&pio>;
- interrupts = <151 IRQ_TYPE_LEVEL_LOW>;
+ interrupts-extended = <&pio 151 IRQ_TYPE_LEVEL_LOW>;
pinctrl-names = "default";
pinctrl-0 = <&ec_ap_int_odl>;
diff --git a/dts/upstream/src/arm64/mediatek/mt8183-pumpkin.dts b/dts/upstream/src/arm64/mediatek/mt8183-pumpkin.dts
index b5784a6..76449b4 100644
--- a/dts/upstream/src/arm64/mediatek/mt8183-pumpkin.dts
+++ b/dts/upstream/src/arm64/mediatek/mt8183-pumpkin.dts
@@ -370,6 +370,10 @@
};
};
+&pmic {
+ interrupts-extended = <&pio 182 IRQ_TYPE_LEVEL_HIGH>;
+};
+
&mfg {
domain-supply = <&mt6358_vgpu_reg>;
};
diff --git a/dts/upstream/src/arm64/mediatek/mt8183.dtsi b/dts/upstream/src/arm64/mediatek/mt8183.dtsi
index 976dc96..920ee41 100644
--- a/dts/upstream/src/arm64/mediatek/mt8183.dtsi
+++ b/dts/upstream/src/arm64/mediatek/mt8183.dtsi
@@ -1183,22 +1183,10 @@
status = "disabled";
};
- svs: svs@1100b000 {
- compatible = "mediatek,mt8183-svs";
- reg = <0 0x1100b000 0 0x1000>;
- interrupts = <GIC_SPI 127 IRQ_TYPE_LEVEL_LOW>;
- clocks = <&infracfg CLK_INFRA_THERM>;
- clock-names = "main";
- nvmem-cells = <&svs_calibration>,
- <&thermal_calibration>;
- nvmem-cell-names = "svs-calibration-data",
- "t-calibration-data";
- };
-
thermal: thermal@1100b000 {
#thermal-sensor-cells = <1>;
compatible = "mediatek,mt8183-thermal";
- reg = <0 0x1100b000 0 0x1000>;
+ reg = <0 0x1100b000 0 0xc00>;
clocks = <&infracfg CLK_INFRA_THERM>,
<&infracfg CLK_INFRA_AUXADC>;
clock-names = "therm", "auxadc";
@@ -1210,6 +1198,18 @@
nvmem-cell-names = "calibration-data";
};
+ svs: svs@1100bc00 {
+ compatible = "mediatek,mt8183-svs";
+ reg = <0 0x1100bc00 0 0x400>;
+ interrupts = <GIC_SPI 127 IRQ_TYPE_LEVEL_LOW>;
+ clocks = <&infracfg CLK_INFRA_THERM>;
+ clock-names = "main";
+ nvmem-cells = <&svs_calibration>,
+ <&thermal_calibration>;
+ nvmem-cell-names = "svs-calibration-data",
+ "t-calibration-data";
+ };
+
pwm0: pwm@1100e000 {
compatible = "mediatek,mt8183-disp-pwm";
reg = <0 0x1100e000 0 0x1000>;
@@ -1660,7 +1660,7 @@
mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0 0x1000>;
};
- mdp3-rdma0@14001000 {
+ dma-controller0@14001000 {
compatible = "mediatek,mt8183-mdp3-rdma";
reg = <0 0x14001000 0 0x1000>;
mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0x1000 0x1000>;
@@ -1672,6 +1672,7 @@
iommus = <&iommu M4U_PORT_MDP_RDMA0>;
mboxes = <&gce 20 CMDQ_THR_PRIO_LOWEST 0>,
<&gce 21 CMDQ_THR_PRIO_LOWEST 0>;
+ #dma-cells = <1>;
};
mdp3-rsz0@14003000 {
@@ -1692,7 +1693,7 @@
clocks = <&mmsys CLK_MM_MDP_RSZ1>;
};
- mdp3-wrot0@14005000 {
+ dma-controller@14005000 {
compatible = "mediatek,mt8183-mdp3-wrot";
reg = <0 0x14005000 0 0x1000>;
mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0x5000 0x1000>;
@@ -1701,6 +1702,7 @@
power-domains = <&spm MT8183_POWER_DOMAIN_DISP>;
clocks = <&mmsys CLK_MM_MDP_WROT0>;
iommus = <&iommu M4U_PORT_MDP_WROT0>;
+ #dma-cells = <1>;
};
mdp3-wdma@14006000 {
@@ -1898,6 +1900,36 @@
#clock-cells = <1>;
};
+ vcodec_dec: video-codec@16020000 {
+ compatible = "mediatek,mt8183-vcodec-dec";
+ reg = <0 0x16020000 0 0x1000>, /* VDEC_MISC */
+ <0 0x16021000 0 0x800>, /* VDEC_VLD */
+ <0 0x16021800 0 0x800>, /* VDEC_TOP */
+ <0 0x16022000 0 0x1000>, /* VDEC_MC */
+ <0 0x16023000 0 0x1000>, /* VDEC_AVCVLD */
+ <0 0x16024000 0 0x1000>, /* VDEC_AVCMV */
+ <0 0x16025000 0 0x1000>, /* VDEC_PP */
+ <0 0x16026800 0 0x800>, /* VP8_VD */
+ <0 0x16027000 0 0x800>, /* VP6_VD */
+ <0 0x16027800 0 0x800>, /* VP8_VL */
+ <0 0x16028400 0 0x400>; /* VP9_VD */
+ reg-names = "misc", "ld", "top", "cm", "ad", "av", "pp",
+ "hwd", "hwq", "hwb", "hwg";
+ interrupts = <GIC_SPI 250 IRQ_TYPE_LEVEL_LOW>;
+ iommus = <&iommu M4U_PORT_HW_VDEC_MC_EXT>,
+ <&iommu M4U_PORT_HW_VDEC_PP_EXT>,
+ <&iommu M4U_PORT_HW_VDEC_VLD_EXT>,
+ <&iommu M4U_PORT_HW_VDEC_AVC_MV_EXT>,
+ <&iommu M4U_PORT_HW_VDEC_PRED_RD_EXT>,
+ <&iommu M4U_PORT_HW_VDEC_PRED_WR_EXT>,
+ <&iommu M4U_PORT_HW_VDEC_PPWRAP_EXT>;
+ mediatek,scp = <&scp>;
+ mediatek,vdecsys = <&vdecsys>;
+ power-domains = <&spm MT8183_POWER_DOMAIN_VDEC>;
+ clocks = <&vdecsys CLK_VDEC_VDEC>;
+ clock-names = "vdec";
+ };
+
larb1: larb@16010000 {
compatible = "mediatek,mt8183-smi-larb";
reg = <0 0x16010000 0 0x1000>;
diff --git a/dts/upstream/src/arm64/mediatek/mt8186.dtsi b/dts/upstream/src/arm64/mediatek/mt8186.dtsi
index df0c04f..2fec6fd 100644
--- a/dts/upstream/src/arm64/mediatek/mt8186.dtsi
+++ b/dts/upstream/src/arm64/mediatek/mt8186.dtsi
@@ -22,7 +22,7 @@
aliases {
ovl0 = &ovl0;
- ovl_2l0 = &ovl_2l0;
+ ovl-2l0 = &ovl_2l0;
rdma0 = &rdma0;
rdma1 = &rdma1;
};
@@ -1160,14 +1160,14 @@
status = "disabled";
};
- adsp_mailbox0: mailbox@10686000 {
+ adsp_mailbox0: mailbox@10686100 {
compatible = "mediatek,mt8186-adsp-mbox";
#mbox-cells = <0>;
reg = <0 0x10686100 0 0x1000>;
interrupts = <GIC_SPI 361 IRQ_TYPE_LEVEL_HIGH 0>;
};
- adsp_mailbox1: mailbox@10687000 {
+ adsp_mailbox1: mailbox@10687100 {
compatible = "mediatek,mt8186-adsp-mbox";
#mbox-cells = <0>;
reg = <0 0x10687100 0 0x1000>;
diff --git a/dts/upstream/src/arm64/mediatek/mt8188-evb.dts b/dts/upstream/src/arm64/mediatek/mt8188-evb.dts
new file mode 100644
index 0000000..68a82b4
--- /dev/null
+++ b/dts/upstream/src/arm64/mediatek/mt8188-evb.dts
@@ -0,0 +1,387 @@
+// SPDX-License-Identifier: (GPL-2.0 OR MIT)
+/*
+ * Copyright (C) 2023 MediaTek Inc.
+ */
+/dts-v1/;
+#include "mt8188.dtsi"
+#include "mt6359.dtsi"
+
+/ {
+ model = "MediaTek MT8188 evaluation board";
+ compatible = "mediatek,mt8188-evb", "mediatek,mt8188";
+
+ aliases {
+ serial0 = &uart0;
+ i2c0 = &i2c0;
+ i2c1 = &i2c1;
+ i2c2 = &i2c2;
+ i2c3 = &i2c3;
+ i2c4 = &i2c4;
+ i2c5 = &i2c5;
+ i2c6 = &i2c6;
+ mmc0 = &mmc0;
+ };
+
+ chosen: chosen {
+ stdout-path = "serial0:115200n8";
+ };
+
+ memory@40000000 {
+ device_type = "memory";
+ reg = <0 0x40000000 0 0x80000000>;
+ };
+
+ reserved_memory: reserved-memory {
+ #address-cells = <2>;
+ #size-cells = <2>;
+ ranges;
+
+ scp_mem_reserved: memory@50000000 {
+ compatible = "shared-dma-pool";
+ reg = <0 0x50000000 0 0x2900000>;
+ no-map;
+ };
+ };
+};
+
+&auxadc {
+ status = "okay";
+};
+
+&i2c0 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&i2c0_pins>;
+ clock-frequency = <400000>;
+ status = "okay";
+};
+
+&i2c1 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&i2c1_pins>;
+ clock-frequency = <400000>;
+ status = "okay";
+};
+
+&i2c2 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&i2c2_pins>;
+ clock-frequency = <400000>;
+ status = "okay";
+};
+
+&i2c3 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&i2c3_pins>;
+ clock-frequency = <400000>;
+ status = "okay";
+};
+
+&i2c4 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&i2c4_pins>;
+ clock-frequency = <400000>;
+ status = "okay";
+};
+
+&i2c5 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&i2c5_pins>;
+ clock-frequency = <400000>;
+ status = "okay";
+};
+
+&i2c6 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&i2c6_pins>;
+ clock-frequency = <400000>;
+ status = "okay";
+};
+
+&mmc0 {
+ bus-width = <8>;
+ hs400-ds-delay = <0x1481b>;
+ max-frequency = <200000000>;
+
+ cap-mmc-highspeed;
+ mmc-hs200-1_8v;
+ mmc-hs400-1_8v;
+ supports-cqe;
+ cap-mmc-hw-reset;
+ no-sdio;
+ no-sd;
+ non-removable;
+
+ vmmc-supply = <&mt6359_vemc_1_ldo_reg>;
+ vqmmc-supply = <&mt6359_vufs_ldo_reg>;
+
+ pinctrl-names = "default", "state_uhs";
+ pinctrl-0 = <&mmc0_default_pins>;
+ pinctrl-1 = <&mmc0_uhs_pins>;
+
+ status = "okay";
+};
+
+&mt6359_vcore_buck_reg {
+ regulator-always-on;
+};
+
+&mt6359_vgpu11_buck_reg {
+ regulator-always-on;
+};
+
+&mt6359_vpu_buck_reg {
+ regulator-always-on;
+};
+
+&mt6359_vrf12_ldo_reg {
+ regulator-always-on;
+};
+
+&nor_flash {
+ pinctrl-names = "default";
+ pinctrl-0 = <&nor_pins_default>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "okay";
+
+ flash@0 {
+ compatible = "jedec,spi-nor";
+ reg = <0>;
+ spi-max-frequency = <52000000>;
+ };
+};
+
+&pio {
+ adsp_uart_pins: adsp-uart-pins {
+ pins-tx-rx {
+ pinmux = <PINMUX_GPIO35__FUNC_O_ADSP_UTXD0>,
+ <PINMUX_GPIO36__FUNC_I1_ADSP_URXD0>;
+ };
+ };
+
+ i2c0_pins: i2c0-pins {
+ pins-bus {
+ pinmux = <PINMUX_GPIO56__FUNC_B1_SDA0>,
+ <PINMUX_GPIO55__FUNC_B1_SCL0>;
+ bias-pull-up = <MTK_PULL_SET_RSEL_011>;
+ };
+ };
+
+ i2c1_pins: i2c1-pins {
+ pins-bus {
+ pinmux = <PINMUX_GPIO58__FUNC_B1_SDA1>,
+ <PINMUX_GPIO57__FUNC_B1_SCL1>;
+ bias-pull-up = <MTK_PULL_SET_RSEL_011>;
+ };
+ };
+
+ i2c2_pins: i2c2-pins {
+ pins-bus {
+ pinmux = <PINMUX_GPIO60__FUNC_B1_SDA2>,
+ <PINMUX_GPIO59__FUNC_B1_SCL2>;
+ bias-pull-up = <MTK_PULL_SET_RSEL_011>;
+ };
+ };
+
+ i2c3_pins: i2c3-pins {
+ pins-bus {
+ pinmux = <PINMUX_GPIO62__FUNC_B1_SDA3>,
+ <PINMUX_GPIO61__FUNC_B1_SCL3>;
+ bias-pull-up = <MTK_PULL_SET_RSEL_011>;
+ };
+ };
+
+ i2c4_pins: i2c4-pins {
+ pins-bus {
+ pinmux = <PINMUX_GPIO64__FUNC_B1_SDA4>,
+ <PINMUX_GPIO63__FUNC_B1_SCL4>;
+ bias-pull-up = <MTK_PULL_SET_RSEL_011>;
+ };
+ };
+
+ i2c5_pins: i2c5-pins {
+ pins-bus {
+ pinmux = <PINMUX_GPIO66__FUNC_B1_SDA5>,
+ <PINMUX_GPIO65__FUNC_B1_SCL5>;
+ bias-pull-up = <MTK_PULL_SET_RSEL_011>;
+ };
+ };
+
+ i2c6_pins: i2c6-pins {
+ pins-bus {
+ pinmux = <PINMUX_GPIO68__FUNC_B1_SDA6>,
+ <PINMUX_GPIO67__FUNC_B1_SCL6>;
+ bias-pull-up = <MTK_PULL_SET_RSEL_011>;
+ };
+ };
+
+ mmc0_default_pins: mmc0-default-pins {
+ pins-cmd-dat {
+ pinmux = <PINMUX_GPIO161__FUNC_B1_MSDC0_DAT0>,
+ <PINMUX_GPIO160__FUNC_B1_MSDC0_DAT1>,
+ <PINMUX_GPIO159__FUNC_B1_MSDC0_DAT2>,
+ <PINMUX_GPIO158__FUNC_B1_MSDC0_DAT3>,
+ <PINMUX_GPIO154__FUNC_B1_MSDC0_DAT4>,
+ <PINMUX_GPIO153__FUNC_B1_MSDC0_DAT5>,
+ <PINMUX_GPIO152__FUNC_B1_MSDC0_DAT6>,
+ <PINMUX_GPIO151__FUNC_B1_MSDC0_DAT7>,
+ <PINMUX_GPIO156__FUNC_B1_MSDC0_CMD>;
+ input-enable;
+ drive-strength = <6>;
+ bias-pull-up = <MTK_PUPD_SET_R1R0_01>;
+ };
+
+ pins-clk {
+ pinmux = <PINMUX_GPIO157__FUNC_B1_MSDC0_CLK>;
+ drive-strength = <6>;
+ bias-pull-down = <MTK_PUPD_SET_R1R0_10>;
+ };
+
+ pins-rst {
+ pinmux = <PINMUX_GPIO155__FUNC_O_MSDC0_RSTB>;
+ drive-strength = <6>;
+ bias-pull-up = <MTK_PUPD_SET_R1R0_01>;
+ };
+ };
+
+ mmc0_uhs_pins: mmc0-uhs-pins {
+ pins-cmd-dat {
+ pinmux = <PINMUX_GPIO161__FUNC_B1_MSDC0_DAT0>,
+ <PINMUX_GPIO160__FUNC_B1_MSDC0_DAT1>,
+ <PINMUX_GPIO159__FUNC_B1_MSDC0_DAT2>,
+ <PINMUX_GPIO158__FUNC_B1_MSDC0_DAT3>,
+ <PINMUX_GPIO154__FUNC_B1_MSDC0_DAT4>,
+ <PINMUX_GPIO153__FUNC_B1_MSDC0_DAT5>,
+ <PINMUX_GPIO152__FUNC_B1_MSDC0_DAT6>,
+ <PINMUX_GPIO151__FUNC_B1_MSDC0_DAT7>,
+ <PINMUX_GPIO156__FUNC_B1_MSDC0_CMD>;
+ input-enable;
+ drive-strength = <8>;
+ bias-pull-up = <MTK_PUPD_SET_R1R0_01>;
+ };
+
+ pins-clk-ds {
+ pinmux = <PINMUX_GPIO157__FUNC_B1_MSDC0_CLK>,
+ <PINMUX_GPIO162__FUNC_B0_MSDC0_DSL>;
+ drive-strength = <8>;
+ bias-pull-down = <MTK_PUPD_SET_R1R0_10>;
+ };
+
+ pins-rst {
+ pinmux = <PINMUX_GPIO155__FUNC_O_MSDC0_RSTB>;
+ drive-strength = <8>;
+ bias-pull-up = <MTK_PUPD_SET_R1R0_01>;
+ };
+ };
+
+ nor_pins_default: nor-pins {
+ pins-io-ck {
+ pinmux = <PINMUX_GPIO127__FUNC_B0_SPINOR_IO0>,
+ <PINMUX_GPIO125__FUNC_O_SPINOR_CK>,
+ <PINMUX_GPIO128__FUNC_B0_SPINOR_IO1>;
+ bias-pull-down;
+ };
+
+ pins-io-cs {
+ pinmux = <PINMUX_GPIO126__FUNC_O_SPINOR_CS>,
+ <PINMUX_GPIO129__FUNC_B0_SPINOR_IO2>,
+ <PINMUX_GPIO130__FUNC_B0_SPINOR_IO3>;
+ bias-pull-up;
+ };
+ };
+
+ spi0_pins: spi0-pins {
+ pins-spi {
+ pinmux = <PINMUX_GPIO69__FUNC_O_SPIM0_CSB>,
+ <PINMUX_GPIO70__FUNC_O_SPIM0_CLK>,
+ <PINMUX_GPIO71__FUNC_B0_SPIM0_MOSI>,
+ <PINMUX_GPIO72__FUNC_B0_SPIM0_MISO>;
+ bias-disable;
+ };
+ };
+
+ spi1_pins: spi1-pins {
+ pins-spi {
+ pinmux = <PINMUX_GPIO75__FUNC_O_SPIM1_CSB>,
+ <PINMUX_GPIO76__FUNC_O_SPIM1_CLK>,
+ <PINMUX_GPIO77__FUNC_B0_SPIM1_MOSI>,
+ <PINMUX_GPIO78__FUNC_B0_SPIM1_MISO>;
+ bias-disable;
+ };
+ };
+
+ spi2_pins: spi2-pins {
+ pins-spi {
+ pinmux = <PINMUX_GPIO79__FUNC_O_SPIM2_CSB>,
+ <PINMUX_GPIO80__FUNC_O_SPIM2_CLK>,
+ <PINMUX_GPIO81__FUNC_B0_SPIM2_MOSI>,
+ <PINMUX_GPIO82__FUNC_B0_SPIM2_MISO>;
+ bias-disable;
+ };
+ };
+
+ uart0_pins: uart0-pins {
+ pins-rx-tx {
+ pinmux = <PINMUX_GPIO31__FUNC_O_UTXD0>,
+ <PINMUX_GPIO32__FUNC_I1_URXD0>;
+ bias-pull-up;
+ };
+ };
+};
+
+&pmic {
+ interrupts-extended = <&pio 222 IRQ_TYPE_LEVEL_HIGH>;
+};
+
+&scp {
+ memory-region = <&scp_mem_reserved>;
+ status = "okay";
+};
+
+&spi0 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&spi0_pins>;
+ status = "okay";
+};
+
+&spi1 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&spi1_pins>;
+ status = "okay";
+};
+
+&spi2 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&spi2_pins>;
+ status = "okay";
+};
+
+&u3phy0 {
+ status = "okay";
+};
+
+&u3phy1 {
+ status = "okay";
+};
+
+&u3phy2 {
+ status = "okay";
+};
+
+&uart0 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&uart0_pins>;
+ status = "okay";
+};
+
+&xhci0 {
+ status = "okay";
+};
+
+&xhci1 {
+ status = "okay";
+};
+
+&xhci2 {
+ status = "okay";
+};
diff --git a/dts/upstream/src/arm64/mediatek/mt8188.dtsi b/dts/upstream/src/arm64/mediatek/mt8188.dtsi
new file mode 100644
index 0000000..b4315c9
--- /dev/null
+++ b/dts/upstream/src/arm64/mediatek/mt8188.dtsi
@@ -0,0 +1,956 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (c) 2023 MediaTek Inc.
+ *
+ */
+
+/dts-v1/;
+#include <dt-bindings/clock/mediatek,mt8188-clk.h>
+#include <dt-bindings/interrupt-controller/arm-gic.h>
+#include <dt-bindings/interrupt-controller/irq.h>
+#include <dt-bindings/phy/phy.h>
+#include <dt-bindings/pinctrl/mediatek,mt8188-pinfunc.h>
+#include <dt-bindings/power/mediatek,mt8188-power.h>
+
+/ {
+ compatible = "mediatek,mt8188";
+ interrupt-parent = <&gic>;
+ #address-cells = <2>;
+ #size-cells = <2>;
+
+ cpus {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ cpu0: cpu@0 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a55";
+ reg = <0x000>;
+ enable-method = "psci";
+ clock-frequency = <2000000000>;
+ capacity-dmips-mhz = <282>;
+ cpu-idle-states = <&cpu_off_l &cluster_off_l>;
+ i-cache-size = <32768>;
+ i-cache-line-size = <64>;
+ i-cache-sets = <128>;
+ d-cache-size = <32768>;
+ d-cache-line-size = <64>;
+ d-cache-sets = <128>;
+ next-level-cache = <&l2_0>;
+ #cooling-cells = <2>;
+ };
+
+ cpu1: cpu@100 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a55";
+ reg = <0x100>;
+ enable-method = "psci";
+ clock-frequency = <2000000000>;
+ capacity-dmips-mhz = <282>;
+ cpu-idle-states = <&cpu_off_l &cluster_off_l>;
+ i-cache-size = <32768>;
+ i-cache-line-size = <64>;
+ i-cache-sets = <128>;
+ d-cache-size = <32768>;
+ d-cache-line-size = <64>;
+ d-cache-sets = <128>;
+ next-level-cache = <&l2_0>;
+ #cooling-cells = <2>;
+ };
+
+ cpu2: cpu@200 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a55";
+ reg = <0x200>;
+ enable-method = "psci";
+ clock-frequency = <2000000000>;
+ capacity-dmips-mhz = <282>;
+ cpu-idle-states = <&cpu_off_l &cluster_off_l>;
+ i-cache-size = <32768>;
+ i-cache-line-size = <64>;
+ i-cache-sets = <128>;
+ d-cache-size = <32768>;
+ d-cache-line-size = <64>;
+ d-cache-sets = <128>;
+ next-level-cache = <&l2_0>;
+ #cooling-cells = <2>;
+ };
+
+ cpu3: cpu@300 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a55";
+ reg = <0x300>;
+ enable-method = "psci";
+ clock-frequency = <2000000000>;
+ capacity-dmips-mhz = <282>;
+ cpu-idle-states = <&cpu_off_l &cluster_off_l>;
+ i-cache-size = <32768>;
+ i-cache-line-size = <64>;
+ i-cache-sets = <128>;
+ d-cache-size = <32768>;
+ d-cache-line-size = <64>;
+ d-cache-sets = <128>;
+ next-level-cache = <&l2_0>;
+ #cooling-cells = <2>;
+ };
+
+ cpu4: cpu@400 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a55";
+ reg = <0x400>;
+ enable-method = "psci";
+ clock-frequency = <2000000000>;
+ capacity-dmips-mhz = <282>;
+ cpu-idle-states = <&cpu_off_l &cluster_off_l>;
+ i-cache-size = <32768>;
+ i-cache-line-size = <64>;
+ i-cache-sets = <128>;
+ d-cache-size = <32768>;
+ d-cache-line-size = <64>;
+ d-cache-sets = <128>;
+ next-level-cache = <&l2_0>;
+ #cooling-cells = <2>;
+ };
+
+ cpu5: cpu@500 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a55";
+ reg = <0x500>;
+ enable-method = "psci";
+ clock-frequency = <2000000000>;
+ capacity-dmips-mhz = <282>;
+ cpu-idle-states = <&cpu_off_l &cluster_off_l>;
+ i-cache-size = <32768>;
+ i-cache-line-size = <64>;
+ i-cache-sets = <128>;
+ d-cache-size = <32768>;
+ d-cache-line-size = <64>;
+ d-cache-sets = <128>;
+ next-level-cache = <&l2_0>;
+ #cooling-cells = <2>;
+ };
+
+ cpu6: cpu@600 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a78";
+ reg = <0x600>;
+ enable-method = "psci";
+ clock-frequency = <2600000000>;
+ capacity-dmips-mhz = <1024>;
+ cpu-idle-states = <&cpu_off_b &cluster_off_b>;
+ i-cache-size = <65536>;
+ i-cache-line-size = <64>;
+ i-cache-sets = <256>;
+ d-cache-size = <65536>;
+ d-cache-line-size = <64>;
+ d-cache-sets = <256>;
+ next-level-cache = <&l2_1>;
+ #cooling-cells = <2>;
+ };
+
+ cpu7: cpu@700 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a78";
+ reg = <0x700>;
+ enable-method = "psci";
+ clock-frequency = <2600000000>;
+ capacity-dmips-mhz = <1024>;
+ cpu-idle-states = <&cpu_off_b &cluster_off_b>;
+ i-cache-size = <65536>;
+ i-cache-line-size = <64>;
+ i-cache-sets = <256>;
+ d-cache-size = <65536>;
+ d-cache-line-size = <64>;
+ d-cache-sets = <256>;
+ next-level-cache = <&l2_1>;
+ #cooling-cells = <2>;
+ };
+
+ cpu-map {
+ cluster0 {
+ core0 {
+ cpu = <&cpu0>;
+ };
+
+ core1 {
+ cpu = <&cpu1>;
+ };
+
+ core2 {
+ cpu = <&cpu2>;
+ };
+
+ core3 {
+ cpu = <&cpu3>;
+ };
+
+ core4 {
+ cpu = <&cpu4>;
+ };
+
+ core5 {
+ cpu = <&cpu5>;
+ };
+
+ core6 {
+ cpu = <&cpu6>;
+ };
+
+ core7 {
+ cpu = <&cpu7>;
+ };
+ };
+ };
+
+ idle-states {
+ entry-method = "psci";
+
+ cpu_off_l: cpu-off-l {
+ compatible = "arm,idle-state";
+ arm,psci-suspend-param = <0x00010000>;
+ local-timer-stop;
+ entry-latency-us = <50>;
+ exit-latency-us = <95>;
+ min-residency-us = <580>;
+ };
+
+ cpu_off_b: cpu-off-b {
+ compatible = "arm,idle-state";
+ arm,psci-suspend-param = <0x00010000>;
+ local-timer-stop;
+ entry-latency-us = <45>;
+ exit-latency-us = <140>;
+ min-residency-us = <740>;
+ };
+
+ cluster_off_l: cluster-off-l {
+ compatible = "arm,idle-state";
+ arm,psci-suspend-param = <0x01010010>;
+ local-timer-stop;
+ entry-latency-us = <55>;
+ exit-latency-us = <155>;
+ min-residency-us = <840>;
+ };
+
+ cluster_off_b: cluster-off-b {
+ compatible = "arm,idle-state";
+ arm,psci-suspend-param = <0x01010010>;
+ local-timer-stop;
+ entry-latency-us = <50>;
+ exit-latency-us = <200>;
+ min-residency-us = <1000>;
+ };
+ };
+
+ l2_0: l2-cache0 {
+ compatible = "cache";
+ cache-level = <2>;
+ cache-size = <131072>;
+ cache-line-size = <64>;
+ cache-sets = <512>;
+ next-level-cache = <&l3_0>;
+ cache-unified;
+ };
+
+ l2_1: l2-cache1 {
+ compatible = "cache";
+ cache-level = <2>;
+ cache-size = <262144>;
+ cache-line-size = <64>;
+ cache-sets = <512>;
+ next-level-cache = <&l3_0>;
+ cache-unified;
+ };
+
+ l3_0: l3-cache {
+ compatible = "cache";
+ cache-level = <3>;
+ cache-size = <2097152>;
+ cache-line-size = <64>;
+ cache-sets = <2048>;
+ cache-unified;
+ };
+ };
+
+ clk13m: oscillator-13m {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <13000000>;
+ clock-output-names = "clk13m";
+ };
+
+ clk26m: oscillator-26m {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <26000000>;
+ clock-output-names = "clk26m";
+ };
+
+ clk32k: oscillator-32k {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <32768>;
+ clock-output-names = "clk32k";
+ };
+
+ pmu-a55 {
+ compatible = "arm,cortex-a55-pmu";
+ interrupt-parent = <&gic>;
+ interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH &ppi_cluster0>;
+ };
+
+ pmu-a78 {
+ compatible = "arm,cortex-a78-pmu";
+ interrupt-parent = <&gic>;
+ interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH &ppi_cluster1>;
+ };
+
+ psci {
+ compatible = "arm,psci-1.0";
+ method = "smc";
+ };
+
+ timer: timer {
+ compatible = "arm,armv8-timer";
+ interrupt-parent = <&gic>;
+ interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_HIGH 0>,
+ <GIC_PPI 14 IRQ_TYPE_LEVEL_HIGH 0>,
+ <GIC_PPI 11 IRQ_TYPE_LEVEL_HIGH 0>,
+ <GIC_PPI 10 IRQ_TYPE_LEVEL_HIGH 0>;
+ clock-frequency = <13000000>;
+ };
+
+ soc {
+ #address-cells = <2>;
+ #size-cells = <2>;
+ compatible = "simple-bus";
+ ranges;
+
+ gic: interrupt-controller@c000000 {
+ compatible = "arm,gic-v3";
+ #interrupt-cells = <4>;
+ #redistributor-regions = <1>;
+ interrupt-parent = <&gic>;
+ interrupt-controller;
+ reg = <0 0x0c000000 0 0x40000>,
+ <0 0x0c040000 0 0x200000>;
+ interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH 0>;
+
+ ppi-partitions {
+ ppi_cluster0: interrupt-partition-0 {
+ affinity = <&cpu0 &cpu1 &cpu2 &cpu3 &cpu4 &cpu5>;
+ };
+
+ ppi_cluster1: interrupt-partition-1 {
+ affinity = <&cpu6 &cpu7>;
+ };
+ };
+ };
+
+ topckgen: syscon@10000000 {
+ compatible = "mediatek,mt8188-topckgen", "syscon";
+ reg = <0 0x10000000 0 0x1000>;
+ #clock-cells = <1>;
+ };
+
+ infracfg_ao: syscon@10001000 {
+ compatible = "mediatek,mt8188-infracfg-ao", "syscon";
+ reg = <0 0x10001000 0 0x1000>;
+ #clock-cells = <1>;
+ };
+
+ pericfg: syscon@10003000 {
+ compatible = "mediatek,mt8188-pericfg", "syscon";
+ reg = <0 0x10003000 0 0x1000>;
+ #clock-cells = <1>;
+ };
+
+ pio: pinctrl@10005000 {
+ compatible = "mediatek,mt8188-pinctrl";
+ reg = <0 0x10005000 0 0x1000>,
+ <0 0x11c00000 0 0x1000>,
+ <0 0x11e10000 0 0x1000>,
+ <0 0x11e20000 0 0x1000>,
+ <0 0x11ea0000 0 0x1000>,
+ <0 0x1000b000 0 0x1000>;
+ reg-names = "iocfg0", "iocfg_rm", "iocfg_lt",
+ "iocfg_lm", "iocfg_rt", "eint";
+ gpio-controller;
+ #gpio-cells = <2>;
+ gpio-ranges = <&pio 0 0 176>;
+ interrupt-controller;
+ interrupts = <GIC_SPI 235 IRQ_TYPE_LEVEL_HIGH 0>;
+ #interrupt-cells = <2>;
+ };
+
+ watchdog: watchdog@10007000 {
+ compatible = "mediatek,mt8188-wdt";
+ reg = <0 0x10007000 0 0x100>;
+ mediatek,disable-extrst;
+ #reset-cells = <1>;
+ };
+
+ apmixedsys: syscon@1000c000 {
+ compatible = "mediatek,mt8188-apmixedsys", "syscon";
+ reg = <0 0x1000c000 0 0x1000>;
+ #clock-cells = <1>;
+ };
+
+ systimer: timer@10017000 {
+ compatible = "mediatek,mt8188-timer", "mediatek,mt6765-timer";
+ reg = <0 0x10017000 0 0x1000>;
+ interrupts = <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH 0>;
+ clocks = <&clk13m>;
+ };
+
+ pwrap: pwrap@10024000 {
+ compatible = "mediatek,mt8188-pwrap", "mediatek,mt8195-pwrap", "syscon";
+ reg = <0 0x10024000 0 0x1000>;
+ reg-names = "pwrap";
+ interrupts = <GIC_SPI 243 IRQ_TYPE_LEVEL_HIGH 0>;
+ clocks = <&infracfg_ao CLK_INFRA_AO_PMIC_AP>,
+ <&infracfg_ao CLK_INFRA_AO_PMIC_TMR>;
+ clock-names = "spi", "wrap";
+ };
+
+ scp: scp@10500000 {
+ compatible = "mediatek,mt8188-scp";
+ reg = <0 0x10500000 0 0x100000>,
+ <0 0x10720000 0 0xe0000>;
+ reg-names = "sram", "cfg";
+ interrupts = <GIC_SPI 462 IRQ_TYPE_LEVEL_HIGH 0>;
+ };
+
+ adsp_audio26m: clock-controller@10b91100 {
+ compatible = "mediatek,mt8188-adsp-audio26m";
+ reg = <0 0x10b91100 0 0x100>;
+ #clock-cells = <1>;
+ };
+
+ uart0: serial@11001100 {
+ compatible = "mediatek,mt8188-uart", "mediatek,mt6577-uart";
+ reg = <0 0x11001100 0 0x100>;
+ interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH 0>;
+ clocks = <&clk26m>, <&infracfg_ao CLK_INFRA_AO_UART0>;
+ clock-names = "baud", "bus";
+ status = "disabled";
+ };
+
+ uart1: serial@11001200 {
+ compatible = "mediatek,mt8188-uart", "mediatek,mt6577-uart";
+ reg = <0 0x11001200 0 0x100>;
+ interrupts = <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH 0>;
+ clocks = <&clk26m>, <&infracfg_ao CLK_INFRA_AO_UART1>;
+ clock-names = "baud", "bus";
+ status = "disabled";
+ };
+
+ uart2: serial@11001300 {
+ compatible = "mediatek,mt8188-uart", "mediatek,mt6577-uart";
+ reg = <0 0x11001300 0 0x100>;
+ interrupts = <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH 0>;
+ clocks = <&clk26m>, <&infracfg_ao CLK_INFRA_AO_UART2>;
+ clock-names = "baud", "bus";
+ status = "disabled";
+ };
+
+ uart3: serial@11001400 {
+ compatible = "mediatek,mt8188-uart", "mediatek,mt6577-uart";
+ reg = <0 0x11001400 0 0x100>;
+ interrupts = <GIC_SPI 723 IRQ_TYPE_LEVEL_HIGH 0>;
+ clocks = <&clk26m>, <&infracfg_ao CLK_INFRA_AO_UART3>;
+ clock-names = "baud", "bus";
+ status = "disabled";
+ };
+
+ auxadc: adc@11002000 {
+ compatible = "mediatek,mt8188-auxadc", "mediatek,mt8173-auxadc";
+ reg = <0 0x11002000 0 0x1000>;
+ clocks = <&infracfg_ao CLK_INFRA_AO_AUXADC>;
+ clock-names = "main";
+ #io-channel-cells = <1>;
+ status = "disabled";
+ };
+
+ pericfg_ao: syscon@11003000 {
+ compatible = "mediatek,mt8188-pericfg-ao", "syscon";
+ reg = <0 0x11003000 0 0x1000>;
+ #clock-cells = <1>;
+ };
+
+ spi0: spi@1100a000 {
+ compatible = "mediatek,mt8188-spi-ipm", "mediatek,spi-ipm";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0 0x1100a000 0 0x1000>;
+ interrupts = <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH 0>;
+ clocks = <&topckgen CLK_TOP_UNIVPLL_D6_D2>,
+ <&topckgen CLK_TOP_SPI>,
+ <&infracfg_ao CLK_INFRA_AO_SPI0>;
+ clock-names = "parent-clk", "sel-clk", "spi-clk";
+ status = "disabled";
+ };
+
+ spi1: spi@11010000 {
+ compatible = "mediatek,mt8188-spi-ipm", "mediatek,spi-ipm";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0 0x11010000 0 0x1000>;
+ interrupts = <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH 0>;
+ clocks = <&topckgen CLK_TOP_UNIVPLL_D6_D2>,
+ <&topckgen CLK_TOP_SPI>,
+ <&infracfg_ao CLK_INFRA_AO_SPI1>;
+ clock-names = "parent-clk", "sel-clk", "spi-clk";
+ status = "disabled";
+ };
+
+ spi2: spi@11012000 {
+ compatible = "mediatek,mt8188-spi-ipm", "mediatek,spi-ipm";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0 0x11012000 0 0x1000>;
+ interrupts = <GIC_SPI 193 IRQ_TYPE_LEVEL_HIGH 0>;
+ clocks = <&topckgen CLK_TOP_UNIVPLL_D6_D2>,
+ <&topckgen CLK_TOP_SPI>,
+ <&infracfg_ao CLK_INFRA_AO_SPI2>;
+ clock-names = "parent-clk", "sel-clk", "spi-clk";
+ status = "disabled";
+ };
+
+ spi3: spi@11013000 {
+ compatible = "mediatek,mt8188-spi-ipm", "mediatek,spi-ipm";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0 0x11013000 0 0x1000>;
+ interrupts = <GIC_SPI 194 IRQ_TYPE_LEVEL_HIGH 0>;
+ clocks = <&topckgen CLK_TOP_UNIVPLL_D6_D2>,
+ <&topckgen CLK_TOP_SPI>,
+ <&infracfg_ao CLK_INFRA_AO_SPI3>;
+ clock-names = "parent-clk", "sel-clk", "spi-clk";
+ status = "disabled";
+ };
+
+ spi4: spi@11018000 {
+ compatible = "mediatek,mt8188-spi-ipm", "mediatek,spi-ipm";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0 0x11018000 0 0x1000>;
+ interrupts = <GIC_SPI 195 IRQ_TYPE_LEVEL_HIGH 0>;
+ clocks = <&topckgen CLK_TOP_UNIVPLL_D6_D2>,
+ <&topckgen CLK_TOP_SPI>,
+ <&infracfg_ao CLK_INFRA_AO_SPI4>;
+ clock-names = "parent-clk", "sel-clk", "spi-clk";
+ status = "disabled";
+ };
+
+ spi5: spi@11019000 {
+ compatible = "mediatek,mt8188-spi-ipm", "mediatek,spi-ipm";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0 0x11019000 0 0x1000>;
+ interrupts = <GIC_SPI 196 IRQ_TYPE_LEVEL_HIGH 0>;
+ clocks = <&topckgen CLK_TOP_UNIVPLL_D6_D2>,
+ <&topckgen CLK_TOP_SPI>,
+ <&infracfg_ao CLK_INFRA_AO_SPI5>;
+ clock-names = "parent-clk", "sel-clk", "spi-clk";
+ status = "disabled";
+ };
+
+ xhci1: usb@11200000 {
+ compatible = "mediatek,mt8188-xhci", "mediatek,mtk-xhci";
+ reg = <0 0x11200000 0 0x1000>,
+ <0 0x11203e00 0 0x0100>;
+ reg-names = "mac", "ippc";
+ interrupts = <GIC_SPI 129 IRQ_TYPE_LEVEL_HIGH 0>;
+ phys = <&u2port1 PHY_TYPE_USB2>,
+ <&u3port1 PHY_TYPE_USB3>;
+ assigned-clocks = <&topckgen CLK_TOP_USB_TOP>,
+ <&topckgen CLK_TOP_SSUSB_XHCI>;
+ assigned-clock-parents = <&topckgen CLK_TOP_UNIVPLL_D5_D4>,
+ <&topckgen CLK_TOP_UNIVPLL_D5_D4>;
+ clocks = <&pericfg_ao CLK_PERI_AO_SSUSB_BUS>,
+ <&topckgen CLK_TOP_SSUSB_TOP_REF>,
+ <&pericfg_ao CLK_PERI_AO_SSUSB_XHCI>;
+ clock-names = "sys_ck", "ref_ck", "mcu_ck";
+ mediatek,syscon-wakeup = <&pericfg 0x468 2>;
+ wakeup-source;
+ status = "disabled";
+ };
+
+ mmc0: mmc@11230000 {
+ compatible = "mediatek,mt8188-mmc", "mediatek,mt8183-mmc";
+ reg = <0 0x11230000 0 0x10000>,
+ <0 0x11f50000 0 0x1000>;
+ interrupts = <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH 0>;
+ clocks = <&topckgen CLK_TOP_MSDC50_0>,
+ <&infracfg_ao CLK_INFRA_AO_MSDC0>,
+ <&infracfg_ao CLK_INFRA_AO_MSDC0_SRC>,
+ <&infracfg_ao CLK_INFRA_AO_RG_AES_MSDCFDE_CK_0P>;
+ clock-names = "source", "hclk", "source_cg", "crypto_clk";
+ status = "disabled";
+ };
+
+ mmc1: mmc@11240000 {
+ compatible = "mediatek,mt8188-mmc", "mediatek,mt8183-mmc";
+ reg = <0 0x11240000 0 0x1000>,
+ <0 0x11eb0000 0 0x1000>;
+ interrupts = <GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH 0>;
+ clocks = <&topckgen CLK_TOP_MSDC30_1>,
+ <&infracfg_ao CLK_INFRA_AO_MSDC1>,
+ <&infracfg_ao CLK_INFRA_AO_MSDC1_SRC>;
+ clock-names = "source", "hclk", "source_cg";
+ assigned-clocks = <&topckgen CLK_TOP_MSDC30_1>;
+ assigned-clock-parents = <&topckgen CLK_TOP_MSDCPLL_D2>;
+ status = "disabled";
+ };
+
+ i2c0: i2c@11280000 {
+ compatible = "mediatek,mt8188-i2c";
+ reg = <0 0x11280000 0 0x1000>,
+ <0 0x10220080 0 0x80>;
+ interrupts = <GIC_SPI 151 IRQ_TYPE_LEVEL_HIGH 0>;
+ clock-div = <1>;
+ clocks = <&imp_iic_wrap_c CLK_IMP_IIC_WRAP_C_AP_CLOCK_I2C0>,
+ <&infracfg_ao CLK_INFRA_AO_APDMA_BCLK>;
+ clock-names = "main", "dma";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+ };
+
+ i2c2: i2c@11281000 {
+ compatible = "mediatek,mt8188-i2c";
+ reg = <0 0x11281000 0 0x1000>,
+ <0 0x10220180 0 0x80>;
+ interrupts = <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH 0>;
+ clock-div = <1>;
+ clocks = <&imp_iic_wrap_c CLK_IMP_IIC_WRAP_C_AP_CLOCK_I2C2>,
+ <&infracfg_ao CLK_INFRA_AO_APDMA_BCLK>;
+ clock-names = "main", "dma";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+ };
+
+ i2c3: i2c@11282000 {
+ compatible = "mediatek,mt8188-i2c";
+ reg = <0 0x11282000 0 0x1000>,
+ <0 0x10220280 0 0x80>;
+ interrupts = <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH 0>;
+ clock-div = <1>;
+ clocks = <&imp_iic_wrap_c CLK_IMP_IIC_WRAP_C_AP_CLOCK_I2C3>,
+ <&infracfg_ao CLK_INFRA_AO_APDMA_BCLK>;
+ clock-names = "main", "dma";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+ };
+
+ imp_iic_wrap_c: clock-controller@11283000 {
+ compatible = "mediatek,mt8188-imp-iic-wrap-c";
+ reg = <0 0x11283000 0 0x1000>;
+ #clock-cells = <1>;
+ };
+
+ xhci2: usb@112a0000 {
+ compatible = "mediatek,mt8188-xhci", "mediatek,mtk-xhci";
+ reg = <0 0x112a0000 0 0x1000>,
+ <0 0x112a3e00 0 0x0100>;
+ reg-names = "mac", "ippc";
+ interrupts = <GIC_SPI 536 IRQ_TYPE_LEVEL_HIGH 0>;
+ phys = <&u2port2 PHY_TYPE_USB2>;
+ assigned-clocks = <&topckgen CLK_TOP_SSUSB_XHCI_3P>,
+ <&topckgen CLK_TOP_USB_TOP_3P>;
+ assigned-clock-parents = <&topckgen CLK_TOP_UNIVPLL_D5_D4>,
+ <&topckgen CLK_TOP_UNIVPLL_D5_D4>;
+ clocks = <&pericfg_ao CLK_PERI_AO_SSUSB_3P_BUS>,
+ <&topckgen CLK_TOP_SSUSB_TOP_P3_REF>,
+ <&pericfg_ao CLK_PERI_AO_SSUSB_3P_XHCI>;
+ clock-names = "sys_ck", "ref_ck", "mcu_ck";
+ status = "disabled";
+ };
+
+ xhci0: usb@112b0000 {
+ compatible = "mediatek,mt8188-xhci", "mediatek,mtk-xhci";
+ reg = <0 0x112b0000 0 0x1000>,
+ <0 0x112b3e00 0 0x0100>;
+ reg-names = "mac", "ippc";
+ interrupts = <GIC_SPI 533 IRQ_TYPE_LEVEL_HIGH 0>;
+ phys = <&u2port0 PHY_TYPE_USB2>;
+ assigned-clocks = <&topckgen CLK_TOP_SSUSB_XHCI_2P>,
+ <&topckgen CLK_TOP_USB_TOP_2P>;
+ assigned-clock-parents = <&topckgen CLK_TOP_UNIVPLL_D5_D4>,
+ <&topckgen CLK_TOP_UNIVPLL_D5_D4>;
+ clocks = <&pericfg_ao CLK_PERI_AO_SSUSB_2P_BUS>,
+ <&topckgen CLK_TOP_SSUSB_TOP_P2_REF>,
+ <&pericfg_ao CLK_PERI_AO_SSUSB_2P_XHCI>;
+ clock-names = "sys_ck", "ref_ck", "mcu_ck";
+ mediatek,syscon-wakeup = <&pericfg 0x460 2>;
+ wakeup-source;
+ status = "disabled";
+ };
+
+ nor_flash: spi@1132c000 {
+ compatible = "mediatek,mt8188-nor", "mediatek,mt8186-nor";
+ reg = <0 0x1132c000 0 0x1000>;
+ clocks = <&topckgen CLK_TOP_SPINOR>,
+ <&pericfg_ao CLK_PERI_AO_FLASHIFLASHCK>,
+ <&pericfg_ao CLK_PERI_AO_FLASHIF_BUS>;
+ clock-names = "spi", "sf", "axi";
+ assigned-clocks = <&topckgen CLK_TOP_SPINOR>;
+ interrupts = <GIC_SPI 825 IRQ_TYPE_LEVEL_HIGH 0>;
+ status = "disabled";
+ };
+
+ i2c1: i2c@11e00000 {
+ compatible = "mediatek,mt8188-i2c";
+ reg = <0 0x11e00000 0 0x1000>,
+ <0 0x10220100 0 0x80>;
+ interrupts = <GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH 0>;
+ clock-div = <1>;
+ clocks = <&imp_iic_wrap_w CLK_IMP_IIC_WRAP_W_AP_CLOCK_I2C1>,
+ <&infracfg_ao CLK_INFRA_AO_APDMA_BCLK>;
+ clock-names = "main", "dma";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+ };
+
+ i2c4: i2c@11e01000 {
+ compatible = "mediatek,mt8188-i2c";
+ reg = <0 0x11e01000 0 0x1000>,
+ <0 0x10220380 0 0x80>;
+ interrupts = <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH 0>;
+ clock-div = <1>;
+ clocks = <&imp_iic_wrap_w CLK_IMP_IIC_WRAP_W_AP_CLOCK_I2C4>,
+ <&infracfg_ao CLK_INFRA_AO_APDMA_BCLK>;
+ clock-names = "main", "dma";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+ };
+
+ imp_iic_wrap_w: clock-controller@11e02000 {
+ compatible = "mediatek,mt8188-imp-iic-wrap-w";
+ reg = <0 0x11e02000 0 0x1000>;
+ #clock-cells = <1>;
+ };
+
+ u3phy0: t-phy@11e30000 {
+ compatible = "mediatek,mt8188-tphy", "mediatek,generic-tphy-v3";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0x0 0x0 0x11e30000 0x1000>;
+ status = "disabled";
+
+ u2port0: usb-phy@0 {
+ reg = <0x0 0x700>;
+ clocks = <&topckgen CLK_TOP_SSUSB_PHY_P2_REF>,
+ <&apmixedsys CLK_APMIXED_PLL_SSUSB26M_EN>;
+ clock-names = "ref", "da_ref";
+ #phy-cells = <1>;
+ };
+ };
+
+ u3phy1: t-phy@11e40000 {
+ compatible = "mediatek,mt8188-tphy", "mediatek,generic-tphy-v3";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0x0 0x0 0x11e40000 0x1000>;
+ status = "disabled";
+
+ u2port1: usb-phy@0 {
+ reg = <0x0 0x700>;
+ clocks = <&topckgen CLK_TOP_SSUSB_PHY_REF>,
+ <&apmixedsys CLK_APMIXED_PLL_SSUSB26M_EN>;
+ clock-names = "ref", "da_ref";
+ #phy-cells = <1>;
+ };
+
+ u3port1: usb-phy@700 {
+ reg = <0x700 0x700>;
+ clocks = <&apmixedsys CLK_APMIXED_PLL_SSUSB26M_EN>,
+ <&clk26m>;
+ clock-names = "ref", "da_ref";
+ #phy-cells = <1>;
+ status = "disabled";
+ };
+ };
+
+ u3phy2: t-phy@11e80000 {
+ compatible = "mediatek,mt8188-tphy", "mediatek,generic-tphy-v3";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0x0 0x0 0x11e80000 0x1000>;
+ status = "disabled";
+
+ u2port2: usb-phy@0 {
+ reg = <0x0 0x700>;
+ clocks = <&topckgen CLK_TOP_SSUSB_PHY_P3_REF>,
+ <&apmixedsys CLK_APMIXED_PLL_SSUSB26M_EN>;
+ clock-names = "ref", "da_ref";
+ #phy-cells = <1>;
+ };
+ };
+
+ i2c5: i2c@11ec0000 {
+ compatible = "mediatek,mt8188-i2c";
+ reg = <0 0x11ec0000 0 0x1000>,
+ <0 0x10220480 0 0x80>;
+ interrupts = <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH 0>;
+ clock-div = <1>;
+ clocks = <&imp_iic_wrap_en CLK_IMP_IIC_WRAP_EN_AP_CLOCK_I2C5>,
+ <&infracfg_ao CLK_INFRA_AO_APDMA_BCLK>;
+ clock-names = "main", "dma";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+ };
+
+ i2c6: i2c@11ec1000 {
+ compatible = "mediatek,mt8188-i2c";
+ reg = <0 0x11ec1000 0 0x1000>,
+ <0 0x10220600 0 0x80>;
+ interrupts = <GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH 0>;
+ clock-div = <1>;
+ clocks = <&imp_iic_wrap_en CLK_IMP_IIC_WRAP_EN_AP_CLOCK_I2C6>,
+ <&infracfg_ao CLK_INFRA_AO_APDMA_BCLK>;
+ clock-names = "main", "dma";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+ };
+
+ imp_iic_wrap_en: clock-controller@11ec2000 {
+ compatible = "mediatek,mt8188-imp-iic-wrap-en";
+ reg = <0 0x11ec2000 0 0x1000>;
+ #clock-cells = <1>;
+ };
+
+ mfgcfg: clock-controller@13fbf000 {
+ compatible = "mediatek,mt8188-mfgcfg";
+ reg = <0 0x13fbf000 0 0x1000>;
+ #clock-cells = <1>;
+ };
+
+ vppsys0: clock-controller@14000000 {
+ compatible = "mediatek,mt8188-vppsys0";
+ reg = <0 0x14000000 0 0x1000>;
+ #clock-cells = <1>;
+ };
+
+ wpesys: clock-controller@14e00000 {
+ compatible = "mediatek,mt8188-wpesys";
+ reg = <0 0x14e00000 0 0x1000>;
+ #clock-cells = <1>;
+ };
+
+ wpesys_vpp0: clock-controller@14e02000 {
+ compatible = "mediatek,mt8188-wpesys-vpp0";
+ reg = <0 0x14e02000 0 0x1000>;
+ #clock-cells = <1>;
+ };
+
+ vppsys1: clock-controller@14f00000 {
+ compatible = "mediatek,mt8188-vppsys1";
+ reg = <0 0x14f00000 0 0x1000>;
+ #clock-cells = <1>;
+ };
+
+ imgsys: clock-controller@15000000 {
+ compatible = "mediatek,mt8188-imgsys";
+ reg = <0 0x15000000 0 0x1000>;
+ #clock-cells = <1>;
+ };
+
+ imgsys1_dip_top: clock-controller@15110000 {
+ compatible = "mediatek,mt8188-imgsys1-dip-top";
+ reg = <0 0x15110000 0 0x1000>;
+ #clock-cells = <1>;
+ };
+
+ imgsys1_dip_nr: clock-controller@15130000 {
+ compatible = "mediatek,mt8188-imgsys1-dip-nr";
+ reg = <0 0x15130000 0 0x1000>;
+ #clock-cells = <1>;
+ };
+
+ imgsys_wpe1: clock-controller@15220000 {
+ compatible = "mediatek,mt8188-imgsys-wpe1";
+ reg = <0 0x15220000 0 0x1000>;
+ #clock-cells = <1>;
+ };
+
+ ipesys: clock-controller@15330000 {
+ compatible = "mediatek,mt8188-ipesys";
+ reg = <0 0x15330000 0 0x1000>;
+ #clock-cells = <1>;
+ };
+
+ imgsys_wpe2: clock-controller@15520000 {
+ compatible = "mediatek,mt8188-imgsys-wpe2";
+ reg = <0 0x15520000 0 0x1000>;
+ #clock-cells = <1>;
+ };
+
+ imgsys_wpe3: clock-controller@15620000 {
+ compatible = "mediatek,mt8188-imgsys-wpe3";
+ reg = <0 0x15620000 0 0x1000>;
+ #clock-cells = <1>;
+ };
+
+ camsys: clock-controller@16000000 {
+ compatible = "mediatek,mt8188-camsys";
+ reg = <0 0x16000000 0 0x1000>;
+ #clock-cells = <1>;
+ };
+
+ camsys_rawa: clock-controller@1604f000 {
+ compatible = "mediatek,mt8188-camsys-rawa";
+ reg = <0 0x1604f000 0 0x1000>;
+ #clock-cells = <1>;
+ };
+
+ camsys_yuva: clock-controller@1606f000 {
+ compatible = "mediatek,mt8188-camsys-yuva";
+ reg = <0 0x1606f000 0 0x1000>;
+ #clock-cells = <1>;
+ };
+
+ camsys_rawb: clock-controller@1608f000 {
+ compatible = "mediatek,mt8188-camsys-rawb";
+ reg = <0 0x1608f000 0 0x1000>;
+ #clock-cells = <1>;
+ };
+
+ camsys_yuvb: clock-controller@160af000 {
+ compatible = "mediatek,mt8188-camsys-yuvb";
+ reg = <0 0x160af000 0 0x1000>;
+ #clock-cells = <1>;
+ };
+
+ ccusys: clock-controller@17200000 {
+ compatible = "mediatek,mt8188-ccusys";
+ reg = <0 0x17200000 0 0x1000>;
+ #clock-cells = <1>;
+ };
+
+ vdecsys_soc: clock-controller@1800f000 {
+ compatible = "mediatek,mt8188-vdecsys-soc";
+ reg = <0 0x1800f000 0 0x1000>;
+ #clock-cells = <1>;
+ };
+
+ vdecsys: clock-controller@1802f000 {
+ compatible = "mediatek,mt8188-vdecsys";
+ reg = <0 0x1802f000 0 0x1000>;
+ #clock-cells = <1>;
+ };
+
+ vencsys: clock-controller@1a000000 {
+ compatible = "mediatek,mt8188-vencsys";
+ reg = <0 0x1a000000 0 0x1000>;
+ #clock-cells = <1>;
+ };
+ };
+};
diff --git a/dts/upstream/src/arm64/mediatek/mt8192-asurada.dtsi b/dts/upstream/src/arm64/mediatek/mt8192-asurada.dtsi
index f228125..d87aab8 100644
--- a/dts/upstream/src/arm64/mediatek/mt8192-asurada.dtsi
+++ b/dts/upstream/src/arm64/mediatek/mt8192-asurada.dtsi
@@ -1402,7 +1402,7 @@
pinctrl-names = "default";
pinctrl-0 = <&spi5_pins>;
- cr50@0 {
+ tpm@0 {
compatible = "google,cr50";
reg = <0>;
interrupts-extended = <&pio 171 IRQ_TYPE_EDGE_RISING>;
diff --git a/dts/upstream/src/arm64/mediatek/mt8192.dtsi b/dts/upstream/src/arm64/mediatek/mt8192.dtsi
index 69f4cde..6dd32db 100644
--- a/dts/upstream/src/arm64/mediatek/mt8192.dtsi
+++ b/dts/upstream/src/arm64/mediatek/mt8192.dtsi
@@ -14,6 +14,8 @@
#include <dt-bindings/phy/phy.h>
#include <dt-bindings/power/mt8192-power.h>
#include <dt-bindings/reset/mt8192-resets.h>
+#include <dt-bindings/thermal/thermal.h>
+#include <dt-bindings/thermal/mediatek,lvts-thermal.h>
/ {
compatible = "mediatek,mt8192";
@@ -72,6 +74,7 @@
next-level-cache = <&l2_0>;
performance-domains = <&performance 0>;
capacity-dmips-mhz = <427>;
+ #cooling-cells = <2>;
};
cpu1: cpu@100 {
@@ -90,6 +93,7 @@
next-level-cache = <&l2_0>;
performance-domains = <&performance 0>;
capacity-dmips-mhz = <427>;
+ #cooling-cells = <2>;
};
cpu2: cpu@200 {
@@ -108,6 +112,7 @@
next-level-cache = <&l2_0>;
performance-domains = <&performance 0>;
capacity-dmips-mhz = <427>;
+ #cooling-cells = <2>;
};
cpu3: cpu@300 {
@@ -126,6 +131,7 @@
next-level-cache = <&l2_0>;
performance-domains = <&performance 0>;
capacity-dmips-mhz = <427>;
+ #cooling-cells = <2>;
};
cpu4: cpu@400 {
@@ -144,6 +150,7 @@
next-level-cache = <&l2_1>;
performance-domains = <&performance 1>;
capacity-dmips-mhz = <1024>;
+ #cooling-cells = <2>;
};
cpu5: cpu@500 {
@@ -162,6 +169,7 @@
next-level-cache = <&l2_1>;
performance-domains = <&performance 1>;
capacity-dmips-mhz = <1024>;
+ #cooling-cells = <2>;
};
cpu6: cpu@600 {
@@ -180,6 +188,7 @@
next-level-cache = <&l2_1>;
performance-domains = <&performance 1>;
capacity-dmips-mhz = <1024>;
+ #cooling-cells = <2>;
};
cpu7: cpu@700 {
@@ -198,6 +207,7 @@
next-level-cache = <&l2_1>;
performance-domains = <&performance 1>;
capacity-dmips-mhz = <1024>;
+ #cooling-cells = <2>;
};
cpu-map {
@@ -788,6 +798,29 @@
status = "disabled";
};
+ lvts_ap: thermal-sensor@1100b000 {
+ compatible = "mediatek,mt8192-lvts-ap";
+ reg = <0 0x1100b000 0 0xc00>;
+ interrupts = <GIC_SPI 169 IRQ_TYPE_LEVEL_HIGH 0>;
+ clocks = <&infracfg CLK_INFRA_THERM>;
+ resets = <&infracfg MT8192_INFRA_RST0_THERM_CTRL_SWRST>;
+ nvmem-cells = <&lvts_e_data1>;
+ nvmem-cell-names = "lvts-calib-data-1";
+ #thermal-sensor-cells = <1>;
+ };
+
+ svs: svs@1100bc00 {
+ compatible = "mediatek,mt8192-svs";
+ reg = <0 0x1100bc00 0 0x400>;
+ interrupts = <GIC_SPI 167 IRQ_TYPE_LEVEL_HIGH 0>;
+ clocks = <&infracfg CLK_INFRA_THERM>;
+ clock-names = "main";
+ nvmem-cells = <&svs_calibration>, <&lvts_e_data1>;
+ nvmem-cell-names = "svs-calibration-data", "t-calibration-data";
+ resets = <&infracfg MT8192_INFRA_RST3_THERM_CTRL_PTP_SWRST>;
+ reset-names = "svs_rst";
+ };
+
pwm0: pwm@1100e000 {
compatible = "mediatek,mt8183-disp-pwm";
reg = <0 0x1100e000 0 0x1000>;
@@ -1114,6 +1147,17 @@
status = "disabled";
};
+ lvts_mcu: thermal-sensor@11278000 {
+ compatible = "mediatek,mt8192-lvts-mcu";
+ reg = <0 0x11278000 0 0x1000>;
+ interrupts = <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH 0>;
+ clocks = <&infracfg CLK_INFRA_THERM>;
+ resets = <&infracfg MT8192_INFRA_RST4_THERM_CTRL_MCU_SWRST>;
+ nvmem-cells = <&lvts_e_data1>;
+ nvmem-cell-names = "lvts-calib-data-1";
+ #thermal-sensor-cells = <1>;
+ };
+
efuse: efuse@11c10000 {
compatible = "mediatek,mt8192-efuse", "mediatek,efuse";
reg = <0 0x11c10000 0 0x1000>;
@@ -1899,4 +1943,426 @@
power-domains = <&spm MT8192_POWER_DOMAIN_MDP>;
};
};
+
+ thermal_zones: thermal-zones {
+ cpu0-thermal {
+ polling-delay = <1000>;
+ polling-delay-passive = <250>;
+ thermal-sensors = <&lvts_mcu MT8192_MCU_LITTLE_CPU0>;
+
+ trips {
+ cpu0_alert: trip-alert {
+ temperature = <85000>;
+ hysteresis = <2000>;
+ type = "passive";
+ };
+
+ cpu0_crit: trip-crit {
+ temperature = <100000>;
+ hysteresis = <2000>;
+ type = "critical";
+ };
+ };
+
+ cooling-maps {
+ map0 {
+ trip = <&cpu0_alert>;
+ cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+ <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+ <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+ <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
+ };
+ };
+ };
+
+ cpu1-thermal {
+ polling-delay = <1000>;
+ polling-delay-passive = <250>;
+ thermal-sensors = <&lvts_mcu MT8192_MCU_LITTLE_CPU1>;
+
+ trips {
+ cpu1_alert: trip-alert {
+ temperature = <85000>;
+ hysteresis = <2000>;
+ type = "passive";
+ };
+
+ cpu1_crit: trip-crit {
+ temperature = <100000>;
+ hysteresis = <2000>;
+ type = "critical";
+ };
+ };
+
+ cooling-maps {
+ map0 {
+ trip = <&cpu1_alert>;
+ cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+ <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+ <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+ <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
+ };
+ };
+ };
+
+ cpu2-thermal {
+ polling-delay = <1000>;
+ polling-delay-passive = <250>;
+ thermal-sensors = <&lvts_mcu MT8192_MCU_LITTLE_CPU2>;
+
+ trips {
+ cpu2_alert: trip-alert {
+ temperature = <85000>;
+ hysteresis = <2000>;
+ type = "passive";
+ };
+
+ cpu2_crit: trip-crit {
+ temperature = <100000>;
+ hysteresis = <2000>;
+ type = "critical";
+ };
+ };
+
+ cooling-maps {
+ map0 {
+ trip = <&cpu2_alert>;
+ cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+ <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+ <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+ <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
+ };
+ };
+ };
+
+ cpu3-thermal {
+ polling-delay = <1000>;
+ polling-delay-passive = <250>;
+ thermal-sensors = <&lvts_mcu MT8192_MCU_LITTLE_CPU3>;
+
+ trips {
+ cpu3_alert: trip-alert {
+ temperature = <85000>;
+ hysteresis = <2000>;
+ type = "passive";
+ };
+
+ cpu3_crit: trip-crit {
+ temperature = <100000>;
+ hysteresis = <2000>;
+ type = "critical";
+ };
+ };
+
+ cooling-maps {
+ map0 {
+ trip = <&cpu3_alert>;
+ cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+ <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+ <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+ <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
+ };
+ };
+ };
+
+ cpu4-thermal {
+ polling-delay = <1000>;
+ polling-delay-passive = <250>;
+ thermal-sensors = <&lvts_mcu MT8192_MCU_BIG_CPU0>;
+
+ trips {
+ cpu4_alert: trip-alert {
+ temperature = <85000>;
+ hysteresis = <2000>;
+ type = "passive";
+ };
+
+ cpu4_crit: trip-crit {
+ temperature = <100000>;
+ hysteresis = <2000>;
+ type = "critical";
+ };
+ };
+
+ cooling-maps {
+ map0 {
+ trip = <&cpu4_alert>;
+ cooling-device = <&cpu4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+ <&cpu5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+ <&cpu6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+ <&cpu7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
+ };
+ };
+ };
+
+ cpu5-thermal {
+ polling-delay = <1000>;
+ polling-delay-passive = <250>;
+ thermal-sensors = <&lvts_mcu MT8192_MCU_BIG_CPU1>;
+
+ trips {
+ cpu5_alert: trip-alert {
+ temperature = <85000>;
+ hysteresis = <2000>;
+ type = "passive";
+ };
+
+ cpu5_crit: trip-crit {
+ temperature = <100000>;
+ hysteresis = <2000>;
+ type = "critical";
+ };
+ };
+
+ cooling-maps {
+ map0 {
+ trip = <&cpu5_alert>;
+ cooling-device = <&cpu4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+ <&cpu5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+ <&cpu6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+ <&cpu7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
+ };
+ };
+ };
+
+ cpu6-thermal {
+ polling-delay = <1000>;
+ polling-delay-passive = <250>;
+ thermal-sensors = <&lvts_mcu MT8192_MCU_BIG_CPU2>;
+
+ trips {
+ cpu6_alert: trip-alert {
+ temperature = <85000>;
+ hysteresis = <2000>;
+ type = "passive";
+ };
+
+ cpu6_crit: trip-crit {
+ temperature = <100000>;
+ hysteresis = <2000>;
+ type = "critical";
+ };
+ };
+
+ cooling-maps {
+ map0 {
+ trip = <&cpu6_alert>;
+ cooling-device = <&cpu4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+ <&cpu5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+ <&cpu6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+ <&cpu7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
+ };
+ };
+ };
+
+ cpu7-thermal {
+ polling-delay = <1000>;
+ polling-delay-passive = <250>;
+ thermal-sensors = <&lvts_mcu MT8192_MCU_BIG_CPU3>;
+
+ trips {
+ cpu7_alert: trip-alert {
+ temperature = <85000>;
+ hysteresis = <2000>;
+ type = "passive";
+ };
+
+ cpu7_crit: trip-crit {
+ temperature = <100000>;
+ hysteresis = <2000>;
+ type = "critical";
+ };
+ };
+
+ cooling-maps {
+ map0 {
+ trip = <&cpu7_alert>;
+ cooling-device = <&cpu4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+ <&cpu5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+ <&cpu6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+ <&cpu7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
+ };
+ };
+ };
+
+ vpu0-thermal {
+ polling-delay = <1000>;
+ polling-delay-passive = <250>;
+ thermal-sensors = <&lvts_ap MT8192_AP_VPU0>;
+
+ trips {
+ vpu0_alert: trip-alert {
+ temperature = <85000>;
+ hysteresis = <2000>;
+ type = "passive";
+ };
+
+ vpu0_crit: trip-crit {
+ temperature = <100000>;
+ hysteresis = <2000>;
+ type = "critical";
+ };
+ };
+ };
+
+ vpu1-thermal {
+ polling-delay = <1000>;
+ polling-delay-passive = <250>;
+ thermal-sensors = <&lvts_ap MT8192_AP_VPU1>;
+
+ trips {
+ vpu1_alert: trip-alert {
+ temperature = <85000>;
+ hysteresis = <2000>;
+ type = "passive";
+ };
+
+ vpu1_crit: trip-crit {
+ temperature = <100000>;
+ hysteresis = <2000>;
+ type = "critical";
+ };
+ };
+ };
+
+ gpu0-thermal {
+ polling-delay = <1000>;
+ polling-delay-passive = <250>;
+ thermal-sensors = <&lvts_ap MT8192_AP_GPU0>;
+
+ trips {
+ gpu0_alert: trip-alert {
+ temperature = <85000>;
+ hysteresis = <2000>;
+ type = "passive";
+ };
+
+ gpu0_crit: trip-crit {
+ temperature = <100000>;
+ hysteresis = <2000>;
+ type = "critical";
+ };
+ };
+ };
+
+ gpu1-thermal {
+ polling-delay = <1000>;
+ polling-delay-passive = <250>;
+ thermal-sensors = <&lvts_ap MT8192_AP_GPU1>;
+
+ trips {
+ gpu1_alert: trip-alert {
+ temperature = <85000>;
+ hysteresis = <2000>;
+ type = "passive";
+ };
+
+ gpu1_crit: trip-crit {
+ temperature = <100000>;
+ hysteresis = <2000>;
+ type = "critical";
+ };
+ };
+ };
+
+ infra-thermal {
+ polling-delay = <1000>;
+ polling-delay-passive = <250>;
+ thermal-sensors = <&lvts_ap MT8192_AP_INFRA>;
+
+ trips {
+ infra_alert: trip-alert {
+ temperature = <85000>;
+ hysteresis = <2000>;
+ type = "passive";
+ };
+
+ infra_crit: trip-crit {
+ temperature = <100000>;
+ hysteresis = <2000>;
+ type = "critical";
+ };
+ };
+ };
+
+ cam-thermal {
+ polling-delay = <1000>;
+ polling-delay-passive = <250>;
+ thermal-sensors = <&lvts_ap MT8192_AP_CAM>;
+
+ trips {
+ cam_alert: trip-alert {
+ temperature = <85000>;
+ hysteresis = <2000>;
+ type = "passive";
+ };
+
+ cam_crit: trip-crit {
+ temperature = <100000>;
+ hysteresis = <2000>;
+ type = "critical";
+ };
+ };
+ };
+
+ md0-thermal {
+ polling-delay = <1000>;
+ polling-delay-passive = <250>;
+ thermal-sensors = <&lvts_ap MT8192_AP_MD0>;
+
+ trips {
+ md0_alert: trip-alert {
+ temperature = <85000>;
+ hysteresis = <2000>;
+ type = "passive";
+ };
+
+ md0_crit: trip-crit {
+ temperature = <100000>;
+ hysteresis = <2000>;
+ type = "critical";
+ };
+ };
+ };
+
+ md1-thermal {
+ polling-delay = <1000>;
+ polling-delay-passive = <250>;
+ thermal-sensors = <&lvts_ap MT8192_AP_MD1>;
+
+ trips {
+ md1_alert: trip-alert {
+ temperature = <85000>;
+ hysteresis = <2000>;
+ type = "passive";
+ };
+
+ md1_crit: trip-crit {
+ temperature = <100000>;
+ hysteresis = <2000>;
+ type = "critical";
+ };
+ };
+ };
+
+ md2-thermal {
+ polling-delay = <1000>;
+ polling-delay-passive = <250>;
+ thermal-sensors = <&lvts_ap MT8192_AP_MD2>;
+
+ trips {
+ md2_alert: trip-alert {
+ temperature = <85000>;
+ hysteresis = <2000>;
+ type = "passive";
+ };
+
+ md2_crit: trip-crit {
+ temperature = <100000>;
+ hysteresis = <2000>;
+ type = "critical";
+ };
+ };
+ };
+ };
};
diff --git a/dts/upstream/src/arm64/mediatek/mt8195-cherry.dtsi b/dts/upstream/src/arm64/mediatek/mt8195-cherry.dtsi
index 5a7cab4..3c6079e 100644
--- a/dts/upstream/src/arm64/mediatek/mt8195-cherry.dtsi
+++ b/dts/upstream/src/arm64/mediatek/mt8195-cherry.dtsi
@@ -127,6 +127,77 @@
regulator-boot-on;
};
+ /* Murata NCP03WF104F05RL */
+ tboard_thermistor1: thermal-sensor-t1 {
+ compatible = "generic-adc-thermal";
+ #thermal-sensor-cells = <0>;
+ io-channels = <&auxadc 0>;
+ io-channel-names = "sensor-channel";
+ temperature-lookup-table = < (-10000) 1553
+ (-5000) 1485
+ 0 1406
+ 5000 1317
+ 10000 1219
+ 15000 1115
+ 20000 1007
+ 25000 900
+ 30000 796
+ 35000 697
+ 40000 605
+ 45000 523
+ 50000 449
+ 55000 384
+ 60000 327
+ 65000 279
+ 70000 237
+ 75000 202
+ 80000 172
+ 85000 147
+ 90000 125
+ 95000 107
+ 100000 92
+ 105000 79
+ 110000 68
+ 115000 59
+ 120000 51
+ 125000 44>;
+ };
+
+ tboard_thermistor2: thermal-sensor-t2 {
+ compatible = "generic-adc-thermal";
+ #thermal-sensor-cells = <0>;
+ io-channels = <&auxadc 1>;
+ io-channel-names = "sensor-channel";
+ temperature-lookup-table = < (-10000) 1553
+ (-5000) 1485
+ 0 1406
+ 5000 1317
+ 10000 1219
+ 15000 1115
+ 20000 1007
+ 25000 900
+ 30000 796
+ 35000 697
+ 40000 605
+ 45000 523
+ 50000 449
+ 55000 384
+ 60000 327
+ 65000 279
+ 70000 237
+ 75000 202
+ 80000 172
+ 85000 147
+ 90000 125
+ 95000 107
+ 100000 92
+ 105000 79
+ 110000 68
+ 115000 59
+ 120000 51
+ 125000 44>;
+ };
+
usb_vbus: regulator-5v0-usb-vbus {
compatible = "regulator-fixed";
regulator-name = "usb-vbus";
@@ -189,6 +260,10 @@
memory-region = <&afe_mem>;
};
+&auxadc {
+ status = "okay";
+};
+
&dp_intf0 {
status = "okay";
@@ -401,6 +476,14 @@
};
};
+&mfg0 {
+ domain-supply = <&mt6315_7_vbuck1>;
+};
+
+&mfg1 {
+ domain-supply = <&mt6359_vsram_others_ldo_reg>;
+};
+
&mmc0 {
status = "okay";
@@ -471,7 +554,6 @@
/* for GPU SRAM */
&mt6359_vsram_others_ldo_reg {
- regulator-always-on;
regulator-min-microvolt = <750000>;
regulator-max-microvolt = <750000>;
};
@@ -1154,7 +1236,36 @@
regulator-enable-ramp-delay = <256>;
regulator-ramp-delay = <6250>;
regulator-allowed-modes = <0 1 2>;
- regulator-always-on;
+ };
+ };
+ };
+};
+
+&thermal_zones {
+ soc-area-thermal {
+ polling-delay = <1000>;
+ polling-delay-passive = <250>;
+ thermal-sensors = <&tboard_thermistor1>;
+
+ trips {
+ trip-crit {
+ temperature = <84000>;
+ hysteresis = <1000>;
+ type = "critical";
+ };
+ };
+ };
+
+ pmic-area-thermal {
+ polling-delay = <1000>;
+ polling-delay-passive = <0>;
+ thermal-sensors = <&tboard_thermistor2>;
+
+ trips {
+ trip-crit {
+ temperature = <84000>;
+ hysteresis = <1000>;
+ type = "critical";
};
};
};
@@ -1183,6 +1294,7 @@
&xhci0 {
status = "okay";
+ rx-fifo-depth = <3072>;
vusb33-supply = <&mt6359_vusb_ldo_reg>;
vbus-supply = <&usb_vbus>;
};
@@ -1190,6 +1302,7 @@
&xhci1 {
status = "okay";
+ rx-fifo-depth = <3072>;
vusb33-supply = <&mt6359_vusb_ldo_reg>;
vbus-supply = <&usb_vbus>;
};
diff --git a/dts/upstream/src/arm64/mediatek/mt8195-demo.dts b/dts/upstream/src/arm64/mediatek/mt8195-demo.dts
index 69c7f39..4127cb8 100644
--- a/dts/upstream/src/arm64/mediatek/mt8195-demo.dts
+++ b/dts/upstream/src/arm64/mediatek/mt8195-demo.dts
@@ -128,6 +128,7 @@
compatible = "mediatek,mt6360";
reg = <0x34>;
interrupt-controller;
+ #interrupt-cells = <1>;
interrupts-extended = <&pio 101 IRQ_TYPE_EDGE_FALLING>;
interrupt-names = "IRQB";
diff --git a/dts/upstream/src/arm64/mediatek/mt8195.dtsi b/dts/upstream/src/arm64/mediatek/mt8195.dtsi
index e0ac2e9..b910166 100644
--- a/dts/upstream/src/arm64/mediatek/mt8195.dtsi
+++ b/dts/upstream/src/arm64/mediatek/mt8195.dtsi
@@ -538,7 +538,7 @@
#size-cells = <0>;
#power-domain-cells = <1>;
- power-domain@MT8195_POWER_DOMAIN_MFG1 {
+ mfg1: power-domain@MT8195_POWER_DOMAIN_MFG1 {
reg = <MT8195_POWER_DOMAIN_MFG1>;
clocks = <&apmixedsys CLK_APMIXED_MFGPLL>,
<&topckgen CLK_TOP_MFG_CORE_TMP>;
@@ -1119,7 +1119,7 @@
lvts_ap: thermal-sensor@1100b000 {
compatible = "mediatek,mt8195-lvts-ap";
- reg = <0 0x1100b000 0 0x1000>;
+ reg = <0 0x1100b000 0 0xc00>;
interrupts = <GIC_SPI 169 IRQ_TYPE_LEVEL_HIGH 0>;
clocks = <&infracfg_ao CLK_INFRA_AO_THERM>;
resets = <&infracfg_ao MT8195_INFRA_RST0_THERM_CTRL_SWRST>;
@@ -1128,6 +1128,18 @@
#thermal-sensor-cells = <1>;
};
+ svs: svs@1100bc00 {
+ compatible = "mediatek,mt8195-svs";
+ reg = <0 0x1100bc00 0 0x400>;
+ interrupts = <GIC_SPI 199 IRQ_TYPE_LEVEL_HIGH 0>;
+ clocks = <&infracfg_ao CLK_INFRA_AO_THERM>;
+ clock-names = "main";
+ nvmem-cells = <&svs_calib_data &lvts_efuse_data1>;
+ nvmem-cell-names = "svs-calibration-data", "t-calibration-data";
+ resets = <&infracfg_ao MT8195_INFRA_RST3_THERM_CTRL_PTP_SWRST>;
+ reset-names = "svs_rst";
+ };
+
disp_pwm0: pwm@1100e000 {
compatible = "mediatek,mt8195-disp-pwm", "mediatek,mt8183-disp-pwm";
reg = <0 0x1100e000 0 0x1000>;
@@ -1686,6 +1698,9 @@
lvts_efuse_data2: lvts2-calib@1d0 {
reg = <0x1d0 0x38>;
};
+ svs_calib_data: svs-calib@580 {
+ reg = <0x580 0x64>;
+ };
};
u3phy2: t-phy@11c40000 {
@@ -1718,6 +1733,26 @@
};
};
+ mipi_tx0: dsi-phy@11c80000 {
+ compatible = "mediatek,mt8195-mipi-tx", "mediatek,mt8183-mipi-tx";
+ reg = <0 0x11c80000 0 0x1000>;
+ clocks = <&clk26m>;
+ clock-output-names = "mipi_tx0_pll";
+ #clock-cells = <0>;
+ #phy-cells = <0>;
+ status = "disabled";
+ };
+
+ mipi_tx1: dsi-phy@11c90000 {
+ compatible = "mediatek,mt8195-mipi-tx", "mediatek,mt8183-mipi-tx";
+ reg = <0 0x11c90000 0 0x1000>;
+ clocks = <&clk26m>;
+ clock-output-names = "mipi_tx1_pll";
+ #clock-cells = <0>;
+ #phy-cells = <0>;
+ status = "disabled";
+ };
+
i2c5: i2c@11d00000 {
compatible = "mediatek,mt8195-i2c",
"mediatek,mt8192-i2c";
@@ -1965,6 +2000,115 @@
#clock-cells = <1>;
};
+ dma-controller@14001000 {
+ compatible = "mediatek,mt8195-mdp3-rdma";
+ reg = <0 0x14001000 0 0x1000>;
+ mediatek,gce-client-reg = <&gce1 SUBSYS_1400XXXX 0x1000 0x1000>;
+ mediatek,gce-events = <CMDQ_EVENT_VPP0_MDP_RDMA_SOF>,
+ <CMDQ_EVENT_VPP0_MDP_RDMA_FRAME_DONE>;
+ power-domains = <&spm MT8195_POWER_DOMAIN_VPPSYS0>;
+ iommus = <&iommu_vpp M4U_PORT_L4_MDP_RDMA>;
+ clocks = <&vppsys0 CLK_VPP0_MDP_RDMA>;
+ mboxes = <&gce1 12 CMDQ_THR_PRIO_1>,
+ <&gce1 13 CMDQ_THR_PRIO_1>,
+ <&gce1 14 CMDQ_THR_PRIO_1>,
+ <&gce1 21 CMDQ_THR_PRIO_1>,
+ <&gce1 22 CMDQ_THR_PRIO_1>;
+ #dma-cells = <1>;
+ };
+
+ display@14002000 {
+ compatible = "mediatek,mt8195-mdp3-fg";
+ reg = <0 0x14002000 0 0x1000>;
+ mediatek,gce-client-reg = <&gce1 SUBSYS_1400XXXX 0x2000 0x1000>;
+ clocks = <&vppsys0 CLK_VPP0_MDP_FG>;
+ };
+
+ display@14003000 {
+ compatible = "mediatek,mt8195-mdp3-stitch";
+ reg = <0 0x14003000 0 0x1000>;
+ mediatek,gce-client-reg = <&gce1 SUBSYS_1400XXXX 0x3000 0x1000>;
+ clocks = <&vppsys0 CLK_VPP0_STITCH>;
+ };
+
+ display@14004000 {
+ compatible = "mediatek,mt8195-mdp3-hdr";
+ reg = <0 0x14004000 0 0x1000>;
+ mediatek,gce-client-reg = <&gce1 SUBSYS_1400XXXX 0x4000 0x1000>;
+ clocks = <&vppsys0 CLK_VPP0_MDP_HDR>;
+ };
+
+ display@14005000 {
+ compatible = "mediatek,mt8195-mdp3-aal";
+ reg = <0 0x14005000 0 0x1000>;
+ interrupts = <GIC_SPI 582 IRQ_TYPE_LEVEL_HIGH 0>;
+ mediatek,gce-client-reg = <&gce1 SUBSYS_1400XXXX 0x5000 0x1000>;
+ clocks = <&vppsys0 CLK_VPP0_MDP_AAL>;
+ power-domains = <&spm MT8195_POWER_DOMAIN_VPPSYS0>;
+ };
+
+ display@14006000 {
+ compatible = "mediatek,mt8195-mdp3-rsz", "mediatek,mt8183-mdp3-rsz";
+ reg = <0 0x14006000 0 0x1000>;
+ mediatek,gce-client-reg = <&gce1 SUBSYS_1400XXXX 0x6000 0x1000>;
+ mediatek,gce-events = <CMDQ_EVENT_VPP0_MDP_RSZ_IN_RSZ_SOF>,
+ <CMDQ_EVENT_VPP0_MDP_RSZ_FRAME_DONE>;
+ clocks = <&vppsys0 CLK_VPP0_MDP_RSZ>;
+ };
+
+ display@14007000 {
+ compatible = "mediatek,mt8195-mdp3-tdshp";
+ reg = <0 0x14007000 0 0x1000>;
+ mediatek,gce-client-reg = <&gce1 SUBSYS_1400XXXX 0x7000 0x1000>;
+ clocks = <&vppsys0 CLK_VPP0_MDP_TDSHP>;
+ };
+
+ display@14008000 {
+ compatible = "mediatek,mt8195-mdp3-color";
+ reg = <0 0x14008000 0 0x1000>;
+ interrupts = <GIC_SPI 585 IRQ_TYPE_LEVEL_HIGH 0>;
+ mediatek,gce-client-reg = <&gce1 SUBSYS_1400XXXX 0x8000 0x1000>;
+ clocks = <&vppsys0 CLK_VPP0_MDP_COLOR>;
+ power-domains = <&spm MT8195_POWER_DOMAIN_VPPSYS0>;
+ };
+
+ display@14009000 {
+ compatible = "mediatek,mt8195-mdp3-ovl";
+ reg = <0 0x14009000 0 0x1000>;
+ interrupts = <GIC_SPI 586 IRQ_TYPE_LEVEL_HIGH 0>;
+ mediatek,gce-client-reg = <&gce1 SUBSYS_1400XXXX 0x9000 0x1000>;
+ clocks = <&vppsys0 CLK_VPP0_MDP_OVL>;
+ power-domains = <&spm MT8195_POWER_DOMAIN_VPPSYS0>;
+ iommus = <&iommu_vpp M4U_PORT_L4_MDP_OVL>;
+ };
+
+ display@1400a000 {
+ compatible = "mediatek,mt8195-mdp3-padding";
+ reg = <0 0x1400a000 0 0x1000>;
+ mediatek,gce-client-reg = <&gce1 SUBSYS_1400XXXX 0xa000 0x1000>;
+ clocks = <&vppsys0 CLK_VPP0_PADDING>;
+ power-domains = <&spm MT8195_POWER_DOMAIN_VPPSYS0>;
+ };
+
+ display@1400b000 {
+ compatible = "mediatek,mt8195-mdp3-tcc";
+ reg = <0 0x1400b000 0 0x1000>;
+ mediatek,gce-client-reg = <&gce1 SUBSYS_1400XXXX 0xb000 0x1000>;
+ clocks = <&vppsys0 CLK_VPP0_MDP_TCC>;
+ };
+
+ dma-controller@1400c000 {
+ compatible = "mediatek,mt8195-mdp3-wrot", "mediatek,mt8183-mdp3-wrot";
+ reg = <0 0x1400c000 0 0x1000>;
+ mediatek,gce-client-reg = <&gce1 SUBSYS_1400XXXX 0xc000 0x1000>;
+ mediatek,gce-events = <CMDQ_EVENT_VPP0_MDP_WROT_SOF>,
+ <CMDQ_EVENT_VPP0_MDP_WROT_VIDO_WDONE>;
+ clocks = <&vppsys0 CLK_VPP0_MDP_WROT>;
+ iommus = <&iommu_vpp M4U_PORT_L4_MDP_WROT>;
+ power-domains = <&spm MT8195_POWER_DOMAIN_VPPSYS0>;
+ #dma-cells = <1>;
+ };
+
mutex@1400f000 {
compatible = "mediatek,mt8195-vpp-mutex";
reg = <0 0x1400f000 0 0x1000>;
@@ -2112,6 +2256,289 @@
power-domains = <&spm MT8195_POWER_DOMAIN_VPPSYS1>;
};
+ display@14f06000 {
+ compatible = "mediatek,mt8195-mdp3-split";
+ reg = <0 0x14f06000 0 0x1000>;
+ mediatek,gce-client-reg = <&gce1 SUBSYS_14f0XXXX 0x6000 0x1000>;
+ clocks = <&vppsys1 CLK_VPP1_VPP_SPLIT>,
+ <&vppsys1 CLK_VPP1_HDMI_META>,
+ <&vppsys1 CLK_VPP1_VPP_SPLIT_HDMI>;
+ power-domains = <&spm MT8195_POWER_DOMAIN_VPPSYS1>;
+ };
+
+ display@14f07000 {
+ compatible = "mediatek,mt8195-mdp3-tcc";
+ reg = <0 0x14f07000 0 0x1000>;
+ mediatek,gce-client-reg = <&gce1 SUBSYS_14f0XXXX 0x7000 0x1000>;
+ clocks = <&vppsys1 CLK_VPP1_SVPP1_MDP_TCC>;
+ };
+
+ dma-controller@14f08000 {
+ compatible = "mediatek,mt8195-mdp3-rdma";
+ reg = <0 0x14f08000 0 0x1000>;
+ mediatek,gce-client-reg = <&gce1 SUBSYS_14f0XXXX 0x8000 0x1000>;
+ mediatek,gce-events = <CMDQ_EVENT_VPP1_SVPP1_MDP_RDMA_SOF>,
+ <CMDQ_EVENT_VPP1_SVPP1_MDP_RDMA_FRAME_DONE>;
+ clocks = <&vppsys1 CLK_VPP1_SVPP1_MDP_RDMA>;
+ iommus = <&iommu_vdo M4U_PORT_L5_SVPP1_MDP_RDMA>;
+ power-domains = <&spm MT8195_POWER_DOMAIN_VPPSYS1>;
+ #dma-cells = <1>;
+ };
+
+ dma-controller@14f09000 {
+ compatible = "mediatek,mt8195-mdp3-rdma";
+ reg = <0 0x14f09000 0 0x1000>;
+ mediatek,gce-client-reg = <&gce1 SUBSYS_14f0XXXX 0x9000 0x1000>;
+ mediatek,gce-events = <CMDQ_EVENT_VPP1_SVPP2_MDP_RDMA_SOF>,
+ <CMDQ_EVENT_VPP1_SVPP2_MDP_RDMA_FRAME_DONE>;
+ clocks = <&vppsys1 CLK_VPP1_SVPP2_MDP_RDMA>;
+ iommus = <&iommu_vdo M4U_PORT_L5_SVPP2_MDP_RDMA>;
+ power-domains = <&spm MT8195_POWER_DOMAIN_VPPSYS1>;
+ #dma-cells = <1>;
+ };
+
+ dma-controller@14f0a000 {
+ compatible = "mediatek,mt8195-mdp3-rdma";
+ reg = <0 0x14f0a000 0 0x1000>;
+ mediatek,gce-client-reg = <&gce1 SUBSYS_14f0XXXX 0xa000 0x1000>;
+ mediatek,gce-events = <CMDQ_EVENT_VPP1_SVPP3_MDP_RDMA_SOF>,
+ <CMDQ_EVENT_VPP1_SVPP3_MDP_RDMA_FRAME_DONE>;
+ clocks = <&vppsys1 CLK_VPP1_SVPP3_MDP_RDMA>;
+ iommus = <&iommu_vpp M4U_PORT_L6_SVPP3_MDP_RDMA>;
+ power-domains = <&spm MT8195_POWER_DOMAIN_VPPSYS1>;
+ #dma-cells = <1>;
+ };
+
+ display@14f0b000 {
+ compatible = "mediatek,mt8195-mdp3-fg";
+ reg = <0 0x14f0b000 0 0x1000>;
+ mediatek,gce-client-reg = <&gce1 SUBSYS_14f0XXXX 0xb000 0x1000>;
+ clocks = <&vppsys1 CLK_VPP1_SVPP1_MDP_FG>;
+ };
+
+ display@14f0c000 {
+ compatible = "mediatek,mt8195-mdp3-fg";
+ reg = <0 0x14f0c000 0 0x1000>;
+ mediatek,gce-client-reg = <&gce1 SUBSYS_14f0XXXX 0xc000 0x1000>;
+ clocks = <&vppsys1 CLK_VPP1_SVPP2_MDP_FG>;
+ };
+
+ display@14f0d000 {
+ compatible = "mediatek,mt8195-mdp3-fg";
+ reg = <0 0x14f0d000 0 0x1000>;
+ mediatek,gce-client-reg = <&gce1 SUBSYS_14f0XXXX 0xd000 0x1000>;
+ clocks = <&vppsys1 CLK_VPP1_SVPP3_MDP_FG>;
+ };
+
+ display@14f0e000 {
+ compatible = "mediatek,mt8195-mdp3-hdr";
+ reg = <0 0x14f0e000 0 0x1000>;
+ mediatek,gce-client-reg = <&gce1 SUBSYS_14f0XXXX 0xe000 0x1000>;
+ clocks = <&vppsys1 CLK_VPP1_SVPP1_MDP_HDR>;
+ };
+
+ display@14f0f000 {
+ compatible = "mediatek,mt8195-mdp3-hdr";
+ reg = <0 0x14f0f000 0 0x1000>;
+ mediatek,gce-client-reg = <&gce1 SUBSYS_14f0XXXX 0xf000 0x1000>;
+ clocks = <&vppsys1 CLK_VPP1_SVPP2_MDP_HDR>;
+ };
+
+ display@14f10000 {
+ compatible = "mediatek,mt8195-mdp3-hdr";
+ reg = <0 0x14f10000 0 0x1000>;
+ mediatek,gce-client-reg = <&gce1 SUBSYS_14f1XXXX 0 0x1000>;
+ clocks = <&vppsys1 CLK_VPP1_SVPP3_MDP_HDR>;
+ };
+
+ display@14f11000 {
+ compatible = "mediatek,mt8195-mdp3-aal";
+ reg = <0 0x14f11000 0 0x1000>;
+ interrupts = <GIC_SPI 617 IRQ_TYPE_LEVEL_HIGH 0>;
+ mediatek,gce-client-reg = <&gce1 SUBSYS_14f1XXXX 0x1000 0x1000>;
+ clocks = <&vppsys1 CLK_VPP1_SVPP1_MDP_AAL>;
+ power-domains = <&spm MT8195_POWER_DOMAIN_VPPSYS1>;
+ };
+
+ display@14f12000 {
+ compatible = "mediatek,mt8195-mdp3-aal";
+ reg = <0 0x14f12000 0 0x1000>;
+ interrupts = <GIC_SPI 618 IRQ_TYPE_LEVEL_HIGH 0>;
+ mediatek,gce-client-reg = <&gce1 SUBSYS_14f1XXXX 0x2000 0x1000>;
+ clocks = <&vppsys1 CLK_VPP1_SVPP2_MDP_AAL>;
+ power-domains = <&spm MT8195_POWER_DOMAIN_VPPSYS1>;
+ };
+
+ display@14f13000 {
+ compatible = "mediatek,mt8195-mdp3-aal";
+ reg = <0 0x14f13000 0 0x1000>;
+ interrupts = <GIC_SPI 619 IRQ_TYPE_LEVEL_HIGH 0>;
+ mediatek,gce-client-reg = <&gce1 SUBSYS_14f1XXXX 0x3000 0x1000>;
+ clocks = <&vppsys1 CLK_VPP1_SVPP3_MDP_AAL>;
+ power-domains = <&spm MT8195_POWER_DOMAIN_VPPSYS1>;
+ };
+
+ display@14f14000 {
+ compatible = "mediatek,mt8195-mdp3-rsz", "mediatek,mt8183-mdp3-rsz";
+ reg = <0 0x14f14000 0 0x1000>;
+ mediatek,gce-client-reg = <&gce1 SUBSYS_14f1XXXX 0x4000 0x1000>;
+ mediatek,gce-events = <CMDQ_EVENT_VPP1_SVPP1_MDP_RSZ_SOF>,
+ <CMDQ_EVENT_VPP1_SVPP1_MDP_RSZ_FRAME_DONE>;
+ clocks = <&vppsys1 CLK_VPP1_SVPP1_MDP_RSZ>;
+ };
+
+ display@14f15000 {
+ compatible = "mediatek,mt8195-mdp3-rsz", "mediatek,mt8183-mdp3-rsz";
+ reg = <0 0x14f15000 0 0x1000>;
+ mediatek,gce-client-reg = <&gce1 SUBSYS_14f1XXXX 0x5000 0x1000>;
+ mediatek,gce-events = <CMDQ_EVENT_VPP1_SVPP2_MDP_RSZ_SOF>,
+ <CMDQ_EVENT_VPP1_SVPP2_MDP_RSZ_FRAME_DONE>;
+ clocks = <&vppsys1 CLK_VPP1_SVPP2_MDP_RSZ>;
+ };
+
+ display@14f16000 {
+ compatible = "mediatek,mt8195-mdp3-rsz", "mediatek,mt8183-mdp3-rsz";
+ reg = <0 0x14f16000 0 0x1000>;
+ mediatek,gce-client-reg = <&gce1 SUBSYS_14f1XXXX 0x6000 0x1000>;
+ mediatek,gce-events = <CMDQ_EVENT_VPP1_SVPP3_MDP_RSZ_SOF>,
+ <CMDQ_EVENT_VPP1_SVPP3_MDP_RSZ_FRAME_DONE>;
+ clocks = <&vppsys1 CLK_VPP1_SVPP3_MDP_RSZ>;
+ };
+
+ display@14f17000 {
+ compatible = "mediatek,mt8195-mdp3-tdshp";
+ reg = <0 0x14f17000 0 0x1000>;
+ mediatek,gce-client-reg = <&gce1 SUBSYS_14f1XXXX 0x7000 0x1000>;
+ clocks = <&vppsys1 CLK_VPP1_SVPP1_MDP_TDSHP>;
+ };
+
+ display@14f18000 {
+ compatible = "mediatek,mt8195-mdp3-tdshp";
+ reg = <0 0x14f18000 0 0x1000>;
+ mediatek,gce-client-reg = <&gce1 SUBSYS_14f1XXXX 0x8000 0x1000>;
+ clocks = <&vppsys1 CLK_VPP1_SVPP2_MDP_TDSHP>;
+ };
+
+ display@14f19000 {
+ compatible = "mediatek,mt8195-mdp3-tdshp";
+ reg = <0 0x14f19000 0 0x1000>;
+ mediatek,gce-client-reg = <&gce1 SUBSYS_14f1XXXX 0x9000 0x1000>;
+ clocks = <&vppsys1 CLK_VPP1_SVPP3_MDP_TDSHP>;
+ };
+
+ display@14f1a000 {
+ compatible = "mediatek,mt8195-mdp3-merge";
+ reg = <0 0x14f1a000 0 0x1000>;
+ mediatek,gce-client-reg = <&gce1 SUBSYS_14f1XXXX 0xa000 0x1000>;
+ clocks = <&vppsys1 CLK_VPP1_SVPP2_VPP_MERGE>;
+ power-domains = <&spm MT8195_POWER_DOMAIN_VPPSYS1>;
+ };
+
+ display@14f1b000 {
+ compatible = "mediatek,mt8195-mdp3-merge";
+ reg = <0 0x14f1b000 0 0x1000>;
+ mediatek,gce-client-reg = <&gce1 SUBSYS_14f1XXXX 0xb000 0x1000>;
+ clocks = <&vppsys1 CLK_VPP1_SVPP3_VPP_MERGE>;
+ power-domains = <&spm MT8195_POWER_DOMAIN_VPPSYS1>;
+ };
+
+ display@14f1c000 {
+ compatible = "mediatek,mt8195-mdp3-color";
+ reg = <0 0x14f1c000 0 0x1000>;
+ interrupts = <GIC_SPI 628 IRQ_TYPE_LEVEL_HIGH 0>;
+ mediatek,gce-client-reg = <&gce1 SUBSYS_14f1XXXX 0xc000 0x1000>;
+ clocks = <&vppsys1 CLK_VPP1_SVPP1_MDP_COLOR>;
+ power-domains = <&spm MT8195_POWER_DOMAIN_VPPSYS1>;
+ };
+
+ display@14f1d000 {
+ compatible = "mediatek,mt8195-mdp3-color";
+ reg = <0 0x14f1d000 0 0x1000>;
+ mediatek,gce-client-reg = <&gce1 SUBSYS_14f1XXXX 0xd000 0x1000>;
+ interrupts = <GIC_SPI 629 IRQ_TYPE_LEVEL_HIGH 0>;
+ clocks = <&vppsys1 CLK_VPP1_SVPP2_MDP_COLOR>;
+ power-domains = <&spm MT8195_POWER_DOMAIN_VPPSYS1>;
+ };
+
+ display@14f1e000 {
+ compatible = "mediatek,mt8195-mdp3-color";
+ reg = <0 0x14f1e000 0 0x1000>;
+ interrupts = <GIC_SPI 630 IRQ_TYPE_LEVEL_HIGH 0>;
+ mediatek,gce-client-reg = <&gce1 SUBSYS_14f1XXXX 0xe000 0x1000>;
+ clocks = <&vppsys1 CLK_VPP1_SVPP3_MDP_COLOR>;
+ power-domains = <&spm MT8195_POWER_DOMAIN_VPPSYS1>;
+ };
+
+ display@14f1f000 {
+ compatible = "mediatek,mt8195-mdp3-ovl";
+ reg = <0 0x14f1f000 0 0x1000>;
+ interrupts = <GIC_SPI 631 IRQ_TYPE_LEVEL_HIGH 0>;
+ mediatek,gce-client-reg = <&gce1 SUBSYS_14f1XXXX 0xf000 0x1000>;
+ clocks = <&vppsys1 CLK_VPP1_SVPP1_MDP_OVL>;
+ power-domains = <&spm MT8195_POWER_DOMAIN_VPPSYS1>;
+ iommus = <&iommu_vdo M4U_PORT_L5_SVPP1_MDP_OVL>;
+ };
+
+ display@14f20000 {
+ compatible = "mediatek,mt8195-mdp3-padding";
+ reg = <0 0x14f20000 0 0x1000>;
+ mediatek,gce-client-reg = <&gce1 SUBSYS_14f2XXXX 0 0x1000>;
+ clocks = <&vppsys1 CLK_VPP1_SVPP1_VPP_PAD>;
+ power-domains = <&spm MT8195_POWER_DOMAIN_VPPSYS1>;
+ };
+
+ display@14f21000 {
+ compatible = "mediatek,mt8195-mdp3-padding";
+ reg = <0 0x14f21000 0 0x1000>;
+ mediatek,gce-client-reg = <&gce1 SUBSYS_14f2XXXX 0x1000 0x1000>;
+ clocks = <&vppsys1 CLK_VPP1_SVPP2_VPP_PAD>;
+ power-domains = <&spm MT8195_POWER_DOMAIN_VPPSYS1>;
+ };
+
+ display@14f22000 {
+ compatible = "mediatek,mt8195-mdp3-padding";
+ reg = <0 0x14f22000 0 0x1000>;
+ mediatek,gce-client-reg = <&gce1 SUBSYS_14f2XXXX 0x2000 0x1000>;
+ clocks = <&vppsys1 CLK_VPP1_SVPP3_VPP_PAD>;
+ power-domains = <&spm MT8195_POWER_DOMAIN_VPPSYS1>;
+ };
+
+ dma-controller@14f23000 {
+ compatible = "mediatek,mt8195-mdp3-wrot", "mediatek,mt8183-mdp3-wrot";
+ reg = <0 0x14f23000 0 0x1000>;
+ mediatek,gce-client-reg = <&gce1 SUBSYS_14f2XXXX 0x3000 0x1000>;
+ mediatek,gce-events = <CMDQ_EVENT_VPP1_SVPP1_MDP_WROT_SOF>,
+ <CMDQ_EVENT_VPP1_SVPP1_MDP_WROT_FRAME_DONE>;
+ clocks = <&vppsys1 CLK_VPP1_SVPP1_MDP_WROT>;
+ iommus = <&iommu_vdo M4U_PORT_L5_SVPP1_MDP_WROT>;
+ power-domains = <&spm MT8195_POWER_DOMAIN_VPPSYS1>;
+ #dma-cells = <1>;
+ };
+
+ dma-controller@14f24000 {
+ compatible = "mediatek,mt8195-mdp3-wrot", "mediatek,mt8183-mdp3-wrot";
+ reg = <0 0x14f24000 0 0x1000>;
+ mediatek,gce-client-reg = <&gce1 SUBSYS_14f2XXXX 0x4000 0x1000>;
+ mediatek,gce-events = <CMDQ_EVENT_VPP1_SVPP2_MDP_WROT_SOF>,
+ <CMDQ_EVENT_VPP1_SVPP2_MDP_WROT_FRAME_DONE>;
+ clocks = <&vppsys1 CLK_VPP1_SVPP2_MDP_WROT>;
+ iommus = <&iommu_vdo M4U_PORT_L5_SVPP2_MDP_WROT>;
+ power-domains = <&spm MT8195_POWER_DOMAIN_VPPSYS1>;
+ #dma-cells = <1>;
+ };
+
+ dma-controller@14f25000 {
+ compatible = "mediatek,mt8195-mdp3-wrot", "mediatek,mt8183-mdp3-wrot";
+ reg = <0 0x14f25000 0 0x1000>;
+ mediatek,gce-client-reg = <&gce1 SUBSYS_14f2XXXX 0x5000 0x1000>;
+ mediatek,gce-events = <CMDQ_EVENT_VPP1_SVPP3_MDP_WROT_SOF>,
+ <CMDQ_EVENT_VPP1_SVPP3_MDP_WROT_FRAME_DONE>;
+ clocks = <&vppsys1 CLK_VPP1_SVPP3_MDP_WROT>;
+ iommus = <&iommu_vpp M4U_PORT_L6_SVPP3_MDP_WROT>;
+ power-domains = <&spm MT8195_POWER_DOMAIN_VPPSYS1>;
+ #dma-cells = <1>;
+ };
+
imgsys: clock-controller@15000000 {
compatible = "mediatek,mt8195-imgsys";
reg = <0 0x15000000 0 0x1000>;
@@ -2741,6 +3168,20 @@
mediatek,gce-client-reg = <&gce0 SUBSYS_1c00XXXX 0x7000 0x1000>;
};
+ dsi0: dsi@1c008000 {
+ compatible = "mediatek,mt8195-dsi", "mediatek,mt8183-dsi";
+ reg = <0 0x1c008000 0 0x1000>;
+ interrupts = <GIC_SPI 644 IRQ_TYPE_LEVEL_HIGH 0>;
+ power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS0>;
+ clocks = <&vdosys0 CLK_VDO0_DSI0>,
+ <&vdosys0 CLK_VDO0_DSI0_DSI>,
+ <&mipi_tx0>;
+ clock-names = "engine", "digital", "hs";
+ phys = <&mipi_tx0>;
+ phy-names = "dphy";
+ status = "disabled";
+ };
+
dsc0: dsc@1c009000 {
compatible = "mediatek,mt8195-disp-dsc";
reg = <0 0x1c009000 0 0x1000>;
@@ -2750,6 +3191,20 @@
mediatek,gce-client-reg = <&gce0 SUBSYS_1c00XXXX 0x9000 0x1000>;
};
+ dsi1: dsi@1c012000 {
+ compatible = "mediatek,mt8195-dsi", "mediatek,mt8183-dsi";
+ reg = <0 0x1c012000 0 0x1000>;
+ interrupts = <GIC_SPI 654 IRQ_TYPE_LEVEL_HIGH 0>;
+ power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS0>;
+ clocks = <&vdosys0 CLK_VDO0_DSI1>,
+ <&vdosys0 CLK_VDO0_DSI1_DSI>,
+ <&mipi_tx1>;
+ clock-names = "engine", "digital", "hs";
+ phys = <&mipi_tx1>;
+ phy-names = "dphy";
+ status = "disabled";
+ };
+
merge0: merge@1c014000 {
compatible = "mediatek,mt8195-disp-merge";
reg = <0 0x1c014000 0 0x1000>;
@@ -2873,7 +3328,7 @@
power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS1>;
};
- vdo1_rdma0: rdma@1c104000 {
+ vdo1_rdma0: dma-controller@1c104000 {
compatible = "mediatek,mt8195-vdo1-rdma";
reg = <0 0x1c104000 0 0x1000>;
interrupts = <GIC_SPI 495 IRQ_TYPE_LEVEL_HIGH 0>;
@@ -2881,9 +3336,10 @@
power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS1>;
iommus = <&iommu_vdo M4U_PORT_L2_MDP_RDMA0>;
mediatek,gce-client-reg = <&gce0 SUBSYS_1c10XXXX 0x4000 0x1000>;
+ #dma-cells = <1>;
};
- vdo1_rdma1: rdma@1c105000 {
+ vdo1_rdma1: dma-controller@1c105000 {
compatible = "mediatek,mt8195-vdo1-rdma";
reg = <0 0x1c105000 0 0x1000>;
interrupts = <GIC_SPI 496 IRQ_TYPE_LEVEL_HIGH 0>;
@@ -2891,9 +3347,10 @@
power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS1>;
iommus = <&iommu_vpp M4U_PORT_L3_MDP_RDMA1>;
mediatek,gce-client-reg = <&gce0 SUBSYS_1c10XXXX 0x5000 0x1000>;
+ #dma-cells = <1>;
};
- vdo1_rdma2: rdma@1c106000 {
+ vdo1_rdma2: dma-controller@1c106000 {
compatible = "mediatek,mt8195-vdo1-rdma";
reg = <0 0x1c106000 0 0x1000>;
interrupts = <GIC_SPI 497 IRQ_TYPE_LEVEL_HIGH 0>;
@@ -2901,9 +3358,10 @@
power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS1>;
iommus = <&iommu_vdo M4U_PORT_L2_MDP_RDMA2>;
mediatek,gce-client-reg = <&gce0 SUBSYS_1c10XXXX 0x6000 0x1000>;
+ #dma-cells = <1>;
};
- vdo1_rdma3: rdma@1c107000 {
+ vdo1_rdma3: dma-controller@1c107000 {
compatible = "mediatek,mt8195-vdo1-rdma";
reg = <0 0x1c107000 0 0x1000>;
interrupts = <GIC_SPI 498 IRQ_TYPE_LEVEL_HIGH 0>;
@@ -2911,9 +3369,10 @@
power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS1>;
iommus = <&iommu_vpp M4U_PORT_L3_MDP_RDMA3>;
mediatek,gce-client-reg = <&gce0 SUBSYS_1c10XXXX 0x7000 0x1000>;
+ #dma-cells = <1>;
};
- vdo1_rdma4: rdma@1c108000 {
+ vdo1_rdma4: dma-controller@1c108000 {
compatible = "mediatek,mt8195-vdo1-rdma";
reg = <0 0x1c108000 0 0x1000>;
interrupts = <GIC_SPI 499 IRQ_TYPE_LEVEL_HIGH 0>;
@@ -2921,9 +3380,10 @@
power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS1>;
iommus = <&iommu_vdo M4U_PORT_L2_MDP_RDMA4>;
mediatek,gce-client-reg = <&gce0 SUBSYS_1c10XXXX 0x8000 0x1000>;
+ #dma-cells = <1>;
};
- vdo1_rdma5: rdma@1c109000 {
+ vdo1_rdma5: dma-controller@1c109000 {
compatible = "mediatek,mt8195-vdo1-rdma";
reg = <0 0x1c109000 0 0x1000>;
interrupts = <GIC_SPI 500 IRQ_TYPE_LEVEL_HIGH 0>;
@@ -2931,9 +3391,10 @@
power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS1>;
iommus = <&iommu_vpp M4U_PORT_L3_MDP_RDMA5>;
mediatek,gce-client-reg = <&gce0 SUBSYS_1c10XXXX 0x9000 0x1000>;
+ #dma-cells = <1>;
};
- vdo1_rdma6: rdma@1c10a000 {
+ vdo1_rdma6: dma-controller@1c10a000 {
compatible = "mediatek,mt8195-vdo1-rdma";
reg = <0 0x1c10a000 0 0x1000>;
interrupts = <GIC_SPI 501 IRQ_TYPE_LEVEL_HIGH 0>;
@@ -2941,9 +3402,10 @@
power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS1>;
iommus = <&iommu_vdo M4U_PORT_L2_MDP_RDMA6>;
mediatek,gce-client-reg = <&gce0 SUBSYS_1c10XXXX 0xa000 0x1000>;
+ #dma-cells = <1>;
};
- vdo1_rdma7: rdma@1c10b000 {
+ vdo1_rdma7: dma-controller@1c10b000 {
compatible = "mediatek,mt8195-vdo1-rdma";
reg = <0 0x1c10b000 0 0x1000>;
interrupts = <GIC_SPI 502 IRQ_TYPE_LEVEL_HIGH 0>;
@@ -2951,6 +3413,7 @@
power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS1>;
iommus = <&iommu_vpp M4U_PORT_L3_MDP_RDMA7>;
mediatek,gce-client-reg = <&gce0 SUBSYS_1c10XXXX 0xb000 0x1000>;
+ #dma-cells = <1>;
};
merge1: vpp-merge@1c10c000 {
diff --git a/dts/upstream/src/arm64/mediatek/mt8395-genio-1200-evk.dts b/dts/upstream/src/arm64/mediatek/mt8395-genio-1200-evk.dts
index 00ac59a..7fc515a 100644
--- a/dts/upstream/src/arm64/mediatek/mt8395-genio-1200-evk.dts
+++ b/dts/upstream/src/arm64/mediatek/mt8395-genio-1200-evk.dts
@@ -210,8 +210,7 @@
touchscreen@5d {
compatible = "goodix,gt9271";
reg = <0x5d>;
- interrupt-parent = <&pio>;
- interrupts = <132 IRQ_TYPE_EDGE_RISING>;
+ interrupts-extended = <&pio 132 IRQ_TYPE_EDGE_RISING>;
irq-gpios = <&pio 132 GPIO_ACTIVE_HIGH>;
reset-gpios = <&pio 133 GPIO_ACTIVE_HIGH>;
AVDD28-supply = <&mt6360_ldo1>;
@@ -774,8 +773,7 @@
};
&pmic {
- interrupt-parent = <&pio>;
- interrupts = <222 IRQ_TYPE_LEVEL_HIGH>;
+ interrupts-extended = <&pio 222 IRQ_TYPE_LEVEL_HIGH>;
};
&scp {
diff --git a/dts/upstream/src/arm64/nvidia/tegra234-p3737-0000+p3701-0000.dts b/dts/upstream/src/arm64/nvidia/tegra234-p3737-0000+p3701-0000.dts
index ea13c4a..81a8293 100644
--- a/dts/upstream/src/arm64/nvidia/tegra234-p3737-0000+p3701-0000.dts
+++ b/dts/upstream/src/arm64/nvidia/tegra234-p3737-0000+p3701-0000.dts
@@ -175,7 +175,7 @@
status = "okay";
phy-handle = <&mgbe0_phy>;
- phy-mode = "usxgmii";
+ phy-mode = "10gbase-r";
mdio {
#address-cells = <1>;
diff --git a/dts/upstream/src/arm64/nvidia/tegra234.dtsi b/dts/upstream/src/arm64/nvidia/tegra234.dtsi
index 3f16595..d1bd328 100644
--- a/dts/upstream/src/arm64/nvidia/tegra234.dtsi
+++ b/dts/upstream/src/arm64/nvidia/tegra234.dtsi
@@ -1459,7 +1459,7 @@
<&mc TEGRA234_MEMORY_CLIENT_MGBEAWR &emc>;
interconnect-names = "dma-mem", "write";
iommus = <&smmu_niso0 TEGRA234_SID_MGBE>;
- power-domains = <&bpmp TEGRA234_POWER_DOMAIN_MGBEA>;
+ power-domains = <&bpmp TEGRA234_POWER_DOMAIN_MGBEB>;
status = "disabled";
};
@@ -1493,7 +1493,7 @@
<&mc TEGRA234_MEMORY_CLIENT_MGBEBWR &emc>;
interconnect-names = "dma-mem", "write";
iommus = <&smmu_niso0 TEGRA234_SID_MGBE_VF1>;
- power-domains = <&bpmp TEGRA234_POWER_DOMAIN_MGBEB>;
+ power-domains = <&bpmp TEGRA234_POWER_DOMAIN_MGBEC>;
status = "disabled";
};
@@ -1527,7 +1527,7 @@
<&mc TEGRA234_MEMORY_CLIENT_MGBECWR &emc>;
interconnect-names = "dma-mem", "write";
iommus = <&smmu_niso0 TEGRA234_SID_MGBE_VF2>;
- power-domains = <&bpmp TEGRA234_POWER_DOMAIN_MGBEC>;
+ power-domains = <&bpmp TEGRA234_POWER_DOMAIN_MGBED>;
status = "disabled";
};
diff --git a/dts/upstream/src/arm64/qcom/ipq5018-rdp432-c2.dts b/dts/upstream/src/arm64/qcom/ipq5018-rdp432-c2.dts
index e636a1c..8460b53 100644
--- a/dts/upstream/src/arm64/qcom/ipq5018-rdp432-c2.dts
+++ b/dts/upstream/src/arm64/qcom/ipq5018-rdp432-c2.dts
@@ -67,6 +67,18 @@
};
};
+&usb {
+ status = "okay";
+};
+
+&usb_dwc {
+ dr_mode = "host";
+};
+
+&usbphy0 {
+ status = "okay";
+};
+
&xo_board_clk {
clock-frequency = <24000000>;
};
diff --git a/dts/upstream/src/arm64/qcom/ipq5018.dtsi b/dts/upstream/src/arm64/qcom/ipq5018.dtsi
index 38ffdc3..32b178b 100644
--- a/dts/upstream/src/arm64/qcom/ipq5018.dtsi
+++ b/dts/upstream/src/arm64/qcom/ipq5018.dtsi
@@ -5,6 +5,7 @@
* Copyright (c) 2023 The Linux Foundation. All rights reserved.
*/
+#include <dt-bindings/clock/qcom,apss-ipq.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/clock/qcom,gcc-ipq5018.h>
#include <dt-bindings/reset/qcom,gcc-ipq5018.h>
@@ -36,6 +37,8 @@
reg = <0x0>;
enable-method = "psci";
next-level-cache = <&L2_0>;
+ clocks = <&apcs_glb APCS_ALIAS0_CORE_CLK>;
+ operating-points-v2 = <&cpu_opp_table>;
};
CPU1: cpu@1 {
@@ -44,6 +47,8 @@
reg = <0x1>;
enable-method = "psci";
next-level-cache = <&L2_0>;
+ clocks = <&apcs_glb APCS_ALIAS0_CORE_CLK>;
+ operating-points-v2 = <&cpu_opp_table>;
};
L2_0: l2-cache {
@@ -54,6 +59,23 @@
};
};
+ cpu_opp_table: opp-table-cpu {
+ compatible = "operating-points-v2";
+ opp-shared;
+
+ opp-800000000 {
+ opp-hz = /bits/ 64 <800000000>;
+ opp-microvolt = <1100000>;
+ clock-latency-ns = <200000>;
+ };
+
+ opp-1008000000 {
+ opp-hz = /bits/ 64 <1008000000>;
+ opp-microvolt = <1100000>;
+ clock-latency-ns = <200000>;
+ };
+ };
+
firmware {
scm {
compatible = "qcom,scm-ipq5018", "qcom,scm";
@@ -82,6 +104,24 @@
#size-cells = <2>;
ranges;
+ bootloader@4a800000 {
+ reg = <0x0 0x4a800000 0x0 0x200000>;
+ no-map;
+ };
+
+ sbl@4aa00000 {
+ reg = <0x0 0x4aa00000 0x0 0x100000>;
+ no-map;
+ };
+
+ smem@4ab00000 {
+ compatible = "qcom,smem";
+ reg = <0x0 0x4ab00000 0x0 0x100000>;
+ no-map;
+
+ hwlocks = <&tcsr_mutex 3>;
+ };
+
tz_region: tz@4ac00000 {
reg = <0x0 0x4ac00000 0x0 0x200000>;
no-map;
@@ -94,6 +134,19 @@
#size-cells = <1>;
ranges = <0 0 0 0xffffffff>;
+ usbphy0: phy@5b000 {
+ compatible = "qcom,ipq5018-usb-hsphy";
+ reg = <0x0005b000 0x120>;
+
+ clocks = <&gcc GCC_USB0_PHY_CFG_AHB_CLK>;
+
+ resets = <&gcc GCC_QUSB2_0_PHY_BCR>;
+
+ #phy-cells = <0>;
+
+ status = "disabled";
+ };
+
tlmm: pinctrl@1000000 {
compatible = "qcom,ipq5018-tlmm";
reg = <0x01000000 0x300000>;
@@ -129,6 +182,12 @@
#power-domain-cells = <1>;
};
+ tcsr_mutex: hwlock@1905000 {
+ compatible = "qcom,tcsr-mutex";
+ reg = <0x01905000 0x20000>;
+ #hwlock-cells = <1>;
+ };
+
sdhc_1: mmc@7804000 {
compatible = "qcom,ipq5018-sdhci", "qcom,sdhci-msm-v5";
reg = <0x7804000 0x1000>;
@@ -146,6 +205,16 @@
status = "disabled";
};
+ blsp_dma: dma-controller@7884000 {
+ compatible = "qcom,bam-v1.7.0";
+ reg = <0x07884000 0x1d000>;
+ interrupts = <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&gcc GCC_BLSP1_AHB_CLK>;
+ clock-names = "bam_clk";
+ #dma-cells = <1>;
+ qcom,ee = <0>;
+ };
+
blsp1_uart1: serial@78af000 {
compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
reg = <0x078af000 0x200>;
@@ -153,9 +222,64 @@
clocks = <&gcc GCC_BLSP1_UART1_APPS_CLK>,
<&gcc GCC_BLSP1_AHB_CLK>;
clock-names = "core", "iface";
+ status = "disabled";
+ };
+
+ blsp1_spi1: spi@78b5000 {
+ compatible = "qcom,spi-qup-v2.2.1";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0x078b5000 0x600>;
+ interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&gcc GCC_BLSP1_QUP1_SPI_APPS_CLK>,
+ <&gcc GCC_BLSP1_AHB_CLK>;
+ clock-names = "core", "iface";
+ dmas = <&blsp_dma 4>, <&blsp_dma 5>;
+ dma-names = "tx", "rx";
status = "disabled";
};
+ usb: usb@8af8800 {
+ compatible = "qcom,ipq5018-dwc3", "qcom,dwc3";
+ reg = <0x08af8800 0x400>;
+
+ interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "hs_phy_irq";
+
+ clocks = <&gcc GCC_USB0_MASTER_CLK>,
+ <&gcc GCC_SYS_NOC_USB0_AXI_CLK>,
+ <&gcc GCC_USB0_SLEEP_CLK>,
+ <&gcc GCC_USB0_MOCK_UTMI_CLK>;
+ clock-names = "core",
+ "iface",
+ "sleep",
+ "mock_utmi";
+
+ resets = <&gcc GCC_USB0_BCR>;
+
+ qcom,select-utmi-as-pipe-clk;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges;
+
+ status = "disabled";
+
+ usb_dwc: usb@8a00000 {
+ compatible = "snps,dwc3";
+ reg = <0x08a00000 0xe000>;
+ clocks = <&gcc GCC_USB0_MOCK_UTMI_CLK>;
+ clock-names = "ref";
+ interrupts = <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>;
+ phy-names = "usb2-phy";
+ phys = <&usbphy0>;
+ tx-fifo-resize;
+ snps,is-utmi-l1-suspend;
+ snps,hird-threshold = /bits/ 8 <0x0>;
+ snps,dis_u2_susphy_quirk;
+ snps,dis_u3_susphy_quirk;
+ };
+ };
+
intc: interrupt-controller@b000000 {
compatible = "qcom,msm-qgic2";
reg = <0x0b000000 0x1000>, /* GICD */
@@ -189,6 +313,24 @@
clocks = <&sleep_clk>;
};
+ apcs_glb: mailbox@b111000 {
+ compatible = "qcom,ipq5018-apcs-apps-global",
+ "qcom,ipq6018-apcs-apps-global";
+ reg = <0x0b111000 0x1000>;
+ #clock-cells = <1>;
+ clocks = <&a53pll>, <&xo_board_clk>, <&gcc GPLL0>;
+ clock-names = "pll", "xo", "gpll0";
+ #mbox-cells = <1>;
+ };
+
+ a53pll: clock@b116000 {
+ compatible = "qcom,ipq5018-a53pll";
+ reg = <0x0b116000 0x40>;
+ #clock-cells = <0>;
+ clocks = <&xo_board_clk>;
+ clock-names = "xo";
+ };
+
timer@b120000 {
compatible = "arm,armv7-timer-mem";
reg = <0x0b120000 0x1000>;
diff --git a/dts/upstream/src/arm64/qcom/ipq5332-rdp-common.dtsi b/dts/upstream/src/arm64/qcom/ipq5332-rdp-common.dtsi
index 4870cdb..b37ae77 100644
--- a/dts/upstream/src/arm64/qcom/ipq5332-rdp-common.dtsi
+++ b/dts/upstream/src/arm64/qcom/ipq5332-rdp-common.dtsi
@@ -9,6 +9,7 @@
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/input/input.h>
+#include <dt-bindings/leds/common.h>
#include "ipq5332.dtsi"
/ {
@@ -39,6 +40,8 @@
pinctrl-names = "default";
led-0 {
+ color = <LED_COLOR_ID_GREEN>;
+ function = LED_FUNCTION_WLAN;
gpios = <&tlmm 36 GPIO_ACTIVE_HIGH>;
linux,default-trigger = "phy0tx";
default-state = "off";
diff --git a/dts/upstream/src/arm64/qcom/ipq5332-rdp441.dts b/dts/upstream/src/arm64/qcom/ipq5332-rdp441.dts
index e89e2e9..8464138 100644
--- a/dts/upstream/src/arm64/qcom/ipq5332-rdp441.dts
+++ b/dts/upstream/src/arm64/qcom/ipq5332-rdp441.dts
@@ -15,7 +15,7 @@
};
&blsp1_i2c1 {
- clock-frequency = <400000>;
+ clock-frequency = <400000>;
pinctrl-0 = <&i2c_1_pins>;
pinctrl-names = "default";
status = "okay";
diff --git a/dts/upstream/src/arm64/qcom/ipq5332-rdp442.dts b/dts/upstream/src/arm64/qcom/ipq5332-rdp442.dts
index efd480a..ed8a54e 100644
--- a/dts/upstream/src/arm64/qcom/ipq5332-rdp442.dts
+++ b/dts/upstream/src/arm64/qcom/ipq5332-rdp442.dts
@@ -15,7 +15,7 @@
};
&blsp1_i2c1 {
- clock-frequency = <400000>;
+ clock-frequency = <400000>;
pinctrl-0 = <&i2c_1_pins>;
pinctrl-names = "default";
status = "okay";
diff --git a/dts/upstream/src/arm64/qcom/ipq5332-rdp474.dts b/dts/upstream/src/arm64/qcom/ipq5332-rdp474.dts
index eb1fa33..d5f99e7 100644
--- a/dts/upstream/src/arm64/qcom/ipq5332-rdp474.dts
+++ b/dts/upstream/src/arm64/qcom/ipq5332-rdp474.dts
@@ -15,7 +15,7 @@
};
&blsp1_i2c1 {
- clock-frequency = <400000>;
+ clock-frequency = <400000>;
pinctrl-0 = <&i2c_1_pins>;
pinctrl-names = "default";
status = "okay";
diff --git a/dts/upstream/src/arm64/qcom/ipq5332.dtsi b/dts/upstream/src/arm64/qcom/ipq5332.dtsi
index d3fef2f..42e2e48 100644
--- a/dts/upstream/src/arm64/qcom/ipq5332.dtsi
+++ b/dts/upstream/src/arm64/qcom/ipq5332.dtsi
@@ -91,13 +91,21 @@
};
cpu_opp_table: opp-table-cpu {
- compatible = "operating-points-v2";
+ compatible = "operating-points-v2-kryo-cpu";
opp-shared;
+ nvmem-cells = <&cpu_speed_bin>;
- opp-1488000000 {
- opp-hz = /bits/ 64 <1488000000>;
+ opp-1100000000 {
+ opp-hz = /bits/ 64 <1100000000>;
+ opp-supported-hw = <0x7>;
clock-latency-ns = <200000>;
};
+
+ opp-1500000000 {
+ opp-hz = /bits/ 64 <1500000000>;
+ opp-supported-hw = <0x3>;
+ clock-latency-ns = <200000>;
+ };
};
pmu {
@@ -163,6 +171,11 @@
reg = <0x000a4000 0x721>;
#address-cells = <1>;
#size-cells = <1>;
+
+ cpu_speed_bin: cpu-speed-bin@1d {
+ reg = <0x1d 0x2>;
+ bits = <7 2>;
+ };
};
rng: rng@e3000 {
@@ -390,8 +403,8 @@
"qcom,ipq6018-apcs-apps-global";
reg = <0x0b111000 0x1000>;
#clock-cells = <1>;
- clocks = <&a53pll>, <&xo_board>;
- clock-names = "pll", "xo";
+ clocks = <&a53pll>, <&xo_board>, <&gcc GPLL0>;
+ clock-names = "pll", "xo", "gpll0";
#mbox-cells = <1>;
};
diff --git a/dts/upstream/src/arm64/qcom/ipq6018.dtsi b/dts/upstream/src/arm64/qcom/ipq6018.dtsi
index e59b9df..61c8fd4 100644
--- a/dts/upstream/src/arm64/qcom/ipq6018.dtsi
+++ b/dts/upstream/src/arm64/qcom/ipq6018.dtsi
@@ -96,42 +96,49 @@
};
cpu_opp_table: opp-table-cpu {
- compatible = "operating-points-v2";
+ compatible = "operating-points-v2-kryo-cpu";
+ nvmem-cells = <&cpu_speed_bin>;
opp-shared;
opp-864000000 {
opp-hz = /bits/ 64 <864000000>;
opp-microvolt = <725000>;
+ opp-supported-hw = <0xf>;
clock-latency-ns = <200000>;
};
opp-1056000000 {
opp-hz = /bits/ 64 <1056000000>;
opp-microvolt = <787500>;
+ opp-supported-hw = <0xf>;
clock-latency-ns = <200000>;
};
opp-1320000000 {
opp-hz = /bits/ 64 <1320000000>;
opp-microvolt = <862500>;
+ opp-supported-hw = <0x3>;
clock-latency-ns = <200000>;
};
opp-1440000000 {
opp-hz = /bits/ 64 <1440000000>;
opp-microvolt = <925000>;
+ opp-supported-hw = <0x3>;
clock-latency-ns = <200000>;
};
opp-1608000000 {
opp-hz = /bits/ 64 <1608000000>;
opp-microvolt = <987500>;
+ opp-supported-hw = <0x1>;
clock-latency-ns = <200000>;
};
opp-1800000000 {
opp-hz = /bits/ 64 <1800000000>;
opp-microvolt = <1062500>;
+ opp-supported-hw = <0x1>;
clock-latency-ns = <200000>;
};
};
@@ -236,31 +243,26 @@
ssphy_0: ssphy@78000 {
compatible = "qcom,ipq6018-qmp-usb3-phy";
- reg = <0x0 0x00078000 0x0 0x1c4>;
- #address-cells = <2>;
- #size-cells = <2>;
- ranges;
+ reg = <0x0 0x00078000 0x0 0x1000>;
clocks = <&gcc GCC_USB0_AUX_CLK>,
- <&gcc GCC_USB0_PHY_CFG_AHB_CLK>, <&xo>;
- clock-names = "aux", "cfg_ahb", "ref";
+ <&xo>,
+ <&gcc GCC_USB0_PHY_CFG_AHB_CLK>,
+ <&gcc GCC_USB0_PIPE_CLK>;
+ clock-names = "aux",
+ "ref",
+ "cfg_ahb",
+ "pipe";
+ clock-output-names = "gcc_usb0_pipe_clk_src";
+ #clock-cells = <0>;
+ #phy-cells = <0>;
resets = <&gcc GCC_USB0_PHY_BCR>,
<&gcc GCC_USB3PHY_0_PHY_BCR>;
- reset-names = "phy","common";
- status = "disabled";
+ reset-names = "phy",
+ "phy_phy";
- usb0_ssphy: phy@78200 {
- reg = <0x0 0x00078200 0x0 0x130>, /* Tx */
- <0x0 0x00078400 0x0 0x200>, /* Rx */
- <0x0 0x00078800 0x0 0x1f8>, /* PCS */
- <0x0 0x00078600 0x0 0x044>; /* PCS misc */
- #phy-cells = <0>;
- #clock-cells = <0>;
- clocks = <&gcc GCC_USB0_PIPE_CLK>;
- clock-names = "pipe0";
- clock-output-names = "gcc_usb0_pipe_clk_src";
- };
+ status = "disabled";
};
qusb_phy_0: qusb@79000 {
@@ -314,6 +316,11 @@
reg = <0x0 0x000a4000 0x0 0x2000>;
#address-cells = <1>;
#size-cells = <1>;
+
+ cpu_speed_bin: cpu-speed-bin@135 {
+ reg = <0x135 0x1>;
+ bits = <7 1>;
+ };
};
prng: qrng@e3000 {
@@ -439,6 +446,26 @@
qcom,ee = <0>;
};
+ blsp1_uart1: serial@78af000 {
+ compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
+ reg = <0x0 0x78af000 0x0 0x200>;
+ interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&gcc GCC_BLSP1_UART1_APPS_CLK>,
+ <&gcc GCC_BLSP1_AHB_CLK>;
+ clock-names = "core", "iface";
+ status = "disabled";
+ };
+
+ blsp1_uart2: serial@78b0000 {
+ compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
+ reg = <0x0 0x78b0000 0x0 0x200>;
+ interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&gcc GCC_BLSP1_UART2_APPS_CLK>,
+ <&gcc GCC_BLSP1_AHB_CLK>;
+ clock-names = "core", "iface";
+ status = "disabled";
+ };
+
blsp1_uart3: serial@78b1000 {
compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
reg = <0x0 0x078b1000 0x0 0x200>;
@@ -449,6 +476,36 @@
status = "disabled";
};
+ blsp1_uart4: serial@78b2000 {
+ compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
+ reg = <0x0 0x078b2000 0x0 0x200>;
+ interrupts = <GIC_SPI 307 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&gcc GCC_BLSP1_UART4_APPS_CLK>,
+ <&gcc GCC_BLSP1_AHB_CLK>;
+ clock-names = "core", "iface";
+ status = "disabled";
+ };
+
+ blsp1_uart5: serial@78b3000 {
+ compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
+ reg = <0x0 0x78b3000 0x0 0x200>;
+ interrupts = <GIC_SPI 308 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&gcc GCC_BLSP1_UART5_APPS_CLK>,
+ <&gcc GCC_BLSP1_AHB_CLK>;
+ clock-names = "core", "iface";
+ status = "disabled";
+ };
+
+ blsp1_uart6: serial@78b4000 {
+ compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
+ reg = <0x0 0x078b4000 0x0 0x200>;
+ interrupts = <GIC_SPI 309 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&gcc GCC_BLSP1_UART6_APPS_CLK>,
+ <&gcc GCC_BLSP1_AHB_CLK>;
+ clock-names = "core", "iface";
+ status = "disabled";
+ };
+
blsp1_spi1: spi@78b5000 {
compatible = "qcom,spi-qup-v2.2.1";
#address-cells = <1>;
@@ -477,6 +534,20 @@
status = "disabled";
};
+ blsp1_spi5: spi@78b9000 {
+ compatible = "qcom,spi-qup-v2.2.1";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0x0 0x078b9000 0x0 0x600>;
+ interrupts = <GIC_SPI 299 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&gcc GCC_BLSP1_QUP5_SPI_APPS_CLK>,
+ <&gcc GCC_BLSP1_AHB_CLK>;
+ clock-names = "core", "iface";
+ dmas = <&blsp_dma 20>, <&blsp_dma 21>;
+ dma-names = "tx", "rx";
+ status = "disabled";
+ };
+
blsp1_i2c2: i2c@78b6000 {
compatible = "qcom,i2c-qup-v2.2.1";
#address-cells = <1>;
@@ -557,7 +628,7 @@
<&gcc GCC_USB0_MOCK_UTMI_CLK>;
assigned-clock-rates = <133330000>,
<133330000>,
- <20000000>;
+ <24000000>;
resets = <&gcc GCC_USB0_BCR>;
status = "disabled";
@@ -566,7 +637,7 @@
compatible = "snps,dwc3";
reg = <0x0 0x08a00000 0x0 0xcd00>;
interrupts = <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>;
- phys = <&qusb_phy_0>, <&usb0_ssphy>;
+ phys = <&qusb_phy_0>, <&ssphy_0>;
phy-names = "usb2-phy", "usb3-phy";
clocks = <&xo>;
clock-names = "ref";
@@ -611,8 +682,8 @@
compatible = "qcom,ipq6018-apcs-apps-global";
reg = <0x0 0x0b111000 0x0 0x1000>;
#clock-cells = <1>;
- clocks = <&a53pll>, <&xo>;
- clock-names = "pll", "xo";
+ clocks = <&a53pll>, <&xo>, <&gcc GPLL0>;
+ clock-names = "pll", "xo", "gpll0";
#mbox-cells = <1>;
};
@@ -731,7 +802,7 @@
};
};
- pcie0: pci@20000000 {
+ pcie0: pcie@20000000 {
compatible = "qcom,pcie-ipq6018";
reg = <0x0 0x20000000 0x0 0xf1d>,
<0x0 0x20000f20 0x0 0xa8>,
@@ -759,10 +830,10 @@
#interrupt-cells = <1>;
interrupt-map-mask = <0 0 0 0x7>;
- interrupt-map = <0 0 0 1 &intc 0 75 IRQ_TYPE_LEVEL_HIGH>, /* int_a */
- <0 0 0 2 &intc 0 78 IRQ_TYPE_LEVEL_HIGH>, /* int_b */
- <0 0 0 3 &intc 0 79 IRQ_TYPE_LEVEL_HIGH>, /* int_c */
- <0 0 0 4 &intc 0 83 IRQ_TYPE_LEVEL_HIGH>; /* int_d */
+ interrupt-map = <0 0 0 1 &intc 0 0 0 75 IRQ_TYPE_LEVEL_HIGH>, /* int_a */
+ <0 0 0 2 &intc 0 0 0 78 IRQ_TYPE_LEVEL_HIGH>, /* int_b */
+ <0 0 0 3 &intc 0 0 0 79 IRQ_TYPE_LEVEL_HIGH>, /* int_c */
+ <0 0 0 4 &intc 0 0 0 83 IRQ_TYPE_LEVEL_HIGH>; /* int_d */
clocks = <&gcc GCC_SYS_NOC_PCIE0_AXI_CLK>,
<&gcc GCC_PCIE0_AXI_M_CLK>,
diff --git a/dts/upstream/src/arm64/qcom/ipq8074.dtsi b/dts/upstream/src/arm64/qcom/ipq8074.dtsi
index 2f275c8..2644144 100644
--- a/dts/upstream/src/arm64/qcom/ipq8074.dtsi
+++ b/dts/upstream/src/arm64/qcom/ipq8074.dtsi
@@ -125,32 +125,26 @@
ssphy_1: phy@58000 {
compatible = "qcom,ipq8074-qmp-usb3-phy";
- reg = <0x00058000 0x1c4>;
- #address-cells = <1>;
- #size-cells = <1>;
- ranges;
+ reg = <0x00058000 0x1000>;
clocks = <&gcc GCC_USB1_AUX_CLK>,
- <&gcc GCC_USB1_PHY_CFG_AHB_CLK>,
- <&xo>;
- clock-names = "aux", "cfg_ahb", "ref";
+ <&xo>,
+ <&gcc GCC_USB1_PHY_CFG_AHB_CLK>,
+ <&gcc GCC_USB1_PIPE_CLK>;
+ clock-names = "aux",
+ "ref",
+ "cfg_ahb",
+ "pipe";
+ clock-output-names = "usb3phy_1_cc_pipe_clk";
+ #clock-cells = <0>;
+ #phy-cells = <0>;
resets = <&gcc GCC_USB1_PHY_BCR>,
- <&gcc GCC_USB3PHY_1_PHY_BCR>;
- reset-names = "phy","common";
- status = "disabled";
+ <&gcc GCC_USB3PHY_1_PHY_BCR>;
+ reset-names = "phy",
+ "phy_phy";
- usb1_ssphy: phy@58200 {
- reg = <0x00058200 0x130>, /* Tx */
- <0x00058400 0x200>, /* Rx */
- <0x00058800 0x1f8>, /* PCS */
- <0x00058600 0x044>; /* PCS misc */
- #phy-cells = <0>;
- #clock-cells = <0>;
- clocks = <&gcc GCC_USB1_PIPE_CLK>;
- clock-names = "pipe0";
- clock-output-names = "usb3phy_1_cc_pipe_clk";
- };
+ status = "disabled";
};
qusb_phy_1: phy@59000 {
@@ -168,32 +162,26 @@
ssphy_0: phy@78000 {
compatible = "qcom,ipq8074-qmp-usb3-phy";
- reg = <0x00078000 0x1c4>;
- #address-cells = <1>;
- #size-cells = <1>;
- ranges;
+ reg = <0x00078000 0x1000>;
clocks = <&gcc GCC_USB0_AUX_CLK>,
- <&gcc GCC_USB0_PHY_CFG_AHB_CLK>,
- <&xo>;
- clock-names = "aux", "cfg_ahb", "ref";
+ <&xo>,
+ <&gcc GCC_USB0_PHY_CFG_AHB_CLK>,
+ <&gcc GCC_USB0_PIPE_CLK>;
+ clock-names = "aux",
+ "ref",
+ "cfg_ahb",
+ "pipe";
+ clock-output-names = "usb3phy_0_cc_pipe_clk";
+ #clock-cells = <0>;
+ #phy-cells = <0>;
resets = <&gcc GCC_USB0_PHY_BCR>,
- <&gcc GCC_USB3PHY_0_PHY_BCR>;
- reset-names = "phy","common";
- status = "disabled";
+ <&gcc GCC_USB3PHY_0_PHY_BCR>;
+ reset-names = "phy",
+ "phy_phy";
- usb0_ssphy: phy@78200 {
- reg = <0x00078200 0x130>, /* Tx */
- <0x00078400 0x200>, /* Rx */
- <0x00078800 0x1f8>, /* PCS */
- <0x00078600 0x044>; /* PCS misc */
- #phy-cells = <0>;
- #clock-cells = <0>;
- clocks = <&gcc GCC_USB0_PIPE_CLK>;
- clock-names = "pipe0";
- clock-output-names = "usb3phy_0_cc_pipe_clk";
- };
+ status = "disabled";
};
qusb_phy_0: phy@79000 {
@@ -369,8 +357,14 @@
gcc: gcc@1800000 {
compatible = "qcom,gcc-ipq8074";
reg = <0x01800000 0x80000>;
- clocks = <&xo>, <&sleep_clk>;
- clock-names = "xo", "sleep_clk";
+ clocks = <&xo>,
+ <&sleep_clk>,
+ <&pcie_qmp0>,
+ <&pcie_qmp1>;
+ clock-names = "xo",
+ "sleep_clk",
+ "pcie0_pipe",
+ "pcie1_pipe";
#clock-cells = <1>;
#power-domain-cells = <1>;
#reset-cells = <1>;
@@ -406,7 +400,7 @@
};
sdhc_1: mmc@7824900 {
- compatible = "qcom,sdhci-msm-v4";
+ compatible = "qcom,ipq8074-sdhci", "qcom,sdhci-msm-v4";
reg = <0x7824900 0x500>, <0x7824000 0x800>;
reg-names = "hc", "core";
@@ -523,6 +517,20 @@
status = "disabled";
};
+ blsp1_spi4: spi@78b8000 {
+ compatible = "qcom,spi-qup-v2.2.1";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0x78b8000 0x600>;
+ interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&gcc GCC_BLSP1_QUP4_SPI_APPS_CLK>,
+ <&gcc GCC_BLSP1_AHB_CLK>;
+ clock-names = "core", "iface";
+ dmas = <&blsp_dma 18>, <&blsp_dma 19>;
+ dma-names = "tx", "rx";
+ status = "disabled";
+ };
+
blsp1_i2c5: i2c@78b9000 {
compatible = "qcom,i2c-qup-v2.2.1";
#address-cells = <1>;
@@ -628,7 +636,7 @@
compatible = "snps,dwc3";
reg = <0x8a00000 0xcd00>;
interrupts = <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>;
- phys = <&qusb_phy_0>, <&usb0_ssphy>;
+ phys = <&qusb_phy_0>, <&ssphy_0>;
phy-names = "usb2-phy", "usb3-phy";
snps,is-utmi-l1-suspend;
snps,hird-threshold = /bits/ 8 <0x0>;
@@ -670,7 +678,7 @@
compatible = "snps,dwc3";
reg = <0x8c00000 0xcd00>;
interrupts = <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>;
- phys = <&qusb_phy_1>, <&usb1_ssphy>;
+ phys = <&qusb_phy_1>, <&ssphy_1>;
phy-names = "usb2-phy", "usb3-phy";
snps,is-utmi-l1-suspend;
snps,hird-threshold = /bits/ 8 <0x0>;
@@ -708,8 +716,8 @@
compatible = "qcom,ipq8074-apcs-apps-global",
"qcom,ipq6018-apcs-apps-global";
reg = <0x0b111000 0x1000>;
- clocks = <&a53pll>, <&xo>;
- clock-names = "pll", "xo";
+ clocks = <&a53pll>, <&xo>, <&gcc GPLL0>;
+ clock-names = "pll", "xo", "gpll0";
#clock-cells = <1>;
#mbox-cells = <1>;
@@ -781,7 +789,7 @@
};
};
- pcie1: pci@10000000 {
+ pcie1: pcie@10000000 {
compatible = "qcom,pcie-ipq8074";
reg = <0x10000000 0xf1d>,
<0x10000f20 0xa8>,
@@ -806,13 +814,13 @@
interrupt-names = "msi";
#interrupt-cells = <1>;
interrupt-map-mask = <0 0 0 0x7>;
- interrupt-map = <0 0 0 1 &intc 0 142
+ interrupt-map = <0 0 0 1 &intc 0 0 142
IRQ_TYPE_LEVEL_HIGH>, /* int_a */
- <0 0 0 2 &intc 0 143
+ <0 0 0 2 &intc 0 0 143
IRQ_TYPE_LEVEL_HIGH>, /* int_b */
- <0 0 0 3 &intc 0 144
+ <0 0 0 3 &intc 0 0 144
IRQ_TYPE_LEVEL_HIGH>, /* int_c */
- <0 0 0 4 &intc 0 145
+ <0 0 0 4 &intc 0 0 145
IRQ_TYPE_LEVEL_HIGH>; /* int_d */
clocks = <&gcc GCC_SYS_NOC_PCIE1_AXI_CLK>,
@@ -842,7 +850,7 @@
status = "disabled";
};
- pcie0: pci@20000000 {
+ pcie0: pcie@20000000 {
compatible = "qcom,pcie-ipq8074-gen3";
reg = <0x20000000 0xf1d>,
<0x20000f20 0xa8>,
@@ -868,13 +876,13 @@
interrupt-names = "msi";
#interrupt-cells = <1>;
interrupt-map-mask = <0 0 0 0x7>;
- interrupt-map = <0 0 0 1 &intc 0 75
+ interrupt-map = <0 0 0 1 &intc 0 0 75
IRQ_TYPE_LEVEL_HIGH>, /* int_a */
- <0 0 0 2 &intc 0 78
+ <0 0 0 2 &intc 0 0 78
IRQ_TYPE_LEVEL_HIGH>, /* int_b */
- <0 0 0 3 &intc 0 79
+ <0 0 0 3 &intc 0 0 79
IRQ_TYPE_LEVEL_HIGH>, /* int_c */
- <0 0 0 4 &intc 0 83
+ <0 0 0 4 &intc 0 0 83
IRQ_TYPE_LEVEL_HIGH>; /* int_d */
clocks = <&gcc GCC_SYS_NOC_PCIE0_AXI_CLK>,
diff --git a/dts/upstream/src/arm64/qcom/ipq9574-rdp-common.dtsi b/dts/upstream/src/arm64/qcom/ipq9574-rdp-common.dtsi
new file mode 100644
index 0000000..91e104b
--- /dev/null
+++ b/dts/upstream/src/arm64/qcom/ipq9574-rdp-common.dtsi
@@ -0,0 +1,169 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
+/*
+ * IPQ9574 RDP board common device tree source
+ *
+ * Copyright (c) 2020-2021 The Linux Foundation. All rights reserved.
+ * Copyright (c) 2023, Qualcomm Innovation Center, Inc. All rights reserved.
+ */
+
+/dts-v1/;
+
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/input/input.h>
+#include <dt-bindings/leds/common.h>
+#include "ipq9574.dtsi"
+
+/ {
+ aliases {
+ serial0 = &blsp1_uart2;
+ };
+
+ chosen {
+ stdout-path = "serial0:115200n8";
+ };
+
+ regulator_fixed_3p3: s3300 {
+ compatible = "regulator-fixed";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-boot-on;
+ regulator-always-on;
+ regulator-name = "fixed_3p3";
+ };
+
+ regulator_fixed_0p925: s0925 {
+ compatible = "regulator-fixed";
+ regulator-min-microvolt = <925000>;
+ regulator-max-microvolt = <925000>;
+ regulator-boot-on;
+ regulator-always-on;
+ regulator-name = "fixed_0p925";
+ };
+
+ gpio-keys {
+ compatible = "gpio-keys";
+ pinctrl-0 = <&gpio_keys_default>;
+ pinctrl-names = "default";
+
+ button-wps {
+ label = "wps";
+ linux,code = <KEY_WPS_BUTTON>;
+ gpios = <&tlmm 37 GPIO_ACTIVE_LOW>;
+ debounce-interval = <60>;
+ };
+ };
+
+ leds {
+ compatible = "gpio-leds";
+ pinctrl-0 = <&gpio_leds_default>;
+ pinctrl-names = "default";
+
+ led-0 {
+ color = <LED_COLOR_ID_GREEN>;
+ function = LED_FUNCTION_WLAN;
+ gpios = <&tlmm 64 GPIO_ACTIVE_LOW>;
+ linux,default-trigger = "phy0tx";
+ default-state = "off";
+ };
+ };
+};
+
+&blsp1_spi0 {
+ pinctrl-0 = <&spi_0_pins>;
+ pinctrl-names = "default";
+ status = "okay";
+
+ flash@0 {
+ compatible = "micron,n25q128a11", "jedec,spi-nor";
+ reg = <0>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ spi-max-frequency = <50000000>;
+ };
+};
+
+&blsp1_uart2 {
+ pinctrl-0 = <&uart2_pins>;
+ pinctrl-names = "default";
+ status = "okay";
+};
+
+&rpm_requests {
+ regulators {
+ compatible = "qcom,rpm-mp5496-regulators";
+
+ ipq9574_s1: s1 {
+ /*
+ * During kernel bootup, the SoC runs at 800MHz with 875mV set by the bootloaders.
+ * During regulator registration, kernel not knowing the initial voltage,
+ * considers it as zero and brings up the regulators with minimum supported voltage.
+ * Update the regulator-min-microvolt with SVS voltage of 725mV so that
+ * the regulators are brought up with 725mV which is sufficient for all the
+ * corner parts to operate at 800MHz
+ */
+ regulator-min-microvolt = <725000>;
+ regulator-max-microvolt = <1075000>;
+ };
+
+ mp5496_l2: l2 {
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-always-on;
+ regulator-boot-on;
+ };
+ };
+};
+
+&sleep_clk {
+ clock-frequency = <32000>;
+};
+
+&tlmm {
+ spi_0_pins: spi-0-state {
+ pins = "gpio11", "gpio12", "gpio13", "gpio14";
+ function = "blsp0_spi";
+ drive-strength = <8>;
+ bias-disable;
+ };
+
+ gpio_keys_default: gpio-keys-default-state {
+ pins = "gpio37";
+ function = "gpio";
+ drive-strength = <8>;
+ bias-pull-up;
+ };
+
+ gpio_leds_default: gpio-leds-default-state {
+ pins = "gpio64";
+ function = "gpio";
+ drive-strength = <8>;
+ bias-pull-up;
+ };
+};
+
+&usb_0_dwc3 {
+ dr_mode = "host";
+};
+
+&usb_0_qmpphy {
+ vdda-pll-supply = <&mp5496_l2>;
+ vdda-phy-supply = <®ulator_fixed_0p925>;
+
+ status = "okay";
+};
+
+&usb_0_qusbphy {
+ vdd-supply = <®ulator_fixed_0p925>;
+ vdda-pll-supply = <&mp5496_l2>;
+ vdda-phy-dpdm-supply = <®ulator_fixed_3p3>;
+
+ status = "okay";
+};
+
+&usb3 {
+ status = "okay";
+};
+
+&xo_board_clk {
+ clock-frequency = <24000000>;
+};
diff --git a/dts/upstream/src/arm64/qcom/ipq9574-rdp418.dts b/dts/upstream/src/arm64/qcom/ipq9574-rdp418.dts
index 2b093e0..f4f9199 100644
--- a/dts/upstream/src/arm64/qcom/ipq9574-rdp418.dts
+++ b/dts/upstream/src/arm64/qcom/ipq9574-rdp418.dts
@@ -8,58 +8,12 @@
/dts-v1/;
-#include "ipq9574.dtsi"
+#include "ipq9574-rdp-common.dtsi"
/ {
model = "Qualcomm Technologies, Inc. IPQ9574/AP-AL02-C2";
compatible = "qcom,ipq9574-ap-al02-c2", "qcom,ipq9574";
- aliases {
- serial0 = &blsp1_uart2;
- };
-
- chosen {
- stdout-path = "serial0:115200n8";
- };
-};
-
-&blsp1_spi0 {
- pinctrl-0 = <&spi_0_pins>;
- pinctrl-names = "default";
- status = "okay";
-
- flash@0 {
- compatible = "micron,n25q128a11", "jedec,spi-nor";
- reg = <0>;
- #address-cells = <1>;
- #size-cells = <1>;
- spi-max-frequency = <50000000>;
- };
-};
-
-&blsp1_uart2 {
- pinctrl-0 = <&uart2_pins>;
- pinctrl-names = "default";
- status = "okay";
-};
-
-&rpm_requests {
- regulators {
- compatible = "qcom,rpm-mp5496-regulators";
-
- ipq9574_s1: s1 {
- /*
- * During kernel bootup, the SoC runs at 800MHz with 875mV set by the bootloaders.
- * During regulator registration, kernel not knowing the initial voltage,
- * considers it as zero and brings up the regulators with minimum supported voltage.
- * Update the regulator-min-microvolt with SVS voltage of 725mV so that
- * the regulators are brought up with 725mV which is sufficient for all the
- * corner parts to operate at 800MHz
- */
- regulator-min-microvolt = <725000>;
- regulator-max-microvolt = <1075000>;
- };
- };
};
&sdhc_1 {
@@ -74,10 +28,6 @@
status = "okay";
};
-&sleep_clk {
- clock-frequency = <32000>;
-};
-
&tlmm {
sdc_default_state: sdc-default-state {
clk-pins {
@@ -110,15 +60,4 @@
bias-pull-down;
};
};
-
- spi_0_pins: spi-0-state {
- pins = "gpio11", "gpio12", "gpio13", "gpio14";
- function = "blsp0_spi";
- drive-strength = <8>;
- bias-disable;
- };
};
-
-&xo_board_clk {
- clock-frequency = <24000000>;
-};
diff --git a/dts/upstream/src/arm64/qcom/ipq9574-rdp433.dts b/dts/upstream/src/arm64/qcom/ipq9574-rdp433.dts
index 877026c..1bb8d96 100644
--- a/dts/upstream/src/arm64/qcom/ipq9574-rdp433.dts
+++ b/dts/upstream/src/arm64/qcom/ipq9574-rdp433.dts
@@ -8,69 +8,11 @@
/dts-v1/;
-#include "ipq9574.dtsi"
+#include "ipq9574-rdp-common.dtsi"
/ {
model = "Qualcomm Technologies, Inc. IPQ9574/AP-AL02-C7";
compatible = "qcom,ipq9574-ap-al02-c7", "qcom,ipq9574";
-
- aliases {
- serial0 = &blsp1_uart2;
- };
-
- chosen {
- stdout-path = "serial0:115200n8";
- };
-
- regulator_fixed_3p3: s3300 {
- compatible = "regulator-fixed";
- regulator-min-microvolt = <3300000>;
- regulator-max-microvolt = <3300000>;
- regulator-boot-on;
- regulator-always-on;
- regulator-name = "fixed_3p3";
- };
-
- regulator_fixed_0p925: s0925 {
- compatible = "regulator-fixed";
- regulator-min-microvolt = <925000>;
- regulator-max-microvolt = <925000>;
- regulator-boot-on;
- regulator-always-on;
- regulator-name = "fixed_0p925";
- };
-};
-
-&blsp1_uart2 {
- pinctrl-0 = <&uart2_pins>;
- pinctrl-names = "default";
- status = "okay";
-};
-
-&rpm_requests {
- regulators {
- compatible = "qcom,rpm-mp5496-regulators";
-
- ipq9574_s1: s1 {
- /*
- * During kernel bootup, the SoC runs at 800MHz with 875mV set by the bootloaders.
- * During regulator registration, kernel not knowing the initial voltage,
- * considers it as zero and brings up the regulators with minimum supported voltage.
- * Update the regulator-min-microvolt with SVS voltage of 725mV so that
- * the regulators are brought up with 725mV which is sufficient for all the
- * corner parts to operate at 800MHz
- */
- regulator-min-microvolt = <725000>;
- regulator-max-microvolt = <1075000>;
- };
-
- mp5496_l2: l2 {
- regulator-min-microvolt = <1800000>;
- regulator-max-microvolt = <1800000>;
- regulator-always-on;
- regulator-boot-on;
- };
- };
};
&sdhc_1 {
@@ -85,10 +27,6 @@
status = "okay";
};
-&sleep_clk {
- clock-frequency = <32000>;
-};
-
&tlmm {
sdc_default_state: sdc-default-state {
clk-pins {
@@ -122,30 +60,3 @@
};
};
};
-
-&usb_0_dwc3 {
- dr_mode = "host";
-};
-
-&usb_0_qmpphy {
- vdda-pll-supply = <&mp5496_l2>;
- vdda-phy-supply = <®ulator_fixed_0p925>;
-
- status = "okay";
-};
-
-&usb_0_qusbphy {
- vdd-supply = <®ulator_fixed_0p925>;
- vdda-pll-supply = <&mp5496_l2>;
- vdda-phy-dpdm-supply = <®ulator_fixed_3p3>;
-
- status = "okay";
-};
-
-&usb3 {
- status = "okay";
-};
-
-&xo_board_clk {
- clock-frequency = <24000000>;
-};
diff --git a/dts/upstream/src/arm64/qcom/ipq9574-rdp449.dts b/dts/upstream/src/arm64/qcom/ipq9574-rdp449.dts
index c8fa54e..d36d107 100644
--- a/dts/upstream/src/arm64/qcom/ipq9574-rdp449.dts
+++ b/dts/upstream/src/arm64/qcom/ipq9574-rdp449.dts
@@ -8,73 +8,10 @@
/dts-v1/;
-#include "ipq9574.dtsi"
+#include "ipq9574-rdp-common.dtsi"
/ {
model = "Qualcomm Technologies, Inc. IPQ9574/AP-AL02-C6";
compatible = "qcom,ipq9574-ap-al02-c6", "qcom,ipq9574";
- aliases {
- serial0 = &blsp1_uart2;
- };
-
- chosen {
- stdout-path = "serial0:115200n8";
- };
-};
-
-&blsp1_spi0 {
- pinctrl-0 = <&spi_0_pins>;
- pinctrl-names = "default";
- status = "okay";
-
- flash@0 {
- compatible = "micron,n25q128a11", "jedec,spi-nor";
- reg = <0>;
- #address-cells = <1>;
- #size-cells = <1>;
- spi-max-frequency = <50000000>;
- };
-};
-
-&blsp1_uart2 {
- pinctrl-0 = <&uart2_pins>;
- pinctrl-names = "default";
- status = "okay";
-};
-
-&rpm_requests {
- regulators {
- compatible = "qcom,rpm-mp5496-regulators";
-
- ipq9574_s1: s1 {
- /*
- * During kernel bootup, the SoC runs at 800MHz with 875mV set by the bootloaders.
- * During regulator registration, kernel not knowing the initial voltage,
- * considers it as zero and brings up the regulators with minimum supported voltage.
- * Update the regulator-min-microvolt with SVS voltage of 725mV so that
- * the regulators are brought up with 725mV which is sufficient for all the
- * corner parts to operate at 800MHz
- */
- regulator-min-microvolt = <725000>;
- regulator-max-microvolt = <1075000>;
- };
- };
-};
-
-&sleep_clk {
- clock-frequency = <32000>;
-};
-
-&tlmm {
- spi_0_pins: spi-0-state {
- pins = "gpio11", "gpio12", "gpio13", "gpio14";
- function = "blsp0_spi";
- drive-strength = <8>;
- bias-disable;
- };
-};
-
-&xo_board_clk {
- clock-frequency = <24000000>;
};
diff --git a/dts/upstream/src/arm64/qcom/ipq9574-rdp453.dts b/dts/upstream/src/arm64/qcom/ipq9574-rdp453.dts
index f01de66..c30c9fb 100644
--- a/dts/upstream/src/arm64/qcom/ipq9574-rdp453.dts
+++ b/dts/upstream/src/arm64/qcom/ipq9574-rdp453.dts
@@ -8,73 +8,10 @@
/dts-v1/;
-#include "ipq9574.dtsi"
+#include "ipq9574-rdp-common.dtsi"
/ {
model = "Qualcomm Technologies, Inc. IPQ9574/AP-AL02-C8";
compatible = "qcom,ipq9574-ap-al02-c8", "qcom,ipq9574";
- aliases {
- serial0 = &blsp1_uart2;
- };
-
- chosen {
- stdout-path = "serial0:115200n8";
- };
-};
-
-&blsp1_spi0 {
- pinctrl-0 = <&spi_0_pins>;
- pinctrl-names = "default";
- status = "okay";
-
- flash@0 {
- compatible = "micron,n25q128a11", "jedec,spi-nor";
- reg = <0>;
- #address-cells = <1>;
- #size-cells = <1>;
- spi-max-frequency = <50000000>;
- };
-};
-
-&blsp1_uart2 {
- pinctrl-0 = <&uart2_pins>;
- pinctrl-names = "default";
- status = "okay";
-};
-
-&rpm_requests {
- regulators {
- compatible = "qcom,rpm-mp5496-regulators";
-
- ipq9574_s1: s1 {
- /*
- * During kernel bootup, the SoC runs at 800MHz with 875mV set by the bootloaders.
- * During regulator registration, kernel not knowing the initial voltage,
- * considers it as zero and brings up the regulators with minimum supported voltage.
- * Update the regulator-min-microvolt with SVS voltage of 725mV so that
- * the regulators are brought up with 725mV which is sufficient for all the
- * corner parts to operate at 800MHz
- */
- regulator-min-microvolt = <725000>;
- regulator-max-microvolt = <1075000>;
- };
- };
-};
-
-&sleep_clk {
- clock-frequency = <32000>;
-};
-
-&tlmm {
- spi_0_pins: spi-0-state {
- pins = "gpio11", "gpio12", "gpio13", "gpio14";
- function = "blsp0_spi";
- drive-strength = <8>;
- bias-disable;
- };
-};
-
-&xo_board_clk {
- clock-frequency = <24000000>;
};
diff --git a/dts/upstream/src/arm64/qcom/ipq9574-rdp454.dts b/dts/upstream/src/arm64/qcom/ipq9574-rdp454.dts
index 6efae34..0dc382f 100644
--- a/dts/upstream/src/arm64/qcom/ipq9574-rdp454.dts
+++ b/dts/upstream/src/arm64/qcom/ipq9574-rdp454.dts
@@ -8,73 +8,9 @@
/dts-v1/;
-#include "ipq9574.dtsi"
+#include "ipq9574-rdp-common.dtsi"
/ {
model = "Qualcomm Technologies, Inc. IPQ9574/AP-AL02-C9";
compatible = "qcom,ipq9574-ap-al02-c9", "qcom,ipq9574";
-
- aliases {
- serial0 = &blsp1_uart2;
- };
-
- chosen {
- stdout-path = "serial0:115200n8";
- };
-};
-
-&blsp1_spi0 {
- pinctrl-0 = <&spi_0_pins>;
- pinctrl-names = "default";
- status = "okay";
-
- flash@0 {
- compatible = "micron,n25q128a11", "jedec,spi-nor";
- reg = <0>;
- #address-cells = <1>;
- #size-cells = <1>;
- spi-max-frequency = <50000000>;
- };
-};
-
-&blsp1_uart2 {
- pinctrl-0 = <&uart2_pins>;
- pinctrl-names = "default";
- status = "okay";
-};
-
-&rpm_requests {
- regulators {
- compatible = "qcom,rpm-mp5496-regulators";
-
- ipq9574_s1: s1 {
- /*
- * During kernel bootup, the SoC runs at 800MHz with 875mV set by the bootloaders.
- * During regulator registration, kernel not knowing the initial voltage,
- * considers it as zero and brings up the regulators with minimum supported voltage.
- * Update the regulator-min-microvolt with SVS voltage of 725mV so that
- * the regulators are brought up with 725mV which is sufficient for all the
- * corner parts to operate at 800MHz
- */
- regulator-min-microvolt = <725000>;
- regulator-max-microvolt = <1075000>;
- };
- };
-};
-
-&sleep_clk {
- clock-frequency = <32000>;
-};
-
-&tlmm {
- spi_0_pins: spi-0-state {
- pins = "gpio11", "gpio12", "gpio13", "gpio14";
- function = "blsp0_spi";
- drive-strength = <8>;
- bias-disable;
- };
-};
-
-&xo_board_clk {
- clock-frequency = <24000000>;
};
diff --git a/dts/upstream/src/arm64/qcom/ipq9574.dtsi b/dts/upstream/src/arm64/qcom/ipq9574.dtsi
index 8a72ad4..5f83ee4 100644
--- a/dts/upstream/src/arm64/qcom/ipq9574.dtsi
+++ b/dts/upstream/src/arm64/qcom/ipq9574.dtsi
@@ -106,42 +106,56 @@
};
cpu_opp_table: opp-table-cpu {
- compatible = "operating-points-v2";
+ compatible = "operating-points-v2-kryo-cpu";
opp-shared;
+ nvmem-cells = <&cpu_speed_bin>;
opp-936000000 {
opp-hz = /bits/ 64 <936000000>;
opp-microvolt = <725000>;
+ opp-supported-hw = <0xf>;
clock-latency-ns = <200000>;
};
opp-1104000000 {
opp-hz = /bits/ 64 <1104000000>;
opp-microvolt = <787500>;
+ opp-supported-hw = <0xf>;
clock-latency-ns = <200000>;
};
+ opp-1200000000 {
+ opp-hz = /bits/ 64 <1200000000>;
+ opp-microvolt = <862500>;
+ opp-supported-hw = <0xf>;
+ clock-latency-ns = <200000>;
+ };
+
opp-1416000000 {
opp-hz = /bits/ 64 <1416000000>;
opp-microvolt = <862500>;
+ opp-supported-hw = <0x7>;
clock-latency-ns = <200000>;
};
opp-1488000000 {
opp-hz = /bits/ 64 <1488000000>;
opp-microvolt = <925000>;
+ opp-supported-hw = <0x7>;
clock-latency-ns = <200000>;
};
opp-1800000000 {
opp-hz = /bits/ 64 <1800000000>;
opp-microvolt = <987500>;
+ opp-supported-hw = <0x5>;
clock-latency-ns = <200000>;
};
opp-2208000000 {
opp-hz = /bits/ 64 <2208000000>;
opp-microvolt = <1062500>;
+ opp-supported-hw = <0x1>;
clock-latency-ns = <200000>;
};
};
@@ -223,6 +237,11 @@
reg = <0x000a4000 0x5a1>;
#address-cells = <1>;
#size-cells = <1>;
+
+ cpu_speed_bin: cpu-speed-bin@15 {
+ reg = <0x15 0x2>;
+ bits = <7 2>;
+ };
};
cryptobam: dma-controller@704000 {
@@ -652,8 +671,8 @@
"qcom,ipq6018-apcs-apps-global";
reg = <0x0b111000 0x1000>;
#clock-cells = <1>;
- clocks = <&a73pll>, <&xo_board_clk>;
- clock-names = "pll", "xo";
+ clocks = <&a73pll>, <&xo_board_clk>, <&gcc GPLL0>;
+ clock-names = "pll", "xo", "gpll0";
#mbox-cells = <1>;
};
diff --git a/dts/upstream/src/arm64/qcom/msm8916-acer-a1-724.dts b/dts/upstream/src/arm64/qcom/msm8916-acer-a1-724.dts
index 57a74ee..b32c7a9 100644
--- a/dts/upstream/src/arm64/qcom/msm8916-acer-a1-724.dts
+++ b/dts/upstream/src/arm64/qcom/msm8916-acer-a1-724.dts
@@ -7,6 +7,7 @@
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/input/input.h>
#include <dt-bindings/interrupt-controller/irq.h>
+#include <dt-bindings/leds/common.h>
/*
* NOTE: The original firmware from Acer can only boot 32-bit kernels.
@@ -83,6 +84,29 @@
};
};
+&blsp_i2c4 {
+ status = "okay";
+
+ led-controller@30 {
+ compatible = "kinetic,ktd2026";
+ reg = <0x30>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ led@0 {
+ reg = <0>;
+ function = LED_FUNCTION_STATUS;
+ color = <LED_COLOR_ID_RED>;
+ };
+
+ led@1 {
+ reg = <1>;
+ function = LED_FUNCTION_STATUS;
+ color = <LED_COLOR_ID_GREEN>;
+ };
+ };
+};
+
&blsp_i2c5 {
status = "okay";
diff --git a/dts/upstream/src/arm64/qcom/msm8916-alcatel-idol347.dts b/dts/upstream/src/arm64/qcom/msm8916-alcatel-idol347.dts
index aa4c1ab..3459145 100644
--- a/dts/upstream/src/arm64/qcom/msm8916-alcatel-idol347.dts
+++ b/dts/upstream/src/arm64/qcom/msm8916-alcatel-idol347.dts
@@ -3,6 +3,8 @@
/dts-v1/;
#include "msm8916-pm8916.dtsi"
+#include "msm8916-modem-qdsp6.dtsi"
+
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/input/input.h>
#include <dt-bindings/leds/common.h>
@@ -22,6 +24,19 @@
stdout-path = "serial0";
};
+ reserved-memory {
+ /delete-node/ reserved@86680000;
+ /delete-node/ rmtfs@86700000;
+
+ rmtfs: rmtfs@86680000 {
+ compatible = "qcom,rmtfs-mem";
+ reg = <0x0 0x86680000 0x0 0x160000>;
+ no-map;
+
+ qcom,client-id = <1>;
+ };
+ };
+
gpio-keys {
compatible = "gpio-keys";
@@ -50,6 +65,17 @@
};
};
+ reg_headphones_avdd: regulator-headphones-avdd {
+ compatible = "regulator-fixed";
+ regulator-name = "headphones_avdd";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ gpio = <&tlmm 121 GPIO_ACTIVE_HIGH>;
+ enable-active-high;
+ pinctrl-0 = <&headphones_avdd_default>;
+ pinctrl-names = "default";
+ };
+
usb_id: usb-id {
compatible = "linux,extcon-usb-gpio";
id-gpios = <&tlmm 69 GPIO_ACTIVE_HIGH>;
@@ -58,8 +84,41 @@
};
};
-&blsp_uart2 {
+&blsp_i2c3 {
status = "okay";
+
+ headphones: audio-codec@10 {
+ compatible = "asahi-kasei,ak4375";
+ reg = <0x10>;
+ avdd-supply = <®_headphones_avdd>;
+ tvdd-supply = <&pm8916_l6>;
+ pdn-gpios = <&tlmm 114 GPIO_ACTIVE_HIGH>;
+ pinctrl-0 = <&headphones_pdn_default>;
+ pinctrl-names = "default";
+ #sound-dai-cells = <0>;
+ };
+
+ speaker_codec_top: audio-codec@34 {
+ compatible = "nxp,tfa9897";
+ reg = <0x34>;
+ vddd-supply = <&pm8916_l6>;
+ rcv-gpios = <&tlmm 50 GPIO_ACTIVE_HIGH>;
+ pinctrl-0 = <&speaker_top_default>;
+ pinctrl-names = "default";
+ sound-name-prefix = "Speaker Top";
+ #sound-dai-cells = <0>;
+ };
+
+ speaker_codec_bottom: audio-codec@36 {
+ compatible = "nxp,tfa9897";
+ reg = <0x36>;
+ vddd-supply = <&pm8916_l6>;
+ rcv-gpios = <&tlmm 111 GPIO_ACTIVE_HIGH>;
+ pinctrl-0 = <&speaker_bottom_default>;
+ pinctrl-names = "default";
+ sound-name-prefix = "Speaker Bottom";
+ #sound-dai-cells = <0>;
+ };
};
&blsp_i2c4 {
@@ -153,6 +212,22 @@
};
};
+&blsp_uart2 {
+ status = "okay";
+};
+
+&mpss_mem {
+ reg = <0x0 0x86800000 0x0 0x5000000>;
+};
+
+&pm8916_codec {
+ qcom,micbias1-ext-cap;
+ qcom,micbias-lvl = <2800>;
+ qcom,mbhc-vthreshold-low = <75 100 120 180 500>;
+ qcom,mbhc-vthreshold-high = <75 100 120 180 500>;
+ qcom,hphl-jack-type-normally-open;
+};
+
&pm8916_resin {
status = "okay";
linux,code = <KEY_VOLUMEDOWN>;
@@ -169,6 +244,17 @@
status = "okay";
};
+&q6afedai {
+ dai@18 {
+ reg = <SECONDARY_MI2S_RX>;
+ qcom,sd-lines = <0>;
+ };
+ dai@22 {
+ reg = <QUATERNARY_MI2S_RX>;
+ qcom,sd-lines = <0>;
+ };
+};
+
&sdhc_1 {
status = "okay";
};
@@ -183,6 +269,54 @@
cd-gpios = <&tlmm 38 GPIO_ACTIVE_LOW>;
};
+&sound {
+ /* Add pin switches for speakers to allow disabling them individually */
+ model = "alcatel-idol3";
+ widgets =
+ "Speaker", "Speaker Top",
+ "Speaker", "Speaker Bottom";
+ pin-switches = "Speaker Top", "Speaker Bottom";
+ audio-routing =
+ "Speaker Top", "Speaker Top OUT",
+ "Speaker Bottom", "Speaker Bottom OUT",
+ "AMIC1", "MIC BIAS External1",
+ "AMIC2", "MIC BIAS Internal2",
+ "AMIC3", "MIC BIAS External1";
+
+ pinctrl-0 = <&cdc_pdm_default &pri_mi2s_default &pri_mi2s_ws_default &sec_mi2s_default>;
+ pinctrl-1 = <&cdc_pdm_sleep &pri_mi2s_sleep &pri_mi2s_ws_sleep &sec_mi2s_sleep>;
+ pinctrl-names = "default", "sleep";
+
+ sound_link_backend2: backend2-dai-link {
+ link-name = "Quaternary MI2S";
+
+ cpu {
+ sound-dai = <&q6afedai QUATERNARY_MI2S_RX>;
+ };
+ platform {
+ sound-dai = <&q6routing>;
+ };
+ codec {
+ sound-dai = <&speaker_codec_top>, <&speaker_codec_bottom>;
+ };
+ };
+};
+
+&sound_link_backend0 {
+ /* Primary MI2S is not used, replace with Secondary MI2S for headphones */
+ link-name = "Secondary MI2S";
+
+ cpu {
+ sound-dai = <&q6afedai SECONDARY_MI2S_RX>;
+ };
+ platform {
+ sound-dai = <&q6routing>;
+ };
+ codec {
+ sound-dai = <&headphones>;
+ };
+};
+
&usb {
status = "okay";
extcon = <&usb_id>, <&usb_id>;
@@ -212,6 +346,15 @@
status = "okay";
};
+/* Only some of the pins are used */
+&pri_mi2s_default {
+ pins = "gpio113", "gpio115";
+};
+
+&pri_mi2s_sleep {
+ pins = "gpio113", "gpio115";
+};
+
&tlmm {
accel_int_default: accel-int-default-state {
pins = "gpio31";
@@ -245,6 +388,20 @@
bias-disable;
};
+ headphones_avdd_default: headphones-avdd-default-state {
+ pins = "gpio121";
+ function = "gpio";
+ drive-strength = <2>;
+ bias-disable;
+ };
+
+ headphones_pdn_default: headphones-pdn-default-state {
+ pins = "gpio114";
+ function = "gpio";
+ drive-strength = <2>;
+ bias-disable;
+ };
+
/*
* The OEM wired an additional GPIO to be asserted so that
* the si-en,sn3190 LED IC works. Since this GPIO is not
@@ -291,6 +448,20 @@
bias-disable;
};
+ speaker_bottom_default: speaker-bottom-default-state {
+ pins = "gpio111";
+ function = "gpio";
+ drive-strength = <2>;
+ bias-disable;
+ };
+
+ speaker_top_default: speaker-top-default-state {
+ pins = "gpio50";
+ function = "gpio";
+ drive-strength = <2>;
+ bias-disable;
+ };
+
ts_int_reset_default: ts-int-reset-default-state {
pins = "gpio13", "gpio100";
function = "gpio";
diff --git a/dts/upstream/src/arm64/qcom/msm8916-asus-z00l.dts b/dts/upstream/src/arm64/qcom/msm8916-asus-z00l.dts
index a8be6ff..77618c7 100644
--- a/dts/upstream/src/arm64/qcom/msm8916-asus-z00l.dts
+++ b/dts/upstream/src/arm64/qcom/msm8916-asus-z00l.dts
@@ -3,6 +3,8 @@
/dts-v1/;
#include "msm8916-pm8916.dtsi"
+#include "msm8916-modem-qdsp6.dtsi"
+
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/input/input.h>
#include <dt-bindings/interrupt-controller/irq.h>
@@ -130,6 +132,18 @@
status = "okay";
};
+&mpss_mem {
+ reg = <0x0 0x86800000 0x0 0x5500000>;
+};
+
+&pm8916_codec {
+ qcom,micbias-lvl = <2800>;
+ qcom,mbhc-vthreshold-low = <75 150 237 450 500>;
+ qcom,mbhc-vthreshold-high = <75 150 237 450 500>;
+ qcom,micbias1-ext-cap;
+ qcom,hphl-jack-type-normally-open;
+};
+
&pm8916_rpm_regulators {
pm8916_l17: l17 {
regulator-min-microvolt = <2850000>;
@@ -151,6 +165,13 @@
cd-gpios = <&tlmm 38 GPIO_ACTIVE_LOW>;
};
+&sound {
+ audio-routing =
+ "AMIC1", "MIC BIAS External1",
+ "AMIC2", "MIC BIAS Internal2",
+ "AMIC3", "MIC BIAS External1";
+};
+
&usb {
status = "okay";
extcon = <&usb_id>, <&usb_id>;
diff --git a/dts/upstream/src/arm64/qcom/msm8916-longcheer-l8150.dts b/dts/upstream/src/arm64/qcom/msm8916-longcheer-l8150.dts
index 47d1c5c..3a3e794 100644
--- a/dts/upstream/src/arm64/qcom/msm8916-longcheer-l8150.dts
+++ b/dts/upstream/src/arm64/qcom/msm8916-longcheer-l8150.dts
@@ -3,6 +3,8 @@
/dts-v1/;
#include "msm8916-pm8916.dtsi"
+#include "msm8916-modem-qdsp6.dtsi"
+
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/input/input.h>
#include <dt-bindings/interrupt-controller/irq.h>
@@ -25,19 +27,47 @@
/*
* For some reason, the signed wcnss firmware is not relocatable.
- * It must be loaded at 0x8b600000. All other firmware is relocatable,
- * so place wcnss at the fixed address and then all other firmware
- * regions will be automatically allocated at a fitting place.
+ * It must be loaded at 0x8b600000. Unfortunately, this also means that
+ * mpss_mem does not fit when loaded to the typical address at 0x86800000.
+ *
+ * Load wcnss_mem to the fixed address and relocate mpss_mem to the next
+ * working higher address. For some reason the modem firmware does not
+ * boot when placed at 0x8a800000 to 0x8e800000.
*/
reserved-memory {
+ /delete-node/ mpss@86800000;
/delete-node/ wcnss;
wcnss_mem: wcnss@8b600000 {
reg = <0x0 0x8b600000 0x0 0x600000>;
no-map;
};
+
+ mpss_mem: mpss@8e800000 {
+ reg = <0x0 0x8e800000 0x0 0x5000000>;
+ no-map;
+ };
};
+ battery: battery {
+ compatible = "simple-battery";
+ voltage-min-design-microvolt = <3400000>;
+ voltage-max-design-microvolt = <4350000>;
+ energy-full-design-microwatt-hours = <9500000>;
+ charge-full-design-microamp-hours = <2500000>;
+
+ ocv-capacity-celsius = <25>;
+ ocv-capacity-table-0 = <4330000 100>, <4265000 95>,
+ <4208000 90>, <4153000 85>, <4100000 80>, <4049000 75>,
+ <4001000 70>, <3962000 65>, <3919000 60>, <3872000 55>,
+ <3839000 50>, <3817000 45>, <3798000 40>, <3783000 35>,
+ <3767000 30>, <3747000 25>, <3729000 20>, <3709000 16>,
+ <3688000 13>, <3681000 11>, <3680000 10>, <3679000 9>,
+ <3677000 8>, <3674000 7>, <3666000 6>, <3641000 5>,
+ <3597000 4>, <3537000 3>, <3457000 2>, <3336000 1>,
+ <3000000 0>;
+ };
+
gpio-keys {
compatible = "gpio-keys";
@@ -93,6 +123,7 @@
#size-cells = <0>;
vcc-supply = <&pm8916_l17>;
+ vio-supply = <&pm8916_l6>;
led@0 {
reg = <0>;
@@ -223,6 +254,29 @@
&blsp_uart2 {
status = "okay";
+};
+
+&pm8916_bms {
+ status = "okay";
+
+ monitored-battery = <&battery>;
+ power-supplies = <&pm8916_charger>;
+};
+
+&pm8916_charger {
+ status = "okay";
+
+ monitored-battery = <&battery>;
+
+ qcom,fast-charge-safe-current = <900000>;
+ qcom,fast-charge-safe-voltage = <4300000>;
+};
+
+&pm8916_codec {
+ qcom,micbias-lvl = <2800>;
+ qcom,mbhc-vthreshold-low = <75 150 237 450 500>;
+ qcom,mbhc-vthreshold-high = <75 150 237 450 500>;
+ qcom,hphl-jack-type-normally-open;
};
&pm8916_resin {
@@ -237,10 +291,6 @@
};
};
-&pm8916_usbin {
- status = "okay";
-};
-
&pm8916_vib {
status = "okay";
};
@@ -254,14 +304,21 @@
non-removable;
};
+&sound {
+ audio-routing =
+ "AMIC1", "MIC BIAS Internal1",
+ "AMIC2", "MIC BIAS Internal2",
+ "AMIC3", "MIC BIAS Internal3";
+};
+
&usb {
status = "okay";
dr_mode = "peripheral";
- extcon = <&pm8916_usbin>;
+ extcon = <&pm8916_charger>;
};
&usb_hs_phy {
- extcon = <&pm8916_usbin>;
+ extcon = <&pm8916_charger>;
};
&venus {
diff --git a/dts/upstream/src/arm64/qcom/msm8916-longcheer-l8910.dts b/dts/upstream/src/arm64/qcom/msm8916-longcheer-l8910.dts
index 41cadb9..3b7fdb6 100644
--- a/dts/upstream/src/arm64/qcom/msm8916-longcheer-l8910.dts
+++ b/dts/upstream/src/arm64/qcom/msm8916-longcheer-l8910.dts
@@ -3,9 +3,12 @@
/dts-v1/;
#include "msm8916-pm8916.dtsi"
+#include "msm8916-modem-qdsp6.dtsi"
+
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/input/input.h>
#include <dt-bindings/leds/common.h>
+#include <dt-bindings/pinctrl/qcom,pmic-gpio.h>
/ {
model = "BQ Aquaris X5 (Longcheer L8910)";
@@ -22,6 +25,16 @@
stdout-path = "serial0";
};
+ speaker_amp: audio-amplifier {
+ compatible = "awinic,aw8738";
+ mode-gpios = <&tlmm 114 GPIO_ACTIVE_HIGH>;
+ awinic,mode = <5>;
+ sound-name-prefix = "Speaker Amp";
+
+ pinctrl-0 = <&spk_ext_pa_default>;
+ pinctrl-names = "default";
+ };
+
flash-led-controller {
compatible = "ocs,ocp8110";
enable-gpios = <&tlmm 49 GPIO_ACTIVE_HIGH>;
@@ -74,6 +87,46 @@
};
};
+&blsp_i2c2 {
+ status = "okay";
+
+ led-controller@30 {
+ compatible = "kinetic,ktd2026";
+ reg = <0x30>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ vin-supply = <&pm8916_l17>;
+ vio-supply = <&pm8916_l6>;
+
+ pinctrl-0 = <&status_led_default>;
+ pinctrl-names = "default";
+
+ multi-led {
+ color = <LED_COLOR_ID_RGB>;
+ function = LED_FUNCTION_STATUS;
+
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ led@0 {
+ reg = <0>;
+ color = <LED_COLOR_ID_RED>;
+ };
+
+ led@1 {
+ reg = <1>;
+ color = <LED_COLOR_ID_GREEN>;
+ };
+
+ led@2 {
+ reg = <2>;
+ color = <LED_COLOR_ID_BLUE>;
+ };
+ };
+ };
+};
+
&blsp_i2c3 {
status = "okay";
@@ -107,6 +160,27 @@
status = "okay";
};
+&mpss_mem {
+ reg = <0x0 0x86800000 0x0 0x5000000>;
+};
+
+&pm8916_codec {
+ qcom,micbias-lvl = <2800>;
+ qcom,mbhc-vthreshold-low = <75 100 120 180 500>;
+ qcom,mbhc-vthreshold-high = <75 100 120 180 500>;
+ qcom,hphl-jack-type-normally-open;
+};
+
+&pm8916_gpios {
+ status_led_default: status-led-default-state {
+ pins = "gpio3";
+ function = PMIC_GPIO_FUNC_NORMAL;
+ power-source = <PM8916_GPIO_VPH>;
+ bias-disable;
+ output-high;
+ };
+};
+
&pm8916_resin {
status = "okay";
linux,code = <KEY_VOLUMEDOWN>;
@@ -137,6 +211,28 @@
cd-gpios = <&tlmm 38 GPIO_ACTIVE_LOW>;
};
+&sound {
+ /*
+ * Provide widgets/pin-switches to allow enabling speaker separately.
+ * The hardware does not provide a way to disable the output via the
+ * headphone jack when the speaker is enabled.
+ */
+ model = "bq-paella";
+ widgets =
+ "Speaker", "Speaker",
+ "Headphone", "Headphones";
+ pin-switches = "Speaker";
+ audio-routing =
+ "Speaker", "Speaker Amp OUT",
+ "Speaker Amp IN", "HPH_R",
+ "Headphones", "HPH_L",
+ "Headphones", "HPH_R",
+ "AMIC1", "MIC BIAS External1",
+ "AMIC2", "MIC BIAS Internal2",
+ "AMIC3", "MIC BIAS External1";
+ aux-devs = <&speaker_amp>;
+};
+
&usb {
status = "okay";
extcon = <&usb_id>, <&usb_id>;
@@ -205,6 +301,13 @@
bias-disable;
};
+ spk_ext_pa_default: spk-ext-pa-default-state {
+ pins = "gpio114";
+ function = "gpio";
+ drive-strength = <2>;
+ bias-disable;
+ };
+
usb_id_default: usb-id-default-state {
pins = "gpio110";
function = "gpio";
diff --git a/dts/upstream/src/arm64/qcom/msm8916-modem-qdsp6.dtsi b/dts/upstream/src/arm64/qcom/msm8916-modem-qdsp6.dtsi
new file mode 100644
index 0000000..0399616
--- /dev/null
+++ b/dts/upstream/src/arm64/qcom/msm8916-modem-qdsp6.dtsi
@@ -0,0 +1,148 @@
+// SPDX-License-Identifier: (GPL-2.0-only OR BSD-3-Clause)
+/*
+ * msm8916-modem-qdsp6.dtsi describes the typical modem setup on MSM8916 devices
+ * (or similar SoCs) with audio routed via the QDSP6 services provided by the
+ * modem firmware. The digital/analog codec in the SoC/PMIC is used by default,
+ * but boards can define additional codecs by adding additional backend DAI links.
+ */
+
+#include <dt-bindings/sound/qcom,q6afe.h>
+#include <dt-bindings/sound/qcom,q6asm.h>
+
+&apr {
+ status = "okay";
+};
+
+&bam_dmux {
+ status = "okay";
+};
+
+&bam_dmux_dma {
+ status = "okay";
+};
+
+&lpass {
+ status = "reserved"; /* Controlled by QDSP6 */
+};
+
+&lpass_codec {
+ status = "okay";
+};
+
+&mba_mem {
+ status = "okay";
+};
+
+&mpss {
+ status = "okay";
+};
+
+&mpss_mem {
+ status = "okay";
+};
+
+&pm8916_codec {
+ status = "okay";
+};
+
+&q6afedai {
+ dai@16 {
+ reg = <PRIMARY_MI2S_RX>;
+ qcom,sd-lines = <0 1>;
+ };
+ dai@20 {
+ reg = <TERTIARY_MI2S_TX>;
+ qcom,sd-lines = <0 1>;
+ };
+};
+
+&q6asmdai {
+ dai@0 {
+ reg = <0>;
+ direction = <Q6ASM_DAI_RX>;
+ };
+ dai@1 {
+ reg = <1>;
+ direction = <Q6ASM_DAI_TX>;
+ };
+ dai@2 {
+ reg = <2>;
+ direction = <Q6ASM_DAI_RX>;
+ };
+ dai@3 {
+ reg = <3>;
+ direction = <Q6ASM_DAI_RX>;
+ is-compress-dai;
+ };
+};
+
+&sound {
+ compatible = "qcom,msm8916-qdsp6-sndcard";
+ model = "msm8916";
+
+ pinctrl-0 = <&cdc_pdm_default>;
+ pinctrl-1 = <&cdc_pdm_sleep>;
+ pinctrl-names = "default", "sleep";
+
+ status = "okay";
+
+ frontend0-dai-link {
+ link-name = "MultiMedia1";
+
+ cpu {
+ sound-dai = <&q6asmdai MSM_FRONTEND_DAI_MULTIMEDIA1>;
+ };
+ };
+
+ frontend1-dai-link {
+ link-name = "MultiMedia2";
+
+ cpu {
+ sound-dai = <&q6asmdai MSM_FRONTEND_DAI_MULTIMEDIA2>;
+ };
+ };
+
+ frontend2-dai-link {
+ link-name = "MultiMedia3";
+
+ cpu {
+ sound-dai = <&q6asmdai MSM_FRONTEND_DAI_MULTIMEDIA3>;
+ };
+ };
+
+ frontend3-dai-link {
+ link-name = "MultiMedia4";
+
+ cpu {
+ sound-dai = <&q6asmdai MSM_FRONTEND_DAI_MULTIMEDIA4>;
+ };
+ };
+
+ sound_link_backend0: backend0-dai-link {
+ link-name = "Primary MI2S";
+
+ cpu {
+ sound-dai = <&q6afedai PRIMARY_MI2S_RX>;
+ };
+ platform {
+ sound-dai = <&q6routing>;
+ };
+ codec {
+ sound-dai = <&lpass_codec 0>, <&pm8916_codec 0>;
+ };
+ };
+
+ sound_link_backend1: backend1-dai-link {
+ link-name = "Tertiary MI2S";
+
+ cpu {
+ sound-dai = <&q6afedai TERTIARY_MI2S_TX>;
+ };
+ platform {
+ sound-dai = <&q6routing>;
+ };
+ codec {
+ sound-dai = <&lpass_codec 1>, <&pm8916_codec 1>;
+ };
+ };
+};
diff --git a/dts/upstream/src/arm64/qcom/msm8916-samsung-a2015-common.dtsi b/dts/upstream/src/arm64/qcom/msm8916-samsung-a2015-common.dtsi
index 0b29132..2937495 100644
--- a/dts/upstream/src/arm64/qcom/msm8916-samsung-a2015-common.dtsi
+++ b/dts/upstream/src/arm64/qcom/msm8916-samsung-a2015-common.dtsi
@@ -1,10 +1,13 @@
// SPDX-License-Identifier: GPL-2.0-only
#include "msm8916-pm8916.dtsi"
+#include "msm8916-modem-qdsp6.dtsi"
+
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/input/input.h>
#include <dt-bindings/interrupt-controller/irq.h>
#include <dt-bindings/pinctrl/qcom,pmic-gpio.h>
+#include <dt-bindings/sound/apq8016-lpass.h>
/ {
aliases {
@@ -196,6 +199,18 @@
};
};
+&blsp_i2c1 {
+ status = "okay";
+
+ speaker_codec: audio-codec@34 {
+ compatible = "nxp,tfa9895";
+ reg = <0x34>;
+ vddd-supply = <&pm8916_l5>;
+ sound-name-prefix = "Speaker";
+ #sound-dai-cells = <0>;
+ };
+};
+
&blsp_i2c2 {
status = "okay";
@@ -243,6 +258,25 @@
status = "okay";
};
+/*
+ * For some reason the speaker amplifier is connected to the second SD line
+ * (MI2S_2_D1) instead of the first (MI2S_2_D0). This must be configured in the
+ * device tree, otherwise audio will seemingly play fine on the wrong SD line
+ * but the speaker stays silent.
+ *
+ * When routing audio via QDSP6 (the default) the &lpass node is reserved and
+ * the definitions from &q6afedai are used. When the modem is disabled audio can
+ * be alternatively routed directly to the LPASS hardware with reduced latency.
+ * The definitions for &lpass are here for completeness to simplify changing the
+ * setup with minor changes to the DT (either manually or with DT overlays).
+ */
+&lpass {
+ dai-link@3 {
+ reg = <MI2S_QUATERNARY>;
+ qcom,playback-sd-lines = <1>;
+ };
+};
+
&mdss {
status = "okay";
};
@@ -253,6 +287,10 @@
pinctrl-1 = <&mdss_sleep>;
};
+&mpss_mem {
+ reg = <0x0 0x86800000 0x0 0x5400000>;
+};
+
&pm8916_resin {
status = "okay";
linux,code = <KEY_VOLUMEDOWN>;
@@ -265,6 +303,13 @@
};
};
+&q6afedai {
+ dai@22 {
+ reg = <QUATERNARY_MI2S_RX>;
+ qcom,sd-lines = <1>;
+ };
+};
+
&sdhc_1 {
status = "okay";
};
@@ -279,6 +324,32 @@
cd-gpios = <&tlmm 38 GPIO_ACTIVE_LOW>;
};
+&sound {
+ model = "samsung-a2015";
+ audio-routing =
+ "AMIC1", "MIC BIAS External1",
+ "AMIC2", "MIC BIAS Internal2",
+ "AMIC3", "MIC BIAS External1";
+
+ pinctrl-0 = <&cdc_pdm_default &sec_mi2s_default>;
+ pinctrl-1 = <&cdc_pdm_sleep &sec_mi2s_sleep>;
+ pinctrl-names = "default", "sleep";
+
+ sound_link_backend2: backend2-dai-link {
+ link-name = "Quaternary MI2S";
+
+ cpu {
+ sound-dai = <&q6afedai QUATERNARY_MI2S_RX>;
+ };
+ platform {
+ sound-dai = <&q6routing>;
+ };
+ codec {
+ sound-dai = <&speaker_codec>;
+ };
+ };
+};
+
&usb {
status = "okay";
extcon = <&muic>, <&muic>;
diff --git a/dts/upstream/src/arm64/qcom/msm8916-samsung-a3u-eur.dts b/dts/upstream/src/arm64/qcom/msm8916-samsung-a3u-eur.dts
index f5a8083..3b934f5 100644
--- a/dts/upstream/src/arm64/qcom/msm8916-samsung-a3u-eur.dts
+++ b/dts/upstream/src/arm64/qcom/msm8916-samsung-a3u-eur.dts
@@ -49,11 +49,6 @@
};
};
-&touchkey {
- vcc-supply = <®_touch_key>;
- vdd-supply = <®_key_led>;
-};
-
&accelerometer {
mount-matrix = "0", "1", "0",
"1", "0", "0",
@@ -108,6 +103,11 @@
remote-endpoint = <&panel_in>;
};
+&touchkey {
+ vcc-supply = <®_touch_key>;
+ vdd-supply = <®_key_led>;
+};
+
&vibrator {
status = "okay";
};
diff --git a/dts/upstream/src/arm64/qcom/msm8916-samsung-e2015-common.dtsi b/dts/upstream/src/arm64/qcom/msm8916-samsung-e2015-common.dtsi
index 0824ab0..3c49dac 100644
--- a/dts/upstream/src/arm64/qcom/msm8916-samsung-e2015-common.dtsi
+++ b/dts/upstream/src/arm64/qcom/msm8916-samsung-e2015-common.dtsi
@@ -65,6 +65,10 @@
};
};
+&mpss_mem {
+ reg = <0x0 0x86800000 0x0 0x5a00000>;
+};
+
®_motor_vdd {
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
diff --git a/dts/upstream/src/arm64/qcom/msm8916-samsung-grandmax.dts b/dts/upstream/src/arm64/qcom/msm8916-samsung-grandmax.dts
index 3f145dd..5882b3a 100644
--- a/dts/upstream/src/arm64/qcom/msm8916-samsung-grandmax.dts
+++ b/dts/upstream/src/arm64/qcom/msm8916-samsung-grandmax.dts
@@ -49,6 +49,10 @@
status = "disabled";
};
+&sound {
+ model = "samsung-gmax"; /* No secondary microphone */
+};
+
&tlmm {
gpio_leds_default: gpio-led-default-state {
pins = "gpio60";
diff --git a/dts/upstream/src/arm64/qcom/msm8916-samsung-gt5-common.dtsi b/dts/upstream/src/arm64/qcom/msm8916-samsung-gt5-common.dtsi
index c19cf20..fbd2caf 100644
--- a/dts/upstream/src/arm64/qcom/msm8916-samsung-gt5-common.dtsi
+++ b/dts/upstream/src/arm64/qcom/msm8916-samsung-gt5-common.dtsi
@@ -3,9 +3,12 @@
/dts-v1/;
#include "msm8916-pm8916.dtsi"
+#include "msm8916-modem-qdsp6.dtsi"
+
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/input/input.h>
#include <dt-bindings/interrupt-controller/irq.h>
+#include <dt-bindings/sound/apq8016-lpass.h>
/ {
aliases {
@@ -65,25 +68,6 @@
};
};
-&blsp_i2c4 {
- status = "okay";
-
- fuelgauge@36 {
- compatible = "maxim,max77849-battery";
- reg = <0x36>;
-
- maxim,rsns-microohm = <10000>;
- maxim,over-heat-temp = <600>;
- maxim,over-volt = <4400>;
-
- interrupt-parent = <&tlmm>;
- interrupts = <121 IRQ_TYPE_EDGE_FALLING>;
-
- pinctrl-0 = <&fuelgauge_int_default>;
- pinctrl-names = "default";
- };
-};
-
&blsp_i2c2 {
status = "okay";
@@ -112,10 +96,52 @@
};
};
+&blsp_i2c4 {
+ status = "okay";
+
+ fuelgauge@36 {
+ compatible = "maxim,max77849-battery";
+ reg = <0x36>;
+
+ maxim,rsns-microohm = <10000>;
+ maxim,over-heat-temp = <600>;
+ maxim,over-volt = <4400>;
+
+ interrupt-parent = <&tlmm>;
+ interrupts = <121 IRQ_TYPE_EDGE_FALLING>;
+
+ pinctrl-0 = <&fuelgauge_int_default>;
+ pinctrl-names = "default";
+ };
+};
+
&blsp_uart2 {
status = "okay";
};
+/*
+ * For some reason the speaker amplifier is connected to the second SD line
+ * (MI2S_2_D1) instead of the first (MI2S_2_D0). This must be configured in the
+ * device tree, otherwise audio will seemingly play fine on the wrong SD line
+ * but the speaker stays silent.
+ *
+ * When routing audio via QDSP6 (the default) the &lpass node is reserved and
+ * the definitions from &q6afedai are used. When the modem is disabled audio can
+ * be alternatively routed directly to the LPASS hardware with reduced latency.
+ * The definitions for &lpass are here for completeness to simplify changing the
+ * setup with minor changes to the DT (either manually or with DT overlays).
+ */
+&lpass {
+ dai-link@3 {
+ reg = <MI2S_QUATERNARY>;
+ qcom,playback-sd-lines = <1>;
+ };
+};
+
+&mpss_mem {
+ reg = <0x0 0x86800000 0x0 0x5400000>;
+};
+
&pm8916_resin {
linux,code = <KEY_VOLUMEDOWN>;
status = "okay";
@@ -133,6 +159,13 @@
status = "okay";
};
+&q6afedai {
+ dai@22 {
+ reg = <QUATERNARY_MI2S_RX>;
+ qcom,sd-lines = <1>;
+ };
+};
+
&sdhc_1 {
status = "okay";
};
@@ -147,6 +180,27 @@
status = "okay";
};
+&sound {
+ audio-routing =
+ "AMIC1", "MIC BIAS External1",
+ "AMIC2", "MIC BIAS Internal2",
+ "AMIC3", "MIC BIAS External1";
+
+ sound_link_backend2: backend2-dai-link {
+ link-name = "Quaternary MI2S";
+
+ cpu {
+ sound-dai = <&q6afedai QUATERNARY_MI2S_RX>;
+ };
+ platform {
+ sound-dai = <&q6routing>;
+ };
+ codec {
+ sound-dai = <&speaker_codec>;
+ };
+ };
+};
+
&usb {
dr_mode = "peripheral";
extcon = <&pm8916_usbin>;
diff --git a/dts/upstream/src/arm64/qcom/msm8916-samsung-gt510.dts b/dts/upstream/src/arm64/qcom/msm8916-samsung-gt510.dts
index 75c4854..5b34529 100644
--- a/dts/upstream/src/arm64/qcom/msm8916-samsung-gt510.dts
+++ b/dts/upstream/src/arm64/qcom/msm8916-samsung-gt510.dts
@@ -9,6 +9,14 @@
compatible = "samsung,gt510", "qcom,msm8916";
chassis-type = "tablet";
+ speaker_codec: audio-codec {
+ compatible = "maxim,max98357a";
+ sdmode-gpios = <&tlmm 55 GPIO_ACTIVE_HIGH>;
+ #sound-dai-cells = <0>;
+ pinctrl-0 = <&audio_sdmode_default>;
+ pinctrl-names = "default";
+ };
+
clk_pwm: pwm {
compatible = "clk-pwm";
#pwm-cells = <2>;
@@ -112,6 +120,10 @@
};
};
+&gpu {
+ status = "okay";
+};
+
&mdss {
status = "okay";
};
@@ -142,7 +154,21 @@
remote-endpoint = <&panel_in>;
};
+&sound {
+ model = "samsung-gt510";
+ pinctrl-0 = <&cdc_pdm_default &sec_mi2s_default>;
+ pinctrl-1 = <&cdc_pdm_sleep &sec_mi2s_sleep>;
+ pinctrl-names = "default", "sleep";
+};
+
&tlmm {
+ audio_sdmode_default: audio-sdmode-default-state {
+ pins = "gpio55";
+ function = "gpio";
+ drive-strength = <2>;
+ bias-disable;
+ };
+
buckbooster_en_default: buckbooster-en-default-state {
pins = "gpio51";
function = "gpio";
diff --git a/dts/upstream/src/arm64/qcom/msm8916-samsung-gt58.dts b/dts/upstream/src/arm64/qcom/msm8916-samsung-gt58.dts
index 11359bc..579312e 100644
--- a/dts/upstream/src/arm64/qcom/msm8916-samsung-gt58.dts
+++ b/dts/upstream/src/arm64/qcom/msm8916-samsung-gt58.dts
@@ -35,6 +35,26 @@
pinctrl-names = "default";
};
+ i2c-amplifier {
+ compatible = "i2c-gpio";
+ sda-gpios = <&tlmm 55 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
+ scl-gpios = <&tlmm 56 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
+
+ pinctrl-0 = <&_i2c_default>;
+ pinctrl-names = "default";
+
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ speaker_codec: audio-codec@34 {
+ compatible = "nxp,tfa9895";
+ reg = <0x34>;
+ vddd-supply = <&pm8916_l5>;
+ sound-name-prefix = "Speaker";
+ #sound-dai-cells = <0>;
+ };
+ };
+
vibrator {
compatible = "gpio-vibrator";
enable-gpios = <&tlmm 76 GPIO_ACTIVE_HIGH>;
@@ -64,6 +84,10 @@
};
};
+&gpu {
+ status = "okay";
+};
+
&mdss {
status = "okay";
};
@@ -94,7 +118,21 @@
remote-endpoint = <&panel_in>;
};
+&sound {
+ model = "samsung-a2015";
+ pinctrl-0 = <&cdc_pdm_default &sec_mi2s_default &secondary_mic_default>;
+ pinctrl-1 = <&cdc_pdm_sleep &sec_mi2s_sleep &secondary_mic_default>;
+ pinctrl-names = "default", "sleep";
+};
+
&tlmm {
+ amp_i2c_default: amp-i2c-default-state {
+ pins = "gpio55", "gpio56";
+ function = "gpio";
+ drive-strength = <2>;
+ bias-disable;
+ };
+
buckbooster_en_default: buckbooster-en-default-state {
pins = "gpio8";
function = "gpio";
@@ -123,6 +161,14 @@
bias-disable;
};
+ secondary_mic_default: secondary-mic-default-state {
+ pins = "gpio98";
+ function = "gpio";
+ drive-strength = <2>;
+ bias-disable;
+ output-high;
+ };
+
tsp_int_default: tsp-int-default-state {
pins = "gpio13";
function = "gpio";
diff --git a/dts/upstream/src/arm64/qcom/msm8916-samsung-j5-common.dtsi b/dts/upstream/src/arm64/qcom/msm8916-samsung-j5-common.dtsi
index fe59be3..5ca2ada 100644
--- a/dts/upstream/src/arm64/qcom/msm8916-samsung-j5-common.dtsi
+++ b/dts/upstream/src/arm64/qcom/msm8916-samsung-j5-common.dtsi
@@ -1,6 +1,8 @@
// SPDX-License-Identifier: GPL-2.0-only
#include "msm8916-pm8916.dtsi"
+#include "msm8916-modem-qdsp6.dtsi"
+
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/input/input.h>
#include <dt-bindings/interrupt-controller/irq.h>
@@ -135,6 +137,10 @@
status = "okay";
};
+&mpss_mem {
+ reg = <0x0 0x86800000 0x0 0x5800000>;
+};
+
&pm8916_resin {
status = "okay";
linux,code = <KEY_VOLUMEDOWN>;
@@ -154,6 +160,14 @@
cd-gpios = <&tlmm 38 GPIO_ACTIVE_LOW>;
};
+&sound {
+ model = "msm8916-1mic";
+ audio-routing =
+ "AMIC1", "MIC BIAS External1",
+ "AMIC2", "MIC BIAS Internal2",
+ "AMIC3", "MIC BIAS External1";
+};
+
&usb {
extcon = <&muic>, <&muic>;
status = "okay";
diff --git a/dts/upstream/src/arm64/qcom/msm8916-samsung-j5.dts b/dts/upstream/src/arm64/qcom/msm8916-samsung-j5.dts
index 58c2f5a..ba86509 100644
--- a/dts/upstream/src/arm64/qcom/msm8916-samsung-j5.dts
+++ b/dts/upstream/src/arm64/qcom/msm8916-samsung-j5.dts
@@ -19,6 +19,10 @@
status = "disabled";
};
+&pm8916_codec {
+ qcom,micbias1-ext-cap;
+};
+
&touchscreen {
/* FIXME: Missing sm5703-mfd driver to power up vdd-supply */
};
diff --git a/dts/upstream/src/arm64/qcom/msm8916-samsung-serranove.dts b/dts/upstream/src/arm64/qcom/msm8916-samsung-serranove.dts
index 68da2a2..5ce8f13 100644
--- a/dts/upstream/src/arm64/qcom/msm8916-samsung-serranove.dts
+++ b/dts/upstream/src/arm64/qcom/msm8916-samsung-serranove.dts
@@ -6,6 +6,8 @@
/dts-v1/;
#include "msm8916-pm8916.dtsi"
+#include "msm8916-modem-qdsp6.dtsi"
+
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/input/input.h>
#include <dt-bindings/interrupt-controller/irq.h>
@@ -319,6 +321,10 @@
status = "okay";
};
+&mpss_mem {
+ reg = <0x0 0x86800000 0x0 0x5a00000>;
+};
+
&pm8916_resin {
status = "okay";
linux,code = <KEY_VOLUMEDOWN>;
@@ -350,6 +356,13 @@
no-1-8-v;
};
+&sound {
+ audio-routing =
+ "AMIC1", "MIC BIAS External1",
+ "AMIC2", "MIC BIAS Internal2",
+ "AMIC3", "MIC BIAS External1";
+};
+
&usb {
status = "okay";
extcon = <&muic>, <&muic>;
diff --git a/dts/upstream/src/arm64/qcom/msm8916-thwc-uf896.dts b/dts/upstream/src/arm64/qcom/msm8916-thwc-uf896.dts
index 6fe1850..f349975 100644
--- a/dts/upstream/src/arm64/qcom/msm8916-thwc-uf896.dts
+++ b/dts/upstream/src/arm64/qcom/msm8916-thwc-uf896.dts
@@ -13,16 +13,16 @@
gpios = <&tlmm 35 GPIO_ACTIVE_LOW>;
};
-&led_r {
- gpios = <&tlmm 82 GPIO_ACTIVE_HIGH>;
+&led_b {
+ gpios = <&tlmm 81 GPIO_ACTIVE_HIGH>;
};
&led_g {
gpios = <&tlmm 83 GPIO_ACTIVE_HIGH>;
};
-&led_b {
- gpios = <&tlmm 81 GPIO_ACTIVE_HIGH>;
+&led_r {
+ gpios = <&tlmm 82 GPIO_ACTIVE_HIGH>;
};
&button_default {
diff --git a/dts/upstream/src/arm64/qcom/msm8916-thwc-ufi001c.dts b/dts/upstream/src/arm64/qcom/msm8916-thwc-ufi001c.dts
index 16d4a91..6cb3911 100644
--- a/dts/upstream/src/arm64/qcom/msm8916-thwc-ufi001c.dts
+++ b/dts/upstream/src/arm64/qcom/msm8916-thwc-ufi001c.dts
@@ -13,16 +13,16 @@
gpios = <&tlmm 37 GPIO_ACTIVE_HIGH>;
};
-&led_r {
- gpios = <&tlmm 22 GPIO_ACTIVE_HIGH>;
+&led_b {
+ gpios = <&tlmm 20 GPIO_ACTIVE_HIGH>;
};
&led_g {
gpios = <&tlmm 21 GPIO_ACTIVE_HIGH>;
};
-&led_b {
- gpios = <&tlmm 20 GPIO_ACTIVE_HIGH>;
+&led_r {
+ gpios = <&tlmm 22 GPIO_ACTIVE_HIGH>;
};
&mpss {
diff --git a/dts/upstream/src/arm64/qcom/msm8916-wingtech-wt88047.dts b/dts/upstream/src/arm64/qcom/msm8916-wingtech-wt88047.dts
index 419f35c..510b3b3 100644
--- a/dts/upstream/src/arm64/qcom/msm8916-wingtech-wt88047.dts
+++ b/dts/upstream/src/arm64/qcom/msm8916-wingtech-wt88047.dts
@@ -6,6 +6,8 @@
/dts-v1/;
#include "msm8916-pm8916.dtsi"
+#include "msm8916-modem-qdsp6.dtsi"
+
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/input/input.h>
#include <dt-bindings/leds/common.h>
@@ -25,6 +27,28 @@
stdout-path = "serial0";
};
+ speaker_amp: audio-amplifier {
+ compatible = "simple-audio-amplifier";
+ enable-gpios = <&tlmm 117 GPIO_ACTIVE_HIGH>;
+ sound-name-prefix = "Speaker Amp";
+ pinctrl-0 = <&speaker_amp_default>;
+ pinctrl-names = "default";
+ };
+
+ /*
+ * This seems to be actually an analog switch that either routes audio
+ * to the headphone jack or nowhere. Given that we need to enable a GPIO
+ * to get sound on headphones, modelling it as simple-audio-amplifier
+ * works just fine.
+ */
+ headphones_switch: audio-switch {
+ compatible = "simple-audio-amplifier";
+ enable-gpios = <&tlmm 8 GPIO_ACTIVE_HIGH>;
+ sound-name-prefix = "Headphones Switch";
+ pinctrl-0 = <&headphones_switch_default>;
+ pinctrl-names = "default";
+ };
+
flash-led-controller {
compatible = "ocs,ocp8110";
enable-gpios = <&tlmm 31 GPIO_ACTIVE_HIGH>;
@@ -118,6 +142,7 @@
#size-cells = <0>;
vcc-supply = <&pm8916_l16>;
+ vio-supply = <&pm8916_l5>;
led@0 {
reg = <0>;
@@ -146,6 +171,18 @@
status = "okay";
};
+&mpss_mem {
+ reg = <0x0 0x86800000 0x0 0x5100000>;
+};
+
+&pm8916_codec {
+ qcom,micbias1-ext-cap;
+ qcom,micbias-lvl = <2800>;
+ qcom,mbhc-vthreshold-low = <75 100 120 180 500>;
+ qcom,mbhc-vthreshold-high = <75 100 120 180 500>;
+ qcom,hphl-jack-type-normally-open;
+};
+
&pm8916_resin {
status = "okay";
linux,code = <KEY_VOLUMEDOWN>;
@@ -180,6 +217,30 @@
non-removable;
};
+&sound {
+ /*
+ * Provide widgets/pin-switches to allow enabling speaker and headphones
+ * separately. Both are routed via the HPH_L/HPH_R pins of the codec.
+ */
+ model = "wt88047";
+ widgets =
+ "Speaker", "Speaker",
+ "Headphone", "Headphones";
+ pin-switches = "Speaker", "Headphones";
+ audio-routing =
+ "Speaker", "Speaker Amp OUTL",
+ "Speaker", "Speaker Amp OUTR",
+ "Speaker Amp INL", "HPH_R",
+ "Speaker Amp INR", "HPH_R",
+ "Headphones", "Headphones Switch OUTL",
+ "Headphones", "Headphones Switch OUTR",
+ "Headphones Switch INL", "HPH_L",
+ "Headphones Switch INR", "HPH_R",
+ "AMIC1", "MIC BIAS External1",
+ "AMIC2", "MIC BIAS Internal2";
+ aux-devs = <&speaker_amp>, <&headphones_switch>;
+};
+
&usb {
status = "okay";
extcon = <&usb_id>, <&usb_id>;
@@ -226,6 +287,13 @@
bias-pull-up;
};
+ headphones_switch_default: headphones-switch-default-state {
+ pins = "gpio8";
+ function = "gpio";
+ drive-strength = <2>;
+ bias-disable;
+ };
+
imu_default: imu-default-state {
pins = "gpio115";
function = "gpio";
@@ -234,6 +302,13 @@
bias-disable;
};
+ speaker_amp_default: speaker-amp-default-state {
+ pins = "gpio117";
+ function = "gpio";
+ drive-strength = <2>;
+ bias-disable;
+ };
+
touchscreen_default: touchscreen-default-state {
touchscreen-pins {
pins = "gpio13";
diff --git a/dts/upstream/src/arm64/qcom/msm8916-yiming-uz801v3.dts b/dts/upstream/src/arm64/qcom/msm8916-yiming-uz801v3.dts
index 5e6ba8c..a98efcf 100644
--- a/dts/upstream/src/arm64/qcom/msm8916-yiming-uz801v3.dts
+++ b/dts/upstream/src/arm64/qcom/msm8916-yiming-uz801v3.dts
@@ -13,16 +13,16 @@
gpios = <&tlmm 23 GPIO_ACTIVE_LOW>;
};
-&led_r {
- gpios = <&tlmm 7 GPIO_ACTIVE_HIGH>;
+&led_b {
+ gpios = <&tlmm 6 GPIO_ACTIVE_HIGH>;
};
&led_g {
gpios = <&tlmm 8 GPIO_ACTIVE_HIGH>;
};
-&led_b {
- gpios = <&tlmm 6 GPIO_ACTIVE_HIGH>;
+&led_r {
+ gpios = <&tlmm 7 GPIO_ACTIVE_HIGH>;
};
&button_default {
diff --git a/dts/upstream/src/arm64/qcom/msm8916.dtsi b/dts/upstream/src/arm64/qcom/msm8916.dtsi
index 4f799b5..e423c57 100644
--- a/dts/upstream/src/arm64/qcom/msm8916.dtsi
+++ b/dts/upstream/src/arm64/qcom/msm8916.dtsi
@@ -10,6 +10,7 @@
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/power/qcom-rpmpd.h>
#include <dt-bindings/reset/qcom,gcc-msm8916.h>
+#include <dt-bindings/soc/qcom,apr.h>
#include <dt-bindings/thermal/thermal.h>
/ {
@@ -539,9 +540,6 @@
compatible = "qcom,msm8916-bimc";
reg = <0x00400000 0x62000>;
#interconnect-cells = <1>;
- clock-names = "bus", "bus_a";
- clocks = <&rpmcc RPM_SMD_BIMC_CLK>,
- <&rpmcc RPM_SMD_BIMC_A_CLK>;
};
tsens: thermal-sensor@4a9000 {
@@ -574,18 +572,12 @@
compatible = "qcom,msm8916-pcnoc";
reg = <0x00500000 0x11000>;
#interconnect-cells = <1>;
- clock-names = "bus", "bus_a";
- clocks = <&rpmcc RPM_SMD_PCNOC_CLK>,
- <&rpmcc RPM_SMD_PCNOC_A_CLK>;
};
snoc: interconnect@580000 {
compatible = "qcom,msm8916-snoc";
reg = <0x00580000 0x14000>;
#interconnect-cells = <1>;
- clock-names = "bus", "bus_a";
- clocks = <&rpmcc RPM_SMD_SNOC_CLK>,
- <&rpmcc RPM_SMD_SNOC_A_CLK>;
};
stm: stm@802000 {
@@ -1989,6 +1981,54 @@
label = "hexagon";
+ apr: apr {
+ compatible = "qcom,apr-v2";
+ qcom,smd-channels = "apr_audio_svc";
+ qcom,domain = <APR_DOMAIN_ADSP>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+
+ q6core: service@3 {
+ compatible = "qcom,q6core";
+ reg = <APR_SVC_ADSP_CORE>;
+ };
+
+ q6afe: service@4 {
+ compatible = "qcom,q6afe";
+ reg = <APR_SVC_AFE>;
+
+ q6afedai: dais {
+ compatible = "qcom,q6afe-dais";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ #sound-dai-cells = <1>;
+ };
+ };
+
+ q6asm: service@7 {
+ compatible = "qcom,q6asm";
+ reg = <APR_SVC_ASM>;
+
+ q6asmdai: dais {
+ compatible = "qcom,q6asm-dais";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ #sound-dai-cells = <1>;
+ };
+ };
+
+ q6adm: service@8 {
+ compatible = "qcom,q6adm";
+ reg = <APR_SVC_ADM>;
+
+ q6routing: routing {
+ compatible = "qcom,q6adm-routing";
+ #sound-dai-cells = <0>;
+ };
+ };
+ };
+
fastrpc {
compatible = "qcom,fastrpc";
qcom,smd-channels = "fastrpcsmd-apps-dsp";
@@ -2106,6 +2146,7 @@
clock-names = "bam_clk";
#dma-cells = <1>;
qcom,ee = <0>;
+ qcom,controlled-remotely;
};
blsp_uart1: serial@78af000 {
diff --git a/dts/upstream/src/arm64/qcom/msm8939-huawei-kiwi.dts b/dts/upstream/src/arm64/qcom/msm8939-huawei-kiwi.dts
new file mode 100644
index 0000000..3cec518
--- /dev/null
+++ b/dts/upstream/src/arm64/qcom/msm8939-huawei-kiwi.dts
@@ -0,0 +1,242 @@
+// SPDX-License-Identifier: GPL-2.0-only
+
+/dts-v1/;
+
+#include "msm8939-pm8916.dtsi"
+#include <dt-bindings/gpio/gpio.h>
+
+/ {
+ model = "Huawei Honor 5X / GR5 (2016)";
+ compatible = "huawei,kiwi", "qcom,msm8939";
+ chassis-type = "handset";
+
+ aliases {
+ mmc0 = &sdhc_1; /* SDC1 eMMC slot */
+ mmc1 = &sdhc_2; /* SDC2 SD card slot */
+ serial0 = &blsp_uart2;
+ };
+
+ chosen {
+ stdout-path = "serial0";
+ };
+
+ reserved-memory {
+ qseecom_mem: qseecom@84a00000 {
+ reg = <0x0 0x84a00000 0x0 0x1600000>;
+ no-map;
+ };
+ };
+
+ gpio-hall-sensor {
+ compatible = "gpio-keys";
+
+ pinctrl-0 = <&gpio_hall_sensor_default>;
+ pinctrl-names = "default";
+
+ label = "GPIO Hall Effect Sensor";
+
+ event-hall-sensor {
+ label = "Hall Effect Sensor";
+ gpios = <&tlmm 69 GPIO_ACTIVE_LOW>;
+ linux,input-type = <EV_SW>;
+ linux,code = <SW_LID>;
+ linux,can-disable;
+ };
+ };
+
+ gpio-keys {
+ compatible = "gpio-keys";
+
+ pinctrl-0 = <&gpio_keys_default>;
+ pinctrl-names = "default";
+
+ label = "GPIO Buttons";
+
+ button-volume-up {
+ label = "Volume Up";
+ gpios = <&tlmm 107 GPIO_ACTIVE_LOW>;
+ linux,code = <KEY_VOLUMEUP>;
+ };
+ };
+
+ usb_id: usb-id {
+ compatible = "linux,extcon-usb-gpio";
+ id-gpios = <&tlmm 110 GPIO_ACTIVE_HIGH>;
+ pinctrl-0 = <&usb_id_default>;
+ pinctrl-names = "default";
+ };
+};
+
+&blsp_i2c2 {
+ status = "okay";
+
+ accelerometer@1e {
+ compatible = "kionix,kx023-1025";
+ reg = <0x1e>;
+
+ vdd-supply = <&pm8916_l17>;
+ vddio-supply = <&pm8916_l6>;
+ pinctrl-0 = <&accel_int_default>;
+ pinctrl-names = "default";
+ mount-matrix = "-1", "0", "0",
+ "0", "1", "0",
+ "0", "0", "1";
+ };
+
+ proximity@39 {
+ compatible = "avago,apds9930";
+ reg = <0x39>;
+
+ interrupt-parent = <&tlmm>;
+ interrupts = <113 IRQ_TYPE_EDGE_FALLING>;
+
+ vdd-supply = <&pm8916_l17>;
+ vddio-supply = <&pm8916_l6>;
+
+ led-max-microamp = <25000>;
+ amstaos,proximity-diodes = <0>;
+
+ pinctrl-0 = <&prox_irq_default>;
+ pinctrl-names = "default";
+ };
+};
+
+&blsp_i2c5 {
+ status = "okay";
+
+ touchscreen@1c {
+ compatible = "cypress,tt21000";
+
+ reg = <0x1c>;
+ interrupt-parent = <&tlmm>;
+ interrupts = <13 IRQ_TYPE_EDGE_FALLING>;
+
+ reset-gpios = <&tlmm 12 GPIO_ACTIVE_LOW>;
+
+ /*
+ * NOTE: vdd is not directly supplied by pm8916_l16, it seems to be a
+ * fixed regulator that is automatically enabled by pm8916_l16.
+ */
+ vdd-supply = <&pm8916_l16>;
+ vddio-supply = <&pm8916_l16>;
+
+ pinctrl-0 = <&touchscreen_default>;
+ pinctrl-names = "default";
+ };
+};
+
+&blsp_uart2 {
+ status = "okay";
+};
+
+&pm8916_l8 {
+ regulator-min-microvolt = <2950000>;
+ regulator-max-microvolt = <2950000>;
+};
+
+&pm8916_resin {
+ linux,code = <KEY_VOLUMEDOWN>;
+ status = "okay";
+};
+
+&pm8916_rpm_regulators {
+ pm8916_l16: l16 {
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ };
+
+ pm8916_l17: l17 {
+ regulator-min-microvolt = <2850000>;
+ regulator-max-microvolt = <2850000>;
+ };
+};
+
+&pm8916_vib {
+ status = "okay";
+};
+
+&sdhc_1 {
+ status = "okay";
+};
+
+&sdhc_2 {
+ pinctrl-0 = <&sdc2_default &sdc2_cd_default>;
+ pinctrl-1 = <&sdc2_sleep &sdc2_cd_default>;
+ pinctrl-names = "default", "sleep";
+
+ cd-gpios = <&tlmm 38 GPIO_ACTIVE_HIGH>;
+
+ status = "okay";
+};
+
+&usb {
+ extcon = <&usb_id>, <&usb_id>;
+ status = "okay";
+};
+
+&usb_hs_phy {
+ extcon = <&usb_id>;
+};
+
+&wcnss {
+ status = "okay";
+};
+
+&wcnss_iris {
+ compatible = "qcom,wcn3620";
+};
+
+&wcnss_mem {
+ status = "okay";
+};
+
+&tlmm {
+ accel_int_default: accel-int-default-state {
+ pins = "gpio115";
+ function = "gpio";
+ drive-strength = <2>;
+ bias-disable;
+ };
+
+ gpio_hall_sensor_default: gpio-hall-sensor-default-state {
+ pins = "gpio69";
+ function = "gpio";
+ drive-strength = <2>;
+ bias-disable;
+ };
+
+ gpio_keys_default: gpio-keys-default-state {
+ pins = "gpio107";
+ function = "gpio";
+ drive-strength = <2>;
+ bias-pull-up;
+ };
+
+ prox_irq_default: prox-irq-default-state {
+ pins = "gpio113";
+ function = "gpio";
+ drive-strength = <2>;
+ bias-disable;
+ };
+
+ sdc2_cd_default: sdc2-cd-default-state {
+ pins = "gpio38";
+ function = "gpio";
+ drive-strength = <2>;
+ bias-disable;
+ };
+
+ touchscreen_default: touchscreen-default-state {
+ pins = "gpio12", "gpio13";
+ function = "gpio";
+ drive-strength = <2>;
+ bias-disable;
+ };
+
+ usb_id_default: usb-id-default-state {
+ pins = "gpio110";
+ function = "gpio";
+ drive-strength = <8>;
+ bias-pull-up;
+ };
+};
diff --git a/dts/upstream/src/arm64/qcom/msm8939-longcheer-l9100.dts b/dts/upstream/src/arm64/qcom/msm8939-longcheer-l9100.dts
index 6802714..e3404c4 100644
--- a/dts/upstream/src/arm64/qcom/msm8939-longcheer-l9100.dts
+++ b/dts/upstream/src/arm64/qcom/msm8939-longcheer-l9100.dts
@@ -8,6 +8,7 @@
#include <dt-bindings/input/input.h>
#include <dt-bindings/interrupt-controller/irq.h>
#include <dt-bindings/leds/common.h>
+#include <dt-bindings/pinctrl/qcom,pmic-gpio.h>
#include <dt-bindings/pinctrl/qcom,pmic-mpp.h>
/ {
@@ -120,6 +121,46 @@
};
+&blsp_i2c2 {
+ status = "okay";
+
+ led-controller@30 {
+ compatible = "kinetic,ktd2026";
+ reg = <0x30>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ vin-supply = <&pm8916_l17>;
+ vio-supply = <&pm8916_l6>;
+
+ pinctrl-0 = <&status_led_default>;
+ pinctrl-names = "default";
+
+ multi-led {
+ color = <LED_COLOR_ID_RGB>;
+ function = LED_FUNCTION_STATUS;
+
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ led@0 {
+ reg = <0>;
+ color = <LED_COLOR_ID_RED>;
+ };
+
+ led@1 {
+ reg = <1>;
+ color = <LED_COLOR_ID_GREEN>;
+ };
+
+ led@2 {
+ reg = <2>;
+ color = <LED_COLOR_ID_BLUE>;
+ };
+ };
+ };
+};
+
&blsp_i2c3 {
status = "okay";
@@ -139,6 +180,7 @@
light-sensor@23 {
compatible = "liteon,ltr559";
reg = <0x23>;
+ proximity-near-level = <75>;
vdd-supply = <&pm8916_l17>;
vddio-supply = <&pm8916_l5>;
@@ -184,6 +226,16 @@
status = "okay";
};
+&pm8916_gpios {
+ status_led_default: status-led-default-state {
+ pins = "gpio3";
+ function = PMIC_GPIO_FUNC_NORMAL;
+ power-source = <PM8916_GPIO_VPH>;
+ bias-disable;
+ output-high;
+ };
+};
+
&pm8916_mpps {
pwm_out: mpp4-state {
pins = "mpp4";
@@ -247,6 +299,10 @@
compatible = "qcom,wcn3620";
};
+&wcnss_mem {
+ status = "okay";
+};
+
&tlmm {
button_backlight_default: button-backlight-default-state {
pins = "gpio17";
diff --git a/dts/upstream/src/arm64/qcom/msm8939-samsung-a7.dts b/dts/upstream/src/arm64/qcom/msm8939-samsung-a7.dts
index fccd8fe..aa6c394 100644
--- a/dts/upstream/src/arm64/qcom/msm8939-samsung-a7.dts
+++ b/dts/upstream/src/arm64/qcom/msm8939-samsung-a7.dts
@@ -3,10 +3,12 @@
/dts-v1/;
#include "msm8939-pm8916.dtsi"
+#include "msm8916-modem-qdsp6.dtsi"
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/input/input.h>
#include <dt-bindings/interrupt-controller/irq.h>
+#include <dt-bindings/sound/apq8016-lpass.h>
/ {
model = "Samsung Galaxy A7 (2015)";
@@ -287,6 +289,18 @@
};
};
+&blsp_i2c2 {
+ status = "okay";
+
+ speaker_codec: audio-codec@34 {
+ compatible = "nxp,tfa9895";
+ reg = <0x34>;
+ vddd-supply = <&pm8916_l5>;
+ sound-name-prefix = "Speaker";
+ #sound-dai-cells = <0>;
+ };
+};
+
&blsp_i2c5 {
status = "okay";
@@ -309,6 +323,29 @@
status = "okay";
};
+/*
+ * For some reason the speaker amplifier is connected to the second SD line
+ * (MI2S_2_D1) instead of the first (MI2S_2_D0). This must be configured in the
+ * device tree, otherwise audio will seemingly play fine on the wrong SD line
+ * but the speaker stays silent.
+ *
+ * When routing audio via QDSP6 (the default) the &lpass node is reserved and
+ * the definitions from &q6afedai are used. When the modem is disabled audio can
+ * be alternatively routed directly to the LPASS hardware with reduced latency.
+ * The definitions for &lpass are here for completeness to simplify changing the
+ * setup with minor changes to the DT (either manually or with DT overlays).
+ */
+&lpass {
+ dai-link@3 {
+ reg = <MI2S_QUATERNARY>;
+ qcom,playback-sd-lines = <1>;
+ };
+};
+
+&mpss_mem {
+ reg = <0x0 0x86800000 0x0 0x5800000>;
+};
+
&pm8916_resin {
linux,code = <KEY_VOLUMEDOWN>;
status = "okay";
@@ -321,6 +358,13 @@
};
};
+&q6afedai {
+ dai@22 {
+ reg = <QUATERNARY_MI2S_RX>;
+ qcom,sd-lines = <1>;
+ };
+};
+
&sdhc_1 {
status = "okay";
};
@@ -335,6 +379,32 @@
status = "okay";
};
+&sound {
+ model = "samsung-a2015";
+ audio-routing =
+ "AMIC1", "MIC BIAS External1",
+ "AMIC2", "MIC BIAS Internal2",
+ "AMIC3", "MIC BIAS External1";
+
+ pinctrl-0 = <&cdc_pdm_default &sec_mi2s_default>;
+ pinctrl-1 = <&cdc_pdm_sleep &sec_mi2s_sleep>;
+ pinctrl-names = "default", "sleep";
+
+ sound_link_backend2: backend2-dai-link {
+ link-name = "Quaternary MI2S";
+
+ cpu {
+ sound-dai = <&q6afedai QUATERNARY_MI2S_RX>;
+ };
+ platform {
+ sound-dai = <&q6routing>;
+ };
+ codec {
+ sound-dai = <&speaker_codec>;
+ };
+ };
+};
+
&usb {
extcon = <&muic>, <&muic>;
status = "okay";
diff --git a/dts/upstream/src/arm64/qcom/msm8939.dtsi b/dts/upstream/src/arm64/qcom/msm8939.dtsi
index 324b5d2..82d85ff 100644
--- a/dts/upstream/src/arm64/qcom/msm8939.dtsi
+++ b/dts/upstream/src/arm64/qcom/msm8939.dtsi
@@ -10,6 +10,7 @@
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/power/qcom-rpmpd.h>
#include <dt-bindings/reset/qcom,gcc-msm8939.h>
+#include <dt-bindings/soc/qcom,apr.h>
#include <dt-bindings/thermal/thermal.h>
/ {
@@ -601,9 +602,6 @@
bimc: interconnect@400000 {
compatible = "qcom,msm8939-bimc";
reg = <0x00400000 0x62000>;
- clock-names = "bus", "bus_a";
- clocks = <&rpmcc RPM_SMD_BIMC_CLK>,
- <&rpmcc RPM_SMD_BIMC_A_CLK>;
#interconnect-cells = <1>;
};
@@ -647,25 +645,16 @@
pcnoc: interconnect@500000 {
compatible = "qcom,msm8939-pcnoc";
reg = <0x00500000 0x11000>;
- clock-names = "bus", "bus_a";
- clocks = <&rpmcc RPM_SMD_PCNOC_CLK>,
- <&rpmcc RPM_SMD_PCNOC_A_CLK>;
#interconnect-cells = <1>;
};
snoc: interconnect@580000 {
compatible = "qcom,msm8939-snoc";
reg = <0x00580000 0x14080>;
- clock-names = "bus", "bus_a";
- clocks = <&rpmcc RPM_SMD_SNOC_CLK>,
- <&rpmcc RPM_SMD_SNOC_A_CLK>;
#interconnect-cells = <1>;
snoc_mm: interconnect-snoc {
compatible = "qcom,msm8939-snoc-mm";
- clock-names = "bus", "bus_a";
- clocks = <&rpmcc RPM_SMD_SYSMMNOC_CLK>,
- <&rpmcc RPM_SMD_SYSMMNOC_A_CLK>;
#interconnect-cells = <1>;
};
};
@@ -1537,6 +1526,20 @@
#interrupt-cells = <4>;
};
+ bam_dmux_dma: dma-controller@4044000 {
+ compatible = "qcom,bam-v1.7.0";
+ reg = <0x04044000 0x19000>;
+ interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
+ #dma-cells = <1>;
+ qcom,ee = <0>;
+
+ num-channels = <6>;
+ qcom,num-ees = <1>;
+ qcom,powered-remotely;
+
+ status = "disabled";
+ };
+
mpss: remoteproc@4080000 {
compatible = "qcom,msm8916-mss-pil";
reg = <0x04080000 0x100>, <0x04020000 0x040>;
@@ -1569,6 +1572,22 @@
qcom,halt-regs = <&tcsr 0x18000 0x19000 0x1a000>;
status = "disabled";
+ bam_dmux: bam-dmux {
+ compatible = "qcom,bam-dmux";
+
+ interrupt-parent = <&hexagon_smsm>;
+ interrupts = <1 IRQ_TYPE_EDGE_BOTH>, <11 IRQ_TYPE_EDGE_BOTH>;
+ interrupt-names = "pc", "pc-ack";
+
+ qcom,smem-states = <&apps_smsm 1>, <&apps_smsm 11>;
+ qcom,smem-state-names = "pc", "pc-ack";
+
+ dmas = <&bam_dmux_dma 4>, <&bam_dmux_dma 5>;
+ dma-names = "tx", "rx";
+
+ status = "disabled";
+ };
+
mba {
memory-region = <&mba_mem>;
};
@@ -1585,6 +1604,54 @@
qcom,remote-pid = <1>;
label = "hexagon";
+
+ apr: apr {
+ compatible = "qcom,apr-v2";
+ qcom,smd-channels = "apr_audio_svc";
+ qcom,domain = <APR_DOMAIN_ADSP>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+
+ q6core: service@3 {
+ compatible = "qcom,q6core";
+ reg = <APR_SVC_ADSP_CORE>;
+ };
+
+ q6afe: service@4 {
+ compatible = "qcom,q6afe";
+ reg = <APR_SVC_AFE>;
+
+ q6afedai: dais {
+ compatible = "qcom,q6afe-dais";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ #sound-dai-cells = <1>;
+ };
+ };
+
+ q6asm: service@7 {
+ compatible = "qcom,q6asm";
+ reg = <APR_SVC_ASM>;
+
+ q6asmdai: dais {
+ compatible = "qcom,q6asm-dais";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ #sound-dai-cells = <1>;
+ };
+ };
+
+ q6adm: service@8 {
+ compatible = "qcom,q6adm";
+ reg = <APR_SVC_ADM>;
+
+ q6routing: routing {
+ compatible = "qcom,q6adm-routing";
+ #sound-dai-cells = <0>;
+ };
+ };
+ };
};
};
@@ -1682,6 +1749,7 @@
clock-names = "bam_clk";
#dma-cells = <1>;
qcom,ee = <0>;
+ qcom,controlled-remotely;
};
blsp_uart1: serial@78af000 {
@@ -2116,6 +2184,8 @@
#address-cells = <1>;
#size-cells = <1>;
ranges;
+ /* Necessary because firmware does not configure this correctly */
+ clock-frequency = <19200000>;
frame@b121000 {
reg = <0x0b121000 0x1000>,
diff --git a/dts/upstream/src/arm64/qcom/msm8953-xiaomi-mido.dts b/dts/upstream/src/arm64/qcom/msm8953-xiaomi-mido.dts
index ed95d09..6b9245c 100644
--- a/dts/upstream/src/arm64/qcom/msm8953-xiaomi-mido.dts
+++ b/dts/upstream/src/arm64/qcom/msm8953-xiaomi-mido.dts
@@ -111,6 +111,7 @@
reg = <0x45>;
vcc-supply = <&pm8953_l10>;
+ vio-supply = <&pm8953_l5>;
#address-cells = <1>;
#size-cells = <0>;
diff --git a/dts/upstream/src/arm64/qcom/msm8953-xiaomi-tissot.dts b/dts/upstream/src/arm64/qcom/msm8953-xiaomi-tissot.dts
index 61ff629..9ac4f50 100644
--- a/dts/upstream/src/arm64/qcom/msm8953-xiaomi-tissot.dts
+++ b/dts/upstream/src/arm64/qcom/msm8953-xiaomi-tissot.dts
@@ -104,6 +104,7 @@
reg = <0x45>;
vcc-supply = <&pm8953_l10>;
+ vio-supply = <&pm8953_l5>;
#address-cells = <1>;
#size-cells = <0>;
diff --git a/dts/upstream/src/arm64/qcom/msm8953-xiaomi-vince.dts b/dts/upstream/src/arm64/qcom/msm8953-xiaomi-vince.dts
index 1a1d3f9..b0588f3 100644
--- a/dts/upstream/src/arm64/qcom/msm8953-xiaomi-vince.dts
+++ b/dts/upstream/src/arm64/qcom/msm8953-xiaomi-vince.dts
@@ -113,6 +113,7 @@
reg = <0x45>;
vcc-supply = <&pm8953_l10>;
+ vio-supply = <&pm8953_l5>;
#address-cells = <1>;
#size-cells = <0>;
diff --git a/dts/upstream/src/arm64/qcom/msm8953.dtsi b/dts/upstream/src/arm64/qcom/msm8953.dtsi
index e7de763..ad2f8cf 100644
--- a/dts/upstream/src/arm64/qcom/msm8953.dtsi
+++ b/dts/upstream/src/arm64/qcom/msm8953.dtsi
@@ -174,10 +174,10 @@
};
};
- memory {
+ memory@10000000 {
device_type = "memory";
/* We expect the bootloader to fill in the reg */
- reg = <0 0 0 0>;
+ reg = <0 0x10000000 0 0>;
};
pmu {
@@ -726,6 +726,48 @@
bias-disable;
};
+ spi_3_default: spi-3-default-state {
+ pins = "gpio10", "gpio11";
+ function = "blsp_spi3";
+ drive-strength = <2>;
+ bias-disable;
+ };
+
+ spi_3_sleep: spi-3-sleep-state {
+ pins = "gpio10", "gpio11";
+ function = "gpio";
+ drive-strength = <2>;
+ bias-disable;
+ };
+
+ spi_5_default: spi-5-default-state {
+ pins = "gpio18", "gpio19";
+ function = "blsp_spi5";
+ drive-strength = <2>;
+ bias-disable;
+ };
+
+ spi_5_sleep: spi-5-sleep-state {
+ pins = "gpio18", "gpio19";
+ function = "gpio";
+ drive-strength = <2>;
+ bias-disable;
+ };
+
+ spi_6_default: spi-6-default-state {
+ pins = "gpio22", "gpio23";
+ function = "blsp_spi6";
+ drive-strength = <2>;
+ bias-disable;
+ };
+
+ spi_6_sleep: spi-6-sleep-state {
+ pins = "gpio22", "gpio23";
+ function = "gpio";
+ drive-strength = <2>;
+ bias-disable;
+ };
+
wcnss_pin_a: wcnss-active-state {
wcss-wlan2-pins {
@@ -1004,7 +1046,7 @@
apps_iommu: iommu@1e20000 {
compatible = "qcom,msm8953-iommu", "qcom,msm-iommu-v1";
- ranges = <0 0x01e20000 0x20000>;
+ ranges = <0 0x01e20000 0x20000>;
clocks = <&gcc GCC_SMMU_CFG_CLK>,
<&gcc GCC_APSS_TCU_ASYNC_CLK>;
@@ -1360,6 +1402,26 @@
status = "disabled";
};
+ spi_3: spi@78b7000 {
+ compatible = "qcom,spi-qup-v2.2.1";
+ reg = <0x078b7000 0x600>;
+ interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>;
+ clock-names = "core", "iface";
+ clocks = <&gcc GCC_BLSP1_QUP3_I2C_APPS_CLK>,
+ <&gcc GCC_BLSP1_AHB_CLK>;
+ dmas = <&blsp1_dma 8>, <&blsp1_dma 9>;
+ dma-names = "tx", "rx";
+
+ pinctrl-names = "default", "sleep";
+ pinctrl-0 = <&spi_3_default>;
+ pinctrl-1 = <&spi_3_sleep>;
+
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ status = "disabled";
+ };
+
i2c_4: i2c@78b8000 {
compatible = "qcom,i2c-qup-v2.2.1";
reg = <0x078b8000 0x600>;
@@ -1413,6 +1475,26 @@
status = "disabled";
};
+ spi_5: spi@7af5000 {
+ compatible = "qcom,spi-qup-v2.2.1";
+ reg = <0x07af5000 0x600>;
+ interrupts = <GIC_SPI 299 IRQ_TYPE_LEVEL_HIGH>;
+ clock-names = "core", "iface";
+ clocks = <&gcc GCC_BLSP2_QUP1_I2C_APPS_CLK>,
+ <&gcc GCC_BLSP2_AHB_CLK>;
+ dmas = <&blsp2_dma 4>, <&blsp2_dma 5>;
+ dma-names = "tx", "rx";
+
+ pinctrl-names = "default", "sleep";
+ pinctrl-0 = <&spi_5_default>;
+ pinctrl-1 = <&spi_5_sleep>;
+
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ status = "disabled";
+ };
+
i2c_6: i2c@7af6000 {
compatible = "qcom,i2c-qup-v2.2.1";
reg = <0x07af6000 0x600>;
@@ -1433,6 +1515,26 @@
status = "disabled";
};
+ spi_6: spi@7af6000 {
+ compatible = "qcom,spi-qup-v2.2.1";
+ reg = <0x07af6000 0x600>;
+ interrupts = <GIC_SPI 300 IRQ_TYPE_LEVEL_HIGH>;
+ clock-names = "core", "iface";
+ clocks = <&gcc GCC_BLSP2_QUP2_I2C_APPS_CLK>,
+ <&gcc GCC_BLSP2_AHB_CLK>;
+ dmas = <&blsp2_dma 6>, <&blsp2_dma 7>;
+ dma-names = "tx", "rx";
+
+ pinctrl-names = "default", "sleep";
+ pinctrl-0 = <&spi_6_default>;
+ pinctrl-1 = <&spi_6_sleep>;
+
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ status = "disabled";
+ };
+
i2c_7: i2c@7af7000 {
compatible = "qcom,i2c-qup-v2.2.1";
reg = <0x07af7000 0x600>;
@@ -1645,7 +1747,7 @@
apr {
compatible = "qcom,apr-v2";
qcom,smd-channels = "apr_audio_svc";
- qcom,apr-domain = <APR_DOMAIN_ADSP>;
+ qcom,domain = <APR_DOMAIN_ADSP>;
#address-cells = <1>;
#size-cells = <0>;
diff --git a/dts/upstream/src/arm64/qcom/msm8996.dtsi b/dts/upstream/src/arm64/qcom/msm8996.dtsi
index 6ba9da9..ee6f87c 100644
--- a/dts/upstream/src/arm64/qcom/msm8996.dtsi
+++ b/dts/upstream/src/arm64/qcom/msm8996.dtsi
@@ -444,6 +444,19 @@
reg = <0x0 0x80000000 0x0 0x0>;
};
+ etm {
+ compatible = "qcom,coresight-remote-etm";
+
+ out-ports {
+ port {
+ modem_etm_out_funnel_in2: endpoint {
+ remote-endpoint =
+ <&funnel_in2_in_modem_etm>;
+ };
+ };
+ };
+ };
+
psci {
compatible = "arm,psci-1.0";
method = "smc";
@@ -779,10 +792,10 @@
<&pciephy_0>,
<&pciephy_1>,
<&pciephy_2>,
- <&ssusb_phy_0>,
- <&ufsphy_lane 0>,
- <&ufsphy_lane 1>,
- <&ufsphy_lane 2>;
+ <&usb3phy>,
+ <&ufsphy 0>,
+ <&ufsphy 1>,
+ <&ufsphy 2>;
clock-names = "cxo",
"cxo2",
"sleep_clk",
@@ -799,9 +812,6 @@
compatible = "qcom,msm8996-bimc";
reg = <0x00408000 0x5a000>;
#interconnect-cells = <1>;
- clock-names = "bus", "bus_a";
- clocks = <&rpmcc RPM_SMD_BIMC_CLK>,
- <&rpmcc RPM_SMD_BIMC_A_CLK>;
};
tsens0: thermal-sensor@4a9000 {
@@ -852,18 +862,12 @@
compatible = "qcom,msm8996-cnoc";
reg = <0x00500000 0x1000>;
#interconnect-cells = <1>;
- clock-names = "bus", "bus_a";
- clocks = <&rpmcc RPM_SMD_CNOC_CLK>,
- <&rpmcc RPM_SMD_CNOC_A_CLK>;
};
snoc: interconnect@524000 {
compatible = "qcom,msm8996-snoc";
reg = <0x00524000 0x1c000>;
#interconnect-cells = <1>;
- clock-names = "bus", "bus_a";
- clocks = <&rpmcc RPM_SMD_SNOC_CLK>,
- <&rpmcc RPM_SMD_SNOC_A_CLK>;
};
a0noc: interconnect@543000 {
@@ -883,19 +887,14 @@
compatible = "qcom,msm8996-a1noc";
reg = <0x00562000 0x5000>;
#interconnect-cells = <1>;
- clock-names = "bus", "bus_a";
- clocks = <&rpmcc RPM_SMD_AGGR1_NOC_CLK>,
- <&rpmcc RPM_SMD_AGGR1_NOC_A_CLK>;
};
a2noc: interconnect@583000 {
compatible = "qcom,msm8996-a2noc";
reg = <0x00583000 0x7000>;
#interconnect-cells = <1>;
- clock-names = "bus", "bus_a", "aggre2_ufs_axi", "ufs_axi";
- clocks = <&rpmcc RPM_SMD_AGGR2_NOC_CLK>,
- <&rpmcc RPM_SMD_AGGR2_NOC_A_CLK>,
- <&gcc GCC_AGGRE2_UFS_AXI_CLK>,
+ clock-names = "aggre2_ufs_axi", "ufs_axi";
+ clocks = <&gcc GCC_AGGRE2_UFS_AXI_CLK>,
<&gcc GCC_UFS_AXI_CLK>;
};
@@ -903,19 +902,14 @@
compatible = "qcom,msm8996-mnoc";
reg = <0x005a4000 0x1c000>;
#interconnect-cells = <1>;
- clock-names = "bus", "bus_a", "iface";
- clocks = <&rpmcc RPM_SMD_MMAXI_CLK>,
- <&rpmcc RPM_SMD_MMAXI_A_CLK>,
- <&mmcc AHB_CLK_SRC>;
+ clock-names = "iface";
+ clocks = <&mmcc AHB_CLK_SRC>;
};
pnoc: interconnect@5c0000 {
compatible = "qcom,msm8996-pnoc";
reg = <0x005c0000 0x3000>;
#interconnect-cells = <1>;
- clock-names = "bus", "bus_a";
- clocks = <&rpmcc RPM_SMD_PCNOC_CLK>,
- <&rpmcc RPM_SMD_PCNOC_A_CLK>;
};
tcsr_mutex: hwlock@740000 {
@@ -2047,7 +2041,7 @@
reg = <0x00624000 0x2500>;
interrupts = <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH>;
- phys = <&ufsphy_lane>;
+ phys = <&ufsphy>;
phy-names = "ufsphy";
power-domains = <&gcc UFS_GDSC>;
@@ -2100,25 +2094,18 @@
ufsphy: phy@627000 {
compatible = "qcom,msm8996-qmp-ufs-phy";
- reg = <0x00627000 0x1c4>;
- #address-cells = <1>;
- #size-cells = <1>;
- ranges;
+ reg = <0x00627000 0x1000>;
clocks = <&gcc GCC_UFS_CLKREF_CLK>;
clock-names = "ref";
resets = <&ufshc 0>;
reset-names = "ufsphy";
- status = "disabled";
- ufsphy_lane: phy@627400 {
- reg = <0x627400 0x12c>,
- <0x627600 0x200>,
- <0x627c00 0x1b4>;
- #clock-cells = <1>;
- #phy-cells = <0>;
- };
+ #clock-cells = <1>;
+ #phy-cells = <0>;
+
+ status = "disabled";
};
camss: camss@a34000 {
@@ -2453,9 +2440,8 @@
"handover",
"stop-ack";
- clocks = <&xo_board>,
- <&rpmcc RPM_SMD_AGGR2_NOC_CLK>;
- clock-names = "xo", "aggre2";
+ clocks = <&xo_board>;
+ clock-names = "xo";
memory-region = <&slpi_mem>;
@@ -2500,10 +2486,15 @@
<&gcc GCC_MSS_GPLL0_DIV_CLK>,
<&gcc GCC_MSS_SNOC_AXI_CLK>,
<&gcc GCC_MSS_MNOC_BIMC_AXI_CLK>,
- <&rpmcc RPM_SMD_PCNOC_CLK>,
<&rpmcc RPM_SMD_QDSS_CLK>;
- clock-names = "iface", "bus", "mem", "xo", "gpll0_mss",
- "snoc_axi", "mnoc_axi", "pnoc", "qdss";
+ clock-names = "iface",
+ "bus",
+ "mem",
+ "xo",
+ "gpll0_mss",
+ "snoc_axi",
+ "mnoc_axi",
+ "qdss";
resets = <&gcc GCC_MSS_RESTART>;
reset-names = "mss_restart";
@@ -2644,6 +2635,14 @@
clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>;
clock-names = "apb_pclk", "atclk";
+ in-ports {
+ port {
+ funnel_in2_in_modem_etm: endpoint {
+ remote-endpoint =
+ <&modem_etm_out_funnel_in2>;
+ };
+ };
+ };
out-ports {
port {
@@ -3056,7 +3055,7 @@
compatible = "snps,dwc3";
reg = <0x06a00000 0xcc00>;
interrupts = <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>;
- phys = <&hsusb_phy1>, <&ssusb_phy_0>;
+ phys = <&hsusb_phy1>, <&usb3phy>;
phy-names = "usb2-phy", "usb3-phy";
snps,hird-threshold = /bits/ 8 <0>;
snps,dis_u2_susphy_quirk;
@@ -3068,32 +3067,26 @@
usb3phy: phy@7410000 {
compatible = "qcom,msm8996-qmp-usb3-phy";
- reg = <0x07410000 0x1c4>;
- #address-cells = <1>;
- #size-cells = <1>;
- ranges;
+ reg = <0x07410000 0x1000>;
clocks = <&gcc GCC_USB3_PHY_AUX_CLK>,
- <&gcc GCC_USB_PHY_CFG_AHB2PHY_CLK>,
- <&gcc GCC_USB3_CLKREF_CLK>;
- clock-names = "aux", "cfg_ahb", "ref";
+ <&gcc GCC_USB3_CLKREF_CLK>,
+ <&gcc GCC_USB_PHY_CFG_AHB2PHY_CLK>,
+ <&gcc GCC_USB3_PHY_PIPE_CLK>;
+ clock-names = "aux",
+ "ref",
+ "cfg_ahb",
+ "pipe";
+ clock-output-names = "usb3_phy_pipe_clk_src";
+ #clock-cells = <0>;
+ #phy-cells = <0>;
resets = <&gcc GCC_USB3_PHY_BCR>,
- <&gcc GCC_USB3PHY_PHY_BCR>;
- reset-names = "phy", "common";
- status = "disabled";
-
- ssusb_phy_0: phy@7410200 {
- reg = <0x07410200 0x200>,
- <0x07410400 0x130>,
- <0x07410600 0x1a8>;
- #phy-cells = <0>;
+ <&gcc GCC_USB3PHY_PHY_BCR>;
+ reset-names = "phy",
+ "phy_phy";
- #clock-cells = <0>;
- clock-output-names = "usb3_phy_pipe_clk_src";
- clocks = <&gcc GCC_USB3_PHY_PIPE_CLK>;
- clock-names = "pipe0";
- };
+ status = "disabled";
};
hsusb_phy1: phy@7411000 {
diff --git a/dts/upstream/src/arm64/qcom/msm8998.dtsi b/dts/upstream/src/arm64/qcom/msm8998.dtsi
index b485bf9..2793cc2 100644
--- a/dts/upstream/src/arm64/qcom/msm8998.dtsi
+++ b/dts/upstream/src/arm64/qcom/msm8998.dtsi
@@ -933,7 +933,7 @@
<GIC_SPI 465 IRQ_TYPE_EDGE_RISING>;
};
- pcie0: pci@1c00000 {
+ pcie0: pcie@1c00000 {
compatible = "qcom,pcie-msm8998", "qcom,pcie-msm8996";
reg = <0x01c00000 0x2000>,
<0x1b000000 0xf1d>,
@@ -1004,7 +1004,7 @@
compatible = "qcom,msm8998-ufshc", "qcom,ufshc", "jedec,ufs-2.0";
reg = <0x01da4000 0x2500>;
interrupts = <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH>;
- phys = <&ufsphy_lanes>;
+ phys = <&ufsphy>;
phy-names = "ufsphy";
lanes-per-direction = <2>;
power-domains = <&gcc UFS_GDSC>;
@@ -1045,11 +1045,7 @@
ufsphy: phy@1da7000 {
compatible = "qcom,msm8998-qmp-ufs-phy";
- reg = <0x01da7000 0x18c>;
- #address-cells = <1>;
- #size-cells = <1>;
- status = "disabled";
- ranges;
+ reg = <0x01da7000 0x1000>;
clock-names =
"ref",
@@ -1061,14 +1057,8 @@
reset-names = "ufsphy";
resets = <&ufshc 0>;
- ufsphy_lanes: phy@1da7400 {
- reg = <0x01da7400 0x128>,
- <0x01da7600 0x1fc>,
- <0x01da7c00 0x1dc>,
- <0x01da7800 0x128>,
- <0x01da7a00 0x1fc>;
- #phy-cells = <0>;
- };
+ #phy-cells = <0>;
+ status = "disabled";
};
tcsr_mutex: hwlock@1f40000 {
@@ -1615,9 +1605,8 @@
px-supply = <&vreg_lvs2a_1p8>;
- clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>,
- <&rpmcc RPM_SMD_AGGR2_NOC_CLK>;
- clock-names = "xo", "aggre2";
+ clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>;
+ clock-names = "xo";
memory-region = <&slpi_mem>;
@@ -2031,9 +2020,11 @@
cpu = <&CPU4>;
- port {
- etm4_out: endpoint {
- remote-endpoint = <&apss_funnel_in4>;
+ out-ports {
+ port {
+ etm4_out: endpoint {
+ remote-endpoint = <&apss_funnel_in4>;
+ };
};
};
};
@@ -2048,9 +2039,11 @@
cpu = <&CPU5>;
- port {
- etm5_out: endpoint {
- remote-endpoint = <&apss_funnel_in5>;
+ out-ports {
+ port {
+ etm5_out: endpoint {
+ remote-endpoint = <&apss_funnel_in5>;
+ };
};
};
};
@@ -2065,9 +2058,11 @@
cpu = <&CPU6>;
- port {
- etm6_out: endpoint {
- remote-endpoint = <&apss_funnel_in6>;
+ out-ports {
+ port {
+ etm6_out: endpoint {
+ remote-endpoint = <&apss_funnel_in6>;
+ };
};
};
};
@@ -2082,9 +2077,11 @@
cpu = <&CPU7>;
- port {
- etm7_out: endpoint {
- remote-endpoint = <&apss_funnel_in7>;
+ out-ports {
+ port {
+ etm7_out: endpoint {
+ remote-endpoint = <&apss_funnel_in7>;
+ };
};
};
};
@@ -2149,7 +2146,7 @@
interrupts = <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>;
snps,dis_u2_susphy_quirk;
snps,dis_enblslpm_quirk;
- phys = <&qusb2phy>, <&usb1_ssphy>;
+ phys = <&qusb2phy>, <&usb3phy>;
phy-names = "usb2-phy", "usb3-phy";
snps,has-lpm-erratum;
snps,hird-threshold = /bits/ 8 <0x10>;
@@ -2158,33 +2155,26 @@
usb3phy: phy@c010000 {
compatible = "qcom,msm8998-qmp-usb3-phy";
- reg = <0x0c010000 0x18c>;
- status = "disabled";
- #address-cells = <1>;
- #size-cells = <1>;
- ranges;
+ reg = <0x0c010000 0x1000>;
clocks = <&gcc GCC_USB3_PHY_AUX_CLK>,
+ <&gcc GCC_USB3_CLKREF_CLK>,
<&gcc GCC_USB_PHY_CFG_AHB2PHY_CLK>,
- <&gcc GCC_USB3_CLKREF_CLK>;
- clock-names = "aux", "cfg_ahb", "ref";
+ <&gcc GCC_USB3_PHY_PIPE_CLK>;
+ clock-names = "aux",
+ "ref",
+ "cfg_ahb",
+ "pipe";
+ clock-output-names = "usb3_phy_pipe_clk_src";
+ #clock-cells = <0>;
+ #phy-cells = <0>;
resets = <&gcc GCC_USB3_PHY_BCR>,
<&gcc GCC_USB3PHY_PHY_BCR>;
- reset-names = "phy", "common";
+ reset-names = "phy",
+ "phy_phy";
- usb1_ssphy: phy@c010200 {
- reg = <0xc010200 0x128>,
- <0xc010400 0x200>,
- <0xc010c00 0x20c>,
- <0xc010600 0x128>,
- <0xc010800 0x200>;
- #phy-cells = <0>;
- #clock-cells = <0>;
- clocks = <&gcc GCC_USB3_PHY_PIPE_CLK>;
- clock-names = "pipe0";
- clock-output-names = "usb3_phy_pipe_clk_src";
- };
+ status = "disabled";
};
qusb2phy: phy@c012000 {
diff --git a/dts/upstream/src/arm64/qcom/pm7250b.dtsi b/dts/upstream/src/arm64/qcom/pm7250b.dtsi
index df0afe8..3bf7cf5 100644
--- a/dts/upstream/src/arm64/qcom/pm7250b.dtsi
+++ b/dts/upstream/src/arm64/qcom/pm7250b.dtsi
@@ -148,7 +148,7 @@
status = "disabled";
};
- pm7250b_gpios: pinctrl@c000 {
+ pm7250b_gpios: gpio@c000 {
compatible = "qcom,pm7250b-gpio", "qcom,spmi-gpio";
reg = <0xc000>;
gpio-controller;
diff --git a/dts/upstream/src/arm64/qcom/pm8550.dtsi b/dts/upstream/src/arm64/qcom/pm8550.dtsi
index db3d5c1..797a18c 100644
--- a/dts/upstream/src/arm64/qcom/pm8550.dtsi
+++ b/dts/upstream/src/arm64/qcom/pm8550.dtsi
@@ -64,9 +64,6 @@
pm8550_pwm: pwm {
compatible = "qcom,pm8550-pwm", "qcom,pm8350c-pwm";
-
- #address-cells = <1>;
- #size-cells = <0>;
#pwm-cells = <2>;
status = "disabled";
diff --git a/dts/upstream/src/arm64/qcom/pm8550ve.dtsi b/dts/upstream/src/arm64/qcom/pm8550ve.dtsi
index c47646a..4dc1f03 100644
--- a/dts/upstream/src/arm64/qcom/pm8550ve.dtsi
+++ b/dts/upstream/src/arm64/qcom/pm8550ve.dtsi
@@ -33,16 +33,16 @@
&spmi_bus {
- pm8550ve: pmic@5 {
+ pm8550ve: pmic@PMK8550VE_SID {
compatible = "qcom,pm8550", "qcom,spmi-pmic";
- reg = <0x5 SPMI_USID>;
+ reg = <PMK8550VE_SID SPMI_USID>;
#address-cells = <1>;
#size-cells = <0>;
pm8550ve_temp_alarm: temp-alarm@a00 {
compatible = "qcom,spmi-temp-alarm";
reg = <0xa00>;
- interrupts = <0x5 0xa 0x0 IRQ_TYPE_EDGE_BOTH>;
+ interrupts = <PMK8550VE_SID 0xa 0x0 IRQ_TYPE_EDGE_BOTH>;
#thermal-sensor-cells = <0>;
};
diff --git a/dts/upstream/src/arm64/qcom/pm8916.dtsi b/dts/upstream/src/arm64/qcom/pm8916.dtsi
index f4de867..4b2e8fb 100644
--- a/dts/upstream/src/arm64/qcom/pm8916.dtsi
+++ b/dts/upstream/src/arm64/qcom/pm8916.dtsi
@@ -41,6 +41,35 @@
};
};
+ pm8916_charger: charger@1000 {
+ compatible = "qcom,pm8916-lbc";
+ reg = <0x1000>, <0x1200>, <0x1300>, <0x1600>;
+ reg-names = "chgr", "bat_if", "usb", "misc";
+
+ interrupts = <0x0 0x10 0 IRQ_TYPE_EDGE_BOTH>,
+ <0x0 0x10 5 IRQ_TYPE_EDGE_BOTH>,
+ <0x0 0x10 6 IRQ_TYPE_EDGE_BOTH>,
+ <0x0 0x10 7 IRQ_TYPE_EDGE_BOTH>,
+ <0x0 0x12 0 IRQ_TYPE_EDGE_BOTH>,
+ <0x0 0x12 1 IRQ_TYPE_EDGE_BOTH>,
+ <0x0 0x13 0 IRQ_TYPE_EDGE_BOTH>,
+ <0x0 0x13 1 IRQ_TYPE_EDGE_BOTH>,
+ <0x0 0x13 2 IRQ_TYPE_EDGE_BOTH>,
+ <0x0 0x13 4 IRQ_TYPE_EDGE_BOTH>;
+ interrupt-names = "vbat_det",
+ "fast_chg",
+ "chg_fail",
+ "chg_done",
+ "bat_pres",
+ "temp_ok",
+ "coarse_det",
+ "usb_vbus",
+ "chg_gone",
+ "overtemp";
+
+ status = "disabled";
+ };
+
pm8916_usbin: usb-detect@1300 {
compatible = "qcom,pm8941-misc";
reg = <0x1300>;
@@ -91,6 +120,25 @@
};
};
+ pm8916_bms: battery@4000 {
+ compatible = "qcom,pm8916-bms-vm";
+ reg = <0x4000>;
+ interrupts = <0x0 0x40 0 IRQ_TYPE_EDGE_RISING>,
+ <0x0 0x40 1 IRQ_TYPE_EDGE_RISING>,
+ <0x0 0x40 2 IRQ_TYPE_EDGE_RISING>,
+ <0x0 0x40 3 IRQ_TYPE_EDGE_RISING>,
+ <0x0 0x40 4 IRQ_TYPE_EDGE_RISING>,
+ <0x0 0x40 5 IRQ_TYPE_EDGE_RISING>;
+ interrupt-names = "cv_leave",
+ "cv_enter",
+ "ocv_good",
+ "ocv_thr",
+ "fifo",
+ "state_chg";
+
+ status = "disabled";
+ };
+
rtc@6000 {
compatible = "qcom,pm8941-rtc";
reg = <0x6000>, <0x6100>;
diff --git a/dts/upstream/src/arm64/qcom/pmk8350.dtsi b/dts/upstream/src/arm64/qcom/pmk8350.dtsi
index 1eb7401..f0ed154 100644
--- a/dts/upstream/src/arm64/qcom/pmk8350.dtsi
+++ b/dts/upstream/src/arm64/qcom/pmk8350.dtsi
@@ -22,7 +22,7 @@
mode-bootloader = <0x02>;
};
};
-
+
&spmi_bus {
pmk8350: pmic@PMK8350_SID {
compatible = "qcom,pmk8350", "qcom,spmi-pmic";
diff --git a/dts/upstream/src/arm64/qcom/qcm2290.dtsi b/dts/upstream/src/arm64/qcom/qcm2290.dtsi
index d46e591..0911fb0 100644
--- a/dts/upstream/src/arm64/qcom/qcm2290.dtsi
+++ b/dts/upstream/src/arm64/qcom/qcm2290.dtsi
@@ -5,12 +5,15 @@
* Based on sm6115.dtsi and previous efforts by Shawn Guo & Loic Poulain.
*/
+#include <dt-bindings/clock/qcom,dispcc-qcm2290.h>
#include <dt-bindings/clock/qcom,gcc-qcm2290.h>
#include <dt-bindings/clock/qcom,rpmcc.h>
#include <dt-bindings/dma/qcom-gpi.h>
#include <dt-bindings/firmware/qcom,scm.h>
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
+#include <dt-bindings/interconnect/qcom,qcm2290.h>
+#include <dt-bindings/interconnect/qcom,rpm-icc.h>
#include <dt-bindings/power/qcom-rpmpd.h>
/ {
@@ -150,6 +153,8 @@
clocks = <&rpmcc RPM_SMD_CE1_CLK>;
clock-names = "core";
#reset-cells = <1>;
+ interconnects = <&system_noc MASTER_CRYPTO_CORE0 RPM_ALWAYS_TAG
+ &bimc SLAVE_EBI1 RPM_ALWAYS_TAG>;
};
};
@@ -194,6 +199,7 @@
CLUSTER_PD: power-domain-cpu-cluster {
#power-domain-cells = <0>;
+ power-domains = <&mpm>;
domain-idle-states = <&CLUSTER_SLEEP>;
};
};
@@ -261,6 +267,24 @@
};
};
};
+
+ mpm: interrupt-controller {
+ compatible = "qcom,mpm";
+ qcom,rpm-msg-ram = <&apss_mpm>;
+ interrupts = <GIC_SPI 197 IRQ_TYPE_EDGE_RISING>;
+ mboxes = <&apcs_glb 1>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ #power-domain-cells = <0>;
+ interrupt-parent = <&intc>;
+ qcom,mpm-pin-count = <96>;
+ qcom,mpm-pin-map = <2 275>, /* TSENS0 uplow */
+ <5 296>, /* Soundwire master_irq */
+ <12 422>, /* DWC3 ss_phy_irq */
+ <24 79>, /* Soundwire wake_irq */
+ <86 183>, /* MPM wake, SPMI */
+ <90 260>; /* QUSB2_PHY DP+DM */
+ };
};
reserved_memory: reserved-memory {
@@ -424,6 +448,7 @@
interrupts = <GIC_SPI 227 IRQ_TYPE_LEVEL_HIGH>;
gpio-controller;
gpio-ranges = <&tlmm 0 0 127>;
+ wakeup-parent = <&mpm>;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
@@ -668,6 +693,33 @@
status = "disabled";
};
+ system_noc: interconnect@1880000 {
+ compatible = "qcom,qcm2290-snoc";
+ reg = <0x0 0x01880000 0x0 0x60200>;
+ #interconnect-cells = <2>;
+
+ qup_virt: interconnect-qup {
+ compatible = "qcom,qcm2290-qup-virt";
+ #interconnect-cells = <2>;
+ };
+
+ mmnrt_virt: interconnect-mmnrt {
+ compatible = "qcom,qcm2290-mmnrt-virt";
+ #interconnect-cells = <2>;
+ };
+
+ mmrt_virt: interconnect-mmrt {
+ compatible = "qcom,qcm2290-mmrt-virt";
+ #interconnect-cells = <2>;
+ };
+ };
+
+ config_noc: interconnect@1900000 {
+ compatible = "qcom,qcm2290-cnoc";
+ reg = <0x0 0x01900000 0x0 0x8200>;
+ #interconnect-cells = <2>;
+ };
+
qfprom@1b44000 {
compatible = "qcom,qcm2290-qfprom", "qcom,qfprom";
reg = <0x0 0x01b44000 0x0 0x3000>;
@@ -680,6 +732,60 @@
};
};
+ pmu@1b8e300 {
+ compatible = "qcom,qcm2290-cpu-bwmon", "qcom,sdm845-bwmon";
+ reg = <0x0 0x01b8e300 0x0 0x600>;
+ interrupts = <GIC_SPI 421 IRQ_TYPE_LEVEL_HIGH>;
+
+ operating-points-v2 = <&cpu_bwmon_opp_table>;
+ interconnects = <&bimc MASTER_APPSS_PROC RPM_ACTIVE_TAG
+ &bimc SLAVE_EBI1 RPM_ACTIVE_TAG>;
+
+ cpu_bwmon_opp_table: opp-table {
+ compatible = "operating-points-v2";
+
+ opp-0 {
+ opp-peak-kBps = <(200 * 4 * 1000)>;
+ };
+
+ opp-1 {
+ opp-peak-kBps = <(300 * 4 * 1000)>;
+ };
+
+ opp-2 {
+ opp-peak-kBps = <(451 * 4 * 1000)>;
+ };
+
+ opp-3 {
+ opp-peak-kBps = <(547 * 4 * 1000)>;
+ };
+
+ opp-4 {
+ opp-peak-kBps = <(681 * 4 * 1000)>;
+ };
+
+ opp-5 {
+ opp-peak-kBps = <(768 * 4 * 1000)>;
+ };
+
+ opp-6 {
+ opp-peak-kBps = <(1017 * 4 * 1000)>;
+ };
+
+ opp-7 {
+ opp-peak-kBps = <(1353 * 4 * 1000)>;
+ };
+
+ opp-8 {
+ opp-peak-kBps = <(1555 * 4 * 1000)>;
+ };
+
+ opp-9 {
+ opp-peak-kBps = <(1804 * 4 * 1000)>;
+ };
+ };
+ };
+
spmi_bus: spmi@1c40000 {
compatible = "qcom,spmi-pmic-arb";
reg = <0x0 0x01c40000 0x0 0x1100>,
@@ -692,7 +798,7 @@
"obsrvr",
"intr",
"cnfg";
- interrupts = <GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH>;
+ interrupts-extended = <&mpm 86 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "periph_irq";
qcom,ee = <0>;
qcom,channel = <0>;
@@ -707,8 +813,8 @@
reg = <0x0 0x04411000 0x0 0x1ff>,
<0x0 0x04410000 0x0 0x8>;
#qcom,sensors = <10>;
- interrupts = <GIC_SPI 275 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>;
+ interrupts-extended = <&mpm 2 IRQ_TYPE_LEVEL_HIGH>,
+ <&intc GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "uplow", "critical";
#thermal-sensor-cells = <1>;
};
@@ -720,9 +826,22 @@
clock-names = "core";
};
+ bimc: interconnect@4480000 {
+ compatible = "qcom,qcm2290-bimc";
+ reg = <0x0 0x04480000 0x0 0x80000>;
+ #interconnect-cells = <2>;
+ };
+
rpm_msg_ram: sram@45f0000 {
- compatible = "qcom,rpm-msg-ram";
+ compatible = "qcom,rpm-msg-ram", "mmio-sram";
reg = <0x0 0x045f0000 0x0 0x7000>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0 0x0 0x045f0000 0x7000>;
+
+ apss_mpm: sram@1b8 {
+ reg = <0x1b8 0x48>;
+ };
};
sram@4690000 {
@@ -755,13 +874,45 @@
resets = <&gcc GCC_SDCC1_BCR>;
power-domains = <&rpmpd QCM2290_VDDCX>;
+ operating-points-v2 = <&sdhc1_opp_table>;
iommus = <&apps_smmu 0xc0 0x0>;
+ interconnects = <&system_noc MASTER_SDCC_1 RPM_ALWAYS_TAG
+ &bimc SLAVE_EBI1 RPM_ALWAYS_TAG>,
+ <&bimc MASTER_APPSS_PROC RPM_ALWAYS_TAG
+ &config_noc SLAVE_SDCC_1 RPM_ALWAYS_TAG>;
+ interconnect-names = "sdhc-ddr",
+ "cpu-sdhc";
qcom,dll-config = <0x000f642c>;
qcom,ddr-config = <0x80040868>;
bus-width = <8>;
status = "disabled";
+
+ sdhc1_opp_table: opp-table {
+ compatible = "operating-points-v2";
+
+ opp-100000000 {
+ opp-hz = /bits/ 64 <100000000>;
+ required-opps = <&rpmpd_opp_low_svs>;
+ opp-peak-kBps = <250000 133320>;
+ opp-avg-kBps = <102400 65000>;
+ };
+
+ opp-192000000 {
+ opp-hz = /bits/ 64 <192000000>;
+ required-opps = <&rpmpd_opp_low_svs>;
+ opp-peak-kBps = <800000 300000>;
+ opp-avg-kBps = <204800 200000>;
+ };
+
+ opp-384000000 {
+ opp-hz = /bits/ 64 <384000000>;
+ required-opps = <&rpmpd_opp_svs_plus>;
+ opp-peak-kBps = <800000 300000>;
+ opp-avg-kBps = <204800 200000>;
+ };
+ };
};
sdhc_2: mmc@4784000 {
@@ -785,6 +936,12 @@
power-domains = <&rpmpd QCM2290_VDDCX>;
operating-points-v2 = <&sdhc2_opp_table>;
iommus = <&apps_smmu 0xa0 0x0>;
+ interconnects = <&system_noc MASTER_SDCC_2 RPM_ALWAYS_TAG
+ &bimc SLAVE_EBI1 RPM_ALWAYS_TAG>,
+ <&bimc MASTER_APPSS_PROC RPM_ALWAYS_TAG
+ &config_noc SLAVE_SDCC_2 RPM_ALWAYS_TAG>;
+ interconnect-names = "sdhc-ddr",
+ "cpu-sdhc";
qcom,dll-config = <0x0007642c>;
qcom,ddr-config = <0x80040868>;
@@ -798,11 +955,15 @@
opp-100000000 {
opp-hz = /bits/ 64 <100000000>;
required-opps = <&rpmpd_opp_low_svs>;
+ opp-peak-kBps = <250000 133320>;
+ opp-avg-kBps = <261438 150000>;
};
opp-202000000 {
opp-hz = /bits/ 64 <202000000>;
required-opps = <&rpmpd_opp_svs_plus>;
+ opp-peak-kBps = <800000 300000>;
+ opp-avg-kBps = <261438 300000>;
};
};
};
@@ -850,6 +1011,15 @@
dmas = <&gpi_dma0 0 0 QCOM_GPI_I2C>,
<&gpi_dma0 1 0 QCOM_GPI_I2C>;
dma-names = "tx", "rx";
+ interconnects = <&qup_virt MASTER_QUP_CORE_0 RPM_ALWAYS_TAG
+ &qup_virt SLAVE_QUP_CORE_0 RPM_ALWAYS_TAG>,
+ <&bimc MASTER_APPSS_PROC RPM_ALWAYS_TAG
+ &config_noc SLAVE_QUP_0 RPM_ALWAYS_TAG>,
+ <&system_noc MASTER_QUP_0 RPM_ALWAYS_TAG
+ &bimc SLAVE_EBI1 RPM_ALWAYS_TAG>;
+ interconnect-names = "qup-core",
+ "qup-config",
+ "qup-memory";
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
@@ -866,6 +1036,12 @@
dmas = <&gpi_dma0 0 0 QCOM_GPI_SPI>,
<&gpi_dma0 1 0 QCOM_GPI_SPI>;
dma-names = "tx", "rx";
+ interconnects = <&qup_virt MASTER_QUP_CORE_0 RPM_ALWAYS_TAG
+ &qup_virt SLAVE_QUP_CORE_0 RPM_ALWAYS_TAG>,
+ <&bimc MASTER_APPSS_PROC RPM_ALWAYS_TAG
+ &config_noc MASTER_APPSS_PROC RPM_ALWAYS_TAG>;
+ interconnect-names = "qup-core",
+ "qup-config";
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
@@ -879,6 +1055,12 @@
clock-names = "se";
pinctrl-0 = <&qup_uart0_default>;
pinctrl-names = "default";
+ interconnects = <&qup_virt MASTER_QUP_CORE_0 RPM_ALWAYS_TAG
+ &qup_virt SLAVE_QUP_CORE_0 RPM_ALWAYS_TAG>,
+ <&bimc MASTER_APPSS_PROC RPM_ALWAYS_TAG
+ &config_noc MASTER_APPSS_PROC RPM_ALWAYS_TAG>;
+ interconnect-names = "qup-core",
+ "qup-config";
status = "disabled";
};
@@ -893,6 +1075,15 @@
dmas = <&gpi_dma0 0 1 QCOM_GPI_I2C>,
<&gpi_dma0 1 1 QCOM_GPI_I2C>;
dma-names = "tx", "rx";
+ interconnects = <&qup_virt MASTER_QUP_CORE_0 RPM_ALWAYS_TAG
+ &qup_virt SLAVE_QUP_CORE_0 RPM_ALWAYS_TAG>,
+ <&bimc MASTER_APPSS_PROC RPM_ALWAYS_TAG
+ &config_noc SLAVE_QUP_0 RPM_ALWAYS_TAG>,
+ <&system_noc MASTER_QUP_0 RPM_ALWAYS_TAG
+ &bimc SLAVE_EBI1 RPM_ALWAYS_TAG>;
+ interconnect-names = "qup-core",
+ "qup-config",
+ "qup-memory";
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
@@ -909,6 +1100,12 @@
dmas = <&gpi_dma0 0 1 QCOM_GPI_SPI>,
<&gpi_dma0 1 1 QCOM_GPI_SPI>;
dma-names = "tx", "rx";
+ interconnects = <&qup_virt MASTER_QUP_CORE_0 RPM_ALWAYS_TAG
+ &qup_virt SLAVE_QUP_CORE_0 RPM_ALWAYS_TAG>,
+ <&bimc MASTER_APPSS_PROC RPM_ALWAYS_TAG
+ &config_noc MASTER_APPSS_PROC RPM_ALWAYS_TAG>;
+ interconnect-names = "qup-core",
+ "qup-config";
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
@@ -925,6 +1122,15 @@
dmas = <&gpi_dma0 0 2 QCOM_GPI_I2C>,
<&gpi_dma0 1 2 QCOM_GPI_I2C>;
dma-names = "tx", "rx";
+ interconnects = <&qup_virt MASTER_QUP_CORE_0 RPM_ALWAYS_TAG
+ &qup_virt SLAVE_QUP_CORE_0 RPM_ALWAYS_TAG>,
+ <&bimc MASTER_APPSS_PROC RPM_ALWAYS_TAG
+ &config_noc SLAVE_QUP_0 RPM_ALWAYS_TAG>,
+ <&system_noc MASTER_QUP_0 RPM_ALWAYS_TAG
+ &bimc SLAVE_EBI1 RPM_ALWAYS_TAG>;
+ interconnect-names = "qup-core",
+ "qup-config",
+ "qup-memory";
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
@@ -941,6 +1147,12 @@
dmas = <&gpi_dma0 0 2 QCOM_GPI_SPI>,
<&gpi_dma0 1 2 QCOM_GPI_SPI>;
dma-names = "tx", "rx";
+ interconnects = <&qup_virt MASTER_QUP_CORE_0 RPM_ALWAYS_TAG
+ &qup_virt SLAVE_QUP_CORE_0 RPM_ALWAYS_TAG>,
+ <&bimc MASTER_APPSS_PROC RPM_ALWAYS_TAG
+ &config_noc MASTER_APPSS_PROC RPM_ALWAYS_TAG>;
+ interconnect-names = "qup-core",
+ "qup-config";
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
@@ -957,6 +1169,15 @@
dmas = <&gpi_dma0 0 3 QCOM_GPI_I2C>,
<&gpi_dma0 1 3 QCOM_GPI_I2C>;
dma-names = "tx", "rx";
+ interconnects = <&qup_virt MASTER_QUP_CORE_0 RPM_ALWAYS_TAG
+ &qup_virt SLAVE_QUP_CORE_0 RPM_ALWAYS_TAG>,
+ <&bimc MASTER_APPSS_PROC RPM_ALWAYS_TAG
+ &config_noc SLAVE_QUP_0 RPM_ALWAYS_TAG>,
+ <&system_noc MASTER_QUP_0 RPM_ALWAYS_TAG
+ &bimc SLAVE_EBI1 RPM_ALWAYS_TAG>;
+ interconnect-names = "qup-core",
+ "qup-config",
+ "qup-memory";
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
@@ -973,6 +1194,12 @@
dmas = <&gpi_dma0 0 3 QCOM_GPI_SPI>,
<&gpi_dma0 1 3 QCOM_GPI_SPI>;
dma-names = "tx", "rx";
+ interconnects = <&qup_virt MASTER_QUP_CORE_0 RPM_ALWAYS_TAG
+ &qup_virt SLAVE_QUP_CORE_0 RPM_ALWAYS_TAG>,
+ <&bimc MASTER_APPSS_PROC RPM_ALWAYS_TAG
+ &config_noc MASTER_APPSS_PROC RPM_ALWAYS_TAG>;
+ interconnect-names = "qup-core",
+ "qup-config";
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
@@ -989,6 +1216,15 @@
dmas = <&gpi_dma0 0 4 QCOM_GPI_I2C>,
<&gpi_dma0 1 4 QCOM_GPI_I2C>;
dma-names = "tx", "rx";
+ interconnects = <&qup_virt MASTER_QUP_CORE_0 RPM_ALWAYS_TAG
+ &qup_virt SLAVE_QUP_CORE_0 RPM_ALWAYS_TAG>,
+ <&bimc MASTER_APPSS_PROC RPM_ALWAYS_TAG
+ &config_noc SLAVE_QUP_0 RPM_ALWAYS_TAG>,
+ <&system_noc MASTER_QUP_0 RPM_ALWAYS_TAG
+ &bimc SLAVE_EBI1 RPM_ALWAYS_TAG>;
+ interconnect-names = "qup-core",
+ "qup-config",
+ "qup-memory";
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
@@ -1005,6 +1241,12 @@
dmas = <&gpi_dma0 0 4 QCOM_GPI_SPI>,
<&gpi_dma0 1 4 QCOM_GPI_SPI>;
dma-names = "tx", "rx";
+ interconnects = <&qup_virt MASTER_QUP_CORE_0 RPM_ALWAYS_TAG
+ &qup_virt SLAVE_QUP_CORE_0 RPM_ALWAYS_TAG>,
+ <&bimc MASTER_APPSS_PROC RPM_ALWAYS_TAG
+ &config_noc MASTER_APPSS_PROC RPM_ALWAYS_TAG>;
+ interconnect-names = "qup-core",
+ "qup-config";
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
@@ -1018,6 +1260,12 @@
clock-names = "se";
pinctrl-0 = <&qup_uart4_default>;
pinctrl-names = "default";
+ interconnects = <&qup_virt MASTER_QUP_CORE_0 RPM_ALWAYS_TAG
+ &qup_virt SLAVE_QUP_CORE_0 RPM_ALWAYS_TAG>,
+ <&bimc MASTER_APPSS_PROC RPM_ALWAYS_TAG
+ &config_noc MASTER_APPSS_PROC RPM_ALWAYS_TAG>;
+ interconnect-names = "qup-core",
+ "qup-config";
status = "disabled";
};
@@ -1032,6 +1280,15 @@
dmas = <&gpi_dma0 0 5 QCOM_GPI_I2C>,
<&gpi_dma0 1 5 QCOM_GPI_I2C>;
dma-names = "tx", "rx";
+ interconnects = <&qup_virt MASTER_QUP_CORE_0 RPM_ALWAYS_TAG
+ &qup_virt SLAVE_QUP_CORE_0 RPM_ALWAYS_TAG>,
+ <&bimc MASTER_APPSS_PROC RPM_ALWAYS_TAG
+ &config_noc SLAVE_QUP_0 RPM_ALWAYS_TAG>,
+ <&system_noc MASTER_QUP_0 RPM_ALWAYS_TAG
+ &bimc SLAVE_EBI1 RPM_ALWAYS_TAG>;
+ interconnect-names = "qup-core",
+ "qup-config",
+ "qup-memory";
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
@@ -1048,6 +1305,12 @@
dmas = <&gpi_dma0 0 5 QCOM_GPI_SPI>,
<&gpi_dma0 1 5 QCOM_GPI_SPI>;
dma-names = "tx", "rx";
+ interconnects = <&qup_virt MASTER_QUP_CORE_0 RPM_ALWAYS_TAG
+ &qup_virt SLAVE_QUP_CORE_0 RPM_ALWAYS_TAG>,
+ <&bimc MASTER_APPSS_PROC RPM_ALWAYS_TAG
+ &config_noc MASTER_APPSS_PROC RPM_ALWAYS_TAG>;
+ interconnect-names = "qup-core",
+ "qup-config";
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
@@ -1057,9 +1320,10 @@
usb: usb@4ef8800 {
compatible = "qcom,qcm2290-dwc3", "qcom,dwc3";
reg = <0x0 0x04ef8800 0x0 0x400>;
- interrupts = <GIC_SPI 260 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 422 IRQ_TYPE_LEVEL_HIGH>;
- interrupt-names = "hs_phy_irq", "ss_phy_irq";
+ interrupts-extended = <&intc GIC_SPI 260 IRQ_TYPE_LEVEL_HIGH>,
+ <&mpm 12 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "hs_phy_irq",
+ "ss_phy_irq";
clocks = <&gcc GCC_CFG_NOC_USB3_PRIM_AXI_CLK>,
<&gcc GCC_USB30_PRIM_MASTER_CLK>,
@@ -1080,6 +1344,13 @@
resets = <&gcc GCC_USB30_PRIM_BCR>;
power-domains = <&gcc GCC_USB30_PRIM_GDSC>;
+ /* TODO: USB<->IPA path */
+ interconnects = <&system_noc MASTER_USB3_0 RPM_ALWAYS_TAG
+ &bimc SLAVE_EBI1 RPM_ALWAYS_TAG>,
+ <&bimc MASTER_APPSS_PROC RPM_ALWAYS_TAG
+ &config_noc SLAVE_USB3 RPM_ALWAYS_TAG>;
+ interconnect-names = "usb-ddr",
+ "apps-usb";
wakeup-source;
#address-cells = <2>;
@@ -1103,6 +1374,225 @@
maximum-speed = "super-speed";
dr_mode = "otg";
};
+ };
+
+ mdss: display-subsystem@5e00000 {
+ compatible = "qcom,qcm2290-mdss";
+ reg = <0x0 0x05e00000 0x0 0x1000>;
+ reg-names = "mdss";
+ interrupts = <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-controller;
+ #interrupt-cells = <1>;
+
+ clocks = <&gcc GCC_DISP_AHB_CLK>,
+ <&gcc GCC_DISP_HF_AXI_CLK>,
+ <&dispcc DISP_CC_MDSS_MDP_CLK>;
+ clock-names = "iface",
+ "bus",
+ "core";
+
+ resets = <&dispcc DISP_CC_MDSS_CORE_BCR>;
+
+ power-domains = <&dispcc MDSS_GDSC>;
+
+ iommus = <&apps_smmu 0x420 0x2>,
+ <&apps_smmu 0x421 0x0>;
+ interconnects = <&mmrt_virt MASTER_MDP0 RPM_ALWAYS_TAG
+ &bimc SLAVE_EBI1 RPM_ALWAYS_TAG>,
+ <&bimc MASTER_APPSS_PROC RPM_ALWAYS_TAG
+ &config_noc SLAVE_DISPLAY_CFG RPM_ALWAYS_TAG>;
+ interconnect-names = "mdp0-mem",
+ "cpu-cfg";
+
+ #address-cells = <2>;
+ #size-cells = <2>;
+ ranges;
+
+ status = "disabled";
+
+ mdp: display-controller@5e01000 {
+ compatible = "qcom,qcm2290-dpu";
+ reg = <0x0 0x05e01000 0x0 0x8f000>,
+ <0x0 0x05eb0000 0x0 0x2008>;
+ reg-names = "mdp",
+ "vbif";
+
+ interrupt-parent = <&mdss>;
+ interrupts = <0>;
+
+ clocks = <&gcc GCC_DISP_HF_AXI_CLK>,
+ <&dispcc DISP_CC_MDSS_AHB_CLK>,
+ <&dispcc DISP_CC_MDSS_MDP_CLK>,
+ <&dispcc DISP_CC_MDSS_MDP_LUT_CLK>,
+ <&dispcc DISP_CC_MDSS_VSYNC_CLK>;
+ clock-names = "bus",
+ "iface",
+ "core",
+ "lut",
+ "vsync";
+
+ operating-points-v2 = <&mdp_opp_table>;
+ power-domains = <&rpmpd QCM2290_VDDCX>;
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+ dpu_intf1_out: endpoint {
+ remote-endpoint = <&mdss_dsi0_in>;
+ };
+ };
+ };
+
+ mdp_opp_table: opp-table {
+ compatible = "operating-points-v2";
+
+ opp-19200000 {
+ opp-hz = /bits/ 64 <19200000>;
+ required-opps = <&rpmpd_opp_min_svs>;
+ };
+
+ opp-192000000 {
+ opp-hz = /bits/ 64 <192000000>;
+ required-opps = <&rpmpd_opp_low_svs>;
+ };
+
+ opp-256000000 {
+ opp-hz = /bits/ 64 <256000000>;
+ required-opps = <&rpmpd_opp_svs>;
+ };
+
+ opp-307200000 {
+ opp-hz = /bits/ 64 <307200000>;
+ required-opps = <&rpmpd_opp_svs_plus>;
+ };
+
+ opp-384000000 {
+ opp-hz = /bits/ 64 <384000000>;
+ required-opps = <&rpmpd_opp_nom>;
+ };
+ };
+ };
+
+ mdss_dsi0: dsi@5e94000 {
+ compatible = "qcom,qcm2290-dsi-ctrl", "qcom,mdss-dsi-ctrl";
+ reg = <0x0 0x05e94000 0x0 0x400>;
+ reg-names = "dsi_ctrl";
+
+ interrupt-parent = <&mdss>;
+ interrupts = <4>;
+
+ clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK>,
+ <&dispcc DISP_CC_MDSS_BYTE0_INTF_CLK>,
+ <&dispcc DISP_CC_MDSS_PCLK0_CLK>,
+ <&dispcc DISP_CC_MDSS_ESC0_CLK>,
+ <&dispcc DISP_CC_MDSS_AHB_CLK>,
+ <&gcc GCC_DISP_HF_AXI_CLK>;
+ clock-names = "byte",
+ "byte_intf",
+ "pixel",
+ "core",
+ "iface",
+ "bus";
+
+ assigned-clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK_SRC>,
+ <&dispcc DISP_CC_MDSS_PCLK0_CLK_SRC>;
+ assigned-clock-parents = <&mdss_dsi0_phy 0>,
+ <&mdss_dsi0_phy 1>;
+
+ operating-points-v2 = <&dsi_opp_table>;
+ power-domains = <&rpmpd QCM2290_VDDCX>;
+ phys = <&mdss_dsi0_phy>;
+
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ status = "disabled";
+
+ dsi_opp_table: opp-table {
+ compatible = "operating-points-v2";
+
+ opp-19200000 {
+ opp-hz = /bits/ 64 <19200000>;
+ required-opps = <&rpmpd_opp_min_svs>;
+ };
+
+ opp-164000000 {
+ opp-hz = /bits/ 64 <164000000>;
+ required-opps = <&rpmpd_opp_low_svs>;
+ };
+
+ opp-187500000 {
+ opp-hz = /bits/ 64 <187500000>;
+ required-opps = <&rpmpd_opp_svs>;
+ };
+ };
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+
+ mdss_dsi0_in: endpoint {
+ remote-endpoint = <&dpu_intf1_out>;
+ };
+ };
+
+ port@1 {
+ reg = <1>;
+
+ mdss_dsi0_out: endpoint {
+ };
+ };
+ };
+ };
+
+ mdss_dsi0_phy: phy@5e94400 {
+ compatible = "qcom,dsi-phy-14nm-2290";
+ reg = <0x0 0x05e94400 0x0 0x100>,
+ <0x0 0x05e94500 0x0 0x300>,
+ <0x0 0x05e94800 0x0 0x188>;
+ reg-names = "dsi_phy",
+ "dsi_phy_lane",
+ "dsi_pll";
+
+ clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>,
+ <&rpmcc RPM_SMD_XO_CLK_SRC>;
+ clock-names = "iface",
+ "ref";
+
+ power-domains = <&rpmpd QCM2290_VDDMX>;
+ required-opps = <&rpmpd_opp_nom>;
+
+ #clock-cells = <1>;
+ #phy-cells = <0>;
+
+ status = "disabled";
+ };
+ };
+
+ dispcc: clock-controller@5f00000 {
+ compatible = "qcom,qcm2290-dispcc";
+ reg = <0x0 0x05f00000 0x0 0x20000>;
+ clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>,
+ <&rpmcc RPM_SMD_XO_A_CLK_SRC>,
+ <&gcc GCC_DISP_GPLL0_CLK_SRC>,
+ <&gcc GCC_DISP_GPLL0_DIV_CLK_SRC>,
+ <&mdss_dsi0_phy 0>,
+ <&mdss_dsi0_phy 1>;
+ clock-names = "bi_tcxo",
+ "bi_tcxo_ao",
+ "gcc_disp_gpll0_clk_src",
+ "gcc_disp_gpll0_div_clk_src",
+ "dsi0_phy_pll_out_byteclk",
+ "dsi0_phy_pll_out_dsiclk";
+ #power-domain-cells = <1>;
+ #clock-cells = <1>;
+ #reset-cells = <1>;
};
remoteproc_mpss: remoteproc@6080000 {
diff --git a/dts/upstream/src/arm64/qcom/qcm6490-fairphone-fp5.dts b/dts/upstream/src/arm64/qcom/qcm6490-fairphone-fp5.dts
index 2de0b8c..176898c 100644
--- a/dts/upstream/src/arm64/qcom/qcm6490-fairphone-fp5.dts
+++ b/dts/upstream/src/arm64/qcom/qcm6490-fairphone-fp5.dts
@@ -9,6 +9,8 @@
#define PM7250B_SID 8
#define PM7250B_SID1 9
+#include <dt-bindings/iio/qcom,spmi-adc7-pm7325.h>
+#include <dt-bindings/iio/qcom,spmi-adc7-pmk8350.h>
#include <dt-bindings/leds/common.h>
#include <dt-bindings/pinctrl/qcom,pmic-gpio.h>
#include <dt-bindings/regulator/qcom,rpmh-regulator.h>
@@ -75,26 +77,11 @@
no-map;
};
- adsp_mem: adsp@86700000 {
- reg = <0x0 0x86700000 0x0 0x2800000>;
- no-map;
- };
-
cdsp_mem: cdsp@88f00000 {
reg = <0x0 0x88f00000 0x0 0x1e00000>;
no-map;
};
- mpss_mem: mpss@8b800000 {
- reg = <0x0 0x8b800000 0x0 0xf600000>;
- no-map;
- };
-
- wpss_mem: wpss@9ae00000 {
- reg = <0x0 0x9ae00000 0x0 0x1900000>;
- no-map;
- };
-
rmtfs_mem: memory@f8500000 {
compatible = "qcom,rmtfs-mem";
reg = <0x0 0xf8500000 0x0 0x600000>;
@@ -134,6 +121,106 @@
enable-active-high;
vin-supply = <&vreg_bob>;
};
+
+ thermal-zones {
+ camera-thermal {
+ polling-delay-passive = <0>;
+ polling-delay = <0>;
+ thermal-sensors = <&pmk8350_adc_tm 2>;
+
+ trips {
+ active-config0 {
+ temperature = <125000>;
+ hysteresis = <1000>;
+ type = "passive";
+ };
+ };
+ };
+
+ chg-skin-thermal {
+ polling-delay-passive = <0>;
+ polling-delay = <0>;
+ thermal-sensors = <&pm7250b_adc_tm 0>;
+
+ trips {
+ active-config0 {
+ temperature = <125000>;
+ hysteresis = <1000>;
+ type = "passive";
+ };
+ };
+ };
+
+ conn-thermal {
+ polling-delay-passive = <0>;
+ polling-delay = <0>;
+ thermal-sensors = <&pm7250b_adc_tm 1>;
+
+ trips {
+ active-config0 {
+ temperature = <125000>;
+ hysteresis = <1000>;
+ type = "passive";
+ };
+ };
+ };
+
+ quiet-thermal {
+ polling-delay-passive = <0>;
+ polling-delay = <0>;
+ thermal-sensors = <&pmk8350_adc_tm 1>;
+
+ trips {
+ active-config0 {
+ temperature = <125000>;
+ hysteresis = <1000>;
+ type = "passive";
+ };
+ };
+ };
+
+ rear-cam-thermal {
+ polling-delay-passive = <0>;
+ polling-delay = <0>;
+ thermal-sensors = <&pmk8350_adc_tm 4>;
+
+ trips {
+ active-config0 {
+ temperature = <125000>;
+ hysteresis = <1000>;
+ type = "passive";
+ };
+ };
+ };
+
+ sdm-skin-thermal {
+ polling-delay-passive = <0>;
+ polling-delay = <0>;
+ thermal-sensors = <&pmk8350_adc_tm 3>;
+
+ trips {
+ active-config0 {
+ temperature = <125000>;
+ hysteresis = <1000>;
+ type = "passive";
+ };
+ };
+ };
+
+ xo-thermal {
+ polling-delay-passive = <0>;
+ polling-delay = <0>;
+ thermal-sensors = <&pmk8350_adc_tm 0>;
+
+ trips {
+ active-config0 {
+ temperature = <125000>;
+ hysteresis = <1000>;
+ type = "passive";
+ };
+ };
+ };
+ };
};
&apps_rsc {
@@ -182,8 +269,9 @@
};
vreg_l7b: ldo7 {
- regulator-min-microvolt = <2400000>;
- regulator-max-microvolt = <3544000>;
+ /* Constrained for UFS VCC, at least until UFS driver scales voltage */
+ regulator-min-microvolt = <2952000>;
+ regulator-max-microvolt = <2952000>;
regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
};
@@ -423,6 +511,42 @@
memory-region = <&ipa_fw_mem>;
firmware-name = "qcom/qcm6490/fairphone5/ipa_fws.mdt";
status = "okay";
+};
+
+&pm7250b_adc {
+ channel@4d {
+ reg = <ADC5_AMUX_THM1_100K_PU>;
+ qcom,ratiometric;
+ qcom,hw-settle-time = <200>;
+ qcom,pre-scaling = <1 1>;
+ label = "charger_skin_therm";
+ };
+
+ channel@4f {
+ reg = <ADC5_AMUX_THM3_100K_PU>;
+ qcom,ratiometric;
+ qcom,hw-settle-time = <200>;
+ qcom,pre-scaling = <1 1>;
+ label = "conn_therm";
+ };
+};
+
+&pm7250b_adc_tm {
+ status = "okay";
+
+ charger-skin-therm@0 {
+ reg = <0>;
+ io-channels = <&pm7250b_adc ADC5_AMUX_THM1_100K_PU>;
+ qcom,ratiometric;
+ qcom,hw-settle-time-us = <200>;
+ };
+
+ conn-therm@1 {
+ reg = <1>;
+ io-channels = <&pm7250b_adc ADC5_AMUX_THM3_100K_PU>;
+ qcom,ratiometric;
+ qcom,hw-settle-time-us = <200>;
+ };
};
&pm7325_gpios {
@@ -448,8 +572,91 @@
};
};
+&pmk8350_adc_tm {
+ status = "okay";
+
+ xo-therm@0 {
+ reg = <0>;
+ io-channels = <&pmk8350_vadc PMK8350_ADC7_AMUX_THM1_100K_PU>;
+ qcom,ratiometric;
+ qcom,hw-settle-time-us = <200>;
+ };
+
+ quiet-therm@1 {
+ reg = <1>;
+ io-channels = <&pmk8350_vadc PM7325_ADC7_AMUX_THM1_100K_PU>;
+ qcom,ratiometric;
+ qcom,hw-settle-time-us = <200>;
+ };
+
+ cam-flash-therm@2 {
+ reg = <2>;
+ io-channels = <&pmk8350_vadc PM7325_ADC7_AMUX_THM2_100K_PU>;
+ qcom,ratiometric;
+ qcom,hw-settle-time-us = <200>;
+ };
+
+ sdm-skin-therm@3 {
+ reg = <3>;
+ io-channels = <&pmk8350_vadc PM7325_ADC7_AMUX_THM3_100K_PU>;
+ qcom,ratiometric;
+ qcom,hw-settle-time-us = <200>;
+ };
+
+ wide-rfc-therm@4 {
+ reg = <4>;
+ io-channels = <&pmk8350_vadc PM7325_ADC7_AMUX_THM4_100K_PU>;
+ qcom,ratiometric;
+ qcom,hw-settle-time-us = <200>;
+ };
+};
+
&pmk8350_rtc {
status = "okay";
+};
+
+&pmk8350_vadc {
+ status = "okay";
+
+ channel@44 {
+ reg = <PMK8350_ADC7_AMUX_THM1_100K_PU>;
+ qcom,ratiometric;
+ qcom,hw-settle-time = <200>;
+ qcom,pre-scaling = <1 1>;
+ label = "pmk8350_xo_therm";
+ };
+
+ channel@144 {
+ reg = <PM7325_ADC7_AMUX_THM1_100K_PU>;
+ qcom,ratiometric;
+ qcom,hw-settle-time = <200>;
+ qcom,pre-scaling = <1 1>;
+ label = "pm7325_quiet_therm";
+ };
+
+ channel@145 {
+ reg = <PM7325_ADC7_AMUX_THM2_100K_PU>;
+ qcom,ratiometric;
+ qcom,hw-settle-time = <200>;
+ qcom,pre-scaling = <1 1>;
+ label = "pm7325_cam_flash_therm";
+ };
+
+ channel@146 {
+ reg = <PM7325_ADC7_AMUX_THM3_100K_PU>;
+ qcom,ratiometric;
+ qcom,hw-settle-time = <200>;
+ qcom,pre-scaling = <1 1>;
+ label = "pm7325_sdm_skin_therm";
+ };
+
+ channel@147 {
+ reg = <PM7325_ADC7_AMUX_THM4_100K_PU>;
+ qcom,ratiometric;
+ qcom,hw-settle-time = <200>;
+ qcom,pre-scaling = <1 1>;
+ label = "pm7325_wide_rfc_therm";
+ };
};
&pon_pwrkey {
@@ -489,6 +696,26 @@
status = "okay";
};
+&remoteproc_adsp {
+ firmware-name = "qcom/qcm6490/fairphone5/adsp.mbn";
+ status = "okay";
+};
+
+&remoteproc_cdsp {
+ firmware-name = "qcom/qcm6490/fairphone5/cdsp.mbn";
+ status = "okay";
+};
+
+&remoteproc_mpss {
+ firmware-name = "qcom/qcm6490/fairphone5/modem.mbn";
+ status = "okay";
+};
+
+&remoteproc_wpss {
+ firmware-name = "qcom/qcm6490/fairphone5/wpss.mbn";
+ status = "okay";
+};
+
&sdc2_clk {
drive-strength = <16>;
bias-disable;
@@ -632,6 +859,28 @@
};
};
+&ufs_mem_hc {
+ reset-gpios = <&tlmm 175 GPIO_ACTIVE_LOW>;
+
+ vcc-supply = <&vreg_l7b>;
+ vcc-max-microamp = <800000>;
+ /*
+ * Technically l9b enables an eLDO (supplied by s1b) which then powers
+ * VCCQ2 of the UFS.
+ */
+ vccq-supply = <&vreg_l9b>;
+ vccq-max-microamp = <900000>;
+
+ status = "okay";
+};
+
+&ufs_mem_phy {
+ vdda-phy-supply = <&vreg_l10c>;
+ vdda-pll-supply = <&vreg_l6b>;
+
+ status = "okay";
+};
+
&usb_1 {
status = "okay";
};
@@ -665,3 +914,8 @@
status = "okay";
};
+
+&wifi {
+ qcom,ath11k-calibration-variant = "Fairphone_5";
+ status = "okay";
+};
diff --git a/dts/upstream/src/arm64/qcom/qcm6490-idp.dts b/dts/upstream/src/arm64/qcom/qcm6490-idp.dts
new file mode 100644
index 0000000..03e97e2
--- /dev/null
+++ b/dts/upstream/src/arm64/qcom/qcm6490-idp.dts
@@ -0,0 +1,468 @@
+// SPDX-License-Identifier: BSD-3-Clause
+/*
+ * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved.
+ */
+
+/dts-v1/;
+
+#include <dt-bindings/regulator/qcom,rpmh-regulator.h>
+#include "sc7280.dtsi"
+#include "pm7325.dtsi"
+#include "pm8350c.dtsi"
+#include "pmk8350.dtsi"
+
+/delete-node/ &ipa_fw_mem;
+/delete-node/ &rmtfs_mem;
+/delete-node/ &adsp_mem;
+/delete-node/ &cdsp_mem;
+/delete-node/ &video_mem;
+/delete-node/ &wlan_ce_mem;
+/delete-node/ &wpss_mem;
+/delete-node/ &xbl_mem;
+
+/ {
+ model = "Qualcomm Technologies, Inc. QCM6490 IDP";
+ compatible = "qcom,qcm6490-idp", "qcom,qcm6490";
+ chassis-type = "embedded";
+
+ aliases {
+ serial0 = &uart5;
+ };
+
+ chosen {
+ stdout-path = "serial0:115200n8";
+ };
+
+ reserved-memory {
+ xbl_mem: xbl@80700000 {
+ reg = <0x0 0x80700000 0x0 0x100000>;
+ no-map;
+ };
+
+ cdsp_secure_heap_mem: cdsp-secure-heap@81800000 {
+ reg = <0x0 0x81800000 0x0 0x1e00000>;
+ no-map;
+ };
+
+ camera_mem: camera@84300000 {
+ reg = <0x0 0x84300000 0x0 0x500000>;
+ no-map;
+ };
+
+ wpss_mem: wpss@84800000 {
+ reg = <0x0 0x84800000 0x0 0x1900000>;
+ no-map;
+ };
+
+ adsp_mem: adsp@86100000 {
+ reg = <0x0 0x86100000 0x0 0x2800000>;
+ no-map;
+ };
+
+ cdsp_mem: cdsp@88900000 {
+ reg = <0x0 0x88900000 0x0 0x1e00000>;
+ no-map;
+ };
+
+ video_mem: video@8a700000 {
+ reg = <0x0 0x8a700000 0x0 0x700000>;
+ no-map;
+ };
+
+ cvp_mem: cvp@8ae00000 {
+ reg = <0x0 0x8ae00000 0x0 0x500000>;
+ no-map;
+ };
+
+ ipa_fw_mem: ipa-fw@8b300000 {
+ reg = <0x0 0x8b300000 0x0 0x10000>;
+ no-map;
+ };
+
+ ipa_gsi_mem: ipa-gsi@8b310000 {
+ reg = <0x0 0x8b310000 0x0 0xa000>;
+ no-map;
+ };
+
+ gpu_microcode_mem: gpu-microcode@8b31a000 {
+ reg = <0x0 0x8b31a000 0x0 0x2000>;
+ no-map;
+ };
+
+ mpss_mem: mpss@8b800000 {
+ reg = <0x0 0x8b800000 0x0 0xf600000>;
+ no-map;
+ };
+
+ tz_stat_mem: tz-stat@c0000000 {
+ reg = <0x0 0xc0000000 0x0 0x100000>;
+ no-map;
+ };
+
+ tags_mem: tags@c0100000 {
+ reg = <0x0 0xc0100000 0x0 0x1200000>;
+ no-map;
+ };
+
+ qtee_mem: qtee@c1300000 {
+ reg = <0x0 0xc1300000 0x0 0x500000>;
+ no-map;
+ };
+
+ trusted_apps_mem: trusted_apps@c1800000 {
+ reg = <0x0 0xc1800000 0x0 0x1c00000>;
+ no-map;
+ };
+
+ debug_vm_mem: debug-vm@d0600000 {
+ reg = <0x0 0xd0600000 0x0 0x100000>;
+ no-map;
+ };
+ };
+
+ vph_pwr: vph-pwr-regulator {
+ compatible = "regulator-fixed";
+ regulator-name = "vph_pwr";
+ regulator-min-microvolt = <2500000>;
+ regulator-max-microvolt = <4350000>;
+ };
+};
+
+&apps_rsc {
+ regulators-0 {
+ compatible = "qcom,pm7325-rpmh-regulators";
+ qcom,pmic-id = "b";
+
+ vdd-s1-supply = <&vph_pwr>;
+ vdd-s2-supply = <&vph_pwr>;
+ vdd-s3-supply = <&vph_pwr>;
+ vdd-s4-supply = <&vph_pwr>;
+ vdd-s5-supply = <&vph_pwr>;
+ vdd-s6-supply = <&vph_pwr>;
+ vdd-s7-supply = <&vph_pwr>;
+ vdd-s8-supply = <&vph_pwr>;
+ vdd-l1-l4-l12-l15-supply = <&vreg_s7b_0p972>;
+ vdd-l2-l7-supply = <&vreg_bob_3p296>;
+ vdd-l3-supply = <&vreg_s2b_0p876>;
+ vdd-l5-supply = <&vreg_s2b_0p876>;
+ vdd-l6-l9-l10-supply = <&vreg_s8b_1p272>;
+ vdd-l8-supply = <&vreg_s7b_0p972>;
+ vdd-l11-l17-l18-l19-supply = <&vreg_s1b_1p872>;
+ vdd-l13-supply = <&vreg_s7b_0p972>;
+ vdd-l14-l16-supply = <&vreg_s8b_1p272>;
+
+ vreg_s1b_1p872: smps1 {
+ regulator-min-microvolt = <1840000>;
+ regulator-max-microvolt = <2040000>;
+ };
+
+ vreg_s2b_0p876: smps2 {
+ regulator-min-microvolt = <570070>;
+ regulator-max-microvolt = <1050000>;
+ };
+
+ vreg_s7b_0p972: smps7 {
+ regulator-min-microvolt = <535000>;
+ regulator-max-microvolt = <1120000>;
+ };
+
+ vreg_s8b_1p272: smps8 {
+ regulator-min-microvolt = <1200000>;
+ regulator-max-microvolt = <1500000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_RET>;
+ };
+
+ vreg_l1b_0p912: ldo1 {
+ regulator-min-microvolt = <825000>;
+ regulator-max-microvolt = <925000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_l2b_3p072: ldo2 {
+ regulator-min-microvolt = <2700000>;
+ regulator-max-microvolt = <3544000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_l3b_0p504: ldo3 {
+ regulator-min-microvolt = <312000>;
+ regulator-max-microvolt = <910000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_l4b_0p752: ldo4 {
+ regulator-min-microvolt = <752000>;
+ regulator-max-microvolt = <820000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ reg_l5b_0p752: ldo5 {
+ regulator-min-microvolt = <552000>;
+ regulator-max-microvolt = <832000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_l6b_1p2: ldo6 {
+ regulator-min-microvolt = <1140000>;
+ regulator-max-microvolt = <1260000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_l7b_2p952: ldo7 {
+ regulator-min-microvolt = <2400000>;
+ regulator-max-microvolt = <3544000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_l8b_0p904: ldo8 {
+ regulator-min-microvolt = <870000>;
+ regulator-max-microvolt = <970000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_l9b_1p2: ldo9 {
+ regulator-min-microvolt = <1200000>;
+ regulator-max-microvolt = <1304000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_l11b_1p504: ldo11 {
+ regulator-min-microvolt = <1504000>;
+ regulator-max-microvolt = <2000000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_l12b_0p751: ldo12 {
+ regulator-min-microvolt = <751000>;
+ regulator-max-microvolt = <824000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_l13b_0p53: ldo13 {
+ regulator-min-microvolt = <530000>;
+ regulator-max-microvolt = <824000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_l14b_1p08: ldo14 {
+ regulator-min-microvolt = <1080000>;
+ regulator-max-microvolt = <1304000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_l15b_0p765: ldo15 {
+ regulator-min-microvolt = <765000>;
+ regulator-max-microvolt = <1020000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_l16b_1p1: ldo16 {
+ regulator-min-microvolt = <1100000>;
+ regulator-max-microvolt = <1300000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_l17b_1p7: ldo17 {
+ regulator-min-microvolt = <1700000>;
+ regulator-max-microvolt = <1900000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_l18b_1p8: ldo18 {
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <2000000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_l19b_1p8: ldo19 {
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <2000000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ regulator-allow-set-load;
+ regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM
+ RPMH_REGULATOR_MODE_HPM>;
+ };
+ };
+
+ regulators-1 {
+ compatible = "qcom,pm8350c-rpmh-regulators";
+ qcom,pmic-id = "c";
+
+ vdd-s1-supply = <&vph_pwr>;
+ vdd-s2-supply = <&vph_pwr>;
+ vdd-s3-supply = <&vph_pwr>;
+ vdd-s4-supply = <&vph_pwr>;
+ vdd-s5-supply = <&vph_pwr>;
+ vdd-s6-supply = <&vph_pwr>;
+ vdd-s7-supply = <&vph_pwr>;
+ vdd-s8-supply = <&vph_pwr>;
+ vdd-s9-supply = <&vph_pwr>;
+ vdd-s10-supply = <&vph_pwr>;
+ vdd-l1-l12-supply = <&vreg_s1b_1p872>;
+ vdd-l2-l8-supply = <&vreg_s1b_1p872>;
+ vdd-l3-l4-l5-l7-l13-supply = <&vreg_bob_3p296>;
+ vdd-l6-l9-l11-supply = <&vreg_bob_3p296>;
+ vdd-l10-supply = <&vreg_s7b_0p972>;
+ vdd-bob-supply = <&vph_pwr>;
+
+ vreg_s1c_2p19: smps1 {
+ regulator-min-microvolt = <2190000>;
+ regulator-max-microvolt = <2210000>;
+ };
+
+ vreg_s2c_0p752: smps2 {
+ regulator-min-microvolt = <750000>;
+ regulator-max-microvolt = <800000>;
+ };
+
+ vreg_s5c_0p752: smps5 {
+ regulator-min-microvolt = <465000>;
+ regulator-max-microvolt = <1050000>;
+ };
+
+ vreg_s7c_0p752: smps7 {
+ regulator-min-microvolt = <465000>;
+ regulator-max-microvolt = <800000>;
+ };
+
+ vreg_s9c_1p084: smps9 {
+ regulator-min-microvolt = <1010000>;
+ regulator-max-microvolt = <1170000>;
+ };
+
+ vreg_l1c_1p8: ldo1 {
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1980000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_l2c_1p62: ldo2 {
+ regulator-min-microvolt = <1620000>;
+ regulator-max-microvolt = <1980000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_l3c_2p8: ldo3 {
+ regulator-min-microvolt = <2800000>;
+ regulator-max-microvolt = <3540000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_l4c_1p62: ldo4 {
+ regulator-min-microvolt = <1620000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_l5c_1p62: ldo5 {
+ regulator-min-microvolt = <1620000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_l6c_2p96: ldo6 {
+ regulator-min-microvolt = <1650000>;
+ regulator-max-microvolt = <3544000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_l7c_3p0: ldo7 {
+ regulator-min-microvolt = <3000000>;
+ regulator-max-microvolt = <3544000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_l8c_1p62: ldo8 {
+ regulator-min-microvolt = <1620000>;
+ regulator-max-microvolt = <2000000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_l9c_2p96: ldo9 {
+ regulator-min-microvolt = <2700000>;
+ regulator-max-microvolt = <35440000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_l10c_0p88: ldo10 {
+ regulator-min-microvolt = <720000>;
+ regulator-max-microvolt = <1050000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_l11c_2p8: ldo11 {
+ regulator-min-microvolt = <2800000>;
+ regulator-max-microvolt = <3544000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_l12c_1p65: ldo12 {
+ regulator-min-microvolt = <1650000>;
+ regulator-max-microvolt = <2000000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_l13c_2p7: ldo13 {
+ regulator-min-microvolt = <2700000>;
+ regulator-max-microvolt = <3544000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_bob_3p296: bob {
+ regulator-min-microvolt = <3008000>;
+ regulator-max-microvolt = <3960000>;
+ };
+ };
+};
+
+&qupv3_id_0 {
+ status = "okay";
+};
+
+&sdhc_1 {
+ non-removable;
+ no-sd;
+ no-sdio;
+
+ vmmc-supply = <&vreg_l7b_2p952>;
+ vqmmc-supply = <&vreg_l19b_1p8>;
+
+ status = "okay";
+};
+
+&tlmm {
+ gpio-reserved-ranges = <32 2>, /* ADSP */
+ <48 4>; /* NFC */
+};
+
+&uart5 {
+ compatible = "qcom,geni-debug-uart";
+ status = "okay";
+};
+
+&usb_1 {
+ status = "okay";
+};
+
+&usb_1_dwc3 {
+ dr_mode = "peripheral";
+};
+
+&usb_1_hsphy {
+ vdda-pll-supply = <&vreg_l10c_0p88>;
+ vdda33-supply = <&vreg_l2b_3p072>;
+ vdda18-supply = <&vreg_l1c_1p8>;
+
+ status = "okay";
+};
+
+&usb_1_qmpphy {
+ vdda-phy-supply = <&vreg_l6b_1p2>;
+ vdda-pll-supply = <&vreg_l1b_0p912>;
+
+ status = "okay";
+};
+
+&wifi {
+ memory-region = <&wlan_fw_mem>;
+};
diff --git a/dts/upstream/src/arm64/qcom/qcs404.dtsi b/dts/upstream/src/arm64/qcom/qcs404.dtsi
index 2721f32..2f2eeaf 100644
--- a/dts/upstream/src/arm64/qcom/qcs404.dtsi
+++ b/dts/upstream/src/arm64/qcom/qcs404.dtsi
@@ -558,9 +558,6 @@
reg = <0x00400000 0x80000>;
compatible = "qcom,qcs404-bimc";
#interconnect-cells = <1>;
- clock-names = "bus", "bus_a";
- clocks = <&rpmcc RPM_SMD_BIMC_CLK>,
- <&rpmcc RPM_SMD_BIMC_A_CLK>;
};
tsens: thermal-sensor@4a9000 {
@@ -601,18 +598,12 @@
reg = <0x00500000 0x15080>;
compatible = "qcom,qcs404-pcnoc";
#interconnect-cells = <1>;
- clock-names = "bus", "bus_a";
- clocks = <&rpmcc RPM_SMD_PNOC_CLK>,
- <&rpmcc RPM_SMD_PNOC_A_CLK>;
};
snoc: interconnect@580000 {
reg = <0x00580000 0x23080>;
compatible = "qcom,qcs404-snoc";
#interconnect-cells = <1>;
- clock-names = "bus", "bus_a";
- clocks = <&rpmcc RPM_SMD_SNOC_CLK>,
- <&rpmcc RPM_SMD_SNOC_A_CLK>;
};
remoteproc_cdsp: remoteproc@b00000 {
@@ -1461,7 +1452,7 @@
};
};
- pcie: pci@10000000 {
+ pcie: pcie@10000000 {
compatible = "qcom,pcie-qcs404";
reg = <0x10000000 0xf1d>,
<0x10000f20 0xa8>,
diff --git a/dts/upstream/src/arm64/qcom/qcs6490-rb3gen2.dts b/dts/upstream/src/arm64/qcom/qcs6490-rb3gen2.dts
new file mode 100644
index 0000000..8bb7d13
--- /dev/null
+++ b/dts/upstream/src/arm64/qcom/qcs6490-rb3gen2.dts
@@ -0,0 +1,455 @@
+// SPDX-License-Identifier: BSD-3-Clause
+/*
+ * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved.
+ */
+
+/dts-v1/;
+
+/* PM7250B is configured to use SID8/9 */
+#define PM7250B_SID 8
+#define PM7250B_SID1 9
+
+#include <dt-bindings/regulator/qcom,rpmh-regulator.h>
+#include "sc7280.dtsi"
+#include "pm7250b.dtsi"
+#include "pm7325.dtsi"
+#include "pm8350c.dtsi"
+#include "pmk8350.dtsi"
+
+/delete-node/ &ipa_fw_mem;
+/delete-node/ &remoteproc_mpss;
+/delete-node/ &rmtfs_mem;
+/delete-node/ &adsp_mem;
+/delete-node/ &cdsp_mem;
+/delete-node/ &video_mem;
+/delete-node/ &wlan_ce_mem;
+/delete-node/ &wpss_mem;
+/delete-node/ &xbl_mem;
+
+/ {
+ model = "Qualcomm Technologies, Inc. Robotics RB3gen2";
+ compatible = "qcom,qcs6490-rb3gen2", "qcom,qcm6490";
+ chassis-type = "embedded";
+
+ aliases {
+ serial0 = &uart5;
+ };
+
+ chosen {
+ stdout-path = "serial0:115200n8";
+ };
+
+ reserved-memory {
+ xbl_mem: xbl@80700000 {
+ reg = <0x0 0x80700000 0x0 0x100000>;
+ no-map;
+ };
+
+ cdsp_secure_heap_mem: cdsp-secure-heap@81800000 {
+ reg = <0x0 0x81800000 0x0 0x1e00000>;
+ no-map;
+ };
+
+ camera_mem: camera@84300000 {
+ reg = <0x0 0x84300000 0x0 0x500000>;
+ no-map;
+ };
+
+ wpss_mem: wpss@84800000 {
+ reg = <0x0 0x84800000 0x0 0x1900000>;
+ no-map;
+ };
+
+ adsp_mem: adsp@86100000 {
+ reg = <0x0 0x86100000 0x0 0x2800000>;
+ no-map;
+ };
+
+ cdsp_mem: cdsp@88900000 {
+ reg = <0x0 0x88900000 0x0 0x1e00000>;
+ no-map;
+ };
+
+ video_mem: video@8a700000 {
+ reg = <0x0 0x8a700000 0x0 0x700000>;
+ no-map;
+ };
+
+ cvp_mem: cvp@8ae00000 {
+ reg = <0x0 0x8ae00000 0x0 0x500000>;
+ no-map;
+ };
+
+ ipa_fw_mem: ipa-fw@8b300000 {
+ reg = <0x0 0x8b300000 0x0 0x10000>;
+ no-map;
+ };
+
+ ipa_gsi_mem: ipa-gsi@8b310000 {
+ reg = <0x0 0x8b310000 0x0 0xa000>;
+ no-map;
+ };
+
+ gpu_microcode_mem: gpu-microcode@8b31a000 {
+ reg = <0x0 0x8b31a000 0x0 0x2000>;
+ no-map;
+ };
+
+ tz_stat_mem: tz-stat@c0000000 {
+ reg = <0x0 0xc0000000 0x0 0x100000>;
+ no-map;
+ };
+
+ tags_mem: tags@c0100000 {
+ reg = <0x0 0xc0100000 0x0 0x1200000>;
+ no-map;
+ };
+
+ qtee_mem: qtee@c1300000 {
+ reg = <0x0 0xc1300000 0x0 0x500000>;
+ no-map;
+ };
+
+ trusted_apps_mem: trusted_apps@c1800000 {
+ reg = <0x0 0xc1800000 0x0 0x1c00000>;
+ no-map;
+ };
+
+ debug_vm_mem: debug-vm@d0600000 {
+ reg = <0x0 0xd0600000 0x0 0x100000>;
+ no-map;
+ };
+ };
+
+ vph_pwr: vph-pwr-regulator {
+ compatible = "regulator-fixed";
+ regulator-name = "vph_pwr";
+ regulator-min-microvolt = <2500000>;
+ regulator-max-microvolt = <4350000>;
+ };
+};
+
+&apps_rsc {
+ regulators-0 {
+ compatible = "qcom,pm7325-rpmh-regulators";
+ qcom,pmic-id = "b";
+
+ vdd-s1-supply = <&vph_pwr>;
+ vdd-s2-supply = <&vph_pwr>;
+ vdd-s3-supply = <&vph_pwr>;
+ vdd-s4-supply = <&vph_pwr>;
+ vdd-s5-supply = <&vph_pwr>;
+ vdd-s6-supply = <&vph_pwr>;
+ vdd-s7-supply = <&vph_pwr>;
+ vdd-s8-supply = <&vph_pwr>;
+ vdd-l1-l4-l12-l15-supply = <&vreg_s7b_0p972>;
+ vdd-l2-l7-supply = <&vreg_bob_3p296>;
+ vdd-l3-supply = <&vreg_s2b_0p876>;
+ vdd-l5-supply = <&vreg_s2b_0p876>;
+ vdd-l6-l9-l10-supply = <&vreg_s8b_1p272>;
+ vdd-l8-supply = <&vreg_s7b_0p972>;
+ vdd-l11-l17-l18-l19-supply = <&vreg_s1b_1p872>;
+ vdd-l13-supply = <&vreg_s7b_0p972>;
+ vdd-l14-l16-supply = <&vreg_s8b_1p272>;
+
+ vreg_s1b_1p872: smps1 {
+ regulator-min-microvolt = <1840000>;
+ regulator-max-microvolt = <2040000>;
+ };
+
+ vreg_s2b_0p876: smps2 {
+ regulator-min-microvolt = <570070>;
+ regulator-max-microvolt = <1050000>;
+ };
+
+ vreg_s7b_0p972: smps7 {
+ regulator-min-microvolt = <535000>;
+ regulator-max-microvolt = <1120000>;
+ };
+
+ vreg_s8b_1p272: smps8 {
+ regulator-min-microvolt = <1200000>;
+ regulator-max-microvolt = <1500000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_RET>;
+ };
+
+ vreg_l1b_0p912: ldo1 {
+ regulator-min-microvolt = <825000>;
+ regulator-max-microvolt = <925000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_l2b_3p072: ldo2 {
+ regulator-min-microvolt = <2700000>;
+ regulator-max-microvolt = <3544000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_l3b_0p504: ldo3 {
+ regulator-min-microvolt = <312000>;
+ regulator-max-microvolt = <910000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_l4b_0p752: ldo4 {
+ regulator-min-microvolt = <752000>;
+ regulator-max-microvolt = <820000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ reg_l5b_0p752: ldo5 {
+ regulator-min-microvolt = <552000>;
+ regulator-max-microvolt = <832000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_l6b_1p2: ldo6 {
+ regulator-min-microvolt = <1140000>;
+ regulator-max-microvolt = <1260000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_l7b_2p952: ldo7 {
+ regulator-min-microvolt = <2400000>;
+ regulator-max-microvolt = <3544000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_l8b_0p904: ldo8 {
+ regulator-min-microvolt = <870000>;
+ regulator-max-microvolt = <970000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_l9b_1p2: ldo9 {
+ regulator-min-microvolt = <1200000>;
+ regulator-max-microvolt = <1304000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_l11b_1p504: ldo11 {
+ regulator-min-microvolt = <1504000>;
+ regulator-max-microvolt = <2000000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_l12b_0p751: ldo12 {
+ regulator-min-microvolt = <751000>;
+ regulator-max-microvolt = <824000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_l13b_0p53: ldo13 {
+ regulator-min-microvolt = <530000>;
+ regulator-max-microvolt = <824000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_l14b_1p08: ldo14 {
+ regulator-min-microvolt = <1080000>;
+ regulator-max-microvolt = <1304000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_l15b_0p765: ldo15 {
+ regulator-min-microvolt = <765000>;
+ regulator-max-microvolt = <1020000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_l16b_1p1: ldo16 {
+ regulator-min-microvolt = <1100000>;
+ regulator-max-microvolt = <1300000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_l17b_1p7: ldo17 {
+ regulator-min-microvolt = <1700000>;
+ regulator-max-microvolt = <1900000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_l18b_1p8: ldo18 {
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <2000000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_l19b_1p8: ldo19 {
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <2000000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+ };
+
+ regulators-1 {
+ compatible = "qcom,pm8350c-rpmh-regulators";
+ qcom,pmic-id = "c";
+
+ vdd-s1-supply = <&vph_pwr>;
+ vdd-s2-supply = <&vph_pwr>;
+ vdd-s3-supply = <&vph_pwr>;
+ vdd-s4-supply = <&vph_pwr>;
+ vdd-s5-supply = <&vph_pwr>;
+ vdd-s6-supply = <&vph_pwr>;
+ vdd-s7-supply = <&vph_pwr>;
+ vdd-s8-supply = <&vph_pwr>;
+ vdd-s9-supply = <&vph_pwr>;
+ vdd-s10-supply = <&vph_pwr>;
+ vdd-l1-l12-supply = <&vreg_s1b_1p872>;
+ vdd-l2-l8-supply = <&vreg_s1b_1p872>;
+ vdd-l3-l4-l5-l7-l13-supply = <&vreg_bob_3p296>;
+ vdd-l6-l9-l11-supply = <&vreg_bob_3p296>;
+ vdd-l10-supply = <&vreg_s7b_0p972>;
+ vdd-bob-supply = <&vph_pwr>;
+
+ vreg_s1c_2p19: smps1 {
+ regulator-min-microvolt = <2190000>;
+ regulator-max-microvolt = <2210000>;
+ };
+
+ vreg_s2c_0p752: smps2 {
+ regulator-min-microvolt = <750000>;
+ regulator-max-microvolt = <800000>;
+ };
+
+ vreg_s5c_0p752: smps5 {
+ regulator-min-microvolt = <465000>;
+ regulator-max-microvolt = <1050000>;
+ };
+
+ vreg_s7c_0p752: smps7 {
+ regulator-min-microvolt = <465000>;
+ regulator-max-microvolt = <800000>;
+ };
+
+ vreg_s9c_1p084: smps9 {
+ regulator-min-microvolt = <1010000>;
+ regulator-max-microvolt = <1170000>;
+ };
+
+ vreg_l1c_1p8: ldo1 {
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1980000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_l2c_1p62: ldo2 {
+ regulator-min-microvolt = <1620000>;
+ regulator-max-microvolt = <1980000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_l3c_2p8: ldo3 {
+ regulator-min-microvolt = <2800000>;
+ regulator-max-microvolt = <3540000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_l4c_1p62: ldo4 {
+ regulator-min-microvolt = <1620000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_l5c_1p62: ldo5 {
+ regulator-min-microvolt = <1620000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_l6c_2p96: ldo6 {
+ regulator-min-microvolt = <1650000>;
+ regulator-max-microvolt = <3544000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_l7c_3p0: ldo7 {
+ regulator-min-microvolt = <3000000>;
+ regulator-max-microvolt = <3544000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_l8c_1p62: ldo8 {
+ regulator-min-microvolt = <1620000>;
+ regulator-max-microvolt = <2000000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_l9c_2p96: ldo9 {
+ regulator-min-microvolt = <2700000>;
+ regulator-max-microvolt = <35440000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_l10c_0p88: ldo10 {
+ regulator-min-microvolt = <720000>;
+ regulator-max-microvolt = <1050000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_l11c_2p8: ldo11 {
+ regulator-min-microvolt = <2800000>;
+ regulator-max-microvolt = <3544000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_l12c_1p65: ldo12 {
+ regulator-min-microvolt = <1650000>;
+ regulator-max-microvolt = <2000000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_l13c_2p7: ldo13 {
+ regulator-min-microvolt = <2700000>;
+ regulator-max-microvolt = <3544000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_bob_3p296: bob {
+ regulator-min-microvolt = <3008000>;
+ regulator-max-microvolt = <3960000>;
+ };
+ };
+};
+
+&qupv3_id_0 {
+ status = "okay";
+};
+
+&tlmm {
+ gpio-reserved-ranges = <32 2>, /* ADSP */
+ <48 4>; /* NFC */
+};
+
+&uart5 {
+ compatible = "qcom,geni-debug-uart";
+ status = "okay";
+};
+
+&usb_1 {
+ status = "okay";
+};
+
+&usb_1_dwc3 {
+ dr_mode = "peripheral";
+};
+
+&usb_1_hsphy {
+ vdda-pll-supply = <&vreg_l10c_0p88>;
+ vdda33-supply = <&vreg_l2b_3p072>;
+ vdda18-supply = <&vreg_l1c_1p8>;
+
+ status = "okay";
+};
+
+&usb_1_qmpphy {
+ vdda-phy-supply = <&vreg_l6b_1p2>;
+ vdda-pll-supply = <&vreg_l1b_0p912>;
+
+ status = "okay";
+};
+
+&wifi {
+ memory-region = <&wlan_fw_mem>;
+};
diff --git a/dts/upstream/src/arm64/qcom/qdu1000.dtsi b/dts/upstream/src/arm64/qcom/qdu1000.dtsi
index 1c0e5d2..832f472 100644
--- a/dts/upstream/src/arm64/qcom/qdu1000.dtsi
+++ b/dts/upstream/src/arm64/qcom/qdu1000.dtsi
@@ -381,6 +381,20 @@
#power-domain-cells = <1>;
};
+ ecpricc: clock-controller@280000 {
+ compatible = "qcom,qdu1000-ecpricc";
+ reg = <0x0 0x00280000 0x0 0x31c00>;
+ clocks = <&rpmhcc RPMH_CXO_CLK>,
+ <&gcc GCC_ECPRI_CC_GPLL0_CLK_SRC>,
+ <&gcc GCC_ECPRI_CC_GPLL1_EVEN_CLK_SRC>,
+ <&gcc GCC_ECPRI_CC_GPLL2_EVEN_CLK_SRC>,
+ <&gcc GCC_ECPRI_CC_GPLL3_CLK_SRC>,
+ <&gcc GCC_ECPRI_CC_GPLL4_CLK_SRC>,
+ <&gcc GCC_ECPRI_CC_GPLL5_EVEN_CLK_SRC>;
+ #clock-cells = <1>;
+ #reset-cells = <1>;
+ };
+
gpi_dma0: dma-controller@900000 {
compatible = "qcom,qdu1000-gpi-dma", "qcom,sm6350-gpi-dma";
reg = <0x0 0x900000 0x0 0x60000>;
@@ -1446,13 +1460,10 @@
system-cache-controller@19200000 {
compatible = "qcom,qdu1000-llcc";
reg = <0 0x19200000 0 0xd80000>,
- <0 0x1a200000 0 0x80000>,
- <0 0x221c8128 0 0x4>;
- reg-names = "llcc_base",
- "llcc_broadcast_base",
- "multi_channel_register";
+ <0 0x1a200000 0 0x80000>;
+ reg-names = "llcc0_base",
+ "llcc_broadcast_base";
interrupts = <GIC_SPI 266 IRQ_TYPE_LEVEL_HIGH>;
- multi-ch-bit-off = <24 2>;
};
};
diff --git a/dts/upstream/src/arm64/qcom/qrb2210-rb1.dts b/dts/upstream/src/arm64/qcom/qrb2210-rb1.dts
index 94885b9..aa53b6a 100644
--- a/dts/upstream/src/arm64/qcom/qrb2210-rb1.dts
+++ b/dts/upstream/src/arm64/qcom/qrb2210-rb1.dts
@@ -23,6 +23,14 @@
stdout-path = "serial0:115200n8";
};
+ clocks {
+ clk40M: can-clk {
+ compatible = "fixed-clock";
+ clock-frequency = <40000000>;
+ #clock-cells = <0>;
+ };
+ };
+
gpio-keys {
compatible = "gpio-keys";
label = "gpio-keys";
@@ -40,6 +48,17 @@
};
};
+ hdmi-connector {
+ compatible = "hdmi-connector";
+ type = "a";
+
+ port {
+ hdmi_con: endpoint {
+ remote-endpoint = <<9611_out>;
+ };
+ };
+ };
+
leds {
compatible = "gpio-leds";
@@ -158,6 +177,68 @@
};
};
+&gpi_dma0 {
+ status = "okay";
+};
+
+&i2c2 {
+ clock-frequency = <400000>;
+ status = "okay";
+
+ lt9611_codec: hdmi-bridge@2b {
+ compatible = "lontium,lt9611uxc";
+ reg = <0x2b>;
+ interrupts-extended = <&tlmm 46 IRQ_TYPE_EDGE_FALLING>;
+ reset-gpios = <&tlmm 41 GPIO_ACTIVE_HIGH>;
+
+ vdd-supply = <&vreg_hdmi_out_1p2>;
+ vcc-supply = <<9611_3v3>;
+
+ pinctrl-0 = <<9611_irq_pin <9611_rst_pin>;
+ pinctrl-names = "default";
+ #sound-dai-cells = <1>;
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+
+ lt9611_a: endpoint {
+ remote-endpoint = <&mdss_dsi0_out>;
+ };
+ };
+
+ port@2 {
+ reg = <2>;
+
+ lt9611_out: endpoint {
+ remote-endpoint = <&hdmi_con>;
+ };
+ };
+ };
+ };
+};
+
+&mdss {
+ status = "okay";
+};
+
+&mdss_dsi0 {
+ vdda-supply = <&pm2250_l5>;
+ status = "okay";
+};
+
+&mdss_dsi0_out {
+ remote-endpoint = <<9611_a>;
+ data-lanes = <0 1 2 3>;
+};
+
+&mdss_dsi0_phy {
+ status = "okay";
+};
+
&pm2250_resin {
linux,code = <KEY_VOLUMEDOWN>;
status = "okay";
@@ -374,9 +455,36 @@
no-sdio;
no-mmc;
status = "okay";
+};
+
+&spi5 {
+ status = "okay";
+
+ can@0 {
+ compatible = "microchip,mcp2518fd";
+ reg = <0>;
+ interrupts-extended = <&tlmm 39 IRQ_TYPE_LEVEL_LOW>;
+ clocks = <&clk40M>;
+ spi-max-frequency = <10000000>;
+ vdd-supply = <&vdc_5v>;
+ xceiver-supply = <&vdc_5v>;
+ };
};
&tlmm {
+ lt9611_rst_pin: lt9611-rst-state {
+ pins = "gpio41";
+ function = "gpio";
+ input-disable;
+ output-high;
+ };
+
+ lt9611_irq_pin: lt9611-irq-state {
+ pins = "gpio46";
+ function = "gpio";
+ bias-disable;
+ };
+
sd_det_in_on: sd-det-in-on-state {
pins = "gpio88";
function = "gpio";
@@ -415,6 +523,10 @@
status = "okay";
};
+&usb_dwc3 {
+ dr_mode = "host";
+};
+
&usb_hsphy {
vdd-supply = <&pm2250_l12>;
vdda-pll-supply = <&pm2250_l13>;
@@ -427,6 +539,7 @@
vdd-1.8-xo-supply = <&pm2250_l13>;
vdd-1.3-rfa-supply = <&pm2250_l10>;
vdd-3.3-ch0-supply = <&pm2250_l22>;
+ qcom,ath10k-calibration-variant = "Thundercomm_RB1";
status = "okay";
};
diff --git a/dts/upstream/src/arm64/qcom/qrb4210-rb2.dts b/dts/upstream/src/arm64/qcom/qrb4210-rb2.dts
index a7278a9..7c19f87 100644
--- a/dts/upstream/src/arm64/qcom/qrb4210-rb2.dts
+++ b/dts/upstream/src/arm64/qcom/qrb4210-rb2.dts
@@ -15,6 +15,7 @@
aliases {
serial0 = &uart4;
+ serial1 = &uart3;
};
chosen {
@@ -280,6 +281,12 @@
status = "okay";
};
+&remoteproc_mpss {
+ firmware-name = "qcom/qrb4210/modem.mbn";
+
+ status = "okay";
+};
+
&rpm_requests {
regulators {
compatible = "qcom,rpm-pm6125-regulators";
@@ -346,13 +353,14 @@
};
vreg_l8a_0p664: l8 {
- regulator-min-microvolt = <400000>;
- regulator-max-microvolt = <728000>;
+ regulator-min-microvolt = <640000>;
+ regulator-max-microvolt = <640000>;
};
vreg_l9a_1p8: l9 {
regulator-min-microvolt = <1800000>;
- regulator-max-microvolt = <2000000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-allow-set-load;
};
vreg_l10a_1p8: l10 {
@@ -389,11 +397,13 @@
vreg_l16a_1p3: l16 {
regulator-min-microvolt = <1704000>;
regulator-max-microvolt = <1904000>;
+ regulator-allow-set-load;
};
vreg_l17a_1p3: l17 {
regulator-min-microvolt = <1152000>;
regulator-max-microvolt = <1384000>;
+ regulator-allow-set-load;
};
vreg_l18a_1p232: l18 {
@@ -424,8 +434,9 @@
};
vreg_l23a_3p3: l23 {
- regulator-min-microvolt = <3200000>;
- regulator-max-microvolt = <3400000>;
+ regulator-min-microvolt = <3312000>;
+ regulator-max-microvolt = <3312000>;
+ regulator-allow-set-load;
};
vreg_l24a_2p96: l24 {
@@ -487,6 +498,66 @@
<56 3>, <61 2>, <64 1>,
<68 1>, <72 8>, <96 1>;
+ uart3_default: uart3-default-state {
+ cts-pins {
+ pins = "gpio8";
+ function = "qup3";
+ drive-strength = <2>;
+ bias-bus-hold;
+ };
+
+ rts-pins {
+ pins = "gpio9";
+ function = "qup3";
+ drive-strength = <2>;
+ bias-disable;
+ };
+
+ tx-pins {
+ pins = "gpio10";
+ function = "qup3";
+ drive-strength = <2>;
+ bias-disable;
+ };
+
+ rx-pins {
+ pins = "gpio11";
+ function = "qup3";
+ drive-strength = <2>;
+ bias-pull-up;
+ };
+ };
+
+ uart3_sleep: uart3-sleep-state {
+ cts-pins {
+ pins = "gpio8";
+ function = "gpio";
+ drive-strength = <2>;
+ bias-bus-hold;
+ };
+
+ rts-pins {
+ pins = "gpio9";
+ function = "gpio";
+ drive-strength = <2>;
+ bias-pull-down;
+ };
+
+ tx-pins {
+ pins = "gpio10";
+ function = "gpio";
+ drive-strength = <2>;
+ bias-pull-up;
+ };
+
+ rx-pins {
+ pins = "gpio11";
+ function = "gpio";
+ drive-strength = <2>;
+ bias-pull-up;
+ };
+ };
+
lt9611_rst_pin: lt9611-rst-state {
pins = "gpio41";
function = "gpio";
@@ -508,6 +579,26 @@
};
};
+&uart3 {
+ interrupts-extended = <&intc GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH>,
+ <&tlmm 11 IRQ_TYPE_LEVEL_HIGH>;
+ pinctrl-0 = <&uart3_default>;
+ pinctrl-1 = <&uart3_sleep>;
+ pinctrl-names = "default", "sleep";
+ status = "okay";
+
+ bluetooth {
+ compatible = "qcom,wcn3988-bt";
+
+ vddio-supply = <&vreg_l9a_1p8>;
+ vddxo-supply = <&vreg_l16a_1p3>;
+ vddrf-supply = <&vreg_l17a_1p3>;
+ vddch0-supply = <&vreg_l23a_3p3>;
+ enable-gpios = <&tlmm 87 GPIO_ACTIVE_HIGH>;
+ max-speed = <3200000>;
+ };
+};
+
&uart4 {
status = "okay";
};
@@ -518,7 +609,6 @@
&usb_dwc3 {
maximum-speed = "super-speed";
- dr_mode = "peripheral";
};
&usb_hsphy {
@@ -536,6 +626,16 @@
status = "okay";
};
+&wifi {
+ vdd-0.8-cx-mx-supply = <&vreg_l8a_0p664>;
+ vdd-1.8-xo-supply = <&vreg_l16a_1p3>;
+ vdd-1.3-rfa-supply = <&vreg_l17a_1p3>;
+ vdd-3.3-ch0-supply = <&vreg_l23a_3p3>;
+ qcom,ath10k-calibration-variant = "Thundercomm_RB2";
+
+ status = "okay";
+};
+
&xo_board {
clock-frequency = <19200000>;
};
diff --git a/dts/upstream/src/arm64/qcom/qrb5165-rb5-vision-mezzanine.dts b/dts/upstream/src/arm64/qcom/qrb5165-rb5-vision-mezzanine.dts
index bb149e5..edc0e42 100644
--- a/dts/upstream/src/arm64/qcom/qrb5165-rb5-vision-mezzanine.dts
+++ b/dts/upstream/src/arm64/qcom/qrb5165-rb5-vision-mezzanine.dts
@@ -46,7 +46,7 @@
assigned-clocks = <&camcc CAM_CC_MCLK2_CLK>;
assigned-clock-rates = <24000000>;
- dovdd-supply = <&vreg_l7f_1p8>;
+ dovdd-supply = <&vreg_l7f_1p8>;
avdd-supply = <&vdc_5v>;
dvdd-supply = <&vdc_5v>;
diff --git a/dts/upstream/src/arm64/qcom/qrb5165-rb5.dts b/dts/upstream/src/arm64/qcom/qrb5165-rb5.dts
index c8cd40a..cd0db4f 100644
--- a/dts/upstream/src/arm64/qcom/qrb5165-rb5.dts
+++ b/dts/upstream/src/arm64/qcom/qrb5165-rb5.dts
@@ -23,6 +23,7 @@
aliases {
serial0 = &uart12;
+ serial1 = &uart6;
sdhc2 = &sdhc_2;
};
@@ -64,8 +65,8 @@
function = LED_FUNCTION_INDICATOR;
color = <LED_COLOR_ID_GREEN>;
gpios = <&pm8150_gpios 10 GPIO_ACTIVE_HIGH>;
- linux,default-trigger = "panic-indicator";
default-state = "off";
+ panic-indicator;
};
led-wlan {
@@ -1263,6 +1264,14 @@
"HST_WLAN_UART_TX",
"HST_WLAN_UART_RX";
+ bt_en_state: bt-default-state {
+ pins = "gpio21";
+ function = "gpio";
+ drive-strength = <16>;
+ output-low;
+ bias-pull-up;
+ };
+
lt9611_irq_pin: lt9611-irq-state {
pins = "gpio63";
function = "gpio";
@@ -1296,6 +1305,26 @@
};
};
+&uart6 {
+ status = "okay";
+
+ bluetooth {
+ compatible = "qcom,qca6390-bt";
+
+ pinctrl-names = "default";
+ pinctrl-0 = <&bt_en_state>;
+
+ enable-gpios = <&tlmm 21 GPIO_ACTIVE_HIGH>;
+
+ vddio-supply = <&vreg_s4a_1p8>;
+ vddpmu-supply = <&vreg_s2f_0p95>;
+ vddaon-supply = <&vreg_s6a_0p95>;
+ vddrfa0p9-supply = <&vreg_s2f_0p95>;
+ vddrfa1p3-supply = <&vreg_s8c_1p3>;
+ vddrfa1p9-supply = <&vreg_s5a_1p9>;
+ };
+};
+
&uart12 {
status = "okay";
};
@@ -1425,7 +1454,7 @@
altmodes {
displayport {
- svid = <0xff01>;
+ svid = /bits/ 16 <0xff01>;
vdo = <0x00001c46>;
};
};
diff --git a/dts/upstream/src/arm64/qcom/sa8775p-ride.dts b/dts/upstream/src/arm64/qcom/sa8775p-ride.dts
index 9760bb4..26ad05b 100644
--- a/dts/upstream/src/arm64/qcom/sa8775p-ride.dts
+++ b/dts/upstream/src/arm64/qcom/sa8775p-ride.dts
@@ -461,6 +461,11 @@
"ANALOG_PON_OPT";
};
+&pmm8654au_0_pon_resin {
+ linux,code = <KEY_VOLUMEDOWN>;
+ status = "okay";
+};
+
&pmm8654au_1_gpios {
gpio-line-names = "PMIC_C_ID0",
"PMIC_C_ID1",
diff --git a/dts/upstream/src/arm64/qcom/sa8775p.dtsi b/dts/upstream/src/arm64/qcom/sa8775p.dtsi
index b6a93b1..a7eaca3 100644
--- a/dts/upstream/src/arm64/qcom/sa8775p.dtsi
+++ b/dts/upstream/src/arm64/qcom/sa8775p.dtsi
@@ -1487,6 +1487,11 @@
};
};
+ rng: rng@10d2000 {
+ compatible = "qcom,sa8775p-trng", "qcom,trng";
+ reg = <0 0x010d2000 0 0x1000>;
+ };
+
ufs_mem_hc: ufs@1d84000 {
compatible = "qcom,sa8775p-ufshc", "qcom,ufshc", "jedec,ufs-2.0";
reg = <0x0 0x01d84000 0x0 0x3000>;
@@ -1610,8 +1615,8 @@
assigned-clock-rates = <19200000>, <200000000>;
interrupts-extended = <&intc GIC_SPI 287 IRQ_TYPE_LEVEL_HIGH>,
- <&pdc 14 IRQ_TYPE_EDGE_RISING>,
- <&pdc 15 IRQ_TYPE_EDGE_RISING>,
+ <&pdc 14 IRQ_TYPE_EDGE_BOTH>,
+ <&pdc 15 IRQ_TYPE_EDGE_BOTH>,
<&pdc 12 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "pwr_event",
"dp_hs_phy_irq",
@@ -1697,8 +1702,8 @@
assigned-clock-rates = <19200000>, <200000000>;
interrupts-extended = <&intc GIC_SPI 352 IRQ_TYPE_LEVEL_HIGH>,
- <&pdc 8 IRQ_TYPE_EDGE_RISING>,
- <&pdc 7 IRQ_TYPE_EDGE_RISING>,
+ <&pdc 8 IRQ_TYPE_EDGE_BOTH>,
+ <&pdc 7 IRQ_TYPE_EDGE_BOTH>,
<&pdc 13 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "pwr_event",
"dp_hs_phy_irq",
@@ -1760,8 +1765,8 @@
assigned-clock-rates = <19200000>, <200000000>;
interrupts-extended = <&intc GIC_SPI 444 IRQ_TYPE_LEVEL_HIGH>,
- <&pdc 10 IRQ_TYPE_EDGE_RISING>,
- <&pdc 9 IRQ_TYPE_EDGE_RISING>;
+ <&pdc 10 IRQ_TYPE_EDGE_BOTH>,
+ <&pdc 9 IRQ_TYPE_EDGE_BOTH>;
interrupt-names = "pwr_event",
"dp_hs_phy_irq",
"dm_hs_phy_irq";
@@ -1910,6 +1915,50 @@
interrupt-controller;
};
+ tsens2: thermal-sensor@c251000 {
+ compatible = "qcom,sa8775p-tsens", "qcom,tsens-v2";
+ reg = <0x0 0x0c251000 0x0 0x1ff>,
+ <0x0 0x0c224000 0x0 0x8>;
+ interrupts = <GIC_SPI 572 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 609 IRQ_TYPE_LEVEL_HIGH>;
+ #qcom,sensors = <13>;
+ interrupt-names = "uplow", "critical";
+ #thermal-sensor-cells = <1>;
+ };
+
+ tsens3: thermal-sensor@c252000 {
+ compatible = "qcom,sa8775p-tsens", "qcom,tsens-v2";
+ reg = <0x0 0x0c252000 0x0 0x1ff>,
+ <0x0 0x0c225000 0x0 0x8>;
+ interrupts = <GIC_SPI 573 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 610 IRQ_TYPE_LEVEL_HIGH>;
+ #qcom,sensors = <13>;
+ interrupt-names = "uplow", "critical";
+ #thermal-sensor-cells = <1>;
+ };
+
+ tsens0: thermal-sensor@c263000 {
+ compatible = "qcom,sa8775p-tsens", "qcom,tsens-v2";
+ reg = <0x0 0x0c263000 0x0 0x1ff>,
+ <0x0 0x0c222000 0x0 0x8>;
+ interrupts = <GIC_SPI 506 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 508 IRQ_TYPE_LEVEL_HIGH>;
+ #qcom,sensors = <12>;
+ interrupt-names = "uplow", "critical";
+ #thermal-sensor-cells = <1>;
+ };
+
+ tsens1: thermal-sensor@c265000 {
+ compatible = "qcom,sa8775p-tsens", "qcom,tsens-v2";
+ reg = <0x0 0x0c265000 0x0 0x1ff>,
+ <0x0 0x0c223000 0x0 0x8>;
+ interrupts = <GIC_SPI 507 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 509 IRQ_TYPE_LEVEL_HIGH>;
+ #qcom,sensors = <12>;
+ interrupt-names = "uplow", "critical";
+ #thermal-sensor-cells = <1>;
+ };
+
aoss_qmp: power-management@c300000 {
compatible = "qcom,sa8775p-aoss-qmp", "qcom,aoss-qmp";
reg = <0x0 0x0c300000 0x0 0x400>;
@@ -1920,6 +1969,11 @@
#clock-cells = <0>;
};
+ sram@c3f0000 {
+ compatible = "qcom,rpmh-stats";
+ reg = <0x0 0x0c3f0000 0x0 0x400>;
+ };
+
spmi_bus: spmi@c440000 {
compatible = "qcom,spmi-pmic-arb";
reg = <0x0 0x0c440000 0x0 0x1100>,
@@ -2181,7 +2235,7 @@
compatible = "qcom,apss-wdt-sa8775p", "qcom,kpss-wdt";
reg = <0x0 0x17c10000 0x0 0x1000>;
clocks = <&sleep_clk>;
- interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>;
+ interrupts = <GIC_SPI 0 IRQ_TYPE_EDGE_RISING>;
};
memtimer: timer@17c20000 {
@@ -2401,6 +2455,1058 @@
};
};
+ thermal-zones {
+ aoss-0-thermal {
+ polling-delay-passive = <0>;
+ polling-delay = <0>;
+
+ thermal-sensors = <&tsens0 0>;
+
+ trips {
+ trip-point0 {
+ temperature = <105000>;
+ hysteresis = <5000>;
+ type = "passive";
+ };
+
+ trip-point1 {
+ temperature = <115000>;
+ hysteresis = <5000>;
+ type = "passive";
+ };
+ };
+ };
+
+ cpu-0-0-0-thermal {
+ polling-delay-passive = <10>;
+ polling-delay = <0>;
+
+ thermal-sensors = <&tsens0 1>;
+
+ trips {
+ trip-point0 {
+ temperature = <105000>;
+ hysteresis = <5000>;
+ type = "passive";
+ };
+
+ trip-point1 {
+ temperature = <115000>;
+ hysteresis = <5000>;
+ type = "passive";
+ };
+ };
+ };
+
+ cpu-0-1-0-thermal {
+ polling-delay-passive = <10>;
+ polling-delay = <0>;
+
+ thermal-sensors = <&tsens0 2>;
+
+ trips {
+ trip-point0 {
+ temperature = <105000>;
+ hysteresis = <5000>;
+ type = "passive";
+ };
+
+ trip-point1 {
+ temperature = <115000>;
+ hysteresis = <5000>;
+ type = "passive";
+ };
+ };
+ };
+
+ cpu-0-2-0-thermal {
+ polling-delay-passive = <10>;
+ polling-delay = <0>;
+
+ thermal-sensors = <&tsens0 3>;
+
+ trips {
+ trip-point0 {
+ temperature = <105000>;
+ hysteresis = <5000>;
+ type = "passive";
+ };
+
+ trip-point1 {
+ temperature = <115000>;
+ hysteresis = <5000>;
+ type = "passive";
+ };
+ };
+ };
+
+ cpu-0-3-0-thermal {
+ polling-delay-passive = <10>;
+ polling-delay = <0>;
+
+ thermal-sensors = <&tsens0 4>;
+
+ trips {
+ trip-point0 {
+ temperature = <105000>;
+ hysteresis = <5000>;
+ type = "passive";
+ };
+
+ trip-point1 {
+ temperature = <115000>;
+ hysteresis = <5000>;
+ type = "passive";
+ };
+ };
+ };
+
+ gpuss-0-thermal {
+ polling-delay-passive = <10>;
+ polling-delay = <0>;
+
+ thermal-sensors = <&tsens0 5>;
+
+ trips {
+ trip-point0 {
+ temperature = <105000>;
+ hysteresis = <5000>;
+ type = "passive";
+ };
+
+ trip-point1 {
+ temperature = <115000>;
+ hysteresis = <5000>;
+ type = "passive";
+ };
+ };
+ };
+
+ gpuss-1-thermal {
+ polling-delay-passive = <10>;
+ polling-delay = <0>;
+
+ thermal-sensors = <&tsens0 6>;
+
+ trips {
+ trip-point0 {
+ temperature = <105000>;
+ hysteresis = <5000>;
+ type = "passive";
+ };
+
+ trip-point1 {
+ temperature = <115000>;
+ hysteresis = <5000>;
+ type = "passive";
+ };
+ };
+ };
+
+ gpuss-2-thermal {
+ polling-delay-passive = <10>;
+ polling-delay = <0>;
+
+ thermal-sensors = <&tsens0 7>;
+
+ trips {
+ trip-point0 {
+ temperature = <105000>;
+ hysteresis = <5000>;
+ type = "passive";
+ };
+
+ trip-point1 {
+ temperature = <115000>;
+ hysteresis = <5000>;
+ type = "passive";
+ };
+ };
+ };
+
+ audio-thermal {
+ polling-delay-passive = <0>;
+ polling-delay = <0>;
+
+ thermal-sensors = <&tsens0 8>;
+
+ trips {
+ trip-point0 {
+ temperature = <105000>;
+ hysteresis = <5000>;
+ type = "passive";
+ };
+
+ trip-point1 {
+ temperature = <115000>;
+ hysteresis = <5000>;
+ type = "passive";
+ };
+ };
+ };
+
+ camss-0-thermal {
+ polling-delay-passive = <0>;
+ polling-delay = <0>;
+
+ thermal-sensors = <&tsens0 9>;
+
+ trips {
+ trip-point0 {
+ temperature = <105000>;
+ hysteresis = <5000>;
+ type = "passive";
+ };
+
+ trip-point1 {
+ temperature = <115000>;
+ hysteresis = <5000>;
+ type = "passive";
+ };
+ };
+ };
+
+ pcie-0-thermal {
+ polling-delay-passive = <0>;
+ polling-delay = <0>;
+
+ thermal-sensors = <&tsens0 10>;
+
+ trips {
+ trip-point0 {
+ temperature = <105000>;
+ hysteresis = <5000>;
+ type = "passive";
+ };
+
+ trip-point1 {
+ temperature = <115000>;
+ hysteresis = <5000>;
+ type = "passive";
+ };
+ };
+ };
+
+ cpuss-0-0-thermal {
+ polling-delay-passive = <0>;
+ polling-delay = <0>;
+
+ thermal-sensors = <&tsens0 11>;
+
+ trips {
+ trip-point0 {
+ temperature = <105000>;
+ hysteresis = <5000>;
+ type = "passive";
+ };
+
+ trip-point1 {
+ temperature = <115000>;
+ hysteresis = <5000>;
+ type = "passive";
+ };
+ };
+ };
+
+ aoss-1-thermal {
+ polling-delay-passive = <0>;
+ polling-delay = <0>;
+
+ thermal-sensors = <&tsens1 0>;
+
+ trips {
+ trip-point0 {
+ temperature = <105000>;
+ hysteresis = <5000>;
+ type = "passive";
+ };
+
+ trip-point1 {
+ temperature = <115000>;
+ hysteresis = <5000>;
+ type = "passive";
+ };
+ };
+ };
+
+ cpu-0-0-1-thermal {
+ polling-delay-passive = <10>;
+ polling-delay = <0>;
+
+ thermal-sensors = <&tsens1 1>;
+
+ trips {
+ trip-point0 {
+ temperature = <105000>;
+ hysteresis = <5000>;
+ type = "passive";
+ };
+
+ trip-point1 {
+ temperature = <115000>;
+ hysteresis = <5000>;
+ type = "passive";
+ };
+ };
+ };
+
+ cpu-0-1-1-thermal {
+ polling-delay-passive = <10>;
+ polling-delay = <0>;
+
+ thermal-sensors = <&tsens1 2>;
+
+ trips {
+ trip-point0 {
+ temperature = <105000>;
+ hysteresis = <5000>;
+ type = "passive";
+ };
+
+ trip-point1 {
+ temperature = <115000>;
+ hysteresis = <5000>;
+ type = "passive";
+ };
+ };
+ };
+
+ cpu-0-2-1-thermal {
+ polling-delay-passive = <10>;
+ polling-delay = <0>;
+
+ thermal-sensors = <&tsens1 3>;
+
+ trips {
+ trip-point0 {
+ temperature = <105000>;
+ hysteresis = <5000>;
+ type = "passive";
+ };
+
+ trip-point1 {
+ temperature = <115000>;
+ hysteresis = <5000>;
+ type = "passive";
+ };
+ };
+ };
+
+ cpu-0-3-1-thermal {
+ polling-delay-passive = <10>;
+ polling-delay = <0>;
+
+ thermal-sensors = <&tsens1 4>;
+
+ trips {
+ trip-point0 {
+ temperature = <105000>;
+ hysteresis = <5000>;
+ type = "passive";
+ };
+
+ trip-point1 {
+ temperature = <115000>;
+ hysteresis = <5000>;
+ type = "passive";
+ };
+ };
+ };
+
+ gpuss-3-thermal {
+ polling-delay-passive = <10>;
+ polling-delay = <0>;
+
+ thermal-sensors = <&tsens1 5>;
+
+ trips {
+ trip-point0 {
+ temperature = <105000>;
+ hysteresis = <5000>;
+ type = "passive";
+ };
+
+ trip-point1 {
+ temperature = <115000>;
+ hysteresis = <5000>;
+ type = "passive";
+ };
+ };
+ };
+
+ gpuss-4-thermal {
+ polling-delay-passive = <10>;
+ polling-delay = <0>;
+
+ thermal-sensors = <&tsens1 6>;
+
+ trips {
+ trip-point0 {
+ temperature = <105000>;
+ hysteresis = <5000>;
+ type = "passive";
+ };
+
+ trip-point1 {
+ temperature = <115000>;
+ hysteresis = <5000>;
+ type = "passive";
+ };
+ };
+ };
+
+ gpuss-5-thermal {
+ polling-delay-passive = <10>;
+ polling-delay = <0>;
+
+ thermal-sensors = <&tsens1 7>;
+
+ trips {
+ trip-point0 {
+ temperature = <105000>;
+ hysteresis = <5000>;
+ type = "passive";
+ };
+
+ trip-point1 {
+ temperature = <115000>;
+ hysteresis = <5000>;
+ type = "passive";
+ };
+ };
+ };
+
+ video-thermal {
+ polling-delay-passive = <0>;
+ polling-delay = <0>;
+
+ thermal-sensors = <&tsens1 8>;
+
+ trips {
+ trip-point0 {
+ temperature = <105000>;
+ hysteresis = <5000>;
+ type = "passive";
+ };
+
+ trip-point1 {
+ temperature = <115000>;
+ hysteresis = <5000>;
+ type = "passive";
+ };
+ };
+ };
+
+ camss-1-thermal {
+ polling-delay-passive = <0>;
+ polling-delay = <0>;
+
+ thermal-sensors = <&tsens1 9>;
+
+ trips {
+ trip-point0 {
+ temperature = <105000>;
+ hysteresis = <5000>;
+ type = "passive";
+ };
+
+ trip-point1 {
+ temperature = <115000>;
+ hysteresis = <5000>;
+ type = "passive";
+ };
+ };
+ };
+
+ pcie-1-thermal {
+ polling-delay-passive = <0>;
+ polling-delay = <0>;
+
+ thermal-sensors = <&tsens1 10>;
+
+ trips {
+ trip-point0 {
+ temperature = <105000>;
+ hysteresis = <5000>;
+ type = "passive";
+ };
+
+ trip-point1 {
+ temperature = <115000>;
+ hysteresis = <5000>;
+ type = "passive";
+ };
+ };
+ };
+
+ cpuss-0-1-thermal {
+ polling-delay-passive = <0>;
+ polling-delay = <0>;
+
+ thermal-sensors = <&tsens1 11>;
+
+ trips {
+ trip-point0 {
+ temperature = <105000>;
+ hysteresis = <5000>;
+ type = "passive";
+ };
+
+ trip-point1 {
+ temperature = <115000>;
+ hysteresis = <5000>;
+ type = "passive";
+ };
+ };
+ };
+
+ aoss-2-thermal {
+ polling-delay-passive = <0>;
+ polling-delay = <0>;
+
+ thermal-sensors = <&tsens2 0>;
+
+ trips {
+ trip-point0 {
+ temperature = <105000>;
+ hysteresis = <5000>;
+ type = "passive";
+ };
+
+ trip-point1 {
+ temperature = <115000>;
+ hysteresis = <5000>;
+ type = "passive";
+ };
+ };
+ };
+
+ cpu-1-0-0-thermal {
+ polling-delay-passive = <10>;
+ polling-delay = <0>;
+
+ thermal-sensors = <&tsens2 1>;
+
+ trips {
+ trip-point0 {
+ temperature = <105000>;
+ hysteresis = <5000>;
+ type = "passive";
+ };
+
+ trip-point1 {
+ temperature = <115000>;
+ hysteresis = <5000>;
+ type = "passive";
+ };
+ };
+ };
+
+ cpu-1-1-0-thermal {
+ polling-delay-passive = <10>;
+ polling-delay = <0>;
+
+ thermal-sensors = <&tsens2 2>;
+
+ trips {
+ trip-point0 {
+ temperature = <105000>;
+ hysteresis = <5000>;
+ type = "passive";
+ };
+
+ trip-point1 {
+ temperature = <115000>;
+ hysteresis = <5000>;
+ type = "passive";
+ };
+ };
+ };
+
+ cpu-1-2-0-thermal {
+ polling-delay-passive = <10>;
+ polling-delay = <0>;
+
+ thermal-sensors = <&tsens2 3>;
+
+ trips {
+ trip-point0 {
+ temperature = <105000>;
+ hysteresis = <5000>;
+ type = "passive";
+ };
+
+ trip-point1 {
+ temperature = <115000>;
+ hysteresis = <5000>;
+ type = "passive";
+ };
+ };
+ };
+
+ cpu-1-3-0-thermal {
+ polling-delay-passive = <10>;
+ polling-delay = <0>;
+
+ thermal-sensors = <&tsens2 4>;
+
+ trips {
+ trip-point0 {
+ temperature = <105000>;
+ hysteresis = <5000>;
+ type = "passive";
+ };
+
+ trip-point1 {
+ temperature = <115000>;
+ hysteresis = <5000>;
+ type = "passive";
+ };
+ };
+ };
+
+ nsp-0-0-0-thermal {
+ polling-delay-passive = <10>;
+ polling-delay = <0>;
+
+ thermal-sensors = <&tsens2 5>;
+
+ trips {
+ trip-point0 {
+ temperature = <105000>;
+ hysteresis = <5000>;
+ type = "passive";
+ };
+
+ trip-point1 {
+ temperature = <115000>;
+ hysteresis = <5000>;
+ type = "passive";
+ };
+ };
+ };
+
+ nsp-0-1-0-thermal {
+ polling-delay-passive = <10>;
+ polling-delay = <0>;
+
+ thermal-sensors = <&tsens2 6>;
+
+ trips {
+ trip-point0 {
+ temperature = <105000>;
+ hysteresis = <5000>;
+ type = "passive";
+ };
+
+ trip-point1 {
+ temperature = <115000>;
+ hysteresis = <5000>;
+ type = "passive";
+ };
+ };
+ };
+
+ nsp-0-2-0-thermal {
+ polling-delay-passive = <10>;
+ polling-delay = <0>;
+
+ thermal-sensors = <&tsens2 7>;
+
+ trips {
+ trip-point0 {
+ temperature = <105000>;
+ hysteresis = <5000>;
+ type = "passive";
+ };
+
+ trip-point1 {
+ temperature = <115000>;
+ hysteresis = <5000>;
+ type = "passive";
+ };
+ };
+ };
+
+ nsp-1-0-0-thermal {
+ polling-delay-passive = <10>;
+ polling-delay = <0>;
+
+ thermal-sensors = <&tsens2 8>;
+
+ trips {
+ trip-point0 {
+ temperature = <105000>;
+ hysteresis = <5000>;
+ type = "passive";
+ };
+
+ trip-point1 {
+ temperature = <115000>;
+ hysteresis = <5000>;
+ type = "passive";
+ };
+ };
+ };
+
+ nsp-1-1-0-thermal {
+ polling-delay-passive = <10>;
+ polling-delay = <0>;
+
+ thermal-sensors = <&tsens2 9>;
+
+ trips {
+ trip-point0 {
+ temperature = <105000>;
+ hysteresis = <5000>;
+ type = "passive";
+ };
+
+ trip-point1 {
+ temperature = <115000>;
+ hysteresis = <5000>;
+ type = "passive";
+ };
+ };
+ };
+
+ nsp-1-2-0-thermal {
+ polling-delay-passive = <10>;
+ polling-delay = <0>;
+
+ thermal-sensors = <&tsens2 10>;
+
+ trips {
+ trip-point0 {
+ temperature = <105000>;
+ hysteresis = <5000>;
+ type = "passive";
+ };
+
+ trip-point1 {
+ temperature = <115000>;
+ hysteresis = <5000>;
+ type = "passive";
+ };
+ };
+ };
+
+ ddrss-0-thermal {
+ polling-delay-passive = <0>;
+ polling-delay = <0>;
+
+ thermal-sensors = <&tsens2 11>;
+
+ trips {
+ trip-point0 {
+ temperature = <105000>;
+ hysteresis = <5000>;
+ type = "passive";
+ };
+
+ trip-point1 {
+ temperature = <115000>;
+ hysteresis = <5000>;
+ type = "passive";
+ };
+ };
+ };
+
+ cpuss-1-0-thermal {
+ polling-delay-passive = <0>;
+ polling-delay = <0>;
+
+ thermal-sensors = <&tsens2 12>;
+
+ trips {
+ trip-point0 {
+ temperature = <105000>;
+ hysteresis = <5000>;
+ type = "passive";
+ };
+
+ trip-point1 {
+ temperature = <115000>;
+ hysteresis = <5000>;
+ type = "passive";
+ };
+ };
+ };
+
+ aoss-3-thermal {
+ polling-delay-passive = <0>;
+ polling-delay = <0>;
+
+ thermal-sensors = <&tsens3 0>;
+
+ trips {
+ trip-point0 {
+ temperature = <105000>;
+ hysteresis = <5000>;
+ type = "passive";
+ };
+
+ trip-point1 {
+ temperature = <115000>;
+ hysteresis = <5000>;
+ type = "passive";
+ };
+ };
+ };
+
+ cpu-1-0-1-thermal {
+ polling-delay-passive = <10>;
+ polling-delay = <0>;
+
+ thermal-sensors = <&tsens3 1>;
+
+ trips {
+ trip-point0 {
+ temperature = <105000>;
+ hysteresis = <5000>;
+ type = "passive";
+ };
+
+ trip-point1 {
+ temperature = <115000>;
+ hysteresis = <5000>;
+ type = "passive";
+ };
+ };
+ };
+
+ cpu-1-1-1-thermal {
+ polling-delay-passive = <10>;
+ polling-delay = <0>;
+
+ thermal-sensors = <&tsens3 2>;
+
+ trips {
+ trip-point0 {
+ temperature = <105000>;
+ hysteresis = <5000>;
+ type = "passive";
+ };
+
+ trip-point1 {
+ temperature = <115000>;
+ hysteresis = <5000>;
+ type = "passive";
+ };
+ };
+ };
+
+ cpu-1-2-1-thermal {
+ polling-delay-passive = <10>;
+ polling-delay = <0>;
+
+ thermal-sensors = <&tsens3 3>;
+
+ trips {
+ trip-point0 {
+ temperature = <105000>;
+ hysteresis = <5000>;
+ type = "passive";
+ };
+
+ trip-point1 {
+ temperature = <115000>;
+ hysteresis = <5000>;
+ type = "passive";
+ };
+ };
+ };
+
+ cpu-1-3-1-thermal {
+ polling-delay-passive = <10>;
+ polling-delay = <0>;
+
+ thermal-sensors = <&tsens3 4>;
+
+ trips {
+ trip-point0 {
+ temperature = <105000>;
+ hysteresis = <5000>;
+ type = "passive";
+ };
+
+ trip-point1 {
+ temperature = <115000>;
+ hysteresis = <5000>;
+ type = "passive";
+ };
+ };
+ };
+
+ nsp-0-0-1-thermal {
+ polling-delay-passive = <10>;
+ polling-delay = <0>;
+
+ thermal-sensors = <&tsens3 5>;
+
+ trips {
+ trip-point0 {
+ temperature = <105000>;
+ hysteresis = <5000>;
+ type = "passive";
+ };
+
+ trip-point1 {
+ temperature = <115000>;
+ hysteresis = <5000>;
+ type = "passive";
+ };
+ };
+ };
+
+ nsp-0-1-1-thermal {
+ polling-delay-passive = <10>;
+ polling-delay = <0>;
+
+ thermal-sensors = <&tsens3 6>;
+
+ trips {
+ trip-point0 {
+ temperature = <105000>;
+ hysteresis = <5000>;
+ type = "passive";
+ };
+
+ trip-point1 {
+ temperature = <115000>;
+ hysteresis = <5000>;
+ type = "passive";
+ };
+ };
+ };
+
+ nsp-0-2-1-thermal {
+ polling-delay-passive = <10>;
+ polling-delay = <0>;
+
+ thermal-sensors = <&tsens3 7>;
+
+ trips {
+ trip-point0 {
+ temperature = <105000>;
+ hysteresis = <5000>;
+ type = "passive";
+ };
+
+ trip-point1 {
+ temperature = <115000>;
+ hysteresis = <5000>;
+ type = "passive";
+ };
+ };
+ };
+
+ nsp-1-0-1-thermal {
+ polling-delay-passive = <10>;
+ polling-delay = <0>;
+
+ thermal-sensors = <&tsens3 8>;
+
+ trips {
+ trip-point0 {
+ temperature = <105000>;
+ hysteresis = <5000>;
+ type = "passive";
+ };
+
+ trip-point1 {
+ temperature = <115000>;
+ hysteresis = <5000>;
+ type = "passive";
+ };
+ };
+ };
+
+ nsp-1-1-1-thermal {
+ polling-delay-passive = <10>;
+ polling-delay = <0>;
+
+ thermal-sensors = <&tsens3 9>;
+
+ trips {
+ trip-point0 {
+ temperature = <105000>;
+ hysteresis = <5000>;
+ type = "passive";
+ };
+
+ trip-point1 {
+ temperature = <115000>;
+ hysteresis = <5000>;
+ type = "passive";
+ };
+ };
+ };
+
+ nsp-1-2-1-thermal {
+ polling-delay-passive = <10>;
+ polling-delay = <0>;
+
+ thermal-sensors = <&tsens3 10>;
+
+ trips {
+ trip-point0 {
+ temperature = <105000>;
+ hysteresis = <5000>;
+ type = "passive";
+ };
+
+ trip-point1 {
+ temperature = <115000>;
+ hysteresis = <5000>;
+ type = "passive";
+ };
+ };
+ };
+
+ ddrss-1-thermal {
+ polling-delay-passive = <0>;
+ polling-delay = <0>;
+
+ thermal-sensors = <&tsens3 11>;
+
+ trips {
+ trip-point0 {
+ temperature = <105000>;
+ hysteresis = <5000>;
+ type = "passive";
+ };
+
+ trip-point1 {
+ temperature = <115000>;
+ hysteresis = <5000>;
+ type = "passive";
+ };
+ };
+ };
+
+ cpuss-1-1-thermal {
+ polling-delay-passive = <0>;
+ polling-delay = <0>;
+
+ thermal-sensors = <&tsens3 12>;
+
+ trips {
+ trip-point0 {
+ temperature = <105000>;
+ hysteresis = <5000>;
+ type = "passive";
+ };
+
+ trip-point1 {
+ temperature = <115000>;
+ hysteresis = <5000>;
+ type = "passive";
+ };
+ };
+ };
+ };
+
arch_timer: timer {
compatible = "arm,armv8-timer";
interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
@@ -2409,7 +3515,7 @@
<GIC_PPI 12 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>;
};
- pcie0: pci@1c00000{
+ pcie0: pcie@1c00000 {
compatible = "qcom,pcie-sa8775p";
reg = <0x0 0x01c00000 0x0 0x3000>,
<0x0 0x40000000 0x0 0xf20>,
@@ -2509,7 +3615,7 @@
status = "disabled";
};
- pcie1: pci@1c10000{
+ pcie1: pcie@1c10000 {
compatible = "qcom,pcie-sa8775p";
reg = <0x0 0x01c10000 0x0 0x3000>,
<0x0 0x60000000 0x0 0xf20>,
diff --git a/dts/upstream/src/arm64/qcom/sc7180-acer-aspire1.dts b/dts/upstream/src/arm64/qcom/sc7180-acer-aspire1.dts
index dbb4893..5afcb82 100644
--- a/dts/upstream/src/arm64/qcom/sc7180-acer-aspire1.dts
+++ b/dts/upstream/src/arm64/qcom/sc7180-acer-aspire1.dts
@@ -3,6 +3,7 @@
/dts-v1/;
#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/sound/qcom,q6asm.h>
#include <dt-bindings/regulator/qcom,rpmh-regulator.h>
#include "sc7180.dtsi"
@@ -129,6 +130,113 @@
pinctrl-names = "default";
};
+ sound: sound {
+ compatible = "qcom,sc7180-qdsp6-sndcard";
+ pinctrl-0 = <&pri_mi2s_active>, <&pri_mi2s_mclk_active>, <&ter_mi2s_active>;
+ pinctrl-names = "default";
+ model = "Acer-Aspire-1";
+
+ audio-routing =
+ "Headphone Jack", "HPOL",
+ "Headphone Jack", "HPOR";
+
+ multimedia1-dai-link {
+ link-name = "MultiMedia1";
+
+ cpu {
+ sound-dai = <&q6asmdai MSM_FRONTEND_DAI_MULTIMEDIA1>;
+ };
+ };
+
+ multimedia2-dai-link {
+ link-name = "MultiMedia2";
+
+ cpu {
+ sound-dai = <&q6asmdai MSM_FRONTEND_DAI_MULTIMEDIA2>;
+ };
+ };
+
+ multimedia3-dai-link {
+ link-name = "MultiMedia3";
+
+ cpu {
+ sound-dai = <&q6asmdai MSM_FRONTEND_DAI_MULTIMEDIA3>;
+ };
+ };
+
+ multimedia4-dai-link {
+ link-name = "MultiMedia4";
+
+ cpu {
+ sound-dai = <&q6asmdai MSM_FRONTEND_DAI_MULTIMEDIA4>;
+ };
+ };
+
+ primary-rx-dai-link {
+ link-name = "Primary MI2S Playback";
+
+ cpu {
+ sound-dai = <&q6afedai PRIMARY_MI2S_RX>;
+ };
+
+ platform {
+ sound-dai = <&q6routing>;
+ };
+
+ codec {
+ sound-dai = <&alc5682 0>;
+ };
+ };
+
+ primary-tx-dai-link {
+ link-name = "Primary MI2S Capture";
+
+ cpu {
+ sound-dai = <&q6afedai PRIMARY_MI2S_TX>;
+ };
+
+ platform {
+ sound-dai = <&q6routing>;
+ };
+
+ codec {
+ sound-dai = <&alc5682 0>;
+ };
+ };
+
+ tertiary-rx-dai-link {
+ link-name = "Tertiary MI2S Playback";
+
+ cpu {
+ sound-dai = <&q6afedai TERTIARY_MI2S_RX>;
+ };
+
+ platform {
+ sound-dai = <&q6routing>;
+ };
+
+ codec {
+ sound-dai = <&max98357a>;
+ };
+ };
+
+ displayport-rx-dai-link {
+ link-name = "DisplayPort Playback";
+
+ cpu {
+ sound-dai = <&q6afedai DISPLAY_PORT_RX>;
+ };
+
+ platform {
+ sound-dai = <&q6routing>;
+ };
+
+ codec {
+ sound-dai = <&mdss_dp>;
+ };
+ };
+ };
+
reg_tp_3p3: touchpad-regulator {
compatible = "regulator-fixed";
regulator-name = "tp_3p3";
@@ -209,9 +317,22 @@
AVDD-supply = <&vreg_l15a_1p8>;
MICVDD-supply = <®_codec_3p3>;
VBAT-supply = <®_codec_3p3>;
+ DBVDD-supply = <&vreg_l15a_1p8>;
+ LDO1-IN-supply = <&vreg_l15a_1p8>;
- realtek,dmic1-data-pin = <1>;
- realtek,dmic1-clk-pin = <1>;
+ /*
+ * NOTE: The board has a path from this codec to the
+ * DMIC microphones in the lid, however some of the option
+ * resistors are absent and the microphones are connected
+ * to the SoC instead.
+ *
+ * If the resistors were to be changed by the user to
+ * connect the codec, the following could be used:
+ *
+ * realtek,dmic1-data-pin = <1>;
+ * realtek,dmic1-clk-pin = <1>;
+ */
+
realtek,jd-src = <1>;
};
};
@@ -351,6 +472,49 @@
status = "disabled";
};
+&pm6150_rtc {
+ status = "okay";
+};
+
+&q6afedai {
+ dai@16 {
+ reg = <PRIMARY_MI2S_RX>;
+ qcom,sd-lines = <1>;
+ };
+
+ dai@17 {
+ reg = <PRIMARY_MI2S_TX>;
+ qcom,sd-lines = <0>;
+ };
+
+ dai@20 {
+ reg = <TERTIARY_MI2S_RX>;
+ qcom,sd-lines = <0>;
+ };
+
+ dai@104 {
+ reg = <DISPLAY_PORT_RX>;
+ };
+};
+
+&q6asmdai {
+ dai@0 {
+ reg = <0>;
+ };
+
+ dai@1 {
+ reg = <1>;
+ };
+
+ dai@2 {
+ reg = <2>;
+ };
+
+ dai@3 {
+ reg = <3>;
+ };
+};
+
&qupv3_id_0 {
status = "okay";
};
@@ -359,6 +523,12 @@
status = "okay";
};
+&remoteproc_adsp {
+ memory-region = <&adsp_mem>;
+ firmware-name = "qcom/sc7180/acer/aspire1/qcadsp7180.mbn";
+ status = "okay";
+};
+
&remoteproc_mpss {
firmware-name = "qcom/sc7180/acer/aspire1/qcmpss7180_nm.mbn";
status = "okay";
diff --git a/dts/upstream/src/arm64/qcom/sc7180-trogdor-pompom.dtsi b/dts/upstream/src/arm64/qcom/sc7180-trogdor-pompom.dtsi
index 0be6233..067813f 100644
--- a/dts/upstream/src/arm64/qcom/sc7180-trogdor-pompom.dtsi
+++ b/dts/upstream/src/arm64/qcom/sc7180-trogdor-pompom.dtsi
@@ -141,7 +141,7 @@
};
&panel {
- compatible = "kingdisplay,kd116n21-30nv-a010";
+ compatible = "edp-panel";
};
&pen_insert {
diff --git a/dts/upstream/src/arm64/qcom/sc7180.dtsi b/dts/upstream/src/arm64/qcom/sc7180.dtsi
index 11f353d..4dcaa15 100644
--- a/dts/upstream/src/arm64/qcom/sc7180.dtsi
+++ b/dts/upstream/src/arm64/qcom/sc7180.dtsi
@@ -2966,8 +2966,8 @@
interrupts-extended = <&intc GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>,
<&pdc 6 IRQ_TYPE_LEVEL_HIGH>,
- <&pdc 8 IRQ_TYPE_LEVEL_HIGH>,
- <&pdc 9 IRQ_TYPE_LEVEL_HIGH>;
+ <&pdc 8 IRQ_TYPE_EDGE_BOTH>,
+ <&pdc 9 IRQ_TYPE_EDGE_BOTH>;
interrupt-names = "hs_phy_irq", "ss_phy_irq",
"dm_hs_phy_irq", "dp_hs_phy_irq";
@@ -3100,8 +3100,12 @@
interrupt-controller;
#interrupt-cells = <1>;
- interconnects = <&mmss_noc MASTER_MDP0 0 &mc_virt SLAVE_EBI1 0>;
- interconnect-names = "mdp0-mem";
+ interconnects = <&mmss_noc MASTER_MDP0 QCOM_ICC_TAG_ALWAYS
+ &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>,
+ <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
+ &config_noc SLAVE_DISPLAY_CFG QCOM_ICC_TAG_ALWAYS>;
+ interconnect-names = "mdp0-mem",
+ "cpu-cfg";
iommus = <&apps_smmu 0x800 0x2>;
@@ -3576,7 +3580,7 @@
compatible = "qcom,apss-wdt-sc7180", "qcom,kpss-wdt";
reg = <0 0x17c10000 0 0x1000>;
clocks = <&sleep_clk>;
- interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>;
+ interrupts = <GIC_SPI 0 IRQ_TYPE_EDGE_RISING>;
};
timer@17c20000 {
diff --git a/dts/upstream/src/arm64/qcom/sc7280-chrome-common.dtsi b/dts/upstream/src/arm64/qcom/sc7280-chrome-common.dtsi
index 5d462ae..c4d00a8 100644
--- a/dts/upstream/src/arm64/qcom/sc7280-chrome-common.dtsi
+++ b/dts/upstream/src/arm64/qcom/sc7280-chrome-common.dtsi
@@ -17,6 +17,9 @@
* required by the setup for Chrome boards.
*/
+/delete-node/ &cdsp_mem;
+/delete-node/ &gpu_zap_mem;
+/delete-node/ &gpu_zap_shader;
/delete-node/ &hyp_mem;
/delete-node/ &xbl_mem;
/delete-node/ &reserved_xbl_uefi_log;
@@ -24,11 +27,6 @@
/ {
reserved-memory {
- adsp_mem: memory@86700000 {
- reg = <0x0 0x86700000 0x0 0x2800000>;
- no-map;
- };
-
camera_mem: memory@8ad00000 {
reg = <0x0 0x8ad00000 0x0 0x500000>;
no-map;
@@ -38,11 +36,6 @@
reg = <0x0 0x8b200000 0x0 0x500000>;
no-map;
};
-
- wpss_mem: memory@9ae00000 {
- reg = <0x0 0x9ae00000 0x0 0x1900000>;
- no-map;
- };
};
};
@@ -94,9 +87,31 @@
};
};
+/* Currently not used */
+&remoteproc_cdsp {
+ /delete-property/ memory-region;
+};
+
&remoteproc_wpss {
- status = "okay";
+ compatible = "qcom,sc7280-wpss-pil";
+ clocks = <&gcc GCC_WPSS_AHB_BDG_MST_CLK>,
+ <&gcc GCC_WPSS_AHB_CLK>,
+ <&gcc GCC_WPSS_RSCP_CLK>,
+ <&rpmhcc RPMH_CXO_CLK>;
+ clock-names = "ahb_bdg",
+ "ahb",
+ "rscp",
+ "xo";
+
+ resets = <&aoss_reset AOSS_CC_WCSS_RESTART>,
+ <&pdc_reset PDC_WPSS_SYNC_RESET>;
+ reset-names = "restart", "pdc_sync";
+
+ qcom,halt-regs = <&tcsr_1 0x17000>;
+
firmware-name = "ath11k/WCN6750/hw1.0/wpss.mdt";
+
+ status = "okay";
};
&scm {
diff --git a/dts/upstream/src/arm64/qcom/sc7280-herobrine-lte-sku.dtsi b/dts/upstream/src/arm64/qcom/sc7280-herobrine-lte-sku.dtsi
index 9550554..b721a85 100644
--- a/dts/upstream/src/arm64/qcom/sc7280-herobrine-lte-sku.dtsi
+++ b/dts/upstream/src/arm64/qcom/sc7280-herobrine-lte-sku.dtsi
@@ -8,11 +8,6 @@
/ {
reserved-memory {
- mpss_mem: memory@8b800000 {
- reg = <0x0 0x8b800000 0x0 0xf600000>;
- no-map;
- };
-
mba_mem: memory@9c700000 {
reg = <0x0 0x9c700000 0x0 0x200000>;
no-map;
@@ -33,6 +28,8 @@
&remoteproc_mpss {
compatible = "qcom,sc7280-mss-pil";
+ reg = <0 0x04080000 0 0x10000>, <0 0x04180000 0 0x48>;
+ reg-names = "qdsp6", "rmb";
clocks = <&gcc GCC_MSS_CFG_AHB_CLK>,
<&gcc GCC_MSS_OFFLINE_AXI_CLK>,
diff --git a/dts/upstream/src/arm64/qcom/sc7280-herobrine-wifi-sku.dtsi b/dts/upstream/src/arm64/qcom/sc7280-herobrine-wifi-sku.dtsi
index 2febd61..3ebc915 100644
--- a/dts/upstream/src/arm64/qcom/sc7280-herobrine-wifi-sku.dtsi
+++ b/dts/upstream/src/arm64/qcom/sc7280-herobrine-wifi-sku.dtsi
@@ -7,5 +7,6 @@
/* WIFI SKUs save 256M by not having modem/mba/rmtfs memory regions defined. */
+/delete-node/ &mpss_mem;
/delete-node/ &remoteproc_mpss;
/delete-node/ &rmtfs_mem;
diff --git a/dts/upstream/src/arm64/qcom/sc7280-idp.dtsi b/dts/upstream/src/arm64/qcom/sc7280-idp.dtsi
index 2ff549f..a005952 100644
--- a/dts/upstream/src/arm64/qcom/sc7280-idp.dtsi
+++ b/dts/upstream/src/arm64/qcom/sc7280-idp.dtsi
@@ -499,6 +499,25 @@
status = "okay";
};
+&ufs_mem_hc {
+ reset-gpios = <&tlmm 175 GPIO_ACTIVE_LOW>;
+ vcc-supply = <&vreg_l7b_2p9>;
+ vcc-max-microamp = <800000>;
+ vccq-supply = <&vreg_l9b_1p2>;
+ vccq-max-microamp = <900000>;
+ vccq2-supply = <&vreg_l9b_1p2>;
+ vccq2-max-microamp = <900000>;
+
+ status = "okay";
+};
+
+&ufs_mem_phy {
+ vdda-phy-supply = <&vreg_l10c_0p8>;
+ vdda-pll-supply = <&vreg_l6b_1p2>;
+
+ status = "okay";
+};
+
&usb_1 {
status = "okay";
};
diff --git a/dts/upstream/src/arm64/qcom/sc7280.dtsi b/dts/upstream/src/arm64/qcom/sc7280.dtsi
index 66f1eb8..83b5b76 100644
--- a/dts/upstream/src/arm64/qcom/sc7280.dtsi
+++ b/dts/upstream/src/arm64/qcom/sc7280.dtsi
@@ -15,6 +15,7 @@
#include <dt-bindings/dma/qcom-gpi.h>
#include <dt-bindings/firmware/qcom,scm.h>
#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/interconnect/qcom,icc.h>
#include <dt-bindings/interconnect/qcom,osm-l3.h>
#include <dt-bindings/interconnect/qcom,sc7280.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
@@ -91,68 +92,93 @@
#size-cells = <2>;
ranges;
- wlan_ce_mem: memory@4cd000 {
+ wlan_ce_mem: wlan-ce@4cd000 {
no-map;
reg = <0x0 0x004cd000 0x0 0x1000>;
};
- hyp_mem: memory@80000000 {
+ hyp_mem: hyp@80000000 {
reg = <0x0 0x80000000 0x0 0x600000>;
no-map;
};
- xbl_mem: memory@80600000 {
+ xbl_mem: xbl@80600000 {
reg = <0x0 0x80600000 0x0 0x200000>;
no-map;
};
- aop_mem: memory@80800000 {
+ aop_mem: aop@80800000 {
reg = <0x0 0x80800000 0x0 0x60000>;
no-map;
};
- aop_cmd_db_mem: memory@80860000 {
+ aop_cmd_db_mem: aop-cmd-db@80860000 {
reg = <0x0 0x80860000 0x0 0x20000>;
compatible = "qcom,cmd-db";
no-map;
};
- reserved_xbl_uefi_log: memory@80880000 {
+ reserved_xbl_uefi_log: xbl-uefi-res@80880000 {
reg = <0x0 0x80884000 0x0 0x10000>;
no-map;
};
- sec_apps_mem: memory@808ff000 {
+ sec_apps_mem: sec-apps@808ff000 {
reg = <0x0 0x808ff000 0x0 0x1000>;
no-map;
};
- smem_mem: memory@80900000 {
+ smem_mem: smem@80900000 {
reg = <0x0 0x80900000 0x0 0x200000>;
no-map;
};
- cpucp_mem: memory@80b00000 {
+ cpucp_mem: cpucp@80b00000 {
no-map;
reg = <0x0 0x80b00000 0x0 0x100000>;
};
- wlan_fw_mem: memory@80c00000 {
+ wlan_fw_mem: wlan-fw@80c00000 {
reg = <0x0 0x80c00000 0x0 0xc00000>;
no-map;
};
- video_mem: memory@8b200000 {
+ adsp_mem: adsp@86700000 {
+ reg = <0x0 0x86700000 0x0 0x2800000>;
+ no-map;
+ };
+
+ video_mem: video@8b200000 {
reg = <0x0 0x8b200000 0x0 0x500000>;
no-map;
};
+ cdsp_mem: cdsp@88f00000 {
+ reg = <0x0 0x88f00000 0x0 0x1e00000>;
+ no-map;
+ };
+
- ipa_fw_mem: memory@8b700000 {
+ ipa_fw_mem: ipa-fw@8b700000 {
reg = <0 0x8b700000 0 0x10000>;
no-map;
};
+ gpu_zap_mem: zap@8b71a000 {
+ reg = <0 0x8b71a000 0 0x2000>;
+ no-map;
+ };
+
+ mpss_mem: mpss@8b800000 {
+ reg = <0x0 0x8b800000 0x0 0xf600000>;
+ no-map;
+ };
+
+ wpss_mem: wpss@9ae00000 {
+ reg = <0x0 0x9ae00000 0x0 0x1900000>;
+ no-map;
+ };
+
- rmtfs_mem: memory@9c900000 {
+ rmtfs_mem: rmtfs@9c900000 {
compatible = "qcom,rmtfs-mem";
reg = <0x0 0x9c900000 0x0 0x280000>;
no-map;
@@ -906,7 +932,7 @@
clocks = <&rpmhcc RPMH_CXO_CLK>,
<&rpmhcc RPMH_CXO_CLK_A>, <&sleep_clk>,
<0>, <&pcie1_phy>,
- <0>, <0>, <0>,
+ <&ufs_mem_phy 0>, <&ufs_mem_phy 1>, <&ufs_mem_phy 2>,
<&usb_1_qmpphy QMP_USB43DP_USB3_PIPE_CLK>;
clock-names = "bi_tcxo", "bi_tcxo_ao", "sleep_clk",
"pcie_0_pipe_clk", "pcie_1_pipe_clk",
@@ -974,6 +1000,7 @@
bus-width = <8>;
supports-cqe;
+ dma-coherent;
qcom,dll-config = <0x0007642c>;
qcom,ddr-config = <0x80040868>;
@@ -2034,6 +2061,11 @@
};
};
+ rng: rng@10d3000 {
+ compatible = "qcom,sc7280-trng", "qcom,trng";
+ reg = <0 0x010d3000 0 0x1000>;
+ };
+
cnoc2: interconnect@1500000 {
reg = <0 0x01500000 0 0x1000>;
compatible = "qcom,sc7280-cnoc2";
@@ -2126,7 +2158,7 @@
qcom,smem-state-names = "wlan-smp2p-out";
};
- pcie1: pci@1c08000 {
+ pcie1: pcie@1c08000 {
compatible = "qcom,pcie-sc7280";
reg = <0 0x01c08000 0 0x3000>,
<0 0x40000000 0 0xf1d>,
@@ -2233,6 +2265,99 @@
status = "disabled";
};
+ ufs_mem_hc: ufs@1d84000 {
+ compatible = "qcom,sc7280-ufshc", "qcom,ufshc",
+ "jedec,ufs-2.0";
+ reg = <0x0 0x01d84000 0x0 0x3000>;
+ interrupts = <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH>;
+ phys = <&ufs_mem_phy>;
+ phy-names = "ufsphy";
+ lanes-per-direction = <2>;
+ #reset-cells = <1>;
+ resets = <&gcc GCC_UFS_PHY_BCR>;
+ reset-names = "rst";
+
+ power-domains = <&gcc GCC_UFS_PHY_GDSC>;
+ required-opps = <&rpmhpd_opp_nom>;
+
+ iommus = <&apps_smmu 0x80 0x0>;
+ dma-coherent;
+
+ interconnects = <&aggre1_noc MASTER_UFS_MEM QCOM_ICC_TAG_ALWAYS
+ &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>,
+ <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
+ &cnoc2 SLAVE_UFS_MEM_CFG QCOM_ICC_TAG_ALWAYS>;
+ interconnect-names = "ufs-ddr", "cpu-ufs";
+
+ clocks = <&gcc GCC_UFS_PHY_AXI_CLK>,
+ <&gcc GCC_AGGRE_UFS_PHY_AXI_CLK>,
+ <&gcc GCC_UFS_PHY_AHB_CLK>,
+ <&gcc GCC_UFS_PHY_UNIPRO_CORE_CLK>,
+ <&rpmhcc RPMH_CXO_CLK>,
+ <&gcc GCC_UFS_PHY_TX_SYMBOL_0_CLK>,
+ <&gcc GCC_UFS_PHY_RX_SYMBOL_0_CLK>,
+ <&gcc GCC_UFS_PHY_RX_SYMBOL_1_CLK>;
+ clock-names = "core_clk",
+ "bus_aggr_clk",
+ "iface_clk",
+ "core_clk_unipro",
+ "ref_clk",
+ "tx_lane0_sync_clk",
+ "rx_lane0_sync_clk",
+ "rx_lane1_sync_clk";
+ freq-table-hz =
+ <75000000 300000000>,
+ <0 0>,
+ <0 0>,
+ <75000000 300000000>,
+ <0 0>,
+ <0 0>,
+ <0 0>,
+ <0 0>;
+ status = "disabled";
+ };
+
+ ufs_mem_phy: phy@1d87000 {
+ compatible = "qcom,sc7280-qmp-ufs-phy";
+ reg = <0x0 0x01d87000 0x0 0xe00>;
+ clocks = <&rpmhcc RPMH_CXO_CLK>,
+ <&gcc GCC_UFS_PHY_PHY_AUX_CLK>,
+ <&gcc GCC_UFS_1_CLKREF_EN>;
+ clock-names = "ref", "ref_aux", "qref";
+
+ power-domains = <&rpmhpd SC7280_MX>;
+
+ resets = <&ufs_mem_hc 0>;
+ reset-names = "ufsphy";
+
+ #clock-cells = <1>;
+ #phy-cells = <0>;
+
+ status = "disabled";
+ };
+
+ cryptobam: dma-controller@1dc4000 {
+ compatible = "qcom,bam-v1.7.4", "qcom,bam-v1.7.0";
+ reg = <0x0 0x01dc4000 0x0 0x28000>;
+ interrupts = <GIC_SPI 272 IRQ_TYPE_LEVEL_HIGH>;
+ #dma-cells = <1>;
+ iommus = <&apps_smmu 0x4e4 0x0011>,
+ <&apps_smmu 0x4e6 0x0011>;
+ qcom,ee = <0>;
+ qcom,controlled-remotely;
+ };
+
+ crypto: crypto@1dfa000 {
+ compatible = "qcom,sc7280-qce", "qcom,sm8150-qce", "qcom,qce";
+ reg = <0x0 0x01dfa000 0x0 0x6000>;
+ dmas = <&cryptobam 4>, <&cryptobam 5>;
+ dma-names = "rx", "tx";
+ iommus = <&apps_smmu 0x4e4 0x0011>,
+ <&apps_smmu 0x4e4 0x0011>;
+ interconnects = <&aggre2_noc MASTER_CRYPTO 0 &mc_virt SLAVE_EBI1 0>;
+ interconnect-names = "memory";
+ };
+
ipa: ipa@1e40000 {
compatible = "qcom,sc7280-ipa";
@@ -2598,7 +2723,8 @@
"cx_mem",
"cx_dbgc";
interrupts = <GIC_SPI 300 IRQ_TYPE_LEVEL_HIGH>;
- iommus = <&adreno_smmu 0 0x401>;
+ iommus = <&adreno_smmu 0 0x400>,
+ <&adreno_smmu 1 0x400>;
operating-points-v2 = <&gpu_opp_table>;
qcom,gmu = <&gmu>;
interconnects = <&gem_noc MASTER_GFX3D 0 &mc_virt SLAVE_EBI1 0>;
@@ -2608,6 +2734,10 @@
nvmem-cells = <&gpu_speed_bin>;
nvmem-cell-names = "speed_bin";
+ gpu_zap_shader: zap-shader {
+ memory-region = <&gpu_zap_mem>;
+ };
+
gpu_opp_table: opp-table {
compatible = "operating-points-v2";
@@ -2615,14 +2745,14 @@
opp-hz = /bits/ 64 <315000000>;
opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>;
opp-peak-kBps = <1804000>;
- opp-supported-hw = <0x03>;
+ opp-supported-hw = <0x07>;
};
opp-450000000 {
opp-hz = /bits/ 64 <450000000>;
opp-level = <RPMH_REGULATOR_LEVEL_SVS>;
opp-peak-kBps = <4068000>;
- opp-supported-hw = <0x03>;
+ opp-supported-hw = <0x07>;
};
/* Only applicable for SKUs which has 550Mhz as Fmax */
@@ -2637,28 +2767,28 @@
opp-hz = /bits/ 64 <550000000>;
opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>;
opp-peak-kBps = <6832000>;
- opp-supported-hw = <0x02>;
+ opp-supported-hw = <0x06>;
};
opp-608000000 {
opp-hz = /bits/ 64 <608000000>;
opp-level = <RPMH_REGULATOR_LEVEL_SVS_L2>;
opp-peak-kBps = <8368000>;
- opp-supported-hw = <0x02>;
+ opp-supported-hw = <0x06>;
};
opp-700000000 {
opp-hz = /bits/ 64 <700000000>;
opp-level = <RPMH_REGULATOR_LEVEL_NOM>;
opp-peak-kBps = <8532000>;
- opp-supported-hw = <0x02>;
+ opp-supported-hw = <0x06>;
};
opp-812000000 {
opp-hz = /bits/ 64 <812000000>;
opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>;
opp-peak-kBps = <8532000>;
- opp-supported-hw = <0x02>;
+ opp-supported-hw = <0x06>;
};
opp-840000000 {
@@ -2772,12 +2902,12 @@
"gpu_cc_hub_aon_clk";
power-domains = <&gpucc GPU_CC_CX_GDSC>;
+ dma-coherent;
};
remoteproc_mpss: remoteproc@4080000 {
compatible = "qcom,sc7280-mpss-pas";
- reg = <0 0x04080000 0 0x10000>, <0 0x04180000 0 0x48>;
- reg-names = "qdsp6", "rmb";
+ reg = <0 0x04080000 0 0x10000>;
interrupts-extended = <&intc GIC_SPI 264 IRQ_TYPE_EDGE_RISING>,
<&modem_smp2p_in 0 IRQ_TYPE_EDGE_RISING>,
@@ -3329,6 +3459,7 @@
operating-points-v2 = <&sdhc2_opp_table>;
bus-width = <4>;
+ dma-coherent;
qcom,dll-config = <0x0007642c>;
@@ -3399,6 +3530,32 @@
#clock-cells = <1>;
#phy-cells = <1>;
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+
+ usb_dp_qmpphy_out: endpoint {
+ };
+ };
+
+ port@1 {
+ reg = <1>;
+
+ usb_dp_qmpphy_usb_ss_in: endpoint {
+ };
+ };
+
+ port@2 {
+ reg = <2>;
+
+ usb_dp_qmpphy_dp_in: endpoint {
+ };
+ };
+ };
};
usb_2: usb@8cf8800 {
@@ -3426,8 +3583,8 @@
assigned-clock-rates = <19200000>, <200000000>;
interrupts-extended = <&intc GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
- <&pdc 12 IRQ_TYPE_EDGE_RISING>,
- <&pdc 13 IRQ_TYPE_EDGE_RISING>;
+ <&pdc 12 IRQ_TYPE_EDGE_BOTH>,
+ <&pdc 13 IRQ_TYPE_EDGE_BOTH>;
interrupt-names = "hs_phy_irq",
"dp_hs_phy_irq",
"dm_hs_phy_irq";
@@ -3479,8 +3636,77 @@
status = "disabled";
};
+ remoteproc_adsp: remoteproc@3700000 {
+ compatible = "qcom,sc7280-adsp-pas";
+ reg = <0 0x03700000 0 0x100>;
+
+ interrupts-extended = <&pdc 6 IRQ_TYPE_LEVEL_HIGH>,
+ <&adsp_smp2p_in 0 IRQ_TYPE_EDGE_RISING>,
+ <&adsp_smp2p_in 1 IRQ_TYPE_EDGE_RISING>,
+ <&adsp_smp2p_in 2 IRQ_TYPE_EDGE_RISING>,
+ <&adsp_smp2p_in 3 IRQ_TYPE_EDGE_RISING>,
+ <&adsp_smp2p_in 7 IRQ_TYPE_EDGE_RISING>;
+ interrupt-names = "wdog", "fatal", "ready", "handover",
+ "stop-ack", "shutdown-ack";
+
+ clocks = <&rpmhcc RPMH_CXO_CLK>;
+ clock-names = "xo";
+
+ power-domains = <&rpmhpd SC7280_LCX>,
+ <&rpmhpd SC7280_LMX>;
+ power-domain-names = "lcx", "lmx";
+
+ memory-region = <&adsp_mem>;
+
+ qcom,qmp = <&aoss_qmp>;
+
+ qcom,smem-states = <&adsp_smp2p_out 0>;
+ qcom,smem-state-names = "stop";
+
+ status = "disabled";
+
+ glink-edge {
+ interrupts-extended = <&ipcc IPCC_CLIENT_LPASS
+ IPCC_MPROC_SIGNAL_GLINK_QMP
+ IRQ_TYPE_EDGE_RISING>;
+
+ mboxes = <&ipcc IPCC_CLIENT_LPASS
+ IPCC_MPROC_SIGNAL_GLINK_QMP>;
+
+ label = "lpass";
+ qcom,remote-pid = <2>;
+
+ fastrpc {
+ compatible = "qcom,fastrpc";
+ qcom,glink-channels = "fastrpcglink-apps-dsp";
+ label = "adsp";
+ qcom,non-secure-domain;
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ compute-cb@3 {
+ compatible = "qcom,fastrpc-compute-cb";
+ reg = <3>;
+ iommus = <&apps_smmu 0x1803 0x0>;
+ };
+
+ compute-cb@4 {
+ compatible = "qcom,fastrpc-compute-cb";
+ reg = <4>;
+ iommus = <&apps_smmu 0x1804 0x0>;
+ };
+
+ compute-cb@5 {
+ compatible = "qcom,fastrpc-compute-cb";
+ reg = <5>;
+ iommus = <&apps_smmu 0x1805 0x0>;
+ };
+ };
+ };
+ };
+
remoteproc_wpss: remoteproc@8a00000 {
- compatible = "qcom,sc7280-wpss-pil";
+ compatible = "qcom,sc7280-wpss-pas";
reg = <0 0x08a00000 0 0x10000>;
interrupts-extended = <&intc GIC_SPI 587 IRQ_TYPE_EDGE_RISING>,
@@ -3492,12 +3718,8 @@
interrupt-names = "wdog", "fatal", "ready", "handover",
"stop-ack", "shutdown-ack";
- clocks = <&gcc GCC_WPSS_AHB_BDG_MST_CLK>,
- <&gcc GCC_WPSS_AHB_CLK>,
- <&gcc GCC_WPSS_RSCP_CLK>,
- <&rpmhcc RPMH_CXO_CLK>;
- clock-names = "ahb_bdg", "ahb",
- "rscp", "xo";
+ clocks = <&rpmhcc RPMH_CXO_CLK>;
+ clock-names = "xo";
power-domains = <&rpmhpd SC7280_CX>,
<&rpmhpd SC7280_MX>;
@@ -3510,11 +3732,6 @@
qcom,smem-states = <&wpss_smp2p_out 0>;
qcom,smem-state-names = "stop";
- resets = <&aoss_reset AOSS_CC_WCSS_RESTART>,
- <&pdc_reset PDC_WPSS_SYNC_RESET>;
- reset-names = "restart", "pdc_sync";
-
- qcom,halt-regs = <&tcsr_1 0x17000>;
status = "disabled";
@@ -3656,6 +3873,144 @@
qcom,bcm-voters = <&apps_bcm_voter>;
};
+ remoteproc_cdsp: remoteproc@a300000 {
+ compatible = "qcom,sc7280-cdsp-pas";
+ reg = <0 0x0a300000 0 0x10000>;
+
+ interrupts-extended = <&intc GIC_SPI 578 IRQ_TYPE_LEVEL_HIGH>,
+ <&cdsp_smp2p_in 0 IRQ_TYPE_EDGE_RISING>,
+ <&cdsp_smp2p_in 1 IRQ_TYPE_EDGE_RISING>,
+ <&cdsp_smp2p_in 2 IRQ_TYPE_EDGE_RISING>,
+ <&cdsp_smp2p_in 3 IRQ_TYPE_EDGE_RISING>,
+ <&cdsp_smp2p_in 7 IRQ_TYPE_EDGE_RISING>;
+ interrupt-names = "wdog", "fatal", "ready", "handover",
+ "stop-ack", "shutdown-ack";
+
+ clocks = <&rpmhcc RPMH_CXO_CLK>;
+ clock-names = "xo";
+
+ power-domains = <&rpmhpd SC7280_CX>,
+ <&rpmhpd SC7280_MX>;
+ power-domain-names = "cx", "mx";
+
+ interconnects = <&nsp_noc MASTER_CDSP_PROC 0 &mc_virt SLAVE_EBI1 0>;
+
+ memory-region = <&cdsp_mem>;
+
+ qcom,qmp = <&aoss_qmp>;
+
+ qcom,smem-states = <&cdsp_smp2p_out 0>;
+ qcom,smem-state-names = "stop";
+
+ status = "disabled";
+
+ glink-edge {
+ interrupts-extended = <&ipcc IPCC_CLIENT_CDSP
+ IPCC_MPROC_SIGNAL_GLINK_QMP
+ IRQ_TYPE_EDGE_RISING>;
+ mboxes = <&ipcc IPCC_CLIENT_CDSP
+ IPCC_MPROC_SIGNAL_GLINK_QMP>;
+
+ label = "cdsp";
+ qcom,remote-pid = <5>;
+
+ fastrpc {
+ compatible = "qcom,fastrpc";
+ qcom,glink-channels = "fastrpcglink-apps-dsp";
+ label = "cdsp";
+ qcom,non-secure-domain;
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ compute-cb@1 {
+ compatible = "qcom,fastrpc-compute-cb";
+ reg = <1>;
+ iommus = <&apps_smmu 0x11a1 0x0420>,
+ <&apps_smmu 0x1181 0x0420>;
+ };
+
+ compute-cb@2 {
+ compatible = "qcom,fastrpc-compute-cb";
+ reg = <2>;
+ iommus = <&apps_smmu 0x11a2 0x0420>,
+ <&apps_smmu 0x1182 0x0420>;
+ };
+
+ compute-cb@3 {
+ compatible = "qcom,fastrpc-compute-cb";
+ reg = <3>;
+ iommus = <&apps_smmu 0x11a3 0x0420>,
+ <&apps_smmu 0x1183 0x0420>;
+ };
+
+ compute-cb@4 {
+ compatible = "qcom,fastrpc-compute-cb";
+ reg = <4>;
+ iommus = <&apps_smmu 0x11a4 0x0420>,
+ <&apps_smmu 0x1184 0x0420>;
+ };
+
+ compute-cb@5 {
+ compatible = "qcom,fastrpc-compute-cb";
+ reg = <5>;
+ iommus = <&apps_smmu 0x11a5 0x0420>,
+ <&apps_smmu 0x1185 0x0420>;
+ };
+
+ compute-cb@6 {
+ compatible = "qcom,fastrpc-compute-cb";
+ reg = <6>;
+ iommus = <&apps_smmu 0x11a6 0x0420>,
+ <&apps_smmu 0x1186 0x0420>;
+ };
+
+ compute-cb@7 {
+ compatible = "qcom,fastrpc-compute-cb";
+ reg = <7>;
+ iommus = <&apps_smmu 0x11a7 0x0420>,
+ <&apps_smmu 0x1187 0x0420>;
+ };
+
+ compute-cb@8 {
+ compatible = "qcom,fastrpc-compute-cb";
+ reg = <8>;
+ iommus = <&apps_smmu 0x11a8 0x0420>,
+ <&apps_smmu 0x1188 0x0420>;
+ };
+
+ /* note: secure cb9 in downstream */
+
+ compute-cb@11 {
+ compatible = "qcom,fastrpc-compute-cb";
+ reg = <11>;
+ iommus = <&apps_smmu 0x11ab 0x0420>,
+ <&apps_smmu 0x118b 0x0420>;
+ };
+
+ compute-cb@12 {
+ compatible = "qcom,fastrpc-compute-cb";
+ reg = <12>;
+ iommus = <&apps_smmu 0x11ac 0x0420>,
+ <&apps_smmu 0x118c 0x0420>;
+ };
+
+ compute-cb@13 {
+ compatible = "qcom,fastrpc-compute-cb";
+ reg = <13>;
+ iommus = <&apps_smmu 0x11ad 0x0420>,
+ <&apps_smmu 0x118d 0x0420>;
+ };
+
+ compute-cb@14 {
+ compatible = "qcom,fastrpc-compute-cb";
+ reg = <14>;
+ iommus = <&apps_smmu 0x11ae 0x0420>,
+ <&apps_smmu 0x118e 0x0420>;
+ };
+ };
+ };
+ };
+
usb_1: usb@a6f8800 {
compatible = "qcom,sc7280-dwc3", "qcom,dwc3";
reg = <0 0x0a6f8800 0 0x400>;
@@ -3681,9 +4036,9 @@
assigned-clock-rates = <19200000>, <200000000>;
interrupts-extended = <&intc GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>,
- <&pdc 14 IRQ_TYPE_LEVEL_HIGH>,
+ <&pdc 14 IRQ_TYPE_EDGE_BOTH>,
<&pdc 15 IRQ_TYPE_EDGE_BOTH>,
- <&pdc 17 IRQ_TYPE_EDGE_BOTH>;
+ <&pdc 17 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "hs_phy_irq",
"dp_hs_phy_irq",
"dm_hs_phy_irq",
@@ -3793,6 +4148,86 @@
#power-domain-cells = <1>;
};
+ cci0: cci@ac4a000 {
+ compatible = "qcom,sc7280-cci", "qcom,msm8996-cci";
+ reg = <0 0x0ac4a000 0 0x1000>;
+ interrupts = <GIC_SPI 460 IRQ_TYPE_EDGE_RISING>;
+ power-domains = <&camcc CAM_CC_TITAN_TOP_GDSC>;
+
+ clocks = <&camcc CAM_CC_CAMNOC_AXI_CLK>,
+ <&camcc CAM_CC_SLOW_AHB_CLK_SRC>,
+ <&camcc CAM_CC_CPAS_AHB_CLK>,
+ <&camcc CAM_CC_CCI_0_CLK>,
+ <&camcc CAM_CC_CCI_0_CLK_SRC>;
+ clock-names = "camnoc_axi",
+ "slow_ahb_src",
+ "cpas_ahb",
+ "cci",
+ "cci_src";
+ pinctrl-0 = <&cci0_default &cci1_default>;
+ pinctrl-1 = <&cci0_sleep &cci1_sleep>;
+ pinctrl-names = "default", "sleep";
+
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ status = "disabled";
+
+ cci0_i2c0: i2c-bus@0 {
+ reg = <0>;
+ clock-frequency = <1000000>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+
+ cci0_i2c1: i2c-bus@1 {
+ reg = <1>;
+ clock-frequency = <1000000>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+ };
+
+ cci1: cci@ac4b000 {
+ compatible = "qcom,sc7280-cci", "qcom,msm8996-cci";
+ reg = <0 0x0ac4b000 0 0x1000>;
+ interrupts = <GIC_SPI 271 IRQ_TYPE_EDGE_RISING>;
+ power-domains = <&camcc CAM_CC_TITAN_TOP_GDSC>;
+
+ clocks = <&camcc CAM_CC_CAMNOC_AXI_CLK>,
+ <&camcc CAM_CC_SLOW_AHB_CLK_SRC>,
+ <&camcc CAM_CC_CPAS_AHB_CLK>,
+ <&camcc CAM_CC_CCI_1_CLK>,
+ <&camcc CAM_CC_CCI_1_CLK_SRC>;
+ clock-names = "camnoc_axi",
+ "slow_ahb_src",
+ "cpas_ahb",
+ "cci",
+ "cci_src";
+ pinctrl-0 = <&cci2_default &cci3_default>;
+ pinctrl-1 = <&cci2_sleep &cci3_sleep>;
+ pinctrl-names = "default", "sleep";
+
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ status = "disabled";
+
+ cci1_i2c0: i2c-bus@0 {
+ reg = <0>;
+ clock-frequency = <1000000>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+
+ cci1_i2c1: i2c-bus@1 {
+ reg = <1>;
+ clock-frequency = <1000000>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+ };
+
camcc: clock-controller@ad00000 {
compatible = "qcom,sc7280-camcc";
reg = <0 0x0ad00000 0 0x10000>;
@@ -3847,8 +4282,12 @@
interrupt-controller;
#interrupt-cells = <1>;
- interconnects = <&mmss_noc MASTER_MDP0 0 &mc_virt SLAVE_EBI1 0>;
- interconnect-names = "mdp0-mem";
+ interconnects = <&mmss_noc MASTER_MDP0 QCOM_ICC_TAG_ALWAYS
+ &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>,
+ <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
+ &cnoc2 SLAVE_DISPLAY_CFG QCOM_ICC_TAG_ALWAYS>;
+ interconnect-names = "mdp0-mem",
+ "cpu-cfg";
iommus = <&apps_smmu 0x900 0x402>;
@@ -4298,6 +4737,62 @@
gpio-ranges = <&tlmm 0 0 175>;
wakeup-parent = <&pdc>;
+ cci0_default: cci0-default-state {
+ pins = "gpio69", "gpio70";
+ function = "cci_i2c";
+ drive-strength = <2>;
+ bias-pull-up;
+ };
+
+ cci0_sleep: cci0-sleep-state {
+ pins = "gpio69", "gpio70";
+ function = "cci_i2c";
+ drive-strength = <2>;
+ bias-pull-down;
+ };
+
+ cci1_default: cci1-default-state {
+ pins = "gpio71", "gpio72";
+ function = "cci_i2c";
+ drive-strength = <2>;
+ bias-pull-up;
+ };
+
+ cci1_sleep: cci1-sleep-state {
+ pins = "gpio71", "gpio72";
+ function = "cci_i2c";
+ drive-strength = <2>;
+ bias-pull-down;
+ };
+
+ cci2_default: cci2-default-state {
+ pins = "gpio73", "gpio74";
+ function = "cci_i2c";
+ drive-strength = <2>;
+ bias-pull-up;
+ };
+
+ cci2_sleep: cci2-sleep-state {
+ pins = "gpio73", "gpio74";
+ function = "cci_i2c";
+ drive-strength = <2>;
+ bias-pull-down;
+ };
+
+ cci3_default: cci3-default-state {
+ pins = "gpio75", "gpio76";
+ function = "cci_i2c";
+ drive-strength = <2>;
+ bias-pull-up;
+ };
+
+ cci3_sleep: cci3-sleep-state {
+ pins = "gpio75", "gpio76";
+ function = "cci_i2c";
+ drive-strength = <2>;
+ bias-pull-down;
+ };
+
dp_hot_plug_det: dp-hot-plug-det-state {
pins = "gpio47";
function = "dp_hot";
@@ -5222,7 +5717,7 @@
compatible = "qcom,apss-wdt-sc7280", "qcom,kpss-wdt";
reg = <0 0x17c10000 0 0x1000>;
clocks = <&sleep_clk>;
- interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>;
+ interrupts = <GIC_SPI 0 IRQ_TYPE_EDGE_RISING>;
status = "reserved"; /* Owned by Gunyah hyp */
};
diff --git a/dts/upstream/src/arm64/qcom/sc8180x-lenovo-flex-5g.dts b/dts/upstream/src/arm64/qcom/sc8180x-lenovo-flex-5g.dts
index 3ea07d0..0c22f3e 100644
--- a/dts/upstream/src/arm64/qcom/sc8180x-lenovo-flex-5g.dts
+++ b/dts/upstream/src/arm64/qcom/sc8180x-lenovo-flex-5g.dts
@@ -452,8 +452,8 @@
};
&pcie3 {
- perst-gpio = <&tlmm 178 GPIO_ACTIVE_LOW>;
- wake-gpio = <&tlmm 180 GPIO_ACTIVE_HIGH>;
+ perst-gpios = <&tlmm 178 GPIO_ACTIVE_LOW>;
+ wake-gpios = <&tlmm 180 GPIO_ACTIVE_HIGH>;
pinctrl-0 = <&pcie3_default_state>;
pinctrl-names = "default";
diff --git a/dts/upstream/src/arm64/qcom/sc8180x-primus.dts b/dts/upstream/src/arm64/qcom/sc8180x-primus.dts
index fd2fab4..bfee60c 100644
--- a/dts/upstream/src/arm64/qcom/sc8180x-primus.dts
+++ b/dts/upstream/src/arm64/qcom/sc8180x-primus.dts
@@ -43,7 +43,7 @@
pinctrl-0 = <&hall_int_active_state>;
lid-switch {
- gpios = <&tlmm 121 GPIO_ACTIVE_HIGH>;
+ gpios = <&tlmm 121 GPIO_ACTIVE_LOW>;
linux,input-type = <EV_SW>;
linux,code = <SW_LID>;
wakeup-source;
@@ -386,12 +386,18 @@
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM
+ RPMH_REGULATOR_MODE_HPM>;
+ regulator-allow-set-load;
};
vreg_l10e_2p9: ldo10 {
regulator-min-microvolt = <2904000>;
regulator-max-microvolt = <2904000>;
regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM
+ RPMH_REGULATOR_MODE_HPM>;
+ regulator-allow-set-load;
};
vreg_l12e: ldo12 {
@@ -531,8 +537,8 @@
};
&pcie1 {
- perst-gpio = <&tlmm 175 GPIO_ACTIVE_LOW>;
- wake-gpio = <&tlmm 177 GPIO_ACTIVE_HIGH>;
+ perst-gpios = <&tlmm 175 GPIO_ACTIVE_LOW>;
+ wake-gpios = <&tlmm 177 GPIO_ACTIVE_HIGH>;
pinctrl-names = "default";
pinctrl-0 = <&pcie2_default_state>;
diff --git a/dts/upstream/src/arm64/qcom/sc8180x.dtsi b/dts/upstream/src/arm64/qcom/sc8180x.dtsi
index a34f438..0430d99 100644
--- a/dts/upstream/src/arm64/qcom/sc8180x.dtsi
+++ b/dts/upstream/src/arm64/qcom/sc8180x.dtsi
@@ -8,6 +8,7 @@
#include <dt-bindings/clock/qcom,gcc-sc8180x.h>
#include <dt-bindings/clock/qcom,gpucc-sm8150.h>
#include <dt-bindings/clock/qcom,rpmh.h>
+#include <dt-bindings/interconnect/qcom,icc.h>
#include <dt-bindings/interconnect/qcom,osm-l3.h>
#include <dt-bindings/interconnect/qcom,sc8180x.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
@@ -1684,7 +1685,7 @@
qcom,bcm-voters = <&apps_bcm_voter>;
};
- pcie0: pci@1c00000 {
+ pcie0: pcie@1c00000 {
compatible = "qcom,pcie-sc8180x";
reg = <0 0x01c00000 0 0x3000>,
<0 0x60000000 0 0xf1d>,
@@ -1736,7 +1737,6 @@
assigned-clocks = <&gcc GCC_PCIE_0_AUX_CLK>;
assigned-clock-rates = <19200000>;
- iommus = <&apps_smmu 0x1d80 0x7f>;
iommu-map = <0x0 &apps_smmu 0x1d80 0x1>,
<0x100 &apps_smmu 0x1d81 0x1>;
@@ -1751,6 +1751,7 @@
phys = <&pcie0_phy>;
phy-names = "pciephy";
+ dma-coherent;
status = "disabled";
};
@@ -1761,7 +1762,7 @@
clocks = <&gcc GCC_PCIE_PHY_AUX_CLK>,
<&gcc GCC_PCIE_0_CFG_AHB_CLK>,
<&gcc GCC_PCIE_0_CLKREF_CLK>,
- <&gcc GCC_PCIE1_PHY_REFGEN_CLK>,
+ <&gcc GCC_PCIE0_PHY_REFGEN_CLK>,
<&gcc GCC_PCIE_0_PIPE_CLK>;
clock-names = "aux",
"cfg_ahb",
@@ -1781,7 +1782,7 @@
status = "disabled";
};
- pcie3: pci@1c08000 {
+ pcie3: pcie@1c08000 {
compatible = "qcom,pcie-sc8180x";
reg = <0 0x01c08000 0 0x3000>,
<0 0x40000000 0 0xf1d>,
@@ -1833,7 +1834,6 @@
assigned-clocks = <&gcc GCC_PCIE_3_AUX_CLK>;
assigned-clock-rates = <19200000>;
- iommus = <&apps_smmu 0x1e00 0x7f>;
iommu-map = <0x0 &apps_smmu 0x1e00 0x1>,
<0x100 &apps_smmu 0x1e01 0x1>;
@@ -1848,6 +1848,7 @@
phys = <&pcie3_phy>;
phy-names = "pciephy";
+ dma-coherent;
status = "disabled";
};
@@ -1858,7 +1859,7 @@
clocks = <&gcc GCC_PCIE_PHY_AUX_CLK>,
<&gcc GCC_PCIE_3_CFG_AHB_CLK>,
<&gcc GCC_PCIE_3_CLKREF_CLK>,
- <&gcc GCC_PCIE2_PHY_REFGEN_CLK>,
+ <&gcc GCC_PCIE3_PHY_REFGEN_CLK>,
<&gcc GCC_PCIE_3_PIPE_CLK>;
clock-names = "aux",
"cfg_ahb",
@@ -1879,7 +1880,7 @@
status = "disabled";
};
- pcie1: pci@1c10000 {
+ pcie1: pcie@1c10000 {
compatible = "qcom,pcie-sc8180x";
reg = <0 0x01c10000 0 0x3000>,
<0 0x68000000 0 0xf1d>,
@@ -1931,7 +1932,6 @@
assigned-clocks = <&gcc GCC_PCIE_1_AUX_CLK>;
assigned-clock-rates = <19200000>;
- iommus = <&apps_smmu 0x1c80 0x7f>;
iommu-map = <0x0 &apps_smmu 0x1c80 0x1>,
<0x100 &apps_smmu 0x1c81 0x1>;
@@ -1946,6 +1946,7 @@
phys = <&pcie1_phy>;
phy-names = "pciephy";
+ dma-coherent;
status = "disabled";
};
@@ -1977,7 +1978,7 @@
status = "disabled";
};
- pcie2: pci@1c18000 {
+ pcie2: pcie@1c18000 {
compatible = "qcom,pcie-sc8180x";
reg = <0 0x01c18000 0 0x3000>,
<0 0x70000000 0 0xf1d>,
@@ -2029,7 +2030,6 @@
assigned-clocks = <&gcc GCC_PCIE_2_AUX_CLK>;
assigned-clock-rates = <19200000>;
- iommus = <&apps_smmu 0x1d00 0x7f>;
iommu-map = <0x0 &apps_smmu 0x1d00 0x1>,
<0x100 &apps_smmu 0x1d01 0x1>;
@@ -2044,6 +2044,7 @@
phys = <&pcie2_phy>;
phy-names = "pciephy";
+ dma-coherent;
status = "disabled";
};
@@ -2062,7 +2063,7 @@
"refgen",
"pipe";
#clock-cells = <0>;
- clock-output-names = "pcie_3_pipe_clk";
+ clock-output-names = "pcie_2_pipe_clk";
#phy-cells = <0>;
@@ -2114,6 +2115,14 @@
<0 0>,
<0 0>;
+ power-domains = <&gcc UFS_PHY_GDSC>;
+
+ interconnects = <&aggre1_noc MASTER_UFS_MEM QCOM_ICC_TAG_ALWAYS
+ &mc_virt SLAVE_EBI_CH0 QCOM_ICC_TAG_ALWAYS>,
+ <&gem_noc MASTER_AMPSS_M0 QCOM_ICC_TAG_ALWAYS
+ &config_noc SLAVE_UFS_MEM_0_CFG QCOM_ICC_TAG_ALWAYS>;
+ interconnect-names = "ufs-ddr", "cpu-ufs";
+
status = "disabled";
};
@@ -2548,10 +2557,10 @@
usb_prim: usb@a6f8800 {
compatible = "qcom,sc8180x-dwc3", "qcom,dwc3";
reg = <0 0x0a6f8800 0 0x400>;
- interrupts = <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 486 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 488 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 489 IRQ_TYPE_LEVEL_HIGH>;
+ interrupts-extended = <&intc GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>,
+ <&pdc 6 IRQ_TYPE_LEVEL_HIGH>,
+ <&pdc 8 IRQ_TYPE_EDGE_BOTH>,
+ <&pdc 9 IRQ_TYPE_EDGE_BOTH>;
interrupt-names = "hs_phy_irq",
"ss_phy_irq",
"dm_hs_phy_irq",
@@ -2622,10 +2631,10 @@
"xo";
resets = <&gcc GCC_USB30_SEC_BCR>;
power-domains = <&gcc USB30_SEC_GDSC>;
- interrupts = <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 487 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 490 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 491 IRQ_TYPE_LEVEL_HIGH>;
+ interrupts-extended = <&intc GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>,
+ <&pdc 7 IRQ_TYPE_LEVEL_HIGH>,
+ <&pdc 10 IRQ_TYPE_EDGE_BOTH>,
+ <&pdc 11 IRQ_TYPE_EDGE_BOTH>;
interrupt-names = "hs_phy_irq", "ss_phy_irq",
"dm_hs_phy_irq", "dp_hs_phy_irq";
@@ -2704,11 +2713,15 @@
clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>,
<&gcc GCC_DISP_HF_AXI_CLK>,
<&dispcc DISP_CC_MDSS_MDP_CLK>,
- <&dispcc DISP_CC_MDSS_VSYNC_CLK>;
+ <&dispcc DISP_CC_MDSS_VSYNC_CLK>,
+ <&dispcc DISP_CC_MDSS_ROT_CLK>,
+ <&dispcc DISP_CC_MDSS_MDP_LUT_CLK>;
clock-names = "iface",
"bus",
"core",
- "vsync";
+ "vsync",
+ "rot",
+ "lut";
assigned-clocks = <&dispcc DISP_CC_MDSS_MDP_CLK>,
<&dispcc DISP_CC_MDSS_VSYNC_CLK>;
@@ -3117,8 +3130,6 @@
phys = <&edp_phy>;
phy-names = "dp";
- #sound-dai-cells = <0>;
-
operating-points-v2 = <&edp_opp_table>;
power-domains = <&rpmhpd SC8180X_MMCX>;
@@ -3418,10 +3429,12 @@
reg = <0x0 0x17a00000 0x0 0x10000>, /* GICD */
<0x0 0x17a60000 0x0 0x100000>; /* GICR * 8 */
interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
+ #redistributor-regions = <1>;
+ redistributor-stride = <0 0x20000>;
};
apss_shared: mailbox@17c00000 {
- compatible = "qcom,sc8180x-apss-shared";
+ compatible = "qcom,sc8180x-apss-shared", "qcom,sdm845-apss-shared";
reg = <0x0 0x17c00000 0x0 0x1000>;
#mbox-cells = <1>;
};
diff --git a/dts/upstream/src/arm64/qcom/sc8280xp-crd.dts b/dts/upstream/src/arm64/qcom/sc8280xp-crd.dts
index e4861c6..4121556 100644
--- a/dts/upstream/src/arm64/qcom/sc8280xp-crd.dts
+++ b/dts/upstream/src/arm64/qcom/sc8280xp-crd.dts
@@ -458,6 +458,8 @@
};
&mdss0_dp3_phy {
+ compatible = "qcom,sc8280xp-edp-phy";
+
vdda-phy-supply = <&vreg_l6b>;
vdda-pll-supply = <&vreg_l3b>;
@@ -561,6 +563,8 @@
};
&pcie4 {
+ max-link-speed = <2>;
+
perst-gpios = <&tlmm 141 GPIO_ACTIVE_LOW>;
wake-gpios = <&tlmm 139 GPIO_ACTIVE_LOW>;
diff --git a/dts/upstream/src/arm64/qcom/sc8280xp-lenovo-thinkpad-x13s.dts b/dts/upstream/src/arm64/qcom/sc8280xp-lenovo-thinkpad-x13s.dts
index 38edaf5..eb657e5 100644
--- a/dts/upstream/src/arm64/qcom/sc8280xp-lenovo-thinkpad-x13s.dts
+++ b/dts/upstream/src/arm64/qcom/sc8280xp-lenovo-thinkpad-x13s.dts
@@ -82,6 +82,9 @@
leds {
compatible = "gpio-leds";
+ pinctrl-names = "default";
+ pinctrl-0 = <&cam_indicator_en>;
+
led-camera-indicator {
label = "white:camera-indicator";
function = LED_FUNCTION_INDICATOR;
@@ -570,6 +573,7 @@
&mdss0_dp3 {
compatible = "qcom,sc8280xp-edp";
+ /delete-property/ #sound-dai-cells;
data-lanes = <0 1 2 3>;
@@ -601,6 +605,7 @@
};
&mdss0_dp3_phy {
+ compatible = "qcom,sc8280xp-edp-phy";
vdda-phy-supply = <&vreg_l6b>;
vdda-pll-supply = <&vreg_l3b>;
@@ -717,6 +722,8 @@
};
&pcie4 {
+ max-link-speed = <2>;
+
perst-gpios = <&tlmm 141 GPIO_ACTIVE_LOW>;
wake-gpios = <&tlmm 139 GPIO_ACTIVE_LOW>;
@@ -1277,6 +1284,13 @@
};
};
+ cam_indicator_en: cam-indicator-en-state {
+ pins = "gpio28";
+ function = "gpio";
+ drive-strength = <2>;
+ bias-disable;
+ };
+
edp_reg_en: edp-reg-en-state {
pins = "gpio25";
function = "gpio";
diff --git a/dts/upstream/src/arm64/qcom/sc8280xp.dtsi b/dts/upstream/src/arm64/qcom/sc8280xp.dtsi
index cad59af..febf283 100644
--- a/dts/upstream/src/arm64/qcom/sc8280xp.dtsi
+++ b/dts/upstream/src/arm64/qcom/sc8280xp.dtsi
@@ -8,6 +8,7 @@
#include <dt-bindings/clock/qcom,gcc-sc8280xp.h>
#include <dt-bindings/clock/qcom,gpucc-sc8280xp.h>
#include <dt-bindings/clock/qcom,rpmh.h>
+#include <dt-bindings/clock/qcom,sc8280xp-camcc.h>
#include <dt-bindings/clock/qcom,sc8280xp-lpasscc.h>
#include <dt-bindings/interconnect/qcom,osm-l3.h>
#include <dt-bindings/interconnect/qcom,sc8280xp.h>
@@ -2731,7 +2732,7 @@
status = "disabled";
};
- swr1: soundwire-controller@3210000 {
+ swr1: soundwire@3210000 {
compatible = "qcom,soundwire-v1.6.0";
reg = <0 0x03210000 0 0x2000>;
interrupts = <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>;
@@ -2807,7 +2808,7 @@
status = "disabled";
};
- swr0: soundwire-controller@3250000 {
+ swr0: soundwire@3250000 {
reg = <0 0x03250000 0 0x2000>;
compatible = "qcom,soundwire-v1.6.0";
interrupts = <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>;
@@ -2844,7 +2845,7 @@
#reset-cells = <1>;
};
- swr2: soundwire-controller@3330000 {
+ swr2: soundwire@3330000 {
compatible = "qcom,soundwire-v1.6.0";
reg = <0 0x03330000 0 0x2000>;
interrupts = <GIC_SPI 959 IRQ_TYPE_LEVEL_HIGH>,
@@ -3450,6 +3451,20 @@
};
};
+ camcc: clock-controller@ad00000 {
+ compatible = "qcom,sc8280xp-camcc";
+ reg = <0 0x0ad00000 0 0x20000>;
+ clocks = <&gcc GCC_CAMERA_AHB_CLK>,
+ <&rpmhcc RPMH_CXO_CLK>,
+ <&rpmhcc RPMH_CXO_CLK_A>,
+ <&sleep_clk>;
+ power-domains = <&rpmhpd SC8280XP_MMCX>;
+ required-opps = <&rpmhpd_opp_low_svs>;
+ #clock-cells = <1>;
+ #reset-cells = <1>;
+ #power-domain-cells = <1>;
+ };
+
mdss0: display-subsystem@ae00000 {
compatible = "qcom,sc8280xp-mdss";
reg = <0 0x0ae00000 0 0x1000>;
@@ -4030,6 +4045,7 @@
sram@c3f0000 {
compatible = "qcom,rpmh-stats";
reg = <0 0x0c3f0000 0 0x400>;
+ qcom,qmp = <&aoss_qmp>;
};
spmi_bus: spmi@c440000 {
@@ -4225,7 +4241,7 @@
compatible = "qcom,apss-wdt-sc8280xp", "qcom,kpss-wdt";
reg = <0 0x17c10000 0 0x1000>;
clocks = <&sleep_clk>;
- interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>;
+ interrupts = <GIC_SPI 0 IRQ_TYPE_EDGE_RISING>;
};
timer@17c20000 {
diff --git a/dts/upstream/src/arm64/qcom/sdm630.dtsi b/dts/upstream/src/arm64/qcom/sdm630.dtsi
index 775700f..513fe5e 100644
--- a/dts/upstream/src/arm64/qcom/sdm630.dtsi
+++ b/dts/upstream/src/arm64/qcom/sdm630.dtsi
@@ -606,9 +606,6 @@
compatible = "qcom,sdm660-bimc";
reg = <0x01008000 0x78000>;
#interconnect-cells = <1>;
- clock-names = "bus", "bus_a";
- clocks = <&rpmcc RPM_SMD_BIMC_CLK>,
- <&rpmcc RPM_SMD_BIMC_A_CLK>;
};
restart@10ac000 {
@@ -620,28 +617,17 @@
compatible = "qcom,sdm660-cnoc";
reg = <0x01500000 0x10000>;
#interconnect-cells = <1>;
- clock-names = "bus", "bus_a";
- clocks = <&rpmcc RPM_SMD_CNOC_CLK>,
- <&rpmcc RPM_SMD_CNOC_A_CLK>;
};
snoc: interconnect@1626000 {
compatible = "qcom,sdm660-snoc";
reg = <0x01626000 0x7090>;
#interconnect-cells = <1>;
- clock-names = "bus", "bus_a";
- clocks = <&rpmcc RPM_SMD_SNOC_CLK>,
- <&rpmcc RPM_SMD_SNOC_A_CLK>;
};
anoc2_smmu: iommu@16c0000 {
compatible = "qcom,sdm630-smmu-v2", "qcom,smmu-v2";
reg = <0x016c0000 0x40000>;
-
- assigned-clocks = <&rpmcc RPM_SMD_AGGR2_NOC_CLK>;
- assigned-clock-rates = <1000>;
- clocks = <&rpmcc RPM_SMD_AGGR2_NOC_CLK>;
- clock-names = "bus";
#global-interrupts = <2>;
#iommu-cells = <1>;
@@ -686,16 +672,12 @@
compatible = "qcom,sdm660-a2noc";
reg = <0x01704000 0xc100>;
#interconnect-cells = <1>;
- clock-names = "bus",
- "bus_a",
- "ipa",
+ clock-names = "ipa",
"ufs_axi",
"aggre2_ufs_axi",
"aggre2_usb3_axi",
"cfg_noc_usb2_axi";
- clocks = <&rpmcc RPM_SMD_AGGR2_NOC_CLK>,
- <&rpmcc RPM_SMD_AGGR2_NOC_A_CLK>,
- <&rpmcc RPM_SMD_IPA_CLK>,
+ clocks = <&rpmcc RPM_SMD_IPA_CLK>,
<&gcc GCC_UFS_AXI_CLK>,
<&gcc GCC_AGGRE2_UFS_AXI_CLK>,
<&gcc GCC_AGGRE2_USB3_AXI_CLK>,
@@ -706,10 +688,8 @@
compatible = "qcom,sdm660-mnoc";
reg = <0x01745000 0xa010>;
#interconnect-cells = <1>;
- clock-names = "bus", "bus_a", "iface";
- clocks = <&rpmcc RPM_SMD_MMSSNOC_AXI_CLK>,
- <&rpmcc RPM_SMD_MMSSNOC_AXI_CLK_A>,
- <&mmcc AHB_CLK_SRC>;
+ clock-names = "iface";
+ clocks = <&mmcc AHB_CLK_SRC>;
};
tsens: thermal-sensor@10ae000 {
@@ -1186,7 +1166,9 @@
clocks = <&gcc GCC_GPU_CFG_AHB_CLK>,
<&gcc GCC_BIMC_GFX_CLK>,
<&gcc GCC_GPU_BIMC_GFX_CLK>;
- clock-names = "iface", "mem", "mem_iface";
+ clock-names = "iface",
+ "mem",
+ "mem_iface";
#global-interrupts = <2>;
#iommu-cells = <1>;
@@ -1288,20 +1270,16 @@
<&gcc GCC_USB30_MASTER_CLK>,
<&gcc GCC_AGGRE2_USB3_AXI_CLK>,
<&gcc GCC_USB30_SLEEP_CLK>,
- <&gcc GCC_USB30_MOCK_UTMI_CLK>,
- <&rpmcc RPM_SMD_AGGR2_NOC_CLK>;
+ <&gcc GCC_USB30_MOCK_UTMI_CLK>;
clock-names = "cfg_noc",
"core",
"iface",
"sleep",
- "mock_utmi",
- "bus";
+ "mock_utmi";
assigned-clocks = <&gcc GCC_USB30_MOCK_UTMI_CLK>,
- <&gcc GCC_USB30_MASTER_CLK>,
- <&rpmcc RPM_SMD_AGGR2_NOC_CLK>;
- assigned-clock-rates = <19200000>, <120000000>,
- <19200000>;
+ <&gcc GCC_USB30_MASTER_CLK>;
+ assigned-clock-rates = <19200000>, <120000000>;
interrupts = <GIC_SPI 347 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 243 IRQ_TYPE_LEVEL_HIGH>;
@@ -2204,10 +2182,9 @@
clocks = <&mmcc MNOC_AHB_CLK>,
<&mmcc BIMC_SMMU_AHB_CLK>,
- <&rpmcc RPM_SMD_MMSSNOC_AXI_CLK>,
<&mmcc BIMC_SMMU_AXI_CLK>;
clock-names = "iface-mm", "iface-smmu",
- "bus-mm", "bus-smmu";
+ "bus-smmu";
#global-interrupts = <2>;
#iommu-cells = <1>;
@@ -2324,12 +2301,6 @@
compatible = "qcom,sdm660-gnoc";
reg = <0x17900000 0xe000>;
#interconnect-cells = <1>;
- /*
- * This one apparently features no clocks,
- * so let's not mess with the driver needlessly
- */
- clock-names = "bus", "bus_a";
- clocks = <&xo_board>, <&xo_board>;
};
apcs_glb: mailbox@17911000 {
diff --git a/dts/upstream/src/arm64/qcom/sdm632-fairphone-fp3.dts b/dts/upstream/src/arm64/qcom/sdm632-fairphone-fp3.dts
index 301eca9..057579a 100644
--- a/dts/upstream/src/arm64/qcom/sdm632-fairphone-fp3.dts
+++ b/dts/upstream/src/arm64/qcom/sdm632-fairphone-fp3.dts
@@ -80,6 +80,10 @@
};
};
+&lpass {
+ status = "okay";
+};
+
&pm8953_resin {
status = "okay";
linux,code = <KEY_VOLUMEDOWN>;
@@ -239,3 +243,18 @@
&usb3_dwc3 {
dr_mode = "peripheral";
};
+
+&wcnss {
+ status = "okay";
+
+ vddpx-supply = <&pm8953_l5>;
+};
+
+&wcnss_iris {
+ compatible = "qcom,wcn3680";
+
+ vddxo-supply = <&pm8953_l7>;
+ vddrfa-supply = <&pm8953_l19>;
+ vddpa-supply = <&pm8953_l9>;
+ vdddig-supply = <&pm8953_l5>;
+};
diff --git a/dts/upstream/src/arm64/qcom/sdm670.dtsi b/dts/upstream/src/arm64/qcom/sdm670.dtsi
index ba2043d..4d7b77a 100644
--- a/dts/upstream/src/arm64/qcom/sdm670.dtsi
+++ b/dts/upstream/src/arm64/qcom/sdm670.dtsi
@@ -6,6 +6,7 @@
* Copyright (c) 2022, Richard Acayan. All rights reserved.
*/
+#include <dt-bindings/clock/qcom,dispcc-sdm845.h>
#include <dt-bindings/clock/qcom,gcc-sdm845.h>
#include <dt-bindings/clock/qcom,rpmh.h>
#include <dt-bindings/dma/qcom-gpi.h>
@@ -400,6 +401,30 @@
};
};
+ dsi_opp_table: opp-table-dsi {
+ compatible = "operating-points-v2";
+
+ opp-19200000 {
+ opp-hz = /bits/ 64 <19200000>;
+ required-opps = <&rpmhpd_opp_min_svs>;
+ };
+
+ opp-180000000 {
+ opp-hz = /bits/ 64 <180000000>;
+ required-opps = <&rpmhpd_opp_low_svs>;
+ };
+
+ opp-275000000 {
+ opp-hz = /bits/ 64 <275000000>;
+ required-opps = <&rpmhpd_opp_svs>;
+ };
+
+ opp-358000000 {
+ opp-hz = /bits/ 64 <358000000>;
+ required-opps = <&rpmhpd_opp_svs_l1>;
+ };
+ };
+
psci {
compatible = "arm,psci-1.0";
method = "smc";
@@ -1295,10 +1320,10 @@
<&gcc GCC_USB30_PRIM_MASTER_CLK>;
assigned-clock-rates = <19200000>, <150000000>;
- interrupts = <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 486 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 488 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 489 IRQ_TYPE_LEVEL_HIGH>;
+ interrupts-extended = <&intc GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>,
+ <&pdc 6 IRQ_TYPE_LEVEL_HIGH>,
+ <&pdc 8 IRQ_TYPE_EDGE_BOTH>,
+ <&pdc 9 IRQ_TYPE_EDGE_BOTH>;
interrupt-names = "hs_phy_irq", "ss_phy_irq",
"dm_hs_phy_irq", "dp_hs_phy_irq";
@@ -1353,6 +1378,273 @@
#interrupt-cells = <4>;
};
+ mdss: display-subsystem@ae00000 {
+ compatible = "qcom,sdm670-mdss";
+ reg = <0 0x0ae00000 0 0x1000>;
+ reg-names = "mdss";
+
+ power-domains = <&dispcc MDSS_GDSC>;
+
+ clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>,
+ <&dispcc DISP_CC_MDSS_MDP_CLK>;
+ clock-names = "iface", "core";
+
+ interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-controller;
+ #interrupt-cells = <1>;
+
+ interconnects = <&mmss_noc MASTER_MDP_PORT0 0 &mem_noc SLAVE_EBI_CH0 0>,
+ <&mmss_noc MASTER_MDP_PORT1 0 &mem_noc SLAVE_EBI_CH0 0>;
+ interconnect-names = "mdp0-mem", "mdp1-mem";
+
+ iommus = <&apps_smmu 0x880 0x8>,
+ <&apps_smmu 0xc80 0x8>;
+
+ #address-cells = <2>;
+ #size-cells = <2>;
+ ranges;
+
+ status = "disabled";
+
+ mdss_mdp: display-controller@ae01000 {
+ compatible = "qcom,sdm670-dpu";
+ reg = <0 0x0ae01000 0 0x8f000>,
+ <0 0x0aeb0000 0 0x2008>;
+ reg-names = "mdp", "vbif";
+
+ clocks = <&gcc GCC_DISP_AXI_CLK>,
+ <&dispcc DISP_CC_MDSS_AHB_CLK>,
+ <&dispcc DISP_CC_MDSS_AXI_CLK>,
+ <&dispcc DISP_CC_MDSS_MDP_CLK>,
+ <&dispcc DISP_CC_MDSS_VSYNC_CLK>;
+ clock-names = "gcc-bus", "iface", "bus", "core", "vsync";
+
+ assigned-clocks = <&dispcc DISP_CC_MDSS_VSYNC_CLK>;
+ assigned-clock-rates = <19200000>;
+ operating-points-v2 = <&mdp_opp_table>;
+ power-domains = <&rpmhpd SDM670_CX>;
+
+ interrupt-parent = <&mdss>;
+ interrupts = <0>;
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+ dpu_intf0_out: endpoint {
+ remote-endpoint = <&mdss_dsi0_in>;
+ };
+ };
+
+ port@1 {
+ reg = <1>;
+ dpu_intf1_out: endpoint {
+ remote-endpoint = <&mdss_dsi1_in>;
+ };
+ };
+ };
+
+ mdp_opp_table: opp-table {
+ compatible = "operating-points-v2";
+
+ opp-19200000 {
+ opp-hz = /bits/ 64 <19200000>;
+ required-opps = <&rpmhpd_opp_min_svs>;
+ };
+
+ opp-171428571 {
+ opp-hz = /bits/ 64 <171428571>;
+ required-opps = <&rpmhpd_opp_low_svs>;
+ };
+
+ opp-358000000 {
+ opp-hz = /bits/ 64 <358000000>;
+ required-opps = <&rpmhpd_opp_svs_l1>;
+ };
+
+ opp-430000000 {
+ opp-hz = /bits/ 64 <430000000>;
+ required-opps = <&rpmhpd_opp_nom>;
+ };
+ };
+ };
+
+ mdss_dsi0: dsi@ae94000 {
+ compatible = "qcom,sdm670-dsi-ctrl",
+ "qcom,mdss-dsi-ctrl";
+ reg = <0 0x0ae94000 0 0x400>;
+ reg-names = "dsi_ctrl";
+
+ interrupt-parent = <&mdss>;
+ interrupts = <4>;
+
+ clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK>,
+ <&dispcc DISP_CC_MDSS_BYTE0_INTF_CLK>,
+ <&dispcc DISP_CC_MDSS_PCLK0_CLK>,
+ <&dispcc DISP_CC_MDSS_ESC0_CLK>,
+ <&dispcc DISP_CC_MDSS_AHB_CLK>,
+ <&dispcc DISP_CC_MDSS_AXI_CLK>;
+ clock-names = "byte",
+ "byte_intf",
+ "pixel",
+ "core",
+ "iface",
+ "bus";
+ assigned-clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK_SRC>,
+ <&dispcc DISP_CC_MDSS_PCLK0_CLK_SRC>;
+ assigned-clock-parents = <&mdss_dsi0_phy 0>,
+ <&mdss_dsi0_phy 1>;
+
+ operating-points-v2 = <&dsi_opp_table>;
+ power-domains = <&rpmhpd SDM670_CX>;
+
+ phys = <&mdss_dsi0_phy>;
+
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ status = "disabled";
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+ mdss_dsi0_in: endpoint {
+ remote-endpoint = <&dpu_intf0_out>;
+ };
+ };
+
+ port@1 {
+ reg = <1>;
+ mdss_dsi0_out: endpoint {
+ };
+ };
+ };
+ };
+
+ mdss_dsi0_phy: phy@ae94400 {
+ compatible = "qcom,dsi-phy-10nm";
+ reg = <0 0x0ae94400 0 0x200>,
+ <0 0x0ae94600 0 0x280>,
+ <0 0x0ae94a00 0 0x1e0>;
+ reg-names = "dsi_phy",
+ "dsi_phy_lane",
+ "dsi_pll";
+
+ #clock-cells = <1>;
+ #phy-cells = <0>;
+
+ clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>,
+ <&rpmhcc RPMH_CXO_CLK>;
+ clock-names = "iface", "ref";
+
+ status = "disabled";
+ };
+
+ mdss_dsi1: dsi@ae96000 {
+ compatible = "qcom,sdm670-dsi-ctrl",
+ "qcom,mdss-dsi-ctrl";
+ reg = <0 0x0ae96000 0 0x400>;
+ reg-names = "dsi_ctrl";
+
+ interrupt-parent = <&mdss>;
+ interrupts = <5>;
+
+ clocks = <&dispcc DISP_CC_MDSS_BYTE1_CLK>,
+ <&dispcc DISP_CC_MDSS_BYTE1_INTF_CLK>,
+ <&dispcc DISP_CC_MDSS_PCLK1_CLK>,
+ <&dispcc DISP_CC_MDSS_ESC1_CLK>,
+ <&dispcc DISP_CC_MDSS_AHB_CLK>,
+ <&dispcc DISP_CC_MDSS_AXI_CLK>;
+ clock-names = "byte",
+ "byte_intf",
+ "pixel",
+ "core",
+ "iface",
+ "bus";
+ assigned-clocks = <&dispcc DISP_CC_MDSS_BYTE1_CLK_SRC>,
+ <&dispcc DISP_CC_MDSS_PCLK1_CLK_SRC>;
+ assigned-clock-parents = <&mdss_dsi1_phy 0>, <&mdss_dsi1_phy 1>;
+
+ operating-points-v2 = <&dsi_opp_table>;
+ power-domains = <&rpmhpd SDM670_CX>;
+
+ phys = <&mdss_dsi1_phy>;
+
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ status = "disabled";
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+ mdss_dsi1_in: endpoint {
+ remote-endpoint = <&dpu_intf1_out>;
+ };
+ };
+
+ port@1 {
+ reg = <1>;
+ mdss_dsi1_out: endpoint {
+ };
+ };
+ };
+ };
+
+ mdss_dsi1_phy: phy@ae96400 {
+ compatible = "qcom,dsi-phy-10nm";
+ reg = <0 0x0ae96400 0 0x200>,
+ <0 0x0ae96600 0 0x280>,
+ <0 0x0ae96a00 0 0x10e>;
+ reg-names = "dsi_phy",
+ "dsi_phy_lane",
+ "dsi_pll";
+
+ #clock-cells = <1>;
+ #phy-cells = <0>;
+
+ clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>,
+ <&rpmhcc RPMH_CXO_CLK>;
+ clock-names = "iface", "ref";
+
+ status = "disabled";
+ };
+ };
+
+ dispcc: clock-controller@af00000 {
+ compatible = "qcom,sdm845-dispcc";
+ reg = <0 0x0af00000 0 0x10000>;
+ clocks = <&rpmhcc RPMH_CXO_CLK>,
+ <&gcc GCC_DISP_GPLL0_CLK_SRC>,
+ <&gcc GCC_DISP_GPLL0_DIV_CLK_SRC>,
+ <&mdss_dsi0_phy 0>,
+ <&mdss_dsi0_phy 1>,
+ <&mdss_dsi1_phy 0>,
+ <&mdss_dsi1_phy 1>,
+ <0>,
+ <0>;
+ clock-names = "bi_tcxo",
+ "gcc_disp_gpll0_clk_src",
+ "gcc_disp_gpll0_div_clk_src",
+ "dsi0_phy_pll_out_byteclk",
+ "dsi0_phy_pll_out_dsiclk",
+ "dsi1_phy_pll_out_byteclk",
+ "dsi1_phy_pll_out_dsiclk",
+ "dp_link_clk_divsel_ten",
+ "dp_vco_divided_clk_src_mux";
+ #clock-cells = <1>;
+ #reset-cells = <1>;
+ #power-domain-cells = <1>;
+ };
+
apps_smmu: iommu@15000000 {
compatible = "qcom,sdm670-smmu-500", "qcom,smmu-500", "arm,mmu-500";
reg = <0 0x15000000 0 0x80000>;
@@ -1532,7 +1824,7 @@
};
cpufreq_hw: cpufreq@17d43000 {
- compatible = "qcom,cpufreq-hw";
+ compatible = "qcom,sdm670-cpufreq-hw", "qcom,cpufreq-hw";
reg = <0 0x17d43000 0 0x1400>, <0 0x17d45800 0 0x1400>;
reg-names = "freq-domain0", "freq-domain1";
diff --git a/dts/upstream/src/arm64/qcom/sdm845-db845c.dts b/dts/upstream/src/arm64/qcom/sdm845-db845c.dts
index c7eba6c..ab62204 100644
--- a/dts/upstream/src/arm64/qcom/sdm845-db845c.dts
+++ b/dts/upstream/src/arm64/qcom/sdm845-db845c.dts
@@ -67,8 +67,8 @@
function = LED_FUNCTION_INDICATOR;
color = <LED_COLOR_ID_GREEN>;
gpios = <&pm8998_gpios 13 GPIO_ACTIVE_HIGH>;
- linux,default-trigger = "panic-indicator";
default-state = "off";
+ panic-indicator;
};
led-1 {
@@ -1130,7 +1130,7 @@
vdd-rx-supply = <&vreg_s4a_1p8>;
vdd-io-supply = <&vreg_s4a_1p8>;
- swm: swm@c85 {
+ swm: soundwire@c85 {
left_spkr: speaker@0,1 {
compatible = "sdw10217201000";
reg = <0 1>;
diff --git a/dts/upstream/src/arm64/qcom/sdm845-oneplus-common.dtsi b/dts/upstream/src/arm64/qcom/sdm845-oneplus-common.dtsi
index b523b5f..e821103 100644
--- a/dts/upstream/src/arm64/qcom/sdm845-oneplus-common.dtsi
+++ b/dts/upstream/src/arm64/qcom/sdm845-oneplus-common.dtsi
@@ -8,6 +8,7 @@
/dts-v1/;
#include <dt-bindings/input/linux-event-codes.h>
+#include <dt-bindings/leds/common.h>
#include <dt-bindings/regulator/qcom,rpmh-regulator.h>
#include <dt-bindings/sound/qcom,q6afe.h>
#include <dt-bindings/sound/qcom,q6asm.h>
@@ -484,6 +485,28 @@
status = "okay";
};
+&pmi8998_flash {
+ status = "okay";
+
+ led-0 {
+ function = LED_FUNCTION_FLASH;
+ color = <LED_COLOR_ID_WHITE>;
+ led-sources = <1>;
+ led-max-microamp = <500000>;
+ flash-max-microamp = <1500000>;
+ flash-max-timeout-us = <1280000>;
+ };
+
+ led-1 {
+ function = LED_FUNCTION_FLASH;
+ color = <LED_COLOR_ID_YELLOW>;
+ led-sources = <2>;
+ led-max-microamp = <500000>;
+ flash-max-microamp = <1500000>;
+ flash-max-timeout-us = <1280000>;
+ };
+};
+
&q6afedai {
qi2s@22 {
reg = <22>;
diff --git a/dts/upstream/src/arm64/qcom/sdm845-wcd9340.dtsi b/dts/upstream/src/arm64/qcom/sdm845-wcd9340.dtsi
index c15d488..6172cd1 100644
--- a/dts/upstream/src/arm64/qcom/sdm845-wcd9340.dtsi
+++ b/dts/upstream/src/arm64/qcom/sdm845-wcd9340.dtsi
@@ -54,7 +54,7 @@
reg = <0x42 0x2>;
};
- swm: swm@c85 {
+ swm: soundwire@c85 {
compatible = "qcom,soundwire-v1.3.0";
reg = <0xc85 0x40>;
interrupts-extended = <&wcd9340 20>;
diff --git a/dts/upstream/src/arm64/qcom/sdm845-xiaomi-beryllium-common.dtsi b/dts/upstream/src/arm64/qcom/sdm845-xiaomi-beryllium-common.dtsi
index 93b1582..617b17b 100644
--- a/dts/upstream/src/arm64/qcom/sdm845-xiaomi-beryllium-common.dtsi
+++ b/dts/upstream/src/arm64/qcom/sdm845-xiaomi-beryllium-common.dtsi
@@ -355,6 +355,28 @@
status = "okay";
};
+&pmi8998_flash {
+ status = "okay";
+
+ led-0 {
+ function = LED_FUNCTION_FLASH;
+ color = <LED_COLOR_ID_WHITE>;
+ led-sources = <1>;
+ led-max-microamp = <500000>;
+ flash-max-microamp = <1500000>;
+ flash-max-timeout-us = <1280000>;
+ };
+
+ led-1 {
+ function = LED_FUNCTION_FLASH;
+ color = <LED_COLOR_ID_YELLOW>;
+ led-sources = <2>;
+ led-max-microamp = <500000>;
+ flash-max-microamp = <1500000>;
+ flash-max-timeout-us = <1280000>;
+ };
+};
+
&pm8998_resin {
linux,code = <KEY_VOLUMEDOWN>;
status = "okay";
diff --git a/dts/upstream/src/arm64/qcom/sdm845.dtsi b/dts/upstream/src/arm64/qcom/sdm845.dtsi
index bf5e6eb..c224482 100644
--- a/dts/upstream/src/arm64/qcom/sdm845.dtsi
+++ b/dts/upstream/src/arm64/qcom/sdm845.dtsi
@@ -2306,7 +2306,7 @@
};
};
- pcie0: pci@1c00000 {
+ pcie0: pcie@1c00000 {
compatible = "qcom,pcie-sdm845";
reg = <0 0x01c00000 0 0x2000>,
<0 0x60000000 0 0xf1d>,
@@ -2405,7 +2405,7 @@
status = "disabled";
};
- pcie1: pci@1c08000 {
+ pcie1: pcie@1c08000 {
compatible = "qcom,pcie-sdm845";
reg = <0 0x01c08000 0 0x2000>,
<0 0x40000000 0 0xf1d>,
@@ -2565,7 +2565,7 @@
<0 0x01d90000 0 0x8000>;
reg-names = "std", "ice";
interrupts = <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH>;
- phys = <&ufs_mem_phy_lanes>;
+ phys = <&ufs_mem_phy>;
phy-names = "ufsphy";
lanes-per-direction = <2>;
power-domains = <&gcc UFS_PHY_GDSC>;
@@ -2595,30 +2595,50 @@
<&gcc GCC_UFS_PHY_RX_SYMBOL_0_CLK>,
<&gcc GCC_UFS_PHY_RX_SYMBOL_1_CLK>,
<&gcc GCC_UFS_PHY_ICE_CORE_CLK>;
- freq-table-hz =
- <50000000 200000000>,
- <0 0>,
- <0 0>,
- <37500000 150000000>,
- <0 0>,
- <0 0>,
- <0 0>,
- <0 0>,
- <75000000 300000000>;
+
+ operating-points-v2 = <&ufs_opp_table>;
interconnects = <&aggre1_noc MASTER_UFS_MEM 0 &mem_noc SLAVE_EBI1 0>,
<&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_UFS_MEM_CFG 0>;
interconnect-names = "ufs-ddr", "cpu-ufs";
status = "disabled";
+
+ ufs_opp_table: opp-table {
+ compatible = "operating-points-v2";
+
+ opp-50000000 {
+ opp-hz = /bits/ 64 <50000000>,
+ /bits/ 64 <0>,
+ /bits/ 64 <0>,
+ /bits/ 64 <37500000>,
+ /bits/ 64 <0>,
+ /bits/ 64 <0>,
+ /bits/ 64 <0>,
+ /bits/ 64 <0>,
+ /bits/ 64 <75000000>;
+ required-opps = <&rpmhpd_opp_low_svs>;
+ };
+
+ opp-200000000 {
+ opp-hz = /bits/ 64 <200000000>,
+ /bits/ 64 <0>,
+ /bits/ 64 <0>,
+ /bits/ 64 <150000000>,
+ /bits/ 64 <0>,
+ /bits/ 64 <0>,
+ /bits/ 64 <0>,
+ /bits/ 64 <0>,
+ /bits/ 64 <300000000>;
+ required-opps = <&rpmhpd_opp_nom>;
+ };
+ };
};
ufs_mem_phy: phy@1d87000 {
compatible = "qcom,sdm845-qmp-ufs-phy";
- reg = <0 0x01d87000 0 0x18c>;
- #address-cells = <2>;
- #size-cells = <2>;
- ranges;
+ reg = <0 0x01d87000 0 0x1000>;
+
clock-names = "ref",
"ref_aux";
clocks = <&gcc GCC_UFS_MEM_CLKREF_CLK>,
@@ -2626,16 +2646,9 @@
resets = <&ufs_mem_hc 0>;
reset-names = "ufsphy";
- status = "disabled";
- ufs_mem_phy_lanes: phy@1d87400 {
- reg = <0 0x01d87400 0 0x108>,
- <0 0x01d87600 0 0x1e0>,
- <0 0x01d87c00 0 0x1dc>,
- <0 0x01d87800 0 0x108>,
- <0 0x01d87a00 0 0x1e0>;
- #phy-cells = <0>;
- };
+ #phy-cells = <0>;
+ status = "disabled";
};
cryptobam: dma-controller@1dc4000 {
@@ -3545,11 +3558,8 @@
};
in-ports {
- #address-cells = <1>;
- #size-cells = <0>;
- port@1 {
- reg = <1>;
+ port {
etf_in: endpoint {
remote-endpoint =
<&merge_funnel_out>;
@@ -4000,33 +4010,28 @@
usb_2_qmpphy: phy@88eb000 {
compatible = "qcom,sdm845-qmp-usb3-uni-phy";
- reg = <0 0x088eb000 0 0x18c>;
- status = "disabled";
- #address-cells = <2>;
- #size-cells = <2>;
- ranges;
+ reg = <0 0x088eb000 0 0x1000>;
clocks = <&gcc GCC_USB3_SEC_PHY_AUX_CLK>,
<&gcc GCC_USB_PHY_CFG_AHB2PHY_CLK>,
<&gcc GCC_USB3_SEC_CLKREF_CLK>,
- <&gcc GCC_USB3_SEC_PHY_COM_AUX_CLK>;
- clock-names = "aux", "cfg_ahb", "ref", "com_aux";
+ <&gcc GCC_USB3_SEC_PHY_COM_AUX_CLK>,
+ <&gcc GCC_USB3_SEC_PHY_PIPE_CLK>;
+ clock-names = "aux",
+ "cfg_ahb",
+ "ref",
+ "com_aux",
+ "pipe";
+ clock-output-names = "usb3_uni_phy_pipe_clk_src";
+ #clock-cells = <0>;
+ #phy-cells = <0>;
- resets = <&gcc GCC_USB3PHY_PHY_SEC_BCR>,
- <&gcc GCC_USB3_PHY_SEC_BCR>;
- reset-names = "phy", "common";
+ resets = <&gcc GCC_USB3_PHY_SEC_BCR>,
+ <&gcc GCC_USB3PHY_PHY_SEC_BCR>;
+ reset-names = "phy",
+ "phy_phy";
- usb_2_ssphy: phy@88eb200 {
- reg = <0 0x088eb200 0 0x128>,
- <0 0x088eb400 0 0x1fc>,
- <0 0x088eb800 0 0x218>,
- <0 0x088eb600 0 0x70>;
- #clock-cells = <0>;
- #phy-cells = <0>;
- clocks = <&gcc GCC_USB3_SEC_PHY_PIPE_CLK>;
- clock-names = "pipe0";
- clock-output-names = "usb3_uni_phy_pipe_clk_src";
- };
+ status = "disabled";
};
usb_1: usb@a6f8800 {
@@ -4053,10 +4058,10 @@
<&gcc GCC_USB30_PRIM_MASTER_CLK>;
assigned-clock-rates = <19200000>, <150000000>;
- interrupts = <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 486 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 488 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 489 IRQ_TYPE_LEVEL_HIGH>;
+ interrupts-extended = <&intc GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>,
+ <&pdc_intc 6 IRQ_TYPE_LEVEL_HIGH>,
+ <&pdc_intc 8 IRQ_TYPE_EDGE_BOTH>,
+ <&pdc_intc 9 IRQ_TYPE_EDGE_BOTH>;
interrupt-names = "hs_phy_irq", "ss_phy_irq",
"dm_hs_phy_irq", "dp_hs_phy_irq";
@@ -4104,10 +4109,10 @@
<&gcc GCC_USB30_SEC_MASTER_CLK>;
assigned-clock-rates = <19200000>, <150000000>;
- interrupts = <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 487 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 490 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 491 IRQ_TYPE_LEVEL_HIGH>;
+ interrupts-extended = <&intc GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>,
+ <&pdc_intc 7 IRQ_TYPE_LEVEL_HIGH>,
+ <&pdc_intc 10 IRQ_TYPE_EDGE_BOTH>,
+ <&pdc_intc 11 IRQ_TYPE_EDGE_BOTH>;
interrupt-names = "hs_phy_irq", "ss_phy_irq",
"dm_hs_phy_irq", "dp_hs_phy_irq";
@@ -4126,7 +4131,7 @@
iommus = <&apps_smmu 0x760 0>;
snps,dis_u2_susphy_quirk;
snps,dis_enblslpm_quirk;
- phys = <&usb_2_hsphy>, <&usb_2_ssphy>;
+ phys = <&usb_2_hsphy>, <&usb_2_qmpphy>;
phy-names = "usb2-phy", "usb3-phy";
};
};
@@ -5088,7 +5093,7 @@
compatible = "qcom,apss-wdt-sdm845", "qcom,kpss-wdt";
reg = <0 0x17980000 0 0x1000>;
clocks = <&sleep_clk>;
- interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>;
+ interrupts = <GIC_SPI 0 IRQ_TYPE_EDGE_RISING>;
};
apss_shared: mailbox@17990000 {
diff --git a/dts/upstream/src/arm64/qcom/sdm850-lenovo-yoga-c630.dts b/dts/upstream/src/arm64/qcom/sdm850-lenovo-yoga-c630.dts
index 92a812b..47dc42f 100644
--- a/dts/upstream/src/arm64/qcom/sdm850-lenovo-yoga-c630.dts
+++ b/dts/upstream/src/arm64/qcom/sdm850-lenovo-yoga-c630.dts
@@ -392,6 +392,8 @@
hid-descr-addr = <0x20>;
interrupts-extended = <&tlmm 37 IRQ_TYPE_LEVEL_HIGH>;
+
+ wakeup-source;
};
};
@@ -408,6 +410,8 @@
pinctrl-names = "default";
pinctrl-0 = <&i2c5_hid_active>;
+
+ wakeup-source;
};
};
@@ -482,6 +486,8 @@
pinctrl-names = "default";
pinctrl-0 = <&i2c11_hid_active>;
+
+ wakeup-source;
};
};
@@ -797,7 +803,7 @@
qcom,mbhc-headset-vthreshold-microvolt = <1700000>;
qcom,mbhc-headphone-vthreshold-microvolt = <50000>;
- swm: swm@c85 {
+ swm: soundwire@c85 {
left_spkr: speaker@0,3 {
compatible = "sdw10217211000";
reg = <0 3>;
diff --git a/dts/upstream/src/arm64/qcom/sdm850-samsung-w737.dts b/dts/upstream/src/arm64/qcom/sdm850-samsung-w737.dts
index 5438373..2621783 100644
--- a/dts/upstream/src/arm64/qcom/sdm850-samsung-w737.dts
+++ b/dts/upstream/src/arm64/qcom/sdm850-samsung-w737.dts
@@ -658,7 +658,7 @@
qcom,mbhc-headset-vthreshold-microvolt = <1700000>;
qcom,mbhc-headphone-vthreshold-microvolt = <50000>;
- swm: swm@c85 {
+ swm: soundwire@c85 {
left_spkr: speaker@0,3 {
compatible = "sdw10217211000";
reg = <0 3>;
diff --git a/dts/upstream/src/arm64/qcom/sdx75-idp.dts b/dts/upstream/src/arm64/qcom/sdx75-idp.dts
index a14e065..f76e72f 100644
--- a/dts/upstream/src/arm64/qcom/sdx75-idp.dts
+++ b/dts/upstream/src/arm64/qcom/sdx75-idp.dts
@@ -250,6 +250,11 @@
stdout-path = "serial0:115200n8";
};
+&pm7550ba_eusb2_repeater {
+ vdd18-supply = <&vreg_l5b_1p776>;
+ vdd3-supply = <&vreg_l10b_3p08>;
+};
+
&qupv3_id_0 {
status = "okay";
};
@@ -261,3 +266,27 @@
&uart1 {
status = "okay";
};
+
+&usb {
+ status = "okay";
+};
+
+&usb_dwc3 {
+ dr_mode = "peripheral";
+};
+
+&usb_hsphy {
+ vdd-supply = <&vreg_l4b_0p88>;
+ vdda12-supply = <&vreg_l1b_1p2>;
+
+ phys = <&pm7550ba_eusb2_repeater>;
+
+ status = "okay";
+};
+
+&usb_qmpphy {
+ vdda-phy-supply = <&vreg_l4b_0p88>;
+ vdda-pll-supply = <&vreg_l1b_1p2>;
+
+ status = "okay";
+};
diff --git a/dts/upstream/src/arm64/qcom/sdx75.dtsi b/dts/upstream/src/arm64/qcom/sdx75.dtsi
index e180aa4..7dbdf8c 100644
--- a/dts/upstream/src/arm64/qcom/sdx75.dtsi
+++ b/dts/upstream/src/arm64/qcom/sdx75.dtsi
@@ -8,6 +8,8 @@
#include <dt-bindings/clock/qcom,rpmh.h>
#include <dt-bindings/clock/qcom,sdx75-gcc.h>
+#include <dt-bindings/interconnect/qcom,icc.h>
+#include <dt-bindings/interconnect/qcom,sdx75.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/power/qcom,rpmhpd.h>
#include <dt-bindings/power/qcom-rpmpd.h>
@@ -203,6 +205,19 @@
};
};
+ clk_virt: interconnect-0 {
+ compatible = "qcom,sdx75-clk-virt";
+ #interconnect-cells = <2>;
+ qcom,bcm-voters = <&apps_bcm_voter>;
+ clocks = <&rpmhcc RPMH_QPIC_CLK>;
+ };
+
+ mc_virt: interconnect-1 {
+ compatible = "qcom,sdx75-mc-virt";
+ #interconnect-cells = <2>;
+ qcom,bcm-voters = <&apps_bcm_voter>;
+ };
+
memory@80000000 {
device_type = "memory";
reg = <0x0 0x80000000 0x0 0x0>;
@@ -434,6 +449,9 @@
clock-names = "m-ahb",
"s-ahb";
iommus = <&apps_smmu 0xe3 0x0>;
+ interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS
+ &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>;
+ interconnect-names = "qup-core";
#address-cells = <2>;
#size-cells = <2>;
ranges;
@@ -444,6 +462,12 @@
reg = <0x0 0x00984000 0x0 0x4000>;
clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>;
clock-names = "se";
+ interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS
+ &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>,
+ <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
+ &system_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>;
+ interconnect-names = "qup-core",
+ "qup-config";
interrupts = <GIC_SPI 338 IRQ_TYPE_LEVEL_HIGH>;
pinctrl-0 = <&qupv3_se1_2uart_active>;
pinctrl-1 = <&qupv3_se1_2uart_sleep>;
@@ -453,12 +477,144 @@
};
};
+ usb_hsphy: phy@ff4000 {
+ compatible = "qcom,sdx75-snps-eusb2-phy", "qcom,sm8550-snps-eusb2-phy";
+ reg = <0x0 0x00ff4000 0x0 0x154>;
+ #phy-cells = <0>;
+
+ clocks = <&rpmhcc RPMH_CXO_CLK>;
+ clock-names = "ref";
+
+ resets = <&gcc GCC_QUSB2PHY_BCR>;
+
+ status = "disabled";
+ };
+
+ usb_qmpphy: phy@ff6000 {
+ compatible = "qcom,sdx75-qmp-usb3-uni-phy";
+ reg = <0x0 0x00ff6000 0x0 0x2000>;
+
+ clocks = <&gcc GCC_USB3_PHY_AUX_CLK>,
+ <&gcc GCC_USB2_CLKREF_EN>,
+ <&gcc GCC_USB_PHY_CFG_AHB2PHY_CLK>,
+ <&gcc GCC_USB3_PHY_PIPE_CLK>;
+ clock-names = "aux",
+ "ref",
+ "cfg_ahb",
+ "pipe";
+
+ power-domains = <&gcc GCC_USB3_PHY_GDSC>;
+
+ resets = <&gcc GCC_USB3_PHY_BCR>,
+ <&gcc GCC_USB3PHY_PHY_BCR>;
+ reset-names = "phy",
+ "phy_phy";
+
+ #clock-cells = <0>;
+ clock-output-names = "usb3_uni_phy_pipe_clk_src";
+
+ #phy-cells = <0>;
+
+ status = "disabled";
+ };
+
+ system_noc: interconnect@1640000 {
+ compatible = "qcom,sdx75-system-noc";
+ reg = <0x0 0x01640000 0x0 0x4b400>;
+ #interconnect-cells = <2>;
+ qcom,bcm-voters = <&apps_bcm_voter>;
+ };
+
+ pcie_anoc: interconnect@16c0000 {
+ compatible = "qcom,sdx75-pcie-anoc";
+ reg = <0x0 0x016c0000 0x0 0x14200>;
+ #interconnect-cells = <2>;
+ qcom,bcm-voters = <&apps_bcm_voter>;
+ };
+
tcsr_mutex: hwlock@1f40000 {
compatible = "qcom,tcsr-mutex";
reg = <0x0 0x01f40000 0x0 0x40000>;
#hwlock-cells = <1>;
};
+ usb: usb@a6f8800 {
+ compatible = "qcom,sdx75-dwc3", "qcom,dwc3";
+ reg = <0x0 0x0a6f8800 0x0 0x400>;
+ #address-cells = <2>;
+ #size-cells = <2>;
+ ranges;
+
+ clocks = <&gcc GCC_USB30_SLV_AHB_CLK>,
+ <&gcc GCC_USB30_MASTER_CLK>,
+ <&gcc GCC_USB30_MSTR_AXI_CLK>,
+ <&gcc GCC_USB30_SLEEP_CLK>,
+ <&gcc GCC_USB30_MOCK_UTMI_CLK>;
+ clock-names = "cfg_noc",
+ "core",
+ "iface",
+ "sleep",
+ "mock_utmi";
+
+ assigned-clocks = <&gcc GCC_USB30_MOCK_UTMI_CLK>,
+ <&gcc GCC_USB30_MASTER_CLK>;
+ assigned-clock-rates = <19200000>, <200000000>;
+
+ interrupts-extended = <&intc GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>,
+ <&pdc 17 IRQ_TYPE_LEVEL_HIGH>,
+ <&pdc 9 IRQ_TYPE_EDGE_RISING>,
+ <&pdc 10 IRQ_TYPE_EDGE_RISING>;
+ interrupt-names = "hs_phy_irq",
+ "ss_phy_irq",
+ "dm_hs_phy_irq",
+ "dp_hs_phy_irq";
+
+ power-domains = <&gcc GCC_USB30_GDSC>;
+
+ resets = <&gcc GCC_USB30_BCR>;
+
+ interconnects = <&system_noc MASTER_USB3_0 QCOM_ICC_TAG_ALWAYS
+ &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>,
+ <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
+ &system_noc SLAVE_USB3 QCOM_ICC_TAG_ALWAYS>;
+ interconnect-names = "usb-ddr",
+ "apps-usb";
+
+ status = "disabled";
+
+ usb_dwc3: usb@a600000 {
+ compatible = "snps,dwc3";
+ reg = <0x0 0x0a600000 0x0 0xcd00>;
+ interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>;
+ iommus = <&apps_smmu 0x80 0x0>;
+ snps,dis_u2_susphy_quirk;
+ snps,dis_enblslpm_quirk;
+ phys = <&usb_hsphy>,
+ <&usb_qmpphy>;
+ phy-names = "usb2-phy",
+ "usb3-phy";
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+
+ usb_1_dwc3_hs: endpoint {
+ };
+ };
+
+ port@1 {
+ reg = <1>;
+
+ usb_1_dwc3_ss: endpoint {
+ };
+ };
+ };
+ };
+ };
+
pdc: interrupt-controller@b220000 {
compatible = "qcom,sdx75-pdc", "qcom,pdc";
reg = <0x0 0xb220000 0x0 0x30000>,
@@ -733,6 +889,20 @@
#freq-domain-cells = <1>;
#clock-cells = <1>;
};
+
+ dc_noc: interconnect@190e0000 {
+ compatible = "qcom,sdx75-dc-noc";
+ reg = <0x0 0x190e0000 0x0 0x8200>;
+ #interconnect-cells = <2>;
+ qcom,bcm-voters = <&apps_bcm_voter>;
+ };
+
+ gem_noc: interconnect@19100000 {
+ compatible = "qcom,sdx75-gem-noc";
+ reg = <0x0 0x19100000 0x0 0x34080>;
+ #interconnect-cells = <2>;
+ qcom,bcm-voters = <&apps_bcm_voter>;
+ };
};
timer {
diff --git a/dts/upstream/src/arm64/qcom/sm4450-qrd.dts b/dts/upstream/src/arm64/qcom/sm4450-qrd.dts
index 00a1c81..866e937 100644
--- a/dts/upstream/src/arm64/qcom/sm4450-qrd.dts
+++ b/dts/upstream/src/arm64/qcom/sm4450-qrd.dts
@@ -10,9 +10,23 @@
model = "Qualcomm Technologies, Inc. SM4450 QRD";
compatible = "qcom,sm4450-qrd", "qcom,sm4450";
- aliases { };
+ aliases {
+ serial0 = &uart7;
+ };
chosen {
- bootargs = "console=hvc0";
+ stdout-path = "serial0:115200n8";
};
};
+
+&qupv3_id_0 {
+ status = "okay";
+};
+
+&tlmm {
+ gpio-reserved-ranges = <0 4>; /* NFC eSE SPI */
+};
+
+&uart7 {
+ status = "okay";
+};
diff --git a/dts/upstream/src/arm64/qcom/sm4450.dtsi b/dts/upstream/src/arm64/qcom/sm4450.dtsi
index c4e5b33..3e7ae3b 100644
--- a/dts/upstream/src/arm64/qcom/sm4450.dtsi
+++ b/dts/upstream/src/arm64/qcom/sm4450.dtsi
@@ -3,8 +3,11 @@
* Copyright (c) 2023, Qualcomm Innovation Center, Inc. All rights reserved.
*/
+#include <dt-bindings/clock/qcom,rpmh.h>
+#include <dt-bindings/clock/qcom,sm4450-gcc.h>
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
+#include <dt-bindings/soc/qcom,rpmh-rsc.h>
/ {
interrupt-parent = <&intc>;
@@ -328,6 +331,18 @@
};
};
+ reserved_memory: reserved-memory {
+ #address-cells = <2>;
+ #size-cells = <2>;
+ ranges;
+
+ aop_cmd_db_mem: cmd-db@80860000 {
+ compatible = "qcom,cmd-db";
+ reg = <0x0 0x80860000 0x0 0x20000>;
+ no-map;
+ };
+ };
+
soc: soc@0 {
#address-cells = <2>;
#size-cells = <2>;
@@ -335,6 +350,43 @@
dma-ranges = <0 0 0 0 0x10 0>;
compatible = "simple-bus";
+ gcc: clock-controller@100000 {
+ compatible = "qcom,sm4450-gcc";
+ reg = <0x0 0x00100000 0x0 0x1f4200>;
+ #clock-cells = <1>;
+ #reset-cells = <1>;
+ #power-domain-cells = <1>;
+ clocks = <&rpmhcc RPMH_CXO_CLK>,
+ <&sleep_clk>,
+ <0>,
+ <0>,
+ <0>,
+ <0>;
+ };
+
+ qupv3_id_0: geniqup@ac0000 {
+ compatible = "qcom,geni-se-qup";
+ reg = <0x0 0x00ac0000 0x0 0x2000>;
+ ranges;
+ clocks = <&gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>,
+ <&gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>;
+ clock-names = "m-ahb", "s-ahb";
+ #address-cells = <2>;
+ #size-cells = <2>;
+ status = "disabled";
+
+ uart7: serial@a88000 {
+ compatible = "qcom,geni-debug-uart";
+ reg = <0x0 0x00a88000 0x0 0x4000>;
+ clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>;
+ clock-names = "se";
+ interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>;
+ pinctrl-0 = <&qup_uart7_tx>, <&qup_uart7_rx>;
+ pinctrl-names = "default";
+ status = "disabled";
+ };
+ };
+
tcsr_mutex: hwlock@1f40000 {
compatible = "qcom,tcsr-mutex";
reg = <0x0 0x01f40000 0x0 0x40000>;
@@ -351,6 +403,32 @@
interrupt-controller;
};
+ tlmm: pinctrl@f100000 {
+ compatible = "qcom,sm4450-tlmm";
+ reg = <0x0 0x0f100000 0x0 0x300000>;
+ interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ gpio-ranges = <&tlmm 0 0 137>;
+ wakeup-parent = <&pdc>;
+
+ qup_uart7_rx: qup-uart7-rx-state {
+ pins = "gpio23";
+ function = "qup1_se2_l2";
+ drive-strength = <2>;
+ bias-disable;
+ };
+
+ qup_uart7_tx: qup-uart7-tx-state {
+ pins = "gpio22";
+ function = "qup1_se2_l2";
+ drive-strength = <2>;
+ bias-disable;
+ };
+ };
+
intc: interrupt-controller@17200000 {
compatible = "arm,gic-v3";
reg = <0x0 0x17200000 0x0 0x10000>, /* GICD */
@@ -419,6 +497,35 @@
status = "disabled";
};
};
+
+ apps_rsc: rsc@17a00000 {
+ compatible = "qcom,rpmh-rsc";
+ reg = <0x0 0x17a00000 0x0 0x10000>,
+ <0x0 0x17a10000 0x0 0x10000>,
+ <0x0 0x17a20000 0x0 0x10000>;
+ reg-names = "drv-0", "drv-1", "drv-2";
+ interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
+ label = "apps_rsc";
+ qcom,tcs-offset = <0xd00>;
+ qcom,drv-id = <2>;
+ qcom,tcs-config = <ACTIVE_TCS 2>, <SLEEP_TCS 3>,
+ <WAKE_TCS 3>, <CONTROL_TCS 0>;
+ power-domains = <&CLUSTER_PD>;
+
+ apps_bcm_voter: bcm-voter {
+ compatible = "qcom,bcm-voter";
+ };
+
+ rpmhcc: clock-controller {
+ compatible = "qcom,sm4450-rpmh-clk";
+ #clock-cells = <1>;
+ clocks = <&xo_board>;
+ clock-names = "xo";
+ };
+ };
+
};
timer {
diff --git a/dts/upstream/src/arm64/qcom/sm6115.dtsi b/dts/upstream/src/arm64/qcom/sm6115.dtsi
index 839c603..f9849b8 100644
--- a/dts/upstream/src/arm64/qcom/sm6115.dtsi
+++ b/dts/upstream/src/arm64/qcom/sm6115.dtsi
@@ -10,6 +10,8 @@
#include <dt-bindings/dma/qcom-gpi.h>
#include <dt-bindings/firmware/qcom,scm.h>
#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/interconnect/qcom,rpm-icc.h>
+#include <dt-bindings/interconnect/qcom,sm6115.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/power/qcom-rpmpd.h>
@@ -264,6 +266,8 @@
scm: scm {
compatible = "qcom,scm-sm6115", "qcom,scm";
#reset-cells = <1>;
+ interconnects = <&system_noc MASTER_CRYPTO_CORE0 RPM_ALWAYS_TAG
+ &bimc SLAVE_EBI_CH0 RPM_ALWAYS_TAG>;
};
};
@@ -273,6 +277,25 @@
reg = <0 0x80000000 0 0>;
};
+ qup_opp_table: opp-table-qup {
+ compatible = "operating-points-v2";
+
+ opp-75000000 {
+ opp-hz = /bits/ 64 <75000000>;
+ required-opps = <&rpmpd_opp_low_svs>;
+ };
+
+ opp-100000000 {
+ opp-hz = /bits/ 64 <100000000>;
+ required-opps = <&rpmpd_opp_svs>;
+ };
+
+ opp-128000000 {
+ opp-hz = /bits/ 64 <128000000>;
+ required-opps = <&rpmpd_opp_nom>;
+ };
+ };
+
pmu {
compatible = "arm,armv8-pmuv3";
interrupts = <GIC_PPI 6 IRQ_TYPE_LEVEL_HIGH>;
@@ -859,6 +882,43 @@
status = "disabled";
};
+ system_noc: interconnect@1880000 {
+ compatible = "qcom,sm6115-snoc";
+ reg = <0x0 0x01880000 0x0 0x5f080>;
+ clocks = <&gcc GCC_SYS_NOC_CPUSS_AHB_CLK>,
+ <&gcc GCC_SYS_NOC_UFS_PHY_AXI_CLK>,
+ <&gcc GCC_SYS_NOC_USB3_PRIM_AXI_CLK>,
+ <&rpmcc RPM_SMD_IPA_CLK>;
+ clock-names = "cpu_axi",
+ "ufs_axi",
+ "usb_axi",
+ "ipa";
+ #interconnect-cells = <2>;
+
+ clk_virt: interconnect-clk {
+ compatible = "qcom,sm6115-clk-virt";
+ #interconnect-cells = <2>;
+ };
+
+ mmrt_virt: interconnect-mmrt {
+ compatible = "qcom,sm6115-mmrt-virt";
+ #interconnect-cells = <2>;
+ };
+
+ mmnrt_virt: interconnect-mmnrt {
+ compatible = "qcom,sm6115-mmnrt-virt";
+ #interconnect-cells = <2>;
+ };
+ };
+
+ config_noc: interconnect@1900000 {
+ compatible = "qcom,sm6115-cnoc";
+ reg = <0x0 0x01900000 0x0 0x6200>;
+ clocks = <&gcc GCC_CFG_NOC_USB3_PRIM_AXI_CLK>;
+ clock-names = "usb_axi";
+ #interconnect-cells = <2>;
+ };
+
qfprom@1b40000 {
compatible = "qcom,sm6115-qfprom", "qcom,qfprom";
reg = <0x0 0x01b40000 0x0 0x7000>;
@@ -883,6 +943,60 @@
clock-names = "core";
};
+ pmu@1b8e300 {
+ compatible = "qcom,sm6115-cpu-bwmon", "qcom,sdm845-bwmon";
+ reg = <0x0 0x01b8e300 0x0 0x600>;
+ interrupts = <GIC_SPI 421 IRQ_TYPE_LEVEL_HIGH>;
+
+ operating-points-v2 = <&cpu_bwmon_opp_table>;
+ interconnects = <&bimc MASTER_AMPSS_M0 RPM_ACTIVE_TAG
+ &bimc SLAVE_EBI_CH0 RPM_ACTIVE_TAG>;
+
+ cpu_bwmon_opp_table: opp-table {
+ compatible = "operating-points-v2";
+
+ opp-0 {
+ opp-peak-kBps = <(200 * 4 * 1000)>;
+ };
+
+ opp-1 {
+ opp-peak-kBps = <(300 * 4 * 1000)>;
+ };
+
+ opp-2 {
+ opp-peak-kBps = <(451 * 4 * 1000)>;
+ };
+
+ opp-3 {
+ opp-peak-kBps = <(547 * 4 * 1000)>;
+ };
+
+ opp-4 {
+ opp-peak-kBps = <(681 * 4 * 1000)>;
+ };
+
+ opp-5 {
+ opp-peak-kBps = <(768 * 4 * 1000)>;
+ };
+
+ opp-6 {
+ opp-peak-kBps = <(1017 * 4 * 1000)>;
+ };
+
+ opp-7 {
+ opp-peak-kBps = <(1353 * 4 * 1000)>;
+ };
+
+ opp-8 {
+ opp-peak-kBps = <(1555 * 4 * 1000)>;
+ };
+
+ opp-9 {
+ opp-peak-kBps = <(1804 * 4 * 1000)>;
+ };
+ };
+ };
+
spmi_bus: spmi@1c40000 {
compatible = "qcom,spmi-pmic-arb";
reg = <0x0 0x01c40000 0x0 0x1100>,
@@ -912,6 +1026,12 @@
#thermal-sensor-cells = <1>;
};
+ bimc: interconnect@4480000 {
+ compatible = "qcom,sm6115-bimc";
+ reg = <0x0 0x04480000 0x0 0x80000>;
+ #interconnect-cells = <2>;
+ };
+
rpm_msg_ram: sram@45f0000 {
compatible = "qcom,rpm-msg-ram";
reg = <0x0 0x045f0000 0x0 0x7000>;
@@ -939,8 +1059,42 @@
<&gcc GCC_SDCC1_ICE_CORE_CLK>;
clock-names = "iface", "core", "xo", "ice";
+ power-domains = <&rpmpd SM6115_VDDCX>;
+ operating-points-v2 = <&sdhc1_opp_table>;
+ interconnects = <&system_noc MASTER_SDCC_1 RPM_ALWAYS_TAG
+ &bimc SLAVE_EBI_CH0 RPM_ALWAYS_TAG>,
+ <&bimc MASTER_AMPSS_M0 RPM_ALWAYS_TAG
+ &config_noc SLAVE_SDCC_1 RPM_ALWAYS_TAG>;
+ interconnect-names = "sdhc-ddr",
+ "cpu-sdhc";
+
bus-width = <8>;
status = "disabled";
+
+ sdhc1_opp_table: opp-table {
+ compatible = "operating-points-v2";
+
+ opp-100000000 {
+ opp-hz = /bits/ 64 <100000000>;
+ required-opps = <&rpmpd_opp_low_svs>;
+ opp-peak-kBps = <250000 133320>;
+ opp-avg-kBps = <102400 65000>;
+ };
+
+ opp-192000000 {
+ opp-hz = /bits/ 64 <192000000>;
+ required-opps = <&rpmpd_opp_low_svs>;
+ opp-peak-kBps = <800000 300000>;
+ opp-avg-kBps = <204800 200000>;
+ };
+
+ opp-384000000 {
+ opp-hz = /bits/ 64 <384000000>;
+ required-opps = <&rpmpd_opp_svs_plus>;
+ opp-peak-kBps = <800000 300000>;
+ opp-avg-kBps = <204800 200000>;
+ };
+ };
};
sdhc_2: mmc@4784000 {
@@ -961,6 +1115,12 @@
operating-points-v2 = <&sdhc2_opp_table>;
iommus = <&apps_smmu 0x00a0 0x0>;
resets = <&gcc GCC_SDCC2_BCR>;
+ interconnects = <&system_noc MASTER_SDCC_2 RPM_ALWAYS_TAG
+ &bimc SLAVE_EBI_CH0 RPM_ALWAYS_TAG>,
+ <&bimc MASTER_AMPSS_M0 RPM_ALWAYS_TAG
+ &config_noc SLAVE_SDCC_2 RPM_ALWAYS_TAG>;
+ interconnect-names = "sdhc-ddr",
+ "cpu-sdhc";
bus-width = <4>;
qcom,dll-config = <0x0007642c>;
@@ -973,11 +1133,15 @@
opp-100000000 {
opp-hz = /bits/ 64 <100000000>;
required-opps = <&rpmpd_opp_low_svs>;
+ opp-peak-kBps = <250000 133320>;
+ opp-avg-kBps = <261438 150000>;
};
opp-202000000 {
opp-hz = /bits/ 64 <202000000>;
required-opps = <&rpmpd_opp_nom>;
+ opp-peak-kBps = <800000 300000>;
+ opp-avg-kBps = <261438 300000>;
};
};
};
@@ -987,7 +1151,7 @@
reg = <0x0 0x04804000 0x0 0x3000>, <0x0 0x04810000 0x0 0x8000>;
reg-names = "std", "ice";
interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>;
- phys = <&ufs_mem_phy_lanes>;
+ phys = <&ufs_mem_phy>;
phy-names = "ufsphy";
lanes-per-direction = <1>;
#reset-cells = <1>;
@@ -1028,24 +1192,17 @@
ufs_mem_phy: phy@4807000 {
compatible = "qcom,sm6115-qmp-ufs-phy";
- reg = <0x0 0x04807000 0x0 0x1c4>;
- #address-cells = <2>;
- #size-cells = <2>;
- ranges;
+ reg = <0x0 0x04807000 0x0 0x1000>;
clocks = <&gcc GCC_UFS_CLKREF_CLK>, <&gcc GCC_UFS_PHY_PHY_AUX_CLK>;
clock-names = "ref", "ref_aux";
resets = <&ufs_mem_hc 0>;
reset-names = "ufsphy";
- status = "disabled";
- ufs_mem_phy_lanes: phy@4807400 {
- reg = <0x0 0x04807400 0x0 0x098>,
- <0x0 0x04807600 0x0 0x130>,
- <0x0 0x04807c00 0x0 0x16c>;
- #phy-cells = <0>;
- };
+ #phy-cells = <0>;
+
+ status = "disabled";
};
gpi_dma0: dma-controller@4a00000 {
@@ -1091,6 +1248,15 @@
dmas = <&gpi_dma0 0 0 QCOM_GPI_I2C>,
<&gpi_dma0 1 0 QCOM_GPI_I2C>;
dma-names = "tx", "rx";
+ interconnects = <&clk_virt MASTER_QUP_CORE_0 RPM_ALWAYS_TAG
+ &clk_virt SLAVE_QUP_CORE_0 RPM_ALWAYS_TAG>,
+ <&bimc MASTER_AMPSS_M0 RPM_ALWAYS_TAG
+ &config_noc SLAVE_QUP_0 RPM_ALWAYS_TAG>,
+ <&system_noc MASTER_QUP_0 RPM_ALWAYS_TAG
+ &bimc SLAVE_EBI_CH0 RPM_ALWAYS_TAG>;
+ interconnect-names = "qup-core",
+ "qup-config",
+ "qup-memory";
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
@@ -1107,6 +1273,15 @@
dmas = <&gpi_dma0 0 0 QCOM_GPI_SPI>,
<&gpi_dma0 1 0 QCOM_GPI_SPI>;
dma-names = "tx", "rx";
+ interconnects = <&clk_virt MASTER_QUP_CORE_0 RPM_ALWAYS_TAG
+ &clk_virt SLAVE_QUP_CORE_0 RPM_ALWAYS_TAG>,
+ <&bimc MASTER_AMPSS_M0 RPM_ALWAYS_TAG
+ &config_noc SLAVE_QUP_0 RPM_ALWAYS_TAG>,
+ <&system_noc MASTER_QUP_0 RPM_ALWAYS_TAG
+ &bimc SLAVE_EBI_CH0 RPM_ALWAYS_TAG>;
+ interconnect-names = "qup-core",
+ "qup-config",
+ "qup-memory";
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
@@ -1123,6 +1298,15 @@
dmas = <&gpi_dma0 0 1 QCOM_GPI_I2C>,
<&gpi_dma0 1 1 QCOM_GPI_I2C>;
dma-names = "tx", "rx";
+ interconnects = <&clk_virt MASTER_QUP_CORE_0 RPM_ALWAYS_TAG
+ &clk_virt SLAVE_QUP_CORE_0 RPM_ALWAYS_TAG>,
+ <&bimc MASTER_AMPSS_M0 RPM_ALWAYS_TAG
+ &config_noc SLAVE_QUP_0 RPM_ALWAYS_TAG>,
+ <&system_noc MASTER_QUP_0 RPM_ALWAYS_TAG
+ &bimc SLAVE_EBI_CH0 RPM_ALWAYS_TAG>;
+ interconnect-names = "qup-core",
+ "qup-config",
+ "qup-memory";
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
@@ -1139,6 +1323,15 @@
dmas = <&gpi_dma0 0 1 QCOM_GPI_SPI>,
<&gpi_dma0 1 1 QCOM_GPI_SPI>;
dma-names = "tx", "rx";
+ interconnects = <&clk_virt MASTER_QUP_CORE_0 RPM_ALWAYS_TAG
+ &clk_virt SLAVE_QUP_CORE_0 RPM_ALWAYS_TAG>,
+ <&bimc MASTER_AMPSS_M0 RPM_ALWAYS_TAG
+ &config_noc SLAVE_QUP_0 RPM_ALWAYS_TAG>,
+ <&system_noc MASTER_QUP_0 RPM_ALWAYS_TAG
+ &bimc SLAVE_EBI_CH0 RPM_ALWAYS_TAG>;
+ interconnect-names = "qup-core",
+ "qup-config",
+ "qup-memory";
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
@@ -1155,6 +1348,15 @@
dmas = <&gpi_dma0 0 2 QCOM_GPI_I2C>,
<&gpi_dma0 1 2 QCOM_GPI_I2C>;
dma-names = "tx", "rx";
+ interconnects = <&clk_virt MASTER_QUP_CORE_0 RPM_ALWAYS_TAG
+ &clk_virt SLAVE_QUP_CORE_0 RPM_ALWAYS_TAG>,
+ <&bimc MASTER_AMPSS_M0 RPM_ALWAYS_TAG
+ &config_noc SLAVE_QUP_0 RPM_ALWAYS_TAG>,
+ <&system_noc MASTER_QUP_0 RPM_ALWAYS_TAG
+ &bimc SLAVE_EBI_CH0 RPM_ALWAYS_TAG>;
+ interconnect-names = "qup-core",
+ "qup-config",
+ "qup-memory";
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
@@ -1171,6 +1373,15 @@
dmas = <&gpi_dma0 0 2 QCOM_GPI_SPI>,
<&gpi_dma0 1 2 QCOM_GPI_SPI>;
dma-names = "tx", "rx";
+ interconnects = <&clk_virt MASTER_QUP_CORE_0 RPM_ALWAYS_TAG
+ &clk_virt SLAVE_QUP_CORE_0 RPM_ALWAYS_TAG>,
+ <&bimc MASTER_AMPSS_M0 RPM_ALWAYS_TAG
+ &config_noc SLAVE_QUP_0 RPM_ALWAYS_TAG>,
+ <&system_noc MASTER_QUP_0 RPM_ALWAYS_TAG
+ &bimc SLAVE_EBI_CH0 RPM_ALWAYS_TAG>;
+ interconnect-names = "qup-core",
+ "qup-config",
+ "qup-memory";
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
@@ -1187,6 +1398,15 @@
dmas = <&gpi_dma0 0 3 QCOM_GPI_I2C>,
<&gpi_dma0 1 3 QCOM_GPI_I2C>;
dma-names = "tx", "rx";
+ interconnects = <&clk_virt MASTER_QUP_CORE_0 RPM_ALWAYS_TAG
+ &clk_virt SLAVE_QUP_CORE_0 RPM_ALWAYS_TAG>,
+ <&bimc MASTER_AMPSS_M0 RPM_ALWAYS_TAG
+ &config_noc SLAVE_QUP_0 RPM_ALWAYS_TAG>,
+ <&system_noc MASTER_QUP_0 RPM_ALWAYS_TAG
+ &bimc SLAVE_EBI_CH0 RPM_ALWAYS_TAG>;
+ interconnect-names = "qup-core",
+ "qup-config",
+ "qup-memory";
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
@@ -1203,11 +1423,37 @@
dmas = <&gpi_dma0 0 3 QCOM_GPI_SPI>,
<&gpi_dma0 1 3 QCOM_GPI_SPI>;
dma-names = "tx", "rx";
+ interconnects = <&clk_virt MASTER_QUP_CORE_0 RPM_ALWAYS_TAG
+ &clk_virt SLAVE_QUP_CORE_0 RPM_ALWAYS_TAG>,
+ <&bimc MASTER_AMPSS_M0 RPM_ALWAYS_TAG
+ &config_noc SLAVE_QUP_0 RPM_ALWAYS_TAG>,
+ <&system_noc MASTER_QUP_0 RPM_ALWAYS_TAG
+ &bimc SLAVE_EBI_CH0 RPM_ALWAYS_TAG>;
+ interconnect-names = "qup-core",
+ "qup-config",
+ "qup-memory";
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
};
+ uart3: serial@4a8c000 {
+ compatible = "qcom,geni-uart";
+ reg = <0x0 0x04a8c000 0x0 0x4000>;
+ interrupts-extended = <&intc GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>;
+ clock-names = "se";
+ power-domains = <&rpmpd SM6115_VDDCX>;
+ operating-points-v2 = <&qup_opp_table>;
+ interconnects = <&clk_virt MASTER_QUP_CORE_0 RPM_ALWAYS_TAG
+ &clk_virt SLAVE_QUP_CORE_0 RPM_ALWAYS_TAG>,
+ <&bimc MASTER_AMPSS_M0 RPM_ALWAYS_TAG
+ &config_noc SLAVE_QUP_0 RPM_ALWAYS_TAG>;
+ interconnect-names = "qup-core",
+ "qup-config";
+ status = "disabled";
+ };
+
i2c4: i2c@4a90000 {
compatible = "qcom,geni-i2c";
reg = <0x0 0x04a90000 0x0 0x4000>;
@@ -1219,6 +1465,15 @@
dmas = <&gpi_dma0 0 4 QCOM_GPI_I2C>,
<&gpi_dma0 1 4 QCOM_GPI_I2C>;
dma-names = "tx", "rx";
+ interconnects = <&clk_virt MASTER_QUP_CORE_0 RPM_ALWAYS_TAG
+ &clk_virt SLAVE_QUP_CORE_0 RPM_ALWAYS_TAG>,
+ <&bimc MASTER_AMPSS_M0 RPM_ALWAYS_TAG
+ &config_noc SLAVE_QUP_0 RPM_ALWAYS_TAG>,
+ <&system_noc MASTER_QUP_0 RPM_ALWAYS_TAG
+ &bimc SLAVE_EBI_CH0 RPM_ALWAYS_TAG>;
+ interconnect-names = "qup-core",
+ "qup-config",
+ "qup-memory";
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
@@ -1235,6 +1490,15 @@
dmas = <&gpi_dma0 0 4 QCOM_GPI_SPI>,
<&gpi_dma0 1 4 QCOM_GPI_SPI>;
dma-names = "tx", "rx";
+ interconnects = <&clk_virt MASTER_QUP_CORE_0 RPM_ALWAYS_TAG
+ &clk_virt SLAVE_QUP_CORE_0 RPM_ALWAYS_TAG>,
+ <&bimc MASTER_AMPSS_M0 RPM_ALWAYS_TAG
+ &config_noc SLAVE_QUP_0 RPM_ALWAYS_TAG>,
+ <&system_noc MASTER_QUP_0 RPM_ALWAYS_TAG
+ &bimc SLAVE_EBI_CH0 RPM_ALWAYS_TAG>;
+ interconnect-names = "qup-core",
+ "qup-config",
+ "qup-memory";
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
@@ -1246,6 +1510,12 @@
clock-names = "se";
clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>;
interrupts = <GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH>;
+ interconnects = <&clk_virt MASTER_QUP_CORE_0 RPM_ALWAYS_TAG
+ &clk_virt SLAVE_QUP_CORE_0 RPM_ALWAYS_TAG>,
+ <&bimc MASTER_AMPSS_M0 RPM_ALWAYS_TAG
+ &config_noc SLAVE_QUP_0 RPM_ALWAYS_TAG>;
+ interconnect-names = "qup-core",
+ "qup-config";
status = "disabled";
};
@@ -1260,6 +1530,15 @@
dmas = <&gpi_dma0 0 5 QCOM_GPI_I2C>,
<&gpi_dma0 1 5 QCOM_GPI_I2C>;
dma-names = "tx", "rx";
+ interconnects = <&clk_virt MASTER_QUP_CORE_0 RPM_ALWAYS_TAG
+ &clk_virt SLAVE_QUP_CORE_0 RPM_ALWAYS_TAG>,
+ <&bimc MASTER_AMPSS_M0 RPM_ALWAYS_TAG
+ &config_noc SLAVE_QUP_0 RPM_ALWAYS_TAG>,
+ <&system_noc MASTER_QUP_0 RPM_ALWAYS_TAG
+ &bimc SLAVE_EBI_CH0 RPM_ALWAYS_TAG>;
+ interconnect-names = "qup-core",
+ "qup-config",
+ "qup-memory";
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
@@ -1276,6 +1555,15 @@
dmas = <&gpi_dma0 0 5 QCOM_GPI_SPI>,
<&gpi_dma0 1 5 QCOM_GPI_SPI>;
dma-names = "tx", "rx";
+ interconnects = <&clk_virt MASTER_QUP_CORE_0 RPM_ALWAYS_TAG
+ &clk_virt SLAVE_QUP_CORE_0 RPM_ALWAYS_TAG>,
+ <&bimc MASTER_AMPSS_M0 RPM_ALWAYS_TAG
+ &config_noc SLAVE_QUP_0 RPM_ALWAYS_TAG>,
+ <&system_noc MASTER_QUP_0 RPM_ALWAYS_TAG
+ &bimc SLAVE_EBI_CH0 RPM_ALWAYS_TAG>;
+ interconnect-names = "qup-core",
+ "qup-config",
+ "qup-memory";
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
@@ -1307,6 +1595,14 @@
resets = <&gcc GCC_USB30_PRIM_BCR>;
power-domains = <&gcc GCC_USB30_PRIM_GDSC>;
+ /* TODO: USB<->IPA path */
+ interconnects = <&system_noc MASTER_USB3 RPM_ALWAYS_TAG
+ &bimc SLAVE_EBI_CH0 RPM_ALWAYS_TAG>,
+ <&bimc MASTER_AMPSS_M0 RPM_ALWAYS_TAG
+ &config_noc SLAVE_USB3 RPM_ALWAYS_TAG>;
+ interconnect-names = "usb-ddr",
+ "apps-usb";
+
qcom,select-utmi-as-pipe-clk;
status = "disabled";
@@ -1478,6 +1774,13 @@
iommus = <&apps_smmu 0x420 0x2>,
<&apps_smmu 0x421 0x0>;
+ interconnects = <&mmrt_virt MASTER_MDP_PORT0 RPM_ALWAYS_TAG
+ &bimc SLAVE_EBI_CH0 RPM_ALWAYS_TAG>,
+ <&bimc MASTER_AMPSS_M0 RPM_ALWAYS_TAG
+ &config_noc SLAVE_DISPLAY_CFG RPM_ALWAYS_TAG>;
+ interconnect-names = "mdp0-mem",
+ "cpu-cfg";
+
#address-cells = <2>;
#size-cells = <2>;
ranges;
@@ -2566,54 +2869,54 @@
compatible = "arm,armv7-timer-mem";
reg = <0x0 0x0f120000 0x0 0x1000>;
#address-cells = <2>;
- #size-cells = <2>;
- ranges;
+ #size-cells = <1>;
+ ranges = <0x0 0x0 0x0 0x0 0x20000000>;
clock-frequency = <19200000>;
frame@f121000 {
- reg = <0x0 0x0f121000 0x0 0x1000>, <0x0 0x0f122000 0x0 0x1000>;
+ reg = <0x0 0x0f121000 0x1000>, <0x0 0x0f122000 0x1000>;
frame-number = <0>;
interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
};
frame@f123000 {
- reg = <0x0 0x0f123000 0x0 0x1000>;
+ reg = <0x0 0x0f123000 0x1000>;
frame-number = <1>;
interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
status = "disabled";
};
frame@f124000 {
- reg = <0x0 0x0f124000 0x0 0x1000>;
+ reg = <0x0 0x0f124000 0x1000>;
frame-number = <2>;
interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
status = "disabled";
};
frame@f125000 {
- reg = <0x0 0x0f125000 0x0 0x1000>;
+ reg = <0x0 0x0f125000 0x1000>;
frame-number = <3>;
interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
status = "disabled";
};
frame@f126000 {
- reg = <0x0 0x0f126000 0x0 0x1000>;
+ reg = <0x0 0x0f126000 0x1000>;
frame-number = <4>;
interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
status = "disabled";
};
frame@f127000 {
- reg = <0x0 0x0f127000 0x0 0x1000>;
+ reg = <0x0 0x0f127000 0x1000>;
frame-number = <5>;
interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
status = "disabled";
};
frame@f128000 {
- reg = <0x0 0x0f128000 0x0 0x1000>;
+ reg = <0x0 0x0f128000 0x1000>;
frame-number = <6>;
interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
status = "disabled";
diff --git a/dts/upstream/src/arm64/qcom/sm6125.dtsi b/dts/upstream/src/arm64/qcom/sm6125.dtsi
index eb07eca..1dd3a40 100644
--- a/dts/upstream/src/arm64/qcom/sm6125.dtsi
+++ b/dts/upstream/src/arm64/qcom/sm6125.dtsi
@@ -1185,6 +1185,10 @@
<&gcc GCC_USB30_PRIM_MASTER_CLK>;
assigned-clock-rates = <19200000>, <66666667>;
+ interrupts = <GIC_SPI 260 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 422 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "hs_phy_irq", "ss_phy_irq";
+
power-domains = <&gcc USB30_PRIM_GDSC>;
qcom,select-utmi-as-pipe-clk;
status = "disabled";
diff --git a/dts/upstream/src/arm64/qcom/sm6350.dtsi b/dts/upstream/src/arm64/qcom/sm6350.dtsi
index 8fd6f4d..43cffe8 100644
--- a/dts/upstream/src/arm64/qcom/sm6350.dtsi
+++ b/dts/upstream/src/arm64/qcom/sm6350.dtsi
@@ -1142,7 +1142,7 @@
<0 0x01d90000 0 0x8000>;
reg-names = "std", "ice";
interrupts = <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH>;
- phys = <&ufs_mem_phy_lanes>;
+ phys = <&ufs_mem_phy>;
phy-names = "ufsphy";
lanes-per-direction = <2>;
#reset-cells = <1>;
@@ -1187,10 +1187,7 @@
ufs_mem_phy: phy@1d87000 {
compatible = "qcom,sm6350-qmp-ufs-phy";
- reg = <0 0x01d87000 0 0x18c>;
- #address-cells = <2>;
- #size-cells = <2>;
- ranges;
+ reg = <0 0x01d87000 0 0x1000>;
clock-names = "ref",
"ref_aux";
@@ -1200,16 +1197,9 @@
resets = <&ufs_mem_hc 0>;
reset-names = "ufsphy";
- status = "disabled";
+ #phy-cells = <0>;
- ufs_mem_phy_lanes: phy@1d87400 {
- reg = <0 0x01d87400 0 0x128>,
- <0 0x01d87600 0 0x1fc>,
- <0 0x01d87c00 0 0x1dc>,
- <0 0x01d87800 0 0x128>,
- <0 0x01d87a00 0 0x1fc>;
- #phy-cells = <0>;
- };
+ status = "disabled";
};
ipa: ipa@1e40000 {
@@ -2524,7 +2514,7 @@
compatible = "qcom,apss-wdt-sm6350", "qcom,kpss-wdt";
reg = <0 0x17c10000 0 0x1000>;
clocks = <&sleep_clk>;
- interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>;
+ interrupts = <GIC_SPI 0 IRQ_TYPE_EDGE_RISING>;
};
timer@17c20000 {
diff --git a/dts/upstream/src/arm64/qcom/sm6375-sony-xperia-murray-pdx225.dts b/dts/upstream/src/arm64/qcom/sm6375-sony-xperia-murray-pdx225.dts
index b2f1bb1..cca2c2e 100644
--- a/dts/upstream/src/arm64/qcom/sm6375-sony-xperia-murray-pdx225.dts
+++ b/dts/upstream/src/arm64/qcom/sm6375-sony-xperia-murray-pdx225.dts
@@ -80,6 +80,15 @@
};
};
+ touch_avdd: touch-avdd-regulator {
+ compatible = "regulator-fixed";
+ regulator-name = "touch_avdd";
+ gpio = <&tlmm 59 GPIO_ACTIVE_HIGH>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&ts_avdd_default>;
+ enable-active-high;
+ };
+
vph_pwr: vph-pwr-regulator {
compatible = "regulator-fixed";
regulator-name = "vph_pwr";
@@ -136,9 +145,10 @@
interrupts = <22 0x2008>;
vdd-supply = <&pm6125_l13>;
+ avdd-supply = <&touch_avdd>;
pinctrl-names = "default";
- pinctrl-0 = <&ts_int_default &ts_avdd_default>;
+ pinctrl-0 = <&ts_int_default>;
};
};
@@ -187,6 +197,11 @@
status = "okay";
};
+&remoteproc_mss {
+ firmware-name = "qcom/sm6375/Sony/murray/modem.mbn";
+ status = "okay";
+};
+
&rpm_requests {
regulators-0 {
compatible = "qcom,rpm-pm6125-regulators";
@@ -238,8 +253,8 @@
};
pm6125_l7: l7 {
- regulator-min-microvolt = <720000>;
- regulator-max-microvolt = <1050000>;
+ regulator-min-microvolt = <880000>;
+ regulator-max-microvolt = <880000>;
};
pm6125_l8: l8 {
@@ -306,7 +321,7 @@
pm6125_l21: l21 {
regulator-min-microvolt = <3000000>;
- regulator-max-microvolt = <3400000>;
+ regulator-max-microvolt = <3312000>;
};
pm6125_l22: l22 {
@@ -317,7 +332,7 @@
pm6125_l23: l23 {
regulator-min-microvolt = <3000000>;
- regulator-max-microvolt = <3400000>;
+ regulator-max-microvolt = <3312000>;
};
pm6125_l24: l24 {
@@ -340,8 +355,8 @@
};
pmr735a_l2: l2 {
- regulator-min-microvolt = <352000>;
- regulator-max-microvolt = <796000>;
+ regulator-min-microvolt = <640000>;
+ regulator-max-microvolt = <640000>;
};
pmr735a_l3: l3 {
@@ -412,7 +427,7 @@
pins = "gpio59";
function = "gpio";
drive-strength = <8>;
- output-high;
+ output-low;
};
};
@@ -425,6 +440,18 @@
};
&usb_1_hsphy {
+ vdda-pll-supply = <&pm6125_l7>;
+ vdda18-supply = <&pm6125_l10>;
+ vdda33-supply = <&pmr735a_l7>;
+ status = "okay";
+};
+
+&wifi {
+ vdd-0.8-cx-mx-supply = <&pmr735a_l2>;
+ vdd-1.8-xo-supply = <&pm6125_l16>;
+ vdd-1.3-rfa-supply = <&pm6125_l2>;
+ vdd-3.3-ch0-supply = <&pm6125_l23>;
+ vdd-3.3-ch1-supply = <&pm6125_l21>;
status = "okay";
};
diff --git a/dts/upstream/src/arm64/qcom/sm6375.dtsi b/dts/upstream/src/arm64/qcom/sm6375.dtsi
index e7ff554..7ac8bf2 100644
--- a/dts/upstream/src/arm64/qcom/sm6375.dtsi
+++ b/dts/upstream/src/arm64/qcom/sm6375.dtsi
@@ -311,6 +311,25 @@
};
};
+ mpm: interrupt-controller {
+ compatible = "qcom,mpm";
+ qcom,rpm-msg-ram = <&apss_mpm>;
+ interrupts = <GIC_SPI 197 IRQ_TYPE_EDGE_RISING>;
+ mboxes = <&ipcc IPCC_CLIENT_AOP IPCC_MPROC_SIGNAL_SMP2P>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ #power-domain-cells = <0>;
+ interrupt-parent = <&intc>;
+ qcom,mpm-pin-count = <96>;
+ qcom,mpm-pin-map = <5 296>, /* Soundwire wake_irq */
+ <12 422>, /* DWC3 ss_phy_irq */
+ <86 183>, /* MPM wake, SPMI */
+ <89 314>, /* TSENS0 0C */
+ <90 315>, /* TSENS1 0C */
+ <93 164>, /* DWC3 dm_hs_phy_irq */
+ <94 165>; /* DWC3 dp_hs_phy_irq */
+ };
+
memory@80000000 {
device_type = "memory";
/* We expect the bootloader to fill in the size */
@@ -486,6 +505,7 @@
CLUSTER_PD: power-domain-cpu-cluster0 {
#power-domain-cells = <0>;
+ power-domains = <&mpm>;
domain-idle-states = <&CLUSTER_SLEEP_0>;
};
};
@@ -808,7 +828,7 @@
reg = <0 0x00500000 0 0x800000>;
interrupts = <GIC_SPI 227 IRQ_TYPE_LEVEL_HIGH>;
gpio-ranges = <&tlmm 0 0 157>;
- /* TODO: Hook up MPM as wakeup-parent when it's there */
+ wakeup-parent = <&mpm>;
interrupt-controller;
gpio-controller;
#interrupt-cells = <2>;
@@ -896,6 +916,36 @@
drive-strength = <6>;
bias-disable;
};
+
+ qup_uart1_default: qup-uart1-default-state {
+ cts-pins {
+ pins = "gpio61";
+ function = "qup01";
+ drive-strength = <2>;
+ bias-pull-down;
+ };
+
+ rts-pins {
+ pins = "gpio62";
+ function = "qup01";
+ drive-strength = <2>;
+ bias-disable;
+ };
+
+ tx-pins {
+ pins = "gpio63";
+ function = "qup01";
+ drive-strength = <2>;
+ bias-disable;
+ };
+
+ rx-pins {
+ pins = "gpio64";
+ function = "qup01";
+ drive-strength = <2>;
+ bias-pull-up;
+ };
+ };
};
gcc: clock-controller@1400000 {
@@ -930,7 +980,7 @@
<0 0x01c0a000 0 0x26000>;
reg-names = "core", "chnls", "obsrvr", "intr", "cnfg";
interrupt-names = "periph_irq";
- interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
+ interrupts-extended = <&mpm 86 IRQ_TYPE_LEVEL_HIGH>;
qcom,ee = <0>;
qcom,channel = <0>;
#address-cells = <2>;
@@ -962,8 +1012,15 @@
};
rpm_msg_ram: sram@45f0000 {
- compatible = "qcom,rpm-msg-ram";
+ compatible = "qcom,rpm-msg-ram", "mmio-sram";
reg = <0 0x045f0000 0 0x7000>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0 0x0 0x045f0000 0x7000>;
+
+ apss_mpm: sram@1b8 {
+ reg = <0x1b8 0x48>;
+ };
};
sram@4690000 {
@@ -1111,6 +1168,19 @@
status = "disabled";
};
+ uart1: serial@4a84000 {
+ compatible = "qcom,geni-uart";
+ reg = <0x0 0x04a84000 0x0 0x4000>;
+ interrupts = <GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>;
+ clock-names = "se";
+ power-domains = <&rpmpd SM6375_VDDCX>;
+ operating-points-v2 = <&qup_opp_table>;
+ pinctrl-0 = <&qup_uart1_default>;
+ pinctrl-names = "default";
+ status = "disabled";
+ };
+
i2c2: i2c@4a88000 {
compatible = "qcom,geni-i2c";
reg = <0x0 0x04a88000 0x0 0x4000>;
@@ -1360,10 +1430,10 @@
<&gcc GCC_USB30_PRIM_MASTER_CLK>;
assigned-clock-rates = <19200000>, <133333333>;
- interrupts = <GIC_SPI 302 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>;
+ interrupts-extended = <&intc GIC_SPI 302 IRQ_TYPE_LEVEL_HIGH>,
+ <&mpm 12 IRQ_TYPE_LEVEL_HIGH>,
+ <&mpm 93 IRQ_TYPE_EDGE_BOTH>,
+ <&mpm 94 IRQ_TYPE_EDGE_BOTH>;
interrupt-names = "hs_phy_irq",
"ss_phy_irq",
"dm_hs_phy_irq",
diff --git a/dts/upstream/src/arm64/qcom/sm8150-hdk.dts b/dts/upstream/src/arm64/qcom/sm8150-hdk.dts
index bb161b5..de670b4 100644
--- a/dts/upstream/src/arm64/qcom/sm8150-hdk.dts
+++ b/dts/upstream/src/arm64/qcom/sm8150-hdk.dts
@@ -7,6 +7,7 @@
#include <dt-bindings/regulator/qcom,rpmh-regulator.h>
#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/usb/pd.h>
#include "sm8150.dtsi"
#include "pm8150.dtsi"
#include "pm8150b.dtsi"
@@ -54,6 +55,17 @@
gpios = <&pm8150_gpios 6 GPIO_ACTIVE_LOW>;
};
};
+
+ hdmi-out {
+ compatible = "hdmi-connector";
+ type = "a";
+
+ port {
+ hdmi_con: endpoint {
+ remote-endpoint = <<9611_out>;
+ };
+ };
+ };
};
&apps_rsc {
@@ -127,8 +139,6 @@
vdda_sp_sensor:
vdda_ufs_2ln_core_1:
vdda_ufs_2ln_core_2:
- vdda_usb_ss_dp_core_1:
- vdda_usb_ss_dp_core_2:
vdda_qlink_lv:
vdda_qlink_lv_ck:
vreg_l5a_0p875: ldo5 {
@@ -210,6 +220,12 @@
regulator-max-microvolt = <3008000>;
regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
};
+
+ vreg_l18a_0p8: ldo18 {
+ regulator-min-microvolt = <880000>;
+ regulator-max-microvolt = <880000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
};
regulators-1 {
@@ -359,15 +375,210 @@
status = "okay";
};
+&gpi_dma0 {
+ status = "okay";
+};
+
+&gpi_dma1 {
+ status = "okay";
+};
+
&gpu {
- /*
- * NOTE: "amd,imageon" makes Adreno start in headless mode, remove it
- * after display support is added on this board.
- */
- compatible = "qcom,adreno-640.1", "qcom,adreno", "amd,imageon";
+ status = "okay";
+};
+
+&i2c4 {
+ clock-frequency = <100000>;
+
+ status = "okay";
+
+ typec-mux@42 {
+ compatible = "fcs,fsa4480";
+ reg = <0x42>;
+
+ interrupts-extended = <&tlmm 152 IRQ_TYPE_LEVEL_LOW>;
+
+ vcc-supply = <&vreg_bob>;
+ mode-switch;
+ orientation-switch;
+
+ port {
+ fsa4480_sbu_mux: endpoint {
+ remote-endpoint = <&pm8150b_typec_sbu_out>;
+ };
+ };
+ };
+};
+
+&i2c9 {
+ status = "okay";
+ clock-frequency = <400000>;
+
+ lt9611_codec: hdmi-bridge@3b {
+ compatible = "lontium,lt9611";
+ reg = <0x3b>;
+ #sound-dai-cells = <1>;
+
+ interrupts-extended = <&tlmm 9 IRQ_TYPE_EDGE_FALLING>;
+
+ reset-gpios = <&tlmm 7 GPIO_ACTIVE_HIGH>;
+
+ vdd-supply = <&vreg_s4a_1p8>;
+ vcc-supply = <&vreg_bob>;
+
+ pinctrl-names = "default";
+ pinctrl-0 = <<9611_irq_pin>;
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+
+ lt9611_a: endpoint {
+ remote-endpoint = <&mdss_dsi0_out>;
+ };
+ };
+
+ port@1 {
+ reg = <1>;
+
+ lt9611_b: endpoint {
+ remote-endpoint = <&mdss_dsi1_out>;
+ };
+ };
+
+ port@2 {
+ reg = <2>;
+
+ lt9611_out: endpoint {
+ remote-endpoint = <&hdmi_con>;
+ };
+ };
+ };
+ };
+};
+
+&mdss {
+ status = "okay";
+};
+
+&mdss_dp {
status = "okay";
};
+&mdss_dp_out {
+ data-lanes = <0 1>;
+ remote-endpoint = <&usb_1_qmpphy_dp_in>;
+};
+
+&mdss_dsi0 {
+ status = "okay";
+ vdda-supply = <&vreg_l3c_1p2>;
+
+ qcom,dual-dsi-mode;
+ qcom,master-dsi;
+
+ ports {
+ port@1 {
+ endpoint {
+ remote-endpoint = <<9611_a>;
+ data-lanes = <0 1 2 3>;
+ };
+ };
+ };
+};
+
+&mdss_dsi0_phy {
+ status = "okay";
+ vdds-supply = <&vreg_l5a_0p875>;
+};
+
+&mdss_dsi1 {
+ vdda-supply = <&vreg_l3c_1p2>;
+
+ qcom,dual-dsi-mode;
+
+ /* DSI1 is slave, so use DSI0 clocks */
+ assigned-clock-parents = <&mdss_dsi0_phy 0>, <&mdss_dsi0_phy 1>;
+
+ status = "okay";
+
+ ports {
+ port@1 {
+ endpoint {
+ remote-endpoint = <<9611_b>;
+ data-lanes = <0 1 2 3>;
+ };
+ };
+ };
+};
+
+&mdss_dsi1_phy {
+ vdds-supply = <&vreg_l5a_0p875>;
+ status = "okay";
+};
+
+&pm8150b_vbus {
+ regulator-min-microamp = <500000>;
+ regulator-max-microamp = <3000000>;
+ status = "okay";
+};
+
+&pm8150b_typec {
+ status = "okay";
+
+ vdd-pdphy-supply = <&vreg_l2a_3p1>;
+
+ connector {
+ compatible = "usb-c-connector";
+
+ power-role = "source";
+ data-role = "dual";
+ self-powered;
+
+ source-pdos = <PDO_FIXED(5000, 3000,
+ PDO_FIXED_DUAL_ROLE |
+ PDO_FIXED_USB_COMM |
+ PDO_FIXED_DATA_SWAP)>;
+
+ altmodes {
+ displayport {
+ svid = /bits/ 16 <0xff01>;
+ vdo = <0x00001c46>;
+ };
+ };
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+ pm8150b_role_switch_in: endpoint {
+ remote-endpoint = <&usb_1_dwc3_hs>;
+ };
+ };
+
+ port@1 {
+ reg = <1>;
+ pm8150b_typec_mux_in: endpoint {
+ remote-endpoint = <&usb_1_qmpphy_out>;
+ };
+ };
+
+ port@2 {
+ reg = <2>;
+
+ pm8150b_typec_sbu_out: endpoint {
+ remote-endpoint = <&fsa4480_sbu_mux>;
+ };
+ };
+ };
+ };
+};
+
&pon_pwrkey {
status = "okay";
};
@@ -378,6 +589,10 @@
linux,code = <KEY_VOLUMEDOWN>;
};
+&qupv3_id_0 {
+ status = "okay";
+};
+
&qupv3_id_1 {
status = "okay";
};
@@ -402,6 +617,13 @@
&tlmm {
gpio-reserved-ranges = <0 4>, <126 4>;
+
+ lt9611_irq_pin: lt9611-irq-state {
+ pins = "gpio9";
+ function = "gpio";
+ bias-disable;
+ };
+
};
&uart2 {
@@ -445,13 +667,26 @@
&usb_1_qmpphy {
status = "okay";
vdda-phy-supply = <&vreg_l3c_1p2>;
- vdda-pll-supply = <&vdda_usb_ss_dp_core_1>;
+ vdda-pll-supply = <&vreg_l18a_0p8>;
+ orientation-switch;
+};
+
+&usb_1_qmpphy_dp_in {
+ remote-endpoint = <&mdss_dp_out>;
+};
+
+&usb_1_qmpphy_out {
+ remote-endpoint = <&pm8150b_typec_mux_in>;
};
+&usb_1_qmpphy_usb_ss_in {
+ remote-endpoint = <&usb_1_dwc3_ss>;
+};
+
&usb_2_qmpphy {
status = "okay";
vdda-phy-supply = <&vreg_l3c_1p2>;
- vdda-pll-supply = <&vdda_usb_ss_dp_core_1>;
+ vdda-pll-supply = <&vreg_l5a_0p875>;
};
&usb_1 {
@@ -463,7 +698,16 @@
};
&usb_1_dwc3 {
- dr_mode = "peripheral";
+ dr_mode = "otg";
+ usb-role-switch;
+};
+
+&usb_1_dwc3_hs {
+ remote-endpoint = <&pm8150b_role_switch_in>;
+};
+
+&usb_1_dwc3_ss {
+ remote-endpoint = <&usb_1_qmpphy_usb_ss_in>;
};
&usb_2_dwc3 {
diff --git a/dts/upstream/src/arm64/qcom/sm8150.dtsi b/dts/upstream/src/arm64/qcom/sm8150.dtsi
index 97623af..761a675 100644
--- a/dts/upstream/src/arm64/qcom/sm8150.dtsi
+++ b/dts/upstream/src/arm64/qcom/sm8150.dtsi
@@ -1824,7 +1824,7 @@
<0x0 0x010ad000 0x0 0x3000>;
};
- pcie0: pci@1c00000 {
+ pcie0: pcie@1c00000 {
compatible = "qcom,pcie-sm8150";
reg = <0 0x01c00000 0 0x3000>,
<0 0x60000000 0 0xf1d>,
@@ -1878,7 +1878,7 @@
phys = <&pcie0_phy>;
phy-names = "pciephy";
- perst-gpio = <&tlmm 35 GPIO_ACTIVE_HIGH>;
+ perst-gpios = <&tlmm 35 GPIO_ACTIVE_HIGH>;
enable-gpio = <&tlmm 37 GPIO_ACTIVE_HIGH>;
pinctrl-names = "default";
@@ -1915,7 +1915,7 @@
status = "disabled";
};
- pcie1: pci@1c08000 {
+ pcie1: pcie@1c08000 {
compatible = "qcom,pcie-sm8150";
reg = <0 0x01c08000 0 0x3000>,
<0 0x40000000 0 0xf1d>,
@@ -1972,7 +1972,7 @@
phys = <&pcie1_phy>;
phy-names = "pciephy";
- perst-gpio = <&tlmm 102 GPIO_ACTIVE_HIGH>;
+ perst-gpios = <&tlmm 102 GPIO_ACTIVE_HIGH>;
enable-gpio = <&tlmm 104 GPIO_ACTIVE_HIGH>;
pinctrl-names = "default";
@@ -2016,7 +2016,7 @@
<0 0x01d90000 0 0x8000>;
reg-names = "std", "ice";
interrupts = <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH>;
- phys = <&ufs_mem_phy_lanes>;
+ phys = <&ufs_mem_phy>;
phy-names = "ufsphy";
lanes-per-direction = <2>;
#reset-cells = <1>;
@@ -2061,10 +2061,8 @@
ufs_mem_phy: phy@1d87000 {
compatible = "qcom,sm8150-qmp-ufs-phy";
- reg = <0 0x01d87000 0 0x1c0>;
- #address-cells = <2>;
- #size-cells = <2>;
- ranges;
+ reg = <0 0x01d87000 0 0x1000>;
+
clock-names = "ref",
"ref_aux";
clocks = <&gcc GCC_UFS_MEM_CLKREF_CLK>,
@@ -2074,16 +2072,10 @@
resets = <&ufs_mem_hc 0>;
reset-names = "ufsphy";
- status = "disabled";
- ufs_mem_phy_lanes: phy@1d87400 {
- reg = <0 0x01d87400 0 0x16c>,
- <0 0x01d87600 0 0x200>,
- <0 0x01d87c00 0 0x200>,
- <0 0x01d87800 0 0x16c>,
- <0 0x01d87a00 0 0x200>;
- #phy-cells = <0>;
- };
+ #phy-cells = <0>;
+
+ status = "disabled";
};
cryptobam: dma-controller@1dc4000 {
@@ -2957,11 +2949,8 @@
};
in-ports {
- #address-cells = <1>;
- #size-cells = <0>;
- port@1 {
- reg = <1>;
+ port {
replicator1_in: endpoint {
remote-endpoint = <&replicator_out1>;
};
@@ -3447,37 +3436,56 @@
#phy-cells = <1>;
status = "disabled";
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+
+ usb_1_qmpphy_out: endpoint {
+ };
+ };
+
+ port@1 {
+ reg = <1>;
+
+ usb_1_qmpphy_usb_ss_in: endpoint {
+ };
+ };
+
+ port@2 {
+ reg = <2>;
+
+ usb_1_qmpphy_dp_in: endpoint {
+ };
+ };
+ };
};
usb_2_qmpphy: phy@88eb000 {
compatible = "qcom,sm8150-qmp-usb3-uni-phy";
- reg = <0 0x088eb000 0 0x200>;
- status = "disabled";
- #address-cells = <2>;
- #size-cells = <2>;
- ranges;
+ reg = <0 0x088eb000 0 0x1000>;
clocks = <&gcc GCC_USB3_SEC_PHY_AUX_CLK>,
- <&rpmhcc RPMH_CXO_CLK>,
<&gcc GCC_USB3_SEC_CLKREF_CLK>,
- <&gcc GCC_USB3_SEC_PHY_COM_AUX_CLK>;
- clock-names = "aux", "ref_clk_src", "ref", "com_aux";
+ <&gcc GCC_USB3_SEC_PHY_COM_AUX_CLK>,
+ <&gcc GCC_USB3_SEC_PHY_PIPE_CLK>;
+ clock-names = "aux",
+ "ref",
+ "com_aux",
+ "pipe";
+ clock-output-names = "usb3_uni_phy_pipe_clk_src";
+ #clock-cells = <0>;
+ #phy-cells = <0>;
- resets = <&gcc GCC_USB3PHY_PHY_SEC_BCR>,
- <&gcc GCC_USB3_PHY_SEC_BCR>;
- reset-names = "phy", "common";
+ resets = <&gcc GCC_USB3_PHY_SEC_BCR>,
+ <&gcc GCC_USB3PHY_PHY_SEC_BCR>;
+ reset-names = "phy",
+ "phy_phy";
- usb_2_ssphy: phy@88eb200 {
- reg = <0 0x088eb200 0 0x200>,
- <0 0x088eb400 0 0x200>,
- <0 0x088eb800 0 0x800>,
- <0 0x088eb600 0 0x200>;
- #clock-cells = <0>;
- #phy-cells = <0>;
- clocks = <&gcc GCC_USB3_SEC_PHY_PIPE_CLK>;
- clock-names = "pipe0";
- clock-output-names = "usb3_uni_phy_pipe_clk_src";
- };
+ status = "disabled";
};
sdhc_2: mmc@8804000 {
@@ -3565,10 +3573,10 @@
<&gcc GCC_USB30_PRIM_MASTER_CLK>;
assigned-clock-rates = <19200000>, <200000000>;
- interrupts = <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 486 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 488 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 489 IRQ_TYPE_LEVEL_HIGH>;
+ interrupts-extended = <&intc GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>,
+ <&pdc 6 IRQ_TYPE_LEVEL_HIGH>,
+ <&pdc 8 IRQ_TYPE_EDGE_BOTH>,
+ <&pdc 9 IRQ_TYPE_EDGE_BOTH>;
interrupt-names = "hs_phy_irq", "ss_phy_irq",
"dm_hs_phy_irq", "dp_hs_phy_irq";
@@ -3589,6 +3597,25 @@
snps,dis_enblslpm_quirk;
phys = <&usb_1_hsphy>, <&usb_1_qmpphy QMP_USB43DP_USB3_PHY>;
phy-names = "usb2-phy", "usb3-phy";
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+
+ usb_1_dwc3_hs: endpoint {
+ };
+ };
+
+ port@1 {
+ reg = <1>;
+
+ usb_1_dwc3_ss: endpoint {
+ };
+ };
+ };
};
};
@@ -3618,10 +3645,10 @@
<&gcc GCC_USB30_SEC_MASTER_CLK>;
assigned-clock-rates = <19200000>, <200000000>;
- interrupts = <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 487 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 490 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 491 IRQ_TYPE_LEVEL_HIGH>;
+ interrupts-extended = <&intc GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>,
+ <&pdc 7 IRQ_TYPE_LEVEL_HIGH>,
+ <&pdc 10 IRQ_TYPE_EDGE_BOTH>,
+ <&pdc 11 IRQ_TYPE_EDGE_BOTH>;
interrupt-names = "hs_phy_irq", "ss_phy_irq",
"dm_hs_phy_irq", "dp_hs_phy_irq";
@@ -3640,7 +3667,7 @@
iommus = <&apps_smmu 0x160 0>;
snps,dis_u2_susphy_quirk;
snps,dis_enblslpm_quirk;
- phys = <&usb_2_hsphy>, <&usb_2_ssphy>;
+ phys = <&usb_2_hsphy>, <&usb_2_qmpphy>;
phy-names = "usb2-phy", "usb3-phy";
};
};
@@ -3719,6 +3746,13 @@
remote-endpoint = <&mdss_dsi1_in>;
};
};
+
+ port@2 {
+ reg = <2>;
+ dpu_intf0_out: endpoint {
+ remote-endpoint = <&mdss_dp_in>;
+ };
+ };
};
mdp_opp_table: opp-table {
@@ -3746,6 +3780,86 @@
};
};
+ mdss_dp: displayport-controller@ae90000 {
+ compatible = "qcom,sm8150-dp", "qcom,sm8350-dp";
+ reg = <0 0xae90000 0 0x200>,
+ <0 0xae90200 0 0x200>,
+ <0 0xae90400 0 0x600>,
+ <0 0x0ae90a00 0 0x600>,
+ <0 0x0ae91000 0 0x600>;
+
+ interrupt-parent = <&mdss>;
+ interrupts = <12>;
+ clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>,
+ <&dispcc DISP_CC_MDSS_DP_AUX_CLK>,
+ <&dispcc DISP_CC_MDSS_DP_LINK_CLK>,
+ <&dispcc DISP_CC_MDSS_DP_LINK_INTF_CLK>,
+ <&dispcc DISP_CC_MDSS_DP_PIXEL_CLK>;
+ clock-names = "core_iface",
+ "core_aux",
+ "ctrl_link",
+ "ctrl_link_iface",
+ "stream_pixel";
+
+ assigned-clocks = <&dispcc DISP_CC_MDSS_DP_LINK_CLK_SRC>,
+ <&dispcc DISP_CC_MDSS_DP_PIXEL_CLK_SRC>;
+ assigned-clock-parents = <&usb_1_qmpphy QMP_USB43DP_DP_LINK_CLK>,
+ <&usb_1_qmpphy QMP_USB43DP_DP_VCO_DIV_CLK>;
+
+ phys = <&usb_1_qmpphy QMP_USB43DP_DP_PHY>;
+ phy-names = "dp";
+
+ #sound-dai-cells = <0>;
+
+ operating-points-v2 = <&dp_opp_table>;
+ power-domains = <&rpmhpd SM8250_MMCX>;
+
+ status = "disabled";
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+ mdss_dp_in: endpoint {
+ remote-endpoint = <&dpu_intf0_out>;
+ };
+ };
+
+ port@1 {
+ reg = <1>;
+
+ mdss_dp_out: endpoint {
+ };
+ };
+ };
+
+ dp_opp_table: opp-table {
+ compatible = "operating-points-v2";
+
+ opp-160000000 {
+ opp-hz = /bits/ 64 <160000000>;
+ required-opps = <&rpmhpd_opp_low_svs>;
+ };
+
+ opp-270000000 {
+ opp-hz = /bits/ 64 <270000000>;
+ required-opps = <&rpmhpd_opp_svs>;
+ };
+
+ opp-540000000 {
+ opp-hz = /bits/ 64 <540000000>;
+ required-opps = <&rpmhpd_opp_svs_l1>;
+ };
+
+ opp-810000000 {
+ opp-hz = /bits/ 64 <810000000>;
+ required-opps = <&rpmhpd_opp_nom>;
+ };
+ };
+ };
+
mdss_dsi0: dsi@ae94000 {
compatible = "qcom,sm8150-dsi-ctrl", "qcom,mdss-dsi-ctrl";
reg = <0 0x0ae94000 0 0x400>;
@@ -3932,6 +4046,7 @@
"dp_phy_pll_link_clk",
"dp_phy_pll_vco_div_clk";
power-domains = <&rpmhpd SM8150_MMCX>;
+ required-opps = <&rpmhpd_opp_low_svs>;
#clock-cells = <1>;
#reset-cells = <1>;
#power-domain-cells = <1>;
@@ -4170,7 +4285,7 @@
compatible = "qcom,apss-wdt-sm8150", "qcom,kpss-wdt";
reg = <0 0x17c10000 0 0x1000>;
clocks = <&sleep_clk>;
- interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>;
+ interrupts = <GIC_SPI 0 IRQ_TYPE_EDGE_RISING>;
};
timer@17c20000 {
diff --git a/dts/upstream/src/arm64/qcom/sm8250-xiaomi-elish-common.dtsi b/dts/upstream/src/arm64/qcom/sm8250-xiaomi-elish-common.dtsi
index 85e5cf3..946365f 100644
--- a/dts/upstream/src/arm64/qcom/sm8250-xiaomi-elish-common.dtsi
+++ b/dts/upstream/src/arm64/qcom/sm8250-xiaomi-elish-common.dtsi
@@ -6,6 +6,7 @@
#include <dt-bindings/arm/qcom,ids.h>
#include <dt-bindings/phy/phy.h>
#include <dt-bindings/regulator/qcom,rpmh-regulator.h>
+#include <dt-bindings/usb/pd.h>
#include "sm8250.dtsi"
#include "pm8150.dtsi"
#include "pm8150b.dtsi"
@@ -23,7 +24,7 @@
/delete-node/ &xbl_aop_mem;
/ {
- classis-type = "tablet";
+ chassis-type = "tablet";
/* required for bootloader to select correct board */
qcom,msm-id = <QCOM_ID_SM8250 0x20001>; /* SM8250 v2.1 */
@@ -114,7 +115,7 @@
};
reserved-memory {
- xbl_aop_mem: xbl-aop@80700000 {
+ xbl_aop_mem: xbl-aop@80600000 {
reg = <0x0 0x80600000 0x0 0x260000>;
no-map;
};
@@ -627,6 +628,41 @@
};
};
+&pm8150b_typec {
+ vdd-pdphy-supply = <&vreg_l2a_3p1>;
+ status = "okay";
+
+ connector {
+ compatible = "usb-c-connector";
+
+ power-role = "source";
+ data-role = "dual";
+ self-powered;
+
+ source-pdos = <PDO_FIXED(5000, 3000,
+ PDO_FIXED_DUAL_ROLE |
+ PDO_FIXED_USB_COMM |
+ PDO_FIXED_DATA_SWAP)>;
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+
+ pm8150b_role_switch_in: endpoint {
+ remote-endpoint = <&usb_1_role_switch_out>;
+ };
+ };
+ };
+ };
+};
+
+&pm8150b_vbus {
+ status = "okay";
+};
+
&pon_pwrkey {
status = "okay";
};
@@ -664,11 +700,12 @@
};
&usb_1_dwc3 {
- dr_mode = "peripheral";
+ dr_mode = "otg";
maximum-speed = "high-speed";
/* Remove USB3 phy */
phys = <&usb_1_hsphy>;
phy-names = "usb2-phy";
+ usb-role-switch;
};
&usb_1_hsphy {
@@ -678,6 +715,10 @@
status = "okay";
};
+&usb_1_role_switch_out {
+ remote-endpoint = <&pm8150b_role_switch_in>;
+};
+
&ufs_mem_hc {
vcc-supply = <&vreg_l17a_3p0>;
vcc-max-microamp = <800000>;
diff --git a/dts/upstream/src/arm64/qcom/sm8250-xiaomi-pipa.dts b/dts/upstream/src/arm64/qcom/sm8250-xiaomi-pipa.dts
new file mode 100644
index 0000000..86e1f7f
--- /dev/null
+++ b/dts/upstream/src/arm64/qcom/sm8250-xiaomi-pipa.dts
@@ -0,0 +1,623 @@
+// SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
+/*
+ * Copyright (c) 2023 Luka Panio <lukapanio@gmail.com>
+ */
+
+/dts-v1/;
+
+#include <dt-bindings/arm/qcom,ids.h>
+#include <dt-bindings/phy/phy.h>
+#include <dt-bindings/regulator/qcom,rpmh-regulator.h>
+#include "sm8250.dtsi"
+#include "pm8150.dtsi"
+#include "pm8150b.dtsi"
+#include "pm8150l.dtsi"
+#include "pm8009.dtsi"
+
+/*
+ * Delete following upstream (sm8250.dtsi) reserved
+ * memory mappings which are different on this device.
+ */
+/delete-node/ &adsp_mem;
+/delete-node/ &cdsp_secure_heap;
+/delete-node/ &slpi_mem;
+/delete-node/ &spss_mem;
+/delete-node/ &xbl_aop_mem;
+
+/ {
+
+ model = "Xiaomi Pad 6";
+ compatible = "xiaomi,pipa", "qcom,sm8250";
+
+ chassis-type = "tablet";
+
+ /* required for bootloader to select correct board */
+ qcom,msm-id = <QCOM_ID_SM8250 0x20001>; /* SM8250 v2.1 */
+ qcom,board-id = <0x34 0>;
+
+ chosen {
+ #address-cells = <2>;
+ #size-cells = <2>;
+ ranges;
+
+ framebuffer: framebuffer@9c000000 {
+ compatible = "simple-framebuffer";
+ reg = <0x0 0x9c000000 0x0 0x2300000>;
+ width = <1800>;
+ height = <2880>;
+ stride = <(1800 * 4)>;
+ format = "a8r8g8b8";
+ };
+ };
+
+ battery_l: battery-l {
+ compatible = "simple-battery";
+ voltage-min-design-microvolt = <3870000>;
+ energy-full-design-microwatt-hours = <16700000>;
+ charge-full-design-microamp-hours = <4420000>;
+ };
+
+ battery_r: battery-r {
+ compatible = "simple-battery";
+ voltage-min-design-microvolt = <3870000>;
+ energy-full-design-microwatt-hours = <16700000>;
+ charge-full-design-microamp-hours = <4420000>;
+ };
+
+ bl_vddpos_5p5: bl-vddpos-regulator {
+ compatible = "regulator-fixed";
+ regulator-name = "bl_vddpos_5p5";
+ regulator-min-microvolt = <5500000>;
+ regulator-max-microvolt = <5500000>;
+ regulator-enable-ramp-delay = <233>;
+ gpio = <&tlmm 130 GPIO_ACTIVE_HIGH>;
+ enable-active-high;
+ regulator-boot-on;
+ };
+
+ bl_vddneg_5p5: bl-vddneg-regulator {
+ compatible = "regulator-fixed";
+ regulator-name = "bl_vddneg_5p5";
+ regulator-min-microvolt = <5500000>;
+ regulator-max-microvolt = <5500000>;
+ regulator-enable-ramp-delay = <233>;
+ gpio = <&tlmm 131 GPIO_ACTIVE_HIGH>;
+ enable-active-high;
+ regulator-boot-on;
+ };
+
+ gpio_keys: gpio-keys {
+ compatible = "gpio-keys";
+
+ pinctrl-0 = <&vol_up_n>;
+ pinctrl-names = "default";
+
+ key-vol-up {
+ label = "Volume Up";
+ gpios = <&pm8150_gpios 6 GPIO_ACTIVE_LOW>;
+ linux,code = <KEY_VOLUMEUP>;
+ debounce-interval = <15>;
+ linux,can-disable;
+ wakeup-source;
+ };
+ };
+
+ vph_pwr: vph-pwr-regulator {
+ compatible = "regulator-fixed";
+ regulator-name = "vph_pwr";
+ regulator-min-microvolt = <3700000>;
+ regulator-max-microvolt = <3700000>;
+ };
+
+ /* S6c is really ebi.lvl but it's there for supply map completeness sake. */
+ vreg_s6c_0p88: smpc6-regulator {
+ compatible = "regulator-fixed";
+ regulator-name = "vreg_s6c_0p88";
+ regulator-min-microvolt = <880000>;
+ regulator-max-microvolt = <880000>;
+ regulator-always-on;
+ vin-supply = <&vph_pwr>;
+ };
+
+ reserved-memory {
+ xbl_aop_mem: xbl-aop@80700000 {
+ reg = <0x0 0x80600000 0x0 0x260000>;
+ no-map;
+ };
+
+ slpi_mem: slpi@88c00000 {
+ reg = <0x0 0x88c00000 0x0 0x2f00000>;
+ no-map;
+ };
+
+ adsp_mem: adsp@8bb00000 {
+ reg = <0x0 0x8bb00000 0x0 0x2500000>;
+ no-map;
+ };
+
+ spss_mem: spss@8e000000 {
+ reg = <0x0 0x8e000000 0x0 0x100000>;
+ no-map;
+ };
+
+ cdsp_secure_heap: cdsp-secure-heap@8e100000 {
+ reg = <0x0 0x8e100000 0x0 0x4600000>;
+ no-map;
+ };
+
+ cont_splash_mem: cont-splash@9c000000 {
+ reg = <0x0 0x9c000000 0x0 0x2300000>;
+ no-map;
+ };
+
+ ramoops@b0000000 {
+ compatible = "ramoops";
+ reg = <0x0 0xb0000000 0x0 0x400000>;
+ record-size = <0x1000>;
+ console-size = <0x200000>;
+ ecc-size = <16>;
+ no-map;
+ };
+ };
+};
+
+&adsp {
+ firmware-name = "qcom/sm8250/xiaomi/pipa/adsp.mbn";
+ status = "okay";
+};
+
+&apps_rsc {
+ regulators-0 {
+ compatible = "qcom,pm8150-rpmh-regulators";
+ qcom,pmic-id = "a";
+
+ vdd-s1-supply = <&vph_pwr>;
+ vdd-s2-supply = <&vph_pwr>;
+ vdd-s3-supply = <&vph_pwr>;
+ vdd-s4-supply = <&vph_pwr>;
+ vdd-s5-supply = <&vph_pwr>;
+ vdd-s6-supply = <&vph_pwr>;
+ vdd-s7-supply = <&vph_pwr>;
+ vdd-s8-supply = <&vph_pwr>;
+ vdd-s9-supply = <&vph_pwr>;
+ vdd-s10-supply = <&vph_pwr>;
+ vdd-l1-l8-l11-supply = <&vreg_s6c_0p88>;
+ vdd-l2-l10-supply = <&vreg_bob>;
+ vdd-l3-l4-l5-l18-supply = <&vreg_s6a_0p95>;
+ vdd-l6-l9-supply = <&vreg_s8c_1p35>;
+ vdd-l7-l12-l14-l15-supply = <&vreg_s5a_1p9>;
+ vdd-l13-l16-l17-supply = <&vreg_bob>;
+
+ /* (S1+S2+S3) - cx.lvl (ARC) */
+
+ vreg_s4a_1p8: smps4 {
+ regulator-name = "vreg_s4a_1p8";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1920000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ regulator-allow-set-load;
+ regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM
+ RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_s5a_1p9: smps5 {
+ regulator-name = "vreg_s5a_1p9";
+ regulator-min-microvolt = <1900000>;
+ regulator-max-microvolt = <2040000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_s6a_0p95: smps6 {
+ regulator-name = "vreg_s6a_0p95";
+ regulator-min-microvolt = <600000>;
+ regulator-max-microvolt = <1128000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_l2a_3p1: ldo2 {
+ regulator-name = "vreg_l2a_3p1";
+ regulator-min-microvolt = <3072000>;
+ regulator-max-microvolt = <3072000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_l3a_0p9: ldo3 {
+ regulator-name = "vreg_l3a_0p9";
+ regulator-min-microvolt = <928000>;
+ regulator-max-microvolt = <932000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ /* L4 - lmx.lvl (ARC) */
+
+ vreg_l5a_0p88: ldo5 {
+ regulator-name = "vreg_l5a_0p88";
+ regulator-min-microvolt = <880000>;
+ regulator-max-microvolt = <880000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_l6a_1p2: ldo6 {
+ regulator-name = "vreg_l6a_1p2";
+ regulator-min-microvolt = <1200000>;
+ regulator-max-microvolt = <1200000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ regulator-allow-set-load;
+ regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM
+ RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ /* L7 is unused. */
+
+ vreg_l9a_1p2: ldo9 {
+ regulator-name = "vreg_l9a_1p2";
+ regulator-min-microvolt = <1200000>;
+ regulator-max-microvolt = <1200000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ /* L10 is unused, L11 - lcx.lvl (ARC) */
+
+ vreg_l12a_1p8: ldo12 {
+ regulator-name = "vreg_l12a_1p8";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ /* L13 is unused. */
+
+ vreg_l14a_1p88: ldo14 {
+ regulator-name = "vreg_l14a_1p88";
+ regulator-min-microvolt = <1880000>;
+ regulator-max-microvolt = <1880000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ /* L15 & L16 are unused. */
+
+ vreg_l17a_3p0: ldo17 {
+ regulator-name = "vreg_l17a_3p0";
+ regulator-min-microvolt = <2496000>;
+ regulator-max-microvolt = <3008000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ regulator-allow-set-load;
+ regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM
+ RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_l18a_0p9: ldo18 {
+ regulator-name = "vreg_l18a_0p9";
+ regulator-min-microvolt = <800000>;
+ regulator-max-microvolt = <920000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+ };
+
+ regulators-1 {
+ compatible = "qcom,pm8150l-rpmh-regulators";
+ qcom,pmic-id = "c";
+
+ vdd-s1-supply = <&vph_pwr>;
+ vdd-s2-supply = <&vph_pwr>;
+ vdd-s3-supply = <&vph_pwr>;
+ vdd-s4-supply = <&vph_pwr>;
+ vdd-s5-supply = <&vph_pwr>;
+ vdd-s6-supply = <&vph_pwr>;
+ vdd-s7-supply = <&vph_pwr>;
+ vdd-s8-supply = <&vph_pwr>;
+ vdd-l1-l8-supply = <&vreg_s4a_1p8>;
+ vdd-l2-l3-supply = <&vreg_s8c_1p35>;
+ vdd-l4-l5-l6-supply = <&vreg_bob>;
+ vdd-l7-l11-supply = <&vreg_bob>;
+ vdd-l9-l10-supply = <&vreg_bob>;
+ vdd-bob-supply = <&vph_pwr>;
+
+ vreg_bob: bob {
+ regulator-name = "vreg_bob";
+ regulator-min-microvolt = <3350000>;
+ regulator-max-microvolt = <3960000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_AUTO>;
+ };
+
+ /*
+ * S1-S6 are ARCs:
+ * (S1+S2) - gfx.lvl,
+ * S3 - mx.lvl,
+ * (S4+S5) - mmcx.lvl,
+ * S6 - ebi.lvl
+ */
+
+ vreg_s7c_0p35: smps7 {
+ regulator-name = "vreg_s7c_0p35";
+ regulator-min-microvolt = <348000>;
+ regulator-max-microvolt = <1000000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_s8c_1p35: smps8 {
+ regulator-name = "vreg_s8c_1p35";
+ regulator-min-microvolt = <1200000>;
+ regulator-max-microvolt = <1400000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_l1c_1p8: ldo1 {
+ regulator-name = "vreg_l1c_1p8";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ /* L2-4 are unused. */
+
+ vreg_l5c_1p8: ldo5 {
+ regulator-name = "vreg_l5c_1p8";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <2800000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_l6c_2p9: ldo6 {
+ regulator-name = "vreg_l6c_2p9";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <2960000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ regulator-allow-set-load;
+ regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM
+ RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_l7c_2p85: ldo7 {
+ regulator-name = "vreg_l7c_2p85";
+ regulator-min-microvolt = <2856000>;
+ regulator-max-microvolt = <3104000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_l8c_1p8: ldo8 {
+ regulator-name = "vreg_l8c_1p8";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_l9c_2p9: ldo9 {
+ regulator-name = "vreg_l9c_2p9";
+ regulator-min-microvolt = <2704000>;
+ regulator-max-microvolt = <2960000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ regulator-allow-set-load;
+ regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM
+ RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_l10c_3p3: ldo10 {
+ regulator-name = "vreg_l10c_3p3";
+ regulator-min-microvolt = <3000000>;
+ regulator-max-microvolt = <3312000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_l11c_3p0: ldo11 {
+ regulator-name = "vreg_l11c_3p0";
+ regulator-min-microvolt = <3104000>;
+ regulator-max-microvolt = <3304000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+ };
+
+ regulators-2 {
+ compatible = "qcom,pm8009-rpmh-regulators";
+ qcom,pmic-id = "f";
+
+ vdd-s1-supply = <&vph_pwr>;
+ vdd-s2-supply = <&vreg_bob>;
+ vdd-l2-supply = <&vreg_s8c_1p35>;
+ vdd-l5-l6-supply = <&vreg_bob>;
+ vdd-l7-supply = <&vreg_s4a_1p8>;
+
+ vreg_s1f_1p2: smps1 {
+ regulator-name = "vreg_s1f_1p2";
+ regulator-min-microvolt = <1200000>;
+ regulator-max-microvolt = <1300000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_s2f_0p5: smps2 {
+ regulator-name = "vreg_s2f_0p5";
+ regulator-min-microvolt = <512000>;
+ regulator-max-microvolt = <1100000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ /* L1 is unused. */
+
+ vreg_l2f_1p3: ldo2 {
+ regulator-name = "vreg_l2f_1p3";
+ regulator-min-microvolt = <1056000>;
+ regulator-max-microvolt = <1200000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ /* L3 & L4 are unused. */
+
+ vreg_l5f_2p8: ldo5 {
+ regulator-name = "vreg_l5f_2p85";
+ regulator-min-microvolt = <2800000>;
+ regulator-max-microvolt = <3000000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_l6f_2p8: ldo6 {
+ regulator-name = "vreg_l6f_2p8";
+ regulator-min-microvolt = <2800000>;
+ regulator-max-microvolt = <3000000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_l7f_1p8: ldo7 {
+ regulator-name = "vreg_l7f_1p8";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+ };
+};
+
+&cdsp {
+ firmware-name = "qcom/sm8250/xiaomi/pipa/cdsp.mbn";
+ status = "okay";
+};
+
+&gmu {
+ status = "okay";
+};
+
+&gpi_dma0 {
+ status = "okay";
+};
+
+&gpi_dma1 {
+ status = "okay";
+};
+
+&gpi_dma2 {
+ status = "okay";
+};
+
+&gpu {
+ status = "okay";
+
+ zap-shader {
+ memory-region = <&gpu_mem>;
+ firmware-name = "qcom/sm8250/xiaomi/pipa/a650_zap.mbn";
+ };
+};
+
+&i2c0 {
+ clock-frequency = <400000>;
+ status = "okay";
+
+ fuel-gauge@55 {
+ compatible = "ti,bq27z561";
+ reg = <0x55>;
+ monitored-battery = <&battery_r>;
+ };
+};
+
+&i2c11 {
+ clock-frequency = <400000>;
+ status = "okay";
+
+ backlight: backlight@11 {
+ compatible = "kinetic,ktz8866";
+ reg = <0x11>;
+ vddpos-supply = <&bl_vddpos_5p5>;
+ vddneg-supply = <&bl_vddneg_5p5>;
+ enable-gpios = <&tlmm 139 GPIO_ACTIVE_HIGH>;
+ current-num-sinks = <5>;
+ kinetic,current-ramp-delay-ms = <128>;
+ kinetic,led-enable-ramp-delay-ms = <1>;
+ kinetic,enable-lcd-bias;
+ };
+};
+
+&i2c13 {
+ clock-frequency = <400000>;
+ status = "okay";
+
+ fuel-gauge@55 {
+ compatible = "ti,bq27z561";
+ reg = <0x55>;
+ monitored-battery = <&battery_l>;
+ };
+};
+
+&pcie0 {
+ status = "okay";
+};
+
+&pcie0_phy {
+ vdda-phy-supply = <&vreg_l5a_0p88>;
+ vdda-pll-supply = <&vreg_l9a_1p2>;
+ status = "okay";
+};
+
+&pm8150_gpios {
+ vol_up_n: vol-up-n-state {
+ pins = "gpio6";
+ function = "normal";
+ power-source = <1>;
+ input-enable;
+ bias-pull-up;
+ };
+};
+
+&pon_pwrkey {
+ status = "okay";
+};
+
+&pon_resin {
+ linux,code = <KEY_VOLUMEDOWN>;
+ status = "okay";
+};
+
+&qupv3_id_0 {
+ status = "okay";
+};
+
+&qupv3_id_1 {
+ status = "okay";
+};
+
+&qupv3_id_2 {
+ status = "okay";
+};
+
+&slpi {
+ firmware-name = "qcom/sm8250/xiaomi/pipa/slpi.mbn";
+ status = "okay";
+};
+
+&usb_1 {
+ status = "okay";
+};
+
+&usb_1_dwc3 {
+ dr_mode = "peripheral";
+};
+
+&usb_1_hsphy {
+ vdda-pll-supply = <&vreg_l5a_0p88>;
+ vdda18-supply = <&vreg_l12a_1p8>;
+ vdda33-supply = <&vreg_l2a_3p1>;
+ status = "okay";
+};
+
+&usb_1_qmpphy {
+ status = "okay";
+ vdda-phy-supply = <&vreg_l9a_1p2>;
+ vdda-pll-supply = <&vreg_l18a_0p9>;
+};
+
+&ufs_mem_hc {
+ vcc-supply = <&vreg_l17a_3p0>;
+ vcc-max-microamp = <800000>;
+ vccq-supply = <&vreg_l6a_1p2>;
+ vccq-max-microamp = <800000>;
+ vccq2-supply = <&vreg_s4a_1p8>;
+ vccq2-max-microamp = <800000>;
+ status = "okay";
+};
+
+&ufs_mem_phy {
+ vdda-phy-supply = <&vreg_l5a_0p88>;
+ vdda-pll-supply = <&vreg_l9a_1p2>;
+ status = "okay";
+};
+
+&venus {
+ firmware-name = "qcom/sm8250/xiaomi/pipa/venus.mbn";
+ status = "okay";
+};
diff --git a/dts/upstream/src/arm64/qcom/sm8250.dtsi b/dts/upstream/src/arm64/qcom/sm8250.dtsi
index be97047..760501c 100644
--- a/dts/upstream/src/arm64/qcom/sm8250.dtsi
+++ b/dts/upstream/src/arm64/qcom/sm8250.dtsi
@@ -671,6 +671,7 @@
firmware {
scm: scm {
compatible = "qcom,scm-sm8250", "qcom,scm";
+ qcom,dload-mode = <&tcsr 0x13000>;
#reset-cells = <1>;
};
};
@@ -2123,7 +2124,7 @@
qcom,bcm-voters = <&apps_bcm_voter>;
};
- pcie0: pci@1c00000 {
+ pcie0: pcie@1c00000 {
compatible = "qcom,pcie-sm8250";
reg = <0 0x01c00000 0 0x3000>,
<0 0x60000000 0 0xf1d>,
@@ -2227,7 +2228,7 @@
status = "disabled";
};
- pcie1: pci@1c08000 {
+ pcie1: pcie@1c08000 {
compatible = "qcom,pcie-sm8250";
reg = <0 0x01c08000 0 0x3000>,
<0 0x40000000 0 0xf1d>,
@@ -2328,7 +2329,7 @@
status = "disabled";
};
- pcie2: pci@1c10000 {
+ pcie2: pcie@1c10000 {
compatible = "qcom,pcie-sm8250";
reg = <0 0x01c10000 0 0x3000>,
<0 0x64000000 0 0xf1d>,
@@ -2434,7 +2435,7 @@
"jedec,ufs-2.0";
reg = <0 0x01d84000 0 0x3000>;
interrupts = <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH>;
- phys = <&ufs_mem_phy_lanes>;
+ phys = <&ufs_mem_phy>;
phy-names = "ufsphy";
lanes-per-direction = <2>;
#reset-cells = <1>;
@@ -2463,29 +2464,48 @@
<&gcc GCC_UFS_PHY_TX_SYMBOL_0_CLK>,
<&gcc GCC_UFS_PHY_RX_SYMBOL_0_CLK>,
<&gcc GCC_UFS_PHY_RX_SYMBOL_1_CLK>;
- freq-table-hz =
- <37500000 300000000>,
- <0 0>,
- <0 0>,
- <37500000 300000000>,
- <0 0>,
- <0 0>,
- <0 0>,
- <0 0>;
+
+ operating-points-v2 = <&ufs_opp_table>;
interconnects = <&aggre1_noc MASTER_UFS_MEM 0 &mc_virt SLAVE_EBI_CH0 0>,
<&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_UFS_MEM_CFG 0>;
interconnect-names = "ufs-ddr", "cpu-ufs";
status = "disabled";
+
+ ufs_opp_table: opp-table {
+ compatible = "operating-points-v2";
+
+ opp-37500000 {
+ opp-hz = /bits/ 64 <37500000>,
+ /bits/ 64 <0>,
+ /bits/ 64 <0>,
+ /bits/ 64 <37500000>,
+ /bits/ 64 <0>,
+ /bits/ 64 <0>,
+ /bits/ 64 <0>,
+ /bits/ 64 <0>;
+ required-opps = <&rpmhpd_opp_low_svs>;
+ };
+
+ opp-300000000 {
+ opp-hz = /bits/ 64 <300000000>,
+ /bits/ 64 <0>,
+ /bits/ 64 <0>,
+ /bits/ 64 <300000000>,
+ /bits/ 64 <0>,
+ /bits/ 64 <0>,
+ /bits/ 64 <0>,
+ /bits/ 64 <0>;
+ required-opps = <&rpmhpd_opp_nom>;
+ };
+ };
};
ufs_mem_phy: phy@1d87000 {
compatible = "qcom,sm8250-qmp-ufs-phy";
- reg = <0 0x01d87000 0 0x1c0>;
- #address-cells = <2>;
- #size-cells = <2>;
- ranges;
+ reg = <0 0x01d87000 0 0x1000>;
+
clock-names = "ref",
"ref_aux";
clocks = <&rpmhcc RPMH_CXO_CLK>,
@@ -2493,16 +2513,10 @@
resets = <&ufs_mem_hc 0>;
reset-names = "ufsphy";
- status = "disabled";
- ufs_mem_phy_lanes: phy@1d87400 {
- reg = <0 0x01d87400 0 0x16c>,
- <0 0x01d87600 0 0x200>,
- <0 0x01d87c00 0 0x200>,
- <0 0x01d87800 0 0x16c>,
- <0 0x01d87a00 0 0x200>;
- #phy-cells = <0>;
- };
+ #phy-cells = <0>;
+
+ status = "disabled";
};
cryptobam: dma-controller@1dc4000 {
@@ -2543,6 +2557,11 @@
#hwlock-cells = <1>;
};
+ tcsr: syscon@1fc0000 {
+ compatible = "qcom,sm8250-tcsr", "syscon";
+ reg = <0x0 0x1fc0000 0x0 0x30000>;
+ };
+
wsamacro: codec@3240000 {
compatible = "qcom,sm8250-lpass-wsa-macro";
reg = <0 0x03240000 0 0x1000>;
@@ -2565,7 +2584,7 @@
status = "disabled";
};
- swr0: soundwire-controller@3250000 {
+ swr0: soundwire@3250000 {
reg = <0 0x03250000 0 0x2000>;
compatible = "qcom,soundwire-v1.5.1";
interrupts = <GIC_SPI 202 IRQ_TYPE_LEVEL_HIGH>;
@@ -2631,7 +2650,7 @@
#sound-dai-cells = <1>;
};
- swr1: soundwire-controller@3210000 {
+ swr1: soundwire@3210000 {
reg = <0 0x03210000 0 0x2000>;
compatible = "qcom,soundwire-v1.5.1";
status = "disabled";
@@ -2678,7 +2697,7 @@
};
/* tx macro */
- swr2: soundwire-controller@3230000 {
+ swr2: soundwire@3230000 {
reg = <0 0x03230000 0 0x2000>;
compatible = "qcom,soundwire-v1.5.1";
interrupts = <GIC_SPI 297 IRQ_TYPE_LEVEL_HIGH>;
@@ -3095,11 +3114,8 @@
clock-names = "apb_pclk";
out-ports {
- #address-cells = <1>;
- #size-cells = <0>;
- port@0 {
- reg = <0>;
+ port {
tpda_out_funnel_qatb: endpoint {
remote-endpoint = <&funnel_qatb_in_tpda>;
};
@@ -3142,11 +3158,7 @@
};
in-ports {
- #address-cells = <1>;
- #size-cells = <0>;
-
- port@0 {
- reg = <0>;
+ port {
funnel_qatb_in_tpda: endpoint {
remote-endpoint = <&tpda_out_funnel_qatb>;
};
@@ -3355,11 +3367,8 @@
};
in-ports {
- #address-cells = <1>;
- #size-cells = <0>;
- port@0 {
- reg = <0>;
+ port {
etf_in_funnel_swao_out: endpoint {
remote-endpoint = <&funnel_swao_out_etf>;
};
@@ -3443,8 +3452,6 @@
clock-names = "apb_pclk";
out-ports {
- #address-cells = <1>;
- #size-cells = <0>;
port {
tpdm_mm_out_tpda9: endpoint {
remote-endpoint = <&tpda_9_in_tpdm_mm>;
@@ -3710,11 +3717,7 @@
};
in-ports {
- #address-cells = <1>;
- #size-cells = <0>;
-
- port@0 {
- reg = <0>;
+ port {
funnel_apss_merg_in_funnel_apss: endpoint {
remote-endpoint = <&funnel_apss_out_funnel_apss_merg>;
};
@@ -3889,32 +3892,26 @@
usb_2_qmpphy: phy@88eb000 {
compatible = "qcom,sm8250-qmp-usb3-uni-phy";
- reg = <0 0x088eb000 0 0x200>;
- status = "disabled";
- #address-cells = <2>;
- #size-cells = <2>;
- ranges;
+ reg = <0 0x088eb000 0 0x1000>;
clocks = <&gcc GCC_USB3_SEC_PHY_AUX_CLK>,
- <&rpmhcc RPMH_CXO_CLK>,
<&gcc GCC_USB3_SEC_CLKREF_EN>,
- <&gcc GCC_USB3_SEC_PHY_COM_AUX_CLK>;
- clock-names = "aux", "ref_clk_src", "ref", "com_aux";
+ <&gcc GCC_USB3_SEC_PHY_COM_AUX_CLK>,
+ <&gcc GCC_USB3_SEC_PHY_PIPE_CLK>;
+ clock-names = "aux",
+ "ref",
+ "com_aux",
+ "pipe";
+ clock-output-names = "usb3_uni_phy_pipe_clk_src";
+ #clock-cells = <0>;
+ #phy-cells = <0>;
- resets = <&gcc GCC_USB3PHY_PHY_SEC_BCR>,
- <&gcc GCC_USB3_PHY_SEC_BCR>;
- reset-names = "phy", "common";
+ resets = <&gcc GCC_USB3_PHY_SEC_BCR>,
+ <&gcc GCC_USB3PHY_PHY_SEC_BCR>;
+ reset-names = "phy",
+ "phy_phy";
- usb_2_ssphy: phy@88eb200 {
- reg = <0 0x088eb200 0 0x200>,
- <0 0x088eb400 0 0x200>,
- <0 0x088eb800 0 0x800>;
- #clock-cells = <0>;
- #phy-cells = <0>;
- clocks = <&gcc GCC_USB3_SEC_PHY_PIPE_CLK>;
- clock-names = "pipe0";
- clock-output-names = "usb3_uni_phy_pipe_clk_src";
- };
+ status = "disabled";
};
sdhc_2: mmc@8804000 {
@@ -4141,6 +4138,7 @@
"dp_hs_phy_irq";
power-domains = <&gcc USB30_PRIM_GDSC>;
+ wakeup-source;
resets = <&gcc GCC_USB30_PRIM_BCR>;
@@ -4209,6 +4207,7 @@
"dp_hs_phy_irq";
power-domains = <&gcc USB30_SEC_GDSC>;
+ wakeup-source;
resets = <&gcc GCC_USB30_SEC_BCR>;
@@ -4223,7 +4222,7 @@
iommus = <&apps_smmu 0x20 0>;
snps,dis_u2_susphy_quirk;
snps,dis_enblslpm_quirk;
- phys = <&usb_2_hsphy>, <&usb_2_ssphy>;
+ phys = <&usb_2_hsphy>, <&usb_2_qmpphy>;
phy-names = "usb2-phy", "usb3-phy";
};
};
@@ -6018,7 +6017,7 @@
compatible = "qcom,apss-wdt-sm8250", "qcom,kpss-wdt";
reg = <0 0x17c10000 0 0x1000>;
clocks = <&sleep_clk>;
- interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>;
+ interrupts = <GIC_SPI 0 IRQ_TYPE_EDGE_RISING>;
};
timer@17c20000 {
diff --git a/dts/upstream/src/arm64/qcom/sm8350.dtsi b/dts/upstream/src/arm64/qcom/sm8350.dtsi
index b462362..e78c83a 100644
--- a/dts/upstream/src/arm64/qcom/sm8350.dtsi
+++ b/dts/upstream/src/arm64/qcom/sm8350.dtsi
@@ -289,6 +289,7 @@
firmware {
scm: scm {
compatible = "qcom,scm-sm8350", "qcom,scm";
+ qcom,dload-mode = <&tcsr 0x13000>;
#reset-cells = <1>;
};
};
@@ -677,9 +678,9 @@
<0>,
<0>,
<0>,
- <&ufs_mem_phy_lanes 0>,
- <&ufs_mem_phy_lanes 1>,
- <&ufs_mem_phy_lanes 2>,
+ <&ufs_mem_phy 0>,
+ <&ufs_mem_phy 1>,
+ <&ufs_mem_phy 2>,
<&usb_1_qmpphy QMP_USB43DP_USB3_PIPE_CLK>,
<0>;
};
@@ -919,9 +920,9 @@
};
};
- gpi_dma0: dma-controller@9800000 {
+ gpi_dma0: dma-controller@900000 {
compatible = "qcom,sm8350-gpi-dma", "qcom,sm6350-gpi-dma";
- reg = <0 0x09800000 0 0x60000>;
+ reg = <0 0x00900000 0 0x60000>;
interrupts = <GIC_SPI 244 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 245 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 246 IRQ_TYPE_LEVEL_HIGH>,
@@ -1498,7 +1499,7 @@
qcom,bcm-voters = <&apps_bcm_voter>;
};
- pcie0: pci@1c00000 {
+ pcie0: pcie@1c00000 {
compatible = "qcom,pcie-sm8350";
reg = <0 0x01c00000 0 0x3000>,
<0 0x60000000 0 0xf1d>,
@@ -1591,7 +1592,7 @@
status = "disabled";
};
- pcie1: pci@1c08000 {
+ pcie1: pcie@1c08000 {
compatible = "qcom,pcie-sm8350";
reg = <0 0x01c08000 0 0x3000>,
<0 0x40000000 0 0xf1d>,
@@ -1679,7 +1680,7 @@
"jedec,ufs-2.0";
reg = <0 0x01d84000 0 0x3000>;
interrupts = <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH>;
- phys = <&ufs_mem_phy_lanes>;
+ phys = <&ufs_mem_phy>;
phy-names = "ufsphy";
lanes-per-direction = <2>;
#reset-cells = <1>;
@@ -1723,10 +1724,8 @@
ufs_mem_phy: phy@1d87000 {
compatible = "qcom,sm8350-qmp-ufs-phy";
- reg = <0 0x01d87000 0 0x1c4>;
- #address-cells = <2>;
- #size-cells = <2>;
- ranges;
+ reg = <0 0x01d87000 0 0x1000>;
+
clock-names = "ref",
"ref_aux";
clocks = <&rpmhcc RPMH_CXO_CLK>,
@@ -1734,17 +1733,11 @@
resets = <&ufs_mem_hc 0>;
reset-names = "ufsphy";
- status = "disabled";
- ufs_mem_phy_lanes: phy@1d87400 {
- reg = <0 0x01d87400 0 0x188>,
- <0 0x01d87600 0 0x200>,
- <0 0x01d87c00 0 0x200>,
- <0 0x01d87800 0 0x188>,
- <0 0x01d87a00 0 0x200>;
- #clock-cells = <1>;
- #phy-cells = <0>;
- };
+ #clock-cells = <1>;
+ #phy-cells = <0>;
+
+ status = "disabled";
};
cryptobam: dma-controller@1dc4000 {
@@ -1818,6 +1811,11 @@
#hwlock-cells = <1>;
};
+ tcsr: syscon@1fc0000 {
+ compatible = "qcom,sm8350-tcsr", "syscon";
+ reg = <0x0 0x1fc0000 0x0 0x30000>;
+ };
+
lpass_tlmm: pinctrl@33c0000 {
compatible = "qcom,sm8350-lpass-lpi-pinctrl";
reg = <0 0x033c0000 0 0x20000>,
@@ -2021,7 +2019,7 @@
compatible = "qcom,sm8350-mpss-pas";
reg = <0x0 0x04080000 0x0 0x4040>;
- interrupts-extended = <&intc GIC_SPI 264 IRQ_TYPE_LEVEL_HIGH>,
+ interrupts-extended = <&intc GIC_SPI 264 IRQ_TYPE_EDGE_RISING>,
<&smp2p_modem_in 0 IRQ_TYPE_EDGE_RISING>,
<&smp2p_modem_in 1 IRQ_TYPE_EDGE_RISING>,
<&smp2p_modem_in 2 IRQ_TYPE_EDGE_RISING>,
@@ -2063,7 +2061,7 @@
compatible = "qcom,sm8350-slpi-pas";
reg = <0 0x05c00000 0 0x4000>;
- interrupts-extended = <&pdc 9 IRQ_TYPE_LEVEL_HIGH>,
+ interrupts-extended = <&pdc 9 IRQ_TYPE_EDGE_RISING>,
<&smp2p_slpi_in 0 IRQ_TYPE_EDGE_RISING>,
<&smp2p_slpi_in 1 IRQ_TYPE_EDGE_RISING>,
<&smp2p_slpi_in 2 IRQ_TYPE_EDGE_RISING>,
@@ -2238,34 +2236,27 @@
};
};
- usb_2_qmpphy: phy-wrapper@88eb000 {
+ usb_2_qmpphy: phy@88eb000 {
compatible = "qcom,sm8350-qmp-usb3-uni-phy";
- reg = <0 0x088eb000 0 0x200>;
+ reg = <0 0x088eb000 0 0x2000>;
status = "disabled";
- #address-cells = <2>;
- #size-cells = <2>;
- ranges;
clocks = <&gcc GCC_USB3_SEC_PHY_AUX_CLK>,
- <&rpmhcc RPMH_CXO_CLK>,
<&gcc GCC_USB3_SEC_CLKREF_EN>,
- <&gcc GCC_USB3_SEC_PHY_COM_AUX_CLK>;
- clock-names = "aux", "ref_clk_src", "ref", "com_aux";
-
- resets = <&gcc GCC_USB3PHY_PHY_SEC_BCR>,
- <&gcc GCC_USB3_PHY_SEC_BCR>;
- reset-names = "phy", "common";
+ <&gcc GCC_USB3_SEC_PHY_COM_AUX_CLK>,
+ <&gcc GCC_USB3_SEC_PHY_PIPE_CLK>;
+ clock-names = "aux",
+ "ref",
+ "com_aux",
+ "pipe";
+ clock-output-names = "usb3_uni_phy_pipe_clk_src";
+ #clock-cells = <0>;
+ #phy-cells = <0>;
- usb_2_ssphy: phy@88ebe00 {
- reg = <0 0x088ebe00 0 0x200>,
- <0 0x088ec000 0 0x200>,
- <0 0x088eb200 0 0x1100>;
- #phy-cells = <0>;
- #clock-cells = <0>;
- clocks = <&gcc GCC_USB3_SEC_PHY_PIPE_CLK>;
- clock-names = "pipe0";
- clock-output-names = "usb3_uni_phy_pipe_clk_src";
- };
+ resets = <&gcc GCC_USB3_PHY_SEC_BCR>,
+ <&gcc GCC_USB3PHY_PHY_SEC_BCR>;
+ reset-names = "phy",
+ "phy_phy";
};
dc_noc: interconnect@90c0000 {
@@ -2418,7 +2409,7 @@
iommus = <&apps_smmu 0x20 0x0>;
snps,dis_u2_susphy_quirk;
snps,dis_enblslpm_quirk;
- phys = <&usb_2_hsphy>, <&usb_2_ssphy>;
+ phys = <&usb_2_hsphy>, <&usb_2_qmpphy>;
phy-names = "usb2-phy", "usb3-phy";
};
};
@@ -2453,35 +2444,6 @@
#size-cells = <2>;
ranges;
- dpu_opp_table: opp-table {
- compatible = "operating-points-v2";
-
- /* TODO: opp-200000000 should work with
- * &rpmhpd_opp_low_svs, but one some of
- * sm8350_hdk boards reboot using this
- * opp.
- */
- opp-200000000 {
- opp-hz = /bits/ 64 <200000000>;
- required-opps = <&rpmhpd_opp_svs>;
- };
-
- opp-300000000 {
- opp-hz = /bits/ 64 <300000000>;
- required-opps = <&rpmhpd_opp_svs>;
- };
-
- opp-345000000 {
- opp-hz = /bits/ 64 <345000000>;
- required-opps = <&rpmhpd_opp_svs_l1>;
- };
-
- opp-460000000 {
- opp-hz = /bits/ 64 <460000000>;
- required-opps = <&rpmhpd_opp_nom>;
- };
- };
-
mdss_mdp: display-controller@ae01000 {
compatible = "qcom,sm8350-dpu";
reg = <0 0x0ae01000 0 0x8f000>,
@@ -2510,6 +2472,35 @@
interrupt-parent = <&mdss>;
interrupts = <0>;
+ dpu_opp_table: opp-table {
+ compatible = "operating-points-v2";
+
+ /* TODO: opp-200000000 should work with
+ * &rpmhpd_opp_low_svs, but one some of
+ * sm8350_hdk boards reboot using this
+ * opp.
+ */
+ opp-200000000 {
+ opp-hz = /bits/ 64 <200000000>;
+ required-opps = <&rpmhpd_opp_svs>;
+ };
+
+ opp-300000000 {
+ opp-hz = /bits/ 64 <300000000>;
+ required-opps = <&rpmhpd_opp_svs>;
+ };
+
+ opp-345000000 {
+ opp-hz = /bits/ 64 <345000000>;
+ required-opps = <&rpmhpd_opp_svs_l1>;
+ };
+
+ opp-460000000 {
+ opp-hz = /bits/ 64 <460000000>;
+ required-opps = <&rpmhpd_opp_nom>;
+ };
+ };
+
ports {
#address-cells = <1>;
#size-cells = <0>;
@@ -3207,7 +3198,7 @@
compatible = "qcom,sm8350-adsp-pas";
reg = <0 0x17300000 0 0x100>;
- interrupts-extended = <&pdc 6 IRQ_TYPE_LEVEL_HIGH>,
+ interrupts-extended = <&pdc 6 IRQ_TYPE_EDGE_RISING>,
<&smp2p_adsp_in 0 IRQ_TYPE_EDGE_RISING>,
<&smp2p_adsp_in 1 IRQ_TYPE_EDGE_RISING>,
<&smp2p_adsp_in 2 IRQ_TYPE_EDGE_RISING>,
@@ -3512,7 +3503,7 @@
compatible = "qcom,sm8350-cdsp-pas";
reg = <0 0x98900000 0 0x1400000>;
- interrupts-extended = <&intc GIC_SPI 578 IRQ_TYPE_LEVEL_HIGH>,
+ interrupts-extended = <&intc GIC_SPI 578 IRQ_TYPE_EDGE_RISING>,
<&smp2p_cdsp_in 0 IRQ_TYPE_EDGE_RISING>,
<&smp2p_cdsp_in 1 IRQ_TYPE_EDGE_RISING>,
<&smp2p_cdsp_in 2 IRQ_TYPE_EDGE_RISING>,
diff --git a/dts/upstream/src/arm64/qcom/sm8450-hdk.dts b/dts/upstream/src/arm64/qcom/sm8450-hdk.dts
index 20153d0..a20d5d7 100644
--- a/dts/upstream/src/arm64/qcom/sm8450-hdk.dts
+++ b/dts/upstream/src/arm64/qcom/sm8450-hdk.dts
@@ -580,6 +580,14 @@
status = "okay";
};
+&gpu {
+ status = "okay";
+
+ zap-shader {
+ firmware-name = "qcom/sm8450/a730_zap.mbn";
+ };
+};
+
&i2c9 {
clock-frequency = <400000>;
status = "okay";
diff --git a/dts/upstream/src/arm64/qcom/sm8450.dtsi b/dts/upstream/src/arm64/qcom/sm8450.dtsi
index 1783fa7..01e4dfc 100644
--- a/dts/upstream/src/arm64/qcom/sm8450.dtsi
+++ b/dts/upstream/src/arm64/qcom/sm8450.dtsi
@@ -8,6 +8,7 @@
#include <dt-bindings/clock/qcom,rpmh.h>
#include <dt-bindings/clock/qcom,sm8450-camcc.h>
#include <dt-bindings/clock/qcom,sm8450-dispcc.h>
+#include <dt-bindings/clock/qcom,sm8450-gpucc.h>
#include <dt-bindings/clock/qcom,sm8450-videocc.h>
#include <dt-bindings/dma/qcom-gpi.h>
#include <dt-bindings/firmware/qcom,scm.h>
@@ -18,6 +19,7 @@
#include <dt-bindings/power/qcom-rpmpd.h>
#include <dt-bindings/interconnect/qcom,icc.h>
#include <dt-bindings/interconnect/qcom,sm8450.h>
+#include <dt-bindings/reset/qcom,sm8450-gpucc.h>
#include <dt-bindings/soc/qcom,gpr.h>
#include <dt-bindings/soc/qcom,rpmh-rsc.h>
#include <dt-bindings/sound/qcom,q6dsp-lpass-ports.h>
@@ -754,9 +756,9 @@
<&pcie0_phy>,
<&pcie1_phy>,
<0>,
- <&ufs_mem_phy_lanes 0>,
- <&ufs_mem_phy_lanes 1>,
- <&ufs_mem_phy_lanes 2>,
+ <&ufs_mem_phy 0>,
+ <&ufs_mem_phy 1>,
+ <&ufs_mem_phy 2>,
<&usb_1_qmpphy QMP_USB43DP_USB3_PIPE_CLK>;
clock-names = "bi_tcxo",
"sleep_clk",
@@ -1739,7 +1741,12 @@
};
};
- pcie0: pci@1c00000 {
+ rng: rng@10c3000 {
+ compatible = "qcom,sm8450-trng", "qcom,trng";
+ reg = <0 0x010c3000 0 0x1000>;
+ };
+
+ pcie0: pcie@1c00000 {
compatible = "qcom,pcie-sm8450-pcie0";
reg = <0 0x01c00000 0 0x3000>,
<0 0x60000000 0 0xf1d>,
@@ -1848,7 +1855,7 @@
status = "disabled";
};
- pcie1: pci@1c08000 {
+ pcie1: pcie@1c08000 {
compatible = "qcom,pcie-sm8450-pcie1";
reg = <0 0x01c08000 0 0x3000>,
<0 0x40000000 0 0xf1d>,
@@ -2014,6 +2021,206 @@
reg = <0x0 0x1fc0000 0x0 0x30000>;
};
+ gpu: gpu@3d00000 {
+ compatible = "qcom,adreno-730.1", "qcom,adreno";
+ reg = <0x0 0x03d00000 0x0 0x40000>,
+ <0x0 0x03d9e000 0x0 0x1000>,
+ <0x0 0x03d61000 0x0 0x800>;
+ reg-names = "kgsl_3d0_reg_memory",
+ "cx_mem",
+ "cx_dbgc";
+
+ interrupts = <GIC_SPI 300 IRQ_TYPE_LEVEL_HIGH>;
+
+ iommus = <&adreno_smmu 0 0x400>,
+ <&adreno_smmu 1 0x400>;
+
+ operating-points-v2 = <&gpu_opp_table>;
+
+ qcom,gmu = <&gmu>;
+
+ status = "disabled";
+
+ zap-shader {
+ memory-region = <&gpu_micro_code_mem>;
+ };
+
+ gpu_opp_table: opp-table {
+ compatible = "operating-points-v2";
+
+ opp-818000000 {
+ opp-hz = /bits/ 64 <818000000>;
+ opp-level = <RPMH_REGULATOR_LEVEL_TURBO>;
+ };
+
+ opp-791000000 {
+ opp-hz = /bits/ 64 <791000000>;
+ opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>;
+ };
+
+ opp-734000000 {
+ opp-hz = /bits/ 64 <734000000>;
+ opp-level = <RPMH_REGULATOR_LEVEL_NOM>;
+ };
+
+ opp-640000000 {
+ opp-hz = /bits/ 64 <640000000>;
+ opp-level = <RPMH_REGULATOR_LEVEL_SVS_L2>;
+ };
+
+ opp-599000000 {
+ opp-hz = /bits/ 64 <599000000>;
+ opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>;
+ };
+
+ opp-545000000 {
+ opp-hz = /bits/ 64 <545000000>;
+ opp-level = <RPMH_REGULATOR_LEVEL_SVS_L0>;
+ };
+
+ opp-492000000 {
+ opp-hz = /bits/ 64 <492000000>;
+ opp-level = <RPMH_REGULATOR_LEVEL_SVS>;
+ };
+
+ opp-421000000 {
+ opp-hz = /bits/ 64 <421000000>;
+ opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS_L1>;
+ };
+
+ opp-350000000 {
+ opp-hz = /bits/ 64 <350000000>;
+ opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>;
+ };
+
+ opp-317000000 {
+ opp-hz = /bits/ 64 <317000000>;
+ opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>;
+ };
+
+ opp-285000000 {
+ opp-hz = /bits/ 64 <285000000>;
+ opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS_D1>;
+ };
+
+ opp-220000000 {
+ opp-hz = /bits/ 64 <220000000>;
+ opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS_D1>;
+ };
+ };
+ };
+
+ gmu: gmu@3d6a000 {
+ compatible = "qcom,adreno-gmu-730.1", "qcom,adreno-gmu";
+ reg = <0x0 0x03d6a000 0x0 0x35000>,
+ <0x0 0x03d50000 0x0 0x10000>,
+ <0x0 0x0b290000 0x0 0x10000>;
+ reg-names = "gmu", "rscc", "gmu_pdc";
+
+ interrupts = <GIC_SPI 304 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 305 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "hfi", "gmu";
+
+ clocks = <&gpucc GPU_CC_AHB_CLK>,
+ <&gpucc GPU_CC_CX_GMU_CLK>,
+ <&gpucc GPU_CC_CXO_CLK>,
+ <&gcc GCC_DDRSS_GPU_AXI_CLK>,
+ <&gcc GCC_GPU_MEMNOC_GFX_CLK>,
+ <&gpucc GPU_CC_HUB_CX_INT_CLK>,
+ <&gpucc GPU_CC_DEMET_CLK>;
+ clock-names = "ahb",
+ "gmu",
+ "cxo",
+ "axi",
+ "memnoc",
+ "hub",
+ "demet";
+
+ power-domains = <&gpucc GPU_CX_GDSC>,
+ <&gpucc GPU_GX_GDSC>;
+ power-domain-names = "cx",
+ "gx";
+
+ iommus = <&adreno_smmu 5 0x400>;
+
+ qcom,qmp = <&aoss_qmp>;
+
+ operating-points-v2 = <&gmu_opp_table>;
+
+ gmu_opp_table: opp-table {
+ compatible = "operating-points-v2";
+
+ opp-500000000 {
+ opp-hz = /bits/ 64 <500000000>;
+ opp-level = <RPMH_REGULATOR_LEVEL_SVS>;
+ };
+
+ opp-200000000 {
+ opp-hz = /bits/ 64 <200000000>;
+ opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>;
+ };
+ };
+ };
+
+ gpucc: clock-controller@3d90000 {
+ compatible = "qcom,sm8450-gpucc";
+ reg = <0x0 0x03d90000 0x0 0xa000>;
+ clocks = <&rpmhcc RPMH_CXO_CLK>,
+ <&gcc GCC_GPU_GPLL0_CLK_SRC>,
+ <&gcc GCC_GPU_GPLL0_DIV_CLK_SRC>;
+ #clock-cells = <1>;
+ #reset-cells = <1>;
+ #power-domain-cells = <1>;
+ };
+
+ adreno_smmu: iommu@3da0000 {
+ compatible = "qcom,sm8450-smmu-500", "qcom,adreno-smmu",
+ "qcom,smmu-500", "arm,mmu-500";
+ reg = <0x0 0x03da0000 0x0 0x40000>;
+ #iommu-cells = <2>;
+ #global-interrupts = <1>;
+ interrupts = <GIC_SPI 673 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 678 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 679 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 680 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 681 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 682 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 683 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 684 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 685 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 686 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 687 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 422 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 476 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 574 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 575 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 576 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 577 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 659 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 661 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 664 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 665 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 666 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 668 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 669 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 699 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 700 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&gpucc GPU_CC_CX_GMU_CLK>,
+ <&gpucc GPU_CC_HUB_CX_INT_CLK>,
+ <&gpucc GPU_CC_HLOS1_VOTE_GPU_SMMU_CLK>,
+ <&gcc GCC_GPU_MEMNOC_GFX_CLK>,
+ <&gcc GCC_GPU_SNOC_DVM_GFX_CLK>,
+ <&gpucc GPU_CC_AHB_CLK>;
+ clock-names = "gmu",
+ "hub",
+ "hlos",
+ "bus",
+ "iface",
+ "ahb";
+ power-domains = <&gpucc GPU_CX_GDSC>;
+ dma-coherent;
+ };
+
usb_1_hsphy: phy@88e3000 {
compatible = "qcom,sm8450-usb-hs-phy",
"qcom,usb-snps-hs-7nm-phy";
@@ -2149,18 +2356,13 @@
<&q6prmcc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
<&vamacro>;
clock-names = "mclk", "npl", "macro", "dcodec", "fsgen";
- assigned-clocks = <&q6prmcc LPASS_CLK_ID_WSA2_CORE_TX_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
- <&q6prmcc LPASS_CLK_ID_WSA2_CORE_TX_2X_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>;
- assigned-clock-rates = <19200000>, <19200000>;
#clock-cells = <0>;
clock-output-names = "wsa2-mclk";
- pinctrl-names = "default";
- pinctrl-0 = <&wsa2_swr_active>;
#sound-dai-cells = <1>;
};
- swr4: soundwire-controller@31f0000 {
+ swr4: soundwire@31f0000 {
compatible = "qcom,soundwire-v1.7.0";
reg = <0 0x031f0000 0 0x2000>;
interrupts = <GIC_SPI 171 IRQ_TYPE_LEVEL_HIGH>;
@@ -2168,6 +2370,9 @@
clock-names = "iface";
label = "WSA2";
+ pinctrl-0 = <&wsa2_swr_active>;
+ pinctrl-names = "default";
+
qcom,din-ports = <2>;
qcom,dout-ports = <6>;
@@ -2197,18 +2402,12 @@
<&vamacro>;
clock-names = "mclk", "npl", "macro", "dcodec", "fsgen";
- assigned-clocks = <&q6prmcc LPASS_CLK_ID_RX_CORE_TX_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
- <&q6prmcc LPASS_CLK_ID_RX_CORE_MCLK2_2X_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>;
- assigned-clock-rates = <19200000>, <19200000>;
-
#clock-cells = <0>;
clock-output-names = "mclk";
- pinctrl-names = "default";
- pinctrl-0 = <&rx_swr_active>;
#sound-dai-cells = <1>;
};
- swr1: soundwire-controller@3210000 {
+ swr1: soundwire@3210000 {
compatible = "qcom,soundwire-v1.7.0";
reg = <0 0x03210000 0 0x2000>;
interrupts = <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>;
@@ -2218,6 +2417,9 @@
qcom,din-ports = <0>;
qcom,dout-ports = <5>;
+ pinctrl-0 = <&rx_swr_active>;
+ pinctrl-names = "default";
+
qcom,ports-sinterval-low = /bits/ 8 <0x03 0x1f 0x1f 0x07 0x00>;
qcom,ports-offset1 = /bits/ 8 <0x00 0x00 0x0b 0x01 0x00>;
qcom,ports-offset2 = /bits/ 8 <0x00 0x00 0x0b 0x00 0x00>;
@@ -2243,14 +2445,9 @@
<&q6prmcc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
<&vamacro>;
clock-names = "mclk", "npl", "macro", "dcodec", "fsgen";
- assigned-clocks = <&q6prmcc LPASS_CLK_ID_RX_CORE_TX_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
- <&q6prmcc LPASS_CLK_ID_RX_CORE_MCLK2_2X_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>;
- assigned-clock-rates = <19200000>, <19200000>;
#clock-cells = <0>;
clock-output-names = "mclk";
- pinctrl-names = "default";
- pinctrl-0 = <&tx_swr_active>;
#sound-dai-cells = <1>;
};
@@ -2264,18 +2461,12 @@
<&vamacro>;
clock-names = "mclk", "npl", "macro", "dcodec", "fsgen";
- assigned-clocks = <&q6prmcc LPASS_CLK_ID_WSA_CORE_TX_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
- <&q6prmcc LPASS_CLK_ID_WSA_CORE_TX_2X_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>;
- assigned-clock-rates = <19200000>, <19200000>;
-
#clock-cells = <0>;
clock-output-names = "mclk";
- pinctrl-names = "default";
- pinctrl-0 = <&wsa_swr_active>;
#sound-dai-cells = <1>;
};
- swr0: soundwire-controller@3250000 {
+ swr0: soundwire@3250000 {
compatible = "qcom,soundwire-v1.7.0";
reg = <0 0x03250000 0 0x2000>;
interrupts = <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>;
@@ -2283,6 +2474,9 @@
clock-names = "iface";
label = "WSA";
+ pinctrl-0 = <&wsa_swr_active>;
+ pinctrl-names = "default";
+
qcom,din-ports = <2>;
qcom,dout-ports = <6>;
@@ -2302,17 +2496,20 @@
status = "disabled";
};
- swr2: soundwire-controller@33b0000 {
+ swr2: soundwire@33b0000 {
compatible = "qcom,soundwire-v1.7.0";
reg = <0 0x033b0000 0 0x2000>;
interrupts = <GIC_SPI 496 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 520 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "core", "wakeup";
- clocks = <&vamacro>;
+ clocks = <&txmacro>;
clock-names = "iface";
label = "TX";
+ pinctrl-0 = <&tx_swr_active>;
+ pinctrl-names = "default";
+
qcom,din-ports = <4>;
qcom,dout-ports = <0>;
qcom,ports-sinterval-low = /bits/ 8 <0x01 0x01 0x03 0x03>;
@@ -2339,8 +2536,6 @@
<&q6prmcc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
<&q6prmcc LPASS_CLK_ID_RX_CORE_MCLK2_2X_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>;
clock-names = "mclk", "macro", "dcodec", "npl";
- assigned-clocks = <&q6prmcc LPASS_CLK_ID_TX_CORE_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>;
- assigned-clock-rates = <19200000>;
#clock-cells = <0>;
clock-output-names = "fsgen";
@@ -4122,7 +4317,7 @@
"jedec,ufs-2.0";
reg = <0 0x01d84000 0 0x3000>;
interrupts = <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH>;
- phys = <&ufs_mem_phy_lanes>;
+ phys = <&ufs_mem_phy>;
phy-names = "ufsphy";
lanes-per-direction = <2>;
#reset-cells = <1>;
@@ -4171,10 +4366,8 @@
ufs_mem_phy: phy@1d87000 {
compatible = "qcom,sm8450-qmp-ufs-phy";
- reg = <0 0x01d87000 0 0x1c4>;
- #address-cells = <2>;
- #size-cells = <2>;
- ranges;
+ reg = <0 0x01d87000 0 0x1000>;
+
clock-names = "ref", "ref_aux", "qref";
clocks = <&rpmhcc RPMH_CXO_CLK>,
<&gcc GCC_UFS_PHY_PHY_AUX_CLK>,
@@ -4182,17 +4375,11 @@
resets = <&ufs_mem_hc 0>;
reset-names = "ufsphy";
- status = "disabled";
- ufs_mem_phy_lanes: phy@1d87400 {
- reg = <0 0x01d87400 0 0x188>,
- <0 0x01d87600 0 0x200>,
- <0 0x01d87c00 0 0x200>,
- <0 0x01d87800 0 0x188>,
- <0 0x01d87a00 0 0x200>;
- #clock-cells = <1>;
- #phy-cells = <0>;
- };
+ #clock-cells = <1>;
+ #phy-cells = <0>;
+
+ status = "disabled";
};
ice: crypto@1d88000 {
diff --git a/dts/upstream/src/arm64/qcom/sm8550-mtp.dts b/dts/upstream/src/arm64/qcom/sm8550-mtp.dts
index 9a70875..c1135ad 100644
--- a/dts/upstream/src/arm64/qcom/sm8550-mtp.dts
+++ b/dts/upstream/src/arm64/qcom/sm8550-mtp.dts
@@ -10,6 +10,7 @@
#include "pm8010.dtsi"
#include "pm8550.dtsi"
#include "pm8550b.dtsi"
+#define PMK8550VE_SID 5
#include "pm8550ve.dtsi"
#include "pm8550vs.dtsi"
#include "pmk8550.dtsi"
@@ -510,6 +511,134 @@
regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
};
};
+
+ regulators-6 {
+ compatible = "qcom,pm8010-rpmh-regulators";
+ qcom,pmic-id = "m";
+
+ vdd-l1-l2-supply = <&vreg_s4g_1p3>;
+ vdd-l3-l4-supply = <&vreg_bob2>;
+ vdd-l5-supply = <&vreg_s6g_1p8>;
+ vdd-l6-supply = <&vreg_s6g_1p8>;
+ vdd-l7-supply = <&vreg_bob1>;
+
+ vreg_l1m_1p056: ldo1 {
+ regulator-name = "vreg_l1m_1p056";
+ regulator-min-microvolt = <1056000>;
+ regulator-max-microvolt = <1056000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_l2m_1p056: ldo2 {
+ regulator-name = "vreg_l2m_1p056";
+ regulator-min-microvolt = <1056000>;
+ regulator-max-microvolt = <1056000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_l3m_2p8: ldo3 {
+ regulator-name = "vreg_l3m_2p8";
+ regulator-min-microvolt = <2800000>;
+ regulator-max-microvolt = <2800000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_l4m_2p8: ldo4 {
+ regulator-name = "vreg_l4m_2p8";
+ regulator-min-microvolt = <2800000>;
+ regulator-max-microvolt = <2800000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_l5m_1p8: ldo5 {
+ regulator-name = "vreg_l5m_1p8";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_l6m_1p8: ldo6 {
+ regulator-name = "vreg_l6m_1p8";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_l7m_2p9: ldo7 {
+ regulator-name = "vreg_l7m_2p9";
+ regulator-min-microvolt = <2800000>;
+ regulator-max-microvolt = <2904000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+ };
+
+ regulators-7 {
+ compatible = "qcom,pm8010-rpmh-regulators";
+ qcom,pmic-id = "n";
+
+ vdd-l1-l2-supply = <&vreg_s4g_1p3>;
+ vdd-l3-l4-supply = <&vreg_bob2>;
+ vdd-l5-supply = <&vreg_s6g_1p8>;
+ vdd-l6-supply = <&vreg_bob1>;
+ vdd-l7-supply = <&vreg_bob1>;
+
+ vreg_l1n_1p1: ldo1 {
+ regulator-name = "vreg_l1n_1p1";
+ regulator-min-microvolt = <1104000>;
+ regulator-max-microvolt = <1200000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_l2n_1p1: ldo2 {
+ regulator-name = "vreg_l2n_1p1";
+ regulator-min-microvolt = <1104000>;
+ regulator-max-microvolt = <1200000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_l3n_2p8: ldo3 {
+ regulator-name = "vreg_l3n_2p8";
+ regulator-min-microvolt = <2800000>;
+ regulator-max-microvolt = <3000000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_l4n_2p8: ldo4 {
+ regulator-name = "vreg_l4n_2p8";
+ regulator-min-microvolt = <2800000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_l5n_1p8: ldo5 {
+ regulator-name = "vreg_l5n_1p8";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_l6n_3p3: ldo6 {
+ regulator-name = "vreg_l6n_3p3";
+ regulator-min-microvolt = <2800000>;
+ regulator-max-microvolt = <3304000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_l7n_2p96: ldo7 {
+ regulator-name = "vreg_l7n_2p96";
+ regulator-min-microvolt = <2800000>;
+ regulator-max-microvolt = <2960000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+ };
+};
+
+&gpu {
+ status = "okay";
+
+ zap-shader {
+ firmware-name = "qcom/sm8550/a740_zap.mbn";
+ };
};
&i2c_master_hub_0 {
diff --git a/dts/upstream/src/arm64/qcom/sm8550-qrd.dts b/dts/upstream/src/arm64/qcom/sm8550-qrd.dts
index eef811d..d401d63 100644
--- a/dts/upstream/src/arm64/qcom/sm8550-qrd.dts
+++ b/dts/upstream/src/arm64/qcom/sm8550-qrd.dts
@@ -11,6 +11,7 @@
#include "pm8010.dtsi"
#include "pm8550.dtsi"
#include "pm8550b.dtsi"
+#define PMK8550VE_SID 5
#include "pm8550ve.dtsi"
#include "pm8550vs.dtsi"
#include "pmk8550.dtsi"
@@ -527,6 +528,126 @@
regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
};
};
+
+ regulators-6 {
+ compatible = "qcom,pm8010-rpmh-regulators";
+ qcom,pmic-id = "m";
+
+ vdd-l1-l2-supply = <&vreg_s4g_1p25>;
+ vdd-l3-l4-supply = <&vreg_bob2>;
+ vdd-l5-supply = <&vreg_s6g_1p86>;
+ vdd-l6-supply = <&vreg_s6g_1p86>;
+ vdd-l7-supply = <&vreg_bob1>;
+
+ vreg_l1m_1p056: ldo1 {
+ regulator-name = "vreg_l1m_1p056";
+ regulator-min-microvolt = <1056000>;
+ regulator-max-microvolt = <1056000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_l2m_1p056: ldo2 {
+ regulator-name = "vreg_l2m_1p056";
+ regulator-min-microvolt = <1056000>;
+ regulator-max-microvolt = <1056000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_l3m_2p8: ldo3 {
+ regulator-name = "vreg_l3m_2p8";
+ regulator-min-microvolt = <2800000>;
+ regulator-max-microvolt = <2800000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_l4m_2p8: ldo4 {
+ regulator-name = "vreg_l4m_2p8";
+ regulator-min-microvolt = <2800000>;
+ regulator-max-microvolt = <2800000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_l5m_1p8: ldo5 {
+ regulator-name = "vreg_l5m_1p8";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_l6m_1p8: ldo6 {
+ regulator-name = "vreg_l6m_1p8";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_l7m_2p9: ldo7 {
+ regulator-name = "vreg_l7m_2p9";
+ regulator-min-microvolt = <2800000>;
+ regulator-max-microvolt = <2904000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+ };
+
+ regulators-7 {
+ compatible = "qcom,pm8010-rpmh-regulators";
+ qcom,pmic-id = "n";
+
+ vdd-l1-l2-supply = <&vreg_s4g_1p25>;
+ vdd-l3-l4-supply = <&vreg_bob2>;
+ vdd-l5-supply = <&vreg_s6g_1p86>;
+ vdd-l6-supply = <&vreg_bob1>;
+ vdd-l7-supply = <&vreg_bob1>;
+
+ vreg_l1n_1p1: ldo1 {
+ regulator-name = "vreg_l1n_1p1";
+ regulator-min-microvolt = <1104000>;
+ regulator-max-microvolt = <1200000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_l2n_1p1: ldo2 {
+ regulator-name = "vreg_l2n_1p1";
+ regulator-min-microvolt = <1104000>;
+ regulator-max-microvolt = <1200000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_l3n_2p8: ldo3 {
+ regulator-name = "vreg_l3n_2p8";
+ regulator-min-microvolt = <2800000>;
+ regulator-max-microvolt = <3000000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_l4n_2p8: ldo4 {
+ regulator-name = "vreg_l4n_2p8";
+ regulator-min-microvolt = <2800000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_l5n_1p8: ldo5 {
+ regulator-name = "vreg_l5n_1p8";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_l6n_3p3: ldo6 {
+ regulator-name = "vreg_l6n_3p3";
+ regulator-min-microvolt = <2800000>;
+ regulator-max-microvolt = <3304000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_l7n_2p96: ldo7 {
+ regulator-name = "vreg_l7n_2p96";
+ regulator-min-microvolt = <2800000>;
+ regulator-max-microvolt = <2960000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+ };
};
&i2c_master_hub_0 {
@@ -585,6 +706,13 @@
};
};
+&ipa {
+ qcom,gsi-loader = "self";
+ memory-region = <&ipa_fw_mem>;
+ firmware-name = "qcom/sm8550/ipa_fws.mbn";
+ status = "okay";
+};
+
&gcc {
clocks = <&bi_tcxo_div2>, <&sleep_clk>,
<&pcie0_phy>,
@@ -596,6 +724,14 @@
<&usb_dp_qmpphy QMP_USB43DP_USB3_PIPE_CLK>;
};
+&gpu {
+ status = "okay";
+
+ zap-shader {
+ firmware-name = "qcom/sm8550/a740_zap.mbn";
+ };
+};
+
&lpass_tlmm {
spkr_1_sd_n_active: spkr-1-sd-n-active-state {
pins = "gpio17";
diff --git a/dts/upstream/src/arm64/qcom/sm8550.dtsi b/dts/upstream/src/arm64/qcom/sm8550.dtsi
index 7b9ddde..ee1ba5a 100644
--- a/dts/upstream/src/arm64/qcom/sm8550.dtsi
+++ b/dts/upstream/src/arm64/qcom/sm8550.dtsi
@@ -285,9 +285,9 @@
compatible = "arm,idle-state";
idle-state-name = "silver-rail-power-collapse";
arm,psci-suspend-param = <0x40000004>;
- entry-latency-us = <800>;
+ entry-latency-us = <550>;
exit-latency-us = <750>;
- min-residency-us = <4090>;
+ min-residency-us = <6700>;
local-timer-stop;
};
@@ -296,27 +296,37 @@
idle-state-name = "gold-rail-power-collapse";
arm,psci-suspend-param = <0x40000004>;
entry-latency-us = <600>;
- exit-latency-us = <1550>;
- min-residency-us = <4791>;
+ exit-latency-us = <1300>;
+ min-residency-us = <8136>;
local-timer-stop;
};
+
+ PRIME_CPU_SLEEP_0: cpu-sleep-2-0 {
+ compatible = "arm,idle-state";
+ idle-state-name = "goldplus-rail-power-collapse";
+ arm,psci-suspend-param = <0x40000004>;
+ entry-latency-us = <500>;
+ exit-latency-us = <1350>;
+ min-residency-us = <7480>;
+ local-timer-stop;
+ };
};
domain-idle-states {
CLUSTER_SLEEP_0: cluster-sleep-0 {
compatible = "domain-idle-state";
arm,psci-suspend-param = <0x41000044>;
- entry-latency-us = <1050>;
- exit-latency-us = <2500>;
- min-residency-us = <5309>;
+ entry-latency-us = <750>;
+ exit-latency-us = <2350>;
+ min-residency-us = <9144>;
};
CLUSTER_SLEEP_1: cluster-sleep-1 {
compatible = "domain-idle-state";
arm,psci-suspend-param = <0x4100c344>;
- entry-latency-us = <2700>;
- exit-latency-us = <3500>;
- min-residency-us = <13959>;
+ entry-latency-us = <2800>;
+ exit-latency-us = <4400>;
+ min-residency-us = <10150>;
};
};
};
@@ -324,6 +334,7 @@
firmware {
scm: scm {
compatible = "qcom,scm-sm8550", "qcom,scm";
+ qcom,dload-mode = <&tcsr 0x19000>;
interconnects = <&aggre2_noc MASTER_CRYPTO 0 &mc_virt SLAVE_EBI1 0>;
};
};
@@ -400,7 +411,7 @@
CPU_PD7: power-domain-cpu7 {
#power-domain-cells = <0>;
power-domains = <&CLUSTER_PD>;
- domain-idle-states = <&BIG_CPU_SLEEP_0>;
+ domain-idle-states = <&PRIME_CPU_SLEEP_0>;
};
CLUSTER_PD: power-domain-cluster {
@@ -1677,7 +1688,12 @@
qcom,bcm-voters = <&apps_bcm_voter>;
};
- pcie0: pci@1c00000 {
+ rng: rng@10c3000 {
+ compatible = "qcom,sm8550-trng", "qcom,trng";
+ reg = <0 0x010c3000 0 0x1000>;
+ };
+
+ pcie0: pcie@1c00000 {
device_type = "pci";
compatible = "qcom,pcie-sm8550";
reg = <0 0x01c00000 0 0x3000>,
@@ -1768,7 +1784,7 @@
status = "disabled";
};
- pcie1: pci@1c08000 {
+ pcie1: pcie@1c08000 {
device_type = "pci";
compatible = "qcom,pcie-sm8550";
reg = <0x0 0x01c08000 0x0 0x3000>,
@@ -1979,6 +1995,128 @@
#reset-cells = <1>;
};
+ gpu: gpu@3d00000 {
+ compatible = "qcom,adreno-43050a01", "qcom,adreno";
+ reg = <0x0 0x03d00000 0x0 0x40000>,
+ <0x0 0x03d9e000 0x0 0x1000>,
+ <0x0 0x03d61000 0x0 0x800>;
+ reg-names = "kgsl_3d0_reg_memory",
+ "cx_mem",
+ "cx_dbgc";
+
+ interrupts = <GIC_SPI 300 IRQ_TYPE_LEVEL_HIGH>;
+
+ iommus = <&adreno_smmu 0 0x0>,
+ <&adreno_smmu 1 0x0>;
+
+ operating-points-v2 = <&gpu_opp_table>;
+
+ qcom,gmu = <&gmu>;
+
+ status = "disabled";
+
+ zap-shader {
+ memory-region = <&gpu_micro_code_mem>;
+ };
+
+ /* Speedbin needs more work on A740+, keep only lower freqs */
+ gpu_opp_table: opp-table {
+ compatible = "operating-points-v2";
+
+ opp-680000000 {
+ opp-hz = /bits/ 64 <680000000>;
+ opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>;
+ };
+
+ opp-615000000 {
+ opp-hz = /bits/ 64 <615000000>;
+ opp-level = <RPMH_REGULATOR_LEVEL_SVS_L0>;
+ };
+
+ opp-550000000 {
+ opp-hz = /bits/ 64 <550000000>;
+ opp-level = <RPMH_REGULATOR_LEVEL_SVS>;
+ };
+
+ opp-475000000 {
+ opp-hz = /bits/ 64 <475000000>;
+ opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS_L1>;
+ };
+
+ opp-401000000 {
+ opp-hz = /bits/ 64 <401000000>;
+ opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>;
+ };
+
+ opp-348000000 {
+ opp-hz = /bits/ 64 <348000000>;
+ opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS_D0>;
+ };
+
+ opp-295000000 {
+ opp-hz = /bits/ 64 <295000000>;
+ opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS_D1>;
+ };
+
+ opp-220000000 {
+ opp-hz = /bits/ 64 <220000000>;
+ opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS_D2>;
+ };
+ };
+ };
+
+ gmu: gmu@3d6a000 {
+ compatible = "qcom,adreno-gmu-740.1", "qcom,adreno-gmu";
+ reg = <0x0 0x03d6a000 0x0 0x35000>,
+ <0x0 0x03d50000 0x0 0x10000>,
+ <0x0 0x0b280000 0x0 0x10000>;
+ reg-names = "gmu", "rscc", "gmu_pdc";
+
+ interrupts = <GIC_SPI 304 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 305 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "hfi", "gmu";
+
+ clocks = <&gpucc GPU_CC_AHB_CLK>,
+ <&gpucc GPU_CC_CX_GMU_CLK>,
+ <&gpucc GPU_CC_CXO_CLK>,
+ <&gcc GCC_DDRSS_GPU_AXI_CLK>,
+ <&gcc GCC_GPU_MEMNOC_GFX_CLK>,
+ <&gpucc GPU_CC_HUB_CX_INT_CLK>,
+ <&gpucc GPU_CC_DEMET_CLK>;
+ clock-names = "ahb",
+ "gmu",
+ "cxo",
+ "axi",
+ "memnoc",
+ "hub",
+ "demet";
+
+ power-domains = <&gpucc GPU_CC_CX_GDSC>,
+ <&gpucc GPU_CC_GX_GDSC>;
+ power-domain-names = "cx",
+ "gx";
+
+ iommus = <&adreno_smmu 5 0x0>;
+
+ qcom,qmp = <&aoss_qmp>;
+
+ operating-points-v2 = <&gmu_opp_table>;
+
+ gmu_opp_table: opp-table {
+ compatible = "operating-points-v2";
+
+ opp-500000000 {
+ opp-hz = /bits/ 64 <500000000>;
+ opp-level = <RPMH_REGULATOR_LEVEL_SVS>;
+ };
+
+ opp-200000000 {
+ opp-hz = /bits/ 64 <200000000>;
+ opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>;
+ };
+ };
+ };
+
gpucc: clock-controller@3d90000 {
compatible = "qcom,sm8550-gpucc";
reg = <0 0x03d90000 0 0xa000>;
@@ -1990,6 +2128,89 @@
#power-domain-cells = <1>;
};
+ adreno_smmu: iommu@3da0000 {
+ compatible = "qcom,sm8550-smmu-500", "qcom,adreno-smmu",
+ "qcom,smmu-500", "arm,mmu-500";
+ reg = <0x0 0x03da0000 0x0 0x40000>;
+ #iommu-cells = <2>;
+ #global-interrupts = <1>;
+ interrupts = <GIC_SPI 673 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 677 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 678 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 679 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 680 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 681 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 682 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 683 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 684 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 685 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 686 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 687 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 422 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 476 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 574 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 575 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 576 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 577 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 659 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 661 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 664 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 665 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 666 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 668 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 669 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 699 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&gpucc GPU_CC_HLOS1_VOTE_GPU_SMMU_CLK>,
+ <&gcc GCC_GPU_MEMNOC_GFX_CLK>,
+ <&gcc GCC_GPU_SNOC_DVM_GFX_CLK>,
+ <&gpucc GPU_CC_AHB_CLK>;
+ clock-names = "hlos",
+ "bus",
+ "iface",
+ "ahb";
+ power-domains = <&gpucc GPU_CC_CX_GDSC>;
+ dma-coherent;
+ };
+
+ ipa: ipa@3f40000 {
+ compatible = "qcom,sm8550-ipa";
+
+ iommus = <&apps_smmu 0x4a0 0x0>,
+ <&apps_smmu 0x4a2 0x0>;
+ reg = <0 0x3f40000 0 0x10000>,
+ <0 0x3f50000 0 0x5000>,
+ <0 0x3e04000 0 0xfc000>;
+ reg-names = "ipa-reg",
+ "ipa-shared",
+ "gsi";
+
+ interrupts-extended = <&intc GIC_SPI 654 IRQ_TYPE_EDGE_RISING>,
+ <&intc GIC_SPI 432 IRQ_TYPE_LEVEL_HIGH>,
+ <&ipa_smp2p_in 0 IRQ_TYPE_EDGE_RISING>,
+ <&ipa_smp2p_in 1 IRQ_TYPE_EDGE_RISING>;
+ interrupt-names = "ipa",
+ "gsi",
+ "ipa-clock-query",
+ "ipa-setup-ready";
+
+ clocks = <&rpmhcc RPMH_IPA_CLK>;
+ clock-names = "core";
+
+ interconnects = <&aggre2_noc MASTER_IPA 0 &mc_virt SLAVE_EBI1 0>,
+ <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_IPA_CFG 0>;
+ interconnect-names = "memory",
+ "config";
+
+ qcom,qmp = <&aoss_qmp>;
+
+ qcom,smem-states = <&ipa_smp2p_out 0>,
+ <&ipa_smp2p_out 1>;
+ qcom,smem-state-names = "ipa-clock-enabled-valid",
+ "ipa-clock-enabled";
+
+ status = "disabled";
+ };
+
remoteproc_mpss: remoteproc@4080000 {
compatible = "qcom,sm8550-mpss-pas";
reg = <0x0 0x04080000 0x0 0x4040>;
@@ -2040,17 +2261,13 @@
<&q6prmcc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
<&lpass_vamacro>;
clock-names = "mclk", "macro", "dcodec", "fsgen";
- assigned-clocks = <&q6prmcc LPASS_CLK_ID_WSA2_CORE_TX_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>;
- assigned-clock-rates = <19200000>;
#clock-cells = <0>;
clock-output-names = "wsa2-mclk";
- pinctrl-names = "default";
- pinctrl-0 = <&wsa2_swr_active>;
#sound-dai-cells = <1>;
};
- swr3: soundwire-controller@6ab0000 {
+ swr3: soundwire@6ab0000 {
compatible = "qcom,soundwire-v2.0.0";
reg = <0 0x06ab0000 0 0x10000>;
interrupts = <GIC_SPI 171 IRQ_TYPE_LEVEL_HIGH>;
@@ -2058,6 +2275,9 @@
clock-names = "iface";
label = "WSA2";
+ pinctrl-0 = <&wsa2_swr_active>;
+ pinctrl-names = "default";
+
qcom,din-ports = <4>;
qcom,dout-ports = <9>;
@@ -2086,17 +2306,12 @@
<&lpass_vamacro>;
clock-names = "mclk", "macro", "dcodec", "fsgen";
- assigned-clocks = <&q6prmcc LPASS_CLK_ID_RX_CORE_TX_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>;
- assigned-clock-rates = <19200000>;
-
#clock-cells = <0>;
clock-output-names = "mclk";
- pinctrl-names = "default";
- pinctrl-0 = <&rx_swr_active>;
#sound-dai-cells = <1>;
};
- swr1: soundwire-controller@6ad0000 {
+ swr1: soundwire@6ad0000 {
compatible = "qcom,soundwire-v2.0.0";
reg = <0 0x06ad0000 0 0x10000>;
interrupts = <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>;
@@ -2104,18 +2319,21 @@
clock-names = "iface";
label = "RX";
+ pinctrl-0 = <&rx_swr_active>;
+ pinctrl-names = "default";
+
- qcom,din-ports = <0>;
- qcom,dout-ports = <10>;
+ qcom,din-ports = <1>;
+ qcom,dout-ports = <11>;
- qcom,ports-sinterval = /bits/ 16 <0x03 0x3f 0x1f 0x07 0x00 0x18f 0xff 0xff 0xff 0xff>;
- qcom,ports-offset1 = /bits/ 8 <0x00 0x00 0x0b 0x01 0x00 0x00 0xff 0xff 0xff 0xff>;
- qcom,ports-offset2 = /bits/ 8 <0x00 0x00 0x0b 0x00 0x00 0x00 0xff 0xff 0xff 0xff>;
- qcom,ports-hstart = /bits/ 8 <0xff 0x03 0xff 0xff 0xff 0x08 0xff 0xff 0xff 0xff>;
- qcom,ports-hstop = /bits/ 8 <0xff 0x06 0xff 0xff 0xff 0x08 0xff 0xff 0xff 0xff>;
- qcom,ports-word-length = /bits/ 8 <0x01 0x07 0x04 0xff 0xff 0x0f 0xff 0xff 0xff 0xff>;
- qcom,ports-block-pack-mode = /bits/ 8 <0xff 0x00 0x01 0xff 0xff 0x00 0xff 0xff 0xff 0xff>;
- qcom,ports-block-group-count = /bits/ 8 <0xff 0xff 0xff 0xff 0x00 0x00 0xff 0xff 0xff 0xff>;
- qcom,ports-lane-control = /bits/ 8 <0x01 0x00 0x00 0x00 0x00 0x00 0xff 0xff 0xff 0xff>;
+ qcom,ports-sinterval = /bits/ 16 <0x03 0x3f 0x1f 0x07 0x00 0x18f 0xff 0xff 0xff 0xff 0xff 0xff>;
+ qcom,ports-offset1 = /bits/ 8 <0x00 0x00 0x0b 0x01 0x00 0x00 0xff 0xff 0xff 0xff 0xff 0xff>;
+ qcom,ports-offset2 = /bits/ 8 <0x00 0x00 0x0b 0x00 0x00 0x00 0xff 0xff 0xff 0xff 0xff 0xff>;
+ qcom,ports-hstart = /bits/ 8 <0xff 0x03 0xff 0xff 0xff 0x08 0xff 0xff 0xff 0xff 0xff 0xff>;
+ qcom,ports-hstop = /bits/ 8 <0xff 0x06 0xff 0xff 0xff 0x08 0xff 0xff 0xff 0xff 0xff 0xff>;
+ qcom,ports-word-length = /bits/ 8 <0x01 0x07 0x04 0xff 0xff 0x0f 0xff 0xff 0xff 0xff 0xff 0xff>;
+ qcom,ports-block-pack-mode = /bits/ 8 <0xff 0x00 0x01 0xff 0xff 0x00 0xff 0xff 0xff 0xff 0xff 0xff>;
+ qcom,ports-block-group-count = /bits/ 8 <0xff 0xff 0xff 0xff 0x00 0x00 0xff 0xff 0xff 0xff 0xff 0xff>;
+ qcom,ports-lane-control = /bits/ 8 <0x01 0x00 0x00 0x00 0x00 0x00 0xff 0xff 0xff 0xff 0xff 0xff>;
#address-cells = <2>;
#size-cells = <0>;
@@ -2131,14 +2349,9 @@
<&q6prmcc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
<&lpass_vamacro>;
clock-names = "mclk", "macro", "dcodec", "fsgen";
- assigned-clocks = <&q6prmcc LPASS_CLK_ID_TX_CORE_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>;
-
- assigned-clock-rates = <19200000>;
#clock-cells = <0>;
clock-output-names = "mclk";
- pinctrl-names = "default";
- pinctrl-0 = <&tx_swr_active>;
#sound-dai-cells = <1>;
};
@@ -2151,17 +2364,12 @@
<&lpass_vamacro>;
clock-names = "mclk", "macro", "dcodec", "fsgen";
- assigned-clocks = <&q6prmcc LPASS_CLK_ID_WSA_CORE_TX_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>;
- assigned-clock-rates = <19200000>;
-
#clock-cells = <0>;
clock-output-names = "mclk";
- pinctrl-names = "default";
- pinctrl-0 = <&wsa_swr_active>;
#sound-dai-cells = <1>;
};
- swr0: soundwire-controller@6b10000 {
+ swr0: soundwire@6b10000 {
compatible = "qcom,soundwire-v2.0.0";
reg = <0 0x06b10000 0 0x10000>;
interrupts = <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>;
@@ -2169,6 +2377,9 @@
clock-names = "iface";
label = "WSA";
+ pinctrl-0 = <&wsa_swr_active>;
+ pinctrl-names = "default";
+
qcom,din-ports = <4>;
qcom,dout-ports = <9>;
@@ -2188,16 +2399,19 @@
status = "disabled";
};
- swr2: soundwire-controller@6d30000 {
+ swr2: soundwire@6d30000 {
compatible = "qcom,soundwire-v2.0.0";
reg = <0 0x06d30000 0 0x10000>;
interrupts = <GIC_SPI 496 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 520 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "core", "wakeup";
- clocks = <&lpass_vamacro>;
+ clocks = <&lpass_txmacro>;
clock-names = "iface";
label = "TX";
+ pinctrl-0 = <&tx_swr_active>;
+ pinctrl-names = "default";
+
qcom,din-ports = <4>;
qcom,dout-ports = <0>;
qcom,ports-sinterval-low = /bits/ 8 <0x01 0x01 0x03 0x03>;
@@ -2224,9 +2438,6 @@
<&q6prmcc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>;
clock-names = "mclk", "macro", "dcodec";
- assigned-clocks = <&q6prmcc LPASS_CLK_ID_TX_CORE_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>;
- assigned-clock-rates = <19200000>;
-
#clock-cells = <0>;
clock-output-names = "fsgen";
#sound-dai-cells = <1>;
@@ -2923,8 +3134,8 @@
interrupts-extended = <&intc GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>,
<&pdc 17 IRQ_TYPE_LEVEL_HIGH>,
- <&pdc 15 IRQ_TYPE_EDGE_RISING>,
- <&pdc 14 IRQ_TYPE_EDGE_RISING>;
+ <&pdc 15 IRQ_TYPE_EDGE_BOTH>,
+ <&pdc 14 IRQ_TYPE_EDGE_BOTH>;
interrupt-names = "hs_phy_irq",
"ss_phy_irq",
"dm_hs_phy_irq",
diff --git a/dts/upstream/src/arm64/qcom/sm8650-mtp.dts b/dts/upstream/src/arm64/qcom/sm8650-mtp.dts
new file mode 100644
index 0000000..be133a3
--- /dev/null
+++ b/dts/upstream/src/arm64/qcom/sm8650-mtp.dts
@@ -0,0 +1,727 @@
+// SPDX-License-Identifier: BSD-3-Clause
+/*
+ * Copyright (c) 2023, Linaro Limited
+ */
+
+/dts-v1/;
+
+#include <dt-bindings/regulator/qcom,rpmh-regulator.h>
+#include "sm8650.dtsi"
+#include "pm8010.dtsi"
+#include "pm8550.dtsi"
+#include "pm8550b.dtsi"
+#define PMK8550VE_SID 8
+#include "pm8550ve.dtsi"
+#include "pm8550vs.dtsi"
+#include "pmk8550.dtsi"
+#include "pmr735d_a.dtsi"
+
+/ {
+ model = "Qualcomm Technologies, Inc. SM8650 MTP";
+ compatible = "qcom,sm8650-mtp", "qcom,sm8650";
+
+ aliases {
+ serial0 = &uart15;
+ };
+
+ chosen {
+ stdout-path = "serial0:115200n8";
+ };
+
+ pmic-glink {
+ compatible = "qcom,sm8650-pmic-glink",
+ "qcom,sm8550-pmic-glink",
+ "qcom,pmic-glink";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ orientation-gpios = <&tlmm 29 GPIO_ACTIVE_HIGH>;
+
+ connector@0 {
+ compatible = "usb-c-connector";
+ reg = <0>;
+
+ power-role = "dual";
+ data-role = "dual";
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+
+ pmic_glink_hs_in: endpoint {
+ remote-endpoint = <&usb_1_dwc3_hs>;
+ };
+ };
+
+ port@1 {
+ reg = <1>;
+
+ pmic_glink_ss_in: endpoint {
+ remote-endpoint = <&usb_1_dwc3_ss>;
+ };
+ };
+ };
+ };
+ };
+
+ vph_pwr: vph-pwr-regulator {
+ compatible = "regulator-fixed";
+
+ regulator-name = "vph_pwr";
+ regulator-min-microvolt = <3700000>;
+ regulator-max-microvolt = <3700000>;
+
+ regulator-always-on;
+ regulator-boot-on;
+ };
+};
+
+&apps_rsc {
+ regulators-0 {
+ compatible = "qcom,pm8550-rpmh-regulators";
+
+ vdd-bob1-supply = <&vph_pwr>;
+ vdd-bob2-supply = <&vph_pwr>;
+ vdd-l2-l13-l14-supply = <&vreg_bob1>;
+ vdd-l3-supply = <&vreg_s1c_1p2>;
+ vdd-l5-l16-supply = <&vreg_bob1>;
+ vdd-l6-l7-supply = <&vreg_bob1>;
+ vdd-l8-l9-supply = <&vreg_bob1>;
+ vdd-l11-supply = <&vreg_s1c_1p2>;
+ vdd-l12-supply = <&vreg_s6c_1p8>;
+ vdd-l15-supply = <&vreg_s6c_1p8>;
+ vdd-l17-supply = <&vreg_bob2>;
+
+ qcom,pmic-id = "b";
+
+ vreg_bob1: bob1 {
+ regulator-name = "vreg_bob1";
+ regulator-min-microvolt = <3296000>;
+ regulator-max-microvolt = <3960000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_bob2: bob2 {
+ regulator-name = "vreg_bob2";
+ regulator-min-microvolt = <2720000>;
+ regulator-max-microvolt = <3008000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_l2b_3p0: ldo2 {
+ regulator-name = "vreg_l2b_3p0";
+ regulator-min-microvolt = <3008000>;
+ regulator-max-microvolt = <3008000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ regulator-allow-set-load;
+ regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM
+ RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_l5b_3p1: ldo5 {
+ regulator-name = "vreg_l5b_3p1";
+ regulator-min-microvolt = <3104000>;
+ regulator-max-microvolt = <3104000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ regulator-allow-set-load;
+ regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM
+ RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_l6b_1p8: ldo6 {
+ regulator-name = "vreg_l6b_1p8";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <3008000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ regulator-allow-set-load;
+ regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM
+ RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_l7b_1p8: ldo7 {
+ regulator-name = "vreg_l7b_1p8";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <3008000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_l8b_1p8: ldo8 {
+ regulator-name = "vreg_l8b_1p8";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <3008000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ regulator-allow-set-load;
+ regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM
+ RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_l9b_2p9: ldo9 {
+ regulator-name = "vreg_l9b_2p9";
+ regulator-min-microvolt = <2960000>;
+ regulator-max-microvolt = <3008000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ regulator-allow-set-load;
+ regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM
+ RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_l11b_1p2: ldo11 {
+ regulator-name = "vreg_l11b_1p2";
+ regulator-min-microvolt = <1200000>;
+ regulator-max-microvolt = <1504000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ regulator-allow-set-load;
+ regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM
+ RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_l12b_1p8: ldo12 {
+ regulator-name = "vreg_l12b_1p8";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ regulator-allow-set-load;
+ regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM
+ RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_l13b_3p0: ldo13 {
+ regulator-name = "vreg_l13b_3p0";
+ regulator-min-microvolt = <3000000>;
+ regulator-max-microvolt = <3000000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ regulator-allow-set-load;
+ regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM
+ RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_l14b_3p2: ldo14 {
+ regulator-name = "vreg_l14b_3p2";
+ regulator-min-microvolt = <3200000>;
+ regulator-max-microvolt = <3200000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ regulator-allow-set-load;
+ regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM
+ RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_l15b_1p8: ldo15 {
+ regulator-name = "vreg_l15b_1p8";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ regulator-allow-set-load;
+ regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM
+ RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_l16b_2p8: ldo16 {
+ regulator-name = "vreg_l16b_2p8";
+ regulator-min-microvolt = <2800000>;
+ regulator-max-microvolt = <2800000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ regulator-allow-set-load;
+ regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM
+ RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_l17b_2p5: ldo17 {
+ regulator-name = "vreg_l17b_2p5";
+ regulator-min-microvolt = <2504000>;
+ regulator-max-microvolt = <2504000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ regulator-allow-set-load;
+ regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM
+ RPMH_REGULATOR_MODE_HPM>;
+ };
+ };
+
+ regulators-1 {
+ compatible = "qcom,pm8550vs-rpmh-regulators";
+
+ vdd-l1-supply = <&vreg_s1c_1p2>;
+ vdd-l2-supply = <&vreg_s1c_1p2>;
+ vdd-l3-supply = <&vreg_s1c_1p2>;
+ vdd-s1-supply = <&vph_pwr>;
+ vdd-s2-supply = <&vph_pwr>;
+ vdd-s3-supply = <&vph_pwr>;
+ vdd-s4-supply = <&vph_pwr>;
+ vdd-s5-supply = <&vph_pwr>;
+ vdd-s6-supply = <&vph_pwr>;
+
+ qcom,pmic-id = "c";
+
+ vreg_s1c_1p2: smps1 {
+ regulator-name = "vreg_s1c_1p2";
+ regulator-min-microvolt = <1256000>;
+ regulator-max-microvolt = <1348000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_s2c_0p8: smps2 {
+ regulator-name = "vreg_s2c_0p8";
+ regulator-min-microvolt = <852000>;
+ regulator-max-microvolt = <1036000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_s3c_0p9: smps3 {
+ regulator-name = "vreg_s3c_0p9";
+ regulator-min-microvolt = <976000>;
+ regulator-max-microvolt = <1064000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_s4c_1p2: smps4 {
+ regulator-name = "vreg_s4c_1p2";
+ regulator-min-microvolt = <1224000>;
+ regulator-max-microvolt = <1280000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_s5c_0p7: smps5 {
+ regulator-name = "vreg_s5c_0p7";
+ regulator-min-microvolt = <752000>;
+ regulator-max-microvolt = <900000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_s6c_1p8: smps6 {
+ regulator-name = "vreg_s6c_1p8";
+ regulator-min-microvolt = <1856000>;
+ regulator-max-microvolt = <2000000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_l1c_1p2: ldo1 {
+ regulator-name = "vreg_l1c_1p2";
+ regulator-min-microvolt = <1200000>;
+ regulator-max-microvolt = <1200000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ regulator-allow-set-load;
+ regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM
+ RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_l3c_1p2: ldo3 {
+ regulator-name = "vreg_l3c_1p2";
+ regulator-min-microvolt = <1200000>;
+ regulator-max-microvolt = <1200000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ regulator-allow-set-load;
+ regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM
+ RPMH_REGULATOR_MODE_HPM>;
+ };
+ };
+
+ regulators-2 {
+ compatible = "qcom,pm8550vs-rpmh-regulators";
+
+ vdd-l1-supply = <&vreg_s3c_0p9>;
+
+ qcom,pmic-id = "d";
+
+ vreg_l1d_0p88: ldo1 {
+ regulator-name = "vreg_l1d_0p88";
+ regulator-min-microvolt = <912000>;
+ regulator-max-microvolt = <920000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ regulator-allow-set-load;
+ regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM
+ RPMH_REGULATOR_MODE_HPM>;
+ };
+ };
+
+ regulators-3 {
+ compatible = "qcom,pm8550vs-rpmh-regulators";
+
+ vdd-l3-supply = <&vreg_s3c_0p9>;
+
+ qcom,pmic-id = "e";
+
+ vreg_l3e_0p9: ldo3 {
+ regulator-name = "vreg_l3e_0p9";
+ regulator-min-microvolt = <880000>;
+ regulator-max-microvolt = <920000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ regulator-allow-set-load;
+ regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM
+ RPMH_REGULATOR_MODE_HPM>;
+ };
+ };
+
+ regulators-4 {
+ compatible = "qcom,pm8550vs-rpmh-regulators";
+
+ vdd-l1-supply = <&vreg_s3c_0p9>;
+ vdd-l3-supply = <&vreg_s3c_0p9>;
+
+ qcom,pmic-id = "g";
+
+ vreg_l1g_0p91: ldo1 {
+ regulator-name = "vreg_l1g_0p91";
+ regulator-min-microvolt = <912000>;
+ regulator-max-microvolt = <920000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ regulator-allow-set-load;
+ regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM
+ RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_l3g_0p91: ldo3 {
+ regulator-name = "vreg_l3g_0p91";
+ regulator-min-microvolt = <880000>;
+ regulator-max-microvolt = <912000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ regulator-allow-set-load;
+ regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM
+ RPMH_REGULATOR_MODE_HPM>;
+ };
+ };
+
+ regulators-5 {
+ compatible = "qcom,pm8550ve-rpmh-regulators";
+
+ vdd-l1-supply = <&vreg_s3c_0p9>;
+ vdd-l2-supply = <&vreg_s3c_0p9>;
+ vdd-l3-supply = <&vreg_s1c_1p2>;
+ vdd-s4-supply = <&vph_pwr>;
+
+ qcom,pmic-id = "i";
+
+ vreg_s4i_0p85: smps4 {
+ regulator-name = "vreg_s4i_0p85";
+ regulator-min-microvolt = <852000>;
+ regulator-max-microvolt = <1004000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_l1i_0p88: ldo1 {
+ regulator-name = "vreg_l1i_0p88";
+ regulator-min-microvolt = <880000>;
+ regulator-max-microvolt = <912000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ regulator-allow-set-load;
+ regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM
+ RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_l2i_0p88: ldo2 {
+ regulator-name = "vreg_l2i_0p88";
+ regulator-min-microvolt = <880000>;
+ regulator-max-microvolt = <912000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ regulator-allow-set-load;
+ regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM
+ RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_l3i_1p2: ldo3 {
+ regulator-name = "vreg_l3i_0p91";
+ regulator-min-microvolt = <1200000>;
+ regulator-max-microvolt = <1200000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ regulator-allow-set-load;
+ regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM
+ RPMH_REGULATOR_MODE_HPM>;
+ };
+ };
+};
+
+&dispcc {
+ status = "okay";
+};
+
+&lpass_tlmm {
+ spkr_1_sd_n_active: spkr-1-sd-n-active-state {
+ pins = "gpio21";
+ function = "gpio";
+ drive-strength = <16>;
+ bias-disable;
+ output-low;
+ };
+};
+
+&mdss {
+ status = "okay";
+};
+
+&mdss_dsi0 {
+ vdda-supply = <&vreg_l3i_1p2>;
+
+ status = "okay";
+
+ panel@0 {
+ compatible = "visionox,vtdr6130";
+ reg = <0>;
+
+ reset-gpios = <&tlmm 133 GPIO_ACTIVE_LOW>;
+
+ vddio-supply = <&vreg_l12b_1p8>;
+ vci-supply = <&vreg_l13b_3p0>;
+ vdd-supply = <&vreg_l11b_1p2>;
+
+ pinctrl-0 = <&disp0_reset_n_active>, <&mdp_vsync_active>;
+ pinctrl-1 = <&disp0_reset_n_suspend>, <&mdp_vsync_suspend>;
+ pinctrl-names = "default", "sleep";
+
+ port {
+ panel0_in: endpoint {
+ remote-endpoint = <&mdss_dsi0_out>;
+ };
+ };
+ };
+};
+
+&mdss_dsi0_out {
+ remote-endpoint = <&panel0_in>;
+ data-lanes = <0 1 2 3>;
+};
+
+&mdss_dsi0_phy {
+ vdds-supply = <&vreg_l1i_0p88>;
+
+ status = "okay";
+};
+
+&mdss_mdp {
+ status = "okay";
+};
+
+&pcie_1_phy_aux_clk {
+ clock-frequency = <1000>;
+};
+
+&pcie0 {
+ wake-gpios = <&tlmm 96 GPIO_ACTIVE_HIGH>;
+ perst-gpios = <&tlmm 94 GPIO_ACTIVE_LOW>;
+
+ pinctrl-0 = <&pcie0_default_state>;
+ pinctrl-names = "default";
+
+ status = "okay";
+};
+
+&pcie0_phy {
+ vdda-phy-supply = <&vreg_l1i_0p88>;
+ vdda-pll-supply = <&vreg_l3i_1p2>;
+
+ status = "okay";
+};
+
+&pcie1 {
+ wake-gpios = <&tlmm 99 GPIO_ACTIVE_HIGH>;
+ perst-gpios = <&tlmm 97 GPIO_ACTIVE_LOW>;
+
+ pinctrl-0 = <&pcie1_default_state>;
+ pinctrl-names = "default";
+
+ status = "okay";
+};
+
+&pcie1_phy {
+ vdda-phy-supply = <&vreg_l3e_0p9>;
+ vdda-pll-supply = <&vreg_l3i_1p2>;
+ vdda-qref-supply = <&vreg_l1i_0p88>;
+
+ status = "okay";
+};
+
+&pm8550_gpios {
+ sdc2_card_det_n: sdc2-card-det-state {
+ pins = "gpio12";
+ function = "normal";
+ bias-pull-up;
+ input-enable;
+ output-disable;
+ power-source = <1>; /* 1.8 V */
+ };
+};
+
+&pm8550b_eusb2_repeater {
+ vdd18-supply = <&vreg_l15b_1p8>;
+ vdd3-supply = <&vreg_l5b_3p1>;
+};
+
+&qupv3_id_1 {
+ status = "okay";
+};
+
+&remoteproc_adsp {
+ firmware-name = "qcom/sm8650/adsp.mbn",
+ "qcom/sm8650/adsp_dtb.mbn";
+
+ status = "okay";
+};
+
+&remoteproc_cdsp {
+ firmware-name = "qcom/sm8650/cdsp.mbn",
+ "qcom/sm8650/cdsp_dtb.mbn";
+
+ status = "okay";
+};
+
+&remoteproc_mpss {
+ firmware-name = "qcom/sm8650/modem.mbn",
+ "qcom/sm8650/modem_dtb.mbn";
+
+ status = "okay";
+};
+
+&sdhc_2 {
+ cd-gpios = <&pm8550_gpios 12 GPIO_ACTIVE_LOW>;
+
+ vmmc-supply = <&vreg_l9b_2p9>;
+ vqmmc-supply = <&vreg_l8b_1p8>;
+ bus-width = <4>;
+ no-sdio;
+ no-mmc;
+
+ pinctrl-0 = <&sdc2_default>, <&sdc2_card_det_n>;
+ pinctrl-1 = <&sdc2_sleep>, <&sdc2_card_det_n>;
+ pinctrl-names = "default", "sleep";
+
+ status = "okay";
+};
+
+&sleep_clk {
+ clock-frequency = <32000>;
+};
+
+&swr0 {
+ status = "okay";
+
+ /* WSA8845, Speaker Left */
+ left_spkr: speaker@0,0 {
+ compatible = "sdw20217020400";
+ reg = <0 0>;
+ pinctrl-0 = <&spkr_1_sd_n_active>;
+ pinctrl-names = "default";
+ powerdown-gpios = <&lpass_tlmm 21 GPIO_ACTIVE_LOW>;
+ #sound-dai-cells = <0>;
+ sound-name-prefix = "SpkrLeft";
+ vdd-1p8-supply = <&vreg_l15b_1p8>;
+ vdd-io-supply = <&vreg_l3c_1p2>;
+ };
+
+ /* WSA8845, Speaker Right */
+ right_spkr: speaker@0,1 {
+ compatible = "sdw20217020400";
+ reg = <0 1>;
+ pinctrl-0 = <&spkr_2_sd_n_active>;
+ pinctrl-names = "default";
+ powerdown-gpios = <&tlmm 77 GPIO_ACTIVE_LOW>;
+ #sound-dai-cells = <0>;
+ sound-name-prefix = "SpkrRight";
+ vdd-1p8-supply = <&vreg_l15b_1p8>;
+ vdd-io-supply = <&vreg_l3c_1p2>;
+ };
+};
+
+&tlmm {
+ /* Reserved I/Os for NFC */
+ gpio-reserved-ranges = <32 8>, <74 1>;
+
+ disp0_reset_n_active: disp0-reset-n-active-state {
+ pins = "gpio133";
+ function = "gpio";
+ drive-strength = <8>;
+ bias-disable;
+ };
+
+ disp0_reset_n_suspend: disp0-reset-n-suspend-state {
+ pins = "gpio133";
+ function = "gpio";
+ drive-strength = <2>;
+ bias-pull-down;
+ };
+
+ mdp_vsync_active: mdp-vsync-active-state {
+ pins = "gpio86";
+ function = "mdp_vsync";
+ drive-strength = <2>;
+ bias-pull-down;
+ };
+
+ mdp_vsync_suspend: mdp-vsync-suspend-state {
+ pins = "gpio86";
+ function = "mdp_vsync";
+ drive-strength = <2>;
+ bias-pull-down;
+ };
+
+ spkr_2_sd_n_active: spkr-2-sd-n-active-state {
+ pins = "gpio77";
+ function = "gpio";
+ drive-strength = <16>;
+ bias-disable;
+ output-low;
+ };
+};
+
+&uart15 {
+ status = "okay";
+};
+
+&ufs_mem_hc {
+ reset-gpios = <&tlmm 210 GPIO_ACTIVE_LOW>;
+
+ vcc-supply = <&vreg_l17b_2p5>;
+ vcc-max-microamp = <1300000>;
+ vccq-supply = <&vreg_l1c_1p2>;
+ vccq-max-microamp = <1200000>;
+
+ status = "okay";
+};
+
+&ufs_mem_phy {
+ vdda-phy-supply = <&vreg_l1d_0p88>;
+ vdda-pll-supply = <&vreg_l3i_1p2>;
+
+ status = "okay";
+};
+
+/*
+ * DPAUX -> WCD9395 -> USB_SBU -> USB-C
+ * eUSB2 DP/DM -> PM85550HS -> eUSB2 DP/DM -> USB-C
+ * USB SS -> USB-C
+ */
+
+&usb_1 {
+ status = "okay";
+};
+
+&usb_1_dwc3 {
+ dr_mode = "otg";
+ usb-role-switch;
+};
+
+&usb_1_dwc3_hs {
+ remote-endpoint = <&pmic_glink_hs_in>;
+};
+
+&usb_1_dwc3_ss {
+ remote-endpoint = <&pmic_glink_ss_in>;
+};
+
+&usb_1_hsphy {
+ vdd-supply = <&vreg_l1i_0p88>;
+ vdda12-supply = <&vreg_l3i_1p2>;
+
+ phys = <&pm8550b_eusb2_repeater>;
+
+ status = "okay";
+};
+
+&usb_dp_qmpphy {
+ vdda-phy-supply = <&vreg_l3i_1p2>;
+ vdda-pll-supply = <&vreg_l3g_0p91>;
+
+ status = "okay";
+};
+
+&xo_board {
+ clock-frequency = <76800000>;
+};
diff --git a/dts/upstream/src/arm64/qcom/sm8650-qrd.dts b/dts/upstream/src/arm64/qcom/sm8650-qrd.dts
new file mode 100644
index 0000000..b9151c2
--- /dev/null
+++ b/dts/upstream/src/arm64/qcom/sm8650-qrd.dts
@@ -0,0 +1,811 @@
+// SPDX-License-Identifier: BSD-3-Clause
+/*
+ * Copyright (c) 2023, Linaro Limited
+ */
+
+/dts-v1/;
+
+#include <dt-bindings/leds/common.h>
+#include <dt-bindings/regulator/qcom,rpmh-regulator.h>
+#include "sm8650.dtsi"
+#include "pm8010.dtsi"
+#include "pm8550.dtsi"
+#include "pm8550b.dtsi"
+#define PMK8550VE_SID 8
+#include "pm8550ve.dtsi"
+#include "pm8550vs.dtsi"
+#include "pmk8550.dtsi"
+#include "pmr735d_a.dtsi"
+
+/ {
+ model = "Qualcomm Technologies, Inc. SM8650 QRD";
+ compatible = "qcom,sm8650-qrd", "qcom,sm8650";
+
+ aliases {
+ serial0 = &uart15;
+ serial1 = &uart14;
+ };
+
+ chosen {
+ stdout-path = "serial0:115200n8";
+ };
+
+ gpio-keys {
+ compatible = "gpio-keys";
+
+ pinctrl-0 = <&volume_up_n>;
+ pinctrl-names = "default";
+
+ key-volume-up {
+ label = "Volume Up";
+ linux,code = <KEY_VOLUMEUP>;
+ gpios = <&pm8550_gpios 6 GPIO_ACTIVE_LOW>;
+ debounce-interval = <15>;
+ linux,can-disable;
+ wakeup-source;
+ };
+ };
+
+ pmic-glink {
+ compatible = "qcom,sm8650-pmic-glink",
+ "qcom,sm8550-pmic-glink",
+ "qcom,pmic-glink";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ orientation-gpios = <&tlmm 29 GPIO_ACTIVE_HIGH>;
+
+ connector@0 {
+ compatible = "usb-c-connector";
+ reg = <0>;
+
+ power-role = "dual";
+ data-role = "dual";
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+
+ pmic_glink_hs_in: endpoint {
+ remote-endpoint = <&usb_1_dwc3_hs>;
+ };
+ };
+
+ port@1 {
+ reg = <1>;
+
+ pmic_glink_ss_in: endpoint {
+ remote-endpoint = <&usb_1_dwc3_ss>;
+ };
+ };
+ };
+ };
+ };
+
+ vph_pwr: vph-pwr-regulator {
+ compatible = "regulator-fixed";
+
+ regulator-name = "vph_pwr";
+ regulator-min-microvolt = <3700000>;
+ regulator-max-microvolt = <3700000>;
+
+ regulator-always-on;
+ regulator-boot-on;
+ };
+};
+
+&apps_rsc {
+ regulators-0 {
+ compatible = "qcom,pm8550-rpmh-regulators";
+
+ vdd-bob1-supply = <&vph_pwr>;
+ vdd-bob2-supply = <&vph_pwr>;
+ vdd-l2-l13-l14-supply = <&vreg_bob1>;
+ vdd-l3-supply = <&vreg_s1c_1p2>;
+ vdd-l5-l16-supply = <&vreg_bob1>;
+ vdd-l6-l7-supply = <&vreg_bob1>;
+ vdd-l8-l9-supply = <&vreg_bob1>;
+ vdd-l11-supply = <&vreg_s1c_1p2>;
+ vdd-l12-supply = <&vreg_s6c_1p8>;
+ vdd-l15-supply = <&vreg_s6c_1p8>;
+ vdd-l17-supply = <&vreg_bob2>;
+
+ qcom,pmic-id = "b";
+
+ vreg_bob1: bob1 {
+ regulator-name = "vreg_bob1";
+ regulator-min-microvolt = <3296000>;
+ regulator-max-microvolt = <3960000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_bob2: bob2 {
+ regulator-name = "vreg_bob2";
+ regulator-min-microvolt = <2720000>;
+ regulator-max-microvolt = <3008000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_l2b_3p0: ldo2 {
+ regulator-name = "vreg_l2b_3p0";
+ regulator-min-microvolt = <3008000>;
+ regulator-max-microvolt = <3008000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ regulator-allow-set-load;
+ regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM
+ RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_l5b_3p1: ldo5 {
+ regulator-name = "vreg_l5b_3p1";
+ regulator-min-microvolt = <3104000>;
+ regulator-max-microvolt = <3104000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ regulator-allow-set-load;
+ regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM
+ RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_l6b_1p8: ldo6 {
+ regulator-name = "vreg_l6b_1p8";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <3008000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ regulator-allow-set-load;
+ regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM
+ RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_l7b_1p8: ldo7 {
+ regulator-name = "vreg_l7b_1p8";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <3008000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_l8b_1p8: ldo8 {
+ regulator-name = "vreg_l8b_1p8";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <3008000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ regulator-allow-set-load;
+ regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM
+ RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_l11b_1p2: ldo11 {
+ regulator-name = "vreg_l11b_1p2";
+ regulator-min-microvolt = <1200000>;
+ regulator-max-microvolt = <1504000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ regulator-allow-set-load;
+ regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM
+ RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_l12b_1p8: ldo12 {
+ regulator-name = "vreg_l12b_1p8";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ regulator-allow-set-load;
+ regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM
+ RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_l13b_3p0: ldo13 {
+ regulator-name = "vreg_l13b_3p0";
+ regulator-min-microvolt = <3000000>;
+ regulator-max-microvolt = <3000000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ regulator-allow-set-load;
+ regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM
+ RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_l14b_3p2: ldo14 {
+ regulator-name = "vreg_l14b_3p2";
+ regulator-min-microvolt = <3200000>;
+ regulator-max-microvolt = <3200000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ regulator-allow-set-load;
+ regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM
+ RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_l15b_1p8: ldo15 {
+ regulator-name = "vreg_l15b_1p8";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ regulator-allow-set-load;
+ regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM
+ RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_l16b_2p8: ldo16 {
+ regulator-name = "vreg_l16b_2p8";
+ regulator-min-microvolt = <2800000>;
+ regulator-max-microvolt = <2800000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ regulator-allow-set-load;
+ regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM
+ RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_l17b_2p5: ldo17 {
+ regulator-name = "vreg_l17b_2p5";
+ regulator-min-microvolt = <2504000>;
+ regulator-max-microvolt = <2504000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ regulator-allow-set-load;
+ regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM
+ RPMH_REGULATOR_MODE_HPM>;
+ };
+ };
+
+ regulators-1 {
+ compatible = "qcom,pm8550vs-rpmh-regulators";
+
+ vdd-l1-supply = <&vreg_s1c_1p2>;
+ vdd-l2-supply = <&vreg_s1c_1p2>;
+ vdd-l3-supply = <&vreg_s1c_1p2>;
+ vdd-s1-supply = <&vph_pwr>;
+ vdd-s2-supply = <&vph_pwr>;
+ vdd-s3-supply = <&vph_pwr>;
+ vdd-s4-supply = <&vph_pwr>;
+ vdd-s5-supply = <&vph_pwr>;
+ vdd-s6-supply = <&vph_pwr>;
+
+ qcom,pmic-id = "c";
+
+ vreg_s1c_1p2: smps1 {
+ regulator-name = "vreg_s1c_1p2";
+ regulator-min-microvolt = <1256000>;
+ regulator-max-microvolt = <1348000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_s2c_0p8: smps2 {
+ regulator-name = "vreg_s2c_0p8";
+ regulator-min-microvolt = <852000>;
+ regulator-max-microvolt = <1036000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_s3c_0p9: smps3 {
+ regulator-name = "vreg_s3c_0p9";
+ regulator-min-microvolt = <976000>;
+ regulator-max-microvolt = <1064000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_s4c_1p2: smps4 {
+ regulator-name = "vreg_s4c_1p2";
+ regulator-min-microvolt = <1224000>;
+ regulator-max-microvolt = <1280000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_s5c_0p7: smps5 {
+ regulator-name = "vreg_s5c_0p7";
+ regulator-min-microvolt = <752000>;
+ regulator-max-microvolt = <900000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_s6c_1p8: smps6 {
+ regulator-name = "vreg_s6c_1p8";
+ regulator-min-microvolt = <1856000>;
+ regulator-max-microvolt = <2000000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_l1c_1p2: ldo1 {
+ regulator-name = "vreg_l1c_1p2";
+ regulator-min-microvolt = <1200000>;
+ regulator-max-microvolt = <1200000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ regulator-allow-set-load;
+ regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM
+ RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_l3c_1p2: ldo3 {
+ regulator-name = "vreg_l3c_1p2";
+ regulator-min-microvolt = <1200000>;
+ regulator-max-microvolt = <1200000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ regulator-allow-set-load;
+ regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM
+ RPMH_REGULATOR_MODE_HPM>;
+ };
+ };
+
+ regulators-2 {
+ compatible = "qcom,pm8550vs-rpmh-regulators";
+
+ vdd-l1-supply = <&vreg_s3c_0p9>;
+
+ qcom,pmic-id = "d";
+
+ vreg_l1d_0p88: ldo1 {
+ regulator-name = "vreg_l1d_0p88";
+ regulator-min-microvolt = <912000>;
+ regulator-max-microvolt = <920000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ regulator-allow-set-load;
+ regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM
+ RPMH_REGULATOR_MODE_HPM>;
+ };
+ };
+
+ regulators-3 {
+ compatible = "qcom,pm8550vs-rpmh-regulators";
+
+ vdd-l3-supply = <&vreg_s3c_0p9>;
+
+ qcom,pmic-id = "e";
+
+ vreg_l3e_0p9: ldo3 {
+ regulator-name = "vreg_l3e_0p9";
+ regulator-min-microvolt = <880000>;
+ regulator-max-microvolt = <920000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ regulator-allow-set-load;
+ regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM
+ RPMH_REGULATOR_MODE_HPM>;
+ };
+ };
+
+ regulators-4 {
+ compatible = "qcom,pm8550vs-rpmh-regulators";
+
+ vdd-l1-supply = <&vreg_s3c_0p9>;
+ vdd-l3-supply = <&vreg_s3c_0p9>;
+
+ qcom,pmic-id = "g";
+
+ vreg_l1g_0p91: ldo1 {
+ regulator-name = "vreg_l1g_0p91";
+ regulator-min-microvolt = <912000>;
+ regulator-max-microvolt = <920000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ regulator-allow-set-load;
+ regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM
+ RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_l3g_0p91: ldo3 {
+ regulator-name = "vreg_l3g_0p91";
+ regulator-min-microvolt = <880000>;
+ regulator-max-microvolt = <912000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ regulator-allow-set-load;
+ regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM
+ RPMH_REGULATOR_MODE_HPM>;
+ };
+ };
+
+ regulators-5 {
+ compatible = "qcom,pm8550ve-rpmh-regulators";
+
+ vdd-l1-supply = <&vreg_s3c_0p9>;
+ vdd-l2-supply = <&vreg_s3c_0p9>;
+ vdd-l3-supply = <&vreg_s1c_1p2>;
+ vdd-s4-supply = <&vph_pwr>;
+
+ qcom,pmic-id = "i";
+
+ vreg_s4i_0p85: smps4 {
+ regulator-name = "vreg_s4i_0p85";
+ regulator-min-microvolt = <852000>;
+ regulator-max-microvolt = <1004000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_l1i_0p88: ldo1 {
+ regulator-name = "vreg_l1i_0p88";
+ regulator-min-microvolt = <880000>;
+ regulator-max-microvolt = <912000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ regulator-allow-set-load;
+ regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM
+ RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_l2i_0p88: ldo2 {
+ regulator-name = "vreg_l2i_0p88";
+ regulator-min-microvolt = <880000>;
+ regulator-max-microvolt = <912000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ regulator-allow-set-load;
+ regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM
+ RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_l3i_1p2: ldo3 {
+ regulator-name = "vreg_l3i_0p91";
+ regulator-min-microvolt = <1200000>;
+ regulator-max-microvolt = <1200000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ regulator-allow-set-load;
+ regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM
+ RPMH_REGULATOR_MODE_HPM>;
+ };
+ };
+};
+
+&dispcc {
+ status = "okay";
+};
+
+&gpi_dma1 {
+ status = "okay";
+};
+
+&ipa {
+ qcom,gsi-loader = "self";
+ memory-region = <&ipa_fw_mem>;
+ firmware-name = "qcom/sm8650/ipa_fws.mbn";
+ status = "okay";
+};
+
+&mdss {
+ status = "okay";
+};
+
+&mdss_dsi0 {
+ vdda-supply = <&vreg_l3i_1p2>;
+
+ status = "okay";
+
+ panel@0 {
+ compatible = "visionox,vtdr6130";
+ reg = <0>;
+
+ reset-gpios = <&tlmm 133 GPIO_ACTIVE_LOW>;
+
+ vddio-supply = <&vreg_l12b_1p8>;
+ vci-supply = <&vreg_l13b_3p0>;
+ vdd-supply = <&vreg_l11b_1p2>;
+
+ pinctrl-0 = <&disp0_reset_n_active>, <&mdp_vsync_active>;
+ pinctrl-1 = <&disp0_reset_n_suspend>, <&mdp_vsync_suspend>;
+ pinctrl-names = "default", "sleep";
+
+ port {
+ panel0_in: endpoint {
+ remote-endpoint = <&mdss_dsi0_out>;
+ };
+ };
+ };
+};
+
+&mdss_dsi0_out {
+ remote-endpoint = <&panel0_in>;
+ data-lanes = <0 1 2 3>;
+};
+
+&mdss_dsi0_phy {
+ vdds-supply = <&vreg_l1i_0p88>;
+
+ status = "okay";
+};
+
+&mdss_mdp {
+ status = "okay";
+};
+
+&pcie_1_phy_aux_clk {
+ clock-frequency = <1000>;
+};
+
+&pcie0 {
+ wake-gpios = <&tlmm 96 GPIO_ACTIVE_HIGH>;
+ perst-gpios = <&tlmm 94 GPIO_ACTIVE_LOW>;
+
+ pinctrl-0 = <&pcie0_default_state>;
+ pinctrl-names = "default";
+
+ status = "okay";
+};
+
+&pcie0_phy {
+ vdda-phy-supply = <&vreg_l1i_0p88>;
+ vdda-pll-supply = <&vreg_l3i_1p2>;
+
+ status = "okay";
+};
+
+&pon_pwrkey {
+ status = "okay";
+};
+
+&pon_resin {
+ linux,code = <KEY_VOLUMEDOWN>;
+
+ status = "okay";
+};
+
+&pm8550_flash {
+ status = "okay";
+
+ led-0 {
+ function = LED_FUNCTION_FLASH;
+ color = <LED_COLOR_ID_YELLOW>;
+ led-sources = <1>, <4>;
+ led-max-microamp = <500000>;
+ flash-max-microamp = <2000000>;
+ flash-max-timeout-us = <1280000>;
+ function-enumerator = <0>;
+ };
+
+ led-1 {
+ function = LED_FUNCTION_FLASH;
+ color = <LED_COLOR_ID_WHITE>;
+ led-sources = <2>, <3>;
+ led-max-microamp = <500000>;
+ flash-max-microamp = <2000000>;
+ flash-max-timeout-us = <1280000>;
+ function-enumerator = <1>;
+ };
+};
+
+&pm8550_gpios {
+ volume_up_n: volume-up-n-state {
+ pins = "gpio6";
+ function = "normal";
+ bias-pull-up;
+ input-enable;
+ power-source = <1>;
+ };
+};
+
+&pm8550_pwm {
+ status = "okay";
+
+ multi-led {
+ color = <LED_COLOR_ID_RGB>;
+ function = LED_FUNCTION_STATUS;
+
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ led@1 {
+ reg = <1>;
+ color = <LED_COLOR_ID_RED>;
+ };
+
+ led@2 {
+ reg = <2>;
+ color = <LED_COLOR_ID_GREEN>;
+ };
+
+ led@3 {
+ reg = <3>;
+ color = <LED_COLOR_ID_BLUE>;
+ };
+ };
+};
+
+&pm8550b_eusb2_repeater {
+ vdd18-supply = <&vreg_l15b_1p8>;
+ vdd3-supply = <&vreg_l5b_3p1>;
+};
+
+&pmk8550_rtc {
+ status = "okay";
+};
+
+&qupv3_id_0 {
+ status = "okay";
+};
+
+&qupv3_id_1 {
+ status = "okay";
+};
+
+&remoteproc_adsp {
+ firmware-name = "qcom/sm8650/adsp.mbn",
+ "qcom/sm8650/adsp_dtb.mbn";
+
+ status = "okay";
+};
+
+&remoteproc_cdsp {
+ firmware-name = "qcom/sm8650/cdsp.mbn",
+ "qcom/sm8650/cdsp_dtb.mbn";
+
+ status = "okay";
+};
+
+&remoteproc_mpss {
+ firmware-name = "qcom/sm8650/modem.mbn",
+ "qcom/sm8650/modem_dtb.mbn";
+
+ status = "okay";
+};
+
+&sleep_clk {
+ clock-frequency = <32000>;
+};
+
+&spi4 {
+ status = "okay";
+
+ touchscreen@0 {
+ compatible = "goodix,gt9916";
+ reg = <0>;
+
+ interrupt-parent = <&tlmm>;
+ interrupts = <162 IRQ_TYPE_LEVEL_LOW>;
+
+ reset-gpios = <&tlmm 161 GPIO_ACTIVE_LOW>;
+
+ avdd-supply = <&vreg_l14b_3p2>;
+
+ spi-max-frequency = <1000000>;
+
+ touchscreen-size-x = <1080>;
+ touchscreen-size-y = <2400>;
+
+ pinctrl-0 = <&ts_irq>, <&ts_reset>;
+ pinctrl-names = "default";
+ };
+};
+
+&tlmm {
+ /* Reserved I/Os for NFC */
+ gpio-reserved-ranges = <32 8>, <74 1>;
+
+ bt_default: bt-default-state {
+ bt-en-pins {
+ pins = "gpio17";
+ function = "gpio";
+ drive-strength = <16>;
+ bias-disable;
+ };
+
+ sw-ctrl-pins {
+ pins = "gpio18";
+ function = "gpio";
+ bias-pull-down;
+ };
+ };
+
+ disp0_reset_n_active: disp0-reset-n-active-state {
+ pins = "gpio133";
+ function = "gpio";
+ drive-strength = <8>;
+ bias-disable;
+ };
+
+ disp0_reset_n_suspend: disp0-reset-n-suspend-state {
+ pins = "gpio133";
+ function = "gpio";
+ drive-strength = <2>;
+ bias-pull-down;
+ };
+
+ mdp_vsync_active: mdp-vsync-active-state {
+ pins = "gpio86";
+ function = "mdp_vsync";
+ drive-strength = <2>;
+ bias-pull-down;
+ };
+
+ mdp_vsync_suspend: mdp-vsync-suspend-state {
+ pins = "gpio86";
+ function = "mdp_vsync";
+ drive-strength = <2>;
+ bias-pull-down;
+ };
+
+ ts_irq: ts-irq-state {
+ pins = "gpio161";
+ function = "gpio";
+ drive-strength = <8>;
+ bias-pull-up;
+ output-disable;
+ };
+
+ ts_reset: ts-reset-state {
+ pins = "gpio162";
+ function = "gpio";
+ drive-strength = <8>;
+ bias-pull-up;
+ };
+};
+
+&uart14 {
+ status = "okay";
+
+ bluetooth {
+ compatible = "qcom,wcn7850-bt";
+
+ clocks = <&rpmhcc RPMH_RF_CLK1>;
+
+ vddio-supply = <&vreg_l3c_1p2>;
+ vddaon-supply = <&vreg_l15b_1p8>;
+ vdddig-supply = <&vreg_s3c_0p9>;
+ vddrfa0p8-supply = <&vreg_s3c_0p9>;
+ vddrfa1p2-supply = <&vreg_s1c_1p2>;
+ vddrfa1p9-supply = <&vreg_s6c_1p8>;
+
+ max-speed = <3200000>;
+
+ enable-gpios = <&tlmm 17 GPIO_ACTIVE_HIGH>;
+ swctrl-gpios = <&tlmm 18 GPIO_ACTIVE_HIGH>;
+
+ pinctrl-0 = <&bt_default>;
+ pinctrl-names = "default";
+ };
+};
+
+&uart15 {
+ status = "okay";
+};
+
+&ufs_mem_hc {
+ reset-gpios = <&tlmm 210 GPIO_ACTIVE_LOW>;
+
+ vcc-supply = <&vreg_l17b_2p5>;
+ vcc-max-microamp = <1300000>;
+ vccq-supply = <&vreg_l1c_1p2>;
+ vccq-max-microamp = <1200000>;
+
+ status = "okay";
+};
+
+&ufs_mem_phy {
+ vdda-phy-supply = <&vreg_l1d_0p88>;
+ vdda-pll-supply = <&vreg_l3i_1p2>;
+
+ status = "okay";
+};
+
+/*
+ * DPAUX -> WCD9395 -> USB_SBU -> USB-C
+ * eUSB2 DP/DM -> PM85550HS -> eUSB2 DP/DM -> WCD9395 -> USB-C
+ * USB SS -> NB7VPQ904MMUTWG -> USB-C
+ */
+
+&usb_1 {
+ status = "okay";
+};
+
+&usb_1_dwc3 {
+ dr_mode = "otg";
+ usb-role-switch;
+};
+
+&usb_1_dwc3_hs {
+ remote-endpoint = <&pmic_glink_hs_in>;
+};
+
+&usb_1_dwc3_ss {
+ remote-endpoint = <&pmic_glink_ss_in>;
+};
+
+&usb_1_hsphy {
+ vdd-supply = <&vreg_l1i_0p88>;
+ vdda12-supply = <&vreg_l3i_1p2>;
+
+ phys = <&pm8550b_eusb2_repeater>;
+
+ status = "okay";
+};
+
+&usb_dp_qmpphy {
+ vdda-phy-supply = <&vreg_l3i_1p2>;
+ vdda-pll-supply = <&vreg_l3g_0p91>;
+
+ status = "okay";
+};
+
+&xo_board {
+ clock-frequency = <76800000>;
+};
diff --git a/dts/upstream/src/arm64/qcom/sm8650.dtsi b/dts/upstream/src/arm64/qcom/sm8650.dtsi
new file mode 100644
index 0000000..2df7712
--- /dev/null
+++ b/dts/upstream/src/arm64/qcom/sm8650.dtsi
@@ -0,0 +1,6013 @@
+// SPDX-License-Identifier: BSD-3-Clause
+/*
+ * Copyright (c) 2023, Linaro Limited
+ */
+
+#include <dt-bindings/clock/qcom,rpmh.h>
+#include <dt-bindings/clock/qcom,sm8650-dispcc.h>
+#include <dt-bindings/clock/qcom,sm8650-gcc.h>
+#include <dt-bindings/clock/qcom,sm8650-gpucc.h>
+#include <dt-bindings/clock/qcom,sm8650-tcsr.h>
+#include <dt-bindings/dma/qcom-gpi.h>
+#include <dt-bindings/firmware/qcom,scm.h>
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/interconnect/qcom,icc.h>
+#include <dt-bindings/interconnect/qcom,sm8650-rpmh.h>
+#include <dt-bindings/interrupt-controller/arm-gic.h>
+#include <dt-bindings/mailbox/qcom-ipcc.h>
+#include <dt-bindings/phy/phy-qcom-qmp.h>
+#include <dt-bindings/power/qcom,rpmhpd.h>
+#include <dt-bindings/power/qcom-rpmpd.h>
+#include <dt-bindings/reset/qcom,sm8650-gpucc.h>
+#include <dt-bindings/soc/qcom,gpr.h>
+#include <dt-bindings/soc/qcom,rpmh-rsc.h>
+#include <dt-bindings/sound/qcom,q6dsp-lpass-ports.h>
+#include <dt-bindings/thermal/thermal.h>
+
+/ {
+ interrupt-parent = <&intc>;
+
+ #address-cells = <2>;
+ #size-cells = <2>;
+
+ chosen { };
+
+ clocks {
+ xo_board: xo-board {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ };
+
+ sleep_clk: sleep-clk {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ };
+
+ bi_tcxo_div2: bi-tcxo-div2-clk {
+ compatible = "fixed-factor-clock";
+ #clock-cells = <0>;
+
+ clocks = <&rpmhcc RPMH_CXO_CLK>;
+ clock-mult = <1>;
+ clock-div = <2>;
+ };
+
+ bi_tcxo_ao_div2: bi-tcxo-ao-div2-clk {
+ compatible = "fixed-factor-clock";
+ #clock-cells = <0>;
+
+ clocks = <&rpmhcc RPMH_CXO_CLK_A>;
+ clock-mult = <1>;
+ clock-div = <2>;
+ };
+
+ pcie_1_phy_aux_clk: pcie-1-phy-aux-clk {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ };
+ };
+
+ cpus {
+ #address-cells = <2>;
+ #size-cells = <0>;
+
+ CPU0: cpu@0 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a520";
+ reg = <0 0>;
+
+ clocks = <&cpufreq_hw 0>;
+
+ power-domains = <&CPU_PD0>;
+ power-domain-names = "psci";
+
+ enable-method = "psci";
+ next-level-cache = <&L2_0>;
+ capacity-dmips-mhz = <1024>;
+ dynamic-power-coefficient = <100>;
+
+ qcom,freq-domain = <&cpufreq_hw 0>;
+
+ #cooling-cells = <2>;
+
+ L2_0: l2-cache {
+ compatible = "cache";
+ cache-level = <2>;
+ cache-unified;
+ next-level-cache = <&L3_0>;
+
+ L3_0: l3-cache {
+ compatible = "cache";
+ cache-level = <3>;
+ cache-unified;
+ };
+ };
+ };
+
+ CPU1: cpu@100 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a520";
+ reg = <0 0x100>;
+
+ clocks = <&cpufreq_hw 0>;
+
+ power-domains = <&CPU_PD1>;
+ power-domain-names = "psci";
+
+ enable-method = "psci";
+ next-level-cache = <&L2_0>;
+ capacity-dmips-mhz = <1024>;
+ dynamic-power-coefficient = <100>;
+
+ qcom,freq-domain = <&cpufreq_hw 0>;
+
+ #cooling-cells = <2>;
+ };
+
+ CPU2: cpu@200 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a720";
+ reg = <0 0x200>;
+
+ clocks = <&cpufreq_hw 3>;
+
+ power-domains = <&CPU_PD2>;
+ power-domain-names = "psci";
+
+ enable-method = "psci";
+ next-level-cache = <&L2_200>;
+ capacity-dmips-mhz = <1792>;
+ dynamic-power-coefficient = <238>;
+
+ qcom,freq-domain = <&cpufreq_hw 3>;
+
+ #cooling-cells = <2>;
+
+ L2_200: l2-cache {
+ compatible = "cache";
+ cache-level = <2>;
+ cache-unified;
+ next-level-cache = <&L3_0>;
+ };
+ };
+
+ CPU3: cpu@300 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a720";
+ reg = <0 0x300>;
+
+ clocks = <&cpufreq_hw 3>;
+
+ power-domains = <&CPU_PD3>;
+ power-domain-names = "psci";
+
+ enable-method = "psci";
+ next-level-cache = <&L2_200>;
+ capacity-dmips-mhz = <1792>;
+ dynamic-power-coefficient = <238>;
+
+ qcom,freq-domain = <&cpufreq_hw 3>;
+
+ #cooling-cells = <2>;
+ };
+
+ CPU4: cpu@400 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a720";
+ reg = <0 0x400>;
+
+ clocks = <&cpufreq_hw 3>;
+
+ power-domains = <&CPU_PD4>;
+ power-domain-names = "psci";
+
+ enable-method = "psci";
+ next-level-cache = <&L2_400>;
+ capacity-dmips-mhz = <1792>;
+ dynamic-power-coefficient = <238>;
+
+ qcom,freq-domain = <&cpufreq_hw 3>;
+
+ #cooling-cells = <2>;
+
+ L2_400: l2-cache {
+ compatible = "cache";
+ cache-level = <2>;
+ cache-unified;
+ next-level-cache = <&L3_0>;
+ };
+ };
+
+ CPU5: cpu@500 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a720";
+ reg = <0 0x500>;
+
+ clocks = <&cpufreq_hw 1>;
+
+ power-domains = <&CPU_PD5>;
+ power-domain-names = "psci";
+
+ enable-method = "psci";
+ next-level-cache = <&L2_500>;
+ capacity-dmips-mhz = <1792>;
+ dynamic-power-coefficient = <238>;
+
+ qcom,freq-domain = <&cpufreq_hw 1>;
+
+ #cooling-cells = <2>;
+
+ L2_500: l2-cache {
+ compatible = "cache";
+ cache-level = <2>;
+ cache-unified;
+ next-level-cache = <&L3_0>;
+ };
+ };
+
+ CPU6: cpu@600 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a720";
+ reg = <0 0x600>;
+
+ clocks = <&cpufreq_hw 1>;
+
+ power-domains = <&CPU_PD6>;
+ power-domain-names = "psci";
+
+ enable-method = "psci";
+ next-level-cache = <&L2_600>;
+ capacity-dmips-mhz = <1792>;
+ dynamic-power-coefficient = <238>;
+
+ qcom,freq-domain = <&cpufreq_hw 1>;
+
+ #cooling-cells = <2>;
+
+ L2_600: l2-cache {
+ compatible = "cache";
+ cache-level = <2>;
+ cache-unified;
+ next-level-cache = <&L3_0>;
+ };
+ };
+
+ CPU7: cpu@700 {
+ device_type = "cpu";
+ compatible = "arm,cortex-x4";
+ reg = <0 0x700>;
+
+ clocks = <&cpufreq_hw 2>;
+
+ power-domains = <&CPU_PD7>;
+ power-domain-names = "psci";
+
+ enable-method = "psci";
+ next-level-cache = <&L2_700>;
+ capacity-dmips-mhz = <1894>;
+ dynamic-power-coefficient = <588>;
+
+ qcom,freq-domain = <&cpufreq_hw 2>;
+
+ #cooling-cells = <2>;
+
+ L2_700: l2-cache {
+ compatible = "cache";
+ cache-level = <2>;
+ cache-unified;
+ next-level-cache = <&L3_0>;
+ };
+ };
+
+ cpu-map {
+ cluster0 {
+ core0 {
+ cpu = <&CPU0>;
+ };
+
+ core1 {
+ cpu = <&CPU1>;
+ };
+
+ core2 {
+ cpu = <&CPU2>;
+ };
+
+ core3 {
+ cpu = <&CPU3>;
+ };
+
+ core4 {
+ cpu = <&CPU4>;
+ };
+
+ core5 {
+ cpu = <&CPU5>;
+ };
+
+ core6 {
+ cpu = <&CPU6>;
+ };
+
+ core7 {
+ cpu = <&CPU7>;
+ };
+ };
+ };
+
+ idle-states {
+ entry-method = "psci";
+
+ SILVER_CPU_SLEEP_0: cpu-sleep-0-0 {
+ compatible = "arm,idle-state";
+ idle-state-name = "silver-rail-power-collapse";
+ arm,psci-suspend-param = <0x40000004>;
+ entry-latency-us = <550>;
+ exit-latency-us = <750>;
+ min-residency-us = <6700>;
+ local-timer-stop;
+ };
+
+ GOLD_CPU_SLEEP_0: cpu-sleep-1-0 {
+ compatible = "arm,idle-state";
+ idle-state-name = "gold-rail-power-collapse";
+ arm,psci-suspend-param = <0x40000004>;
+ entry-latency-us = <600>;
+ exit-latency-us = <1300>;
+ min-residency-us = <8136>;
+ local-timer-stop;
+ };
+
+ GOLD_PLUS_CPU_SLEEP_0: cpu-sleep-2-0 {
+ compatible = "arm,idle-state";
+ idle-state-name = "gold-plus-rail-power-collapse";
+ arm,psci-suspend-param = <0x40000004>;
+ entry-latency-us = <500>;
+ exit-latency-us = <1350>;
+ min-residency-us = <7480>;
+ local-timer-stop;
+ };
+ };
+
+ domain-idle-states {
+ CLUSTER_SLEEP_0: cluster-sleep-0 {
+ compatible = "domain-idle-state";
+ arm,psci-suspend-param = <0x41000044>;
+ entry-latency-us = <750>;
+ exit-latency-us = <2350>;
+ min-residency-us = <9144>;
+ };
+
+ CLUSTER_SLEEP_1: cluster-sleep-1 {
+ compatible = "domain-idle-state";
+ arm,psci-suspend-param = <0x4100c344>;
+ entry-latency-us = <2800>;
+ exit-latency-us = <4400>;
+ min-residency-us = <10150>;
+ };
+ };
+ };
+
+ firmware {
+ scm: scm {
+ compatible = "qcom,scm-sm8650", "qcom,scm";
+ interconnects = <&aggre2_noc MASTER_CRYPTO QCOM_ICC_TAG_ALWAYS
+ &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
+ };
+ };
+
+ clk_virt: interconnect-0 {
+ compatible = "qcom,sm8650-clk-virt";
+ #interconnect-cells = <2>;
+ qcom,bcm-voters = <&apps_bcm_voter>;
+ };
+
+ mc_virt: interconnect-1 {
+ compatible = "qcom,sm8650-mc-virt";
+ #interconnect-cells = <2>;
+ qcom,bcm-voters = <&apps_bcm_voter>;
+ };
+
+ memory@a0000000 {
+ device_type = "memory";
+ /* We expect the bootloader to fill in the size */
+ reg = <0 0xa0000000 0 0>;
+ };
+
+ pmu {
+ compatible = "arm,armv8-pmuv3";
+ interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_LOW>;
+ };
+
+ psci {
+ compatible = "arm,psci-1.0";
+ method = "smc";
+
+ CPU_PD0: power-domain-cpu0 {
+ #power-domain-cells = <0>;
+ power-domains = <&CLUSTER_PD>;
+ domain-idle-states = <&SILVER_CPU_SLEEP_0>;
+ };
+
+ CPU_PD1: power-domain-cpu1 {
+ #power-domain-cells = <0>;
+ power-domains = <&CLUSTER_PD>;
+ domain-idle-states = <&SILVER_CPU_SLEEP_0>;
+ };
+
+ CPU_PD2: power-domain-cpu2 {
+ #power-domain-cells = <0>;
+ power-domains = <&CLUSTER_PD>;
+ domain-idle-states = <&SILVER_CPU_SLEEP_0>;
+ };
+
+ CPU_PD3: power-domain-cpu3 {
+ #power-domain-cells = <0>;
+ power-domains = <&CLUSTER_PD>;
+ domain-idle-states = <&GOLD_CPU_SLEEP_0>;
+ };
+
+ CPU_PD4: power-domain-cpu4 {
+ #power-domain-cells = <0>;
+ power-domains = <&CLUSTER_PD>;
+ domain-idle-states = <&GOLD_CPU_SLEEP_0>;
+ };
+
+ CPU_PD5: power-domain-cpu5 {
+ #power-domain-cells = <0>;
+ power-domains = <&CLUSTER_PD>;
+ domain-idle-states = <&GOLD_CPU_SLEEP_0>;
+ };
+
+ CPU_PD6: power-domain-cpu6 {
+ #power-domain-cells = <0>;
+ power-domains = <&CLUSTER_PD>;
+ domain-idle-states = <&GOLD_CPU_SLEEP_0>;
+ };
+
+ CPU_PD7: power-domain-cpu7 {
+ #power-domain-cells = <0>;
+ power-domains = <&CLUSTER_PD>;
+ domain-idle-states = <&GOLD_PLUS_CPU_SLEEP_0>;
+ };
+
+ CLUSTER_PD: power-domain-cluster {
+ #power-domain-cells = <0>;
+ domain-idle-states = <&CLUSTER_SLEEP_0>,
+ <&CLUSTER_SLEEP_1>;
+ };
+ };
+
+ reserved_memory: reserved-memory {
+ #address-cells = <2>;
+ #size-cells = <2>;
+ ranges;
+
+ hyp_mem: hyp@80000000 {
+ reg = <0 0x80000000 0 0xe00000>;
+ no-map;
+ };
+
+ cpusys_vm_mem: cpusys-vm@80e00000 {
+ reg = <0 0x80e00000 0 0x400000>;
+ no-map;
+ };
+
+ /* Merged xbl_dtlog, xbl_ramdump and aop_image regions */
+ xbl_dt_log_merged_mem: xbl-dt-log-merged@81a00000 {
+ reg = <0 0x81a00000 0 0x260000>;
+ no-map;
+ };
+
+ aop_cmd_db_mem: aop-cmd-db@81c60000 {
+ compatible = "qcom,cmd-db";
+ reg = <0 0x81c60000 0 0x20000>;
+ no-map;
+ };
+
+ /* Merged aop_config, tme_crash_dump, tme_log and uefi_log regions */
+ aop_tme_uefi_merged_mem: aop-tme-uefi-merged@81c80000 {
+ reg = <0 0x81c80000 0 0x74000>;
+ no-map;
+ };
+
+ /* Secdata region can be reused by apps */
+
+ smem: smem@81d00000 {
+ compatible = "qcom,smem";
+ reg = <0 0x81d00000 0 0x200000>;
+ hwlocks = <&tcsr_mutex 3>;
+ no-map;
+ };
+
+ adsp_mhi_mem: adsp-mhi@81f00000 {
+ reg = <0 0x81f00000 0 0x20000>;
+ no-map;
+ };
+
+ pvmfw_mem: pvmfw@824a0000 {
+ reg = <0 0x824a0000 0 0x100000>;
+ no-map;
+ };
+
+ global_sync_mem: global-sync@82600000 {
+ reg = <0 0x82600000 0 0x100000>;
+ no-map;
+ };
+
+ tz_stat_mem: tz-stat@82700000 {
+ reg = <0 0x82700000 0 0x100000>;
+ no-map;
+ };
+
+ qdss_mem: qdss@82800000 {
+ reg = <0 0x82800000 0 0x2000000>;
+ no-map;
+ };
+
+ mpss_dsm_mem: mpss-dsm@86b00000 {
+ reg = <0 0x86b00000 0 0x4900000>;
+ no-map;
+ };
+
+ mpss_dsm_mem_2: mpss-dsm-2@8b400000 {
+ reg = <0 0x8b400000 0 0x800000>;
+ no-map;
+ };
+
+ mpss_mem: mpss@8bc00000 {
+ reg = <0 0x8bc00000 0 0xf400000>;
+ no-map;
+ };
+
+ q6_mpss_dtb_mem: q6-mpss-dtb@9b000000 {
+ reg = <0 0x9b000000 0 0x80000>;
+ no-map;
+ };
+
+ ipa_fw_mem: ipa-fw@9b080000 {
+ reg = <0 0x9b080000 0 0x10000>;
+ no-map;
+ };
+
+ ipa_gsi_mem: ipa-gsi@9b090000 {
+ reg = <0 0x9b090000 0 0xa000>;
+ no-map;
+ };
+
+ gpu_micro_code_mem: gpu-micro-code@9b09a000 {
+ reg = <0 0x9b09a000 0 0x2000>;
+ no-map;
+ };
+
+ spss_region_mem: spss@9b0a0000 {
+ reg = <0 0x9b0a0000 0 0x1e0000>;
+ no-map;
+ };
+
+ /* First part of the "SPU secure shared memory" region */
+ spu_tz_shared_mem: spu-tz-shared@9b280000 {
+ reg = <0 0x9b280000 0 0x60000>;
+ no-map;
+ };
+
+ /* Second part of the "SPU secure shared memory" region */
+ spu_modem_shared_mem: spu-modem-shared@9b2e0000 {
+ reg = <0 0x9b2e0000 0 0x20000>;
+ no-map;
+ };
+
+ camera_mem: camera@9b300000 {
+ reg = <0 0x9b300000 0 0x800000>;
+ no-map;
+ };
+
+ video_mem: video@9bb00000 {
+ reg = <0 0x9bb00000 0 0x800000>;
+ no-map;
+ };
+
+ cvp_mem: cvp@9c300000 {
+ reg = <0 0x9c300000 0 0x700000>;
+ no-map;
+ };
+
+ cdsp_mem: cdsp@9ca00000 {
+ reg = <0 0x9ca00000 0 0x1400000>;
+ no-map;
+ };
+
+ q6_cdsp_dtb_mem: q6-cdsp-dtb@9de00000 {
+ reg = <0 0x9de00000 0 0x80000>;
+ no-map;
+ };
+
+ q6_adsp_dtb_mem: q6-adsp-dtb@9de80000 {
+ reg = <0 0x9de80000 0 0x80000>;
+ no-map;
+ };
+
+ adspslpi_mem: adspslpi@9df00000 {
+ reg = <0 0x9df00000 0 0x4080000>;
+ no-map;
+ };
+
+ rmtfs_mem: rmtfs@d7c00000 {
+ compatible = "qcom,rmtfs-mem";
+ reg = <0 0xd7c00000 0 0x400000>;
+ no-map;
+
+ qcom,client-id = <1>;
+ qcom,vmid = <QCOM_SCM_VMID_MSS_MSA>;
+ };
+
+ /* Merged tz_reserved, xbl_sc, cpucp_fw and qtee regions */
+ tz_merged_mem: tz-merged@d8000000 {
+ reg = <0 0xd8000000 0 0x800000>;
+ no-map;
+ };
+
+ hwfence_shbuf: hwfence-shbuf@e6440000 {
+ reg = <0 0xe6440000 0 0x2dd000>;
+ no-map;
+ };
+
+ trust_ui_vm_mem: trust-ui-vm@f3800000 {
+ reg = <0 0xf3800000 0 0x4400000>;
+ no-map;
+ };
+
+ oem_vm_mem: oem-vm@f7c00000 {
+ reg = <0 0xf7c00000 0 0x4c00000>;
+ no-map;
+ };
+
+ llcc_lpi_mem: llcc-lpi@ff800000 {
+ reg = <0 0xff800000 0 0x600000>;
+ no-map;
+ };
+ };
+
+ smp2p-adsp {
+ compatible = "qcom,smp2p";
+
+ interrupts-extended = <&ipcc IPCC_CLIENT_LPASS
+ IPCC_MPROC_SIGNAL_SMP2P
+ IRQ_TYPE_EDGE_RISING>;
+
+ mboxes = <&ipcc IPCC_CLIENT_LPASS
+ IPCC_MPROC_SIGNAL_SMP2P>;
+
+ qcom,smem = <443>, <429>;
+ qcom,local-pid = <0>;
+ qcom,remote-pid = <2>;
+
+ smp2p_adsp_out: master-kernel {
+ qcom,entry-name = "master-kernel";
+ #qcom,smem-state-cells = <1>;
+ };
+
+ smp2p_adsp_in: slave-kernel {
+ qcom,entry-name = "slave-kernel";
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+ };
+
+ smp2p-cdsp {
+ compatible = "qcom,smp2p";
+
+ interrupts-extended = <&ipcc IPCC_CLIENT_CDSP
+ IPCC_MPROC_SIGNAL_SMP2P
+ IRQ_TYPE_EDGE_RISING>;
+
+ mboxes = <&ipcc IPCC_CLIENT_CDSP
+ IPCC_MPROC_SIGNAL_SMP2P>;
+
+ qcom,smem = <94>, <432>;
+ qcom,local-pid = <0>;
+ qcom,remote-pid = <5>;
+
+ smp2p_cdsp_out: master-kernel {
+ qcom,entry-name = "master-kernel";
+ #qcom,smem-state-cells = <1>;
+ };
+
+ smp2p_cdsp_in: slave-kernel {
+ qcom,entry-name = "slave-kernel";
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+ };
+
+ smp2p-modem {
+ compatible = "qcom,smp2p";
+
+ interrupts-extended = <&ipcc IPCC_CLIENT_MPSS
+ IPCC_MPROC_SIGNAL_SMP2P
+ IRQ_TYPE_EDGE_RISING>;
+
+ mboxes = <&ipcc IPCC_CLIENT_MPSS
+ IPCC_MPROC_SIGNAL_SMP2P>;
+
+ qcom,smem = <435>, <428>;
+ qcom,local-pid = <0>;
+ qcom,remote-pid = <1>;
+
+ smp2p_modem_out: master-kernel {
+ qcom,entry-name = "master-kernel";
+ #qcom,smem-state-cells = <1>;
+ };
+
+ smp2p_modem_in: slave-kernel {
+ qcom,entry-name = "slave-kernel";
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+
+ ipa_smp2p_out: ipa-ap-to-modem {
+ qcom,entry-name = "ipa";
+ #qcom,smem-state-cells = <1>;
+ };
+
+ ipa_smp2p_in: ipa-modem-to-ap {
+ qcom,entry-name = "ipa";
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+ };
+
+ soc: soc@0 {
+ compatible = "simple-bus";
+
+ #address-cells = <2>;
+ #size-cells = <2>;
+ dma-ranges = <0 0 0 0 0x10 0>;
+ ranges = <0 0 0 0 0x10 0>;
+
+ gcc: clock-controller@100000 {
+ compatible = "qcom,sm8650-gcc";
+ reg = <0 0x00100000 0 0x1f4200>;
+
+ clocks = <&bi_tcxo_div2>,
+ <&bi_tcxo_ao_div2>,
+ <&sleep_clk>,
+ <&pcie0_phy>,
+ <&pcie1_phy>,
+ <&pcie_1_phy_aux_clk>,
+ <&ufs_mem_phy 0>,
+ <&ufs_mem_phy 1>,
+ <&ufs_mem_phy 2>,
+ <&usb_dp_qmpphy QMP_USB43DP_USB3_PIPE_CLK>;
+
+ #clock-cells = <1>;
+ #reset-cells = <1>;
+ #power-domain-cells = <1>;
+ };
+
+ ipcc: mailbox@406000 {
+ compatible = "qcom,sm8650-ipcc", "qcom,ipcc";
+ reg = <0 0x00406000 0 0x1000>;
+
+ interrupts = <GIC_SPI 229 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-controller;
+ #interrupt-cells = <3>;
+
+ #mbox-cells = <2>;
+ };
+
+ gpi_dma2: dma-controller@800000 {
+ compatible = "qcom,sm8650-gpi-dma", "qcom,sm6350-gpi-dma";
+ reg = <0 0x00800000 0 0x60000>;
+
+ interrupts = <GIC_SPI 588 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 589 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 590 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 591 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 592 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 593 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 594 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 595 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 596 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 597 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 598 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 599 IRQ_TYPE_LEVEL_HIGH>;
+
+ dma-channels = <12>;
+ dma-channel-mask = <0x3f>;
+ #dma-cells = <3>;
+
+ iommus = <&apps_smmu 0x436 0>;
+
+ dma-coherent;
+
+ status = "disabled";
+ };
+
+ qupv3_id_1: geniqup@8c0000 {
+ compatible = "qcom,geni-se-qup";
+ reg = <0 0x008c0000 0 0x2000>;
+
+ clocks = <&gcc GCC_QUPV3_WRAP_2_M_AHB_CLK>,
+ <&gcc GCC_QUPV3_WRAP_2_S_AHB_CLK>;
+ clock-names = "m-ahb",
+ "s-ahb";
+
+ iommus = <&apps_smmu 0x423 0>;
+
+ dma-coherent;
+
+ #address-cells = <2>;
+ #size-cells = <2>;
+ ranges;
+
+ status = "disabled";
+
+ i2c8: i2c@880000 {
+ compatible = "qcom,geni-i2c";
+ reg = <0 0x00880000 0 0x4000>;
+
+ interrupts = <GIC_SPI 373 IRQ_TYPE_LEVEL_HIGH>;
+
+ clocks = <&gcc GCC_QUPV3_WRAP2_S0_CLK>;
+ clock-names = "se";
+
+ interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS
+ &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>,
+ <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
+ &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>,
+ <&aggre2_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS
+ &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
+ interconnect-names = "qup-core",
+ "qup-config",
+ "qup-memory";
+
+ dmas = <&gpi_dma2 0 0 QCOM_GPI_I2C>,
+ <&gpi_dma2 1 0 QCOM_GPI_I2C>;
+ dma-names = "tx",
+ "rx";
+
+ pinctrl-0 = <&qup_i2c8_data_clk>;
+ pinctrl-names = "default";
+
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ status = "disabled";
+ };
+
+ spi8: spi@880000 {
+ compatible = "qcom,geni-spi";
+ reg = <0 0x00880000 0 0x4000>;
+
+ interrupts = <GIC_SPI 373 IRQ_TYPE_LEVEL_HIGH>;
+
+ clocks = <&gcc GCC_QUPV3_WRAP2_S0_CLK>;
+ clock-names = "se";
+
+ interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS
+ &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>,
+ <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
+ &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>,
+ <&aggre2_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS
+ &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
+ interconnect-names = "qup-core",
+ "qup-config",
+ "qup-memory";
+
+ dmas = <&gpi_dma2 0 0 QCOM_GPI_SPI>,
+ <&gpi_dma2 1 0 QCOM_GPI_SPI>;
+ dma-names = "tx",
+ "rx";
+
+ pinctrl-0 = <&qup_spi8_data_clk>, <&qup_spi8_cs>;
+ pinctrl-names = "default";
+
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ status = "disabled";
+ };
+
+ i2c9: i2c@884000 {
+ compatible = "qcom,geni-i2c";
+ reg = <0 0x00884000 0 0x4000>;
+
+ interrupts = <GIC_SPI 583 IRQ_TYPE_LEVEL_HIGH>;
+
+ clocks = <&gcc GCC_QUPV3_WRAP2_S1_CLK>;
+ clock-names = "se";
+
+ interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS
+ &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>,
+ <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
+ &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>,
+ <&aggre2_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS
+ &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
+ interconnect-names = "qup-core",
+ "qup-config",
+ "qup-memory";
+
+ dmas = <&gpi_dma2 0 1 QCOM_GPI_I2C>,
+ <&gpi_dma2 1 1 QCOM_GPI_I2C>;
+ dma-names = "tx",
+ "rx";
+
+ pinctrl-0 = <&qup_i2c9_data_clk>;
+ pinctrl-names = "default";
+
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ status = "disabled";
+ };
+
+ spi9: spi@884000 {
+ compatible = "qcom,geni-spi";
+ reg = <0 0x00884000 0 0x4000>;
+
+ interrupts = <GIC_SPI 583 IRQ_TYPE_LEVEL_HIGH>;
+
+ clocks = <&gcc GCC_QUPV3_WRAP2_S1_CLK>;
+ clock-names = "se";
+
+ interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS
+ &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>,
+ <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
+ &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>,
+ <&aggre2_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS
+ &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
+ interconnect-names = "qup-core",
+ "qup-config",
+ "qup-memory";
+
+ dmas = <&gpi_dma2 0 1 QCOM_GPI_SPI>,
+ <&gpi_dma2 1 1 QCOM_GPI_SPI>;
+ dma-names = "tx",
+ "rx";
+
+ pinctrl-0 = <&qup_spi9_data_clk>, <&qup_spi9_cs>;
+ pinctrl-names = "default";
+
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ status = "disabled";
+ };
+
+ i2c10: i2c@888000 {
+ compatible = "qcom,geni-i2c";
+ reg = <0 0x00888000 0 0x4000>;
+
+ interrupts = <GIC_SPI 584 IRQ_TYPE_LEVEL_HIGH>;
+
+ clocks = <&gcc GCC_QUPV3_WRAP2_S2_CLK>;
+ clock-names = "se";
+
+ interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS
+ &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>,
+ <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
+ &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>,
+ <&aggre2_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS
+ &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
+ interconnect-names = "qup-core",
+ "qup-config",
+ "qup-memory";
+
+ dmas = <&gpi_dma2 0 2 QCOM_GPI_I2C>,
+ <&gpi_dma2 1 2 QCOM_GPI_I2C>;
+ dma-names = "tx",
+ "rx";
+
+ pinctrl-0 = <&qup_i2c10_data_clk>;
+ pinctrl-names = "default";
+
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ status = "disabled";
+ };
+
+ spi10: spi@888000 {
+ compatible = "qcom,geni-spi";
+ reg = <0 0x00888000 0 0x4000>;
+
+ interrupts = <GIC_SPI 584 IRQ_TYPE_LEVEL_HIGH>;
+
+ clocks = <&gcc GCC_QUPV3_WRAP2_S2_CLK>;
+ clock-names = "se";
+
+ interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS
+ &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>,
+ <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
+ &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>,
+ <&aggre2_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS
+ &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
+ interconnect-names = "qup-core",
+ "qup-config",
+ "qup-memory";
+
+ dmas = <&gpi_dma2 0 2 QCOM_GPI_SPI>,
+ <&gpi_dma2 1 2 QCOM_GPI_SPI>;
+ dma-names = "tx",
+ "rx";
+
+ pinctrl-0 = <&qup_spi10_data_clk>, <&qup_spi10_cs>;
+ pinctrl-names = "default";
+
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ status = "disabled";
+ };
+
+ i2c11: i2c@88c000 {
+ compatible = "qcom,geni-i2c";
+ reg = <0 0x0088c000 0 0x4000>;
+
+ interrupts = <GIC_SPI 585 IRQ_TYPE_LEVEL_HIGH>;
+
+ clocks = <&gcc GCC_QUPV3_WRAP2_S3_CLK>;
+ clock-names = "se";
+
+ interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS
+ &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>,
+ <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
+ &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>,
+ <&aggre2_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS
+ &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
+ interconnect-names = "qup-core",
+ "qup-config",
+ "qup-memory";
+
+ dmas = <&gpi_dma2 0 3 QCOM_GPI_I2C>,
+ <&gpi_dma2 1 3 QCOM_GPI_I2C>;
+ dma-names = "tx",
+ "rx";
+
+ pinctrl-0 = <&qup_i2c11_data_clk>;
+ pinctrl-names = "default";
+
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ status = "disabled";
+ };
+
+ spi11: spi@88c000 {
+ compatible = "qcom,geni-spi";
+ reg = <0 0x0088c000 0 0x4000>;
+
+ interrupts = <GIC_SPI 585 IRQ_TYPE_LEVEL_HIGH>;
+
+ clocks = <&gcc GCC_QUPV3_WRAP2_S3_CLK>;
+ clock-names = "se";
+
+ interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS
+ &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>,
+ <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
+ &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>,
+ <&aggre2_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS
+ &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
+ interconnect-names = "qup-core",
+ "qup-config",
+ "qup-memory";
+
+ dmas = <&gpi_dma2 0 3 QCOM_GPI_SPI>,
+ <&gpi_dma2 1 3 QCOM_GPI_SPI>;
+ dma-names = "tx",
+ "rx";
+
+ pinctrl-0 = <&qup_spi11_data_clk>, <&qup_spi11_cs>;
+ pinctrl-names = "default";
+
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ status = "disabled";
+ };
+
+ i2c12: i2c@890000 {
+ compatible = "qcom,geni-i2c";
+ reg = <0 0x00890000 0 0x4000>;
+
+ interrupts = <GIC_SPI 586 IRQ_TYPE_LEVEL_HIGH>;
+
+ clocks = <&gcc GCC_QUPV3_WRAP2_S4_CLK>;
+ clock-names = "se";
+
+ interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS
+ &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>,
+ <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
+ &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>,
+ <&aggre2_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS
+ &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
+ interconnect-names = "qup-core",
+ "qup-config",
+ "qup-memory";
+
+ dmas = <&gpi_dma2 0 4 QCOM_GPI_I2C>,
+ <&gpi_dma2 1 4 QCOM_GPI_I2C>;
+ dma-names = "tx",
+ "rx";
+
+ pinctrl-0 = <&qup_i2c12_data_clk>;
+ pinctrl-names = "default";
+
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ status = "disabled";
+ };
+
+ spi12: spi@890000 {
+ compatible = "qcom,geni-spi";
+ reg = <0 0x00890000 0 0x4000>;
+
+ interrupts = <GIC_SPI 586 IRQ_TYPE_LEVEL_HIGH>;
+
+ clocks = <&gcc GCC_QUPV3_WRAP2_S4_CLK>;
+ clock-names = "se";
+
+ interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS
+ &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>,
+ <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
+ &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>,
+ <&aggre2_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS
+ &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
+ interconnect-names = "qup-core",
+ "qup-config",
+ "qup-memory";
+
+ dmas = <&gpi_dma2 0 4 QCOM_GPI_SPI>,
+ <&gpi_dma2 1 4 QCOM_GPI_SPI>;
+ dma-names = "tx",
+ "rx";
+
+ pinctrl-0 = <&qup_spi12_data_clk>, <&qup_spi12_cs>;
+ pinctrl-names = "default";
+
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ status = "disabled";
+ };
+
+ i2c13: i2c@894000 {
+ compatible = "qcom,geni-i2c";
+ reg = <0 0x00894000 0 0x4000>;
+
+ interrupts = <GIC_SPI 587 IRQ_TYPE_LEVEL_HIGH>;
+
+ clocks = <&gcc GCC_QUPV3_WRAP2_S5_CLK>;
+ clock-names = "se";
+
+ interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS
+ &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>,
+ <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
+ &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>,
+ <&aggre2_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS
+ &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
+ interconnect-names = "qup-core",
+ "qup-config",
+ "qup-memory";
+
+ dmas = <&gpi_dma2 0 5 QCOM_GPI_I2C>,
+ <&gpi_dma2 1 5 QCOM_GPI_I2C>;
+ dma-names = "tx",
+ "rx";
+
+ pinctrl-0 = <&qup_i2c13_data_clk>;
+ pinctrl-names = "default";
+
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ status = "disabled";
+ };
+
+ spi13: spi@894000 {
+ compatible = "qcom,geni-spi";
+ reg = <0 0x00894000 0 0x4000>;
+
+ interrupts = <GIC_SPI 587 IRQ_TYPE_LEVEL_HIGH>;
+
+ clocks = <&gcc GCC_QUPV3_WRAP2_S5_CLK>;
+ clock-names = "se";
+
+ interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS
+ &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>,
+ <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
+ &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>,
+ <&aggre2_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS
+ &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
+ interconnect-names = "qup-core",
+ "qup-config",
+ "qup-memory";
+
+ dmas = <&gpi_dma2 0 5 QCOM_GPI_SPI>,
+ <&gpi_dma2 1 5 QCOM_GPI_SPI>;
+ dma-names = "tx",
+ "rx";
+
+ pinctrl-0 = <&qup_spi13_data_clk>, <&qup_spi13_cs>;
+ pinctrl-names = "default";
+
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ status = "disabled";
+ };
+
+ uart14: serial@898000 {
+ compatible = "qcom,geni-uart";
+ reg = <0 0x00898000 0 0x4000>;
+
+ interrupts = <GIC_SPI 461 IRQ_TYPE_LEVEL_HIGH>;
+
+ clocks = <&gcc GCC_QUPV3_WRAP2_S6_CLK>;
+ clock-names = "se";
+
+ interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS
+ &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>,
+ <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
+ &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>;
+ interconnect-names = "qup-core",
+ "qup-config";
+
+ pinctrl-0 = <&qup_uart14_default>, <&qup_uart14_cts_rts>;
+ pinctrl-names = "default";
+
+ status = "disabled";
+ };
+
+ uart15: serial@89c000 {
+ compatible = "qcom,geni-debug-uart";
+ reg = <0 0x0089c000 0 0x4000>;
+
+ interrupts = <GIC_SPI 462 IRQ_TYPE_LEVEL_HIGH>;
+
+ clocks = <&gcc GCC_QUPV3_WRAP2_S7_CLK>;
+ clock-names = "se";
+
+ interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS
+ &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>,
+ <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
+ &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>;
+ interconnect-names = "qup-core",
+ "qup-config";
+
+ pinctrl-0 = <&qup_uart15_default>;
+ pinctrl-names = "default";
+
+ status = "disabled";
+ };
+ };
+
+ i2c_master_hub_0: geniqup@9c0000 {
+ compatible = "qcom,geni-se-i2c-master-hub";
+ reg = <0 0x009c0000 0 0x2000>;
+
+ clocks = <&gcc GCC_QUPV3_I2C_S_AHB_CLK>;
+ clock-names = "s-ahb";
+
+ #address-cells = <2>;
+ #size-cells = <2>;
+ ranges;
+
+ status = "disabled";
+
+ i2c_hub_0: i2c@980000 {
+ compatible = "qcom,geni-i2c-master-hub";
+ reg = <0 0x00980000 0 0x4000>;
+
+ interrupts = <GIC_SPI 464 IRQ_TYPE_LEVEL_HIGH>;
+
+ clocks = <&gcc GCC_QUPV3_I2C_S0_CLK>,
+ <&gcc GCC_QUPV3_I2C_CORE_CLK>;
+ clock-names = "se",
+ "core";
+
+ interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS
+ &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>,
+ <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
+ &config_noc SLAVE_I2C QCOM_ICC_TAG_ALWAYS>;
+ interconnect-names = "qup-core",
+ "qup-config";
+
+ pinctrl-0 = <&hub_i2c0_data_clk>;
+ pinctrl-names = "default";
+
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ status = "disabled";
+ };
+
+ i2c_hub_1: i2c@984000 {
+ compatible = "qcom,geni-i2c-master-hub";
+ reg = <0 0x00984000 0 0x4000>;
+
+ interrupts = <GIC_SPI 465 IRQ_TYPE_LEVEL_HIGH>;
+
+ clocks = <&gcc GCC_QUPV3_I2C_S1_CLK>,
+ <&gcc GCC_QUPV3_I2C_CORE_CLK>;
+ clock-names = "se",
+ "core";
+
+ interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS
+ &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>,
+ <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
+ &config_noc SLAVE_I2C QCOM_ICC_TAG_ALWAYS>;
+ interconnect-names = "qup-core",
+ "qup-config";
+
+ pinctrl-0 = <&hub_i2c1_data_clk>;
+ pinctrl-names = "default";
+
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ status = "disabled";
+ };
+
+ i2c_hub_2: i2c@988000 {
+ compatible = "qcom,geni-i2c-master-hub";
+ reg = <0 0x00988000 0 0x4000>;
+
+ interrupts = <GIC_SPI 466 IRQ_TYPE_LEVEL_HIGH>;
+
+ clocks = <&gcc GCC_QUPV3_I2C_S2_CLK>,
+ <&gcc GCC_QUPV3_I2C_CORE_CLK>;
+ clock-names = "se",
+ "core";
+
+ interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS
+ &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>,
+ <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
+ &config_noc SLAVE_I2C QCOM_ICC_TAG_ALWAYS>;
+ interconnect-names = "qup-core",
+ "qup-config";
+
+ pinctrl-0 = <&hub_i2c2_data_clk>;
+ pinctrl-names = "default";
+
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ status = "disabled";
+ };
+
+ i2c_hub_3: i2c@98c000 {
+ compatible = "qcom,geni-i2c-master-hub";
+ reg = <0 0x0098c000 0 0x4000>;
+
+ interrupts = <GIC_SPI 467 IRQ_TYPE_LEVEL_HIGH>;
+
+ clocks = <&gcc GCC_QUPV3_I2C_S3_CLK>,
+ <&gcc GCC_QUPV3_I2C_CORE_CLK>;
+ clock-names = "se",
+ "core";
+
+ interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS
+ &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>,
+ <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
+ &config_noc SLAVE_I2C QCOM_ICC_TAG_ALWAYS>;
+ interconnect-names = "qup-core",
+ "qup-config";
+
+ pinctrl-0 = <&hub_i2c3_data_clk>;
+ pinctrl-names = "default";
+
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ status = "disabled";
+ };
+
+ i2c_hub_4: i2c@990000 {
+ compatible = "qcom,geni-i2c-master-hub";
+ reg = <0 0x00990000 0 0x4000>;
+
+ interrupts = <GIC_SPI 468 IRQ_TYPE_LEVEL_HIGH>;
+
+ clocks = <&gcc GCC_QUPV3_I2C_S4_CLK>,
+ <&gcc GCC_QUPV3_I2C_CORE_CLK>;
+ clock-names = "se",
+ "core";
+
+ interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS
+ &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>,
+ <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
+ &config_noc SLAVE_I2C QCOM_ICC_TAG_ALWAYS>;
+ interconnect-names = "qup-core",
+ "qup-config";
+
+ pinctrl-0 = <&hub_i2c4_data_clk>;
+ pinctrl-names = "default";
+
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ status = "disabled";
+ };
+
+ i2c_hub_5: i2c@994000 {
+ compatible = "qcom,geni-i2c-master-hub";
+ reg = <0 0x00994000 0 0x4000>;
+
+ interrupts = <GIC_SPI 469 IRQ_TYPE_LEVEL_HIGH>;
+
+ clocks = <&gcc GCC_QUPV3_I2C_S5_CLK>,
+ <&gcc GCC_QUPV3_I2C_CORE_CLK>;
+ clock-names = "se",
+ "core";
+
+ interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS
+ &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>,
+ <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
+ &config_noc SLAVE_I2C QCOM_ICC_TAG_ALWAYS>;
+ interconnect-names = "qup-core",
+ "qup-config";
+
+ pinctrl-0 = <&hub_i2c5_data_clk>;
+ pinctrl-names = "default";
+
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ status = "disabled";
+ };
+
+ i2c_hub_6: i2c@998000 {
+ compatible = "qcom,geni-i2c-master-hub";
+ reg = <0 0x00998000 0 0x4000>;
+
+ interrupts = <GIC_SPI 470 IRQ_TYPE_LEVEL_HIGH>;
+
+ clocks = <&gcc GCC_QUPV3_I2C_S6_CLK>,
+ <&gcc GCC_QUPV3_I2C_CORE_CLK>;
+ clock-names = "se",
+ "core";
+
+ interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS
+ &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>,
+ <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
+ &config_noc SLAVE_I2C QCOM_ICC_TAG_ALWAYS>;
+ interconnect-names = "qup-core",
+ "qup-config";
+
+ pinctrl-0 = <&hub_i2c6_data_clk>;
+ pinctrl-names = "default";
+
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ status = "disabled";
+ };
+
+ i2c_hub_7: i2c@99c000 {
+ compatible = "qcom,geni-i2c-master-hub";
+ reg = <0 0x0099c000 0 0x4000>;
+
+ interrupts = <GIC_SPI 471 IRQ_TYPE_LEVEL_HIGH>;
+
+ clocks = <&gcc GCC_QUPV3_I2C_S7_CLK>,
+ <&gcc GCC_QUPV3_I2C_CORE_CLK>;
+ clock-names = "se",
+ "core";
+
+ interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS
+ &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>,
+ <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
+ &config_noc SLAVE_I2C QCOM_ICC_TAG_ALWAYS>;
+ interconnect-names = "qup-core",
+ "qup-config";
+
+ pinctrl-0 = <&hub_i2c7_data_clk>;
+ pinctrl-names = "default";
+
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ status = "disabled";
+ };
+
+ i2c_hub_8: i2c@9a0000 {
+ compatible = "qcom,geni-i2c-master-hub";
+ reg = <0 0x009a0000 0 0x4000>;
+
+ interrupts = <GIC_SPI 472 IRQ_TYPE_LEVEL_HIGH>;
+
+ clocks = <&gcc GCC_QUPV3_I2C_S8_CLK>,
+ <&gcc GCC_QUPV3_I2C_CORE_CLK>;
+ clock-names = "se",
+ "core";
+
+ interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS
+ &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>,
+ <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
+ &config_noc SLAVE_I2C QCOM_ICC_TAG_ALWAYS>;
+ interconnect-names = "qup-core",
+ "qup-config";
+
+ pinctrl-0 = <&hub_i2c8_data_clk>;
+ pinctrl-names = "default";
+
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ status = "disabled";
+ };
+
+ i2c_hub_9: i2c@9a4000 {
+ compatible = "qcom,geni-i2c-master-hub";
+ reg = <0 0x009a4000 0 0x4000>;
+
+ interrupts = <GIC_SPI 473 IRQ_TYPE_LEVEL_HIGH>;
+
+ clocks = <&gcc GCC_QUPV3_I2C_S9_CLK>,
+ <&gcc GCC_QUPV3_I2C_CORE_CLK>;
+ clock-names = "se",
+ "core";
+
+ interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS
+ &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>,
+ <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
+ &config_noc SLAVE_I2C QCOM_ICC_TAG_ALWAYS>;
+ interconnect-names = "qup-core",
+ "qup-config";
+
+ pinctrl-0 = <&hub_i2c9_data_clk>;
+ pinctrl-names = "default";
+
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ status = "disabled";
+ };
+ };
+
+ gpi_dma1: dma-controller@a00000 {
+ compatible = "qcom,sm8650-gpi-dma", "qcom,sm6350-gpi-dma";
+ reg = <0 0x00a00000 0 0x60000>;
+
+ interrupts = <GIC_SPI 279 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 280 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 281 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 282 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 283 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 284 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 293 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 294 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 295 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 296 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 297 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 298 IRQ_TYPE_LEVEL_HIGH>;
+
+ dma-channels = <12>;
+ dma-channel-mask = <0xc>;
+ #dma-cells = <3>;
+
+ iommus = <&apps_smmu 0xb6 0>;
+ dma-coherent;
+
+ status = "disabled";
+ };
+
+ qupv3_id_0: geniqup@ac0000 {
+ compatible = "qcom,geni-se-qup";
+ reg = <0 0x00ac0000 0 0x2000>;
+
+ clocks = <&gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>,
+ <&gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>;
+ clock-names = "m-ahb",
+ "s-ahb";
+
+ interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS
+ &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>;
+ interconnect-names = "qup-core";
+
+ iommus = <&apps_smmu 0xa3 0>;
+
+ dma-coherent;
+
+ #address-cells = <2>;
+ #size-cells = <2>;
+ ranges;
+
+ status = "disabled";
+
+ i2c0: i2c@a80000 {
+ compatible = "qcom,geni-i2c";
+ reg = <0 0x00a80000 0 0x4000>;
+
+ interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>;
+
+ clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>;
+ clock-names = "se";
+
+ interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS
+ &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>,
+ <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
+ &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>,
+ <&aggre1_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS
+ &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
+ interconnect-names = "qup-core",
+ "qup-config",
+ "qup-memory";
+
+ dmas = <&gpi_dma1 0 0 QCOM_GPI_I2C>,
+ <&gpi_dma1 1 0 QCOM_GPI_I2C>;
+ dma-names = "tx",
+ "rx";
+
+ pinctrl-0 = <&qup_i2c0_data_clk>;
+ pinctrl-names = "default";
+
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ status = "disabled";
+ };
+
+ spi0: spi@a80000 {
+ compatible = "qcom,geni-spi";
+ reg = <0 0x00a80000 0 0x4000>;
+
+ interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>;
+
+ clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>;
+ clock-names = "se";
+
+ interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS
+ &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>,
+ <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
+ &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>,
+ <&aggre1_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS
+ &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
+ interconnect-names = "qup-core",
+ "qup-config",
+ "qup-memory";
+
+ dmas = <&gpi_dma1 0 0 QCOM_GPI_SPI>,
+ <&gpi_dma1 1 0 QCOM_GPI_SPI>;
+ dma-names = "tx",
+ "rx";
+
+ pinctrl-0 = <&qup_spi0_data_clk>, <&qup_spi0_cs>;
+ pinctrl-names = "default";
+
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ status = "disabled";
+ };
+
+ i2c1: i2c@a84000 {
+ compatible = "qcom,geni-i2c";
+ reg = <0 0x00a84000 0 0x4000>;
+
+ interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>;
+
+ clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>;
+ clock-names = "se";
+
+ interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS
+ &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>,
+ <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
+ &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>,
+ <&aggre1_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS
+ &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
+ interconnect-names = "qup-core",
+ "qup-config",
+ "qup-memory";
+
+ dmas = <&gpi_dma1 0 1 QCOM_GPI_I2C>,
+ <&gpi_dma1 1 1 QCOM_GPI_I2C>;
+ dma-names = "tx",
+ "rx";
+
+ pinctrl-0 = <&qup_i2c1_data_clk>;
+ pinctrl-names = "default";
+
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ status = "disabled";
+ };
+
+ spi1: spi@a84000 {
+ compatible = "qcom,geni-spi";
+ reg = <0 0x00a84000 0 0x4000>;
+
+ interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>;
+
+ clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>;
+ clock-names = "se";
+
+ interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS
+ &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>,
+ <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
+ &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>,
+ <&aggre1_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS
+ &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
+ interconnect-names = "qup-core",
+ "qup-config",
+ "qup-memory";
+
+ dmas = <&gpi_dma1 0 1 QCOM_GPI_SPI>,
+ <&gpi_dma1 1 1 QCOM_GPI_SPI>;
+ dma-names = "tx",
+ "rx";
+
+ pinctrl-0 = <&qup_spi1_data_clk>, <&qup_spi1_cs>;
+ pinctrl-names = "default";
+
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ status = "disabled";
+ };
+
+ i2c2: i2c@a88000 {
+ compatible = "qcom,geni-i2c";
+ reg = <0 0x00a88000 0 0x4000>;
+
+ interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>;
+
+ clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>;
+ clock-names = "se";
+
+ interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS
+ &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>,
+ <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
+ &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>,
+ <&aggre1_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS
+ &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
+ interconnect-names = "qup-core",
+ "qup-config",
+ "qup-memory";
+
+ dmas = <&gpi_dma1 0 2 QCOM_GPI_I2C>,
+ <&gpi_dma1 1 2 QCOM_GPI_I2C>;
+ dma-names = "tx",
+ "rx";
+
+ pinctrl-0 = <&qup_i2c2_data_clk>;
+ pinctrl-names = "default";
+
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ status = "disabled";
+ };
+
+ spi2: spi@a88000 {
+ compatible = "qcom,geni-spi";
+ reg = <0 0x00a88000 0 0x4000>;
+
+ interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>;
+
+ clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>;
+ clock-names = "se";
+
+ interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS
+ &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>,
+ <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
+ &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>,
+ <&aggre1_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS
+ &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
+ interconnect-names = "qup-core",
+ "qup-config",
+ "qup-memory";
+
+ dmas = <&gpi_dma1 0 2 QCOM_GPI_SPI>,
+ <&gpi_dma1 1 2 QCOM_GPI_SPI>;
+ dma-names = "tx",
+ "rx";
+
+ pinctrl-0 = <&qup_spi2_data_clk>, <&qup_spi2_cs>;
+ pinctrl-names = "default";
+
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ status = "disabled";
+ };
+
+ i2c3: i2c@a8c000 {
+ compatible = "qcom,geni-i2c";
+ reg = <0 0x00a8c000 0 0x4000>;
+
+ interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>;
+
+ clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>;
+ clock-names = "se";
+
+ interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS
+ &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>,
+ <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
+ &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>,
+ <&aggre1_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS
+ &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
+ interconnect-names = "qup-core",
+ "qup-config",
+ "qup-memory";
+
+ dmas = <&gpi_dma1 0 3 QCOM_GPI_I2C>,
+ <&gpi_dma1 1 3 QCOM_GPI_I2C>;
+ dma-names = "tx",
+ "rx";
+
+ pinctrl-0 = <&qup_i2c3_data_clk>;
+ pinctrl-names = "default";
+
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ status = "disabled";
+ };
+
+ spi3: spi@a8c000 {
+ compatible = "qcom,geni-spi";
+ reg = <0 0x00a8c000 0 0x4000>;
+
+ interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>;
+
+ clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>;
+ clock-names = "se";
+
+ interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS
+ &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>,
+ <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
+ &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>,
+ <&aggre1_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS
+ &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
+ interconnect-names = "qup-core",
+ "qup-config",
+ "qup-memory";
+
+ dmas = <&gpi_dma1 0 3 QCOM_GPI_SPI>,
+ <&gpi_dma1 1 3 QCOM_GPI_SPI>;
+ dma-names = "tx",
+ "rx";
+
+ pinctrl-0 = <&qup_spi3_data_clk>, <&qup_spi3_cs>;
+ pinctrl-names = "default";
+
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ status = "disabled";
+ };
+
+ i2c4: i2c@a90000 {
+ compatible = "qcom,geni-i2c";
+ reg = <0 0x00a90000 0 0x4000>;
+
+ interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>;
+
+ clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>;
+ clock-names = "se";
+
+ interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS
+ &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>,
+ <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
+ &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>,
+ <&aggre1_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS
+ &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
+ interconnect-names = "qup-core",
+ "qup-config",
+ "qup-memory";
+
+ dmas = <&gpi_dma1 0 4 QCOM_GPI_I2C>,
+ <&gpi_dma1 1 4 QCOM_GPI_I2C>;
+ dma-names = "tx",
+ "rx";
+
+ pinctrl-0 = <&qup_i2c4_data_clk>;
+ pinctrl-names = "default";
+
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ status = "disabled";
+ };
+
+ spi4: spi@a90000 {
+ compatible = "qcom,geni-spi";
+ reg = <0 0x00a90000 0 0x4000>;
+
+ interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>;
+
+ clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>;
+ clock-names = "se";
+
+ interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS
+ &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>,
+ <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
+ &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>,
+ <&aggre1_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS
+ &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
+ interconnect-names = "qup-core",
+ "qup-config",
+ "qup-memory";
+
+ dmas = <&gpi_dma1 0 4 QCOM_GPI_SPI>,
+ <&gpi_dma1 1 4 QCOM_GPI_SPI>;
+ dma-names = "tx",
+ "rx";
+
+ pinctrl-0 = <&qup_spi4_data_clk>, <&qup_spi4_cs>;
+ pinctrl-names = "default";
+
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ status = "disabled";
+ };
+
+ i2c5: i2c@a94000 {
+ compatible = "qcom,geni-i2c";
+ reg = <0 0x00a94000 0 0x4000>;
+
+ interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>;
+
+ clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>;
+ clock-names = "se";
+
+ interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS
+ &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>,
+ <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
+ &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>,
+ <&aggre1_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS
+ &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
+ interconnect-names = "qup-core",
+ "qup-config",
+ "qup-memory";
+
+ dmas = <&gpi_dma1 0 5 QCOM_GPI_I2C>,
+ <&gpi_dma1 1 5 QCOM_GPI_I2C>;
+ dma-names = "tx",
+ "rx";
+
+ pinctrl-0 = <&qup_i2c5_data_clk>;
+ pinctrl-names = "default";
+
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ status = "disabled";
+ };
+
+ spi5: spi@a94000 {
+ compatible = "qcom,geni-spi";
+ reg = <0 0x00a94000 0 0x4000>;
+
+ interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>;
+
+ clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>;
+ clock-names = "se";
+
+ interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS
+ &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>,
+ <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
+ &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>,
+ <&aggre1_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS
+ &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
+ interconnect-names = "qup-core",
+ "qup-config",
+ "qup-memory";
+
+ dmas = <&gpi_dma1 0 5 QCOM_GPI_SPI>,
+ <&gpi_dma1 1 5 QCOM_GPI_SPI>;
+ dma-names = "tx",
+ "rx";
+
+ pinctrl-0 = <&qup_spi5_data_clk>, <&qup_spi5_cs>;
+ pinctrl-names = "default";
+
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ status = "disabled";
+ };
+
+ i2c6: i2c@a98000 {
+ compatible = "qcom,geni-i2c";
+ reg = <0 0x00a98000 0 0x4000>;
+
+ interrupts = <GIC_SPI 363 IRQ_TYPE_LEVEL_HIGH>;
+
+ clocks = <&gcc GCC_QUPV3_WRAP1_S6_CLK>;
+ clock-names = "se";
+
+ interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS
+ &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>,
+ <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
+ &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>,
+ <&aggre1_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS
+ &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
+ interconnect-names = "qup-core",
+ "qup-config",
+ "qup-memory";
+
+ dmas = <&gpi_dma1 0 6 QCOM_GPI_I2C>,
+ <&gpi_dma1 1 6 QCOM_GPI_I2C>;
+ dma-names = "tx",
+ "rx";
+
+ pinctrl-0 = <&qup_i2c6_data_clk>;
+ pinctrl-names = "default";
+
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ status = "disabled";
+ };
+
+ spi6: spi@a98000 {
+ compatible = "qcom,geni-spi";
+ reg = <0 0x00a98000 0 0x4000>;
+
+ interrupts = <GIC_SPI 363 IRQ_TYPE_LEVEL_HIGH>;
+
+ clocks = <&gcc GCC_QUPV3_WRAP1_S6_CLK>;
+ clock-names = "se";
+
+ interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS
+ &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>,
+ <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
+ &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>,
+ <&aggre1_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS
+ &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
+ interconnect-names = "qup-core",
+ "qup-config",
+ "qup-memory";
+
+ dmas = <&gpi_dma1 0 6 QCOM_GPI_SPI>,
+ <&gpi_dma1 1 6 QCOM_GPI_SPI>;
+ dma-names = "tx",
+ "rx";
+
+ pinctrl-0 = <&qup_spi6_data_clk>, <&qup_spi6_cs>;
+ pinctrl-names = "default";
+
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ status = "disabled";
+ };
+
+ i2c7: i2c@a9c000 {
+ compatible = "qcom,geni-i2c";
+ reg = <0 0x00a9c000 0 0x4000>;
+
+ interrupts = <GIC_SPI 579 IRQ_TYPE_LEVEL_HIGH>;
+
+ clocks = <&gcc GCC_QUPV3_WRAP1_S7_CLK>;
+ clock-names = "se";
+
+ interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS
+ &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>,
+ <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
+ &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>,
+ <&aggre1_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS
+ &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
+ interconnect-names = "qup-core",
+ "qup-config",
+ "qup-memory";
+
+ dmas = <&gpi_dma1 0 7 QCOM_GPI_I2C>,
+ <&gpi_dma1 1 7 QCOM_GPI_I2C>;
+ dma-names = "tx",
+ "rx";
+
+ pinctrl-0 = <&qup_i2c7_data_clk>;
+ pinctrl-names = "default";
+
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ status = "disabled";
+ };
+
+ spi7: spi@a9c000 {
+ compatible = "qcom,geni-spi";
+ reg = <0 0x00a9c000 0 0x4000>;
+
+ interrupts = <GIC_SPI 579 IRQ_TYPE_LEVEL_HIGH>;
+
+ clocks = <&gcc GCC_QUPV3_WRAP1_S7_CLK>;
+ clock-names = "se";
+
+ interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS
+ &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>,
+ <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
+ &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>,
+ <&aggre1_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS
+ &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
+ interconnect-names = "qup-core",
+ "qup-config",
+ "qup-memory";
+
+ dmas = <&gpi_dma1 0 7 QCOM_GPI_SPI>,
+ <&gpi_dma1 1 7 QCOM_GPI_SPI>;
+ dma-names = "tx",
+ "rx";
+
+ pinctrl-0 = <&qup_spi7_data_clk>, <&qup_spi7_cs>;
+ pinctrl-names = "default";
+
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ status = "disabled";
+ };
+ };
+
+ cnoc_main: interconnect@1500000 {
+ compatible = "qcom,sm8650-cnoc-main";
+ reg = <0 0x01500000 0 0x14080>;
+
+ qcom,bcm-voters = <&apps_bcm_voter>;
+
+ #interconnect-cells = <2>;
+ };
+
+ config_noc: interconnect@1600000 {
+ compatible = "qcom,sm8650-config-noc";
+ reg = <0 0x01600000 0 0x6200>;
+
+ qcom,bcm-voters = <&apps_bcm_voter>;
+
+ #interconnect-cells = <2>;
+ };
+
+ system_noc: interconnect@1680000 {
+ compatible = "qcom,sm8650-system-noc";
+ reg = <0 0x01680000 0 0x1d080>;
+
+ qcom,bcm-voters = <&apps_bcm_voter>;
+
+ #interconnect-cells = <2>;
+ };
+
+ pcie_noc: interconnect@16c0000 {
+ compatible = "qcom,sm8650-pcie-anoc";
+ reg = <0 0x016c0000 0 0x12200>;
+
+ clocks = <&gcc GCC_AGGRE_NOC_PCIE_AXI_CLK>,
+ <&gcc GCC_CFG_NOC_PCIE_ANOC_AHB_CLK>;
+
+ qcom,bcm-voters = <&apps_bcm_voter>;
+
+ #interconnect-cells = <2>;
+ };
+
+ aggre1_noc: interconnect@16e0000 {
+ compatible = "qcom,sm8650-aggre1-noc";
+ reg = <0 0x016e0000 0 0x16400>;
+
+ clocks = <&gcc GCC_AGGRE_UFS_PHY_AXI_CLK>,
+ <&gcc GCC_AGGRE_USB3_PRIM_AXI_CLK>;
+
+ qcom,bcm-voters = <&apps_bcm_voter>;
+
+ #interconnect-cells = <2>;
+ };
+
+ aggre2_noc: interconnect@1700000 {
+ compatible = "qcom,sm8650-aggre2-noc";
+ reg = <0 0x01700000 0 0x1e400>;
+
+ clocks = <&rpmhcc RPMH_IPA_CLK>;
+
+ qcom,bcm-voters = <&apps_bcm_voter>;
+
+ #interconnect-cells = <2>;
+ };
+
+ mmss_noc: interconnect@1780000 {
+ compatible = "qcom,sm8650-mmss-noc";
+ reg = <0 0x01780000 0 0x5b800>;
+
+ qcom,bcm-voters = <&apps_bcm_voter>;
+
+ #interconnect-cells = <2>;
+ };
+
+ rng: rng@10c3000 {
+ compatible = "qcom,sm8650-trng", "qcom,trng";
+ reg = <0 0x010c3000 0 0x1000>;
+ };
+
+ pcie0: pci@1c00000 {
+ device_type = "pci";
+ compatible = "qcom,pcie-sm8650", "qcom,pcie-sm8550";
+ reg = <0 0x01c00000 0 0x3000>,
+ <0 0x60000000 0 0xf1d>,
+ <0 0x60000f20 0 0xa8>,
+ <0 0x60001000 0 0x1000>,
+ <0 0x60100000 0 0x100000>;
+ reg-names = "parf", "dbi", "elbi", "atu", "config";
+
+ interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "msi";
+
+ clocks = <&gcc GCC_PCIE_0_AUX_CLK>,
+ <&gcc GCC_PCIE_0_CFG_AHB_CLK>,
+ <&gcc GCC_PCIE_0_MSTR_AXI_CLK>,
+ <&gcc GCC_PCIE_0_SLV_AXI_CLK>,
+ <&gcc GCC_PCIE_0_SLV_Q2A_AXI_CLK>,
+ <&gcc GCC_DDRSS_PCIE_SF_QTB_CLK>,
+ <&gcc GCC_AGGRE_NOC_PCIE_AXI_CLK>,
+ <&gcc GCC_CNOC_PCIE_SF_AXI_CLK>;
+ clock-names = "aux",
+ "cfg",
+ "bus_master",
+ "bus_slave",
+ "slave_q2a",
+ "ddrss_sf_tbu",
+ "noc_aggr",
+ "cnoc_sf_axi";
+
+ resets = <&gcc GCC_PCIE_0_BCR>;
+ reset-names = "pci";
+
+ interconnects = <&pcie_noc MASTER_PCIE_0 QCOM_ICC_TAG_ALWAYS
+ &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>,
+ <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
+ &cnoc_main SLAVE_PCIE_0 QCOM_ICC_TAG_ALWAYS>;
+ interconnect-names = "pcie-mem",
+ "cpu-pcie";
+
+ power-domains = <&gcc PCIE_0_GDSC>;
+
+ iommu-map = <0 &apps_smmu 0x1400 0x1>,
+ <0x100 &apps_smmu 0x1401 0x1>;
+
+ interrupt-map = <0 0 0 1 &intc 0 0 0 149 IRQ_TYPE_LEVEL_HIGH>,
+ <0 0 0 2 &intc 0 0 0 150 IRQ_TYPE_LEVEL_HIGH>,
+ <0 0 0 3 &intc 0 0 0 151 IRQ_TYPE_LEVEL_HIGH>,
+ <0 0 0 4 &intc 0 0 0 152 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-map-mask = <0 0 0 0x7>;
+ #interrupt-cells = <1>;
+
+ linux,pci-domain = <0>;
+ num-lanes = <2>;
+ bus-range = <0 0xff>;
+
+ phys = <&pcie0_phy>;
+ phy-names = "pciephy";
+
+ #address-cells = <3>;
+ #size-cells = <2>;
+ ranges = <0x01000000 0 0x00000000 0 0x60200000 0 0x100000>,
+ <0x02000000 0 0x60300000 0 0x60300000 0 0x3d00000>;
+
+ dma-coherent;
+
+ status = "disabled";
+ };
+
+ pcie0_phy: phy@1c06000 {
+ compatible = "qcom,sm8650-qmp-gen3x2-pcie-phy";
+ reg = <0 0x01c06000 0 0x2000>;
+
+ clocks = <&gcc GCC_PCIE_0_AUX_CLK>,
+ <&gcc GCC_PCIE_0_CFG_AHB_CLK>,
+ <&tcsr TCSR_PCIE_0_CLKREF_EN>,
+ <&gcc GCC_PCIE_0_PHY_RCHNG_CLK>,
+ <&gcc GCC_PCIE_0_PIPE_CLK>;
+ clock-names = "aux",
+ "cfg_ahb",
+ "ref",
+ "rchng",
+ "pipe";
+
+ assigned-clocks = <&gcc GCC_PCIE_0_PHY_RCHNG_CLK>;
+ assigned-clock-rates = <100000000>;
+
+ resets = <&gcc GCC_PCIE_0_PHY_BCR>;
+ reset-names = "phy";
+
+ power-domains = <&gcc PCIE_0_PHY_GDSC>;
+
+ #clock-cells = <0>;
+ clock-output-names = "pcie0_pipe_clk";
+
+ #phy-cells = <0>;
+
+ status = "disabled";
+ };
+
+ pcie1: pci@1c08000 {
+ device_type = "pci";
+ compatible = "qcom,pcie-sm8650", "qcom,pcie-sm8550";
+ reg = <0 0x01c08000 0 0x3000>,
+ <0 0x40000000 0 0xf1d>,
+ <0 0x40000f20 0 0xa8>,
+ <0 0x40001000 0 0x1000>,
+ <0 0x40100000 0 0x100000>;
+ reg-names = "parf",
+ "dbi",
+ "elbi",
+ "atu",
+ "config";
+
+ interrupts = <GIC_SPI 307 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "msi";
+
+ clocks = <&gcc GCC_PCIE_1_AUX_CLK>,
+ <&gcc GCC_PCIE_1_CFG_AHB_CLK>,
+ <&gcc GCC_PCIE_1_MSTR_AXI_CLK>,
+ <&gcc GCC_PCIE_1_SLV_AXI_CLK>,
+ <&gcc GCC_PCIE_1_SLV_Q2A_AXI_CLK>,
+ <&gcc GCC_DDRSS_PCIE_SF_QTB_CLK>,
+ <&gcc GCC_AGGRE_NOC_PCIE_AXI_CLK>,
+ <&gcc GCC_CNOC_PCIE_SF_AXI_CLK>;
+ clock-names = "aux",
+ "cfg",
+ "bus_master",
+ "bus_slave",
+ "slave_q2a",
+ "ddrss_sf_tbu",
+ "noc_aggr",
+ "cnoc_sf_axi";
+
+ assigned-clocks = <&gcc GCC_PCIE_1_AUX_CLK>;
+ assigned-clock-rates = <19200000>;
+
+ resets = <&gcc GCC_PCIE_1_BCR>,
+ <&gcc GCC_PCIE_1_LINK_DOWN_BCR>;
+ reset-names = "pci",
+ "link_down";
+
+ interconnects = <&pcie_noc MASTER_PCIE_1 QCOM_ICC_TAG_ALWAYS
+ &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>,
+ <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
+ &cnoc_main SLAVE_PCIE_1 QCOM_ICC_TAG_ALWAYS>;
+ interconnect-names = "pcie-mem",
+ "cpu-pcie";
+
+ power-domains = <&gcc PCIE_1_GDSC>;
+
+ iommu-map = <0 &apps_smmu 0x1480 0x1>,
+ <0x100 &apps_smmu 0x1481 0x1>;
+
+ interrupt-map = <0 0 0 1 &intc 0 0 0 434 IRQ_TYPE_LEVEL_HIGH>,
+ <0 0 0 2 &intc 0 0 0 435 IRQ_TYPE_LEVEL_HIGH>,
+ <0 0 0 3 &intc 0 0 0 438 IRQ_TYPE_LEVEL_HIGH>,
+ <0 0 0 4 &intc 0 0 0 439 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-map-mask = <0 0 0 0x7>;
+ #interrupt-cells = <1>;
+
+ linux,pci-domain = <1>;
+ num-lanes = <2>;
+ bus-range = <0 0xff>;
+
+ phys = <&pcie1_phy>;
+ phy-names = "pciephy";
+
+ dma-coherent;
+
+ #address-cells = <3>;
+ #size-cells = <2>;
+ ranges = <0x01000000 0 0x00000000 0 0x40200000 0 0x100000>,
+ <0x02000000 0 0x40300000 0 0x40300000 0 0x1fd00000>;
+
+ status = "disabled";
+ };
+
+ pcie1_phy: phy@1c0e000 {
+ compatible = "qcom,sm8650-qmp-gen4x2-pcie-phy";
+ reg = <0 0x01c0e000 0 0x2000>;
+
+ clocks = <&gcc GCC_PCIE_1_PHY_AUX_CLK>,
+ <&gcc GCC_PCIE_1_CFG_AHB_CLK>,
+ <&tcsr TCSR_PCIE_1_CLKREF_EN>,
+ <&gcc GCC_PCIE_1_PHY_RCHNG_CLK>,
+ <&gcc GCC_PCIE_1_PIPE_CLK>;
+ clock-names = "aux",
+ "cfg_ahb",
+ "ref",
+ "rchng",
+ "pipe";
+
+ assigned-clocks = <&gcc GCC_PCIE_1_PHY_RCHNG_CLK>;
+ assigned-clock-rates = <100000000>;
+
+ resets = <&gcc GCC_PCIE_1_PHY_BCR>,
+ <&gcc GCC_PCIE_1_NOCSR_COM_PHY_BCR>;
+ reset-names = "phy",
+ "phy_nocsr";
+
+ power-domains = <&gcc PCIE_1_PHY_GDSC>;
+
+ #clock-cells = <0>;
+ clock-output-names = "pcie1_pipe_clk";
+
+ #phy-cells = <0>;
+
+ status = "disabled";
+ };
+
+ cryptobam: dma-controller@1dc4000 {
+ compatible = "qcom,bam-v1.7.0";
+ reg = <0 0x01dc4000 0 0x28000>;
+
+ interrupts = <GIC_SPI 272 IRQ_TYPE_LEVEL_HIGH>;
+
+ #dma-cells = <1>;
+
+ iommus = <&apps_smmu 0x480 0>,
+ <&apps_smmu 0x481 0>;
+
+ qcom,ee = <0>;
+ qcom,controlled-remotely;
+ };
+
+ crypto: crypto@1dfa000 {
+ compatible = "qcom,sm8650-qce", "qcom,sm8150-qce", "qcom,qce";
+ reg = <0 0x01dfa000 0 0x6000>;
+
+ interconnects = <&aggre2_noc MASTER_CRYPTO QCOM_ICC_TAG_ALWAYS
+ &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
+ interconnect-names = "memory";
+
+ dmas = <&cryptobam 4>, <&cryptobam 5>;
+ dma-names = "rx", "tx";
+
+ iommus = <&apps_smmu 0x480 0>,
+ <&apps_smmu 0x481 0>;
+ };
+
+ ufs_mem_phy: phy@1d80000 {
+ compatible = "qcom,sm8650-qmp-ufs-phy";
+ reg = <0 0x01d80000 0 0x2000>;
+
+ clocks = <&tcsr TCSR_UFS_CLKREF_EN>,
+ <&gcc GCC_UFS_PHY_PHY_AUX_CLK>;
+ clock-names = "ref",
+ "ref_aux";
+
+ resets = <&ufs_mem_hc 0>;
+ reset-names = "ufsphy";
+
+ power-domains = <&gcc UFS_MEM_PHY_GDSC>;
+
+ #clock-cells = <1>;
+ #phy-cells = <0>;
+
+ status = "disabled";
+ };
+
+ ufs_mem_hc: ufs@1d84000 {
+ compatible = "qcom,sm8650-ufshc", "qcom,ufshc", "jedec,ufs-2.0";
+ reg = <0 0x01d84000 0 0x3000>;
+
+ interrupts = <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH>;
+
+ clocks = <&gcc GCC_UFS_PHY_AXI_CLK>,
+ <&gcc GCC_AGGRE_UFS_PHY_AXI_CLK>,
+ <&gcc GCC_UFS_PHY_AHB_CLK>,
+ <&gcc GCC_UFS_PHY_UNIPRO_CORE_CLK>,
+ <&tcsr TCSR_UFS_PAD_CLKREF_EN>,
+ <&gcc GCC_UFS_PHY_TX_SYMBOL_0_CLK>,
+ <&gcc GCC_UFS_PHY_RX_SYMBOL_0_CLK>,
+ <&gcc GCC_UFS_PHY_RX_SYMBOL_1_CLK>;
+ clock-names = "core_clk",
+ "bus_aggr_clk",
+ "iface_clk",
+ "core_clk_unipro",
+ "ref_clk",
+ "tx_lane0_sync_clk",
+ "rx_lane0_sync_clk",
+ "rx_lane1_sync_clk";
+ freq-table-hz = <100000000 403000000>,
+ <0 0>,
+ <0 0>,
+ <100000000 403000000>,
+ <100000000 403000000>,
+ <0 0>,
+ <0 0>,
+ <0 0>;
+
+ resets = <&gcc GCC_UFS_PHY_BCR>;
+ reset-names = "rst";
+
+ interconnects = <&aggre1_noc MASTER_UFS_MEM QCOM_ICC_TAG_ALWAYS
+ &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>,
+ <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
+ &config_noc SLAVE_UFS_MEM_CFG QCOM_ICC_TAG_ALWAYS>;
+ interconnect-names = "ufs-ddr",
+ "cpu-ufs";
+
+ power-domains = <&gcc UFS_PHY_GDSC>;
+ required-opps = <&rpmhpd_opp_nom>;
+
+ iommus = <&apps_smmu 0x60 0>;
+
+ lanes-per-direction = <2>;
+ qcom,ice = <&ice>;
+
+ phys = <&ufs_mem_phy>;
+ phy-names = "ufsphy";
+
+ #reset-cells = <1>;
+
+ status = "disabled";
+ };
+
+ ice: crypto@1d88000 {
+ compatible = "qcom,sm8650-inline-crypto-engine",
+ "qcom,inline-crypto-engine";
+ reg = <0 0x01d88000 0 0x8000>;
+
+ clocks = <&gcc GCC_UFS_PHY_ICE_CORE_CLK>;
+ };
+
+ tcsr_mutex: hwlock@1f40000 {
+ compatible = "qcom,tcsr-mutex";
+ reg = <0 0x01f40000 0 0x20000>;
+
+ #hwlock-cells = <1>;
+ };
+
+ tcsr: clock-controller@1fc0000 {
+ compatible = "qcom,sm8650-tcsr", "syscon";
+ reg = <0 0x01fc0000 0 0xa0000>;
+
+ clocks = <&rpmhcc RPMH_CXO_CLK>;
+
+ #clock-cells = <1>;
+ #reset-cells = <1>;
+ };
+
+ gpucc: clock-controller@3d90000 {
+ compatible = "qcom,sm8650-gpucc";
+ reg = <0 0x03d90000 0 0xa000>;
+
+ clocks = <&bi_tcxo_div2>,
+ <&gcc GCC_GPU_GPLL0_CLK_SRC>,
+ <&gcc GCC_GPU_GPLL0_DIV_CLK_SRC>;
+
+ #clock-cells = <1>;
+ #reset-cells = <1>;
+ #power-domain-cells = <1>;
+ };
+
+ ipa: ipa@3f40000 {
+ compatible = "qcom,sm8650-ipa", "qcom,sm8550-ipa";
+
+ iommus = <&apps_smmu 0x4a0 0x0>,
+ <&apps_smmu 0x4a2 0x0>;
+ reg = <0 0x3f40000 0 0x10000>,
+ <0 0x3f50000 0 0x5000>,
+ <0 0x3e04000 0 0xfc000>;
+ reg-names = "ipa-reg",
+ "ipa-shared",
+ "gsi";
+
+ interrupts-extended = <&intc GIC_SPI 654 IRQ_TYPE_EDGE_RISING>,
+ <&intc GIC_SPI 432 IRQ_TYPE_LEVEL_HIGH>,
+ <&ipa_smp2p_in 0 IRQ_TYPE_EDGE_RISING>,
+ <&ipa_smp2p_in 1 IRQ_TYPE_EDGE_RISING>;
+ interrupt-names = "ipa",
+ "gsi",
+ "ipa-clock-query",
+ "ipa-setup-ready";
+
+ clocks = <&rpmhcc RPMH_IPA_CLK>;
+ clock-names = "core";
+
+ interconnects = <&aggre2_noc MASTER_IPA 0 &mc_virt SLAVE_EBI1 0>,
+ <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_IPA_CFG 0>;
+ interconnect-names = "memory",
+ "config";
+
+ qcom,qmp = <&aoss_qmp>;
+
+ qcom,smem-states = <&ipa_smp2p_out 0>,
+ <&ipa_smp2p_out 1>;
+ qcom,smem-state-names = "ipa-clock-enabled-valid",
+ "ipa-clock-enabled";
+
+ status = "disabled";
+ };
+
+ remoteproc_mpss: remoteproc@4080000 {
+ compatible = "qcom,sm8650-mpss-pas";
+ reg = <0 0x04080000 0 0x4040>;
+
+ interrupts-extended = <&intc GIC_SPI 264 IRQ_TYPE_EDGE_RISING>,
+ <&smp2p_modem_in 0 IRQ_TYPE_EDGE_RISING>,
+ <&smp2p_modem_in 1 IRQ_TYPE_EDGE_RISING>,
+ <&smp2p_modem_in 2 IRQ_TYPE_EDGE_RISING>,
+ <&smp2p_modem_in 3 IRQ_TYPE_EDGE_RISING>,
+ <&smp2p_modem_in 7 IRQ_TYPE_EDGE_RISING>;
+ interrupt-names = "wdog",
+ "fatal",
+ "ready",
+ "handover",
+ "stop-ack",
+ "shutdown-ack";
+
+ clocks = <&rpmhcc RPMH_CXO_CLK>;
+ clock-names = "xo";
+
+ interconnects = <&mc_virt MASTER_LLCC QCOM_ICC_TAG_ALWAYS
+ &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
+
+ power-domains = <&rpmhpd RPMHPD_CX>,
+ <&rpmhpd RPMHPD_MSS>;
+ power-domain-names = "cx",
+ "mss";
+
+ memory-region = <&mpss_mem>, <&q6_mpss_dtb_mem>,
+ <&mpss_dsm_mem>, <&mpss_dsm_mem_2>;
+
+ qcom,qmp = <&aoss_qmp>;
+
+ qcom,smem-states = <&smp2p_modem_out 0>;
+ qcom,smem-state-names = "stop";
+
+ status = "disabled";
+
+ glink-edge {
+ interrupts-extended = <&ipcc IPCC_CLIENT_MPSS
+ IPCC_MPROC_SIGNAL_GLINK_QMP
+ IRQ_TYPE_EDGE_RISING>;
+
+ mboxes = <&ipcc IPCC_CLIENT_MPSS
+ IPCC_MPROC_SIGNAL_GLINK_QMP>;
+
+ qcom,remote-pid = <1>;
+
+ label = "mpss";
+ };
+ };
+
+ lpass_wsa2macro: codec@6aa0000 {
+ compatible = "qcom,sm8650-lpass-wsa-macro", "qcom,sm8550-lpass-wsa-macro";
+ reg = <0 0x06aa0000 0 0x1000>;
+ clocks = <&q6prmcc LPASS_CLK_ID_WSA2_CORE_TX_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
+ <&q6prmcc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
+ <&q6prmcc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
+ <&lpass_vamacro>;
+ clock-names = "mclk",
+ "macro",
+ "dcodec",
+ "fsgen";
+
+ #clock-cells = <0>;
+ clock-output-names = "wsa2-mclk";
+ #sound-dai-cells = <1>;
+ };
+
+ swr3: soundwire@6ab0000 {
+ compatible = "qcom,soundwire-v2.0.0";
+ reg = <0 0x06ab0000 0 0x10000>;
+ interrupts = <GIC_SPI 171 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&lpass_wsa2macro>;
+ clock-names = "iface";
+ label = "WSA2";
+
+ pinctrl-0 = <&wsa2_swr_active>;
+ pinctrl-names = "default";
+
+ qcom,din-ports = <4>;
+ qcom,dout-ports = <9>;
+
+ qcom,ports-sinterval = /bits/ 16 <0x07 0x1f 0x3f 0x07 0x1f 0x3f 0x18f 0xff 0xff 0x0f 0x0f 0xff 0x31f>;
+ qcom,ports-offset1 = /bits/ 8 <0x01 0x03 0x05 0x02 0x04 0x15 0x00 0xff 0xff 0x06 0x0d 0xff 0x00>;
+ qcom,ports-offset2 = /bits/ 8 <0xff 0x07 0x1f 0xff 0x07 0x1f 0xff 0xff 0xff 0xff 0xff 0xff 0xff>;
+ qcom,ports-hstart = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0x08 0xff 0xff 0xff 0xff 0xff 0x0f>;
+ qcom,ports-hstop = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0x08 0xff 0xff 0xff 0xff 0xff 0x0f>;
+ qcom,ports-word-length = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0x08 0xff 0xff 0xff 0xff 0xff 0x18>;
+ qcom,ports-block-pack-mode = /bits/ 8 <0x00 0x01 0x01 0x00 0x01 0x01 0x00 0x00 0x00 0x01 0x01 0x00 0x00>;
+ qcom,ports-block-group-count = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff>;
+ qcom,ports-lane-control = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff>;
+
+ #address-cells = <2>;
+ #size-cells = <0>;
+ #sound-dai-cells = <1>;
+ status = "disabled";
+ };
+
+ lpass_rxmacro: codec@6ac0000 {
+ compatible = "qcom,sm8650-lpass-rx-macro", "qcom,sm8550-lpass-rx-macro";
+ reg = <0 0x06ac0000 0 0x1000>;
+ clocks = <&q6prmcc LPASS_CLK_ID_RX_CORE_TX_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
+ <&q6prmcc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
+ <&q6prmcc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
+ <&lpass_vamacro>;
+ clock-names = "mclk",
+ "macro",
+ "dcodec",
+ "fsgen";
+
+ #clock-cells = <0>;
+ clock-output-names = "mclk";
+ #sound-dai-cells = <1>;
+ };
+
+ swr1: soundwire@6ad0000 {
+ compatible = "qcom,soundwire-v2.0.0";
+ reg = <0 0x06ad0000 0 0x10000>;
+ interrupts = <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&lpass_rxmacro>;
+ clock-names = "iface";
+ label = "RX";
+
+ pinctrl-0 = <&rx_swr_active>;
+ pinctrl-names = "default";
+
+ qcom,din-ports = <0>;
+ qcom,dout-ports = <11>;
+
+ qcom,ports-sinterval = /bits/ 16 <0x03 0x1f 0x1f 0x07 0x03 0xff 0xff 0x31 0xff 0xff 0xff>;
+ qcom,ports-offset1 = /bits/ 8 <0x00 0x00 0x0b 0x09 0x01 0xff 0xff 0x00 0xff 0xff 0xff>;
+ qcom,ports-offset2 = /bits/ 8 <0x00 0x00 0x0b 0x00 0x00 0xff 0xff 0x00 0xff 0xff 0xff>;
+ qcom,ports-hstart = /bits/ 8 <0xff 0x03 0xff 0xff 0xff 0xff 0xff 0x00 0xff 0xff 0xff>;
+ qcom,ports-hstop = /bits/ 8 <0xff 0x06 0xff 0xff 0xff 0xff 0xff 0x0f 0xff 0xff 0xff>;
+ qcom,ports-word-length = /bits/ 8 <0x01 0x07 0x04 0xff 0xff 0xff 0xff 0x18 0xff 0xff 0xff>;
+ qcom,ports-block-pack-mode = /bits/ 8 <0xff 0x00 0x01 0xff 0xff 0xff 0xff 0x01 0xff 0xff 0xff>;
+ qcom,ports-block-group-count = /bits/ 8 <0xff 0xff 0xff 0x01 0x03 0xff 0xff 0x00 0xff 0xff 0xff>;
+ qcom,ports-lane-control = /bits/ 8 <0x01 0x00 0x00 0x00 0x00 0xff 0xff 0x01 0xff 0xff 0xff>;
+
+ #address-cells = <2>;
+ #size-cells = <0>;
+ #sound-dai-cells = <1>;
+ status = "disabled";
+ };
+
+ lpass_txmacro: codec@6ae0000 {
+ compatible = "qcom,sm8650-lpass-tx-macro", "qcom,sm8550-lpass-tx-macro";
+ reg = <0 0x06ae0000 0 0x1000>;
+ clocks = <&q6prmcc LPASS_CLK_ID_TX_CORE_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
+ <&q6prmcc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
+ <&q6prmcc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
+ <&lpass_vamacro>;
+ clock-names = "mclk",
+ "macro",
+ "dcodec",
+ "fsgen";
+
+ #clock-cells = <0>;
+ clock-output-names = "mclk";
+ #sound-dai-cells = <1>;
+ };
+
+ lpass_wsamacro: codec@6b00000 {
+ compatible = "qcom,sm8650-lpass-wsa-macro", "qcom,sm8550-lpass-wsa-macro";
+ reg = <0 0x06b00000 0 0x1000>;
+ clocks = <&q6prmcc LPASS_CLK_ID_WSA_CORE_TX_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
+ <&q6prmcc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
+ <&q6prmcc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
+ <&lpass_vamacro>;
+ clock-names = "mclk",
+ "macro",
+ "dcodec",
+ "fsgen";
+
+ #clock-cells = <0>;
+ clock-output-names = "mclk";
+ #sound-dai-cells = <1>;
+ };
+
+ swr0: soundwire@6b10000 {
+ compatible = "qcom,soundwire-v2.0.0";
+ reg = <0 0x06b10000 0 0x10000>;
+ interrupts = <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&lpass_wsamacro>;
+ clock-names = "iface";
+ label = "WSA";
+
+ pinctrl-0 = <&wsa_swr_active>;
+ pinctrl-names = "default";
+
+ qcom,din-ports = <4>;
+ qcom,dout-ports = <9>;
+
+ qcom,ports-sinterval = /bits/ 16 <0x07 0x1f 0x3f 0x07 0x1f 0x3f 0x18f 0xff 0xff 0x0f 0x0f 0xff 0x31f>;
+ qcom,ports-offset1 = /bits/ 8 <0x01 0x03 0x05 0x02 0x04 0x15 0x00 0xff 0xff 0x06 0x0d 0xff 0x00>;
+ qcom,ports-offset2 = /bits/ 8 <0xff 0x07 0x1f 0xff 0x07 0x1f 0xff 0xff 0xff 0xff 0xff 0xff 0xff>;
+ qcom,ports-hstart = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0x08 0xff 0xff 0xff 0xff 0xff 0x0f>;
+ qcom,ports-hstop = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0x08 0xff 0xff 0xff 0xff 0xff 0x0f>;
+ qcom,ports-word-length = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0x08 0xff 0xff 0xff 0xff 0xff 0x18>;
+ qcom,ports-block-pack-mode = /bits/ 8 <0x00 0x01 0x01 0x00 0x01 0x01 0x00 0x00 0x00 0x01 0x01 0x00 0x00>;
+ qcom,ports-block-group-count = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff>;
+ qcom,ports-lane-control = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff>;
+
+ #address-cells = <2>;
+ #size-cells = <0>;
+ #sound-dai-cells = <1>;
+ status = "disabled";
+ };
+
+ swr2: soundwire@6d30000 {
+ compatible = "qcom,soundwire-v2.0.0";
+ reg = <0 0x06d30000 0 0x10000>;
+ interrupts = <GIC_SPI 496 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 520 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "core", "wakeup";
+ clocks = <&lpass_txmacro>;
+ clock-names = "iface";
+ label = "TX";
+
+ pinctrl-0 = <&tx_swr_active>;
+ pinctrl-names = "default";
+
+ qcom,din-ports = <4>;
+ qcom,dout-ports = <0>;
+
+ qcom,ports-sinterval-low = /bits/ 8 <0x01 0x01 0x03 0x03>;
+ qcom,ports-offset1 = /bits/ 8 <0x00 0x00 0x01 0x01>;
+ qcom,ports-offset2 = /bits/ 8 <0x00 0x00 0x00 0x00>;
+ qcom,ports-hstart = /bits/ 8 <0xff 0xff 0xff 0xff>;
+ qcom,ports-hstop = /bits/ 8 <0xff 0xff 0xff 0xff>;
+ qcom,ports-word-length = /bits/ 8 <0xff 0xff 0xff 0xff>;
+ qcom,ports-block-pack-mode = /bits/ 8 <0xff 0xff 0xff 0xff>;
+ qcom,ports-block-group-count = /bits/ 8 <0xff 0xff 0xff 0xff>;
+ qcom,ports-lane-control = /bits/ 8 <0x01 0x02 0x00 0x00>;
+
+ #address-cells = <2>;
+ #size-cells = <0>;
+ #sound-dai-cells = <1>;
+ status = "disabled";
+ };
+
+ lpass_vamacro: codec@6d44000 {
+ compatible = "qcom,sm8650-lpass-va-macro", "qcom,sm8550-lpass-va-macro";
+ reg = <0 0x06d44000 0 0x1000>;
+ clocks = <&q6prmcc LPASS_CLK_ID_TX_CORE_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
+ <&q6prmcc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
+ <&q6prmcc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>;
+ clock-names = "mclk",
+ "macro",
+ "dcodec";
+
+ #clock-cells = <0>;
+ clock-output-names = "fsgen";
+ #sound-dai-cells = <1>;
+ };
+
+ lpass_tlmm: pinctrl@6e80000 {
+ compatible = "qcom,sm8650-lpass-lpi-pinctrl";
+ reg = <0 0x06e80000 0 0x20000>;
+
+ clocks = <&q6prmcc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
+ <&q6prmcc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>;
+ clock-names = "core", "audio";
+
+ gpio-controller;
+ #gpio-cells = <2>;
+ gpio-ranges = <&lpass_tlmm 0 0 23>;
+
+ tx_swr_active: tx-swr-active-state {
+ clk-pins {
+ pins = "gpio0";
+ function = "swr_tx_clk";
+ drive-strength = <2>;
+ slew-rate = <1>;
+ bias-disable;
+ };
+
+ data-pins {
+ pins = "gpio1", "gpio2", "gpio14";
+ function = "swr_tx_data";
+ drive-strength = <2>;
+ slew-rate = <1>;
+ bias-bus-hold;
+ };
+ };
+
+ rx_swr_active: rx-swr-active-state {
+ clk-pins {
+ pins = "gpio3";
+ function = "swr_rx_clk";
+ drive-strength = <2>;
+ slew-rate = <1>;
+ bias-disable;
+ };
+
+ data-pins {
+ pins = "gpio4", "gpio5";
+ function = "swr_rx_data";
+ drive-strength = <2>;
+ slew-rate = <1>;
+ bias-bus-hold;
+ };
+ };
+
+ dmic01_default: dmic01-default-state {
+ clk-pins {
+ pins = "gpio6";
+ function = "dmic1_clk";
+ drive-strength = <8>;
+ output-high;
+ };
+
+ data-pins {
+ pins = "gpio7";
+ function = "dmic1_data";
+ drive-strength = <8>;
+ input-enable;
+ };
+ };
+
+ dmic02_default: dmic02-default-state {
+ clk-pins {
+ pins = "gpio8";
+ function = "dmic2_clk";
+ drive-strength = <8>;
+ output-high;
+ };
+
+ data-pins {
+ pins = "gpio9";
+ function = "dmic2_data";
+ drive-strength = <8>;
+ input-enable;
+ };
+ };
+
+ wsa_swr_active: wsa-swr-active-state {
+ clk-pins {
+ pins = "gpio10";
+ function = "wsa_swr_clk";
+ drive-strength = <2>;
+ slew-rate = <1>;
+ bias-disable;
+ };
+
+ data-pins {
+ pins = "gpio11";
+ function = "wsa_swr_data";
+ drive-strength = <2>;
+ slew-rate = <1>;
+ bias-bus-hold;
+ };
+ };
+
+ wsa2_swr_active: wsa2-swr-active-state {
+ clk-pins {
+ pins = "gpio15";
+ function = "wsa2_swr_clk";
+ drive-strength = <2>;
+ slew-rate = <1>;
+ bias-disable;
+ };
+
+ data-pins {
+ pins = "gpio16";
+ function = "wsa2_swr_data";
+ drive-strength = <2>;
+ slew-rate = <1>;
+ bias-bus-hold;
+ };
+ };
+ };
+
+ lpass_lpiaon_noc: interconnect@7400000 {
+ compatible = "qcom,sm8650-lpass-lpiaon-noc";
+ reg = <0 0x07400000 0 0x19080>;
+
+ #interconnect-cells = <2>;
+
+ qcom,bcm-voters = <&apps_bcm_voter>;
+ };
+
+ lpass_lpicx_noc: interconnect@7430000 {
+ compatible = "qcom,sm8650-lpass-lpicx-noc";
+ reg = <0 0x07430000 0 0x3a200>;
+
+ #interconnect-cells = <2>;
+
+ qcom,bcm-voters = <&apps_bcm_voter>;
+ };
+
+ lpass_ag_noc: interconnect@7e40000 {
+ compatible = "qcom,sm8650-lpass-ag-noc";
+ reg = <0 0x07e40000 0 0xe080>;
+
+ #interconnect-cells = <2>;
+
+ qcom,bcm-voters = <&apps_bcm_voter>;
+ };
+
+ sdhc_2: mmc@8804000 {
+ compatible = "qcom,sm8650-sdhci", "qcom,sdhci-msm-v5";
+ reg = <0 0x08804000 0 0x1000>;
+
+ interrupts = <GIC_SPI 207 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 223 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "hc_irq",
+ "pwr_irq";
+
+ clocks = <&gcc GCC_SDCC2_AHB_CLK>,
+ <&gcc GCC_SDCC2_APPS_CLK>,
+ <&rpmhcc RPMH_CXO_CLK>;
+ clock-names = "iface",
+ "core",
+ "xo";
+
+ interconnects = <&aggre2_noc MASTER_SDCC_2 QCOM_ICC_TAG_ALWAYS
+ &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>,
+ <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
+ &config_noc SLAVE_SDCC_2 QCOM_ICC_TAG_ALWAYS>;
+ interconnect-names = "sdhc-ddr",
+ "cpu-sdhc";
+
+ power-domains = <&rpmhpd RPMHPD_CX>;
+ operating-points-v2 = <&sdhc2_opp_table>;
+
+ iommus = <&apps_smmu 0x540 0>;
+
+ bus-width = <4>;
+
+ /* Forbid SDR104/SDR50 - broken hw! */
+ sdhci-caps-mask = <0x3 0>;
+
+ qcom,dll-config = <0x0007642c>;
+ qcom,ddr-config = <0x80040868>;
+
+ dma-coherent;
+
+ status = "disabled";
+
+ sdhc2_opp_table: opp-table {
+ compatible = "operating-points-v2";
+
+ opp-19200000 {
+ opp-hz = /bits/ 64 <19200000>;
+ required-opps = <&rpmhpd_opp_min_svs>;
+ };
+
+ opp-50000000 {
+ opp-hz = /bits/ 64 <50000000>;
+ required-opps = <&rpmhpd_opp_low_svs>;
+ };
+
+ opp-100000000 {
+ opp-hz = /bits/ 64 <100000000>;
+ required-opps = <&rpmhpd_opp_svs>;
+ };
+
+ opp-202000000 {
+ opp-hz = /bits/ 64 <202000000>;
+ required-opps = <&rpmhpd_opp_svs_l1>;
+ };
+ };
+ };
+
+ mdss: display-subsystem@ae00000 {
+ compatible = "qcom,sm8650-mdss";
+ reg = <0 0x0ae00000 0 0x1000>;
+ reg-names = "mdss";
+
+ interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
+
+ clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>,
+ <&gcc GCC_DISP_HF_AXI_CLK>,
+ <&dispcc DISP_CC_MDSS_MDP_CLK>;
+
+ resets = <&dispcc DISP_CC_MDSS_CORE_BCR>;
+
+ interconnects = <&mmss_noc MASTER_MDP QCOM_ICC_TAG_ALWAYS
+ &gem_noc SLAVE_LLCC QCOM_ICC_TAG_ALWAYS>,
+ <&mc_virt MASTER_LLCC QCOM_ICC_TAG_ALWAYS
+ &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
+ interconnect-names = "mdp0-mem",
+ "mdp1-mem";
+
+ power-domains = <&dispcc MDSS_GDSC>;
+
+ iommus = <&apps_smmu 0x1c00 0x2>;
+
+ interrupt-controller;
+ #interrupt-cells = <1>;
+
+ #address-cells = <2>;
+ #size-cells = <2>;
+ ranges;
+
+ status = "disabled";
+
+ mdss_mdp: display-controller@ae01000 {
+ compatible = "qcom,sm8650-dpu";
+ reg = <0 0x0ae01000 0 0x8f000>,
+ <0 0x0aeb0000 0 0x2008>;
+ reg-names = "mdp",
+ "vbif";
+
+ interrupts-extended = <&mdss 0>;
+
+ clocks = <&gcc GCC_DISP_HF_AXI_CLK>,
+ <&dispcc DISP_CC_MDSS_AHB_CLK>,
+ <&dispcc DISP_CC_MDSS_MDP_LUT_CLK>,
+ <&dispcc DISP_CC_MDSS_MDP_CLK>,
+ <&dispcc DISP_CC_MDSS_VSYNC_CLK>;
+ clock-names = "nrt_bus",
+ "iface",
+ "lut",
+ "core",
+ "vsync";
+
+ assigned-clocks = <&dispcc DISP_CC_MDSS_VSYNC_CLK>;
+ assigned-clock-rates = <19200000>;
+
+ operating-points-v2 = <&mdp_opp_table>;
+
+ power-domains = <&rpmhpd RPMHPD_MMCX>;
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+
+ dpu_intf1_out: endpoint {
+ remote-endpoint = <&mdss_dsi0_in>;
+ };
+ };
+
+ port@1 {
+ reg = <1>;
+
+ dpu_intf2_out: endpoint {
+ remote-endpoint = <&mdss_dsi1_in>;
+ };
+ };
+
+ port@2 {
+ reg = <2>;
+
+ dpu_intf0_out: endpoint {
+ remote-endpoint = <&mdss_dp0_in>;
+ };
+ };
+ };
+
+ mdp_opp_table: opp-table {
+ compatible = "operating-points-v2";
+
+ opp-200000000 {
+ opp-hz = /bits/ 64 <200000000>;
+ required-opps = <&rpmhpd_opp_low_svs>;
+ };
+
+ opp-325000000 {
+ opp-hz = /bits/ 64 <325000000>;
+ required-opps = <&rpmhpd_opp_svs>;
+ };
+
+ opp-375000000 {
+ opp-hz = /bits/ 64 <375000000>;
+ required-opps = <&rpmhpd_opp_svs_l1>;
+ };
+
+ opp-514000000 {
+ opp-hz = /bits/ 64 <514000000>;
+ required-opps = <&rpmhpd_opp_nom>;
+ };
+ };
+ };
+
+ mdss_dsi0: dsi@ae94000 {
+ compatible = "qcom,sm8650-dsi-ctrl", "qcom,mdss-dsi-ctrl";
+ reg = <0 0x0ae94000 0 0x400>;
+ reg-names = "dsi_ctrl";
+
+ interrupts-extended = <&mdss 4>;
+
+ clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK>,
+ <&dispcc DISP_CC_MDSS_BYTE0_INTF_CLK>,
+ <&dispcc DISP_CC_MDSS_PCLK0_CLK>,
+ <&dispcc DISP_CC_MDSS_ESC0_CLK>,
+ <&dispcc DISP_CC_MDSS_AHB_CLK>,
+ <&gcc GCC_DISP_HF_AXI_CLK>;
+ clock-names = "byte",
+ "byte_intf",
+ "pixel",
+ "core",
+ "iface",
+ "bus";
+
+ assigned-clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK_SRC>,
+ <&dispcc DISP_CC_MDSS_PCLK0_CLK_SRC>;
+ assigned-clock-parents = <&mdss_dsi0_phy 0>,
+ <&mdss_dsi0_phy 1>;
+
+ operating-points-v2 = <&mdss_dsi_opp_table>;
+
+ power-domains = <&rpmhpd RPMHPD_MMCX>;
+
+ phys = <&mdss_dsi0_phy>;
+ phy-names = "dsi";
+
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ status = "disabled";
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+
+ mdss_dsi0_in: endpoint {
+ remote-endpoint = <&dpu_intf1_out>;
+ };
+ };
+
+ port@1 {
+ reg = <1>;
+
+ mdss_dsi0_out: endpoint {
+ };
+ };
+ };
+
+ mdss_dsi_opp_table: opp-table {
+ compatible = "operating-points-v2";
+
+ opp-187500000 {
+ opp-hz = /bits/ 64 <187500000>;
+ required-opps = <&rpmhpd_opp_low_svs>;
+ };
+
+ opp-300000000 {
+ opp-hz = /bits/ 64 <300000000>;
+ required-opps = <&rpmhpd_opp_svs>;
+ };
+
+ opp-358000000 {
+ opp-hz = /bits/ 64 <358000000>;
+ required-opps = <&rpmhpd_opp_svs_l1>;
+ };
+ };
+ };
+
+ mdss_dsi0_phy: phy@ae95000 {
+ compatible = "qcom,sm8650-dsi-phy-4nm";
+ reg = <0 0x0ae95000 0 0x200>,
+ <0 0x0ae95200 0 0x280>,
+ <0 0x0ae95500 0 0x400>;
+ reg-names = "dsi_phy",
+ "dsi_phy_lane",
+ "dsi_pll";
+
+ clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>,
+ <&rpmhcc RPMH_CXO_CLK>;
+ clock-names = "iface",
+ "ref";
+
+ #clock-cells = <1>;
+ #phy-cells = <0>;
+
+ status = "disabled";
+ };
+
+ mdss_dsi1: dsi@ae96000 {
+ compatible = "qcom,sm8650-dsi-ctrl", "qcom,mdss-dsi-ctrl";
+ reg = <0 0x0ae96000 0 0x400>;
+ reg-names = "dsi_ctrl";
+
+ interrupts-extended = <&mdss 5>;
+
+ clocks = <&dispcc DISP_CC_MDSS_BYTE1_CLK>,
+ <&dispcc DISP_CC_MDSS_BYTE1_INTF_CLK>,
+ <&dispcc DISP_CC_MDSS_PCLK1_CLK>,
+ <&dispcc DISP_CC_MDSS_ESC1_CLK>,
+ <&dispcc DISP_CC_MDSS_AHB_CLK>,
+ <&gcc GCC_DISP_HF_AXI_CLK>;
+ clock-names = "byte",
+ "byte_intf",
+ "pixel",
+ "core",
+ "iface",
+ "bus";
+
+ assigned-clocks = <&dispcc DISP_CC_MDSS_BYTE1_CLK_SRC>,
+ <&dispcc DISP_CC_MDSS_PCLK1_CLK_SRC>;
+ assigned-clock-parents = <&mdss_dsi1_phy 0>,
+ <&mdss_dsi1_phy 1>;
+
+ operating-points-v2 = <&mdss_dsi_opp_table>;
+
+ power-domains = <&rpmhpd RPMHPD_MMCX>;
+
+ phys = <&mdss_dsi1_phy>;
+ phy-names = "dsi";
+
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ status = "disabled";
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+
+ mdss_dsi1_in: endpoint {
+ remote-endpoint = <&dpu_intf2_out>;
+ };
+ };
+
+ port@1 {
+ reg = <1>;
+
+ mdss_dsi1_out: endpoint {
+ };
+ };
+ };
+ };
+
+ mdss_dsi1_phy: phy@ae97000 {
+ compatible = "qcom,sm8650-dsi-phy-4nm";
+ reg = <0 0x0ae97000 0 0x200>,
+ <0 0x0ae97200 0 0x280>,
+ <0 0x0ae97500 0 0x400>;
+ reg-names = "dsi_phy",
+ "dsi_phy_lane",
+ "dsi_pll";
+
+ clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>,
+ <&rpmhcc RPMH_CXO_CLK>;
+ clock-names = "iface",
+ "ref";
+
+ #clock-cells = <1>;
+ #phy-cells = <0>;
+
+ status = "disabled";
+ };
+
+ mdss_dp0: displayport-controller@af54000 {
+ compatible = "qcom,sm8650-dp";
+ reg = <0 0xaf54000 0 0x104>,
+ <0 0xaf54200 0 0xc0>,
+ <0 0xaf55000 0 0x770>,
+ <0 0xaf56000 0 0x9c>,
+ <0 0xaf57000 0 0x9c>;
+
+ interrupts-extended = <&mdss 12>;
+
+ clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>,
+ <&dispcc DISP_CC_MDSS_DPTX0_AUX_CLK>,
+ <&dispcc DISP_CC_MDSS_DPTX0_LINK_CLK>,
+ <&dispcc DISP_CC_MDSS_DPTX0_LINK_INTF_CLK>,
+ <&dispcc DISP_CC_MDSS_DPTX0_PIXEL0_CLK>;
+ clock-names = "core_iface",
+ "core_aux",
+ "ctrl_link",
+ "ctrl_link_iface",
+ "stream_pixel";
+
+ assigned-clocks = <&dispcc DISP_CC_MDSS_DPTX0_LINK_CLK_SRC>,
+ <&dispcc DISP_CC_MDSS_DPTX0_PIXEL0_CLK_SRC>;
+ assigned-clock-parents = <&usb_dp_qmpphy QMP_USB43DP_DP_LINK_CLK>,
+ <&usb_dp_qmpphy QMP_USB43DP_DP_VCO_DIV_CLK>;
+
+ operating-points-v2 = <&dp_opp_table>;
+
+ power-domains = <&rpmhpd RPMHPD_MMCX>;
+
+ phys = <&usb_dp_qmpphy QMP_USB43DP_DP_PHY>;
+ phy-names = "dp";
+
+ #sound-dai-cells = <0>;
+
+ status = "disabled";
+
+ dp_opp_table: opp-table {
+ compatible = "operating-points-v2";
+
+ opp-162000000 {
+ opp-hz = /bits/ 64 <162000000>;
+ required-opps = <&rpmhpd_opp_low_svs_d1>;
+ };
+
+ opp-270000000 {
+ opp-hz = /bits/ 64 <270000000>;
+ required-opps = <&rpmhpd_opp_low_svs>;
+ };
+
+ opp-540000000 {
+ opp-hz = /bits/ 64 <540000000>;
+ required-opps = <&rpmhpd_opp_svs_l1>;
+ };
+
+ opp-810000000 {
+ opp-hz = /bits/ 64 <810000000>;
+ required-opps = <&rpmhpd_opp_nom>;
+ };
+ };
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+
+ mdss_dp0_in: endpoint {
+ remote-endpoint = <&dpu_intf0_out>;
+ };
+ };
+
+ port@1 {
+ reg = <1>;
+
+ mdss_dp0_out: endpoint {
+ };
+ };
+ };
+ };
+ };
+
+ dispcc: clock-controller@af00000 {
+ compatible = "qcom,sm8650-dispcc";
+ reg = <0 0x0af00000 0 0x20000>;
+
+ clocks = <&bi_tcxo_div2>,
+ <&bi_tcxo_ao_div2>,
+ <&gcc GCC_DISP_AHB_CLK>,
+ <&sleep_clk>,
+ <&mdss_dsi0_phy 0>,
+ <&mdss_dsi0_phy 1>,
+ <&mdss_dsi1_phy 0>,
+ <&mdss_dsi1_phy 1>,
+ <&usb_dp_qmpphy QMP_USB43DP_DP_LINK_CLK>,
+ <&usb_dp_qmpphy QMP_USB43DP_DP_VCO_DIV_CLK>,
+ <0>, /* dp1 */
+ <0>,
+ <0>, /* dp2 */
+ <0>,
+ <0>, /* dp3 */
+ <0>;
+
+ power-domains = <&rpmhpd RPMHPD_MMCX>;
+ required-opps = <&rpmhpd_opp_low_svs>;
+
+ #clock-cells = <1>;
+ #reset-cells = <1>;
+ #power-domain-cells = <1>;
+
+ status = "disabled";
+ };
+
+ usb_1_hsphy: phy@88e3000 {
+ compatible = "qcom,sm8650-snps-eusb2-phy",
+ "qcom,sm8550-snps-eusb2-phy";
+ reg = <0 0x088e3000 0 0x154>;
+
+ clocks = <&tcsr TCSR_USB2_CLKREF_EN>;
+ clock-names = "ref";
+
+ resets = <&gcc GCC_QUSB2PHY_PRIM_BCR>;
+
+ #phy-cells = <0>;
+
+ status = "disabled";
+ };
+
+ usb_dp_qmpphy: phy@88e8000 {
+ compatible = "qcom,sm8650-qmp-usb3-dp-phy";
+ reg = <0 0x088e8000 0 0x3000>;
+
+ clocks = <&gcc GCC_USB3_PRIM_PHY_AUX_CLK>,
+ <&rpmhcc RPMH_CXO_CLK>,
+ <&gcc GCC_USB3_PRIM_PHY_COM_AUX_CLK>,
+ <&gcc GCC_USB3_PRIM_PHY_PIPE_CLK>;
+ clock-names = "aux",
+ "ref",
+ "com_aux",
+ "usb3_pipe";
+
+ resets = <&gcc GCC_USB3_PHY_PRIM_BCR>,
+ <&gcc GCC_USB3_DP_PHY_PRIM_BCR>;
+ reset-names = "phy",
+ "common";
+
+ power-domains = <&gcc USB3_PHY_GDSC>;
+
+ #clock-cells = <1>;
+ #phy-cells = <1>;
+
+ status = "disabled";
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+
+ usb_dp_qmpphy_out: endpoint {
+ };
+ };
+
+ port@1 {
+ reg = <1>;
+
+ usb_dp_qmpphy_usb_ss_in: endpoint {
+ };
+ };
+
+ port@2 {
+ reg = <2>;
+
+ usb_dp_qmpphy_dp_in: endpoint {
+ };
+ };
+ };
+ };
+
+ usb_1: usb@a6f8800 {
+ compatible = "qcom,sm8650-dwc3", "qcom,dwc3";
+ reg = <0 0x0a6f8800 0 0x400>;
+
+ interrupts-extended = <&intc GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>,
+ <&pdc 17 IRQ_TYPE_LEVEL_HIGH>,
+ <&pdc 15 IRQ_TYPE_EDGE_RISING>,
+ <&pdc 14 IRQ_TYPE_EDGE_RISING>;
+ interrupt-names = "hs_phy_irq",
+ "ss_phy_irq",
+ "dm_hs_phy_irq",
+ "dp_hs_phy_irq";
+
+ clocks = <&gcc GCC_CFG_NOC_USB3_PRIM_AXI_CLK>,
+ <&gcc GCC_USB30_PRIM_MASTER_CLK>,
+ <&gcc GCC_AGGRE_USB3_PRIM_AXI_CLK>,
+ <&gcc GCC_USB30_PRIM_SLEEP_CLK>,
+ <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>,
+ <&tcsr TCSR_USB3_CLKREF_EN>;
+ clock-names = "cfg_noc",
+ "core",
+ "iface",
+ "sleep",
+ "mock_utmi",
+ "xo";
+
+ assigned-clocks = <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>,
+ <&gcc GCC_USB30_PRIM_MASTER_CLK>;
+ assigned-clock-rates = <19200000>, <200000000>;
+
+ resets = <&gcc GCC_USB30_PRIM_BCR>;
+
+ power-domains = <&gcc USB30_PRIM_GDSC>;
+ required-opps = <&rpmhpd_opp_nom>;
+
+ #address-cells = <2>;
+ #size-cells = <2>;
+ ranges;
+
+ status = "disabled";
+
+ usb_1_dwc3: usb@a600000 {
+ compatible = "snps,dwc3";
+ reg = <0 0x0a600000 0 0xcd00>;
+
+ interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>;
+
+ iommus = <&apps_smmu 0x40 0>;
+
+ phys = <&usb_1_hsphy>,
+ <&usb_dp_qmpphy QMP_USB43DP_USB3_PHY>;
+ phy-names = "usb2-phy",
+ "usb3-phy";
+
+ snps,hird-threshold = /bits/ 8 <0x0>;
+ snps,usb2-gadget-lpm-disable;
+ snps,dis_u2_susphy_quirk;
+ snps,dis_enblslpm_quirk;
+ snps,dis-u1-entry-quirk;
+ snps,dis-u2-entry-quirk;
+ snps,is-utmi-l1-suspend;
+ snps,usb3_lpm_capable;
+ snps,usb2-lpm-disable;
+ snps,has-lpm-erratum;
+ tx-fifo-resize;
+
+ dma-coherent;
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+
+ usb_1_dwc3_hs: endpoint {
+ };
+ };
+
+ port@1 {
+ reg = <1>;
+
+ usb_1_dwc3_ss: endpoint {
+ };
+ };
+ };
+ };
+ };
+
+ pdc: interrupt-controller@b220000 {
+ compatible = "qcom,sm8650-pdc", "qcom,pdc";
+ reg = <0 0x0b220000 0 0x30000>, <0 0x174000f0 0 0x64>;
+
+ interrupt-parent = <&intc>;
+
+ qcom,pdc-ranges = <0 480 94>, <94 609 31>,
+ <125 63 1>, <126 716 12>,
+ <138 251 5>, <143 244 4>;
+
+ #interrupt-cells = <2>;
+ interrupt-controller;
+ };
+
+ tsens0: thermal-sensor@c228000 {
+ compatible = "qcom,sm8650-tsens", "qcom,tsens-v2";
+ reg = <0 0x0c228000 0 0x1000>, /* TM */
+ <0 0x0c222000 0 0x1000>; /* SROT */
+
+ interrupts = <GIC_SPI 506 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 640 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "uplow",
+ "critical";
+
+ #qcom,sensors = <15>;
+
+ #thermal-sensor-cells = <1>;
+ };
+
+ tsens1: thermal-sensor@c229000 {
+ compatible = "qcom,sm8650-tsens", "qcom,tsens-v2";
+ reg = <0 0x0c229000 0 0x1000>, /* TM */
+ <0 0x0c223000 0 0x1000>; /* SROT */
+
+ interrupts = <GIC_SPI 507 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 641 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "uplow",
+ "critical";
+
+ #qcom,sensors = <16>;
+
+ #thermal-sensor-cells = <1>;
+ };
+
+ tsens2: thermal-sensor@c22a000 {
+ compatible = "qcom,sm8650-tsens", "qcom,tsens-v2";
+ reg = <0 0x0c22a000 0 0x1000>, /* TM */
+ <0 0x0c224000 0 0x1000>; /* SROT */
+
+ interrupts = <GIC_SPI 508 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 642 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "uplow",
+ "critical";
+
+ #qcom,sensors = <13>;
+
+ #thermal-sensor-cells = <1>;
+ };
+
+ aoss_qmp: power-management@c300000 {
+ compatible = "qcom,sm8650-aoss-qmp", "qcom,aoss-qmp";
+ reg = <0 0x0c300000 0 0x400>;
+
+ interrupt-parent = <&ipcc>;
+ interrupts-extended = <&ipcc IPCC_CLIENT_AOP IPCC_MPROC_SIGNAL_GLINK_QMP
+ IRQ_TYPE_EDGE_RISING>;
+
+ mboxes = <&ipcc IPCC_CLIENT_AOP IPCC_MPROC_SIGNAL_GLINK_QMP>;
+
+ #clock-cells = <0>;
+ };
+
+ sram@c3f0000 {
+ compatible = "qcom,rpmh-stats";
+ reg = <0 0x0c3f0000 0 0x400>;
+ };
+
+ spmi_bus: spmi@c400000 {
+ compatible = "qcom,spmi-pmic-arb";
+ reg = <0 0x0c400000 0 0x3000>,
+ <0 0x0c500000 0 0x4000000>,
+ <0 0x0c440000 0 0x80000>,
+ <0 0x0c4c0000 0 0x20000>,
+ <0 0x0c42d000 0 0x4000>;
+ reg-names = "core",
+ "chnls",
+ "obsrvr",
+ "intr",
+ "cnfg";
+
+ interrupts-extended = <&pdc 1 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "periph_irq";
+
+ qcom,ee = <0>;
+ qcom,channel = <0>;
+ qcom,bus-id = <0>;
+
+ interrupt-controller;
+ #interrupt-cells = <4>;
+
+ #address-cells = <2>;
+ #size-cells = <0>;
+ };
+
+ tlmm: pinctrl@f100000 {
+ compatible = "qcom,sm8650-tlmm";
+ reg = <0 0x0f100000 0 0x300000>;
+
+ interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>;
+
+ gpio-controller;
+ #gpio-cells = <2>;
+
+ interrupt-controller;
+ #interrupt-cells = <2>;
+
+ gpio-ranges = <&tlmm 0 0 211>;
+
+ wakeup-parent = <&pdc>;
+
+ hub_i2c0_data_clk: hub-i2c0-data-clk-state {
+ /* SDA, SCL */
+ pins = "gpio64", "gpio65";
+ function = "i2chub0_se0";
+ drive-strength = <2>;
+ bias-pull-up;
+ };
+
+ hub_i2c1_data_clk: hub-i2c1-data-clk-state {
+ /* SDA, SCL */
+ pins = "gpio66", "gpio67";
+ function = "i2chub0_se1";
+ drive-strength = <2>;
+ bias-pull-up;
+ };
+
+ hub_i2c2_data_clk: hub-i2c2-data-clk-state {
+ /* SDA, SCL */
+ pins = "gpio68", "gpio69";
+ function = "i2chub0_se2";
+ drive-strength = <2>;
+ bias-pull-up;
+ };
+
+ hub_i2c3_data_clk: hub-i2c3-data-clk-state {
+ /* SDA, SCL */
+ pins = "gpio70", "gpio71";
+ function = "i2chub0_se3";
+ drive-strength = <2>;
+ bias-pull-up;
+ };
+
+ hub_i2c4_data_clk: hub-i2c4-data-clk-state {
+ /* SDA, SCL */
+ pins = "gpio72", "gpio73";
+ function = "i2chub0_se4";
+ drive-strength = <2>;
+ bias-pull-up;
+ };
+
+ hub_i2c5_data_clk: hub-i2c5-data-clk-state {
+ /* SDA, SCL */
+ pins = "gpio74", "gpio75";
+ function = "i2chub0_se5";
+ drive-strength = <2>;
+ bias-pull-up;
+ };
+
+ hub_i2c6_data_clk: hub-i2c6-data-clk-state {
+ /* SDA, SCL */
+ pins = "gpio76", "gpio77";
+ function = "i2chub0_se6";
+ drive-strength = <2>;
+ bias-pull-up;
+ };
+
+ hub_i2c7_data_clk: hub-i2c7-data-clk-state {
+ /* SDA, SCL */
+ pins = "gpio78", "gpio79";
+ function = "i2chub0_se7";
+ drive-strength = <2>;
+ bias-pull-up;
+ };
+
+ hub_i2c8_data_clk: hub-i2c8-data-clk-state {
+ /* SDA, SCL */
+ pins = "gpio206", "gpio207";
+ function = "i2chub0_se8";
+ drive-strength = <2>;
+ bias-pull-up;
+ };
+
+ hub_i2c9_data_clk: hub-i2c9-data-clk-state {
+ /* SDA, SCL */
+ pins = "gpio80", "gpio81";
+ function = "i2chub0_se9";
+ drive-strength = <2>;
+ bias-pull-up;
+ };
+
+ pcie0_default_state: pcie0-default-state {
+ perst-pins {
+ pins = "gpio94";
+ function = "gpio";
+ drive-strength = <2>;
+ bias-pull-down;
+ };
+
+ clkreq-pins {
+ pins = "gpio95";
+ function = "pcie0_clk_req_n";
+ drive-strength = <2>;
+ bias-pull-up;
+ };
+
+ wake-pins {
+ pins = "gpio96";
+ function = "gpio";
+ drive-strength = <2>;
+ bias-pull-up;
+ };
+ };
+
+ pcie1_default_state: pcie1-default-state {
+ perst-pins {
+ pins = "gpio97";
+ function = "gpio";
+ drive-strength = <2>;
+ bias-pull-down;
+ };
+
+ clkreq-pins {
+ pins = "gpio98";
+ function = "pcie1_clk_req_n";
+ drive-strength = <2>;
+ bias-pull-up;
+ };
+
+ wake-pins {
+ pins = "gpio99";
+ function = "gpio";
+ drive-strength = <2>;
+ bias-pull-up;
+ };
+ };
+
+ qup_i2c0_data_clk: qup-i2c0-data-clk-state {
+ /* SDA, SCL */
+ pins = "gpio32", "gpio33";
+ function = "qup1_se0";
+ drive-strength = <2>;
+ bias-pull-up;
+ };
+
+ qup_i2c1_data_clk: qup-i2c1-data-clk-state {
+ /* SDA, SCL */
+ pins = "gpio36", "gpio37";
+ function = "qup1_se1";
+ drive-strength = <2>;
+ bias-pull-up;
+ };
+
+ qup_i2c2_data_clk: qup-i2c2-data-clk-state {
+ /* SDA, SCL */
+ pins = "gpio40", "gpio41";
+ function = "qup1_se2";
+ drive-strength = <2>;
+ bias-pull-up;
+ };
+
+ qup_i2c3_data_clk: qup-i2c3-data-clk-state {
+ /* SDA, SCL */
+ pins = "gpio44", "gpio45";
+ function = "qup1_se3";
+ drive-strength = <2>;
+ bias-pull-up;
+ };
+
+ qup_i2c4_data_clk: qup-i2c4-data-clk-state {
+ /* SDA, SCL */
+ pins = "gpio48", "gpio49";
+ function = "qup1_se4";
+ drive-strength = <2>;
+ bias-pull-up;
+ };
+
+ qup_i2c5_data_clk: qup-i2c5-data-clk-state {
+ /* SDA, SCL */
+ pins = "gpio52", "gpio53";
+ function = "qup1_se5";
+ drive-strength = <2>;
+ bias-pull-up;
+ };
+
+ qup_i2c6_data_clk: qup-i2c6-data-clk-state {
+ /* SDA, SCL */
+ pins = "gpio56", "gpio57";
+ function = "qup1_se6";
+ drive-strength = <2>;
+ bias-pull-up;
+ };
+
+ qup_i2c7_data_clk: qup-i2c7-data-clk-state {
+ /* SDA, SCL */
+ pins = "gpio60", "gpio61";
+ function = "qup1_se7";
+ drive-strength = <2>;
+ bias-pull-up;
+ };
+
+ qup_i2c8_data_clk: qup-i2c8-data-clk-state {
+ /* SDA, SCL */
+ pins = "gpio0", "gpio1";
+ function = "qup2_se0";
+ drive-strength = <2>;
+ bias-pull-up;
+ };
+
+ qup_i2c9_data_clk: qup-i2c9-data-clk-state {
+ /* SDA, SCL */
+ pins = "gpio4", "gpio5";
+ function = "qup2_se1";
+ drive-strength = <2>;
+ bias-pull-up;
+ };
+
+ qup_i2c10_data_clk: qup-i2c10-data-clk-state {
+ /* SDA, SCL */
+ pins = "gpio8", "gpio9";
+ function = "qup2_se2";
+ drive-strength = <2>;
+ bias-pull-up;
+ };
+
+ qup_i2c11_data_clk: qup-i2c11-data-clk-state {
+ /* SDA, SCL */
+ pins = "gpio12", "gpio13";
+ function = "qup2_se3";
+ drive-strength = <2>;
+ bias-pull-up;
+ };
+
+ qup_i2c12_data_clk: qup-i2c12-data-clk-state {
+ /* SDA, SCL */
+ pins = "gpio16", "gpio17";
+ function = "qup2_se4";
+ drive-strength = <2>;
+ bias-pull-up;
+ };
+
+ qup_i2c13_data_clk: qup-i2c13-data-clk-state {
+ /* SDA, SCL */
+ pins = "gpio20", "gpio21";
+ function = "qup2_se5";
+ drive-strength = <2>;
+ bias-pull-up;
+ };
+
+ qup_i2c14_data_clk: qup-i2c14-data-clk-state {
+ /* SDA, SCL */
+ pins = "gpio24", "gpio25";
+ function = "qup2_se6";
+ drive-strength = <2>;
+ bias-pull-up;
+ };
+
+ qup_spi0_cs: qup-spi0-cs-state {
+ pins = "gpio35";
+ function = "qup1_se0";
+ drive-strength = <6>;
+ bias-disable;
+ };
+
+ qup_spi0_data_clk: qup-spi0-data-clk-state {
+ /* MISO, MOSI, CLK */
+ pins = "gpio32", "gpio33", "gpio34";
+ function = "qup1_se0";
+ drive-strength = <6>;
+ bias-disable;
+ };
+
+ qup_spi1_cs: qup-spi1-cs-state {
+ pins = "gpio39";
+ function = "qup1_se1";
+ drive-strength = <6>;
+ bias-disable;
+ };
+
+ qup_spi1_data_clk: qup-spi1-data-clk-state {
+ /* MISO, MOSI, CLK */
+ pins = "gpio36", "gpio37", "gpio38";
+ function = "qup1_se1";
+ drive-strength = <6>;
+ bias-disable;
+ };
+
+ qup_spi2_cs: qup-spi2-cs-state {
+ pins = "gpio43";
+ function = "qup1_se2";
+ drive-strength = <6>;
+ bias-disable;
+ };
+
+ qup_spi2_data_clk: qup-spi2-data-clk-state {
+ /* MISO, MOSI, CLK */
+ pins = "gpio40", "gpio41", "gpio42";
+ function = "qup1_se2";
+ drive-strength = <6>;
+ bias-disable;
+ };
+
+ qup_spi3_cs: qup-spi3-cs-state {
+ pins = "gpio47";
+ function = "qup1_se3";
+ drive-strength = <6>;
+ bias-disable;
+ };
+
+ qup_spi3_data_clk: qup-spi3-data-clk-state {
+ /* MISO, MOSI, CLK */
+ pins = "gpio44", "gpio45", "gpio46";
+ function = "qup1_se3";
+ drive-strength = <6>;
+ bias-disable;
+ };
+
+ qup_spi4_cs: qup-spi4-cs-state {
+ pins = "gpio51";
+ function = "qup1_se4";
+ drive-strength = <6>;
+ bias-disable;
+ };
+
+ qup_spi4_data_clk: qup-spi4-data-clk-state {
+ /* MISO, MOSI, CLK */
+ pins = "gpio48", "gpio49", "gpio50";
+ function = "qup1_se4";
+ drive-strength = <6>;
+ bias-disable;
+ };
+
+ qup_spi5_cs: qup-spi5-cs-state {
+ pins = "gpio55";
+ function = "qup1_se5";
+ drive-strength = <6>;
+ bias-disable;
+ };
+
+ qup_spi5_data_clk: qup-spi5-data-clk-state {
+ /* MISO, MOSI, CLK */
+ pins = "gpio52", "gpio53", "gpio54";
+ function = "qup1_se5";
+ drive-strength = <6>;
+ bias-disable;
+ };
+
+ qup_spi6_cs: qup-spi6-cs-state {
+ pins = "gpio59";
+ function = "qup1_se6";
+ drive-strength = <6>;
+ bias-disable;
+ };
+
+ qup_spi6_data_clk: qup-spi6-data-clk-state {
+ /* MISO, MOSI, CLK */
+ pins = "gpio56", "gpio57", "gpio58";
+ function = "qup1_se6";
+ drive-strength = <6>;
+ bias-disable;
+ };
+
+ qup_spi7_cs: qup-spi7-cs-state {
+ pins = "gpio63";
+ function = "qup1_se7";
+ drive-strength = <6>;
+ bias-disable;
+ };
+
+ qup_spi7_data_clk: qup-spi7-data-clk-state {
+ /* MISO, MOSI, CLK */
+ pins = "gpio60", "gpio61", "gpio62";
+ function = "qup1_se7";
+ drive-strength = <6>;
+ bias-disable;
+ };
+
+ qup_spi8_cs: qup-spi8-cs-state {
+ pins = "gpio3";
+ function = "qup2_se0";
+ drive-strength = <6>;
+ bias-disable;
+ };
+
+ qup_spi8_data_clk: qup-spi8-data-clk-state {
+ /* MISO, MOSI, CLK */
+ pins = "gpio0", "gpio1", "gpio2";
+ function = "qup2_se0";
+ drive-strength = <6>;
+ bias-disable;
+ };
+
+ qup_spi9_cs: qup-spi9-cs-state {
+ pins = "gpio7";
+ function = "qup2_se1";
+ drive-strength = <6>;
+ bias-disable;
+ };
+
+ qup_spi9_data_clk: qup-spi9-data-clk-state {
+ /* MISO, MOSI, CLK */
+ pins = "gpio4", "gpio5", "gpio6";
+ function = "qup2_se1";
+ drive-strength = <6>;
+ bias-disable;
+ };
+
+ qup_spi10_cs: qup-spi10-cs-state {
+ pins = "gpio11";
+ function = "qup2_se2";
+ drive-strength = <6>;
+ bias-disable;
+ };
+
+ qup_spi10_data_clk: qup-spi10-data-clk-state {
+ /* MISO, MOSI, CLK */
+ pins = "gpio8", "gpio9", "gpio10";
+ function = "qup2_se2";
+ drive-strength = <6>;
+ bias-disable;
+ };
+
+ qup_spi11_cs: qup-spi11-cs-state {
+ pins = "gpio15";
+ function = "qup2_se3";
+ drive-strength = <6>;
+ bias-disable;
+ };
+
+ qup_spi11_data_clk: qup-spi11-data-clk-state {
+ /* MISO, MOSI, CLK */
+ pins = "gpio12", "gpio13", "gpio14";
+ function = "qup2_se3";
+ drive-strength = <6>;
+ bias-disable;
+ };
+
+ qup_spi12_cs: qup-spi12-cs-state {
+ pins = "gpio19";
+ function = "qup2_se4";
+ drive-strength = <6>;
+ bias-disable;
+ };
+
+ qup_spi12_data_clk: qup-spi12-data-clk-state {
+ /* MISO, MOSI, CLK */
+ pins = "gpio16", "gpio17", "gpio18";
+ function = "qup2_se4";
+ drive-strength = <6>;
+ bias-disable;
+ };
+
+ qup_spi13_cs: qup-spi13-cs-state {
+ pins = "gpio23";
+ function = "qup2_se5";
+ drive-strength = <6>;
+ bias-disable;
+ };
+
+ qup_spi13_data_clk: qup-spi13-data-clk-state {
+ /* MISO, MOSI, CLK */
+ pins = "gpio20", "gpio21", "gpio22";
+ function = "qup2_se5";
+ drive-strength = <6>;
+ bias-disable;
+ };
+
+ qup_spi14_cs: qup-spi14-cs-state {
+ pins = "gpio27";
+ function = "qup2_se6";
+ drive-strength = <6>;
+ bias-disable;
+ };
+
+ qup_spi14_data_clk: qup-spi14-data-clk-state {
+ /* MISO, MOSI, CLK */
+ pins = "gpio24", "gpio25", "gpio26";
+ function = "qup2_se6";
+ drive-strength = <6>;
+ bias-disable;
+ };
+
+ qup_uart14_default: qup-uart14-default-state {
+ /* TX, RX */
+ pins = "gpio26", "gpio27";
+ function = "qup2_se6";
+ drive-strength = <2>;
+ bias-pull-up;
+ };
+
+ qup_uart14_cts_rts: qup-uart14-cts-rts-state {
+ /* CTS, RTS */
+ pins = "gpio24", "gpio25";
+ function = "qup2_se6";
+ drive-strength = <2>;
+ bias-pull-down;
+ };
+
+ qup_uart15_default: qup-uart15-default-state {
+ /* TX, RX */
+ pins = "gpio30", "gpio31";
+ function = "qup2_se7";
+ drive-strength = <2>;
+ bias-disable;
+ };
+
+ sdc2_sleep: sdc2-sleep-state {
+ clk-pins {
+ pins = "sdc2_clk";
+ drive-strength = <2>;
+ bias-disable;
+ };
+
+ cmd-pins {
+ pins = "sdc2_cmd";
+ drive-strength = <2>;
+ bias-pull-up;
+ };
+
+ data-pins {
+ pins = "sdc2_data";
+ drive-strength = <2>;
+ bias-pull-up;
+ };
+ };
+
+ sdc2_default: sdc2-default-state {
+ clk-pins {
+ pins = "sdc2_clk";
+ drive-strength = <16>;
+ bias-disable;
+ };
+
+ cmd-pins {
+ pins = "sdc2_cmd";
+ drive-strength = <10>;
+ bias-pull-up;
+ };
+
+ data-pins {
+ pins = "sdc2_data";
+ drive-strength = <10>;
+ bias-pull-up;
+ };
+ };
+ };
+
+ apps_smmu: iommu@15000000 {
+ compatible = "qcom,sm8650-smmu-500", "qcom,smmu-500", "arm,mmu-500";
+ reg = <0 0x15000000 0 0x100000>;
+
+ interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 181 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 182 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 319 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 322 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 323 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 324 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 325 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 333 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 336 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 337 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 338 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 339 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 340 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 341 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 342 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 343 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 344 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 345 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 395 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 396 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 397 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 398 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 399 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 400 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 401 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 402 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 403 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 404 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 405 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 406 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 407 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 408 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 409 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 418 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 419 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 412 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 421 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 706 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 423 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 424 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 425 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 689 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 690 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 691 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 692 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 693 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 694 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 695 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 696 IRQ_TYPE_LEVEL_HIGH>;
+
+ #iommu-cells = <2>;
+ #global-interrupts = <1>;
+
+ dma-coherent;
+ };
+
+ intc: interrupt-controller@17100000 {
+ compatible = "arm,gic-v3";
+ reg = <0 0x17100000 0 0x10000>, /* GICD */
+ <0 0x17180000 0 0x200000>; /* GICR * 8 */
+
+ interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_LOW>;
+
+ #interrupt-cells = <3>;
+ interrupt-controller;
+
+ #redistributor-regions = <1>;
+ redistributor-stride = <0 0x40000>;
+
+ #address-cells = <2>;
+ #size-cells = <2>;
+ ranges;
+
+ gic_its: msi-controller@17140000 {
+ compatible = "arm,gic-v3-its";
+ reg = <0 0x17140000 0 0x20000>;
+
+ msi-controller;
+ #msi-cells = <1>;
+ };
+ };
+
+ timer@17420000 {
+ compatible = "arm,armv7-timer-mem";
+ reg = <0 0x17420000 0 0x1000>;
+
+ ranges = <0 0 0 0x20000000>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ frame@17421000 {
+ reg = <0x17421000 0x1000>,
+ <0x17422000 0x1000>;
+
+ interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
+
+ frame-number = <0>;
+ };
+
+ frame@17423000 {
+ reg = <0x17423000 0x1000>;
+
+ interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
+
+ frame-number = <1>;
+
+ status = "disabled";
+ };
+
+ frame@17425000 {
+ reg = <0x17425000 0x1000>;
+
+ interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
+
+ frame-number = <2>;
+
+ status = "disabled";
+ };
+
+ frame@17427000 {
+ reg = <0x17427000 0x1000>;
+
+ interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
+
+ frame-number = <3>;
+
+ status = "disabled";
+ };
+
+ frame@17429000 {
+ reg = <0x17429000 0x1000>;
+
+ interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
+
+ frame-number = <4>;
+
+ status = "disabled";
+ };
+
+ frame@1742b000 {
+ reg = <0x1742b000 0x1000>;
+
+ interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
+
+ frame-number = <5>;
+
+ status = "disabled";
+ };
+
+ frame@1742d000 {
+ reg = <0x1742d000 0x1000>;
+
+ interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
+
+ frame-number = <6>;
+
+ status = "disabled";
+ };
+ };
+
+ apps_rsc: rsc@17a00000 {
+ compatible = "qcom,rpmh-rsc";
+ reg = <0 0x17a00000 0 0x10000>,
+ <0 0x17a10000 0 0x10000>,
+ <0 0x17a20000 0 0x10000>,
+ <0 0x17a30000 0 0x10000>;
+ reg-names = "drv-0",
+ "drv-1",
+ "drv-2";
+
+ interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
+
+ power-domains = <&CLUSTER_PD>;
+
+ qcom,tcs-offset = <0xd00>;
+ qcom,drv-id = <2>;
+ qcom,tcs-config = <ACTIVE_TCS 3>, <SLEEP_TCS 2>,
+ <WAKE_TCS 2>, <CONTROL_TCS 0>;
+
+ label = "apps_rsc";
+
+ apps_bcm_voter: bcm-voter {
+ compatible = "qcom,bcm-voter";
+ };
+
+ rpmhcc: clock-controller {
+ compatible = "qcom,sm8650-rpmh-clk";
+
+ clocks = <&xo_board>;
+ clock-names = "xo";
+
+ #clock-cells = <1>;
+ };
+
+ rpmhpd: power-controller {
+ compatible = "qcom,sm8650-rpmhpd";
+
+ operating-points-v2 = <&rpmhpd_opp_table>;
+
+ #power-domain-cells = <1>;
+
+ rpmhpd_opp_table: opp-table {
+ compatible = "operating-points-v2";
+
+ rpmhpd_opp_ret: opp-16 {
+ opp-level = <RPMH_REGULATOR_LEVEL_RETENTION>;
+ };
+
+ rpmhpd_opp_min_svs: opp-48 {
+ opp-level = <RPMH_REGULATOR_LEVEL_MIN_SVS>;
+ };
+
+ rpmhpd_opp_low_svs_d2: opp-52 {
+ opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS_D2>;
+ };
+
+ rpmhpd_opp_low_svs_d1: opp-56 {
+ opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS_D1>;
+ };
+
+ rpmhpd_opp_low_svs_d0: opp-60 {
+ opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS_D0>;
+ };
+
+ rpmhpd_opp_low_svs: opp-64 {
+ opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>;
+ };
+
+ rpmhpd_opp_low_svs_l1: opp-80 {
+ opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS_L1>;
+ };
+
+ rpmhpd_opp_svs: opp-128 {
+ opp-level = <RPMH_REGULATOR_LEVEL_SVS>;
+ };
+
+ rpmhpd_opp_svs_l0: opp-144 {
+ opp-level = <RPMH_REGULATOR_LEVEL_SVS_L0>;
+ };
+
+ rpmhpd_opp_svs_l1: opp-192 {
+ opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>;
+ };
+
+ rpmhpd_opp_nom: opp-256 {
+ opp-level = <RPMH_REGULATOR_LEVEL_NOM>;
+ };
+
+ rpmhpd_opp_nom_l1: opp-320 {
+ opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>;
+ };
+
+ rpmhpd_opp_nom_l2: opp-336 {
+ opp-level = <RPMH_REGULATOR_LEVEL_NOM_L2>;
+ };
+
+ rpmhpd_opp_turbo: opp-384 {
+ opp-level = <RPMH_REGULATOR_LEVEL_TURBO>;
+ };
+
+ rpmhpd_opp_turbo_l1: opp-416 {
+ opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L1>;
+ };
+ };
+ };
+ };
+
+ cpufreq_hw: cpufreq@17d91000 {
+ compatible = "qcom,sm8650-cpufreq-epss", "qcom,cpufreq-epss";
+ reg = <0 0x17d91000 0 0x1000>,
+ <0 0x17d92000 0 0x1000>,
+ <0 0x17d93000 0 0x1000>,
+ <0 0x17d94000 0 0x1000>;
+ reg-names = "freq-domain0",
+ "freq-domain1",
+ "freq-domain2",
+ "freq-domain3";
+
+ interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 738 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "dcvsh-irq-0",
+ "dcvsh-irq-1",
+ "dcvsh-irq-2",
+ "dcvsh-irq-3";
+
+ clocks = <&bi_tcxo_div2>, <&gcc GCC_GPLL0>;
+ clock-names = "xo", "alternate";
+
+ #freq-domain-cells = <1>;
+ #clock-cells = <1>;
+ };
+
+ pmu@24091000 {
+ compatible = "qcom,sm8650-llcc-bwmon", "qcom,sc7280-llcc-bwmon";
+ reg = <0 0x24091000 0 0x1000>;
+
+ interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>;
+
+ interconnects = <&mc_virt MASTER_LLCC QCOM_ICC_TAG_ACTIVE_ONLY
+ &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ACTIVE_ONLY>;
+
+ operating-points-v2 = <&llcc_bwmon_opp_table>;
+
+ llcc_bwmon_opp_table: opp-table {
+ compatible = "operating-points-v2";
+
+ opp-0 {
+ opp-peak-kBps = <2086000>;
+ };
+
+ opp-1 {
+ opp-peak-kBps = <2929000>;
+ };
+
+ opp-2 {
+ opp-peak-kBps = <5931000>;
+ };
+
+ opp-3 {
+ opp-peak-kBps = <6515000>;
+ };
+
+ opp-4 {
+ opp-peak-kBps = <7980000>;
+ };
+
+ opp-5 {
+ opp-peak-kBps = <10437000>;
+ };
+
+ opp-6 {
+ opp-peak-kBps = <12157000>;
+ };
+
+ opp-7 {
+ opp-peak-kBps = <14060000>;
+ };
+
+ opp-8 {
+ opp-peak-kBps = <16113000>;
+ };
+ };
+ };
+
+ pmu@240b7400 {
+ compatible = "qcom,sm8650-cpu-bwmon", "qcom,sdm845-bwmon";
+ reg = <0 0x240b7400 0 0x600>;
+
+ interrupts = <GIC_SPI 581 IRQ_TYPE_LEVEL_HIGH>;
+
+ interconnects = <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY
+ &gem_noc SLAVE_LLCC QCOM_ICC_TAG_ACTIVE_ONLY>;
+
+ operating-points-v2 = <&cpu_bwmon_opp_table>;
+
+ cpu_bwmon_opp_table: opp-table {
+ compatible = "operating-points-v2";
+
+ opp-0 {
+ opp-peak-kBps = <4577000>;
+ };
+
+ opp-1 {
+ opp-peak-kBps = <7110000>;
+ };
+
+ opp-2 {
+ opp-peak-kBps = <9155000>;
+ };
+
+ opp-3 {
+ opp-peak-kBps = <12298000>;
+ };
+
+ opp-4 {
+ opp-peak-kBps = <14236000>;
+ };
+
+ opp-5 {
+ opp-peak-kBps = <16265000>;
+ };
+ };
+ };
+
+ gem_noc: interconnect@24100000 {
+ compatible = "qcom,sm8650-gem-noc";
+ reg = <0 0x24100000 0 0xc5080>;
+
+ qcom,bcm-voters = <&apps_bcm_voter>;
+
+ #interconnect-cells = <2>;
+ };
+
+ system-cache-controller@25000000 {
+ compatible = "qcom,sm8650-llcc";
+ reg = <0 0x25000000 0 0x200000>,
+ <0 0x25400000 0 0x200000>,
+ <0 0x25200000 0 0x200000>,
+ <0 0x25600000 0 0x200000>,
+ <0 0x25800000 0 0x200000>;
+ reg-names = "llcc0_base",
+ "llcc1_base",
+ "llcc2_base",
+ "llcc3_base",
+ "llcc_broadcast_base";
+
+ interrupts = <GIC_SPI 266 IRQ_TYPE_LEVEL_HIGH>;
+ };
+
+ remoteproc_adsp: remoteproc@30000000 {
+ compatible = "qcom,sm8650-adsp-pas";
+ reg = <0 0x30000000 0 0x100>;
+
+ interrupts-extended = <&pdc 6 IRQ_TYPE_EDGE_RISING>,
+ <&smp2p_adsp_in 0 IRQ_TYPE_EDGE_RISING>,
+ <&smp2p_adsp_in 1 IRQ_TYPE_EDGE_RISING>,
+ <&smp2p_adsp_in 2 IRQ_TYPE_EDGE_RISING>,
+ <&smp2p_adsp_in 3 IRQ_TYPE_EDGE_RISING>;
+ interrupt-names = "wdog",
+ "fatal",
+ "ready",
+ "handover",
+ "stop-ack";
+
+ clocks = <&rpmhcc RPMH_CXO_CLK>;
+ clock-names = "xo";
+
+ interconnects = <&lpass_lpicx_noc MASTER_LPASS_PROC QCOM_ICC_TAG_ALWAYS
+ &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
+
+ power-domains = <&rpmhpd RPMHPD_LCX>,
+ <&rpmhpd RPMHPD_LMX>;
+ power-domain-names = "lcx",
+ "lmx";
+
+ memory-region = <&adspslpi_mem>, <&q6_adsp_dtb_mem>;
+
+ qcom,qmp = <&aoss_qmp>;
+
+ qcom,smem-states = <&smp2p_adsp_out 0>;
+ qcom,smem-state-names = "stop";
+
+ status = "disabled";
+
+ remoteproc_adsp_glink: glink-edge {
+ interrupts-extended = <&ipcc IPCC_CLIENT_LPASS
+ IPCC_MPROC_SIGNAL_GLINK_QMP
+ IRQ_TYPE_EDGE_RISING>;
+
+ mboxes = <&ipcc IPCC_CLIENT_LPASS
+ IPCC_MPROC_SIGNAL_GLINK_QMP>;
+
+ qcom,remote-pid = <2>;
+
+ label = "lpass";
+
+ fastrpc {
+ compatible = "qcom,fastrpc";
+
+ qcom,glink-channels = "fastrpcglink-apps-dsp";
+
+ label = "adsp";
+
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ compute-cb@3 {
+ compatible = "qcom,fastrpc-compute-cb";
+ reg = <3>;
+
+ iommus = <&apps_smmu 0x1003 0x80>,
+ <&apps_smmu 0x1043 0x20>;
+ };
+
+ compute-cb@4 {
+ compatible = "qcom,fastrpc-compute-cb";
+ reg = <4>;
+
+ iommus = <&apps_smmu 0x1004 0x80>,
+ <&apps_smmu 0x1044 0x20>;
+ };
+
+ compute-cb@5 {
+ compatible = "qcom,fastrpc-compute-cb";
+ reg = <5>;
+
+ iommus = <&apps_smmu 0x1005 0x80>,
+ <&apps_smmu 0x1045 0x20>;
+ };
+
+ compute-cb@6 {
+ compatible = "qcom,fastrpc-compute-cb";
+ reg = <6>;
+
+ iommus = <&apps_smmu 0x1006 0x80>,
+ <&apps_smmu 0x1046 0x20>;
+ };
+
+ compute-cb@7 {
+ compatible = "qcom,fastrpc-compute-cb";
+ reg = <7>;
+
+ iommus = <&apps_smmu 0x1007 0x40>,
+ <&apps_smmu 0x1067 0x0>,
+ <&apps_smmu 0x1087 0x0>;
+ };
+ };
+
+ gpr {
+ compatible = "qcom,gpr";
+ qcom,glink-channels = "adsp_apps";
+ qcom,domain = <GPR_DOMAIN_ID_ADSP>;
+ qcom,intents = <512 20>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ q6apm: service@1 {
+ compatible = "qcom,q6apm";
+ reg = <GPR_APM_MODULE_IID>;
+ #sound-dai-cells = <0>;
+ qcom,protection-domain = "avs/audio",
+ "msm/adsp/audio_pd";
+
+ q6apmbedai: bedais {
+ compatible = "qcom,q6apm-lpass-dais";
+ #sound-dai-cells = <1>;
+ };
+
+ q6apmdai: dais {
+ compatible = "qcom,q6apm-dais";
+ iommus = <&apps_smmu 0x1001 0x80>,
+ <&apps_smmu 0x1061 0x0>;
+ };
+ };
+
+ q6prm: service@2 {
+ compatible = "qcom,q6prm";
+ reg = <GPR_PRM_MODULE_IID>;
+ qcom,protection-domain = "avs/audio",
+ "msm/adsp/audio_pd";
+
+ q6prmcc: clock-controller {
+ compatible = "qcom,q6prm-lpass-clocks";
+ #clock-cells = <2>;
+ };
+ };
+ };
+ };
+ };
+
+ nsp_noc: interconnect@320c0000 {
+ compatible = "qcom,sm8650-nsp-noc";
+ reg = <0 0x320c0000 0 0xf080>;
+
+ qcom,bcm-voters = <&apps_bcm_voter>;
+
+ #interconnect-cells = <2>;
+ };
+
+ remoteproc_cdsp: remoteproc@32300000 {
+ compatible = "qcom,sm8650-cdsp-pas";
+ reg = <0 0x32300000 0 0x1400000>;
+
+ interrupts-extended = <&intc GIC_SPI 578 IRQ_TYPE_EDGE_RISING>,
+ <&smp2p_cdsp_in 0 IRQ_TYPE_EDGE_RISING>,
+ <&smp2p_cdsp_in 1 IRQ_TYPE_EDGE_RISING>,
+ <&smp2p_cdsp_in 2 IRQ_TYPE_EDGE_RISING>,
+ <&smp2p_cdsp_in 3 IRQ_TYPE_EDGE_RISING>;
+ interrupt-names = "wdog",
+ "fatal",
+ "ready",
+ "handover",
+ "stop-ack";
+
+ clocks = <&rpmhcc RPMH_CXO_CLK>;
+ clock-names = "xo";
+
+ interconnects = <&nsp_noc MASTER_CDSP_PROC QCOM_ICC_TAG_ALWAYS
+ &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
+
+ power-domains = <&rpmhpd RPMHPD_CX>,
+ <&rpmhpd RPMHPD_MXC>,
+ <&rpmhpd RPMHPD_NSP>;
+ power-domain-names = "cx",
+ "mxc",
+ "nsp";
+
+ memory-region = <&cdsp_mem>, <&q6_cdsp_dtb_mem>, <&global_sync_mem>;
+
+ qcom,qmp = <&aoss_qmp>;
+
+ qcom,smem-states = <&smp2p_cdsp_out 0>;
+ qcom,smem-state-names = "stop";
+
+ status = "disabled";
+
+ glink-edge {
+ interrupts-extended = <&ipcc IPCC_CLIENT_CDSP
+ IPCC_MPROC_SIGNAL_GLINK_QMP
+ IRQ_TYPE_EDGE_RISING>;
+
+ mboxes = <&ipcc IPCC_CLIENT_CDSP
+ IPCC_MPROC_SIGNAL_GLINK_QMP>;
+
+ qcom,remote-pid = <5>;
+
+ label = "cdsp";
+
+ fastrpc {
+ compatible = "qcom,fastrpc";
+
+ qcom,glink-channels = "fastrpcglink-apps-dsp";
+
+ label = "cdsp";
+
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ compute-cb@1 {
+ compatible = "qcom,fastrpc-compute-cb";
+ reg = <1>;
+
+ iommus = <&apps_smmu 0x1961 0x0>,
+ <&apps_smmu 0x0c01 0x20>,
+ <&apps_smmu 0x19c1 0x0>;
+ };
+
+ compute-cb@2 {
+ compatible = "qcom,fastrpc-compute-cb";
+ reg = <2>;
+
+ iommus = <&apps_smmu 0x1962 0x0>,
+ <&apps_smmu 0x0c02 0x20>,
+ <&apps_smmu 0x19c2 0x0>;
+ };
+
+ compute-cb@3 {
+ compatible = "qcom,fastrpc-compute-cb";
+ reg = <3>;
+
+ iommus = <&apps_smmu 0x1963 0x0>,
+ <&apps_smmu 0x0c03 0x20>,
+ <&apps_smmu 0x19c3 0x0>;
+ };
+
+ compute-cb@4 {
+ compatible = "qcom,fastrpc-compute-cb";
+ reg = <4>;
+
+ iommus = <&apps_smmu 0x1964 0x0>,
+ <&apps_smmu 0x0c04 0x20>,
+ <&apps_smmu 0x19c4 0x0>;
+ };
+
+ compute-cb@5 {
+ compatible = "qcom,fastrpc-compute-cb";
+ reg = <5>;
+
+ iommus = <&apps_smmu 0x1965 0x0>,
+ <&apps_smmu 0x0c05 0x20>,
+ <&apps_smmu 0x19c5 0x0>;
+ };
+
+ compute-cb@6 {
+ compatible = "qcom,fastrpc-compute-cb";
+ reg = <6>;
+
+ iommus = <&apps_smmu 0x1966 0x0>,
+ <&apps_smmu 0x0c06 0x20>,
+ <&apps_smmu 0x19c6 0x0>;
+ };
+
+ compute-cb@7 {
+ compatible = "qcom,fastrpc-compute-cb";
+ reg = <7>;
+
+ iommus = <&apps_smmu 0x1967 0x0>,
+ <&apps_smmu 0x0c07 0x20>,
+ <&apps_smmu 0x19c7 0x0>;
+ };
+
+ compute-cb@8 {
+ compatible = "qcom,fastrpc-compute-cb";
+ reg = <8>;
+
+ iommus = <&apps_smmu 0x1968 0x0>,
+ <&apps_smmu 0x0c08 0x20>,
+ <&apps_smmu 0x19c8 0x0>;
+ };
+ };
+ };
+ };
+ };
+
+ thermal-zones {
+ aoss0-thermal {
+ polling-delay-passive = <0>;
+ polling-delay = <0>;
+ thermal-sensors = <&tsens0 0>;
+
+ trips {
+ trip-point0 {
+ temperature = <90000>;
+ hysteresis = <2000>;
+ type = "hot";
+ };
+
+ aoss0-critical {
+ temperature = <110000>;
+ hysteresis = <0>;
+ type = "critical";
+ };
+ };
+ };
+
+ cpuss0-thermal {
+ polling-delay-passive = <0>;
+ polling-delay = <0>;
+ thermal-sensors = <&tsens0 1>;
+
+ trips {
+ trip-point0 {
+ temperature = <90000>;
+ hysteresis = <2000>;
+ type = "hot";
+ };
+
+ cpuss0-critical {
+ temperature = <110000>;
+ hysteresis = <0>;
+ type = "critical";
+ };
+ };
+ };
+
+ cpuss1-thermal {
+ polling-delay-passive = <0>;
+ polling-delay = <0>;
+ thermal-sensors = <&tsens0 2>;
+
+ trips {
+ trip-point0 {
+ temperature = <90000>;
+ hysteresis = <2000>;
+ type = "hot";
+ };
+
+ cpuss1-critical {
+ temperature = <110000>;
+ hysteresis = <0>;
+ type = "critical";
+ };
+ };
+ };
+
+ cpuss2-thermal {
+ polling-delay-passive = <0>;
+ polling-delay = <0>;
+ thermal-sensors = <&tsens0 3>;
+
+ trips {
+ trip-point0 {
+ temperature = <90000>;
+ hysteresis = <2000>;
+ type = "hot";
+ };
+
+ cpuss2-critical {
+ temperature = <110000>;
+ hysteresis = <0>;
+ type = "critical";
+ };
+ };
+ };
+
+ cpuss3-thermal {
+ polling-delay-passive = <0>;
+ polling-delay = <0>;
+ thermal-sensors = <&tsens0 4>;
+
+ trips {
+ trip-point0 {
+ temperature = <90000>;
+ hysteresis = <2000>;
+ type = "hot";
+ };
+
+ cpuss3-critical {
+ temperature = <110000>;
+ hysteresis = <0>;
+ type = "critical";
+ };
+ };
+ };
+
+ cpu2-top-thermal {
+ polling-delay-passive = <0>;
+ polling-delay = <0>;
+ thermal-sensors = <&tsens0 5>;
+
+ trips {
+ trip-point0 {
+ temperature = <90000>;
+ hysteresis = <2000>;
+ type = "passive";
+ };
+
+ trip-point1 {
+ temperature = <95000>;
+ hysteresis = <2000>;
+ type = "passive";
+ };
+
+ cpu2-critical {
+ temperature = <110000>;
+ hysteresis = <1000>;
+ type = "critical";
+ };
+ };
+ };
+
+ cpu2-bottom-thermal {
+ polling-delay-passive = <0>;
+ polling-delay = <0>;
+ thermal-sensors = <&tsens0 6>;
+
+ trips {
+ trip-point0 {
+ temperature = <90000>;
+ hysteresis = <2000>;
+ type = "passive";
+ };
+
+ trip-point1 {
+ temperature = <95000>;
+ hysteresis = <2000>;
+ type = "passive";
+ };
+
+ cpu2-critical {
+ temperature = <110000>;
+ hysteresis = <1000>;
+ type = "critical";
+ };
+ };
+ };
+
+ cpu3-top-thermal {
+ polling-delay-passive = <0>;
+ polling-delay = <0>;
+ thermal-sensors = <&tsens0 7>;
+
+ trips {
+ trip-point0 {
+ temperature = <90000>;
+ hysteresis = <2000>;
+ type = "passive";
+ };
+
+ trip-point1 {
+ temperature = <95000>;
+ hysteresis = <2000>;
+ type = "passive";
+ };
+
+ cpu3-critical {
+ temperature = <110000>;
+ hysteresis = <1000>;
+ type = "critical";
+ };
+ };
+ };
+
+ cpu3-bottom-thermal {
+ polling-delay-passive = <0>;
+ polling-delay = <0>;
+ thermal-sensors = <&tsens0 8>;
+
+ trips {
+ trip-point0 {
+ temperature = <90000>;
+ hysteresis = <2000>;
+ type = "passive";
+ };
+
+ trip-point1 {
+ temperature = <95000>;
+ hysteresis = <2000>;
+ type = "passive";
+ };
+
+ cpu3-critical {
+ temperature = <110000>;
+ hysteresis = <1000>;
+ type = "critical";
+ };
+ };
+ };
+
+ cpu4-top-thermal {
+ polling-delay-passive = <0>;
+ polling-delay = <0>;
+ thermal-sensors = <&tsens0 9>;
+
+ trips {
+ trip-point0 {
+ temperature = <90000>;
+ hysteresis = <2000>;
+ type = "passive";
+ };
+
+ trip-point1 {
+ temperature = <95000>;
+ hysteresis = <2000>;
+ type = "passive";
+ };
+
+ cpu4-critical {
+ temperature = <110000>;
+ hysteresis = <1000>;
+ type = "critical";
+ };
+ };
+ };
+
+ cpu4-bottom-thermal {
+ polling-delay-passive = <0>;
+ polling-delay = <0>;
+ thermal-sensors = <&tsens0 10>;
+
+ trips {
+ trip-point0 {
+ temperature = <90000>;
+ hysteresis = <2000>;
+ type = "passive";
+ };
+
+ trip-point1 {
+ temperature = <95000>;
+ hysteresis = <2000>;
+ type = "passive";
+ };
+
+ cpu4-critical {
+ temperature = <110000>;
+ hysteresis = <1000>;
+ type = "critical";
+ };
+ };
+ };
+
+ cpu5-top-thermal {
+ polling-delay-passive = <0>;
+ polling-delay = <0>;
+ thermal-sensors = <&tsens0 11>;
+
+ trips {
+ trip-point0 {
+ temperature = <90000>;
+ hysteresis = <2000>;
+ type = "passive";
+ };
+
+ trip-point1 {
+ temperature = <95000>;
+ hysteresis = <2000>;
+ type = "passive";
+ };
+
+ cpu5-critical {
+ temperature = <110000>;
+ hysteresis = <1000>;
+ type = "critical";
+ };
+ };
+ };
+
+ cpu5-bottom-thermal {
+ polling-delay-passive = <0>;
+ polling-delay = <0>;
+ thermal-sensors = <&tsens0 12>;
+
+ trips {
+ trip-point0 {
+ temperature = <90000>;
+ hysteresis = <2000>;
+ type = "passive";
+ };
+
+ trip-point1 {
+ temperature = <95000>;
+ hysteresis = <2000>;
+ type = "passive";
+ };
+
+ cpu5-critical {
+ temperature = <110000>;
+ hysteresis = <1000>;
+ type = "critical";
+ };
+ };
+ };
+
+ cpu6-top-thermal {
+ polling-delay-passive = <0>;
+ polling-delay = <0>;
+ thermal-sensors = <&tsens0 13>;
+
+ trips {
+ trip-point0 {
+ temperature = <90000>;
+ hysteresis = <2000>;
+ type = "passive";
+ };
+
+ trip-point1 {
+ temperature = <95000>;
+ hysteresis = <2000>;
+ type = "passive";
+ };
+
+ cpu6-critical {
+ temperature = <110000>;
+ hysteresis = <1000>;
+ type = "critical";
+ };
+ };
+ };
+
+ cpu6-bottom-thermal {
+ polling-delay-passive = <0>;
+ polling-delay = <0>;
+ thermal-sensors = <&tsens0 14>;
+
+ trips {
+ trip-point0 {
+ temperature = <90000>;
+ hysteresis = <2000>;
+ type = "passive";
+ };
+
+ trip-point1 {
+ temperature = <95000>;
+ hysteresis = <2000>;
+ type = "passive";
+ };
+
+ cpu6-critical {
+ temperature = <110000>;
+ hysteresis = <1000>;
+ type = "critical";
+ };
+ };
+ };
+
+ aoss1-thermal {
+ polling-delay-passive = <0>;
+ polling-delay = <0>;
+ thermal-sensors = <&tsens1 0>;
+
+ trips {
+ trip-point0 {
+ temperature = <90000>;
+ hysteresis = <2000>;
+ type = "hot";
+ };
+
+ aoss1-critical {
+ temperature = <110000>;
+ hysteresis = <0>;
+ type = "critical";
+ };
+ };
+ };
+
+ cpu7-top-thermal {
+ polling-delay-passive = <0>;
+ polling-delay = <0>;
+ thermal-sensors = <&tsens1 1>;
+
+ trips {
+ trip-point0 {
+ temperature = <90000>;
+ hysteresis = <2000>;
+ type = "passive";
+ };
+
+ trip-point1 {
+ temperature = <95000>;
+ hysteresis = <2000>;
+ type = "passive";
+ };
+
+ cpu7-critical {
+ temperature = <110000>;
+ hysteresis = <1000>;
+ type = "critical";
+ };
+ };
+ };
+
+ cpu7-middle-thermal {
+ polling-delay-passive = <0>;
+ polling-delay = <0>;
+ thermal-sensors = <&tsens1 2>;
+
+ trips {
+ trip-point0 {
+ temperature = <90000>;
+ hysteresis = <2000>;
+ type = "passive";
+ };
+
+ trip-point1 {
+ temperature = <95000>;
+ hysteresis = <2000>;
+ type = "passive";
+ };
+
+ cpu7-critical {
+ temperature = <110000>;
+ hysteresis = <1000>;
+ type = "critical";
+ };
+ };
+ };
+
+ cpu7-bottom-thermal {
+ polling-delay-passive = <0>;
+ polling-delay = <0>;
+ thermal-sensors = <&tsens1 3>;
+
+ trips {
+ trip-point0 {
+ temperature = <90000>;
+ hysteresis = <2000>;
+ type = "passive";
+ };
+
+ trip-point1 {
+ temperature = <95000>;
+ hysteresis = <2000>;
+ type = "passive";
+ };
+
+ cpu7-critical {
+ temperature = <110000>;
+ hysteresis = <1000>;
+ type = "critical";
+ };
+ };
+ };
+
+ cpu0-thermal {
+ polling-delay-passive = <0>;
+ polling-delay = <0>;
+ thermal-sensors = <&tsens1 4>;
+
+ trips {
+ trip-point0 {
+ temperature = <90000>;
+ hysteresis = <2000>;
+ type = "passive";
+ };
+
+ trip-point1 {
+ temperature = <95000>;
+ hysteresis = <2000>;
+ type = "passive";
+ };
+
+ cpu0-critical {
+ temperature = <110000>;
+ hysteresis = <1000>;
+ type = "critical";
+ };
+ };
+ };
+
+ cpu1-thermal {
+ polling-delay-passive = <0>;
+ polling-delay = <0>;
+ thermal-sensors = <&tsens1 5>;
+
+ trips {
+ trip-point0 {
+ temperature = <90000>;
+ hysteresis = <2000>;
+ type = "passive";
+ };
+
+ trip-point1 {
+ temperature = <95000>;
+ hysteresis = <2000>;
+ type = "passive";
+ };
+
+ cpu1-critical {
+ temperature = <110000>;
+ hysteresis = <1000>;
+ type = "critical";
+ };
+ };
+ };
+
+ nsphvx0-thermal {
+ polling-delay-passive = <10>;
+ polling-delay = <0>;
+ thermal-sensors = <&tsens2 6>;
+
+ trips {
+ trip-point0 {
+ temperature = <90000>;
+ hysteresis = <2000>;
+ type = "hot";
+ };
+
+ nsphvx1-critical {
+ temperature = <110000>;
+ hysteresis = <0>;
+ type = "critical";
+ };
+ };
+ };
+
+ nsphvx1-thermal {
+ polling-delay-passive = <10>;
+ polling-delay = <0>;
+ thermal-sensors = <&tsens2 7>;
+
+ trips {
+ trip-point0 {
+ temperature = <90000>;
+ hysteresis = <2000>;
+ type = "hot";
+ };
+
+ nsphvx1-critical {
+ temperature = <110000>;
+ hysteresis = <0>;
+ type = "critical";
+ };
+ };
+ };
+
+ nsphmx0-thermal {
+ polling-delay-passive = <10>;
+ polling-delay = <0>;
+ thermal-sensors = <&tsens2 8>;
+
+ trips {
+ trip-point0 {
+ temperature = <90000>;
+ hysteresis = <2000>;
+ type = "hot";
+ };
+
+ nsphmx0-critical {
+ temperature = <110000>;
+ hysteresis = <0>;
+ type = "critical";
+ };
+ };
+ };
+
+ nsphmx1-thermal {
+ polling-delay-passive = <10>;
+ polling-delay = <0>;
+ thermal-sensors = <&tsens2 9>;
+
+ trips {
+ trip-point0 {
+ temperature = <90000>;
+ hysteresis = <2000>;
+ type = "hot";
+ };
+
+ nsphmx1-critical {
+ temperature = <110000>;
+ hysteresis = <0>;
+ type = "critical";
+ };
+ };
+ };
+
+ nsphmx2-thermal {
+ polling-delay-passive = <10>;
+ polling-delay = <0>;
+ thermal-sensors = <&tsens2 10>;
+
+ trips {
+ trip-point0 {
+ temperature = <90000>;
+ hysteresis = <2000>;
+ type = "hot";
+ };
+
+ nsphmx2-critical {
+ temperature = <110000>;
+ hysteresis = <0>;
+ type = "critical";
+ };
+ };
+ };
+
+ nsphmx3-thermal {
+ polling-delay-passive = <10>;
+ polling-delay = <0>;
+ thermal-sensors = <&tsens2 11>;
+
+ trips {
+ trip-point0 {
+ temperature = <90000>;
+ hysteresis = <2000>;
+ type = "hot";
+ };
+
+ nsphmx3-critical {
+ temperature = <110000>;
+ hysteresis = <0>;
+ type = "critical";
+ };
+ };
+ };
+
+ video-thermal {
+ polling-delay-passive = <10>;
+ polling-delay = <0>;
+ thermal-sensors = <&tsens1 12>;
+
+ trips {
+ trip-point0 {
+ temperature = <90000>;
+ hysteresis = <2000>;
+ type = "hot";
+ };
+
+ video-critical {
+ temperature = <110000>;
+ hysteresis = <0>;
+ type = "critical";
+ };
+ };
+ };
+
+ ddr-thermal {
+ polling-delay-passive = <10>;
+ polling-delay = <0>;
+ thermal-sensors = <&tsens1 13>;
+
+ trips {
+ trip-point0 {
+ temperature = <90000>;
+ hysteresis = <2000>;
+ type = "hot";
+ };
+
+ ddr-critical {
+ temperature = <110000>;
+ hysteresis = <0>;
+ type = "critical";
+ };
+ };
+ };
+
+ camera0-thermal {
+ polling-delay-passive = <0>;
+ polling-delay = <0>;
+ thermal-sensors = <&tsens1 14>;
+
+ trips {
+ trip-point0 {
+ temperature = <90000>;
+ hysteresis = <2000>;
+ type = "hot";
+ };
+
+ camera0-critical {
+ temperature = <110000>;
+ hysteresis = <0>;
+ type = "critical";
+ };
+ };
+ };
+
+ camera1-thermal {
+ polling-delay-passive = <0>;
+ polling-delay = <0>;
+ thermal-sensors = <&tsens1 15>;
+
+ trips {
+ trip-point0 {
+ temperature = <90000>;
+ hysteresis = <2000>;
+ type = "hot";
+ };
+
+ camera1-critical {
+ temperature = <110000>;
+ hysteresis = <0>;
+ type = "critical";
+ };
+ };
+ };
+
+ aoss2-thermal {
+ polling-delay-passive = <0>;
+ polling-delay = <0>;
+ thermal-sensors = <&tsens2 0>;
+
+ trips {
+ trip-point0 {
+ temperature = <90000>;
+ hysteresis = <2000>;
+ type = "hot";
+ };
+
+ aoss2-critical {
+ temperature = <110000>;
+ hysteresis = <0>;
+ type = "critical";
+ };
+ };
+ };
+
+ gpuss0-thermal {
+ polling-delay-passive = <10>;
+ polling-delay = <0>;
+ thermal-sensors = <&tsens2 1>;
+
+ trips {
+ trip-point0 {
+ temperature = <90000>;
+ hysteresis = <2000>;
+ type = "hot";
+ };
+
+ gpuss0-critical {
+ temperature = <110000>;
+ hysteresis = <0>;
+ type = "critical";
+ };
+ };
+ };
+
+ gpuss1-thermal {
+ polling-delay-passive = <10>;
+ polling-delay = <0>;
+ thermal-sensors = <&tsens2 2>;
+
+ trips {
+ trip-point0 {
+ temperature = <90000>;
+ hysteresis = <2000>;
+ type = "hot";
+ };
+
+ gpuss1-critical {
+ temperature = <110000>;
+ hysteresis = <0>;
+ type = "critical";
+ };
+ };
+ };
+
+ gpuss2-thermal {
+ polling-delay-passive = <10>;
+ polling-delay = <0>;
+ thermal-sensors = <&tsens2 3>;
+
+ trips {
+ trip-point0 {
+ temperature = <90000>;
+ hysteresis = <2000>;
+ type = "hot";
+ };
+
+ gpuss2-critical {
+ temperature = <110000>;
+ hysteresis = <0>;
+ type = "critical";
+ };
+ };
+ };
+
+ gpuss3-thermal {
+ polling-delay-passive = <10>;
+ polling-delay = <0>;
+ thermal-sensors = <&tsens2 4>;
+
+ trips {
+ trip-point0 {
+ temperature = <90000>;
+ hysteresis = <2000>;
+ type = "hot";
+ };
+
+ gpuss3-critical {
+ temperature = <110000>;
+ hysteresis = <0>;
+ type = "critical";
+ };
+ };
+ };
+
+ gpuss4-thermal {
+ polling-delay-passive = <10>;
+ polling-delay = <0>;
+ thermal-sensors = <&tsens2 5>;
+
+ trips {
+ trip-point0 {
+ temperature = <90000>;
+ hysteresis = <2000>;
+ type = "hot";
+ };
+
+ gpuss4-critical {
+ temperature = <110000>;
+ hysteresis = <0>;
+ type = "critical";
+ };
+ };
+ };
+
+ gpuss5-thermal {
+ polling-delay-passive = <10>;
+ polling-delay = <0>;
+ thermal-sensors = <&tsens2 6>;
+
+ trips {
+ trip-point0 {
+ temperature = <90000>;
+ hysteresis = <2000>;
+ type = "hot";
+ };
+
+ gpuss5-critical {
+ temperature = <110000>;
+ hysteresis = <0>;
+ type = "critical";
+ };
+ };
+ };
+
+ gpuss6-thermal {
+ polling-delay-passive = <10>;
+ polling-delay = <0>;
+ thermal-sensors = <&tsens2 7>;
+
+ trips {
+ trip-point0 {
+ temperature = <90000>;
+ hysteresis = <2000>;
+ type = "hot";
+ };
+
+ gpuss6-critical {
+ temperature = <110000>;
+ hysteresis = <0>;
+ type = "critical";
+ };
+ };
+ };
+
+ gpuss7-thermal {
+ polling-delay-passive = <10>;
+ polling-delay = <0>;
+ thermal-sensors = <&tsens2 8>;
+
+ trips {
+ trip-point0 {
+ temperature = <90000>;
+ hysteresis = <2000>;
+ type = "hot";
+ };
+
+ gpuss7-critical {
+ temperature = <110000>;
+ hysteresis = <0>;
+ type = "critical";
+ };
+ };
+ };
+
+ modem0-thermal {
+ polling-delay-passive = <0>;
+ polling-delay = <0>;
+ thermal-sensors = <&tsens2 9>;
+
+ trips {
+ trip-point0 {
+ temperature = <90000>;
+ hysteresis = <2000>;
+ type = "hot";
+ };
+
+ modem0-critical {
+ temperature = <110000>;
+ hysteresis = <0>;
+ type = "critical";
+ };
+ };
+ };
+
+ modem1-thermal {
+ polling-delay-passive = <0>;
+ polling-delay = <0>;
+ thermal-sensors = <&tsens2 10>;
+
+ trips {
+ trip-point0 {
+ temperature = <90000>;
+ hysteresis = <2000>;
+ type = "hot";
+ };
+
+ modem1-critical {
+ temperature = <110000>;
+ hysteresis = <0>;
+ type = "critical";
+ };
+ };
+ };
+
+ modem2-thermal {
+ polling-delay-passive = <0>;
+ polling-delay = <0>;
+ thermal-sensors = <&tsens2 11>;
+
+ trips {
+ trip-point0 {
+ temperature = <90000>;
+ hysteresis = <2000>;
+ type = "hot";
+ };
+
+ modem2-critical {
+ temperature = <110000>;
+ hysteresis = <0>;
+ type = "critical";
+ };
+ };
+ };
+
+ modem3-thermal {
+ polling-delay-passive = <0>;
+ polling-delay = <0>;
+ thermal-sensors = <&tsens2 12>;
+
+ trips {
+ trip-point0 {
+ temperature = <90000>;
+ hysteresis = <2000>;
+ type = "hot";
+ };
+
+ modem3-critical {
+ temperature = <110000>;
+ hysteresis = <0>;
+ type = "critical";
+ };
+ };
+ };
+ };
+
+ timer {
+ compatible = "arm,armv8-timer";
+
+ interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>,
+ <GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>,
+ <GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>,
+ <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>;
+ };
+};
diff --git a/dts/upstream/src/arm64/qcom/x1e80100-crd.dts b/dts/upstream/src/arm64/qcom/x1e80100-crd.dts
new file mode 100644
index 0000000..7532d8e
--- /dev/null
+++ b/dts/upstream/src/arm64/qcom/x1e80100-crd.dts
@@ -0,0 +1,424 @@
+// SPDX-License-Identifier: BSD-3-Clause
+/*
+ * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved.
+ */
+
+/dts-v1/;
+
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/regulator/qcom,rpmh-regulator.h>
+
+#include "x1e80100.dtsi"
+
+/ {
+ model = "Qualcomm Technologies, Inc. X1E80100 CRD";
+ compatible = "qcom,x1e80100-crd", "qcom,x1e80100";
+
+ aliases {
+ serial0 = &uart21;
+ };
+
+ chosen {
+ stdout-path = "serial0:115200n8";
+ };
+
+ vph_pwr: vph-pwr-regulator {
+ compatible = "regulator-fixed";
+
+ regulator-name = "vph_pwr";
+ regulator-min-microvolt = <3700000>;
+ regulator-max-microvolt = <3700000>;
+
+ regulator-always-on;
+ regulator-boot-on;
+ };
+
+ vreg_edp_3p3: regulator-edp-3p3 {
+ compatible = "regulator-fixed";
+
+ regulator-name = "VREG_EDP_3P3";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+
+ gpio = <&tlmm 70 GPIO_ACTIVE_HIGH>;
+ enable-active-high;
+
+ pinctrl-0 = <&edp_reg_en>;
+ pinctrl-names = "default";
+
+ regulator-always-on;
+ regulator-boot-on;
+ };
+};
+
+&apps_rsc {
+ regulators-0 {
+ compatible = "qcom,pm8550-rpmh-regulators";
+ qcom,pmic-id = "b";
+
+ vdd-bob1-supply = <&vph_pwr>;
+ vdd-bob2-supply = <&vph_pwr>;
+ vdd-l1-l4-l10-supply = <&vreg_s4c_1p8>;
+ vdd-l2-l13-l14-supply = <&vreg_bob1>;
+ vdd-l5-l16-supply = <&vreg_bob1>;
+ vdd-l6-l7-supply = <&vreg_bob2>;
+ vdd-l8-l9-supply = <&vreg_bob1>;
+ vdd-l12-supply = <&vreg_s5j_1p2>;
+ vdd-l15-supply = <&vreg_s4c_1p8>;
+ vdd-l17-supply = <&vreg_bob2>;
+
+ vreg_bob1: bob1 {
+ regulator-name = "vreg_bob1";
+ regulator-min-microvolt = <3008000>;
+ regulator-max-microvolt = <3960000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_bob2: bob2 {
+ regulator-name = "vreg_bob2";
+ regulator-min-microvolt = <2504000>;
+ regulator-max-microvolt = <3008000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_l1b_1p8: ldo1 {
+ regulator-name = "vreg_l1b_1p8";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_l2b_3p0: ldo2 {
+ regulator-name = "vreg_l2b_3p0";
+ regulator-min-microvolt = <3072000>;
+ regulator-max-microvolt = <3100000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_l4b_1p8: ldo4 {
+ regulator-name = "vreg_l4b_1p8";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_l5b_3p0: ldo5 {
+ regulator-name = "vreg_l5b_3p0";
+ regulator-min-microvolt = <3000000>;
+ regulator-max-microvolt = <3000000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_l6b_1p8: ldo6 {
+ regulator-name = "vreg_l6b_1p8";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <2960000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_l7b_2p8: ldo7 {
+ regulator-name = "vreg_l7b_2p8";
+ regulator-min-microvolt = <2800000>;
+ regulator-max-microvolt = <2800000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_l8b_3p0: ldo8 {
+ regulator-name = "vreg_l8b_3p0";
+ regulator-min-microvolt = <3072000>;
+ regulator-max-microvolt = <3072000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_l9b_2p9: ldo9 {
+ regulator-name = "vreg_l9b_2p9";
+ regulator-min-microvolt = <2960000>;
+ regulator-max-microvolt = <2960000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_l10b_1p8: ldo10 {
+ regulator-name = "vreg_l10b_1p8";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_l12b_1p2: ldo12 {
+ regulator-name = "vreg_l12b_1p2";
+ regulator-min-microvolt = <1200000>;
+ regulator-max-microvolt = <1200000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_l13b_3p0: ldo13 {
+ regulator-name = "vreg_l13b_3p0";
+ regulator-min-microvolt = <3072000>;
+ regulator-max-microvolt = <3100000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_l14b_3p0: ldo14 {
+ regulator-name = "vreg_l14b_3p0";
+ regulator-min-microvolt = <3072000>;
+ regulator-max-microvolt = <3072000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_l15b_1p8: ldo15 {
+ regulator-name = "vreg_l15b_1p8";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_l16b_2p9: ldo16 {
+ regulator-name = "vreg_l16b_2p9";
+ regulator-min-microvolt = <2912000>;
+ regulator-max-microvolt = <2912000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_l17b_2p5: ldo17 {
+ regulator-name = "vreg_l17b_2p5";
+ regulator-min-microvolt = <2504000>;
+ regulator-max-microvolt = <2504000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+ };
+
+ regulators-1 {
+ compatible = "qcom,pm8550ve-rpmh-regulators";
+ qcom,pmic-id = "c";
+
+ vdd-l1-supply = <&vreg_s5j_1p2>;
+ vdd-l2-supply = <&vreg_s1f_0p7>;
+ vdd-l3-supply = <&vreg_s1f_0p7>;
+ vdd-s4-supply = <&vph_pwr>;
+
+ vreg_s4c_1p8: smps4 {
+ regulator-name = "vreg_s4c_1p8";
+ regulator-min-microvolt = <1856000>;
+ regulator-max-microvolt = <2000000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_l1c_1p2: ldo1 {
+ regulator-name = "vreg_l1c_1p2";
+ regulator-min-microvolt = <1200000>;
+ regulator-max-microvolt = <1200000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_l2c_0p8: ldo2 {
+ regulator-name = "vreg_l2c_0p8";
+ regulator-min-microvolt = <880000>;
+ regulator-max-microvolt = <920000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_l3c_0p8: ldo3 {
+ regulator-name = "vreg_l3c_0p8";
+ regulator-min-microvolt = <880000>;
+ regulator-max-microvolt = <920000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+ };
+
+ regulators-2 {
+ compatible = "qcom,pmc8380-rpmh-regulators";
+ qcom,pmic-id = "d";
+
+ vdd-l1-supply = <&vreg_s1f_0p7>;
+ vdd-l2-supply = <&vreg_s1f_0p7>;
+ vdd-l3-supply = <&vreg_s4c_1p8>;
+ vdd-s1-supply = <&vph_pwr>;
+
+ vreg_l1d_0p8: ldo1 {
+ regulator-name = "vreg_l1d_0p8";
+ regulator-min-microvolt = <880000>;
+ regulator-max-microvolt = <920000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_l2d_0p9: ldo2 {
+ regulator-name = "vreg_l2d_0p9";
+ regulator-min-microvolt = <912000>;
+ regulator-max-microvolt = <920000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_l3d_1p8: ldo3 {
+ regulator-name = "vreg_l3d_1p8";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+ };
+
+ regulators-3 {
+ compatible = "qcom,pmc8380-rpmh-regulators";
+ qcom,pmic-id = "e";
+
+ vdd-l2-supply = <&vreg_s1f_0p7>;
+ vdd-l3-supply = <&vreg_s5j_1p2>;
+
+ vreg_l2e_0p8: ldo2 {
+ regulator-name = "vreg_l2e_0p8";
+ regulator-min-microvolt = <880000>;
+ regulator-max-microvolt = <920000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_l3e_1p2: ldo3 {
+ regulator-name = "vreg_l3e_1p2";
+ regulator-min-microvolt = <1200000>;
+ regulator-max-microvolt = <1200000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+ };
+
+ regulators-4 {
+ compatible = "qcom,pmc8380-rpmh-regulators";
+ qcom,pmic-id = "f";
+
+ vdd-l1-supply = <&vreg_s5j_1p2>;
+ vdd-l2-supply = <&vreg_s5j_1p2>;
+ vdd-l3-supply = <&vreg_s5j_1p2>;
+ vdd-s1-supply = <&vph_pwr>;
+
+ vreg_s1f_0p7: smps1 {
+ regulator-name = "vreg_s1f_0p7";
+ regulator-min-microvolt = <700000>;
+ regulator-max-microvolt = <1100000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_l1f_1p0: ldo1 {
+ regulator-name = "vreg_l1f_1p0";
+ regulator-min-microvolt = <1024000>;
+ regulator-max-microvolt = <1024000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_l2f_1p0: ldo2 {
+ regulator-name = "vreg_l2f_1p0";
+ regulator-min-microvolt = <1024000>;
+ regulator-max-microvolt = <1024000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_l3f_1p0: ldo3 {
+ regulator-name = "vreg_l3f_1p0";
+ regulator-min-microvolt = <1024000>;
+ regulator-max-microvolt = <1024000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+ };
+
+ regulators-6 {
+ compatible = "qcom,pm8550ve-rpmh-regulators";
+ qcom,pmic-id = "i";
+
+ vdd-l1-supply = <&vreg_s4c_1p8>;
+ vdd-l2-supply = <&vreg_s5j_1p2>;
+ vdd-l3-supply = <&vreg_s1f_0p7>;
+ vdd-s1-supply = <&vph_pwr>;
+ vdd-s2-supply = <&vph_pwr>;
+
+ vreg_s1i_0p9: smps1 {
+ regulator-name = "vreg_s1i_0p9";
+ regulator-min-microvolt = <900000>;
+ regulator-max-microvolt = <920000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_s2i_1p0: smps2 {
+ regulator-name = "vreg_s2i_1p0";
+ regulator-min-microvolt = <1000000>;
+ regulator-max-microvolt = <1100000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_l1i_1p8: ldo1 {
+ regulator-name = "vreg_l1i_1p8";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_l2i_1p2: ldo2 {
+ regulator-name = "vreg_l2i_1p2";
+ regulator-min-microvolt = <1200000>;
+ regulator-max-microvolt = <1200000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_l3i_0p8: ldo3 {
+ regulator-name = "vreg_l3i_0p8";
+ regulator-min-microvolt = <880000>;
+ regulator-max-microvolt = <920000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+ };
+
+ regulators-7 {
+ compatible = "qcom,pm8550ve-rpmh-regulators";
+ qcom,pmic-id = "j";
+
+ vdd-l1-supply = <&vreg_s1f_0p7>;
+ vdd-l2-supply = <&vreg_s5j_1p2>;
+ vdd-l3-supply = <&vreg_s1f_0p7>;
+ vdd-s5-supply = <&vph_pwr>;
+
+ vreg_s5j_1p2: smps5 {
+ regulator-name = "vreg_s5j_1p2";
+ regulator-min-microvolt = <1256000>;
+ regulator-max-microvolt = <1304000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_l1j_0p8: ldo1 {
+ regulator-name = "vreg_l1j_0p8";
+ regulator-min-microvolt = <880000>;
+ regulator-max-microvolt = <920000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_l2j_1p2: ldo2 {
+ regulator-name = "vreg_l2j_1p2";
+ regulator-min-microvolt = <1200000>;
+ regulator-max-microvolt = <1200000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_l3j_0p8: ldo3 {
+ regulator-name = "vreg_l3j_0p8";
+ regulator-min-microvolt = <880000>;
+ regulator-max-microvolt = <920000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+ };
+};
+
+&qupv3_2 {
+ status = "okay";
+};
+
+&tlmm {
+ gpio-reserved-ranges = <34 2>, /* Unused */
+ <44 4>, /* SPI (TPM) */
+ <238 1>; /* UFS Reset */
+
+ edp_reg_en: edp-reg-en-state {
+ pins = "gpio70";
+ function = "gpio";
+ drive-strength = <16>;
+ bias-disable;
+ };
+};
+
+&uart21 {
+ compatible = "qcom,geni-debug-uart";
+ status = "okay";
+};
diff --git a/dts/upstream/src/arm64/qcom/x1e80100-qcp.dts b/dts/upstream/src/arm64/qcom/x1e80100-qcp.dts
new file mode 100644
index 0000000..a37ad94
--- /dev/null
+++ b/dts/upstream/src/arm64/qcom/x1e80100-qcp.dts
@@ -0,0 +1,399 @@
+// SPDX-License-Identifier: BSD-3-Clause
+/*
+ * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved.
+ */
+
+/dts-v1/;
+
+#include <dt-bindings/regulator/qcom,rpmh-regulator.h>
+
+#include "x1e80100.dtsi"
+
+/ {
+ model = "Qualcomm Technologies, Inc. X1E80100 QCP";
+ compatible = "qcom,x1e80100-qcp", "qcom,x1e80100";
+
+ aliases {
+ serial0 = &uart21;
+ };
+
+ chosen {
+ stdout-path = "serial0:115200n8";
+ };
+
+ vph_pwr: vph-pwr-regulator {
+ compatible = "regulator-fixed";
+
+ regulator-name = "vph_pwr";
+ regulator-min-microvolt = <3700000>;
+ regulator-max-microvolt = <3700000>;
+
+ regulator-always-on;
+ regulator-boot-on;
+ };
+};
+
+&apps_rsc {
+ regulators-0 {
+ compatible = "qcom,pm8550-rpmh-regulators";
+ qcom,pmic-id = "b";
+
+ vdd-bob1-supply = <&vph_pwr>;
+ vdd-bob2-supply = <&vph_pwr>;
+ vdd-l1-l4-l10-supply = <&vreg_s4c_1p8>;
+ vdd-l2-l13-l14-supply = <&vreg_bob1>;
+ vdd-l5-l16-supply = <&vreg_bob1>;
+ vdd-l6-l7-supply = <&vreg_bob2>;
+ vdd-l8-l9-supply = <&vreg_bob1>;
+ vdd-l12-supply = <&vreg_s5j_1p2>;
+ vdd-l15-supply = <&vreg_s4c_1p8>;
+ vdd-l17-supply = <&vreg_bob2>;
+
+ vreg_bob1: bob1 {
+ regulator-name = "vreg_bob1";
+ regulator-min-microvolt = <3008000>;
+ regulator-max-microvolt = <3960000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_bob2: bob2 {
+ regulator-name = "vreg_bob2";
+ regulator-min-microvolt = <2504000>;
+ regulator-max-microvolt = <3008000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_l1b_1p8: ldo1 {
+ regulator-name = "vreg_l1b_1p8";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_l2b_3p0: ldo2 {
+ regulator-name = "vreg_l2b_3p0";
+ regulator-min-microvolt = <3072000>;
+ regulator-max-microvolt = <3100000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_l4b_1p8: ldo4 {
+ regulator-name = "vreg_l4b_1p8";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_l5b_3p0: ldo5 {
+ regulator-name = "vreg_l5b_3p0";
+ regulator-min-microvolt = <3000000>;
+ regulator-max-microvolt = <3000000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_l6b_1p8: ldo6 {
+ regulator-name = "vreg_l6b_1p8";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <2960000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_l7b_2p8: ldo7 {
+ regulator-name = "vreg_l7b_2p8";
+ regulator-min-microvolt = <2800000>;
+ regulator-max-microvolt = <2800000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_l8b_3p0: ldo8 {
+ regulator-name = "vreg_l8b_3p0";
+ regulator-min-microvolt = <3072000>;
+ regulator-max-microvolt = <3072000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_l9b_2p9: ldo9 {
+ regulator-name = "vreg_l9b_2p9";
+ regulator-min-microvolt = <2960000>;
+ regulator-max-microvolt = <2960000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_l10b_1p8: ldo10 {
+ regulator-name = "vreg_l10b_1p8";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_l12b_1p2: ldo12 {
+ regulator-name = "vreg_l12b_1p2";
+ regulator-min-microvolt = <1200000>;
+ regulator-max-microvolt = <1200000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_l13b_3p0: ldo13 {
+ regulator-name = "vreg_l13b_3p0";
+ regulator-min-microvolt = <3072000>;
+ regulator-max-microvolt = <3100000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_l14b_3p0: ldo14 {
+ regulator-name = "vreg_l14b_3p0";
+ regulator-min-microvolt = <3072000>;
+ regulator-max-microvolt = <3072000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_l15b_1p8: ldo15 {
+ regulator-name = "vreg_l15b_1p8";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_l16b_2p9: ldo16 {
+ regulator-name = "vreg_l16b_2p9";
+ regulator-min-microvolt = <2912000>;
+ regulator-max-microvolt = <2912000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_l17b_2p5: ldo17 {
+ regulator-name = "vreg_l17b_2p5";
+ regulator-min-microvolt = <2504000>;
+ regulator-max-microvolt = <2504000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+ };
+
+ regulators-1 {
+ compatible = "qcom,pm8550ve-rpmh-regulators";
+ qcom,pmic-id = "c";
+
+ vdd-l1-supply = <&vreg_s5j_1p2>;
+ vdd-l2-supply = <&vreg_s1f_0p7>;
+ vdd-l3-supply = <&vreg_s1f_0p7>;
+ vdd-s4-supply = <&vph_pwr>;
+
+ vreg_s4c_1p8: smps4 {
+ regulator-name = "vreg_s4c_1p8";
+ regulator-min-microvolt = <1856000>;
+ regulator-max-microvolt = <2000000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_l1c_1p2: ldo1 {
+ regulator-name = "vreg_l1c_1p2";
+ regulator-min-microvolt = <1200000>;
+ regulator-max-microvolt = <1200000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_l2c_0p8: ldo2 {
+ regulator-name = "vreg_l2c_0p8";
+ regulator-min-microvolt = <880000>;
+ regulator-max-microvolt = <920000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_l3c_0p8: ldo3 {
+ regulator-name = "vreg_l3c_0p8";
+ regulator-min-microvolt = <880000>;
+ regulator-max-microvolt = <920000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+ };
+
+ regulators-2 {
+ compatible = "qcom,pmc8380-rpmh-regulators";
+ qcom,pmic-id = "d";
+
+ vdd-l1-supply = <&vreg_s1f_0p7>;
+ vdd-l2-supply = <&vreg_s1f_0p7>;
+ vdd-l3-supply = <&vreg_s4c_1p8>;
+ vdd-s1-supply = <&vph_pwr>;
+
+ vreg_l1d_0p8: ldo1 {
+ regulator-name = "vreg_l1d_0p8";
+ regulator-min-microvolt = <880000>;
+ regulator-max-microvolt = <920000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_l2d_0p9: ldo2 {
+ regulator-name = "vreg_l2d_0p9";
+ regulator-min-microvolt = <912000>;
+ regulator-max-microvolt = <920000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_l3d_1p8: ldo3 {
+ regulator-name = "vreg_l3d_1p8";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+ };
+
+ regulators-3 {
+ compatible = "qcom,pmc8380-rpmh-regulators";
+ qcom,pmic-id = "e";
+
+ vdd-l2-supply = <&vreg_s1f_0p7>;
+ vdd-l3-supply = <&vph_pwr>;
+
+ vreg_l2e_0p8: ldo2 {
+ regulator-name = "vreg_l2e_0p8";
+ regulator-min-microvolt = <880000>;
+ regulator-max-microvolt = <920000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_l3e_1p2: ldo3 {
+ regulator-name = "vreg_l3e_1p2";
+ regulator-min-microvolt = <1200000>;
+ regulator-max-microvolt = <1200000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+ };
+
+ regulators-4 {
+ compatible = "qcom,pmc8380-rpmh-regulators";
+ qcom,pmic-id = "f";
+
+ vdd-l1-supply = <&vreg_s5j_1p2>;
+ vdd-l2-supply = <&vreg_s5j_1p2>;
+ vdd-l3-supply = <&vreg_s5j_1p2>;
+ vdd-s1-supply = <&vph_pwr>;
+
+ vreg_s1f_0p7: smps1 {
+ regulator-name = "vreg_s1f_0p7";
+ regulator-min-microvolt = <700000>;
+ regulator-max-microvolt = <1100000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_l1f_1p0: ldo1 {
+ regulator-name = "vreg_l1f_1p0";
+ regulator-min-microvolt = <1024000>;
+ regulator-max-microvolt = <1024000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_l2f_1p0: ldo2 {
+ regulator-name = "vreg_l2f_1p0";
+ regulator-min-microvolt = <1024000>;
+ regulator-max-microvolt = <1024000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_l3f_1p0: ldo3 {
+ regulator-name = "vreg_l3f_1p0";
+ regulator-min-microvolt = <1024000>;
+ regulator-max-microvolt = <1024000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+ };
+
+ regulators-6 {
+ compatible = "qcom,pm8550ve-rpmh-regulators";
+ qcom,pmic-id = "i";
+
+ vdd-l1-supply = <&vreg_s4c_1p8>;
+ vdd-l2-supply = <&vreg_s5j_1p2>;
+ vdd-l3-supply = <&vreg_s1f_0p7>;
+ vdd-s1-supply = <&vph_pwr>;
+ vdd-s2-supply = <&vph_pwr>;
+
+ vreg_s1i_0p9: smps1 {
+ regulator-name = "vreg_s1i_0p9";
+ regulator-min-microvolt = <900000>;
+ regulator-max-microvolt = <920000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_s2i_1p0: smps2 {
+ regulator-name = "vreg_s2i_1p0";
+ regulator-min-microvolt = <1000000>;
+ regulator-max-microvolt = <1100000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_l1i_1p8: ldo1 {
+ regulator-name = "vreg_l1i_1p8";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_l2i_1p2: ldo2 {
+ regulator-name = "vreg_l2i_1p2";
+ regulator-min-microvolt = <1200000>;
+ regulator-max-microvolt = <1200000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_l3i_0p8: ldo3 {
+ regulator-name = "vreg_l3i_0p8";
+ regulator-min-microvolt = <880000>;
+ regulator-max-microvolt = <920000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+ };
+
+ regulators-7 {
+ compatible = "qcom,pm8550ve-rpmh-regulators";
+ qcom,pmic-id = "j";
+
+ vdd-l1-supply = <&vreg_s1f_0p7>;
+ vdd-l2-supply = <&vph_pwr>;
+ vdd-l3-supply = <&vreg_s1f_0p7>;
+ vdd-s5-supply = <&vph_pwr>;
+
+ vreg_s5j_1p2: smps5 {
+ regulator-name = "vreg_s5j_1p2";
+ regulator-min-microvolt = <1256000>;
+ regulator-max-microvolt = <1304000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_l1j_0p8: ldo1 {
+ regulator-name = "vreg_l1j_0p8";
+ regulator-min-microvolt = <880000>;
+ regulator-max-microvolt = <920000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_l2j_1p2: ldo2 {
+ regulator-name = "vreg_l2j_1p2";
+ regulator-min-microvolt = <1200000>;
+ regulator-max-microvolt = <1200000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_l3j_0p8: ldo3 {
+ regulator-name = "vreg_l3j_0p8";
+ regulator-min-microvolt = <880000>;
+ regulator-max-microvolt = <920000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+ };
+};
+
+&qupv3_2 {
+ status = "okay";
+};
+
+&tlmm {
+ gpio-reserved-ranges = <33 3>, /* Unused */
+ <44 4>, /* SPI (TPM) */
+ <238 1>; /* UFS Reset */
+};
+
+&uart21 {
+ compatible = "qcom,geni-debug-uart";
+ status = "okay";
+};
diff --git a/dts/upstream/src/arm64/qcom/x1e80100.dtsi b/dts/upstream/src/arm64/qcom/x1e80100.dtsi
new file mode 100644
index 0000000..6f75fc3
--- /dev/null
+++ b/dts/upstream/src/arm64/qcom/x1e80100.dtsi
@@ -0,0 +1,3527 @@
+// SPDX-License-Identifier: BSD-3-Clause
+/*
+ * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved.
+ */
+
+#include <dt-bindings/clock/qcom,rpmh.h>
+#include <dt-bindings/clock/qcom,x1e80100-gcc.h>
+#include <dt-bindings/dma/qcom-gpi.h>
+#include <dt-bindings/interconnect/qcom,icc.h>
+#include <dt-bindings/interconnect/qcom,x1e80100-rpmh.h>
+#include <dt-bindings/interrupt-controller/arm-gic.h>
+#include <dt-bindings/power/qcom,rpmhpd.h>
+#include <dt-bindings/power/qcom-rpmpd.h>
+#include <dt-bindings/soc/qcom,rpmh-rsc.h>
+
+/ {
+ interrupt-parent = <&intc>;
+
+ #address-cells = <2>;
+ #size-cells = <2>;
+
+ chosen { };
+
+ clocks {
+ xo_board: xo-board {
+ compatible = "fixed-clock";
+ clock-frequency = <76800000>;
+ #clock-cells = <0>;
+ };
+
+ sleep_clk: sleep-clk {
+ compatible = "fixed-clock";
+ clock-frequency = <32000>;
+ #clock-cells = <0>;
+ };
+
+ bi_tcxo_div2: bi-tcxo-div2-clk {
+ compatible = "fixed-factor-clock";
+ #clock-cells = <0>;
+
+ clocks = <&rpmhcc RPMH_CXO_CLK>;
+ clock-mult = <1>;
+ clock-div = <2>;
+ };
+
+ bi_tcxo_ao_div2: bi-tcxo-ao-div2-clk {
+ compatible = "fixed-factor-clock";
+ #clock-cells = <0>;
+
+ clocks = <&rpmhcc RPMH_CXO_CLK_A>;
+ clock-mult = <1>;
+ clock-div = <2>;
+ };
+ };
+
+ cpus {
+ #address-cells = <2>;
+ #size-cells = <0>;
+
+ CPU0: cpu@0 {
+ device_type = "cpu";
+ compatible = "qcom,oryon";
+ reg = <0x0 0x0>;
+ enable-method = "psci";
+ next-level-cache = <&L2_0>;
+ power-domains = <&CPU_PD0>;
+ power-domain-names = "psci";
+ cpu-idle-states = <&CLUSTER_C4>;
+
+ L2_0: l2-cache {
+ compatible = "cache";
+ cache-level = <2>;
+ cache-unified;
+ };
+ };
+
+ CPU1: cpu@100 {
+ device_type = "cpu";
+ compatible = "qcom,oryon";
+ reg = <0x0 0x100>;
+ enable-method = "psci";
+ next-level-cache = <&L2_0>;
+ power-domains = <&CPU_PD1>;
+ power-domain-names = "psci";
+ cpu-idle-states = <&CLUSTER_C4>;
+ };
+
+ CPU2: cpu@200 {
+ device_type = "cpu";
+ compatible = "qcom,oryon";
+ reg = <0x0 0x200>;
+ enable-method = "psci";
+ next-level-cache = <&L2_0>;
+ power-domains = <&CPU_PD2>;
+ power-domain-names = "psci";
+ cpu-idle-states = <&CLUSTER_C4>;
+ };
+
+ CPU3: cpu@300 {
+ device_type = "cpu";
+ compatible = "qcom,oryon";
+ reg = <0x0 0x300>;
+ enable-method = "psci";
+ next-level-cache = <&L2_0>;
+ power-domains = <&CPU_PD3>;
+ power-domain-names = "psci";
+ cpu-idle-states = <&CLUSTER_C4>;
+ };
+
+ CPU4: cpu@10000 {
+ device_type = "cpu";
+ compatible = "qcom,oryon";
+ reg = <0x0 0x10000>;
+ enable-method = "psci";
+ next-level-cache = <&L2_1>;
+ power-domains = <&CPU_PD4>;
+ power-domain-names = "psci";
+ cpu-idle-states = <&CLUSTER_C4>;
+
+ L2_1: l2-cache {
+ compatible = "cache";
+ cache-level = <2>;
+ cache-unified;
+ };
+ };
+
+ CPU5: cpu@10100 {
+ device_type = "cpu";
+ compatible = "qcom,oryon";
+ reg = <0x0 0x10100>;
+ enable-method = "psci";
+ next-level-cache = <&L2_1>;
+ power-domains = <&CPU_PD5>;
+ power-domain-names = "psci";
+ cpu-idle-states = <&CLUSTER_C4>;
+ };
+
+ CPU6: cpu@10200 {
+ device_type = "cpu";
+ compatible = "qcom,oryon";
+ reg = <0x0 0x10200>;
+ enable-method = "psci";
+ next-level-cache = <&L2_1>;
+ power-domains = <&CPU_PD6>;
+ power-domain-names = "psci";
+ cpu-idle-states = <&CLUSTER_C4>;
+ };
+
+ CPU7: cpu@10300 {
+ device_type = "cpu";
+ compatible = "qcom,oryon";
+ reg = <0x0 0x10300>;
+ enable-method = "psci";
+ next-level-cache = <&L2_1>;
+ power-domains = <&CPU_PD7>;
+ power-domain-names = "psci";
+ cpu-idle-states = <&CLUSTER_C4>;
+ };
+
+ CPU8: cpu@20000 {
+ device_type = "cpu";
+ compatible = "qcom,oryon";
+ reg = <0x0 0x20000>;
+ enable-method = "psci";
+ next-level-cache = <&L2_2>;
+ power-domains = <&CPU_PD8>;
+ power-domain-names = "psci";
+ cpu-idle-states = <&CLUSTER_C4>;
+
+ L2_2: l2-cache {
+ compatible = "cache";
+ cache-level = <2>;
+ cache-unified;
+ };
+ };
+
+ CPU9: cpu@20100 {
+ device_type = "cpu";
+ compatible = "qcom,oryon";
+ reg = <0x0 0x20100>;
+ enable-method = "psci";
+ next-level-cache = <&L2_2>;
+ power-domains = <&CPU_PD9>;
+ power-domain-names = "psci";
+ cpu-idle-states = <&CLUSTER_C4>;
+ };
+
+ CPU10: cpu@20200 {
+ device_type = "cpu";
+ compatible = "qcom,oryon";
+ reg = <0x0 0x20200>;
+ enable-method = "psci";
+ next-level-cache = <&L2_2>;
+ power-domains = <&CPU_PD10>;
+ power-domain-names = "psci";
+ cpu-idle-states = <&CLUSTER_C4>;
+ };
+
+ CPU11: cpu@20300 {
+ device_type = "cpu";
+ compatible = "qcom,oryon";
+ reg = <0x0 0x20300>;
+ enable-method = "psci";
+ next-level-cache = <&L2_2>;
+ power-domains = <&CPU_PD11>;
+ power-domain-names = "psci";
+ cpu-idle-states = <&CLUSTER_C4>;
+ };
+
+ cpu-map {
+ cluster0 {
+ core0 {
+ cpu = <&CPU0>;
+ };
+
+ core1 {
+ cpu = <&CPU1>;
+ };
+
+ core2 {
+ cpu = <&CPU2>;
+ };
+
+ core3 {
+ cpu = <&CPU3>;
+ };
+ };
+
+ cluster1 {
+ core0 {
+ cpu = <&CPU4>;
+ };
+
+ core1 {
+ cpu = <&CPU5>;
+ };
+
+ core2 {
+ cpu = <&CPU6>;
+ };
+
+ core3 {
+ cpu = <&CPU7>;
+ };
+ };
+
+ cluster2 {
+ core0 {
+ cpu = <&CPU8>;
+ };
+
+ core1 {
+ cpu = <&CPU9>;
+ };
+
+ core2 {
+ cpu = <&CPU10>;
+ };
+
+ core3 {
+ cpu = <&CPU11>;
+ };
+ };
+ };
+
+ idle-states {
+ entry-method = "psci";
+
+ CLUSTER_C4: cpu-sleep-0 {
+ compatible = "arm,idle-state";
+ idle-state-name = "ret";
+ arm,psci-suspend-param = <0x00000004>;
+ entry-latency-us = <180>;
+ exit-latency-us = <320>;
+ min-residency-us = <1000>;
+ };
+ };
+
+ domain-idle-states {
+ CLUSTER_CL4: cluster-sleep-0 {
+ compatible = "arm,idle-state";
+ idle-state-name = "l2-ret";
+ arm,psci-suspend-param = <0x01000044>;
+ entry-latency-us = <350>;
+ exit-latency-us = <500>;
+ min-residency-us = <2500>;
+ };
+
+ CLUSTER_CL5: cluster-sleep-1 {
+ compatible = "arm,idle-state";
+ idle-state-name = "ret-pll-off";
+ arm,psci-suspend-param = <0x01000054>;
+ entry-latency-us = <2200>;
+ exit-latency-us = <2500>;
+ min-residency-us = <7000>;
+ };
+ };
+ };
+
+ firmware {
+ scm: scm {
+ compatible = "qcom,scm-x1e80100", "qcom,scm";
+ interconnects = <&aggre2_noc MASTER_CRYPTO QCOM_ICC_TAG_ALWAYS
+ &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
+ };
+ };
+
+ clk_virt: interconnect-0 {
+ compatible = "qcom,x1e80100-clk-virt";
+ #interconnect-cells = <2>;
+ qcom,bcm-voters = <&apps_bcm_voter>;
+ };
+
+ mc_virt: interconnect-1 {
+ compatible = "qcom,x1e80100-mc-virt";
+ #interconnect-cells = <2>;
+ qcom,bcm-voters = <&apps_bcm_voter>;
+ };
+
+ memory@80000000 {
+ device_type = "memory";
+ /* We expect the bootloader to fill in the size */
+ reg = <0 0x80000000 0 0>;
+ };
+
+ pmu {
+ compatible = "arm,armv8-pmuv3";
+ interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_LOW>;
+ };
+
+ psci {
+ compatible = "arm,psci-1.0";
+ method = "smc";
+
+ CPU_PD0: power-domain-cpu0 {
+ #power-domain-cells = <0>;
+ power-domains = <&CLUSTER_PD0>;
+ };
+
+ CPU_PD1: power-domain-cpu1 {
+ #power-domain-cells = <0>;
+ power-domains = <&CLUSTER_PD0>;
+ };
+
+ CPU_PD2: power-domain-cpu2 {
+ #power-domain-cells = <0>;
+ power-domains = <&CLUSTER_PD0>;
+ };
+
+ CPU_PD3: power-domain-cpu3 {
+ #power-domain-cells = <0>;
+ power-domains = <&CLUSTER_PD0>;
+ };
+
+ CPU_PD4: power-domain-cpu4 {
+ #power-domain-cells = <0>;
+ power-domains = <&CLUSTER_PD1>;
+ };
+
+ CPU_PD5: power-domain-cpu5 {
+ #power-domain-cells = <0>;
+ power-domains = <&CLUSTER_PD1>;
+ };
+
+ CPU_PD6: power-domain-cpu6 {
+ #power-domain-cells = <0>;
+ power-domains = <&CLUSTER_PD1>;
+ };
+
+ CPU_PD7: power-domain-cpu7 {
+ #power-domain-cells = <0>;
+ power-domains = <&CLUSTER_PD1>;
+ };
+
+ CPU_PD8: power-domain-cpu8 {
+ #power-domain-cells = <0>;
+ power-domains = <&CLUSTER_PD2>;
+ };
+
+ CPU_PD9: power-domain-cpu9 {
+ #power-domain-cells = <0>;
+ power-domains = <&CLUSTER_PD2>;
+ };
+
+ CPU_PD10: power-domain-cpu10 {
+ #power-domain-cells = <0>;
+ power-domains = <&CLUSTER_PD2>;
+ };
+
+ CPU_PD11: power-domain-cpu11 {
+ #power-domain-cells = <0>;
+ power-domains = <&CLUSTER_PD2>;
+ };
+
+ CLUSTER_PD0: power-domain-cpu-cluster0 {
+ #power-domain-cells = <0>;
+ domain-idle-states = <&CLUSTER_CL4>, <&CLUSTER_CL5>;
+ };
+
+ CLUSTER_PD1: power-domain-cpu-cluster1 {
+ #power-domain-cells = <0>;
+ domain-idle-states = <&CLUSTER_CL4>, <&CLUSTER_CL5>;
+ };
+
+ CLUSTER_PD2: power-domain-cpu-cluster2 {
+ #power-domain-cells = <0>;
+ domain-idle-states = <&CLUSTER_CL4>, <&CLUSTER_CL5>;
+ };
+ };
+
+ reserved-memory {
+ #address-cells = <2>;
+ #size-cells = <2>;
+ ranges;
+
+ gunyah_hyp_mem: gunyah-hyp@80000000 {
+ reg = <0x0 0x80000000 0x0 0x800000>;
+ no-map;
+ };
+
+ hyp_elf_package_mem: hyp-elf-package@80800000 {
+ reg = <0x0 0x80800000 0x0 0x200000>;
+ no-map;
+ };
+
+ ncc_mem: ncc@80a00000 {
+ reg = <0x0 0x80a00000 0x0 0x400000>;
+ no-map;
+ };
+
+ cpucp_log_mem: cpucp-log@80e00000 {
+ reg = <0x0 0x80e00000 0x0 0x40000>;
+ no-map;
+ };
+
+ cpucp_mem: cpucp@80e40000 {
+ reg = <0x0 0x80e40000 0x0 0x540000>;
+ no-map;
+ };
+
+ reserved-region@81380000 {
+ reg = <0x0 0x81380000 0x0 0x80000>;
+ no-map;
+ };
+
+ tags_mem: tags-region@81400000 {
+ reg = <0x0 0x81400000 0x0 0x1a0000>;
+ no-map;
+ };
+
+ xbl_dtlog_mem: xbl-dtlog@81a00000 {
+ reg = <0x0 0x81a00000 0x0 0x40000>;
+ no-map;
+ };
+
+ xbl_ramdump_mem: xbl-ramdump@81a40000 {
+ reg = <0x0 0x81a40000 0x0 0x1c0000>;
+ no-map;
+ };
+
+ aop_image_mem: aop-image@81c00000 {
+ reg = <0x0 0x81c00000 0x0 0x60000>;
+ no-map;
+ };
+
+ aop_cmd_db_mem: aop-cmd-db@81c60000 {
+ compatible = "qcom,cmd-db";
+ reg = <0x0 0x81c60000 0x0 0x20000>;
+ no-map;
+ };
+
+ aop_config_mem: aop-config@81c80000 {
+ reg = <0x0 0x81c80000 0x0 0x20000>;
+ no-map;
+ };
+
+ tme_crash_dump_mem: tme-crash-dump@81ca0000 {
+ reg = <0x0 0x81ca0000 0x0 0x40000>;
+ no-map;
+ };
+
+ tme_log_mem: tme-log@81ce0000 {
+ reg = <0x0 0x81ce0000 0x0 0x4000>;
+ no-map;
+ };
+
+ uefi_log_mem: uefi-log@81ce4000 {
+ reg = <0x0 0x81ce4000 0x0 0x10000>;
+ no-map;
+ };
+
+ secdata_apss_mem: secdata-apss@81cff000 {
+ reg = <0x0 0x81cff000 0x0 0x1000>;
+ no-map;
+ };
+
+ pdp_ns_shared_mem: pdp-ns-shared@81e00000 {
+ reg = <0x0 0x81e00000 0x0 0x100000>;
+ no-map;
+ };
+
+ gpu_prr_mem: gpu-prr@81f00000 {
+ reg = <0x0 0x81f00000 0x0 0x10000>;
+ no-map;
+ };
+
+ tpm_control_mem: tpm-control@81f10000 {
+ reg = <0x0 0x81f10000 0x0 0x10000>;
+ no-map;
+ };
+
+ usb_ucsi_shared_mem: usb-ucsi-shared@81f20000 {
+ reg = <0x0 0x81f20000 0x0 0x10000>;
+ no-map;
+ };
+
+ pld_pep_mem: pld-pep@81f30000 {
+ reg = <0x0 0x81f30000 0x0 0x6000>;
+ no-map;
+ };
+
+ pld_gmu_mem: pld-gmu@81f36000 {
+ reg = <0x0 0x81f36000 0x0 0x1000>;
+ no-map;
+ };
+
+ pld_pdp_mem: pld-pdp@81f37000 {
+ reg = <0x0 0x81f37000 0x0 0x1000>;
+ no-map;
+ };
+
+ tz_stat_mem: tz-stat@82700000 {
+ reg = <0x0 0x82700000 0x0 0x100000>;
+ no-map;
+ };
+
+ xbl_tmp_buffer_mem: xbl-tmp-buffer@82800000 {
+ reg = <0x0 0x82800000 0x0 0xc00000>;
+ no-map;
+ };
+
+ adsp_rpc_remote_heap_mem: adsp-rpc-remote-heap@84b00000 {
+ reg = <0x0 0x84b00000 0x0 0x800000>;
+ no-map;
+ };
+
+ spu_secure_shared_memory_mem: spu-secure-shared-memory@85300000 {
+ reg = <0x0 0x85300000 0x0 0x80000>;
+ no-map;
+ };
+
+ adsp_boot_dtb_mem: adsp-boot-dtb@866c0000 {
+ reg = <0x0 0x866c0000 0x0 0x40000>;
+ no-map;
+ };
+
+ spss_region_mem: spss-region@86700000 {
+ reg = <0x0 0x86700000 0x0 0x400000>;
+ no-map;
+ };
+
+ adsp_boot_mem: adsp-boot@86b00000 {
+ reg = <0x0 0x86b00000 0x0 0xc00000>;
+ no-map;
+ };
+
+ video_mem: video@87700000 {
+ reg = <0x0 0x87700000 0x0 0x700000>;
+ no-map;
+ };
+
+ adspslpi_mem: adspslpi@87e00000 {
+ reg = <0x0 0x87e00000 0x0 0x3a00000>;
+ no-map;
+ };
+
+ q6_adsp_dtb_mem: q6-adsp-dtb@8b800000 {
+ reg = <0x0 0x8b800000 0x0 0x80000>;
+ no-map;
+ };
+
+ cdsp_mem: cdsp@8b900000 {
+ reg = <0x0 0x8b900000 0x0 0x2000000>;
+ no-map;
+ };
+
+ q6_cdsp_dtb_mem: q6-cdsp-dtb@8d900000 {
+ reg = <0x0 0x8d900000 0x0 0x80000>;
+ no-map;
+ };
+
+ gpu_microcode_mem: gpu-microcode@8d9fe000 {
+ reg = <0x0 0x8d9fe000 0x0 0x2000>;
+ no-map;
+ };
+
+ cvp_mem: cvp@8da00000 {
+ reg = <0x0 0x8da00000 0x0 0x700000>;
+ no-map;
+ };
+
+ camera_mem: camera@8e100000 {
+ reg = <0x0 0x8e100000 0x0 0x800000>;
+ no-map;
+ };
+
+ av1_encoder_mem: av1-encoder@8e900000 {
+ reg = <0x0 0x8e900000 0x0 0x700000>;
+ no-map;
+ };
+
+ reserved-region@8f000000 {
+ reg = <0x0 0x8f000000 0x0 0xa00000>;
+ no-map;
+ };
+
+ wpss_mem: wpss@8fa00000 {
+ reg = <0x0 0x8fa00000 0x0 0x1900000>;
+ no-map;
+ };
+
+ q6_wpss_dtb_mem: q6-wpss-dtb@91300000 {
+ reg = <0x0 0x91300000 0x0 0x80000>;
+ no-map;
+ };
+
+ xbl_sc_mem: xbl-sc@d8000000 {
+ reg = <0x0 0xd8000000 0x0 0x40000>;
+ no-map;
+ };
+
+ reserved-region@d8040000 {
+ reg = <0x0 0xd8040000 0x0 0xa0000>;
+ no-map;
+ };
+
+ qtee_mem: qtee@d80e0000 {
+ reg = <0x0 0xd80e0000 0x0 0x520000>;
+ no-map;
+ };
+
+ ta_mem: ta@d8600000 {
+ reg = <0x0 0xd8600000 0x0 0x8a00000>;
+ no-map;
+ };
+
+ tags_mem1: tags@e1000000 {
+ reg = <0x0 0xe1000000 0x0 0x26a0000>;
+ no-map;
+ };
+
+ llcc_lpi_mem: llcc-lpi@ff800000 {
+ reg = <0x0 0xff800000 0x0 0x600000>;
+ no-map;
+ };
+
+ smem_mem: smem@ffe00000 {
+ compatible = "qcom,smem";
+ reg = <0x0 0xffe00000 0x0 0x200000>;
+ hwlocks = <&tcsr_mutex 3>;
+ no-map;
+ };
+ };
+
+ soc: soc@0 {
+ compatible = "simple-bus";
+
+ #address-cells = <2>;
+ #size-cells = <2>;
+ dma-ranges = <0 0 0 0 0x10 0>;
+ ranges = <0 0 0 0 0x10 0>;
+
+ gcc: clock-controller@100000 {
+ compatible = "qcom,x1e80100-gcc";
+ reg = <0 0x00100000 0 0x200000>;
+
+ clocks = <&bi_tcxo_div2>,
+ <&sleep_clk>,
+ <0>,
+ <0>,
+ <0>,
+ <0>,
+ <0>,
+ <0>,
+ <0>,
+ <0>;
+
+ power-domains = <&rpmhpd RPMHPD_CX>;
+ #clock-cells = <1>;
+ #reset-cells = <1>;
+ #power-domain-cells = <1>;
+ };
+
+ gpi_dma2: dma-controller@800000 {
+ compatible = "qcom,x1e80100-gpi-dma", "qcom,sm6350-gpi-dma";
+ reg = <0 0x00800000 0 0x60000>;
+
+ interrupts = <GIC_SPI 788 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 789 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 790 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 791 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 792 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 793 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 794 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 795 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 796 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 797 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 798 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 799 IRQ_TYPE_LEVEL_HIGH>;
+
+ dma-channels = <12>;
+ dma-channel-mask = <0x3e>;
+ #dma-cells = <3>;
+
+ iommus = <&apps_smmu 0x436 0x0>;
+
+ status = "disabled";
+ };
+
+ qupv3_2: geniqup@8c0000 {
+ compatible = "qcom,geni-se-qup";
+ reg = <0 0x008c0000 0 0x2000>;
+
+ clocks = <&gcc GCC_QUPV3_WRAP_2_M_AHB_CLK>,
+ <&gcc GCC_QUPV3_WRAP_2_S_AHB_CLK>;
+ clock-names = "m-ahb",
+ "s-ahb";
+
+ iommus = <&apps_smmu 0x423 0x0>;
+
+ #address-cells = <2>;
+ #size-cells = <2>;
+ ranges;
+
+ status = "disabled";
+
+ i2c16: i2c@880000 {
+ compatible = "qcom,geni-i2c";
+ reg = <0 0x00880000 0 0x4000>;
+
+ interrupts = <GIC_SPI 808 IRQ_TYPE_LEVEL_HIGH>;
+
+ clocks = <&gcc GCC_QUPV3_WRAP2_S0_CLK>;
+ clock-names = "se";
+
+ interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS
+ &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>,
+ <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
+ &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>,
+ <&aggre2_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS
+ &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
+ interconnect-names = "qup-core",
+ "qup-config",
+ "qup-memory";
+
+ dmas = <&gpi_dma2 0 0 QCOM_GPI_I2C>,
+ <&gpi_dma2 1 0 QCOM_GPI_I2C>;
+ dma-names = "tx",
+ "rx";
+
+ pinctrl-0 = <&qup_i2c16_data_clk>;
+ pinctrl-names = "default";
+
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ status = "disabled";
+ };
+
+ spi16: spi@880000 {
+ compatible = "qcom,geni-spi";
+ reg = <0 0x00880000 0 0x4000>;
+
+ interrupts = <GIC_SPI 808 IRQ_TYPE_LEVEL_HIGH>;
+
+ clocks = <&gcc GCC_QUPV3_WRAP2_S0_CLK>;
+ clock-names = "se";
+
+ interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS
+ &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>,
+ <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
+ &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>,
+ <&aggre2_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS
+ &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
+ interconnect-names = "qup-core",
+ "qup-config",
+ "qup-memory";
+
+ dmas = <&gpi_dma2 0 0 QCOM_GPI_SPI>,
+ <&gpi_dma2 1 0 QCOM_GPI_SPI>;
+ dma-names = "tx",
+ "rx";
+
+ pinctrl-0 = <&qup_spi16_data_clk>, <&qup_spi16_cs>;
+ pinctrl-names = "default";
+
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ status = "disabled";
+ };
+
+ i2c17: i2c@884000 {
+ compatible = "qcom,geni-i2c";
+ reg = <0 0x00884000 0 0x4000>;
+
+ interrupts = <GIC_SPI 809 IRQ_TYPE_LEVEL_HIGH>;
+
+ clocks = <&gcc GCC_QUPV3_WRAP2_S1_CLK>;
+ clock-names = "se";
+
+ interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS
+ &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>,
+ <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
+ &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>,
+ <&aggre2_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS
+ &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
+ interconnect-names = "qup-core",
+ "qup-config",
+ "qup-memory";
+
+ dmas = <&gpi_dma2 0 1 QCOM_GPI_I2C>,
+ <&gpi_dma2 1 1 QCOM_GPI_I2C>;
+ dma-names = "tx",
+ "rx";
+
+ pinctrl-0 = <&qup_i2c17_data_clk>;
+ pinctrl-names = "default";
+
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ status = "disabled";
+ };
+
+ spi17: spi@884000 {
+ compatible = "qcom,geni-spi";
+ reg = <0 0x00884000 0 0x4000>;
+
+ interrupts = <GIC_SPI 809 IRQ_TYPE_LEVEL_HIGH>;
+
+ clocks = <&gcc GCC_QUPV3_WRAP2_S1_CLK>;
+ clock-names = "se";
+
+ interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS
+ &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>,
+ <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
+ &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>,
+ <&aggre2_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS
+ &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
+ interconnect-names = "qup-core",
+ "qup-config",
+ "qup-memory";
+
+ dmas = <&gpi_dma2 0 1 QCOM_GPI_SPI>,
+ <&gpi_dma2 1 1 QCOM_GPI_SPI>;
+ dma-names = "tx",
+ "rx";
+
+ pinctrl-0 = <&qup_spi17_data_clk>, <&qup_spi17_cs>;
+ pinctrl-names = "default";
+
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ status = "disabled";
+ };
+
+ i2c18: i2c@888000 {
+ compatible = "qcom,geni-i2c";
+ reg = <0 0x00888000 0 0x4000>;
+
+ interrupts = <GIC_SPI 810 IRQ_TYPE_LEVEL_HIGH>;
+
+ clocks = <&gcc GCC_QUPV3_WRAP2_S2_CLK>;
+ clock-names = "se";
+
+ interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS
+ &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>,
+ <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
+ &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>,
+ <&aggre2_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS
+ &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
+ interconnect-names = "qup-core",
+ "qup-config",
+ "qup-memory";
+
+ dmas = <&gpi_dma2 0 2 QCOM_GPI_I2C>,
+ <&gpi_dma2 1 2 QCOM_GPI_I2C>;
+ dma-names = "tx",
+ "rx";
+
+ pinctrl-0 = <&qup_i2c18_data_clk>;
+ pinctrl-names = "default";
+
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ status = "disabled";
+ };
+
+ spi18: spi@888000 {
+ compatible = "qcom,geni-spi";
+ reg = <0 0x00888000 0 0x4000>;
+
+ interrupts = <GIC_SPI 810 IRQ_TYPE_LEVEL_HIGH>;
+
+ clocks = <&gcc GCC_QUPV3_WRAP2_S2_CLK>;
+ clock-names = "se";
+
+ interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS
+ &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>,
+ <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
+ &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>,
+ <&aggre2_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS
+ &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
+ interconnect-names = "qup-core",
+ "qup-config",
+ "qup-memory";
+
+ dmas = <&gpi_dma2 0 2 QCOM_GPI_SPI>,
+ <&gpi_dma2 1 2 QCOM_GPI_SPI>;
+ dma-names = "tx",
+ "rx";
+
+ pinctrl-0 = <&qup_spi18_data_clk>, <&qup_spi18_cs>;
+ pinctrl-names = "default";
+
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ status = "disabled";
+ };
+
+ i2c19: i2c@88c000 {
+ compatible = "qcom,geni-i2c";
+ reg = <0 0x0088c000 0 0x4000>;
+
+ interrupts = <GIC_SPI 811 IRQ_TYPE_LEVEL_HIGH>;
+
+ clocks = <&gcc GCC_QUPV3_WRAP2_S3_CLK>;
+ clock-names = "se";
+
+ interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS
+ &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>,
+ <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
+ &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>,
+ <&aggre2_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS
+ &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
+ interconnect-names = "qup-core",
+ "qup-config",
+ "qup-memory";
+
+ dmas = <&gpi_dma2 0 3 QCOM_GPI_I2C>,
+ <&gpi_dma2 1 3 QCOM_GPI_I2C>;
+ dma-names = "tx",
+ "rx";
+
+ pinctrl-0 = <&qup_i2c19_data_clk>;
+ pinctrl-names = "default";
+
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ status = "disabled";
+ };
+
+ spi19: spi@88c000 {
+ compatible = "qcom,geni-spi";
+ reg = <0 0x0088c000 0 0x4000>;
+
+ interrupts = <GIC_SPI 811 IRQ_TYPE_LEVEL_HIGH>;
+
+ clocks = <&gcc GCC_QUPV3_WRAP2_S3_CLK>;
+ clock-names = "se";
+
+ interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS
+ &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>,
+ <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
+ &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>,
+ <&aggre2_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS
+ &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
+ interconnect-names = "qup-core",
+ "qup-config",
+ "qup-memory";
+
+ dmas = <&gpi_dma2 0 3 QCOM_GPI_SPI>,
+ <&gpi_dma2 1 3 QCOM_GPI_SPI>;
+ dma-names = "tx",
+ "rx";
+
+ pinctrl-0 = <&qup_spi19_data_clk>, <&qup_spi19_cs>;
+ pinctrl-names = "default";
+
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ status = "disabled";
+ };
+
+ i2c20: i2c@890000 {
+ compatible = "qcom,geni-i2c";
+ reg = <0 0x00890000 0 0x4000>;
+
+ interrupts = <GIC_SPI 812 IRQ_TYPE_LEVEL_HIGH>;
+
+ clocks = <&gcc GCC_QUPV3_WRAP2_S4_CLK>;
+ clock-names = "se";
+
+ interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS
+ &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>,
+ <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
+ &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>,
+ <&aggre2_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS
+ &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
+ interconnect-names = "qup-core",
+ "qup-config",
+ "qup-memory";
+
+ dmas = <&gpi_dma2 0 4 QCOM_GPI_I2C>,
+ <&gpi_dma2 1 4 QCOM_GPI_I2C>;
+ dma-names = "tx",
+ "rx";
+
+ pinctrl-0 = <&qup_i2c20_data_clk>;
+ pinctrl-names = "default";
+
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ status = "disabled";
+ };
+
+ spi20: spi@890000 {
+ compatible = "qcom,geni-spi";
+ reg = <0 0x00890000 0 0x4000>;
+
+ interrupts = <GIC_SPI 812 IRQ_TYPE_LEVEL_HIGH>;
+
+ clocks = <&gcc GCC_QUPV3_WRAP2_S4_CLK>;
+ clock-names = "se";
+
+ interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS
+ &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>,
+ <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
+ &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>,
+ <&aggre2_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS
+ &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
+ interconnect-names = "qup-core",
+ "qup-config",
+ "qup-memory";
+
+ dmas = <&gpi_dma2 0 4 QCOM_GPI_SPI>,
+ <&gpi_dma2 1 4 QCOM_GPI_SPI>;
+ dma-names = "tx",
+ "rx";
+
+ pinctrl-0 = <&qup_spi20_data_clk>, <&qup_spi20_cs>;
+ pinctrl-names = "default";
+
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ status = "disabled";
+ };
+
+ i2c21: i2c@894000 {
+ compatible = "qcom,geni-i2c";
+ reg = <0 0x00894000 0 0x4000>;
+
+ interrupts = <GIC_SPI 813 IRQ_TYPE_LEVEL_HIGH>;
+
+ clocks = <&gcc GCC_QUPV3_WRAP2_S5_CLK>;
+ clock-names = "se";
+
+ interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS
+ &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>,
+ <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
+ &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>,
+ <&aggre2_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS
+ &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
+ interconnect-names = "qup-core",
+ "qup-config",
+ "qup-memory";
+
+ dmas = <&gpi_dma2 0 5 QCOM_GPI_I2C>,
+ <&gpi_dma2 1 5 QCOM_GPI_I2C>;
+ dma-names = "tx",
+ "rx";
+
+ pinctrl-0 = <&qup_i2c21_data_clk>;
+ pinctrl-names = "default";
+
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ status = "disabled";
+ };
+
+ spi21: spi@894000 {
+ compatible = "qcom,geni-spi";
+ reg = <0 0x00894000 0 0x4000>;
+
+ interrupts = <GIC_SPI 813 IRQ_TYPE_LEVEL_HIGH>;
+
+ clocks = <&gcc GCC_QUPV3_WRAP2_S5_CLK>;
+ clock-names = "se";
+
+ interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS
+ &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>,
+ <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
+ &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>,
+ <&aggre2_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS
+ &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
+ interconnect-names = "qup-core",
+ "qup-config",
+ "qup-memory";
+
+ dmas = <&gpi_dma2 0 5 QCOM_GPI_SPI>,
+ <&gpi_dma2 1 5 QCOM_GPI_SPI>;
+ dma-names = "tx",
+ "rx";
+
+ pinctrl-0 = <&qup_spi21_data_clk>, <&qup_spi21_cs>;
+ pinctrl-names = "default";
+
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ status = "disabled";
+ };
+
+ uart21: serial@894000 {
+ compatible = "qcom,geni-uart";
+ reg = <0 0x00894000 0 0x4000>;
+
+ interrupts = <GIC_SPI 813 IRQ_TYPE_LEVEL_HIGH>;
+
+ clocks = <&gcc GCC_QUPV3_WRAP2_S5_CLK>;
+ clock-names = "se";
+
+ interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS
+ &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>,
+ <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
+ &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>;
+ interconnect-names = "qup-core",
+ "qup-config";
+
+ pinctrl-0 = <&qup_uart21_default>;
+ pinctrl-names = "default";
+
+ status = "disabled";
+ };
+
+ i2c22: i2c@898000 {
+ compatible = "qcom,geni-i2c";
+ reg = <0 0x00898000 0 0x4000>;
+
+ interrupts = <GIC_SPI 461 IRQ_TYPE_LEVEL_HIGH>;
+
+ clocks = <&gcc GCC_QUPV3_WRAP2_S6_CLK>;
+ clock-names = "se";
+
+ interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS
+ &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>,
+ <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
+ &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>,
+ <&aggre2_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS
+ &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
+ interconnect-names = "qup-core",
+ "qup-config",
+ "qup-memory";
+
+ dmas = <&gpi_dma2 0 6 QCOM_GPI_I2C>,
+ <&gpi_dma2 1 6 QCOM_GPI_I2C>;
+ dma-names = "tx",
+ "rx";
+
+ pinctrl-0 = <&qup_i2c22_data_clk>;
+ pinctrl-names = "default";
+
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ status = "disabled";
+ };
+
+ spi22: spi@898000 {
+ compatible = "qcom,geni-spi";
+ reg = <0 0x00898000 0 0x4000>;
+
+ interrupts = <GIC_SPI 461 IRQ_TYPE_LEVEL_HIGH>;
+
+ clocks = <&gcc GCC_QUPV3_WRAP2_S6_CLK>;
+ clock-names = "se";
+
+ interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS
+ &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>,
+ <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
+ &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>,
+ <&aggre2_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS
+ &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
+ interconnect-names = "qup-core",
+ "qup-config",
+ "qup-memory";
+
+ dmas = <&gpi_dma2 0 6 QCOM_GPI_SPI>,
+ <&gpi_dma2 1 6 QCOM_GPI_SPI>;
+ dma-names = "tx",
+ "rx";
+
+ pinctrl-0 = <&qup_spi22_data_clk>, <&qup_spi22_cs>;
+ pinctrl-names = "default";
+
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ status = "disabled";
+ };
+
+ i2c23: i2c@89c000 {
+ compatible = "qcom,geni-i2c";
+ reg = <0 0x0089c000 0 0x4000>;
+
+ interrupts = <GIC_SPI 462 IRQ_TYPE_LEVEL_HIGH>;
+
+ clocks = <&gcc GCC_QUPV3_WRAP2_S7_CLK>;
+ clock-names = "se";
+
+ interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS
+ &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>,
+ <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
+ &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>,
+ <&aggre2_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS
+ &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
+ interconnect-names = "qup-core",
+ "qup-config",
+ "qup-memory";
+
+ dmas = <&gpi_dma2 0 7 QCOM_GPI_I2C>,
+ <&gpi_dma2 1 7 QCOM_GPI_I2C>;
+ dma-names = "tx",
+ "rx";
+
+ pinctrl-0 = <&qup_i2c23_data_clk>;
+ pinctrl-names = "default";
+
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ status = "disabled";
+ };
+
+ spi23: spi@89c000 {
+ compatible = "qcom,geni-spi";
+ reg = <0 0x0089c000 0 0x4000>;
+
+ interrupts = <GIC_SPI 462 IRQ_TYPE_LEVEL_HIGH>;
+
+ clocks = <&gcc GCC_QUPV3_WRAP2_S7_CLK>;
+ clock-names = "se";
+
+ interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS
+ &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>,
+ <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
+ &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>,
+ <&aggre2_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS
+ &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
+ interconnect-names = "qup-core",
+ "qup-config",
+ "qup-memory";
+
+ dmas = <&gpi_dma2 0 7 QCOM_GPI_SPI>,
+ <&gpi_dma2 1 7 QCOM_GPI_SPI>;
+ dma-names = "tx",
+ "rx";
+
+ pinctrl-0 = <&qup_spi23_data_clk>, <&qup_spi23_cs>;
+ pinctrl-names = "default";
+
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ status = "disabled";
+ };
+ };
+
+ gpi_dma1: dma-controller@a00000 {
+ compatible = "qcom,x1e80100-gpi-dma", "qcom,sm6350-gpi-dma";
+ reg = <0 0x00a00000 0 0x60000>;
+
+ interrupts = <GIC_SPI 776 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 777 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 778 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 779 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 780 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 781 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 782 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 783 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 784 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 785 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 786 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 787 IRQ_TYPE_LEVEL_HIGH>;
+
+ dma-channels = <12>;
+ dma-channel-mask = <0x3e>;
+ #dma-cells = <3>;
+
+ iommus = <&apps_smmu 0x136 0x0>;
+
+ status = "disabled";
+ };
+
+ qupv3_1: geniqup@ac0000 {
+ compatible = "qcom,geni-se-qup";
+ reg = <0 0x00ac0000 0 0x2000>;
+
+ clocks = <&gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>,
+ <&gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>;
+ clock-names = "m-ahb",
+ "s-ahb";
+
+ iommus = <&apps_smmu 0x123 0x0>;
+
+ #address-cells = <2>;
+ #size-cells = <2>;
+ ranges;
+
+ status = "disabled";
+
+ i2c8: i2c@a80000 {
+ compatible = "qcom,geni-i2c";
+ reg = <0 0x00a80000 0 0x4000>;
+
+ interrupts = <GIC_SPI 800 IRQ_TYPE_LEVEL_HIGH>;
+
+ clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>;
+ clock-names = "se";
+
+ interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS
+ &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>,
+ <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
+ &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>,
+ <&aggre1_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS
+ &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
+ interconnect-names = "qup-core",
+ "qup-config",
+ "qup-memory";
+
+ dmas = <&gpi_dma1 0 0 QCOM_GPI_I2C>,
+ <&gpi_dma1 1 0 QCOM_GPI_I2C>;
+ dma-names = "tx",
+ "rx";
+
+ pinctrl-0 = <&qup_i2c8_data_clk>;
+ pinctrl-names = "default";
+
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ status = "disabled";
+ };
+
+ spi8: spi@a80000 {
+ compatible = "qcom,geni-spi";
+ reg = <0 0x00a80000 0 0x4000>;
+
+ interrupts = <GIC_SPI 800 IRQ_TYPE_LEVEL_HIGH>;
+
+ clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>;
+ clock-names = "se";
+
+ interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS
+ &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>,
+ <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
+ &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>,
+ <&aggre1_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS
+ &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
+ interconnect-names = "qup-core",
+ "qup-config",
+ "qup-memory";
+
+ dmas = <&gpi_dma1 0 0 QCOM_GPI_SPI>,
+ <&gpi_dma1 1 0 QCOM_GPI_SPI>;
+ dma-names = "tx",
+ "rx";
+
+ pinctrl-0 = <&qup_spi8_data_clk>, <&qup_spi8_cs>;
+ pinctrl-names = "default";
+
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ status = "disabled";
+ };
+
+ i2c9: i2c@a84000 {
+ compatible = "qcom,geni-i2c";
+ reg = <0 0x00a84000 0 0x4000>;
+
+ interrupts = <GIC_SPI 801 IRQ_TYPE_LEVEL_HIGH>;
+
+ clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>;
+ clock-names = "se";
+
+ interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS
+ &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>,
+ <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
+ &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>,
+ <&aggre1_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS
+ &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
+ interconnect-names = "qup-core",
+ "qup-config",
+ "qup-memory";
+
+ dmas = <&gpi_dma1 0 1 QCOM_GPI_I2C>,
+ <&gpi_dma1 1 1 QCOM_GPI_I2C>;
+ dma-names = "tx",
+ "rx";
+
+ pinctrl-0 = <&qup_i2c9_data_clk>;
+ pinctrl-names = "default";
+
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ status = "disabled";
+ };
+
+ spi9: spi@a84000 {
+ compatible = "qcom,geni-spi";
+ reg = <0 0x00a84000 0 0x4000>;
+
+ interrupts = <GIC_SPI 801 IRQ_TYPE_LEVEL_HIGH>;
+
+ clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>;
+ clock-names = "se";
+
+ interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS
+ &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>,
+ <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
+ &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>,
+ <&aggre1_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS
+ &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
+ interconnect-names = "qup-core",
+ "qup-config",
+ "qup-memory";
+
+ dmas = <&gpi_dma1 0 1 QCOM_GPI_SPI>,
+ <&gpi_dma1 1 1 QCOM_GPI_SPI>;
+ dma-names = "tx",
+ "rx";
+
+ pinctrl-0 = <&qup_spi9_data_clk>, <&qup_spi9_cs>;
+ pinctrl-names = "default";
+
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ status = "disabled";
+ };
+
+ i2c10: i2c@a88000 {
+ compatible = "qcom,geni-i2c";
+ reg = <0 0x00a88000 0 0x4000>;
+
+ interrupts = <GIC_SPI 802 IRQ_TYPE_LEVEL_HIGH>;
+
+ clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>;
+ clock-names = "se";
+
+ interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS
+ &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>,
+ <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
+ &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>,
+ <&aggre1_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS
+ &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
+ interconnect-names = "qup-core",
+ "qup-config",
+ "qup-memory";
+
+ dmas = <&gpi_dma1 0 2 QCOM_GPI_I2C>,
+ <&gpi_dma1 1 2 QCOM_GPI_I2C>;
+ dma-names = "tx",
+ "rx";
+
+ pinctrl-0 = <&qup_i2c10_data_clk>;
+ pinctrl-names = "default";
+
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ status = "disabled";
+ };
+
+ spi10: spi@a88000 {
+ compatible = "qcom,geni-spi";
+ reg = <0 0x00a88000 0 0x4000>;
+
+ interrupts = <GIC_SPI 802 IRQ_TYPE_LEVEL_HIGH>;
+
+ clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>;
+ clock-names = "se";
+
+ interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS
+ &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>,
+ <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
+ &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>,
+ <&aggre1_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS
+ &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
+ interconnect-names = "qup-core",
+ "qup-config",
+ "qup-memory";
+
+ dmas = <&gpi_dma1 0 2 QCOM_GPI_SPI>,
+ <&gpi_dma1 1 2 QCOM_GPI_SPI>;
+ dma-names = "tx",
+ "rx";
+
+ pinctrl-0 = <&qup_spi10_data_clk>, <&qup_spi10_cs>;
+ pinctrl-names = "default";
+
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ status = "disabled";
+ };
+
+ i2c11: i2c@a8c000 {
+ compatible = "qcom,geni-i2c";
+ reg = <0 0x00a8c000 0 0x4000>;
+
+ interrupts = <GIC_SPI 803 IRQ_TYPE_LEVEL_HIGH>;
+
+ clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>;
+ clock-names = "se";
+
+ interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS
+ &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>,
+ <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
+ &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>,
+ <&aggre1_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS
+ &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
+ interconnect-names = "qup-core",
+ "qup-config",
+ "qup-memory";
+
+ dmas = <&gpi_dma1 0 3 QCOM_GPI_I2C>,
+ <&gpi_dma1 1 3 QCOM_GPI_I2C>;
+ dma-names = "tx",
+ "rx";
+
+ pinctrl-0 = <&qup_i2c11_data_clk>;
+ pinctrl-names = "default";
+
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ status = "disabled";
+ };
+
+ spi11: spi@a8c000 {
+ compatible = "qcom,geni-spi";
+ reg = <0 0x00a8c000 0 0x4000>;
+
+ interrupts = <GIC_SPI 803 IRQ_TYPE_LEVEL_HIGH>;
+
+ clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>;
+ clock-names = "se";
+
+ interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS
+ &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>,
+ <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
+ &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>,
+ <&aggre1_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS
+ &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
+ interconnect-names = "qup-core",
+ "qup-config",
+ "qup-memory";
+
+ dmas = <&gpi_dma1 0 3 QCOM_GPI_SPI>,
+ <&gpi_dma1 1 3 QCOM_GPI_SPI>;
+ dma-names = "tx",
+ "rx";
+
+ pinctrl-0 = <&qup_spi11_data_clk>, <&qup_spi11_cs>;
+ pinctrl-names = "default";
+
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ status = "disabled";
+ };
+
+ i2c12: i2c@a90000 {
+ compatible = "qcom,geni-i2c";
+ reg = <0 0x00a90000 0 0x4000>;
+
+ interrupts = <GIC_SPI 804 IRQ_TYPE_LEVEL_HIGH>;
+
+ clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>;
+ clock-names = "se";
+
+ interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS
+ &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>,
+ <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
+ &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>,
+ <&aggre1_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS
+ &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
+ interconnect-names = "qup-core",
+ "qup-config",
+ "qup-memory";
+
+ dmas = <&gpi_dma1 0 4 QCOM_GPI_I2C>,
+ <&gpi_dma1 1 4 QCOM_GPI_I2C>;
+ dma-names = "tx",
+ "rx";
+
+ pinctrl-0 = <&qup_i2c12_data_clk>;
+ pinctrl-names = "default";
+
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ status = "disabled";
+ };
+
+ spi12: spi@a90000 {
+ compatible = "qcom,geni-spi";
+ reg = <0 0x00a90000 0 0x4000>;
+
+ interrupts = <GIC_SPI 804 IRQ_TYPE_LEVEL_HIGH>;
+
+ clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>;
+ clock-names = "se";
+
+ interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS
+ &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>,
+ <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
+ &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>,
+ <&aggre1_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS
+ &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
+ interconnect-names = "qup-core",
+ "qup-config",
+ "qup-memory";
+
+ dmas = <&gpi_dma1 0 4 QCOM_GPI_SPI>,
+ <&gpi_dma1 1 4 QCOM_GPI_SPI>;
+ dma-names = "tx",
+ "rx";
+
+ pinctrl-0 = <&qup_spi12_data_clk>, <&qup_spi12_cs>;
+ pinctrl-names = "default";
+
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ status = "disabled";
+ };
+
+ i2c13: i2c@a94000 {
+ compatible = "qcom,geni-i2c";
+ reg = <0 0x00a94000 0 0x4000>;
+
+ interrupts = <GIC_SPI 805 IRQ_TYPE_LEVEL_HIGH>;
+
+ clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>;
+ clock-names = "se";
+
+ interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS
+ &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>,
+ <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
+ &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>,
+ <&aggre1_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS
+ &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
+ interconnect-names = "qup-core",
+ "qup-config",
+ "qup-memory";
+
+ dmas = <&gpi_dma1 0 5 QCOM_GPI_I2C>,
+ <&gpi_dma1 1 5 QCOM_GPI_I2C>;
+ dma-names = "tx",
+ "rx";
+
+ pinctrl-0 = <&qup_i2c13_data_clk>;
+ pinctrl-names = "default";
+
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ status = "disabled";
+ };
+
+ spi13: spi@a94000 {
+ compatible = "qcom,geni-spi";
+ reg = <0 0x00a94000 0 0x4000>;
+
+ interrupts = <GIC_SPI 805 IRQ_TYPE_LEVEL_HIGH>;
+
+ clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>;
+ clock-names = "se";
+
+ interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS
+ &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>,
+ <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
+ &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>,
+ <&aggre1_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS
+ &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
+ interconnect-names = "qup-core",
+ "qup-config",
+ "qup-memory";
+
+ dmas = <&gpi_dma1 0 5 QCOM_GPI_SPI>,
+ <&gpi_dma1 1 5 QCOM_GPI_SPI>;
+ dma-names = "tx",
+ "rx";
+
+ pinctrl-0 = <&qup_spi13_data_clk>, <&qup_spi13_cs>;
+ pinctrl-names = "default";
+
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ status = "disabled";
+ };
+
+ i2c14: i2c@a98000 {
+ compatible = "qcom,geni-i2c";
+ reg = <0 0x00a98000 0 0x4000>;
+
+ interrupts = <GIC_SPI 806 IRQ_TYPE_LEVEL_HIGH>;
+
+ clocks = <&gcc GCC_QUPV3_WRAP1_S6_CLK>;
+ clock-names = "se";
+
+ interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS
+ &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>,
+ <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
+ &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>,
+ <&aggre1_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS
+ &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
+ interconnect-names = "qup-core",
+ "qup-config",
+ "qup-memory";
+
+ dmas = <&gpi_dma1 0 6 QCOM_GPI_I2C>,
+ <&gpi_dma1 1 6 QCOM_GPI_I2C>;
+ dma-names = "tx",
+ "rx";
+
+ pinctrl-0 = <&qup_i2c14_data_clk>;
+ pinctrl-names = "default";
+
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ status = "disabled";
+ };
+
+ spi14: spi@a98000 {
+ compatible = "qcom,geni-spi";
+ reg = <0 0x00a98000 0 0x4000>;
+
+ interrupts = <GIC_SPI 806 IRQ_TYPE_LEVEL_HIGH>;
+
+ clocks = <&gcc GCC_QUPV3_WRAP1_S6_CLK>;
+ clock-names = "se";
+
+ interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS
+ &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>,
+ <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
+ &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>,
+ <&aggre1_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS
+ &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
+ interconnect-names = "qup-core",
+ "qup-config",
+ "qup-memory";
+
+ dmas = <&gpi_dma1 0 6 QCOM_GPI_SPI>,
+ <&gpi_dma1 1 6 QCOM_GPI_SPI>;
+ dma-names = "tx",
+ "rx";
+
+ pinctrl-0 = <&qup_spi14_data_clk>, <&qup_spi14_cs>;
+ pinctrl-names = "default";
+
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ status = "disabled";
+ };
+
+ i2c15: i2c@a9c000 {
+ compatible = "qcom,geni-i2c";
+ reg = <0 0x00a9c000 0 0x4000>;
+
+ interrupts = <GIC_SPI 807 IRQ_TYPE_LEVEL_HIGH>;
+
+ clocks = <&gcc GCC_QUPV3_WRAP1_S7_CLK>;
+ clock-names = "se";
+
+ interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS
+ &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>,
+ <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
+ &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>,
+ <&aggre1_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS
+ &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
+ interconnect-names = "qup-core",
+ "qup-config",
+ "qup-memory";
+
+ dmas = <&gpi_dma1 0 7 QCOM_GPI_I2C>,
+ <&gpi_dma1 1 7 QCOM_GPI_I2C>;
+ dma-names = "tx",
+ "rx";
+
+ pinctrl-0 = <&qup_i2c15_data_clk>;
+ pinctrl-names = "default";
+
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ status = "disabled";
+ };
+
+ spi15: spi@a9c000 {
+ compatible = "qcom,geni-spi";
+ reg = <0 0x00a9c000 0 0x4000>;
+
+ interrupts = <GIC_SPI 807 IRQ_TYPE_LEVEL_HIGH>;
+
+ clocks = <&gcc GCC_QUPV3_WRAP1_S7_CLK>;
+ clock-names = "se";
+
+ interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS
+ &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>,
+ <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
+ &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>,
+ <&aggre1_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS
+ &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
+ interconnect-names = "qup-core",
+ "qup-config",
+ "qup-memory";
+
+ dmas = <&gpi_dma1 0 7 QCOM_GPI_SPI>,
+ <&gpi_dma1 1 7 QCOM_GPI_SPI>;
+ dma-names = "tx",
+ "rx";
+
+ pinctrl-0 = <&qup_spi15_data_clk>, <&qup_spi15_cs>;
+ pinctrl-names = "default";
+
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ status = "disabled";
+ };
+ };
+
+ gpi_dma0: dma-controller@b00000 {
+ compatible = "qcom,x1e80100-gpi-dma", "qcom,sm6350-gpi-dma";
+ reg = <0 0x00b00000 0 0x60000>;
+
+ interrupts = <GIC_SPI 588 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 589 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 590 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 591 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 592 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 593 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 594 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 595 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 596 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 597 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 598 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 599 IRQ_TYPE_LEVEL_HIGH>;
+
+ dma-channels = <12>;
+ dma-channel-mask = <0x3e>;
+ #dma-cells = <3>;
+
+ iommus = <&apps_smmu 0x456 0x0>;
+
+ status = "disabled";
+ };
+
+ qupv3_0: geniqup@bc0000 {
+ compatible = "qcom,geni-se-qup";
+ reg = <0 0x00bc0000 0 0x2000>;
+
+ clocks = <&gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>,
+ <&gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>;
+ clock-names = "m-ahb",
+ "s-ahb";
+
+ iommus = <&apps_smmu 0x443 0x0>;
+ #address-cells = <2>;
+ #size-cells = <2>;
+ ranges;
+
+ status = "disabled";
+
+ i2c0: i2c@b80000 {
+ compatible = "qcom,geni-i2c";
+ reg = <0 0xb80000 0 0x4000>;
+
+ interrupts = <GIC_SPI 373 IRQ_TYPE_LEVEL_HIGH>;
+
+ clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>;
+ clock-names = "se";
+
+ interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS
+ &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>,
+ <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
+ &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>,
+ <&aggre2_noc MASTER_QUP_0 QCOM_ICC_TAG_ALWAYS
+ &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
+ interconnect-names = "qup-core",
+ "qup-config",
+ "qup-memory";
+
+ dmas = <&gpi_dma0 0 0 QCOM_GPI_I2C>,
+ <&gpi_dma0 1 0 QCOM_GPI_I2C>;
+ dma-names = "tx",
+ "rx";
+
+ pinctrl-0 = <&qup_i2c0_data_clk>;
+ pinctrl-names = "default";
+
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ status = "disabled";
+ };
+
+ spi0: spi@b80000 {
+ compatible = "qcom,geni-spi";
+ reg = <0 0x00b80000 0 0x4000>;
+
+ interrupts = <GIC_SPI 373 IRQ_TYPE_LEVEL_HIGH>;
+
+ clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>;
+ clock-names = "se";
+
+ interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS
+ &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>,
+ <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
+ &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>,
+ <&aggre2_noc MASTER_QUP_0 QCOM_ICC_TAG_ALWAYS
+ &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
+ interconnect-names = "qup-core",
+ "qup-config",
+ "qup-memory";
+
+ dmas = <&gpi_dma0 0 0 QCOM_GPI_SPI>,
+ <&gpi_dma0 1 0 QCOM_GPI_SPI>;
+ dma-names = "tx",
+ "rx";
+
+ pinctrl-0 = <&qup_spi0_data_clk>, <&qup_spi0_cs>;
+ pinctrl-names = "default";
+
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ status = "disabled";
+ };
+
+ i2c1: i2c@b84000 {
+ compatible = "qcom,geni-i2c";
+ reg = <0 0x00b84000 0 0x4000>;
+
+ interrupts = <GIC_SPI 583 IRQ_TYPE_LEVEL_HIGH>;
+
+ clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>;
+ clock-names = "se";
+
+ interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS
+ &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>,
+ <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
+ &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>,
+ <&aggre2_noc MASTER_QUP_0 QCOM_ICC_TAG_ALWAYS
+ &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
+ interconnect-names = "qup-core",
+ "qup-config",
+ "qup-memory";
+
+ dmas = <&gpi_dma0 0 1 QCOM_GPI_I2C>,
+ <&gpi_dma0 1 1 QCOM_GPI_I2C>;
+ dma-names = "tx",
+ "rx";
+
+ pinctrl-0 = <&qup_i2c1_data_clk>;
+ pinctrl-names = "default";
+
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ status = "disabled";
+ };
+
+ spi1: spi@b84000 {
+ compatible = "qcom,geni-spi";
+ reg = <0 0x00b84000 0 0x4000>;
+
+ interrupts = <GIC_SPI 583 IRQ_TYPE_LEVEL_HIGH>;
+
+ clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>;
+ clock-names = "se";
+
+ interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS
+ &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>,
+ <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
+ &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>,
+ <&aggre2_noc MASTER_QUP_0 QCOM_ICC_TAG_ALWAYS
+ &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
+ interconnect-names = "qup-core",
+ "qup-config",
+ "qup-memory";
+
+ dmas = <&gpi_dma0 0 1 QCOM_GPI_SPI>,
+ <&gpi_dma0 1 1 QCOM_GPI_SPI>;
+ dma-names = "tx",
+ "rx";
+
+ pinctrl-0 = <&qup_spi1_data_clk>, <&qup_spi1_cs>;
+ pinctrl-names = "default";
+
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ status = "disabled";
+ };
+
+ i2c2: i2c@b88000 {
+ compatible = "qcom,geni-i2c";
+ reg = <0 0x00b88000 0 0x4000>;
+
+ interrupts = <GIC_SPI 584 IRQ_TYPE_LEVEL_HIGH>;
+
+ clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>;
+ clock-names = "se";
+
+ interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS
+ &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>,
+ <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
+ &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>,
+ <&aggre2_noc MASTER_QUP_0 QCOM_ICC_TAG_ALWAYS
+ &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
+ interconnect-names = "qup-core",
+ "qup-config",
+ "qup-memory";
+
+ dmas = <&gpi_dma0 0 2 QCOM_GPI_I2C>,
+ <&gpi_dma0 1 2 QCOM_GPI_I2C>;
+ dma-names = "tx",
+ "rx";
+
+ pinctrl-0 = <&qup_i2c2_data_clk>;
+ pinctrl-names = "default";
+
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ status = "disabled";
+ };
+
+ spi2: spi@b88000 {
+ compatible = "qcom,geni-spi";
+ reg = <0 0xb88000 0 0x4000>;
+
+ interrupts = <GIC_SPI 584 IRQ_TYPE_LEVEL_HIGH>;
+
+ clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>;
+ clock-names = "se";
+
+ interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS
+ &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>,
+ <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
+ &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>,
+ <&aggre2_noc MASTER_QUP_0 QCOM_ICC_TAG_ALWAYS
+ &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
+ interconnect-names = "qup-core",
+ "qup-config",
+ "qup-memory";
+
+ dmas = <&gpi_dma0 0 2 QCOM_GPI_SPI>,
+ <&gpi_dma0 1 2 QCOM_GPI_SPI>;
+ dma-names = "tx",
+ "rx";
+
+ pinctrl-0 = <&qup_spi2_data_clk>, <&qup_spi2_cs>;
+ pinctrl-names = "default";
+
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ status = "disabled";
+ };
+
+ i2c3: i2c@b8c000 {
+ compatible = "qcom,geni-i2c";
+ reg = <0 0x00b8c000 0 0x4000>;
+
+ interrupts = <GIC_SPI 585 IRQ_TYPE_LEVEL_HIGH>;
+
+ clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>;
+ clock-names = "se";
+
+ interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS
+ &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>,
+ <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
+ &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>,
+ <&aggre2_noc MASTER_QUP_0 QCOM_ICC_TAG_ALWAYS
+ &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
+ interconnect-names = "qup-core",
+ "qup-config",
+ "qup-memory";
+
+ dmas = <&gpi_dma0 0 3 QCOM_GPI_I2C>,
+ <&gpi_dma0 1 3 QCOM_GPI_I2C>;
+ dma-names = "tx",
+ "rx";
+
+ pinctrl-0 = <&qup_i2c3_data_clk>;
+ pinctrl-names = "default";
+
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ status = "disabled";
+ };
+
+ spi3: spi@b8c000 {
+ compatible = "qcom,geni-spi";
+ reg = <0 0x00b8c000 0 0x4000>;
+
+ interrupts = <GIC_SPI 585 IRQ_TYPE_LEVEL_HIGH>;
+
+ clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>;
+ clock-names = "se";
+
+ interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS
+ &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>,
+ <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
+ &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>,
+ <&aggre2_noc MASTER_QUP_0 QCOM_ICC_TAG_ALWAYS
+ &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
+ interconnect-names = "qup-core",
+ "qup-config",
+ "qup-memory";
+
+ dmas = <&gpi_dma0 0 3 QCOM_GPI_SPI>,
+ <&gpi_dma0 1 3 QCOM_GPI_SPI>;
+ dma-names = "tx",
+ "rx";
+
+ pinctrl-0 = <&qup_spi3_data_clk>, <&qup_spi3_cs>;
+ pinctrl-names = "default";
+
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ status = "disabled";
+ };
+
+ i2c4: i2c@b90000 {
+ compatible = "qcom,geni-i2c";
+ reg = <0 0xb90000 0 0x4000>;
+
+ interrupts = <GIC_SPI 586 IRQ_TYPE_LEVEL_HIGH>;
+
+ clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>;
+ clock-names = "se";
+
+ interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS
+ &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>,
+ <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
+ &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>,
+ <&aggre2_noc MASTER_QUP_0 QCOM_ICC_TAG_ALWAYS
+ &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
+ interconnect-names = "qup-core",
+ "qup-config",
+ "qup-memory";
+
+ dmas = <&gpi_dma0 0 4 QCOM_GPI_I2C>,
+ <&gpi_dma0 1 4 QCOM_GPI_I2C>;
+ dma-names = "tx",
+ "rx";
+
+ pinctrl-0 = <&qup_i2c4_data_clk>;
+ pinctrl-names = "default";
+
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ status = "disabled";
+ };
+
+ spi4: spi@b90000 {
+ compatible = "qcom,geni-spi";
+ reg = <0 0x00b90000 0 0x4000>;
+
+ interrupts = <GIC_SPI 586 IRQ_TYPE_LEVEL_HIGH>;
+
+ clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>;
+ clock-names = "se";
+
+ interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS
+ &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>,
+ <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
+ &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>,
+ <&aggre2_noc MASTER_QUP_0 QCOM_ICC_TAG_ALWAYS
+ &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
+ interconnect-names = "qup-core",
+ "qup-config",
+ "qup-memory";
+
+ dmas = <&gpi_dma0 0 4 QCOM_GPI_SPI>,
+ <&gpi_dma0 1 4 QCOM_GPI_SPI>;
+ dma-names = "tx",
+ "rx";
+
+ pinctrl-0 = <&qup_spi4_data_clk>, <&qup_spi4_cs>;
+ pinctrl-names = "default";
+
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ status = "disabled";
+ };
+
+ i2c5: i2c@b94000 {
+ compatible = "qcom,geni-i2c";
+ reg = <0 0x00b94000 0 0x4000>;
+
+ interrupts = <GIC_SPI 587 IRQ_TYPE_LEVEL_HIGH>;
+
+ clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>;
+ clock-names = "se";
+
+ interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS
+ &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>,
+ <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
+ &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>,
+ <&aggre2_noc MASTER_QUP_0 QCOM_ICC_TAG_ALWAYS
+ &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
+ interconnect-names = "qup-core",
+ "qup-config",
+ "qup-memory";
+
+ dmas = <&gpi_dma0 0 5 QCOM_GPI_I2C>,
+ <&gpi_dma0 1 5 QCOM_GPI_I2C>;
+ dma-names = "tx",
+ "rx";
+
+ pinctrl-0 = <&qup_i2c5_data_clk>;
+ pinctrl-names = "default";
+
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ status = "disabled";
+ };
+
+ spi5: spi@b94000 {
+ compatible = "qcom,geni-spi";
+ reg = <0 0x00b94000 0 0x4000>;
+
+ interrupts = <GIC_SPI 587 IRQ_TYPE_LEVEL_HIGH>;
+
+ clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>;
+ clock-names = "se";
+
+ interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS
+ &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>,
+ <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
+ &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>,
+ <&aggre2_noc MASTER_QUP_0 QCOM_ICC_TAG_ALWAYS
+ &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
+ interconnect-names = "qup-core",
+ "qup-config",
+ "qup-memory";
+
+ dmas = <&gpi_dma0 0 5 QCOM_GPI_SPI>,
+ <&gpi_dma0 1 5 QCOM_GPI_SPI>;
+ dma-names = "tx",
+ "rx";
+
+ pinctrl-0 = <&qup_spi5_data_clk>, <&qup_spi5_cs>;
+ pinctrl-names = "default";
+
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ status = "disabled";
+ };
+
+ i2c6: i2c@b98000 {
+ compatible = "qcom,geni-i2c";
+ reg = <0 0x00b98000 0 0x4000>;
+
+ interrupts = <GIC_SPI 461 IRQ_TYPE_LEVEL_HIGH>;
+
+ clocks = <&gcc GCC_QUPV3_WRAP0_S6_CLK>;
+ clock-names = "se";
+
+ interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS
+ &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>,
+ <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
+ &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>,
+ <&aggre2_noc MASTER_QUP_0 QCOM_ICC_TAG_ALWAYS
+ &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
+ interconnect-names = "qup-core",
+ "qup-config",
+ "qup-memory";
+
+ dmas = <&gpi_dma0 0 6 QCOM_GPI_I2C>,
+ <&gpi_dma0 1 6 QCOM_GPI_I2C>;
+ dma-names = "tx",
+ "rx";
+
+ pinctrl-0 = <&qup_i2c6_data_clk>;
+ pinctrl-names = "default";
+
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ status = "disabled";
+ };
+
+ spi6: spi@b98000 {
+ compatible = "qcom,geni-spi";
+ reg = <0 0x00b98000 0 0x4000>;
+
+ interrupts = <GIC_SPI 461 IRQ_TYPE_LEVEL_HIGH>;
+
+ clocks = <&gcc GCC_QUPV3_WRAP0_S6_CLK>;
+ clock-names = "se";
+
+ interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS
+ &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>,
+ <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
+ &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>,
+ <&aggre2_noc MASTER_QUP_0 QCOM_ICC_TAG_ALWAYS
+ &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
+ interconnect-names = "qup-core",
+ "qup-config",
+ "qup-memory";
+
+ dmas = <&gpi_dma0 0 6 QCOM_GPI_SPI>,
+ <&gpi_dma0 1 6 QCOM_GPI_SPI>;
+ dma-names = "tx",
+ "rx";
+
+ pinctrl-0 = <&qup_spi6_data_clk>, <&qup_spi6_cs>;
+ pinctrl-names = "default";
+
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ status = "disabled";
+ };
+
+ i2c7: i2c@b9c000 {
+ compatible = "qcom,geni-i2c";
+ reg = <0 0x00b9c000 0 0x4000>;
+
+ interrupts = <GIC_SPI 462 IRQ_TYPE_LEVEL_HIGH>;
+
+ clocks = <&gcc GCC_QUPV3_WRAP0_S7_CLK>;
+ clock-names = "se";
+
+ interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS
+ &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>,
+ <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
+ &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>,
+ <&aggre2_noc MASTER_QUP_0 QCOM_ICC_TAG_ALWAYS
+ &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
+ interconnect-names = "qup-core",
+ "qup-config",
+ "qup-memory";
+
+ dmas = <&gpi_dma0 0 7 QCOM_GPI_I2C>,
+ <&gpi_dma0 1 7 QCOM_GPI_I2C>;
+ dma-names = "tx",
+ "rx";
+
+ pinctrl-0 = <&qup_i2c7_data_clk>;
+ pinctrl-names = "default";
+
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ status = "disabled";
+ };
+
+ spi7: spi@b9c000 {
+ compatible = "qcom,geni-spi";
+ reg = <0 0x00b9c000 0 0x4000>;
+
+ interrupts = <GIC_SPI 462 IRQ_TYPE_LEVEL_HIGH>;
+
+ clocks = <&gcc GCC_QUPV3_WRAP0_S7_CLK>;
+ clock-names = "se";
+
+ interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS
+ &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>,
+ <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
+ &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>,
+ <&aggre2_noc MASTER_QUP_0 QCOM_ICC_TAG_ALWAYS
+ &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
+ interconnect-names = "qup-core",
+ "qup-config",
+ "qup-memory";
+
+ dmas = <&gpi_dma0 0 7 QCOM_GPI_SPI>,
+ <&gpi_dma0 1 7 QCOM_GPI_SPI>;
+ dma-names = "tx",
+ "rx";
+
+ pinctrl-0 = <&qup_spi7_data_clk>, <&qup_spi7_cs>;
+ pinctrl-names = "default";
+
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ status = "disabled";
+ };
+ };
+
+ cnoc_main: interconnect@1500000 {
+ compatible = "qcom,x1e80100-cnoc-main";
+ reg = <0 0x1500000 0 0x14400>;
+
+ qcom,bcm-voters = <&apps_bcm_voter>;
+
+ #interconnect-cells = <2>;
+ };
+
+ config_noc: interconnect@1600000 {
+ compatible = "qcom,x1e80100-cnoc-cfg";
+ reg = <0 0x1600000 0 0x6600>;
+
+ qcom,bcm-voters = <&apps_bcm_voter>;
+
+ #interconnect-cells = <2>;
+ };
+
+ system_noc: interconnect@1680000 {
+ compatible = "qcom,x1e80100-system-noc";
+ reg = <0 0x1680000 0 0x1c080>;
+
+ qcom,bcm-voters = <&apps_bcm_voter>;
+
+ #interconnect-cells = <2>;
+ };
+
+ pcie_south_anoc: interconnect@16c0000 {
+ compatible = "qcom,x1e80100-pcie-south-anoc";
+ reg = <0 0x16c0000 0 0xd080>;
+
+ qcom,bcm-voters = <&apps_bcm_voter>;
+
+ #interconnect-cells = <2>;
+ };
+
+ pcie_center_anoc: interconnect@16d0000 {
+ compatible = "qcom,x1e80100-pcie-center-anoc";
+ reg = <0 0x16d0000 0 0x7000>;
+
+ qcom,bcm-voters = <&apps_bcm_voter>;
+
+ #interconnect-cells = <2>;
+ };
+
+ aggre1_noc: interconnect@16e0000 {
+ compatible = "qcom,x1e80100-aggre1-noc";
+ reg = <0 0x16E0000 0 0x14400>;
+
+ qcom,bcm-voters = <&apps_bcm_voter>;
+
+ #interconnect-cells = <2>;
+ };
+
+ aggre2_noc: interconnect@1700000 {
+ compatible = "qcom,x1e80100-aggre2-noc";
+ reg = <0 0x1700000 0 0x1c400>;
+
+ qcom,bcm-voters = <&apps_bcm_voter>;
+
+ #interconnect-cells = <2>;
+ };
+
+ pcie_north_anoc: interconnect@1740000 {
+ compatible = "qcom,x1e80100-pcie-north-anoc";
+ reg = <0 0x1740000 0 0x9080>;
+
+ qcom,bcm-voters = <&apps_bcm_voter>;
+
+ #interconnect-cells = <2>;
+ };
+
+ usb_center_anoc: interconnect@1750000 {
+ compatible = "qcom,x1e80100-usb-center-anoc";
+ reg = <0 0x1750000 0 0x8800>;
+
+ qcom,bcm-voters = <&apps_bcm_voter>;
+
+ #interconnect-cells = <2>;
+ };
+
+ usb_north_anoc: interconnect@1760000 {
+ compatible = "qcom,x1e80100-usb-north-anoc";
+ reg = <0 0x1760000 0 0x7080>;
+
+ qcom,bcm-voters = <&apps_bcm_voter>;
+
+ #interconnect-cells = <2>;
+ };
+
+ usb_south_anoc: interconnect@1770000 {
+ compatible = "qcom,x1e80100-usb-south-anoc";
+ reg = <0 0x1770000 0 0xf080>;
+
+ qcom,bcm-voters = <&apps_bcm_voter>;
+
+ #interconnect-cells = <2>;
+ };
+
+ mmss_noc: interconnect@1780000 {
+ compatible = "qcom,x1e80100-mmss-noc";
+ reg = <0 0x1780000 0 0x5B800>;
+
+ qcom,bcm-voters = <&apps_bcm_voter>;
+
+ #interconnect-cells = <2>;
+ };
+
+ tcsr_mutex: hwlock@1f40000 {
+ compatible = "qcom,tcsr-mutex";
+ reg = <0 0x01f40000 0 0x20000>;
+ #hwlock-cells = <1>;
+ };
+
+ gem_noc: interconnect@26400000 {
+ compatible = "qcom,x1e80100-gem-noc";
+ reg = <0 0x26400000 0 0x311200>;
+
+ qcom,bcm-voters = <&apps_bcm_voter>;
+
+ #interconnect-cells = <2>;
+ };
+
+ nsp_noc: interconnect@320c0000 {
+ compatible = "qcom,x1e80100-nsp-noc";
+ reg = <0 0x320C0000 0 0xE080>;
+
+ qcom,bcm-voters = <&apps_bcm_voter>;
+
+ #interconnect-cells = <2>;
+ };
+
+ lpass_ag_noc: interconnect@7e40000 {
+ compatible = "qcom,x1e80100-lpass-ag-noc";
+ reg = <0 0x7e40000 0 0xE080>;
+
+ qcom,bcm-voters = <&apps_bcm_voter>;
+
+ #interconnect-cells = <2>;
+ };
+
+ lpass_lpiaon_noc: interconnect@7400000 {
+ compatible = "qcom,x1e80100-lpass-lpiaon-noc";
+ reg = <0 0x7400000 0 0x19080>;
+
+ qcom,bcm-voters = <&apps_bcm_voter>;
+
+ #interconnect-cells = <2>;
+ };
+
+ lpass_lpicx_noc: interconnect@7430000 {
+ compatible = "qcom,x1e80100-lpass-lpicx-noc";
+ reg = <0 0x7430000 0 0x3A200>;
+
+ qcom,bcm-voters = <&apps_bcm_voter>;
+
+ #interconnect-cells = <2>;
+ };
+
+ pdc: interrupt-controller@b220000 {
+ compatible = "qcom,x1e80100-pdc", "qcom,pdc";
+ reg = <0 0x0b220000 0 0x30000>, <0 0x174000f0 0 0x64>;
+
+ qcom,pdc-ranges = <0 480 42>, <42 251 5>,
+ <47 522 52>, <99 609 32>,
+ <131 717 12>, <143 816 19>;
+ #interrupt-cells = <2>;
+ interrupt-parent = <&intc>;
+ interrupt-controller;
+ };
+
+ tlmm: pinctrl@f100000 {
+ compatible = "qcom,x1e80100-tlmm";
+ reg = <0 0x0f100000 0 0xf00000>;
+
+ interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>;
+
+ gpio-controller;
+ #gpio-cells = <2>;
+
+ interrupt-controller;
+ #interrupt-cells = <2>;
+
+ gpio-ranges = <&tlmm 0 0 239>;
+ wakeup-parent = <&pdc>;
+
+ qup_i2c0_data_clk: qup-i2c0-data-clk-state {
+ /* SDA, SCL */
+ pins = "gpio0", "gpio1";
+ function = "qup0_se0";
+ drive-strength = <2>;
+ bias-pull-up = <2200>;
+ };
+
+ qup_i2c1_data_clk: qup-i2c1-data-clk-state {
+ /* SDA, SCL */
+ pins = "gpio4", "gpio5";
+ function = "qup0_se1";
+ drive-strength = <2>;
+ bias-pull-up = <2200>;
+ };
+
+ qup_i2c2_data_clk: qup-i2c2-data-clk-state {
+ /* SDA, SCL */
+ pins = "gpio8", "gpio9";
+ function = "qup0_se2";
+ drive-strength = <2>;
+ bias-pull-up = <2200>;
+ };
+
+ qup_i2c3_data_clk: qup-i2c3-data-clk-state {
+ /* SDA, SCL */
+ pins = "gpio12", "gpio13";
+ function = "qup0_se3";
+ drive-strength = <2>;
+ bias-pull-up = <2200>;
+ };
+
+ qup_i2c4_data_clk: qup-i2c4-data-clk-state {
+ /* SDA, SCL */
+ pins = "gpio16", "gpio17";
+ function = "qup0_se4";
+ drive-strength = <2>;
+ bias-pull-up = <2200>;
+ };
+
+ qup_i2c5_data_clk: qup-i2c5-data-clk-state {
+ /* SDA, SCL */
+ pins = "gpio20", "gpio21";
+ function = "qup0_se5";
+ drive-strength = <2>;
+ bias-pull-up = <2200>;
+ };
+
+ qup_i2c6_data_clk: qup-i2c6-data-clk-state {
+ /* SDA, SCL */
+ pins = "gpio24", "gpio25";
+ function = "qup0_se6";
+ drive-strength = <2>;
+ bias-pull-up = <2200>;
+ };
+
+ qup_i2c7_data_clk: qup-i2c7-data-clk-state {
+ /* SDA, SCL */
+ pins = "gpio14", "gpio15";
+ function = "qup0_se7";
+ drive-strength = <2>;
+ bias-pull-up = <2200>;
+ };
+
+ qup_i2c8_data_clk: qup-i2c8-data-clk-state {
+ /* SDA, SCL */
+ pins = "gpio32", "gpio33";
+ function = "qup1_se0";
+ drive-strength = <2>;
+ bias-pull-up = <2200>;
+ };
+
+ qup_i2c9_data_clk: qup-i2c9-data-clk-state {
+ /* SDA, SCL */
+ pins = "gpio36", "gpio37";
+ function = "qup1_se1";
+ drive-strength = <2>;
+ bias-pull-up = <2200>;
+ };
+
+ qup_i2c10_data_clk: qup-i2c10-data-clk-state {
+ /* SDA, SCL */
+ pins = "gpio40", "gpio41";
+ function = "qup1_se2";
+ drive-strength = <2>;
+ bias-pull-up = <2200>;
+ };
+
+ qup_i2c11_data_clk: qup-i2c11-data-clk-state {
+ /* SDA, SCL */
+ pins = "gpio44", "gpio45";
+ function = "qup1_se3";
+ drive-strength = <2>;
+ bias-pull-up = <2200>;
+ };
+
+ qup_i2c12_data_clk: qup-i2c12-data-clk-state {
+ /* SDA, SCL */
+ pins = "gpio48", "gpio49";
+ function = "qup1_se4";
+ drive-strength = <2>;
+ bias-pull-up = <2200>;
+ };
+
+ qup_i2c13_data_clk: qup-i2c13-data-clk-state {
+ /* SDA, SCL */
+ pins = "gpio52", "gpio53";
+ function = "qup1_se5";
+ drive-strength = <2>;
+ bias-pull-up = <2200>;
+ };
+
+ qup_i2c14_data_clk: qup-i2c14-data-clk-state {
+ /* SDA, SCL */
+ pins = "gpio56", "gpio57";
+ function = "qup1_se6";
+ drive-strength = <2>;
+ bias-pull-up = <2200>;
+ };
+
+ qup_i2c15_data_clk: qup-i2c15-data-clk-state {
+ /* SDA, SCL */
+ pins = "gpio54", "gpio55";
+ function = "qup1_se7";
+ drive-strength = <2>;
+ bias-pull-up = <2200>;
+ };
+
+ qup_i2c16_data_clk: qup-i2c16-data-clk-state {
+ /* SDA, SCL */
+ pins = "gpio64", "gpio65";
+ function = "qup2_se0";
+ drive-strength = <2>;
+ bias-pull-up = <2200>;
+ };
+
+ qup_i2c17_data_clk: qup-i2c17-data-clk-state {
+ /* SDA, SCL */
+ pins = "gpio68", "gpio69";
+ function = "qup2_se1";
+ drive-strength = <2>;
+ bias-pull-up = <2200>;
+ };
+
+ qup_i2c18_data_clk: qup-i2c18-data-clk-state {
+ /* SDA, SCL */
+ pins = "gpio72", "gpio73";
+ function = "qup2_se2";
+ drive-strength = <2>;
+ bias-pull-up = <2200>;
+ };
+
+ qup_i2c19_data_clk: qup-i2c19-data-clk-state {
+ /* SDA, SCL */
+ pins = "gpio76", "gpio77";
+ function = "qup2_se3";
+ drive-strength = <2>;
+ bias-pull-up = <2200>;
+ };
+
+ qup_i2c20_data_clk: qup-i2c20-data-clk-state {
+ /* SDA, SCL */
+ pins = "gpio80", "gpio81";
+ function = "qup2_se4";
+ drive-strength = <2>;
+ bias-pull-up = <2200>;
+ };
+
+ qup_i2c21_data_clk: qup-i2c21-data-clk-state {
+ /* SDA, SCL */
+ pins = "gpio84", "gpio85";
+ function = "qup2_se5";
+ drive-strength = <2>;
+ bias-pull-up = <2200>;
+ };
+
+ qup_i2c22_data_clk: qup-i2c22-data-clk-state {
+ /* SDA, SCL */
+ pins = "gpio88", "gpio89";
+ function = "qup2_se6";
+ drive-strength = <2>;
+ bias-pull-up = <2200>;
+ };
+
+ qup_i2c23_data_clk: qup-i2c23-data-clk-state {
+ /* SDA, SCL */
+ pins = "gpio86", "gpio87";
+ function = "qup2_se7";
+ drive-strength = <2>;
+ bias-pull-up = <2200>;
+ };
+
+ qup_spi0_cs: qup-spi0-cs-state {
+ pins = "gpio3";
+ function = "qup0_se0";
+ drive-strength = <6>;
+ bias-disable;
+ };
+
+ qup_spi0_data_clk: qup-spi0-data-clk-state {
+ /* MISO, MOSI, CLK */
+ pins = "gpio0", "gpio1", "gpio2";
+ function = "qup0_se0";
+ drive-strength = <6>;
+ bias-disable;
+ };
+
+ qup_spi1_cs: qup-spi1-cs-state {
+ pins = "gpio7";
+ function = "qup0_se1";
+ drive-strength = <6>;
+ bias-disable;
+ };
+
+ qup_spi1_data_clk: qup-spi1-data-clk-state {
+ /* MISO, MOSI, CLK */
+ pins = "gpio4", "gpio5", "gpio6";
+ function = "qup0_se1";
+ drive-strength = <6>;
+ bias-disable;
+ };
+
+ qup_spi2_cs: qup-spi2-cs-state {
+ pins = "gpio11";
+ function = "qup0_se2";
+ drive-strength = <6>;
+ bias-disable;
+ };
+
+ qup_spi2_data_clk: qup-spi2-data-clk-state {
+ /* MISO, MOSI, CLK */
+ pins = "gpio8", "gpio9", "gpio10";
+ function = "qup0_se2";
+ drive-strength = <6>;
+ bias-disable;
+ };
+
+ qup_spi3_cs: qup-spi3-cs-state {
+ pins = "gpio15";
+ function = "qup0_se3";
+ drive-strength = <6>;
+ bias-disable;
+ };
+
+ qup_spi3_data_clk: qup-spi3-data-clk-state {
+ /* MISO, MOSI, CLK */
+ pins = "gpio12", "gpio13", "gpio14";
+ function = "qup0_se3";
+ drive-strength = <6>;
+ bias-disable;
+ };
+
+ qup_spi4_cs: qup-spi4-cs-state {
+ pins = "gpio19";
+ function = "qup0_se4";
+ drive-strength = <6>;
+ bias-disable;
+ };
+
+ qup_spi4_data_clk: qup-spi4-data-clk-state {
+ /* MISO, MOSI, CLK */
+ pins = "gpio16", "gpio17", "gpio18";
+ function = "qup0_se4";
+ drive-strength = <6>;
+ bias-disable;
+ };
+
+ qup_spi5_cs: qup-spi5-cs-state {
+ pins = "gpio23";
+ function = "qup0_se5";
+ drive-strength = <6>;
+ bias-disable;
+ };
+
+ qup_spi5_data_clk: qup-spi5-data-clk-state {
+ /* MISO, MOSI, CLK */
+ pins = "gpio20", "gpio21", "gpio22";
+ function = "qup0_se5";
+ drive-strength = <6>;
+ bias-disable;
+ };
+
+ qup_spi6_cs: qup-spi6-cs-state {
+ pins = "gpio27";
+ function = "qup0_se6";
+ drive-strength = <6>;
+ bias-disable;
+ };
+
+ qup_spi6_data_clk: qup-spi6-data-clk-state {
+ /* MISO, MOSI, CLK */
+ pins = "gpio24", "gpio25", "gpio26";
+ function = "qup0_se6";
+ drive-strength = <6>;
+ bias-disable;
+ };
+
+ qup_spi7_cs: qup-spi7-cs-state {
+ pins = "gpio13";
+ function = "qup0_se7";
+ drive-strength = <6>;
+ bias-disable;
+ };
+
+ qup_spi7_data_clk: qup-spi7-data-clk-state {
+ /* MISO, MOSI, CLK */
+ pins = "gpio14", "gpio15", "gpio12";
+ function = "qup0_se7";
+ drive-strength = <6>;
+ bias-disable;
+ };
+
+ qup_spi8_cs: qup-spi8-cs-state {
+ pins = "gpio35";
+ function = "qup1_se0";
+ drive-strength = <6>;
+ bias-disable;
+ };
+
+ qup_spi8_data_clk: qup-spi8-data-clk-state {
+ /* MISO, MOSI, CLK */
+ pins = "gpio32", "gpio33", "gpio34";
+ function = "qup1_se0";
+ drive-strength = <6>;
+ bias-disable;
+ };
+
+ qup_spi9_cs: qup-spi9-cs-state {
+ pins = "gpio39";
+ function = "qup1_se1";
+ drive-strength = <6>;
+ bias-disable;
+ };
+
+ qup_spi9_data_clk: qup-spi9-data-clk-state {
+ /* MISO, MOSI, CLK */
+ pins = "gpio36", "gpio37", "gpio38";
+ function = "qup1_se1";
+ drive-strength = <6>;
+ bias-disable;
+ };
+
+ qup_spi10_cs: qup-spi10-cs-state {
+ pins = "gpio43";
+ function = "qup1_se2";
+ drive-strength = <6>;
+ bias-disable;
+ };
+
+ qup_spi10_data_clk: qup-spi10-data-clk-state {
+ /* MISO, MOSI, CLK */
+ pins = "gpio40", "gpio41", "gpio42";
+ function = "qup1_se2";
+ drive-strength = <6>;
+ bias-disable;
+ };
+
+ qup_spi11_cs: qup-spi11-cs-state {
+ pins = "gpio47";
+ function = "qup1_se3";
+ drive-strength = <6>;
+ bias-disable;
+ };
+
+ qup_spi11_data_clk: qup-spi11-data-clk-state {
+ /* MISO, MOSI, CLK */
+ pins = "gpio44", "gpio45", "gpio46";
+ function = "qup1_se3";
+ drive-strength = <6>;
+ bias-disable;
+ };
+
+ qup_spi12_cs: qup-spi12-cs-state {
+ pins = "gpio51";
+ function = "qup1_se4";
+ drive-strength = <6>;
+ bias-disable;
+ };
+
+ qup_spi12_data_clk: qup-spi12-data-clk-state {
+ /* MISO, MOSI, CLK */
+ pins = "gpio48", "gpio49", "gpio50";
+ function = "qup1_se4";
+ drive-strength = <6>;
+ bias-disable;
+ };
+
+ qup_spi13_cs: qup-spi13-cs-state {
+ pins = "gpio55";
+ function = "qup1_se5";
+ drive-strength = <6>;
+ bias-disable;
+ };
+
+ qup_spi13_data_clk: qup-spi13-data-clk-state {
+ /* MISO, MOSI, CLK */
+ pins = "gpio52", "gpio53", "gpio54";
+ function = "qup1_se5";
+ drive-strength = <6>;
+ bias-disable;
+ };
+
+ qup_spi14_cs: qup-spi14-cs-state {
+ pins = "gpio59";
+ function = "qup1_se6";
+ drive-strength = <6>;
+ bias-disable;
+ };
+
+ qup_spi14_data_clk: qup-spi14-data-clk-state {
+ /* MISO, MOSI, CLK */
+ pins = "gpio56", "gpio57", "gpio58";
+ function = "qup1_se6";
+ drive-strength = <6>;
+ bias-disable;
+ };
+
+ qup_spi15_cs: qup-spi15-cs-state {
+ pins = "gpio53";
+ function = "qup1_se7";
+ drive-strength = <6>;
+ bias-disable;
+ };
+
+ qup_spi15_data_clk: qup-spi15-data-clk-state {
+ /* MISO, MOSI, CLK */
+ pins = "gpio54", "gpio55", "gpio52";
+ function = "qup1_se7";
+ drive-strength = <6>;
+ bias-disable;
+ };
+
+ qup_spi16_cs: qup-spi16-cs-state {
+ pins = "gpio67";
+ function = "qup2_se0";
+ drive-strength = <6>;
+ bias-disable;
+ };
+
+ qup_spi16_data_clk: qup-spi16-data-clk-state {
+ /* MISO, MOSI, CLK */
+ pins = "gpio64", "gpio65", "gpio66";
+ function = "qup2_se0";
+ drive-strength = <6>;
+ bias-disable;
+ };
+
+ qup_spi17_cs: qup-spi17-cs-state {
+ pins = "gpio71";
+ function = "qup2_se1";
+ drive-strength = <6>;
+ bias-disable;
+ };
+
+ qup_spi17_data_clk: qup-spi17-data-clk-state {
+ /* MISO, MOSI, CLK */
+ pins = "gpio68", "gpio69", "gpio70";
+ function = "qup2_se1";
+ drive-strength = <6>;
+ bias-disable;
+ };
+
+ qup_spi18_cs: qup-spi18-cs-state {
+ pins = "gpio75";
+ function = "qup2_se2";
+ drive-strength = <6>;
+ bias-disable;
+ };
+
+ qup_spi18_data_clk: qup-spi18-data-clk-state {
+ /* MISO, MOSI, CLK */
+ pins = "gpio72", "gpio73", "gpio74";
+ function = "qup2_se2";
+ drive-strength = <6>;
+ bias-disable;
+ };
+
+ qup_spi19_cs: qup-spi19-cs-state {
+ pins = "gpio79";
+ function = "qup2_se3";
+ drive-strength = <6>;
+ bias-disable;
+ };
+
+ qup_spi19_data_clk: qup-spi19-data-clk-state {
+ /* MISO, MOSI, CLK */
+ pins = "gpio76", "gpio77", "gpio78";
+ function = "qup2_se3";
+ drive-strength = <6>;
+ bias-disable;
+ };
+
+ qup_spi20_cs: qup-spi20-cs-state {
+ pins = "gpio83";
+ function = "qup2_se4";
+ drive-strength = <6>;
+ bias-disable;
+ };
+
+ qup_spi20_data_clk: qup-spi20-data-clk-state {
+ /* MISO, MOSI, CLK */
+ pins = "gpio80", "gpio81", "gpio82";
+ function = "qup2_se4";
+ drive-strength = <6>;
+ bias-disable;
+ };
+
+ qup_spi21_cs: qup-spi21-cs-state {
+ pins = "gpio87";
+ function = "qup2_se5";
+ drive-strength = <6>;
+ bias-disable;
+ };
+
+ qup_spi21_data_clk: qup-spi21-data-clk-state {
+ /* MISO, MOSI, CLK */
+ pins = "gpio84", "gpio85", "gpio86";
+ function = "qup2_se5";
+ drive-strength = <6>;
+ bias-disable;
+ };
+
+ qup_spi22_cs: qup-spi22-cs-state {
+ pins = "gpio91";
+ function = "qup2_se6";
+ drive-strength = <6>;
+ bias-disable;
+ };
+
+ qup_spi22_data_clk: qup-spi22-data-clk-state {
+ /* MISO, MOSI, CLK */
+ pins = "gpio88", "gpio89", "gpio90";
+ function = "qup2_se6";
+ drive-strength = <6>;
+ bias-disable;
+ };
+
+ qup_spi23_cs: qup-spi23-cs-state {
+ pins = "gpio85";
+ function = "qup2_se7";
+ drive-strength = <6>;
+ bias-disable;
+ };
+
+ qup_spi23_data_clk: qup-spi23-data-clk-state {
+ /* MISO, MOSI, CLK */
+ pins = "gpio86", "gpio87", "gpio84";
+ function = "qup2_se7";
+ drive-strength = <6>;
+ bias-disable;
+ };
+
+ qup_uart21_default: qup-uart21-default-state {
+ /* TX, RX */
+ pins = "gpio86", "gpio87";
+ function = "qup2_se5";
+ drive-strength= <2>;
+ bias-disable;
+ };
+ };
+
+ apps_smmu: iommu@15000000 {
+ compatible = "qcom,x1e80100-smmu-500", "qcom,smmu-500", "arm,mmu-500";
+ reg = <0 0x15000000 0 0x100000>;
+
+ interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 181 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 182 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 319 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 322 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 323 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 324 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 325 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 333 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 336 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 337 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 338 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 339 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 340 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 341 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 342 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 343 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 344 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 345 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 395 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 396 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 397 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 398 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 399 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 400 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 401 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 402 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 403 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 404 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 405 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 406 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 407 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 408 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 409 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 418 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 419 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 412 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 421 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 707 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 423 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 424 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 425 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 690 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 691 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 692 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 693 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 694 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 695 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 696 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 697 IRQ_TYPE_LEVEL_HIGH>;
+
+ #iommu-cells = <2>;
+ #global-interrupts = <1>;
+ };
+
+ intc: interrupt-controller@17000000 {
+ compatible = "arm,gic-v3";
+ reg = <0 0x17000000 0 0x10000>, /* GICD */
+ <0 0x17080000 0 0x480000>; /* GICR * 12 */
+
+ interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
+
+ #interrupt-cells = <3>;
+ interrupt-controller;
+
+ #redistributor-regions = <1>;
+ redistributor-stride = <0x0 0x40000>;
+
+ #address-cells = <2>;
+ #size-cells = <2>;
+ ranges;
+
+ gic_its: msi-controller@17040000 {
+ compatible = "arm,gic-v3-its";
+ reg = <0 0x17040000 0 0x40000>;
+
+ msi-controller;
+ #msi-cells = <1>;
+
+ status = "disabled";
+ };
+ };
+
+ apps_rsc: rsc@17500000 {
+ compatible = "qcom,rpmh-rsc";
+ reg = <0 0x17500000 0 0x10000>,
+ <0 0x17510000 0 0x10000>,
+ <0 0x17520000 0 0x10000>;
+ reg-names = "drv-0", "drv-1", "drv-2";
+ qcom,drv-count = <3>;
+
+ interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
+ qcom,tcs-offset = <0xd00>;
+ qcom,drv-id = <2>;
+ qcom,tcs-config = <ACTIVE_TCS 3>, <SLEEP_TCS 2>,
+ <WAKE_TCS 2>, <CONTROL_TCS 0>;
+
+ label = "apps_rsc";
+
+ apps_bcm_voter: bcm-voter {
+ compatible = "qcom,bcm-voter";
+ };
+
+ rpmhcc: clock-controller {
+ compatible = "qcom,x1e80100-rpmh-clk";
+
+ clocks = <&xo_board>;
+ clock-names = "xo";
+
+ #clock-cells = <1>;
+ };
+
+ rpmhpd: power-controller {
+ compatible = "qcom,x1e80100-rpmhpd";
+
+ operating-points-v2 = <&rpmhpd_opp_table>;
+
+ #power-domain-cells = <1>;
+
+ rpmhpd_opp_table: opp-table {
+ compatible = "operating-points-v2";
+
+ rpmhpd_opp_ret: opp-16 {
+ opp-level = <RPMH_REGULATOR_LEVEL_RETENTION>;
+ };
+
+ rpmhpd_opp_min_svs: opp-48 {
+ opp-level = <RPMH_REGULATOR_LEVEL_MIN_SVS>;
+ };
+
+ rpmhpd_opp_low_svs_d2: opp-52 {
+ opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS_D2>;
+ };
+
+ rpmhpd_opp_low_svs_d1: opp-56 {
+ opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS_D1>;
+ };
+
+ rpmhpd_opp_low_svs_d0: opp-60 {
+ opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS_D0>;
+ };
+
+ rpmhpd_opp_low_svs: opp-64 {
+ opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>;
+ };
+
+ rpmhpd_opp_low_svs_l1: opp-80 {
+ opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS_L1>;
+ };
+
+ rpmhpd_opp_svs: opp-128 {
+ opp-level = <RPMH_REGULATOR_LEVEL_SVS>;
+ };
+
+ rpmhpd_opp_svs_l0: opp-144 {
+ opp-level = <RPMH_REGULATOR_LEVEL_SVS_L0>;
+ };
+
+ rpmhpd_opp_svs_l1: opp-192 {
+ opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>;
+ };
+
+ rpmhpd_opp_nom: opp-256 {
+ opp-level = <RPMH_REGULATOR_LEVEL_NOM>;
+ };
+
+ rpmhpd_opp_nom_l1: opp-320 {
+ opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>;
+ };
+
+ rpmhpd_opp_nom_l2: opp-336 {
+ opp-level = <RPMH_REGULATOR_LEVEL_NOM_L2>;
+ };
+
+ rpmhpd_opp_turbo: opp-384 {
+ opp-level = <RPMH_REGULATOR_LEVEL_TURBO>;
+ };
+
+ rpmhpd_opp_turbo_l1: opp-416 {
+ opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L1>;
+ };
+ };
+ };
+ };
+
+ timer@17800000 {
+ compatible = "arm,armv7-timer-mem";
+ reg = <0 0x17800000 0 0x1000>;
+
+ #address-cells = <2>;
+ #size-cells = <1>;
+ ranges = <0 0 0 0 0x20000000>;
+
+ frame@17801000 {
+ reg = <0 0x17801000 0x1000>,
+ <0 0x17802000 0x1000>;
+
+ interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
+
+ frame-number = <0>;
+ };
+
+ frame@17803000 {
+ reg = <0 0x17803000 0x1000>;
+
+ interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
+
+ frame-number = <1>;
+
+ status = "disabled";
+ };
+
+ frame@17805000 {
+ reg = <0 0x17805000 0x1000>;
+
+ interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
+
+ frame-number = <2>;
+
+ status = "disabled";
+ };
+
+ frame@17807000 {
+ reg = <0 0x17807000 0x1000>;
+
+ interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
+
+ frame-number = <3>;
+
+ status = "disabled";
+ };
+
+ frame@17809000 {
+ reg = <0 0x17809000 0x1000>;
+
+ interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
+
+ frame-number = <4>;
+
+ status = "disabled";
+ };
+
+ frame@1780b000 {
+ reg = <0 0x1780b000 0x1000>;
+
+ interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
+
+ frame-number = <5>;
+
+ status = "disabled";
+ };
+
+ frame@1780d000 {
+ reg = <0 0x1780d000 0x1000>;
+
+ interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
+
+ frame-number = <6>;
+
+ status = "disabled";
+ };
+ };
+
+ system-cache-controller@25000000 {
+ compatible = "qcom,x1e80100-llcc";
+ reg = <0 0x25000000 0 0x200000>,
+ <0 0x25200000 0 0x200000>,
+ <0 0x25400000 0 0x200000>,
+ <0 0x25600000 0 0x200000>,
+ <0 0x25800000 0 0x200000>,
+ <0 0x25a00000 0 0x200000>,
+ <0 0x25c00000 0 0x200000>,
+ <0 0x25e00000 0 0x200000>,
+ <0 0x26000000 0 0x200000>;
+ reg-names = "llcc0_base",
+ "llcc1_base",
+ "llcc2_base",
+ "llcc3_base",
+ "llcc4_base",
+ "llcc5_base",
+ "llcc6_base",
+ "llcc7_base",
+ "llcc_broadcast_base";
+ interrupts = <GIC_SPI 266 IRQ_TYPE_LEVEL_HIGH>;
+ };
+ };
+
+ timer {
+ compatible = "arm,armv8-timer";
+
+ interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>,
+ <GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>,
+ <GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>,
+ <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>;
+ };
+};
diff --git a/dts/upstream/src/arm64/renesas/draak.dtsi b/dts/upstream/src/arm64/renesas/draak.dtsi
index ef3bb83..6f133f5 100644
--- a/dts/upstream/src/arm64/renesas/draak.dtsi
+++ b/dts/upstream/src/arm64/renesas/draak.dtsi
@@ -356,12 +356,9 @@
* CVBS and HDMI inputs through SW[49-53]
* switches.
*
- * CVBS is the default selection, link it to
- * VIN4 here.
+ * HDMI is the default selection, leave CVBS
+ * not connected here.
*/
- adv7180_out: endpoint {
- remote-endpoint = <&vin4_in>;
- };
};
};
@@ -374,6 +371,12 @@
interrupt-parent = <&gpio1>;
interrupts = <28 IRQ_TYPE_LEVEL_LOW>;
+ avdd-supply = <®_1p8v>;
+ dvdd-supply = <®_1p8v>;
+ pvdd-supply = <®_1p8v>;
+ dvdd-3v-supply = <®_3p3v>;
+ bgvdd-supply = <®_1p8v>;
+
adi,input-depth = <8>;
adi,input-colorspace = "rgb";
adi,input-clock = "1x";
@@ -423,13 +426,11 @@
* CVBS and HDMI inputs through SW[49-53]
* switches.
*
- * CVBS is the default selection, leave HDMI
- * not connected here.
+ * HDMI is the default selection, link it to
+ * VIN4 here.
*/
adv7612_out: endpoint {
- pclk-sample = <0>;
- hsync-active = <0>;
- vsync-active = <0>;
+ remote-endpoint = <&vin4_in>;
};
};
};
@@ -580,8 +581,8 @@
function = "usb0";
};
- vin4_pins_cvbs: vin4 {
- groups = "vin4_data8", "vin4_sync", "vin4_clk";
+ vin4_pins: vin4 {
+ groups = "vin4_data24", "vin4_sync", "vin4_clk";
function = "vin4";
};
};
@@ -729,7 +730,7 @@
};
&vin4 {
- pinctrl-0 = <&vin4_pins_cvbs>;
+ pinctrl-0 = <&vin4_pins>;
pinctrl-names = "default";
status = "okay";
@@ -737,7 +738,10 @@
ports {
port {
vin4_in: endpoint {
- remote-endpoint = <&adv7180_out>;
+ pclk-sample = <0>;
+ hsync-active = <0>;
+ vsync-active = <0>;
+ remote-endpoint = <&adv7612_out>;
};
};
};
diff --git a/dts/upstream/src/arm64/renesas/ebisu.dtsi b/dts/upstream/src/arm64/renesas/ebisu.dtsi
index f1a5778..cba2fde 100644
--- a/dts/upstream/src/arm64/renesas/ebisu.dtsi
+++ b/dts/upstream/src/arm64/renesas/ebisu.dtsi
@@ -403,6 +403,12 @@
interrupt-parent = <&gpio1>;
interrupts = <1 IRQ_TYPE_LEVEL_LOW>;
+ avdd-supply = <®_1p8v>;
+ dvdd-supply = <®_1p8v>;
+ pvdd-supply = <®_1p8v>;
+ dvdd-3v-supply = <®_3p3v>;
+ bgvdd-supply = <®_1p8v>;
+
adi,input-depth = <8>;
adi,input-colorspace = "rgb";
adi,input-clock = "1x";
diff --git a/dts/upstream/src/arm64/renesas/r8a77970-eagle.dts b/dts/upstream/src/arm64/renesas/r8a77970-eagle.dts
index 405404c..0608dce 100644
--- a/dts/upstream/src/arm64/renesas/r8a77970-eagle.dts
+++ b/dts/upstream/src/arm64/renesas/r8a77970-eagle.dts
@@ -29,6 +29,15 @@
stdout-path = "serial0:115200n8";
};
+ d1p8: regulator-fixed {
+ compatible = "regulator-fixed";
+ regulator-name = "fixed-1.8V";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-boot-on;
+ regulator-always-on;
+ };
+
d3p3: regulator-fixed {
compatible = "regulator-fixed";
regulator-name = "fixed-3.3V";
@@ -166,6 +175,12 @@
interrupt-parent = <&gpio1>;
interrupts = <20 IRQ_TYPE_LEVEL_LOW>;
+ avdd-supply = <&d1p8>;
+ dvdd-supply = <&d1p8>;
+ pvdd-supply = <&d1p8>;
+ dvdd-3v-supply = <&d3p3>;
+ bgvdd-supply = <&d1p8>;
+
adi,input-depth = <8>;
adi,input-colorspace = "rgb";
adi,input-clock = "1x";
diff --git a/dts/upstream/src/arm64/renesas/r8a779g0-white-hawk-cpu.dtsi b/dts/upstream/src/arm64/renesas/r8a779g0-white-hawk-cpu.dtsi
index bb4a527..913f70f 100644
--- a/dts/upstream/src/arm64/renesas/r8a779g0-white-hawk-cpu.dtsi
+++ b/dts/upstream/src/arm64/renesas/r8a779g0-white-hawk-cpu.dtsi
@@ -187,6 +187,9 @@
};
&hscif0 {
+ pinctrl-0 = <&hscif0_pins>;
+ pinctrl-names = "default";
+
status = "okay";
};
diff --git a/dts/upstream/src/arm64/renesas/r9a08g045.dtsi b/dts/upstream/src/arm64/renesas/r9a08g045.dtsi
index 6c7b29b..5facfad 100644
--- a/dts/upstream/src/arm64/renesas/r9a08g045.dtsi
+++ b/dts/upstream/src/arm64/renesas/r9a08g045.dtsi
@@ -96,6 +96,7 @@
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
+ interrupt-parent = <&irqc>;
gpio-ranges = <&pinctrl 0 0 152>;
clocks = <&cpg CPG_MOD R9A08G045_GPIO_HCLK>;
power-domains = <&cpg>;
@@ -104,6 +105,73 @@
<&cpg R9A08G045_GPIO_SPARE_RESETN>;
};
+ irqc: interrupt-controller@11050000 {
+ compatible = "renesas,r9a08g045-irqc", "renesas,rzg2l-irqc";
+ #interrupt-cells = <2>;
+ #address-cells = <0>;
+ interrupt-controller;
+ reg = <0 0x11050000 0 0x10000>;
+ interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 429 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 430 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 431 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 432 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 433 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 434 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 435 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 436 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 437 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 438 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 439 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 440 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 441 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 442 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 443 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 444 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 445 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 446 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 447 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 448 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 449 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 450 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 451 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 452 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 453 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 454 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 455 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 456 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 457 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 458 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 459 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 460 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "nmi",
+ "irq0", "irq1", "irq2", "irq3",
+ "irq4", "irq5", "irq6", "irq7",
+ "tint0", "tint1", "tint2", "tint3",
+ "tint4", "tint5", "tint6", "tint7",
+ "tint8", "tint9", "tint10", "tint11",
+ "tint12", "tint13", "tint14", "tint15",
+ "tint16", "tint17", "tint18", "tint19",
+ "tint20", "tint21", "tint22", "tint23",
+ "tint24", "tint25", "tint26", "tint27",
+ "tint28", "tint29", "tint30", "tint31",
+ "bus-err";
+ clocks = <&cpg CPG_MOD R9A08G045_IA55_CLK>,
+ <&cpg CPG_MOD R9A08G045_IA55_PCLK>;
+ clock-names = "clk", "pclk";
+ power-domains = <&cpg>;
+ resets = <&cpg R9A08G045_IA55_RESETN>;
+ };
+
sdhi0: mmc@11c00000 {
compatible = "renesas,sdhi-r9a08g045", "renesas,rcar-gen3-sdhi";
reg = <0x0 0x11c00000 0 0x10000>;
@@ -146,6 +214,44 @@
clock-names = "core", "clkh", "cd", "aclk";
resets = <&cpg R9A08G045_SDHI2_IXRST>;
power-domains = <&cpg>;
+ status = "disabled";
+ };
+
+ eth0: ethernet@11c30000 {
+ compatible = "renesas,r9a08g045-gbeth", "renesas,rzg2l-gbeth";
+ reg = <0 0x11c30000 0 0x10000>;
+ interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "mux", "fil", "arp_ns";
+ phy-mode = "rgmii";
+ clocks = <&cpg CPG_MOD R9A08G045_ETH0_CLK_AXI>,
+ <&cpg CPG_MOD R9A08G045_ETH0_CLK_CHI>,
+ <&cpg CPG_MOD R9A08G045_ETH0_REFCLK>;
+ clock-names = "axi", "chi", "refclk";
+ resets = <&cpg R9A08G045_ETH0_RST_HW_N>;
+ power-domains = <&cpg>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+ };
+
+ eth1: ethernet@11c40000 {
+ compatible = "renesas,r9a08g045-gbeth", "renesas,rzg2l-gbeth";
+ reg = <0 0x11c40000 0 0x10000>;
+ interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "mux", "fil", "arp_ns";
+ phy-mode = "rgmii";
+ clocks = <&cpg CPG_MOD R9A08G045_ETH1_CLK_AXI>,
+ <&cpg CPG_MOD R9A08G045_ETH1_CLK_CHI>,
+ <&cpg CPG_MOD R9A08G045_ETH1_REFCLK>;
+ clock-names = "axi", "chi", "refclk";
+ resets = <&cpg R9A08G045_ETH1_RST_HW_N>;
+ power-domains = <&cpg>;
+ #address-cells = <1>;
+ #size-cells = <0>;
status = "disabled";
};
diff --git a/dts/upstream/src/arm64/renesas/r9a09g011.dtsi b/dts/upstream/src/arm64/renesas/r9a09g011.dtsi
index 33f2ecf..50ed66d 100644
--- a/dts/upstream/src/arm64/renesas/r9a09g011.dtsi
+++ b/dts/upstream/src/arm64/renesas/r9a09g011.dtsi
@@ -163,7 +163,7 @@
};
avb: ethernet@a3300000 {
- compatible = "renesas,etheravb-r9a09g011","renesas,etheravb-rzv2m";
+ compatible = "renesas,etheravb-r9a09g011", "renesas,etheravb-rzv2m";
reg = <0 0xa3300000 0 0x800>;
interrupts = <GIC_SPI 251 IRQ_TYPE_LEVEL_HIGH>, /* ch0: Rx0 BE */
<GIC_SPI 252 IRQ_TYPE_LEVEL_HIGH>, /* ch1: Rx1 NC */
diff --git a/dts/upstream/src/arm64/renesas/rzg2l-smarc-som.dtsi b/dts/upstream/src/arm64/renesas/rzg2l-smarc-som.dtsi
index 547859c..4409c47 100644
--- a/dts/upstream/src/arm64/renesas/rzg2l-smarc-som.dtsi
+++ b/dts/upstream/src/arm64/renesas/rzg2l-smarc-som.dtsi
@@ -312,6 +312,7 @@
m25p,fast-read;
spi-max-frequency = <50000000>;
spi-rx-bus-width = <4>;
+ spi-tx-bus-width = <4>;
partitions {
compatible = "fixed-partitions";
diff --git a/dts/upstream/src/arm64/renesas/rzg2lc-smarc-som.dtsi b/dts/upstream/src/arm64/renesas/rzg2lc-smarc-som.dtsi
index 56ff924..5e4209d 100644
--- a/dts/upstream/src/arm64/renesas/rzg2lc-smarc-som.dtsi
+++ b/dts/upstream/src/arm64/renesas/rzg2lc-smarc-som.dtsi
@@ -241,6 +241,7 @@
m25p,fast-read;
spi-max-frequency = <50000000>;
spi-rx-bus-width = <4>;
+ spi-tx-bus-width = <4>;
partitions {
compatible = "fixed-partitions";
diff --git a/dts/upstream/src/arm64/renesas/rzg3s-smarc-som.dtsi b/dts/upstream/src/arm64/renesas/rzg3s-smarc-som.dtsi
index a199de8..f062d4a 100644
--- a/dts/upstream/src/arm64/renesas/rzg3s-smarc-som.dtsi
+++ b/dts/upstream/src/arm64/renesas/rzg3s-smarc-som.dtsi
@@ -9,18 +9,36 @@
#include <dt-bindings/pinctrl/rzg2l-pinctrl.h>
/*
- * Signals of SW_CONFIG switches:
- * @SW_SD0_DEV_SEL:
- * 0 - SD0 is connected to eMMC
- * 1 - SD0 is connected to uSD0 card
+ * On-board switches' states:
+ * @SW_OFF: switch's state is OFF
+ * @SW_ON: switch's state is ON
*/
-#define SW_SD0_DEV_SEL 1
+#define SW_OFF 0
+#define SW_ON 1
+
+/*
+ * SW_CONFIG[x] switches' states:
+ * @SW_CONFIG2:
+ * SW_OFF - SD0 is connected to eMMC
+ * SW_ON - SD0 is connected to uSD0 card
+ * @SW_CONFIG3:
+ * SW_OFF - SD2 is connected to SoC
+ * SW_ON - SCIF1, SSI0, IRQ0, IRQ1 connected to SoC
+ */
+#define SW_CONFIG2 SW_ON
+#define SW_CONFIG3 SW_ON
/ {
compatible = "renesas,rzg3s-smarcm", "renesas,r9a08g045s33", "renesas,r9a08g045";
aliases {
mmc0 = &sdhi0;
+#if SW_CONFIG3 == SW_OFF
+ mmc2 = &sdhi2;
+#else
+ eth0 = ð0;
+ eth1 = ð1;
+#endif
};
chosen {
@@ -43,7 +61,7 @@
enable-active-high;
};
-#if SW_SD0_DEV_SEL
+#if SW_CONFIG2 == SW_ON
vccq_sdhi0: regulator1 {
compatible = "regulator-gpio";
regulator-name = "SDHI0 VccQ";
@@ -63,13 +81,76 @@
regulator-always-on;
};
#endif
+
+ vcc_sdhi2: regulator2 {
+ compatible = "regulator-fixed";
+ regulator-name = "SDHI2 Vcc";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ gpios = <&pinctrl RZG2L_GPIO(8, 1) GPIO_ACTIVE_HIGH>;
+ enable-active-high;
+ };
+};
+
+#if SW_CONFIG3 == SW_ON
+ð0 {
+ pinctrl-0 = <ð0_pins>;
+ pinctrl-names = "default";
+ phy-handle = <&phy0>;
+ phy-mode = "rgmii-id";
+ status = "okay";
+
+ phy0: ethernet-phy@7 {
+ reg = <7>;
+ interrupt-parent = <&pinctrl>;
+ interrupts = <RZG2L_GPIO(12, 0) IRQ_TYPE_EDGE_FALLING>;
+ rxc-skew-psec = <0>;
+ txc-skew-psec = <0>;
+ rxdv-skew-psec = <0>;
+ txen-skew-psec = <0>;
+ rxd0-skew-psec = <0>;
+ rxd1-skew-psec = <0>;
+ rxd2-skew-psec = <0>;
+ rxd3-skew-psec = <0>;
+ txd0-skew-psec = <0>;
+ txd1-skew-psec = <0>;
+ txd2-skew-psec = <0>;
+ txd3-skew-psec = <0>;
+ };
};
+ð1 {
+ pinctrl-0 = <ð1_pins>;
+ pinctrl-names = "default";
+ phy-handle = <&phy1>;
+ phy-mode = "rgmii-id";
+ status = "okay";
+
+ phy1: ethernet-phy@7 {
+ reg = <7>;
+ interrupt-parent = <&pinctrl>;
+ interrupts = <RZG2L_GPIO(12, 1) IRQ_TYPE_EDGE_FALLING>;
+ rxc-skew-psec = <0>;
+ txc-skew-psec = <0>;
+ rxdv-skew-psec = <0>;
+ txen-skew-psec = <0>;
+ rxd0-skew-psec = <0>;
+ rxd1-skew-psec = <0>;
+ rxd2-skew-psec = <0>;
+ rxd3-skew-psec = <0>;
+ txd0-skew-psec = <0>;
+ txd1-skew-psec = <0>;
+ txd2-skew-psec = <0>;
+ txd3-skew-psec = <0>;
+ };
+};
+#endif
+
&extal_clk {
clock-frequency = <24000000>;
};
-#if SW_SD0_DEV_SEL
+#if SW_CONFIG2 == SW_ON
/* SD0 slot */
&sdhi0 {
pinctrl-0 = <&sdhi0_pins>;
@@ -100,7 +181,100 @@
};
#endif
+#if SW_CONFIG3 == SW_OFF
+&sdhi2 {
+ pinctrl-0 = <&sdhi2_pins>;
+ pinctrl-names = "default";
+ vmmc-supply = <&vcc_sdhi2>;
+ bus-width = <4>;
+ max-frequency = <50000000>;
+ status = "okay";
+};
+#endif
+
&pinctrl {
+ eth0-phy-irq-hog {
+ gpio-hog;
+ gpios = <RZG2L_GPIO(12, 0) GPIO_ACTIVE_LOW>;
+ input;
+ line-name = "eth0-phy-irq";
+ };
+
+ eth0_pins: eth0 {
+ txc {
+ pinmux = <RZG2L_PORT_PINMUX(1, 0, 1)>; /* ET0_TXC */
+ power-source = <1800>;
+ output-enable;
+ input-enable;
+ drive-strength-microamp = <5200>;
+ };
+
+ tx_ctl {
+ pinmux = <RZG2L_PORT_PINMUX(1, 1, 1)>; /* ET0_TX_CTL */
+ power-source = <1800>;
+ output-enable;
+ drive-strength-microamp = <5200>;
+ };
+
+ mux {
+ pinmux = <RZG2L_PORT_PINMUX(1, 2, 1)>, /* ET0_TXD0 */
+ <RZG2L_PORT_PINMUX(1, 3, 1)>, /* ET0_TXD1 */
+ <RZG2L_PORT_PINMUX(1, 4, 1)>, /* ET0_TXD2 */
+ <RZG2L_PORT_PINMUX(2, 0, 1)>, /* ET0_TXD3 */
+ <RZG2L_PORT_PINMUX(3, 0, 1)>, /* ET0_RXC */
+ <RZG2L_PORT_PINMUX(3, 1, 1)>, /* ET0_RX_CTL */
+ <RZG2L_PORT_PINMUX(3, 2, 1)>, /* ET0_RXD0 */
+ <RZG2L_PORT_PINMUX(3, 3, 1)>, /* ET0_RXD1 */
+ <RZG2L_PORT_PINMUX(4, 0, 1)>, /* ET0_RXD2 */
+ <RZG2L_PORT_PINMUX(4, 1, 1)>, /* ET0_RXD3 */
+ <RZG2L_PORT_PINMUX(4, 3, 1)>, /* ET0_MDC */
+ <RZG2L_PORT_PINMUX(4, 4, 1)>, /* ET0_MDIO */
+ <RZG2L_PORT_PINMUX(4, 5, 1)>; /* ET0_LINKSTA */
+ power-source = <1800>;
+ };
+ };
+
+ eth1-phy-irq-hog {
+ gpio-hog;
+ gpios = <RZG2L_GPIO(12, 1) GPIO_ACTIVE_LOW>;
+ input;
+ line-name = "eth1-phy-irq";
+ };
+
+ eth1_pins: eth1 {
+ txc {
+ pinmux = <RZG2L_PORT_PINMUX(7, 0, 1)>; /* ET1_TXC */
+ power-source = <1800>;
+ output-enable;
+ input-enable;
+ drive-strength-microamp = <5200>;
+ };
+
+ tx_ctl {
+ pinmux = <RZG2L_PORT_PINMUX(7, 1, 1)>; /* ET1_TX_CTL */
+ power-source = <1800>;
+ output-enable;
+ drive-strength-microamp = <5200>;
+ };
+
+ mux {
+ pinmux = <RZG2L_PORT_PINMUX(7, 2, 1)>, /* ET1_TXD0 */
+ <RZG2L_PORT_PINMUX(7, 3, 1)>, /* ET1_TXD1 */
+ <RZG2L_PORT_PINMUX(7, 4, 1)>, /* ET1_TXD2 */
+ <RZG2L_PORT_PINMUX(8, 0, 1)>, /* ET1_TXD3 */
+ <RZG2L_PORT_PINMUX(8, 4, 1)>, /* ET1_RXC */
+ <RZG2L_PORT_PINMUX(9, 0, 1)>, /* ET1_RX_CTL */
+ <RZG2L_PORT_PINMUX(9, 1, 1)>, /* ET1_RXD0 */
+ <RZG2L_PORT_PINMUX(9, 2, 1)>, /* ET1_RXD1 */
+ <RZG2L_PORT_PINMUX(9, 3, 1)>, /* ET1_RXD2 */
+ <RZG2L_PORT_PINMUX(10, 0, 1)>, /* ET1_RXD3 */
+ <RZG2L_PORT_PINMUX(10, 2, 1)>, /* ET1_MDC */
+ <RZG2L_PORT_PINMUX(10, 3, 1)>, /* ET1_MDIO */
+ <RZG2L_PORT_PINMUX(10, 4, 1)>; /* ET1_LINKSTA */
+ power-source = <1800>;
+ };
+ };
+
sdhi0_pins: sd0 {
data {
pins = "SD0_DATA0", "SD0_DATA1", "SD0_DATA2", "SD0_DATA3";
@@ -139,4 +313,26 @@
"SD0_CLK", "SD0_CMD", "SD0_RST#";
power-source = <1800>;
};
+
+ sdhi2_pins: sd2 {
+ data {
+ pins = "P11_2", "P11_3", "P12_0", "P12_1";
+ input-enable;
+ };
+
+ ctrl {
+ pins = "P11_1";
+ input-enable;
+ };
+
+ mux {
+ pinmux = <RZG2L_PORT_PINMUX(11, 0, 8)>, /* SD2_CLK */
+ <RZG2L_PORT_PINMUX(11, 1, 8)>, /* SD2_CMD */
+ <RZG2L_PORT_PINMUX(11, 2, 8)>, /* SD2_DATA0 */
+ <RZG2L_PORT_PINMUX(11, 3, 8)>, /* SD2_DATA1 */
+ <RZG2L_PORT_PINMUX(12, 0, 8)>, /* SD2_DATA2 */
+ <RZG2L_PORT_PINMUX(12, 1, 8)>, /* SD2_DATA3 */
+ <RZG2L_PORT_PINMUX(14, 1, 7)>; /* SD2_CD# */
+ };
+ };
};
diff --git a/dts/upstream/src/arm64/renesas/rzg3s-smarc.dtsi b/dts/upstream/src/arm64/renesas/rzg3s-smarc.dtsi
index e7073a0..2145201 100644
--- a/dts/upstream/src/arm64/renesas/rzg3s-smarc.dtsi
+++ b/dts/upstream/src/arm64/renesas/rzg3s-smarc.dtsi
@@ -11,6 +11,26 @@
/ {
aliases {
serial0 = &scif0;
+ mmc1 = &sdhi1;
+ };
+
+ vcc_sdhi1: regulator-vcc-sdhi1 {
+ compatible = "regulator-fixed";
+ regulator-name = "SDHI1 Vcc";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ gpios = <&pinctrl RZG2L_GPIO(2, 3) GPIO_ACTIVE_HIGH>;
+ enable-active-high;
+ };
+
+ vccq_sdhi1: regulator-vccq-sdhi1 {
+ compatible = "regulator-gpio";
+ regulator-name = "SDHI1 VccQ";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <3300000>;
+ gpios = <&pinctrl RZG2L_GPIO(4, 2) GPIO_ACTIVE_HIGH>;
+ gpios-states = <1>;
+ states = <3300000 1>, <1800000 0>;
};
};
@@ -19,6 +39,38 @@
pinmux = <RZG2L_PORT_PINMUX(6, 3, 1)>, /* RXD */
<RZG2L_PORT_PINMUX(6, 4, 1)>; /* TXD */
};
+
+ sdhi1_pins: sd1 {
+ data {
+ pins = "SD1_DATA0", "SD1_DATA1", "SD1_DATA2", "SD1_DATA3";
+ power-source = <3300>;
+ };
+
+ ctrl {
+ pins = "SD1_CLK", "SD1_CMD";
+ power-source = <3300>;
+ };
+
+ cd {
+ pinmux = <RZG2L_PORT_PINMUX(0, 2, 1)>; /* SD1_CD */
+ };
+ };
+
+ sdhi1_pins_uhs: sd1-uhs {
+ data {
+ pins = "SD1_DATA0", "SD1_DATA1", "SD1_DATA2", "SD1_DATA3";
+ power-source = <1800>;
+ };
+
+ ctrl {
+ pins = "SD1_CLK", "SD1_CMD";
+ power-source = <1800>;
+ };
+
+ cd {
+ pinmux = <RZG2L_PORT_PINMUX(0, 2, 1)>; /* SD1_CD */
+ };
+ };
};
&scif0 {
@@ -26,3 +78,16 @@
pinctrl-0 = <&scif0_pins>;
status = "okay";
};
+
+&sdhi1 {
+ pinctrl-0 = <&sdhi1_pins>;
+ pinctrl-1 = <&sdhi1_pins_uhs>;
+ pinctrl-names = "default", "state_uhs";
+ vmmc-supply = <&vcc_sdhi1>;
+ vqmmc-supply = <&vccq_sdhi1>;
+ bus-width = <4>;
+ sd-uhs-sdr50;
+ sd-uhs-sdr104;
+ max-frequency = <125000000>;
+ status = "okay";
+};
diff --git a/dts/upstream/src/arm64/renesas/ulcb-kf.dtsi b/dts/upstream/src/arm64/renesas/ulcb-kf.dtsi
index 3885ef3..50de17e 100644
--- a/dts/upstream/src/arm64/renesas/ulcb-kf.dtsi
+++ b/dts/upstream/src/arm64/renesas/ulcb-kf.dtsi
@@ -234,6 +234,7 @@
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
+ #interrupt-cells = <2>;
interrupt-parent = <&gpio6>;
interrupts = <8 IRQ_TYPE_EDGE_FALLING>;
@@ -294,6 +295,7 @@
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
+ #interrupt-cells = <2>;
interrupt-parent = <&gpio6>;
interrupts = <4 IRQ_TYPE_EDGE_FALLING>;
};
@@ -314,6 +316,7 @@
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
+ #interrupt-cells = <2>;
interrupt-parent = <&gpio7>;
interrupts = <3 IRQ_TYPE_EDGE_FALLING>;
};
@@ -324,6 +327,7 @@
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
+ #interrupt-cells = <2>;
interrupt-parent = <&gpio5>;
interrupts = <9 IRQ_TYPE_EDGE_FALLING>;
};
diff --git a/dts/upstream/src/arm64/rockchip/px30-engicam-common.dtsi b/dts/upstream/src/arm64/rockchip/px30-engicam-common.dtsi
index 3429e12..5b4e223 100644
--- a/dts/upstream/src/arm64/rockchip/px30-engicam-common.dtsi
+++ b/dts/upstream/src/arm64/rockchip/px30-engicam-common.dtsi
@@ -7,6 +7,7 @@
/ {
aliases {
+ ethernet0 = &gmac;
mmc1 = &sdmmc;
mmc2 = &sdio;
};
diff --git a/dts/upstream/src/arm64/rockchip/px30-evb.dts b/dts/upstream/src/arm64/rockchip/px30-evb.dts
index c1bbd55..0a90a88 100644
--- a/dts/upstream/src/arm64/rockchip/px30-evb.dts
+++ b/dts/upstream/src/arm64/rockchip/px30-evb.dts
@@ -14,6 +14,7 @@
compatible = "rockchip,px30-evb", "rockchip,px30";
aliases {
+ ethernet0 = &gmac;
mmc0 = &sdmmc;
mmc1 = &sdio;
mmc2 = &emmc;
diff --git a/dts/upstream/src/arm64/rockchip/px30-ringneck-haikou.dts b/dts/upstream/src/arm64/rockchip/px30-ringneck-haikou.dts
index 7d4c532..16798eb 100644
--- a/dts/upstream/src/arm64/rockchip/px30-ringneck-haikou.dts
+++ b/dts/upstream/src/arm64/rockchip/px30-ringneck-haikou.dts
@@ -13,6 +13,7 @@
compatible = "tsd,px30-ringneck-haikou", "rockchip,px30";
aliases {
+ ethernet0 = &gmac;
mmc2 = &sdmmc;
};
diff --git a/dts/upstream/src/arm64/rockchip/px30.dtsi b/dts/upstream/src/arm64/rockchip/px30.dtsi
index 42ce78b..9137dd7 100644
--- a/dts/upstream/src/arm64/rockchip/px30.dtsi
+++ b/dts/upstream/src/arm64/rockchip/px30.dtsi
@@ -20,7 +20,6 @@
#size-cells = <2>;
aliases {
- ethernet0 = &gmac;
i2c0 = &i2c0;
i2c1 = &i2c1;
i2c2 = &i2c2;
@@ -632,6 +631,7 @@
clock-names = "spiclk", "apb_pclk";
dmas = <&dmac 12>, <&dmac 13>;
dma-names = "tx", "rx";
+ num-cs = <2>;
pinctrl-names = "default";
pinctrl-0 = <&spi0_clk &spi0_csn &spi0_miso &spi0_mosi>;
#address-cells = <1>;
@@ -647,6 +647,7 @@
clock-names = "spiclk", "apb_pclk";
dmas = <&dmac 14>, <&dmac 15>;
dma-names = "tx", "rx";
+ num-cs = <2>;
pinctrl-names = "default";
pinctrl-0 = <&spi1_clk &spi1_csn0 &spi1_csn1 &spi1_miso &spi1_mosi>;
#address-cells = <1>;
diff --git a/dts/upstream/src/arm64/rockchip/rk3308-rock-pi-s.dts b/dts/upstream/src/arm64/rockchip/rk3308-rock-pi-s.dts
index e9810d2..b47fe02 100644
--- a/dts/upstream/src/arm64/rockchip/rk3308-rock-pi-s.dts
+++ b/dts/upstream/src/arm64/rockchip/rk3308-rock-pi-s.dts
@@ -143,6 +143,68 @@
status = "okay";
};
+&gpio0 {
+ gpio-line-names =
+ /* GPIO0_A0 - A7 */
+ "", "", "", "", "", "", "", "",
+ /* GPIO0_B0 - B7 */
+ "", "", "", "header1-pin3 [GPIO0_B3]",
+ "header1-pin5 [GPIO0_B4]", "", "",
+ "header1-pin11 [GPIO0_B7]",
+ /* GPIO0_C0 - C7 */
+ "header1-pin13 [GPIO0_C0]",
+ "header1-pin15 [GPIO0_C1]", "", "", "",
+ "", "", "",
+ /* GPIO0_D0 - D7 */
+ "", "", "", "", "", "", "", "";
+};
+
+&gpio1 {
+ gpio-line-names =
+ /* GPIO1_A0 - A7 */
+ "", "", "", "", "", "", "", "",
+ /* GPIO1_B0 - B7 */
+ "", "", "", "", "", "", "", "",
+ /* GPIO1_C0 - C7 */
+ "", "", "", "", "", "", "header1-pin21 [GPIO1_C6]",
+ "header1-pin19 [GPIO1_C7]",
+ /* GPIO1_D0 - D7 */
+ "header1-pin23 [GPIO1_D0]", "header1-pin24 [GPIO1_D1]",
+ "", "", "", "", "", "";
+};
+
+&gpio2 {
+ gpio-line-names =
+ /* GPIO2_A0 - A7 */
+ "header1-pin10 [GPIO2_A0]", "header1-pin8 [GPIO2_A1]",
+ "", "",
+ "header1-pin7 [GPIO2_A4]", "header1-pin12 [GPIO2_A5]",
+ "header2-pin46 [GPIO2_A6]", "header1-pin22 [GPIO1_A7]",
+ /* GPIO2_B0 - B7 */
+ "header2-pin45 [GPIO2_B0]", "header1-pin18 [GPIO2_B1]",
+ "header1-pin16 [GPIO2_B2]", "header2-pin44 [GPIO2_B3]",
+ "header2-pin43 [GPIO2_B4]", "header2-pin28 [GPIO2_B5]",
+ "header2-pin30 [GPIO2_B6]", "header2-pin32 [GPIO2_B7]",
+ /* GPIO2_C0 - C7 */
+ "header2-pin34 [GPIO2_C0]", "", "", "", "", "", "", "",
+ /* GPIO2_D0 - D7 */
+ "", "", "", "", "", "", "", "";
+};
+
+&gpio3 {
+ gpio-line-names =
+ /* GPIO3_A0 - A7 */
+ "", "", "", "", "", "", "", "",
+ /* GPIO3_B0 - B7 */
+ "", "", "header2-pin42 [GPIO3_B2]",
+ "header2-pin41 [GPIO3_B3]", "header2-pin40 [GPIO3_B4]",
+ "header2-pin39 [GPIO3_B5]", "", "",
+ /* GPIO3_C0 - C7 */
+ "", "", "", "", "", "", "", "",
+ /* GPIO3_D0 - D7 */
+ "", "", "", "", "", "", "", "";
+};
+
&i2c1 {
status = "okay";
};
diff --git a/dts/upstream/src/arm64/rockchip/rk3308.dtsi b/dts/upstream/src/arm64/rockchip/rk3308.dtsi
index 2ae4bb7..cfc0a87 100644
--- a/dts/upstream/src/arm64/rockchip/rk3308.dtsi
+++ b/dts/upstream/src/arm64/rockchip/rk3308.dtsi
@@ -20,6 +20,11 @@
#size-cells = <2>;
aliases {
+ gpio0 = &gpio0;
+ gpio1 = &gpio1;
+ gpio2 = &gpio2;
+ gpio3 = &gpio3;
+ gpio4 = &gpio4;
i2c0 = &i2c0;
i2c1 = &i2c1;
i2c2 = &i2c2;
diff --git a/dts/upstream/src/arm64/rockchip/rk3318-a95x-z2.dts b/dts/upstream/src/arm64/rockchip/rk3318-a95x-z2.dts
index 1deef53..c7b1862 100644
--- a/dts/upstream/src/arm64/rockchip/rk3318-a95x-z2.dts
+++ b/dts/upstream/src/arm64/rockchip/rk3318-a95x-z2.dts
@@ -9,6 +9,7 @@
compatible = "zkmagic,a95x-z2", "rockchip,rk3318";
aliases {
+ ethernet0 = &gmac2phy;
mmc0 = &sdmmc;
mmc1 = &sdio;
mmc2 = &emmc;
diff --git a/dts/upstream/src/arm64/rockchip/rk3326-anbernic-rg351m.dts b/dts/upstream/src/arm64/rockchip/rk3326-anbernic-rg351m.dts
index ce318e0..f4d20f2 100644
--- a/dts/upstream/src/arm64/rockchip/rk3326-anbernic-rg351m.dts
+++ b/dts/upstream/src/arm64/rockchip/rk3326-anbernic-rg351m.dts
@@ -6,30 +6,16 @@
*/
/dts-v1/;
-#include "rk3326-odroid-go.dtsi"
+#include "rk3326-anbernic-rg351m.dtsi"
/ {
model = "Anbernic RG351M";
compatible = "anbernic,rg351m", "rockchip,rk3326";
-
- vibrator {
- compatible = "pwm-vibrator";
- pwms = <&pwm0 0 1000000 0>;
- pwm-names = "enable";
- };
};
-/delete-node/ &builtin_gamepad;
-/delete-node/ &vcc_host; /* conflicts with pwm vibration motor */
-
&internal_display {
compatible = "elida,kd35t133";
iovcc-supply = <&vcc_lcd>;
+ rotation = <270>;
vdd-supply = <&vcc_lcd>;
};
-
-&pwm0 {
- status = "okay";
-};
-
-/delete-node/ &rk817_charger;
diff --git a/dts/upstream/src/arm64/rockchip/rk3326-anbernic-rg351m.dtsi b/dts/upstream/src/arm64/rockchip/rk3326-anbernic-rg351m.dtsi
new file mode 100644
index 0000000..b6d041d
--- /dev/null
+++ b/dts/upstream/src/arm64/rockchip/rk3326-anbernic-rg351m.dtsi
@@ -0,0 +1,478 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (c) 2019 Hardkernel Co., Ltd
+ * Copyright (c) 2020 Theobroma Systems Design und Consulting GmbH
+ * Copyright (c) 2022 Maya Matuszczyk <maccraft123mc@gmail.com>
+ */
+
+/dts-v1/;
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/input/input.h>
+#include <dt-bindings/leds/common.h>
+#include <dt-bindings/pinctrl/rockchip.h>
+#include "rk3326.dtsi"
+
+/ {
+ aliases {
+ mmc0 = &sdmmc;
+ };
+
+ chosen {
+ stdout-path = "serial2:115200n8";
+ };
+
+ backlight: backlight {
+ compatible = "pwm-backlight";
+ power-supply = <&vcc_bl>;
+ pwms = <&pwm1 0 25000 0>;
+ };
+
+ /*
+ * LED is a tri-state. Driven high it is red, driven low it is
+ * green, and not driven at all (pin set to input) it is amber.
+ * Additionally, there is a 2nd LED that is not controllable
+ * that is on (red) when plugged in to power.
+ */
+ gpio_led: gpio-leds {
+ compatible = "gpio-leds";
+ pinctrl-names = "default";
+ pinctrl-0 = <&led_pin>;
+
+ red_green_led: led-0 {
+ color = <LED_COLOR_ID_RED>;
+ gpios = <&gpio2 RK_PB5 GPIO_ACTIVE_HIGH>;
+ function = LED_FUNCTION_CHARGING;
+ };
+ };
+
+ rk817-sound {
+ compatible = "simple-audio-card";
+ simple-audio-card,name = "rk817_int";
+ simple-audio-card,format = "i2s";
+ simple-audio-card,hp-det-gpio = <&gpio2 RK_PC6 GPIO_ACTIVE_HIGH>;
+ simple-audio-card,mclk-fs = <256>;
+ simple-audio-card,widgets =
+ "Microphone", "Mic Jack",
+ "Headphone", "Headphones",
+ "Speaker", "Speaker";
+ simple-audio-card,routing =
+ "MICL", "Mic Jack",
+ "Headphones", "HPOL",
+ "Headphones", "HPOR",
+ "Speaker", "SPKO";
+
+ simple-audio-card,codec {
+ sound-dai = <&rk817>;
+ };
+
+ simple-audio-card,cpu {
+ sound-dai = <&i2s1_2ch>;
+ };
+ };
+
+ vccsys: vccsys {
+ compatible = "regulator-fixed";
+ regulator-name = "vcc3v8_sys";
+ regulator-always-on;
+ regulator-min-microvolt = <3800000>;
+ regulator-max-microvolt = <3800000>;
+ };
+
+ vibrator {
+ compatible = "pwm-vibrator";
+ pwms = <&pwm0 0 1000000 0>;
+ pwm-names = "enable";
+ };
+};
+
+&cpu0 {
+ cpu-supply = <&vdd_arm>;
+};
+
+&cpu1 {
+ cpu-supply = <&vdd_arm>;
+};
+
+&cpu2 {
+ cpu-supply = <&vdd_arm>;
+};
+
+&cpu3 {
+ cpu-supply = <&vdd_arm>;
+};
+
+&cru {
+ assigned-clocks = <&cru PLL_NPLL>,
+ <&cru ACLK_BUS_PRE>, <&cru ACLK_PERI_PRE>,
+ <&cru HCLK_BUS_PRE>, <&cru HCLK_PERI_PRE>,
+ <&cru PCLK_BUS_PRE>, <&cru SCLK_GPU>;
+
+ assigned-clock-rates = <1188000000>,
+ <200000000>, <200000000>,
+ <150000000>, <150000000>,
+ <100000000>, <200000000>;
+};
+
+&display_subsystem {
+ status = "okay";
+};
+
+&dsi {
+ status = "okay";
+
+ ports {
+ mipi_out: port@1 {
+ reg = <1>;
+
+ mipi_out_panel: endpoint {
+ remote-endpoint = <&mipi_in_panel>;
+ };
+ };
+ };
+
+ internal_display: panel@0 {
+ reg = <0>;
+ backlight = <&backlight>;
+ reset-gpios = <&gpio3 RK_PC0 GPIO_ACTIVE_LOW>;
+
+ port {
+ mipi_in_panel: endpoint {
+ remote-endpoint = <&mipi_out_panel>;
+ };
+ };
+ };
+};
+
+&dsi_dphy {
+ status = "okay";
+};
+
+&gpu {
+ mali-supply = <&vdd_logic>;
+ status = "okay";
+};
+
+&i2c0 {
+ clock-frequency = <400000>;
+ i2c-scl-falling-time-ns = <16>;
+ i2c-scl-rising-time-ns = <280>;
+ status = "okay";
+
+ rk817: pmic@20 {
+ compatible = "rockchip,rk817";
+ reg = <0x20>;
+ #clock-cells = <1>;
+ clock-names = "mclk";
+ clock-output-names = "rk808-clkout1", "xin32k";
+ clocks = <&cru SCLK_I2S1_OUT>;
+ interrupt-parent = <&gpio0>;
+ interrupts = <RK_PB2 IRQ_TYPE_LEVEL_LOW>;
+ pinctrl-0 = <&pmic_int>, <&i2s1_2ch_mclk>;
+ pinctrl-names = "default";
+ #sound-dai-cells = <0>;
+ wakeup-source;
+
+ vcc1-supply = <&vccsys>;
+ vcc2-supply = <&vccsys>;
+ vcc3-supply = <&vccsys>;
+ vcc4-supply = <&vccsys>;
+ vcc5-supply = <&vccsys>;
+ vcc6-supply = <&vccsys>;
+ vcc7-supply = <&vccsys>;
+ vcc8-supply = <&vccsys>;
+
+ regulators {
+ vdd_logic: DCDC_REG1 {
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-max-microvolt = <1150000>;
+ regulator-min-microvolt = <950000>;
+ regulator-name = "vdd_logic";
+ regulator-ramp-delay = <6001>;
+
+ regulator-state-mem {
+ regulator-on-in-suspend;
+ regulator-suspend-microvolt = <950000>;
+ };
+ };
+
+ vdd_arm: DCDC_REG2 {
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-max-microvolt = <1350000>;
+ regulator-min-microvolt = <950000>;
+ regulator-name = "vdd_arm";
+ regulator-ramp-delay = <6001>;
+
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ regulator-suspend-microvolt = <950000>;
+ };
+ };
+
+ vcc_ddr: DCDC_REG3 {
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-name = "vcc_ddr";
+
+ regulator-state-mem {
+ regulator-on-in-suspend;
+ };
+ };
+
+ vcc_3v3: DCDC_REG4 {
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-max-microvolt = <3300000>;
+ regulator-min-microvolt = <3300000>;
+ regulator-name = "vcc_3v3";
+
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ regulator-suspend-microvolt = <3300000>;
+ };
+ };
+
+ vcc_1v8: LDO_REG2 {
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-max-microvolt = <1800000>;
+ regulator-min-microvolt = <1800000>;
+ regulator-name = "vcc_1v8";
+
+ regulator-state-mem {
+ regulator-on-in-suspend;
+ regulator-suspend-microvolt = <1800000>;
+ };
+ };
+
+ vdd_1v0: LDO_REG3 {
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-max-microvolt = <1000000>;
+ regulator-min-microvolt = <1000000>;
+ regulator-name = "vdd_1v0";
+
+ regulator-state-mem {
+ regulator-on-in-suspend;
+ regulator-suspend-microvolt = <1000000>;
+ };
+ };
+
+ vcc3v3_pmu: LDO_REG4 {
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-max-microvolt = <3300000>;
+ regulator-min-microvolt = <3300000>;
+ regulator-name = "vcc3v3_pmu";
+
+ regulator-state-mem {
+ regulator-on-in-suspend;
+ regulator-suspend-microvolt = <3300000>;
+ };
+ };
+
+ vccio_sd: LDO_REG5 {
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-max-microvolt = <3300000>;
+ regulator-min-microvolt = <1800000>;
+ regulator-name = "vccio_sd";
+
+ regulator-state-mem {
+ regulator-on-in-suspend;
+ regulator-suspend-microvolt = <3300000>;
+ };
+ };
+
+ vcc_sd: LDO_REG6 {
+ regulator-boot-on;
+ regulator-max-microvolt = <3300000>;
+ regulator-min-microvolt = <3300000>;
+ regulator-name = "vcc_sd";
+
+ regulator-state-mem {
+ regulator-on-in-suspend;
+ regulator-suspend-microvolt = <3300000>;
+ };
+ };
+
+ vcc_bl: LDO_REG7 {
+ regulator-max-microvolt = <3300000>;
+ regulator-min-microvolt = <3300000>;
+ regulator-name = "vcc_bl";
+
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ regulator-suspend-microvolt = <3300000>;
+ };
+ };
+
+ vcc_lcd: LDO_REG8 {
+ regulator-max-microvolt = <2800000>;
+ regulator-min-microvolt = <2800000>;
+ regulator-name = "vcc_lcd";
+
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ regulator-suspend-microvolt = <2800000>;
+ };
+ };
+
+ vcc_wifi: LDO_REG9 {
+ regulator-max-microvolt = <3300000>;
+ regulator-min-microvolt = <3300000>;
+ regulator-name = "vcc_wifi";
+
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ regulator-suspend-microvolt = <3300000>;
+ };
+ };
+
+ usb_midu: BOOST {
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-max-microvolt = <5400000>;
+ regulator-min-microvolt = <5000000>;
+ regulator-name = "usb_midu";
+ };
+ };
+
+ rk817_codec: codec {
+ rockchip,mic-in-differential;
+ };
+ };
+};
+
+&i2s1_2ch {
+ status = "okay";
+};
+
+&io_domains {
+ vccio1-supply = <&vcc_3v3>;
+ vccio2-supply = <&vccio_sd>;
+ vccio3-supply = <&vcc_3v3>;
+ vccio4-supply = <&vcc_3v3>;
+ vccio5-supply = <&vcc_3v3>;
+ vccio6-supply = <&vcc_3v3>;
+ status = "okay";
+};
+
+&pmu_io_domains {
+ pmuio1-supply = <&vcc3v3_pmu>;
+ pmuio2-supply = <&vcc3v3_pmu>;
+ status = "okay";
+};
+
+&pwm0 {
+ status = "okay";
+};
+
+&pwm1 {
+ status = "okay";
+};
+
+&saradc {
+ vref-supply = <&vcc_1v8>;
+ status = "okay";
+};
+
+&sdmmc {
+ cap-sd-highspeed;
+ card-detect-delay = <200>;
+ cd-gpios = <&gpio0 RK_PA3 GPIO_ACTIVE_LOW>;
+ sd-uhs-sdr12;
+ sd-uhs-sdr25;
+ sd-uhs-sdr50;
+ sd-uhs-sdr104;
+ vmmc-supply = <&vcc_sd>;
+ vqmmc-supply = <&vccio_sd>;
+ status = "okay";
+};
+
+&sfc {
+ #address-cells = <1>;
+ pinctrl-0 = <&sfc_clk &sfc_cs0 &sfc_bus2>;
+ pinctrl-names = "default";
+ #size-cells = <0>;
+ status = "okay";
+
+ flash@0 {
+ compatible = "jedec,spi-nor";
+ reg = <0>;
+ spi-max-frequency = <108000000>;
+ spi-rx-bus-width = <2>;
+ spi-tx-bus-width = <1>;
+ };
+};
+
+&tsadc {
+ status = "okay";
+};
+
+&u2phy {
+ status = "okay";
+
+ u2phy_host: host-port {
+ status = "okay";
+ };
+
+ u2phy_otg: otg-port {
+ status = "disabled";
+ };
+};
+
+&usb20_otg {
+ status = "okay";
+};
+
+&uart2 {
+ pinctrl-0 = <&uart2m1_xfer>;
+ pinctrl-names = "default";
+ status = "okay";
+};
+
+&vopb {
+ status = "okay";
+};
+
+&vopb_mmu {
+ status = "okay";
+};
+
+&pinctrl {
+ headphone {
+ hp_det: hp-det {
+ rockchip,pins = <2 RK_PC6 RK_FUNC_GPIO &pcfg_pull_down>;
+ };
+ };
+
+ leds {
+ led_pin: led-pin {
+ rockchip,pins = <2 RK_PB5 RK_FUNC_GPIO &pcfg_pull_none>;
+ };
+ };
+
+ pmic {
+ dc_det: dc-det {
+ rockchip,pins = <0 RK_PB3 RK_FUNC_GPIO &pcfg_pull_none>;
+ };
+
+ pmic_int: pmic-int {
+ rockchip,pins = <0 RK_PB2 RK_FUNC_GPIO &pcfg_pull_up>;
+ };
+
+ soc_slppin_gpio: soc_slppin_gpio {
+ rockchip,pins = <0 RK_PA4 RK_FUNC_GPIO &pcfg_output_low>;
+ };
+
+ soc_slppin_rst: soc_slppin_rst {
+ rockchip,pins = <0 RK_PA4 2 &pcfg_pull_none>;
+ };
+
+ soc_slppin_slp: soc_slppin_slp {
+ rockchip,pins = <0 RK_PA4 1 &pcfg_pull_none>;
+ };
+ };
+};
diff --git a/dts/upstream/src/arm64/rockchip/rk3326-anbernic-rg351v.dts b/dts/upstream/src/arm64/rockchip/rk3326-anbernic-rg351v.dts
new file mode 100644
index 0000000..c79f7a7
--- /dev/null
+++ b/dts/upstream/src/arm64/rockchip/rk3326-anbernic-rg351v.dts
@@ -0,0 +1,44 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+
+/dts-v1/;
+#include "rk3326-anbernic-rg351m.dtsi"
+
+/ {
+ model = "Anbernic RG351V";
+ compatible = "anbernic,rg351v", "rockchip,rk3326";
+
+ gpio_keys_vol: gpio-keys-vol {
+ compatible = "gpio-keys";
+ autorepeat;
+
+ button-vol-down {
+ gpios = <&gpio2 RK_PA1 GPIO_ACTIVE_LOW>;
+ label = "VOLUMEDOWN";
+ linux,code = <KEY_VOLUMEDOWN>;
+ };
+
+ button-vol-up {
+ gpios = <&gpio2 RK_PA0 GPIO_ACTIVE_LOW>;
+ label = "VOLUMEUP";
+ linux,code = <KEY_VOLUMEUP>;
+ };
+ };
+};
+
+&internal_display {
+ compatible = "anbernic,rg351v-panel", "newvision,nv3051d";
+ vdd-supply = <&vcc_lcd>;
+};
+
+&io_domains {
+ vccio1-supply = <&vccio_sd>;
+};
+
+&vcc_sd {
+ regulator-max-microvolt = <3000000>;
+ regulator-min-microvolt = <1800000>;
+};
+
+&vccio_sd {
+ regulator-max-microvolt = <1800000>;
+};
diff --git a/dts/upstream/src/arm64/rockchip/rk3328-a1.dts b/dts/upstream/src/arm64/rockchip/rk3328-a1.dts
index 40bf808..824183e 100644
--- a/dts/upstream/src/arm64/rockchip/rk3328-a1.dts
+++ b/dts/upstream/src/arm64/rockchip/rk3328-a1.dts
@@ -9,6 +9,7 @@
compatible = "azw,beelink-a1", "rockchip,rk3328";
aliases {
+ ethernet0 = &gmac2io;
mmc0 = &sdmmc;
mmc1 = &emmc;
};
diff --git a/dts/upstream/src/arm64/rockchip/rk3328-evb.dts b/dts/upstream/src/arm64/rockchip/rk3328-evb.dts
index ff6b466..1eef550 100644
--- a/dts/upstream/src/arm64/rockchip/rk3328-evb.dts
+++ b/dts/upstream/src/arm64/rockchip/rk3328-evb.dts
@@ -11,6 +11,7 @@
compatible = "rockchip,rk3328-evb", "rockchip,rk3328";
aliases {
+ ethernet0 = &gmac2phy;
mmc0 = &sdmmc;
mmc1 = &sdio;
mmc2 = &emmc;
diff --git a/dts/upstream/src/arm64/rockchip/rk3328-nanopi-r2s.dts b/dts/upstream/src/arm64/rockchip/rk3328-nanopi-r2s.dts
index 1445b87..a4399da 100644
--- a/dts/upstream/src/arm64/rockchip/rk3328-nanopi-r2s.dts
+++ b/dts/upstream/src/arm64/rockchip/rk3328-nanopi-r2s.dts
@@ -14,6 +14,7 @@
compatible = "friendlyarm,nanopi-r2s", "rockchip,rk3328";
aliases {
+ ethernet0 = &gmac2io;
ethernet1 = &rtl8153;
mmc0 = &sdmmc;
};
diff --git a/dts/upstream/src/arm64/rockchip/rk3328-orangepi-r1-plus-lts.dts b/dts/upstream/src/arm64/rockchip/rk3328-orangepi-r1-plus-lts.dts
index 5d7d567..4237f2e 100644
--- a/dts/upstream/src/arm64/rockchip/rk3328-orangepi-r1-plus-lts.dts
+++ b/dts/upstream/src/arm64/rockchip/rk3328-orangepi-r1-plus-lts.dts
@@ -26,9 +26,11 @@
compatible = "ethernet-phy-ieee802.3-c22";
reg = <0>;
+ motorcomm,auto-sleep-disabled;
motorcomm,clk-out-frequency-hz = <125000000>;
motorcomm,keep-pll-enabled;
- motorcomm,auto-sleep-disabled;
+ motorcomm,rx-clk-drv-microamp = <5020>;
+ motorcomm,rx-data-drv-microamp = <5020>;
pinctrl-0 = <ð_phy_reset_pin>;
pinctrl-names = "default";
diff --git a/dts/upstream/src/arm64/rockchip/rk3328-orangepi-r1-plus.dts b/dts/upstream/src/arm64/rockchip/rk3328-orangepi-r1-plus.dts
index dc83d74..f206629 100644
--- a/dts/upstream/src/arm64/rockchip/rk3328-orangepi-r1-plus.dts
+++ b/dts/upstream/src/arm64/rockchip/rk3328-orangepi-r1-plus.dts
@@ -15,6 +15,7 @@
compatible = "xunlong,orangepi-r1-plus", "rockchip,rk3328";
aliases {
+ ethernet0 = &gmac2io;
ethernet1 = &rtl8153;
mmc0 = &sdmmc;
};
diff --git a/dts/upstream/src/arm64/rockchip/rk3328-roc-cc.dts b/dts/upstream/src/arm64/rockchip/rk3328-roc-cc.dts
index 5d5d957..414897a 100644
--- a/dts/upstream/src/arm64/rockchip/rk3328-roc-cc.dts
+++ b/dts/upstream/src/arm64/rockchip/rk3328-roc-cc.dts
@@ -11,6 +11,7 @@
compatible = "firefly,roc-rk3328-cc", "rockchip,rk3328";
aliases {
+ ethernet0 = &gmac2io;
mmc0 = &sdmmc;
mmc1 = &emmc;
};
diff --git a/dts/upstream/src/arm64/rockchip/rk3328-rock-pi-e.dts b/dts/upstream/src/arm64/rockchip/rk3328-rock-pi-e.dts
index 018a3a5..3cda6c6 100644
--- a/dts/upstream/src/arm64/rockchip/rk3328-rock-pi-e.dts
+++ b/dts/upstream/src/arm64/rockchip/rk3328-rock-pi-e.dts
@@ -21,6 +21,8 @@
compatible = "radxa,rockpi-e", "rockchip,rk3328";
aliases {
+ ethernet0 = &gmac2io;
+ ethernet1 = &gmac2phy;
mmc0 = &sdmmc;
mmc1 = &emmc;
};
@@ -180,6 +182,59 @@
status = "okay";
};
+&gpio0 {
+ gpio-line-names =
+ /* GPIO0_A0 - A7 */
+ "", "", "", "", "", "", "", "",
+ /* GPIO0_B0 - B7 */
+ "", "", "", "", "", "", "", "",
+ /* GPIO0_C0 - C7 */
+ "", "", "", "", "", "", "", "",
+ /* GPIO0_D0 - D7 */
+ "", "", "", "pin-15 [GPIO0_D3]", "", "", "", "";
+};
+
+&gpio1 {
+ gpio-line-names =
+ /* GPIO1_A0 - A7 */
+ "", "", "", "", "", "", "", "",
+ /* GPIO1_B0 - B7 */
+ "", "", "", "", "", "", "", "",
+ /* GPIO1_C0 - C7 */
+ "", "", "", "", "", "", "", "",
+ /* GPIO1_D0 - D7 */
+ "", "", "", "", "pin-07 [GPIO1_D4]", "", "", "";
+};
+
+&gpio2 {
+ gpio-line-names =
+ /* GPIO2_A0 - A7 */
+ "pin-08 [GPIO2_A0]", "pin-10 [GPIO2_A1]", "pin-11 [GPIO2_A2]",
+ "pin-13 [GPIO2-A3]", "pin-27 [GPIO2_A4]", "pin-28 [GPIO2_A5]",
+ "pin-33 [GPIO2_A6]", "",
+ /* GPIO2_B0 - B7 */
+ "", "", "", "", "pin-26 [GPIO2_B4]", "", "", "pin-36 [GPIO2_B7]",
+ /* GPIO2_C0 - C7 */
+ "pin-32 [GPIO2_C0]", "pin-35 [GPIO2_C1]", "pin-12 [GPIO2_C2]",
+ "pin-38 [GPIO2_C3]", "pin-29 [GPIO2_C4]", "pin-31 [GPIO2_C5]",
+ "pin-37 [GPIO2_C6]", "pin-40 [GPIO2_C7]",
+ /* GPIO2_D0 - D7 */
+ "", "", "", "", "", "", "", "";
+};
+
+&gpio3 {
+ gpio-line-names =
+ /* GPIO3_A0 - A7 */
+ "pin-23 [GPIO3_A0]", "pin-19 [GPIO3_A1]", "pin-21 [GPIO3_A2]",
+ "", "pin-03 [GPIO3_A4]", "", "pin-05 [GPIO3_A6]", "",
+ /* GPIO3_B0 - B7 */
+ "pin-24 [GPIO3_B0]", "", "", "", "", "", "", "",
+ /* GPIO3_C0 - C7 */
+ "", "", "", "", "", "", "", "",
+ /* GPIO3_D0 - D7 */
+ "", "", "", "", "", "", "", "";
+};
+
&i2c1 {
status = "okay";
diff --git a/dts/upstream/src/arm64/rockchip/rk3328-rock64.dts b/dts/upstream/src/arm64/rockchip/rk3328-rock64.dts
index 0a27fa5..229fe9d 100644
--- a/dts/upstream/src/arm64/rockchip/rk3328-rock64.dts
+++ b/dts/upstream/src/arm64/rockchip/rk3328-rock64.dts
@@ -11,6 +11,7 @@
compatible = "pine64,rock64", "rockchip,rk3328";
aliases {
+ ethernet0 = &gmac2io;
mmc0 = &sdmmc;
mmc1 = &emmc;
};
diff --git a/dts/upstream/src/arm64/rockchip/rk3328.dtsi b/dts/upstream/src/arm64/rockchip/rk3328.dtsi
index cc82097..7b4c15c 100644
--- a/dts/upstream/src/arm64/rockchip/rk3328.dtsi
+++ b/dts/upstream/src/arm64/rockchip/rk3328.dtsi
@@ -20,6 +20,10 @@
#size-cells = <2>;
aliases {
+ gpio0 = &gpio0;
+ gpio1 = &gpio1;
+ gpio2 = &gpio2;
+ gpio3 = &gpio3;
serial0 = &uart0;
serial1 = &uart1;
serial2 = &uart2;
@@ -27,8 +31,6 @@
i2c1 = &i2c1;
i2c2 = &i2c2;
i2c3 = &i2c3;
- ethernet0 = &gmac2io;
- ethernet1 = &gmac2phy;
};
cpus {
@@ -486,7 +488,6 @@
pwm3: pwm@ff1b0030 {
compatible = "rockchip,rk3328-pwm";
reg = <0x0 0xff1b0030 0x0 0x10>;
- interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cru SCLK_PWM>, <&cru PCLK_PWM>;
clock-names = "pwm", "pclk";
pinctrl-names = "default";
@@ -916,6 +917,8 @@
resets = <&cru SRST_GMAC2IO_A>;
reset-names = "stmmaceth";
rockchip,grf = <&grf>;
+ tx-fifo-depth = <2048>;
+ rx-fifo-depth = <4096>;
snps,txpbl = <0x4>;
status = "disabled";
};
@@ -938,6 +941,8 @@
reset-names = "stmmaceth";
phy-mode = "rmii";
phy-handle = <&phy>;
+ tx-fifo-depth = <2048>;
+ rx-fifo-depth = <4096>;
snps,txpbl = <0x4>;
clock_in_out = "output";
status = "disabled";
diff --git a/dts/upstream/src/arm64/rockchip/rk3368-evb.dtsi b/dts/upstream/src/arm64/rockchip/rk3368-evb.dtsi
index e47d139..b48b98c 100644
--- a/dts/upstream/src/arm64/rockchip/rk3368-evb.dtsi
+++ b/dts/upstream/src/arm64/rockchip/rk3368-evb.dtsi
@@ -9,6 +9,7 @@
/ {
aliases {
+ ethernet0 = &gmac;
mmc0 = &emmc;
};
diff --git a/dts/upstream/src/arm64/rockchip/rk3368-geekbox.dts b/dts/upstream/src/arm64/rockchip/rk3368-geekbox.dts
index be06e6e..029b8e2 100644
--- a/dts/upstream/src/arm64/rockchip/rk3368-geekbox.dts
+++ b/dts/upstream/src/arm64/rockchip/rk3368-geekbox.dts
@@ -12,6 +12,7 @@
compatible = "geekbuying,geekbox", "rockchip,rk3368";
aliases {
+ ethernet0 = &gmac;
mmc0 = &emmc;
};
diff --git a/dts/upstream/src/arm64/rockchip/rk3368-lion.dtsi b/dts/upstream/src/arm64/rockchip/rk3368-lion.dtsi
index 5753e57..8ac8acf 100644
--- a/dts/upstream/src/arm64/rockchip/rk3368-lion.dtsi
+++ b/dts/upstream/src/arm64/rockchip/rk3368-lion.dtsi
@@ -8,6 +8,7 @@
/ {
aliases {
+ ethernet0 = &gmac;
mmc0 = &emmc;
};
diff --git a/dts/upstream/src/arm64/rockchip/rk3368-orion-r68-meta.dts b/dts/upstream/src/arm64/rockchip/rk3368-orion-r68-meta.dts
index 81d1064..dcee2e2 100644
--- a/dts/upstream/src/arm64/rockchip/rk3368-orion-r68-meta.dts
+++ b/dts/upstream/src/arm64/rockchip/rk3368-orion-r68-meta.dts
@@ -12,6 +12,7 @@
compatible = "tronsmart,orion-r68-meta", "rockchip,rk3368";
aliases {
+ ethernet0 = &gmac;
mmc0 = &sdmmc;
mmc1 = &emmc;
};
diff --git a/dts/upstream/src/arm64/rockchip/rk3368-r88.dts b/dts/upstream/src/arm64/rockchip/rk3368-r88.dts
index 5589f3d..b16b7ca 100644
--- a/dts/upstream/src/arm64/rockchip/rk3368-r88.dts
+++ b/dts/upstream/src/arm64/rockchip/rk3368-r88.dts
@@ -12,6 +12,7 @@
compatible = "rockchip,r88", "rockchip,rk3368";
aliases {
+ ethernet0 = &gmac;
mmc0 = &sdio0;
mmc1 = &emmc;
};
diff --git a/dts/upstream/src/arm64/rockchip/rk3368.dtsi b/dts/upstream/src/arm64/rockchip/rk3368.dtsi
index a4c5aaf..62af0cb 100644
--- a/dts/upstream/src/arm64/rockchip/rk3368.dtsi
+++ b/dts/upstream/src/arm64/rockchip/rk3368.dtsi
@@ -19,7 +19,10 @@
#size-cells = <2>;
aliases {
- ethernet0 = &gmac;
+ gpio0 = &gpio0;
+ gpio1 = &gpio1;
+ gpio2 = &gpio2;
+ gpio3 = &gpio3;
i2c0 = &i2c0;
i2c1 = &i2c1;
i2c2 = &i2c2;
diff --git a/dts/upstream/src/arm64/rockchip/rk3399-eaidk-610.dts b/dts/upstream/src/arm64/rockchip/rk3399-eaidk-610.dts
index 6464ef4..173da81 100644
--- a/dts/upstream/src/arm64/rockchip/rk3399-eaidk-610.dts
+++ b/dts/upstream/src/arm64/rockchip/rk3399-eaidk-610.dts
@@ -15,6 +15,7 @@
compatible = "openailab,eaidk-610", "rockchip,rk3399";
aliases {
+ ethernet0 = &gmac;
mmc0 = &sdio0;
mmc1 = &sdmmc;
mmc2 = &sdhci;
diff --git a/dts/upstream/src/arm64/rockchip/rk3399-evb.dts b/dts/upstream/src/arm64/rockchip/rk3399-evb.dts
index 3d1e126..55eca7a 100644
--- a/dts/upstream/src/arm64/rockchip/rk3399-evb.dts
+++ b/dts/upstream/src/arm64/rockchip/rk3399-evb.dts
@@ -12,6 +12,7 @@
compatible = "rockchip,rk3399-evb", "rockchip,rk3399";
aliases {
+ ethernet0 = &gmac;
mmc0 = &sdhci;
};
diff --git a/dts/upstream/src/arm64/rockchip/rk3399-ficus.dts b/dts/upstream/src/arm64/rockchip/rk3399-ficus.dts
index 1ce85a5..30e4879 100644
--- a/dts/upstream/src/arm64/rockchip/rk3399-ficus.dts
+++ b/dts/upstream/src/arm64/rockchip/rk3399-ficus.dts
@@ -13,6 +13,10 @@
model = "96boards RK3399 Ficus";
compatible = "vamrs,ficus", "rockchip,rk3399";
+ aliases {
+ ethernet0 = &gmac;
+ };
+
chosen {
stdout-path = "serial2:1500000n8";
};
diff --git a/dts/upstream/src/arm64/rockchip/rk3399-firefly.dts b/dts/upstream/src/arm64/rockchip/rk3399-firefly.dts
index c5db64f..260415d 100644
--- a/dts/upstream/src/arm64/rockchip/rk3399-firefly.dts
+++ b/dts/upstream/src/arm64/rockchip/rk3399-firefly.dts
@@ -16,6 +16,7 @@
compatible = "firefly,firefly-rk3399", "rockchip,rk3399";
aliases {
+ ethernet0 = &gmac;
mmc0 = &sdio0;
mmc1 = &sdmmc;
mmc2 = &sdhci;
diff --git a/dts/upstream/src/arm64/rockchip/rk3399-gru-bob.dts b/dts/upstream/src/arm64/rockchip/rk3399-gru-bob.dts
index 0f9cc04..1cba1d8 100644
--- a/dts/upstream/src/arm64/rockchip/rk3399-gru-bob.dts
+++ b/dts/upstream/src/arm64/rockchip/rk3399-gru-bob.dts
@@ -70,7 +70,7 @@
&spi0 {
status = "okay";
- cr50@0 {
+ tpm@0 {
compatible = "google,cr50";
reg = <0>;
interrupt-parent = <&gpio0>;
diff --git a/dts/upstream/src/arm64/rockchip/rk3399-gru-scarlet.dtsi b/dts/upstream/src/arm64/rockchip/rk3399-gru-scarlet.dtsi
index c5e7de6..5846a11 100644
--- a/dts/upstream/src/arm64/rockchip/rk3399-gru-scarlet.dtsi
+++ b/dts/upstream/src/arm64/rockchip/rk3399-gru-scarlet.dtsi
@@ -706,7 +706,7 @@
&spi2 {
status = "okay";
- cr50@0 {
+ tpm@0 {
compatible = "google,cr50";
reg = <0>;
interrupt-parent = <&gpio1>;
diff --git a/dts/upstream/src/arm64/rockchip/rk3399-hugsun-x99.dts b/dts/upstream/src/arm64/rockchip/rk3399-hugsun-x99.dts
index 7af27e8..4a6ab6c 100644
--- a/dts/upstream/src/arm64/rockchip/rk3399-hugsun-x99.dts
+++ b/dts/upstream/src/arm64/rockchip/rk3399-hugsun-x99.dts
@@ -11,6 +11,7 @@
compatible = "hugsun,x99", "rockchip,rk3399";
aliases {
+ ethernet0 = &gmac;
mmc0 = &sdio0;
mmc1 = &sdmmc;
mmc2 = &sdhci;
diff --git a/dts/upstream/src/arm64/rockchip/rk3399-khadas-edge-captain.dts b/dts/upstream/src/arm64/rockchip/rk3399-khadas-edge-captain.dts
index 8302e51..99ac4ed 100644
--- a/dts/upstream/src/arm64/rockchip/rk3399-khadas-edge-captain.dts
+++ b/dts/upstream/src/arm64/rockchip/rk3399-khadas-edge-captain.dts
@@ -10,6 +10,10 @@
/ {
model = "Khadas Edge-Captain";
compatible = "khadas,edge-captain", "rockchip,rk3399";
+
+ aliases {
+ ethernet0 = &gmac;
+ };
};
&gmac {
diff --git a/dts/upstream/src/arm64/rockchip/rk3399-khadas-edge-v.dts b/dts/upstream/src/arm64/rockchip/rk3399-khadas-edge-v.dts
index f5dcb99..e12e7b4 100644
--- a/dts/upstream/src/arm64/rockchip/rk3399-khadas-edge-v.dts
+++ b/dts/upstream/src/arm64/rockchip/rk3399-khadas-edge-v.dts
@@ -10,6 +10,10 @@
/ {
model = "Khadas Edge-V";
compatible = "khadas,edge-v", "rockchip,rk3399";
+
+ aliases {
+ ethernet0 = &gmac;
+ };
};
&gmac {
diff --git a/dts/upstream/src/arm64/rockchip/rk3399-kobol-helios64.dts b/dts/upstream/src/arm64/rockchip/rk3399-kobol-helios64.dts
index 1eb287a..9e3aec4 100644
--- a/dts/upstream/src/arm64/rockchip/rk3399-kobol-helios64.dts
+++ b/dts/upstream/src/arm64/rockchip/rk3399-kobol-helios64.dts
@@ -19,6 +19,7 @@
compatible = "kobol,helios64", "rockchip,rk3399";
aliases {
+ ethernet0 = &gmac;
mmc0 = &sdmmc;
mmc1 = &sdhci;
spi1 = &spi1;
diff --git a/dts/upstream/src/arm64/rockchip/rk3399-leez-p710.dts b/dts/upstream/src/arm64/rockchip/rk3399-leez-p710.dts
index a21ac31..cb69e21 100644
--- a/dts/upstream/src/arm64/rockchip/rk3399-leez-p710.dts
+++ b/dts/upstream/src/arm64/rockchip/rk3399-leez-p710.dts
@@ -15,6 +15,7 @@
compatible = "leez,p710", "rockchip,rk3399";
aliases {
+ ethernet0 = &gmac;
mmc0 = &sdio0;
mmc1 = &sdmmc;
mmc2 = &sdhci;
diff --git a/dts/upstream/src/arm64/rockchip/rk3399-nanopi4.dtsi b/dts/upstream/src/arm64/rockchip/rk3399-nanopi4.dtsi
index 7c5f441..b7f1e47 100644
--- a/dts/upstream/src/arm64/rockchip/rk3399-nanopi4.dtsi
+++ b/dts/upstream/src/arm64/rockchip/rk3399-nanopi4.dtsi
@@ -18,6 +18,7 @@
/ {
aliases {
+ ethernet0 = &gmac;
mmc0 = &sdio0;
mmc1 = &sdmmc;
mmc2 = &sdhci;
diff --git a/dts/upstream/src/arm64/rockchip/rk3399-orangepi.dts b/dts/upstream/src/arm64/rockchip/rk3399-orangepi.dts
index dba4d03..e755144 100644
--- a/dts/upstream/src/arm64/rockchip/rk3399-orangepi.dts
+++ b/dts/upstream/src/arm64/rockchip/rk3399-orangepi.dts
@@ -17,6 +17,7 @@
compatible = "rockchip,rk3399-orangepi", "rockchip,rk3399";
aliases {
+ ethernet0 = &gmac;
mmc0 = &sdio0;
mmc1 = &sdmmc;
mmc2 = &sdhci;
diff --git a/dts/upstream/src/arm64/rockchip/rk3399-puma-haikou.dts b/dts/upstream/src/arm64/rockchip/rk3399-puma-haikou.dts
index 115c14c..18a98c4 100644
--- a/dts/upstream/src/arm64/rockchip/rk3399-puma-haikou.dts
+++ b/dts/upstream/src/arm64/rockchip/rk3399-puma-haikou.dts
@@ -5,6 +5,7 @@
/dts-v1/;
#include "rk3399-puma.dtsi"
+#include <dt-bindings/input/input.h>
/ {
model = "Theobroma Systems RK3399-Q7 SoM";
@@ -18,6 +19,38 @@
stdout-path = "serial0:115200n8";
};
+ gpio-keys {
+ compatible = "gpio-keys";
+ pinctrl-0 = <&haikou_keys_pin>;
+ pinctrl-names = "default";
+
+ button-batlow-n {
+ gpios = <&gpio0 RK_PB2 GPIO_ACTIVE_LOW>;
+ label = "BATLOW#";
+ linux,code = <KEY_BATTERY>;
+ };
+
+ button-slp-btn-n {
+ gpios = <&gpio0 RK_PB3 GPIO_ACTIVE_LOW>;
+ label = "SLP_BTN#";
+ linux,code = <KEY_SLEEP>;
+ };
+
+ button-wake-n {
+ gpios = <&gpio0 RK_PB1 GPIO_ACTIVE_LOW>;
+ label = "WAKE#";
+ linux,code = <KEY_WAKEUP>;
+ wakeup-source;
+ };
+
+ switch-lid-btn-n {
+ gpios = <&gpio0 RK_PA4 GPIO_ACTIVE_LOW>;
+ label = "LID_BTN#";
+ linux,code = <SW_LID>;
+ linux,input-type = <EV_SW>;
+ };
+ };
+
leds {
pinctrl-0 = <&module_led_pin>, <&sd_card_led_pin>;
@@ -165,11 +198,8 @@
};
&pinctrl {
- pinctrl-names = "default";
- pinctrl-0 = <&haikou_pin_hog>;
-
- hog {
- haikou_pin_hog: haikou-pin-hog {
+ buttons {
+ haikou_keys_pin: haikou-keys-pin {
rockchip,pins =
/* LID_BTN */
<0 RK_PA4 RK_FUNC_GPIO &pcfg_pull_up>,
@@ -177,7 +207,7 @@
<0 RK_PB2 RK_FUNC_GPIO &pcfg_pull_up>,
/* SLP_BTN# */
<0 RK_PB3 RK_FUNC_GPIO &pcfg_pull_up>,
- /* BIOS_DISABLE# */
+ /* WAKE# */
<0 RK_PB1 RK_FUNC_GPIO &pcfg_pull_up>;
};
};
diff --git a/dts/upstream/src/arm64/rockchip/rk3399-puma.dtsi b/dts/upstream/src/arm64/rockchip/rk3399-puma.dtsi
index 20e3f41..c08e693 100644
--- a/dts/upstream/src/arm64/rockchip/rk3399-puma.dtsi
+++ b/dts/upstream/src/arm64/rockchip/rk3399-puma.dtsi
@@ -9,6 +9,7 @@
/ {
aliases {
+ ethernet0 = &gmac;
mmc0 = &sdhci;
};
@@ -119,6 +120,20 @@
drive-impedance-ohm = <33>;
};
+&gpio0 {
+ /*
+ * The BIOS_DISABLE hog is a feedback pin for the actual status of the
+ * signal. This usually represents the state of a switch on the baseboard.
+ * The pin has a 10k pull-up resistor connected, so no pull-up setting is needed.
+ */
+ bios-disable-hog {
+ gpios = <RK_PB0 GPIO_ACTIVE_HIGH>;
+ gpio-hog;
+ input;
+ line-name = "bios_disable";
+ };
+};
+
&gmac {
assigned-clocks = <&cru SCLK_RMII_SRC>;
assigned-clock-parents = <&clkin_gmac>;
diff --git a/dts/upstream/src/arm64/rockchip/rk3399-roc-pc.dtsi b/dts/upstream/src/arm64/rockchip/rk3399-roc-pc.dtsi
index c32913d..ca7a446 100644
--- a/dts/upstream/src/arm64/rockchip/rk3399-roc-pc.dtsi
+++ b/dts/upstream/src/arm64/rockchip/rk3399-roc-pc.dtsi
@@ -14,6 +14,7 @@
compatible = "firefly,roc-rk3399-pc", "rockchip,rk3399";
aliases {
+ ethernet0 = &gmac;
mmc0 = &sdmmc;
mmc1 = &sdhci;
};
diff --git a/dts/upstream/src/arm64/rockchip/rk3399-rock-4c-plus.dts b/dts/upstream/src/arm64/rockchip/rk3399-rock-4c-plus.dts
index 8bfd5f8..7baf9d1 100644
--- a/dts/upstream/src/arm64/rockchip/rk3399-rock-4c-plus.dts
+++ b/dts/upstream/src/arm64/rockchip/rk3399-rock-4c-plus.dts
@@ -15,6 +15,7 @@
compatible = "radxa,rock-4c-plus", "rockchip,rk3399";
aliases {
+ ethernet0 = &gmac;
mmc0 = &sdhci;
mmc1 = &sdmmc;
};
diff --git a/dts/upstream/src/arm64/rockchip/rk3399-rock-pi-4.dtsi b/dts/upstream/src/arm64/rockchip/rk3399-rock-pi-4.dtsi
index f2279aa..281a121 100644
--- a/dts/upstream/src/arm64/rockchip/rk3399-rock-pi-4.dtsi
+++ b/dts/upstream/src/arm64/rockchip/rk3399-rock-pi-4.dtsi
@@ -12,6 +12,7 @@
/ {
aliases {
+ ethernet0 = &gmac;
mmc0 = &sdhci;
mmc1 = &sdmmc;
};
diff --git a/dts/upstream/src/arm64/rockchip/rk3399-rockpro64.dtsi b/dts/upstream/src/arm64/rockchip/rk3399-rockpro64.dtsi
index bca2b50..f30b82a 100644
--- a/dts/upstream/src/arm64/rockchip/rk3399-rockpro64.dtsi
+++ b/dts/upstream/src/arm64/rockchip/rk3399-rockpro64.dtsi
@@ -11,6 +11,7 @@
/ {
aliases {
+ ethernet0 = &gmac;
mmc0 = &sdio0;
mmc1 = &sdmmc;
mmc2 = &sdhci;
diff --git a/dts/upstream/src/arm64/rockchip/rk3399-sapphire.dtsi b/dts/upstream/src/arm64/rockchip/rk3399-sapphire.dtsi
index e6ac292..b3ef1c8 100644
--- a/dts/upstream/src/arm64/rockchip/rk3399-sapphire.dtsi
+++ b/dts/upstream/src/arm64/rockchip/rk3399-sapphire.dtsi
@@ -12,6 +12,7 @@
compatible = "rockchip,rk3399-sapphire", "rockchip,rk3399";
aliases {
+ ethernet0 = &gmac;
mmc0 = &sdmmc;
mmc1 = &sdhci;
};
@@ -44,7 +45,7 @@
fan0: gpio-fan {
#cooling-cells = <2>;
compatible = "gpio-fan";
- gpio-fan,speed-map = <0 0 3000 1>;
+ gpio-fan,speed-map = <0 0>, <3000 1>;
gpios = <&gpio1 RK_PC2 GPIO_ACTIVE_HIGH>;
status = "okay";
};
diff --git a/dts/upstream/src/arm64/rockchip/rk3399.dtsi b/dts/upstream/src/arm64/rockchip/rk3399.dtsi
index da0dfb2..6e12c5a 100644
--- a/dts/upstream/src/arm64/rockchip/rk3399.dtsi
+++ b/dts/upstream/src/arm64/rockchip/rk3399.dtsi
@@ -19,7 +19,11 @@
#size-cells = <2>;
aliases {
- ethernet0 = &gmac;
+ gpio0 = &gpio0;
+ gpio1 = &gpio1;
+ gpio2 = &gpio2;
+ gpio3 = &gpio3;
+ gpio4 = &gpio4;
i2c0 = &i2c0;
i2c1 = &i2c1;
i2c2 = &i2c2;
@@ -2114,6 +2118,7 @@
interrupt-names = "job", "mmu", "gpu";
clocks = <&cru ACLK_GPU>;
#cooling-cells = <2>;
+ dynamic-power-coefficient = <2640>;
power-domains = <&power RK3399_PD_GPU>;
status = "disabled";
};
diff --git a/dts/upstream/src/arm64/rockchip/rk3399pro-vmarc-som.dtsi b/dts/upstream/src/arm64/rockchip/rk3399pro-vmarc-som.dtsi
index 8b8992a..8823c92 100644
--- a/dts/upstream/src/arm64/rockchip/rk3399pro-vmarc-som.dtsi
+++ b/dts/upstream/src/arm64/rockchip/rk3399pro-vmarc-som.dtsi
@@ -13,6 +13,7 @@
compatible = "vamrs,rk3399pro-vmarc-som", "rockchip,rk3399pro";
aliases {
+ ethernet0 = &gmac;
mmc0 = &sdhci;
mmc1 = &sdmmc;
};
diff --git a/dts/upstream/src/arm64/rockchip/rk3566-lubancat-1.dts b/dts/upstream/src/arm64/rockchip/rk3566-lubancat-1.dts
index 1c6d83b..6ecdf5d 100644
--- a/dts/upstream/src/arm64/rockchip/rk3566-lubancat-1.dts
+++ b/dts/upstream/src/arm64/rockchip/rk3566-lubancat-1.dts
@@ -455,7 +455,7 @@
&pinctrl {
leds {
sys_led_pin: sys-status-led-pin {
- rockchip,pins = <0 RK_PC7 RK_FUNC_GPIO &pcfg_pull_none>;
+ rockchip,pins = <0 RK_PC5 RK_FUNC_GPIO &pcfg_pull_none>;
};
};
diff --git a/dts/upstream/src/arm64/rockchip/rk3566-powkiddy-rgb30.dts b/dts/upstream/src/arm64/rockchip/rk3566-powkiddy-rgb30.dts
index 1ead3c5..0ac64f0 100644
--- a/dts/upstream/src/arm64/rockchip/rk3566-powkiddy-rgb30.dts
+++ b/dts/upstream/src/arm64/rockchip/rk3566-powkiddy-rgb30.dts
@@ -5,67 +5,11 @@
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/input/linux-event-codes.h>
#include <dt-bindings/pinctrl/rockchip.h>
-#include "rk3566-anbernic-rg353x.dtsi"
+#include "rk3566-powkiddy-rk2023.dtsi"
/ {
model = "RGB30";
compatible = "powkiddy,rgb30", "rockchip,rk3566";
-
- aliases {
- mmc1 = &sdmmc0;
- mmc2 = &sdmmc1;
- mmc3 = &sdmmc2;
- };
-
- battery: battery {
- compatible = "simple-battery";
- charge-full-design-microamp-hours = <3151000>;
- charge-term-current-microamp = <300000>;
- constant-charge-current-max-microamp = <2000000>;
- constant-charge-voltage-max-microvolt = <4250000>;
- factory-internal-resistance-micro-ohms = <117000>;
- voltage-max-design-microvolt = <4172000>;
- voltage-min-design-microvolt = <3400000>;
-
- ocv-capacity-celsius = <20>;
- ocv-capacity-table-0 = <4172000 100>, <4092000 95>, <4035000 90>, <3990000 85>,
- <3939000 80>, <3895000 75>, <3852000 70>, <3807000 65>,
- <3762000 60>, <3713000 55>, <3672000 50>, <3647000 45>,
- <3629000 40>, <3613000 35>, <3598000 30>, <3578000 25>,
- <3550000 20>, <3519000 15>, <3479000 10>, <3438000 5>,
- <3400000 0>;
- };
-
- /*
- * Channels reversed for speakers. Headphones automatically switch via hardware when
- * detected with no ability to control output in software. Headphones appear to be mono
- * (each output channel receives all audio). No microphone support on 3.5mm jack.
- */
- sound {
- compatible = "simple-audio-card";
- simple-audio-card,name = "rk817_ext";
- simple-audio-card,format = "i2s";
- simple-audio-card,mclk-fs = <256>;
- simple-audio-card,widgets =
- "Headphone", "Headphones";
- simple-audio-card,routing =
- "Headphones", "HPOL",
- "Headphones", "HPOR";
-
- simple-audio-card,codec {
- sound-dai = <&rk817>;
- };
-
- simple-audio-card,cpu {
- sound-dai = <&i2s1_8ch>;
- };
- };
-};
-
-/delete-node/ &adc_keys;
-
-&chosen {
- /delete-property/ stdout-path;
};
&cru {
@@ -75,87 +19,21 @@
<200000000>, <292500000>;
};
-&gpio_keys_control {
- button-r1 {
- gpios = <&gpio3 RK_PB3 GPIO_ACTIVE_LOW>;
- label = "TR";
- linux,code = <BTN_TR>;
- };
-
- button-r2 {
- gpios = <&gpio3 RK_PB4 GPIO_ACTIVE_LOW>;
- label = "TR2";
- linux,code = <BTN_TR2>;
- };
-};
+&dsi0 {
+ panel: panel@0 {
+ compatible = "powkiddy,rgb30-panel";
+ reg = <0>;
+ backlight = <&backlight>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&lcd_rst>;
+ reset-gpios = <&gpio4 RK_PA0 GPIO_ACTIVE_LOW>;
+ vcc-supply = <&vcc3v3_lcd0_n>;
+ iovcc-supply = <&vcc3v3_lcd0_n>;
-/delete-node/ &{/i2c@fdd40000/regulator@40};
-
-&i2c0 {
- vdd_cpu: regulator@1c {
- compatible = "tcs,tcs4525";
- reg = <0x1c>;
- fcs,suspend-voltage-selector = <1>;
- regulator-always-on;
- regulator-boot-on;
- regulator-min-microvolt = <712500>;
- regulator-max-microvolt = <1390000>;
- regulator-name = "vdd_cpu";
- regulator-ramp-delay = <2300>;
- vin-supply = <&vcc_sys>;
- regulator-state-mem {
- regulator-off-in-suspend;
+ port {
+ mipi_in_panel: endpoint {
+ remote-endpoint = <&mipi_out_panel>;
+ };
};
};
-};
-
-/*
- * Device has 2 red LEDs instead of an amber and a red. Relabel LEDs as
- * red_led0 and red_led1.
- */
-/delete-node/ &{/pwm-leds/led-1};
-/delete-node/ &{/pwm-leds/led-2};
-
-&leds {
- red_led0: led-1 {
- color = <LED_COLOR_ID_RED>;
- function = LED_FUNCTION_CHARGING;
- max-brightness = <255>;
- pwms = <&pwm7 0 25000 0>;
- };
-
- red_led1: led-2 {
- color = <LED_COLOR_ID_RED>;
- default-state = "off";
- function = LED_FUNCTION_STATUS;
- max-brightness = <255>;
- pwms = <&pwm0 0 25000 0>;
- };
-};
-
-&panel {
- compatible = "powkiddy,rgb30-panel";
- vcc-supply = <&vcc3v3_lcd0_n>;
- iovcc-supply = <&vcc3v3_lcd0_n>;
- /delete-property/ vdd-supply;
};
-
-&pwm5 {
- status = "disabled";
-};
-
-&rk817 {
- rk817_charger: charger {
- monitored-battery = <&battery>;
- rockchip,resistor-sense-micro-ohms = <10000>;
- rockchip,sleep-enter-current-microamp = <300000>;
- rockchip,sleep-filter-current-microamp = <100000>;
- };
-};
-
-/* There is no UART header visible on the board for this device. */
-&uart2 {
- status = "disabled";
-};
-
-/delete-node/ &vibrator;
diff --git a/dts/upstream/src/arm64/rockchip/rk3566-powkiddy-rk2023.dts b/dts/upstream/src/arm64/rockchip/rk3566-powkiddy-rk2023.dts
new file mode 100644
index 0000000..ba32d07
--- /dev/null
+++ b/dts/upstream/src/arm64/rockchip/rk3566-powkiddy-rk2023.dts
@@ -0,0 +1,38 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+
+/dts-v1/;
+
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/input/linux-event-codes.h>
+#include <dt-bindings/pinctrl/rockchip.h>
+#include "rk3566-powkiddy-rk2023.dtsi"
+
+/ {
+ model = "RK2023";
+ compatible = "powkiddy,rk2023", "rockchip,rk3566";
+};
+
+&cru {
+ assigned-clocks = <&pmucru CLK_RTC_32K>, <&cru PLL_GPLL>,
+ <&pmucru PLL_PPLL>, <&cru PLL_VPLL>;
+ assigned-clock-rates = <32768>, <1200000000>,
+ <200000000>, <115200000>;
+};
+
+&dsi0 {
+ panel: panel@0 {
+ compatible = "powkiddy,rk2023-panel", "newvision,nv3051d";
+ reg = <0>;
+ backlight = <&backlight>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&lcd_rst>;
+ reset-gpios = <&gpio4 RK_PA0 GPIO_ACTIVE_LOW>;
+ vdd-supply = <&vcc3v3_lcd0_n>;
+
+ port {
+ mipi_in_panel: endpoint {
+ remote-endpoint = <&mipi_out_panel>;
+ };
+ };
+ };
+};
diff --git a/dts/upstream/src/arm64/rockchip/rk3566-powkiddy-rk2023.dtsi b/dts/upstream/src/arm64/rockchip/rk3566-powkiddy-rk2023.dtsi
new file mode 100644
index 0000000..0fa8f06
--- /dev/null
+++ b/dts/upstream/src/arm64/rockchip/rk3566-powkiddy-rk2023.dtsi
@@ -0,0 +1,875 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+
+/dts-v1/;
+
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/input/linux-event-codes.h>
+#include <dt-bindings/leds/common.h>
+#include <dt-bindings/pinctrl/rockchip.h>
+#include <dt-bindings/soc/rockchip,vop2.h>
+#include "rk3566.dtsi"
+
+/ {
+ aliases {
+ mmc1 = &sdmmc0;
+ mmc2 = &sdmmc1;
+ mmc3 = &sdmmc2;
+ };
+
+ adc-joystick {
+ compatible = "adc-joystick";
+ io-channels = <&adc_mux 0>,
+ <&adc_mux 1>,
+ <&adc_mux 2>,
+ <&adc_mux 3>;
+ pinctrl-0 = <&joy_mux_en>;
+ pinctrl-names = "default";
+ poll-interval = <60>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ axis@0 {
+ reg = <0>;
+ abs-flat = <32>;
+ abs-fuzz = <32>;
+ abs-range = <1023 15>;
+ linux,code = <ABS_X>;
+ };
+
+ axis@1 {
+ reg = <1>;
+ abs-flat = <32>;
+ abs-fuzz = <32>;
+ abs-range = <15 1023>;
+ linux,code = <ABS_RX>;
+ };
+
+ axis@2 {
+ reg = <2>;
+ abs-flat = <32>;
+ abs-fuzz = <32>;
+ abs-range = <15 1023>;
+ linux,code = <ABS_Y>;
+ };
+
+ axis@3 {
+ reg = <3>;
+ abs-flat = <32>;
+ abs-fuzz = <32>;
+ abs-range = <1023 15>;
+ linux,code = <ABS_RY>;
+ };
+ };
+
+ adc_mux: adc-mux {
+ compatible = "io-channel-mux";
+ channels = "left_x", "right_x", "left_y", "right_y";
+ #io-channel-cells = <1>;
+ io-channels = <&saradc 3>;
+ io-channel-names = "parent";
+ mux-controls = <&gpio_mux>;
+ settle-time-us = <100>;
+ };
+
+ backlight: backlight {
+ compatible = "pwm-backlight";
+ power-supply = <&vcc_sys>;
+ pwms = <&pwm4 0 25000 0>;
+ };
+
+ battery: battery {
+ compatible = "simple-battery";
+ charge-full-design-microamp-hours = <3151000>;
+ charge-term-current-microamp = <300000>;
+ constant-charge-current-max-microamp = <2000000>;
+ constant-charge-voltage-max-microvolt = <4250000>;
+ factory-internal-resistance-micro-ohms = <117000>;
+ voltage-max-design-microvolt = <4172000>;
+ voltage-min-design-microvolt = <3400000>;
+
+ ocv-capacity-celsius = <20>;
+ ocv-capacity-table-0 = <4172000 100>, <4092000 95>, <4035000 90>, <3990000 85>,
+ <3939000 80>, <3895000 75>, <3852000 70>, <3807000 65>,
+ <3762000 60>, <3713000 55>, <3672000 50>, <3647000 45>,
+ <3629000 40>, <3613000 35>, <3598000 30>, <3578000 25>,
+ <3550000 20>, <3519000 15>, <3479000 10>, <3438000 5>,
+ <3400000 0>;
+ };
+
+ gpio_keys_control: gpio-keys-control {
+ compatible = "gpio-keys";
+ pinctrl-0 = <&btn_pins_ctrl>;
+ pinctrl-names = "default";
+
+ button-a {
+ gpios = <&gpio3 RK_PC2 GPIO_ACTIVE_LOW>;
+ label = "EAST";
+ linux,code = <BTN_EAST>;
+ };
+
+ button-b {
+ gpios = <&gpio3 RK_PC3 GPIO_ACTIVE_LOW>;
+ label = "SOUTH";
+ linux,code = <BTN_SOUTH>;
+ };
+
+ button-down {
+ gpios = <&gpio3 RK_PA4 GPIO_ACTIVE_LOW>;
+ label = "DPAD-DOWN";
+ linux,code = <BTN_DPAD_DOWN>;
+ };
+
+ button-l1 {
+ gpios = <&gpio3 RK_PB1 GPIO_ACTIVE_LOW>;
+ label = "TL";
+ linux,code = <BTN_TL>;
+ };
+
+ button-l2 {
+ gpios = <&gpio3 RK_PB2 GPIO_ACTIVE_LOW>;
+ label = "TL2";
+ linux,code = <BTN_TL2>;
+ };
+
+ button-left {
+ gpios = <&gpio3 RK_PA6 GPIO_ACTIVE_LOW>;
+ label = "DPAD-LEFT";
+ linux,code = <BTN_DPAD_LEFT>;
+ };
+
+ button-r1 {
+ gpios = <&gpio3 RK_PB3 GPIO_ACTIVE_LOW>;
+ label = "TR";
+ linux,code = <BTN_TR>;
+ };
+
+ button-r2 {
+ gpios = <&gpio3 RK_PB4 GPIO_ACTIVE_LOW>;
+ label = "TR2";
+ linux,code = <BTN_TR2>;
+ };
+
+ button-right {
+ gpios = <&gpio3 RK_PA5 GPIO_ACTIVE_LOW>;
+ label = "DPAD-RIGHT";
+ linux,code = <BTN_DPAD_RIGHT>;
+ };
+
+ button-select {
+ gpios = <&gpio3 RK_PB6 GPIO_ACTIVE_LOW>;
+ label = "SELECT";
+ linux,code = <BTN_SELECT>;
+ };
+
+ button-start {
+ gpios = <&gpio3 RK_PB5 GPIO_ACTIVE_LOW>;
+ label = "START";
+ linux,code = <BTN_START>;
+ };
+
+ button-thumbl {
+ gpios = <&gpio3 RK_PA1 GPIO_ACTIVE_LOW>;
+ label = "THUMBL";
+ linux,code = <BTN_THUMBL>;
+ };
+
+ button-thumbr {
+ gpios = <&gpio3 RK_PA2 GPIO_ACTIVE_LOW>;
+ label = "THUMBR";
+ linux,code = <BTN_THUMBR>;
+ };
+
+ button-up {
+ gpios = <&gpio3 RK_PA3 GPIO_ACTIVE_LOW>;
+ label = "DPAD-UP";
+ linux,code = <BTN_DPAD_UP>;
+ };
+
+ button-x {
+ gpios = <&gpio3 RK_PC0 GPIO_ACTIVE_LOW>;
+ label = "NORTH";
+ linux,code = <BTN_NORTH>;
+ };
+
+ button-y {
+ gpios = <&gpio3 RK_PC1 GPIO_ACTIVE_LOW>;
+ label = "WEST";
+ linux,code = <BTN_WEST>;
+ };
+ };
+
+ gpio_keys_vol: gpio-keys-vol {
+ compatible = "gpio-keys";
+ autorepeat;
+ pinctrl-0 = <&btn_pins_vol>;
+ pinctrl-names = "default";
+
+ button-vol-down {
+ gpios = <&gpio3 RK_PB0 GPIO_ACTIVE_LOW>;
+ label = "VOLUMEDOWN";
+ linux,code = <KEY_VOLUMEDOWN>;
+ };
+
+ button-vol-up {
+ gpios = <&gpio3 RK_PA7 GPIO_ACTIVE_LOW>;
+ label = "VOLUMEUP";
+ linux,code = <KEY_VOLUMEUP>;
+ };
+ };
+
+ gpio_mux: mux-controller {
+ compatible = "gpio-mux";
+ mux-gpios = <&gpio0 RK_PB6 GPIO_ACTIVE_LOW>,
+ <&gpio0 RK_PB7 GPIO_ACTIVE_LOW>;
+ #mux-control-cells = <0>;
+ };
+
+ hdmi-con {
+ compatible = "hdmi-connector";
+ ddc-i2c-bus = <&i2c5>;
+ type = "c";
+
+ port {
+ hdmi_con_in: endpoint {
+ remote-endpoint = <&hdmi_out_con>;
+ };
+ };
+ };
+
+ /*
+ * Device also includes an always on LED that is wired to the 5V input
+ * voltage and is on when the device is plugged in.
+ */
+ leds: pwm-leds {
+ compatible = "pwm-leds";
+
+ green_led: led-0 {
+ color = <LED_COLOR_ID_GREEN>;
+ function = LED_FUNCTION_STATUS;
+ max-brightness = <255>;
+ pwms = <&pwm6 0 25000 0>;
+ };
+
+ red_led: led-1 {
+ color = <LED_COLOR_ID_RED>;
+ function = LED_FUNCTION_CHARGING;
+ max-brightness = <255>;
+ pwms = <&pwm7 0 25000 0>;
+ };
+ };
+
+ sdio_pwrseq: sdio-pwrseq {
+ compatible = "mmc-pwrseq-simple";
+ clocks = <&rk817 1>;
+ clock-names = "ext_clock";
+ pinctrl-0 = <&wifi_enable_h>;
+ pinctrl-names = "default";
+ post-power-on-delay-ms = <200>;
+ reset-gpios = <&gpio4 RK_PA2 GPIO_ACTIVE_LOW>;
+ };
+
+ /*
+ * Channels reversed for speakers. Headphones automatically switch via hardware when
+ * detected with no ability to control output in software. Headphones appear to be mono
+ * (each output channel receives all audio). No microphone support on 3.5mm jack.
+ */
+ sound {
+ compatible = "simple-audio-card";
+ simple-audio-card,name = "rk817_ext";
+ simple-audio-card,format = "i2s";
+ simple-audio-card,mclk-fs = <256>;
+ simple-audio-card,widgets =
+ "Headphone", "Headphones";
+ simple-audio-card,routing =
+ "Headphones", "HPOL",
+ "Headphones", "HPOR";
+
+ simple-audio-card,codec {
+ sound-dai = <&rk817>;
+ };
+
+ simple-audio-card,cpu {
+ sound-dai = <&i2s1_8ch>;
+ };
+ };
+
+ vcc3v3_lcd0_n: regulator-vcc3v3-lcd0 {
+ compatible = "regulator-fixed";
+ gpio = <&gpio0 RK_PC2 GPIO_ACTIVE_HIGH>;
+ enable-active-high;
+ pinctrl-0 = <&vcc_lcd_h>;
+ pinctrl-names = "default";
+ regulator-boot-on;
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-name = "vcc3v3_lcd0_n";
+ vin-supply = <&vcc_3v3>;
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ };
+ };
+
+ vcc_sys: regulator-vcc-sys {
+ compatible = "regulator-fixed";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <3800000>;
+ regulator-max-microvolt = <3800000>;
+ regulator-name = "vcc_sys";
+ };
+
+ vcc_wifi: regulator-vcc-wifi {
+ compatible = "regulator-fixed";
+ enable-active-high;
+ gpio = <&gpio0 RK_PA0 GPIO_ACTIVE_HIGH>;
+ pinctrl-0 = <&vcc_wifi_h>;
+ pinctrl-names = "default";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-name = "vcc_wifi";
+ };
+};
+
+&combphy1 {
+ status = "okay";
+};
+
+&cpu0 {
+ cpu-supply = <&vdd_cpu>;
+};
+
+&cpu1 {
+ cpu-supply = <&vdd_cpu>;
+};
+
+&cpu2 {
+ cpu-supply = <&vdd_cpu>;
+};
+
+&cpu3 {
+ cpu-supply = <&vdd_cpu>;
+};
+
+&dsi0 {
+ status = "okay";
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ ports {
+ dsi0_in: port@0 {
+ reg = <0>;
+ dsi0_in_vp1: endpoint {
+ remote-endpoint = <&vp1_out_dsi0>;
+ };
+ };
+
+ dsi0_out: port@1 {
+ reg = <1>;
+ mipi_out_panel: endpoint {
+ remote-endpoint = <&mipi_in_panel>;
+ };
+ };
+ };
+};
+
+&dsi_dphy0 {
+ status = "okay";
+};
+
+&gpu {
+ mali-supply = <&vdd_gpu>;
+ status = "okay";
+};
+
+&hdmi {
+ ddc-i2c-bus = <&i2c5>;
+ pinctrl-0 = <&hdmitxm0_cec>;
+ pinctrl-names = "default";
+ status = "okay";
+};
+
+&hdmi_in {
+ hdmi_in_vp0: endpoint {
+ remote-endpoint = <&vp0_out_hdmi>;
+ };
+};
+
+&hdmi_out {
+ hdmi_out_con: endpoint {
+ remote-endpoint = <&hdmi_con_in>;
+ };
+};
+
+&hdmi_sound {
+ status = "okay";
+};
+
+&i2c0 {
+ status = "okay";
+
+ rk817: pmic@20 {
+ compatible = "rockchip,rk817";
+ reg = <0x20>;
+ interrupt-parent = <&gpio0>;
+ interrupts = <RK_PA3 IRQ_TYPE_LEVEL_LOW>;
+ clock-output-names = "rk808-clkout1", "rk808-clkout2";
+ clock-names = "mclk";
+ clocks = <&cru I2S1_MCLKOUT_TX>;
+ assigned-clocks = <&cru I2S1_MCLKOUT_TX>;
+ assigned-clock-parents = <&cru CLK_I2S1_8CH_TX>;
+ #clock-cells = <1>;
+ #sound-dai-cells = <0>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&i2s1m0_mclk>, <&pmic_int_l>;
+ wakeup-source;
+
+ vcc1-supply = <&vcc_sys>;
+ vcc2-supply = <&vcc_sys>;
+ vcc3-supply = <&vcc_sys>;
+ vcc4-supply = <&vcc_sys>;
+ vcc5-supply = <&vcc_sys>;
+ vcc6-supply = <&vcc_sys>;
+ vcc7-supply = <&vcc_sys>;
+ vcc8-supply = <&vcc_sys>;
+ vcc9-supply = <&dcdc_boost>;
+
+ regulators {
+ vdd_logic: DCDC_REG1 {
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <500000>;
+ regulator-max-microvolt = <1350000>;
+ regulator-ramp-delay = <6001>;
+ regulator-initial-mode = <0x2>;
+ regulator-name = "vdd_logic";
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ regulator-suspend-microvolt = <900000>;
+ };
+ };
+
+ vdd_gpu: DCDC_REG2 {
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <500000>;
+ regulator-max-microvolt = <1350000>;
+ regulator-ramp-delay = <6001>;
+ regulator-initial-mode = <0x2>;
+ regulator-name = "vdd_gpu";
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ };
+ };
+
+ vcc_ddr: DCDC_REG3 {
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-initial-mode = <0x2>;
+ regulator-name = "vcc_ddr";
+ regulator-state-mem {
+ regulator-on-in-suspend;
+ };
+ };
+
+ vcc_3v3: DCDC_REG4 {
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-initial-mode = <0x2>;
+ regulator-name = "vcc_3v3";
+ regulator-state-mem {
+ regulator-on-in-suspend;
+ regulator-suspend-microvolt = <3300000>;
+ };
+ };
+
+ vcca1v8_pmu: LDO_REG1 {
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-name = "vcca1v8_pmu";
+ regulator-state-mem {
+ regulator-on-in-suspend;
+ regulator-suspend-microvolt = <1800000>;
+ };
+ };
+
+ vdda_0v9: LDO_REG2 {
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <900000>;
+ regulator-max-microvolt = <900000>;
+ regulator-name = "vdda_0v9";
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ };
+ };
+
+ vdda0v9_pmu: LDO_REG3 {
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <900000>;
+ regulator-max-microvolt = <900000>;
+ regulator-name = "vdda0v9_pmu";
+ regulator-state-mem {
+ regulator-on-in-suspend;
+ regulator-suspend-microvolt = <900000>;
+ };
+ };
+
+ vccio_acodec: LDO_REG4 {
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-name = "vccio_acodec";
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ };
+ };
+
+ vccio_sd: LDO_REG5 {
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-name = "vccio_sd";
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ };
+ };
+
+ vcc3v3_pmu: LDO_REG6 {
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-name = "vcc3v3_pmu";
+ regulator-state-mem {
+ regulator-on-in-suspend;
+ regulator-suspend-microvolt = <3300000>;
+ };
+ };
+
+ vcc_1v8: LDO_REG7 {
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-name = "vcc_1v8";
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ };
+ };
+
+ vcc1v8_dvp: LDO_REG8 {
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-name = "vcc1v8_dvp";
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ };
+ };
+
+ vcc2v8_dvp: LDO_REG9 {
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <2800000>;
+ regulator-max-microvolt = <2800000>;
+ regulator-name = "vcc2v8_dvp";
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ };
+ };
+
+ dcdc_boost: BOOST {
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <4700000>;
+ regulator-max-microvolt = <5400000>;
+ regulator-name = "boost";
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ };
+ };
+
+ otg_switch: OTG_SWITCH {
+ regulator-name = "otg_switch";
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ };
+ };
+ };
+
+ rk817_charger: charger {
+ monitored-battery = <&battery>;
+ rockchip,resistor-sense-micro-ohms = <10000>;
+ rockchip,sleep-enter-current-microamp = <300000>;
+ rockchip,sleep-filter-current-microamp = <100000>;
+ };
+ };
+
+ vdd_cpu: regulator@1c {
+ compatible = "tcs,tcs4525";
+ reg = <0x1c>;
+ fcs,suspend-voltage-selector = <1>;
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <712500>;
+ regulator-max-microvolt = <1390000>;
+ regulator-name = "vdd_cpu";
+ regulator-ramp-delay = <2300>;
+ vin-supply = <&vcc_sys>;
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ };
+ };
+};
+
+&i2c5 {
+ pinctrl-0 = <&i2c5m1_xfer>;
+ pinctrl-names = "default";
+ status = "okay";
+};
+
+&i2s0_8ch {
+ status = "okay";
+};
+
+&i2s1_8ch {
+ pinctrl-0 = <&i2s1m0_sclktx
+ &i2s1m0_lrcktx
+ &i2s1m0_sdi0
+ &i2s1m0_sdo0>;
+ pinctrl-names = "default";
+ rockchip,trcm-sync-tx-only;
+ status = "okay";
+};
+
+&pinctrl {
+ gpio-btns {
+ btn_pins_ctrl: btn-pins-ctrl {
+ rockchip,pins =
+ <3 RK_PA1 RK_FUNC_GPIO &pcfg_pull_up>,
+ <3 RK_PA2 RK_FUNC_GPIO &pcfg_pull_up>,
+ <3 RK_PA3 RK_FUNC_GPIO &pcfg_pull_up>,
+ <3 RK_PA4 RK_FUNC_GPIO &pcfg_pull_up>,
+ <3 RK_PA5 RK_FUNC_GPIO &pcfg_pull_up>,
+ <3 RK_PA6 RK_FUNC_GPIO &pcfg_pull_up>,
+ <3 RK_PB1 RK_FUNC_GPIO &pcfg_pull_up>,
+ <3 RK_PB2 RK_FUNC_GPIO &pcfg_pull_up>,
+ <3 RK_PB3 RK_FUNC_GPIO &pcfg_pull_up>,
+ <3 RK_PB4 RK_FUNC_GPIO &pcfg_pull_up>,
+ <3 RK_PB5 RK_FUNC_GPIO &pcfg_pull_up>,
+ <3 RK_PB6 RK_FUNC_GPIO &pcfg_pull_up>,
+ <3 RK_PC0 RK_FUNC_GPIO &pcfg_pull_up>,
+ <3 RK_PC1 RK_FUNC_GPIO &pcfg_pull_up>,
+ <3 RK_PC2 RK_FUNC_GPIO &pcfg_pull_up>,
+ <3 RK_PC3 RK_FUNC_GPIO &pcfg_pull_up>;
+ };
+
+ btn_pins_vol: btn-pins-vol {
+ rockchip,pins =
+ <3 RK_PA7 RK_FUNC_GPIO &pcfg_pull_up>,
+ <3 RK_PB0 RK_FUNC_GPIO &pcfg_pull_up>;
+ };
+ };
+
+ joy-mux {
+ joy_mux_en: joy-mux-en {
+ rockchip,pins =
+ <0 RK_PB5 RK_FUNC_GPIO &pcfg_output_low>;
+ };
+ };
+
+ gpio-lcd {
+ lcd_rst: lcd-rst {
+ rockchip,pins =
+ <4 RK_PA0 RK_FUNC_GPIO &pcfg_pull_none>;
+ };
+ };
+
+ pmic {
+ pmic_int_l: pmic-int-l {
+ rockchip,pins =
+ <0 RK_PA3 RK_FUNC_GPIO &pcfg_pull_up>;
+ };
+ };
+
+ sdio-pwrseq {
+ wifi_enable_h: wifi-enable-h {
+ rockchip,pins =
+ <4 RK_PA2 RK_FUNC_GPIO &pcfg_pull_none>;
+ };
+ };
+
+ vcc3v3-lcd {
+ vcc_lcd_h: vcc-lcd-h {
+ rockchip,pins =
+ <0 RK_PC2 RK_FUNC_GPIO &pcfg_pull_none>;
+ };
+ };
+
+ vcc-wifi {
+ vcc_wifi_h: vcc-wifi-h {
+ rockchip,pins =
+ <0 RK_PA0 RK_FUNC_GPIO &pcfg_pull_none>;
+ };
+ };
+};
+
+&pmu_io_domains {
+ status = "okay";
+ pmuio1-supply = <&vcc3v3_pmu>;
+ pmuio2-supply = <&vcc3v3_pmu>;
+ vccio1-supply = <&vccio_acodec>;
+ vccio3-supply = <&vccio_sd>;
+ vccio4-supply = <&vcc_1v8>;
+ vccio5-supply = <&vcc_3v3>;
+ vccio6-supply = <&vcc1v8_dvp>;
+ vccio7-supply = <&vcc_3v3>;
+};
+
+&pwm4 {
+ status = "okay";
+};
+
+&pwm6 {
+ status = "okay";
+};
+
+&pwm7 {
+ status = "okay";
+};
+
+&saradc {
+ vref-supply = <&vcc_1v8>;
+ status = "okay";
+};
+
+&sdmmc0 {
+ bus-width = <4>;
+ cap-sd-highspeed;
+ cd-gpios = <&gpio0 RK_PA4 GPIO_ACTIVE_LOW>;
+ disable-wp;
+ pinctrl-0 = <&sdmmc0_bus4 &sdmmc0_clk &sdmmc0_cmd &sdmmc0_det>;
+ pinctrl-names = "default";
+ sd-uhs-sdr104;
+ vmmc-supply = <&vcc_3v3>;
+ vqmmc-supply = <&vccio_sd>;
+ status = "okay";
+};
+
+&sdmmc1 {
+ bus-width = <4>;
+ cap-sd-highspeed;
+ cd-gpios = <&gpio2 RK_PB2 GPIO_ACTIVE_LOW>;
+ disable-wp;
+ pinctrl-0 = <&sdmmc1_bus4 &sdmmc1_cmd &sdmmc1_clk &sdmmc1_det>;
+ pinctrl-names = "default";
+ sd-uhs-sdr104;
+ vmmc-supply = <&vcc_3v3>;
+ vqmmc-supply = <&vcc1v8_dvp>;
+ status = "okay";
+};
+
+&sdmmc2 {
+ bus-width = <4>;
+ cap-sd-highspeed;
+ cap-sdio-irq;
+ keep-power-in-suspend;
+ mmc-pwrseq = <&sdio_pwrseq>;
+ non-removable;
+ pinctrl-0 = <&sdmmc2m0_bus4 &sdmmc2m0_cmd &sdmmc2m0_clk>;
+ pinctrl-names = "default";
+ vmmc-supply = <&vcc_wifi>;
+ vqmmc-supply = <&vcca1v8_pmu>;
+ status = "okay";
+};
+
+&tsadc {
+ rockchip,hw-tshut-mode = <1>;
+ rockchip,hw-tshut-polarity = <0>;
+ status = "okay";
+};
+
+&uart1 {
+ pinctrl-0 = <&uart1m1_xfer &uart1m1_ctsn &uart1m1_rtsn>;
+ pinctrl-names = "default";
+ uart-has-rtscts;
+ status = "okay";
+
+ bluetooth {
+ compatible = "realtek,rtl8821cs-bt", "realtek,rtl8723bs-bt";
+ device-wake-gpios = <&gpio4 4 GPIO_ACTIVE_HIGH>;
+ enable-gpios = <&gpio4 3 GPIO_ACTIVE_HIGH>;
+ host-wake-gpios = <&gpio4 5 GPIO_ACTIVE_HIGH>;
+ };
+};
+
+&usb_host0_xhci {
+ dr_mode = "peripheral";
+ phys = <&usb2phy0_otg>;
+ phy-names = "usb2-phy";
+ status = "okay";
+};
+
+&usb_host1_ehci {
+ status = "okay";
+};
+
+&usb_host1_ohci {
+ status = "okay";
+};
+
+&usb_host1_xhci {
+ phy-names = "usb2-phy", "usb3-phy";
+ phys = <&usb2phy1_host>, <&combphy1 PHY_TYPE_USB3>;
+ status = "okay";
+};
+
+&usb2phy0 {
+ status = "okay";
+};
+
+&usb2phy0_otg {
+ status = "okay";
+};
+
+&usb2phy1 {
+ status = "okay";
+};
+
+&usb2phy1_host {
+ status = "okay";
+};
+
+&vop {
+ assigned-clocks = <&cru DCLK_VOP0>, <&cru DCLK_VOP1>;
+ assigned-clock-parents = <&pmucru PLL_HPLL>, <&cru PLL_VPLL>;
+ status = "okay";
+};
+
+&vop_mmu {
+ status = "okay";
+};
+
+&vp0 {
+ vp0_out_hdmi: endpoint@ROCKCHIP_VOP2_EP_HDMI0 {
+ reg = <ROCKCHIP_VOP2_EP_HDMI0>;
+ remote-endpoint = <&hdmi_in_vp0>;
+ };
+};
+
+&vp1 {
+ vp1_out_dsi0: endpoint@ROCKCHIP_VOP2_EP_MIPI0 {
+ reg = <ROCKCHIP_VOP2_EP_MIPI0>;
+ remote-endpoint = <&dsi0_in_vp1>;
+ };
+};
diff --git a/dts/upstream/src/arm64/rockchip/rk3566-powkiddy-x55.dts b/dts/upstream/src/arm64/rockchip/rk3566-powkiddy-x55.dts
new file mode 100644
index 0000000..4786b19
--- /dev/null
+++ b/dts/upstream/src/arm64/rockchip/rk3566-powkiddy-x55.dts
@@ -0,0 +1,926 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+
+/dts-v1/;
+
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/input/linux-event-codes.h>
+#include <dt-bindings/leds/common.h>
+#include <dt-bindings/pinctrl/rockchip.h>
+#include <dt-bindings/soc/rockchip,vop2.h>
+#include "rk3566.dtsi"
+
+/ {
+ model = "Powkiddy x55";
+ compatible = "powkiddy,x55", "rockchip,rk3566";
+
+ aliases {
+ mmc0 = &sdhci;
+ mmc1 = &sdmmc0;
+ mmc2 = &sdmmc2;
+ mmc3 = &sdmmc1;
+ };
+
+ chosen: chosen {
+ stdout-path = "serial2:1500000n8";
+ };
+
+ adc_joystick: adc-joystick {
+ compatible = "adc-joystick";
+ io-channels = <&saradc 0>, <&saradc 1>,
+ <&saradc 2>, <&saradc 3>;
+ poll-interval = <60>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ axis@0 {
+ reg = <0>;
+ abs-flat = <30>;
+ abs-fuzz = <20>;
+ abs-range = <15 1023>;
+ linux,code = <ABS_X>;
+ };
+
+ axis@1 {
+ reg = <1>;
+ abs-flat = <30>;
+ abs-fuzz = <20>;
+ abs-range = <1023 15>;
+ linux,code = <ABS_Y>;
+ };
+
+ axis@2 {
+ reg = <2>;
+ abs-flat = <30>;
+ abs-fuzz = <20>;
+ abs-range = <15 1023>;
+ linux,code = <ABS_RX>;
+ };
+
+ axis@3 {
+ reg = <3>;
+ abs-flat = <30>;
+ abs-fuzz = <20>;
+ abs-range = <1023 15>;
+ linux,code = <ABS_RY>;
+ };
+ };
+
+ backlight: backlight {
+ compatible = "pwm-backlight";
+ power-supply = <&vcc_sys>;
+ pwms = <&pwm4 0 25000 0>;
+ };
+
+ battery: battery {
+ compatible = "simple-battery";
+ charge-full-design-microamp-hours = <4000000>;
+ charge-term-current-microamp = <300000>;
+ constant-charge-current-max-microamp = <2000000>;
+ constant-charge-voltage-max-microvolt = <4300000>;
+ factory-internal-resistance-micro-ohms = <91000>;
+ voltage-max-design-microvolt = <4138000>;
+ voltage-min-design-microvolt = <3400000>;
+
+ ocv-capacity-celsius = <20>;
+ ocv-capacity-table-0 = <4138000 100>, <4083000 95>, <4059000 90>, <4044000 85>,
+ <4030000 80>, <4020000 75>, <4006000 70>, <3972000 65>,
+ <3934000 60>, <3904000 55>, <3878000 50>, <3857000 45>,
+ <3843000 40>, <3826000 35>, <3801000 30>, <3768000 25>,
+ <3735000 20>, <3688000 15>, <3621000 10>, <3553000 5>,
+ <3400000 0>;
+ };
+
+ gpio_keys_control: gpio-keys-control {
+ compatible = "gpio-keys";
+ pinctrl-0 = <&btn_pins_ctrl>;
+ pinctrl-names = "default";
+
+ button-a {
+ gpios = <&gpio3 RK_PD3 GPIO_ACTIVE_LOW>;
+ label = "EAST";
+ linux,code = <BTN_EAST>;
+ };
+
+ button-b {
+ gpios = <&gpio3 RK_PD2 GPIO_ACTIVE_LOW>;
+ label = "SOUTH";
+ linux,code = <BTN_SOUTH>;
+ };
+
+ button-down {
+ gpios = <&gpio4 RK_PA1 GPIO_ACTIVE_LOW>;
+ label = "DPAD-DOWN";
+ linux,code = <BTN_DPAD_DOWN>;
+ };
+
+ button-l1 {
+ gpios = <&gpio3 RK_PD0 GPIO_ACTIVE_LOW>;
+ label = "TL";
+ linux,code = <BTN_TL>;
+ };
+
+ button-l2 {
+ gpios = <&gpio3 RK_PD1 GPIO_ACTIVE_LOW>;
+ label = "TL2";
+ linux,code = <BTN_TL2>;
+ };
+
+ button-left {
+ gpios = <&gpio3 RK_PD6 GPIO_ACTIVE_LOW>;
+ label = "DPAD-LEFT";
+ linux,code = <BTN_DPAD_LEFT>;
+ };
+
+ button-right {
+ gpios = <&gpio3 RK_PD7 GPIO_ACTIVE_LOW>;
+ label = "DPAD-RIGHT";
+ linux,code = <BTN_DPAD_RIGHT>;
+ };
+
+ button-select {
+ gpios = <&gpio4 RK_PA4 GPIO_ACTIVE_LOW>;
+ label = "SELECT";
+ linux,code = <BTN_SELECT>;
+ };
+
+ button-start {
+ gpios = <&gpio4 RK_PA2 GPIO_ACTIVE_LOW>;
+ label = "START";
+ linux,code = <BTN_START>;
+ };
+
+ button-thumbl {
+ gpios = <&gpio4 RK_PA7 GPIO_ACTIVE_LOW>;
+ label = "THUMBL";
+ linux,code = <BTN_THUMBL>;
+ };
+
+ button-thumbr {
+ gpios = <&gpio4 RK_PB0 GPIO_ACTIVE_LOW>;
+ label = "THUMBR";
+ linux,code = <BTN_THUMBR>;
+ };
+
+ button-r1 {
+ gpios = <&gpio3 RK_PC6 GPIO_ACTIVE_LOW>;
+ label = "TR";
+ linux,code = <BTN_TR>;
+ };
+
+ button-r2 {
+ gpios = <&gpio3 RK_PC7 GPIO_ACTIVE_LOW>;
+ label = "TR2";
+ linux,code = <BTN_TR2>;
+ };
+
+ button-up {
+ gpios = <&gpio4 RK_PA0 GPIO_ACTIVE_LOW>;
+ label = "DPAD-UP";
+ linux,code = <BTN_DPAD_UP>;
+ };
+
+ button-x {
+ gpios = <&gpio3 RK_PD5 GPIO_ACTIVE_LOW>;
+ label = "NORTH";
+ linux,code = <BTN_NORTH>;
+ };
+
+ button-y {
+ gpios = <&gpio3 RK_PD4 GPIO_ACTIVE_LOW>;
+ label = "WEST";
+ linux,code = <BTN_WEST>;
+ };
+ };
+
+ gpio_keys_vol: gpio-keys-vol {
+ compatible = "gpio-keys";
+ autorepeat;
+ pinctrl-0 = <&btn_pins_vol>;
+ pinctrl-names = "default";
+
+ button-voldown {
+ gpios = <&gpio4 RK_PA3 GPIO_ACTIVE_LOW>;
+ label = "VOLUMEDOWN";
+ linux,code = <KEY_VOLUMEDOWN>;
+ };
+
+ button-volup {
+ gpios = <&gpio4 RK_PA5 GPIO_ACTIVE_LOW>;
+ label = "VOLUMEUP";
+ linux,code = <KEY_VOLUMEUP>;
+ };
+ };
+
+ gpio_leds: gpio-leds {
+ compatible = "gpio-leds";
+ pinctrl-names = "default";
+ pinctrl-0 = <&led_pins>;
+
+ red_led: led-0 {
+ color = <LED_COLOR_ID_RED>;
+ default-state = "off";
+ gpios = <&gpio4 RK_PB4 GPIO_ACTIVE_HIGH>;
+ function = LED_FUNCTION_STATUS;
+ };
+
+ green_led: led-1 {
+ color = <LED_COLOR_ID_GREEN>;
+ default-state = "on";
+ gpios = <&gpio4 RK_PB5 GPIO_ACTIVE_HIGH>;
+ function = LED_FUNCTION_POWER;
+ };
+
+ amber_led: led-2 {
+ color = <LED_COLOR_ID_AMBER>;
+ gpios = <&gpio4 RK_PB6 GPIO_ACTIVE_HIGH>;
+ function = LED_FUNCTION_CHARGING;
+ };
+
+ };
+
+ hdmi-con {
+ compatible = "hdmi-connector";
+ ddc-i2c-bus = <&i2c5>;
+ type = "c";
+
+ port {
+ hdmi_con_in: endpoint {
+ remote-endpoint = <&hdmi_out_con>;
+ };
+ };
+ };
+
+ sdio_pwrseq: sdio-pwrseq {
+ compatible = "mmc-pwrseq-simple";
+ clocks = <&rk817 1>;
+ clock-names = "ext_clock";
+ pinctrl-0 = <&wifi_enable_h>;
+ pinctrl-names = "default";
+ post-power-on-delay-ms = <200>;
+ reset-gpios = <&gpio0 RK_PC0 GPIO_ACTIVE_LOW>;
+ };
+
+ /* Channels reversed for both headphones and speakers. */
+ sound {
+ compatible = "simple-audio-card";
+ pinctrl-0 = <&hp_det>;
+ pinctrl-names = "default";
+ simple-audio-card,name = "rk817_ext";
+ simple-audio-card,aux-devs = <&spk_amp>;
+ simple-audio-card,format = "i2s";
+ simple-audio-card,hp-det-gpio = <&gpio4 RK_PC6 GPIO_ACTIVE_HIGH>;
+ simple-audio-card,mclk-fs = <256>;
+ simple-audio-card,widgets =
+ "Microphone", "Mic Jack",
+ "Headphone", "Headphones",
+ "Speaker", "Internal Speakers";
+ simple-audio-card,routing =
+ "MICL", "Mic Jack",
+ "Headphones", "HPOL",
+ "Headphones", "HPOR",
+ "Internal Speakers", "Speaker Amp OUTL",
+ "Internal Speakers", "Speaker Amp OUTR",
+ "Speaker Amp INL", "HPOL",
+ "Speaker Amp INR", "HPOR";
+ simple-audio-card,pin-switches = "Internal Speakers";
+
+ simple-audio-card,codec {
+ sound-dai = <&rk817>;
+ };
+
+ simple-audio-card,cpu {
+ sound-dai = <&i2s1_8ch>;
+ };
+ };
+
+ spk_amp: audio-amplifier {
+ compatible = "simple-audio-amplifier";
+ enable-gpios = <&gpio4 RK_PC2 GPIO_ACTIVE_HIGH>;
+ pinctrl-0 = <&spk_amp_enable_h>;
+ pinctrl-names = "default";
+ sound-name-prefix = "Speaker Amp";
+ };
+
+ vcc5v0_host: regulator-vcc5v0-host {
+ compatible = "regulator-fixed";
+ enable-active-high;
+ gpio = <&gpio4 RK_PC4 GPIO_ACTIVE_HIGH>;
+ pinctrl-0 = <&vcc5v0_host_en>;
+ pinctrl-names = "default";
+ regulator-name = "vcc5v0_host";
+ vin-supply = <&dcdc_boost>;
+ };
+
+ vcc_lcd: regulator-vcc-lcd {
+ compatible = "regulator-fixed";
+ enable-active-high;
+ gpio = <&gpio0 RK_PC7 GPIO_ACTIVE_HIGH>;
+ pinctrl-0 = <&vcc_lcd_en>;
+ pinctrl-names = "default";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-name = "vcc_lcd";
+ };
+
+ vcc_sys: regulator-vcc-sys {
+ compatible = "regulator-fixed";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <3800000>;
+ regulator-max-microvolt = <3800000>;
+ regulator-name = "vcc_sys";
+ };
+
+ vcc_wifi: regulator-vcc-wifi {
+ compatible = "regulator-fixed";
+ gpio = <&gpio0 RK_PA0 GPIO_ACTIVE_LOW>;
+ pinctrl-0 = <&vcc_wifi_h>;
+ pinctrl-names = "default";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-name = "vcc_wifi";
+ };
+};
+
+&combphy1 {
+ status = "okay";
+};
+
+&cru {
+ assigned-clocks = <&pmucru CLK_RTC_32K>, <&cru PLL_GPLL>,
+ <&pmucru PLL_PPLL>, <&cru PLL_VPLL>;
+ assigned-clock-rates = <32768>, <1200000000>,
+ <200000000>, <126400000>;
+};
+
+&cpu0 {
+ cpu-supply = <&vdd_cpu>;
+};
+
+&cpu1 {
+ cpu-supply = <&vdd_cpu>;
+};
+
+&cpu2 {
+ cpu-supply = <&vdd_cpu>;
+};
+
+&cpu3 {
+ cpu-supply = <&vdd_cpu>;
+};
+
+&dsi_dphy0 {
+ status = "okay";
+};
+
+&dsi0 {
+ status = "okay";
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ ports {
+ dsi0_in: port@0 {
+ reg = <0>;
+ dsi0_in_vp1: endpoint {
+ remote-endpoint = <&vp1_out_dsi0>;
+ };
+ };
+
+ dsi0_out: port@1 {
+ reg = <1>;
+ mipi_out_panel: endpoint {
+ remote-endpoint = <&mipi_in_panel>;
+ };
+ };
+ };
+
+ panel: panel@0 {
+ compatible = "powkiddy,x55-panel", "himax,hx8394";
+ reg = <0>;
+ backlight = <&backlight>;
+ iovcc-supply = <&vcc_lcd>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&lcd_rst>;
+ reset-gpios = <&gpio0 RK_PD5 GPIO_ACTIVE_LOW>;
+ rotation = <270>;
+ vcc-supply = <&vcc_lcd>;
+
+ port {
+ mipi_in_panel: endpoint {
+ remote-endpoint = <&mipi_out_panel>;
+ };
+ };
+ };
+};
+
+&gpu {
+ mali-supply = <&vdd_gpu>;
+ status = "okay";
+};
+
+&hdmi {
+ ddc-i2c-bus = <&i2c5>;
+ pinctrl-0 = <&hdmitxm0_cec>;
+ pinctrl-names = "default";
+ status = "okay";
+};
+
+&hdmi_in {
+ hdmi_in_vp0: endpoint {
+ remote-endpoint = <&vp0_out_hdmi>;
+ };
+};
+
+&hdmi_out {
+ hdmi_out_con: endpoint {
+ remote-endpoint = <&hdmi_con_in>;
+ };
+};
+
+&hdmi_sound {
+ status = "okay";
+};
+
+&i2c0 {
+ status = "okay";
+
+ rk817: pmic@20 {
+ compatible = "rockchip,rk817";
+ reg = <0x20>;
+ assigned-clocks = <&cru I2S1_MCLKOUT_TX>;
+ assigned-clock-parents = <&cru CLK_I2S1_8CH_TX>;
+ clock-names = "mclk";
+ clock-output-names = "rk808-clkout1", "rk808-clkout2";
+ clocks = <&cru I2S1_MCLKOUT_TX>;
+ interrupt-parent = <&gpio0>;
+ interrupts = <RK_PA3 IRQ_TYPE_LEVEL_LOW>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&i2s1m0_mclk>, <&pmic_int_l>;
+ wakeup-source;
+ #clock-cells = <1>;
+ #sound-dai-cells = <0>;
+
+ vcc1-supply = <&vcc_sys>;
+ vcc2-supply = <&vcc_sys>;
+ vcc3-supply = <&vcc_sys>;
+ vcc4-supply = <&vcc_sys>;
+ vcc5-supply = <&vcc_sys>;
+ vcc6-supply = <&vcc_sys>;
+ vcc7-supply = <&vcc_sys>;
+ vcc8-supply = <&vcc_sys>;
+ vcc9-supply = <&dcdc_boost>;
+
+ regulators {
+ vdd_logic: DCDC_REG1 {
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <500000>;
+ regulator-max-microvolt = <1350000>;
+ regulator-ramp-delay = <6001>;
+ regulator-initial-mode = <0x2>;
+ regulator-name = "vdd_logic";
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ regulator-suspend-microvolt = <900000>;
+ };
+ };
+
+ vdd_gpu: DCDC_REG2 {
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <500000>;
+ regulator-max-microvolt = <1350000>;
+ regulator-ramp-delay = <6001>;
+ regulator-initial-mode = <0x2>;
+ regulator-name = "vdd_gpu";
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ };
+ };
+
+ vcc_ddr: DCDC_REG3 {
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-initial-mode = <0x2>;
+ regulator-name = "vcc_ddr";
+ regulator-state-mem {
+ regulator-on-in-suspend;
+ };
+ };
+
+ vcc_3v3: DCDC_REG4 {
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-initial-mode = <0x2>;
+ regulator-name = "vcc_3v3";
+ regulator-state-mem {
+ regulator-on-in-suspend;
+ regulator-suspend-microvolt = <3300000>;
+ };
+ };
+
+ vcca1v8_pmu: LDO_REG1 {
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-name = "vcca1v8_pmu";
+ regulator-state-mem {
+ regulator-on-in-suspend;
+ regulator-suspend-microvolt = <1800000>;
+ };
+ };
+
+ vdda_0v9: LDO_REG2 {
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <900000>;
+ regulator-max-microvolt = <900000>;
+ regulator-name = "vdda_0v9";
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ };
+ };
+
+ vdda0v9_pmu: LDO_REG3 {
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <900000>;
+ regulator-max-microvolt = <900000>;
+ regulator-name = "vdda0v9_pmu";
+ regulator-state-mem {
+ regulator-on-in-suspend;
+ regulator-suspend-microvolt = <900000>;
+ };
+ };
+
+ vccio_acodec: LDO_REG4 {
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-name = "vccio_acodec";
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ };
+ };
+
+ vccio_sd: LDO_REG5 {
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-name = "vccio_sd";
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ };
+ };
+
+ vcc3v3_pmu: LDO_REG6 {
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-name = "vcc3v3_pmu";
+ regulator-state-mem {
+ regulator-on-in-suspend;
+ regulator-suspend-microvolt = <3300000>;
+ };
+ };
+
+ vcc_1v8: LDO_REG7 {
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-name = "vcc_1v8";
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ };
+ };
+
+ vcc1v8_dvp: LDO_REG8 {
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-name = "vcc1v8_dvp";
+ regulator-state-mem {
+ regulator-on-in-suspend;
+ };
+ };
+
+ vcc2v8_dvp: LDO_REG9 {
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-name = "vcc2v8_dvp";
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ };
+ };
+
+ dcdc_boost: BOOST {
+ regulator-min-microvolt = <4700000>;
+ regulator-max-microvolt = <5400000>;
+ regulator-name = "boost";
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ };
+ };
+
+ otg_switch: OTG_SWITCH {
+ regulator-name = "otg_switch";
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ };
+ };
+ };
+
+ rk817_charger: charger {
+ monitored-battery = <&battery>;
+ rockchip,resistor-sense-micro-ohms = <10000>;
+ rockchip,sleep-enter-current-microamp = <150000>;
+ rockchip,sleep-filter-current-microamp = <100000>;
+ };
+
+ };
+
+ vdd_cpu: regulator@1c {
+ compatible = "tcs,tcs4525";
+ reg = <0x1c>;
+ fcs,suspend-voltage-selector = <1>;
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <712500>;
+ regulator-max-microvolt = <1390000>;
+ regulator-name = "vdd_cpu";
+ regulator-ramp-delay = <2300>;
+ vin-supply = <&vcc_sys>;
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ };
+ };
+};
+
+&i2c5 {
+ pinctrl-0 = <&i2c5m1_xfer>;
+ pinctrl-names = "default";
+ status = "okay";
+};
+
+&i2s0_8ch {
+ status = "okay";
+};
+
+&i2s1_8ch {
+ pinctrl-0 = <&i2s1m0_sclktx>, <&i2s1m0_lrcktx>, <&i2s1m0_sdi0>,
+ <&i2s1m0_sdo0>;
+ pinctrl-names = "default";
+ rockchip,trcm-sync-tx-only;
+ status = "okay";
+};
+
+&pinctrl {
+ audio-amplifier {
+ spk_amp_enable_h: spk-amp-enable-h {
+ rockchip,pins =
+ <4 RK_PC2 RK_FUNC_GPIO &pcfg_pull_none>;
+ };
+ };
+
+ gpio-control {
+ btn_pins_ctrl: btn-pins-ctrl {
+ rockchip,pins =
+ <3 RK_PC6 RK_FUNC_GPIO &pcfg_pull_up>,
+ <3 RK_PC7 RK_FUNC_GPIO &pcfg_pull_up>,
+ <3 RK_PD0 RK_FUNC_GPIO &pcfg_pull_up>,
+ <3 RK_PD1 RK_FUNC_GPIO &pcfg_pull_up>,
+ <3 RK_PD2 RK_FUNC_GPIO &pcfg_pull_up>,
+ <3 RK_PD3 RK_FUNC_GPIO &pcfg_pull_up>,
+ <3 RK_PD4 RK_FUNC_GPIO &pcfg_pull_up>,
+ <3 RK_PD5 RK_FUNC_GPIO &pcfg_pull_up>,
+ <3 RK_PD6 RK_FUNC_GPIO &pcfg_pull_up>,
+ <3 RK_PD7 RK_FUNC_GPIO &pcfg_pull_up>,
+ <4 RK_PA0 RK_FUNC_GPIO &pcfg_pull_up>,
+ <4 RK_PA1 RK_FUNC_GPIO &pcfg_pull_up>,
+ <4 RK_PA2 RK_FUNC_GPIO &pcfg_pull_up>,
+ <4 RK_PA4 RK_FUNC_GPIO &pcfg_pull_up>,
+ <4 RK_PA7 RK_FUNC_GPIO &pcfg_pull_up>,
+ <4 RK_PB0 RK_FUNC_GPIO &pcfg_pull_up>;
+ };
+
+ btn_pins_vol: btn-pins-vol {
+ rockchip,pins =
+ <4 RK_PA3 RK_FUNC_GPIO &pcfg_pull_up>,
+ <4 RK_PA5 RK_FUNC_GPIO &pcfg_pull_up>;
+ };
+ };
+
+ gpio-lcd {
+ lcd_rst: lcd-rst {
+ rockchip,pins =
+ <0 RK_PD5 RK_FUNC_GPIO &pcfg_pull_none>;
+ };
+ };
+
+ gpio-leds {
+ led_pins: led-pins {
+ rockchip,pins =
+ <4 RK_PB4 RK_FUNC_GPIO &pcfg_pull_none>,
+ <4 RK_PB5 RK_FUNC_GPIO &pcfg_pull_none>,
+ <4 RK_PB6 RK_FUNC_GPIO &pcfg_pull_none>;
+ };
+ };
+
+ hp-detect {
+ hp_det: hp-det {
+ rockchip,pins =
+ <4 RK_PC6 RK_FUNC_GPIO &pcfg_pull_up>;
+ };
+ };
+
+ pmic {
+ pmic_int_l: pmic-int-l {
+ rockchip,pins =
+ <0 RK_PA3 RK_FUNC_GPIO &pcfg_pull_up>;
+ };
+ };
+
+ sdio-pwrseq {
+ wifi_enable_h: wifi-enable-h {
+ rockchip,pins =
+ <0 RK_PC0 RK_FUNC_GPIO &pcfg_pull_none>;
+ };
+ };
+
+ usb {
+ vcc5v0_host_en: vcc5v0-host-en {
+ rockchip,pins =
+ <4 RK_PC4 RK_FUNC_GPIO &pcfg_pull_up>;
+ };
+
+ vcc5v0_otg_en: vcc5v0-otg-en {
+ rockchip,pins =
+ <4 RK_PC5 RK_FUNC_GPIO &pcfg_pull_up>;
+ };
+ };
+
+ vcc-lcd {
+ vcc_lcd_en: vcc-lcd-en {
+ rockchip,pins =
+ <0 RK_PC7 RK_FUNC_GPIO &pcfg_pull_none>;
+ };
+ };
+
+ vcc-wifi {
+ vcc_wifi_h: vcc-wifi-h {
+ rockchip,pins =
+ <0 RK_PA0 RK_FUNC_GPIO &pcfg_pull_none>;
+ };
+ };
+};
+
+&pmu_io_domains {
+ status = "okay";
+ pmuio1-supply = <&vcc3v3_pmu>;
+ pmuio2-supply = <&vcca1v8_pmu>;
+ vccio1-supply = <&vccio_acodec>;
+ vccio3-supply = <&vccio_sd>;
+ vccio4-supply = <&vcca1v8_pmu>;
+ vccio5-supply = <&vcc2v8_dvp>;
+ vccio6-supply = <&vcc1v8_dvp>;
+ vccio7-supply = <&vcc_3v3>;
+};
+
+&pwm4 {
+ status = "okay";
+};
+
+&saradc {
+ vref-supply = <&vcc_1v8>;
+ status = "okay";
+};
+
+&sdhci {
+ bus-width = <8>;
+ mmc-hs200-1_8v;
+ non-removable;
+ pinctrl-0 = <&emmc_bus8>, <&emmc_clk>, <&emmc_cmd>,
+ <&emmc_datastrobe>, <&emmc_rstnout>;
+ pinctrl-names = "default";
+ status = "okay";
+};
+
+&sdmmc0 {
+ bus-width = <4>;
+ cap-mmc-highspeed;
+ cap-sd-highspeed;
+ disable-wp;
+ pinctrl-0 = <&sdmmc0_bus4>, <&sdmmc0_clk>, <&sdmmc0_cmd>,
+ <&sdmmc0_det>;
+ pinctrl-names = "default";
+ sd-uhs-sdr104;
+ vqmmc-supply = <&vccio_sd>;
+ status = "okay";
+};
+
+&sdmmc1 {
+ bus-width = <4>;
+ cap-sd-highspeed;
+ cap-sdio-irq;
+ keep-power-in-suspend;
+ mmc-pwrseq = <&sdio_pwrseq>;
+ non-removable;
+ pinctrl-0 = <&sdmmc1_bus4>, <&sdmmc1_cmd>, <&sdmmc1_clk>;
+ pinctrl-names = "default";
+ vmmc-supply = <&vcc_wifi>;
+ status = "okay";
+};
+
+&sdmmc2 {
+ bus-width = <4>;
+ cap-mmc-highspeed;
+ cap-sd-highspeed;
+ disable-wp;
+ pinctrl-0 = <&sdmmc2m1_bus4>, <&sdmmc2m1_cmd>, <&sdmmc2m1_clk>,
+ <&sdmmc2m1_det>;
+ pinctrl-names = "default";
+ sd-uhs-sdr104;
+ vqmmc-supply = <&vcc2v8_dvp>;
+ status = "okay";
+};
+
+&tsadc {
+ rockchip,hw-tshut-mode = <1>;
+ rockchip,hw-tshut-polarity = <0>;
+ status = "okay";
+};
+
+&uart1 {
+ pinctrl-0 = <&uart1m0_xfer>, <&uart1m0_ctsn>, <&uart1m0_rtsn>;
+ pinctrl-names = "default";
+ uart-has-rtscts;
+ status = "okay";
+
+ bluetooth {
+ compatible = "realtek,rtl8821cs-bt", "realtek,rtl8723bs-bt";
+ device-wake-gpios = <&gpio0 RK_PB6 GPIO_ACTIVE_HIGH>;
+ enable-gpios = <&gpio0 RK_PC1 GPIO_ACTIVE_HIGH>;
+ host-wake-gpios = <&gpio0 RK_PB5 GPIO_ACTIVE_HIGH>;
+ };
+};
+
+&uart2 {
+ status = "okay";
+};
+
+&usb_host0_xhci {
+ phys = <&usb2phy0_otg>;
+ phy-names = "usb2-phy";
+ status = "okay";
+};
+
+&usb_host1_xhci {
+ status = "okay";
+};
+
+&usb2phy0 {
+ status = "okay";
+};
+
+&usb2phy0_otg {
+ status = "okay";
+};
+
+&usb2phy0_host {
+ phy-supply = <&vcc5v0_host>;
+ status = "okay";
+};
+
+&vop {
+ assigned-clocks = <&cru DCLK_VOP0>, <&cru DCLK_VOP1>;
+ assigned-clock-parents = <&pmucru PLL_HPLL>, <&cru PLL_VPLL>;
+ status = "okay";
+};
+
+&vop_mmu {
+ status = "okay";
+};
+
+&vp0 {
+ vp0_out_hdmi: endpoint@ROCKCHIP_VOP2_EP_HDMI0 {
+ reg = <ROCKCHIP_VOP2_EP_HDMI0>;
+ remote-endpoint = <&hdmi_in_vp0>;
+ };
+};
+
+&vp1 {
+ vp1_out_dsi0: endpoint@ROCKCHIP_VOP2_EP_MIPI0 {
+ reg = <ROCKCHIP_VOP2_EP_MIPI0>;
+ remote-endpoint = <&dsi0_in_vp1>;
+ };
+};
diff --git a/dts/upstream/src/arm64/rockchip/rk3566-quartz64-a.dts b/dts/upstream/src/arm64/rockchip/rk3566-quartz64-a.dts
index 854d02b4..59843a7 100644
--- a/dts/upstream/src/arm64/rockchip/rk3566-quartz64-a.dts
+++ b/dts/upstream/src/arm64/rockchip/rk3566-quartz64-a.dts
@@ -31,8 +31,9 @@
fan: gpio_fan {
compatible = "gpio-fan";
gpios = <&gpio0 RK_PD5 GPIO_ACTIVE_HIGH>;
- gpio-fan,speed-map = <0 0
- 4500 1>;
+ gpio-fan,speed-map =
+ < 0 0>,
+ <4500 1>;
pinctrl-names = "default";
pinctrl-0 = <&fan_en_h>;
#cooling-cells = <2>;
diff --git a/dts/upstream/src/arm64/rockchip/rk3566-radxa-cm3-io.dts b/dts/upstream/src/arm64/rockchip/rk3566-radxa-cm3-io.dts
index 1b1c67d..3ae24e3 100644
--- a/dts/upstream/src/arm64/rockchip/rk3566-radxa-cm3-io.dts
+++ b/dts/upstream/src/arm64/rockchip/rk3566-radxa-cm3-io.dts
@@ -14,6 +14,7 @@
compatible = "radxa,cm3-io", "radxa,cm3", "rockchip,rk3566";
aliases {
+ ethernet0 = &gmac1;
mmc1 = &sdmmc0;
};
diff --git a/dts/upstream/src/arm64/rockchip/rk3566-roc-pc.dts b/dts/upstream/src/arm64/rockchip/rk3566-roc-pc.dts
index 938092f..63eea27 100644
--- a/dts/upstream/src/arm64/rockchip/rk3566-roc-pc.dts
+++ b/dts/upstream/src/arm64/rockchip/rk3566-roc-pc.dts
@@ -12,6 +12,7 @@
compatible = "firefly,rk3566-roc-pc", "rockchip,rk3566";
aliases {
+ ethernet0 = &gmac1;
mmc0 = &sdmmc0;
mmc1 = &sdhci;
mmc2 = &sdmmc1;
diff --git a/dts/upstream/src/arm64/rockchip/rk3566-soquartz-blade.dts b/dts/upstream/src/arm64/rockchip/rk3566-soquartz-blade.dts
index 4e49beb..fdbf1c7 100644
--- a/dts/upstream/src/arm64/rockchip/rk3566-soquartz-blade.dts
+++ b/dts/upstream/src/arm64/rockchip/rk3566-soquartz-blade.dts
@@ -13,6 +13,10 @@
model = "PINE64 RK3566 SOQuartz on Blade carrier board";
compatible = "pine64,soquartz-blade", "pine64,soquartz", "rockchip,rk3566";
+ aliases {
+ ethernet0 = &gmac1;
+ };
+
/* labeled VCC3V0_SD in schematic to not conflict with PMIC regulator */
vcc3v0_sd: vcc3v0-sd-regulator {
compatible = "regulator-fixed";
diff --git a/dts/upstream/src/arm64/rockchip/rk3566-soquartz-cm4.dts b/dts/upstream/src/arm64/rockchip/rk3566-soquartz-cm4.dts
index cddf6cd..6ed3fa4 100644
--- a/dts/upstream/src/arm64/rockchip/rk3566-soquartz-cm4.dts
+++ b/dts/upstream/src/arm64/rockchip/rk3566-soquartz-cm4.dts
@@ -8,6 +8,10 @@
model = "Pine64 RK3566 SoQuartz with CM4-IO Carrier Board";
compatible = "pine64,soquartz-cm4io", "pine64,soquartz", "rockchip,rk3566";
+ aliases {
+ ethernet0 = &gmac1;
+ };
+
/* labeled +12v in schematic */
vcc12v_dcin: vcc12v-dcin-regulator {
compatible = "regulator-fixed";
diff --git a/dts/upstream/src/arm64/rockchip/rk3566-soquartz-model-a.dts b/dts/upstream/src/arm64/rockchip/rk3566-soquartz-model-a.dts
index 2208dbf..f2095df 100644
--- a/dts/upstream/src/arm64/rockchip/rk3566-soquartz-model-a.dts
+++ b/dts/upstream/src/arm64/rockchip/rk3566-soquartz-model-a.dts
@@ -8,6 +8,10 @@
model = "PINE64 RK3566 SOQuartz on Model A carrier board";
compatible = "pine64,soquartz-model-a", "pine64,soquartz", "rockchip,rk3566";
+ aliases {
+ ethernet0 = &gmac1;
+ };
+
/* labeled DCIN_12V in schematic */
vcc12v_dcin: vcc12v-dcin-regulator {
compatible = "regulator-fixed";
diff --git a/dts/upstream/src/arm64/rockchip/rk3566-soquartz.dtsi b/dts/upstream/src/arm64/rockchip/rk3566-soquartz.dtsi
index 63bae36..bfb7b95 100644
--- a/dts/upstream/src/arm64/rockchip/rk3566-soquartz.dtsi
+++ b/dts/upstream/src/arm64/rockchip/rk3566-soquartz.dtsi
@@ -12,7 +12,6 @@
compatible = "pine64,soquartz", "rockchip,rk3566";
aliases {
- ethernet0 = &gmac1;
mmc0 = &sdmmc0;
mmc1 = &sdhci;
mmc2 = &sdmmc1;
diff --git a/dts/upstream/src/arm64/rockchip/rk3588-coolpi-cm5-evb.dts b/dts/upstream/src/arm64/rockchip/rk3588-coolpi-cm5-evb.dts
new file mode 100644
index 0000000..a4946cd
--- /dev/null
+++ b/dts/upstream/src/arm64/rockchip/rk3588-coolpi-cm5-evb.dts
@@ -0,0 +1,216 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (c) 2023 Rockchip Electronics Co., Ltd.
+ *
+ */
+
+/dts-v1/;
+
+#include <dt-bindings/leds/common.h>
+#include "rk3588-coolpi-cm5.dtsi"
+
+/ {
+ model = "RK3588 CoolPi CM5 EVB";
+ compatible = "coolpi,pi-cm5-evb", "coolpi,pi-cm5", "rockchip,rk3588";
+
+ backlight: backlight {
+ compatible = "pwm-backlight";
+ enable-gpios = <&gpio4 RK_PA3 GPIO_ACTIVE_HIGH>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&bl_en>;
+ power-supply = <&vcc12v_dcin>;
+ pwms = <&pwm2 0 25000 0>;
+ };
+
+ leds: leds {
+ compatible = "gpio-leds";
+
+ green_led: led-0 {
+ color = <LED_COLOR_ID_GREEN>;
+ function = LED_FUNCTION_STATUS;
+ gpios = <&gpio3 RK_PB7 GPIO_ACTIVE_HIGH>;
+ linux,default-trigger = "heartbeat";
+ };
+ };
+
+ vcc12v_dcin: vcc12v-dcin-regulator {
+ compatible = "regulator-fixed";
+ regulator-name = "vcc12v_dcin";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <12000000>;
+ regulator-max-microvolt = <12000000>;
+ };
+
+ vcc5v0_sys: vcc5v0-sys-regulator {
+ compatible = "regulator-fixed";
+ regulator-name = "vcc5v0_sys";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <5000000>;
+ regulator-max-microvolt = <5000000>;
+ vin-supply = <&vcc12v_dcin>;
+ };
+
+ vcc3v3_sys: vcc3v3-sys-regulator {
+ compatible = "regulator-fixed";
+ regulator-name = "vcc3v3_sys";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ vin-supply = <&vcc12v_dcin>;
+ };
+
+ vcc3v3_lcd: vcc3v3-lcd-regulator {
+ compatible = "regulator-fixed";
+ regulator-name = "vcc3v3_lcd";
+ enable-active-high;
+ gpio = <&gpio1 RK_PC4 GPIO_ACTIVE_HIGH>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&lcdpwr_en>;
+ vin-supply = <&vcc3v3_sys>;
+ };
+
+ vcc5v0_usb_host1: vcc5v0_usb_host2: vcc5v0-usb-host-regulator {
+ compatible = "regulator-fixed";
+ regulator-name = "vcc5v0_host";
+ regulator-boot-on;
+ regulator-always-on;
+ enable-active-high;
+ regulator-min-microvolt = <5000000>;
+ regulator-max-microvolt = <5000000>;
+ gpio = <&gpio1 RK_PD5 GPIO_ACTIVE_HIGH>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&usb_host_pwren>;
+ vin-supply = <&vcc5v0_sys>;
+ };
+
+ vcc5v0_usb30_otg: vcc5v0-usb30-otg-regulator {
+ compatible = "regulator-fixed";
+ regulator-name = "vcc5v0_otg";
+ regulator-boot-on;
+ regulator-always-on;
+ enable-active-high;
+ regulator-min-microvolt = <5000000>;
+ regulator-max-microvolt = <5000000>;
+ gpios = <&gpio0 RK_PA0 GPIO_ACTIVE_HIGH>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&usb_otg_pwren>;
+ vin-supply = <&vcc5v0_sys>;
+ };
+};
+
+/* M.2 E-Key */
+&pcie2x1l1 {
+ reset-gpios = <&gpio4 RK_PA2 GPIO_ACTIVE_HIGH>;
+ vpcie3v3-supply = <&vcc3v3_sys>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pcie_clkreq &pcie_wake &pcie_rst &wifi_pwron &bt_pwron>;
+ status = "okay";
+};
+
+&pcie30phy {
+ status = "okay";
+};
+
+/* Standard pcie */
+&pcie3x2 {
+ reset-gpios = <&gpio3 RK_PB0 GPIO_ACTIVE_HIGH>;
+ vpcie3v3-supply = <&vcc3v3_sys>;
+ status = "okay";
+};
+
+/* M.2 M-Key ssd */
+&pcie3x4 {
+ num-lanes = <2>;
+ reset-gpios = <&gpio4 RK_PB6 GPIO_ACTIVE_HIGH>;
+ vpcie3v3-supply = <&vcc3v3_sys>;
+ status = "okay";
+};
+
+&pinctrl {
+ lcd {
+ lcdpwr_en: lcdpwr-en {
+ rockchip,pins = <1 RK_PC4 RK_FUNC_GPIO &pcfg_pull_down>;
+ };
+
+ bl_en: bl-en {
+ rockchip,pins = <4 RK_PA3 RK_FUNC_GPIO &pcfg_pull_none>;
+ };
+ };
+
+ usb {
+ usb_host_pwren: usb-host-pwren {
+ rockchip,pins = <1 RK_PD5 RK_FUNC_GPIO &pcfg_pull_up>;
+ };
+
+ usb_otg_pwren: usb-otg-pwren {
+ rockchip,pins = <0 RK_PA0 RK_FUNC_GPIO &pcfg_pull_up>;
+ };
+ };
+
+ wifi {
+ bt_pwron: bt-pwron {
+ rockchip,pins = <3 RK_PA6 RK_FUNC_GPIO &pcfg_pull_up>;
+ };
+
+ pcie_clkreq: pcie-clkreq {
+ rockchip,pins = <4 RK_PA0 RK_FUNC_GPIO &pcfg_pull_up>;
+ };
+
+ pcie_rst: pcie-rst {
+ rockchip,pins = <4 RK_PA2 RK_FUNC_GPIO &pcfg_pull_up>;
+ };
+
+ wifi_pwron: wifi-pwron {
+ rockchip,pins = <3 RK_PB1 RK_FUNC_GPIO &pcfg_pull_up>;
+ };
+
+ pcie_wake: pcie-wake {
+ rockchip,pins = <4 RK_PA1 RK_FUNC_GPIO &pcfg_pull_up>;
+ };
+ };
+};
+
+&pwm2 {
+ status = "okay";
+};
+
+&sata1 {
+ status = "okay";
+};
+
+&u2phy2 {
+ status = "okay";
+};
+
+&u2phy3 {
+ status = "okay";
+};
+
+&u2phy2_host {
+ phy-supply = <&vcc5v0_usb_host1>;
+ status = "okay";
+};
+
+&u2phy3_host {
+ phy-supply = <&vcc5v0_usb_host2>;
+ status = "okay";
+};
+
+&usb_host0_ehci {
+ status = "okay";
+};
+
+&usb_host0_ohci {
+ status = "okay";
+};
+
+&usb_host1_ehci {
+ status = "okay";
+};
+
+&usb_host1_ohci {
+ status = "okay";
+};
diff --git a/dts/upstream/src/arm64/rockchip/rk3588-coolpi-cm5.dtsi b/dts/upstream/src/arm64/rockchip/rk3588-coolpi-cm5.dtsi
new file mode 100644
index 0000000..cce1c8e
--- /dev/null
+++ b/dts/upstream/src/arm64/rockchip/rk3588-coolpi-cm5.dtsi
@@ -0,0 +1,650 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (c) 2023 Rockchip Electronics Co., Ltd.
+ *
+ */
+
+/dts-v1/;
+
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/pwm/pwm.h>
+#include <dt-bindings/pinctrl/rockchip.h>
+#include "rk3588.dtsi"
+
+/ {
+ compatible = "coolpi,pi-cm5", "rockchip,rk3588";
+
+ aliases {
+ mmc0 = &sdhci;
+ mmc1 = &sdmmc;
+ mmc2 = &sdio;
+ serial2 = &uart2;
+ };
+
+ analog-sound {
+ compatible = "audio-graph-card";
+ dais = <&i2s0_8ch_p0>;
+ label = "rk3588-es8316";
+ routing = "MIC2", "Mic Jack",
+ "Headphones", "HPOL",
+ "Headphones", "HPOR";
+ widgets = "Microphone", "Mic Jack",
+ "Headphone", "Headphones";
+ };
+
+ chosen {
+ stdout-path = "serial2:1500000n8";
+ };
+
+ avdd0v85_pcie20: avdd0v85-pcie20-regulator {
+ compatible = "regulator-fixed";
+ regulator-name = "avdd0v85_pcie20";
+ regulator-boot-on;
+ regulator-always-on;
+ regulator-min-microvolt = <850000>;
+ regulator-max-microvolt = <850000>;
+ vin-supply = <&vdd_0v85_s0>;
+ };
+
+ avdd1v8_pcie20: avdd1v8-pcie20-regulator {
+ compatible = "regulator-fixed";
+ regulator-name = "avdd1v8_pcie20";
+ regulator-boot-on;
+ regulator-always-on;
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ vin-supply = <&avcc_1v8_s0>;
+ };
+
+ avdd0v75_pcie30: avdd0v75-pcie30-regulator {
+ compatible = "regulator-fixed";
+ regulator-name = "avdd0v75_pcie30";
+ regulator-boot-on;
+ regulator-always-on;
+ regulator-min-microvolt = <750000>;
+ regulator-max-microvolt = <750000>;
+ vin-supply = <&avdd_0v75_s0>;
+ };
+
+ pcie30_avdd1v8: avdd1v8-pcie30-regulator {
+ compatible = "regulator-fixed";
+ regulator-name = "pcie30_avdd1v8";
+ regulator-boot-on;
+ regulator-always-on;
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ vin-supply = <&avcc_1v8_s0>;
+ };
+};
+
+&combphy0_ps {
+ status = "okay";
+};
+
+&combphy1_ps {
+ status = "okay";
+};
+
+&combphy2_psu {
+ status = "okay";
+};
+
+&cpu_b0 {
+ cpu-supply = <&vdd_cpu_big0_s0>;
+};
+
+&cpu_b1 {
+ cpu-supply = <&vdd_cpu_big0_s0>;
+};
+
+&cpu_b2 {
+ cpu-supply = <&vdd_cpu_big1_s0>;
+};
+
+&cpu_b3 {
+ cpu-supply = <&vdd_cpu_big1_s0>;
+};
+
+&cpu_l0 {
+ cpu-supply = <&vdd_cpu_lit_s0>;
+};
+
+&cpu_l1 {
+ cpu-supply = <&vdd_cpu_lit_s0>;
+};
+
+&cpu_l2 {
+ cpu-supply = <&vdd_cpu_lit_s0>;
+};
+
+&cpu_l3 {
+ cpu-supply = <&vdd_cpu_lit_s0>;
+};
+
+&gmac0 {
+ clock_in_out = "output";
+ phy-handle = <&rgmii_phy>;
+ phy-mode = "rgmii-rxid";
+ pinctrl-0 = <&gmac0_miim
+ &gmac0_tx_bus2
+ &gmac0_rx_bus2
+ &gmac0_rgmii_clk
+ &gmac0_rgmii_bus>;
+ pinctrl-names = "default";
+ rx_delay = <0x00>;
+ tx_delay = <0x43>;
+ status = "okay";
+};
+
+&i2c0 {
+ pinctrl-0 = <&i2c0m2_xfer>;
+ status = "okay";
+
+ vdd_cpu_big0_s0: regulator@42 {
+ compatible = "rockchip,rk8602";
+ reg = <0x42>;
+ fcs,suspend-voltage-selector = <1>;
+ regulator-name = "vdd_cpu_big0_s0";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <550000>;
+ regulator-max-microvolt = <1050000>;
+ regulator-ramp-delay = <2300>;
+ vin-supply = <&vcc5v0_sys>;
+
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ };
+ };
+
+ vdd_cpu_big1_s0: regulator@43 {
+ compatible = "rockchip,rk8603", "rockchip,rk8602";
+ reg = <0x43>;
+ fcs,suspend-voltage-selector = <1>;
+ regulator-name = "vdd_cpu_big1_s0";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <550000>;
+ regulator-max-microvolt = <1050000>;
+ regulator-ramp-delay = <2300>;
+ vin-supply = <&vcc5v0_sys>;
+
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ };
+ };
+};
+
+&i2c2 {
+ status = "okay";
+
+ vdd_npu_s0: regulator@42 {
+ compatible = "rockchip,rk8602";
+ reg = <0x42>;
+ fcs,suspend-voltage-selector = <1>;
+ regulator-name = "vdd_npu_s0";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <550000>;
+ regulator-max-microvolt = <950000>;
+ regulator-ramp-delay = <2300>;
+ vin-supply = <&vcc5v0_sys>;
+
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ };
+ };
+};
+
+&i2c6 {
+ status = "okay";
+
+ hym8563: rtc@51 {
+ compatible = "haoyu,hym8563";
+ reg = <0x51>;
+ interrupt-parent = <&gpio0>;
+ interrupts = <RK_PD4 IRQ_TYPE_LEVEL_LOW>;
+ #clock-cells = <0>;
+ clock-output-names = "hym8563";
+ pinctrl-names = "default";
+ pinctrl-0 = <&hym8563_int>;
+ wakeup-source;
+ };
+};
+
+&i2c7 {
+ pinctrl-0 = <&i2c7m0_xfer>;
+ status = "okay";
+
+ es8316: audio-codec@11 {
+ compatible = "everest,es8316";
+ reg = <0x11>;
+ assigned-clocks = <&cru I2S0_8CH_MCLKOUT>;
+ assigned-clock-rates = <12288000>;
+ clocks = <&cru I2S0_8CH_MCLKOUT>;
+ clock-names = "mclk";
+ #sound-dai-cells = <0>;
+
+ port {
+ es8316_p0_0: endpoint {
+ remote-endpoint = <&i2s0_8ch_p0_0>;
+ };
+ };
+ };
+};
+
+&i2s0_8ch {
+ pinctrl-0 = <&i2s0_lrck
+ &i2s0_mclk
+ &i2s0_sclk
+ &i2s0_sdi0
+ &i2s0_sdo0>;
+ status = "okay";
+
+ i2s0_8ch_p0: port {
+ i2s0_8ch_p0_0: endpoint {
+ dai-format = "i2s";
+ mclk-fs = <256>;
+ remote-endpoint = <&es8316_p0_0>;
+ };
+ };
+};
+
+&mdio0 {
+ rgmii_phy: ethernet-phy@1 {
+ /* YT8531C/H */
+ compatible = "ethernet-phy-ieee802.3-c22";
+ reg = <0x1>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&yt8531_rst>;
+ reset-assert-us = <20000>;
+ reset-deassert-us = <100000>;
+ reset-gpios = <&gpio4 RK_PB3 GPIO_ACTIVE_LOW>;
+ };
+};
+
+/* ethernet */
+&pcie2x1l2 {
+ reset-gpios = <&gpio3 RK_PD1 GPIO_ACTIVE_HIGH>;
+ vpcie3v3-supply = <&vcc3v3_sys>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&yt6801_isolate>;
+ status = "okay";
+};
+
+&pinctrl {
+ hym8563 {
+ hym8563_int: hym8563-int {
+ rockchip,pins = <0 RK_PD4 RK_FUNC_GPIO &pcfg_pull_up>;
+ };
+ };
+
+ yt6801 {
+ yt6801_isolate: yt6801-isolate {
+ rockchip,pins = <1 RK_PA4 RK_FUNC_GPIO &pcfg_pull_up>;
+ };
+ };
+
+ yt8531 {
+ yt8531_rst: yt8531-rst {
+ rockchip,pins = <4 RK_PB3 RK_FUNC_GPIO &pcfg_pull_none>;
+ };
+ };
+};
+
+&saradc {
+ vref-supply = <&vcc_1v8_s0>;
+ status = "okay";
+};
+
+&sdhci {
+ bus-width = <8>;
+ max-frequency = <200000000>;
+ mmc-hs400-1_8v;
+ mmc-hs400-enhanced-strobe;
+ no-sdio;
+ no-sd;
+ non-removable;
+ status = "okay";
+};
+
+&sdmmc {
+ bus-width = <4>;
+ cap-mmc-highspeed;
+ cap-sd-highspeed;
+ disable-wp;
+ max-frequency = <150000000>;
+ no-sdio;
+ no-mmc;
+ sd-uhs-sdr104;
+ vqmmc-supply = <&vccio_sd_s0>;
+ status = "okay";
+};
+
+&spi2 {
+ assigned-clocks = <&cru CLK_SPI2>;
+ assigned-clock-rates = <200000000>;
+ num-cs = <1>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&spi2m2_cs0 &spi2m2_pins>;
+ status = "okay";
+
+ pmic@0 {
+ compatible = "rockchip,rk806";
+ reg = <0x0>;
+ interrupt-parent = <&gpio0>;
+ interrupts = <7 IRQ_TYPE_LEVEL_LOW>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pmic_pins>, <&rk806_dvs1_null>,
+ <&rk806_dvs2_null>, <&rk806_dvs3_null>;
+ spi-max-frequency = <1000000>;
+ vcc1-supply = <&vcc5v0_sys>;
+ vcc2-supply = <&vcc5v0_sys>;
+ vcc3-supply = <&vcc5v0_sys>;
+ vcc4-supply = <&vcc5v0_sys>;
+ vcc5-supply = <&vcc5v0_sys>;
+ vcc6-supply = <&vcc5v0_sys>;
+ vcc7-supply = <&vcc5v0_sys>;
+ vcc8-supply = <&vcc5v0_sys>;
+ vcc9-supply = <&vcc5v0_sys>;
+ vcc10-supply = <&vcc5v0_sys>;
+ vcc11-supply = <&vcc_2v0_pldo_s3>;
+ vcc12-supply = <&vcc5v0_sys>;
+ vcc13-supply = <&vcc_2v0_pldo_s3>;
+ vcc14-supply = <&vcc_2v0_pldo_s3>;
+ vcca-supply = <&vcc5v0_sys>;
+
+ rk806_dvs1_null: dvs1-null-pins {
+ pins = "gpio_pwrctrl2";
+ function = "pin_fun0";
+ };
+
+ rk806_dvs2_null: dvs2-null-pins {
+ pins = "gpio_pwrctrl2";
+ function = "pin_fun0";
+ };
+
+ rk806_dvs3_null: dvs3-null-pins {
+ pins = "gpio_pwrctrl3";
+ function = "pin_fun0";
+ };
+
+ regulators {
+ vdd_gpu_s0: vdd_gpu_mem_s0: dcdc-reg1 {
+ regulator-boot-on;
+ regulator-min-microvolt = <550000>;
+ regulator-max-microvolt = <950000>;
+ regulator-ramp-delay = <12500>;
+ regulator-name = "vdd_gpu_s0";
+ regulator-enable-ramp-delay = <400>;
+
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ };
+ };
+
+ vdd_cpu_lit_s0: vdd_cpu_lit_mem_s0: dcdc-reg2 {
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <550000>;
+ regulator-max-microvolt = <950000>;
+ regulator-ramp-delay = <12500>;
+ regulator-name = "vdd_cpu_lit_s0";
+
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ };
+ };
+
+ vdd_log_s0: dcdc-reg3 {
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <675000>;
+ regulator-max-microvolt = <750000>;
+ regulator-ramp-delay = <12500>;
+ regulator-name = "vdd_log_s0";
+
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ regulator-suspend-microvolt = <750000>;
+ };
+ };
+
+ vdd_vdenc_s0: vdd_vdenc_mem_s0: dcdc-reg4 {
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <550000>;
+ regulator-max-microvolt = <950000>;
+ regulator-ramp-delay = <12500>;
+ regulator-name = "vdd_vdenc_s0";
+
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ };
+ };
+
+ vdd_ddr_s0: dcdc-reg5 {
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <675000>;
+ regulator-max-microvolt = <900000>;
+ regulator-ramp-delay = <12500>;
+ regulator-name = "vdd_ddr_s0";
+
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ regulator-suspend-microvolt = <850000>;
+ };
+ };
+
+ vdd2_ddr_s3: dcdc-reg6 {
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-name = "vdd2_ddr_s3";
+
+ regulator-state-mem {
+ regulator-on-in-suspend;
+ };
+ };
+
+ vcc_2v0_pldo_s3: dcdc-reg7 {
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <2000000>;
+ regulator-max-microvolt = <2000000>;
+ regulator-ramp-delay = <12500>;
+ regulator-name = "vdd_2v0_pldo_s3";
+
+ regulator-state-mem {
+ regulator-on-in-suspend;
+ regulator-suspend-microvolt = <2000000>;
+ };
+ };
+
+ vcc_3v3_s3: dcdc-reg8 {
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-name = "vcc_3v3_s3";
+
+ regulator-state-mem {
+ regulator-on-in-suspend;
+ regulator-suspend-microvolt = <3300000>;
+ };
+ };
+
+ vddq_ddr_s0: dcdc-reg9 {
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-name = "vddq_ddr_s0";
+
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ };
+ };
+
+ vcc_1v8_s3: dcdc-reg10 {
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-name = "vcc_1v8_s3";
+
+ regulator-state-mem {
+ regulator-on-in-suspend;
+ regulator-suspend-microvolt = <1800000>;
+ };
+ };
+
+ avcc_1v8_s0: pldo-reg1 {
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-name = "avcc_1v8_s0";
+
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ };
+ };
+
+ vcc_1v8_s0: pldo-reg2 {
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-name = "vcc_1v8_s0";
+
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ regulator-suspend-microvolt = <1800000>;
+ };
+ };
+
+ avdd_1v2_s0: pldo-reg3 {
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <1200000>;
+ regulator-max-microvolt = <1200000>;
+ regulator-name = "avdd_1v2_s0";
+
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ };
+ };
+
+ vcc_3v3_s0: pldo-reg4 {
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-ramp-delay = <12500>;
+ regulator-name = "vcc_3v3_s0";
+
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ };
+ };
+
+ vccio_sd_s0: pldo-reg5 {
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-ramp-delay = <12500>;
+ regulator-name = "vccio_sd_s0";
+
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ };
+ };
+
+ pldo6_s3: pldo-reg6 {
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-name = "pldo6_s3";
+
+ regulator-state-mem {
+ regulator-on-in-suspend;
+ regulator-suspend-microvolt = <1800000>;
+ };
+ };
+
+ vdd_0v75_s3: nldo-reg1 {
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <750000>;
+ regulator-max-microvolt = <750000>;
+ regulator-name = "vdd_0v75_s3";
+
+ regulator-state-mem {
+ regulator-on-in-suspend;
+ regulator-suspend-microvolt = <750000>;
+ };
+ };
+
+ vdd_ddr_pll_s0: nldo-reg2 {
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <850000>;
+ regulator-max-microvolt = <850000>;
+ regulator-name = "vdd_ddr_pll_s0";
+
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ regulator-suspend-microvolt = <850000>;
+ };
+ };
+
+ avdd_0v75_s0: nldo-reg3 {
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <750000>;
+ regulator-max-microvolt = <750000>;
+ regulator-name = "avdd_0v75_s0";
+
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ };
+ };
+
+ vdd_0v85_s0: nldo-reg4 {
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <850000>;
+ regulator-max-microvolt = <850000>;
+ regulator-name = "vdd_0v85_s0";
+
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ };
+ };
+
+ vdd_0v75_s0: nldo-reg5 {
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <750000>;
+ regulator-max-microvolt = <750000>;
+ regulator-name = "vdd_0v75_s0";
+
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ };
+ };
+ };
+ };
+};
+
+&tsadc {
+ status = "okay";
+};
+
+&uart2 {
+ pinctrl-0 = <&uart2m0_xfer>;
+ status = "okay";
+};
diff --git a/dts/upstream/src/arm64/rockchip/rk3588-edgeble-neu6a-io.dts b/dts/upstream/src/arm64/rockchip/rk3588-edgeble-neu6a-io.dts
index b515438..be6a4f4 100644
--- a/dts/upstream/src/arm64/rockchip/rk3588-edgeble-neu6a-io.dts
+++ b/dts/upstream/src/arm64/rockchip/rk3588-edgeble-neu6a-io.dts
@@ -12,10 +12,6 @@
compatible = "edgeble,neural-compute-module-6a-io",
"edgeble,neural-compute-module-6a", "rockchip,rk3588";
- aliases {
- serial2 = &uart2;
- };
-
chosen {
stdout-path = "serial2:1500000n8";
};
diff --git a/dts/upstream/src/arm64/rockchip/rk3588-edgeble-neu6b-io.dts b/dts/upstream/src/arm64/rockchip/rk3588-edgeble-neu6b-io.dts
index 9933765..070baeb 100644
--- a/dts/upstream/src/arm64/rockchip/rk3588-edgeble-neu6b-io.dts
+++ b/dts/upstream/src/arm64/rockchip/rk3588-edgeble-neu6b-io.dts
@@ -9,13 +9,9 @@
/ {
model = "Edgeble Neu6B IO Board";
- compatible = "edgeble,neural-compute-module-6b-io",
+ compatible = "edgeble,neural-compute-module-6a-io",
"edgeble,neural-compute-module-6b", "rockchip,rk3588";
- aliases {
- serial2 = &uart2;
- };
-
chosen {
stdout-path = "serial2:1500000n8";
};
diff --git a/dts/upstream/src/arm64/rockchip/rk3588-evb1-v10.dts b/dts/upstream/src/arm64/rockchip/rk3588-evb1-v10.dts
index b9d789d..de30c26 100644
--- a/dts/upstream/src/arm64/rockchip/rk3588-evb1-v10.dts
+++ b/dts/upstream/src/arm64/rockchip/rk3588-evb1-v10.dts
@@ -16,8 +16,8 @@
compatible = "rockchip,rk3588-evb1-v10", "rockchip,rk3588";
aliases {
+ ethernet0 = &gmac0;
mmc0 = &sdhci;
- serial2 = &uart2;
};
chosen {
@@ -56,6 +56,63 @@
};
};
+ analog-sound {
+ compatible = "simple-audio-card";
+ pinctrl-names = "default";
+ pinctrl-0 = <&hp_detect>;
+ simple-audio-card,name = "RK3588 EVB1 Audio";
+ simple-audio-card,aux-devs = <&_headphone>, <&_speaker>;
+ simple-audio-card,bitclock-master = <&masterdai>;
+ simple-audio-card,format = "i2s";
+ simple-audio-card,frame-master = <&masterdai>;
+ simple-audio-card,hp-det-gpio = <&gpio1 RK_PD5 GPIO_ACTIVE_LOW>;
+ simple-audio-card,mclk-fs = <256>;
+ simple-audio-card,pin-switches = "Headphones", "Speaker";
+ simple-audio-card,routing =
+ "Speaker Amplifier INL", "LOUT2",
+ "Speaker Amplifier INR", "ROUT2",
+ "Speaker", "Speaker Amplifier OUTL",
+ "Speaker", "Speaker Amplifier OUTR",
+ "Headphones Amplifier INL", "LOUT1",
+ "Headphones Amplifier INR", "ROUT1",
+ "Headphones", "Headphones Amplifier OUTL",
+ "Headphones", "Headphones Amplifier OUTR",
+ "LINPUT1", "Onboard Microphone",
+ "RINPUT1", "Onboard Microphone",
+ "LINPUT2", "Microphone Jack",
+ "RINPUT2", "Microphone Jack";
+ simple-audio-card,widgets =
+ "Microphone", "Microphone Jack",
+ "Microphone", "Onboard Microphone",
+ "Headphone", "Headphones",
+ "Speaker", "Speaker";
+
+ simple-audio-card,cpu {
+ sound-dai = <&i2s0_8ch>;
+ };
+
+ masterdai: simple-audio-card,codec {
+ sound-dai = <&es8388>;
+ system-clock-frequency = <12288000>;
+ };
+ };
+
+ amp_headphone: headphone-amplifier {
+ compatible = "simple-audio-amplifier";
+ enable-gpios = <&gpio1 RK_PD2 GPIO_ACTIVE_HIGH>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&headphone_amplifier_en>;
+ sound-name-prefix = "Headphones Amplifier";
+ };
+
+ amp_speaker: speaker-amplifier {
+ compatible = "simple-audio-amplifier";
+ enable-gpios = <&gpio1 RK_PD3 GPIO_ACTIVE_HIGH>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&speaker_amplifier_en>;
+ sound-name-prefix = "Speaker Amplifier";
+ };
+
backlight: backlight {
compatible = "pwm-backlight";
power-supply = <&vcc12v_dcin>;
@@ -240,6 +297,32 @@
};
};
+&i2c7 {
+ status = "okay";
+
+ es8388: audio-codec@11 {
+ compatible = "everest,es8388";
+ reg = <0x11>;
+ clocks = <&cru I2S0_8CH_MCLKOUT>;
+ assigned-clocks = <&cru I2S0_8CH_MCLKOUT>;
+ assigned-clock-rates = <12288000>;
+ AVDD-supply = <&avcc_1v8_codec_s0>;
+ DVDD-supply = <&avcc_1v8_codec_s0>;
+ HPVDD-supply = <&vcc_3v3_s0>;
+ PVDD-supply = <&vcc_3v3_s0>;
+ #sound-dai-cells = <0>;
+ };
+};
+
+&i2s0_8ch {
+ pinctrl-0 = <&i2s0_lrck
+ &i2s0_mclk
+ &i2s0_sclk
+ &i2s0_sdi0
+ &i2s0_sdo0>;
+ status = "okay";
+};
+
&mdio0 {
rgmii_phy: ethernet-phy@1 {
/* RTL8211F */
@@ -273,6 +356,20 @@
};
&pinctrl {
+ audio {
+ hp_detect: headphone-detect {
+ rockchip,pins = <1 RK_PD5 RK_FUNC_GPIO &pcfg_pull_none>;
+ };
+
+ headphone_amplifier_en: headphone-amplifier-en {
+ rockchip,pins = <1 RK_PD2 RK_FUNC_GPIO &pcfg_pull_none>;
+ };
+
+ speaker_amplifier_en: speaker-amplifier-en {
+ rockchip,pins = <1 RK_PD3 RK_FUNC_GPIO &pcfg_pull_none>;
+ };
+ };
+
rtl8111 {
rtl8111_isolate: rtl8111-isolate {
rockchip,pins = <1 RK_PA4 RK_FUNC_GPIO &pcfg_pull_up>;
@@ -351,6 +448,7 @@
<&rk806_dvs2_null>, <&rk806_dvs3_null>;
pinctrl-names = "default";
spi-max-frequency = <1000000>;
+ system-power-controller;
vcc1-supply = <&vcc5v0_sys>;
vcc2-supply = <&vcc5v0_sys>;
diff --git a/dts/upstream/src/arm64/rockchip/rk3588-jaguar.dts b/dts/upstream/src/arm64/rockchip/rk3588-jaguar.dts
new file mode 100644
index 0000000..39d6500
--- /dev/null
+++ b/dts/upstream/src/arm64/rockchip/rk3588-jaguar.dts
@@ -0,0 +1,802 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (c) 2023 Theobroma Systems Design und Consulting GmbH
+ */
+
+/dts-v1/;
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/input/input.h>
+#include <dt-bindings/leds/common.h>
+#include <dt-bindings/pinctrl/rockchip.h>
+#include <dt-bindings/usb/pd.h>
+#include "rk3588.dtsi"
+
+/ {
+ model = "Theobroma Systems RK3588-SBC Jaguar";
+ compatible = "tsd,rk3588-jaguar", "rockchip,rk3588";
+
+ adc-keys {
+ compatible = "adc-keys";
+ io-channels = <&saradc 0>;
+ io-channel-names = "buttons";
+ keyup-threshold-microvolt = <1800000>;
+ poll-interval = <100>;
+
+ /* Can be controlled through SW2 but also GPIO1 on CP2102 on P20 */
+ button-bios-disable {
+ label = "BIOS_DISABLE";
+ linux,code = <KEY_VENDOR>;
+ press-threshold-microvolt = <0>;
+ };
+ };
+
+ aliases {
+ ethernet0 = &gmac0;
+ mmc0 = &sdhci;
+ mmc1 = &sdmmc;
+ rtc0 = &rtc_twi;
+ };
+
+ chosen {
+ stdout-path = "serial2:115200n8";
+ };
+
+ /* DCIN is 12-24V but standard is 12V */
+ dc_12v: dc-12v-regulator {
+ compatible = "regulator-fixed";
+ regulator-name = "dc_12v";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <12000000>;
+ regulator-max-microvolt = <12000000>;
+ };
+
+ emmc_pwrseq: emmc-pwrseq {
+ compatible = "mmc-pwrseq-emmc";
+ pinctrl-0 = <&emmc_reset>;
+ pinctrl-names = "default";
+ reset-gpios = <&gpio2 RK_PA3 GPIO_ACTIVE_HIGH>;
+ };
+
+ leds {
+ compatible = "gpio-leds";
+ pinctrl-names = "default";
+ pinctrl-0 = <&led1_pin>;
+
+ /* LED1 on PCB */
+ led-1 {
+ gpios = <&gpio1 RK_PD4 GPIO_ACTIVE_HIGH>;
+ function = LED_FUNCTION_HEARTBEAT;
+ linux,default-trigger = "heartbeat";
+ color = <LED_COLOR_ID_AMBER>;
+ };
+ };
+
+ pps {
+ compatible = "pps-gpio";
+ gpios = <&gpio0 RK_PD5 GPIO_ACTIVE_HIGH>;
+ };
+
+ vcc_1v1_nldo_s3: vcc-1v1-nldo-s3-regulator {
+ compatible = "regulator-fixed";
+ regulator-name = "vcc_1v1_nldo_s3";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <1100000>;
+ regulator-max-microvolt = <1100000>;
+ vin-supply = <&vcc5v0_sys>;
+ };
+
+ vcc_1v2_s3: vcc-1v2-s3-regulator {
+ compatible = "regulator-fixed";
+ regulator-name = "vcc_1v2_s3";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <1200000>;
+ regulator-max-microvolt = <1200000>;
+ vin-supply = <&vcc5v0_sys>;
+ };
+
+ /* Exposed on P14 and P15 */
+ vcc_2v8_s3: vcc-2v8-s3-regulator {
+ compatible = "regulator-fixed";
+ regulator-name = "vcc_2v8_s3";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <2800000>;
+ regulator-max-microvolt = <2800000>;
+ vin-supply = <&vcc_3v3_s3>;
+ };
+
+ vcc_5v0_usb_a: vcc-5v0-usb-a-regulator {
+ compatible = "regulator-fixed";
+ regulator-name = "usb_a_vcc";
+ regulator-min-microvolt = <5000000>;
+ regulator-max-microvolt = <5000000>;
+ vin-supply = <&vcc5v0_sys>;
+ gpio = <&gpio1 RK_PB4 GPIO_ACTIVE_HIGH>;
+ enable-active-high;
+ };
+
+ vcc_5v0_usb_c1: vcc-5v0-usb-c1-regulator {
+ compatible = "regulator-fixed";
+ regulator-name = "5v_usbc1";
+ regulator-min-microvolt = <5000000>;
+ regulator-max-microvolt = <5000000>;
+ vin-supply = <&vcc5v0_usb>;
+ gpio = <&gpio4 RK_PB5 GPIO_ACTIVE_HIGH>;
+ enable-active-high;
+ };
+
+ vcc_5v0_usb_c2: vcc-5v0-usb-c2-regulator {
+ compatible = "regulator-fixed";
+ regulator-name = "5v_usbc2";
+ regulator-min-microvolt = <5000000>;
+ regulator-max-microvolt = <5000000>;
+ vin-supply = <&vcc5v0_usb>;
+ gpio = <&gpio4 RK_PB6 GPIO_ACTIVE_HIGH>;
+ enable-active-high;
+ };
+
+ vcc3v3_mdot2: vcc3v3-mdot2-regulator {
+ compatible = "regulator-fixed";
+ regulator-name = "vcc3v3_mdot2";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ vin-supply = <&dc_12v>;
+ };
+
+ vcc5v0_sys: vcc5v0-sys-regulator {
+ compatible = "regulator-fixed";
+ regulator-name = "vcc5v0_sys";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <5000000>;
+ regulator-max-microvolt = <5000000>;
+ vin-supply = <&dc_12v>;
+ };
+
+ vcc5v0_usb: vcc5v0-usb-regulator {
+ compatible = "regulator-fixed";
+ regulator-name = "vcc5v0_usb";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <5000000>;
+ regulator-max-microvolt = <5000000>;
+ vin-supply = <&vcc5v0_sys>;
+ };
+};
+
+&combphy1_ps {
+ status = "okay";
+};
+
+&cpu_b0 {
+ cpu-supply = <&vdd_cpu_big0_s0>;
+};
+
+&cpu_b1 {
+ cpu-supply = <&vdd_cpu_big0_s0>;
+};
+
+&cpu_b2 {
+ cpu-supply = <&vdd_cpu_big1_s0>;
+};
+
+&cpu_b3 {
+ cpu-supply = <&vdd_cpu_big1_s0>;
+};
+
+&cpu_l0 {
+ cpu-supply = <&vdd_cpu_lit_s0>;
+};
+
+&cpu_l1 {
+ cpu-supply = <&vdd_cpu_lit_s0>;
+};
+
+&cpu_l2 {
+ cpu-supply = <&vdd_cpu_lit_s0>;
+};
+
+&cpu_l3 {
+ cpu-supply = <&vdd_cpu_lit_s0>;
+};
+
+&gmac0 {
+ clock_in_out = "output";
+ phy-handle = <&rgmii_phy>;
+ phy-mode = "rgmii";
+ phy-supply = <&vcc_1v2_s3>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&gmac0_miim
+ &gmac0_rx_bus2
+ &gmac0_tx_bus2
+ &gmac0_rgmii_clk
+ &gmac0_rgmii_bus
+ ð0_pins
+ ð_reset>;
+ tx_delay = <0x10>;
+ rx_delay = <0x10>;
+ snps,reset-gpio = <&gpio4 RK_PC3 GPIO_ACTIVE_LOW>;
+ snps,reset-active-low;
+ snps,reset-delays-us = <0 10000 100000>;
+
+ status = "okay";
+};
+
+&gpio1 {
+ mdot2e-w-disable1-n-hog {
+ gpios = <RK_PB1 GPIO_ACTIVE_LOW>;
+ output-low;
+ line-name = "m.2 E-key W_DISABLE1#";
+ gpio-hog;
+ };
+};
+
+&gpio4 {
+ mdot2e-w-disable2-n-hog {
+ gpios = <RK_PC1 GPIO_ACTIVE_LOW>;
+ output-low;
+ line-name = "m.2 E-key W_DISABLE2#";
+ gpio-hog;
+ };
+};
+
+&i2c0 {
+ pinctrl-0 = <&i2c0m2_xfer>;
+ status = "okay";
+
+ fan@18 {
+ compatible = "ti,amc6821";
+ reg = <0x18>;
+ };
+
+ vdd_npu_s0: regulator@42 {
+ compatible = "rockchip,rk8602";
+ reg = <0x42>;
+ fcs,suspend-voltage-selector = <1>;
+ regulator-name = "vdd_npu_s0";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <550000>;
+ regulator-max-microvolt = <950000>;
+ regulator-ramp-delay = <2300>;
+ vin-supply = <&vcc5v0_sys>;
+
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ };
+ };
+
+ vdd_cpu_big1_s0: regulator@43 {
+ compatible = "rockchip,rk8603", "rockchip,rk8602";
+ reg = <0x43>;
+ fcs,suspend-voltage-selector = <1>;
+ regulator-name = "vdd_cpu_big1_s0";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <550000>;
+ regulator-max-microvolt = <1050000>;
+ regulator-ramp-delay = <2300>;
+ vin-supply = <&vcc5v0_sys>;
+
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ };
+ };
+
+ rtc_twi: rtc@6f {
+ compatible = "isil,isl1208";
+ reg = <0x6f>;
+ };
+};
+
+&i2c1 {
+ pinctrl-0 = <&i2c1m4_xfer>;
+};
+
+&i2c6 {
+ pinctrl-0 = <&i2c6m4_xfer>;
+};
+
+&i2c7 {
+ status = "okay";
+
+ /* SE050 Secure Element at 0x48; GPIO1_A4 for enable pin */
+
+ /* Also on 0x55 */
+ eeprom@54 {
+ compatible = "st,24c04", "atmel,24c04";
+ reg = <0x54>;
+ pagesize = <16>;
+ vcc-supply = <&vcc_3v3_s3>;
+ };
+};
+
+&i2c8 {
+ pinctrl-0 = <&i2c8m2_xfer>;
+ status = "okay";
+
+ vdd_cpu_big0_s0: regulator@42 {
+ compatible = "rockchip,rk8602";
+ reg = <0x42>;
+ fcs,suspend-voltage-selector = <1>;
+ regulator-name = "vdd_cpu_big0_s0";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <550000>;
+ regulator-max-microvolt = <1050000>;
+ regulator-ramp-delay = <2300>;
+ vin-supply = <&vcc5v0_sys>;
+
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ };
+ };
+};
+
+&mdio0 {
+ rgmii_phy: ethernet-phy@6 {
+ /* KSZ9031 or KSZ9131 */
+ compatible = "ethernet-phy-ieee802.3-c22";
+ reg = <0x6>;
+ clocks = <&cru REFCLKO25M_ETH0_OUT>;
+ };
+};
+
+&pcie2x1l0 {
+ reset-gpios = <&gpio4 RK_PB3 GPIO_ACTIVE_HIGH>; /* WIFI_PERST0# */
+ vpcie3v3-supply = <&vcc3v3_mdot2>;
+ status = "okay";
+};
+
+&pinctrl {
+ emmc {
+ emmc_reset: emmc-reset {
+ rockchip,pins = <2 RK_PA3 RK_FUNC_GPIO &pcfg_pull_none>;
+ };
+ };
+
+ ethernet {
+ eth_reset: eth-reset {
+ rockchip,pins = <4 RK_PC3 RK_FUNC_GPIO &pcfg_pull_none>;
+ };
+ };
+
+ leds {
+ led1_pin: led1-pin {
+ rockchip,pins = <1 RK_PD4 RK_FUNC_GPIO &pcfg_pull_none>;
+ };
+ };
+};
+
+&saradc {
+ vref-supply = <&vcc_1v8_s0>;
+ status = "okay";
+};
+
+&sdhci {
+ bus-width = <8>;
+ cap-mmc-highspeed;
+ mmc-ddr-1_8v;
+ mmc-hs200-1_8v;
+ mmc-hs400-1_8v;
+ mmc-hs400-enhanced-strobe;
+ mmc-pwrseq = <&emmc_pwrseq>;
+ no-sdio;
+ no-sd;
+ non-removable;
+ pinctrl-names = "default";
+ pinctrl-0 = <&emmc_bus8 &emmc_cmd &emmc_clk &emmc_data_strobe>;
+ supports-cqe;
+ vmmc-supply = <&vcc_3v3_s3>;
+ vqmmc-supply = <&vcc_1v8_s3>;
+ status = "okay";
+};
+
+&sdmmc {
+ broken-cd;
+ bus-width = <4>;
+ cap-sd-highspeed;
+ disable-wp;
+ max-frequency = <150000000>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&sdmmc_bus4 &sdmmc_cmd &sdmmc_clk>;
+ sd-uhs-sdr12;
+ sd-uhs-sdr25;
+ sd-uhs-sdr50;
+ sd-uhs-ddr50;
+ sd-uhs-sdr104;
+ vmmc-supply = <&vcc_3v3_s3>;
+ vqmmc-supply = <&vccio_sd_s0>;
+ status = "okay";
+};
+
+&spi2 {
+ assigned-clocks = <&cru CLK_SPI2>;
+ assigned-clock-rates = <200000000>;
+ num-cs = <1>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&spi2m2_cs0 &spi2m2_pins>;
+ status = "okay";
+
+ pmic@0 {
+ compatible = "rockchip,rk806";
+ reg = <0x0>;
+ interrupt-parent = <&gpio0>;
+ interrupts = <7 IRQ_TYPE_LEVEL_LOW>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pmic_pins>, <&rk806_dvs1_null>,
+ <&rk806_dvs2_null>, <&rk806_dvs3_null>;
+ spi-max-frequency = <1000000>;
+ system-power-controller;
+ vcc1-supply = <&vcc5v0_sys>;
+ vcc2-supply = <&vcc5v0_sys>;
+ vcc3-supply = <&vcc5v0_sys>;
+ vcc4-supply = <&vcc5v0_sys>;
+ vcc5-supply = <&vcc5v0_sys>;
+ vcc6-supply = <&vcc5v0_sys>;
+ vcc7-supply = <&vcc5v0_sys>;
+ vcc8-supply = <&vcc5v0_sys>;
+ vcc9-supply = <&vcc5v0_sys>;
+ vcc10-supply = <&vcc5v0_sys>;
+ vcc11-supply = <&vcc_2v0_pldo_s3>;
+ vcc12-supply = <&vcc5v0_sys>;
+ vcc13-supply = <&vcc_1v1_nldo_s3>;
+ vcc14-supply = <&vcc_1v1_nldo_s3>;
+ vcca-supply = <&vcc5v0_sys>;
+
+ rk806_dvs1_null: dvs1-null-pins {
+ pins = "gpio_pwrctrl2";
+ function = "pin_fun0";
+ };
+
+ rk806_dvs2_null: dvs2-null-pins {
+ pins = "gpio_pwrctrl2";
+ function = "pin_fun0";
+ };
+
+ rk806_dvs3_null: dvs3-null-pins {
+ pins = "gpio_pwrctrl3";
+ function = "pin_fun0";
+ };
+
+ regulators {
+ vdd_gpu_s0: dcdc-reg1 {
+ regulator-boot-on;
+ regulator-min-microvolt = <550000>;
+ regulator-max-microvolt = <950000>;
+ regulator-ramp-delay = <12500>;
+ regulator-name = "vdd_gpu_s0";
+ regulator-enable-ramp-delay = <400>;
+
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ };
+ };
+
+ vdd_cpu_lit_s0: dcdc-reg2 {
+ regulator-name = "vdd_cpu_lit_s0";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <550000>;
+ regulator-max-microvolt = <950000>;
+ regulator-ramp-delay = <12500>;
+
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ };
+ };
+
+ vdd_log_s0: dcdc-reg3 {
+ regulator-name = "vdd_log_s0";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <675000>;
+ regulator-max-microvolt = <750000>;
+ regulator-ramp-delay = <12500>;
+
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ regulator-suspend-microvolt = <750000>;
+ };
+ };
+
+ vdd_vdenc_s0: dcdc-reg4 {
+ regulator-name = "vdd_vdenc_s0";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <550000>;
+ regulator-max-microvolt = <950000>;
+ regulator-ramp-delay = <12500>;
+
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ };
+ };
+
+ vdd_ddr_s0: dcdc-reg5 {
+ regulator-name = "vdd_ddr_s0";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <675000>;
+ regulator-max-microvolt = <900000>;
+ regulator-ramp-delay = <12500>;
+
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ regulator-suspend-microvolt = <850000>;
+ };
+ };
+
+ vdd2_ddr_s3: dcdc-reg6 {
+ regulator-name = "vdd2_ddr_s3";
+ regulator-always-on;
+ regulator-boot-on;
+
+ regulator-state-mem {
+ regulator-on-in-suspend;
+ };
+ };
+
+ vcc_2v0_pldo_s3: dcdc-reg7 {
+ regulator-name = "vdd_2v0_pldo_s3";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <2000000>;
+ regulator-max-microvolt = <2000000>;
+ regulator-ramp-delay = <12500>;
+
+ regulator-state-mem {
+ regulator-on-in-suspend;
+ regulator-suspend-microvolt = <2000000>;
+ };
+ };
+
+ vcc_3v3_s3: dcdc-reg8 {
+ regulator-name = "vcc_3v3_s3";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+
+ regulator-state-mem {
+ regulator-on-in-suspend;
+ regulator-suspend-microvolt = <3300000>;
+ };
+ };
+
+ vddq_ddr_s0: dcdc-reg9 {
+ regulator-name = "vddq_ddr_s0";
+ regulator-always-on;
+ regulator-boot-on;
+
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ };
+ };
+
+ vcc_1v8_s3: dcdc-reg10 {
+ regulator-name = "vcc_1v8_s3";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+
+ regulator-state-mem {
+ regulator-on-in-suspend;
+ regulator-suspend-microvolt = <1800000>;
+ };
+ };
+
+ vcca_1v8_s0: pldo-reg1 {
+ regulator-name = "vcca_1v8_s0";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ };
+ };
+
+ vcc_1v8_s0: pldo-reg2 {
+ regulator-name = "vcc_1v8_s0";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ regulator-suspend-microvolt = <1800000>;
+ };
+ };
+
+ vdda_1v2_s0: pldo-reg3 {
+ regulator-name = "vdda_1v2_s0";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <1200000>;
+ regulator-max-microvolt = <1200000>;
+
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ };
+ };
+
+ vcca_3v3_s0: pldo-reg4 {
+ regulator-name = "vcca_3v3_s0";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-ramp-delay = <12500>;
+
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ };
+ };
+
+ vccio_sd_s0: pldo-reg5 {
+ regulator-name = "vccio_sd_s0";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-ramp-delay = <12500>;
+
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ };
+ };
+
+ pldo6_s3: pldo-reg6 {
+ regulator-name = "pldo6_s3";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+
+ regulator-state-mem {
+ regulator-on-in-suspend;
+ regulator-suspend-microvolt = <1800000>;
+ };
+ };
+
+ vdd_0v75_s3: nldo-reg1 {
+ regulator-name = "vdd_0v75_s3";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <750000>;
+ regulator-max-microvolt = <750000>;
+
+ regulator-state-mem {
+ regulator-on-in-suspend;
+ regulator-suspend-microvolt = <750000>;
+ };
+ };
+
+ vdda_ddr_pll_s0: nldo-reg2 {
+ regulator-name = "vdda_ddr_pll_s0";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <850000>;
+ regulator-max-microvolt = <850000>;
+
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ regulator-suspend-microvolt = <850000>;
+ };
+ };
+
+ vdda_0v75_s0: nldo-reg3 {
+ regulator-name = "vdda_0v75_s0";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <750000>;
+ regulator-max-microvolt = <750000>;
+
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ };
+ };
+
+ vdda_0v85_s0: nldo-reg4 {
+ regulator-name = "vdda_0v85_s0";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <850000>;
+ regulator-max-microvolt = <850000>;
+
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ };
+ };
+
+ vdd_0v75_s0: nldo-reg5 {
+ regulator-name = "vdd_0v75_s0";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <750000>;
+ regulator-max-microvolt = <750000>;
+
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ };
+ };
+ };
+ };
+};
+
+&tsadc {
+ status = "okay";
+};
+
+&u2phy2 {
+ status = "okay";
+};
+
+&u2phy2_host {
+ phy-supply = <&vcc_5v0_usb_a>;
+ status = "okay";
+};
+
+&u2phy3 {
+ status = "okay";
+};
+
+&u2phy3_host {
+ status = "okay";
+};
+
+/* Mule-ATtiny debug UART; typically baudrate 9600 */
+&uart0 {
+ pinctrl-0 = <&uart0m0_xfer>;
+ status = "okay";
+};
+
+/* Main debug interface on P20 micro-USB B port and P21 header */
+&uart2 {
+ pinctrl-0 = <&uart2m0_xfer>;
+ status = "okay";
+};
+
+/* RS485 on P19 */
+&uart3 {
+ pinctrl-0 = <&uart3m2_xfer &uart3_rtsn>;
+ linux,rs485-enabled-at-boot-time;
+ status = "okay";
+};
+
+/* Mule-ATtiny UPDI flashing UART */
+&uart7 {
+ pinctrl-0 = <&uart7m0_xfer>;
+ status = "okay";
+};
+
+/* host0 on P10 USB-A */
+&usb_host0_ehci {
+ status = "okay";
+};
+
+/* host0 on P10 USB-A */
+&usb_host0_ohci {
+ status = "okay";
+};
+
+/* host1 on M.2 E-key */
+&usb_host1_ehci {
+ status = "okay";
+};
+
+/* host1 on M.2 E-key */
+&usb_host1_ohci {
+ status = "okay";
+};
diff --git a/dts/upstream/src/arm64/rockchip/rk3588-nanopc-t6.dts b/dts/upstream/src/arm64/rockchip/rk3588-nanopc-t6.dts
index 97af4f9..997b516 100644
--- a/dts/upstream/src/arm64/rockchip/rk3588-nanopc-t6.dts
+++ b/dts/upstream/src/arm64/rockchip/rk3588-nanopc-t6.dts
@@ -19,7 +19,6 @@
aliases {
mmc0 = &sdhci;
mmc1 = &sdmmc;
- serial2 = &uart2;
};
chosen {
@@ -190,19 +189,19 @@
cpu-supply = <&vdd_cpu_lit_s0>;
};
-&cpu_b0{
+&cpu_b0 {
cpu-supply = <&vdd_cpu_big0_s0>;
};
-&cpu_b1{
+&cpu_b1 {
cpu-supply = <&vdd_cpu_big0_s0>;
};
-&cpu_b2{
+&cpu_b2 {
cpu-supply = <&vdd_cpu_big1_s0>;
};
-&cpu_b3{
+&cpu_b3 {
cpu-supply = <&vdd_cpu_big1_s0>;
};
@@ -537,13 +536,12 @@
};
&sdmmc {
- max-frequency = <200000000>;
- no-sdio;
- no-mmc;
bus-width = <4>;
cap-mmc-highspeed;
cap-sd-highspeed;
disable-wp;
+ no-mmc;
+ no-sdio;
sd-uhs-sdr104;
vmmc-supply = <&vcc_3v3_s3>;
vqmmc-supply = <&vccio_sd_s0>;
@@ -570,6 +568,8 @@
pinctrl-0 = <&pmic_pins>, <&rk806_dvs1_null>,
<&rk806_dvs2_null>, <&rk806_dvs3_null>;
+ system-power-controller;
+
vcc1-supply = <&vcc4v0_sys>;
vcc2-supply = <&vcc4v0_sys>;
vcc3-supply = <&vcc4v0_sys>;
@@ -590,7 +590,7 @@
#gpio-cells = <2>;
rk806_dvs1_null: dvs1-null-pins {
- pins = "gpio_pwrctrl2";
+ pins = "gpio_pwrctrl1";
function = "pin_fun0";
};
diff --git a/dts/upstream/src/arm64/rockchip/rk3588-orangepi-5-plus.dts b/dts/upstream/src/arm64/rockchip/rk3588-orangepi-5-plus.dts
index 298c183..3e660ff 100644
--- a/dts/upstream/src/arm64/rockchip/rk3588-orangepi-5-plus.dts
+++ b/dts/upstream/src/arm64/rockchip/rk3588-orangepi-5-plus.dts
@@ -19,7 +19,6 @@
aliases {
mmc0 = &sdhci;
mmc1 = &sdmmc;
- serial2 = &uart2;
};
chosen {
diff --git a/dts/upstream/src/arm64/rockchip/rk3588-quartzpro64.dts b/dts/upstream/src/arm64/rockchip/rk3588-quartzpro64.dts
index 5c59f95..87a0abf 100644
--- a/dts/upstream/src/arm64/rockchip/rk3588-quartzpro64.dts
+++ b/dts/upstream/src/arm64/rockchip/rk3588-quartzpro64.dts
@@ -17,9 +17,9 @@
compatible = "pine64,quartzpro64", "rockchip,rk3588";
aliases {
+ ethernet0 = &gmac0;
mmc0 = &sdhci;
mmc1 = &sdmmc;
- serial2 = &uart2;
};
chosen {
diff --git a/dts/upstream/src/arm64/rockchip/rk3588-rock-5b.dts b/dts/upstream/src/arm64/rockchip/rk3588-rock-5b.dts
index 741f631..a0e303c 100644
--- a/dts/upstream/src/arm64/rockchip/rk3588-rock-5b.dts
+++ b/dts/upstream/src/arm64/rockchip/rk3588-rock-5b.dts
@@ -14,7 +14,6 @@
mmc0 = &sdhci;
mmc1 = &sdmmc;
mmc2 = &sdio;
- serial2 = &uart2;
};
chosen {
@@ -138,6 +137,10 @@
status = "okay";
};
+&combphy2_psu {
+ status = "okay";
+};
+
&cpu_b0 {
cpu-supply = <&vdd_cpu_big0_s0>;
};
@@ -423,6 +426,8 @@
pinctrl-0 = <&pmic_pins>, <&rk806_dvs1_null>,
<&rk806_dvs2_null>, <&rk806_dvs3_null>;
+ system-power-controller;
+
vcc1-supply = <&vcc5v0_sys>;
vcc2-supply = <&vcc5v0_sys>;
vcc3-supply = <&vcc5v0_sys>;
@@ -443,7 +448,7 @@
#gpio-cells = <2>;
rk806_dvs1_null: dvs1-null-pins {
- pins = "gpio_pwrctrl2";
+ pins = "gpio_pwrctrl1";
function = "pin_fun0";
};
@@ -765,3 +770,7 @@
&usb_host1_ohci {
status = "okay";
};
+
+&usb_host2_xhci {
+ status = "okay";
+};
diff --git a/dts/upstream/src/arm64/rockchip/rk3588-turing-rk1.dtsi b/dts/upstream/src/arm64/rockchip/rk3588-turing-rk1.dtsi
index d88c0e8..dc08da5 100644
--- a/dts/upstream/src/arm64/rockchip/rk3588-turing-rk1.dtsi
+++ b/dts/upstream/src/arm64/rockchip/rk3588-turing-rk1.dtsi
@@ -19,8 +19,6 @@
aliases {
ethernet0 = &gmac1;
mmc0 = &sdhci;
- serial2 = &uart2;
- serial9 = &uart9;
};
fan: pwm-fan {
diff --git a/dts/upstream/src/arm64/rockchip/rk3588s-coolpi-4b.dts b/dts/upstream/src/arm64/rockchip/rk3588s-coolpi-4b.dts
new file mode 100644
index 0000000..e037bf9
--- /dev/null
+++ b/dts/upstream/src/arm64/rockchip/rk3588s-coolpi-4b.dts
@@ -0,0 +1,812 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (c) 2023 Rockchip Electronics Co., Ltd.
+ *
+ * https://cool-pi.com/topic/130/coolpi-4b-product-spec-introduction
+ *
+ */
+
+/dts-v1/;
+
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/leds/common.h>
+#include <dt-bindings/pinctrl/rockchip.h>
+#include "rk3588s.dtsi"
+
+/ {
+ model = "RK3588S CoolPi 4 Model B";
+ compatible = "coolpi,pi-4b", "rockchip,rk3588s";
+
+ aliases {
+ mmc0 = &sdhci;
+ mmc1 = &sdmmc;
+ mmc2 = &sdio;
+ };
+
+ analog-sound {
+ compatible = "audio-graph-card";
+ dais = <&i2s0_8ch_p0>;
+ label = "rk3588-es8316";
+ routing = "MIC2", "Mic Jack",
+ "Headphones", "HPOL",
+ "Headphones", "HPOR";
+ widgets = "Microphone", "Mic Jack",
+ "Headphone", "Headphones";
+ };
+
+ chosen {
+ stdout-path = "serial2:1500000n8";
+ };
+
+ leds: leds {
+ compatible = "gpio-leds";
+ pinctrl-names = "default";
+ pinctrl-0 = <&gpio_leds>;
+
+ led0: led-green {
+ color = <LED_COLOR_ID_GREEN>;
+ function = LED_FUNCTION_STATUS;
+ gpios = <&gpio0 RK_PD0 GPIO_ACTIVE_HIGH>;
+ linux,default-trigger = "heartbeat";
+ };
+
+ led1: led-red {
+ color = <LED_COLOR_ID_RED>;
+ default-state = "off";
+ function = LED_FUNCTION_WLAN;
+ gpios = <&gpio0 RK_PC4 GPIO_ACTIVE_HIGH>;
+ linux,default-trigger = "phy0tx";
+ };
+ };
+
+ sdio_pwrseq: sdio-pwrseq {
+ compatible = "mmc-pwrseq-simple";
+ clocks = <&hym8563>;
+ clock-names = "ext_clock";
+ pinctrl-names = "default";
+ pinctrl-0 = <&wifi_enable_h>;
+ /*
+ * On the module itself this is one of these (depending
+ * on the actual card populated):
+ * - SDIO_RESET_L_WL_REG_ON
+ * - PDN (power down when low)
+ */
+ post-power-on-delay-ms = <200>;
+ reset-gpios = <&gpio0 RK_PC7 GPIO_ACTIVE_LOW>;
+ };
+
+ vcc12v_dcin: vcc12v-dcin-regulator {
+ compatible = "regulator-fixed";
+ regulator-name = "vcc12v_dcin";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <12000000>;
+ regulator-max-microvolt = <12000000>;
+ };
+
+ vcc5v0_sys: vcc5v0-sys-regulator {
+ compatible = "regulator-fixed";
+ regulator-name = "vcc5v0_sys";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <5000000>;
+ regulator-max-microvolt = <5000000>;
+ vin-supply = <&vcc12v_dcin>;
+ };
+
+ vcc5v0_usbdcin: vcc5v0-usbdcin-regulator {
+ compatible = "regulator-fixed";
+ regulator-name = "vcc5v0_usbdcin";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <5000000>;
+ regulator-max-microvolt = <5000000>;
+ vin-supply = <&vcc12v_dcin>;
+ };
+
+ vcc5v0_usb: vcc5v0-usb-regulator {
+ compatible = "regulator-fixed";
+ regulator-name = "vcc5v0_usb";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <5000000>;
+ regulator-max-microvolt = <5000000>;
+ vin-supply = <&vcc5v0_usbdcin>;
+ };
+
+ avdd0v85_pcie20: avdd0v85-pcie20-regulator {
+ compatible = "regulator-fixed";
+ regulator-name = "avdd0v85_pcie20";
+ regulator-boot-on;
+ regulator-always-on;
+ regulator-min-microvolt = <850000>;
+ regulator-max-microvolt = <850000>;
+ vin-supply = <&vdd_0v85_s0>;
+ };
+
+ avdd1v8_pcie20: avdd1v8-pcie20-regulator {
+ compatible = "regulator-fixed";
+ regulator-name = "avdd1v8_pcie20";
+ regulator-boot-on;
+ regulator-always-on;
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ vin-supply = <&avcc_1v8_s0>;
+ };
+
+ vcc3v3_mipi: vcc3v3-mipi-regulator {
+ compatible = "regulator-fixed";
+ enable-active-high;
+ gpio = <&gpio3 RK_PC2 GPIO_ACTIVE_HIGH>;
+ regulator-name = "vcc3v3_mipi";
+ regulator-boot-on;
+ regulator-always-on;
+ vin-supply = <&vcc_3v3_s3>;
+ };
+
+ vcc5v0_host: vcc5v0-host-regulator {
+ compatible = "regulator-fixed";
+ enable-active-high;
+ gpio = <&gpio3 RK_PC0 GPIO_ACTIVE_HIGH>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&vcc5v0_host_en>;
+ regulator-name = "vcc5v0_host";
+ regulator-boot-on;
+ regulator-always-on;
+ regulator-min-microvolt = <5000000>;
+ regulator-max-microvolt = <5000000>;
+ vin-supply = <&vcc5v0_sys>;
+ };
+
+ vcc5v0_otg: vcc5v0-otg-regulator {
+ compatible = "regulator-fixed";
+ enable-active-high;
+ gpio = <&gpio3 RK_PC1 GPIO_ACTIVE_HIGH>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&vcc5v0_u3host_en>;
+ regulator-name = "vcc5v0_otg";
+ regulator-boot-on;
+ regulator-always-on;
+ regulator-min-microvolt = <5000000>;
+ regulator-max-microvolt = <5000000>;
+ vin-supply = <&vcc5v0_sys>;
+ };
+
+ vcc_1v1_nldo_s3: vcc-1v1-nldo-s3-regulator {
+ compatible = "regulator-fixed";
+ regulator-name = "vcc_1v1_nldo_s3";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <1100000>;
+ regulator-max-microvolt = <1100000>;
+ vin-supply = <&vcc5v0_sys>;
+ };
+};
+
+&combphy0_ps {
+ status = "okay";
+};
+
+&combphy2_psu {
+ status = "okay";
+};
+
+&cpu_l0 {
+ cpu-supply = <&vdd_cpu_lit_s0>;
+};
+
+&cpu_b0 {
+ cpu-supply = <&vdd_cpu_big0_s0>;
+};
+
+&cpu_b2 {
+ cpu-supply = <&vdd_cpu_big1_s0>;
+};
+
+&i2c0 {
+ pinctrl-0 = <&i2c0m2_xfer>;
+ status = "okay";
+
+ vdd_cpu_big0_s0: regulator@42 {
+ compatible = "rockchip,rk8602";
+ reg = <0x42>;
+ fcs,suspend-voltage-selector = <1>;
+ regulator-name = "vdd_cpu_big0_s0";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <550000>;
+ regulator-max-microvolt = <1050000>;
+ regulator-ramp-delay = <2300>;
+ vin-supply = <&vcc5v0_sys>;
+
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ };
+ };
+
+ vdd_cpu_big1_s0: regulator@43 {
+ compatible = "rockchip,rk8603", "rockchip,rk8602";
+ reg = <0x43>;
+ fcs,suspend-voltage-selector = <1>;
+ regulator-name = "vdd_cpu_big1_s0";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <550000>;
+ regulator-max-microvolt = <1050000>;
+ regulator-ramp-delay = <2300>;
+ vin-supply = <&vcc5v0_sys>;
+
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ };
+ };
+};
+
+&i2c2 {
+ status = "okay";
+
+ vdd_npu_s0: regulator@42 {
+ compatible = "rockchip,rk8602";
+ reg = <0x42>;
+ fcs,suspend-voltage-selector = <1>;
+ regulator-name = "vdd_npu_s0";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <550000>;
+ regulator-max-microvolt = <950000>;
+ regulator-ramp-delay = <2300>;
+ vin-supply = <&vcc5v0_sys>;
+
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ };
+ };
+};
+
+&i2c6 {
+ pinctrl-0 = <&i2c6m3_xfer>;
+ status = "okay";
+
+ hym8563: rtc@51 {
+ compatible = "haoyu,hym8563";
+ reg = <0x51>;
+ interrupt-parent = <&gpio0>;
+ interrupts = <RK_PB0 IRQ_TYPE_LEVEL_LOW>;
+ #clock-cells = <0>;
+ clock-output-names = "hym8563";
+ pinctrl-names = "default";
+ pinctrl-0 = <&hym8563_int>;
+ };
+};
+
+&i2c7 {
+ pinctrl-0 = <&i2c7m0_xfer>;
+ status = "okay";
+
+ es8316: audio-codec@11 {
+ compatible = "everest,es8316";
+ reg = <0x11>;
+ assigned-clocks = <&cru I2S0_8CH_MCLKOUT>;
+ assigned-clock-rates = <12288000>;
+ clocks = <&cru I2S0_8CH_MCLKOUT>;
+ clock-names = "mclk";
+ #sound-dai-cells = <0>;
+
+ port {
+ es8316_p0_0: endpoint {
+ remote-endpoint = <&i2s0_8ch_p0_0>;
+ };
+ };
+ };
+};
+
+&i2s0_8ch {
+ pinctrl-0 = <&i2s0_lrck
+ &i2s0_mclk
+ &i2s0_sclk
+ &i2s0_sdi0
+ &i2s0_sdo0>;
+ status = "okay";
+
+ i2s0_8ch_p0: port {
+ i2s0_8ch_p0_0: endpoint {
+ dai-format = "i2s";
+ mclk-fs = <256>;
+ remote-endpoint = <&es8316_p0_0>;
+ };
+ };
+};
+
+&pcie2x1l2 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&rtl8111_isolate>;
+ reset-gpios = <&gpio3 RK_PD1 GPIO_ACTIVE_HIGH>;
+ status = "okay";
+};
+
+&pinctrl {
+ hym8563 {
+ hym8563_int: hym8563-int {
+ rockchip,pins = <0 RK_PB0 RK_FUNC_GPIO &pcfg_pull_up>;
+ };
+ };
+
+ led {
+ gpio_leds: gpio-leds {
+ rockchip,pins = <0 RK_PC4 RK_FUNC_GPIO &pcfg_pull_down>,
+ <0 RK_PD0 RK_FUNC_GPIO &pcfg_pull_down>;
+ };
+ };
+
+ rtl8111 {
+ rtl8111_isolate: rtl8111-isolate {
+ rockchip,pins = <1 RK_PA4 RK_FUNC_GPIO &pcfg_pull_up>;
+ };
+ };
+
+ sdio-pwrseq {
+ wifi_enable_h: wifi-enable-h {
+ rockchip,pins = <0 RK_PC7 RK_FUNC_GPIO &pcfg_pull_up>;
+ };
+ };
+
+ usb {
+ vcc5v0_host_en: vcc5v0-host-en {
+ rockchip,pins = <3 RK_PC0 RK_FUNC_GPIO &pcfg_pull_none>,
+ <4 RK_PB5 RK_FUNC_GPIO &pcfg_pull_up>;
+ };
+
+ vcc5v0_u3host_en: vcc5v0-u3host-en {
+ rockchip,pins = <3 RK_PC1 RK_FUNC_GPIO &pcfg_pull_none>;
+ };
+ };
+
+ wireless-bluetooth {
+ bt_reset_gpio: bt-reset-pin {
+ rockchip,pins = <0 RK_PD3 RK_FUNC_GPIO &pcfg_pull_none>;
+ };
+
+ bt_wake_gpio: bt-wake-pin {
+ rockchip,pins = <0 RK_PC6 RK_FUNC_GPIO &pcfg_pull_none>;
+ };
+
+ bt_wake_host_irq: bt-wake-host-irq {
+ rockchip,pins = <0 RK_PC5 RK_FUNC_GPIO &pcfg_pull_down>;
+ };
+ };
+
+ wireless-wlan {
+ wifi_host_wake_irq: wifi-host-wake-irq {
+ rockchip,pins = <0 RK_PA0 RK_FUNC_GPIO &pcfg_pull_down>;
+ };
+
+ wifi_poweren_pin: wifi-poweren-pin {
+ rockchip,pins = <1 RK_PD3 RK_FUNC_GPIO &pcfg_pull_up>;
+ };
+ };
+};
+
+&pwm2 {
+ pinctrl-0 = <&pwm2m1_pins>;
+ status = "okay";
+};
+
+&pwm13 {
+ pinctrl-names = "active";
+ pinctrl-0 = <&pwm13m2_pins>;
+ status = "okay";
+};
+
+&saradc {
+ vref-supply = <&vcc_1v8_s0>;
+ status = "okay";
+};
+
+&sdhci {
+ bus-width = <8>;
+ max-frequency = <200000000>;
+ mmc-hs400-1_8v;
+ mmc-hs400-enhanced-strobe;
+ no-sdio;
+ no-sd;
+ non-removable;
+ status = "okay";
+};
+
+&sdio {
+ bus-width = <4>;
+ cap-sd-highspeed;
+ cap-sdio-irq;
+ disable-wp;
+ keep-power-in-suspend;
+ max-frequency = <150000000>;
+ mmc-pwrseq = <&sdio_pwrseq>;
+ no-sd;
+ no-mmc;
+ non-removable;
+ pinctrl-names = "default";
+ pinctrl-0 = <&sdiom1_pins>,<&wifi_poweren_pin>;
+ status = "okay";
+};
+
+&sdmmc {
+ bus-width = <4>;
+ cap-mmc-highspeed;
+ cap-sd-highspeed;
+ disable-wp;
+ max-frequency = <150000000>;
+ no-sdio;
+ no-mmc;
+ sd-uhs-sdr104;
+ vmmc-supply = <&vcc_3v3_s3>;
+ vqmmc-supply = <&vccio_sd_s0>;
+ status = "okay";
+};
+
+&spi2 {
+ assigned-clocks = <&cru CLK_SPI2>;
+ assigned-clock-rates = <200000000>;
+ num-cs = <1>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&spi2m2_cs0 &spi2m2_pins>;
+ status = "okay";
+
+ pmic@0 {
+ compatible = "rockchip,rk806";
+ reg = <0x0>;
+ interrupt-parent = <&gpio0>;
+ interrupts = <7 IRQ_TYPE_LEVEL_LOW>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pmic_pins>, <&rk806_dvs1_null>,
+ <&rk806_dvs2_null>, <&rk806_dvs3_null>;
+ spi-max-frequency = <1000000>;
+ vcc1-supply = <&vcc5v0_sys>;
+ vcc2-supply = <&vcc5v0_sys>;
+ vcc3-supply = <&vcc5v0_sys>;
+ vcc4-supply = <&vcc5v0_sys>;
+ vcc5-supply = <&vcc5v0_sys>;
+ vcc6-supply = <&vcc5v0_sys>;
+ vcc7-supply = <&vcc5v0_sys>;
+ vcc8-supply = <&vcc5v0_sys>;
+ vcc9-supply = <&vcc5v0_sys>;
+ vcc10-supply = <&vcc5v0_sys>;
+ vcc11-supply = <&vcc_2v0_pldo_s3>;
+ vcc12-supply = <&vcc5v0_sys>;
+ vcc13-supply = <&vcc_1v1_nldo_s3>;
+ vcc14-supply = <&vcc_1v1_nldo_s3>;
+ vcca-supply = <&vcc5v0_sys>;
+
+ rk806_dvs1_null: dvs1-null-pins {
+ pins = "gpio_pwrctrl2";
+ function = "pin_fun0";
+ };
+
+ rk806_dvs2_null: dvs2-null-pins {
+ pins = "gpio_pwrctrl2";
+ function = "pin_fun0";
+ };
+
+ rk806_dvs3_null: dvs3-null-pins {
+ pins = "gpio_pwrctrl3";
+ function = "pin_fun0";
+ };
+
+ regulators {
+ vdd_gpu_s0: vdd_gpu_mem_s0: dcdc-reg1 {
+ regulator-name = "vdd_gpu_s0";
+ regulator-boot-on;
+ regulator-min-microvolt = <550000>;
+ regulator-max-microvolt = <950000>;
+ regulator-ramp-delay = <12500>;
+ regulator-enable-ramp-delay = <400>;
+
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ };
+ };
+
+ vdd_cpu_lit_s0: vdd_cpu_lit_mem_s0: dcdc-reg2 {
+ regulator-name = "vdd_cpu_lit_s0";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <550000>;
+ regulator-max-microvolt = <950000>;
+ regulator-ramp-delay = <12500>;
+
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ };
+ };
+
+ vdd_log_s0: dcdc-reg3 {
+ regulator-name = "vdd_log_s0";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <675000>;
+ regulator-max-microvolt = <750000>;
+ regulator-ramp-delay = <12500>;
+
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ regulator-suspend-microvolt = <750000>;
+ };
+ };
+
+ vdd_vdenc_s0: vdd_vdenc_mem_s0: dcdc-reg4 {
+ regulator-name = "vdd_vdenc_s0";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <550000>;
+ regulator-max-microvolt = <950000>;
+ regulator-ramp-delay = <12500>;
+
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ };
+ };
+
+ vdd_ddr_s0: dcdc-reg5 {
+ regulator-name = "vdd_ddr_s0";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <675000>;
+ regulator-max-microvolt = <900000>;
+ regulator-ramp-delay = <12500>;
+
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ regulator-suspend-microvolt = <850000>;
+ };
+ };
+
+ vdd2_ddr_s3: dcdc-reg6 {
+ regulator-name = "vdd2_ddr_s3";
+ regulator-always-on;
+ regulator-boot-on;
+
+ regulator-state-mem {
+ regulator-on-in-suspend;
+ };
+ };
+
+ vcc_2v0_pldo_s3: dcdc-reg7 {
+ regulator-name = "vdd_2v0_pldo_s3";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <2000000>;
+ regulator-max-microvolt = <2000000>;
+ regulator-ramp-delay = <12500>;
+
+ regulator-state-mem {
+ regulator-on-in-suspend;
+ regulator-suspend-microvolt = <2000000>;
+ };
+ };
+
+ vcc_3v3_s3: dcdc-reg8 {
+ regulator-name = "vcc_3v3_s3";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+
+ regulator-state-mem {
+ regulator-on-in-suspend;
+ regulator-suspend-microvolt = <3300000>;
+ };
+ };
+
+ vddq_ddr_s0: dcdc-reg9 {
+ regulator-name = "vddq_ddr_s0";
+ regulator-always-on;
+ regulator-boot-on;
+
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ };
+ };
+
+ vcc_1v8_s3: dcdc-reg10 {
+ regulator-name = "vcc_1v8_s3";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+
+ regulator-state-mem {
+ regulator-on-in-suspend;
+ regulator-suspend-microvolt = <1800000>;
+ };
+ };
+
+ avcc_1v8_s0: pldo-reg1 {
+ regulator-name = "avcc_1v8_s0";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ };
+ };
+
+ vcc_1v8_s0: pldo-reg2 {
+ regulator-name = "vcc_1v8_s0";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ regulator-suspend-microvolt = <1800000>;
+ };
+ };
+
+ avdd_1v2_s0: pldo-reg3 {
+ regulator-name = "avdd_1v2_s0";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <1200000>;
+ regulator-max-microvolt = <1200000>;
+
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ };
+ };
+
+ vcc_3v3_s0: pldo-reg4 {
+ regulator-name = "vcc_3v3_s0";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-ramp-delay = <12500>;
+
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ };
+ };
+
+ vccio_sd_s0: pldo-reg5 {
+ regulator-name = "vccio_sd_s0";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-ramp-delay = <12500>;
+
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ };
+ };
+
+ pldo6_s3: pldo-reg6 {
+ regulator-name = "pldo6_s3";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+
+ regulator-state-mem {
+ regulator-on-in-suspend;
+ regulator-suspend-microvolt = <1800000>;
+ };
+ };
+
+ vdd_0v75_s3: nldo-reg1 {
+ regulator-name = "vdd_0v75_s3";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <750000>;
+ regulator-max-microvolt = <750000>;
+
+ regulator-state-mem {
+ regulator-on-in-suspend;
+ regulator-suspend-microvolt = <750000>;
+ };
+ };
+
+ vdd_ddr_pll_s0: nldo-reg2 {
+ regulator-name = "vdd_ddr_pll_s0";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <850000>;
+ regulator-max-microvolt = <850000>;
+
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ regulator-suspend-microvolt = <850000>;
+ };
+ };
+
+ avdd_0v75_s0: nldo-reg3 {
+ regulator-name = "avdd_0v75_s0";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <750000>;
+ regulator-max-microvolt = <750000>;
+
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ };
+ };
+
+ vdd_0v85_s0: nldo-reg4 {
+ regulator-name = "vdd_0v85_s0";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <850000>;
+ regulator-max-microvolt = <850000>;
+
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ };
+ };
+
+ vdd_0v75_s0: nldo-reg5 {
+ regulator-name = "vdd_0v75_s0";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <750000>;
+ regulator-max-microvolt = <750000>;
+
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ };
+ };
+ };
+ };
+};
+
+&tsadc {
+ status = "okay";
+};
+
+&u2phy2 {
+ status = "okay";
+};
+
+&u2phy3 {
+ status = "okay";
+};
+
+&u2phy2_host {
+ phy-supply = <&vcc5v0_host>;
+ status = "okay";
+};
+
+&u2phy3_host {
+ status = "okay";
+};
+
+&uart2 {
+ pinctrl-0 = <&uart2m0_xfer>;
+ status = "okay";
+};
+
+/* bt */
+&uart9 {
+ status = "okay";
+ pinctrl-names = "default";
+ pinctrl-0 = <&uart9m2_xfer &uart9m2_ctsn>;
+};
+
+&usb_host0_ehci {
+ status = "okay";
+};
+
+&usb_host0_ohci {
+ status = "okay";
+};
+
+&usb_host1_ehci {
+ status = "okay";
+};
+
+&usb_host1_ohci {
+ status = "okay";
+};
diff --git a/dts/upstream/src/arm64/rockchip/rk3588s-indiedroid-nova.dts b/dts/upstream/src/arm64/rockchip/rk3588s-indiedroid-nova.dts
index 60f00ce..3c22788 100644
--- a/dts/upstream/src/arm64/rockchip/rk3588s-indiedroid-nova.dts
+++ b/dts/upstream/src/arm64/rockchip/rk3588s-indiedroid-nova.dts
@@ -44,7 +44,6 @@
mmc0 = &sdhci;
mmc1 = &sdmmc;
mmc2 = &sdio;
- serial2 = &uart2;
};
chosen {
@@ -196,13 +195,13 @@
&gpio1 {
gpio-line-names = /* GPIO1 A0-A7 */
- "HEADER_27_3v3", "HEADER_28_3v3", "", "",
+ "HEADER_27_3v3", "", "", "",
"HEADER_29_1v8", "", "HEADER_7_1v8", "",
/* GPIO1 B0-B7 */
"", "HEADER_31_1v8", "HEADER_33_1v8", "",
"HEADER_11_1v8", "HEADER_13_1v8", "", "",
/* GPIO1 C0-C7 */
- "", "", "", "",
+ "", "HEADER_28_3v3", "", "",
"", "", "", "",
/* GPIO1 D0-D7 */
"", "", "", "",
@@ -226,11 +225,11 @@
&gpio4 {
gpio-line-names = /* GPIO4 A0-A7 */
- "", "", "HEADER_37_3v3", "HEADER_32_3v3",
- "HEADER_36_3v3", "", "HEADER_35_3v3", "HEADER_38_3v3",
+ "", "", "HEADER_37_3v3", "HEADER_8_3v3",
+ "HEADER_10_3v3", "", "HEADER_32_3v3", "HEADER_35_3v3",
/* GPIO4 B0-B7 */
"", "", "", "HEADER_40_3v3",
- "HEADER_8_3v3", "HEADER_10_3v3", "", "",
+ "HEADER_38_3v3", "HEADER_36_3v3", "", "",
/* GPIO4 C0-C7 */
"", "", "", "",
"", "", "", "",
diff --git a/dts/upstream/src/arm64/rockchip/rk3588s-khadas-edge2.dts b/dts/upstream/src/arm64/rockchip/rk3588s-khadas-edge2.dts
index 82478a4..f53e993 100644
--- a/dts/upstream/src/arm64/rockchip/rk3588s-khadas-edge2.dts
+++ b/dts/upstream/src/arm64/rockchip/rk3588s-khadas-edge2.dts
@@ -12,7 +12,6 @@
aliases {
mmc0 = &sdhci;
- serial2 = &uart2;
};
chosen {
diff --git a/dts/upstream/src/arm64/rockchip/rk3588s-orangepi-5.dts b/dts/upstream/src/arm64/rockchip/rk3588s-orangepi-5.dts
index e3a839a..25de436 100644
--- a/dts/upstream/src/arm64/rockchip/rk3588s-orangepi-5.dts
+++ b/dts/upstream/src/arm64/rockchip/rk3588s-orangepi-5.dts
@@ -13,8 +13,8 @@
compatible = "xunlong,orangepi-5", "rockchip,rk3588s";
aliases {
+ ethernet0 = &gmac1;
mmc0 = &sdmmc;
- serial2 = &uart2;
};
chosen {
@@ -314,6 +314,7 @@
pinctrl-0 = <&pmic_pins>, <&rk806_dvs1_null>,
<&rk806_dvs2_null>, <&rk806_dvs3_null>;
spi-max-frequency = <1000000>;
+ system-power-controller;
vcc1-supply = <&vcc5v0_sys>;
vcc2-supply = <&vcc5v0_sys>;
@@ -660,3 +661,7 @@
&usb_host1_ohci {
status = "okay";
};
+
+&usb_host2_xhci {
+ status = "okay";
+};
diff --git a/dts/upstream/src/arm64/rockchip/rk3588s-rock-5a.dts b/dts/upstream/src/arm64/rockchip/rk3588s-rock-5a.dts
index 8347adc..2002fd0 100644
--- a/dts/upstream/src/arm64/rockchip/rk3588s-rock-5a.dts
+++ b/dts/upstream/src/arm64/rockchip/rk3588s-rock-5a.dts
@@ -12,9 +12,9 @@
compatible = "radxa,rock-5a", "rockchip,rk3588s";
aliases {
+ ethernet0 = &gmac1;
mmc0 = &sdhci;
mmc1 = &sdmmc;
- serial2 = &uart2;
};
analog-sound {
@@ -114,6 +114,10 @@
};
};
+&combphy2_psu {
+ status = "okay";
+};
+
&cpu_b0 {
cpu-supply = <&vdd_cpu_big0_s0>;
};
@@ -734,3 +738,7 @@
&usb_host1_ohci {
status = "okay";
};
+
+&usb_host2_xhci {
+ status = "okay";
+};
diff --git a/dts/upstream/src/arm64/rockchip/rk3588s.dtsi b/dts/upstream/src/arm64/rockchip/rk3588s.dtsi
index 8aa0499..36b1b7a 100644
--- a/dts/upstream/src/arm64/rockchip/rk3588s.dtsi
+++ b/dts/upstream/src/arm64/rockchip/rk3588s.dtsi
@@ -18,6 +18,38 @@
#address-cells = <2>;
#size-cells = <2>;
+ aliases {
+ gpio0 = &gpio0;
+ gpio1 = &gpio1;
+ gpio2 = &gpio2;
+ gpio3 = &gpio3;
+ gpio4 = &gpio4;
+ i2c0 = &i2c0;
+ i2c1 = &i2c1;
+ i2c2 = &i2c2;
+ i2c3 = &i2c3;
+ i2c4 = &i2c4;
+ i2c5 = &i2c5;
+ i2c6 = &i2c6;
+ i2c7 = &i2c7;
+ i2c8 = &i2c8;
+ serial0 = &uart0;
+ serial1 = &uart1;
+ serial2 = &uart2;
+ serial3 = &uart3;
+ serial4 = &uart4;
+ serial5 = &uart5;
+ serial6 = &uart6;
+ serial7 = &uart7;
+ serial8 = &uart8;
+ serial9 = &uart9;
+ spi0 = &spi0;
+ spi1 = &spi1;
+ spi2 = &spi2;
+ spi3 = &spi3;
+ spi4 = &spi4;
+ };
+
cpus {
#address-cells = <1>;
#size-cells = <0>;
@@ -362,6 +394,11 @@
#clock-cells = <0>;
};
+ display_subsystem: display-subsystem {
+ compatible = "rockchip,display-subsystem";
+ ports = <&vop_out>;
+ };
+
timer {
compatible = "arm,armv8-timer";
interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_HIGH 0>,
@@ -474,6 +511,16 @@
reg = <0x0 0xfd58c000 0x0 0x1000>;
};
+ vop_grf: syscon@fd5a4000 {
+ compatible = "rockchip,rk3588-vop-grf", "syscon";
+ reg = <0x0 0xfd5a4000 0x0 0x2000>;
+ };
+
+ vo1_grf: syscon@fd5a8000 {
+ compatible = "rockchip,rk3588-vo-grf", "syscon";
+ reg = <0x0 0xfd5a8000 0x0 0x100>;
+ };
+
php_grf: syscon@fd5b0000 {
compatible = "rockchip,rk3588-php-grf", "syscon";
reg = <0x0 0xfd5b0000 0x0 0x1000>;
@@ -593,6 +640,74 @@
status = "disabled";
};
+ vop: vop@fdd90000 {
+ compatible = "rockchip,rk3588-vop";
+ reg = <0x0 0xfdd90000 0x0 0x4200>, <0x0 0xfdd95000 0x0 0x1000>;
+ reg-names = "vop", "gamma-lut";
+ interrupts = <GIC_SPI 156 IRQ_TYPE_LEVEL_HIGH 0>;
+ clocks = <&cru ACLK_VOP>,
+ <&cru HCLK_VOP>,
+ <&cru DCLK_VOP0>,
+ <&cru DCLK_VOP1>,
+ <&cru DCLK_VOP2>,
+ <&cru DCLK_VOP3>,
+ <&cru PCLK_VOP_ROOT>;
+ clock-names = "aclk",
+ "hclk",
+ "dclk_vp0",
+ "dclk_vp1",
+ "dclk_vp2",
+ "dclk_vp3",
+ "pclk_vop";
+ iommus = <&vop_mmu>;
+ power-domains = <&power RK3588_PD_VOP>;
+ rockchip,grf = <&sys_grf>;
+ rockchip,vop-grf = <&vop_grf>;
+ rockchip,vo1-grf = <&vo1_grf>;
+ rockchip,pmu = <&pmu>;
+ status = "disabled";
+
+ vop_out: ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ vp0: port@0 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0>;
+ };
+
+ vp1: port@1 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <1>;
+ };
+
+ vp2: port@2 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <2>;
+ };
+
+ vp3: port@3 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <3>;
+ };
+ };
+ };
+
+ vop_mmu: iommu@fdd97e00 {
+ compatible = "rockchip,rk3588-iommu", "rockchip,rk3568-iommu";
+ reg = <0x0 0xfdd97e00 0x0 0x100>, <0x0 0xfdd97f00 0x0 0x100>;
+ interrupts = <GIC_SPI 156 IRQ_TYPE_LEVEL_HIGH 0>;
+ clocks = <&cru ACLK_VOP>, <&cru HCLK_VOP>;
+ clock-names = "aclk", "iface";
+ #iommu-cells = <0>;
+ power-domains = <&power RK3588_PD_VOP>;
+ status = "disabled";
+ };
+
uart0: serial@fd890000 {
compatible = "rockchip,rk3588-uart", "snps,dw-apb-uart";
reg = <0x0 0xfd890000 0x0 0x100>;
@@ -916,6 +1031,7 @@
reg = <RK3588_PD_USB>;
clocks = <&cru PCLK_PHP_ROOT>,
<&cru ACLK_USB_ROOT>,
+ <&cru ACLK_USB>,
<&cru HCLK_USB_ROOT>,
<&cru HCLK_HOST0>,
<&cru HCLK_HOST_ARB0>,
diff --git a/dts/upstream/src/arm64/sprd/ums512.dtsi b/dts/upstream/src/arm64/sprd/ums512.dtsi
index 024be59..dbdb79f 100644
--- a/dts/upstream/src/arm64/sprd/ums512.dtsi
+++ b/dts/upstream/src/arm64/sprd/ums512.dtsi
@@ -96,7 +96,7 @@
CPU6: cpu@600 {
device_type = "cpu";
- compatible = "arm,cortex-a55";
+ compatible = "arm,cortex-a75";
reg = <0x0 0x600>;
enable-method = "psci";
cpu-idle-states = <&CORE_PD>;
@@ -104,7 +104,7 @@
CPU7: cpu@700 {
device_type = "cpu";
- compatible = "arm,cortex-a55";
+ compatible = "arm,cortex-a75";
reg = <0x0 0x700>;
enable-method = "psci";
cpu-idle-states = <&CORE_PD>;
@@ -113,7 +113,7 @@
idle-states {
entry-method = "psci";
- CORE_PD: core-pd {
+ CORE_PD: cpu-pd {
compatible = "arm,idle-state";
entry-latency-us = <4000>;
exit-latency-us = <4000>;
@@ -291,6 +291,7 @@
pll2: clock-controller@0 {
compatible = "sprd,ums512-gc-pll";
reg = <0x0 0x100>;
+ clocks = <&ext_26m>;
clock-names = "ext-26m";
#clock-cells = <1>;
};
@@ -682,8 +683,8 @@
compatible = "arm,coresight-etm4x", "arm,primecell";
reg = <0 0x3f040000 0 0x1000>;
cpu = <&CPU0>;
- clocks = <&ext_26m>, <&aon_clk CLK_CSSYS>, <&pll2 CLK_TWPLL_512M>;
- clock-names = "apb_pclk", "clk_cs", "cs_src";
+ clocks = <&ext_26m>;
+ clock-names = "apb_pclk";
out-ports {
port {
@@ -699,8 +700,8 @@
compatible = "arm,coresight-etm4x", "arm,primecell";
reg = <0 0x3f140000 0 0x1000>;
cpu = <&CPU1>;
- clocks = <&ext_26m>, <&aon_clk CLK_CSSYS>, <&pll2 CLK_TWPLL_512M>;
- clock-names = "apb_pclk", "clk_cs", "cs_src";
+ clocks = <&ext_26m>;
+ clock-names = "apb_pclk";
out-ports {
port {
@@ -716,8 +717,8 @@
compatible = "arm,coresight-etm4x", "arm,primecell";
reg = <0 0x3f240000 0 0x1000>;
cpu = <&CPU2>;
- clocks = <&ext_26m>, <&aon_clk CLK_CSSYS>, <&pll2 CLK_TWPLL_512M>;
- clock-names = "apb_pclk", "clk_cs", "cs_src";
+ clocks = <&ext_26m>;
+ clock-names = "apb_pclk";
out-ports {
port {
@@ -733,8 +734,8 @@
compatible = "arm,coresight-etm4x", "arm,primecell";
reg = <0 0x3f340000 0 0x1000>;
cpu = <&CPU3>;
- clocks = <&ext_26m>, <&aon_clk CLK_CSSYS>, <&pll2 CLK_TWPLL_512M>;
- clock-names = "apb_pclk", "clk_cs", "cs_src";
+ clocks = <&ext_26m>;
+ clock-names = "apb_pclk";
out-ports {
port {
@@ -750,8 +751,8 @@
compatible = "arm,coresight-etm4x", "arm,primecell";
reg = <0 0x3f440000 0 0x1000>;
cpu = <&CPU4>;
- clocks = <&ext_26m>, <&aon_clk CLK_CSSYS>, <&pll2 CLK_TWPLL_512M>;
- clock-names = "apb_pclk", "clk_cs", "cs_src";
+ clocks = <&ext_26m>;
+ clock-names = "apb_pclk";
out-ports {
port {
@@ -767,8 +768,8 @@
compatible = "arm,coresight-etm4x", "arm,primecell";
reg = <0 0x3f540000 0 0x1000>;
cpu = <&CPU5>;
- clocks = <&ext_26m>, <&aon_clk CLK_CSSYS>, <&pll2 CLK_TWPLL_512M>;
- clock-names = "apb_pclk", "clk_cs", "cs_src";
+ clocks = <&ext_26m>;
+ clock-names = "apb_pclk";
out-ports {
port {
@@ -784,8 +785,8 @@
compatible = "arm,coresight-etm4x", "arm,primecell";
reg = <0 0x3f640000 0 0x1000>;
cpu = <&CPU6>;
- clocks = <&ext_26m>, <&aon_clk CLK_CSSYS>, <&pll2 CLK_TWPLL_512M>;
- clock-names = "apb_pclk", "clk_cs", "cs_src";
+ clocks = <&ext_26m>;
+ clock-names = "apb_pclk";
out-ports {
port {
@@ -801,8 +802,8 @@
compatible = "arm,coresight-etm4x", "arm,primecell";
reg = <0 0x3f740000 0 0x1000>;
cpu = <&CPU7>;
- clocks = <&ext_26m>, <&aon_clk CLK_CSSYS>, <&pll2 CLK_TWPLL_512M>;
- clock-names = "apb_pclk", "clk_cs", "cs_src";
+ clocks = <&ext_26m>;
+ clock-names = "apb_pclk";
out-ports {
port {
diff --git a/dts/upstream/src/arm64/sprd/ums9620-2h10.dts b/dts/upstream/src/arm64/sprd/ums9620-2h10.dts
new file mode 100644
index 0000000..b356711
--- /dev/null
+++ b/dts/upstream/src/arm64/sprd/ums9620-2h10.dts
@@ -0,0 +1,38 @@
+// SPDX-License-Identifier: (GPL-2.0 OR MIT)
+/*
+ * Unisoc UMS9620-2h10 board DTS file
+ *
+ * Copyright (C) 2023, Unisoc Inc.
+ */
+
+/dts-v1/;
+
+#include "ums9620.dtsi"
+
+/ {
+ model = "Unisoc UMS9620-2H10 Board";
+
+ compatible = "sprd,ums9620-2h10", "sprd,ums9620";
+
+ aliases {
+ serial0 = &uart0;
+ serial1 = &uart1;
+ };
+
+ memory@80000000 {
+ device_type = "memory";
+ reg = <0x0 0x80000000 0x2 0x00000000>;
+ };
+
+ chosen {
+ stdout-path = "serial1:921600n8";
+ };
+};
+
+&uart0 {
+ status = "okay";
+};
+
+&uart1 {
+ status = "okay";
+};
diff --git a/dts/upstream/src/arm64/sprd/ums9620.dtsi b/dts/upstream/src/arm64/sprd/ums9620.dtsi
new file mode 100644
index 0000000..2191f0a
--- /dev/null
+++ b/dts/upstream/src/arm64/sprd/ums9620.dtsi
@@ -0,0 +1,245 @@
+// SPDX-License-Identifier: (GPL-2.0 OR MIT)
+/*
+ * Unisoc UMS9620 DTS file
+ *
+ * Copyright (C) 2023, Unisoc Inc.
+ */
+
+#include <dt-bindings/interrupt-controller/arm-gic.h>
+
+/ {
+ interrupt-parent = <&gic>;
+ #address-cells = <2>;
+ #size-cells = <2>;
+
+ cpus {
+ #address-cells = <2>;
+ #size-cells = <0>;
+
+ cpu-map {
+ cluster0 {
+ core0 {
+ cpu = <&CPU0>;
+ };
+ core1 {
+ cpu = <&CPU1>;
+ };
+ core2 {
+ cpu = <&CPU2>;
+ };
+ core3 {
+ cpu = <&CPU3>;
+ };
+ core4 {
+ cpu = <&CPU4>;
+ };
+ core5 {
+ cpu = <&CPU5>;
+ };
+ core6 {
+ cpu = <&CPU6>;
+ };
+ core7 {
+ cpu = <&CPU7>;
+ };
+ };
+ };
+
+ CPU0: cpu@0 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a55";
+ reg = <0x0 0x0>;
+ enable-method = "psci";
+ cpu-idle-states = <&LIT_CORE_PD>;
+ };
+
+ CPU1: cpu@100 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a55";
+ reg = <0x0 0x100>;
+ enable-method = "psci";
+ cpu-idle-states = <&LIT_CORE_PD>;
+ };
+
+ CPU2: cpu@200 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a55";
+ reg = <0x0 0x200>;
+ enable-method = "psci";
+ cpu-idle-states = <&LIT_CORE_PD>;
+ };
+
+ CPU3: cpu@300 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a55";
+ reg = <0x0 0x300>;
+ enable-method = "psci";
+ cpu-idle-states = <&LIT_CORE_PD>;
+ };
+
+ CPU4: cpu@400 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a76";
+ reg = <0x0 0x400>;
+ enable-method = "psci";
+ cpu-idle-states = <&BIG_CORE_PD>;
+ };
+
+ CPU5: cpu@500 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a76";
+ reg = <0x0 0x500>;
+ enable-method = "psci";
+ cpu-idle-states = <&BIG_CORE_PD>;
+ };
+
+ CPU6: cpu@600 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a76";
+ reg = <0x0 0x600>;
+ enable-method = "psci";
+ cpu-idle-states = <&BIG_CORE_PD>;
+ };
+
+ CPU7: cpu@700 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a76";
+ reg = <0x0 0x700>;
+ enable-method = "psci";
+ cpu-idle-states = <&BIG_CORE_PD>;
+ };
+ };
+
+ idle-states {
+ entry-method = "psci";
+ LIT_CORE_PD: cpu-pd-lit {
+ compatible = "arm,idle-state";
+ entry-latency-us = <1000>;
+ exit-latency-us = <500>;
+ min-residency-us = <2500>;
+ local-timer-stop;
+ arm,psci-suspend-param = <0x00010000>;
+ };
+
+ BIG_CORE_PD: cpu-pd-big {
+ compatible = "arm,idle-state";
+ entry-latency-us = <4000>;
+ exit-latency-us = <4000>;
+ min-residency-us = <10000>;
+ local-timer-stop;
+ arm,psci-suspend-param = <0x00010000>;
+ };
+ };
+
+ psci {
+ compatible = "arm,psci-0.2";
+ method = "smc";
+ };
+
+ timer {
+ compatible = "arm,armv8-timer";
+ interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_HIGH>, /* Physical Secure PPI */
+ <GIC_PPI 14 IRQ_TYPE_LEVEL_HIGH>, /* Physical Non-Secure PPI */
+ <GIC_PPI 11 IRQ_TYPE_LEVEL_HIGH>, /* Virtual PPI */
+ <GIC_PPI 10 IRQ_TYPE_LEVEL_HIGH>; /* Hipervisor PPI */
+ };
+
+ pmu {
+ compatible = "arm,armv8-pmuv3";
+ interrupts = <GIC_SPI 177 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 178 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 179 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 180 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 181 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 182 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>;
+ };
+
+ soc: soc {
+ compatible = "simple-bus";
+ ranges;
+ #address-cells = <2>;
+ #size-cells = <2>;
+
+ gic: interrupt-controller@12000000 {
+ compatible = "arm,gic-v3";
+ reg = <0x0 0x12000000 0 0x20000>, /* GICD */
+ <0x0 0x12040000 0 0x100000>; /* GICR */
+ #interrupt-cells = <3>;
+ #address-cells = <2>;
+ #size-cells = <2>;
+ redistributor-stride = <0x0 0x20000>; /* 128KB stride */
+ #redistributor-regions = <1>;
+ interrupt-controller;
+ interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
+ };
+
+ apb@20200000 {
+ compatible = "simple-bus";
+ ranges = <0 0 0x20200000 0x100000>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ uart0: serial@0 {
+ compatible = "sprd,ums9620-uart",
+ "sprd,sc9836-uart";
+ reg = <0 0x100>;
+ interrupts = <GIC_SPI 196 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&ext_26m>;
+ status = "disabled";
+ };
+
+ uart1: serial@10000 {
+ compatible = "sprd,ums9620-uart",
+ "sprd,sc9836-uart";
+ reg = <0x10000 0x100>;
+ interrupts = <GIC_SPI 195 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&ext_26m>;
+ status = "disabled";
+ };
+ };
+ };
+
+ ext_26m: clk-26m {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <26000000>;
+ clock-output-names = "ext-26m";
+ };
+
+ ext_4m: clk-4m {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <4000000>;
+ clock-output-names = "ext-4m";
+ };
+
+ ext_32k: clk-32k {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <32768>;
+ clock-output-names = "ext-32k";
+ };
+
+ rco_100m: clk-100m {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <100000000>;
+ clock-output-names = "rco-100m";
+ };
+
+ dphy_312m5: dphy-312m5 {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <312500000>;
+ clock-output-names = "dphy-312m5";
+ };
+
+ dphy_416m7: dphy-416m7 {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <416700000>;
+ clock-output-names = "dphy-416m7";
+ };
+};
diff --git a/dts/upstream/src/arm64/st/stm32mp251.dtsi b/dts/upstream/src/arm64/st/stm32mp251.dtsi
index 124403f..96859d0 100644
--- a/dts/upstream/src/arm64/st/stm32mp251.dtsi
+++ b/dts/upstream/src/arm64/st/stm32mp251.dtsi
@@ -140,6 +140,22 @@
};
};
+ bsec: efuse@44000000 {
+ compatible = "st,stm32mp25-bsec";
+ reg = <0x44000000 0x1000>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ part_number_otp@24 {
+ reg = <0x24 0x4>;
+ };
+
+ package_otp@1e8 {
+ reg = <0x1e8 0x1>;
+ bits = <0 3>;
+ };
+ };
+
syscfg: syscon@44230000 {
compatible = "st,stm32mp25-syscfg", "syscon";
reg = <0x44230000 0x10000>;
diff --git a/dts/upstream/src/arm64/tesla/fsd.dtsi b/dts/upstream/src/arm64/tesla/fsd.dtsi
index bb50a9f..aaffb50 100644
--- a/dts/upstream/src/arm64/tesla/fsd.dtsi
+++ b/dts/upstream/src/arm64/tesla/fsd.dtsi
@@ -342,6 +342,18 @@
#clock-cells = <0>;
};
+ reserved-memory {
+ #address-cells = <2>;
+ #size-cells = <2>;
+ ranges;
+
+ mfc_left: region@84000000 {
+ compatible = "shared-dma-pool";
+ no-map;
+ reg = <0 0x84000000 0 0x8000000>;
+ };
+ };
+
soc: soc@0 {
compatible = "simple-bus";
#address-cells = <2>;
@@ -581,7 +593,7 @@
};
serial_0: serial@14180000 {
- compatible = "samsung,exynos4210-uart";
+ compatible = "tesla,fsd-uart", "samsung,exynos4210-uart";
reg = <0x0 0x14180000 0x0 0x100>;
interrupts = <GIC_SPI 171 IRQ_TYPE_LEVEL_HIGH>;
dmas = <&pdma1 1>, <&pdma1 0>;
@@ -593,7 +605,7 @@
};
serial_1: serial@14190000 {
- compatible = "samsung,exynos4210-uart";
+ compatible = "tesla,fsd-uart", "samsung,exynos4210-uart";
reg = <0x0 0x14190000 0x0 0x100>;
interrupts = <GIC_SPI 172 IRQ_TYPE_LEVEL_HIGH>;
dmas = <&pdma1 3>, <&pdma1 2>;
@@ -605,12 +617,12 @@
};
pmu_system_controller: system-controller@11400000 {
- compatible = "samsung,exynos7-pmu", "syscon";
+ compatible = "tesla,fsd-pmu", "samsung,exynos7-pmu", "syscon";
reg = <0x0 0x11400000 0x0 0x5000>;
};
watchdog_0: watchdog@100a0000 {
- compatible = "samsung,exynos7-wdt";
+ compatible = "tesla,fsd-wdt", "samsung,exynos7-wdt";
reg = <0x0 0x100a0000 0x0 0x100>;
interrupts = <GIC_SPI 471 IRQ_TYPE_LEVEL_HIGH>;
samsung,syscon-phandle = <&pmu_system_controller>;
@@ -619,7 +631,7 @@
};
watchdog_1: watchdog@100b0000 {
- compatible = "samsung,exynos7-wdt";
+ compatible = "tesla,fsd-wdt", "samsung,exynos7-wdt";
reg = <0x0 0x100b0000 0x0 0x100>;
interrupts = <GIC_SPI 472 IRQ_TYPE_LEVEL_HIGH>;
samsung,syscon-phandle = <&pmu_system_controller>;
@@ -628,7 +640,7 @@
};
watchdog_2: watchdog@100c0000 {
- compatible = "samsung,exynos7-wdt";
+ compatible = "tesla,fsd-wdt", "samsung,exynos7-wdt";
reg = <0x0 0x100c0000 0x0 0x100>;
interrupts = <GIC_SPI 473 IRQ_TYPE_LEVEL_HIGH>;
samsung,syscon-phandle = <&pmu_system_controller>;
@@ -637,7 +649,7 @@
};
pwm_0: pwm@14100000 {
- compatible = "samsung,exynos4210-pwm";
+ compatible = "tesla,fsd-pwm", "samsung,exynos4210-pwm";
reg = <0x0 0x14100000 0x0 0x100>;
samsung,pwm-outputs = <0>, <1>, <2>, <3>;
#pwm-cells = <3>;
@@ -647,7 +659,7 @@
};
pwm_1: pwm@14110000 {
- compatible = "samsung,exynos4210-pwm";
+ compatible = "tesla,fsd-pwm", "samsung,exynos4210-pwm";
reg = <0x0 0x14110000 0x0 0x100>;
samsung,pwm-outputs = <0>, <1>, <2>, <3>;
#pwm-cells = <3>;
@@ -657,7 +669,7 @@
};
hsi2c_0: i2c@14200000 {
- compatible = "samsung,exynos7-hsi2c";
+ compatible = "tesla,fsd-hsi2c", "samsung,exynos7-hsi2c";
reg = <0x0 0x14200000 0x0 0x1000>;
interrupts = <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>;
#address-cells = <1>;
@@ -670,7 +682,7 @@
};
hsi2c_1: i2c@14210000 {
- compatible = "samsung,exynos7-hsi2c";
+ compatible = "tesla,fsd-hsi2c", "samsung,exynos7-hsi2c";
reg = <0x0 0x14210000 0x0 0x1000>;
interrupts = <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>;
#address-cells = <1>;
@@ -683,7 +695,7 @@
};
hsi2c_2: i2c@14220000 {
- compatible = "samsung,exynos7-hsi2c";
+ compatible = "tesla,fsd-hsi2c", "samsung,exynos7-hsi2c";
reg = <0x0 0x14220000 0x0 0x1000>;
interrupts = <GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH>;
#address-cells = <1>;
@@ -696,7 +708,7 @@
};
hsi2c_3: i2c@14230000 {
- compatible = "samsung,exynos7-hsi2c";
+ compatible = "tesla,fsd-hsi2c", "samsung,exynos7-hsi2c";
reg = <0x0 0x14230000 0x0 0x1000>;
interrupts = <GIC_SPI 151 IRQ_TYPE_LEVEL_HIGH>;
#address-cells = <1>;
@@ -709,7 +721,7 @@
};
hsi2c_4: i2c@14240000 {
- compatible = "samsung,exynos7-hsi2c";
+ compatible = "tesla,fsd-hsi2c", "samsung,exynos7-hsi2c";
reg = <0x0 0x14240000 0x0 0x1000>;
interrupts = <GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>;
#address-cells = <1>;
@@ -722,7 +734,7 @@
};
hsi2c_5: i2c@14250000 {
- compatible = "samsung,exynos7-hsi2c";
+ compatible = "tesla,fsd-hsi2c", "samsung,exynos7-hsi2c";
reg = <0x0 0x14250000 0x0 0x1000>;
interrupts = <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>;
#address-cells = <1>;
@@ -735,7 +747,7 @@
};
hsi2c_6: i2c@14260000 {
- compatible = "samsung,exynos7-hsi2c";
+ compatible = "tesla,fsd-hsi2c", "samsung,exynos7-hsi2c";
reg = <0x0 0x14260000 0x0 0x1000>;
interrupts = <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>;
#address-cells = <1>;
@@ -748,7 +760,7 @@
};
hsi2c_7: i2c@14270000 {
- compatible = "samsung,exynos7-hsi2c";
+ compatible = "tesla,fsd-hsi2c", "samsung,exynos7-hsi2c";
reg = <0x0 0x14270000 0x0 0x1000>;
interrupts = <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>;
#address-cells = <1>;
@@ -956,6 +968,15 @@
clock-names = "fin_pll", "mct";
};
+ mfc: mfc@12880000 {
+ compatible = "tesla,fsd-mfc";
+ reg = <0x0 0x12880000 0x0 0x10000>;
+ interrupts = <GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>;
+ clock-names = "mfc";
+ clocks = <&clock_mfc MFC_MFC_IPCLKPORT_ACLK>;
+ memory-region = <&mfc_left>;
+ };
+
ufs: ufs@15120000 {
compatible = "tesla,fsd-ufs";
reg = <0x0 0x15120000 0x0 0x200>, /* 0: HCI standard */
diff --git a/dts/upstream/src/arm64/ti/k3-am62-main.dtsi b/dts/upstream/src/arm64/ti/k3-am62-main.dtsi
index e5c64c8..464b756 100644
--- a/dts/upstream/src/arm64/ti/k3-am62-main.dtsi
+++ b/dts/upstream/src/arm64/ti/k3-am62-main.dtsi
@@ -121,8 +121,13 @@
<0x00 0x4c000000 0x00 0x20000>,
<0x00 0x4a820000 0x00 0x20000>,
<0x00 0x4aa40000 0x00 0x20000>,
- <0x00 0x4bc00000 0x00 0x100000>;
- reg-names = "gcfg", "bchanrt", "rchanrt", "tchanrt", "ringrt";
+ <0x00 0x4bc00000 0x00 0x100000>,
+ <0x00 0x48600000 0x00 0x8000>,
+ <0x00 0x484a4000 0x00 0x2000>,
+ <0x00 0x484c2000 0x00 0x2000>,
+ <0x00 0x48420000 0x00 0x2000>;
+ reg-names = "gcfg", "bchanrt", "rchanrt", "tchanrt", "ringrt",
+ "ring", "tchan", "rchan", "bchan";
msi-parent = <&inta_main_dmss>;
#dma-cells = <3>;
@@ -138,8 +143,13 @@
reg = <0x00 0x485c0000 0x00 0x100>,
<0x00 0x4a800000 0x00 0x20000>,
<0x00 0x4aa00000 0x00 0x40000>,
- <0x00 0x4b800000 0x00 0x400000>;
- reg-names = "gcfg", "rchanrt", "tchanrt", "ringrt";
+ <0x00 0x4b800000 0x00 0x400000>,
+ <0x00 0x485e0000 0x00 0x10000>,
+ <0x00 0x484a0000 0x00 0x2000>,
+ <0x00 0x484c0000 0x00 0x2000>,
+ <0x00 0x48430000 0x00 0x1000>;
+ reg-names = "gcfg", "rchanrt", "tchanrt", "ringrt",
+ "ring", "tchan", "rchan", "rflow";
msi-parent = <&inta_main_dmss>;
#dma-cells = <2>;
@@ -502,6 +512,9 @@
main_gpio0: gpio@600000 {
compatible = "ti,am64-gpio", "ti,keystone-gpio";
reg = <0x0 0x00600000 0x0 0x100>;
+ gpio-ranges = <&main_pmx0 0 0 32>,
+ <&main_pmx0 32 33 38>,
+ <&main_pmx0 70 72 22>;
gpio-controller;
#gpio-cells = <2>;
interrupt-parent = <&main_gpio_intr>;
@@ -520,6 +533,10 @@
compatible = "ti,am64-gpio", "ti,keystone-gpio";
reg = <0x0 0x00601000 0x0 0x100>;
gpio-controller;
+ gpio-ranges = <&main_pmx0 0 94 41>,
+ <&main_pmx0 41 136 6>,
+ <&main_pmx0 47 143 3>,
+ <&main_pmx0 50 149 2>;
#gpio-cells = <2>;
interrupt-parent = <&main_gpio_intr>;
interrupts = <180>, <181>, <182>,
@@ -675,6 +692,15 @@
};
};
+ gpu: gpu@fd00000 {
+ compatible = "ti,am62-gpu", "img,img-axe";
+ reg = <0x00 0x0fd00000 0x00 0x20000>;
+ clocks = <&k3_clks 187 0>;
+ clock-names = "core";
+ interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
+ power-domains = <&k3_pds 187 TI_SCI_PD_EXCLUSIVE>;
+ };
+
cpsw3g: ethernet@8000000 {
compatible = "ti,am642-cpsw-nuss";
#address-cells = <2>;
@@ -965,4 +991,66 @@
power-domains = <&k3_pds 192 TI_SCI_PD_EXCLUSIVE>;
status = "disabled";
};
+
+ ti_csi2rx0: ticsi2rx@30102000 {
+ compatible = "ti,j721e-csi2rx-shim";
+ dmas = <&main_bcdma 0 0x4700 0>;
+ dma-names = "rx0";
+ reg = <0x00 0x30102000 0x00 0x1000>;
+ power-domains = <&k3_pds 182 TI_SCI_PD_EXCLUSIVE>;
+ #address-cells = <2>;
+ #size-cells = <2>;
+ ranges;
+ status = "disabled";
+
+ cdns_csi2rx0: csi-bridge@30101000 {
+ compatible = "ti,j721e-csi2rx", "cdns,csi2rx";
+ reg = <0x00 0x30101000 0x00 0x1000>;
+ clocks = <&k3_clks 182 0>, <&k3_clks 182 3>, <&k3_clks 182 0>,
+ <&k3_clks 182 0>, <&k3_clks 182 4>, <&k3_clks 182 4>;
+ clock-names = "sys_clk", "p_clk", "pixel_if0_clk",
+ "pixel_if1_clk", "pixel_if2_clk", "pixel_if3_clk";
+ phys = <&dphy0>;
+ phy-names = "dphy";
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ csi0_port0: port@0 {
+ reg = <0>;
+ status = "disabled";
+ };
+
+ csi0_port1: port@1 {
+ reg = <1>;
+ status = "disabled";
+ };
+
+ csi0_port2: port@2 {
+ reg = <2>;
+ status = "disabled";
+ };
+
+ csi0_port3: port@3 {
+ reg = <3>;
+ status = "disabled";
+ };
+
+ csi0_port4: port@4 {
+ reg = <4>;
+ status = "disabled";
+ };
+ };
+ };
+ };
+
+ dphy0: phy@30110000 {
+ compatible = "cdns,dphy-rx";
+ reg = <0x00 0x30110000 0x00 0x1100>;
+ #phy-cells = <0>;
+ power-domains = <&k3_pds 185 TI_SCI_PD_EXCLUSIVE>;
+ status = "disabled";
+ };
+
};
diff --git a/dts/upstream/src/arm64/ti/k3-am62-verdin-dahlia.dtsi b/dts/upstream/src/arm64/ti/k3-am62-verdin-dahlia.dtsi
index 013357d..bf6d27e 100644
--- a/dts/upstream/src/arm64/ti/k3-am62-verdin-dahlia.dtsi
+++ b/dts/upstream/src/arm64/ti/k3-am62-verdin-dahlia.dtsi
@@ -214,6 +214,5 @@
/* Verdin UART_2 */
&wkup_uart0 {
- /* FIXME: WKUP UART0 is used by DM firmware */
- status = "reserved";
+ status = "okay";
};
diff --git a/dts/upstream/src/arm64/ti/k3-am62-verdin-dev.dtsi b/dts/upstream/src/arm64/ti/k3-am62-verdin-dev.dtsi
index 6701cb8..6800716 100644
--- a/dts/upstream/src/arm64/ti/k3-am62-verdin-dev.dtsi
+++ b/dts/upstream/src/arm64/ti/k3-am62-verdin-dev.dtsi
@@ -235,6 +235,5 @@
/* Verdin UART_2 */
&wkup_uart0 {
- /* FIXME: WKUP UART0 is used by DM firmware */
- status = "reserved";
+ status = "okay";
};
diff --git a/dts/upstream/src/arm64/ti/k3-am62-verdin-mallow.dtsi b/dts/upstream/src/arm64/ti/k3-am62-verdin-mallow.dtsi
new file mode 100644
index 0000000..17b9353
--- /dev/null
+++ b/dts/upstream/src/arm64/ti/k3-am62-verdin-mallow.dtsi
@@ -0,0 +1,188 @@
+// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
+/*
+ * Copyright 2023 Toradex
+ *
+ * Common dtsi for Verdin AM62 SoM on Mallow carrier board
+ *
+ * https://www.toradex.com/computer-on-modules/verdin-arm-family/ti-am62
+ * https://www.toradex.com/products/carrier-board/mallow-carrier-board
+ */
+
+#include <dt-bindings/leds/common.h>
+
+/ {
+ leds {
+ compatible = "gpio-leds";
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_qspi1_clk_gpio>,
+ <&pinctrl_qspi1_cs_gpio>,
+ <&pinctrl_qspi1_io0_gpio>,
+ <&pinctrl_qspi1_io1_gpio>;
+
+ /* SODIMM 52 - USER_LED_1_RED */
+ led-0 {
+ color = <LED_COLOR_ID_RED>;
+ function = LED_FUNCTION_DEBUG;
+ function-enumerator = <1>;
+ gpios = <&main_gpio0 0 GPIO_ACTIVE_HIGH>;
+ };
+
+ /* SODIMM 54 - USER_LED_1_GREEN */
+ led-1 {
+ color = <LED_COLOR_ID_GREEN>;
+ function = LED_FUNCTION_DEBUG;
+ function-enumerator = <1>;
+ gpios = <&main_gpio0 11 GPIO_ACTIVE_HIGH>;
+ };
+
+ /* SODIMM 56 - USER_LED_2_RED */
+ led-2 {
+ color = <LED_COLOR_ID_RED>;
+ function = LED_FUNCTION_DEBUG;
+ function-enumerator = <2>;
+ gpios = <&main_gpio0 3 GPIO_ACTIVE_HIGH>;
+ };
+
+ /* SODIMM 58 - USER_LED_2_GREEN */
+ led-3 {
+ color = <LED_COLOR_ID_GREEN>;
+ function = LED_FUNCTION_DEBUG;
+ function-enumerator = <2>;
+ gpios = <&main_gpio0 4 GPIO_ACTIVE_HIGH>;
+ };
+ };
+};
+
+/* Verdin ETH */
+&cpsw3g {
+ status = "okay";
+};
+
+/* Verdin MDIO */
+&cpsw3g_mdio {
+ status = "okay";
+};
+
+/* Verdin ETH_1*/
+&cpsw_port1 {
+ status = "okay";
+};
+
+/* Verdin PWM_1 and PWM_2*/
+&epwm0 {
+ status = "okay";
+};
+
+/* Verdin PWM_3 DSI */
+&epwm1 {
+ status = "okay";
+};
+
+&main_gpio0 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_ctrl_sleep_moci>,
+ <&pinctrl_gpio_1>,
+ <&pinctrl_gpio_2>,
+ <&pinctrl_gpio_3>,
+ <&pinctrl_gpio_4>;
+};
+
+/* Verdin I2C_1 */
+&main_i2c1 {
+ status = "okay";
+
+ /* Temperature sensor */
+ sensor@4f {
+ compatible = "ti,tmp1075";
+ reg = <0x4f>;
+ };
+
+ /* EEPROM */
+ eeprom@57 {
+ compatible = "st,24c02", "atmel,24c02";
+ reg = <0x57>;
+ pagesize = <16>;
+ };
+};
+
+/* Verdin I2C_2 DSI */
+&main_i2c2 {
+ status = "okay";
+};
+
+/* Verdin I2C_4 CSI */
+&main_i2c3 {
+ status = "okay";
+};
+
+/* Verdin CAN_1 */
+&main_mcan0 {
+ status = "okay";
+};
+
+/* Verdin SPI_1 */
+&main_spi1 {
+ pinctrl-0 = <&pinctrl_spi1>,
+ <&pinctrl_spi1_cs0>,
+ <&pinctrl_qspi1_cs2_gpio>;
+ cs-gpios = <0>, <&main_gpio0 12 GPIO_ACTIVE_LOW>;
+ status = "okay";
+};
+
+/* Verdin UART_3 */
+&main_uart0 {
+ status = "okay";
+};
+
+/* Verdin UART_1 */
+&main_uart1 {
+ status = "okay";
+};
+
+/* Verdin I2C_3_HDMI */
+&mcu_i2c0 {
+ status = "okay";
+};
+
+/* Verdin CAN_2 */
+&mcu_mcan0 {
+ status = "okay";
+};
+
+/* Verdin UART_4 */
+&mcu_uart0 {
+ status = "okay";
+};
+
+/* Verdin SD_1 */
+&sdhci1 {
+ status = "okay";
+};
+
+/* Verdin USB_1 */
+&usbss0 {
+ status = "okay";
+};
+
+&usb0 {
+ status = "okay";
+};
+
+/* Verdin USB_2 */
+&usbss1 {
+ status = "okay";
+};
+
+&usb1 {
+ status = "okay";
+};
+
+/* Verdin CTRL_WAKE1_MICO# */
+&verdin_gpio_keys {
+ status = "okay";
+};
+
+/* Verdin UART_2 */
+&wkup_uart0 {
+ status = "okay";
+};
diff --git a/dts/upstream/src/arm64/ti/k3-am62-verdin-yavia.dtsi b/dts/upstream/src/arm64/ti/k3-am62-verdin-yavia.dtsi
index c685df7..997dfaf 100644
--- a/dts/upstream/src/arm64/ti/k3-am62-verdin-yavia.dtsi
+++ b/dts/upstream/src/arm64/ti/k3-am62-verdin-yavia.dtsi
@@ -207,6 +207,5 @@
/* Verdin UART_2 */
&wkup_uart0 {
- /* FIXME: WKUP UART0 is used by DM firmware */
- status = "reserved";
+ status = "okay";
};
diff --git a/dts/upstream/src/arm64/ti/k3-am62-verdin.dtsi b/dts/upstream/src/arm64/ti/k3-am62-verdin.dtsi
index 5db52f2..6a06724 100644
--- a/dts/upstream/src/arm64/ti/k3-am62-verdin.dtsi
+++ b/dts/upstream/src/arm64/ti/k3-am62-verdin.dtsi
@@ -233,6 +233,13 @@
>;
};
+ /* Verdin SPI_1 CS as GPIO */
+ pinctrl_qspi1_io4_gpio: main-gpio0-7-default-pins {
+ pinctrl-single,pins = <
+ AM62X_IOPAD(0x001c, PIN_INPUT, 7) /* (J23) OSPI0_D4.GPIO0_7 */ /* SODIMM 202 */
+ >;
+ };
+
/* Verdin QSPI_1_CS# as GPIO (conflict with Verdin QSPI_1 interface) */
pinctrl_qspi1_cs_gpio: main-gpio0-11-default-pins {
pinctrl-single,pins = <
@@ -599,12 +606,18 @@
pinctrl_spi1: main-spi1-default-pins {
pinctrl-single,pins = <
AM62X_IOPAD(0x0020, PIN_INPUT, 1) /* (J25) OSPI0_D5.SPI1_CLK */ /* SODIMM 196 */
- AM62X_IOPAD(0x001c, PIN_INPUT, 1) /* (J23) OSPI0_D4.SPI1_CS0 */ /* SODIMM 202 */
AM62X_IOPAD(0x0024, PIN_INPUT, 1) /* (H25) OSPI0_D6.SPI1_D0 */ /* SODIMM 200 */
AM62X_IOPAD(0x0028, PIN_INPUT, 1) /* (J22) OSPI0_D7.SPI1_D1 */ /* SODIMM 198 */
>;
};
+ /* Verdin SPI_1 CS */
+ pinctrl_spi1_cs0: main-spi1-cs0-default-pins {
+ pinctrl-single,pins = <
+ AM62X_IOPAD(0x001c, PIN_INPUT, 1) /* (J23) OSPI0_D4.SPI1_CS0 */ /* SODIMM 202 */
+ >;
+ };
+
/* ETH_25MHz_CLK */
pinctrl_eth_clock: main-system-clkout0-default-pins {
pinctrl-single,pins = <
@@ -1278,7 +1291,7 @@
/* Verdin SPI_1 */
&main_spi1 {
pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_spi1>;
+ pinctrl-0 = <&pinctrl_spi1>, <&pinctrl_spi1_cs0>;
ti,pindir-d0-out-d1-in;
status = "disabled";
};
diff --git a/dts/upstream/src/arm64/ti/k3-am625-beagleplay-csi2-ov5640.dtso b/dts/upstream/src/arm64/ti/k3-am625-beagleplay-csi2-ov5640.dtso
new file mode 100644
index 0000000..5e80ca7
--- /dev/null
+++ b/dts/upstream/src/arm64/ti/k3-am625-beagleplay-csi2-ov5640.dtso
@@ -0,0 +1,77 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * ALINX AN5641 & Digilent PCam 5C - OV5640 camera module
+ * Copyright (C) 2022-2023 Texas Instruments Incorporated - https://www.ti.com/
+ */
+
+/dts-v1/;
+/plugin/;
+
+#include <dt-bindings/gpio/gpio.h>
+
+&{/} {
+ clk_ov5640_fixed: ov5640-xclk {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <12000000>;
+ };
+};
+
+&main_gpio0 {
+ p11-hog {
+ /* P11 - CSI2_CAMERA_GPIO1 */
+ gpio-hog;
+ gpios = <11 GPIO_ACTIVE_HIGH>;
+ output-high;
+ line-name = "CSI2_CAMERA_GPIO1";
+ };
+};
+
+&wkup_i2c0 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "okay";
+
+ ov5640: camera@3c {
+ compatible = "ovti,ov5640";
+ reg = <0x3c>;
+
+ clocks = <&clk_ov5640_fixed>;
+ clock-names = "xclk";
+
+ port {
+ csi2_cam0: endpoint {
+ remote-endpoint = <&csi2rx0_in_sensor>;
+ clock-lanes = <0>;
+ data-lanes = <1 2>;
+ };
+ };
+ };
+};
+
+&cdns_csi2rx0 {
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ csi0_port0: port@0 {
+ reg = <0>;
+ status = "okay";
+
+ csi2rx0_in_sensor: endpoint {
+ remote-endpoint = <&csi2_cam0>;
+ bus-type = <4>; /* CSI2 DPHY. */
+ clock-lanes = <0>;
+ data-lanes = <1 2>;
+ };
+ };
+ };
+};
+
+&dphy0 {
+ status = "okay";
+};
+
+&ti_csi2rx0 {
+ status = "okay";
+};
diff --git a/dts/upstream/src/arm64/ti/k3-am625-beagleplay-csi2-tevi-ov5640.dtso b/dts/upstream/src/arm64/ti/k3-am625-beagleplay-csi2-tevi-ov5640.dtso
new file mode 100644
index 0000000..5e1cbbc
--- /dev/null
+++ b/dts/upstream/src/arm64/ti/k3-am625-beagleplay-csi2-tevi-ov5640.dtso
@@ -0,0 +1,77 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Technexion TEVI-OV5640-*-RPI - OV5640 camera module
+ * Copyright (C) 2022-2023 Texas Instruments Incorporated - https://www.ti.com/
+ */
+
+/dts-v1/;
+/plugin/;
+
+#include <dt-bindings/gpio/gpio.h>
+
+&{/} {
+ clk_ov5640_fixed: ov5640-xclk {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <24000000>;
+ };
+};
+
+&main_gpio0 {
+ p11-hog {
+ /* P11 - CSI2_CAMERA_GPIO1 */
+ gpio-hog;
+ gpios = <11 GPIO_ACTIVE_HIGH>;
+ output-high;
+ line-name = "CSI2_CAMERA_GPIO1";
+ };
+};
+
+&wkup_i2c0 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "okay";
+
+ ov5640: camera@3c {
+ compatible = "ovti,ov5640";
+ reg = <0x3c>;
+
+ clocks = <&clk_ov5640_fixed>;
+ clock-names = "xclk";
+
+ port {
+ csi2_cam0: endpoint {
+ remote-endpoint = <&csi2rx0_in_sensor>;
+ clock-lanes = <0>;
+ data-lanes = <1 2>;
+ };
+ };
+ };
+};
+
+&cdns_csi2rx0 {
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ csi0_port0: port@0 {
+ reg = <0>;
+ status = "okay";
+
+ csi2rx0_in_sensor: endpoint {
+ remote-endpoint = <&csi2_cam0>;
+ bus-type = <4>; /* CSI2 DPHY. */
+ clock-lanes = <0>;
+ data-lanes = <1 2>;
+ };
+ };
+ };
+};
+
+&dphy0 {
+ status = "okay";
+};
+
+&ti_csi2rx0 {
+ status = "okay";
+};
diff --git a/dts/upstream/src/arm64/ti/k3-am625-beagleplay.dts b/dts/upstream/src/arm64/ti/k3-am625-beagleplay.dts
index 9a6bd0a..eadbdd9 100644
--- a/dts/upstream/src/arm64/ti/k3-am625-beagleplay.dts
+++ b/dts/upstream/src/arm64/ti/k3-am625-beagleplay.dts
@@ -443,7 +443,7 @@
>;
};
- console_pins_default: console-default-pins {
+ main_uart0_pins_default: main-uart0-default-pins {
bootph-all;
pinctrl-single,pins = <
AM62X_IOPAD(0x01c8, PIN_INPUT, 0) /* (D14) UART0_RXD */
@@ -877,7 +877,7 @@
&main_uart0 {
bootph-all;
pinctrl-names = "default";
- pinctrl-0 = <&console_pins_default>;
+ pinctrl-0 = <&main_uart0_pins_default>;
status = "okay";
};
diff --git a/dts/upstream/src/arm64/ti/k3-am625-phyboard-lyra-rdk.dts b/dts/upstream/src/arm64/ti/k3-am625-phyboard-lyra-rdk.dts
index a438baf..4bc0134 100644
--- a/dts/upstream/src/arm64/ti/k3-am625-phyboard-lyra-rdk.dts
+++ b/dts/upstream/src/arm64/ti/k3-am625-phyboard-lyra-rdk.dts
@@ -35,6 +35,18 @@
standby-gpios = <&gpio_exp 1 GPIO_ACTIVE_HIGH>;
};
+ hdmi0: connector-hdmi {
+ compatible = "hdmi-connector";
+ label = "hdmi";
+ type = "a";
+
+ port {
+ hdmi_connector_in: endpoint {
+ remote-endpoint = <&sii9022_out>;
+ };
+ };
+ };
+
keys {
compatible = "gpio-keys";
autorepeat;
@@ -93,6 +105,37 @@
>;
};
+ hdmi_int_pins_default: hdmi-int-default-pins {
+ pinctrl-single,pins = <
+ AM62X_IOPAD(0x040, PIN_INPUT, 7) /* (N23) GPMC0_AD1.GPIO0_16 */
+ >;
+ };
+
+ main_dss0_pins_default: main-dss0-default-pins {
+ pinctrl-single,pins = <
+ AM62X_IOPAD(0x0b8, PIN_OUTPUT, 0) /* (U22) VOUT0_DATA0 */
+ AM62X_IOPAD(0x0bc, PIN_OUTPUT, 0) /* (V24) VOUT0_DATA1 */
+ AM62X_IOPAD(0x0e0, PIN_OUTPUT, 0) /* (V20) VOUT0_DATA10 */
+ AM62X_IOPAD(0x0e4, PIN_OUTPUT, 0) /* (AA23) VOUT0_DATA11 */
+ AM62X_IOPAD(0x0e8, PIN_OUTPUT, 0) /* (AB25) VOUT0_DATA12 */
+ AM62X_IOPAD(0x0ec, PIN_OUTPUT, 0) /* (AA24) VOUT0_DATA13 */
+ AM62X_IOPAD(0x0f0, PIN_OUTPUT, 0) /* (Y22) VOUT0_DATA14 */
+ AM62X_IOPAD(0x0f4, PIN_OUTPUT, 0) /* (AA21) VOUT0_DATA15 */
+ AM62X_IOPAD(0x0c0, PIN_OUTPUT, 0) /* (W25) VOUT0_DATA2 */
+ AM62X_IOPAD(0x0c4, PIN_OUTPUT, 0) /* (W24) VOUT0_DATA3 */
+ AM62X_IOPAD(0x0c8, PIN_OUTPUT, 0) /* (Y25) VOUT0_DATA4 */
+ AM62X_IOPAD(0x0cc, PIN_OUTPUT, 0) /* (Y24) VOUT0_DATA5 */
+ AM62X_IOPAD(0x0d0, PIN_OUTPUT, 0) /* (Y23) VOUT0_DATA6 */
+ AM62X_IOPAD(0x0d4, PIN_OUTPUT, 0) /* (AA25) VOUT0_DATA7 */
+ AM62X_IOPAD(0x0d8, PIN_OUTPUT, 0) /* (V21) VOUT0_DATA8 */
+ AM62X_IOPAD(0x0dc, PIN_OUTPUT, 0) /* (W21) VOUT0_DATA9 */
+ AM62X_IOPAD(0x0fc, PIN_OUTPUT, 0) /* (Y20) VOUT0_DE */
+ AM62X_IOPAD(0x0f8, PIN_OUTPUT, 0) /* (AB24) VOUT0_HSYNC */
+ AM62X_IOPAD(0x104, PIN_OUTPUT, 0) /* (AC24) VOUT0_PCLK */
+ AM62X_IOPAD(0x100, PIN_OUTPUT, 0) /* (AC25) VOUT0_VSYNC */
+ >;
+ };
+
main_i2c1_pins_default: main-i2c1-default-pins {
pinctrl-single,pins = <
AM62X_IOPAD(0x1e8, PIN_INPUT_PULLUP, 0) /* (B17) I2C1_SCL */
@@ -184,10 +227,30 @@
};
};
+&dss {
+ pinctrl-names = "default";
+ pinctrl-0 = <&main_dss0_pins_default>;
+ status = "okay";
+};
+
+&dss_ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ /* VP2: DPI/HDMI Output */
+ port@1 {
+ reg = <1>;
+
+ dpi1_out: endpoint {
+ remote-endpoint = <&sii9022_in>;
+ };
+ };
+};
+
&main_i2c1 {
pinctrl-names = "default";
pinctrl-0 = <&main_i2c1_pins_default>;
- clock-frequency = <400000>;
+ clock-frequency = <100000>;
status = "okay";
gpio_exp: gpio-expander@21 {
@@ -201,12 +264,43 @@
gpio-controller;
interrupt-controller;
#interrupt-cells = <2>;
- gpio-line-names = "GPIO0_HDMI_RST", "GPIO1_CAN0_nEN",
+ gpio-line-names = "", "GPIO1_CAN0_nEN",
"GPIO2_LED2", "GPIO3_LVDS_GPIO",
"GPIO4_BUT2", "GPIO5_LVDS_BKLT_EN",
"GPIO6_ETH1_USER_RESET", "GPIO7_AUDIO_USER_RESET";
};
+ sii9022: bridge-hdmi@39 {
+ compatible = "sil,sii9022";
+ reg = <0x39>;
+
+ interrupt-parent = <&main_gpio0>;
+ interrupts = <16 IRQ_TYPE_EDGE_FALLING>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&hdmi_int_pins_default>;
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+
+ sii9022_in: endpoint {
+ remote-endpoint = <&dpi1_out>;
+ };
+ };
+
+ port@1 {
+ reg = <1>;
+
+ sii9022_out: endpoint {
+ remote-endpoint = <&hdmi_connector_in>;
+ };
+ };
+ };
+ };
+
eeprom@51 {
compatible = "atmel,24c02";
pagesize = <16>;
diff --git a/dts/upstream/src/arm64/ti/k3-am625-verdin-nonwifi-mallow.dts b/dts/upstream/src/arm64/ti/k3-am625-verdin-nonwifi-mallow.dts
new file mode 100644
index 0000000..9cae121
--- /dev/null
+++ b/dts/upstream/src/arm64/ti/k3-am625-verdin-nonwifi-mallow.dts
@@ -0,0 +1,22 @@
+// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
+/*
+ * Copyright 2023 Toradex
+ *
+ * https://www.toradex.com/computer-on-modules/verdin-arm-family/ti-am62
+ * https://www.toradex.com/products/carrier-board/mallow-carrier-board
+ */
+
+/dts-v1/;
+
+#include "k3-am625.dtsi"
+#include "k3-am62-verdin.dtsi"
+#include "k3-am62-verdin-nonwifi.dtsi"
+#include "k3-am62-verdin-mallow.dtsi"
+
+/ {
+ model = "Toradex Verdin AM62 on Mallow Board";
+ compatible = "toradex,verdin-am62-nonwifi-mallow",
+ "toradex,verdin-am62-nonwifi",
+ "toradex,verdin-am62",
+ "ti,am625";
+};
diff --git a/dts/upstream/src/arm64/ti/k3-am625-verdin-wifi-mallow.dts b/dts/upstream/src/arm64/ti/k3-am625-verdin-wifi-mallow.dts
new file mode 100644
index 0000000..81d834b
--- /dev/null
+++ b/dts/upstream/src/arm64/ti/k3-am625-verdin-wifi-mallow.dts
@@ -0,0 +1,22 @@
+// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
+/*
+ * Copyright 2023 Toradex
+ *
+ * https://www.toradex.com/computer-on-modules/verdin-arm-family/ti-am62
+ * https://www.toradex.com/products/carrier-board/mallow-carrier-board
+ */
+
+/dts-v1/;
+
+#include "k3-am625.dtsi"
+#include "k3-am62-verdin.dtsi"
+#include "k3-am62-verdin-wifi.dtsi"
+#include "k3-am62-verdin-mallow.dtsi"
+
+/ {
+ model = "Toradex Verdin AM62 WB on Mallow Board";
+ compatible = "toradex,verdin-am62-wifi-mallow",
+ "toradex,verdin-am62-wifi",
+ "toradex,verdin-am62",
+ "ti,am625";
+};
diff --git a/dts/upstream/src/arm64/ti/k3-am62a-main.dtsi b/dts/upstream/src/arm64/ti/k3-am62a-main.dtsi
index 4ae7fdc..f0b8c9a 100644
--- a/dts/upstream/src/arm64/ti/k3-am62a-main.dtsi
+++ b/dts/upstream/src/arm64/ti/k3-am62a-main.dtsi
@@ -101,8 +101,13 @@
<0x00 0x4c000000 0x00 0x20000>,
<0x00 0x4a820000 0x00 0x20000>,
<0x00 0x4aa40000 0x00 0x20000>,
- <0x00 0x4bc00000 0x00 0x100000>;
- reg-names = "gcfg", "bchanrt", "rchanrt", "tchanrt", "ringrt";
+ <0x00 0x4bc00000 0x00 0x100000>,
+ <0x00 0x48600000 0x00 0x8000>,
+ <0x00 0x484a4000 0x00 0x2000>,
+ <0x00 0x484c2000 0x00 0x2000>,
+ <0x00 0x48420000 0x00 0x2000>;
+ reg-names = "gcfg", "bchanrt", "rchanrt", "tchanrt", "ringrt",
+ "ring", "tchan", "rchan", "bchan";
msi-parent = <&inta_main_dmss>;
#dma-cells = <3>;
ti,sci = <&dmsc>;
@@ -117,8 +122,13 @@
reg = <0x00 0x485c0000 0x00 0x100>,
<0x00 0x4a800000 0x00 0x20000>,
<0x00 0x4aa00000 0x00 0x40000>,
- <0x00 0x4b800000 0x00 0x400000>;
- reg-names = "gcfg", "rchanrt", "tchanrt", "ringrt";
+ <0x00 0x4b800000 0x00 0x400000>,
+ <0x00 0x485e0000 0x00 0x10000>,
+ <0x00 0x484a0000 0x00 0x2000>,
+ <0x00 0x484c0000 0x00 0x2000>,
+ <0x00 0x48430000 0x00 0x1000>;
+ reg-names = "gcfg", "rchanrt", "tchanrt", "ringrt",
+ "ring", "tchan", "rchan", "rflow";
msi-parent = <&inta_main_dmss>;
#dma-cells = <2>;
ti,sci = <&dmsc>;
@@ -144,6 +154,44 @@
};
};
+ dmss_csi: bus@4e000000 {
+ compatible = "simple-bus";
+ #address-cells = <2>;
+ #size-cells = <2>;
+ dma-ranges;
+ ranges = <0x00 0x4e000000 0x00 0x4e000000 0x00 0x300000>;
+
+ ti,sci-dev-id = <198>;
+
+ inta_main_dmss_csi: interrupt-controller@4e0a0000 {
+ compatible = "ti,sci-inta";
+ reg = <0x00 0x4e0a0000 0x00 0x8000>;
+ #interrupt-cells = <0>;
+ interrupt-controller;
+ interrupt-parent = <&gic500>;
+ msi-controller;
+ ti,sci = <&dmsc>;
+ ti,sci-dev-id = <200>;
+ ti,interrupt-ranges = <0 237 8>;
+ ti,unmapped-event-sources = <&main_bcdma_csi>;
+ power-domains = <&k3_pds 182 TI_SCI_PD_EXCLUSIVE>;
+ };
+
+ main_bcdma_csi: dma-controller@4e230000 {
+ compatible = "ti,am62a-dmss-bcdma-csirx";
+ reg = <0x00 0x4e230000 0x00 0x100>,
+ <0x00 0x4e180000 0x00 0x8000>,
+ <0x00 0x4e100000 0x00 0x10000>;
+ reg-names = "gcfg", "rchanrt", "ringrt";
+ msi-parent = <&inta_main_dmss_csi>;
+ #dma-cells = <3>;
+ ti,sci = <&dmsc>;
+ ti,sci-dev-id = <199>;
+ ti,sci-rm-range-rchan = <0x21>;
+ power-domains = <&k3_pds 182 TI_SCI_PD_EXCLUSIVE>;
+ };
+ };
+
dmsc: system-controller@44043000 {
compatible = "ti,k2g-sci";
reg = <0x00 0x44043000 0x00 0xfe0>;
@@ -462,7 +510,7 @@
<193>, <194>, <195>;
interrupt-controller;
#interrupt-cells = <2>;
- ti,ngpio = <87>;
+ ti,ngpio = <92>;
ti,davinci-gpio-unbanked = <0>;
power-domains = <&k3_pds 77 TI_SCI_PD_EXCLUSIVE>;
clocks = <&k3_clks 77 0>;
@@ -480,7 +528,7 @@
<183>, <184>, <185>;
interrupt-controller;
#interrupt-cells = <2>;
- ti,ngpio = <88>;
+ ti,ngpio = <52>;
ti,davinci-gpio-unbanked = <0>;
power-domains = <&k3_pds 78 TI_SCI_PD_EXCLUSIVE>;
clocks = <&k3_clks 78 0>;
@@ -876,4 +924,65 @@
power-domains = <&k3_pds 192 TI_SCI_PD_EXCLUSIVE>;
status = "disabled";
};
+
+ ti_csi2rx0: ticsi2rx@30102000 {
+ compatible = "ti,j721e-csi2rx-shim";
+ dmas = <&main_bcdma_csi 0 0x5000 0>;
+ dma-names = "rx0";
+ reg = <0x00 0x30102000 0x00 0x1000>;
+ power-domains = <&k3_pds 182 TI_SCI_PD_EXCLUSIVE>;
+ #address-cells = <2>;
+ #size-cells = <2>;
+ ranges;
+ status = "disabled";
+
+ cdns_csi2rx0: csi-bridge@30101000 {
+ compatible = "ti,j721e-csi2rx", "cdns,csi2rx";
+ reg = <0x00 0x30101000 0x00 0x1000>;
+ clocks = <&k3_clks 182 0>, <&k3_clks 182 3>, <&k3_clks 182 0>,
+ <&k3_clks 182 0>, <&k3_clks 182 4>, <&k3_clks 182 4>;
+ clock-names = "sys_clk", "p_clk", "pixel_if0_clk",
+ "pixel_if1_clk", "pixel_if2_clk", "pixel_if3_clk";
+ phys = <&dphy0>;
+ phy-names = "dphy";
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ csi0_port0: port@0 {
+ reg = <0>;
+ status = "disabled";
+ };
+
+ csi0_port1: port@1 {
+ reg = <1>;
+ status = "disabled";
+ };
+
+ csi0_port2: port@2 {
+ reg = <2>;
+ status = "disabled";
+ };
+
+ csi0_port3: port@3 {
+ reg = <3>;
+ status = "disabled";
+ };
+
+ csi0_port4: port@4 {
+ reg = <4>;
+ status = "disabled";
+ };
+ };
+ };
+ };
+
+ dphy0: phy@30110000 {
+ compatible = "cdns,dphy-rx";
+ reg = <0x00 0x30110000 0x00 0x1100>;
+ #phy-cells = <0>;
+ power-domains = <&k3_pds 185 TI_SCI_PD_EXCLUSIVE>;
+ status = "disabled";
+ };
};
diff --git a/dts/upstream/src/arm64/ti/k3-am62a7-sk.dts b/dts/upstream/src/arm64/ti/k3-am62a7-sk.dts
index 8f64ac2..7b71425 100644
--- a/dts/upstream/src/arm64/ti/k3-am62a7-sk.dts
+++ b/dts/upstream/src/arm64/ti/k3-am62a7-sk.dts
@@ -274,6 +274,12 @@
AM62AX_IOPAD(0x084, PIN_INPUT, 2) /* (L18) GPMC0_ADVn_ALE.MCASP1_AXR2 */
>;
};
+
+ main_gpio1_ioexp_intr_pins_default: main-gpio1-ioexp-intr-default-pins {
+ pinctrl-single,pins = <
+ AM62AX_IOPAD(0x01d4, PIN_INPUT, 7) /* (C15) UART0_RTSn.GPIO1_23 */
+ >;
+ };
};
&mcu_pmx0 {
@@ -407,6 +413,12 @@
reg = <0x22>;
gpio-controller;
#gpio-cells = <2>;
+ interrupt-parent = <&main_gpio1>;
+ interrupts = <23 IRQ_TYPE_EDGE_FALLING>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&main_gpio1_ioexp_intr_pins_default>;
gpio-line-names = "GPIO_CPSW2_RST", "GPIO_CPSW1_RST",
"BT_EN_SOC", "MMC1_SD_EN",
@@ -434,8 +446,35 @@
DRVDD-supply = <&vcc_3v3_sys>;
DVDD-supply = <&buck5>;
};
+
+ exp2: gpio@23 {
+ compatible = "ti,tca6424";
+ reg = <0x23>;
+ gpio-controller;
+ #gpio-cells = <2>;
+
+ gpio-line-names = "", "",
+ "", "",
+ "", "",
+ "", "",
+ "WL_LT_EN", "CSI_RSTz",
+ "", "",
+ "", "",
+ "", "",
+ "SPI0_FET_SEL", "SPI0_FET_OE",
+ "RGMII2_BRD_CONN_DET", "CSI_SEL2",
+ "CSI_EN", "AUTO_100M_1000M_CONFIG",
+ "CSI_VLDO_SEL", "SoC_WLAN_SDIO_RST";
+ };
};
+&main_i2c2 {
+ status = "okay";
+ pinctrl-names = "default";
+ pinctrl-0 = <&main_i2c2_pins_default>;
+ clock-frequency = <400000>;
+};
+
&sdhci1 {
/* SD/MMC */
status = "okay";
diff --git a/dts/upstream/src/arm64/ti/k3-am62p-main.dtsi b/dts/upstream/src/arm64/ti/k3-am62p-main.dtsi
index 963758c..4c51bae 100644
--- a/dts/upstream/src/arm64/ti/k3-am62p-main.dtsi
+++ b/dts/upstream/src/arm64/ti/k3-am62p-main.dtsi
@@ -101,8 +101,13 @@
<0x00 0x4c000000 0x00 0x20000>,
<0x00 0x4a820000 0x00 0x20000>,
<0x00 0x4aa40000 0x00 0x20000>,
- <0x00 0x4bc00000 0x00 0x100000>;
- reg-names = "gcfg", "bchanrt", "rchanrt", "tchanrt", "ringrt";
+ <0x00 0x4bc00000 0x00 0x100000>,
+ <0x00 0x48600000 0x00 0x8000>,
+ <0x00 0x484a4000 0x00 0x2000>,
+ <0x00 0x484c2000 0x00 0x2000>,
+ <0x00 0x48420000 0x00 0x2000>;
+ reg-names = "gcfg", "bchanrt", "rchanrt", "tchanrt", "ringrt",
+ "ring", "tchan", "rchan", "bchan";
msi-parent = <&inta_main_dmss>;
#dma-cells = <3>;
@@ -119,8 +124,13 @@
reg = <0x00 0x485c0000 0x00 0x100>,
<0x00 0x4a800000 0x00 0x20000>,
<0x00 0x4aa00000 0x00 0x40000>,
- <0x00 0x4b800000 0x00 0x400000>;
- reg-names = "gcfg", "rchanrt", "tchanrt", "ringrt";
+ <0x00 0x4b800000 0x00 0x400000>,
+ <0x00 0x485e0000 0x00 0x10000>,
+ <0x00 0x484a0000 0x00 0x2000>,
+ <0x00 0x484c0000 0x00 0x2000>,
+ <0x00 0x48430000 0x00 0x1000>;
+ reg-names = "gcfg", "rchanrt", "tchanrt", "ringrt",
+ "ring", "tchan", "rchan", "rflow";
msi-parent = <&inta_main_dmss>;
#dma-cells = <2>;
bootph-all;
diff --git a/dts/upstream/src/arm64/ti/k3-am62p5-sk.dts b/dts/upstream/src/arm64/ti/k3-am62p5-sk.dts
index f377ead..1773c05 100644
--- a/dts/upstream/src/arm64/ti/k3-am62p5-sk.dts
+++ b/dts/upstream/src/arm64/ti/k3-am62p5-sk.dts
@@ -598,3 +598,12 @@
status = "reserved";
bootph-all;
};
+
+/* mcu_gpio0 and mcu_gpio_intr are reserved for mcu firmware usage */
+&mcu_gpio0 {
+ status = "reserved";
+};
+
+&mcu_gpio_intr {
+ status = "reserved";
+};
diff --git a/dts/upstream/src/arm64/ti/k3-am62x-sk-common.dtsi b/dts/upstream/src/arm64/ti/k3-am62x-sk-common.dtsi
index 19f57ea..33768c0 100644
--- a/dts/upstream/src/arm64/ti/k3-am62x-sk-common.dtsi
+++ b/dts/upstream/src/arm64/ti/k3-am62x-sk-common.dtsi
@@ -399,6 +399,13 @@
};
};
+&main_i2c2 {
+ status = "okay";
+ pinctrl-names = "default";
+ pinctrl-0 = <&main_i2c2_pins_default>;
+ clock-frequency = <400000>;
+};
+
&sdhci0 {
bootph-all;
status = "okay";
@@ -517,3 +524,12 @@
};
};
};
+
+/* mcu_gpio0 and mcu_gpio_intr are reserved for mcu firmware usage */
+&mcu_gpio0 {
+ status = "reserved";
+};
+
+&mcu_gpio_intr {
+ status = "reserved";
+};
diff --git a/dts/upstream/src/arm64/ti/k3-am62x-sk-csi2-imx219.dtso b/dts/upstream/src/arm64/ti/k3-am62x-sk-csi2-imx219.dtso
new file mode 100644
index 0000000..6f4cd73
--- /dev/null
+++ b/dts/upstream/src/arm64/ti/k3-am62x-sk-csi2-imx219.dtso
@@ -0,0 +1,84 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * IMX219 (RPi v2) Camera Module
+ * Copyright (C) 2023 Texas Instruments Incorporated - https://www.ti.com/
+ */
+
+/dts-v1/;
+/plugin/;
+
+#include <dt-bindings/gpio/gpio.h>
+
+&{/} {
+ clk_imx219_fixed: imx219-xclk {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <24000000>;
+ };
+};
+
+&main_i2c2 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "okay";
+
+ i2c-switch@71 {
+ compatible = "nxp,pca9543";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0x71>;
+
+ /* CAM port */
+ i2c@1 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <1>;
+
+ ov5640: camera@10 {
+ compatible = "sony,imx219";
+ reg = <0x10>;
+
+ clocks = <&clk_imx219_fixed>;
+ clock-names = "xclk";
+
+ reset-gpios = <&exp1 13 GPIO_ACTIVE_HIGH>;
+
+ port {
+ csi2_cam0: endpoint {
+ remote-endpoint = <&csi2rx0_in_sensor>;
+ link-frequencies = /bits/ 64 <456000000>;
+ clock-lanes = <0>;
+ data-lanes = <1 2>;
+ };
+ };
+ };
+ };
+ };
+};
+
+&cdns_csi2rx0 {
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ csi0_port0: port@0 {
+ reg = <0>;
+ status = "okay";
+
+ csi2rx0_in_sensor: endpoint {
+ remote-endpoint = <&csi2_cam0>;
+ bus-type = <4>; /* CSI2 DPHY. */
+ clock-lanes = <0>;
+ data-lanes = <1 2>;
+ };
+ };
+ };
+};
+
+&ti_csi2rx0 {
+ status = "okay";
+};
+
+&dphy0 {
+ status = "okay";
+};
diff --git a/dts/upstream/src/arm64/ti/k3-am62x-sk-csi2-ov5640.dtso b/dts/upstream/src/arm64/ti/k3-am62x-sk-csi2-ov5640.dtso
new file mode 100644
index 0000000..9323a4b
--- /dev/null
+++ b/dts/upstream/src/arm64/ti/k3-am62x-sk-csi2-ov5640.dtso
@@ -0,0 +1,82 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * ALINX AN5641 & Digilent PCam 5C - OV5640 camera module
+ * Copyright (C) 2022-2023 Texas Instruments Incorporated - https://www.ti.com/
+ */
+
+/dts-v1/;
+/plugin/;
+
+#include <dt-bindings/gpio/gpio.h>
+
+&{/} {
+ clk_ov5640_fixed: ov5640-xclk {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <12000000>;
+ };
+};
+
+&main_i2c2 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "okay";
+
+ i2c-switch@71 {
+ compatible = "nxp,pca9543";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0x71>;
+
+ /* CAM port */
+ i2c@1 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <1>;
+
+ ov5640: camera@3c {
+ compatible = "ovti,ov5640";
+ reg = <0x3c>;
+
+ clocks = <&clk_ov5640_fixed>;
+ clock-names = "xclk";
+ powerdown-gpios = <&exp1 13 GPIO_ACTIVE_LOW>;
+
+ port {
+ csi2_cam0: endpoint {
+ remote-endpoint = <&csi2rx0_in_sensor>;
+ clock-lanes = <0>;
+ data-lanes = <1 2>;
+ };
+ };
+ };
+ };
+ };
+};
+
+&cdns_csi2rx0 {
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ csi0_port0: port@0 {
+ reg = <0>;
+ status = "okay";
+
+ csi2rx0_in_sensor: endpoint {
+ remote-endpoint = <&csi2_cam0>;
+ bus-type = <4>; /* CSI2 DPHY. */
+ clock-lanes = <0>;
+ data-lanes = <1 2>;
+ };
+ };
+ };
+};
+
+&ti_csi2rx0 {
+ status = "okay";
+};
+
+&dphy0 {
+ status = "okay";
+};
diff --git a/dts/upstream/src/arm64/ti/k3-am62x-sk-csi2-tevi-ov5640.dtso b/dts/upstream/src/arm64/ti/k3-am62x-sk-csi2-tevi-ov5640.dtso
new file mode 100644
index 0000000..dcaa33a
--- /dev/null
+++ b/dts/upstream/src/arm64/ti/k3-am62x-sk-csi2-tevi-ov5640.dtso
@@ -0,0 +1,82 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Technexion TEVI-OV5640-*-RPI - OV5640 camera module
+ * Copyright (C) 2022-2023 Texas Instruments Incorporated - https://www.ti.com/
+ */
+
+/dts-v1/;
+/plugin/;
+
+#include <dt-bindings/gpio/gpio.h>
+
+&{/} {
+ clk_ov5640_fixed: ov5640-xclk {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <24000000>;
+ };
+};
+
+&main_i2c2 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "okay";
+
+ i2c-switch@71 {
+ compatible = "nxp,pca9543";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0x71>;
+
+ /* CAM port */
+ i2c@1 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <1>;
+
+ ov5640: camera@3c {
+ compatible = "ovti,ov5640";
+ reg = <0x3c>;
+
+ clocks = <&clk_ov5640_fixed>;
+ clock-names = "xclk";
+ powerdown-gpios = <&exp1 13 GPIO_ACTIVE_LOW>;
+
+ port {
+ csi2_cam0: endpoint {
+ remote-endpoint = <&csi2rx0_in_sensor>;
+ clock-lanes = <0>;
+ data-lanes = <1 2>;
+ };
+ };
+ };
+ };
+ };
+};
+
+&cdns_csi2rx0 {
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ csi0_port0: port@0 {
+ reg = <0>;
+ status = "okay";
+
+ csi2rx0_in_sensor: endpoint {
+ remote-endpoint = <&csi2_cam0>;
+ bus-type = <4>; /* CSI2 DPHY. */
+ clock-lanes = <0>;
+ data-lanes = <1 2>;
+ };
+ };
+ };
+};
+
+&ti_csi2rx0 {
+ status = "okay";
+};
+
+&dphy0 {
+ status = "okay";
+};
diff --git a/dts/upstream/src/arm64/ti/k3-am64-main.dtsi b/dts/upstream/src/arm64/ti/k3-am64-main.dtsi
index 0be642b..e348114 100644
--- a/dts/upstream/src/arm64/ti/k3-am64-main.dtsi
+++ b/dts/upstream/src/arm64/ti/k3-am64-main.dtsi
@@ -63,7 +63,7 @@
#phy-cells = <1>;
};
- epwm_tbclk: clock-controller@4140 {
+ epwm_tbclk: clock-controller@4130 {
compatible = "ti,am64-epwm-tbclk";
reg = <0x4130 0x4>;
#clock-cells = <1>;
@@ -138,8 +138,13 @@
<0x00 0x4c000000 0x00 0x20000>,
<0x00 0x4a820000 0x00 0x20000>,
<0x00 0x4aa40000 0x00 0x20000>,
- <0x00 0x4bc00000 0x00 0x100000>;
- reg-names = "gcfg", "bchanrt", "rchanrt", "tchanrt", "ringrt";
+ <0x00 0x4bc00000 0x00 0x100000>,
+ <0x00 0x48600000 0x00 0x8000>,
+ <0x00 0x484a4000 0x00 0x2000>,
+ <0x00 0x484c2000 0x00 0x2000>,
+ <0x00 0x48420000 0x00 0x2000>;
+ reg-names = "gcfg", "bchanrt", "rchanrt", "tchanrt", "ringrt",
+ "ring", "tchan", "rchan", "bchan";
msi-parent = <&inta_main_dmss>;
#dma-cells = <3>;
@@ -155,8 +160,13 @@
reg = <0x00 0x485c0000 0x00 0x100>,
<0x00 0x4a800000 0x00 0x20000>,
<0x00 0x4aa00000 0x00 0x40000>,
- <0x00 0x4b800000 0x00 0x400000>;
- reg-names = "gcfg", "rchanrt", "tchanrt", "ringrt";
+ <0x00 0x4b800000 0x00 0x400000>,
+ <0x00 0x485e0000 0x00 0x20000>,
+ <0x00 0x484a0000 0x00 0x4000>,
+ <0x00 0x484c0000 0x00 0x2000>,
+ <0x00 0x48430000 0x00 0x4000>;
+ reg-names = "gcfg", "rchanrt", "tchanrt", "ringrt",
+ "ring", "tchan", "rchan", "rflow";
msi-parent = <&inta_main_dmss>;
#dma-cells = <2>;
@@ -623,6 +633,7 @@
ti,otap-del-sel-mmc-hs = <0x0>;
ti,otap-del-sel-ddr52 = <0x6>;
ti,otap-del-sel-hs200 = <0x7>;
+ status = "disabled";
};
sdhci1: mmc@fa00000 {
@@ -641,6 +652,7 @@
ti,otap-del-sel-sdr104 = <0x6>;
ti,otap-del-sel-ddr50 = <0x9>;
ti,clkbuf-sel = <0x7>;
+ status = "disabled";
};
cpsw3g: ethernet@8000000 {
diff --git a/dts/upstream/src/arm64/ti/k3-am64-phycore-som.dtsi b/dts/upstream/src/arm64/ti/k3-am64-phycore-som.dtsi
index f87f09d..1678e74 100644
--- a/dts/upstream/src/arm64/ti/k3-am64-phycore-som.dtsi
+++ b/dts/upstream/src/arm64/ti/k3-am64-phycore-som.dtsi
@@ -29,7 +29,7 @@
reg = <0x00000000 0x80000000 0x00000000 0x80000000>;
};
- reserved-memory {
+ reserved_memory: reserved-memory {
#address-cells = <2>;
#size-cells = <2>;
ranges;
@@ -39,6 +39,54 @@
alignment = <0x1000>;
no-map;
};
+
+ main_r5fss0_core0_dma_memory_region: r5f-dma-memory@a0000000 {
+ compatible = "shared-dma-pool";
+ reg = <0x00 0xa0000000 0x00 0x100000>;
+ no-map;
+ };
+
+ main_r5fss0_core0_memory_region: r5f-memory@a0100000 {
+ compatible = "shared-dma-pool";
+ reg = <0x00 0xa0100000 0x00 0xf00000>;
+ no-map;
+ };
+
+ main_r5fss0_core1_dma_memory_region: r5f-dma-memory@a1000000 {
+ compatible = "shared-dma-pool";
+ reg = <0x00 0xa1000000 0x00 0x100000>;
+ no-map;
+ };
+
+ main_r5fss0_core1_memory_region: r5f-memory@a1100000 {
+ compatible = "shared-dma-pool";
+ reg = <0x00 0xa1100000 0x00 0xf00000>;
+ no-map;
+ };
+
+ main_r5fss1_core0_dma_memory_region: r5f-dma-memory@a2000000 {
+ compatible = "shared-dma-pool";
+ reg = <0x00 0xa2000000 0x00 0x100000>;
+ no-map;
+ };
+
+ main_r5fss1_core0_memory_region: r5f-memory@a2100000 {
+ compatible = "shared-dma-pool";
+ reg = <0x00 0xa2100000 0x00 0xf00000>;
+ no-map;
+ };
+
+ main_r5fss1_core1_dma_memory_region: r5f-dma-memory@a3000000 {
+ compatible = "shared-dma-pool";
+ reg = <0x00 0xa3000000 0x00 0x100000>;
+ no-map;
+ };
+
+ main_r5fss1_core1_memory_region: r5f-memory@a3100000 {
+ compatible = "shared-dma-pool";
+ reg = <0x00 0xa3100000 0x00 0xf00000>;
+ no-map;
+ };
};
leds {
@@ -166,6 +214,34 @@
status = "disabled";
};
+&mailbox0_cluster2 {
+ status = "okay";
+
+ mbox_main_r5fss0_core0: mbox-main-r5fss0-core0 {
+ ti,mbox-rx = <0 0 2>;
+ ti,mbox-tx = <1 0 2>;
+ };
+
+ mbox_main_r5fss0_core1: mbox-main-r5fss0-core1 {
+ ti,mbox-rx = <2 0 2>;
+ ti,mbox-tx = <3 0 2>;
+ };
+};
+
+&mailbox0_cluster4 {
+ status = "okay";
+
+ mbox_main_r5fss1_core0: mbox-main-r5fss1-core0 {
+ ti,mbox-rx = <0 0 2>;
+ ti,mbox-tx = <1 0 2>;
+ };
+
+ mbox_main_r5fss1_core1: mbox-main-r5fss1-core1 {
+ ti,mbox-rx = <2 0 2>;
+ ti,mbox-tx = <3 0 2>;
+ };
+};
+
&main_i2c0 {
status = "okay";
pinctrl-names = "default";
@@ -191,6 +267,30 @@
};
};
+&main_r5fss0_core0 {
+ mboxes = <&mailbox0_cluster2 &mbox_main_r5fss0_core0>;
+ memory-region = <&main_r5fss0_core0_dma_memory_region>,
+ <&main_r5fss0_core0_memory_region>;
+};
+
+&main_r5fss0_core1 {
+ mboxes = <&mailbox0_cluster2 &mbox_main_r5fss0_core1>;
+ memory-region = <&main_r5fss0_core1_dma_memory_region>,
+ <&main_r5fss0_core1_memory_region>;
+};
+
+&main_r5fss1_core0 {
+ mboxes = <&mailbox0_cluster4 &mbox_main_r5fss1_core0>;
+ memory-region = <&main_r5fss1_core0_dma_memory_region>,
+ <&main_r5fss1_core0_memory_region>;
+};
+
+&main_r5fss1_core1 {
+ mboxes = <&mailbox0_cluster4 &mbox_main_r5fss1_core1>;
+ memory-region = <&main_r5fss1_core1_dma_memory_region>,
+ <&main_r5fss1_core1_memory_region>;
+};
+
&ospi0 {
status = "okay";
pinctrl-names = "default";
@@ -211,6 +311,7 @@
};
&sdhci0 {
+ status = "okay";
bus-width = <8>;
non-removable;
ti,driver-strength-ohm = <50>;
diff --git a/dts/upstream/src/arm64/ti/k3-am642-evm.dts b/dts/upstream/src/arm64/ti/k3-am642-evm.dts
index 4dba189..8c5651d 100644
--- a/dts/upstream/src/arm64/ti/k3-am642-evm.dts
+++ b/dts/upstream/src/arm64/ti/k3-am642-evm.dts
@@ -468,11 +468,15 @@
bootph-all;
};
-/* mcu_gpio0 is reserved for mcu firmware usage */
+/* mcu_gpio0 and mcu_gpio_intr are reserved for mcu firmware usage */
&mcu_gpio0 {
status = "reserved";
};
+&mcu_gpio_intr {
+ status = "reserved";
+};
+
&main_spi0 {
status = "okay";
pinctrl-names = "default";
@@ -487,17 +491,19 @@
};
};
+/* eMMC */
&sdhci0 {
- /* emmc */
+ status = "okay";
bus-width = <8>;
non-removable;
ti,driver-strength-ohm = <50>;
disable-wp;
};
+/* SD/MMC */
&sdhci1 {
- /* SD/MMC */
bootph-all;
+ status = "okay";
vmmc-supply = <&vdd_mmc1>;
pinctrl-names = "default";
bus-width = <4>;
diff --git a/dts/upstream/src/arm64/ti/k3-am642-phyboard-electra-rdk.dts b/dts/upstream/src/arm64/ti/k3-am642-phyboard-electra-rdk.dts
index 9175e96..53b64e5 100644
--- a/dts/upstream/src/arm64/ti/k3-am642-phyboard-electra-rdk.dts
+++ b/dts/upstream/src/arm64/ti/k3-am642-phyboard-electra-rdk.dts
@@ -264,6 +264,7 @@
};
&sdhci1 {
+ status = "okay";
vmmc-supply = <&vcc_3v3_mmc>;
pinctrl-names = "default";
pinctrl-0 = <&main_mmc1_pins_default>;
diff --git a/dts/upstream/src/arm64/ti/k3-am642-sk.dts b/dts/upstream/src/arm64/ti/k3-am642-sk.dts
index f29c8a9..1dddd6f 100644
--- a/dts/upstream/src/arm64/ti/k3-am642-sk.dts
+++ b/dts/upstream/src/arm64/ti/k3-am642-sk.dts
@@ -433,12 +433,17 @@
};
};
-/* mcu_gpio0 is reserved for mcu firmware usage */
+/* mcu_gpio0 and mcu_gpio_intr are reserved for mcu firmware usage */
&mcu_gpio0 {
status = "reserved";
};
+&mcu_gpio_intr {
+ status = "reserved";
+};
+
&sdhci0 {
+ status = "okay";
vmmc-supply = <&wlan_en>;
bus-width = <4>;
non-removable;
@@ -458,9 +463,10 @@
};
};
+/* SD/MMC */
&sdhci1 {
- /* SD/MMC */
bootph-all;
+ status = "okay";
vmmc-supply = <&vdd_mmc1>;
pinctrl-names = "default";
bus-width = <4>;
diff --git a/dts/upstream/src/arm64/ti/k3-am642-tqma64xxl-mbax4xxl.dts b/dts/upstream/src/arm64/ti/k3-am642-tqma64xxl-mbax4xxl.dts
index d95d800..55102d3 100644
--- a/dts/upstream/src/arm64/ti/k3-am642-tqma64xxl-mbax4xxl.dts
+++ b/dts/upstream/src/arm64/ti/k3-am642-tqma64xxl-mbax4xxl.dts
@@ -425,7 +425,6 @@
ti,driver-strength-ohm = <50>;
ti,fails-without-test-cd;
/* Enabled by overlay */
- status = "disabled";
};
&tscadc0 {
diff --git a/dts/upstream/src/arm64/ti/k3-am642-tqma64xxl.dtsi b/dts/upstream/src/arm64/ti/k3-am642-tqma64xxl.dtsi
index d82d4a9..6c785ef 100644
--- a/dts/upstream/src/arm64/ti/k3-am642-tqma64xxl.dtsi
+++ b/dts/upstream/src/arm64/ti/k3-am642-tqma64xxl.dtsi
@@ -219,6 +219,7 @@
};
&sdhci0 {
+ status = "okay";
non-removable;
disable-wp;
no-sdio;
diff --git a/dts/upstream/src/arm64/ti/k3-am65-iot2050-common-pg1.dtsi b/dts/upstream/src/arm64/ti/k3-am65-iot2050-common-pg1.dtsi
index 51f902f..1d19798 100644
--- a/dts/upstream/src/arm64/ti/k3-am65-iot2050-common-pg1.dtsi
+++ b/dts/upstream/src/arm64/ti/k3-am65-iot2050-common-pg1.dtsi
@@ -1,6 +1,6 @@
// SPDX-License-Identifier: GPL-2.0
/*
- * Copyright (c) Siemens AG, 2021
+ * Copyright (c) Siemens AG, 2021-2023
*
* Authors:
* Jan Kiszka <jan.kiszka@siemens.com>
@@ -44,3 +44,11 @@
&tx_pru2_1 {
status = "disabled";
};
+
+&icssg0_eth {
+ status = "disabled";
+};
+
+&icssg0_mdio {
+ status = "disabled";
+};
diff --git a/dts/upstream/src/arm64/ti/k3-am65-iot2050-common-pg2.dtsi b/dts/upstream/src/arm64/ti/k3-am65-iot2050-common-pg2.dtsi
index e9419c4..e9b57b8 100644
--- a/dts/upstream/src/arm64/ti/k3-am65-iot2050-common-pg2.dtsi
+++ b/dts/upstream/src/arm64/ti/k3-am65-iot2050-common-pg2.dtsi
@@ -20,7 +20,9 @@
&main_gpio1 {
pinctrl-names = "default";
- pinctrl-0 = <&cp2102n_reset_pin_default>;
+ pinctrl-0 =
+ <&main_pcie_enable_pins_default>,
+ <&cp2102n_reset_pin_default>;
gpio-line-names =
"", "", "", "", "", "", "", "", "", "",
"", "", "", "", "", "", "", "", "", "",
diff --git a/dts/upstream/src/arm64/ti/k3-am65-iot2050-common.dtsi b/dts/upstream/src/arm64/ti/k3-am65-iot2050-common.dtsi
index ba1c14a..61a634a 100644
--- a/dts/upstream/src/arm64/ti/k3-am65-iot2050-common.dtsi
+++ b/dts/upstream/src/arm64/ti/k3-am65-iot2050-common.dtsi
@@ -9,14 +9,26 @@
* Common bits of the IOT2050 Basic and Advanced variants, PG1 and PG2
*/
-#include "k3-am654.dtsi"
#include <dt-bindings/phy/phy.h>
+#include <dt-bindings/net/ti-dp83867.h>
/ {
aliases {
+ serial0 = &wkup_uart0;
+ serial1 = &mcu_uart0;
+ serial2 = &main_uart0;
+ serial3 = &main_uart1;
+ i2c0 = &wkup_i2c0;
+ i2c1 = &mcu_i2c0;
+ i2c2 = &main_i2c0;
+ i2c3 = &main_i2c1;
+ i2c4 = &main_i2c2;
+ i2c5 = &main_i2c3;
spi0 = &mcu_spi0;
mmc0 = &sdhci1;
mmc1 = &sdhci0;
+ ethernet1 = &icssg0_emac0;
+ ethernet2 = &icssg0_emac1;
};
chosen {
@@ -101,9 +113,498 @@
#clock-cells = <0>;
clock-frequency = <19200000>;
};
+
+ /* Dual Ethernet application node on PRU-ICSSG0 */
+ icssg0_eth: icssg0-eth {
+ compatible = "ti,am654-icssg-prueth";
+ pinctrl-names = "default";
+ pinctrl-0 = <&icssg0_rgmii_pins_default>;
+ sram = <&msmc_ram>;
+
+ ti,prus = <&pru0_0>, <&rtu0_0>, <&tx_pru0_0>,
+ <&pru0_1>, <&rtu0_1>, <&tx_pru0_1>;
+ firmware-name = "ti-pruss/am65x-sr2-pru0-prueth-fw.elf",
+ "ti-pruss/am65x-sr2-rtu0-prueth-fw.elf",
+ "ti-pruss/am65x-sr2-txpru0-prueth-fw.elf",
+ "ti-pruss/am65x-sr2-pru1-prueth-fw.elf",
+ "ti-pruss/am65x-sr2-rtu1-prueth-fw.elf",
+ "ti-pruss/am65x-sr2-txpru1-prueth-fw.elf";
+
+ ti,pruss-gp-mux-sel = <2>, /* MII mode */
+ <2>,
+ <2>,
+ <2>, /* MII mode */
+ <2>,
+ <2>;
+
+ ti,mii-g-rt = <&icssg0_mii_g_rt>;
+ ti,mii-rt = <&icssg0_mii_rt>;
+ ti,iep = <&icssg0_iep0>, <&icssg0_iep1>;
+
+ interrupt-parent = <&icssg0_intc>;
+ interrupts = <24 0 2>, <25 1 3>;
+ interrupt-names = "tx_ts0", "tx_ts1";
+
+ dmas = <&main_udmap 0xc100>, /* egress slice 0 */
+ <&main_udmap 0xc101>, /* egress slice 0 */
+ <&main_udmap 0xc102>, /* egress slice 0 */
+ <&main_udmap 0xc103>, /* egress slice 0 */
+ <&main_udmap 0xc104>, /* egress slice 1 */
+ <&main_udmap 0xc105>, /* egress slice 1 */
+ <&main_udmap 0xc106>, /* egress slice 1 */
+ <&main_udmap 0xc107>, /* egress slice 1 */
+ <&main_udmap 0x4100>, /* ingress slice 0 */
+ <&main_udmap 0x4101>; /* ingress slice 1 */
+ dma-names = "tx0-0", "tx0-1", "tx0-2", "tx0-3",
+ "tx1-0", "tx1-1", "tx1-2", "tx1-3",
+ "rx0", "rx1";
+
+ ethernet-ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ icssg0_emac0: port@0 {
+ reg = <0>;
+ phy-handle = <&icssg0_eth0_phy>;
+ phy-mode = "rgmii-id";
+ ti,syscon-rgmii-delay = <&scm_conf 0x4100>;
+ ti,half-duplex-capable;
+ /* Filled in by bootloader */
+ local-mac-address = [00 00 00 00 00 00];
+ };
+
+ icssg0_emac1: port@1 {
+ reg = <1>;
+ phy-handle = <&icssg0_eth1_phy>;
+ phy-mode = "rgmii-id";
+ ti,syscon-rgmii-delay = <&scm_conf 0x4104>;
+ ti,half-duplex-capable;
+ /* Filled in by bootloader */
+ local-mac-address = [00 00 00 00 00 00];
+ };
+ };
+ };
};
&wkup_pmx0 {
+ pinctrl-names =
+ "default",
+ "d0-uart0-rxd", "d0-gpio", "d0-gpio-pullup", "d0-gpio-pulldown",
+ "d1-uart0-txd", "d1-gpio", "d1-gpio-pullup", "d1-gpio-pulldown",
+ "d2-uart0-ctsn", "d2-gpio", "d2-gpio-pullup", "d2-gpio-pulldown",
+ "d3-uart0-rtsn", "d3-gpio", "d3-gpio-pullup", "d3-gpio-pulldown",
+ "d10-spi0-cs0", "d10-gpio", "d10-gpio-pullup", "d10-gpio-pulldown",
+ "d11-spi0-d0", "d11-gpio", "d11-gpio-pullup", "d11-gpio-pulldown",
+ "d12-spi0-d1", "d12-gpio", "d12-gpio-pullup", "d12-gpio-pulldown",
+ "d13-spi0-clk", "d13-gpio", "d13-gpio-pullup", "d13-gpio-pulldown",
+ "a0-gpio", "a0-gpio-pullup", "a0-gpio-pulldown",
+ "a1-gpio", "a1-gpio-pullup", "a1-gpio-pulldown",
+ "a2-gpio", "a2-gpio-pullup", "a2-gpio-pulldown",
+ "a3-gpio", "a3-gpio-pullup", "a3-gpio-pulldown",
+ "a4-gpio", "a4-gpio-pullup", "a4-gpio-pulldown",
+ "a5-gpio", "a5-gpio-pullup", "a5-gpio-pulldown";
+
+ pinctrl-0 = <&d0_uart0_rxd>;
+ pinctrl-1 = <&d0_uart0_rxd>;
+ pinctrl-2 = <&d0_gpio>;
+ pinctrl-3 = <&d0_gpio_pullup>;
+ pinctrl-4 = <&d0_gpio_pulldown>;
+ pinctrl-5 = <&d1_uart0_txd>;
+ pinctrl-6 = <&d1_gpio>;
+ pinctrl-7 = <&d1_gpio_pullup>;
+ pinctrl-8 = <&d1_gpio_pulldown>;
+ pinctrl-9 = <&d2_uart0_ctsn>;
+ pinctrl-10 = <&d2_gpio>;
+ pinctrl-11 = <&d2_gpio_pullup>;
+ pinctrl-12 = <&d2_gpio_pulldown>;
+ pinctrl-13 = <&d3_uart0_rtsn>;
+ pinctrl-14 = <&d3_gpio>;
+ pinctrl-15 = <&d3_gpio_pullup>;
+ pinctrl-16 = <&d3_gpio_pulldown>;
+ pinctrl-17 = <&d10_spi0_cs0>;
+ pinctrl-18 = <&d10_gpio>;
+ pinctrl-19 = <&d10_gpio_pullup>;
+ pinctrl-20 = <&d10_gpio_pulldown>;
+ pinctrl-21 = <&d11_spi0_d0>;
+ pinctrl-22 = <&d11_gpio>;
+ pinctrl-23 = <&d11_gpio_pullup>;
+ pinctrl-24 = <&d11_gpio_pulldown>;
+ pinctrl-25 = <&d12_spi0_d1>;
+ pinctrl-26 = <&d12_gpio>;
+ pinctrl-27 = <&d12_gpio_pullup>;
+ pinctrl-28 = <&d12_gpio_pulldown>;
+ pinctrl-29 = <&d13_spi0_clk>;
+ pinctrl-30 = <&d13_gpio>;
+ pinctrl-31 = <&d13_gpio_pullup>;
+ pinctrl-32 = <&d13_gpio_pulldown>;
+ pinctrl-33 = <&a0_gpio>;
+ pinctrl-34 = <&a0_gpio_pullup>;
+ pinctrl-35 = <&a0_gpio_pulldown>;
+ pinctrl-36 = <&a1_gpio>;
+ pinctrl-37 = <&a1_gpio_pullup>;
+ pinctrl-38 = <&a1_gpio_pulldown>;
+ pinctrl-39 = <&a2_gpio>;
+ pinctrl-40 = <&a2_gpio_pullup>;
+ pinctrl-41 = <&a2_gpio_pulldown>;
+ pinctrl-42 = <&a3_gpio>;
+ pinctrl-43 = <&a3_gpio_pullup>;
+ pinctrl-44 = <&a3_gpio_pulldown>;
+ pinctrl-45 = <&a4_gpio>;
+ pinctrl-46 = <&a4_gpio_pullup>;
+ pinctrl-47 = <&a4_gpio_pulldown>;
+ pinctrl-48 = <&a5_gpio>;
+ pinctrl-49 = <&a5_gpio_pullup>;
+ pinctrl-50 = <&a5_gpio_pulldown>;
+
+ d0_uart0_rxd: d0-uart0-rxd-pins {
+ pinctrl-single,pins = <
+ /* (P4) MCU_UART0_RXD */
+ AM65X_WKUP_IOPAD(0x0044, PIN_INPUT, 4)
+ >;
+ };
+
+ d0_gpio: d0-gpio-pins {
+ pinctrl-single,pins = <
+ /* (P4) WKUP_GPIO0_29 */
+ AM65X_WKUP_IOPAD(0x0044, PIN_INPUT, 7)
+ >;
+ };
+
+ d0_gpio_pullup: d0-gpio-pullup-pins {
+ pinctrl-single,pins = <
+ /* (P4) WKUP_GPIO0_29 */
+ AM65X_WKUP_IOPAD(0x0044, PIN_INPUT_PULLUP, 7)
+ >;
+ };
+
+ d0_gpio_pulldown: d0-gpio-pulldown-pins {
+ pinctrl-single,pins = <
+ /* (P4) WKUP_GPIO0_29 */
+ AM65X_WKUP_IOPAD(0x0044, PIN_INPUT_PULLDOWN, 7)
+ >;
+ };
+
+ d1_uart0_txd: d1-uart0-txd-pins {
+ pinctrl-single,pins = <
+ /* (P5) MCU_UART0_TXD */
+ AM65X_WKUP_IOPAD(0x0048, PIN_OUTPUT, 4)
+ >;
+ };
+
+ d1_gpio: d1-gpio-pins {
+ pinctrl-single,pins = <
+ /* (P5) WKUP_GPIO0_30 */
+ AM65X_WKUP_IOPAD(0x0048, PIN_INPUT, 7)
+ >;
+ };
+
+ d1_gpio_pullup: d1-gpio-pullup-pins {
+ pinctrl-single,pins = <
+ /* (P5) WKUP_GPIO0_30 */
+ AM65X_WKUP_IOPAD(0x0048, PIN_INPUT, 7)
+ >;
+ };
+
+ d1_gpio_pulldown: d1-gpio-pulldown-pins {
+ pinctrl-single,pins = <
+ /* (P5) WKUP_GPIO0_30 */
+ AM65X_WKUP_IOPAD(0x0048, PIN_INPUT_PULLDOWN, 7)
+ >;
+ };
+
+ d2_uart0_ctsn: d2-uart0-ctsn-pins {
+ pinctrl-single,pins = <
+ /* (P1) MCU_UART0_CTSn */
+ AM65X_WKUP_IOPAD(0x004C, PIN_INPUT, 4)
+ >;
+ };
+
+ d2_gpio: d2-gpio-pins {
+ pinctrl-single,pins = <
+ /* (P5) WKUP_GPIO0_31 */
+ AM65X_WKUP_IOPAD(0x004C, PIN_INPUT, 7)
+ >;
+ };
+
+ d2_gpio_pullup: d2-gpio-pullup-pins {
+ pinctrl-single,pins = <
+ /* (P5) WKUP_GPIO0_31 */
+ AM65X_WKUP_IOPAD(0x004C, PIN_INPUT, 7)
+ >;
+ };
+
+ d2_gpio_pulldown: d2-gpio-pulldown-pins {
+ pinctrl-single,pins = <
+ /* (P5) WKUP_GPIO0_31 */
+ AM65X_WKUP_IOPAD(0x004C, PIN_INPUT_PULLDOWN, 7)
+ >;
+ };
+
+ d3_uart0_rtsn: d3-uart0-rtsn-pins {
+ pinctrl-single,pins = <
+ /* (N3) MCU_UART0_RTSn */
+ AM65X_WKUP_IOPAD(0x0054, PIN_OUTPUT, 4)
+ >;
+ };
+
+ d3_gpio: d3-gpio-pins {
+ pinctrl-single,pins = <
+ /* (N3) WKUP_GPIO0_33 */
+ AM65X_WKUP_IOPAD(0x0054, PIN_INPUT, 7)
+ >;
+ };
+
+ d3_gpio_pullup: d3-gpio-pullup-pins {
+ pinctrl-single,pins = <
+ /* (N3) WKUP_GPIO0_33 */
+ AM65X_WKUP_IOPAD(0x0054, PIN_INPUT, 7)
+ >;
+ };
+
+ d3_gpio_pulldown: d3-gpio-pulldown-pins {
+ pinctrl-single,pins = <
+ /* (N3) WKUP_GPIO0_33 */
+ AM65X_WKUP_IOPAD(0x0054, PIN_INPUT_PULLDOWN, 7)
+ >;
+ };
+
+ d10_spi0_cs0: d10-spi0-cs0-pins {
+ pinctrl-single,pins = <
+ /* (Y4) MCU_SPI0_CS0 */
+ AM65X_WKUP_IOPAD(0x009c, PIN_OUTPUT, 0)
+ >;
+ };
+
+ d10_gpio: d10-gpio-pins {
+ pinctrl-single,pins = <
+ /* (Y4) WKUP_GPIO0_51 */
+ AM65X_WKUP_IOPAD(0x009c, PIN_INPUT, 7)
+ >;
+ };
+
+ d10_gpio_pullup: d10-gpio-pullup-pins {
+ pinctrl-single,pins = <
+ /* (Y4) WKUP_GPIO0_51 */
+ AM65X_WKUP_IOPAD(0x009c, PIN_INPUT, 7)
+ >;
+ };
+
+ d10_gpio_pulldown: d10-gpio-pulldown-pins {
+ pinctrl-single,pins = <
+ /* (Y4) WKUP_GPIO0_51 */
+ AM65X_WKUP_IOPAD(0x009c, PIN_INPUT_PULLDOWN, 7)
+ >;
+ };
+
+ d11_spi0_d0: d11-spi0-d0-pins {
+ pinctrl-single,pins = <
+ /* (Y3) MCU_SPI0_D0 */
+ AM65X_WKUP_IOPAD(0x0094, PIN_INPUT, 0)
+ >;
+ };
+
+ d11_gpio: d11-gpio-pins {
+ pinctrl-single,pins = <
+ /* (Y3) WKUP_GPIO0_49 */
+ AM65X_WKUP_IOPAD(0x0094, PIN_INPUT, 7)
+ >;
+ };
+
+ d11_gpio_pullup: d11-gpio-pullup-pins {
+ pinctrl-single,pins = <
+ /* (Y3) WKUP_GPIO0_49 */
+ AM65X_WKUP_IOPAD(0x0094, PIN_INPUT, 7)
+ >;
+ };
+
+ d11_gpio_pulldown: d11-gpio-pulldown-pins {
+ pinctrl-single,pins = <
+ /* (Y3) WKUP_GPIO0_49 */
+ AM65X_WKUP_IOPAD(0x0094, PIN_INPUT_PULLDOWN, 7)
+ >;
+ };
+
+ d12_spi0_d1: d12-spi0-d1-pins {
+ pinctrl-single,pins = <
+ /* (Y2) MCU_SPI0_D1 */
+ AM65X_WKUP_IOPAD(0x0098, PIN_INPUT, 0)
+ >;
+ };
+
+ d12_gpio: d12-gpio-pins {
+ pinctrl-single,pins = <
+ /* (Y2) WKUP_GPIO0_50 */
+ AM65X_WKUP_IOPAD(0x0098, PIN_INPUT, 7)
+ >;
+ };
+
+ d12_gpio_pullup: d12-gpio-pullup-pins {
+ pinctrl-single,pins = <
+ /* (Y2) WKUP_GPIO0_50 */
+ AM65X_WKUP_IOPAD(0x0098, PIN_INPUT, 7)
+ >;
+ };
+
+ d12_gpio_pulldown: d12-gpio-pulldown-pins {
+ pinctrl-single,pins = <
+ /* (Y2) WKUP_GPIO0_50 */
+ AM65X_WKUP_IOPAD(0x0098, PIN_INPUT_PULLDOWN, 7)
+ >;
+ };
+
+ d13_spi0_clk: d13-spi0-clk-pins {
+ pinctrl-single,pins = <
+ /* (Y1) MCU_SPI0_CLK */
+ AM65X_WKUP_IOPAD(0x0090, PIN_INPUT, 0)
+ >;
+ };
+
+ d13_gpio: d13-gpio-pins {
+ pinctrl-single,pins = <
+ /* (Y1) WKUP_GPIO0_48 */
+ AM65X_WKUP_IOPAD(0x0090, PIN_INPUT, 7)
+ >;
+ };
+
+ d13_gpio_pullup: d13-gpio-pullup-pins {
+ pinctrl-single,pins = <
+ /* (Y1) WKUP_GPIO0_48 */
+ AM65X_WKUP_IOPAD(0x0090, PIN_INPUT, 7)
+ >;
+ };
+
+ d13_gpio_pulldown: d13-gpio-pulldown-pins {
+ pinctrl-single,pins = <
+ /* (Y1) WKUP_GPIO0_48 */
+ AM65X_WKUP_IOPAD(0x0090, PIN_INPUT_PULLDOWN, 7)
+ >;
+ };
+
+ a0_gpio: a0-gpio-pins {
+ pinctrl-single,pins = <
+ /* (L6) WKUP_GPIO0_45 */
+ AM65X_WKUP_IOPAD(0x0084, PIN_INPUT, 7)
+ >;
+ };
+
+ a0_gpio_pullup: a0-gpio-pullup-pins {
+ pinctrl-single,pins = <
+ /* (L6) WKUP_GPIO0_45 */
+ AM65X_WKUP_IOPAD(0x0084, PIN_INPUT, 7)
+ >;
+ };
+
+ a0_gpio_pulldown: a0-gpio-pulldown-pins {
+ pinctrl-single,pins = <
+ /* (L6) WKUP_GPIO0_45 */
+ AM65X_WKUP_IOPAD(0x0084, PIN_INPUT_PULLDOWN, 7)
+ >;
+ };
+
+ a1_gpio: a1-gpio-pins {
+ pinctrl-single,pins = <
+ /* (M6) WKUP_GPIO0_44 */
+ AM65X_WKUP_IOPAD(0x0080, PIN_INPUT, 7)
+ >;
+ };
+
+ a1_gpio_pullup: a1-gpio-pullup-pins {
+ pinctrl-single,pins = <
+ /* (M6) WKUP_GPIO0_44 */
+ AM65X_WKUP_IOPAD(0x0080, PIN_INPUT, 7)
+ >;
+ };
+
+ a1_gpio_pulldown: a1-gpio-pulldown-pins {
+ pinctrl-single,pins = <
+ /* (M6) WKUP_GPIO0_44 */
+ AM65X_WKUP_IOPAD(0x0080, PIN_INPUT_PULLDOWN, 7)
+ >;
+ };
+
+ a2_gpio: a2-gpio-pins {
+ pinctrl-single,pins = <
+ /* (L5) WKUP_GPIO0_43 */
+ AM65X_WKUP_IOPAD(0x007C, PIN_INPUT, 7)
+ >;
+ };
+
+ a2_gpio_pullup: a2-gpio-pullup-pins {
+ pinctrl-single,pins = <
+ /* (L5) WKUP_GPIO0_43 */
+ AM65X_WKUP_IOPAD(0x007C, PIN_INPUT, 7)
+ >;
+ };
+
+ a2_gpio_pulldown: a2-gpio-pulldown-pins {
+ pinctrl-single,pins = <
+ /* (L5) WKUP_GPIO0_43 */
+ AM65X_WKUP_IOPAD(0x007C, PIN_INPUT_PULLDOWN, 7)
+ >;
+ };
+
+ a3_gpio: a3-gpio-pins {
+ pinctrl-single,pins = <
+ /* (M5) WKUP_GPIO0_39 */
+ AM65X_WKUP_IOPAD(0x006C, PIN_INPUT, 7)
+ >;
+ };
+
+ a3_gpio_pullup: a3-gpio-pullup-pins {
+ pinctrl-single,pins = <
+ /* (M5) WKUP_GPIO0_39 */
+ AM65X_WKUP_IOPAD(0x006C, PIN_INPUT, 7)
+ >;
+ };
+
+ a3_gpio_pulldown: a3-gpio-pulldown-pins {
+ pinctrl-single,pins = <
+ /* (M5) WKUP_GPIO0_39 */
+ AM65X_WKUP_IOPAD(0x006C, PIN_INPUT_PULLDOWN, 7)
+ >;
+ };
+
+ a4_gpio: a4-gpio-pins {
+ pinctrl-single,pins = <
+ /* (L2) WKUP_GPIO0_42 */
+ AM65X_WKUP_IOPAD(0x0078, PIN_INPUT, 7)
+ >;
+ };
+
+ a4_gpio_pullup: a4-gpio-pullup-pins {
+ pinctrl-single,pins = <
+ /* (L2) WKUP_GPIO0_42 */
+ AM65X_WKUP_IOPAD(0x0078, PIN_INPUT, 7)
+ >;
+ };
+
+ a4_gpio_pulldown: a4-gpio-pulldown-pins {
+ pinctrl-single,pins = <
+ /* (L2) WKUP_GPIO0_42 */
+ AM65X_WKUP_IOPAD(0x0078, PIN_INPUT_PULLDOWN, 7)
+ >;
+ };
+
+ a5_gpio: a5-gpio-pins {
+ pinctrl-single,pins = <
+ /* (N5) WKUP_GPIO0_35 */
+ AM65X_WKUP_IOPAD(0x005C, PIN_INPUT, 7)
+ >;
+ };
+
+ a5_gpio_pullup: a5-gpio-pullup-pins {
+ pinctrl-single,pins = <
+ /* (N5) WKUP_GPIO0_35 */
+ AM65X_WKUP_IOPAD(0x005C, PIN_INPUT_PULLUP, 7)
+ >;
+ };
+
+ a5_gpio_pulldown: a5-gpio-pulldown-pins {
+ pinctrl-single,pins = <
+ /* (N5) WKUP_GPIO0_35 */
+ AM65X_WKUP_IOPAD(0x005C, PIN_INPUT_PULLDOWN, 7)
+ >;
+ };
+
wkup_i2c0_pins_default: wkup-i2c0-default-pins {
pinctrl-single,pins = <
/* (AC7) WKUP_I2C0_SCL */
@@ -136,23 +637,6 @@
>;
};
- arduino_uart_pins_default: arduino-uart-default-pins {
- pinctrl-single,pins = <
- /* (P4) MCU_UART0_RXD */
- AM65X_WKUP_IOPAD(0x0044, PIN_INPUT, 4)
- /* (P5) MCU_UART0_TXD */
- AM65X_WKUP_IOPAD(0x0048, PIN_OUTPUT, 4)
- >;
- };
-
- arduino_io_d2_to_d3_pins_default: arduino-io-d2-to-d3-default-pins {
- pinctrl-single,pins = <
- /* (P1) WKUP_GPIO0_31 */
- AM65X_WKUP_IOPAD(0x004C, PIN_OUTPUT, 7)
- /* (N3) WKUP_GPIO0_33 */
- AM65X_WKUP_IOPAD(0x0054, PIN_OUTPUT, 7)
- >;
- };
arduino_io_oe_pins_default: arduino-io-oe-default-pins {
pinctrl-single,pins = <
@@ -232,6 +716,220 @@
};
&main_pmx0 {
+ pinctrl-names =
+ "default",
+ "d4-ehrpwm0-a", "d4-gpio", "d4-gpio-pullup", "d4-gpio-pulldown",
+ "d5-ehrpwm1-a", "d5-gpio", "d5-gpio-pullup", "d5-gpio-pulldown",
+ "d6-ehrpwm2-a", "d6-gpio", "d6-gpio-pullup", "d6-gpio-pulldown",
+ "d7-ehrpwm3-a", "d7-gpio", "d7-gpio-pullup", "d7-gpio-pulldown",
+ "d8-ehrpwm4-a", "d8-gpio", "d8-gpio-pullup", "d8-gpio-pulldown",
+ "d9-ehrpwm5-a", "d9-gpio", "d9-gpio-pullup", "d9-gpio-pulldown";
+
+ pinctrl-0 = <&d4_ehrpwm0_a>;
+ pinctrl-1 = <&d4_ehrpwm0_a>;
+ pinctrl-2 = <&d4_gpio>;
+ pinctrl-3 = <&d4_gpio_pullup>;
+ pinctrl-4 = <&d4_gpio_pulldown>;
+
+ pinctrl-5 = <&d5_ehrpwm1_a>;
+ pinctrl-6 = <&d5_gpio>;
+ pinctrl-7 = <&d5_gpio_pullup>;
+ pinctrl-8 = <&d5_gpio_pulldown>;
+
+ pinctrl-9 = <&d6_ehrpwm2_a>;
+ pinctrl-10 = <&d6_gpio>;
+ pinctrl-11 = <&d6_gpio_pullup>;
+ pinctrl-12 = <&d6_gpio_pulldown>;
+
+ pinctrl-13 = <&d7_ehrpwm3_a>;
+ pinctrl-14 = <&d7_gpio>;
+ pinctrl-15 = <&d7_gpio_pullup>;
+ pinctrl-16 = <&d7_gpio_pulldown>;
+
+ pinctrl-17 = <&d8_ehrpwm4_a>;
+ pinctrl-18 = <&d8_gpio>;
+ pinctrl-19 = <&d8_gpio_pullup>;
+ pinctrl-20 = <&d8_gpio_pulldown>;
+
+ pinctrl-21 = <&d9_ehrpwm5_a>;
+ pinctrl-22 = <&d9_gpio>;
+ pinctrl-23 = <&d9_gpio_pullup>;
+ pinctrl-24 = <&d9_gpio_pulldown>;
+
+ d4_ehrpwm0_a: d4-ehrpwm0-a-pins {
+ pinctrl-single,pins = <
+ /* (AG18) EHRPWM0_A */
+ AM65X_IOPAD(0x0084, PIN_OUTPUT, 5)
+ >;
+ };
+
+ d4_gpio: d4-gpio-pins {
+ pinctrl-single,pins = <
+ /* (AG18) GPIO0_33 */
+ AM65X_IOPAD(0x0084, PIN_INPUT, 7)
+ >;
+ };
+
+ d4_gpio_pullup: d4-gpio-pullup-pins {
+ pinctrl-single,pins = <
+ /* (AG18) GPIO0_33 */
+ AM65X_IOPAD(0x0084, PIN_INPUT_PULLUP, 7)
+ >;
+ };
+
+ d4_gpio_pulldown: d4-gpio-pulldown-pins {
+ pinctrl-single,pins = <
+ /* (AG18) GPIO0_33 */
+ AM65X_IOPAD(0x0084, PIN_INPUT_PULLDOWN, 7)
+ >;
+ };
+
+ d5_ehrpwm1_a: d5-ehrpwm1-a-pins {
+ pinctrl-single,pins = <
+ /* (AF17) EHRPWM1_A */
+ AM65X_IOPAD(0x008C, PIN_OUTPUT, 5)
+ >;
+ };
+
+ d5_gpio: d5-gpio-pins {
+ pinctrl-single,pins = <
+ /* (AF17) GPIO0_35 */
+ AM65X_IOPAD(0x008C, PIN_INPUT, 7)
+ >;
+ };
+
+ d5_gpio_pullup: d5-gpio-pullup-pins {
+ pinctrl-single,pins = <
+ /* (AF17) GPIO0_35 */
+ AM65X_IOPAD(0x008C, PIN_INPUT_PULLUP, 7)
+ >;
+ };
+
+ d5_gpio_pulldown: d5-gpio-pulldown-pins {
+ pinctrl-single,pins = <
+ /* (AF17) GPIO0_35 */
+ AM65X_IOPAD(0x008C, PIN_INPUT_PULLDOWN, 7)
+ >;
+ };
+
+ d6_ehrpwm2_a: d6-ehrpwm2-a-pins {
+ pinctrl-single,pins = <
+ /* (AH16) EHRPWM2_A */
+ AM65X_IOPAD(0x0098, PIN_OUTPUT, 5)
+ >;
+ };
+
+ d6_gpio: d6-gpio-pins {
+ pinctrl-single,pins = <
+ /* (AH16) GPIO0_38 */
+ AM65X_IOPAD(0x0098, PIN_INPUT, 7)
+ >;
+ };
+
+ d6_gpio_pullup: d6-gpio-pullup-pins {
+ pinctrl-single,pins = <
+ /* (AH16) GPIO0_38 */
+ AM65X_IOPAD(0x0098, PIN_INPUT_PULLUP, 7)
+ >;
+ };
+
+ d6_gpio_pulldown: d6-gpio-pulldown-pins {
+ pinctrl-single,pins = <
+ /* (AH16) GPIO0_38 */
+ AM65X_IOPAD(0x0098, PIN_INPUT_PULLDOWN, 7)
+ >;
+ };
+
+ d7_ehrpwm3_a: d7-ehrpwm3-a-pins {
+ pinctrl-single,pins = <
+ /* (AH15) EHRPWM3_A */
+ AM65X_IOPAD(0x00AC, PIN_OUTPUT, 5)
+ >;
+ };
+
+ d7_gpio: d7-gpio-pins {
+ pinctrl-single,pins = <
+ /* (AH15) GPIO0_43 */
+ AM65X_IOPAD(0x00AC, PIN_INPUT, 7)
+ >;
+ };
+
+ d7_gpio_pullup: d7-gpio-pullup-pins {
+ pinctrl-single,pins = <
+ /* (AH15) GPIO0_43 */
+ AM65X_IOPAD(0x00AC, PIN_INPUT_PULLUP, 7)
+ >;
+ };
+
+ d7_gpio_pulldown: d7-gpio-pulldown-pins {
+ pinctrl-single,pins = <
+ /* (AH15) GPIO0_43 */
+ AM65X_IOPAD(0x00AC, PIN_INPUT_PULLDOWN, 7)
+ >;
+ };
+
+ d8_ehrpwm4_a: d8-ehrpwm4-a-pins {
+ pinctrl-single,pins = <
+ /* (AG15) EHRPWM4_A */
+ AM65X_IOPAD(0x00C0, PIN_OUTPUT, 5)
+ >;
+ };
+
+ d8_gpio: d8-gpio-pins {
+ pinctrl-single,pins = <
+ /* (AG15) GPIO0_48 */
+ AM65X_IOPAD(0x00C0, PIN_INPUT, 7)
+ >;
+ };
+
+ d8_gpio_pullup: d8-gpio-pullup-pins {
+ pinctrl-single,pins = <
+ /* (AG15) GPIO0_48 */
+ AM65X_IOPAD(0x00C0, PIN_INPUT_PULLUP, 7)
+ >;
+ };
+
+ d8_gpio_pulldown: d8-gpio-pulldown-pins {
+ pinctrl-single,pins = <
+ /* (AG15) GPIO0_48 */
+ AM65X_IOPAD(0x00C0, PIN_INPUT_PULLDOWN, 7)
+ >;
+ };
+
+ d9_ehrpwm5_a: d9-ehrpwm5-a-pins {
+ pinctrl-single,pins = <
+ /* (AD15) EHRPWM5_A */
+ AM65X_IOPAD(0x00CC, PIN_OUTPUT, 5)
+ >;
+ };
+
+ d9_gpio: d9-gpio-pins {
+ pinctrl-single,pins = <
+ /* (AD15) GPIO0_51 */
+ AM65X_IOPAD(0x00CC, PIN_INPUT, 7)
+ >;
+ };
+
+ d9_gpio_pullup: d9-gpio-pullup-pins {
+ pinctrl-single,pins = <
+ /* (AD15) GPIO0_51 */
+ AM65X_IOPAD(0x00CC, PIN_INPUT_PULLUP, 7)
+ >;
+ };
+
+ d9_gpio_pulldown: d9-gpio-pulldown-pins {
+ pinctrl-single,pins = <
+ /* (AD15) GPIO0_51 */
+ AM65X_IOPAD(0x00CC, PIN_INPUT_PULLDOWN, 7)
+ >;
+ };
+
+ main_pcie_enable_pins_default: main-pcie-enable-default-pins {
+ pinctrl-single,pins = <
+ AM65X_IOPAD(0x01c4, PIN_INPUT_PULLUP, 7) /* (AH13) GPIO1_17 */
+ >;
+ };
+
main_uart1_pins_default: main-uart1-default-pins {
pinctrl-single,pins = <
AM65X_IOPAD(0x0174, PIN_INPUT, 6) /* (AE23) UART1_RXD */
@@ -273,17 +971,6 @@
>;
};
- arduino_io_d4_to_d9_pins_default: arduino-io-d4-to-d9-default-pins {
- pinctrl-single,pins = <
- AM65X_IOPAD(0x0084, PIN_OUTPUT, 7) /* (AG18) GPIO0_33 */
- AM65X_IOPAD(0x008C, PIN_OUTPUT, 7) /* (AF17) GPIO0_35 */
- AM65X_IOPAD(0x0098, PIN_OUTPUT, 7) /* (AH16) GPIO0_38 */
- AM65X_IOPAD(0x00AC, PIN_OUTPUT, 7) /* (AH15) GPIO0_43 */
- AM65X_IOPAD(0x00C0, PIN_OUTPUT, 7) /* (AG15) GPIO0_48 */
- AM65X_IOPAD(0x00CC, PIN_OUTPUT, 7) /* (AD15) GPIO0_51 */
- >;
- };
-
dss_vout1_pins_default: dss-vout1-default-pins {
pinctrl-single,pins = <
AM65X_IOPAD(0x0000, PIN_OUTPUT, 1) /* VOUT1_DATA0 */
@@ -329,6 +1016,43 @@
AM65X_IOPAD(0x0070, PIN_INPUT, 5) /* (R25) I2C2_SDA */
>;
};
+
+ icssg0_mdio_pins_default: icssg0-mdio-default-pins {
+ pinctrl-single,pins = <
+ AM65X_IOPAD(0x0294, PIN_INPUT, 0) /* (AE26) PRG0_MDIO0_MDIO */
+ AM65X_IOPAD(0x0298, PIN_OUTPUT, 0) /* (AE28) PRG0_MDIO0_MDC */
+ >;
+ };
+
+ icssg0_rgmii_pins_default: icssg0-rgmii-default-pins {
+ pinctrl-single,pins = <
+ AM65X_IOPAD(0x0244, PIN_INPUT, 2) /* (AB28) PRG0_PRU1_GPO0.PRG0_RGMII2_RD0 */
+ AM65X_IOPAD(0x0248, PIN_INPUT, 2) /* (AC28) PRG0_PRU1_GPO1.PRG0_RGMII2_RD1 */
+ AM65X_IOPAD(0x024c, PIN_INPUT, 2) /* (AC27) PRG0_PRU1_GPO2.PRG0_RGMII2_RD2 */
+ AM65X_IOPAD(0x0250, PIN_INPUT, 2) /* (AB26) PRG0_PRU1_GPO3.PRG0_RGMII2_RD3 */
+ AM65X_IOPAD(0x0274, PIN_OUTPUT, 2) /* (AC25) PRG0_PRU1_GPO12.PRG0_RGMII2_TD0 */
+ AM65X_IOPAD(0x0278, PIN_OUTPUT, 2) /* (AD25) PRG0_PRU1_GPO13.PRG0_RGMII2_TD1 */
+ AM65X_IOPAD(0x027c, PIN_OUTPUT, 2) /* (AD24) PRG0_PRU1_GPO14.PRG0_RGMII2_TD2 */
+ AM65X_IOPAD(0x0280, PIN_OUTPUT, 2) /* (AE27) PRG0_PRU1_GPO15.PRG0_RGMII2_TD3 */
+ AM65X_IOPAD(0x0284, PIN_INPUT, 2) /* (AC24) PRG0_PRU1_GPO16.PRG0_RGMII2_TXC */
+ AM65X_IOPAD(0x0270, PIN_OUTPUT, 2) /* (AB24) PRG0_PRU1_GPO11.PRG0_RGMII2_TX_CTL */
+ AM65X_IOPAD(0x025c, PIN_INPUT, 2) /* (AB27) PRG0_PRU1_GPO6.PRG0_RGMII2_RXC */
+ AM65X_IOPAD(0x0254, PIN_INPUT, 2) /* (AA25) PRG0_PRU1_GPO4.PRG0_RGMII2_RX_CTL */
+
+ AM65X_IOPAD(0x01f4, PIN_INPUT, 2) /* (V24) PRG0_PRU0_GPO0.PRG0_RGMII1_RD0 */
+ AM65X_IOPAD(0x01f8, PIN_INPUT, 2) /* (W25) PRG0_PRU0_GPO1.PRG0_RGMII1_RD1 */
+ AM65X_IOPAD(0x01fc, PIN_INPUT, 2) /* (W24) PRG0_PRU0_GPO2.PRG0_RGMII1_RD2 */
+ AM65X_IOPAD(0x0200, PIN_INPUT, 2) /* (AA27) PRG0_PRU0_GPO3.PRG0_RGMII1_RD3 */
+ AM65X_IOPAD(0x0224, PIN_OUTPUT, 2) /* (AD27) PRG0_PRU0_GPO12.PRG0_RGMII1_TD0 */
+ AM65X_IOPAD(0x0228, PIN_OUTPUT, 2) /* (AC26) PRG0_PRU0_GPO13.PRG0_RGMII1_TD1 */
+ AM65X_IOPAD(0x022c, PIN_OUTPUT, 2) /* (AD26) PRG0_PRU0_GPO14.PRG0_RGMII1_TD2 */
+ AM65X_IOPAD(0x0230, PIN_OUTPUT, 2) /* (AA24) PRG0_PRU0_GPO15.PRG0_RGMII1_TD3 */
+ AM65X_IOPAD(0x0234, PIN_INPUT, 2) /* (AD28) PRG0_PRU0_GPO16.PRG0_RGMII1_TXC */
+ AM65X_IOPAD(0x0220, PIN_OUTPUT, 2) /* (AB25) PRG0_PRU0_GPO11.PRG0_RGMII1_TX_CTL */
+ AM65X_IOPAD(0x020c, PIN_INPUT, 2) /* (Y25) PRG0_PRU0_GPO6.PRG0_RGMII1_RXC */
+ AM65X_IOPAD(0x0204, PIN_INPUT, 2) /* (Y24) PRG0_PRU0_GPO4.PRG0_RGMII1_RX_CTL */
+ >;
+ };
};
&main_pmx1 {
@@ -345,12 +1069,6 @@
AM65X_IOPAD(0x000c, PIN_INPUT, 0) /* (E21) I2C1_SDA */
>;
};
-
- ecap0_pins_default: ecap0-default-pins {
- pinctrl-single,pins = <
- AM65X_IOPAD(0x0010, PIN_INPUT, 0) /* (D21) ECAP0_IN_APWM_OUT */
- >;
- };
};
&wkup_uart0 {
@@ -366,13 +1084,9 @@
&mcu_uart0 {
status = "okay";
- pinctrl-names = "default";
- pinctrl-0 = <&arduino_uart_pins_default>;
};
&main_gpio0 {
- pinctrl-names = "default";
- pinctrl-0 = <&arduino_io_d4_to_d9_pins_default>;
gpio-line-names =
"main_gpio0-base", "", "", "", "", "", "", "", "", "",
"", "", "", "", "", "", "", "", "", "",
@@ -382,10 +1096,14 @@
"", "IO9";
};
+&main_gpio1 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&main_pcie_enable_pins_default>;
+};
+
&wkup_gpio0 {
pinctrl-names = "default";
pinctrl-0 =
- <&arduino_io_d2_to_d3_pins_default>,
<&arduino_i2c_aio_switch_pins_default>,
<&arduino_io_oe_pins_default>,
<&push_button_pins_default>,
@@ -547,13 +1265,8 @@
status = "disabled";
};
-&ecap0 {
- status = "okay";
- pinctrl-names = "default";
- pinctrl-0 = <&ecap0_pins_default>;
-};
-
&sdhci1 {
+ status = "okay";
pinctrl-names = "default";
pinctrl-0 = <&main_mmc1_pins_default>;
ti,driver-strength-ohm = <50>;
@@ -574,9 +1287,6 @@
&mcu_spi0 {
status = "okay";
- pinctrl-names = "default";
- pinctrl-0 = <&mcu_spi0_pins_default>;
-
#address-cells = <1>;
#size-cells = <0>;
ti,pindir-d0-out-d1-in;
@@ -716,3 +1426,21 @@
<&mcu_r5fss0_core1_memory_region>;
mboxes = <&mailbox0_cluster1>, <&mbox_mcu_r5fss0_core1>;
};
+
+&icssg0_mdio {
+ status = "okay";
+ pinctrl-names = "default";
+ pinctrl-0 = <&icssg0_mdio_pins_default>;
+
+ icssg0_eth0_phy: ethernet-phy@0 {
+ reg = <0>;
+ ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_00_NS>;
+ ti,fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>;
+ };
+
+ icssg0_eth1_phy: ethernet-phy@1 {
+ reg = <1>;
+ ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_00_NS>;
+ ti,fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>;
+ };
+};
diff --git a/dts/upstream/src/arm64/ti/k3-am65-main.dtsi b/dts/upstream/src/arm64/ti/k3-am65-main.dtsi
index 5ebb87f..fcea544 100644
--- a/dts/upstream/src/arm64/ti/k3-am65-main.dtsi
+++ b/dts/upstream/src/arm64/ti/k3-am65-main.dtsi
@@ -449,6 +449,7 @@
ti,otap-del-sel-hs400 = <0x0>;
ti,trm-icp = <0x8>;
dma-coherent;
+ status = "disabled";
};
sdhci1: mmc@4fa0000 {
@@ -471,6 +472,7 @@
ti,clkbuf-sel = <0x7>;
ti,trm-icp = <0x8>;
dma-coherent;
+ status = "disabled";
};
scm_conf: scm-conf@100000 {
@@ -498,8 +500,8 @@
};
dss_oldi_io_ctrl: dss-oldi-io-ctrl@41e0 {
- compatible = "syscon";
- reg = <0x000041e0 0x14>;
+ compatible = "ti,am654-dss-oldi-io-ctrl", "syscon";
+ reg = <0x41e0 0x14>;
};
ehrpwm_tbclk: clock-controller@4140 {
@@ -790,8 +792,12 @@
compatible = "ti,am654-navss-main-udmap";
reg = <0x0 0x31150000 0x0 0x100>,
<0x0 0x34000000 0x0 0x100000>,
- <0x0 0x35000000 0x0 0x100000>;
- reg-names = "gcfg", "rchanrt", "tchanrt";
+ <0x0 0x35000000 0x0 0x100000>,
+ <0x0 0x30b00000 0x0 0x10000>,
+ <0x0 0x30c00000 0x0 0x10000>,
+ <0x0 0x30d00000 0x0 0x8000>;
+ reg-names = "gcfg", "rchanrt", "tchanrt",
+ "tchan", "rchan", "rflow";
msi-parent = <&inta_main_udmass>;
#dma-cells = <1>;
@@ -1034,7 +1040,7 @@
assigned-clocks = <&k3_clks 67 2>;
assigned-clock-parents = <&k3_clks 67 5>;
- interrupts = <GIC_SPI 166 IRQ_TYPE_EDGE_RISING>;
+ interrupts = <GIC_SPI 166 IRQ_TYPE_LEVEL_HIGH>;
dma-coherent;
diff --git a/dts/upstream/src/arm64/ti/k3-am65-mcu.dtsi b/dts/upstream/src/arm64/ti/k3-am65-mcu.dtsi
index edd5cfb..ecd7356 100644
--- a/dts/upstream/src/arm64/ti/k3-am65-mcu.dtsi
+++ b/dts/upstream/src/arm64/ti/k3-am65-mcu.dtsi
@@ -214,8 +214,12 @@
compatible = "ti,am654-navss-mcu-udmap";
reg = <0x0 0x285c0000 0x0 0x100>,
<0x0 0x2a800000 0x0 0x40000>,
- <0x0 0x2aa00000 0x0 0x40000>;
- reg-names = "gcfg", "rchanrt", "tchanrt";
+ <0x0 0x2aa00000 0x0 0x40000>,
+ <0x0 0x284a0000 0x0 0x4000>,
+ <0x0 0x284c0000 0x0 0x4000>,
+ <0x0 0x28400000 0x0 0x2000>;
+ reg-names = "gcfg", "rchanrt", "tchanrt",
+ "tchan", "rchan", "rflow";
msi-parent = <&inta_main_udmass>;
#dma-cells = <1>;
diff --git a/dts/upstream/src/arm64/ti/k3-am65-wakeup.dtsi b/dts/upstream/src/arm64/ti/k3-am65-wakeup.dtsi
index fd2b998..f037b36 100644
--- a/dts/upstream/src/arm64/ti/k3-am65-wakeup.dtsi
+++ b/dts/upstream/src/arm64/ti/k3-am65-wakeup.dtsi
@@ -34,9 +34,16 @@
};
};
- chipid@43000014 {
- compatible = "ti,am654-chipid";
- reg = <0x43000014 0x4>;
+ wkup_conf: bus@43000000 {
+ compatible = "simple-bus";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0x0 0x43000000 0x20000>;
+
+ chipid: chipid@14 {
+ compatible = "ti,am654-chipid";
+ reg = <0x14 0x4>;
+ };
};
wkup_pmx0: pinctrl@4301c000 {
diff --git a/arch/arm/dts/k3-am642.dtsi b/dts/upstream/src/arm64/ti/k3-am652.dtsi
similarity index 69%
rename from arch/arm/dts/k3-am642.dtsi
rename to dts/upstream/src/arm64/ti/k3-am652.dtsi
index 7a6eede..0f22e00 100644
--- a/arch/arm/dts/k3-am642.dtsi
+++ b/dts/upstream/src/arm64/ti/k3-am652.dtsi
@@ -1,19 +1,16 @@
// SPDX-License-Identifier: GPL-2.0
/*
- * Device Tree Source for AM642 SoC family in Dual core configuration
+ * Device Tree Source for AM65 SoC family in Dual core configuration
*
- * Copyright (C) 2020-2021 Texas Instruments Incorporated - https://www.ti.com/
+ * Copyright (C) 2023 Texas Instruments Incorporated - https://www.ti.com/
*/
-/dts-v1/;
-
-#include "k3-am64.dtsi"
+#include "k3-am65.dtsi"
/ {
cpus {
#address-cells = <1>;
#size-cells = <0>;
-
cpu-map {
cluster0: cluster0 {
core0 {
@@ -59,8 +56,19 @@
compatible = "cache";
cache-level = <2>;
cache-unified;
- cache-size = <0x40000>;
+ cache-size = <0x80000>;
cache-line-size = <64>;
- cache-sets = <256>;
+ cache-sets = <512>;
+ next-level-cache = <&msmc_l3>;
+ };
+
+ msmc_l3: l3-cache0 {
+ compatible = "cache";
+ cache-level = <3>;
+ cache-unified;
+ };
+
+ thermal_zones: thermal-zones {
+ #include "k3-am654-industrial-thermal.dtsi"
};
};
diff --git a/dts/upstream/src/arm64/ti/k3-am6528-iot2050-basic-common.dtsi b/dts/upstream/src/arm64/ti/k3-am6528-iot2050-basic-common.dtsi
index 5ab434c..1d6cddb 100644
--- a/dts/upstream/src/arm64/ti/k3-am6528-iot2050-basic-common.dtsi
+++ b/dts/upstream/src/arm64/ti/k3-am6528-iot2050-basic-common.dtsi
@@ -9,6 +9,7 @@
* Common bits of the IOT2050 Basic variant, PG1 and PG2
*/
+#include "k3-am652.dtsi"
#include "k3-am65-iot2050-common.dtsi"
/ {
@@ -17,21 +18,6 @@
/* 1G RAM */
reg = <0x00000000 0x80000000 0x00000000 0x40000000>;
};
-
- cpus {
- cpu-map {
- /delete-node/ cluster1;
- };
- /delete-node/ cpu@100;
- /delete-node/ cpu@101;
- };
-
- /delete-node/ l2-cache1;
-};
-
-/* eMMC */
-&sdhci0 {
- status = "disabled";
};
&main_pmx0 {
diff --git a/dts/upstream/src/arm64/ti/k3-am654-base-board.dts b/dts/upstream/src/arm64/ti/k3-am654-base-board.dts
index 1637ec5..822c288 100644
--- a/dts/upstream/src/arm64/ti/k3-am654-base-board.dts
+++ b/dts/upstream/src/arm64/ti/k3-am654-base-board.dts
@@ -449,6 +449,7 @@
};
&sdhci0 {
+ status = "okay";
pinctrl-names = "default";
pinctrl-0 = <&main_mmc0_pins_default>;
bus-width = <8>;
@@ -463,6 +464,7 @@
* disable sdhci1
*/
&sdhci1 {
+ status = "okay";
vmmc-supply = <&vdd_mmc1_sd>;
pinctrl-names = "default";
pinctrl-0 = <&main_mmc1_pins_default>;
diff --git a/dts/upstream/src/arm64/ti/k3-am6548-iot2050-advanced-common.dtsi b/dts/upstream/src/arm64/ti/k3-am6548-iot2050-advanced-common.dtsi
index be55494..3864ec5 100644
--- a/dts/upstream/src/arm64/ti/k3-am6548-iot2050-advanced-common.dtsi
+++ b/dts/upstream/src/arm64/ti/k3-am6548-iot2050-advanced-common.dtsi
@@ -11,6 +11,7 @@
/dts-v1/;
+#include "k3-am654.dtsi"
#include "k3-am65-iot2050-common.dtsi"
/ {
@@ -43,6 +44,7 @@
/* eMMC */
&sdhci0 {
+ status = "okay";
pinctrl-names = "default";
pinctrl-0 = <&main_mmc0_pins_default>;
bus-width = <8>;
diff --git a/dts/upstream/src/arm64/ti/k3-am6548-iot2050-advanced-m2.dts b/dts/upstream/src/arm64/ti/k3-am6548-iot2050-advanced-m2.dts
index 774eb14..bd6f2e6 100644
--- a/dts/upstream/src/arm64/ti/k3-am6548-iot2050-advanced-m2.dts
+++ b/dts/upstream/src/arm64/ti/k3-am6548-iot2050-advanced-m2.dts
@@ -27,12 +27,6 @@
};
&main_pmx0 {
- main_m2_enable_pins_default: main-m2-enable-default-pins {
- pinctrl-single,pins = <
- AM65X_IOPAD(0x01c4, PIN_INPUT_PULLUP, 7) /* (AH13) GPIO1_17 */
- >;
- };
-
main_bkey_pcie_reset: main-bkey-pcie-reset-default-pins {
pinctrl-single,pins = <
AM65X_IOPAD(0x01bc, PIN_OUTPUT_PULLUP, 7) /* (AG13) GPIO1_15 */
@@ -66,15 +60,13 @@
&main_gpio0 {
pinctrl-names = "default";
- pinctrl-0 =
- <&main_m2_pcie_mux_control>,
- <&arduino_io_d4_to_d9_pins_default>;
+ pinctrl-0 = <&main_m2_pcie_mux_control>;
};
&main_gpio1 {
pinctrl-names = "default";
pinctrl-0 =
- <&main_m2_enable_pins_default>,
+ <&main_pcie_enable_pins_default>,
<&main_pmx0_m2_config_pins_default>,
<&main_pmx1_m2_config_pins_default>,
<&cp2102n_reset_pin_default>;
diff --git a/dts/upstream/src/arm64/ti/k3-am68-sk-base-board.dts b/dts/upstream/src/arm64/ti/k3-am68-sk-base-board.dts
index 1e1a82f..d0cfdea 100644
--- a/dts/upstream/src/arm64/ti/k3-am68-sk-base-board.dts
+++ b/dts/upstream/src/arm64/ti/k3-am68-sk-base-board.dts
@@ -31,6 +31,7 @@
can1 = &mcu_mcan1;
can2 = &main_mcan6;
can3 = &main_mcan7;
+ ethernet0 = &cpsw_port1;
};
vusb_main: regulator-vusb-main5v0 {
diff --git a/dts/upstream/src/arm64/ti/k3-am69-sk.dts b/dts/upstream/src/arm64/ti/k3-am69-sk.dts
index 9868c70..8da5915 100644
--- a/dts/upstream/src/arm64/ti/k3-am69-sk.dts
+++ b/dts/upstream/src/arm64/ti/k3-am69-sk.dts
@@ -433,6 +433,13 @@
&wkup_pmx2 {
bootph-all;
+ pmic_irq_pins_default: pmic-irq-default-pins {
+ pinctrl-single,pins = <
+ /* (AA37) MCU_ADC1_AIN4.WKUP_GPIO0_83 */
+ J784S4_WKUP_IOPAD(0x0fc, PIN_INPUT, 7)
+ >;
+ };
+
wkup_uart0_pins_default: wkup-uart0-default-pins {
bootph-all;
pinctrl-single,pins = <
@@ -631,6 +638,93 @@
compatible = "atmel,24c512";
reg = <0x51>;
};
+
+ tps659413: pmic@48 {
+ compatible = "ti,tps6594-q1";
+ reg = <0x48>;
+ system-power-controller;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pmic_irq_pins_default>;
+ interrupt-parent = <&wkup_gpio0>;
+ interrupts = <39 IRQ_TYPE_EDGE_FALLING>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ ti,primary-pmic;
+ buck12-supply = <&vsys_3v3>;
+ buck3-supply = <&vsys_3v3>;
+ buck4-supply = <&vsys_3v3>;
+ buck5-supply = <&vsys_3v3>;
+ ldo1-supply = <&vsys_3v3>;
+ ldo2-supply = <&vsys_3v3>;
+ ldo3-supply = <&vsys_3v3>;
+ ldo4-supply = <&vsys_3v3>;
+
+ regulators {
+ bucka12: buck12 {
+ regulator-name = "vdd_ddr_1v1";
+ regulator-min-microvolt = <1100000>;
+ regulator-max-microvolt = <1100000>;
+ regulator-boot-on;
+ regulator-always-on;
+ };
+
+ bucka3: buck3 {
+ regulator-name = "vdd_ram_0v85";
+ regulator-min-microvolt = <850000>;
+ regulator-max-microvolt = <850000>;
+ regulator-boot-on;
+ regulator-always-on;
+ };
+
+ bucka4: buck4 {
+ regulator-name = "vdd_io_1v8";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-boot-on;
+ regulator-always-on;
+ };
+
+ bucka5: buck5 {
+ regulator-name = "vdd_mcu_0v85";
+ regulator-min-microvolt = <850000>;
+ regulator-max-microvolt = <850000>;
+ regulator-boot-on;
+ regulator-always-on;
+ };
+
+ ldoa1: ldo1 {
+ regulator-name = "vdd_mcuio_1v8";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-boot-on;
+ regulator-always-on;
+ };
+
+ ldoa2: ldo2 {
+ regulator-name = "vdd_mcuio_3v3";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-boot-on;
+ regulator-always-on;
+ };
+
+ ldoa3: ldo3 {
+ regulator-name = "vds_dll_0v8";
+ regulator-min-microvolt = <800000>;
+ regulator-max-microvolt = <800000>;
+ regulator-boot-on;
+ regulator-always-on;
+ };
+
+ ldoa4: ldo4 {
+ regulator-name = "vda_mcu_1v8";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-boot-on;
+ regulator-always-on;
+ };
+ };
+ };
};
&wkup_gpio0 {
@@ -671,7 +765,7 @@
reg = <0x21>;
gpio-controller;
#gpio-cells = <2>;
- gpio-line-names = "BOARDID_EEPROM_WP", "CAN_STB", "GPIO_uSD_PWR_EN",
+ gpio-line-names = "BOARDID_EEPROM_WP", "CAN_STB", "GPIO_uSD_PWR_EN",
"IO_EXP_MCU_RGMII_RST#", "IO_EXP_PCIe0_4L_PERST#",
"IO_EXP_PCIe1_M.2_RTSz", "IO_EXP_PCIe3_M.2_RTSz",
"PM_INA_BUS_EN", "ENET1_EXP_PWRDN", "EXP1_ENET_RSTz",
diff --git a/dts/upstream/src/arm64/ti/k3-j7200-main.dtsi b/dts/upstream/src/arm64/ti/k3-j7200-main.dtsi
index 264913f..da67bf8 100644
--- a/dts/upstream/src/arm64/ti/k3-j7200-main.dtsi
+++ b/dts/upstream/src/arm64/ti/k3-j7200-main.dtsi
@@ -281,8 +281,12 @@
compatible = "ti,j721e-navss-main-udmap";
reg = <0x00 0x31150000 0x00 0x100>,
<0x00 0x34000000 0x00 0x100000>,
- <0x00 0x35000000 0x00 0x100000>;
- reg-names = "gcfg", "rchanrt", "tchanrt";
+ <0x00 0x35000000 0x00 0x100000>,
+ <0x00 0x30b00000 0x00 0x4000>,
+ <0x00 0x30c00000 0x00 0x4000>,
+ <0x00 0x30d00000 0x00 0x4000>;
+ reg-names = "gcfg", "rchanrt", "tchanrt",
+ "tchan", "rchan", "rflow";
msi-parent = <&main_udmass_inta>;
#dma-cells = <1>;
@@ -647,6 +651,7 @@
ti,otap-del-sel-hs400 = <0x5>;
ti,itap-del-sel-legacy = <0x10>;
ti,itap-del-sel-mmc-hs = <0xa>;
+ ti,itap-del-sel-ddr52 = <0x3>;
ti,strobe-sel = <0x77>;
ti,clkbuf-sel = <0x7>;
ti,trm-icp = <0x8>;
diff --git a/dts/upstream/src/arm64/ti/k3-j7200-mcu-wakeup.dtsi b/dts/upstream/src/arm64/ti/k3-j7200-mcu-wakeup.dtsi
index 3fc588b..60b2637 100644
--- a/dts/upstream/src/arm64/ti/k3-j7200-mcu-wakeup.dtsi
+++ b/dts/upstream/src/arm64/ti/k3-j7200-mcu-wakeup.dtsi
@@ -178,9 +178,16 @@
};
};
- chipid@43000014 {
- compatible = "ti,am654-chipid";
- reg = <0x00 0x43000014 0x00 0x4>;
+ wkup_conf: bus@43000000 {
+ compatible = "simple-bus";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0x0 0x00 0x43000000 0x20000>;
+
+ chipid: chipid@14 {
+ compatible = "ti,am654-chipid";
+ reg = <0x14 0x4>;
+ };
};
/* MCU_TIMERIO pad input CTRLMMR_MCU_TIMER*_CTRL registers */
@@ -346,8 +353,12 @@
compatible = "ti,j721e-navss-mcu-udmap";
reg = <0x00 0x285c0000 0x00 0x100>,
<0x00 0x2a800000 0x00 0x40000>,
- <0x00 0x2aa00000 0x00 0x40000>;
- reg-names = "gcfg", "rchanrt", "tchanrt";
+ <0x00 0x2aa00000 0x00 0x40000>,
+ <0x00 0x284a0000 0x00 0x4000>,
+ <0x00 0x284c0000 0x00 0x4000>,
+ <0x00 0x28400000 0x00 0x2000>;
+ reg-names = "gcfg", "rchanrt", "tchanrt",
+ "tchan", "rchan", "rflow";
msi-parent = <&main_udmass_inta>;
#dma-cells = <1>;
diff --git a/dts/upstream/src/arm64/ti/k3-j7200-som-p0.dtsi b/dts/upstream/src/arm64/ti/k3-j7200-som-p0.dtsi
index 5a300d4..ea47f10 100644
--- a/dts/upstream/src/arm64/ti/k3-j7200-som-p0.dtsi
+++ b/dts/upstream/src/arm64/ti/k3-j7200-som-p0.dtsi
@@ -127,6 +127,14 @@
};
};
+&wkup_pmx3 {
+ pmic_irq_pins_default: pmic-irq-default-pins {
+ pinctrl-single,pins = <
+ J721E_WKUP_IOPAD(0x01c, PIN_INPUT, 7) /* (E18) WKUP_GPIO0_84 */
+ >;
+ };
+};
+
&main_pmx0 {
main_i2c0_pins_default: main-i2c0-default-pins {
pinctrl-single,pins = <
@@ -264,6 +272,151 @@
compatible = "atmel,24c256";
reg = <0x50>;
};
+
+ tps659414: pmic@48 {
+ compatible = "ti,tps6594-q1";
+ reg = <0x48>;
+ system-power-controller;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pmic_irq_pins_default>;
+ interrupt-parent = <&wkup_gpio0>;
+ interrupts = <84 IRQ_TYPE_EDGE_FALLING>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ ti,primary-pmic;
+ buck1-supply = <&vsys_3v3>;
+ buck2-supply = <&vsys_3v3>;
+ buck3-supply = <&vsys_3v3>;
+ buck4-supply = <&vsys_3v3>;
+ buck5-supply = <&vsys_3v3>;
+ ldo1-supply = <&vsys_3v3>;
+ ldo2-supply = <&vsys_3v3>;
+ ldo3-supply = <&vsys_3v3>;
+ ldo4-supply = <&vsys_3v3>;
+
+ regulators {
+ bucka1: buck1 {
+ regulator-name = "vda_mcu_1v8";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-boot-on;
+ regulator-always-on;
+ };
+
+ bucka2: buck2 {
+ regulator-name = "vdd_mcuio_1v8";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-boot-on;
+ regulator-always-on;
+ };
+
+ bucka3: buck3 {
+ regulator-name = "vdd_mcu_0v85";
+ regulator-min-microvolt = <850000>;
+ regulator-max-microvolt = <850000>;
+ regulator-boot-on;
+ regulator-always-on;
+ };
+
+ bucka4: buck4 {
+ regulator-name = "vdd_ddr_1v1";
+ regulator-min-microvolt = <1100000>;
+ regulator-max-microvolt = <1100000>;
+ regulator-boot-on;
+ regulator-always-on;
+ };
+
+ bucka5: buck5 {
+ regulator-name = "vdd_phyio_1v8";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-boot-on;
+ regulator-always-on;
+ };
+
+ ldoa1: ldo1 {
+ regulator-name = "vdd1_lpddr4_1v8";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-boot-on;
+ regulator-always-on;
+ };
+
+ ldoa2: ldo2 {
+ regulator-name = "vda_dll_0v8";
+ regulator-min-microvolt = <800000>;
+ regulator-max-microvolt = <800000>;
+ regulator-boot-on;
+ regulator-always-on;
+ };
+
+ ldoa3: ldo3 {
+ regulator-name = "vdd_wk_0v8";
+ regulator-min-microvolt = <800000>;
+ regulator-max-microvolt = <800000>;
+ regulator-boot-on;
+ regulator-always-on;
+ };
+
+ ldoa4: ldo4 {
+ regulator-name = "vda_pll_1v8";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-boot-on;
+ regulator-always-on;
+ };
+ };
+ };
+
+ lp876441: pmic@4c {
+ compatible = "ti,lp8764-q1";
+ reg = <0x4c>;
+ system-power-controller;
+ interrupt-parent = <&wkup_gpio0>;
+ interrupts = <84 IRQ_TYPE_EDGE_FALLING>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ buck1-supply = <&vsys_3v3>;
+ buck2-supply = <&vsys_3v3>;
+ buck3-supply = <&vsys_3v3>;
+ buck4-supply = <&vsys_3v3>;
+
+ regulators: regulators {
+ buckb1: buck1 {
+ regulator-name = "vdd_cpu_avs";
+ regulator-min-microvolt = <600000>;
+ regulator-max-microvolt = <900000>;
+ regulator-always-on;
+ regulator-boot-on;
+ bootph-pre-ram;
+ };
+
+ buckb2: buck2 {
+ regulator-name = "vdd_ram_0v85";
+ regulator-min-microvolt = <850000>;
+ regulator-max-microvolt = <850000>;
+ regulator-boot-on;
+ regulator-always-on;
+ };
+
+ buckb3: buck3 {
+ regulator-name = "vdd_core_0v85";
+ regulator-min-microvolt = <850000>;
+ regulator-max-microvolt = <850000>;
+ regulator-boot-on;
+ regulator-always-on;
+ };
+
+ buckb4: buck4 {
+ regulator-name = "vdd_io_1v8";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-boot-on;
+ regulator-always-on;
+ };
+ };
+ };
};
&ospi0 {
diff --git a/dts/upstream/src/arm64/ti/k3-j721e-evm-pcie0-ep.dtso b/dts/upstream/src/arm64/ti/k3-j721e-evm-pcie0-ep.dtso
new file mode 100644
index 0000000..0c82a13
--- /dev/null
+++ b/dts/upstream/src/arm64/ti/k3-j721e-evm-pcie0-ep.dtso
@@ -0,0 +1,53 @@
+// SPDX-License-Identifier: GPL-2.0
+/**
+ * DT Overlay for enabling PCIE0 instance in Endpoint Configuration with the
+ * J7 common processor board.
+ *
+ * J7 Common Processor Board Product Link: https://www.ti.com/tool/J721EXCPXEVM
+ *
+ * Copyright (C) 2023 Texas Instruments Incorporated - https://www.ti.com/
+ */
+
+/dts-v1/;
+/plugin/;
+
+#include <dt-bindings/interrupt-controller/arm-gic.h>
+#include <dt-bindings/soc/ti,sci_pm_domain.h>
+
+#include "k3-pinctrl.h"
+
+/*
+ * Since Root Complex and Endpoint modes are mutually exclusive
+ * disable Root Complex mode.
+ */
+&pcie0_rc {
+ status = "disabled";
+};
+
+&cbass_main {
+ #address-cells = <2>;
+ #size-cells = <2>;
+ interrupt-parent = <&gic500>;
+
+ pcie0_ep: pcie-ep@2900000 {
+ compatible = "ti,j721e-pcie-ep";
+ reg = <0x00 0x02900000 0x00 0x1000>,
+ <0x00 0x02907000 0x00 0x400>,
+ <0x00 0x0d000000 0x00 0x00800000>,
+ <0x00 0x10000000 0x00 0x08000000>;
+ reg-names = "intd_cfg", "user_cfg", "reg", "mem";
+ interrupt-names = "link_state";
+ interrupts = <GIC_SPI 318 IRQ_TYPE_EDGE_RISING>;
+ ti,syscon-pcie-ctrl = <&scm_conf 0x4070>;
+ max-link-speed = <3>;
+ num-lanes = <1>;
+ power-domains = <&k3_pds 239 TI_SCI_PD_EXCLUSIVE>;
+ clocks = <&k3_clks 239 1>;
+ clock-names = "fck";
+ max-functions = /bits/ 8 <6>;
+ max-virtual-functions = /bits/ 8 <4 4 4 4 0 0>;
+ dma-coherent;
+ phys = <&serdes0_pcie_link>;
+ phy-names = "pcie-phy";
+ };
+};
diff --git a/dts/upstream/src/arm64/ti/k3-j721e-main.dtsi b/dts/upstream/src/arm64/ti/k3-j721e-main.dtsi
index 746b9f8..2569b4c 100644
--- a/dts/upstream/src/arm64/ti/k3-j721e-main.dtsi
+++ b/dts/upstream/src/arm64/ti/k3-j721e-main.dtsi
@@ -382,8 +382,12 @@
compatible = "ti,j721e-navss-main-udmap";
reg = <0x0 0x31150000 0x0 0x100>,
<0x0 0x34000000 0x0 0x100000>,
- <0x0 0x35000000 0x0 0x100000>;
- reg-names = "gcfg", "rchanrt", "tchanrt";
+ <0x0 0x35000000 0x0 0x100000>,
+ <0x0 0x30b00000 0x0 0x20000>,
+ <0x0 0x30c00000 0x0 0x10000>,
+ <0x0 0x30d00000 0x0 0x8000>;
+ reg-names = "gcfg", "rchanrt", "tchanrt",
+ "tchan", "rchan", "rflow";
msi-parent = <&main_udmass_inta>;
#dma-cells = <1>;
diff --git a/dts/upstream/src/arm64/ti/k3-j721e-mcu-wakeup.dtsi b/dts/upstream/src/arm64/ti/k3-j721e-mcu-wakeup.dtsi
index f7ab771..a74912d 100644
--- a/dts/upstream/src/arm64/ti/k3-j721e-mcu-wakeup.dtsi
+++ b/dts/upstream/src/arm64/ti/k3-j721e-mcu-wakeup.dtsi
@@ -48,9 +48,16 @@
};
};
- chipid@43000014 {
- compatible = "ti,am654-chipid";
- reg = <0x0 0x43000014 0x0 0x4>;
+ wkup_conf: bus@43000000 {
+ compatible = "simple-bus";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0x0 0x00 0x43000000 0x20000>;
+
+ chipid: chipid@14 {
+ compatible = "ti,am654-chipid";
+ reg = <0x14 0x4>;
+ };
};
wkup_pmx0: pinctrl@4301c000 {
@@ -468,8 +475,12 @@
compatible = "ti,j721e-navss-mcu-udmap";
reg = <0x0 0x285c0000 0x0 0x100>,
<0x0 0x2a800000 0x0 0x40000>,
- <0x0 0x2aa00000 0x0 0x40000>;
- reg-names = "gcfg", "rchanrt", "tchanrt";
+ <0x0 0x2aa00000 0x0 0x40000>,
+ <0x0 0x284a0000 0x0 0x4000>,
+ <0x0 0x284c0000 0x0 0x4000>,
+ <0x0 0x28400000 0x0 0x2000>;
+ reg-names = "gcfg", "rchanrt", "tchanrt",
+ "tchan", "rchan", "rflow";
msi-parent = <&main_udmass_inta>;
#dma-cells = <1>;
diff --git a/dts/upstream/src/arm64/ti/k3-j721e-sk.dts b/dts/upstream/src/arm64/ti/k3-j721e-sk.dts
index 42fe8ee..188dfe2 100644
--- a/dts/upstream/src/arm64/ti/k3-j721e-sk.dts
+++ b/dts/upstream/src/arm64/ti/k3-j721e-sk.dts
@@ -459,6 +459,12 @@
};
&wkup_pmx0 {
+ pmic_irq_pins_default: pmic-irq-default-pins {
+ pinctrl-single,pins = <
+ J721E_WKUP_IOPAD(0x0cc, PIN_INPUT, 7) /* (G28) WKUP_GPIO0_7 */
+ >;
+ };
+
mcu_cpsw_pins_default: mcu-cpsw-default-pins {
pinctrl-single,pins = <
J721E_WKUP_IOPAD(0x84, PIN_INPUT, 0) /* (B24) MCU_RGMII1_RD0 */
@@ -560,6 +566,151 @@
compatible = "atmel,24c512";
reg = <0x51>;
};
+
+ tps659413: pmic@48 {
+ compatible = "ti,tps6594-q1";
+ reg = <0x48>;
+ system-power-controller;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pmic_irq_pins_default>;
+ interrupt-parent = <&wkup_gpio0>;
+ interrupts = <9 IRQ_TYPE_EDGE_FALLING>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ ti,primary-pmic;
+ buck123-supply = <&vsys_3v3>;
+ buck4-supply = <&vsys_3v3>;
+ buck5-supply = <&vsys_3v3>;
+ ldo1-supply = <&vsys_3v3>;
+ ldo2-supply = <&vsys_3v3>;
+ ldo3-supply = <&vsys_3v3>;
+ ldo4-supply = <&vsys_3v3>;
+
+ regulators {
+ bucka123: buck123 {
+ regulator-name = "vdd_cpu_avs";
+ regulator-min-microvolt = <600000>;
+ regulator-max-microvolt = <900000>;
+ regulator-boot-on;
+ regulator-always-on;
+ bootph-pre-ram;
+ };
+
+ bucka4: buck4 {
+ regulator-name = "vdd_mcu_0v85";
+ regulator-min-microvolt = <850000>;
+ regulator-max-microvolt = <850000>;
+ regulator-boot-on;
+ regulator-always-on;
+ };
+
+ bucka5: buck5 {
+ regulator-name = "vdd_phyio_1v8";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-boot-on;
+ regulator-always-on;
+ };
+
+ ldoa1: ldo1 {
+ regulator-name = "vdd1_lpddr4_1v8";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-boot-on;
+ regulator-always-on;
+ };
+
+ ldoa2: ldo2 {
+ regulator-name = "vdd_mcuio_1v8";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-boot-on;
+ regulator-always-on;
+ };
+
+ ldoa3: ldo3 {
+ regulator-name = "vdda_dll_0v8";
+ regulator-min-microvolt = <800000>;
+ regulator-max-microvolt = <800000>;
+ regulator-boot-on;
+ regulator-always-on;
+ };
+
+ ldoa4: ldo4 {
+ regulator-name = "vda_mcu_1v8";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-boot-on;
+ regulator-always-on;
+ };
+ };
+ };
+
+ tps659411: pmic@4c {
+ compatible = "ti,tps6594-q1";
+ reg = <0x4c>;
+ system-power-controller;
+ interrupt-parent = <&wkup_gpio0>;
+ interrupts = <9 IRQ_TYPE_EDGE_FALLING>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ buck1234-supply = <&vsys_3v3>;
+ buck5-supply = <&vsys_3v3>;
+ ldo1-supply = <&vsys_3v3>;
+ ldo2-supply = <&vsys_3v3>;
+ ldo3-supply = <&vsys_3v3>;
+ ldo4-supply = <&vsys_3v3>;
+
+ regulators {
+ buckb1234: buck1234 {
+ regulator-name = "vdd_core_0v8";
+ regulator-min-microvolt = <800000>;
+ regulator-max-microvolt = <800000>;
+ regulator-boot-on;
+ regulator-always-on;
+ };
+
+ buckb5: buck5 {
+ regulator-name = "vdd_ram_0v85";
+ regulator-min-microvolt = <850000>;
+ regulator-max-microvolt = <850000>;
+ regulator-boot-on;
+ regulator-always-on;
+ };
+
+ ldob1: ldo1 {
+ regulator-name = "vdd_sd_dv";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-boot-on;
+ regulator-always-on;
+ };
+
+ ldob2: ldo2 {
+ regulator-name = "vdd_usb_3v3";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-boot-on;
+ regulator-always-on;
+ };
+
+ ldob3: ldo3 {
+ regulator-name = "vdd_io_1v8";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-boot-on;
+ regulator-always-on;
+ };
+
+ ldob4: ldo4 {
+ regulator-name = "vda_pll_1v8";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-boot-on;
+ regulator-always-on;
+ };
+ };
+ };
};
&mcu_uart0 {
diff --git a/dts/upstream/src/arm64/ti/k3-j721e-som-p0.dtsi b/dts/upstream/src/arm64/ti/k3-j721e-som-p0.dtsi
index 7f0686c2..a75611e 100644
--- a/dts/upstream/src/arm64/ti/k3-j721e-som-p0.dtsi
+++ b/dts/upstream/src/arm64/ti/k3-j721e-som-p0.dtsi
@@ -152,6 +152,12 @@
>;
};
+ pmic_irq_pins_default: pmic-irq-default-pins {
+ pinctrl-single,pins = <
+ J721E_WKUP_IOPAD(0x0d4, PIN_INPUT, 7) /* (G26) WKUP_GPIO0_9 */
+ >;
+ };
+
mcu_fss0_ospi0_pins_default: mcu-fss0-ospi0-default-pins {
pinctrl-single,pins = <
J721E_WKUP_IOPAD(0x0000, PIN_OUTPUT, 0) /* MCU_OSPI0_CLK */
@@ -199,6 +205,160 @@
compatible = "atmel,24c256";
reg = <0x50>;
};
+
+ tps659413: pmic@48 {
+ compatible = "ti,tps6594-q1";
+ reg = <0x48>;
+ system-power-controller;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pmic_irq_pins_default>;
+ interrupt-parent = <&wkup_gpio0>;
+ interrupts = <9 IRQ_TYPE_EDGE_FALLING>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ ti,primary-pmic;
+ buck12-supply = <&vsys_3v3>;
+ buck3-supply = <&vsys_3v3>;
+ buck4-supply = <&vsys_3v3>;
+ buck5-supply = <&vsys_3v3>;
+ ldo1-supply = <&vsys_3v3>;
+ ldo2-supply = <&vsys_3v3>;
+ ldo3-supply = <&vsys_3v3>;
+ ldo4-supply = <&vsys_3v3>;
+
+ regulators {
+ bucka12: buck12 {
+ regulator-name = "vdd_cpu_avs";
+ regulator-min-microvolt = <600000>;
+ regulator-max-microvolt = <900000>;
+ regulator-boot-on;
+ regulator-always-on;
+ bootph-pre-ram;
+ };
+
+ bucka3: buck3 {
+ regulator-name = "vdd_mcu_0v85";
+ regulator-min-microvolt = <850000>;
+ regulator-max-microvolt = <850000>;
+ regulator-boot-on;
+ regulator-always-on;
+ };
+
+ bucka4: buck4 {
+ regulator-name = "vdd_ddr_1v1";
+ regulator-min-microvolt = <1100000>;
+ regulator-max-microvolt = <1100000>;
+ regulator-boot-on;
+ regulator-always-on;
+ };
+
+ bucka5: buck5 {
+ regulator-name = "vdd_phyio_1v8";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-boot-on;
+ regulator-always-on;
+ };
+
+ ldoa1: ldo1 {
+ regulator-name = "vdd1_lpddr4_1v8";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-boot-on;
+ regulator-always-on;
+ };
+
+ ldoa2: ldo2 {
+ regulator-name = "vdd_mcuio_1v8";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-boot-on;
+ regulator-always-on;
+ };
+
+ ldoa3: ldo3 {
+ regulator-name = "vdda_dll_0v8";
+ regulator-min-microvolt = <800000>;
+ regulator-max-microvolt = <800000>;
+ regulator-boot-on;
+ regulator-always-on;
+ };
+
+ ldoa4: ldo4 {
+ regulator-name = "vda_mcu_1v8";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-boot-on;
+ regulator-always-on;
+ };
+ };
+ };
+
+ tps659411: pmic@4c {
+ compatible = "ti,tps6594-q1";
+ reg = <0x4c>;
+ system-power-controller;
+ interrupt-parent = <&wkup_gpio0>;
+ interrupts = <9 IRQ_TYPE_EDGE_FALLING>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ buck1234-supply = <&vsys_3v3>;
+ buck5-supply = <&vsys_3v3>;
+ ldo1-supply = <&vsys_3v3>;
+ ldo2-supply = <&vsys_3v3>;
+ ldo3-supply = <&vsys_3v3>;
+ ldo4-supply = <&vsys_3v3>;
+
+ regulators {
+ buckb1234: buck1234 {
+ regulator-name = "vdd_core_0v8";
+ regulator-min-microvolt = <800000>;
+ regulator-max-microvolt = <800000>;
+ regulator-boot-on;
+ regulator-always-on;
+ };
+
+ buckb5: buck5 {
+ regulator-name = "vdd_ram_0v85";
+ regulator-min-microvolt = <850000>;
+ regulator-max-microvolt = <850000>;
+ regulator-boot-on;
+ regulator-always-on;
+ };
+
+ ldob1: ldo1 {
+ regulator-name = "vdd_sd_dv";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-boot-on;
+ regulator-always-on;
+ };
+
+ ldob2: ldo2 {
+ regulator-name = "vdd_usb_3v3";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-boot-on;
+ regulator-always-on;
+ };
+
+ ldob3: ldo3 {
+ regulator-name = "vdd_io_1v8";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-boot-on;
+ regulator-always-on;
+ };
+
+ ldob4: ldo4 {
+ regulator-name = "vda_pll_1v8";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-boot-on;
+ regulator-always-on;
+ };
+ };
+ };
};
&ospi0 {
diff --git a/dts/upstream/src/arm64/ti/k3-j721s2-evm-pcie1-ep.dtso b/dts/upstream/src/arm64/ti/k3-j721s2-evm-pcie1-ep.dtso
new file mode 100644
index 0000000..43568eb
--- /dev/null
+++ b/dts/upstream/src/arm64/ti/k3-j721s2-evm-pcie1-ep.dtso
@@ -0,0 +1,53 @@
+// SPDX-License-Identifier: GPL-2.0
+/**
+ * DT Overlay for enabling PCIE1 instance in Endpoint Configuration with the
+ * J7 common processor board.
+ *
+ * J7 Common Processor Board Product Link: https://www.ti.com/tool/J721EXCPXEVM
+ *
+ * Copyright (C) 2023 Texas Instruments Incorporated - https://www.ti.com/
+ */
+
+/dts-v1/;
+/plugin/;
+
+#include <dt-bindings/interrupt-controller/arm-gic.h>
+#include <dt-bindings/soc/ti,sci_pm_domain.h>
+
+#include "k3-pinctrl.h"
+
+/*
+ * Since Root Complex and Endpoint modes are mutually exclusive
+ * disable Root Complex mode.
+ */
+&pcie1_rc {
+ status = "disabled";
+};
+
+&cbass_main {
+ #address-cells = <2>;
+ #size-cells = <2>;
+ interrupt-parent = <&gic500>;
+
+ pcie1_ep: pcie-ep@2910000 {
+ compatible = "ti,j7200-pcie-ep", "ti,j721e-pcie-ep";
+ reg = <0x00 0x02910000 0x00 0x1000>,
+ <0x00 0x02917000 0x00 0x400>,
+ <0x00 0x0d800000 0x00 0x00800000>,
+ <0x00 0x18000000 0x00 0x08000000>;
+ reg-names = "intd_cfg", "user_cfg", "reg", "mem";
+ interrupt-names = "link_state";
+ interrupts = <GIC_SPI 330 IRQ_TYPE_EDGE_RISING>;
+ ti,syscon-pcie-ctrl = <&scm_conf 0x074>;
+ max-link-speed = <3>;
+ num-lanes = <1>;
+ power-domains = <&k3_pds 276 TI_SCI_PD_EXCLUSIVE>;
+ clocks = <&k3_clks 276 41>;
+ clock-names = "fck";
+ max-functions = /bits/ 8 <6>;
+ max-virtual-functions = /bits/ 8 <4 4 4 4 0 0>;
+ dma-coherent;
+ phys = <&serdes0_pcie_link>;
+ phy-names = "pcie-phy";
+ };
+};
diff --git a/dts/upstream/src/arm64/ti/k3-j721s2-main.dtsi b/dts/upstream/src/arm64/ti/k3-j721s2-main.dtsi
index b03731b..ea7f2b2 100644
--- a/dts/upstream/src/arm64/ti/k3-j721s2-main.dtsi
+++ b/dts/upstream/src/arm64/ti/k3-j721s2-main.dtsi
@@ -766,6 +766,7 @@
ti,itap-del-sel-sd-hs = <0x0>;
ti,itap-del-sel-sdr12 = <0x0>;
ti,itap-del-sel-sdr25 = <0x0>;
+ ti,itap-del-sel-ddr50 = <0x2>;
ti,clkbuf-sel = <0x7>;
ti,trm-icp = <0x8>;
dma-coherent;
@@ -1086,8 +1087,12 @@
compatible = "ti,j721e-navss-main-udmap";
reg = <0x0 0x31150000 0x0 0x100>,
<0x0 0x34000000 0x0 0x80000>,
- <0x0 0x35000000 0x0 0x200000>;
- reg-names = "gcfg", "rchanrt", "tchanrt";
+ <0x0 0x35000000 0x0 0x200000>,
+ <0x0 0x30b00000 0x0 0x20000>,
+ <0x0 0x30c00000 0x0 0x8000>,
+ <0x0 0x30d00000 0x0 0x4000>;
+ reg-names = "gcfg", "rchanrt", "tchanrt",
+ "tchan", "rchan", "rflow";
msi-parent = <&main_udmass_inta>;
#dma-cells = <1>;
diff --git a/dts/upstream/src/arm64/ti/k3-j721s2-mcu-wakeup.dtsi b/dts/upstream/src/arm64/ti/k3-j721s2-mcu-wakeup.dtsi
index 7254f3b..80aa33c 100644
--- a/dts/upstream/src/arm64/ti/k3-j721s2-mcu-wakeup.dtsi
+++ b/dts/upstream/src/arm64/ti/k3-j721s2-mcu-wakeup.dtsi
@@ -34,9 +34,16 @@
};
};
- chipid@43000014 {
- compatible = "ti,am654-chipid";
- reg = <0x00 0x43000014 0x00 0x4>;
+ wkup_conf: bus@43000000 {
+ compatible = "simple-bus";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0x0 0x00 0x43000000 0x20000>;
+
+ chipid: chipid@14 {
+ compatible = "ti,am654-chipid";
+ reg = <0x14 0x4>;
+ };
};
secure_proxy_sa3: mailbox@43600000 {
@@ -471,8 +478,12 @@
compatible = "ti,j721e-navss-mcu-udmap";
reg = <0x0 0x285c0000 0x0 0x100>,
<0x0 0x2a800000 0x0 0x40000>,
- <0x0 0x2aa00000 0x0 0x40000>;
- reg-names = "gcfg", "rchanrt", "tchanrt";
+ <0x0 0x2aa00000 0x0 0x40000>,
+ <0x0 0x284a0000 0x0 0x4000>,
+ <0x0 0x284c0000 0x0 0x4000>,
+ <0x0 0x28400000 0x0 0x2000>;
+ reg-names = "gcfg", "rchanrt", "tchanrt",
+ "tchan", "rchan", "rflow";
msi-parent = <&main_udmass_inta>;
#dma-cells = <1>;
diff --git a/dts/upstream/src/arm64/ti/k3-j721s2-som-p0.dtsi b/dts/upstream/src/arm64/ti/k3-j721s2-som-p0.dtsi
index dcad372..da3237b 100644
--- a/dts/upstream/src/arm64/ti/k3-j721s2-som-p0.dtsi
+++ b/dts/upstream/src/arm64/ti/k3-j721s2-som-p0.dtsi
@@ -172,6 +172,15 @@
};
};
+&wkup_pmx1 {
+ pmic_irq_pins_default: pmic-irq-default-pins {
+ pinctrl-single,pins = <
+ /* (C21) MCU_OSPI1_CSn1.WKUP_GPIO0_39 */
+ J721S2_WKUP_IOPAD(0x028, PIN_INPUT, 7)
+ >;
+ };
+};
+
&wkup_pmx2 {
wkup_i2c0_pins_default: wkup-i2c0-default-pins {
pinctrl-single,pins = <
@@ -208,6 +217,190 @@
compatible = "atmel,24c256";
reg = <0x50>;
};
+
+ tps659411: pmic@48 {
+ compatible = "ti,tps6594-q1";
+ reg = <0x48>;
+ system-power-controller;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pmic_irq_pins_default>;
+ interrupt-parent = <&wkup_gpio0>;
+ interrupts = <39 IRQ_TYPE_EDGE_FALLING>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ ti,primary-pmic;
+ buck1234-supply = <&vsys_3v3>;
+ buck5-supply = <&vsys_3v3>;
+ ldo1-supply = <&vsys_3v3>;
+ ldo2-supply = <&vsys_3v3>;
+ ldo3-supply = <&vsys_3v3>;
+ ldo4-supply = <&vsys_3v3>;
+
+ regulators {
+ bucka1234: buck1234 {
+ regulator-name = "vdd_cpu_avs";
+ regulator-min-microvolt = <600000>;
+ regulator-max-microvolt = <900000>;
+ regulator-boot-on;
+ regulator-always-on;
+ bootph-pre-ram;
+ };
+
+ bucka5: buck5 {
+ regulator-name = "vdd_mcu_0v85";
+ regulator-min-microvolt = <850000>;
+ regulator-max-microvolt = <850000>;
+ regulator-boot-on;
+ regulator-always-on;
+ };
+
+ ldoa1: ldo1 {
+ regulator-name = "vdd_mcuwk_0v8";
+ regulator-min-microvolt = <800000>;
+ regulator-max-microvolt = <800000>;
+ regulator-boot-on;
+ regulator-always-on;
+ };
+
+ ldoa2: ldo2 {
+ regulator-name = "vdd_mcu_gpioret_3v3";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-boot-on;
+ regulator-always-on;
+ };
+
+ ldoa3: ldo3 {
+ regulator-name = "vdd_mcuio_1v8";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-boot-on;
+ regulator-always-on;
+ };
+
+ ldoa4: ldo4 {
+ regulator-name = "vda_mcu_1v8";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-boot-on;
+ regulator-always-on;
+ };
+ };
+ };
+
+ tps659414: pmic@4c {
+ compatible = "ti,tps6594-q1";
+ reg = <0x4c>;
+ system-power-controller;
+ interrupt-parent = <&wkup_gpio0>;
+ interrupts = <39 IRQ_TYPE_EDGE_FALLING>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ buck1-supply = <&vsys_3v3>;
+ buck2-supply = <&vsys_3v3>;
+ buck3-supply = <&vsys_3v3>;
+ buck4-supply = <&vsys_3v3>;
+ buck5-supply = <&vsys_3v3>;
+ ldo1-supply = <&vsys_3v3>;
+ ldo2-supply = <&vsys_3v3>;
+ ldo3-supply = <&vsys_3v3>;
+ ldo4-supply = <&vsys_3v3>;
+
+ regulators {
+ buckb1: buck1 {
+ regulator-name = "vdd_io_1v8_reg";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-always-on;
+ regulator-boot-on;
+ };
+
+ buckb2: buck2 {
+ regulator-name = "vdd_fpd_1v1";
+ regulator-min-microvolt = <1100000>;
+ regulator-max-microvolt = <1100000>;
+ regulator-boot-on;
+ regulator-always-on;
+ };
+
+ buckb3: buck3 {
+ regulator-name = "vdd_phy_1v8";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-boot-on;
+ regulator-always-on;
+ };
+
+ buckb4: buck4 {
+ regulator-name = "vdd_ddr_1v1";
+ regulator-min-microvolt = <1100000>;
+ regulator-max-microvolt = <1100000>;
+ regulator-boot-on;
+ regulator-always-on;
+ };
+
+ buckb5: buck5 {
+ regulator-name = "vdd_ram_0v85";
+ regulator-min-microvolt = <850000>;
+ regulator-max-microvolt = <850000>;
+ regulator-boot-on;
+ regulator-always-on;
+ };
+
+ ldob1: ldo1 {
+ regulator-name = "vdd_wk_0v8";
+ regulator-min-microvolt = <800000>;
+ regulator-max-microvolt = <800000>;
+ regulator-boot-on;
+ regulator-always-on;
+ };
+
+ ldob2: ldo2 {
+ regulator-name = "vdd_gpioret_3v3";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-boot-on;
+ regulator-always-on;
+ };
+
+ ldob3: ldo3 {
+ regulator-name = "vda_dll_0v8";
+ regulator-min-microvolt = <800000>;
+ regulator-max-microvolt = <800000>;
+ regulator-boot-on;
+ regulator-always-on;
+ };
+
+ ldob4: ldo4 {
+ regulator-name = "vda_pll_1v8";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-boot-on;
+ regulator-always-on;
+ };
+ };
+ };
+
+ lp876411: pmic@58 {
+ compatible = "ti,lp8764-q1";
+ reg = <0x58>;
+ system-power-controller;
+ interrupt-parent = <&wkup_gpio0>;
+ interrupts = <39 IRQ_TYPE_EDGE_FALLING>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ buck1234-supply = <&vsys_3v3>;
+
+ regulators {
+ buckc1234: buck1234 {
+ regulator-name = "vdd_core_0v8";
+ regulator-min-microvolt = <800000>;
+ regulator-max-microvolt = <800000>;
+ regulator-boot-on;
+ regulator-always-on;
+ };
+ };
+ };
};
&main_i2c0 {
diff --git a/dts/upstream/src/arm64/ti/k3-j784s4-evm.dts b/dts/upstream/src/arm64/ti/k3-j784s4-evm.dts
index f1f4c86..f34b92a 100644
--- a/dts/upstream/src/arm64/ti/k3-j784s4-evm.dts
+++ b/dts/upstream/src/arm64/ti/k3-j784s4-evm.dts
@@ -273,6 +273,10 @@
};
};
+&wkup_gpio0 {
+ status = "okay";
+};
+
&main_pmx0 {
bootph-all;
main_uart8_pins_default: main-uart8-default-pins {
@@ -407,6 +411,17 @@
};
};
+&wkup_pmx1 {
+ status = "okay";
+
+ pmic_irq_pins_default: pmic-irq-default-pins {
+ pinctrl-single,pins = <
+ /* (G33) MCU_OSPI1_CSn1.WKUP_GPIO0_39 */
+ J784S4_WKUP_IOPAD(0x028, PIN_INPUT, 7)
+ >;
+ };
+};
+
&wkup_pmx0 {
bootph-all;
mcu_fss0_ospi0_pins_default: mcu-fss0-ospi0-default-pins {
@@ -471,6 +486,93 @@
compatible = "atmel,24c256";
reg = <0x50>;
};
+
+ tps659413: pmic@48 {
+ compatible = "ti,tps6594-q1";
+ reg = <0x48>;
+ system-power-controller;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pmic_irq_pins_default>;
+ interrupt-parent = <&wkup_gpio0>;
+ interrupts = <39 IRQ_TYPE_EDGE_FALLING>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ ti,primary-pmic;
+ buck12-supply = <&vsys_3v3>;
+ buck3-supply = <&vsys_3v3>;
+ buck4-supply = <&vsys_3v3>;
+ buck5-supply = <&vsys_3v3>;
+ ldo1-supply = <&vsys_3v3>;
+ ldo2-supply = <&vsys_3v3>;
+ ldo3-supply = <&vsys_3v3>;
+ ldo4-supply = <&vsys_3v3>;
+
+ regulators {
+ bucka12: buck12 {
+ regulator-name = "vdd_ddr_1v1";
+ regulator-min-microvolt = <1100000>;
+ regulator-max-microvolt = <1100000>;
+ regulator-boot-on;
+ regulator-always-on;
+ };
+
+ bucka3: buck3 {
+ regulator-name = "vdd_ram_0v85";
+ regulator-min-microvolt = <850000>;
+ regulator-max-microvolt = <850000>;
+ regulator-boot-on;
+ regulator-always-on;
+ };
+
+ bucka4: buck4 {
+ regulator-name = "vdd_io_1v8";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-boot-on;
+ regulator-always-on;
+ };
+
+ bucka5: buck5 {
+ regulator-name = "vdd_mcu_0v85";
+ regulator-min-microvolt = <850000>;
+ regulator-max-microvolt = <850000>;
+ regulator-boot-on;
+ regulator-always-on;
+ };
+
+ ldoa1: ldo1 {
+ regulator-name = "vdd_mcuio_1v8";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-boot-on;
+ regulator-always-on;
+ };
+
+ ldoa2: ldo2 {
+ regulator-name = "vdd_mcuio_3v3";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-boot-on;
+ regulator-always-on;
+ };
+
+ ldoa3: ldo3 {
+ regulator-name = "vds_dll_0v8";
+ regulator-min-microvolt = <800000>;
+ regulator-max-microvolt = <800000>;
+ regulator-boot-on;
+ regulator-always-on;
+ };
+
+ ldoa4: ldo4 {
+ regulator-name = "vda_mcu_1v8";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-boot-on;
+ regulator-always-on;
+ };
+ };
+ };
};
&mcu_uart0 {
diff --git a/dts/upstream/src/arm64/ti/k3-j784s4-main.dtsi b/dts/upstream/src/arm64/ti/k3-j784s4-main.dtsi
index d89bcdd..f2b720e 100644
--- a/dts/upstream/src/arm64/ti/k3-j784s4-main.dtsi
+++ b/dts/upstream/src/arm64/ti/k3-j784s4-main.dtsi
@@ -712,6 +712,7 @@
ti,itap-del-sel-sd-hs = <0x0>;
ti,itap-del-sel-sdr12 = <0x0>;
ti,itap-del-sel-sdr25 = <0x0>;
+ ti,itap-del-sel-ddr50 = <0x2>;
ti,clkbuf-sel = <0x7>;
ti,trm-icp = <0x8>;
dma-coherent;
@@ -1188,8 +1189,12 @@
compatible = "ti,j721e-navss-main-udmap";
reg = <0x00 0x31150000 0x00 0x100>,
<0x00 0x34000000 0x00 0x80000>,
- <0x00 0x35000000 0x00 0x200000>;
- reg-names = "gcfg", "rchanrt", "tchanrt";
+ <0x00 0x35000000 0x00 0x200000>,
+ <0x00 0x30b00000 0x00 0x20000>,
+ <0x00 0x30c00000 0x00 0x8000>,
+ <0x00 0x30d00000 0x00 0x4000>;
+ reg-names = "gcfg", "rchanrt", "tchanrt",
+ "tchan", "rchan", "rflow";
msi-parent = <&main_udmass_inta>;
#dma-cells = <1>;
diff --git a/dts/upstream/src/arm64/ti/k3-j784s4-mcu-wakeup.dtsi b/dts/upstream/src/arm64/ti/k3-j784s4-mcu-wakeup.dtsi
index adb5ea6..3902a92 100644
--- a/dts/upstream/src/arm64/ti/k3-j784s4-mcu-wakeup.dtsi
+++ b/dts/upstream/src/arm64/ti/k3-j784s4-mcu-wakeup.dtsi
@@ -38,10 +38,18 @@
};
};
- chipid@43000014 {
+ wkup_conf: bus@43000000 {
bootph-all;
- compatible = "ti,am654-chipid";
- reg = <0x00 0x43000014 0x00 0x4>;
+ compatible = "simple-bus";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0x0 0x00 0x43000000 0x20000>;
+
+ chipid: chipid@14 {
+ bootph-all;
+ compatible = "ti,am654-chipid";
+ reg = <0x14 0x4>;
+ };
};
secure_proxy_sa3: mailbox@43600000 {
@@ -478,8 +486,12 @@
compatible = "ti,j721e-navss-mcu-udmap";
reg = <0x00 0x285c0000 0x00 0x100>,
<0x00 0x2a800000 0x00 0x40000>,
- <0x00 0x2aa00000 0x00 0x40000>;
- reg-names = "gcfg", "rchanrt", "tchanrt";
+ <0x00 0x2aa00000 0x00 0x40000>,
+ <0x00 0x284a0000 0x00 0x4000>,
+ <0x00 0x284c0000 0x00 0x4000>,
+ <0x00 0x28400000 0x00 0x2000>;
+ reg-names = "gcfg", "rchanrt", "tchanrt",
+ "tchan", "rchan", "rflow";
msi-parent = <&main_udmass_inta>;
#dma-cells = <1>;
diff --git a/dts/upstream/src/arm64/xilinx/zynqmp-sck-kv-g-revA.dtso b/dts/upstream/src/arm64/xilinx/zynqmp-sck-kv-g-revA.dtso
index ae1b9b2..92f4190 100644
--- a/dts/upstream/src/arm64/xilinx/zynqmp-sck-kv-g-revA.dtso
+++ b/dts/upstream/src/arm64/xilinx/zynqmp-sck-kv-g-revA.dtso
@@ -21,57 +21,57 @@
/dts-v1/;
/plugin/;
-&i2c1 { /* I2C_SCK C23/C24 - MIO from SOM */
- #address-cells = <1>;
- #size-cells = <0>;
- pinctrl-names = "default", "gpio";
- pinctrl-0 = <&pinctrl_i2c1_default>;
- pinctrl-1 = <&pinctrl_i2c1_gpio>;
- scl-gpios = <&gpio 24 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
- sda-gpios = <&gpio 25 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
-
- /* u14 - 0x40 - ina260 */
- /* u27 - 0xe0 - STDP4320 DP/HDMI splitter */
-};
-
-&amba {
- si5332_0: si5332_0 { /* u17 */
+&{/} {
+ si5332_0: si5332-0 { /* u17 */
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <125000000>;
};
- si5332_1: si5332_1 { /* u17 */
+ si5332_1: si5332-1 { /* u17 */
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <25000000>;
};
- si5332_2: si5332_2 { /* u17 */
+ si5332_2: si5332-2 { /* u17 */
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <48000000>;
};
- si5332_3: si5332_3 { /* u17 */
+ si5332_3: si5332-3 { /* u17 */
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <24000000>;
};
- si5332_4: si5332_4 { /* u17 */
+ si5332_4: si5332-4 { /* u17 */
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <26000000>;
};
- si5332_5: si5332_5 { /* u17 */
+ si5332_5: si5332-5 { /* u17 */
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <27000000>;
};
};
+&i2c1 { /* I2C_SCK C23/C24 - MIO from SOM */
+ #address-cells = <1>;
+ #size-cells = <0>;
+ pinctrl-names = "default", "gpio";
+ pinctrl-0 = <&pinctrl_i2c1_default>;
+ pinctrl-1 = <&pinctrl_i2c1_gpio>;
+ scl-gpios = <&gpio 24 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
+ sda-gpios = <&gpio 25 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
+
+ /* u14 - 0x40 - ina260 */
+ /* u27 - 0xe0 - STDP4320 DP/HDMI splitter */
+};
+
/* DP/USB 3.0 and SATA */
&psgtr {
status = "okay";
diff --git a/dts/upstream/src/arm64/xilinx/zynqmp-sck-kv-g-revB.dtso b/dts/upstream/src/arm64/xilinx/zynqmp-sck-kv-g-revB.dtso
index b59e48b..f88b71f 100644
--- a/dts/upstream/src/arm64/xilinx/zynqmp-sck-kv-g-revB.dtso
+++ b/dts/upstream/src/arm64/xilinx/zynqmp-sck-kv-g-revB.dtso
@@ -16,58 +16,58 @@
/dts-v1/;
/plugin/;
-&i2c1 { /* I2C_SCK C23/C24 - MIO from SOM */
- #address-cells = <1>;
- #size-cells = <0>;
- pinctrl-names = "default", "gpio";
- pinctrl-0 = <&pinctrl_i2c1_default>;
- pinctrl-1 = <&pinctrl_i2c1_gpio>;
- scl-gpios = <&gpio 24 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
- sda-gpios = <&gpio 25 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
-
- /* u14 - 0x40 - ina260 */
- /* u43 - 0x2d - usb5744 */
- /* u27 - 0xe0 - STDP4320 DP/HDMI splitter */
-};
-
-&amba {
- si5332_0: si5332_0 { /* u17 */
+&{/} {
+ si5332_0: si5332-0 { /* u17 */
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <125000000>;
};
- si5332_1: si5332_1 { /* u17 */
+ si5332_1: si5332-1 { /* u17 */
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <25000000>;
};
- si5332_2: si5332_2 { /* u17 */
+ si5332_2: si5332-2 { /* u17 */
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <48000000>;
};
- si5332_3: si5332_3 { /* u17 */
+ si5332_3: si5332-3 { /* u17 */
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <24000000>;
};
- si5332_4: si5332_4 { /* u17 */
+ si5332_4: si5332-4 { /* u17 */
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <26000000>;
};
- si5332_5: si5332_5 { /* u17 */
+ si5332_5: si5332-5 { /* u17 */
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <27000000>;
};
};
+&i2c1 { /* I2C_SCK C23/C24 - MIO from SOM */
+ #address-cells = <1>;
+ #size-cells = <0>;
+ pinctrl-names = "default", "gpio";
+ pinctrl-0 = <&pinctrl_i2c1_default>;
+ pinctrl-1 = <&pinctrl_i2c1_gpio>;
+ scl-gpios = <&gpio 24 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
+ sda-gpios = <&gpio 25 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
+
+ /* u14 - 0x40 - ina260 */
+ /* u43 - 0x2d - usb5744 */
+ /* u27 - 0xe0 - STDP4320 DP/HDMI splitter */
+};
+
/* DP/USB 3.0 */
&psgtr {
status = "okay";
diff --git a/dts/upstream/src/arm64/xilinx/zynqmp-sm-k26-revA.dts b/dts/upstream/src/arm64/xilinx/zynqmp-sm-k26-revA.dts
index c4774a4..5162289 100644
--- a/dts/upstream/src/arm64/xilinx/zynqmp-sm-k26-revA.dts
+++ b/dts/upstream/src/arm64/xilinx/zynqmp-sm-k26-revA.dts
@@ -131,9 +131,7 @@
&qspi { /* MIO 0-5 - U143 */
status = "okay";
spi_flash: flash@0 { /* MT25QU512A */
- compatible = "mt25qu512a", "jedec,spi-nor"; /* 64MB */
- #address-cells = <1>;
- #size-cells = <1>;
+ compatible = "jedec,spi-nor"; /* 64MB */
reg = <0>;
spi-tx-bus-width = <4>;
spi-rx-bus-width = <4>;
@@ -222,9 +220,9 @@
label = "Secure OS Storage";
reg = <0x2280000 0x20000>; /* 128KB */
};
- partition@22A0000 {
+ partition@22a0000 {
label = "User";
- reg = <0x22A0000 0x1d60000>; /* 29.375 MB */
+ reg = <0x22a0000 0x1d60000>; /* 29.375 MB */
};
};
};
diff --git a/dts/upstream/src/arm64/xilinx/zynqmp-zc1751-xm015-dc1.dts b/dts/upstream/src/arm64/xilinx/zynqmp-zc1751-xm015-dc1.dts
index e821d55..7349162 100644
--- a/dts/upstream/src/arm64/xilinx/zynqmp-zc1751-xm015-dc1.dts
+++ b/dts/upstream/src/arm64/xilinx/zynqmp-zc1751-xm015-dc1.dts
@@ -98,8 +98,12 @@
phy-mode = "rgmii-id";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_gem3_default>;
- phy0: ethernet-phy@0 {
- reg = <0>;
+ mdio: mdio {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ phy0: ethernet-phy@0 {
+ reg = <0>;
+ };
};
};
diff --git a/dts/upstream/src/arm64/xilinx/zynqmp-zc1751-xm016-dc2.dts b/dts/upstream/src/arm64/xilinx/zynqmp-zc1751-xm016-dc2.dts
index b59e113..f767708 100644
--- a/dts/upstream/src/arm64/xilinx/zynqmp-zc1751-xm016-dc2.dts
+++ b/dts/upstream/src/arm64/xilinx/zynqmp-zc1751-xm016-dc2.dts
@@ -91,12 +91,16 @@
phy-mode = "rgmii-id";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_gem2_default>;
- phy0: ethernet-phy@5 {
- reg = <5>;
- ti,rx-internal-delay = <0x8>;
- ti,tx-internal-delay = <0xa>;
- ti,fifo-depth = <0x1>;
- ti,dp83867-rxctrl-strap-quirk;
+ mdio: mdio {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ phy0: ethernet-phy@5 {
+ reg = <5>;
+ ti,rx-internal-delay = <0x8>;
+ ti,tx-internal-delay = <0xa>;
+ ti,fifo-depth = <0x1>;
+ ti,dp83867-rxctrl-strap-quirk;
+ };
};
};
diff --git a/dts/upstream/src/arm64/xilinx/zynqmp-zc1751-xm017-dc3.dts b/dts/upstream/src/arm64/xilinx/zynqmp-zc1751-xm017-dc3.dts
index 38b0a31..f553b31 100644
--- a/dts/upstream/src/arm64/xilinx/zynqmp-zc1751-xm017-dc3.dts
+++ b/dts/upstream/src/arm64/xilinx/zynqmp-zc1751-xm017-dc3.dts
@@ -88,8 +88,12 @@
status = "okay";
phy-handle = <&phy0>;
phy-mode = "rgmii-id";
- phy0: ethernet-phy@0 { /* VSC8211 */
- reg = <0>;
+ mdio: mdio {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ phy0: ethernet-phy@0 { /* VSC8211 */
+ reg = <0>;
+ };
};
};
diff --git a/dts/upstream/src/arm64/xilinx/zynqmp-zc1751-xm018-dc4.dts b/dts/upstream/src/arm64/xilinx/zynqmp-zc1751-xm018-dc4.dts
index 6636e76..6ec1d98 100644
--- a/dts/upstream/src/arm64/xilinx/zynqmp-zc1751-xm018-dc4.dts
+++ b/dts/upstream/src/arm64/xilinx/zynqmp-zc1751-xm018-dc4.dts
@@ -116,17 +116,21 @@
status = "okay";
phy-mode = "rgmii-id";
phy-handle = <ðernet_phy0>;
- ethernet_phy0: ethernet-phy@0 { /* Marvell 88e1512 */
- reg = <0>;
- };
- ethernet_phy7: ethernet-phy@7 { /* Vitesse VSC8211 */
- reg = <7>;
- };
- ethernet_phy3: ethernet-phy@3 { /* Realtek RTL8211DN */
- reg = <3>;
- };
- ethernet_phy8: ethernet-phy@8 { /* Vitesse VSC8211 */
- reg = <8>;
+ mdio: mdio {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ ethernet_phy0: ethernet-phy@0 { /* Marvell 88e1512 */
+ reg = <0>;
+ };
+ ethernet_phy7: ethernet-phy@7 { /* Vitesse VSC8211 */
+ reg = <7>;
+ };
+ ethernet_phy3: ethernet-phy@3 { /* Realtek RTL8211DN */
+ reg = <3>;
+ };
+ ethernet_phy8: ethernet-phy@8 { /* Vitesse VSC8211 */
+ reg = <8>;
+ };
};
};
diff --git a/dts/upstream/src/arm64/xilinx/zynqmp-zc1751-xm019-dc5.dts b/dts/upstream/src/arm64/xilinx/zynqmp-zc1751-xm019-dc5.dts
index 0d2ea9c..b1857e1 100644
--- a/dts/upstream/src/arm64/xilinx/zynqmp-zc1751-xm019-dc5.dts
+++ b/dts/upstream/src/arm64/xilinx/zynqmp-zc1751-xm019-dc5.dts
@@ -77,8 +77,12 @@
phy-mode = "rgmii-id";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_gem1_default>;
- phy0: ethernet-phy@0 {
- reg = <0>;
+ mdio: mdio {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ phy0: ethernet-phy@0 {
+ reg = <0>;
+ };
};
};
diff --git a/dts/upstream/src/arm64/xilinx/zynqmp-zcu100-revC.dts b/dts/upstream/src/arm64/xilinx/zynqmp-zcu100-revC.dts
index d0091d3..52f998c 100644
--- a/dts/upstream/src/arm64/xilinx/zynqmp-zcu100-revC.dts
+++ b/dts/upstream/src/arm64/xilinx/zynqmp-zcu100-revC.dts
@@ -123,13 +123,13 @@
io-channels = <&u35 0>, <&u35 1>, <&u35 2>, <&u35 3>;
};
- si5335_0: si5335_0 { /* clk0_usb - u23 */
+ si5335_0: si5335-0 { /* clk0_usb - u23 */
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <26000000>;
};
- si5335_1: si5335_1 { /* clk1_dp - u23 */
+ si5335_1: si5335-1 { /* clk1_dp - u23 */
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <27000000>;
diff --git a/dts/upstream/src/arm64/xilinx/zynqmp.dtsi b/dts/upstream/src/arm64/xilinx/zynqmp.dtsi
index b61fc99..eaba466 100644
--- a/dts/upstream/src/arm64/xilinx/zynqmp.dtsi
+++ b/dts/upstream/src/arm64/xilinx/zynqmp.dtsi
@@ -129,7 +129,7 @@
};
};
- zynqmp_ipi: zynqmp_ipi {
+ zynqmp_ipi: zynqmp-ipi {
bootph-all;
compatible = "xlnx,zynqmp-ipi-mailbox";
interrupt-parent = <&gic>;
@@ -141,6 +141,7 @@
ipi_mailbox_pmu1: mailbox@ff9905c0 {
bootph-all;
+ compatible = "xlnx,zynqmp-ipi-dest-mailbox";
reg = <0x0 0xff9905c0 0x0 0x20>,
<0x0 0xff9905e0 0x0 0x20>,
<0x0 0xff990e80 0x0 0x20>,
@@ -194,12 +195,12 @@
mbox-names = "tx", "rx";
};
- nvmem_firmware {
+ nvmem-firmware {
compatible = "xlnx,zynqmp-nvmem-fw";
#address-cells = <1>;
#size-cells = <1>;
- soc_revision: soc_revision@0 {
+ soc_revision: soc-revision@0 {
reg = <0x0 0x4>;
};
};
@@ -584,8 +585,6 @@
<GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>;
reg = <0x0 0xff0b0000 0x0 0x1000>;
clock-names = "pclk", "hclk", "tx_clk", "rx_clk", "tsu_clk";
- #address-cells = <1>;
- #size-cells = <0>;
iommus = <&smmu 0x874>;
power-domains = <&zynqmp_firmware PD_ETH_0>;
resets = <&zynqmp_reset ZYNQMP_RESET_GEM0>;
@@ -600,8 +599,6 @@
<GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>;
reg = <0x0 0xff0c0000 0x0 0x1000>;
clock-names = "pclk", "hclk", "tx_clk", "rx_clk", "tsu_clk";
- #address-cells = <1>;
- #size-cells = <0>;
iommus = <&smmu 0x875>;
power-domains = <&zynqmp_firmware PD_ETH_1>;
resets = <&zynqmp_reset ZYNQMP_RESET_GEM1>;
@@ -616,8 +613,6 @@
<GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>;
reg = <0x0 0xff0d0000 0x0 0x1000>;
clock-names = "pclk", "hclk", "tx_clk", "rx_clk", "tsu_clk";
- #address-cells = <1>;
- #size-cells = <0>;
iommus = <&smmu 0x876>;
power-domains = <&zynqmp_firmware PD_ETH_2>;
resets = <&zynqmp_reset ZYNQMP_RESET_GEM2>;
@@ -632,8 +627,6 @@
<GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>;
reg = <0x0 0xff0e0000 0x0 0x1000>;
clock-names = "pclk", "hclk", "tx_clk", "rx_clk", "tsu_clk";
- #address-cells = <1>;
- #size-cells = <0>;
iommus = <&smmu 0x877>;
power-domains = <&zynqmp_firmware PD_ETH_3>;
resets = <&zynqmp_reset ZYNQMP_RESET_GEM3>;
diff --git a/dts/upstream/src/loongarch/loongson-2k0500-ref.dts b/dts/upstream/src/loongarch/loongson-2k0500-ref.dts
new file mode 100644
index 0000000..8aefb0c
--- /dev/null
+++ b/dts/upstream/src/loongarch/loongson-2k0500-ref.dts
@@ -0,0 +1,88 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (C) 2023 Loongson Technology Corporation Limited
+ */
+
+/dts-v1/;
+
+#include "loongson-2k0500.dtsi"
+
+/ {
+ compatible = "loongson,ls2k0500-ref", "loongson,ls2k0500";
+ model = "Loongson-2K0500 Reference Board";
+
+ aliases {
+ ethernet0 = &gmac0;
+ ethernet1 = &gmac1;
+ serial0 = &uart0;
+ };
+
+ chosen {
+ stdout-path = "serial0:115200n8";
+ };
+
+ memory@200000 {
+ device_type = "memory";
+ reg = <0x0 0x00200000 0x0 0x0ee00000>,
+ <0x0 0x90000000 0x0 0x60000000>;
+ };
+
+ reserved-memory {
+ #address-cells = <2>;
+ #size-cells = <2>;
+ ranges;
+
+ linux,cma {
+ compatible = "shared-dma-pool";
+ reusable;
+ size = <0x0 0x2000000>;
+ linux,cma-default;
+ };
+ };
+};
+
+&gmac0 {
+ status = "okay";
+
+ phy-mode = "rgmii";
+ bus_id = <0x0>;
+};
+
+&gmac1 {
+ status = "okay";
+
+ phy-mode = "rgmii";
+ bus_id = <0x1>;
+};
+
+&i2c0 {
+ status = "okay";
+
+ #address-cells = <1>;
+ #size-cells = <0>;
+ eeprom@57 {
+ compatible = "atmel,24c16";
+ reg = <0x57>;
+ pagesize = <16>;
+ };
+};
+
+&ehci0 {
+ status = "okay";
+};
+
+&ohci0 {
+ status = "okay";
+};
+
+&sata {
+ status = "okay";
+};
+
+&uart0 {
+ status = "okay";
+};
+
+&rtc0 {
+ status = "okay";
+};
diff --git a/dts/upstream/src/loongarch/loongson-2k0500.dtsi b/dts/upstream/src/loongarch/loongson-2k0500.dtsi
new file mode 100644
index 0000000..444779c
--- /dev/null
+++ b/dts/upstream/src/loongarch/loongson-2k0500.dtsi
@@ -0,0 +1,266 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (C) 2023 Loongson Technology Corporation Limited
+ */
+
+/dts-v1/;
+
+#include <dt-bindings/interrupt-controller/irq.h>
+
+/ {
+ #address-cells = <2>;
+ #size-cells = <2>;
+
+ cpus {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ cpu0: cpu@0 {
+ compatible = "loongson,la264";
+ device_type = "cpu";
+ reg = <0x0>;
+ clocks = <&cpu_clk>;
+ };
+ };
+
+ cpu_clk: cpu-clk {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <500000000>;
+ };
+
+ cpuintc: interrupt-controller {
+ compatible = "loongson,cpu-interrupt-controller";
+ #interrupt-cells = <1>;
+ interrupt-controller;
+ };
+
+ bus@10000000 {
+ compatible = "simple-bus";
+ ranges = <0x0 0x10000000 0x0 0x10000000 0x0 0x10000000>,
+ <0x0 0x02000000 0x0 0x02000000 0x0 0x02000000>,
+ <0x0 0x20000000 0x0 0x20000000 0x0 0x10000000>,
+ <0x0 0x40000000 0x0 0x40000000 0x0 0x40000000>,
+ <0xfe 0x0 0xfe 0x0 0x0 0x40000000>;
+ #address-cells = <2>;
+ #size-cells = <2>;
+
+ isa@16400000 {
+ compatible = "isa";
+ #size-cells = <1>;
+ #address-cells = <2>;
+ ranges = <1 0x0 0x0 0x16400000 0x4000>;
+ };
+
+ liointc0: interrupt-controller@1fe11400 {
+ compatible = "loongson,liointc-2.0";
+ reg = <0x0 0x1fe11400 0x0 0x40>,
+ <0x0 0x1fe11040 0x0 0x8>;
+ reg-names = "main", "isr0";
+
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ interrupt-parent = <&cpuintc>;
+ interrupts = <2>;
+ interrupt-names = "int0";
+
+ loongson,parent_int_map = <0xffffffff>, /* int0 */
+ <0x00000000>, /* int1 */
+ <0x00000000>, /* int2 */
+ <0x00000000>; /* int3 */
+ };
+
+ liointc1: interrupt-controller@1fe11440 {
+ compatible = "loongson,liointc-2.0";
+ reg = <0x0 0x1fe11440 0x0 0x40>,
+ <0x0 0x1fe11048 0x0 0x8>;
+ reg-names = "main", "isr0";
+
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ interrupt-parent = <&cpuintc>;
+ interrupts = <4>;
+ interrupt-names = "int2";
+
+ loongson,parent_int_map = <0x00000000>, /* int0 */
+ <0x00000000>, /* int1 */
+ <0xffffffff>, /* int2 */
+ <0x00000000>; /* int3 */
+ };
+
+ eiointc: interrupt-controller@1fe11600 {
+ compatible = "loongson,ls2k0500-eiointc";
+ reg = <0x0 0x1fe11600 0x0 0xea00>;
+ interrupt-controller;
+ #interrupt-cells = <1>;
+ interrupt-parent = <&cpuintc>;
+ interrupts = <3>;
+ };
+
+ gmac0: ethernet@1f020000 {
+ compatible = "snps,dwmac-3.70a";
+ reg = <0x0 0x1f020000 0x0 0x10000>;
+ interrupt-parent = <&liointc0>;
+ interrupts = <12 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "macirq";
+ status = "disabled";
+ };
+
+ gmac1: ethernet@1f030000 {
+ compatible = "snps,dwmac-3.70a";
+ reg = <0x0 0x1f030000 0x0 0x10000>;
+ interrupt-parent = <&liointc0>;
+ interrupts = <14 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "macirq";
+ status = "disabled";
+ };
+
+ sata: sata@1f040000 {
+ compatible = "snps,spear-ahci";
+ reg = <0x0 0x1f040000 0x0 0x10000>;
+ interrupt-parent = <&eiointc>;
+ interrupts = <75>;
+ status = "disabled";
+ };
+
+ ehci0: usb@1f050000 {
+ compatible = "generic-ehci";
+ reg = <0x0 0x1f050000 0x0 0x8000>;
+ interrupt-parent = <&eiointc>;
+ interrupts = <71>;
+ status = "disabled";
+ };
+
+ ohci0: usb@1f058000 {
+ compatible = "generic-ohci";
+ reg = <0x0 0x1f058000 0x0 0x8000>;
+ interrupt-parent = <&eiointc>;
+ interrupts = <72>;
+ status = "disabled";
+ };
+
+ uart0: serial@1ff40800 {
+ compatible = "ns16550a";
+ reg = <0x0 0x1ff40800 0x0 0x10>;
+ clock-frequency = <100000000>;
+ interrupt-parent = <&eiointc>;
+ interrupts = <2>;
+ no-loopback-test;
+ status = "disabled";
+ };
+
+ i2c0: i2c@1ff48000 {
+ compatible = "loongson,ls2k-i2c";
+ reg = <0x0 0x1ff48000 0x0 0x0800>;
+ interrupt-parent = <&eiointc>;
+ interrupts = <14>;
+ status = "disabled";
+ };
+
+ i2c@1ff48800 {
+ compatible = "loongson,ls2k-i2c";
+ reg = <0x0 0x1ff48800 0x0 0x0800>;
+ interrupt-parent = <&eiointc>;
+ interrupts = <15>;
+ status = "disabled";
+ };
+
+ i2c@1ff49000 {
+ compatible = "loongson,ls2k-i2c";
+ reg = <0x0 0x1ff49000 0x0 0x0800>;
+ interrupt-parent = <&eiointc>;
+ interrupts = <16>;
+ status = "disabled";
+ };
+
+ i2c@1ff49800 {
+ compatible = "loongson,ls2k-i2c";
+ reg = <0x0 0x1ff49800 0x0 0x0800>;
+ interrupt-parent = <&eiointc>;
+ interrupts = <17>;
+ status = "disabled";
+ };
+
+ i2c@1ff4a000 {
+ compatible = "loongson,ls2k-i2c";
+ reg = <0x0 0x1ff4a000 0x0 0x0800>;
+ interrupt-parent = <&eiointc>;
+ interrupts = <18>;
+ status = "disabled";
+ };
+
+ i2c@1ff4a800 {
+ compatible = "loongson,ls2k-i2c";
+ reg = <0x0 0x1ff4a800 0x0 0x0800>;
+ interrupt-parent = <&eiointc>;
+ interrupts = <19>;
+ status = "disabled";
+ };
+
+ pmc: power-management@1ff6c000 {
+ compatible = "loongson,ls2k0500-pmc", "syscon";
+ reg = <0x0 0x1ff6c000 0x0 0x58>;
+ interrupt-parent = <&eiointc>;
+ interrupts = <56>;
+ loongson,suspend-address = <0x0 0x1c000500>;
+
+ syscon-reboot {
+ compatible = "syscon-reboot";
+ offset = <0x30>;
+ mask = <0x1>;
+ };
+
+ syscon-poweroff {
+ compatible = "syscon-poweroff";
+ regmap = <&pmc>;
+ offset = <0x14>;
+ mask = <0x3c00>;
+ value = <0x3c00>;
+ };
+ };
+
+ rtc0: rtc@1ff6c100 {
+ compatible = "loongson,ls2k0500-rtc", "loongson,ls7a-rtc";
+ reg = <0x0 0x1ff6c100 0x0 0x100>;
+ interrupt-parent = <&eiointc>;
+ interrupts = <35>;
+ status = "disabled";
+ };
+
+ pcie@1a000000 {
+ compatible = "loongson,ls2k-pci";
+ reg = <0x0 0x1a000000 0x0 0x02000000>,
+ <0xfe 0x0 0x0 0x20000000>;
+ #address-cells = <3>;
+ #size-cells = <2>;
+ device_type = "pci";
+ bus-range = <0x0 0x5>;
+ ranges = <0x01000000 0x0 0x00004000 0x0 0x16404000 0x0 0x00004000>,
+ <0x02000000 0x0 0x40000000 0x0 0x40000000 0x0 0x40000000>;
+
+ pcie@0,0 {
+ reg = <0x0000 0x0 0x0 0x0 0x0>;
+ #address-cells = <3>;
+ #size-cells = <2>;
+ device_type = "pci";
+ interrupt-parent = <&eiointc>;
+ #interrupt-cells = <1>;
+ interrupt-map-mask = <0x0 0x0 0x0 0x0>;
+ interrupt-map = <0x0 0x0 0x0 0x0 &eiointc 81>;
+ ranges;
+ };
+
+ pcie@1,0 {
+ reg = <0x0800 0x0 0x0 0x0 0x0>;
+ #address-cells = <3>;
+ #size-cells = <2>;
+ device_type = "pci";
+ interrupt-parent = <&eiointc>;
+ #interrupt-cells = <1>;
+ interrupt-map-mask = <0x0 0x0 0x0 0x0>;
+ interrupt-map = <0x0 0x0 0x0 0x0 &eiointc 82>;
+ ranges;
+ };
+ };
+ };
+};
diff --git a/dts/upstream/src/loongarch/loongson-2k1000-ref.dts b/dts/upstream/src/loongarch/loongson-2k1000-ref.dts
new file mode 100644
index 0000000..ed4d324
--- /dev/null
+++ b/dts/upstream/src/loongarch/loongson-2k1000-ref.dts
@@ -0,0 +1,183 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (C) 2023 Loongson Technology Corporation Limited
+ */
+
+/dts-v1/;
+
+#include "loongson-2k1000.dtsi"
+
+/ {
+ compatible = "loongson,ls2k1000-ref", "loongson,ls2k1000";
+ model = "Loongson-2K1000 Reference Board";
+
+ aliases {
+ serial0 = &uart0;
+ };
+
+ chosen {
+ stdout-path = "serial0:115200n8";
+ };
+
+ memory@200000 {
+ device_type = "memory";
+ reg = <0x0 0x00200000 0x0 0x06e00000>,
+ <0x0 0x08000000 0x0 0x07000000>,
+ <0x0 0x90000000 0x1 0xe0000000>;
+ };
+
+ reserved-memory {
+ #address-cells = <2>;
+ #size-cells = <2>;
+ ranges;
+
+ linux,cma {
+ compatible = "shared-dma-pool";
+ reusable;
+ size = <0x0 0x2000000>;
+ linux,cma-default;
+ };
+ };
+};
+
+&gmac0 {
+ status = "okay";
+
+ phy-mode = "rgmii";
+ phy-handle = <&phy0>;
+ mdio {
+ compatible = "snps,dwmac-mdio";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ phy0: ethernet-phy@0 {
+ reg = <0>;
+ };
+ };
+};
+
+&gmac1 {
+ status = "okay";
+
+ phy-mode = "rgmii";
+ phy-handle = <&phy1>;
+ mdio {
+ compatible = "snps,dwmac-mdio";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ phy1: ethernet-phy@1 {
+ reg = <16>;
+ };
+ };
+};
+
+&i2c2 {
+ status = "okay";
+
+ pinctrl-0 = <&i2c0_pins_default>;
+ pinctrl-names = "default";
+
+ #address-cells = <1>;
+ #size-cells = <0>;
+ eeprom@57 {
+ compatible = "atmel,24c16";
+ reg = <0x57>;
+ pagesize = <16>;
+ };
+};
+
+&spi0 {
+ status = "okay";
+
+ #address-cells = <1>;
+ #size-cells = <0>;
+ spidev@0 {
+ compatible = "rohm,dh2228fv";
+ spi-max-frequency = <100000000>;
+ reg = <0>;
+ };
+};
+
+&ehci0 {
+ status = "okay";
+};
+
+&ohci0 {
+ status = "okay";
+};
+
+&sata {
+ status = "okay";
+};
+
+&uart0 {
+ status = "okay";
+};
+
+&clk {
+ status = "okay";
+};
+
+&rtc0 {
+ status = "okay";
+};
+
+&pctrl {
+ status = "okay";
+
+ sdio_pins_default: sdio-pins {
+ sdio-pinmux {
+ groups = "sdio";
+ function = "sdio";
+ };
+ sdio-det-pinmux {
+ groups = "pwm2";
+ function = "gpio";
+ };
+ };
+
+ pwm1_pins_default: pwm1-pins {
+ pinmux {
+ groups = "pwm1";
+ function = "pwm1";
+ };
+ };
+
+ pwm0_pins_default: pwm0-pins {
+ pinmux {
+ groups = "pwm0";
+ function = "pwm0";
+ };
+ };
+
+ i2c1_pins_default: i2c1-pins {
+ pinmux {
+ groups = "i2c1";
+ function = "i2c1";
+ };
+ };
+
+ i2c0_pins_default: i2c0-pins {
+ pinmux {
+ groups = "i2c0";
+ function = "i2c0";
+ };
+ };
+
+ nand_pins_default: nand-pins {
+ pinmux {
+ groups = "nand";
+ function = "nand";
+ };
+ };
+
+ hda_pins_default: hda-pins {
+ grp0-pinmux {
+ groups = "hda";
+ function = "hda";
+ };
+ grp1-pinmux {
+ groups = "i2s";
+ function = "gpio";
+ };
+ };
+};
diff --git a/dts/upstream/src/loongarch/loongson-2k1000.dtsi b/dts/upstream/src/loongarch/loongson-2k1000.dtsi
new file mode 100644
index 0000000..49a70f8
--- /dev/null
+++ b/dts/upstream/src/loongarch/loongson-2k1000.dtsi
@@ -0,0 +1,492 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (C) 2023 Loongson Technology Corporation Limited
+ */
+
+/dts-v1/;
+
+#include <dt-bindings/interrupt-controller/irq.h>
+#include <dt-bindings/clock/loongson,ls2k-clk.h>
+#include <dt-bindings/gpio/gpio.h>
+
+/ {
+ #address-cells = <2>;
+ #size-cells = <2>;
+
+ cpus {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ cpu0: cpu@0 {
+ compatible = "loongson,la264";
+ device_type = "cpu";
+ reg= <0x0>;
+ clocks = <&clk LOONGSON2_NODE_CLK>;
+ };
+
+ cpu1: cpu@1 {
+ compatible = "loongson,la264";
+ device_type = "cpu";
+ reg = <0x1>;
+ clocks = <&clk LOONGSON2_NODE_CLK>;
+ };
+ };
+
+ ref_100m: clock-ref-100m {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <100000000>;
+ clock-output-names = "ref_100m";
+ };
+
+ cpuintc: interrupt-controller {
+ compatible = "loongson,cpu-interrupt-controller";
+ #interrupt-cells = <1>;
+ interrupt-controller;
+ };
+
+ /* i2c of the dvi eeprom edid */
+ i2c-gpio-0 {
+ compatible = "i2c-gpio";
+ scl-gpios = <&gpio0 0 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
+ sda-gpios = <&gpio0 1 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
+ i2c-gpio,delay-us = <5>; /* ~100 kHz */
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+ };
+
+ /* i2c of the eeprom edid */
+ i2c-gpio-1 {
+ compatible = "i2c-gpio";
+ scl-gpios = <&gpio0 33 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
+ sda-gpios = <&gpio0 32 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
+ i2c-gpio,delay-us = <5>; /* ~100 kHz */
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+ };
+
+ thermal-zones {
+ cpu-thermal {
+ polling-delay-passive = <1000>;
+ polling-delay = <5000>;
+ thermal-sensors = <&tsensor 0>;
+
+ trips {
+ cpu_alert: cpu-alert {
+ temperature = <33000>;
+ hysteresis = <2000>;
+ type = "active";
+ };
+
+ cpu_crit: cpu-crit {
+ temperature = <85000>;
+ hysteresis = <5000>;
+ type = "critical";
+ };
+ };
+ };
+ };
+
+ bus@10000000 {
+ compatible = "simple-bus";
+ ranges = <0x0 0x10000000 0x0 0x10000000 0x0 0x10000000>,
+ <0x0 0x02000000 0x0 0x02000000 0x0 0x02000000>,
+ <0x0 0x20000000 0x0 0x20000000 0x0 0x10000000>,
+ <0x0 0x40000000 0x0 0x40000000 0x0 0x40000000>,
+ <0xfe 0x0 0xfe 0x0 0x0 0x40000000>;
+ #address-cells = <2>;
+ #size-cells = <2>;
+ dma-coherent;
+
+ liointc0: interrupt-controller@1fe01400 {
+ compatible = "loongson,liointc-2.0";
+ reg = <0x0 0x1fe01400 0x0 0x40>,
+ <0x0 0x1fe01040 0x0 0x8>,
+ <0x0 0x1fe01140 0x0 0x8>;
+ reg-names = "main", "isr0", "isr1";
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ interrupt-parent = <&cpuintc>;
+ interrupts = <2>;
+ interrupt-names = "int0";
+ loongson,parent_int_map = <0xffffffff>, /* int0 */
+ <0x00000000>, /* int1 */
+ <0x00000000>, /* int2 */
+ <0x00000000>; /* int3 */
+ };
+
+ liointc1: interrupt-controller@1fe01440 {
+ compatible = "loongson,liointc-2.0";
+ reg = <0x0 0x1fe01440 0x0 0x40>,
+ <0x0 0x1fe01048 0x0 0x8>,
+ <0x0 0x1fe01148 0x0 0x8>;
+ reg-names = "main", "isr0", "isr1";
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ interrupt-parent = <&cpuintc>;
+ interrupts = <3>;
+ interrupt-names = "int1";
+ loongson,parent_int_map = <0x00000000>, /* int0 */
+ <0xffffffff>, /* int1 */
+ <0x00000000>, /* int2 */
+ <0x00000000>; /* int3 */
+ };
+
+ chipid@1fe00000 {
+ compatible = "loongson,ls2k-chipid";
+ reg = <0x0 0x1fe00000 0x0 0x30>;
+ little-endian;
+ };
+
+ pctrl: pinctrl@1fe00420 {
+ compatible = "loongson,ls2k-pinctrl";
+ reg = <0x0 0x1fe00420 0x0 0x18>;
+ status = "disabled";
+ };
+
+ clk: clock-controller@1fe00480 {
+ compatible = "loongson,ls2k-clk";
+ reg = <0x0 0x1fe00480 0x0 0x58>;
+ #clock-cells = <1>;
+ clocks = <&ref_100m>;
+ clock-names = "ref_100m";
+ status = "disabled";
+ };
+
+ gpio0: gpio@1fe00500 {
+ compatible = "loongson,ls2k-gpio";
+ reg = <0x0 0x1fe00500 0x0 0x38>;
+ ngpios = <64>;
+ #gpio-cells = <2>;
+ gpio-controller;
+ gpio-ranges = <&pctrl 0x0 0x0 15>,
+ <&pctrl 16 16 15>,
+ <&pctrl 32 32 10>,
+ <&pctrl 44 44 20>;
+ interrupt-parent = <&liointc1>;
+ interrupts = <28 IRQ_TYPE_LEVEL_HIGH>,
+ <29 IRQ_TYPE_LEVEL_HIGH>,
+ <30 IRQ_TYPE_LEVEL_HIGH>,
+ <30 IRQ_TYPE_LEVEL_HIGH>,
+ <26 IRQ_TYPE_LEVEL_HIGH>,
+ <26 IRQ_TYPE_LEVEL_HIGH>,
+ <26 IRQ_TYPE_LEVEL_HIGH>,
+ <26 IRQ_TYPE_LEVEL_HIGH>,
+ <26 IRQ_TYPE_LEVEL_HIGH>,
+ <26 IRQ_TYPE_LEVEL_HIGH>,
+ <26 IRQ_TYPE_LEVEL_HIGH>,
+ <26 IRQ_TYPE_LEVEL_HIGH>,
+ <26 IRQ_TYPE_LEVEL_HIGH>,
+ <26 IRQ_TYPE_LEVEL_HIGH>,
+ <26 IRQ_TYPE_LEVEL_HIGH>,
+ <>,
+ <26 IRQ_TYPE_LEVEL_HIGH>,
+ <26 IRQ_TYPE_LEVEL_HIGH>,
+ <26 IRQ_TYPE_LEVEL_HIGH>,
+ <26 IRQ_TYPE_LEVEL_HIGH>,
+ <26 IRQ_TYPE_LEVEL_HIGH>,
+ <26 IRQ_TYPE_LEVEL_HIGH>,
+ <26 IRQ_TYPE_LEVEL_HIGH>,
+ <26 IRQ_TYPE_LEVEL_HIGH>,
+ <26 IRQ_TYPE_LEVEL_HIGH>,
+ <26 IRQ_TYPE_LEVEL_HIGH>,
+ <26 IRQ_TYPE_LEVEL_HIGH>,
+ <26 IRQ_TYPE_LEVEL_HIGH>,
+ <26 IRQ_TYPE_LEVEL_HIGH>,
+ <26 IRQ_TYPE_LEVEL_HIGH>,
+ <26 IRQ_TYPE_LEVEL_HIGH>,
+ <26 IRQ_TYPE_LEVEL_HIGH>,
+ <27 IRQ_TYPE_LEVEL_HIGH>,
+ <27 IRQ_TYPE_LEVEL_HIGH>,
+ <27 IRQ_TYPE_LEVEL_HIGH>,
+ <27 IRQ_TYPE_LEVEL_HIGH>,
+ <27 IRQ_TYPE_LEVEL_HIGH>,
+ <>,
+ <27 IRQ_TYPE_LEVEL_HIGH>,
+ <27 IRQ_TYPE_LEVEL_HIGH>,
+ <27 IRQ_TYPE_LEVEL_HIGH>,
+ <27 IRQ_TYPE_LEVEL_HIGH>,
+ <>,
+ <>,
+ <27 IRQ_TYPE_LEVEL_HIGH>,
+ <27 IRQ_TYPE_LEVEL_HIGH>,
+ <27 IRQ_TYPE_LEVEL_HIGH>,
+ <27 IRQ_TYPE_LEVEL_HIGH>,
+ <27 IRQ_TYPE_LEVEL_HIGH>,
+ <27 IRQ_TYPE_LEVEL_HIGH>,
+ <27 IRQ_TYPE_LEVEL_HIGH>,
+ <27 IRQ_TYPE_LEVEL_HIGH>,
+ <27 IRQ_TYPE_LEVEL_HIGH>,
+ <27 IRQ_TYPE_LEVEL_HIGH>,
+ <27 IRQ_TYPE_LEVEL_HIGH>,
+ <27 IRQ_TYPE_LEVEL_HIGH>,
+ <27 IRQ_TYPE_LEVEL_HIGH>,
+ <27 IRQ_TYPE_LEVEL_HIGH>,
+ <27 IRQ_TYPE_LEVEL_HIGH>,
+ <27 IRQ_TYPE_LEVEL_HIGH>,
+ <27 IRQ_TYPE_LEVEL_HIGH>,
+ <27 IRQ_TYPE_LEVEL_HIGH>,
+ <27 IRQ_TYPE_LEVEL_HIGH>,
+ <27 IRQ_TYPE_LEVEL_HIGH>;
+ };
+
+ tsensor: thermal-sensor@1fe01500 {
+ compatible = "loongson,ls2k1000-thermal";
+ reg = <0x0 0x1fe01500 0x0 0x30>;
+ interrupt-parent = <&liointc0>;
+ interrupts = <7 IRQ_TYPE_LEVEL_HIGH>;
+ #thermal-sensor-cells = <1>;
+ };
+
+ dma-controller@1fe00c00 {
+ compatible = "loongson,ls2k1000-apbdma";
+ reg = <0x0 0x1fe00c00 0x0 0x8>;
+ interrupt-parent = <&liointc1>;
+ interrupts = <12 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&clk LOONGSON2_APB_CLK>;
+ #dma-cells = <1>;
+ status = "disabled";
+ };
+
+ dma-controller@1fe00c10 {
+ compatible = "loongson,ls2k1000-apbdma";
+ reg = <0x0 0x1fe00c10 0x0 0x8>;
+ interrupt-parent = <&liointc1>;
+ interrupts = <13 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&clk LOONGSON2_APB_CLK>;
+ #dma-cells = <1>;
+ status = "disabled";
+ };
+
+ dma-controller@1fe00c20 {
+ compatible = "loongson,ls2k1000-apbdma";
+ reg = <0x0 0x1fe00c20 0x0 0x8>;
+ interrupt-parent = <&liointc1>;
+ interrupts = <14 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&clk LOONGSON2_APB_CLK>;
+ #dma-cells = <1>;
+ status = "disabled";
+ };
+
+ dma-controller@1fe00c30 {
+ compatible = "loongson,ls2k1000-apbdma";
+ reg = <0x0 0x1fe00c30 0x0 0x8>;
+ interrupt-parent = <&liointc1>;
+ interrupts = <15 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&clk LOONGSON2_APB_CLK>;
+ #dma-cells = <1>;
+ status = "disabled";
+ };
+
+ dma-controller@1fe00c40 {
+ compatible = "loongson,ls2k1000-apbdma";
+ reg = <0x0 0x1fe00c40 0x0 0x8>;
+ interrupt-parent = <&liointc1>;
+ interrupts = <16 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&clk LOONGSON2_APB_CLK>;
+ #dma-cells = <1>;
+ status = "disabled";
+ };
+
+ uart0: serial@1fe20000 {
+ compatible = "ns16550a";
+ reg = <0x0 0x1fe20000 0x0 0x10>;
+ clock-frequency = <125000000>;
+ interrupt-parent = <&liointc0>;
+ interrupts = <0x0 IRQ_TYPE_LEVEL_HIGH>;
+ no-loopback-test;
+ status = "disabled";
+ };
+
+ i2c2: i2c@1fe21000 {
+ compatible = "loongson,ls2k-i2c";
+ reg = <0x0 0x1fe21000 0x0 0x8>;
+ interrupt-parent = <&liointc0>;
+ interrupts = <22 IRQ_TYPE_LEVEL_HIGH>;
+ status = "disabled";
+ };
+
+ i2c3: i2c@1fe21800 {
+ compatible = "loongson,ls2k-i2c";
+ reg = <0x0 0x1fe21800 0x0 0x8>;
+ interrupt-parent = <&liointc0>;
+ interrupts = <23 IRQ_TYPE_LEVEL_HIGH>;
+ status = "disabled";
+ };
+
+ pmc: power-management@1fe27000 {
+ compatible = "loongson,ls2k1000-pmc", "loongson,ls2k0500-pmc", "syscon";
+ reg = <0x0 0x1fe27000 0x0 0x58>;
+ interrupt-parent = <&liointc1>;
+ interrupts = <11 IRQ_TYPE_LEVEL_HIGH>;
+ loongson,suspend-address = <0x0 0x1c000500>;
+
+ syscon-reboot {
+ compatible = "syscon-reboot";
+ offset = <0x30>;
+ mask = <0x1>;
+ };
+
+ syscon-poweroff {
+ compatible = "syscon-poweroff";
+ regmap = <&pmc>;
+ offset = <0x14>;
+ mask = <0x3c00>;
+ value = <0x3c00>;
+ };
+ };
+
+ rtc0: rtc@1fe27800 {
+ compatible = "loongson,ls2k1000-rtc";
+ reg = <0x0 0x1fe27800 0x0 0x100>;
+ interrupt-parent = <&liointc1>;
+ interrupts = <8 IRQ_TYPE_LEVEL_HIGH>;
+ status = "disabled";
+ };
+
+ spi0: spi@1fff0220 {
+ compatible = "loongson,ls2k1000-spi";
+ reg = <0x0 0x1fff0220 0x0 0x10>;
+ clocks = <&clk LOONGSON2_BOOT_CLK>;
+ status = "disabled";
+ };
+
+ pcie@1a000000 {
+ compatible = "loongson,ls2k-pci";
+ reg = <0x0 0x1a000000 0x0 0x02000000>,
+ <0xfe 0x0 0x0 0x20000000>;
+ #address-cells = <3>;
+ #size-cells = <2>;
+ device_type = "pci";
+ bus-range = <0x0 0xff>;
+ ranges = <0x01000000 0x0 0x00008000 0x0 0x18008000 0x0 0x00008000>,
+ <0x02000000 0x0 0x60000000 0x0 0x60000000 0x0 0x20000000>;
+
+ gmac0: ethernet@3,0 {
+ reg = <0x1800 0x0 0x0 0x0 0x0>;
+ interrupt-parent = <&liointc0>;
+ interrupts = <12 IRQ_TYPE_LEVEL_HIGH>,
+ <13 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "macirq", "eth_lpi";
+ status = "disabled";
+ };
+
+ gmac1: ethernet@3,1 {
+ reg = <0x1900 0x0 0x0 0x0 0x0>;
+ interrupt-parent = <&liointc0>;
+ interrupts = <14 IRQ_TYPE_LEVEL_HIGH>,
+ <15 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "macirq", "eth_lpi";
+ status = "disabled";
+ };
+
+ ehci0: usb@4,1 {
+ reg = <0x2100 0x0 0x0 0x0 0x0>;
+ interrupt-parent = <&liointc1>;
+ interrupts = <18 IRQ_TYPE_LEVEL_HIGH>;
+ status = "disabled";
+ };
+
+ ohci0: usb@4,2 {
+ reg = <0x2200 0x0 0x0 0x0 0x0>;
+ interrupt-parent = <&liointc1>;
+ interrupts = <19 IRQ_TYPE_LEVEL_HIGH>;
+ status = "disabled";
+ };
+
+ display@6,0 {
+ reg = <0x3000 0x0 0x0 0x0 0x0>;
+ interrupt-parent = <&liointc0>;
+ interrupts = <28 IRQ_TYPE_LEVEL_HIGH>;
+ status = "disabled";
+ };
+
+ hda@7,0 {
+ reg = <0x3800 0x0 0x0 0x0 0x0>;
+ interrupt-parent = <&liointc0>;
+ interrupts = <4 IRQ_TYPE_LEVEL_HIGH>;
+ status = "disabled";
+ };
+
+ sata: sata@8,0 {
+ reg = <0x4000 0x0 0x0 0x0 0x0>;
+ interrupt-parent = <&liointc0>;
+ interrupts = <19 IRQ_TYPE_LEVEL_HIGH>;
+ status = "disabled";
+ };
+
+ pcie@9,0 {
+ reg = <0x4800 0x0 0x0 0x0 0x0>;
+ #address-cells = <3>;
+ #size-cells = <2>;
+ device_type = "pci";
+ #interrupt-cells = <1>;
+ interrupt-map-mask = <0x0 0x0 0x0 0x0>;
+ interrupt-map = <0x0 0x0 0x0 0x0 &liointc1 0x0 IRQ_TYPE_LEVEL_HIGH>;
+ ranges;
+ };
+
+ pcie@a,0 {
+ reg = <0x5000 0x0 0x0 0x0 0x0>;
+ #address-cells = <3>;
+ #size-cells = <2>;
+ device_type = "pci";
+ interrupt-parent = <&liointc1>;
+ #interrupt-cells = <1>;
+ interrupt-map-mask = <0x0 0x0 0x0 0x0>;
+ interrupt-map = <0x0 0x0 0x0 0x0 &liointc1 1 IRQ_TYPE_LEVEL_HIGH>;
+ ranges;
+ };
+
+ pcie@b,0 {
+ reg = <0x5800 0x0 0x0 0x0 0x0>;
+ #address-cells = <3>;
+ #size-cells = <2>;
+ device_type = "pci";
+ interrupt-parent = <&liointc1>;
+ #interrupt-cells = <1>;
+ interrupt-map-mask = <0x0 0x0 0x0 0x0>;
+ interrupt-map = <0x0 0x0 0x0 0x0 &liointc1 2 IRQ_TYPE_LEVEL_HIGH>;
+ ranges;
+ };
+
+ pcie@c,0 {
+ reg = <0x6000 0x0 0x0 0x0 0x0>;
+ #address-cells = <3>;
+ #size-cells = <2>;
+ device_type = "pci";
+ interrupt-parent = <&liointc1>;
+ #interrupt-cells = <1>;
+ interrupt-map-mask = <0x0 0x0 0x0 0x0>;
+ interrupt-map = <0x0 0x0 0x0 0x0 &liointc1 3 IRQ_TYPE_LEVEL_HIGH>;
+ ranges;
+ };
+
+ pcie@d,0 {
+ reg = <0x6800 0x0 0x0 0x0 0x0>;
+ #address-cells = <3>;
+ #size-cells = <2>;
+ device_type = "pci";
+ interrupt-parent = <&liointc1>;
+ #interrupt-cells = <1>;
+ interrupt-map-mask = <0x0 0x0 0x0 0x0>;
+ interrupt-map = <0x0 0x0 0x0 0x0 &liointc1 4 IRQ_TYPE_LEVEL_HIGH>;
+ ranges;
+ };
+
+ pcie@e,0 {
+ reg = <0x7000 0x0 0x0 0x0 0x0>;
+ #address-cells = <3>;
+ #size-cells = <2>;
+ device_type = "pci";
+ interrupt-parent = <&liointc1>;
+ #interrupt-cells = <1>;
+ interrupt-map-mask = <0x0 0x0 0x0 0x0>;
+ interrupt-map = <0x0 0x0 0x0 0x0 &liointc1 5 IRQ_TYPE_LEVEL_HIGH>;
+ ranges;
+ };
+ };
+ };
+};
diff --git a/dts/upstream/src/loongarch/loongson-2k2000-ref.dts b/dts/upstream/src/loongarch/loongson-2k2000-ref.dts
new file mode 100644
index 0000000..dca91ca
--- /dev/null
+++ b/dts/upstream/src/loongarch/loongson-2k2000-ref.dts
@@ -0,0 +1,72 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (C) 2023 Loongson Technology Corporation Limited
+ */
+
+/dts-v1/;
+
+#include "loongson-2k2000.dtsi"
+
+/ {
+ compatible = "loongson,ls2k2000-ref", "loongson,ls2k2000";
+ model = "Loongson-2K2000 Reference Board";
+
+ aliases {
+ serial0 = &uart0;
+ };
+
+ chosen {
+ stdout-path = "serial0:115200n8";
+ };
+
+ memory@200000 {
+ device_type = "memory";
+ reg = <0x0 0x00200000 0x0 0x0ee00000>,
+ <0x0 0x90000000 0x0 0x70000000>;
+ };
+
+ reserved-memory {
+ #address-cells = <2>;
+ #size-cells = <2>;
+ ranges;
+
+ linux,cma {
+ compatible = "shared-dma-pool";
+ reusable;
+ size = <0x0 0x2000000>;
+ linux,cma-default;
+ };
+ };
+};
+
+&sata {
+ status = "okay";
+};
+
+&uart0 {
+ status = "okay";
+};
+
+&rtc0 {
+ status = "okay";
+};
+
+&xhci0 {
+ status = "okay";
+};
+
+&xhci1 {
+ status = "okay";
+};
+
+&gmac0 {
+ status = "okay";
+};
+
+&gmac1 {
+ status = "okay";
+};
+
+&gmac2 {
+ status = "okay";
+};
diff --git a/dts/upstream/src/loongarch/loongson-2k2000.dtsi b/dts/upstream/src/loongarch/loongson-2k2000.dtsi
new file mode 100644
index 0000000..a231949
--- /dev/null
+++ b/dts/upstream/src/loongarch/loongson-2k2000.dtsi
@@ -0,0 +1,300 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (C) 2023 Loongson Technology Corporation Limited
+ */
+
+/dts-v1/;
+
+#include <dt-bindings/interrupt-controller/irq.h>
+
+/ {
+ #address-cells = <2>;
+ #size-cells = <2>;
+
+ cpus {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ cpu0: cpu@1 {
+ compatible = "loongson,la364";
+ device_type = "cpu";
+ reg = <0x0>;
+ clocks = <&cpu_clk>;
+ };
+
+ cpu1: cpu@2 {
+ compatible = "loongson,la364";
+ device_type = "cpu";
+ reg = <0x1>;
+ clocks = <&cpu_clk>;
+ };
+ };
+
+ cpu_clk: cpu-clk {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <1400000000>;
+ };
+
+ cpuintc: interrupt-controller {
+ compatible = "loongson,cpu-interrupt-controller";
+ #interrupt-cells = <1>;
+ interrupt-controller;
+ };
+
+ bus@10000000 {
+ compatible = "simple-bus";
+ ranges = <0x0 0x10000000 0x0 0x10000000 0x0 0x10000000>,
+ <0x0 0x02000000 0x0 0x02000000 0x0 0x02000000>,
+ <0x0 0x40000000 0x0 0x40000000 0x0 0x40000000>,
+ <0xfe 0x0 0xfe 0x0 0x0 0x40000000>;
+ #address-cells = <2>;
+ #size-cells = <2>;
+
+ pmc: power-management@100d0000 {
+ compatible = "loongson,ls2k2000-pmc", "loongson,ls2k0500-pmc", "syscon";
+ reg = <0x0 0x100d0000 0x0 0x58>;
+ interrupt-parent = <&eiointc>;
+ interrupts = <47>;
+ loongson,suspend-address = <0x0 0x1c000500>;
+
+ syscon-reboot {
+ compatible = "syscon-reboot";
+ offset = <0x30>;
+ mask = <0x1>;
+ };
+
+ syscon-poweroff {
+ compatible = "syscon-poweroff";
+ regmap = <&pmc>;
+ offset = <0x14>;
+ mask = <0x3c00>;
+ value = <0x3c00>;
+ };
+ };
+
+ liointc: interrupt-controller@1fe01400 {
+ compatible = "loongson,liointc-1.0";
+ reg = <0x0 0x1fe01400 0x0 0x64>;
+
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ interrupt-parent = <&cpuintc>;
+ interrupts = <2>;
+ interrupt-names = "int0";
+ loongson,parent_int_map = <0xffffffff>, /* int0 */
+ <0x00000000>, /* int1 */
+ <0x00000000>, /* int2 */
+ <0x00000000>; /* int3 */
+ };
+
+ eiointc: interrupt-controller@1fe01600 {
+ compatible = "loongson,ls2k2000-eiointc";
+ reg = <0x0 0x1fe01600 0x0 0xea00>;
+ interrupt-controller;
+ #interrupt-cells = <1>;
+ interrupt-parent = <&cpuintc>;
+ interrupts = <3>;
+ };
+
+ pic: interrupt-controller@10000000 {
+ compatible = "loongson,pch-pic-1.0";
+ reg = <0x0 0x10000000 0x0 0x400>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ loongson,pic-base-vec = <0>;
+ interrupt-parent = <&eiointc>;
+ };
+
+ msi: msi-controller@1fe01140 {
+ compatible = "loongson,pch-msi-1.0";
+ reg = <0x0 0x1fe01140 0x0 0x8>;
+ msi-controller;
+ loongson,msi-base-vec = <64>;
+ loongson,msi-num-vecs = <192>;
+ interrupt-parent = <&eiointc>;
+ };
+
+ rtc0: rtc@100d0100 {
+ compatible = "loongson,ls2k2000-rtc", "loongson,ls7a-rtc";
+ reg = <0x0 0x100d0100 0x0 0x100>;
+ interrupt-parent = <&pic>;
+ interrupts = <52 IRQ_TYPE_LEVEL_HIGH>;
+ status = "disabled";
+ };
+
+ uart0: serial@1fe001e0 {
+ compatible = "ns16550a";
+ reg = <0x0 0x1fe001e0 0x0 0x10>;
+ clock-frequency = <100000000>;
+ interrupt-parent = <&liointc>;
+ interrupts = <10 IRQ_TYPE_LEVEL_HIGH>;
+ no-loopback-test;
+ status = "disabled";
+ };
+
+ pcie@1a000000 {
+ compatible = "loongson,ls2k-pci";
+ reg = <0x0 0x1a000000 0x0 0x02000000>,
+ <0xfe 0x0 0x0 0x20000000>;
+ #address-cells = <3>;
+ #size-cells = <2>;
+ device_type = "pci";
+ bus-range = <0x0 0xff>;
+ ranges = <0x01000000 0x0 0x00008000 0x0 0x18400000 0x0 0x00008000>,
+ <0x02000000 0x0 0x60000000 0x0 0x60000000 0x0 0x20000000>;
+
+ gmac0: ethernet@3,0 {
+ reg = <0x1800 0x0 0x0 0x0 0x0>;
+ interrupts = <12 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-parent = <&pic>;
+ status = "disabled";
+ };
+
+ gmac1: ethernet@3,1 {
+ reg = <0x1900 0x0 0x0 0x0 0x0>;
+ interrupts = <14 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-parent = <&pic>;
+ status = "disabled";
+ };
+
+ gmac2: ethernet@3,2 {
+ reg = <0x1a00 0x0 0x0 0x0 0x0>;
+ interrupts = <17 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-parent = <&pic>;
+ status = "disabled";
+ };
+
+ xhci0: usb@4,0 {
+ reg = <0x2000 0x0 0x0 0x0 0x0>;
+ interrupts = <48 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-parent = <&pic>;
+ status = "disabled";
+ };
+
+ xhci1: usb@19,0 {
+ reg = <0xc800 0x0 0x0 0x0 0x0>;
+ interrupts = <22 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-parent = <&pic>;
+ status = "disabled";
+ };
+
+ display@6,1 {
+ reg = <0x3100 0x0 0x0 0x0 0x0>;
+ interrupts = <28 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-parent = <&pic>;
+ status = "disabled";
+ };
+
+ hda@7,0 {
+ reg = <0x3800 0x0 0x0 0x0 0x0>;
+ interrupts = <58 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-parent = <&pic>;
+ status = "disabled";
+ };
+
+ sata: sata@8,0 {
+ reg = <0x4000 0x0 0x0 0x0 0x0>;
+ interrupts = <16 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-parent = <&pic>;
+ status = "disabled";
+ };
+
+ pcie@9,0 {
+ reg = <0x4800 0x0 0x0 0x0 0x0>;
+ #address-cells = <3>;
+ #size-cells = <2>;
+ device_type = "pci";
+ interrupt-parent = <&pic>;
+ #interrupt-cells = <1>;
+ interrupt-map-mask = <0x0 0x0 0x0 0x0>;
+ interrupt-map = <0x0 0x0 0x0 0x0 &pic 32 IRQ_TYPE_LEVEL_HIGH>;
+ ranges;
+ };
+
+ pcie@a,0 {
+ reg = <0x5000 0x0 0x0 0x0 0x0>;
+ #address-cells = <3>;
+ #size-cells = <2>;
+ device_type = "pci";
+ interrupt-parent = <&pic>;
+ #interrupt-cells = <1>;
+ interrupt-map-mask = <0x0 0x0 0x0 0x0>;
+ interrupt-map = <0x0 0x0 0x0 0x0 &pic 33 IRQ_TYPE_LEVEL_HIGH>;
+ ranges;
+ };
+
+ pcie@b,0 {
+ reg = <0x5800 0x0 0x0 0x0 0x0>;
+ #address-cells = <3>;
+ #size-cells = <2>;
+ device_type = "pci";
+ interrupt-parent = <&pic>;
+ #interrupt-cells = <1>;
+ interrupt-map-mask = <0x0 0x0 0x0 0x0>;
+ interrupt-map = <0x0 0x0 0x0 0x0 &pic 34 IRQ_TYPE_LEVEL_HIGH>;
+ ranges;
+ };
+
+ pcie@c,0 {
+ reg = <0x6000 0x0 0x0 0x0 0x0>;
+ #address-cells = <3>;
+ #size-cells = <2>;
+ device_type = "pci";
+ interrupt-parent = <&pic>;
+ #interrupt-cells = <1>;
+ interrupt-map-mask = <0x0 0x0 0x0 0x0>;
+ interrupt-map = <0x0 0x0 0x0 0x0 &pic 35 IRQ_TYPE_LEVEL_HIGH>;
+ ranges;
+ };
+
+ pcie@d,0 {
+ reg = <0x6800 0x0 0x0 0x0 0x0>;
+ #address-cells = <3>;
+ #size-cells = <2>;
+ device_type = "pci";
+ interrupt-parent = <&pic>;
+ #interrupt-cells = <1>;
+ interrupt-map-mask = <0x0 0x0 0x0 0x0>;
+ interrupt-map = <0x0 0x0 0x0 0x0 &pic 36 IRQ_TYPE_LEVEL_HIGH>;
+ ranges;
+ };
+
+ pcie@e,0 {
+ reg = <0x7000 0x0 0x0 0x0 0x0>;
+ #address-cells = <3>;
+ #size-cells = <2>;
+ device_type = "pci";
+ interrupt-parent = <&pic>;
+ #interrupt-cells = <1>;
+ interrupt-map-mask = <0x0 0x0 0x0 0x0>;
+ interrupt-map = <0x0 0x0 0x0 0x0 &pic 37 IRQ_TYPE_LEVEL_HIGH>;
+ ranges;
+ };
+
+ pcie@f,0 {
+ reg = <0x7800 0x0 0x0 0x0 0x0>;
+ #address-cells = <3>;
+ #size-cells = <2>;
+ device_type = "pci";
+ interrupt-parent = <&pic>;
+ #interrupt-cells = <1>;
+ interrupt-map-mask = <0x0 0x0 0x0 0x0>;
+ interrupt-map = <0x0 0x0 0x0 0x0 &pic 40 IRQ_TYPE_LEVEL_HIGH>;
+ ranges;
+ };
+
+ pcie@10,0 {
+ reg = <0x8000 0x0 0x0 0x0 0x0>;
+ #address-cells = <3>;
+ #size-cells = <2>;
+ device_type = "pci";
+ interrupt-parent = <&pic>;
+ #interrupt-cells = <1>;
+ interrupt-map-mask = <0x0 0x0 0x0 0x0>;
+ interrupt-map = <0x0 0x0 0x0 0x0 &pic 30 IRQ_TYPE_LEVEL_HIGH>;
+ ranges;
+ };
+ };
+ };
+};
diff --git a/dts/upstream/src/powerpc/fsl/t1023si-post.dtsi b/dts/upstream/src/powerpc/fsl/t1023si-post.dtsi
index d552044..aa5152c 100644
--- a/dts/upstream/src/powerpc/fsl/t1023si-post.dtsi
+++ b/dts/upstream/src/powerpc/fsl/t1023si-post.dtsi
@@ -367,45 +367,46 @@
reg = <0xf0000 0x1000>;
interrupts = <18 2 0 0>;
fsl,tmu-range = <0xb0000 0xa0026 0x80048 0x30061>;
- fsl,tmu-calibration = <0x00000000 0x0000000f
- 0x00000001 0x00000017
- 0x00000002 0x0000001e
- 0x00000003 0x00000026
- 0x00000004 0x0000002e
- 0x00000005 0x00000035
- 0x00000006 0x0000003d
- 0x00000007 0x00000044
- 0x00000008 0x0000004c
- 0x00000009 0x00000053
- 0x0000000a 0x0000005b
- 0x0000000b 0x00000064
+ fsl,tmu-calibration =
+ <0x00000000 0x0000000f>,
+ <0x00000001 0x00000017>,
+ <0x00000002 0x0000001e>,
+ <0x00000003 0x00000026>,
+ <0x00000004 0x0000002e>,
+ <0x00000005 0x00000035>,
+ <0x00000006 0x0000003d>,
+ <0x00000007 0x00000044>,
+ <0x00000008 0x0000004c>,
+ <0x00000009 0x00000053>,
+ <0x0000000a 0x0000005b>,
+ <0x0000000b 0x00000064>,
- 0x00010000 0x00000011
- 0x00010001 0x0000001c
- 0x00010002 0x00000024
- 0x00010003 0x0000002b
- 0x00010004 0x00000034
- 0x00010005 0x00000039
- 0x00010006 0x00000042
- 0x00010007 0x0000004c
- 0x00010008 0x00000051
- 0x00010009 0x0000005a
- 0x0001000a 0x00000063
+ <0x00010000 0x00000011>,
+ <0x00010001 0x0000001c>,
+ <0x00010002 0x00000024>,
+ <0x00010003 0x0000002b>,
+ <0x00010004 0x00000034>,
+ <0x00010005 0x00000039>,
+ <0x00010006 0x00000042>,
+ <0x00010007 0x0000004c>,
+ <0x00010008 0x00000051>,
+ <0x00010009 0x0000005a>,
+ <0x0001000a 0x00000063>,
- 0x00020000 0x00000013
- 0x00020001 0x00000019
- 0x00020002 0x00000024
- 0x00020003 0x0000002c
- 0x00020004 0x00000035
- 0x00020005 0x0000003d
- 0x00020006 0x00000046
- 0x00020007 0x00000050
- 0x00020008 0x00000059
+ <0x00020000 0x00000013>,
+ <0x00020001 0x00000019>,
+ <0x00020002 0x00000024>,
+ <0x00020003 0x0000002c>,
+ <0x00020004 0x00000035>,
+ <0x00020005 0x0000003d>,
+ <0x00020006 0x00000046>,
+ <0x00020007 0x00000050>,
+ <0x00020008 0x00000059>,
- 0x00030000 0x00000002
- 0x00030001 0x0000000d
- 0x00030002 0x00000019
- 0x00030003 0x00000024>;
+ <0x00030000 0x00000002>,
+ <0x00030001 0x0000000d>,
+ <0x00030002 0x00000019>,
+ <0x00030003 0x00000024>;
#thermal-sensor-cells = <1>;
};
diff --git a/dts/upstream/src/powerpc/fsl/t1040si-post.dtsi b/dts/upstream/src/powerpc/fsl/t1040si-post.dtsi
index ad0ab33..7767886 100644
--- a/dts/upstream/src/powerpc/fsl/t1040si-post.dtsi
+++ b/dts/upstream/src/powerpc/fsl/t1040si-post.dtsi
@@ -447,41 +447,42 @@
reg = <0xf0000 0x1000>;
interrupts = <18 2 0 0>;
fsl,tmu-range = <0xa0000 0x90026 0x8004a 0x1006a>;
- fsl,tmu-calibration = <0x00000000 0x00000025
- 0x00000001 0x00000028
- 0x00000002 0x0000002d
- 0x00000003 0x00000031
- 0x00000004 0x00000036
- 0x00000005 0x0000003a
- 0x00000006 0x00000040
- 0x00000007 0x00000044
- 0x00000008 0x0000004a
- 0x00000009 0x0000004f
- 0x0000000a 0x00000054
+ fsl,tmu-calibration =
+ <0x00000000 0x00000025>,
+ <0x00000001 0x00000028>,
+ <0x00000002 0x0000002d>,
+ <0x00000003 0x00000031>,
+ <0x00000004 0x00000036>,
+ <0x00000005 0x0000003a>,
+ <0x00000006 0x00000040>,
+ <0x00000007 0x00000044>,
+ <0x00000008 0x0000004a>,
+ <0x00000009 0x0000004f>,
+ <0x0000000a 0x00000054>,
- 0x00010000 0x0000000d
- 0x00010001 0x00000013
- 0x00010002 0x00000019
- 0x00010003 0x0000001f
- 0x00010004 0x00000025
- 0x00010005 0x0000002d
- 0x00010006 0x00000033
- 0x00010007 0x00000043
- 0x00010008 0x0000004b
- 0x00010009 0x00000053
+ <0x00010000 0x0000000d>,
+ <0x00010001 0x00000013>,
+ <0x00010002 0x00000019>,
+ <0x00010003 0x0000001f>,
+ <0x00010004 0x00000025>,
+ <0x00010005 0x0000002d>,
+ <0x00010006 0x00000033>,
+ <0x00010007 0x00000043>,
+ <0x00010008 0x0000004b>,
+ <0x00010009 0x00000053>,
- 0x00020000 0x00000010
- 0x00020001 0x00000017
- 0x00020002 0x0000001f
- 0x00020003 0x00000029
- 0x00020004 0x00000031
- 0x00020005 0x0000003c
- 0x00020006 0x00000042
- 0x00020007 0x0000004d
- 0x00020008 0x00000056
+ <0x00020000 0x00000010>,
+ <0x00020001 0x00000017>,
+ <0x00020002 0x0000001f>,
+ <0x00020003 0x00000029>,
+ <0x00020004 0x00000031>,
+ <0x00020005 0x0000003c>,
+ <0x00020006 0x00000042>,
+ <0x00020007 0x0000004d>,
+ <0x00020008 0x00000056>,
- 0x00030000 0x00000012
- 0x00030001 0x0000001d>;
+ <0x00030000 0x00000012>,
+ <0x00030001 0x0000001d>;
#thermal-sensor-cells = <1>;
};
diff --git a/dts/upstream/src/riscv/microchip/mpfs-icicle-kit.dts b/dts/upstream/src/riscv/microchip/mpfs-icicle-kit.dts
index dce96f2..222a39d 100644
--- a/dts/upstream/src/riscv/microchip/mpfs-icicle-kit.dts
+++ b/dts/upstream/src/riscv/microchip/mpfs-icicle-kit.dts
@@ -192,6 +192,27 @@
status = "okay";
};
+&syscontroller_qspi {
+ /*
+ * The flash *is* there, but Icicle kits that have engineering sample
+ * silicon (write?) access to this flash to non-functional. The system
+ * controller itself can actually access it, but the MSS cannot write
+ * an image there. Instantiating a coreQSPI in the fabric & connecting
+ * it to the flash instead should work though. Pre-production or later
+ * silicon does not have this issue.
+ */
+ status = "disabled";
+
+ sys_ctrl_flash: flash@0 { // MT25QL01GBBB8ESF-0SIT
+ compatible = "jedec,spi-nor";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ spi-max-frequency = <20000000>;
+ spi-rx-bus-width = <1>;
+ reg = <0>;
+ };
+};
+
&usb {
status = "okay";
dr_mode = "host";
diff --git a/dts/upstream/src/riscv/microchip/mpfs.dtsi b/dts/upstream/src/riscv/microchip/mpfs.dtsi
index 266489d..59fd2d4 100644
--- a/dts/upstream/src/riscv/microchip/mpfs.dtsi
+++ b/dts/upstream/src/riscv/microchip/mpfs.dtsi
@@ -194,6 +194,12 @@
mboxes = <&mbox 0>;
};
+ scbclk: mssclkclk {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <80000000>;
+ };
+
soc {
#address-cells = <2>;
#size-cells = <2>;
@@ -524,5 +530,16 @@
#mbox-cells = <1>;
status = "disabled";
};
+
+ syscontroller_qspi: spi@37020100 {
+ compatible = "microchip,mpfs-qspi", "microchip,coreqspi-rtl-v2";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0x0 0x37020100 0x0 0x100>;
+ interrupt-parent = <&plic>;
+ interrupts = <110>;
+ clocks = <&scbclk>;
+ status = "disabled";
+ };
};
};
diff --git a/dts/upstream/src/riscv/renesas/r9a07g043f.dtsi b/dts/upstream/src/riscv/renesas/r9a07g043f.dtsi
index b079601..a92cfcf 100644
--- a/dts/upstream/src/riscv/renesas/r9a07g043f.dtsi
+++ b/dts/upstream/src/riscv/renesas/r9a07g043f.dtsi
@@ -24,6 +24,10 @@
reg = <0x0>;
status = "okay";
riscv,isa = "rv64imafdc";
+ riscv,isa-base = "rv64i";
+ riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
+ "zicntr", "zicsr", "zifencei",
+ "zihpm";
mmu-type = "riscv,sv39";
i-cache-size = <0x8000>;
i-cache-line-size = <0x40>;
diff --git a/dts/upstream/src/riscv/sifive/hifive-unmatched-a00.dts b/dts/upstream/src/riscv/sifive/hifive-unmatched-a00.dts
index 07387f9..72b87b0 100644
--- a/dts/upstream/src/riscv/sifive/hifive-unmatched-a00.dts
+++ b/dts/upstream/src/riscv/sifive/hifive-unmatched-a00.dts
@@ -123,6 +123,7 @@
interrupt-parent = <&gpio>;
interrupts = <1 IRQ_TYPE_LEVEL_LOW>;
interrupt-controller;
+ #interrupt-cells = <2>;
onkey {
compatible = "dlg,da9063-onkey";
diff --git a/dts/upstream/src/riscv/sophgo/cv1800b.dtsi b/dts/upstream/src/riscv/sophgo/cv1800b.dtsi
index aec6401..165e9e3 100644
--- a/dts/upstream/src/riscv/sophgo/cv1800b.dtsi
+++ b/dts/upstream/src/riscv/sophgo/cv1800b.dtsi
@@ -3,120 +3,16 @@
* Copyright (C) 2023 Jisheng Zhang <jszhang@kernel.org>
*/
-#include <dt-bindings/interrupt-controller/irq.h>
+#include "cv18xx.dtsi"
/ {
compatible = "sophgo,cv1800b";
- #address-cells = <1>;
- #size-cells = <1>;
+};
- cpus: cpus {
- #address-cells = <1>;
- #size-cells = <0>;
- timebase-frequency = <25000000>;
-
- cpu0: cpu@0 {
- compatible = "thead,c906", "riscv";
- device_type = "cpu";
- reg = <0>;
- d-cache-block-size = <64>;
- d-cache-sets = <512>;
- d-cache-size = <65536>;
- i-cache-block-size = <64>;
- i-cache-sets = <128>;
- i-cache-size = <32768>;
- mmu-type = "riscv,sv39";
- riscv,isa = "rv64imafdc";
- riscv,isa-base = "rv64i";
- riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "zicntr", "zicsr",
- "zifencei", "zihpm";
-
- cpu0_intc: interrupt-controller {
- compatible = "riscv,cpu-intc";
- interrupt-controller;
- #interrupt-cells = <1>;
- };
- };
- };
-
- osc: oscillator {
- compatible = "fixed-clock";
- clock-output-names = "osc_25m";
- #clock-cells = <0>;
- };
-
- soc {
- compatible = "simple-bus";
- interrupt-parent = <&plic>;
- #address-cells = <1>;
- #size-cells = <1>;
- dma-noncoherent;
- ranges;
-
- uart0: serial@4140000 {
- compatible = "snps,dw-apb-uart";
- reg = <0x04140000 0x100>;
- interrupts = <44 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&osc>;
- reg-shift = <2>;
- reg-io-width = <4>;
- status = "disabled";
- };
-
- uart1: serial@4150000 {
- compatible = "snps,dw-apb-uart";
- reg = <0x04150000 0x100>;
- interrupts = <45 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&osc>;
- reg-shift = <2>;
- reg-io-width = <4>;
- status = "disabled";
- };
-
- uart2: serial@4160000 {
- compatible = "snps,dw-apb-uart";
- reg = <0x04160000 0x100>;
- interrupts = <46 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&osc>;
- reg-shift = <2>;
- reg-io-width = <4>;
- status = "disabled";
- };
-
- uart3: serial@4170000 {
- compatible = "snps,dw-apb-uart";
- reg = <0x04170000 0x100>;
- interrupts = <47 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&osc>;
- reg-shift = <2>;
- reg-io-width = <4>;
- status = "disabled";
- };
-
- uart4: serial@41c0000 {
- compatible = "snps,dw-apb-uart";
- reg = <0x041c0000 0x100>;
- interrupts = <48 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&osc>;
- reg-shift = <2>;
- reg-io-width = <4>;
- status = "disabled";
- };
-
- plic: interrupt-controller@70000000 {
- compatible = "sophgo,cv1800b-plic", "thead,c900-plic";
- reg = <0x70000000 0x4000000>;
- interrupts-extended = <&cpu0_intc 11>, <&cpu0_intc 9>;
- interrupt-controller;
- #address-cells = <0>;
- #interrupt-cells = <2>;
- riscv,ndev = <101>;
- };
+&plic {
+ compatible = "sophgo,cv1800b-plic", "thead,c900-plic";
+};
- clint: timer@74000000 {
- compatible = "sophgo,cv1800b-clint", "thead,c900-clint";
- reg = <0x74000000 0x10000>;
- interrupts-extended = <&cpu0_intc 3>, <&cpu0_intc 7>;
- };
- };
+&clint {
+ compatible = "sophgo,cv1800b-clint", "thead,c900-clint";
};
diff --git a/dts/upstream/src/riscv/sophgo/cv1812h-huashan-pi.dts b/dts/upstream/src/riscv/sophgo/cv1812h-huashan-pi.dts
new file mode 100644
index 0000000..aa361f3
--- /dev/null
+++ b/dts/upstream/src/riscv/sophgo/cv1812h-huashan-pi.dts
@@ -0,0 +1,48 @@
+// SPDX-License-Identifier: (GPL-2.0 OR MIT)
+/*
+ * Copyright (C) 2023 Inochi Amaoto <inochiama@outlook.com>
+ */
+
+/dts-v1/;
+
+#include "cv1812h.dtsi"
+
+/ {
+ model = "Huashan Pi";
+ compatible = "sophgo,huashan-pi", "sophgo,cv1812h";
+
+ aliases {
+ gpio0 = &gpio0;
+ gpio1 = &gpio1;
+ gpio2 = &gpio2;
+ gpio3 = &gpio3;
+ serial0 = &uart0;
+ serial1 = &uart1;
+ serial2 = &uart2;
+ serial3 = &uart3;
+ serial4 = &uart4;
+ };
+
+ chosen {
+ stdout-path = "serial0:115200n8";
+ };
+
+ reserved-memory {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges;
+
+ coprocessor_rtos: region@8fe00000 {
+ reg = <0x8fe00000 0x200000>;
+ no-map;
+ };
+ };
+};
+
+&osc {
+ clock-frequency = <25000000>;
+};
+
+&uart0 {
+ status = "okay";
+};
diff --git a/dts/upstream/src/riscv/sophgo/cv1812h.dtsi b/dts/upstream/src/riscv/sophgo/cv1812h.dtsi
new file mode 100644
index 0000000..3e7a942
--- /dev/null
+++ b/dts/upstream/src/riscv/sophgo/cv1812h.dtsi
@@ -0,0 +1,24 @@
+// SPDX-License-Identifier: (GPL-2.0 OR MIT)
+/*
+ * Copyright (C) 2023 Inochi Amaoto <inochiama@outlook.com>
+ */
+
+#include <dt-bindings/interrupt-controller/irq.h>
+#include "cv18xx.dtsi"
+
+/ {
+ compatible = "sophgo,cv1812h";
+
+ memory@80000000 {
+ device_type = "memory";
+ reg = <0x80000000 0x10000000>;
+ };
+};
+
+&plic {
+ compatible = "sophgo,cv1812h-plic", "thead,c900-plic";
+};
+
+&clint {
+ compatible = "sophgo,cv1812h-clint", "thead,c900-clint";
+};
diff --git a/dts/upstream/src/riscv/sophgo/cv18xx.dtsi b/dts/upstream/src/riscv/sophgo/cv18xx.dtsi
new file mode 100644
index 0000000..2d6f4a4
--- /dev/null
+++ b/dts/upstream/src/riscv/sophgo/cv18xx.dtsi
@@ -0,0 +1,192 @@
+// SPDX-License-Identifier: (GPL-2.0 OR MIT)
+/*
+ * Copyright (C) 2023 Jisheng Zhang <jszhang@kernel.org>
+ * Copyright (C) 2023 Inochi Amaoto <inochiama@outlook.com>
+ */
+
+#include <dt-bindings/interrupt-controller/irq.h>
+
+/ {
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ cpus: cpus {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ timebase-frequency = <25000000>;
+
+ cpu0: cpu@0 {
+ compatible = "thead,c906", "riscv";
+ device_type = "cpu";
+ reg = <0>;
+ d-cache-block-size = <64>;
+ d-cache-sets = <512>;
+ d-cache-size = <65536>;
+ i-cache-block-size = <64>;
+ i-cache-sets = <128>;
+ i-cache-size = <32768>;
+ mmu-type = "riscv,sv39";
+ riscv,isa = "rv64imafdc";
+ riscv,isa-base = "rv64i";
+ riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "zicntr", "zicsr",
+ "zifencei", "zihpm";
+
+ cpu0_intc: interrupt-controller {
+ compatible = "riscv,cpu-intc";
+ interrupt-controller;
+ #interrupt-cells = <1>;
+ };
+ };
+ };
+
+ osc: oscillator {
+ compatible = "fixed-clock";
+ clock-output-names = "osc_25m";
+ #clock-cells = <0>;
+ };
+
+ soc {
+ compatible = "simple-bus";
+ interrupt-parent = <&plic>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ dma-noncoherent;
+ ranges;
+
+ gpio0: gpio@3020000 {
+ compatible = "snps,dw-apb-gpio";
+ reg = <0x3020000 0x1000>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ porta: gpio-controller@0 {
+ compatible = "snps,dw-apb-gpio-port";
+ gpio-controller;
+ #gpio-cells = <2>;
+ ngpios = <32>;
+ reg = <0>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ interrupts = <60 IRQ_TYPE_LEVEL_HIGH>;
+ };
+ };
+
+ gpio1: gpio@3021000 {
+ compatible = "snps,dw-apb-gpio";
+ reg = <0x3021000 0x1000>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ portb: gpio-controller@0 {
+ compatible = "snps,dw-apb-gpio-port";
+ gpio-controller;
+ #gpio-cells = <2>;
+ ngpios = <32>;
+ reg = <0>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ interrupts = <61 IRQ_TYPE_LEVEL_HIGH>;
+ };
+ };
+
+ gpio2: gpio@3022000 {
+ compatible = "snps,dw-apb-gpio";
+ reg = <0x3022000 0x1000>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ portc: gpio-controller@0 {
+ compatible = "snps,dw-apb-gpio-port";
+ gpio-controller;
+ #gpio-cells = <2>;
+ ngpios = <32>;
+ reg = <0>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ interrupts = <62 IRQ_TYPE_LEVEL_HIGH>;
+ };
+ };
+
+ gpio3: gpio@3023000 {
+ compatible = "snps,dw-apb-gpio";
+ reg = <0x3023000 0x1000>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ portd: gpio-controller@0 {
+ compatible = "snps,dw-apb-gpio-port";
+ gpio-controller;
+ #gpio-cells = <2>;
+ ngpios = <32>;
+ reg = <0>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ interrupts = <63 IRQ_TYPE_LEVEL_HIGH>;
+ };
+ };
+
+ uart0: serial@4140000 {
+ compatible = "snps,dw-apb-uart";
+ reg = <0x04140000 0x100>;
+ interrupts = <44 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&osc>;
+ reg-shift = <2>;
+ reg-io-width = <4>;
+ status = "disabled";
+ };
+
+ uart1: serial@4150000 {
+ compatible = "snps,dw-apb-uart";
+ reg = <0x04150000 0x100>;
+ interrupts = <45 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&osc>;
+ reg-shift = <2>;
+ reg-io-width = <4>;
+ status = "disabled";
+ };
+
+ uart2: serial@4160000 {
+ compatible = "snps,dw-apb-uart";
+ reg = <0x04160000 0x100>;
+ interrupts = <46 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&osc>;
+ reg-shift = <2>;
+ reg-io-width = <4>;
+ status = "disabled";
+ };
+
+ uart3: serial@4170000 {
+ compatible = "snps,dw-apb-uart";
+ reg = <0x04170000 0x100>;
+ interrupts = <47 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&osc>;
+ reg-shift = <2>;
+ reg-io-width = <4>;
+ status = "disabled";
+ };
+
+ uart4: serial@41c0000 {
+ compatible = "snps,dw-apb-uart";
+ reg = <0x041c0000 0x100>;
+ interrupts = <48 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&osc>;
+ reg-shift = <2>;
+ reg-io-width = <4>;
+ status = "disabled";
+ };
+
+ plic: interrupt-controller@70000000 {
+ reg = <0x70000000 0x4000000>;
+ interrupts-extended = <&cpu0_intc 11>, <&cpu0_intc 9>;
+ interrupt-controller;
+ #address-cells = <0>;
+ #interrupt-cells = <2>;
+ riscv,ndev = <101>;
+ };
+
+ clint: timer@74000000 {
+ reg = <0x74000000 0x10000>;
+ interrupts-extended = <&cpu0_intc 3>, <&cpu0_intc 7>;
+ };
+ };
+};
diff --git a/dts/upstream/src/riscv/sophgo/sg2042.dtsi b/dts/upstream/src/riscv/sophgo/sg2042.dtsi
index 9325654..ead1cc3 100644
--- a/dts/upstream/src/riscv/sophgo/sg2042.dtsi
+++ b/dts/upstream/src/riscv/sophgo/sg2042.dtsi
@@ -93,144 +93,160 @@
<&cpu63_intc 3>;
};
- clint_mtimer0: timer@70ac000000 {
+ clint_mtimer0: timer@70ac004000 {
compatible = "sophgo,sg2042-aclint-mtimer", "thead,c900-aclint-mtimer";
- reg = <0x00000070 0xac000000 0x00000000 0x00007ff8>;
+ reg = <0x00000070 0xac004000 0x00000000 0x0000c000>;
+ reg-names = "mtimecmp";
interrupts-extended = <&cpu0_intc 7>,
<&cpu1_intc 7>,
<&cpu2_intc 7>,
<&cpu3_intc 7>;
};
- clint_mtimer1: timer@70ac010000 {
+ clint_mtimer1: timer@70ac014000 {
compatible = "sophgo,sg2042-aclint-mtimer", "thead,c900-aclint-mtimer";
- reg = <0x00000070 0xac010000 0x00000000 0x00007ff8>;
+ reg = <0x00000070 0xac014000 0x00000000 0x0000c000>;
+ reg-names = "mtimecmp";
interrupts-extended = <&cpu4_intc 7>,
<&cpu5_intc 7>,
<&cpu6_intc 7>,
<&cpu7_intc 7>;
};
- clint_mtimer2: timer@70ac020000 {
+ clint_mtimer2: timer@70ac024000 {
compatible = "sophgo,sg2042-aclint-mtimer", "thead,c900-aclint-mtimer";
- reg = <0x00000070 0xac020000 0x00000000 0x00007ff8>;
+ reg = <0x00000070 0xac024000 0x00000000 0x0000c000>;
+ reg-names = "mtimecmp";
interrupts-extended = <&cpu8_intc 7>,
<&cpu9_intc 7>,
<&cpu10_intc 7>,
<&cpu11_intc 7>;
};
- clint_mtimer3: timer@70ac030000 {
+ clint_mtimer3: timer@70ac034000 {
compatible = "sophgo,sg2042-aclint-mtimer", "thead,c900-aclint-mtimer";
- reg = <0x00000070 0xac030000 0x00000000 0x00007ff8>;
+ reg = <0x00000070 0xac034000 0x00000000 0x0000c000>;
+ reg-names = "mtimecmp";
interrupts-extended = <&cpu12_intc 7>,
<&cpu13_intc 7>,
<&cpu14_intc 7>,
<&cpu15_intc 7>;
};
- clint_mtimer4: timer@70ac040000 {
+ clint_mtimer4: timer@70ac044000 {
compatible = "sophgo,sg2042-aclint-mtimer", "thead,c900-aclint-mtimer";
- reg = <0x00000070 0xac040000 0x00000000 0x00007ff8>;
+ reg = <0x00000070 0xac044000 0x00000000 0x0000c000>;
+ reg-names = "mtimecmp";
interrupts-extended = <&cpu16_intc 7>,
<&cpu17_intc 7>,
<&cpu18_intc 7>,
<&cpu19_intc 7>;
};
- clint_mtimer5: timer@70ac050000 {
+ clint_mtimer5: timer@70ac054000 {
compatible = "sophgo,sg2042-aclint-mtimer", "thead,c900-aclint-mtimer";
- reg = <0x00000070 0xac050000 0x00000000 0x00007ff8>;
+ reg = <0x00000070 0xac054000 0x00000000 0x0000c000>;
+ reg-names = "mtimecmp";
interrupts-extended = <&cpu20_intc 7>,
<&cpu21_intc 7>,
<&cpu22_intc 7>,
<&cpu23_intc 7>;
};
- clint_mtimer6: timer@70ac060000 {
+ clint_mtimer6: timer@70ac064000 {
compatible = "sophgo,sg2042-aclint-mtimer", "thead,c900-aclint-mtimer";
- reg = <0x00000070 0xac060000 0x00000000 0x00007ff8>;
+ reg = <0x00000070 0xac064000 0x00000000 0x0000c000>;
+ reg-names = "mtimecmp";
interrupts-extended = <&cpu24_intc 7>,
<&cpu25_intc 7>,
<&cpu26_intc 7>,
<&cpu27_intc 7>;
};
- clint_mtimer7: timer@70ac070000 {
+ clint_mtimer7: timer@70ac074000 {
compatible = "sophgo,sg2042-aclint-mtimer", "thead,c900-aclint-mtimer";
- reg = <0x00000070 0xac070000 0x00000000 0x00007ff8>;
+ reg = <0x00000070 0xac074000 0x00000000 0x0000c000>;
+ reg-names = "mtimecmp";
interrupts-extended = <&cpu28_intc 7>,
<&cpu29_intc 7>,
<&cpu30_intc 7>,
<&cpu31_intc 7>;
};
- clint_mtimer8: timer@70ac080000 {
+ clint_mtimer8: timer@70ac084000 {
compatible = "sophgo,sg2042-aclint-mtimer", "thead,c900-aclint-mtimer";
- reg = <0x00000070 0xac080000 0x00000000 0x00007ff8>;
+ reg = <0x00000070 0xac084000 0x00000000 0x0000c000>;
+ reg-names = "mtimecmp";
interrupts-extended = <&cpu32_intc 7>,
<&cpu33_intc 7>,
<&cpu34_intc 7>,
<&cpu35_intc 7>;
};
- clint_mtimer9: timer@70ac090000 {
+ clint_mtimer9: timer@70ac094000 {
compatible = "sophgo,sg2042-aclint-mtimer", "thead,c900-aclint-mtimer";
- reg = <0x00000070 0xac090000 0x00000000 0x00007ff8>;
+ reg = <0x00000070 0xac094000 0x00000000 0x0000c000>;
+ reg-names = "mtimecmp";
interrupts-extended = <&cpu36_intc 7>,
<&cpu37_intc 7>,
<&cpu38_intc 7>,
<&cpu39_intc 7>;
};
- clint_mtimer10: timer@70ac0a0000 {
+ clint_mtimer10: timer@70ac0a4000 {
compatible = "sophgo,sg2042-aclint-mtimer", "thead,c900-aclint-mtimer";
- reg = <0x00000070 0xac0a0000 0x00000000 0x00007ff8>;
+ reg = <0x00000070 0xac0a4000 0x00000000 0x0000c000>;
+ reg-names = "mtimecmp";
interrupts-extended = <&cpu40_intc 7>,
<&cpu41_intc 7>,
<&cpu42_intc 7>,
<&cpu43_intc 7>;
};
- clint_mtimer11: timer@70ac0b0000 {
+ clint_mtimer11: timer@70ac0b4000 {
compatible = "sophgo,sg2042-aclint-mtimer", "thead,c900-aclint-mtimer";
- reg = <0x00000070 0xac0b0000 0x00000000 0x00007ff8>;
+ reg = <0x00000070 0xac0b4000 0x00000000 0x0000c000>;
+ reg-names = "mtimecmp";
interrupts-extended = <&cpu44_intc 7>,
<&cpu45_intc 7>,
<&cpu46_intc 7>,
<&cpu47_intc 7>;
};
- clint_mtimer12: timer@70ac0c0000 {
+ clint_mtimer12: timer@70ac0c4000 {
compatible = "sophgo,sg2042-aclint-mtimer", "thead,c900-aclint-mtimer";
- reg = <0x00000070 0xac0c0000 0x00000000 0x00007ff8>;
+ reg = <0x00000070 0xac0c4000 0x00000000 0x0000c000>;
+ reg-names = "mtimecmp";
interrupts-extended = <&cpu48_intc 7>,
<&cpu49_intc 7>,
<&cpu50_intc 7>,
<&cpu51_intc 7>;
};
- clint_mtimer13: timer@70ac0d0000 {
+ clint_mtimer13: timer@70ac0d4000 {
compatible = "sophgo,sg2042-aclint-mtimer", "thead,c900-aclint-mtimer";
- reg = <0x00000070 0xac0d0000 0x00000000 0x00007ff8>;
+ reg = <0x00000070 0xac0d4000 0x00000000 0x0000c000>;
+ reg-names = "mtimecmp";
interrupts-extended = <&cpu52_intc 7>,
<&cpu53_intc 7>,
<&cpu54_intc 7>,
<&cpu55_intc 7>;
};
- clint_mtimer14: timer@70ac0e0000 {
+ clint_mtimer14: timer@70ac0e4000 {
compatible = "sophgo,sg2042-aclint-mtimer", "thead,c900-aclint-mtimer";
- reg = <0x00000070 0xac0e0000 0x00000000 0x00007ff8>;
+ reg = <0x00000070 0xac0e4000 0x00000000 0x0000c000>;
+ reg-names = "mtimecmp";
interrupts-extended = <&cpu56_intc 7>,
<&cpu57_intc 7>,
<&cpu58_intc 7>,
<&cpu59_intc 7>;
};
- clint_mtimer15: timer@70ac0f0000 {
+ clint_mtimer15: timer@70ac0f4000 {
compatible = "sophgo,sg2042-aclint-mtimer", "thead,c900-aclint-mtimer";
- reg = <0x00000070 0xac0f0000 0x00000000 0x00007ff8>;
+ reg = <0x00000070 0xac0f4000 0x00000000 0x0000c000>;
+ reg-names = "mtimecmp";
interrupts-extended = <&cpu60_intc 7>,
<&cpu61_intc 7>,
<&cpu62_intc 7>,
diff --git a/dts/upstream/src/riscv/starfive/jh7100-common.dtsi b/dts/upstream/src/riscv/starfive/jh7100-common.dtsi
index b93ce35..42fb61c 100644
--- a/dts/upstream/src/riscv/starfive/jh7100-common.dtsi
+++ b/dts/upstream/src/riscv/starfive/jh7100-common.dtsi
@@ -12,6 +12,8 @@
/ {
aliases {
+ mmc0 = &sdio0;
+ mmc1 = &sdio1;
serial0 = &uart3;
};
@@ -39,6 +41,35 @@
label = "ack";
};
};
+
+ reserved-memory {
+ #address-cells = <2>;
+ #size-cells = <2>;
+ ranges;
+
+ dma-reserved@fa000000 {
+ reg = <0x0 0xfa000000 0x0 0x1000000>;
+ no-map;
+ };
+
+ linux,dma@107a000000 {
+ compatible = "shared-dma-pool";
+ reg = <0x10 0x7a000000 0x0 0x1000000>;
+ no-map;
+ linux,dma-default;
+ };
+ };
+
+ soc {
+ dma-ranges = <0x00 0x80000000 0x00 0x80000000 0x00 0x7a000000>,
+ <0x00 0xfa000000 0x10 0x7a000000 0x00 0x01000000>,
+ <0x00 0xfb000000 0x00 0xfb000000 0x07 0x85000000>;
+ };
+
+ wifi_pwrseq: wifi-pwrseq {
+ compatible = "mmc-pwrseq-simple";
+ reset-gpios = <&gpio 37 GPIO_ACTIVE_LOW>;
+ };
};
&gpio {
@@ -84,6 +115,78 @@
};
};
+ sdio0_pins: sdio0-0 {
+ clk-pins {
+ pinmux = <GPIOMUX(54, GPO_SDIO0_PAD_CCLK_OUT,
+ GPO_ENABLE, GPI_NONE)>;
+ bias-disable;
+ input-disable;
+ input-schmitt-disable;
+ };
+ sdio-pins {
+ pinmux = <GPIOMUX(55, GPO_LOW, GPO_DISABLE,
+ GPI_SDIO0_PAD_CARD_DETECT_N)>,
+ <GPIOMUX(53,
+ GPO_SDIO0_PAD_CCMD_OUT,
+ GPO_SDIO0_PAD_CCMD_OEN,
+ GPI_SDIO0_PAD_CCMD_IN)>,
+ <GPIOMUX(49,
+ GPO_SDIO0_PAD_CDATA_OUT_BIT0,
+ GPO_SDIO0_PAD_CDATA_OEN_BIT0,
+ GPI_SDIO0_PAD_CDATA_IN_BIT0)>,
+ <GPIOMUX(50,
+ GPO_SDIO0_PAD_CDATA_OUT_BIT1,
+ GPO_SDIO0_PAD_CDATA_OEN_BIT1,
+ GPI_SDIO0_PAD_CDATA_IN_BIT1)>,
+ <GPIOMUX(51,
+ GPO_SDIO0_PAD_CDATA_OUT_BIT2,
+ GPO_SDIO0_PAD_CDATA_OEN_BIT2,
+ GPI_SDIO0_PAD_CDATA_IN_BIT2)>,
+ <GPIOMUX(52,
+ GPO_SDIO0_PAD_CDATA_OUT_BIT3,
+ GPO_SDIO0_PAD_CDATA_OEN_BIT3,
+ GPI_SDIO0_PAD_CDATA_IN_BIT3)>;
+ bias-pull-up;
+ input-enable;
+ input-schmitt-enable;
+ };
+ };
+
+ sdio1_pins: sdio1-0 {
+ clk-pins {
+ pinmux = <GPIOMUX(33, GPO_SDIO1_PAD_CCLK_OUT,
+ GPO_ENABLE, GPI_NONE)>;
+ bias-disable;
+ input-disable;
+ input-schmitt-disable;
+ };
+ sdio-pins {
+ pinmux = <GPIOMUX(29,
+ GPO_SDIO1_PAD_CCMD_OUT,
+ GPO_SDIO1_PAD_CCMD_OEN,
+ GPI_SDIO1_PAD_CCMD_IN)>,
+ <GPIOMUX(36,
+ GPO_SDIO1_PAD_CDATA_OUT_BIT0,
+ GPO_SDIO1_PAD_CDATA_OEN_BIT0,
+ GPI_SDIO1_PAD_CDATA_IN_BIT0)>,
+ <GPIOMUX(30,
+ GPO_SDIO1_PAD_CDATA_OUT_BIT1,
+ GPO_SDIO1_PAD_CDATA_OEN_BIT1,
+ GPI_SDIO1_PAD_CDATA_IN_BIT1)>,
+ <GPIOMUX(34,
+ GPO_SDIO1_PAD_CDATA_OUT_BIT2,
+ GPO_SDIO1_PAD_CDATA_OEN_BIT2,
+ GPI_SDIO1_PAD_CDATA_IN_BIT2)>,
+ <GPIOMUX(31,
+ GPO_SDIO1_PAD_CDATA_OUT_BIT3,
+ GPO_SDIO1_PAD_CDATA_OEN_BIT3,
+ GPI_SDIO1_PAD_CDATA_IN_BIT3)>;
+ bias-pull-up;
+ input-enable;
+ input-schmitt-enable;
+ };
+ };
+
uart3_pins: uart3-0 {
rx-pins {
pinmux = <GPIOMUX(13, GPO_LOW, GPO_DISABLE,
@@ -154,6 +257,34 @@
clock-frequency = <27000000>;
};
+&sdio0 {
+ broken-cd;
+ bus-width = <4>;
+ cap-sd-highspeed;
+ pinctrl-names = "default";
+ pinctrl-0 = <&sdio0_pins>;
+ status = "okay";
+};
+
+&sdio1 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ bus-width = <4>;
+ cap-sd-highspeed;
+ cap-sdio-irq;
+ cap-power-off-card;
+ mmc-pwrseq = <&wifi_pwrseq>;
+ non-removable;
+ pinctrl-names = "default";
+ pinctrl-0 = <&sdio1_pins>;
+ status = "okay";
+
+ wifi@1 {
+ compatible = "brcm,bcm4329-fmac";
+ reg = <1>;
+ };
+};
+
&uart3 {
pinctrl-names = "default";
pinctrl-0 = <&uart3_pins>;
diff --git a/dts/upstream/src/riscv/starfive/jh7100.dtsi b/dts/upstream/src/riscv/starfive/jh7100.dtsi
index e68cafe..8bcf36d 100644
--- a/dts/upstream/src/riscv/starfive/jh7100.dtsi
+++ b/dts/upstream/src/riscv/starfive/jh7100.dtsi
@@ -32,6 +32,7 @@
i-tlb-sets = <1>;
i-tlb-size = <32>;
mmu-type = "riscv,sv39";
+ next-level-cache = <&ccache>;
riscv,isa = "rv64imafdc";
riscv,isa-base = "rv64i";
riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "zicntr", "zicsr",
@@ -60,6 +61,7 @@
i-tlb-sets = <1>;
i-tlb-size = <32>;
mmu-type = "riscv,sv39";
+ next-level-cache = <&ccache>;
riscv,isa = "rv64imafdc";
riscv,isa-base = "rv64i";
riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "zicntr", "zicsr",
@@ -94,14 +96,14 @@
thermal-sensors = <&sfctemp>;
trips {
- cpu_alert0 {
+ cpu-alert0 {
/* milliCelsius */
temperature = <75000>;
hysteresis = <2000>;
type = "passive";
};
- cpu_crit {
+ cpu-crit {
/* milliCelsius */
temperature = <90000>;
hysteresis = <2000>;
@@ -111,28 +113,28 @@
};
};
- osc_sys: osc_sys {
+ osc_sys: osc-sys {
compatible = "fixed-clock";
#clock-cells = <0>;
/* This value must be overridden by the board */
clock-frequency = <0>;
};
- osc_aud: osc_aud {
+ osc_aud: osc-aud {
compatible = "fixed-clock";
#clock-cells = <0>;
/* This value must be overridden by the board */
clock-frequency = <0>;
};
- gmac_rmii_ref: gmac_rmii_ref {
+ gmac_rmii_ref: gmac-rmii-ref {
compatible = "fixed-clock";
#clock-cells = <0>;
/* Should be overridden by the board when needed */
clock-frequency = <0>;
};
- gmac_gr_mii_rxclk: gmac_gr_mii_rxclk {
+ gmac_gr_mii_rxclk: gmac-gr-mii-rxclk {
compatible = "fixed-clock";
#clock-cells = <0>;
/* Should be overridden by the board when needed */
@@ -144,26 +146,64 @@
interrupt-parent = <&plic>;
#address-cells = <2>;
#size-cells = <2>;
+ dma-noncoherent;
ranges;
clint: clint@2000000 {
compatible = "starfive,jh7100-clint", "sifive,clint0";
reg = <0x0 0x2000000 0x0 0x10000>;
- interrupts-extended = <&cpu0_intc 3 &cpu0_intc 7
- &cpu1_intc 3 &cpu1_intc 7>;
+ interrupts-extended = <&cpu0_intc 3>, <&cpu0_intc 7>,
+ <&cpu1_intc 3>, <&cpu1_intc 7>;
};
+ ccache: cache-controller@2010000 {
+ compatible = "starfive,jh7100-ccache", "sifive,ccache0", "cache";
+ reg = <0x0 0x2010000 0x0 0x1000>;
+ interrupts = <128>, <130>, <131>, <129>;
+ cache-block-size = <64>;
+ cache-level = <2>;
+ cache-sets = <2048>;
+ cache-size = <2097152>;
+ cache-unified;
+ };
+
plic: interrupt-controller@c000000 {
compatible = "starfive,jh7100-plic", "sifive,plic-1.0.0";
reg = <0x0 0xc000000 0x0 0x4000000>;
- interrupts-extended = <&cpu0_intc 11 &cpu0_intc 9
- &cpu1_intc 11 &cpu1_intc 9>;
+ interrupts-extended = <&cpu0_intc 11>, <&cpu0_intc 9>,
+ <&cpu1_intc 11>, <&cpu1_intc 9>;
interrupt-controller;
#address-cells = <0>;
#interrupt-cells = <1>;
riscv,ndev = <133>;
};
+ sdio0: mmc@10000000 {
+ compatible = "snps,dw-mshc";
+ reg = <0x0 0x10000000 0x0 0x10000>;
+ clocks = <&clkgen JH7100_CLK_SDIO0_AHB>,
+ <&clkgen JH7100_CLK_SDIO0_CCLKINT_INV>;
+ clock-names = "biu", "ciu";
+ interrupts = <4>;
+ data-addr = <0>;
+ fifo-depth = <32>;
+ fifo-watermark-aligned;
+ status = "disabled";
+ };
+
+ sdio1: mmc@10010000 {
+ compatible = "snps,dw-mshc";
+ reg = <0x0 0x10010000 0x0 0x10000>;
+ clocks = <&clkgen JH7100_CLK_SDIO1_AHB>,
+ <&clkgen JH7100_CLK_SDIO1_CCLKINT_INV>;
+ clock-names = "biu", "ciu";
+ interrupts = <5>;
+ data-addr = <0>;
+ fifo-depth = <32>;
+ fifo-watermark-aligned;
+ status = "disabled";
+ };
+
clkgen: clock-controller@11800000 {
compatible = "starfive,jh7100-clkgen";
reg = <0x0 0x11800000 0x0 0x10000>;
diff --git a/dts/upstream/src/riscv/starfive/jh7110.dtsi b/dts/upstream/src/riscv/starfive/jh7110.dtsi
index 45213cd..74ed3b9 100644
--- a/dts/upstream/src/riscv/starfive/jh7110.dtsi
+++ b/dts/upstream/src/riscv/starfive/jh7110.dtsi
@@ -237,14 +237,14 @@
};
trips {
- cpu_alert0: cpu_alert0 {
+ cpu_alert0: cpu-alert0 {
/* milliCelsius */
temperature = <85000>;
hysteresis = <2000>;
type = "passive";
};
- cpu_crit {
+ cpu-crit {
/* milliCelsius */
temperature = <100000>;
hysteresis = <2000>;
diff --git a/dts/upstream/src/riscv/thead/th1520-beaglev-ahead.dts b/dts/upstream/src/riscv/thead/th1520-beaglev-ahead.dts
index 70e8042..d9b4de9 100644
--- a/dts/upstream/src/riscv/thead/th1520-beaglev-ahead.dts
+++ b/dts/upstream/src/riscv/thead/th1520-beaglev-ahead.dts
@@ -48,6 +48,10 @@
clock-frequency = <62500000>;
};
+&sdhci_clk {
+ clock-frequency = <198000000>;
+};
+
&uart_sclk {
clock-frequency = <100000000>;
};
@@ -56,6 +60,22 @@
status = "okay";
};
+&emmc {
+ bus-width = <8>;
+ max-frequency = <198000000>;
+ mmc-hs400-1_8v;
+ non-removable;
+ no-sdio;
+ no-sd;
+ status = "okay";
+};
+
+&sdio0 {
+ bus-width = <4>;
+ max-frequency = <198000000>;
+ status = "okay";
+};
+
&uart0 {
status = "okay";
};
diff --git a/dts/upstream/src/riscv/thead/th1520-lichee-module-4a.dtsi b/dts/upstream/src/riscv/thead/th1520-lichee-module-4a.dtsi
index a802ab1..1365d3a 100644
--- a/dts/upstream/src/riscv/thead/th1520-lichee-module-4a.dtsi
+++ b/dts/upstream/src/riscv/thead/th1520-lichee-module-4a.dtsi
@@ -29,6 +29,10 @@
clock-frequency = <62500000>;
};
+&sdhci_clk {
+ clock-frequency = <198000000>;
+};
+
&uart_sclk {
clock-frequency = <100000000>;
};
@@ -36,3 +40,19 @@
&dmac0 {
status = "okay";
};
+
+&emmc {
+ bus-width = <8>;
+ max-frequency = <198000000>;
+ mmc-hs400-1_8v;
+ non-removable;
+ no-sdio;
+ no-sd;
+ status = "okay";
+};
+
+&sdio0 {
+ bus-width = <4>;
+ max-frequency = <198000000>;
+ status = "okay";
+};
diff --git a/dts/upstream/src/riscv/thead/th1520.dtsi b/dts/upstream/src/riscv/thead/th1520.dtsi
index ba4d2c6..8b915e2 100644
--- a/dts/upstream/src/riscv/thead/th1520.dtsi
+++ b/dts/upstream/src/riscv/thead/th1520.dtsi
@@ -146,6 +146,13 @@
#clock-cells = <0>;
};
+ sdhci_clk: sdhci-clock {
+ compatible = "fixed-clock";
+ clock-frequency = <198000000>;
+ clock-output-names = "sdhci_clk";
+ #clock-cells = <0>;
+ };
+
soc {
compatible = "simple-bus";
interrupt-parent = <&plic>;
@@ -304,6 +311,33 @@
status = "disabled";
};
+ emmc: mmc@ffe7080000 {
+ compatible = "thead,th1520-dwcmshc";
+ reg = <0xff 0xe7080000 0x0 0x10000>;
+ interrupts = <62 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&sdhci_clk>;
+ clock-names = "core";
+ status = "disabled";
+ };
+
+ sdio0: mmc@ffe7090000 {
+ compatible = "thead,th1520-dwcmshc";
+ reg = <0xff 0xe7090000 0x0 0x10000>;
+ interrupts = <64 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&sdhci_clk>;
+ clock-names = "core";
+ status = "disabled";
+ };
+
+ sdio1: mmc@ffe70a0000 {
+ compatible = "thead,th1520-dwcmshc";
+ reg = <0xff 0xe70a0000 0x0 0x10000>;
+ interrupts = <71 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&sdhci_clk>;
+ clock-names = "core";
+ status = "disabled";
+ };
+
timer0: timer@ffefc32000 {
compatible = "snps,dw-apb-timer";
reg = <0xff 0xefc32000 0x0 0x14>;
diff --git a/env/Kconfig b/env/Kconfig
index 7885c8b..1f8e90af 100644
--- a/env/Kconfig
+++ b/env/Kconfig
@@ -472,7 +472,7 @@
string "Device and partition for where to store the environemt in FAT"
depends on ENV_IS_IN_FAT
default "0:1" if TI_COMMON_CMD_OPTIONS
- default "0:auto" if ARCH_ZYNQ || ARCH_ZYNQMP || ARCH_VERSAL
+ default "0:auto" if ARCH_ZYNQ || ARCH_ZYNQMP || ARCH_VERSAL || ARCH_VERSAL_NET
default ":auto" if ARCH_SUNXI
default "0" if ARCH_AT91
help
diff --git a/fs/ext4/ext4_common.c b/fs/ext4/ext4_common.c
index 365c514..2ff0dca 100644
--- a/fs/ext4/ext4_common.c
+++ b/fs/ext4/ext4_common.c
@@ -765,11 +765,6 @@
struct ext2_inode *first_inode = NULL;
struct ext2_inode temp_inode;
- if (*dirname != '/') {
- printf("Please supply Absolute path\n");
- return -1;
- }
-
/* TODO: input validation make equivalent to linux */
depth_dirname = zalloc(strlen(dirname) + 1);
if (!depth_dirname)
diff --git a/fs/ext4/ext4_journal.c b/fs/ext4/ext4_journal.c
index 1a340b4..e80f797 100644
--- a/fs/ext4/ext4_journal.c
+++ b/fs/ext4/ext4_journal.c
@@ -430,7 +430,7 @@
printf("Recovery required\n");
} else {
if (recovery_flag == RECOVER)
- printf("File System is consistent\n");
+ log_debug("File System is consistent\n");
goto end;
}
diff --git a/fs/ext4/ext4_write.c b/fs/ext4/ext4_write.c
index ea4c5d4..d057f6b 100644
--- a/fs/ext4/ext4_write.c
+++ b/fs/ext4/ext4_write.c
@@ -847,6 +847,7 @@
{
int ret = 0;
struct ext2_inode *file_inode = NULL;
+ struct ext2_inode *existing_file_inode = NULL;
unsigned char *inode_buffer = NULL;
int parent_inodeno;
int inodeno;
@@ -900,6 +901,15 @@
/* check if the filename is already present in root */
existing_file_inodeno = ext4fs_filename_unlink(filename);
if (existing_file_inodeno != -1) {
+ existing_file_inode = (struct ext2_inode *)zalloc(fs->inodesz);
+ if (!existing_file_inode)
+ goto fail;
+ ret = ext4fs_iget(existing_file_inodeno, existing_file_inode);
+ if (ret) {
+ free(existing_file_inode);
+ goto fail;
+ }
+
ret = ext4fs_delete_file(existing_file_inodeno);
fs->first_pass_bbmap = 0;
fs->curr_blkno = 0;
@@ -948,9 +958,15 @@
sizebytes = 0;
}
} else {
- file_inode->mode = cpu_to_le16(S_IFREG | S_IRWXU | S_IRGRP |
- S_IROTH | S_IXGRP | S_IXOTH);
+ if (existing_file_inode) {
+ file_inode->mode = existing_file_inode->mode;
+ } else {
+ file_inode->mode = cpu_to_le16(S_IFREG | S_IRWXU | S_IRGRP |
+ S_IROTH | S_IXGRP | S_IXOTH);
+ }
}
+ if (existing_file_inode)
+ free(existing_file_inode);
/* ToDo: Update correct time */
file_inode->mtime = cpu_to_le32(timestamp);
file_inode->atime = cpu_to_le32(timestamp);
diff --git a/include/acpi/acpi_table.h b/include/acpi/acpi_table.h
index e67562e..15fd61a 100644
--- a/include/acpi/acpi_table.h
+++ b/include/acpi/acpi_table.h
@@ -57,17 +57,41 @@
char oem_id[6]; /* OEM identification */
char oem_table_id[8]; /* OEM table identification */
u32 oem_revision; /* OEM revision number */
- char aslc_id[4]; /* ASL compiler vendor ID */
- u32 aslc_revision; /* ASL compiler revision number */
+ char creator_id[4]; /* ASL compiler vendor ID */
+ u32 creator_revision; /* ASL compiler revision number */
};
+/**
+ * struct acpi_gen_regaddr - generic address structure (GAS)
+ */
struct acpi_gen_regaddr {
- u8 space_id; /* Address space ID */
- u8 bit_width; /* Register size in bits */
- u8 bit_offset; /* Register bit offset */
- u8 access_size; /* Access size */
- u32 addrl; /* Register address, low 32 bits */
- u32 addrh; /* Register address, high 32 bits */
+ /**
+ * @space_id: address space ID
+ *
+ * See table "Operation Region Address Space Identifiers" in the ACPI
+ * specification.
+ */
+ u8 space_id;
+ /** @bit_width: size in bits of the register */
+ u8 bit_width;
+ /** @bit_offset: bit offset of the register */
+ u8 bit_offset;
+ /**
+ * @access_size: access size
+ *
+ * * 0 - undefined
+ * * 1 - byte access
+ * * 2 - word (2 bytes) access
+ * * 3 - Dword (4 bytes) access
+ * * 4 - Qword (8 bytes) access
+ *
+ * See ACPI_ACCESS_SIZE_*_ACCESS macros.
+ */
+ u8 access_size;
+ /** @addrl: register address, low 32 bits */
+ u32 addrl;
+ /** @addrh: register address, high 32 bits */
+ u32 addrh;
};
/* A maximum number of 32 ACPI tables ought to be enough for now */
@@ -85,15 +109,26 @@
u64 entry[MAX_ACPI_TABLES];
};
-/* HPET timers */
-struct __packed acpi_hpet {
+/**
+ * struct acpi_hpet: High Precision Event Timers (HETP)
+ *
+ * The structure is defined in the
+ * "IA-PC HPET (High Precision Event Timers) Specification", rev 1.0a, Oct 2004
+ */
+struct acpi_hpet {
+ /** @header: table header */
struct acpi_table_header header;
+ /** @id hardware ID of Event Timer Block */
u32 id;
+ /** @addr: address of Event Timer Block */
struct acpi_gen_regaddr addr;
+ /** @number: HPET sequence number */
u8 number;
+ /** @min_tick: minimum clock ticks without lost interrupts */
u16 min_tick;
+ /** @attributes: page protection and OEM atttribute */
u8 attributes;
-};
+} __packed;
struct __packed acpi_tpm2 {
struct acpi_table_header header;
@@ -364,7 +399,7 @@
* This holds information about the Generic Interrupt Controller (GIC) CPU
* interface. See ACPI Spec v6.3 section 5.2.12.14
*/
-struct __packed acpi_madr_gicc {
+struct acpi_madr_gicc {
u8 type;
u8 length;
u16 reserved;
@@ -383,7 +418,7 @@
u8 efficiency;
u8 reserved2;
u16 spi_overflow_irq;
-};
+} __packed;
/**
* struct __packed acpi_madr_gicc - GIC distributor (type 0xc)
@@ -391,7 +426,7 @@
* This holds information about the Generic Interrupt Controller (GIC)
* Distributor interface. See ACPI Spec v6.3 section 5.2.12.15
*/
-struct __packed acpi_madr_gicd {
+struct acpi_madr_gicd {
u8 type;
u8 length;
u16 reserved;
@@ -400,7 +435,7 @@
u32 reserved2;
u8 gic_version;
u8 reserved3[3];
-};
+} __packed;
/* MCFG (PCI Express MMIO config space BAR description table) */
struct acpi_mcfg {
@@ -653,7 +688,7 @@
*
* See ACPI Spec v6.3 section 5.2.24 for details
*/
-struct __packed acpi_gtdt {
+struct acpi_gtdt {
struct acpi_table_header header;
u64 cnt_ctrl_base;
u32 reserved0;
@@ -670,7 +705,7 @@
u32 plat_timer_offset;
u32 virt_el2_gsiv;
u32 virt_el2_flags;
-};
+} __packed;
/**
* struct acpi_bgrt - Boot Graphics Resource Table (BGRT)
@@ -680,7 +715,7 @@
*
* See ACPI Spec v6.3 section 5.2.22 for details
*/
-struct __packed acpi_bgrt {
+struct acpi_bgrt {
struct acpi_table_header header;
u16 version;
u8 status;
@@ -688,7 +723,7 @@
u64 addr;
u32 offset_x;
u32 offset_y;
-};
+} __packed;
/* Types for PPTT */
#define ACPI_PPTT_TYPE_PROC 0
@@ -709,22 +744,22 @@
*
* See ACPI Spec v6.3 section 5.2.29 for details
*/
-struct __packed acpi_pptt_header {
+struct acpi_pptt_header {
u8 type; /* ACPI_PPTT_TYPE_... */
u8 length;
u16 reserved;
-};
+} __packed;
/**
* struct acpi_pptt_proc - a processor as described by PPTT
*/
-struct __packed acpi_pptt_proc {
+struct acpi_pptt_proc {
struct acpi_pptt_header hdr;
u32 flags;
u32 parent;
u32 proc_id;
u32 num_resources;
-};
+} __packed;
/* Cache flags for acpi_pptt_cache */
#define ACPI_PPTT_SIZE_VALID BIT(0)
@@ -751,7 +786,7 @@
/**
* struct acpi_pptt_cache - a cache as described by PPTT
*/
-struct __packed acpi_pptt_cache {
+struct acpi_pptt_cache {
struct acpi_pptt_header hdr;
u32 flags;
u32 next_cache_level;
@@ -760,7 +795,7 @@
u8 assoc;
u8 attributes;
u16 line_size;
-};
+} __packed;
/* Tables defined/reserved by ACPI and generated by U-Boot */
enum acpi_tables {
@@ -829,16 +864,6 @@
const char *device_path);
/**
- * acpi_fill_header() - Set up a new table header
- *
- * This sets all fields except length, revision, checksum and aslc_revision
- *
- * @header: ACPI header to update
- * @signature: Table signature to use (4 characters)
- */
-void acpi_fill_header(struct acpi_table_header *header, char *signature);
-
-/**
* acpi_align() - Align the ACPI output pointer to a 16-byte boundary
*
* @ctx: ACPI context
diff --git a/include/asm-generic/sections.h b/include/asm-generic/sections.h
index 1e1657a..b6bca53 100644
--- a/include/asm-generic/sections.h
+++ b/include/asm-generic/sections.h
@@ -34,6 +34,9 @@
/* Start and end of .ctors section - used for constructor calls. */
extern char __ctors_start[], __ctors_end[];
+extern char __efi_runtime_rel_start[], __efi_runtime_rel_stop[];
+extern char __efi_runtime_start[], __efi_runtime_stop[];
+
/* function descriptor handling (if any). Override
* in asm/sections.h */
#ifndef dereference_function_descriptor
diff --git a/include/bootm.h b/include/bootm.h
index 9e0f8d6..6983375 100644
--- a/include/bootm.h
+++ b/include/bootm.h
@@ -273,21 +273,24 @@
int bootm_process_cmdline_env(int flags);
/**
- * zboot_start() - Boot a zimage
+ * zboot_run() - Run through the various steps to boot a zimage
*
* Boot a zimage, given the component parts
*
* @addr: Address where the bzImage is moved before booting, either
* BZIMAGE_LOAD_ADDR or ZIMAGE_LOAD_ADDR
- * @base: Pointer to the boot parameters, typically at address
- * DEFAULT_SETUP_BASE
+ * @size: Size of bzImage, or 0 to detect this
* @initrd: Address of the initial ramdisk, or 0 if none
* @initrd_size: Size of the initial ramdisk, or 0 if none
- * @cmdline: Command line to use for booting
+ * @base_addr: If non-zero, this indicates that the boot parameters have already
+ * been loaded by the caller to this address, so the load_zimage() call
+ * in zboot_load() will be skipped when booting
+ * @cmdline: If non-NULL, the environment variable containing the command line
+ * to use for booting
* Return: -EFAULT on error (normally it does not return)
*/
-int zboot_start(ulong addr, ulong size, ulong initrd, ulong initrd_size,
- ulong base, char *cmdline);
+int zboot_run(ulong addr, ulong size, ulong initrd, ulong initrd_size,
+ ulong base, char *cmdline);
/*
* zimage_get_kernel_version() - Get the version string from a kernel
@@ -314,7 +317,7 @@
* bootm_boot_start() - Boot an image at the given address
*
* @addr: Image address
- * @cmdline: Command line to set
+ * @cmdline: Command line to set, NULL for default
*/
int bootm_boot_start(ulong addr, const char *cmdline);
diff --git a/include/charset.h b/include/charset.h
index f1050c9..348bad5 100644
--- a/include/charset.h
+++ b/include/charset.h
@@ -16,7 +16,7 @@
/*
* codepage_437 - Unicode to codepage 437 translation table
*/
-extern const u16 codepage_437[128];
+extern const u16 codepage_437[160];
/**
* console_read_unicode() - read Unicode code point from console
diff --git a/include/configs/jaguar_rk3588.h b/include/configs/jaguar_rk3588.h
new file mode 100644
index 0000000..843028c
--- /dev/null
+++ b/include/configs/jaguar_rk3588.h
@@ -0,0 +1,15 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (c) 2023 Theobroma Systems Design und Consulting GmbH
+ */
+
+#ifndef __JAGUAR_RK3588_H
+#define __JAGUAR_RK3588_H
+
+#define ROCKCHIP_DEVICE_SETTINGS \
+ "stdout=serial,vidconsole\0" \
+ "stderr=serial,vidconsole\0"
+
+#include <configs/rk3588_common.h>
+
+#endif /* __JAGUAR_RK3588_H */
diff --git a/include/configs/jethub.h b/include/configs/jethub.h
index e22db49..2c44bfc 100644
--- a/include/configs/jethub.h
+++ b/include/configs/jethub.h
@@ -11,7 +11,7 @@
#if defined(CONFIG_MESON_AXG)
#define BOOTENV_DEV_RESCUE(devtypeu, devtypel, instance) \
"bootcmd_rescue=" \
- "if gpio input 10; then " \
+ "if gpio input periphs-banks10; then " \
"run bootcmd_mmc0; " \
"run bootcmd_usb0;" \
"fi;\0"
diff --git a/include/configs/meson64.h b/include/configs/meson64.h
index efab9a6..65fa5f3 100644
--- a/include/configs/meson64.h
+++ b/include/configs/meson64.h
@@ -120,6 +120,12 @@
#include <config_distro_bootcmd.h>
+#ifdef CONFIG_OF_UPSTREAM
+#define FDTFILE_NAME CONFIG_DEFAULT_DEVICE_TREE ".dtb"
+#else
+#define FDTFILE_NAME "amlogic/" CONFIG_DEFAULT_DEVICE_TREE ".dtb"
+#endif
+
#ifndef CFG_EXTRA_ENV_SETTINGS
#define CFG_EXTRA_ENV_SETTINGS \
"stdin=" STDIN_CFG "\0" \
@@ -133,7 +139,7 @@
"pxefile_addr_r=" PXEFILE_ADDR_R "\0" \
"fdtoverlay_addr_r=" FDTOVERLAY_ADDR_R "\0" \
"ramdisk_addr_r=" RAMDISK_ADDR_R "\0" \
- "fdtfile=amlogic/" CONFIG_DEFAULT_DEVICE_TREE ".dtb\0" \
+ "fdtfile=" FDTFILE_NAME "\0" \
"dfu_alt_info=fitimage ram " KERNEL_ADDR_R " 0x4000000 \0" \
BOOTENV
#endif
diff --git a/include/configs/phycore_imx8mp.h b/include/configs/phycore_imx8mp.h
index 11a17be..206c4d5 100644
--- a/include/configs/phycore_imx8mp.h
+++ b/include/configs/phycore_imx8mp.h
@@ -13,49 +13,6 @@
#define CFG_SYS_UBOOT_BASE \
(QSPI0_AMBA_BASE + CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR * 512)
-#define CFG_EXTRA_ENV_SETTINGS \
- "image=Image\0" \
- "console=ttymxc0,115200\0" \
- "fdt_addr=0x48000000\0" \
- "fdt_file=" CONFIG_DEFAULT_FDT_FILE "\0" \
- "ip_dyn=yes\0" \
- "dofastboot=0\0" \
- "fastboot_raw_partition_bootloader=64 8128\0" \
- "fastboot_raw_partition_all=0 4194304\0" \
- "emmc_dev=2\0" \
- "sd_dev=1\0" \
- "mmcdev=" __stringify(CONFIG_SYS_MMC_ENV_DEV) "\0" \
- "mmcpart=1\0" \
- "mmcroot=2\0" \
- "mmcautodetect=yes\0" \
- "mmcargs=setenv bootargs console=${console} " \
- "root=/dev/mmcblk${mmcdev}p${mmcroot} rootwait rw\0" \
- "loadimage=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${image}\0" \
- "loadfdt=fatload mmc ${mmcdev}:${mmcpart} ${fdt_addr} ${fdt_file}\0" \
- "mmcboot=echo Booting from mmc ...; " \
- "run mmcargs; " \
- "if run loadfdt; then " \
- "booti ${loadaddr} - ${fdt_addr}; " \
- "else " \
- "echo WARN: Cannot load the DT; " \
- "fi;\0 " \
- "nfsroot=/nfs\0" \
- "netargs=setenv bootargs console=${console} root=/dev/nfs ip=dhcp " \
- "nfsroot=${serverip}:${nfsroot},v3,tcp\0" \
- "netboot=echo Booting from net ...; " \
- "run netargs; " \
- "if test ${ip_dyn} = yes; then " \
- "setenv get_cmd dhcp; " \
- "else " \
- "setenv get_cmd tftp; " \
- "fi; " \
- "${get_cmd} ${loadaddr} ${image}; " \
- "if ${get_cmd} ${fdt_addr} ${fdt_file}; then " \
- "booti ${loadaddr} - ${fdt_addr}; " \
- "else " \
- "echo WARN: Cannot load the DT; " \
- "fi;\0" \
-
/* Link Definitions */
#define CFG_SYS_INIT_RAM_ADDR 0x40000000
diff --git a/include/configs/rk3036_common.h b/include/configs/rk3036_common.h
index c2abd14..0bf9e8b 100644
--- a/include/configs/rk3036_common.h
+++ b/include/configs/rk3036_common.h
@@ -5,7 +5,6 @@
#ifndef __CONFIG_RK3036_COMMON_H
#define __CONFIG_RK3036_COMMON_H
-#include <asm/arch-rockchip/hardware.h>
#include "rockchip-common.h"
#define CFG_SYS_HZ_CLOCK 24000000
diff --git a/include/configs/rk3066_common.h b/include/configs/rk3066_common.h
index d70c8f7..6a3b690 100644
--- a/include/configs/rk3066_common.h
+++ b/include/configs/rk3066_common.h
@@ -6,7 +6,6 @@
#ifndef __CONFIG_RK3066_COMMON_H
#define __CONFIG_RK3066_COMMON_H
-#include <asm/arch-rockchip/hardware.h>
#include "rockchip-common.h"
#define CFG_IRAM_BASE 0x10080000
diff --git a/include/configs/rk3188_common.h b/include/configs/rk3188_common.h
index a8cee1e..98f2c25 100644
--- a/include/configs/rk3188_common.h
+++ b/include/configs/rk3188_common.h
@@ -6,7 +6,6 @@
#ifndef __CONFIG_RK3188_COMMON_H
#define __CONFIG_RK3188_COMMON_H
-#include <asm/arch-rockchip/hardware.h>
#include "rockchip-common.h"
#define CFG_IRAM_BASE 0x10080000
diff --git a/include/configs/rk322x_common.h b/include/configs/rk322x_common.h
index 15f77df..bab4ca0 100644
--- a/include/configs/rk322x_common.h
+++ b/include/configs/rk322x_common.h
@@ -5,7 +5,6 @@
#ifndef __CONFIG_RK322X_COMMON_H
#define __CONFIG_RK322X_COMMON_H
-#include <asm/arch-rockchip/hardware.h>
#include "rockchip-common.h"
#define CFG_SYS_HZ_CLOCK 24000000
diff --git a/include/configs/rk3288_common.h b/include/configs/rk3288_common.h
index 3063076..0c449e3 100644
--- a/include/configs/rk3288_common.h
+++ b/include/configs/rk3288_common.h
@@ -6,7 +6,6 @@
#ifndef __CONFIG_RK3288_COMMON_H
#define __CONFIG_RK3288_COMMON_H
-#include <asm/arch-rockchip/hardware.h>
#include "rockchip-common.h"
#define CFG_SYS_HZ_CLOCK 24000000
diff --git a/include/configs/rk3368_common.h b/include/configs/rk3368_common.h
index ccb5369..d488f8d 100644
--- a/include/configs/rk3368_common.h
+++ b/include/configs/rk3368_common.h
@@ -8,7 +8,6 @@
#include "rockchip-common.h"
-#include <asm/arch-rockchip/hardware.h>
#include <linux/sizes.h>
#define CFG_SYS_SDRAM_BASE 0
diff --git a/include/configs/rk3399_common.h b/include/configs/rk3399_common.h
index 96ba19c..4e75771 100644
--- a/include/configs/rk3399_common.h
+++ b/include/configs/rk3399_common.h
@@ -13,22 +13,6 @@
#define CFG_SYS_SDRAM_BASE 0
#define SDRAM_MAX_SIZE 0xf8000000
-#define ROCKPI_4B_IDBLOADER_IMAGE_GUID \
- EFI_GUID(0x02f4d760, 0xcfd5, 0x43bd, 0x8e, 0x2d, \
- 0xa4, 0x2a, 0xcb, 0x33, 0xc6, 0x60)
-
-#define ROCKPI_4B_UBOOT_IMAGE_GUID \
- EFI_GUID(0x4ce292da, 0x1dd8, 0x428d, 0xa1, 0xc2, \
- 0x77, 0x74, 0x3e, 0xf8, 0xb9, 0x6e)
-
-#define ROCKPI_4C_IDBLOADER_IMAGE_GUID \
- EFI_GUID(0xfd68510c, 0x12d3, 0x4f0a, 0xb8, 0xd3, \
- 0xd8, 0x79, 0xe1, 0xd3, 0xa5, 0x40)
-
-#define ROCKPI_4C_UBOOT_IMAGE_GUID \
- EFI_GUID(0xb81fb4ae, 0xe4f3, 0x471b, 0x99, 0xb4, \
- 0x0b, 0x3d, 0xa5, 0x49, 0xce, 0x13)
-
#ifndef CONFIG_SPL_BUILD
#define ENV_MEM_LAYOUT_SETTINGS \
diff --git a/include/configs/rockpi4-rk3399.h b/include/configs/rockpi4-rk3399.h
new file mode 100644
index 0000000..1936e06
--- /dev/null
+++ b/include/configs/rockpi4-rk3399.h
@@ -0,0 +1,32 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * (C) Copyright 2016 Rockchip Electronics Co., Ltd
+ */
+
+#ifndef __ROCKPI4_RK3399_H
+#define __ROCKPI4_RK3399_H
+
+#define ROCKPI_4B_IDBLOADER_IMAGE_GUID \
+ EFI_GUID(0x02f4d760, 0xcfd5, 0x43bd, 0x8e, 0x2d, \
+ 0xa4, 0x2a, 0xcb, 0x33, 0xc6, 0x60)
+
+#define ROCKPI_4B_UBOOT_IMAGE_GUID \
+ EFI_GUID(0x4ce292da, 0x1dd8, 0x428d, 0xa1, 0xc2, \
+ 0x77, 0x74, 0x3e, 0xf8, 0xb9, 0x6e)
+
+#define ROCKPI_4C_IDBLOADER_IMAGE_GUID \
+ EFI_GUID(0xfd68510c, 0x12d3, 0x4f0a, 0xb8, 0xd3, \
+ 0xd8, 0x79, 0xe1, 0xd3, 0xa5, 0x40)
+
+#define ROCKPI_4C_UBOOT_IMAGE_GUID \
+ EFI_GUID(0xb81fb4ae, 0xe4f3, 0x471b, 0x99, 0xb4, \
+ 0x0b, 0x3d, 0xa5, 0x49, 0xce, 0x13)
+
+#define ROCKCHIP_DEVICE_SETTINGS \
+ "stdin=serial,usbkbd\0" \
+ "stdout=serial,vidconsole\0" \
+ "stderr=serial,vidconsole\0"
+
+#include <configs/rk3399_common.h>
+
+#endif
diff --git a/include/configs/rv1108_common.h b/include/configs/rv1108_common.h
index 3bf70a0..ff28236 100644
--- a/include/configs/rv1108_common.h
+++ b/include/configs/rv1108_common.h
@@ -5,7 +5,6 @@
#ifndef __CONFIG_RV1108_COMMON_H
#define __CONFIG_RV1108_COMMON_H
-#include <asm/arch-rockchip/hardware.h>
#include "rockchip-common.h"
#define CFG_IRAM_BASE 0x10080000
diff --git a/include/configs/sama7g54_curiosity.h b/include/configs/sama7g54_curiosity.h
new file mode 100644
index 0000000..fe47236
--- /dev/null
+++ b/include/configs/sama7g54_curiosity.h
@@ -0,0 +1,17 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Configuration file for the SAMA7G54 CURIOSITY board.
+ *
+ * Copyright (C) 2024 Microchip Technology Inc. and its subsidiaries
+ *
+ * Author: Mihai Sain <mihai.sain@microchip.com>
+ *
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+#define CFG_SYS_AT91_SLOW_CLOCK 32768
+#define CFG_SYS_AT91_MAIN_CLOCK 24000000
+
+#endif
diff --git a/include/configs/socfpga_agilex5_socdk.h b/include/configs/socfpga_agilex5_socdk.h
new file mode 100644
index 0000000..b5b5bd7
--- /dev/null
+++ b/include/configs/socfpga_agilex5_socdk.h
@@ -0,0 +1,12 @@
+/* SPDX-License-Identifier: GPL-2.0
+ *
+ * Copyright (C) 2024 Intel Corporation <www.intel.com>
+ *
+ */
+
+#ifndef __CONFIG_SOCFGPA_AGILEX5_H__
+#define __CONFIG_SOCFGPA_AGILEX5_H__
+
+#include <configs/socfpga_soc64_common.h>
+
+#endif /* __CONFIG_SOCFGPA_AGILEX5_H__ */
diff --git a/include/configs/socfpga_soc64_common.h b/include/configs/socfpga_soc64_common.h
index 820372c..b7ee1db 100644
--- a/include/configs/socfpga_soc64_common.h
+++ b/include/configs/socfpga_soc64_common.h
@@ -1,6 +1,6 @@
/* SPDX-License-Identifier: GPL-2.0
*
- * Copyright (C) 2017-2019 Intel Corporation <www.intel.com>
+ * Copyright (C) 2017-2024 Intel Corporation <www.intel.com>
*
*/
@@ -26,8 +26,13 @@
/*
* U-Boot run time memory configurations
*/
+#if IS_ENABLED(CONFIG_TARGET_SOCFPGA_AGILEX5)
+#define CFG_SYS_INIT_RAM_ADDR 0x0
+#define CFG_SYS_INIT_RAM_SIZE 0x80000
+#else
#define CFG_SYS_INIT_RAM_ADDR 0xFFE00000
#define CFG_SYS_INIT_RAM_SIZE 0x40000
+#endif
/*
* U-Boot environment configurations
@@ -36,9 +41,121 @@
/*
* Environment variable
*/
+#if IS_ENABLED(CONFIG_DISTRO_DEFAULTS)
+#if IS_ENABLED(CONFIG_CMD_MMC)
+#define BOOT_TARGET_DEVICES_MMC(func) func(MMC, mmc, 0)
+#else
+#define BOOT_TARGET_DEVICES_MMC(func)
+#endif
+
+#if IS_ENABLED(CONFIG_CMD_SF)
+#define BOOT_TARGET_DEVICES_QSPI(func) func(QSPI, qspi, na)
+#else
+#define BOOT_TARGET_DEVICES_QSPI(func)
+#endif
+
+#define BOOTENV_DEV_QSPI(devtypeu, devtypel, instance) \
+ "bootcmd_qspi=ubi detach; sf probe && " \
+ "if ubi part root && ubi readvol ${scriptaddr} script; " \
+ "then echo QSPI: Running script from UBIFS; " \
+ "elif sf read ${scriptaddr} ${qspiscriptaddr} ${scriptsize}; " \
+ "then echo QSPI: Running script from JFFS2; fi; " \
+ "echo QSPI: Trying to boot script at ${scriptaddr} && " \
+ "source ${scriptaddr}; " \
+ "echo QSPI: SCRIPT FAILED: continuing...; ubi detach;\0"
+
+#define BOOTENV_DEV_NAME_QSPI(devtypeu, devtypel, instance) \
+ "qspi "
+
+#define BOOT_TARGET_DEVICES(func) \
+ BOOT_TARGET_DEVICES_MMC(func) \
+ BOOT_TARGET_DEVICES_QSPI(func)
+
+#include <config_distro_bootcmd.h>
+
+#if IS_ENABLED(CONFIG_TARGET_SOCFPGA_AGILEX5)
+
#define CFG_EXTRA_ENV_SETTINGS \
+ "kernel_addr_r=0x82000000\0" \
+ "fdt_addr_r=0x86000000\0" \
+ "qspiscriptaddr=0x02110000\0" \
+ "scriptsize=0x00010000\0" \
+ "qspibootimageaddr=0x02120000\0" \
+ "bootimagesize=0x03200000\0" \
"loadaddr=" __stringify(CONFIG_SYS_LOAD_ADDR) "\0" \
"bootfile=" CONFIG_BOOTFILE "\0" \
+ "mmcroot=/dev/mmcblk0p2\0" \
+ "mtdids=" CONFIG_MTDIDS_DEFAULT "\0" \
+ "mtdparts=" CONFIG_MTDPARTS_DEFAULT "\0" \
+ "linux_qspi_enable=if sf probe; then " \
+ "echo Enabling QSPI at Linux DTB...;" \
+ "fdt addr ${fdt_addr}; fdt resize;" \
+ "fdt set /soc/spi@108d2000 status okay;" \
+ "if fdt set /clocks/qspi-clk clock-frequency" \
+ " ${qspi_clock}; then echo QSPI clock frequency updated;" \
+ " elif fdt set /soc/clkmgr/clocks/qspi_clk clock-frequency" \
+ " ${qspi_clock}; then echo QSPI clock frequency updated;" \
+ " else fdt set /clocks/qspi-clk clock-frequency" \
+ " ${qspi_clock}; echo QSPI clock frequency updated; fi; fi\0" \
+ "scriptaddr=0x81000000\0" \
+ "scriptfile=boot.scr\0" \
+ "socfpga_legacy_reset_compat=1\0" \
+ "smc_fid_rd=0xC2000007\0" \
+ "smc_fid_wr=0xC2000008\0" \
+ "smc_fid_upd=0xC2000009\0 " \
+ BOOTENV
+
+#else
+
+#define CFG_EXTRA_ENV_SETTINGS \
+ "kernel_addr_r=0x2000000\0" \
+ "fdt_addr_r=0x6000000\0" \
+ "qspiscriptaddr=0x02110000\0" \
+ "scriptsize=0x00010000\0" \
+ "qspibootimageaddr=0x02120000\0" \
+ "bootimagesize=0x03200000\0" \
+ "loadaddr=" __stringify(CONFIG_SYS_LOAD_ADDR) "\0" \
+ "bootfile=" CONFIG_BOOTFILE "\0" \
+ "mmcroot=/dev/mmcblk0p2\0" \
+ "mtdids=" CONFIG_MTDIDS_DEFAULT "\0" \
+ "mtdparts=" CONFIG_MTDPARTS_DEFAULT "\0" \
+ "linux_qspi_enable=if sf probe; then " \
+ "echo Enabling QSPI at Linux DTB...;" \
+ "fdt addr ${fdt_addr}; fdt resize;" \
+ "fdt set /soc/spi@ff8d2000 status okay;" \
+ "if fdt set /soc/clocks/qspi-clk clock-frequency" \
+ " ${qspi_clock}; then echo QSPI clock frequency updated;" \
+ " elif fdt set /soc/clkmgr/clocks/qspi_clk clock-frequency" \
+ " ${qspi_clock}; then echo QSPI clock frequency updated;" \
+ " else fdt set /clocks/qspi-clk clock-frequency" \
+ " ${qspi_clock}; echo QSPI clock frequency updated; fi; fi\0" \
+ "scriptaddr=0x05FF0000\0" \
+ "scriptfile=boot.scr\0" \
+ "socfpga_legacy_reset_compat=1\0" \
+ "smc_fid_rd=0xC2000007\0" \
+ "smc_fid_wr=0xC2000008\0" \
+ "smc_fid_upd=0xC2000009\0 " \
+ BOOTENV
+#endif /*#IS_ENABLED(CONFIG_TARGET_SOCFPGA_AGILEX5)*/
+
+#else
+
+#define CFG_EXTRA_ENV_SETTINGS \
+ "kernel_comp_addr_r=0x9000000\0" \
+ "kernel_comp_size=0x01000000\0" \
+ "qspibootimageaddr=0x020E0000\0" \
+ "qspifdtaddr=0x020D0000\0" \
+ "bootimagesize=0x01F00000\0" \
+ "fdtimagesize=0x00010000\0" \
+ "qspiload=sf read ${loadaddr} ${qspibootimageaddr} ${bootimagesize};" \
+ "sf read ${fdt_addr} ${qspifdtaddr} ${fdtimagesize}\0" \
+ "qspiboot=setenv bootargs earlycon root=/dev/mtdblock1 rw " \
+ "rootfstype=jffs2 rootwait;booti ${loadaddr} - ${fdt_addr}\0" \
+ "qspifitload=sf read ${loadaddr} ${qspibootimageaddr} ${bootimagesize}\0" \
+ "qspifitboot=setenv bootargs earlycon root=/dev/mtdblock1 rw " \
+ "rootfstype=jffs2 rootwait;bootm ${loadaddr}\0" \
+ "loadaddr=" __stringify(CONFIG_SYS_LOAD_ADDR) "\0" \
+ "bootfile=" CONFIG_BOOTFILE "\0" \
"fdt_addr=8000000\0" \
"fdtimage=" CONFIG_DEFAULT_DEVICE_TREE ".dtb\0" \
"mmcroot=/dev/mmcblk0p2\0" \
@@ -53,24 +170,40 @@
"bootm ${loadaddr}\0" \
"mmcfitload=mmc rescan;" \
"load mmc 0:1 ${loadaddr} ${bootfile}\0" \
+ "mtdids=" CONFIG_MTDIDS_DEFAULT "\0" \
+ "mtdparts=" CONFIG_MTDPARTS_DEFAULT "\0" \
"linux_qspi_enable=if sf probe; then " \
"echo Enabling QSPI at Linux DTB...;" \
"fdt addr ${fdt_addr}; fdt resize;" \
"fdt set /soc/spi@ff8d2000 status okay;" \
- "fdt set /soc/clkmgr/clocks/qspi_clk clock-frequency " \
- " ${qspi_clock}; fi; \0" \
+ "if fdt set /soc/clocks/qspi-clk clock-frequency" \
+ " ${qspi_clock}; then echo QSPI clock frequency updated;" \
+ " elif fdt set /soc/clkmgr/clocks/qspi_clk clock-frequency" \
+ " ${qspi_clock}; then echo QSPI clock frequency updated;" \
+ " else fdt set /clocks/qspi-clk clock-frequency" \
+ " ${qspi_clock}; echo QSPI clock frequency updated; fi; fi\0" \
"scriptaddr=0x02100000\0" \
"scriptfile=u-boot.scr\0" \
"fatscript=if fatload mmc 0:1 ${scriptaddr} ${scriptfile};" \
- "then source ${scriptaddr}; fi\0" \
- "socfpga_legacy_reset_compat=1\0"
+ "then source ${scriptaddr}:script; fi\0" \
+ "socfpga_legacy_reset_compat=1\0" \
+ "smc_fid_rd=0xC2000007\0" \
+ "smc_fid_wr=0xC2000008\0" \
+ "smc_fid_upd=0xC2000009\0 "
+#endif /*#if IS_ENABLED(CONFIG_DISTRO_DEFAULTS)*/
/*
* External memory configurations
*/
+#if IS_ENABLED(CONFIG_TARGET_SOCFPGA_AGILEX5)
+#define PHYS_SDRAM_1 0x80000000
+#define PHYS_SDRAM_1_SIZE (1 * 1024 * 1024 * 1024)
+#define CFG_SYS_SDRAM_BASE 0x80000000
+#else
#define PHYS_SDRAM_1 0x0
#define PHYS_SDRAM_1_SIZE (1 * 1024 * 1024 * 1024)
#define CFG_SYS_SDRAM_BASE 0
+#endif
/*
* Serial / UART configurations
diff --git a/include/configs/starfive-visionfive2.h b/include/configs/starfive-visionfive2.h
index 29c7447..049b0a0 100644
--- a/include/configs/starfive-visionfive2.h
+++ b/include/configs/starfive-visionfive2.h
@@ -15,17 +15,6 @@
#define __io
-/* Environment options */
-
-#define BOOT_TARGET_DEVICES(func) \
- func(NVME, nvme, 0) \
- func(USB, usb, 0) \
- func(MMC, mmc, 0) \
- func(MMC, mmc, 1) \
- func(DHCP, dhcp, na)
-
-#include <config_distro_bootcmd.h>
-
#define TYPE_GUID_SPL "2E54B353-1271-4842-806F-E436D6AF6985"
#define TYPE_GUID_UBOOT "BC13C2FF-59E6-4262-A352-B275FD6F7172"
#define TYPE_GUID_SYSTEM "EBD0A0A2-B9E5-4433-87C0-68B6B72699C7"
@@ -48,7 +37,6 @@
"type_guid_gpt_loader2=" TYPE_GUID_UBOOT "\0" \
"type_guid_gpt_system=" TYPE_GUID_SYSTEM "\0" \
"partitions=" PARTS_DEFAULT "\0" \
- "fdtfile=" CONFIG_DEFAULT_FDT_FILE "\0" \
- BOOTENV
+ "fdtfile=" CONFIG_DEFAULT_FDT_FILE "\0"
#endif /* _STARFIVE_VISIONFIVE2_H */
diff --git a/include/configs/stv0991.h b/include/configs/stv0991.h
deleted file mode 100644
index 7eadb6d..0000000
--- a/include/configs/stv0991.h
+++ /dev/null
@@ -1,25 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0+ */
-/*
- * Copyright (C) 2014, STMicroelectronics - All Rights Reserved
- * Author(s): Vikas Manocha, <vikas.manocha@st.com> for STMicroelectronics.
- */
-
-#ifndef __CONFIG_STV0991_H
-#define __CONFIG_STV0991_H
-#define CFG_SYS_EXCEPTION_VECTORS_HIGH
-
-/* ram memory-related information */
-#define PHYS_SDRAM_1 0x00000000
-#define CFG_SYS_SDRAM_BASE PHYS_SDRAM_1
-#define PHYS_SDRAM_1_SIZE 0x00198000
-
-/* user interface */
-
-/* MISC */
-#define CFG_SYS_INIT_RAM_SIZE 0x8000
-#define CFG_SYS_INIT_RAM_ADDR 0x00190000
-/* U-Boot Load Address */
-
-/* Misc configuration */
-
-#endif /* __CONFIG_H */
diff --git a/include/configs/toybrick_rk3588.h b/include/configs/toybrick_rk3588.h
new file mode 100644
index 0000000..faa2e6c
--- /dev/null
+++ b/include/configs/toybrick_rk3588.h
@@ -0,0 +1,15 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (c) 2024 Rockchip Electronics Co., Ltd.
+ */
+
+#ifndef __TOYBRICK_RK3588_H
+#define __TOYBRICK_RK3588_H
+
+#include <configs/rk3588_common.h>
+
+#define ROCKCHIP_DEVICE_SETTINGS \
+ "stdout=serial,vidconsole\0" \
+ "stderr=serial,vidconsole\0"
+
+#endif
diff --git a/include/cp1250.h b/include/cp1250.h
index adacf8a..b762c78 100644
--- a/include/cp1250.h
+++ b/include/cp1250.h
@@ -1,10 +1,18 @@
/* SPDX-License-Identifier: GPL-2.0+ */
/*
- * Constant CP1250 contains the Unicode code points for characters 0x80 - 0xff
- * of the code page 1250.
+ * Constant CP1250 contains the Unicode code points for characters 0x00 - 0x1f
+ * and 0x80 - 0xff of the code page 1250.
*/
#define CP1250 { \
+ 0x0000, 0x0000, 0x0000, 0x0000, \
+ 0x0000, 0x0000, 0x0000, 0x0000, \
+ 0x0000, 0x0000, 0x0000, 0x0000, \
+ 0x0000, 0x0000, 0x0000, 0x0000, \
+ 0x0000, 0x0000, 0x0000, 0x0000, \
+ 0x0000, 0x0000, 0x0000, 0x0000, \
+ 0x0000, 0x0000, 0x0000, 0x0000, \
+ 0x0000, 0x0000, 0x0000, 0x0000, \
0x20ac, 0x0000, 0x201a, 0x0000, \
0x201e, 0x2026, 0x2020, 0x2021, \
0x0000, 0x2030, 0x0160, 0x2039, \
diff --git a/include/cp437.h b/include/cp437.h
index 0b2b971..5093130 100644
--- a/include/cp437.h
+++ b/include/cp437.h
@@ -1,10 +1,18 @@
/* SPDX-License-Identifier: GPL-2.0+ */
/*
- * Constant CP437 contains the Unicode code points for characters 0x80 - 0xff
- * of the code page 437.
+ * Constant CP437 contains the Unicode code points for characters 0x00 - 0x1f
+ * and 0x80 - 0xff of the code page 437.
*/
#define CP437 { \
+ 0x0000, 0x263a, 0x263b, 0x2665, \
+ 0x2666, 0x2663, 0x2660, 0x2022, \
+ 0x25d8, 0x25cb, 0x25d9, 0x2642, \
+ 0x2640, 0x266a, 0x266b, 0x263c, \
+ 0x25ba, 0x25c4, 0x2195, 0x203c, \
+ 0x00b6, 0x00a7, 0x25ac, 0x21a8, \
+ 0x2191, 0x2193, 0x2192, 0x2190, \
+ 0x221f, 0x2194, 0x25b2, 0x25bc, \
0x00c7, 0x00fc, 0x00e9, 0x00e2, \
0x00e4, 0x00e0, 0x00e5, 0x00e7, \
0x00ea, 0x00eb, 0x00e8, 0x00ef, \
diff --git a/include/dt-bindings/clock/agilex5-clock.h b/include/dt-bindings/clock/agilex5-clock.h
new file mode 100644
index 0000000..c84fa51
--- /dev/null
+++ b/include/dt-bindings/clock/agilex5-clock.h
@@ -0,0 +1,71 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Copyright (C) 2024, Intel Corporation
+ */
+
+#ifndef __AGILEX5_CLOCK_H
+#define __AGILEX5_CLOCK_H
+
+/* fixed rate clocks */
+#define AGILEX5_OSC1 0
+#define AGILEX5_CB_INTOSC_HS_DIV2_CLK 1
+#define AGILEX5_CB_INTOSC_LS_CLK 2
+#define AGILEX5_L4_SYS_FREE_CLK 3
+#define AGILEX5_F2S_FREE_CLK 4
+
+/* PLL clocks */
+#define AGILEX5_MAIN_PLL_CLK 5
+#define AGILEX5_MAIN_PLL_C0_CLK 6
+#define AGILEX5_MAIN_PLL_C1_CLK 7
+#define AGILEX5_MAIN_PLL_C2_CLK 8
+#define AGILEX5_MAIN_PLL_C3_CLK 9
+#define AGILEX5_PERIPH_PLL_CLK 10
+#define AGILEX5_PERIPH_PLL_C0_CLK 11
+#define AGILEX5_PERIPH_PLL_C1_CLK 12
+#define AGILEX5_PERIPH_PLL_C2_CLK 13
+#define AGILEX5_PERIPH_PLL_C3_CLK 14
+#define AGILEX5_MPU_FREE_CLK 15
+#define AGILEX5_MPU_CCU_CLK 16
+#define AGILEX5_BOOT_CLK 17
+
+/* fixed factor clocks */
+#define AGILEX5_L3_MAIN_FREE_CLK 18
+#define AGILEX5_NOC_FREE_CLK 19
+#define AGILEX5_S2F_USR0_CLK 20
+#define AGILEX5_NOC_CLK 21
+#define AGILEX5_EMAC_A_FREE_CLK 22
+#define AGILEX5_EMAC_B_FREE_CLK 23
+#define AGILEX5_EMAC_PTP_FREE_CLK 24
+#define AGILEX5_GPIO_DB_FREE_CLK 25
+#define AGILEX5_SDMMC_FREE_CLK 26
+#define AGILEX5_S2F_USER0_FREE_CLK 27
+#define AGILEX5_S2F_USER1_FREE_CLK 28
+#define AGILEX5_PSI_REF_FREE_CLK 29
+
+/* Gate clocks */
+#define AGILEX5_MPU_CLK 30
+#define AGILEX5_MPU_PERIPH_CLK 31
+#define AGILEX5_L4_MAIN_CLK 32
+#define AGILEX5_L4_MP_CLK 33
+#define AGILEX5_L4_SP_CLK 34
+#define AGILEX5_CS_AT_CLK 35
+#define AGILEX5_CS_TRACE_CLK 36
+#define AGILEX5_CS_PDBG_CLK 37
+#define AGILEX5_CS_TIMER_CLK 38
+#define AGILEX5_S2F_USER0_CLK 39
+#define AGILEX5_EMAC0_CLK 40
+#define AGILEX5_EMAC1_CLK 41
+#define AGILEX5_EMAC2_CLK 42
+#define AGILEX5_EMAC_PTP_CLK 43
+#define AGILEX5_GPIO_DB_CLK 44
+#define AGILEX5_NAND_CLK 45
+#define AGILEX5_PSI_REF_CLK 46
+#define AGILEX5_S2F_USER1_CLK 47
+#define AGILEX5_SDMMC_CLK 48
+#define AGILEX5_SPI_M_CLK 49
+#define AGILEX5_USB_CLK 50
+#define AGILEX5_NAND_X_CLK 51
+#define AGILEX5_NAND_ECC_CLK 52
+#define AGILEX5_NUM_CLKS 53
+
+#endif /* __AGILEX5_CLOCK_H */
diff --git a/include/dt-bindings/gpio/meson-axg-gpio.h b/include/dt-bindings/gpio/meson-axg-gpio.h
deleted file mode 100644
index 25bb1ff..0000000
--- a/include/dt-bindings/gpio/meson-axg-gpio.h
+++ /dev/null
@@ -1,116 +0,0 @@
-/*
- * Copyright (c) 2017 Amlogic, Inc. All rights reserved.
- * Author: Xingyu Chen <xingyu.chen@amlogic.com>
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#ifndef _DT_BINDINGS_MESON_AXG_GPIO_H
-#define _DT_BINDINGS_MESON_AXG_GPIO_H
-
-/* First GPIO chip */
-#define GPIOAO_0 0
-#define GPIOAO_1 1
-#define GPIOAO_2 2
-#define GPIOAO_3 3
-#define GPIOAO_4 4
-#define GPIOAO_5 5
-#define GPIOAO_6 6
-#define GPIOAO_7 7
-#define GPIOAO_8 8
-#define GPIOAO_9 9
-#define GPIOAO_10 10
-#define GPIOAO_11 11
-#define GPIOAO_12 12
-#define GPIOAO_13 13
-#define GPIO_TEST_N 14
-
-/* Second GPIO chip */
-#define GPIOZ_0 0
-#define GPIOZ_1 1
-#define GPIOZ_2 2
-#define GPIOZ_3 3
-#define GPIOZ_4 4
-#define GPIOZ_5 5
-#define GPIOZ_6 6
-#define GPIOZ_7 7
-#define GPIOZ_8 8
-#define GPIOZ_9 9
-#define GPIOZ_10 10
-#define BOOT_0 11
-#define BOOT_1 12
-#define BOOT_2 13
-#define BOOT_3 14
-#define BOOT_4 15
-#define BOOT_5 16
-#define BOOT_6 17
-#define BOOT_7 18
-#define BOOT_8 19
-#define BOOT_9 20
-#define BOOT_10 21
-#define BOOT_11 22
-#define BOOT_12 23
-#define BOOT_13 24
-#define BOOT_14 25
-#define GPIOA_0 26
-#define GPIOA_1 27
-#define GPIOA_2 28
-#define GPIOA_3 29
-#define GPIOA_4 30
-#define GPIOA_5 31
-#define GPIOA_6 32
-#define GPIOA_7 33
-#define GPIOA_8 34
-#define GPIOA_9 35
-#define GPIOA_10 36
-#define GPIOA_11 37
-#define GPIOA_12 38
-#define GPIOA_13 39
-#define GPIOA_14 40
-#define GPIOA_15 41
-#define GPIOA_16 42
-#define GPIOA_17 43
-#define GPIOA_18 44
-#define GPIOA_19 45
-#define GPIOA_20 46
-#define GPIOX_0 47
-#define GPIOX_1 48
-#define GPIOX_2 49
-#define GPIOX_3 50
-#define GPIOX_4 51
-#define GPIOX_5 52
-#define GPIOX_6 53
-#define GPIOX_7 54
-#define GPIOX_8 55
-#define GPIOX_9 56
-#define GPIOX_10 57
-#define GPIOX_11 58
-#define GPIOX_12 59
-#define GPIOX_13 60
-#define GPIOX_14 61
-#define GPIOX_15 62
-#define GPIOX_16 63
-#define GPIOX_17 64
-#define GPIOX_18 65
-#define GPIOX_19 66
-#define GPIOX_20 67
-#define GPIOX_21 68
-#define GPIOX_22 69
-#define GPIOY_0 70
-#define GPIOY_1 71
-#define GPIOY_2 72
-#define GPIOY_3 73
-#define GPIOY_4 74
-#define GPIOY_5 75
-#define GPIOY_6 76
-#define GPIOY_7 77
-#define GPIOY_8 78
-#define GPIOY_9 79
-#define GPIOY_10 80
-#define GPIOY_11 81
-#define GPIOY_12 82
-#define GPIOY_13 83
-#define GPIOY_14 84
-#define GPIOY_15 85
-
-#endif /* _DT_BINDINGS_MESON_AXG_GPIO_H */
diff --git a/include/dt-bindings/gpio/meson-g12a-gpio.h b/include/dt-bindings/gpio/meson-g12a-gpio.h
deleted file mode 100644
index f7bd693..0000000
--- a/include/dt-bindings/gpio/meson-g12a-gpio.h
+++ /dev/null
@@ -1,114 +0,0 @@
-/* SPDX-License-Identifier: (GPL-2.0+ or MIT) */
-/*
- * Copyright (c) 2018 Amlogic, Inc. All rights reserved.
- * Author: Xingyu Chen <xingyu.chen@amlogic.com>
- */
-
-#ifndef _DT_BINDINGS_MESON_G12A_GPIO_H
-#define _DT_BINDINGS_MESON_G12A_GPIO_H
-
-/* First GPIO chip */
-#define GPIOAO_0 0
-#define GPIOAO_1 1
-#define GPIOAO_2 2
-#define GPIOAO_3 3
-#define GPIOAO_4 4
-#define GPIOAO_5 5
-#define GPIOAO_6 6
-#define GPIOAO_7 7
-#define GPIOAO_8 8
-#define GPIOAO_9 9
-#define GPIOAO_10 10
-#define GPIOAO_11 11
-#define GPIOE_0 12
-#define GPIOE_1 13
-#define GPIOE_2 14
-
-/* Second GPIO chip */
-#define GPIOZ_0 0
-#define GPIOZ_1 1
-#define GPIOZ_2 2
-#define GPIOZ_3 3
-#define GPIOZ_4 4
-#define GPIOZ_5 5
-#define GPIOZ_6 6
-#define GPIOZ_7 7
-#define GPIOZ_8 8
-#define GPIOZ_9 9
-#define GPIOZ_10 10
-#define GPIOZ_11 11
-#define GPIOZ_12 12
-#define GPIOZ_13 13
-#define GPIOZ_14 14
-#define GPIOZ_15 15
-#define GPIOH_0 16
-#define GPIOH_1 17
-#define GPIOH_2 18
-#define GPIOH_3 19
-#define GPIOH_4 20
-#define GPIOH_5 21
-#define GPIOH_6 22
-#define GPIOH_7 23
-#define GPIOH_8 24
-#define BOOT_0 25
-#define BOOT_1 26
-#define BOOT_2 27
-#define BOOT_3 28
-#define BOOT_4 29
-#define BOOT_5 30
-#define BOOT_6 31
-#define BOOT_7 32
-#define BOOT_8 33
-#define BOOT_9 34
-#define BOOT_10 35
-#define BOOT_11 36
-#define BOOT_12 37
-#define BOOT_13 38
-#define BOOT_14 39
-#define BOOT_15 40
-#define GPIOC_0 41
-#define GPIOC_1 42
-#define GPIOC_2 43
-#define GPIOC_3 44
-#define GPIOC_4 45
-#define GPIOC_5 46
-#define GPIOC_6 47
-#define GPIOC_7 48
-#define GPIOA_0 49
-#define GPIOA_1 50
-#define GPIOA_2 51
-#define GPIOA_3 52
-#define GPIOA_4 53
-#define GPIOA_5 54
-#define GPIOA_6 55
-#define GPIOA_7 56
-#define GPIOA_8 57
-#define GPIOA_9 58
-#define GPIOA_10 59
-#define GPIOA_11 60
-#define GPIOA_12 61
-#define GPIOA_13 62
-#define GPIOA_14 63
-#define GPIOA_15 64
-#define GPIOX_0 65
-#define GPIOX_1 66
-#define GPIOX_2 67
-#define GPIOX_3 68
-#define GPIOX_4 69
-#define GPIOX_5 70
-#define GPIOX_6 71
-#define GPIOX_7 72
-#define GPIOX_8 73
-#define GPIOX_9 74
-#define GPIOX_10 75
-#define GPIOX_11 76
-#define GPIOX_12 77
-#define GPIOX_13 78
-#define GPIOX_14 79
-#define GPIOX_15 80
-#define GPIOX_16 81
-#define GPIOX_17 82
-#define GPIOX_18 83
-#define GPIOX_19 84
-
-#endif /* _DT_BINDINGS_MESON_G12A_GPIO_H */
diff --git a/include/dt-bindings/gpio/meson-gxbb-gpio.h b/include/dt-bindings/gpio/meson-gxbb-gpio.h
deleted file mode 100644
index 489c75b..0000000
--- a/include/dt-bindings/gpio/meson-gxbb-gpio.h
+++ /dev/null
@@ -1,148 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0-only */
-/*
- * GPIO definitions for Amlogic Meson GXBB SoCs
- *
- * Copyright (C) 2016 Endless Mobile, Inc.
- * Author: Carlo Caione <carlo@endlessm.com>
- */
-
-#ifndef _DT_BINDINGS_MESON_GXBB_GPIO_H
-#define _DT_BINDINGS_MESON_GXBB_GPIO_H
-
-#define GPIOAO_0 0
-#define GPIOAO_1 1
-#define GPIOAO_2 2
-#define GPIOAO_3 3
-#define GPIOAO_4 4
-#define GPIOAO_5 5
-#define GPIOAO_6 6
-#define GPIOAO_7 7
-#define GPIOAO_8 8
-#define GPIOAO_9 9
-#define GPIOAO_10 10
-#define GPIOAO_11 11
-#define GPIOAO_12 12
-#define GPIOAO_13 13
-#define GPIO_TEST_N 14
-
-#define GPIOZ_0 0
-#define GPIOZ_1 1
-#define GPIOZ_2 2
-#define GPIOZ_3 3
-#define GPIOZ_4 4
-#define GPIOZ_5 5
-#define GPIOZ_6 6
-#define GPIOZ_7 7
-#define GPIOZ_8 8
-#define GPIOZ_9 9
-#define GPIOZ_10 10
-#define GPIOZ_11 11
-#define GPIOZ_12 12
-#define GPIOZ_13 13
-#define GPIOZ_14 14
-#define GPIOZ_15 15
-#define GPIOH_0 16
-#define GPIOH_1 17
-#define GPIOH_2 18
-#define GPIOH_3 19
-#define BOOT_0 20
-#define BOOT_1 21
-#define BOOT_2 22
-#define BOOT_3 23
-#define BOOT_4 24
-#define BOOT_5 25
-#define BOOT_6 26
-#define BOOT_7 27
-#define BOOT_8 28
-#define BOOT_9 29
-#define BOOT_10 30
-#define BOOT_11 31
-#define BOOT_12 32
-#define BOOT_13 33
-#define BOOT_14 34
-#define BOOT_15 35
-#define BOOT_16 36
-#define BOOT_17 37
-#define CARD_0 38
-#define CARD_1 39
-#define CARD_2 40
-#define CARD_3 41
-#define CARD_4 42
-#define CARD_5 43
-#define CARD_6 44
-#define GPIODV_0 45
-#define GPIODV_1 46
-#define GPIODV_2 47
-#define GPIODV_3 48
-#define GPIODV_4 49
-#define GPIODV_5 50
-#define GPIODV_6 51
-#define GPIODV_7 52
-#define GPIODV_8 53
-#define GPIODV_9 54
-#define GPIODV_10 55
-#define GPIODV_11 56
-#define GPIODV_12 57
-#define GPIODV_13 58
-#define GPIODV_14 59
-#define GPIODV_15 60
-#define GPIODV_16 61
-#define GPIODV_17 62
-#define GPIODV_18 63
-#define GPIODV_19 64
-#define GPIODV_20 65
-#define GPIODV_21 66
-#define GPIODV_22 67
-#define GPIODV_23 68
-#define GPIODV_24 69
-#define GPIODV_25 70
-#define GPIODV_26 71
-#define GPIODV_27 72
-#define GPIODV_28 73
-#define GPIODV_29 74
-#define GPIOY_0 75
-#define GPIOY_1 76
-#define GPIOY_2 77
-#define GPIOY_3 78
-#define GPIOY_4 79
-#define GPIOY_5 80
-#define GPIOY_6 81
-#define GPIOY_7 82
-#define GPIOY_8 83
-#define GPIOY_9 84
-#define GPIOY_10 85
-#define GPIOY_11 86
-#define GPIOY_12 87
-#define GPIOY_13 88
-#define GPIOY_14 89
-#define GPIOY_15 90
-#define GPIOY_16 91
-#define GPIOX_0 92
-#define GPIOX_1 93
-#define GPIOX_2 94
-#define GPIOX_3 95
-#define GPIOX_4 96
-#define GPIOX_5 97
-#define GPIOX_6 98
-#define GPIOX_7 99
-#define GPIOX_8 100
-#define GPIOX_9 101
-#define GPIOX_10 102
-#define GPIOX_11 103
-#define GPIOX_12 104
-#define GPIOX_13 105
-#define GPIOX_14 106
-#define GPIOX_15 107
-#define GPIOX_16 108
-#define GPIOX_17 109
-#define GPIOX_18 110
-#define GPIOX_19 111
-#define GPIOX_20 112
-#define GPIOX_21 113
-#define GPIOX_22 114
-#define GPIOCLK_0 115
-#define GPIOCLK_1 116
-#define GPIOCLK_2 117
-#define GPIOCLK_3 118
-
-#endif
diff --git a/include/dt-bindings/gpio/meson-gxl-gpio.h b/include/dt-bindings/gpio/meson-gxl-gpio.h
deleted file mode 100644
index 0a001ae..0000000
--- a/include/dt-bindings/gpio/meson-gxl-gpio.h
+++ /dev/null
@@ -1,125 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0-only */
-/*
- * GPIO definitions for Amlogic Meson GXL SoCs
- *
- * Copyright (C) 2016 Endless Mobile, Inc.
- * Author: Carlo Caione <carlo@endlessm.com>
- */
-
-#ifndef _DT_BINDINGS_MESON_GXL_GPIO_H
-#define _DT_BINDINGS_MESON_GXL_GPIO_H
-
-#define GPIOAO_0 0
-#define GPIOAO_1 1
-#define GPIOAO_2 2
-#define GPIOAO_3 3
-#define GPIOAO_4 4
-#define GPIOAO_5 5
-#define GPIOAO_6 6
-#define GPIOAO_7 7
-#define GPIOAO_8 8
-#define GPIOAO_9 9
-#define GPIO_TEST_N 10
-
-#define GPIOZ_0 0
-#define GPIOZ_1 1
-#define GPIOZ_2 2
-#define GPIOZ_3 3
-#define GPIOZ_4 4
-#define GPIOZ_5 5
-#define GPIOZ_6 6
-#define GPIOZ_7 7
-#define GPIOZ_8 8
-#define GPIOZ_9 9
-#define GPIOZ_10 10
-#define GPIOZ_11 11
-#define GPIOZ_12 12
-#define GPIOZ_13 13
-#define GPIOZ_14 14
-#define GPIOZ_15 15
-#define GPIOH_0 16
-#define GPIOH_1 17
-#define GPIOH_2 18
-#define GPIOH_3 19
-#define GPIOH_4 20
-#define GPIOH_5 21
-#define GPIOH_6 22
-#define GPIOH_7 23
-#define GPIOH_8 24
-#define GPIOH_9 25
-#define BOOT_0 26
-#define BOOT_1 27
-#define BOOT_2 28
-#define BOOT_3 29
-#define BOOT_4 30
-#define BOOT_5 31
-#define BOOT_6 32
-#define BOOT_7 33
-#define BOOT_8 34
-#define BOOT_9 35
-#define BOOT_10 36
-#define BOOT_11 37
-#define BOOT_12 38
-#define BOOT_13 39
-#define BOOT_14 40
-#define BOOT_15 41
-#define CARD_0 42
-#define CARD_1 43
-#define CARD_2 44
-#define CARD_3 45
-#define CARD_4 46
-#define CARD_5 47
-#define CARD_6 48
-#define GPIODV_0 49
-#define GPIODV_1 50
-#define GPIODV_2 51
-#define GPIODV_3 52
-#define GPIODV_4 53
-#define GPIODV_5 54
-#define GPIODV_6 55
-#define GPIODV_7 56
-#define GPIODV_8 57
-#define GPIODV_9 58
-#define GPIODV_10 59
-#define GPIODV_11 60
-#define GPIODV_12 61
-#define GPIODV_13 62
-#define GPIODV_14 63
-#define GPIODV_15 64
-#define GPIODV_16 65
-#define GPIODV_17 66
-#define GPIODV_18 67
-#define GPIODV_19 68
-#define GPIODV_20 69
-#define GPIODV_21 70
-#define GPIODV_22 71
-#define GPIODV_23 72
-#define GPIODV_24 73
-#define GPIODV_25 74
-#define GPIODV_26 75
-#define GPIODV_27 76
-#define GPIODV_28 77
-#define GPIODV_29 78
-#define GPIOX_0 79
-#define GPIOX_1 80
-#define GPIOX_2 81
-#define GPIOX_3 82
-#define GPIOX_4 83
-#define GPIOX_5 84
-#define GPIOX_6 85
-#define GPIOX_7 86
-#define GPIOX_8 87
-#define GPIOX_9 88
-#define GPIOX_10 89
-#define GPIOX_11 90
-#define GPIOX_12 91
-#define GPIOX_13 92
-#define GPIOX_14 93
-#define GPIOX_15 94
-#define GPIOX_16 95
-#define GPIOX_17 96
-#define GPIOX_18 97
-#define GPIOCLK_0 98
-#define GPIOCLK_1 99
-
-#endif
diff --git a/include/dt-bindings/power/meson-axg-power.h b/include/dt-bindings/power/meson-axg-power.h
deleted file mode 100644
index e524388..0000000
--- a/include/dt-bindings/power/meson-axg-power.h
+++ /dev/null
@@ -1,14 +0,0 @@
-/* SPDX-License-Identifier: (GPL-2.0+ or MIT) */
-/*
- * Copyright (c) 2020 BayLibre, SAS
- * Author: Neil Armstrong <narmstrong@baylibre.com>
- */
-
-#ifndef _DT_BINDINGS_MESON_AXG_POWER_H
-#define _DT_BINDINGS_MESON_AXG_POWER_H
-
-#define PWRC_AXG_VPU_ID 0
-#define PWRC_AXG_ETHERNET_MEM_ID 1
-#define PWRC_AXG_AUDIO_ID 2
-
-#endif
diff --git a/include/dt-bindings/power/meson-g12a-power.h b/include/dt-bindings/power/meson-g12a-power.h
deleted file mode 100644
index bb5e67a..0000000
--- a/include/dt-bindings/power/meson-g12a-power.h
+++ /dev/null
@@ -1,13 +0,0 @@
-/* SPDX-License-Identifier: (GPL-2.0+ or MIT) */
-/*
- * Copyright (c) 2019 BayLibre, SAS
- * Author: Neil Armstrong <narmstrong@baylibre.com>
- */
-
-#ifndef _DT_BINDINGS_MESON_G12A_POWER_H
-#define _DT_BINDINGS_MESON_G12A_POWER_H
-
-#define PWRC_G12A_VPU_ID 0
-#define PWRC_G12A_ETH_ID 1
-
-#endif
diff --git a/include/dt-bindings/power/meson-gxbb-power.h b/include/dt-bindings/power/meson-gxbb-power.h
deleted file mode 100644
index 1262dac..0000000
--- a/include/dt-bindings/power/meson-gxbb-power.h
+++ /dev/null
@@ -1,13 +0,0 @@
-/* SPDX-License-Identifier: (GPL-2.0+ or MIT) */
-/*
- * Copyright (c) 2019 BayLibre, SAS
- * Author: Neil Armstrong <narmstrong@baylibre.com>
- */
-
-#ifndef _DT_BINDINGS_MESON_GXBB_POWER_H
-#define _DT_BINDINGS_MESON_GXBB_POWER_H
-
-#define PWRC_GXBB_VPU_ID 0
-#define PWRC_GXBB_ETHERNET_MEM_ID 1
-
-#endif
diff --git a/include/dt-bindings/power/meson-sm1-power.h b/include/dt-bindings/power/meson-sm1-power.h
deleted file mode 100644
index a020ab0..0000000
--- a/include/dt-bindings/power/meson-sm1-power.h
+++ /dev/null
@@ -1,18 +0,0 @@
-/* SPDX-License-Identifier: (GPL-2.0+ or MIT) */
-/*
- * Copyright (c) 2019 BayLibre, SAS
- * Author: Neil Armstrong <narmstrong@baylibre.com>
- */
-
-#ifndef _DT_BINDINGS_MESON_SM1_POWER_H
-#define _DT_BINDINGS_MESON_SM1_POWER_H
-
-#define PWRC_SM1_VPU_ID 0
-#define PWRC_SM1_NNA_ID 1
-#define PWRC_SM1_USB_ID 2
-#define PWRC_SM1_PCIE_ID 3
-#define PWRC_SM1_GE2D_ID 4
-#define PWRC_SM1_AUDIO_ID 5
-#define PWRC_SM1_ETH_ID 6
-
-#endif
diff --git a/include/dt-bindings/reset/altr,rst-mgr-agx5.h b/include/dt-bindings/reset/altr,rst-mgr-agx5.h
new file mode 100644
index 0000000..1dba270
--- /dev/null
+++ b/include/dt-bindings/reset/altr,rst-mgr-agx5.h
@@ -0,0 +1,80 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Copyright (C) 2024 Intel Corporation. All rights reserved
+ */
+
+#ifndef _DT_BINDINGS_RESET_ALTR_RST_MGR_AGX_EDGE_H
+#define _DT_BINDINGS_RESET_ALTR_RST_MGR_AGX_EDGE_H
+
+/* PER0MODRST */
+#define EMAC0_RESET 0
+#define EMAC1_RESET 1
+#define EMAC2_RESET 2
+#define USB0_RESET 3
+#define USB1_RESET 4
+#define NAND_RESET 5
+#define COMBOPHY_RESET 6
+#define SDMMC_RESET 7
+#define EMAC0_OCP_RESET 8
+#define EMAC1_OCP_RESET 9
+#define EMAC2_OCP_RESET 10
+#define USB0_OCP_RESET 11
+#define USB1_OCP_RESET 12
+#define NAND_OCP_RESET 13
+/* 14 is empty */
+#define SDMMC_OCP_RESET 15
+#define DMA_RESET 16
+#define SPIM0_RESET 17
+#define SPIM1_RESET 18
+#define SPIS0_RESET 19
+#define SPIS1_RESET 20
+#define DMA_OCP_RESET 21
+#define EMAC_PTP_RESET 22
+/* 23 is empty*/
+#define DMAIF0_RESET 24
+#define DMAIF1_RESET 25
+#define DMAIF2_RESET 26
+#define DMAIF3_RESET 27
+#define DMAIF4_RESET 28
+#define DMAIF5_RESET 29
+#define DMAIF6_RESET 30
+#define DMAIF7_RESET 31
+
+/* PER1MODRST */
+#define WATCHDOG0_RESET 32
+#define WATCHDOG1_RESET 33
+#define WATCHDOG2_RESET 34
+#define WATCHDOG3_RESET 35
+#define L4SYSTIMER0_RESET 36
+#define L4SYSTIMER1_RESET 37
+#define SPTIMER0_RESET 38
+#define SPTIMER1_RESET 39
+#define I2C0_RESET 40
+#define I2C1_RESET 41
+#define I2C2_RESET 42
+#define I2C3_RESET 43
+#define I2C4_RESET 44
+#define I3C0_RESET 45
+#define I3C1_RESET 46
+/* 47 is empty */
+#define UART0_RESET 48
+#define UART1_RESET 49
+/* 50-55 is empty */
+#define GPIO0_RESET 56
+#define GPIO1_RESET 57
+#define WATCHDOG4_RESET 58
+/* 59-63 is empty */
+
+/* BRGMODRST */
+#define SOC2FPGA_RESET 64
+#define LWHPS2FPGA_RESET 65
+#define FPGA2SOC_RESET 66
+#define F2SSDRAM_RESET 67
+/* 68-69 is empty */
+#define DDRSCH_RESET 70
+/* 71-95 is empty */
+
+/* DBGMODRST */
+#define DBG_RESET 192
+
+#endif
diff --git a/include/dt-bindings/reset/amlogic,meson-axg-audio-arb.h b/include/dt-bindings/reset/amlogic,meson-axg-audio-arb.h
deleted file mode 100644
index 1ef8078..0000000
--- a/include/dt-bindings/reset/amlogic,meson-axg-audio-arb.h
+++ /dev/null
@@ -1,19 +0,0 @@
-/* SPDX-License-Identifier: (GPL-2.0 OR MIT)
- *
- * Copyright (c) 2018 Baylibre SAS.
- * Author: Jerome Brunet <jbrunet@baylibre.com>
- */
-
-#ifndef _DT_BINDINGS_AMLOGIC_MESON_AXG_AUDIO_ARB_H
-#define _DT_BINDINGS_AMLOGIC_MESON_AXG_AUDIO_ARB_H
-
-#define AXG_ARB_TODDR_A 0
-#define AXG_ARB_TODDR_B 1
-#define AXG_ARB_TODDR_C 2
-#define AXG_ARB_FRDDR_A 3
-#define AXG_ARB_FRDDR_B 4
-#define AXG_ARB_FRDDR_C 5
-#define AXG_ARB_TODDR_D 6
-#define AXG_ARB_FRDDR_D 7
-
-#endif /* _DT_BINDINGS_AMLOGIC_MESON_AXG_AUDIO_ARB_H */
diff --git a/include/dt-bindings/reset/amlogic,meson-axg-reset.h b/include/dt-bindings/reset/amlogic,meson-axg-reset.h
deleted file mode 100644
index 0f2e0fe..0000000
--- a/include/dt-bindings/reset/amlogic,meson-axg-reset.h
+++ /dev/null
@@ -1,123 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0+ OR BSD-3-Clause */
-/*
- * Copyright (c) 2016 BayLibre, SAS.
- * Author: Neil Armstrong <narmstrong@baylibre.com>
- *
- * Copyright (c) 2017 Amlogic, inc.
- * Author: Yixun Lan <yixun.lan@amlogic.com>
- *
- */
-
-#ifndef _DT_BINDINGS_AMLOGIC_MESON_AXG_RESET_H
-#define _DT_BINDINGS_AMLOGIC_MESON_AXG_RESET_H
-
-/* RESET0 */
-#define RESET_HIU 0
-#define RESET_PCIE_A 1
-#define RESET_PCIE_B 2
-#define RESET_DDR_TOP 3
-/* 4 */
-#define RESET_VIU 5
-#define RESET_PCIE_PHY 6
-#define RESET_PCIE_APB 7
-/* 8 */
-/* 9 */
-#define RESET_VENC 10
-#define RESET_ASSIST 11
-/* 12 */
-#define RESET_VCBUS 13
-/* 14 */
-/* 15 */
-#define RESET_GIC 16
-#define RESET_CAPB3_DECODE 17
-/* 18-21 */
-#define RESET_SYS_CPU_CAPB3 22
-#define RESET_CBUS_CAPB3 23
-#define RESET_AHB_CNTL 24
-#define RESET_AHB_DATA 25
-#define RESET_VCBUS_CLK81 26
-#define RESET_MMC 27
-/* 28-31 */
-/* RESET1 */
-/* 32 */
-/* 33 */
-#define RESET_USB_OTG 34
-#define RESET_DDR 35
-#define RESET_AO_RESET 36
-/* 37 */
-#define RESET_AHB_SRAM 38
-/* 39 */
-/* 40 */
-#define RESET_DMA 41
-#define RESET_ISA 42
-#define RESET_ETHERNET 43
-/* 44 */
-#define RESET_SD_EMMC_B 45
-#define RESET_SD_EMMC_C 46
-#define RESET_ROM_BOOT 47
-#define RESET_SYS_CPU_0 48
-#define RESET_SYS_CPU_1 49
-#define RESET_SYS_CPU_2 50
-#define RESET_SYS_CPU_3 51
-#define RESET_SYS_CPU_CORE_0 52
-#define RESET_SYS_CPU_CORE_1 53
-#define RESET_SYS_CPU_CORE_2 54
-#define RESET_SYS_CPU_CORE_3 55
-#define RESET_SYS_PLL_DIV 56
-#define RESET_SYS_CPU_AXI 57
-#define RESET_SYS_CPU_L2 58
-#define RESET_SYS_CPU_P 59
-#define RESET_SYS_CPU_MBIST 60
-/* 61-63 */
-/* RESET2 */
-/* 64 */
-/* 65 */
-#define RESET_AUDIO 66
-/* 67 */
-#define RESET_MIPI_HOST 68
-#define RESET_AUDIO_LOCKER 69
-#define RESET_GE2D 70
-/* 71-76 */
-#define RESET_AO_CPU_RESET 77
-/* 78-95 */
-/* RESET3 */
-#define RESET_RING_OSCILLATOR 96
-/* 97-127 */
-/* RESET4 */
-/* 128 */
-/* 129 */
-#define RESET_MIPI_PHY 130
-/* 131-140 */
-#define RESET_VENCL 141
-#define RESET_I2C_MASTER_2 142
-#define RESET_I2C_MASTER_1 143
-/* 144-159 */
-/* RESET5 */
-/* 160-191 */
-/* RESET6 */
-#define RESET_PERIPHS_GENERAL 192
-#define RESET_PERIPHS_SPICC 193
-/* 194 */
-/* 195 */
-#define RESET_PERIPHS_I2C_MASTER_0 196
-/* 197-200 */
-#define RESET_PERIPHS_UART_0 201
-#define RESET_PERIPHS_UART_1 202
-/* 203-204 */
-#define RESET_PERIPHS_SPI_0 205
-#define RESET_PERIPHS_I2C_MASTER_3 206
-/* 207-223 */
-/* RESET7 */
-#define RESET_USB_DDR_0 224
-#define RESET_USB_DDR_1 225
-#define RESET_USB_DDR_2 226
-#define RESET_USB_DDR_3 227
-/* 228 */
-#define RESET_DEVICE_MMC_ARB 229
-/* 230 */
-#define RESET_VID_LOCK 231
-#define RESET_A9_DMC_PIPEL 232
-#define RESET_DMC_VPU_PIPEL 233
-/* 234-255 */
-
-#endif
diff --git a/include/dt-bindings/reset/amlogic,meson-g12a-audio-reset.h b/include/dt-bindings/reset/amlogic,meson-g12a-audio-reset.h
deleted file mode 100644
index f805129..0000000
--- a/include/dt-bindings/reset/amlogic,meson-g12a-audio-reset.h
+++ /dev/null
@@ -1,53 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 */
-/*
- * Copyright (c) 2019 BayLibre, SAS.
- * Author: Jerome Brunet <jbrunet@baylibre.com>
- *
- */
-
-#ifndef _DT_BINDINGS_AMLOGIC_MESON_G12A_AUDIO_RESET_H
-#define _DT_BINDINGS_AMLOGIC_MESON_G12A_AUDIO_RESET_H
-
-#define AUD_RESET_PDM 0
-#define AUD_RESET_TDMIN_A 1
-#define AUD_RESET_TDMIN_B 2
-#define AUD_RESET_TDMIN_C 3
-#define AUD_RESET_TDMIN_LB 4
-#define AUD_RESET_LOOPBACK 5
-#define AUD_RESET_TODDR_A 6
-#define AUD_RESET_TODDR_B 7
-#define AUD_RESET_TODDR_C 8
-#define AUD_RESET_FRDDR_A 9
-#define AUD_RESET_FRDDR_B 10
-#define AUD_RESET_FRDDR_C 11
-#define AUD_RESET_TDMOUT_A 12
-#define AUD_RESET_TDMOUT_B 13
-#define AUD_RESET_TDMOUT_C 14
-#define AUD_RESET_SPDIFOUT 15
-#define AUD_RESET_SPDIFOUT_B 16
-#define AUD_RESET_SPDIFIN 17
-#define AUD_RESET_EQDRC 18
-#define AUD_RESET_RESAMPLE 19
-#define AUD_RESET_DDRARB 20
-#define AUD_RESET_POWDET 21
-#define AUD_RESET_TORAM 22
-#define AUD_RESET_TOACODEC 23
-#define AUD_RESET_TOHDMITX 24
-#define AUD_RESET_CLKTREE 25
-
-/* SM1 added resets */
-#define AUD_RESET_RESAMPLE_B 26
-#define AUD_RESET_TOVAD 27
-#define AUD_RESET_LOCKER 28
-#define AUD_RESET_SPDIFIN_LB 29
-#define AUD_RESET_FRATV 30
-#define AUD_RESET_FRHDMIRX 31
-#define AUD_RESET_FRDDR_D 32
-#define AUD_RESET_TODDR_D 33
-#define AUD_RESET_LOOPBACK_B 34
-#define AUD_RESET_EARCTX 35
-#define AUD_RESET_EARCRX 36
-#define AUD_RESET_FRDDR_E 37
-#define AUD_RESET_TODDR_E 38
-
-#endif
diff --git a/include/dt-bindings/reset/amlogic,meson-g12a-reset.h b/include/dt-bindings/reset/amlogic,meson-g12a-reset.h
deleted file mode 100644
index 6d487c5..0000000
--- a/include/dt-bindings/reset/amlogic,meson-g12a-reset.h
+++ /dev/null
@@ -1,137 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0+ OR BSD-3-Clause */
-/*
- * Copyright (c) 2019 BayLibre, SAS.
- * Author: Jerome Brunet <jbrunet@baylibre.com>
- *
- */
-
-#ifndef _DT_BINDINGS_AMLOGIC_MESON_G12A_RESET_H
-#define _DT_BINDINGS_AMLOGIC_MESON_G12A_RESET_H
-
-/* RESET0 */
-#define RESET_HIU 0
-/* 1 */
-#define RESET_DOS 2
-/* 3-4 */
-#define RESET_VIU 5
-#define RESET_AFIFO 6
-#define RESET_VID_PLL_DIV 7
-/* 8-9 */
-#define RESET_VENC 10
-#define RESET_ASSIST 11
-#define RESET_PCIE_CTRL_A 12
-#define RESET_VCBUS 13
-#define RESET_PCIE_PHY 14
-#define RESET_PCIE_APB 15
-#define RESET_GIC 16
-#define RESET_CAPB3_DECODE 17
-/* 18 */
-#define RESET_HDMITX_CAPB3 19
-#define RESET_DVALIN_CAPB3 20
-#define RESET_DOS_CAPB3 21
-/* 22 */
-#define RESET_CBUS_CAPB3 23
-#define RESET_AHB_CNTL 24
-#define RESET_AHB_DATA 25
-#define RESET_VCBUS_CLK81 26
-/* 27-31 */
-/* RESET1 */
-/* 32 */
-#define RESET_DEMUX 33
-#define RESET_USB 34
-#define RESET_DDR 35
-/* 36 */
-#define RESET_BT656 37
-#define RESET_AHB_SRAM 38
-/* 39 */
-#define RESET_PARSER 40
-/* 41 */
-#define RESET_ISA 42
-#define RESET_ETHERNET 43
-#define RESET_SD_EMMC_A 44
-#define RESET_SD_EMMC_B 45
-#define RESET_SD_EMMC_C 46
-/* 47 */
-#define RESET_USB_PHY20 48
-#define RESET_USB_PHY21 49
-/* 50-60 */
-#define RESET_AUDIO_CODEC 61
-/* 62-63 */
-/* RESET2 */
-/* 64 */
-#define RESET_AUDIO 65
-#define RESET_HDMITX_PHY 66
-/* 67 */
-#define RESET_MIPI_DSI_HOST 68
-#define RESET_ALOCKER 69
-#define RESET_GE2D 70
-#define RESET_PARSER_REG 71
-#define RESET_PARSER_FETCH 72
-#define RESET_CTL 73
-#define RESET_PARSER_TOP 74
-/* 75-77 */
-#define RESET_DVALIN 78
-#define RESET_HDMITX 79
-/* 80-95 */
-/* RESET3 */
-/* 96-95 */
-#define RESET_DEMUX_TOP 105
-#define RESET_DEMUX_DES_PL 106
-#define RESET_DEMUX_S2P_0 107
-#define RESET_DEMUX_S2P_1 108
-#define RESET_DEMUX_0 109
-#define RESET_DEMUX_1 110
-#define RESET_DEMUX_2 111
-/* 112-127 */
-/* RESET4 */
-/* 128-129 */
-#define RESET_MIPI_DSI_PHY 130
-/* 131-132 */
-#define RESET_RDMA 133
-#define RESET_VENCI 134
-#define RESET_VENCP 135
-/* 136 */
-#define RESET_VDAC 137
-/* 138-139 */
-#define RESET_VDI6 140
-#define RESET_VENCL 141
-#define RESET_I2C_M1 142
-#define RESET_I2C_M2 143
-/* 144-159 */
-/* RESET5 */
-/* 160-191 */
-/* RESET6 */
-#define RESET_GEN 192
-#define RESET_SPICC0 193
-#define RESET_SC 194
-#define RESET_SANA_3 195
-#define RESET_I2C_M0 196
-#define RESET_TS_PLL 197
-#define RESET_SPICC1 198
-#define RESET_STREAM 199
-#define RESET_TS_CPU 200
-#define RESET_UART0 201
-#define RESET_UART1_2 202
-#define RESET_ASYNC0 203
-#define RESET_ASYNC1 204
-#define RESET_SPIFC0 205
-#define RESET_I2C_M3 206
-/* 207-223 */
-/* RESET7 */
-#define RESET_USB_DDR_0 224
-#define RESET_USB_DDR_1 225
-#define RESET_USB_DDR_2 226
-#define RESET_USB_DDR_3 227
-#define RESET_TS_GPU 228
-#define RESET_DEVICE_MMC_ARB 229
-#define RESET_DVALIN_DMC_PIPL 230
-#define RESET_VID_LOCK 231
-#define RESET_NIC_DMC_PIPL 232
-#define RESET_DMC_VPU_PIPL 233
-#define RESET_GE2D_DMC_PIPL 234
-#define RESET_HCODEC_DMC_PIPL 235
-#define RESET_WAVE420_DMC_PIPL 236
-#define RESET_HEVCF_DMC_PIPL 237
-/* 238-255 */
-
-#endif
diff --git a/include/dt-bindings/reset/amlogic,meson-gxbb-reset.h b/include/dt-bindings/reset/amlogic,meson-gxbb-reset.h
deleted file mode 100644
index 883bfd3..0000000
--- a/include/dt-bindings/reset/amlogic,meson-gxbb-reset.h
+++ /dev/null
@@ -1,161 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause */
-/*
- * Copyright (c) 2016 BayLibre, SAS.
- * Author: Neil Armstrong <narmstrong@baylibre.com>
- */
-#ifndef _DT_BINDINGS_AMLOGIC_MESON_GXBB_RESET_H
-#define _DT_BINDINGS_AMLOGIC_MESON_GXBB_RESET_H
-
-/* RESET0 */
-#define RESET_HIU 0
-/* 1 */
-#define RESET_DOS_RESET 2
-#define RESET_DDR_TOP 3
-#define RESET_DCU_RESET 4
-#define RESET_VIU 5
-#define RESET_AIU 6
-#define RESET_VID_PLL_DIV 7
-/* 8 */
-#define RESET_PMUX 9
-#define RESET_VENC 10
-#define RESET_ASSIST 11
-#define RESET_AFIFO2 12
-#define RESET_VCBUS 13
-/* 14 */
-/* 15 */
-#define RESET_GIC 16
-#define RESET_CAPB3_DECODE 17
-#define RESET_NAND_CAPB3 18
-#define RESET_HDMITX_CAPB3 19
-#define RESET_MALI_CAPB3 20
-#define RESET_DOS_CAPB3 21
-#define RESET_SYS_CPU_CAPB3 22
-#define RESET_CBUS_CAPB3 23
-#define RESET_AHB_CNTL 24
-#define RESET_AHB_DATA 25
-#define RESET_VCBUS_CLK81 26
-#define RESET_MMC 27
-#define RESET_MIPI_0 28
-#define RESET_MIPI_1 29
-#define RESET_MIPI_2 30
-#define RESET_MIPI_3 31
-/* RESET1 */
-#define RESET_CPPM 32
-#define RESET_DEMUX 33
-#define RESET_USB_OTG 34
-#define RESET_DDR 35
-#define RESET_AO_RESET 36
-#define RESET_BT656 37
-#define RESET_AHB_SRAM 38
-/* 39 */
-#define RESET_PARSER 40
-#define RESET_BLKMV 41
-#define RESET_ISA 42
-#define RESET_ETHERNET 43
-#define RESET_SD_EMMC_A 44
-#define RESET_SD_EMMC_B 45
-#define RESET_SD_EMMC_C 46
-#define RESET_ROM_BOOT 47
-#define RESET_SYS_CPU_0 48
-#define RESET_SYS_CPU_1 49
-#define RESET_SYS_CPU_2 50
-#define RESET_SYS_CPU_3 51
-#define RESET_SYS_CPU_CORE_0 52
-#define RESET_SYS_CPU_CORE_1 53
-#define RESET_SYS_CPU_CORE_2 54
-#define RESET_SYS_CPU_CORE_3 55
-#define RESET_SYS_PLL_DIV 56
-#define RESET_SYS_CPU_AXI 57
-#define RESET_SYS_CPU_L2 58
-#define RESET_SYS_CPU_P 59
-#define RESET_SYS_CPU_MBIST 60
-#define RESET_ACODEC 61
-/* 62 */
-/* 63 */
-/* RESET2 */
-#define RESET_VD_RMEM 64
-#define RESET_AUDIN 65
-#define RESET_HDMI_TX 66
-/* 67 */
-/* 68 */
-/* 69 */
-#define RESET_GE2D 70
-#define RESET_PARSER_REG 71
-#define RESET_PARSER_FETCH 72
-#define RESET_PARSER_CTL 73
-#define RESET_PARSER_TOP 74
-/* 75 */
-/* 76 */
-#define RESET_AO_CPU_RESET 77
-#define RESET_MALI 78
-#define RESET_HDMI_SYSTEM_RESET 79
-/* 80-95 */
-/* RESET3 */
-#define RESET_RING_OSCILLATOR 96
-#define RESET_SYS_CPU 97
-#define RESET_EFUSE 98
-#define RESET_SYS_CPU_BVCI 99
-#define RESET_AIFIFO 100
-#define RESET_TVFE 101
-#define RESET_AHB_BRIDGE_CNTL 102
-/* 103 */
-#define RESET_AUDIO_DAC 104
-#define RESET_DEMUX_TOP 105
-#define RESET_DEMUX_DES 106
-#define RESET_DEMUX_S2P_0 107
-#define RESET_DEMUX_S2P_1 108
-#define RESET_DEMUX_RESET_0 109
-#define RESET_DEMUX_RESET_1 110
-#define RESET_DEMUX_RESET_2 111
-/* 112-127 */
-/* RESET4 */
-/* 128 */
-/* 129 */
-/* 130 */
-/* 131 */
-#define RESET_DVIN_RESET 132
-#define RESET_RDMA 133
-#define RESET_VENCI 134
-#define RESET_VENCP 135
-/* 136 */
-#define RESET_VDAC 137
-#define RESET_RTC 138
-/* 139 */
-#define RESET_VDI6 140
-#define RESET_VENCL 141
-#define RESET_I2C_MASTER_2 142
-#define RESET_I2C_MASTER_1 143
-/* 144-159 */
-/* RESET5 */
-/* 160-191 */
-/* RESET6 */
-#define RESET_PERIPHS_GENERAL 192
-#define RESET_PERIPHS_SPICC 193
-#define RESET_PERIPHS_SMART_CARD 194
-#define RESET_PERIPHS_SAR_ADC 195
-#define RESET_PERIPHS_I2C_MASTER_0 196
-#define RESET_SANA 197
-/* 198 */
-#define RESET_PERIPHS_STREAM_INTERFACE 199
-#define RESET_PERIPHS_SDIO 200
-#define RESET_PERIPHS_UART_0 201
-#define RESET_PERIPHS_UART_1_2 202
-#define RESET_PERIPHS_ASYNC_0 203
-#define RESET_PERIPHS_ASYNC_1 204
-#define RESET_PERIPHS_SPI_0 205
-#define RESET_PERIPHS_SDHC 206
-#define RESET_UART_SLIP 207
-/* 208-223 */
-/* RESET7 */
-#define RESET_USB_DDR_0 224
-#define RESET_USB_DDR_1 225
-#define RESET_USB_DDR_2 226
-#define RESET_USB_DDR_3 227
-/* 228 */
-#define RESET_DEVICE_MMC_ARB 229
-/* 230 */
-#define RESET_VID_LOCK 231
-#define RESET_A9_DMC_PIPEL 232
-/* 233-255 */
-
-#endif
diff --git a/include/dt-bindings/sound/meson-aiu.h b/include/dt-bindings/sound/meson-aiu.h
deleted file mode 100644
index 1051b8a..0000000
--- a/include/dt-bindings/sound/meson-aiu.h
+++ /dev/null
@@ -1,18 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 */
-#ifndef __DT_MESON_AIU_H
-#define __DT_MESON_AIU_H
-
-#define AIU_CPU 0
-#define AIU_HDMI 1
-#define AIU_ACODEC 2
-
-#define CPU_I2S_FIFO 0
-#define CPU_SPDIF_FIFO 1
-#define CPU_I2S_ENCODER 2
-#define CPU_SPDIF_ENCODER 3
-
-#define CTRL_I2S 0
-#define CTRL_PCM 1
-#define CTRL_OUT 2
-
-#endif /* __DT_MESON_AIU_H */
diff --git a/include/dt-bindings/sound/meson-g12a-toacodec.h b/include/dt-bindings/sound/meson-g12a-toacodec.h
deleted file mode 100644
index 69d7a75..0000000
--- a/include/dt-bindings/sound/meson-g12a-toacodec.h
+++ /dev/null
@@ -1,10 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 */
-#ifndef __DT_MESON_G12A_TOACODEC_H
-#define __DT_MESON_G12A_TOACODEC_H
-
-#define TOACODEC_IN_A 0
-#define TOACODEC_IN_B 1
-#define TOACODEC_IN_C 2
-#define TOACODEC_OUT 3
-
-#endif /* __DT_MESON_G12A_TOACODEC_H */
diff --git a/include/dt-bindings/sound/meson-g12a-tohdmitx.h b/include/dt-bindings/sound/meson-g12a-tohdmitx.h
deleted file mode 100644
index c5e1f48..0000000
--- a/include/dt-bindings/sound/meson-g12a-tohdmitx.h
+++ /dev/null
@@ -1,13 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 */
-#ifndef __DT_MESON_G12A_TOHDMITX_H
-#define __DT_MESON_G12A_TOHDMITX_H
-
-#define TOHDMITX_I2S_IN_A 0
-#define TOHDMITX_I2S_IN_B 1
-#define TOHDMITX_I2S_IN_C 2
-#define TOHDMITX_I2S_OUT 3
-#define TOHDMITX_SPDIF_IN_A 4
-#define TOHDMITX_SPDIF_IN_B 5
-#define TOHDMITX_SPDIF_OUT 6
-
-#endif /* __DT_MESON_G12A_TOHDMITX_H */
diff --git a/include/dwc3-omap-uboot.h b/include/dwc3-omap-uboot.h
index ed92bfc..f220705 100644
--- a/include/dwc3-omap-uboot.h
+++ b/include/dwc3-omap-uboot.h
@@ -27,5 +27,4 @@
int dwc3_omap_uboot_init(struct dwc3_omap_device *dev);
void dwc3_omap_uboot_exit(int index);
-int dwc3_omap_uboot_interrupt_status(struct udevice *dev);
#endif /* __DWC3_OMAP_UBOOT_H_ */
diff --git a/include/dwc3-uboot.h b/include/dwc3-uboot.h
index 35cfbb9..3689d60 100644
--- a/include/dwc3-uboot.h
+++ b/include/dwc3-uboot.h
@@ -44,7 +44,7 @@
int dwc3_uboot_init(struct dwc3_device *dev);
void dwc3_uboot_exit(int index);
-void dwc3_uboot_handle_interrupt(struct udevice *dev);
+int dwc3_uboot_interrupt_status(struct udevice *dev);
struct phy;
#if CONFIG_IS_ENABLED(PHY) && CONFIG_IS_ENABLED(DM_USB)
diff --git a/include/efi.h b/include/efi.h
index f0e5faa..c3c4b93 100644
--- a/include/efi.h
+++ b/include/efi.h
@@ -492,13 +492,14 @@
/*
* Variable Attributes
*/
-#define EFI_VARIABLE_NON_VOLATILE 0x0000000000000001
-#define EFI_VARIABLE_BOOTSERVICE_ACCESS 0x0000000000000002
-#define EFI_VARIABLE_RUNTIME_ACCESS 0x0000000000000004
-#define EFI_VARIABLE_HARDWARE_ERROR_RECORD 0x0000000000000008
-#define EFI_VARIABLE_AUTHENTICATED_WRITE_ACCESS 0x0000000000000010
-#define EFI_VARIABLE_TIME_BASED_AUTHENTICATED_WRITE_ACCESS 0x0000000000000020
-#define EFI_VARIABLE_APPEND_WRITE 0x0000000000000040
+#define EFI_VARIABLE_NON_VOLATILE 0x00000001
+#define EFI_VARIABLE_BOOTSERVICE_ACCESS 0x00000002
+#define EFI_VARIABLE_RUNTIME_ACCESS 0x00000004
+#define EFI_VARIABLE_HARDWARE_ERROR_RECORD 0x00000008
+#define EFI_VARIABLE_AUTHENTICATED_WRITE_ACCESS 0x00000010
+#define EFI_VARIABLE_TIME_BASED_AUTHENTICATED_WRITE_ACCESS 0x00000020
+#define EFI_VARIABLE_APPEND_WRITE 0x00000040
+#define EFI_VARIABLE_ENHANCED_AUTHENTICATED_ACCESS 0x00000080
#define EFI_VARIABLE_MASK (EFI_VARIABLE_NON_VOLATILE | \
EFI_VARIABLE_BOOTSERVICE_ACCESS | \
@@ -506,7 +507,8 @@
EFI_VARIABLE_HARDWARE_ERROR_RECORD | \
EFI_VARIABLE_AUTHENTICATED_WRITE_ACCESS | \
EFI_VARIABLE_TIME_BASED_AUTHENTICATED_WRITE_ACCESS | \
- EFI_VARIABLE_APPEND_WRITE)
+ EFI_VARIABLE_APPEND_WRITE | \
+ EFI_VARIABLE_ENHANCED_AUTHENTICATED_ACCESS)
/**
* efi_get_priv() - Get access to the EFI-private information
diff --git a/include/efi_variable.h b/include/efi_variable.h
index 805e6c5..42a2b7c 100644
--- a/include/efi_variable.h
+++ b/include/efi_variable.h
@@ -8,7 +8,7 @@
#include <linux/bitops.h>
-#define EFI_VARIABLE_READ_ONLY BIT(31)
+#define EFI_VARIABLE_READ_ONLY 0x80000000
enum efi_auth_var_type {
EFI_AUTH_VAR_NONE = 0,
diff --git a/include/env/phytec/rauc.env b/include/env/phytec/rauc.env
new file mode 100644
index 0000000..89e17ff
--- /dev/null
+++ b/include/env/phytec/rauc.env
@@ -0,0 +1,52 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+
+/* Logic to select a boot partition based on environment variables and switch
+ * to the other if the boot fails. */
+
+doraucboot=0
+
+raucbootpart0=1
+raucrootpart0=5
+raucbootpart1=2
+raucrootpart1=6
+
+raucinit=
+ echo Booting RAUC A/B system;
+ test -n "${BOOT_ORDER}" || env set BOOT_ORDER "system0 system1";
+ test -n "${BOOT_system0_LEFT}" || env set BOOT_system0_LEFT 3;
+ test -n "${BOOT_system1_LEFT}" || env set BOOT_system1_LEFT 3;
+ env set raucstatus;
+ for BOOT_SLOT in "${BOOT_ORDER}"; do
+ if test "x${raucstatus}" != "x"; then
+ echo Skipping remaing slots!;
+ elif test "x${BOOT_SLOT}" = "xsystem0"; then
+ if test ${BOOT_system0_LEFT} -gt 0; then
+ echo Found valid slot A, ${BOOT_system0_LEFT} attempts remaining;
+ setexpr BOOT_system0_LEFT ${BOOT_system0_LEFT} - 1;
+ env set mmcpart ${raucbootpart0};
+ env set mmcroot ${raucrootpart0};
+ env set raucargs rauc.slot=system0;
+ env set raucstatus success;
+ fi;
+ elif test "x${BOOT_SLOT}" = "xsystem1"; then
+ if test ${BOOT_system1_LEFT} -gt 0; then
+ echo Found valid slot B, ${BOOT_system1_LEFT} attempts remaining;
+ setexpr BOOT_system1_LEFT ${BOOT_system1_LEFT} - 1;
+ env set mmcpart ${raucbootpart1};
+ env set mmcroot ${raucrootpart1};
+ env set raucargs rauc.slot=system1;
+ env set raucstatus success;
+ fi;
+ fi;
+ done;
+ if test -n "${raucstatus}"; then
+ env delete raucstatus;
+ env save;
+ else
+ echo WARN: No valid slot found;
+ env set BOOT_system0_LEFT 3;
+ env set BOOT_system1_LEFT 3;
+ env delete raucstatus;
+ env save;
+ reset;
+ fi;
diff --git a/include/fastboot-internal.h b/include/fastboot-internal.h
index 610d4f9..e59c187 100644
--- a/include/fastboot-internal.h
+++ b/include/fastboot-internal.h
@@ -6,7 +6,7 @@
/**
* fastboot_buf_addr - base address of the fastboot download buffer
*/
-extern void *fastboot_buf_addr;
+extern ulong fastboot_buf_addr;
/**
* fastboot_buf_size - size of the fastboot download buffer
diff --git a/include/fastboot.h b/include/fastboot.h
index 1e7920e..c75184c 100644
--- a/include/fastboot.h
+++ b/include/fastboot.h
@@ -114,13 +114,13 @@
*/
void fastboot_set_progress_callback(void (*progress)(const char *msg));
-/*
+/**
* fastboot_init() - initialise new fastboot protocol session
*
- * @buf_addr: Pointer to download buffer, or NULL for default
+ * @buf_addr: Address of download buffer, or 0 for default
* @buf_size: Size of download buffer, or zero for default
*/
-void fastboot_init(void *buf_addr, u32 buf_size);
+void fastboot_init(ulong buf_addr, u32 buf_size);
/**
* fastboot_boot() - Execute fastboot boot command
diff --git a/include/host_arch.h b/include/host_arch.h
index 169d494..261194b 100644
--- a/include/host_arch.h
+++ b/include/host_arch.h
@@ -16,6 +16,8 @@
export HOST_ARCH_X86_64=0x8664
#endif
+#include <version.h>
+
#define HOST_ARCH_AARCH64 0xaa64
#define HOST_ARCH_ARM 0x00a7
#define HOST_ARCH_RISCV32 0x5032
diff --git a/include/imx_container.h b/include/imx_container.h
index 54cd684..691c764 100644
--- a/include/imx_container.h
+++ b/include/imx_container.h
@@ -50,10 +50,10 @@
u8 length_lsb;
u8 length_msb;
u8 tag;
- u16 srk_table_offset;
u16 cert_offset;
- u16 blob_offset;
+ u16 srk_table_offset;
u16 signature_offset;
+ u16 blob_offset;
u32 reserved;
} __packed;
diff --git a/include/linux/arm-smccc.h b/include/linux/arm-smccc.h
index f44e9e8..da3d29a 100644
--- a/include/linux/arm-smccc.h
+++ b/include/linux/arm-smccc.h
@@ -55,8 +55,14 @@
#define ARM_SMCCC_QUIRK_NONE 0
#define ARM_SMCCC_QUIRK_QCOM_A6 1 /* Save/restore register a6 */
+#define ARM_SMCCC_VERSION 0x80000000
#define ARM_SMCCC_ARCH_FEATURES 0x80000001
+#define ARM_SMCCC_VERSION_1_0 0x10000
+#define ARM_SMCCC_VERSION_1_1 0x10001
+#define ARM_SMCCC_VERSION_1_2 0x10002
+#define ARM_SMCCC_VERSION_1_3 0x10003
+
#define ARM_SMCCC_RET_NOT_SUPPORTED ((unsigned long)-1)
#ifndef __ASSEMBLY__
diff --git a/include/pci_ids.h b/include/pci_ids.h
index b63bf45..f1886c3 100644
--- a/include/pci_ids.h
+++ b/include/pci_ids.h
@@ -2710,6 +2710,8 @@
#define PCI_DEVICE_ID_INTEL_I211_COPPER 0x1539
#define PCI_DEVICE_ID_INTEL_I210_COPPER_FLASHLESS 0x157b
#define PCI_DEVICE_ID_INTEL_I210_SERDES_FLASHLESS 0x157c
+#define PCI_DEVICE_ID_INTEL_I225_UNPROGRAMMED 0x15dF
+#define PCI_DEVICE_ID_INTEL_I225_IT 0x0d9f
#define PCI_DEVICE_ID_INTEL_80960_RP 0x1960
#define PCI_DEVICE_ID_INTEL_82840_HB 0x1a21
#define PCI_DEVICE_ID_INTEL_82845_HB 0x1a30
diff --git a/include/phy.h b/include/phy.h
index ae23814..90b7e36 100644
--- a/include/phy.h
+++ b/include/phy.h
@@ -184,6 +184,15 @@
int phy_reset(struct phy_device *phydev);
/**
+ * phy_gpio_reset() - Resets the specified PHY using GPIO reset
+ * Toggles the optional PHY reset GPIO
+ *
+ * @dev: PHY udevice to reset
+ * @return: 0 if OK, -ve on error
+ */
+int phy_gpio_reset(struct udevice *dev);
+
+/**
* phy_find_by_mask() - Searches for a PHY on the specified MDIO bus
* The function checks the PHY addresses flagged in phy_mask and returns a
* phy_device pointer if it detects a PHY.
diff --git a/include/power/rk8xx_pmic.h b/include/power/rk8xx_pmic.h
index 3cbfc02..31221aa 100644
--- a/include/power/rk8xx_pmic.h
+++ b/include/power/rk8xx_pmic.h
@@ -183,7 +183,18 @@
};
enum {
+ RK806_POWER_SLP_EN0 = 0x06,
+ RK806_POWER_SLP_EN1,
+ RK806_POWER_SLP_EN2,
+ RK806_REG_SYS_CFG3 = 0x72,
+ RK806_WDT_REG,
+ RK806_ON_SOURCE,
+ RK806_OFF_SOURCE
+};
+
+enum {
RK805_ID = 0x8050,
+ RK806_ID = 0x8060,
RK808_ID = 0x0000,
RK809_ID = 0x8090,
RK816_ID = 0x8160,
@@ -201,6 +212,14 @@
#define RK817_POWER_EN_SAVE0 0x99
#define RK817_POWER_EN_SAVE1 0xa4
+#define RK806_POWER_EN(x) (0x00 + (x))
+/* POWER_ENx register lower 4 bits are write-protected unless the associated top bit is set */
+#define RK806_POWER_EN_CLRSETBITS(bit, val) (((val) << (bit)) | (1 << ((bit) + 4)))
+
+#define RK806_POWER_SLP_EN(x) (0x06 + (x))
+
+#define RK806_ID_MSB 0x5a
+#define RK806_ID_LSB 0x5b
#define RK817_ID_MSB 0xed
#define RK817_ID_LSB 0xee
#define RK8XX_ID_MSK 0xfff0
@@ -233,7 +252,5 @@
};
int rk8xx_spl_configure_buck(struct udevice *pmic, int buck, int uvolt);
-int rk818_spl_configure_usb_input_current(struct udevice *pmic, int current_ma);
-int rk818_spl_configure_usb_chrg_shutdown(struct udevice *pmic, int uvolt);
#endif
diff --git a/include/remoteproc.h b/include/remoteproc.h
index 91a8879..6f8068e 100644
--- a/include/remoteproc.h
+++ b/include/remoteproc.h
@@ -403,6 +403,7 @@
* @name: Platform-specific way of naming the Remote proc
* @mem_type: one of 'enum rproc_mem_type'
* @driver_plat_data: driver specific platform data that may be needed.
+ * @fw_name: firmware name
*
* This can be accessed with dev_get_uclass_plat() for any UCLASS_REMOTEPROC
* device.
@@ -412,6 +413,7 @@
const char *name;
enum rproc_mem_type mem_type;
void *driver_plat_data;
+ char *fw_name;
};
/**
@@ -705,6 +707,34 @@
struct resource_table *rproc_find_resource_table(struct udevice *dev,
unsigned int addr,
int *tablesz);
+/**
+ * rproc_set_firmware() - assign a new firmware name
+ * @rproc_dev: device for which new firmware name is being assigned
+ * @fw_name: new firmware name to be assigned
+ *
+ * This function allows remoteproc drivers or clients to configure a custom
+ * firmware name. The function does not trigger a remote processor boot,
+ * only sets the firmware name used for a subsequent boot.
+ *
+ * This function sets the fw_name field in uclass pdata of the Remote proc
+ *
+ * Return: 0 on success or a negative value upon failure
+ */
+int rproc_set_firmware(struct udevice *rproc_dev, const char *fw_name);
+
+/**
+ * rproc_boot() - boot a remote processor
+ * @rproc_dev: rproc device to boot
+ *
+ * Boot a remote processor (i.e. load its firmware, power it on, ...).
+ *
+ * This function first loads the firmware set in the uclass pdata of Remote
+ * processor to a buffer and then loads firmware to the remote processor
+ * using rproc_load().
+ *
+ * Return: 0 on success, and an appropriate error value otherwise
+ */
+int rproc_boot(struct udevice *rproc_dev);
#else
static inline int rproc_init(void) { return -ENOSYS; }
static inline int rproc_dev_init(int id) { return -ENOSYS; }
@@ -744,6 +774,10 @@
ulong fw_size, ulong *rsc_addr,
ulong *rsc_size)
{ return -ENOSYS; }
+static inline int rproc_set_firmware(struct udevice *rproc_dev, const char *fw_name)
+{ return -ENOSYS; }
+static inline int rproc_boot(struct udevice *rproc_dev)
+{ return -ENOSYS; }
#endif
#endif /* _RPROC_H_ */
diff --git a/include/smbios.h b/include/smbios.h
index 3df8827..a4fda9d 100644
--- a/include/smbios.h
+++ b/include/smbios.h
@@ -108,6 +108,33 @@
char eos[SMBIOS_STRUCT_EOS_BYTES];
};
+/**
+ * enum smbios_wakeup_type - wake-up type
+ *
+ * These constants are used for the Wake-Up Type field in the SMBIOS
+ * System Information (Type 1) structure.
+ */
+enum smbios_wakeup_type {
+ /** @SMBIOS_WAKEUP_TYPE_RESERVED: Reserved */
+ SMBIOS_WAKEUP_TYPE_RESERVED,
+ /** @SMBIOS_WAKEUP_TYPE_OTHER: Other */
+ SMBIOS_WAKEUP_TYPE_OTHER,
+ /** @SMBIOS_WAKEUP_TYPE_UNKNOWN: Unknown */
+ SMBIOS_WAKEUP_TYPE_UNKNOWN,
+ /** @SMBIOS_WAKEUP_TYPE_APM_TIMER: APM Timer */
+ SMBIOS_WAKEUP_TYPE_APM_TIMER,
+ /** @SMBIOS_WAKEUP_TYPE_MODEM_RING: Modem Ring */
+ SMBIOS_WAKEUP_TYPE_MODEM_RING,
+ /** @SMBIOS_WAKEUP_TYPE_LAN_REMOTE: LAN Remote */
+ SMBIOS_WAKEUP_TYPE_LAN_REMOTE,
+ /** @SMBIOS_WAKEUP_TYPE_POWER_SWITCH: Power Switch */
+ SMBIOS_WAKEUP_TYPE_POWER_SWITCH,
+ /** @SMBIOS_WAKEUP_TYPE_PCI_PME: PCI PME# */
+ SMBIOS_WAKEUP_TYPE_PCI_PME,
+ /** @SMBIOS_WAKEUP_TYPE_AC_POWER_RESTORED: AC Power Restored */
+ SMBIOS_WAKEUP_TYPE_AC_POWER_RESTORED,
+};
+
struct __packed smbios_type1 {
u8 type;
u8 length;
diff --git a/include/turris-omnia-mcu-interface.h b/include/turris-omnia-mcu-interface.h
new file mode 100644
index 0000000..3c4638f
--- /dev/null
+++ b/include/turris-omnia-mcu-interface.h
@@ -0,0 +1,248 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * CZ.NIC's Turris Omnia MCU I2C interface commands definitions
+ *
+ * 2023 by Marek Behún <kabel@kernel.org>
+ */
+
+#ifndef __TURRIS_OMNIA_MCU_INTERFACE_H
+#define __TURRIS_OMNIA_MCU_INTERFACE_H
+
+#include <linux/bitops.h>
+
+enum omnia_commands_e {
+ CMD_GET_STATUS_WORD = 0x01, /* slave sends status word back */
+ CMD_GENERAL_CONTROL = 0x02,
+ CMD_LED_MODE = 0x03, /* default/user */
+ CMD_LED_STATE = 0x04, /* LED on/off */
+ CMD_LED_COLOR = 0x05, /* LED number + RED + GREEN + BLUE */
+ CMD_USER_VOLTAGE = 0x06,
+ CMD_SET_BRIGHTNESS = 0x07,
+ CMD_GET_BRIGHTNESS = 0x08,
+ CMD_GET_RESET = 0x09,
+ CMD_GET_FW_VERSION_APP = 0x0A, /* 20B git hash number */
+ CMD_SET_WATCHDOG_STATE = 0x0B, /* 0 - disable
+ * 1 - enable / ping
+ * after boot watchdog is started
+ * with 2 minutes timeout
+ */
+
+ /* CMD_WATCHDOG_STATUS = 0x0C, not implemented anymore */
+
+ CMD_GET_WATCHDOG_STATE = 0x0D,
+ CMD_GET_FW_VERSION_BOOT = 0x0E, /* 20B git hash number */
+ CMD_GET_FW_CHECKSUM = 0x0F, /* 4B length, 4B checksum */
+
+ /* available if FEATURES_SUPPORTED bit set in status word */
+ CMD_GET_FEATURES = 0x10,
+
+ /* available if EXT_CMD bit set in features */
+ CMD_GET_EXT_STATUS_DWORD = 0x11,
+ CMD_EXT_CONTROL = 0x12,
+ CMD_GET_EXT_CONTROL_STATUS = 0x13,
+
+ /* available if NEW_INT_API bit set in features */
+ CMD_GET_INT_AND_CLEAR = 0x14,
+ CMD_GET_INT_MASK = 0x15,
+ CMD_SET_INT_MASK = 0x16,
+
+ /* available if FLASHING bit set in features */
+ CMD_FLASH = 0x19,
+
+ /* available if WDT_PING bit set in features */
+ CMD_SET_WDT_TIMEOUT = 0x20,
+ CMD_GET_WDT_TIMELEFT = 0x21,
+
+ /* available if POWEROFF_WAKEUP bit set in features */
+ CMD_SET_WAKEUP = 0x22,
+ CMD_GET_UPTIME_AND_WAKEUP = 0x23,
+ CMD_POWER_OFF = 0x24,
+
+ /* available if USB_OVC_PROT_SETTING bit set in features */
+ CMD_SET_USB_OVC_PROT = 0x25,
+ CMD_GET_USB_OVC_PROT = 0x26,
+
+ /* available if TRNG bit set in features */
+ CMD_TRNG_COLLECT_ENTROPY = 0x28,
+
+ /* available if CRYPTO bit set in features */
+ CMD_CRYPTO_GET_PUBLIC_KEY = 0x29,
+ CMD_CRYPTO_SIGN_MESSAGE = 0x2A,
+ CMD_CRYPTO_COLLECT_SIGNATURE = 0x2B,
+
+ /* available if BOARD_INFO it set in features */
+ CMD_BOARD_INFO_GET = 0x2C,
+ CMD_BOARD_INFO_BURN = 0x2D,
+
+ /* available only at address 0x2b (led-controller) */
+ /* available only if LED_GAMMA_CORRECTION bit set in features */
+ CMD_SET_GAMMA_CORRECTION = 0x30,
+ CMD_GET_GAMMA_CORRECTION = 0x31,
+
+ /* available only at address 0x2b (led-controller) */
+ /* available only if PER_LED_CORRECTION bit set in features */
+ /* available only if FROM_BIT_16_INVALID bit NOT set in features */
+ CMD_SET_LED_CORRECTIONS = 0x32,
+ CMD_GET_LED_CORRECTIONS = 0x33,
+};
+
+enum omnia_flashing_commands_e {
+ FLASH_CMD_UNLOCK = 0x01,
+ FLASH_CMD_SIZE_AND_CSUM = 0x02,
+ FLASH_CMD_PROGRAM = 0x03,
+ FLASH_CMD_RESET = 0x04,
+};
+
+enum omnia_sts_word_e {
+ STS_MCU_TYPE_MASK = GENMASK(1, 0),
+ STS_MCU_TYPE_STM32 = 0 << 0,
+ STS_MCU_TYPE_GD32 = 1 << 0,
+ STS_MCU_TYPE_MKL = 2 << 0,
+ STS_FEATURES_SUPPORTED = BIT(2),
+ STS_USER_REGULATOR_NOT_SUPPORTED = BIT(3),
+ STS_CARD_DET = BIT(4),
+ STS_MSATA_IND = BIT(5),
+ STS_USB30_OVC = BIT(6),
+ STS_USB31_OVC = BIT(7),
+ STS_USB30_PWRON = BIT(8),
+ STS_USB31_PWRON = BIT(9),
+ STS_ENABLE_4V5 = BIT(10),
+ STS_BUTTON_MODE = BIT(11),
+ STS_BUTTON_PRESSED = BIT(12),
+ STS_BUTTON_COUNTER_MASK = GENMASK(15, 13)
+};
+
+enum omnia_ctl_byte_e {
+ CTL_LIGHT_RST = BIT(0),
+ CTL_HARD_RST = BIT(1),
+ /* BIT(2) is currently reserved */
+ CTL_USB30_PWRON = BIT(3),
+ CTL_USB31_PWRON = BIT(4),
+ CTL_ENABLE_4V5 = BIT(5),
+ CTL_BUTTON_MODE = BIT(6),
+ CTL_BOOTLOADER = BIT(7)
+};
+
+enum omnia_features_e {
+ FEAT_PERIPH_MCU = BIT(0),
+ FEAT_EXT_CMDS = BIT(1),
+ FEAT_WDT_PING = BIT(2),
+ FEAT_LED_STATE_EXT_MASK = GENMASK(4, 3),
+ FEAT_LED_STATE_EXT = 1 << 3,
+ FEAT_LED_STATE_EXT_V32 = 2 << 3,
+ FEAT_LED_GAMMA_CORRECTION = BIT(5),
+ FEAT_NEW_INT_API = BIT(6),
+ FEAT_BOOTLOADER = BIT(7),
+ FEAT_FLASHING = BIT(8),
+ FEAT_NEW_MESSAGE_API = BIT(9),
+ FEAT_BRIGHTNESS_INT = BIT(10),
+ FEAT_POWEROFF_WAKEUP = BIT(11),
+ FEAT_CAN_OLD_MESSAGE_API = BIT(12),
+ FEAT_TRNG = BIT(13),
+ FEAT_CRYPTO = BIT(14),
+ FEAT_BOARD_INFO = BIT(15),
+
+ /*
+ * Orginally the features command replied only 16 bits. If more were
+ * read, either the I2C transaction failed or 0xff bytes were sent.
+ * Therefore to consider bits 16 - 31 valid, one bit (20) was reserved
+ * to be zero.
+ */
+
+ /* Bits 16 - 19 correspond to bits 0 - 3 of status word */
+ FEAT_MCU_TYPE_MASK = GENMASK(17, 16),
+ FEAT_MCU_TYPE_STM32 = 0 << 16,
+ FEAT_MCU_TYPE_GD32 = 1 << 16,
+ FEAT_MCU_TYPE_MKL = 2 << 16,
+ FEAT_FEATURES_SUPPORTED = BIT(18),
+ FEAT_USER_REGULATOR_NOT_SUPPORTED = BIT(19),
+
+ /* must not be set */
+ FEAT_FROM_BIT_16_INVALID = BIT(20),
+
+ FEAT_PER_LED_CORRECTION = BIT(21),
+ FEAT_USB_OVC_PROT_SETTING = BIT(22),
+};
+
+enum omnia_ext_sts_dword_e {
+ EXT_STS_SFP_nDET = BIT(0),
+ EXT_STS_LED_STATES_MASK = GENMASK(31, 12),
+ EXT_STS_WLAN0_MSATA_LED = BIT(12),
+ EXT_STS_WLAN1_LED = BIT(13),
+ EXT_STS_WLAN2_LED = BIT(14),
+ EXT_STS_WPAN0_LED = BIT(15),
+ EXT_STS_WPAN1_LED = BIT(16),
+ EXT_STS_WPAN2_LED = BIT(17),
+ EXT_STS_WAN_LED0 = BIT(18),
+ EXT_STS_WAN_LED1 = BIT(19),
+ EXT_STS_LAN0_LED0 = BIT(20),
+ EXT_STS_LAN0_LED1 = BIT(21),
+ EXT_STS_LAN1_LED0 = BIT(22),
+ EXT_STS_LAN1_LED1 = BIT(23),
+ EXT_STS_LAN2_LED0 = BIT(24),
+ EXT_STS_LAN2_LED1 = BIT(25),
+ EXT_STS_LAN3_LED0 = BIT(26),
+ EXT_STS_LAN3_LED1 = BIT(27),
+ EXT_STS_LAN4_LED0 = BIT(28),
+ EXT_STS_LAN4_LED1 = BIT(29),
+ EXT_STS_LAN5_LED0 = BIT(30),
+ EXT_STS_LAN5_LED1 = BIT(31),
+};
+
+enum omnia_ext_ctl_e {
+ EXT_CTL_nRES_MMC = BIT(0),
+ EXT_CTL_nRES_LAN = BIT(1),
+ EXT_CTL_nRES_PHY = BIT(2),
+ EXT_CTL_nPERST0 = BIT(3),
+ EXT_CTL_nPERST1 = BIT(4),
+ EXT_CTL_nPERST2 = BIT(5),
+ EXT_CTL_PHY_SFP = BIT(6),
+ EXT_CTL_PHY_SFP_AUTO = BIT(7),
+ EXT_CTL_nVHV_CTRL = BIT(8),
+};
+
+enum omnia_int_e {
+ INT_CARD_DET = BIT(0),
+ INT_MSATA_IND = BIT(1),
+ INT_USB30_OVC = BIT(2),
+ INT_USB31_OVC = BIT(3),
+ INT_BUTTON_PRESSED = BIT(4),
+ INT_SFP_nDET = BIT(5),
+ INT_BRIGHTNESS_CHANGED = BIT(6),
+ INT_TRNG = BIT(7),
+ INT_MESSAGE_SIGNED = BIT(8),
+
+ INT_LED_STATES_MASK = GENMASK(31, 12),
+ INT_WLAN0_MSATA_LED = BIT(12),
+ INT_WLAN1_LED = BIT(13),
+ INT_WLAN2_LED = BIT(14),
+ INT_WPAN0_LED = BIT(15),
+ INT_WPAN1_LED = BIT(16),
+ INT_WPAN2_LED = BIT(17),
+ INT_WAN_LED0 = BIT(18),
+ INT_WAN_LED1 = BIT(19),
+ INT_LAN0_LED0 = BIT(20),
+ INT_LAN0_LED1 = BIT(21),
+ INT_LAN1_LED0 = BIT(22),
+ INT_LAN1_LED1 = BIT(23),
+ INT_LAN2_LED0 = BIT(24),
+ INT_LAN2_LED1 = BIT(25),
+ INT_LAN3_LED0 = BIT(26),
+ INT_LAN3_LED1 = BIT(27),
+ INT_LAN4_LED0 = BIT(28),
+ INT_LAN4_LED1 = BIT(29),
+ INT_LAN5_LED0 = BIT(30),
+ INT_LAN5_LED1 = BIT(31),
+};
+
+enum omnia_cmd_poweroff_e {
+ CMD_POWER_OFF_POWERON_BUTTON = BIT(0),
+ CMD_POWER_OFF_MAGIC = 0xdead,
+};
+
+enum cmd_usb_ovc_prot_e {
+ CMD_xET_USB_OVC_PROT_PORT_MASK = GENMASK(3, 0),
+ CMD_xET_USB_OVC_PROT_ENABLE = BIT(4),
+};
+
+#endif /* __TURRIS_OMNIA_MCU_INTERFACE_H */
diff --git a/include/usb_mass_storage.h b/include/usb_mass_storage.h
index 83ab93b..6d83d93 100644
--- a/include/usb_mass_storage.h
+++ b/include/usb_mass_storage.h
@@ -7,7 +7,6 @@
#ifndef __USB_MASS_STORAGE_H__
#define __USB_MASS_STORAGE_H__
-#define SECTOR_SIZE 0x200
#include <part.h>
#include <linux/usb/composite.h>
diff --git a/include/video_console.h b/include/video_console.h
index bde67fa..8b5928d 100644
--- a/include/video_console.h
+++ b/include/video_console.h
@@ -43,6 +43,7 @@
* @col_saved: Saved X position, in fractional units (VID_TO_POS(x))
* @row_saved: Saved Y position in pixels (0=top)
* @escape_buf: Buffer to accumulate escape sequence
+ * @utf8_buf: Buffer to accumulate UTF-8 byte sequence
*/
struct vidconsole_priv {
struct stdio_dev sdev;
@@ -66,6 +67,7 @@
int row_saved;
int col_saved;
char escape_buf[32];
+ char utf8_buf[5];
};
/**
@@ -124,12 +126,12 @@
* @x_frac: Fractional pixel X position (0=left-most pixel) which
* is the X position multipled by VID_FRAC_DIV.
* @y: Pixel Y position (0=top-most pixel)
- * @ch: Character to write
+ * @cp: UTF-32 code point to write
* @return number of fractional pixels that the cursor should move,
* if all is OK, -EAGAIN if we ran out of space on this line, other -ve
* on error
*/
- int (*putc_xy)(struct udevice *dev, uint x_frac, uint y, char ch);
+ int (*putc_xy)(struct udevice *dev, uint x_frac, uint y, int cp);
/**
* move_rows() - Move text rows from one place to another
@@ -403,12 +405,12 @@
* @x_frac: Fractional pixel X position (0=left-most pixel) which
* is the X position multipled by VID_FRAC_DIV.
* @y: Pixel Y position (0=top-most pixel)
- * @ch: Character to write
+ * @cp: UTF-32 code point to write
* Return: number of fractional pixels that the cursor should move,
* if all is OK, -EAGAIN if we ran out of space on this line, other -ve
* on error
*/
-int vidconsole_putc_xy(struct udevice *dev, uint x, uint y, char ch);
+int vidconsole_putc_xy(struct udevice *dev, uint x, uint y, int cp);
/**
* vidconsole_move_rows() - Move text rows from one place to another
diff --git a/lib/acpi/acpi_table.c b/lib/acpi/acpi_table.c
index 39dd53e..c16ead6 100644
--- a/lib/acpi/acpi_table.c
+++ b/lib/acpi/acpi_table.c
@@ -116,7 +116,7 @@
memcpy(header->oem_id, OEM_ID, 6);
memcpy(header->oem_table_id, OEM_TABLE_ID, 8);
header->oem_revision = OEM_REVISION;
- memcpy(header->aslc_id, ASLC_ID, 4);
+ memcpy(header->creator_id, ASLC_ID, 4);
}
void acpi_align(struct acpi_ctx *ctx)
@@ -219,7 +219,7 @@
header->revision = acpi_get_table_revision(ACPITAB_DBG2);
acpi_fill_header(header, "DBG2");
- header->aslc_revision = ASL_REVISION;
+ header->creator_revision = ASL_REVISION;
/* One debug device defined */
dbg2->devices_offset = sizeof(struct acpi_dbg2_header);
diff --git a/lib/acpi/ssdt.c b/lib/acpi/ssdt.c
index b0a96f8..e032e26 100644
--- a/lib/acpi/ssdt.c
+++ b/lib/acpi/ssdt.c
@@ -23,7 +23,7 @@
acpi_fill_header(ssdt, "SSDT");
ssdt->revision = acpi_get_table_revision(ACPITAB_SSDT);
- ssdt->aslc_revision = 1;
+ ssdt->creator_revision = 1;
ssdt->length = sizeof(struct acpi_table_header);
acpi_inc(ctx, sizeof(struct acpi_table_header));
diff --git a/lib/charset.c b/lib/charset.c
index 2b43175..df4f040 100644
--- a/lib/charset.c
+++ b/lib/charset.c
@@ -15,7 +15,7 @@
/**
* codepage_437 - Unicode to codepage 437 translation table
*/
-const u16 codepage_437[128] = CP437;
+const u16 codepage_437[160] = CP437;
static struct capitalization_table capitalization_table[] =
#ifdef CONFIG_EFI_UNICODE_CAPITALIZATION
@@ -516,9 +516,12 @@
int j;
/* Look up codepage translation */
- for (j = 0; j < 0x80; ++j) {
+ for (j = 0; j < 0xA0; ++j) {
if (*c == codepage[j]) {
- *c = j + 0x80;
+ if (j < 0x20)
+ *c = j;
+ else
+ *c = j + 0x60;
return 0;
}
}
diff --git a/lib/efi_loader/Kconfig b/lib/efi_loader/Kconfig
index a7c3e05..e13a6f9 100644
--- a/lib/efi_loader/Kconfig
+++ b/lib/efi_loader/Kconfig
@@ -44,7 +44,6 @@
config EFI_BOOTMGR
bool "UEFI Boot Manager"
default y
- select BOOTMETH_GLOBAL if BOOTSTD
help
Select this option if you want to select the UEFI binary to be booted
via UEFI variables Boot####, BootOrder, and BootNext. You should also
diff --git a/lib/efi_loader/Makefile b/lib/efi_loader/Makefile
index fcb0af7..086521f 100644
--- a/lib/efi_loader/Makefile
+++ b/lib/efi_loader/Makefile
@@ -6,8 +6,7 @@
# This file only gets included with CONFIG_EFI_LOADER set, so all
# object inclusion implicitly depends on it
-asflags-y += -DHOST_ARCH="$(HOST_ARCH)" -I.
-ccflags-y += -DHOST_ARCH="$(HOST_ARCH)"
+asflags-y += -I.
CFLAGS_efi_boottime.o += \
-DFW_VERSION="0x$(VERSION)" \
diff --git a/lib/efi_loader/efi_bootbin.c b/lib/efi_loader/efi_bootbin.c
index 733cc1a..b7910f7 100644
--- a/lib/efi_loader/efi_bootbin.c
+++ b/lib/efi_loader/efi_bootbin.c
@@ -125,7 +125,7 @@
efi_handle_t mem_handle = NULL, handle;
struct efi_device_path *file_path = NULL;
struct efi_device_path *msg_path;
- efi_status_t ret, ret2;
+ efi_status_t ret;
u16 *load_options;
if (!bootefi_device_path || !bootefi_image_path) {
@@ -172,11 +172,17 @@
ret = do_bootefi_exec(handle, load_options);
out:
- ret2 = efi_uninstall_multiple_protocol_interfaces(mem_handle,
- &efi_guid_device_path,
- file_path, NULL);
+ if (mem_handle) {
+ efi_status_t r;
+
+ r = efi_uninstall_multiple_protocol_interfaces(
+ mem_handle, &efi_guid_device_path, file_path, NULL);
+ if (r != EFI_SUCCESS)
+ log_err("Uninstalling protocol interfaces failed\n");
+ }
efi_free_pool(file_path);
- return (ret != EFI_SUCCESS) ? ret : ret2;
+
+ return ret;
}
/**
diff --git a/lib/efi_loader/efi_helper.c b/lib/efi_loader/efi_helper.c
index 5dd9cc8..58761fa 100644
--- a/lib/efi_loader/efi_helper.c
+++ b/lib/efi_loader/efi_helper.c
@@ -456,11 +456,11 @@
return EFI_LOAD_ERROR;
}
- /* Create memory reservations as indicated by the device tree */
- efi_carve_out_dt_rsv(fdt);
-
- if (CONFIG_IS_ENABLED(GENERATE_ACPI_TABLE))
+ if (CONFIG_IS_ENABLED(GENERATE_ACPI_TABLE)) {
+ /* Create memory reservations as indicated by the device tree */
+ efi_carve_out_dt_rsv(fdt);
return EFI_SUCCESS;
+ }
/* Prepare device tree for payload */
ret = copy_fdt(&fdt);
@@ -474,6 +474,9 @@
return EFI_LOAD_ERROR;
}
+ /* Create memory reservations as indicated by the device tree */
+ efi_carve_out_dt_rsv(fdt);
+
efi_try_purge_kaslr_seed(fdt);
if (CONFIG_IS_ENABLED(EFI_TCG2_PROTOCOL_MEASURE_DTB)) {
diff --git a/lib/efi_loader/efi_memory.c b/lib/efi_loader/efi_memory.c
index edfad2d..aba3100 100644
--- a/lib/efi_loader/efi_memory.c
+++ b/lib/efi_loader/efi_memory.c
@@ -933,8 +933,8 @@
* Add Runtime Services. We mark surrounding boottime code as runtime as
* well to fulfill the runtime alignment constraints but avoid padding.
*/
- runtime_start = (ulong)&__efi_runtime_start & ~runtime_mask;
- runtime_end = (ulong)&__efi_runtime_stop;
+ runtime_start = (uintptr_t)__efi_runtime_start & ~runtime_mask;
+ runtime_end = (uintptr_t)__efi_runtime_stop;
runtime_end = (runtime_end + runtime_mask) & ~runtime_mask;
runtime_pages = (runtime_end - runtime_start) >> EFI_PAGE_SHIFT;
efi_add_memory_map_pg(runtime_start, runtime_pages,
diff --git a/lib/efi_loader/efi_runtime.c b/lib/efi_loader/efi_runtime.c
index 18da689..a61c9a7 100644
--- a/lib/efi_loader/efi_runtime.c
+++ b/lib/efi_loader/efi_runtime.c
@@ -15,6 +15,7 @@
#include <rtc.h>
#include <asm/global_data.h>
#include <u-boot/crc.h>
+#include <asm/sections.h>
/* For manual relocation support */
DECLARE_GLOBAL_DATA_PTR;
@@ -668,14 +669,14 @@
void efi_runtime_relocate(ulong offset, struct efi_mem_desc *map)
{
#ifdef IS_RELA
- struct elf_rela *rel = (void*)&__efi_runtime_rel_start;
+ struct elf_rela *rel = (void *)__efi_runtime_rel_start;
#else
- struct elf_rel *rel = (void*)&__efi_runtime_rel_start;
+ struct elf_rel *rel = (void *)__efi_runtime_rel_start;
static ulong lastoff = CONFIG_TEXT_BASE;
#endif
debug("%s: Relocating to offset=%lx\n", __func__, offset);
- for (; (ulong)rel < (ulong)&__efi_runtime_rel_stop; rel++) {
+ for (; (uintptr_t)rel < (uintptr_t)__efi_runtime_rel_stop; rel++) {
ulong base = CONFIG_TEXT_BASE;
ulong *p;
ulong newaddr;
diff --git a/lib/efi_loader/efi_unicode_collation.c b/lib/efi_loader/efi_unicode_collation.c
index 2b6912c..627bb91 100644
--- a/lib/efi_loader/efi_unicode_collation.c
+++ b/lib/efi_loader/efi_unicode_collation.c
@@ -256,7 +256,7 @@
for (i = 0; i < fat_size; ++i) {
c = (unsigned char)fat[i];
if (c > 0x80)
- c = codepage[c - 0x80];
+ c = codepage[c - 0x60];
string[i] = c;
if (!c)
break;
diff --git a/lib/efi_loader/efi_var_common.c b/lib/efi_loader/efi_var_common.c
index d528747..16b2c3d 100644
--- a/lib/efi_loader/efi_var_common.c
+++ b/lib/efi_loader/efi_var_common.c
@@ -99,7 +99,7 @@
data_size, data);
/* Make sure that the EFI_VARIABLE_READ_ONLY flag is not set */
- if (attributes & ~(u32)EFI_VARIABLE_MASK)
+ if (attributes & ~EFI_VARIABLE_MASK)
ret = EFI_INVALID_PARAMETER;
else
ret = efi_set_variable_int(variable_name, vendor, attributes,
diff --git a/lib/efi_loader/efi_variable.c b/lib/efi_loader/efi_variable.c
index 40f7a0f..2951dc7 100644
--- a/lib/efi_loader/efi_variable.c
+++ b/lib/efi_loader/efi_variable.c
@@ -235,8 +235,12 @@
if (data_size && !data)
return EFI_INVALID_PARAMETER;
- /* EFI_VARIABLE_AUTHENTICATED_WRITE_ACCESS is deprecated */
- if (attributes & EFI_VARIABLE_AUTHENTICATED_WRITE_ACCESS)
+ /*
+ * EFI_VARIABLE_AUTHENTICATED_WRITE_ACCESS is deprecated.
+ * We don't support EFI_VARIABLE_ENHANCED_AUTHENTICATED_ACCESS.
+ */
+ if (attributes & (EFI_VARIABLE_AUTHENTICATED_WRITE_ACCESS | \
+ EFI_VARIABLE_ENHANCED_AUTHENTICATED_ACCESS))
return EFI_UNSUPPORTED;
/* Make sure if runtime bit is set, boot service bit is set also */
@@ -259,7 +263,7 @@
/* check if a variable exists */
var = efi_var_mem_find(vendor, variable_name, NULL);
append = !!(attributes & EFI_VARIABLE_APPEND_WRITE);
- attributes &= ~(u32)EFI_VARIABLE_APPEND_WRITE;
+ attributes &= ~EFI_VARIABLE_APPEND_WRITE;
delete = !append && (!data_size || !attributes);
/* check attributes */
@@ -276,17 +280,27 @@
/* attributes won't be changed */
if (!delete &&
((ro_check && var->attr != attributes) ||
- (!ro_check && ((var->attr & ~(u32)EFI_VARIABLE_READ_ONLY)
- != (attributes & ~(u32)EFI_VARIABLE_READ_ONLY))))) {
+ (!ro_check && ((var->attr & ~EFI_VARIABLE_READ_ONLY)
+ != (attributes & ~EFI_VARIABLE_READ_ONLY))))) {
return EFI_INVALID_PARAMETER;
}
time = var->time;
} else {
- if (delete || append)
- /*
- * Trying to delete or to update a non-existent
- * variable.
- */
+ /*
+ * UEFI specification does not clearly describe the expected
+ * behavior of append write with data size 0, we follow
+ * the EDK II reference implementation.
+ */
+ if (append && !data_size)
+ return EFI_SUCCESS;
+
+ /*
+ * EFI_VARIABLE_APPEND_WRITE to non-existent variable is accepted
+ * and new variable is created in EDK II reference implementation.
+ * We follow it and only check the deletion here.
+ */
+ if (delete)
+ /* Trying to delete a non-existent variable. */
return EFI_NOT_FOUND;
}
@@ -329,7 +343,11 @@
/* EFI_NOT_FOUND has been handled before */
attributes = var->attr;
ret = EFI_SUCCESS;
- } else if (append) {
+ } else if (append && var) {
+ /*
+ * data is appended if EFI_VARIABLE_APPEND_WRITE is set and
+ * variable exists.
+ */
u16 *old_data = var->name;
for (; *old_data; ++old_data)
@@ -342,11 +360,12 @@
ret = efi_var_mem_ins(variable_name, vendor, attributes,
data_size, data, 0, NULL, time);
}
- efi_var_mem_del(var);
if (ret != EFI_SUCCESS)
return ret;
+ efi_var_mem_del(var);
+
if (var_type == EFI_AUTH_VAR_PK)
ret = efi_init_secure_state();
else
@@ -384,7 +403,7 @@
EFI_VARIABLE_RUNTIME_ACCESS)
return EFI_INVALID_PARAMETER;
- if (attributes & ~(u32)EFI_VARIABLE_MASK)
+ if (attributes & ~EFI_VARIABLE_MASK)
return EFI_INVALID_PARAMETER;
*maximum_variable_storage_size = EFI_VAR_BUF_SIZE -
diff --git a/lib/efi_selftest/efi_selftest_textoutput.c b/lib/efi_selftest/efi_selftest_textoutput.c
index cc44b38..a3023c8 100644
--- a/lib/efi_selftest/efi_selftest_textoutput.c
+++ b/lib/efi_selftest/efi_selftest_textoutput.c
@@ -31,6 +31,42 @@
0xD804, 0xDC22,
0};
+ const u16 text[] =
+ u"This should render international characters as described\n"
+ u"U+00D6 \u00D6 - Latin capital letter O with diaresis\n"
+ u"U+00DF \u00DF - Latin small letter sharp s\n"
+ u"U+00E5 \u00E5 - Latin small letter a with ring above\n"
+ u"U+00E9 \u00E9 - Latin small letter e with acute\n"
+ u"U+00F1 \u00F1 - Latin small letter n with tilde\n"
+ u"U+00F6 \u00F6 - Latin small letter o with diaresis\n"
+ u"The following characters will render as '?' with bitmap fonts\n"
+ u"U+00F8 \u00F8 - Latin small letter o with stroke\n"
+ u"U+03AC \u03AC - Greek small letter alpha with tonus\n"
+ u"U+03BB \u03BB - Greek small letter lambda\n"
+ u"U+03C2 \u03C2 - Greek small letter final sigma\n"
+ u"U+1F19 \u1F19 - Greek capital letter epsilon with dasia\n";
+
+ const u16 boxes[] =
+ u"This should render as four boxes with text\n"
+ u"\u250c\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500"
+ u"\u2500\u2500\u2500\u252c\u2500\u2500\u2500\u2500\u2500\u2500\u2500"
+ u"\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2510\n\u2502"
+ u" left top \u2502 right top \u2502\n\u251c\u2500"
+ u"\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500"
+ u"\u2500\u253c\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500"
+ u"\u2500\u2500\u2500\u2500\u2500\u2500\u2524\n\u2502 "
+ u"left bottom \u2502 right bottom \u2502\n\u2514\u2500\u2500\u2500"
+ u"\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2534"
+ u"\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500"
+ u"\u2500\u2500\u2500\u2500\u2518\n";
+
+ const u16 shapes[] =
+ u"Geometric shapes as described\n"
+ u"U+25B2 \u25B2 - Black up-pointing triangle\n"
+ u"U+25BA \u25BA - Black right-pointing pointer\n"
+ u"U+25BC \u25BC - Black down-pointing triangle\n"
+ u"U+25C4 \u25C4 - Black left-pointing pointer\n";
+
/* SetAttribute */
efi_st_printf("\nColor palette\n");
for (foreground = 0; foreground < 0x10; ++foreground) {
@@ -119,6 +155,24 @@
return EFI_ST_FAILURE;
}
efi_st_printf("\n");
+ ret = con_out->output_string(con_out, text);
+ if (ret != EFI_ST_SUCCESS) {
+ efi_st_error("OutputString failed for international chars\n");
+ return EFI_ST_FAILURE;
+ }
+ efi_st_printf("\n");
+ ret = con_out->output_string(con_out, boxes);
+ if (ret != EFI_ST_SUCCESS) {
+ efi_st_error("OutputString failed for box drawing chars\n");
+ return EFI_ST_FAILURE;
+ }
+ efi_st_printf("\n");
+ ret = con_out->output_string(con_out, shapes);
+ if (ret != EFI_ST_SUCCESS) {
+ efi_st_error("OutputString failed for geometric shapes\n");
+ return EFI_ST_FAILURE;
+ }
+ efi_st_printf("\n");
return EFI_ST_SUCCESS;
}
diff --git a/lib/efi_selftest/efi_selftest_unicode_collation.c b/lib/efi_selftest/efi_selftest_unicode_collation.c
index 32c99ca..ad7dfa9 100644
--- a/lib/efi_selftest/efi_selftest_unicode_collation.c
+++ b/lib/efi_selftest/efi_selftest_unicode_collation.c
@@ -220,6 +220,18 @@
return EFI_ST_FAILURE;
}
+ /*
+ * Test unicode code points which map to CP 437 0x01 - 0x1f are
+ * converted to '_'.
+ */
+ boottime->set_mem(fat, 16, 0);
+ ret = unicode_collation_protocol->str_to_fat(unicode_collation_protocol,
+ u"\u263a\u2666\u2022\u25d8\u2642\u2194\u00b6\u203c", 8, fat);
+ if (!ret || efi_st_strcmp_16_8(u"________", fat)) {
+ efi_st_error("str_to_fat returned %u, \"%s\"\n", ret, fat);
+ return EFI_ST_FAILURE;
+ }
+
return EFI_ST_SUCCESS;
}
diff --git a/lib/efi_selftest/efi_selftest_variables.c b/lib/efi_selftest/efi_selftest_variables.c
index c7a3fdb..39ad03a0 100644
--- a/lib/efi_selftest/efi_selftest_variables.c
+++ b/lib/efi_selftest/efi_selftest_variables.c
@@ -131,13 +131,57 @@
(unsigned int)len);
if (memcmp(data, v, len))
efi_st_todo("GetVariable returned wrong value\n");
- /* Append variable 2 */
+
+ /* Append variable 2, write to non-existent variable with datasize=0 */
ret = runtime->set_variable(u"efi_none", &guid_vendor1,
EFI_VARIABLE_BOOTSERVICE_ACCESS |
EFI_VARIABLE_APPEND_WRITE,
+ 0, v);
+ if (ret != EFI_SUCCESS) {
+ efi_st_error(
+ "SetVariable(APPEND_WRITE) with size 0 to non-existent variable returns wrong code\n");
+ return EFI_ST_FAILURE;
+ }
+ len = EFI_ST_MAX_DATA_SIZE;
+ ret = runtime->get_variable(u"efi_none", &guid_vendor1,
+ &attr, &len, data);
+ if (ret != EFI_NOT_FOUND) {
+ efi_st_error("Variable must not be created\n");
+ return EFI_ST_FAILURE;
+ }
+ /* Append variable 2, write to non-existent variable with valid data size*/
+ ret = runtime->set_variable(u"efi_none", &guid_vendor1,
+ EFI_VARIABLE_BOOTSERVICE_ACCESS |
+ EFI_VARIABLE_APPEND_WRITE,
15, v);
+ if (ret != EFI_SUCCESS) {
+ efi_st_error("SetVariable(APPEND_WRITE) with valid size and data to non-existent variable must be succcessful\n");
+ return EFI_ST_FAILURE;
+ }
+ len = EFI_ST_MAX_DATA_SIZE;
+ ret = runtime->get_variable(u"efi_none", &guid_vendor1,
+ &attr, &len, data);
+ if (ret != EFI_SUCCESS) {
+ efi_st_error("GetVariable failed\n");
+ return EFI_ST_FAILURE;
+ }
+ if (len != 15)
+ efi_st_todo("GetVariable returned wrong length %u\n",
+ (unsigned int)len);
+ if (memcmp(data, v, len))
+ efi_st_todo("GetVariable returned wrong value\n");
+ /* Delete variable efi_none */
+ ret = runtime->set_variable(u"efi_none", &guid_vendor1,
+ 0, 0, NULL);
+ if (ret != EFI_SUCCESS) {
+ efi_st_error("SetVariable failed\n");
+ return EFI_ST_FAILURE;
+ }
+ len = EFI_ST_MAX_DATA_SIZE;
+ ret = runtime->get_variable(u"efi_none", &guid_vendor1,
+ &attr, &len, data);
if (ret != EFI_NOT_FOUND) {
- efi_st_error("SetVariable(APPEND_WRITE) with size 0 to non-existent variable returns wrong code\n");
+ efi_st_error("Variable was not deleted\n");
return EFI_ST_FAILURE;
}
/* Enumerate variables */
diff --git a/lib/initcall.c b/lib/initcall.c
index ce317af..c8e2b0f 100644
--- a/lib/initcall.c
+++ b/lib/initcall.c
@@ -55,7 +55,7 @@
init_fnc_t func;
int ret = 0;
- for (ptr = init_sequence; func = *ptr, !ret && func; ptr++) {
+ for (ptr = init_sequence; func = *ptr, func; ptr++) {
type = initcall_is_event(func);
if (type) {
@@ -71,6 +71,8 @@
}
ret = type ? event_notify_null(type) : func();
+ if (ret)
+ break;
}
if (ret) {
diff --git a/lib/rsa/rsa-verify.c b/lib/rsa/rsa-verify.c
index 1007b69..d3b4f71 100644
--- a/lib/rsa/rsa-verify.c
+++ b/lib/rsa/rsa-verify.c
@@ -342,7 +342,7 @@
return -EINVAL;
}
- debug("Checksum algorithm: %s", checksum->name);
+ debug("Checksum algorithm: %s\n", checksum->name);
/* Sanity check for stack size */
if (sig_len > RSA_MAX_SIG_BITS / 8) {
@@ -444,13 +444,13 @@
const char *algo;
if (node < 0) {
- debug("%s: Skipping invalid node", __func__);
+ debug("%s: Skipping invalid node\n", __func__);
return -EBADF;
}
algo = fdt_getprop(blob, node, "algo", NULL);
if (strcmp(info->name, algo)) {
- debug("%s: Wrong algo: have %s, expected %s", __func__,
+ debug("%s: Wrong algo: have %s, expected %s\n", __func__,
info->name, algo);
return -EFAULT;
}
@@ -470,7 +470,7 @@
prop.rr = fdt_getprop(blob, node, "rsa,r-squared", NULL);
if (!prop.num_bits || !prop.modulus || !prop.rr) {
- debug("%s: Missing RSA key info", __func__);
+ debug("%s: Missing RSA key info\n", __func__);
return -EFAULT;
}
diff --git a/lib/smbios.c b/lib/smbios.c
index c83af73..b190b01 100644
--- a/lib/smbios.c
+++ b/lib/smbios.c
@@ -394,6 +394,7 @@
} else {
t->serial_number = smbios_add_prop(ctx, "serial", NULL);
}
+ t->wakeup_type = SMBIOS_WAKEUP_TYPE_UNKNOWN;
t->sku_number = smbios_add_prop(ctx, "sku", NULL);
t->family = smbios_add_prop(ctx, "family", NULL);
diff --git a/net/mdio-uclass.c b/net/mdio-uclass.c
index 6fc7034..0ebfb2f 100644
--- a/net/mdio-uclass.c
+++ b/net/mdio-uclass.c
@@ -6,6 +6,8 @@
#include <common.h>
#include <dm.h>
+#include <dm/lists.h>
+#include <eth_phy.h>
#include <log.h>
#include <malloc.h>
#include <miiphy.h>
@@ -121,6 +123,42 @@
return dm_mdio_reset(mii_bus->priv);
}
+static int mdio_bind_phy_nodes(struct udevice *mdio_dev)
+{
+ ofnode mdio_node, phy_node;
+ struct udevice *phy_dev;
+ const char *node_name;
+ int ret;
+
+ mdio_node = dev_ofnode(mdio_dev);
+ if (!ofnode_valid(mdio_node)) {
+ dev_dbg(mdio_dev, "invalid ofnode for mdio_dev\n");
+ return -ENXIO;
+ }
+
+ ofnode_for_each_subnode(phy_node, mdio_node) {
+ node_name = ofnode_get_name(phy_node);
+ dev_dbg(mdio_dev, "* Found child node: '%s'\n", node_name);
+ ret = device_bind_driver_to_node(mdio_dev,
+ "eth_phy_generic_drv",
+ node_name, phy_node, &phy_dev);
+ if (ret) {
+ dev_dbg(mdio_dev, " - Eth phy binding error: %d\n", ret);
+ continue;
+ }
+
+ dev_dbg(mdio_dev, " - bound phy device: '%s'\n", node_name);
+ ret = device_probe(phy_dev);
+ if (ret) {
+ dev_dbg(mdio_dev, "Device '%s' probe failed\n", phy_dev->name);
+ device_unbind(phy_dev);
+ continue;
+ }
+ }
+
+ return 0;
+}
+
static int dm_mdio_post_probe(struct udevice *dev)
{
struct mdio_perdev_priv *pdata = dev_get_uclass_priv(dev);
@@ -154,6 +192,9 @@
}
}
+ if (CONFIG_IS_ENABLED(DM_ETH_PHY))
+ mdio_bind_phy_nodes(dev);
+
return mdio_register(pdata->mii_bus);
}
diff --git a/net/nfs.c b/net/nfs.c
index 7a8887e..c182824 100644
--- a/net/nfs.c
+++ b/net/nfs.c
@@ -57,7 +57,8 @@
static int nfs_len;
static const ulong nfs_timeout = CONFIG_NFS_TIMEOUT;
-static char dirfh[NFS_FHSIZE]; /* NFSv2 / NFSv3 file handle of directory */
+static char dirfh[NFS3_FHSIZE]; /* NFSv2 / NFSv3 file handle of directory */
+static unsigned int dirfh3_length; /* (variable) length of dirfh when NFSv3 */
static char filefh[NFS3_FHSIZE]; /* NFSv2 / NFSv3 file handle */
static unsigned int filefh3_length; /* (variable) length of filefh when NFSv3 */
@@ -377,9 +378,9 @@
rpc_req(PROG_NFS, NFS_LOOKUP, data, len);
} else { /* NFS_V3 */
- *p++ = htonl(NFS_FHSIZE); /* Dir handle length */
- memcpy(p, dirfh, NFS_FHSIZE);
- p += (NFS_FHSIZE / 4);
+ *p++ = htonl(dirfh3_length); /* Dir handle length */
+ memcpy(p, dirfh, dirfh3_length);
+ p += (dirfh3_length / 4);
*p++ = htonl(fnamelen);
if (fnamelen & 3)
*(p + fnamelen / 4) = 0;
@@ -565,7 +566,14 @@
fs_mounted = 1;
/* NFSv2 and NFSv3 use same structure */
- memcpy(dirfh, rpc_pkt.u.reply.data + 1, NFS_FHSIZE);
+ if (choosen_nfs_version != NFS_V3) {
+ memcpy(dirfh, rpc_pkt.u.reply.data + 1, NFS_FHSIZE);
+ } else {
+ dirfh3_length = ntohl(rpc_pkt.u.reply.data[1]);
+ if (dirfh3_length > NFS3_FHSIZE)
+ dirfh3_length = NFS3_FHSIZE;
+ memcpy(dirfh, rpc_pkt.u.reply.data + 2, dirfh3_length);
+ }
return 0;
}
diff --git a/scripts/Makefile.spl b/scripts/Makefile.spl
index d074ba2..1868f1b 100644
--- a/scripts/Makefile.spl
+++ b/scripts/Makefile.spl
@@ -381,6 +381,11 @@
$(objtree)/tools/mkexynosspl) $(VAR_SIZE_PARAM) $< $@
endif
+$(obj)/u-boot-spl.ldr: $(obj)/u-boot-spl
+ $(CREATE_LDR_ENV)
+ $(LDR) -T $(CONFIG_LDR_CPU) -c $@ $< $(LDR_FLAGS)
+ $(BOARD_SIZE_CHECK)
+
quiet_cmd_objcopy = OBJCOPY $@
cmd_objcopy = $(OBJCOPY) $(OBJCOPYFLAGS) $(OBJCOPYFLAGS_$(@F)) $< $@
@@ -575,7 +580,7 @@
SPL_OF_LIST_TARGETS = $(patsubst %,dts/%.dtb,$(subst ",,$(CONFIG_SPL_OF_LIST)))
SHRUNK_ARCH_DTB = $(addprefix $(obj)/,$(SPL_OF_LIST_TARGETS))
-$(dir $(SHRUNK_ARCH_DTB)):
+$(sort $(dir $(SHRUNK_ARCH_DTB))):
$(shell [ -d $@ ] || mkdir -p $@)
.SECONDEXPANSION:
diff --git a/scripts/kconfig/Makefile b/scripts/kconfig/Makefile
index 5ce5845..079add4 100644
--- a/scripts/kconfig/Makefile
+++ b/scripts/kconfig/Makefile
@@ -93,7 +93,7 @@
endif
%_defconfig: $(obj)/conf
- $(Q)$(CPP) -nostdinc -I $(srctree) -undef -x assembler-with-cpp $(srctree)/arch/$(SRCARCH)/configs/$@ -o generated_defconfig
+ $(Q)$(CPP) -nostdinc -P -I $(srctree) -undef -x assembler-with-cpp $(srctree)/arch/$(SRCARCH)/configs/$@ -o generated_defconfig
$(Q)$< $(silent) --defconfig=generated_defconfig $(Kconfig)
# Added for U-Boot (backward compatibility)
diff --git a/test/boot/bootflow.c b/test/boot/bootflow.c
index 4845b71..674d4c0 100644
--- a/test/boot/bootflow.c
+++ b/test/boot/bootflow.c
@@ -13,6 +13,7 @@
#include <bootstd.h>
#include <cli.h>
#include <dm.h>
+#include <efi_default_filename.h>
#include <expo.h>
#ifdef CONFIG_SANDBOX
#include <asm/test.h>
@@ -179,7 +180,8 @@
ut_assert_nextline(" 3 efi media mmc 0 mmc1.bootdev.whole ");
ut_assert_nextline(" ** No partition found, err=-2: No such file or directory");
ut_assert_nextline(" 4 extlinux ready mmc 1 mmc1.bootdev.part_1 /extlinux/extlinux.conf");
- ut_assert_nextline(" 5 efi fs mmc 1 mmc1.bootdev.part_1 efi/boot/bootsbox.efi");
+ ut_assert_nextline(" 5 efi fs mmc 1 mmc1.bootdev.part_1 /EFI/BOOT/"
+ BOOTEFI_NAME);
ut_assert_skip_to_line("Scanning bootdev 'mmc0.bootdev':");
ut_assert_skip_to_line(
@@ -377,7 +379,7 @@
if (!IS_ENABLED(CONFIG_EFI_BOOTMGR))
return -EAGAIN;
ut_assertok(uclass_first_device_err(UCLASS_BOOTSTD, &bootstd));
- ut_assertok(device_bind(bootstd, DM_DRIVER_GET(bootmeth_efi_mgr),
+ ut_assertok(device_bind(bootstd, DM_DRIVER_GET(bootmeth_3efi_mgr),
"efi_mgr", 0, ofnode_null(), &dev));
ut_assertok(device_probe(dev));
sandbox_set_fake_efi_mgr_dev(dev, true);
diff --git a/test/dm/acpi.c b/test/dm/acpi.c
index c53ebcd..f14b396 100644
--- a/test/dm/acpi.c
+++ b/test/dm/acpi.c
@@ -237,7 +237,7 @@
hdr.length = 0x11;
hdr.revision = 0x22;
hdr.checksum = 0x33;
- hdr.aslc_revision = 0x44;
+ hdr.creator_revision = 0x44;
acpi_fill_header(&hdr, "ABCD");
ut_asserteq_mem("ABCD", hdr.signature, sizeof(hdr.signature));
@@ -248,8 +248,8 @@
ut_asserteq_mem(OEM_TABLE_ID, hdr.oem_table_id,
sizeof(hdr.oem_table_id));
ut_asserteq(OEM_REVISION, hdr.oem_revision);
- ut_asserteq_mem(ASLC_ID, hdr.aslc_id, sizeof(hdr.aslc_id));
- ut_asserteq(0x44, hdr.aslc_revision);
+ ut_asserteq_mem(ASLC_ID, hdr.creator_id, sizeof(hdr.creator_id));
+ ut_asserteq(0x44, hdr.creator_revision);
return 0;
}
diff --git a/test/dm/button.c b/test/dm/button.c
index 3318668..830d96f 100644
--- a/test/dm/button.c
+++ b/test/dm/button.c
@@ -131,3 +131,99 @@
return 0;
}
DM_TEST(dm_test_button_keys_adc, UT_TESTF_SCAN_PDATA | UT_TESTF_SCAN_FDT);
+
+/* Test of the button uclass using the button_gpio driver */
+static int dm_test_button_cmd(struct unit_test_state *uts)
+{
+ struct udevice *btn1_dev, *btn2_dev, *gpio;
+ const char *envstr;
+
+#define BTN1_GPIO 3
+#define BTN2_GPIO 4
+#define BTN1_PASS_VAR "test_button_cmds_0"
+#define BTN2_PASS_VAR "test_button_cmds_1"
+
+ /*
+ * Buttons 1 and 2 are connected to gpio_a gpios 3 and 4 respectively.
+ * set the GPIOs to known values and then check that the appropriate
+ * commands are run when invoking process_button_cmds().
+ */
+ ut_assertok(uclass_get_device(UCLASS_BUTTON, 1, &btn1_dev));
+ ut_assertok(uclass_get_device(UCLASS_BUTTON, 2, &btn2_dev));
+ ut_assertok(uclass_get_device(UCLASS_GPIO, 1, &gpio));
+
+ /*
+ * Map a command to button 1 and check that it process_button_cmds()
+ * runs it if called with button 1 pressed.
+ */
+ ut_assertok(env_set("button_cmd_0_name", "button1"));
+ ut_assertok(env_set("button_cmd_0", "env set " BTN1_PASS_VAR " PASS"));
+ ut_assertok(sandbox_gpio_set_value(gpio, BTN1_GPIO, 1));
+ /* Sanity check that the button is actually pressed */
+ ut_asserteq(BUTTON_ON, button_get_state(btn1_dev));
+ process_button_cmds();
+ ut_assertnonnull((envstr = env_get(BTN1_PASS_VAR)));
+ ut_asserteq_str(envstr, "PASS");
+
+ /* Clear result */
+ ut_assertok(env_set(BTN1_PASS_VAR, NULL));
+
+ /*
+ * Map a command for button 2, press it, check that only the command
+ * for button 1 runs because it comes first and is also pressed.
+ */
+ ut_assertok(env_set("button_cmd_1_name", "button2"));
+ ut_assertok(env_set("button_cmd_1", "env set " BTN2_PASS_VAR " PASS"));
+ ut_assertok(sandbox_gpio_set_value(gpio, BTN2_GPIO, 1));
+ ut_asserteq(BUTTON_ON, button_get_state(btn2_dev));
+ process_button_cmds();
+ /* Check that button 1 triggered again */
+ ut_assertnonnull((envstr = env_get(BTN1_PASS_VAR)));
+ ut_asserteq_str(envstr, "PASS");
+ /* And button 2 didn't */
+ ut_assertnull(env_get(BTN2_PASS_VAR));
+
+ /* Clear result */
+ ut_assertok(env_set(BTN1_PASS_VAR, NULL));
+
+ /*
+ * Release button 1 and check that the command for button 2 is run
+ */
+ ut_assertok(sandbox_gpio_set_value(gpio, BTN1_GPIO, 0));
+ process_button_cmds();
+ ut_assertnull(env_get(BTN1_PASS_VAR));
+ /* Check that the command for button 2 ran */
+ ut_assertnonnull((envstr = env_get(BTN2_PASS_VAR)));
+ ut_asserteq_str(envstr, "PASS");
+
+ /* Clear result */
+ ut_assertok(env_set(BTN2_PASS_VAR, NULL));
+
+ /*
+ * Unset "button_cmd_0_name" and check that no commands run even
+ * with both buttons pressed.
+ */
+ ut_assertok(env_set("button_cmd_0_name", NULL));
+ /* Press button 1 (button 2 is already pressed )*/
+ ut_assertok(sandbox_gpio_set_value(gpio, BTN1_GPIO, 1));
+ ut_asserteq(BUTTON_ON, button_get_state(btn1_dev));
+ process_button_cmds();
+ ut_assertnull(env_get(BTN1_PASS_VAR));
+ ut_assertnull(env_get(BTN2_PASS_VAR));
+
+ /*
+ * Check that no command is run if the button name is wrong.
+ */
+ ut_assertok(env_set("button_cmd_0_name", "invalid_button"));
+ process_button_cmds();
+ ut_assertnull(env_get(BTN1_PASS_VAR));
+ ut_assertnull(env_get(BTN2_PASS_VAR));
+
+#undef BTN1_PASS_VAR
+#undef BTN2_PASS_VAR
+#undef BTN1_GPIO
+#undef BTN2_GPIO
+
+ return 0;
+}
+DM_TEST(dm_test_button_cmd, UT_TESTF_SCAN_PDATA | UT_TESTF_SCAN_FDT);
diff --git a/test/py/tests/test_efi_capsule/capsule_gen_binman.dts b/test/py/tests/test_efi_capsule/capsule_gen_binman.dts
index e8a1858..1a62c26 100644
--- a/test/py/tests/test_efi_capsule/capsule_gen_binman.dts
+++ b/test/py/tests/test_efi_capsule/capsule_gen_binman.dts
@@ -55,42 +55,6 @@
};
capsule1 {
- filename = "Test01";
- efi-capsule {
- image-index = <0x1>;
- image-guid = SANDBOX_UBOOT_IMAGE_GUID;
-
- text {
- text = "u-boot:New";
- };
- };
- };
-
- capsule2 {
- filename = "Test02";
- efi-capsule {
- image-index = <0x2>;
- image-guid = SANDBOX_UBOOT_ENV_IMAGE_GUID;
-
- text {
- text = "u-boot-env:New";
- };
- };
- };
-
- capsule3 {
- filename = "Test03";
- efi-capsule {
- image-index = <0x1>;
- image-guid = SANDBOX_INCORRECT_GUID;
-
- text {
- text = "u-boot:New";
- };
- };
- };
-
- capsule4 {
filename = "Test04";
efi-capsule {
image-index = <0x1>;
@@ -102,7 +66,7 @@
};
};
- capsule5 {
+ capsule2 {
filename = "Test05";
efi-capsule {
image-index = <0x1>;
@@ -114,46 +78,7 @@
};
};
- capsule6 {
- filename = "Test101";
- efi-capsule {
- image-index = <0x1>;
- fw-version = <0x5>;
- image-guid = SANDBOX_UBOOT_IMAGE_GUID;
-
- text {
- text = "u-boot:New";
- };
- };
- };
-
- capsule7 {
- filename = "Test102";
- efi-capsule {
- image-index = <0x2>;
- fw-version = <0xa>;
- image-guid = SANDBOX_UBOOT_ENV_IMAGE_GUID;
-
- text {
- text = "u-boot-env:New";
- };
- };
- };
-
- capsule8 {
- filename = "Test103";
- efi-capsule {
- image-index = <0x1>;
- fw-version = <0x2>;
- image-guid = SANDBOX_UBOOT_IMAGE_GUID;
-
- text {
- text = "u-boot:New";
- };
- };
- };
-
- capsule9 {
+ capsule3 {
filename = "Test104";
efi-capsule {
image-index = <0x1>;
@@ -166,7 +91,7 @@
};
};
- capsule10 {
+ capsule4 {
filename = "Test105";
efi-capsule {
image-index = <0x1>;
@@ -179,37 +104,7 @@
};
};
- capsule11 {
- filename = "Test11";
- efi-capsule {
- image-index = <0x1>;
- image-guid = SANDBOX_UBOOT_IMAGE_GUID;
- private-key = CAPSULE_PRIV_KEY;
- public-key-cert = CAPSULE_PUB_KEY;
- monotonic-count = <0x1>;
-
- text {
- text = "u-boot:New";
- };
- };
- };
-
- capsule12 {
- filename = "Test12";
- efi-capsule {
- image-index = <0x1>;
- image-guid = SANDBOX_UBOOT_IMAGE_GUID;
- private-key = CAPSULE_INVAL_KEY;
- public-key-cert = CAPSULE_INVAL_PUB_KEY;
- monotonic-count = <0x1>;
-
- text {
- text = "u-boot:New";
- };
- };
- };
-
- capsule13 {
+ capsule5 {
filename = "Test13";
efi-capsule {
image-index = <0x1>;
@@ -224,7 +119,7 @@
};
};
- capsule14 {
+ capsule6 {
filename = "Test14";
efi-capsule {
image-index = <0x1>;
@@ -239,55 +134,7 @@
};
};
- capsule15 {
- filename = "Test111";
- efi-capsule {
- image-index = <0x1>;
- fw-version = <0x5>;
- image-guid = SANDBOX_UBOOT_IMAGE_GUID;
- private-key = CAPSULE_PRIV_KEY;
- public-key-cert = CAPSULE_PUB_KEY;
- monotonic-count = <0x1>;
-
- text {
- text = "u-boot:New";
- };
- };
- };
-
- capsule16 {
- filename = "Test112";
- efi-capsule {
- image-index = <0x2>;
- fw-version = <0xa>;
- image-guid = SANDBOX_UBOOT_ENV_IMAGE_GUID;
- private-key = CAPSULE_PRIV_KEY;
- public-key-cert = CAPSULE_PUB_KEY;
- monotonic-count = <0x1>;
-
- text {
- text = "u-boot-env:New";
- };
- };
- };
-
- capsule17 {
- filename = "Test113";
- efi-capsule {
- image-index = <0x1>;
- fw-version = <0x2>;
- image-guid = SANDBOX_UBOOT_IMAGE_GUID;
- private-key = CAPSULE_PRIV_KEY;
- public-key-cert = CAPSULE_PUB_KEY;
- monotonic-count = <0x1>;
-
- text {
- text = "u-boot:New";
- };
- };
- };
-
- capsule18 {
+ capsule7 {
filename = "Test114";
efi-capsule {
image-index = <0x1>;
@@ -303,7 +150,7 @@
};
};
- capsule19 {
+ capsule8 {
filename = "Test115";
efi-capsule {
image-index = <0x1>;
diff --git a/test/py/tests/test_efi_capsule/conftest.py b/test/py/tests/test_efi_capsule/conftest.py
index dd41da9..80b1297 100644
--- a/test/py/tests/test_efi_capsule/conftest.py
+++ b/test/py/tests/test_efi_capsule/conftest.py
@@ -85,6 +85,7 @@
check_call('cd %s; '
'./tools/binman/binman --toolpath %s/tools build -u -d %s/capsule_binman.dtb -O %s -m --allow-missing -I %s -I ./board/sandbox -I ./arch/sandbox/dts'
% (u_boot_config.source_dir, u_boot_config.build_dir, data_dir, data_dir, data_dir), shell=True)
+ check_call('cp %s/Test* %s' % (u_boot_config.build_dir, data_dir), shell=True)
os.environ['PYTHONPATH'] = pythonpath
# Create a disk image with EFI system partition
diff --git a/test/py/tests/test_reset.py b/test/py/tests/test_reset.py
new file mode 100644
index 0000000..00fc31d
--- /dev/null
+++ b/test/py/tests/test_reset.py
@@ -0,0 +1,63 @@
+# SPDX-License-Identifier: GPL-2.0
+# (C) Copyright 2023, Advanced Micro Devices, Inc.
+
+"""
+Note: This test doesn't rely on boardenv_* configuration value but they can
+change test behavior.
+
+For example:
+
+# Setup env__reset_test_skip to True if reset test is not possible or desired
+# and should be skipped.
+env__reset_test_skip = True
+
+# Setup env__reset_test to set the bootmode if 'modeboot' u-boot environment
+# variable is not set. Test will be skipped if bootmode is not set in both
+# places i.e, boardenv and modeboot u-boot environment variable
+env__reset_test = {
+ 'bootmode': 'qspiboot',
+}
+
+# This test will be also skipped if the bootmode is detected to JTAG.
+"""
+
+import pytest
+import test_000_version
+
+def setup_reset_env(u_boot_console):
+ if u_boot_console.config.env.get('env__reset_test_skip', False):
+ pytest.skip('reset test is not enabled')
+
+ output = u_boot_console.run_command('echo $modeboot')
+ if output:
+ bootmode = output
+ else:
+ f = u_boot_console.config.env.get('env__reset_test', None)
+ if not f:
+ pytest.skip('bootmode cannot be determined')
+ bootmode = f.get('bootmode', 'jtagboot')
+
+ if 'jtag' in bootmode:
+ pytest.skip('skipping reset test due to jtag bootmode')
+
+@pytest.mark.buildconfigspec('hush_parser')
+def test_reset(u_boot_console):
+ """Test the reset command in non-JTAG bootmode.
+ It does COLD reset, which resets CPU, DDR and peripherals
+ """
+ setup_reset_env(u_boot_console)
+ u_boot_console.run_command('reset', wait_for_reboot=True)
+
+ # Checks the u-boot command prompt's functionality after reset
+ test_000_version.test_version(u_boot_console)
+
+@pytest.mark.buildconfigspec('hush_parser')
+def test_reset_w(u_boot_console):
+ """Test the reset -w command in non-JTAG bootmode.
+ It does WARM reset, which resets CPU but keep DDR/peripherals active.
+ """
+ setup_reset_env(u_boot_console)
+ u_boot_console.run_command('reset -w', wait_for_reboot=True)
+
+ # Checks the u-boot command prompt's functionality after reset
+ test_000_version.test_version(u_boot_console)
diff --git a/test/py/tests/test_saveenv.py b/test/py/tests/test_saveenv.py
new file mode 100644
index 0000000..7faa3bd
--- /dev/null
+++ b/test/py/tests/test_saveenv.py
@@ -0,0 +1,137 @@
+# SPDX-License-Identifier: GPL-2.0
+# (C) Copyright 2023, Advanced Micro Devices, Inc.
+
+"""
+Note: This test doesn't rely on boardenv_* configuration value but they can
+change test behavior.
+
+For example:
+
+# Setup env__saveenv_test_skip to True if saveenv test is not possible or
+# desired and should be skipped.
+env__saveenv_test_skip = True
+
+# Setup env__saveenv_test to set the bootmode if 'modeboot' u-boot environment
+# variable is not set. Test will be skipped if bootmode is not set in both
+# places i.e, boardenv and modeboot u-boot environment variable
+env__saveenv_test = {
+ 'bootmode': 'qspiboot',
+}
+
+# This test will be also skipped if the bootmode is detected to JTAG.
+"""
+
+import pytest
+import random
+import ipaddress
+import string
+import uuid
+
+# Setup the env
+def setup_saveenv_env(u_boot_console):
+ if u_boot_console.config.env.get('env__saveenv_test_skip', False):
+ pytest.skip('saveenv test is not enabled')
+
+ output = u_boot_console.run_command('echo $modeboot')
+ if output:
+ bootmode = output
+ else:
+ f = u_boot_console.config.env.get('env__saveenv_test', None)
+ if not f:
+ pytest.skip('bootmode cannot be determined')
+ bootmode = f.get('bootmode', 'jtagboot')
+
+ if 'jtag' in bootmode:
+ pytest.skip('skipping saveenv test due to jtag bootmode')
+
+# Check return code
+def ret_code(u_boot_console):
+ return u_boot_console.run_command('echo $?')
+
+# Verify env variable
+def check_env(u_boot_console, var_name, var_value):
+ if var_value:
+ output = u_boot_console.run_command(f'printenv {var_name}')
+ var_value = str(var_value)
+ if (var_value.startswith("'") and var_value.endswith("'")) or (
+ var_value.startswith('"') and var_value.endswith('"')
+ ):
+ var_value = var_value.split(var_value[-1])[1]
+ assert var_value in output
+ assert ret_code(u_boot_console).endswith('0')
+ else:
+ u_boot_console.p.send(f'printenv {var_name}\n')
+ output = u_boot_console.p.expect(['not defined'])
+ assert output == 0
+ assert ret_code(u_boot_console).endswith('1')
+
+# Set env variable
+def set_env(u_boot_console, var_name, var_value):
+ u_boot_console.run_command(f'setenv {var_name} {var_value}')
+ assert ret_code(u_boot_console).endswith('0')
+ check_env(u_boot_console, var_name, var_value)
+
+@pytest.mark.buildconfigspec('cmd_saveenv')
+@pytest.mark.buildconfigspec('hush_parser')
+def test_saveenv(u_boot_console):
+ """Test the saveenv command in non-JTAG bootmode.
+ It saves the U-Boot environment in persistent storage.
+ """
+ setup_saveenv_env(u_boot_console)
+
+ # Set env for random mac address
+ rand_mac = '%02x:%02x:%02x:%02x:%02x:%02x' % (
+ random.randint(0, 255),
+ random.randint(0, 255),
+ random.randint(0, 255),
+ random.randint(0, 255),
+ random.randint(0, 255),
+ random.randint(0, 255),
+ )
+ set_env(u_boot_console, 'mac_addr', rand_mac)
+
+ # Set env for random IPv4 address
+ rand_ipv4 = ipaddress.IPv4Address._string_from_ip_int(
+ random.randint(0, ipaddress.IPv4Address._ALL_ONES)
+ )
+ set_env(u_boot_console, 'ipv4_addr', rand_ipv4)
+
+ # Set env for random IPv6 address
+ rand_ipv6 = ipaddress.IPv6Address._string_from_ip_int(
+ random.randint(0, ipaddress.IPv6Address._ALL_ONES)
+ )
+ set_env(u_boot_console, 'ipv6_addr', rand_ipv6)
+
+ # Set env for random number
+ rand_num = random.randrange(1, 10**9)
+ set_env(u_boot_console, 'num_var', rand_num)
+
+ # Set env for uuid
+ uuid_str = uuid.uuid4().hex.lower()
+ set_env(u_boot_console, 'uuid_var', uuid_str)
+
+ # Set env for random string including special characters
+ sc = "!#%&()*+,-./:;<=>?@[\\]^_`{|}~"
+ rand_str = ''.join(
+ random.choices(' ' + string.ascii_letters + sc + string.digits, k=300)
+ )
+ set_env(u_boot_console, 'str_var', f'"{rand_str}"')
+
+ # Set env for empty string
+ set_env(u_boot_console, 'empty_var', '')
+
+ # Save the env variables
+ u_boot_console.run_command('saveenv')
+ assert ret_code(u_boot_console).endswith('0')
+
+ # Reboot
+ u_boot_console.run_command('reset', wait_for_reboot=True)
+
+ # Verify the saved env variables
+ check_env(u_boot_console, 'mac_addr', rand_mac)
+ check_env(u_boot_console, 'ipv4_addr', rand_ipv4)
+ check_env(u_boot_console, 'ipv6_addr', rand_ipv6)
+ check_env(u_boot_console, 'num_var', rand_num)
+ check_env(u_boot_console, 'uuid_var', uuid_str)
+ check_env(u_boot_console, 'str_var', rand_str)
+ check_env(u_boot_console, 'empty_var', '')
diff --git a/tools/docker/Dockerfile b/tools/docker/Dockerfile
index 2742554..cda8735 100644
--- a/tools/docker/Dockerfile
+++ b/tools/docker/Dockerfile
@@ -2,7 +2,7 @@
# This Dockerfile is used to build an image containing basic stuff to be used
# to build U-Boot and run our test suites.
-FROM ubuntu:jammy-20240125
+FROM ubuntu:jammy-20240227
MAINTAINER Tom Rini <trini@konsulko.com>
LABEL Description=" This image is for building U-Boot inside a container"
@@ -12,7 +12,7 @@
# Add LLVM repository
RUN apt-get update && apt-get install -y gnupg2 wget xz-utils && rm -rf /var/lib/apt/lists/*
RUN wget -O - https://apt.llvm.org/llvm-snapshot.gpg.key | apt-key add -
-RUN echo deb http://apt.llvm.org/jammy/ llvm-toolchain-jammy-16 main | tee /etc/apt/sources.list.d/llvm.list
+RUN echo deb http://apt.llvm.org/jammy/ llvm-toolchain-jammy-17 main | tee /etc/apt/sources.list.d/llvm.list
# Manually install the kernel.org "Crosstool" based toolchains for gcc-13.2.0
RUN wget -O - https://mirrors.edge.kernel.org/pub/tools/crosstool/files/bin/x86_64/13.2.0/x86_64-gcc-13.2.0-nolibc-aarch64-linux.tar.xz | tar -C /opt -xJ
@@ -40,7 +40,7 @@
bison \
build-essential \
cgpt \
- clang-16 \
+ clang-17 \
coreutils \
cpio \
curl \
@@ -116,6 +116,7 @@
virtualenv \
vboot-kernel-utils \
vboot-utils \
+ xilinx-bootgen \
xxd \
zip \
&& rm -rf /var/lib/apt/lists/*
@@ -184,10 +185,21 @@
git config user.email u-boot@denx.de && \
git format-patch 0c7ffc977195~..0c7ffc977195 && \
git am 0001-hw-net-cadence_gem-Fix-MDIO_OP_xxx-values.patch && \
+ git cherry-pick d3c79c3974 && \
./configure --prefix=/opt/qemu --target-list="aarch64-softmmu,arm-softmmu,i386-softmmu,m68k-softmmu,mips-softmmu,mips64-softmmu,mips64el-softmmu,mipsel-softmmu,ppc-softmmu,riscv32-softmmu,riscv64-softmmu,sh4-softmmu,x86_64-softmmu,xtensa-softmmu" && \
make -j$(nproc) all install && \
rm -rf /tmp/qemu
+# Build fiptool
+RUN git clone https://git.trustedfirmware.org/TF-A/trusted-firmware-a.git /tmp/tf-a && \
+ cd /tmp/tf-a/ && \
+ git checkout v2.10.0 && \
+ cd tools/fiptool && \
+ make && \
+ mkdir -p /usr/local/bin && \
+ cp fiptool /usr/local/bin && \
+ rm -rf /tmp/tf-a
+
# Build genimage (required by some targets to generate disk images)
RUN wget -O - https://github.com/pengutronix/genimage/releases/download/v14/genimage-14.tar.xz | tar -C /tmp -xJ && \
cd /tmp/genimage-14 && \
diff --git a/tools/fit_image.c b/tools/fit_image.c
index beef1fa..0fccfbb 100644
--- a/tools/fit_image.c
+++ b/tools/fit_image.c
@@ -137,7 +137,7 @@
int ret;
int fd;
- fd = open(fname, O_RDWR | O_BINARY);
+ fd = open(fname, O_RDONLY | O_BINARY);
if (fd < 0) {
fprintf(stderr, "%s: Can't open %s: %s\n",
params->cmdname, fname, strerror(errno));
diff --git a/tools/patman/patman.rst b/tools/patman/patman.rst
index e013558..f4588c0 100644
--- a/tools/patman/patman.rst
+++ b/tools/patman/patman.rst
@@ -144,7 +144,7 @@
process_tags: False
verbose: True
smtp_server: /path/to/sendmail
- patchwork_server: https://patchwork.ozlabs.org
+ patchwork_url: https://patchwork.ozlabs.org
If you want to adjust settings (or aliases) that affect just a single
project you can add a section that looks like [project_settings] or
@@ -248,9 +248,9 @@
Series-patchwork-url: url
This allows specifying the Patchwork URL for a branch. This overrides
- both the setting files and the command-line argument. The URL should
- include the protocol and web site, with no trailing slash, for example
- 'https://patchwork.ozlabs.org/project'
+ both the setting files ("patchwork_url") and the command-line argument.
+ The URL should include the protocol and web site, with no trailing slash,
+ for example 'https://patchwork.ozlabs.org/project'
Cover-letter:
Sets the cover letter contents for the series. The first line
diff --git a/tools/proftool.c b/tools/proftool.c
index fca45e4..c2e3809 100644
--- a/tools/proftool.c
+++ b/tools/proftool.c
@@ -290,7 +290,7 @@
"Options:\n"
" -c <cfg>\tSpecify config file\n"
" -f <subtype>\tSpecify output subtype\n"
- " -m <map>\tSpecify Systen.map file\n"
+ " -m <map>\tSpecify System.map file\n"
" -o <fname>\tSpecify output file\n"
" -t <fname>\tSpecify trace data file (from U-Boot 'trace calls')\n"
" -v <0-4>\tSpecify verbosity\n"
@@ -306,7 +306,7 @@
}
/**
- * h_cmp_offset - bsearch() function to compare two functions bny their offset
+ * h_cmp_offset - bsearch() function to compare two functions by their offset
*
* @v1: Pointer to first function (struct func_info)
* @v2: Pointer to second function (struct func_info)
@@ -431,7 +431,7 @@
static struct func_info *find_caller_by_offset(uint offset)
{
int low; /* least function that could be a match */
- int high; /* greated function that could be a match */
+ int high; /* greatest function that could be a match */
struct func_info key;
low = 0;
@@ -1352,7 +1352,7 @@
}
if (!(func->flags & FUNCF_TRACE)) {
- debug("Funcion '%s' is excluded from trace\n",
+ debug("Function '%s' is excluded from trace\n",
func->name);
skip_count++;
continue;
@@ -1781,7 +1781,8 @@
*
* This works by maintaining a string shared across all recursive calls. The
* function name for this node is added to the existing string, to make up the
- * full call-stack description. For example, on entry, @str might contain:
+ * full call-stack description. For example, on entry, @str_buf->data might
+ * contain:
*
* "initf_bootstage;bootstage_mark_name"
* ^ @base
@@ -1795,18 +1796,18 @@
* @fout: Output file
* @out_format: Output format to use
* @node: Node to output (pass the whole tree at first)
- * @str: String to use to build the output line (e.g. 500 charas long)
- * @maxlen: Maximum length of string
+ * @str_buf: String buffer to use to build the output line
* @base: Current base position in the string
* @treep: Returns the resulting flamegraph tree
* Returns 0 if OK, -1 on error
*/
static int output_tree(FILE *fout, enum out_format_t out_format,
- const struct flame_node *node, char *str, int maxlen,
+ const struct flame_node *node, struct abuf *str_buf,
int base)
{
const struct flame_node *child;
int pos;
+ char *str = abuf_data(str_buf);
if (node->count) {
if (out_format == OUT_FMT_FLAMEGRAPH_CALLS) {
@@ -1832,18 +1833,29 @@
if (pos)
str[pos++] = ';';
list_for_each_entry(child, &node->child_head, sibling_node) {
- int len;
+ int len, needed;
len = strlen(child->func->name);
- if (pos + len + 1 >= maxlen) {
- fprintf(stderr, "String too short (%d chars)\n",
- maxlen);
- return -1;
+ needed = pos + len + 1;
+ if (needed > abuf_size(str_buf)) {
+ /*
+ * We need to re-allocate the string buffer; increase
+ * its size by multiples of 500 characters.
+ */
+ needed = 500 * ((needed / 500) + 1);
+ if (!abuf_realloc(str_buf, needed))
+ return -1;
+ str = abuf_data(str_buf);
+ memset(str + pos, 0, abuf_size(str_buf) - pos);
}
strcpy(str + pos, child->func->name);
- if (output_tree(fout, out_format, child, str, maxlen,
- pos + len))
+ if (output_tree(fout, out_format, child, str_buf, pos + len))
return -1;
+ /*
+ * Update our pointer as the string buffer might have been
+ * re-allocated.
+ */
+ str = abuf_data(str_buf);
}
return 0;
@@ -1859,16 +1871,24 @@
static int make_flamegraph(FILE *fout, enum out_format_t out_format)
{
struct flame_node *tree;
- char str[500];
+ struct abuf str_buf;
+ char *str;
+ int ret = 0;
if (make_flame_tree(out_format, &tree))
return -1;
- *str = '\0';
- if (output_tree(fout, out_format, tree, str, sizeof(str), 0))
+ abuf_init(&str_buf);
+ if (!abuf_realloc(&str_buf, 500))
return -1;
- return 0;
+ str = abuf_data(&str_buf);
+ memset(str, 0, abuf_size(&str_buf));
+ if (output_tree(fout, out_format, tree, &str_buf, 0))
+ ret = -1;
+
+ abuf_uninit(&str_buf);
+ return ret;
}
/**