| commit | 3abd16b38411756d69f451f658fe0d55c7991f18 | [log] [tgz] |
|---|---|---|
| author | York Sun <york.sun@nxp.com> | Wed May 18 21:11:19 2016 -0700 |
| committer | York Sun <york.sun@nxp.com> | Fri Jun 03 14:12:06 2016 -0700 |
| tree | 261ba20afcda83bd9e50ea82f9981eac9b151752 | |
| parent | d097bd9832a26f571ff8cf43a0835e31cd8d7d16 [diff] |
drivers/ddr/fsl: Fix timing_cfg_2 register Commit 34e026f9 added one extra bit to wr_lat for timing_cfg_2, but with wrong bit position. It is bit 13 in big-endian, or left shift 18 from LSB. This error hasn't had any impact because we don't have fast enough DDR4 using the extra bit so far. Signed-off-by: York Sun <york.sun@nxp.com>