Merge patch series "This series adds support for file renaming to EFI_FILE_PROTOCOL.SetInfo()."
Gabriel Dalimonte <gabriel.dalimonte@gmail.com> says:
This series adds support for file renaming to EFI_FILE_PROTOCOL.SetInfo().
One of the use cases for renaming in EFI is to facilitate boot loader
boot counting.
No existing filesystems in U-Boot currently include file renaming,
resulting in support for renaming at the filesystem level and a
concrete implementation for the FAT filesystem.
Link: https://lore.kernel.org/r/20250217182648.31294-1-gabriel.dalimonte@gmail.com
diff --git a/.azure-pipelines.yml b/.azure-pipelines.yml
index 1f2766e..d5cfa59 100644
--- a/.azure-pipelines.yml
+++ b/.azure-pipelines.yml
@@ -173,7 +173,7 @@
-r tools/buildman/requirements.txt \
-r tools/patman/requirements.txt \
-r tools/u_boot_pylib/requirements.txt \
- asteval pylint==2.12.2 pyopenssl
+ asteval pylint==3.3.4 pyopenssl
export PATH=${PATH}:~/.local/bin
echo "[MASTER]" >> .pylintrc
echo "load-plugins=pylint.extensions.docparams" >> .pylintrc
diff --git a/.gitlab-ci.yml b/.gitlab-ci.yml
index e339c25..2dbe632 100644
--- a/.gitlab-ci.yml
+++ b/.gitlab-ci.yml
@@ -40,6 +40,7 @@
# qemu_arm64_lwip_defconfig is the same as qemu_arm64 but with NET_LWIP enabled.
# The test config and the boardenv file from qemu_arm64 can be re-used so create symlinks
- ln -s conf.qemu_arm64_na /tmp/uboot-test-hooks/bin/travis-ci/conf.qemu_arm64_lwip_na
+ - ln -s u_boot_boardenv_qemu_arm64_na.py /tmp/uboot-test-hooks/py/travis-ci/u_boot_boardenv_qemu_arm64_lwip_na.py
- ln -s travis-ci /tmp/uboot-test-hooks/bin/`hostname`
- ln -s travis-ci /tmp/uboot-test-hooks/py/`hostname`
- if [[ "${TEST_PY_BD}" == "qemu-riscv32_spl" ]]; then
@@ -210,7 +211,7 @@
- . /tmp/venv/bin/activate
- pip install -r test/py/requirements.txt -r tools/binman/requirements.txt
-r tools/buildman/requirements.txt -r tools/patman/requirements.txt
- -r tools/u_boot_pylib/requirements.txt asteval pylint==2.12.2 pyopenssl
+ -r tools/u_boot_pylib/requirements.txt asteval pylint==3.3.4 pyopenssl
- export PATH=${PATH}:~/.local/bin
- echo "[MASTER]" >> .pylintrc
- echo "load-plugins=pylint.extensions.docparams" >> .pylintrc
diff --git a/MAINTAINERS b/MAINTAINERS
index 10f7f1f..687262b 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -151,9 +151,11 @@
ARM ALTERA SOCFPGA
M: Marek Vasut <marex@denx.de>
M: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
-M: Tien Fong Chee <tien.fong.chee@intel.com>
+M: Tien Fong Chee <tien.fong.chee@altera.com>
+M: Tingting Meng <tingting.meng@altera.com>
S: Maintained
T: git https://source.denx.de/u-boot/custodians/u-boot-socfpga.git
+F: drivers/ddr/altera/
F: arch/arm/mach-socfpga/
F: drivers/sysreset/sysreset_socfpga*
@@ -671,8 +673,7 @@
F: drivers/serial/serial_sti_asc.c
F: drivers/sysreset/sysreset_sti.c
F: drivers/timer/arm_global_timer.c
-F: drivers/usb/host/dwc3-sti-glue.c
-F: include/dwc3-sti-glue.h
+F: drivers/usb/host/dwc3-sti.c
F: include/dt-bindings/clock/stih407-clks.h
F: include/dt-bindings/clock/stih410-clks.h
F: include/dt-bindings/reset/stih407-resets.h
diff --git a/Makefile b/Makefile
index d4fedd8..5f90cea 100644
--- a/Makefile
+++ b/Makefile
@@ -3,7 +3,7 @@
VERSION = 2025
PATCHLEVEL = 04
SUBLEVEL =
-EXTRAVERSION = -rc2
+EXTRAVERSION = -rc3
NAME =
# *DOCUMENTATION*
@@ -1016,8 +1016,10 @@
# Generate this input file for binman
ifeq ($(CONFIG_SPL),)
+ifneq ($(patsubst "%",%,$(CONFIG_MTK_BROM_HEADER_INFO)),)
INPUTS-$(CONFIG_ARCH_MEDIATEK) += u-boot-mtk.bin
endif
+endif
# Add optional build target if defined in board/cpu/soc headers
ifneq ($(CONFIG_BUILD_TARGET),)
@@ -2512,7 +2514,7 @@
sed -e '/^\s*$$/d' | \
sort -t '=' -k 1,1 -s -o $@
-u-boot-initial-env: scripts_basic $(env_h) FORCE
+u-boot-initial-env: scripts_basic $(version_h) $(env_h) include/config.h FORCE
$(Q)$(MAKE) $(build)=tools $(objtree)/tools/printinitialenv
$(call if_changed,genenv)
diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
index da6f117..cf08fe6 100644
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@ -1128,7 +1128,6 @@
select CPU_V7A if TARGET_SOCFPGA_GEN5 || TARGET_SOCFPGA_ARRIA10
select DM
select DM_SERIAL
- select GICV2
select GPIO_EXTRA_HEADER
select ENABLE_ARM_SOC_BOOT0_HOOK if TARGET_SOCFPGA_GEN5 || TARGET_SOCFPGA_ARRIA10
select OF_CONTROL
@@ -1150,6 +1149,7 @@
select SYSRESET_SOCFPGA if TARGET_SOCFPGA_GEN5 || TARGET_SOCFPGA_ARRIA10
select SYSRESET_SOCFPGA_SOC64 if !TARGET_SOCFPGA_AGILEX5 && \
TARGET_SOCFPGA_SOC64
+ select SYSRESET_PSCI if TARGET_SOCFPGA_AGILEX5
imply CMD_DM
imply CMD_MTDPARTS
imply CRC32_VERIFY
diff --git a/arch/arm/cpu/armv8/spl_data.c b/arch/arm/cpu/armv8/spl_data.c
index 259b49f..492353c 100644
--- a/arch/arm/cpu/armv8/spl_data.c
+++ b/arch/arm/cpu/armv8/spl_data.c
@@ -5,23 +5,28 @@
#include <spl.h>
+char __data_start[0] __section(".__data_start");
char __data_save_start[0] __section(".__data_save_start");
char __data_save_end[0] __section(".__data_save_end");
u32 cold_reboot_flag = 1;
+u32 __weak reset_flag(void)
+{
+ return 1;
+}
+
void spl_save_restore_data(void)
{
u32 data_size = __data_save_end - __data_save_start;
+ cold_reboot_flag = reset_flag();
if (cold_reboot_flag == 1) {
/* Save data section to data_save section */
- memcpy(__data_save_start, __data_save_start - data_size,
- data_size);
+ memcpy(__data_save_start, __data_start, data_size);
} else {
/* Restore the data_save section to data section */
- memcpy(__data_save_start - data_size, __data_save_start,
- data_size);
+ memcpy(__data_start, __data_save_start, data_size);
}
cold_reboot_flag++;
diff --git a/arch/arm/cpu/armv8/transition.S b/arch/arm/cpu/armv8/transition.S
index 9dbdff3..85f13cc 100644
--- a/arch/arm/cpu/armv8/transition.S
+++ b/arch/arm/cpu/armv8/transition.S
@@ -9,8 +9,16 @@
#include <linux/linkage.h>
#include <asm/macro.h>
+.pushsection .text.armv8_switch_to_el2_prep, "ax"
+WEAK(armv8_switch_to_el2_prep)
+ ret
+ENDPROC(armv8_switch_to_el2_prep)
+.popsection
+
.pushsection .text.armv8_switch_to_el2, "ax"
ENTRY(armv8_switch_to_el2)
+ bl armv8_switch_to_el2_prep
+ nop
switch_el x6, 1f, 0f, 0f
0:
cmp x5, #ES_TO_AARCH64
diff --git a/arch/arm/cpu/armv8/u-boot-spl.lds b/arch/arm/cpu/armv8/u-boot-spl.lds
index fed6964..c4f83ec 100644
--- a/arch/arm/cpu/armv8/u-boot-spl.lds
+++ b/arch/arm/cpu/armv8/u-boot-spl.lds
@@ -37,6 +37,7 @@
.data : {
. = ALIGN(8);
+ *(.__data_start)
*(.data*)
} >.sram
diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile
index 0bf3697..85a03b5 100644
--- a/arch/arm/dts/Makefile
+++ b/arch/arm/dts/Makefile
@@ -52,9 +52,6 @@
dtb-$(CONFIG_MACH_S700) += \
s700-cubieboard7.dtb
-dtb-$(CONFIG_ROCKCHIP_RK3036) += \
- rk3036-sdk.dtb
-
dtb-$(CONFIG_ROCKCHIP_RK3128) += \
rk3128-evb.dtb
@@ -84,6 +81,7 @@
meson-a1-ad401.dtb
dtb-$(CONFIG_ARCH_TEGRA) += \
+ tegra20-acer-a500-picasso.dtb \
tegra20-asus-sl101.dtb \
tegra20-asus-tf101.dtb \
tegra20-asus-tf101g.dtb \
@@ -797,7 +795,6 @@
imx6q-icore-rqs.dtb \
imx6q-kp.dtb \
imx6q-logicpd.dtb \
- imx6q-lxr.dtb \
imx6q-marsboard.dtb \
imx6q-mccmon6.dtb\
imx6q-nitrogen6x.dtb \
@@ -920,8 +917,7 @@
imx93-var-som-symphony.dtb \
imx93-phyboard-segin.dtb
-dtb-$(CONFIG_ARCH_IMXRT) += imxrt1050-evk.dtb \
- imxrt1020-evk.dtb \
+dtb-$(CONFIG_ARCH_IMXRT) += imxrt1020-evk.dtb \
imxrt1170-evk.dtb \
dtb-$(CONFIG_RZA1) += \
diff --git a/arch/arm/dts/at91-sam9x60_curiosity.dts b/arch/arm/dts/at91-sam9x60_curiosity.dts
index 99867d2..7f00014 100644
--- a/arch/arm/dts/at91-sam9x60_curiosity.dts
+++ b/arch/arm/dts/at91-sam9x60_curiosity.dts
@@ -82,6 +82,11 @@
};
};
+&dbgu {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_dbgu>;
+};
+
&ebi {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_ebi_addr_nand &pinctrl_ebi_data_0_7>;
@@ -171,10 +176,20 @@
&macb0 {
phy-mode = "rmii";
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_macb0_rmii>;
status = "okay";
};
&pinctrl {
+ dbgu {
+ pinctrl_dbgu: dbgu-0 {
+ atmel,pins =
+ <AT91_PIOA 9 AT91_PERIPH_A AT91_PINCTRL_PULL_UP
+ AT91_PIOA 10 AT91_PERIPH_A AT91_PINCTRL_NONE>;
+ };
+ };
+
ebi {
pinctrl_ebi_data_0_7: ebi-data-lsb-0 {
atmel,pins =
@@ -217,6 +232,22 @@
};
};
+ macb0 {
+ pinctrl_macb0_rmii: macb0_rmii-0 {
+ atmel,pins =
+ <AT91_PIOB 0 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB0 periph A */
+ AT91_PIOB 1 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB1 periph A */
+ AT91_PIOB 2 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB2 periph A */
+ AT91_PIOB 3 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB3 periph A */
+ AT91_PIOB 4 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB4 periph A */
+ AT91_PIOB 5 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB5 periph A */
+ AT91_PIOB 6 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB6 periph A */
+ AT91_PIOB 7 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB7 periph A */
+ AT91_PIOB 9 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB9 periph A */
+ AT91_PIOB 10 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PB10 periph A */
+ };
+ };
+
nand {
pinctrl_nand_oe_we: nand-oe-we-0 {
atmel,pins =
@@ -240,6 +271,36 @@
<AT91_PIOD 14 AT91_PERIPH_GPIO AT91_PINCTRL_PULL_UP>;
};
+ sdhci0 {
+ pinctrl_sdhci0: sdhci0 {
+ atmel,pins =
+ <AT91_PIOA 17 AT91_PERIPH_A
+ (AT91_PINCTRL_DRIVE_STRENGTH_HI | AT91_PINCTRL_SLEWRATE_ENA) /* PA17 CK periph A with pullup */
+ AT91_PIOA 16 AT91_PERIPH_A
+ (AT91_PINCTRL_PULL_UP | AT91_PINCTRL_DRIVE_STRENGTH_HI | AT91_PINCTRL_SLEWRATE_ENA) /* PA16 CMD periph A with pullup */
+ AT91_PIOA 15 AT91_PERIPH_A
+ (AT91_PINCTRL_PULL_UP | AT91_PINCTRL_DRIVE_STRENGTH_HI | AT91_PINCTRL_SLEWRATE_ENA) /* PA15 DAT0 periph A */
+ AT91_PIOA 18 AT91_PERIPH_A
+ (AT91_PINCTRL_PULL_UP | AT91_PINCTRL_DRIVE_STRENGTH_HI | AT91_PINCTRL_SLEWRATE_ENA) /* PA18 DAT1 periph A with pullup */
+ AT91_PIOA 19 AT91_PERIPH_A
+ (AT91_PINCTRL_PULL_UP | AT91_PINCTRL_DRIVE_STRENGTH_HI | AT91_PINCTRL_SLEWRATE_ENA) /* PA19 DAT2 periph A with pullup */
+ AT91_PIOA 20 AT91_PERIPH_A
+ (AT91_PINCTRL_PULL_UP | AT91_PINCTRL_DRIVE_STRENGTH_HI | AT91_PINCTRL_SLEWRATE_ENA)>; /* PA20 DAT3 periph A with pullup */
+ };
+ };
+
+ sdhci1 {
+ pinctrl_sdhci1: sdhci1 {
+ atmel,pins =
+ <AT91_PIOA 13 AT91_PERIPH_B (AT91_PINCTRL_DRIVE_STRENGTH_HI) /* PA13 CK periph B */
+ AT91_PIOA 12 AT91_PERIPH_B (AT91_PINCTRL_PULL_UP | AT91_PINCTRL_DRIVE_STRENGTH_HI) /* PA12 CMD periph B with pullup */
+ AT91_PIOA 11 AT91_PERIPH_B (AT91_PINCTRL_PULL_UP | AT91_PINCTRL_DRIVE_STRENGTH_HI) /* PA11 DAT0 periph B with pullup */
+ AT91_PIOA 2 AT91_PERIPH_B (AT91_PINCTRL_PULL_UP | AT91_PINCTRL_DRIVE_STRENGTH_HI) /* PA2 DAT1 periph B with pullup */
+ AT91_PIOA 3 AT91_PERIPH_B (AT91_PINCTRL_PULL_UP | AT91_PINCTRL_DRIVE_STRENGTH_HI) /* PA3 DAT2 periph B with pullup */
+ AT91_PIOA 4 AT91_PERIPH_B (AT91_PINCTRL_PULL_UP | AT91_PINCTRL_DRIVE_STRENGTH_HI)>; /* PA4 DAT3 periph B with pullup */
+ };
+ };
+
usb1 {
pinctrl_usb_default: usb_default {
atmel,pins = <AT91_PIOD 15 AT91_PERIPH_GPIO AT91_PINCTRL_NONE
@@ -248,6 +309,16 @@
};
};
+&sdhci0 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_sdhci0>;
+};
+
+&sdhci1 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_sdhci1>;
+};
+
&usb1 {
num-ports = <3>;
atmel,vbus-gpio = <0
diff --git a/arch/arm/dts/at91sam9260.dtsi b/arch/arm/dts/at91sam9260.dtsi
index 4ea4202..8d49620 100644
--- a/arch/arm/dts/at91sam9260.dtsi
+++ b/arch/arm/dts/at91sam9260.dtsi
@@ -401,51 +401,11 @@
clock-names = "t0_clk", "t1_clk", "t2_clk", "slow_clk";
};
- pioA: gpio@fffff400 {
- compatible = "atmel,at91rm9200-gpio";
- reg = <0xfffff400 0x200>;
- interrupts = <2 IRQ_TYPE_LEVEL_HIGH 1>;
- #gpio-cells = <2>;
- gpio-controller;
- interrupt-controller;
- #interrupt-cells = <2>;
- clocks = <&pioA_clk>;
- bootph-all;
- };
-
- pioB: gpio@fffff600 {
- compatible = "atmel,at91rm9200-gpio";
- reg = <0xfffff600 0x200>;
- interrupts = <3 IRQ_TYPE_LEVEL_HIGH 1>;
- #gpio-cells = <2>;
- gpio-controller;
- interrupt-controller;
- #interrupt-cells = <2>;
- clocks = <&pioB_clk>;
- bootph-all;
- };
-
- pioC: gpio@fffff800 {
- compatible = "atmel,at91rm9200-gpio";
- reg = <0xfffff800 0x200>;
- interrupts = <4 IRQ_TYPE_LEVEL_HIGH 1>;
- #gpio-cells = <2>;
- gpio-controller;
- interrupt-controller;
- #interrupt-cells = <2>;
- clocks = <&pioC_clk>;
- bootph-all;
- };
-
pinctrl: pinctrl@fffff400 {
#address-cells = <1>;
#size-cells = <1>;
compatible = "atmel,at91rm9200-pinctrl", "simple-bus";
ranges = <0xfffff400 0xfffff400 0x600>;
- reg = <0xfffff400 0x200 /* pioA */
- 0xfffff600 0x200 /* pioB */
- 0xfffff800 0x200 /* pioC */
- >;
atmel,mux-mask = <
/* A B */
@@ -767,6 +727,42 @@
atmel,pins = <AT91_PIOB 19 AT91_PERIPH_B AT91_PINCTRL_NONE>;
};
};
+
+ pioA: gpio@fffff400 {
+ compatible = "atmel,at91rm9200-gpio";
+ reg = <0xfffff400 0x200>;
+ interrupts = <2 IRQ_TYPE_LEVEL_HIGH 1>;
+ #gpio-cells = <2>;
+ gpio-controller;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ clocks = <&pioA_clk>;
+ bootph-all;
+ };
+
+ pioB: gpio@fffff600 {
+ compatible = "atmel,at91rm9200-gpio";
+ reg = <0xfffff600 0x200>;
+ interrupts = <3 IRQ_TYPE_LEVEL_HIGH 1>;
+ #gpio-cells = <2>;
+ gpio-controller;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ clocks = <&pioB_clk>;
+ bootph-all;
+ };
+
+ pioC: gpio@fffff800 {
+ compatible = "atmel,at91rm9200-gpio";
+ reg = <0xfffff800 0x200>;
+ interrupts = <4 IRQ_TYPE_LEVEL_HIGH 1>;
+ #gpio-cells = <2>;
+ gpio-controller;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ clocks = <&pioC_clk>;
+ bootph-all;
+ };
};
dbgu: serial@fffff200 {
diff --git a/arch/arm/dts/at91sam9261.dtsi b/arch/arm/dts/at91sam9261.dtsi
index 804340e..65e0e4f 100644
--- a/arch/arm/dts/at91sam9261.dtsi
+++ b/arch/arm/dts/at91sam9261.dtsi
@@ -286,51 +286,12 @@
status = "disabled";
};
- pioA: gpio@fffff400 {
- compatible = "atmel,at91rm9200-gpio";
- reg = <0xfffff400 0x200>;
- interrupts = <2 IRQ_TYPE_LEVEL_HIGH 1>;
- #gpio-cells = <2>;
- gpio-controller;
- interrupt-controller;
- #interrupt-cells = <2>;
- clocks = <&pioA_clk>;
- bootph-all;
- };
-
- pioB: gpio@fffff600 {
- compatible = "atmel,at91rm9200-gpio";
- reg = <0xfffff600 0x200>;
- interrupts = <3 IRQ_TYPE_LEVEL_HIGH 1>;
- #gpio-cells = <2>;
- gpio-controller;
- interrupt-controller;
- #interrupt-cells = <2>;
- clocks = <&pioB_clk>;
- bootph-all;
- };
-
- pioC: gpio@fffff800 {
- compatible = "atmel,at91rm9200-gpio";
- reg = <0xfffff800 0x200>;
- interrupts = <4 IRQ_TYPE_LEVEL_HIGH 1>;
- #gpio-cells = <2>;
- gpio-controller;
- interrupt-controller;
- #interrupt-cells = <2>;
- clocks = <&pioC_clk>;
- bootph-all;
- };
-
pinctrl@fffff400 {
#address-cells = <1>;
#size-cells = <1>;
compatible = "atmel,at91rm9200-pinctrl", "simple-bus";
ranges = <0xfffff400 0xfffff400 0x600>;
- reg = <0xfffff400 0x200 /* pioA */
- 0xfffff600 0x200 /* pioB */
- 0xfffff800 0x200 /* pioC */
- >;
+
atmel,mux-mask =
/* A B */
<0xffffffff 0xfffffff7>, /* pioA */
@@ -573,6 +534,42 @@
<AT91_PIOB 28 AT91_PERIPH_B AT91_PINCTRL_NONE>;
};
};
+
+ pioA: gpio@fffff400 {
+ compatible = "atmel,at91rm9200-gpio";
+ reg = <0xfffff400 0x200>;
+ interrupts = <2 IRQ_TYPE_LEVEL_HIGH 1>;
+ #gpio-cells = <2>;
+ gpio-controller;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ clocks = <&pioA_clk>;
+ bootph-all;
+ };
+
+ pioB: gpio@fffff600 {
+ compatible = "atmel,at91rm9200-gpio";
+ reg = <0xfffff600 0x200>;
+ interrupts = <3 IRQ_TYPE_LEVEL_HIGH 1>;
+ #gpio-cells = <2>;
+ gpio-controller;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ clocks = <&pioB_clk>;
+ bootph-all;
+ };
+
+ pioC: gpio@fffff800 {
+ compatible = "atmel,at91rm9200-gpio";
+ reg = <0xfffff800 0x200>;
+ interrupts = <4 IRQ_TYPE_LEVEL_HIGH 1>;
+ #gpio-cells = <2>;
+ gpio-controller;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ clocks = <&pioC_clk>;
+ bootph-all;
+ };
};
pmc: pmc@fffffc00 {
diff --git a/arch/arm/dts/at91sam9263.dtsi b/arch/arm/dts/at91sam9263.dtsi
index 98cdd8e..55b7966 100644
--- a/arch/arm/dts/at91sam9263.dtsi
+++ b/arch/arm/dts/at91sam9263.dtsi
@@ -404,12 +404,6 @@
#size-cells = <1>;
compatible = "atmel,at91rm9200-pinctrl", "simple-bus";
ranges = <0xfffff200 0xfffff200 0xa00>;
- reg = <0xfffff200 0x200
- 0xfffff400 0x200
- 0xfffff600 0x200
- 0xfffff800 0x200
- 0xfffffa00 0x200
- >;
atmel,mux-mask = <
/* A B */
@@ -719,66 +713,65 @@
};
};
- };
-
- pioA: gpio@fffff200 {
- compatible = "atmel,at91rm9200-gpio";
- reg = <0xfffff200 0x200>;
- interrupts = <2 IRQ_TYPE_LEVEL_HIGH 1>;
- #gpio-cells = <2>;
- gpio-controller;
- interrupt-controller;
- #interrupt-cells = <2>;
- clocks = <&pioA_clk>;
- bootph-all;
- };
+ pioA: gpio@fffff200 {
+ compatible = "atmel,at91rm9200-gpio";
+ reg = <0xfffff200 0x200>;
+ interrupts = <2 IRQ_TYPE_LEVEL_HIGH 1>;
+ #gpio-cells = <2>;
+ gpio-controller;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ clocks = <&pioA_clk>;
+ bootph-all;
+ };
- pioB: gpio@fffff400 {
- compatible = "atmel,at91rm9200-gpio";
- reg = <0xfffff400 0x200>;
- interrupts = <3 IRQ_TYPE_LEVEL_HIGH 1>;
- #gpio-cells = <2>;
- gpio-controller;
- interrupt-controller;
- #interrupt-cells = <2>;
- clocks = <&pioB_clk>;
- bootph-all;
- };
+ pioB: gpio@fffff400 {
+ compatible = "atmel,at91rm9200-gpio";
+ reg = <0xfffff400 0x200>;
+ interrupts = <3 IRQ_TYPE_LEVEL_HIGH 1>;
+ #gpio-cells = <2>;
+ gpio-controller;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ clocks = <&pioB_clk>;
+ bootph-all;
+ };
- pioC: gpio@fffff600 {
- compatible = "atmel,at91rm9200-gpio";
- reg = <0xfffff600 0x200>;
- interrupts = <4 IRQ_TYPE_LEVEL_HIGH 1>;
- #gpio-cells = <2>;
- gpio-controller;
- interrupt-controller;
- #interrupt-cells = <2>;
- clocks = <&pioCDE_clk>;
- bootph-all;
- };
+ pioC: gpio@fffff600 {
+ compatible = "atmel,at91rm9200-gpio";
+ reg = <0xfffff600 0x200>;
+ interrupts = <4 IRQ_TYPE_LEVEL_HIGH 1>;
+ #gpio-cells = <2>;
+ gpio-controller;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ clocks = <&pioCDE_clk>;
+ bootph-all;
+ };
- pioD: gpio@fffff800 {
- compatible = "atmel,at91rm9200-gpio";
- reg = <0xfffff800 0x200>;
- interrupts = <4 IRQ_TYPE_LEVEL_HIGH 1>;
- #gpio-cells = <2>;
- gpio-controller;
- interrupt-controller;
- #interrupt-cells = <2>;
- clocks = <&pioCDE_clk>;
- bootph-all;
- };
+ pioD: gpio@fffff800 {
+ compatible = "atmel,at91rm9200-gpio";
+ reg = <0xfffff800 0x200>;
+ interrupts = <4 IRQ_TYPE_LEVEL_HIGH 1>;
+ #gpio-cells = <2>;
+ gpio-controller;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ clocks = <&pioCDE_clk>;
+ bootph-all;
+ };
- pioE: gpio@fffffa00 {
- compatible = "atmel,at91rm9200-gpio";
- reg = <0xfffffa00 0x200>;
- interrupts = <4 IRQ_TYPE_LEVEL_HIGH 1>;
- #gpio-cells = <2>;
- gpio-controller;
- interrupt-controller;
- #interrupt-cells = <2>;
- clocks = <&pioCDE_clk>;
- bootph-all;
+ pioE: gpio@fffffa00 {
+ compatible = "atmel,at91rm9200-gpio";
+ reg = <0xfffffa00 0x200>;
+ interrupts = <4 IRQ_TYPE_LEVEL_HIGH 1>;
+ #gpio-cells = <2>;
+ gpio-controller;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ clocks = <&pioCDE_clk>;
+ bootph-all;
+ };
};
dbgu: serial@ffffee00 {
diff --git a/arch/arm/dts/at91sam9g45.dtsi b/arch/arm/dts/at91sam9g45.dtsi
index d0bcd79..63a0613 100644
--- a/arch/arm/dts/at91sam9g45.dtsi
+++ b/arch/arm/dts/at91sam9g45.dtsi
@@ -435,12 +435,6 @@
#size-cells = <1>;
compatible = "atmel,at91rm9200-pinctrl", "simple-bus";
ranges = <0xfffff200 0xfffff200 0xa00>;
- reg = <0xfffff200 0x200
- 0xfffff400 0x200
- 0xfffff600 0x200
- 0xfffff800 0x200
- 0xfffffa00 0x200
- >;
bootph-all;
atmel,mux-mask = <
@@ -854,61 +848,61 @@
AT91_PIOE 30 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PE30 periph A */
};
};
- };
- pioA: gpio@fffff200 {
- compatible = "atmel,at91rm9200-gpio";
- reg = <0xfffff200 0x200>;
- interrupts = <2 IRQ_TYPE_LEVEL_HIGH 1>;
- #gpio-cells = <2>;
- gpio-controller;
- interrupt-controller;
- #interrupt-cells = <2>;
- clocks = <&pioA_clk>;
- };
+ pioA: gpio@fffff200 {
+ compatible = "atmel,at91rm9200-gpio";
+ reg = <0xfffff200 0x200>;
+ interrupts = <2 IRQ_TYPE_LEVEL_HIGH 1>;
+ #gpio-cells = <2>;
+ gpio-controller;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ clocks = <&pioA_clk>;
+ };
- pioB: gpio@fffff400 {
- compatible = "atmel,at91rm9200-gpio";
- reg = <0xfffff400 0x200>;
- interrupts = <3 IRQ_TYPE_LEVEL_HIGH 1>;
- #gpio-cells = <2>;
- gpio-controller;
- interrupt-controller;
- #interrupt-cells = <2>;
- clocks = <&pioB_clk>;
- };
+ pioB: gpio@fffff400 {
+ compatible = "atmel,at91rm9200-gpio";
+ reg = <0xfffff400 0x200>;
+ interrupts = <3 IRQ_TYPE_LEVEL_HIGH 1>;
+ #gpio-cells = <2>;
+ gpio-controller;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ clocks = <&pioB_clk>;
+ };
- pioC: gpio@fffff600 {
- compatible = "atmel,at91rm9200-gpio";
- reg = <0xfffff600 0x200>;
- interrupts = <4 IRQ_TYPE_LEVEL_HIGH 1>;
- #gpio-cells = <2>;
- gpio-controller;
- interrupt-controller;
- #interrupt-cells = <2>;
- clocks = <&pioC_clk>;
- };
+ pioC: gpio@fffff600 {
+ compatible = "atmel,at91rm9200-gpio";
+ reg = <0xfffff600 0x200>;
+ interrupts = <4 IRQ_TYPE_LEVEL_HIGH 1>;
+ #gpio-cells = <2>;
+ gpio-controller;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ clocks = <&pioC_clk>;
+ };
- pioD: gpio@fffff800 {
- compatible = "atmel,at91rm9200-gpio";
- reg = <0xfffff800 0x200>;
- interrupts = <5 IRQ_TYPE_LEVEL_HIGH 1>;
- #gpio-cells = <2>;
- gpio-controller;
- interrupt-controller;
- #interrupt-cells = <2>;
- clocks = <&pioDE_clk>;
- };
+ pioD: gpio@fffff800 {
+ compatible = "atmel,at91rm9200-gpio";
+ reg = <0xfffff800 0x200>;
+ interrupts = <5 IRQ_TYPE_LEVEL_HIGH 1>;
+ #gpio-cells = <2>;
+ gpio-controller;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ clocks = <&pioDE_clk>;
+ };
- pioE: gpio@fffffa00 {
- compatible = "atmel,at91rm9200-gpio";
- reg = <0xfffffa00 0x200>;
- interrupts = <5 IRQ_TYPE_LEVEL_HIGH 1>;
- #gpio-cells = <2>;
- gpio-controller;
- interrupt-controller;
- #interrupt-cells = <2>;
- clocks = <&pioDE_clk>;
+ pioE: gpio@fffffa00 {
+ compatible = "atmel,at91rm9200-gpio";
+ reg = <0xfffffa00 0x200>;
+ interrupts = <5 IRQ_TYPE_LEVEL_HIGH 1>;
+ #gpio-cells = <2>;
+ gpio-controller;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ clocks = <&pioDE_clk>;
+ };
};
dbgu: serial@ffffee00 {
diff --git a/arch/arm/dts/at91sam9n12.dtsi b/arch/arm/dts/at91sam9n12.dtsi
index cb3a037..8408983 100644
--- a/arch/arm/dts/at91sam9n12.dtsi
+++ b/arch/arm/dts/at91sam9n12.dtsi
@@ -492,11 +492,6 @@
#size-cells = <1>;
compatible = "atmel,at91sam9x5-pinctrl", "atmel,at91rm9200-pinctrl", "simple-bus";
ranges = <0xfffff400 0xfffff400 0x800>;
- reg = <0xfffff400 0x200
- 0xfffff600 0x200
- 0xfffff800 0x200
- 0xfffffa00 0x200
- >;
atmel,mux-mask = <
/* A B C */
@@ -795,54 +790,54 @@
atmel,pins = <AT91_PIOC 13 AT91_PERIPH_C AT91_PINCTRL_NONE>;
};
};
- };
- pioA: gpio@fffff400 {
- compatible = "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio";
- reg = <0xfffff400 0x200>;
- interrupts = <2 IRQ_TYPE_LEVEL_HIGH 1>;
- #gpio-cells = <2>;
- gpio-controller;
- interrupt-controller;
- #interrupt-cells = <2>;
- clocks = <&pioAB_clk>;
- bootph-all;
- };
+ pioA: gpio@fffff400 {
+ compatible = "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio";
+ reg = <0xfffff400 0x200>;
+ interrupts = <2 IRQ_TYPE_LEVEL_HIGH 1>;
+ #gpio-cells = <2>;
+ gpio-controller;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ clocks = <&pioAB_clk>;
+ bootph-all;
+ };
- pioB: gpio@fffff600 {
- compatible = "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio";
- reg = <0xfffff600 0x200>;
- interrupts = <2 IRQ_TYPE_LEVEL_HIGH 1>;
- #gpio-cells = <2>;
- gpio-controller;
- interrupt-controller;
- #interrupt-cells = <2>;
- clocks = <&pioAB_clk>;
- bootph-all;
- };
+ pioB: gpio@fffff600 {
+ compatible = "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio";
+ reg = <0xfffff600 0x200>;
+ interrupts = <2 IRQ_TYPE_LEVEL_HIGH 1>;
+ #gpio-cells = <2>;
+ gpio-controller;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ clocks = <&pioAB_clk>;
+ bootph-all;
+ };
- pioC: gpio@fffff800 {
- compatible = "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio";
- reg = <0xfffff800 0x200>;
- interrupts = <3 IRQ_TYPE_LEVEL_HIGH 1>;
- #gpio-cells = <2>;
- gpio-controller;
- interrupt-controller;
- #interrupt-cells = <2>;
- clocks = <&pioCD_clk>;
- bootph-all;
- };
+ pioC: gpio@fffff800 {
+ compatible = "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio";
+ reg = <0xfffff800 0x200>;
+ interrupts = <3 IRQ_TYPE_LEVEL_HIGH 1>;
+ #gpio-cells = <2>;
+ gpio-controller;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ clocks = <&pioCD_clk>;
+ bootph-all;
+ };
- pioD: gpio@fffffa00 {
- compatible = "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio";
- reg = <0xfffffa00 0x200>;
- interrupts = <3 IRQ_TYPE_LEVEL_HIGH 1>;
- #gpio-cells = <2>;
- gpio-controller;
- interrupt-controller;
- #interrupt-cells = <2>;
- clocks = <&pioCD_clk>;
- bootph-all;
+ pioD: gpio@fffffa00 {
+ compatible = "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio";
+ reg = <0xfffffa00 0x200>;
+ interrupts = <3 IRQ_TYPE_LEVEL_HIGH 1>;
+ #gpio-cells = <2>;
+ gpio-controller;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ clocks = <&pioCD_clk>;
+ bootph-all;
+ };
};
dbgu: serial@fffff200 {
diff --git a/arch/arm/dts/at91sam9rl.dtsi b/arch/arm/dts/at91sam9rl.dtsi
index b855c8f..3b99de2 100644
--- a/arch/arm/dts/at91sam9rl.dtsi
+++ b/arch/arm/dts/at91sam9rl.dtsi
@@ -386,11 +386,6 @@
#size-cells = <1>;
compatible = "atmel,at91rm9200-pinctrl", "simple-bus";
ranges = <0xfffff400 0xfffff400 0x800>;
- reg = <0xfffff400 0x200
- 0xfffff600 0x200
- 0xfffff800 0x200
- 0xfffffa00 0x200
- >;
atmel,mux-mask =
/* A B */
@@ -768,54 +763,54 @@
<AT91_PIOA 20 AT91_PERIPH_B AT91_PINCTRL_NONE>;
};
};
- };
- pioA: gpio@fffff400 {
- compatible = "atmel,at91rm9200-gpio";
- reg = <0xfffff400 0x200>;
- interrupts = <2 IRQ_TYPE_LEVEL_HIGH 1>;
- #gpio-cells = <2>;
- gpio-controller;
- interrupt-controller;
- #interrupt-cells = <2>;
- clocks = <&pioA_clk>;
- bootph-all;
- };
+ pioA: gpio@fffff400 {
+ compatible = "atmel,at91rm9200-gpio";
+ reg = <0xfffff400 0x200>;
+ interrupts = <2 IRQ_TYPE_LEVEL_HIGH 1>;
+ #gpio-cells = <2>;
+ gpio-controller;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ clocks = <&pioA_clk>;
+ bootph-all;
+ };
- pioB: gpio@fffff600 {
- compatible = "atmel,at91rm9200-gpio";
- reg = <0xfffff600 0x200>;
- interrupts = <3 IRQ_TYPE_LEVEL_HIGH 1>;
- #gpio-cells = <2>;
- gpio-controller;
- interrupt-controller;
- #interrupt-cells = <2>;
- clocks = <&pioB_clk>;
- bootph-all;
- };
+ pioB: gpio@fffff600 {
+ compatible = "atmel,at91rm9200-gpio";
+ reg = <0xfffff600 0x200>;
+ interrupts = <3 IRQ_TYPE_LEVEL_HIGH 1>;
+ #gpio-cells = <2>;
+ gpio-controller;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ clocks = <&pioB_clk>;
+ bootph-all;
+ };
- pioC: gpio@fffff800 {
- compatible = "atmel,at91rm9200-gpio";
- reg = <0xfffff800 0x200>;
- interrupts = <4 IRQ_TYPE_LEVEL_HIGH 1>;
- #gpio-cells = <2>;
- gpio-controller;
- interrupt-controller;
- #interrupt-cells = <2>;
- clocks = <&pioC_clk>;
- bootph-all;
- };
+ pioC: gpio@fffff800 {
+ compatible = "atmel,at91rm9200-gpio";
+ reg = <0xfffff800 0x200>;
+ interrupts = <4 IRQ_TYPE_LEVEL_HIGH 1>;
+ #gpio-cells = <2>;
+ gpio-controller;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ clocks = <&pioC_clk>;
+ bootph-all;
+ };
- pioD: gpio@fffffa00 {
- compatible = "atmel,at91rm9200-gpio";
- reg = <0xfffffa00 0x200>;
- interrupts = <5 IRQ_TYPE_LEVEL_HIGH 1>;
- #gpio-cells = <2>;
- gpio-controller;
- interrupt-controller;
- #interrupt-cells = <2>;
- clocks = <&pioD_clk>;
- bootph-all;
+ pioD: gpio@fffffa00 {
+ compatible = "atmel,at91rm9200-gpio";
+ reg = <0xfffffa00 0x200>;
+ interrupts = <5 IRQ_TYPE_LEVEL_HIGH 1>;
+ #gpio-cells = <2>;
+ gpio-controller;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ clocks = <&pioD_clk>;
+ bootph-all;
+ };
};
pmc: pmc@fffffc00 {
diff --git a/arch/arm/dts/at91sam9x5.dtsi b/arch/arm/dts/at91sam9x5.dtsi
index 5fca9b1..4c6d8b9b 100644
--- a/arch/arm/dts/at91sam9x5.dtsi
+++ b/arch/arm/dts/at91sam9x5.dtsi
@@ -461,14 +461,8 @@
#size-cells = <1>;
compatible = "atmel,at91sam9x5-pinctrl", "atmel,at91rm9200-pinctrl", "simple-bus";
ranges = <0xfffff400 0xfffff400 0x800>;
- reg = <0xfffff400 0x200 /* pioA */
- 0xfffff600 0x200 /* pioB */
- 0xfffff800 0x200 /* pioC */
- 0xfffffa00 0x200 /* pioD */
- >;
bootph-all;
-
/* shared pinctrl settings */
dbgu {
bootph-all;
@@ -831,52 +825,52 @@
atmel,pins = <AT91_PIOC 13 AT91_PERIPH_C AT91_PINCTRL_NONE>;
};
};
- };
- pioA: gpio@fffff400 {
- compatible = "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio";
- reg = <0xfffff400 0x200>;
- interrupts = <2 IRQ_TYPE_LEVEL_HIGH 1>;
- #gpio-cells = <2>;
- gpio-controller;
- interrupt-controller;
- #interrupt-cells = <2>;
- clocks = <&pioAB_clk>;
- };
+ pioA: gpio@fffff400 {
+ compatible = "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio";
+ reg = <0xfffff400 0x200>;
+ interrupts = <2 IRQ_TYPE_LEVEL_HIGH 1>;
+ #gpio-cells = <2>;
+ gpio-controller;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ clocks = <&pioAB_clk>;
+ };
- pioB: gpio@fffff600 {
- compatible = "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio";
- reg = <0xfffff600 0x200>;
- interrupts = <2 IRQ_TYPE_LEVEL_HIGH 1>;
- #gpio-cells = <2>;
- gpio-controller;
- #gpio-lines = <19>;
- interrupt-controller;
- #interrupt-cells = <2>;
- clocks = <&pioAB_clk>;
- };
+ pioB: gpio@fffff600 {
+ compatible = "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio";
+ reg = <0xfffff600 0x200>;
+ interrupts = <2 IRQ_TYPE_LEVEL_HIGH 1>;
+ #gpio-cells = <2>;
+ gpio-controller;
+ #gpio-lines = <19>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ clocks = <&pioAB_clk>;
+ };
- pioC: gpio@fffff800 {
- compatible = "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio";
- reg = <0xfffff800 0x200>;
- interrupts = <3 IRQ_TYPE_LEVEL_HIGH 1>;
- #gpio-cells = <2>;
- gpio-controller;
- interrupt-controller;
- #interrupt-cells = <2>;
- clocks = <&pioCD_clk>;
- };
+ pioC: gpio@fffff800 {
+ compatible = "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio";
+ reg = <0xfffff800 0x200>;
+ interrupts = <3 IRQ_TYPE_LEVEL_HIGH 1>;
+ #gpio-cells = <2>;
+ gpio-controller;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ clocks = <&pioCD_clk>;
+ };
- pioD: gpio@fffffa00 {
- compatible = "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio";
- reg = <0xfffffa00 0x200>;
- interrupts = <3 IRQ_TYPE_LEVEL_HIGH 1>;
- #gpio-cells = <2>;
- gpio-controller;
- #gpio-lines = <22>;
- interrupt-controller;
- #interrupt-cells = <2>;
- clocks = <&pioCD_clk>;
+ pioD: gpio@fffffa00 {
+ compatible = "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio";
+ reg = <0xfffffa00 0x200>;
+ interrupts = <3 IRQ_TYPE_LEVEL_HIGH 1>;
+ #gpio-cells = <2>;
+ gpio-controller;
+ #gpio-lines = <22>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ clocks = <&pioCD_clk>;
+ };
};
ssc0: ssc@f0010000 {
diff --git a/arch/arm/dts/imx6q-lxr.dts b/arch/arm/dts/imx6q-lxr.dts
deleted file mode 100644
index ae4f8ee..0000000
--- a/arch/arm/dts/imx6q-lxr.dts
+++ /dev/null
@@ -1,87 +0,0 @@
-// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
-//
-// Copyright 2024 Comvetia AG
-
-/dts-v1/;
-#include "imx6q-phytec-pfla02.dtsi"
-
-/ {
- model = "COMVETIA QSoIP LXR-2";
- compatible = "comvetia,imx6q-lxr", "phytec,imx6q-pfla02", "fsl,imx6q";
-
- chosen {
- stdout-path = &uart4;
- };
-
- spi {
- compatible = "spi-gpio";
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_spi_gpio>;
- sck-gpios = <&gpio5 8 GPIO_ACTIVE_HIGH>;
- mosi-gpios = <&gpio5 7 GPIO_ACTIVE_HIGH>;
- num-chipselects = <0>;
- #address-cells = <1>;
- #size-cells = <0>;
-
- fpga@0 {
- compatible = "altr,fpga-passive-serial";
- reg = <0>;
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_fpga>;
- nconfig-gpios = <&gpio4 18 GPIO_ACTIVE_LOW>;
- nstat-gpios = <&gpio4 19 GPIO_ACTIVE_LOW>;
- confd-gpios = <&gpio1 6 GPIO_ACTIVE_HIGH>;
- };
- };
-};
-
-&ecspi3 {
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_ecspi3>;
- cs-gpios = <&gpio4 24 GPIO_ACTIVE_LOW>;
- status = "okay";
-
- flash@0 {
- compatible = "jedec,spi-nor";
- reg = <0>;
- spi-max-frequency = <20000000>;
- };
-};
-
-&fec {
- status = "okay";
-};
-
-&i2c3 {
- status = "okay";
-};
-
-&uart3 {
- status = "okay";
-};
-
-&uart4 {
- status = "okay";
-};
-
-&usdhc3 {
- no-1-8-v;
- status = "okay";
-};
-
-&iomuxc {
- pinctrl_fpga: fpgagrp {
- fsl,pins = <
- MX6QDL_PAD_GPIO_6__GPIO1_IO06 0x1b0b0
- MX6QDL_PAD_DI0_PIN2__GPIO4_IO18 0x1b0b0
- MX6QDL_PAD_DI0_PIN3__GPIO4_IO19 0x1b0b0
- >;
- };
-
- pinctrl_spi_gpio: spigpiogrp {
- fsl,pins = <
- MX6QDL_PAD_DISP0_DAT14__GPIO5_IO08 0x1b0b0
- MX6QDL_PAD_DISP0_DAT13__GPIO5_IO07 0x1b0b0
- >;
- };
-};
diff --git a/arch/arm/dts/imx6q-phytec-pfla02.dtsi b/arch/arm/dts/imx6q-phytec-pfla02.dtsi
deleted file mode 100644
index 500944b..0000000
--- a/arch/arm/dts/imx6q-phytec-pfla02.dtsi
+++ /dev/null
@@ -1,17 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0-or-later
-/*
- * Copyright 2013 Christian Hemp, Phytec Messtechnik GmbH
- */
-
-#include "imx6q.dtsi"
-#include "imx6qdl-phytec-pfla02.dtsi"
-
-/ {
- model = "Phytec phyFLEX-i.MX6 Quad";
- compatible = "phytec,imx6q-pfla02", "fsl,imx6q";
-
- memory@10000000 {
- device_type = "memory";
- reg = <0x10000000 0x80000000>;
- };
-};
diff --git a/arch/arm/dts/imx6qdl-phytec-pfla02.dtsi b/arch/arm/dts/imx6qdl-phytec-pfla02.dtsi
deleted file mode 100644
index c0c47ad..0000000
--- a/arch/arm/dts/imx6qdl-phytec-pfla02.dtsi
+++ /dev/null
@@ -1,467 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0-or-later
-/*
- * Copyright 2013 Christian Hemp, Phytec Messtechnik GmbH
- */
-
-#include <dt-bindings/gpio/gpio.h>
-
-/ {
- model = "Phytec phyFLEX-i.MX6 Quad";
- compatible = "phytec,imx6q-pfla02", "fsl,imx6q";
-
- memory@10000000 {
- device_type = "memory";
- reg = <0x10000000 0x80000000>;
- };
-
- reg_usb_otg_vbus: regulator-usb-otg-vbus {
- compatible = "regulator-fixed";
- regulator-name = "usb_otg_vbus";
- regulator-min-microvolt = <5000000>;
- regulator-max-microvolt = <5000000>;
- gpio = <&gpio4 15 0>;
- enable-active-high;
- };
-
- reg_usb_h1_vbus: regulator-usb-h1-vbus {
- compatible = "regulator-fixed";
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_usbh1_vbus>;
- regulator-name = "usb_h1_vbus";
- regulator-min-microvolt = <5000000>;
- regulator-max-microvolt = <5000000>;
- gpio = <&gpio1 0 0>;
- enable-active-high;
- };
-
- gpio_leds: leds {
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_leds>;
- compatible = "gpio-leds";
-
- led_green: led-green {
- label = "phyflex:green";
- gpios = <&gpio1 30 0>;
- };
-
- led_red: led-red {
- label = "phyflex:red";
- gpios = <&gpio2 31 0>;
- };
- };
-};
-
-&audmux {
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_audmux>;
- status = "disabled";
-};
-
-&can1 {
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_flexcan1>;
- status = "disabled";
-};
-
-&ecspi3 {
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_ecspi3>;
- status = "okay";
- cs-gpios = <&gpio4 24 GPIO_ACTIVE_LOW>;
-
- som_flash: flash@0 {
- compatible = "m25p80", "jedec,spi-nor";
- spi-max-frequency = <20000000>;
- reg = <0>;
- };
-};
-
-&fec {
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_enet>;
- phy-handle = <ðphy>;
- phy-mode = "rgmii";
- phy-reset-duration = <10>; /* in msecs */
- phy-reset-gpios = <&gpio3 23 GPIO_ACTIVE_LOW>;
- phy-supply = <&vdd_eth_io_reg>;
- status = "disabled";
-
- fec_mdio: mdio {
- #address-cells = <1>;
- #size-cells = <0>;
-
- ethphy: ethernet-phy@0 {
- compatible = "ethernet-phy-ieee802.3-c22";
- reg = <0>;
- txc-skew-ps = <1680>;
- rxc-skew-ps = <1860>;
- };
- };
-};
-
-&gpmi {
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_gpmi_nand>;
- nand-on-flash-bbt;
- status = "okay";
-};
-
-&i2c1 {
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_i2c1>;
- status = "okay";
-
- som_eeprom: eeprom@50 {
- compatible = "catalyst,24c32", "atmel,24c32";
- pagesize = <32>;
- reg = <0x50>;
- };
-
- pmic@58 {
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_pmic>;
- compatible = "dlg,da9063";
- reg = <0x58>;
- interrupt-parent = <&gpio2>;
- interrupts = <9 IRQ_TYPE_LEVEL_LOW>; /* active-low GPIO2_9 */
- #interrupt-cells = <2>;
- interrupt-controller;
-
- regulators {
- vddcore_reg: bcore1 {
- regulator-min-microvolt = <730000>;
- regulator-max-microvolt = <1380000>;
- regulator-always-on;
- };
-
- vddsoc_reg: bcore2 {
- regulator-min-microvolt = <730000>;
- regulator-max-microvolt = <1380000>;
- regulator-always-on;
- };
-
- vdd_ddr3_reg: bpro {
- regulator-min-microvolt = <1500000>;
- regulator-max-microvolt = <1500000>;
- regulator-always-on;
- };
-
- vdd_3v3_reg: bperi {
- regulator-min-microvolt = <3300000>;
- regulator-max-microvolt = <3300000>;
- regulator-always-on;
- };
-
- vdd_buckmem_reg: bmem {
- regulator-min-microvolt = <3300000>;
- regulator-max-microvolt = <3300000>;
- regulator-always-on;
- };
-
- vdd_eth_reg: bio {
- regulator-min-microvolt = <1200000>;
- regulator-max-microvolt = <1200000>;
- regulator-always-on;
- };
-
- vdd_eth_io_reg: ldo4 {
- regulator-min-microvolt = <2500000>;
- regulator-max-microvolt = <2500000>;
- regulator-always-on;
- };
-
- vdd_mx6_snvs_reg: ldo5 {
- regulator-min-microvolt = <3000000>;
- regulator-max-microvolt = <3000000>;
- regulator-always-on;
- };
-
- vdd_3v3_pmic_io_reg: ldo6 {
- regulator-min-microvolt = <3300000>;
- regulator-max-microvolt = <3300000>;
- regulator-always-on;
- };
-
- vdd_sd0_reg: ldo9 {
- regulator-min-microvolt = <3300000>;
- regulator-max-microvolt = <3300000>;
- };
-
- vdd_sd1_reg: ldo10 {
- regulator-min-microvolt = <3300000>;
- regulator-max-microvolt = <3300000>;
- };
-
- vdd_mx6_high_reg: ldo11 {
- regulator-min-microvolt = <3000000>;
- regulator-max-microvolt = <3000000>;
- regulator-always-on;
- };
- };
-
- da9063_rtc: rtc {
- compatible = "dlg,da9063-rtc";
- };
-
- da9063_wdog: watchdog {
- compatible = "dlg,da9063-watchdog";
- };
-
- onkey {
- compatible = "dlg,da9063-onkey";
- status = "disabled";
- };
- };
-};
-
-&i2c2 {
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_i2c2>;
- clock-frequency = <100000>;
-};
-
-&i2c3 {
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_i2c3>;
- clock-frequency = <100000>;
-};
-
-&iomuxc {
- imx6q-phytec-pfla02 {
- pinctrl_ecspi3: ecspi3grp {
- fsl,pins = <
- MX6QDL_PAD_DISP0_DAT2__ECSPI3_MISO 0x100b1
- MX6QDL_PAD_DISP0_DAT1__ECSPI3_MOSI 0x100b1
- MX6QDL_PAD_DISP0_DAT0__ECSPI3_SCLK 0x100b1
- MX6QDL_PAD_DISP0_DAT3__GPIO4_IO24 0x80000000 /* CS0 */
- >;
- };
-
- pinctrl_enet: enetgrp {
- fsl,pins = <
- MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x1b0b0
- MX6QDL_PAD_ENET_MDC__ENET_MDC 0x1b0b0
- MX6QDL_PAD_RGMII_TXC__RGMII_TXC 0x1b030
- MX6QDL_PAD_RGMII_TD0__RGMII_TD0 0x1b030
- MX6QDL_PAD_RGMII_TD1__RGMII_TD1 0x1b030
- MX6QDL_PAD_RGMII_TD2__RGMII_TD2 0x1b030
- MX6QDL_PAD_RGMII_TD3__RGMII_TD3 0x1b030
- MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x1b030
- MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK 0x1b0b0
- MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x1b030
- MX6QDL_PAD_RGMII_RD0__RGMII_RD0 0x1b030
- MX6QDL_PAD_RGMII_RD1__RGMII_RD1 0x1b030
- MX6QDL_PAD_RGMII_RD2__RGMII_RD2 0x1b030
- MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x1b030
- MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b030
- MX6QDL_PAD_ENET_TX_EN__ENET_TX_EN 0x1b0b0
- MX6QDL_PAD_EIM_D23__GPIO3_IO23 0x80000000 /* Reset GPIO */
- >;
- };
-
- pinctrl_flexcan1: flexcan1grp {
- fsl,pins = <
- MX6QDL_PAD_KEY_ROW2__FLEXCAN1_RX 0x1b0b0
- MX6QDL_PAD_KEY_COL2__FLEXCAN1_TX 0x1b0b0
- >;
- };
-
- pinctrl_gpmi_nand: gpminandgrp {
- fsl,pins = <
- MX6QDL_PAD_NANDF_CLE__NAND_CLE 0xb0b1
- MX6QDL_PAD_NANDF_ALE__NAND_ALE 0xb0b1
- MX6QDL_PAD_NANDF_WP_B__NAND_WP_B 0xb0b1
- MX6QDL_PAD_NANDF_RB0__NAND_READY_B 0xb000
- MX6QDL_PAD_NANDF_CS0__NAND_CE0_B 0xb0b1
- MX6QDL_PAD_NANDF_CS1__NAND_CE1_B 0xb0b1
- MX6QDL_PAD_SD4_CMD__NAND_RE_B 0xb0b1
- MX6QDL_PAD_SD4_CLK__NAND_WE_B 0xb0b1
- MX6QDL_PAD_NANDF_D0__NAND_DATA00 0xb0b1
- MX6QDL_PAD_NANDF_D1__NAND_DATA01 0xb0b1
- MX6QDL_PAD_NANDF_D2__NAND_DATA02 0xb0b1
- MX6QDL_PAD_NANDF_D3__NAND_DATA03 0xb0b1
- MX6QDL_PAD_NANDF_D4__NAND_DATA04 0xb0b1
- MX6QDL_PAD_NANDF_D5__NAND_DATA05 0xb0b1
- MX6QDL_PAD_NANDF_D6__NAND_DATA06 0xb0b1
- MX6QDL_PAD_NANDF_D7__NAND_DATA07 0xb0b1
- MX6QDL_PAD_SD4_DAT0__NAND_DQS 0x00b1
- >;
- };
-
- pinctrl_i2c1: i2c1grp {
- fsl,pins = <
- MX6QDL_PAD_EIM_D21__I2C1_SCL 0x4001b8b1
- MX6QDL_PAD_EIM_D28__I2C1_SDA 0x4001b8b1
- >;
- };
-
- pinctrl_i2c2: i2c2grp {
- fsl,pins = <
- MX6QDL_PAD_EIM_EB2__I2C2_SCL 0x4001b8b1
- MX6QDL_PAD_EIM_D16__I2C2_SDA 0x4001b8b1
- >;
- };
-
- pinctrl_i2c3: i2c3grp {
- fsl,pins = <
- MX6QDL_PAD_EIM_D17__I2C3_SCL 0x4001b8b1
- MX6QDL_PAD_EIM_D18__I2C3_SDA 0x4001b8b1
- >;
- };
-
- pinctrl_leds: ledsgrp {
- fsl,pins = <
- MX6QDL_PAD_ENET_TXD0__GPIO1_IO30 0x80000000 /* Green LED */
- MX6QDL_PAD_EIM_EB3__GPIO2_IO31 0x80000000 /* Red LED */
- >;
- };
-
- pinctrl_pcie: pciegrp {
- fsl,pins = <MX6QDL_PAD_DI0_PIN15__GPIO4_IO17 0x80000000>;
- };
-
- pinctrl_pmic: pmicgrp {
- fsl,pins = <MX6QDL_PAD_SD4_DAT1__GPIO2_IO09 0x80000000>; /* PMIC interrupt */
- };
-
- pinctrl_uart3: uart3grp {
- fsl,pins = <
- MX6QDL_PAD_EIM_D24__UART3_TX_DATA 0x1b0b1
- MX6QDL_PAD_EIM_D25__UART3_RX_DATA 0x1b0b1
- MX6QDL_PAD_EIM_D31__UART3_RTS_B 0x1b0b1
- MX6QDL_PAD_EIM_D30__UART3_CTS_B 0x1b0b1
- >;
- };
-
- pinctrl_uart4: uart4grp {
- fsl,pins = <
- MX6QDL_PAD_KEY_COL0__UART4_TX_DATA 0x1b0b1
- MX6QDL_PAD_KEY_ROW0__UART4_RX_DATA 0x1b0b1
- >;
- };
-
- pinctrl_usbh1_vbus: usbh1vbusgrp {
- fsl,pins = <
- MX6QDL_PAD_GPIO_0__GPIO1_IO00 0x1b0b0
- >;
- };
-
- pinctrl_usbotg: usbotggrp {
- fsl,pins = <
- MX6QDL_PAD_GPIO_1__USB_OTG_ID 0x17059
- MX6QDL_PAD_KEY_COL4__USB_OTG_OC 0x1b0b0
- MX6QDL_PAD_KEY_ROW4__GPIO4_IO15 0x80000000
- >;
- };
-
- pinctrl_usdhc2: usdhc2grp {
- fsl,pins = <
- MX6QDL_PAD_SD2_CMD__SD2_CMD 0x17059
- MX6QDL_PAD_SD2_CLK__SD2_CLK 0x10059
- MX6QDL_PAD_SD2_DAT0__SD2_DATA0 0x17059
- MX6QDL_PAD_SD2_DAT1__SD2_DATA1 0x17059
- MX6QDL_PAD_SD2_DAT2__SD2_DATA2 0x17059
- MX6QDL_PAD_SD2_DAT3__SD2_DATA3 0x17059
- >;
- };
-
- pinctrl_usdhc3: usdhc3grp {
- fsl,pins = <
- MX6QDL_PAD_SD3_CMD__SD3_CMD 0x17059
- MX6QDL_PAD_SD3_CLK__SD3_CLK 0x10059
- MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x17059
- MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x17059
- MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x17059
- MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x17059
- >;
- };
-
- pinctrl_usdhc3_cdwp: usdhc3cdwp {
- fsl,pins = <
- MX6QDL_PAD_ENET_RXD0__GPIO1_IO27 0x80000000
- MX6QDL_PAD_ENET_TXD1__GPIO1_IO29 0x80000000
- >;
- };
-
- pinctrl_audmux: audmuxgrp {
- fsl,pins = <
- MX6QDL_PAD_DISP0_DAT16__AUD5_TXC 0x130b0
- MX6QDL_PAD_DISP0_DAT17__AUD5_TXD 0x110b0
- MX6QDL_PAD_DISP0_DAT18__AUD5_TXFS 0x130b0
- MX6QDL_PAD_DISP0_DAT19__AUD5_RXD 0x130b0
- >;
- };
- };
-};
-
-&pcie {
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_pcie>;
- reset-gpio = <&gpio4 17 GPIO_ACTIVE_LOW>;
- status = "disabled";
-};
-
-®_arm {
- vin-supply = <&vddcore_reg>;
-};
-
-®_pu {
- vin-supply = <&vddsoc_reg>;
-};
-
-®_soc {
- vin-supply = <&vddsoc_reg>;
-};
-
-&uart3 {
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_uart3>;
- uart-has-rtscts;
- status = "disabled";
-};
-
-&uart4 {
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_uart4>;
- status = "disabled";
-};
-
-&usbh1 {
- vbus-supply = <®_usb_h1_vbus>;
- status = "disabled";
-};
-
-&usbotg {
- vbus-supply = <®_usb_otg_vbus>;
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_usbotg>;
- disable-over-current;
- status = "disabled";
-};
-
-&usdhc2 {
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_usdhc2>;
- cd-gpios = <&gpio1 4 GPIO_ACTIVE_LOW>;
- wp-gpios = <&gpio1 2 GPIO_ACTIVE_HIGH>;
- vmmc-supply = <&vdd_sd1_reg>;
- status = "disabled";
-};
-
-&usdhc3 {
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_usdhc3
- &pinctrl_usdhc3_cdwp>;
- cd-gpios = <&gpio1 27 GPIO_ACTIVE_LOW>;
- wp-gpios = <&gpio1 29 GPIO_ACTIVE_HIGH>;
- vmmc-supply = <&vdd_sd0_reg>;
- status = "disabled";
-};
-
-&wdog1 {
- /*
- * Rely on PMIC reboot handler. Internal i.MX6 watchdog, that is also
- * used for reboot, does not reset all external PMIC voltages on reset.
- */
- status = "disabled";
-};
diff --git a/arch/arm/dts/imxrt1050-evk.dts b/arch/arm/dts/imxrt1050-evk.dts
deleted file mode 100644
index 6a9c10d..0000000
--- a/arch/arm/dts/imxrt1050-evk.dts
+++ /dev/null
@@ -1,72 +0,0 @@
-// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
-/*
- * Copyright (C) 2019
- * Author(s): Giulio Benetti <giulio.benetti@benettiengineering.com>
- */
-
-/dts-v1/;
-#include "imxrt1050.dtsi"
-#include "imxrt1050-pinfunc.h"
-
-/ {
- model = "NXP IMXRT1050-evk board";
- compatible = "fsl,imxrt1050-evk", "fsl,imxrt1050";
-
- chosen {
- stdout-path = &lpuart1;
- };
-
- aliases {
- gpio0 = &gpio1;
- gpio1 = &gpio2;
- gpio2 = &gpio3;
- gpio3 = &gpio4;
- gpio4 = &gpio5;
- mmc0 = &usdhc1;
- serial0 = &lpuart1;
- };
-
- memory@80000000 {
- device_type = "memory";
- reg = <0x80000000 0x2000000>;
- };
-};
-
-&lpuart1 {
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_lpuart1>;
- status = "okay";
-};
-
-&iomuxc {
- pinctrl-names = "default";
- pinctrl_lpuart1: lpuart1grp {
- fsl,pins = <
- MXRT1050_IOMUXC_GPIO_AD_B0_12_LPUART1_TXD 0xf1
- MXRT1050_IOMUXC_GPIO_AD_B0_13_LPUART1_RXD 0xf1
- >;
- };
-
- pinctrl_usdhc0: usdhc0grp {
- fsl,pins = <
- MXRT1050_IOMUXC_GPIO_B1_12_USDHC1_CD_B 0x1B000
- MXRT1050_IOMUXC_GPIO_B1_14_USDHC1_VSELECT 0xB069
- MXRT1050_IOMUXC_GPIO_SD_B0_00_USDHC1_CMD 0x17061
- MXRT1050_IOMUXC_GPIO_SD_B0_01_USDHC1_CLK 0x17061
- MXRT1050_IOMUXC_GPIO_SD_B0_05_USDHC1_DATA3 0x17061
- MXRT1050_IOMUXC_GPIO_SD_B0_04_USDHC1_DATA2 0x17061
- MXRT1050_IOMUXC_GPIO_SD_B0_03_USDHC1_DATA1 0x17061
- MXRT1050_IOMUXC_GPIO_SD_B0_02_USDHC1_DATA0 0x17061
- >;
- };
-};
-
-&usdhc1 {
- pinctrl-names = "default", "state_100mhz", "state_200mhz", "sleep";
- pinctrl-0 = <&pinctrl_usdhc0>;
- pinctrl-1 = <&pinctrl_usdhc0>;
- pinctrl-2 = <&pinctrl_usdhc0>;
- pinctrl-3 = <&pinctrl_usdhc0>;
- cd-gpios = <&gpio2 28 GPIO_ACTIVE_LOW>;
- status = "okay";
-};
diff --git a/arch/arm/dts/imxrt1050-pinfunc.h b/arch/arm/dts/imxrt1050-pinfunc.h
deleted file mode 100644
index 22c14a3..0000000
--- a/arch/arm/dts/imxrt1050-pinfunc.h
+++ /dev/null
@@ -1,993 +0,0 @@
-/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */
-/*
- * Copyright (C) 2019
- * Author(s): Giulio Benetti <giulio.benetti@benettiengineering.com>
- */
-
-#ifndef _DT_BINDINGS_PINCTRL_IMXRT1050_PINFUNC_H
-#define _DT_BINDINGS_PINCTRL_IMXRT1050_PINFUNC_H
-
-#define IMX_PAD_SION 0x40000000
-
-/*
- * The pin function ID is a tuple of
- * <mux_reg conf_reg input_reg mux_mode input_val>
- */
-
-#define MXRT1050_IOMUXC_GPIO_EMC_00_SEMC_DA00 0x014 0x204 0x000 0x0 0x0
-#define MXRT1050_IOMUXC_GPIO_EMC_00_FLEXPWM4_PWM0_A 0x014 0x204 0x494 0x1 0x0
-#define MXRT1050_IOMUXC_GPIO_EMC_00_LPSPI2_SCK 0x014 0x204 0x500 0x2 0x1
-#define MXRT1050_IOMUXC_GPIO_EMC_00_XBAR_INOUT2 0x014 0x204 0x60C 0x3 0x0
-#define MXRT1050_IOMUXC_GPIO_EMC_00_FLEXIO1_D00 0x014 0x204 0x000 0x4 0x0
-#define MXRT1050_IOMUXC_GPIO_EMC_00_GPIO4_IO00 0x014 0x204 0x000 0x5 0x0
-
-#define MXRT1050_IOMUXC_GPIO_EMC_01_SEMC_DA01 0x018 0x208 0x000 0x0 0x0
-#define MXRT1050_IOMUXC_GPIO_EMC_01_FLEXPWM4_PWM0_B 0x018 0x208 0x000 0x1 0x0
-#define MXRT1050_IOMUXC_GPIO_EMC_01_LPSPI2_PCS0 0x018 0x208 0x4FC 0x2 0x1
-#define MXRT1050_IOMUXC_GPIO_EMC_01_XBAR_INOUT3 0x018 0x208 0x610 0x3 0x0
-#define MXRT1050_IOMUXC_GPIO_EMC_01_FLEXIO1_D01 0x018 0x208 0x000 0x4 0x0
-#define MXRT1050_IOMUXC_GPIO_EMC_01_GPIO4_IO01 0x018 0x208 0x000 0x5 0x0
-
-#define MXRT1050_IOMUXC_GPIO_EMC_02_SEMC_DA02 0x01C 0x20C 0x000 0x0 0x0
-#define MXRT1050_IOMUXC_GPIO_EMC_02_FLEXPWM4_PWM1_A 0x01C 0x20C 0x498 0x1 0x0
-#define MXRT1050_IOMUXC_GPIO_EMC_02_LPSPI2_SDO 0x01C 0x20C 0x508 0x2 0x1
-#define MXRT1050_IOMUXC_GPIO_EMC_02_XBAR_INOUT4 0x01C 0x20C 0x614 0x3 0x0
-#define MXRT1050_IOMUXC_GPIO_EMC_02_FLEXIO1_D02 0x01C 0x20C 0x000 0x4 0x0
-#define MXRT1050_IOMUXC_GPIO_EMC_02_GPIO4_IO02 0x01C 0x20C 0x000 0x5 0x0
-
-#define MXRT1050_IOMUXC_GPIO_EMC_03_SEMC_DA03 0x020 0x210 0x000 0x0 0x0
-#define MXRT1050_IOMUXC_GPIO_EMC_03_FLEXPWM4_PWM1_B 0x020 0x210 0x000 0x1 0x0
-#define MXRT1050_IOMUXC_GPIO_EMC_03_LPSPI2_SDI 0x020 0x210 0x504 0x2 0x1
-#define MXRT1050_IOMUXC_GPIO_EMC_03_XBAR_INOUT5 0x020 0x210 0x618 0x3 0x0
-#define MXRT1050_IOMUXC_GPIO_EMC_03_FLEXIO1_D03 0x020 0x210 0x000 0x4 0x0
-#define MXRT1050_IOMUXC_GPIO_EMC_03_GPIO4_IO03 0x020 0x210 0x000 0x5 0x0
-
-#define MXRT1050_IOMUXC_GPIO_EMC_04_SEMC_DA04 0x024 0x214 0x000 0x0 0x0
-#define MXRT1050_IOMUXC_GPIO_EMC_04_FLEXPWM4_PWM2_A 0x024 0x214 0x49C 0x1 0x0
-#define MXRT1050_IOMUXC_GPIO_EMC_04_SAI2_TX_DATA 0x024 0x214 0x000 0x2 0x0
-#define MXRT1050_IOMUXC_GPIO_EMC_04_XBAR_INOUT6 0x024 0x214 0x61C 0x3 0x0
-#define MXRT1050_IOMUXC_GPIO_EMC_04_FLEXIO1_D04 0x024 0x214 0x000 0x4 0x0
-#define MXRT1050_IOMUXC_GPIO_EMC_04_GPIO4_IO04 0x024 0x214 0x000 0x5 0x0
-
-#define MXRT1050_IOMUXC_GPIO_EMC_05_SEMC_DA05 0x028 0x218 0x000 0x0 0x0
-#define MXRT1050_IOMUXC_GPIO_EMC_05_FLEXPWM4_PWM2_B 0x028 0x218 0x000 0x1 0x0
-#define MXRT1050_IOMUXC_GPIO_EMC_05_SAI2_TX_SYNC 0x028 0x218 0x5C4 0x2 0x0
-#define MXRT1050_IOMUXC_GPIO_EMC_05_XBAR_INOUT7 0x028 0x218 0x620 0x3 0x0
-#define MXRT1050_IOMUXC_GPIO_EMC_05_FLEXIO1_D05 0x028 0x218 0x000 0x4 0x0
-#define MXRT1050_IOMUXC_GPIO_EMC_05_GPIO4_IO05 0x028 0x218 0x000 0x5 0x0
-
-#define MXRT1050_IOMUXC_GPIO_EMC_06_SEMC_DA06 0x02C 0x21C 0x000 0x0 0x0
-#define MXRT1050_IOMUXC_GPIO_EMC_06_FLEXPWM2_PWM0_A 0x02C 0x21C 0x478 0x1 0x0
-#define MXRT1050_IOMUXC_GPIO_EMC_06_SAI2_TX_BCLK 0x02C 0x21C 0x5C0 0x2 0x0
-#define MXRT1050_IOMUXC_GPIO_EMC_06_XBAR_INOUT8 0x02C 0x21C 0x624 0x3 0x0
-#define MXRT1050_IOMUXC_GPIO_EMC_06_FLEXIO1_D06 0x02C 0x21C 0x000 0x4 0x0
-#define MXRT1050_IOMUXC_GPIO_EMC_06_GPIO4_IO06 0x02C 0x21C 0x000 0x5 0x0
-
-#define MXRT1050_IOMUXC_GPIO_EMC_07_SEMC_DA07 0x030 0x220 0x000 0x0 0x0
-#define MXRT1050_IOMUXC_GPIO_EMC_07_FLEXPWM2_PWM0_B 0x030 0x220 0x488 0x1 0x0
-#define MXRT1050_IOMUXC_GPIO_EMC_07_SAI2_MCLK 0x030 0x220 0x5B0 0x2 0x0
-#define MXRT1050_IOMUXC_GPIO_EMC_07_XBAR_INOUT9 0x030 0x220 0x628 0x3 0x0
-#define MXRT1050_IOMUXC_GPIO_EMC_07_FLEXIO1_D07 0x030 0x220 0x000 0x4 0x0
-#define MXRT1050_IOMUXC_GPIO_EMC_07_GPIO4_IO07 0x030 0x220 0x000 0x5 0x0
-
-#define MXRT1050_IOMUXC_GPIO_EMC_08_SEMC_DM00 0x034 0x224 0x000 0x0 0x0
-#define MXRT1050_IOMUXC_GPIO_EMC_08_FLEXPWM2_PWM1_A 0x034 0x224 0x47C 0x1 0x0
-#define MXRT1050_IOMUXC_GPIO_EMC_08_SAI2_RX_DATA 0x034 0x224 0x5B8 0x2 0x0
-#define MXRT1050_IOMUXC_GPIO_EMC_08_XBAR_INOUT17 0x034 0x224 0x62C 0x3 0x0
-#define MXRT1050_IOMUXC_GPIO_EMC_08_FLEXIO1_D08 0x034 0x224 0x000 0x4 0x0
-#define MXRT1050_IOMUXC_GPIO_EMC_08_GPIO4_IO08 0x034 0x224 0x000 0x5 0x0
-
-#define MXRT1050_IOMUXC_GPIO_EMC_09_SEMC_ADDR00 0x038 0x228 0x000 0x0 0x0
-#define MXRT1050_IOMUXC_GPIO_EMC_09_FLEXPWM2_PWM1_B 0x038 0x228 0x48C 0x1 0x0
-#define MXRT1050_IOMUXC_GPIO_EMC_09_SAI2_RX_SYNC 0x038 0x228 0x5BC 0x2 0x0
-#define MXRT1050_IOMUXC_GPIO_EMC_09_FLEXCAN2_TX 0x038 0x228 0x000 0x3 0x0
-#define MXRT1050_IOMUXC_GPIO_EMC_09_FLEXIO1_D09 0x038 0x228 0x000 0x4 0x0
-#define MXRT1050_IOMUXC_GPIO_EMC_09_GPIO4_IO09 0x038 0x228 0x000 0x5 0x0
-
-#define MXRT1050_IOMUXC_GPIO_EMC_10_SEMC_ADDR01 0x03C 0x22C 0x000 0x0 0x0
-#define MXRT1050_IOMUXC_GPIO_EMC_10_FLEXPWM2_PWM2_A 0x03C 0x22C 0x480 0x1 0x0
-#define MXRT1050_IOMUXC_GPIO_EMC_10_SAI2_RX_BCLK 0x03C 0x22C 0x5B4 0x2 0x0
-#define MXRT1050_IOMUXC_GPIO_EMC_10_FLEXCAN2_RX 0x03C 0x22C 0x450 0x3 0x0
-#define MXRT1050_IOMUXC_GPIO_EMC_10_FLEXIO1_D10 0x03C 0x22C 0x000 0x4 0x0
-#define MXRT1050_IOMUXC_GPIO_EMC_10_GPIO4_IO10 0x03C 0x22C 0x000 0x5 0x0
-
-#define MXRT1050_IOMUXC_GPIO_EMC_11_SEMC_ADDR02 0x040 0x230 0x000 0x0 0x0
-#define MXRT1050_IOMUXC_GPIO_EMC_11_FLEXPWM2_PWM2_B 0x040 0x230 0x490 0x1 0x0
-#define MXRT1050_IOMUXC_GPIO_EMC_11_LPI2C4_SDA 0x040 0x230 0x4E8 0x2 0x0
-#define MXRT1050_IOMUXC_GPIO_EMC_11_USDHC2_RESET_B 0x040 0x230 0x000 0x3 0x0
-#define MXRT1050_IOMUXC_GPIO_EMC_11_FLEXIO1_D11 0x040 0x230 0x000 0x4 0x0
-#define MXRT1050_IOMUXC_GPIO_EMC_11_GPIO4_IO11 0x040 0x230 0x000 0x5 0x0
-
-#define MXRT1050_IOMUXC_GPIO_EMC_12_SEMC_ADDR03 0x044 0x234 0x000 0x0 0x0
-#define MXRT1050_IOMUXC_GPIO_EMC_12_XBAR_INOUT24 0x044 0x234 0x640 0x1 0x0
-#define MXRT1050_IOMUXC_GPIO_EMC_12_LPI2C4_SCL 0x044 0x234 0x4E4 0x2 0x0
-#define MXRT1050_IOMUXC_GPIO_EMC_12_USDHC2_WP 0x044 0x234 0x5D8 0x3 0x0
-#define MXRT1050_IOMUXC_GPIO_EMC_12_FLEXPWM1_PWM3_A 0x044 0x234 0x454 0x4 0x1
-#define MXRT1050_IOMUXC_GPIO_EMC_12_GPIO4_IO12 0x044 0x234 0x000 0x5 0x0
-
-#define MXRT1050_IOMUXC_GPIO_EMC_13_SEMC_ADDR04 0x048 0x238 0x000 0x0 0x0
-#define MXRT1050_IOMUXC_GPIO_EMC_13_XBAR_INOUT25 0x048 0x238 0x650 0x1 0x1
-#define MXRT1050_IOMUXC_GPIO_EMC_13_LPUART3_TXD 0x048 0x238 0x53C 0x2 0x0
-#define MXRT1050_IOMUXC_GPIO_EMC_13_MQS_RIGHT 0x048 0x238 0x000 0x3 0x0
-#define MXRT1050_IOMUXC_GPIO_EMC_13_FLEXPWM1_PWM3_B 0x048 0x238 0x464 0x4 0x1
-#define MXRT1050_IOMUXC_GPIO_EMC_13_GPIO4_IO13 0x048 0x238 0x000 0x5 0x0
-
-#define MXRT1050_IOMUXC_GPIO_EMC_14_SEMC_ADDR05 0x04C 0x23C 0x000 0x0 0x0
-#define MXRT1050_IOMUXC_GPIO_EMC_14_XBAR_INOUT19 0x04C 0x23C 0x654 0x1 0x0
-#define MXRT1050_IOMUXC_GPIO_EMC_14_LPUART3_RXD 0x04C 0x23C 0x538 0x2 0x0
-#define MXRT1050_IOMUXC_GPIO_EMC_14_MQS_LEFT 0x04C 0x23C 0x000 0x3 0x0
-#define MXRT1050_IOMUXC_GPIO_EMC_14_LPSPI2_PCS1 0x04C 0x23C 0x000 0x4 0x0
-#define MXRT1050_IOMUXC_GPIO_EMC_14_GPIO4_IO14 0x04C 0x23C 0x000 0x5 0x0
-
-#define MXRT1050_IOMUXC_GPIO_EMC_15_SEMC_ADDR06 0x050 0x240 0x000 0x0 0x0
-#define MXRT1050_IOMUXC_GPIO_EMC_15_XBAR_INOUT20 0x050 0x240 0x634 0x1 0x0
-#define MXRT1050_IOMUXC_GPIO_EMC_15_LPUART3_CTS_B 0x050 0x240 0x534 0x2 0x0
-#define MXRT1050_IOMUXC_GPIO_EMC_15_SPDIF_OUT 0x050 0x240 0x000 0x3 0x0
-#define MXRT1050_IOMUXC_GPIO_EMC_15_TMR3_TIMER0 0x050 0x240 0x57C 0x4 0x0
-#define MXRT1050_IOMUXC_GPIO_EMC_15_GPIO4_IO15 0x050 0x240 0x000 0x5 0x0
-
-#define MXRT1050_IOMUXC_GPIO_EMC_16_SEMC_ADDR07 0x054 0x244 0x000 0x0 0x0
-#define MXRT1050_IOMUXC_GPIO_EMC_16_XBAR_INOUT21 0x054 0x244 0x658 0x1 0x0
-#define MXRT1050_IOMUXC_GPIO_EMC_16_LPUART3_RTS_B 0x054 0x244 0x000 0x2 0x0
-#define MXRT1050_IOMUXC_GPIO_EMC_16_SPDIF_IN 0x054 0x244 0x5C8 0x3 0x1
-#define MXRT1050_IOMUXC_GPIO_EMC_16_TMR3_TIMER1 0x054 0x244 0x580 0x4 0x0
-#define MXRT1050_IOMUXC_GPIO_EMC_16_GPIO4_IO16 0x054 0x244 0x000 0x5 0x0
-
-#define MXRT1050_IOMUXC_GPIO_EMC_17_SEMC_ADDR08 0x058 0x248 0x000 0x0 0x0
-#define MXRT1050_IOMUXC_GPIO_EMC_17_FLEXPWM4_PWM3_A 0x058 0x248 0x4A0 0x1 0x0
-#define MXRT1050_IOMUXC_GPIO_EMC_17_LPUART4_CTS_B 0x058 0x248 0x000 0x2 0x0
-#define MXRT1050_IOMUXC_GPIO_EMC_17_FLEXCAN1_TX 0x058 0x248 0x000 0x3 0x0
-#define MXRT1050_IOMUXC_GPIO_EMC_17_TMR3_TIMER2 0x058 0x248 0x584 0x4 0x0
-#define MXRT1050_IOMUXC_GPIO_EMC_17_GPIO4_IO17 0x058 0x248 0x000 0x5 0x0
-
-#define MXRT1050_IOMUXC_GPIO_EMC_18_SEMC_ADDR09 0x05C 0x24C 0x000 0x0 0x0
-#define MXRT1050_IOMUXC_GPIO_EMC_18_FLEXPWM4_PWM3_B 0x05C 0x24C 0x000 0x1 0x0
-#define MXRT1050_IOMUXC_GPIO_EMC_18_LPUART4_RTS_B 0x05C 0x24C 0x000 0x2 0x0
-#define MXRT1050_IOMUXC_GPIO_EMC_18_FLEXCAN1_RX 0x05C 0x24C 0x44C 0x3 0x1
-#define MXRT1050_IOMUXC_GPIO_EMC_18_TMR3_TIMER3 0x05C 0x24C 0x588 0x4 0x0
-#define MXRT1050_IOMUXC_GPIO_EMC_18_GPIO4_IO18 0x05C 0x24C 0x000 0x5 0x0
-#define MXRT1050_IOMUXC_GPIO_EMC_18_SNVS_VIO_5_CTL 0x05C 0x24C 0x000 0x6 0x0
-
-#define MXRT1050_IOMUXC_GPIO_EMC_19_SEMC_ADDR11 0x060 0x250 0x000 0x0 0x0
-#define MXRT1050_IOMUXC_GPIO_EMC_19_FLEXPWM2_PWM3_A 0x060 0x250 0x000 0x1 0x0
-#define MXRT1050_IOMUXC_GPIO_EMC_19_LPUART4_TXD 0x060 0x250 0x544 0x2 0x1
-#define MXRT1050_IOMUXC_GPIO_EMC_19_ENET_RX_DATA01 0x060 0x250 0x438 0x3 0x0
-#define MXRT1050_IOMUXC_GPIO_EMC_19_TMR2_TIMER0 0x060 0x250 0x56C 0x4 0x0
-#define MXRT1050_IOMUXC_GPIO_EMC_19_GPIO4_IO19 0x060 0x250 0x000 0x5 0x0
-#define MXRT1050_IOMUXC_GPIO_EMC_19_SNVS_VIO_5 0x060 0x250 0x000 0x6 0x0
-
-#define MXRT1050_IOMUXC_GPIO_EMC_20_SEMC_ADDR12 0x064 0x254 0x000 0x0 0x0
-#define MXRT1050_IOMUXC_GPIO_EMC_20_FLEXPWM2_PWM3_B 0x064 0x254 0x484 0x1 0x1
-#define MXRT1050_IOMUXC_GPIO_EMC_20_LPUART4_RXD 0x064 0x254 0x540 0x2 0x1
-#define MXRT1050_IOMUXC_GPIO_EMC_20_ENET_RX_DATA00 0x064 0x254 0x434 0x3 0x0
-#define MXRT1050_IOMUXC_GPIO_EMC_20_TMR2_TIMER0 0x064 0x254 0x570 0x4 0x0
-#define MXRT1050_IOMUXC_GPIO_EMC_20_GPIO4_IO20 0x064 0x254 0x000 0x5 0x0
-
-#define MXRT1050_IOMUXC_GPIO_EMC_21_SEMC_BA0 0x068 0x258 0x000 0x0 0x0
-#define MXRT1050_IOMUXC_GPIO_EMC_21_FLEXPWM3_PWM3_A 0x068 0x258 0x000 0x1 0x0
-#define MXRT1050_IOMUXC_GPIO_EMC_21_LPI2C3_SDA 0x068 0x258 0x4E0 0x2 0x0
-#define MXRT1050_IOMUXC_GPIO_EMC_21_ENET_TX_DATA01 0x068 0x258 0x000 0x3 0x0
-#define MXRT1050_IOMUXC_GPIO_EMC_21_TMR2_TIMER2 0x068 0x258 0x574 0x4 0x0
-#define MXRT1050_IOMUXC_GPIO_EMC_21_GPIO4_IO21 0x068 0x258 0x000 0x5 0x0
-
-#define MXRT1050_IOMUXC_GPIO_EMC_22_SEMC_BA1 0x06C 0x25C 0x000 0x0 0x0
-#define MXRT1050_IOMUXC_GPIO_EMC_22_FLEXPWM3_PWM3_B 0x06C 0x25C 0x000 0x1 0x0
-#define MXRT1050_IOMUXC_GPIO_EMC_22_LPI2C3_SCL 0x06C 0x25C 0x4DC 0x2 0x0
-#define MXRT1050_IOMUXC_GPIO_EMC_22_ENET_TX_DATA00 0x06C 0x25C 0x000 0x3 0x0
-#define MXRT1050_IOMUXC_GPIO_EMC_22_TMR2_TIMER3 0x06C 0x25C 0x578 0x4 0x0
-#define MXRT1050_IOMUXC_GPIO_EMC_22_GPIO4_IO22 0x06C 0x25C 0x000 0x5 0x0
-
-#define MXRT1050_IOMUXC_GPIO_EMC_23_SEMC_ADDR10 0x070 0x260 0x000 0x0 0x0
-#define MXRT1050_IOMUXC_GPIO_EMC_23_FLEXPWM1_PWM0_A 0x070 0x260 0x458 0x1 0x0
-#define MXRT1050_IOMUXC_GPIO_EMC_23_LPUART5_TXD 0x070 0x260 0x54C 0x2 0x0
-#define MXRT1050_IOMUXC_GPIO_EMC_23_ENET_RX_EN 0x070 0x260 0x43C 0x3 0x0
-#define MXRT1050_IOMUXC_GPIO_EMC_23_GPT1_CAPTURE2 0x070 0x260 0x000 0x4 0x0
-#define MXRT1050_IOMUXC_GPIO_EMC_23_GPIO4_IO23 0x070 0x260 0x000 0x5 0x0
-
-#define MXRT1050_IOMUXC_GPIO_EMC_24_SEMC_CAS 0x074 0x264 0x000 0x0 0x0
-#define MXRT1050_IOMUXC_GPIO_EMC_24_FLEXPWM1_PWM0_B 0x074 0x264 0x000 0x1 0x0
-#define MXRT1050_IOMUXC_GPIO_EMC_24_LPUART5_RXD 0x074 0x264 0x548 0x2 0x0
-#define MXRT1050_IOMUXC_GPIO_EMC_24_ENET_TX_EN 0x074 0x264 0x000 0x3 0x0
-#define MXRT1050_IOMUXC_GPIO_EMC_24_GPT1_CAPTURE1 0x074 0x264 0x000 0x4 0x0
-#define MXRT1050_IOMUXC_GPIO_EMC_24_GPIO4_IO24 0x074 0x264 0x000 0x5 0x0
-
-#define MXRT1050_IOMUXC_GPIO_EMC_25_SEMC_RAS 0x078 0x268 0x000 0x0 0x0
-#define MXRT1050_IOMUXC_GPIO_EMC_25_FLEXPWM1_PWM1_A 0x078 0x268 0x45C 0x1 0x0
-#define MXRT1050_IOMUXC_GPIO_EMC_25_LPUART6_TXD 0x078 0x268 0x554 0x2 0x0
-#define MXRT1050_IOMUXC_GPIO_EMC_25_ENET_TX_CLK 0x078 0x268 0x448 0x3 0x0
-#define MXRT1050_IOMUXC_GPIO_EMC_25_ENET_REF_CLK 0x078 0x268 0x42C 0x4 0x0
-#define MXRT1050_IOMUXC_GPIO_EMC_25_GPIO4_IO25 0x078 0x268 0x000 0x5 0x0
-
-#define MXRT1050_IOMUXC_GPIO_EMC_26_SEMC_CLK 0x07C 0x26C 0x000 0x0 0x0
-#define MXRT1050_IOMUXC_GPIO_EMC_26_FLEXPWM1_PWM1_B 0x07C 0x26C 0x46C 0x1 0x0
-#define MXRT1050_IOMUXC_GPIO_EMC_26_LPUART6_RXD 0x07C 0x26C 0x550 0x2 0x0
-#define MXRT1050_IOMUXC_GPIO_EMC_26_ENET_RX_ER 0x07C 0x26C 0x440 0x3 0x0
-#define MXRT1050_IOMUXC_GPIO_EMC_26_FLEXIO1_D12 0x07C 0x26C 0x000 0x4 0x0
-#define MXRT1050_IOMUXC_GPIO_EMC_26_GPIO4_IO26 0x07C 0x26C 0x000 0x5 0x0
-
-#define MXRT1050_IOMUXC_GPIO_EMC_27_SEMC_CKE 0x080 0x270 0x000 0x0 0x0
-#define MXRT1050_IOMUXC_GPIO_EMC_27_FLEXPWM1_PWM2_A 0x080 0x270 0x460 0x1 0x0
-#define MXRT1050_IOMUXC_GPIO_EMC_27_LPUART5_RTS_B 0x080 0x270 0x000 0x2 0x0
-#define MXRT1050_IOMUXC_GPIO_EMC_27_LPSPI1_SCK 0x080 0x270 0x4F0 0x3 0x0
-#define MXRT1050_IOMUXC_GPIO_EMC_27_FLEXIO1_D13 0x080 0x270 0x000 0x4 0x0
-#define MXRT1050_IOMUXC_GPIO_EMC_27_GPIO4_IO27 0x080 0x270 0x000 0x5 0x0
-
-#define MXRT1050_IOMUXC_GPIO_EMC_28_SEMC_WE 0x084 0x274 0x000 0x0 0x0
-#define MXRT1050_IOMUXC_GPIO_EMC_28_FLEXPWM1_PWM2_B 0x084 0x274 0x470 0x1 0x0
-#define MXRT1050_IOMUXC_GPIO_EMC_28_LPUART5_CTS_B 0x084 0x274 0x000 0x2 0x0
-#define MXRT1050_IOMUXC_GPIO_EMC_28_LPSPI1_SDO 0x084 0x274 0x4F8 0x3 0x0
-#define MXRT1050_IOMUXC_GPIO_EMC_28_FLEXIO1_D14 0x084 0x274 0x000 0x4 0x0
-#define MXRT1050_IOMUXC_GPIO_EMC_28_GPIO4_IO28 0x084 0x274 0x000 0x5 0x0
-
-#define MXRT1050_IOMUXC_GPIO_EMC_29_SEMC_CS0 0x088 0x278 0x000 0x0 0x0
-#define MXRT1050_IOMUXC_GPIO_EMC_29_FLEXPWM3_PWM0_A 0x088 0x278 0x000 0x1 0x0
-#define MXRT1050_IOMUXC_GPIO_EMC_29_LPUART6_RTS_B 0x088 0x278 0x000 0x2 0x0
-#define MXRT1050_IOMUXC_GPIO_EMC_29_LPSPI1_SDI 0x088 0x278 0x4F4 0x3 0x0
-#define MXRT1050_IOMUXC_GPIO_EMC_29_FLEXIO1_D15 0x088 0x278 0x000 0x4 0x0
-#define MXRT1050_IOMUXC_GPIO_EMC_29_GPIO4_IO29 0x088 0x278 0x000 0x5 0x0
-
-#define MXRT1050_IOMUXC_GPIO_EMC_30_SEMC_DA08 0x08C 0x27C 0x000 0x0 0x0
-#define MXRT1050_IOMUXC_GPIO_EMC_30_FLEXPWM3_PWM0_B 0x08C 0x27C 0x000 0x1 0x0
-#define MXRT1050_IOMUXC_GPIO_EMC_30_LPUART6_CTS_B 0x08C 0x27C 0x000 0x2 0x0
-#define MXRT1050_IOMUXC_GPIO_EMC_30_LPSPI1_PCS0 0x08C 0x27C 0x4EC 0x3 0x1
-#define MXRT1050_IOMUXC_GPIO_EMC_30_CSI_DATA23 0x08C 0x27C 0x000 0x4 0x0
-#define MXRT1050_IOMUXC_GPIO_EMC_30_GPIO4_IO30 0x08C 0x27C 0x000 0x5 0x0
-
-#define MXRT1050_IOMUXC_GPIO_EMC_31_SEMC_DA09 0x090 0x280 0x000 0x0 0x0
-#define MXRT1050_IOMUXC_GPIO_EMC_31_FLEXPWM3_PWM1_A 0x090 0x280 0x000 0x1 0x0
-#define MXRT1050_IOMUXC_GPIO_EMC_31_LPUART7_TXD 0x090 0x280 0x55C 0x2 0x1
-#define MXRT1050_IOMUXC_GPIO_EMC_31_LPSPI1_PCS1 0x090 0x280 0x000 0x3 0x0
-#define MXRT1050_IOMUXC_GPIO_EMC_31_CSI_DATA22 0x090 0x280 0x000 0x4 0x0
-#define MXRT1050_IOMUXC_GPIO_EMC_31_GPIO4_IO31 0x090 0x280 0x000 0x5 0x0
-
-#define MXRT1050_IOMUXC_GPIO_EMC_32_SEMC_DA10 0x094 0x284 0x000 0x0 0x0
-#define MXRT1050_IOMUXC_GPIO_EMC_32_FLEXPWM3_PWM1_B 0x094 0x284 0x000 0x1 0x0
-#define MXRT1050_IOMUXC_GPIO_EMC_32_LPUART7_RXD 0x094 0x284 0x558 0x2 0x1
-#define MXRT1050_IOMUXC_GPIO_EMC_32_CCM_PMIC_READY 0x094 0x284 0x3FC 0x3 0x4
-#define MXRT1050_IOMUXC_GPIO_EMC_32_CSI_DATA21 0x094 0x284 0x000 0x4 0x0
-#define MXRT1050_IOMUXC_GPIO_EMC_32_GPIO3_IO18 0x094 0x284 0x000 0x5 0x0
-
-#define MXRT1050_IOMUXC_GPIO_EMC_33_SEMC_DA11 0x098 0x288 0x000 0x0 0x0
-#define MXRT1050_IOMUXC_GPIO_EMC_33_FLEXPWM3_PWM2_A 0x098 0x288 0x000 0x1 0x0
-#define MXRT1050_IOMUXC_GPIO_EMC_33_USDHC1_RESET_B 0x098 0x288 0x000 0x2 0x0
-#define MXRT1050_IOMUXC_GPIO_EMC_33_SAI3_RX_DATA 0x098 0x288 0x000 0x3 0x0
-#define MXRT1050_IOMUXC_GPIO_EMC_33_CSI_DATA20 0x098 0x288 0x000 0x4 0x0
-#define MXRT1050_IOMUXC_GPIO_EMC_33_GPIO3_IO19 0x098 0x288 0x000 0x5 0x0
-
-#define MXRT1050_IOMUXC_GPIO_EMC_34_SEMC_DA12 0x09C 0x28C 0x000 0x0 0x0
-#define MXRT1050_IOMUXC_GPIO_EMC_34_FLEXPWM3_PWM2_B 0x09C 0x28C 0x000 0x1 0x0
-#define MXRT1050_IOMUXC_GPIO_EMC_34_USDHC1_VSELECT 0x09C 0x28C 0x000 0x2 0x0
-#define MXRT1050_IOMUXC_GPIO_EMC_34_SAI3_RX_SYNC 0x09C 0x28C 0x000 0x3 0x0
-#define MXRT1050_IOMUXC_GPIO_EMC_34_CSI_DATA19 0x09C 0x28C 0x000 0x4 0x0
-#define MXRT1050_IOMUXC_GPIO_EMC_34_GPIO3_IO20 0x09C 0x28C 0x000 0x5 0x0
-
-#define MXRT1050_IOMUXC_GPIO_EMC_35_SEMC_DA13 0x0A0 0x290 0x000 0x0 0x0
-#define MXRT1050_IOMUXC_GPIO_EMC_35_XBAR_INOUT18 0x0A0 0x290 0x630 0x1 0x0
-#define MXRT1050_IOMUXC_GPIO_EMC_35_GPT1_COMPARE1 0x0A0 0x290 0x000 0x2 0x0
-#define MXRT1050_IOMUXC_GPIO_EMC_35_SAI3_RX_BCLK 0x0A0 0x290 0x000 0x3 0x0
-#define MXRT1050_IOMUXC_GPIO_EMC_35_CSI_DATA18 0x0A0 0x290 0x000 0x4 0x0
-#define MXRT1050_IOMUXC_GPIO_EMC_35_GPIO3_IO21 0x0A0 0x290 0x000 0x5 0x0
-#define MXRT1050_IOMUXC_GPIO_EMC_35_USDHC1_CD_B 0x0A0 0x290 0x5D4 0x6 0x0
-
-#define MXRT1050_IOMUXC_GPIO_EMC_36_SEMC_DA14 0x0A4 0x294 0x000 0x0 0x0
-#define MXRT1050_IOMUXC_GPIO_EMC_36_XBAR_INOUT22 0x0A4 0x294 0x638 0x1 0x0
-#define MXRT1050_IOMUXC_GPIO_EMC_36_GPT1_COMPARE2 0x0A4 0x294 0x000 0x2 0x0
-#define MXRT1050_IOMUXC_GPIO_EMC_36_SAI3_TX_DATA 0x0A4 0x294 0x000 0x3 0x0
-#define MXRT1050_IOMUXC_GPIO_EMC_36_CSI_DATA17 0x0A4 0x294 0x000 0x4 0x0
-#define MXRT1050_IOMUXC_GPIO_EMC_36_GPIO3_IO22 0x0A4 0x294 0x000 0x5 0x0
-#define MXRT1050_IOMUXC_GPIO_EMC_36_USDHC1_WP 0x0A4 0x294 0x5D8 0x6 0x1
-
-#define MXRT1050_IOMUXC_GPIO_EMC_37_SEMC_DA15 0x0A8 0x298 0x000 0x0 0x0
-#define MXRT1050_IOMUXC_GPIO_EMC_37_XBAR_INOUT23 0x0A8 0x298 0x63C 0x1 0x0
-#define MXRT1050_IOMUXC_GPIO_EMC_37_GPT1_COMPARE3 0x0A8 0x298 0x000 0x2 0x0
-#define MXRT1050_IOMUXC_GPIO_EMC_37_SAI3_MCLK 0x0A8 0x298 0x000 0x3 0x0
-#define MXRT1050_IOMUXC_GPIO_EMC_37_CSI_DATA16 0x0A8 0x298 0x000 0x4 0x0
-#define MXRT1050_IOMUXC_GPIO_EMC_37_GPIO3_IO23 0x0A8 0x298 0x000 0x5 0x0
-#define MXRT1050_IOMUXC_GPIO_EMC_37_USDHC2_WP 0x0A8 0x298 0x608 0x6 0x0
-
-#define MXRT1050_IOMUXC_GPIO_EMC_38_SEMC_DM01 0x0AC 0x29C 0x000 0x0 0x0
-#define MXRT1050_IOMUXC_GPIO_EMC_38_FLEXPWM1_PWM3_A 0x0AC 0x29C 0x454 0x1 0x2
-#define MXRT1050_IOMUXC_GPIO_EMC_38_LPUART8_TXD 0x0AC 0x29C 0x564 0x2 0x2
-#define MXRT1050_IOMUXC_GPIO_EMC_38_SAI3_TX_BCLK 0x0AC 0x29C 0x000 0x3 0x0
-#define MXRT1050_IOMUXC_GPIO_EMC_38_CSI_FIELD 0x0AC 0x29C 0x000 0x4 0x0
-#define MXRT1050_IOMUXC_GPIO_EMC_38_GPIO3_IO24 0x0AC 0x29C 0x000 0x5 0x0
-#define MXRT1050_IOMUXC_GPIO_EMC_38_USDHC2_VSELECT 0x0AC 0x29C 0x000 0x6 0x0
-
-#define MXRT1050_IOMUXC_GPIO_EMC_39_SEMC_DQS 0x0B0 0x2A0 0x000 0x0 0x0
-#define MXRT1050_IOMUXC_GPIO_EMC_39_FLEXPWM1_PWM3_B 0x0B0 0x2A0 0x464 0x1 0x2
-#define MXRT1050_IOMUXC_GPIO_EMC_39_LPUART8_RXD 0x0B0 0x2A0 0x560 0x2 0x2
-#define MXRT1050_IOMUXC_GPIO_EMC_39_SAI3_TX_SYNC 0x0B0 0x2A0 0x000 0x3 0x0
-#define MXRT1050_IOMUXC_GPIO_EMC_39_WDOG1_B 0x0B0 0x2A0 0x000 0x4 0x0
-#define MXRT1050_IOMUXC_GPIO_EMC_39_GPIO3_IO25 0x0B0 0x2A0 0x000 0x5 0x0
-#define MXRT1050_IOMUXC_GPIO_EMC_39_USDHC2_CD_B 0x0B0 0x2A0 0x5E0 0x6 0x1
-
-#define MXRT1050_IOMUXC_GPIO_EMC_40_SEMC_RDY 0x0B4 0x2A4 0x000 0x0 0x0
-#define MXRT1050_IOMUXC_GPIO_EMC_40_GPT2_CAPTURE2 0x0B4 0x2A4 0x000 0x1 0x0
-#define MXRT1050_IOMUXC_GPIO_EMC_40_LPSPI1_PCS2 0x0B4 0x2A4 0x000 0x2 0x0
-#define MXRT1050_IOMUXC_GPIO_EMC_40_USB_OTG2_OC 0x0B4 0x2A4 0x5CC 0x3 0x1
-#define MXRT1050_IOMUXC_GPIO_EMC_40_ENET_MDC 0x0B4 0x2A4 0x000 0x4 0x0
-#define MXRT1050_IOMUXC_GPIO_EMC_40_GPIO3_IO26 0x0B4 0x2A4 0x000 0x5 0x0
-#define MXRT1050_IOMUXC_GPIO_EMC_40_USDHC2_RESET_B 0x0B4 0x2A4 0x000 0x6 0x0
-
-#define MXRT1050_IOMUXC_GPIO_EMC_41_SEMC_CSX0 0x0B8 0x2A8 0x000 0x0 0x0
-#define MXRT1050_IOMUXC_GPIO_EMC_41_GPT2_CAPTURE1 0x0B8 0x2A8 0x000 0x1 0x0
-#define MXRT1050_IOMUXC_GPIO_EMC_41_LPSPI1_PCS3 0x0B8 0x2A8 0x000 0x2 0x0
-#define MXRT1050_IOMUXC_GPIO_EMC_41_USB_OTG2_PWR 0x0B8 0x2A8 0x000 0x3 0x0
-#define MXRT1050_IOMUXC_GPIO_EMC_41_ENET_MDIO 0x0B8 0x2A8 0x430 0x4 0x1
-#define MXRT1050_IOMUXC_GPIO_EMC_41_GPIO3_IO27 0x0B8 0x2A8 0x000 0x5 0x0
-#define MXRT1050_IOMUXC_GPIO_EMC_41_USDHC2_VSELECT 0x0B8 0x2A8 0x000 0x6 0x0
-
-#define MXRT1050_IOMUXC_GPIO_AD_B0_00_FLEXPWM2_PWM3_A 0x0BC 0x2AC 0x000 0x0 0x0
-#define MXRT1050_IOMUXC_GPIO_AD_B0_00_XBAR_INOUT14 0x0BC 0x2AC 0x644 0x1 0x0
-#define MXRT1050_IOMUXC_GPIO_AD_B0_00_REF_CLK_32K 0x0BC 0x2AC 0x000 0x2 0x0
-#define MXRT1050_IOMUXC_GPIO_AD_B0_00_USB_OTG2_ID 0x0BC 0x2AC 0x3F8 0x3 0x0
-#define MXRT1050_IOMUXC_GPIO_AD_B0_00_LPI2C1_SCLS 0x0BC 0x2AC 0x000 0x4 0x0
-#define MXRT1050_IOMUXC_GPIO_AD_B0_00_GPIO1_IO00 0x0BC 0x2AC 0x000 0x5 0x0
-#define MXRT1050_IOMUXC_GPIO_AD_B0_00_USDHC1_RESET_B 0x0BC 0x2AC 0x000 0x6 0x0
-#define MXRT1050_IOMUXC_GPIO_AD_B0_00_LPSPI3_SCK 0x0BC 0x2AC 0x510 0x7 0x0
-
-#define MXRT1050_IOMUXC_GPIO_AD_B0_01_FLEXPWM2_PWM3_B 0x0C0 0x2B0 0x484 0x0 0x2
-#define MXRT1050_IOMUXC_GPIO_AD_B0_01_XBAR_INOUT15 0x0C0 0x2B0 0x648 0x1 0x0
-#define MXRT1050_IOMUXC_GPIO_AD_B0_01_REF_CLK_24M 0x0C0 0x2B0 0x000 0x2 0x0
-#define MXRT1050_IOMUXC_GPIO_AD_B0_01_USB_OTG1_ID 0x0C0 0x2B0 0x3F4 0x3 0x0
-#define MXRT1050_IOMUXC_GPIO_AD_B0_01_LPI2C1_SDAS 0x0C0 0x2B0 0x000 0x4 0x0
-#define MXRT1050_IOMUXC_GPIO_AD_B0_01_GPIO1_IO01 0x0C0 0x2B0 0x000 0x5 0x0
-#define MXRT1050_IOMUXC_GPIO_AD_B0_01_EWM_OUT_B 0x0C0 0x2B0 0x000 0x6 0x0
-#define MXRT1050_IOMUXC_GPIO_AD_B0_01_LPSPI3_SDO 0x0C0 0x2B0 0x518 0x7 0x1
-
-#define MXRT1050_IOMUXC_GPIO_AD_B0_02_FLEXCAN2_TX 0x0C4 0x2B4 0x000 0x0 0x0
-#define MXRT1050_IOMUXC_GPIO_AD_B0_02_XBAR_INOUT16 0x0C4 0x2B4 0x64C 0x1 0x0
-#define MXRT1050_IOMUXC_GPIO_AD_B0_02_LPUART6_TXD 0x0C4 0x2B4 0x554 0x2 0x1
-#define MXRT1050_IOMUXC_GPIO_AD_B0_02_USB_OTG1_PWR 0x0C4 0x2B4 0x000 0x3 0x0
-#define MXRT1050_IOMUXC_GPIO_AD_B0_02_FLEXPWM1_PWM0_X 0x0C4 0x2B4 0x000 0x4 0x0
-#define MXRT1050_IOMUXC_GPIO_AD_B0_02_GPIO1_IO02 0x0C4 0x2B4 0x000 0x5 0x0
-#define MXRT1050_IOMUXC_GPIO_AD_B0_02_LPI2C1_HREQ 0x0C4 0x2B4 0x000 0x6 0x0
-#define MXRT1050_IOMUXC_GPIO_AD_B0_02_LPSPI3_SDI 0x0C4 0x2B4 0x514 0x7 0x1
-
-#define MXRT1050_IOMUXC_GPIO_AD_B0_03_FLEXCAN2_RX 0x0C8 0x2B8 0x450 0x0 0x1
-#define MXRT1050_IOMUXC_GPIO_AD_B0_03_XBAR_INOUT17 0x0C8 0x2B8 0x62C 0x1 0x1
-#define MXRT1050_IOMUXC_GPIO_AD_B0_03_LPUART6_RXD 0x0C8 0x2B8 0x550 0x2 0x1
-#define MXRT1050_IOMUXC_GPIO_AD_B0_03_USB_OTG1_OC 0x0C8 0x2B8 0x5D0 0x3 0x0
-#define MXRT1050_IOMUXC_GPIO_AD_B0_03_FLEXPWM1_PWM1_X 0x0C8 0x2B8 0x000 0x4 0x0
-#define MXRT1050_IOMUXC_GPIO_AD_B0_03_GPIO1_IO03 0x0C8 0x2B8 0x000 0x5 0x0
-#define MXRT1050_IOMUXC_GPIO_AD_B0_03_REF_CLK_24M 0x0C8 0x2B8 0x000 0x6 0x0
-#define MXRT1050_IOMUXC_GPIO_AD_B0_03_LPSPI3_PCS0 0x0C8 0x2B8 0x50C 0x7 0x0
-
-#define MXRT1050_IOMUXC_GPIO_AD_B0_04_SRC_BOOT_MODE00 0x0CC 0x2BC 0x000 0x0 0x0
-#define MXRT1050_IOMUXC_GPIO_AD_B0_04_MQS_RIGHT 0x0CC 0x2BC 0x000 0x1 0x0
-#define MXRT1050_IOMUXC_GPIO_AD_B0_04_ENET_TX_DATA03 0x0CC 0x2BC 0x000 0x2 0x0
-#define MXRT1050_IOMUXC_GPIO_AD_B0_04_SAI2_TX_SYNC 0x0CC 0x2BC 0x5C4 0x3 0x1
-#define MXRT1050_IOMUXC_GPIO_AD_B0_04_CSI_DATA09 0x0CC 0x2BC 0x41C 0x4 0x1
-#define MXRT1050_IOMUXC_GPIO_AD_B0_04_GPIO1_IO04 0x0CC 0x2BC 0x000 0x5 0x0
-#define MXRT1050_IOMUXC_GPIO_AD_B0_04_PIT_TRIGGER00 0x0CC 0x2BC 0x000 0x6 0x0
-#define MXRT1050_IOMUXC_GPIO_AD_B0_04_LPSPI3_PCS1 0x0CC 0x2BC 0x000 0x7 0x0
-
-#define MXRT1050_IOMUXC_GPIO_AD_B0_05_SRC_BOOT_MODE01 0x0D0 0x2C0 0x000 0x0 0x0
-#define MXRT1050_IOMUXC_GPIO_AD_B0_05_MQS_LEFT 0x0D0 0x2C0 0x000 0x1 0x0
-#define MXRT1050_IOMUXC_GPIO_AD_B0_05_ENET_TX_DATA02 0x0D0 0x2C0 0x000 0x2 0x0
-#define MXRT1050_IOMUXC_GPIO_AD_B0_05_SAI2_TX_BCLK 0x0D0 0x2C0 0x5C0 0x3 0x1
-#define MXRT1050_IOMUXC_GPIO_AD_B0_05_CSI_DATA08 0x0D0 0x2C0 0x418 0x4 0x1
-#define MXRT1050_IOMUXC_GPIO_AD_B0_05_GPIO1_IO05 0x0D0 0x2C0 0x000 0x5 0x0
-#define MXRT1050_IOMUXC_GPIO_AD_B0_05_XBAR_INOUT17 0x0D0 0x2C0 0x62C 0x6 0x2
-#define MXRT1050_IOMUXC_GPIO_AD_B0_05_LPSPI3_PCS2 0x0D0 0x2C0 0x000 0x7 0x0
-
-#define MXRT1050_IOMUXC_GPIO_AD_B0_06_JTAG_TMS 0x0D4 0x2C4 0x000 0x0 0x0
-#define MXRT1050_IOMUXC_GPIO_AD_B0_06_GPT2_COMPARE1 0x0D4 0x2C4 0x000 0x1 0x0
-#define MXRT1050_IOMUXC_GPIO_AD_B0_06_ENET_RX_CLK 0x0D4 0x2C4 0x000 0x2 0x0
-#define MXRT1050_IOMUXC_GPIO_AD_B0_06_SAI2_RX_BCLK 0x0D4 0x2C4 0x5B4 0x3 0x1
-#define MXRT1050_IOMUXC_GPIO_AD_B0_06_CSI_DATA07 0x0D4 0x2C4 0x414 0x4 0x1
-#define MXRT1050_IOMUXC_GPIO_AD_B0_06_GPIO1_IO06 0x0D4 0x2C4 0x000 0x5 0x0
-#define MXRT1050_IOMUXC_GPIO_AD_B0_06_XBAR_INOUT18 0x0D4 0x2C4 0x630 0x6 0x1
-#define MXRT1050_IOMUXC_GPIO_AD_B0_06_LPSPI3_PCS3 0x0D4 0x2C4 0x000 0x7 0x0
-
-#define MXRT1050_IOMUXC_GPIO_AD_B0_07_JTAG_TCK 0x0D8 0x2C8 0x000 0x0 0x0
-#define MXRT1050_IOMUXC_GPIO_AD_B0_07_GPT2_COMPARE2 0x0D8 0x2C8 0x000 0x1 0x0
-#define MXRT1050_IOMUXC_GPIO_AD_B0_07_ENET_TX_ER 0x0D8 0x2C8 0x000 0x2 0x0
-#define MXRT1050_IOMUXC_GPIO_AD_B0_07_SAI2_RX_SYNC 0x0D8 0x2C8 0x5BC 0x3 0x1
-#define MXRT1050_IOMUXC_GPIO_AD_B0_07_CSI_DATA06 0x0D8 0x2C8 0x410 0x4 0x1
-#define MXRT1050_IOMUXC_GPIO_AD_B0_07_GPIO1_IO07 0x0D8 0x2C8 0x000 0x5 0x0
-#define MXRT1050_IOMUXC_GPIO_AD_B0_07_XBAR_INOUT19 0x0D8 0x2C8 0x654 0x6 0x1
-#define MXRT1050_IOMUXC_GPIO_AD_B0_07_ENET_1588_EVENT3_OUT 0x0D8 0x2C8 0x000 0x7 0x0
-
-#define MXRT1050_IOMUXC_GPIO_AD_B0_08_JTAG_MOD 0x0DC 0x2CC 0x000 0x0 0x0
-#define MXRT1050_IOMUXC_GPIO_AD_B0_08_GPT2_COMPARE3 0x0DC 0x2CC 0x000 0x1 0x0
-#define MXRT1050_IOMUXC_GPIO_AD_B0_08_ENET_RX_DATA03 0x0DC 0x2CC 0x000 0x2 0x0
-#define MXRT1050_IOMUXC_GPIO_AD_B0_08_SAI2_RX_DATA 0x0DC 0x2CC 0x5B8 0x3 0x1
-#define MXRT1050_IOMUXC_GPIO_AD_B0_08_CSI_DATA05 0x0DC 0x2CC 0x40C 0x4 0x1
-#define MXRT1050_IOMUXC_GPIO_AD_B0_08_GPIO1_IO08 0x0DC 0x2CC 0x000 0x5 0x0
-#define MXRT1050_IOMUXC_GPIO_AD_B0_08_XBAR_INOUT20 0x0DC 0x2CC 0x634 0x6 0x1
-#define MXRT1050_IOMUXC_GPIO_AD_B0_08_ENET_1588_EVENT3_IN 0x0DC 0x2CC 0x000 0x7 0x0
-
-#define MXRT1050_IOMUXC_GPIO_AD_B0_09_JTAG_TDI 0x0E0 0x2D0 0x000 0x0 0x0
-#define MXRT1050_IOMUXC_GPIO_AD_B0_09_FLEXPWM2_PWM3_A 0x0E0 0x2D0 0x000 0x1 0x0
-#define MXRT1050_IOMUXC_GPIO_AD_B0_09_ENET_RX_DATA02 0x0E0 0x2D0 0x000 0x2 0x0
-#define MXRT1050_IOMUXC_GPIO_AD_B0_09_SAI2_TX_DATA 0x0E0 0x2D0 0x000 0x3 0x0
-#define MXRT1050_IOMUXC_GPIO_AD_B0_09_CSI_DATA04 0x0E0 0x2D0 0x408 0x4 0x1
-#define MXRT1050_IOMUXC_GPIO_AD_B0_09_GPIO1_IO09 0x0E0 0x2D0 0x000 0x5 0x0
-#define MXRT1050_IOMUXC_GPIO_AD_B0_09_XBAR_INOUT21 0x0E0 0x2D0 0x658 0x6 0x1
-#define MXRT1050_IOMUXC_GPIO_AD_B0_09_GPT2_CLK 0x0E0 0x2D0 0x000 0x7 0x0
-
-#define MXRT1050_IOMUXC_GPIO_AD_B0_10_JTAG_TDO 0x0E4 0x2D4 0x000 0x0 0x0
-#define MXRT1050_IOMUXC_GPIO_AD_B0_10_FLEXPWM1_PWM3_A 0x0E4 0x2D4 0x454 0x1 0x3
-#define MXRT1050_IOMUXC_GPIO_AD_B0_10_ENET_CRS 0x0E4 0x2D4 0x000 0x2 0x0
-#define MXRT1050_IOMUXC_GPIO_AD_B0_10_SAI2_MCLK 0x0E4 0x2D4 0x5B0 0x3 0x1
-#define MXRT1050_IOMUXC_GPIO_AD_B0_10_CSI_DATA03 0x0E4 0x2D4 0x404 0x4 0x1
-#define MXRT1050_IOMUXC_GPIO_AD_B0_10_GPIO1_IO10 0x0E4 0x2D4 0x000 0x5 0x0
-#define MXRT1050_IOMUXC_GPIO_AD_B0_10_XBAR_INOUT22 0x0E4 0x2D4 0x638 0x6 0x1
-#define MXRT1050_IOMUXC_GPIO_AD_B0_10_ENET_1588_EVENT0_OUT 0x0E4 0x2D4 0x000 0x7 0x0
-
-#define MXRT1050_IOMUXC_GPIO_AD_B0_11_JTAG_TRSTB 0x0E8 0x2D8 0x000 0x0 0x0
-#define MXRT1050_IOMUXC_GPIO_AD_B0_11_FLEXPWM1_PWM3_B 0x0E8 0x2D8 0x464 0x1 0x3
-#define MXRT1050_IOMUXC_GPIO_AD_B0_11_ENET_COL 0x0E8 0x2D8 0x000 0x2 0x0
-#define MXRT1050_IOMUXC_GPIO_AD_B0_11_WDOG1_B 0x0E8 0x2D8 0x000 0x3 0x0
-#define MXRT1050_IOMUXC_GPIO_AD_B0_11_CSI_DATA02 0x0E8 0x2D8 0x400 0x4 0x1
-#define MXRT1050_IOMUXC_GPIO_AD_B0_11_GPIO1_IO11 0x0E8 0x2D8 0x000 0x5 0x0
-#define MXRT1050_IOMUXC_GPIO_AD_B0_11_XBAR_INOUT23 0x0E8 0x2D8 0x63C 0x6 0x1
-#define MXRT1050_IOMUXC_GPIO_AD_B0_11_ENET_1588_EVENT0_IN 0x0E8 0x2D8 0x444 0x7 0x1
-
-#define MXRT1050_IOMUXC_GPIO_AD_B0_12_LPI2C4_SCL 0x0EC 0x2DC 0x4E4 0x0 0x1
-#define MXRT1050_IOMUXC_GPIO_AD_B0_12_CCM_PMIC_READY 0x0EC 0x2DC 0x3FC 0x1 0x1
-#define MXRT1050_IOMUXC_GPIO_AD_B0_12_LPUART1_TXD 0x0EC 0x2DC 0x000 0x2 0x0
-#define MXRT1050_IOMUXC_GPIO_AD_B0_12_WDOG2_B 0x0EC 0x2DC 0x000 0x3 0x0
-#define MXRT1050_IOMUXC_GPIO_AD_B0_12_FLEXPWM1_PWM2_X 0x0EC 0x2DC 0x000 0x4 0x0
-#define MXRT1050_IOMUXC_GPIO_AD_B0_12_GPIO1_IO12 0x0EC 0x2DC 0x000 0x5 0x0
-#define MXRT1050_IOMUXC_GPIO_AD_B0_12_ENET_1588_EVENT1_OUT 0x0EC 0x2DC 0x000 0x6 0x0
-#define MXRT1050_IOMUXC_GPIO_AD_B0_12_NMI 0x0EC 0x2DC 0x568 0x7 0x0
-
-#define MXRT1050_IOMUXC_GPIO_AD_B0_13_LPI2C4_SDA 0x0F0 0x2E0 0x4E8 0x0 0x1
-#define MXRT1050_IOMUXC_GPIO_AD_B0_13_GPT1_CLK 0x0F0 0x2E0 0x000 0x1 0x0
-#define MXRT1050_IOMUXC_GPIO_AD_B0_13_LPUART1_RXD 0x0F0 0x2E0 0x000 0x2 0x0
-#define MXRT1050_IOMUXC_GPIO_AD_B0_13_EWM_OUT_B 0x0F0 0x2E0 0x000 0x3 0x0
-#define MXRT1050_IOMUXC_GPIO_AD_B0_13_FLEXPWM1_PWM3_X 0x0F0 0x2E0 0x000 0x4 0x0
-#define MXRT1050_IOMUXC_GPIO_AD_B0_13_GPIO1_IO13 0x0F0 0x2E0 0x000 0x5 0x0
-#define MXRT1050_IOMUXC_GPIO_AD_B0_13_ENET_1588_EVENT1_IN 0x0F0 0x2E0 0x000 0x6 0x0
-#define MXRT1050_IOMUXC_GPIO_AD_B0_13_REF_CLK_24M 0x0F0 0x2E0 0x000 0x7 0x0
-
-#define MXRT1050_IOMUXC_GPIO_AD_B0_14_USB_OTG2_OC 0x0F4 0x2E4 0x5CC 0x0 0x0
-#define MXRT1050_IOMUXC_GPIO_AD_B0_14_XBAR_INOUT24 0x0F4 0x2E4 0x640 0x1 0x1
-#define MXRT1050_IOMUXC_GPIO_AD_B0_14_LPUART1_CTS_B 0x0F4 0x2E4 0x000 0x2 0x0
-#define MXRT1050_IOMUXC_GPIO_AD_B0_14_ENET_1588_EVENT0_OUT 0x0F4 0x2E4 0x000 0x3 0x0
-#define MXRT1050_IOMUXC_GPIO_AD_B0_14_CSI_VSYNC 0x0F4 0x2E4 0x428 0x4 0x0
-#define MXRT1050_IOMUXC_GPIO_AD_B0_14_GPIO1_IO14 0x0F4 0x2E4 0x000 0x5 0x0
-#define MXRT1050_IOMUXC_GPIO_AD_B0_14_FLEXCAN2_TX 0x0F4 0x2E4 0x000 0x6 0x0
-
-#define MXRT1050_IOMUXC_GPIO_AD_B0_15_USB_OTG2_PWR 0x0F8 0x2E8 0x000 0x0 0x0
-#define MXRT1050_IOMUXC_GPIO_AD_B0_15_XBAR_INOUT25 0x0F8 0x2E8 0x650 0x1 0x0
-#define MXRT1050_IOMUXC_GPIO_AD_B0_15_LPUART1_RTS_B 0x0F8 0x2E8 0x000 0x2 0x0
-#define MXRT1050_IOMUXC_GPIO_AD_B0_15_ENET_1588_EVENT0_IN 0x0F8 0x2E8 0x444 0x3 0x0
-#define MXRT1050_IOMUXC_GPIO_AD_B0_15_CSI_HSYNC 0x0F8 0x2E8 0x420 0x4 0x0
-#define MXRT1050_IOMUXC_GPIO_AD_B0_15_GPIO1_IO15 0x0F8 0x2E8 0x000 0x5 0x0
-#define MXRT1050_IOMUXC_GPIO_AD_B0_15_FLEXCAN2_RX 0x0F8 0x2E8 0x450 0x6 0x2
-#define MXRT1050_IOMUXC_GPIO_AD_B0_15_WDOG1_WDOG_RST_B_DEB 0x0F8 0x2E8 0x000 0x7 0x0
-
-#define MXRT1050_IOMUXC_GPIO_AD_B1_00_USB_OTG2_ID 0x0FC 0x2EC 0x3F8 0x0 0x1
-#define MXRT1050_IOMUXC_GPIO_AD_B1_00_TMR3_TIMER0 0x0FC 0x2EC 0x57C 0x1 0x1
-#define MXRT1050_IOMUXC_GPIO_AD_B1_00_LPUART2_CTS_B 0x0FC 0x2EC 0x000 0x2 0x0
-#define MXRT1050_IOMUXC_GPIO_AD_B1_00_LPI2C1_SCL 0x0FC 0x2EC 0x4CC 0x3 0x1
-#define MXRT1050_IOMUXC_GPIO_AD_B1_00_WDOG1_B 0x0FC 0x2EC 0x000 0x4 0x0
-#define MXRT1050_IOMUXC_GPIO_AD_B1_00_GPIO1_IO16 0x0FC 0x2EC 0x000 0x5 0x0
-#define MXRT1050_IOMUXC_GPIO_AD_B1_00_USDHC1_WP 0x0FC 0x2EC 0x5D8 0x6 0x2
-#define MXRT1050_IOMUXC_GPIO_AD_B1_00_KPP_ROW07 0x0FC 0x2EC 0x000 0x7 0x0
-
-#define MXRT1050_IOMUXC_GPIO_AD_B1_01_USB_OTG1_PWR 0x100 0x2F0 0x000 0x0 0x0
-#define MXRT1050_IOMUXC_GPIO_AD_B1_01_TMR3_TIMER1 0x100 0x2F0 0x580 0x1 0x1
-#define MXRT1050_IOMUXC_GPIO_AD_B1_01_LPUART2_RTS_B 0x100 0x2F0 0x000 0x2 0x0
-#define MXRT1050_IOMUXC_GPIO_AD_B1_01_LPI2C1_SDA 0x100 0x2F0 0x4D0 0x3 0x1
-#define MXRT1050_IOMUXC_GPIO_AD_B1_01_CCM_PMIC_READY 0x100 0x2F0 0x3FC 0x4 0x2
-#define MXRT1050_IOMUXC_GPIO_AD_B1_01_GPIO1_IO17 0x100 0x2F0 0x000 0x5 0x0
-#define MXRT1050_IOMUXC_GPIO_AD_B1_01_USDHC1_VSELECT 0x100 0x2F0 0x000 0x6 0x0
-#define MXRT1050_IOMUXC_GPIO_AD_B1_01_KPP_COL07 0x100 0x2F0 0x000 0x7 0x0
-
-#define MXRT1050_IOMUXC_GPIO_AD_B1_02_USB_OTG1_ID 0x104 0x2F4 0x3F4 0x0 0x1
-#define MXRT1050_IOMUXC_GPIO_AD_B1_02_TMR3_TIMER2 0x104 0x2F4 0x584 0x1 0x1
-#define MXRT1050_IOMUXC_GPIO_AD_B1_02_LPUART2_TXD 0x104 0x2F4 0x530 0x2 0x1
-#define MXRT1050_IOMUXC_GPIO_AD_B1_02_SPDIF_OUT 0x104 0x2F4 0x000 0x3 0x0
-#define MXRT1050_IOMUXC_GPIO_AD_B1_02_ENET_1588_EVENT2_OUT 0x104 0x2F4 0x000 0x4 0x0
-#define MXRT1050_IOMUXC_GPIO_AD_B1_02_GPIO1_IO18 0x104 0x2F4 0x000 0x5 0x0
-#define MXRT1050_IOMUXC_GPIO_AD_B1_02_USDHC1_CD_B 0x104 0x2F4 0x5D4 0x6 0x1
-#define MXRT1050_IOMUXC_GPIO_AD_B1_02_KPP_ROW06 0x104 0x2F4 0x000 0x7 0x0
-
-#define MXRT1050_IOMUXC_GPIO_AD_B1_03_USB_OTG1_OC 0x108 0x2F8 0x5D0 0x0 0x1
-#define MXRT1050_IOMUXC_GPIO_AD_B1_03_TMR3_TIMER3 0x108 0x2F8 0x588 0x1 0x1
-#define MXRT1050_IOMUXC_GPIO_AD_B1_03_LPUART2_RXD 0x108 0x2F8 0x52C 0x2 0x1
-#define MXRT1050_IOMUXC_GPIO_AD_B1_03_SPDIF_IN 0x108 0x2F8 0x5C8 0x3 0x0
-#define MXRT1050_IOMUXC_GPIO_AD_B1_03_ENET_1588_EVENT2_IN 0x108 0x2F8 0x000 0x4 0x0
-#define MXRT1050_IOMUXC_GPIO_AD_B1_03_GPIO1_IO19 0x108 0x2F8 0x000 0x5 0x0
-#define MXRT1050_IOMUXC_GPIO_AD_B1_03_USDHC2_CD_B 0x108 0x2F8 0x5E0 0x6 0x0
-#define MXRT1050_IOMUXC_GPIO_AD_B1_03_KPP_COL06 0x108 0x2F8 0x000 0x7 0x0
-
-#define MXRT1050_IOMUXC_GPIO_AD_B1_04_FLEXSPI_B_DATA3 0x10C 0x2FC 0x4C4 0x0 0x1
-#define MXRT1050_IOMUXC_GPIO_AD_B1_04_ENET_MDC 0x10C 0x2FC 0x000 0x1 0x0
-#define MXRT1050_IOMUXC_GPIO_AD_B1_04_LPUART3_CTS_B 0x10C 0x2FC 0x534 0x2 0x1
-#define MXRT1050_IOMUXC_GPIO_AD_B1_04_SPDIF_SR_CLK 0x10C 0x2FC 0x000 0x3 0x0
-#define MXRT1050_IOMUXC_GPIO_AD_B1_04_CSI_PIXCLK 0x10C 0x2FC 0x424 0x4 0x0
-#define MXRT1050_IOMUXC_GPIO_AD_B1_04_GPIO1_IO20 0x10C 0x2FC 0x000 0x5 0x0
-#define MXRT1050_IOMUXC_GPIO_AD_B1_04_USDHC2_DATA0 0x10C 0x2FC 0x5E8 0x6 0x1
-#define MXRT1050_IOMUXC_GPIO_AD_B1_04_KPP_ROW05 0x10C 0x2FC 0x000 0x7 0x0
-
-#define MXRT1050_IOMUXC_GPIO_AD_B1_05_FLEXSPI_B_DATA2 0x110 0x300 0x4C0 0x0 0x1
-#define MXRT1050_IOMUXC_GPIO_AD_B1_05_ENET_MDIO 0x110 0x300 0x430 0x1 0x0
-#define MXRT1050_IOMUXC_GPIO_AD_B1_05_LPUART3_RTS_B 0x110 0x300 0x000 0x2 0x0
-#define MXRT1050_IOMUXC_GPIO_AD_B1_05_SPDIF_OUT 0x110 0x300 0x000 0x3 0x0
-#define MXRT1050_IOMUXC_GPIO_AD_B1_05_CSI_MCLK 0x110 0x300 0x000 0x4 0x0
-#define MXRT1050_IOMUXC_GPIO_AD_B1_05_GPIO1_IO21 0x110 0x300 0x000 0x5 0x0
-#define MXRT1050_IOMUXC_GPIO_AD_B1_05_USDHC2_DATA1 0x110 0x300 0x5EC 0x6 0x1
-#define MXRT1050_IOMUXC_GPIO_AD_B1_05_KPP_COL05 0x110 0x300 0x000 0x7 0x0
-
-#define MXRT1050_IOMUXC_GPIO_AD_B1_06_FLEXSPI_B_DATA1 0x114 0x304 0x4BC 0x0 0x1
-#define MXRT1050_IOMUXC_GPIO_AD_B1_06_LPI2C3_SDA 0x114 0x304 0x4E0 0x1 0x2
-#define MXRT1050_IOMUXC_GPIO_AD_B1_06_LPUART3_TXD 0x114 0x304 0x53C 0x2 0x1
-#define MXRT1050_IOMUXC_GPIO_AD_B1_06_SPDIF_LOCK 0x114 0x304 0x000 0x3 0x0
-#define MXRT1050_IOMUXC_GPIO_AD_B1_06_CSI_VSYNC 0x114 0x304 0x428 0x4 0x1
-#define MXRT1050_IOMUXC_GPIO_AD_B1_06_GPIO1_IO22 0x114 0x304 0x000 0x5 0x0
-#define MXRT1050_IOMUXC_GPIO_AD_B1_06_USDHC2_DATA2 0x114 0x304 0x5F0 0x6 0x1
-#define MXRT1050_IOMUXC_GPIO_AD_B1_06_KPP_ROW04 0x114 0x304 0x000 0x7 0x0
-
-#define MXRT1050_IOMUXC_GPIO_AD_B1_07_FLEXSPI_B_DATA0 0x118 0x308 0x4B8 0x0 0x1
-#define MXRT1050_IOMUXC_GPIO_AD_B1_07_LPI2C3_SCL 0x118 0x308 0x4DC 0x1 0x2
-#define MXRT1050_IOMUXC_GPIO_AD_B1_07_LPUART3_RXD 0x118 0x308 0x538 0x2 0x1
-#define MXRT1050_IOMUXC_GPIO_AD_B1_07_SPDIF_EXT_CLK 0x118 0x308 0x000 0x3 0x0
-#define MXRT1050_IOMUXC_GPIO_AD_B1_07_CSI_HSYNC 0x118 0x308 0x420 0x4 0x1
-#define MXRT1050_IOMUXC_GPIO_AD_B1_07_GPIO1_IO23 0x118 0x308 0x000 0x5 0x0
-#define MXRT1050_IOMUXC_GPIO_AD_B1_07_USDHC2_DATA3 0x118 0x308 0x5F4 0x6 0x1
-#define MXRT1050_IOMUXC_GPIO_AD_B1_07_KPP_COL04 0x118 0x308 0x000 0x7 0x0
-
-#define MXRT1050_IOMUXC_GPIO_AD_B1_08_FLEXSPI_A_SS1_B 0x11C 0x30C 0x000 0x0 0x0
-#define MXRT1050_IOMUXC_GPIO_AD_B1_08_FLEXPWM4_PWM0_A 0x11C 0x30C 0x494 0x1 0x1
-#define MXRT1050_IOMUXC_GPIO_AD_B1_08_FLEXCAN1_TX 0x11C 0x30C 0x000 0x2 0x0
-#define MXRT1050_IOMUXC_GPIO_AD_B1_08_CCM_PMIC_READY 0x11C 0x30C 0x3FC 0x3 0x3
-#define MXRT1050_IOMUXC_GPIO_AD_B1_08_CSI_DATA09 0x11C 0x30C 0x41C 0x4 0x0
-#define MXRT1050_IOMUXC_GPIO_AD_B1_08_GPIO1_IO24 0x11C 0x30C 0x000 0x5 0x0
-#define MXRT1050_IOMUXC_GPIO_AD_B1_08_USDHC2_CMD 0x11C 0x30C 0x5E4 0x6 0x1
-#define MXRT1050_IOMUXC_GPIO_AD_B1_08_KPP_ROW03 0x11C 0x30C 0x000 0x7 0x0
-
-#define MXRT1050_IOMUXC_GPIO_AD_B1_09_FLEXSPI_A_DQS 0x120 0x310 0x4A4 0x0 0x1
-#define MXRT1050_IOMUXC_GPIO_AD_B1_09_FLEXPWM4_PWM1_A 0x120 0x310 0x498 0x1 0x1
-#define MXRT1050_IOMUXC_GPIO_AD_B1_09_FLEXCAN1_RX 0x120 0x310 0x44C 0x2 0x2
-#define MXRT1050_IOMUXC_GPIO_AD_B1_09_SAI1_MCLK 0x120 0x310 0x58C 0x3 0x1
-#define MXRT1050_IOMUXC_GPIO_AD_B1_09_CSI_DATA08 0x120 0x310 0x418 0x4 0x0
-#define MXRT1050_IOMUXC_GPIO_AD_B1_09_GPIO1_IO25 0x120 0x310 0x000 0x5 0x0
-#define MXRT1050_IOMUXC_GPIO_AD_B1_09_USDHC2_CLK 0x120 0x310 0x5DC 0x6 0x1
-#define MXRT1050_IOMUXC_GPIO_AD_B1_09_KPP_COL03 0x120 0x310 0x000 0x7 0x0
-
-#define MXRT1050_IOMUXC_GPIO_AD_B1_10_FLEXSPI_A_DATA3 0x124 0x314 0x4B4 0x0 0x1
-#define MXRT1050_IOMUXC_GPIO_AD_B1_10_WDOG1_B 0x124 0x314 0x000 0x1 0x0
-#define MXRT1050_IOMUXC_GPIO_AD_B1_10_LPUART8_TXD 0x124 0x314 0x564 0x2 0x1
-#define MXRT1050_IOMUXC_GPIO_AD_B1_10_SAI1_RX_SYNC 0x124 0x314 0x5A4 0x3 0x1
-#define MXRT1050_IOMUXC_GPIO_AD_B1_10_CSI_DATA07 0x124 0x314 0x414 0x4 0x0
-#define MXRT1050_IOMUXC_GPIO_AD_B1_10_GPIO1_IO26 0x124 0x314 0x000 0x5 0x0
-#define MXRT1050_IOMUXC_GPIO_AD_B1_10_USDHC2_WP 0x124 0x314 0x608 0x6 0x1
-#define MXRT1050_IOMUXC_GPIO_AD_B1_10_KPP_ROW02 0x124 0x314 0x000 0x7 0x0
-
-#define MXRT1050_IOMUXC_GPIO_AD_B1_11_FLEXSPI_A_DATA2 0x128 0x318 0x4B0 0x0 0x1
-#define MXRT1050_IOMUXC_GPIO_AD_B1_11_EWM_OUT_B 0x128 0x318 0x000 0x1 0x0
-#define MXRT1050_IOMUXC_GPIO_AD_B1_11_LPUART8_RXD 0x128 0x318 0x560 0x2 0x1
-#define MXRT1050_IOMUXC_GPIO_AD_B1_11_SAI1_RX_BCLK 0x128 0x318 0x590 0x3 0x1
-#define MXRT1050_IOMUXC_GPIO_AD_B1_11_CSI_DATA06 0x128 0x318 0x410 0x4 0x0
-#define MXRT1050_IOMUXC_GPIO_AD_B1_11_GPIO1_IO27 0x128 0x318 0x000 0x5 0x0
-#define MXRT1050_IOMUXC_GPIO_AD_B1_11_USDHC2_RESET_B 0x128 0x318 0x000 0x6 0x0
-#define MXRT1050_IOMUXC_GPIO_AD_B1_11_KPP_COL02 0x128 0x318 0x000 0x7 0x0
-
-#define MXRT1050_IOMUXC_GPIO_AD_B1_12_FLEXSPI_A_DATA1 0x12C 0x31C 0x4AC 0x0 0x1
-#define MXRT1050_IOMUXC_GPIO_AD_B1_12_ACMP1_OUT 0x12C 0x31C 0x000 0x1 0x0
-#define MXRT1050_IOMUXC_GPIO_AD_B1_12_LPSPI3_PCS0 0x12C 0x31C 0x50C 0x2 0x1
-#define MXRT1050_IOMUXC_GPIO_AD_B1_12_SAI1_RX_DATA00 0x12C 0x31C 0x594 0x3 0x1
-#define MXRT1050_IOMUXC_GPIO_AD_B1_12_CSI_DATA05 0x12C 0x31C 0x40C 0x4 0x0
-#define MXRT1050_IOMUXC_GPIO_AD_B1_12_GPIO1_IO28 0x12C 0x31C 0x000 0x5 0x0
-#define MXRT1050_IOMUXC_GPIO_AD_B1_12_USDHC2_DATA4 0x12C 0x31C 0x5F8 0x6 0x1
-#define MXRT1050_IOMUXC_GPIO_AD_B1_12_KPP_ROW01 0x12C 0x31C 0x000 0x7 0x0
-
-#define MXRT1050_IOMUXC_GPIO_AD_B1_13_FLEXSPI_A_DATA0 0x130 0x320 0x4A8 0x0 0x1
-#define MXRT1050_IOMUXC_GPIO_AD_B1_13_ACMP2_OUT 0x130 0x320 0x000 0x1 0x0
-#define MXRT1050_IOMUXC_GPIO_AD_B1_13_LPSPI3_SDI 0x130 0x320 0x514 0x2 0x0
-#define MXRT1050_IOMUXC_GPIO_AD_B1_13_SAI1_TX_DATA00 0x130 0x320 0x000 0x3 0x0
-#define MXRT1050_IOMUXC_GPIO_AD_B1_13_CSI_DATA04 0x130 0x320 0x408 0x4 0x0
-#define MXRT1050_IOMUXC_GPIO_AD_B1_13_GPIO1_IO29 0x130 0x320 0x000 0x5 0x0
-#define MXRT1050_IOMUXC_GPIO_AD_B1_13_USDHC2_DATA5 0x130 0x320 0x5FC 0x6 0x1
-#define MXRT1050_IOMUXC_GPIO_AD_B1_13_KPP_COL01 0x130 0x320 0x000 0x7 0x0
-
-#define MXRT1050_IOMUXC_GPIO_AD_B1_14_FLEXSPI_A_SCLK 0x134 0x324 0x4C8 0x0 0x1
-#define MXRT1050_IOMUXC_GPIO_AD_B1_14_ACMP3_OUT 0x134 0x324 0x000 0x1 0x0
-#define MXRT1050_IOMUXC_GPIO_AD_B1_14_LPSPI3_SDO 0x134 0x324 0x518 0x2 0x0
-#define MXRT1050_IOMUXC_GPIO_AD_B1_14_SAI1_TX_BCLK 0x134 0x324 0x5A8 0x3 0x1
-#define MXRT1050_IOMUXC_GPIO_AD_B1_14_CSI_DATA03 0x134 0x324 0x404 0x4 0x0
-#define MXRT1050_IOMUXC_GPIO_AD_B1_14_GPIO1_IO30 0x134 0x324 0x000 0x5 0x0
-#define MXRT1050_IOMUXC_GPIO_AD_B1_14_USDHC2_DATA6 0x134 0x324 0x600 0x6 0x1
-#define MXRT1050_IOMUXC_GPIO_AD_B1_14_KPP_ROW00 0x134 0x324 0x000 0x7 0x0
-
-#define MXRT1050_IOMUXC_GPIO_AD_B1_15_FLEXSPI_A_SS0_B 0x138 0x328 0x000 0x0 0x0
-#define MXRT1050_IOMUXC_GPIO_AD_B1_15_ACMP4_OUT 0x138 0x328 0x000 0x1 0x0
-#define MXRT1050_IOMUXC_GPIO_AD_B1_15_LPSPI3_SCK 0x138 0x328 0x510 0x2 0x1
-#define MXRT1050_IOMUXC_GPIO_AD_B1_15_SAI1_TX_SYNC 0x138 0x328 0x5AC 0x3 0x1
-#define MXRT1050_IOMUXC_GPIO_AD_B1_15_CSI_DATA02 0x138 0x328 0x400 0x4 0x0
-#define MXRT1050_IOMUXC_GPIO_AD_B1_15_GPIO1_IO31 0x138 0x328 0x000 0x5 0x0
-#define MXRT1050_IOMUXC_GPIO_AD_B1_15_USDHC2_DATA7 0x138 0x328 0x604 0x6 0x1
-#define MXRT1050_IOMUXC_GPIO_AD_B1_15_KPP_COL00 0x138 0x328 0x000 0x7 0x0
-
-#define MXRT1050_IOMUXC_GPIO_B0_00_LCD_CLK 0x13C 0x32C 0x000 0x0 0x0
-#define MXRT1050_IOMUXC_GPIO_B0_00_TMR1_TIMER0 0x13C 0x32C 0x000 0x1 0x0
-#define MXRT1050_IOMUXC_GPIO_B0_00_MQS_RIGHT 0x13C 0x32C 0x000 0x2 0x0
-#define MXRT1050_IOMUXC_GPIO_B0_00_LPSPI4_PCS0 0x13C 0x32C 0x51C 0x3 0x0
-#define MXRT1050_IOMUXC_GPIO_B0_00_FLEXIO2_D00 0x13C 0x32C 0x000 0x4 0x0
-#define MXRT1050_IOMUXC_GPIO_B0_00_GPIO2_IO00 0x13C 0x32C 0x000 0x5 0x0
-#define MXRT1050_IOMUXC_GPIO_B0_00_SEMC_CSX1 0x13C 0x32C 0x000 0x6 0x0
-
-#define MXRT1050_IOMUXC_GPIO_B0_01_LCD_ENABLE 0x140 0x330 0x000 0x0 0x0
-#define MXRT1050_IOMUXC_GPIO_B0_01_TMR1_TIMER1 0x140 0x330 0x000 0x1 0x0
-#define MXRT1050_IOMUXC_GPIO_B0_01_MQS_LEFT 0x140 0x330 0x000 0x2 0x0
-#define MXRT1050_IOMUXC_GPIO_B0_01_LPSPI4_SDI 0x140 0x330 0x524 0x3 0x0
-#define MXRT1050_IOMUXC_GPIO_B0_01_FLEXIO2_D01 0x140 0x330 0x000 0x4 0x0
-#define MXRT1050_IOMUXC_GPIO_B0_01_GPIO2_IO01 0x140 0x330 0x000 0x5 0x0
-#define MXRT1050_IOMUXC_GPIO_B0_01_SEMC_CSX2 0x140 0x330 0x000 0x6 0x0
-
-#define MXRT1050_IOMUXC_GPIO_B0_02_LCD_HSYNC 0x144 0x334 0x000 0x0 0x0
-#define MXRT1050_IOMUXC_GPIO_B0_02_TMR1_TIMER2 0x144 0x334 0x000 0x1 0x0
-#define MXRT1050_IOMUXC_GPIO_B0_02_FLEXCAN1_TX 0x144 0x334 0x000 0x2 0x0
-#define MXRT1050_IOMUXC_GPIO_B0_02_LPSPI4_SDO 0x144 0x334 0x528 0x3 0x0
-#define MXRT1050_IOMUXC_GPIO_B0_02_FLEXIO2_D02 0x144 0x334 0x000 0x4 0x0
-#define MXRT1050_IOMUXC_GPIO_B0_02_GPIO2_IO02 0x144 0x334 0x000 0x5 0x0
-#define MXRT1050_IOMUXC_GPIO_B0_02_SEMC_CSX3 0x144 0x334 0x000 0x6 0x0
-
-#define MXRT1050_IOMUXC_GPIO_B0_03_LCD_VSYNC 0x148 0x338 0x000 0x0 0x0
-#define MXRT1050_IOMUXC_GPIO_B0_03_TMR2_TIMER0 0x148 0x338 0x56C 0x1 0x1
-#define MXRT1050_IOMUXC_GPIO_B0_03_FLEXCAN1_RX 0x148 0x338 0x44C 0x2 0x3
-#define MXRT1050_IOMUXC_GPIO_B0_03_LPSPI4_SCK 0x148 0x338 0x520 0x3 0x0
-#define MXRT1050_IOMUXC_GPIO_B0_03_FLEXIO2_D03 0x148 0x338 0x000 0x4 0x0
-#define MXRT1050_IOMUXC_GPIO_B0_03_GPIO2_IO03 0x148 0x338 0x000 0x5 0x0
-#define MXRT1050_IOMUXC_GPIO_B0_03_WDOG2_RESET_B_DEB 0x148 0x338 0x000 0x6 0x0
-
-#define MXRT1050_IOMUXC_GPIO_B0_04_LCD_DATA00 0x14C 0x33C 0x000 0x0 0x0
-#define MXRT1050_IOMUXC_GPIO_B0_04_TMR2_TIMER1 0x14C 0x33C 0x570 0x1 0x1
-#define MXRT1050_IOMUXC_GPIO_B0_04_LPI2C2_SCL 0x14C 0x33C 0x4D4 0x2 0x1
-#define MXRT1050_IOMUXC_GPIO_B0_04_ARM_TRACE00 0x14C 0x33C 0x000 0x3 0x0
-#define MXRT1050_IOMUXC_GPIO_B0_04_FLEXIO2_D04 0x14C 0x33C 0x000 0x4 0x0
-#define MXRT1050_IOMUXC_GPIO_B0_04_GPIO2_IO04 0x14C 0x33C 0x000 0x5 0x0
-#define MXRT1050_IOMUXC_GPIO_B0_04_SRC_BT_CFG00 0x14C 0x33C 0x000 0x6 0x0
-
-#define MXRT1050_IOMUXC_GPIO_B0_05_LCD_DATA01 0x150 0x340 0x000 0x0 0x0
-#define MXRT1050_IOMUXC_GPIO_B0_05_TMR2_TIMER2 0x150 0x340 0x574 0x1 0x1
-#define MXRT1050_IOMUXC_GPIO_B0_05_LPI2C2_SDA 0x150 0x340 0x4D8 0x2 0x1
-#define MXRT1050_IOMUXC_GPIO_B0_05_ARM_TRACE01 0x150 0x340 0x000 0x3 0x0
-#define MXRT1050_IOMUXC_GPIO_B0_05_FLEXIO2_D05 0x150 0x340 0x000 0x4 0x0
-#define MXRT1050_IOMUXC_GPIO_B0_05_GPIO2_IO05 0x150 0x340 0x000 0x5 0x0
-#define MXRT1050_IOMUXC_GPIO_B0_05_SRC_BT_CFG01 0x150 0x340 0x000 0x6 0x0
-
-#define MXRT1050_IOMUXC_GPIO_B0_06_LCD_DATA02 0x154 0x344 0x000 0x0 0x0
-#define MXRT1050_IOMUXC_GPIO_B0_06_TMR3_TIMER0 0x154 0x344 0x57C 0x1 0x2
-#define MXRT1050_IOMUXC_GPIO_B0_06_FLEXPWM2_PWM0_A 0x154 0x344 0x478 0x2 0x1
-#define MXRT1050_IOMUXC_GPIO_B0_06_ARM_TRACE02 0x154 0x344 0x000 0x3 0x0
-#define MXRT1050_IOMUXC_GPIO_B0_06_FLEXIO2_D06 0x154 0x344 0x000 0x4 0x0
-#define MXRT1050_IOMUXC_GPIO_B0_06_GPIO2_IO06 0x154 0x344 0x000 0x5 0x0
-#define MXRT1050_IOMUXC_GPIO_B0_06_SRC_BT_CFG02 0x154 0x344 0x000 0x6 0x0
-
-#define MXRT1050_IOMUXC_GPIO_B0_07_LCD_DATA03 0x158 0x348 0x000 0x0 0x0
-#define MXRT1050_IOMUXC_GPIO_B0_07_TMR3_TIMER1 0x158 0x348 0x580 0x1 0x2
-#define MXRT1050_IOMUXC_GPIO_B0_07_FLEXPWM2_PWM0_B 0x158 0x348 0x488 0x2 0x1
-#define MXRT1050_IOMUXC_GPIO_B0_07_ARM_TRACE03 0x158 0x348 0x000 0x3 0x0
-#define MXRT1050_IOMUXC_GPIO_B0_07_FLEXIO2_D07 0x158 0x348 0x000 0x4 0x0
-#define MXRT1050_IOMUXC_GPIO_B0_07_GPIO2_IO07 0x158 0x348 0x000 0x5 0x0
-#define MXRT1050_IOMUXC_GPIO_B0_07_SRC_BT_CFG03 0x158 0x348 0x000 0x6 0x0
-
-#define MXRT1050_IOMUXC_GPIO_B0_08_LCD_DATA04 0x15C 0x34C 0x000 0x0 0x0
-#define MXRT1050_IOMUXC_GPIO_B0_08_TMR3_TIMER2 0x15C 0x34C 0x584 0x1 0x2
-#define MXRT1050_IOMUXC_GPIO_B0_08_FLEXPWM2_PWM1_A 0x15C 0x34C 0x47C 0x2 0x1
-#define MXRT1050_IOMUXC_GPIO_B0_08_LPUART3_TXD 0x15C 0x34C 0x53C 0x3 0x2
-#define MXRT1050_IOMUXC_GPIO_B0_08_FLEXIO2_D08 0x15C 0x34C 0x000 0x4 0x0
-#define MXRT1050_IOMUXC_GPIO_B0_08_GPIO2_IO08 0x15C 0x34C 0x000 0x5 0x0
-#define MXRT1050_IOMUXC_GPIO_B0_08_SRC_BT_CFG04 0x15C 0x34C 0x000 0x6 0x0
-
-#define MXRT1050_IOMUXC_GPIO_B0_09_LCD_DATA05 0x160 0x350 0x000 0x0 0x0
-#define MXRT1050_IOMUXC_GPIO_B0_09_TMR4_TIMER0 0x160 0x350 0x000 0x1 0x0
-#define MXRT1050_IOMUXC_GPIO_B0_09_FLEXPWM2_PWM1_B 0x160 0x350 0x48C 0x2 0x1
-#define MXRT1050_IOMUXC_GPIO_B0_09_LPUART3_RXD 0x160 0x350 0x538 0x3 0x2
-#define MXRT1050_IOMUXC_GPIO_B0_09_FLEXIO2_D09 0x160 0x350 0x000 0x4 0x0
-#define MXRT1050_IOMUXC_GPIO_B0_09_GPIO2_IO09 0x160 0x350 0x000 0x5 0x0
-#define MXRT1050_IOMUXC_GPIO_B0_09_SRC_BT_CFG05 0x160 0x350 0x000 0x6 0x0
-
-#define MXRT1050_IOMUXC_GPIO_B0_10_LCD_DATA06 0x164 0x354 0x000 0x0 0x0
-#define MXRT1050_IOMUXC_GPIO_B0_10_TMR4_TIMER1 0x164 0x354 0x000 0x1 0x0
-#define MXRT1050_IOMUXC_GPIO_B0_10_FLEXPWM2_PWM2_A 0x164 0x354 0x480 0x2 0x1
-#define MXRT1050_IOMUXC_GPIO_B0_10_SAI1_TX_DATA03 0x164 0x354 0x598 0x3 0x1
-#define MXRT1050_IOMUXC_GPIO_B0_10_FLEXIO2_D10 0x164 0x354 0x000 0x4 0x0
-#define MXRT1050_IOMUXC_GPIO_B0_10_GPIO2_IO10 0x164 0x354 0x000 0x5 0x0
-#define MXRT1050_IOMUXC_GPIO_B0_10_SRC_BT_CFG06 0x164 0x354 0x000 0x6 0x0
-
-#define MXRT1050_IOMUXC_GPIO_B0_11_LCD_DATA07 0x168 0x358 0x000 0x0 0x0
-#define MXRT1050_IOMUXC_GPIO_B0_11_TMR4_TIMER2 0x168 0x358 0x000 0x1 0x0
-#define MXRT1050_IOMUXC_GPIO_B0_11_FLEXPWM2_PWM2_B 0x168 0x358 0x490 0x2 0x1
-#define MXRT1050_IOMUXC_GPIO_B0_11_SAI1_TX_DATA02 0x168 0x358 0x59C 0x3 0x1
-#define MXRT1050_IOMUXC_GPIO_B0_11_FLEXIO2_D11 0x168 0x358 0x000 0x4 0x0
-#define MXRT1050_IOMUXC_GPIO_B0_11_GPIO2_IO11 0x168 0x358 0x000 0x5 0x0
-#define MXRT1050_IOMUXC_GPIO_B0_11_SRC_BT_CFG07 0x168 0x358 0x000 0x6 0x0
-
-#define MXRT1050_IOMUXC_GPIO_B0_12_LCD_DATA08 0x16C 0x35C 0x000 0x0 0x0
-#define MXRT1050_IOMUXC_GPIO_B0_12_XBAR_INOUT10 0x16C 0x35C 0x000 0x1 0x0
-#define MXRT1050_IOMUXC_GPIO_B0_12_ARM_TRACE_CLK 0x16C 0x35C 0x000 0x2 0x0
-#define MXRT1050_IOMUXC_GPIO_B0_12_SAI1_TX_DATA01 0x16C 0x35C 0x5A0 0x3 0x1
-#define MXRT1050_IOMUXC_GPIO_B0_12_FLEXIO2_D12 0x16C 0x35C 0x000 0x4 0x0
-#define MXRT1050_IOMUXC_GPIO_B0_12_GPIO2_IO12 0x16C 0x35C 0x000 0x5 0x0
-#define MXRT1050_IOMUXC_GPIO_B0_12_SRC_BT_CFG08 0x16C 0x35C 0x000 0x6 0x0
-
-#define MXRT1050_IOMUXC_GPIO_B0_13_LCD_DATA09 0x170 0x360 0x000 0x0 0x0
-#define MXRT1050_IOMUXC_GPIO_B0_13_XBAR_INOUT11 0x170 0x360 0x000 0x1 0x0
-#define MXRT1050_IOMUXC_GPIO_B0_13_ARM_TRACE_SWO 0x170 0x360 0x000 0x2 0x0
-#define MXRT1050_IOMUXC_GPIO_B0_13_SAI1_MCLK 0x170 0x360 0x58C 0x3 0x2
-#define MXRT1050_IOMUXC_GPIO_B0_13_FLEXIO2_D13 0x170 0x360 0x000 0x4 0x0
-#define MXRT1050_IOMUXC_GPIO_B0_13_GPIO2_IO13 0x170 0x360 0x000 0x5 0x0
-#define MXRT1050_IOMUXC_GPIO_B0_13_SRC_BT_CFG09 0x170 0x360 0x000 0x6 0x0
-
-#define MXRT1050_IOMUXC_GPIO_B0_14_LCD_DATA10 0x174 0x364 0x000 0x0 0x0
-#define MXRT1050_IOMUXC_GPIO_B0_14_XBAR_INOUT12 0x174 0x364 0x000 0x1 0x0
-#define MXRT1050_IOMUXC_GPIO_B0_14_ARM_CM7_TXEV 0x174 0x364 0x000 0x2 0x0
-#define MXRT1050_IOMUXC_GPIO_B0_14_SAI1_RX_SYNC 0x174 0x364 0x5A4 0x3 0x2
-#define MXRT1050_IOMUXC_GPIO_B0_14_FLEXIO2_D14 0x174 0x364 0x000 0x4 0x0
-#define MXRT1050_IOMUXC_GPIO_B0_14_GPIO2_IO14 0x174 0x364 0x000 0x5 0x0
-#define MXRT1050_IOMUXC_GPIO_B0_14_SRC_BT_CFG10 0x174 0x364 0x000 0x6 0x0
-
-#define MXRT1050_IOMUXC_GPIO_B0_15_LCD_DATA11 0x178 0x368 0x000 0x0 0x0
-#define MXRT1050_IOMUXC_GPIO_B0_15_XBAR_INOUT13 0x178 0x368 0x000 0x1 0x0
-#define MXRT1050_IOMUXC_GPIO_B0_15_ARM_CM7_RXEV 0x178 0x368 0x000 0x2 0x0
-#define MXRT1050_IOMUXC_GPIO_B0_15_SAI1_RX_BCLK 0x178 0x368 0x590 0x3 0x2
-#define MXRT1050_IOMUXC_GPIO_B0_15_FLEXIO2_D15 0x178 0x368 0x000 0x4 0x0
-#define MXRT1050_IOMUXC_GPIO_B0_15_GPIO2_IO15 0x178 0x368 0x000 0x5 0x0
-#define MXRT1050_IOMUXC_GPIO_B0_15_SRC_BT_CFG11 0x178 0x368 0x000 0x6 0x0
-
-#define MXRT1050_IOMUXC_GPIO_B1_00_LCD_DATA12 0x17C 0x36C 0x000 0x0 0x0
-#define MXRT1050_IOMUXC_GPIO_B1_00_XBAR_INOUT14 0x17C 0x36C 0x644 0x1 0x1
-#define MXRT1050_IOMUXC_GPIO_B1_00_LPUART4_TXD 0x17C 0x36C 0x544 0x2 0x2
-#define MXRT1050_IOMUXC_GPIO_B1_00_SAI1_RX_DATA00 0x17C 0x36C 0x594 0x3 0x2
-#define MXRT1050_IOMUXC_GPIO_B1_00_FLEXIO2_D16 0x17C 0x36C 0x000 0x4 0x0
-#define MXRT1050_IOMUXC_GPIO_B1_00_GPIO2_IO16 0x17C 0x36C 0x000 0x5 0x0
-#define MXRT1050_IOMUXC_GPIO_B1_00_FLEXPWM1_PWM3_A 0x17C 0x36C 0x454 0x6 0x4
-
-#define MXRT1050_IOMUXC_GPIO_B1_01_LCD_DATA13 0x180 0x370 0x000 0x0 0x0
-#define MXRT1050_IOMUXC_GPIO_B1_01_XBAR_INOUT15 0x180 0x370 0x648 0x1 0x1
-#define MXRT1050_IOMUXC_GPIO_B1_01_LPUART4_RXD 0x180 0x370 0x540 0x2 0x2
-#define MXRT1050_IOMUXC_GPIO_B1_01_SAI1_TX_DATA00 0x180 0x370 0x000 0x3 0x0
-#define MXRT1050_IOMUXC_GPIO_B1_01_FLEXIO2_D17 0x180 0x370 0x000 0x4 0x0
-#define MXRT1050_IOMUXC_GPIO_B1_01_GPIO2_IO17 0x180 0x370 0x000 0x5 0x0
-#define MXRT1050_IOMUXC_GPIO_B1_01_FLEXPWM1_PWM3_B 0x180 0x370 0x464 0x6 0x4
-
-#define MXRT1050_IOMUXC_GPIO_B1_02_LCD_DATA14 0x184 0x374 0x000 0x0 0x0
-#define MXRT1050_IOMUXC_GPIO_B1_02_XBAR_INOUT16 0x184 0x374 0x64C 0x1 0x1
-#define MXRT1050_IOMUXC_GPIO_B1_02_LPSPI4_PCS2 0x184 0x374 0x000 0x2 0x0
-#define MXRT1050_IOMUXC_GPIO_B1_02_SAI1_TX_BCLK 0x184 0x374 0x5A8 0x3 0x2
-#define MXRT1050_IOMUXC_GPIO_B1_02_FLEXIO2_D18 0x184 0x374 0x000 0x4 0x0
-#define MXRT1050_IOMUXC_GPIO_B1_02_GPIO2_IO18 0x184 0x374 0x000 0x5 0x0
-#define MXRT1050_IOMUXC_GPIO_B1_02_FLEXPWM2_PWM3_A 0x184 0x374 0x000 0x6 0x0
-
-#define MXRT1050_IOMUXC_GPIO_B1_03_LCD_DATA15 0x188 0x378 0x000 0x0 0x0
-#define MXRT1050_IOMUXC_GPIO_B1_03_XBAR_INOUT17 0x188 0x378 0x62C 0x1 0x3
-#define MXRT1050_IOMUXC_GPIO_B1_03_LPSPI4_PCS1 0x188 0x378 0x000 0x2 0x0
-#define MXRT1050_IOMUXC_GPIO_B1_03_SAI1_TX_SYNC 0x188 0x378 0x5AC 0x3 0x2
-#define MXRT1050_IOMUXC_GPIO_B1_03_FLEXIO2_D19 0x188 0x378 0x000 0x4 0x0
-#define MXRT1050_IOMUXC_GPIO_B1_03_GPIO2_IO19 0x188 0x378 0x000 0x5 0x0
-#define MXRT1050_IOMUXC_GPIO_B1_03_FLEXPWM2_PWM3_B 0x188 0x378 0x484 0x6 0x3
-
-#define MXRT1050_IOMUXC_GPIO_B1_04_LCD_DATA16 0x18C 0x37C 0x000 0x0 0x0
-#define MXRT1050_IOMUXC_GPIO_B1_04_LPSPI4_PCS0 0x18C 0x37C 0x51C 0x1 0x1
-#define MXRT1050_IOMUXC_GPIO_B1_04_CSI_DATA15 0x18C 0x37C 0x000 0x2 0x0
-#define MXRT1050_IOMUXC_GPIO_B1_04_ENET_RX_DATA00 0x18C 0x37C 0x434 0x3 0x1
-#define MXRT1050_IOMUXC_GPIO_B1_04_FLEXIO2_D20 0x18C 0x37C 0x000 0x4 0x0
-#define MXRT1050_IOMUXC_GPIO_B1_04_GPIO2_IO20 0x18C 0x37C 0x000 0x5 0x0
-
-#define MXRT1050_IOMUXC_GPIO_B1_05_LCD_DATA17 0x190 0x380 0x000 0x0 0x0
-#define MXRT1050_IOMUXC_GPIO_B1_05_LPSPI4_SDI 0x190 0x380 0x524 0x1 0x1
-#define MXRT1050_IOMUXC_GPIO_B1_05_CSI_DATA14 0x190 0x380 0x000 0x2 0x0
-#define MXRT1050_IOMUXC_GPIO_B1_05_ENET_RX_DATA01 0x190 0x380 0x438 0x3 0x1
-#define MXRT1050_IOMUXC_GPIO_B1_05_FLEXIO2_D21 0x190 0x380 0x000 0x4 0x0
-#define MXRT1050_IOMUXC_GPIO_B1_05_GPIO2_IO21 0x190 0x380 0x000 0x5 0x0
-
-#define MXRT1050_IOMUXC_GPIO_B1_06_LCD_DATA18 0x194 0x384 0x000 0x0 0x0
-#define MXRT1050_IOMUXC_GPIO_B1_06_LPSPI4_SDO 0x194 0x384 0x528 0x1 0x1
-#define MXRT1050_IOMUXC_GPIO_B1_06_CSI_DATA13 0x194 0x384 0x000 0x2 0x0
-#define MXRT1050_IOMUXC_GPIO_B1_06_ENET_RX_EN 0x194 0x384 0x43C 0x3 0x1
-#define MXRT1050_IOMUXC_GPIO_B1_06_FLEXIO2_D22 0x194 0x384 0x000 0x4 0x0
-#define MXRT1050_IOMUXC_GPIO_B1_06_GPIO2_IO22 0x194 0x384 0x000 0x5 0x0
-
-#define MXRT1050_IOMUXC_GPIO_B1_07_LCD_DATA19 0x198 0x388 0x000 0x0 0x0
-#define MXRT1050_IOMUXC_GPIO_B1_07_LPSPI4_SCK 0x198 0x388 0x520 0x1 0x1
-#define MXRT1050_IOMUXC_GPIO_B1_07_CSI_DATA12 0x198 0x388 0x000 0x2 0x0
-#define MXRT1050_IOMUXC_GPIO_B1_07_ENET_TX_DATA00 0x198 0x388 0x000 0x3 0x0
-#define MXRT1050_IOMUXC_GPIO_B1_07_FLEXIO2_D23 0x198 0x388 0x000 0x4 0x0
-#define MXRT1050_IOMUXC_GPIO_B1_07_GPIO2_IO23 0x198 0x388 0x000 0x5 0x0
-
-#define MXRT1050_IOMUXC_GPIO_B1_08_LCD_DATA20 0x19C 0x38C 0x000 0x0 0x0
-#define MXRT1050_IOMUXC_GPIO_B1_08_TMR1_TIMER3 0x19C 0x38C 0x000 0x1 0x0
-#define MXRT1050_IOMUXC_GPIO_B1_08_CSI_DATA11 0x19C 0x38C 0x000 0x2 0x0
-#define MXRT1050_IOMUXC_GPIO_B1_08_ENET_TX_DATA01 0x19C 0x38C 0x000 0x3 0x0
-#define MXRT1050_IOMUXC_GPIO_B1_08_FLEXIO2_D24 0x19C 0x38C 0x000 0x4 0x0
-#define MXRT1050_IOMUXC_GPIO_B1_08_GPIO2_IO24 0x19C 0x38C 0x000 0x5 0x0
-#define MXRT1050_IOMUXC_GPIO_B1_08_FLEXCAN2_TX 0x19C 0x38C 0x000 0x6 0x0
-
-#define MXRT1050_IOMUXC_GPIO_B1_09_LCD_DATA21 0x1A0 0x390 0x000 0x0 0x0
-#define MXRT1050_IOMUXC_GPIO_B1_09_TMR2_TIMER3 0x1A0 0x390 0x578 0x1 0x1
-#define MXRT1050_IOMUXC_GPIO_B1_09_CSI_DATA10 0x1A0 0x390 0x000 0x2 0x0
-#define MXRT1050_IOMUXC_GPIO_B1_09_ENET_TX_EN 0x1A0 0x390 0x000 0x3 0x0
-#define MXRT1050_IOMUXC_GPIO_B1_09_FLEXIO2_D25 0x1A0 0x390 0x000 0x4 0x0
-#define MXRT1050_IOMUXC_GPIO_B1_09_GPIO2_IO25 0x1A0 0x390 0x000 0x5 0x0
-#define MXRT1050_IOMUXC_GPIO_B1_09_FLEXCAN2_RX 0x1A0 0x390 0x450 0x6 0x3
-
-#define MXRT1050_IOMUXC_GPIO_B1_10_LCD_DATA22 0x1A4 0x394 0x000 0x0 0x0
-#define MXRT1050_IOMUXC_GPIO_B1_10_TMR3_TIMER3 0x1A4 0x394 0x588 0x1 0x2
-#define MXRT1050_IOMUXC_GPIO_B1_10_CSI_DATA00 0x1A4 0x394 0x000 0x2 0x0
-#define MXRT1050_IOMUXC_GPIO_B1_10_ENET_TX_CLK 0x1A4 0x394 0x448 0x3 0x1
-#define MXRT1050_IOMUXC_GPIO_B1_10_FLEXIO2_D26 0x1A4 0x394 0x000 0x4 0x0
-#define MXRT1050_IOMUXC_GPIO_B1_10_GPIO2_IO26 0x1A4 0x394 0x000 0x5 0x0
-#define MXRT1050_IOMUXC_GPIO_B1_10_ENET_REF_CLK 0x1A4 0x394 0x42C 0x6 0x1
-
-#define MXRT1050_IOMUXC_GPIO_B1_11_LCD_DATA23 0x1A8 0x398 0x000 0x0 0x0
-#define MXRT1050_IOMUXC_GPIO_B1_11_TMR4_TIMER3 0x1A8 0x398 0x000 0x1 0x0
-#define MXRT1050_IOMUXC_GPIO_B1_11_CSI_DATA01 0x1A8 0x398 0x000 0x2 0x0
-#define MXRT1050_IOMUXC_GPIO_B1_11_ENET_RX_ER 0x1A8 0x398 0x440 0x3 0x1
-#define MXRT1050_IOMUXC_GPIO_B1_11_FLEXIO2_D27 0x1A8 0x398 0x000 0x4 0x0
-#define MXRT1050_IOMUXC_GPIO_B1_11_GPIO2_IO27 0x1A8 0x398 0x000 0x5 0x0
-#define MXRT1050_IOMUXC_GPIO_B1_11_LPSPI4_PCS3 0x1A8 0x398 0x000 0x6 0x0
-
-#define MXRT1050_IOMUXC_GPIO_B1_12_LPUART5_TXD 0x1AC 0x39C 0x54C 0x1 0x1
-#define MXRT1050_IOMUXC_GPIO_B1_12_CSI_PIXCLK 0x1AC 0x39C 0x424 0x2 0x1
-#define MXRT1050_IOMUXC_GPIO_B1_12_ENET_1588_EVENT0_IN 0x1AC 0x39C 0x444 0x3 0x2
-#define MXRT1050_IOMUXC_GPIO_B1_12_FLEXIO2_D28 0x1AC 0x39C 0x000 0x4 0x0
-#define MXRT1050_IOMUXC_GPIO_B1_12_GPIO2_IO28 0x1AC 0x39C 0x000 0x5 0x0
-#define MXRT1050_IOMUXC_GPIO_B1_12_USDHC1_CD_B 0x1AC 0x39C 0x5D4 0x6 0x2
-
-#define MXRT1050_IOMUXC_GPIO_B1_13_WDOG1_B 0x1B0 0x3A0 0x000 0x0 0x0
-#define MXRT1050_IOMUXC_GPIO_B1_13_LPUART5_RXD 0x1B0 0x3A0 0x548 0x1 0x1
-#define MXRT1050_IOMUXC_GPIO_B1_13_CSI_VSYNC 0x1B0 0x3A0 0x428 0x2 0x2
-#define MXRT1050_IOMUXC_GPIO_B1_13_ENET_1588_EVENT0_OUT 0x1B0 0x3A0 0x000 0x3 0x0
-#define MXRT1050_IOMUXC_GPIO_B1_13_FLEXIO2_D29 0x1B0 0x3A0 0x000 0x4 0x0
-#define MXRT1050_IOMUXC_GPIO_B1_13_GPIO2_IO29 0x1B0 0x3A0 0x000 0x5 0x0
-#define MXRT1050_IOMUXC_GPIO_B1_13_USDHC1_WP 0x1B0 0x3A0 0x5D8 0x6 0x3
-
-#define MXRT1050_IOMUXC_GPIO_B1_14_ENET_MDC 0x1B4 0x3A4 0x000 0x0 0x0
-#define MXRT1050_IOMUXC_GPIO_B1_14_FLEXPWM4_PWM2_A 0x1B4 0x3A4 0x49C 0x1 0x1
-#define MXRT1050_IOMUXC_GPIO_B1_14_CSI_HSYNC 0x1B4 0x3A4 0x420 0x2 0x2
-#define MXRT1050_IOMUXC_GPIO_B1_14_XBAR_INOUT02 0x1B4 0x3A4 0x60C 0x3 0x1
-#define MXRT1050_IOMUXC_GPIO_B1_14_FLEXIO2_D30 0x1B4 0x3A4 0x000 0x4 0x0
-#define MXRT1050_IOMUXC_GPIO_B1_14_GPIO2_IO30 0x1B4 0x3A4 0x000 0x5 0x0
-#define MXRT1050_IOMUXC_GPIO_B1_14_USDHC1_VSELECT 0x1B4 0x3A4 0x000 0x6 0x0
-
-#define MXRT1050_IOMUXC_GPIO_B1_15_ENET_MDIO 0x1B8 0x3A8 0x430 0x0 0x2
-#define MXRT1050_IOMUXC_GPIO_B1_15_FLEXPWM4_PWM3_A 0x1B8 0x3A8 0x4A0 0x1 0x1
-#define MXRT1050_IOMUXC_GPIO_B1_15_CSI_MCLK 0x1B8 0x3A8 0x000 0x2 0x0
-#define MXRT1050_IOMUXC_GPIO_B1_15_XBAR_INOUT03 0x1B8 0x3A8 0x610 0x3 0x1
-#define MXRT1050_IOMUXC_GPIO_B1_15_FLEXIO2_D31 0x1B8 0x3A8 0x000 0x4 0x0
-#define MXRT1050_IOMUXC_GPIO_B1_15_GPIO2_IO31 0x1B8 0x3A8 0x000 0x5 0x0
-#define MXRT1050_IOMUXC_GPIO_B1_15_USDHC1_RESET_B 0x1B8 0x3A8 0x000 0x6 0x0
-
-#define MXRT1050_IOMUXC_GPIO_SD_B0_00_USDHC1_CMD 0x1BC 0x3AC 0x000 0x0 0x0
-#define MXRT1050_IOMUXC_GPIO_SD_B0_00_FLEXPWM1_PWM0_A 0x1BC 0x3AC 0x458 0x1 0x1
-#define MXRT1050_IOMUXC_GPIO_SD_B0_00_LPI2C3_SCL 0x1BC 0x3AC 0x4DC 0x2 0x1
-#define MXRT1050_IOMUXC_GPIO_SD_B0_00_XBAR_INOUT04 0x1BC 0x3AC 0x614 0x3 0x1
-#define MXRT1050_IOMUXC_GPIO_SD_B0_00_LPSPI1_SCK 0x1BC 0x3AC 0x4F0 0x4 0x1
-#define MXRT1050_IOMUXC_GPIO_SD_B0_00_GPIO3_IO12 0x1BC 0x3AC 0x000 0x5 0x0
-#define MXRT1050_IOMUXC_GPIO_SD_B0_00_FLEXSPI_A_SS1_B 0x1BC 0x3AC 0x000 0x6 0x0
-
-#define MXRT1050_IOMUXC_GPIO_SD_B0_01_USDHC1_CLK 0x1C0 0x3B0 0x000 0x0 0x0
-#define MXRT1050_IOMUXC_GPIO_SD_B0_01_FLEXPWM1_PWM0_B 0x1C0 0x3B0 0x000 0x1 0x0
-#define MXRT1050_IOMUXC_GPIO_SD_B0_01_LPI2C3_SDA 0x1C0 0x3B0 0x4E0 0x2 0x1
-#define MXRT1050_IOMUXC_GPIO_SD_B0_01_XBAR_INOUT05 0x1C0 0x3B0 0x618 0x3 0x1
-#define MXRT1050_IOMUXC_GPIO_SD_B0_01_LPSPI1_PCS0 0x1C0 0x3B0 0x4EC 0x4 0x0
-#define MXRT1050_IOMUXC_GPIO_SD_B0_01_GPIO3_IO13 0x1C0 0x3B0 0x000 0x5 0x0
-#define MXRT1050_IOMUXC_GPIO_SD_B0_01_FLEXSPI_B_SS1_B 0x1C0 0x3B0 0x000 0x6 0x0
-
-#define MXRT1050_IOMUXC_GPIO_SD_B0_02_USDHC1_DATA0 0x1C4 0x3B4 0x000 0x0 0x0
-#define MXRT1050_IOMUXC_GPIO_SD_B0_02_FLEXPWM1_PWM1_A 0x1C4 0x3B4 0x45C 0x1 0x1
-#define MXRT1050_IOMUXC_GPIO_SD_B0_02_LPUART8_CTS_B 0x1C4 0x3B4 0x000 0x2 0x0
-#define MXRT1050_IOMUXC_GPIO_SD_B0_02_XBAR_INOUT06 0x1C4 0x3B4 0x61C 0x3 0x1
-#define MXRT1050_IOMUXC_GPIO_SD_B0_02_LPSPI1_SDO 0x1C4 0x3B4 0x4F8 0x4 0x1
-#define MXRT1050_IOMUXC_GPIO_SD_B0_02_GPIO3_IO14 0x1C4 0x3B4 0x000 0x5 0x0
-
-#define MXRT1050_IOMUXC_GPIO_SD_B0_03_USDHC1_DATA1 0x1C8 0x3B8 0x000 0x0 0x0
-#define MXRT1050_IOMUXC_GPIO_SD_B0_03_FLEXPWM1_PWM1_B 0x1C8 0x3B8 0x46C 0x1 0x1
-#define MXRT1050_IOMUXC_GPIO_SD_B0_03_LPUART8_RTS_B 0x1C8 0x3B8 0x000 0x2 0x0
-#define MXRT1050_IOMUXC_GPIO_SD_B0_03_XBAR_INOUT07 0x1C8 0x3B8 0x620 0x3 0x1
-#define MXRT1050_IOMUXC_GPIO_SD_B0_03_LPSPI1_SDI 0x1C8 0x3B8 0x4F4 0x4 0x1
-#define MXRT1050_IOMUXC_GPIO_SD_B0_03_GPIO3_IO15 0x1C8 0x3B8 0x000 0x5 0x0
-
-#define MXRT1050_IOMUXC_GPIO_SD_B0_04_USDHC1_DATA2 0x1CC 0x3BC 0x000 0x0 0x0
-#define MXRT1050_IOMUXC_GPIO_SD_B0_04_FLEXPWM1_PWM2_A 0x1CC 0x3BC 0x460 0x1 0x1
-#define MXRT1050_IOMUXC_GPIO_SD_B0_04_LPUART8_TXD 0x1CC 0x3BC 0x564 0x2 0x0
-#define MXRT1050_IOMUXC_GPIO_SD_B0_04_XBAR_INOUT08 0x1CC 0x3BC 0x624 0x3 0x1
-#define MXRT1050_IOMUXC_GPIO_SD_B0_04_FLEXSPI_B_SS0_B 0x1CC 0x3BC 0x000 0x4 0x0
-#define MXRT1050_IOMUXC_GPIO_SD_B0_04_GPIO3_IO16 0x1CC 0x3BC 0x000 0x5 0x0
-#define MXRT1050_IOMUXC_GPIO_SD_B0_04_CCM_CLKO1 0x1CC 0x3BC 0x000 0x6 0x0
-
-#define MXRT1050_IOMUXC_GPIO_SD_B0_05_USDHC1_DATA3 0x1D0 0x3C0 0x000 0x0 0x0
-#define MXRT1050_IOMUXC_GPIO_SD_B0_05_FLEXPWM1_PWM2_B 0x1D0 0x3C0 0x470 0x1 0x1
-#define MXRT1050_IOMUXC_GPIO_SD_B0_05_LPUART8_RXD 0x1D0 0x3C0 0x560 0x2 0x0
-#define MXRT1050_IOMUXC_GPIO_SD_B0_05_XBAR_INOUT09 0x1D0 0x3C0 0x628 0x3 0x1
-#define MXRT1050_IOMUXC_GPIO_SD_B0_05_FLEXSPI_B_DQS 0x1D0 0x3C0 0x000 0x4 0x0
-#define MXRT1050_IOMUXC_GPIO_SD_B0_05_GPIO3_IO17 0x1D0 0x3C0 0x000 0x5 0x0
-#define MXRT1050_IOMUXC_GPIO_SD_B0_05_CCM_CLKO2 0x1D0 0x3C0 0x000 0x6 0x0
-
-#define MXRT1050_IOMUXC_GPIO_SD_B1_00_USDHC2_DATA3 0x1D4 0x3C4 0x5F4 0x0 0x0
-#define MXRT1050_IOMUXC_GPIO_SD_B1_00_FLEXSPI_B_DATA3 0x1D4 0x3C4 0x4C4 0x1 0x0
-#define MXRT1050_IOMUXC_GPIO_SD_B1_00_FLEXPWM1_PWM3_A 0x1D4 0x3C4 0x454 0x2 0x0
-#define MXRT1050_IOMUXC_GPIO_SD_B1_00_SAI1_TX_DATA03 0x1D4 0x3C4 0x598 0x3 0x0
-#define MXRT1050_IOMUXC_GPIO_SD_B1_00_LPUART4_TXD 0x1D4 0x3C4 0x544 0x4 0x0
-#define MXRT1050_IOMUXC_GPIO_SD_B1_00_GPIO3_IO00 0x1D4 0x3C4 0x000 0x5 0x0
-
-#define MXRT1050_IOMUXC_GPIO_SD_B1_01_USDHC2_DATA2 0x1D8 0x3C8 0x5F0 0x0 0x0
-#define MXRT1050_IOMUXC_GPIO_SD_B1_01_FLEXSPI_B_DATA2 0x1D8 0x3C8 0x4C0 0x1 0x0
-#define MXRT1050_IOMUXC_GPIO_SD_B1_01_FLEXPWM1_PWM3_B 0x1D8 0x3C8 0x464 0x2 0x0
-#define MXRT1050_IOMUXC_GPIO_SD_B1_01_SAI1_TX_DATA02 0x1D8 0x3C8 0x59C 0x3 0x0
-#define MXRT1050_IOMUXC_GPIO_SD_B1_01_LPUART4_RXD 0x1D8 0x3C8 0x540 0x4 0x0
-#define MXRT1050_IOMUXC_GPIO_SD_B1_01_GPIO3_IO01 0x1D8 0x3C8 0x000 0x5 0x0
-
-#define MXRT1050_IOMUXC_GPIO_SD_B1_02_USDHC2_DATA1 0x1DC 0x3CC 0x5EC 0x0 0x0
-#define MXRT1050_IOMUXC_GPIO_SD_B1_02_FLEXSPI_B_DATA1 0x1DC 0x3CC 0x4BC 0x1 0x0
-#define MXRT1050_IOMUXC_GPIO_SD_B1_02_FLEXPWM2_PWM3_A 0x1DC 0x3CC 0x000 0x2 0x0
-#define MXRT1050_IOMUXC_GPIO_SD_B1_02_SAI1_TX_DATA01 0x1DC 0x3CC 0x5A0 0x3 0x0
-#define MXRT1050_IOMUXC_GPIO_SD_B1_02_FLEXCAN1_TX 0x1DC 0x3CC 0x000 0x4 0x0
-#define MXRT1050_IOMUXC_GPIO_SD_B1_02_GPIO3_IO02 0x1DC 0x3CC 0x000 0x5 0x0
-#define MXRT1050_IOMUXC_GPIO_SD_B1_02_CCM_WAIT 0x1DC 0x3CC 0x000 0x6 0x0
-
-#define MXRT1050_IOMUXC_GPIO_SD_B1_03_USDHC2_DATA0 0x1E0 0x3D0 0x5E8 0x0 0x0
-#define MXRT1050_IOMUXC_GPIO_SD_B1_03_FLEXSPI_B_DATA0 0x1E0 0x3D0 0x4B8 0x1 0x0
-#define MXRT1050_IOMUXC_GPIO_SD_B1_03_FLEXPWM2_PWM3_B 0x1E0 0x3D0 0x484 0x2 0x0
-#define MXRT1050_IOMUXC_GPIO_SD_B1_03_SAI1_MCLK 0x1E0 0x3D0 0x58C 0x3 0x0
-#define MXRT1050_IOMUXC_GPIO_SD_B1_03_FLEXCAN1_RX 0x1E0 0x3D0 0x44C 0x4 0x0
-#define MXRT1050_IOMUXC_GPIO_SD_B1_03_GPIO3_IO03 0x1E0 0x3D0 0x000 0x5 0x0
-#define MXRT1050_IOMUXC_GPIO_SD_B1_03_CCM_PMIC_READY 0x1E0 0x3D0 0x3FC 0x6 0x0
-
-#define MXRT1050_IOMUXC_GPIO_SD_B1_04_USDHC2_CLK 0x1E4 0x3D4 0x5DC 0x0 0x0
-#define MXRT1050_IOMUXC_GPIO_SD_B1_04_FLEXSPI_B_SCLK 0x1E4 0x3D4 0x000 0x1 0x0
-#define MXRT1050_IOMUXC_GPIO_SD_B1_04_LPI2C1_SCL 0x1E4 0x3D4 0x4CC 0x2 0x0
-#define MXRT1050_IOMUXC_GPIO_SD_B1_04_SAI1_RX_SYNC 0x1E4 0x3D4 0x5A4 0x3 0x0
-#define MXRT1050_IOMUXC_GPIO_SD_B1_04_FLEXCAN1_A_SS1_B 0x1E4 0x3D4 0x000 0x4 0x0
-#define MXRT1050_IOMUXC_GPIO_SD_B1_04_GPIO3_IO04 0x1E4 0x3D4 0x000 0x5 0x0
-#define MXRT1050_IOMUXC_GPIO_SD_B1_04_CCM_STOP 0x1E4 0x3D4 0x000 0x6 0x0
-
-#define MXRT1050_IOMUXC_GPIO_SD_B1_05_USDHC2_CMD 0x1E8 0x3D8 0x5E4 0x0 0x0
-#define MXRT1050_IOMUXC_GPIO_SD_B1_05_FLEXSPI_A_DQS 0x1E8 0x3D8 0x4A4 0x1 0x0
-#define MXRT1050_IOMUXC_GPIO_SD_B1_05_LPI2C1_SDA 0x1E8 0x3D8 0x4D0 0x2 0x0
-#define MXRT1050_IOMUXC_GPIO_SD_B1_05_SAI1_RX_BCLK 0x1E8 0x3D8 0x590 0x3 0x0
-#define MXRT1050_IOMUXC_GPIO_SD_B1_05_FLEXCAN1_B_SS0_B 0x1E8 0x3D8 0x000 0x4 0x0
-#define MXRT1050_IOMUXC_GPIO_SD_B1_05_GPIO3_IO05 0x1E8 0x3D8 0x000 0x5 0x0
-
-#define MXRT1050_IOMUXC_GPIO_SD_B1_06_USDHC2_RESET_B 0x1EC 0x3DC 0x000 0x0 0x0
-#define MXRT1050_IOMUXC_GPIO_SD_B1_06_FLEXSPI_A_SS0_B 0x1EC 0x3DC 0x000 0x1 0x0
-#define MXRT1050_IOMUXC_GPIO_SD_B1_06_LPUART7_CTS_B 0x1EC 0x3DC 0x000 0x2 0x0
-#define MXRT1050_IOMUXC_GPIO_SD_B1_06_SAI1_RX_DATA00 0x1EC 0x3DC 0x594 0x3 0x0
-#define MXRT1050_IOMUXC_GPIO_SD_B1_06_LPSPI2_PCS0 0x1EC 0x3DC 0x4FC 0x4 0x0
-#define MXRT1050_IOMUXC_GPIO_SD_B1_06_GPIO3_IO06 0x1EC 0x3DC 0x000 0x5 0x0
-
-#define MXRT1050_IOMUXC_GPIO_SD_B1_07_SEMC_CSX1 0x1F0 0x3E0 0x000 0x0 0x0
-#define MXRT1050_IOMUXC_GPIO_SD_B1_07_FLEXSPI_A_SCLK 0x1F0 0x3E0 0x4C8 0x1 0x0
-#define MXRT1050_IOMUXC_GPIO_SD_B1_07_LPUART7_RTS_B 0x1F0 0x3E0 0x000 0x2 0x0
-#define MXRT1050_IOMUXC_GPIO_SD_B1_07_SAI1_TX_DATA00 0x1F0 0x3E0 0x000 0x3 0x0
-#define MXRT1050_IOMUXC_GPIO_SD_B1_07_LPSPI2_SCK 0x1F0 0x3E0 0x500 0x4 0x0
-#define MXRT1050_IOMUXC_GPIO_SD_B1_07_GPIO3_IO07 0x1F0 0x3E0 0x000 0x5 0x0
-#define MXRT1050_IOMUXC_GPIO_SD_B1_07_CCM_REF_EN_B 0x1F0 0x3E0 0x000 0x6 0x0
-
-#define MXRT1050_IOMUXC_GPIO_SD_B1_08_USDHC2_DATA4 0x1F4 0x3E4 0x5F8 0x0 0x0
-#define MXRT1050_IOMUXC_GPIO_SD_B1_08_FLEXSPI_A_DATA0 0x1F4 0x3E4 0x4A8 0x1 0x0
-#define MXRT1050_IOMUXC_GPIO_SD_B1_08_LPUART7_TXD 0x1F4 0x3E4 0x55C 0x2 0x0
-#define MXRT1050_IOMUXC_GPIO_SD_B1_08_SAI1_TX_BLCK 0x1F4 0x3E4 0x5A8 0x3 0x0
-#define MXRT1050_IOMUXC_GPIO_SD_B1_08_LPSPI2_SDO 0x1F4 0x3E4 0x508 0x4 0x0
-#define MXRT1050_IOMUXC_GPIO_SD_B1_08_GPIO3_IO08 0x1F4 0x3E4 0x000 0x5 0x0
-#define MXRT1050_IOMUXC_GPIO_SD_B1_08_SEMC_CSX2 0x1F4 0x3E4 0x000 0x6 0x0
-
-#define MXRT1050_IOMUXC_GPIO_SD_B1_09_USDHC2_DATA5 0x1F8 0x3E8 0x5FC 0x0 0x0
-#define MXRT1050_IOMUXC_GPIO_SD_B1_09_FLEXSPI_A_DATA1 0x1F8 0x3E8 0x4AC 0x1 0x0
-#define MXRT1050_IOMUXC_GPIO_SD_B1_09_LPUART7_RXD 0x1F8 0x3E8 0x558 0x2 0x0
-#define MXRT1050_IOMUXC_GPIO_SD_B1_09_SAI1_TX_SYNC 0x1F8 0x3E8 0x5AC 0x3 0x0
-#define MXRT1050_IOMUXC_GPIO_SD_B1_09_LPSPI2_SDI 0x1F8 0x3E8 0x504 0x4 0x0
-#define MXRT1050_IOMUXC_GPIO_SD_B1_09_GPIO3_IO09 0x1F8 0x3E8 0x000 0x5 0x0
-
-#define MXRT1050_IOMUXC_GPIO_SD_B1_10_USDHC2_DATA6 0x1FC 0x3EC 0x600 0x0 0x0
-#define MXRT1050_IOMUXC_GPIO_SD_B1_10_FLEXSPI_A_DATA2 0x1FC 0x3EC 0x4B0 0x1 0x0
-#define MXRT1050_IOMUXC_GPIO_SD_B1_10_LPUART2_RXD 0x1FC 0x3EC 0x52C 0x2 0x0
-#define MXRT1050_IOMUXC_GPIO_SD_B1_10_LPI2C2_SDA 0x1FC 0x3EC 0x4D8 0x3 0x0
-#define MXRT1050_IOMUXC_GPIO_SD_B1_10_LPSPI2_PCS2 0x1FC 0x3EC 0x000 0x4 0x0
-#define MXRT1050_IOMUXC_GPIO_SD_B1_10_GPIO3_IO10 0x1FC 0x3EC 0x000 0x5 0x0
-
-#define MXRT1050_IOMUXC_GPIO_SD_B1_11_USDHC2_DATA7 0x200 0x3F0 0x604 0x0 0x0
-#define MXRT1050_IOMUXC_GPIO_SD_B1_11_FLEXSPI_A_DATA3 0x200 0x3F0 0x4B4 0x1 0x0
-#define MXRT1050_IOMUXC_GPIO_SD_B1_11_LPUART2_TXD 0x200 0x3F0 0x530 0x2 0x0
-#define MXRT1050_IOMUXC_GPIO_SD_B1_11_LPI2C2_SCL 0x200 0x3F0 0x4D4 0x3 0x0
-#define MXRT1050_IOMUXC_GPIO_SD_B1_11_LPSPI2_PCS3 0x200 0x3F0 0x000 0x4 0x0
-#define MXRT1050_IOMUXC_GPIO_SD_B1_11_GPIO3_IO11 0x200 0x3F0 0x000 0x5 0x0
-
-#endif /* _DT_BINDINGS_PINCTRL_IMXRT1050_PINFUNC_H */
diff --git a/arch/arm/dts/imxrt1050.dtsi b/arch/arm/dts/imxrt1050.dtsi
deleted file mode 100644
index a25eae9..0000000
--- a/arch/arm/dts/imxrt1050.dtsi
+++ /dev/null
@@ -1,160 +0,0 @@
-// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
-/*
- * Copyright (C) 2019
- * Author(s): Giulio Benetti <giulio.benetti@benettiengineering.com>
- */
-
-#include "armv7-m.dtsi"
-#include <dt-bindings/interrupt-controller/arm-gic.h>
-#include <dt-bindings/clock/imxrt1050-clock.h>
-#include <dt-bindings/gpio/gpio.h>
-
-/ {
- #address-cells = <1>;
- #size-cells = <1>;
-
- clocks {
- osc: osc {
- compatible = "fixed-clock";
- #clock-cells = <0>;
- clock-frequency = <24000000>;
- };
-
- osc3M: osc3M {
- compatible = "fixed-clock";
- #clock-cells = <0>;
- clock-frequency = <3000000>;
- };
- };
-
- soc {
- lpuart1: serial@40184000 {
- compatible = "fsl,imxrt1050-lpuart", "fsl,imx7ulp-lpuart";
- reg = <0x40184000 0x4000>;
- interrupts = <20>;
- clocks = <&clks IMXRT1050_CLK_LPUART1>;
- clock-names = "ipg";
- status = "disabled";
- };
-
- iomuxc: pinctrl@401f8000 {
- compatible = "fsl,imxrt1050-iomuxc";
- reg = <0x401f8000 0x4000>;
- fsl,mux_mask = <0x7>;
- };
-
- anatop: anatop@400d8000 {
- compatible = "fsl,imxrt-anatop";
- reg = <0x400d8000 0x4000>;
- };
-
- clks: clock-controller@400fc000 {
- compatible = "fsl,imxrt1050-ccm";
- reg = <0x400fc000 0x4000>;
- interrupts = <95>, <96>;
- clocks = <&osc>;
- clock-names = "osc";
- #clock-cells = <1>;
- assigned-clocks = <&clks IMXRT1050_CLK_PLL1_BYPASS>,
- <&clks IMXRT1050_CLK_PLL1_BYPASS>,
- <&clks IMXRT1050_CLK_PLL2_BYPASS>,
- <&clks IMXRT1050_CLK_PLL3_BYPASS>,
- <&clks IMXRT1050_CLK_PLL3_PFD1_664_62M>,
- <&clks IMXRT1050_CLK_PLL2_PFD2_396M>;
- assigned-clock-parents = <&clks IMXRT1050_CLK_PLL1_REF_SEL>,
- <&clks IMXRT1050_CLK_PLL1_ARM>,
- <&clks IMXRT1050_CLK_PLL2_SYS>,
- <&clks IMXRT1050_CLK_PLL3_USB_OTG>,
- <&clks IMXRT1050_CLK_PLL3_USB_OTG>,
- <&clks IMXRT1050_CLK_PLL2_SYS>;
- };
-
- edma1: dma-controller@400e8000 {
- #dma-cells = <2>;
- compatible = "fsl,imx7ulp-edma";
- reg = <0x400e8000 0x4000>,
- <0x400ec000 0x4000>;
- dma-channels = <32>;
- interrupts = <0>, <1>, <2>, <3>, <4>, <5>, <6>, <7>, <8>,
- <9>, <10>, <11>, <12>, <13>, <14>, <15>, <16>;
- clock-names = "dma", "dmamux0";
- clocks = <&clks IMXRT1050_CLK_DMA>,
- <&clks IMXRT1050_CLK_DMA_MUX>;
- };
-
- usdhc1: mmc@402c0000 {
- compatible = "fsl,imxrt1050-usdhc", "fsl,imx6sl-usdhc";
- reg = <0x402c0000 0x4000>;
- interrupts = <110>;
- clocks = <&clks IMXRT1050_CLK_IPG_PDOF>,
- <&clks IMXRT1050_CLK_AHB_PODF>,
- <&clks IMXRT1050_CLK_USDHC1>;
- clock-names = "ipg", "ahb", "per";
- bus-width = <4>;
- fsl,wp-controller;
- no-1-8-v;
- max-frequency = <4000000>;
- fsl,tuning-start-tap = <20>;
- fsl,tuning-step = <2>;
- status = "disabled";
- };
-
- gpio1: gpio@401b8000 {
- compatible = "fsl,imxrt1050-gpio", "fsl,imx35-gpio";
- reg = <0x401b8000 0x4000>;
- interrupts = <80>, <81>;
- gpio-controller;
- #gpio-cells = <2>;
- interrupt-controller;
- #interrupt-cells = <2>;
- };
-
- gpio2: gpio@401bc000 {
- compatible = "fsl,imxrt1050-gpio", "fsl,imx35-gpio";
- reg = <0x401bc000 0x4000>;
- interrupts = <82>, <83>;
- gpio-controller;
- #gpio-cells = <2>;
- interrupt-controller;
- #interrupt-cells = <2>;
- };
-
- gpio3: gpio@401c0000 {
- compatible = "fsl,imxrt1050-gpio", "fsl,imx35-gpio";
- reg = <0x401c0000 0x4000>;
- interrupts = <84>, <85>;
- gpio-controller;
- #gpio-cells = <2>;
- interrupt-controller;
- #interrupt-cells = <2>;
- };
-
- gpio4: gpio@401c4000 {
- compatible = "fsl,imxrt1050-gpio", "fsl,imx35-gpio";
- reg = <0x401c4000 0x4000>;
- interrupts = <86>, <87>;
- gpio-controller;
- #gpio-cells = <2>;
- interrupt-controller;
- #interrupt-cells = <2>;
- };
-
- gpio5: gpio@400c0000 {
- compatible = "fsl,imxrt1050-gpio", "fsl,imx35-gpio";
- reg = <0x400c0000 0x4000>;
- interrupts = <88>, <89>;
- gpio-controller;
- #gpio-cells = <2>;
- interrupt-controller;
- #interrupt-cells = <2>;
- };
-
- gpt: timer@401ec000 {
- compatible = "fsl,imxrt1050-gpt", "fsl,imx6dl-gpt", "fsl,imx6sl-gpt";
- reg = <0x401ec000 0x4000>;
- interrupts = <100>;
- clocks = <&osc3M>;
- clock-names = "per";
- };
- };
-};
diff --git a/arch/arm/dts/k3-am65-iot2050-common-u-boot.dtsi b/arch/arm/dts/k3-am65-iot2050-common-u-boot.dtsi
index b6d2c81..5533717 100644
--- a/arch/arm/dts/k3-am65-iot2050-common-u-boot.dtsi
+++ b/arch/arm/dts/k3-am65-iot2050-common-u-boot.dtsi
@@ -14,6 +14,24 @@
spi0 = &ospi0;
};
+ sysinfo {
+ compatible = "siemens,sysinfo-iot2050";
+ /* TI_SRAM_SCRATCH_BOARD_EEPROM_START */
+ offset = <0x40280000>;
+ bootph-all;
+
+ smbios {
+ system {
+ manufacturer = "SIEMENS AG";
+ product = "SIMATIC IOT2050";
+ };
+
+ baseboard {
+ manufacturer = "SIEMENS AG";
+ };
+ };
+ };
+
leds {
bootph-all;
status-led-red {
diff --git a/arch/arm/dts/rk3036-sdk-u-boot.dtsi b/arch/arm/dts/rk3036-evb-u-boot.dtsi
similarity index 99%
rename from arch/arm/dts/rk3036-sdk-u-boot.dtsi
rename to arch/arm/dts/rk3036-evb-u-boot.dtsi
index ef7e020..f8857c7 100644
--- a/arch/arm/dts/rk3036-sdk-u-boot.dtsi
+++ b/arch/arm/dts/rk3036-evb-u-boot.dtsi
@@ -1,13 +1,13 @@
#include "rk3036-u-boot.dtsi"
-&uart2 {
+&grf {
bootph-all;
};
-&grf {
+&pinctrl {
bootph-all;
};
-&pinctrl {
+&uart2 {
bootph-all;
};
diff --git a/arch/arm/dts/rk3036-sdk-u-boot.dtsi b/arch/arm/dts/rk3036-kylin-u-boot.dtsi
similarity index 99%
copy from arch/arm/dts/rk3036-sdk-u-boot.dtsi
copy to arch/arm/dts/rk3036-kylin-u-boot.dtsi
index ef7e020..f8857c7 100644
--- a/arch/arm/dts/rk3036-sdk-u-boot.dtsi
+++ b/arch/arm/dts/rk3036-kylin-u-boot.dtsi
@@ -1,13 +1,13 @@
#include "rk3036-u-boot.dtsi"
-&uart2 {
+&grf {
bootph-all;
};
-&grf {
+&pinctrl {
bootph-all;
};
-&pinctrl {
+&uart2 {
bootph-all;
};
diff --git a/arch/arm/dts/rk3036-sdk.dts b/arch/arm/dts/rk3036-sdk.dts
deleted file mode 100644
index 3493150..0000000
--- a/arch/arm/dts/rk3036-sdk.dts
+++ /dev/null
@@ -1,74 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * (C) Copyright 2015 Rockchip Electronics Co., Ltd
- */
-
-/dts-v1/;
-
-#include "rk3036.dtsi"
-
-/ {
- model = "SDK-RK3036";
- compatible = "sdk,sdk-rk3036", "rockchip,rk3036";
-
- chosen {
- stdout-path = &uart2;
- };
-
- vcc5v0_otg: vcc5v0-otg-drv {
- compatible = "regulator-fixed";
- regulator-name = "vcc5v0_otg";
- gpio = <&gpio0 26 GPIO_ACTIVE_HIGH>;
- pinctrl-names = "default";
- pinctrl-0 = <&otg_vbus_drv>;
- regulator-min-microvolt = <5000000>;
- regulator-max-microvolt = <5000000>;
- };
-
- vcc5v0_host: vcc5v0-host-drv {
- compatible = "regulator-fixed";
- regulator-name = "vcc5v0_host";
- gpio = <&gpio2 23 GPIO_ACTIVE_HIGH>;
- pinctrl-names = "default";
- pinctrl-0 = <&host_vbus_drv>;
- regulator-min-microvolt = <5000000>;
- regulator-max-microvolt = <5000000>;
- regulator-always-on;
- };
-};
-
-&i2c1 {
- status = "okay";
-
- hym8563: hym8563@51 {
- compatible = "haoyu,hym8563";
- reg = <0x51>;
- #clock-cells = <0>;
- clock-frequency = <32768>;
- clock-output-names = "xin32k";
- };
-};
-
-&usb_host {
- vbus-supply = <&vcc5v0_host>;
- status = "okay";
-};
-
-&usb_otg {
- vbus-supply = <&vcc5v0_otg>;
- status = "okay";
-};
-
-&pinctrl {
- usb_otg {
- otg_vbus_drv: host-vbus-drv {
- rockchip,pins = <0 26 RK_FUNC_GPIO &pcfg_pull_none>;
- };
- };
-
- usb_host {
- host_vbus_drv: host-vbus-drv {
- rockchip,pins = <2 23 RK_FUNC_GPIO &pcfg_pull_none>;
- };
- };
-};
diff --git a/arch/arm/dts/rk3036.dtsi b/arch/arm/dts/rk3036.dtsi
deleted file mode 100644
index 75588de..0000000
--- a/arch/arm/dts/rk3036.dtsi
+++ /dev/null
@@ -1,439 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+
-
-#include <dt-bindings/gpio/gpio.h>
-#include <dt-bindings/interrupt-controller/irq.h>
-#include <dt-bindings/interrupt-controller/arm-gic.h>
-#include <dt-bindings/pinctrl/rockchip.h>
-#include <dt-bindings/clock/rk3036-cru.h>
-#include "skeleton.dtsi"
-
-/ {
- compatible = "rockchip,rk3036";
-
- interrupt-parent = <&gic>;
-
- aliases {
- gpio0 = &gpio0;
- gpio1 = &gpio1;
- gpio2 = &gpio2;
- i2c1 = &i2c1;
- serial0 = &uart0;
- serial1 = &uart1;
- serial2 = &uart2;
- mmc0 = &emmc;
- mmc1 = &sdmmc;
- };
-
- memory {
- device_type = "memory";
- reg = <0x60000000 0x40000000>;
- };
-
- arm-pmu {
- compatible = "arm,cortex-a7-pmu";
- interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>;
- interrupt-affinity = <&cpu0>, <&cpu1>;
- };
-
- cpus {
- #address-cells = <1>;
- #size-cells = <0>;
- enable-method = "rockchip,rk3036-smp";
-
- cpu0: cpu@f00 {
- device_type = "cpu";
- compatible = "arm,cortex-a7";
- reg = <0xf00>;
- operating-points = <
- /* KHz uV */
- 816000 1000000
- >;
- #cooling-cells = <2>; /* min followed by max */
- clock-latency = <40000>;
- clocks = <&cru ARMCLK>;
- resets = <&cru SRST_CORE0>;
- };
- cpu1: cpu@f01 {
- device_type = "cpu";
- compatible = "arm,cortex-a7";
- reg = <0xf01>;
- resets = <&cru SRST_CORE1>;
- };
- };
-
- amba {
- compatible = "arm,amba-bus";
- #address-cells = <1>;
- #size-cells = <1>;
- ranges;
-
- pdma: pdma@20078000 {
- compatible = "arm,pl330", "arm,primecell";
- reg = <0x20078000 0x4000>;
- arm,pl330-broken-no-flushp;
- interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
- #dma-cells = <1>;
- clocks = <&cru ACLK_DMAC2>;
- clock-names = "apb_pclk";
- };
- };
-
- xin24m: oscillator {
- compatible = "fixed-clock";
- clock-frequency = <24000000>;
- clock-output-names = "xin24m";
- #clock-cells = <0>;
- };
-
- timer {
- compatible = "arm,armv7-timer";
- arm,cpu-registers-not-fw-configured;
- interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
- <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
- <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
- <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
- clock-frequency = <24000000>;
- };
-
- cru: clock-controller@20000000 {
- compatible = "rockchip,rk3036-cru";
- reg = <0x20000000 0x1000>;
- rockchip,grf = <&grf>;
- #clock-cells = <1>;
- #reset-cells = <1>;
- assigned-clocks = <&cru PLL_GPLL>;
- assigned-clock-rates = <594000000>;
- };
-
- uart0: serial@20060000 {
- compatible = "rockchip,rk3036-uart", "snps,dw-apb-uart";
- reg = <0x20060000 0x100>;
- interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
- reg-shift = <2>;
- reg-io-width = <4>;
- clock-frequency = <24000000>;
- clocks = <&cru SCLK_UART0>, <&cru PCLK_UART0>;
- clock-names = "baudclk", "apb_pclk";
- pinctrl-names = "default";
- pinctrl-0 = <&uart0_xfer &uart0_cts &uart0_rts>;
- };
-
- uart1: serial@20064000 {
- compatible = "rockchip,rk3036-uart", "snps,dw-apb-uart";
- reg = <0x20064000 0x100>;
- interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>;
- reg-shift = <2>;
- reg-io-width = <4>;
- clock-frequency = <24000000>;
- clocks = <&cru SCLK_UART1>, <&cru PCLK_UART1>;
- clock-names = "baudclk", "apb_pclk";
- pinctrl-names = "default";
- pinctrl-0 = <&uart1_xfer>;
- };
-
- uart2: serial@20068000 {
- compatible = "rockchip,rk3036-uart", "snps,dw-apb-uart";
- reg = <0x20068000 0x100>;
- interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>;
- reg-shift = <2>;
- reg-io-width = <4>;
- clock-frequency = <24000000>;
- clocks = <&cru SCLK_UART2>, <&cru PCLK_UART2>;
- clock-names = "baudclk", "apb_pclk";
- pinctrl-names = "default";
- pinctrl-0 = <&uart2_xfer>;
- };
-
- pwm0: pwm@20050000 {
- compatible = "rockchip,rk2928-pwm";
- reg = <0x20050000 0x10>;
- #pwm-cells = <3>;
- pinctrl-names = "default";
- pinctrl-0 = <&pwm0_pin>;
- clocks = <&cru PCLK_PWM>;
- clock-names = "pwm";
- status = "disabled";
- };
-
- pwm1: pwm@20050010 {
- compatible = "rockchip,rk2928-pwm";
- reg = <0x20050010 0x10>;
- #pwm-cells = <3>;
- pinctrl-names = "default";
- pinctrl-0 = <&pwm1_pin>;
- clocks = <&cru PCLK_PWM>;
- clock-names = "pwm";
- status = "disabled";
- };
-
- pwm2: pwm@20050020 {
- compatible = "rockchip,rk2928-pwm";
- reg = <0x20050020 0x10>;
- #pwm-cells = <3>;
- pinctrl-names = "default";
- pinctrl-0 = <&pwm2_pin>;
- clocks = <&cru PCLK_PWM>;
- clock-names = "pwm";
- status = "disabled";
- };
-
- pwm3: pwm@20050030 {
- compatible = "rockchip,rk2928-pwm";
- reg = <0x20050030 0x10>;
- #pwm-cells = <2>;
- pinctrl-names = "default";
- pinctrl-0 = <&pwm3_pin>;
- clocks = <&cru PCLK_PWM>;
- clock-names = "pwm";
- status = "disabled";
- };
-
- sram: sram@10080000 {
- compatible = "rockchip,rk3036-smp-sram", "mmio-sram";
- reg = <0x10080000 0x2000>;
- };
-
- gic: interrupt-controller@10139000 {
- compatible = "arm,gic-400";
- interrupt-controller;
- #interrupt-cells = <3>;
- #address-cells = <0>;
-
- reg = <0x10139000 0x1000>,
- <0x1013a000 0x1000>,
- <0x1013c000 0x2000>,
- <0x1013e000 0x2000>;
- interrupts = <GIC_PPI 9 0xf04>;
- };
-
- grf: syscon@20008000 {
- compatible = "rockchip,rk3036-grf", "syscon";
- reg = <0x20008000 0x1000>;
- };
-
- usb_otg: usb@10180000 {
- compatible = "rockchip,rk3288-usb", "rockchip,rk3066-usb",
- "snps,dwc2";
- reg = <0x10180000 0x40000>;
- interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cru HCLK_OTG0>;
- clock-names = "otg";
- dr_mode = "otg";
- g-np-tx-fifo-size = <16>;
- g-rx-fifo-size = <275>;
- g-tx-fifo-size = <256 128 128 64 64 32>;
- g-use-dma;
- status = "disabled";
- };
-
- usb_host: usb@101c0000 {
- compatible = "rockchip,rk3288-usb", "rockchip,rk3066-usb",
- "snps,dwc2";
- reg = <0x101c0000 0x40000>;
- interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cru HCLK_OTG1>;
- clock-names = "otg";
- dr_mode = "host";
- status = "disabled";
- };
-
- emmc: dwmmc@1021c000 {
- compatible = "rockchip,rk3288-dw-mshc";
- clock-frequency = <37500000>;
- max-frequency = <37500000>;
- clocks = <&cru HCLK_EMMC>, <&cru SCLK_EMMC>,
- <&cru SCLK_EMMC_DRV>, <&cru SCLK_EMMC_SAMPLE>;
- clock-names = "biu", "ciu", "ciu_drv", "ciu_sample";
- dmas = <&pdma 12>;
- dma-names = "rx-tx";
- fifo-depth = <0x100>;
- interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
- reg = <0x1021c000 0x4000>;
- broken-cd;
- bus-width = <8>;
- cap-mmc-highspeed;
- mmc-ddr-1_8v;
- disable-wp;
- fifo-mode;
- non-removable;
- num-slots = <1>;
- default-sample-phase = <158>;
- pinctrl-names = "default";
- pinctrl-0 = <&emmc_clk &emmc_cmd &emmc_bus8>;
- };
-
- sdmmc: dwmmc@10214000 {
- compatible = "rockchip,rk3036-dw-mshc", "rockchip,rk3288-dw-mshc";
- reg = <0x10214000 0x4000>;
- clock-frequency = <37500000>;
- max-frequency = <37500000>;
- clocks = <&cru HCLK_SDMMC>, <&cru SCLK_SDMMC>;
- clock-names = "biu", "ciu";
- fifo-depth = <0x100>;
- interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
- status = "disabled";
- };
-
- pinctrl: pinctrl {
- compatible = "rockchip,rk3036-pinctrl";
- rockchip,grf = <&grf>;
- #address-cells = <1>;
- #size-cells = <1>;
- ranges;
-
- gpio0: gpio0@2007c000 {
- compatible = "rockchip,gpio-bank";
- reg = <0x2007c000 0x100>;
- interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cru PCLK_GPIO0>;
-
- gpio-controller;
- #gpio-cells = <2>;
-
- interrupt-controller;
- #interrupt-cells = <2>;
- };
-
- gpio1: gpio1@20080000 {
- compatible = "rockchip,gpio-bank";
- reg = <0x20080000 0x100>;
- interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cru PCLK_GPIO1>;
-
- gpio-controller;
- #gpio-cells = <2>;
-
- interrupt-controller;
- #interrupt-cells = <2>;
- };
-
- gpio2: gpio2@20084000 {
- compatible = "rockchip,gpio-bank";
- reg = <0x20084000 0x100>;
- interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cru PCLK_GPIO2>;
-
- gpio-controller;
- #gpio-cells = <2>;
-
- interrupt-controller;
- #interrupt-cells = <2>;
- };
-
- pcfg_pull_up: pcfg-pull-up {
- bias-pull-up;
- };
-
- pcfg_pull_down: pcfg-pull-down {
- bias-pull-down;
- };
-
- pcfg_pull_none: pcfg-pull-none {
- bias-disable;
- };
-
- emmc {
- /*
- * We run eMMC at max speed; bump up drive strength.
- * We also have external pulls, so disable the internal ones.
- */
- emmc_clk: emmc-clk {
- rockchip,pins = <2 4 RK_FUNC_2 &pcfg_pull_none>;
- };
-
- emmc_cmd: emmc-cmd {
- rockchip,pins = <2 1 RK_FUNC_2 &pcfg_pull_none>;
- };
-
- emmc_bus8: emmc-bus8 {
- rockchip,pins = <1 24 RK_FUNC_2 &pcfg_pull_none>,
- <1 25 RK_FUNC_2 &pcfg_pull_none>,
- <1 26 RK_FUNC_2 &pcfg_pull_none>,
- <1 27 RK_FUNC_2 &pcfg_pull_none>;
- /*
- <1 28 RK_FUNC_2 &pcfg_pull_up>,
- <1 29 RK_FUNC_2 &pcfg_pull_up>,
- <1 30 RK_FUNC_2 &pcfg_pull_up>,
- <1 31 RK_FUNC_2 &pcfg_pull_up>;
- */
- };
- };
-
- uart0 {
- uart0_xfer: uart0-xfer {
- rockchip,pins = <0 16 RK_FUNC_1 &pcfg_pull_none>,
- <0 17 RK_FUNC_1 &pcfg_pull_none>;
- };
-
- uart0_cts: uart0-cts {
- rockchip,pins = <0 18 RK_FUNC_1 &pcfg_pull_none>;
- };
-
- uart0_rts: uart0-rts {
- rockchip,pins = <0 19 RK_FUNC_1 &pcfg_pull_none>;
- };
- };
-
- uart1 {
- uart1_xfer: uart1-xfer {
- rockchip,pins = <2 22 RK_FUNC_1 &pcfg_pull_none>,
- <2 23 RK_FUNC_1 &pcfg_pull_none>;
- };
- /* no rts / cts for uart1 */
- };
-
- uart2 {
- uart2_xfer: uart2-xfer {
- rockchip,pins = <1 18 RK_FUNC_2 &pcfg_pull_none>,
- <1 19 RK_FUNC_2 &pcfg_pull_none>;
- };
- /* no rts / cts for uart2 */
- };
-
- pwm0 {
- pwm0_pin: pwm0-pin {
- rockchip,pins = <0 0 RK_FUNC_2 &pcfg_pull_none>;
- };
- };
-
- pwm1 {
- pwm1_pin: pwm1-pin {
- rockchip,pins = <0 1 RK_FUNC_2 &pcfg_pull_none>;
- };
- };
-
- pwm2 {
- pwm2_pin: pwm2-pin {
- rockchip,pins = <0 1 2 &pcfg_pull_none>;
- };
- };
-
- pwm3 {
- pwm3_pin: pwm3-pin {
- rockchip,pins = <0 27 1 &pcfg_pull_none>;
- };
- };
-
- i2c1 {
- i2c1_xfer: i2c1-xfer {
- rockchip,pins = <0 2 RK_FUNC_1 &pcfg_pull_none>,
- <0 3 RK_FUNC_1 &pcfg_pull_none>;
- };
- };
- };
-
- i2c1: i2c@20056000 {
- compatible = "rockchip,rk3288-i2c";
- reg = <0x20056000 0x1000>;
- interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
- #address-cells = <1>;
- #size-cells = <0>;
- clock-names = "i2c";
- clocks = <&cru PCLK_I2C1>;
- pinctrl-names = "default";
- pinctrl-0 = <&i2c1_xfer>;
- status = "disabled";
- };
-};
diff --git a/arch/arm/dts/sam9x60.dtsi b/arch/arm/dts/sam9x60.dtsi
index 3b684fc..60de914 100644
--- a/arch/arm/dts/sam9x60.dtsi
+++ b/arch/arm/dts/sam9x60.dtsi
@@ -17,6 +17,7 @@
/{
model = "Microchip SAM9X60 SoC";
compatible = "microchip,sam9x60";
+ interrupt-parent = <&aic>;
aliases {
serial0 = &dbgu;
@@ -122,8 +123,6 @@
assigned-clock-rates = <100000000>;
assigned-clock-parents = <&pmc PMC_TYPE_CORE 10>; /* ID_PLL_A_DIV */
bus-width = <4>;
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_sdhci0>;
};
sdhci1: sdhci-host@90000000 {
@@ -135,8 +134,6 @@
assigned-clock-rates = <100000000>;
assigned-clock-parents = <&pmc PMC_TYPE_CORE 10>; /* ID_PLL_A_DIV */
bus-width = <4>;
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_sdhci1>;
};
apb {
@@ -176,8 +173,6 @@
macb0: ethernet@f802c000 {
compatible = "cdns,sam9x60-macb", "cdns,macb";
reg = <0xf802c000 0x100>;
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_macb0_rmii>;
clock-names = "hclk", "pclk";
clocks = <&pmc PMC_TYPE_PERIPHERAL 24>, <&pmc PMC_TYPE_PERIPHERAL 24>;
status = "disabled";
@@ -199,11 +194,17 @@
reg = <0xffffea00 0x100>;
};
+ aic: interrupt-controller@fffff100 {
+ compatible = "microchip,sam9x60-aic";
+ #interrupt-cells = <3>;
+ interrupt-controller;
+ reg = <0xfffff100 0x100>;
+ atmel,external-irqs = <31>;
+ };
+
dbgu: serial@fffff200 {
compatible = "atmel,at91sam9260-dbgu", "atmel,at91sam9260-usart";
reg = <0xfffff200 0x200>;
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_dbgu>;
clocks = <&pmc PMC_TYPE_PERIPHERAL 47>;
clock-names = "usart";
};
@@ -211,99 +212,63 @@
pinctrl: pinctrl@fffff400 {
#address-cells = <1>;
#size-cells = <1>;
- compatible = "microchip,sam9x60-pinctrl", "simple-bus";
+ compatible = "microchip,sam9x60-pinctrl", "simple-mfd";
ranges = <0xfffff400 0xfffff400 0x800>;
- reg = <0xfffff400 0x200 /* pioA */
- 0xfffff600 0x200 /* pioB */
- 0xfffff800 0x200 /* pioC */
- 0xfffffa00 0x200>; /* pioD */
- /* shared pinctrl settings */
- dbgu {
- pinctrl_dbgu: dbgu-0 {
- atmel,pins =
- <AT91_PIOA 9 AT91_PERIPH_A AT91_PINCTRL_PULL_UP
- AT91_PIOA 10 AT91_PERIPH_A AT91_PINCTRL_NONE>;
- };
- };
+ /* mux-mask corresponding to sam9x60 SoC in TFBGA228L package */
+ atmel,mux-mask = <
+ /* A B C */
+ 0xffffffff 0xffe03fff 0xef00019d /* pioA */
+ 0x03ffffff 0x02fc7e7f 0x00780000 /* pioB */
+ 0xffffffff 0xffffffff 0xf83fffff /* pioC */
+ 0x003fffff 0x003f8000 0x00000000 /* pioD */
+ >;
- macb0 {
- pinctrl_macb0_rmii: macb0_rmii-0 {
- atmel,pins =
- <AT91_PIOB 0 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB0 periph A */
- AT91_PIOB 1 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB1 periph A */
- AT91_PIOB 2 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB2 periph A */
- AT91_PIOB 3 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB3 periph A */
- AT91_PIOB 4 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB4 periph A */
- AT91_PIOB 5 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB5 periph A */
- AT91_PIOB 6 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB6 periph A */
- AT91_PIOB 7 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB7 periph A */
- AT91_PIOB 9 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB9 periph A */
- AT91_PIOB 10 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PB10 periph A */
- };
+ pioA: gpio@fffff400 {
+ compatible = "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio";
+ reg = <0xfffff400 0x200>;
+ interrupts = <2 IRQ_TYPE_LEVEL_HIGH 1>;
+ #gpio-cells = <2>;
+ gpio-controller;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ clocks = <&pmc PMC_TYPE_PERIPHERAL 2>;
};
- sdhci0 {
- pinctrl_sdhci0: sdhci0 {
- atmel,pins =
- <AT91_PIOA 17 AT91_PERIPH_A
- (AT91_PINCTRL_DRIVE_STRENGTH_HI | AT91_PINCTRL_SLEWRATE_ENA) /* PA17 CK periph A with pullup */
- AT91_PIOA 16 AT91_PERIPH_A
- (AT91_PINCTRL_PULL_UP | AT91_PINCTRL_DRIVE_STRENGTH_HI | AT91_PINCTRL_SLEWRATE_ENA) /* PA16 CMD periph A with pullup */
- AT91_PIOA 15 AT91_PERIPH_A
- (AT91_PINCTRL_PULL_UP | AT91_PINCTRL_DRIVE_STRENGTH_HI | AT91_PINCTRL_SLEWRATE_ENA) /* PA15 DAT0 periph A */
- AT91_PIOA 18 AT91_PERIPH_A
- (AT91_PINCTRL_PULL_UP | AT91_PINCTRL_DRIVE_STRENGTH_HI | AT91_PINCTRL_SLEWRATE_ENA) /* PA18 DAT1 periph A with pullup */
- AT91_PIOA 19 AT91_PERIPH_A
- (AT91_PINCTRL_PULL_UP | AT91_PINCTRL_DRIVE_STRENGTH_HI | AT91_PINCTRL_SLEWRATE_ENA) /* PA19 DAT2 periph A with pullup */
- AT91_PIOA 20 AT91_PERIPH_A
- (AT91_PINCTRL_PULL_UP | AT91_PINCTRL_DRIVE_STRENGTH_HI | AT91_PINCTRL_SLEWRATE_ENA)>; /* PA20 DAT3 periph A with pullup */
- };
+ pioB: gpio@fffff600 {
+ compatible = "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio";
+ reg = <0xfffff600 0x200>;
+ interrupts = <3 IRQ_TYPE_LEVEL_HIGH 1>;
+ #gpio-cells = <2>;
+ gpio-controller;
+ #gpio-lines = <26>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ clocks = <&pmc PMC_TYPE_PERIPHERAL 3>;
};
- sdhci1 {
- pinctrl_sdhci1: sdhci1 {
- atmel,pins =
- <AT91_PIOA 13 AT91_PERIPH_B (AT91_PINCTRL_DRIVE_STRENGTH_HI) /* PA13 CK periph B */
- AT91_PIOA 12 AT91_PERIPH_B (AT91_PINCTRL_PULL_UP | AT91_PINCTRL_DRIVE_STRENGTH_HI) /* PA12 CMD periph B with pullup */
- AT91_PIOA 11 AT91_PERIPH_B (AT91_PINCTRL_PULL_UP | AT91_PINCTRL_DRIVE_STRENGTH_HI) /* PA11 DAT0 periph B with pullup */
- AT91_PIOA 2 AT91_PERIPH_B (AT91_PINCTRL_PULL_UP | AT91_PINCTRL_DRIVE_STRENGTH_HI) /* PA2 DAT1 periph B with pullup */
- AT91_PIOA 3 AT91_PERIPH_B (AT91_PINCTRL_PULL_UP | AT91_PINCTRL_DRIVE_STRENGTH_HI) /* PA3 DAT2 periph B with pullup */
- AT91_PIOA 4 AT91_PERIPH_B (AT91_PINCTRL_PULL_UP | AT91_PINCTRL_DRIVE_STRENGTH_HI)>; /* PA4 DAT3 periph B with pullup */
- };
+ pioC: gpio@fffff800 {
+ compatible = "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio";
+ reg = <0xfffff800 0x200>;
+ interrupts = <4 IRQ_TYPE_LEVEL_HIGH 1>;
+ #gpio-cells = <2>;
+ gpio-controller;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ clocks = <&pmc PMC_TYPE_PERIPHERAL 4>;
};
- };
-
- pioA: gpio@fffff400 {
- compatible = "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio";
- reg = <0xfffff400 0x200>;
- #gpio-cells = <2>;
- gpio-controller;
- clocks = <&pmc PMC_TYPE_PERIPHERAL 2>;
- };
- pioB: gpio@fffff600 {
- compatible = "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio";
- reg = <0xfffff600 0x200>;
- #gpio-cells = <2>;
- gpio-controller;
- clocks = <&pmc PMC_TYPE_PERIPHERAL 3>;
- };
-
- pioC: gpio@fffff800 {
- compatible = "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio";
- reg = <0xfffff800 0x200>;
- #gpio-cells = <2>;
- gpio-controller;
- clocks = <&pmc PMC_TYPE_PERIPHERAL 4>;
- };
-
- pioD: gpio@fffffa00 {
- compatible = "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio";
- reg = <0xfffffa00 0x200>;
- #gpio-cells = <2>;
- gpio-controller;
- clocks = <&pmc PMC_TYPE_PERIPHERAL 44>;
+ pioD: gpio@fffffa00 {
+ compatible = "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio";
+ reg = <0xfffffa00 0x200>;
+ interrupts = <44 IRQ_TYPE_LEVEL_HIGH 1>;
+ #gpio-cells = <2>;
+ gpio-controller;
+ #gpio-lines = <22>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ clocks = <&pmc PMC_TYPE_PERIPHERAL 44>;
+ };
};
pmc: pmc@fffffc00 {
diff --git a/arch/arm/dts/sam9x60ek.dts b/arch/arm/dts/sam9x60ek.dts
index 74016f5..6521585 100644
--- a/arch/arm/dts/sam9x60ek.dts
+++ b/arch/arm/dts/sam9x60ek.dts
@@ -78,79 +78,15 @@
};
};
};
-
- pinctrl {
- nand {
- pinctrl_nand_oe_we: nand-oe-we-0 {
- atmel,pins =
- <AT91_PIOD 0 AT91_PERIPH_A (AT91_PINCTRL_NONE | AT91_PINCTRL_SLEWRATE_DIS)
- AT91_PIOD 1 AT91_PERIPH_A (AT91_PINCTRL_NONE | AT91_PINCTRL_SLEWRATE_DIS)>;
- };
-
- pinctrl_nand_rb: nand-rb-0 {
- atmel,pins =
- <AT91_PIOD 5 AT91_PERIPH_GPIO AT91_PINCTRL_PULL_UP>;
- };
-
- pinctrl_nand_cs: nand-cs-0 {
- atmel,pins =
- <AT91_PIOD 4 AT91_PERIPH_GPIO AT91_PINCTRL_PULL_UP>;
- };
- };
-
- ebi {
- pinctrl_ebi_data_0_7: ebi-data-lsb-0 {
- atmel,pins =
- <AT91_PIOD 6 AT91_PERIPH_A (AT91_PINCTRL_NONE | AT91_PINCTRL_SLEWRATE_DIS)
- AT91_PIOD 7 AT91_PERIPH_A (AT91_PINCTRL_NONE | AT91_PINCTRL_SLEWRATE_DIS)
- AT91_PIOD 8 AT91_PERIPH_A (AT91_PINCTRL_NONE | AT91_PINCTRL_SLEWRATE_DIS)
- AT91_PIOD 9 AT91_PERIPH_A (AT91_PINCTRL_NONE | AT91_PINCTRL_SLEWRATE_DIS)
- AT91_PIOD 10 AT91_PERIPH_A (AT91_PINCTRL_NONE | AT91_PINCTRL_SLEWRATE_DIS)
- AT91_PIOD 11 AT91_PERIPH_A (AT91_PINCTRL_NONE | AT91_PINCTRL_SLEWRATE_DIS)
- AT91_PIOD 12 AT91_PERIPH_A (AT91_PINCTRL_NONE | AT91_PINCTRL_SLEWRATE_DIS)
- AT91_PIOD 13 AT91_PERIPH_A (AT91_PINCTRL_NONE | AT91_PINCTRL_SLEWRATE_DIS)>;
- };
-
- pinctrl_ebi_addr_nand: ebi-addr-0 {
- atmel,pins =
- <AT91_PIOD 2 AT91_PERIPH_A (AT91_PINCTRL_NONE | AT91_PINCTRL_SLEWRATE_DIS)
- AT91_PIOD 3 AT91_PERIPH_A (AT91_PINCTRL_NONE | AT91_PINCTRL_SLEWRATE_DIS)>;
- };
- };
-
- pinctrl_qspi: qspi {
- atmel,pins =
- <AT91_PIOB 19 AT91_PERIPH_A AT91_PINCTRL_NONE
- AT91_PIOB 20 AT91_PERIPH_A AT91_PINCTRL_NONE
- AT91_PIOB 21 AT91_PERIPH_A AT91_PINCTRL_PULL_UP
- AT91_PIOB 22 AT91_PERIPH_A AT91_PINCTRL_PULL_UP
- AT91_PIOB 23 AT91_PERIPH_A AT91_PINCTRL_PULL_UP
- AT91_PIOB 24 AT91_PERIPH_A AT91_PINCTRL_PULL_UP>;
- };
-
- pinctrl_flx0: flx0_default {
- atmel,pins =
- <AT91_PIOA 0 AT91_PERIPH_A AT91_PINCTRL_NONE
- AT91_PIOA 1 AT91_PERIPH_A AT91_PINCTRL_NONE>;
- };
-
- pinctrl_onewire_tm_default: onewire_tm_default {
- atmel,pins =
- <AT91_PIOD 14 AT91_PERIPH_GPIO AT91_PINCTRL_PULL_UP>;
- };
-
- usb1 {
- pinctrl_usb_default: usb_default {
- atmel,pins = <AT91_PIOD 15 AT91_PERIPH_GPIO AT91_PINCTRL_NONE
- AT91_PIOD 16 AT91_PERIPH_GPIO AT91_PINCTRL_NONE>;
- };
- };
-
- };
};
};
};
+&dbgu {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_dbgu>;
+};
+
&ebi {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_ebi_addr_nand &pinctrl_ebi_data_0_7>;
@@ -218,9 +154,148 @@
&macb0 {
phy-mode = "rmii";
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_macb0_rmii>;
status = "okay";
};
+&pinctrl {
+ /* shared pinctrl settings */
+ dbgu {
+ pinctrl_dbgu: dbgu-0 {
+ atmel,pins =
+ <AT91_PIOA 9 AT91_PERIPH_A AT91_PINCTRL_PULL_UP
+ AT91_PIOA 10 AT91_PERIPH_A AT91_PINCTRL_NONE>;
+ };
+ };
+
+ qspi {
+ pinctrl_qspi: qspi {
+ atmel,pins =
+ <AT91_PIOB 19 AT91_PERIPH_A AT91_PINCTRL_NONE
+ AT91_PIOB 20 AT91_PERIPH_A AT91_PINCTRL_NONE
+ AT91_PIOB 21 AT91_PERIPH_A AT91_PINCTRL_PULL_UP
+ AT91_PIOB 22 AT91_PERIPH_A AT91_PINCTRL_PULL_UP
+ AT91_PIOB 23 AT91_PERIPH_A AT91_PINCTRL_PULL_UP
+ AT91_PIOB 24 AT91_PERIPH_A AT91_PINCTRL_PULL_UP>;
+ };
+ };
+
+ nand {
+ pinctrl_nand_oe_we: nand-oe-we-0 {
+ atmel,pins =
+ <AT91_PIOD 0 AT91_PERIPH_A (AT91_PINCTRL_NONE | AT91_PINCTRL_SLEWRATE_DIS)
+ AT91_PIOD 1 AT91_PERIPH_A (AT91_PINCTRL_NONE | AT91_PINCTRL_SLEWRATE_DIS)>;
+ };
+
+ pinctrl_nand_rb: nand-rb-0 {
+ atmel,pins =
+ <AT91_PIOD 5 AT91_PERIPH_GPIO AT91_PINCTRL_PULL_UP>;
+ };
+
+ pinctrl_nand_cs: nand-cs-0 {
+ atmel,pins =
+ <AT91_PIOD 4 AT91_PERIPH_GPIO AT91_PINCTRL_PULL_UP>;
+ };
+ };
+
+ ebi {
+ pinctrl_ebi_data_0_7: ebi-data-lsb-0 {
+ atmel,pins =
+ <AT91_PIOD 6 AT91_PERIPH_A (AT91_PINCTRL_NONE | AT91_PINCTRL_SLEWRATE_DIS)
+ AT91_PIOD 7 AT91_PERIPH_A (AT91_PINCTRL_NONE | AT91_PINCTRL_SLEWRATE_DIS)
+ AT91_PIOD 8 AT91_PERIPH_A (AT91_PINCTRL_NONE | AT91_PINCTRL_SLEWRATE_DIS)
+ AT91_PIOD 9 AT91_PERIPH_A (AT91_PINCTRL_NONE | AT91_PINCTRL_SLEWRATE_DIS)
+ AT91_PIOD 10 AT91_PERIPH_A (AT91_PINCTRL_NONE | AT91_PINCTRL_SLEWRATE_DIS)
+ AT91_PIOD 11 AT91_PERIPH_A (AT91_PINCTRL_NONE | AT91_PINCTRL_SLEWRATE_DIS)
+ AT91_PIOD 12 AT91_PERIPH_A (AT91_PINCTRL_NONE | AT91_PINCTRL_SLEWRATE_DIS)
+ AT91_PIOD 13 AT91_PERIPH_A (AT91_PINCTRL_NONE | AT91_PINCTRL_SLEWRATE_DIS)>;
+ };
+
+ pinctrl_ebi_addr_nand: ebi-addr-0 {
+ atmel,pins =
+ <AT91_PIOD 2 AT91_PERIPH_A (AT91_PINCTRL_NONE | AT91_PINCTRL_SLEWRATE_DIS)
+ AT91_PIOD 3 AT91_PERIPH_A (AT91_PINCTRL_NONE | AT91_PINCTRL_SLEWRATE_DIS)>;
+ };
+ };
+
+ flexcom {
+ pinctrl_flx0: flx0_default {
+ atmel,pins =
+ <AT91_PIOA 0 AT91_PERIPH_A AT91_PINCTRL_NONE
+ AT91_PIOA 1 AT91_PERIPH_A AT91_PINCTRL_NONE>;
+ };
+ };
+
+ macb0 {
+ pinctrl_macb0_rmii: macb0_rmii-0 {
+ atmel,pins =
+ <AT91_PIOB 0 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB0 periph A */
+ AT91_PIOB 1 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB1 periph A */
+ AT91_PIOB 2 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB2 periph A */
+ AT91_PIOB 3 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB3 periph A */
+ AT91_PIOB 4 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB4 periph A */
+ AT91_PIOB 5 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB5 periph A */
+ AT91_PIOB 6 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB6 periph A */
+ AT91_PIOB 7 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB7 periph A */
+ AT91_PIOB 9 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB9 periph A */
+ AT91_PIOB 10 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PB10 periph A */
+ };
+ };
+
+ pinctrl_onewire_tm_default: onewire_tm_default {
+ atmel,pins =
+ <AT91_PIOD 14 AT91_PERIPH_GPIO AT91_PINCTRL_PULL_UP>;
+ };
+
+ sdhci0 {
+ pinctrl_sdhci0: sdhci0 {
+ atmel,pins =
+ <AT91_PIOA 17 AT91_PERIPH_A
+ (AT91_PINCTRL_DRIVE_STRENGTH_HI | AT91_PINCTRL_SLEWRATE_ENA) /* PA17 CK periph A with pullup */
+ AT91_PIOA 16 AT91_PERIPH_A
+ (AT91_PINCTRL_PULL_UP | AT91_PINCTRL_DRIVE_STRENGTH_HI | AT91_PINCTRL_SLEWRATE_ENA) /* PA16 CMD periph A with pullup */
+ AT91_PIOA 15 AT91_PERIPH_A
+ (AT91_PINCTRL_PULL_UP | AT91_PINCTRL_DRIVE_STRENGTH_HI | AT91_PINCTRL_SLEWRATE_ENA) /* PA15 DAT0 periph A */
+ AT91_PIOA 18 AT91_PERIPH_A
+ (AT91_PINCTRL_PULL_UP | AT91_PINCTRL_DRIVE_STRENGTH_HI | AT91_PINCTRL_SLEWRATE_ENA) /* PA18 DAT1 periph A with pullup */
+ AT91_PIOA 19 AT91_PERIPH_A
+ (AT91_PINCTRL_PULL_UP | AT91_PINCTRL_DRIVE_STRENGTH_HI | AT91_PINCTRL_SLEWRATE_ENA) /* PA19 DAT2 periph A with pullup */
+ AT91_PIOA 20 AT91_PERIPH_A
+ (AT91_PINCTRL_PULL_UP | AT91_PINCTRL_DRIVE_STRENGTH_HI | AT91_PINCTRL_SLEWRATE_ENA)>; /* PA20 DAT3 periph A with pullup */
+ };
+ };
+
+ sdhci1 {
+ pinctrl_sdhci1: sdhci1 {
+ atmel,pins =
+ <AT91_PIOA 13 AT91_PERIPH_B (AT91_PINCTRL_DRIVE_STRENGTH_HI) /* PA13 CK periph B */
+ AT91_PIOA 12 AT91_PERIPH_B (AT91_PINCTRL_PULL_UP | AT91_PINCTRL_DRIVE_STRENGTH_HI) /* PA12 CMD periph B with pullup */
+ AT91_PIOA 11 AT91_PERIPH_B (AT91_PINCTRL_PULL_UP | AT91_PINCTRL_DRIVE_STRENGTH_HI) /* PA11 DAT0 periph B with pullup */
+ AT91_PIOA 2 AT91_PERIPH_B (AT91_PINCTRL_PULL_UP | AT91_PINCTRL_DRIVE_STRENGTH_HI) /* PA2 DAT1 periph B with pullup */
+ AT91_PIOA 3 AT91_PERIPH_B (AT91_PINCTRL_PULL_UP | AT91_PINCTRL_DRIVE_STRENGTH_HI) /* PA3 DAT2 periph B with pullup */
+ AT91_PIOA 4 AT91_PERIPH_B (AT91_PINCTRL_PULL_UP | AT91_PINCTRL_DRIVE_STRENGTH_HI)>; /* PA4 DAT3 periph B with pullup */
+ };
+ };
+
+ usb1 {
+ pinctrl_usb_default: usb_default {
+ atmel,pins = <AT91_PIOD 15 AT91_PERIPH_GPIO AT91_PINCTRL_NONE
+ AT91_PIOD 16 AT91_PERIPH_GPIO AT91_PINCTRL_NONE>;
+ };
+ };
+};
+
+&sdhci0 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_sdhci0>;
+};
+
+&sdhci1 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_sdhci1>;
+};
+
&usb1 {
num-ports = <3>;
atmel,vbus-gpio = <0
diff --git a/arch/arm/dts/sama5d3.dtsi b/arch/arm/dts/sama5d3.dtsi
index 4c03a30..10d6e74 100644
--- a/arch/arm/dts/sama5d3.dtsi
+++ b/arch/arm/dts/sama5d3.dtsi
@@ -492,12 +492,6 @@
0xffffffff 0xc001c0e0 0x0001c1e0 /* pioD */
0xffffffff 0xbf9f8000 0x18000000 /* pioE */
>;
- reg = <0xfffff200 0x100 /* pioA */
- 0xfffff400 0x100 /* pioB */
- 0xfffff600 0x100 /* pioC */
- 0xfffff800 0x100 /* pioD */
- 0xfffffa00 0x100 /* pioE */
- >;
/* shared pinctrl settings */
adc0 {
@@ -873,66 +867,66 @@
AT91_PIOE 17 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* PE17 periph B, conflicts with A17 */
};
};
- };
- pioA: gpio@fffff200 {
- compatible = "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio";
- reg = <0xfffff200 0x100>;
- interrupts = <6 IRQ_TYPE_LEVEL_HIGH 1>;
- #gpio-cells = <2>;
- gpio-controller;
- interrupt-controller;
- #interrupt-cells = <2>;
- clocks = <&pioA_clk>;
- bootph-all;
- };
+ pioA: gpio@fffff200 {
+ compatible = "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio";
+ reg = <0xfffff200 0x100>;
+ interrupts = <6 IRQ_TYPE_LEVEL_HIGH 1>;
+ #gpio-cells = <2>;
+ gpio-controller;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ clocks = <&pioA_clk>;
+ bootph-all;
+ };
- pioB: gpio@fffff400 {
- compatible = "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio";
- reg = <0xfffff400 0x100>;
- interrupts = <7 IRQ_TYPE_LEVEL_HIGH 1>;
- #gpio-cells = <2>;
- gpio-controller;
- interrupt-controller;
- #interrupt-cells = <2>;
- clocks = <&pioB_clk>;
- bootph-all;
- };
+ pioB: gpio@fffff400 {
+ compatible = "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio";
+ reg = <0xfffff400 0x100>;
+ interrupts = <7 IRQ_TYPE_LEVEL_HIGH 1>;
+ #gpio-cells = <2>;
+ gpio-controller;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ clocks = <&pioB_clk>;
+ bootph-all;
+ };
- pioC: gpio@fffff600 {
- compatible = "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio";
- reg = <0xfffff600 0x100>;
- interrupts = <8 IRQ_TYPE_LEVEL_HIGH 1>;
- #gpio-cells = <2>;
- gpio-controller;
- interrupt-controller;
- #interrupt-cells = <2>;
- clocks = <&pioC_clk>;
- bootph-all;
- };
+ pioC: gpio@fffff600 {
+ compatible = "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio";
+ reg = <0xfffff600 0x100>;
+ interrupts = <8 IRQ_TYPE_LEVEL_HIGH 1>;
+ #gpio-cells = <2>;
+ gpio-controller;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ clocks = <&pioC_clk>;
+ bootph-all;
+ };
- pioD: gpio@fffff800 {
- compatible = "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio";
- reg = <0xfffff800 0x100>;
- interrupts = <9 IRQ_TYPE_LEVEL_HIGH 1>;
- #gpio-cells = <2>;
- gpio-controller;
- interrupt-controller;
- #interrupt-cells = <2>;
- clocks = <&pioD_clk>;
- bootph-all;
- };
+ pioD: gpio@fffff800 {
+ compatible = "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio";
+ reg = <0xfffff800 0x100>;
+ interrupts = <9 IRQ_TYPE_LEVEL_HIGH 1>;
+ #gpio-cells = <2>;
+ gpio-controller;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ clocks = <&pioD_clk>;
+ bootph-all;
+ };
- pioE: gpio@fffffa00 {
- compatible = "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio";
- reg = <0xfffffa00 0x100>;
- interrupts = <10 IRQ_TYPE_LEVEL_HIGH 1>;
- #gpio-cells = <2>;
- gpio-controller;
- interrupt-controller;
- #interrupt-cells = <2>;
- clocks = <&pioE_clk>;
- bootph-all;
+ pioE: gpio@fffffa00 {
+ compatible = "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio";
+ reg = <0xfffffa00 0x100>;
+ interrupts = <10 IRQ_TYPE_LEVEL_HIGH 1>;
+ #gpio-cells = <2>;
+ gpio-controller;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ clocks = <&pioE_clk>;
+ bootph-all;
+ };
};
pmc: pmc@fffffc00 {
diff --git a/arch/arm/dts/sama5d4.dtsi b/arch/arm/dts/sama5d4.dtsi
index 5e2c9a1..482cf03 100644
--- a/arch/arm/dts/sama5d4.dtsi
+++ b/arch/arm/dts/sama5d4.dtsi
@@ -1361,62 +1361,6 @@
status = "disabled";
};
- pioA: gpio@fc06a000 {
- compatible = "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio";
- reg = <0xfc06a000 0x100>;
- interrupts = <23 IRQ_TYPE_LEVEL_HIGH 1>;
- #gpio-cells = <2>;
- gpio-controller;
- interrupt-controller;
- #interrupt-cells = <2>;
- clocks = <&pioA_clk>;
- };
-
- pioB: gpio@fc06b000 {
- compatible = "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio";
- reg = <0xfc06b000 0x100>;
- interrupts = <24 IRQ_TYPE_LEVEL_HIGH 1>;
- #gpio-cells = <2>;
- gpio-controller;
- interrupt-controller;
- #interrupt-cells = <2>;
- clocks = <&pioB_clk>;
- };
-
- pioC: gpio@fc06c000 {
- compatible = "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio";
- reg = <0xfc06c000 0x100>;
- interrupts = <25 IRQ_TYPE_LEVEL_HIGH 1>;
- #gpio-cells = <2>;
- gpio-controller;
- interrupt-controller;
- #interrupt-cells = <2>;
- clocks = <&pioC_clk>;
- bootph-all;
- };
-
- pioD: gpio@fc068000 {
- compatible = "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio";
- reg = <0xfc068000 0x100>;
- interrupts = <5 IRQ_TYPE_LEVEL_HIGH 1>;
- #gpio-cells = <2>;
- gpio-controller;
- interrupt-controller;
- #interrupt-cells = <2>;
- clocks = <&pioD_clk>;
- };
-
- pioE: gpio@fc06d000 {
- compatible = "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio";
- reg = <0xfc06d000 0x100>;
- interrupts = <26 IRQ_TYPE_LEVEL_HIGH 1>;
- #gpio-cells = <2>;
- gpio-controller;
- interrupt-controller;
- #interrupt-cells = <2>;
- clocks = <&pioE_clk>;
- };
-
pinctrl@fc06a000 {
bootph-all;
#address-cells = <1>;
@@ -1433,12 +1377,62 @@
0x0003ff00 0x8002a800 0x00000000 /* pioD */
0xffffffff 0x7fffffff 0x76fff1bf /* pioE */
>;
- reg = < 0xfc06a000 0x100
- 0xfc06b000 0x100
- 0xfc06c000 0x100
- 0xfc068000 0x100
- 0xfc06d000 0x100
- >;
+
+ pioA: gpio@fc06a000 {
+ compatible = "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio";
+ reg = <0xfc06a000 0x100>;
+ interrupts = <23 IRQ_TYPE_LEVEL_HIGH 1>;
+ #gpio-cells = <2>;
+ gpio-controller;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ clocks = <&pioA_clk>;
+ };
+
+ pioB: gpio@fc06b000 {
+ compatible = "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio";
+ reg = <0xfc06b000 0x100>;
+ interrupts = <24 IRQ_TYPE_LEVEL_HIGH 1>;
+ #gpio-cells = <2>;
+ gpio-controller;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ clocks = <&pioB_clk>;
+ };
+
+ pioC: gpio@fc06c000 {
+ compatible = "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio";
+ reg = <0xfc06c000 0x100>;
+ interrupts = <25 IRQ_TYPE_LEVEL_HIGH 1>;
+ #gpio-cells = <2>;
+ gpio-controller;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ clocks = <&pioC_clk>;
+ bootph-all;
+ };
+
+ pioD: gpio@fc068000 {
+ compatible = "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio";
+ reg = <0xfc068000 0x100>;
+ interrupts = <5 IRQ_TYPE_LEVEL_HIGH 1>;
+ #gpio-cells = <2>;
+ gpio-controller;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ clocks = <&pioD_clk>;
+ };
+
+ pioE: gpio@fc06d000 {
+ compatible = "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio";
+ reg = <0xfc06d000 0x100>;
+ interrupts = <26 IRQ_TYPE_LEVEL_HIGH 1>;
+ #gpio-cells = <2>;
+ gpio-controller;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ clocks = <&pioE_clk>;
+ };
/* pinctrl pin settings */
adc0 {
diff --git a/arch/arm/dts/socfpga_agilex5-u-boot.dtsi b/arch/arm/dts/socfpga_agilex5-u-boot.dtsi
index a8167e5..8d6503d 100644
--- a/arch/arm/dts/socfpga_agilex5-u-boot.dtsi
+++ b/arch/arm/dts/socfpga_agilex5-u-boot.dtsi
@@ -3,6 +3,7 @@
* U-Boot additions
*
* Copyright (C) 2024 Intel Corporation <www.intel.com>
+ * Copyright (C) 2025 Altera Corporation <www.altera.com>
*/
#include "socfpga_soc64_fit-u-boot.dtsi"
@@ -13,6 +14,659 @@
#size-cells = <2>;
bootph-all;
};
+
+ soc {
+ bootph-all;
+
+ socfpga_ccu_config: socfpga-ccu-config {
+ compatible = "intel,socfpga-dtreg";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ bootph-all;
+
+ /* DSU */
+ i_ccu_caiu0@1c000000 {
+ reg = <0x1c000000 0x00001000>;
+ intel,offset-settings =
+ /* CAIUMIFSR */
+ <0x000003c4 0x00000000 0x07070777>,
+ /* DII1_MPFEREGS */
+ <0x00000414 0x00018000 0xffffffff>,
+ <0x00000418 0x00000000 0x000000ff>,
+ <0x00000410 0xc0e00200 0xc1f03e1f>,
+ /* DII2_GICREGS */
+ <0x00000424 0x0001d000 0xffffffff>,
+ <0x00000428 0x00000000 0x000000ff>,
+ <0x00000420 0xc0800400 0xc1f03e1f>,
+ /* NCAIU0_LWSOC2FPGA */
+ <0x00000444 0x00020000 0xffffffff>,
+ <0x00000448 0x00000000 0x000000ff>,
+ <0x00000440 0xc1100006 0xc1f03e1f>,
+ /* NCAIU0_SOC2FPGA_1G */
+ <0x00000454 0x00040000 0xffffffff>,
+ <0x00000458 0x00000000 0x000000ff>,
+ <0x00000450 0xc1200006 0xc1f03e1f>,
+ /* DMI_SDRAM_2G */
+ <0x00000464 0x00080000 0xffffffff>,
+ <0x00000468 0x00000000 0x000000ff>,
+ /* NCAIU0_SOC2FPGA_16G */
+ <0x00000474 0x00400000 0xffffffff>,
+ <0x00000478 0x00000000 0x000000ff>,
+ <0x00000470 0xc1600006 0xc1f03e1f>,
+ /* DMI_SDRAM_30G */
+ <0x00000484 0x00800000 0xffffffff>,
+ <0x00000488 0x00000000 0x000000ff>,
+ /* NCAIU0_SOC2FPGA_256G */
+ <0x00000494 0x04000000 0xffffffff>,
+ <0x00000498 0x00000000 0x000000ff>,
+ <0x00000490 0xc1a00006 0xc1f03e1f>,
+ /* DMI_SDRAM_480G */
+ <0x000004a4 0x08000000 0xffffffff>,
+ <0x000004a8 0x00000000 0x000000ff>;
+ bootph-all;
+ };
+
+ /* FPGA2SOC */
+ i_ccu_ncaiu0@1c001000 {
+ reg = <0x1c001000 0x00001000>;
+ intel,offset-settings =
+ /* NCAIU0MIFSR */
+ <0x000003c4 0x00000000 0x07070777>,
+ /* PSS */
+ <0x00000404 0x00010000 0xffffffff>,
+ <0x00000408 0x00000000 0x000000ff>,
+ <0x00000400 0xC0F00000 0xc1f03e1f>,
+ /* DII1_MPFEREGS */
+ <0x00000414 0x00018000 0xffffffff>,
+ <0x00000418 0x00000000 0x000000ff>,
+ <0x00000410 0xc0e00200 0xc1f03e1f>,
+ /* NCAIU0_LWSOC2FPGA */
+ <0x00000444 0x00020000 0xffffffff>,
+ <0x00000448 0x00000000 0x000000ff>,
+ <0x00000440 0xc1100006 0xc1f03e1f>,
+ /* NCAIU0_SOC2FPGA_1G */
+ <0x00000454 0x00040000 0xffffffff>,
+ <0x00000458 0x00000000 0x000000ff>,
+ <0x00000450 0xc1200006 0xc1f03e1f>,
+ /* DMI_SDRAM_2G */
+ <0x00000464 0x00080000 0xffffffff>,
+ <0x00000468 0x00000000 0x000000ff>,
+ /* NCAIU0_SOC2FPGA_16G */
+ <0x00000474 0x00400000 0xffffffff>,
+ <0x00000478 0x00000000 0x000000ff>,
+ <0x00000470 0xc1600006 0xc1f03e1f>,
+ /* DMI_SDRAM_30G */
+ <0x00000484 0x00800000 0xffffffff>,
+ <0x00000488 0x00000000 0x000000ff>,
+ /* NCAIU0_SOC2FPGA_256G */
+ <0x00000494 0x04000000 0xffffffff>,
+ <0x00000498 0x00000000 0x000000ff>,
+ <0x00000490 0xc1a00006 0xc1f03e1f>,
+ /* DMI_SDRAM_480G */
+ <0x000004a4 0x08000000 0xffffffff>,
+ <0x000004a8 0x00000000 0x000000ff>;
+ bootph-all;
+ };
+
+ /* GIC_M */
+ i_ccu_ncaiu1@1c002000 {
+ reg = <0x1c002000 0x00001000>;
+ intel,offset-settings =
+ /* NCAIU1MIFSR */
+ <0x000003c4 0x00000000 0x07070777>,
+ /* DMI_SDRAM_2G */
+ <0x00000464 0x00080000 0xffffffff>,
+ <0x00000468 0x00000000 0x000000ff>,
+ /* DMI_SDRAM_30G */
+ <0x00000484 0x00800000 0xffffffff>,
+ <0x00000488 0x00000000 0x000000ff>,
+ /* DMI_SDRAM_480G */
+ <0x000004a4 0x08000000 0xffffffff>,
+ <0x000004a8 0x00000000 0x000000ff>;
+ bootph-all;
+ };
+
+ /* SMMU */
+ i_ccu_ncaiu2@1c003000 {
+ reg = <0x1c003000 0x00001000>;
+ intel,offset-settings =
+ /* NCAIU2MIFSR */
+ <0x000003c4 0x00000000 0x07070777>,
+ /* DMI_SDRAM_2G */
+ <0x00000464 0x00080000 0xffffffff>,
+ <0x00000468 0x00000000 0x000000ff>,
+ /* DMI_SDRAM_30G */
+ <0x00000484 0x00800000 0xffffffff>,
+ <0x00000488 0x00000000 0x000000ff>,
+ /* DMI_SDRAM_480G */
+ <0x000004a4 0x08000000 0xffffffff>,
+ <0x000004a8 0x00000000 0x000000ff>;
+ bootph-all;
+ };
+
+ /* PSS NOC */
+ i_ccu_ncaiu3@1c004000 {
+ reg = <0x1c004000 0x00001000>;
+ intel,offset-settings =
+ /* NCAIU3MIFSR */
+ <0x000003c4 0x00000000 0x07070777>,
+ /* DII1_MPFEREGS */
+ <0x00000414 0x00018000 0xffffffff>,
+ <0x00000418 0x00000000 0x000000ff>,
+ <0x00000410 0xc0e00200 0xc1f03e1f>,
+ /* DMI_SDRAM_2G */
+ <0x00000464 0x00080000 0xffffffff>,
+ <0x00000468 0x00000000 0x000000ff>,
+ /* DMI_SDRAM_30G */
+ <0x00000484 0x00800000 0xffffffff>,
+ <0x00000488 0x00000000 0x000000ff>,
+ /* DMI_SDRAM_480G */
+ <0x000004a4 0x08000000 0xffffffff>,
+ <0x000004a8 0x00000000 0x000000ff>;
+ bootph-all;
+ };
+
+ /* DCE0 */
+ i_ccu_dce0@1c005000 {
+ reg = <0x1c005000 0x00001000>;
+ intel,offset-settings =
+ /* DCEUMIFSR0 */
+ <0x000003c4 0x00000000 0x07070777>,
+ /* DMI_SDRAM_2G */
+ <0x00000464 0x00080000 0xffffffff>,
+ <0x00000468 0x00000000 0x000000ff>,
+ /* DMI_SDRAM_30G */
+ <0x00000484 0x00800000 0xffffffff>,
+ <0x00000488 0x00000000 0x000000ff>,
+ /* DMI_SDRAM_480G */
+ <0x000004a4 0x08000000 0xffffffff>,
+ <0x000004a8 0x00000000 0x000000ff>;
+ bootph-all;
+ };
+
+ /* DCE1 */
+ i_ccu_dce1@1c006000 {
+ reg = <0x1c006000 0x00001000>;
+ intel,offset-settings =
+ /* DCEUMIFSR1 */
+ <0x000003c4 0x00000000 0x07070777>,
+ /* DMI_SDRAM_2G */
+ <0x00000464 0x00080000 0xffffffff>,
+ <0x00000468 0x00000000 0x000000ff>,
+ /* DMI_SDRAM_30G */
+ <0x00000484 0x00800000 0xffffffff>,
+ <0x00000488 0x00000000 0x000000ff>,
+ /* DMI_SDRAM_480G */
+ <0x000004a4 0x08000000 0xffffffff>,
+ <0x000004a8 0x00000000 0x000000ff>;
+ bootph-all;
+ };
+
+ /* DMI0 */
+ i_ccu_dmi0@1c007000 {
+ reg = <0x1c007000 0x00001000>;
+ intel,offset-settings =
+ /* DMIUSMCTCR */
+ <0x00000300 0x00000001 0x00000003>,
+ <0x00000300 0x00000003 0x00000003>;
+ bootph-all;
+ };
+
+ /* DMI1 */
+ i_ccu_dmi0@1c008000 {
+ reg = <0x1c008000 0x00001000>;
+ intel,offset-settings =
+ /* DMIUSMCTCR */
+ <0x00000300 0x00000001 0x00000003>,
+ <0x00000300 0x00000003 0x00000003>;
+ bootph-all;
+ };
+ };
+
+ socfpga_firewall_config: socfpga-firewall-config {
+ compatible = "intel,socfpga-dtreg";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ bootph-all;
+
+ /* L4 peripherals firewall */
+ noc_fw_l4_per@10d21000 {
+ reg = <0x10d21000 0x0000008c>;
+ intel,offset-settings =
+ /* NAND */
+ <0x00000000 0x01010001 0x01010001>,
+ /* USB0 */
+ <0x0000000c 0x01010001 0x01010001>,
+ /* USB1 */
+ <0x00000010 0x01010001 0x01010001>,
+ /* SPI_MAIN0 */
+ <0x0000001c 0x01010301 0x01010301>,
+ /* SPI_MAIN1 */
+ <0x00000020 0x01010301 0x01010301>,
+ /* SPI_SECONDARY0 */
+ <0x00000024 0x01010301 0x01010301>,
+ /* SPI_SECONDARY1 */
+ <0x00000028 0x01010301 0x01010301>,
+ /* EMAC0 */
+ <0x0000002c 0x01010001 0x01010001>,
+ /* EMAC1 */
+ <0x00000030 0x01010001 0x01010001>,
+ /* EMAC2 */
+ <0x00000034 0x01010001 0x01010001>,
+ /* SDMMC */
+ <0x00000040 0x01010001 0x01010001>,
+ /* GPIO0 */
+ <0x00000044 0x01010301 0x01010301>,
+ /* GPIO1 */
+ <0x00000048 0x01010301 0x01010301>,
+ /* I2C0 */
+ <0x00000050 0x01010301 0x01010301>,
+ /* I2C1 */
+ <0x00000054 0x01010301 0x01010301>,
+ /* I2C2 */
+ <0x00000058 0x01010301 0x01010301>,
+ /* I2C3 */
+ <0x0000005c 0x01010301 0x01010301>,
+ /* I2C4 */
+ <0x00000060 0x01010301 0x01010301>,
+ /* SP_TIMER0 */
+ <0x00000064 0x01010301 0x01010301>,
+ /* SP_TIMER1 */
+ <0x00000068 0x01010301 0x01010301>,
+ /* UART0 */
+ <0x0000006c 0x01010301 0x01010301>,
+ /* UART1 */
+ <0x00000070 0x01010301 0x01010301>,
+ /* I3C0 */
+ <0x00000074 0x01010301 0x01010301>,
+ /* I3C1 */
+ <0x00000078 0x01010301 0x01010301>,
+ /* DMA0 */
+ <0x0000007c 0x01010001 0x01010001>,
+ /* DMA1 */
+ <0x00000080 0x01010001 0x01010001>,
+ /* COMBO_PHY */
+ <0x00000084 0x01010001 0x01010001>,
+ /* NAND_SDMA */
+ <0x00000088 0x01010301 0x01010301>;
+ bootph-all;
+ };
+
+ /* L4 system firewall */
+ noc_fw_l4_sys@10d21100 {
+ reg = <0x10d21100 0x00000098>;
+ intel,offset-settings =
+ /* DMA_ECC */
+ <0x00000008 0x01010001 0x01010001>,
+ /* EMAC0RX_ECC */
+ <0x0000000c 0x01010001 0x01010001>,
+ /* EMAC0TX_ECC */
+ <0x00000010 0x01010001 0x01010001>,
+ /* EMAC1RX_ECC */
+ <0x00000014 0x01010001 0x01010001>,
+ /* EMAC1TX_ECC */
+ <0x00000018 0x01010001 0x01010001>,
+ /* EMAC2RX_ECC */
+ <0x0000001c 0x01010001 0x01010001>,
+ /* EMAC2TX_ECC */
+ <0x00000020 0x01010001 0x01010001>,
+ /* NAND_ECC */
+ <0x0000002c 0x01010001 0x01010001>,
+ /* NAND_READ_ECC */
+ <0x00000030 0x01010001 0x01010001>,
+ /* NAND_WRITE_ECC */
+ <0x00000034 0x01010001 0x01010001>,
+ /* OCRAM_ECC */
+ <0x00000038 0x01010001 0x01010001>,
+ /* SDMMC_ECC */
+ <0x00000040 0x01010001 0x01010001>,
+ /* USB0_ECC */
+ <0x00000044 0x01010001 0x01010001>,
+ /* USB1_CACHEECC */
+ <0x00000048 0x01010001 0x01010001>,
+ /* CLOCK_MANAGER */
+ <0x0000004c 0x01010001 0x01010001>,
+ /* IO_MANAGER */
+ <0x00000054 0x01010001 0x01010001>,
+ /* RESET_MANAGER */
+ <0x00000058 0x01010001 0x01010001>,
+ /* SYSTEM_MANAGER */
+ <0x0000005c 0x01010001 0x01010001>,
+ /* OSC0_TIMER */
+ <0x00000060 0x01010301 0x01010301>,
+ /* OSC1_TIMER0*/
+ <0x00000064 0x01010301 0x01010301>,
+ /* WATCHDOG0 */
+ <0x00000068 0x01010301 0x01010301>,
+ /* WATCHDOG1 */
+ <0x0000006c 0x01010301 0x01010301>,
+ /* WATCHDOG2 */
+ <0x00000070 0x01010301 0x01010301>,
+ /* WATCHDOG3 */
+ <0x00000074 0x01010301 0x01010301>,
+ /* DAP */
+ <0x00000078 0x03010001 0x03010001>,
+ /* WATCHDOG4 */
+ <0x0000007c 0x01010301 0x01010301>,
+ /* POWER_MANAGER */
+ <0x00000080 0x01010001 0x01010001>,
+ /* USB1_RXECC */
+ <0x00000084 0x01010001 0x01010001>,
+ /* USB1_TXECC */
+ <0x00000088 0x01010001 0x01010001>,
+ /* L4_NOC_PROBES */
+ <0x00000090 0x01010001 0x01010001>,
+ /* L4_NOC_QOS */
+ <0x00000094 0x01010001 0x01010001>;
+ bootph-all;
+ };
+
+ /* Light weight SoC2FPGA */
+ noc_fw_lwsoc2fpga@10d21300 {
+ reg = <0x10d21300 0x0000004>;
+ intel,offset-settings =
+ /* LWSOC2FPGA_CSR */
+ <0x00000000 0x0ffe0301 0x0ffe0301>;
+ bootph-all;
+ };
+
+ /* SoC2FPGA */
+ noc_fw_soc2fpga@10d21200 {
+ reg = <0x10d21200 0x0000004>;
+ intel,offset-settings =
+ /* SOC2FPGA_CSR */
+ <0x00000000 0x0ffe0301 0x0ffe0301>;
+ bootph-all;
+ };
+
+ /* TCU */
+ noc_fw_tcu@10d21400 {
+ reg = <0x10d21400 0x0000004>;
+ intel,offset-settings =
+ /* TCU_CSR */
+ <0x00000000 0x01010001 0x01010001>;
+ bootph-all;
+ };
+ };
+
+ socfpga_ccu_ddr_interleaving_off: socfpga-ccu-ddr-interleaving-off {
+ compatible = "intel,socfpga-dtreg";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ bootph-all;
+
+ /* DSU */
+ i_ccu_caiu0@1c000000 {
+ reg = <0x1c000000 0x00001000>;
+ intel,offset-settings =
+ /* CAIUAMIGR */
+ <0x000003c0 0x00000003 0x0000001f>,
+ /* DMI_SDRAM_2G */
+ <0x00000460 0x81300006 0xc1f03e1f>,
+ /* DMI_SDRAM_30G */
+ <0x00000480 0x81700006 0xc1f03e1f>,
+ /* DMI_SDRAM_480G */
+ <0x000004a0 0x81b00006 0xc1f03e1f>;
+ bootph-all;
+ };
+
+ /* FPGA2SOC */
+ i_ccu_ncaiu0@1c001000 {
+ reg = <0x1c001000 0x00001000>;
+ intel,offset-settings =
+ /* NCAIU0AMIGR */
+ <0x000003c0 0x00000003 0x0000001f>,
+ /* DMI_SDRAM_2G */
+ <0x00000460 0x81300006 0xc1f03e1f>,
+ /* DMI_SDRAM_30G */
+ <0x00000480 0x81700006 0xc1f03e1f>,
+ /* DMI_SDRAM_480G */
+ <0x000004a0 0x81b00006 0xc1f03e1f>;
+ bootph-all;
+ };
+
+ /* GIC_M */
+ i_ccu_ncaiu1@1c002000 {
+ reg = <0x1c002000 0x00001000>;
+ intel,offset-settings =
+ /* NCAIU1AMIGR */
+ <0x000003c0 0x00000003 0x0000001f>,
+ /* DMI_SDRAM_2G */
+ <0x00000460 0x81300006 0xc1f03e1f>,
+ /* DMI_SDRAM_30G */
+ <0x00000480 0x81700006 0xc1f03e1f>,
+ /* DMI_SDRAM_480G */
+ <0x000004a0 0x81b00006 0xc1f03e1f>;
+ bootph-all;
+ };
+
+ /* SMMU */
+ i_ccu_ncaiu2@1c003000 {
+ reg = <0x1c003000 0x00001000>;
+ intel,offset-settings =
+ /* NCAIU2AMIGR */
+ <0x000003c0 0x00000003 0x0000001f>,
+ /* DMI_SDRAM_2G */
+ <0x00000460 0x81300006 0xc1f03e1f>,
+ /* DMI_SDRAM_30G */
+ <0x00000480 0x81700006 0xc1f03e1f>,
+ /* DMI_SDRAM_480G */
+ <0x000004a0 0x81b00006 0xc1f03e1f>;
+ bootph-all;
+ };
+
+ /* PSS NOC */
+ i_ccu_ncaiu3@1c004000 {
+ reg = <0x1c004000 0x00001000>;
+ intel,offset-settings =
+ /* NCAIU3AMIGR */
+ <0x000003c0 0x00000003 0x0000001f>,
+ /* DMI_SDRAM_2G */
+ <0x00000460 0x81300006 0xc1f03e1f>,
+ /* DMI_SDRAM_30G */
+ <0x00000480 0x81700006 0xc1f03e1f>,
+ /* DMI_SDRAM_480G */
+ <0x000004a0 0x81b00006 0xc1f03e1f>;
+ bootph-all;
+ };
+
+ /* DCE0 */
+ i_ccu_dce0@1c005000 {
+ reg = <0x1c005000 0x00001000>;
+ intel,offset-settings =
+ /* DCEUAMIGR0 */
+ <0x000003c0 0x00000003 0x0000001f>,
+ /* DMI_SDRAM_2G */
+ <0x00000460 0x81300006 0xc1f03e1f>,
+ /* DMI_SDRAM_30G */
+ <0x00000480 0x81700006 0xc1f03e1f>,
+ /* DMI_SDRAM_480G */
+ <0x000004a0 0x81b00006 0xc1f03e1f>;
+ bootph-all;
+ };
+
+ /* DCE1 */
+ i_ccu_dce1@1c006000 {
+ reg = <0x1c006000 0x00001000>;
+ intel,offset-settings =
+ /* DCEUAMIGR1 */
+ <0x000003c0 0x00000003 0x0000001f>,
+ /* DMI_SDRAM_2G */
+ <0x00000460 0x81300006 0xc1f03e1f>,
+ /* DMI_SDRAM_30G */
+ <0x00000480 0x81700006 0xc1f03e1f>,
+ /* DMI_SDRAM_480G */
+ <0x000004a0 0x81b00006 0xc1f03e1f>;
+ bootph-all;
+ };
+ };
+
+ socfpga_ccu_ddr_interleaving_on: socfpga-ccu-ddr-interleaving-on {
+ compatible = "intel,socfpga-dtreg";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ bootph-all;
+
+ /* DSU */
+ i_ccu_caiu0@1c000000 {
+ reg = <0x1c000000 0x00001000>;
+ intel,offset-settings =
+ /* CAIUAMIGR */
+ <0x000003c0 0x00000001 0x0000001f>,
+ /* DMI_SDRAM_2G */
+ <0x00000460 0x81200006 0xc1f03e1f>,
+ /* DMI_SDRAM_30G */
+ <0x00000480 0x81600006 0xc1f03e1f>,
+ /* DMI_SDRAM_480G */
+ <0x000004a0 0x81a00006 0xc1f03e1f>;
+ bootph-all;
+ };
+
+ /* FPGA2SOC */
+ i_ccu_ncaiu0@1c001000 {
+ reg = <0x1c001000 0x00001000>;
+ intel,offset-settings =
+ /* NCAIU0AMIGR */
+ <0x000003c0 0x00000001 0x0000001f>,
+ /* DMI_SDRAM_2G */
+ <0x00000460 0x81200006 0xc1f03e1f>,
+ /* DMI_SDRAM_30G */
+ <0x00000480 0x81600006 0xc1f03e1f>,
+ /* DMI_SDRAM_480G */
+ <0x000004a0 0x81a00006 0xc1f03e1f>;
+ bootph-all;
+ };
+
+ /* GIC_M */
+ i_ccu_ncaiu1@1c002000 {
+ reg = <0x1c002000 0x00001000>;
+ intel,offset-settings =
+ /* NCAIU1AMIGR */
+ <0x000003c0 0x00000001 0x0000001f>,
+ /* DMI_SDRAM_2G */
+ <0x00000460 0x81200006 0xc1f03e1f>,
+ /* DMI_SDRAM_30G */
+ <0x00000480 0x81600006 0xc1f03e1f>,
+ /* DMI_SDRAM_480G */
+ <0x000004a0 0x81a00006 0xc1f03e1f>;
+ bootph-all;
+ };
+
+ /* SMMU */
+ i_ccu_ncaiu2@1c003000 {
+ reg = <0x1c003000 0x00001000>;
+ intel,offset-settings =
+ /* NCAIU2AMIGR */
+ <0x000003c0 0x00000001 0x0000001f>,
+ /* DMI_SDRAM_2G */
+ <0x00000460 0x81200006 0xc1f03e1f>,
+ /* DMI_SDRAM_30G */
+ <0x00000480 0x81600006 0xc1f03e1f>,
+ /* DMI_SDRAM_480G */
+ <0x000004a0 0x81a00006 0xc1f03e1f>;
+ bootph-all;
+ };
+
+ /* PSS NOC */
+ i_ccu_ncaiu3@1c004000 {
+ reg = <0x1c004000 0x00001000>;
+ intel,offset-settings =
+ /* NCAIU3AMIGR */
+ <0x000003c0 0x00000001 0x0000001f>,
+ /* DMI_SDRAM_2G */
+ <0x00000460 0x81200006 0xc1f03e1f>,
+ /* DMI_SDRAM_30G */
+ <0x00000480 0x81600006 0xc1f03e1f>,
+ /* DMI_SDRAM_480G */
+ <0x000004a0 0x81a00006 0xc1f03e1f>;
+ bootph-all;
+ };
+
+ /* DCE0 */
+ i_ccu_dce0@1c005000 {
+ reg = <0x1c005000 0x00001000>;
+ intel,offset-settings =
+ /* DCEUAMIGR0 */
+ <0x000003c0 0x00000001 0x0000001f>,
+ /* DMI_SDRAM_2G */
+ <0x00000460 0x81200006 0xc1f03e1f>,
+ /* DMI_SDRAM_30G */
+ <0x00000480 0x81600006 0xc1f03e1f>,
+ /* DMI_SDRAM_480G */
+ <0x000004a0 0x81a00006 0xc1f03e1f>;
+ bootph-all;
+ };
+
+ /* DCE1 */
+ i_ccu_dce1@1c006000 {
+ reg = <0x1c006000 0x00001000>;
+ intel,offset-settings =
+ /* DCEUAMIGR1 */
+ <0x000003c0 0x00000001 0x0000001f>,
+ /* DMI_SDRAM_2G */
+ <0x00000460 0x81200006 0xc1f03e1f>,
+ /* DMI_SDRAM_30G */
+ <0x00000480 0x81600006 0xc1f03e1f>,
+ /* DMI_SDRAM_480G */
+ <0x000004a0 0x81a00006 0xc1f03e1f>;
+ bootph-all;
+ };
+ };
+
+ socfpga_smmu_secure_config: socfpga-smmu-secure-config {
+ compatible = "intel,socfpga-dtreg";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ bootph-all;
+
+ /* System manager */
+ i_sys_mgt_sysmgr_csr@10d12000 {
+ reg = <0x10d12000 0x00000500>;
+ intel,offset-settings =
+ /* dma_tbu_stream_ctrl_reg_0_dma0 */
+ <0x0000017c 0x00000000 0x0000003f>,
+ /* dma_tbu_stream_ctrl_reg_0_dma1 */
+ <0x00000180 0x00000000 0x0000003f>,
+ /* sdm_tbu_stream_ctrl_reg_1_sdm */
+ <0x00000184 0x00000000 0x0000003f>,
+ /* io_tbu_stream_ctrl_reg_2_usb2 */
+ <0x00000188 0x00000000 0x0000003f>,
+ /* io_tbu_stream_ctrl_reg_2_sdmmc */
+ <0x00000190 0x00000000 0x0000003f>,
+ /* io_tbu_stream_ctrl_reg_2_nand */
+ <0x00000194 0x00000000 0x0000003f>,
+ /* io_tbu_stream_ctrl_reg_2_etr */
+ <0x00000198 0x00000000 0x0000003f>,
+ /* tsn_tbu_stream_ctrl_reg_3_tsn0 */
+ <0x0000019c 0x00000000 0x0000003f>,
+ /* tsn_tbu_stream_ctrl_reg_3_tsn1 */
+ <0x000001a0 0x00000000 0x0000003f>,
+ /* tsn_tbu_stream_ctrl_reg_3_tsn2 */
+ <0x000001a4 0x00000000 0x0000003f>;
+ bootph-all;
+ };
+ };
+
+ socfpga_noc_fw_mpfe_csr: socfpga-noc-fw-mpfe-csr {
+ compatible = "intel,socfpga-dtreg";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ bootph-all;
+
+ /* noc fw mpfe csr */
+ i_noc_fw_mpfe_csr@18000d00 {
+ reg = <0x18000d00 0x00000100>;
+ intel,offset-settings =
+ /* mpfe scr io96b0 reg*/
+ <0x00000000 0x00000001 0x00010101>,
+ /* mpfe scr io96b1 reg*/
+ <0x00000004 0x00000001 0x00010101>,
+ /* mpfe scr noc csr*/
+ <0x00000008 0x00000001 0x00010101>;
+ bootph-all;
+ };
+ };
+ };
};
&clkmgr {
@@ -57,6 +711,13 @@
bootph-all;
};
+&sdr {
+ compatible = "intel,sdr-ctl-agilex5";
+ reg = <0x18000000 0x400000>;
+ resets = <&rst DDRSCH_RESET>;
+ bootph-all;
+};
+
&sysmgr {
compatible = "altr,sys-mgr", "syscon";
bootph-all;
diff --git a/arch/arm/dts/socfpga_agilex5.dtsi b/arch/arm/dts/socfpga_agilex5.dtsi
index 03b5504..788e44f 100644
--- a/arch/arm/dts/socfpga_agilex5.dtsi
+++ b/arch/arm/dts/socfpga_agilex5.dtsi
@@ -1,6 +1,7 @@
// SPDX-License-Identifier: GPL-2.0
/*
* Copyright (C) 2024 Intel Corporation <www.intel.com>
+ * Copyright (C) 2025 Altera Corporation <www.altera.com>
*/
/dts-v1/;
@@ -544,6 +545,13 @@
status = "disabled";
};
+ sdr: sdr@18000000 {
+ compatible = "intel,sdr-ctl-agilex5";
+ reg = <0x18000000 0x400000>;
+ resets = <&rst DDRSCH_RESET>;
+ bootph-all;
+ };
+
/* QSPI address not available yet */
qspi: spi@108d2000 {
compatible = "cdns,qspi-nor";
diff --git a/arch/arm/dts/socfpga_agilex5_socdk-u-boot.dtsi b/arch/arm/dts/socfpga_agilex5_socdk-u-boot.dtsi
index 9eb21d6..e08dd55 100644
--- a/arch/arm/dts/socfpga_agilex5_socdk-u-boot.dtsi
+++ b/arch/arm/dts/socfpga_agilex5_socdk-u-boot.dtsi
@@ -3,6 +3,7 @@
* U-Boot additions
*
* Copyright (C) 2024 Intel Corporation <www.intel.com>
+ * Copyright (C) 2025 Altera Corporation <www.altera.com>
*/
#include "socfpga_agilex5-u-boot.dtsi"
@@ -21,11 +22,38 @@
};
};
- memory {
- /* 8GB */
- reg = <0 0x80000000 0 0x80000000>,
- <8 0x80000000 1 0x80000000>;
- };
+ /*
+ * Both Memory base address and size default info is retrieved from HW setting.
+ * Reconfiguration / Overwrite these info can be done with examples below.
+ */
+ /*
+ * Example for memory size with 2GB:
+ * memory {
+ * reg = <0x0 0x80000000 0x0 0x80000000>;
+ * };
+ */
+ /*
+ * Example for memory size with 8GB:
+ * memory {
+ * reg = <0x0 0x80000000 0x0 0x80000000>,
+ * <0x8 0x80000000 0x1 0x80000000>;
+ * };
+ */
+ /*
+ * Example for memory size with 32GB:
+ * memory {
+ * reg = <0x0 0x80000000 0x0 0x80000000>,
+ * <0x8 0x80000000 0x7 0x80000000>;
+ * };
+ */
+ /*
+ * Example for memory size with 512GB:
+ * memory {
+ * reg = <0x0 0x80000000 0x0 0x80000000>,
+ * <0x8 0x80000000 0x7 0x80000000>,
+ * <0x88 0x00000000 0x78 0x00000000>;
+ * };
+ */
chosen {
stdout-path = "serial0:115200n8";
@@ -122,3 +150,36 @@
bootph-all;
};
+&gmac0 {
+ status = "okay";
+ phy-mode = "rgmii";
+ phy-handle = <&emac0_phy0>;
+
+ max-frame-size = <9000>;
+
+ mdio0 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ compatible = "snps,dwxgmac-mdio";
+ emac0_phy0: ethernet-phy@0 {
+ reg = <0>;
+ };
+ };
+};
+
+&gmac2 {
+ status = "okay";
+ phy-mode = "rgmii";
+ phy-handle = <&emac2_phy0>;
+
+ max-frame-size = <9000>;
+
+ mdio0 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ compatible = "snps,dwxgmac-mdio";
+ emac2_phy0: ethernet-phy@0 {
+ reg = <0>;
+ };
+ };
+};
diff --git a/arch/arm/dts/socfpga_agilex5_socdk.dts b/arch/arm/dts/socfpga_agilex5_socdk.dts
index 852e1e5..ca87e99 100644
--- a/arch/arm/dts/socfpga_agilex5_socdk.dts
+++ b/arch/arm/dts/socfpga_agilex5_socdk.dts
@@ -62,6 +62,10 @@
status = "okay";
};
+&i2c3 {
+ status = "okay";
+};
+
&i3c0 {
status = "okay";
};
diff --git a/arch/arm/dts/stih410-b2260-u-boot.dtsi b/arch/arm/dts/stih410-b2260-u-boot.dtsi
index 3b080ac..e9d7ec9 100644
--- a/arch/arm/dts/stih410-b2260-u-boot.dtsi
+++ b/arch/arm/dts/stih410-b2260-u-boot.dtsi
@@ -14,20 +14,30 @@
};
};
+ clk_usb: clk-usb {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <100000000>;
+ };
+
ohci0: usb@9a03c00 {
compatible = "generic-ohci";
+ clocks = <&clk_usb>;
};
ehci0: usb@9a03e00 {
compatible = "generic-ehci";
+ clocks = <&clk_usb>;
};
ohci1: usb@9a83c00 {
compatible = "generic-ohci";
+ clocks = <&clk_usb>;
};
ehci1: usb@9a83e00 {
compatible = "generic-ehci";
+ clocks = <&clk_usb>;
};
};
};
diff --git a/arch/arm/dts/tegra124-nyan-big-u-boot.dtsi b/arch/arm/dts/tegra124-nyan-big-u-boot.dtsi
index 376dcdf..8a629bf 100644
--- a/arch/arm/dts/tegra124-nyan-big-u-boot.dtsi
+++ b/arch/arm/dts/tegra124-nyan-big-u-boot.dtsi
@@ -4,16 +4,9 @@
* Written by Simon Glass <sjg@chromium.org>
*/
-#include "tegra-u-boot.dtsi"
+#include "tegra124-u-boot.dtsi"
/ {
- host1x@50000000 {
- bootph-all;
- dc@54200000 {
- bootph-all;
- };
- };
-
spi@7000d400 {
spi-deactivate-delay = <500>;
spi-max-frequency = <3000000>;
diff --git a/arch/arm/dts/tegra124-u-boot.dtsi b/arch/arm/dts/tegra124-u-boot.dtsi
index 7c11972..6a02714 100644
--- a/arch/arm/dts/tegra124-u-boot.dtsi
+++ b/arch/arm/dts/tegra124-u-boot.dtsi
@@ -1,3 +1,16 @@
#include <config.h>
#include "tegra-u-boot.dtsi"
+
+/ {
+ host1x@50000000 {
+ bootph-all;
+ dc@54200000 {
+ bootph-all;
+ };
+
+ dc@54240000 {
+ bootph-all;
+ };
+ };
+};
diff --git a/arch/arm/dts/tegra124.dtsi b/arch/arm/dts/tegra124.dtsi
index ffec9ca..cac9b11 100644
--- a/arch/arm/dts/tegra124.dtsi
+++ b/arch/arm/dts/tegra124.dtsi
@@ -136,6 +136,38 @@
status = "disabled";
};
+ dsi@54300000 {
+ compatible = "nvidia,tegra124-dsi";
+ reg = <0x54300000 0x00040000>;
+ clocks = <&tegra_car TEGRA124_CLK_DSIA>,
+ <&tegra_car TEGRA124_CLK_DSIALP>,
+ <&tegra_car TEGRA124_CLK_PLL_D_OUT0>;
+ clock-names = "dsi", "lp", "parent";
+ resets = <&tegra_car 48>;
+ reset-names = "dsi";
+ nvidia,mipi-calibrate = <&mipi 0x060>; /* DSIA & DSIB pads */
+ status = "disabled";
+
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+
+ dsi@54400000 {
+ compatible = "nvidia,tegra124-dsi";
+ reg = <0x54400000 0x00040000>;
+ clocks = <&tegra_car TEGRA124_CLK_DSIB>,
+ <&tegra_car TEGRA124_CLK_DSIBLP>,
+ <&tegra_car TEGRA124_CLK_PLL_D_OUT0>;
+ clock-names = "dsi", "lp", "parent";
+ resets = <&tegra_car 82>;
+ reset-names = "dsi";
+ nvidia,mipi-calibrate = <&mipi 0x180>; /* DSIC & DSID pads */
+ status = "disabled";
+
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+
sor@54540000 {
compatible = "nvidia,tegra124-sor";
reg = <0x54540000 0x00040000>;
@@ -737,6 +769,13 @@
#thermal-sensor-cells = <1>;
};
+ mipi: mipi@700e3000 {
+ compatible = "nvidia,tegra124-mipi";
+ reg = <0x700e3000 0x100>;
+ clocks = <&tegra_car TEGRA124_CLK_MIPI_CAL>;
+ #nvidia,mipi-calibrate-cells = <1>;
+ };
+
dfll: clock@70110000 {
compatible = "nvidia,tegra124-dfll";
reg = <0x70110000 0x100>, /* DFLL control */
diff --git a/arch/arm/dts/tegra20-acer-a500-picasso.dts b/arch/arm/dts/tegra20-acer-a500-picasso.dts
new file mode 100644
index 0000000..0c30148
--- /dev/null
+++ b/arch/arm/dts/tegra20-acer-a500-picasso.dts
@@ -0,0 +1,508 @@
+// SPDX-License-Identifier: GPL-2.0
+/dts-v1/;
+
+#include <dt-bindings/input/input.h>
+#include "tegra20.dtsi"
+
+/ {
+ model = "Acer Iconia Tab A500";
+ compatible = "acer,picasso", "nvidia,tegra20";
+
+ chosen {
+ stdout-path = &uartd;
+ };
+
+ aliases {
+ i2c0 = &pwr_i2c;
+
+ mmc0 = &sdmmc4; /* eMMC */
+ mmc1 = &sdmmc3; /* MicroSD */
+
+ rtc0 = &pmic;
+ rtc1 = "/rtc@7000e000";
+
+ usb0 = &usb1;
+ usb1 = &usb3;
+ };
+
+ memory {
+ device_type = "memory";
+ reg = <0x00000000 0x40000000>;
+ };
+
+ host1x@50000000 {
+ dc@54200000 {
+ rgb {
+ status = "okay";
+
+ nvidia,panel = <&panel>;
+ };
+ };
+ };
+
+ pinmux@70000014 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&state_default>;
+
+ state_default: pinmux {
+ ata {
+ nvidia,pins = "ata";
+ nvidia,function = "ide";
+ };
+ atb {
+ nvidia,pins = "atb", "gma", "gme";
+ nvidia,function = "sdio4";
+ };
+ atc {
+ nvidia,pins = "atc";
+ nvidia,function = "nand";
+ };
+ atd {
+ nvidia,pins = "atd", "ate", "gmb", "spia",
+ "spib", "spic";
+ nvidia,function = "gmi";
+ };
+ cdev1 {
+ nvidia,pins = "cdev1";
+ nvidia,function = "plla_out";
+ };
+ cdev2 {
+ nvidia,pins = "cdev2";
+ nvidia,function = "pllp_out4";
+ };
+ crtp {
+ nvidia,pins = "crtp", "lm1";
+ nvidia,function = "crt";
+ };
+ csus {
+ nvidia,pins = "csus";
+ nvidia,function = "vi_sensor_clk";
+ };
+ dap1 {
+ nvidia,pins = "dap1";
+ nvidia,function = "dap1";
+ };
+ dap2 {
+ nvidia,pins = "dap2";
+ nvidia,function = "dap2";
+ };
+ dap3 {
+ nvidia,pins = "dap3";
+ nvidia,function = "dap3";
+ };
+ dap4 {
+ nvidia,pins = "dap4";
+ nvidia,function = "dap4";
+ };
+ dta {
+ nvidia,pins = "dta", "dtb", "dtc", "dtd", "dte";
+ nvidia,function = "vi";
+ };
+ dtf {
+ nvidia,pins = "dtf";
+ nvidia,function = "i2c3";
+ };
+ gmc {
+ nvidia,pins = "gmc";
+ nvidia,function = "uartd";
+ };
+ gmd {
+ nvidia,pins = "gmd";
+ nvidia,function = "sflash";
+ };
+ gpu {
+ nvidia,pins = "gpu";
+ nvidia,function = "pwm";
+ };
+ gpu7 {
+ nvidia,pins = "gpu7";
+ nvidia,function = "rtck";
+ };
+ gpv {
+ nvidia,pins = "gpv", "slxa";
+ nvidia,function = "pcie";
+ };
+ hdint {
+ nvidia,pins = "hdint";
+ nvidia,function = "hdmi";
+ };
+ i2cp {
+ nvidia,pins = "i2cp";
+ nvidia,function = "i2cp";
+ };
+ irrx {
+ nvidia,pins = "irrx", "irtx";
+ nvidia,function = "uartb";
+ };
+ kbca {
+ nvidia,pins = "kbca", "kbcb", "kbcc", "kbcd",
+ "kbce", "kbcf";
+ nvidia,function = "kbc";
+ };
+ lcsn {
+ nvidia,pins = "lcsn", "ldc", "lm0", "lpw1",
+ "lsdi", "lvp0";
+ nvidia,function = "rsvd4";
+ };
+ ld0 {
+ nvidia,pins = "ld0", "ld1", "ld2", "ld3", "ld4",
+ "ld5", "ld6", "ld7", "ld8", "ld9",
+ "ld10", "ld11", "ld12", "ld13", "ld14",
+ "ld15", "ld16", "ld17", "ldi", "lhp0",
+ "lhp1", "lhp2", "lhs", "lpp", "lsc0",
+ "lsc1", "lsck", "lsda", "lspi", "lvp1",
+ "lvs";
+ nvidia,function = "displaya";
+ };
+ owc {
+ nvidia,pins = "owc", "spdi", "spdo", "uac";
+ nvidia,function = "rsvd2";
+ };
+ pmc {
+ nvidia,pins = "pmc";
+ nvidia,function = "pwr_on";
+ };
+ rm {
+ nvidia,pins = "rm";
+ nvidia,function = "i2c1";
+ };
+ sdb {
+ nvidia,pins = "sdb", "sdc", "sdd", "slxc", "slxk";
+ nvidia,function = "sdio3";
+ };
+ sdio1 {
+ nvidia,pins = "sdio1";
+ nvidia,function = "sdio1";
+ };
+ slxd {
+ nvidia,pins = "slxd";
+ nvidia,function = "spdif";
+ };
+ spid {
+ nvidia,pins = "spid", "spie", "spif";
+ nvidia,function = "spi1";
+ };
+ spig {
+ nvidia,pins = "spig", "spih";
+ nvidia,function = "spi2_alt";
+ };
+ uaa {
+ nvidia,pins = "uaa", "uab", "uda";
+ nvidia,function = "ulpi";
+ };
+ uad {
+ nvidia,pins = "uad";
+ nvidia,function = "irda";
+ };
+ uca {
+ nvidia,pins = "uca", "ucb";
+ nvidia,function = "uartc";
+ };
+ conf_ata {
+ nvidia,pins = "ata", "atb", "atc", "atd",
+ "cdev1", "cdev2", "csus", "dap1",
+ "dap4", "dte", "dtf", "gma", "gmc",
+ "gme", "gpu", "gpu7", "gpv", "i2cp",
+ "irrx", "irtx", "pta", "rm",
+ "sdc", "sdd", "slxc", "slxd", "slxk",
+ "spdi", "spdo", "uac", "uad", "uda";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ };
+ conf_ate {
+ nvidia,pins = "ate", "dap2", "dap3",
+ "gmd", "owc", "spia", "spib", "spic",
+ "spid", "spie";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_ENABLE>;
+ };
+ conf_ck32 {
+ nvidia,pins = "ck32", "ddrc", "pmca", "pmcb",
+ "pmcc", "pmcd", "pmce", "xm2c", "xm2d";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ };
+ conf_crtp {
+ nvidia,pins = "crtp", "gmb", "slxa", "spig",
+ "spih";
+ nvidia,pull = <TEGRA_PIN_PULL_UP>;
+ nvidia,tristate = <TEGRA_PIN_ENABLE>;
+ };
+ conf_dta {
+ nvidia,pins = "dta", "dtb", "dtc", "dtd", "kbcb";
+ nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ };
+ conf_dte {
+ nvidia,pins = "spif";
+ nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
+ nvidia,tristate = <TEGRA_PIN_ENABLE>;
+ };
+ conf_hdint {
+ nvidia,pins = "hdint", "lcsn", "ldc", "lm1",
+ "lpw1", "lsck", "lsda", "lsdi",
+ "lvp0";
+ nvidia,tristate = <TEGRA_PIN_ENABLE>;
+ };
+ conf_kbca {
+ nvidia,pins = "kbca", "kbcc", "kbcd",
+ "kbce", "kbcf", "sdio1", "uaa",
+ "uab", "uca", "ucb";
+ nvidia,pull = <TEGRA_PIN_PULL_UP>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ };
+ conf_lc {
+ nvidia,pins = "lc", "ls";
+ nvidia,pull = <TEGRA_PIN_PULL_UP>;
+ };
+ conf_ld0 {
+ nvidia,pins = "ld0", "ld1", "ld2", "ld3", "ld4",
+ "ld5", "ld6", "ld7", "ld8", "ld9",
+ "ld10", "ld11", "ld12", "ld13", "ld14",
+ "ld15", "ld16", "ld17", "ldi", "lhp0",
+ "lhp1", "lhp2", "lhs", "lm0", "lpp",
+ "lpw0", "lpw2", "lsc0", "lsc1", "lspi",
+ "lvp1", "lvs", "pmc", "sdb";
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ };
+ conf_ld17_0 {
+ nvidia,pins = "ld17_0";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ };
+ drive_ddc {
+ nvidia,pins = "drive_ddc",
+ "drive_vi1",
+ "drive_sdio1";
+ nvidia,pull-up-strength = <31>;
+ nvidia,pull-down-strength = <31>;
+ nvidia,schmitt = <TEGRA_PIN_ENABLE>;
+ nvidia,high-speed-mode = <TEGRA_PIN_DISABLE>;
+ nvidia,low-power-mode = <TEGRA_PIN_LP_DRIVE_DIV_1>;
+ nvidia,slew-rate-rising = <TEGRA_PIN_SLEW_RATE_SLOWEST>;
+ nvidia,slew-rate-falling = <TEGRA_PIN_SLEW_RATE_SLOWEST>;
+ };
+ drive_dbg {
+ nvidia,pins = "drive_dbg",
+ "drive_vi2",
+ "drive_at1",
+ "drive_ao1";
+ nvidia,pull-up-strength = <31>;
+ nvidia,pull-down-strength = <31>;
+ nvidia,schmitt = <TEGRA_PIN_ENABLE>;
+ nvidia,high-speed-mode = <TEGRA_PIN_DISABLE>;
+ nvidia,low-power-mode = <TEGRA_PIN_LP_DRIVE_DIV_1>;
+ nvidia,slew-rate-rising = <TEGRA_PIN_SLEW_RATE_FASTEST>;
+ nvidia,slew-rate-falling = <TEGRA_PIN_SLEW_RATE_FASTEST>;
+ };
+ };
+
+ state_i2cmux_ddc: pinmux-i2cmux-ddc {
+ ddc {
+ nvidia,pins = "ddc";
+ nvidia,function = "i2c2";
+ };
+
+ pta {
+ nvidia,pins = "pta";
+ nvidia,function = "rsvd4";
+ };
+ };
+
+ state_i2cmux_idle: pinmux-i2cmux-idle {
+ ddc {
+ nvidia,pins = "ddc";
+ nvidia,function = "rsvd4";
+ };
+
+ pta {
+ nvidia,pins = "pta";
+ nvidia,function = "rsvd4";
+ };
+ };
+
+ state_i2cmux_pta: pinmux-i2cmux-pta {
+ ddc {
+ nvidia,pins = "ddc";
+ nvidia,function = "rsvd4";
+ };
+
+ pta {
+ nvidia,pins = "pta";
+ nvidia,function = "i2c2";
+ };
+ };
+ };
+
+ uartd: serial@70006300 {
+ status = "okay";
+ clock-frequency = <216000000>;
+ };
+
+ pwm: pwm@7000a000 {
+ status = "okay";
+ };
+
+ pwr_i2c: i2c@7000d000 {
+ status = "okay";
+ clock-frequency = <100000>;
+
+ pmic: tps6586x@34 {
+ compatible = "ti,tps6586x";
+ reg = <0x34>;
+ interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
+
+ ti,system-power-controller;
+
+ #gpio-cells = <2>;
+ gpio-controller;
+
+ regulators {
+ avdd_usb: ldo3 {
+ regulator-name = "vdd_ldo3,avdd_usb*";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-always-on;
+ regulator-boot-on;
+ };
+
+ vcore_emmc: ldo5 {
+ regulator-name = "vdd_ldo5,vcore_mmc";
+ regulator-min-microvolt = <2850000>;
+ regulator-max-microvolt = <2850000>;
+ };
+ };
+ };
+ };
+
+ usb1: usb@c5000000 {
+ status = "okay";
+ dr_mode = "otg";
+ };
+
+ usb-phy@c5000000 {
+ status = "okay";
+ nvidia,xcvr-setup-use-fuses;
+ nvidia,xcvr-lsfslew = <2>;
+ nvidia,xcvr-lsrslew = <2>;
+ };
+
+ usb3: usb@c5008000 {
+ status = "okay";
+ };
+
+ usb-phy@c5008000 {
+ status = "okay";
+ nvidia,xcvr-setup-use-fuses;
+ nvidia,xcvr-lsfslew = <2>;
+ nvidia,xcvr-lsrslew = <2>;
+ };
+
+ sdmmc3: sdhci@c8000400 {
+ status = "okay";
+ bus-width = <4>;
+
+ cd-gpios = <&gpio TEGRA_GPIO(I, 5) GPIO_ACTIVE_LOW>;
+ wp-gpios = <&gpio TEGRA_GPIO(H, 1) GPIO_ACTIVE_HIGH>;
+ power-gpios = <&gpio TEGRA_GPIO(I, 6) GPIO_ACTIVE_HIGH>;
+
+ vmmc-supply = <&vdd_3v3_sys>;
+ vqmmc-supply = <&vdd_3v3_sys>;
+ };
+
+ sdmmc4: sdhci@c8000600 {
+ status = "okay";
+ bus-width = <8>;
+ non-removable;
+
+ vmmc-supply = <&vcore_emmc>;
+ vqmmc-supply = <&vdd_3v3_sys>;
+ };
+
+ backlight: backlight {
+ compatible = "pwm-backlight";
+
+ enable-gpios = <&gpio TEGRA_GPIO(D, 4) GPIO_ACTIVE_HIGH>;
+ power-supply = <&vdd_3v3_sys>;
+ pwms = <&pwm 2 41667>;
+
+ brightness-levels = <1 35 70 105 140 175 210 255>;
+ default-brightness-level = <5>;
+ };
+
+ /* PMIC has a built-in 32KHz oscillator which is used by PMC */
+ clk32k_in: clock-32k-in {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <32768>;
+ clock-output-names = "tps658621-out32k";
+ };
+
+ gpio-keys {
+ compatible = "gpio-keys";
+
+ key-power {
+ label = "Power";
+ gpios = <&gpio TEGRA_GPIO(I, 3) GPIO_ACTIVE_HIGH>;
+ linux,code = <KEY_ENTER>;
+ };
+
+ key-volume-down {
+ label = "Volume Down";
+ gpios = <&gpio TEGRA_GPIO(Q, 5) GPIO_ACTIVE_LOW>;
+ linux,code = <KEY_DOWN>;
+ };
+
+ key-volume-up {
+ label = "Volume Up";
+ gpios = <&gpio TEGRA_GPIO(Q, 4) GPIO_ACTIVE_LOW>;
+ linux,code = <KEY_UP>;
+ };
+
+ switch-rotation-lock {
+ label = "Rotate-lock";
+ gpios = <&gpio TEGRA_GPIO(Q, 2) GPIO_ACTIVE_HIGH>;
+ linux,code = <SW_ROTATE_LOCK>;
+ };
+ };
+
+ panel: panel {
+ compatible = "simple-panel";
+
+ power-supply = <&vdd_pnl_reg>;
+ enable-gpios = <&gpio TEGRA_GPIO(B, 2) GPIO_ACTIVE_HIGH>;
+
+ backlight = <&backlight>;
+
+ display-timings {
+ timing@0 {
+ clock-frequency = <71200000>;
+
+ hactive = <1280>;
+ hfront-porch = <8>;
+ hback-porch = <18>;
+ hsync-len = <184>;
+
+ vactive = <800>;
+ vfront-porch = <4>;
+ vback-porch = <8>;
+ vsync-len = <3>;
+ };
+ };
+ };
+
+ vdd_3v3_sys: regulator-3v3 {
+ compatible = "regulator-fixed";
+ regulator-name = "vdd_3v3_vs";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-always-on;
+ };
+
+ vdd_pnl_reg: regulator-pnl {
+ compatible = "regulator-fixed";
+ regulator-name = "vdd_panel";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ gpio = <&gpio TEGRA_GPIO(C, 6) GPIO_ACTIVE_HIGH>;
+ enable-active-high;
+ };
+};
diff --git a/arch/arm/dts/tegra30.dtsi b/arch/arm/dts/tegra30.dtsi
index 1177e2a..d5de1ec 100644
--- a/arch/arm/dts/tegra30.dtsi
+++ b/arch/arm/dts/tegra30.dtsi
@@ -218,10 +218,29 @@
dsi@54300000 {
compatible = "nvidia,tegra30-dsi";
reg = <0x54300000 0x00040000>;
- clocks = <&tegra_car TEGRA30_CLK_DSIA>;
+ clocks = <&tegra_car TEGRA30_CLK_DSIA>,
+ <&tegra_car TEGRA30_CLK_PLL_D_OUT0>;
+ clock-names = "dsi", "parent";
resets = <&tegra_car 48>;
reset-names = "dsi";
status = "disabled";
+
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+
+ dsi@54400000 {
+ compatible = "nvidia,tegra30-dsi";
+ reg = <0x54400000 0x00040000>;
+ clocks = <&tegra_car TEGRA30_CLK_DSIB>,
+ <&tegra_car TEGRA30_CLK_PLL_D_OUT0>;
+ clock-names = "dsi", "parent";
+ resets = <&tegra_car 84>;
+ reset-names = "dsi";
+ status = "disabled";
+
+ #address-cells = <1>;
+ #size-cells = <0>;
};
};
diff --git a/arch/arm/include/asm/arch-npcm8xx/gmac.h b/arch/arm/include/asm/arch-npcm8xx/gmac.h
new file mode 100644
index 0000000..f84eedd
--- /dev/null
+++ b/arch/arm/include/asm/arch-npcm8xx/gmac.h
@@ -0,0 +1,18 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+
+#ifndef _NPCM_GMAC_H_
+#define _NPCM_GMAC_H_
+
+/* PCS registers */
+#define PCS_BA 0xF0780000
+#define PCS_IND_AC 0x1FE
+#define SR_MII_MMD 0x3E0000
+#define SR_MII_MMD_CTRL 0x0
+#define SR_MII_MMD_STS 0x2
+#define VR_MII_MMD 0x3F0000
+#define VR_MII_MMD_CTRL1 0x0
+#define VR_MII_MMD_AN_CTRL 0x2
+
+#define LINK_UP_TIMEOUT (3 * CONFIG_SYS_HZ)
+
+#endif
diff --git a/arch/arm/include/asm/arch-rockchip/grf_rk3399.h b/arch/arm/include/asm/arch-rockchip/grf_rk3399.h
index dd89cd2..e6125d6 100644
--- a/arch/arm/include/asm/arch-rockchip/grf_rk3399.h
+++ b/arch/arm/include/asm/arch-rockchip/grf_rk3399.h
@@ -466,18 +466,18 @@
/* GRF_GPIO4C_IOMUX */
GRF_GPIO4C0_SEL_SHIFT = 0,
GRF_GPIO4C0_SEL_MASK = 3 << GRF_GPIO4C0_SEL_SHIFT,
- GRF_UART2DGBB_SIN = 2,
+ GRF_UART2DBGB_SIN = 2,
GRF_HDMII2C_SCL = 3,
GRF_GPIO4C1_SEL_SHIFT = 2,
GRF_GPIO4C1_SEL_MASK = 3 << GRF_GPIO4C1_SEL_SHIFT,
- GRF_UART2DGBB_SOUT = 2,
+ GRF_UART2DBGB_SOUT = 2,
GRF_HDMII2C_SDA = 3,
GRF_GPIO4C2_SEL_SHIFT = 4,
GRF_GPIO4C2_SEL_MASK = 3 << GRF_GPIO4C2_SEL_SHIFT,
GRF_PWM_0 = 1,
GRF_GPIO4C3_SEL_SHIFT = 6,
GRF_GPIO4C3_SEL_MASK = 3 << GRF_GPIO4C3_SEL_SHIFT,
- GRF_UART2DGBC_SIN = 1,
+ GRF_UART2DBGC_SIN = 1,
GRF_GPIO4C4_SEL_SHIFT = 8,
GRF_GPIO4C4_SEL_MASK = 3 << GRF_GPIO4C4_SEL_SHIFT,
GRF_UART2DBGC_SOUT = 1,
diff --git a/arch/arm/include/asm/arch-tegra124/clock-tables.h b/arch/arm/include/asm/arch-tegra124/clock-tables.h
index 9f53125..055948e 100644
--- a/arch/arm/include/asm/arch-tegra124/clock-tables.h
+++ b/arch/arm/include/asm/arch-tegra124/clock-tables.h
@@ -24,6 +24,7 @@
CLOCK_ID_XCPU = CLOCK_ID_FIRST_SIMPLE,
CLOCK_ID_EPCI,
CLOCK_ID_SFROM32KHZ,
+ CLOCK_ID_DISPLAY2,
CLOCK_ID_DP, /* Special for Tegra124 */
/* These are the base clocks (inputs to the Tegra SoC) */
@@ -37,7 +38,6 @@
* These are clock IDs that are used in table clock_source[][]
* but will not be assigned as a clock source for any peripheral.
*/
- CLOCK_ID_DISPLAY2,
CLOCK_ID_CGENERAL2,
CLOCK_ID_CGENERAL3,
CLOCK_ID_MEMORY2,
diff --git a/arch/arm/include/asm/arch-tegra210/clock-tables.h b/arch/arm/include/asm/arch-tegra210/clock-tables.h
index c6d7487..5c4d7fc 100644
--- a/arch/arm/include/asm/arch-tegra210/clock-tables.h
+++ b/arch/arm/include/asm/arch-tegra210/clock-tables.h
@@ -24,6 +24,7 @@
CLOCK_ID_XCPU = CLOCK_ID_FIRST_SIMPLE,
CLOCK_ID_EPCI,
CLOCK_ID_SFROM32KHZ,
+ CLOCK_ID_DISPLAY2,
CLOCK_ID_DP,
/* These are the base clocks (inputs to the Tegra SoC) */
@@ -37,7 +38,6 @@
* These are clock IDs that are used in table clock_source[][]
* but will not be assigned as a clock source for any peripheral.
*/
- CLOCK_ID_DISPLAY2,
CLOCK_ID_CGENERAL_0,
CLOCK_ID_CGENERAL_1,
CLOCK_ID_CGENERAL2,
diff --git a/arch/arm/include/asm/system.h b/arch/arm/include/asm/system.h
index dbf9ab4..0910822 100644
--- a/arch/arm/include/asm/system.h
+++ b/arch/arm/include/asm/system.h
@@ -239,6 +239,22 @@
void __asm_switch_ttbr(u64 new_ttbr);
/*
+ * armv8_switch_to_el2_prep() - prepare for switch from EL3 to EL2 for ARMv8
+ *
+ * @args: For loading 64-bit OS, fdt address.
+ * For loading 32-bit OS, zero.
+ * @mach_nr: For loading 64-bit OS, zero.
+ * For loading 32-bit OS, machine nr
+ * @fdt_addr: For loading 64-bit OS, zero.
+ * For loading 32-bit OS, fdt address.
+ * @arg4: Input argument.
+ * @entry_point: kernel entry point
+ * @es_flag: execution state flag, ES_TO_AARCH64 or ES_TO_AARCH32
+ */
+void armv8_switch_to_el2_prep(u64 args, u64 mach_nr, u64 fdt_addr,
+ u64 arg4, u64 entry_point, u64 es_flag);
+
+/*
* armv8_switch_to_el2() - switch from EL3 to EL2 for ARMv8
*
* @args: For loading 64-bit OS, fdt address.
diff --git a/arch/arm/lib/xferlist.c b/arch/arm/lib/xferlist.c
index f9c5d88..6425936 100644
--- a/arch/arm/lib/xferlist.c
+++ b/arch/arm/lib/xferlist.c
@@ -8,18 +8,16 @@
#include <bloblist.h>
#include "xferlist.h"
-int xferlist_from_boot_arg(ulong addr, ulong size)
+int xferlist_from_boot_arg(ulong *addr)
{
int ret;
- ret = bloblist_check(saved_args[3], size);
- if (ret)
- return ret;
-
ret = bloblist_check_reg_conv(saved_args[0], saved_args[2],
- saved_args[1]);
+ saved_args[1], saved_args[3]);
if (ret)
return ret;
- return bloblist_reloc((void *)addr, size);
+ *addr = bloblist_get_base();
+
+ return 0;
}
diff --git a/arch/arm/mach-imx/mx6/Kconfig b/arch/arm/mach-imx/mx6/Kconfig
index 4020e16..2f873ed 100644
--- a/arch/arm/mach-imx/mx6/Kconfig
+++ b/arch/arm/mach-imx/mx6/Kconfig
@@ -550,6 +550,7 @@
select DM_THERMAL
select SUPPORT_SPL
imply CMD_DM
+ imply OF_UPSTREAM
config TARGET_PCM058
bool "Phytec PCM058 i.MX6 Quad"
diff --git a/arch/arm/mach-k3/am65x/Kconfig b/arch/arm/mach-k3/am65x/Kconfig
index 72a8298..056ae11 100644
--- a/arch/arm/mach-k3/am65x/Kconfig
+++ b/arch/arm/mach-k3/am65x/Kconfig
@@ -35,6 +35,8 @@
select BOARD_LATE_INIT
select SYS_DISABLE_DCACHE_OPS
select BINMAN
+ select SYSINFO
+ select SPL_SYSINFO if SPL
help
This builds U-Boot for the IOT2050 devices.
diff --git a/arch/arm/mach-k3/j722s/j722s_init.c b/arch/arm/mach-k3/j722s/j722s_init.c
index f8c5c2a..af21137 100644
--- a/arch/arm/mach-k3/j722s/j722s_init.c
+++ b/arch/arm/mach-k3/j722s/j722s_init.c
@@ -27,6 +27,9 @@
u32 bootindex __section(".data");
static struct rom_extended_boot_data bootdata __section(".data");
+#define CTRLMMR_MCU_RST_CTRL (MCU_CTRL_MMR0_BASE + 0x18170)
+#define RST_CTRL_ESM_ERROR_RST_EN_Z_MASK (~BIT(17))
+
static void store_boot_info_from_rom(void)
{
bootindex = *(u32 *)(CONFIG_SYS_K3_BOOT_PARAM_TABLE_INDEX);
@@ -161,11 +164,40 @@
}
}
+static __maybe_unused void enable_mcu_esm_reset(void)
+{
+ /* Set CTRLMMR_MCU_RST_CTRL:MCU_ESM_ERROR_RST_EN_Z to '0' (low active) */
+ u32 stat = readl(CTRLMMR_MCU_RST_CTRL);
+
+ stat &= RST_CTRL_ESM_ERROR_RST_EN_Z_MASK;
+ writel(stat, CTRLMMR_MCU_RST_CTRL);
+}
+
void board_init_f(ulong dummy)
{
+ int ret;
+ struct udevice *dev;
+
k3_spl_init();
k3_mem_init();
setup_qos();
+
+ if (IS_ENABLED(CONFIG_ESM_K3)) {
+ /* Probe/configure ESM0 */
+ ret = uclass_get_device_by_name(UCLASS_MISC, "esm@420000", &dev);
+ if (ret) {
+ printf("esm main init failed: %d\n", ret);
+ return;
+ }
+
+ /* Probe/configure MCUESM */
+ ret = uclass_get_device_by_name(UCLASS_MISC, "esm@4100000", &dev);
+ if (ret) {
+ printf("esm mcu init failed: %d\n", ret);
+ return;
+ }
+ enable_mcu_esm_reset();
+ }
}
static u32 __get_backup_bootmedia(u32 devstat)
diff --git a/arch/arm/mach-mediatek/Kconfig b/arch/arm/mach-mediatek/Kconfig
index 39eea05..e54c456 100644
--- a/arch/arm/mach-mediatek/Kconfig
+++ b/arch/arm/mach-mediatek/Kconfig
@@ -6,9 +6,6 @@
config SYS_VENDOR
default "mediatek"
-config MT8512
- bool "MediaTek MT8512 SoC"
-
choice
prompt "MediaTek board select"
@@ -96,9 +93,8 @@
I2C, I2S, S/PDIF, and several LPDDR3 and LPDDR4 options.
config TARGET_MT8512
- bool "MediaTek MT8512 M1 Board"
+ bool "MediaTek MT8512 SoC"
select ARM64
- select MT8512
help
The MediaTek MT8512 is a ARM64-based SoC with a dual-core Cortex-A53.
including UART, SPI, USB2.0 and OTG, SD and MMC cards, NAND, PWM,
@@ -160,9 +156,8 @@
config MTK_BROM_HEADER_INFO
string
- default "media=nor" if TARGET_MT8518 || TARGET_MT8512 || TARGET_MT7629 || TARGET_MT7622
+ default "media=nor" if TARGET_MT8518 || TARGET_MT8512 || TARGET_MT7629
default "media=emmc" if TARGET_MT8516 || TARGET_MT8365 || TARGET_MT8183
- default "media=snand;nandinfo=2k+64" if TARGET_MT7981 || TARGET_MT7986 || TARGET_MT7987 || TARGET_MT7988
default "lk=1" if TARGET_MT7623
config MTK_TZ_MOVABLE
diff --git a/arch/arm/mach-mediatek/Makefile b/arch/arm/mach-mediatek/Makefile
index 344434c..c11d6ad 100644
--- a/arch/arm/mach-mediatek/Makefile
+++ b/arch/arm/mach-mediatek/Makefile
@@ -4,7 +4,6 @@
obj-$(CONFIG_MTK_TZ_MOVABLE) += tzcfg.o
obj-$(CONFIG_XPL_BUILD) += spl.o
-obj-$(CONFIG_MT8512) += mt8512/
obj-$(CONFIG_TARGET_MT7622) += mt7622/
obj-$(CONFIG_TARGET_MT7623) += mt7623/
obj-$(CONFIG_TARGET_MT7629) += mt7629/
@@ -14,5 +13,6 @@
obj-$(CONFIG_TARGET_MT7988) += mt7988/
obj-$(CONFIG_TARGET_MT8183) += mt8183/
obj-$(CONFIG_TARGET_MT8365) += mt8365/
+obj-$(CONFIG_TARGET_MT8512) += mt8512/
obj-$(CONFIG_TARGET_MT8516) += mt8516/
obj-$(CONFIG_TARGET_MT8518) += mt8518/
diff --git a/arch/arm/mach-rockchip/Kconfig b/arch/arm/mach-rockchip/Kconfig
index 4d3157b..adac11a 100644
--- a/arch/arm/mach-rockchip/Kconfig
+++ b/arch/arm/mach-rockchip/Kconfig
@@ -29,6 +29,7 @@
select CPU_V7A
select SUPPORT_SPL
select SPL
+ imply OF_UPSTREAM
imply USB_FUNCTION_ROCKUSB
imply CMD_ROCKUSB
imply ROCKCHIP_COMMON_BOARD
diff --git a/arch/arm/mach-rockchip/rk3399/rk3399.c b/arch/arm/mach-rockchip/rk3399/rk3399.c
index 1ce43c6..9959707 100644
--- a/arch/arm/mach-rockchip/rk3399/rk3399.c
+++ b/arch/arm/mach-rockchip/rk3399/rk3399.c
@@ -7,6 +7,7 @@
#include <init.h>
#include <log.h>
#include <spl.h>
+#include <spl_gpio.h>
#include <syscon.h>
#include <asm/armv8/mmu.h>
#include <asm/arch-rockchip/bootrom.h>
@@ -15,7 +16,6 @@
#include <asm/arch-rockchip/gpio.h>
#include <asm/arch-rockchip/grf_rk3399.h>
#include <asm/arch-rockchip/hardware.h>
-#include <asm/gpio.h>
#include <linux/bitops.h>
#include <linux/printk.h>
#include <power/regulator.h>
@@ -133,10 +133,31 @@
GRF_GPIO3B7_SEL_MASK,
GRF_UART3_SOUT << GRF_GPIO3B7_SEL_SHIFT);
#else
+ struct rk3399_pmugrf_regs * const pmugrf = (void *)PMUGRF_BASE;
+ struct rockchip_gpio_regs * const gpio = (void *)GPIO0_BASE;
+
+ if (IS_ENABLED(CONFIG_XPL_BUILD) &&
+ (IS_ENABLED(CONFIG_TARGET_CHROMEBOOK_BOB) ||
+ IS_ENABLED(CONFIG_TARGET_CHROMEBOOK_KEVIN))) {
+ rk_setreg(&grf->io_vsel, 1 << 0);
+
+ /*
+ * Let's enable these power rails here, we are already running
+ * the SPI-Flash-based code.
+ */
+ spl_gpio_output(gpio, GPIO(BANK_B, 2), 1); /* PP1500_EN */
+ spl_gpio_set_pull(&pmugrf->gpio0_p, GPIO(BANK_B, 2),
+ GPIO_PULL_NORMAL);
+
+ spl_gpio_output(gpio, GPIO(BANK_B, 4), 1); /* PP3000_EN */
+ spl_gpio_set_pull(&pmugrf->gpio0_p, GPIO(BANK_B, 4),
+ GPIO_PULL_NORMAL);
+ }
+
/* Enable early UART2 channel C on the RK3399 */
rk_clrsetreg(&grf->gpio4c_iomux,
GRF_GPIO4C3_SEL_MASK,
- GRF_UART2DGBC_SIN << GRF_GPIO4C3_SEL_SHIFT);
+ GRF_UART2DBGC_SIN << GRF_GPIO4C3_SEL_SHIFT);
rk_clrsetreg(&grf->gpio4c_iomux,
GRF_GPIO4C4_SEL_MASK,
GRF_UART2DBGC_SOUT << GRF_GPIO4C4_SEL_SHIFT);
diff --git a/arch/arm/mach-rockchip/sdram.c b/arch/arm/mach-rockchip/sdram.c
index 1fb01e1..f7d3282 100644
--- a/arch/arm/mach-rockchip/sdram.c
+++ b/arch/arm/mach-rockchip/sdram.c
@@ -309,6 +309,8 @@
if (ram_top > SZ_4G && top < SZ_4G) {
gd->bd->bi_dram[1].start = SZ_4G;
gd->bd->bi_dram[1].size = ram_top - gd->bd->bi_dram[1].start;
+ } else if (ram_top > SZ_4G && top == SZ_4G) {
+ gd->bd->bi_dram[0].size = ram_top - gd->bd->bi_dram[0].start;
}
#else
#ifdef CONFIG_SPL_OPTEE_IMAGE
@@ -476,6 +478,7 @@
debug("Cannot get DRAM size: %d\n", ret);
return ret;
}
+ gd->ram_base = ram.base;
gd->ram_size = ram.size;
debug("SDRAM base=%lx, size=%lx\n",
(unsigned long)ram.base, (unsigned long)ram.size);
@@ -485,7 +488,8 @@
phys_addr_t board_get_usable_ram_top(phys_size_t total_size)
{
- unsigned long top = CFG_SYS_SDRAM_BASE + SDRAM_MAX_SIZE;
+ /* Make sure U-Boot only uses the space below the 4G address boundary */
+ u64 top = min_t(u64, CFG_SYS_SDRAM_BASE + SDRAM_MAX_SIZE, SZ_4G);
return (gd->ram_top > top) ? top : gd->ram_top;
}
diff --git a/arch/arm/mach-socfpga/Kconfig b/arch/arm/mach-socfpga/Kconfig
index 6b6a162..a76a9fb 100644
--- a/arch/arm/mach-socfpga/Kconfig
+++ b/arch/arm/mach-socfpga/Kconfig
@@ -55,6 +55,7 @@
select BINMAN if SPL_ATF
select CLK
select FPGA_INTEL_SDM_MAILBOX
+ select GICV2
select NCORE_CACHE
select SPL_CLK if SPL
select TARGET_SOCFPGA_SOC64
@@ -64,7 +65,6 @@
select BINMAN if SPL_ATF
select CLK
select FPGA_INTEL_SDM_MAILBOX
- select GICV3
select SPL_CLK if SPL
select TARGET_SOCFPGA_SOC64
@@ -74,6 +74,7 @@
config TARGET_SOCFPGA_ARRIA10
bool
+ select GICV2
select SPL_ALTERA_SDRAM
select SPL_BOARD_INIT if SPL
select SPL_CACHE if SPL
@@ -118,6 +119,7 @@
select ARMV8_SET_SMPEN
select BINMAN if SPL_ATF
select CLK
+ select GICV2
select FPGA_INTEL_SDM_MAILBOX
select NCORE_CACHE
select SPL_ALTERA_SDRAM
@@ -137,6 +139,7 @@
select ARMV8_SET_SMPEN
select BINMAN if SPL_ATF
select FPGA_INTEL_SDM_MAILBOX
+ select GICV2
select TARGET_SOCFPGA_SOC64
choice
diff --git a/arch/arm/mach-socfpga/Makefile b/arch/arm/mach-socfpga/Makefile
index 5fc61b4..22d48df 100644
--- a/arch/arm/mach-socfpga/Makefile
+++ b/arch/arm/mach-socfpga/Makefile
@@ -3,7 +3,7 @@
# (C) Copyright 2000-2003
# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
#
-# Copyright (C) 2012-2017 Altera Corporation <www.altera.com>
+# Copyright (C) 2012-2025 Altera Corporation <www.altera.com>
# Copyright (C) 2017-2024 Intel Corporation <www.intel.com>
obj-y += board.o
@@ -62,7 +62,12 @@
obj-y += misc_soc64.o
obj-y += mmu-arm64_s10.o
obj-y += reset_manager_s10.o
+obj-y += wrap_handoff_soc64.o
obj-y += wrap_pll_config_soc64.o
+obj-y += altera-sysmgr.o
+obj-y += ccu_ncore3.o
+obj-y += system_manager_soc64.o
+obj-y += timer_s10.o
endif
ifdef CONFIG_TARGET_SOCFPGA_N5X
@@ -106,6 +111,7 @@
endif
ifdef CONFIG_TARGET_SOCFPGA_AGILEX5
obj-y += spl_soc64.o
+obj-y += spl_agilex5.o
endif
else
obj-$(CONFIG_SPL_ATF) += secure_reg_helper.o
diff --git a/arch/arm/mach-socfpga/altera-sysmgr.c b/arch/arm/mach-socfpga/altera-sysmgr.c
new file mode 100644
index 0000000..ca3f5ca
--- /dev/null
+++ b/arch/arm/mach-socfpga/altera-sysmgr.c
@@ -0,0 +1,113 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (C) 2025 Altera Corporation <www.altera.com>
+ */
+
+/*
+ * This driver supports the SOCFPGA System Manager Register block which
+ * aggregates different peripheral function into one area.
+ * On 64 bit ARM parts, the system manager only can be accessed during
+ * EL3 mode. At lower exception level a SMC call is required to perform
+ * the read and write operation.
+ */
+
+#define LOG_CATEGORY UCLASS_NOP
+
+#include <dm.h>
+#include <log.h>
+#include <misc.h>
+#include <asm/io.h>
+#include <asm/system.h>
+#include <asm/arch/altera-sysmgr.h>
+#include <asm/arch/smc_api.h>
+#include <linux/delay.h>
+#include <linux/err.h>
+#include <linux/intel-smc.h>
+
+static int altr_sysmgr_read_generic(struct udevice *dev, u32 *addr, u32 *value)
+{
+ u64 args[1];
+ u64 ret_arg;
+ int ret = 0;
+
+ debug("%s: %s(dev=%p, addr=0x%lx):\n", __func__,
+ dev->name, dev, (uintptr_t)addr);
+
+ if (current_el() == 3) {
+ ret_arg = readl((uintptr_t)addr);
+ } else {
+ if (!(IS_ENABLED(CONFIG_SPL_BUILD)) && IS_ENABLED(CONFIG_SPL_ATF)) {
+ args[0] = (u64)(uintptr_t)addr;
+ ret = invoke_smc(INTEL_SIP_SMC_REG_READ, args, 1, &ret_arg, 1);
+ } else {
+ pr_err("%s Failed to read system manager at lower privilege and without BL31\n",
+ dev->name);
+ return -EPROTONOSUPPORT;
+ }
+ }
+
+ *value = (u32)ret_arg;
+ return ret;
+}
+
+static int altr_sysmgr_write_generic(struct udevice *dev, u32 *addr, u32 value)
+{
+ u64 args[2];
+ int ret = 0;
+
+ debug("%s: %s(dev=%p, addr=0x%lx, val=0x%x):\n", __func__,
+ dev->name, dev, (uintptr_t)addr, value);
+
+ if (current_el() == 3) {
+ writel(value, (uintptr_t)addr);
+ } else {
+ if (!(IS_ENABLED(CONFIG_SPL_BUILD)) && IS_ENABLED(CONFIG_SPL_ATF)) {
+ args[0] = (u64)(uintptr_t)(addr);
+ args[1] = value;
+ ret = invoke_smc(INTEL_SIP_SMC_REG_WRITE, args, 2, NULL, 0);
+ } else {
+ pr_err("%s Failed to write to system manager at lower privilege and without BL31\n",
+ dev->name);
+ return -EPROTONOSUPPORT;
+ }
+ }
+
+ return ret;
+}
+
+static int altr_sysmgr_probe(struct udevice *dev)
+{
+ fdt_addr_t addr;
+ struct altr_sysmgr_priv *altr_priv = dev_get_priv(dev);
+
+ debug("%s: %s(dev=%p):\n", __func__, dev->name, dev);
+ addr = dev_read_addr(dev);
+ if (addr == FDT_ADDR_T_NONE) {
+ pr_err("%s dev_read_addr() failed\n", dev->name);
+ return -ENODEV;
+ }
+
+ altr_priv->regs = (void __iomem *)addr;
+ return 0;
+}
+
+static const struct altr_sysmgr_ops sysmgr_ops = {
+ .read = altr_sysmgr_read_generic,
+ .write = altr_sysmgr_write_generic,
+};
+
+static const struct udevice_id altr_sysmgr_ids[] = {
+ { .compatible = "altr,sys-mgr-s10" },
+ { .compatible = "altr,sys-mgr" },
+ { },
+};
+
+U_BOOT_DRIVER(altr_sysmgr) = {
+ .name = "altr_sysmgr",
+ .id = UCLASS_NOP,
+ .of_match = altr_sysmgr_ids,
+ .probe = altr_sysmgr_probe,
+ .ops = &sysmgr_ops,
+ .priv_auto = sizeof(struct altr_sysmgr_priv),
+ .flags = DM_FLAG_PRE_RELOC,
+};
diff --git a/arch/arm/mach-socfpga/board.c b/arch/arm/mach-socfpga/board.c
index 24a15f7..27072e5 100644
--- a/arch/arm/mach-socfpga/board.c
+++ b/arch/arm/mach-socfpga/board.c
@@ -6,22 +6,24 @@
*/
#include <config.h>
-#include <asm/arch/clock_manager.h>
-#include <asm/arch/mailbox_s10.h>
-#include <asm/arch/misc.h>
-#include <asm/arch/reset_manager.h>
-#include <asm/arch/secure_vab.h>
-#include <asm/arch/smc_api.h>
-#include <asm/global_data.h>
-#include <asm/io.h>
#include <errno.h>
#include <fdtdec.h>
+#include <log.h>
+#include <init.h>
#include <hang.h>
+#include <handoff.h>
#include <image.h>
-#include <init.h>
-#include <log.h>
#include <usb.h>
#include <usb/dwc2_udc.h>
+#include <asm/global_data.h>
+#include <asm/io.h>
+#include <asm/arch/clock_manager.h>
+#include <asm/arch/mailbox_s10.h>
+#include <asm/arch/misc.h>
+#include <asm/arch/reset_manager.h>
+#include <asm/arch/secure_vab.h>
+#include <asm/arch/smc_api.h>
+#include <bloblist.h>
DECLARE_GLOBAL_DATA_PTR;
@@ -57,7 +59,18 @@
int dram_init_banksize(void)
{
+#if CONFIG_IS_ENABLED(HANDOFF) && IS_ENABLED(CONFIG_TARGET_SOCFPGA_AGILEX5)
+#ifndef CONFIG_SPL_BUILD
+ struct spl_handoff *ho;
+
+ ho = bloblist_find(BLOBLISTT_U_BOOT_SPL_HANDOFF, sizeof(*ho));
+ if (!ho)
+ return log_msg_ret("Missing SPL hand-off info", -ENOENT);
+ handoff_load_dram_banks(ho);
+#endif
+#else
fdtdec_setup_memory_banksize();
+#endif /* HANDOFF && CONFIG_TARGET_SOCFPGA_AGILEX5 */
return 0;
}
diff --git a/arch/arm/mach-socfpga/ccu_ncore3.c b/arch/arm/mach-socfpga/ccu_ncore3.c
new file mode 100644
index 0000000..a399aed
--- /dev/null
+++ b/arch/arm/mach-socfpga/ccu_ncore3.c
@@ -0,0 +1,64 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (C) 2025 Altera Corporation <www.altera.com>
+ *
+ */
+#include <wait_bit.h>
+#include <asm/arch/base_addr_soc64.h>
+#include <linux/bitfield.h>
+
+#define CCU_DMI0_DMIUSMCTCR SOCFPGA_CCU_ADDRESS + 0x7300
+#define CCU_DMI0_DMIUSMCMCR SOCFPGA_CCU_ADDRESS + 0x7340
+#define CCU_DMI0_DMIUSMCMAR SOCFPGA_CCU_ADDRESS + 0x7344
+#define CCU_DMI0_DMIUSMCMCR_MNTOP GENMASK(3, 0)
+#define MAX_DISTRIBUTED_MEM_INTERFACE 2
+#define FLUSH_ALL_ENTRIES 0x4
+#define CCU_DMI0_DMIUSMCMCR_ARRAY_ID GENMASK(21, 16)
+#define ARRAY_ID_TAG 0x0
+#define ARRAY_ID_DATA 0x1
+#define CACHE_OPERATION_DONE BIT(0)
+#define TIMEOUT_200MS 200
+
+int __asm_flush_l3_dcache(void)
+{
+ int i;
+ int ret = 0;
+
+ /* Flushing all entries in CCU system memory cache */
+ for (i = 0; i < MAX_DISTRIBUTED_MEM_INTERFACE; i++) {
+ /*
+ * Skipping if the system memory cache is not enabled for
+ * particular DMI
+ */
+ if (!readl((uintptr_t)(CCU_DMI0_DMIUSMCTCR + (i * 0x1000))))
+ continue;
+
+ writel(FIELD_PREP(CCU_DMI0_DMIUSMCMCR_MNTOP, FLUSH_ALL_ENTRIES) |
+ FIELD_PREP(CCU_DMI0_DMIUSMCMCR_ARRAY_ID, ARRAY_ID_TAG),
+ (uintptr_t)(CCU_DMI0_DMIUSMCMCR + (i * 0x1000)));
+
+ /* Wait for cache maintenance operation done */
+ ret = wait_for_bit_le32((const void *)(uintptr_t)(CCU_DMI0_DMIUSMCMAR +
+ (i * 0x1000)), CACHE_OPERATION_DONE, false, TIMEOUT_200MS,
+ false);
+ if (ret) {
+ debug("%s: Timeout while waiting for flushing tag in DMI%d done\n",
+ __func__, i);
+ return ret;
+ }
+
+ writel(FIELD_PREP(CCU_DMI0_DMIUSMCMCR_MNTOP, FLUSH_ALL_ENTRIES) |
+ FIELD_PREP(CCU_DMI0_DMIUSMCMCR_ARRAY_ID, ARRAY_ID_DATA),
+ (uintptr_t)(CCU_DMI0_DMIUSMCMCR + (i * 0x1000)));
+
+ /* Wait for cache maintenance operation done */
+ ret = wait_for_bit_le32((const void *)(uintptr_t)(CCU_DMI0_DMIUSMCMAR +
+ (i * 0x1000)), CACHE_OPERATION_DONE, false, TIMEOUT_200MS,
+ false);
+ if (ret)
+ debug("%s: Timeout waiting for flushing data in DMI%d done\n",
+ __func__, i);
+ }
+
+ return ret;
+}
diff --git a/arch/arm/mach-socfpga/include/mach/altera-sysmgr.h b/arch/arm/mach-socfpga/include/mach/altera-sysmgr.h
new file mode 100644
index 0000000..8516617
--- /dev/null
+++ b/arch/arm/mach-socfpga/include/mach/altera-sysmgr.h
@@ -0,0 +1,16 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (C) 2025 Altera Corporation <www.altera.com>
+ */
+
+struct altr_sysmgr_ops {
+ int (*read)(struct udevice *dev, u32 *addr, u32 *value);
+ int (*write)(struct udevice *dev, u32 *addr, u32 value);
+};
+
+struct altr_sysmgr_priv {
+ void __iomem *regs;
+};
+
+#define altr_sysmgr_get_ops(dev) ((struct altr_sysmgr_ops *)(dev)->driver->ops)
+#define altr_sysmgr_get_priv(dev) ((struct altr_sysmgr_priv *)(dev_get_priv(dev)))
diff --git a/arch/arm/mach-socfpga/include/mach/board.h b/arch/arm/mach-socfpga/include/mach/board.h
new file mode 100644
index 0000000..2c3127e
--- /dev/null
+++ b/arch/arm/mach-socfpga/include/mach/board.h
@@ -0,0 +1,11 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (C) 2025 Altera Corporation <www.altera.com>
+ */
+
+#ifndef BOARD_H_
+#define BOARD_H_
+
+u8 socfpga_get_board_id(void);
+
+#endif /* _BOARD_H_ */
diff --git a/arch/arm/mach-socfpga/include/mach/firewall.h b/arch/arm/mach-socfpga/include/mach/firewall.h
index 5cb7f23..2b436b64 100644
--- a/arch/arm/mach-socfpga/include/mach/firewall.h
+++ b/arch/arm/mach-socfpga/include/mach/firewall.h
@@ -1,6 +1,7 @@
/* SPDX-License-Identifier: GPL-2.0
*
* Copyright (C) 2017-2019 Intel Corporation <www.intel.com>
+ * Copyright (C) 2025 Altera Corporation <www.altera.com>
*
*/
@@ -126,11 +127,27 @@
#define FW_MPU_DDR_SCR_NONMPUREGION0ADDR_LIMITEXT 0x9c
#define FW_MPU_DDR_SCR_NONMPUREGION0ADDR_LIMITEXT_FIELD 0xff
+/* Firewall F2SDRAM DDR SCR registers */
+#define FW_F2SDRAM_DDR_SCR_EN 0x00
+#define FW_F2SDRAM_DDR_SCR_EN_SET 0x04
+#define FW_F2SDRAM_DDR_SCR_REGION0ADDR_BASE 0x10
+#define FW_F2SDRAM_DDR_SCR_REGION0ADDR_BASEEXT 0x14
+#define FW_F2SDRAM_DDR_SCR_REGION0ADDR_LIMIT 0x18
+#define FW_F2SDRAM_DDR_SCR_REGION0ADDR_LIMITEXT 0x1c
+
#define MPUREGION0_ENABLE BIT(0)
#define NONMPUREGION0_ENABLE BIT(8)
+#if IS_ENABLED(CONFIG_TARGET_SOCFPGA_AGILEX5)
+#define FW_MPU_DDR_SCR_WRITEL(data, reg) \
+ writel(data, SOCFPGA_FW_DDR_CCU_DMI0_ADDRESS + (reg)); \
+ writel(data, SOCFPGA_FW_DDR_CCU_DMI1_ADDRESS + (reg))
+#define FW_F2SDRAM_DDR_SCR_WRITEL(data, reg) \
+ writel(data, SOCFPGA_FW_TBU2NOC_ADDRESS + (reg))
+#else
#define FW_MPU_DDR_SCR_WRITEL(data, reg) \
writel(data, SOCFPGA_FW_MPU_DDR_SCR_ADDRESS + (reg))
+#endif
void firewall_setup(void);
diff --git a/arch/arm/mach-socfpga/include/mach/handoff_soc64.h b/arch/arm/mach-socfpga/include/mach/handoff_soc64.h
index d839f28..763b077 100644
--- a/arch/arm/mach-socfpga/include/mach/handoff_soc64.h
+++ b/arch/arm/mach-socfpga/include/mach/handoff_soc64.h
@@ -1,6 +1,7 @@
/* SPDX-License-Identifier: GPL-2.0
*
* Copyright (C) 2016-2024 Intel Corporation <www.intel.com>
+ * Copyright (C) 2025 Altera Corporation <www.altera.com>
*
*/
@@ -17,9 +18,9 @@
#define SOC64_HANDOFF_MAGIC_FPGA 0x46504741
#define SOC64_HANDOFF_MAGIC_DELAY 0x444C4159
#define SOC64_HANDOFF_MAGIC_CLOCK 0x434C4B53
+#define SOC64_HANDOFF_MAGIC_SDRAM 0x5344524d
#if IS_ENABLED(CONFIG_TARGET_SOCFPGA_AGILEX5)
#define SOC64_HANDOFF_MAGIC_PERI 0x50455249
-#define SOC64_HANDOFF_MAGIC_SDRAM 0x5344524d
#else
#define SOC64_HANDOFF_MAGIC_MISC 0x4D495343
#endif
@@ -68,7 +69,7 @@
#if IS_ENABLED(CONFIG_TARGET_SOCFPGA_AGILEX5)
#define SOC64_HANDOFF_PERI (SOC64_HANDOFF_BASE + 0x620)
#define SOC64_HANDOFF_SDRAM (SOC64_HANDOFF_BASE + 0x634)
-#define SOC64_HANDOFF_SDRAM_LEN 1
+#define SOC64_HANDOFF_SDRAM_LEN 5
#endif
#if IS_ENABLED(CONFIG_TARGET_SOCFPGA_STRATIX10)
diff --git a/arch/arm/mach-socfpga/include/mach/misc.h b/arch/arm/mach-socfpga/include/mach/misc.h
index 8460acb..ab46415 100644
--- a/arch/arm/mach-socfpga/include/mach/misc.h
+++ b/arch/arm/mach-socfpga/include/mach/misc.h
@@ -1,6 +1,7 @@
/* SPDX-License-Identifier: GPL-2.0 */
/*
* Copyright (C) 2016-2021 Intel Corporation
+ * Copyright (C) 2025 Altera Corporation <www.altera.com>
*/
#ifndef _SOCFPGA_MISC_H_
@@ -51,6 +52,7 @@
void set_regular_boot(unsigned int status);
void socfpga_pl310_clear(void);
void socfpga_get_managers_addr(void);
+void socfpga_get_sys_mgr_addr(const char *compat);
int qspi_flash_software_reset(void);
#endif /* _SOCFPGA_MISC_H_ */
diff --git a/arch/arm/mach-socfpga/include/mach/reset_manager_soc64.h b/arch/arm/mach-socfpga/include/mach/reset_manager_soc64.h
index c8bb727..058fdd6 100644
--- a/arch/arm/mach-socfpga/include/mach/reset_manager_soc64.h
+++ b/arch/arm/mach-socfpga/include/mach/reset_manager_soc64.h
@@ -1,6 +1,7 @@
/* SPDX-License-Identifier: GPL-2.0 */
/*
* Copyright (C) 2016-2019 Intel Corporation <www.intel.com>
+ * Copyright (C) 2025 Altera Corporation <www.altera.com>
*/
#ifndef _RESET_MANAGER_SOC64_H_
@@ -23,14 +24,20 @@
#define RSTMGR_BRGMODRST_FPGA2SOC_MASK 0x00000004
/* SDM, Watchdogs and MPU warm reset mask */
-#define RSTMGR_STAT_SDMWARMRST BIT(1)
+#define RSTMGR_STAT_SDMWARMRST 0x2
#define RSTMGR_STAT_MPU0RST_BITPOS 8
#define RSTMGR_STAT_L4WD0RST_BITPOS 16
+#if IS_ENABLED(CONFIG_TARGET_SOCFPGA_AGILEX5)
+#define RSTMGR_STAT_L4WD0RST_BIT 0x1F0000
+#define RSTMGR_L4WD_MPU_WARMRESET_MASK (RSTMGR_STAT_SDMWARMRST | \
+ RSTMGR_STAT_L4WD0RST_BIT)
+#else
#define RSTMGR_L4WD_MPU_WARMRESET_MASK (RSTMGR_STAT_SDMWARMRST | \
GENMASK(RSTMGR_STAT_MPU0RST_BITPOS + 3, \
RSTMGR_STAT_MPU0RST_BITPOS) | \
GENMASK(RSTMGR_STAT_L4WD0RST_BITPOS + 3, \
RSTMGR_STAT_L4WD0RST_BITPOS))
+#endif
/*
* SocFPGA Stratix10 reset IDs, bank mapping is as follows:
diff --git a/arch/arm/mach-socfpga/include/mach/system_manager_soc64.h b/arch/arm/mach-socfpga/include/mach/system_manager_soc64.h
index 78eff24..c2ca0a5 100644
--- a/arch/arm/mach-socfpga/include/mach/system_manager_soc64.h
+++ b/arch/arm/mach-socfpga/include/mach/system_manager_soc64.h
@@ -1,6 +1,7 @@
/* SPDX-License-Identifier: GPL-2.0 */
/*
* Copyright (C) 2019-2021 Intel Corporation <www.intel.com>
+ * Copyright (C) 2025 Altera Corporation <www.altera.com>
*/
#ifndef _SYSTEM_MANAGER_SOC64_H_
@@ -11,22 +12,43 @@
void populate_sysmgr_fpgaintf_module(void);
void populate_sysmgr_pinmux(void);
-#define SYSMGR_SOC64_WDDBG 0x08
-#define SYSMGR_SOC64_DMA 0x20
-#define SYSMGR_SOC64_DMA_PERIPH 0x24
-#define SYSMGR_SOC64_SDMMC 0x28
-#define SYSMGR_SOC64_SDMMC_L3MASTER 0x2c
-#define SYSMGR_SOC64_EMAC_GLOBAL 0x40
-#define SYSMGR_SOC64_EMAC0 0x44
-#define SYSMGR_SOC64_EMAC1 0x48
-#define SYSMGR_SOC64_EMAC2 0x4c
-#define SYSMGR_SOC64_EMAC0_ACE 0x50
-#define SYSMGR_SOC64_EMAC1_ACE 0x54
-#define SYSMGR_SOC64_EMAC2_ACE 0x58
+#if IS_ENABLED(CONFIG_TARGET_SOCFPGA_AGILEX5)
+#define SYSMGR_SOC64_SILICONID_1 0x00
+#define SYSMGR_SOC64_SILICONID_2 0x04
+#define SYSMGR_SOC64_MPU_STATUS 0x10
+#define SYSMGR_SOC64_COMBOPHY_DFISEL 0xfc
+#define SYSMGR_SOC64_COMBOPHY_DFISEL_SDMMC 0x1
+#define SYSMGR_SOC64_NANDGRP_L3MASTER 0x34
+#define SYSMGR_SOC64_USB0_L3MASTER 0x38
+#define SYSMGR_SOC64_USB1_L3MASTER 0x3c
+#define SYSMGR_SOC64_DMAC0_L3_MASTER 0x74
+#define SYSMGR_SOC64_ETR_L3_MASTER 0x78
+#define SYSMGR_SOC64_DMAC1_L3_MASTER 0x7C
+#define SYSMGR_SOC64_SEC_CTRL_SLT 0x80
+#define SYSMGR_SOC64_OSC_TRIM 0x84
+#define SYSMGR_SOC64_DMAC0_CTRL_STATUS_REG 0x88
+#define SYSMGR_SOC64_DMAC1_CTRL_STATUS_REG 0x8C
+#define SYSMGR_SOC64_ECC_INTMASK_VALUE 0x90
+#define SYSMGR_SOC64_ECC_INTMASK_SET 0x94
+#define SYSMGR_SOC64_ECC_INTMASK_CLR 0x98
+#define SYSMGR_SOC64_ECC_INTMASK_SERR 0x9C
+#define SYSMGR_SOC64_ECC_INTMASK_DERR 0xA0
+#define SYSMGR_SOC64_MPFE_CONFIG 0x228
+#define SYSMGR_SOC64_BOOT_SCRATCH_POR0 0x258
+#define SYSMGR_SOC64_BOOT_SCRATCH_POR1 0x25C
+#define SYSMGR_SCRATCH_REG_0_QSPI_REFCLK_MASK GENMASK(31, 0)
+#define ALT_SYSMGR_SCRATCH_REG_3_DDR_RESET_TYPE_MASK GENMASK(31, 29)
+#define ALT_SYSMGR_SCRATCH_REG_3_DDR_RESET_TYPE_SHIFT 29
+#define ALT_SYSMGR_SCRATCH_REG_3_DDR_PORT_INFO_MASK BIT(27)
+#define ALT_SYSMGR_SCRATCH_REG_3_DDR_EMIF_INFO_MASK BIT(28)
+#define ALT_SYSMGR_SCRATCH_REG_3_DDR_PORT_EMIF_INFO_MASK GENMASK(28, 27)
+#define ALT_SYSMGR_SCRATCH_REG_3_DDR_DBE_MASK BIT(1)
+#define ALT_SYSMGR_SCRATCH_REG_3_OCRAM_DBE_MASK BIT(0)
+#define ALT_SYSMGR_SCRATCH_REG_POR_0_DDR_PROGRESS_MASK BIT(0)
+#define ALT_SYSMGR_SCRATCH_REG_POR_1_REVA_WORKAROUND_USER_MODE_MASK BIT(0)
+#define ALT_SYSMGR_SCRATCH_REG_POR_1_REVA_WORKAROUND_MASK BIT(1)
+#else
#define SYSMGR_SOC64_NAND_AXUSER 0x5c
-#define SYSMGR_SOC64_FPGAINTF_EN1 0x68
-#define SYSMGR_SOC64_FPGAINTF_EN2 0x6c
-#define SYSMGR_SOC64_FPGAINTF_EN3 0x70
#define SYSMGR_SOC64_DMA_L3MASTER 0x74
#if IS_ENABLED(CONFIG_TARGET_SOCFPGA_N5X)
#define SYSMGR_SOC64_DDR_MODE 0xb8
@@ -34,39 +56,56 @@
#define SYSMGR_SOC64_HMC_CLK 0xb4
#define SYSMGR_SOC64_IO_PA_CTRL 0xb8
#endif
-#define SYSMGR_SOC64_NOC_TIMEOUT 0xc0
-#define SYSMGR_SOC64_NOC_IDLEREQ_SET 0xc4
-#define SYSMGR_SOC64_NOC_IDLEREQ_CLR 0xc8
-#define SYSMGR_SOC64_NOC_IDLEREQ_VAL 0xcc
-#define SYSMGR_SOC64_NOC_IDLEACK 0xd0
-#define SYSMGR_SOC64_NOC_IDLESTATUS 0xd4
-#define SYSMGR_SOC64_FPGA2SOC_CTRL 0xd8
-#define SYSMGR_SOC64_FPGA_CONFIG 0xdc
#define SYSMGR_SOC64_IOCSRCLK_GATE 0xe0
#define SYSMGR_SOC64_GPO 0xe4
#define SYSMGR_SOC64_GPI 0xe8
#define SYSMGR_SOC64_MPU 0xf0
-/*
- * Bits[31:28] reserved for N5X DDR retention, bits[27:0] reserved for SOC 64-bit
- * storing qspi ref clock (kHz)
- */
-#define SYSMGR_SOC64_BOOT_SCRATCH_COLD0 0x200
-/* store osc1 clock freq */
-#define SYSMGR_SOC64_BOOT_SCRATCH_COLD1 0x204
-/* store fpga clock freq */
-#define SYSMGR_SOC64_BOOT_SCRATCH_COLD2 0x208
-/* reserved for customer use */
-#define SYSMGR_SOC64_BOOT_SCRATCH_COLD3 0x20c
-/* store PSCI_CPU_ON value */
-#define SYSMGR_SOC64_BOOT_SCRATCH_COLD4 0x210
-/* store PSCI_CPU_ON value */
-#define SYSMGR_SOC64_BOOT_SCRATCH_COLD5 0x214
-/* store VBAR_EL3 value */
-#define SYSMGR_SOC64_BOOT_SCRATCH_COLD6 0x218
-/* store VBAR_EL3 value */
-#define SYSMGR_SOC64_BOOT_SCRATCH_COLD7 0x21c
-#define SYSMGR_SOC64_BOOT_SCRATCH_COLD8 0x220
-#define SYSMGR_SOC64_BOOT_SCRATCH_COLD9 0x224
+#define SYSMGR_SCRATCH_REG_0_QSPI_REFCLK_MASK GENMASK(27, 0)
+#endif /*CONFIG_TARGET_SOCFPGA_AGILEX5*/
+
+#define SYSMGR_SOC64_DMA 0x20
+#define SYSMGR_SOC64_DMA_PERIPH 0x24
+#define SYSMGR_SOC64_WDDBG 0x08
+#define SYSMGR_SOC64_SDMMC 0x28
+#define SYSMGR_SOC64_SDMMC_L3MASTER 0x2C
+#define SYSMGR_SOC64_FPGAINTF_EN1 0x68
+#define SYSMGR_SOC64_FPGAINTF_EN2 0x6C
+#define SYSMGR_SOC64_FPGAINTF_EN3 0x70
+#define SYSMGR_SOC64_NOC_TIMEOUT 0xC0
+#define SYSMGR_SOC64_NOC_IDLEREQ_SET 0xC4
+#define SYSMGR_SOC64_NOC_IDLEREQ_CLR 0xC8
+#define SYSMGR_SOC64_NOC_IDLEREQ_VAL 0xCC
+#define SYSMGR_SOC64_NOC_IDLEACK 0xd0
+#define SYSMGR_SOC64_NOC_IDLESTATUS 0xD4
+#define SYSMGR_SOC64_FPGA2SOC_CTRL 0xD8
+#define SYSMGR_SOC64_FPGA_CONFIG 0xDC
+
+#define SYSMGR_SOC64_TSN_GLOBAL 0x40
+#define SYSMGR_SOC64_TSN_0 0x44
+#define SYSMGR_SOC64_TSN_1 0x48
+#define SYSMGR_SOC64_TSN_2 0x4C
+#define SYSMGR_SOC64_TSN_0_ACE 0x50
+#define SYSMGR_SOC64_TSN_1_ACE 0x54
+#define SYSMGR_SOC64_TSN_2_ACE 0x58
+#define SYSMGR_SOC64_EMAC_GLOBAL SYSMGR_SOC64_TSN_GLOBAL
+#define SYSMGR_SOC64_EMAC0 SYSMGR_SOC64_TSN_0
+#define SYSMGR_SOC64_EMAC1 SYSMGR_SOC64_TSN_1
+#define SYSMGR_SOC64_EMAC2 SYSMGR_SOC64_TSN_2
+#define SYSMGR_SOC64_EMAC0_ACE SYSMGR_SOC64_TSN_0_ACE
+#define SYSMGR_SOC64_EMAC1_ACE SYSMGR_SOC64_TSN_1_ACE
+#define SYSMGR_SOC64_EMAC2_ACE SYSMGR_SOC64_TSN_2_ACE
+
+#define SYSMGR_SOC64_BOOT_SCRATCH_COLD0 0x200
+#define SYSMGR_SOC64_BOOT_SCRATCH_COLD1 0x204
+#define SYSMGR_SOC64_BOOT_SCRATCH_COLD2 0x208
+#define SYSMGR_SOC64_BOOT_SCRATCH_COLD3 0x20C
+#define SYSMGR_SOC64_BOOT_SCRATCH_COLD4 0x210
+#define SYSMGR_SOC64_BOOT_SCRATCH_COLD5 0x214
+#define SYSMGR_SOC64_BOOT_SCRATCH_COLD6 0x218
+#define SYSMGR_SOC64_BOOT_SCRATCH_COLD7 0x21C
+#define SYSMGR_SOC64_BOOT_SCRATCH_COLD8 0x220
+#define SYSMGR_SOC64_BOOT_SCRATCH_COLD9 0x224
+
#define SYSMGR_SOC64_PINSEL0 0x1000
#define SYSMGR_SOC64_IOCTRL0 0x1130
#define SYSMGR_SOC64_EMAC0_USEFPGA 0x1300
@@ -97,7 +136,6 @@
* Bits[31:28] reserved for DM DDR retention, bits[27:0] reserved for SOC 64-bit
* storing qspi ref clock (kHz)
*/
-#define SYSMGR_SCRATCH_REG_0_QSPI_REFCLK_MASK GENMASK(27, 0)
#define ALT_SYSMGR_SCRATCH_REG_0_DDR_RETENTION_MASK BIT(31)
#define ALT_SYSMGR_SCRATCH_REG_0_DDR_SHA_MASK BIT(30)
#define ALT_SYSMGR_SCRATCH_REG_0_DDR_RESET_TYPE_MASK (BIT(29) | BIT(28))
diff --git a/arch/arm/mach-socfpga/misc.c b/arch/arm/mach-socfpga/misc.c
index 46f9c82..97e0114 100644
--- a/arch/arm/mach-socfpga/misc.c
+++ b/arch/arm/mach-socfpga/misc.c
@@ -1,31 +1,33 @@
// SPDX-License-Identifier: GPL-2.0+
/*
- * Copyright (C) 2012-2017 Altera Corporation <www.altera.com>
+ * Copyright (C) 2012-2025 Altera Corporation <www.altera.com>
*/
#include <config.h>
#include <command.h>
-#include <cpu_func.h>
-#include <hang.h>
-#include <asm/cache.h>
-#include <init.h>
-#include <asm/global_data.h>
-#include <asm/io.h>
#include <errno.h>
+#include <init.h>
+#include <handoff.h>
+#include <hang.h>
+#include <watchdog.h>
#include <fdtdec.h>
#include <linux/libfdt.h>
-#include <altera.h>
+#include <linux/printk.h>
#include <miiphy.h>
#include <netdev.h>
-#include <watchdog.h>
+#include <asm/global_data.h>
+#include <asm/io.h>
+#include <asm/cache.h>
+#include <asm/pl310.h>
#include <asm/arch/misc.h>
+#include <asm/arch/nic301.h>
#include <asm/arch/reset_manager.h>
#include <asm/arch/scan_manager.h>
-#include <asm/arch/system_manager.h>
-#include <asm/arch/nic301.h>
#include <asm/arch/scu.h>
-#include <asm/pl310.h>
-#include <linux/printk.h>
+#include <asm/arch/system_manager.h>
+#include <altera.h>
+#include <bloblist.h>
+#include <cpu_func.h>
DECLARE_GLOBAL_DATA_PTR;
@@ -51,8 +53,18 @@
int dram_init(void)
{
+#if CONFIG_IS_ENABLED(HANDOFF) && IS_ENABLED(CONFIG_TARGET_SOCFPGA_AGILEX5)
+ struct spl_handoff *ho;
+
+ ho = bloblist_find(BLOBLISTT_U_BOOT_SPL_HANDOFF, sizeof(*ho));
+ if (!ho)
+ return log_msg_ret("Missing SPL hand-off info", -ENOENT);
+ gd->ram_size = ho->ram_bank[0].size;
+ gd->ram_base = ho->ram_bank[0].start;
+#else
if (fdtdec_setup_mem_size_base() != 0)
return -EINVAL;
+#endif /* HANDOFF && CONFIG_TARGET_SOCFPGA_AGILEX5 */
return 0;
}
@@ -248,21 +260,32 @@
if (ret)
hang();
- ret = socfpga_get_base_addr("altr,sys-mgr", &socfpga_sysmgr_base);
+ if (IS_ENABLED(CONFIG_TARGET_SOCFPGA_AGILEX))
+ ret = socfpga_get_base_addr("intel,agilex-clkmgr",
+ &socfpga_clkmgr_base);
+ else if (IS_ENABLED(CONFIG_TARGET_SOCFPGA_N5X))
+ ret = socfpga_get_base_addr("intel,n5x-clkmgr",
+ &socfpga_clkmgr_base);
+ else if (!IS_ENABLED(CONFIG_TARGET_SOCFPGA_AGILEX5))
+ ret = socfpga_get_base_addr("altr,clk-mgr",
+ &socfpga_clkmgr_base);
+
if (ret)
hang();
+}
-#ifdef CONFIG_TARGET_SOCFPGA_AGILEX
- ret = socfpga_get_base_addr("intel,agilex-clkmgr",
- &socfpga_clkmgr_base);
-#elif IS_ENABLED(CONFIG_TARGET_SOCFPGA_N5X)
- ret = socfpga_get_base_addr("intel,n5x-clkmgr",
- &socfpga_clkmgr_base);
-#else
- ret = socfpga_get_base_addr("altr,clk-mgr", &socfpga_clkmgr_base);
-#endif
- if (ret)
+void socfpga_get_sys_mgr_addr(const char *compat)
+{
+ int ret;
+ struct udevice *sysmgr_dev;
+
+ ret = uclass_get_device_by_name(UCLASS_NOP, compat, &sysmgr_dev);
+ if (ret) {
+ printf("Altera system manager init failed: %d\n", ret);
hang();
+ } else {
+ socfpga_sysmgr_base = (phys_addr_t)dev_read_addr(sysmgr_dev);
+ }
}
phys_addr_t socfpga_get_rstmgr_addr(void)
diff --git a/arch/arm/mach-socfpga/misc_soc64.c b/arch/arm/mach-socfpga/misc_soc64.c
index a6cc784..e0b2b42 100644
--- a/arch/arm/mach-socfpga/misc_soc64.c
+++ b/arch/arm/mach-socfpga/misc_soc64.c
@@ -1,20 +1,23 @@
// SPDX-License-Identifier: GPL-2.0
/*
* Copyright (C) 2016-2018 Intel Corporation <www.intel.com>
+ * Copyright (C) 2025 Altera Corporation <www.altera.com>
*
*/
#include <altera.h>
+#include <env.h>
+#include <errno.h>
+#include <init.h>
+#include <log.h>
+#include <asm/arch/board.h>
#include <asm/arch/mailbox_s10.h>
#include <asm/arch/misc.h>
#include <asm/arch/reset_manager.h>
#include <asm/arch/system_manager.h>
#include <asm/io.h>
+#include <asm/system.h>
#include <asm/global_data.h>
-#include <env.h>
-#include <errno.h>
-#include <init.h>
-#include <log.h>
#include <mach/clock_manager.h>
DECLARE_GLOBAL_DATA_PTR;
@@ -40,12 +43,26 @@
};
/*
+ * The Agilex5 platform has enabled the bloblist feature, and the bloblist
+ * address and size are initialized based on the defconfig settings.
+ * During the SPL phase, this function is used to prevent the bloblist
+ * from initializing its address and size with the saved boot parameters,
+ * which may have been incorrectly set.
+ */
+void save_boot_params(unsigned long r0, unsigned long r1, unsigned long r2,
+ unsigned long r3)
+{
+ save_boot_params_ret();
+}
+
+/*
* Print CPU information
*/
#if defined(CONFIG_DISPLAY_CPUINFO)
int print_cpuinfo(void)
{
- puts("CPU: Intel FPGA SoCFPGA Platform (ARMv8 64bit Cortex-A53)\n");
+ printf("CPU: Intel FPGA SoCFPGA Platform (ARMv8 64bit Cortex-%s)\n",
+ IS_ENABLED(CONFIG_TARGET_SOCFPGA_AGILEX5) ? "A55/A76" : "A53");
return 0;
}
@@ -55,10 +72,15 @@
int arch_misc_init(void)
{
char qspi_string[13];
+ unsigned long id;
sprintf(qspi_string, "<0x%08x>", cm_get_qspi_controller_clk_hz());
env_set("qspi_clock", qspi_string);
+ /* Export board_id as environment variable */
+ id = socfpga_get_board_id();
+ env_set_ulong("board_id", id);
+
return 0;
}
#endif
diff --git a/arch/arm/mach-socfpga/smc_api.c b/arch/arm/mach-socfpga/smc_api.c
index ebaa0b8..b212a94 100644
--- a/arch/arm/mach-socfpga/smc_api.c
+++ b/arch/arm/mach-socfpga/smc_api.c
@@ -1,9 +1,11 @@
// SPDX-License-Identifier: GPL-2.0+
/*
* Copyright (C) 2020 Intel Corporation <www.intel.com>
+ * Copyright (C) 2025 Altera Corporation <www.altera.com>
*
*/
+#include <cpu_func.h>
#include <asm/ptrace.h>
#include <asm/system.h>
#include <linux/errno.h>
@@ -40,10 +42,16 @@
args[2] = len;
args[3] = urgent;
args[4] = (u64)resp_buf;
- if (resp_buf_len)
+
+ if (arg && len > 0)
+ flush_dcache_range((uintptr_t)arg, (uintptr_t)arg + len);
+
+ if (resp_buf && resp_buf_len && *resp_buf_len > 0) {
args[5] = *resp_buf_len;
- else
+ flush_dcache_range((uintptr_t)resp_buf, (uintptr_t)resp_buf + *resp_buf_len);
+ } else {
args[5] = 0;
+ }
ret = invoke_smc(INTEL_SIP_SMC_MBOX_SEND_CMD, args, ARRAY_SIZE(args),
resp, ARRAY_SIZE(resp));
diff --git a/arch/arm/mach-socfpga/spl_agilex5.c b/arch/arm/mach-socfpga/spl_agilex5.c
new file mode 100644
index 0000000..3451611
--- /dev/null
+++ b/arch/arm/mach-socfpga/spl_agilex5.c
@@ -0,0 +1,110 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (C) 2024 Intel Corporation <www.intel.com>
+ * Copyright (C) 2025 Altera Corporation <www.altera.com>
+ *
+ */
+
+#include <init.h>
+#include <asm/global_data.h>
+#include <asm/io.h>
+#include <hang.h>
+#include <spl.h>
+#include <asm/arch/base_addr_soc64.h>
+#include <asm/arch/clock_manager.h>
+#include <asm/arch/mailbox_s10.h>
+#include <asm/arch/misc.h>
+#include <asm/arch/reset_manager.h>
+#include <asm/arch/system_manager.h>
+#include <wdt.h>
+#include <dm/uclass.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+u32 reset_flag(void)
+{
+ /* Check rstmgr.stat for warm reset status */
+ u32 status = readl(SOCFPGA_RSTMGR_ADDRESS);
+
+ /* Check whether any L4 watchdogs or SDM had triggered warm reset */
+ u32 warm_reset_mask = RSTMGR_L4WD_MPU_WARMRESET_MASK;
+
+ if (status & warm_reset_mask)
+ return 0;
+
+ return 1;
+}
+
+void board_init_f(ulong dummy)
+{
+ int ret;
+ struct udevice *dev;
+
+ /* Enable Async */
+ asm volatile("msr daifclr, #4");
+
+#ifdef CONFIG_SPL_BUILD
+ spl_save_restore_data();
+#endif
+
+ ret = spl_early_init();
+ if (ret)
+ hang();
+
+ socfpga_get_sys_mgr_addr("sysmgr@10d12000");
+ socfpga_get_managers_addr();
+
+ sysmgr_pinmux_init();
+
+ /* Ensure watchdog is paused when debugging is happening */
+ writel(SYSMGR_WDDBG_PAUSE_ALL_CPU,
+ socfpga_get_sysmgr_addr() + SYSMGR_SOC64_WDDBG);
+
+ timer_init();
+
+ ret = uclass_get_device(UCLASS_CLK, 0, &dev);
+ if (ret) {
+ debug("Clock init failed: %d\n", ret);
+ hang();
+ }
+
+ /*
+ * Enable watchdog as early as possible before initializing other
+ * component. Watchdog need to be enabled after clock driver because
+ * it will retrieve the clock frequency from clock driver.
+ */
+ if (CONFIG_IS_ENABLED(WDT))
+ initr_watchdog();
+
+ preloader_console_init();
+ print_reset_info();
+ cm_print_clock_quick_summary();
+
+ ret = uclass_get_device_by_name(UCLASS_NOP, "socfpga-ccu-config", &dev);
+ if (ret) {
+ printf("HPS CCU settings init failed: %d\n", ret);
+ hang();
+ }
+
+ ret = uclass_get_device_by_name(UCLASS_NOP, "socfpga-firewall-config", &dev);
+ if (ret) {
+ printf("HPS firewall settings init failed: %d\n", ret);
+ hang();
+ }
+
+ if (IS_ENABLED(CONFIG_SPL_ALTERA_SDRAM)) {
+ ret = uclass_get_device(UCLASS_RAM, 0, &dev);
+ if (ret) {
+ debug("DRAM init failed: %d\n", ret);
+ hang();
+ }
+ }
+
+ mbox_init();
+
+ if (IS_ENABLED(CONFIG_CADENCE_QSPI))
+ mbox_qspi_open();
+
+ /* Enable non secure access to ocram */
+ clrbits_le32(SOCFPGA_OCRAM_FIREWALL_ADDRESS + 0x18, BIT(0));
+}
diff --git a/arch/arm/mach-socfpga/spl_soc64.c b/arch/arm/mach-socfpga/spl_soc64.c
index 4fe67ea..651d9fc 100644
--- a/arch/arm/mach-socfpga/spl_soc64.c
+++ b/arch/arm/mach-socfpga/spl_soc64.c
@@ -1,10 +1,13 @@
// SPDX-License-Identifier: GPL-2.0
/*
* Copyright (C) 2020 Intel Corporation. All rights reserved
+ * Copyright (C) 2025 Altera Corporation <www.altera.com>
*
*/
+#include <hang.h>
#include <spl.h>
+#include <dm/uclass.h>
DECLARE_GLOBAL_DATA_PTR;
@@ -13,6 +16,109 @@
return BOOT_DEVICE_MMC1;
}
+/* This function is to map specified node onto SPL boot devices */
+static int spl_node_to_boot_device(int node)
+{
+ const void *blob = gd->fdt_blob;
+ struct udevice *parent;
+ const char *prop;
+
+ if (!uclass_get_device_by_of_offset(UCLASS_MMC, node, &parent))
+ return BOOT_DEVICE_MMC1;
+ else if (!uclass_get_device_by_of_offset(UCLASS_SPI_FLASH, node, &parent))
+ return BOOT_DEVICE_SPI;
+ else if (!uclass_get_device_by_of_offset(UCLASS_MTD, node, &parent))
+ return BOOT_DEVICE_NAND;
+
+ prop = fdt_getprop(blob, node, "device_type", NULL);
+ if (prop) {
+ if (!strcmp(prop, "memory"))
+ return BOOT_DEVICE_RAM;
+
+ printf("%s: unknown device_type %s\n", __func__, prop);
+ }
+
+ return -ENODEV;
+}
+
+static void default_spl_boot_list(u32 *spl_boot_list, int length)
+{
+ spl_boot_list[0] = spl_boot_device();
+
+ if (length > 1)
+ spl_boot_list[1] = BOOT_DEVICE_SPI;
+
+ if (length > 2)
+ spl_boot_list[2] = BOOT_DEVICE_NAND;
+}
+
+void board_boot_order(u32 *spl_boot_list)
+{
+ int idx = 0;
+ const void *blob = gd->fdt_blob;
+ int chosen_node = fdt_path_offset(blob, "/chosen");
+ const char *conf;
+ int elem;
+ int boot_device;
+ int node;
+ int length;
+
+ /* expect valid initialized spl_boot_list */
+ if (!spl_boot_list)
+ return;
+
+ length = 1;
+ while (spl_boot_list[length] == spl_boot_list[length - 1])
+ length++;
+
+ debug("%s: chosen_node is %d\n", __func__, chosen_node);
+ if (chosen_node < 0) {
+ printf("%s: /chosen not found, using default\n", __func__);
+ default_spl_boot_list(spl_boot_list, length);
+ return;
+ }
+
+ for (elem = 0;
+ (conf = fdt_stringlist_get(blob, chosen_node,
+ "u-boot,spl-boot-order", elem, NULL));
+ elem++) {
+ if (idx >= length) {
+ printf("%s: limit %d to spl_boot_list exceeded\n", __func__,
+ length);
+ break;
+ }
+
+ /* Resolve conf item as a path in device tree */
+ node = fdt_path_offset(blob, conf);
+ if (node < 0) {
+ debug("%s: could not find %s in FDT\n", __func__, conf);
+ continue;
+ }
+
+ /* Try to map spl node back onto SPL boot devices */
+ boot_device = spl_node_to_boot_device(node);
+ if (boot_device < 0) {
+ debug("%s: could not map node @%x to a boot-device\n",
+ __func__, node);
+ continue;
+ }
+
+ spl_boot_list[idx] = boot_device;
+ debug("%s: spl_boot_list[%d] = %u\n", __func__, idx,
+ spl_boot_list[idx]);
+ idx++;
+ }
+
+ if (idx == 0) {
+ if (!conf && !elem) {
+ printf("%s: spl-boot-order invalid, using default\n", __func__);
+ default_spl_boot_list(spl_boot_list, length);
+ } else {
+ printf("%s: no valid element spl-boot-order list\n", __func__);
+ }
+ }
+}
+
#if IS_ENABLED(CONFIG_SPL_MMC)
u32 spl_boot_mode(const u32 boot_device)
{
@@ -22,3 +128,16 @@
return MMCSD_MODE_RAW;
}
#endif
+
+/* board specific function prior loading SSBL / U-Boot */
+void spl_perform_fixups(struct spl_image_info *spl_image)
+{
+ int ret;
+ struct udevice *dev;
+
+ ret = uclass_get_device_by_name(UCLASS_NOP, "socfpga-smmu-secure-config", &dev);
+ if (ret) {
+ printf("HPS SMMU secure settings init failed: %d\n", ret);
+ hang();
+ }
+}
diff --git a/arch/arm/mach-socfpga/wrap_handoff_soc64.c b/arch/arm/mach-socfpga/wrap_handoff_soc64.c
index 92051d1..7105cdc 100644
--- a/arch/arm/mach-socfpga/wrap_handoff_soc64.c
+++ b/arch/arm/mach-socfpga/wrap_handoff_soc64.c
@@ -1,15 +1,17 @@
// SPDX-License-Identifier: GPL-2.0
/*
* Copyright (C) 2020-2021 Intel Corporation <www.intel.com>
+ * Copyright (C) 2025 Altera Corporation <www.altera.com>
*
*/
+#include <errno.h>
#include <asm/arch/handoff_soc64.h>
#include <asm/io.h>
-#include <errno.h>
#include "log.h"
#ifndef __ASSEMBLY__
+#include <asm/types.h>
enum endianness {
LITTLE_ENDIAN = 0,
BIG_ENDIAN,
@@ -26,7 +28,12 @@
case SOC64_HANDOFF_MAGIC_FPGA:
case SOC64_HANDOFF_MAGIC_DELAY:
case SOC64_HANDOFF_MAGIC_CLOCK:
+ case SOC64_HANDOFF_MAGIC_SDRAM:
+#if IS_ENABLED(CONFIG_TARGET_SOCFPGA_AGILEX5)
+ case SOC64_HANDOFF_MAGIC_PERI:
+#else
case SOC64_HANDOFF_MAGIC_MISC:
+#endif
return BIG_ENDIAN;
#if IS_ENABLED(CONFIG_TARGET_SOCFPGA_N5X)
case SOC64_HANDOFF_DDR_UMCTL2_MAGIC:
diff --git a/arch/arm/mach-tegra/tegra124/clock.c b/arch/arm/mach-tegra/tegra124/clock.c
index 4ac0c10..0ea212f 100644
--- a/arch/arm/mach-tegra/tegra124/clock.c
+++ b/arch/arm/mach-tegra/tegra124/clock.c
@@ -598,6 +598,8 @@
.lock_ena = 9, .lock_det = 11, .kcp_shift = 6, .kcp_mask = 3, .kvco_shift = 0, .kvco_mask = 1 }, /* PLLE */
{ .m_shift = 0, .m_mask = 0x0F, .n_shift = 8, .n_mask = 0x3FF, .p_shift = 20, .p_mask = 0x07,
.lock_ena = 18, .lock_det = 27, .kcp_shift = 8, .kcp_mask = 0xF, .kvco_shift = 4, .kvco_mask = 0xF }, /* PLLS (RESERVED) */
+ { .m_shift = 0, .m_mask = 0x1F, .n_shift = 8, .n_mask = 0x3FF, .p_shift = 20, .p_mask = 0x07,
+ .lock_ena = 22, .lock_det = 27, .kcp_shift = 8, .kcp_mask = 0xF, .kvco_shift = 4, .kvco_mask = 0xF }, /* PLLD2 */
{ .m_shift = 0, .m_mask = 0xFF, .n_shift = 8, .n_mask = 0xFF, .p_shift = 20, .p_mask = 0xF,
.lock_ena = 30, .lock_det = 27, .kcp_shift = 25, .kcp_mask = 3, .kvco_shift = 24, .kvco_mask = 1 }, /* PLLDP */
};
@@ -852,6 +854,9 @@
case TEGRA124_CLK_PLL_D:
case TEGRA124_CLK_PLL_D_OUT0:
return CLOCK_ID_DISPLAY;
+ case TEGRA124_CLK_PLL_D2:
+ case TEGRA124_CLK_PLL_D2_OUT0:
+ return CLOCK_ID_DISPLAY2;
case TEGRA124_CLK_PLL_X:
return CLOCK_ID_XCPU;
case TEGRA124_CLK_PLL_E:
@@ -1194,6 +1199,8 @@
case CLOCK_ID_EPCI:
case CLOCK_ID_SFROM32KHZ:
return &clkrst->crc_pll_simple[clkid - CLOCK_ID_FIRST_SIMPLE];
+ case CLOCK_ID_DISPLAY2:
+ return &clkrst->plld2;
case CLOCK_ID_DP:
return &clkrst->plldp;
default:
diff --git a/arch/arm/mach-tegra/tegra20/Kconfig b/arch/arm/mach-tegra/tegra20/Kconfig
index 6458827..e2735d9 100644
--- a/arch/arm/mach-tegra/tegra20/Kconfig
+++ b/arch/arm/mach-tegra/tegra20/Kconfig
@@ -33,6 +33,10 @@
bool "Paz00 board"
select BOARD_LATE_INIT
+config TARGET_PICASSO
+ bool "Acer Tegra20 Picasso board"
+ select BOARD_LATE_INIT
+
config TARGET_PLUTUX
bool "Avionic Design Plutux board"
select BOARD_LATE_INIT
@@ -73,6 +77,7 @@
source "board/nvidia/harmony/Kconfig"
source "board/avionic-design/medcom-wide/Kconfig"
source "board/compal/paz00/Kconfig"
+source "board/acer/picasso/Kconfig"
source "board/avionic-design/plutux/Kconfig"
source "board/nvidia/seaboard/Kconfig"
source "board/avionic-design/tec/Kconfig"
diff --git a/arch/arm/mach-tegra/tegra210/clock.c b/arch/arm/mach-tegra/tegra210/clock.c
index 57ff0b2..04708f9 100644
--- a/arch/arm/mach-tegra/tegra210/clock.c
+++ b/arch/arm/mach-tegra/tegra210/clock.c
@@ -668,6 +668,8 @@
.lock_ena = 9, .lock_det = 11, .kcp_shift = 6, .kcp_mask = 3, .kvco_shift = 0, .kvco_mask = 1 }, /* PLLE */
{ .m_shift = 0, .m_mask = 0, .n_shift = 0, .n_mask = 0, .p_shift = 0, .p_mask = 0,
.lock_ena = 0, .lock_det = 0, .kcp_shift = 0, .kcp_mask = 0, .kvco_shift = 0, .kvco_mask = 0 }, /* PLLS (gone)*/
+ { .m_shift = 0, .m_mask = 0x1F, .n_shift = 8, .n_mask = 0x3FF, .p_shift = 20, .p_mask = 0x07,
+ .lock_ena = 22, .lock_det = 27, .kcp_shift = 8, .kcp_mask = 0xF, .kvco_shift = 4, .kvco_mask = 0xF }, /* PLLD2 */
{ .m_shift = 0, .m_mask = 0xFF, .n_shift = 8, .n_mask = 0xFF, .p_shift = 19, .p_mask = 0x1F,
.lock_ena = 30, .lock_det = 27, .kcp_shift = 25, .kcp_mask = 3, .kvco_shift = 24, .kvco_mask = 1 }, /* PLLDP */
};
@@ -939,6 +941,9 @@
case TEGRA210_CLK_PLL_D:
case TEGRA210_CLK_PLL_D_OUT0:
return CLOCK_ID_DISPLAY;
+ case TEGRA210_CLK_PLL_D2:
+ case TEGRA210_CLK_PLL_D2_OUT0:
+ return CLOCK_ID_DISPLAY2;
case TEGRA210_CLK_PLL_X:
return CLOCK_ID_XCPU;
case TEGRA210_CLK_PLL_E:
@@ -1276,6 +1281,8 @@
case CLOCK_ID_EPCI:
case CLOCK_ID_SFROM32KHZ:
return &clkrst->crc_pll_simple[clkid - CLOCK_ID_FIRST_SIMPLE];
+ case CLOCK_ID_DISPLAY2:
+ return &clkrst->plld2;
default:
return NULL;
}
diff --git a/board/acer/picasso/Kconfig b/board/acer/picasso/Kconfig
new file mode 100644
index 0000000..73c0aa0
--- /dev/null
+++ b/board/acer/picasso/Kconfig
@@ -0,0 +1,12 @@
+if TARGET_PICASSO
+
+config SYS_BOARD
+ default "picasso"
+
+config SYS_VENDOR
+ default "acer"
+
+config SYS_CONFIG_NAME
+ default "picasso"
+
+endif
diff --git a/board/acer/picasso/MAINTAINERS b/board/acer/picasso/MAINTAINERS
new file mode 100644
index 0000000..99f8c0b
--- /dev/null
+++ b/board/acer/picasso/MAINTAINERS
@@ -0,0 +1,7 @@
+PICASSO BOARD
+M: Svyatoslav Ryhel <clamor95@gmail.com>
+S: Maintained
+F: board/acer/picasso/
+F: configs/picasso_defconfig
+F: doc/board/acer/picasso.rst
+F: include/configs/picasso.h
diff --git a/board/acer/picasso/Makefile b/board/acer/picasso/Makefile
new file mode 100644
index 0000000..675059c
--- /dev/null
+++ b/board/acer/picasso/Makefile
@@ -0,0 +1,9 @@
+# SPDX-License-Identifier: GPL-2.0+
+#
+# (C) Copyright 2010,2011
+# NVIDIA Corporation <www.nvidia.com>
+#
+# (C) Copyright 2024
+# Svyatoslav Ryhel <clamor95@gmail.com>
+
+obj-y += picasso.o
diff --git a/board/acer/picasso/picasso.c b/board/acer/picasso/picasso.c
new file mode 100644
index 0000000..d3e600c
--- /dev/null
+++ b/board/acer/picasso/picasso.c
@@ -0,0 +1,57 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * (C) Copyright 2010,2011
+ * NVIDIA Corporation <www.nvidia.com>
+ *
+ * (C) Copyright 2024
+ * Svyatoslav Ryhel <clamor95@gmail.com>
+ */
+
+/* Picasso derives from Ventana board */
+
+#include <dm.h>
+#include <i2c.h>
+#include <log.h>
+#include <linux/delay.h>
+
+#define TPS6586X_I2C_ADDRESS 0x34
+#define TPS6586X_SUPPLYENE 0x14
+#define EXITSLREQ_BIT BIT(1)
+#define SLEEP_MODE_BIT BIT(3)
+
+#ifdef CONFIG_CMD_POWEROFF
+int do_poweroff(struct cmd_tbl *cmdtp,
+ int flag, int argc, char *const argv[])
+{
+ struct udevice *dev;
+ uchar data_buffer[1];
+ int ret;
+
+ ret = i2c_get_chip_for_busnum(0, TPS6586X_I2C_ADDRESS, 1, &dev);
+ if (ret) {
+ log_debug("cannot find PMIC I2C chip\n");
+ return 0;
+ }
+
+ ret = dm_i2c_read(dev, TPS6586X_SUPPLYENE, data_buffer, 1);
+ if (ret)
+ return ret;
+
+ data_buffer[0] &= ~EXITSLREQ_BIT;
+
+ ret = dm_i2c_write(dev, TPS6586X_SUPPLYENE, data_buffer, 1);
+ if (ret)
+ return ret;
+
+ data_buffer[0] |= SLEEP_MODE_BIT;
+
+ ret = dm_i2c_write(dev, TPS6586X_SUPPLYENE, data_buffer, 1);
+ if (ret)
+ return ret;
+
+ // wait some time and then print error
+ mdelay(5000);
+ printf("Failed to power off!!!\n");
+ return 1;
+}
+#endif
diff --git a/board/acer/picasso/picasso.env b/board/acer/picasso/picasso.env
new file mode 100644
index 0000000..d9409b0
--- /dev/null
+++ b/board/acer/picasso/picasso.env
@@ -0,0 +1,18 @@
+#include <env/nvidia/prod_upd.env>
+
+button_cmd_0_name=Volume Down
+button_cmd_0=bootmenu
+partitions=name=emmc,start=0,size=-,uuid=${uuid_gpt_rootfs}
+
+boot_block_size_r=0x100000
+boot_block_size=0x800
+boot_dev=1
+
+bootmenu_0=mount internal storage=usb start && ums 0 mmc 0; bootmenu
+bootmenu_1=mount external storage=usb start && ums 0 mmc 1; bootmenu
+bootmenu_2=fastboot=echo Starting Fastboot protocol ...; fastboot usb 0; bootmenu
+bootmenu_3=update bootloader=run flash_uboot
+bootmenu_4=reboot RCM=enterrcm
+bootmenu_5=reboot=reset
+bootmenu_6=power off=poweroff
+bootmenu_delay=-1
diff --git a/board/asus/grouper/Makefile b/board/asus/grouper/Makefile
index 8a8e653..b83b7fc 100644
--- a/board/asus/grouper/Makefile
+++ b/board/asus/grouper/Makefile
@@ -6,7 +6,7 @@
# (C) Copyright 2021
# Svyatoslav Ryhel <clamor95@gmail.com>
-obj-$(CONFIG_SPL_BUILD) += grouper-spl.o
+obj-$(CONFIG_XPL_BUILD) += grouper-spl.o
obj-$(CONFIG_MULTI_DTB_FIT) += board-info.o
obj-y += grouper.o
diff --git a/board/asus/transformer-t30/Makefile b/board/asus/transformer-t30/Makefile
index 22b6160..b8617f8 100644
--- a/board/asus/transformer-t30/Makefile
+++ b/board/asus/transformer-t30/Makefile
@@ -6,7 +6,7 @@
# (C) Copyright 2021
# Svyatoslav Ryhel <clamor95@gmail.com>
-obj-$(CONFIG_SPL_BUILD) += transformer-t30-spl.o
+obj-$(CONFIG_XPL_BUILD) += transformer-t30-spl.o
obj-$(CONFIG_MULTI_DTB_FIT) += board-info.o
obj-y += transformer-t30.o
diff --git a/board/asus/transformer-t30/board-info.c b/board/asus/transformer-t30/board-info.c
index a2b540c..e726141 100644
--- a/board/asus/transformer-t30/board-info.c
+++ b/board/asus/transformer-t30/board-info.c
@@ -11,14 +11,14 @@
#include <asm/arch/pinmux.h>
/*
- * PCB_ID[1] is kb_row5_pr5
* PCB_ID[3] is kb_col7_pq7
* PCB_ID[4] is kb_row2_pr2
* PCB_ID[5] is kb_col5_pq5
+ * PCB_ID[7] is gmi_cs1_n_pj2
*
* Project ID
* =====================================================
- * PCB_ID[1] PCB_ID[5] PCB_ID[4] PCB_ID[3] Project
+ * PCB_ID[7] PCB_ID[5] PCB_ID[4] PCB_ID[3] Project
* 0 0 0 0 TF201
* 0 0 0 1 P1801
* 0 0 1 0 TF300T
@@ -45,10 +45,10 @@
[TF600T] = "tegra30-asus-tf600t",
};
-static int id_gpio_get_value(u32 pingrp, u32 pin)
+static int id_gpio_get_value(u32 pingrp, u32 func, u32 pin)
{
/* Configure pinmux */
- pinmux_set_func(pingrp, PMUX_FUNC_KBC);
+ pinmux_set_func(pingrp, func);
pinmux_set_pullupdown(pingrp, PMUX_PULL_DOWN);
pinmux_tristate_enable(pingrp);
pinmux_set_io(pingrp, PMUX_PIN_INPUT);
@@ -65,19 +65,19 @@
static int get_project_id(void)
{
- u32 pcb_id1, pcb_id3, pcb_id4, pcb_id5;
+ u32 pcb_id3, pcb_id4, pcb_id5, pcb_id7;
- pcb_id1 = id_gpio_get_value(PMUX_PINGRP_KB_ROW5_PR5,
- TEGRA_GPIO(R, 5));
pcb_id3 = id_gpio_get_value(PMUX_PINGRP_KB_COL7_PQ7,
- TEGRA_GPIO(Q, 7));
+ PMUX_FUNC_KBC, TEGRA_GPIO(Q, 7));
pcb_id4 = id_gpio_get_value(PMUX_PINGRP_KB_ROW2_PR2,
- TEGRA_GPIO(R, 2));
+ PMUX_FUNC_KBC, TEGRA_GPIO(R, 2));
pcb_id5 = id_gpio_get_value(PMUX_PINGRP_KB_COL5_PQ5,
- TEGRA_GPIO(Q, 5));
+ PMUX_FUNC_KBC, TEGRA_GPIO(Q, 5));
+ pcb_id7 = id_gpio_get_value(PMUX_PINGRP_GMI_CS1_N_PJ2,
+ PMUX_FUNC_RSVD1, TEGRA_GPIO(J, 2));
/* Construct board ID */
- int proj_id = pcb_id1 << 3 | pcb_id5 << 2 |
+ int proj_id = pcb_id7 << 3 | pcb_id5 << 2 |
pcb_id4 << 1 | pcb_id3;
log_debug("[TRANSFORMER]: project id %d (%s)\n", proj_id,
diff --git a/board/gdsys/a38x/ihs_phys.c b/board/gdsys/a38x/ihs_phys.c
index 690a296..0c68087 100644
--- a/board/gdsys/a38x/ihs_phys.c
+++ b/board/gdsys/a38x/ihs_phys.c
@@ -102,102 +102,6 @@
return octo_phy_mask;
}
-int register_miiphy_bus(uint k, struct mii_dev **bus)
-{
- int retval;
- struct mii_dev *mdiodev = mdio_alloc();
- char *name = bb_miiphy_buses[k].name;
-
- if (!mdiodev)
- return -ENOMEM;
- strlcpy(mdiodev->name, name, MDIO_NAME_LEN);
- mdiodev->read = bb_miiphy_read;
- mdiodev->write = bb_miiphy_write;
-
- retval = mdio_register(mdiodev);
- if (retval < 0)
- return retval;
- *bus = miiphy_get_dev_by_name(name);
-
- return 0;
-}
-
-struct porttype *get_porttype(uint octo_phy_mask, uint k)
-{
- uint octo_index = k * 4;
-
- if (!k) {
- if (octo_phy_mask & 0x01)
- return &porttypes[PORTTYPE_MAIN_CAT];
- else if (!(octo_phy_mask & 0x03))
- return &porttypes[PORTTYPE_16C_16F];
- } else {
- if (octo_phy_mask & (1 << octo_index))
- return &porttypes[PORTTYPE_TOP_CAT];
- }
-
- return NULL;
-}
-
-int init_single_phy(struct porttype *porttype, struct mii_dev *bus,
- uint bus_idx, uint m, uint phy_idx)
-{
- struct phy_device *phydev;
-
- phydev = phy_find_by_mask(bus, BIT(m * 8 + phy_idx));
- printf(" %u", bus_idx * 32 + m * 8 + phy_idx);
-
- if (!phydev)
- puts("!");
- else
- ihs_phy_config(phydev, porttype->phy_invert_in_pol,
- porttype->phy_invert_out_pol);
-
- return 0;
-}
-
-int init_octo_phys(uint octo_phy_mask)
-{
- uint bus_idx;
-
- /* there are up to four octo-phys on each mdio bus */
- for (bus_idx = 0; bus_idx < bb_miiphy_buses_num; ++bus_idx) {
- uint m;
- uint octo_index = bus_idx * 4;
- struct mii_dev *bus = NULL;
- struct porttype *porttype = NULL;
- int ret;
-
- porttype = get_porttype(octo_phy_mask, bus_idx);
-
- if (!porttype)
- continue;
-
- for (m = 0; m < 4; ++m) {
- uint phy_idx;
-
- /**
- * Register a bus device if there is at least one phy
- * on the current bus
- */
- if (!m && octo_phy_mask & (0xf << octo_index)) {
- ret = register_miiphy_bus(bus_idx, &bus);
- if (ret)
- return ret;
- }
-
- if (!(octo_phy_mask & BIT(octo_index + m)))
- continue;
-
- for (phy_idx = 0; phy_idx < 8; ++phy_idx)
- init_single_phy(porttype, bus, bus_idx, m,
- phy_idx);
- }
- }
-
- return 0;
-}
-
/*
* MII GPIO bitbang implementation
* MDC MDIO bus
@@ -315,40 +219,109 @@
return 0;
}
-struct bb_miiphy_bus bb_miiphy_buses[] = {
- {
- .name = "ihs0",
- .init = mii_mdio_init,
- .mdio_active = mii_mdio_active,
- .mdio_tristate = mii_mdio_tristate,
- .set_mdio = mii_set_mdio,
- .get_mdio = mii_get_mdio,
- .set_mdc = mii_set_mdc,
- .delay = mii_delay,
- .priv = &gpio_mii_set[0],
- },
- {
- .name = "ihs1",
- .init = mii_mdio_init,
- .mdio_active = mii_mdio_active,
- .mdio_tristate = mii_mdio_tristate,
- .set_mdio = mii_set_mdio,
- .get_mdio = mii_get_mdio,
- .set_mdc = mii_set_mdc,
- .delay = mii_delay,
- .priv = &gpio_mii_set[1],
- },
- {
- .name = "ihs2",
- .init = mii_mdio_init,
- .mdio_active = mii_mdio_active,
- .mdio_tristate = mii_mdio_tristate,
- .set_mdio = mii_set_mdio,
- .get_mdio = mii_get_mdio,
- .set_mdc = mii_set_mdc,
- .delay = mii_delay,
- .priv = &gpio_mii_set[2],
- },
-};
+int register_miiphy_bus(uint k, struct mii_dev **bus)
+{
+ struct bb_miiphy_bus *bb_miiphy = bb_miiphy_alloc();
+ struct mii_dev *mdiodev;
+ int retval;
+
+ if (!bb_miiphy)
+ return -ENOMEM;
+
+ mdiodev = &bb_miiphy->mii;
+ snprintf(mdiodev->name, MDIO_NAME_LEN, "ihs%d", k);
+ mdiodev->read = bb_miiphy_read;
+ mdiodev->write = bb_miiphy_write;
+
+ /* Copy the bus accessors and private data */
+ bb_miiphy->mdio_active = mii_mdio_active;
+ bb_miiphy->mdio_tristate = mii_mdio_tristate;
+ bb_miiphy->set_mdio = mii_set_mdio;
+ bb_miiphy->get_mdio = mii_get_mdio;
+ bb_miiphy->set_mdc = mii_set_mdc;
+ bb_miiphy->delay = mii_delay;
+ bb_miiphy->priv = &gpio_mii_set[k];
+
+ retval = mdio_register(mdiodev);
+ if (retval < 0)
+ return retval;
+ *bus = &bb_miiphy->mii;
+
+ return mii_mdio_init(bb_miiphy);
+}
+
+struct porttype *get_porttype(uint octo_phy_mask, uint k)
+{
+ uint octo_index = k * 4;
+
+ if (!k) {
+ if (octo_phy_mask & 0x01)
+ return &porttypes[PORTTYPE_MAIN_CAT];
+ else if (!(octo_phy_mask & 0x03))
+ return &porttypes[PORTTYPE_16C_16F];
+ } else {
+ if (octo_phy_mask & (1 << octo_index))
+ return &porttypes[PORTTYPE_TOP_CAT];
+ }
+
+ return NULL;
+}
+
+int init_single_phy(struct porttype *porttype, struct mii_dev *bus,
+ uint bus_idx, uint m, uint phy_idx)
+{
+ struct phy_device *phydev;
+
+ phydev = phy_find_by_mask(bus, BIT(m * 8 + phy_idx));
+ printf(" %u", bus_idx * 32 + m * 8 + phy_idx);
+
+ if (!phydev)
+ puts("!");
+ else
+ ihs_phy_config(phydev, porttype->phy_invert_in_pol,
+ porttype->phy_invert_out_pol);
+
+ return 0;
+}
+
+int init_octo_phys(uint octo_phy_mask)
+{
+ uint bus_idx;
-int bb_miiphy_buses_num = ARRAY_SIZE(bb_miiphy_buses);
+ /* there are up to four octo-phys on each mdio bus */
+ for (bus_idx = 0; bus_idx < ARRAY_SIZE(gpio_mii_set); ++bus_idx) {
+ uint m;
+ uint octo_index = bus_idx * 4;
+ struct mii_dev *bus = NULL;
+ struct porttype *porttype = NULL;
+ int ret;
+
+ porttype = get_porttype(octo_phy_mask, bus_idx);
+
+ if (!porttype)
+ continue;
+
+ for (m = 0; m < 4; ++m) {
+ uint phy_idx;
+
+ /**
+ * Register a bus device if there is at least one phy
+ * on the current bus
+ */
+ if (!m && octo_phy_mask & (0xf << octo_index)) {
+ ret = register_miiphy_bus(bus_idx, &bus);
+ if (ret)
+ return ret;
+ }
+
+ if (!(octo_phy_mask & BIT(octo_index + m)))
+ continue;
+
+ for (phy_idx = 0; phy_idx < 8; ++phy_idx)
+ init_single_phy(porttype, bus, bus_idx, m,
+ phy_idx);
+ }
+ }
+
+ return 0;
+}
diff --git a/board/intel/agilex5-socdk/Makefile b/board/intel/agilex5-socdk/Makefile
new file mode 100644
index 0000000..306a8cf
--- /dev/null
+++ b/board/intel/agilex5-socdk/Makefile
@@ -0,0 +1,7 @@
+#
+# Copyright (C) 2025 Altera Corporation <www.altera.com>
+#
+# SPDX-License-Identifier: GPL-2.0
+#
+
+obj-y := socfpga.o
diff --git a/board/intel/agilex5-socdk/socfpga.c b/board/intel/agilex5-socdk/socfpga.c
new file mode 100644
index 0000000..d6628cf
--- /dev/null
+++ b/board/intel/agilex5-socdk/socfpga.c
@@ -0,0 +1,12 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (C) 2025 Altera Corporation <www.altera.com>
+ */
+
+#include <asm/arch/misc.h>
+
+int board_early_init_f(void)
+{
+ socfpga_get_sys_mgr_addr("sysmgr@10d12000");
+ return 0;
+}
diff --git a/board/nuvoton/arbel_evb/arbel_evb.c b/board/nuvoton/arbel_evb/arbel_evb.c
index 55e93a7..699e5ca 100644
--- a/board/nuvoton/arbel_evb/arbel_evb.c
+++ b/board/nuvoton/arbel_evb/arbel_evb.c
@@ -4,6 +4,7 @@
*/
#include <dm.h>
+#include <event.h>
#include <asm/io.h>
#include <asm/arch/gcr.h>
#include "../common/uart.h"
@@ -98,9 +99,5 @@
return 0;
}
-int last_stage_init(void)
-{
- board_set_console();
+EVENT_SPY_SIMPLE(EVT_LAST_STAGE_INIT, board_set_console);
- return 0;
-}
diff --git a/board/nuvoton/common/uart.c b/board/nuvoton/common/uart.c
index b35c795..06f6378 100644
--- a/board/nuvoton/common/uart.c
+++ b/board/nuvoton/common/uart.c
@@ -14,7 +14,7 @@
#define UART_LCR 0xc
#define LCR_DLAB BIT(7)
-void board_set_console(void)
+int board_set_console(void)
{
const unsigned long baudrate_table[] = CFG_SYS_BAUDRATE_TABLE;
struct udevice *dev = gd->cur_serial_dev;
@@ -28,12 +28,12 @@
int ret, i;
if (!dev)
- return;
+ return -ENODEV;
uart_reg = dev_read_addr_ptr(dev);
ret = clk_get_by_index(dev, 0, &clk);
if (ret)
- return;
+ return ret;
uart_clk = clk_get_rate(&clk);
setbits_8(uart_reg + UART_LCR, LCR_DLAB);
@@ -67,4 +67,5 @@
snprintf(string, sizeof(string), "ttyS0,%un8", gd->baudrate);
env_set("console", string);
+ return 0;
}
diff --git a/board/nuvoton/common/uart.h b/board/nuvoton/common/uart.h
index 9cc8952..fc8ec47 100644
--- a/board/nuvoton/common/uart.h
+++ b/board/nuvoton/common/uart.h
@@ -6,6 +6,6 @@
#ifndef _NUVOTON_UART_H
#define _NUVOTON_UART_H
-void board_set_console(void);
+int board_set_console(void);
#endif /* _NUVOTON_COMMON_H */
diff --git a/board/nuvoton/poleg_evb/poleg_evb.c b/board/nuvoton/poleg_evb/poleg_evb.c
index 3c4e5aa..2faa349 100644
--- a/board/nuvoton/poleg_evb/poleg_evb.c
+++ b/board/nuvoton/poleg_evb/poleg_evb.c
@@ -6,6 +6,7 @@
#include <dm.h>
#include <env.h>
+#include <event.h>
#include <asm/io.h>
#include <asm/arch/gcr.h>
#include <asm/mach-types.h>
@@ -48,7 +49,7 @@
return 0;
}
-int last_stage_init(void)
+static int last_stage_init(void)
{
char value[32];
@@ -68,8 +69,10 @@
}
sprintf(value, "ttyS%d,115200n8", dev->seq_);
env_set("console", value);
- board_set_console();
+ return board_set_console();
}
return 0;
}
+EVENT_SPY_SIMPLE(EVT_LAST_STAGE_INIT, last_stage_init);
+
diff --git a/board/phytec/phycore_am62x/phycore_am62x.env b/board/phytec/phycore_am62x/phycore_am62x.env
index 711ca30..024f38e 100644
--- a/board/phytec/phycore_am62x/phycore_am62x.env
+++ b/board/phytec/phycore_am62x/phycore_am62x.env
@@ -22,4 +22,4 @@
spi_fdt_addr=0x700000
spi_image_addr=0x800000
-spi_ramdisk_addr=0x1e00000
+spi_ramdisk_addr=0x2200000
diff --git a/board/phytec/phycore_am64x/phycore_am64x.env b/board/phytec/phycore_am64x/phycore_am64x.env
index 3032b51..d69dfe7 100644
--- a/board/phytec/phycore_am64x/phycore_am64x.env
+++ b/board/phytec/phycore_am64x/phycore_am64x.env
@@ -21,4 +21,4 @@
spi_fdt_addr=0x700000
spi_image_addr=0x800000
-spi_ramdisk_addr=0x1e00000
+spi_ramdisk_addr=0x2200000
diff --git a/board/siemens/common/Kconfig b/board/siemens/common/Kconfig
index 4ae12b1..3808257 100644
--- a/board/siemens/common/Kconfig
+++ b/board/siemens/common/Kconfig
@@ -3,4 +3,5 @@
config DDR_SI_TEST
bool "DDR signal integrity test implementations"
+ depends on TARGET_CAPRICORN
default y
diff --git a/board/siemens/iot2050/board.c b/board/siemens/iot2050/board.c
index e6bedc3..d827f72 100644
--- a/board/siemens/iot2050/board.c
+++ b/board/siemens/iot2050/board.c
@@ -25,28 +25,7 @@
#include <asm/gpio.h>
#include <asm/io.h>
-#define IOT2050_INFO_MAGIC 0x20502050
-
-struct iot2050_info {
- u32 magic;
- u16 size;
- char name[20 + 1];
- char serial[16 + 1];
- char mlfb[18 + 1];
- char uuid[32 + 1];
- char a5e[18 + 1];
- u8 mac_addr_cnt;
- u8 mac_addr[8][ARP_HLEN];
- char seboot_version[40 + 1];
- u8 padding[3];
- u32 ddr_size_mb;
-} __packed;
-
-/*
- * Scratch SRAM (available before DDR RAM) contains extracted EEPROM data.
- */
-#define IOT2050_INFO_DATA ((struct iot2050_info *) \
- TI_SRAM_SCRATCH_BOARD_EEPROM_START)
+#include "../../../../drivers/sysinfo/iot2050.h"
DECLARE_GLOBAL_DATA_PTR;
@@ -117,6 +96,8 @@
static enum m2_connector_mode connector_mode;
+static char iot2050_board_name[21];
+
#if defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP)
static void *connector_overlay;
static u32 connector_overlay_size;
@@ -149,37 +130,57 @@
dm_gpio_set_value(&gpio, value);
}
+static bool setup_sysinfo(struct udevice **sysinfo_ptr)
+{
+ if (sysinfo_get(sysinfo_ptr)) {
+ pr_err("Could not find sysinfo device.\n");
+ return false;
+ }
+ if (sysinfo_detect(*sysinfo_ptr)) {
+ pr_err("Board info parsing error\n");
+ return false;
+ }
+ return true;
+}
+
+static void get_board_name(void)
+{
+ struct udevice *sysinfo;
+
+ if (iot2050_board_name[0] != 0)
+ return;
+
+ if (!setup_sysinfo(&sysinfo))
+ return;
+
+ sysinfo_get_str(sysinfo, BOARD_NAME, sizeof(iot2050_board_name),
+ iot2050_board_name);
+}
+
static bool board_is_advanced(void)
{
- struct iot2050_info *info = IOT2050_INFO_DATA;
- return info->magic == IOT2050_INFO_MAGIC &&
- strstr((char *)info->name, "IOT2050-ADVANCED") != NULL;
+ get_board_name();
+ return strstr(iot2050_board_name, "IOT2050-ADVANCED") != NULL;
}
static bool board_is_pg1(void)
{
- struct iot2050_info *info = IOT2050_INFO_DATA;
-
- return info->magic == IOT2050_INFO_MAGIC &&
- (strcmp((char *)info->name, "IOT2050-BASIC") == 0 ||
- strcmp((char *)info->name, "IOT2050-ADVANCED") == 0);
+ get_board_name();
+ return strcmp(iot2050_board_name, "IOT2050-BASIC") == 0 ||
+ strcmp(iot2050_board_name, "IOT2050-ADVANCED") == 0;
}
static bool board_is_m2(void)
{
- struct iot2050_info *info = IOT2050_INFO_DATA;
-
- return info->magic == IOT2050_INFO_MAGIC &&
- strcmp((char *)info->name, "IOT2050-ADVANCED-M2") == 0;
+ get_board_name();
+ return strcmp(iot2050_board_name, "IOT2050-ADVANCED-M2") == 0;
}
static bool board_is_sm(void)
{
- struct iot2050_info *info = IOT2050_INFO_DATA;
-
- return info->magic == IOT2050_INFO_MAGIC &&
- strcmp((char *)info->name, "IOT2050-ADVANCED-SM") == 0;
+ get_board_name();
+ return strcmp(iot2050_board_name, "IOT2050-ADVANCED-SM") == 0;
}
static void remove_mmc1_target(void)
@@ -206,33 +207,43 @@
void set_board_info_env(void)
{
- struct iot2050_info *info = IOT2050_INFO_DATA;
- u8 __maybe_unused mac_cnt;
+ struct udevice *sysinfo;
const char *fdtfile;
+ char buf[41];
- if (info->magic != IOT2050_INFO_MAGIC) {
- pr_err("IOT2050: Board info parsing error!\n");
+ if (env_get("board_uuid"))
return;
- }
- if (env_get("board_uuid"))
+ if (!setup_sysinfo(&sysinfo))
return;
- env_set("board_name", info->name);
- env_set("board_serial", info->serial);
- env_set("mlfb", info->mlfb);
- env_set("board_uuid", info->uuid);
- env_set("board_a5e", info->a5e);
+ if (sysinfo_get_str(sysinfo, BOARD_NAME, sizeof(buf), buf) == 0)
+ env_set("board_name", buf);
+ if (sysinfo_get_str(sysinfo, SYSID_SM_SYSTEM_SERIAL, sizeof(buf), buf) == 0)
+ env_set("board_serial", buf);
+ if (sysinfo_get_str(sysinfo, BOARD_MLFB, sizeof(buf), buf) == 0)
+ env_set("mlfb", buf);
+ if (sysinfo_get_str(sysinfo, BOARD_UUID, sizeof(buf), buf) == 0)
+ env_set("board_uuid", buf);
+ if (sysinfo_get_str(sysinfo, BOARD_A5E, sizeof(buf), buf) == 0)
+ env_set("board_a5e", buf);
+ if (sysinfo_get_str(sysinfo, BOARD_SEBOOT_VER, sizeof(buf), buf) == 0)
+ env_set("seboot_version", buf);
env_set("fw_version", PLAIN_VERSION);
- env_set("seboot_version", info->seboot_version);
if (IS_ENABLED(CONFIG_NET)) {
+ int mac_cnt;
+
+ mac_cnt = sysinfo_get_item_count(sysinfo, SYSID_BOARD_MAC_ADDR);
/* set MAC addresses to ensure forwarding to the OS */
- for (mac_cnt = 0; mac_cnt < info->mac_addr_cnt; mac_cnt++) {
- if (is_valid_ethaddr(info->mac_addr[mac_cnt]))
- eth_env_set_enetaddr_by_index("eth",
- mac_cnt + 1,
- info->mac_addr[mac_cnt]);
+ for (int i = 0; i < mac_cnt; i++) {
+ u8 *mac = NULL;
+ size_t bytes = 0;
+
+ sysinfo_get_data_by_index(sysinfo, SYSID_BOARD_MAC_ADDR,
+ i, (void **)&mac, &bytes);
+ if (bytes == ARP_HLEN && is_valid_ethaddr(mac))
+ eth_env_set_enetaddr_by_index("eth", i + 1, mac);
}
}
@@ -288,7 +299,7 @@
return;
fit_error:
- pr_err("M.2 device tree overlay %s not available,\n", overlay_path);
+ pr_err("M.2 device tree overlay %s not available.\n", overlay_path);
#endif
}
@@ -362,8 +373,15 @@
int dram_init(void)
{
- struct iot2050_info *info = IOT2050_INFO_DATA;
- gd->ram_size = ((phys_size_t)(info->ddr_size_mb)) << 20;
+ struct udevice *sysinfo;
+ u32 ddr_size_mb;
+
+ if (!setup_sysinfo(&sysinfo))
+ return -ENODEV;
+
+ sysinfo_get_int(sysinfo, SYSID_BOARD_RAM_SIZE_MB, &ddr_size_mb);
+
+ gd->ram_size = ((phys_size_t)(ddr_size_mb)) << 20;
return 0;
}
@@ -405,18 +423,18 @@
#ifdef CONFIG_SPL_LOAD_FIT
int board_fit_config_name_match(const char *name)
{
- struct iot2050_info *info = IOT2050_INFO_DATA;
char upper_name[32];
+ get_board_name();
+
/* skip the prefix "ti/k3-am65x8-" */
name += 13;
- if (info->magic != IOT2050_INFO_MAGIC ||
- strlen(name) >= sizeof(upper_name))
+ if (strlen(name) >= sizeof(upper_name))
return -1;
str_to_upper(name, upper_name, sizeof(upper_name));
- if (!strcmp(upper_name, (char *)info->name))
+ if (!strcmp(upper_name, iot2050_board_name))
return 0;
return -1;
diff --git a/board/st/stih410-b2260/board.c b/board/st/stih410-b2260/board.c
index a912712..8ad593c 100644
--- a/board/st/stih410-b2260/board.c
+++ b/board/st/stih410-b2260/board.c
@@ -7,11 +7,6 @@
#include <cpu_func.h>
#include <init.h>
#include <asm/cache.h>
-#include <asm/global_data.h>
-#include <linux/usb/otg.h>
-#include <dwc3-sti-glue.h>
-#include <dwc3-uboot.h>
-#include <usb.h>
DECLARE_GLOBAL_DATA_PTR;
@@ -43,31 +38,6 @@
}
#ifdef CONFIG_USB_DWC3
-static struct dwc3_device dwc3_device_data = {
- .maximum_speed = USB_SPEED_HIGH,
- .dr_mode = USB_DR_MODE_PERIPHERAL,
- .index = 0,
-};
-
-int board_usb_init(int index, enum usb_init_type init)
-{
- int node;
- const void *blob = gd->fdt_blob;
-
- /* find the snps,dwc3 node */
- node = fdt_node_offset_by_compatible(blob, -1, "snps,dwc3");
-
- dwc3_device_data.base = fdtdec_get_addr(blob, node, "reg");
-
- return dwc3_uboot_init(&dwc3_device_data);
-}
-
-int board_usb_cleanup(int index, enum usb_init_type init)
-{
- dwc3_uboot_exit(index);
- return 0;
-}
-
int g_dnl_board_usb_cable_connected(void)
{
return 1;
diff --git a/board/starfive/visionfive2/MAINTAINERS b/board/starfive/visionfive2/MAINTAINERS
index d7f638f..898e284 100644
--- a/board/starfive/visionfive2/MAINTAINERS
+++ b/board/starfive/visionfive2/MAINTAINERS
@@ -1,8 +1,7 @@
STARFIVE JH7110 VISIONFIVE2 BOARD
M: Minda Chen <minda.chen@starfivetech.com>
+M: Hal Feng <hal.feng@starfivetech.com>
S: Maintained
-F: arch/riscv/include/asm/arch-jh7110/
-F: board/starfive/visionfive2/
-F: include/configs/starfive-visionfive2.h
-F: configs/starfive_visionfive2_defconfig
-F: drivers/pci/pcie_starfive_jh7110.c
+F: drivers/ram/starfive/
+N: jh7110
+N: visionfive2
diff --git a/board/ti/am62px/am62px.env b/board/ti/am62px/am62px.env
index 2b2c938..f19e158 100644
--- a/board/ti/am62px/am62px.env
+++ b/board/ti/am62px/am62px.env
@@ -1,5 +1,6 @@
#include <env/ti/ti_common.env>
#include <env/ti/mmc.env>
+#include <env/ti/k3_dfu.env>
#if CONFIG_CMD_REMOTEPROC
#include <env/ti/k3_rproc.env>
@@ -13,7 +14,7 @@
${mtdparts}
run_kern=booti ${loadaddr} ${rd_spec} ${fdtaddr}
-boot_targets=mmc1 mmc0 pxe dhcp
+boot_targets=mmc1 mmc0 usb pxe dhcp
boot=mmc
mmcdev=1
bootpart=1:2
@@ -23,4 +24,4 @@
#if CONFIG_BOOTMETH_ANDROID
#include <env/ti/android.env>
adtb_idx=3
-#endif
\ No newline at end of file
+#endif
diff --git a/board/ti/j722s/j722s.env b/board/ti/j722s/j722s.env
index 10d6203..4cc66e8 100644
--- a/board/ti/j722s/j722s.env
+++ b/board/ti/j722s/j722s.env
@@ -1,5 +1,6 @@
#include <env/ti/ti_common.env>
#include <env/ti/mmc.env>
+#include <env/ti/k3_dfu.env>
#if CONFIG_CMD_REMOTEPROC
#include <env/ti/k3_rproc.env>
diff --git a/board/toradex/verdin-am62/verdin-am62.c b/board/toradex/verdin-am62/verdin-am62.c
index e948fc1..b80b39b 100644
--- a/board/toradex/verdin-am62/verdin-am62.c
+++ b/board/toradex/verdin-am62/verdin-am62.c
@@ -35,6 +35,17 @@
return 0;
}
+int dram_init_banksize(void)
+{
+ s32 ret;
+
+ ret = fdtdec_setup_memory_banksize();
+ if (ret)
+ printf("Error setting up memory banksize. %d\n", ret);
+
+ return ret;
+}
+
/*
* Avoid relocated U-Boot clash with Linux reserved-memory on 512 MB SoM
*/
diff --git a/boot/image-android.c b/boot/image-android.c
index fa4e14c..1746b01 100644
--- a/boot/image-android.c
+++ b/boot/image-android.c
@@ -696,7 +696,10 @@
ulong dtb_addr; /* address of DTB blob with specified index */
u32 i; /* index iterator */
- android_image_get_dtb_img_addr(hdr_addr, vendor_boot_img, &dtb_img_addr);
+ if (!android_image_get_dtb_img_addr(hdr_addr, vendor_boot_img,
+ &dtb_img_addr))
+ return false;
+
/* Check if DTB area of boot image is in DTBO format */
if (android_dt_check_header(dtb_img_addr)) {
return android_dt_get_fdt_by_index(dtb_img_addr, index, addr,
diff --git a/boot/image-fit.c b/boot/image-fit.c
index aa139da..41ab1f5 100644
--- a/boot/image-fit.c
+++ b/boot/image-fit.c
@@ -2175,6 +2175,7 @@
type_ok = fit_image_check_type(fit, noffset, image_type) ||
fit_image_check_type(fit, noffset, IH_TYPE_FIRMWARE) ||
fit_image_check_type(fit, noffset, IH_TYPE_TEE) ||
+ fit_image_check_type(fit, noffset, IH_TYPE_TFA_BL31) ||
(image_type == IH_TYPE_KERNEL &&
fit_image_check_type(fit, noffset, IH_TYPE_KERNEL_NOLOAD));
diff --git a/boot/image-pre-load.c b/boot/image-pre-load.c
index cc19017..adf3b34 100644
--- a/boot/image-pre-load.c
+++ b/boot/image-pre-load.c
@@ -3,13 +3,24 @@
* Copyright (C) 2021 Philippe Reynes <philippe.reynes@softathome.com>
*/
+#ifdef USE_HOSTCC
+#include "mkimage.h"
+#else
#include <asm/global_data.h>
-DECLARE_GLOBAL_DATA_PTR;
-#include <image.h>
#include <mapmem.h>
+DECLARE_GLOBAL_DATA_PTR;
+#endif /* !USE_HOSTCC*/
+#include <image.h>
#include <u-boot/sha256.h>
+#ifdef USE_HOSTCC
+/* Define compat stuff for use in tools. */
+typedef uint8_t u8;
+typedef uint16_t u16;
+typedef uint32_t u32;
+#endif
+
/*
* Offset of the image
*
@@ -17,6 +28,47 @@
*/
ulong image_load_offset;
+#ifdef USE_HOSTCC
+/* Host tools use these implementations to setup information related to the
+ * pre-load signatures
+ */
+static struct image_sig_info *host_info;
+
+#define log_info(fmt, args...) printf(fmt, ##args)
+#define log_err(fmt, args...) printf(fmt, ##args)
+
+void image_pre_load_sig_set_info(struct image_sig_info *info)
+{
+ host_info = info;
+}
+
+/*
+ * This function sets a pointer to information for the signature check.
+ * It expects that host_info has been initially provision by the host
+ * application.
+ *
+ * return:
+ * < 0 => an error has occurred
+ * 0 => OK
+ */
+static int image_pre_load_sig_setup(struct image_sig_info *info)
+{
+ if (!info) {
+ log_err("ERROR: info is NULL\n");
+ return -EINVAL;
+ }
+
+ if (!host_info) {
+ log_err("ERROR: host_info is NULL\n");
+ log_err("ERROR: Set it with image_pre_load_sig_set_info()\n");
+ return -EINVAL;
+ }
+
+ memcpy(info, host_info, sizeof(struct image_sig_info));
+
+ return 0;
+}
+#else
/*
* This function gathers information about the signature check
* that could be done before launching the image.
@@ -106,6 +158,7 @@
out:
return ret;
}
+#endif /* !USE_HOSTCC */
static int image_pre_load_sig_get_magic(ulong addr, u32 *magic)
{
diff --git a/boot/image.c b/boot/image.c
index abac254..139c5bd 100644
--- a/boot/image.c
+++ b/boot/image.c
@@ -183,6 +183,7 @@
{ IH_TYPE_FDT_LEGACY, "fdt_legacy", "legacy Image with Flat Device Tree ", },
{ IH_TYPE_RENESAS_SPKG, "spkgimage", "Renesas SPKG Image" },
{ IH_TYPE_STARFIVE_SPL, "sfspl", "StarFive SPL Image" },
+ { IH_TYPE_TFA_BL31, "tfa-bl31", "TFA BL31 Image", },
{ -1, "", "", },
};
diff --git a/cmd/Kconfig b/cmd/Kconfig
index 2f275bd..8dd4257 100644
--- a/cmd/Kconfig
+++ b/cmd/Kconfig
@@ -2162,6 +2162,7 @@
depends on CMD_WGET
depends on PROT_TCP_LWIP
depends on MBEDTLS_LIB
+ depends on DM_RNG
select SHA256
select RSA
select ASYMMETRIC_KEY_TYPE
diff --git a/common/Kconfig b/common/Kconfig
index 7b2db46..1d6de8b 100644
--- a/common/Kconfig
+++ b/common/Kconfig
@@ -1066,11 +1066,15 @@
specify a fixed address on systems where this is unknown or can
change at runtime.
-config BLOBLIST_PASSAGE
- bool "Use bloblist in-place"
+config BLOBLIST_PASSAGE_MANDATORY
+ bool "Use bloblist in-place mandatorily"
help
- Use a bloblist in the incoming standard passage. The size is detected
- automatically so CONFIG_BLOBLIST_SIZE can be 0.
+ By default U-Boot will use a bloblist in the incoming standard passage.
+ This option controls whether U-Boot tries to load a static bloblist or
+ allocate one if a valid incoming bloblist does not exist.
+ Select this option to mark incoming standard passage as mandatory and
+ U-Boot will report an error when a valid incoming bloblist does not
+ exist.
endchoice
@@ -1086,7 +1090,7 @@
config BLOBLIST_SIZE
hex "Size of bloblist"
- default 0x0 if BLOBLIST_PASSAGE
+ default 0x0 if BLOBLIST_PASSAGE_MANDATORY
default 0x400
help
Sets the size of the bloblist in bytes. This must include all
diff --git a/common/bloblist.c b/common/bloblist.c
index 31ba031..6e4f020 100644
--- a/common/bloblist.c
+++ b/common/bloblist.c
@@ -505,8 +505,7 @@
/*
* Weak default function for getting bloblist from boot args.
*/
-int __weak xferlist_from_boot_arg(ulong __always_unused addr,
- ulong __always_unused size)
+int __weak xferlist_from_boot_arg(ulong __always_unused *addr)
{
return -ENOENT;
}
@@ -514,37 +513,46 @@
int bloblist_init(void)
{
bool fixed = IS_ENABLED(CONFIG_BLOBLIST_FIXED);
- int ret = -ENOENT;
+ int ret = 0;
ulong addr = 0, size;
- /*
- * If U-Boot is not in the first phase, an existing bloblist must be
- * at a fixed address.
- */
- bool from_addr = fixed && !xpl_is_first_phase();
- if (xpl_prev_phase() == PHASE_TPL && !IS_ENABLED(CONFIG_TPL_BLOBLIST))
- from_addr = false;
- if (fixed)
- addr = IF_ENABLED_INT(CONFIG_BLOBLIST_FIXED,
- CONFIG_BLOBLIST_ADDR);
- size = CONFIG_BLOBLIST_SIZE;
+ /* Check if a valid transfer list passed in */
+ if (!xferlist_from_boot_arg(&addr)) {
+ size = bloblist_get_total_size();
+ } else {
+ /*
+ * If U-Boot is not in the first phase, an existing bloblist must
+ * be at a fixed address.
+ */
+ bool from_addr = fixed && !xpl_is_first_phase();
- /*
- * If the current boot stage is the first phase of U-Boot, then an
- * architecture-specific routine should be used to handle the bloblist
- * passed from the previous boot loader
- */
- if (xpl_is_first_phase() && !IS_ENABLED(CONFIG_BLOBLIST_ALLOC))
- ret = xferlist_from_boot_arg(addr, size);
- else if (from_addr)
- ret = bloblist_check(addr, size);
+ /*
+ * If Firmware Handoff is mandatory but no transfer list is
+ * observed, report it as an error.
+ */
+ if (IS_ENABLED(CONFIG_BLOBLIST_PASSAGE_MANDATORY))
+ return -ENOENT;
- if (ret)
- log_warning("Bloblist at %lx not found (err=%d)\n",
- addr, ret);
- else
- /* Get the real size */
- size = gd->bloblist->total_size;
+ ret = -ENOENT;
+
+ if (xpl_prev_phase() == PHASE_TPL &&
+ !IS_ENABLED(CONFIG_TPL_BLOBLIST))
+ from_addr = false;
+ if (fixed)
+ addr = IF_ENABLED_INT(CONFIG_BLOBLIST_FIXED,
+ CONFIG_BLOBLIST_ADDR);
+ size = CONFIG_BLOBLIST_SIZE;
+
+ if (from_addr)
+ ret = bloblist_check(addr, size);
+
+ if (ret)
+ log_warning("Bloblist at %lx not found (err=%d)\n",
+ addr, ret);
+ else
+ /* Get the real size */
+ size = gd->bloblist->total_size;
+ }
if (ret) {
/*
@@ -569,6 +577,7 @@
log_debug("Found existing bloblist size %lx at %lx\n", size,
addr);
}
+
if (ret)
return log_msg_ret("ini", ret);
gd->flags |= GD_FLG_BLOBLIST_READY;
@@ -589,10 +598,11 @@
return 0;
}
-int bloblist_check_reg_conv(ulong rfdt, ulong rzero, ulong rsig)
+int bloblist_check_reg_conv(ulong rfdt, ulong rzero, ulong rsig, ulong xlist)
{
u64 version = BLOBLIST_REGCONV_VER;
ulong sigval;
+ int ret;
if ((IS_ENABLED(CONFIG_64BIT) && !IS_ENABLED(CONFIG_SPL_BUILD)) ||
(IS_ENABLED(CONFIG_SPL_64BIT) && IS_ENABLED(CONFIG_SPL_BUILD))) {
@@ -603,8 +613,14 @@
((version & BLOBLIST_REGCONV_MASK) << BLOBLIST_REGCONV_SHIFT_32));
}
- if (rzero || rsig != sigval ||
- rfdt != (ulong)bloblist_find(BLOBLISTT_CONTROL_FDT, 0)) {
+ if (rzero || rsig != sigval)
+ return -EIO;
+
+ ret = bloblist_check(xlist, 0);
+ if (ret)
+ return ret;
+
+ if (rfdt != (ulong)bloblist_find(BLOBLISTT_CONTROL_FDT, 0)) {
gd->bloblist = NULL; /* Reset the gd bloblist pointer */
return -EIO;
}
diff --git a/common/board_f.c b/common/board_f.c
index 6c5c3bf..2912320 100644
--- a/common/board_f.c
+++ b/common/board_f.c
@@ -624,11 +624,14 @@
static int reserve_bloblist(void)
{
#ifdef CONFIG_BLOBLIST
+ ulong size = bloblist_get_total_size();
+
+ if (size < CONFIG_BLOBLIST_SIZE_RELOC)
+ size = CONFIG_BLOBLIST_SIZE_RELOC;
+
/* Align to a 4KB boundary for easier reading of addresses */
- gd->start_addr_sp = ALIGN_DOWN(gd->start_addr_sp -
- CONFIG_BLOBLIST_SIZE_RELOC, 0x1000);
- gd->boardf->new_bloblist = map_sysmem(gd->start_addr_sp,
- CONFIG_BLOBLIST_SIZE_RELOC);
+ gd->start_addr_sp = ALIGN_DOWN(gd->start_addr_sp - size, 0x1000);
+ gd->boardf->new_bloblist = map_sysmem(gd->start_addr_sp, size);
#endif
return 0;
@@ -698,11 +701,14 @@
return 0;
}
if (gd->boardf->new_bloblist) {
- debug("Copying bloblist from %p to %p, size %x\n",
- gd->bloblist, gd->boardf->new_bloblist,
- gd->bloblist->total_size);
- return bloblist_reloc(gd->boardf->new_bloblist,
- CONFIG_BLOBLIST_SIZE_RELOC);
+ ulong size = bloblist_get_total_size();
+
+ if (size < CONFIG_BLOBLIST_SIZE_RELOC)
+ size = CONFIG_BLOBLIST_SIZE_RELOC;
+
+ debug("Copying bloblist from %p to %p, size %lx\n",
+ gd->bloblist, gd->boardf->new_bloblist, size);
+ return bloblist_reloc(gd->boardf->new_bloblist, size);
}
#endif
diff --git a/common/board_r.c b/common/board_r.c
index 179259b..db0c5cb 100644
--- a/common/board_r.c
+++ b/common/board_r.c
@@ -749,9 +749,6 @@
#ifdef CONFIG_BOARD_LATE_INIT
board_late_init,
#endif
-#ifdef CONFIG_BITBANGMII
- bb_miiphy_init,
-#endif
#ifdef CONFIG_PCI_ENDPOINT
pci_ep_init,
#endif
diff --git a/common/miiphyutil.c b/common/miiphyutil.c
index 9b8744e..2a034d3 100644
--- a/common/miiphyutil.c
+++ b/common/miiphyutil.c
@@ -65,6 +65,14 @@
current_mii = NULL;
}
+void mdio_init(struct mii_dev *bus)
+{
+ memset(bus, 0, sizeof(*bus));
+
+ /* initialize mii_dev struct fields */
+ INIT_LIST_HEAD(&bus->link);
+}
+
struct mii_dev *mdio_alloc(void)
{
struct mii_dev *bus;
@@ -73,10 +81,7 @@
if (!bus)
return bus;
- memset(bus, 0, sizeof(*bus));
-
- /* initalize mii_dev struct fields */
- INIT_LIST_HEAD(&bus->link);
+ mdio_init(bus);
return bus;
}
diff --git a/configs/am57xx_evm_defconfig b/configs/am57xx_evm_defconfig
index d10d2a5..13260ed 100644
--- a/configs/am57xx_evm_defconfig
+++ b/configs/am57xx_evm_defconfig
@@ -10,7 +10,6 @@
CONFIG_SPL_TEXT_BASE=0x40300000
CONFIG_SYS_BOOTM_LEN=0x4000000
CONFIG_SPL=y
-CONFIG_ENV_OFFSET_REDUND=0x280000
CONFIG_SPL_SPI_FLASH_SUPPORT=y
CONFIG_SPL_SPI=y
CONFIG_ARMV7_LPAE=y
@@ -54,8 +53,7 @@
CONFIG_OF_CONTROL=y
CONFIG_SPL_OF_CONTROL=y
CONFIG_OF_LIST="am57xx-beagle-x15 am57xx-beagle-x15-revb1 am57xx-beagle-x15-revc am5729-beagleboneai am572x-idk am571x-idk am574x-idk"
-CONFIG_ENV_OVERWRITE=y
-CONFIG_ENV_IS_IN_MMC=y
+# CONFIG_ENV_IS_IN_FAT is not set
CONFIG_SYS_REDUNDAND_ENVIRONMENT=y
CONFIG_SYS_RELOC_GD_ENV_ADDR=y
CONFIG_SYS_MMC_ENV_DEV=1
diff --git a/configs/am57xx_hs_evm_defconfig b/configs/am57xx_hs_evm_defconfig
index 5cacd7f..a406e89 100644
--- a/configs/am57xx_hs_evm_defconfig
+++ b/configs/am57xx_hs_evm_defconfig
@@ -13,7 +13,6 @@
CONFIG_TARGET_AM57XX_EVM=y
CONFIG_SYS_BOOTM_LEN=0x4000000
CONFIG_SPL=y
-CONFIG_ENV_OFFSET_REDUND=0x280000
CONFIG_SPL_SPI_FLASH_SUPPORT=y
CONFIG_SPL_SPI=y
CONFIG_ARMV7_LPAE=y
@@ -50,8 +49,7 @@
CONFIG_OF_CONTROL=y
CONFIG_SPL_OF_CONTROL=y
CONFIG_OF_LIST="am57xx-beagle-x15 am57xx-beagle-x15-revb1 am57xx-beagle-x15-revc am5729-beagleboneai am572x-idk am571x-idk am574x-idk"
-CONFIG_ENV_OVERWRITE=y
-CONFIG_ENV_IS_IN_MMC=y
+# CONFIG_ENV_IS_IN_FAT is not set
CONFIG_SYS_REDUNDAND_ENVIRONMENT=y
CONFIG_SYS_RELOC_GD_ENV_ADDR=y
CONFIG_SYS_MMC_ENV_DEV=1
diff --git a/configs/am62ax_evm_a53_defconfig b/configs/am62ax_evm_a53_defconfig
index 315d660..d77ff2d 100644
--- a/configs/am62ax_evm_a53_defconfig
+++ b/configs/am62ax_evm_a53_defconfig
@@ -103,3 +103,5 @@
CONFIG_SPL_SYSRESET=y
CONFIG_SYSRESET_TI_SCI=y
CONFIG_FS_FAT_MAX_CLUSTSIZE=16384
+
+#include <configs/am62x_a53_usbdfu.config>
diff --git a/configs/am62ax_evm_r5_defconfig b/configs/am62ax_evm_r5_defconfig
index 3948ba22..cbdc219 100644
--- a/configs/am62ax_evm_r5_defconfig
+++ b/configs/am62ax_evm_r5_defconfig
@@ -81,7 +81,6 @@
CONFIG_SYS_I2C_OMAP24XX=y
CONFIG_DM_MAILBOX=y
CONFIG_K3_SEC_PROXY=y
-CONFIG_SPL_MISC=y
CONFIG_ESM_K3=y
CONFIG_MMC_SDHCI=y
CONFIG_MMC_SDHCI_ADMA=y
diff --git a/configs/am62px_evm_a53_defconfig b/configs/am62px_evm_a53_defconfig
index a17b306..4b5d1ec 100644
--- a/configs/am62px_evm_a53_defconfig
+++ b/configs/am62px_evm_a53_defconfig
@@ -40,14 +40,11 @@
CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR=y
CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x1400
CONFIG_SPL_DMA=y
-CONFIG_SPL_ENV_SUPPORT=y
CONFIG_SPL_FS_LOAD_PAYLOAD_NAME="u-boot.img"
CONFIG_SPL_I2C=y
CONFIG_SPL_DM_MAILBOX=y
CONFIG_SPL_DM_SPI_FLASH=y
CONFIG_SPL_POWER_DOMAIN=y
-CONFIG_SPL_RAM_SUPPORT=y
-CONFIG_SPL_RAM_DEVICE=y
# CONFIG_SPL_SPI_FLASH_TINY is not set
CONFIG_SPL_SPI_FLASH_SFDP_SUPPORT=y
CONFIG_SPL_SPI_LOAD=y
@@ -57,12 +54,12 @@
CONFIG_CMD_BOOTEFI_SELFTEST=y
CONFIG_CMD_NVEDIT_EFI=y
CONFIG_CMD_CLK=y
-CONFIG_CMD_DFU=y
CONFIG_CMD_GPIO=y
CONFIG_CMD_GPT=y
CONFIG_CMD_I2C=y
CONFIG_CMD_MMC=y
CONFIG_CMD_MTD=y
+CONFIG_CMD_REMOTEPROC=y
CONFIG_CMD_USB=y
CONFIG_CMD_USB_MASS_STORAGE=y
CONFIG_CMD_EFIDEBUG=y
@@ -83,17 +80,12 @@
CONFIG_SPL_DM_SEQ_ALIAS=y
CONFIG_REGMAP=y
CONFIG_SPL_REGMAP=y
-CONFIG_SPL_SYSCON=y
CONFIG_SPL_OF_TRANSLATE=y
CONFIG_CLK=y
CONFIG_SPL_CLK=y
CONFIG_CLK_TI_SCI=y
-CONFIG_DFU_MMC=y
CONFIG_DFU_MTD=y
-CONFIG_DFU_RAM=y
CONFIG_DFU_SF=y
-CONFIG_SYS_DFU_DATA_BUF_SIZE=0x40000
-CONFIG_SYS_DFU_MAX_FILE_SIZE=0x800000
CONFIG_DMA_CHANNELS=y
CONFIG_TI_K3_NAVSS_UDMA=y
CONFIG_USB_FUNCTION_FASTBOOT=y
@@ -159,22 +151,10 @@
CONFIG_SPL_SYSRESET=y
CONFIG_SYSRESET_TI_SCI=y
CONFIG_DM_THERMAL=y
-CONFIG_USB=y
-CONFIG_DM_USB_GADGET=y
-CONFIG_SPL_DM_USB_GADGET=y
CONFIG_SPL_USB_HOST=y
-CONFIG_USB_XHCI_HCD=y
-CONFIG_USB_DWC3=y
-CONFIG_USB_DWC3_GENERIC=y
-CONFIG_SPL_USB_DWC3_GENERIC=y
CONFIG_SPL_USB_STORAGE=y
-CONFIG_USB_GADGET=y
-CONFIG_SPL_USB_GADGET=y
-CONFIG_USB_GADGET_MANUFACTURER="Texas Instruments"
-CONFIG_USB_GADGET_VENDOR_NUM=0x0451
-CONFIG_USB_GADGET_PRODUCT_NUM=0x6165
-CONFIG_SPL_DFU=y
CONFIG_FS_FAT_MAX_CLUSTSIZE=16384
CONFIG_EFI_SET_TIME=y
#include <configs/k3_efi_capsule.config>
+#include <configs/am62x_a53_usbdfu.config>
diff --git a/configs/am62px_evm_r5_defconfig b/configs/am62px_evm_r5_defconfig
index 2438d2b..39b6a83 100644
--- a/configs/am62px_evm_r5_defconfig
+++ b/configs/am62px_evm_r5_defconfig
@@ -86,7 +86,6 @@
CONFIG_SYS_I2C_OMAP24XX=y
CONFIG_DM_MAILBOX=y
CONFIG_K3_SEC_PROXY=y
-CONFIG_SPL_MISC=y
CONFIG_ESM_K3=y
CONFIG_MMC_HS400_SUPPORT=y
CONFIG_MMC_SDHCI=y
diff --git a/configs/am62x_a53_usbdfu.config b/configs/am62x_a53_usbdfu.config
index 812f99e..16cd4c8 100644
--- a/configs/am62x_a53_usbdfu.config
+++ b/configs/am62x_a53_usbdfu.config
@@ -6,6 +6,7 @@
CONFIG_SPL_DFU=y
CONFIG_CMD_DFU=y
CONFIG_CMD_USB=y
+CONFIG_CMD_USB_MASS_STORAGE=y
CONFIG_SYSCON=y
CONFIG_SPL_SYSCON=y
CONFIG_DFU_MMC=y
diff --git a/configs/am62x_r5_usbdfu.config b/configs/am62x_r5_usbdfu.config
index 62c9247..5bbb99e 100644
--- a/configs/am62x_r5_usbdfu.config
+++ b/configs/am62x_r5_usbdfu.config
@@ -25,3 +25,6 @@
# CONFIG_CMD_GPT is not set
# CONFIG_CMD_FAT is not set
# CONFIG_MMC is not set
+# CONFIG_SPL_MTD is not set
+# CONFIG_DMA_CHANNELS is not set
+# CONFIG_TI_K3_NAVSS_UDMA is not set
diff --git a/configs/arbel_evb_defconfig b/configs/arbel_evb_defconfig
index 2b0b8b2..f5c05fd 100644
--- a/configs/arbel_evb_defconfig
+++ b/configs/arbel_evb_defconfig
@@ -25,7 +25,6 @@
CONFIG_FIT_VERBOSE=y
CONFIG_USE_BOOTCOMMAND=y
CONFIG_BOOTCOMMAND="run common_bootargs; run romboot"
-CONFIG_LAST_STAGE_INIT=y
CONFIG_HUSH_PARSER=y
CONFIG_SYS_PROMPT="U-Boot>"
CONFIG_SYS_MAXARGS=32
@@ -81,7 +80,6 @@
CONFIG_SPI_FLASH_WINBOND=y
# CONFIG_SPI_FLASH_USE_4K_SECTORS is not set
CONFIG_BITBANGMII=y
-CONFIG_BITBANGMII_MULTI=y
CONFIG_PHY_ADDR_ENABLE=y
CONFIG_PHY_BROADCOM=y
CONFIG_PHY_GIGE=y
diff --git a/configs/bitmain_antminer_s9_defconfig b/configs/bitmain_antminer_s9_defconfig
index afff2d5..edb49de 100644
--- a/configs/bitmain_antminer_s9_defconfig
+++ b/configs/bitmain_antminer_s9_defconfig
@@ -44,10 +44,10 @@
CONFIG_SYS_MAXARGS=32
CONFIG_CMD_BOOTZ=y
# CONFIG_CMD_ELF is not set
+CONFIG_CMD_FPGA_LOADP=y
CONFIG_CMD_FPGA_LOADBP=y
CONFIG_CMD_FPGA_LOADFS=y
CONFIG_CMD_FPGA_LOADMK=y
-CONFIG_CMD_FPGA_LOADP=y
CONFIG_CMD_GPIO=y
CONFIG_CMD_MMC=y
CONFIG_CMD_MTD=y
diff --git a/configs/chromebook_bob_defconfig b/configs/chromebook_bob_defconfig
index 1b018ef..5b8c0d3 100644
--- a/configs/chromebook_bob_defconfig
+++ b/configs/chromebook_bob_defconfig
@@ -35,6 +35,7 @@
CONFIG_SYS_SPI_U_BOOT_OFFS=0xE0000
CONFIG_SPL_ATF_NO_PLATFORM_PARAM=y
CONFIG_TPL=y
+CONFIG_TPL_GPIO=y
CONFIG_CMD_BOOTZ=y
CONFIG_CMD_GPIO=y
CONFIG_CMD_GPT=y
diff --git a/configs/chromebook_kevin_defconfig b/configs/chromebook_kevin_defconfig
index 1ee0c0e..a29a04a 100644
--- a/configs/chromebook_kevin_defconfig
+++ b/configs/chromebook_kevin_defconfig
@@ -36,6 +36,7 @@
CONFIG_SYS_SPI_U_BOOT_OFFS=0xE0000
CONFIG_SPL_ATF_NO_PLATFORM_PARAM=y
CONFIG_TPL=y
+CONFIG_TPL_GPIO=y
CONFIG_CMD_BOOTZ=y
CONFIG_CMD_GPIO=y
CONFIG_CMD_GPT=y
diff --git a/configs/dh_imx6.config b/configs/dh_imx6.config
new file mode 100644
index 0000000..01db41b
--- /dev/null
+++ b/configs/dh_imx6.config
@@ -0,0 +1,76 @@
+#include <configs/imx_dhsom.config>
+
+CONFIG_ARM=y
+CONFIG_ARCH_MX6=y
+CONFIG_MX6QDL=y
+CONFIG_TARGET_DHCOMIMX6=y
+CONFIG_SPL_SYS_L2_PL310=y
+CONFIG_MX6_DDRCAL=y
+CONFIG_NR_DRAM_BANKS=1
+CONFIG_OF_LIBFDT_OVERLAY=y
+CONFIG_OF_UPSTREAM=y
+CONFIG_FIT_VERBOSE=y
+CONFIG_MULTI_DTB_FIT=y
+CONFIG_LTO=y
+
+CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE=y
+CONFIG_SYS_I2C_MXC=y
+CONFIG_SYS_MALLOC_F_LEN=0x1000
+CONFIG_SYS_MAXARGS=32
+CONFIG_SYS_MEMTEST_END=0x20000000
+CONFIG_SYS_MEMTEST_START=0x10000000
+CONFIG_SYS_MONITOR_LEN=409600
+CONFIG_SYS_PBSIZE=532
+
+CONFIG_SYS_BOOTCOUNT_ADDR=0x020CC068
+CONFIG_SYS_BOOTCOUNT_BE=y
+CONFIG_BOOTCOUNT_LIMIT=y
+CONFIG_BOOTDELAY=3
+
+CONFIG_BZIP2=y
+CONFIG_CMD_SATA=y
+CONFIG_CMD_UNZIP=y
+CONFIG_CMD_WDT=y
+CONFIG_DISTRO_DEFAULTS=y
+
+CONFIG_ENV_OFFSET=0x100000
+CONFIG_ENV_OFFSET_REDUND=0x110000
+CONFIG_ENV_SECT_SIZE=0x10000
+CONFIG_ENV_SIZE=0x4000
+
+# CONFIG_CMD_SCSI is not set
+CONFIG_AHCI=y
+CONFIG_BOUNCE_BUFFER=y
+CONFIG_DWC_AHSATA=y
+CONFIG_LBA48=y
+CONFIG_SCSI=y
+
+CONFIG_ARP_TIMEOUT=200
+CONFIG_ETHPRIME="FEC"
+CONFIG_USE_ETHPRIME=y
+CONFIG_PHYLIB=y
+
+CONFIG_SF_DEFAULT_SPEED=25000000
+CONFIG_SPI_FLASH_GIGADEVICE=y
+CONFIG_SPI_FLASH_MACRONIX=y
+CONFIG_SPI_FLASH_SPANSION=y
+CONFIG_SPI_FLASH_UNLOCK_ALL=y
+
+CONFIG_MISC=y
+
+CONFIG_PINCTRL_IMX6=y
+
+CONFIG_SDP_LOADADDR=0x17ffffc0
+CONFIG_SPL_FIT=y
+CONFIG_SPL_SPI=y
+CONFIG_SPL_SPI_FLASH_SUPPORT=y
+CONFIG_SPL_SPI_LOAD=y
+CONFIG_SPL_USB_GADGET=y
+CONFIG_SPL_USB_HOST=y
+CONFIG_SPL_USB_SDP_SUPPORT=y
+CONFIG_SYS_DFU_DATA_BUF_SIZE=0x1000000
+CONFIG_SYS_SPI_U_BOOT_OFFS=0x11400
+CONFIG_CI_UDC=y
+CONFIG_USB_GADGET_DOWNLOAD=y
+
+CONFIG_WATCHDOG_TIMEOUT_MSECS=60000
diff --git a/configs/dh_imx6_defconfig b/configs/dh_imx6_defconfig
index 43ac5a5..552d743 100644
--- a/configs/dh_imx6_defconfig
+++ b/configs/dh_imx6_defconfig
@@ -1,78 +1,4 @@
-#include <configs/imx_dhsom.config>
+#include <configs/dh_imx6.config>
-CONFIG_ARM=y
-CONFIG_ARCH_MX6=y
-CONFIG_MX6QDL=y
-CONFIG_TARGET_DHCOMIMX6=y
-CONFIG_SPL_SYS_L2_PL310=y
CONFIG_DEFAULT_DEVICE_TREE="nxp/imx/imx6q-dhcom-pdk2"
-CONFIG_MX6_DDRCAL=y
-CONFIG_NR_DRAM_BANKS=1
-CONFIG_OF_LIBFDT_OVERLAY=y
CONFIG_OF_LIST="nxp/imx/imx6q-dhcom-pdk2 nxp/imx/imx6dl-dhcom-pdk2 nxp/imx/imx6s-dhcom-drc02 nxp/imx/imx6dl-dhcom-picoitx"
-CONFIG_OF_UPSTREAM=y
-CONFIG_FIT_VERBOSE=y
-CONFIG_MULTI_DTB_FIT=y
-CONFIG_LTO=y
-
-CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE=y
-CONFIG_SYS_I2C_MXC=y
-CONFIG_SYS_MALLOC_F_LEN=0x1000
-CONFIG_SYS_MAXARGS=32
-CONFIG_SYS_MEMTEST_END=0x20000000
-CONFIG_SYS_MEMTEST_START=0x10000000
-CONFIG_SYS_MONITOR_LEN=409600
-CONFIG_SYS_PBSIZE=532
-
-CONFIG_SYS_BOOTCOUNT_ADDR=0x020CC068
-CONFIG_SYS_BOOTCOUNT_BE=y
-CONFIG_BOOTCOUNT_LIMIT=y
-CONFIG_BOOTDELAY=3
-
-CONFIG_BZIP2=y
-CONFIG_CMD_SATA=y
-CONFIG_CMD_UNZIP=y
-CONFIG_CMD_WDT=y
-CONFIG_DISTRO_DEFAULTS=y
-
-CONFIG_ENV_OFFSET=0x100000
-CONFIG_ENV_OFFSET_REDUND=0x110000
-CONFIG_ENV_SECT_SIZE=0x10000
-CONFIG_ENV_SIZE=0x4000
-
-# CONFIG_CMD_SCSI is not set
-CONFIG_AHCI=y
-CONFIG_BOUNCE_BUFFER=y
-CONFIG_DWC_AHSATA=y
-CONFIG_LBA48=y
-CONFIG_SCSI=y
-
-CONFIG_ARP_TIMEOUT=200
-CONFIG_ETHPRIME="FEC"
-CONFIG_USE_ETHPRIME=y
-CONFIG_PHYLIB=y
-
-CONFIG_SF_DEFAULT_SPEED=25000000
-CONFIG_SPI_FLASH_GIGADEVICE=y
-CONFIG_SPI_FLASH_MACRONIX=y
-CONFIG_SPI_FLASH_SPANSION=y
-CONFIG_SPI_FLASH_UNLOCK_ALL=y
-
-CONFIG_MISC=y
-
-CONFIG_PINCTRL_IMX6=y
-
-CONFIG_SDP_LOADADDR=0x17ffffc0
-CONFIG_SPL_FIT=y
-CONFIG_SPL_SPI=y
-CONFIG_SPL_SPI_FLASH_SUPPORT=y
-CONFIG_SPL_SPI_LOAD=y
-CONFIG_SPL_USB_GADGET=y
-CONFIG_SPL_USB_HOST=y
-CONFIG_SPL_USB_SDP_SUPPORT=y
-CONFIG_SYS_DFU_DATA_BUF_SIZE=0x1000000
-CONFIG_SYS_SPI_U_BOOT_OFFS=0x11400
-CONFIG_CI_UDC=y
-CONFIG_USB_GADGET_DOWNLOAD=y
-
-CONFIG_WATCHDOG_TIMEOUT_MSECS=60000
diff --git a/configs/evb-rk3036_defconfig b/configs/evb-rk3036_defconfig
index ba79960..d215af0 100644
--- a/configs/evb-rk3036_defconfig
+++ b/configs/evb-rk3036_defconfig
@@ -11,7 +11,7 @@
CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y
CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x60100000
CONFIG_SF_DEFAULT_SPEED=20000000
-CONFIG_DEFAULT_DEVICE_TREE="rk3036-sdk"
+CONFIG_DEFAULT_DEVICE_TREE="rockchip/rk3036-evb"
CONFIG_ROCKCHIP_RK3036=y
CONFIG_SPL_STACK_R_ADDR=0x80000
CONFIG_SPL_STACK=0x10081fff
@@ -23,7 +23,7 @@
CONFIG_DEBUG_UART=y
# CONFIG_ANDROID_BOOT_IMAGE is not set
CONFIG_USE_PREBOOT=y
-CONFIG_DEFAULT_FDT_FILE="rk3036-evb.dtb"
+CONFIG_DEFAULT_FDT_FILE="rockchip/rk3036-evb.dtb"
# CONFIG_DISPLAY_CPUINFO is not set
CONFIG_DISPLAY_BOARDINFO_LATE=y
# CONFIG_SPL_FRAMEWORK is not set
diff --git a/configs/ibex-ast2700_defconfig b/configs/ibex-ast2700_defconfig
index e4b9a9a..6cb2a21 100644
--- a/configs/ibex-ast2700_defconfig
+++ b/configs/ibex-ast2700_defconfig
@@ -27,7 +27,6 @@
# CONFIG_SPL_SMP is not set
CONFIG_XIP=y
CONFIG_SPL_XIP=y
-# CONFIG_AVAILABLE_HARTS is not set
CONFIG_STACK_SIZE_SHIFT=11
CONFIG_ENV_VARS_UBOOT_CONFIG=y
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
diff --git a/configs/imx6_dhcom_drc02_defconfig b/configs/imx6_dhcom_drc02_defconfig
new file mode 100644
index 0000000..72a0498
--- /dev/null
+++ b/configs/imx6_dhcom_drc02_defconfig
@@ -0,0 +1,4 @@
+#include <configs/dh_imx6.config>
+
+CONFIG_DEFAULT_DEVICE_TREE="nxp/imx/imx6s-dhcom-drc02"
+CONFIG_OF_LIST="nxp/imx/imx6s-dhcom-drc02"
diff --git a/configs/imx6_dhcom_pdk2_defconfig b/configs/imx6_dhcom_pdk2_defconfig
new file mode 100644
index 0000000..6cc81f6
--- /dev/null
+++ b/configs/imx6_dhcom_pdk2_defconfig
@@ -0,0 +1,4 @@
+#include <configs/dh_imx6.config>
+
+CONFIG_DEFAULT_DEVICE_TREE="nxp/imx/imx6q-dhcom-pdk2"
+CONFIG_OF_LIST="nxp/imx/imx6q-dhcom-pdk2 nxp/imx/imx6dl-dhcom-pdk2"
diff --git a/configs/imx6_dhcom_picoitx_defconfig b/configs/imx6_dhcom_picoitx_defconfig
new file mode 100644
index 0000000..837aab6
--- /dev/null
+++ b/configs/imx6_dhcom_picoitx_defconfig
@@ -0,0 +1,4 @@
+#include <configs/dh_imx6.config>
+
+CONFIG_DEFAULT_DEVICE_TREE="nxp/imx/imx6dl-dhcom-picoitx"
+CONFIG_OF_LIST="nxp/imx/imx6dl-dhcom-picoitx"
diff --git a/configs/imx8m_data_modul.config b/configs/imx8m_data_modul.config
index 2164c75..37e11e5 100644
--- a/configs/imx8m_data_modul.config
+++ b/configs/imx8m_data_modul.config
@@ -13,6 +13,7 @@
CONFIG_ARM=y
CONFIG_BOARD_LATE_INIT=y
CONFIG_BOOTCOMMAND="run dmo_update_env ; load ${devtype} ${devnum}:${devpart} ${loadaddr} boot/fitImage && source ${loadaddr}:bootscr-boot.cmd ; reset"
+CONFIG_BOOTCOUNT_ALTBOOTCMD="run bootcmd"
CONFIG_BOOTCOUNT_BOOTLIMIT=3
CONFIG_BOOTCOUNT_LIMIT=y
CONFIG_CLK_COMPOSITE_CCF=y
diff --git a/configs/imx8mm_data_modul_edm_sbc_defconfig b/configs/imx8mm_data_modul_edm_sbc_defconfig
index debaa7c..66cb133 100644
--- a/configs/imx8mm_data_modul_edm_sbc_defconfig
+++ b/configs/imx8mm_data_modul_edm_sbc_defconfig
@@ -37,4 +37,3 @@
CONFIG_SPL_USB_HOST=y
CONFIG_SPL_USB_SDP_SUPPORT=y
CONFIG_SYS_LOAD_ADDR=0x60000000
-CONFIG_BOOTCOUNT_ALTBOOTCMD=run bootcmd
diff --git a/configs/imx8mp_data_modul_edm_sbc_defconfig b/configs/imx8mp_data_modul_edm_sbc_defconfig
index 5024c09..ea8109b 100644
--- a/configs/imx8mp_data_modul_edm_sbc_defconfig
+++ b/configs/imx8mp_data_modul_edm_sbc_defconfig
@@ -52,4 +52,3 @@
CONFIG_USB_XHCI_DWC3=y
CONFIG_USB_XHCI_DWC3_OF_SIMPLE=y
CONFIG_USB_XHCI_HCD=y
-CONFIG_BOOTCOUNT_ALTBOOTCMD="run bootcmd"
diff --git a/configs/imx8mp_dhcom_drc02_defconfig b/configs/imx8mp_dhcom_drc02_defconfig
index dccf5ff..c43839c 100644
--- a/configs/imx8mp_dhcom_drc02_defconfig
+++ b/configs/imx8mp_dhcom_drc02_defconfig
@@ -5,4 +5,3 @@
CONFIG_DEFAULT_DEVICE_TREE="imx8mp-dhcom-drc02"
CONFIG_DEFAULT_FDT_FILE="imx8mp-dhcom-drc02.dtb"
CONFIG_PREBOOT=""
-CONFIG_BOOTCOUNT_ALTBOOTCMD="run bootcmd ; reset"
diff --git a/configs/imx8mp_dhcom_pdk2_defconfig b/configs/imx8mp_dhcom_pdk2_defconfig
index 4f50806..aae2e21 100644
--- a/configs/imx8mp_dhcom_pdk2_defconfig
+++ b/configs/imx8mp_dhcom_pdk2_defconfig
@@ -7,4 +7,3 @@
CONFIG_PREBOOT=""
CONFIG_OF_UPSTREAM=y
CONFIG_OF_UPSTREAM_INCLUDE_LOCAL_FALLBACK_DTBOS=y
-CONFIG_BOOTCOUNT_ALTBOOTCMD="run bootcmd ; reset"
diff --git a/configs/imx8mp_dhcom_pdk3_defconfig b/configs/imx8mp_dhcom_pdk3_defconfig
index d505ddf..f40bf26 100644
--- a/configs/imx8mp_dhcom_pdk3_defconfig
+++ b/configs/imx8mp_dhcom_pdk3_defconfig
@@ -14,4 +14,3 @@
CONFIG_PHY_IMX8M_PCIE=y
CONFIG_I2C_MUX=y
CONFIG_I2C_MUX_PCA954x=y
-CONFIG_BOOTCOUNT_ALTBOOTCMD="run bootcmd ; reset"
diff --git a/configs/imx8mp_dhcom_picoitx_defconfig b/configs/imx8mp_dhcom_picoitx_defconfig
index d98ca9e..99cd5f2 100644
--- a/configs/imx8mp_dhcom_picoitx_defconfig
+++ b/configs/imx8mp_dhcom_picoitx_defconfig
@@ -5,4 +5,3 @@
CONFIG_DEFAULT_DEVICE_TREE="imx8mp-dhcom-picoitx"
CONFIG_DEFAULT_FDT_FILE="imx8mp-dhcom-picoitx.dtb"
CONFIG_PREBOOT=""
-CONFIG_BOOTCOUNT_ALTBOOTCMD="run bootcmd ; reset"
diff --git a/configs/imx8mp_dhsom.config b/configs/imx8mp_dhsom.config
index 4161431..7adbb9a 100644
--- a/configs/imx8mp_dhsom.config
+++ b/configs/imx8mp_dhsom.config
@@ -70,6 +70,7 @@
CONFIG_SF_DEFAULT_SPEED=50000000
# CONFIG_SPI_FLASH_UNLOCK_ALL is not set
+CONFIG_BOOTCOUNT_ALTBOOTCMD="run bootcmd ; reset"
CONFIG_BOOTCOUNT_LIMIT=y
CONFIG_SYS_BOOTCOUNT_MAGIC=0xB0C40000
diff --git a/configs/imxrt1050-evk_defconfig b/configs/imxrt1050-evk_defconfig
index b488ff1..918713a 100644
--- a/configs/imxrt1050-evk_defconfig
+++ b/configs/imxrt1050-evk_defconfig
@@ -13,7 +13,7 @@
CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x20020000
CONFIG_ENV_OFFSET=0x80000
CONFIG_DM_GPIO=y
-CONFIG_DEFAULT_DEVICE_TREE="imxrt1050-evk"
+CONFIG_DEFAULT_DEVICE_TREE="nxp/imx/imxrt1050-evk"
CONFIG_TARGET_IMXRT1050_EVK=y
CONFIG_SPL_MMC=y
CONFIG_SPL_SERIAL=y
@@ -48,6 +48,7 @@
# CONFIG_EFI_PARTITION is not set
CONFIG_OF_CONTROL=y
CONFIG_SPL_OF_CONTROL=y
+CONFIG_OF_UPSTREAM=y
CONFIG_ENV_IS_NOWHERE=y
CONFIG_ENV_IS_IN_MMC=y
CONFIG_SYS_RELOC_GD_ENV_ADDR=y
diff --git a/configs/imxrt1050-evk_fspi_defconfig b/configs/imxrt1050-evk_fspi_defconfig
index 5d58e72..86acd15 100644
--- a/configs/imxrt1050-evk_fspi_defconfig
+++ b/configs/imxrt1050-evk_fspi_defconfig
@@ -15,7 +15,7 @@
CONFIG_ENV_OFFSET=0x80000
CONFIG_IMX_CONFIG="board/freescale/imxrt1050-evk/imximage-nor.cfg"
CONFIG_DM_GPIO=y
-CONFIG_DEFAULT_DEVICE_TREE="imxrt1050-evk"
+CONFIG_DEFAULT_DEVICE_TREE="nxp/imx/imxrt1050-evk"
CONFIG_TARGET_IMXRT1050_EVK=y
CONFIG_SPL_MMC=y
CONFIG_SPL_SERIAL=y
@@ -50,6 +50,7 @@
# CONFIG_EFI_PARTITION is not set
CONFIG_OF_CONTROL=y
CONFIG_SPL_OF_CONTROL=y
+CONFIG_OF_UPSTREAM=y
CONFIG_ENV_IS_NOWHERE=y
CONFIG_ENV_IS_IN_MMC=y
CONFIG_SYS_RELOC_GD_ENV_ADDR=y
diff --git a/configs/j722s_evm_a53_defconfig b/configs/j722s_evm_a53_defconfig
index 2062eca..5d2bb52 100644
--- a/configs/j722s_evm_a53_defconfig
+++ b/configs/j722s_evm_a53_defconfig
@@ -150,6 +150,8 @@
CONFIG_USB_DWC3=y
CONFIG_USB_DWC3_GENERIC=y
CONFIG_SPL_USB_DWC3_GENERIC=y
+CONFIG_SPL_USB_DWC3_AM62=y
+CONFIG_USB_DWC3_AM62=y
CONFIG_SPL_USB_STORAGE=y
CONFIG_USB_GADGET=y
CONFIG_SPL_USB_GADGET=y
diff --git a/configs/j722s_evm_r5_defconfig b/configs/j722s_evm_r5_defconfig
index d51b21d..d96392d 100644
--- a/configs/j722s_evm_r5_defconfig
+++ b/configs/j722s_evm_r5_defconfig
@@ -124,4 +124,7 @@
CONFIG_SPL_TIMER=y
CONFIG_OMAP_TIMER=y
CONFIG_LIB_RATIONAL=y
+CONFIG_ESM_K3=y
+CONFIG_SPL_DRIVERS_MISC=y
+CONFIG_SPL_MISC=y
CONFIG_SPL_LIB_RATIONAL=y
diff --git a/configs/j784s4_evm_a72_defconfig b/configs/j784s4_evm_a72_defconfig
index 1ac2430..1ba2bfe 100644
--- a/configs/j784s4_evm_a72_defconfig
+++ b/configs/j784s4_evm_a72_defconfig
@@ -2,6 +2,7 @@
CONFIG_ARCH_K3=y
CONFIG_SYS_MALLOC_LEN=0x2000000
CONFIG_SYS_MALLOC_F_LEN=0x8000
+CONFIG_TI_COMMON_CMD_OPTIONS=y
CONFIG_SPL_GPIO=y
CONFIG_SPL_LIBCOMMON_SUPPORT=y
CONFIG_SPL_LIBGENERIC_SUPPORT=y
@@ -14,13 +15,13 @@
CONFIG_DM_GPIO=y
CONFIG_SPL_DM_SPI=y
CONFIG_DEFAULT_DEVICE_TREE="ti/k3-j784s4-evm"
-CONFIG_SPL_TEXT_BASE=0x80080000
CONFIG_OF_LIBFDT_OVERLAY=y
CONFIG_DM_RESET=y
CONFIG_SPL_MMC=y
CONFIG_SPL_SERIAL=y
CONFIG_SPL_DRIVERS_MISC=y
CONFIG_SPL_STACK_R_ADDR=0x82000000
+CONFIG_SPL_TEXT_BASE=0x80080000
CONFIG_SPL_HAS_BSS_LINKER_SECTION=y
CONFIG_SPL_BSS_START_ADDR=0x80a00000
CONFIG_SPL_BSS_MAX_SIZE=0x80000
@@ -29,6 +30,7 @@
CONFIG_SPL_LIBDISK_SUPPORT=y
CONFIG_SPL_SPI_FLASH_SUPPORT=y
CONFIG_SPL_SPI=y
+CONFIG_EFI_SET_TIME=y
CONFIG_SPL_LOAD_FIT=y
CONFIG_SPL_LOAD_FIT_ADDRESS=0x81000000
CONFIG_BOOTSTD_FULL=y
@@ -38,10 +40,8 @@
CONFIG_SPL_BOARD_INIT=y
CONFIG_SPL_SYS_MALLOC_SIMPLE=y
CONFIG_SPL_SYS_MMCSD_RAW_MODE=y
-CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR=y
CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x1400
CONFIG_SPL_DMA=y
-CONFIG_SPL_DM_DEVICE_REMOVE=y
CONFIG_SPL_ENV_SUPPORT=y
CONFIG_SPL_FS_LOAD_PAYLOAD_NAME="u-boot.img"
CONFIG_SPL_I2C=y
@@ -49,7 +49,6 @@
CONFIG_SPL_DM_SPI_FLASH=y
CONFIG_SPL_DM_RESET=y
CONFIG_SPL_POWER_DOMAIN=y
-CONFIG_SPL_RAM_SUPPORT=y
CONFIG_SPL_RAM_DEVICE=y
# CONFIG_SPL_SPI_FLASH_TINY is not set
CONFIG_SPL_SPI_FLASH_SFDP_SUPPORT=y
@@ -58,10 +57,9 @@
CONFIG_SPL_THERMAL=y
CONFIG_SPL_YMODEM_SUPPORT=y
CONFIG_CMD_BOOTEFI_SELFTEST=y
-CONFIG_CMD_ASKENV=y
CONFIG_CMD_NVEDIT_EFI=y
CONFIG_CMD_MTD=y
-CONFIG_CMD_USB=y
+CONFIG_CMD_USB_MASS_STORAGE=y
CONFIG_CMD_EFIDEBUG=y
CONFIG_OF_CONTROL=y
CONFIG_SPL_OF_CONTROL=y
@@ -72,6 +70,7 @@
CONFIG_SYS_RELOC_GD_ENV_ADDR=y
CONFIG_NET_RANDOM_ETHADDR=y
CONFIG_SPL_DM=y
+CONFIG_SPL_DM_DEVICE_REMOVE=y
CONFIG_SPL_DM_SEQ_ALIAS=y
CONFIG_REGMAP=y
CONFIG_SPL_REGMAP=y
@@ -81,6 +80,8 @@
CONFIG_SPL_CLK=y
CONFIG_CLK_CCF=y
CONFIG_CLK_TI_SCI=y
+CONFIG_DFU_MMC=y
+CONFIG_DFU_RAM=y
CONFIG_DFU_SF=y
CONFIG_SYS_DFU_DATA_BUF_SIZE=0x40000
CONFIG_SYS_DFU_MAX_FILE_SIZE=0x800000
@@ -154,7 +155,20 @@
CONFIG_SPL_SYSRESET=y
CONFIG_SYSRESET_TI_SCI=y
CONFIG_DM_THERMAL=y
-CONFIG_EFI_SET_TIME=y
-CONFIG_TI_COMMON_CMD_OPTIONS=y
+CONFIG_USB=y
+CONFIG_DM_USB_GADGET=y
+CONFIG_SPL_DM_USB_GADGET=y
+CONFIG_USB_XHCI_HCD=y
+CONFIG_USB_CDNS3=y
+CONFIG_USB_CDNS3_GADGET=y
+CONFIG_USB_CDNS3_HOST=y
+CONFIG_SPL_USB_CDNS3_GADGET=y
+CONFIG_USB_GADGET=y
+CONFIG_SPL_USB_GADGET=y
+CONFIG_USB_GADGET_MANUFACTURER="Texas Instruments"
+CONFIG_USB_GADGET_VENDOR_NUM=0x0451
+CONFIG_USB_GADGET_PRODUCT_NUM=0x6168
+CONFIG_USB_GADGET_DOWNLOAD=y
+CONFIG_SPL_DFU=y
#include <configs/k3_efi_capsule.config>
diff --git a/configs/j784s4_evm_r5_defconfig b/configs/j784s4_evm_r5_defconfig
index a307055..5a5b045 100644
--- a/configs/j784s4_evm_r5_defconfig
+++ b/configs/j784s4_evm_r5_defconfig
@@ -62,6 +62,7 @@
CONFIG_SPL_THERMAL=y
CONFIG_SPL_YMODEM_SUPPORT=y
CONFIG_HUSH_PARSER=y
+CONFIG_CMD_DFU=y
CONFIG_CMD_GPT=y
CONFIG_CMD_MMC=y
CONFIG_CMD_TIME=y
@@ -84,6 +85,7 @@
CONFIG_SPL_CLK_CCF=y
CONFIG_SPL_CLK_K3_PLL=y
CONFIG_SPL_CLK_K3=y
+CONFIG_SYS_DFU_DATA_BUF_SIZE=0x40000
CONFIG_DMA_CHANNELS=y
CONFIG_TI_K3_NAVSS_UDMA=y
CONFIG_TI_SCI_PROTOCOL=y
@@ -142,6 +144,19 @@
CONFIG_TIMER=y
CONFIG_SPL_TIMER=y
CONFIG_OMAP_TIMER=y
+CONFIG_USB=y
+CONFIG_DM_USB_GADGET=y
+CONFIG_SPL_DM_USB_GADGET=y
+CONFIG_USB_CDNS3=y
+CONFIG_USB_CDNS3_GADGET=y
+CONFIG_SPL_USB_CDNS3_GADGET=y
+CONFIG_USB_GADGET=y
+CONFIG_SPL_USB_GADGET=y
+CONFIG_USB_GADGET_MANUFACTURER="Texas Instruments"
+CONFIG_USB_GADGET_VENDOR_NUM=0x0451
+CONFIG_USB_GADGET_PRODUCT_NUM=0x6168
+CONFIG_USB_GADGET_DOWNLOAD=y
+CONFIG_SPL_DFU=y
CONFIG_FS_EXT4=y
CONFIG_FS_FAT_MAX_CLUSTSIZE=16384
CONFIG_PANIC_HANG=y
diff --git a/configs/kylin-rk3036_defconfig b/configs/kylin-rk3036_defconfig
index dd25fd6..bc60bc5 100644
--- a/configs/kylin-rk3036_defconfig
+++ b/configs/kylin-rk3036_defconfig
@@ -12,7 +12,7 @@
CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x60100000
CONFIG_SF_DEFAULT_SPEED=20000000
CONFIG_ENV_OFFSET=0x3F8000
-CONFIG_DEFAULT_DEVICE_TREE="rk3036-sdk"
+CONFIG_DEFAULT_DEVICE_TREE="rockchip/rk3036-kylin"
CONFIG_ROCKCHIP_RK3036=y
CONFIG_TARGET_KYLIN_RK3036=y
CONFIG_SPL_STACK_R_ADDR=0x80000
@@ -25,7 +25,7 @@
CONFIG_DEBUG_UART=y
# CONFIG_ANDROID_BOOT_IMAGE is not set
CONFIG_USE_PREBOOT=y
-CONFIG_DEFAULT_FDT_FILE="rk3036-kylin.dtb"
+CONFIG_DEFAULT_FDT_FILE="rockchip/rk3036-kylin.dtb"
# CONFIG_DISPLAY_CPUINFO is not set
CONFIG_DISPLAY_BOARDINFO_LATE=y
# CONFIG_SPL_FRAMEWORK is not set
diff --git a/configs/lxr2_defconfig b/configs/lxr2_defconfig
index b41a6ed..0bc4ae0 100644
--- a/configs/lxr2_defconfig
+++ b/configs/lxr2_defconfig
@@ -13,7 +13,7 @@
CONFIG_MX6Q=y
CONFIG_TARGET_LXR2=y
CONFIG_DM_GPIO=y
-CONFIG_DEFAULT_DEVICE_TREE="imx6q-lxr"
+CONFIG_DEFAULT_DEVICE_TREE="nxp/imx/imx6q-lxr"
CONFIG_SYS_MONITOR_LEN=409600
CONFIG_SPL_MMC=y
CONFIG_SPL_SERIAL=y
diff --git a/configs/microchip_mpfs_icicle_defconfig b/configs/microchip_mpfs_icicle_defconfig
index 5ea6cc3..f8acaa9 100644
--- a/configs/microchip_mpfs_icicle_defconfig
+++ b/configs/microchip_mpfs_icicle_defconfig
@@ -12,6 +12,7 @@
CONFIG_RISCV_SMODE=y
CONFIG_FIT=y
CONFIG_DISTRO_DEFAULTS=y
+CONFIG_DEFAULT_FDT_FILE="microchip/mpfs-icicle-kit.dtb"
CONFIG_SYS_CBSIZE=256
CONFIG_SYS_PBSIZE=282
CONFIG_DISPLAY_CPUINFO=y
diff --git a/configs/mt7987_rfb_defconfig b/configs/mt7987_rfb_defconfig
index 00e3cea..c6a88e7 100644
--- a/configs/mt7987_rfb_defconfig
+++ b/configs/mt7987_rfb_defconfig
@@ -12,7 +12,6 @@
CONFIG_DEBUG_UART_BASE=0x11000000
CONFIG_DEBUG_UART_CLOCK=40000000
CONFIG_DEBUG_UART=y
-# CONFIG_EFI_LOADER is not set
CONFIG_FIT=y
# CONFIG_AUTOBOOT is not set
CONFIG_DEFAULT_FDT_FILE="mt7987a-rfb"
diff --git a/configs/phycore_am62x_a53_defconfig b/configs/phycore_am62x_a53_defconfig
index 0494fc4..d7aa59b 100644
--- a/configs/phycore_am62x_a53_defconfig
+++ b/configs/phycore_am62x_a53_defconfig
@@ -13,6 +13,7 @@
CONFIG_SF_DEFAULT_SPEED=25000000
CONFIG_ENV_SIZE=0x20000
CONFIG_ENV_OFFSET=0x680000
+CONFIG_ENV_SECT_SIZE=0x20000
CONFIG_SPL_DM_SPI=y
CONFIG_DEFAULT_DEVICE_TREE="ti/k3-am625-phyboard-lyra-rdk"
CONFIG_OF_LIBFDT_OVERLAY=y
@@ -84,6 +85,7 @@
CONFIG_ENV_OVERWRITE=y
CONFIG_ENV_IS_NOWHERE=y
CONFIG_ENV_IS_IN_MMC=y
+CONFIG_ENV_IS_IN_SPI_FLASH=y
CONFIG_SYS_REDUNDAND_ENVIRONMENT=y
CONFIG_SYS_MMC_ENV_DEV=1
CONFIG_NET_RANDOM_ETHADDR=y
diff --git a/configs/phycore_am64x_a53_defconfig b/configs/phycore_am64x_a53_defconfig
index f0c7ee2..4ee1bd8 100644
--- a/configs/phycore_am64x_a53_defconfig
+++ b/configs/phycore_am64x_a53_defconfig
@@ -14,6 +14,7 @@
CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x80480000
CONFIG_ENV_SIZE=0x20000
CONFIG_ENV_OFFSET=0x680000
+CONFIG_ENV_SECT_SIZE=0x20000
CONFIG_DM_GPIO=y
CONFIG_SPL_DM_SPI=y
CONFIG_DEFAULT_DEVICE_TREE="ti/k3-am642-phyboard-electra-rdk"
@@ -91,6 +92,7 @@
CONFIG_ENV_OVERWRITE=y
CONFIG_ENV_IS_NOWHERE=y
CONFIG_ENV_IS_IN_MMC=y
+CONFIG_ENV_IS_IN_SPI_FLASH=y
CONFIG_SYS_REDUNDAND_ENVIRONMENT=y
CONFIG_SYS_MMC_ENV_DEV=1
CONFIG_NET_RANDOM_ETHADDR=y
diff --git a/configs/picasso_defconfig b/configs/picasso_defconfig
new file mode 100644
index 0000000..994951b
--- /dev/null
+++ b/configs/picasso_defconfig
@@ -0,0 +1,83 @@
+CONFIG_ARM=y
+CONFIG_ARCH_TEGRA=y
+CONFIG_SUPPORT_PASSING_ATAGS=y
+CONFIG_CMDLINE_TAG=y
+CONFIG_INITRD_TAG=y
+CONFIG_TEXT_BASE=0x00110000
+CONFIG_NR_DRAM_BANKS=2
+CONFIG_ENV_SOURCE_FILE="picasso"
+CONFIG_ENV_SIZE=0x3000
+CONFIG_ENV_OFFSET=0xFFFFD000
+CONFIG_DEFAULT_DEVICE_TREE="tegra20-acer-a500-picasso"
+CONFIG_SPL_STACK=0xffffc
+CONFIG_SPL_TEXT_BASE=0x00108000
+CONFIG_SYS_LOAD_ADDR=0x2000000
+CONFIG_TEGRA20=y
+CONFIG_TARGET_PICASSO=y
+CONFIG_TEGRA_ENABLE_UARTD=y
+CONFIG_CMD_EBTUPDATE=y
+CONFIG_BUTTON_CMD=y
+CONFIG_BOOTDELAY=0
+CONFIG_AUTOBOOT_KEYED=y
+CONFIG_AUTOBOOT_KEYED_CTRLC=y
+CONFIG_OF_SYSTEM_SETUP=y
+CONFIG_BOOTCOMMAND="bootflow scan; poweroff"
+CONFIG_SYS_PBSIZE=2085
+CONFIG_SPL_FOOTPRINT_LIMIT=y
+CONFIG_SPL_MAX_FOOTPRINT=0x8000
+# CONFIG_SPL_SHARES_INIT_SP_ADDR is not set
+CONFIG_SPL_SYS_MALLOC=y
+CONFIG_SPL_HAS_CUSTOM_MALLOC_START=y
+CONFIG_SPL_CUSTOM_SYS_MALLOC_ADDR=0x90000
+CONFIG_SPL_SYS_MALLOC_SIZE=0x10000
+CONFIG_SYS_PROMPT="Tegra20 (Picasso) # "
+# CONFIG_CMD_BOOTEFI_BOOTMGR is not set
+CONFIG_CMD_BOOTMENU=y
+# CONFIG_CMD_IMI is not set
+CONFIG_CMD_GPIO=y
+CONFIG_CMD_GPT=y
+CONFIG_CMD_GPT_RENAME=y
+CONFIG_CMD_I2C=y
+CONFIG_CMD_MMC=y
+CONFIG_CMD_POWEROFF=y
+CONFIG_CMD_USB=y
+CONFIG_CMD_USB_MASS_STORAGE=y
+CONFIG_CMD_UMS_ABORT_KEYED=y
+# CONFIG_CMD_SETEXPR is not set
+CONFIG_CMD_PAUSE=y
+CONFIG_CMD_EXT4_WRITE=y
+# CONFIG_SPL_DOS_PARTITION is not set
+# CONFIG_SPL_EFI_PARTITION is not set
+CONFIG_ENV_OVERWRITE=y
+CONFIG_ENV_IS_IN_MMC=y
+CONFIG_SYS_RELOC_GD_ENV_ADDR=y
+CONFIG_SYS_MMC_ENV_PART=2
+CONFIG_BUTTON=y
+CONFIG_USB_FUNCTION_FASTBOOT=y
+CONFIG_FASTBOOT_BUF_ADDR=0x11000000
+CONFIG_FASTBOOT_BUF_SIZE=0x10000000
+CONFIG_FASTBOOT_FLASH=y
+CONFIG_FASTBOOT_FLASH_MMC_DEV=0
+CONFIG_FASTBOOT_CMD_OEM_FORMAT=y
+CONFIG_SYS_I2C_TEGRA=y
+CONFIG_BUTTON_KEYBOARD=y
+CONFIG_DM_PMIC=y
+CONFIG_DM_REGULATOR=y
+CONFIG_DM_REGULATOR_FIXED=y
+CONFIG_PWM_TEGRA=y
+CONFIG_SYS_NS16550=y
+CONFIG_USB=y
+CONFIG_USB_EHCI_HCD=y
+CONFIG_USB_EHCI_TEGRA=y
+CONFIG_USB_ULPI_VIEWPORT=y
+CONFIG_USB_ULPI=y
+CONFIG_USB_KEYBOARD=y
+CONFIG_USB_GADGET=y
+CONFIG_USB_GADGET_MANUFACTURER="Acer"
+CONFIG_USB_GADGET_VENDOR_NUM=0x0502
+CONFIG_USB_GADGET_PRODUCT_NUM=0x3325
+CONFIG_CI_UDC=y
+CONFIG_VIDEO=y
+# CONFIG_VIDEO_LOGO is not set
+# CONFIG_VIDEO_BPP8 is not set
+CONFIG_VIDEO_TEGRA20=y
diff --git a/configs/poleg_evb_defconfig b/configs/poleg_evb_defconfig
index 74f4092..365f643 100644
--- a/configs/poleg_evb_defconfig
+++ b/configs/poleg_evb_defconfig
@@ -16,6 +16,7 @@
CONFIG_DM_RESET=y
CONFIG_SYS_LOAD_ADDR=0x10000000
CONFIG_TARGET_POLEG=y
+CONFIG_SYS_SKIP_UART_INIT=y
CONFIG_ENV_ADDR=0x80100000
CONFIG_FIT=y
CONFIG_USE_BOOTCOMMAND=y
diff --git a/configs/qemu_arm64_defconfig b/configs/qemu_arm64_defconfig
index 763fc14..03028c7 100644
--- a/configs/qemu_arm64_defconfig
+++ b/configs/qemu_arm64_defconfig
@@ -74,5 +74,5 @@
CONFIG_SEMIHOSTING=y
CONFIG_MBEDTLS_LIB=y
CONFIG_TPM=y
-CONFIG_GENERATE_SMBIOS_TABLE_VERBOSE=y
CONFIG_TPM_PCR_ALLOCATE=y
+CONFIG_GENERATE_SMBIOS_TABLE_VERBOSE=y
diff --git a/configs/socfpga_agilex5_defconfig b/configs/socfpga_agilex5_defconfig
index 8577ac6..ca3ec23 100644
--- a/configs/socfpga_agilex5_defconfig
+++ b/configs/socfpga_agilex5_defconfig
@@ -1,8 +1,7 @@
CONFIG_ARM=y
CONFIG_ARCH_SOCFPGA=y
CONFIG_TEXT_BASE=0x80200000
-CONFIG_NR_DRAM_BANKS=2
-CONFIG_SPL_LDSCRIPT="arch/arm/mach-socfpga/u-boot-spl-soc64.lds"
+CONFIG_NR_DRAM_BANKS=3
CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y
CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x80300000
CONFIG_SF_DEFAULT_MODE=0x2003
@@ -10,7 +9,7 @@
CONFIG_DM_GPIO=y
CONFIG_DEFAULT_DEVICE_TREE="socfpga_agilex5_socdk"
CONFIG_DM_RESET=y
-CONFIG_SPL_STACK=0x7f000
+CONFIG_SPL_STACK=0x7d000
CONFIG_SPL_HAS_BSS_LINKER_SECTION=y
CONFIG_SPL_BSS_START_ADDR=0xbff00000
CONFIG_SPL_BSS_MAX_SIZE=0x100000
@@ -30,10 +29,15 @@
CONFIG_USE_BOOTARGS=y
CONFIG_BOOTARGS="console=ttyS0,115200 initrd=0x90000000 root=/dev/ram0 rw init=/sbin/init ramdisk_size=10000000 earlycon panic=-1 nosmp kvm-arm.mode=nvhe"
CONFIG_SPL_MAX_SIZE=0x40000
+CONFIG_SPL_SYS_MALLOC=y
+CONFIG_SPL_HAS_CUSTOM_MALLOC_START=y
+CONFIG_SPL_CUSTOM_SYS_MALLOC_ADDR=0xbfa00000
+CONFIG_SPL_SYS_MALLOC_SIZE=0x500000
# CONFIG_SPL_RAW_IMAGE_SUPPORT is not set
# CONFIG_SPL_SHARES_INIT_SP_ADDR is not set
CONFIG_SPL_CACHE=y
CONFIG_SPL_SPI_FLASH_MTD=y
+CONFIG_SPL_MTD=y
CONFIG_SPL_SPI_LOAD=y
CONFIG_SYS_SPI_U_BOOT_OFFS=0x04000000
CONFIG_SPL_ATF=y
@@ -82,9 +86,15 @@
CONFIG_USB=y
CONFIG_USB_XHCI_HCD=y
CONFIG_USB_DWC2=y
-# CONFIG_WATCHDOG_AUTOSTART is not set
CONFIG_DESIGNWARE_WATCHDOG=y
CONFIG_WDT=y
# CONFIG_SPL_USE_TINY_PRINTF is not set
CONFIG_PANIC_HANG=y
CONFIG_SPL_CRC32=y
+CONFIG_BOARD_EARLY_INIT_F=y
+CONFIG_BLOBLIST=y
+CONFIG_BLOBLIST_SIZE=0x1000
+CONFIG_BLOBLIST_ADDR=0x7e000
+CONFIG_HANDOFF=y
+CONFIG_SPL_RECOVER_DATA_SECTION=y
+CONFIG_DWC_ETH_XGMAC=y
diff --git a/configs/starfive_visionfive2_defconfig b/configs/starfive_visionfive2_defconfig
index c3f2142..1e0a99e 100644
--- a/configs/starfive_visionfive2_defconfig
+++ b/configs/starfive_visionfive2_defconfig
@@ -75,7 +75,7 @@
CONFIG_CMD_PCI=y
CONFIG_CMD_USB=y
CONFIG_CMD_WDT=y
-CONFIG_CMD_TFTPPUT=y
+CONFIG_CMD_WGET=y
CONFIG_CMD_BOOTSTAGE=y
CONFIG_OF_BOARD=y
CONFIG_OF_LIST="starfive/jh7110-milkv-mars starfive/jh7110-pine64-star64 starfive/jh7110-starfive-visionfive-2-v1.2a starfive/jh7110-starfive-visionfive-2-v1.3b"
@@ -84,6 +84,7 @@
CONFIG_ENV_IS_IN_SPI_FLASH=y
CONFIG_ENV_SECT_SIZE_AUTO=y
CONFIG_SYS_RELOC_GD_ENV_ADDR=y
+CONFIG_NET_LWIP=y
CONFIG_SPL_DM_SEQ_ALIAS=y
CONFIG_REGMAP=y
CONFIG_SYSCON=y
diff --git a/configs/stih410-b2260_defconfig b/configs/stih410-b2260_defconfig
index 815f755..1e5190d 100644
--- a/configs/stih410-b2260_defconfig
+++ b/configs/stih410-b2260_defconfig
@@ -25,6 +25,7 @@
CONFIG_CMD_GPT=y
CONFIG_CMD_MMC=y
CONFIG_CMD_USB=y
+CONFIG_CMD_USB_MASS_STORAGE=y
CONFIG_CMD_TIME=y
CONFIG_CMD_TIMER=y
CONFIG_CMD_EXT4_WRITE=y
@@ -48,11 +49,13 @@
CONFIG_PHY=y
CONFIG_STI_USB_PHY=y
CONFIG_PINCTRL=y
+CONFIG_DM_REGULATOR=y
CONFIG_STI_RESET=y
CONFIG_STI_ASC_SERIAL=y
CONFIG_SYSRESET=y
CONFIG_TIMER=y
CONFIG_USB=y
+CONFIG_DM_USB_GADGET=y
CONFIG_USB_XHCI_HCD=y
CONFIG_USB_XHCI_DWC3=y
CONFIG_USB_EHCI_HCD=y
@@ -60,6 +63,8 @@
CONFIG_USB_OHCI_HCD=y
CONFIG_USB_OHCI_GENERIC=y
CONFIG_USB_DWC3=y
+CONFIG_USB_DWC3_GENERIC=y
+CONFIG_USB_DWC3_STI=y
CONFIG_USB_HOST_ETHER=y
CONFIG_USB_ETHER_ASIX=y
CONFIG_USB_ETHER_MCS7830=y
diff --git a/configs/syzygy_hub_defconfig b/configs/syzygy_hub_defconfig
index e7e15c6..27ff391 100644
--- a/configs/syzygy_hub_defconfig
+++ b/configs/syzygy_hub_defconfig
@@ -36,10 +36,10 @@
CONFIG_SPL_OS_BOOT=y
CONFIG_SPL_PAYLOAD_ARGS_ADDR=0x10000000
CONFIG_SYS_MAXARGS=32
+CONFIG_CMD_FPGA_LOADP=y
CONFIG_CMD_FPGA_LOADBP=y
CONFIG_CMD_FPGA_LOADFS=y
CONFIG_CMD_FPGA_LOADMK=y
-CONFIG_CMD_FPGA_LOADP=y
CONFIG_CMD_GPIO=y
CONFIG_CMD_I2C=y
CONFIG_CMD_MMC=y
diff --git a/configs/tools-only_defconfig b/configs/tools-only_defconfig
index cecd261..e64bb76 100644
--- a/configs/tools-only_defconfig
+++ b/configs/tools-only_defconfig
@@ -9,10 +9,11 @@
CONFIG_ANDROID_BOOT_IMAGE=y
CONFIG_TIMESTAMP=y
CONFIG_FIT=y
-CONFIG_FIT_SIGNATURE=y
CONFIG_BOOTSTD_FULL=n
CONFIG_BOOTMETH_CROS=n
CONFIG_BOOTMETH_VBE=n
+CONFIG_IMAGE_PRE_LOAD=y
+CONFIG_IMAGE_PRE_LOAD_SIG=y
CONFIG_USE_BOOTCOMMAND=y
CONFIG_BOOTCOMMAND="run distro_bootcmd"
CONFIG_CMD_BOOTD=n
diff --git a/configs/vexpress_fvp_bloblist_defconfig b/configs/vexpress_fvp_bloblist_defconfig
index dcc87db..4d52b96 100644
--- a/configs/vexpress_fvp_bloblist_defconfig
+++ b/configs/vexpress_fvp_bloblist_defconfig
@@ -1,5 +1,5 @@
#include <configs/vexpress_fvp_defconfig>
CONFIG_BLOBLIST=y
-CONFIG_BLOBLIST_PASSAGE=y
+CONFIG_BLOBLIST_PASSAGE_MANDATORY=y
CONFIG_BLOBLIST_SIZE_RELOC=0x10000
diff --git a/configs/xilinx_zynq_virt_defconfig b/configs/xilinx_zynq_virt_defconfig
index fdf8bb3..9196a95 100644
--- a/configs/xilinx_zynq_virt_defconfig
+++ b/configs/xilinx_zynq_virt_defconfig
@@ -61,10 +61,10 @@
CONFIG_CMD_MEMTEST=y
CONFIG_SYS_ALT_MEMTEST=y
CONFIG_CMD_DFU=y
+CONFIG_CMD_FPGA_LOADP=y
CONFIG_CMD_FPGA_LOADBP=y
CONFIG_CMD_FPGA_LOADFS=y
CONFIG_CMD_FPGA_LOADMK=y
-CONFIG_CMD_FPGA_LOADP=y
CONFIG_CMD_GPIO=y
CONFIG_CMD_I2C=y
CONFIG_CMD_MMC=y
diff --git a/configs/xilinx_zynqmp_kria_defconfig b/configs/xilinx_zynqmp_kria_defconfig
index ad46c09..1a6bd67 100644
--- a/configs/xilinx_zynqmp_kria_defconfig
+++ b/configs/xilinx_zynqmp_kria_defconfig
@@ -70,8 +70,8 @@
CONFIG_CMD_SHA1SUM=y
CONFIG_CMD_CLK=y
CONFIG_CMD_DFU=y
-CONFIG_CMD_FPGA_LOADBP=y
CONFIG_CMD_FPGA_LOADP=y
+CONFIG_CMD_FPGA_LOADBP=y
CONFIG_CMD_FPGA_LOAD_SECURE=y
CONFIG_CMD_GPIO=y
CONFIG_CMD_PWM=y
diff --git a/configs/xilinx_zynqmp_virt_defconfig b/configs/xilinx_zynqmp_virt_defconfig
index 036268c..e5e56ba 100644
--- a/configs/xilinx_zynqmp_virt_defconfig
+++ b/configs/xilinx_zynqmp_virt_defconfig
@@ -68,8 +68,8 @@
CONFIG_CMD_SHA1SUM=y
CONFIG_CMD_CLK=y
CONFIG_CMD_DFU=y
-CONFIG_CMD_FPGA_LOADBP=y
CONFIG_CMD_FPGA_LOADP=y
+CONFIG_CMD_FPGA_LOADBP=y
CONFIG_CMD_FPGA_LOAD_SECURE=y
CONFIG_CMD_GPIO=y
CONFIG_CMD_PWM=y
diff --git a/doc/board/acer/index.rst b/doc/board/acer/index.rst
new file mode 100644
index 0000000..3741a70
--- /dev/null
+++ b/doc/board/acer/index.rst
@@ -0,0 +1,9 @@
+.. SPDX-License-Identifier: GPL-2.0+
+
+ACER
+====
+
+.. toctree::
+ :maxdepth: 2
+
+ picasso
diff --git a/doc/board/acer/picasso.rst b/doc/board/acer/picasso.rst
new file mode 100644
index 0000000..b1d360d
--- /dev/null
+++ b/doc/board/acer/picasso.rst
@@ -0,0 +1,125 @@
+.. SPDX-License-Identifier: GPL-2.0+
+
+U-Boot for the Acer Iconia Tab A500
+===================================
+
+``DISCLAMER!`` Moving your Acer Iconia Tab A500 to use U-Boot assumes
+replacement of the vendor Acer bootloader. Vendor Android firmwares will no
+longer be able to run on the device. This replacement IS reversible.
+
+Quick Start
+-----------
+
+- Build U-Boot
+- Process U-Boot
+- Flashing U-Boot into the eMMC
+- Boot
+- Self Upgrading
+
+Build U-Boot
+------------
+
+.. code-block:: bash
+
+ $ export CROSS_COMPILE=arm-none-eabi-
+ $ make picasso_defconfig
+ $ make
+
+After the build succeeds, you will obtain the final ``u-boot-dtb-tegra.bin``
+image, ready for further processing.
+
+Process U-Boot
+--------------
+
+``DISCLAMER!`` All questions related to the re-crypt work should be asked
+in re-crypt repo issues. NOT HERE!
+
+re-crypt is a tool that processes the ``u-boot-dtb-tegra.bin`` binary into form
+usable by device. This process is required only on the first installation or
+to recover the device in case of a failed update.
+
+Permanent installation can be performed either by using the nv3p protocol or by
+pre-loading just built U-Boot into RAM.
+
+Processing for the NV3P protocol
+********************************
+
+.. code-block:: bash
+
+ $ git clone https://gitlab.com/grate-driver/re-crypt.git
+ $ cd re-crypt # place your u-boot-dtb-tegra.bin here
+ $ ./re-crypt.py --dev a500
+
+The script will produce a ``repart-block.bin`` ready to flash.
+
+Processing for pre-loaded U-Boot
+********************************
+
+The procedure is the same, but the ``--split`` argument is used with the
+``re-crypt.py``. The script will produce ``bct.img`` and ``ebt.img`` ready
+to flash.
+
+Flashing U-Boot into the eMMC
+-----------------------------
+
+``DISCLAMER!`` All questions related to NvFlash should be asked in the proper
+place. NOT HERE! Flashing U-Boot will erase all eMMC, so make a backup before!
+
+Permanent installation can be performed either by using the nv3p protocol or by
+pre-loading just built U-Boot into RAM.
+
+Flashing with the NV3P protocol
+*******************************
+
+Nv3p is a custom Nvidia protocol used to recover bricked devices. Devices can
+enter it either by pre-loading vendor bootloader into RAM with the nvflash.
+
+With nv3p, ``repart-block.bin`` is used. It contains BCT and a bootloader in
+encrypted state in form, which can just be written RAW at the start of eMMC.
+
+.. code-block:: bash
+
+ $ nvflash --setbct --bct picasso.bct --configfile flash.cfg --bl bootloader.bin
+ --sbk 0xXXXXXXXX 0xXXXXXXXX 0xXXXXXXXX 0xXXXXXXXX --sync # replace with your SBK
+ $ nvflash --resume --rawdevicewrite 0 1024 repart-block.bin
+
+When flashing is done, reboot the device.
+
+Flashing with a pre-loaded U-Boot
+*********************************
+
+U-Boot pre-loaded into RAM acts the same as when it was booted "cold". Currently
+U-Boot supports bootmenu entry fastboot, which allows to write a processed copy
+of U-Boot permanently into eMMC.
+
+While pre-loading U-Boot, hold the ``volume down`` button which will trigger
+the bootmenu. There, select ``fastboot`` using the volume and power buttons.
+After, on host PC, do:
+
+.. code-block:: bash
+
+ $ fastboot flash 0.1 bct.img
+ $ fastboot flash 0.2 ebt.img
+ $ fastboot reboot
+
+Device will reboot.
+
+Boot
+----
+
+To boot Linux, U-Boot will look for an ``extlinux.conf`` on MicroSD and then on
+eMMC. Additionally, if the Volume Down button is pressed while booting, the
+device will enter bootmenu. Bootmenu contains entries to mount MicroSD and eMMC
+as mass storage, fastboot, reboot, reboot RCM, poweroff, enter U-Boot console
+and update bootloader (check the next chapter).
+
+Flashing ``repart-block.bin`` eliminates vendor restrictions on eMMC and allows
+the user to use/partition it in any way the user desires.
+
+Self Upgrading
+--------------
+
+Place your ``u-boot-dtb-tegra.bin`` on the first partition of the MicroSD card
+and insert it into the tablet. Enter bootmenu, choose update the bootloader
+option with the Power button and U-Boot should update itself. Once the process
+is completed, U-Boot will ask to press any button to reboot.
diff --git a/doc/board/armltd/vexpress64.rst b/doc/board/armltd/vexpress64.rst
index 4dadadb..a732fac 100644
--- a/doc/board/armltd/vexpress64.rst
+++ b/doc/board/armltd/vexpress64.rst
@@ -53,8 +53,8 @@
bloblist, or utilizing a standard passage-provided bloblist with automatic size
detection.
-By default, ``vexpress_fvp_bloblist_defconfig`` uses the standard passage method
-(CONFIG_BLOBLIST_PASSAGE) because TF-A provides a Transfer List in non-secure
+By default, ``vexpress_fvp_bloblist_defconfig`` uses the standard passage method mandatorily
+(CONFIG_BLOBLIST_PASSAGE_MANDATORY) because TF-A provides a Transfer List in non-secure
memory that U-Boot can utilise. This Bloblist, which is referred to as a Transfer List in
TF-A, contains all necessary data for the handoff process, including DT and ACPI
tables.
diff --git a/doc/board/asus/grouper.rst b/doc/board/asus/grouper.rst
index d56a9ca..1446958 100644
--- a/doc/board/asus/grouper.rst
+++ b/doc/board/asus/grouper.rst
@@ -25,7 +25,7 @@
.. code-block:: bash
- $ export CROSS_COMPILE=arm-linux-gnueabi-
+ $ export CROSS_COMPILE=arm-none-eabi-
$ make grouper_defconfig # For all grouper versions and tilapia
$ make
@@ -79,18 +79,18 @@
*******************************
Nv3p is a custom Nvidia protocol used to recover bricked devices. Devices can
-enter it either by using ``wheelie`` with the correct ``blob.bin`` file or by
-pre-loading vendor bootloader with the Fusée Gelée.
+enter it by pre-loading vendor bootloader with the Fusée Gelée.
With nv3p, ``repart-block.bin`` is used. It contains BCT and a bootloader in
encrypted state in form, which can just be written RAW at the start of eMMC.
.. code-block:: bash
- $ wheelie --blob blob.bin
- $ nvflash --resume --rawdevicewrite 0 1024 repart-block.bin
+ $ ./run_bootloader.sh -s T30 -t ./bct/grouper.bct -b android_bootloader.bin
+ $ ./utiils/nvflash_v1.13.87205 --resume --rawdevicewrite 0 1024 repart-block.bin
-When flashing is done, reboot the device.
+When flashing is done, reboot the device. Note that if you have cellular version,
+use ``tilapia.bct``.
Flashing with a pre-loaded U-Boot
*********************************
diff --git a/doc/board/asus/transformer_t20.rst b/doc/board/asus/transformer_t20.rst
index d4bc12d..4f4f893 100644
--- a/doc/board/asus/transformer_t20.rst
+++ b/doc/board/asus/transformer_t20.rst
@@ -25,7 +25,7 @@
.. code-block:: bash
- $ export CROSS_COMPILE=arm-linux-gnueabi-
+ $ export CROSS_COMPILE=arm-none-eabi-
$ make transformer_t20_defconfig tf101.config # For TF101
$ make
@@ -84,8 +84,8 @@
.. code-block:: bash
- $ wheelie --blob blob.bin
- $ nvflash --resume --rawdevicewrite 0 1024 repart-block.bin
+ $ wheelie -1 --bl bootloader.bin --bct tf101.bct --odm 0x300d8011 || break
+ $ nvflash --resume --rawdevicewrite 0 2048 repart-block.bin
When flashing is done, reboot the device.
diff --git a/doc/board/asus/transformer_t30.rst b/doc/board/asus/transformer_t30.rst
index bebc4b9..012a382 100644
--- a/doc/board/asus/transformer_t30.rst
+++ b/doc/board/asus/transformer_t30.rst
@@ -22,6 +22,7 @@
U-Boot features ability to detect transformer device model on which it is
loaded. The list of supported devices include:
+
- ASUS Transformer Prime TF201
- ASUS Transformer Pad (3G/LTE) TF300T/TG/TL
- ASUS Transformer Infinity TF700T
@@ -30,7 +31,7 @@
.. code-block:: bash
- $ export CROSS_COMPILE=arm-linux-gnueabi-
+ $ export CROSS_COMPILE=arm-none-eabi-
$ make transformer_t30_defconfig
$ make
@@ -84,18 +85,18 @@
*******************************
Nv3p is a custom Nvidia protocol used to recover bricked devices. Devices can
-enter it either by using ``wheelie`` with the correct ``blob.bin`` file or by
-pre-loading vendor bootloader with the Fusée Gelée.
+enter it by pre-loading vendor bootloader with the Fusée Gelée.
With nv3p, ``repart-block.bin`` is used. It contains BCT and a bootloader in
encrypted state in form, which can just be written RAW at the start of eMMC.
.. code-block:: bash
- $ wheelie --blob blob.bin
- $ nvflash --resume --rawdevicewrite 0 1024 repart-block.bin
+ $ ./run_bootloader.sh -s T30 -t ./bct/tf201.bct -b android_bootloader.bin
+ $ ./utiils/nvflash_v1.13.87205 --resume --rawdevicewrite 0 1024 repart-block.bin
-When flashing is done, reboot the device.
+When flashing is done, reboot the device. Note that you should adjust bct file
+name according to your device.
Flashing with a pre-loaded U-Boot
*********************************
diff --git a/doc/board/htc/endeavoru.rst b/doc/board/htc/endeavoru.rst
index e0edefe..53df2d0 100644
--- a/doc/board/htc/endeavoru.rst
+++ b/doc/board/htc/endeavoru.rst
@@ -21,7 +21,7 @@
.. code-block:: bash
- $ export CROSS_COMPILE=arm-linux-gnueabi-
+ $ export CROSS_COMPILE=arm-none-eabi-
$ make endeavoru_defconfig
$ make
@@ -72,16 +72,15 @@
*******************************
Nv3p is a custom Nvidia protocol used to recover bricked devices. Devices can
-enter it either by using ``wheelie`` with the correct ``blob.bin`` file or by
-pre-loading vendor bootloader with the Fusée Gelée.
+enter it by pre-loading vendor bootloader with the Fusée Gelée.
With nv3p, ``repart-block.bin`` is used. It contains BCT and a bootloader in
encrypted state in form, which can just be written RAW at the start of eMMC.
.. code-block:: bash
- $ wheelie --blob blob.bin
- $ nvflash --resume --rawdevicewrite 0 1024 repart-block.bin
+ $ ./run_bootloader.sh -s T30 -t ./bct/endeavoru.bct -b android_bootloader.bin
+ $ ./utiils/nvflash_v1.13.87205 --resume --rawdevicewrite 0 1024 repart-block.bin
When flashing is done, reboot the device.
diff --git a/doc/board/index.rst b/doc/board/index.rst
index 74c4dd1..b055046 100644
--- a/doc/board/index.rst
+++ b/doc/board/index.rst
@@ -6,6 +6,7 @@
.. toctree::
:maxdepth: 2
+ acer/index
actions/index
advantech/index
andestech/index
diff --git a/doc/board/lg/x3_t30.rst b/doc/board/lg/x3_t30.rst
index 618b00d..9ff7503 100644
--- a/doc/board/lg/x3_t30.rst
+++ b/doc/board/lg/x3_t30.rst
@@ -24,7 +24,7 @@
.. code-block:: bash
- $ export CROSS_COMPILE=arm-linux-gnueabi-
+ $ export CROSS_COMPILE=arm-none-eabi-
$ make x3_t30_defconfig p895.config # For LG Optimus Vu
$ make
@@ -75,18 +75,18 @@
*******************************
Nv3p is a custom Nvidia protocol used to recover bricked devices. Devices can
-enter it either by using ``wheelie`` with the correct ``blob.bin`` file or by
-pre-loading vendor bootloader with the Fusée Gelée.
+enter it by pre-loading vendor bootloader with the Fusée Gelée.
With nv3p, ``repart-block.bin`` is used. It contains BCT and a bootloader in
encrypted state in form, which can just be written RAW at the start of eMMC.
.. code-block:: bash
- $ wheelie --blob blob.bin
- $ nvflash --resume --rawdevicewrite 0 1024 repart-block.bin
+ $ ./run_bootloader.sh -s T30 -t ./bct/p895.bct -b android_bootloader.bin
+ $ ./utiils/nvflash_v1.13.87205 --resume --rawdevicewrite 0 1024 repart-block.bin
-When flashing is done, reboot the device.
+When flashing is done, reboot the device. Note that if you have Optimus 4x HD,
+use ``p880.bct``.
Flashing with a pre-loaded U-Boot
*********************************
@@ -122,7 +122,7 @@
Self Upgrading
--------------
-Place your ``u-boot-dtb-tegra.bin`` on the first partition of the eMMC (using
-ability of u-boot to mount it). Enter bootmenu, choose update bootloader option
-with Power button and U-Boot should update itself. Once the process is
-completed, U-Boot will ask to press any button to reboot.
+Place your ``u-boot-dtb-tegra.bin`` on the first partition of the eMMC or MicroSD
+card if it is supported (using ability of u-boot to mount it). Enter bootmenu,
+choose update bootloader option with Power button and U-Boot should update itself.
+Once the process is completed, U-Boot will ask to press any button to reboot.
diff --git a/doc/board/microsoft/surface-rt.rst b/doc/board/microsoft/surface-rt.rst
index b5645e7..2b29cce 100644
--- a/doc/board/microsoft/surface-rt.rst
+++ b/doc/board/microsoft/surface-rt.rst
@@ -14,7 +14,7 @@
.. code-block:: bash
- $ export CROSS_COMPILE=arm-linux-gnueabi-
+ $ export CROSS_COMPILE=arm-none-eabi-
$ make surface-rt_defconfig
$ make
@@ -38,4 +38,4 @@
To boot Linux, U-Boot will look for an ``extlinux.conf`` on MicroSD and then on
eMMC. Additionally, if the Volume Down button is pressed while loading, the
device will enter bootmenu. Bootmenu contains entries to mount MicroSD and eMMC
-as mass storage, fastboot, reboot, reboot RCM, poweroffand enter U-Boot console.
+as mass storage, fastboot, reboot, reboot RCM, poweroff and enter U-Boot console.
diff --git a/doc/board/wexler/qc750.rst b/doc/board/wexler/qc750.rst
index b61e401..169629c 100644
--- a/doc/board/wexler/qc750.rst
+++ b/doc/board/wexler/qc750.rst
@@ -21,7 +21,7 @@
.. code-block:: bash
- $ export CROSS_COMPILE=arm-linux-gnueabi-
+ $ export CROSS_COMPILE=arm-none-eabi-
$ make qc750_defconfig
$ make
@@ -71,16 +71,15 @@
Flashing with the NV3P protocol
*******************************
-Nv3p is a custom Nvidia protocol used to recover bricked devices. Devices can
-enter it either by using ``wheelie`` with the correct ``blob.bin`` file or by
-pre-loading vendor bootloader with the Fusée Gelée.
+Nv3p is a custom Nvidia protocol used to recover bricked devices. Tegrarcm is
+used to handle such state.
With nv3p, ``repart-block.bin`` is used. It contains BCT and a bootloader in
encrypted state in form, which can just be written RAW at the start of eMMC.
.. code-block:: bash
- $ wheelie --bct qc750.bct --bl bootloader.bin
+ $ tegrarcm --bct qc750.bct --bootloader android_bootloader.bin --loadaddr 0x80108000
$ nvflash --resume --rawdevicewrite 0 1024 repart-block.bin
When flashing is done, reboot the device.
diff --git a/doc/develop/release_cycle.rst b/doc/develop/release_cycle.rst
index 03deea2..b6ad721 100644
--- a/doc/develop/release_cycle.rst
+++ b/doc/develop/release_cycle.rst
@@ -72,7 +72,7 @@
* U-Boot v2025.04-rc2 was released on Mon 10 February 2025.
-.. * U-Boot v2025.04-rc3 was released on Mon 24 February 2025.
+* U-Boot v2025.04-rc3 was released on Mon 24 February 2025.
.. * U-Boot v2025.04-rc4 was released on Mon 10 March 2025.
diff --git a/doc/usage/index.rst b/doc/usage/index.rst
index bf2335d..fc05847 100644
--- a/doc/usage/index.rst
+++ b/doc/usage/index.rst
@@ -93,6 +93,7 @@
cmd/msr
cmd/mtest
cmd/mtrr
+ cmd/mv
cmd/optee
cmd/panic
cmd/part
diff --git a/drivers/clk/altera/clk-agilex5.c b/drivers/clk/altera/clk-agilex5.c
index 716c715..fb1e72f 100644
--- a/drivers/clk/altera/clk-agilex5.c
+++ b/drivers/clk/altera/clk-agilex5.c
@@ -1,13 +1,13 @@
// SPDX-License-Identifier: GPL-2.0
/*
* Copyright (C) 2024 Intel Corporation <www.intel.com>
+ * Copyright (C) 2025 Altera Corporation <www.altera.com>
*/
-#include <clk-uclass.h>
#include <config.h>
-#include <errno.h>
-#include <dm.h>
#include <log.h>
+#include <dm.h>
+#include <errno.h>
#include <stdarg.h>
#include <stdio.h>
#include <time.h>
@@ -23,9 +23,14 @@
#include <linux/types.h>
#include <asm/arch/clock_manager.h>
#include <dt-bindings/clock/agilex5-clock.h>
+#include <wait_bit.h>
+#include <clk-uclass.h>
DECLARE_GLOBAL_DATA_PTR;
+#define CLKMGR_CTRL_SWCTRLBTCLKEN_MASK BIT(8)
+#define CLKMGR_CTRL_SWCTRLBTCLKSEL_MASK BIT(9)
+
struct socfpga_clk_plat {
void __iomem *regs;
};
@@ -36,21 +41,30 @@
*/
static void clk_write_bypass_mainpll(struct socfpga_clk_plat *plat, u32 val)
{
+ uintptr_t base_addr = (uintptr_t)plat->regs;
+
CM_REG_WRITEL(plat, val, CLKMGR_MAINPLL_BYPASS);
- cm_wait_for_fsm();
+ wait_for_bit_le32((const void *)(base_addr + CLKMGR_STAT), CLKMGR_STAT_BUSY,
+ false, 20000, false);
}
static void clk_write_bypass_perpll(struct socfpga_clk_plat *plat, u32 val)
{
+ uintptr_t base_addr = (uintptr_t)plat->regs;
+
CM_REG_WRITEL(plat, val, CLKMGR_PERPLL_BYPASS);
- cm_wait_for_fsm();
+ wait_for_bit_le32((const void *)(base_addr + CLKMGR_STAT), CLKMGR_STAT_BUSY,
+ false, 20000, false);
}
/* function to write the ctrl register which requires a poll of the busy bit */
static void clk_write_ctrl(struct socfpga_clk_plat *plat, u32 val)
{
+ uintptr_t base_addr = (uintptr_t)plat->regs;
+
CM_REG_WRITEL(plat, val, CLKMGR_CTRL);
- cm_wait_for_fsm();
+ wait_for_bit_le32((const void *)(base_addr + CLKMGR_STAT), CLKMGR_STAT_BUSY,
+ false, 20000, false);
}
static const struct {
@@ -59,15 +73,6 @@
u32 mask;
} membus_pll[] = {
{
- MEMBUS_CLKSLICE_REG,
- /*
- * BIT[7:7]
- * Enable source synchronous mode
- */
- BIT(7),
- BIT(7)
- },
- {
MEMBUS_SYNTHCALFOSC_INIT_CENTERFREQ_REG,
/*
* BIT[0:0]
@@ -238,6 +243,7 @@
{
struct socfpga_clk_plat *plat = dev_get_plat(dev);
u32 vcocalib;
+ uintptr_t base_addr = (uintptr_t)plat->regs;
if (!cfg)
return;
@@ -249,7 +255,8 @@
CM_REG_SETBITS(plat, CLKMGR_PERPLL_PLLGLOB,
CLKMGR_PLLGLOB_PD_MASK | CLKMGR_PLLGLOB_RST_MASK);
- cm_wait_for_lock(CLKMGR_STAT_ALLPLL_LOCKED_MASK);
+ wait_for_bit_le32((const void *)(base_addr + CLKMGR_STAT),
+ CLKMGR_STAT_ALLPLL_LOCKED_MASK, true, 20000, false);
/* Put both PLLs in bypass */
clk_write_bypass_mainpll(plat, CLKMGR_BYPASS_MAINPLL_ALL);
@@ -264,9 +271,14 @@
CM_REG_READL(plat, CLKMGR_CTRL) & ~CLKMGR_CTRL_BOOTMODE);
} else {
#ifdef CONFIG_XPL_BUILD
- /* Always force clock manager into boot mode before any configuration */
- clk_write_ctrl(plat,
- CM_REG_READL(plat, CLKMGR_CTRL) | CLKMGR_CTRL_BOOTMODE);
+ /*
+ * Configure HPS Internal Oscillator as default boot_clk source,
+ * always force clock manager into boot mode before any configuration
+ */
+ clk_write_ctrl(plat, CM_REG_READL(plat, CLKMGR_CTRL) |
+ CLKMGR_CTRL_BOOTMODE |
+ CLKMGR_CTRL_SWCTRLBTCLKEN_MASK |
+ CLKMGR_CTRL_SWCTRLBTCLKSEL_MASK);
#else
/* Skip clock configuration in SSBL if it's not in boot mode */
if (!(CM_REG_READL(plat, CLKMGR_CTRL) & CLKMGR_CTRL_BOOTMODE))
@@ -365,7 +377,8 @@
CLKMGR_PLLCX_EN_SET_MSK,
CLKMGR_PERPLL_PLLC3);
- cm_wait_for_lock(CLKMGR_STAT_ALLPLL_LOCKED_MASK);
+ wait_for_bit_le32((const void *)(base_addr + CLKMGR_STAT),
+ CLKMGR_STAT_ALLPLL_LOCKED_MASK, true, 20000, false);
CM_REG_WRITEL(plat, CLKMGR_LOSTLOCK_SET_MASK, CLKMGR_MAINPLL_LOSTLOCK);
CM_REG_WRITEL(plat, CLKMGR_LOSTLOCK_SET_MASK, CLKMGR_PERPLL_LOSTLOCK);
diff --git a/drivers/clk/mediatek/Makefile b/drivers/clk/mediatek/Makefile
index e412c92..1289368 100644
--- a/drivers/clk/mediatek/Makefile
+++ b/drivers/clk/mediatek/Makefile
@@ -3,7 +3,6 @@
obj-$(CONFIG_ARCH_MEDIATEK) += clk-mtk.o
# SoC Drivers
-obj-$(CONFIG_MT8512) += clk-mt8512.o
obj-$(CONFIG_TARGET_MT7623) += clk-mt7623.o
obj-$(CONFIG_TARGET_MT7622) += clk-mt7622.o
obj-$(CONFIG_TARGET_MT7629) += clk-mt7629.o
@@ -13,5 +12,6 @@
obj-$(CONFIG_TARGET_MT7987) += clk-mt7987.o
obj-$(CONFIG_TARGET_MT8183) += clk-mt8183.o
obj-$(CONFIG_TARGET_MT8365) += clk-mt8365.o
+obj-$(CONFIG_TARGET_MT8512) += clk-mt8512.o
obj-$(CONFIG_TARGET_MT8516) += clk-mt8516.o
obj-$(CONFIG_TARGET_MT8518) += clk-mt8518.o
diff --git a/drivers/ddr/altera/Makefile b/drivers/ddr/altera/Makefile
index c1d6a6b..b19f360 100644
--- a/drivers/ddr/altera/Makefile
+++ b/drivers/ddr/altera/Makefile
@@ -4,7 +4,7 @@
# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
#
# (C) Copyright 2010, Thomas Chou <thomas@wytron.com.tw>
-# Copyright (C) 2014-2021 Altera Corporation <www.altera.com>
+# Copyright (C) 2014-2025 Altera Corporation <www.altera.com>
ifdef CONFIG_$(XPL_)ALTERA_SDRAM
obj-$(CONFIG_TARGET_SOCFPGA_GEN5) += sdram_gen5.o sequencer.o
@@ -12,4 +12,5 @@
obj-$(CONFIG_TARGET_SOCFPGA_STRATIX10) += sdram_soc64.o sdram_s10.o
obj-$(CONFIG_TARGET_SOCFPGA_AGILEX) += sdram_soc64.o sdram_agilex.o
obj-$(CONFIG_TARGET_SOCFPGA_N5X) += sdram_soc64.o sdram_n5x.o
+obj-$(CONFIG_TARGET_SOCFPGA_AGILEX5) += sdram_soc64.o sdram_agilex5.o iossm_mailbox.o
endif
diff --git a/drivers/ddr/altera/iossm_mailbox.c b/drivers/ddr/altera/iossm_mailbox.c
new file mode 100644
index 0000000..db9435d
--- /dev/null
+++ b/drivers/ddr/altera/iossm_mailbox.c
@@ -0,0 +1,748 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (C) 2025 Altera Corporation <www.altera.com>
+ *
+ */
+
+#include <hang.h>
+#include <string.h>
+#include <wait_bit.h>
+#include <asm/arch/base_addr_soc64.h>
+#include <asm/io.h>
+#include <linux/bitfield.h>
+#include "iossm_mailbox.h"
+
+#define TIMEOUT_120000MS 120000
+#define TIMEOUT_60000MS 60000
+#define TIMEOUT TIMEOUT_120000MS
+#define IOSSM_STATUS_CAL_SUCCESS BIT(0)
+#define IOSSM_STATUS_CAL_FAIL BIT(1)
+#define IOSSM_STATUS_CAL_BUSY BIT(2)
+#define IOSSM_STATUS_COMMAND_RESPONSE_READY BIT(0)
+#define IOSSM_CMD_RESPONSE_STATUS_OFFSET 0x45C
+#define IOSSM_CMD_RESPONSE_DATA_0_OFFSET 0x458
+#define IOSSM_CMD_RESPONSE_DATA_1_OFFSET 0x454
+#define IOSSM_CMD_RESPONSE_DATA_2_OFFSET 0x450
+#define IOSSM_CMD_REQ_OFFSET 0x43C
+#define IOSSM_CMD_PARAM_0_OFFSET 0x438
+#define IOSSM_CMD_PARAM_1_OFFSET 0x434
+#define IOSSM_CMD_PARAM_2_OFFSET 0x430
+#define IOSSM_CMD_PARAM_3_OFFSET 0x42C
+#define IOSSM_CMD_PARAM_4_OFFSET 0x428
+#define IOSSM_CMD_PARAM_5_OFFSET 0x424
+#define IOSSM_CMD_PARAM_6_OFFSET 0x420
+#define IOSSM_CMD_RESPONSE_DATA_SHORT_MASK GENMASK(31, 16)
+#define IOSSM_CMD_RESPONSE_DATA_SHORT(n) FIELD_GET(IOSSM_CMD_RESPONSE_DATA_SHORT_MASK, n)
+#define IOSSM_STATUS_CMD_RESPONSE_ERROR_MASK GENMASK(7, 5)
+#define IOSSM_STATUS_CMD_RESPONSE_ERROR(n) FIELD_GET(IOSSM_STATUS_CMD_RESPONSE_ERROR_MASK, n)
+#define IOSSM_STATUS_GENERAL_ERROR_MASK GENMASK(4, 1)
+#define IOSSM_STATUS_GENERAL_ERROR(n) FIELD_GET(IOSSM_STATUS_GENERAL_ERROR_MASK, n)
+
+/* Offset of Mailbox Read-only Registers */
+#define IOSSM_MAILBOX_HEADER_OFFSET 0x0
+#define IOSSM_MEM_INTF_INFO_0_OFFSET 0X200
+#define IOSSM_MEM_INTF_INFO_1_OFFSET 0x280
+#define IOSSM_MEM_TECHNOLOGY_INTF0_OFFSET 0x210
+#define IOSSM_MEM_TECHNOLOGY_INTF1_OFFSET 0x290
+#define IOSSM_MEM_WIDTH_INFO_INTF0_OFFSET 0x230
+#define IOSSM_MEM_WIDTH_INFO_INTF1_OFFSET 0x2B0
+#define IOSSM_MEM_TOTAL_CAPACITY_INTF0_OFFSET 0x234
+#define IOSSM_MEM_TOTAL_CAPACITY_INTF1_OFFSET 0x2B4
+#define IOSSM_ECC_ENABLE_INTF0_OFFSET 0x240
+#define IOSSM_ECC_ENABLE_INTF1_OFFSET 0x2C0
+#define IOSSM_ECC_SCRUB_STATUS_INTF0_OFFSET 0x244
+#define IOSSM_ECC_SCRUB_STATUS_INTF1_OFFSET 0x2C4
+#define IOSSM_LP_MODE_INTF0_OFFSET 0x250
+#define IOSSM_LP_MODE_INTF1_OFFSET 0x2D0
+#define IOSSM_MEM_INIT_STATUS_INTF0_OFFSET 0x260
+#define IOSSM_MEM_INIT_STATUS_INTF1_OFFSET 0x2E0
+#define IOSSM_BIST_STATUS_INTF0_OFFSET 0x264
+#define IOSSM_BIST_STATUS_INTF1_OFFSET 0x2E4
+#define IOSSM_ECC_ERR_STATUS_OFFSET 0x300
+#define IOSSM_ECC_ERR_DATA_START_OFFSET 0x310
+#define IOSSM_STATUS_OFFSET 0x400
+#define IOSSM_STATUS_CAL_INTF0_OFFSET 0x404
+#define IOSSM_STATUS_CAL_INTF1_OFFSET 0x408
+
+#define ECC_INTSTATUS_SERR SOCFPGA_SYSMGR_ADDRESS + 0x9C
+#define ECC_INISTATUS_DERR SOCFPGA_SYSMGR_ADDRESS + 0xA0
+#define DDR_CSR_CLKGEN_LOCKED_IO96B0_MASK BIT(16)
+#define DDR_CSR_CLKGEN_LOCKED_IO96B1_MASK BIT(17)
+
+/* offset info of GET_MEM_INTF_INFO */
+#define INTF_IP_TYPE_MASK GENMASK(31, 29)
+#define INTF_INSTANCE_ID_MASK GENMASK(28, 24)
+
+/* offset info of GET_MEM_CAL_STATUS */
+#define INTF_UNUSED 0x0
+#define INTF_MEM_CAL_STATUS_SUCCESS 0x1
+#define INTF_MEM_CAL_STATUS_FAIL 0x2
+#define INTF_MEM_CAL_STATUS_ONGOING 0x4
+
+/* offset info of MEM_TECHNOLOGY_INTF */
+#define INTF_DDR_TYPE_MASK GENMASK(2, 0)
+
+/* offset info of MEM_TOTAL_CAPACITY_INTF */
+#define INTF_CAPACITY_GBITS_MASK GENMASK(7, 0)
+
+/* offset info of ECC_ENABLE_INTF */
+#define INTF_ECC_ENABLE_TYPE_MASK GENMASK(1, 0)
+
+/* cmd opcode BIST_MEM_INIT_START, BIST performed on full memory address range */
+#define BIST_FULL_MEM BIT(6)
+
+/* offset info of ECC_ENABLE_INTF */
+#define INTF_BIST_STATUS_MASK BIT(0)
+
+/* offset info of ECC_ERR_STATUS */
+#define ECC_ERR_COUNTER_MASK GENMASK(15, 0)
+
+/* offset info of ECC_ERR_DATA */
+#define ECC_ERR_IP_TYPE_MASK GENMASK(24, 22)
+#define ECC_ERR_INSTANCE_ID_MASK GENMASK(21, 17)
+#define ECC_ERR_SOURCE_ID_MASK GENMASK(16, 10)
+#define ECC_ERR_TYPE_MASK GENMASK(9, 6)
+#define ECC_ERR_ADDR_UPPER_MASK GENMASK(5, 0)
+#define ECC_ERR_ADDR_LOWER_MASK GENMASK(31, 0)
+
+#define MAX_ECC_ERR_INFO_COUNT 16
+
+#define IO96B_MB_REQ_SETUP(v, w, x, y, z) \
+ usr_req.ip_type = v; \
+ usr_req.ip_id = w; \
+ usr_req.usr_cmd_type = x; \
+ usr_req.usr_cmd_opcode = y; \
+ usr_req.cmd_param[0] = z; \
+ for (n = 1; n < NUM_CMD_PARAM; n++) \
+ usr_req.cmd_param[n] = 0
+#define MAX_RETRY_COUNT 3
+#define NUM_CMD_RESPONSE_DATA 3
+
+#define IO96B0_PLL_A_MASK BIT(0)
+#define IO96B0_PLL_B_MASK BIT(1)
+#define IO96B1_PLL_A_MASK BIT(2)
+#define IO96B1_PLL_B_MASK BIT(3)
+
+/* supported DDR type list */
+static const char *ddr_type_list[7] = {
+ "DDR4", "DDR5", "DDR5_RDIMM", "LPDDR4", "LPDDR5", "QDRIV", "UNKNOWN"
+};
+
+/* Define an enumeration for ECC error types */
+enum ecc_error_type {
+ SINGLE_BIT_ERROR = 0, /* 0b0000 */
+ MULTIPLE_SINGLE_BIT_ERRORS = 1, /* 0b0001 */
+ DOUBLE_BIT_ERROR = 2, /* 0b0010 */
+ MULTIPLE_DOUBLE_BIT_ERRORS = 3, /* 0b0011 */
+ SINGLE_BIT_ERROR_SCRUBBING = 8, /* 0b1000 */
+ WRITE_LINK_SINGLE_BIT_ERROR = 9, /* 0b1001 */
+ WRITE_LINK_DOUBLE_BIT_ERROR = 10, /* 0b1010 */
+ READ_LINK_SINGLE_BIT_ERROR = 11, /* 0b1011 */
+ READ_LINK_DOUBLE_BIT_ERROR = 12, /* 0b1100 */
+ READ_MODIFY_WRITE_DOUBLE_BIT_ERROR = 13 /* 0b1101 */
+};
+
+/*
+ * ecc error info
+ *
+ * @ip_type: The IP type of the interface that produced the ECC interrupt.
+ * @instance_id: The instance ID of the interface that produced the ECC interrupt.
+ * @ecc_err_source_id: The source ID associated with the ECC event.
+ * @ecc_err_type: The ECC error type of the ECC event.
+ * @ecc_err_addr_upper: Upper 6 bits of the address of the read data that caused the ECC event.
+ * @ecc_err_addr_lower: Lower 32 bits of the address of the read data that caused the ECC event.
+ */
+struct ecc_err_info {
+ u32 ip_type;
+ u32 instance_id;
+ u32 source_id;
+ enum ecc_error_type err_type;
+ u32 addr_upper;
+ u32 addr_lower;
+};
+
+static int is_ddr_csr_clkgen_locked(u8 io96b_pll)
+{
+ int ret = 0;
+ const char *pll_names[MAX_IO96B_SUPPORTED][2] = {
+ {"io96b_0 clkgenA", "io96b_0 clkgenB"},
+ {"io96b_1 clkgenA", "io96b_1 clkgenB"}
+ };
+ u32 masks[MAX_IO96B_SUPPORTED][2] = {
+ {IO96B0_PLL_A_MASK, IO96B0_PLL_B_MASK},
+ {IO96B1_PLL_A_MASK, IO96B1_PLL_B_MASK}
+ };
+ u32 lock_masks[MAX_IO96B_SUPPORTED] = {
+ DDR_CSR_CLKGEN_LOCKED_IO96B0_MASK,
+ DDR_CSR_CLKGEN_LOCKED_IO96B1_MASK
+ };
+
+ for (int i = 0; i < MAX_IO96B_SUPPORTED ; i++) {
+ /* Check for PLL_A */
+ if (io96b_pll & masks[i][0]) {
+ ret = wait_for_bit_le32((const void *)(ECC_INTSTATUS_SERR), lock_masks[i],
+ true, TIMEOUT, false);
+
+ if (ret) {
+ debug("%s: ddr csr %s locked is timeout\n",
+ __func__, pll_names[i][0]);
+ goto err;
+ } else {
+ debug("%s: ddr csr %s is successfully locked\n",
+ __func__, pll_names[i][0]);
+ }
+ }
+
+ /* Check for PLL_B */
+ if (io96b_pll & masks[i][1]) {
+ ret = wait_for_bit_le32((const void *)(ECC_INISTATUS_DERR), lock_masks[i],
+ true, TIMEOUT, false);
+
+ if (ret) {
+ debug("%s: ddr csr %s locked is timeout\n",
+ __func__, pll_names[i][1]);
+ goto err;
+ } else {
+ debug("%s: ddr csr %s is successfully locked\n",
+ __func__, pll_names[i][1]);
+ }
+ }
+ }
+
+err:
+ return ret;
+}
+
+/*
+ * Mailbox request function
+ * This function will send the request to IOSSM mailbox and wait for response return
+ *
+ * @io96b_csr_addr: CSR address for the target IO96B
+ * @req: Structure contain command request for IOSSM mailbox command
+ * @resp_data_len: User desire extra response data fields other than
+ * CMD_RESPONSE_DATA_SHORT field on CMD_RESPONSE_STATUS
+ * @resp: Structure contain responses returned from the requested IOSSM
+ * mailbox command
+ */
+int io96b_mb_req(phys_addr_t io96b_csr_addr, struct io96b_mb_req req,
+ u32 resp_data_len, struct io96b_mb_resp *resp)
+{
+ int i, ret;
+ u32 cmd_req;
+
+ if (!resp) {
+ ret = -EINVAL;
+ goto err;
+ }
+
+ /* Zero initialization for responses */
+ resp->cmd_resp_status = 0;
+
+ /* Ensure CMD_REQ is cleared before write any command request */
+ ret = wait_for_bit_le32((const void *)(io96b_csr_addr + IOSSM_CMD_REQ_OFFSET),
+ GENMASK(31, 0), false, TIMEOUT, false);
+ if (ret) {
+ printf("%s: Timeout of waiting DDR mailbox ready to be functioned!\n",
+ __func__);
+ goto err;
+ }
+
+ /* Write CMD_PARAM_* */
+ for (i = 0; i < NUM_CMD_PARAM ; i++) {
+ switch (i) {
+ case 0:
+ if (req.cmd_param[0])
+ writel(req.cmd_param[0], io96b_csr_addr + IOSSM_CMD_PARAM_0_OFFSET);
+ break;
+ case 1:
+ if (req.cmd_param[1])
+ writel(req.cmd_param[1], io96b_csr_addr + IOSSM_CMD_PARAM_1_OFFSET);
+ break;
+ case 2:
+ if (req.cmd_param[2])
+ writel(req.cmd_param[2], io96b_csr_addr + IOSSM_CMD_PARAM_2_OFFSET);
+ break;
+ case 3:
+ if (req.cmd_param[3])
+ writel(req.cmd_param[3], io96b_csr_addr + IOSSM_CMD_PARAM_3_OFFSET);
+ break;
+ case 4:
+ if (req.cmd_param[4])
+ writel(req.cmd_param[4], io96b_csr_addr + IOSSM_CMD_PARAM_4_OFFSET);
+ break;
+ case 5:
+ if (req.cmd_param[5])
+ writel(req.cmd_param[5], io96b_csr_addr + IOSSM_CMD_PARAM_5_OFFSET);
+ break;
+ case 6:
+ if (req.cmd_param[6])
+ writel(req.cmd_param[6], io96b_csr_addr + IOSSM_CMD_PARAM_6_OFFSET);
+ break;
+ }
+ }
+
+ /* Write CMD_REQ (IP_TYPE, IP_INSTANCE_ID, CMD_TYPE and CMD_OPCODE) */
+ cmd_req = FIELD_PREP(CMD_TARGET_IP_TYPE_MASK, req.ip_type) |
+ FIELD_PREP(CMD_TARGET_IP_INSTANCE_ID_MASK, req.ip_id) |
+ FIELD_PREP(CMD_TYPE_MASK, req.usr_cmd_type) |
+ FIELD_PREP(CMD_OPCODE_MASK, req.usr_cmd_opcode);
+ writel(cmd_req, io96b_csr_addr + IOSSM_CMD_REQ_OFFSET);
+
+ debug("%s: Write 0x%x to IOSSM_CMD_REQ_OFFSET 0x%llx\n", __func__, cmd_req,
+ io96b_csr_addr + IOSSM_CMD_REQ_OFFSET);
+
+ /* Read CMD_RESPONSE_READY in CMD_RESPONSE_STATUS */
+ ret = wait_for_bit_le32((const void *)(io96b_csr_addr + IOSSM_CMD_RESPONSE_STATUS_OFFSET),
+ IOSSM_STATUS_COMMAND_RESPONSE_READY, true, TIMEOUT, false);
+
+ /* read CMD_RESPONSE_STATUS */
+ resp->cmd_resp_status = readl(io96b_csr_addr + IOSSM_CMD_RESPONSE_STATUS_OFFSET);
+
+ debug("%s: CMD_RESPONSE_STATUS 0x%llx: 0x%x\n", __func__, io96b_csr_addr +
+ IOSSM_CMD_RESPONSE_STATUS_OFFSET, resp->cmd_resp_status);
+
+ if (ret) {
+ printf("%s: CMD_RESPONSE ERROR:\n", __func__);
+
+ printf("%s: STATUS_GENERAL_ERROR: 0x%lx\n", __func__,
+ IOSSM_STATUS_GENERAL_ERROR(resp->cmd_resp_status));
+ printf("%s: STATUS_CMD_RESPONSE_ERROR: 0x%lx\n", __func__,
+ IOSSM_STATUS_CMD_RESPONSE_ERROR(resp->cmd_resp_status));
+ goto err;
+ }
+
+ /* read CMD_RESPONSE_DATA_* */
+ for (i = 0; i < resp_data_len; i++) {
+ switch (i) {
+ case 0:
+ resp->cmd_resp_data[i] =
+ readl(io96b_csr_addr + IOSSM_CMD_RESPONSE_DATA_0_OFFSET);
+
+ debug("%s: IOSSM_CMD_RESPONSE_DATA_0_OFFSET 0x%llx: 0x%x\n", __func__,
+ io96b_csr_addr + IOSSM_CMD_RESPONSE_DATA_0_OFFSET,
+ resp->cmd_resp_data[i]);
+ break;
+ case 1:
+ resp->cmd_resp_data[i] =
+ readl(io96b_csr_addr + IOSSM_CMD_RESPONSE_DATA_1_OFFSET);
+
+ debug("%s: IOSSM_CMD_RESPONSE_DATA_1_OFFSET 0x%llx: 0x%x\n", __func__,
+ io96b_csr_addr + IOSSM_CMD_RESPONSE_DATA_1_OFFSET,
+ resp->cmd_resp_data[i]);
+ break;
+ case 2:
+ resp->cmd_resp_data[i] =
+ readl(io96b_csr_addr + IOSSM_CMD_RESPONSE_DATA_2_OFFSET);
+
+ debug("%s: IOSSM_CMD_RESPONSE_DATA_2_OFFSET 0x%llx: 0x%x\n", __func__,
+ io96b_csr_addr + IOSSM_CMD_RESPONSE_DATA_2_OFFSET,
+ resp->cmd_resp_data[i]);
+ break;
+ default:
+ resp->cmd_resp_data[i] = 0;
+ printf("%s: Invalid response data\n", __func__);
+ }
+ }
+
+ /* write CMD_RESPONSE_READY = 0 */
+ clrbits_le32((u32 *)(uintptr_t)(io96b_csr_addr + IOSSM_CMD_RESPONSE_STATUS_OFFSET),
+ IOSSM_STATUS_COMMAND_RESPONSE_READY);
+
+ debug("%s: After clear CMD_RESPONSE_READY bit: 0x%llx: 0x%x\n", __func__,
+ io96b_csr_addr + IOSSM_CMD_RESPONSE_STATUS_OFFSET,
+ readl(io96b_csr_addr + IOSSM_CMD_RESPONSE_STATUS_OFFSET));
+
+err:
+ return ret;
+}
+
+/*
+ * Initial function to be called to set memory interface IP type and instance ID
+ * IP type and instance ID need to be determined before sending mailbox command
+ */
+void io96b_mb_init(struct io96b_info *io96b_ctrl)
+{
+ int i, j;
+ u32 mem_intf_info_0, mem_intf_info_1;
+
+ debug("%s: num_instance %d\n", __func__, io96b_ctrl->num_instance);
+
+ for (i = 0; i < io96b_ctrl->num_instance; i++) {
+ debug("%s: get memory interface IO96B %d\n", __func__, i);
+ io96b_ctrl->io96b[i].mb_ctrl.num_mem_interface = 0;
+
+ mem_intf_info_0 = readl(io96b_ctrl->io96b[i].io96b_csr_addr +
+ IOSSM_MEM_INTF_INFO_0_OFFSET);
+ mem_intf_info_1 = readl(io96b_ctrl->io96b[i].io96b_csr_addr +
+ IOSSM_MEM_INTF_INFO_1_OFFSET);
+
+ io96b_ctrl->io96b[i].mb_ctrl.ip_type[0] = FIELD_GET(INTF_IP_TYPE_MASK,
+ mem_intf_info_0);
+ io96b_ctrl->io96b[i].mb_ctrl.ip_id[0] = FIELD_GET(INTF_INSTANCE_ID_MASK,
+ mem_intf_info_0);
+ io96b_ctrl->io96b[i].mb_ctrl.ip_type[1] = FIELD_GET(INTF_IP_TYPE_MASK,
+ mem_intf_info_1);
+ io96b_ctrl->io96b[i].mb_ctrl.ip_id[1] = FIELD_GET(INTF_INSTANCE_ID_MASK,
+ mem_intf_info_1);
+
+ for (j = 0; j < MAX_MEM_INTERFACE_SUPPORTED; j++) {
+ if (io96b_ctrl->io96b[i].mb_ctrl.ip_type[j]) {
+ io96b_ctrl->io96b[i].mb_ctrl.num_mem_interface++;
+
+ debug("%s: IO96B %d mem_interface %d: ip_type_ret: 0x%x\n",
+ __func__, i, j, io96b_ctrl->io96b[i].mb_ctrl.ip_type[j]);
+ debug("%s: IO96B %d mem_interface %d: instance_id_ret: 0x%x\n",
+ __func__, i, j, io96b_ctrl->io96b[i].mb_ctrl.ip_id[j]);
+ }
+ }
+
+ debug("%s: IO96B %d: num_mem_interface: 0x%x\n", __func__, i,
+ io96b_ctrl->io96b[i].mb_ctrl.num_mem_interface);
+ }
+}
+
+int io96b_cal_status(phys_addr_t addr)
+{
+ u32 cal_success, cal_fail;
+ phys_addr_t status_addr = addr + IOSSM_STATUS_OFFSET;
+ u32 start = get_timer(0);
+
+ do {
+ if (get_timer(start) > TIMEOUT_60000MS) {
+ printf("%s: SDRAM calibration for IO96B instance 0x%llx timeout!\n",
+ __func__, status_addr);
+ hang();
+ }
+
+ udelay(1);
+ schedule();
+
+ /* Polling until getting any calibration result */
+ cal_success = readl(status_addr) & IOSSM_STATUS_CAL_SUCCESS;
+ cal_fail = readl(status_addr) & IOSSM_STATUS_CAL_FAIL;
+ } while (!cal_success && !cal_fail);
+
+ debug("%s: Calibration for IO96B instance 0x%llx done at %ld msec!\n",
+ __func__, status_addr, get_timer(start));
+
+ if (cal_success && !cal_fail)
+ return 0;
+ else
+ return -EPERM;
+}
+
+void init_mem_cal(struct io96b_info *io96b_ctrl)
+{
+ int count, i, ret;
+
+ /* Initialize overall calibration status */
+ io96b_ctrl->overall_cal_status = false;
+
+ if (io96b_ctrl->ckgen_lock) {
+ ret = is_ddr_csr_clkgen_locked(io96b_ctrl->io96b_pll);
+ if (ret) {
+ printf("%s: iossm IO96B ckgena_lock is not locked\n", __func__);
+ hang();
+ }
+ }
+
+ /* Check initial calibration status for the assigned IO96B */
+ count = 0;
+ for (i = 0; i < io96b_ctrl->num_instance; i++) {
+ ret = io96b_cal_status(io96b_ctrl->io96b[i].io96b_csr_addr);
+ if (ret) {
+ io96b_ctrl->io96b[i].cal_status = false;
+
+ printf("%s: Initial DDR calibration IO96B_%d failed %d\n", __func__,
+ i, ret);
+
+ hang();
+ }
+
+ io96b_ctrl->io96b[i].cal_status = true;
+
+ printf("%s: Initial DDR calibration IO96B_%d succeed\n", __func__, i);
+
+ count++;
+ }
+
+ if (count == io96b_ctrl->num_instance)
+ io96b_ctrl->overall_cal_status = true;
+}
+
+int get_mem_technology(struct io96b_info *io96b_ctrl)
+{
+ int i, j, ret = 0;
+ u32 mem_technology_intf;
+ u8 ddr_type_ret;
+
+ u32 mem_technology_intf_offset[MAX_MEM_INTERFACE_SUPPORTED] = {
+ IOSSM_MEM_TECHNOLOGY_INTF0_OFFSET,
+ IOSSM_MEM_TECHNOLOGY_INTF1_OFFSET
+ };
+
+ /* Initialize ddr type */
+ io96b_ctrl->ddr_type = ddr_type_list[6];
+
+ /* Get and ensure all memory interface(s) same DDR type */
+ for (i = 0; i < io96b_ctrl->num_instance; i++) {
+ for (j = 0; j < io96b_ctrl->io96b[i].mb_ctrl.num_mem_interface; j++) {
+ mem_technology_intf = readl(io96b_ctrl->io96b[i].io96b_csr_addr +
+ mem_technology_intf_offset[j]);
+
+ ddr_type_ret = FIELD_GET(INTF_DDR_TYPE_MASK, mem_technology_intf);
+
+ if (!strcmp(io96b_ctrl->ddr_type, "UNKNOWN"))
+ io96b_ctrl->ddr_type = ddr_type_list[ddr_type_ret];
+
+ if (ddr_type_list[ddr_type_ret] != io96b_ctrl->ddr_type) {
+ printf("%s: Mismatch DDR type on IO96B_%d\n", __func__, i);
+
+ ret = -EINVAL;
+ goto err;
+ }
+ }
+ }
+
+err:
+ return ret;
+}
+
+int get_mem_width_info(struct io96b_info *io96b_ctrl)
+{
+ int i, j, ret = 0;
+ u32 mem_width_info;
+ u16 memory_size, total_memory_size = 0;
+
+ u32 mem_total_capacity_intf_offset[MAX_MEM_INTERFACE_SUPPORTED] = {
+ IOSSM_MEM_TOTAL_CAPACITY_INTF0_OFFSET,
+ IOSSM_MEM_TOTAL_CAPACITY_INTF1_OFFSET
+ };
+
+ /* Get all memory interface(s) total memory size on all instance(s) */
+ for (i = 0; i < io96b_ctrl->num_instance; i++) {
+ memory_size = 0;
+ for (j = 0; j < io96b_ctrl->io96b[i].mb_ctrl.num_mem_interface; j++) {
+ mem_width_info = readl(io96b_ctrl->io96b[i].io96b_csr_addr +
+ mem_total_capacity_intf_offset[j]);
+
+ memory_size = memory_size +
+ FIELD_GET(INTF_CAPACITY_GBITS_MASK, mem_width_info);
+ }
+
+ if (!memory_size) {
+ printf("%s: Failed to get valid memory size\n", __func__);
+ ret = -EINVAL;
+ goto err;
+ }
+
+ io96b_ctrl->io96b[i].size = memory_size;
+
+ total_memory_size = total_memory_size + memory_size;
+ }
+
+ if (!total_memory_size) {
+ printf("%s: Failed to get valid memory size\n", __func__);
+ ret = -EINVAL;
+ }
+
+ io96b_ctrl->overall_size = total_memory_size;
+
+err:
+ return ret;
+}
+
+int ecc_enable_status(struct io96b_info *io96b_ctrl)
+{
+ int i, j, ret = 0;
+ u32 ecc_enable_intf;
+ bool ecc_stat, ecc_stat_set = false;
+
+ u32 ecc_enable_intf_offset[MAX_MEM_INTERFACE_SUPPORTED] = {
+ IOSSM_ECC_ENABLE_INTF0_OFFSET,
+ IOSSM_ECC_ENABLE_INTF1_OFFSET
+ };
+
+ /* Initialize ECC status */
+ io96b_ctrl->ecc_status = false;
+
+ /* Get and ensure all memory interface(s) same ECC status */
+ for (i = 0; i < io96b_ctrl->num_instance; i++) {
+ for (j = 0; j < io96b_ctrl->io96b[i].mb_ctrl.num_mem_interface; j++) {
+ ecc_enable_intf = readl(io96b_ctrl->io96b[i].io96b_csr_addr +
+ ecc_enable_intf_offset[j]);
+
+ ecc_stat = (FIELD_GET(INTF_ECC_ENABLE_TYPE_MASK, ecc_enable_intf)
+ == 0) ? false : true;
+
+ if (!ecc_stat_set) {
+ io96b_ctrl->ecc_status = ecc_stat;
+ ecc_stat_set = true;
+ }
+
+ if (ecc_stat != io96b_ctrl->ecc_status) {
+ printf("%s: Mismatch DDR ECC status on IO96B_%d\n", __func__, i);
+
+ ret = -EINVAL;
+ goto err;
+ }
+ }
+ }
+
+ debug("%s: ECC enable status: %d\n", __func__, io96b_ctrl->ecc_status);
+
+err:
+ return ret;
+}
+
+bool is_double_bit_error(enum ecc_error_type err_type)
+{
+ switch (err_type) {
+ case DOUBLE_BIT_ERROR:
+ case MULTIPLE_DOUBLE_BIT_ERRORS:
+ case WRITE_LINK_DOUBLE_BIT_ERROR:
+ case READ_LINK_DOUBLE_BIT_ERROR:
+ case READ_MODIFY_WRITE_DOUBLE_BIT_ERROR:
+ return true;
+
+ default:
+ return false;
+ }
+}
+
+bool ecc_interrupt_status(struct io96b_info *io96b_ctrl)
+{
+ int i, j;
+ u32 ecc_err_status;
+ u16 ecc_err_counter;
+ bool ecc_error_flag = false;
+
+ /* Get ECC double-bit error status */
+ for (i = 0; i < io96b_ctrl->num_instance; i++) {
+ ecc_err_status = readl(io96b_ctrl->io96b[i].io96b_csr_addr +
+ IOSSM_ECC_ERR_STATUS_OFFSET);
+ ecc_err_counter = FIELD_GET(ECC_ERR_COUNTER_MASK, ecc_err_status);
+ debug("%s: ECC error number detected on IO96B_%d: %d\n",
+ __func__, i, ecc_err_counter);
+
+ if (ecc_err_counter != 0) {
+ phys_addr_t address;
+ u32 ecc_err_data;
+ struct ecc_err_info err_info;
+
+ address = io96b_ctrl->io96b[i].io96b_csr_addr +
+ IOSSM_ECC_ERR_DATA_START_OFFSET;
+
+ for (j = 0; j < ecc_err_counter && j < MAX_ECC_ERR_INFO_COUNT; j++) {
+ ecc_err_data = readl(address);
+ err_info.err_type = FIELD_GET(ECC_ERR_TYPE_MASK,
+ ecc_err_data);
+ err_info.ip_type = FIELD_GET(ECC_ERR_IP_TYPE_MASK,
+ ecc_err_data);
+ err_info.instance_id = FIELD_GET(ECC_ERR_INSTANCE_ID_MASK,
+ ecc_err_data);
+ err_info.source_id = FIELD_GET(ECC_ERR_SOURCE_ID_MASK,
+ ecc_err_data);
+ err_info.addr_upper = FIELD_GET(ECC_ERR_ADDR_UPPER_MASK,
+ ecc_err_data);
+ err_info.addr_lower = readl(address + sizeof(u32));
+
+ debug("%s: ECC double-bit error detected on IO96B_%d:\n",
+ __func__, i);
+ debug("- error info address :0x%llx\n", address);
+ debug("- error ip type: %d\n", err_info.ip_type);
+ debug("- error instance id: %d\n", err_info.instance_id);
+ debug("- error source id: %d\n", err_info.source_id);
+ debug("- error type: %d\n", err_info.err_type);
+ debug("- error address upper: 0x%x\n", err_info.addr_upper);
+ debug("- error address lower: 0x%x\n", err_info.addr_lower);
+
+ if (is_double_bit_error(err_info.err_type)) {
+ if (!ecc_error_flag)
+ ecc_error_flag = true;
+ }
+
+ address += sizeof(u32) * 2;
+ }
+ }
+ }
+
+ if (ecc_error_flag)
+ printf("\n%s: ECC double-bit error detected!\n", __func__);
+
+ return ecc_error_flag;
+}
+
+int bist_mem_init_start(struct io96b_info *io96b_ctrl)
+{
+ struct io96b_mb_req usr_req;
+ struct io96b_mb_resp usr_resp;
+ int i, j, n, ret = 0;
+ bool bist_start, bist_success;
+ u32 mem_init_status_intf, start;
+
+ u32 mem_init_status_offset[MAX_MEM_INTERFACE_SUPPORTED] = {
+ IOSSM_MEM_INIT_STATUS_INTF0_OFFSET,
+ IOSSM_MEM_INIT_STATUS_INTF1_OFFSET
+ };
+
+ /* Full memory initialization BIST performed on all memory interface(s) */
+ for (i = 0; i < io96b_ctrl->num_instance; i++) {
+ for (j = 0; j < io96b_ctrl->io96b[i].mb_ctrl.num_mem_interface; j++) {
+ bist_start = false;
+ bist_success = false;
+
+ /* Start memory initialization BIST on full memory address */
+ IO96B_MB_REQ_SETUP(io96b_ctrl->io96b[i].mb_ctrl.ip_type[j],
+ io96b_ctrl->io96b[i].mb_ctrl.ip_id[j],
+ CMD_TRIG_CONTROLLER_OP, BIST_MEM_INIT_START,
+ BIST_FULL_MEM);
+
+ ret = io96b_mb_req(io96b_ctrl->io96b[i].io96b_csr_addr,
+ usr_req, 0, &usr_resp);
+ if (ret)
+ goto err;
+
+ bist_start = IOSSM_CMD_RESPONSE_DATA_SHORT(usr_resp.cmd_resp_status)
+ & BIT(0);
+
+ if (!bist_start) {
+ printf("%s: Failed to initialize memory on IO96B_%d\n", __func__,
+ i);
+ printf("%s: BIST_MEM_INIT_START Error code 0x%lx\n", __func__,
+ IOSSM_STATUS_CMD_RESPONSE_ERROR(usr_resp.cmd_resp_status));
+
+ ret = -EINVAL;
+ goto err;
+ }
+
+ /* Polling for the initiated memory initialization BIST status */
+ start = get_timer(0);
+ while (!bist_success) {
+ udelay(1);
+
+ mem_init_status_intf = readl(io96b_ctrl->io96b[i].io96b_csr_addr +
+ mem_init_status_offset[j]);
+
+ bist_success = FIELD_GET(INTF_BIST_STATUS_MASK,
+ mem_init_status_intf);
+
+ if (!bist_success && (get_timer(start) > TIMEOUT)) {
+ printf("%s: Timeout initialize memory on IO96B_%d\n",
+ __func__, i);
+ printf("%s: BIST_MEM_INIT_STATUS Error code 0x%lx\n",
+ __func__,
+ IOSSM_STATUS_CMD_RESPONSE_ERROR(usr_resp.cmd_resp_status));
+
+ ret = -ETIMEDOUT;
+ goto err;
+ }
+ }
+ }
+
+ debug("%s: Memory initialized successfully on IO96B_%d\n", __func__, i);
+ }
+
+err:
+ return ret;
+}
diff --git a/drivers/ddr/altera/iossm_mailbox.h b/drivers/ddr/altera/iossm_mailbox.h
new file mode 100644
index 0000000..6f79478
--- /dev/null
+++ b/drivers/ddr/altera/iossm_mailbox.h
@@ -0,0 +1,136 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Copyright (C) 2025 Altera Corporation <www.altera.com>
+ *
+ */
+
+#define MAX_IO96B_SUPPORTED 2
+#define MAX_MEM_INTERFACE_SUPPORTED 2
+#define NUM_CMD_RESPONSE_DATA 3
+#define NUM_CMD_PARAM 7
+
+/* supported mailbox command type */
+enum iossm_mailbox_cmd_type {
+ CMD_NOP,
+ CMD_GET_SYS_INFO,
+ CMD_GET_MEM_INFO,
+ CMD_GET_MEM_CAL_INFO,
+ CMD_TRIG_CONTROLLER_OP,
+ CMD_TRIG_MEM_CAL_OP
+};
+
+/* supported mailbox command opcode */
+enum iossm_mailbox_cmd_opcode {
+ ECC_ENABLE_SET = 0x0101,
+ ECC_INTERRUPT_MASK = 0x0105,
+ ECC_WRITEBACK_ENABLE = 0x0106,
+ ECC_INJECT_ERROR = 0x0109,
+ ECC_SCRUB_MODE_0_START = 0x0202,
+ ECC_SCRUB_MODE_1_START = 0x0203,
+ BIST_STANDARD_MODE_START = 0x0301,
+ BIST_MEM_INIT_START = 0x0303,
+ BIST_SET_DATA_PATTERN_UPPER = 0x0305,
+ BIST_SET_DATA_PATTERN_LOWER = 0x0306,
+ TRIG_MEM_CAL = 0x000a
+};
+
+/*
+ * IOSSM mailbox required information
+ *
+ * @num_mem_interface: Number of memory interfaces instantiated
+ * @ip_type: IP type implemented on the IO96B
+ * @ip_instance_id: IP identifier for every IP instance implemented on the IO96B
+ */
+struct io96b_mb_ctrl {
+ u32 num_mem_interface;
+ u32 ip_type[2];
+ u32 ip_id[2];
+};
+
+/* CMD_REQ Register Definition */
+#define CMD_TARGET_IP_TYPE_MASK GENMASK(31, 29)
+#define CMD_TARGET_IP_INSTANCE_ID_MASK GENMASK(28, 24)
+#define CMD_TYPE_MASK GENMASK(23, 16)
+#define CMD_OPCODE_MASK GENMASK(15, 0)
+
+/*
+ * IOSSM mailbox request
+ * @ip_type: IP type for the specified memory interface
+ * @ip_id: IP instance ID for the specified memory interface
+ * @usr_cmd_type: User desire IOSSM mailbox command type
+ * @usr_cmd_opcode: User desire IOSSM mailbox command opcode
+ * @cmd_param_*: Parameters (if applicable) for the requested IOSSM mailbox command
+ */
+struct io96b_mb_req {
+ u32 ip_type;
+ u32 ip_id;
+ u32 usr_cmd_type;
+ u32 usr_cmd_opcode;
+ u32 cmd_param[NUM_CMD_PARAM];
+};
+
+/*
+ * IOSSM mailbox response outputs
+ *
+ * @cmd_resp_status: Command Interface status
+ * @cmd_resp_data_*: More spaces for command response
+ */
+struct io96b_mb_resp {
+ u32 cmd_resp_status;
+ u32 cmd_resp_data[NUM_CMD_RESPONSE_DATA];
+};
+
+/*
+ * IO96B instance specific information
+ *
+ * @size: Memory size
+ * @io96b_csr_addr: IO96B instance CSR address
+ * @cal_status: IO96B instance calibration status
+ * @mb_ctrl: IOSSM mailbox required information
+ */
+struct io96b_instance {
+ u16 size;
+ phys_addr_t io96b_csr_addr;
+ bool cal_status;
+ struct io96b_mb_ctrl mb_ctrl;
+};
+
+/*
+ * Overall IO96B instance(s) information
+ *
+ * @num_instance: Number of instance(s) assigned to HPS
+ * @overall_cal_status: Overall calibration status for all IO96B instance(s)
+ * @ddr_type: DDR memory type
+ * @ecc_status: ECC enable status (false = disabled, true = enabled)
+ * @overall_size: Total DDR memory size
+ * @io96b[]: IO96B instance specific information
+ * @ckgen_lock: IO96B GEN PLL lock (false = not locked, true = locked)
+ * @num_port: Number of IO96B port.
+ * @io96b_pll: Selected IO96B PLL. Example bit 0: EMIF0 PLL A selected,
+ * bit 1: EMIF0 PLL B selected, bit 2 - EMIF1 PLL A selected,
+ * bit 3: EMIF1 PLL B selected
+ */
+struct io96b_info {
+ u8 num_instance;
+ bool overall_cal_status;
+ const char *ddr_type;
+ bool ecc_status;
+ u16 overall_size;
+ struct io96b_instance io96b[MAX_IO96B_SUPPORTED];
+ bool ckgen_lock;
+ u8 num_port;
+ u8 io96b_pll;
+};
+
+int io96b_mb_req(phys_addr_t io96b_csr_addr, struct io96b_mb_req req,
+ u32 resp_data_len, struct io96b_mb_resp *resp);
+
+/* Supported IOSSM mailbox function */
+void io96b_mb_init(struct io96b_info *io96b_ctrl);
+int io96b_cal_status(phys_addr_t addr);
+void init_mem_cal(struct io96b_info *io96b_ctrl);
+int get_mem_technology(struct io96b_info *io96b_ctrl);
+int get_mem_width_info(struct io96b_info *io96b_ctrl);
+int ecc_enable_status(struct io96b_info *io96b_ctrl);
+int bist_mem_init_start(struct io96b_info *io96b_ctrl);
+bool ecc_interrupt_status(struct io96b_info *io96b_ctrl);
diff --git a/drivers/ddr/altera/sdram_agilex5.c b/drivers/ddr/altera/sdram_agilex5.c
new file mode 100644
index 0000000..801a6bb
--- /dev/null
+++ b/drivers/ddr/altera/sdram_agilex5.c
@@ -0,0 +1,420 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (C) 2025 Altera Corporation <www.altera.com>
+ *
+ */
+
+#include <stdlib.h>
+#include <div64.h>
+#include <dm.h>
+#include <errno.h>
+#include <fdtdec.h>
+#include <hang.h>
+#include <log.h>
+#include <ram.h>
+#include <reset.h>
+#include <wait_bit.h>
+#include <wdt.h>
+#include <linux/bitfield.h>
+#include <linux/sizes.h>
+#include <asm/arch/firewall.h>
+#include <asm/arch/reset_manager.h>
+#include <asm/arch/system_manager.h>
+#include <asm/global_data.h>
+#include <asm/io.h>
+#include "iossm_mailbox.h"
+#include "sdram_soc64.h"
+
+DECLARE_GLOBAL_DATA_PTR;
+
+/* MPFE NOC registers */
+#define F2SDRAM_SIDEBAND_FLAGOUTSET0 0x50
+#define F2SDRAM_SIDEBAND_FLAGOUTSTATUS0 0x58
+#define SIDEBANDMGR_FLAGOUTSET0_REG SOCFPGA_F2SDRAM_MGR_ADDRESS +\
+ F2SDRAM_SIDEBAND_FLAGOUTSET0
+#define SIDEBANDMGR_FLAGOUTSTATUS0_REG SOCFPGA_F2SDRAM_MGR_ADDRESS +\
+ F2SDRAM_SIDEBAND_FLAGOUTSTATUS0
+#define BOOT_SCRATCH_COLD3_REG (socfpga_get_sysmgr_addr() +\
+ SYSMGR_SOC64_BOOT_SCRATCH_COLD3)
+#define PORT_EMIF_CONFIG_OFFSET 4
+#define EMIF_PLL_MASK GENMASK(19, 16)
+
+#define IO96B0_DUAL_PORT_MASK BIT(0)
+#define IO96B0_DUAL_EMIF_MASK BIT(1)
+
+#define FIREWALL_MPFE_SCR_IO96B0_REG 0x18000d00
+#define FIREWALL_MPFE_SCR_IO96B1_REG 0x18000d04
+#define FIREWALL_MPFE_NOC_CSR_REG 0x18000d08
+
+#define MEMORY_BANK_MAX_COUNT 3
+
+/* Reset type */
+enum reset_type {
+ POR_RESET,
+ WARM_RESET,
+ COLD_RESET,
+ NCONFIG,
+ JTAG_CONFIG,
+ RSU_RECONFIG
+};
+
+phys_addr_t io96b_csr_reg_addr[] = {
+ 0x18400000, /* IO96B_0 CSR registers address */
+ 0x18800000 /* IO96B_1 CSR registers address */
+};
+
+struct dram_bank_info_s {
+ phys_addr_t start;
+ phys_size_t max_size;
+};
+
+struct dram_bank_info_s dram_bank_info[MEMORY_BANK_MAX_COUNT] = {
+ {0x80000000, 0x80000000}, /* Memory Bank 0 */
+ {0x880000000, 0x780000000}, /* Memory Bank 1 */
+ {0x8800000000, 0x7800000000} /* Memory Bank 2 */
+};
+
+static enum reset_type get_reset_type(u32 reg)
+{
+ return FIELD_GET(ALT_SYSMGR_SCRATCH_REG_3_DDR_RESET_TYPE_MASK, reg);
+}
+
+static void update_io96b_assigned_to_hps(bool dual_port_flag, bool dual_emif_flag)
+{
+ clrsetbits_le32(BOOT_SCRATCH_COLD3_REG,
+ ALT_SYSMGR_SCRATCH_REG_3_DDR_PORT_EMIF_INFO_MASK,
+ FIELD_PREP(ALT_SYSMGR_SCRATCH_REG_3_DDR_PORT_INFO_MASK, dual_port_flag) |
+ FIELD_PREP(ALT_SYSMGR_SCRATCH_REG_3_DDR_EMIF_INFO_MASK, dual_emif_flag));
+
+ debug("%s: update dual port dual emif info: 0x%x\n", __func__,
+ readl(BOOT_SCRATCH_COLD3_REG));
+}
+
+static void set_mpfe_config(void)
+{
+ /* Set mpfe_lite_intfcsel */
+ setbits_le32(socfpga_get_sysmgr_addr() + SYSMGR_SOC64_MPFE_CONFIG, BIT(2));
+
+ /* Set mpfe_lite_active */
+ setbits_le32(socfpga_get_sysmgr_addr() + SYSMGR_SOC64_MPFE_CONFIG, BIT(8));
+
+ debug("%s: mpfe_config: 0x%x\n", __func__,
+ readl(socfpga_get_sysmgr_addr() + SYSMGR_SOC64_MPFE_CONFIG));
+}
+
+static bool is_ddr_init_hang(void)
+{
+ u32 reg = readl(socfpga_get_sysmgr_addr() +
+ SYSMGR_SOC64_BOOT_SCRATCH_POR0);
+
+ debug("%s: 0x%x\n", __func__, reg);
+
+ if (reg & ALT_SYSMGR_SCRATCH_REG_POR_0_DDR_PROGRESS_MASK)
+ return true;
+
+ return false;
+}
+
+static void ddr_init_inprogress(bool start)
+{
+ if (start)
+ setbits_le32(socfpga_get_sysmgr_addr() +
+ SYSMGR_SOC64_BOOT_SCRATCH_POR0,
+ ALT_SYSMGR_SCRATCH_REG_POR_0_DDR_PROGRESS_MASK);
+ else
+ clrbits_le32(socfpga_get_sysmgr_addr() +
+ SYSMGR_SOC64_BOOT_SCRATCH_POR0,
+ ALT_SYSMGR_SCRATCH_REG_POR_0_DDR_PROGRESS_MASK);
+}
+
+static void populate_ddr_handoff(struct udevice *dev, struct io96b_info *io96b_ctrl)
+{
+ struct altera_sdram_plat *plat = dev_get_plat(dev);
+ int i;
+ u32 len = SOC64_HANDOFF_SDRAM_LEN;
+ u32 handoff_table[len];
+
+ /* Read handoff for DDR configuration */
+ socfpga_handoff_read((void *)SOC64_HANDOFF_SDRAM, handoff_table, len);
+
+ /* Read handoff - dual port */
+ plat->dualport = FIELD_GET(IO96B0_DUAL_PORT_MASK, handoff_table[PORT_EMIF_CONFIG_OFFSET]);
+ debug("%s: dualport from handoff: 0x%x\n", __func__, plat->dualport);
+
+ if (plat->dualport)
+ io96b_ctrl->num_port = 2;
+ else
+ io96b_ctrl->num_port = 1;
+
+ /* Read handoff - dual EMIF */
+ plat->dualemif = FIELD_GET(IO96B0_DUAL_EMIF_MASK, handoff_table[PORT_EMIF_CONFIG_OFFSET]);
+ debug("%s: dualemif from handoff: 0x%x\n", __func__, plat->dualemif);
+
+ if (plat->dualemif)
+ io96b_ctrl->num_instance = 2;
+ else
+ io96b_ctrl->num_instance = 1;
+
+ io96b_ctrl->io96b_pll = FIELD_GET(EMIF_PLL_MASK,
+ handoff_table[PORT_EMIF_CONFIG_OFFSET]);
+ debug("%s: io96b enabled pll from handoff: 0x%x\n", __func__, io96b_ctrl->io96b_pll);
+
+ update_io96b_assigned_to_hps(plat->dualport, plat->dualemif);
+
+ /* Assign IO96B CSR base address if it is valid */
+ for (i = 0; i < io96b_ctrl->num_instance; i++) {
+ io96b_ctrl->io96b[i].io96b_csr_addr = io96b_csr_reg_addr[i];
+ debug("%s: IO96B 0x%llx CSR enabled\n", __func__,
+ io96b_ctrl->io96b[i].io96b_csr_addr);
+ }
+}
+
+static void config_mpfe_sideband_mgr(struct udevice *dev)
+{
+ struct altera_sdram_plat *plat = dev_get_plat(dev);
+
+ /* Dual port setting */
+ if (plat->dualport)
+ setbits_le32(SIDEBANDMGR_FLAGOUTSET0_REG, BIT(4));
+
+ /* Dual EMIF setting */
+ if (plat->dualemif) {
+ set_mpfe_config();
+ setbits_le32(SIDEBANDMGR_FLAGOUTSET0_REG, BIT(5));
+ }
+
+ debug("%s: SIDEBANDMGR_FLAGOUTSTATUS0: 0x%x\n", __func__,
+ readl(SIDEBANDMGR_FLAGOUTSTATUS0_REG));
+}
+
+static void config_ccu_mgr(struct udevice *dev)
+{
+ int ret = 0;
+ struct altera_sdram_plat *plat = dev_get_plat(dev);
+
+ if (plat->dualport || plat->dualemif) {
+ debug("%s: config interleaving on ccu reg\n", __func__);
+ ret = uclass_get_device_by_name(UCLASS_NOP,
+ "socfpga-ccu-ddr-interleaving-on", &dev);
+ } else {
+ debug("%s: config interleaving off ccu reg\n", __func__);
+ ret = uclass_get_device_by_name(UCLASS_NOP,
+ "socfpga-ccu-ddr-interleaving-off", &dev);
+ }
+
+ if (ret) {
+ printf("interleaving on/off ccu settings init failed: %d\n", ret);
+ hang();
+ }
+}
+
+static void config_firewall_mpfe_csr(struct udevice *dev)
+{
+ int ret = 0;
+
+ debug("%s: config Firewall setting for MPFE CSR\n", __func__);
+ ret = uclass_get_device_by_name(UCLASS_NOP,
+ "socfpga-noc-fw-mpfe-csr", &dev);
+
+ if (ret) {
+ printf("Firewall setting for MPFE CSR init failed: %d\n", ret);
+ hang();
+ }
+}
+
+static bool hps_ocram_dbe_status(void)
+{
+ u32 reg = readl(BOOT_SCRATCH_COLD3_REG);
+
+ if (reg & ALT_SYSMGR_SCRATCH_REG_3_OCRAM_DBE_MASK)
+ return true;
+
+ return false;
+}
+
+int sdram_mmr_init_full(struct udevice *dev)
+{
+ int i, ret = 0;
+ phys_size_t hw_size;
+ struct altera_sdram_plat *plat = dev_get_plat(dev);
+ struct altera_sdram_priv *priv = dev_get_priv(dev);
+ struct io96b_info *io96b_ctrl = malloc(sizeof(*io96b_ctrl));
+
+ u32 reg = readl(BOOT_SCRATCH_COLD3_REG);
+ enum reset_type reset_t = get_reset_type(reg);
+ bool full_mem_init = false;
+
+ /* DDR initialization progress status tracking */
+ bool is_ddr_hang_be4_rst = is_ddr_init_hang();
+
+ debug("DDR: SDRAM init in progress ...\n");
+ ddr_init_inprogress(true);
+
+ gd->bd = (struct bd_info *)malloc(sizeof(struct bd_info));
+ memset(gd->bd, '\0', sizeof(struct bd_info));
+
+ debug("DDR: Address MPFE 0x%llx\n", plat->mpfe_base_addr);
+
+ /* Populating DDR handoff data */
+ debug("DDR: Checking SDRAM configuration in progress ...\n");
+ populate_ddr_handoff(dev, io96b_ctrl);
+
+ /* Configuring MPFE sideband manager registers - dual port & dual emif */
+ config_mpfe_sideband_mgr(dev);
+
+ /* Configuring Interleave/Non-interleave ccu registers */
+ config_ccu_mgr(dev);
+
+ /* Configure if polling is needed for IO96B GEN PLL locked */
+ io96b_ctrl->ckgen_lock = true;
+
+ /* Ensure calibration status passing */
+ init_mem_cal(io96b_ctrl);
+
+ printf("DDR: Calibration success\n");
+
+ /* Initiate IOSSM mailbox */
+ io96b_mb_init(io96b_ctrl);
+
+ /* DDR type, DDR size and ECC status) */
+ ret = get_mem_technology(io96b_ctrl);
+ if (ret) {
+ printf("DDR: Failed to get DDR type\n");
+
+ goto err;
+ }
+
+ ret = get_mem_width_info(io96b_ctrl);
+ if (ret) {
+ printf("DDR: Failed to get DDR size\n");
+
+ goto err;
+ }
+
+ hw_size = (phys_size_t)io96b_ctrl->overall_size * SZ_1G / SZ_8;
+
+ /* Get bank configuration from devicetree */
+ ret = fdtdec_decode_ram_size(gd->fdt_blob, NULL, 0, NULL,
+ (phys_size_t *)&gd->ram_size, gd->bd);
+ if (ret) {
+ puts("DDR: Failed to decode memory node\n");
+ ret = -ENXIO;
+
+ goto err;
+ }
+
+ if (gd->ram_size > hw_size) {
+ printf("DDR: Warning: DRAM size from device tree (%lld MiB) exceeds\n",
+ gd->ram_size >> 20);
+ printf(" the actual hardware capacity(%lld MiB). Memory configuration will be\n",
+ hw_size >> 20);
+ printf(" adjusted to match the detected hardware size.\n");
+ gd->ram_size = 0;
+ }
+
+ if (gd->ram_size > 0 && gd->ram_size != hw_size) {
+ printf("DDR: Warning: DRAM size from device tree (%lld MiB)\n",
+ gd->ram_size >> 20);
+ printf(" mismatch with hardware capacity(%lld MiB).\n",
+ hw_size >> 20);
+ }
+
+ if (gd->ram_size == 0 && hw_size > 0) {
+ phys_size_t remaining_size, size_counter = 0;
+ u8 config_dram_banks;
+
+ if (CONFIG_NR_DRAM_BANKS > MEMORY_BANK_MAX_COUNT) {
+ printf("DDR: Warning: CONFIG_NR_DRAM_BANKS(%d) is bigger than Max Memory Bank count(%d).\n",
+ CONFIG_NR_DRAM_BANKS, MEMORY_BANK_MAX_COUNT);
+ printf(" Max Memory Bank count is in use instead of CONFIG_NR_DRAM_BANKS.\n");
+ config_dram_banks = MEMORY_BANK_MAX_COUNT;
+ } else {
+ config_dram_banks = CONFIG_NR_DRAM_BANKS;
+ }
+
+ for (i = 0; i < config_dram_banks; i++) {
+ remaining_size = hw_size - size_counter;
+ if (remaining_size <= dram_bank_info[i].max_size) {
+ gd->bd->bi_dram[i].start = dram_bank_info[i].start;
+ gd->bd->bi_dram[i].size = remaining_size;
+ debug("Memory bank[%d] Starting address: 0x%llx size: 0x%llx\n",
+ i, gd->bd->bi_dram[i].start, gd->bd->bi_dram[i].size);
+ break;
+ }
+
+ gd->bd->bi_dram[i].start = dram_bank_info[i].start;
+ gd->bd->bi_dram[i].size = dram_bank_info[i].max_size;
+
+ debug("Memory bank[%d] Starting address: 0x%llx size: 0x%llx\n",
+ i, gd->bd->bi_dram[i].start, gd->bd->bi_dram[i].size);
+ size_counter += gd->bd->bi_dram[i].size;
+ }
+
+ gd->ram_size = hw_size;
+ }
+
+ printf("%s: %lld MiB\n", io96b_ctrl->ddr_type, gd->ram_size >> 20);
+
+ ret = ecc_enable_status(io96b_ctrl);
+ if (ret) {
+ printf("DDR: Failed to get ECC enabled status\n");
+
+ goto err;
+ }
+
+ /* Is HPS cold or warm reset? If yes, Skip full memory initialization if ECC
+ * enabled to preserve memory content
+ */
+ if (io96b_ctrl->ecc_status) {
+ if (ecc_interrupt_status(io96b_ctrl)) {
+ if (CONFIG_IS_ENABLED(WDT)) {
+ struct udevice *wdt;
+
+ printf("DDR: ECC error recover start now\n");
+ ret = uclass_first_device_err(UCLASS_WDT, &wdt);
+ if (ret) {
+ printf("DDR: Failed to trigger watchdog reset\n");
+ hang();
+ }
+
+ wdt_expire_now(wdt, 0);
+ }
+ hang();
+ }
+
+ full_mem_init = hps_ocram_dbe_status() | is_ddr_hang_be4_rst;
+ if (full_mem_init || !(reset_t == WARM_RESET || reset_t == COLD_RESET)) {
+ ret = bist_mem_init_start(io96b_ctrl);
+ if (ret) {
+ printf("DDR: Failed to fully initialize DDR memory\n");
+
+ goto err;
+ }
+ }
+
+ printf("SDRAM-ECC: Initialized success\n");
+ }
+
+ sdram_size_check(gd->bd);
+ printf("DDR: size check success\n");
+
+ sdram_set_firewall(gd->bd);
+
+ /* Firewall setting for MPFE CSR */
+ config_firewall_mpfe_csr(dev);
+
+ printf("DDR: firewall init success\n");
+
+ priv->info.base = gd->bd->bi_dram[0].start;
+ priv->info.size = gd->ram_size;
+
+ /* Ending DDR driver initialization success tracking */
+ ddr_init_inprogress(false);
+
+ printf("DDR: init success\n");
+
+err:
+ free(io96b_ctrl);
+
+ return ret;
+}
diff --git a/drivers/ddr/altera/sdram_soc64.c b/drivers/ddr/altera/sdram_soc64.c
index 10a8e64..c8c9211 100644
--- a/drivers/ddr/altera/sdram_soc64.c
+++ b/drivers/ddr/altera/sdram_soc64.c
@@ -1,6 +1,7 @@
// SPDX-License-Identifier: GPL-2.0
/*
* Copyright (C) 2016-2022 Intel Corporation <www.intel.com>
+ * Copyright (C) 2025 Altera Corporation <www.altera.com>
*
*/
@@ -28,6 +29,7 @@
#define PGTABLE_OFF 0x4000
+#if !IS_ENABLED(CONFIG_TARGET_SOCFPGA_AGILEX5)
u32 hmc_readl(struct altera_sdram_plat *plat, u32 reg)
{
return readl(plat->iomhc + reg);
@@ -99,8 +101,9 @@
debug("DDR: %s triggered successly\n", __func__);
return 0;
}
+#endif
-#if !IS_ENABLED(CONFIG_TARGET_SOCFPGA_N5X)
+#if !(IS_ENABLED(CONFIG_TARGET_SOCFPGA_N5X) || IS_ENABLED(CONFIG_TARGET_SOCFPGA_AGILEX5))
int poll_hmc_clock_status(void)
{
return wait_for_bit_le32((const void *)(socfpga_get_sysmgr_addr() +
@@ -252,7 +255,7 @@
return size;
}
-void sdram_set_firewall(struct bd_info *bd)
+static void sdram_set_firewall_non_f2sdram(struct bd_info *bd)
{
u32 i;
phys_size_t value;
@@ -288,7 +291,7 @@
FW_MPU_DDR_SCR_NONMPUREGION0ADDR_BASEEXT +
(i * 4 * sizeof(u32)));
- /* Setting non-secure MPU limit and limit extexded */
+ /* Setting non-secure MPU limit and limit extended */
value = bd->bi_dram[i].start + bd->bi_dram[i].size - 1;
lower = lower_32_bits(value);
@@ -301,7 +304,7 @@
FW_MPU_DDR_SCR_MPUREGION0ADDR_LIMITEXT +
(i * 4 * sizeof(u32)));
- /* Setting non-secure Non-MPU limit and limit extexded */
+ /* Setting non-secure Non-MPU limit and limit extended */
FW_MPU_DDR_SCR_WRITEL(lower,
FW_MPU_DDR_SCR_NONMPUREGION0ADDR_LIMIT +
(i * 4 * sizeof(u32)));
@@ -314,15 +317,77 @@
}
}
+#if IS_ENABLED(CONFIG_TARGET_SOCFPGA_AGILEX5)
+static void sdram_set_firewall_f2sdram(struct bd_info *bd)
+{
+ u32 i, lower, upper;
+ phys_size_t value;
+
+ for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++) {
+ if (!bd->bi_dram[i].size)
+ continue;
+
+ value = bd->bi_dram[i].start;
+
+ /* Keep first 1MB of SDRAM memory region as secure region when
+ * using ATF flow, where the ATF code is located.
+ */
+ if (IS_ENABLED(CONFIG_SPL_ATF) && i == 0)
+ value += SZ_1M;
+
+ /* Setting base and base extended */
+ lower = lower_32_bits(value);
+ upper = upper_32_bits(value);
+ FW_F2SDRAM_DDR_SCR_WRITEL(lower,
+ FW_F2SDRAM_DDR_SCR_REGION0ADDR_BASE +
+ (i * 4 * sizeof(u32)));
+ FW_F2SDRAM_DDR_SCR_WRITEL(upper & 0xff,
+ FW_F2SDRAM_DDR_SCR_REGION0ADDR_BASEEXT +
+ (i * 4 * sizeof(u32)));
+
+ /* Setting limit and limit extended */
+ value = bd->bi_dram[i].start + bd->bi_dram[i].size - 1;
+
+ lower = lower_32_bits(value);
+ upper = upper_32_bits(value);
+
+ FW_F2SDRAM_DDR_SCR_WRITEL(lower,
+ FW_F2SDRAM_DDR_SCR_REGION0ADDR_LIMIT +
+ (i * 4 * sizeof(u32)));
+ FW_F2SDRAM_DDR_SCR_WRITEL(upper & 0xff,
+ FW_F2SDRAM_DDR_SCR_REGION0ADDR_LIMITEXT +
+ (i * 4 * sizeof(u32)));
+
+ FW_F2SDRAM_DDR_SCR_WRITEL(BIT(i), FW_F2SDRAM_DDR_SCR_EN_SET);
+ }
+}
+#endif
+
+void sdram_set_firewall(struct bd_info *bd)
+{
+ sdram_set_firewall_non_f2sdram(bd);
+
+#if IS_ENABLED(CONFIG_TARGET_SOCFPGA_AGILEX5)
+ sdram_set_firewall_f2sdram(bd);
+#endif
+}
+
static int altera_sdram_of_to_plat(struct udevice *dev)
{
+#if !IS_ENABLED(CONFIG_TARGET_SOCFPGA_N5X)
struct altera_sdram_plat *plat = dev_get_plat(dev);
fdt_addr_t addr;
+#endif
/* These regs info are part of DDR handoff in bitstream */
#if IS_ENABLED(CONFIG_TARGET_SOCFPGA_N5X)
return 0;
-#endif
+#elif IS_ENABLED(CONFIG_TARGET_SOCFPGA_AGILEX5)
+ addr = dev_read_addr_index(dev, 0);
+ if (addr == FDT_ADDR_T_NONE)
+ return -EINVAL;
+ plat->mpfe_base_addr = addr;
+#else
addr = dev_read_addr_index(dev, 0);
if (addr == FDT_ADDR_T_NONE)
@@ -338,7 +403,7 @@
if (addr == FDT_ADDR_T_NONE)
return -EINVAL;
plat->hmc = (void __iomem *)addr;
-
+#endif
return 0;
}
@@ -385,6 +450,7 @@
{ .compatible = "altr,sdr-ctl-s10" },
{ .compatible = "intel,sdr-ctl-agilex" },
{ .compatible = "intel,sdr-ctl-n5x" },
+ { .compatible = "intel,sdr-ctl-agilex5" },
{ /* sentinel */ }
};
diff --git a/drivers/ddr/altera/sdram_soc64.h b/drivers/ddr/altera/sdram_soc64.h
index 87a70a8..183b1a3 100644
--- a/drivers/ddr/altera/sdram_soc64.h
+++ b/drivers/ddr/altera/sdram_soc64.h
@@ -1,6 +1,8 @@
/* SPDX-License-Identifier: GPL-2.0 */
/*
* Copyright (C) 2017-2019 Intel Corporation <www.intel.com>
+ * Copyright (C) 2025 Altera Corporation <www.altera.com>
+ *
*/
#ifndef _SDRAM_SOC64_H_
@@ -13,11 +15,19 @@
struct reset_ctl_bulk resets;
};
+#if IS_ENABLED(CONFIG_TARGET_SOCFPGA_AGILEX5)
+struct altera_sdram_plat {
+ fdt_addr_t mpfe_base_addr;
+ bool dualport;
+ bool dualemif;
+};
+#else
struct altera_sdram_plat {
void __iomem *hmc;
void __iomem *ddr_sch;
void __iomem *iomhc;
};
+#endif
/* ECC HMC registers */
#define DDRIOCTRL 0x8
diff --git a/drivers/dma/ti/k3-udma.c b/drivers/dma/ti/k3-udma.c
index 3013c47..723265a 100644
--- a/drivers/dma/ti/k3-udma.c
+++ b/drivers/dma/ti/k3-udma.c
@@ -36,6 +36,7 @@
#include "k3-psil-priv.h"
#define K3_UDMA_MAX_RFLOWS 1024
+#define K3_UDMA_MAX_TR 2
struct udma_chan;
@@ -74,7 +75,6 @@
struct k3_nav_ring *t_ring; /* Transmit ring */
struct k3_nav_ring *tc_ring; /* Transmit Completion ring */
int tflow_id; /* applicable only for PKTDMA */
-
};
#define udma_bchan udma_tchan
@@ -175,6 +175,7 @@
struct udma_rflow *rflows;
struct udma_match_data *match_data;
+ void *bc_desc;
struct udma_chan *channels;
u32 psil_base;
@@ -1349,6 +1350,7 @@
struct ti_sci_resource_desc *rm_desc;
struct ti_sci_resource *rm_res;
struct udma_tisci_rm *tisci_rm = &ud->tisci_rm;
+ size_t desc_size;
ud->tchan_map = devm_kmalloc_array(dev, BITS_TO_LONGS(ud->tchan_cnt),
sizeof(unsigned long), GFP_KERNEL);
@@ -1366,9 +1368,11 @@
ud->rflows = devm_kcalloc(dev, ud->rflow_cnt, sizeof(*ud->rflows),
GFP_KERNEL);
+ desc_size = cppi5_trdesc_calc_size(K3_UDMA_MAX_TR, sizeof(struct cppi5_tr_type15_t));
+ ud->bc_desc = devm_kzalloc(dev, ALIGN(desc_size, ARCH_DMA_MINALIGN), GFP_KERNEL);
if (!ud->tchan_map || !ud->rchan_map || !ud->rflow_map ||
!ud->rflow_map_reserved || !ud->tchans || !ud->rchans ||
- !ud->rflows)
+ !ud->rflows || !ud->bc_desc)
return -ENOMEM;
/*
@@ -1444,6 +1448,7 @@
struct ti_sci_resource_desc *rm_desc;
struct ti_sci_resource *rm_res;
struct udma_tisci_rm *tisci_rm = &ud->tisci_rm;
+ size_t desc_size;
ud->bchan_map = devm_kmalloc_array(dev, BITS_TO_LONGS(ud->bchan_cnt),
sizeof(unsigned long), GFP_KERNEL);
@@ -1460,9 +1465,12 @@
ud->rflows = devm_kcalloc(dev, ud->rchan_cnt, sizeof(*ud->rflows),
GFP_KERNEL);
+ desc_size = cppi5_trdesc_calc_size(K3_UDMA_MAX_TR, sizeof(struct cppi5_tr_type15_t));
+ ud->bc_desc = devm_kzalloc(dev, ALIGN(desc_size, ARCH_DMA_MINALIGN), GFP_KERNEL);
+
if (!ud->bchan_map || !ud->tchan_map || !ud->rchan_map ||
!ud->bchans || !ud->tchans || !ud->rchans ||
- !ud->rflows)
+ !ud->rflows || !ud->bc_desc)
return -ENOMEM;
/* Get resource ranges from tisci */
@@ -1718,8 +1726,7 @@
int num_tr;
size_t tr_size = sizeof(struct cppi5_tr_type15_t);
u16 tr0_cnt0, tr0_cnt1, tr1_cnt0;
- unsigned long dummy;
- void *tr_desc;
+ void *tr_desc = uc->ud->bc_desc;
size_t desc_size;
if (len < SZ_64K) {
@@ -1748,9 +1755,6 @@
}
desc_size = cppi5_trdesc_calc_size(num_tr, tr_size);
- tr_desc = dma_alloc_coherent(desc_size, &dummy);
- if (!tr_desc)
- return NULL;
memset(tr_desc, 0, desc_size);
cppi5_trdesc_init(tr_desc, num_tr, tr_size, 0, 0);
diff --git a/drivers/gpio/gpio-uclass.c b/drivers/gpio/gpio-uclass.c
index da929c3..3d9f8b3 100644
--- a/drivers/gpio/gpio-uclass.c
+++ b/drivers/gpio/gpio-uclass.c
@@ -1145,29 +1145,9 @@
ret = uclass_get_device_by_ofnode(UCLASS_GPIO, args->node,
&desc->dev);
if (ret) {
-#if CONFIG_IS_ENABLED(MAX77663_GPIO) || CONFIG_IS_ENABLED(PALMAS_GPIO)
- struct udevice *pmic;
- ret = uclass_get_device_by_ofnode(UCLASS_PMIC, args->node,
- &pmic);
- if (ret) {
- log_debug("%s: PMIC device get failed, err %d\n",
- __func__, ret);
- goto err;
- }
-
- device_foreach_child(desc->dev, pmic) {
- if (device_get_uclass_id(desc->dev) == UCLASS_GPIO)
- break;
- }
-
- /* if loop exits without GPIO device return error */
- if (device_get_uclass_id(desc->dev) != UCLASS_GPIO)
- goto err;
-#else
debug("%s: uclass_get_device_by_ofnode failed\n",
__func__);
goto err;
-#endif
}
}
ret = gpio_find_and_xlate(desc, args);
diff --git a/drivers/gpio/pca953x_gpio.c b/drivers/gpio/pca953x_gpio.c
index e84038f..523ca84 100644
--- a/drivers/gpio/pca953x_gpio.c
+++ b/drivers/gpio/pca953x_gpio.c
@@ -393,6 +393,8 @@
{ .compatible = "nxp,pca9575", .data = OF_957X(16, PCA_INT), },
{ .compatible = "nxp,pca9698", .data = OF_953X(40, 0), },
+ { .compatible = "nxp,pcal6408", .data = OF_953X(8, PCA_LATCH_INT), },
+ { .compatible = "nxp,pcal6416", .data = OF_953X(16, PCA_LATCH_INT), },
{ .compatible = "nxp,pcal6524", .data = OF_953X(24, PCA_LATCH_INT), },
{ .compatible = "maxim,max7310", .data = OF_953X(8, 0), },
diff --git a/drivers/led/led-uclass.c b/drivers/led/led-uclass.c
index 27ef890..22f61d1 100644
--- a/drivers/led/led-uclass.c
+++ b/drivers/led/led-uclass.c
@@ -273,6 +273,10 @@
/* Now try to detect function label name */
func = dev_read_string(dev, "function");
cp = dev_read_u32(dev, "color", &color);
+ // prevent coverity scan error CID 541279: (TAINTED_SCALAR)
+ if (color < LED_COLOR_ID_WHITE || color >= LED_COLOR_ID_MAX)
+ cp = -EINVAL;
+
if (cp == 0 || func) {
ret = dev_read_u32(dev, "function-enumerator", &enumerator);
if (!ret) {
diff --git a/drivers/mmc/mmc.c b/drivers/mmc/mmc.c
index 7995868..31a7236 100644
--- a/drivers/mmc/mmc.c
+++ b/drivers/mmc/mmc.c
@@ -2376,7 +2376,7 @@
| ext_csd[EXT_CSD_SEC_CNT + 2] << 16
| ext_csd[EXT_CSD_SEC_CNT + 3] << 24;
capacity *= MMC_MAX_BLOCK_LEN;
- if ((capacity >> 20) > 2 * 1024)
+ if (mmc->high_capacity)
mmc->capacity_user = capacity;
}
diff --git a/drivers/mtd/mtdpart.c b/drivers/mtd/mtdpart.c
index 88094b8..3f8edeb 100644
--- a/drivers/mtd/mtdpart.c
+++ b/drivers/mtd/mtdpart.c
@@ -208,7 +208,7 @@
{
struct mtd_partition partition = {}, *parts;
const char *mtdparts = *_mtdparts;
- uint64_t cur_off = 0, cur_sz = 0;
+ uint64_t cur_off = 0;
int nparts = 0;
int ret, idx;
u64 sz;
@@ -237,8 +237,7 @@
return ret;
if (parts[idx].size == MTD_SIZE_REMAINING)
- parts[idx].size = parent->size - cur_sz;
- cur_sz += parts[idx].size;
+ parts[idx].size = parent->size - parts[idx].offset;
sz = parts[idx].size;
if (sz < parent->writesize || do_div(sz, parent->writesize)) {
diff --git a/drivers/mtd/nand/raw/atmel/nand-controller.c b/drivers/mtd/nand/raw/atmel/nand-controller.c
index 56fbd64..c90a4ea 100644
--- a/drivers/mtd/nand/raw/atmel/nand-controller.c
+++ b/drivers/mtd/nand/raw/atmel/nand-controller.c
@@ -1127,7 +1127,7 @@
const struct nand_data_interface *conf,
struct atmel_smc_cs_conf *smcconf)
{
- u32 ncycles, totalcycles, timeps, mckperiodps;
+ u32 ncycles, totalcycles, timeps, mckperiodps, pulse;
struct atmel_nand_controller *nc;
int ret;
@@ -1253,11 +1253,16 @@
ATMEL_SMC_MODE_TDFMODE_OPTIMIZED;
/*
- * Read pulse timing directly matches tRP:
+ * Read pulse timing would directly match tRP,
+ * but some NAND flash chips (S34ML01G2 and W29N02KVxxAF)
+ * do not work properly in timing mode 3.
+ * The workaround is to extend the SMC NRD pulse to meet tREA
+ * timing.
*
- * NRD_PULSE = tRP
+ * NRD_PULSE = max(tRP, tREA)
*/
- ncycles = DIV_ROUND_UP(conf->timings.sdr.tRP_min, mckperiodps);
+ pulse = max(conf->timings.sdr.tRP_min, conf->timings.sdr.tREA_max);
+ ncycles = DIV_ROUND_UP(pulse, mckperiodps);
totalcycles += ncycles;
ret = atmel_smc_cs_conf_set_pulse(smcconf, ATMEL_SMC_NRD_SHIFT,
ncycles);
diff --git a/drivers/net/designware.c b/drivers/net/designware.c
index 0a1fff3..5a6e89c 100644
--- a/drivers/net/designware.c
+++ b/drivers/net/designware.c
@@ -33,6 +33,9 @@
#include <linux/printk.h>
#include <power/regulator.h>
#include "designware.h"
+#if IS_ENABLED(CONFIG_ARCH_NPCM8XX)
+#include <asm/arch/gmac.h>
+#endif
static int dw_mdio_read(struct mii_dev *bus, int addr, int devad, int reg)
{
@@ -223,6 +226,124 @@
}
#endif
+#if IS_ENABLED(CONFIG_BITBANGMII) && IS_ENABLED(CONFIG_DM_GPIO)
+static int dw_eth_bb_mdio_active(struct bb_miiphy_bus *bus)
+{
+ struct dw_eth_dev *priv = bus->priv;
+ struct gpio_desc *desc = &priv->mdio_gpio;
+
+ desc->flags = 0;
+ dm_gpio_set_dir_flags(&priv->mdio_gpio, GPIOD_IS_OUT | GPIOD_IS_OUT_ACTIVE);
+
+ return 0;
+}
+
+static int dw_eth_bb_mdio_tristate(struct bb_miiphy_bus *bus)
+{
+ struct dw_eth_dev *priv = bus->priv;
+ struct gpio_desc *desc = &priv->mdio_gpio;
+
+ desc->flags = 0;
+ dm_gpio_set_dir_flags(&priv->mdio_gpio, GPIOD_IS_IN);
+
+ return 0;
+}
+
+static int dw_eth_bb_set_mdio(struct bb_miiphy_bus *bus, int v)
+{
+ struct dw_eth_dev *priv = bus->priv;
+
+ if (v)
+ dm_gpio_set_value(&priv->mdio_gpio, 1);
+ else
+ dm_gpio_set_value(&priv->mdio_gpio, 0);
+
+ return 0;
+}
+
+static int dw_eth_bb_get_mdio(struct bb_miiphy_bus *bus, int *v)
+{
+ struct dw_eth_dev *priv = bus->priv;
+
+ *v = dm_gpio_get_value(&priv->mdio_gpio);
+
+ return 0;
+}
+
+static int dw_eth_bb_set_mdc(struct bb_miiphy_bus *bus, int v)
+{
+ struct dw_eth_dev *priv = bus->priv;
+
+ if (v)
+ dm_gpio_set_value(&priv->mdc_gpio, 1);
+ else
+ dm_gpio_set_value(&priv->mdc_gpio, 0);
+
+ return 0;
+}
+
+static int dw_eth_bb_delay(struct bb_miiphy_bus *bus)
+{
+ struct dw_eth_dev *priv = bus->priv;
+
+ udelay(priv->bb_delay);
+ return 0;
+}
+
+static int dw_bb_mdio_init(const char *name, struct udevice *dev)
+{
+ struct dw_eth_dev *dwpriv = dev_get_priv(dev);
+ struct bb_miiphy_bus *bb_miiphy = bb_miiphy_alloc();
+ struct mii_dev *bus;
+ int ret;
+
+ if (!bb_miiphy) {
+ printf("Failed to allocate MDIO bus\n");
+ return -ENOMEM;
+ }
+
+ bus = &bb_miiphy->mii;
+
+ debug("\n%s: use bitbang mii..\n", dev->name);
+ ret = gpio_request_by_name(dev, "snps,mdc-gpio", 0,
+ &dwpriv->mdc_gpio,
+ GPIOD_IS_OUT | GPIOD_IS_OUT_ACTIVE);
+ if (ret) {
+ debug("no mdc-gpio\n");
+ return ret;
+ }
+ ret = gpio_request_by_name(dev, "snps,mdio-gpio", 0,
+ &dwpriv->mdio_gpio,
+ GPIOD_IS_OUT | GPIOD_IS_OUT_ACTIVE);
+ if (ret) {
+ debug("no mdio-gpio\n");
+ return ret;
+ }
+ dwpriv->bb_delay = dev_read_u32_default(dev, "snps,bitbang-delay", 1);
+
+ dwpriv->bus = bus;
+ dwpriv->dev = dev;
+
+ snprintf(bus->name, sizeof(bus->name), "%s", name);
+ bus->read = bb_miiphy_read;
+ bus->write = bb_miiphy_write;
+#if CONFIG_IS_ENABLED(DM_GPIO)
+ bus->reset = dw_mdio_reset;
+#endif
+ bus->priv = dwpriv;
+
+ /* Copy the bus accessors and private data */
+ bb_miiphy->mdio_active = dw_eth_bb_mdio_active;
+ bb_miiphy->mdio_tristate = dw_eth_bb_mdio_tristate;
+ bb_miiphy->set_mdio = dw_eth_bb_set_mdio;
+ bb_miiphy->get_mdio = dw_eth_bb_get_mdio;
+ bb_miiphy->set_mdc = dw_eth_bb_set_mdc;
+ bb_miiphy->delay = dw_eth_bb_delay;
+
+ return mdio_register(bus);
+}
+#endif
+
static void tx_descs_init(struct dw_eth_dev *priv)
{
struct eth_dma_regs *dma_p = priv->dma_regs_p;
@@ -352,10 +473,35 @@
(phydev->port == PORT_FIBRE) ? ", fiber mode" : "");
#ifdef CONFIG_ARCH_NPCM8XX
+ if (phydev->interface == PHY_INTERFACE_MODE_SGMII) {
+ unsigned int start;
+
+ /* Indirect access to VR_MII_MMD registers */
+ writew((VR_MII_MMD >> 9), PCS_BA + PCS_IND_AC);
+ /* Set PCS_Mode to SGMII */
+ clrsetbits_le16(PCS_BA + VR_MII_MMD_AN_CTRL, BIT(1), BIT(2));
+ /* Set Auto Speed Mode Change */
+ setbits_le16(PCS_BA + VR_MII_MMD_CTRL1, BIT(9));
+ /* Indirect access to SR_MII_MMD registers */
+ writew((SR_MII_MMD >> 9), PCS_BA + PCS_IND_AC);
+ /* Restart Auto-Negotiation */
+ setbits_le16(PCS_BA + SR_MII_MMD_CTRL, BIT(9) | BIT(12));
+
+ printf("SGMII PHY Wait for link up \n");
+ /* SGMII PHY Wait for link up */
+ start = get_timer(0);
+ while (!(readw(PCS_BA + SR_MII_MMD_STS) & BIT(2))) {
+ if (get_timer(start) >= LINK_UP_TIMEOUT) {
+ printf("PHY link up timeout\n");
+ return -ETIMEDOUT;
+ }
+ mdelay(1);
+ };
+ }
/* Pass all Multicast Frames */
setbits_le32(&mac_p->framefilt, BIT(4));
-
#endif
+
return 0;
}
@@ -694,6 +840,7 @@
{
struct eth_pdata *pdata = dev_get_plat(dev);
struct dw_eth_dev *priv = dev_get_priv(dev);
+ bool __maybe_unused bbmiiphy = false;
phys_addr_t iobase = pdata->iobase;
void *ioaddr;
int ret, err;
@@ -784,51 +931,30 @@
priv->interface = pdata->phy_interface;
priv->max_speed = pdata->max_speed;
-#if IS_ENABLED(CONFIG_DM_MDIO)
- ret = dw_dm_mdio_init(dev->name, dev);
-#else
- ret = dw_mdio_init(dev->name, dev);
-#endif
- if (ret) {
- err = ret;
- goto mdio_err;
- }
- priv->bus = miiphy_get_dev_by_name(dev->name);
- priv->dev = dev;
-
#if IS_ENABLED(CONFIG_BITBANGMII) && IS_ENABLED(CONFIG_DM_GPIO)
- if (dev_read_bool(dev, "snps,bitbang-mii")) {
- int bus_idx;
-
- debug("\n%s: use bitbang mii..\n", dev->name);
- ret = gpio_request_by_name(dev, "snps,mdc-gpio", 0,
- &priv->mdc_gpio, GPIOD_IS_OUT
- | GPIOD_IS_OUT_ACTIVE);
+ bbmiiphy = dev_read_bool(dev, "snps,bitbang-mii");
+ if (bbmiiphy) {
+ ret = dw_bb_mdio_init(dev->name, dev);
if (ret) {
- debug("no mdc-gpio\n");
- return ret;
+ err = ret;
+ goto mdio_err;
}
- ret = gpio_request_by_name(dev, "snps,mdio-gpio", 0,
- &priv->mdio_gpio, GPIOD_IS_OUT
- | GPIOD_IS_OUT_ACTIVE);
+ } else
+#endif
+ {
+#if IS_ENABLED(CONFIG_DM_MDIO)
+ ret = dw_dm_mdio_init(dev->name, dev);
+#else
+ ret = dw_mdio_init(dev->name, dev);
+#endif
if (ret) {
- debug("no mdio-gpio\n");
- return ret;
- }
- priv->bb_delay = dev_read_u32_default(dev, "snps,bitbang-delay", 1);
-
- for (bus_idx = 0; bus_idx < bb_miiphy_buses_num; bus_idx++) {
- if (!bb_miiphy_buses[bus_idx].priv) {
- bb_miiphy_buses[bus_idx].priv = priv;
- strlcpy(bb_miiphy_buses[bus_idx].name, priv->bus->name,
- MDIO_NAME_LEN);
- priv->bus->read = bb_miiphy_read;
- priv->bus->write = bb_miiphy_write;
- break;
- }
+ err = ret;
+ goto mdio_err;
}
+ priv->bus = miiphy_get_dev_by_name(dev->name);
+ priv->dev = dev;
}
-#endif
+
ret = dw_phy_init(priv, dev);
debug("%s, ret=%d\n", __func__, ret);
if (!ret)
@@ -837,7 +963,12 @@
/* continue here for cleanup if no PHY found */
err = ret;
mdio_unregister(priv->bus);
- mdio_free(priv->bus);
+#if IS_ENABLED(CONFIG_BITBANGMII) && IS_ENABLED(CONFIG_DM_GPIO)
+ if (bbmiiphy)
+ bb_miiphy_free(container_of(priv->bus, struct bb_miiphy_bus, mii));
+ else
+#endif
+ mdio_free(priv->bus);
mdio_err:
#ifdef CONFIG_CLK
@@ -939,83 +1070,3 @@
};
U_BOOT_PCI_DEVICE(eth_designware, supported);
-
-#if IS_ENABLED(CONFIG_BITBANGMII) && IS_ENABLED(CONFIG_DM_GPIO)
-static int dw_eth_bb_mdio_active(struct bb_miiphy_bus *bus)
-{
- struct dw_eth_dev *priv = bus->priv;
- struct gpio_desc *desc = &priv->mdio_gpio;
-
- desc->flags = 0;
- dm_gpio_set_dir_flags(&priv->mdio_gpio, GPIOD_IS_OUT | GPIOD_IS_OUT_ACTIVE);
-
- return 0;
-}
-
-static int dw_eth_bb_mdio_tristate(struct bb_miiphy_bus *bus)
-{
- struct dw_eth_dev *priv = bus->priv;
- struct gpio_desc *desc = &priv->mdio_gpio;
-
- desc->flags = 0;
- dm_gpio_set_dir_flags(&priv->mdio_gpio, GPIOD_IS_IN);
-
- return 0;
-}
-
-static int dw_eth_bb_set_mdio(struct bb_miiphy_bus *bus, int v)
-{
- struct dw_eth_dev *priv = bus->priv;
-
- if (v)
- dm_gpio_set_value(&priv->mdio_gpio, 1);
- else
- dm_gpio_set_value(&priv->mdio_gpio, 0);
-
- return 0;
-}
-
-static int dw_eth_bb_get_mdio(struct bb_miiphy_bus *bus, int *v)
-{
- struct dw_eth_dev *priv = bus->priv;
-
- *v = dm_gpio_get_value(&priv->mdio_gpio);
-
- return 0;
-}
-
-static int dw_eth_bb_set_mdc(struct bb_miiphy_bus *bus, int v)
-{
- struct dw_eth_dev *priv = bus->priv;
-
- if (v)
- dm_gpio_set_value(&priv->mdc_gpio, 1);
- else
- dm_gpio_set_value(&priv->mdc_gpio, 0);
-
- return 0;
-}
-
-static int dw_eth_bb_delay(struct bb_miiphy_bus *bus)
-{
- struct dw_eth_dev *priv = bus->priv;
-
- udelay(priv->bb_delay);
- return 0;
-}
-
-struct bb_miiphy_bus bb_miiphy_buses[] = {
- {
- .name = BB_MII_DEVNAME,
- .mdio_active = dw_eth_bb_mdio_active,
- .mdio_tristate = dw_eth_bb_mdio_tristate,
- .set_mdio = dw_eth_bb_set_mdio,
- .get_mdio = dw_eth_bb_get_mdio,
- .set_mdc = dw_eth_bb_set_mdc,
- .delay = dw_eth_bb_delay,
- .priv = NULL,
- }
-};
-
-int bb_miiphy_buses_num = ARRAY_SIZE(bb_miiphy_buses);
-#endif
diff --git a/drivers/net/dwc_eth_qos_rockchip.c b/drivers/net/dwc_eth_qos_rockchip.c
index 9fc8c68..f3a0f63 100644
--- a/drivers/net/dwc_eth_qos_rockchip.c
+++ b/drivers/net/dwc_eth_qos_rockchip.c
@@ -46,6 +46,10 @@
#define GRF_BIT(nr) (BIT(nr) | BIT((nr) + 16))
#define GRF_CLR_BIT(nr) (BIT((nr) + 16))
+#define DELAY_ENABLE(soc, tx, rx) \
+ (((tx) ? soc##_GMAC_TXCLK_DLY_ENABLE : soc##_GMAC_TXCLK_DLY_DISABLE) | \
+ ((rx) ? soc##_GMAC_RXCLK_DLY_ENABLE : soc##_GMAC_RXCLK_DLY_DISABLE))
+
#define RK3568_GRF_GMAC0_CON0 0x0380
#define RK3568_GRF_GMAC0_CON1 0x0384
#define RK3568_GRF_GMAC1_CON0 0x0388
@@ -85,8 +89,7 @@
regmap_write(data->grf, con1,
RK3568_GMAC_PHY_INTF_SEL_RGMII |
- RK3568_GMAC_RXCLK_DLY_ENABLE |
- RK3568_GMAC_TXCLK_DLY_ENABLE);
+ DELAY_ENABLE(RK3568, tx_delay, rx_delay));
return 0;
}
@@ -131,6 +134,10 @@
return 0;
}
+#define RK3588_DELAY_ENABLE(id, tx, rx) \
+ (((tx) ? RK3588_GMAC_TXCLK_DLY_ENABLE(id) : RK3588_GMAC_TXCLK_DLY_DISABLE(id)) | \
+ ((rx) ? RK3588_GMAC_RXCLK_DLY_ENABLE(id) : RK3588_GMAC_RXCLK_DLY_DISABLE(id)))
+
/* sys_grf */
#define RK3588_GRF_GMAC_CON7 0x031c
#define RK3588_GRF_GMAC_CON8 0x0320
@@ -189,8 +196,7 @@
RK3588_GMAC_CLK_RGMII_MODE(id));
regmap_write(data->grf, RK3588_GRF_GMAC_CON7,
- RK3588_GMAC_RXCLK_DLY_ENABLE(id) |
- RK3588_GMAC_TXCLK_DLY_ENABLE(id));
+ RK3588_DELAY_ENABLE(id, tx_delay, rx_delay));
regmap_write(data->grf, offset_con,
RK3588_GMAC_CLK_RX_DL_CFG(rx_delay) |
diff --git a/drivers/net/phy/miiphybb.c b/drivers/net/phy/miiphybb.c
index 9f5f9b1..553af2c 100644
--- a/drivers/net/phy/miiphybb.c
+++ b/drivers/net/phy/miiphybb.c
@@ -14,31 +14,31 @@
#include <ioports.h>
#include <ppc_asm.tmpl>
+#include <malloc.h>
#include <miiphy.h>
#include <asm/global_data.h>
-int bb_miiphy_init(void)
+static inline struct bb_miiphy_bus *bb_miiphy_getbus(struct mii_dev *miidev)
{
- int i;
+ return container_of(miidev, struct bb_miiphy_bus, mii);
+}
+
+struct bb_miiphy_bus *bb_miiphy_alloc(void)
+{
+ struct bb_miiphy_bus *bus;
- for (i = 0; i < bb_miiphy_buses_num; i++)
- if (bb_miiphy_buses[i].init != NULL)
- bb_miiphy_buses[i].init(&bb_miiphy_buses[i]);
+ bus = malloc(sizeof(*bus));
+ if (!bus)
+ return bus;
- return 0;
+ mdio_init(&bus->mii);
+
+ return bus;
}
-static inline struct bb_miiphy_bus *bb_miiphy_getbus(const char *devname)
+void bb_miiphy_free(struct bb_miiphy_bus *bus)
{
- int i;
-
- /* Search the correct bus */
- for (i = 0; i < bb_miiphy_buses_num; i++) {
- if (!strcmp(bb_miiphy_buses[i].name, devname)) {
- return &bb_miiphy_buses[i];
- }
- }
- return NULL;
+ free(bus);
}
/*****************************************************************************
@@ -133,7 +133,7 @@
int j; /* counter */
struct bb_miiphy_bus *bus;
- bus = bb_miiphy_getbus(miidev->name);
+ bus = bb_miiphy_getbus(miidev);
if (bus == NULL) {
return -1;
}
@@ -201,7 +201,7 @@
struct bb_miiphy_bus *bus;
int j; /* counter */
- bus = bb_miiphy_getbus(miidev->name);
+ bus = bb_miiphy_getbus(miidev);
if (bus == NULL) {
/* Bus not found! */
return -1;
diff --git a/drivers/net/ravb.c b/drivers/net/ravb.c
index 7286ad1..cb727ae 100644
--- a/drivers/net/ravb.c
+++ b/drivers/net/ravb.c
@@ -490,10 +490,70 @@
ravb_reset(dev);
}
+/* Bitbang MDIO access */
+static int ravb_bb_mdio_active(struct bb_miiphy_bus *bus)
+{
+ struct ravb_priv *eth = bus->priv;
+
+ setbits_le32(eth->iobase + RAVB_REG_PIR, PIR_MMD);
+
+ return 0;
+}
+
+static int ravb_bb_mdio_tristate(struct bb_miiphy_bus *bus)
+{
+ struct ravb_priv *eth = bus->priv;
+
+ clrbits_le32(eth->iobase + RAVB_REG_PIR, PIR_MMD);
+
+ return 0;
+}
+
+static int ravb_bb_set_mdio(struct bb_miiphy_bus *bus, int v)
+{
+ struct ravb_priv *eth = bus->priv;
+
+ if (v)
+ setbits_le32(eth->iobase + RAVB_REG_PIR, PIR_MDO);
+ else
+ clrbits_le32(eth->iobase + RAVB_REG_PIR, PIR_MDO);
+
+ return 0;
+}
+
+static int ravb_bb_get_mdio(struct bb_miiphy_bus *bus, int *v)
+{
+ struct ravb_priv *eth = bus->priv;
+
+ *v = (readl(eth->iobase + RAVB_REG_PIR) & PIR_MDI) >> 3;
+
+ return 0;
+}
+
+static int ravb_bb_set_mdc(struct bb_miiphy_bus *bus, int v)
+{
+ struct ravb_priv *eth = bus->priv;
+
+ if (v)
+ setbits_le32(eth->iobase + RAVB_REG_PIR, PIR_MDC);
+ else
+ clrbits_le32(eth->iobase + RAVB_REG_PIR, PIR_MDC);
+
+ return 0;
+}
+
+static int ravb_bb_delay(struct bb_miiphy_bus *bus)
+{
+ udelay(10);
+
+ return 0;
+}
+
static int ravb_probe(struct udevice *dev)
{
struct eth_pdata *pdata = dev_get_plat(dev);
struct ravb_priv *eth = dev_get_priv(dev);
+ struct bb_miiphy_bus *bb_miiphy;
struct mii_dev *mdiodev;
void __iomem *iobase;
int ret;
@@ -505,22 +565,32 @@
if (ret < 0)
goto err_mdio_alloc;
- mdiodev = mdio_alloc();
- if (!mdiodev) {
+ bb_miiphy = bb_miiphy_alloc();
+ if (!bb_miiphy) {
ret = -ENOMEM;
goto err_mdio_alloc;
}
+ mdiodev = &bb_miiphy->mii;
+
mdiodev->read = bb_miiphy_read;
mdiodev->write = bb_miiphy_write;
- bb_miiphy_buses[0].priv = eth;
snprintf(mdiodev->name, sizeof(mdiodev->name), dev->name);
+ /* Copy the bus accessors and private data */
+ bb_miiphy->mdio_active = ravb_bb_mdio_active;
+ bb_miiphy->mdio_tristate = ravb_bb_mdio_tristate;
+ bb_miiphy->set_mdio = ravb_bb_set_mdio;
+ bb_miiphy->get_mdio = ravb_bb_get_mdio;
+ bb_miiphy->set_mdc = ravb_bb_set_mdc;
+ bb_miiphy->delay = ravb_bb_delay;
+ bb_miiphy->priv = eth;
+
ret = mdio_register(mdiodev);
if (ret < 0)
goto err_mdio_register;
- eth->bus = miiphy_get_dev_by_name(dev->name);
+ eth->bus = &bb_miiphy->mii;
/* Bring up PHY */
ret = clk_enable_bulk(ð->clks);
@@ -540,7 +610,7 @@
err_mdio_reset:
clk_release_bulk(ð->clks);
err_mdio_register:
- mdio_free(mdiodev);
+ bb_miiphy_free(bb_miiphy);
err_mdio_alloc:
unmap_physmem(eth->iobase, MAP_NOCACHE);
return ret;
@@ -560,83 +630,6 @@
return 0;
}
-static int ravb_bb_init(struct bb_miiphy_bus *bus)
-{
- return 0;
-}
-
-static int ravb_bb_mdio_active(struct bb_miiphy_bus *bus)
-{
- struct ravb_priv *eth = bus->priv;
-
- setbits_le32(eth->iobase + RAVB_REG_PIR, PIR_MMD);
-
- return 0;
-}
-
-static int ravb_bb_mdio_tristate(struct bb_miiphy_bus *bus)
-{
- struct ravb_priv *eth = bus->priv;
-
- clrbits_le32(eth->iobase + RAVB_REG_PIR, PIR_MMD);
-
- return 0;
-}
-
-static int ravb_bb_set_mdio(struct bb_miiphy_bus *bus, int v)
-{
- struct ravb_priv *eth = bus->priv;
-
- if (v)
- setbits_le32(eth->iobase + RAVB_REG_PIR, PIR_MDO);
- else
- clrbits_le32(eth->iobase + RAVB_REG_PIR, PIR_MDO);
-
- return 0;
-}
-
-static int ravb_bb_get_mdio(struct bb_miiphy_bus *bus, int *v)
-{
- struct ravb_priv *eth = bus->priv;
-
- *v = (readl(eth->iobase + RAVB_REG_PIR) & PIR_MDI) >> 3;
-
- return 0;
-}
-
-static int ravb_bb_set_mdc(struct bb_miiphy_bus *bus, int v)
-{
- struct ravb_priv *eth = bus->priv;
-
- if (v)
- setbits_le32(eth->iobase + RAVB_REG_PIR, PIR_MDC);
- else
- clrbits_le32(eth->iobase + RAVB_REG_PIR, PIR_MDC);
-
- return 0;
-}
-
-static int ravb_bb_delay(struct bb_miiphy_bus *bus)
-{
- udelay(10);
-
- return 0;
-}
-
-struct bb_miiphy_bus bb_miiphy_buses[] = {
- {
- .name = "ravb",
- .init = ravb_bb_init,
- .mdio_active = ravb_bb_mdio_active,
- .mdio_tristate = ravb_bb_mdio_tristate,
- .set_mdio = ravb_bb_set_mdio,
- .get_mdio = ravb_bb_get_mdio,
- .set_mdc = ravb_bb_set_mdc,
- .delay = ravb_bb_delay,
- },
-};
-int bb_miiphy_buses_num = ARRAY_SIZE(bb_miiphy_buses);
-
static const struct eth_ops ravb_ops = {
.start = ravb_start,
.send = ravb_send,
@@ -658,8 +651,6 @@
pdata->max_speed = dev_read_u32_default(dev, "max-speed", 1000);
- sprintf(bb_miiphy_buses[0].name, dev->name);
-
return 0;
}
diff --git a/drivers/net/sh_eth.c b/drivers/net/sh_eth.c
index f1ce994..83e4860 100644
--- a/drivers/net/sh_eth.c
+++ b/drivers/net/sh_eth.c
@@ -643,11 +643,80 @@
sh_eth_stop(&priv->shdev);
}
+/******* for bb_miiphy *******/
+static int sh_eth_bb_mdio_active(struct bb_miiphy_bus *bus)
+{
+ struct sh_eth_dev *eth = bus->priv;
+ struct sh_eth_info *port_info = ð->port_info[eth->port];
+
+ sh_eth_write(port_info, sh_eth_read(port_info, PIR) | PIR_MMD, PIR);
+
+ return 0;
+}
+
+static int sh_eth_bb_mdio_tristate(struct bb_miiphy_bus *bus)
+{
+ struct sh_eth_dev *eth = bus->priv;
+ struct sh_eth_info *port_info = ð->port_info[eth->port];
+
+ sh_eth_write(port_info, sh_eth_read(port_info, PIR) & ~PIR_MMD, PIR);
+
+ return 0;
+}
+
+static int sh_eth_bb_set_mdio(struct bb_miiphy_bus *bus, int v)
+{
+ struct sh_eth_dev *eth = bus->priv;
+ struct sh_eth_info *port_info = ð->port_info[eth->port];
+
+ if (v)
+ sh_eth_write(port_info,
+ sh_eth_read(port_info, PIR) | PIR_MDO, PIR);
+ else
+ sh_eth_write(port_info,
+ sh_eth_read(port_info, PIR) & ~PIR_MDO, PIR);
+
+ return 0;
+}
+
+static int sh_eth_bb_get_mdio(struct bb_miiphy_bus *bus, int *v)
+{
+ struct sh_eth_dev *eth = bus->priv;
+ struct sh_eth_info *port_info = ð->port_info[eth->port];
+
+ *v = (sh_eth_read(port_info, PIR) & PIR_MDI) >> 3;
+
+ return 0;
+}
+
+static int sh_eth_bb_set_mdc(struct bb_miiphy_bus *bus, int v)
+{
+ struct sh_eth_dev *eth = bus->priv;
+ struct sh_eth_info *port_info = ð->port_info[eth->port];
+
+ if (v)
+ sh_eth_write(port_info,
+ sh_eth_read(port_info, PIR) | PIR_MDC, PIR);
+ else
+ sh_eth_write(port_info,
+ sh_eth_read(port_info, PIR) & ~PIR_MDC, PIR);
+
+ return 0;
+}
+
+static int sh_eth_bb_delay(struct bb_miiphy_bus *bus)
+{
+ udelay(10);
+
+ return 0;
+}
+
static int sh_ether_probe(struct udevice *udev)
{
struct eth_pdata *pdata = dev_get_plat(udev);
struct sh_ether_priv *priv = dev_get_priv(udev);
struct sh_eth_dev *eth = &priv->shdev;
+ struct bb_miiphy_bus *bb_miiphy;
struct mii_dev *mdiodev;
int ret;
@@ -658,22 +727,32 @@
if (ret < 0)
return ret;
#endif
- mdiodev = mdio_alloc();
- if (!mdiodev) {
+ bb_miiphy = bb_miiphy_alloc();
+ if (!bb_miiphy) {
ret = -ENOMEM;
return ret;
}
+ mdiodev = &bb_miiphy->mii;
+
mdiodev->read = bb_miiphy_read;
mdiodev->write = bb_miiphy_write;
- bb_miiphy_buses[0].priv = eth;
snprintf(mdiodev->name, sizeof(mdiodev->name), udev->name);
+ /* Copy the bus accessors and private data */
+ bb_miiphy->mdio_active = sh_eth_bb_mdio_active;
+ bb_miiphy->mdio_tristate = sh_eth_bb_mdio_tristate;
+ bb_miiphy->set_mdio = sh_eth_bb_set_mdio;
+ bb_miiphy->get_mdio = sh_eth_bb_get_mdio;
+ bb_miiphy->set_mdc = sh_eth_bb_set_mdc;
+ bb_miiphy->delay = sh_eth_bb_delay;
+ bb_miiphy->priv = eth;
+
ret = mdio_register(mdiodev);
if (ret < 0)
goto err_mdio_register;
- priv->bus = miiphy_get_dev_by_name(udev->name);
+ priv->bus = &bb_miiphy->mii;
eth->port = CFG_SH_ETHER_USE_PORT;
eth->port_info[eth->port].phy_addr = CFG_SH_ETHER_PHY_ADDR;
@@ -703,7 +782,7 @@
clk_disable(&priv->clk);
#endif
err_mdio_register:
- mdio_free(mdiodev);
+ bb_miiphy_free(bb_miiphy);
return ret;
}
@@ -748,8 +827,6 @@
if (cell)
pdata->max_speed = fdt32_to_cpu(*cell);
- sprintf(bb_miiphy_buses[0].name, dev->name);
-
return 0;
}
@@ -775,91 +852,3 @@
.plat_auto = sizeof(struct eth_pdata),
.flags = DM_FLAG_ALLOC_PRIV_DMA,
};
-
-/******* for bb_miiphy *******/
-static int sh_eth_bb_init(struct bb_miiphy_bus *bus)
-{
- return 0;
-}
-
-static int sh_eth_bb_mdio_active(struct bb_miiphy_bus *bus)
-{
- struct sh_eth_dev *eth = bus->priv;
- struct sh_eth_info *port_info = ð->port_info[eth->port];
-
- sh_eth_write(port_info, sh_eth_read(port_info, PIR) | PIR_MMD, PIR);
-
- return 0;
-}
-
-static int sh_eth_bb_mdio_tristate(struct bb_miiphy_bus *bus)
-{
- struct sh_eth_dev *eth = bus->priv;
- struct sh_eth_info *port_info = ð->port_info[eth->port];
-
- sh_eth_write(port_info, sh_eth_read(port_info, PIR) & ~PIR_MMD, PIR);
-
- return 0;
-}
-
-static int sh_eth_bb_set_mdio(struct bb_miiphy_bus *bus, int v)
-{
- struct sh_eth_dev *eth = bus->priv;
- struct sh_eth_info *port_info = ð->port_info[eth->port];
-
- if (v)
- sh_eth_write(port_info,
- sh_eth_read(port_info, PIR) | PIR_MDO, PIR);
- else
- sh_eth_write(port_info,
- sh_eth_read(port_info, PIR) & ~PIR_MDO, PIR);
-
- return 0;
-}
-
-static int sh_eth_bb_get_mdio(struct bb_miiphy_bus *bus, int *v)
-{
- struct sh_eth_dev *eth = bus->priv;
- struct sh_eth_info *port_info = ð->port_info[eth->port];
-
- *v = (sh_eth_read(port_info, PIR) & PIR_MDI) >> 3;
-
- return 0;
-}
-
-static int sh_eth_bb_set_mdc(struct bb_miiphy_bus *bus, int v)
-{
- struct sh_eth_dev *eth = bus->priv;
- struct sh_eth_info *port_info = ð->port_info[eth->port];
-
- if (v)
- sh_eth_write(port_info,
- sh_eth_read(port_info, PIR) | PIR_MDC, PIR);
- else
- sh_eth_write(port_info,
- sh_eth_read(port_info, PIR) & ~PIR_MDC, PIR);
-
- return 0;
-}
-
-static int sh_eth_bb_delay(struct bb_miiphy_bus *bus)
-{
- udelay(10);
-
- return 0;
-}
-
-struct bb_miiphy_bus bb_miiphy_buses[] = {
- {
- .name = "sh_eth",
- .init = sh_eth_bb_init,
- .mdio_active = sh_eth_bb_mdio_active,
- .mdio_tristate = sh_eth_bb_mdio_tristate,
- .set_mdio = sh_eth_bb_set_mdio,
- .get_mdio = sh_eth_bb_get_mdio,
- .set_mdc = sh_eth_bb_set_mdc,
- .delay = sh_eth_bb_delay,
- }
-};
-
-int bb_miiphy_buses_num = ARRAY_SIZE(bb_miiphy_buses);
diff --git a/drivers/pinctrl/pinctrl-at91.c b/drivers/pinctrl/pinctrl-at91.c
index 5038cb5..2938635 100644
--- a/drivers/pinctrl/pinctrl-at91.c
+++ b/drivers/pinctrl/pinctrl-at91.c
@@ -9,6 +9,8 @@
#include <dm.h>
#include <log.h>
#include <asm/global_data.h>
+#include <dm/device-internal.h>
+#include <dm/lists.h>
#include <dm/pinctrl.h>
#include <asm/hardware.h>
#include <linux/bitops.h>
@@ -492,21 +494,58 @@
.set_state = at91_pinctrl_set_state,
};
+/**
+ * at91_pinctrl_bind() - Iterates through all subnodes of the pinctrl device
+ * in the DT and binds them to U-Boot's device model. Each subnode
+ * typically represents a GPIO controller or pin configuration data.
+ *
+ * @dev: Pointer to the pinctrl device
+ *
+ * Returns 0 on success or negative error on failure
+ */
+static int at91_pinctrl_bind(struct udevice *dev)
+{
+ ofnode gpio_node;
+ struct udevice *gpio;
+ int ret;
+
+ ofnode_for_each_subnode(gpio_node, dev_ofnode(dev)) {
+ ret = lists_bind_fdt(dev, gpio_node, &gpio, NULL, false);
+ if (ret)
+ return ret;
+ }
+
+ return 0;
+}
+
static int at91_pinctrl_probe(struct udevice *dev)
{
struct at91_pinctrl_priv *priv = dev_get_priv(dev);
fdt_addr_t addr_base;
+ struct udevice *gpio_node;
int index;
- for (index = 0; index < MAX_GPIO_BANKS; index++) {
- addr_base = devfdt_get_addr_index(dev, index);
- if (addr_base == FDT_ADDR_T_NONE)
- break;
+ if (list_empty(&dev->child_head)) {
+ for (index = 0; index < MAX_GPIO_BANKS; index++) {
+ addr_base = devfdt_get_addr_index(dev, index);
+ if (addr_base == FDT_ADDR_T_NONE)
+ break;
+
+ priv->reg_base[index] = (struct at91_port *)addr_base;
+ }
+ } else {
+ index = 0;
+ list_for_each_entry(gpio_node, &dev->child_head, sibling_node) {
+ addr_base = dev_read_addr(gpio_node);
+ if (addr_base == FDT_ADDR_T_NONE)
+ break;
- priv->reg_base[index] = (struct at91_port *)addr_base;
+ priv->reg_base[index] = (struct at91_port *)addr_base;
+ index++;
+ }
}
- priv->nbanks = index;
+ priv->nbanks = index < MAX_GPIO_BANKS ? index : MAX_GPIO_BANKS;
return 0;
}
@@ -524,6 +563,7 @@
.id = UCLASS_PINCTRL,
.of_match = at91_pinctrl_match,
.probe = at91_pinctrl_probe,
+ .bind = at91_pinctrl_bind,
.priv_auto = sizeof(struct at91_pinctrl_priv),
.ops = &at91_pinctrl_ops,
};
diff --git a/drivers/pinctrl/rockchip/pinctrl-rk3328.c b/drivers/pinctrl/rockchip/pinctrl-rk3328.c
index 47c2e92..dd0dc2e 100644
--- a/drivers/pinctrl/rockchip/pinctrl-rk3328.c
+++ b/drivers/pinctrl/rockchip/pinctrl-rk3328.c
@@ -14,23 +14,68 @@
static struct rockchip_mux_recalced_data rk3328_mux_recalced_data[] = {
{
- .num = 2,
- .pin = 12,
- .reg = 0x24,
- .bit = 8,
- .mask = 0x3
- }, {
+ /* gpio2_b7_sel */
.num = 2,
.pin = 15,
.reg = 0x28,
.bit = 0,
.mask = 0x7
}, {
+ /* gpio2_c7_sel */
.num = 2,
.pin = 23,
.reg = 0x30,
.bit = 14,
.mask = 0x3
+ }, {
+ /* gpio3_b1_sel */
+ .num = 3,
+ .pin = 9,
+ .reg = 0x44,
+ .bit = 2,
+ .mask = 0x3
+ }, {
+ /* gpio3_b2_sel */
+ .num = 3,
+ .pin = 10,
+ .reg = 0x44,
+ .bit = 4,
+ .mask = 0x3
+ }, {
+ /* gpio3_b3_sel */
+ .num = 3,
+ .pin = 11,
+ .reg = 0x44,
+ .bit = 6,
+ .mask = 0x3
+ }, {
+ /* gpio3_b4_sel */
+ .num = 3,
+ .pin = 12,
+ .reg = 0x44,
+ .bit = 8,
+ .mask = 0x3
+ }, {
+ /* gpio3_b5_sel */
+ .num = 3,
+ .pin = 13,
+ .reg = 0x44,
+ .bit = 10,
+ .mask = 0x3
+ }, {
+ /* gpio3_b6_sel */
+ .num = 3,
+ .pin = 14,
+ .reg = 0x44,
+ .bit = 12,
+ .mask = 0x3
+ }, {
+ /* gpio3_b7_sel */
+ .num = 3,
+ .pin = 15,
+ .reg = 0x44,
+ .bit = 14,
+ .mask = 0x3
},
};
@@ -275,7 +320,7 @@
PIN_BANK_IOMUX_FLAGS(0, 32, "gpio0", 0, 0, 0, 0),
PIN_BANK_IOMUX_FLAGS(1, 32, "gpio1", 0, 0, 0, 0),
PIN_BANK_IOMUX_FLAGS(2, 32, "gpio2", 0,
- IOMUX_WIDTH_3BIT,
+ IOMUX_8WIDTH_2BIT,
IOMUX_WIDTH_3BIT,
0),
PIN_BANK_IOMUX_FLAGS(3, 32, "gpio3",
diff --git a/drivers/pinctrl/tegra/pinctrl-tegra20.c b/drivers/pinctrl/tegra/pinctrl-tegra20.c
index d5171b8..d59b3ec 100644
--- a/drivers/pinctrl/tegra/pinctrl-tegra20.c
+++ b/drivers/pinctrl/tegra/pinctrl-tegra20.c
@@ -97,9 +97,9 @@
* then actual pins setup (with node name prefix
* conf_*) and then drive setup.
*/
- if (!strncmp(child->name, "conf_", 5))
+ if (!strncmp(child->name, "conf", 4))
tegra_pinctrl_set_pin(child);
- else if (!strncmp(child->name, "drive_", 6))
+ else if (!strncmp(child->name, "drive", 5))
debug("%s: drive configuration is not supported\n", __func__);
else
tegra_pinctrl_set_func(child);
diff --git a/drivers/power/pmic/max77663.c b/drivers/power/pmic/max77663.c
index cf08b6a..c2a7cbf 100644
--- a/drivers/power/pmic/max77663.c
+++ b/drivers/power/pmic/max77663.c
@@ -47,8 +47,9 @@
int children, ret;
if (IS_ENABLED(CONFIG_SYSRESET_MAX77663)) {
- ret = device_bind_driver(dev, MAX77663_RST_DRIVER,
- "sysreset", NULL);
+ ret = device_bind_driver_to_node(dev, MAX77663_RST_DRIVER,
+ "sysreset", dev_ofnode(dev),
+ NULL);
if (ret) {
log_err("cannot bind SYSRESET (ret = %d)\n", ret);
return ret;
@@ -56,8 +57,8 @@
}
if (IS_ENABLED(CONFIG_MAX77663_GPIO)) {
- ret = device_bind_driver(dev, MAX77663_GPIO_DRIVER,
- "gpio", NULL);
+ ret = device_bind_driver_to_node(dev, MAX77663_GPIO_DRIVER,
+ "gpio", dev_ofnode(dev), NULL);
if (ret) {
log_err("cannot bind GPIOs (ret = %d)\n", ret);
return ret;
diff --git a/drivers/power/pmic/palmas.c b/drivers/power/pmic/palmas.c
index f676bf6..37d4190 100644
--- a/drivers/power/pmic/palmas.c
+++ b/drivers/power/pmic/palmas.c
@@ -49,8 +49,9 @@
int children, ret;
if (IS_ENABLED(CONFIG_SYSRESET_PALMAS)) {
- ret = device_bind_driver(dev, PALMAS_RST_DRIVER,
- "sysreset", NULL);
+ ret = device_bind_driver_to_node(dev, PALMAS_RST_DRIVER,
+ "sysreset", dev_ofnode(dev),
+ NULL);
if (ret) {
log_err("cannot bind SYSRESET (ret = %d)\n", ret);
return ret;
diff --git a/drivers/power/regulator/tps65941_regulator.c b/drivers/power/regulator/tps65941_regulator.c
index bc4d153..13f94b7 100644
--- a/drivers/power/regulator/tps65941_regulator.c
+++ b/drivers/power/regulator/tps65941_regulator.c
@@ -388,6 +388,14 @@
return 0;
}
+static int tps65941_ldo_volt2val(__maybe_unused int idx, int uV)
+{
+ if (uV > TPS65941_LDO_VOLT_MAX || uV < TPS65941_LDO_VOLT_MIN)
+ return -EINVAL;
+
+ return ((uV - 600000) / 50000 + 0x4) << TPS65941_LDO_MODE_MASK;
+}
+
static int tps65941_ldo_val2volt(__maybe_unused int idx, int val)
{
if (val > TPS65941_LDO_VOLT_MAX_HEX || val < TPS65941_LDO_VOLT_MIN_HEX)
@@ -459,7 +467,7 @@
static const struct tps65941_reg_conv_ops ldo_conv_ops[] = {
[TPS65941_LDO_CONV_OPS_IDX] = {
.volt_mask = TPS65941_LDO_VOLT_MASK,
- .volt2val = tps65941_buck_volt2val,
+ .volt2val = tps65941_ldo_volt2val,
.val2volt = tps65941_ldo_val2volt,
},
[TPS65224_LDO_CONV_OPS_IDX] = {
@@ -472,7 +480,7 @@
static int tps65941_ldo_val(struct udevice *dev, int op, int *uV)
{
unsigned int hex, adr;
- int ret, ret_volt, idx;
+ int ret, ret_volt, idx, ldo_bypass;
struct dm_regulator_uclass_plat *uc_pdata;
const struct tps65941_reg_conv_ops *conv_ops;
ulong chip_id;
@@ -502,7 +510,9 @@
if (ret < 0)
return ret;
+ ldo_bypass = ret & TPS65941_LDO_BYPASS_EN;
ret &= conv_ops->volt_mask;
+ ret = ret >> TPS65941_LDO_MODE_MASK;
ret_volt = conv_ops->val2volt(idx, ret);
if (ret_volt < 0)
return ret_volt;
@@ -531,7 +541,7 @@
ret &= ~TPS65224_LDO_VOLT_MASK;
ret |= hex;
} else {
- ret = hex;
+ ret = hex | ldo_bypass;
}
ret = pmic_reg_write(dev->parent, adr, ret);
diff --git a/drivers/remoteproc/ti_k3_dsp_rproc.c b/drivers/remoteproc/ti_k3_dsp_rproc.c
index e90f75a..5a7d637 100644
--- a/drivers/remoteproc/ti_k3_dsp_rproc.c
+++ b/drivers/remoteproc/ti_k3_dsp_rproc.c
@@ -15,6 +15,7 @@
#include <clk.h>
#include <reset.h>
#include <asm/io.h>
+#include <asm/system.h>
#include <power-domain.h>
#include <dm/device_compat.h>
#include <linux/err.h>
@@ -56,7 +57,9 @@
* @data: Pointer to DSP specific boot data structure
* @mem: Array of available memories
* @num_mem: Number of available memories
- * @in_use: flag to tell if the core is already in use.
+ * @cached_addr: Cached memory address
+ * @cached_size: Cached memory size
+ * @in_use: flag to tell if the core is already in use.
*/
struct k3_dsp_privdata {
struct reset_ctl dsp_rst;
@@ -64,6 +67,8 @@
struct k3_dsp_boot_data *data;
struct k3_dsp_mem *mem;
int num_mems;
+ void __iomem *cached_addr;
+ size_t cached_size;
bool in_use;
};
@@ -158,6 +163,13 @@
goto unprepare;
}
+ if (dsp->cached_addr && IS_ENABLED(CONFIG_SYS_DISABLE_DCACHE_OPS)) {
+ dev_dbg(dev, "final flush 0x%lx to 0x%lx\n",
+ (ulong)dsp->cached_addr, dsp->cached_size);
+ __asm_invalidate_dcache_range((u64)dsp->cached_addr,
+ (u64)dsp->cached_addr + (u64)dsp->cached_size);
+ }
+
boot_vector = rproc_elf_get_boot_addr(dev, addr);
if (boot_vector & (data->boot_align_addr - 1)) {
ret = -EINVAL;
@@ -253,7 +265,6 @@
{
struct k3_dsp_privdata *dsp = dev_get_priv(dev);
phys_addr_t bus_addr, dev_addr;
- void __iomem *va = NULL;
size_t size;
u32 offset;
int i;
@@ -263,6 +274,16 @@
if (len <= 0)
return NULL;
+ if (dsp->cached_addr && IS_ENABLED(CONFIG_SYS_DISABLE_DCACHE_OPS)) {
+ dev_dbg(dev, "flush 0x%lx to 0x%lx\n", (ulong)dsp->cached_addr,
+ dsp->cached_size);
+ __asm_invalidate_dcache_range((u64)dsp->cached_addr,
+ (u64)dsp->cached_addr + (u64)dsp->cached_size);
+ }
+
+ dsp->cached_size = len;
+ dsp->cached_addr = NULL;
+
for (i = 0; i < dsp->num_mems; i++) {
bus_addr = dsp->mem[i].bus_addr;
dev_addr = dsp->mem[i].dev_addr;
@@ -270,19 +291,20 @@
if (da >= dev_addr && ((da + len) <= (dev_addr + size))) {
offset = da - dev_addr;
- va = dsp->mem[i].cpu_addr + offset;
- return (__force void *)va;
+ dsp->cached_addr = dsp->mem[i].cpu_addr + offset;
}
if (da >= bus_addr && (da + len) <= (bus_addr + size)) {
offset = da - bus_addr;
- va = dsp->mem[i].cpu_addr + offset;
- return (__force void *)va;
+ dsp->cached_addr = dsp->mem[i].cpu_addr + offset;
}
}
/* Assume it is DDR region and return da */
- return map_physmem(da, len, MAP_NOCACHE);
+ if (!dsp->cached_addr)
+ dsp->cached_addr = map_physmem(da, len, MAP_NOCACHE);
+
+ return dsp->cached_addr;
}
static const struct dm_rproc_ops k3_dsp_ops = {
diff --git a/drivers/serial/ns16550.c b/drivers/serial/ns16550.c
index 0e267d0..7e460f6 100644
--- a/drivers/serial/ns16550.c
+++ b/drivers/serial/ns16550.c
@@ -112,9 +112,9 @@
} else if (plat->reg_width == 4) {
if (plat->flags & NS16550_FLAG_ENDIAN) {
if (plat->flags & NS16550_FLAG_BE)
- out_be32(addr, value);
+ out_be32((u32 *)addr, value);
else
- out_le32(addr, value);
+ out_le32((u32 *)addr, value);
} else {
writel(value, addr);
}
@@ -132,9 +132,9 @@
} else if (plat->reg_width == 4) {
if (plat->flags & NS16550_FLAG_ENDIAN) {
if (plat->flags & NS16550_FLAG_BE)
- return in_be32(addr);
+ return in_be32((u32 *)addr);
else
- return in_le32(addr);
+ return in_le32((u32 *)addr);
} else {
return readl(addr);
}
diff --git a/drivers/spi/Kconfig b/drivers/spi/Kconfig
index 96ea033..a916b71 100644
--- a/drivers/spi/Kconfig
+++ b/drivers/spi/Kconfig
@@ -85,7 +85,7 @@
config ATMEL_QSPI
bool "Atmel Quad SPI Controller"
- depends on ARCH_AT91
+ depends on ARCH_AT91 && SPI_MEM
help
Enable the Atmel Quad SPI controller in master mode. This driver
does not support generic SPI. The implementation supports only the
@@ -135,7 +135,7 @@
config CORTINA_SFLASH
bool "Cortina-Access Serial Flash controller driver"
- depends on DM_SPI && SPI_MEM
+ depends on SPI_MEM
help
Enable the Cortina-Access Serial Flash controller driver. This driver
can be used to access the SPI NOR/NAND flash on platforms embedding this
diff --git a/drivers/spi/atmel-quadspi.c b/drivers/spi/atmel-quadspi.c
index 3efb661..8aa7a83 100644
--- a/drivers/spi/atmel-quadspi.c
+++ b/drivers/spi/atmel-quadspi.c
@@ -10,11 +10,13 @@
*/
#include <malloc.h>
+#include <asm/gpio.h>
#include <asm/io.h>
#include <clk.h>
#include <dm.h>
#include <errno.h>
#include <fdtdec.h>
+#include <log.h>
#include <dm/device_compat.h>
#include <linux/bitfield.h>
#include <linux/bitops.h>
@@ -258,6 +260,7 @@
struct atmel_qspi_priv_ops;
+#define MAX_CS_COUNT 2
struct atmel_qspi {
void __iomem *regs;
void __iomem *mem;
@@ -267,6 +270,7 @@
struct udevice *dev;
ulong bus_clk_rate;
u32 mr;
+ struct gpio_desc cs_gpios[MAX_CS_COUNT];
};
struct atmel_qspi_priv_ops {
@@ -395,6 +399,26 @@
writel(value, aq->regs + offset);
}
+static int atmel_qspi_reg_sync(struct atmel_qspi *aq)
+{
+ u32 val;
+
+ return readl_poll_timeout(aq->regs + QSPI_SR2, val,
+ !(val & QSPI_SR2_SYNCBSY),
+ ATMEL_QSPI_SYNC_TIMEOUT);
+}
+
+static int atmel_qspi_update_config(struct atmel_qspi *aq)
+{
+ int ret;
+
+ ret = atmel_qspi_reg_sync(aq);
+ if (ret)
+ return ret;
+ atmel_qspi_write(QSPI_CR_UPDCFG, aq, QSPI_CR);
+ return atmel_qspi_reg_sync(aq);
+}
+
static inline bool atmel_qspi_is_compatible(const struct spi_mem_op *op,
const struct atmel_qspi_mode *mode)
{
@@ -458,6 +482,29 @@
return true;
}
+/*
+ * Switch QSPI controller between regular SPI mode or Serial Memory Mode (SMM).
+ */
+static int atmel_qspi_set_serial_memory_mode(struct atmel_qspi *aq,
+ bool enable)
+{
+ int ret = 0;
+
+ /* only write if designated state differs from current state */
+ if (!!(aq->mr & QSPI_MR_SMM) != enable) {
+ if (enable)
+ aq->mr |= QSPI_MR_SMM;
+ else
+ aq->mr &= ~QSPI_MR_SMM;
+ atmel_qspi_write(aq->mr, aq, QSPI_MR);
+
+ if (aq->caps->has_gclk)
+ ret = atmel_qspi_update_config(aq);
+ }
+
+ return ret;
+}
+
static int atmel_qspi_set_cfg(struct atmel_qspi *aq,
const struct spi_mem_op *op, u32 *offset)
{
@@ -474,7 +521,7 @@
return mode;
ifr |= atmel_qspi_modes[mode].config;
- if (op->dummy.buswidth && op->dummy.nbytes)
+ if (op->dummy.nbytes)
dummy_cycles = op->dummy.nbytes * 8 / op->dummy.buswidth;
/*
@@ -529,43 +576,39 @@
if (dummy_cycles)
ifr |= QSPI_IFR_NBDUM(dummy_cycles);
- /* Set data enable */
- if (op->data.nbytes)
+ /* Set data enable and data transfer type. */
+ if (op->data.nbytes) {
ifr |= QSPI_IFR_DATAEN;
- /*
- * If the QSPI controller is set in regular SPI mode, set it in
- * Serial Memory Mode (SMM).
- */
- if (aq->mr != QSPI_MR_SMM) {
- atmel_qspi_write(QSPI_MR_SMM, aq, QSPI_MR);
- aq->mr = QSPI_MR_SMM;
+ if (op->addr.nbytes)
+ ifr |= QSPI_IFR_TFRTYP_MEM;
}
+ mode = atmel_qspi_set_serial_memory_mode(aq, true);
+ if (mode < 0)
+ return mode;
+
/* Clear pending interrupts */
(void)atmel_qspi_read(aq, QSPI_SR);
- if (aq->caps->has_ricr) {
- if (!op->addr.nbytes && op->data.dir == SPI_MEM_DATA_IN)
- ifr |= QSPI_IFR_APBTFRTYP_READ;
-
- /* Set QSPI Instruction Frame registers */
+ /* Set QSPI Instruction Frame registers. */
+ if (op->addr.nbytes && !op->data.nbytes)
atmel_qspi_write(iar, aq, QSPI_IAR);
+
+ if (aq->caps->has_ricr) {
if (op->data.dir == SPI_MEM_DATA_IN)
atmel_qspi_write(icr, aq, QSPI_RICR);
else
atmel_qspi_write(icr, aq, QSPI_WICR);
- atmel_qspi_write(ifr, aq, QSPI_IFR);
} else {
- if (op->data.dir == SPI_MEM_DATA_OUT)
+ if (op->data.nbytes && op->data.dir == SPI_MEM_DATA_OUT)
ifr |= QSPI_IFR_SAMA5D2_WRITE_TRSFR;
- /* Set QSPI Instruction Frame registers */
- atmel_qspi_write(iar, aq, QSPI_IAR);
atmel_qspi_write(icr, aq, QSPI_ICR);
- atmel_qspi_write(ifr, aq, QSPI_IFR);
}
+ atmel_qspi_write(ifr, aq, QSPI_IFR);
+
return 0;
}
@@ -597,26 +640,6 @@
ATMEL_QSPI_TIMEOUT);
}
-static int atmel_qspi_reg_sync(struct atmel_qspi *aq)
-{
- u32 val;
-
- return readl_poll_timeout(aq->regs + QSPI_SR2, val,
- !(val & QSPI_SR2_SYNCBSY),
- ATMEL_QSPI_SYNC_TIMEOUT);
-}
-
-static int atmel_qspi_update_config(struct atmel_qspi *aq)
-{
- int ret;
-
- ret = atmel_qspi_reg_sync(aq);
- if (ret)
- return ret;
- atmel_qspi_write(QSPI_CR_UPDCFG, aq, QSPI_CR);
- return atmel_qspi_reg_sync(aq);
-}
-
static int atmel_qspi_sama7g5_set_cfg(struct atmel_qspi *aq,
const struct spi_mem_op *op, u32 *offset)
{
@@ -668,17 +691,9 @@
ifr |= QSPI_IFR_TFRTYP_MEM;
}
- /*
- * If the QSPI controller is set in regular SPI mode, set it in
- * Serial Memory Mode (SMM).
- */
- if (aq->mr != QSPI_MR_SMM) {
- atmel_qspi_write(QSPI_MR_SMM | QSPI_MR_DQSDLYEN, aq, QSPI_MR);
- ret = atmel_qspi_update_config(aq);
- if (ret)
- return ret;
- aq->mr = QSPI_MR_SMM;
- }
+ ret = atmel_qspi_set_serial_memory_mode(aq, true);
+ if (ret < 0)
+ return ret;
/* Clear pending interrupts */
(void)atmel_qspi_read(aq, QSPI_SR);
@@ -902,11 +917,10 @@
}
/* Set the QSPI controller by default in Serial Memory Mode */
- atmel_qspi_write(QSPI_MR_SMM | QSPI_MR_DQSDLYEN, aq, QSPI_MR);
- ret = atmel_qspi_update_config(aq);
- if (ret)
+ aq->mr |= QSPI_MR_DQSDLYEN;
+ ret = atmel_qspi_set_serial_memory_mode(aq, true);
+ if (ret < 0)
return ret;
- aq->mr = QSPI_MR_SMM;
/* Enable the QSPI controller. */
ret = atmel_qspi_reg_sync(aq);
@@ -930,6 +944,135 @@
return ret;
}
+static int atmel_qspi_claim_bus(struct udevice *dev)
+{
+ struct udevice *bus = dev_get_parent(dev);
+ struct atmel_qspi *aq = dev_get_priv(bus);
+ int ret;
+
+ aq->mr &= ~QSPI_MR_CSMODE_MASK;
+ aq->mr |= QSPI_MR_CSMODE_LASTXFER | QSPI_MR_WDRBT;
+ atmel_qspi_write(aq->mr, aq, QSPI_MR);
+
+ ret = atmel_qspi_set_serial_memory_mode(aq, false);
+ if (ret)
+ return log_ret(ret);
+
+ /* de-assert all chip selects */
+ if (IS_ENABLED(CONFIG_DM_GPIO)) {
+ for (int i = 0; i < ARRAY_SIZE(aq->cs_gpios); i++) {
+ if (dm_gpio_is_valid(&aq->cs_gpios[i]))
+ dm_gpio_set_value(&aq->cs_gpios[i], 0);
+ }
+ }
+
+ atmel_qspi_write(QSPI_CR_QSPIEN, aq, QSPI_CR);
+
+ return 0;
+}
+
+static int atmel_qspi_release_bus(struct udevice *dev)
+{
+ struct udevice *bus = dev_get_parent(dev);
+ struct atmel_qspi *aq = dev_get_priv(bus);
+
+ /* de-assert all chip selects */
+ if (IS_ENABLED(CONFIG_DM_GPIO)) {
+ for (int i = 0; i < ARRAY_SIZE(aq->cs_gpios); i++) {
+ if (dm_gpio_is_valid(&aq->cs_gpios[i]))
+ dm_gpio_set_value(&aq->cs_gpios[i], 0);
+ }
+ }
+
+ atmel_qspi_write(QSPI_CR_QSPIDIS, aq, QSPI_CR);
+
+ return 0;
+}
+
+static int atmel_qspi_set_cs(struct udevice *dev, int value)
+{
+ struct udevice *bus = dev_get_parent(dev);
+ struct atmel_qspi *aq = dev_get_priv(bus);
+ int cs = spi_chip_select(dev);
+
+ if (IS_ENABLED(CONFIG_DM_GPIO)) {
+ if (!dm_gpio_is_valid(&aq->cs_gpios[cs]))
+ return log_ret(-ENOENT);
+
+ return dm_gpio_set_value(&aq->cs_gpios[cs], value);
+ } else {
+ return -ENOENT;
+ }
+}
+
+static int atmel_qspi_xfer(struct udevice *dev, unsigned int bitlen,
+ const void *dout, void *din, unsigned long flags)
+{
+ struct udevice *bus = dev_get_parent(dev);
+ struct atmel_qspi *aq = dev_get_priv(bus);
+ unsigned int len, len_rx, len_tx;
+ const u8 *txp = dout;
+ u8 *rxp = din;
+ u32 reg;
+ int ret;
+
+ if (bitlen == 0)
+ goto out;
+
+ if (bitlen % 8) {
+ flags |= SPI_XFER_END;
+ goto out;
+ }
+
+ len = bitlen / 8;
+
+ if (flags & SPI_XFER_BEGIN) {
+ ret = atmel_qspi_set_cs(dev, 1);
+ if (ret)
+ return log_ret(ret);
+ reg = atmel_qspi_read(aq, QSPI_RD);
+ }
+
+ for (len_tx = 0, len_rx = 0; len_rx < len; ) {
+ u32 status = atmel_qspi_read(aq, QSPI_SR);
+ u8 value;
+
+ if (status & QSPI_SR_OVRES)
+ return log_ret(-1);
+
+ if (len_tx < len && (status & QSPI_SR_TDRE)) {
+ if (txp)
+ value = *txp++;
+ else
+ value = 0;
+ atmel_qspi_write(value, aq, QSPI_TD);
+ len_tx++;
+ }
+
+ if (status & QSPI_SR_RDRF) {
+ value = atmel_qspi_read(aq, QSPI_RD);
+ if (rxp)
+ *rxp++ = value;
+ len_rx++;
+ }
+ }
+
+out:
+ if (flags & SPI_XFER_END) {
+ readl_poll_timeout(aq->regs + QSPI_SR, reg,
+ reg & QSPI_SR_TXEMPTY,
+ ATMEL_QSPI_TIMEOUT);
+
+ atmel_qspi_write(QSPI_CR_LASTXFER, aq, QSPI_CR);
+
+ ret = atmel_qspi_set_cs(dev, 0);
+ if (ret)
+ return log_ret(ret);
+ }
+
+ return 0;
+}
+
static int atmel_qspi_set_speed(struct udevice *bus, uint hz)
{
struct atmel_qspi *aq = dev_get_priv(bus);
@@ -939,6 +1082,7 @@
return atmel_qspi_sama7g5_set_speed(bus, hz);
/* Compute the QSPI baudrate */
+ dev_dbg(bus, "bus_clk_rate: %lu, hz: %u\n", aq->bus_clk_rate, hz);
scbr = DIV_ROUND_UP(aq->bus_clk_rate, hz);
if (scbr > 0)
scbr--;
@@ -1046,10 +1190,6 @@
/* Reset the QSPI controller */
atmel_qspi_write(QSPI_CR_SWRST, aq, QSPI_CR);
- /* Set the QSPI controller by default in Serial Memory Mode */
- atmel_qspi_write(QSPI_MR_SMM, aq, QSPI_MR);
- aq->mr = QSPI_MR_SMM;
-
/* Enable the QSPI controller */
atmel_qspi_write(QSPI_CR_QSPIEN, aq, QSPI_CR);
@@ -1075,7 +1215,7 @@
aq->caps = (struct atmel_qspi_caps *)dev_get_driver_data(dev);
if (!aq->caps) {
dev_err(dev, "Could not retrieve QSPI caps\n");
- return -EINVAL;
+ return log_ret(-EINVAL);
};
if (aq->caps->has_gclk)
@@ -1083,36 +1223,53 @@
else
aq->ops = &atmel_qspi_priv_ops;
+ if (IS_ENABLED(CONFIG_DM_GPIO)) {
+ ret = gpio_request_list_by_name(dev, "cs-gpios", aq->cs_gpios,
+ ARRAY_SIZE(aq->cs_gpios), 0);
+ if (ret < 0) {
+ pr_err("Can't get %s gpios! Error: %d", dev->name, ret);
+ return log_ret(ret);
+ }
+
+ for (int i = 0; i < ARRAY_SIZE(aq->cs_gpios); i++) {
+ if (!dm_gpio_is_valid(&aq->cs_gpios[i]))
+ continue;
+
+ dm_gpio_set_dir_flags(&aq->cs_gpios[i],
+ GPIOD_IS_OUT | GPIOD_IS_OUT_ACTIVE);
+ }
+ }
+
/* Map the registers */
ret = dev_read_resource_byname(dev, "qspi_base", &res);
if (ret) {
dev_err(dev, "missing registers\n");
- return ret;
+ return log_ret(ret);
}
aq->regs = devm_ioremap(dev, res.start, resource_size(&res));
if (IS_ERR(aq->regs))
- return PTR_ERR(aq->regs);
+ return log_ret(PTR_ERR(aq->regs));
/* Map the AHB memory */
ret = dev_read_resource_byname(dev, "qspi_mmap", &res);
if (ret) {
dev_err(dev, "missing AHB memory\n");
- return ret;
+ return log_ret(ret);
}
aq->mem = devm_ioremap(dev, res.start, resource_size(&res));
if (IS_ERR(aq->mem))
- return PTR_ERR(aq->mem);
+ return log_ret(PTR_ERR(aq->mem));
aq->mmap_size = resource_size(&res);
ret = atmel_qspi_enable_clk(dev);
if (ret)
- return ret;
+ return log_ret(ret);
aq->dev = dev;
- return atmel_qspi_init(aq);
+ return log_ret(atmel_qspi_init(aq));
}
static const struct spi_controller_mem_ops atmel_qspi_mem_ops = {
@@ -1121,9 +1278,12 @@
};
static const struct dm_spi_ops atmel_qspi_ops = {
+ .claim_bus = atmel_qspi_claim_bus,
+ .release_bus = atmel_qspi_release_bus,
+ .xfer = atmel_qspi_xfer,
+ .mem_ops = &atmel_qspi_mem_ops,
.set_speed = atmel_qspi_set_speed,
.set_mode = atmel_qspi_set_mode,
- .mem_ops = &atmel_qspi_mem_ops,
};
static const struct atmel_qspi_caps atmel_sama5d2_qspi_caps = {};
diff --git a/drivers/sysinfo/Kconfig b/drivers/sysinfo/Kconfig
index 2030e4b..df83df6 100644
--- a/drivers/sysinfo/Kconfig
+++ b/drivers/sysinfo/Kconfig
@@ -31,6 +31,13 @@
help
Support querying SoC version information for Renesas R-Car Gen3.
+config SYSINFO_IOT2050
+ bool "Enable sysinfo driver for the Siemens IOT2050"
+ depends on TARGET_IOT2050_A53
+ default y if TARGET_IOT2050_A53
+ help
+ Support querying device information for Siemens IOT2050.
+
config SYSINFO_SANDBOX
bool "Enable sysinfo driver for the Sandbox board"
help
diff --git a/drivers/sysinfo/Makefile b/drivers/sysinfo/Makefile
index 680dde7..26ca315 100644
--- a/drivers/sysinfo/Makefile
+++ b/drivers/sysinfo/Makefile
@@ -5,6 +5,7 @@
obj-y += sysinfo-uclass.o
obj-$(CONFIG_SYSINFO_GAZERBEAM) += gazerbeam.o
obj-$(CONFIG_SYSINFO_GPIO) += gpio.o
+obj-$(CONFIG_SYSINFO_IOT2050) += iot2050.o
obj-$(CONFIG_SYSINFO_RCAR3) += rcar3.o
obj-$(CONFIG_SYSINFO_SANDBOX) += sandbox.o
obj-$(CONFIG_SYSINFO_SMBIOS) += smbios.o
diff --git a/drivers/sysinfo/iot2050.c b/drivers/sysinfo/iot2050.c
new file mode 100644
index 0000000..579a9f4
--- /dev/null
+++ b/drivers/sysinfo/iot2050.c
@@ -0,0 +1,202 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (c) Siemens AG, 2025
+ */
+
+#include <dm.h>
+#include <sysinfo.h>
+#include <net.h>
+#include <u-boot/uuid.h>
+#include <asm/arch/hardware.h>
+
+#include "iot2050.h"
+
+#define IOT2050_INFO_MAGIC 0x20502050
+
+#define IOT2050_UUID_STR_LEN (32)
+
+struct iot2050_info {
+ u32 magic;
+ u16 size;
+ char name[20 + 1];
+ char serial[16 + 1];
+ char mlfb[18 + 1];
+ char uuid[IOT2050_UUID_STR_LEN + 1];
+ char a5e[18 + 1];
+ u8 mac_addr_cnt;
+ u8 mac_addr[8][ARP_HLEN];
+ char seboot_version[40 + 1];
+ u8 padding[3];
+ u32 ddr_size_mb;
+} __packed;
+
+/**
+ * struct sysinfo_iot2050_priv - sysinfo private data
+ * @info: iot2050 board info
+ */
+struct sysinfo_iot2050_priv {
+ struct iot2050_info *info;
+ u8 uuid_smbios[16];
+};
+
+static int sysinfo_iot2050_detect(struct udevice *dev)
+{
+ struct sysinfo_iot2050_priv *priv = dev_get_priv(dev);
+
+ if (!priv->info || priv->info->magic != IOT2050_INFO_MAGIC)
+ return -EFAULT;
+
+ return 0;
+}
+
+static int sysinfo_iot2050_get_str(struct udevice *dev, int id, size_t size,
+ char *val)
+{
+ struct sysinfo_iot2050_priv *priv = dev_get_priv(dev);
+
+ switch (id) {
+ case BOARD_NAME:
+ case SYSID_SM_BASEBOARD_VERSION:
+ strlcpy(val, priv->info->name, size);
+ break;
+ case SYSID_SM_SYSTEM_SERIAL:
+ strlcpy(val, priv->info->serial, size);
+ break;
+ case BOARD_MLFB:
+ case SYSID_SM_SYSTEM_VERSION:
+ strlcpy(val, priv->info->mlfb, size);
+ break;
+ case BOARD_UUID:
+ strlcpy(val, priv->info->uuid, size);
+ break;
+ case BOARD_A5E:
+ case SYSID_SM_BASEBOARD_PRODUCT:
+ strlcpy(val, priv->info->a5e, size);
+ break;
+ case BOARD_SEBOOT_VER:
+ case SYSID_PRIOR_STAGE_VERSION:
+ strlcpy(val, priv->info->seboot_version, size);
+ break;
+ default:
+ return -EINVAL;
+ };
+
+ val[size - 1] = '\0';
+ return 0;
+}
+
+static int sysinfo_iot2050_get_int(struct udevice *dev, int id, int *val)
+{
+ struct sysinfo_iot2050_priv *priv = dev_get_priv(dev);
+
+ switch (id) {
+ case SYSID_BOARD_RAM_SIZE_MB:
+ *val = priv->info->ddr_size_mb;
+ return 0;
+ default:
+ return -EINVAL;
+ };
+}
+
+static int sysinfo_iot2050_get_data(struct udevice *dev, int id, void **data,
+ size_t *size)
+{
+ struct sysinfo_iot2050_priv *priv = dev_get_priv(dev);
+
+ switch (id) {
+ case SYSID_SM_SYSTEM_UUID:
+ *data = priv->uuid_smbios;
+ *size = 16;
+ return 0;
+ default:
+ return -EINVAL;
+ };
+}
+
+static int sysinfo_iot2050_get_item_count(struct udevice *dev, int id)
+{
+ struct sysinfo_iot2050_priv *priv = dev_get_priv(dev);
+
+ switch (id) {
+ case SYSID_BOARD_MAC_ADDR:
+ return priv->info->mac_addr_cnt;
+ default:
+ return -EINVAL;
+ };
+}
+
+static int sysinfo_iot2050_get_data_by_index(struct udevice *dev, int id,
+ int index, void **data,
+ size_t *size)
+{
+ struct sysinfo_iot2050_priv *priv = dev_get_priv(dev);
+
+ switch (id) {
+ case SYSID_BOARD_MAC_ADDR:
+ if (index >= priv->info->mac_addr_cnt)
+ return -EINVAL;
+ *data = priv->info->mac_addr[index];
+ *size = ARP_HLEN;
+ return 0;
+ default:
+ return -EINVAL;
+ };
+}
+
+static const struct sysinfo_ops sysinfo_iot2050_ops = {
+ .detect = sysinfo_iot2050_detect,
+ .get_str = sysinfo_iot2050_get_str,
+ .get_int = sysinfo_iot2050_get_int,
+ .get_data = sysinfo_iot2050_get_data,
+ .get_item_count = sysinfo_iot2050_get_item_count,
+ .get_data_by_index = sysinfo_iot2050_get_data_by_index,
+};
+
+/**
+ * @brief Convert the IOT2050 UUID string to the SMBIOS format
+ *
+ * @param uuid_raw The IOT2050 UUID string parsed from the eeprom
+ * @param uuid_smbios The buffer to hold the SMBIOS formatted UUID
+ */
+static void sysinfo_iot2050_convert_uuid(const char *uuid_iot2050,
+ u8 *uuid_smbios)
+{
+ char uuid_rfc4122_str[IOT2050_UUID_STR_LEN + 4 + 1] = {0};
+ char *tmp = uuid_rfc4122_str;
+
+ for (int i = 0; i < 16; i++) {
+ memcpy(tmp, uuid_iot2050 + i * 2, 2);
+ tmp += 2;
+ if (i == 3 || i == 5 || i == 7 || i == 9)
+ *tmp++ = '-';
+ }
+ uuid_str_to_bin(uuid_rfc4122_str, uuid_smbios, UUID_STR_FORMAT_GUID);
+}
+
+static int sysinfo_iot2050_probe(struct udevice *dev)
+{
+ struct sysinfo_iot2050_priv *priv = dev_get_priv(dev);
+ unsigned long offset;
+
+ offset = dev_read_u32_default(dev, "offset",
+ TI_SRAM_SCRATCH_BOARD_EEPROM_START);
+ priv->info = (struct iot2050_info *)offset;
+
+ sysinfo_iot2050_convert_uuid(priv->info->uuid, priv->uuid_smbios);
+
+ return 0;
+}
+
+static const struct udevice_id sysinfo_iot2050_ids[] = {
+ { .compatible = "siemens,sysinfo-iot2050" },
+ { /* sentinel */ }
+};
+
+U_BOOT_DRIVER(sysinfo_iot2050) = {
+ .name = "sysinfo_iot2050",
+ .id = UCLASS_SYSINFO,
+ .of_match = sysinfo_iot2050_ids,
+ .ops = &sysinfo_iot2050_ops,
+ .priv_auto = sizeof(struct sysinfo_iot2050_priv),
+ .probe = sysinfo_iot2050_probe,
+};
diff --git a/drivers/sysinfo/iot2050.h b/drivers/sysinfo/iot2050.h
new file mode 100644
index 0000000..657221d
--- /dev/null
+++ b/drivers/sysinfo/iot2050.h
@@ -0,0 +1,14 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Copyright (c) Siemens AG, 2025
+ */
+
+#include <sysinfo.h>
+
+enum sysinfo_id_iot2050 {
+ BOARD_MLFB = SYSID_USER,
+ BOARD_A5E,
+ BOARD_NAME,
+ BOARD_UUID,
+ BOARD_SEBOOT_VER,
+};
diff --git a/drivers/sysinfo/sysinfo-uclass.c b/drivers/sysinfo/sysinfo-uclass.c
index 3c0cd51..f04998e 100644
--- a/drivers/sysinfo/sysinfo-uclass.c
+++ b/drivers/sysinfo/sysinfo-uclass.c
@@ -119,6 +119,35 @@
return ops->get_data(dev, id, data, size);
}
+int sysinfo_get_item_count(struct udevice *dev, int id)
+{
+ struct sysinfo_priv *priv = dev_get_uclass_priv(dev);
+ struct sysinfo_ops *ops = sysinfo_get_ops(dev);
+
+ if (!priv->detected)
+ return -EPERM;
+
+ if (!ops->get_item_count)
+ return -ENOSYS;
+
+ return ops->get_item_count(dev, id);
+}
+
+int sysinfo_get_data_by_index(struct udevice *dev, int id, int index,
+ void **data, size_t *size)
+{
+ struct sysinfo_priv *priv = dev_get_uclass_priv(dev);
+ struct sysinfo_ops *ops = sysinfo_get_ops(dev);
+
+ if (!priv->detected)
+ return -EPERM;
+
+ if (!ops->get_data_by_index)
+ return -ENOSYS;
+
+ return ops->get_data_by_index(dev, id, index, data, size);
+}
+
UCLASS_DRIVER(sysinfo) = {
.id = UCLASS_SYSINFO,
.name = "sysinfo",
diff --git a/drivers/tpm/tpm2_tis_mmio.c b/drivers/tpm/tpm2_tis_mmio.c
index dee5503..fc62dcd 100644
--- a/drivers/tpm/tpm2_tis_mmio.c
+++ b/drivers/tpm/tpm2_tis_mmio.c
@@ -135,7 +135,7 @@
.cleanup = tpm_tis_cleanup,
};
-static const struct tpm_tis_chip_data tpm_tis_std_chip_data = {
+static struct tpm_tis_chip_data tpm_tis_std_chip_data = {
.pcr_count = 24,
.pcr_select_min = 3,
};
diff --git a/drivers/usb/dwc3/Kconfig b/drivers/usb/dwc3/Kconfig
index 0100723..682a691 100644
--- a/drivers/usb/dwc3/Kconfig
+++ b/drivers/usb/dwc3/Kconfig
@@ -87,6 +87,14 @@
Host and Peripheral operation modes are supported. OTG is not
supported.
+config USB_DWC3_STI
+ bool "STi USB wrapper"
+ depends on DM_USB && USB_DWC3_GENERIC && SYSCON
+ help
+ Enables support for the on-chip xHCI controller on STMicroelectronics
+ STiH407 family SoCs. This is a driver for the dwc3 to provide the
+ glue logic to configure the controller.
+
menu "PHY Subsystem"
config USB_DWC3_PHY_OMAP
diff --git a/drivers/usb/dwc3/Makefile b/drivers/usb/dwc3/Makefile
index a085c9d..985206e 100644
--- a/drivers/usb/dwc3/Makefile
+++ b/drivers/usb/dwc3/Makefile
@@ -15,3 +15,4 @@
obj-$(CONFIG_USB_DWC3_LAYERSCAPE) += dwc3-layerscape.o
obj-$(CONFIG_USB_DWC3_PHY_OMAP) += ti_usb_phy.o
obj-$(CONFIG_USB_DWC3_PHY_SAMSUNG) += samsung_usb_phy.o
+obj-$(CONFIG_USB_DWC3_STI) += dwc3-generic-sti.o
diff --git a/drivers/usb/dwc3/dwc3-generic-sti.c b/drivers/usb/dwc3/dwc3-generic-sti.c
new file mode 100644
index 0000000..b34f5ce
--- /dev/null
+++ b/drivers/usb/dwc3/dwc3-generic-sti.c
@@ -0,0 +1,134 @@
+// SPDX-License-Identifier: GPL-2.0-or-later OR BSD-3-Clause
+/*
+ * STi specific glue layer for DWC3
+ *
+ * Copyright (C) 2025, STMicroelectronics - All Rights Reserved
+ */
+
+#define LOG_CATEGORY UCLASS_NOP
+
+#include <reset.h>
+#include <regmap.h>
+#include <syscon.h>
+#include <asm/io.h>
+#include <dm/device.h>
+#include <dm/device_compat.h>
+#include <dm/read.h>
+#include <linux/usb/otg.h>
+#include "dwc3-generic.h"
+
+/* glue registers */
+#define CLKRST_CTRL 0x00
+#define AUX_CLK_EN BIT(0)
+#define SW_PIPEW_RESET_N BIT(4)
+#define EXT_CFG_RESET_N BIT(8)
+
+#define XHCI_REVISION BIT(12)
+
+#define USB2_VBUS_MNGMNT_SEL1 0x2C
+#define USB2_VBUS_UTMIOTG 0x1
+
+#define SEL_OVERRIDE_VBUSVALID(n) ((n) << 0)
+#define SEL_OVERRIDE_POWERPRESENT(n) ((n) << 4)
+#define SEL_OVERRIDE_BVALID(n) ((n) << 8)
+
+/* Static DRD configuration */
+#define USB3_CONTROL_MASK 0xf77
+
+#define USB3_DEVICE_NOT_HOST BIT(0)
+#define USB3_FORCE_VBUSVALID BIT(1)
+#define USB3_DELAY_VBUSVALID BIT(2)
+#define USB3_SEL_FORCE_OPMODE BIT(4)
+#define USB3_FORCE_OPMODE(n) ((n) << 5)
+#define USB3_SEL_FORCE_DPPULLDOWN2 BIT(8)
+#define USB3_FORCE_DPPULLDOWN2 BIT(9)
+#define USB3_SEL_FORCE_DMPULLDOWN2 BIT(10)
+#define USB3_FORCE_DMPULLDOWN2 BIT(11)
+
+static void dwc3_stih407_glue_configure(struct udevice *dev, int index,
+ enum usb_dr_mode mode)
+{
+ struct dwc3_glue_data *glue = dev_get_plat(dev);
+ struct regmap *regmap;
+ ulong syscfg_base;
+ ulong syscfg_offset;
+ ulong glue_base;
+ int ret;
+
+ /* deassert both powerdown and softreset */
+ ret = reset_deassert_bulk(&glue->resets);
+ if (ret) {
+ dev_err(dev, "reset_deassert_bulk error: %d\n", ret);
+ return;
+ }
+
+ regmap = syscon_regmap_lookup_by_phandle(dev, "st,syscfg");
+ if (IS_ERR(regmap)) {
+ dev_err(dev, "unable to get st,syscfg, dev %s\n", dev->name);
+ return;
+ }
+
+ syscfg_base = regmap->ranges[0].start;
+ glue_base = dev_read_addr_index(dev, 0);
+ syscfg_offset = dev_read_addr_index(dev, 1);
+
+ clrbits_le32(syscfg_base + syscfg_offset, USB3_CONTROL_MASK);
+
+ /* glue drd init */
+ switch (mode) {
+ case USB_DR_MODE_PERIPHERAL:
+ clrbits_le32(syscfg_base + syscfg_offset,
+ USB3_DELAY_VBUSVALID | USB3_SEL_FORCE_OPMODE |
+ USB3_FORCE_OPMODE(0x3) | USB3_SEL_FORCE_DPPULLDOWN2 |
+ USB3_FORCE_DPPULLDOWN2 | USB3_SEL_FORCE_DMPULLDOWN2 |
+ USB3_FORCE_DMPULLDOWN2);
+
+ setbits_le32(syscfg_base + syscfg_offset,
+ USB3_DEVICE_NOT_HOST | USB3_FORCE_VBUSVALID);
+ break;
+
+ case USB_DR_MODE_HOST:
+ clrbits_le32(syscfg_base + syscfg_offset,
+ USB3_DEVICE_NOT_HOST | USB3_FORCE_VBUSVALID |
+ USB3_SEL_FORCE_OPMODE | USB3_FORCE_OPMODE(0x3) |
+ USB3_SEL_FORCE_DPPULLDOWN2 | USB3_FORCE_DPPULLDOWN2 |
+ USB3_SEL_FORCE_DMPULLDOWN2 | USB3_FORCE_DMPULLDOWN2);
+
+ setbits_le32(syscfg_base + syscfg_offset, USB3_DELAY_VBUSVALID);
+ break;
+
+ default:
+ dev_err(dev, "Unsupported mode of operation %d\n", mode);
+ return;
+ }
+
+ /* glue init */
+ setbits_le32(glue_base + CLKRST_CTRL, AUX_CLK_EN | EXT_CFG_RESET_N | XHCI_REVISION);
+ clrbits_le32(glue_base + CLKRST_CTRL, SW_PIPEW_RESET_N);
+
+ /* configure mux for vbus, powerpresent and bvalid signals */
+ setbits_le32(glue_base + USB2_VBUS_MNGMNT_SEL1,
+ SEL_OVERRIDE_VBUSVALID(USB2_VBUS_UTMIOTG) |
+ SEL_OVERRIDE_POWERPRESENT(USB2_VBUS_UTMIOTG) |
+ SEL_OVERRIDE_BVALID(USB2_VBUS_UTMIOTG));
+ setbits_le32(glue_base + CLKRST_CTRL, SW_PIPEW_RESET_N);
+};
+
+struct dwc3_glue_ops stih407_ops = {
+ .glue_configure = dwc3_stih407_glue_configure,
+};
+
+static const struct udevice_id dwc3_sti_match[] = {
+ { .compatible = "st,stih407-dwc3", .data = (ulong)&stih407_ops},
+ { /* sentinel */ }
+};
+
+U_BOOT_DRIVER(dwc3_sti_wrapper) = {
+ .name = "dwc3-sti",
+ .id = UCLASS_NOP,
+ .of_match = dwc3_sti_match,
+ .bind = dwc3_glue_bind,
+ .probe = dwc3_glue_probe,
+ .remove = dwc3_glue_remove,
+ .plat_auto = sizeof(struct dwc3_glue_data),
+};
diff --git a/drivers/usb/dwc3/dwc3-generic.c b/drivers/usb/dwc3/dwc3-generic.c
index 55e62b3..21452ad 100644
--- a/drivers/usb/dwc3/dwc3-generic.c
+++ b/drivers/usb/dwc3/dwc3-generic.c
@@ -7,29 +7,17 @@
* Based on dwc3-omap.c.
*/
-#include <cpu_func.h>
-#include <log.h>
#include <dm.h>
-#include <dm/device-internal.h>
+#include <reset.h>
+#include <asm/gpio.h>
#include <dm/lists.h>
-#include <dwc3-uboot.h>
-#include <generic-phy.h>
-#include <linux/bitops.h>
#include <linux/delay.h>
-#include <linux/printk.h>
-#include <linux/usb/ch9.h>
#include <linux/usb/gadget.h>
-#include <malloc.h>
#include <power/regulator.h>
-#include <usb.h>
-#include "core.h"
-#include "gadget.h"
-#include <reset.h>
-#include <clk.h>
#include <usb/xhci.h>
-#include <asm/gpio.h>
-
+#include "core.h"
#include "dwc3-generic.h"
+#include "gadget.h"
struct dwc3_generic_plat {
fdt_addr_t base;
diff --git a/drivers/usb/gadget/f_mass_storage.c b/drivers/usb/gadget/f_mass_storage.c
index ffe1ae6..d3fc4ac 100644
--- a/drivers/usb/gadget/f_mass_storage.c
+++ b/drivers/usb/gadget/f_mass_storage.c
@@ -682,6 +682,7 @@
k = 0;
}
+ schedule();
dm_usb_gadget_handle_interrupts(udcdev);
}
common->thread_wakeup_needed = 0;
diff --git a/drivers/usb/gadget/g_dnl.c b/drivers/usb/gadget/g_dnl.c
index 631969b..f2540eb 100644
--- a/drivers/usb/gadget/g_dnl.c
+++ b/drivers/usb/gadget/g_dnl.c
@@ -207,7 +207,8 @@
static int on_serialno(const char *name, const char *value, enum env_op op,
int flags)
{
- g_dnl_set_serialnumber((char *)value);
+ if (value)
+ g_dnl_set_serialnumber((char *)value);
return 0;
}
U_BOOT_ENV_CALLBACK(serialno, on_serialno);
diff --git a/drivers/usb/host/Kconfig b/drivers/usb/host/Kconfig
index a656265..3dc7977 100644
--- a/drivers/usb/host/Kconfig
+++ b/drivers/usb/host/Kconfig
@@ -110,15 +110,6 @@
Choose this option to add support for USB 3.0 driver on Renesas
R-Car Gen3 SoCs.
-config USB_XHCI_STI
- bool "Support for STMicroelectronics STiH407 family on-chip xHCI USB controller"
- depends on ARCH_STI
- default y
- help
- Enables support for the on-chip xHCI controller on STMicroelectronics
- STiH407 family SoCs. This is a driver for the dwc3 to provide the glue logic
- to configure the controller.
-
config USB_XHCI_DRA7XX_INDEX
int "DRA7XX xHCI USB index"
range 0 1
diff --git a/drivers/usb/host/Makefile b/drivers/usb/host/Makefile
index 301bb9f..902d68d 100644
--- a/drivers/usb/host/Makefile
+++ b/drivers/usb/host/Makefile
@@ -54,7 +54,6 @@
obj-$(CONFIG_USB_XHCI_OMAP) += xhci-omap.o
obj-$(CONFIG_USB_XHCI_PCI) += xhci-pci.o
obj-$(CONFIG_USB_XHCI_RCAR) += xhci-rcar.o
-obj-$(CONFIG_USB_XHCI_STI) += dwc3-sti-glue.o
obj-$(CONFIG_USB_XHCI_OCTEON) += dwc3-octeon-glue.o
# designware
diff --git a/drivers/usb/host/dwc3-sti-glue.c b/drivers/usb/host/dwc3-sti-glue.c
deleted file mode 100644
index 3e6834e..0000000
--- a/drivers/usb/host/dwc3-sti-glue.c
+++ /dev/null
@@ -1,253 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * STiH407 family DWC3 specific Glue layer
- *
- * Copyright (C) 2017, STMicroelectronics - All Rights Reserved
- * Author(s): Patrice Chotard, <patrice.chotard@foss.st.com> for STMicroelectronics.
- */
-
-#include <log.h>
-#include <asm/global_data.h>
-#include <asm/io.h>
-#include <dm.h>
-#include <errno.h>
-#include <dm/lists.h>
-#include <regmap.h>
-#include <reset-uclass.h>
-#include <syscon.h>
-#include <usb.h>
-#include <linux/printk.h>
-
-#include <linux/usb/dwc3.h>
-#include <linux/usb/otg.h>
-#include <dwc3-sti-glue.h>
-
-DECLARE_GLOBAL_DATA_PTR;
-
-/*
- * struct sti_dwc3_glue_plat - dwc3 STi glue driver private structure
- * @syscfg_base: addr for the glue syscfg
- * @glue_base: addr for the glue registers
- * @syscfg_offset: usb syscfg control offset
- * @powerdown_ctl: rest controller for powerdown signal
- * @softreset_ctl: reset controller for softreset signal
- * @mode: drd static host/device config
- */
-struct sti_dwc3_glue_plat {
- phys_addr_t syscfg_base;
- phys_addr_t glue_base;
- phys_addr_t syscfg_offset;
- struct reset_ctl powerdown_ctl;
- struct reset_ctl softreset_ctl;
- enum usb_dr_mode mode;
-};
-
-static int sti_dwc3_glue_drd_init(struct sti_dwc3_glue_plat *plat)
-{
- unsigned long val;
-
- val = readl(plat->syscfg_base + plat->syscfg_offset);
-
- val &= USB3_CONTROL_MASK;
-
- switch (plat->mode) {
- case USB_DR_MODE_PERIPHERAL:
- val &= ~(USB3_DELAY_VBUSVALID
- | USB3_SEL_FORCE_OPMODE | USB3_FORCE_OPMODE(0x3)
- | USB3_SEL_FORCE_DPPULLDOWN2 | USB3_FORCE_DPPULLDOWN2
- | USB3_SEL_FORCE_DMPULLDOWN2 | USB3_FORCE_DMPULLDOWN2);
-
- val |= USB3_DEVICE_NOT_HOST | USB3_FORCE_VBUSVALID;
- break;
-
- case USB_DR_MODE_HOST:
- val &= ~(USB3_DEVICE_NOT_HOST | USB3_FORCE_VBUSVALID
- | USB3_SEL_FORCE_OPMODE | USB3_FORCE_OPMODE(0x3)
- | USB3_SEL_FORCE_DPPULLDOWN2 | USB3_FORCE_DPPULLDOWN2
- | USB3_SEL_FORCE_DMPULLDOWN2 | USB3_FORCE_DMPULLDOWN2);
-
- val |= USB3_DELAY_VBUSVALID;
- break;
-
- default:
- pr_err("Unsupported mode of operation %d\n", plat->mode);
- return -EINVAL;
- }
- writel(val, plat->syscfg_base + plat->syscfg_offset);
-
- return 0;
-}
-
-static void sti_dwc3_glue_init(struct sti_dwc3_glue_plat *plat)
-{
- unsigned long reg;
-
- reg = readl(plat->glue_base + CLKRST_CTRL);
-
- reg |= AUX_CLK_EN | EXT_CFG_RESET_N | XHCI_REVISION;
- reg &= ~SW_PIPEW_RESET_N;
-
- writel(reg, plat->glue_base + CLKRST_CTRL);
-
- /* configure mux for vbus, powerpresent and bvalid signals */
- reg = readl(plat->glue_base + USB2_VBUS_MNGMNT_SEL1);
-
- reg |= SEL_OVERRIDE_VBUSVALID(USB2_VBUS_UTMIOTG) |
- SEL_OVERRIDE_POWERPRESENT(USB2_VBUS_UTMIOTG) |
- SEL_OVERRIDE_BVALID(USB2_VBUS_UTMIOTG);
-
- writel(reg, plat->glue_base + USB2_VBUS_MNGMNT_SEL1);
-
- setbits_le32(plat->glue_base + CLKRST_CTRL, SW_PIPEW_RESET_N);
-}
-
-static int sti_dwc3_glue_of_to_plat(struct udevice *dev)
-{
- struct sti_dwc3_glue_plat *plat = dev_get_plat(dev);
- struct udevice *syscon;
- struct regmap *regmap;
- int ret;
- u32 reg[4];
-
- ret = ofnode_read_u32_array(dev_ofnode(dev), "reg", reg,
- ARRAY_SIZE(reg));
- if (ret) {
- pr_err("unable to find st,stih407-dwc3 reg property(%d)\n", ret);
- return ret;
- }
-
- plat->glue_base = reg[0];
- plat->syscfg_offset = reg[2];
-
- /* get corresponding syscon phandle */
- ret = uclass_get_device_by_phandle(UCLASS_SYSCON, dev, "st,syscfg",
- &syscon);
- if (ret) {
- pr_err("unable to find syscon device (%d)\n", ret);
- return ret;
- }
-
- /* get syscfg-reg base address */
- regmap = syscon_get_regmap(syscon);
- if (!regmap) {
- pr_err("unable to find regmap\n");
- return -ENODEV;
- }
- plat->syscfg_base = regmap->ranges[0].start;
-
- /* get powerdown reset */
- ret = reset_get_by_name(dev, "powerdown", &plat->powerdown_ctl);
- if (ret) {
- pr_err("can't get powerdown reset for %s (%d)", dev->name, ret);
- return ret;
- }
-
- /* get softreset reset */
- ret = reset_get_by_name(dev, "softreset", &plat->softreset_ctl);
- if (ret)
- pr_err("can't get soft reset for %s (%d)", dev->name, ret);
-
- return ret;
-};
-
-static int sti_dwc3_glue_bind(struct udevice *dev)
-{
- struct sti_dwc3_glue_plat *plat = dev_get_plat(dev);
- ofnode node, dwc3_node;
-
- /* Find snps,dwc3 node from subnode */
- ofnode_for_each_subnode(node, dev_ofnode(dev)) {
- if (ofnode_device_is_compatible(node, "snps,dwc3"))
- dwc3_node = node;
- }
-
- if (!ofnode_valid(dwc3_node)) {
- pr_err("Can't find dwc3 subnode for %s\n", dev->name);
- return -ENODEV;
- }
-
- /* retrieve the DWC3 dual role mode */
- plat->mode = usb_get_dr_mode(dwc3_node);
- if (plat->mode == USB_DR_MODE_UNKNOWN)
- /* by default set dual role mode to HOST */
- plat->mode = USB_DR_MODE_HOST;
-
- return dm_scan_fdt_dev(dev);
-}
-
-static int sti_dwc3_glue_probe(struct udevice *dev)
-{
- struct sti_dwc3_glue_plat *plat = dev_get_plat(dev);
- int ret;
-
- /* deassert both powerdown and softreset */
- ret = reset_deassert(&plat->powerdown_ctl);
- if (ret < 0) {
- pr_err("DWC3 powerdown reset deassert failed: %d", ret);
- return ret;
- }
-
- ret = reset_deassert(&plat->softreset_ctl);
- if (ret < 0) {
- pr_err("DWC3 soft reset deassert failed: %d", ret);
- goto softreset_err;
- }
-
- ret = sti_dwc3_glue_drd_init(plat);
- if (ret)
- goto init_err;
-
- sti_dwc3_glue_init(plat);
-
- return 0;
-
-init_err:
- ret = reset_assert(&plat->softreset_ctl);
- if (ret < 0) {
- pr_err("DWC3 soft reset deassert failed: %d", ret);
- return ret;
- }
-
-softreset_err:
- ret = reset_assert(&plat->powerdown_ctl);
- if (ret < 0)
- pr_err("DWC3 powerdown reset deassert failed: %d", ret);
-
- return ret;
-}
-
-static int sti_dwc3_glue_remove(struct udevice *dev)
-{
- struct sti_dwc3_glue_plat *plat = dev_get_plat(dev);
- int ret;
-
- /* assert both powerdown and softreset */
- ret = reset_assert(&plat->powerdown_ctl);
- if (ret < 0) {
- pr_err("DWC3 powerdown reset deassert failed: %d", ret);
- return ret;
- }
-
- ret = reset_assert(&plat->softreset_ctl);
- if (ret < 0)
- pr_err("DWC3 soft reset deassert failed: %d", ret);
-
- return ret;
-}
-
-static const struct udevice_id sti_dwc3_glue_ids[] = {
- { .compatible = "st,stih407-dwc3" },
- { }
-};
-
-U_BOOT_DRIVER(dwc3_sti_glue) = {
- .name = "dwc3_sti_glue",
- .id = UCLASS_NOP,
- .of_match = sti_dwc3_glue_ids,
- .of_to_plat = sti_dwc3_glue_of_to_plat,
- .probe = sti_dwc3_glue_probe,
- .remove = sti_dwc3_glue_remove,
- .bind = sti_dwc3_glue_bind,
- .plat_auto = sizeof(struct sti_dwc3_glue_plat),
- .flags = DM_FLAG_ALLOC_PRIV_DMA,
-};
diff --git a/dts/upstream/src/arm64/rockchip/rk3308-rock-s0.dts b/dts/upstream/src/arm64/rockchip/rk3308-rock-s0.dts
index bd6419a..8311af4 100644
--- a/dts/upstream/src/arm64/rockchip/rk3308-rock-s0.dts
+++ b/dts/upstream/src/arm64/rockchip/rk3308-rock-s0.dts
@@ -74,6 +74,23 @@
vin-supply = <&vcc5v0_sys>;
};
+ /*
+ * HW revision prior to v1.2 must pull GPIO4_D6 low to access sdmmc.
+ * This is modeled as an always-on active low fixed regulator.
+ */
+ vcc_sd: regulator-3v3-vcc-sd {
+ compatible = "regulator-fixed";
+ gpios = <&gpio4 RK_PD6 GPIO_ACTIVE_LOW>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&sdmmc_2030>;
+ regulator-name = "vcc_sd";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ vin-supply = <&vcc_io>;
+ };
+
vcc5v0_sys: regulator-5v0-vcc-sys {
compatible = "regulator-fixed";
regulator-name = "vcc5v0_sys";
@@ -181,6 +198,12 @@
};
};
+ sdmmc {
+ sdmmc_2030: sdmmc-2030 {
+ rockchip,pins = <4 RK_PD6 RK_FUNC_GPIO &pcfg_pull_none>;
+ };
+ };
+
wifi {
wifi_reg_on: wifi-reg-on {
rockchip,pins = <0 RK_PA2 RK_FUNC_GPIO &pcfg_pull_none>;
@@ -233,7 +256,7 @@
cap-mmc-highspeed;
cap-sd-highspeed;
disable-wp;
- vmmc-supply = <&vcc_io>;
+ vmmc-supply = <&vcc_sd>;
status = "okay";
};
diff --git a/env/mmc.c b/env/mmc.c
index 379f5ec..2ef15fb 100644
--- a/env/mmc.c
+++ b/env/mmc.c
@@ -40,18 +40,6 @@
DECLARE_GLOBAL_DATA_PTR;
-/*
- * In case the environment is redundant, stored in eMMC hardware boot
- * partition and the environment and redundant environment offsets are
- * identical, store the environment and redundant environment in both
- * eMMC boot partitions, one copy in each.
- * */
-#if (defined(CONFIG_SYS_REDUNDAND_ENVIRONMENT) && \
- (CONFIG_SYS_MMC_ENV_PART == 1) && \
- (CONFIG_ENV_OFFSET == CONFIG_ENV_OFFSET_REDUND))
-#define ENV_MMC_HWPART_REDUND 1
-#endif
-
#if CONFIG_IS_ENABLED(OF_CONTROL)
static int mmc_env_partition_by_name(struct blk_desc *desc, const char *str,
@@ -217,6 +205,23 @@
}
#endif
+static bool mmc_env_is_redundant_in_both_boot_hwparts(struct mmc *mmc)
+{
+ /*
+ * In case the environment is redundant, stored in eMMC hardware boot
+ * partition and the environment and redundant environment offsets are
+ * identical, store the environment and redundant environment in both
+ * eMMC boot partitions, one copy in each.
+ */
+ if (!IS_ENABLED(CONFIG_SYS_REDUNDAND_ENVIRONMENT))
+ return false;
+
+ if (CONFIG_SYS_MMC_ENV_PART != 1)
+ return false;
+
+ return mmc_offset(mmc, 0) == mmc_offset(mmc, 1);
+}
+
__weak int mmc_get_env_addr(struct mmc *mmc, int copy, u32 *env_addr)
{
s64 offset = mmc_offset(mmc, copy);
@@ -336,7 +341,7 @@
if (gd->env_valid == ENV_VALID)
copy = 1;
- if (IS_ENABLED(ENV_MMC_HWPART_REDUND)) {
+ if (mmc_env_is_redundant_in_both_boot_hwparts(mmc)) {
ret = mmc_set_env_part(mmc, copy + 1);
if (ret)
goto fini;
@@ -409,7 +414,7 @@
if (IS_ENABLED(CONFIG_SYS_REDUNDAND_ENVIRONMENT)) {
copy = 1;
- if (IS_ENABLED(ENV_MMC_HWPART_REDUND)) {
+ if (mmc_env_is_redundant_in_both_boot_hwparts(mmc)) {
ret = mmc_set_env_part(mmc, copy + 1);
if (ret)
goto fini;
@@ -443,13 +448,7 @@
return (n == blk_cnt) ? 0 : -1;
}
-#if defined(ENV_IS_EMBEDDED)
-static int env_mmc_load(void)
-{
- return 0;
-}
-#elif defined(CONFIG_SYS_REDUNDAND_ENVIRONMENT)
-static int env_mmc_load(void)
+static int env_mmc_load_redundant(void)
{
struct mmc *mmc;
u32 offset1, offset2;
@@ -477,7 +476,7 @@
goto fini;
}
- if (IS_ENABLED(ENV_MMC_HWPART_REDUND)) {
+ if (mmc_env_is_redundant_in_both_boot_hwparts(mmc)) {
ret = mmc_set_env_part(mmc, 1);
if (ret)
goto fini;
@@ -485,7 +484,7 @@
read1_fail = read_env(mmc, CONFIG_ENV_SIZE, offset1, tmp_env1);
- if (IS_ENABLED(ENV_MMC_HWPART_REDUND)) {
+ if (mmc_env_is_redundant_in_both_boot_hwparts(mmc)) {
ret = mmc_set_env_part(mmc, 2);
if (ret)
goto fini;
@@ -505,8 +504,8 @@
return ret;
}
-#else /* ! CONFIG_SYS_REDUNDAND_ENVIRONMENT */
-static int env_mmc_load(void)
+
+static int env_mmc_load_singular(void)
{
ALLOC_CACHE_ALIGN_BUFFER(char, buf, CONFIG_ENV_SIZE);
struct mmc *mmc;
@@ -551,7 +550,16 @@
return ret;
}
+
+static int env_mmc_load(void)
+{
+ if (IS_ENABLED(CONFIG_ENV_IS_EMBEDDED))
+ return 0;
+ else if (IS_ENABLED(CONFIG_SYS_REDUNDAND_ENVIRONMENT))
+ return env_mmc_load_redundant();
+ else
+ return env_mmc_load_singular();
+}
-#endif /* CONFIG_SYS_REDUNDAND_ENVIRONMENT */
U_BOOT_ENV_LOCATION(mmc) = {
.location = ENVL_MMC,
diff --git a/fs/erofs/fs.c b/fs/erofs/fs.c
index 7bd2e8f..dcdc883 100644
--- a/fs/erofs/fs.c
+++ b/fs/erofs/fs.c
@@ -59,16 +59,19 @@
static int erofs_readlink(struct erofs_inode *vi)
{
- size_t len = vi->i_size;
+ size_t alloc_size;
char *target;
int err;
- target = malloc(len + 1);
+ if (__builtin_add_overflow(vi->i_size, 1, &alloc_size))
+ return -EFSCORRUPTED;
+
+ target = malloc(alloc_size);
if (!target)
return -ENOMEM;
- target[len] = '\0';
+ target[vi->i_size] = '\0';
- err = erofs_pread(vi, target, len, 0);
+ err = erofs_pread(vi, target, vi->i_size, 0);
if (err)
goto err_out;
diff --git a/fs/squashfs/sqfs.c b/fs/squashfs/sqfs.c
index b931401..8fac6c6 100644
--- a/fs/squashfs/sqfs.c
+++ b/fs/squashfs/sqfs.c
@@ -719,6 +719,7 @@
u32 src_len, dest_offset = 0;
unsigned long dest_len = 0;
bool compressed;
+ size_t buf_size;
table_size = get_unaligned_le64(&sblk->directory_table_start) -
get_unaligned_le64(&sblk->inode_table_start);
@@ -728,7 +729,10 @@
sblk->directory_table_start, &table_offset);
/* Allocate a proper sized buffer (itb) to store the inode table */
- itb = malloc_cache_aligned(n_blks * ctxt.cur_dev->blksz);
+ if (__builtin_mul_overflow(n_blks, ctxt.cur_dev->blksz, &buf_size))
+ return -EINVAL;
+
+ itb = malloc_cache_aligned(buf_size);
if (!itb)
return -ENOMEM;
@@ -806,6 +810,7 @@
u32 src_len, dest_offset = 0;
unsigned long dest_len = 0;
bool compressed;
+ size_t buf_size;
*dir_table = NULL;
*pos_list = NULL;
@@ -818,7 +823,10 @@
sblk->fragment_table_start, &table_offset);
/* Allocate a proper sized buffer (dtb) to store the directory table */
- dtb = malloc_cache_aligned(n_blks * ctxt.cur_dev->blksz);
+ if (__builtin_mul_overflow(n_blks, ctxt.cur_dev->blksz, &buf_size))
+ return -EINVAL;
+
+ dtb = malloc_cache_aligned(buf_size);
if (!dtb)
return -ENOMEM;
@@ -1369,6 +1377,7 @@
unsigned long dest_len;
struct fs_dirent *dent;
unsigned char *ipos;
+ size_t buf_size;
*actread = 0;
@@ -1573,7 +1582,10 @@
table_offset = frag_entry.start - (start * ctxt.cur_dev->blksz);
n_blks = DIV_ROUND_UP(table_size + table_offset, ctxt.cur_dev->blksz);
+ if (__builtin_mul_overflow(n_blks, ctxt.cur_dev->blksz, &buf_size))
+ return -EINVAL;
+
- fragment = malloc_cache_aligned(n_blks * ctxt.cur_dev->blksz);
+ fragment = malloc_cache_aligned(buf_size);
if (!fragment) {
ret = -ENOMEM;
diff --git a/include/bloblist.h b/include/bloblist.h
index 98aacf5..f32faf7 100644
--- a/include/bloblist.h
+++ b/include/bloblist.h
@@ -467,9 +467,8 @@
* If CONFIG_BLOBLIST_ALLOC is selected, it allocates memory for a bloblist of
* size CONFIG_BLOBLIST_SIZE.
*
- * If CONFIG_BLOBLIST_PASSAGE is selected, it uses the bloblist in the incoming
- * standard passage. The size is detected automatically so CONFIG_BLOBLIST_SIZE
- * can be 0.
+ * If CONFIG_BLOBLIST_PASSAGE_MANDATORY is selected, bloblist in the incoming
+ * standard passage is mandatorily required.
*
* Sets GD_FLG_BLOBLIST_READY in global_data flags on success
*
@@ -501,19 +500,18 @@
* @rfdt: Register that holds the FDT base address.
* @rzero: Register that must be zero.
* @rsig: Register that holds signature and register conventions version.
+ * @xlist: Register that holds the transfer list.
* Return: 0 if OK, -EIO if the bloblist is not compliant to the register
* conventions.
*/
-int bloblist_check_reg_conv(ulong rfdt, ulong rzero, ulong rsig);
+int bloblist_check_reg_conv(ulong rfdt, ulong rzero, ulong rsig, ulong xlist);
/**
- * xferlist_from_boot_arg() - Get bloblist from the boot args and relocate it
- * to the specified address.
+ * xferlist_from_boot_arg() - Get bloblist from the boot args.
*
- * @addr: Address for the bloblist
- * @size: Size of space reserved for the bloblist
+ * @addr: Address of the bloblist
* Return: 0 if OK, else on error
*/
-int xferlist_from_boot_arg(ulong addr, ulong size);
+int xferlist_from_boot_arg(ulong *addr);
#endif /* __BLOBLIST_H */
diff --git a/include/configs/microchip_mpfs_icicle.h b/include/configs/microchip_mpfs_icicle.h
index 5ced45b..0077f6a 100644
--- a/include/configs/microchip_mpfs_icicle.h
+++ b/include/configs/microchip_mpfs_icicle.h
@@ -26,6 +26,7 @@
"scriptaddr=0x88100000\0" \
"pxefile_addr_r=0x88200000\0" \
"ramdisk_addr_r=0x88300000\0" \
+ "fdtfile=" CONFIG_DEFAULT_FDT_FILE "\0" \
BOOTENV
#endif /* __CONFIG_H */
diff --git a/include/configs/picasso.h b/include/configs/picasso.h
new file mode 100644
index 0000000..a58c7e5
--- /dev/null
+++ b/include/configs/picasso.h
@@ -0,0 +1,23 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * (C) Copyright 2010,2011
+ * NVIDIA Corporation <www.nvidia.com>
+ *
+ * (C) Copyright 2024
+ * Svyatoslav Ryhel <clamor95@gmail.com>
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+#include "tegra20-common.h"
+
+/* High-level configuration options */
+#define CFG_TEGRA_BOARD_STRING "Acer Iconia Tab A500"
+
+/* Board-specific serial config */
+#define CFG_SYS_NS16550_COM1 NV_PA_APB_UARTD_BASE
+
+#include "tegra-common-post.h"
+
+#endif /* __CONFIG_H */
diff --git a/include/configs/socfpga_soc64_common.h b/include/configs/socfpga_soc64_common.h
index b7ee1db..5ed1767 100644
--- a/include/configs/socfpga_soc64_common.h
+++ b/include/configs/socfpga_soc64_common.h
@@ -1,6 +1,7 @@
/* SPDX-License-Identifier: GPL-2.0
*
* Copyright (C) 2017-2024 Intel Corporation <www.intel.com>
+ * Copyright (C) 2025 Altera Corporation <www.altera.com>
*
*/
@@ -56,6 +57,11 @@
#define BOOTENV_DEV_QSPI(devtypeu, devtypel, instance) \
"bootcmd_qspi=ubi detach; sf probe && " \
+ "setenv mtdids 'nor0=nor0,nand0=nand.0' && " \
+ "setenv mtdparts 'mtdparts=nor0:66m(u-boot),190m(root); " \
+ "nand.0:2m(nand_uboot),500m(nand_root)' && " \
+ "env select UBI; saveenv && " \
+ "ubi part root && " \
"if ubi part root && ubi readvol ${scriptaddr} script; " \
"then echo QSPI: Running script from UBIFS; " \
"elif sf read ${scriptaddr} ${qspiscriptaddr} ${scriptsize}; " \
diff --git a/include/configs/ti_omap5_common.h b/include/configs/ti_omap5_common.h
index 26b6c1c..39102f1 100644
--- a/include/configs/ti_omap5_common.h
+++ b/include/configs/ti_omap5_common.h
@@ -239,20 +239,47 @@
"if test $fdtfile = undefined; then " \
"echo WARNING: Could not determine device tree to use; fi; \0"
+#define GET_OVERLAY_MMC_TI_ARGS \
+ "get_overlay_mmc=" \
+ "fdt address ${fdtaddr};" \
+ "fdt resize 0x100000;" \
+ "for overlay in $name_overlays;" \
+ "do;" \
+ "load mmc ${bootpart} ${dtboaddr} ${bootdir}/dtb/${overlay} &&" \
+ "fdt apply ${dtboaddr};" \
+ "done;\0" \
+
#define BOOT_TARGET_DEVICES(func) \
+ func(TI_MMC, ti_mmc, na) \
func(MMC, mmc, 0) \
func(MMC, mmc, 1) \
func(PXE, pxe, na) \
func(DHCP, dhcp, na)
+#define BOOTENV_DEV_TI_MMC(devtypeu, devtypel, instance) \
+ "bootcmd_ti_mmc= run get_name_kern; run mmcboot\0"
+
+#define BOOTENV_DEV_NAME_TI_MMC(devtyeu, devtypel, instance) \
+ "ti_mmc "
+
#include <config_distro_bootcmd.h>
#define CFG_EXTRA_ENV_SETTINGS \
DEFAULT_LINUX_BOOT_ENV \
DEFAULT_MMC_TI_ARGS \
+ "bootpart=0:2\0" \
+ "bootdir=/boot\0" \
+ "get_name_kern=" \
+ "if test $boot_fit -eq 1; then " \
+ "setenv bootfile fitImage; " \
+ "else " \
+ "setenv bootfile zImage; " \
+ "fi\0" \
DEFAULT_FIT_TI_ARGS \
+ "get_fit_config=setenv name_fit_config ${fdtfile}\0" \
DEFAULT_COMMON_BOOT_TI_ARGS \
DEFAULT_FDT_TI_ARGS \
+ GET_OVERLAY_MMC_TI_ARGS \
DFUARGS \
NETARGS \
NANDARGS \
diff --git a/include/dt-bindings/clock/rk3036-cru.h b/include/dt-bindings/clock/rk3036-cru.h
deleted file mode 100644
index 2c0552d..0000000
--- a/include/dt-bindings/clock/rk3036-cru.h
+++ /dev/null
@@ -1,185 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0+ */
-/*
- * Copyright (c) 2014 MundoReader S.L.
- * Author: Heiko Stuebner <heiko@sntech.de>
- */
-
-#ifndef _DT_BINDINGS_CLK_ROCKCHIP_RK3036_H
-#define _DT_BINDINGS_CLK_ROCKCHIP_RK3036_H
-
-/* core clocks */
-#define PLL_APLL 1
-#define PLL_DPLL 2
-#define PLL_GPLL 3
-#define ARMCLK 4
-
-/* sclk gates (special clocks) */
-#define SCLK_GPU 64
-#define SCLK_SPI 65
-#define SCLK_SDMMC 68
-#define SCLK_SDIO 69
-#define SCLK_EMMC 71
-#define SCLK_NANDC 76
-#define SCLK_UART0 77
-#define SCLK_UART1 78
-#define SCLK_UART2 79
-#define SCLK_I2S 82
-#define SCLK_SPDIF 83
-#define SCLK_TIMER0 85
-#define SCLK_TIMER1 86
-#define SCLK_TIMER2 87
-#define SCLK_TIMER3 88
-#define SCLK_OTGPHY0 93
-#define SCLK_LCDC 100
-#define SCLK_HDMI 109
-#define SCLK_HEVC 111
-#define SCLK_I2S_OUT 113
-#define SCLK_SDMMC_DRV 114
-#define SCLK_SDIO_DRV 115
-#define SCLK_EMMC_DRV 117
-#define SCLK_SDMMC_SAMPLE 118
-#define SCLK_SDIO_SAMPLE 119
-#define SCLK_EMMC_SAMPLE 121
-#define SCLK_PVTM_CORE 123
-#define SCLK_PVTM_GPU 124
-#define SCLK_PVTM_VIDEO 125
-#define SCLK_MAC 151
-#define SCLK_MACREF 152
-#define SCLK_SFC 160
-
-#define DCLK_LCDC 190
-
-/* aclk gates */
-#define ACLK_DMAC2 194
-#define ACLK_LCDC 197
-#define ACLK_VIO 203
-#define ACLK_VCODEC 208
-#define ACLK_CPU 209
-#define ACLK_PERI 210
-
-/* pclk gates */
-#define PCLK_GPIO0 320
-#define PCLK_GPIO1 321
-#define PCLK_GPIO2 322
-#define PCLK_GRF 329
-#define PCLK_I2C0 332
-#define PCLK_I2C1 333
-#define PCLK_I2C2 334
-#define PCLK_SPI 338
-#define PCLK_UART0 341
-#define PCLK_UART1 342
-#define PCLK_UART2 343
-#define PCLK_PWM 350
-#define PCLK_TIMER 353
-#define PCLK_HDMI 360
-#define PCLK_CPU 362
-#define PCLK_PERI 363
-#define PCLK_DDRUPCTL 364
-#define PCLK_WDT 368
-
-/* hclk gates */
-#define HCLK_OTG0 449
-#define HCLK_OTG1 450
-#define HCLK_NANDC 453
-#define HCLK_SDMMC 456
-#define HCLK_SDIO 457
-#define HCLK_EMMC 459
-#define HCLK_I2S 462
-#define HCLK_LCDC 465
-#define HCLK_ROM 467
-#define HCLK_VIO_BUS 472
-#define HCLK_VCODEC 476
-#define HCLK_CPU 477
-#define HCLK_PERI 478
-
-#define CLK_NR_CLKS (HCLK_PERI + 1)
-
-/* soft-reset indices */
-#define SRST_CORE0 0
-#define SRST_CORE1 1
-#define SRST_CORE0_DBG 4
-#define SRST_CORE1_DBG 5
-#define SRST_CORE0_POR 8
-#define SRST_CORE1_POR 9
-#define SRST_L2C 12
-#define SRST_TOPDBG 13
-#define SRST_STRC_SYS_A 14
-#define SRST_PD_CORE_NIU 15
-
-#define SRST_TIMER2 16
-#define SRST_CPUSYS_H 17
-#define SRST_AHB2APB_H 19
-#define SRST_TIMER3 20
-#define SRST_INTMEM 21
-#define SRST_ROM 22
-#define SRST_PERI_NIU 23
-#define SRST_I2S 24
-#define SRST_DDR_PLL 25
-#define SRST_GPU_DLL 26
-#define SRST_TIMER0 27
-#define SRST_TIMER1 28
-#define SRST_CORE_DLL 29
-#define SRST_EFUSE_P 30
-#define SRST_ACODEC_P 31
-
-#define SRST_GPIO0 32
-#define SRST_GPIO1 33
-#define SRST_GPIO2 34
-#define SRST_UART0 39
-#define SRST_UART1 40
-#define SRST_UART2 41
-#define SRST_I2C0 43
-#define SRST_I2C1 44
-#define SRST_I2C2 45
-#define SRST_SFC 47
-
-#define SRST_PWM0 48
-#define SRST_DAP 51
-#define SRST_DAP_SYS 52
-#define SRST_GRF 55
-#define SRST_PERIPHSYS_A 57
-#define SRST_PERIPHSYS_H 58
-#define SRST_PERIPHSYS_P 59
-#define SRST_CPU_PERI 61
-#define SRST_EMEM_PERI 62
-#define SRST_USB_PERI 63
-
-#define SRST_DMA2 64
-#define SRST_MAC 66
-#define SRST_NANDC 68
-#define SRST_USBOTG0 69
-#define SRST_OTGC0 71
-#define SRST_USBOTG1 72
-#define SRST_OTGC1 74
-#define SRST_DDRMSCH 79
-
-#define SRST_MMC0 81
-#define SRST_SDIO 82
-#define SRST_EMMC 83
-#define SRST_SPI0 84
-#define SRST_WDT 86
-#define SRST_DDRPHY 88
-#define SRST_DDRPHY_P 89
-#define SRST_DDRCTRL 90
-#define SRST_DDRCTRL_P 91
-
-#define SRST_HDMI_P 96
-#define SRST_VIO_BUS_H 99
-#define SRST_UTMI0 103
-#define SRST_UTMI1 104
-#define SRST_USBPOR 105
-
-#define SRST_VCODEC_A 112
-#define SRST_VCODEC_H 113
-#define SRST_VIO1_A 114
-#define SRST_HEVC 115
-#define SRST_VCODEC_NIU_A 116
-#define SRST_LCDC1_A 117
-#define SRST_LCDC1_H 118
-#define SRST_LCDC1_D 119
-#define SRST_GPU 120
-#define SRST_GPU_NIU_A 122
-
-#define SRST_DBG_P 131
-
-#endif
diff --git a/include/dt-bindings/clock/rk3288-cru.h b/include/dt-bindings/clock/rk3288-cru.h
deleted file mode 100644
index 453f667..0000000
--- a/include/dt-bindings/clock/rk3288-cru.h
+++ /dev/null
@@ -1,381 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0-or-later */
-/*
- * Copyright (c) 2014 MundoReader S.L.
- * Author: Heiko Stuebner <heiko@sntech.de>
- */
-
-#ifndef _DT_BINDINGS_CLK_ROCKCHIP_RK3288_H
-#define _DT_BINDINGS_CLK_ROCKCHIP_RK3288_H
-
-/* core clocks */
-#define PLL_APLL 1
-#define PLL_DPLL 2
-#define PLL_CPLL 3
-#define PLL_GPLL 4
-#define PLL_NPLL 5
-#define ARMCLK 6
-
-/* sclk gates (special clocks) */
-#define SCLK_GPU 64
-#define SCLK_SPI0 65
-#define SCLK_SPI1 66
-#define SCLK_SPI2 67
-#define SCLK_SDMMC 68
-#define SCLK_SDIO0 69
-#define SCLK_SDIO1 70
-#define SCLK_EMMC 71
-#define SCLK_TSADC 72
-#define SCLK_SARADC 73
-#define SCLK_PS2C 74
-#define SCLK_NANDC0 75
-#define SCLK_NANDC1 76
-#define SCLK_UART0 77
-#define SCLK_UART1 78
-#define SCLK_UART2 79
-#define SCLK_UART3 80
-#define SCLK_UART4 81
-#define SCLK_I2S0 82
-#define SCLK_SPDIF 83
-#define SCLK_SPDIF8CH 84
-#define SCLK_TIMER0 85
-#define SCLK_TIMER1 86
-#define SCLK_TIMER2 87
-#define SCLK_TIMER3 88
-#define SCLK_TIMER4 89
-#define SCLK_TIMER5 90
-#define SCLK_TIMER6 91
-#define SCLK_HSADC 92
-#define SCLK_OTGPHY0 93
-#define SCLK_OTGPHY1 94
-#define SCLK_OTGPHY2 95
-#define SCLK_OTG_ADP 96
-#define SCLK_HSICPHY480M 97
-#define SCLK_HSICPHY12M 98
-#define SCLK_MACREF 99
-#define SCLK_LCDC_PWM0 100
-#define SCLK_LCDC_PWM1 101
-#define SCLK_MAC_RX 102
-#define SCLK_MAC_TX 103
-#define SCLK_EDP_24M 104
-#define SCLK_EDP 105
-#define SCLK_RGA 106
-#define SCLK_ISP 107
-#define SCLK_ISP_JPE 108
-#define SCLK_HDMI_HDCP 109
-#define SCLK_HDMI_CEC 110
-#define SCLK_HEVC_CABAC 111
-#define SCLK_HEVC_CORE 112
-#define SCLK_I2S0_OUT 113
-#define SCLK_SDMMC_DRV 114
-#define SCLK_SDIO0_DRV 115
-#define SCLK_SDIO1_DRV 116
-#define SCLK_EMMC_DRV 117
-#define SCLK_SDMMC_SAMPLE 118
-#define SCLK_SDIO0_SAMPLE 119
-#define SCLK_SDIO1_SAMPLE 120
-#define SCLK_EMMC_SAMPLE 121
-#define SCLK_USBPHY480M_SRC 122
-#define SCLK_PVTM_CORE 123
-#define SCLK_PVTM_GPU 124
-#define SCLK_CRYPTO 125
-#define SCLK_MIPIDSI_24M 126
-#define SCLK_VIP_OUT 127
-
-#define SCLK_MAC_PLL 150
-#define SCLK_MAC 151
-#define SCLK_MACREF_OUT 152
-
-#define DCLK_VOP0 190
-#define DCLK_VOP1 191
-
-/* aclk gates */
-#define ACLK_GPU 192
-#define ACLK_DMAC1 193
-#define ACLK_DMAC2 194
-#define ACLK_MMU 195
-#define ACLK_GMAC 196
-#define ACLK_VOP0 197
-#define ACLK_VOP1 198
-#define ACLK_CRYPTO 199
-#define ACLK_RGA 200
-#define ACLK_RGA_NIU 201
-#define ACLK_IEP 202
-#define ACLK_VIO0_NIU 203
-#define ACLK_VIP 204
-#define ACLK_ISP 205
-#define ACLK_VIO1_NIU 206
-#define ACLK_HEVC 207
-#define ACLK_VCODEC 208
-#define ACLK_CPU 209
-#define ACLK_PERI 210
-
-/* pclk gates */
-#define PCLK_GPIO0 320
-#define PCLK_GPIO1 321
-#define PCLK_GPIO2 322
-#define PCLK_GPIO3 323
-#define PCLK_GPIO4 324
-#define PCLK_GPIO5 325
-#define PCLK_GPIO6 326
-#define PCLK_GPIO7 327
-#define PCLK_GPIO8 328
-#define PCLK_GRF 329
-#define PCLK_SGRF 330
-#define PCLK_PMU 331
-#define PCLK_I2C0 332
-#define PCLK_I2C1 333
-#define PCLK_I2C2 334
-#define PCLK_I2C3 335
-#define PCLK_I2C4 336
-#define PCLK_I2C5 337
-#define PCLK_SPI0 338
-#define PCLK_SPI1 339
-#define PCLK_SPI2 340
-#define PCLK_UART0 341
-#define PCLK_UART1 342
-#define PCLK_UART2 343
-#define PCLK_UART3 344
-#define PCLK_UART4 345
-#define PCLK_TSADC 346
-#define PCLK_SARADC 347
-#define PCLK_SIM 348
-#define PCLK_GMAC 349
-#define PCLK_PWM 350
-#define PCLK_RKPWM 351
-#define PCLK_PS2C 352
-#define PCLK_TIMER 353
-#define PCLK_TZPC 354
-#define PCLK_EDP_CTRL 355
-#define PCLK_MIPI_DSI0 356
-#define PCLK_MIPI_DSI1 357
-#define PCLK_MIPI_CSI 358
-#define PCLK_LVDS_PHY 359
-#define PCLK_HDMI_CTRL 360
-#define PCLK_VIO2_H2P 361
-#define PCLK_CPU 362
-#define PCLK_PERI 363
-#define PCLK_DDRUPCTL0 364
-#define PCLK_PUBL0 365
-#define PCLK_DDRUPCTL1 366
-#define PCLK_PUBL1 367
-#define PCLK_WDT 368
-#define PCLK_EFUSE256 369
-#define PCLK_EFUSE1024 370
-#define PCLK_ISP_IN 371
-
-/* hclk gates */
-#define HCLK_GPS 448
-#define HCLK_OTG0 449
-#define HCLK_USBHOST0 450
-#define HCLK_USBHOST1 451
-#define HCLK_HSIC 452
-#define HCLK_NANDC0 453
-#define HCLK_NANDC1 454
-#define HCLK_TSP 455
-#define HCLK_SDMMC 456
-#define HCLK_SDIO0 457
-#define HCLK_SDIO1 458
-#define HCLK_EMMC 459
-#define HCLK_HSADC 460
-#define HCLK_CRYPTO 461
-#define HCLK_I2S0 462
-#define HCLK_SPDIF 463
-#define HCLK_SPDIF8CH 464
-#define HCLK_VOP0 465
-#define HCLK_VOP1 466
-#define HCLK_ROM 467
-#define HCLK_IEP 468
-#define HCLK_ISP 469
-#define HCLK_RGA 470
-#define HCLK_VIO_AHB_ARBI 471
-#define HCLK_VIO_NIU 472
-#define HCLK_VIP 473
-#define HCLK_VIO2_H2P 474
-#define HCLK_HEVC 475
-#define HCLK_VCODEC 476
-#define HCLK_CPU 477
-#define HCLK_PERI 478
-
-#define CLK_NR_CLKS (HCLK_PERI + 1)
-
-/* soft-reset indices */
-#define SRST_CORE0 0
-#define SRST_CORE1 1
-#define SRST_CORE2 2
-#define SRST_CORE3 3
-#define SRST_CORE0_PO 4
-#define SRST_CORE1_PO 5
-#define SRST_CORE2_PO 6
-#define SRST_CORE3_PO 7
-#define SRST_PDCORE_STRSYS 8
-#define SRST_PDBUS_STRSYS 9
-#define SRST_L2C 10
-#define SRST_TOPDBG 11
-#define SRST_CORE0_DBG 12
-#define SRST_CORE1_DBG 13
-#define SRST_CORE2_DBG 14
-#define SRST_CORE3_DBG 15
-
-#define SRST_PDBUG_AHB_ARBITOR 16
-#define SRST_EFUSE256 17
-#define SRST_DMAC1 18
-#define SRST_INTMEM 19
-#define SRST_ROM 20
-#define SRST_SPDIF8CH 21
-#define SRST_TIMER 22
-#define SRST_I2S0 23
-#define SRST_SPDIF 24
-#define SRST_TIMER0 25
-#define SRST_TIMER1 26
-#define SRST_TIMER2 27
-#define SRST_TIMER3 28
-#define SRST_TIMER4 29
-#define SRST_TIMER5 30
-#define SRST_EFUSE 31
-
-#define SRST_GPIO0 32
-#define SRST_GPIO1 33
-#define SRST_GPIO2 34
-#define SRST_GPIO3 35
-#define SRST_GPIO4 36
-#define SRST_GPIO5 37
-#define SRST_GPIO6 38
-#define SRST_GPIO7 39
-#define SRST_GPIO8 40
-#define SRST_I2C0 42
-#define SRST_I2C1 43
-#define SRST_I2C2 44
-#define SRST_I2C3 45
-#define SRST_I2C4 46
-#define SRST_I2C5 47
-
-#define SRST_DWPWM 48
-#define SRST_MMC_PERI 49
-#define SRST_PERIPH_MMU 50
-#define SRST_DAP 51
-#define SRST_DAP_SYS 52
-#define SRST_TPIU 53
-#define SRST_PMU_APB 54
-#define SRST_GRF 55
-#define SRST_PMU 56
-#define SRST_PERIPH_AXI 57
-#define SRST_PERIPH_AHB 58
-#define SRST_PERIPH_APB 59
-#define SRST_PERIPH_NIU 60
-#define SRST_PDPERI_AHB_ARBI 61
-#define SRST_EMEM 62
-#define SRST_USB_PERI 63
-
-#define SRST_DMAC2 64
-#define SRST_MAC 66
-#define SRST_GPS 67
-#define SRST_RKPWM 69
-#define SRST_CCP 71
-#define SRST_USBHOST0 72
-#define SRST_HSIC 73
-#define SRST_HSIC_AUX 74
-#define SRST_HSIC_PHY 75
-#define SRST_HSADC 76
-#define SRST_NANDC0 77
-#define SRST_NANDC1 78
-
-#define SRST_TZPC 80
-#define SRST_SPI0 83
-#define SRST_SPI1 84
-#define SRST_SPI2 85
-#define SRST_SARADC 87
-#define SRST_PDALIVE_NIU 88
-#define SRST_PDPMU_INTMEM 89
-#define SRST_PDPMU_NIU 90
-#define SRST_SGRF 91
-
-#define SRST_VIO_ARBI 96
-#define SRST_RGA_NIU 97
-#define SRST_VIO0_NIU_AXI 98
-#define SRST_VIO_NIU_AHB 99
-#define SRST_LCDC0_AXI 100
-#define SRST_LCDC0_AHB 101
-#define SRST_LCDC0_DCLK 102
-#define SRST_VIO1_NIU_AXI 103
-#define SRST_VIP 104
-#define SRST_RGA_CORE 105
-#define SRST_IEP_AXI 106
-#define SRST_IEP_AHB 107
-#define SRST_RGA_AXI 108
-#define SRST_RGA_AHB 109
-#define SRST_ISP 110
-#define SRST_EDP 111
-
-#define SRST_VCODEC_AXI 112
-#define SRST_VCODEC_AHB 113
-#define SRST_VIO_H2P 114
-#define SRST_MIPIDSI0 115
-#define SRST_MIPIDSI1 116
-#define SRST_MIPICSI 117
-#define SRST_LVDS_PHY 118
-#define SRST_LVDS_CON 119
-#define SRST_GPU 120
-#define SRST_HDMI 121
-#define SRST_CORE_PVTM 124
-#define SRST_GPU_PVTM 125
-
-#define SRST_MMC0 128
-#define SRST_SDIO0 129
-#define SRST_SDIO1 130
-#define SRST_EMMC 131
-#define SRST_USBOTG_AHB 132
-#define SRST_USBOTG_PHY 133
-#define SRST_USBOTG_CON 134
-#define SRST_USBHOST0_AHB 135
-#define SRST_USBHOST0_PHY 136
-#define SRST_USBHOST0_CON 137
-#define SRST_USBHOST1_AHB 138
-#define SRST_USBHOST1_PHY 139
-#define SRST_USBHOST1_CON 140
-#define SRST_USB_ADP 141
-#define SRST_ACC_EFUSE 142
-
-#define SRST_CORESIGHT 144
-#define SRST_PD_CORE_AHB_NOC 145
-#define SRST_PD_CORE_APB_NOC 146
-#define SRST_PD_CORE_MP_AXI 147
-#define SRST_GIC 148
-#define SRST_LCDC_PWM0 149
-#define SRST_LCDC_PWM1 150
-#define SRST_VIO0_H2P_BRG 151
-#define SRST_VIO1_H2P_BRG 152
-#define SRST_RGA_H2P_BRG 153
-#define SRST_HEVC 154
-#define SRST_TSADC 159
-
-#define SRST_DDRPHY0 160
-#define SRST_DDRPHY0_APB 161
-#define SRST_DDRCTRL0 162
-#define SRST_DDRCTRL0_APB 163
-#define SRST_DDRPHY0_CTRL 164
-#define SRST_DDRPHY1 165
-#define SRST_DDRPHY1_APB 166
-#define SRST_DDRCTRL1 167
-#define SRST_DDRCTRL1_APB 168
-#define SRST_DDRPHY1_CTRL 169
-#define SRST_DDRMSCH0 170
-#define SRST_DDRMSCH1 171
-#define SRST_CRYPTO 174
-#define SRST_C2C_HOST 175
-
-#define SRST_LCDC1_AXI 176
-#define SRST_LCDC1_AHB 177
-#define SRST_LCDC1_DCLK 178
-#define SRST_UART0 179
-#define SRST_UART1 180
-#define SRST_UART2 181
-#define SRST_UART3 182
-#define SRST_UART4 183
-#define SRST_SIMC 186
-#define SRST_PS2C 187
-#define SRST_TSP 188
-#define SRST_TSP_CLKIN0 189
-#define SRST_TSP_CLKIN1 190
-#define SRST_TSP_27M 191
-
-#endif
diff --git a/include/dwc3-sti-glue.h b/include/dwc3-sti-glue.h
deleted file mode 100644
index 546ffba..0000000
--- a/include/dwc3-sti-glue.h
+++ /dev/null
@@ -1,41 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0+ */
-/*
- * Copyright (C) 2017, STMicroelectronics - All Rights Reserved
- * Author(s): Patrice Chotard, <patrice.chotard@foss.st.com> for STMicroelectronics.
- */
-
-#ifndef __DWC3_STI_UBOOT_H_
-#define __DWC3_STI_UBOOT_H_
-
-/* glue registers */
-#include <linux/bitops.h>
-#define CLKRST_CTRL 0x00
-#define AUX_CLK_EN BIT(0)
-#define SW_PIPEW_RESET_N BIT(4)
-#define EXT_CFG_RESET_N BIT(8)
-
-#define XHCI_REVISION BIT(12)
-
-#define USB2_VBUS_MNGMNT_SEL1 0x2C
-#define USB2_VBUS_UTMIOTG 0x1
-
-#define SEL_OVERRIDE_VBUSVALID(n) ((n) << 0)
-#define SEL_OVERRIDE_POWERPRESENT(n) ((n) << 4)
-#define SEL_OVERRIDE_BVALID(n) ((n) << 8)
-
-/* Static DRD configuration */
-#define USB3_CONTROL_MASK 0xf77
-
-#define USB3_DEVICE_NOT_HOST BIT(0)
-#define USB3_FORCE_VBUSVALID BIT(1)
-#define USB3_DELAY_VBUSVALID BIT(2)
-#define USB3_SEL_FORCE_OPMODE BIT(4)
-#define USB3_FORCE_OPMODE(n) ((n) << 5)
-#define USB3_SEL_FORCE_DPPULLDOWN2 BIT(8)
-#define USB3_FORCE_DPPULLDOWN2 BIT(9)
-#define USB3_SEL_FORCE_DMPULLDOWN2 BIT(10)
-#define USB3_FORCE_DMPULLDOWN2 BIT(11)
-
-int sti_dwc3_init(enum usb_dr_mode mode);
-
-#endif /* __DWC3_STI_UBOOT_H_ */
diff --git a/include/efi_loader.h b/include/efi_loader.h
index dcae6a7..1d75d97 100644
--- a/include/efi_loader.h
+++ b/include/efi_loader.h
@@ -852,21 +852,6 @@
/* Adds a range into the EFI memory map */
efi_status_t efi_add_memory_map(u64 start, u64 size, int memory_type);
-/**
- * efi_add_memory_map_pg() - add pages to the memory map
- *
- * @start: start address, must be a multiple of
- * EFI_PAGE_SIZE
- * @pages: number of pages to add
- * @memory_type: type of memory added
- * @overlap_conventional: region may only overlap free(conventional)
- * memory
- * Return: status code
- */
-efi_status_t efi_add_memory_map_pg(u64 start, u64 pages,
- int memory_type,
- bool overlap_conventional);
-
/* Called by board init to initialize the EFI drivers */
efi_status_t efi_driver_init(void);
/* Called when a block device is added */
@@ -1264,6 +1249,21 @@
void efi_add_known_memory(void);
/**
+ * efi_map_update_notify() - notify EFI of memory map changes
+ *
+ * @addr: start of memory area
+ * @size: size of memory area
+ * @op: type of change
+ * Return: 0 if change could be processed
+ */
+#ifdef CONFIG_EFI_LOADER
+int efi_map_update_notify(phys_addr_t addr, phys_size_t size,
+ enum lmb_map_op op);
+#else
+#define efi_map_update_notify(addr, size, op) (0)
+#endif
+
+/**
* efi_load_option_dp_join() - join device-paths for load option
*
* @dp: in: binary device-path, out: joined device-path
diff --git a/include/env/ti/mmc.h b/include/env/ti/mmc.h
index d07189b..dbb0e35 100644
--- a/include/env/ti/mmc.h
+++ b/include/env/ti/mmc.h
@@ -44,6 +44,7 @@
"mmcloados=" \
"if test ${boot_fdt} = yes || test ${boot_fdt} = try; then " \
"if run loadfdt; then " \
+ "run get_overlay_mmc;" \
"bootz ${loadaddr} - ${fdtaddr}; " \
"else " \
"if test ${boot_fdt} = try; then " \
diff --git a/include/image.h b/include/image.h
index 8a9f779..c1db838 100644
--- a/include/image.h
+++ b/include/image.h
@@ -232,6 +232,7 @@
IH_TYPE_FDT_LEGACY, /* Binary Flat Device Tree Blob in a Legacy Image */
IH_TYPE_RENESAS_SPKG, /* Renesas SPKG image */
IH_TYPE_STARFIVE_SPL, /* StarFive SPL image */
+ IH_TYPE_TFA_BL31, /* TFA BL31 image */
IH_TYPE_COUNT, /* Number of image types */
};
@@ -1687,6 +1688,24 @@
*/
int image_pre_load(ulong addr);
+#if defined(USE_HOSTCC)
+/**
+ * rsa_verify_openssl() - Verify a signature against some data with openssl API
+ *
+ * Verify a RSA PKCS1.5/PSS signature against an expected hash.
+ *
+ * @info: Specifies the key and algorithms
+ * @region: Pointer to the input data
+ * @region_count: Number of region
+ * @sig: Signature
+ * @sig_len: Number of bytes in the signature
+ * Return: 0 if verified, -ve on error
+ */
+int rsa_verify_openssl(struct image_sign_info *info,
+ const struct image_region region[], int region_count,
+ uint8_t *sig, uint sig_len);
+#endif
+
/**
* fit_image_verify_required_sigs() - Verify signatures marked as 'required'
*
diff --git a/include/linux/string.h b/include/linux/string.h
index 27b2beb..d943fcc 100644
--- a/include/linux/string.h
+++ b/include/linux/string.h
@@ -72,6 +72,9 @@
#ifndef __HAVE_ARCH_STRSTR
extern char * strstr(const char *,const char *);
#endif
+#ifndef __HAVE_ARCH_STRNSTR
+extern char *strnstr(const char *, const char *, size_t);
+#endif
#ifndef __HAVE_ARCH_STRLEN
extern __kernel_size_t strlen(const char *);
#endif
diff --git a/include/lmb.h b/include/lmb.h
index d9d7435..09297a4 100644
--- a/include/lmb.h
+++ b/include/lmb.h
@@ -32,6 +32,18 @@
#define LMB_NONOTIFY BIT(2)
/**
+ * enum lmb_map_op - memory map operation
+ */
+enum lmb_map_op {
+ /** @LMB_MAP_OP_RESERVE: reserve memory */
+ LMB_MAP_OP_RESERVE = 1,
+ /** @LMB_MAP_OP_FREE: free memory */
+ LMB_MAP_OP_FREE,
+ /** @LMB_MAP_OP_ADD: add memory */
+ LMB_MAP_OP_ADD,
+};
+
+/**
* struct lmb_region - Description of one region
* @base: Base address of the region
* @size: Size of the region
diff --git a/include/miiphy.h b/include/miiphy.h
index 1e6c704..b879fd1 100644
--- a/include/miiphy.h
+++ b/include/miiphy.h
@@ -44,6 +44,7 @@
void miiphy_listdev(void);
+void mdio_init(struct mii_dev *bus);
struct mii_dev *mdio_alloc(void);
void mdio_free(struct mii_dev *bus);
int mdio_register(struct mii_dev *bus);
@@ -64,8 +65,6 @@
#define BB_MII_DEVNAME "bb_miiphy"
struct bb_miiphy_bus {
- char name[MDIO_NAME_LEN];
- int (*init)(struct bb_miiphy_bus *bus);
int (*mdio_active)(struct bb_miiphy_bus *bus);
int (*mdio_tristate)(struct bb_miiphy_bus *bus);
int (*set_mdio)(struct bb_miiphy_bus *bus, int v);
@@ -73,19 +72,11 @@
int (*set_mdc)(struct bb_miiphy_bus *bus, int v);
int (*delay)(struct bb_miiphy_bus *bus);
void *priv;
+ struct mii_dev mii;
};
-extern struct bb_miiphy_bus bb_miiphy_buses[];
-extern int bb_miiphy_buses_num;
-
-/**
- * bb_miiphy_init() - Initialize bit-banged MII bus driver
- *
- * It is called during the generic post-relocation init sequence.
- *
- * Return: 0 if OK
- */
-int bb_miiphy_init(void);
+struct bb_miiphy_bus *bb_miiphy_alloc(void);
+void bb_miiphy_free(struct bb_miiphy_bus *bus);
int bb_miiphy_read(struct mii_dev *miidev, int addr, int devad, int reg);
int bb_miiphy_write(struct mii_dev *miidev, int addr, int devad, int reg,
diff --git a/include/net-lwip.h b/include/net-lwip.h
index 4d7f938..64e5c72 100644
--- a/include/net-lwip.h
+++ b/include/net-lwip.h
@@ -10,6 +10,7 @@
TFTPGET
};
+void net_lwip_set_current(void);
struct netif *net_lwip_new_netif(struct udevice *udev);
struct netif *net_lwip_new_netif_noip(struct udevice *udev);
void net_lwip_remove_netif(struct netif *netif);
diff --git a/include/power/tps65941.h b/include/power/tps65941.h
index cec8533..a026ec5 100644
--- a/include/power/tps65941.h
+++ b/include/power/tps65941.h
@@ -21,10 +21,11 @@
#define TPS65941_BUCK_VOLT_MAX 3340000
#define TPS65941_BUCK_MODE_MASK 0x1
-#define TPS65941_LDO_VOLT_MASK 0x3E
+#define TPS65941_LDO_VOLT_MASK 0x7E
#define TPS65941_LDO_VOLT_MAX_HEX 0x3A
#define TPS65941_LDO_VOLT_MIN_HEX 0x4
#define TPS65941_LDO_VOLT_MAX 3300000
+#define TPS65941_LDO_VOLT_MIN 600000
#define TPS65941_LDO_MODE_MASK 0x1
#define TPS65941_LDO_BYPASS_EN 0x80
#define TP65941_BUCK_CONF_SLEW_MASK 0x7
diff --git a/include/sysinfo.h b/include/sysinfo.h
index ba2ac27..e87cf96 100644
--- a/include/sysinfo.h
+++ b/include/sysinfo.h
@@ -57,6 +57,7 @@
SYSID_SM_SYSTEM_WAKEUP,
SYSID_SM_SYSTEM_SKU,
SYSID_SM_SYSTEM_FAMILY,
+ SYSID_SM_SYSTEM_UUID,
/* Baseboard (or Module) Information (Type 2) */
SYSID_SM_BASEBOARD_MANUFACTURER,
@@ -151,6 +152,8 @@
/* For show_board_info() */
SYSID_BOARD_MODEL,
SYSID_BOARD_MANUFACTURER,
+ SYSID_BOARD_MAC_ADDR,
+ SYSID_BOARD_RAM_SIZE_MB,
SYSID_PRIOR_STAGE_VERSION,
SYSID_PRIOR_STAGE_DATE,
@@ -221,6 +224,30 @@
int (*get_data)(struct udevice *dev, int id, void **data, size_t *size);
/**
+ * get_item_count() - Get the item count of the specific data area that
+ * describes the hardware setup.
+ * @dev: The sysinfo instance to gather the data.
+ * @id: A unique identifier for the data area to be get.
+ *
+ * Return: non-negative item count if OK, -ve on error.
+ */
+ int (*get_item_count)(struct udevice *dev, int id);
+
+ /**
+ * get_data_by_index() - Get a data value by index from the platform.
+ *
+ * @dev: The sysinfo instance to gather the data.
+ * @id: A unique identifier for the data area to be get.
+ * @index: The item index, starting from 0.
+ * @data: Pointer to the address of the data area.
+ * @size: Pointer to the size of the data area.
+ *
+ * Return: 0 if OK, -ve on error.
+ */
+ int (*get_data_by_index)(struct udevice *dev, int id, int index,
+ void **data, size_t *size);
+
+ /**
* get_fit_loadable - Get the name of an image to load from FIT
* This function can be used to provide the image names based on runtime
* detection. A classic use-case would when DTBOs are used to describe
@@ -304,6 +331,32 @@
int sysinfo_get_data(struct udevice *dev, int id, void **data, size_t *size);
/**
+ * sysinfo_get_item_count() - Get the item count of the specific data area that
+ * describes the hardware setup.
+ * @dev: The sysinfo instance to gather the data.
+ * @id: A unique identifier for the data area to be get.
+ *
+ * Return: non-negative item count if OK, -EPERM if called before
+ * sysinfo_detect(), else -ve on error.
+ */
+int sysinfo_get_item_count(struct udevice *dev, int id);
+
+/**
+ * sysinfo_get_data_by_index() - Get a data value by index from the platform.
+ *
+ * @dev: The sysinfo instance to gather the data.
+ * @id: A unique identifier for the data area to be get.
+ * @index: The item index, starting from 0.
+ * @data: Pointer to the address of the data area.
+ * @size: Pointer to the size of the data area.
+ *
+ * Return: 0 if OK, -EPERM if called before sysinfo_detect(), else -ve on
+ * error.
+ */
+int sysinfo_get_data_by_index(struct udevice *dev, int id, int index,
+ void **data, size_t *size);
+
+/**
* sysinfo_get() - Return the sysinfo device for the sysinfo in question.
* @devp: Pointer to structure to receive the sysinfo device.
*
@@ -364,6 +417,18 @@
return -ENOSYS;
}
+static inline int sysinfo_get_item_count(struct udevice *dev, int id)
+{
+ return -ENOSYS;
+}
+
+static inline int sysinfo_get_data_by_index(struct udevice *dev, int id,
+ int index, void **data,
+ size_t *size)
+{
+ return -ENOSYS;
+}
+
static inline int sysinfo_get(struct udevice **devp)
{
return -ENOSYS;
diff --git a/lib/ecdsa/ecdsa-libcrypto.c b/lib/ecdsa/ecdsa-libcrypto.c
index 1c5dde6..f0095e9 100644
--- a/lib/ecdsa/ecdsa-libcrypto.c
+++ b/lib/ecdsa/ecdsa-libcrypto.c
@@ -363,8 +363,10 @@
ret = prepare_ctx(&ctx, info);
if (ret >= 0) {
ret = do_add(&ctx, fdt, fdt_key_name, info);
- if (ret < 0)
- ret = ret == -FDT_ERR_NOSPACE ? -ENOSPC : -EIO;
+ if (ret < 0) {
+ free_ctx(&ctx);
+ return ret == -FDT_ERR_NOSPACE ? -ENOSPC : -EIO;
+ }
}
free_ctx(&ctx);
diff --git a/lib/efi_driver/efi_block_device.c b/lib/efi_driver/efi_block_device.c
index d3c668d..070747d 100644
--- a/lib/efi_driver/efi_block_device.c
+++ b/lib/efi_driver/efi_block_device.c
@@ -35,8 +35,10 @@
#include <efi_driver.h>
#include <malloc.h>
#include <dm/device-internal.h>
+#include <dm/lists.h>
#include <dm/root.h>
#include <dm/tag.h>
+#include <dm/uclass-internal.h>
/**
* struct efi_blk_plat - attributes of a block device
@@ -118,13 +120,18 @@
static efi_status_t
efi_bl_create_block_device(efi_handle_t handle, void *interface)
{
- struct udevice *bdev = NULL, *parent = dm_root();
+ struct udevice *bdev = NULL, *parent;
efi_status_t ret;
+ int r;
int devnum;
char *name;
struct efi_block_io *io = interface;
struct efi_blk_plat *plat;
+ r = uclass_find_first_device(UCLASS_EFI_LOADER, &parent);
+ if (r)
+ return EFI_OUT_OF_RESOURCES;
+
devnum = blk_next_free_devnum(UCLASS_EFI_LOADER);
if (devnum < 0)
return EFI_OUT_OF_RESOURCES;
@@ -221,6 +228,24 @@
return EFI_SUCCESS;
}
+/**
+ * efi_block_device_create() - create parent for EFI block devices
+ *
+ * Create a device that serves as parent for all block devices created via
+ * ConnectController().
+ *
+ * Return: 0 for success
+ */
+static int efi_block_device_create(void)
+{
+ int ret;
+ struct udevice *dev;
+
+ ret = device_bind_driver(gd->dm_root, "EFI block driver", "efi", &dev);
+
+ return ret;
+}
+
/* Block device driver operators */
static const struct blk_ops efi_blk_ops = {
.read = efi_bl_read,
@@ -249,3 +274,5 @@
.id = UCLASS_EFI_LOADER,
.ops = &driver_ops,
};
+
+EVENT_SPY_SIMPLE(EVT_LAST_STAGE_INIT, efi_block_device_create);
diff --git a/lib/efi_loader/efi_disk.c b/lib/efi_loader/efi_disk.c
index 1f3de0a..5452640 100644
--- a/lib/efi_loader/efi_disk.c
+++ b/lib/efi_loader/efi_disk.c
@@ -531,7 +531,8 @@
/* Store first EFI system partition */
if (part && efi_system_partition.uclass_id == UCLASS_INVALID) {
- if (part_info->bootable & PART_EFI_SYSTEM_PARTITION) {
+ if (part_info &&
+ part_info->bootable & PART_EFI_SYSTEM_PARTITION) {
efi_system_partition.uclass_id = desc->uclass_id;
efi_system_partition.devnum = desc->devnum;
efi_system_partition.part = part;
diff --git a/lib/efi_loader/efi_memory.c b/lib/efi_loader/efi_memory.c
index 1212772..6d00b18 100644
--- a/lib/efi_loader/efi_memory.c
+++ b/lib/efi_loader/efi_memory.c
@@ -268,6 +268,7 @@
* memory
* Return: status code
*/
+static
efi_status_t efi_add_memory_map_pg(u64 start, u64 pages,
int memory_type,
bool overlap_conventional)
@@ -865,3 +866,30 @@
return 0;
}
+
+int efi_map_update_notify(phys_addr_t addr, phys_size_t size,
+ enum lmb_map_op op)
+{
+ u64 efi_addr;
+ u64 pages;
+ efi_status_t status;
+
+ efi_addr = (uintptr_t)map_sysmem(addr, 0);
+ pages = efi_size_in_pages(size + (efi_addr & EFI_PAGE_MASK));
+ efi_addr &= ~EFI_PAGE_MASK;
+
+ status = efi_add_memory_map_pg(efi_addr, pages,
+ op == LMB_MAP_OP_RESERVE ?
+ EFI_BOOT_SERVICES_DATA :
+ EFI_CONVENTIONAL_MEMORY,
+ false);
+ if (status != EFI_SUCCESS) {
+ log_err("LMB Map notify failure %lu\n",
+ status & ~EFI_ERROR_MASK);
+ return -1;
+ }
+ unmap_sysmem((void *)(uintptr_t)efi_addr);
+
+ return 0;
+}
+
diff --git a/lib/efi_loader/efi_var_mem.c b/lib/efi_loader/efi_var_mem.c
index b265d95..31180df9 100644
--- a/lib/efi_loader/efi_var_mem.c
+++ b/lib/efi_loader/efi_var_mem.c
@@ -19,6 +19,7 @@
*/
static struct efi_var_file __efi_runtime_data *efi_var_buf;
static struct efi_var_entry __efi_runtime_data *efi_current_var;
+static const u16 __efi_runtime_rodata vtf[] = u"VarToFile";
/**
* efi_var_mem_compare() - compare GUID and name with a variable
@@ -331,7 +332,7 @@
if (timep)
*timep = var->time;
- if (!u16_strcmp(variable_name, u"VarToFile"))
+ if (!u16_strcmp(variable_name, vtf))
return efi_var_collect_mem(data, data_size, EFI_VARIABLE_NON_VOLATILE);
old_size = *data_size;
diff --git a/lib/efi_loader/efi_variable_tee.c b/lib/efi_loader/efi_variable_tee.c
index 0d090d0..6a1fa39 100644
--- a/lib/efi_loader/efi_variable_tee.c
+++ b/lib/efi_loader/efi_variable_tee.c
@@ -41,6 +41,7 @@
extern struct efi_var_file __efi_runtime_data *efi_var_buf;
static efi_uintn_t max_buffer_size; /* comm + var + func + data */
static efi_uintn_t max_payload_size; /* func + data */
+static const u16 __efi_runtime_rodata pk[] = u"PK";
struct mm_connection {
struct udevice *tee;
@@ -858,7 +859,7 @@
if (alt_ret != EFI_SUCCESS)
goto out;
- if (!u16_strcmp(variable_name, u"PK"))
+ if (!u16_strcmp(variable_name, pk))
alt_ret = efi_init_secure_state();
out:
free(comm_buf);
diff --git a/lib/lmb.c b/lib/lmb.c
index 7ca4459..93fc1be 100644
--- a/lib/lmb.c
+++ b/lib/lmb.c
@@ -23,10 +23,6 @@
DECLARE_GLOBAL_DATA_PTR;
-#define MAP_OP_RESERVE (u8)0x1
-#define MAP_OP_FREE (u8)0x2
-#define MAP_OP_ADD (u8)0x3
-
/*
* The following low level LMB functions must not access the global LMB memory
* map since they are also used to manage IOVA memory maps in iommu drivers like
@@ -430,42 +426,12 @@
static struct lmb lmb;
-static bool lmb_should_notify(u32 flags)
-{
- return !lmb.test && !(flags & LMB_NONOTIFY) &&
- CONFIG_IS_ENABLED(EFI_LOADER);
-}
-
-static int lmb_map_update_notify(phys_addr_t addr, phys_size_t size, u8 op,
- u32 flags)
+static int lmb_map_update_notify(phys_addr_t addr, phys_size_t size,
+ enum lmb_map_op op, u32 flags)
{
- u64 efi_addr;
- u64 pages;
- efi_status_t status;
-
- if (op != MAP_OP_RESERVE && op != MAP_OP_FREE && op != MAP_OP_ADD) {
- log_err("Invalid map update op received (%d)\n", op);
- return -1;
- }
-
- if (!lmb_should_notify(flags))
- return 0;
-
- efi_addr = (uintptr_t)map_sysmem(addr, 0);
- pages = efi_size_in_pages(size + (efi_addr & EFI_PAGE_MASK));
- efi_addr &= ~EFI_PAGE_MASK;
-
- status = efi_add_memory_map_pg(efi_addr, pages,
- op == MAP_OP_RESERVE ?
- EFI_BOOT_SERVICES_DATA :
- EFI_CONVENTIONAL_MEMORY,
- false);
- if (status != EFI_SUCCESS) {
- log_err("%s: LMB Map notify failure %lu\n", __func__,
- status & ~EFI_ERROR_MASK);
- return -1;
- }
- unmap_sysmem((void *)(uintptr_t)efi_addr);
+ if (CONFIG_IS_ENABLED(EFI_LOADER) &&
+ !lmb.test && !(flags & LMB_NONOTIFY))
+ return efi_map_update_notify(addr, size, op);
return 0;
}
@@ -642,7 +608,7 @@
if (ret)
return ret;
- return lmb_map_update_notify(base, size, MAP_OP_ADD, LMB_NONE);
+ return lmb_map_update_notify(base, size, LMB_MAP_OP_ADD, LMB_NONE);
}
long lmb_free_flags(phys_addr_t base, phys_size_t size,
@@ -654,7 +620,7 @@
if (ret < 0)
return ret;
- return lmb_map_update_notify(base, size, MAP_OP_FREE, flags);
+ return lmb_map_update_notify(base, size, LMB_MAP_OP_FREE, flags);
}
long lmb_free(phys_addr_t base, phys_size_t size)
@@ -671,7 +637,7 @@
if (ret)
return ret;
- return lmb_map_update_notify(base, size, MAP_OP_RESERVE, flags);
+ return lmb_map_update_notify(base, size, LMB_MAP_OP_RESERVE, flags);
}
static phys_addr_t _lmb_alloc_base(phys_size_t size, ulong align,
@@ -712,7 +678,7 @@
return 0;
ret = lmb_map_update_notify(base, size,
- MAP_OP_RESERVE,
+ LMB_MAP_OP_RESERVE,
flags);
if (ret)
return ret;
diff --git a/lib/lwip/lwip/src/apps/tftp/tftp.c b/lib/lwip/lwip/src/apps/tftp/tftp.c
index 56aeabc..63b1e0e 100644
--- a/lib/lwip/lwip/src/apps/tftp/tftp.c
+++ b/lib/lwip/lwip/src/apps/tftp/tftp.c
@@ -264,19 +264,55 @@
return TFTP_DEFAULT_BLOCK_SIZE;
}
+/**
+ * find_option() - check if OACK message contains option
+ *
+ * @p: message buffer
+ * @option: option key
+ * Return: option value
+ */
static const char *
find_option(struct pbuf *p, const char *option)
{
- int i;
- u16_t optlen = strlen(option);
- const char *b = p->payload;
+ const char *pos = p->payload;
+ int rem = p->len;
- for (i = 0; i + optlen + 1 < p->len; i++) {
- if (lwip_strnstr(b + i, option, optlen))
- return b + i + optlen + 2;
- }
+ /*
+ * According to RFC 2347 the OACK packet has the following format:
+ *
+ * +-------+---~~---+---+---~~---+---+---~~---+---+---~~---+---+
+ * | opc | opt1 | 0 | value1 | 0 | optN | 0 | valueN | 0 |
+ * +-------+---~~---+---+---~~---+---+---~~---+---+---~~---+---+
+ */
+
+ /* Skip opc */
+ pos += 2;
+ rem -= 2;
+ if (rem <= 0)
+ return NULL;
+
+ for (;;) {
+ int len;
+ int diff;
+
+ len = strnlen(pos, rem) + 1;
+ if (rem < len)
+ break;
+ diff = strcmp(pos, option);
+ /* Skip option */
+ pos += len;
+ rem -= len;
+ len = strnlen(pos, rem) + 1;
+ if (rem < len)
+ break;
+ if (!diff)
+ return pos;
+ /* Skip value */
+ pos += len;
+ rem -= len;
+ }
- return NULL;
+ return NULL;
}
static void
diff --git a/lib/lwip/u-boot/arch/cc.h b/lib/lwip/u-boot/arch/cc.h
index de13884..6104c29 100644
--- a/lib/lwip/u-boot/arch/cc.h
+++ b/lib/lwip/u-boot/arch/cc.h
@@ -34,7 +34,7 @@
x, __LINE__, __FILE__); } while (0)
#define atoi(str) (int)dectoul(str, NULL)
-#define lwip_strnstr(a, b, c) strstr(a, b)
+#define lwip_strnstr(a, b, c) strnstr(a, b, c)
#define LWIP_ERR_T int
#define LWIP_CONST_CAST(target_type, val) ((target_type)((uintptr_t)val))
diff --git a/lib/mbedtls/external/mbedtls/framework b/lib/mbedtls/external/mbedtls/framework
deleted file mode 160000
index 750634d..0000000
--- a/lib/mbedtls/external/mbedtls/framework
+++ /dev/null
@@ -1 +0,0 @@
-Subproject commit 750634d3a51eb9d61b59fd5d801546927c946588
diff --git a/lib/rsa/rsa-verify.c b/lib/rsa/rsa-verify.c
index d3b4f71..b74aaf8 100644
--- a/lib/rsa/rsa-verify.c
+++ b/lib/rsa/rsa-verify.c
@@ -565,6 +565,11 @@
uint8_t hash[info->crypto->key_len];
int ret;
+#ifdef USE_HOSTCC
+ if (!info->fdt_blob)
+ return rsa_verify_openssl(info, region, region_count, sig, sig_len);
+#endif
+
/*
* Verify that the checksum-length does not exceed the
* rsa-signature-length
diff --git a/lib/smbios.c b/lib/smbios.c
index 78cee8c..7c9701a 100644
--- a/lib/smbios.c
+++ b/lib/smbios.c
@@ -429,6 +429,8 @@
struct smbios_type1 *t;
int len = sizeof(*t);
char *serial_str = env_get("serial#");
+ size_t uuid_len;
+ void *uuid;
t = map_sysmem(*current, len);
memset(t, 0, len);
@@ -450,6 +452,10 @@
SYSID_SM_SYSTEM_SERIAL,
NULL);
}
+ if (!sysinfo_get_data(ctx->dev, SYSID_SM_SYSTEM_UUID, &uuid,
+ &uuid_len) &&
+ uuid_len == sizeof(t->uuid))
+ memcpy(t->uuid, uuid, sizeof(t->uuid));
t->wakeup_type = smbios_get_val_si(ctx, "wakeup-type",
SYSID_SM_SYSTEM_WAKEUP,
SMBIOS_WAKEUP_TYPE_UNKNOWN);
diff --git a/lib/string.c b/lib/string.c
index 0e0900d..d56f88d 100644
--- a/lib/string.c
+++ b/lib/string.c
@@ -15,13 +15,14 @@
* reentrant and should be faster). Use only strsep() in new code, please.
*/
+#include <asm/sections.h>
#include <config.h>
+#include <limits.h>
#include <linux/compiler.h>
-#include <linux/types.h>
-#include <linux/string.h>
#include <linux/ctype.h>
+#include <linux/string.h>
+#include <linux/types.h>
#include <malloc.h>
-#include <asm/sections.h>
/**
* strncasecmp - Case insensitive, length-limited string comparison
@@ -679,30 +680,48 @@
return p;
}
-#ifndef __HAVE_ARCH_STRSTR
+#ifndef __HAVE_ARCH_STRNSTR
/**
- * strstr - Find the first substring in a %NUL terminated string
- * @s1: The string to be searched
- * @s2: The string to search for
+ * strnstr() - find the first substring occurrence in a NUL terminated string
+ *
+ * @s1: string to be searched
+ * @s2: string to search for
+ * @len: maximum number of characters in s2 to consider
+ *
+ * Return: pointer to the first occurrence or NULL
*/
-char * strstr(const char * s1,const char * s2)
+char *strnstr(const char *s1, const char *s2, size_t len)
{
- int l1, l2;
+ size_t l1, l2;
+ l1 = strnlen(s1, len);
l2 = strlen(s2);
- if (!l2)
- return (char *) s1;
- l1 = strlen(s1);
- while (l1 >= l2) {
- l1--;
- if (!memcmp(s1,s2,l2))
+
+ for (; l1 >= l2; --l1, ++s1) {
+ if (!memcmp(s1, s2, l2))
return (char *) s1;
- s1++;
}
+
return NULL;
}
#endif
+#ifndef __HAVE_ARCH_STRSTR
+/**
+ * strstr() - find the first substring occurrence in a NUL terminated string
+ *
+ * @s1: string to be searched
+ * @s2: string to search for
+ * @len: maximum number of characters in s2 to consider
+ *
+ * Return: pointer to the first occurrence or NULL
+ */
+char *strstr(const char *s1, const char *s2)
+{
+ return strnstr(s1, s2, SIZE_MAX);
+}
+#endif
+
#ifndef __HAVE_ARCH_MEMCHR
/**
* memchr - Find a character in an area of memory.
diff --git a/lib/tiny-printf.c b/lib/tiny-printf.c
index 0503c17..faf55d7 100644
--- a/lib/tiny-printf.c
+++ b/lib/tiny-printf.c
@@ -211,6 +211,7 @@
bool lz = false;
int width = 0;
bool islong = false;
+ bool force_char = false;
ch = *(fmt++);
if (ch == '-')
@@ -300,6 +301,8 @@
break;
case 'c':
out(info, (char)(va_arg(va, int)));
+ /* For the case when it's \0 char */
+ force_char = true;
break;
case 's':
p = va_arg(va, char*);
@@ -317,8 +320,10 @@
while (width-- > 0)
info->putc(info, lz ? '0' : ' ');
if (p) {
- while ((ch = *p++))
+ while ((ch = *p++) || force_char) {
info->putc(info, ch);
+ force_char = false;
+ }
}
}
}
diff --git a/lib/uuid.c b/lib/uuid.c
index 97388f5..7565877 100644
--- a/lib/uuid.c
+++ b/lib/uuid.c
@@ -120,6 +120,10 @@
EFI_BLOCK_IO_PROTOCOL_GUID,
},
{
+ "Disk IO",
+ EFI_DISK_IO_PROTOCOL_GUID,
+ },
+ {
"Simple File System",
EFI_SIMPLE_FILE_SYSTEM_PROTOCOL_GUID,
},
@@ -128,6 +132,10 @@
EFI_LOADED_IMAGE_PROTOCOL_GUID,
},
{
+ "Loaded Image Device Path",
+ EFI_LOADED_IMAGE_DEVICE_PATH_PROTOCOL_GUID,
+ },
+ {
"Graphics Output",
EFI_GRAPHICS_OUTPUT_PROTOCOL_GUID,
},
@@ -140,10 +148,18 @@
EFI_HII_DATABASE_PROTOCOL_GUID,
},
{
+ "HII Config Access",
+ EFI_HII_CONFIG_ACCESS_PROTOCOL_GUID,
+ },
+ {
"HII Config Routing",
EFI_HII_CONFIG_ROUTING_PROTOCOL_GUID,
},
{
+ "Load File",
+ EFI_LOAD_FILE_PROTOCOL_GUID,
+ },
+ {
"Load File2",
EFI_LOAD_FILE2_PROTOCOL_GUID,
},
diff --git a/net/lwip/dhcp.c b/net/lwip/dhcp.c
index e7d9147..3b7e470 100644
--- a/net/lwip/dhcp.c
+++ b/net/lwip/dhcp.c
@@ -115,7 +115,7 @@
int ret;
struct udevice *dev;
- eth_set_current();
+ net_lwip_set_current();
dev = eth_get_dev();
if (!dev) {
diff --git a/net/lwip/dns.c b/net/lwip/dns.c
index 1de63c9..149bdb7 100644
--- a/net/lwip/dns.c
+++ b/net/lwip/dns.c
@@ -121,7 +121,7 @@
if (argc == 3)
var = argv[2];
- eth_set_current();
+ net_lwip_set_current();
return dns_loop(eth_get_dev(), name, var);
}
diff --git a/net/lwip/net-lwip.c b/net/lwip/net-lwip.c
index b863047..cab1dd7 100644
--- a/net/lwip/net-lwip.c
+++ b/net/lwip/net-lwip.c
@@ -127,6 +127,20 @@
return 0;
}
+/* Initialize the lwIP stack and the ethernet devices and set current device */
+void net_lwip_set_current(void)
+{
+ static bool init_done;
+
+ if (!init_done) {
+ eth_init_rings();
+ eth_init();
+ lwip_init();
+ init_done = true;
+ }
+ eth_set_current();
+}
+
static struct netif *new_netif(struct udevice *udev, bool with_ip)
{
unsigned char enetaddr[ARP_HLEN];
@@ -134,19 +148,10 @@
ip4_addr_t ip, mask, gw;
struct netif *netif;
int ret = 0;
- static bool first_call = true;
if (!udev)
return NULL;
- if (first_call) {
- eth_init_rings();
- /* Pick a valid active device, if any */
- eth_init();
- lwip_init();
- first_call = false;
- }
-
if (eth_start_udev(udev) < 0) {
log_err("Could not start %s\n", udev->name);
return NULL;
diff --git a/net/lwip/ping.c b/net/lwip/ping.c
index aa61753..200a702 100644
--- a/net/lwip/ping.c
+++ b/net/lwip/ping.c
@@ -168,7 +168,7 @@
if (!ipaddr_aton(argv[1], &addr))
return CMD_RET_USAGE;
- eth_set_current();
+ net_lwip_set_current();
if (ping_loop(eth_get_dev(), &addr) < 0)
return CMD_RET_FAILURE;
diff --git a/net/lwip/tftp.c b/net/lwip/tftp.c
index fc4aff5..123d66b 100644
--- a/net/lwip/tftp.c
+++ b/net/lwip/tftp.c
@@ -280,7 +280,7 @@
goto out;
}
- eth_set_current();
+ net_lwip_set_current();
if (tftp_loop(eth_get_dev(), laddr, fname, srvip, port) < 0)
ret = CMD_RET_FAILURE;
diff --git a/net/lwip/wget.c b/net/lwip/wget.c
index b76f6c0..14f27d4 100644
--- a/net/lwip/wget.c
+++ b/net/lwip/wget.c
@@ -354,7 +354,7 @@
int wget_do_request(ulong dst_addr, char *uri)
{
- eth_set_current();
+ net_lwip_set_current();
if (!wget_info)
wget_info = &default_wget_info;
@@ -433,10 +433,15 @@
if (!strncmp(uri, "http://", strlen("http://"))) {
prefix_len = strlen("http://");
- } else if (!strncmp(uri, "https://", strlen("https://"))) {
- prefix_len = strlen("https://");
+ } else if (CONFIG_IS_ENABLED(WGET_HTTPS)) {
+ if (!strncmp(uri, "https://", strlen("https://"))) {
+ prefix_len = strlen("https://");
+ } else {
+ log_err("only http(s):// is supported\n");
+ return false;
+ }
} else {
- log_err("only http(s):// is supported\n");
+ log_err("only http:// is supported\n");
return false;
}
diff --git a/test/lib/string.c b/test/lib/string.c
index 8d22f3f..31391a3 100644
--- a/test/lib/string.c
+++ b/test/lib/string.c
@@ -11,6 +11,7 @@
#include <command.h>
#include <log.h>
+#include <string.h>
#include <test/lib.h>
#include <test/test.h>
#include <test/ut.h>
@@ -221,3 +222,42 @@
return 0;
}
LIB_TEST(lib_memdup, 0);
+
+/** lib_strnstr() - unit test for strnstr() */
+static int lib_strnstr(struct unit_test_state *uts)
+{
+ const char *s1 = "Itsy Bitsy Teenie Weenie";
+ const char *s2 = "eenie";
+ const char *s3 = "eery";
+
+ ut_asserteq_ptr(&s1[12], strnstr(s1, s2, SIZE_MAX));
+ ut_asserteq_ptr(&s1[12], strnstr(s1, s2, 17));
+ ut_assertnull(strnstr(s1, s2, 16));
+ ut_assertnull(strnstr(s1, s2, 0));
+ ut_asserteq_ptr(&s1[13], strnstr(&s1[3], &s2[1], SIZE_MAX));
+ ut_asserteq_ptr(&s1[13], strnstr(&s1[3], &s2[1], 14));
+ ut_assertnull(strnstr(&s1[3], &s2[1], 13));
+ ut_assertnull(strnstr(&s1[3], &s2[1], 0));
+ ut_assertnull(strnstr(s1, s3, SIZE_MAX));
+ ut_assertnull(strnstr(s1, s3, 0));
+
+ return 0;
+}
+LIB_TEST(lib_strnstr, 0);
+
+/** lib_strstr() - unit test for strstr() */
+static int lib_strstr(struct unit_test_state *uts)
+{
+ const char *s1 = "Itsy Bitsy Teenie Weenie";
+ const char *s2 = "eenie";
+ const char *s3 = "easy";
+
+ ut_asserteq_ptr(&s1[12], strstr(s1, s2));
+ ut_asserteq_ptr(&s1[13], strstr(&s1[3], &s2[1]));
+ ut_assertnull(strstr(s1, s3));
+ ut_asserteq_ptr(&s1[2], strstr(s1, &s3[2]));
+ ut_asserteq_ptr(&s1[8], strstr(&s1[5], &s3[2]));
+
+ return 0;
+}
+LIB_TEST(lib_strstr, 0);
diff --git a/test/py/tests/test_event_dump.py b/test/py/tests/test_event_dump.py
index 45143c1..177b982 100644
--- a/test/py/tests/test_event_dump.py
+++ b/test/py/tests/test_event_dump.py
@@ -19,6 +19,7 @@
EVT_FT_FIXUP bootmeth_vbe_ft_fixup .*boot/vbe_request.c:.*
EVT_FT_FIXUP bootmeth_vbe_simple_ft_fixup .*boot/vbe_simple_os.c:.*
EVT_LAST_STAGE_INIT alloc_write_acpi_tables .*lib/acpi/acpi_table.c:.*
+EVT_LAST_STAGE_INIT efi_block_device_create .*lib/efi_driver/efi_block_device.c:.*
EVT_LAST_STAGE_INIT install_smbios_table .*lib/efi_loader/efi_smbios.c:.*
EVT_MISC_INIT_F sandbox_early_getopt_check .*arch/sandbox/cpu/start.c:.*
EVT_TEST h_adder_simple .*test/common/event.c:'''
diff --git a/test/py/tests/test_spi.py b/test/py/tests/test_spi.py
index 0abdfa7..d57db91 100644
--- a/test/py/tests/test_spi.py
+++ b/test/py/tests/test_spi.py
@@ -119,37 +119,35 @@
pytest.fail('Not recognized the SPI flash part name')
m = re.search('page size (.+?) Bytes', output)
- if m:
- try:
- page_size = int(m.group(1))
- except ValueError:
- pytest.fail('Not recognized the SPI page size')
+ assert m
+ try:
+ page_size = int(m.group(1))
+ except ValueError:
+ pytest.fail('Not recognized the SPI page size')
m = re.search('erase size (.+?) KiB', output)
- if m:
- try:
- erase_size = int(m.group(1))
- except ValueError:
- pytest.fail('Not recognized the SPI erase size')
-
+ assert m
+ try:
+ erase_size = int(m.group(1))
erase_size *= 1024
+ except ValueError:
+ pytest.fail('Not recognized the SPI erase size')
m = re.search('total (.+?) MiB', output)
- if m:
- try:
- total_size = int(m.group(1))
- except ValueError:
- pytest.fail('Not recognized the SPI total size')
-
+ assert m
+ try:
+ total_size = int(m.group(1))
total_size *= 1024 * 1024
+ except ValueError:
+ pytest.fail('Not recognized the SPI total size')
m = re.search('Detected (.+?) with', output)
- if m:
- try:
- flash_part = m.group(1)
- assert flash_part == part_name
- except ValueError:
- pytest.fail('Not recognized the SPI flash part')
+ assert m
+ try:
+ flash_part = m.group(1)
+ assert flash_part == part_name
+ except ValueError:
+ pytest.fail('Not recognized the SPI flash part')
global SPI_DATA
SPI_DATA = {
diff --git a/test/py/tests/test_ums.py b/test/py/tests/test_ums.py
index 749b160..387571c 100644
--- a/test/py/tests/test_ums.py
+++ b/test/py/tests/test_ums.py
@@ -113,14 +113,12 @@
mount_subdir = env__block_devs[0]['writable_fs_subdir']
part_num = env__block_devs[0]['writable_fs_partition']
host_ums_part_node = '%s-part%d' % (host_ums_dev_node, part_num)
+ test_f = u_boot_utils.PersistentRandomFile(u_boot_console, 'ums.bin',
+ 1024 * 1024);
+ mounted_test_fn = mount_point + '/' + mount_subdir + test_f.fn
else:
host_ums_part_node = host_ums_dev_node
- test_f = u_boot_utils.PersistentRandomFile(u_boot_console, 'ums.bin',
- 1024 * 1024);
- if have_writable_fs_partition:
- mounted_test_fn = mount_point + '/' + mount_subdir + test_f.fn
-
def start_ums():
"""Start U-Boot's ums shell command.
@@ -197,25 +195,23 @@
ignore_errors)
ignore_cleanup_errors = True
- try:
- start_ums()
- if not have_writable_fs_partition:
- # Skip filesystem-based testing if not configured
- return
+ if have_writable_fs_partition:
try:
- mount()
- u_boot_console.log.action('Writing test file via UMS')
- cmd = ('rm', '-f', mounted_test_fn)
- u_boot_utils.run_and_log(u_boot_console, cmd)
- if os.path.exists(mounted_test_fn):
- raise Exception('Could not rm target UMS test file')
- cmd = ('cp', test_f.abs_fn, mounted_test_fn)
- u_boot_utils.run_and_log(u_boot_console, cmd)
- ignore_cleanup_errors = False
+ start_ums()
+ try:
+ mount()
+ u_boot_console.log.action('Writing test file via UMS')
+ cmd = ('rm', '-f', mounted_test_fn)
+ u_boot_utils.run_and_log(u_boot_console, cmd)
+ if os.path.exists(mounted_test_fn):
+ raise Exception('Could not rm target UMS test file')
+ cmd = ('cp', test_f.abs_fn, mounted_test_fn)
+ u_boot_utils.run_and_log(u_boot_console, cmd)
+ ignore_cleanup_errors = False
+ finally:
+ umount(ignore_errors=ignore_cleanup_errors)
finally:
- umount(ignore_errors=ignore_cleanup_errors)
- finally:
- stop_ums(ignore_errors=ignore_cleanup_errors)
+ stop_ums(ignore_errors=ignore_cleanup_errors)
ignore_cleanup_errors = True
try:
diff --git a/test/py/tests/test_usb.py b/test/py/tests/test_usb.py
index 566d73b..9bef883 100644
--- a/test/py/tests/test_usb.py
+++ b/test/py/tests/test_usb.py
@@ -580,6 +580,8 @@
elif fs in ['ext4', 'ext2']:
file, size, expected_crc32 = \
usb_ext4load_ext4write(u_boot_console, fs, x, part)
+ else:
+ raise Exception('Unsupported filesystem type %s' % fs)
offset = random.randrange(128, 1024, 128)
output = u_boot_console.run_command(
diff --git a/tools/.gitignore b/tools/.gitignore
index 0108c56..6a5c613 100644
--- a/tools/.gitignore
+++ b/tools/.gitignore
@@ -29,6 +29,7 @@
/mxsboot
/ncb
/prelink-riscv
+/preload_check_sign
/printinitialenv
/proftool
/relocate-rela
diff --git a/tools/Kconfig b/tools/Kconfig
index 01ff0fc..8e272ee 100644
--- a/tools/Kconfig
+++ b/tools/Kconfig
@@ -9,6 +9,11 @@
some cases the system dtc may not support all required features
and the path to a different version should be given here.
+config TOOLS_IMAGE_PRE_LOAD
+ def_bool y
+ help
+ Enable pre-load signature support in the tools builds.
+
config TOOLS_CRC16
def_bool y
help
diff --git a/tools/Makefile b/tools/Makefile
index 237fa90..e5f5eea 100644
--- a/tools/Makefile
+++ b/tools/Makefile
@@ -66,6 +66,7 @@
hostprogs-y += dumpimage mkimage
hostprogs-$(CONFIG_TOOLS_LIBCRYPTO) += fit_info fit_check_sign
hostprogs-$(CONFIG_TOOLS_LIBCRYPTO) += fdt_add_pubkey
+hostprogs-$(CONFIG_TOOLS_LIBCRYPTO) += preload_check_sign
ifneq ($(CONFIG_CMD_BOOTEFI_SELFTEST)$(CONFIG_FWU_MDATA_GPT_BLK),)
hostprogs-y += file2include
@@ -89,6 +90,8 @@
AES_OBJS-$(CONFIG_TOOLS_LIBCRYPTO) := $(addprefix generated/lib/aes/, \
aes-encrypt.o aes-decrypt.o)
+PRELOAD_OBJS-$(CONFIG_TOOLS_LIBCRYPTO) := generated/boot/image-pre-load.o
+
# Cryptographic helpers and image types that depend on openssl/libcrypto
LIBCRYPTO_OBJS-$(CONFIG_TOOLS_LIBCRYPTO) := \
generated/lib/fdt-libcrypto.o \
@@ -158,6 +161,7 @@
fit_check_sign-objs := $(dumpimage-mkimage-objs) fit_check_sign.o
fdt_add_pubkey-objs := $(dumpimage-mkimage-objs) fdt_add_pubkey.o
file2include-objs := file2include.o
+preload_check_sign-objs := $(dumpimage-mkimage-objs) $(PRELOAD_OBJS-y) preload_check_sign.o
ifneq ($(CONFIG_MX23)$(CONFIG_MX28)$(CONFIG_TOOLS_LIBCRYPTO),)
# Add CFG_MXS into host CFLAGS, so we can check whether or not register
@@ -195,6 +199,7 @@
HOSTLDLIBS_fit_info := $(HOSTLDLIBS_mkimage)
HOSTLDLIBS_fit_check_sign := $(HOSTLDLIBS_mkimage)
HOSTLDLIBS_fdt_add_pubkey := $(HOSTLDLIBS_mkimage)
+HOSTLDLIBS_preload_check_sign := $(HOSTLDLIBS_mkimage)
hostprogs-$(CONFIG_EXYNOS5250) += mkexynosspl
hostprogs-$(CONFIG_EXYNOS5420) += mkexynosspl
diff --git a/tools/binman/etype/fdtmap.py b/tools/binman/etype/fdtmap.py
index f1f6217..2259404 100644
--- a/tools/binman/etype/fdtmap.py
+++ b/tools/binman/etype/fdtmap.py
@@ -106,6 +106,9 @@
Returns:
FDT map binary data
"""
+ fsw = libfdt.FdtSw()
+ fsw.finish_reservemap()
+
def _AddNode(node):
"""Add a node to the FDT map"""
for pname, prop in node.props.items():
@@ -134,8 +137,6 @@
# Build a new tree with all nodes and properties starting from that
# node
- fsw = libfdt.FdtSw()
- fsw.finish_reservemap()
with fsw.add_node(''):
fsw.property_string('image-node', node.name)
_AddNode(node)
diff --git a/tools/binman/etype/image_header.py b/tools/binman/etype/image_header.py
index 2401188..2114df8 100644
--- a/tools/binman/etype/image_header.py
+++ b/tools/binman/etype/image_header.py
@@ -62,6 +62,7 @@
def _GetHeader(self):
image_pos = self.GetSiblingImagePos('fdtmap')
+ offset = None
if image_pos == False:
self.Raise("'image_header' section must have an 'fdtmap' sibling")
elif image_pos is None:
diff --git a/tools/binman/etype/pre_load.py b/tools/binman/etype/pre_load.py
index 2e4c723..00f1a89 100644
--- a/tools/binman/etype/pre_load.py
+++ b/tools/binman/etype/pre_load.py
@@ -112,6 +112,8 @@
# Compute the signature
if padding_name is None:
padding_name = "pkcs-1.5"
+ padding = None
+ padding_args = None
if padding_name == "pss":
salt_len = key.size_in_bytes() - hash_image.digest_size - 2
padding = pss
diff --git a/tools/binman/etype/ti_board_config.py b/tools/binman/etype/ti_board_config.py
index c10d66e..7c6773a 100644
--- a/tools/binman/etype/ti_board_config.py
+++ b/tools/binman/etype/ti_board_config.py
@@ -119,12 +119,14 @@
array of bytes representing value
"""
size = 0
+ br = bytearray()
if (data_type == '#/definitions/u8'):
size = 1
elif (data_type == '#/definitions/u16'):
size = 2
else:
size = 4
+ br = None
if type(val) == int:
br = val.to_bytes(size, byteorder='little')
return br
diff --git a/tools/binman/etype/x509_cert.py b/tools/binman/etype/x509_cert.py
index 29630d1..25e6808 100644
--- a/tools/binman/etype/x509_cert.py
+++ b/tools/binman/etype/x509_cert.py
@@ -84,6 +84,7 @@
input_fname = tools.get_output_filename('input.%s' % uniq)
config_fname = tools.get_output_filename('config.%s' % uniq)
tools.write_file(input_fname, input_data)
+ stdout = None
if type == 'generic':
stdout = self.openssl.x509_cert(
cert_fname=output_fname,
diff --git a/tools/binman/ftest.py b/tools/binman/ftest.py
index a553ca9..1bc2fca 100644
--- a/tools/binman/ftest.py
+++ b/tools/binman/ftest.py
@@ -303,7 +303,7 @@
def setUp(self):
# Enable this to turn on debugging output
# tout.init(tout.DEBUG)
- command.test_result = None
+ command.TEST_RESULT = None
def tearDown(self):
"""Remove the temporary output directory"""
@@ -345,8 +345,9 @@
Arguments to pass, as a list of strings
kwargs: Arguments to pass to Command.RunPipe()
"""
- result = command.run_pipe([[self._binman_pathname] + list(args)],
- capture=True, capture_stderr=True, raise_on_error=False)
+ all_args = [self._binman_pathname] + list(args)
+ result = command.run_one(*all_args, capture=True, capture_stderr=True,
+ raise_on_error=False)
if result.return_code and kwargs.get('raise_on_error', True):
raise Exception("Error running '%s': %s" % (' '.join(args),
result.stdout + result.stderr))
@@ -762,6 +763,16 @@
return False
return True
+ def _CheckPreload(self, image, key, algo="sha256,rsa2048",
+ padding="pkcs-1.5"):
+ try:
+ tools.run('preload_check_sign', '-k', key, '-a', algo, '-p',
+ padding, '-f', image)
+ except:
+ self.fail('Expected image signed with a pre-load')
+ return False
+ return True
+
def testRun(self):
"""Test a basic run with valid args"""
result = self._RunBinman('-h')
@@ -780,11 +791,11 @@
def testFullHelpInternal(self):
"""Test that the full help is displayed with -H"""
try:
- command.test_result = command.CommandResult()
+ command.TEST_RESULT = command.CommandResult()
result = self._DoBinman('-H')
help_file = os.path.join(self._binman_dir, 'README.rst')
finally:
- command.test_result = None
+ command.TEST_RESULT = None
def testHelp(self):
"""Test that the basic help is displayed with -h"""
@@ -1872,7 +1883,7 @@
def testGbb(self):
"""Test for the Chromium OS Google Binary Block"""
- command.test_result = self._HandleGbbCommand
+ command.TEST_RESULT = self._HandleGbbCommand
entry_args = {
'keydir': 'devkeys',
'bmpblk': 'bmpblk.bin',
@@ -1941,7 +1952,7 @@
def testVblock(self):
"""Test for the Chromium OS Verified Boot Block"""
self._hash_data = False
- command.test_result = self._HandleVblockCommand
+ command.TEST_RESULT = self._HandleVblockCommand
entry_args = {
'keydir': 'devkeys',
}
@@ -1974,7 +1985,7 @@
def testVblockContent(self):
"""Test that the vblock signs the right data"""
self._hash_data = True
- command.test_result = self._HandleVblockCommand
+ command.TEST_RESULT = self._HandleVblockCommand
entry_args = {
'keydir': 'devkeys',
}
@@ -5496,7 +5507,7 @@
def testFitSubentryUsesBintool(self):
"""Test that binman FIT subentries can use bintools"""
- command.test_result = self._HandleGbbCommand
+ command.TEST_RESULT = self._HandleGbbCommand
entry_args = {
'keydir': 'devkeys',
'bmpblk': 'bmpblk.bin',
@@ -5781,9 +5792,14 @@
data = self._DoReadFileDtb(
'230_pre_load.dts', entry_args=entry_args,
extra_indirs=[os.path.join(self._binman_dir, 'test')])[0]
+
+ image_fname = tools.get_output_filename('image.bin')
+ is_signed = self._CheckPreload(image_fname, self.TestFile("dev.key"))
+
self.assertEqual(PRE_LOAD_MAGIC, data[:len(PRE_LOAD_MAGIC)])
self.assertEqual(PRE_LOAD_VERSION, data[4:4 + len(PRE_LOAD_VERSION)])
self.assertEqual(PRE_LOAD_HDR_SIZE, data[8:8 + len(PRE_LOAD_HDR_SIZE)])
+ self.assertEqual(is_signed, True)
def testPreLoadNoKey(self):
"""Test an image with a pre-load heade0r with missing key"""
@@ -6381,6 +6397,7 @@
ename, prop = entry_m.group(1), entry_m.group(3)
entry, entry_name, prop_name = image.LookupEntry(entries,
name, msg)
+ expect_val = None
if prop_name == 'offset':
expect_val = entry.offset
elif prop_name == 'image_pos':
diff --git a/tools/binman/setup.py b/tools/binman/setup.py
index 9a9206e..bec078a 100644
--- a/tools/binman/setup.py
+++ b/tools/binman/setup.py
@@ -1,6 +1,6 @@
# SPDX-License-Identifier: GPL-2.0+
-from distutils.core import setup
+from setuptools import setup
setup(name='binman',
version='1.0',
license='GPL-2.0+',
diff --git a/tools/binman/state.py b/tools/binman/state.py
index 45bae40..6772d36 100644
--- a/tools/binman/state.py
+++ b/tools/binman/state.py
@@ -406,10 +406,13 @@
hash_node = node.FindNode('hash')
if hash_node:
algo = hash_node.props.get('algo').value
+ data = None
if algo == 'sha256':
m = hashlib.sha256()
m.update(get_data_func())
data = m.digest()
+ if data is None:
+ raise ValueError(f"Node '{node.path}': Unknown hash algorithm '{algo}'")
for n in GetUpdateNodes(hash_node):
n.SetData('value', data)
diff --git a/tools/buildman/boards.py b/tools/buildman/boards.py
index e7aa0d8..2fe43c3 100644
--- a/tools/buildman/boards.py
+++ b/tools/buildman/boards.py
@@ -251,9 +251,9 @@
'-undef',
'-x', 'assembler-with-cpp',
defconfig]
- result = command.run_pipe([cmd], capture=True, capture_stderr=True)
+ stdout = command.output(*cmd, capture_stderr=True)
temp = tempfile.NamedTemporaryFile(prefix='buildman-')
- tools.write_file(temp.name, result.stdout, False)
+ tools.write_file(temp.name, stdout, False)
fname = temp.name
tout.info(f'Processing #include to produce {defconfig}')
else:
diff --git a/tools/buildman/builder.py b/tools/buildman/builder.py
index 2568e4e..4bea0a0 100644
--- a/tools/buildman/builder.py
+++ b/tools/buildman/builder.py
@@ -510,7 +510,7 @@
stage: Stage that we are at (mrproper, config, oldconfig, build)
cwd: Directory where make should be run
args: Arguments to pass to make
- kwargs: Arguments to pass to command.run_pipe()
+ kwargs: Arguments to pass to command.run_one()
"""
def check_output(stream, data):
@@ -531,11 +531,12 @@
return False
self._restarting_config = False
- self._terminated = False
+ self._terminated = False
cmd = [self.gnu_make] + list(args)
- result = command.run_pipe([cmd], capture=True, capture_stderr=True,
- cwd=cwd, raise_on_error=False, infile='/dev/null',
- output_func=check_output, **kwargs)
+ result = command.run_one(*cmd, capture=True, capture_stderr=True,
+ cwd=cwd, raise_on_error=False,
+ infile='/dev/null', output_func=check_output,
+ **kwargs)
if self._terminated:
# Try to be helpful
@@ -1095,14 +1096,13 @@
diff = result[name]
if name.startswith('_'):
continue
- if diff != 0:
- color = self.col.RED if diff > 0 else self.col.GREEN
+ colour = self.col.RED if diff > 0 else self.col.GREEN
msg = ' %s %+d' % (name, diff)
if not printed_target:
tprint('%10s %-15s:' % ('', result['_target']),
newline=False)
printed_target = True
- tprint(msg, colour=color, newline=False)
+ tprint(msg, colour=colour, newline=False)
if printed_target:
tprint()
if show_bloat:
@@ -1353,6 +1353,7 @@
for line in lines:
if not line:
continue
+ col = None
if line[0] == '+':
col = self.col.GREEN
elif line[0] == '-':
diff --git a/tools/buildman/builderthread.py b/tools/buildman/builderthread.py
index 78c95a6..b8578d5 100644
--- a/tools/buildman/builderthread.py
+++ b/tools/buildman/builderthread.py
@@ -179,13 +179,12 @@
cwd (str): Working directory to set, or None to leave it alone
*args (list of str): Arguments to pass to 'make'
**kwargs (dict): A list of keyword arguments to pass to
- command.run_pipe()
+ command.run_one()
Returns:
CommandResult object
"""
- return self.builder.do_make(commit, brd, stage, cwd, *args,
- **kwargs)
+ return self.builder.do_make(commit, brd, stage, cwd, *args, **kwargs)
def _build_args(self, brd, out_dir, out_rel_dir, work_dir, commit_upto):
"""Set up arguments to the args list based on the settings
@@ -588,9 +587,10 @@
lines = []
for fname in BASE_ELF_FILENAMES:
cmd = [f'{self.toolchain.cross}nm', '--size-sort', fname]
- nm_result = command.run_pipe([cmd], capture=True,
- capture_stderr=True, cwd=result.out_dir,
- raise_on_error=False, env=env)
+ nm_result = command.run_one(*cmd, capture=True,
+ capture_stderr=True,
+ cwd=result.out_dir,
+ raise_on_error=False, env=env)
if nm_result.stdout:
nm_fname = self.builder.get_func_sizes_file(
result.commit_upto, result.brd.target, fname)
@@ -598,9 +598,10 @@
print(nm_result.stdout, end=' ', file=outf)
cmd = [f'{self.toolchain.cross}objdump', '-h', fname]
- dump_result = command.run_pipe([cmd], capture=True,
- capture_stderr=True, cwd=result.out_dir,
- raise_on_error=False, env=env)
+ dump_result = command.run_one(*cmd, capture=True,
+ capture_stderr=True,
+ cwd=result.out_dir,
+ raise_on_error=False, env=env)
rodata_size = ''
if dump_result.stdout:
objdump = self.builder.get_objdump_file(result.commit_upto,
@@ -613,9 +614,10 @@
rodata_size = fields[2]
cmd = [f'{self.toolchain.cross}size', fname]
- size_result = command.run_pipe([cmd], capture=True,
- capture_stderr=True, cwd=result.out_dir,
- raise_on_error=False, env=env)
+ size_result = command.run_one(*cmd, capture=True,
+ capture_stderr=True,
+ cwd=result.out_dir,
+ raise_on_error=False, env=env)
if size_result.stdout:
lines.append(size_result.stdout.splitlines()[1] + ' ' +
rodata_size)
@@ -624,9 +626,8 @@
cmd = [f'{self.toolchain.cross}objcopy', '-O', 'binary',
'-j', '.rodata.default_environment',
'env/built-in.o', 'uboot.env']
- command.run_pipe([cmd], capture=True,
- capture_stderr=True, cwd=result.out_dir,
- raise_on_error=False, env=env)
+ command.run_one(*cmd, capture=True, capture_stderr=True,
+ cwd=result.out_dir, raise_on_error=False, env=env)
if not work_in_output:
copy_files(result.out_dir, build_dir, '', ['uboot.env'])
diff --git a/tools/buildman/func_test.py b/tools/buildman/func_test.py
index c7c4f50..d779040 100644
--- a/tools/buildman/func_test.py
+++ b/tools/buildman/func_test.py
@@ -187,7 +187,7 @@
self._git_dir = os.path.join(self._base_dir, 'src')
self._buildman_pathname = sys.argv[0]
self._buildman_dir = os.path.dirname(os.path.realpath(sys.argv[0]))
- command.test_result = self._HandleCommand
+ command.TEST_RESULT = self._HandleCommand
bsettings.setup(None)
bsettings.add_file(settings_data)
self.setupToolchains()
@@ -232,8 +232,8 @@
self._toolchains.Add('gcc', test=False)
def _RunBuildman(self, *args):
- return command.run_pipe([[self._buildman_pathname] + list(args)],
- capture=True, capture_stderr=True)
+ all_args = [self._buildman_pathname] + list(args)
+ return command.run_one(*all_args, capture=True, capture_stderr=True)
def _RunControl(self, *args, brds=False, clean_dir=False,
test_thread_exceptions=False, get_builder=True):
@@ -266,7 +266,7 @@
return result
def testFullHelp(self):
- command.test_result = None
+ command.TEST_RESULT = None
result = self._RunBuildman('-H')
help_file = os.path.join(self._buildman_dir, 'README.rst')
# Remove possible extraneous strings
@@ -277,7 +277,7 @@
self.assertEqual(0, result.return_code)
def testHelp(self):
- command.test_result = None
+ command.TEST_RESULT = None
result = self._RunBuildman('-h')
help_file = os.path.join(self._buildman_dir, 'README.rst')
self.assertTrue(len(result.stdout) > 1000)
@@ -286,11 +286,11 @@
def testGitSetup(self):
"""Test gitutils.Setup(), from outside the module itself"""
- command.test_result = command.CommandResult(return_code=1)
+ command.TEST_RESULT = command.CommandResult(return_code=1)
gitutil.setup()
self.assertEqual(gitutil.use_no_decorate, False)
- command.test_result = command.CommandResult(return_code=0)
+ command.TEST_RESULT = command.CommandResult(return_code=0)
gitutil.setup()
self.assertEqual(gitutil.use_no_decorate, True)
@@ -445,7 +445,7 @@
stage: Stage that we are at (mrproper, config, build)
cwd: Directory where make should be run
args: Arguments to pass to make
- kwargs: Arguments to pass to command.run_pipe()
+ kwargs: Arguments to pass to command.run_one()
"""
self._make_calls += 1
out_dir = ''
diff --git a/tools/buildman/test.py b/tools/buildman/test.py
index 385a34e..c5feb74 100644
--- a/tools/buildman/test.py
+++ b/tools/buildman/test.py
@@ -836,6 +836,7 @@
tmpdir = self.base_dir
with (patch('time.time', side_effect=self.get_time),
+ patch('time.perf_counter', side_effect=self.get_time),
patch('time.monotonic', side_effect=self.get_time),
patch('time.sleep', side_effect=self.inc_time),
patch('os.kill', side_effect=self.kill)):
diff --git a/tools/buildman/toolchain.py b/tools/buildman/toolchain.py
index 958f36f..5d051e0 100644
--- a/tools/buildman/toolchain.py
+++ b/tools/buildman/toolchain.py
@@ -100,7 +100,7 @@
else:
self.priority = priority
if test:
- result = command.run_pipe([cmd], capture=True, env=env,
+ result = command.run_one(*cmd, capture=True, env=env,
raise_on_error=False)
self.ok = result.return_code == 0
if verbose:
diff --git a/tools/dtoc/setup.py b/tools/dtoc/setup.py
index 5e092fe..ae9ad04 100644
--- a/tools/dtoc/setup.py
+++ b/tools/dtoc/setup.py
@@ -1,6 +1,6 @@
# SPDX-License-Identifier: GPL-2.0+
-from distutils.core import setup
+from setuptools import setup
setup(name='dtoc',
version='1.0',
license='GPL-2.0+',
diff --git a/tools/image-host.c b/tools/image-host.c
index 05d8c89..a9b8690 100644
--- a/tools/image-host.c
+++ b/tools/image-host.c
@@ -19,6 +19,11 @@
#include <openssl/evp.h>
#endif
+#if CONFIG_IS_ENABLED(IMAGE_PRE_LOAD)
+#include <openssl/rsa.h>
+#include <openssl/err.h>
+#endif
+
/**
* fit_set_hash_value - set hash value in requested has node
* @fit: pointer to the FIT format image header
@@ -364,33 +369,46 @@
return ret;
}
-static int get_random_data(void *data, int size)
+/**
+ * get_random_data() - fill buffer with random data
+ *
+ * There is no common cryptographically safe function in Linux and BSD.
+ * Hence directly access the /dev/urandom PRNG.
+ *
+ * @data: buffer to fill
+ * @size: buffer size
+ */
+static int get_random_data(void *data, size_t size)
{
- unsigned char *tmp = data;
- struct timespec date;
- int i, ret;
-
- if (!tmp) {
- fprintf(stderr, "%s: pointer data is NULL\n", __func__);
- ret = -1;
- goto out;
- }
+ int fd;
+ int ret;
- ret = clock_gettime(CLOCK_MONOTONIC, &date);
- if (ret) {
- fprintf(stderr, "%s: clock_gettime has failed (%s)\n", __func__,
- strerror(errno));
- goto out;
+ fd = open("/dev/urandom", O_RDONLY);
+ if (fd < 0) {
+ perror("Failed to open /dev/urandom");
+ return -1;
}
- srandom(date.tv_nsec);
+ while (size) {
+ ssize_t count;
- for (i = 0; i < size; i++) {
- *tmp = random() & 0xff;
- tmp++;
+ count = read(fd, data, size);
+ if (count < 0) {
+ if (errno == EINTR) {
+ continue;
+ } else {
+ perror("Failed to read from /dev/urandom");
+ ret = -1;
+ goto out;
+ }
+ }
+ data += count;
+ size -= count;
}
+ ret = 0;
+out:
+ close(fd);
- out:
return ret;
}
@@ -1397,3 +1415,139 @@
return ret;
}
#endif
+
+#if CONFIG_IS_ENABLED(IMAGE_PRE_LOAD)
+/**
+ * rsa_verify_openssl() - Verify a signature against some data with openssl API
+ *
+ * Verify a RSA PKCS1.5/PSS signature against an expected hash.
+ *
+ * @info: Specifies the key and algorithms
+ * @region: Pointer to the input data
+ * @region_count: Number of region
+ * @sig: Signature
+ * @sig_len: Number of bytes in the signature
+ * Return: 0 if verified, -ve on error
+ */
+int rsa_verify_openssl(struct image_sign_info *info,
+ const struct image_region region[], int region_count,
+ uint8_t *sig, uint sig_len)
+{
+ EVP_PKEY *pkey = NULL;
+ EVP_PKEY_CTX *ckey = NULL;
+ EVP_MD_CTX *ctx = NULL;
+ int pad;
+ int size;
+ int i;
+ int ret = 0;
+
+ if (!info) {
+ fprintf(stderr, "No info provided\n");
+ ret = -EINVAL;
+ goto out;
+ }
+
+ if (!info->key) {
+ fprintf(stderr, "No key provided\n");
+ ret = -EINVAL;
+ goto out;
+ }
+
+ if (!info->checksum) {
+ fprintf(stderr, "No checksum information\n");
+ ret = -EINVAL;
+ goto out;
+ }
+
+ if (!info->padding) {
+ fprintf(stderr, "No padding information\n");
+ ret = -EINVAL;
+ goto out;
+ }
+
+ if (region_count < 1) {
+ fprintf(stderr, "Invalid value for region_count: %d\n", region_count);
+ ret = -EINVAL;
+ goto out;
+ }
+
+ pkey = (EVP_PKEY *)info->key;
+
+ ckey = EVP_PKEY_CTX_new(pkey, NULL);
+ if (!ckey) {
+ ret = -ENOMEM;
+ fprintf(stderr, "EVK key context setup failed: %s\n",
+ ERR_error_string(ERR_get_error(), NULL));
+ goto out;
+ }
+
+ size = EVP_PKEY_size(pkey);
+ if (size > sig_len) {
+ fprintf(stderr, "Invalid signature size (%d bytes)\n",
+ size);
+ ret = -EINVAL;
+ goto out;
+ }
+
+ ctx = EVP_MD_CTX_new();
+ if (!ctx) {
+ ret = -ENOMEM;
+ fprintf(stderr, "EVP context creation failed: %s\n",
+ ERR_error_string(ERR_get_error(), NULL));
+ goto out;
+ }
+ EVP_MD_CTX_init(ctx);
+
+ if (EVP_DigestVerifyInit(ctx, &ckey,
+ EVP_get_digestbyname(info->checksum->name),
+ NULL, pkey) <= 0) {
+ ret = -EINVAL;
+ fprintf(stderr, "Verifier setup failed: %s\n",
+ ERR_error_string(ERR_get_error(), NULL));
+ goto out;
+ }
+
+ if (!strcmp(info->padding->name, "pkcs-1.5")) {
+ pad = RSA_PKCS1_PADDING;
+ } else if (!strcmp(info->padding->name, "pss")) {
+ pad = RSA_PKCS1_PSS_PADDING;
+ } else {
+ ret = -ENOMSG;
+ fprintf(stderr, "Unsupported padding: %s\n",
+ info->padding->name);
+ goto out;
+ }
+
+ if (EVP_PKEY_CTX_set_rsa_padding(ckey, pad) <= 0) {
+ ret = -EINVAL;
+ fprintf(stderr, "padding setup has failed: %s\n",
+ ERR_error_string(ERR_get_error(), NULL));
+ goto out;
+ }
+
+ for (i=0 ; i < region_count ; ++i) {
+ if (EVP_DigestVerifyUpdate(ctx, region[i].data,
+ region[i].size) <= 0) {
+ ret = -EINVAL;
+ fprintf(stderr, "Hashing data failed: %s\n",
+ ERR_error_string(ERR_get_error(), NULL));
+ goto out;
+ }
+ }
+
+ if (EVP_DigestVerifyFinal(ctx, sig, sig_len) <= 0) {
+ ret = -EINVAL;
+ fprintf(stderr, "Verifying digest failed: %s\n",
+ ERR_error_string(ERR_get_error(), NULL));
+ goto out;
+ }
+out:
+ if (ctx)
+ EVP_MD_CTX_free(ctx);
+
+ if (ret)
+ fprintf(stderr, "Failed to verify signature\n");
+
+ return ret;
+}
+#endif
diff --git a/tools/imx8image.c b/tools/imx8image.c
index 15510d3..0135b19 100644
--- a/tools/imx8image.c
+++ b/tools/imx8image.c
@@ -290,6 +290,7 @@
}
}
+ free(line);
fclose(fd);
return 0;
}
diff --git a/tools/imx8mimage.c b/tools/imx8mimage.c
index d60d293..0f24ba7 100644
--- a/tools/imx8mimage.c
+++ b/tools/imx8mimage.c
@@ -206,6 +206,7 @@
}
}
+ free(line);
fclose(fd);
return 0;
}
diff --git a/tools/imximage.c b/tools/imximage.c
index 467d9f2..55231ca 100644
--- a/tools/imximage.c
+++ b/tools/imximage.c
@@ -783,6 +783,7 @@
}
(*set_dcd_rst)(imxhdr, dcd_len, name, lineno);
+ free(line);
fclose(fd);
/* Exit if there is no BOOT_FROM field specifying the flash_offset */
diff --git a/tools/kwbimage.c b/tools/kwbimage.c
index d1cbced..3dcf5ba 100644
--- a/tools/kwbimage.c
+++ b/tools/kwbimage.c
@@ -1653,6 +1653,12 @@
char *unknown_msg = "Ignoring unknown line '%s'\n";
keyword = strtok_r(line, delimiters, &saveptr);
+
+ if (!keyword) {
+ fprintf(stderr, "Parameter missing in line '%s'\n", line);
+ return -1;
+ }
+
keyword_id = recognize_keyword(keyword);
if (!keyword_id) {
diff --git a/tools/microcode-tool.py b/tools/microcode-tool.py
index 24c02c4..b726794 100755
--- a/tools/microcode-tool.py
+++ b/tools/microcode-tool.py
@@ -279,6 +279,9 @@
if (not not options.mcfile) != (not not options.mcfile):
parser.error("You must specify either header files or a microcode file, not both")
+ date = None
+ microcodes = None
+ license_text = None
if options.headerfile:
date, license_text, microcodes = ParseHeaderFiles(options.headerfile)
elif options.mcfile:
diff --git a/tools/mkimage.h b/tools/mkimage.h
index 15741f2..5d6bcc9 100644
--- a/tools/mkimage.h
+++ b/tools/mkimage.h
@@ -37,6 +37,10 @@
return (void *)(uintptr_t)paddr;
}
+static inline void unmap_sysmem(const void *vaddr)
+{
+}
+
static inline ulong map_to_sysmem(const void *ptr)
{
return (ulong)(uintptr_t)ptr;
diff --git a/tools/patman/patchstream.py b/tools/patman/patchstream.py
index 08795c4..490d382 100644
--- a/tools/patman/patchstream.py
+++ b/tools/patman/patchstream.py
@@ -711,7 +711,7 @@
"""
params = gitutil.log_cmd(commit_range, reverse=True, count=count,
git_dir=git_dir)
- return command.run_pipe([params], capture=True).stdout
+ return command.run_one(*params, capture=True).stdout
def get_metadata_for_list(commit_range, git_dir=None, count=None,
series=None, allow_overwrite=False):
diff --git a/tools/patman/test_checkpatch.py b/tools/patman/test_checkpatch.py
index 11d003b..3bf16fe 100644
--- a/tools/patman/test_checkpatch.py
+++ b/tools/patman/test_checkpatch.py
@@ -530,4 +530,3 @@
if __name__ == "__main__":
unittest.main()
- gitutil.RunTests()
diff --git a/tools/preload_check_sign.c b/tools/preload_check_sign.c
new file mode 100644
index 0000000..ebead45
--- /dev/null
+++ b/tools/preload_check_sign.c
@@ -0,0 +1,160 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Check a file including a preload header including a signature
+ *
+ * Copyright (c) 2025 Paul HENRYS <paul.henrys_ext@softathome.com>
+ *
+ * Binman makes it possible to generate a preload header signing part or the
+ * complete file. The tool preload_check_sign allows to verify and authenticate
+ * a file starting with a preload header.
+ */
+#include <stdio.h>
+#include <unistd.h>
+#include <openssl/pem.h>
+#include <openssl/evp.h>
+#include <openssl/err.h>
+#include <image.h>
+
+extern void image_pre_load_sig_set_info(struct image_sig_info *info);
+extern int image_pre_load_sig(ulong addr);
+
+static void usage(char *cmdname)
+{
+ fprintf(stderr, "Usage: %s -f file -k PEM key file\n"
+ " -f ==> set file which should be checked\n"
+ " -k ==> PEM key file\n"
+ " -a ==> algo (default: sha256,rsa2048)\n"
+ " -p ==> padding (default: pkcs-1.5)\n"
+ " -h ==> help\n",
+ cmdname);
+ exit(EXIT_FAILURE);
+}
+
+int main(int argc, char **argv)
+{
+ int ret = 0;
+ char cmdname[256];
+ char *file = NULL;
+ char *keyfile = NULL;
+ int c;
+ FILE *fp = NULL;
+ FILE *fp_key = NULL;
+ size_t bytes;
+ long filesize;
+ void *buffer = NULL;
+ EVP_PKEY *pkey = NULL;
+ char *algo = "sha256,rsa2048";
+ char *padding = "pkcs-1.5";
+ struct image_sig_info info = {0};
+
+ strncpy(cmdname, *argv, sizeof(cmdname) - 1);
+ cmdname[sizeof(cmdname) - 1] = '\0';
+ while ((c = getopt(argc, argv, "f:k:a:p:h")) != -1)
+ switch (c) {
+ case 'f':
+ file = optarg;
+ break;
+ case 'k':
+ keyfile = optarg;
+ break;
+ case 'a':
+ algo = optarg;
+ break;
+ case 'p':
+ padding = optarg;
+ break;
+ default:
+ usage(cmdname);
+ break;
+ }
+
+ if (!file) {
+ fprintf(stderr, "%s: Missing file\n", *argv);
+ usage(*argv);
+ }
+
+ if (!keyfile) {
+ fprintf(stderr, "%s: Missing key file\n", *argv);
+ usage(*argv);
+ }
+
+ fp = fopen(file, "r");
+ if (!fp) {
+ fprintf(stderr, "Error opening file: %s\n", file);
+ ret = EXIT_FAILURE;
+ goto out;
+ }
+
+ fseek(fp, 0, SEEK_END);
+ filesize = ftell(fp);
+ rewind(fp);
+
+ buffer = malloc(filesize);
+ if (!buffer) {
+ fprintf(stderr, "Memory allocation failed");
+ ret = EXIT_FAILURE;
+ goto out;
+ }
+
+ bytes = fread(buffer, 1, filesize, fp);
+ if (bytes != filesize) {
+ fprintf(stderr, "Error reading file\n");
+ ret = EXIT_FAILURE;
+ goto out;
+ }
+
+ fp_key = fopen(keyfile, "r");
+ if (!fp_key) {
+ fprintf(stderr, "Error opening file: %s\n", keyfile);
+ ret = EXIT_FAILURE;
+ goto out;
+ }
+
+ /* Attempt to read the private key */
+ pkey = PEM_read_PrivateKey(fp_key, NULL, NULL, NULL);
+ if (!pkey) {
+ /* If private key reading fails, try reading as a public key */
+ fseek(fp_key, 0, SEEK_SET);
+ pkey = PEM_read_PUBKEY(fp_key, NULL, NULL, NULL);
+ }
+ if (!pkey) {
+ fprintf(stderr, "Unable to retrieve the public key: %s\n",
+ ERR_error_string(ERR_get_error(), NULL));
+ ret = EXIT_FAILURE;
+ goto out;
+ }
+
+ info.algo_name = algo;
+ info.padding_name = padding;
+ info.key = (uint8_t *)pkey;
+ info.mandatory = 1;
+ info.sig_size = EVP_PKEY_size(pkey);
+ if (info.sig_size < 0) {
+ fprintf(stderr, "Fail to retrieve the signature size: %s\n",
+ ERR_error_string(ERR_get_error(), NULL));
+ ret = EXIT_FAILURE;
+ goto out;
+ }
+
+ /* Compute signature information */
+ info.sig_info.name = info.algo_name;
+ info.sig_info.padding = image_get_padding_algo(info.padding_name);
+ info.sig_info.checksum = image_get_checksum_algo(info.sig_info.name);
+ info.sig_info.crypto = image_get_crypto_algo(info.sig_info.name);
+ info.sig_info.key = info.key;
+ info.sig_info.keylen = info.key_len;
+
+ /* Check the signature */
+ image_pre_load_sig_set_info(&info);
+ ret = image_pre_load_sig((ulong)buffer);
+out:
+ if (fp)
+ fclose(fp);
+ if (fp_key)
+ fclose(fp_key);
+ if (info.key)
+ EVP_PKEY_free(pkey);
+ free(buffer);
+
+ exit(ret);
+}
diff --git a/tools/rmboard.py b/tools/rmboard.py
index 0c56b14..594fd89 100755
--- a/tools/rmboard.py
+++ b/tools/rmboard.py
@@ -43,18 +43,16 @@
Args:
path: Path to search for and remove
"""
- cmd = ['git', 'grep', path]
- stdout = command.run_pipe([cmd], capture=True, raise_on_error=False).stdout
+ stdout = command.output('git', 'grep', path, raise_on_error=False)
if not stdout:
return
fname = stdout.split(':')[0]
print("Fixing up '%s' to remove reference to '%s'" % (fname, path))
- cmd = ['sed', '-i', '\|%s|d' % path, fname]
- stdout = command.run_pipe([cmd], capture=True).stdout
+ stdout = command.run_one('sed', '-i', rf'\|{path}|d', fname,
+ capture=True).stdout
- cmd = ['git', 'add', fname]
- stdout = command.run_pipe([cmd], capture=True).stdout
+ stdout = command.output('git', 'add', fname)
def rm_board(board):
"""Create a commit which removes a single board
@@ -68,8 +66,7 @@
"""
# Find all MAINTAINERS and Kconfig files which mention the board
- cmd = ['git', 'grep', '-l', board]
- stdout = command.run_pipe([cmd], capture=True).stdout
+ stdout = command.output('git', 'grep', '-l', board)
maintain = []
kconfig = []
for line in stdout.splitlines():
@@ -109,16 +106,14 @@
# Search for Kconfig files in the resulting list. Remove any 'source' lines
# which reference Kconfig files we want to remove
for path in real:
- cmd = ['find', path]
- stdout = (command.run_pipe([cmd], capture=True, raise_on_error=False).
- stdout)
+ stdout = command.output('find', path, raise_on_error=False)
for fname in stdout.splitlines():
if fname.endswith('Kconfig'):
rm_kconfig_include(fname)
# Remove unwanted files
cmd = ['git', 'rm', '-r'] + real
- stdout = command.run_pipe([cmd], capture=True).stdout
+ stdout = command.output(*cmd, capture=True)
## Change the messages as needed
msg = '''arm: Remove %s board
@@ -131,13 +126,11 @@
msg += 'Patch-cc: %s\n' % name
# Create the commit
- cmd = ['git', 'commit', '-s', '-m', msg]
- stdout = command.run_pipe([cmd], capture=True).stdout
+ stdout = command.output('git', 'commit', '-s', '-m', msg)
# Check if the board is mentioned anywhere else. The user will need to deal
# with this
- cmd = ['git', 'grep', '-il', board]
- print(command.run_pipe([cmd], capture=True, raise_on_error=False).stdout)
+ print(command.output('git', 'grep', '-il', board, raise_on_error=False))
print(' '.join(cmd))
for board in sys.argv[1:]:
diff --git a/tools/u_boot_pylib/command.py b/tools/u_boot_pylib/command.py
index bbe95d8..0e24735 100644
--- a/tools/u_boot_pylib/command.py
+++ b/tools/u_boot_pylib/command.py
@@ -1,21 +1,44 @@
# SPDX-License-Identifier: GPL-2.0+
-# Copyright (c) 2011 The Chromium OS Authors.
-#
+"""
+Shell command ease-ups for Python
-import os
+Copyright (c) 2011 The Chromium OS Authors.
+"""
+
+import subprocess
from u_boot_pylib import cros_subprocess
+# This permits interception of RunPipe for test purposes. If it is set to
+# a function, then that function is called with the pipe list being
+# executed. Otherwise, it is assumed to be a CommandResult object, and is
+# returned as the result for every run_pipe() call.
+# When this value is None, commands are executed as normal.
+TEST_RESULT = None
+
+
+class CommandExc(Exception):
+ """Reports an exception to the caller"""
+ def __init__(self, msg, result):
+ """Set up a new exception object
+
-"""Shell command ease-ups for Python."""
+ Args:
+ result (CommandResult): Execution result so far
+ """
+ super().__init__(msg)
+ self.result = result
+
class CommandResult:
"""A class which captures the result of executing a command.
Members:
- stdout: stdout obtained from command, as a string
- stderr: stderr obtained from command, as a string
- return_code: Return code from command
- exception: Exception received, or None if all ok
+ stdout (bytes): stdout obtained from command, as a string
+ stderr (bytes): stderr obtained from command, as a string
+ combined (bytes): stdout and stderr interleaved
+ return_code (int): Return code from command
+ exception (Exception): Exception received, or None if all ok
+ output (str or None): Returns output as a single line if requested
"""
def __init__(self, stdout='', stderr='', combined='', return_code=0,
exception=None):
@@ -24,58 +47,64 @@
self.combined = combined
self.return_code = return_code
self.exception = exception
+ self.output = None
def to_output(self, binary):
+ """Converts binary output to its final form
+
+ Args:
+ binary (bool): True to report binary output, False to use strings
+ Returns:
+ self
+ """
if not binary:
self.stdout = self.stdout.decode('utf-8')
self.stderr = self.stderr.decode('utf-8')
self.combined = self.combined.decode('utf-8')
return self
-
-# This permits interception of RunPipe for test purposes. If it is set to
-# a function, then that function is called with the pipe list being
-# executed. Otherwise, it is assumed to be a CommandResult object, and is
-# returned as the result for every run_pipe() call.
-# When this value is None, commands are executed as normal.
-test_result = None
-def run_pipe(pipe_list, infile=None, outfile=None,
- capture=False, capture_stderr=False, oneline=False,
- raise_on_error=True, cwd=None, binary=False,
- output_func=None, **kwargs):
+def run_pipe(pipe_list, infile=None, outfile=None, capture=False,
+ capture_stderr=False, oneline=False, raise_on_error=True, cwd=None,
+ binary=False, output_func=None, **kwargs):
"""
Perform a command pipeline, with optional input/output filenames.
Args:
- pipe_list: List of command lines to execute. Each command line is
- piped into the next, and is itself a list of strings. For
+ pipe_list (list of list): List of command lines to execute. Each command
+ line is piped into the next, and is itself a list of strings. For
example [ ['ls', '.git'] ['wc'] ] will pipe the output of
'ls .git' into 'wc'.
- infile: File to provide stdin to the pipeline
- outfile: File to store stdout
- capture: True to capture output
- capture_stderr: True to capture stderr
- oneline: True to strip newline chars from output
- output_func: Output function to call with each output fragment
- (if it returns True the function terminates)
- kwargs: Additional keyword arguments to cros_subprocess.Popen()
+ infile (str): File to provide stdin to the pipeline
+ outfile (str): File to store stdout
+ capture (bool): True to capture output
+ capture_stderr (bool): True to capture stderr
+ oneline (bool): True to strip newline chars from output
+ raise_on_error (bool): True to raise on an error, False to return it in
+ the CommandResult
+ cwd (str or None): Directory to run the command in
+ binary (bool): True to report binary output, False to use strings
+ output_func (function): Output function to call with each output
+ fragment (if it returns True the function terminates)
+ **kwargs: Additional keyword arguments to cros_subprocess.Popen()
Returns:
CommandResult object
+ Raises:
+ CommandExc if an exception happens
"""
- if test_result:
- if hasattr(test_result, '__call__'):
+ if TEST_RESULT:
+ if hasattr(TEST_RESULT, '__call__'):
# pylint: disable=E1102
- result = test_result(pipe_list=pipe_list)
+ result = TEST_RESULT(pipe_list=pipe_list)
if result:
return result
else:
- return test_result
+ return TEST_RESULT
# No result: fall through to normal processing
result = CommandResult(b'', b'', b'')
last_pipe = None
pipeline = list(pipe_list)
- user_pipestr = '|'.join([' '.join(pipe) for pipe in pipe_list])
+ user_pipestr = '|'.join([' '.join(pipe) for pipe in pipe_list])
kwargs['stdout'] = None
kwargs['stderr'] = None
while pipeline:
@@ -96,7 +125,8 @@
except Exception as err:
result.exception = err
if raise_on_error:
- raise Exception("Error running '%s': %s" % (user_pipestr, str))
+ raise CommandExc(f"Error running '{user_pipestr}': {err}",
+ result) from err
result.return_code = 255
return result.to_output(binary)
@@ -107,31 +137,84 @@
result.output = result.stdout.rstrip(b'\r\n')
result.return_code = last_pipe.wait()
if raise_on_error and result.return_code:
- raise Exception("Error running '%s'" % user_pipestr)
+ raise CommandExc(f"Error running '{user_pipestr}'", result)
return result.to_output(binary)
+
def output(*cmd, **kwargs):
+ """Run a command and return its output
+
+ Args:
+ *cmd (list of str): Command to run
+ **kwargs (dict of args): Extra arguments to pass in
+
+ Returns:
+ str: command output
+ """
kwargs['raise_on_error'] = kwargs.get('raise_on_error', True)
return run_pipe([cmd], capture=True, **kwargs).stdout
+
def output_one_line(*cmd, **kwargs):
"""Run a command and output it as a single-line string
- The command us expected to produce a single line of output
+ The command is expected to produce a single line of output
+
+ Args:
+ *cmd (list of str): Command to run
+ **kwargs (dict of args): Extra arguments to pass in
Returns:
- String containing output of command
+ str: output of command with all newlines removed
"""
raise_on_error = kwargs.pop('raise_on_error', True)
result = run_pipe([cmd], capture=True, oneline=True,
- raise_on_error=raise_on_error, **kwargs).stdout.strip()
+ raise_on_error=raise_on_error, **kwargs).stdout.strip()
return result
+
def run(*cmd, **kwargs):
+ """Run a command
+
+ Note that you must add 'capture' to kwargs to obtain non-empty output
+
+ Args:
+ *cmd (list of str): Command to run
+ **kwargs (dict of args): Extra arguments to pass in
+
+ Returns:
+ str: output of command
+ """
return run_pipe([cmd], **kwargs).stdout
+
+def run_one(*cmd, **kwargs):
+ """Run a single command
+
+ Note that you must add 'capture' to kwargs to obtain non-empty output
+
+ Args:
+ *cmd (list of str): Command to run
+ **kwargs (dict of args): Extra arguments to pass in
+
+ Returns:
+ CommandResult: output of command
+ """
+ return run_pipe([cmd], **kwargs)
+
+
def run_list(cmd):
+ """Run a command and return its output
+
+ Args:
+ cmd (list of str): Command to run
+
+ Returns:
+ str: output of command
+ """
return run_pipe([cmd], capture=True).stdout
+
def stop_all():
+ """Stop all subprocesses initiated with cros_subprocess"""
cros_subprocess.stay_alive = False
diff --git a/tools/u_boot_pylib/gitutil.py b/tools/u_boot_pylib/gitutil.py
index 10ea5ff..6d6a7ee 100644
--- a/tools/u_boot_pylib/gitutil.py
+++ b/tools/u_boot_pylib/gitutil.py
@@ -65,9 +65,9 @@
rev_range = '%s..%s' % (us, branch)
else:
rev_range = '@{upstream}..'
- pipe = [log_cmd(rev_range, oneline=True)]
- result = command.run_pipe(pipe, capture=True, capture_stderr=True,
- oneline=True, raise_on_error=False)
+ cmd = log_cmd(rev_range, oneline=True)
+ result = command.run_one(*cmd, capture=True, capture_stderr=True,
+ oneline=True, raise_on_error=False)
if result.return_code:
raise ValueError('Failed to determine upstream: %s' %
result.stderr.strip())
@@ -84,8 +84,7 @@
Return:
Name of revision, if any, else None
"""
- pipe = ['git', 'name-rev', commit_hash]
- stdout = command.run_pipe([pipe], capture=True, oneline=True).stdout
+ stdout = command.output_one_line('git', 'name-rev', commit_hash)
# We expect a commit, a space, then a revision name
name = stdout.split(' ')[1].strip()
@@ -108,9 +107,9 @@
Name of upstream branch (e.g. 'upstream/master') or None if none
Warning/error message, or None if none
"""
- pipe = [log_cmd(branch, git_dir=git_dir, oneline=True, count=100)]
- result = command.run_pipe(pipe, capture=True, capture_stderr=True,
- raise_on_error=False)
+ cmd = log_cmd(branch, git_dir=git_dir, oneline=True, count=100)
+ result = command.run_one(*cmd, capture=True, capture_stderr=True,
+ raise_on_error=False)
if result.return_code:
return None, "Branch '%s' not found" % branch
for line in result.stdout.splitlines()[1:]:
@@ -140,7 +139,7 @@
'branch.%s.remote' % branch)
merge = command.output_one_line('git', '--git-dir', git_dir, 'config',
'branch.%s.merge' % branch)
- except Exception:
+ except command.CommandExc:
upstream, msg = guess_upstream(git_dir, branch)
return upstream, msg
@@ -183,9 +182,9 @@
Number of patches that exist in the supplied range or None if none
were found
"""
- pipe = [log_cmd(range_expr, git_dir=git_dir, oneline=True)]
- result = command.run_pipe(pipe, capture=True, capture_stderr=True,
- raise_on_error=False)
+ cmd = log_cmd(range_expr, git_dir=git_dir, oneline=True)
+ result = command.run_one(*cmd, capture=True, capture_stderr=True,
+ raise_on_error=False)
if result.return_code:
return None, "Range '%s' not found or is invalid" % range_expr
patch_count = len(result.stdout.splitlines())
@@ -250,9 +249,8 @@
Args:
commit_hash: Commit hash to check out
"""
- pipe = ['git', 'clone', git_dir, '.']
- result = command.run_pipe([pipe], capture=True, cwd=output_dir,
- capture_stderr=True)
+ result = command.run_one('git', 'clone', git_dir, '.', capture=True,
+ cwd=output_dir, capture_stderr=True)
if result.return_code != 0:
raise OSError('git clone: %s' % result.stderr)
@@ -263,13 +261,13 @@
Args:
commit_hash: Commit hash to check out
"""
- pipe = ['git']
+ cmd = ['git']
if git_dir:
- pipe.extend(['--git-dir', git_dir])
+ cmd.extend(['--git-dir', git_dir])
if work_tree:
- pipe.extend(['--work-tree', work_tree])
- pipe.append('fetch')
- result = command.run_pipe([pipe], capture=True, capture_stderr=True)
+ cmd.extend(['--work-tree', work_tree])
+ cmd.append('fetch')
+ result = command.run_one(*cmd, capture=True, capture_stderr=True)
if result.return_code != 0:
raise OSError('git fetch: %s' % result.stderr)
@@ -283,9 +281,9 @@
Returns:
True if git-worktree commands will work, False otherwise.
"""
- pipe = ['git', '--git-dir', git_dir, 'worktree', 'list']
- result = command.run_pipe([pipe], capture=True, capture_stderr=True,
- raise_on_error=False)
+ result = command.run_one('git', '--git-dir', git_dir, 'worktree', 'list',
+ capture=True, capture_stderr=True,
+ raise_on_error=False)
return result.return_code == 0
@@ -298,11 +296,11 @@
commit_hash: Commit hash to checkout
"""
# We need to pass --detach to avoid creating a new branch
- pipe = ['git', '--git-dir', git_dir, 'worktree', 'add', '.', '--detach']
+ cmd = ['git', '--git-dir', git_dir, 'worktree', 'add', '.', '--detach']
if commit_hash:
- pipe.append(commit_hash)
- result = command.run_pipe([pipe], capture=True, cwd=output_dir,
- capture_stderr=True)
+ cmd.append(commit_hash)
+ result = command.run_one(*cmd, capture=True, cwd=output_dir,
+ capture_stderr=True)
if result.return_code != 0:
raise OSError('git worktree add: %s' % result.stderr)
@@ -313,8 +311,8 @@
Args:
git_dir: The repository whose deleted worktrees should be pruned
"""
- pipe = ['git', '--git-dir', git_dir, 'worktree', 'prune']
- result = command.run_pipe([pipe], capture=True, capture_stderr=True)
+ result = command.run_one('git', '--git-dir', git_dir, 'worktree', 'prune',
+ capture=True, capture_stderr=True)
if result.return_code != 0:
raise OSError('git worktree prune: %s' % result.stderr)
@@ -687,7 +685,7 @@
if alias_fname:
settings.ReadGitAliases(alias_fname)
cmd = log_cmd(None, count=0)
- use_no_decorate = (command.run_pipe([cmd], raise_on_error=False)
+ use_no_decorate = (command.run_one(*cmd, raise_on_error=False)
.return_code == 0)
diff --git a/tools/u_boot_pylib/tools.py b/tools/u_boot_pylib/tools.py
index 0499a75..1afd289 100644
--- a/tools/u_boot_pylib/tools.py
+++ b/tools/u_boot_pylib/tools.py
@@ -376,7 +376,7 @@
args = tuple(extra_args) + args
name = os.path.expanduser(name) # Expand paths containing ~
all_args = (name,) + args
- result = command.run_pipe([all_args], capture=True, capture_stderr=True,
+ result = command.run_one(*all_args, capture=True, capture_stderr=True,
env=env, raise_on_error=False, binary=binary)
if result.return_code:
if raise_on_error: