powerpc: Fix 0 vs. r0 confusion in X/D-form instructions
Instructions such as dcbi are in the X-form; they have RA and RB fields
and the effective address (EA) is computed as (RA|0)+(RB). In words,
this means that if RA is zero, the left-hand side of the addition is
zero, otherwise the corresponding GPR is used. r0 can never be used on
the left-hand side of a X-form instruction.
For D-form instructions such as addis, the Power ISA illustrates this in
the instruction pseudo-code:
if RA = 0 then RT <- EXTS(SI || 0x0000)
else RT <- (RA) + EXIS(SI || 0x0000)
In all of these cases, RA=0 indicates the value zero, not register r0.
I verified with gazerbeam_defconfig (MPC83xx) and qemu-ppce500_defconfig
(MPC85xx) that this patch results in the same machine code.
Signed-off-by: J. Neuschäfer <j.ne@posteo.net>
diff --git a/arch/powerpc/cpu/mpc85xx/start.S b/arch/powerpc/cpu/mpc85xx/start.S
index 89bce5b..5234e42 100644
--- a/arch/powerpc/cpu/mpc85xx/start.S
+++ b/arch/powerpc/cpu/mpc85xx/start.S
@@ -1203,12 +1203,12 @@
mtctr r2
li r0,0
1:
- dcbz r0,r3
+ dcbz 0,r3
#ifdef CONFIG_E6500 /* Lock/unlock L2 cache long with L1 */
- dcbtls 2, r0, r3
- dcbtls 0, r0, r3
+ dcbtls 2, 0, r3
+ dcbtls 0, 0, r3
#else
- dcbtls 0, r0, r3
+ dcbtls 0, 0, r3
#endif
addi r3,r3,CONFIG_SYS_CACHELINE_SIZE
bdnz 1b
@@ -1514,7 +1514,7 @@
/*------------------------------------------------------------------------------- */
.globl out16r
out16r:
- sthbrx r4,r0,r3
+ sthbrx r4,0,r3
sync
blr
@@ -1534,7 +1534,7 @@
/*------------------------------------------------------------------------------- */
.globl out32r
out32r:
- stwbrx r4,r0,r3
+ stwbrx r4,0,r3
sync
blr
@@ -1553,7 +1553,7 @@
/*------------------------------------------------------------------------------- */
.globl in16r
in16r:
- lhbrx r3,r0,r3
+ lhbrx r3,0,r3
blr
/*------------------------------------------------------------------------------- */
@@ -1571,7 +1571,7 @@
/*------------------------------------------------------------------------------- */
.globl in32r
in32r:
- lwbrx r3,r0,r3
+ lwbrx r3,0,r3
blr
#endif /* !MINIMAL_SPL */
@@ -1832,12 +1832,12 @@
andi. r4,r4,0x1ff
slwi r4,r4,(10 - 1 - L1_CACHE_SHIFT)
mtctr r4
-1: dcbi r0,r3
+1: dcbi 0,r3
#ifdef CONFIG_E6500 /* lock/unlock L2 cache long with L1 */
- dcblc 2, r0, r3
- dcblc 0, r0, r3
+ dcblc 2, 0, r3
+ dcblc 0, 0, r3
#else
- dcblc r0,r3
+ dcblc 0,r3
#endif
addi r3,r3,CONFIG_SYS_CACHELINE_SIZE
bdnz 1b