commit a35cb4c504a6701d7226fc4bca96ab03b12ce22f
author Simon Guinot <simon.guinot@sequanux.org> Mon Nov 21 19:25:47 2011 +0530
committer Albert ARIBAUD <albert.u.boot@aribaud.net> Tue Dec 06 23:59:30 2011 +0100
tree 72bd114929a758873cdeaf075db880e9d5018ee0
parent 72198a3c46268d74f925bb470ba0cabebc607281

ARM: remove duplicated code for LaCie boards

This patch groups together all the common functions for LaCie boards:
Ethernet PHY and MAC address initializations.

Moreover the configurations for LaCie Kirkwood boards are merged into
a single file: include/configs/lacie_kw.h

Signed-off-by: Simon Guinot <simon.guinot@sequanux.org>

board/LaCie/edminiv2/edminiv2.c

diff --git a/board/LaCie/edminiv2/edminiv2.c b/board/LaCie/edminiv2/edminiv2.c
index ee26893..c1a01bc 100644
--- a/board/LaCie/edminiv2/edminiv2.c
+++ b/board/LaCie/edminiv2/edminiv2.c
@@ -27,7 +27,6 @@
 #include <common.h>
 #include <miiphy.h>
 #include <asm/arch/orion5x.h>
-#include "edminiv2.h"
 
 DECLARE_GLOBAL_DATA_PTR;
 
@@ -96,33 +95,6 @@
 /* Configure and enable MV88E1116 PHY */
 void reset_phy(void)
 {
-	u16 reg;
-	u16 devadr;
-	char *name = "egiga0";
-
-	if (miiphy_set_current_dev(name))
-		return;
-
-	/* command to read PHY dev address */
-	if (miiphy_read(name, 0xEE, 0xEE, (u16 *) &devadr)) {
-		printf("Err..%s could not read PHY dev address\n",
-			__func__);
-		return;
-	}
-
-	/*
-	 * Enable RGMII delay on Tx and Rx for CPU port
-	 * Ref: sec 4.7.2 of chip datasheet
-	 */
-	miiphy_write(name, devadr, MV88E1116_PGADR_REG, 2);
-	miiphy_read(name, devadr, MV88E1116_MAC_CTRL_REG, &reg);
-	reg |= (MV88E1116_RGMII_RXTM_CTRL | MV88E1116_RGMII_TXTM_CTRL);
-	miiphy_write(name, devadr, MV88E1116_MAC_CTRL_REG, reg);
-	miiphy_write(name, devadr, MV88E1116_PGADR_REG, 0);
-
-	/* reset the phy */
-	miiphy_reset(name, devadr);
-
-	printf("88E1116 Initialized on %s\n", name);
+	mv_phy_88e1116_init("egiga0");
 }
 #endif /* CONFIG_RESET_PHY_R */