Merge tag 'u-boot-stm32-20201209' of https://gitlab.denx.de/u-boot/custodians/u-boot-stm
- Manage CONFIG_ENV_EXT4_DEVICE_AND_PART in stm32mp1 board
- Update ARM STI and ARM STM STM32MP Arch maintainers emails
- Enable internal pull-ups for SDMMC1 on DHCOM SoM
diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile
index a669835..02d04f5 100644
--- a/arch/arm/dts/Makefile
+++ b/arch/arm/dts/Makefile
@@ -642,14 +642,8 @@
ifneq ($(CONFIG_MX6DL)$(CONFIG_MX6QDL)$(CONFIG_MX6S),)
dtb-y += \
- imx6dl-aristainetos2_4.dtb \
- imx6dl-aristainetos2_7.dtb \
- imx6dl-aristainetos2b_4.dtb \
- imx6dl-aristainetos2b_7.dtb \
- imx6dl-aristainetos2b_csl_4.dtb \
- imx6dl-aristainetos2b_csl_7.dtb \
- imx6dl-aristainetos2c_4.dtb \
imx6dl-aristainetos2c_7.dtb \
+ imx6dl-aristainetos2c_cslb_7.dtb \
imx6dl-brppt2.dtb \
imx6dl-cubox-i.dtb \
imx6dl-cubox-i-emmc-som-v15.dtb \
@@ -767,6 +761,7 @@
imx8qm-rom7720-a1.dtb \
fsl-imx8qxp-ai_ml.dtb \
fsl-imx8qxp-colibri.dtb \
+ fsl-imx8qxp-apalis.dtb \
fsl-imx8qxp-mek.dtb \
imx8-deneb.dtb \
imx8-giedi.dtb
diff --git a/arch/arm/dts/fsl-imx8qxp-apalis-u-boot.dtsi b/arch/arm/dts/fsl-imx8qxp-apalis-u-boot.dtsi
new file mode 100644
index 0000000..e41911a
--- /dev/null
+++ b/arch/arm/dts/fsl-imx8qxp-apalis-u-boot.dtsi
@@ -0,0 +1,139 @@
+// SPDX-License-Identifier: GPL-2.0+ OR MIT
+/*
+ * Copyright 2020 Toradex
+ */
+
+&{/imx8qx-pm} {
+
+ u-boot,dm-pre-proper;
+};
+
+&mu {
+ u-boot,dm-pre-proper;
+};
+
+&clk {
+ u-boot,dm-pre-proper;
+};
+
+&iomuxc {
+ u-boot,dm-pre-proper;
+};
+
+&pd_lsio {
+ u-boot,dm-pre-proper;
+};
+
+&pd_lsio_gpio0 {
+ u-boot,dm-pre-proper;
+};
+
+&pd_lsio_gpio1 {
+ u-boot,dm-pre-proper;
+};
+
+&pd_lsio_gpio2 {
+ u-boot,dm-pre-proper;
+};
+
+&pd_lsio_gpio3 {
+ u-boot,dm-pre-proper;
+};
+
+&pd_lsio_gpio4 {
+ u-boot,dm-pre-proper;
+};
+
+&pd_lsio_gpio5 {
+ u-boot,dm-pre-proper;
+};
+
+&pd_lsio_gpio6 {
+ u-boot,dm-pre-proper;
+};
+
+&pd_lsio_gpio7 {
+ u-boot,dm-pre-proper;
+};
+
+&pd_dma {
+ u-boot,dm-pre-proper;
+};
+
+&pd_dma_lpuart0 {
+ u-boot,dm-pre-proper;
+};
+
+&pd_dma_lpuart3 {
+ u-boot,dm-pre-proper;
+};
+
+&pd_conn {
+ u-boot,dm-pre-proper;
+};
+
+&pd_conn_sdch0 {
+ u-boot,dm-pre-proper;
+};
+
+&pd_conn_sdch1 {
+ u-boot,dm-pre-proper;
+};
+
+&pd_conn_sdch2 {
+ u-boot,dm-pre-proper;
+};
+
+&pd_conn_enet0 {
+ u-boot,dm-pre-proper;
+};
+
+&gpio0 {
+ u-boot,dm-pre-proper;
+};
+
+&gpio1 {
+ u-boot,dm-pre-proper;
+};
+
+&gpio2 {
+ u-boot,dm-pre-proper;
+};
+
+&gpio3 {
+ u-boot,dm-pre-proper;
+};
+
+&gpio4 {
+ u-boot,dm-pre-proper;
+};
+
+&gpio5 {
+ u-boot,dm-pre-proper;
+};
+
+&gpio6 {
+ u-boot,dm-pre-proper;
+};
+
+&gpio7 {
+ u-boot,dm-pre-proper;
+};
+
+&lpuart3 {
+ u-boot,dm-pre-proper;
+};
+
+&lpuart0 {
+ u-boot,dm-pre-proper;
+};
+
+&usdhc1 {
+ u-boot,dm-pre-proper;
+ /delete-property/ assigned-clock-parents;
+};
+
+&usdhc2 {
+ u-boot,dm-pre-proper;
+ /delete-property/ assigned-clock-parents;
+};
diff --git a/arch/arm/dts/fsl-imx8qxp-apalis.dts b/arch/arm/dts/fsl-imx8qxp-apalis.dts
new file mode 100644
index 0000000..6bd231b
--- /dev/null
+++ b/arch/arm/dts/fsl-imx8qxp-apalis.dts
@@ -0,0 +1,278 @@
+// SPDX-License-Identifier: GPL-2.0+ OR MIT
+/*
+ * Copyright 2020 Toradex
+ */
+
+/dts-v1/;
+
+#include "fsl-imx8qxp.dtsi"
+#include "fsl-imx8qxp-apalis-u-boot.dtsi"
+
+/ {
+ model = "Toradex Apalis iMX8X";
+ compatible = "toradex,apalis-imx8x", "fsl,imx8qxp";
+
+ chosen {
+ bootargs = "console=ttyLP1,115200";
+ stdout-path = &lpuart1;
+ };
+
+ regulators {
+ compatible = "simple-bus";
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ reg_usb_otg1_vbus: regulator@0 {
+ compatible = "regulator-fixed";
+ reg = <0>;
+ regulator-name = "usb_otg1_vbus";
+ regulator-min-microvolt = <5000000>;
+ regulator-max-microvolt = <5000000>;
+ gpio = <&gpio3 16 GPIO_ACTIVE_HIGH>;
+ enable-active-high;
+ };
+ };
+};
+
+&iomuxc {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_hog0>, <&pinctrl_hog1>, <&pinctrl_reset_moci>;
+
+ apalis-imx8x {
+ /* Apalis UART1 */
+ pinctrl_lpuart1: lpuart1grp {
+ fsl,pins = <
+ SC_P_UART1_RX_ADMA_UART1_RX 0x06000020 /* SODIMM 118 */
+ SC_P_UART1_TX_ADMA_UART1_TX 0x06000020 /* SODIMM 112 */
+ >;
+ };
+
+ /* On-module Gigabit Ethernet PHY Micrel KSZ9031 */
+ pinctrl_fec1: fec1grp {
+ fsl,pins = <
+ SC_P_COMP_CTL_GPIO_1V8_3V3_ENET_ENETB0_PAD 0x14a0
+ SC_P_COMP_CTL_GPIO_1V8_3V3_ENET_ENETB1_PAD 0x14a0
+ SC_P_ENET0_MDC_CONN_ENET0_MDC 0x06000020
+ SC_P_ENET0_MDIO_CONN_ENET0_MDIO 0x06000020
+ SC_P_ENET0_RGMII_TX_CTL_CONN_ENET0_RGMII_TX_CTL 0x61
+ SC_P_ENET0_RGMII_TXC_CONN_ENET0_RGMII_TXC 0x61
+ SC_P_ENET0_RGMII_TXD0_CONN_ENET0_RGMII_TXD0 0x61
+ SC_P_ENET0_RGMII_TXD1_CONN_ENET0_RGMII_TXD1 0x61
+ SC_P_ENET0_RGMII_TXD2_CONN_ENET0_RGMII_TXD2 0x61
+ SC_P_ENET0_RGMII_TXD3_CONN_ENET0_RGMII_TXD3 0x61
+ SC_P_ENET0_RGMII_RXC_CONN_ENET0_RGMII_RXC 0x61
+ SC_P_ENET0_RGMII_RX_CTL_CONN_ENET0_RGMII_RX_CTL 0x61
+ SC_P_ENET0_RGMII_RXD0_CONN_ENET0_RGMII_RXD0 0x61
+ SC_P_ENET0_RGMII_RXD1_CONN_ENET0_RGMII_RXD1 0x61
+ SC_P_ENET0_RGMII_RXD2_CONN_ENET0_RGMII_RXD2 0x61
+ SC_P_ENET0_RGMII_RXD3_CONN_ENET0_RGMII_RXD3 0x61
+ /* On-module ETH_RESET# */
+ SC_P_MIPI_CSI0_MCLK_OUT_LSIO_GPIO3_IO04 0x06000020
+ /* On-module ETH_INT# */
+ SC_P_ADC_IN2_LSIO_GPIO1_IO12 0x21
+ >;
+ };
+
+ /* Apalis BKL_ON */
+ pinctrl_gpio_bkl_on: gpio-bkl-on {
+ fsl,pins = <
+ SC_P_QSPI0A_DQS_LSIO_GPIO3_IO13 0x40 /* SODIMM 286 */
+ >;
+ };
+
+ pinctrl_hog0: hog0grp {
+ fsl,pins = <
+ SC_P_COMP_CTL_GPIO_1V8_3V3_GPIORHB_PAD 0x000514a0
+ >;
+ };
+
+ pinctrl_hog1: hog1grp {
+ fsl,pins = <
+ /* Apalis USBO1_EN */
+ SC_P_QSPI0A_SCLK_LSIO_GPIO3_IO16 0x41 /* SODIMM 274 */
+ >;
+ };
+
+ /* Apalis RESET_MOCI# */
+ pinctrl_reset_moci: gpioresetmocigrp {
+ fsl,pins = <
+ SC_P_PCIE_CTRL0_CLKREQ_B_LSIO_GPIO4_IO01 0x21
+ >;
+ };
+
+ /* On-module eMMC */
+ pinctrl_usdhc1: usdhc1grp {
+ fsl,pins = <
+ SC_P_EMMC0_CLK_CONN_EMMC0_CLK 0x06000041
+ SC_P_EMMC0_CMD_CONN_EMMC0_CMD 0x21
+ SC_P_EMMC0_DATA0_CONN_EMMC0_DATA0 0x21
+ SC_P_EMMC0_DATA1_CONN_EMMC0_DATA1 0x21
+ SC_P_EMMC0_DATA2_CONN_EMMC0_DATA2 0x21
+ SC_P_EMMC0_DATA3_CONN_EMMC0_DATA3 0x21
+ SC_P_EMMC0_DATA4_CONN_EMMC0_DATA4 0x21
+ SC_P_EMMC0_DATA5_CONN_EMMC0_DATA5 0x21
+ SC_P_EMMC0_DATA6_CONN_EMMC0_DATA6 0x21
+ SC_P_EMMC0_DATA7_CONN_EMMC0_DATA7 0x21
+ SC_P_EMMC0_STROBE_CONN_EMMC0_STROBE 0x41
+ SC_P_EMMC0_RESET_B_CONN_EMMC0_RESET_B 0x21
+ >;
+ };
+
+ pinctrl_usdhc1_100mhz: usdhc1grp100mhz {
+ fsl,pins = <
+ SC_P_EMMC0_CLK_CONN_EMMC0_CLK 0x06000041
+ SC_P_EMMC0_CMD_CONN_EMMC0_CMD 0x21
+ SC_P_EMMC0_DATA0_CONN_EMMC0_DATA0 0x21
+ SC_P_EMMC0_DATA1_CONN_EMMC0_DATA1 0x21
+ SC_P_EMMC0_DATA2_CONN_EMMC0_DATA2 0x21
+ SC_P_EMMC0_DATA3_CONN_EMMC0_DATA3 0x21
+ SC_P_EMMC0_DATA4_CONN_EMMC0_DATA4 0x21
+ SC_P_EMMC0_DATA5_CONN_EMMC0_DATA5 0x21
+ SC_P_EMMC0_DATA6_CONN_EMMC0_DATA6 0x21
+ SC_P_EMMC0_DATA7_CONN_EMMC0_DATA7 0x21
+ SC_P_EMMC0_STROBE_CONN_EMMC0_STROBE 0x41
+ SC_P_EMMC0_RESET_B_CONN_EMMC0_RESET_B 0x21
+ >;
+ };
+
+ pinctrl_usdhc1_200mhz: usdhc1grp200mhz {
+ fsl,pins = <
+ SC_P_EMMC0_CLK_CONN_EMMC0_CLK 0x06000041
+ SC_P_EMMC0_CMD_CONN_EMMC0_CMD 0x21
+ SC_P_EMMC0_DATA0_CONN_EMMC0_DATA0 0x21
+ SC_P_EMMC0_DATA1_CONN_EMMC0_DATA1 0x21
+ SC_P_EMMC0_DATA2_CONN_EMMC0_DATA2 0x21
+ SC_P_EMMC0_DATA3_CONN_EMMC0_DATA3 0x21
+ SC_P_EMMC0_DATA4_CONN_EMMC0_DATA4 0x21
+ SC_P_EMMC0_DATA5_CONN_EMMC0_DATA5 0x21
+ SC_P_EMMC0_DATA6_CONN_EMMC0_DATA6 0x21
+ SC_P_EMMC0_DATA7_CONN_EMMC0_DATA7 0x21
+ SC_P_EMMC0_STROBE_CONN_EMMC0_STROBE 0x41
+ SC_P_EMMC0_RESET_B_CONN_EMMC0_RESET_B 0x21
+ >;
+ };
+
+ /* Apalis MMC1_CD# */
+ pinctrl_usdhc2_gpio: mmc1gpiogrp {
+ fsl,pins = <
+ SC_P_USDHC1_CD_B_LSIO_GPIO4_IO22 0x06000021 /* SODIMM 164 */
+ >;
+ };
+
+ pinctrl_usdhc2_gpio_sleep: usdhc1gpioslpgrp {
+ fsl,pins = <
+ SC_P_USDHC1_CD_B_LSIO_GPIO4_IO22 0x60 /* SODIMM 164 */
+ >;
+ };
+
+ /* Apalis USBH_EN */
+ pinctrl_usbh_en: usbhen {
+ fsl,pins = <
+ SC_P_USB_SS3_TC1_LSIO_GPIO4_IO04 0x40 /* SODIMM 84 */
+ >;
+ };
+
+ /* Apalis MMC1 */
+ pinctrl_usdhc2: usdhc2grp {
+ fsl,pins = <
+ SC_P_USDHC1_CLK_CONN_USDHC1_CLK 0x06000041 /* SODIMM 154 */
+ SC_P_USDHC1_CMD_CONN_USDHC1_CMD 0x21 /* SODIMM 150 */
+ SC_P_USDHC1_DATA0_CONN_USDHC1_DATA0 0x21 /* SODIMM 160 */
+ SC_P_USDHC1_DATA1_CONN_USDHC1_DATA1 0x21 /* SODIMM 162 */
+ SC_P_USDHC1_DATA2_CONN_USDHC1_DATA2 0x21 /* SODIMM 144 */
+ SC_P_USDHC1_DATA3_CONN_USDHC1_DATA3 0x21 /* SODIMM 146 */
+ SC_P_USDHC1_VSELECT_CONN_USDHC1_VSELECT 0x21
+ >;
+ };
+
+ pinctrl_usdhc2_100mhz: usdhc2grp100mhz {
+ fsl,pins = <
+ SC_P_USDHC1_CLK_CONN_USDHC1_CLK 0x06000041 /* SODIMM 154 */
+ SC_P_USDHC1_CMD_CONN_USDHC1_CMD 0x21 /* SODIMM 150 */
+ SC_P_USDHC1_DATA0_CONN_USDHC1_DATA0 0x21 /* SODIMM 160 */
+ SC_P_USDHC1_DATA1_CONN_USDHC1_DATA1 0x21 /* SODIMM 162 */
+ SC_P_USDHC1_DATA2_CONN_USDHC1_DATA2 0x21 /* SODIMM 144 */
+ SC_P_USDHC1_DATA3_CONN_USDHC1_DATA3 0x21 /* SODIMM 146 */
+ SC_P_USDHC1_VSELECT_CONN_USDHC1_VSELECT 0x21
+ >;
+ };
+
+ pinctrl_usdhc2_200mhz: usdhc2grp200mhz {
+ fsl,pins = <
+ SC_P_USDHC1_CLK_CONN_USDHC1_CLK 0x06000041 /* SODIMM 154 */
+ SC_P_USDHC1_CMD_CONN_USDHC1_CMD 0x21 /* SODIMM 150 */
+ SC_P_USDHC1_DATA0_CONN_USDHC1_DATA0 0x21 /* SODIMM 160 */
+ SC_P_USDHC1_DATA1_CONN_USDHC1_DATA1 0x21 /* SODIMM 162 */
+ SC_P_USDHC1_DATA2_CONN_USDHC1_DATA2 0x21 /* SODIMM 144 */
+ SC_P_USDHC1_DATA3_CONN_USDHC1_DATA3 0x21 /* SODIMM 146 */
+ SC_P_USDHC1_VSELECT_CONN_USDHC1_VSELECT 0x21
+ >;
+ };
+
+ pinctrl_usdhc2_sleep: usdhc2slpgrp {
+ fsl,pins = <
+ SC_P_USDHC1_CLK_LSIO_GPIO4_IO23 0x60 /* SODIMM 154 */
+ SC_P_USDHC1_CMD_LSIO_GPIO4_IO24 0x60 /* SODIMM 150 */
+ SC_P_USDHC1_DATA0_LSIO_GPIO4_IO25 0x60 /* SODIMM 160 */
+ SC_P_USDHC1_DATA1_LSIO_GPIO4_IO26 0x60 /* SODIMM 162 */
+ SC_P_USDHC1_DATA2_LSIO_GPIO4_IO27 0x60 /* SODIMM 144 */
+ SC_P_USDHC1_DATA3_LSIO_GPIO4_IO28 0x60 /* SODIMM 146 */
+ SC_P_USDHC1_VSELECT_CONN_USDHC1_VSELECT 0x21
+ >;
+ };
+ };
+};
+
+/* Apalis Gigabit LAN */
+&fec1 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_fec1>;
+ fsl,magic-packet;
+ phy-handle = <ðphy0>;
+ phy-mode = "rgmii";
+ phy-reset-duration = <10>;
+ phy-reset-post-delay = <150>;
+ phy-reset-gpios = <&gpio3 4 GPIO_ACTIVE_LOW>;
+ status = "okay";
+
+ mdio {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ ethphy0: ethernet-phy@4 {
+ compatible = "ethernet-phy-ieee802.3-c22";
+ reg = <4>;
+ };
+ };
+};
+
+/* Apalis UART1 */
+&lpuart1 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_lpuart1>;
+ status = "okay";
+};
+
+/* On-module eMMC */
+&usdhc1 {
+ bus-width = <8>;
+ non-removable;
+ pinctrl-names = "default", "state_100mhz", "state_200mhz";
+ pinctrl-0 = <&pinctrl_usdhc1>;
+ pinctrl-1 = <&pinctrl_usdhc1_100mhz>;
+ pinctrl-2 = <&pinctrl_usdhc1_200mhz>;
+ status = "okay";
+};
+
+/* Apalis MMC1 */
+&usdhc2 {
+ bus-width = <4>;
+ cd-gpios = <&gpio4 22 GPIO_ACTIVE_LOW>;
+ pinctrl-names = "default", "state_100mhz", "state_200mhz", "sleep";
+ pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>;
+ pinctrl-1 = <&pinctrl_usdhc2_100mhz>, <&pinctrl_usdhc2_gpio>;
+ pinctrl-2 = <&pinctrl_usdhc2_200mhz>, <&pinctrl_usdhc2_gpio>;
+ pinctrl-3 = <&pinctrl_usdhc2_sleep>, <&pinctrl_usdhc2_gpio_sleep>;
+ disable-wp;
+ status = "okay";
+};
diff --git a/arch/arm/dts/imx53-ppd-uboot.dtsi b/arch/arm/dts/imx53-ppd-uboot.dtsi
index d61b7cb..b293e27 100644
--- a/arch/arm/dts/imx53-ppd-uboot.dtsi
+++ b/arch/arm/dts/imx53-ppd-uboot.dtsi
@@ -28,7 +28,7 @@
#size-cells = <1>;
vpd@0 {
- reg = <0 1022>;
+ reg = <0 800>;
};
bootcount: bootcount@1022 {
diff --git a/arch/arm/dts/imx6dl-aristainetos2_4-u-boot.dtsi b/arch/arm/dts/imx6dl-aristainetos2_4-u-boot.dtsi
deleted file mode 100644
index ac7052c..0000000
--- a/arch/arm/dts/imx6dl-aristainetos2_4-u-boot.dtsi
+++ /dev/null
@@ -1,13 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0
-/*
- * Copyright (C) 2019 Heiko Schocher <hs@denx.de>
- */
-
-#include <imx6qdl-aristainetos2-u-boot.dtsi>
-
-&lcd_panel {
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_ipu_disp>;
- enable-gpios = <&gpio6 15 GPIO_ACTIVE_HIGH>;
- backlight = <&backlight>;
-};
diff --git a/arch/arm/dts/imx6dl-aristainetos2_4.dts b/arch/arm/dts/imx6dl-aristainetos2_4.dts
deleted file mode 100644
index 0157e24..0000000
--- a/arch/arm/dts/imx6dl-aristainetos2_4.dts
+++ /dev/null
@@ -1,51 +0,0 @@
-// SPDX-License-Identifier: (GPL-2.0)
-/*
- * support for the imx6 based aristainetos2 board
- * parts for 4.3 inch LG display on spi1 port0
- *
- * Copyright (C) 2019 Heiko Schocher <hs@denx.de>
- * Copyright (C) 2015 Heiko Schocher <hs@denx.de>
- *
- */
-/dts-v1/;
-
-#include "imx6dl-aristainetos2_4.dtsi"
-#include "imx6qdl-aristainetos2.dtsi"
-
-/ {
- model = "aristainetos2 i.MX6 Dual Lite Board 4";
- compatible = "fsl,imx6dl";
-
-};
-
-&ecspi1 {
- lcd_panel: display@0 {
- compatible = "lg,lg4573";
- spi-max-frequency = <10000000>;
- reg = <0>;
- power-on-delay = <10>;
-
- display-timings {
- 480x800p57 {
- native-mode;
- clock-frequency = <27000027>;
- hactive = <480>;
- vactive = <800>;
- hfront-porch = <10>;
- hback-porch = <59>;
- hsync-len = <10>;
- vback-porch = <15>;
- vfront-porch = <15>;
- vsync-len = <15>;
- hsync-active = <1>;
- vsync-active = <1>;
- };
- };
-
- port {
- panel_in: endpoint {
- remote-endpoint = <&display_out>;
- };
- };
- };
-};
diff --git a/arch/arm/dts/imx6dl-aristainetos2_4.dtsi b/arch/arm/dts/imx6dl-aristainetos2_4.dtsi
deleted file mode 100644
index be4601b..0000000
--- a/arch/arm/dts/imx6dl-aristainetos2_4.dtsi
+++ /dev/null
@@ -1,84 +0,0 @@
-// SPDX-License-Identifier: (GPL-2.0)
-/*
- * support for the imx6 based aristainetos2 board
- * parts for 4.3 inch LG display on the parallel port and atmel maxtouch
- *
- * Copyright (C) 2019 Heiko Schocher <hs@denx.de>
- * Copyright (C) 2015 Heiko Schocher <hs@denx.de>
- *
- */
-/dts-v1/;
-#include "imx6dl.dtsi"
-
-/ {
- display0: disp0 {
- #address-cells = <1>;
- #size-cells = <0>;
- compatible = "fsl,imx-parallel-display";
- interface-pix-fmt = "rgb24";
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_ipu_disp>;
-
- port@0 {
- reg = <0>;
- display0_in: endpoint {
- remote-endpoint = <&ipu1_di0_disp0>;
- };
- };
-
- port@1 {
- reg = <1>;
- display_out: endpoint {
- remote-endpoint = <&panel_in>;
- };
- };
- };
-};
-
-&i2c3 {
- touch: touch@4b {
- compatible = "atmel,maxtouch";
- reg = <0x4b>;
- interrupt-parent = <&gpio2>;
- interrupts = <9 8>;
- };
-};
-
-&ipu1_di0_disp0 {
- remote-endpoint = <&display0_in>;
-};
-
-&iomuxc {
- pinctrl_ipu_disp: ipudisp1grp {
- fsl,pins = <
- MX6QDL_PAD_DI0_DISP_CLK__IPU1_DI0_DISP_CLK 0x31
- MX6QDL_PAD_DI0_PIN15__IPU1_DI0_PIN15 0xE1
- MX6QDL_PAD_DI0_PIN2__IPU1_DI0_PIN02 0x10
- MX6QDL_PAD_DI0_PIN3__IPU1_DI0_PIN03 0x10
- MX6QDL_PAD_DISP0_DAT0__IPU1_DISP0_DATA00 0xE1
- MX6QDL_PAD_DISP0_DAT1__IPU1_DISP0_DATA01 0xE1
- MX6QDL_PAD_DISP0_DAT2__IPU1_DISP0_DATA02 0xE1
- MX6QDL_PAD_DISP0_DAT3__IPU1_DISP0_DATA03 0xE1
- MX6QDL_PAD_DISP0_DAT4__IPU1_DISP0_DATA04 0xE1
- MX6QDL_PAD_DISP0_DAT5__IPU1_DISP0_DATA05 0xE1
- MX6QDL_PAD_DISP0_DAT6__IPU1_DISP0_DATA06 0xE1
- MX6QDL_PAD_DISP0_DAT7__IPU1_DISP0_DATA07 0xE1
- MX6QDL_PAD_DISP0_DAT8__IPU1_DISP0_DATA08 0xE1
- MX6QDL_PAD_DISP0_DAT9__IPU1_DISP0_DATA09 0xE1
- MX6QDL_PAD_DISP0_DAT10__IPU1_DISP0_DATA10 0xE1
- MX6QDL_PAD_DISP0_DAT11__IPU1_DISP0_DATA11 0xE1
- MX6QDL_PAD_DISP0_DAT12__IPU1_DISP0_DATA12 0xE1
- MX6QDL_PAD_DISP0_DAT13__IPU1_DISP0_DATA13 0xE1
- MX6QDL_PAD_DISP0_DAT14__IPU1_DISP0_DATA14 0xe1
- MX6QDL_PAD_DISP0_DAT15__IPU1_DISP0_DATA15 0xE1
- MX6QDL_PAD_DISP0_DAT16__IPU1_DISP0_DATA16 0xE1
- MX6QDL_PAD_DISP0_DAT17__IPU1_DISP0_DATA17 0xE1
- MX6QDL_PAD_DISP0_DAT18__IPU1_DISP0_DATA18 0xE1
- MX6QDL_PAD_DISP0_DAT19__IPU1_DISP0_DATA19 0xE1
- MX6QDL_PAD_DISP0_DAT20__IPU1_DISP0_DATA20 0xE1
- MX6QDL_PAD_DISP0_DAT21__IPU1_DISP0_DATA21 0xE1
- MX6QDL_PAD_DISP0_DAT22__IPU1_DISP0_DATA22 0xE1
- MX6QDL_PAD_DISP0_DAT23__IPU1_DISP0_DATA23 0xE1
- >;
- };
-};
diff --git a/arch/arm/dts/imx6dl-aristainetos2_7-u-boot.dtsi b/arch/arm/dts/imx6dl-aristainetos2_7-u-boot.dtsi
deleted file mode 100644
index 25bc562..0000000
--- a/arch/arm/dts/imx6dl-aristainetos2_7-u-boot.dtsi
+++ /dev/null
@@ -1,19 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0
-/*
- * Copyright (C) 2019 Heiko Schocher <hs@denx.de>
- */
-
-#include <imx6qdl-aristainetos2-u-boot.dtsi>
-/ {
- vdd_panel_reg: regulator-panel {
- compatible = "regulator-fixed";
- regulator-name = "panel_regulator";
- regulator-min-microvolt = <3300000>;
- regulator-max-microvolt = <3300000>;
- regulator-always-on;
- };
-};
-
-&panel0 {
- power-supply = <&vdd_panel_reg>;
-};
diff --git a/arch/arm/dts/imx6dl-aristainetos2_7.dts b/arch/arm/dts/imx6dl-aristainetos2_7.dts
deleted file mode 100644
index 0d1e83c..0000000
--- a/arch/arm/dts/imx6dl-aristainetos2_7.dts
+++ /dev/null
@@ -1,16 +0,0 @@
-// SPDX-License-Identifier: (GPL-2.0)
-/*
- * support for the imx6 based aristainetos2 board
- *
- * Copyright (C) 2019 Heiko Schocher <hs@denx.de>
- * Copyright (C) 2015 Heiko Schocher <hs@denx.de>
- *
- */
-/dts-v1/;
-#include "imx6dl-aristainetos2_7.dtsi"
-#include "imx6qdl-aristainetos2.dtsi"
-
-/ {
- model = "aristainetos2 i.MX6 Dual Lite Board 7";
- compatible = "fsl,imx6dl";
-};
diff --git a/arch/arm/dts/imx6dl-aristainetos2_7.dtsi b/arch/arm/dts/imx6dl-aristainetos2_7.dtsi
index 52d6a51..ec633b8 100644
--- a/arch/arm/dts/imx6dl-aristainetos2_7.dtsi
+++ b/arch/arm/dts/imx6dl-aristainetos2_7.dtsi
@@ -1,7 +1,7 @@
// SPDX-License-Identifier: (GPL-2.0)
/*
* support for the imx6 based aristainetos2 board
- * parts for 7 inch LG display connected to the LVDS port and atmel maxtouch
+ * parts for 7 inch LG display connected to the LVDS port
*
* Copyright (C) 2019 Heiko Schocher <hs@denx.de>
* Copyright (C) 2015 Heiko Schocher <hs@denx.de>
@@ -26,15 +26,6 @@
};
};
-&i2c3 {
- touch: touch@4d {
- compatible = "atmel,maxtouch";
- reg = <0x4d>;
- interrupt-parent = <&gpio2>;
- interrupts = <9 8>;
- };
-};
-
&ldb {
status = "okay";
diff --git a/arch/arm/dts/imx6dl-aristainetos2b_4-u-boot.dtsi b/arch/arm/dts/imx6dl-aristainetos2b_4-u-boot.dtsi
deleted file mode 100644
index ee02df3..0000000
--- a/arch/arm/dts/imx6dl-aristainetos2b_4-u-boot.dtsi
+++ /dev/null
@@ -1,13 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+ or X11
-/*
- * Copyright (C) 2019 Heiko Schocher <hs@denx.de>
- */
-
-#include <imx6qdl-aristainetos2b-u-boot.dtsi>
-
-&lcd_panel {
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_ipu_disp>;
- enable-gpios = <&gpio6 15 GPIO_ACTIVE_HIGH>;
- backlight = <&backlight>;
-};
diff --git a/arch/arm/dts/imx6dl-aristainetos2b_4.dts b/arch/arm/dts/imx6dl-aristainetos2b_4.dts
deleted file mode 100644
index a48a25c..0000000
--- a/arch/arm/dts/imx6dl-aristainetos2b_4.dts
+++ /dev/null
@@ -1,50 +0,0 @@
-// SPDX-License-Identifier: (GPL-2.0)
-/*
- * support for the imx6 based aristainetos2b board
- * parts for 4.3 inch LG display on spi1 port1
- *
- * Copyright (C) 2019 Heiko Schocher <hs@denx.de>
- *
- */
-/dts-v1/;
-
-#include "imx6dl-aristainetos2_4.dtsi"
-#include "imx6qdl-aristainetos2b.dtsi"
-
-/ {
- model = "aristainetos2b i.MX6 Dual Lite Board 4";
- compatible = "fsl,imx6dl";
-
-};
-
-&ecspi1 {
- lcd_panel: display@0 {
- compatible = "lg,lg4573";
- spi-max-frequency = <10000000>;
- reg = <1>;
- power-on-delay = <10>;
-
- display-timings {
- 480x800p57 {
- native-mode;
- clock-frequency = <27000027>;
- hactive = <480>;
- vactive = <800>;
- hfront-porch = <10>;
- hback-porch = <59>;
- hsync-len = <10>;
- vback-porch = <15>;
- vfront-porch = <15>;
- vsync-len = <15>;
- hsync-active = <1>;
- vsync-active = <1>;
- };
- };
-
- port {
- panel_in: endpoint {
- remote-endpoint = <&display_out>;
- };
- };
- };
-};
diff --git a/arch/arm/dts/imx6dl-aristainetos2b_7.dts b/arch/arm/dts/imx6dl-aristainetos2b_7.dts
deleted file mode 100644
index f1496cb..0000000
--- a/arch/arm/dts/imx6dl-aristainetos2b_7.dts
+++ /dev/null
@@ -1,16 +0,0 @@
-// SPDX-License-Identifier: (GPL-2.0)
-/*
- * support for the imx6 based aristainetos2 board
- *
- * Copyright (C) 2019 Heiko Schocher <hs@denx.de>
- * Copyright (C) 2015 Heiko Schocher <hs@denx.de>
- *
- */
-/dts-v1/;
-#include "imx6dl-aristainetos2_7.dtsi"
-#include "imx6qdl-aristainetos2b.dtsi"
-
-/ {
- model = "aristainetos2b i.MX6 Dual Lite Board 7";
- compatible = "fsl,imx6dl";
-};
diff --git a/arch/arm/dts/imx6dl-aristainetos2b_csl_4-u-boot.dtsi b/arch/arm/dts/imx6dl-aristainetos2b_csl_4-u-boot.dtsi
deleted file mode 100644
index 654ac12..0000000
--- a/arch/arm/dts/imx6dl-aristainetos2b_csl_4-u-boot.dtsi
+++ /dev/null
@@ -1,13 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+ or X11
-/*
- * Copyright (C) 2019 Heiko Schocher <hs@denx.de>
- */
-
-#include <imx6qdl-aristainetos2b_csl-u-boot.dtsi>
-
-&lcd_panel {
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_ipu_disp>;
- enable-gpios = <&gpio6 15 GPIO_ACTIVE_HIGH>;
- backlight = <&backlight>;
-};
diff --git a/arch/arm/dts/imx6dl-aristainetos2b_csl_4.dts b/arch/arm/dts/imx6dl-aristainetos2b_csl_4.dts
deleted file mode 100644
index bfbb799..0000000
--- a/arch/arm/dts/imx6dl-aristainetos2b_csl_4.dts
+++ /dev/null
@@ -1,50 +0,0 @@
-// SPDX-License-Identifier: (GPL-2.0)
-/*
- * support for the imx6 based aristainetos2b csl board
- * parts for 4.3 inch LG display on spi1 port1
- *
- * Copyright (C) 2019 Heiko Schocher <hs@denx.de>
- *
- */
-/dts-v1/;
-
-#include "imx6dl-aristainetos2_4.dtsi"
-#include "imx6qdl-aristainetos2b_csl.dtsi"
-
-/ {
- model = "aristainetos2b csl i.MX6 Dual Lite Board 4";
- compatible = "fsl,imx6dl";
-
-};
-
-&ecspi1 {
- lcd_panel: display@0 {
- compatible = "lg,lg4573";
- spi-max-frequency = <10000000>;
- reg = <1>;
- power-on-delay = <10>;
-
- display-timings {
- 480x800p57 {
- native-mode;
- clock-frequency = <27000027>;
- hactive = <480>;
- vactive = <800>;
- hfront-porch = <10>;
- hback-porch = <59>;
- hsync-len = <10>;
- vback-porch = <15>;
- vfront-porch = <15>;
- vsync-len = <15>;
- hsync-active = <1>;
- vsync-active = <1>;
- };
- };
-
- port {
- panel_in: endpoint {
- remote-endpoint = <&display_out>;
- };
- };
- };
-};
diff --git a/arch/arm/dts/imx6dl-aristainetos2b_csl_7-u-boot.dtsi b/arch/arm/dts/imx6dl-aristainetos2b_csl_7-u-boot.dtsi
deleted file mode 100644
index 70d195e..0000000
--- a/arch/arm/dts/imx6dl-aristainetos2b_csl_7-u-boot.dtsi
+++ /dev/null
@@ -1,19 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+ or X11
-/*
- * Copyright (C) 2019 Heiko Schocher <hs@denx.de>
- */
-
-#include <imx6qdl-aristainetos2b_csl-u-boot.dtsi>
-/ {
- vdd_panel_reg: regulator-panel {
- compatible = "regulator-fixed";
- regulator-name = "panel_regulator";
- regulator-min-microvolt = <3300000>;
- regulator-max-microvolt = <3300000>;
- regulator-always-on;
- };
-};
-
-&panel0 {
- power-supply = <&vdd_panel_reg>;
-};
diff --git a/arch/arm/dts/imx6dl-aristainetos2b_csl_7.dts b/arch/arm/dts/imx6dl-aristainetos2b_csl_7.dts
deleted file mode 100644
index ecf767d..0000000
--- a/arch/arm/dts/imx6dl-aristainetos2b_csl_7.dts
+++ /dev/null
@@ -1,16 +0,0 @@
-// SPDX-License-Identifier: (GPL-2.0)
-/*
- * support for the imx6 based aristainetos2 board
- *
- * Copyright (C) 2019 Heiko Schocher <hs@denx.de>
- * Copyright (C) 2015 Heiko Schocher <hs@denx.de>
- *
- */
-/dts-v1/;
-#include "imx6dl-aristainetos2_7.dtsi"
-#include "imx6qdl-aristainetos2b_csl.dtsi"
-
-/ {
- model = "aristainetos2b csl i.MX6 Dual Lite Board 7";
- compatible = "fsl,imx6dl";
-};
diff --git a/arch/arm/dts/imx6dl-aristainetos2c_4-u-boot.dtsi b/arch/arm/dts/imx6dl-aristainetos2c_4-u-boot.dtsi
deleted file mode 100644
index 052d518..0000000
--- a/arch/arm/dts/imx6dl-aristainetos2c_4-u-boot.dtsi
+++ /dev/null
@@ -1,13 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+ or X11
-/*
- * Copyright (C) 2019 Heiko Schocher <hs@denx.de>
- */
-
-#include <imx6qdl-aristainetos2c-u-boot.dtsi>
-
-&lcd_panel {
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_ipu_disp>;
- enable-gpios = <&gpio6 15 GPIO_ACTIVE_HIGH>;
- backlight = <&backlight>;
-};
diff --git a/arch/arm/dts/imx6dl-aristainetos2c_4.dts b/arch/arm/dts/imx6dl-aristainetos2c_4.dts
deleted file mode 100644
index 142b108..0000000
--- a/arch/arm/dts/imx6dl-aristainetos2c_4.dts
+++ /dev/null
@@ -1,50 +0,0 @@
-// SPDX-License-Identifier: (GPL-2.0)
-/*
- * support for the imx6 based aristainetos2c board
- * parts for 4.3 inch LG display on spi1 port1
- *
- * Copyright (C) 2019 Heiko Schocher <hs@denx.de>
- *
- */
-/dts-v1/;
-
-#include "imx6dl-aristainetos2_4.dtsi"
-#include "imx6qdl-aristainetos2c.dtsi"
-
-/ {
- model = "aristainetos2c i.MX6 Dual Lite Board 4";
- compatible = "fsl,imx6dl";
-
-};
-
-&ecspi1 {
- lcd_panel: display@0 {
- compatible = "lg,lg4573";
- spi-max-frequency = <10000000>;
- reg = <1>;
- power-on-delay = <10>;
-
- display-timings {
- 480x800p57 {
- native-mode;
- clock-frequency = <27000027>;
- hactive = <480>;
- vactive = <800>;
- hfront-porch = <10>;
- hback-porch = <59>;
- hsync-len = <10>;
- vback-porch = <15>;
- vfront-porch = <15>;
- vsync-len = <15>;
- hsync-active = <1>;
- vsync-active = <1>;
- };
- };
-
- port {
- panel_in: endpoint {
- remote-endpoint = <&display_out>;
- };
- };
- };
-};
diff --git a/arch/arm/dts/imx6dl-aristainetos2c_7.dts b/arch/arm/dts/imx6dl-aristainetos2c_7.dts
index 35435e1..e1f9e88 100644
--- a/arch/arm/dts/imx6dl-aristainetos2c_7.dts
+++ b/arch/arm/dts/imx6dl-aristainetos2c_7.dts
@@ -11,6 +11,6 @@
#include "imx6qdl-aristainetos2c.dtsi"
/ {
- model = "aristainetos2c i.MX6 Dual Lite Board 7";
- compatible = "fsl,imx6dl";
+ model = "aristainetos2c+2d i.MX6 Dual Lite Boards 7";
+ compatible = "abb,aristainetos2-imx6dl-7", "fsl,imx6dl";
};
diff --git a/arch/arm/dts/imx6dl-aristainetos2b_7-u-boot.dtsi b/arch/arm/dts/imx6dl-aristainetos2c_cslb_7-u-boot.dtsi
similarity index 87%
rename from arch/arm/dts/imx6dl-aristainetos2b_7-u-boot.dtsi
rename to arch/arm/dts/imx6dl-aristainetos2c_cslb_7-u-boot.dtsi
index 0cb4f19..b069deb 100644
--- a/arch/arm/dts/imx6dl-aristainetos2b_7-u-boot.dtsi
+++ b/arch/arm/dts/imx6dl-aristainetos2c_cslb_7-u-boot.dtsi
@@ -3,7 +3,7 @@
* Copyright (C) 2019 Heiko Schocher <hs@denx.de>
*/
-#include <imx6qdl-aristainetos2b-u-boot.dtsi>
+#include <imx6qdl-aristainetos2c_cslb-u-boot.dtsi>
/ {
vdd_panel_reg: regulator-panel {
compatible = "regulator-fixed";
diff --git a/arch/arm/dts/imx6dl-aristainetos2c_cslb_7.dts b/arch/arm/dts/imx6dl-aristainetos2c_cslb_7.dts
new file mode 100644
index 0000000..7f839ca
--- /dev/null
+++ b/arch/arm/dts/imx6dl-aristainetos2c_cslb_7.dts
@@ -0,0 +1,16 @@
+// SPDX-License-Identifier: (GPL-2.0)
+/*
+ * support for the imx6 based aristainetos2c cslb board
+ *
+ * Copyright (C) 2019 Heiko Schocher <hs@denx.de>
+ * Copyright (C) 2015 Heiko Schocher <hs@denx.de>
+ *
+ */
+/dts-v1/;
+#include "imx6dl-aristainetos2_7.dtsi"
+#include "imx6qdl-aristainetos2c_cslb.dtsi"
+
+/ {
+ model = "aristainetos2c cslb i.MX6 Dual Lite Board 7";
+ compatible = "abb,aristainetos2-imx6dl-7", "fsl,imx6dl";
+};
diff --git a/arch/arm/dts/imx6q-bx50v3-uboot.dtsi b/arch/arm/dts/imx6q-bx50v3-uboot.dtsi
index 01321ca..2de3b85 100644
--- a/arch/arm/dts/imx6q-bx50v3-uboot.dtsi
+++ b/arch/arm/dts/imx6q-bx50v3-uboot.dtsi
@@ -27,7 +27,7 @@
#size-cells = <1>;
vpd@0 {
- reg = <0 1022>;
+ reg = <0 800>;
};
bootcount: bootcount {
diff --git a/arch/arm/dts/imx6qdl-aristainetos2-common.dtsi b/arch/arm/dts/imx6qdl-aristainetos2-common.dtsi
index 2aa531b..5701436 100644
--- a/arch/arm/dts/imx6qdl-aristainetos2-common.dtsi
+++ b/arch/arm/dts/imx6qdl-aristainetos2-common.dtsi
@@ -1,6 +1,6 @@
// SPDX-License-Identifier: (GPL-2.0)
/*
- * support for the imx6 based aristainetos2 board
+ * support for the imx6 based aristainetos2 boards
* parts common to all versions
*
* Copyright (C) 2019 Heiko Schocher <hs@denx.de>
@@ -13,6 +13,8 @@
/ {
aliases {
eeprom0 = &i2c_eeprom0;
+ eeprom1 = &i2c_eeprom1;
+ eeprom2 = &i2c_eeprom2;
pmic0 = &i2c_pmic0;
};
@@ -250,6 +252,12 @@
};
};
+ i2c_eeprom2: eeprom@57{
+ compatible = "atmel,24c64";
+ reg = <0x57>;
+ pagesize = <32>;
+ };
+
rtc@68 {
compatible = "st,m41t11";
reg = <0x68>;
@@ -274,6 +282,19 @@
};
};
+&gpio2 {
+ tpm_pp {
+ gpio-hog;
+ output-low;
+ gpios = <17 GPIO_ACTIVE_HIGH>;
+ };
+ tpm_reset {
+ gpio-hog;
+ output-high;
+ gpios = <18 GPIO_ACTIVE_HIGH>;
+ };
+};
+
&gpio6 {
spi_bus_ena {
gpio-hog;
diff --git a/arch/arm/dts/imx6qdl-aristainetos2-u-boot.dtsi b/arch/arm/dts/imx6qdl-aristainetos2-u-boot.dtsi
index c713efd..3063f01 100644
--- a/arch/arm/dts/imx6qdl-aristainetos2-u-boot.dtsi
+++ b/arch/arm/dts/imx6qdl-aristainetos2-u-boot.dtsi
@@ -50,28 +50,6 @@
};
};
-&iomuxc {
- pinctrl-0 = <&pinctrl_gpio &pinctrl_gpio_fix>;
- u-boot,dm-pre-reloc;
-
- pinctrl_gpio_fix: gpiofixgrp {
- /*
- * usdhc2 has a levelshifter on the carrier board Rev. DV1,
- * that will automatically detect the driving direction.
- * During initialisation this isn't working correctly,
- * which causes DAT3 to be driven low towards the SD-card.
- * This causes a SD-card enetring the SPI-Mode
- * and therefore getting inaccessible until next power cycle.
- * As workaround we drive the DAT3 line as GPIO and set it high.
- * This makes usdhc2 unusable in u-boot, but works for the
- * initialisation in Linux
- */
- fsl,pins = <
- MX6QDL_PAD_SD2_DAT3__GPIO1_IO12 0x20000
- >;
- };
-};
-
&gpio1 {
usdhc_fix {
gpio-hog;
diff --git a/arch/arm/dts/imx6qdl-aristainetos2.dtsi b/arch/arm/dts/imx6qdl-aristainetos2.dtsi
deleted file mode 100644
index 788e13e..0000000
--- a/arch/arm/dts/imx6qdl-aristainetos2.dtsi
+++ /dev/null
@@ -1,244 +0,0 @@
-// SPDX-License-Identifier: (GPL-2.0)
-/*
- * support for the imx6 based aristainetos2 board
- *
- * Copyright (C) 2019 Heiko Schocher <hs@denx.de>
- * Copyright (C) 2015 Heiko Schocher <hs@denx.de>
- *
- */
-#include <dt-bindings/gpio/gpio.h>
-#include <dt-bindings/clock/imx6qdl-clock.h>
-
-#include "imx6qdl-aristainetos2-common.dtsi"
-
-/ {
- leds {
- compatible = "gpio-leds";
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_gpio>;
-
- LED_blue {
- label = "led_blue";
- gpios = <&gpio2 29 GPIO_ACTIVE_LOW>;
- };
-
- LED_green {
- label = "led_green";
- gpios = <&gpio5 4 GPIO_ACTIVE_LOW>;
- };
-
- LED_red {
- label = "led_red";
- gpios = <&gpio2 28 GPIO_ACTIVE_LOW>;
- };
-
- LED_yellow {
- label = "led_yellow";
- gpios = <&gpio6 16 GPIO_ACTIVE_LOW>;
- };
-
- LED_ena {
- label = "led_ena";
- gpios = <&gpio1 25 GPIO_ACTIVE_LOW>;
- };
- };
-};
-
-&ecspi1 {
- fsl,spi-num-chipselects = <3>;
- cs-gpios = <&gpio4 9 GPIO_ACTIVE_HIGH
- &gpio4 10 GPIO_ACTIVE_HIGH
- &gpio4 11 GPIO_ACTIVE_HIGH>;
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_ecspi1>;
- status = "okay";
-};
-
-&ecspi4 {
- fsl,spi-num-chipselects = <2>;
- cs-gpios = <&gpio3 29 GPIO_ACTIVE_HIGH &gpio5 2 GPIO_ACTIVE_HIGH>;
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_ecspi4>;
- status = "okay";
- pinctrl-assert-gpios = <&gpio2 15 GPIO_ACTIVE_HIGH>;
-
- flash: m25p80@1 {
- #address-cells = <1>;
- #size-cells = <1>;
- compatible = "micron,n25q128a11", "jedec,spi-nor";
- spi-max-frequency = <20000000>;
- reg = <1>;
- };
-};
-
-&gpio7 {
- sd2_driver_ena {
- gpio-hog;
- output-high;
- gpios = <8 GPIO_ACTIVE_HIGH>;
- };
-};
-
-&gpmi {
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_gpmi_nand>;
- status = "okay";
-};
-
-&can1 {
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_flexcan1>;
- status = "okay";
-};
-
-&can2 {
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_flexcan2>;
- status = "okay";
-};
-
-&usdhc1 {
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_usdhc1>;
- cd-gpios = <&gpio1 27 GPIO_ACTIVE_LOW>;
- no-1-8-v;
- status = "okay";
-};
-
-&usdhc2 {
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_usdhc2>;
- cd-gpios = <&gpio4 5 GPIO_ACTIVE_LOW>;
- wp-gpios = <&gpio2 10 GPIO_ACTIVE_HIGH>;
- no-1-8-v;
- status = "okay";
-};
-
-&iomuxc {
- pinctrl_ecspi1: ecspi1grp {
- fsl,pins = <
- MX6QDL_PAD_EIM_D17__ECSPI1_MISO 0x100b1
- MX6QDL_PAD_EIM_D18__ECSPI1_MOSI 0x100b1
- MX6QDL_PAD_EIM_D16__ECSPI1_SCLK 0x100b1
- MX6QDL_PAD_KEY_ROW1__GPIO4_IO09 0x100b1 /* SS0# */
- MX6QDL_PAD_KEY_COL2__GPIO4_IO10 0x100b1 /* SS1# */
- MX6QDL_PAD_KEY_ROW2__GPIO4_IO11 0x100b1 /* SS2# */
- >;
- };
-
- pinctrl_ecspi4: ecspi4grp {
- fsl,pins = <
- MX6QDL_PAD_EIM_D21__ECSPI4_SCLK 0x100b1
- MX6QDL_PAD_EIM_D22__ECSPI4_MISO 0x100b1
- MX6QDL_PAD_EIM_D28__ECSPI4_MOSI 0x100b1
- MX6QDL_PAD_EIM_D29__GPIO3_IO29 0x100b1 /* SS0# */
- MX6QDL_PAD_EIM_A25__GPIO5_IO02 0x100b1 /* SS1# */
- MX6QDL_PAD_SD4_DAT7__GPIO2_IO15 0x4001b0b0 /* WP pin */
- >;
- };
-
- pinctrl_gpio: gpiogrp {
- fsl,pins = <
- /* led enable */
- MX6QDL_PAD_ENET_CRS_DV__GPIO1_IO25 0x4001b0b0
- /* LCD power enable */
- MX6QDL_PAD_NANDF_CS2__GPIO6_IO15 0x4001b0b0
- /* led yellow */
- MX6QDL_PAD_NANDF_CS3__GPIO6_IO16 0x4001b0b0
- /* led red */
- MX6QDL_PAD_EIM_EB0__GPIO2_IO28 0x4001b0b0
- /* led green */
- MX6QDL_PAD_EIM_A24__GPIO5_IO04 0x4001b0b0
- /* led blue */
- MX6QDL_PAD_EIM_EB1__GPIO2_IO29 0x4001b0b0
- /* Profibus IRQ */
- MX6QDL_PAD_SD3_DAT5__GPIO7_IO00 0x1b0b0
- /* FPGA IRQ currently unused*/
- MX6QDL_PAD_SD3_DAT6__GPIO6_IO18 0x1b0b0
- /* Display reset because of clock failure */
- MX6QDL_PAD_SD4_DAT3__GPIO2_IO11 0x4001b0b0
- /* spi bus #2 SS driver enable */
- MX6QDL_PAD_EIM_A23__GPIO6_IO06 0x4001b0b0
- /* RST_LOC# PHY reset input (has pull-down!)*/
- MX6QDL_PAD_GPIO_18__GPIO7_IO13 0x4001b0b0
- /* USB_OTG_ID = GPIO1_24*/
- MX6QDL_PAD_ENET_RX_ER__USB_OTG_ID 0x4001b0b0
- /* Touchscreen IRQ */
- MX6QDL_PAD_SD4_DAT1__GPIO2_IO09 0x1b0b0
- /* PCIe reset */
- MX6QDL_PAD_EIM_A22__GPIO2_IO16 0x4001b0b0
- >;
- };
-
- pinctrl_gpmi_nand: gpmi-nand {
- fsl,pins = <
- MX6QDL_PAD_NANDF_CLE__NAND_CLE 0xb0b1
- MX6QDL_PAD_NANDF_ALE__NAND_ALE 0xb0b1
- MX6QDL_PAD_NANDF_WP_B__NAND_WP_B 0xb0b1
- MX6QDL_PAD_NANDF_RB0__NAND_READY_B 0xb000
- MX6QDL_PAD_NANDF_CS0__NAND_CE0_B 0xb0b1
- MX6QDL_PAD_SD4_CMD__NAND_RE_B 0xb0b1
- MX6QDL_PAD_SD4_CLK__NAND_WE_B 0xb0b1
- MX6QDL_PAD_NANDF_D0__NAND_DATA00 0xb0b1
- MX6QDL_PAD_NANDF_D1__NAND_DATA01 0xb0b1
- MX6QDL_PAD_NANDF_D2__NAND_DATA02 0xb0b1
- MX6QDL_PAD_NANDF_D3__NAND_DATA03 0xb0b1
- MX6QDL_PAD_NANDF_D4__NAND_DATA04 0xb0b1
- MX6QDL_PAD_NANDF_D5__NAND_DATA05 0xb0b1
- MX6QDL_PAD_NANDF_D6__NAND_DATA06 0xb0b1
- MX6QDL_PAD_NANDF_D7__NAND_DATA07 0xb0b1
- >;
- };
-
- pinctrl_flexcan1: flexcan1grp {
- fsl,pins = <
- MX6QDL_PAD_SD3_CLK__FLEXCAN1_RX 0x1b0b0
- MX6QDL_PAD_SD3_CMD__FLEXCAN1_TX 0x1b0b0
- >;
- };
-
- pinctrl_flexcan2: flexcan2grp {
- fsl,pins = <
- MX6QDL_PAD_SD3_DAT0__FLEXCAN2_TX 0x1b0b0
- MX6QDL_PAD_SD3_DAT1__FLEXCAN2_RX 0x1b0b0
- >;
- };
-
- pinctrl_usbotg: usbotggrp {
- fsl,pins = <
- MX6QDL_PAD_GPIO_1__USB_OTG_ID 0x17059
- >;
- };
-
- pinctrl_usdhc1: usdhc1grp {
- fsl,pins = <
- MX6QDL_PAD_SD1_CMD__SD1_CMD 0x17059
- MX6QDL_PAD_SD1_CLK__SD1_CLK 0x10059
- MX6QDL_PAD_SD1_DAT0__SD1_DATA0 0x17059
- MX6QDL_PAD_SD1_DAT1__SD1_DATA1 0x17059
- MX6QDL_PAD_SD1_DAT2__SD1_DATA2 0x17059
- MX6QDL_PAD_SD1_DAT3__SD1_DATA3 0x17059
- /* SD1 card detect input */
- MX6QDL_PAD_ENET_RXD0__GPIO1_IO27 0x1b0b0
- /* SD1 write protect input */
- MX6QDL_PAD_DI0_PIN4__GPIO4_IO20 0x1b0b0
- >;
- };
-
- pinctrl_usdhc2: usdhc2grp {
- fsl,pins = <
- MX6QDL_PAD_SD2_CMD__SD2_CMD 0x71
- MX6QDL_PAD_SD2_CLK__SD2_CLK 0x71
- MX6QDL_PAD_SD2_DAT0__SD2_DATA0 0x71
- MX6QDL_PAD_SD2_DAT1__SD2_DATA1 0x71
- MX6QDL_PAD_SD2_DAT2__SD2_DATA2 0x71
- MX6QDL_PAD_SD2_DAT3__SD2_DATA3 0x71
- /* SD2 level shifter output enable */
- MX6QDL_PAD_SD3_RST__GPIO7_IO08 0x4001b0b0
- /* SD2 card detect input */
- MX6QDL_PAD_GPIO_19__GPIO4_IO05 0x1b0b0
- /* SD2 write protect input */
- MX6QDL_PAD_SD4_DAT2__GPIO2_IO10 0x1b0b0
- >;
- };
-};
diff --git a/arch/arm/dts/imx6qdl-aristainetos2b-u-boot.dtsi b/arch/arm/dts/imx6qdl-aristainetos2b-u-boot.dtsi
deleted file mode 100644
index 88826a2..0000000
--- a/arch/arm/dts/imx6qdl-aristainetos2b-u-boot.dtsi
+++ /dev/null
@@ -1,77 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+ or X11
-/*
- * Copyright (C) 2019 Heiko Schocher <hs@denx.de>
- */
-
-/ {
- chosen {
- u-boot,dm-pre-reloc;
- stdout-path = &uart2;
- };
-
- wdt-reboot {
- compatible = "wdt-reboot";
- wdt = <&wdog1>;
- };
-};
-
-&uart2 {
- u-boot,dm-pre-reloc;
-};
-
-&pinctrl_gpio {
- u-boot,dm-pre-reloc;
-};
-
-&pinctrl_uart2 {
- u-boot,dm-pre-reloc;
-};
-
-&iomuxc {
- u-boot,dm-pre-reloc;
-};
-
-&aips2 {
- u-boot,dm-pre-reloc;
-};
-
-&backlight {
- pwms = <&pwm1 0 300000>;
- default-brightness-level = <2>;
-};
-
-/*
- * allow switching write protect / reset pin by gpio,
- * because "pinctrl-assert-gpios" from &ecspi1 isn't handled by u-boot
- */
-&gpio2 {
- u-boot,dm-pre-reloc;
-
- wp_spi_nor {
- gpio-hog;
- output-high;
- gpios = <15 GPIO_ACTIVE_HIGH>;
- };
-
- reset_spi_nor {
- gpio-hog;
- output-high;
- gpios = <28 GPIO_ACTIVE_HIGH>;
- };
-};
-
-&gpio4 {
- u-boot,dm-pre-reloc;
-};
-
-&ecspi1 {
- u-boot,dm-pre-reloc;
-};
-
-&flash {
- u-boot,dm-pre-reloc;
-};
-
-&pinctrl_ecspi1 {
- u-boot,dm-pre-reloc;
-};
diff --git a/arch/arm/dts/imx6qdl-aristainetos2b.dtsi b/arch/arm/dts/imx6qdl-aristainetos2b.dtsi
deleted file mode 100644
index 7d92ea2..0000000
--- a/arch/arm/dts/imx6qdl-aristainetos2b.dtsi
+++ /dev/null
@@ -1,266 +0,0 @@
-// SPDX-License-Identifier: (GPL-2.0)
-/*
- * support for the imx6 based aristainetos2b board
- *
- * Copyright (C) 2019 Heiko Schocher <hs@denx.de>
- * Copyright (C) 2015 Heiko Schocher <hs@denx.de>
- *
- */
-#include <dt-bindings/gpio/gpio.h>
-#include <dt-bindings/clock/imx6qdl-clock.h>
-
-#include "imx6qdl-aristainetos2-common.dtsi"
-
-/ {
- leds {
- compatible = "gpio-leds";
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_gpio>;
-
- LED_blue {
- label = "led_blue";
- gpios = <&gpio2 29 GPIO_ACTIVE_HIGH>;
- };
-
- LED_green {
- label = "led_green";
- gpios = <&gpio5 4 GPIO_ACTIVE_HIGH>;
- };
-
- LED_red {
- label = "led_red";
- gpios = <&gpio5 0 GPIO_ACTIVE_HIGH>;
- };
-
- LED_yellow {
- label = "led_yellow";
- gpios = <&gpio6 16 GPIO_ACTIVE_HIGH>;
- };
-
- LED_ena {
- label = "led_ena";
- gpios = <&gpio1 25 GPIO_ACTIVE_LOW>;
- };
- };
-};
-
-&ecspi1 {
- fsl,spi-num-chipselects = <3>;
- cs-gpios = <&gpio2 30 GPIO_ACTIVE_HIGH
- &gpio4 10 GPIO_ACTIVE_HIGH
- &gpio4 11 GPIO_ACTIVE_HIGH>;
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_ecspi1>;
- status = "okay";
- pinctrl-assert-gpios = <&gpio2 28 GPIO_ACTIVE_HIGH>;
- pinctrl-assert-gpios = <&gpio2 15 GPIO_ACTIVE_HIGH>;
-
- flash: m25p80@0 {
- #address-cells = <1>;
- #size-cells = <1>;
- compatible = "micron,n25q128a11", "jedec,spi-nor";
- spi-max-frequency = <20000000>;
- reg = <0>;
- };
-};
-
-&ecspi4 {
- fsl,spi-num-chipselects = <2>;
- cs-gpios = <&gpio3 29 GPIO_ACTIVE_HIGH &gpio5 2 GPIO_ACTIVE_HIGH>;
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_ecspi4>;
- status = "okay";
-};
-
-&i2c1 {
- tpm@20 {
- compatible = "infineon,slb9645tt";
- reg = <0x20>;
- };
-};
-
-&gpio7 {
- sd2_driver_ena {
- gpio-hog;
- output-high;
- gpios = <8 GPIO_ACTIVE_HIGH>;
- };
-};
-
-&gpmi {
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_gpmi_nand>;
- status = "okay";
-};
-
-&can1 {
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_flexcan1>;
- status = "okay";
-};
-
-&can2 {
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_flexcan2>;
- status = "okay";
-};
-
-&usdhc1 {
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_usdhc1>;
- cd-gpios = <&gpio1 27 GPIO_ACTIVE_LOW>;
- wp-gpios = <&gpio4 20 GPIO_ACTIVE_HIGH>;
- no-1-8-v;
- status = "okay";
-};
-
-&usdhc2 {
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_usdhc2>;
- /*
- * comment out this line to make the WiFi Eval-Module work in
- * SD-Slot2, and add line:
- * broken-cd;
- * causes 6% CPU load if no WiFi module installed (polling)
- */
- cd-gpios = <&gpio4 5 GPIO_ACTIVE_LOW>;
- wp-gpios = <&gpio2 10 GPIO_ACTIVE_HIGH>;
- no-1-8-v;
- status = "okay";
-};
-
-&iomuxc {
- pinctrl_ecspi1: ecspi1grp {
- fsl,pins = <
- MX6QDL_PAD_EIM_D17__ECSPI1_MISO 0x100b1
- MX6QDL_PAD_EIM_D18__ECSPI1_MOSI 0x100b1
- MX6QDL_PAD_EIM_D16__ECSPI1_SCLK 0x100b1
- /* SS0# */
- MX6QDL_PAD_EIM_EB2__GPIO2_IO30 0x100b1
- /* SS1# */
- MX6QDL_PAD_KEY_COL2__GPIO4_IO10 0x100b1
- /* SS2# */
- MX6QDL_PAD_KEY_ROW2__GPIO4_IO11 0x100b1
- /* WP pin NOR Flash */
- MX6QDL_PAD_SD4_DAT7__GPIO2_IO15 0x4001b0b0
- /* Flash nReset */
- MX6QDL_PAD_EIM_EB0__GPIO2_IO28 0x4001b0b0
- >;
- };
-
- pinctrl_ecspi4: ecspi4grp {
- fsl,pins = <
- MX6QDL_PAD_EIM_D21__ECSPI4_SCLK 0x100b1
- MX6QDL_PAD_EIM_D22__ECSPI4_MISO 0x100b1
- MX6QDL_PAD_EIM_D28__ECSPI4_MOSI 0x100b1
- MX6QDL_PAD_EIM_D29__GPIO3_IO29 0x100b1 /* SS0# */
- MX6QDL_PAD_EIM_A25__GPIO5_IO02 0x100b1 /* SS1# */
- >;
- };
-
- pinctrl_gpio: gpiogrp {
- fsl,pins = <
- /* led enable */
- MX6QDL_PAD_ENET_CRS_DV__GPIO1_IO25 0x4001b0b0
- /* LCD power enable */
- MX6QDL_PAD_NANDF_CS2__GPIO6_IO15 0x4001b0b0
- /* led yellow */
- MX6QDL_PAD_NANDF_CS3__GPIO6_IO16 0x4001b0b0
- /* led red */
- MX6QDL_PAD_EIM_WAIT__GPIO5_IO00 0x4001b0b0
- /* led green */
- MX6QDL_PAD_EIM_A24__GPIO5_IO04 0x4001b0b0
- /* led blue */
- MX6QDL_PAD_EIM_EB1__GPIO2_IO29 0x4001b0b0
- /* Profibus IRQ */
- MX6QDL_PAD_SD3_DAT5__GPIO7_IO00 0x1b0b0
- /* FPGA IRQ currently unused*/
- MX6QDL_PAD_SD3_DAT6__GPIO6_IO18 0x1b0b0
- /* Display reset because of clock failure */
- MX6QDL_PAD_SD4_DAT3__GPIO2_IO11 0x4001b0b0
- /* spi bus #2 SS driver enable */
- MX6QDL_PAD_EIM_A23__GPIO6_IO06 0x4001b0b0
- /* RST_LOC# PHY reset input (has pull-down!)*/
- MX6QDL_PAD_GPIO_18__GPIO7_IO13 0x4001b0b0
- /* Touchscreen IRQ */
- MX6QDL_PAD_SD4_DAT1__GPIO2_IO09 0x1b0b0
- /* PCIe reset */
- MX6QDL_PAD_EIM_A22__GPIO2_IO16 0x4001b0b0
- /* make sure pin is GPIO and not ENET_REF_CLK */
- MX6QDL_PAD_GPIO_16__GPIO7_IO11 0x4001a0b0
- /* SD2 level shifter output enable / SD2 Reset# */
- MX6QDL_PAD_SD3_RST__GPIO7_IO08 0x4001b0b0
- >;
- };
-
- pinctrl_gpmi_nand: gpmi-nand {
- fsl,pins = <
- MX6QDL_PAD_NANDF_CLE__NAND_CLE 0xb0b1
- MX6QDL_PAD_NANDF_ALE__NAND_ALE 0xb0b1
- MX6QDL_PAD_NANDF_WP_B__NAND_WP_B 0xb0b1
- MX6QDL_PAD_NANDF_RB0__NAND_READY_B 0xb000
- MX6QDL_PAD_NANDF_CS0__NAND_CE0_B 0xb0b1
- MX6QDL_PAD_SD4_CMD__NAND_RE_B 0xb0b1
- MX6QDL_PAD_SD4_CLK__NAND_WE_B 0xb0b1
- MX6QDL_PAD_NANDF_D0__NAND_DATA00 0xb0b1
- MX6QDL_PAD_NANDF_D1__NAND_DATA01 0xb0b1
- MX6QDL_PAD_NANDF_D2__NAND_DATA02 0xb0b1
- MX6QDL_PAD_NANDF_D3__NAND_DATA03 0xb0b1
- MX6QDL_PAD_NANDF_D4__NAND_DATA04 0xb0b1
- MX6QDL_PAD_NANDF_D5__NAND_DATA05 0xb0b1
- MX6QDL_PAD_NANDF_D6__NAND_DATA06 0xb0b1
- MX6QDL_PAD_NANDF_D7__NAND_DATA07 0xb0b1
- >;
- };
-
- pinctrl_flexcan1: flexcan1grp {
- fsl,pins = <
- MX6QDL_PAD_SD3_CLK__FLEXCAN1_RX 0x1b0b0
- MX6QDL_PAD_SD3_CMD__FLEXCAN1_TX 0x1b0b0
- >;
- };
-
- pinctrl_flexcan2: flexcan2grp {
- fsl,pins = <
- MX6QDL_PAD_SD3_DAT0__FLEXCAN2_TX 0x1b0b0
- MX6QDL_PAD_SD3_DAT1__FLEXCAN2_RX 0x1b0b0
- >;
- };
-
- pinctrl_usbotg: usbotggrp {
- fsl,pins = <
- MX6QDL_PAD_ENET_RX_ER__USB_OTG_ID 0x17059
- MX6QDL_PAD_KEY_COL4__USB_OTG_OC 0x1b0b0
- >;
- };
-
- pinctrl_usdhc1: usdhc1grp {
- fsl,pins = <
- MX6QDL_PAD_SD1_CMD__SD1_CMD 0x17059
- MX6QDL_PAD_SD1_CLK__SD1_CLK 0x10059
- MX6QDL_PAD_SD1_DAT0__SD1_DATA0 0x17059
- MX6QDL_PAD_SD1_DAT1__SD1_DATA1 0x17059
- MX6QDL_PAD_SD1_DAT2__SD1_DATA2 0x17059
- MX6QDL_PAD_SD1_DAT3__SD1_DATA3 0x17059
- /* SD1 card detect input */
- MX6QDL_PAD_ENET_RXD0__GPIO1_IO27 0x1b0b0
- /* SD1 write protect input */
- MX6QDL_PAD_DI0_PIN4__GPIO4_IO20 0x1b0b0
- >;
- };
-
- pinctrl_usdhc2: usdhc2grp {
- fsl,pins = <
- MX6QDL_PAD_SD2_CMD__SD2_CMD 0x71
- MX6QDL_PAD_SD2_CLK__SD2_CLK 0x71
- MX6QDL_PAD_SD2_DAT0__SD2_DATA0 0x71
- MX6QDL_PAD_SD2_DAT1__SD2_DATA1 0x71
- MX6QDL_PAD_SD2_DAT2__SD2_DATA2 0x71
- MX6QDL_PAD_SD2_DAT3__SD2_DATA3 0x71
- /* SD2 card detect input */
- MX6QDL_PAD_GPIO_19__GPIO4_IO05 0x1b0b0
- /* SD2 write protect input */
- MX6QDL_PAD_SD4_DAT2__GPIO2_IO10 0x1b0b0
- >;
- };
-};
diff --git a/arch/arm/dts/imx6qdl-aristainetos2c.dtsi b/arch/arm/dts/imx6qdl-aristainetos2c.dtsi
index ba13d55..70c0177 100644
--- a/arch/arm/dts/imx6qdl-aristainetos2c.dtsi
+++ b/arch/arm/dts/imx6qdl-aristainetos2c.dtsi
@@ -1,6 +1,6 @@
// SPDX-License-Identifier: (GPL-2.0)
/*
- * support for the imx6 based aristainetos2c board
+ * support for the imx6 based aristainetos2c+2d boards
*
* Copyright (C) 2019 Heiko Schocher <hs@denx.de>
* Copyright (C) 2015 Heiko Schocher <hs@denx.de>
@@ -79,6 +79,14 @@
};
};
+&gpio7 {
+ eMMC_reset {
+ gpio-hog;
+ output-high;
+ gpios = <8 GPIO_ACTIVE_HIGH>;
+ };
+};
+
&can1 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_flexcan1>;
@@ -172,6 +180,8 @@
MX6QDL_PAD_EIM_A21__GPIO2_IO17 0x4001b0b0
/* TPM Reset */
MX6QDL_PAD_EIM_A20__GPIO2_IO18 0x4001b0b0
+ /* eMMC Reset# */
+ MX6QDL_PAD_SD3_RST__GPIO7_IO08 0x4001b0b0
>;
};
diff --git a/arch/arm/dts/imx6qdl-aristainetos2b_csl-u-boot.dtsi b/arch/arm/dts/imx6qdl-aristainetos2c_cslb-u-boot.dtsi
similarity index 100%
rename from arch/arm/dts/imx6qdl-aristainetos2b_csl-u-boot.dtsi
rename to arch/arm/dts/imx6qdl-aristainetos2c_cslb-u-boot.dtsi
diff --git a/arch/arm/dts/imx6qdl-aristainetos2b_csl.dtsi b/arch/arm/dts/imx6qdl-aristainetos2c_cslb.dtsi
similarity index 80%
rename from arch/arm/dts/imx6qdl-aristainetos2b_csl.dtsi
rename to arch/arm/dts/imx6qdl-aristainetos2c_cslb.dtsi
index fa4dade..c3724ec 100644
--- a/arch/arm/dts/imx6qdl-aristainetos2b_csl.dtsi
+++ b/arch/arm/dts/imx6qdl-aristainetos2c_cslb.dtsi
@@ -1,6 +1,6 @@
// SPDX-License-Identifier: (GPL-2.0)
/*
- * support for the imx6 based aristainetos2b-csl board
+ * support for the imx6 based aristainetos2c-cslb board
*
* Copyright (C) 2019 Heiko Schocher <hs@denx.de>
* Copyright (C) 2015 Heiko Schocher <hs@denx.de>
@@ -104,19 +104,13 @@
};
&gpio7 {
- wlan_reset {
+ eMMC_reset {
gpio-hog;
output-high;
gpios = <8 GPIO_ACTIVE_HIGH>;
};
};
-&gpmi {
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_gpmi_nand>;
- status = "okay";
-};
-
&usdhc1 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_usdhc1>;
@@ -127,7 +121,9 @@
&usdhc2 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_usdhc2>;
+ bus-width = <8>;
no-1-8-v;
+ non-removable;
status = "okay";
};
@@ -190,31 +186,15 @@
MX6QDL_PAD_EIM_A22__GPIO2_IO16 0x4001b0b0
/* make sure pin is GPIO and not ENET_REF_CLK */
MX6QDL_PAD_GPIO_16__GPIO7_IO11 0x4001a0b0
- /* WLAN Module Reset# */
+ /* TPM PP */
+ MX6QDL_PAD_EIM_A21__GPIO2_IO17 0x4001b0b0
+ /* TPM Reset */
+ MX6QDL_PAD_EIM_A20__GPIO2_IO18 0x4001b0b0
+ /* eMMC Reset# */
MX6QDL_PAD_SD3_RST__GPIO7_IO08 0x4001b0b0
>;
};
- pinctrl_gpmi_nand: gpmi-nand {
- fsl,pins = <
- MX6QDL_PAD_NANDF_CLE__NAND_CLE 0xb0b1
- MX6QDL_PAD_NANDF_ALE__NAND_ALE 0xb0b1
- MX6QDL_PAD_NANDF_WP_B__NAND_WP_B 0xb0b1
- MX6QDL_PAD_NANDF_RB0__NAND_READY_B 0xb000
- MX6QDL_PAD_NANDF_CS0__NAND_CE0_B 0xb0b1
- MX6QDL_PAD_SD4_CMD__NAND_RE_B 0xb0b1
- MX6QDL_PAD_SD4_CLK__NAND_WE_B 0xb0b1
- MX6QDL_PAD_NANDF_D0__NAND_DATA00 0xb0b1
- MX6QDL_PAD_NANDF_D1__NAND_DATA01 0xb0b1
- MX6QDL_PAD_NANDF_D2__NAND_DATA02 0xb0b1
- MX6QDL_PAD_NANDF_D3__NAND_DATA03 0xb0b1
- MX6QDL_PAD_NANDF_D4__NAND_DATA04 0xb0b1
- MX6QDL_PAD_NANDF_D5__NAND_DATA05 0xb0b1
- MX6QDL_PAD_NANDF_D6__NAND_DATA06 0xb0b1
- MX6QDL_PAD_NANDF_D7__NAND_DATA07 0xb0b1
- >;
- };
-
pinctrl_usbotg: usbotggrp {
fsl,pins = <
MX6QDL_PAD_ENET_RX_ER__USB_OTG_ID 0x17059
@@ -237,12 +217,16 @@
pinctrl_usdhc2: usdhc2grp {
fsl,pins = <
- MX6QDL_PAD_SD2_CMD__SD2_CMD 0x71
- MX6QDL_PAD_SD2_CLK__SD2_CLK 0x71
- MX6QDL_PAD_SD2_DAT0__SD2_DATA0 0x71
- MX6QDL_PAD_SD2_DAT1__SD2_DATA1 0x71
- MX6QDL_PAD_SD2_DAT2__SD2_DATA2 0x71
- MX6QDL_PAD_SD2_DAT3__SD2_DATA3 0x71
+ MX6QDL_PAD_SD2_CMD__SD2_CMD 0x17059
+ MX6QDL_PAD_SD2_CLK__SD2_CLK 0x10059
+ MX6QDL_PAD_SD2_DAT0__SD2_DATA0 0x17059
+ MX6QDL_PAD_SD2_DAT1__SD2_DATA1 0x17059
+ MX6QDL_PAD_SD2_DAT2__SD2_DATA2 0x17059
+ MX6QDL_PAD_SD2_DAT3__SD2_DATA3 0x17059
+ MX6QDL_PAD_NANDF_D4__SD2_DATA4 0x17059
+ MX6QDL_PAD_NANDF_D5__SD2_DATA5 0x17059
+ MX6QDL_PAD_NANDF_D6__SD2_DATA6 0x17059
+ MX6QDL_PAD_NANDF_D7__SD2_DATA7 0x17059
>;
};
};
diff --git a/arch/arm/dts/imx8mm-verdin-u-boot.dtsi b/arch/arm/dts/imx8mm-verdin-u-boot.dtsi
index fe6bb9b..249b0f8 100644
--- a/arch/arm/dts/imx8mm-verdin-u-boot.dtsi
+++ b/arch/arm/dts/imx8mm-verdin-u-boot.dtsi
@@ -2,7 +2,6 @@
/*
* Copyright 2020 Toradex
*/
-
/ {
wdt-reboot {
compatible = "wdt-reboot";
@@ -90,11 +89,11 @@
u-boot,dm-spl;
};
-&{/soc@0/bus@30800000/i2c@30a20000/pmic@4b} {
+&{/soc@0/bus@30800000/i2c@30a20000/pmic} {
u-boot,dm-spl;
};
-&{/soc@0/bus@30800000/i2c@30a20000/pmic@4b/regulators} {
+&{/soc@0/bus@30800000/i2c@30a20000/pmic/regulators} {
u-boot,dm-spl;
};
diff --git a/arch/arm/dts/imx8mm-verdin.dts b/arch/arm/dts/imx8mm-verdin.dts
index 1c67c08..fb0756d 100644
--- a/arch/arm/dts/imx8mm-verdin.dts
+++ b/arch/arm/dts/imx8mm-verdin.dts
@@ -203,115 +203,123 @@
pinctrl-0 = <&pinctrl_i2c1>;
status = "okay";
- pmic@4b {
- compatible = "rohm,bd71840", "rohm,bd71837";
- bd71837,pmic-buck2-uses-i2c-dvs;
- bd71837,pmic-buck2-dvs-voltage = <1000000>, <900000>, <0>; /* VDD_ARM: Run-Idle */
- gpio_intr = <&gpio1 3 GPIO_ACTIVE_LOW>;
- /* PMIC BD71837 PMIC_nINT GPIO1_IO3 */
+ /* Assembled on V1.1 HW and later */
+ pmic {
+ reg = <0x25>;
+ u-boot,dm-spl;
+ compatible = "nxp,pca9450a";
+ /* PMIC PCA9450 PMIC_nINT GPIO1_IO3 */
pinctrl-0 = <&pinctrl_pmic>;
- reg = <0x4b>;
-
- gpo {
- rohm,drv = <0x0C>; /* 0b0000_1100 all gpos with cmos output mode */
- };
+ gpio_intr = <&gpio1 3 GPIO_ACTIVE_LOW>;
regulators {
- buck1_reg: BUCK1 {
- regulator-always-on;
- regulator-boot-on;
+ u-boot,dm-spl;
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ pca9450,pmic-buck2-uses-i2c-dvs;
+ /* Run/Standby voltage */
+ pca9450,pmic-buck2-dvs-voltage = <950000>, <850000>;
+
+ buck1_reg: regulator@0 {
+ reg = <0>;
regulator-compatible = "buck1";
- regulator-max-microvolt = <1300000>;
- regulator-min-microvolt = <700000>;
- regulator-ramp-delay = <1250>;
+ regulator-min-microvolt = <600000>;
+ regulator-max-microvolt = <2187500>;
+ regulator-boot-on;
+ regulator-always-on;
+ regulator-ramp-delay = <3125>;
};
- buck2_reg: BUCK2 {
- regulator-always-on;
- regulator-boot-on;
+ buck2_reg: regulator@1 {
+ reg = <1>;
regulator-compatible = "buck2";
- regulator-max-microvolt = <1300000>;
- regulator-min-microvolt = <700000>;
- regulator-ramp-delay = <1250>;
+ regulator-min-microvolt = <600000>;
+ regulator-max-microvolt = <2187500>;
+ regulator-boot-on;
+ regulator-always-on;
+ regulator-ramp-delay = <3125>;
};
- buck5_reg: BUCK5 {
- regulator-always-on;
+ buck3_reg: regulator@2 {
+ reg = <2>;
+ regulator-compatible = "buck3";
+ regulator-min-microvolt = <600000>;
+ regulator-max-microvolt = <2187500>;
regulator-boot-on;
- regulator-compatible = "buck5";
- regulator-max-microvolt = <1350000>;
- regulator-min-microvolt = <700000>;
+ regulator-always-on;
};
- buck6_reg: BUCK6 {
- regulator-always-on;
+ buck4_reg: regulator@3 {
+ reg = <3>;
+ regulator-compatible = "buck4";
+ regulator-min-microvolt = <600000>;
+ regulator-max-microvolt = <3400000>;
regulator-boot-on;
- regulator-compatible = "buck6";
- regulator-max-microvolt = <3300000>;
- regulator-min-microvolt = <3000000>;
+ regulator-always-on;
};
- buck7_reg: BUCK7 {
- regulator-always-on;
+ buck5_reg: regulator@4 {
+ reg = <4>;
+ regulator-compatible = "buck5";
+ regulator-min-microvolt = <600000>;
+ regulator-max-microvolt = <3400000>;
regulator-boot-on;
- regulator-compatible = "buck7";
- regulator-max-microvolt = <1995000>;
- regulator-min-microvolt = <1605000>;
+ regulator-always-on;
};
- buck8_reg: BUCK8 {
- regulator-always-on;
+ buck6_reg: regulator@5 {
+ reg = <5>;
+ regulator-compatible = "buck6";
+ regulator-min-microvolt = <600000>;
+ regulator-max-microvolt = <3400000>;
regulator-boot-on;
- regulator-compatible = "buck8";
- regulator-max-microvolt = <1400000>;
- regulator-min-microvolt = <800000>;
+ regulator-always-on;
};
- ldo1_reg: LDO1 {
- regulator-always-on;
- regulator-boot-on;
+ ldo1_reg: regulator@6 {
+ reg = <6>;
regulator-compatible = "ldo1";
+ regulator-min-microvolt = <1600000>;
regulator-max-microvolt = <3300000>;
- regulator-min-microvolt = <3000000>;
+ regulator-boot-on;
+ regulator-always-on;
};
- ldo2_reg: LDO2 {
- regulator-always-on;
- regulator-boot-on;
+ ldo2_reg: regulator@7 {
+ reg = <7>;
regulator-compatible = "ldo2";
- regulator-max-microvolt = <900000>;
- regulator-min-microvolt = <900000>;
+ regulator-min-microvolt = <800000>;
+ regulator-max-microvolt = <1150000>;
+ regulator-boot-on;
+ regulator-always-on;
};
- ldo3_reg: LDO3 {
- regulator-always-on;
- regulator-boot-on;
+ ldo3_reg: regulator@8 {
+ reg = <8>;
regulator-compatible = "ldo3";
+ regulator-min-microvolt = <800000>;
regulator-max-microvolt = <3300000>;
- regulator-min-microvolt = <1800000>;
+ regulator-boot-on;
+ regulator-always-on;
};
- ldo4_reg: LDO4 {
- regulator-always-on;
- regulator-boot-on;
+ ldo4_reg: regulator@9 {
+ reg = <9>;
regulator-compatible = "ldo4";
- regulator-max-microvolt = <1800000>;
- regulator-min-microvolt = <900000>;
+ regulator-min-microvolt = <800000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-boot-on;
+ regulator-always-on;
};
- ldo5_reg: LDO5 {
+ ldo5_reg: regulator@10 {
+ reg = <10>;
regulator-compatible = "ldo5";
+ regulator-min-microvolt = <800000>;
regulator-max-microvolt = <3300000>;
- regulator-min-microvolt = <3300000>;
};
- ldo6_reg: LDO6 {
- regulator-always-on;
- regulator-boot-on;
- regulator-compatible = "ldo6";
- regulator-max-microvolt = <1800000>;
- regulator-min-microvolt = <900000>;
- };
};
};
@@ -321,12 +329,6 @@
reg = <0x32>;
};
- adc@34 {
- compatible = "maxim,max11607";
- reg = <0x34>;
- vcc-supply = <&ldo5_reg>;
- };
-
eeprom_module: eeprom@50 {
compatible = "st,24c02", "atmel,24c02", "i2c-eeprom";
pagesize = <16>;
diff --git a/arch/arm/include/asm/mach-imx/sys_proto.h b/arch/arm/include/asm/mach-imx/sys_proto.h
index 5f0c1ae..43eae6d 100644
--- a/arch/arm/include/asm/mach-imx/sys_proto.h
+++ b/arch/arm/include/asm/mach-imx/sys_proto.h
@@ -183,6 +183,11 @@
void init_snvs(void);
void imx_wdog_disable_powerdown(void);
+void board_mem_get_layout(u64 *phys_sdram_1_start,
+ u64 *phys_sdram_1_size,
+ u64 *phys_sdram_2_start,
+ u64 *phys_sdram_2_size);
+
int arch_auxiliary_core_check_up(u32 core_id);
int board_mmc_get_env_dev(int devno);
diff --git a/arch/arm/mach-imx/imx8/Kconfig b/arch/arm/mach-imx/imx8/Kconfig
index 9d1f73d..04b9729 100644
--- a/arch/arm/mach-imx/imx8/Kconfig
+++ b/arch/arm/mach-imx/imx8/Kconfig
@@ -65,6 +65,11 @@
select BOARD_LATE_INIT
select IMX8QXP
+config TARGET_APALIS_IMX8X
+ bool "Support Apalis iMX8X module"
+ select BOARD_LATE_INIT
+ select IMX8QXP
+
config TARGET_DENEB
bool "Support i.MX8QXP Capricorn Deneb board"
select BOARD_LATE_INIT
@@ -98,6 +103,7 @@
source "board/advantech/imx8qm_rom7720_a1/Kconfig"
source "board/toradex/apalis-imx8/Kconfig"
source "board/toradex/colibri-imx8x/Kconfig"
+source "board/toradex/apalis-imx8x/Kconfig"
source "board/siemens/capricorn/Kconfig"
config IMX_SNVS_SEC_SC
diff --git a/arch/arm/mach-imx/imx8/ahab.c b/arch/arm/mach-imx/imx8/ahab.c
index 5dbe1d5..4bb7c46 100644
--- a/arch/arm/mach-imx/imx8/ahab.c
+++ b/arch/arm/mach-imx/imx8/ahab.c
@@ -14,6 +14,7 @@
#include <asm/arch/sys_proto.h>
#include <asm/arch/image.h>
#include <console.h>
+#include <cpu_func.h>
DECLARE_GLOBAL_DATA_PTR;
@@ -92,7 +93,7 @@
sizeof(struct container_hdr) +
i * sizeof(struct boot_img_t));
- debug("img %d, dst 0x%x, src 0x%x, size 0x%x\n",
+ debug("img %d, dst 0x%x, src 0x%lux, size 0x%x\n",
i, (uint32_t) img->dst, img->offset + addr, img->size);
memcpy((void *)img->dst, (const void *)(img->offset + addr),
@@ -106,7 +107,7 @@
/* Find the memreg and set permission for seco pt */
err = sc_rm_find_memreg(-1, &mr, s, e);
if (err) {
- printf("Error: can't find memreg for image load address 0x%x, error %d\n", img->dst, err);
+ printf("Error: can't find memreg for image load address 0x%llx, error %d\n", img->dst, err);
ret = -ENOMEM;
goto exit;
}
diff --git a/arch/arm/mach-imx/imx8/cpu.c b/arch/arm/mach-imx/imx8/cpu.c
index 38b2c09..911d6a5 100644
--- a/arch/arm/mach-imx/imx8/cpu.c
+++ b/arch/arm/mach-imx/imx8/cpu.c
@@ -260,14 +260,30 @@
return -EINVAL;
}
+__weak void board_mem_get_layout(u64 *phys_sdram_1_start,
+ u64 *phys_sdram_1_size,
+ u64 *phys_sdram_2_start,
+ u64 *phys_sdram_2_size)
+{
+ *phys_sdram_1_start = PHYS_SDRAM_1;
+ *phys_sdram_1_size = PHYS_SDRAM_1_SIZE;
+ *phys_sdram_2_start = PHYS_SDRAM_2;
+ *phys_sdram_2_size = PHYS_SDRAM_2_SIZE;
+}
+
phys_size_t get_effective_memsize(void)
{
sc_rm_mr_t mr;
sc_faddr_t start, end, end1, start_aligned;
+ u64 phys_sdram_1_start, phys_sdram_1_size;
+ u64 phys_sdram_2_start, phys_sdram_2_size;
int err;
+ board_mem_get_layout(&phys_sdram_1_start, &phys_sdram_1_size,
+ &phys_sdram_2_start, &phys_sdram_2_size);
+
- end1 = (sc_faddr_t)PHYS_SDRAM_1 + PHYS_SDRAM_1_SIZE;
+ end1 = (sc_faddr_t)phys_sdram_1_start + phys_sdram_1_size;
for (mr = 0; mr < 64; mr++) {
err = get_owned_memreg(mr, &start, &end);
if (!err) {
@@ -277,29 +293,35 @@
continue;
/* Find the memory region runs the U-Boot */
- if (start >= PHYS_SDRAM_1 && start <= end1 &&
+ if (start >= phys_sdram_1_start && start <= end1 &&
(start <= CONFIG_SYS_TEXT_BASE &&
end >= CONFIG_SYS_TEXT_BASE)) {
- if ((end + 1) <= ((sc_faddr_t)PHYS_SDRAM_1 +
- PHYS_SDRAM_1_SIZE))
- return (end - PHYS_SDRAM_1 + 1);
+ if ((end + 1) <=
+ ((sc_faddr_t)phys_sdram_1_start +
+ phys_sdram_1_size))
+ return (end - phys_sdram_1_start + 1);
else
- return PHYS_SDRAM_1_SIZE;
+ return phys_sdram_1_size;
}
}
}
- return PHYS_SDRAM_1_SIZE;
+ return phys_sdram_1_size;
}
int dram_init(void)
{
sc_rm_mr_t mr;
sc_faddr_t start, end, end1, end2;
+ u64 phys_sdram_1_start, phys_sdram_1_size;
+ u64 phys_sdram_2_start, phys_sdram_2_size;
int err;
- end1 = (sc_faddr_t)PHYS_SDRAM_1 + PHYS_SDRAM_1_SIZE;
- end2 = (sc_faddr_t)PHYS_SDRAM_2 + PHYS_SDRAM_2_SIZE;
+ board_mem_get_layout(&phys_sdram_1_start, &phys_sdram_1_size,
+ &phys_sdram_2_start, &phys_sdram_2_size);
+
+ end1 = (sc_faddr_t)phys_sdram_1_start + phys_sdram_1_size;
+ end2 = (sc_faddr_t)phys_sdram_2_start + phys_sdram_2_size;
for (mr = 0; mr < 64; mr++) {
err = get_owned_memreg(mr, &start, &end);
if (!err) {
@@ -308,12 +330,13 @@
if (start > end)
continue;
- if (start >= PHYS_SDRAM_1 && start <= end1) {
+ if (start >= phys_sdram_1_start && start <= end1) {
if ((end + 1) <= end1)
gd->ram_size += end - start + 1;
else
gd->ram_size += end1 - start;
- } else if (start >= PHYS_SDRAM_2 && start <= end2) {
+ } else if (start >= phys_sdram_2_start &&
+ start <= end2) {
if ((end + 1) <= end2)
gd->ram_size += end - start + 1;
else
@@ -324,8 +347,8 @@
/* If error, set to the default value */
if (!gd->ram_size) {
- gd->ram_size = PHYS_SDRAM_1_SIZE;
- gd->ram_size += PHYS_SDRAM_2_SIZE;
+ gd->ram_size = phys_sdram_1_size;
+ gd->ram_size += phys_sdram_2_size;
}
return 0;
}
@@ -358,11 +381,15 @@
sc_rm_mr_t mr;
sc_faddr_t start, end, end1, end2;
int i = 0;
+ u64 phys_sdram_1_start, phys_sdram_1_size;
+ u64 phys_sdram_2_start, phys_sdram_2_size;
int err;
- end1 = (sc_faddr_t)PHYS_SDRAM_1 + PHYS_SDRAM_1_SIZE;
- end2 = (sc_faddr_t)PHYS_SDRAM_2 + PHYS_SDRAM_2_SIZE;
+ board_mem_get_layout(&phys_sdram_1_start, &phys_sdram_1_size,
+ &phys_sdram_2_start, &phys_sdram_2_size);
+ end1 = (sc_faddr_t)phys_sdram_1_start + phys_sdram_1_size;
+ end2 = (sc_faddr_t)phys_sdram_2_start + phys_sdram_2_size;
for (mr = 0; mr < 64 && i < CONFIG_NR_DRAM_BANKS; mr++) {
err = get_owned_memreg(mr, &start, &end);
if (!err) {
@@ -370,7 +397,7 @@
if (start > end) /* Small memory region, no use it */
continue;
- if (start >= PHYS_SDRAM_1 && start <= end1) {
+ if (start >= phys_sdram_1_start && start <= end1) {
gd->bd->bi_dram[i].start = start;
if ((end + 1) <= end1)
@@ -381,7 +408,7 @@
dram_bank_sort(i);
i++;
- } else if (start >= PHYS_SDRAM_2 && start <= end2) {
+ } else if (start >= phys_sdram_2_start && start <= end2) {
gd->bd->bi_dram[i].start = start;
if ((end + 1) <= end2)
@@ -398,10 +425,10 @@
/* If error, set to the default value */
if (!i) {
- gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
- gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE;
- gd->bd->bi_dram[1].start = PHYS_SDRAM_2;
- gd->bd->bi_dram[1].size = PHYS_SDRAM_2_SIZE;
+ gd->bd->bi_dram[0].start = phys_sdram_1_start;
+ gd->bd->bi_dram[0].size = phys_sdram_1_size;
+ gd->bd->bi_dram[1].start = phys_sdram_2_start;
+ gd->bd->bi_dram[1].size = phys_sdram_2_size;
}
return 0;
@@ -411,11 +438,16 @@
{
u64 attr = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | PTE_BLOCK_NON_SHARE |
PTE_BLOCK_PXN | PTE_BLOCK_UXN;
+ u64 phys_sdram_1_start, phys_sdram_1_size;
+ u64 phys_sdram_2_start, phys_sdram_2_size;
+
+ board_mem_get_layout(&phys_sdram_1_start, &phys_sdram_1_size,
+ &phys_sdram_2_start, &phys_sdram_2_size);
- if ((addr_start >= PHYS_SDRAM_1 &&
- addr_start <= ((sc_faddr_t)PHYS_SDRAM_1 + PHYS_SDRAM_1_SIZE)) ||
- (addr_start >= PHYS_SDRAM_2 &&
- addr_start <= ((sc_faddr_t)PHYS_SDRAM_2 + PHYS_SDRAM_2_SIZE)))
+ if ((addr_start >= phys_sdram_1_start &&
+ addr_start <= ((sc_faddr_t)phys_sdram_1_start + phys_sdram_1_size)) ||
+ (addr_start >= phys_sdram_2_start &&
+ addr_start <= ((sc_faddr_t)phys_sdram_2_start + phys_sdram_2_size)))
return (PTE_BLOCK_MEMTYPE(MT_NORMAL) | PTE_BLOCK_OUTER_SHARE);
return attr;
@@ -424,14 +456,20 @@
static u64 get_block_size(sc_faddr_t addr_start, sc_faddr_t addr_end)
{
sc_faddr_t end1, end2;
+ u64 phys_sdram_1_start, phys_sdram_1_size;
+ u64 phys_sdram_2_start, phys_sdram_2_size;
- end1 = (sc_faddr_t)PHYS_SDRAM_1 + PHYS_SDRAM_1_SIZE;
- end2 = (sc_faddr_t)PHYS_SDRAM_2 + PHYS_SDRAM_2_SIZE;
+ board_mem_get_layout(&phys_sdram_1_start, &phys_sdram_1_size,
+ &phys_sdram_2_start, &phys_sdram_2_size);
- if (addr_start >= PHYS_SDRAM_1 && addr_start <= end1) {
+
+ end1 = (sc_faddr_t)phys_sdram_1_start + phys_sdram_1_size;
+ end2 = (sc_faddr_t)phys_sdram_2_start + phys_sdram_2_size;
+
+ if (addr_start >= phys_sdram_1_start && addr_start <= end1) {
if ((addr_end + 1) > end1)
return end1 - addr_start;
- } else if (addr_start >= PHYS_SDRAM_2 && addr_start <= end2) {
+ } else if (addr_start >= phys_sdram_2_start && addr_start <= end2) {
if ((addr_end + 1) > end2)
return end2 - addr_start;
}
diff --git a/arch/arm/mach-imx/imx8m/soc.c b/arch/arm/mach-imx/imx8m/soc.c
index 9bca5bf..5df8e17 100644
--- a/arch/arm/mach-imx/imx8m/soc.c
+++ b/arch/arm/mach-imx/imx8m/soc.c
@@ -210,6 +210,9 @@
else
gd->ram_size = sdram_size;
+ /* also update the SDRAM size in the mem_map used externally */
+ imx8m_mem_map[5].size = sdram_size;
+
#ifdef PHYS_SDRAM_2_SIZE
gd->ram_size += PHYS_SDRAM_2_SIZE;
#endif
diff --git a/arch/arm/mach-imx/mx6/Kconfig b/arch/arm/mach-imx/mx6/Kconfig
index 0646b73..513d007 100644
--- a/arch/arm/mach-imx/mx6/Kconfig
+++ b/arch/arm/mach-imx/mx6/Kconfig
@@ -128,30 +128,8 @@
imply CMD_DM
imply CMD_SATA
-config TARGET_ARISTAINETOS2
- bool "aristainetos2"
- depends on MX6DL
- select BOARD_LATE_INIT
- select SYS_I2C_MXC
- select MXC_UART
- select FEC_MXC
- select DM
- imply CMD_SATA
- imply CMD_DM
-
-config TARGET_ARISTAINETOS2B
- bool "Support aristainetos2-revB"
- depends on MX6DL
- select BOARD_LATE_INIT
- select SYS_I2C_MXC
- select MXC_UART
- select FEC_MXC
- select DM
- imply CMD_SATA
- imply CMD_DM
-
-config TARGET_ARISTAINETOS2BCSL
- bool "Support aristainetos2-revB CSL"
+config TARGET_ARISTAINETOS2C
+ bool "Support aristainetos2-revC"
depends on MX6DL
select BOARD_LATE_INIT
select SYS_I2C_MXC
@@ -161,8 +139,8 @@
imply CMD_SATA
imply CMD_DM
-config TARGET_ARISTAINETOS2C
- bool "Support aristainetos2-revC"
+config TARGET_ARISTAINETOS2CCSLB
+ bool "Support aristainetos2-revC CSL"
depends on MX6DL
select BOARD_LATE_INIT
select SYS_I2C_MXC
diff --git a/board/advantech/imx8qm_rom7720_a1/MAINTAINERS b/board/advantech/imx8qm_rom7720_a1/MAINTAINERS
index b142ee0..58a4d25 100644
--- a/board/advantech/imx8qm_rom7720_a1/MAINTAINERS
+++ b/board/advantech/imx8qm_rom7720_a1/MAINTAINERS
@@ -2,5 +2,6 @@
M: Oliver Graute <oliver.graute@kococonnector.com>
S: Maintained
F: board/advantech/imx8qm_rom7720_a1/
+F: arch/arm/dts/imx8qm-rom7720-a1.dts
F: include/configs/imx8qm_rom7720.h
F: configs/imx8qm_rom7720_a1_4G_defconfig
diff --git a/board/advantech/imx8qm_rom7720_a1/README b/board/advantech/imx8qm_rom7720_a1/README
deleted file mode 100644
index 585fde4..0000000
--- a/board/advantech/imx8qm_rom7720_a1/README
+++ /dev/null
@@ -1,61 +0,0 @@
-U-Boot for the NXP i.MX8QM ROM 7720a1 board
-
-Quick Start
-===========
-
-- Build the ARM Trusted firmware binary
-- Get scfw_tcm.bin and ahab-container.img
-- Get imx-mkimage
-- Build U-Boot
-- Build imx-mkimage
-- Flash the binary into the SD card
-- Boot
-
-Get and Build the ARM Trusted firmware
-======================================
-
-$ git clone https://source.codeaurora.org/external/imx/imx-atf
-$ cd imx-atf/
-$ git checkout origin/imx_4.14.78_1.0.0_ga -b imx_4.14.78_1.0.0_ga
-$ make PLAT=imx8qm bl31
-
-Get scfw_tcm.bin and ahab-container.img
-==============================
-
-$ wget https://www.nxp.com/lgfiles/NMG/MAD/YOCTO/imx-sc-firmware-1.1.bin
-$ chmod +x imx-sc-firmware-1.1.bin
-$ ./imx-sc-firmware-1.1.bin
-$ wget https://www.nxp.com/lgfiles/NMG/MAD/YOCTO/firmware-imx-8.0.bin
-$ chmod +x firmware-imx-8.0.bin
-$ ./firmware-imx-8.0.bin
-
-Or use this to avoid running random scripts from the internet,
-but note that you must agree to the license the script displays:
-
-$ dd if=imx-sc-firmware-1.1.bin of=imx-sc-firmware-1.1.tar.bz2 bs=37185 skip=1
-$ tar -xf imx-sc-firmware-1.1.tar.bz2
-$ cp imx-sc-firmware-1.1/mx8qm-val-scfw-tcm.bin $(builddir)
-
-$ dd if=firmware-imx-8.0.bin of=firmware-imx-8.0.tar.bz2 bs=37180 skip=1
-$ tar -xf firmware-imx-8.0.tar.bz2
-$ cp firmware-imx-8.0/firmware/seco/mx8qm-ahab-container.img $(builddir)
-
-Build U-Boot
-============
-
-$ export ATF_LOAD_ADDR=0x80000000
-$ export BL33_LOAD_ADDR=0x80020000
-$ make imx8qm_rom7720_a1_4G_defconfig
-$ make u-boot.bin
-$ make flash.bin
-
-Flash the binary into the SD card
-=================================
-
-Burn the flash.bin binary to SD card offset 32KB:
-
-$ sudo dd if=flash.bin of=/dev/sd[x] bs=1k seek=32 conv=fsync
-
-Boot
-====
-Set Boot switch SW2: 1100.
diff --git a/board/aristainetos/Kconfig b/board/aristainetos/Kconfig
index 2ad3dbd..cc603c1 100644
--- a/board/aristainetos/Kconfig
+++ b/board/aristainetos/Kconfig
@@ -1,28 +1,4 @@
-if TARGET_ARISTAINETOS2
-
-source "board/aristainetos/common/Kconfig"
-
-config SYS_BOARD
- default "aristainetos"
-
-config SYS_BOARD_VERSION
- default 2
-
-endif
-
-if TARGET_ARISTAINETOS2B
-
-source "board/aristainetos/common/Kconfig"
-
-config SYS_BOARD
- default "aristainetos"
-
-config SYS_BOARD_VERSION
- default 3
-
-endif
-
-if TARGET_ARISTAINETOS2BCSL
+if TARGET_ARISTAINETOS2C
source "board/aristainetos/common/Kconfig"
@@ -30,11 +6,11 @@
default "aristainetos"
config SYS_BOARD_VERSION
- default 4
+ default 5
endif
-if TARGET_ARISTAINETOS2C
+if TARGET_ARISTAINETOS2CCSLB
source "board/aristainetos/common/Kconfig"
@@ -42,6 +18,6 @@
default "aristainetos"
config SYS_BOARD_VERSION
- default 5
+ default 6
endif
diff --git a/board/aristainetos/MAINTAINERS b/board/aristainetos/MAINTAINERS
index b4ca7ab..c81bef9 100644
--- a/board/aristainetos/MAINTAINERS
+++ b/board/aristainetos/MAINTAINERS
@@ -3,34 +3,16 @@
S: Maintained
F: board/aristainetos/
F: include/configs/aristainetos2.h
-F: configs/aristainetos2_defconfig
-F: configs/aristainetos2b_defconfig
-F: configs/aristainetos2bcsl_defconfig
F: configs/aristainetos2c_defconfig
-F: arch/arm/dts/imx6qdl-aristainetos2.dtsi
-F: arch/arm/dts/imx6qdl-aristainetos2-common.dtsi
-F: arch/arm/dts/imx6qdl-aristainetos2-u-boot.dtsi
-F: arch/arm/dts/imx6dl-aristainetos2_7.dts
-F: arch/arm/dts/imx6dl-aristainetos2_7.dtsi
-F: arch/arm/dts/imx6dl-aristainetos2_7-u-boot.dtsi
-F: arch/arm/dts/imx6dl-aristainetos2_4.dts
-F: arch/arm/dts/imx6dl-aristainetos2_4.dtsi
-F: arch/arm/dts/imx6dl-aristainetos2_4-u-boot.dtsi
-F: arch/arm/dts/imx6dl-aristainetos2b_4.dts
-F: arch/arm/dts/imx6dl-aristainetos2b_4-u-boot.dtsi
-F: arch/arm/dts/imx6dl-aristainetos2b_7.dts
-F: arch/arm/dts/imx6dl-aristainetos2b_7-u-boot.dtsi
-F: arch/arm/dts/imx6qdl-aristainetos2b-u-boot.dtsi
-F: arch/arm/dts/imx6qdl-aristainetos2b.dtsi
-F: arch/arm/dts/imx6dl-aristainetos2b_csl_4.dts
-F: arch/arm/dts/imx6dl-aristainetos2b_csl_4-u-boot.dtsi
-F: arch/arm/dts/imx6dl-aristainetos2b_csl_7.dts
-F: arch/arm/dts/imx6dl-aristainetos2b_csl_7-u-boot.dtsi
-F: arch/arm/dts/imx6qdl-aristainetos2b_csl.dtsi
-F: arch/arm/dts/imx6qdl-aristainetos2b_csl-u-boot.dtsi
-F: arch/arm/dts/imx6dl-aristainetos2c_4.dts
-F: arch/arm/dts/imx6dl-aristainetos2c_4-u-boot.dtsi
+F: configs/aristainetos2ccslb_defconfig
F: arch/arm/dts/imx6dl-aristainetos2c_7.dts
F: arch/arm/dts/imx6dl-aristainetos2c_7-u-boot.dtsi
+F: arch/arm/dts/imx6dl-aristainetos2c_cslb_7.dts
+F: arch/arm/dts/imx6dl-aristainetos2c_cslb_7-u-boot.dtsi
+F: arch/arm/dts/imx6dl-aristainetos2_7.dtsi
+F: arch/arm/dts/imx6qdl-aristainetos2-common.dtsi
+F: arch/arm/dts/imx6qdl-aristainetos2-u-boot.dtsi
F: arch/arm/dts/imx6qdl-aristainetos2c.dtsi
F: arch/arm/dts/imx6qdl-aristainetos2c-u-boot.dtsi
+F: arch/arm/dts/imx6qdl-aristainetos2c_cslb.dtsi
+F: arch/arm/dts/imx6qdl-aristainetos2c_cslb-u-boot.dtsi
diff --git a/board/aristainetos/aristainetos.c b/board/aristainetos/aristainetos.c
index 1493112..07d2e3e 100644
--- a/board/aristainetos/aristainetos.c
+++ b/board/aristainetos/aristainetos.c
@@ -27,6 +27,7 @@
#include <bmp_logo.h>
#include <dm/root.h>
#include <env.h>
+#include <env_internal.h>
#include <i2c_eeprom.h>
#include <i2c.h>
#include <micrel.h>
@@ -194,87 +195,6 @@
writel(reg, &iomux->gpr[3]);
}
-static void enable_spi_display(struct display_info_t const *dev)
-{
- struct iomuxc *iomux = (struct iomuxc *)IOMUXC_BASE_ADDR;
- struct mxc_ccm_reg *ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
- int reg;
- s32 timeout = 100000;
-
-#if defined(CONFIG_VIDEO_BMP_LOGO)
- rotate_logo(3); /* portrait display in landscape mode */
-#endif
-
- reg = readl(&ccm->cs2cdr);
-
- /* select pll 5 clock */
- reg &= ~(MXC_CCM_CS2CDR_LDB_DI0_CLK_SEL_MASK
- | MXC_CCM_CS2CDR_LDB_DI1_CLK_SEL_MASK);
- writel(reg, &ccm->cs2cdr);
-
- /* set PLL5 to 197994996Hz */
- reg &= ~BM_ANADIG_PLL_VIDEO_DIV_SELECT;
- reg |= BF_ANADIG_PLL_VIDEO_DIV_SELECT(0x21);
- reg &= ~BM_ANADIG_PLL_VIDEO_POST_DIV_SELECT;
- reg |= BF_ANADIG_PLL_VIDEO_POST_DIV_SELECT(0);
- writel(reg, &ccm->analog_pll_video);
-
- writel(BF_ANADIG_PLL_VIDEO_NUM_A(0xfbf4),
- &ccm->analog_pll_video_num);
- writel(BF_ANADIG_PLL_VIDEO_DENOM_B(0xf4240),
- &ccm->analog_pll_video_denom);
-
- reg &= ~BM_ANADIG_PLL_VIDEO_POWERDOWN;
- writel(reg, &ccm->analog_pll_video);
-
- while (timeout--)
- if (readl(&ccm->analog_pll_video) & BM_ANADIG_PLL_VIDEO_LOCK)
- break;
- if (timeout < 0)
- printf("Warning: video pll lock timeout!\n");
-
- reg = readl(&ccm->analog_pll_video);
- reg |= BM_ANADIG_PLL_VIDEO_ENABLE;
- reg &= ~BM_ANADIG_PLL_VIDEO_BYPASS;
- writel(reg, &ccm->analog_pll_video);
-
- /* set LDB0, LDB1 clk select to 000/000 (PLL5 clock) */
- reg = readl(&ccm->cs2cdr);
- reg &= ~(MXC_CCM_CS2CDR_LDB_DI0_CLK_SEL_MASK
- | MXC_CCM_CS2CDR_LDB_DI1_CLK_SEL_MASK);
- reg |= (0 << MXC_CCM_CS2CDR_LDB_DI0_CLK_SEL_OFFSET)
- | (0 << MXC_CCM_CS2CDR_LDB_DI1_CLK_SEL_OFFSET);
- writel(reg, &ccm->cs2cdr);
-
- reg = readl(&ccm->cscmr2);
- reg |= MXC_CCM_CSCMR2_LDB_DI0_IPU_DIV;
- writel(reg, &ccm->cscmr2);
-
- reg = readl(&ccm->chsccdr);
- reg |= (CHSCCDR_CLK_SEL_LDB_DI0
- << MXC_CCM_CHSCCDR_IPU1_DI0_CLK_SEL_OFFSET);
- reg &= ~MXC_CCM_CHSCCDR_IPU1_DI0_PODF_MASK;
- reg |= (2 << MXC_CCM_CHSCCDR_IPU1_DI0_PODF_OFFSET);
- reg &= ~MXC_CCM_CHSCCDR_IPU1_DI0_PRE_CLK_SEL_MASK;
- reg |= (2 << MXC_CCM_CHSCCDR_IPU1_DI0_PRE_CLK_SEL_OFFSET);
- writel(reg, &ccm->chsccdr);
-
- reg = IOMUXC_GPR2_BGREF_RRMODE_EXTERNAL_RES
- | IOMUXC_GPR2_DI1_VS_POLARITY_ACTIVE_HIGH
- | IOMUXC_GPR2_DI0_VS_POLARITY_ACTIVE_HIGH
- | IOMUXC_GPR2_BIT_MAPPING_CH0_SPWG
- | IOMUXC_GPR2_DATA_WIDTH_CH0_24BIT
- | IOMUXC_GPR2_LVDS_CH1_MODE_DISABLED
- | IOMUXC_GPR2_LVDS_CH0_MODE_ENABLED_DI0;
- writel(reg, &iomux->gpr[2]);
-
- reg = readl(&iomux->gpr[3]);
- reg = (reg & ~IOMUXC_GPR3_LVDS0_MUX_CTL_MASK)
- | (IOMUXC_GPR3_MUX_SRC_IPU1_DI0
- << IOMUXC_GPR3_LVDS0_MUX_CTL_OFFSET);
- writel(reg, &iomux->gpr[3]);
-}
-
static void setup_display(void)
{
enable_ipu_clock();
@@ -331,25 +251,36 @@
setup_one_led("led_blue", LEDST_OFF);
}
-#define ARI_RESC_FMT "setenv rescue_reason setenv bootargs \\${bootargs}" \
- " rescueReason=%d "
-
static void aristainetos_run_rescue_command(int reason)
{
- char rescue_reason_command[80];
+ char rescue_reason_command[20];
- sprintf(rescue_reason_command, ARI_RESC_FMT, reason);
+ sprintf(rescue_reason_command, "setenv rreason %d", reason);
run_command(rescue_reason_command, 0);
}
-static int aristainetos_eeprom(void)
+static int aristainetos_bootmode_settings(void)
{
+ struct gpio_desc *desc;
+ struct src *psrc = (struct src *)SRC_BASE_ADDR;
+ unsigned int sbmr1 = readl(&psrc->sbmr1);
+ char *my_bootdelay;
+ char bootmode = 0;
+ int ret;
struct udevice *dev;
int off;
- int ret;
u8 data[0x10];
u8 rescue_reason;
+ /* jumper controlled reset of the environment */
+ ret = gpio_hog_lookup_name("env_reset", &desc);
+ if (!ret) {
+ if (dm_gpio_get_value(desc)) {
+ printf("\nReset u-boot environment (jumper)\n");
+ run_command("run default_env; saveenv; saveenv", 0);
+ }
+ }
+
off = fdt_path_offset(gd->fdt_blob, "eeprom0");
if (off < 0) {
printf("%s: No eeprom0 path offset\n", __func__);
@@ -366,37 +297,26 @@
if (ret)
return ret;
- ret = i2c_eeprom_read(dev, 0x1ff0, (uint8_t *)data, 6);
+ ret = i2c_eeprom_read(dev, 0x1ff0, (uint8_t *)data, sizeof(data));
if (ret) {
printf("%s: Could not read EEPROM\n", __func__);
return ret;
}
- if (strncmp((char *)&data[3], "ReScUe", 6) == 0) {
- rescue_reason = *(uint8_t *)&data[9];
- memset(&data[3], 0xff, 7);
- i2c_eeprom_write(dev, 0x1ff0, (uint8_t *)&data[3], 7);
- printf("\nBooting into Rescue System (EEPROM)\n");
- aristainetos_run_rescue_command(rescue_reason);
- run_command("run rescue_load_fit rescueboot", 0);
- } else if (strncmp((char *)data, "DeF", 3) == 0) {
+ /* software controlled reset of the environment (EEPROM magic) */
+ if (strncmp((char *)data, "DeF", 3) == 0) {
memset(data, 0xff, 3);
i2c_eeprom_write(dev, 0x1ff0, (uint8_t *)data, 3);
- printf("\nClear u-boot environment (set back to defaults)\n");
+ printf("\nReset u-boot environment (EEPROM)\n");
run_command("run default_env; saveenv; saveenv", 0);
}
- return 0;
-};
-
-static void aristainetos_bootmode_settings(void)
-{
- struct gpio_desc *desc;
- struct src *psrc = (struct src *)SRC_BASE_ADDR;
- unsigned int sbmr1 = readl(&psrc->sbmr1);
- char *my_bootdelay;
- char bootmode = 0;
- int ret;
+ if (sbmr1 & 0x40) {
+ env_set("bootmode", "1");
+ printf("SD bootmode jumper set!\n");
+ } else {
+ env_set("bootmode", "0");
+ }
/*
* Check the boot-source. If booting from NOR Flash,
@@ -420,28 +340,27 @@
env_set("bootdelay", "-2");
}
- if (sbmr1 & 0x40) {
- env_set("bootmode", "1");
- printf("SD bootmode jumper set!\n");
- } else {
- env_set("bootmode", "0");
- }
-
- /* read out some jumper values*/
- ret = gpio_hog_lookup_name("env_reset", &desc);
- if (!ret) {
- if (dm_gpio_get_value(desc)) {
- printf("\nClear env (set back to defaults)\n");
- run_command("run default_env; saveenv; saveenv", 0);
- }
- }
+ /* jumper controlled boot of the rescue system */
ret = gpio_hog_lookup_name("boot_rescue", &desc);
if (!ret) {
if (dm_gpio_get_value(desc)) {
+ printf("\nBooting into Rescue System (jumper)\n");
aristainetos_run_rescue_command(16);
run_command("run rescue_xload_boot", 0);
}
}
+
+ /* software controlled boot of the rescue system (EEPROM magic) */
+ if (strncmp((char *)&data[3], "ReScUe", 6) == 0) {
+ rescue_reason = *(uint8_t *)&data[9];
+ memset(&data[3], 0xff, 7);
+ i2c_eeprom_write(dev, 0x1ff0, (uint8_t *)&data[3], 7);
+ printf("\nBooting into Rescue System (EEPROM)\n");
+ aristainetos_run_rescue_command(rescue_reason);
+ run_command("run rescue_xload_boot", 0);
+ }
+
+ return 0;
}
#if defined(CONFIG_DM_PMIC_DA9063)
@@ -497,15 +416,15 @@
int board_late_init(void)
{
int x, y;
+ int ret;
led_default_state();
splash_get_pos(&x, &y);
bmp_display((ulong)&bmp_logo_bitmap[0], x, y);
- aristainetos_bootmode_settings();
-
- /* eeprom work */
- aristainetos_eeprom();
+ ret = aristainetos_bootmode_settings();
+ if (ret)
+ return ret;
/* set board_type */
if (gd->board_type == BOARD_TYPE_4)
@@ -549,97 +468,9 @@
.vmode = FB_VMODE_NONINTERLACED
}
}
-#if ((CONFIG_SYS_BOARD_VERSION == 2) || \
- (CONFIG_SYS_BOARD_VERSION == 3) || \
- (CONFIG_SYS_BOARD_VERSION == 4) || \
- (CONFIG_SYS_BOARD_VERSION == 5))
- , {
- .bus = -1,
- .addr = 0,
- .pixfmt = IPU_PIX_FMT_RGB24,
- .detect = NULL,
- .enable = enable_spi_display,
- .mode = {
- .name = "lg4573",
- .refresh = 57,
- .xres = 480,
- .yres = 800,
- .pixclock = 37037,
- .left_margin = 59,
- .right_margin = 10,
- .upper_margin = 15,
- .lower_margin = 15,
- .hsync_len = 10,
- .vsync_len = 15,
- .sync = FB_SYNC_EXT | FB_SYNC_HOR_HIGH_ACT |
- FB_SYNC_VERT_HIGH_ACT,
- .vmode = FB_VMODE_NONINTERLACED
- }
- }
-#endif
};
size_t display_count = ARRAY_SIZE(displays);
-#if defined(CONFIG_MTD_RAW_NAND)
-iomux_v3_cfg_t nfc_pads[] = {
- MX6_PAD_NANDF_CLE__NAND_CLE | MUX_PAD_CTRL(NO_PAD_CTRL),
- MX6_PAD_NANDF_ALE__NAND_ALE | MUX_PAD_CTRL(NO_PAD_CTRL),
- MX6_PAD_NANDF_WP_B__NAND_WP_B | MUX_PAD_CTRL(NO_PAD_CTRL),
- MX6_PAD_NANDF_RB0__NAND_READY_B | MUX_PAD_CTRL(NO_PAD_CTRL),
- MX6_PAD_NANDF_CS0__NAND_CE0_B | MUX_PAD_CTRL(NO_PAD_CTRL),
- MX6_PAD_SD4_CMD__NAND_RE_B | MUX_PAD_CTRL(NO_PAD_CTRL),
- MX6_PAD_SD4_CLK__NAND_WE_B | MUX_PAD_CTRL(NO_PAD_CTRL),
- MX6_PAD_NANDF_D0__NAND_DATA00 | MUX_PAD_CTRL(NO_PAD_CTRL),
- MX6_PAD_NANDF_D1__NAND_DATA01 | MUX_PAD_CTRL(NO_PAD_CTRL),
- MX6_PAD_NANDF_D2__NAND_DATA02 | MUX_PAD_CTRL(NO_PAD_CTRL),
- MX6_PAD_NANDF_D3__NAND_DATA03 | MUX_PAD_CTRL(NO_PAD_CTRL),
- MX6_PAD_NANDF_D4__NAND_DATA04 | MUX_PAD_CTRL(NO_PAD_CTRL),
- MX6_PAD_NANDF_D5__NAND_DATA05 | MUX_PAD_CTRL(NO_PAD_CTRL),
- MX6_PAD_NANDF_D6__NAND_DATA06 | MUX_PAD_CTRL(NO_PAD_CTRL),
- MX6_PAD_NANDF_D7__NAND_DATA07 | MUX_PAD_CTRL(NO_PAD_CTRL),
- MX6_PAD_SD4_DAT0__NAND_DQS | MUX_PAD_CTRL(NO_PAD_CTRL),
-};
-
-static void setup_gpmi_nand(void)
-{
- struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
-
- /* config gpmi nand iomux */
- imx_iomux_v3_setup_multiple_pads(nfc_pads,
- ARRAY_SIZE(nfc_pads));
-
- /* gate ENFC_CLK_ROOT clock first,before clk source switch */
- clrbits_le32(&mxc_ccm->CCGR2, MXC_CCM_CCGR2_IOMUX_IPT_CLK_IO_MASK);
-
- /* config gpmi and bch clock to 100 MHz */
- clrsetbits_le32(&mxc_ccm->cs2cdr,
- MXC_CCM_CS2CDR_ENFC_CLK_PODF_MASK |
- MXC_CCM_CS2CDR_ENFC_CLK_PRED_MASK |
- MXC_CCM_CS2CDR_ENFC_CLK_SEL_MASK,
- MXC_CCM_CS2CDR_ENFC_CLK_PODF(0) |
- MXC_CCM_CS2CDR_ENFC_CLK_PRED(3) |
- MXC_CCM_CS2CDR_ENFC_CLK_SEL(3));
-
- /* enable ENFC_CLK_ROOT clock */
- setbits_le32(&mxc_ccm->CCGR2, MXC_CCM_CCGR2_IOMUX_IPT_CLK_IO_MASK);
-
- /* enable gpmi and bch clock gating */
- setbits_le32(&mxc_ccm->CCGR4,
- MXC_CCM_CCGR4_RAWNAND_U_BCH_INPUT_APB_MASK |
- MXC_CCM_CCGR4_RAWNAND_U_GPMI_BCH_INPUT_BCH_MASK |
- MXC_CCM_CCGR4_RAWNAND_U_GPMI_BCH_INPUT_GPMI_IO_MASK |
- MXC_CCM_CCGR4_RAWNAND_U_GPMI_INPUT_APB_MASK |
- MXC_CCM_CCGR4_PL301_MX6QPER1_BCH_OFFSET);
-
- /* enable apbh clock gating */
- setbits_le32(&mxc_ccm->CCGR0, MXC_CCM_CCGR0_APBHDMA_MASK);
-}
-#else
-static void setup_gpmi_nand(void)
-{
-}
-#endif
-
int board_init(void)
{
struct iomuxc *iomux = (struct iomuxc *)IOMUXC_BASE_ADDR;
@@ -648,7 +479,6 @@
gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
setup_board_gpio();
- setup_gpmi_nand();
setup_display();
/* GPIO_1 for USB_OTG_ID */
@@ -698,3 +528,22 @@
return 0;
}
#endif
+
+enum env_location env_get_location(enum env_operation op, int prio)
+{
+ if (op == ENVOP_SAVE || op == ENVOP_ERASE)
+ return ENVL_SPI_FLASH;
+
+ switch (prio) {
+ case 0:
+ return ENVL_NOWHERE;
+
+ case 1:
+ return ENVL_SPI_FLASH;
+
+ default:
+ return ENVL_UNKNOWN;
+ }
+
+ return ENVL_UNKNOWN;
+}
diff --git a/board/aristainetos/common/Kconfig b/board/aristainetos/common/Kconfig
index e26de51..328243c 100644
--- a/board/aristainetos/common/Kconfig
+++ b/board/aristainetos/common/Kconfig
@@ -2,10 +2,8 @@
int "select version of aristainetos board"
help
version of aristainetos board version
- 2 version 2
- 3 version 2b
- 4 version 2bcsl
- 5 version 2c
+ 5 version 2c and 2d
+ 6 version 2c-cslb
config SYS_I2C_MXC_I2C1
default y
diff --git a/board/ge/bx50v3/bx50v3.c b/board/ge/bx50v3/bx50v3.c
index 8a38ac5..4754647 100644
--- a/board/ge/bx50v3/bx50v3.c
+++ b/board/ge/bx50v3/bx50v3.c
@@ -43,28 +43,17 @@
DECLARE_GLOBAL_DATA_PTR;
-static int confidx; /* Default to generic. */
+#define VPD_PRODUCT_B850 1
+#define VPD_PRODUCT_B650 2
+#define VPD_PRODUCT_B450 3
+
+static int productid; /* Default to generic. */
static struct vpd_cache vpd;
#define NC_PAD_CTRL (PAD_CTL_PUS_100K_UP | \
PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | \
PAD_CTL_HYS)
-#define ENET_PAD_CTRL (PAD_CTL_PUS_100K_UP | PAD_CTL_PUE | \
- PAD_CTL_SPEED_HIGH | PAD_CTL_DSE_48ohm | PAD_CTL_SRE_FAST)
-
-#define ENET_CLK_PAD_CTRL (PAD_CTL_SPEED_MED | \
- PAD_CTL_DSE_120ohm | PAD_CTL_SRE_FAST)
-
-#define ENET_RX_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \
- PAD_CTL_SPEED_HIGH | PAD_CTL_SRE_FAST)
-
-#define I2C_PAD_CTRL (PAD_CTL_PUS_100K_UP | \
- PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | PAD_CTL_HYS | \
- PAD_CTL_ODE | PAD_CTL_SRE_FAST)
-
-#define I2C_PAD MUX_PAD_CTRL(I2C_PAD_CTRL)
-
int dram_init(void)
{
gd->ram_size = imx_ddr_size();
@@ -127,7 +116,7 @@
static int is_b850v3(void)
{
- return confidx == 3;
+ return productid == VPD_PRODUCT_B850;
}
static int detect_lcd(struct display_info_t const *dev)
@@ -314,9 +303,6 @@
#define VPD_TYPE_INVALID 0x00
#define VPD_BLOCK_NETWORK 0x20
#define VPD_BLOCK_HWID 0x44
-#define VPD_PRODUCT_B850 1
-#define VPD_PRODUCT_B650 2
-#define VPD_PRODUCT_B450 3
#define VPD_HAS_MAC1 0x1
#define VPD_HAS_MAC2 0x2
#define VPD_MAC_ADDRESS_LENGTH 6
@@ -398,6 +384,7 @@
MX6_PAD_GPIO_9__WDOG1_B | MUX_PAD_CTRL(NC_PAD_CTRL),
};
#define SUS_S3_OUT IMX_GPIO_NR(4, 11)
+#define PWGIN_IN IMX_GPIO_NR(4, 14)
#define WIFI_EN IMX_GPIO_NR(6, 14)
int board_early_init_f(void)
@@ -412,28 +399,13 @@
return 0;
}
-static void set_confidx(const struct vpd_cache* vpd)
-{
- switch (vpd->product_id) {
- case VPD_PRODUCT_B450:
- confidx = 1;
- break;
- case VPD_PRODUCT_B650:
- confidx = 2;
- break;
- case VPD_PRODUCT_B850:
- confidx = 3;
- break;
- }
-}
-
int board_init(void)
{
if (!read_i2c_vpd(&vpd, vpd_callback)) {
int ret, rescan;
vpd.is_read = true;
- set_confidx(&vpd);
+ productid = vpd.product_id;
ret = fdtdec_resetup(&rescan);
if (!ret && rescan) {
@@ -445,6 +417,9 @@
gpio_request(SUS_S3_OUT, "sus_s3_out");
gpio_direction_output(SUS_S3_OUT, 1);
+ gpio_request(PWGIN_IN, "pwgin_in");
+ gpio_direction_input(PWGIN_IN);
+
gpio_request(WIFI_EN, "wifi_en");
gpio_direction_output(WIFI_EN, 1);
@@ -494,6 +469,17 @@
}
}
+static void detect_boot_cause(void)
+{
+ const char *cause = "POR";
+
+ if (is_b850v3())
+ if (!gpio_get_value(PWGIN_IN))
+ cause = "PM_WDOG";
+
+ env_set("bootcause", cause);
+}
+
int board_late_init(void)
{
process_vpd(&vpd);
@@ -507,6 +493,8 @@
else
env_set("videoargs", "video=LVDS-1:1024x768@65");
+ detect_boot_cause();
+
/* board specific pmic init */
pmic_init();
diff --git a/board/ge/common/vpd_reader.c b/board/ge/common/vpd_reader.c
index 421fee5..c28d2c0 100644
--- a/board/ge/common/vpd_reader.c
+++ b/board/ge/common/vpd_reader.c
@@ -209,7 +209,7 @@
u8 *data;
int size;
- ret = uclass_get_device_by_name(UCLASS_I2C_EEPROM, "vpd", &dev);
+ ret = uclass_get_device_by_name(UCLASS_I2C_EEPROM, "vpd@0", &dev);
if (ret)
return ret;
diff --git a/board/toradex/apalis-imx8/apalis-imx8.c b/board/toradex/apalis-imx8/apalis-imx8.c
index 9263b0f..2ed6626 100644
--- a/board/toradex/apalis-imx8/apalis-imx8.c
+++ b/board/toradex/apalis-imx8/apalis-imx8.c
@@ -37,6 +37,29 @@
imx8_iomux_setup_multiple_pads(uart1_pads, ARRAY_SIZE(uart1_pads));
}
+void board_mem_get_layout(u64 *phys_sdram_1_start,
+ u64 *phys_sdram_1_size,
+ u64 *phys_sdram_2_start,
+ u64 *phys_sdram_2_size)
+{
+ u32 is_quadplus = 0, val = 0;
+ sc_err_t scierr = sc_misc_otp_fuse_read(-1, 6, &val);
+
+ if (scierr == SC_ERR_NONE) {
+ /* QP has one A72 core disabled */
+ is_quadplus = ((val >> 4) & 0x3) != 0x0;
+ }
+
+ *phys_sdram_1_start = PHYS_SDRAM_1;
+ *phys_sdram_1_size = PHYS_SDRAM_1_SIZE;
+ *phys_sdram_2_start = PHYS_SDRAM_2;
+ if (is_quadplus)
+ /* Our QP based SKUs only have 2 GB RAM (PHYS_SDRAM_1_SIZE) */
+ *phys_sdram_2_size = 0x0UL;
+ else
+ *phys_sdram_2_size = PHYS_SDRAM_2_SIZE;
+}
+
int board_early_init_f(void)
{
sc_pm_clock_rate_t rate = SC_80MHZ;
diff --git a/board/toradex/apalis-imx8x/Kconfig b/board/toradex/apalis-imx8x/Kconfig
new file mode 100644
index 0000000..ee61e09
--- /dev/null
+++ b/board/toradex/apalis-imx8x/Kconfig
@@ -0,0 +1,30 @@
+if TARGET_APALIS_IMX8X
+
+config SYS_BOARD
+ default "apalis-imx8x"
+
+config SYS_VENDOR
+ default "toradex"
+
+config SYS_CONFIG_NAME
+ default "apalis-imx8x"
+
+config TDX_CFG_BLOCK
+ default y
+
+config TDX_HAVE_MMC
+ default y
+
+config TDX_CFG_BLOCK_DEV
+ default "0"
+
+config TDX_CFG_BLOCK_PART
+ default "1"
+
+# Toradex config block in eMMC, at the end of 1st "boot sector"
+config TDX_CFG_BLOCK_OFFSET
+ default "-512"
+
+source "board/toradex/common/Kconfig"
+
+endif
diff --git a/board/toradex/apalis-imx8x/MAINTAINERS b/board/toradex/apalis-imx8x/MAINTAINERS
new file mode 100644
index 0000000..fbf9379
--- /dev/null
+++ b/board/toradex/apalis-imx8x/MAINTAINERS
@@ -0,0 +1,10 @@
+Apalis iMX8X
+M: Igor Opaniuk <igor.opaniuk@toradex.com>
+W: http://developer.toradex.com/software/linux/linux-software
+S: Maintained
+F: arch/arm/dts/fsl-imx8x-apalis.dts
+F: arch/arm/dts/fsl-imx8x-apalis-u-boot.dtsi
+F: board/toradex/apalis-imx8x/
+F: configs/apalis-imx8x_defconfig
+F: doc/board/toradex/apalis-imx8x.rst
+F: include/configs/apalis-imx8x.h
diff --git a/board/toradex/apalis-imx8x/Makefile b/board/toradex/apalis-imx8x/Makefile
new file mode 100644
index 0000000..9d6e85b
--- /dev/null
+++ b/board/toradex/apalis-imx8x/Makefile
@@ -0,0 +1,6 @@
+# SPDX-License-Identifier: GPL-2.0+
+#
+# Copyright 2020 Toradex
+#
+
+obj-y += apalis-imx8x.o
diff --git a/board/toradex/apalis-imx8x/apalis-imx8x-imximage.cfg b/board/toradex/apalis-imx8x/apalis-imx8x-imximage.cfg
new file mode 100644
index 0000000..58c62d0
--- /dev/null
+++ b/board/toradex/apalis-imx8x/apalis-imx8x-imximage.cfg
@@ -0,0 +1,24 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright 2020 Toradex
+ *
+ * Refer doc/imx/mkimage/imx8image.txt for more details about how-to configure
+ * and create imx8image boot image
+ */
+
+#define __ASSEMBLY__
+
+/* Boot from SD, sector size 0x400 */
+BOOT_FROM EMMC_FASTBOOT 0x400
+/* SoC type IMX8QX */
+SOC_TYPE IMX8QX
+/* Append seco container image */
+APPEND mx8qx-ahab-container.img
+/* Create the 2nd container */
+CONTAINER
+/* Add scfw image with exec attribute */
+IMAGE SCU mx8qx-apalis-scfw-tcm.bin
+/* Add ATF image with exec attribute */
+IMAGE A35 bl31.bin 0x80000000
+/* Add U-Boot image with load attribute */
+DATA A35 u-boot-dtb.bin 0x80020000
diff --git a/board/toradex/apalis-imx8x/apalis-imx8x.c b/board/toradex/apalis-imx8x/apalis-imx8x.c
new file mode 100644
index 0000000..739d2e5
--- /dev/null
+++ b/board/toradex/apalis-imx8x/apalis-imx8x.c
@@ -0,0 +1,154 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright 2020 Toradex
+ */
+
+#include <common.h>
+#include <cpu_func.h>
+#include <init.h>
+
+#include <asm/arch/clock.h>
+#include <asm/arch/imx8-pins.h>
+#include <asm/arch/iomux.h>
+#include <asm/arch/sci/sci.h>
+#include <asm/arch/sys_proto.h>
+#include <asm/gpio.h>
+#include <asm/io.h>
+#include <env.h>
+#include <errno.h>
+#include <linux/libfdt.h>
+
+#include "../common/tdx-cfg-block.h"
+
+DECLARE_GLOBAL_DATA_PTR;
+
+#define UART_PAD_CTRL ((SC_PAD_CONFIG_OUT_IN << PADRING_CONFIG_SHIFT) | \
+ (SC_PAD_ISO_OFF << PADRING_LPCONFIG_SHIFT) | \
+ (SC_PAD_28FDSOI_DSE_DV_HIGH << PADRING_DSE_SHIFT) | \
+ (SC_PAD_28FDSOI_PS_PU << PADRING_PULL_SHIFT))
+
+static iomux_cfg_t uart1_pads[] = {
+ SC_P_UART1_RX | MUX_PAD_CTRL(UART_PAD_CTRL),
+ SC_P_UART1_TX | MUX_PAD_CTRL(UART_PAD_CTRL),
+};
+
+static void setup_iomux_uart(void)
+{
+ imx8_iomux_setup_multiple_pads(uart1_pads, ARRAY_SIZE(uart1_pads));
+}
+
+void board_mem_get_layout(u64 *phys_sdram_1_start,
+ u64 *phys_sdram_1_size,
+ u64 *phys_sdram_2_start,
+ u64 *phys_sdram_2_size)
+{
+ u32 is_dualx = 0, val = 0;
+ sc_err_t scierr = sc_misc_otp_fuse_read(-1, 6, &val);
+
+ if (scierr == SC_ERR_NONE) {
+ /* DX has two A35 cores disabled */
+ is_dualx = (val & 0xf) != 0x0;
+ }
+
+ *phys_sdram_1_start = PHYS_SDRAM_1;
+ if (is_dualx)
+ /* Our DX based SKUs only have 1 GB RAM */
+ *phys_sdram_1_size = SZ_1G;
+ else
+ *phys_sdram_1_size = PHYS_SDRAM_1_SIZE;
+ *phys_sdram_2_start = PHYS_SDRAM_2;
+ *phys_sdram_2_size = PHYS_SDRAM_2_SIZE;
+}
+
+int board_early_init_f(void)
+{
+ sc_pm_clock_rate_t rate;
+ sc_err_t err = 0;
+
+ /*
+ * This works around that having only UART3 up the baudrate is 1.2M
+ * instead of 115.2k. Set UART0 clock root to 80 MHz
+ */
+ rate = 80000000;
+ err = sc_pm_set_clock_rate(-1, SC_R_UART_0, SC_PM_CLK_PER, &rate);
+ if (err != SC_ERR_NONE)
+ return 0;
+
+ /* Set UART3 clock root to 80 MHz and enable it */
+ rate = SC_80MHZ;
+ err = sc_pm_setup_uart(SC_R_UART_1, rate);
+ if (err != SC_ERR_NONE)
+ return 0;
+
+ setup_iomux_uart();
+
+ return 0;
+}
+
+#if IS_ENABLED(CONFIG_DM_GPIO)
+static void board_gpio_init(void)
+{
+ /* TODO */
+}
+#else
+static inline void board_gpio_init(void) {}
+#endif
+
+#if IS_ENABLED(CONFIG_FEC_MXC)
+#include <miiphy.h>
+
+int board_phy_config(struct phy_device *phydev)
+{
+ if (phydev->drv->config)
+ phydev->drv->config(phydev);
+
+ return 0;
+}
+#endif
+
+int checkboard(void)
+{
+ puts("Model: Toradex Apalis iMX8X\n");
+
+ build_info();
+ print_bootinfo();
+
+ return 0;
+}
+
+int board_init(void)
+{
+ board_gpio_init();
+
+ return 0;
+}
+
+/*
+ * Board specific reset that is system reset.
+ */
+void reset_cpu(ulong addr)
+{
+ /* TODO */
+}
+
+#if defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP)
+int ft_board_setup(void *blob, struct bd_info *bd)
+{
+ return ft_common_board_setup(blob, bd);
+}
+#endif
+
+int board_mmc_get_env_dev(int devno)
+{
+ return devno;
+}
+
+int board_late_init(void)
+{
+#ifdef CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG
+/* TODO move to common */
+ env_set("board_name", "Apalis iMX8X");
+#endif
+
+ return 0;
+}
diff --git a/board/toradex/colibri-imx8x/colibri-imx8x.c b/board/toradex/colibri-imx8x/colibri-imx8x.c
index f981c11..da081e3 100644
--- a/board/toradex/colibri-imx8x/colibri-imx8x.c
+++ b/board/toradex/colibri-imx8x/colibri-imx8x.c
@@ -39,6 +39,29 @@
imx8_iomux_setup_multiple_pads(uart3_pads, ARRAY_SIZE(uart3_pads));
}
+void board_mem_get_layout(u64 *phys_sdram_1_start,
+ u64 *phys_sdram_1_size,
+ u64 *phys_sdram_2_start,
+ u64 *phys_sdram_2_size)
+{
+ u32 is_dualx = 0, val = 0;
+ sc_err_t scierr = sc_misc_otp_fuse_read(-1, 6, &val);
+
+ if (scierr == SC_ERR_NONE) {
+ /* DX has two A35 cores disabled */
+ is_dualx = (val & 0xf) != 0x0;
+ }
+
+ *phys_sdram_1_start = PHYS_SDRAM_1;
+ if (is_dualx)
+ /* Our DX based SKUs only have 1 GB RAM */
+ *phys_sdram_1_size = SZ_1G;
+ else
+ *phys_sdram_1_size = PHYS_SDRAM_1_SIZE;
+ *phys_sdram_2_start = PHYS_SDRAM_2;
+ *phys_sdram_2_size = PHYS_SDRAM_2_SIZE;
+}
+
int board_early_init_f(void)
{
sc_pm_clock_rate_t rate;
diff --git a/board/toradex/common/tdx-cfg-block.c b/board/toradex/common/tdx-cfg-block.c
index bf27b2f..adab0a0 100644
--- a/board/toradex/common/tdx-cfg-block.c
+++ b/board/toradex/common/tdx-cfg-block.c
@@ -16,7 +16,8 @@
defined(CONFIG_TARGET_COLIBRI_IMX6) || \
defined(CONFIG_TARGET_COLIBRI_IMX8X) || \
defined(CONFIG_TARGET_VERDIN_IMX8MM) || \
- defined(CONFIG_TARGET_VERDIN_IMX8MN)
+ defined(CONFIG_TARGET_VERDIN_IMX8MN) || \
+ defined(CONFIG_TARGET_VERDIN_IMX8MP)
#include <asm/arch/sys_proto.h>
#else
#define is_cpu_type(cpu) (0)
@@ -137,8 +138,12 @@
[53] = "Apalis iMX8 QuadXPlus 2GB ECC IT",
[54] = "Apalis iMX8 DualXPlus 1GB",
[55] = "Verdin iMX8M Mini Quad 2GB Wi-Fi / BT IT",
- [56] = "Verdin iMX8M Nano SoloLite 1GB", /* not currently on sale */
+ [56] = "Verdin iMX8M Nano Quad 1GB Wi-Fi / BT", /* not currently on sale */
[57] = "Verdin iMX8M Mini DualLite 1GB",
+ [58] = "Verdin iMX8M Plus Quad 4GB Wi-Fi / BT IT",
+ [59] = "Verdin iMX8M Mini Quad 2GB IT",
+ [60] = "Verdin iMX8M Mini DualLite 1GB WB IT",
+ [61] = "Verdin iMX8M Plus Quad 2GB",
};
const char * const toradex_carrier_boards[] = {
@@ -361,21 +366,15 @@
if (cpu_is_pxa27x())
sprintf(message, "Is the module the 312 MHz version? [y/N] ");
-#if !defined(CONFIG_TARGET_VERDIN_IMX8MM) || !defined(CONFIG_TARGET_VERDIN_IMX8MN)
- else
- sprintf(message, "Is the module an IT version? [y/N] ");
-
- len = cli_readline(message);
- it = console_buffer[0];
-#else
else
it = 'y';
-#endif
#if defined(CONFIG_TARGET_APALIS_IMX8) || \
defined(CONFIG_TARGET_APALIS_IMX8X) || \
defined(CONFIG_TARGET_COLIBRI_IMX6ULL) || \
- defined(CONFIG_TARGET_COLIBRI_IMX8X)
+ defined(CONFIG_TARGET_COLIBRI_IMX8X) || \
+ defined(CONFIG_TARGET_VERDIN_IMX8MM) || \
+ defined(CONFIG_TARGET_VERDIN_IMX8MP)
sprintf(message, "Does the module have Wi-Fi / Bluetooth? [y/N] ");
len = cli_readline(message);
wb = console_buffer[0];
@@ -424,12 +423,6 @@
tdx_hw_tag.prodid = COLIBRI_IMX7D;
else if (!strcmp("imx7s", soc))
tdx_hw_tag.prodid = COLIBRI_IMX7S;
- else if (is_cpu_type(MXC_CPU_IMX8MM))
- tdx_hw_tag.prodid = VERDIN_IMX8MMQ_WIFI_BT_IT;
- else if (is_cpu_type(MXC_CPU_IMX8MMDL))
- tdx_hw_tag.prodid = VERDIN_IMX8MMDL;
- else if (is_cpu_type(MXC_CPU_IMX8MN))
- tdx_hw_tag.prodid = VERDIN_IMX8MNSL;
else if (is_cpu_type(MXC_CPU_IMX8QM)) {
if (it == 'y' || it == 'Y') {
if (wb == 'y' || wb == 'Y')
@@ -465,6 +458,23 @@
tdx_hw_tag.prodid = COLIBRI_IMX8DX;
}
#endif
+ } else if (is_cpu_type(MXC_CPU_IMX8MMDL)) {
+ if (wb == 'y' || wb == 'Y')
+ tdx_hw_tag.prodid = VERDIN_IMX8MMDL_WIFI_BT_IT;
+ else
+ tdx_hw_tag.prodid = VERDIN_IMX8MMDL;
+ } else if (is_cpu_type(MXC_CPU_IMX8MM)) {
+ if (wb == 'y' || wb == 'Y')
+ tdx_hw_tag.prodid = VERDIN_IMX8MMQ_WIFI_BT_IT;
+ else
+ tdx_hw_tag.prodid = VERDIN_IMX8MMQ_IT;
+ } else if (is_cpu_type(MXC_CPU_IMX8MN)) {
+ tdx_hw_tag.prodid = VERDIN_IMX8MNQ_WIFI_BT;
+ } else if (is_cpu_type(MXC_CPU_IMX8MP)) {
+ if (wb == 'y' || wb == 'Y')
+ tdx_hw_tag.prodid = VERDIN_IMX8MPQ_WIFI_BT_IT;
+ else
+ tdx_hw_tag.prodid = VERDIN_IMX8MPQ;
} else if (!strcmp("tegra20", soc)) {
if (it == 'y' || it == 'Y')
if (gd->ram_size == 0x10000000)
diff --git a/board/toradex/common/tdx-cfg-block.h b/board/toradex/common/tdx-cfg-block.h
index 8f91d9a..9debd5f 100644
--- a/board/toradex/common/tdx-cfg-block.h
+++ b/board/toradex/common/tdx-cfg-block.h
@@ -75,9 +75,13 @@
COLIBRI_IMX8DX,
APALIS_IMX8QXP,
APALIS_IMX8DXP,
- VERDIN_IMX8MMQ_WIFI_BT_IT,
- VERDIN_IMX8MNSL,
+ VERDIN_IMX8MMQ_WIFI_BT_IT, /* 55 */
+ VERDIN_IMX8MNQ_WIFI_BT,
VERDIN_IMX8MMDL,
+ VERDIN_IMX8MPQ_WIFI_BT_IT,
+ VERDIN_IMX8MMQ_IT,
+ VERDIN_IMX8MMDL_WIFI_BT_IT, /* 60 */
+ VERDIN_IMX8MPQ,
};
enum {
diff --git a/board/toradex/verdin-imx8mm/spl.c b/board/toradex/verdin-imx8mm/spl.c
index cc78c56..72e2e09 100644
--- a/board/toradex/verdin-imx8mm/spl.c
+++ b/board/toradex/verdin-imx8mm/spl.c
@@ -21,12 +21,16 @@
#include <dm/uclass.h>
#include <dm/uclass-internal.h>
#include <hang.h>
+#include <i2c.h>
#include <power/bd71837.h>
+#include <power/pca9450.h>
#include <power/pmic.h>
#include <spl.h>
DECLARE_GLOBAL_DATA_PTR;
+#define I2C_PMIC_BUS_ID 1
+
int spl_board_boot_device(enum boot_device boot_dev_spl)
{
switch (boot_dev_spl) {
@@ -101,33 +105,29 @@
struct udevice *dev;
int ret;
- ret = pmic_get("pmic@4b", &dev);
- if (ret == -ENODEV) {
- puts("No pmic\n");
- return 0;
- }
- if (ret != 0)
- return ret;
+ if (IS_ENABLED(CONFIG_SPL_DM_PMIC_PCA9450)) {
+ ret = pmic_get("pmic", &dev);
+ if (ret == -ENODEV) {
+ puts("No pmic found\n");
+ return ret;
+ }
- /* decrease RESET key long push time from the default 10s to 10ms */
- pmic_reg_write(dev, BD718XX_PWRONCONFIG1, 0x0);
+ if (ret != 0)
+ return ret;
- /* unlock the PMIC regs */
- pmic_reg_write(dev, BD718XX_REGLOCK, 0x1);
+ /* BUCKxOUT_DVS0/1 control BUCK123 output, clear PRESET_EN */
+ pmic_reg_write(dev, PCA9450_BUCK123_DVS, 0x29);
- /* increase VDD_SOC to typical value 0.85v before first DRAM access */
- pmic_reg_write(dev, BD718XX_BUCK1_VOLT_RUN, 0x0f);
+ /* increase VDD_DRAM to 0.975v for 1.5Ghz DDR */
+ pmic_reg_write(dev, PCA9450_BUCK3OUT_DVS0, 0x1c);
- /* increase VDD_DRAM to 0.975v for 3Ghz DDR */
- pmic_reg_write(dev, BD718XX_1ST_NODVS_BUCK_VOLT, 0x83);
+ /* set WDOG_B_CFG to cold reset */
+ pmic_reg_write(dev, PCA9450_RESET_CTRL, 0xA1);
-#ifndef CONFIG_IMX8M_LPDDR4
- /* increase NVCC_DRAM_1V2 to 1.2v for DDR4 */
- pmic_reg_write(dev, BD718XX_4TH_NODVS_BUCK_VOLT, 0x28);
-#endif
+ pmic_reg_write(dev, PCA9450_CONFIG2, 0x1);
- /* lock the PMIC regs */
- pmic_reg_write(dev, BD718XX_REGLOCK, 0x11);
+ return 0;
+ }
return 0;
}
diff --git a/board/toradex/verdin-imx8mm/verdin-imx8mm.c b/board/toradex/verdin-imx8mm/verdin-imx8mm.c
index 66950ed..7cfae87 100644
--- a/board/toradex/verdin-imx8mm/verdin-imx8mm.c
+++ b/board/toradex/verdin-imx8mm/verdin-imx8mm.c
@@ -8,12 +8,22 @@
#include <asm/arch/clock.h>
#include <asm/arch/sys_proto.h>
#include <asm/io.h>
+#include <i2c.h>
#include <miiphy.h>
#include <netdev.h>
#include <micrel.h>
+#include "../common/tdx-cfg-block.h"
+
DECLARE_GLOBAL_DATA_PTR;
+#define I2C_PMIC 0
+
+enum pcb_rev_t {
+ PCB_VERSION_1_0,
+ PCB_VERSION_1_1
+};
+
#if IS_ENABLED(CONFIG_FEC_MXC)
static int setup_fec(void)
{
@@ -104,8 +114,79 @@
return devno;
}
+static enum pcb_rev_t get_pcb_revision(void)
+{
+ struct udevice *bus;
+ struct udevice *i2c_dev = NULL;
+ int ret;
+ u8 is_bd71837 = 0;
+
+ ret = uclass_get_device_by_seq(UCLASS_I2C, I2C_PMIC, &bus);
+ if (!ret)
+ ret = dm_i2c_probe(bus, 0x4b, 0, &i2c_dev);
+ if (!ret)
+ ret = dm_i2c_read(i2c_dev, 0x0, &is_bd71837, 1);
+
+ /* BD71837_REV, High Nibble is major version, fix 1010 */
+ is_bd71837 = !ret && ((is_bd71837 & 0xf0) == 0xa0);
+ return is_bd71837 ? PCB_VERSION_1_0 : PCB_VERSION_1_1;
+}
+
+static void select_dt_from_module_version(void)
+{
+ char variant[32];
+ char *env_variant = env_get("variant");
+ int is_wifi = 0;
+
+ if (IS_ENABLED(CONFIG_TDX_CFG_BLOCK)) {
+ /*
+ * If we have a valid config block and it says we are a
+ * module with Wi-Fi/Bluetooth make sure we use the -wifi
+ * device tree.
+ */
+ is_wifi = (tdx_hw_tag.prodid == VERDIN_IMX8MMQ_WIFI_BT_IT) ||
+ (tdx_hw_tag.prodid == VERDIN_IMX8MMDL_WIFI_BT_IT);
+ }
+
+ switch (get_pcb_revision()) {
+ case PCB_VERSION_1_0:
+ printf("Detected a V1.0 module\n");
+ if (is_wifi)
+ strncpy(&variant[0], "wifi", sizeof(variant));
+ else
+ strncpy(&variant[0], "nonwifi", sizeof(variant));
+ break;
+ default:
+ if (is_wifi)
+ strncpy(&variant[0], "wifi-v1.1", sizeof(variant));
+ else
+ strncpy(&variant[0], "nonwifi-v1.1", sizeof(variant));
+ break;
+ }
+
+ if (strcmp(variant, env_variant)) {
+ printf("Setting variant to %s\n", variant);
+ env_set("variant", variant);
+
+ if (IS_ENABLED(CONFIG_ENV_IS_NOWHERE))
+ env_save();
+ }
+}
+
int board_late_init(void)
{
+ select_dt_from_module_version();
+
+ return 0;
+}
+
+int board_phys_sdram_size(phys_size_t *size)
+{
+ if (!size)
+ return -EINVAL;
+
+ *size = get_ram_size((void *)PHYS_SDRAM, PHYS_SDRAM_SIZE);
+
return 0;
}
diff --git a/configs/apalis-imx8x_defconfig b/configs/apalis-imx8x_defconfig
new file mode 100644
index 0000000..e6aa575
--- /dev/null
+++ b/configs/apalis-imx8x_defconfig
@@ -0,0 +1,77 @@
+CONFIG_ARM=y
+CONFIG_ARCH_IMX8=y
+CONFIG_SYS_TEXT_BASE=0x80020000
+CONFIG_SYS_MALLOC_F_LEN=0x4000
+CONFIG_NR_DRAM_BANKS=3
+CONFIG_ENV_SIZE=0x2000
+CONFIG_ENV_OFFSET=0xFFFFDE00
+CONFIG_DM_GPIO=y
+CONFIG_TARGET_APALIS_IMX8X=y
+CONFIG_DEFAULT_DEVICE_TREE="fsl-imx8qxp-apalis"
+CONFIG_DISTRO_DEFAULTS=y
+CONFIG_FIT=y
+CONFIG_OF_SYSTEM_SETUP=y
+CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/toradex/apalis-imx8x/apalis-imx8x-imximage.cfg"
+CONFIG_BOOTDELAY=1
+CONFIG_LOG=y
+# CONFIG_DISPLAY_BOARDINFO is not set
+CONFIG_BOARD_EARLY_INIT_F=y
+CONFIG_SYS_PROMPT="Apalis iMX8X # "
+CONFIG_CMD_CPU=y
+# CONFIG_BOOTM_NETBSD is not set
+CONFIG_CMD_ASKENV=y
+CONFIG_CMD_MEMTEST=y
+CONFIG_SYS_MEMTEST_START=0x88000000
+CONFIG_SYS_MEMTEST_END=0x89000000
+CONFIG_CMD_CLK=y
+CONFIG_CMD_DM=y
+CONFIG_CMD_GPIO=y
+CONFIG_CMD_I2C=y
+CONFIG_CMD_MMC=y
+CONFIG_CMD_PCI=y
+CONFIG_CMD_CACHE=y
+CONFIG_CMD_UUID=y
+CONFIG_CMD_EXT4_WRITE=y
+CONFIG_ENV_OVERWRITE=y
+CONFIG_ENV_IS_IN_MMC=y
+CONFIG_SYS_RELOC_GD_ENV_ADDR=y
+CONFIG_SYS_MMC_ENV_PART=1
+CONFIG_VERSION_VARIABLE=y
+CONFIG_NET_RANDOM_ETHADDR=y
+CONFIG_IP_DEFRAG=y
+CONFIG_TFTP_BLOCKSIZE=4096
+CONFIG_BOOTCOUNT_LIMIT=y
+CONFIG_BOOTCOUNT_ENV=y
+CONFIG_CLK_IMX8=y
+CONFIG_CPU=y
+CONFIG_MXC_GPIO=y
+CONFIG_DM_I2C=y
+CONFIG_SYS_I2C_IMX_LPI2C=y
+CONFIG_I2C_MUX=y
+CONFIG_I2C_MUX_PCA954x=y
+CONFIG_MISC=y
+CONFIG_DM_MMC=y
+CONFIG_FSL_USDHC=y
+CONFIG_PHYLIB=y
+CONFIG_PHY_ADDR_ENABLE=y
+CONFIG_PHY_MICREL=y
+CONFIG_PHY_MICREL_KSZ90X1=y
+CONFIG_DM_ETH=y
+CONFIG_FEC_MXC_SHARE_MDIO=y
+CONFIG_FEC_MXC_MDIO_BASE=0x5B040000
+CONFIG_FEC_MXC=y
+CONFIG_MII=y
+CONFIG_PCI=y
+CONFIG_DM_PCI=y
+CONFIG_PINCTRL=y
+CONFIG_PINCTRL_IMX8=y
+CONFIG_POWER_DOMAIN=y
+CONFIG_IMX8_POWER_DOMAIN=y
+CONFIG_DM_REGULATOR=y
+CONFIG_DM_REGULATOR_FIXED=y
+CONFIG_DM_REGULATOR_GPIO=y
+CONFIG_DM_SERIAL=y
+CONFIG_FSL_LPUART=y
+CONFIG_DM_THERMAL=y
+CONFIG_IMX_SCU_THERMAL=y
+# CONFIG_EFI_LOADER is not set
diff --git a/configs/aristainetos2_defconfig b/configs/aristainetos2_defconfig
deleted file mode 100644
index 35e4b09..0000000
--- a/configs/aristainetos2_defconfig
+++ /dev/null
@@ -1,121 +0,0 @@
-CONFIG_ARM=y
-CONFIG_ARCH_MX6=y
-CONFIG_SYS_TEXT_BASE=0x17800000
-CONFIG_SYS_MALLOC_F_LEN=0xe000
-CONFIG_NR_DRAM_BANKS=1
-CONFIG_ENV_OFFSET=0xD0000
-CONFIG_MX6DL=y
-CONFIG_TARGET_ARISTAINETOS2=y
-CONFIG_DM_GPIO=y
-CONFIG_ENV_OFFSET_REDUND=0xE0000
-CONFIG_IMX_HAB=y
-# CONFIG_CMD_DEKBLOB is not set
-# CONFIG_CMD_NANDBCB is not set
-CONFIG_DEFAULT_DEVICE_TREE="imx6dl-aristainetos2_4"
-CONFIG_FIT=y
-CONFIG_SUPPORT_RAW_INITRD=y
-CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/aristainetos/aristainetos2.cfg"
-CONFIG_BOOTDELAY=3
-CONFIG_AUTOBOOT_KEYED=y
-CONFIG_AUTOBOOT_ENCRYPTION=y
-CONFIG_AUTOBOOT_STOP_STR_SHA256="30bb0bce5f77da71a6e8e436fe40af54bc823db9501ae170f77e9992499d88fb"
-CONFIG_USE_BOOTCOMMAND=y
-CONFIG_BOOTCOMMAND="run ari_boot"
-# CONFIG_CONSOLE_MUX is not set
-CONFIG_SYS_CONSOLE_IS_IN_ENV=y
-CONFIG_BOARD_TYPES=y
-CONFIG_BOARD_EARLY_INIT_F=y
-CONFIG_HUSH_PARSER=y
-CONFIG_CMD_BOOTZ=y
-# CONFIG_BOOTM_NETBSD is not set
-# CONFIG_BOOTM_PLAN9 is not set
-# CONFIG_BOOTM_RTEMS is not set
-# CONFIG_BOOTM_VXWORKS is not set
-# CONFIG_CMD_FLASH is not set
-CONFIG_CMD_GPIO=y
-CONFIG_CMD_I2C=y
-CONFIG_CMD_MMC=y
-CONFIG_CMD_NAND_TRIMFFS=y
-# CONFIG_CMD_PINMUX is not set
-# CONFIG_CMD_SATA is not set
-CONFIG_CMD_USB=y
-CONFIG_CMD_DHCP=y
-CONFIG_CMD_MII=y
-CONFIG_CMD_PING=y
-CONFIG_CMD_BMP=y
-CONFIG_CMD_CACHE=y
-# CONFIG_CMD_HASH is not set
-CONFIG_CMD_EXT2=y
-CONFIG_CMD_EXT4=y
-CONFIG_CMD_EXT4_WRITE=y
-CONFIG_CMD_FAT=y
-CONFIG_CMD_FS_GENERIC=y
-CONFIG_CMD_MTDPARTS=y
-CONFIG_CMD_UBI=y
-CONFIG_OF_CONTROL=y
-CONFIG_OF_LIST="imx6dl-aristainetos2_4 imx6dl-aristainetos2_7"
-CONFIG_DTB_RESELECT=y
-CONFIG_MULTI_DTB_FIT=y
-CONFIG_ENV_OVERWRITE=y
-CONFIG_ENV_IS_IN_SPI_FLASH=y
-CONFIG_ENV_SPI_EARLY=y
-CONFIG_SYS_REDUNDAND_ENVIRONMENT=y
-CONFIG_SYS_RELOC_GD_ENV_ADDR=y
-CONFIG_VERSION_VARIABLE=y
-CONFIG_BOUNCE_BUFFER=y
-CONFIG_GPIO_HOG=y
-CONFIG_DM_GPIO_LOOKUP_LABEL=y
-CONFIG_DM_PCA953X=y
-CONFIG_DM_I2C=y
-CONFIG_LED=y
-CONFIG_LED_GPIO=y
-CONFIG_MISC=y
-CONFIG_I2C_EEPROM=y
-CONFIG_DM_MMC=y
-CONFIG_FSL_USDHC=y
-CONFIG_MTD=y
-CONFIG_MTD_RAW_NAND=y
-CONFIG_NAND_MXS=y
-CONFIG_DM_SPI_FLASH=y
-CONFIG_SF_DEFAULT_BUS=3
-CONFIG_SF_DEFAULT_CS=1
-CONFIG_SF_DEFAULT_MODE=0
-CONFIG_SF_DEFAULT_SPEED=20000000
-CONFIG_SPI_FLASH_STMICRO=y
-CONFIG_SPI_FLASH_MTD=y
-CONFIG_MTD_UBI_FASTMAP=y
-CONFIG_MTD_UBI_FASTMAP_AUTOCONVERT=1
-CONFIG_PHYLIB=y
-CONFIG_PHY_MICREL=y
-CONFIG_PHY_MICREL_KSZ90X1=y
-CONFIG_DM_ETH=y
-CONFIG_MII=y
-CONFIG_PHY=y
-CONFIG_PINCTRL=y
-CONFIG_PINCTRL_IMX6=y
-CONFIG_DM_PMIC=y
-CONFIG_DM_REGULATOR=y
-CONFIG_DM_REGULATOR_FIXED=y
-CONFIG_DM_PWM=y
-CONFIG_PWM_IMX=y
-CONFIG_DM_RTC=y
-CONFIG_RTC_DS1307=y
-CONFIG_DM_SERIAL=y
-CONFIG_SPI=y
-CONFIG_DM_SPI=y
-CONFIG_MXC_SPI=y
-CONFIG_SYSRESET=y
-CONFIG_SYSRESET_WATCHDOG=y
-CONFIG_USB=y
-CONFIG_DM_USB=y
-CONFIG_USB_STORAGE=y
-CONFIG_DM_VIDEO=y
-CONFIG_SYS_WHITE_ON_BLACK=y
-CONFIG_DISPLAY=y
-CONFIG_VIDEO_IPUV3=y
-CONFIG_SPLASH_SCREEN=y
-CONFIG_SPLASH_SCREEN_ALIGN=y
-CONFIG_VIDEO_BMP_RLE8=y
-CONFIG_BMP_16BPP=y
-CONFIG_IMX_WATCHDOG=y
-# CONFIG_EFI_LOADER is not set
diff --git a/configs/aristainetos2b_defconfig b/configs/aristainetos2b_defconfig
deleted file mode 100644
index d47a074..0000000
--- a/configs/aristainetos2b_defconfig
+++ /dev/null
@@ -1,115 +0,0 @@
-CONFIG_ARM=y
-CONFIG_ARCH_MX6=y
-CONFIG_SYS_TEXT_BASE=0x17800000
-CONFIG_SYS_MALLOC_F_LEN=0xe000
-CONFIG_NR_DRAM_BANKS=1
-CONFIG_ENV_OFFSET=0xD0000
-CONFIG_MX6DL=y
-CONFIG_TARGET_ARISTAINETOS2B=y
-CONFIG_DM_GPIO=y
-CONFIG_ENV_OFFSET_REDUND=0xE0000
-CONFIG_IMX_HAB=y
-# CONFIG_CMD_DEKBLOB is not set
-CONFIG_DEFAULT_DEVICE_TREE="imx6dl-aristainetos2b_4"
-CONFIG_FIT=y
-CONFIG_SUPPORT_RAW_INITRD=y
-CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/aristainetos/aristainetos2.cfg"
-CONFIG_BOOTDELAY=3
-CONFIG_AUTOBOOT_KEYED=y
-CONFIG_AUTOBOOT_ENCRYPTION=y
-CONFIG_AUTOBOOT_STOP_STR_SHA256="30bb0bce5f77da71a6e8e436fe40af54bc823db9501ae170f77e9992499d88fb"
-CONFIG_USE_BOOTCOMMAND=y
-CONFIG_BOOTCOMMAND="run ari_boot"
-# CONFIG_CONSOLE_MUX is not set
-CONFIG_SYS_CONSOLE_IS_IN_ENV=y
-CONFIG_BOARD_TYPES=y
-CONFIG_BOARD_EARLY_INIT_F=y
-CONFIG_HUSH_PARSER=y
-CONFIG_CMD_BOOTZ=y
-# CONFIG_BOOTM_NETBSD is not set
-# CONFIG_BOOTM_PLAN9 is not set
-# CONFIG_BOOTM_RTEMS is not set
-# CONFIG_BOOTM_VXWORKS is not set
-# CONFIG_CMD_FLASH is not set
-CONFIG_CMD_GPIO=y
-CONFIG_CMD_I2C=y
-CONFIG_CMD_MMC=y
-# CONFIG_CMD_PINMUX is not set
-# CONFIG_CMD_SATA is not set
-CONFIG_CMD_USB=y
-CONFIG_CMD_DHCP=y
-CONFIG_CMD_MII=y
-CONFIG_CMD_PING=y
-CONFIG_CMD_BMP=y
-CONFIG_CMD_CACHE=y
-# CONFIG_CMD_HASH is not set
-CONFIG_CMD_EXT2=y
-CONFIG_CMD_EXT4=y
-CONFIG_CMD_EXT4_WRITE=y
-CONFIG_CMD_FAT=y
-CONFIG_CMD_FS_GENERIC=y
-CONFIG_CMD_MTDPARTS=y
-CONFIG_CMD_UBI=y
-CONFIG_OF_CONTROL=y
-CONFIG_OF_LIST="imx6dl-aristainetos2b_4 imx6dl-aristainetos2b_7"
-CONFIG_DTB_RESELECT=y
-CONFIG_MULTI_DTB_FIT=y
-CONFIG_ENV_OVERWRITE=y
-CONFIG_ENV_IS_IN_SPI_FLASH=y
-CONFIG_ENV_SPI_EARLY=y
-CONFIG_SYS_REDUNDAND_ENVIRONMENT=y
-CONFIG_SYS_RELOC_GD_ENV_ADDR=y
-CONFIG_VERSION_VARIABLE=y
-CONFIG_BOUNCE_BUFFER=y
-CONFIG_GPIO_HOG=y
-CONFIG_DM_GPIO_LOOKUP_LABEL=y
-CONFIG_DM_PCA953X=y
-CONFIG_DM_I2C=y
-CONFIG_LED=y
-CONFIG_LED_GPIO=y
-CONFIG_MISC=y
-CONFIG_I2C_EEPROM=y
-CONFIG_DM_MMC=y
-CONFIG_FSL_USDHC=y
-CONFIG_MTD=y
-CONFIG_DM_SPI_FLASH=y
-CONFIG_SF_DEFAULT_MODE=0
-CONFIG_SF_DEFAULT_SPEED=20000000
-CONFIG_SPI_FLASH_STMICRO=y
-CONFIG_SPI_FLASH_MTD=y
-CONFIG_MTD_UBI_FASTMAP=y
-CONFIG_MTD_UBI_FASTMAP_AUTOCONVERT=1
-CONFIG_PHYLIB=y
-CONFIG_PHY_MICREL=y
-CONFIG_PHY_MICREL_KSZ90X1=y
-CONFIG_DM_ETH=y
-CONFIG_MII=y
-CONFIG_PHY=y
-CONFIG_PINCTRL=y
-CONFIG_PINCTRL_IMX6=y
-CONFIG_DM_PMIC=y
-CONFIG_DM_REGULATOR=y
-CONFIG_DM_REGULATOR_FIXED=y
-CONFIG_DM_PWM=y
-CONFIG_PWM_IMX=y
-CONFIG_DM_RTC=y
-CONFIG_RTC_DS1307=y
-CONFIG_DM_SERIAL=y
-CONFIG_SPI=y
-CONFIG_DM_SPI=y
-CONFIG_MXC_SPI=y
-CONFIG_SYSRESET=y
-CONFIG_SYSRESET_WATCHDOG=y
-CONFIG_USB=y
-CONFIG_DM_USB=y
-CONFIG_USB_STORAGE=y
-CONFIG_DM_VIDEO=y
-CONFIG_SYS_WHITE_ON_BLACK=y
-CONFIG_DISPLAY=y
-CONFIG_VIDEO_IPUV3=y
-CONFIG_SPLASH_SCREEN=y
-CONFIG_SPLASH_SCREEN_ALIGN=y
-CONFIG_VIDEO_BMP_RLE8=y
-CONFIG_BMP_16BPP=y
-CONFIG_IMX_WATCHDOG=y
-# CONFIG_EFI_LOADER is not set
diff --git a/configs/aristainetos2c_defconfig b/configs/aristainetos2c_defconfig
index 50cadb7..df0b26d 100644
--- a/configs/aristainetos2c_defconfig
+++ b/configs/aristainetos2c_defconfig
@@ -1,7 +1,7 @@
CONFIG_ARM=y
CONFIG_ARCH_MX6=y
CONFIG_SYS_TEXT_BASE=0x17800000
-CONFIG_SYS_MALLOC_F_LEN=0xe000
+CONFIG_SYS_MALLOC_F_LEN=0x13000
CONFIG_NR_DRAM_BANKS=1
CONFIG_ENV_OFFSET=0xD0000
CONFIG_MX6DL=y
@@ -10,11 +10,11 @@
CONFIG_ENV_OFFSET_REDUND=0xE0000
CONFIG_IMX_HAB=y
# CONFIG_CMD_DEKBLOB is not set
-CONFIG_DEFAULT_DEVICE_TREE="imx6dl-aristainetos2c_4"
+CONFIG_DEFAULT_DEVICE_TREE="imx6dl-aristainetos2c_7"
CONFIG_FIT=y
CONFIG_SUPPORT_RAW_INITRD=y
CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/aristainetos/aristainetos2.cfg"
-CONFIG_BOOTDELAY=3
+CONFIG_BOOTDELAY=-2
CONFIG_AUTOBOOT_KEYED=y
CONFIG_AUTOBOOT_ENCRYPTION=y
CONFIG_AUTOBOOT_STOP_STR_SHA256="30bb0bce5f77da71a6e8e436fe40af54bc823db9501ae170f77e9992499d88fb"
@@ -30,6 +30,8 @@
# CONFIG_BOOTM_PLAN9 is not set
# CONFIG_BOOTM_RTEMS is not set
# CONFIG_BOOTM_VXWORKS is not set
+CONFIG_CMD_ENV_FLAGS=y
+CONFIG_CMD_NVEDIT_INFO=y
# CONFIG_CMD_FLASH is not set
CONFIG_CMD_GPIO=y
CONFIG_CMD_I2C=y
@@ -51,14 +53,17 @@
CONFIG_CMD_MTDPARTS=y
CONFIG_CMD_UBI=y
CONFIG_OF_CONTROL=y
-CONFIG_OF_LIST="imx6dl-aristainetos2c_4 imx6dl-aristainetos2c_7"
CONFIG_DTB_RESELECT=y
CONFIG_MULTI_DTB_FIT=y
CONFIG_ENV_OVERWRITE=y
+CONFIG_ENV_IS_NOWHERE=y
CONFIG_ENV_IS_IN_SPI_FLASH=y
CONFIG_ENV_SPI_EARLY=y
CONFIG_SYS_REDUNDAND_ENVIRONMENT=y
CONFIG_SYS_RELOC_GD_ENV_ADDR=y
+CONFIG_ENV_APPEND=y
+CONFIG_ENV_WRITEABLE_LIST=y
+CONFIG_ENV_ACCESS_IGNORE_FORCE=y
CONFIG_VERSION_VARIABLE=y
CONFIG_BOUNCE_BUFFER=y
CONFIG_APBH_DMA=y
diff --git a/configs/aristainetos2bcsl_defconfig b/configs/aristainetos2ccslb_defconfig
similarity index 84%
rename from configs/aristainetos2bcsl_defconfig
rename to configs/aristainetos2ccslb_defconfig
index 3013962..0156493 100644
--- a/configs/aristainetos2bcsl_defconfig
+++ b/configs/aristainetos2ccslb_defconfig
@@ -1,20 +1,20 @@
CONFIG_ARM=y
CONFIG_ARCH_MX6=y
CONFIG_SYS_TEXT_BASE=0x17800000
-CONFIG_SYS_MALLOC_F_LEN=0xe000
+CONFIG_SYS_MALLOC_F_LEN=0x13000
CONFIG_NR_DRAM_BANKS=1
CONFIG_ENV_OFFSET=0xD0000
CONFIG_MX6DL=y
-CONFIG_TARGET_ARISTAINETOS2BCSL=y
+CONFIG_TARGET_ARISTAINETOS2CCSLB=y
CONFIG_DM_GPIO=y
CONFIG_ENV_OFFSET_REDUND=0xE0000
CONFIG_IMX_HAB=y
# CONFIG_CMD_DEKBLOB is not set
-CONFIG_DEFAULT_DEVICE_TREE="imx6dl-aristainetos2b_csl_4"
+CONFIG_DEFAULT_DEVICE_TREE="imx6dl-aristainetos2c_cslb_7"
CONFIG_FIT=y
CONFIG_SUPPORT_RAW_INITRD=y
CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/aristainetos/aristainetos2.cfg"
-CONFIG_BOOTDELAY=3
+CONFIG_BOOTDELAY=-2
CONFIG_AUTOBOOT_KEYED=y
CONFIG_AUTOBOOT_ENCRYPTION=y
CONFIG_AUTOBOOT_STOP_STR_SHA256="30bb0bce5f77da71a6e8e436fe40af54bc823db9501ae170f77e9992499d88fb"
@@ -30,6 +30,8 @@
# CONFIG_BOOTM_PLAN9 is not set
# CONFIG_BOOTM_RTEMS is not set
# CONFIG_BOOTM_VXWORKS is not set
+CONFIG_CMD_ENV_FLAGS=y
+CONFIG_CMD_NVEDIT_INFO=y
# CONFIG_CMD_FLASH is not set
CONFIG_CMD_GPIO=y
CONFIG_CMD_I2C=y
@@ -51,16 +53,22 @@
CONFIG_CMD_MTDPARTS=y
CONFIG_CMD_UBI=y
CONFIG_OF_CONTROL=y
-CONFIG_OF_LIST="imx6dl-aristainetos2b_csl_4 imx6dl-aristainetos2b_csl_7"
CONFIG_DTB_RESELECT=y
CONFIG_MULTI_DTB_FIT=y
CONFIG_ENV_OVERWRITE=y
+CONFIG_ENV_IS_NOWHERE=y
CONFIG_ENV_IS_IN_SPI_FLASH=y
CONFIG_ENV_SPI_EARLY=y
CONFIG_SYS_REDUNDAND_ENVIRONMENT=y
CONFIG_SYS_RELOC_GD_ENV_ADDR=y
+CONFIG_ENV_APPEND=y
+CONFIG_ENV_WRITEABLE_LIST=y
+CONFIG_ENV_ACCESS_IGNORE_FORCE=y
CONFIG_VERSION_VARIABLE=y
CONFIG_BOUNCE_BUFFER=y
+CONFIG_APBH_DMA=y
+CONFIG_APBH_DMA_BURST=y
+CONFIG_APBH_DMA_BURST8=y
CONFIG_GPIO_HOG=y
CONFIG_DM_GPIO_LOOKUP_LABEL=y
CONFIG_DM_PCA953X=y
@@ -88,7 +96,10 @@
CONFIG_PINCTRL=y
CONFIG_PINCTRL_IMX6=y
CONFIG_DM_PMIC=y
+# CONFIG_SPL_PMIC_CHILDREN is not set
+CONFIG_DM_PMIC_DA9063=y
CONFIG_DM_REGULATOR=y
+CONFIG_DM_REGULATOR_DA9063=y
CONFIG_DM_REGULATOR_FIXED=y
CONFIG_DM_PWM=y
CONFIG_PWM_IMX=y
diff --git a/configs/cgtqmx6eval_defconfig b/configs/cgtqmx6eval_defconfig
index c3f6082..26f7466 100644
--- a/configs/cgtqmx6eval_defconfig
+++ b/configs/cgtqmx6eval_defconfig
@@ -71,6 +71,7 @@
CONFIG_MXC_UART=y
CONFIG_SPI=y
CONFIG_MXC_SPI=y
+CONFIG_IMX_THERMAL=y
CONFIG_USB=y
CONFIG_USB_STORAGE=y
CONFIG_USB_KEYBOARD=y
diff --git a/configs/colibri-imx6ull_defconfig b/configs/colibri-imx6ull_defconfig
index 273cb9d..5e18f66 100644
--- a/configs/colibri-imx6ull_defconfig
+++ b/configs/colibri-imx6ull_defconfig
@@ -84,6 +84,7 @@
CONFIG_DM_REGULATOR_FIXED=y
CONFIG_DM_SERIAL=y
CONFIG_MXC_UART=y
+CONFIG_IMX_THERMAL=y
CONFIG_USB=y
CONFIG_DM_USB=y
CONFIG_USB_GADGET=y
diff --git a/configs/colibri_imx7_defconfig b/configs/colibri_imx7_defconfig
index 42a9d63..71e331e 100644
--- a/configs/colibri_imx7_defconfig
+++ b/configs/colibri_imx7_defconfig
@@ -82,6 +82,7 @@
CONFIG_DM_PMIC=y
CONFIG_PMIC_RN5T567=y
CONFIG_MXC_UART=y
+CONFIG_IMX_THERMAL=y
CONFIG_USB=y
CONFIG_DM_USB=y
CONFIG_USB_EHCI_HCD=y
diff --git a/configs/colibri_imx7_emmc_defconfig b/configs/colibri_imx7_emmc_defconfig
index 81d83c7..c5a6c44 100644
--- a/configs/colibri_imx7_emmc_defconfig
+++ b/configs/colibri_imx7_emmc_defconfig
@@ -79,6 +79,7 @@
CONFIG_DM_PMIC=y
CONFIG_PMIC_RN5T567=y
CONFIG_MXC_UART=y
+CONFIG_IMX_THERMAL=y
CONFIG_USB=y
CONFIG_DM_USB=y
CONFIG_USB_EHCI_HCD=y
diff --git a/configs/gwventana_emmc_defconfig b/configs/gwventana_emmc_defconfig
index fd47aad..41e190b 100644
--- a/configs/gwventana_emmc_defconfig
+++ b/configs/gwventana_emmc_defconfig
@@ -81,6 +81,8 @@
CONFIG_PCI=y
CONFIG_DM_SERIAL=y
CONFIG_MXC_UART=y
+CONFIG_DM_THERMAL=y
+CONFIG_IMX_THERMAL=y
CONFIG_USB=y
CONFIG_USB_STORAGE=y
CONFIG_USB_KEYBOARD=y
diff --git a/configs/gwventana_gw5904_defconfig b/configs/gwventana_gw5904_defconfig
index 2a87353..66b0441 100644
--- a/configs/gwventana_gw5904_defconfig
+++ b/configs/gwventana_gw5904_defconfig
@@ -85,6 +85,8 @@
CONFIG_PCI=y
CONFIG_DM_SERIAL=y
CONFIG_MXC_UART=y
+CONFIG_DM_THERMAL=y
+CONFIG_IMX_THERMAL=y
CONFIG_USB=y
CONFIG_USB_STORAGE=y
CONFIG_USB_KEYBOARD=y
diff --git a/configs/gwventana_nand_defconfig b/configs/gwventana_nand_defconfig
index d2fa6d7..9022f35 100644
--- a/configs/gwventana_nand_defconfig
+++ b/configs/gwventana_nand_defconfig
@@ -85,6 +85,8 @@
CONFIG_PCI=y
CONFIG_DM_SERIAL=y
CONFIG_MXC_UART=y
+CONFIG_DM_THERMAL=y
+CONFIG_IMX_THERMAL=y
CONFIG_USB=y
CONFIG_USB_STORAGE=y
CONFIG_USB_KEYBOARD=y
diff --git a/configs/liteboard_defconfig b/configs/liteboard_defconfig
index 40b5f27..b258880 100644
--- a/configs/liteboard_defconfig
+++ b/configs/liteboard_defconfig
@@ -56,6 +56,7 @@
CONFIG_PINCTRL_IMX6=y
CONFIG_DM_REGULATOR=y
CONFIG_MXC_UART=y
+CONFIG_IMX_THERMAL=y
CONFIG_USB=y
CONFIG_DM_USB=y
CONFIG_USB_STORAGE=y
diff --git a/configs/marsboard_defconfig b/configs/marsboard_defconfig
index 2257871..d2bd9c4 100644
--- a/configs/marsboard_defconfig
+++ b/configs/marsboard_defconfig
@@ -38,6 +38,7 @@
CONFIG_SPI=y
CONFIG_MXC_SPI=y
CONFIG_DM_THERMAL=y
+CONFIG_IMX_THERMAL=y
CONFIG_USB=y
CONFIG_USB_HOST_ETHER=y
CONFIG_USB_ETHER_ASIX=y
diff --git a/configs/mx6cuboxi_defconfig b/configs/mx6cuboxi_defconfig
index 4cabe90..a373d52 100644
--- a/configs/mx6cuboxi_defconfig
+++ b/configs/mx6cuboxi_defconfig
@@ -66,6 +66,7 @@
CONFIG_DM_REGULATOR_FIXED=y
CONFIG_MXC_UART=y
CONFIG_DM_THERMAL=y
+CONFIG_IMX_THERMAL=y
CONFIG_USB=y
CONFIG_DM_USB=y
CONFIG_USB_KEYBOARD=y
diff --git a/configs/mx6sabreauto_defconfig b/configs/mx6sabreauto_defconfig
index 3241ef8..4faf49e 100644
--- a/configs/mx6sabreauto_defconfig
+++ b/configs/mx6sabreauto_defconfig
@@ -89,6 +89,7 @@
CONFIG_SPI=y
CONFIG_DM_SPI=y
CONFIG_MXC_SPI=y
+CONFIG_IMX_THERMAL=y
CONFIG_USB=y
CONFIG_DM_USB=y
CONFIG_USB_STORAGE=y
diff --git a/configs/mx6sabresd_defconfig b/configs/mx6sabresd_defconfig
index baa304f..0016fba 100644
--- a/configs/mx6sabresd_defconfig
+++ b/configs/mx6sabresd_defconfig
@@ -100,6 +100,7 @@
CONFIG_SPI=y
CONFIG_DM_SPI=y
CONFIG_MXC_SPI=y
+CONFIG_IMX_THERMAL=y
CONFIG_USB=y
CONFIG_DM_USB=y
CONFIG_USB_GADGET=y
diff --git a/configs/mx6slevk_defconfig b/configs/mx6slevk_defconfig
index 171941a..5fd78c3 100644
--- a/configs/mx6slevk_defconfig
+++ b/configs/mx6slevk_defconfig
@@ -63,6 +63,7 @@
CONFIG_DM_SPI=y
CONFIG_MXC_SPI=y
CONFIG_DM_THERMAL=y
+CONFIG_IMX_THERMAL=y
CONFIG_USB=y
CONFIG_DM_USB=y
CONFIG_USB_STORAGE=y
diff --git a/configs/mx6slevk_spinor_defconfig b/configs/mx6slevk_spinor_defconfig
index 925886c..9777166 100644
--- a/configs/mx6slevk_spinor_defconfig
+++ b/configs/mx6slevk_spinor_defconfig
@@ -63,6 +63,7 @@
CONFIG_DM_SPI=y
CONFIG_MXC_SPI=y
CONFIG_DM_THERMAL=y
+CONFIG_IMX_THERMAL=y
CONFIG_USB=y
CONFIG_DM_USB=y
CONFIG_USB_STORAGE=y
diff --git a/configs/mx6slevk_spl_defconfig b/configs/mx6slevk_spl_defconfig
index b430955..4e44bc2 100644
--- a/configs/mx6slevk_spl_defconfig
+++ b/configs/mx6slevk_spl_defconfig
@@ -72,6 +72,7 @@
CONFIG_DM_SPI=y
CONFIG_MXC_SPI=y
CONFIG_DM_THERMAL=y
+CONFIG_IMX_THERMAL=y
CONFIG_USB=y
CONFIG_DM_USB=y
CONFIG_USB_STORAGE=y
diff --git a/configs/mx6sllevk_defconfig b/configs/mx6sllevk_defconfig
index d145874..1e446a3 100644
--- a/configs/mx6sllevk_defconfig
+++ b/configs/mx6sllevk_defconfig
@@ -48,6 +48,7 @@
CONFIG_DM_REGULATOR_FIXED=y
CONFIG_DM_REGULATOR_GPIO=y
CONFIG_MXC_UART=y
+CONFIG_IMX_THERMAL=y
CONFIG_USB=y
CONFIG_DM_USB=y
CONFIG_USB_STORAGE=y
diff --git a/configs/mx6sllevk_plugin_defconfig b/configs/mx6sllevk_plugin_defconfig
index 49d76a0..3e0e100 100644
--- a/configs/mx6sllevk_plugin_defconfig
+++ b/configs/mx6sllevk_plugin_defconfig
@@ -49,6 +49,7 @@
CONFIG_DM_REGULATOR_FIXED=y
CONFIG_DM_REGULATOR_GPIO=y
CONFIG_MXC_UART=y
+CONFIG_IMX_THERMAL=y
CONFIG_USB=y
CONFIG_DM_USB=y
CONFIG_USB_STORAGE=y
diff --git a/configs/mx6sxsabreauto_defconfig b/configs/mx6sxsabreauto_defconfig
index f645f75..0d8c07b 100644
--- a/configs/mx6sxsabreauto_defconfig
+++ b/configs/mx6sxsabreauto_defconfig
@@ -61,6 +61,7 @@
CONFIG_SPI=y
CONFIG_DM_SPI=y
CONFIG_FSL_QSPI=y
+CONFIG_IMX_THERMAL=y
CONFIG_USB=y
CONFIG_DM_USB=y
CONFIG_USB_STORAGE=y
diff --git a/configs/mx6sxsabresd_defconfig b/configs/mx6sxsabresd_defconfig
index 0e672ef..af5acc1 100644
--- a/configs/mx6sxsabresd_defconfig
+++ b/configs/mx6sxsabresd_defconfig
@@ -66,6 +66,7 @@
CONFIG_SPI=y
CONFIG_DM_SPI=y
CONFIG_FSL_QSPI=y
+CONFIG_IMX_THERMAL=y
CONFIG_USB=y
CONFIG_DM_USB=y
CONFIG_USB_STORAGE=y
diff --git a/configs/mx6ul_14x14_evk_defconfig b/configs/mx6ul_14x14_evk_defconfig
index f0a155a..878df78 100644
--- a/configs/mx6ul_14x14_evk_defconfig
+++ b/configs/mx6ul_14x14_evk_defconfig
@@ -80,6 +80,7 @@
CONFIG_DM_SPI=y
CONFIG_FSL_QSPI=y
CONFIG_SOFT_SPI=y
+CONFIG_IMX_THERMAL=y
CONFIG_USB=y
CONFIG_DM_USB=y
CONFIG_USB_STORAGE=y
diff --git a/configs/mx6ul_9x9_evk_defconfig b/configs/mx6ul_9x9_evk_defconfig
index 40bb371..9587ff8 100644
--- a/configs/mx6ul_9x9_evk_defconfig
+++ b/configs/mx6ul_9x9_evk_defconfig
@@ -75,6 +75,7 @@
CONFIG_DM_SPI=y
CONFIG_FSL_QSPI=y
CONFIG_SOFT_SPI=y
+CONFIG_IMX_THERMAL=y
CONFIG_USB=y
CONFIG_DM_USB=y
CONFIG_USB_STORAGE=y
diff --git a/configs/mx6ull_14x14_evk_defconfig b/configs/mx6ull_14x14_evk_defconfig
index 4fdbb91..fdd4483 100644
--- a/configs/mx6ull_14x14_evk_defconfig
+++ b/configs/mx6ull_14x14_evk_defconfig
@@ -58,3 +58,4 @@
CONFIG_SPI=y
CONFIG_DM_SPI=y
CONFIG_FSL_QSPI=y
+CONFIG_IMX_THERMAL=y
diff --git a/configs/mx6ull_14x14_evk_plugin_defconfig b/configs/mx6ull_14x14_evk_plugin_defconfig
index f8f8634..a6c30b3 100644
--- a/configs/mx6ull_14x14_evk_plugin_defconfig
+++ b/configs/mx6ull_14x14_evk_plugin_defconfig
@@ -57,3 +57,4 @@
CONFIG_SPI=y
CONFIG_DM_SPI=y
CONFIG_FSL_QSPI=y
+CONFIG_IMX_THERMAL=y
diff --git a/configs/mx6ulz_14x14_evk_defconfig b/configs/mx6ulz_14x14_evk_defconfig
index fac63f3..7180120 100644
--- a/configs/mx6ulz_14x14_evk_defconfig
+++ b/configs/mx6ulz_14x14_evk_defconfig
@@ -49,3 +49,4 @@
CONFIG_SPI=y
CONFIG_DM_SPI=y
CONFIG_FSL_QSPI=y
+CONFIG_IMX_THERMAL=y
diff --git a/configs/mx7dsabresd_defconfig b/configs/mx7dsabresd_defconfig
index e9e1f1e..3687a65 100644
--- a/configs/mx7dsabresd_defconfig
+++ b/configs/mx7dsabresd_defconfig
@@ -70,6 +70,7 @@
CONFIG_SPI=y
CONFIG_DM_SPI=y
CONFIG_SOFT_SPI=y
+CONFIG_IMX_THERMAL=y
CONFIG_USB=y
CONFIG_DM_USB=y
CONFIG_USB_EHCI_HCD=y
diff --git a/configs/mx7dsabresd_qspi_defconfig b/configs/mx7dsabresd_qspi_defconfig
index 6004128..c216b8c 100644
--- a/configs/mx7dsabresd_qspi_defconfig
+++ b/configs/mx7dsabresd_qspi_defconfig
@@ -77,6 +77,7 @@
CONFIG_DM_SPI=y
CONFIG_FSL_QSPI=y
CONFIG_SOFT_SPI=y
+CONFIG_IMX_THERMAL=y
CONFIG_USB=y
CONFIG_DM_USB=y
CONFIG_USB_EHCI_HCD=y
diff --git a/configs/myir_mys_6ulx_defconfig b/configs/myir_mys_6ulx_defconfig
index ef90f5f..e929216 100644
--- a/configs/myir_mys_6ulx_defconfig
+++ b/configs/myir_mys_6ulx_defconfig
@@ -66,6 +66,7 @@
CONFIG_MXC_UART=y
CONFIG_SYSINFO=y
CONFIG_SYSINFO_SMBIOS=y
+CONFIG_IMX_THERMAL=y
CONFIG_USB=y
CONFIG_DM_USB=y
CONFIG_USB_GADGET=y
diff --git a/configs/ot1200_defconfig b/configs/ot1200_defconfig
index a4fb70b..4f8a524 100644
--- a/configs/ot1200_defconfig
+++ b/configs/ot1200_defconfig
@@ -53,6 +53,7 @@
CONFIG_SPI=y
CONFIG_MXC_SPI=y
CONFIG_DM_THERMAL=y
+CONFIG_IMX_THERMAL=y
CONFIG_USB=y
CONFIG_USB_STORAGE=y
CONFIG_OF_LIBFDT=y
diff --git a/configs/ot1200_spl_defconfig b/configs/ot1200_spl_defconfig
index 81feb2f..ec3bf90 100644
--- a/configs/ot1200_spl_defconfig
+++ b/configs/ot1200_spl_defconfig
@@ -64,6 +64,7 @@
CONFIG_SPI=y
CONFIG_MXC_SPI=y
CONFIG_DM_THERMAL=y
+CONFIG_IMX_THERMAL=y
CONFIG_USB=y
CONFIG_USB_STORAGE=y
CONFIG_OF_LIBFDT=y
diff --git a/configs/pfla02_defconfig b/configs/pfla02_defconfig
index dc7151b..fa8ed31 100644
--- a/configs/pfla02_defconfig
+++ b/configs/pfla02_defconfig
@@ -71,4 +71,5 @@
CONFIG_SPI=y
CONFIG_MXC_SPI=y
CONFIG_DM_THERMAL=y
+CONFIG_IMX_THERMAL=y
CONFIG_OF_LIBFDT=y
diff --git a/configs/phycore_pcl063_defconfig b/configs/phycore_pcl063_defconfig
index ab92e3f..65239a0 100644
--- a/configs/phycore_pcl063_defconfig
+++ b/configs/phycore_pcl063_defconfig
@@ -59,6 +59,7 @@
CONFIG_DM_REGULATOR=y
CONFIG_DM_REGULATOR_FIXED=y
CONFIG_MXC_UART=y
+CONFIG_IMX_THERMAL=y
CONFIG_USB=y
CONFIG_DM_USB=y
CONFIG_USB_GADGET=y
diff --git a/configs/phycore_pcl063_ull_defconfig b/configs/phycore_pcl063_ull_defconfig
index 9cc0892..c57ca29 100644
--- a/configs/phycore_pcl063_ull_defconfig
+++ b/configs/phycore_pcl063_ull_defconfig
@@ -48,6 +48,7 @@
CONFIG_DM_REGULATOR=y
CONFIG_DM_REGULATOR_FIXED=y
CONFIG_MXC_UART=y
+CONFIG_IMX_THERMAL=y
CONFIG_USB=y
CONFIG_DM_USB=y
CONFIG_USB_GADGET=y
diff --git a/configs/pico-dwarf-imx7d_defconfig b/configs/pico-dwarf-imx7d_defconfig
index 085913e..dbfa2e0 100644
--- a/configs/pico-dwarf-imx7d_defconfig
+++ b/configs/pico-dwarf-imx7d_defconfig
@@ -67,6 +67,7 @@
CONFIG_PINCTRL=y
CONFIG_PINCTRL_IMX7=y
CONFIG_MXC_UART=y
+CONFIG_IMX_THERMAL=y
CONFIG_USB=y
CONFIG_DM_USB=y
CONFIG_USB_EHCI_HCD=y
diff --git a/configs/pico-hobbit-imx7d_defconfig b/configs/pico-hobbit-imx7d_defconfig
index 6b3b100..f33a725 100644
--- a/configs/pico-hobbit-imx7d_defconfig
+++ b/configs/pico-hobbit-imx7d_defconfig
@@ -67,6 +67,7 @@
CONFIG_PINCTRL=y
CONFIG_PINCTRL_IMX7=y
CONFIG_MXC_UART=y
+CONFIG_IMX_THERMAL=y
CONFIG_USB=y
CONFIG_DM_USB=y
CONFIG_USB_EHCI_HCD=y
diff --git a/configs/pico-imx7d_bl33_defconfig b/configs/pico-imx7d_bl33_defconfig
index 5bd56c6..947dfcb 100644
--- a/configs/pico-imx7d_bl33_defconfig
+++ b/configs/pico-imx7d_bl33_defconfig
@@ -62,6 +62,7 @@
CONFIG_PINCTRL_IMX7=y
CONFIG_CONS_INDEX=4
CONFIG_MXC_UART=y
+CONFIG_IMX_THERMAL=y
CONFIG_USB=y
CONFIG_DM_USB=y
CONFIG_USB_EHCI_HCD=y
diff --git a/configs/pico-imx7d_defconfig b/configs/pico-imx7d_defconfig
index e2e3a56..cc49e6f 100644
--- a/configs/pico-imx7d_defconfig
+++ b/configs/pico-imx7d_defconfig
@@ -67,6 +67,7 @@
CONFIG_PINCTRL=y
CONFIG_PINCTRL_IMX7=y
CONFIG_MXC_UART=y
+CONFIG_IMX_THERMAL=y
CONFIG_USB=y
CONFIG_DM_USB=y
CONFIG_USB_EHCI_HCD=y
diff --git a/configs/pico-nymph-imx7d_defconfig b/configs/pico-nymph-imx7d_defconfig
index 085913e..dbfa2e0 100644
--- a/configs/pico-nymph-imx7d_defconfig
+++ b/configs/pico-nymph-imx7d_defconfig
@@ -67,6 +67,7 @@
CONFIG_PINCTRL=y
CONFIG_PINCTRL_IMX7=y
CONFIG_MXC_UART=y
+CONFIG_IMX_THERMAL=y
CONFIG_USB=y
CONFIG_DM_USB=y
CONFIG_USB_EHCI_HCD=y
diff --git a/configs/pico-pi-imx7d_defconfig b/configs/pico-pi-imx7d_defconfig
index 4005f8d..ab630ca 100644
--- a/configs/pico-pi-imx7d_defconfig
+++ b/configs/pico-pi-imx7d_defconfig
@@ -67,6 +67,7 @@
CONFIG_PINCTRL=y
CONFIG_PINCTRL_IMX7=y
CONFIG_MXC_UART=y
+CONFIG_IMX_THERMAL=y
CONFIG_USB=y
CONFIG_DM_USB=y
CONFIG_USB_EHCI_HCD=y
diff --git a/configs/riotboard_defconfig b/configs/riotboard_defconfig
index 1c632770..b652057 100644
--- a/configs/riotboard_defconfig
+++ b/configs/riotboard_defconfig
@@ -39,6 +39,7 @@
CONFIG_SPI=y
CONFIG_MXC_SPI=y
CONFIG_DM_THERMAL=y
+CONFIG_IMX_THERMAL=y
CONFIG_USB=y
CONFIG_USB_HOST_ETHER=y
CONFIG_USB_ETHER_ASIX=y
diff --git a/configs/riotboard_spl_defconfig b/configs/riotboard_spl_defconfig
index 42d7377..95549ff 100644
--- a/configs/riotboard_spl_defconfig
+++ b/configs/riotboard_spl_defconfig
@@ -49,6 +49,7 @@
CONFIG_SPI=y
CONFIG_MXC_SPI=y
CONFIG_DM_THERMAL=y
+CONFIG_IMX_THERMAL=y
CONFIG_USB=y
CONFIG_USB_HOST_ETHER=y
CONFIG_USB_ETHER_ASIX=y
diff --git a/configs/sksimx6_defconfig b/configs/sksimx6_defconfig
index 927f46f..9b37061 100644
--- a/configs/sksimx6_defconfig
+++ b/configs/sksimx6_defconfig
@@ -49,4 +49,5 @@
CONFIG_MII=y
CONFIG_MXC_UART=y
CONFIG_DM_THERMAL=y
+CONFIG_IMX_THERMAL=y
CONFIG_OF_LIBFDT=y
diff --git a/configs/somlabs_visionsom_6ull_defconfig b/configs/somlabs_visionsom_6ull_defconfig
index 739d4c9..52e34e3 100644
--- a/configs/somlabs_visionsom_6ull_defconfig
+++ b/configs/somlabs_visionsom_6ull_defconfig
@@ -49,6 +49,7 @@
CONFIG_DM_REGULATOR_FIXED=y
CONFIG_DM_REGULATOR_GPIO=y
CONFIG_MXC_UART=y
+CONFIG_IMX_THERMAL=y
CONFIG_USB=y
CONFIG_DM_USB=y
CONFIG_USB_STORAGE=y
diff --git a/configs/tbs2910_defconfig b/configs/tbs2910_defconfig
index e43fab2..239e9ed 100644
--- a/configs/tbs2910_defconfig
+++ b/configs/tbs2910_defconfig
@@ -84,6 +84,7 @@
CONFIG_RTC_DS1307=y
CONFIG_MXC_UART=y
CONFIG_DM_THERMAL=y
+CONFIG_IMX_THERMAL=y
CONFIG_USB=y
CONFIG_DM_USB=y
CONFIG_USB_STORAGE=y
diff --git a/configs/udoo_neo_defconfig b/configs/udoo_neo_defconfig
index 89e9363..ba1e6d3 100644
--- a/configs/udoo_neo_defconfig
+++ b/configs/udoo_neo_defconfig
@@ -38,4 +38,5 @@
CONFIG_PHY_MICREL_KSZ8XXX=y
CONFIG_MII=y
CONFIG_MXC_UART=y
+CONFIG_IMX_THERMAL=y
CONFIG_OF_LIBFDT=y
diff --git a/configs/variscite_dart6ul_defconfig b/configs/variscite_dart6ul_defconfig
index 37d9687..5f94cea 100644
--- a/configs/variscite_dart6ul_defconfig
+++ b/configs/variscite_dart6ul_defconfig
@@ -49,6 +49,7 @@
CONFIG_DM_REGULATOR=y
CONFIG_DM_REGULATOR_FIXED=y
CONFIG_MXC_UART=y
+CONFIG_IMX_THERMAL=y
CONFIG_USB=y
CONFIG_DM_USB=y
CONFIG_USB_GADGET=y
diff --git a/configs/verdin-imx8mm_defconfig b/configs/verdin-imx8mm_defconfig
index 836c6f6..ea0b597 100644
--- a/configs/verdin-imx8mm_defconfig
+++ b/configs/verdin-imx8mm_defconfig
@@ -90,7 +90,7 @@
CONFIG_SPL_PINCTRL=y
CONFIG_PINCTRL_IMX8M=y
CONFIG_DM_PMIC=y
-CONFIG_SPL_DM_PMIC_BD71837=y
+CONFIG_SPL_DM_PMIC_PCA9450=y
CONFIG_DM_PMIC_PFUZE100=y
CONFIG_DM_REGULATOR=y
CONFIG_DM_REGULATOR_FIXED=y
diff --git a/configs/vining_2000_defconfig b/configs/vining_2000_defconfig
index b0a9c65..31e6cfb 100644
--- a/configs/vining_2000_defconfig
+++ b/configs/vining_2000_defconfig
@@ -78,6 +78,7 @@
CONFIG_PWM_IMX=y
CONFIG_DM_SERIAL=y
CONFIG_MXC_UART=y
+CONFIG_IMX_THERMAL=y
CONFIG_USB=y
CONFIG_DM_USB=y
CONFIG_USB_STORAGE=y
diff --git a/configs/warp7_bl33_defconfig b/configs/warp7_bl33_defconfig
index 761fcd7..4b45fcd 100644
--- a/configs/warp7_bl33_defconfig
+++ b/configs/warp7_bl33_defconfig
@@ -52,6 +52,7 @@
CONFIG_DM_SERIAL=y
CONFIG_MXC_UART=y
CONFIG_OPTEE=y
+CONFIG_IMX_THERMAL=y
CONFIG_USB=y
CONFIG_DM_USB=y
CONFIG_USB_EHCI_HCD=y
diff --git a/configs/warp7_defconfig b/configs/warp7_defconfig
index 3fd21dd..3d111960 100644
--- a/configs/warp7_defconfig
+++ b/configs/warp7_defconfig
@@ -58,6 +58,7 @@
CONFIG_DM_SERIAL=y
CONFIG_MXC_UART=y
CONFIG_OPTEE=y
+CONFIG_IMX_THERMAL=y
CONFIG_USB=y
CONFIG_DM_USB=y
CONFIG_USB_EHCI_HCD=y
diff --git a/configs/xpress_defconfig b/configs/xpress_defconfig
index dd0b61c..b77bf9a 100644
--- a/configs/xpress_defconfig
+++ b/configs/xpress_defconfig
@@ -40,6 +40,7 @@
CONFIG_PHY_SMSC=y
CONFIG_MII=y
CONFIG_MXC_UART=y
+CONFIG_IMX_THERMAL=y
CONFIG_USB=y
CONFIG_USB_STORAGE=y
CONFIG_OF_LIBFDT=y
diff --git a/configs/xpress_spl_defconfig b/configs/xpress_spl_defconfig
index 935450e..aee059d 100644
--- a/configs/xpress_spl_defconfig
+++ b/configs/xpress_spl_defconfig
@@ -51,6 +51,7 @@
CONFIG_PHY_SMSC=y
CONFIG_MII=y
CONFIG_MXC_UART=y
+CONFIG_IMX_THERMAL=y
CONFIG_USB=y
CONFIG_USB_STORAGE=y
CONFIG_OF_LIBFDT=y
diff --git a/configs/zc5202_defconfig b/configs/zc5202_defconfig
index 07cd054..321a935 100644
--- a/configs/zc5202_defconfig
+++ b/configs/zc5202_defconfig
@@ -58,4 +58,5 @@
CONFIG_MXC_UART=y
CONFIG_SPI=y
CONFIG_MXC_SPI=y
+CONFIG_IMX_THERMAL=y
CONFIG_OF_LIBFDT=y
diff --git a/configs/zc5601_defconfig b/configs/zc5601_defconfig
index 90736ec..ed6978e 100644
--- a/configs/zc5601_defconfig
+++ b/configs/zc5601_defconfig
@@ -56,4 +56,5 @@
CONFIG_MXC_UART=y
CONFIG_SPI=y
CONFIG_MXC_SPI=y
+CONFIG_IMX_THERMAL=y
CONFIG_OF_LIBFDT=y
diff --git a/doc/board/advantech/imx8qm-rom7720-a1.rst b/doc/board/advantech/imx8qm-rom7720-a1.rst
new file mode 100644
index 0000000..bd4be1d
--- /dev/null
+++ b/doc/board/advantech/imx8qm-rom7720-a1.rst
@@ -0,0 +1,75 @@
+.. SPDX-License-Identifier: GPL-2.0+
+
+U-Boot for the NXP i.MX8QM ROM 7720a1 board
+===========================================
+
+Quick Start
+-----------
+
+- Build the ARM Trusted firmware binary
+- Get scfw_tcm.bin and ahab-container.img
+- Get imx-mkimage
+- Build U-Boot
+- Build imx-mkimage
+- Flash the binary into the SD card
+- Boot
+
+Get and Build the ARM Trusted firmware
+--------------------------------------
+
+.. code-block:: bash
+
+ $ git clone https://source.codeaurora.org/external/imx/imx-atf
+ $ cd imx-atf/
+ $ git checkout origin/imx_4.14.78_1.0.0_ga -b imx_4.14.78_1.0.0_ga
+ $ make PLAT=imx8qm bl31
+
+Get scfw_tcm.bin and ahab-container.img
+---------------------------------------
+
+.. code-block:: bash
+
+ $ wget https://www.nxp.com/lgfiles/NMG/MAD/YOCTO/imx-sc-firmware-1.1.bin
+ $ chmod +x imx-sc-firmware-1.1.bin
+ $ ./imx-sc-firmware-1.1.bin
+ $ wget https://www.nxp.com/lgfiles/NMG/MAD/YOCTO/firmware-imx-8.0.bin
+ $ chmod +x firmware-imx-8.0.bin
+ $ ./firmware-imx-8.0.bin
+
+Or use this to avoid running random scripts from the internet,
+but note that you must agree to the license the script displays:
+
+.. code-block:: bash
+
+ $ dd if=imx-sc-firmware-1.1.bin of=imx-sc-firmware-1.1.tar.bz2 bs=37185 skip=1
+ $ tar -xf imx-sc-firmware-1.1.tar.bz2
+ $ cp imx-sc-firmware-1.1/mx8qm-val-scfw-tcm.bin $(builddir)
+
+ $ dd if=firmware-imx-8.0.bin of=firmware-imx-8.0.tar.bz2 bs=37180 skip=1
+ $ tar -xf firmware-imx-8.0.tar.bz2
+ $ cp firmware-imx-8.0/firmware/seco/mx8qm-ahab-container.img $(builddir)
+
+Build U-Boot
+------------
+
+.. code-block:: bash
+
+ $ export ATF_LOAD_ADDR=0x80000000
+ $ export BL33_LOAD_ADDR=0x80020000
+ $ make imx8qm_rom7720_a1_4G_defconfig
+ $ make u-boot.bin
+ $ make flash.bin
+
+Flash the binary into the SD card
+---------------------------------
+
+Burn the flash.bin binary to SD card offset 32KB:
+
+.. code-block:: bash
+
+ $ sudo dd if=flash.bin of=/dev/sd[x] bs=1k seek=32 conv=fsync
+
+Boot
+----
+
+Set Boot switch SW2: 1100.
diff --git a/doc/board/advantech/index.rst b/doc/board/advantech/index.rst
new file mode 100644
index 0000000..e9b198c
--- /dev/null
+++ b/doc/board/advantech/index.rst
@@ -0,0 +1,9 @@
+.. SPDX-License-Identifier: GPL-2.0+
+
+Advantech
+=========
+
+.. toctree::
+ :maxdepth: 2
+
+ imx8qm-rom7720-a1.rst
diff --git a/doc/board/freescale/imx8mp_evk.rst b/doc/board/freescale/imx8mp_evk.rst
index b34742e..96df6d4 100644
--- a/doc/board/freescale/imx8mp_evk.rst
+++ b/doc/board/freescale/imx8mp_evk.rst
@@ -23,7 +23,7 @@
.. code-block:: bash
$ make PLAT=imx8mp bl31
- $ sudo cp build/imx8mp/release/bl31.bin $(srctree)
+ $ cp build/imx8mp/release/bl31.bin $(srctree)
Get the ddr firmware
--------------------
@@ -32,11 +32,11 @@
$ wget https://www.nxp.com/lgfiles/NMG/MAD/YOCTO/firmware-imx-8.7.bin
$ chmod +x firmware-imx-8.7.bin
- $ ./firmware-imx-8.7
- $ sudo cp firmware-imx-8.7/firmware/ddr/synopsys/lpddr4_pmu_train_1d_dmem_201904.bin $(srctree)/lpddr4_pmu_train_1d_dmem.bin
- $ sudo cp firmware-imx-8.7/firmware/ddr/synopsys/lpddr4_pmu_train_1d_imem_201904.bin $(srctree)/lpddr4_pmu_train_1d_imem.bin
- $ sudo cp firmware-imx-8.7/firmware/ddr/synopsys/lpddr4_pmu_train_2d_dmem_201904.bin $(srctree)/lpddr4_pmu_train_2d_dmem.bin
- $ sudo cp firmware-imx-8.7/firmware/ddr/synopsys/lpddr4_pmu_train_2d_imem_201904.bin $(srctree)/lpddr4_pmu_train_2d_imem.bin
+ $ ./firmware-imx-8.7.bin
+ $ cp firmware-imx-8.7/firmware/ddr/synopsys/lpddr4_pmu_train_1d_dmem_201904.bin $(srctree)/lpddr4_pmu_train_1d_dmem.bin
+ $ cp firmware-imx-8.7/firmware/ddr/synopsys/lpddr4_pmu_train_1d_imem_201904.bin $(srctree)/lpddr4_pmu_train_1d_imem.bin
+ $ cp firmware-imx-8.7/firmware/ddr/synopsys/lpddr4_pmu_train_2d_dmem_201904.bin $(srctree)/lpddr4_pmu_train_2d_dmem.bin
+ $ cp firmware-imx-8.7/firmware/ddr/synopsys/lpddr4_pmu_train_2d_imem_201904.bin $(srctree)/lpddr4_pmu_train_2d_imem.bin
Build U-Boot
------------
diff --git a/doc/board/index.rst b/doc/board/index.rst
index 4b6a996..915f1be 100644
--- a/doc/board/index.rst
+++ b/doc/board/index.rst
@@ -7,6 +7,7 @@
:maxdepth: 2
actions/index
+ advantech/index
AndesTech/index
amlogic/index
atmel/index
diff --git a/doc/board/toradex/apalix-imx8x.rst b/doc/board/toradex/apalix-imx8x.rst
new file mode 100644
index 0000000..ce7dde8
--- /dev/null
+++ b/doc/board/toradex/apalix-imx8x.rst
@@ -0,0 +1,74 @@
+.. SPDX-License-Identifier: GPL-2.0+
+
+Apalis iMX8X V1.1A Module
+==========================
+
+Quick Start
+-----------
+
+- Build the ARM trusted firmware binary
+- Get scfw_tcm.bin and ahab-container.img
+- Build U-Boot
+- Load U-Boot binary using uuu
+- Flash U-Boot binary into the eMMC
+- Boot
+
+Get and Build the ARM Trusted Firmware
+--------------------------------------
+
+.. code-block:: bash
+
+ $ git clone -b toradex_imx_5.4.24_2.1.0 http://git.toradex.com/cgit/imx-atf.git
+ $ cd imx-atf/
+ $ make PLAT=imx8qx bl31
+
+Get scfw_tcm.bin and ahab-container.img
+---------------------------------------
+
+.. code-block:: bash
+
+ $ wget https://github.com/toradex/i.MX-System-Controller-Firmware/blob/master/src/scfw_export_mx8qx_b0/build_mx8qx_b0/mx8qx-apalis-scfw-tcm.bin
+ $ wget https://www.nxp.com/lgfiles/NMG/MAD/YOCTO/imx-seco-3.6.3.bin
+ $ chmod +x imx-seco-3.6.3.bin
+ $ ./imx-seco-3.6.3.bin
+
+Copy the following binaries to the U-Boot folder:
+
+.. code-block:: bash
+
+ $ cp imx-atf/build/imx8qx/release/bl31.bin .
+ $ cp imx-seco-3.6.3/firmware/seco/mx8qxb0-ahab-container.img mx8qx-ahab-container.imx8_defconfig
+
+Build U-Boot
+------------
+.. code-block:: bash
+
+ $ make apalis-imx8x_defconfig
+ $ make u-boot-dtb.imx
+
+Load the U-Boot Binary Using UUU
+--------------------------------
+
+Get the latest version of the universal update utility (uuu) aka ``mfgtools 3.0``:
+
+https://community.nxp.com/external-link.jspa?url=https%3A%2F%2Fgithub.com%2FNXPmicro%2Fmfgtools%2Freleases
+
+Put the module into USB recovery aka serial downloader mode, connect USB device
+to your host and execute uuu:
+
+.. code-block:: bash
+
+ sudo ./uuu u-boot/u-boot-dtb.imx
+
+Flash the U-Boot Binary into the eMMC
+-------------------------------------
+
+Burn the ``u-boot-dtb.imx`` binary to the primary eMMC hardware boot area
+partition and boot:
+
+.. code-block:: bash
+
+ load mmc 1:1 $loadaddr u-boot-dtb.imx
+ setexpr blkcnt ${filesize} + 0x1ff && setexpr blkcnt ${blkcnt} / 0x200
+ mmc dev 0 1
+ mmc write ${loadaddr} 0x0 ${blkcnt}
diff --git a/doc/board/toradex/index.rst b/doc/board/toradex/index.rst
index 16b5a07..abba648 100644
--- a/doc/board/toradex/index.rst
+++ b/doc/board/toradex/index.rst
@@ -7,6 +7,7 @@
:maxdepth: 2
apalix-imx8
+ apalix-imx8x
colibri_imx7
colibri-imx8x
verdin-imx8mm
diff --git a/drivers/clk/imx/clk-imx8qm.c b/drivers/clk/imx/clk-imx8qm.c
index 54fb09f..7e466d6 100644
--- a/drivers/clk/imx/clk-imx8qm.c
+++ b/drivers/clk/imx/clk-imx8qm.c
@@ -53,19 +53,27 @@
resource = SC_R_A53;
pm_clk = SC_PM_CLK_CPU;
break;
+ case IMX8QM_I2C0_IPG_CLK:
case IMX8QM_I2C0_CLK:
+ case IMX8QM_I2C0_DIV:
resource = SC_R_I2C_0;
pm_clk = SC_PM_CLK_PER;
break;
+ case IMX8QM_I2C1_IPG_CLK:
case IMX8QM_I2C1_CLK:
+ case IMX8QM_I2C1_DIV:
resource = SC_R_I2C_1;
pm_clk = SC_PM_CLK_PER;
break;
+ case IMX8QM_I2C2_IPG_CLK:
case IMX8QM_I2C2_CLK:
+ case IMX8QM_I2C2_DIV:
resource = SC_R_I2C_2;
pm_clk = SC_PM_CLK_PER;
break;
+ case IMX8QM_I2C3_IPG_CLK:
case IMX8QM_I2C3_CLK:
+ case IMX8QM_I2C3_DIV:
resource = SC_R_I2C_3;
pm_clk = SC_PM_CLK_PER;
break;
@@ -148,19 +156,27 @@
debug("%s(#%lu), rate: %lu\n", __func__, clk->id, rate);
switch (clk->id) {
+ case IMX8QM_I2C0_IPG_CLK:
case IMX8QM_I2C0_CLK:
+ case IMX8QM_I2C0_DIV:
resource = SC_R_I2C_0;
pm_clk = SC_PM_CLK_PER;
break;
+ case IMX8QM_I2C1_IPG_CLK:
case IMX8QM_I2C1_CLK:
+ case IMX8QM_I2C1_DIV:
resource = SC_R_I2C_1;
pm_clk = SC_PM_CLK_PER;
break;
+ case IMX8QM_I2C2_IPG_CLK:
case IMX8QM_I2C2_CLK:
+ case IMX8QM_I2C2_DIV:
resource = SC_R_I2C_2;
pm_clk = SC_PM_CLK_PER;
break;
+ case IMX8QM_I2C3_IPG_CLK:
case IMX8QM_I2C3_CLK:
+ case IMX8QM_I2C3_DIV:
resource = SC_R_I2C_3;
pm_clk = SC_PM_CLK_PER;
break;
@@ -242,19 +258,27 @@
debug("%s(#%lu)\n", __func__, clk->id);
switch (clk->id) {
+ case IMX8QM_I2C0_IPG_CLK:
case IMX8QM_I2C0_CLK:
+ case IMX8QM_I2C0_DIV:
resource = SC_R_I2C_0;
pm_clk = SC_PM_CLK_PER;
break;
+ case IMX8QM_I2C1_IPG_CLK:
case IMX8QM_I2C1_CLK:
+ case IMX8QM_I2C1_DIV:
resource = SC_R_I2C_1;
pm_clk = SC_PM_CLK_PER;
break;
+ case IMX8QM_I2C2_IPG_CLK:
case IMX8QM_I2C2_CLK:
+ case IMX8QM_I2C2_DIV:
resource = SC_R_I2C_2;
pm_clk = SC_PM_CLK_PER;
break;
+ case IMX8QM_I2C3_IPG_CLK:
case IMX8QM_I2C3_CLK:
+ case IMX8QM_I2C3_DIV:
resource = SC_R_I2C_3;
pm_clk = SC_PM_CLK_PER;
break;
diff --git a/drivers/mmc/fsl_esdhc_imx.c b/drivers/mmc/fsl_esdhc_imx.c
index 22040c6..e5409ad 100644
--- a/drivers/mmc/fsl_esdhc_imx.c
+++ b/drivers/mmc/fsl_esdhc_imx.c
@@ -760,7 +760,6 @@
case MMC_HS_400_ES:
mixctrl |= MIX_CTRL_DDREN | MIX_CTRL_HS400_EN;
esdhc_write32(®s->mixctrl, mixctrl);
- esdhc_set_strobe_dll(mmc);
break;
case MMC_HS:
case MMC_HS_52:
@@ -933,6 +932,23 @@
int ret __maybe_unused;
u32 clock;
+#ifdef MMC_SUPPORTS_TUNING
+ /*
+ * call esdhc_set_timing() before update the clock rate,
+ * This is because current we support DDR and SDR mode,
+ * Once the DDR_EN bit is set, the card clock will be
+ * divide by 2 automatically. So need to do this before
+ * setting clock rate.
+ */
+ if (priv->mode != mmc->selected_mode) {
+ ret = esdhc_set_timing(mmc);
+ if (ret) {
+ printf("esdhc_set_timing error %d\n", ret);
+ return ret;
+ }
+ }
+#endif
+
/* Set the clock speed */
clock = mmc->clock;
if (clock < mmc->cfg->f_min)
@@ -957,13 +973,13 @@
#endif
}
- if (priv->mode != mmc->selected_mode) {
- ret = esdhc_set_timing(mmc);
- if (ret) {
- printf("esdhc_set_timing error %d\n", ret);
- return ret;
- }
- }
+ /*
+ * For HS400/HS400ES mode, make sure set the strobe dll in the
+ * target clock rate. So call esdhc_set_strobe_dll() after the
+ * clock updated.
+ */
+ if (mmc->selected_mode == MMC_HS_400 || mmc->selected_mode == MMC_HS_400_ES)
+ esdhc_set_strobe_dll(mmc);
if (priv->signal_voltage != mmc->signal_voltage) {
ret = esdhc_set_voltage(mmc);
@@ -1646,6 +1662,20 @@
}
#endif
+static int fsl_esdhc_wait_dat0(struct udevice *dev, int state,
+ int timeout_us)
+{
+ int ret;
+ u32 tmp;
+ struct fsl_esdhc_priv *priv = dev_get_priv(dev);
+ struct fsl_esdhc *regs = priv->esdhc_regs;
+
+ ret = readx_poll_timeout(esdhc_read32, ®s->prsstat, tmp,
+ !!(tmp & PRSSTAT_DAT0) == !!state,
+ timeout_us);
+ return ret;
+}
+
static const struct dm_mmc_ops fsl_esdhc_ops = {
.get_cd = fsl_esdhc_get_cd,
.send_cmd = fsl_esdhc_send_cmd,
@@ -1656,6 +1686,7 @@
#if CONFIG_IS_ENABLED(MMC_HS400_ES_SUPPORT)
.set_enhanced_strobe = fsl_esdhc_set_enhanced_strobe,
#endif
+ .wait_dat0 = fsl_esdhc_wait_dat0,
};
#endif
diff --git a/drivers/power/pmic/Kconfig b/drivers/power/pmic/Kconfig
index a62aa38..7d51510 100644
--- a/drivers/power/pmic/Kconfig
+++ b/drivers/power/pmic/Kconfig
@@ -98,6 +98,13 @@
This config enables implementation of driver-model pmic uclass features
for PMIC PCA9450. The driver implements read/write operations.
+config SPL_DM_PMIC_PCA9450
+ bool "Enable Driver Model for PMIC PCA9450"
+ depends on DM_PMIC
+ help
+ This config enables implementation of driver-model pmic uclass features
+ for PMIC PCA9450 in SPL. The driver implements read/write operations.
+
config DM_PMIC_PFUZE100
bool "Enable Driver Model for PMIC PFUZE100"
depends on DM_PMIC
diff --git a/drivers/power/pmic/pca9450.c b/drivers/power/pmic/pca9450.c
index 0c9d9a3..c7f8b80 100644
--- a/drivers/power/pmic/pca9450.c
+++ b/drivers/power/pmic/pca9450.c
@@ -80,7 +80,7 @@
};
static const struct udevice_id pca9450_ids[] = {
- { .compatible = "nxp,pca9450a", .data = 0x35, },
+ { .compatible = "nxp,pca9450a", .data = 0x25, },
{ .compatible = "nxp,pca9450b", .data = 0x25, },
{ }
};
diff --git a/include/configs/apalis-imx8x.h b/include/configs/apalis-imx8x.h
new file mode 100644
index 0000000..db31c21
--- /dev/null
+++ b/include/configs/apalis-imx8x.h
@@ -0,0 +1,149 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright 2020 Toradex
+ */
+
+#ifndef __APALIS_IMX8X_H
+#define __APALIS_IMX8X_H
+
+#include <asm/arch/imx-regs.h>
+#include <linux/sizes.h>
+#include <linux/stringify.h>
+
+#define CONFIG_REMAKE_ELF
+
+#define CONFIG_SYS_FSL_ESDHC_ADDR 0
+#define USDHC1_BASE_ADDR 0x5b010000
+#define USDHC2_BASE_ADDR 0x5b020000
+#define CONFIG_SUPPORT_EMMC_BOOT /* eMMC specific */
+
+#define CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG
+
+#define CONFIG_TFTP_TSIZE
+
+#define CONFIG_IPADDR 192.168.10.2
+#define CONFIG_NETMASK 255.255.255.0
+#define CONFIG_SERVERIP 192.168.10.1
+
+#define FEC_ENET_ENABLE_TXC_DELAY
+#define FEC_ENET_ENABLE_RXC_DELAY
+
+#define MEM_LAYOUT_ENV_SETTINGS \
+ "kernel_addr_r=0x80280000\0" \
+ "fdt_addr_r=0x83100000\0" \
+ "ramdisk_addr_r=0x8a000000\0" \
+ "scriptaddr=0x83200000\0"
+
+#ifdef CONFIG_AHAB_BOOT
+#define AHAB_ENV "sec_boot=yes\0"
+#else
+#define AHAB_ENV "sec_boot=no\0"
+#endif
+
+/* Boot M4 */
+#define M4_BOOT_ENV \
+ "m4_0_image=m4_0.bin\0" \
+ "loadm4image_0=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} " \
+ "${m4_0_image}\0" \
+ "m4boot_0=run loadm4image_0; dcache flush; bootaux ${loadaddr} 0\0" \
+
+#define MFG_NAND_PARTITION ""
+
+#define BOOT_TARGET_DEVICES(func) \
+ func(MMC, mmc, 1) \
+ func(MMC, mmc, 0) \
+ func(DHCP, dhcp, na)
+#include <config_distro_bootcmd.h>
+#undef BOOTENV_RUN_NET_USB_START
+#define BOOTENV_RUN_NET_USB_START ""
+
+#define CONFIG_MFG_ENV_SETTINGS \
+ "mfgtool_args=setenv bootargs ${consoleargs} " \
+ "rdinit=/linuxrc g_mass_storage.stall=0 " \
+ "g_mass_storage.removable=1 g_mass_storage.idVendor=0x066F " \
+ "g_mass_storage.idProduct=0x37FF " \
+ "g_mass_storage.iSerialNumber=\"\" " MFG_NAND_PARTITION \
+ "${vidargs} clk_ignore_unused\0" \
+ "initrd_addr=0x83800000\0" \
+ "bootcmd_mfg=run mfgtool_args;booti ${loadaddr} ${initrd_addr} " \
+ "${fdt_addr};\0" \
+
+/* Initial environment variables */
+#define CONFIG_EXTRA_ENV_SETTINGS \
+ AHAB_ENV \
+ BOOTENV \
+ CONFIG_MFG_ENV_SETTINGS \
+ M4_BOOT_ENV \
+ MEM_LAYOUT_ENV_SETTINGS \
+ "boot_file=Image\0" \
+ "consoleargs=console=ttyLP3,${baudrate} earlycon\0" \
+ "fdt_file=imx8qxp-apalis-eval.dtb\0" \
+ "fdtfile=imx8qxp-apalis-eval.dtb\0" \
+ "finduuid=part uuid mmc ${mmcdev}:2 uuid\0" \
+ "image=Image\0" \
+ "initrd_addr=0x83800000\0" \
+ "mmcargs=setenv bootargs ${consoleargs} " \
+ "root=PARTUUID=${uuid} rootwait " \
+ "mmcdev=" __stringify(CONFIG_SYS_MMC_ENV_DEV) "\0" \
+ "mmcpart=" __stringify(CONFIG_SYS_MMC_IMG_LOAD_PART) "\0" \
+ "netargs=setenv bootargs ${consoleargs} " \
+ "root=/dev/nfs ip=dhcp nfsroot=${serverip}:${nfsroot},v3,tcp " \
+ "${vidargs}\0" \
+ "nfsboot=run netargs; dhcp ${loadaddr} ${image}; tftp ${fdt_addr} " \
+ "apalis-imx8x/${fdt_file}; booti ${loadaddr} - " \
+ "${fdt_addr}\0" \
+ "panel=NULL\0" \
+ "script=boot.scr\0" \
+ "update_uboot=askenv confirm Did you load u-boot-dtb.imx (y/N)?; " \
+ "if test \"$confirm\" = \"y\"; then " \
+ "setexpr blkcnt ${filesize} + 0x1ff && setexpr blkcnt " \
+ "${blkcnt} / 0x200; mmc dev 0 1; mmc write ${loadaddr} 0x0 " \
+ "${blkcnt}; fi\0" \
+ "vidargs=video=imxdpufb5:off video=imxdpufb6:off video=imxdpufb7:off\0"
+
+/* Link Definitions */
+#define CONFIG_LOADADDR 0x89000000
+
+#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR
+
+#define CONFIG_SYS_INIT_SP_ADDR 0x80200000
+
+/* Environment in eMMC, before config block at the end of 1st "boot sector" */
+
+#define CONFIG_SYS_MMC_IMG_LOAD_PART 1
+
+/* On Apalis iMX8X USDHC1 is eMMC, USDHC2 is 4-bit SD */
+#define CONFIG_SYS_FSL_USDHC_NUM 2
+
+#define CONFIG_SYS_BOOTM_LEN SZ_64M /* Increase max gunzip size */
+
+/* Size of malloc() pool */
+#define CONFIG_SYS_MALLOC_LEN ((CONFIG_ENV_SIZE + (32 * 1024)) * 1024)
+
+#define CONFIG_SYS_SDRAM_BASE 0x80000000
+#define PHYS_SDRAM_1 0x80000000
+#define PHYS_SDRAM_2 0x880000000
+#define PHYS_SDRAM_1_SIZE SZ_2G /* 2 GB */
+#define PHYS_SDRAM_2_SIZE 0x00000000 /* 0 GB */
+
+/* Monitor Command Prompt */
+#define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
+#define CONFIG_SYS_CBSIZE SZ_2K
+#define CONFIG_SYS_MAXARGS 64
+#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
+#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \
+ sizeof(CONFIG_SYS_PROMPT) + 16)
+
+/* Generic Timer Definitions */
+#define COUNTER_FREQUENCY 8000000 /* 8MHz */
+
+/* Networking */
+#define CONFIG_FEC_ENET_DEV 0
+#define IMX_FEC_BASE 0x5b040000
+#define CONFIG_FEC_MXC_PHYADDR 0x4
+#define CONFIG_ETHPRIME "eth0"
+#define CONFIG_FEC_XCV_TYPE RGMII
+#define FEC_QUIRK_ENET_MAC
+#define PHY_ANEG_TIMEOUT 20000
+
+#endif /* __APALIS_IMX8X_H */
diff --git a/include/configs/aristainetos2.h b/include/configs/aristainetos2.h
index 6e8595c..78fa1a9 100644
--- a/include/configs/aristainetos2.h
+++ b/include/configs/aristainetos2.h
@@ -13,14 +13,18 @@
#define CONFIG_HOSTNAME "aristainetos2"
+#if (CONFIG_SYS_BOARD_VERSION == 5)
#define CONFIG_MXC_UART_BASE UART2_BASE
#define CONSOLE_DEV "ttymxc1"
+#elif (CONFIG_SYS_BOARD_VERSION == 6)
+#define CONFIG_MXC_UART_BASE UART1_BASE
+#define CONSOLE_DEV "ttymxc0"
+#endif
#define CONFIG_FEC_XCV_TYPE RGMII
/* Framebuffer */
#define CONFIG_SYS_LDB_CLOCK 28341000
-#define CONFIG_LG4573
#include "mx6_common.h"
@@ -77,6 +81,8 @@
"enable_hab_check=1\0"
#else
#define HAB_EXTRA_SETTINGS \
+ "hab_check_addr=echo HAB check addr always returns " \
+ "true;true\0" \
"hab_check_file_fit=echo HAB check FIT file always returns " \
"true;true\0" \
"hab_check_flash_fit=echo HAB check flash FIT always returns " \
@@ -86,96 +92,18 @@
"enable_hab_check=0\0"
#endif
-#if (CONFIG_SYS_BOARD_VERSION == 3)
-#define CONFIG_EXTRA_ENV_BOARD_SETTINGS \
- "dead=led led_red on\0" \
- "mtdids=nand0=gpmi-nand,nor0=spi0.0\0" \
- "mtdparts=mtdparts=spi0.0:832k(u-boot),64k(env),64k(env-red)," \
- "-(ubi-nor);gpmi-nand:-(ubi)\0" \
- "addmisc=setenv bootargs ${bootargs} net.ifnames=0 consoleblank=0 " \
- "bootmode=${bootmode} mmcpart=${mmcpart}\0" \
- "mainboot=echo Booting from SD-card ...; " \
- "run mainargs addmtd addmisc;" \
- "if test -n ${addmiscM}; then run addmiscM;fi;" \
- "if test -n ${addmiscC}; then run addmiscC;fi;" \
- "if test -n ${addmiscD}; then run addmiscD;fi;" \
- "run boot_board_type;" \
- "bootm ${fit_addr_r}\0" \
- "mainargs=setenv bootargs console=${console},${baudrate} " \
- "root=${mmcroot}\0" \
- "main_load_fit=ext4load mmc ${mmcdev}:${mmcpart} ${fit_addr_r} " \
- "${fit_file}\0" \
- "rescue_load_fit=ext4load mmc ${mmcdev}:${mmcrescuepart} " \
- "${fit_addr_r} ${rescue_fit_file}\0"
-#elif (CONFIG_SYS_BOARD_VERSION == 4)
+#if (CONFIG_SYS_BOARD_VERSION == 5)
#define CONFIG_EXTRA_ENV_BOARD_SETTINGS \
- "dead=led led_red on;led led_red2 on;\0" \
- "mtdids=nand0=gpmi-nand,nor0=spi0.0\0" \
- "mtdparts=mtdparts=spi0.0:832k(u-boot),64k(env),64k(env-red)," \
- "-(ubi-nor);gpmi-nand:-(ubi)\0" \
- "addmisc=setenv bootargs ${bootargs} net.ifnames=0 consoleblank=0 " \
- "bootmode=${bootmode} mmcpart=${mmcpart}\0" \
- "mainboot=echo Booting from SD-card ...; " \
- "run mainargs addmtd addmisc;" \
- "if test -n ${addmiscM}; then run addmiscM;fi;" \
- "if test -n ${addmiscC}; then run addmiscC;fi;" \
- "if test -n ${addmiscD}; then run addmiscD;fi;" \
- "run boot_board_type;" \
- "bootm ${fit_addr_r}\0" \
- "mainargs=setenv bootargs console=${console},${baudrate} " \
- "root=${mmcroot}\0" \
- "main_load_fit=ext4load mmc ${mmcdev}:${mmcpart} ${fit_addr_r} " \
- "${fit_file}\0" \
- "rescue_load_fit=ext4load mmc ${mmcdev}:${mmcrescuepart} " \
- "${fit_addr_r} ${rescue_fit_file}\0"
-#elif (CONFIG_SYS_BOARD_VERSION == 5)
-#define CONFIG_EXTRA_ENV_BOARD_SETTINGS \
- "emmcpart=1\0" \
- "emmc_rescue_part=3\0" \
- "emmcdev=1\0" \
- "emmcroot=/dev/mmcblk1p1 rootwait rw\0" \
- "dead=led led_red on\0" \
- "mtdids=nor0=spi0.0\0" \
- "mtdparts=mtdparts=spi0.0:832k(u-boot),64k(env),64k(env-red)," \
- "-(ubi-nor)\0" \
- "addmisc=setenv bootargs ${bootargs} net.ifnames=0 consoleblank=0 " \
- "bootmode=${bootmode} mmcpart=${mmcpart} " \
- "emmcpart=${emmcpart}\0" \
- "mainboot=echo Booting from eMMC ...; " \
- "run mainargs addmtd addmisc;" \
- "if test -n ${addmiscM}; then run addmiscM;fi;" \
- "if test -n ${addmiscC}; then run addmiscC;fi;" \
- "if test -n ${addmiscD}; then run addmiscD;fi;" \
- "run boot_board_type;" \
- "bootm ${fit_addr_r}\0" \
- "mainargs=setenv bootargs console=${console},${baudrate} " \
- "root=${emmcroot} rootfstype=ext4\0 " \
- "main_load_fit=ext4load mmc ${emmcdev}:${emmcpart} ${fit_addr_r} " \
- "${fit_file}; " \
- "imi ${fit_addr_r}\0 " \
- "rescue_load_fit=ext4load mmc ${emmcdev}:${emmc_rescue_part} " \
- "${fit_addr_r} ${rescue_fit_file};imi ${fit_addr_r}\0"
-#else
+ "dead=while true; do; " \
+ "led led_red on; sleep 1;" \
+ "led led_red off; sleep 1;" \
+ "done\0"
+#elif (CONFIG_SYS_BOARD_VERSION == 6)
#define CONFIG_EXTRA_ENV_BOARD_SETTINGS \
- "dead=led led_red on\0" \
- "mtdids=nand0=gpmi-nand,nor0=spi3.1\0" \
- "mtdparts=mtdparts=spi3.1:832k(u-boot),64k(env),64k(env-red)," \
- "-(ubi-nor);gpmi-nand:-(ubi)\0" \
- "addmisc=setenv bootargs ${bootargs} net.ifnames=0 consoleblank=0 " \
- "bootmode=${bootmode} mmcpart=${mmcpart}\0" \
- "mainboot=echo Booting from SD-card ...; " \
- "run mainargs addmtd addmisc;" \
- "if test -n ${addmiscM}; then run addmiscM;fi;" \
- "if test -n ${addmiscC}; then run addmiscC;fi;" \
- "if test -n ${addmiscD}; then run addmiscD;fi;" \
- "run boot_board_type;" \
- "bootm ${fit_addr_r}\0" \
- "mainargs=setenv bootargs console=${console},${baudrate} " \
- "root=${mmcroot}\0" \
- "main_load_fit=ext4load mmc ${mmcdev}:${mmcpart} ${fit_addr_r} " \
- "${fit_file}\0" \
- "rescue_load_fit=ext4load mmc ${mmcdev}:${mmcrescuepart} " \
- "${fit_addr_r} ${rescue_fit_file}\0"
+ "dead=while true; do; " \
+ "led led_red on; led led_red2 on; sleep 1;" \
+ "led led_red off; led led_red2 off;; sleep 1;" \
+ "done\0"
#endif
#define CONFIG_EXTRA_ENV_SETTINGS \
@@ -183,17 +111,24 @@
"usb_pgood_delay=2000\0" \
"nor_bootdelay=-2\0" \
"script=u-boot.scr\0" \
- "fit_file=/boot/system.itb\0" \
- "rescue_fit_file=/boot/rescue.itb\0" \
"loadaddr=0x12000000\0" \
"fit_addr_r=0x14000000\0" \
- "uboot=/boot/u-boot.imx\0" \
"uboot_sz=d0000\0" \
"panel=lb07wv8\0" \
"splashpos=m,m\0" \
"console=" CONSOLE_DEV "\0" \
- "fdt_high=0xffffffff\0" \
- "initrd_high=0xffffffff\0" \
+ "emmcroot=/dev/mmcblk1p1 rootwait rw\0" \
+ "mtdids=nor0=spi0.0\0" \
+ "mtdparts=mtdparts=spi0.0:832k(u-boot),64k(env),64k(env-red)," \
+ "-(ubi-nor)\0" \
+ "mk_fitfile_path=setenv fit_file /${sysnum}/system.itb\0" \
+ "mk_rescue_fitfile_path=setenv rescue_fit_file /${rescue_sysnum}/system.itb\0" \
+ "mk_uboot_path=setenv uboot /${sysnum}/u-boot.imx\0" \
+ "mk_pubkey_path=setenv pubkey /${sysnum}/PCR.pem\0" \
+ "mk_rescue_pubkey_path=setenv pubkey /${rescue_sysnum}/PCR.pem\0" \
+ "addmisc=setenv bootargs ${bootargs} net.ifnames=0 consoleblank=0 " \
+ "bootmode=${bootmode} rng_core.default_quality=1000 " \
+ "mmcpart=${mmcpart} emmcpart=${emmcpart} sysnum=${sysnum}\0" \
"addmtd=setenv bootargs ${bootargs} ${mtdparts}\0" \
"boot_board_type=bootm ${fit_addr_r}#${board_type}\0" \
"get_env=mw ${loadaddr} 0 0x20000;" \
@@ -205,7 +140,7 @@
"sf protect unlock 0 0x1000000;" \
"mw ${loadaddr} 0 0x20000;" \
"env export -t ${loadaddr} serial# ethaddr " \
- "board_type panel addmisc addmiscM addmiscC addmiscD;" \
+ "board_type panel;" \
"env default -a;" \
"env import -t ${loadaddr}\0" \
"loadbootscript=" \
@@ -216,28 +151,62 @@
"loadbootscriptUSBf=" \
"fatload usb 0 ${loadaddr} ${script};\0" \
"bootscriptUSB=echo Running bootscript from usb-stick ...; " \
- "source\0" \
+ "source \0" \
"bootscript=echo Running bootscript from mmc ...; " \
- "source\0" \
+ "source \0" \
"mmcpart=1\0" \
- "mmcrescuepart=3\0" \
"mmcdev=0\0" \
+ "emmcpart=1\0" \
+ "emmcdev=1\0" \
+ "sysnum=1\0" \
+ "rescue_sysnum=0\0" \
+ "rreason=18\0" \
+ "mainboot=echo Booting from eMMC ...; " \
+ "run mainargs addmtd addmisc;" \
+ "run boot_board_type;" \
+ "bootm ${fit_addr_r}\0" \
+ "mainargs=setenv bootargs console=${console},${baudrate} " \
+ "root=${emmcroot} rootfstype=ext4\0 " \
+ "main_load_fit=run mk_fitfile_path; " \
+ "ext4load mmc ${emmcdev}:${emmcpart} ${fit_addr_r} " \
+ "${fit_file}; " \
+ "imi ${fit_addr_r}\0 " \
+ "rescue_load_fit=run mk_rescue_fitfile_path; " \
+ "ext4load mmc ${emmcdev}:${emmcpart} ${fit_addr_r} " \
+ "${rescue_fit_file}; " \
+ "imi ${fit_addr_r}\0" \
+ "main_load_pubkey=run mk_pubkey_path; " \
+ "setenv hab_check_filetype \"PCR.pem\";" \
+ "env set check_addr ${loadaddr};" \
+ "ext4load mmc ${emmcdev}:${emmcpart} ${loadaddr} " \
+ "${pubkey}\0" \
+ "rescue_load_pubkey=run mk_rescue_pubkey_path; " \
+ "setenv hab_check_filetype \"PCR.pem\";" \
+ "env set check_addr ${loadaddr};" \
+ "ext4load mmc ${emmcdev}:${emmcpart} ${loadaddr} " \
+ "${pubkey}\0" \
+ "mainRargs=setenv bootargs console=${console},${baudrate} " \
+ "rescue_sysnum=${rescue_sysnum} root=${emmcroot} rootfstype=ext4\0" \
"mmcroot=" CONFIG_MMCROOT " rootwait rw\0" \
"mmcargs=setenv bootargs console=${console},${baudrate} " \
"root=${mmcroot}\0" \
+ "mmcRargs=setenv bootargs console=${console},${baudrate} " \
+ "rescue_sysnum=${rescue_sysnum} root=${mmcroot}\0" \
"mmcboot=echo Booting from mmc ...; " \
"run mmcargs addmtd addmisc;" \
- "if test -n ${addmiscM}; then run addmiscM;fi;" \
- "if test -n ${addmiscC}; then run addmiscC;fi;" \
- "if test -n ${addmiscD}; then run addmiscD;fi;" \
"run boot_board_type;" \
"bootm ${fit_addr_r}\0" \
- "mmc_load_fit=ext4load mmc ${mmcdev}:${mmcpart} ${fit_addr_r} " \
+ "mmc_load_fit=run mk_fitfile_path; " \
+ "ext4load mmc ${mmcdev}:${mmcpart} ${fit_addr_r} " \
"${fit_file}\0" \
- "mmc_load_uboot=ext4load mmc ${mmcdev}:${mmcpart} ${loadaddr} " \
- "${uboot}\0" \
- "mmc_rescue_load_fit=ext4load mmc ${mmcdev}:${mmcrescuepart} " \
+ "imi ${fit_addr_r}\0" \
+ "mmc_rescue_load_fit=run mk_rescue_fitfile_path; " \
+ "ext4load mmc ${mmcdev}:${mmcpart} " \
"${fit_addr_r} ${rescue_fit_file}\0" \
+ "imi ${fit_addr_r}\0" \
+ "mmc_load_uboot=run mk_uboot_path; " \
+ "ext4load mmc ${mmcdev}:${mmcpart} ${loadaddr} " \
+ "${uboot}\0" \
"mmc_upd_uboot=mw.b ${loadaddr} 0xff ${uboot_sz};" \
"setexpr cmp_buf ${loadaddr} + ${uboot_sz};" \
"setexpr uboot_maxsize ${uboot_sz} - 400;" \
@@ -246,14 +215,19 @@
"sf write ${loadaddr} 400 ${filesize};" \
"sf read ${cmp_buf} 400 ${uboot_sz};" \
"cmp.b ${loadaddr} ${cmp_buf} ${uboot_maxsize}\0" \
- "rescueargs=setenv bootargs console=${console},${baudrate} " \
- "root=/dev/ram rw\0 " \
+ "mmc_load_pubkey=run mk_pubkey_path; " \
+ "setenv hab_check_filetype \"PCR.pem\";" \
+ "env set check_addr ${loadaddr};" \
+ "ext4load mmc ${mmcdev}:${mmcpart} ${loadaddr} " \
+ "${pubkey}\0" \
+ "mmc_rescue_load_pubkey=run mk_rescue_pubkey_path; " \
+ "setenv hab_check_filetype \"PCR.pem\";" \
+ "env set check_addr ${loadaddr};" \
+ "ext4load mmc ${mmcdev}:${mmcpart} ${loadaddr} " \
+ "${pubkey}\0" \
"rescueboot=echo Booting rescue system ...; " \
- "run rescueargs addmtd addmisc;" \
+ "run addmtd addmisc;" \
"if test -n ${rescue_reason}; then run rescue_reason;fi;" \
- "if test -n ${addmiscM}; then run addmiscM;fi;" \
- "if test -n ${addmiscC}; then run addmiscC;fi;" \
- "if test -n ${addmiscD}; then run addmiscD;fi;" \
"run boot_board_type;" \
"if bootm ${fit_addr_r}; then ; " \
"else " \
@@ -261,50 +235,73 @@
"fi; \0" \
"r_reason_syserr=setenv rescue_reason setenv bootargs " \
"\\\\${bootargs} " \
- "rescueReason=18\0 " \
- "usb_load_fit=ext4load usb 0 ${fit_addr_r} ${fit_file}\0" \
- "usb_load_fitf=fatload usb 0 ${fit_addr_r} ${fit_file}\0" \
- "usb_load_rescuefit=ext4load usb 0 ${fit_addr_r} " \
+ "rescueReason=$rreason\0 " \
+ "usb_load_fit=run mk_fitfile_path; " \
+ "ext4load usb 0 ${fit_addr_r} ${fit_file}\0" \
+ "usb_load_fitf=run mk_fitfile_path; " \
+ "fatload usb 0 ${fit_addr_r} ${fit_file}\0" \
+ "usb_load_rescuefit=run mk_rescue_fitfile_path; " \
+ "ext4load usb 0 ${fit_addr_r} " \
"${rescue_fit_file}\0" \
- "usb_load_rescuefitf=fatload usb 0 ${fit_addr_r} " \
+ "usb_load_rescuefitf=run mk_rescue_fitfile_path; " \
+ "fatload usb 0 ${fit_addr_r} " \
"${rescue_fit_file}\0" \
+ "usb_load_pubkey=run mk_pubkey_path; " \
+ "setenv hab_check_filetype \"PCR.pem\";" \
+ "env set check_addr ${loadaddr};" \
+ "ext4load usb 0 ${loadaddr} ${pubkey}\0" \
+ "usb_rescue_load_pubkey=run mk_rescue_pubkey_path; " \
+ "setenv hab_check_filetype \"PCR.pem\";" \
+ "env set check_addr ${loadaddr};" \
+ "ext4load usb 0 ${loadaddr} ${pubkey}\0" \
+ "usb_load_pubkeyf=run mk_pubkey_path; " \
+ "setenv hab_check_filetype \"PCR.pem\";" \
+ "env set check_addr ${loadaddr};" \
+ "fatload usb 0 ${loadaddr} ${pubkey}\0" \
+ "usb_rescue_load_pubkeyf=run mk_rescue_pubkey_path; " \
+ "setenv hab_check_filetype \"PCR.pem\";" \
+ "env set check_addr ${loadaddr};" \
+ "fatload usb 0 ${loadaddr} ${pubkey}\0" \
"usbroot=/dev/sda1 rootwait rw\0" \
"usbboot=echo Booting from usb-stick ...; " \
"run usbargs addmtd addmisc;" \
- "if test -n ${addmiscM}; then run addmiscM;fi;" \
- "if test -n ${addmiscC}; then run addmiscC;fi;" \
- "if test -n ${addmiscD}; then run addmiscD;fi;" \
"run boot_board_type;" \
"bootm ${fit_addr_r}\0" \
"usbargs=setenv bootargs console=${console},${baudrate} " \
"root=${usbroot}\0" \
+ "usbRargs=setenv bootargs console=${console},${baudrate} " \
+ "rescue_sysnum=${rescue_sysnum} root=${usbroot} rw\0 " \
"mmc_rescue_boot=" \
"run r_reason_syserr;" \
- "if run mmc_rescue_load_fit hab_check_file_fit; then " \
- "run rescueboot; " \
+ "if run mmc_rescue_load_pubkey hab_check_addr " \
+ "mmc_rescue_load_fit hab_check_file_fit; then " \
+ "run mmcRargs; run rescueboot; " \
"else " \
- "run dead; " \
"echo RESCUE SYSTEM FROM SD-CARD BOOT FAILURE;" \
+ "run dead; " \
"fi;\0" \
"main_rescue_boot=" \
- "if run main_load_fit hab_check_flash_fit; then " \
+ "if run main_load_pubkey hab_check_addr " \
+ "main_load_fit hab_check_flash_fit; then " \
"if run mainboot; then ; " \
"else " \
"run r_reason_syserr;" \
- "if run rescue_load_fit hab_check_file_fit;" \
- "then run rescueboot; " \
+ "if run rescue_load_pubkey hab_check_addr " \
+ "rescue_load_fit hab_check_file_fit; then " \
+ "run mainRargs; run rescueboot; " \
"else " \
- "run dead; " \
"echo RESCUE SYSTEM BOOT FAILURE;" \
+ "run dead; " \
"fi; " \
"fi; " \
"else " \
"run r_reason_syserr;" \
- "if run rescue_load_fit hab_check_file_fit; then " \
- "run rescueboot; " \
+ "if run rescue_load_pubkey hab_check_addr " \
+ "rescue_load_fit hab_check_file_fit; then " \
+ "run mainRargs; run rescueboot; " \
"else " \
- "run dead; " \
"echo RESCUE SYSTEM BOOT FAILURE;" \
+ "run dead; " \
"fi; " \
"fi;\0" \
"usb_mmc_rescue_boot=" \
@@ -318,17 +315,21 @@
"hab_check_file_bootscript;" \
"then run bootscriptUSB; " \
"fi; " \
- "if run usb_load_fit hab_check_file_fit; then " \
+ "if run usb_load_pubkey hab_check_addr " \
+ "usb_load_fit hab_check_file_fit; then " \
"run usbboot; " \
"fi; " \
- "if run usb_load_fitf hab_check_file_fit; then " \
+ "if run usb_load_pubkeyf hab_check_addr " \
+ "usb_load_fitf hab_check_file_fit; then " \
"run usbboot; " \
"fi; "\
- "if run usb_load_rescuefit hab_check_file_fit;" \
- "then run r_reason_syserr rescueboot;" \
+ "if run usb_rescue_load_pubkey hab_check_addr " \
+ "usb_load_rescuefit hab_check_file_fit; then " \
+ "run r_reason_syserr usbRargs; run rescueboot;" \
"fi; " \
- "if run usb_load_rescuefitf hab_check_file_fit;" \
- "then run r_reason_syserr rescueboot;" \
+ "if run usb_rescue_load_pubkeyf hab_check_addr " \
+ "usb_load_rescuefitf hab_check_file_fit; then " \
+ "run r_reason_syserr usbRargs; run rescueboot;" \
"fi; " \
"run mmc_rescue_boot;" \
"fi; "\
@@ -338,48 +339,57 @@
"if test ${bootmode} -ne 0 ; then " \
"mmc dev ${mmcdev};" \
"if mmc rescan; then " \
- "if run mmc_rescue_load_fit " \
- "hab_check_file_fit; then " \
- "run rescueboot; " \
+ "if run mmc_rescue_load_pubkey " \
+ "hab_check_addr " \
+ "mmc_rescue_load_fit " \
+ "hab_check_file_fit; then " \
+ "run mmcRargs; run rescueboot; " \
"else " \
"usb start;" \
"if usb storage; then " \
- "if run usb_load_rescuefit " \
- "hab_check_file_fit;"\
- "then " \
- "run rescueboot;" \
+ "if run usb_rescue_load_pubkey " \
+ "hab_check_addr " \
+ "usb_load_rescuefit " \
+ "hab_check_file_fit; then " \
+ "run usbRargs; run rescueboot;" \
"fi; " \
- "if run usb_load_rescuefitf "\
- "hab_check_file_fit;"\
- "then " \
- "run rescueboot;" \
+ "if run usb_rescue_load_pubkeyf " \
+ "hab_check_addr " \
+ "usb_load_rescuefitf " \
+ "hab_check_file_fit; then " \
+ "run usbRargs; run rescueboot;" \
"fi; " \
"fi;" \
"fi;" \
- "run dead; " \
"echo RESCUE SYSTEM ON SD OR " \
"USB BOOT FAILURE;" \
+ "run dead; " \
"else " \
"usb start;" \
"if usb storage; then " \
- "if run usb_load_rescuefit " \
- "hab_check_file_fit; then " \
- "run rescueboot;" \
+ "if run usb_rescue_load_pubkey " \
+ "hab_check_addr " \
+ "usb_load_rescuefit " \
+ "hab_check_file_fit; then " \
+ "run usbRargs; run rescueboot;" \
"fi; " \
- "if run usb_load_rescuefitf " \
- "hab_check_file_fit; then " \
- "run rescueboot;" \
+ "if run usb_rescue_load_pubkeyf " \
+ "hab_check_addr " \
+ "usb_load_rescuefitf " \
+ "hab_check_file_fit; then " \
+ "run usbRargs; run rescueboot;" \
"fi; " \
"fi;" \
- "run dead; " \
"echo RESCUE SYSTEM ON USB BOOT FAILURE;" \
+ "run dead; " \
"fi; " \
"else "\
- "if run rescue_load_fit hab_check_file_fit; then " \
- "run rescueboot; " \
+ "if run rescue_load_pubkey hab_check_addr " \
+ "rescue_load_fit hab_check_file_fit; then " \
+ "run mainRargs; run rescueboot; " \
"else " \
- "run dead; " \
"echo RESCUE SYSTEM ON BOARD BOOT FAILURE;" \
+ "run dead; " \
"fi; " \
"fi;\0" \
"ari_boot=if test ${bootmode} -ne 0 ; then " \
@@ -388,7 +398,8 @@
"if run loadbootscript hab_check_file_bootscript;" \
"then run bootscript; " \
"fi; " \
- "if run mmc_load_fit hab_check_file_fit; then " \
+ "if run mmc_load_pubkey hab_check_addr " \
+ "mmc_load_fit hab_check_file_fit; then " \
"if run mmcboot; then ; " \
"else " \
"run mmc_rescue_boot;" \
@@ -421,12 +432,6 @@
#define CONFIG_SYS_FSL_USDHC_NUM 2
-/* NAND stuff */
-#define CONFIG_SYS_MAX_NAND_DEVICE 1
-#define CONFIG_SYS_NAND_BASE 0x40000000
-#define CONFIG_SYS_NAND_5_ADDR_CYCLE
-#define CONFIG_SYS_NAND_ONFI_DETECTION
-
/* DMA stuff, needed for GPMI/MXS NAND support */
/* USB Configs */
@@ -444,4 +449,7 @@
#define CONFIG_IMX6_PWM_PER_CLK 66000000
+#define CONFIG_ENV_FLAGS_LIST_STATIC "ethaddr:mw,serial#:sw,board_type:sw," \
+ "sysnum:dw,panel:sw,ipaddr:iw,serverip:iw"
+
#endif /* __ARISTAINETOS2_CONFIG_H */
diff --git a/include/configs/cgtqmx6eval.h b/include/configs/cgtqmx6eval.h
index 2ef6bfd..bdd5973 100644
--- a/include/configs/cgtqmx6eval.h
+++ b/include/configs/cgtqmx6eval.h
@@ -35,7 +35,6 @@
#define CONFIG_SPI_FLASH_SST
/* Thermal support */
-#define CONFIG_IMX_THERMAL
/* I2C Configs */
#define CONFIG_SYS_I2C
diff --git a/include/configs/cl-som-imx7.h b/include/configs/cl-som-imx7.h
index 07f1893..0ef55b7 100644
--- a/include/configs/cl-som-imx7.h
+++ b/include/configs/cl-som-imx7.h
@@ -141,9 +141,6 @@
#define CONFIG_MXC_USB_FLAGS 0
#define CONFIG_USB_MAX_CONTROLLER_COUNT 2
-/* Uncomment to enable iMX thermal driver support */
-/*#define CONFIG_IMX_THERMAL*/
-
/* SPL */
#include "imx7_spl.h"
diff --git a/include/configs/colibri-imx6ull.h b/include/configs/colibri-imx6ull.h
index d373fda..2827c17 100644
--- a/include/configs/colibri-imx6ull.h
+++ b/include/configs/colibri-imx6ull.h
@@ -140,8 +140,6 @@
#define CONFIG_MXC_USB_FLAGS 0
#define CONFIG_USB_MAX_CONTROLLER_COUNT 2
-#define CONFIG_IMX_THERMAL
-
#define CONFIG_USBD_HS
/* USB Device Firmware Update support */
diff --git a/include/configs/colibri_imx7.h b/include/configs/colibri_imx7.h
index b3601ab..85dd891 100644
--- a/include/configs/colibri_imx7.h
+++ b/include/configs/colibri_imx7.h
@@ -208,8 +208,6 @@
#define CONFIG_MXC_USB_FLAGS 0
#define CONFIG_USB_MAX_CONTROLLER_COUNT 2
-#define CONFIG_IMX_THERMAL
-
#define CONFIG_USBD_HS
#if defined(CONFIG_VIDEO) || defined(CONFIG_DM_VIDEO)
diff --git a/include/configs/dart_6ul.h b/include/configs/dart_6ul.h
index b27f715..4eb50f8 100644
--- a/include/configs/dart_6ul.h
+++ b/include/configs/dart_6ul.h
@@ -84,8 +84,6 @@
#define CONFIG_MXC_USB_FLAGS 0
#define CONFIG_USB_MAX_CONTROLLER_COUNT 2
-#define CONFIG_IMX_THERMAL
-
#define ENV_MMC \
"mmcdev=" __stringify(MMC_ROOTFS_DEV) "\0" \
"mmcpart=" __stringify(MMC_ROOTFS_PART) "\0" \
diff --git a/include/configs/el6x_common.h b/include/configs/el6x_common.h
index bd61f20..9ee7fee 100644
--- a/include/configs/el6x_common.h
+++ b/include/configs/el6x_common.h
@@ -14,8 +14,6 @@
#include "mx6_common.h"
-#define CONFIG_IMX_THERMAL
-
/* Size of malloc() pool */
#define CONFIG_SYS_MALLOC_LEN (10 * SZ_1M)
diff --git a/include/configs/embestmx6boards.h b/include/configs/embestmx6boards.h
index b18db76..ff3a849 100644
--- a/include/configs/embestmx6boards.h
+++ b/include/configs/embestmx6boards.h
@@ -17,8 +17,6 @@
#define PHYS_SDRAM_SIZE (1u * 1024 * 1024 * 1024)
-#define CONFIG_IMX_THERMAL
-
/* Size of malloc() pool */
#define CONFIG_SYS_MALLOC_LEN (10 * SZ_1M)
diff --git a/include/configs/ge_bx50v3.h b/include/configs/ge_bx50v3.h
index 4fdc2b6..e5c580b 100644
--- a/include/configs/ge_bx50v3.h
+++ b/include/configs/ge_bx50v3.h
@@ -48,7 +48,7 @@
#define CONFIG_LOADADDR 0x12000000
-#ifdef CONFIG_NFS_CMD
+#ifdef CONFIG_CMD_NFS
#define NETWORKBOOT \
"setnetworkboot=" \
"setenv ipaddr 172.16.2.10; setenv serverip 172.16.2.20; " \
@@ -56,7 +56,7 @@
"setenv netmask 255.255.255.0; setenv ethaddr ca:fe:de:ca:f0:11; " \
"setenv bootargs root=/dev/nfs nfsroot=${nfsserver}:/srv/nfs/,v3,tcp rw rootwait" \
"setenv bootargs $bootargs ip=${ipaddr}:${nfsserver}:${gatewayip}:${netmask}::eth0:off " \
- "setenv bootargs $bootargs cma=128M bootcause=POR ${videoargs} " \
+ "setenv bootargs $bootargs cma=128M bootcause=${bootcause} ${videoargs} " \
"setenv bootargs $bootargs systemd.mask=helix-network-defaults.service " \
"setenv bootargs $bootargs watchdog.handle_boot_enabled=1\0" \
"networkboot=" \
@@ -74,7 +74,6 @@
#define CONFIG_EXTRA_ENV_SETTINGS \
NETWORKBOOT \
- "bootcause=POR\0" \
"image=/boot/fitImage\0" \
"dev=mmc\0" \
"devnum=2\0" \
@@ -104,7 +103,6 @@
"setenv partnum 1; run hasfirstboot || setenv partnum 2; " \
"run hasfirstboot || setenv partnum 0; " \
"if test ${partnum} != 0; then " \
- "setenv bootcause REVERT; " \
"run swappartitions loadimage doboot; " \
"fi; " \
"run failbootcmd\0" \
@@ -130,7 +128,7 @@
#define CONFIG_USBBOOTCOMMAND \
"echo Unsupported; " \
-#ifdef CONFIG_NFS_CMD
+#ifdef CONFIG_CMD_NFS
#define CONFIG_BOOTCOMMAND CONFIG_NETWORKBOOTCOMMAND
#elif CONFIG_CMD_USB
#define CONFIG_BOOTCOMMAND CONFIG_USBBOOTCOMMAND
diff --git a/include/configs/gw_ventana.h b/include/configs/gw_ventana.h
index a92157d..7c8abda 100644
--- a/include/configs/gw_ventana.h
+++ b/include/configs/gw_ventana.h
@@ -32,16 +32,6 @@
/* Size of malloc() pool */
#define CONFIG_SYS_MALLOC_LEN (10 * SZ_1M)
-/* Init Functions */
-
-/* Driver Model */
-#ifndef CONFIG_SPL_BUILD
-#define CONFIG_DM_THERMAL
-#endif
-
-/* Thermal */
-#define CONFIG_IMX_THERMAL
-
/* Serial */
#define CONFIG_MXC_UART_BASE UART2_BASE
diff --git a/include/configs/liteboard.h b/include/configs/liteboard.h
index db5e6fc..5adbe1c 100644
--- a/include/configs/liteboard.h
+++ b/include/configs/liteboard.h
@@ -141,6 +141,4 @@
#define CONFIG_ETHPRIME "FEC"
#endif
-#define CONFIG_IMX_THERMAL
-
#endif
diff --git a/include/configs/mx6cuboxi.h b/include/configs/mx6cuboxi.h
index cfab9a7..55717c7 100644
--- a/include/configs/mx6cuboxi.h
+++ b/include/configs/mx6cuboxi.h
@@ -13,8 +13,6 @@
#include "imx6_spl.h"
-#define CONFIG_IMX_THERMAL
-
#define CONFIG_SYS_MALLOC_LEN (10 * SZ_1M)
/* MMC Configs */
diff --git a/include/configs/mx6sabre_common.h b/include/configs/mx6sabre_common.h
index c4e34e9..93d00a4 100644
--- a/include/configs/mx6sabre_common.h
+++ b/include/configs/mx6sabre_common.h
@@ -12,8 +12,6 @@
#include "mx6_common.h"
-#define CONFIG_IMX_THERMAL
-
/* Size of malloc() pool */
#define CONFIG_SYS_MALLOC_LEN (10 * SZ_1M)
diff --git a/include/configs/mx6slevk.h b/include/configs/mx6slevk.h
index 44dadd6..ab32f4e 100644
--- a/include/configs/mx6slevk.h
+++ b/include/configs/mx6slevk.h
@@ -132,6 +132,4 @@
#define CONFIG_SYS_FSL_USDHC_NUM 3
-#define CONFIG_IMX_THERMAL
-
#endif /* __CONFIG_H */
diff --git a/include/configs/mx6sllevk.h b/include/configs/mx6sllevk.h
index 9533d30..a38ce4d 100644
--- a/include/configs/mx6sllevk.h
+++ b/include/configs/mx6sllevk.h
@@ -123,8 +123,6 @@
#define CONFIG_SYS_FSL_ESDHC_ADDR USDHC1_BASE_ADDR
#define CONFIG_SYS_FSL_USDHC_NUM 3
-#define CONFIG_IMX_THERMAL
-
#define CONFIG_IOMUX_LPSR
/* USB Configs */
diff --git a/include/configs/mx6sxsabreauto.h b/include/configs/mx6sxsabreauto.h
index 9ad2934..58cc3f0 100644
--- a/include/configs/mx6sxsabreauto.h
+++ b/include/configs/mx6sxsabreauto.h
@@ -138,8 +138,6 @@
#define CONFIG_USB_MAX_CONTROLLER_COUNT 2
#endif
-#define CONFIG_IMX_THERMAL
-
#define CONFIG_SYS_FSL_USDHC_NUM 2
#endif /* __CONFIG_H */
diff --git a/include/configs/mx6sxsabresd.h b/include/configs/mx6sxsabresd.h
index 42feb14..036881f 100644
--- a/include/configs/mx6sxsabresd.h
+++ b/include/configs/mx6sxsabresd.h
@@ -170,8 +170,6 @@
#define CONFIG_PCIE_IMX_POWER_GPIO IMX_GPIO_NR(2, 1)
#endif
-#define CONFIG_IMX_THERMAL
-
#ifndef CONFIG_SPL_BUILD
#ifdef CONFIG_VIDEO
#define CONFIG_VIDEO_MXS
diff --git a/include/configs/mx6ul_14x14_evk.h b/include/configs/mx6ul_14x14_evk.h
index fa6b303..7d36c1e 100644
--- a/include/configs/mx6ul_14x14_evk.h
+++ b/include/configs/mx6ul_14x14_evk.h
@@ -177,8 +177,6 @@
#endif
#endif
-#define CONFIG_IMX_THERMAL
-
#ifndef CONFIG_SPL_BUILD
#if defined(CONFIG_DM_VIDEO)
#define CONFIG_VIDEO_MXS
diff --git a/include/configs/mx6ullevk.h b/include/configs/mx6ullevk.h
index ca2f2bd..23f6de9 100644
--- a/include/configs/mx6ullevk.h
+++ b/include/configs/mx6ullevk.h
@@ -150,8 +150,6 @@
/* environment organization */
#define CONFIG_MMCROOT "/dev/mmcblk1p2" /* USDHC2 */
-#define CONFIG_IMX_THERMAL
-
#define CONFIG_IOMUX_LPSR
#define CONFIG_SOFT_SPI
diff --git a/include/configs/mx7dsabresd.h b/include/configs/mx7dsabresd.h
index 51a7a5f..5801da0 100644
--- a/include/configs/mx7dsabresd.h
+++ b/include/configs/mx7dsabresd.h
@@ -134,8 +134,6 @@
/* USB Configs */
#define CONFIG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW)
-#define CONFIG_IMX_THERMAL
-
#define CONFIG_USBD_HS
#ifdef CONFIG_VIDEO
diff --git a/include/configs/mys_6ulx.h b/include/configs/mys_6ulx.h
index 2087799..5ef16fb 100644
--- a/include/configs/mys_6ulx.h
+++ b/include/configs/mys_6ulx.h
@@ -50,8 +50,6 @@
#define CONFIG_MXC_USB_FLAGS 0
#define CONFIG_USB_MAX_CONTROLLER_COUNT 1
-#define CONFIG_IMX_THERMAL
-
#define CONFIG_EXTRA_ENV_SETTINGS \
"console=ttymxc0,115200n8\0" \
"mtdids=" CONFIG_MTDIDS_DEFAULT "\0" \
diff --git a/include/configs/ot1200.h b/include/configs/ot1200.h
index bf8f7b1..ea61f92 100644
--- a/include/configs/ot1200.h
+++ b/include/configs/ot1200.h
@@ -74,9 +74,6 @@
#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 5
#endif
-/* Thermal support */
-#define CONFIG_IMX_THERMAL
-
/* Physical Memory Map */
#define PHYS_SDRAM MMDC0_ARB_BASE_ADDR
diff --git a/include/configs/pcl063.h b/include/configs/pcl063.h
index 2156da6..4f4d501 100644
--- a/include/configs/pcl063.h
+++ b/include/configs/pcl063.h
@@ -62,8 +62,6 @@
#define CONFIG_MXC_USB_FLAGS 0
#define CONFIG_USB_MAX_CONTROLLER_COUNT 1
-#define CONFIG_IMX_THERMAL
-
#define CONFIG_EXTRA_ENV_SETTINGS \
"console=ttymxc0,115200n8\0" \
"mtdids=" CONFIG_MTDIDS_DEFAULT "\0" \
diff --git a/include/configs/pcl063_ull.h b/include/configs/pcl063_ull.h
index d7c6f88..6009521 100644
--- a/include/configs/pcl063_ull.h
+++ b/include/configs/pcl063_ull.h
@@ -69,8 +69,6 @@
#define CONFIG_MXC_USB_FLAGS 0
#define CONFIG_USB_MAX_CONTROLLER_COUNT 1
-#define CONFIG_IMX_THERMAL
-
#define ENV_MMC \
"mmcdev=" __stringify(MMC_ROOTFS_DEV) "\0" \
"mmcpart=" __stringify(MMC_ROOTFS_PART) "\0" \
diff --git a/include/configs/pfla02.h b/include/configs/pfla02.h
index 3227c42..e964290 100644
--- a/include/configs/pfla02.h
+++ b/include/configs/pfla02.h
@@ -13,9 +13,6 @@
#include "mx6_common.h"
-/* Thermal */
-#define CONFIG_IMX_THERMAL
-
/* Serial */
#define CONFIG_MXC_UART_BASE UART4_BASE
#define CONSOLE_DEV "ttymxc3"
diff --git a/include/configs/pico-imx7d.h b/include/configs/pico-imx7d.h
index 51b7359..80de115 100644
--- a/include/configs/pico-imx7d.h
+++ b/include/configs/pico-imx7d.h
@@ -168,6 +168,4 @@
#define CONFIG_MXC_USB_FLAGS 0
#define CONFIG_USB_MAX_CONTROLLER_COUNT 2
-#define CONFIG_IMX_THERMAL
-
#endif
diff --git a/include/configs/sksimx6.h b/include/configs/sksimx6.h
index 511b1a4..7052d80 100644
--- a/include/configs/sksimx6.h
+++ b/include/configs/sksimx6.h
@@ -10,9 +10,6 @@
#include "mx6_common.h"
#include "imx6_spl.h"
-/* Thermal */
-#define CONFIG_IMX_THERMAL
-
/* Serial */
#define CONFIG_MXC_UART_BASE UART1_BASE
diff --git a/include/configs/somlabs_visionsom_6ull.h b/include/configs/somlabs_visionsom_6ull.h
index 204818b..945d0ec 100644
--- a/include/configs/somlabs_visionsom_6ull.h
+++ b/include/configs/somlabs_visionsom_6ull.h
@@ -104,6 +104,4 @@
#define CONFIG_ETHPRIME "eth0"
#endif
-#define CONFIG_IMX_THERMAL
-
#endif
diff --git a/include/configs/tbs2910.h b/include/configs/tbs2910.h
index 01c1143e..a2e59ce 100644
--- a/include/configs/tbs2910.h
+++ b/include/configs/tbs2910.h
@@ -16,8 +16,6 @@
#define CONFIG_SYS_HZ 1000
-#define CONFIG_IMX_THERMAL
-
/* Physical Memory Map */
#define CONFIG_SYS_SDRAM_BASE MMDC0_ARB_BASE_ADDR
diff --git a/include/configs/udoo_neo.h b/include/configs/udoo_neo.h
index 34a95a0..4935a2b 100644
--- a/include/configs/udoo_neo.h
+++ b/include/configs/udoo_neo.h
@@ -70,10 +70,6 @@
#define CONFIG_SYS_INIT_SP_ADDR \
(CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET)
-/* Environment organization */
-
-#define CONFIG_IMX_THERMAL
-
/* I2C configs */
#define CONFIG_SYS_I2C
#define CONFIG_SYS_I2C_MXC
diff --git a/include/configs/vining_2000.h b/include/configs/vining_2000.h
index a851fb4..f97431f 100644
--- a/include/configs/vining_2000.h
+++ b/include/configs/vining_2000.h
@@ -73,8 +73,6 @@
#define CONFIG_PCIE_IMX_PERST_GPIO IMX_GPIO_NR(4, 6)
#endif
-#define CONFIG_IMX_THERMAL
-
#define CONFIG_IMX6_PWM_PER_CLK 66000000
#ifdef CONFIG_ENV_IS_IN_MMC
diff --git a/include/configs/warp7.h b/include/configs/warp7.h
index 2d1ede3..8eb1060 100644
--- a/include/configs/warp7.h
+++ b/include/configs/warp7.h
@@ -146,8 +146,6 @@
#define CONFIG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW)
-#define CONFIG_IMX_THERMAL
-
#define CONFIG_USBD_HS
/* USB Device Firmware Update support */
diff --git a/include/configs/xpress.h b/include/configs/xpress.h
index 399925a..e7a2658 100644
--- a/include/configs/xpress.h
+++ b/include/configs/xpress.h
@@ -63,8 +63,6 @@
#define CONFIG_FEC_XCV_TYPE RMII
#define CONFIG_ETHPRIME "FEC"
-#define CONFIG_IMX_THERMAL
-
#define CONFIG_SYS_MMC_IMG_LOAD_PART 1
#define CONFIG_UBOOT_SECTOR_START 0x2