commit a33070c617711e0f93c03aaabc1477e009759475
author Zong Li <zong.li@sifive.com> Wed Sep 01 15:01:40 2021 +0800
committer Leo Yu-Chi Liang <ycliang@andestech.com> Tue Sep 07 10:34:29 2021 +0800
tree d231a09a9223c329f6b3dde902a43695e2c96e26
parent feea3fb998331a425fd561eeb79601f97c1a2ea1

common: board_r: support enable_caches for RISC-V

The enable_caches is a generic hook for architecture-implemented, we
leverage this function to enable caches for RISC-V

Signed-off-by: Zong Li <zong.li@sifive.com>
Reviewed-by: Rick Chen <rick@andestech.com>

arch/riscv/lib/cache.c

diff --git a/arch/riscv/lib/cache.c b/arch/riscv/lib/cache.c
index b1d42bc..686e699 100644
--- a/arch/riscv/lib/cache.c
+++ b/arch/riscv/lib/cache.c
@@ -70,3 +70,7 @@
 {
 	return 0;
 }
+
+__weak void enable_caches(void)
+{
+}