tree 7798b7d37cc280700f40ffd4464ac176f67f62ab
parent 1a2fcc25b713148c6bc58d7f79bae5c3393896b5
author Simon Glass <sjg@chromium.org> 1695178807 -0600
committer Bin Meng <bmeng@tinylab.org> 1695333826 +0800

x86: coreboot: Look for DBG2 UART in SPL too

If coreboot does not set up sysinfo for the UART, SPL currently hangs.
Use the DBG2 technique there as well. This allows coreboot64 to boot from
coreboot even if the console info is missing from sysinfo

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>