commit a2ee226911e969f2f6539c9ffe20b9648efadbd2
author Simon Glass <sjg@chromium.org> Tue Sep 19 21:00:07 2023 -0600
committer Bin Meng <bmeng@tinylab.org> Fri Sep 22 06:03:46 2023 +0800
tree 7798b7d37cc280700f40ffd4464ac176f67f62ab
parent 1a2fcc25b713148c6bc58d7f79bae5c3393896b5

x86: coreboot: Look for DBG2 UART in SPL too

If coreboot does not set up sysinfo for the UART, SPL currently hangs.
Use the DBG2 technique there as well. This allows coreboot64 to boot from
coreboot even if the console info is missing from sysinfo

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>

configs/coreboot64_defconfig

diff --git a/configs/coreboot64_defconfig b/configs/coreboot64_defconfig
index 5623197..e816596 100644
--- a/configs/coreboot64_defconfig
+++ b/configs/coreboot64_defconfig
@@ -54,4 +54,5 @@
 CONFIG_SOUND=y
 CONFIG_SOUND_I8254=y
 CONFIG_CONSOLE_SCROLL_LINES=5
+CONFIG_SPL_ACPI=y
 # CONFIG_GZIP is not set