| commit | 5872fc6b43779f54756f2224fe771f140d00fe4b | [log] [tgz] |
|---|---|---|
| author | Eugeniy Paltsev <Eugeniy.Paltsev@synopsys.com> | Wed Jan 29 14:08:30 2020 +0300 |
| committer | Alexey Brodkin <abrodkin@synopsys.com> | Wed Feb 12 20:47:39 2020 +0300 |
| tree | 0908b429e67d6bdd3e5732b64a2be9e82b1de37a | |
| parent | 9d70c9c7a9bf21bc2f00fe8c9a7298826bea1cf9 [diff] |
CLK: HSDK: fix HDMI clock calculation HDMI PLL has its own xtal with 27 MHz output but we treat it the same way as other PLLs with 33.33 MHz input. Fix that. Signed-off-by: Eugeniy Paltsev <Eugeniy.Paltsev@synopsys.com> Signed-off-by: Alexey Brodkin <abrodkin@synopsys.com>